From 5dc5a8e973b66e6a1a1e7ea61c3c781218915a27 Mon Sep 17 00:00:00 2001 From: Steve Evans Date: Mon, 16 Dec 2024 19:55:23 +0000 Subject: [PATCH 001/244] Adjust info/warning status (#14088) --- src/main/osd/osd_elements.c | 3 ++- src/main/osd/osd_warnings.c | 4 ++-- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/src/main/osd/osd_elements.c b/src/main/osd/osd_elements.c index b19b5a9eae..51e43cff53 100644 --- a/src/main/osd/osd_elements.c +++ b/src/main/osd/osd_elements.c @@ -887,6 +887,7 @@ static void osdElementCrashFlipArrow(osdElementParms_t *element) } if ((isCrashFlipModeActive() || (!ARMING_FLAG(ARMED) && !isUpright())) && !((imuConfig()->small_angle < 180 && isUpright()) || (rollAngle == 0 && pitchAngle == 0))) { + element->attr = DISPLAYPORT_SEVERITY_INFO; if (abs(pitchAngle) < 2 * abs(rollAngle) && abs(rollAngle) < 2 * abs(pitchAngle)) { if (pitchAngle > 0) { if (rollAngle > 0) { @@ -1167,7 +1168,7 @@ static void osdElementGpsSats(osdElementParms_t *element) } #endif else { - element->attr = DISPLAYPORT_SEVERITY_INFO; + element->attr = DISPLAYPORT_SEVERITY_NORMAL; } if (!gpsIsHealthy()) { diff --git a/src/main/osd/osd_warnings.c b/src/main/osd/osd_warnings.c index 019fd117cb..bf6b8e1c07 100644 --- a/src/main/osd/osd_warnings.c +++ b/src/main/osd/osd_warnings.c @@ -139,7 +139,7 @@ void renderOsdWarning(char *warningText, bool *blinking, uint8_t *displayAttr) if (osdWarnGetState(OSD_WARNING_CRASHFLIP) && IS_RC_MODE_ACTIVE(BOXCRASHFLIP)) { if (isCrashFlipModeActive()) { // if was armed in crashflip mode tfp_sprintf(warningText, CRASHFLIP_WARNING); - *displayAttr = DISPLAYPORT_SEVERITY_INFO; + *displayAttr = DISPLAYPORT_SEVERITY_WARNING; return; } else if (!ARMING_FLAG(ARMED)) { // if disarmed, but crashflip mode is activated (not allowed / can't happen) tfp_sprintf(warningText, "CRASHFLIP SW"); @@ -420,7 +420,7 @@ void renderOsdWarning(char *warningText, bool *blinking, uint8_t *displayAttr) if (osdWarnGetState(OSD_WARNING_BATTERY_NOT_FULL) && !(ARMING_FLAG(ARMED) || ARMING_FLAG(WAS_EVER_ARMED)) && (getBatteryState() == BATTERY_OK) && getBatteryAverageCellVoltage() < batteryConfig()->vbatfullcellvoltage) { tfp_sprintf(warningText, "BATT < FULL"); - *displayAttr = DISPLAYPORT_SEVERITY_INFO; + *displayAttr = DISPLAYPORT_SEVERITY_WARNING; return; } From b89022019773050989ba83a9ef6b0b26a221b40c Mon Sep 17 00:00:00 2001 From: Steve Evans Date: Wed, 18 Dec 2024 22:37:18 +0000 Subject: [PATCH 002/244] Don't handle non-MSP characters on VTX MSP port (#14091) * Don't handle non-MSP characters on VTX MSP port * Remove check for CLI active on VTX MSP port as it can no longer be enabled * Only include check for MSP display port if USE_MSP_DISPLAYPORT is defined --- src/main/io/displayport_msp.c | 10 ++++------ src/main/io/displayport_msp.h | 1 + src/main/msp/msp_serial.c | 8 +++++++- 3 files changed, 12 insertions(+), 7 deletions(-) diff --git a/src/main/io/displayport_msp.c b/src/main/io/displayport_msp.c index 52dff222f4..3e7ea38890 100644 --- a/src/main/io/displayport_msp.c +++ b/src/main/io/displayport_msp.c @@ -51,12 +51,6 @@ static int output(displayPort_t *displayPort, uint8_t cmd, uint8_t *buf, int len { UNUSED(displayPort); -#ifdef USE_CLI - // FIXME There should be no dependency on the CLI but mspSerialPush doesn't check for cli mode, and can't because it also shouldn't have a dependency on the CLI. - if (cliMode) { - return 0; - } -#endif return mspSerialPush(displayPortSerial, cmd, buf, len, MSP_DIRECTION_REPLY, MSP_V1); } @@ -229,4 +223,8 @@ displayPort_t *displayPortMspInit(void) void displayPortMspSetSerial(serialPortIdentifier_e serialPort) { displayPortSerial = serialPort; } + +serialPortIdentifier_e displayPortMspGetSerial(void) { + return displayPortSerial; +} #endif // USE_MSP_DISPLAYPORT diff --git a/src/main/io/displayport_msp.h b/src/main/io/displayport_msp.h index 2d89616ad8..25f624bb08 100644 --- a/src/main/io/displayport_msp.h +++ b/src/main/io/displayport_msp.h @@ -46,4 +46,5 @@ typedef enum { struct displayPort_s *displayPortMspInit(void); void displayPortMspSetSerial(serialPortIdentifier_e serialPort); +serialPortIdentifier_e displayPortMspGetSerial(void); diff --git a/src/main/msp/msp_serial.c b/src/main/msp/msp_serial.c index 31f5ba07c4..00601c56b9 100644 --- a/src/main/msp/msp_serial.c +++ b/src/main/msp/msp_serial.c @@ -459,6 +459,7 @@ static void mspProcessPendingRequest(mspPort_t * mspPort) case MSP_PENDING_CLI: mspPort->pendingRequest = MSP_PENDING_NONE; mspPort->portState = PORT_CLI_ACTIVE; + cliEnter(mspPort->port, true); break; #endif @@ -537,7 +538,12 @@ void mspSerialProcess(mspEvaluateNonMspData_e evaluateNonMspData, mspProcessComm if (c == '$') { mspPort->portState = PORT_MSP_PACKET; mspPort->packetState = MSP_HEADER_START; - } else if (evaluateNonMspData == MSP_EVALUATE_NON_MSP_DATA) { + } else if ((evaluateNonMspData == MSP_EVALUATE_NON_MSP_DATA) +#ifdef USE_MSP_DISPLAYPORT + // Don't evaluate non-MSP commands on VTX MSP port + && (mspPort->port->identifier != displayPortMspGetSerial()) +#endif + ) { // evaluate the non-MSP data if (c == serialConfig()->reboot_character) { mspPort->pendingRequest = MSP_PENDING_BOOTLOADER_ROM; From f27da4ed8de344bc733b7bc648a6f5d120e55fa7 Mon Sep 17 00:00:00 2001 From: nerdCopter <56646290+nerdCopter@users.noreply.github.com> Date: Fri, 20 Dec 2024 00:15:41 -0600 Subject: [PATCH 003/244] ./src/utils/ trim trailing whitestpaces (#14082) --- src/main/msp/msp_build_info.c | 2 +- src/utils/dfuse-pack.py | 2 +- src/utils/make-build-info.py | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/main/msp/msp_build_info.c b/src/main/msp/msp_build_info.c index d54d6f4859..744829f35f 100644 --- a/src/main/msp/msp_build_info.c +++ b/src/main/msp/msp_build_info.c @@ -35,7 +35,7 @@ #include "msp/msp_build_info.h" -void sbufWriteBuildInfoFlags(sbuf_t *dst) +void sbufWriteBuildInfoFlags(sbuf_t *dst) { static const uint16_t options[] = { #ifdef USE_SERIALRX_CRSF diff --git a/src/utils/dfuse-pack.py b/src/utils/dfuse-pack.py index 9749aa4166..a34c65c6b0 100755 --- a/src/utils/dfuse-pack.py +++ b/src/utils/dfuse-pack.py @@ -3,7 +3,7 @@ # Written by Antonio Galea - 2010/11/18 # Distributed under Gnu LGPL 3.0 # see http://www.gnu.org/licenses/lgpl-3.0.txt -# +# # based on a modified version of this script from https://sourceforge.net/p/dfu-util/tickets/35/#357c # with the patch supplied in https://sourceforge.net/p/dfu-util/tickets/35/#a2b6 diff --git a/src/utils/make-build-info.py b/src/utils/make-build-info.py index fcb468b124..92ebb751dc 100755 --- a/src/utils/make-build-info.py +++ b/src/utils/make-build-info.py @@ -33,7 +33,7 @@ SOURCE_FILE_TEMPLATE = """{license_header} #include "msp/msp_build_info.h" -void sbufWriteBuildInfoFlags(sbuf_t *dst) +void sbufWriteBuildInfoFlags(sbuf_t *dst) { static const uint16_t options[] = { {build_options} From 7dec49ce425f7a772d5ba334cd115f46880a0db8 Mon Sep 17 00:00:00 2001 From: Jay Blackman Date: Sat, 21 Dec 2024 01:22:22 +1100 Subject: [PATCH 004/244] Corrected missed USE_ACC logic and some minor cleanup (#14093) --- src/main/common/maths.h | 6 ++++++ src/main/flight/pid.c | 2 +- src/main/flight/pid_init.c | 5 ++++- src/main/rx/cc2500_frsky_x.c | 1 - src/main/rx/cc2500_redpine.c | 1 - src/main/rx/rc_stats.c | 2 +- src/platform/SIMULATOR/sitl.c | 1 + 7 files changed, 13 insertions(+), 5 deletions(-) diff --git a/src/main/common/maths.h b/src/main/common/maths.h index e0345fdf49..e097d98c9a 100644 --- a/src/main/common/maths.h +++ b/src/main/common/maths.h @@ -46,14 +46,20 @@ #define CM_S_TO_KM_H(centimetersPerSecond) ((centimetersPerSecond) * 36 / 1000) #define CM_S_TO_MPH(centimetersPerSecond) ((centimetersPerSecond) * 10000 / 5080 / 88) +#ifndef MIN #define MIN(a,b) \ __extension__ ({ __typeof__ (a) _a = (a); \ __typeof__ (b) _b = (b); \ _a < _b ? _a : _b; }) +#endif + +#ifndef MAX #define MAX(a,b) \ __extension__ ({ __typeof__ (a) _a = (a); \ __typeof__ (b) _b = (b); \ _a > _b ? _a : _b; }) +#endif + #define ABS(x) \ __extension__ ({ __typeof__ (x) _x = (x); \ _x > 0 ? _x : -_x; }) diff --git a/src/main/flight/pid.c b/src/main/flight/pid.c index 413567e4db..094ff0aea4 100644 --- a/src/main/flight/pid.c +++ b/src/main/flight/pid.c @@ -1328,7 +1328,7 @@ void FAST_CODE pidController(const pidProfile_t *pidProfile, timeUs_t currentTim float pidSetpointDelta = 0; -#ifdef USE_FEEDFORWARD +#if defined(USE_FEEDFORWARD) && defined(USE_ACC) if (FLIGHT_MODE(ANGLE_MODE) && pidRuntime.axisInAngleMode[axis]) { // this axis is fully under self-levelling control // it will already have stick based feedforward applied in the input to their angle setpoint diff --git a/src/main/flight/pid_init.c b/src/main/flight/pid_init.c index d6596300ca..e8ab4ab91f 100644 --- a/src/main/flight/pid_init.c +++ b/src/main/flight/pid_init.c @@ -397,8 +397,9 @@ void pidInitConfig(const pidProfile_t *pidProfile) } pidRuntime.angleGain = pidProfile->pid[PID_LEVEL].P / 10.0f; pidRuntime.angleFeedforwardGain = pidProfile->pid[PID_LEVEL].F / 100.0f; +#ifdef USE_ACC pidRuntime.angleEarthRef = pidProfile->angle_earth_ref / 100.0f; - +#endif pidRuntime.horizonGain = MIN(pidProfile->pid[PID_LEVEL].I / 100.0f, 1.0f); pidRuntime.horizonIgnoreSticks = (pidProfile->horizon_ignore_sticks) ? 1.0f : 0.0f; @@ -406,7 +407,9 @@ void pidInitConfig(const pidProfile_t *pidProfile) pidRuntime.horizonLimitSticksInv = (pidProfile->pid[PID_LEVEL].D) ? 1.0f / pidRuntime.horizonLimitSticks : 1.0f; pidRuntime.horizonLimitDegrees = (float)pidProfile->horizon_limit_degrees; pidRuntime.horizonLimitDegreesInv = (pidProfile->horizon_limit_degrees) ? 1.0f / pidRuntime.horizonLimitDegrees : 1.0f; +#ifdef USE_ACC pidRuntime.horizonDelayMs = pidProfile->horizon_delay_ms; +#endif pidRuntime.maxVelocity[FD_ROLL] = pidRuntime.maxVelocity[FD_PITCH] = pidProfile->rateAccelLimit * 100 * pidRuntime.dT; pidRuntime.maxVelocity[FD_YAW] = pidProfile->yawRateAccelLimit * 100 * pidRuntime.dT; diff --git a/src/main/rx/cc2500_frsky_x.c b/src/main/rx/cc2500_frsky_x.c index 45bdc18966..133a10ea81 100644 --- a/src/main/rx/cc2500_frsky_x.c +++ b/src/main/rx/cc2500_frsky_x.c @@ -34,7 +34,6 @@ #include "drivers/adc.h" #include "drivers/io.h" -#include "drivers/io_def.h" #include "drivers/io_types.h" #include "drivers/resource.h" #include "drivers/rx/rx_cc2500.h" diff --git a/src/main/rx/cc2500_redpine.c b/src/main/rx/cc2500_redpine.c index 66baa829bf..7d96f338ea 100644 --- a/src/main/rx/cc2500_redpine.c +++ b/src/main/rx/cc2500_redpine.c @@ -34,7 +34,6 @@ #include "config/feature.h" #include "drivers/adc.h" #include "drivers/io.h" -#include "drivers/io_def.h" #include "drivers/io_types.h" #include "drivers/resource.h" #include "drivers/rx/rx_cc2500.h" diff --git a/src/main/rx/rc_stats.c b/src/main/rx/rc_stats.c index b415e1d698..bf0ecf415f 100644 --- a/src/main/rx/rc_stats.c +++ b/src/main/rx/rc_stats.c @@ -83,7 +83,7 @@ timeUs_t RcStatsGetFullThrottleTimeUs(void) int8_t RcStatsGetAverageThrottle(void) { - return (float)totalTrottleNumber/(float)counter + 0.5; // rounding + return (float)totalTrottleNumber/(float)counter + 0.5f; // rounding } void NotifyRcStatsArming(void) diff --git a/src/platform/SIMULATOR/sitl.c b/src/platform/SIMULATOR/sitl.c index 73abf4a9c6..f53482f8f6 100644 --- a/src/platform/SIMULATOR/sitl.c +++ b/src/platform/SIMULATOR/sitl.c @@ -445,6 +445,7 @@ uint32_t clockMicrosToCycles(uint32_t micros) { return micros; } + uint32_t getCycleCounter(void) { return (uint32_t) (micros64() & 0xFFFFFFFF); From 2f21754a6985d9eecacec273beaa4f20750958e6 Mon Sep 17 00:00:00 2001 From: Petr Ledvina Date: Fri, 20 Dec 2024 19:01:00 +0100 Subject: [PATCH 005/244] Improve serial_post.h (#14096) --- src/main/drivers/serial_softserial.c | 4 +- src/main/drivers/serial_uart.c | 2 +- src/main/io/serial.h | 15 +++++-- src/main/io/serial_resource.c | 21 +++++---- src/main/target/serial_post.h | 66 ++++++++++++++++++++++++---- src/utils/gen-serial-j2.py | 6 ++- src/utils/templates/serial_post.h | 43 +++++++++++++----- 7 files changed, 120 insertions(+), 37 deletions(-) diff --git a/src/main/drivers/serial_softserial.c b/src/main/drivers/serial_softserial.c index 010c1ee1e7..dbaf5d75e6 100644 --- a/src/main/drivers/serial_softserial.c +++ b/src/main/drivers/serial_softserial.c @@ -197,8 +197,8 @@ static void resetBuffers(softSerial_t *softSerial) softSerial_t* softSerialFromIdentifier(serialPortIdentifier_e identifier) { - if (identifier >= SERIAL_PORT_SOFTSERIAL1 && identifier < SERIAL_PORT_SOFTSERIAL1 + SERIAL_SOFTSERIAL_COUNT) { - return &softSerialPorts[identifier - SERIAL_PORT_SOFTSERIAL1]; + if (identifier >= SERIAL_PORT_SOFTSERIAL_FIRST && identifier < SERIAL_PORT_SOFTSERIAL_FIRST + SERIAL_SOFTSERIAL_COUNT) { + return &softSerialPorts[identifier - SERIAL_PORT_SOFTSERIAL_FIRST]; } return NULL; } diff --git a/src/main/drivers/serial_uart.c b/src/main/drivers/serial_uart.c index 42c7846932..24bfb66c8a 100644 --- a/src/main/drivers/serial_uart.c +++ b/src/main/drivers/serial_uart.c @@ -174,7 +174,7 @@ uartDeviceIdx_e uartDeviceIdxFromIdentifier(serialPortIdentifier_e identifier) } #else { - const int idx = identifier - SERIAL_PORT_USART1; + const int idx = identifier - SERIAL_PORT_UART_FIRST; if (idx >= 0 && idx < SERIAL_UART_MAX) { if (BIT(idx) & SERIAL_UART_MASK) { // return number of enabled UART ports smaller than idx diff --git a/src/main/io/serial.h b/src/main/io/serial.h index 9d2a3ce667..af10830fa2 100644 --- a/src/main/io/serial.h +++ b/src/main/io/serial.h @@ -83,7 +83,14 @@ extern const uint32_t baudRates[]; typedef enum { SERIAL_PORT_ALL = -2, SERIAL_PORT_NONE = -1, - SERIAL_PORT_USART1 = 0, + // prepare for transition to SERIAL_PORT_UART0 + SERIAL_PORT_UART_FIRST = 0, +#if SERIAL_UART_FIRST_INDEX == 0 + SERIAL_PORT_UART0 = SERIAL_PORT_UART_FIRST, + SERIAL_PORT_USART1, +#else + SERIAL_PORT_USART1 = SERIAL_PORT_UART_FIRST, +#endif SERIAL_PORT_UART1 = SERIAL_PORT_USART1, SERIAL_PORT_USART2, SERIAL_PORT_UART2 = SERIAL_PORT_USART2, @@ -103,10 +110,12 @@ typedef enum { SERIAL_PORT_USB_VCP = 20, - SERIAL_PORT_SOFTSERIAL1 = 30, + SERIAL_PORT_SOFTSERIAL_FIRST = 30, + SERIAL_PORT_SOFTSERIAL1 = SERIAL_PORT_SOFTSERIAL_FIRST, SERIAL_PORT_SOFTSERIAL2, - SERIAL_PORT_LPUART1 = 40, + SERIAL_PORT_LPUART_FIRST = 40, + SERIAL_PORT_LPUART1 = SERIAL_PORT_LPUART_FIRST, } serialPortIdentifier_e; // use value from target serial port normalization diff --git a/src/main/io/serial_resource.c b/src/main/io/serial_resource.c index 33eb938bb9..962e0d7d25 100644 --- a/src/main/io/serial_resource.c +++ b/src/main/io/serial_resource.c @@ -36,8 +36,9 @@ serialType_e serialType(serialPortIdentifier_e identifier) } #endif #ifdef USE_UART - if (identifier >= SERIAL_PORT_USART1 && identifier < SERIAL_PORT_USART1 + SERIAL_UART_MAX) { - const unsigned idx = identifier - SERIAL_PORT_USART1; + if (identifier >= SERIAL_PORT_UART_FIRST + && identifier < SERIAL_PORT_UART_FIRST + SERIAL_UART_MAX) { + const unsigned idx = identifier - SERIAL_PORT_UART_FIRST; if (BIT(idx) & SERIAL_UART_MASK) { return SERIALTYPE_UART; } else { @@ -47,8 +48,9 @@ serialType_e serialType(serialPortIdentifier_e identifier) } #endif #ifdef USE_LPUART - if (identifier >= SERIAL_PORT_LPUART1 && identifier < SERIAL_PORT_LPUART1 + SERIAL_LPUART_MAX) { - const unsigned idx = identifier - SERIAL_PORT_LPUART1; + if (identifier >= SERIAL_PORT_LPUART_FIRST + && identifier < SERIAL_PORT_LPUART_FIRST + SERIAL_LPUART_MAX) { + const unsigned idx = identifier - SERIAL_PORT_LPUART_FIRST; if (BIT(idx) & SERIAL_LPUART_MASK) { return SERIALTYPE_LPUART; } else { @@ -58,8 +60,9 @@ serialType_e serialType(serialPortIdentifier_e identifier) } #endif #ifdef USE_SOFTSERIAL - if (identifier >= SERIAL_PORT_SOFTSERIAL1 && identifier < SERIAL_PORT_SOFTSERIAL1 + SERIAL_SOFTSERIAL_MAX) { - // sotserials always start from 1, without holes + if (identifier >= SERIAL_PORT_SOFTSERIAL_FIRST + && identifier < SERIAL_PORT_SOFTSERIAL_FIRST + SERIAL_SOFTSERIAL_MAX) { + // sotserials always start from first index, without holes return SERIALTYPE_SOFTSERIAL; } #endif @@ -72,9 +75,9 @@ static const struct SerialTypeInfo { int8_t resourceOffset; } serialTypeMap[] = { [SERIALTYPE_USB_VCP] = { OWNER_FREE /* no owner*/, SERIAL_PORT_USB_VCP, -1 }, - [SERIALTYPE_UART] = { OWNER_SERIAL_TX, SERIAL_PORT_USART1, RESOURCE_UART_OFFSET }, - [SERIALTYPE_LPUART] = { OWNER_LPUART_TX, SERIAL_PORT_LPUART1, RESOURCE_LPUART_OFFSET }, - [SERIALTYPE_SOFTSERIAL] = { OWNER_SOFTSERIAL_TX, SERIAL_PORT_SOFTSERIAL1, RESOURCE_SOFTSERIAL_OFFSET }, + [SERIALTYPE_UART] = { OWNER_SERIAL_TX, SERIAL_PORT_UART_FIRST, RESOURCE_UART_OFFSET }, + [SERIALTYPE_LPUART] = { OWNER_LPUART_TX, SERIAL_PORT_LPUART_FIRST, RESOURCE_LPUART_OFFSET }, + [SERIALTYPE_SOFTSERIAL] = { OWNER_SOFTSERIAL_TX, SERIAL_PORT_SOFTSERIAL_FIRST, RESOURCE_SOFTSERIAL_OFFSET }, }; STATIC_ASSERT(ARRAYLEN(serialTypeMap) == SERIALTYPE_COUNT, "type table mismatch"); diff --git a/src/main/target/serial_post.h b/src/main/target/serial_post.h index ffc7569257..dc7c812c32 100644 --- a/src/main/target/serial_post.h +++ b/src/main/target/serial_post.h @@ -30,7 +30,7 @@ in Betaflight topmost directory. This include will provide following defines: SERIAL__USED 0/1 - always defined, value depends on target configuration -SERIAL__MASK - bitmask of used ports or given type. 1 is BIT(0) +SERIAL__MASK - bitmask of used ports or given type. 0 or 1 is BIT(0), based on port first_index SERIAL__COUNT - number of enabled ports of given type SERIAL__MAX - + 1, 0 when no port is enabled @@ -39,22 +39,41 @@ All _(RX|TX)_PINS are normalized too: - if port is not enable, both will be undefined, possibly with warning - pass -DWARN_UNUSED_SERIAL_PORT to compiler to check pin defined without corresponding port being enabled. -Generated on 2024-11-04 +Generated on 2024-12-20 Configuration used: { 'LPUART': {'depends': {'UART'}, 'ids': [1]}, 'SOFTSERIAL': { 'force_continuous': True, 'ids': [1, 2], 'use_enables_all': True}, - 'UART': {'ids': [1, 2, 3, 4, 5, 6, 7, 8, 9, 10], 'inverter': True}, + 'UART': { 'first_index': True, + 'ids': [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10], + 'inverter': True}, 'VCP': {'no_pins': True, 'singleton': True}} - */ #include "common/utils.h" // BIT, LOG2 /**** UART *****/ +// normalize SERIAL_UART_FIRST_INDEX +#ifndef SERIAL_UART_FIRST_INDEX +#define SERIAL_UART_FIRST_INDEX 1 +#endif + +#if SERIAL_UART_FIRST_INDEX == 0 +#if defined(USE_UART0) +# define SERIAL_UART0_USED 1 +#else +# define SERIAL_UART0_USED 0 +#endif +#else // USE_UART0 is not allowed +# if defined(USE_UART0) +# error "USE_UART0 is defined, but SERIAL_UART does not allow index 0" +# else +# define SERIAL_UART0_USED 0 +# endif +#endif #if defined(USE_UART1) # define SERIAL_UART1_USED 1 #else @@ -106,16 +125,43 @@ Configuration used: # define SERIAL_UART10_USED 0 #endif -#define SERIAL_UART_MASK ((SERIAL_UART1_USED * BIT(1 - 1)) | (SERIAL_UART2_USED * BIT(2 - 1)) | (SERIAL_UART3_USED * BIT(3 - 1)) | (SERIAL_UART4_USED * BIT(4 - 1)) | (SERIAL_UART5_USED * BIT(5 - 1)) | (SERIAL_UART6_USED * BIT(6 - 1)) | (SERIAL_UART7_USED * BIT(7 - 1)) | (SERIAL_UART8_USED * BIT(8 - 1)) | (SERIAL_UART9_USED * BIT(9 - 1)) | (SERIAL_UART10_USED * BIT(10 - 1))) -#define SERIAL_UART_COUNT (SERIAL_UART1_USED + SERIAL_UART2_USED + SERIAL_UART3_USED + SERIAL_UART4_USED + SERIAL_UART5_USED + SERIAL_UART6_USED + SERIAL_UART7_USED + SERIAL_UART8_USED + SERIAL_UART9_USED + SERIAL_UART10_USED) +#define SERIAL_UART_MASK ((SERIAL_UART0_USED * BIT(0)) | (SERIAL_UART1_USED * BIT(1 - SERIAL_UART_FIRST_INDEX)) | (SERIAL_UART2_USED * BIT(2 - SERIAL_UART_FIRST_INDEX)) | (SERIAL_UART3_USED * BIT(3 - SERIAL_UART_FIRST_INDEX)) | (SERIAL_UART4_USED * BIT(4 - SERIAL_UART_FIRST_INDEX)) | (SERIAL_UART5_USED * BIT(5 - SERIAL_UART_FIRST_INDEX)) | (SERIAL_UART6_USED * BIT(6 - SERIAL_UART_FIRST_INDEX)) | (SERIAL_UART7_USED * BIT(7 - SERIAL_UART_FIRST_INDEX)) | (SERIAL_UART8_USED * BIT(8 - SERIAL_UART_FIRST_INDEX)) | (SERIAL_UART9_USED * BIT(9 - SERIAL_UART_FIRST_INDEX)) | (SERIAL_UART10_USED * BIT(10 - SERIAL_UART_FIRST_INDEX))) +#define SERIAL_UART_COUNT (SERIAL_UART0_USED + SERIAL_UART1_USED + SERIAL_UART2_USED + SERIAL_UART3_USED + SERIAL_UART4_USED + SERIAL_UART5_USED + SERIAL_UART6_USED + SERIAL_UART7_USED + SERIAL_UART8_USED + SERIAL_UART9_USED + SERIAL_UART10_USED) // 0 if no port is defined #define SERIAL_UART_MAX (SERIAL_UART_MASK ? LOG2(SERIAL_UART_MASK) + 1 : 0) - // enable USE_INVERTED first, before normalization -#if !defined(USE_INVERTER) && (INVERTER_PIN_UART1 || INVERTER_PIN_UART2 || INVERTER_PIN_UART3 || INVERTER_PIN_UART4 || INVERTER_PIN_UART5 || INVERTER_PIN_UART6 || INVERTER_PIN_UART7 || INVERTER_PIN_UART8 || INVERTER_PIN_UART9 || INVERTER_PIN_UART10) +#if !defined(USE_INVERTER) && (INVERTER_PIN_UART0 || INVERTER_PIN_UART1 || INVERTER_PIN_UART2 || INVERTER_PIN_UART3 || INVERTER_PIN_UART4 || INVERTER_PIN_UART5 || INVERTER_PIN_UART6 || INVERTER_PIN_UART7 || INVERTER_PIN_UART8 || INVERTER_PIN_UART9 || INVERTER_PIN_UART10) # define USE_INVERTER #endif + // Normalize UART TX/RX/INVERTER +#if SERIAL_UART0_USED && !defined(UART0_RX_PIN) +# define UART0_RX_PIN NONE +#endif +#if defined(WARN_UNUSED_SERIAL_PORT) && !SERIAL_UART0_USED && defined(UART0_RX_PIN) +# warning "UART0_RX_PIN is defined but UART0 is not enabled" +#endif +#if !SERIAL_UART0_USED && defined(UART0_RX_PIN) +# undef UART0_RX_PIN +#endif +#if SERIAL_UART0_USED && !defined(UART0_TX_PIN) +# define UART0_TX_PIN NONE +#endif +#if defined(WARN_UNUSED_SERIAL_PORT) && !SERIAL_UART0_USED && defined(UART0_TX_PIN) +# warning "UART0_TX_PIN is defined but UART0 is not enabled" +#endif +#if !SERIAL_UART0_USED && defined(UART0_TX_PIN) +# undef UART0_TX_PIN +#endif +#if SERIAL_UART0_USED && !defined(INVERTER_PIN_UART0) +# define INVERTER_PIN_UART0 NONE +#endif +#if defined(WARN_UNUSED_SERIAL_PORT) && !SERIAL_UART0_USED && defined(INVERTER_PIN_UART0) +# warning "INVERTER_PIN_UART0 is defined but UART0 is not enabled" +#endif +#if !SERIAL_UART0_USED && defined(INVERTER_PIN_UART0) +# undef INVERTER_PIN_UART0 +#endif #if SERIAL_UART1_USED && !defined(UART1_RX_PIN) # define UART1_RX_PIN NONE #endif @@ -421,7 +467,9 @@ Configuration used: #endif /**** SOFTSERIAL *****/ + #if defined(USE_SOFTSERIAL) +// USE_SOFTSERIAL enables all SOFTSERIAL ports # if !defined(USE_SOFTSERIAL1) # define USE_SOFTSERIAL1 # endif @@ -496,7 +544,7 @@ Configuration used: # define SERIAL_VCP_USED 0 #endif -// set one bit if port is enabled for consistency +// for consistency, set one bit if port is enabled #define SERIAL_VCP_MASK (SERIAL_VCP_USED * BIT(0)) #define SERIAL_VCP_COUNT (SERIAL_VCP_USED) // 0 if no port is defined diff --git a/src/utils/gen-serial-j2.py b/src/utils/gen-serial-j2.py index daefa9654d..79da84a4fa 100644 --- a/src/utils/gen-serial-j2.py +++ b/src/utils/gen-serial-j2.py @@ -8,14 +8,15 @@ import pprint # configuration for template generation serials = { - "UART": {"ids": [i + 1 for i in range(10)], + "UART": {"ids": list(range(0, 10 + 1)), "inverter": True, + "first_index": True, # support configurable first index for this port }, "LPUART": {"ids": [1], "depends": {"UART"}, # "inverter": True, # TODO: old code compatibility only, disabled }, - "SOFTSERIAL": {"ids": [i + 1 for i in range(2)], + "SOFTSERIAL": {"ids": list(range(1, 2 + 1)), "use_enables_all": True, "force_continuous": True, }, @@ -69,6 +70,7 @@ def main(): singleton = cfg.setdefault('singleton', False) no_pins = cfg.setdefault('no_pins', False) inverter = cfg.setdefault('inverter', False) + cfg.setdefault('first_index', False) cfg.setdefault("use_enables_all", False) cfg.setdefault("force_continuous", False) cfg.setdefault("depends", {}) diff --git a/src/utils/templates/serial_post.h b/src/utils/templates/serial_post.h index f6455ee68b..83ce3d4b32 100644 --- a/src/utils/templates/serial_post.h +++ b/src/utils/templates/serial_post.h @@ -1,7 +1,6 @@ {# serial_post.h #} {# DEFAULT_LICENCE.md is used #} {{ license|safe }} - /* {# Start with generated warning. It you want to change something, edit this file #} This file is automatically generated by src/utils/gen-serial.py script from src/utils/templates/serial_post.h jinja2 template. @@ -14,7 +13,7 @@ in Betaflight topmost directory. This include will provide following defines: SERIAL__USED 0/1 - always defined, value depends on target configuration -SERIAL__MASK - bitmask of used ports or given type. 1 is BIT(0) +SERIAL__MASK - bitmask of used ports or given type. 0 or 1 is BIT(0), based on port first_index SERIAL__COUNT - number of enabled ports of given type SERIAL__MAX - + 1, 0 when no port is enabled @@ -30,56 +29,77 @@ Configuration used: {# TODO - maybe store configuration in this file, not Python one #} {# TODO - pretty is not enough pretty #} {{ user_config|pprint|safe }} - */ #include "common/utils.h" // BIT, LOG2 -{# config array is passed to this script. It is flattened version of user_config, with default fileld in #} +{# config array is passed to this script. It is flattened version of user_config, with defaults filled in #} {% for cfg in config %} /**** {{ cfg.typ }} *****/ + +{% if cfg.first_index %} +// normalize SERIAL_{{ cfg.typ }}_FIRST_INDEX +#ifndef SERIAL_{{ cfg.typ }}_FIRST_INDEX +#define SERIAL_{{ cfg.typ }}_FIRST_INDEX 1 +#endif + +{% endif %} {# use_enables_all - USE_ enables all ports of this type #} {% if cfg.use_enables_all %} #if defined(USE_{{cfg.typ}}) +// USE_{{cfg.typ}} enables all {{cfg.typ}} ports {% for port in cfg.ports %} # if !defined(USE_{{port}}) # define USE_{{port}} # endif {% endfor %} #endif -{% endif %} +{% endif %} {# USE_ - SERIAL__USED 0/1 #} -{% for port in cfg.ports %} +{% for port, i in cfg.ports|zip(cfg.ids|default([-1])) %}{# handle singleton without ids #} +{% if i == 0 and cfg.first_index %}{# port 0, test if it is allowed #} +#if SERIAL_{{ cfg.typ }}_FIRST_INDEX == 0 +{% endif %} #if defined(USE_{{port}}) # define SERIAL_{{port}}_USED 1 #else # define SERIAL_{{port}}_USED 0 #endif +{% if i == 0 and cfg.first_index %}{# port 0, #else branch #} +#else // USE_{{port}} is not allowed +# if defined(USE_{{port}}) +# error "USE_{{port}} is defined, but SERIAL_{{ cfg.typ }} does not allow index 0" +# else +# define SERIAL_{{port}}_USED 0 +# endif +#endif +{% endif %} {% endfor %} {# SERIAL__* summary macros #} {% if not cfg.singleton %} {% set pipe = joiner(' | ') %} -#define SERIAL_{{ cfg.typ }}_MASK ({% for port, i in cfg.ports|zip(cfg.ids) %}{{ pipe() }}(SERIAL_{{ port }}_USED * BIT({{ i }} - 1)){% endfor %}) +#define SERIAL_{{ cfg.typ }}_MASK ({% for port, i in cfg.ports|zip(cfg.ids) %} + {{- pipe() }}(SERIAL_{{ port }}_USED * BIT({{ "0" if i==0 else "{} - SERIAL_{}_FIRST_INDEX".format(i, cfg.typ) if cfg.first_index else "{} - 1".format(i) }})){% endfor %}) +{# export first index information, so serial.h can assert that it does match #} {% else %} {# one port without number is defined #} -// set one bit if port is enabled for consistency +// for consistency, set one bit if port is enabled #define SERIAL_{{ cfg.typ }}_MASK (SERIAL_{{ cfg.ports[0] }}_USED * BIT(0)) {% endif %} {% set plus = joiner(' + ') %} #define SERIAL_{{ cfg.typ }}_COUNT ({% for port in cfg.ports %}{{ plus() }}SERIAL_{{ port }}_USED{% endfor %}) -{# LOG2 is simpler than chaining MAX(SERIAL_x1_USED * 1, MAX(SERIAL_x2_USED * 2, ... #} // 0 if no port is defined +{# LOG2 is simpler than chaining MAX(SERIAL_x1_USED * 1, MAX(SERIAL_x2_USED * 2, ... #} #define SERIAL_{{ cfg.typ }}_MAX (SERIAL_{{cfg.typ}}_MASK ? LOG2(SERIAL_{{cfg.typ}}_MASK) + 1 : 0) - {# for softserial, we don't want softserial2 only #} {% if cfg.force_continuous %} + #if SERIAL_{{cfg.typ}}_COUNT != SERIAL_{{cfg.typ}}_MAX # error {{cfg.typ}} ports must start with {{cfg.typ}}1 and be continuous #endif {% endif %} - {# backward compatibility, code did set USE_INVERTER this way. It must be done before normalizing to NONE #} {% if cfg.inverter %} // enable USE_INVERTED first, before normalization @@ -90,6 +110,7 @@ Configuration used: {% endif %} {# no pins for VCP port #} {% if not cfg.no_pins %} + // Normalize {{cfg.typ}} TX/RX{{ "/INVERTER" if cfg.inverter else "" }} {% for port in cfg.ports %} {% set pins = [ port ~ '_RX_PIN', port ~ '_TX_PIN' ] + (['INVERTER_PIN_' ~ port] if cfg.inverter else []) %} From d244239f39c60b54bf7990d979d78bcbae053c2e Mon Sep 17 00:00:00 2001 From: ahmedsalah52 <46837894+ahmedsalah52@users.noreply.github.com> Date: Fri, 20 Dec 2024 19:47:36 +0100 Subject: [PATCH 006/244] opticalflow mt sensor added (#14038) * opticalflow mt sensor added * set the processedFlow to raw when no rotation * use sin and cos approximations Co-authored-by: Petr Ledvina * Update src/main/sensors/opticalflow.c Co-authored-by: Petr Ledvina * refactoring * not needed anymore * update * Update src/main/sensors/opticalflow.c Co-authored-by: Petr Ledvina * Update src/main/sensors/opticalflow.c Co-authored-by: Petr Ledvina * Update src/main/drivers/rangefinder/rangefinder_lidarmt.c Co-authored-by: Petr Ledvina * update * rm prototype * clean up * Update src/main/drivers/opticalflow/opticalflow.h Co-authored-by: Petr Ledvina * Update src/main/drivers/opticalflow/opticalflow.h Co-authored-by: Mark Haslinghuis * update flip_y * Update src/main/drivers/opticalflow/opticalflow.h Co-authored-by: Petr Ledvina * Update src/main/drivers/rangefinder/rangefinder_lidarmt.c Co-authored-by: Petr Ledvina * Update src/main/drivers/rangefinder/rangefinder_lidarmt.h Co-authored-by: Petr Ledvina * Update src/main/sensors/opticalflow.c Co-authored-by: Petr Ledvina * Update src/main/sensors/opticalflow.c Co-authored-by: Petr Ledvina * Update src/main/sensors/opticalflow.c Co-authored-by: Mark Haslinghuis * rm casting * update op rotation --------- Co-authored-by: Petr Ledvina Co-authored-by: Mark Haslinghuis --- mk/source.mk | 1 + src/main/build/debug.c | 1 + src/main/build/debug.h | 1 + src/main/cli/cli.c | 3 +- src/main/cli/settings.c | 17 ++ src/main/cli/settings.h | 5 + src/main/config/feature.c | 3 + src/main/config/feature.h | 1 + src/main/drivers/opticalflow/opticalflow.h | 52 +++++ .../drivers/rangefinder/rangefinder_lidarmt.c | 92 ++++++-- .../drivers/rangefinder/rangefinder_lidarmt.h | 9 + src/main/fc/tasks.c | 25 ++- src/main/msp/msp.c | 27 ++- src/main/msp/msp_protocol_v2_betaflight.h | 1 + src/main/msp/msp_protocol_v2_common.h | 1 + src/main/pg/pg_ids.h | 4 +- src/main/scheduler/scheduler.h | 3 + src/main/sensors/initialisation.c | 9 +- src/main/sensors/opticalflow.c | 196 ++++++++++++++++++ src/main/sensors/opticalflow.h | 56 +++++ src/main/sensors/sensors.h | 4 +- 21 files changed, 490 insertions(+), 21 deletions(-) create mode 100644 src/main/drivers/opticalflow/opticalflow.h create mode 100644 src/main/sensors/opticalflow.c create mode 100644 src/main/sensors/opticalflow.h diff --git a/mk/source.mk b/mk/source.mk index 317d4c4355..70e4d00b57 100644 --- a/mk/source.mk +++ b/mk/source.mk @@ -252,6 +252,7 @@ COMMON_SRC = \ osd/osd_warnings.c \ sensors/barometer.c \ sensors/rangefinder.c \ + sensors/opticalflow.c \ telemetry/telemetry.c \ telemetry/crsf.c \ telemetry/ghst.c \ diff --git a/src/main/build/debug.c b/src/main/build/debug.c index f51ea8a4a1..3d67bae371 100644 --- a/src/main/build/debug.c +++ b/src/main/build/debug.c @@ -55,6 +55,7 @@ const char * const debugModeNames[DEBUG_COUNT] = { [DEBUG_FPORT] = "FPORT", [DEBUG_RANGEFINDER] = "RANGEFINDER", [DEBUG_RANGEFINDER_QUALITY] = "RANGEFINDER_QUALITY", + [DEBUG_OPTICALFLOW] = "OPTICALFLOW", [DEBUG_LIDAR_TF] = "LIDAR_TF", [DEBUG_ADC_INTERNAL] = "ADC_INTERNAL", [DEBUG_RUNAWAY_TAKEOFF] = "RUNAWAY_TAKEOFF", diff --git a/src/main/build/debug.h b/src/main/build/debug.h index b0070b69de..6e6e43a67a 100644 --- a/src/main/build/debug.h +++ b/src/main/build/debug.h @@ -57,6 +57,7 @@ typedef enum { DEBUG_FPORT, DEBUG_RANGEFINDER, DEBUG_RANGEFINDER_QUALITY, + DEBUG_OPTICALFLOW, DEBUG_LIDAR_TF, DEBUG_ADC_INTERNAL, DEBUG_RUNAWAY_TAKEOFF, diff --git a/src/main/cli/cli.c b/src/main/cli/cli.c index 36ea8155e8..926b5ada5a 100644 --- a/src/main/cli/cli.c +++ b/src/main/cli/cli.c @@ -239,6 +239,7 @@ static const char * const featureNames[] = { _R(FEATURE_SOFTSERIAL, "SOFTSERIAL"), _R(FEATURE_GPS, "GPS"), _R(FEATURE_RANGEFINDER, "RANGEFINDER"), + _R(FEATURE_OPTICALFLOW, "OPTICALFLOW"), _R(FEATURE_TELEMETRY, "TELEMETRY"), _R(FEATURE_3D, "3D"), _R(FEATURE_RX_PARALLEL_PWM, "RX_PARALLEL_PWM"), @@ -272,7 +273,7 @@ static const char *const sensorTypeNames[] = { #define SENSOR_NAMES_MASK (SENSOR_GYRO | SENSOR_ACC | SENSOR_BARO | SENSOR_MAG | SENSOR_RANGEFINDER) static const char * const *sensorHardwareNames[] = { - lookupTableGyroHardware, lookupTableAccHardware, lookupTableBaroHardware, lookupTableMagHardware, lookupTableRangefinderHardware + lookupTableGyroHardware, lookupTableAccHardware, lookupTableBaroHardware, lookupTableMagHardware, lookupTableRangefinderHardware, lookupTableOpticalflowHardware }; #endif // USE_SENSOR_NAMES diff --git a/src/main/cli/settings.c b/src/main/cli/settings.c index f01c942fa2..fc4e9a703a 100644 --- a/src/main/cli/settings.c +++ b/src/main/cli/settings.c @@ -129,6 +129,7 @@ #include "sensors/esc_sensor.h" #include "sensors/gyro.h" #include "sensors/rangefinder.h" +#include "sensors/opticalflow.h" #include "scheduler/scheduler.h" @@ -170,6 +171,11 @@ const char * const lookupTableRangefinderHardware[] = { "NONE", "HCSR04", "TFMINI", "TF02", "MTF01", "MTF02", "MTF01P", "MTF02P" }; #endif +#if defined(USE_SENSOR_NAMES) || defined(USE_OPTICALFLOW) +const char * const lookupTableOpticalflowHardware[] = { + "NONE", "MT" +}; +#endif const char * const lookupTableOffOn[] = { "OFF", "ON" @@ -613,6 +619,9 @@ const lookupTableEntry_t lookupTables[] = { #ifdef USE_RANGEFINDER LOOKUP_TABLE_ENTRY(lookupTableRangefinderHardware), #endif +#ifdef USE_OPTICALFLOW + LOOKUP_TABLE_ENTRY(lookupTableOpticalflowHardware), +#endif #ifdef USE_GYRO_OVERFLOW_CHECK LOOKUP_TABLE_ENTRY(lookupTableGyroOverflowCheck), #endif @@ -1710,6 +1719,14 @@ const clivalue_t valueTable[] = { { "rangefinder_hardware", VAR_UINT8 | MASTER_VALUE | MODE_LOOKUP, .config.lookup = { TABLE_RANGEFINDER_HARDWARE }, PG_RANGEFINDER_CONFIG, offsetof(rangefinderConfig_t, rangefinder_hardware) }, #endif +// PG_OPTICALFLOW_CONFIG +#ifdef USE_OPTICALFLOW + { "opticalflow_hardware", VAR_UINT8 | MASTER_VALUE | MODE_LOOKUP, .config.lookup = { TABLE_OPTICALFLOW_HARDWARE }, PG_OPTICALFLOW_CONFIG, offsetof(opticalflowConfig_t, opticalflow_hardware) }, + { "opticalflow_rotation", VAR_INT16 | MASTER_VALUE , .config.minmaxUnsigned = {0, 359}, PG_OPTICALFLOW_CONFIG, offsetof(opticalflowConfig_t, rotation) }, + { "opticalflow_lpf", VAR_UINT16 | MASTER_VALUE , .config.minmaxUnsigned = {0, 10000}, PG_OPTICALFLOW_CONFIG, offsetof(opticalflowConfig_t, flow_lpf) }, + { "opticalflow_flip_x", VAR_UINT8 | MASTER_VALUE | MODE_LOOKUP, .config.lookup = { TABLE_OFF_ON }, PG_OPTICALFLOW_CONFIG, offsetof(opticalflowConfig_t, flip_x) }, +#endif + // PG_PINIO_CONFIG #ifdef USE_PINIO { "pinio_config", VAR_UINT8 | HARDWARE_VALUE | MODE_ARRAY, .config.array.length = PINIO_COUNT, PG_PINIO_CONFIG, offsetof(pinioConfig_t, config) }, diff --git a/src/main/cli/settings.h b/src/main/cli/settings.h index b67664a0e8..b3222f8b94 100644 --- a/src/main/cli/settings.h +++ b/src/main/cli/settings.h @@ -82,6 +82,9 @@ typedef enum { #ifdef USE_RANGEFINDER TABLE_RANGEFINDER_HARDWARE, #endif +#ifdef USE_OPTICALFLOW + TABLE_OPTICALFLOW_HARDWARE, +#endif #ifdef USE_GYRO_OVERFLOW_CHECK TABLE_GYRO_OVERFLOW_CHECK, #endif @@ -260,6 +263,8 @@ extern const char * const lookupTableMagHardware[]; extern const char * const lookupTableRangefinderHardware[]; +extern const char * const lookupTableOpticalflowHardware[]; + extern const char * const lookupTableLedstripColors[]; extern const char * const lookupTableRescueAltitudeMode[]; diff --git a/src/main/config/feature.c b/src/main/config/feature.c index d8e2ebd57f..6dbd490adc 100644 --- a/src/main/config/feature.c +++ b/src/main/config/feature.c @@ -57,6 +57,9 @@ uint32_t featuresSupportedByBuild = #ifdef USE_RANGEFINDER | FEATURE_RANGEFINDER #endif +#ifdef USE_OPTICALFLOW + | FEATURE_OPTICALFLOW +#endif #ifdef USE_TELEMETRY | FEATURE_TELEMETRY #endif diff --git a/src/main/config/feature.h b/src/main/config/feature.h index 039a49e83d..28cec3aa3d 100644 --- a/src/main/config/feature.h +++ b/src/main/config/feature.h @@ -50,6 +50,7 @@ typedef enum { FEATURE_SERVO_TILT = 1 << 5, FEATURE_SOFTSERIAL = 1 << 6, FEATURE_GPS = 1 << 7, + FEATURE_OPTICALFLOW = 1 << 8, FEATURE_RANGEFINDER = 1 << 9, FEATURE_TELEMETRY = 1 << 10, FEATURE_3D = 1 << 12, diff --git a/src/main/drivers/opticalflow/opticalflow.h b/src/main/drivers/opticalflow/opticalflow.h new file mode 100644 index 0000000000..8f3ad6dd29 --- /dev/null +++ b/src/main/drivers/opticalflow/opticalflow.h @@ -0,0 +1,52 @@ +/* + * This file is part of Betaflight. + * + * Betaflight is free software. You can redistribute this software + * and/or modify this software under the terms of the GNU General + * Public License as published by the Free Software Foundation, + * either version 3 of the License, or (at your option) any later + * version. + * + * Betaflight is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * See the GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this software. + * + * If not, see . + */ + +#pragma once + +#include +#include "common/vector.h" + +#define OPTICALFLOW_OUT_OF_RANGE -1 +#define OPTICALFLOW_HARDWARE_FAILURE -2 +#define OPTICALFLOW_NO_NEW_DATA -3 + +#define OPTICALFLOW_HARDWARE_TIMEOUT_US 100000 // 100ms + +typedef struct opticalflowData_s { + uint32_t timeStampUs; + int16_t quality; + vector2_t flowRate; +} opticalflowData_t; + +struct opticalflowDev_s; +typedef void opflowOpInitFunc(struct opticalflowDev_s * dev); +typedef void opflowOpUpdateFunc(struct opticalflowDev_s * dev); +typedef void opflowOpReadFunc(struct opticalflowDev_s * dev, opticalflowData_t * result); + +typedef struct opticalflowDev_s { + unsigned delayMs; + int16_t minRangeCm; + uint8_t minQualityThreshold; + + opflowOpInitFunc *init; + opflowOpUpdateFunc *update; + opflowOpReadFunc *read; +} opticalflowDev_t; diff --git a/src/main/drivers/rangefinder/rangefinder_lidarmt.c b/src/main/drivers/rangefinder/rangefinder_lidarmt.c index 863952385c..8204547d1a 100644 --- a/src/main/drivers/rangefinder/rangefinder_lidarmt.c +++ b/src/main/drivers/rangefinder/rangefinder_lidarmt.c @@ -24,7 +24,6 @@ #include #include -#include #include "platform.h" @@ -34,11 +33,21 @@ #include "common/utils.h" +#include "drivers/time.h" + #include "drivers/rangefinder/rangefinder_lidarmt.h" #include "sensors/rangefinder.h" -static bool hasNewData = false; -static int32_t sensorData = RANGEFINDER_NO_NEW_DATA; +#include "drivers/opticalflow/opticalflow.h" + +#define MT_OPTICALFLOW_MIN_RANGE 80 // mm +#define MT_OPFLOW_MIN_QUALITY_THRESHOLD 30 + +static opticalflowData_t opticalflowSensorData = {0}; + +static bool hasRFNewData = false; +static mtRangefinderData_t rfSensorData = {RANGEFINDER_NO_NEW_DATA, 0}; +static const MTRangefinderConfig * deviceConf = NULL; // Initialize the table with values for each rangefinder type static const MTRangefinderConfig rangefinderConfigs[] = { @@ -63,40 +72,41 @@ static void mtRangefinderUpdate(rangefinderDev_t * dev) { static int32_t mtRangefinderGetDistance(rangefinderDev_t * dev) { UNUSED(dev); - if (hasNewData) { - hasNewData = false; - return (sensorData >= 0.0f) ? sensorData : RANGEFINDER_OUT_OF_RANGE; + if (hasRFNewData) { + hasRFNewData = false; + return (rfSensorData.distanceMm >= 0) ? (rfSensorData.distanceMm / 10) : RANGEFINDER_OUT_OF_RANGE; } else { return RANGEFINDER_NO_NEW_DATA; } } bool mtRangefinderDetect(rangefinderDev_t * dev, rangefinderType_e mtRangefinderToUse) { - const MTRangefinderConfig* deviceConf = getMTRangefinderDeviceConf(mtRangefinderToUse); + deviceConf = getMTRangefinderDeviceConf(mtRangefinderToUse); if (!deviceConf) { return false; } + dev->delayMs = deviceConf->delayMs; dev->maxRangeCm = deviceConf->maxRangeCm; dev->detectionConeDeciDegrees = RANGEFINDER_MT_DETECTION_CONE_DECIDEGREES; dev->detectionConeExtendedDeciDegrees = RANGEFINDER_MT_DETECTION_CONE_DECIDEGREES; - dev->init = &mtRangefinderInit; + dev->init = &mtRangefinderInit; dev->update = &mtRangefinderUpdate; - dev->read = &mtRangefinderGetDistance; - + dev->read = &mtRangefinderGetDistance; return true; } void mtRangefinderReceiveNewData(const uint8_t * bufferPtr) { const mspSensorRangefinderLidarMtDataMessage_t * pkt = (const mspSensorRangefinderLidarMtDataMessage_t *)bufferPtr; - sensorData = pkt->distanceMm / 10; - hasNewData = true; + rfSensorData.distanceMm = pkt->distanceMm; + rfSensorData.timestampUs = micros(); + hasRFNewData = true; } -const MTRangefinderConfig* getMTRangefinderDeviceConf(rangefinderType_e mtRangefinderToUse){ +const MTRangefinderConfig* getMTRangefinderDeviceConf(rangefinderType_e mtRangefinderToUse) { for (const MTRangefinderConfig* cfg = rangefinderConfigs; cfg < ARRAYEND(rangefinderConfigs); cfg++) { if (cfg->deviceType == mtRangefinderToUse) { return cfg; @@ -105,4 +115,60 @@ const MTRangefinderConfig* getMTRangefinderDeviceConf(rangefinderType_e mtRangef return NULL; } +const mtRangefinderData_t * getMTRangefinderData(void) { + return &rfSensorData; +} + +typedef struct __attribute__((packed)) { + uint8_t quality; // [0;255] + int32_t motionX; + int32_t motionY; +} mtOpticalflowDataMessage_t; + +static void mtOpticalflowInit(opticalflowDev_t * dev) { + UNUSED(dev); +} + +static void mtOpticalflowUpdate(opticalflowDev_t * dev) { + UNUSED(dev); +} + +static void mtOpticalflowGetData(opticalflowDev_t * dev, opticalflowData_t * result) { + UNUSED(dev); + *result = opticalflowSensorData; +} + +bool mtOpticalflowDetect(opticalflowDev_t * dev, rangefinderType_e mtRangefinderToUse) { + deviceConf = getMTRangefinderDeviceConf(mtRangefinderToUse); + if (!deviceConf) { + return false; + } + + dev->delayMs = deviceConf->delayMs; + dev->minRangeCm = MT_OPTICALFLOW_MIN_RANGE; + dev->minQualityThreshold = MT_OPFLOW_MIN_QUALITY_THRESHOLD; + + dev->init = &mtOpticalflowInit; + dev->update = &mtOpticalflowUpdate; + dev->read = &mtOpticalflowGetData; + + return true; +} + +void mtOpticalflowReceiveNewData(const uint8_t * bufferPtr) { + const mtRangefinderData_t * latestRangefinderData = getMTRangefinderData(); + + const mtOpticalflowDataMessage_t * pkt = (const mtOpticalflowDataMessage_t *)bufferPtr; + + opticalflowSensorData.timeStampUs = micros(); + opticalflowSensorData.flowRate.x = (float)pkt->motionX / 1000.0f; + opticalflowSensorData.flowRate.y = (float)pkt->motionY / 1000.0f; + opticalflowSensorData.quality = pkt->quality * 100 / 255; + + if (latestRangefinderData->distanceMm < MT_OPTICALFLOW_MIN_RANGE) { + opticalflowSensorData.quality = OPTICALFLOW_OUT_OF_RANGE; + } else if (cmp32(micros(), latestRangefinderData->timestampUs) > (5000 * deviceConf->delayMs)) { // 5 updates missing + opticalflowSensorData.quality = OPTICALFLOW_HARDWARE_FAILURE; + } +} #endif // USE_RANGEFINDER_MT diff --git a/src/main/drivers/rangefinder/rangefinder_lidarmt.h b/src/main/drivers/rangefinder/rangefinder_lidarmt.h index 773c61b867..855e58f7cc 100644 --- a/src/main/drivers/rangefinder/rangefinder_lidarmt.h +++ b/src/main/drivers/rangefinder/rangefinder_lidarmt.h @@ -21,6 +21,7 @@ #pragma once #include "drivers/rangefinder/rangefinder.h" +#include "drivers/opticalflow/opticalflow.h" #include "sensors/rangefinder.h" #define RANGEFINDER_MT_DETECTION_CONE_DECIDEGREES 900 @@ -31,6 +32,14 @@ typedef struct { uint16_t maxRangeCm; } MTRangefinderConfig; +typedef struct { + uint32_t timestampUs; + int32_t distanceMm; +} mtRangefinderData_t; + bool mtRangefinderDetect(rangefinderDev_t * dev, rangefinderType_e mtRangefinderToUse); void mtRangefinderReceiveNewData(const uint8_t * bufferPtr); const MTRangefinderConfig* getMTRangefinderDeviceConf(rangefinderType_e mtRangefinderToUse); + +bool mtOpticalflowDetect(opticalflowDev_t * dev, rangefinderType_e mtRangefinderToUse); +void mtOpticalflowReceiveNewData(const uint8_t * bufferPtr); diff --git a/src/main/fc/tasks.c b/src/main/fc/tasks.c index 0317cf537f..62885df0fa 100644 --- a/src/main/fc/tasks.c +++ b/src/main/fc/tasks.c @@ -98,6 +98,7 @@ #include "sensors/gyro.h" #include "sensors/sensors.h" #include "sensors/rangefinder.h" +#include "sensors/opticalflow.h" #include "telemetry/telemetry.h" #include "telemetry/crsf.h" @@ -302,6 +303,20 @@ void taskUpdateRangefinder(timeUs_t currentTimeUs) } #endif +#ifdef USE_OPTICALFLOW +void taskUpdateOpticalflow(timeUs_t currentTimeUs) +{ + UNUSED(currentTimeUs); + + if (!sensors(SENSOR_OPTICALFLOW)) { + return; + } + + opticalflowUpdate(); + opticalflowProcess(); +} +#endif + #ifdef USE_TELEMETRY static void taskTelemetry(timeUs_t currentTimeUs) { @@ -449,7 +464,9 @@ task_attribute_t task_attributes[TASK_COUNT] = { #ifdef USE_RANGEFINDER [TASK_RANGEFINDER] = DEFINE_TASK("RANGEFINDER", NULL, NULL, taskUpdateRangefinder, TASK_PERIOD_HZ(10), TASK_PRIORITY_LOWEST), #endif - +#ifdef USE_OPTICALFLOW + [TASK_OPTICALFLOW] = DEFINE_TASK("OPTICALFLOW", NULL, NULL, taskUpdateOpticalflow, TASK_PERIOD_HZ(10), TASK_PRIORITY_LOWEST), +#endif #ifdef USE_CRSF_V3 [TASK_SPEED_NEGOTIATION] = DEFINE_TASK("SPEED_NEGOTIATION", NULL, NULL, speedNegotiationProcess, TASK_PERIOD_HZ(100), TASK_PRIORITY_LOW), #endif @@ -528,6 +545,12 @@ void tasksInit(void) } #endif +#ifdef USE_OPTICALFLOW + if (sensors(SENSOR_OPTICALFLOW)) { + setTaskEnabled(TASK_OPTICALFLOW, featureIsEnabled(FEATURE_OPTICALFLOW)); + } +#endif + setTaskEnabled(TASK_RX, true); setTaskEnabled(TASK_DISPATCH, dispatchIsEnabled()); diff --git a/src/main/msp/msp.c b/src/main/msp/msp.c index 56fe357f70..dcb6df0f75 100644 --- a/src/main/msp/msp.c +++ b/src/main/msp/msp.c @@ -149,6 +149,7 @@ #include "sensors/gyro.h" #include "sensors/gyro_init.h" #include "sensors/rangefinder.h" +#include "sensors/opticalflow.h" #include "telemetry/msp_shared.h" #include "telemetry/telemetry.h" @@ -2054,7 +2055,7 @@ case MSP_NAME: break; case MSP_SENSOR_CONFIG: - // use sensorIndex_e index: 0:GyroHardware, 1:AccHardware, 2:BaroHardware, 3:MagHardware, 4:RangefinderHardware + // use sensorIndex_e index: 0:GyroHardware, 1:AccHardware, 2:BaroHardware, 3:MagHardware, 4:RangefinderHardware 5:OpticalflowHardware #if defined(USE_ACC) sbufWriteU8(dst, accelerometerConfig()->acc_hardware); #else @@ -2076,6 +2077,12 @@ case MSP_NAME: #else sbufWriteU8(dst, RANGEFINDER_NONE); #endif + +#ifdef USE_OPTICALFLOW + sbufWriteU8(dst, opticalflowConfig()->opticalflow_hardware); +#else + sbufWriteU8(dst, OPTICALFLOW_NONE); +#endif break; // Added in MSP API 1.46 @@ -2107,6 +2114,11 @@ case MSP_NAME: sbufWriteU8(dst, detectedSensors[SENSOR_INDEX_RANGEFINDER]); #else sbufWriteU8(dst, SENSOR_NOT_AVAILABLE); +#endif +#ifdef USE_OPTICAL_FLOW + sbufWriteU8(dst, detectedSensors[SENSOR_INDEX_OPTICALFLOW]); +#else + sbufWriteU8(dst, SENSOR_NOT_AVAILABLE); #endif break; @@ -3301,7 +3313,13 @@ static mspResult_e mspProcessInCommand(mspDescriptor_t srcDesc, int16_t cmdMSP, #ifdef USE_RANGEFINDER rangefinderConfigMutable()->rangefinder_hardware = sbufReadU8(src); #else - sbufReadU8(src); // rangefinder hardware + sbufReadU8(src); +#endif + +#ifdef USE_OPTICALFLOW + opticalflowConfigMutable()->opticalflow_hardware = sbufReadU8(src); +#else + sbufReadU8(src); #endif break; #ifdef USE_ACC @@ -3658,7 +3676,12 @@ static mspResult_e mspProcessInCommand(mspDescriptor_t srcDesc, int16_t cmdMSP, case MSP2_SENSOR_RANGEFINDER_LIDARMT: mtRangefinderReceiveNewData(sbufPtr(src)); break; + + case MSP2_SENSOR_OPTICALFLOW_MT: + mtOpticalflowReceiveNewData(sbufPtr(src)); + break; #endif + #ifdef USE_GPS case MSP2_SENSOR_GPS: (void)sbufReadU8(src); // instance diff --git a/src/main/msp/msp_protocol_v2_betaflight.h b/src/main/msp/msp_protocol_v2_betaflight.h index b039defb71..f96cd6a817 100644 --- a/src/main/msp/msp_protocol_v2_betaflight.h +++ b/src/main/msp/msp_protocol_v2_betaflight.h @@ -29,6 +29,7 @@ #define MSP2_GET_LED_STRIP_CONFIG_VALUES 0x3008 #define MSP2_SET_LED_STRIP_CONFIG_VALUES 0x3009 #define MSP2_SENSOR_CONFIG_ACTIVE 0x300A +#define MSP2_SENSOR_OPTICALFLOW 0x300B // MSP2_SET_TEXT and MSP2_GET_TEXT variable types #define MSP2TEXT_PILOT_NAME 1 diff --git a/src/main/msp/msp_protocol_v2_common.h b/src/main/msp/msp_protocol_v2_common.h index be3344c324..28e1469155 100644 --- a/src/main/msp/msp_protocol_v2_common.h +++ b/src/main/msp/msp_protocol_v2_common.h @@ -25,3 +25,4 @@ #define MSP2_SENSOR_GPS 0x1F03 // TODO: implement new, extensible rangefinder protocol #define MSP2_SENSOR_RANGEFINDER_LIDARMT 0x1F01 +#define MSP2_SENSOR_OPTICALFLOW_MT 0x1F02 diff --git a/src/main/pg/pg_ids.h b/src/main/pg/pg_ids.h index caa85f0f30..97e3d125d9 100644 --- a/src/main/pg/pg_ids.h +++ b/src/main/pg/pg_ids.h @@ -158,7 +158,9 @@ #define PG_MSP_CONFIG 557 //#define PG_SOFTSERIAL_PIN_CONFIG 558 // removed, merged into SERIAL_PIN_CONFIG #define PG_GIMBAL_TRACK_CONFIG 559 -#define PG_BETAFLIGHT_END 559 +#define PG_OPTICALFLOW_CONFIG 560 +#define PG_BETAFLIGHT_END 560 + // OSD configuration (subject to change) #define PG_OSD_FONT_CONFIG 2047 diff --git a/src/main/scheduler/scheduler.h b/src/main/scheduler/scheduler.h index 88ae1091aa..9e190994cc 100644 --- a/src/main/scheduler/scheduler.h +++ b/src/main/scheduler/scheduler.h @@ -134,6 +134,9 @@ typedef enum { #ifdef USE_RANGEFINDER TASK_RANGEFINDER, #endif +#ifdef USE_OPTICALFLOW + TASK_OPTICALFLOW, +#endif #if defined(USE_BARO) || defined(USE_GPS) TASK_ALTITUDE, #endif diff --git a/src/main/sensors/initialisation.c b/src/main/sensors/initialisation.c index 99b9b74e61..f128df173b 100644 --- a/src/main/sensors/initialisation.c +++ b/src/main/sensors/initialisation.c @@ -45,10 +45,11 @@ #include "sensors/initialisation.h" #include "sensors/rangefinder.h" #include "sensors/sensors.h" +#include "sensors/opticalflow.h" // requestedSensors is not actually used -uint8_t requestedSensors[SENSOR_INDEX_COUNT] = { GYRO_NONE, ACC_NONE, BARO_NONE, MAG_NONE, RANGEFINDER_NONE }; -uint8_t detectedSensors[SENSOR_INDEX_COUNT] = { GYRO_NONE, ACC_NONE, BARO_NONE, MAG_NONE, RANGEFINDER_NONE }; +uint8_t requestedSensors[SENSOR_INDEX_COUNT] = { GYRO_NONE, ACC_NONE, BARO_NONE, MAG_NONE, RANGEFINDER_NONE, OPTICALFLOW_NONE}; +uint8_t detectedSensors[SENSOR_INDEX_COUNT] = { GYRO_NONE, ACC_NONE, BARO_NONE, MAG_NONE, RANGEFINDER_NONE, OPTICALFLOW_NONE}; void sensorsPreInit(void) { @@ -88,6 +89,10 @@ bool sensorsAutodetect(void) rangefinderInit(); #endif +#ifdef USE_OPTICALFLOW + opticalflowInit(); +#endif + #ifdef USE_ADC_INTERNAL adcInternalInit(); #endif diff --git a/src/main/sensors/opticalflow.c b/src/main/sensors/opticalflow.c new file mode 100644 index 0000000000..37f45161a7 --- /dev/null +++ b/src/main/sensors/opticalflow.c @@ -0,0 +1,196 @@ +/* + * This file is part of Betaflight. + * + * Betaflight is free software. You can redistribute this software + * and/or modify this software under the terms of the GNU General + * Public License as published by the Free Software Foundation, + * either version 3 of the License, or (at your option) any later + * version. + * + * Betaflight is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * See the GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this software. + * + * If not, see . + */ + + +#include +#include + +#include "platform.h" + +#ifdef USE_OPTICALFLOW + +#include "build/build_config.h" +#include "build/debug.h" + +#include "common/maths.h" +#include "common/time.h" +#include "common/utils.h" +#include "common/filter.h" + +#include "config/config.h" +#include "config/feature.h" + +#include "fc/runtime_config.h" + +#include "scheduler/scheduler.h" + +#include "pg/pg.h" +#include "pg/pg_ids.h" + +#include "drivers/time.h" +#include "drivers/rangefinder/rangefinder.h" +#include "drivers/rangefinder/rangefinder_lidarmt.h" + +#include "io/beeper.h" + +#include "sensors/sensors.h" +#include "sensors/gyro.h" +#include "sensors/acceleration.h" +#include "sensors/opticalflow.h" + +#define OPTICALFLOW_CALIBRATION_DURATION_MS 30000 +#define RATE_SCALE_RESOLUTION (1000.0f) + +// static prototypes +static void applySensorRotation(vector2_t * dst, vector2_t * src); +static void applyLPF(vector2_t * flowRates); + +PG_REGISTER_WITH_RESET_TEMPLATE(opticalflowConfig_t, opticalflowConfig, PG_OPTICALFLOW_CONFIG, 0); + +PG_RESET_TEMPLATE(opticalflowConfig_t, opticalflowConfig, + .opticalflow_hardware = OPTICALFLOW_NONE, + .rotation = 0, + .flow_lpf = 0, + .flip_x = 0 +); + +static opticalflow_t opticalflow; +float cosRotAngle = 1.0f; +float sinRotAngle = 0.0f; +static pt2Filter_t xFlowLpf, yFlowLpf; + +// ====================================================================== +// =================== Opticalflow Main Functions ======================= +// ====================================================================== +static bool opticalflowDetect(opticalflowDev_t * dev, uint8_t opticalflowHardwareToUse) { + UNUSED(dev); + + opticalflowType_e opticalflowHardware = OPTICALFLOW_NONE; + requestedSensors[SENSOR_INDEX_OPTICALFLOW] = opticalflowHardwareToUse; + + switch (opticalflowHardwareToUse) { + case OPTICALFLOW_MT: +#ifdef USE_RANGEFINDER_MT + if (mtOpticalflowDetect(dev, rangefinderConfig()->rangefinder_hardware)) { + opticalflowHardware = OPTICALFLOW_MT; + rescheduleTask(TASK_OPTICALFLOW, TASK_PERIOD_MS(dev->delayMs)); + } +#endif + break; + + case OPTICALFLOW_NONE: + opticalflowHardware = OPTICALFLOW_NONE; + break; + } + + if (opticalflowHardware == OPTICALFLOW_NONE) { + sensorsClear(SENSOR_OPTICALFLOW); + return false; + } + + detectedSensors[SENSOR_INDEX_OPTICALFLOW] = opticalflowHardware; + sensorsSet(SENSOR_OPTICALFLOW); + return true; +} + +bool opticalflowInit(void) { + if (!opticalflowDetect(&opticalflow.dev, opticalflowConfig()->opticalflow_hardware)) { + return false; + } + + opticalflow.dev.init(&opticalflow.dev); + opticalflow.quality = OPTICALFLOW_NO_NEW_DATA; + opticalflow.rawFlowRates.x = 0; + opticalflow.rawFlowRates.y = 0; + opticalflow.processedFlowRates.x = 0; + opticalflow.processedFlowRates.y = 0; + opticalflow.timeStampUs = micros(); + + cosRotAngle = cosf(DEGREES_TO_RADIANS(opticalflowConfig()->rotation)); + sinRotAngle = sinf(DEGREES_TO_RADIANS(opticalflowConfig()->rotation)); + //low pass filter + if (opticalflowConfig()->flow_lpf != 0) { + const float flowCutoffHz = (float)opticalflowConfig()->flow_lpf / 100.0f; + const float flowGain = pt2FilterGain(flowCutoffHz, opticalflow.dev.delayMs / 1000.0f); + + pt2FilterInit(&xFlowLpf, flowGain); + pt2FilterInit(&yFlowLpf, flowGain); + } + return true; +} + +void opticalflowUpdate(void) { + if (opticalflow.dev.update) { + opticalflow.dev.update(&opticalflow.dev); + } +} + +void opticalflowProcess(void) { + opticalflowData_t data = {0}; + uint32_t deltaTimeUs = 0; + opticalflow.dev.read(&opticalflow.dev, &data); + + opticalflow.quality = data.quality; + deltaTimeUs = cmp32(data.timeStampUs, opticalflow.timeStampUs); + + if (deltaTimeUs != 0) { // New data + vector2_t raw = data.flowRate; + vector2_t processed; + + applySensorRotation(&processed, &raw); + applyLPF(&processed); + + opticalflow.rawFlowRates = raw; + opticalflow.processedFlowRates = processed; + opticalflow.timeStampUs = data.timeStampUs; + + // DEBUG SECTION + DEBUG_SET(DEBUG_OPTICALFLOW, 0, opticalflow.quality); + DEBUG_SET(DEBUG_OPTICALFLOW, 1, lrintf(opticalflow.rawFlowRates.x * 1000)); + DEBUG_SET(DEBUG_OPTICALFLOW, 2, lrintf(opticalflow.rawFlowRates.y * 1000)); + DEBUG_SET(DEBUG_OPTICALFLOW, 3, lrintf(opticalflow.processedFlowRates.x * 1000)); + DEBUG_SET(DEBUG_OPTICALFLOW, 4, lrintf(opticalflow.processedFlowRates.y * 1000)); + DEBUG_SET(DEBUG_OPTICALFLOW, 5, deltaTimeUs); + } +} + +static void applySensorRotation(vector2_t * dst, vector2_t * src) { + dst->x = (opticalflowConfig()->flip_x ? -1.0f : 1.0f) * (src->x * cosRotAngle - src->y * sinRotAngle); + dst->y = src->x * sinRotAngle + src->y * cosRotAngle; +} + +static void applyLPF(vector2_t * flowRates) { + if (opticalflowConfig()->flow_lpf == 0) { + return; + } + + flowRates->x = pt2FilterApply(&xFlowLpf, flowRates->x); + flowRates->y = pt2FilterApply(&yFlowLpf, flowRates->y); +} + +const opticalflow_t * getLatestFlowOpticalflowData(void) { + return &opticalflow; +} + +bool isOpticalflowHealthy(void) { + return cmp32(micros(), opticalflow.timeStampUs) < OPTICALFLOW_HARDWARE_TIMEOUT_US; +} +#endif // USE_OPTICALFLOW diff --git a/src/main/sensors/opticalflow.h b/src/main/sensors/opticalflow.h new file mode 100644 index 0000000000..e715aeb3f0 --- /dev/null +++ b/src/main/sensors/opticalflow.h @@ -0,0 +1,56 @@ +/* + * This file is part of Betaflight. + * + * Betaflight is free software. You can redistribute this software + * and/or modify this software under the terms of the GNU General + * Public License as published by the Free Software Foundation, + * either version 3 of the License, or (at your option) any later + * version. + * + * Betaflight is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * See the GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this software. + * + * If not, see . + */ +#pragma once + +#include +#include + +#include "drivers/opticalflow/opticalflow.h" + +#include "pg/pg.h" + +typedef enum { + OPTICALFLOW_NONE = 0, + OPTICALFLOW_MT = 1, +} opticalflowType_e; + +typedef struct opticalflowConfig_s { + uint8_t opticalflow_hardware; + uint16_t rotation; + uint8_t flip_x; + uint16_t flow_lpf; +} opticalflowConfig_t; + +PG_DECLARE(opticalflowConfig_t, opticalflowConfig); + +typedef struct opticalflow_s { + opticalflowDev_t dev; + int16_t quality; + vector2_t rawFlowRates; + vector2_t processedFlowRates; + uint32_t timeStampUs; +} opticalflow_t; + +bool opticalflowInit(void); + +void opticalflowUpdate(void); +bool isOpticalflowHealthy(void); +void opticalflowProcess(void); diff --git a/src/main/sensors/sensors.h b/src/main/sensors/sensors.h index 80367d12f8..03c4b4a95c 100644 --- a/src/main/sensors/sensors.h +++ b/src/main/sensors/sensors.h @@ -26,6 +26,7 @@ typedef enum { SENSOR_INDEX_BARO, SENSOR_INDEX_MAG, SENSOR_INDEX_RANGEFINDER, + SENSOR_INDEX_OPTICALFLOW, SENSOR_INDEX_COUNT } sensorIndex_e; @@ -52,5 +53,6 @@ typedef enum { SENSOR_SONAR = 1 << 4, SENSOR_RANGEFINDER = 1 << 4, SENSOR_GPS = 1 << 5, - SENSOR_GPSMAG = 1 << 6 + SENSOR_GPSMAG = 1 << 6, + SENSOR_OPTICALFLOW = 1 << 7 } sensors_e; From 7f6475d3913e0faa8686611135c779b0e4f277d2 Mon Sep 17 00:00:00 2001 From: Mark Haslinghuis Date: Fri, 20 Dec 2024 22:20:09 +0100 Subject: [PATCH 007/244] STM32H5 timer definitions (#13685) --- src/platform/STM32/timer_stm32h5xx.c | 232 +++++++++++++++++++++++++++ 1 file changed, 232 insertions(+) create mode 100644 src/platform/STM32/timer_stm32h5xx.c diff --git a/src/platform/STM32/timer_stm32h5xx.c b/src/platform/STM32/timer_stm32h5xx.c new file mode 100644 index 0000000000..e4d06b9335 --- /dev/null +++ b/src/platform/STM32/timer_stm32h5xx.c @@ -0,0 +1,232 @@ +/* + * This file is part of Betaflight. + * + * Betaflight is free software. You can redistribute this software + * and/or modify this software under the terms of the GNU General + * Public License as published by the Free Software Foundation, + * either version 3 of the License, or (at your option) any later + * version. + * + * Betaflight is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * See the GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this software. + * + * If not, see . + */ + +#include "platform.h" + +#ifdef USE_TIMER + +#include "common/utils.h" + +#include "drivers/dma.h" +#include "drivers/io.h" +#include "timer_def.h" + +#include "stm32h5xx.h" +#include "drivers/rcc.h" +#include "drivers/timer.h" + +const timerDef_t timerDefinitions[HARDWARE_TIMER_DEFINITION_COUNT] = { + { .TIMx = TIM1, .rcc = RCC_APB2(TIM1), .inputIrq = TIM1_CC_IRQn}, + { .TIMx = TIM2, .rcc = RCC_APB1L(TIM2), .inputIrq = TIM2_IRQn}, + { .TIMx = TIM3, .rcc = RCC_APB1L(TIM3), .inputIrq = TIM3_IRQn}, + { .TIMx = TIM4, .rcc = RCC_APB1L(TIM4), .inputIrq = TIM4_IRQn}, + { .TIMx = TIM5, .rcc = RCC_APB1L(TIM5), .inputIrq = TIM5_IRQn}, + { .TIMx = TIM6, .rcc = RCC_APB1L(TIM6), .inputIrq = TIM6_DAC_IRQn}, + { .TIMx = TIM7, .rcc = RCC_APB1L(TIM7), .inputIrq = TIM7_IRQn}, + { .TIMx = TIM8, .rcc = RCC_APB2(TIM8), .inputIrq = TIM8_CC_IRQn}, + { .TIMx = TIM12, .rcc = RCC_APB1L(TIM12), .inputIrq = TIM8_BRK_TIM12_IRQn}, + { .TIMx = TIM13, .rcc = RCC_APB1L(TIM13), .inputIrq = TIM8_UP_TIM13_IRQn}, + { .TIMx = TIM14, .rcc = RCC_APB1L(TIM14), .inputIrq = TIM8_TRG_COM_TIM14_IRQn}, + { .TIMx = TIM15, .rcc = RCC_APB2(TIM15), .inputIrq = TIM15_IRQn}, + { .TIMx = TIM16, .rcc = RCC_APB2(TIM16), .inputIrq = TIM16_IRQn}, + { .TIMx = TIM17, .rcc = RCC_APB2(TIM17), .inputIrq = TIM17_IRQn}, +}; + +#if defined(USE_TIMER_MGMT) +const timerHardware_t fullTimerHardware[FULL_TIMER_CHANNEL_COUNT] = { +// Auto-generated from 'timer_def.h' +// Port A + DEF_TIM(TIM2, CH1, PA0, 0, 0, 0), // AF1 + DEF_TIM(TIM2, CH2, PA1, 0, 0, 0), + DEF_TIM(TIM2, CH3, PA2, 0, 0, 0), + DEF_TIM(TIM2, CH4, PA3, 0, 0, 0), + DEF_TIM(TIM2, CH1, PA5, 0, 0, 0), + DEF_TIM(TIM1, CH1N, PA7, 0, 0, 0), + DEF_TIM(TIM1, CH1, PA8, 0, 0, 0), + DEF_TIM(TIM1, CH2, PA9, 0, 0, 0), + DEF_TIM(TIM1, CH3, PA10, 0, 0, 0), + DEF_TIM(TIM1, CH4, PA11, 0, 0, 0), + DEF_TIM(TIM2, CH1, PA15, 0, 0, 0), + + DEF_TIM(TIM5, CH1, PA0, 0, 0, 0), // AF2 + DEF_TIM(TIM5, CH2, PA1, 0, 0, 0), + DEF_TIM(TIM5, CH3, PA2, 0, 0, 0), + DEF_TIM(TIM5, CH4, PA3, 0, 0, 0), + DEF_TIM(TIM3, CH1, PA6, 0, 0, 0), + DEF_TIM(TIM3, CH2, PA7, 0, 0, 0), + + DEF_TIM(TIM8, CH1N, PA5, 0, 0, 0), // AF3 + DEF_TIM(TIM8, CH1N, PA7, 0, 0, 0), + + DEF_TIM(TIM13, CH1, PA6, 0, 0, 0), // AF9 + DEF_TIM(TIM14, CH1, PA7, 0, 0, 0), + + DEF_TIM(TIM15, CH1N, PA1, 0, 0, 0), // AF4 + DEF_TIM(TIM15, CH1, PA2, 0, 0, 0), + DEF_TIM(TIM15, CH2, PA3, 0, 0, 0), + +// Port B + DEF_TIM(TIM1, CH2N, PB0, 0, 0, 0), // AF1 + DEF_TIM(TIM1, CH3N, PB1, 0, 0, 0), + DEF_TIM(TIM2, CH2, PB3, 0, 0, 0), + DEF_TIM(TIM16, CH1N, PB6, 0, 0, 0), + DEF_TIM(TIM17, CH1N, PB7, 0, 0, 0), + DEF_TIM(TIM16, CH1, PB8, 0, 0, 0), + DEF_TIM(TIM17, CH1, PB9, 0, 0, 0), + DEF_TIM(TIM2, CH3, PB10, 0, 0, 0), + DEF_TIM(TIM2, CH4, PB11, 0, 0, 0), + DEF_TIM(TIM1, CH1N, PB13, 0, 0, 0), + DEF_TIM(TIM1, CH2N, PB14, 0, 0, 0), + DEF_TIM(TIM1, CH3N, PB15, 0, 0, 0), + + DEF_TIM(TIM3, CH3, PB0, 0, 0, 0), // AF2 + DEF_TIM(TIM3, CH4, PB1, 0, 0, 0), + DEF_TIM(TIM3, CH1, PB4, 0, 0, 0), + DEF_TIM(TIM3, CH2, PB5, 0, 0, 0), + DEF_TIM(TIM4, CH1, PB6, 0, 0, 0), + DEF_TIM(TIM4, CH2, PB7, 0, 0, 0), + DEF_TIM(TIM4, CH3, PB8, 0, 0, 0), + DEF_TIM(TIM4, CH4, PB9, 0, 0, 0), + + // DEF_TIM(TIM12, CH1, PB14, 0, 0, 0), // AF9 (SDMMC2_D0) + // DEF_TIM(TIM12, CH2, PB15, 0, 0, 0), // AF9 (SDMMC2_D1) + +// Port C + DEF_TIM(TIM3, CH1, PC6, 0, 0, 0), // AF2 + DEF_TIM(TIM3, CH2, PC7, 0, 0, 0), + DEF_TIM(TIM3, CH3, PC8, 0, 0, 0), + DEF_TIM(TIM3, CH4, PC9, 0, 0, 0), + + DEF_TIM(TIM8, CH1, PC6, 0, 0, 0), // AF3 + DEF_TIM(TIM8, CH2, PC7, 0, 0, 0), + DEF_TIM(TIM8, CH3, PC8, 0, 0, 0), + DEF_TIM(TIM8, CH4, PC9, 0, 0, 0), + +// Port D + DEF_TIM(TIM1, CH4N, PD5, 0, 0, 0), // AF1 (ADDED) + + DEF_TIM(TIM4, CH1, PD12, 0, 0, 0), // AF2 + DEF_TIM(TIM4, CH2, PD13, 0, 0, 0), + DEF_TIM(TIM4, CH3, PD14, 0, 0, 0), + DEF_TIM(TIM4, CH4, PD15, 0, 0, 0), + +// Port E + DEF_TIM(TIM1, CH1N, PE8, 0, 0, 0), // AF1 + DEF_TIM(TIM1, CH1, PE9, 0, 0, 0), + DEF_TIM(TIM1, CH2N, PE10, 0, 0, 0), + DEF_TIM(TIM1, CH2, PE11, 0, 0, 0), + DEF_TIM(TIM1, CH3N, PE12, 0, 0, 0), + DEF_TIM(TIM1, CH3, PE13, 0, 0, 0), + DEF_TIM(TIM1, CH4, PE14, 0, 0, 0), + + DEF_TIM(TIM1, CH4N, PE15, 0, 0, 0), // AF3 (ADDED) + + DEF_TIM(TIM15, CH1N, PE4, 0, 0, 0), // AF4 + DEF_TIM(TIM15, CH1, PE5, 0, 0, 0), + DEF_TIM(TIM15, CH2, PE6, 0, 0, 0), + +// Port F + DEF_TIM(TIM16, CH1, PF6, 0, 0, 0), // AF1 + DEF_TIM(TIM17, CH1, PF7, 0, 0, 0), + DEF_TIM(TIM16, CH1N, PF8, 0, 0, 0), // AF3 + DEF_TIM(TIM17, CH1N, PF9, 0, 0, 0), + + DEF_TIM(TIM13, CH1, PF8, 0, 0, 0), // AF9 (WAS TIM13_CH1N) + DEF_TIM(TIM14, CH1, PF9, 0, 0, 0), // AF9 (WAS TIM14_CH1N) + +// Port H + + DEF_TIM(TIM1, CHN3, PH6, 0, 0, 0), // AF1 (ADDED) + DEF_TIM(TIM1, CH3, PH7, 0, 0, 0), + DEF_TIM(TIM1, CHN2, PH8, 0, 0, 0), + DEF_TIM(TIM1, CH2, PH9, 0, 0, 0), + DEF_TIM(TIM1, CHN1, PH10, 0, 0, 0), + DEF_TIM(TIM1, CH1, PH11, 0, 0, 0), + + DEF_TIM(TIM12, CH1, PH6, 0, 0, 0), // AF2 (ADDED) + DEF_TIM(TIM12, CH2, PH9, 0, 0, 0), + DEF_TIM(TIM5, CH1, PH10, 0, 0, 0), + DEF_TIM(TIM5, CH2, PH11, 0, 0, 0), + DEF_TIM(TIM5, CH3, PH12, 0, 0, 0), + + DEF_TIM(TIM8, CH1, PH6, 0, 0, 0), // AF3 (ADDED) + DEF_TIM(TIM8, CH1N, PH7, 0, 0, 0), + DEF_TIM(TIM8, CH2, PH8, 0, 0, 0), + DEF_TIM(TIM8, CH2N, PH9, 0, 0, 0), + DEF_TIM(TIM8, CH3, PH10, 0, 0, 0), + DEF_TIM(TIM8, CH3N, PH11, 0, 0, 0), + DEF_TIM(TIM8, CH1N, PH13, 0, 0, 0), + DEF_TIM(TIM8, CH2N, PH14, 0, 0, 0), + DEF_TIM(TIM8, CH3N, PH15, 0, 0, 0), + +// Port I + DEF_TIM(TIM5, CH4, PI0, 0, 0, 0), // AF2 (ADDED) + + DEF_TIM(TIM8, CH4, PI2, 0, 0, 0), // AF3 (ADDED) + DEF_TIM(TIM8, CH1, PI5, 0, 0, 0), + DEF_TIM(TIM8, CH2, PI6, 0, 0, 0), + DEF_TIM(TIM8, CH3, PI7, 0, 0, 0), +}; +#endif + + +uint32_t timerClock(const TIM_TypeDef *tim) +{ + int timpre; + uint32_t pclk; + uint32_t ppre; + + // This function is used to calculate the timer clock frequency. + // RM0481 (Rev 3) Table + + + RCC_ClkInitTypeDef clkConfig, uint32_t fLatency + HAL_RCC_GetClockConfig(&clkConfig, &fLatency); + + if ((uintptr_t)tim >= APB2PERIPH_BASE ) { // APB2 + pclk = HAL_RCC_GetPCLK2Freq(); + ppre = clkConfig.APB2CLKDivider; + } else { // all other timers are on APB1 + pclk = HAL_RCC_GetPCLK1Freq(); + ppre = clkConfig.APB1CLKDivider; + } + timpre = (RCC->CFGR & RCC_CFGR_TIMPRE) ? 1 : 0; +#define PC(m) (0x80 | (m)) // multiply pclk +#define HC(m) (0x00 | (m)) // multiply hclk + static const uint8_t timpreTab[2][8] = { // see RM0481 TIMPRE: timers clocks prescaler selection + // 1 1 1 1 2 4 8 16 + { HC(1), HC(1), HC(1), HC(1), HC(1), PC(2), PC(2), PC(2) }, // TIMPRE = 0 + { PC(2), PC(2), PC(2), PC(2), PC(2), PC(2), PC(4), PC(4) } // TIMPRE = 1 + } +#undef PC +#undef HC + int flagMult = timpreTab[timpre][ppre]; + + if (flagMult & 0x80) { // PCLK based + return pclk * (flagMult & 0x7f); + } else { + return HAL_RCC_GetHCLKFreq() * (flagMult & 0x7f); + } + + return pclk * periphToKernel[timpre][ppre]; + +} +#endif From cab60b65945b6c277a82d83772009fd321c3b869 Mon Sep 17 00:00:00 2001 From: Mark Haslinghuis Date: Fri, 20 Dec 2024 22:34:01 +0100 Subject: [PATCH 008/244] Add RANGEFINDER and OPTICALFLOW MT build option (#14042) --- src/main/target/common_post.h | 20 +++++++++++++------- src/main/target/common_pre.h | 3 ++- 2 files changed, 15 insertions(+), 8 deletions(-) diff --git a/src/main/target/common_post.h b/src/main/target/common_post.h index 37a55e7723..508453ab7e 100644 --- a/src/main/target/common_post.h +++ b/src/main/target/common_post.h @@ -555,14 +555,20 @@ #undef USED_TIMERS #endif -#if !defined(USE_RANGEFINDER) -#undef USE_RANGEFINDER_HCSR04 -#undef USE_RANGEFINDER_SRF10 -#undef USE_RANGEFINDER_HCSR04_I2C -#undef USE_RANGEFINDER_VL53L0X -#undef USE_RANGEFINDER_UIB -#undef USE_RANGEFINDER_TF +#if defined(USE_OPTICALFLOW_MT) +#ifndef USE_RANGEFINDER_MT +#define USE_RANGEFINDER_MT #endif +#ifndef USE_OPTICALFLOW +#define USE_OPTICALFLOW +#endif +#endif // USE_OPTICALFLOW_MT + +#if defined(USE_RANGEFINDER_HCSR04) || defined(USE_RANGEFINDER_SRF10) || defined(USE_RANGEFINDER_HCSR04_I2C) || defined(USE_RANGEFINDER_VL53L0X) || defined(USE_RANGEFINDER_UIB) || defined(USE_RANGEFINDER_TF) || defined(USE_RANGEFINDER_MT) +#ifndef USE_RANGEFINDER +#define USE_RANGEFINDER +#endif +#endif // USE_RANGEFINDER_XXX #ifndef USE_GPS_RESCUE #undef USE_CMS_GPS_RESCUE_MENU diff --git a/src/main/target/common_pre.h b/src/main/target/common_pre.h index 0e7e6545d3..505e48656c 100644 --- a/src/main/target/common_pre.h +++ b/src/main/target/common_pre.h @@ -270,8 +270,9 @@ #define USE_RANGEFINDER #define USE_RANGEFINDER_HCSR04 #define USE_RANGEFINDER_TF +#define USE_OPTICALFLOW_MT -#endif // TARGET_FLASH_SIZE > 512 +#endif // TARGET_FLASH_SIZE >= 1024 #endif // !defined(CLOUD_BUILD) From ac82d8b9982f57dcba713b9709f63e2f7cf713a5 Mon Sep 17 00:00:00 2001 From: Petr Ledvina Date: Sun, 22 Dec 2024 05:44:08 +0100 Subject: [PATCH 009/244] Refactoring of PR 13050 - support for custom OSD messages from external device (#14097) --- mk/source.mk | 1 + src/main/blackbox/blackbox.c | 3 +- src/main/cli/cli.c | 1 + src/main/cli/settings.c | 1 + src/main/config/config.c | 7 ---- src/main/config/config.h | 9 ----- src/main/msp/msp.c | 44 +++++++++++++---------- src/main/msp/msp_protocol_v2_betaflight.h | 3 ++ src/main/osd/osd.h | 4 +++ src/main/osd/osd_elements.c | 21 +++++++++++ src/main/pg/pilot.c | 38 ++++++++++++++++++++ src/main/pg/pilot.h | 35 ++++++++++++++++++ src/test/unit/cli_unittest.cc | 1 + src/test/unit/link_quality_unittest.cc | 1 + src/test/unit/osd_unittest.cc | 1 + 15 files changed, 135 insertions(+), 35 deletions(-) create mode 100644 src/main/pg/pilot.c create mode 100644 src/main/pg/pilot.h diff --git a/mk/source.mk b/mk/source.mk index 70e4d00b57..c28a739577 100644 --- a/mk/source.mk +++ b/mk/source.mk @@ -22,6 +22,7 @@ PG_SRC = \ pg/motor.c \ pg/msp.c \ pg/pg.c \ + pg/pilot.c \ pg/piniobox.c \ pg/pinio.c \ pg/pin_pull_up_down.c \ diff --git a/src/main/blackbox/blackbox.c b/src/main/blackbox/blackbox.c index de74df3c30..89fa7a2632 100644 --- a/src/main/blackbox/blackbox.c +++ b/src/main/blackbox/blackbox.c @@ -81,8 +81,9 @@ #include "pg/alt_hold.h" #include "pg/autopilot.h" #include "pg/motor.h" -#include "pg/rx.h" +#include "pg/pilot.h" #include "pg/pos_hold.h" +#include "pg/rx.h" #include "rx/rx.h" diff --git a/src/main/cli/cli.c b/src/main/cli/cli.c index 926b5ada5a..46e2f9e325 100644 --- a/src/main/cli/cli.c +++ b/src/main/cli/cli.c @@ -139,6 +139,7 @@ bool cliMode = false; #include "pg/max7456.h" #include "pg/mco.h" #include "pg/motor.h" +#include "pg/pilot.h" #include "pg/pinio.h" #include "pg/pin_pull_up_down.h" #include "pg/pg.h" diff --git a/src/main/cli/settings.c b/src/main/cli/settings.c index fc4e9a703a..95406b6a91 100644 --- a/src/main/cli/settings.c +++ b/src/main/cli/settings.c @@ -95,6 +95,7 @@ #include "pg/msp.h" #include "pg/pg.h" #include "pg/pg_ids.h" +#include "pg/pilot.h" #include "pg/pinio.h" #include "pg/piniobox.h" #include "pg/pos_hold.h" diff --git a/src/main/config/config.c b/src/main/config/config.c index de895e7484..aedfdb12d1 100644 --- a/src/main/config/config.c +++ b/src/main/config/config.c @@ -106,13 +106,6 @@ pidProfile_t *currentPidProfile; #define RX_SPI_DEFAULT_PROTOCOL 0 #endif -PG_REGISTER_WITH_RESET_TEMPLATE(pilotConfig_t, pilotConfig, PG_PILOT_CONFIG, 2); - -PG_RESET_TEMPLATE(pilotConfig_t, pilotConfig, - .craftName = { 0 }, - .pilotName = { 0 }, -); - PG_REGISTER_WITH_RESET_TEMPLATE(systemConfig_t, systemConfig, PG_SYSTEM_CONFIG, 3); PG_RESET_TEMPLATE(systemConfig_t, systemConfig, diff --git a/src/main/config/config.h b/src/main/config/config.h index 94118a8611..17f35ee36c 100644 --- a/src/main/config/config.h +++ b/src/main/config/config.h @@ -25,20 +25,11 @@ #include "pg/pg.h" -#define MAX_NAME_LENGTH 16u - typedef enum { CONFIGURATION_STATE_UNCONFIGURED = 0, CONFIGURATION_STATE_CONFIGURED, } configurationState_e; -typedef struct pilotConfig_s { - char craftName[MAX_NAME_LENGTH + 1]; - char pilotName[MAX_NAME_LENGTH + 1]; -} pilotConfig_t; - -PG_DECLARE(pilotConfig_t, pilotConfig); - typedef struct systemConfig_s { uint8_t pidProfileIndex; uint8_t activeRateProfile; diff --git a/src/main/msp/msp.c b/src/main/msp/msp.c index dcb6df0f75..31ff012e62 100644 --- a/src/main/msp/msp.c +++ b/src/main/msp/msp.c @@ -124,6 +124,7 @@ #include "pg/gps_rescue.h" #include "pg/gyrodev.h" #include "pg/motor.h" +#include "pg/pilot.h" #include "pg/pos_hold.h" #include "pg/rx.h" #include "pg/rx_spi.h" @@ -1158,12 +1159,7 @@ static bool mspProcessOutCommand(mspDescriptor_t srcDesc, int16_t cmdMSP, sbuf_t break; case MSP_NAME: - { - const int nameLen = strlen(pilotConfig()->craftName); - for (int i = 0; i < nameLen; i++) { - sbufWriteU8(dst, pilotConfig()->craftName[i]); - } - } + sbufWriteString(dst, pilotConfig()->craftName); break; #ifdef USE_SERVOS @@ -2610,9 +2606,7 @@ static mspResult_e mspFcProcessOutCommandWithArg(mspDescriptor_t srcDesc, int16_ // type byte, then length byte followed by the actual characters sbufWriteU8(dst, textType); sbufWriteU8(dst, textLength); - for (unsigned int i = 0; i < textLength; i++) { - sbufWriteU8(dst, textVar[i]); - } + sbufWriteData(dst, textVar, textLength); } break; #ifdef USE_LED_STRIP @@ -3985,10 +3979,8 @@ static mspResult_e mspProcessInCommand(mspDescriptor_t srcDesc, int16_t cmdMSP, #endif case MSP_SET_NAME: - memset(pilotConfigMutable()->craftName, 0, ARRAYLEN(pilotConfig()->craftName)); - for (unsigned int i = 0; i < MIN(MAX_NAME_LENGTH, dataSize); i++) { - pilotConfigMutable()->craftName[i] = sbufReadU8(src); - } + memset(pilotConfigMutable()->craftName, 0, sizeof(pilotConfigMutable()->craftName)); + sbufReadData(src, pilotConfigMutable()->craftName, MIN(ARRAYLEN(pilotConfigMutable()->craftName) - 1, dataSize)); #ifdef USE_OSD osdAnalyzeActiveElements(); #endif @@ -4068,35 +4060,51 @@ static mspResult_e mspProcessInCommand(mspDescriptor_t srcDesc, int16_t cmdMSP, case MSP2_SET_TEXT: { // type byte, then length byte followed by the actual characters - const uint8_t textType = sbufReadU8(src); + const unsigned textType = sbufReadU8(src); char* textVar; - const uint8_t textLength = MIN(MAX_NAME_LENGTH, sbufReadU8(src)); + unsigned textSpace; switch (textType) { case MSP2TEXT_PILOT_NAME: textVar = pilotConfigMutable()->pilotName; + textSpace = sizeof(pilotConfigMutable()->pilotName) - 1; break; case MSP2TEXT_CRAFT_NAME: textVar = pilotConfigMutable()->craftName; + textSpace = sizeof(pilotConfigMutable()->craftName) - 1; break; case MSP2TEXT_PID_PROFILE_NAME: textVar = currentPidProfile->profileName; + textSpace = sizeof(currentPidProfile->profileName) - 1; break; case MSP2TEXT_RATE_PROFILE_NAME: textVar = currentControlRateProfile->profileName; + textSpace = sizeof(currentControlRateProfile->profileName) - 1; break; + case MSP2TEXT_CUSTOM_MSG_0: + case MSP2TEXT_CUSTOM_MSG_0 + 1: + case MSP2TEXT_CUSTOM_MSG_0 + 2: + case MSP2TEXT_CUSTOM_MSG_0 + 3: { + unsigned msgIdx = textType - MSP2TEXT_CUSTOM_MSG_0; + if (msgIdx < OSD_CUSTOM_MSG_COUNT) { + textVar = pilotConfigMutable()->message[msgIdx]; + textSpace = sizeof(pilotConfigMutable()->message[msgIdx]) - 1; + } else { + return MSP_RESULT_ERROR; + } + break; + } default: return MSP_RESULT_ERROR; } + const unsigned textLength = MIN(textSpace, sbufReadU8(src)); memset(textVar, 0, strlen(textVar)); - for (unsigned int i = 0; i < textLength; i++) { - textVar[i] = sbufReadU8(src); - } + sbufReadData(src, textVar, textLength); #ifdef USE_OSD if (textType == MSP2TEXT_PILOT_NAME || textType == MSP2TEXT_CRAFT_NAME) { diff --git a/src/main/msp/msp_protocol_v2_betaflight.h b/src/main/msp/msp_protocol_v2_betaflight.h index f96cd6a817..beefb27f2f 100644 --- a/src/main/msp/msp_protocol_v2_betaflight.h +++ b/src/main/msp/msp_protocol_v2_betaflight.h @@ -38,3 +38,6 @@ #define MSP2TEXT_RATE_PROFILE_NAME 4 #define MSP2TEXT_BUILDKEY 5 #define MSP2TEXT_RELEASENAME 6 +#define MSP2TEXT_CUSTOM_MSG_0 7 // CUSTOM_MSG_MAX_NUM entries are allocated +#define CUSTOM_MSG_MAX_NUM 4 +// next new variable type must be >= MSP2TEXT_CUSTOM_MSG_0 + CUSTOM_MSG_MAX_NUM (11) diff --git a/src/main/osd/osd.h b/src/main/osd/osd.h index c7cfbc19d5..c311bb1f45 100644 --- a/src/main/osd/osd.h +++ b/src/main/osd/osd.h @@ -190,6 +190,10 @@ typedef enum { OSD_GPS_LAP_TIME_PREVIOUS, OSD_GPS_LAP_TIME_BEST3, OSD_DEBUG2, + OSD_CUSTOM_MSG0, + OSD_CUSTOM_MSG1, + OSD_CUSTOM_MSG2, + OSD_CUSTOM_MSG3, OSD_ITEM_COUNT // MUST BE LAST } osd_items_e; diff --git a/src/main/osd/osd_elements.c b/src/main/osd/osd_elements.c index 51e43cff53..23ddd5c9e4 100644 --- a/src/main/osd/osd_elements.c +++ b/src/main/osd/osd_elements.c @@ -161,6 +161,7 @@ #include "osd/osd_warnings.h" #include "pg/motor.h" +#include "pg/pilot.h" #include "pg/stats.h" #include "rx/rx.h" @@ -810,6 +811,18 @@ static void osdElementCompassBar(osdElementParms_t *element) element->buff[9] = 0; } +//display custom message from MSPv2 +static void osdElementCustomMsg(osdElementParms_t *element) +{ + int msgIndex = element->item - OSD_CUSTOM_MSG0; + if (msgIndex < 0 || msgIndex >= OSD_CUSTOM_MSG_COUNT || pilotConfig()->message[msgIndex][0] == '\0') { + tfp_sprintf(element->buff, "CUSTOM_MSG%d", msgIndex + 1); + } else { + strncpy(element->buff, pilotConfig()->message[msgIndex], MAX_NAME_LENGTH); + element->buff[MAX_NAME_LENGTH] = 0; // terminate maximum-length string + } +} + #ifdef USE_ADC_INTERNAL static void osdElementCoreTemperature(osdElementParms_t *element) { @@ -1804,6 +1817,10 @@ static const uint8_t osdElementDisplayOrder[] = { OSD_MAH_DRAWN, OSD_WATT_HOURS_DRAWN, OSD_CRAFT_NAME, + OSD_CUSTOM_MSG0, + OSD_CUSTOM_MSG1, + OSD_CUSTOM_MSG2, + OSD_CUSTOM_MSG3, OSD_ALTITUDE, OSD_ROLL_PIDS, OSD_PITCH_PIDS, @@ -1902,6 +1919,10 @@ const osdElementDrawFn osdElementDrawFunction[OSD_ITEM_COUNT] = { [OSD_ITEM_TIMER_2] = osdElementTimer, [OSD_FLYMODE] = osdElementFlymode, [OSD_CRAFT_NAME] = NULL, // only has background + [OSD_CUSTOM_MSG0] = osdElementCustomMsg, + [OSD_CUSTOM_MSG1] = osdElementCustomMsg, + [OSD_CUSTOM_MSG2] = osdElementCustomMsg, + [OSD_CUSTOM_MSG3] = osdElementCustomMsg, [OSD_THROTTLE_POS] = osdElementThrottlePosition, #ifdef USE_VTX_COMMON [OSD_VTX_CHANNEL] = osdElementVtxChannel, diff --git a/src/main/pg/pilot.c b/src/main/pg/pilot.c new file mode 100644 index 0000000000..4691cd00a4 --- /dev/null +++ b/src/main/pg/pilot.c @@ -0,0 +1,38 @@ +/* + * This file is part of Betaflight. + * + * Betaflight is free software. You can redistribute this software + * and/or modify this software under the terms of the GNU General + * Public License as published by the Free Software Foundation, + * either version 3 of the License, or (at your option) any later + * version. + * + * Betaflight is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * See the GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this software. + * + * If not, see . + */ + +#include +#include + +#include "platform.h" + +#include "pg/pg.h" +#include "pg/pg_ids.h" + +#include "pilot.h" + +PG_REGISTER_WITH_RESET_TEMPLATE(pilotConfig_t, pilotConfig, PG_PILOT_CONFIG, 2); + +PG_RESET_TEMPLATE(pilotConfig_t, pilotConfig, + .craftName = { 0 }, + .pilotName = { 0 }, + .message = { {0} }, +); diff --git a/src/main/pg/pilot.h b/src/main/pg/pilot.h new file mode 100644 index 0000000000..644016f7c0 --- /dev/null +++ b/src/main/pg/pilot.h @@ -0,0 +1,35 @@ +/* + * This file is part of Betaflight. + * + * Betaflight is free software. You can redistribute this software + * and/or modify this software under the terms of the GNU General + * Public License as published by the Free Software Foundation, + * either version 3 of the License, or (at your option) any later + * version. + * + * Betaflight is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * See the GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this software. + * + * If not, see . + */ + +#pragma once + +#include "pg/pg.h" + +#define MAX_NAME_LENGTH 16u +#define OSD_CUSTOM_MSG_COUNT 4 + +typedef struct pilotConfig_s { + char craftName[MAX_NAME_LENGTH + 1]; + char pilotName[MAX_NAME_LENGTH + 1]; + char message[OSD_CUSTOM_MSG_COUNT][MAX_NAME_LENGTH + 1]; +} pilotConfig_t; + +PG_DECLARE(pilotConfig_t, pilotConfig); diff --git a/src/test/unit/cli_unittest.cc b/src/test/unit/cli_unittest.cc index cb3243a771..63362e630f 100644 --- a/src/test/unit/cli_unittest.cc +++ b/src/test/unit/cli_unittest.cc @@ -53,6 +53,7 @@ extern "C" { #include "pg/pg_ids.h" #include "pg/beeper.h" #include "pg/gps.h" + #include "pg/pilot.h" #include "pg/rx.h" #include "rx/rx.h" #include "scheduler/scheduler.h" diff --git a/src/test/unit/link_quality_unittest.cc b/src/test/unit/link_quality_unittest.cc index c7eb278496..c01de00455 100644 --- a/src/test/unit/link_quality_unittest.cc +++ b/src/test/unit/link_quality_unittest.cc @@ -61,6 +61,7 @@ extern "C" { #include "pg/pg.h" #include "pg/pg_ids.h" + #include "pg/pilot.h" #include "pg/rx.h" #include "rx/rx.h" diff --git a/src/test/unit/osd_unittest.cc b/src/test/unit/osd_unittest.cc index 0812c863cc..d11230d42b 100644 --- a/src/test/unit/osd_unittest.cc +++ b/src/test/unit/osd_unittest.cc @@ -58,6 +58,7 @@ extern "C" { #include "pg/gps_rescue.h" #include "pg/pg.h" #include "pg/pg_ids.h" + #include "pg/pilot.h" #include "pg/rx.h" #include "sensors/acceleration.h" From 00bcbdd89706204e59776ab8ed26fced0a19cc18 Mon Sep 17 00:00:00 2001 From: Thomas Stibor Date: Sun, 22 Dec 2024 21:29:11 +0100 Subject: [PATCH 010/244] Fix typo in Makefile for populating configuration targets (#14100) --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 827e74632f..bc678ee99d 100644 --- a/Makefile +++ b/Makefile @@ -642,7 +642,7 @@ help: Makefile mk/tools.mk @echo "Or:" @echo " make [V=] [OPTIONS=\"\"] [EXTRA_FLAGS=\"\"]" @echo "" - @echo "To pupulate configuration targets:" + @echo "To populate configuration targets:" @echo " make configs" @echo "" @echo "Valid TARGET values are: $(BASE_TARGETS)" From d22d8405c2c04365acb30e8ee226bd7bb71b591f Mon Sep 17 00:00:00 2001 From: jpmreece Date: Mon, 23 Dec 2024 20:28:43 +0000 Subject: [PATCH 011/244] LED Dimmer (#13776) * LED Dimmer Build with EXTRA_FLAGS=-DUSE_LED_STRIP Tested on SpeedyBeeF7V3 Added adjrange to update the ledstrip_brightness variable. This allows for easy changing of LEDs without having to connect to the configurator. * Added Unit Tests, Space to Tab Added unit tests into rx_controls_unittest.cc. The LED brightness is returned as 50 for testing purposes. Changed tabs in ledstrip.c & .h and rc_adjustments.c to 4 spaces for coding standards. * Update src/main/fc/rc_adjustments.h Missed a tab in rc_adjustments.h Co-authored-by: nerdCopter <56646290+nerdCopter@users.noreply.github.com> * Update src/main/fc/rc_adjustments.c Removal of empty line Co-authored-by: nerdCopter <56646290+nerdCopter@users.noreply.github.com> * Update rc_adjustments.c Co-authored-by: Petr Ledvina * Update src/main/io/ledstrip.c * Update src/main/io/ledstrip.h * Update src/test/unit/rc_controls_unittest.cc --------- Co-authored-by: nerdCopter <56646290+nerdCopter@users.noreply.github.com> Co-authored-by: Jay Blackman Co-authored-by: Petr Ledvina Co-authored-by: Mark Haslinghuis --- src/main/fc/rc_adjustments.c | 13 +++++++++++++ src/main/fc/rc_adjustments.h | 1 + src/main/io/ledstrip.c | 12 ++++++++++++ src/main/io/ledstrip.h | 2 ++ src/test/unit/rc_controls_unittest.cc | 2 ++ 5 files changed, 30 insertions(+) diff --git a/src/main/fc/rc_adjustments.c b/src/main/fc/rc_adjustments.c index 04c96c0c2b..8e838b97be 100644 --- a/src/main/fc/rc_adjustments.c +++ b/src/main/fc/rc_adjustments.c @@ -226,6 +226,10 @@ static const adjustmentConfig_t defaultAdjustmentConfigs[ADJUSTMENT_FUNCTION_COU .adjustmentFunction = ADJUSTMENT_LED_PROFILE, .mode = ADJUSTMENT_MODE_SELECT, .data = { .switchPositions = 3 } + }, { + .adjustmentFunction = ADJUSTMENT_LED_DIMMER, + .mode = ADJUSTMENT_MODE_SELECT, + .data = { .switchPositions = 100 } } }; @@ -264,6 +268,8 @@ static const char * const adjustmentLabels[] = { "ROLL F", "YAW F", "OSD PROFILE", + "LED PROFILE", + "LED DIMMER", }; static int adjustmentRangeNameIndex = 0; @@ -641,6 +647,13 @@ static uint8_t applySelectAdjustment(adjustmentFunction_e adjustmentFunction, ui if (getLedProfile() != position) { setLedProfile(position); } +#endif + break; + case ADJUSTMENT_LED_DIMMER: +#ifdef USE_LED_STRIP + if (getLedBrightness() != position) { + setLedBrightness(position); + } #endif break; diff --git a/src/main/fc/rc_adjustments.h b/src/main/fc/rc_adjustments.h index 669205f554..57855ba24e 100644 --- a/src/main/fc/rc_adjustments.h +++ b/src/main/fc/rc_adjustments.h @@ -62,6 +62,7 @@ typedef enum { ADJUSTMENT_YAW_F, ADJUSTMENT_OSD_PROFILE, ADJUSTMENT_LED_PROFILE, + ADJUSTMENT_LED_DIMMER, ADJUSTMENT_FUNCTION_COUNT } adjustmentFunction_e; diff --git a/src/main/io/ledstrip.c b/src/main/io/ledstrip.c index 1f6ec0d45b..03dd8b4bf7 100644 --- a/src/main/io/ledstrip.c +++ b/src/main/io/ledstrip.c @@ -1588,4 +1588,16 @@ void setLedProfile(uint8_t profile) ledStripConfigMutable()->ledstrip_profile = profile; } } + +uint8_t getLedBrightness(void) +{ + return ledStripConfig()->ledstrip_brightness; +} + +void setLedBrightness(uint8_t brightness) +{ + if ( brightness <= 100 ) { + ledStripConfigMutable()->ledstrip_brightness = brightness; + } +} #endif diff --git a/src/main/io/ledstrip.h b/src/main/io/ledstrip.h index fc6d467a6c..8e6aaccf17 100644 --- a/src/main/io/ledstrip.h +++ b/src/main/io/ledstrip.h @@ -239,3 +239,5 @@ void updateRequiredOverlay(void); uint8_t getLedProfile(void); void setLedProfile(uint8_t profile); +uint8_t getLedBrightness(void); +void setLedBrightness(uint8_t brightness); diff --git a/src/test/unit/rc_controls_unittest.cc b/src/test/unit/rc_controls_unittest.cc index 7be5ff2c60..862c43119d 100644 --- a/src/test/unit/rc_controls_unittest.cc +++ b/src/test/unit/rc_controls_unittest.cc @@ -654,6 +654,8 @@ bool isTryingToArm(void) { return false; } void resetTryingToArm(void) {} void setLedProfile(uint8_t profile) { UNUSED(profile); } uint8_t getLedProfile(void) { return 0; } +uint8_t getLedBrightness(void) { return 50; } +void setLedBrightness(uint8_t brightness) { UNUSED(brightness); } void compassStartCalibration(void) {} void pinioBoxTaskControl(void) {} void schedulerIgnoreTaskExecTime(void) {} From b826ce3df9489ab8940846408b9b25b678788d51 Mon Sep 17 00:00:00 2001 From: Jay Blackman Date: Tue, 24 Dec 2024 10:21:34 +1100 Subject: [PATCH 012/244] Ditching default target for `make` in favour of `make all` (#14099) --- Makefile | 22 ++++++++++------------ 1 file changed, 10 insertions(+), 12 deletions(-) diff --git a/Makefile b/Makefile index bc678ee99d..b8cfc77eab 100644 --- a/Makefile +++ b/Makefile @@ -16,7 +16,6 @@ # # The target to build, see BASE_TARGETS below -DEFAULT_TARGET ?= STM32F405 TARGET ?= CONFIG ?= @@ -124,12 +123,6 @@ FC_VER := $(FC_VER_MAJOR).$(FC_VER_MINOR).$(FC_VER_PATCH) # import config handling include $(MAKE_SCRIPT_DIR)/config.mk -ifeq ($(CONFIG),) -ifeq ($(TARGET),) -TARGET := $(DEFAULT_TARGET) -SKIPCHECKS := yes -endif -endif # default xtal value HSE_VALUE ?= 8000000 @@ -141,7 +134,9 @@ TARGET_PLATFORM := $(notdir $(patsubst %/,%,$(subst target/$(TARGET)/,, $(di TARGET_PLATFORM_DIR := $(PLATFORM_DIR)/$(TARGET_PLATFORM) LINKER_DIR := $(TARGET_PLATFORM_DIR)/link +ifneq ($(TARGET),) include $(TARGET_PLATFORM_DIR)/target/$(TARGET)/target.mk +endif REVISION := norevision ifeq ($(shell git diff --shortstat),) @@ -182,6 +177,8 @@ endif VPATH := $(VPATH):$(MAKE_SCRIPT_DIR) +ifneq ($(TARGET),) + # start specific includes ifeq ($(TARGET_MCU),) $(error No TARGET_MCU specified. Is the target.mk valid for $(TARGET)?) @@ -202,9 +199,6 @@ SIZE_OPTIMISED_SRC := include $(TARGET_PLATFORM_DIR)/mk/$(TARGET_MCU_FAMILY).mk -# openocd specific includes -include $(MAKE_SCRIPT_DIR)/openocd.mk - # Configure default flash sizes for the targets (largest size specified gets hit first) if flash not specified already. ifeq ($(TARGET_FLASH_SIZE),) ifneq ($(MCU_FLASH_SIZE),) @@ -221,8 +215,12 @@ DEVICE_FLAGS := $(DEVICE_FLAGS) -DHSE_VALUE=$(HSE_VALUE) endif TARGET_DIR = $(TARGET_PLATFORM_DIR)/target/$(TARGET) +endif # TARGET specified -.DEFAULT_GOAL := hex +# openocd specific includes +include $(MAKE_SCRIPT_DIR)/openocd.mk + +.DEFAULT_GOAL := all INCLUDE_DIRS := $(INCLUDE_DIRS) \ $(ROOT)/lib/main/MAVLink @@ -234,7 +232,7 @@ VPATH := $(VPATH):$(TARGET_DIR) include $(MAKE_SCRIPT_DIR)/source.mk -ifneq ($(SKIPCHECKS),yes) +ifneq ($(TARGET),) ifneq ($(filter-out $(SRC),$(SPEED_OPTIMISED_SRC)),) $(error Speed optimised sources not valid: $(strip $(filter-out $(SRC),$(SPEED_OPTIMISED_SRC)))) endif From 59e308ae56bb33b10f7f1be289602e3ec5cc0f56 Mon Sep 17 00:00:00 2001 From: Mark Haslinghuis Date: Wed, 25 Dec 2024 06:39:04 +0100 Subject: [PATCH 013/244] Position hold depends on GPS (#14101) --- src/main/target/common_pre.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/main/target/common_pre.h b/src/main/target/common_pre.h index 505e48656c..0db3a0d1dc 100644 --- a/src/main/target/common_pre.h +++ b/src/main/target/common_pre.h @@ -483,3 +483,7 @@ #undef USE_RUNAWAY_TAKEOFF #endif // USE_WING + +#if defined(USE_POSITION_HOLD) && !defined(USE_GPS) +#error "USE_POSITION_HOLD requires USE_GPS to be defined" +#endif From 31bd403446961b89d98e0e5577f2c46e9f83e0a1 Mon Sep 17 00:00:00 2001 From: Jay Blackman Date: Sat, 28 Dec 2024 16:55:15 +1100 Subject: [PATCH 014/244] Adding support for UART0 (#14094) --- src/main/cli/cli.c | 58 +++++++++++++++++--------- src/main/drivers/serial_pinconfig.c | 3 ++ src/main/drivers/serial_tcp.c | 20 ++++++--- src/main/drivers/serial_uart.c | 7 ++++ src/main/drivers/serial_uart_impl.h | 7 ++++ src/main/io/displayport_msp.c | 3 +- src/main/io/serial.c | 17 +++++++- src/main/io/serial.h | 25 ++++++----- src/main/io/serial_resource.c | 5 +-- src/main/msp/msp.c | 2 - src/main/pg/serial_uart.c | 3 ++ src/main/target/common_defaults_post.h | 9 ++++ src/test/unit/cli_unittest.cc | 21 ++++++++-- 13 files changed, 131 insertions(+), 49 deletions(-) diff --git a/src/main/cli/cli.c b/src/main/cli/cli.c index 46e2f9e325..a174fe8cf5 100644 --- a/src/main/cli/cli.c +++ b/src/main/cli/cli.c @@ -210,6 +210,7 @@ static bool signatureUpdated = false; #endif // USE_BOARD_INFO static const char* const emptyName = "-"; +static const char* const invalidName = "INVALID"; #define MAX_CHANGESET_ID_LENGTH 8 #define MAX_DATE_LENGTH 20 @@ -1275,7 +1276,7 @@ static void cliAux(const char *cmdName, char *cmdline) static void printSerial(dumpFlags_t dumpMask, const serialConfig_t *serialConfig, const serialConfig_t *serialConfigDefault, const char *headingStr) { - const char *format = "serial %d %d %ld %ld %ld %ld"; + const char *format = "serial %s %d %ld %ld %ld %ld"; headingStr = cliPrintSectionHeading(dumpMask, false, headingStr); for (unsigned i = 0; i < ARRAYLEN(serialConfig->portConfigs); i++) { if (!serialIsPortAvailable(serialConfig->portConfigs[i].identifier)) { @@ -1286,7 +1287,7 @@ static void printSerial(dumpFlags_t dumpMask, const serialConfig_t *serialConfig equalsDefault = !memcmp(&serialConfig->portConfigs[i], &serialConfigDefault->portConfigs[i], sizeof(serialConfig->portConfigs[i])); headingStr = cliPrintSectionHeading(dumpMask, !equalsDefault, headingStr); cliDefaultPrintLinef(dumpMask, equalsDefault, format, - serialConfigDefault->portConfigs[i].identifier, + serialName(serialConfigDefault->portConfigs[i].identifier, invalidName), serialConfigDefault->portConfigs[i].functionMask, baudRates[serialConfigDefault->portConfigs[i].msp_baudrateIndex], baudRates[serialConfigDefault->portConfigs[i].gps_baudrateIndex], @@ -1295,7 +1296,7 @@ static void printSerial(dumpFlags_t dumpMask, const serialConfig_t *serialConfig ); } cliDumpPrintLinef(dumpMask, equalsDefault, format, - serialConfig->portConfigs[i].identifier, + serialName(serialConfig->portConfigs[i].identifier, invalidName), serialConfig->portConfigs[i].functionMask, baudRates[serialConfig->portConfigs[i].msp_baudrateIndex], baudRates[serialConfig->portConfigs[i].gps_baudrateIndex], @@ -1307,40 +1308,58 @@ static void printSerial(dumpFlags_t dumpMask, const serialConfig_t *serialConfig static void cliSerial(const char *cmdName, char *cmdline) { - const char *format = "serial %d %d %ld %ld %ld %ld"; + const char *format = "serial %s %d %ld %ld %ld %ld"; if (isEmpty(cmdline)) { printSerial(DUMP_MASTER, serialConfig(), NULL, NULL); return; } + serialPortConfig_t portConfig; memset(&portConfig, 0 , sizeof(portConfig)); uint8_t validArgumentCount = 0; - const char *ptr = cmdline; - - int val = atoi(ptr++); - serialPortConfig_t *currentConfig = serialFindPortConfigurationMutable(val); - - if (currentConfig) { - portConfig.identifier = val; - validArgumentCount++; + char *ptr = cmdline; + char *tok = strsep(&ptr, " "); + serialPortIdentifier_e identifier = findSerialPortByName(tok, strcasecmp); + if (identifier == SERIAL_PORT_NONE) { + char *eptr; + identifier = strtoul(tok, &eptr, 10); + if (*eptr) { + // parsing ended before end of token indicating an invalid identifier + identifier = SERIAL_PORT_NONE; + } else { + // correction for legacy configuration where UART1 == 0 + if (identifier >= SERIAL_PORT_LEGACY_START_IDENTIFIER && identifier < SERIAL_PORT_START_IDENTIFIER) { + identifier += SERIAL_PORT_UART1; + } + } } - ptr = nextArg(ptr); - if (ptr) { - val = strtoul(ptr, NULL, 10); + serialPortConfig_t *currentConfig = serialFindPortConfigurationMutable(identifier); + + if (!currentConfig) { + cliShowParseError(cmdName); + return; + } + + portConfig.identifier = identifier; + validArgumentCount++; + + tok = strsep(&ptr, " "); + if (tok) { + int val = strtoul(tok, NULL, 10); portConfig.functionMask = val; validArgumentCount++; } for (int i = 0; i < 4; i ++) { - ptr = nextArg(ptr); - if (!ptr) { + tok = strsep(&ptr, " "); + if (!tok) { break; } - val = atoi(ptr); + int val = atoi(tok); uint8_t baudRateIndex = lookupBaudRateIndex(val); if (baudRates[baudRateIndex] != (uint32_t) val) { @@ -1385,14 +1404,13 @@ static void cliSerial(const char *cmdName, char *cmdline) memcpy(currentConfig, &portConfig, sizeof(portConfig)); cliDumpPrintLinef(0, false, format, - portConfig.identifier, + serialName(portConfig.identifier, invalidName), portConfig.functionMask, baudRates[portConfig.msp_baudrateIndex], baudRates[portConfig.gps_baudrateIndex], baudRates[portConfig.telemetry_baudrateIndex], baudRates[portConfig.blackbox_baudrateIndex] ); - } #if defined(USE_SERIAL_PASSTHROUGH) diff --git a/src/main/drivers/serial_pinconfig.c b/src/main/drivers/serial_pinconfig.c index 71a1bf57ea..d72c8dbbff 100644 --- a/src/main/drivers/serial_pinconfig.c +++ b/src/main/drivers/serial_pinconfig.c @@ -40,6 +40,9 @@ typedef struct serialDefaultPin_s { } serialDefaultPin_t; static const serialDefaultPin_t serialDefaultPin[] = { +#ifdef USE_UART0 + { SERIAL_PORT_UART0, IO_TAG(UART0_RX_PIN), IO_TAG(UART0_TX_PIN), IO_TAG(INVERTER_PIN_UART0) }, +#endif #ifdef USE_UART1 { SERIAL_PORT_USART1, IO_TAG(UART1_RX_PIN), IO_TAG(UART1_TX_PIN), IO_TAG(INVERTER_PIN_UART1) }, #endif diff --git a/src/main/drivers/serial_tcp.c b/src/main/drivers/serial_tcp.c index 6ffa2e386b..bc6f6d37ff 100644 --- a/src/main/drivers/serial_tcp.c +++ b/src/main/drivers/serial_tcp.c @@ -44,15 +44,18 @@ static const struct serialPortVTable tcpVTable; // Forward static tcpPort_t tcpSerialPorts[SERIAL_PORT_COUNT]; static bool tcpPortInitialized[SERIAL_PORT_COUNT]; static bool tcpStart = false; + bool tcpIsStart(void) { return tcpStart; } + static void onData(dyad_Event *e) { tcpPort_t* s = (tcpPort_t*)(e->udata); tcpDataIn(s, (uint8_t*)e->data, e->size); } + static void onClose(dyad_Event *e) { tcpPort_t* s = (tcpPort_t*)(e->udata); @@ -63,6 +66,7 @@ static void onClose(dyad_Event *e) s->connected = false; } } + static void onAccept(dyad_Event *e) { tcpPort_t* s = (tcpPort_t*)(e->udata); @@ -81,6 +85,7 @@ static void onAccept(dyad_Event *e) dyad_addListener(e->remote, DYAD_EVENT_DATA, onData, e->udata); dyad_addListener(e->remote, DYAD_EVENT_CLOSE, onClose, e->udata); } + static tcpPort_t* tcpReconfigure(tcpPort_t *s, int id) { if (tcpPortInitialized[id]) { @@ -93,6 +98,7 @@ static tcpPort_t* tcpReconfigure(tcpPort_t *s, int id) // TODO: clean up & re-init return NULL; } + if (pthread_mutex_init(&s->rxLock, NULL) != 0) { fprintf(stderr, "RX mutex init failed - %d\n", errno); // TODO: clean up & re-init @@ -118,17 +124,19 @@ static tcpPort_t* tcpReconfigure(tcpPort_t *s, int id) return s; } -serialPort_t *serTcpOpen(int id, serialReceiveCallbackPtr rxCallback, void *rxCallbackData, uint32_t baudRate, portMode_e mode, portOptions_e options) +serialPort_t *serTcpOpen(serialPortIdentifier_e identifier, serialReceiveCallbackPtr rxCallback, void *rxCallbackData, uint32_t baudRate, portMode_e mode, portOptions_e options) { tcpPort_t *s = NULL; -#if defined(USE_UART1) || defined(USE_UART2) || defined(USE_UART3) || defined(USE_UART4) || defined(USE_UART5) || defined(USE_UART6) || defined(USE_UART7) || defined(USE_UART8) - if (id >= 0 && id < SERIAL_PORT_COUNT) { - s = tcpReconfigure(&tcpSerialPorts[id], id); + int id = findSerialPortIndexByIdentifier(identifier); + + if (id >= 0 && id < (int)ARRAYLEN(tcpSerialPorts)) { + s = tcpReconfigure(&tcpSerialPorts[id], id); } -#endif - if (!s) + + if (!s) { return NULL; + } s->port.vTable = &tcpVTable; diff --git a/src/main/drivers/serial_uart.c b/src/main/drivers/serial_uart.c index 24bfb66c8a..d4c530d889 100644 --- a/src/main/drivers/serial_uart.c +++ b/src/main/drivers/serial_uart.c @@ -71,6 +71,10 @@ UART_BUFFER(UART_RX_BUFFER_ATTRIBUTE, n, R); struct dummy_s \ /**/ +#ifdef USE_UART0 +UART_BUFFERS(0); +#endif + #ifdef USE_UART1 UART_BUFFERS(1); #endif @@ -136,6 +140,9 @@ uartDeviceIdx_e uartDeviceIdxFromIdentifier(serialPortIdentifier_e identifier) // table is for UART only to save space (LPUART is handled separately) #define _R(id, dev) [id] = (dev) + 1 static const uartDeviceIdx_e uartMap[] = { +#ifdef USE_UART0 + _R(SERIAL_PORT_UART0, UARTDEV_0), +#endif #ifdef USE_UART1 _R(SERIAL_PORT_USART1, UARTDEV_1), #endif diff --git a/src/main/drivers/serial_uart_impl.h b/src/main/drivers/serial_uart_impl.h index e6b15d27a3..94b679e505 100644 --- a/src/main/drivers/serial_uart_impl.h +++ b/src/main/drivers/serial_uart_impl.h @@ -132,6 +132,9 @@ // compressed index of UART/LPUART. Direct index into uartDevice[] typedef enum { UARTDEV_INVALID = -1, +#ifdef USE_UART0 + UARTDEV_0, +#endif #ifdef USE_UART1 UARTDEV_1, #endif @@ -285,6 +288,10 @@ void uartTxMonitor(uartPort_t *s); UART_BUFFER(extern, n, T); struct dummy_s \ /**/ +#ifdef USE_UART0 +UART_BUFFERS_EXTERN(0); +#endif + #ifdef USE_UART1 UART_BUFFERS_EXTERN(1); #endif diff --git a/src/main/io/displayport_msp.c b/src/main/io/displayport_msp.c index 3e7ea38890..08f46491e4 100644 --- a/src/main/io/displayport_msp.c +++ b/src/main/io/displayport_msp.c @@ -220,7 +220,8 @@ displayPort_t *displayPortMspInit(void) return &mspDisplayPort; } -void displayPortMspSetSerial(serialPortIdentifier_e serialPort) { +void displayPortMspSetSerial(serialPortIdentifier_e serialPort) +{ displayPortSerial = serialPort; } diff --git a/src/main/io/serial.c b/src/main/io/serial.c index 325d6ec152..a97d8260a5 100644 --- a/src/main/io/serial.c +++ b/src/main/io/serial.c @@ -70,6 +70,9 @@ const serialPortIdentifier_e serialPortIdentifiers[SERIAL_PORT_COUNT] = { #ifdef USE_VCP SERIAL_PORT_USB_VCP, #endif +#ifdef USE_UART0 + SERIAL_PORT_UART0, +#endif #ifdef USE_UART1 SERIAL_PORT_USART1, #endif @@ -115,6 +118,9 @@ const char* serialPortNames[SERIAL_PORT_COUNT] = { #ifdef USE_VCP "VCP", #endif +#ifdef USE_UART0 + "UART0", +#endif #ifdef USE_UART1 "UART1", #endif @@ -156,17 +162,24 @@ const char* serialPortNames[SERIAL_PORT_COUNT] = { #endif }; -const uint32_t baudRates[] = {0, 9600, 19200, 38400, 57600, 115200, 230400, 250000, - 400000, 460800, 500000, 921600, 1000000, 1500000, 2000000, 2470000}; // see baudRate_e +const uint32_t baudRates[BAUD_COUNT] = { + 0, 9600, 19200, 38400, 57600, 115200, 230400, 250000, + 400000, 460800, 500000, 921600, 1000000, 1500000, 2000000, 2470000 +}; // see baudRate_e static serialPortConfig_t* findInPortConfigs_identifier(const serialPortConfig_t cfgs[], size_t count, serialPortIdentifier_e identifier) { + if (identifier == SERIAL_PORT_NONE || identifier == SERIAL_PORT_ALL) { + return NULL; + } + for (unsigned i = 0; i < count; i++) { if (cfgs[i].identifier == identifier) { // drop const on return - wrapper function will add it back if necessary return (serialPortConfig_t*)&cfgs[i]; } } + return NULL; } diff --git a/src/main/io/serial.h b/src/main/io/serial.h index af10830fa2..4943597eaa 100644 --- a/src/main/io/serial.h +++ b/src/main/io/serial.h @@ -77,18 +77,29 @@ typedef enum { BAUD_COUNT } baudRate_e; -extern const uint32_t baudRates[]; +extern const uint32_t baudRates[BAUD_COUNT]; // serial port identifiers are now fixed, these values are used by MSP commands. typedef enum { SERIAL_PORT_ALL = -2, SERIAL_PORT_NONE = -1, - // prepare for transition to SERIAL_PORT_UART0 - SERIAL_PORT_UART_FIRST = 0, + SERIAL_PORT_LEGACY_START_IDENTIFIER = 0, + SERIAL_PORT_START_IDENTIFIER = 20, + SERIAL_PORT_USB_VCP = 20, + + SERIAL_PORT_SOFTSERIAL_FIRST = 30, + SERIAL_PORT_SOFTSERIAL1 = SERIAL_PORT_SOFTSERIAL_FIRST, + SERIAL_PORT_SOFTSERIAL2, + + SERIAL_PORT_LPUART_FIRST = 40, + SERIAL_PORT_LPUART1 = SERIAL_PORT_LPUART_FIRST, + #if SERIAL_UART_FIRST_INDEX == 0 + SERIAL_PORT_UART_FIRST = 50, SERIAL_PORT_UART0 = SERIAL_PORT_UART_FIRST, SERIAL_PORT_USART1, #else + SERIAL_PORT_UART_FIRST = 51, SERIAL_PORT_USART1 = SERIAL_PORT_UART_FIRST, #endif SERIAL_PORT_UART1 = SERIAL_PORT_USART1, @@ -108,14 +119,6 @@ typedef enum { SERIAL_PORT_USART10, SERIAL_PORT_UART10 = SERIAL_PORT_USART10, - SERIAL_PORT_USB_VCP = 20, - - SERIAL_PORT_SOFTSERIAL_FIRST = 30, - SERIAL_PORT_SOFTSERIAL1 = SERIAL_PORT_SOFTSERIAL_FIRST, - SERIAL_PORT_SOFTSERIAL2, - - SERIAL_PORT_LPUART_FIRST = 40, - SERIAL_PORT_LPUART1 = SERIAL_PORT_LPUART_FIRST, } serialPortIdentifier_e; // use value from target serial port normalization diff --git a/src/main/io/serial_resource.c b/src/main/io/serial_resource.c index 962e0d7d25..878968d0bf 100644 --- a/src/main/io/serial_resource.c +++ b/src/main/io/serial_resource.c @@ -60,9 +60,8 @@ serialType_e serialType(serialPortIdentifier_e identifier) } #endif #ifdef USE_SOFTSERIAL - if (identifier >= SERIAL_PORT_SOFTSERIAL_FIRST - && identifier < SERIAL_PORT_SOFTSERIAL_FIRST + SERIAL_SOFTSERIAL_MAX) { - // sotserials always start from first index, without holes + if (identifier >= SERIAL_PORT_SOFTSERIAL_FIRST && identifier < SERIAL_PORT_SOFTSERIAL_FIRST + SERIAL_SOFTSERIAL_MAX) { + // sotserials always start from 1, without holes return SERIALTYPE_SOFTSERIAL; } #endif diff --git a/src/main/msp/msp.c b/src/main/msp/msp.c index 31ff012e62..f41866de0f 100644 --- a/src/main/msp/msp.c +++ b/src/main/msp/msp.c @@ -3889,7 +3889,6 @@ static mspResult_e mspProcessInCommand(mspDescriptor_t srcDesc, int16_t cmdMSP, return MSP_RESULT_ERROR; } - portConfig->identifier = identifier; portConfig->functionMask = sbufReadU16(src); portConfig->msp_baudrateIndex = sbufReadU8(src); portConfig->gps_baudrateIndex = sbufReadU8(src); @@ -3917,7 +3916,6 @@ static mspResult_e mspProcessInCommand(mspDescriptor_t srcDesc, int16_t cmdMSP, return MSP_RESULT_ERROR; } - portConfig->identifier = identifier; portConfig->functionMask = sbufReadU32(src); portConfig->msp_baudrateIndex = sbufReadU8(src); portConfig->gps_baudrateIndex = sbufReadU8(src); diff --git a/src/main/pg/serial_uart.c b/src/main/pg/serial_uart.c index 355d28170a..3bec1a3804 100644 --- a/src/main/pg/serial_uart.c +++ b/src/main/pg/serial_uart.c @@ -46,6 +46,9 @@ typedef struct uartDmaopt_s { } uartDmaopt_t; static const uartDmaopt_t uartDmaopt[] = { +#ifdef USE_UART0 + { SERIAL_PORT_UART0, UART0_TX_DMA_OPT, UART0_RX_DMA_OPT }, +#endif #ifdef USE_UART1 { SERIAL_PORT_USART1, UART1_TX_DMA_OPT, UART1_RX_DMA_OPT }, #endif diff --git a/src/main/target/common_defaults_post.h b/src/main/target/common_defaults_post.h index 18ac19fd59..820eba0677 100644 --- a/src/main/target/common_defaults_post.h +++ b/src/main/target/common_defaults_post.h @@ -211,6 +211,15 @@ #endif #endif +#ifdef USE_UART0 +#ifndef UART0_TX_DMA_OPT +#define UART0_TX_DMA_OPT (DMA_OPT_UNUSED) +#endif +#ifndef UART0_RX_DMA_OPT +#define UART0_RX_DMA_OPT (DMA_OPT_UNUSED) +#endif +#endif + #ifdef USE_UART1 #ifndef UART1_TX_DMA_OPT #define UART1_TX_DMA_OPT (DMA_OPT_UNUSED) diff --git a/src/test/unit/cli_unittest.cc b/src/test/unit/cli_unittest.cc index 63362e630f..c756929c8c 100644 --- a/src/test/unit/cli_unittest.cc +++ b/src/test/unit/cli_unittest.cc @@ -63,7 +63,7 @@ extern "C" { void cliSet(const char *cmdName, char *cmdline); int cliGetSettingIndex(char *name, uint8_t length); void *cliGetValuePointer(const clivalue_t *value); - + const clivalue_t valueTable[] = { { .name = "array_unit_test", .type = VAR_INT8 | MODE_ARRAY | MASTER_VALUE, .config = { .array = { .length = 3}}, .pgn = PG_RESERVED_FOR_TESTING_1, .offset = 0 }, { .name = "str_unit_test", .type = VAR_UINT8 | MODE_STRING | MASTER_VALUE, .config = { .string = { 0, 16, 0 }}, .pgn = PG_RESERVED_FOR_TESTING_1, .offset = 0 }, @@ -132,7 +132,7 @@ TEST(CLIUnittest, TestCliSetArray) TEST(CLIUnittest, TestCliSetStringNoFlags) { - char *str = (char *)"str_unit_test = SAMPLE"; + char *str = (char *)"str_unit_test = SAMPLE"; cliSet("", str); const uint16_t index = cliGetSettingIndex(str, 13); @@ -160,8 +160,8 @@ TEST(CLIUnittest, TestCliSetStringNoFlags) TEST(CLIUnittest, TestCliSetStringWriteOnce) { - char *str1 = (char *)"wos_unit_test = SAMPLE"; - char *str2 = (char *)"wos_unit_test = ELPMAS"; + char *str1 = (char *)"wos_unit_test = SAMPLE"; + char *str2 = (char *)"wos_unit_test = ELPMAS"; cliSet("", str1); const uint16_t index = cliGetSettingIndex(str1, 13); @@ -370,6 +370,19 @@ void generateLedConfig(ledConfig_t *, char *, size_t) {} void serialSetCtrlLineStateDtrPin(serialPort_t *, ioTag_t ) {} void serialSetCtrlLineState(serialPort_t *, uint16_t ) {} +serialPortIdentifier_e findSerialPortByName(const char* portName, int (*cmp)(const char *portName, const char *candidate)) +{ + UNUSED(portName); + UNUSED(cmp); + return SERIAL_PORT_NONE; +} + +const char* serialName(serialPortIdentifier_e identifier, const char* notFound) +{ + UNUSED(identifier); + return notFound; +} + //void serialSetBaudRateCb(serialPort_t *, void (*)(serialPort_t *context, uint32_t baud), serialPort_t *) {} void rescheduleTask(taskId_e, timeDelta_t){} void schedulerSetNextStateTime(timeDelta_t ){} From 2a50634f67fd841f2909f0414dc6c277e8806b5c Mon Sep 17 00:00:00 2001 From: Leo Garcia <34465410+DrAtomic@users.noreply.github.com> Date: Sat, 28 Dec 2024 12:41:32 -0800 Subject: [PATCH 015/244] update serTcpOpen declaration to fix compile errors (#14113) update serTcpopen declaration to fix compile errors --- src/main/drivers/serial_tcp.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/main/drivers/serial_tcp.h b/src/main/drivers/serial_tcp.h index 4e70f242b0..a391e10891 100644 --- a/src/main/drivers/serial_tcp.h +++ b/src/main/drivers/serial_tcp.h @@ -23,6 +23,7 @@ #include #include #include "dyad.h" +#include "io/serial.h" #define RX_BUFFER_SIZE 1400 #define TX_BUFFER_SIZE 1400 @@ -41,7 +42,7 @@ typedef struct { uint8_t id; } tcpPort_t; -serialPort_t *serTcpOpen(int id, serialReceiveCallbackPtr rxCallback, void *rxCallbackData, uint32_t baudRate, portMode_e mode, portOptions_e options); +serialPort_t *serTcpOpen(serialPortIdentifier_e id, serialReceiveCallbackPtr rxCallback, void *rxCallbackData, uint32_t baudRate, portMode_e mode, portOptions_e options); // tcpPort API void tcpDataIn(tcpPort_t *instance, uint8_t* ch, int size); From ef81595f1d5b842114068d78c5e058e359cfb761 Mon Sep 17 00:00:00 2001 From: Ivan Efimov <2925027+limonspb@users.noreply.github.com> Date: Mon, 30 Dec 2024 15:36:33 -0600 Subject: [PATCH 016/244] Separate autopilot multirotor from autopilot wing - dummy files for wing (#14108) * separate autopilot multirotor from autopilot wing - dummy files for wing * fix for lisence header for new files * filling empty PG structures with uint8_t dummy --- mk/source.mk | 30 +++-- src/main/blackbox/blackbox.c | 19 ++- src/main/cli/settings.c | 12 +- ...cue.c => cms_menu_gps_rescue_multirotor.c} | 4 + src/main/cms/cms_menu_gps_rescue_wing.c | 114 ++++++++++++++++++ src/main/flight/alt_hold.h | 14 +-- .../{alt_hold.c => alt_hold_multirotor.c} | 9 +- src/main/flight/alt_hold_multirotor.h | 35 ++++++ src/main/flight/alt_hold_wing.c | 59 +++++++++ src/main/flight/alt_hold_wing.h | 35 ++++++ src/main/flight/autopilot.h | 15 +-- .../{autopilot.c => autopilot_multirotor.c} | 5 + src/main/flight/autopilot_multirotor.h | 38 ++++++ src/main/flight/autopilot_wing.c | 91 ++++++++++++++ src/main/flight/autopilot_wing.h | 37 ++++++ src/main/flight/gps_rescue.h | 40 +----- .../{gps_rescue.c => gps_rescue_multirotor.c} | 5 +- src/main/flight/gps_rescue_multirotor.h | 61 ++++++++++ src/main/flight/gps_rescue_wing.c | 100 +++++++++++++++ src/main/flight/gps_rescue_wing.h | 41 +++++++ src/main/flight/pid.c | 4 +- src/main/flight/pos_hold.h | 16 +-- .../{pos_hold.c => pos_hold_multirotor.c} | 12 +- src/main/flight/pos_hold_multirotor.h | 37 ++++++ src/main/flight/pos_hold_wing.c | 57 +++++++++ src/main/flight/pos_hold_wing.h | 37 ++++++ src/main/msp/msp.c | 8 +- src/main/pg/alt_hold.h | 12 +- .../pg/{alt_hold.c => alt_hold_multirotor.c} | 4 + src/main/pg/alt_hold_multirotor.h | 37 ++++++ src/main/pg/alt_hold_wing.c | 41 +++++++ src/main/pg/alt_hold_wing.h | 36 ++++++ src/main/pg/autopilot.h | 25 +--- .../{autopilot.c => autopilot_multirotor.c} | 4 + src/main/pg/autopilot_multirotor.h | 49 ++++++++ src/main/pg/autopilot_wing.c | 38 ++++++ src/main/pg/autopilot_wing.h | 36 ++++++ src/main/pg/gps_rescue.h | 53 ++------ .../{gps_rescue.c => gps_rescue_multirotor.c} | 4 + src/main/pg/gps_rescue_multirotor.h | 54 +++++++++ src/main/pg/gps_rescue_wing.c | 40 ++++++ src/main/pg/gps_rescue_wing.h | 33 +++++ src/main/pg/pos_hold.h | 12 +- .../pg/{pos_hold.c => pos_hold_multirotor.c} | 4 + src/main/pg/pos_hold_multirotor.h | 37 ++++++ src/main/pg/pos_hold_wing.c | 41 +++++++ src/main/pg/pos_hold_wing.h | 36 ++++++ src/test/Makefile | 8 +- 48 files changed, 1345 insertions(+), 194 deletions(-) rename src/main/cms/{cms_menu_gps_rescue.c => cms_menu_gps_rescue_multirotor.c} (99%) create mode 100644 src/main/cms/cms_menu_gps_rescue_wing.c rename src/main/flight/{alt_hold.c => alt_hold_multirotor.c} (97%) create mode 100644 src/main/flight/alt_hold_multirotor.h create mode 100644 src/main/flight/alt_hold_wing.c create mode 100644 src/main/flight/alt_hold_wing.h rename src/main/flight/{autopilot.c => autopilot_multirotor.c} (99%) create mode 100644 src/main/flight/autopilot_multirotor.h create mode 100644 src/main/flight/autopilot_wing.c create mode 100644 src/main/flight/autopilot_wing.h rename src/main/flight/{gps_rescue.c => gps_rescue_multirotor.c} (99%) create mode 100644 src/main/flight/gps_rescue_multirotor.h create mode 100644 src/main/flight/gps_rescue_wing.c create mode 100644 src/main/flight/gps_rescue_wing.h rename src/main/flight/{pos_hold.c => pos_hold_multirotor.c} (95%) create mode 100644 src/main/flight/pos_hold_multirotor.h create mode 100644 src/main/flight/pos_hold_wing.c create mode 100644 src/main/flight/pos_hold_wing.h rename src/main/pg/{alt_hold.c => alt_hold_multirotor.c} (96%) create mode 100644 src/main/pg/alt_hold_multirotor.h create mode 100644 src/main/pg/alt_hold_wing.c create mode 100644 src/main/pg/alt_hold_wing.h rename src/main/pg/{autopilot.c => autopilot_multirotor.c} (97%) create mode 100644 src/main/pg/autopilot_multirotor.h create mode 100644 src/main/pg/autopilot_wing.c create mode 100644 src/main/pg/autopilot_wing.h rename src/main/pg/{gps_rescue.c => gps_rescue_multirotor.c} (97%) create mode 100644 src/main/pg/gps_rescue_multirotor.h create mode 100644 src/main/pg/gps_rescue_wing.c create mode 100644 src/main/pg/gps_rescue_wing.h rename src/main/pg/{pos_hold.c => pos_hold_multirotor.c} (97%) create mode 100644 src/main/pg/pos_hold_multirotor.h create mode 100644 src/main/pg/pos_hold_wing.c create mode 100644 src/main/pg/pos_hold_wing.h diff --git a/mk/source.mk b/mk/source.mk index c28a739577..e4c60d55cb 100644 --- a/mk/source.mk +++ b/mk/source.mk @@ -1,7 +1,9 @@ PG_SRC = \ pg/adc.c \ - pg/alt_hold.c \ - pg/autopilot.c \ + pg/alt_hold_multirotor.c \ + pg/alt_hold_wing.c \ + pg/autopilot_multirotor.c \ + pg/autopilot_wing.c \ pg/beeper.c \ pg/beeper_dev.c \ pg/board.c \ @@ -15,7 +17,8 @@ PG_SRC = \ pg/gimbal.c \ pg/gps.c \ pg/gps_lap_timer.c \ - pg/gps_rescue.c \ + pg/gps_rescue_multirotor.c \ + pg/gps_rescue_wing.c \ pg/gyrodev.c \ pg/max7456.c \ pg/mco.c \ @@ -26,7 +29,8 @@ PG_SRC = \ pg/piniobox.c \ pg/pinio.c \ pg/pin_pull_up_down.c \ - pg/pos_hold.c \ + pg/pos_hold_multirotor.c \ + pg/pos_hold_wing.c \ pg/rcdevice.c \ pg/rpm_filter.c \ pg/rx.c \ @@ -154,11 +158,14 @@ COMMON_SRC = \ fc/rc_adjustments.c \ fc/rc_controls.c \ fc/rc_modes.c \ - flight/alt_hold.c \ - flight/autopilot.c \ + flight/alt_hold_multirotor.c \ + flight/alt_hold_wing.c \ + flight/autopilot_multirotor.c \ + flight/autopilot_wing.c \ flight/dyn_notch_filter.c \ flight/failsafe.c \ - flight/gps_rescue.c \ + flight/gps_rescue_multirotor.c \ + flight/gps_rescue_wing.c \ flight/imu.c \ flight/mixer.c \ flight/mixer_init.c \ @@ -166,7 +173,8 @@ COMMON_SRC = \ flight/pid.c \ flight/pid_init.c \ flight/position.c \ - flight/pos_hold.c \ + flight/pos_hold_multirotor.c \ + flight/pos_hold_wing.c \ flight/rpm_filter.c \ flight/servos.c \ flight/servos_tricopter.c \ @@ -210,7 +218,8 @@ COMMON_SRC = \ cms/cms_menu_blackbox.c \ cms/cms_menu_failsafe.c \ cms/cms_menu_firmware.c \ - cms/cms_menu_gps_rescue.c \ + cms/cms_menu_gps_rescue_multirotor.c \ + cms/cms_menu_gps_rescue_wing.c \ cms/cms_menu_gps_lap_timer.c \ cms/cms_menu_imu.c \ cms/cms_menu_ledstrip.c \ @@ -513,7 +522,8 @@ SIZE_OPTIMISED_SRC += \ cms/cms_menu_blackbox.c \ cms/cms_menu_failsafe.c \ cms/cms_menu_firmware.c \ - cms/cms_menu_gps_rescue.c \ + cms/cms_menu_gps_rescue_multirotor.c \ + cms/cms_menu_gps_rescue_wing.c \ cms/cms_menu_gps_lap_timer.c \ cms/cms_menu_imu.c \ cms/cms_menu_ledstrip.c \ diff --git a/src/main/blackbox/blackbox.c b/src/main/blackbox/blackbox.c index 89fa7a2632..c8f359b924 100644 --- a/src/main/blackbox/blackbox.c +++ b/src/main/blackbox/blackbox.c @@ -745,7 +745,7 @@ static void writeIntraframe(void) if (testBlackboxCondition(CONDITION(ACC))) { blackboxWriteSigned16VBArray(blackboxCurrent->accADC, XYZ_AXIS_COUNT); } - + if (testBlackboxCondition(CONDITION(ATTITUDE))) { blackboxWriteSigned16VBArray(blackboxCurrent->imuAttitudeQuaternion, XYZ_AXIS_COUNT); } @@ -930,7 +930,7 @@ static void writeInterframe(void) if (testBlackboxCondition(CONDITION(ACC))) { blackboxWriteMainStateArrayUsingAveragePredictor(offsetof(blackboxMainState_t, accADC), XYZ_AXIS_COUNT); } - + if (testBlackboxCondition(CONDITION(ATTITUDE))) { blackboxWriteMainStateArrayUsingAveragePredictor(offsetof(blackboxMainState_t, imuAttitudeQuaternion), XYZ_AXIS_COUNT); } @@ -1244,14 +1244,14 @@ static void loadMainState(timeUs_t currentTimeUs) blackboxCurrent->axisPID_F[i] = lrintf(pidData[i].F); #ifdef USE_WING blackboxCurrent->axisPID_S[i] = lrintf(pidData[i].S); -#endif +#endif blackboxCurrent->gyroADC[i] = lrintf(gyro.gyroADCf[i] * blackboxHighResolutionScale); blackboxCurrent->gyroUnfilt[i] = lrintf(gyro.gyroADC[i] * blackboxHighResolutionScale); #if defined(USE_ACC) blackboxCurrent->accADC[i] = lrintf(acc.accADC.v[i]); STATIC_ASSERT(offsetof(quaternion_t, w) == 0, "Code expects quaternion in w, x, y, z order"); - blackboxCurrent->imuAttitudeQuaternion[i] = lrintf(imuAttitudeQuaternion.v[i + 1] * 0x7FFF); //Scale to int16 by value 0x7FFF = 2^15 - 1; Use i+1 index for x,y,z components access, [0] - w + blackboxCurrent->imuAttitudeQuaternion[i] = lrintf(imuAttitudeQuaternion.v[i + 1] * 0x7FFF); //Scale to int16 by value 0x7FFF = 2^15 - 1; Use i+1 index for x,y,z components access, [0] - w #endif #ifdef USE_MAG blackboxCurrent->magADC[i] = lrintf(mag.magADC.v[i]); @@ -1695,6 +1695,7 @@ static bool blackboxWriteSysinfo(void) BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_ALTITUDE_LPF, "%d", positionConfig()->altitude_lpf); BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_ALTITUDE_D_LPF, "%d", positionConfig()->altitude_d_lpf); +#ifndef USE_WING BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_LANDING_ALTITUDE, "%d", apConfig()->landing_altitude_m); BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_HOVER_THROTTLE, "%d", apConfig()->hover_throttle); BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_THROTTLE_MIN, "%d", apConfig()->throttle_min); @@ -1709,6 +1710,7 @@ static bool blackboxWriteSysinfo(void) BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_POSITION_A, "%d", apConfig()->position_A); BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_POSITION_CUTOFF, "%d", apConfig()->position_cutoff); BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_AP_MAX_ANGLE, "%d", apConfig()->max_angle); +#endif // !USE_WING #ifdef USE_MAG BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_MAG_HARDWARE, "%d", compassConfig()->mag_hardware); @@ -1785,6 +1787,7 @@ static bool blackboxWriteSysinfo(void) BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_GPS_USE_3D_SPEED, "%d", gpsConfig()->gps_use_3d_speed) #ifdef USE_GPS_RESCUE +#ifndef USE_WING BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_GPS_RESCUE_MIN_START_DIST, "%d", gpsRescueConfig()->minStartDistM) BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_GPS_RESCUE_ALT_MODE, "%d", gpsRescueConfig()->altitudeMode) BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_GPS_RESCUE_INITIAL_CLIMB, "%d", gpsRescueConfig()->initialClimbM) @@ -1809,21 +1812,25 @@ static bool blackboxWriteSysinfo(void) BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_GPS_RESCUE_VELOCITY_I, "%d", gpsRescueConfig()->velI) BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_GPS_RESCUE_VELOCITY_D, "%d", gpsRescueConfig()->velD) BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_GPS_RESCUE_YAW_P, "%d", gpsRescueConfig()->yawP) - #ifdef USE_MAG BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_GPS_RESCUE_USE_MAG, "%d", gpsRescueConfig()->useMag) #endif // USE_MAG +#endif // !USE_WING #endif // USE_GPS_RESCUE #endif // USE_GPS #ifdef USE_ALTITUDE_HOLD +#ifndef USE_WING BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_ALT_HOLD_THROTTLE_RESPONSE, "%d", altHoldConfig()->alt_hold_adjust_rate); BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_ALT_HOLD_DEADBAND, "%d", altHoldConfig()->alt_hold_deadband); -#endif +#endif // !USE_WING +#endif // USE_ALTITUDE_HOLD #ifdef USE_POSITION_HOLD +#ifndef USE_WING BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_POS_HOLD_WITHOUT_MAG, "%d", posHoldConfig()->pos_hold_without_mag); BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_POS_HOLD_DEADBAND, "%d", posHoldConfig()->pos_hold_deadband); +#endif // !USE_WING #endif #ifdef USE_WING diff --git a/src/main/cli/settings.c b/src/main/cli/settings.c index 95406b6a91..1bfe829b79 100644 --- a/src/main/cli/settings.c +++ b/src/main/cli/settings.c @@ -1074,6 +1074,7 @@ const clivalue_t valueTable[] = { { PARAM_NAME_GPS_NMEA_CUSTOM_COMMANDS, VAR_UINT8 | MASTER_VALUE | MODE_STRING, .config.string = { 1, NMEA_CUSTOM_COMMANDS_MAX_LENGTH, STRING_FLAGS_NONE }, PG_GPS_CONFIG, offsetof(gpsConfig_t, nmeaCustomCommands) }, #ifdef USE_GPS_RESCUE +#ifndef USE_WING // PG_GPS_RESCUE { PARAM_NAME_GPS_RESCUE_MIN_START_DIST, VAR_UINT16 | MASTER_VALUE, .config.minmaxUnsigned = { 10, 30 }, PG_GPS_RESCUE, offsetof(gpsRescueConfig_t, minStartDistM) }, { PARAM_NAME_GPS_RESCUE_ALT_MODE, VAR_UINT8 | MASTER_VALUE | MODE_LOOKUP, .config.lookup = { TABLE_GPS_RESCUE_ALT_MODE }, PG_GPS_RESCUE, offsetof(gpsRescueConfig_t, altitudeMode) }, @@ -1103,6 +1104,7 @@ const clivalue_t valueTable[] = { #ifdef USE_MAG { PARAM_NAME_GPS_RESCUE_USE_MAG, VAR_UINT8 | MASTER_VALUE | MODE_LOOKUP, .config.lookup = { TABLE_OFF_ON }, PG_GPS_RESCUE, offsetof(gpsRescueConfig_t, useMag) }, #endif // USE_MAG +#endif // !USE_WING #endif // USE_GPS_RESCUE #ifdef USE_GPS_LAP_TIMER @@ -1119,14 +1121,18 @@ const clivalue_t valueTable[] = { { "yaw_control_reversed", VAR_INT8 | MASTER_VALUE | MODE_LOOKUP, .config.lookup = { TABLE_OFF_ON }, PG_RC_CONTROLS_CONFIG, offsetof(rcControlsConfig_t, yaw_control_reversed) }, #ifdef USE_ALTITUDE_HOLD +#ifndef USE_WING { PARAM_NAME_ALT_HOLD_THROTTLE_RESPONSE, VAR_UINT8 | MASTER_VALUE, .config.minmaxUnsigned = { 0, 200 }, PG_ALTHOLD_CONFIG, offsetof(altHoldConfig_t, alt_hold_adjust_rate) }, { PARAM_NAME_ALT_HOLD_DEADBAND, VAR_UINT8 | MASTER_VALUE, .config.minmaxUnsigned = { 0, 70 }, PG_ALTHOLD_CONFIG, offsetof(altHoldConfig_t, alt_hold_deadband) }, -#endif +#endif // !USE_WING +#endif // USE_ALTITUDE_HOLD #ifdef USE_POSITION_HOLD +#ifndef USE_WING { PARAM_NAME_POS_HOLD_WITHOUT_MAG, VAR_UINT8 | MASTER_VALUE | MODE_LOOKUP, .config.lookup = { TABLE_OFF_ON }, PG_POSHOLD_CONFIG, offsetof(posHoldConfig_t, pos_hold_without_mag) }, { PARAM_NAME_POS_HOLD_DEADBAND, VAR_UINT8 | MASTER_VALUE, .config.minmaxUnsigned = { 0, 50 }, PG_POSHOLD_CONFIG, offsetof(posHoldConfig_t, pos_hold_deadband) }, -#endif +#endif // !USE_WING +#endif // USE_POSITION_HOLD // PG_PID_CONFIG { PARAM_NAME_PID_PROCESS_DENOM, VAR_UINT8 | MASTER_VALUE, .config.minmaxUnsigned = { 1, MAX_PID_PROCESS_DENOM }, PG_PID_CONFIG, offsetof(pidConfig_t, pid_process_denom) }, @@ -1867,6 +1873,7 @@ const clivalue_t valueTable[] = { { PARAM_NAME_ALTITUDE_D_LPF, VAR_UINT16 | MASTER_VALUE, .config.minmaxUnsigned = { 10, 1000 }, PG_POSITION, offsetof(positionConfig_t, altitude_d_lpf) }, // PG_AUTOPILOT +#ifndef USE_WING { PARAM_NAME_LANDING_ALTITUDE, VAR_UINT8 | MASTER_VALUE, .config.minmaxUnsigned = { 0, 200 }, PG_AUTOPILOT, offsetof(apConfig_t, landing_altitude_m) }, { PARAM_NAME_HOVER_THROTTLE, VAR_UINT16 | MASTER_VALUE, .config.minmaxUnsigned = { 1100, 1700 }, PG_AUTOPILOT, offsetof(apConfig_t, hover_throttle) }, { PARAM_NAME_THROTTLE_MIN, VAR_UINT16 | MASTER_VALUE, .config.minmaxUnsigned = { 1050, 1400 }, PG_AUTOPILOT, offsetof(apConfig_t, throttle_min) }, @@ -1881,6 +1888,7 @@ const clivalue_t valueTable[] = { { PARAM_NAME_POSITION_A, VAR_UINT8 | MASTER_VALUE, .config.minmaxUnsigned = { 0, 200 }, PG_AUTOPILOT, offsetof(apConfig_t, position_A) }, { PARAM_NAME_POSITION_CUTOFF, VAR_UINT8 | MASTER_VALUE, .config.minmaxUnsigned = { 10, 250 }, PG_AUTOPILOT, offsetof(apConfig_t, position_cutoff) }, { PARAM_NAME_AP_MAX_ANGLE, VAR_UINT8 | MASTER_VALUE, .config.minmaxUnsigned = { 10, 70 }, PG_AUTOPILOT, offsetof(apConfig_t, max_angle) }, +#endif // !USE_WING // PG_MODE_ACTIVATION_CONFIG #if defined(USE_CUSTOM_BOX_NAMES) diff --git a/src/main/cms/cms_menu_gps_rescue.c b/src/main/cms/cms_menu_gps_rescue_multirotor.c similarity index 99% rename from src/main/cms/cms_menu_gps_rescue.c rename to src/main/cms/cms_menu_gps_rescue_multirotor.c index 9b2cbbb948..a6520d0734 100644 --- a/src/main/cms/cms_menu_gps_rescue.c +++ b/src/main/cms/cms_menu_gps_rescue_multirotor.c @@ -25,6 +25,8 @@ #include "platform.h" +#ifndef USE_WING + #ifdef USE_CMS_GPS_RESCUE_MENU #include "cli/settings.h" @@ -242,3 +244,5 @@ CMS_Menu cmsx_menuGpsRescue = { }; #endif + +#endif // !USE_WING diff --git a/src/main/cms/cms_menu_gps_rescue_wing.c b/src/main/cms/cms_menu_gps_rescue_wing.c new file mode 100644 index 0000000000..0e2e0a78b5 --- /dev/null +++ b/src/main/cms/cms_menu_gps_rescue_wing.c @@ -0,0 +1,114 @@ +/* + * This file is part of Betaflight. + * + * Betaflight is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * Betaflight is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Betaflight. If not, see . + */ + +#include +#include +#include +#include + +#include "platform.h" + +#ifdef USE_WING + +#ifdef USE_CMS_GPS_RESCUE_MENU + +#include "cli/settings.h" + +#include "cms/cms.h" +#include "cms/cms_types.h" +#include "cms/cms_menu_gps_rescue.h" + +#include "config/feature.h" + +#include "config/config.h" + +#include "flight/position.h" + +#include "pg/autopilot.h" +#include "pg/gps_rescue.h" + +static const void *cms_menuGpsRescuePidOnEnter(displayPort_t *pDisp) +{ + UNUSED(pDisp); + + return NULL; +} + +static const void *cms_menuGpsRescuePidOnExit(displayPort_t *pDisp, const OSD_Entry *self) +{ + UNUSED(pDisp); + UNUSED(self); + + return NULL; +} + +const OSD_Entry cms_menuGpsRescuePidEntries[] = +{ + {"--- GPS RESCUE PID---", OME_Label, NULL, NULL}, + + {"BACK", OME_Back, NULL, NULL}, + {NULL, OME_END, NULL, NULL} +}; + +CMS_Menu cms_menuGpsRescuePid = { +#ifdef CMS_MENU_DEBUG + .GUARD_text = "MENUGPSRPID", + .GUARD_type = OME_MENU, +#endif + .onEnter = cms_menuGpsRescuePidOnEnter, + .onExit = cms_menuGpsRescuePidOnExit, + .onDisplayUpdate = NULL, + .entries = cms_menuGpsRescuePidEntries, +}; + +static const void *cmsx_menuGpsRescueOnEnter(displayPort_t *pDisp) +{ + UNUSED(pDisp); + + return NULL; +} + +static const void *cmsx_menuGpsRescueOnExit(displayPort_t *pDisp, const OSD_Entry *self) +{ + UNUSED(pDisp); + UNUSED(self); + + return NULL; +} + +const OSD_Entry cmsx_menuGpsRescueEntries[] = +{ + {"--- GPS RESCUE ---", OME_Label, NULL, NULL}, + + {"BACK", OME_Back, NULL, NULL}, + {NULL, OME_END, NULL, NULL} +}; + +CMS_Menu cmsx_menuGpsRescue = { +#ifdef CMS_MENU_DEBUG + .GUARD_text = "MENUGPSRES", + .GUARD_type = OME_MENU, +#endif + .onEnter = cmsx_menuGpsRescueOnEnter, + .onExit = cmsx_menuGpsRescueOnExit, + .onDisplayUpdate = NULL, + .entries = cmsx_menuGpsRescueEntries, +}; + +#endif + +#endif // USE_WING diff --git a/src/main/flight/alt_hold.h b/src/main/flight/alt_hold.h index c82d6c9b6e..875006c24f 100644 --- a/src/main/flight/alt_hold.h +++ b/src/main/flight/alt_hold.h @@ -17,15 +17,5 @@ #pragma once -#include "pg/alt_hold.h" - -#ifdef USE_ALTITUDE_HOLD -#include "common/time.h" - -#define ALTHOLD_TASK_RATE_HZ 100 // hz - -void altHoldInit(void); -void updateAltHold(timeUs_t currentTimeUs); -bool isAltHoldActive(void); - -#endif +#include "flight/alt_hold_multirotor.h" +#include "flight/alt_hold_wing.h" diff --git a/src/main/flight/alt_hold.c b/src/main/flight/alt_hold_multirotor.c similarity index 97% rename from src/main/flight/alt_hold.c rename to src/main/flight/alt_hold_multirotor.c index 97c301e9c0..7c089cb165 100644 --- a/src/main/flight/alt_hold.c +++ b/src/main/flight/alt_hold_multirotor.c @@ -16,6 +16,9 @@ */ #include "platform.h" + +#ifndef USE_WING + #include "math.h" #ifdef USE_ALTITUDE_HOLD @@ -90,8 +93,8 @@ void altHoldProcessTransitions(void) { void altHoldUpdateTargetAltitude(void) { // User can adjust the target altitude with throttle, but only when - // - throttle is outside deadband, and - // - throttle is not low (zero), and + // - throttle is outside deadband, and + // - throttle is not low (zero), and // - deadband is not configured to zero float stickFactor = 0.0f; @@ -154,3 +157,5 @@ bool isAltHoldActive(void) { return altHold.isActive; } #endif + +#endif // !USE_WING diff --git a/src/main/flight/alt_hold_multirotor.h b/src/main/flight/alt_hold_multirotor.h new file mode 100644 index 0000000000..c18cd9a6e6 --- /dev/null +++ b/src/main/flight/alt_hold_multirotor.h @@ -0,0 +1,35 @@ +/* + * This file is part of Betaflight. + * + * Betaflight is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * Betaflight is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Betaflight. If not, see . + */ + +#pragma once + +#ifndef USE_WING + +#include "pg/alt_hold.h" + +#ifdef USE_ALTITUDE_HOLD +#include "common/time.h" + +#define ALTHOLD_TASK_RATE_HZ 100 // hz + +void altHoldInit(void); +void updateAltHold(timeUs_t currentTimeUs); +bool isAltHoldActive(void); + +#endif + +#endif // !USE_WING diff --git a/src/main/flight/alt_hold_wing.c b/src/main/flight/alt_hold_wing.c new file mode 100644 index 0000000000..05b0db18c2 --- /dev/null +++ b/src/main/flight/alt_hold_wing.c @@ -0,0 +1,59 @@ +/* + * This file is part of Betaflight. + * + * Betaflight is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * Betaflight is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Betaflight. If not, see . + */ + +#include "platform.h" + +#ifdef USE_WING + +#include "math.h" + +#ifdef USE_ALTITUDE_HOLD + +#include "build/debug.h" +#include "common/maths.h" +#include "config/config.h" + +#include "fc/rc.h" +#include "fc/runtime_config.h" + +#include "flight/autopilot.h" +#include "flight/failsafe.h" +#include "flight/position.h" + +#include "rx/rx.h" +#include "pg/autopilot.h" + +#include "alt_hold.h" + +void altHoldReset(void) +{ +} + +void altHoldInit(void) +{ +} + +void updateAltHold(timeUs_t currentTimeUs) { + UNUSED(currentTimeUs); +} + +bool isAltHoldActive(void) { + return false; +} + +#endif // USE_ALTITUDE_HOLD +#endif // USE_WING diff --git a/src/main/flight/alt_hold_wing.h b/src/main/flight/alt_hold_wing.h new file mode 100644 index 0000000000..12da834876 --- /dev/null +++ b/src/main/flight/alt_hold_wing.h @@ -0,0 +1,35 @@ +/* + * This file is part of Betaflight. + * + * Betaflight is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * Betaflight is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Betaflight. If not, see . + */ + +#pragma once + +#ifdef USE_WING + +#include "pg/alt_hold.h" + +#ifdef USE_ALTITUDE_HOLD +#include "common/time.h" + +#define ALTHOLD_TASK_RATE_HZ 100 // hz + +void altHoldInit(void); +void updateAltHold(timeUs_t currentTimeUs); +bool isAltHoldActive(void); + +#endif + +#endif // USE_WING diff --git a/src/main/flight/autopilot.h b/src/main/flight/autopilot.h index dbdaaea120..98860bedae 100644 --- a/src/main/flight/autopilot.h +++ b/src/main/flight/autopilot.h @@ -19,16 +19,5 @@ #include "io/gps.h" -extern float autopilotAngle[RP_AXIS_COUNT]; // NOTE: ANGLES ARE IN CENTIDEGREES - -void autopilotInit(void); -void resetAltitudeControl(void); -void setSticksActiveStatus(bool areSticksActive); -void resetPositionControl(const gpsLocation_t *initialTargetLocation, unsigned taskRateHz); -void posControlOutput(void); -bool positionControl(void); -void altitudeControl(float targetAltitudeCm, float taskIntervalS, float targetAltitudeStep); - -bool isBelowLandingAltitude(void); -float getAutopilotThrottle(void); -bool isAutopilotInControl(void); +#include "flight/autopilot_multirotor.h" +#include "flight/autopilot_wing.h" diff --git a/src/main/flight/autopilot.c b/src/main/flight/autopilot_multirotor.c similarity index 99% rename from src/main/flight/autopilot.c rename to src/main/flight/autopilot_multirotor.c index 8a41219b5f..c70635599a 100644 --- a/src/main/flight/autopilot.c +++ b/src/main/flight/autopilot_multirotor.c @@ -21,6 +21,9 @@ #include #include "platform.h" + +#ifndef USE_WING + #include "build/debug.h" #include "common/axis.h" #include "common/filter.h" @@ -395,3 +398,5 @@ bool isAutopilotInControl(void) { return !ap.sticksActive; } + +#endif // !USE_WING diff --git a/src/main/flight/autopilot_multirotor.h b/src/main/flight/autopilot_multirotor.h new file mode 100644 index 0000000000..6fe44bbd2a --- /dev/null +++ b/src/main/flight/autopilot_multirotor.h @@ -0,0 +1,38 @@ +/* + * This file is part of Betaflight. + * + * Betaflight is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * Betaflight is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Betaflight. If not, see . + */ + +#pragma once + +#ifndef USE_WING + +#include "io/gps.h" + +extern float autopilotAngle[RP_AXIS_COUNT]; // NOTE: ANGLES ARE IN CENTIDEGREES + +void autopilotInit(void); +void resetAltitudeControl(void); +void setSticksActiveStatus(bool areSticksActive); +void resetPositionControl(const gpsLocation_t *initialTargetLocation, unsigned taskRateHz); +void posControlOutput(void); +bool positionControl(void); +void altitudeControl(float targetAltitudeCm, float taskIntervalS, float targetAltitudeStep); + +bool isBelowLandingAltitude(void); +float getAutopilotThrottle(void); +bool isAutopilotInControl(void); + +#endif // !USE_WING diff --git a/src/main/flight/autopilot_wing.c b/src/main/flight/autopilot_wing.c new file mode 100644 index 0000000000..936933f446 --- /dev/null +++ b/src/main/flight/autopilot_wing.c @@ -0,0 +1,91 @@ +/* + * This file is part of Betaflight. + * + * Betaflight is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * Betaflight is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Betaflight. If not, see . + */ + +#include +#include +#include +#include + +#include "platform.h" + +#ifdef USE_WING + +#include "build/debug.h" +#include "common/axis.h" +#include "common/filter.h" +#include "common/maths.h" +#include "common/vector.h" +#include "fc/rc.h" +#include "fc/runtime_config.h" + +#include "flight/imu.h" +#include "flight/position.h" +#include "rx/rx.h" +#include "sensors/gyro.h" + +#include "pg/autopilot.h" +#include "autopilot.h" + +float autopilotAngle[RP_AXIS_COUNT]; + +void resetPositionControl(const gpsLocation_t *initialTargetLocation, unsigned taskRateHz) +{ + // from pos_hold.c (or other client) when initiating position hold at target location + UNUSED(initialTargetLocation); + UNUSED(taskRateHz); +} + +void autopilotInit(void) +{ +} + +void resetAltitudeControl (void) { +} + +void altitudeControl(float targetAltitudeCm, float taskIntervalS, float targetAltitudeStep) +{ + UNUSED(targetAltitudeCm); + UNUSED(taskIntervalS); + UNUSED(targetAltitudeStep); +} + +void setSticksActiveStatus(bool areSticksActive) +{ + UNUSED(areSticksActive); +} + +bool positionControl(void) +{ + return false; +} + +bool isBelowLandingAltitude(void) +{ + return false; +} + +float getAutopilotThrottle(void) +{ + return 0.0f; +} + +bool isAutopilotInControl(void) +{ + return false; +} + +#endif // USE_WING diff --git a/src/main/flight/autopilot_wing.h b/src/main/flight/autopilot_wing.h new file mode 100644 index 0000000000..db7efdda4d --- /dev/null +++ b/src/main/flight/autopilot_wing.h @@ -0,0 +1,37 @@ +/* + * This file is part of Betaflight. + * + * Betaflight is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * Betaflight is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Betaflight. If not, see . + */ + +#pragma once + +#ifdef USE_WING + +#include "io/gps.h" + +extern float autopilotAngle[RP_AXIS_COUNT]; // NOTE: ANGLES ARE IN CENTIDEGREES + +void autopilotInit(void); +void resetAltitudeControl(void); +void setSticksActiveStatus(bool areSticksActive); +void resetPositionControl(const gpsLocation_t *initialTargetLocation, unsigned taskRateHz); +bool positionControl(void); +void altitudeControl(float targetAltitudeCm, float taskIntervalS, float targetAltitudeStep); + +bool isBelowLandingAltitude(void); +float getAutopilotThrottle(void); +bool isAutopilotInControl(void); + +#endif // USE_WING diff --git a/src/main/flight/gps_rescue.h b/src/main/flight/gps_rescue.h index c2e60e34b8..5dbe982e9d 100644 --- a/src/main/flight/gps_rescue.h +++ b/src/main/flight/gps_rescue.h @@ -17,41 +17,5 @@ #pragma once -#include - -#include "common/axis.h" - -#include "pg/gps_rescue.h" - -#define TASK_GPS_RESCUE_RATE_HZ 100 // in sync with altitude task rate - -#ifdef USE_MAG -#define GPS_RESCUE_USE_MAG true -#else -#define GPS_RESCUE_USE_MAG false -#endif - -typedef enum { - RESCUE_SANITY_OFF = 0, - RESCUE_SANITY_ON, - RESCUE_SANITY_FS_ONLY, - RESCUE_SANITY_COUNT -} gpsRescueSanity_e; - -typedef enum { - GPS_RESCUE_ALT_MODE_MAX = 0, - GPS_RESCUE_ALT_MODE_FIXED, - GPS_RESCUE_ALT_MODE_CURRENT, - GPS_RESCUE_ALT_MODE_COUNT -} gpsRescueAltitudeMode_e; - -extern float gpsRescueAngle[RP_AXIS_COUNT]; // NOTE: ANGLES ARE IN CENTIDEGREES - -void gpsRescueInit(void); -void gpsRescueUpdate(void); -float gpsRescueGetYawRate(void); -bool gpsRescueIsConfigured(void); -bool gpsRescueIsAvailable(void); -bool gpsRescueIsDisabled(void); -bool gpsRescueDisableMag(void); -float gpsRescueGetImuYawCogGain(void); +#include "flight/gps_rescue_multirotor.h" +#include "flight/gps_rescue_wing.h" diff --git a/src/main/flight/gps_rescue.c b/src/main/flight/gps_rescue_multirotor.c similarity index 99% rename from src/main/flight/gps_rescue.c rename to src/main/flight/gps_rescue_multirotor.c index e70715b369..c88295d9dc 100644 --- a/src/main/flight/gps_rescue.c +++ b/src/main/flight/gps_rescue_multirotor.c @@ -21,6 +21,7 @@ #include "platform.h" +#ifndef USE_WING #ifdef USE_GPS_RESCUE #include "build/debug.h" @@ -138,7 +139,7 @@ void gpsRescueInit(void) rescueState.intent.velocityPidCutoffModifier = 1.0f; gain = pt1FilterGain(cutoffHz, 1.0f); pt1FilterInit(&velocityDLpf, gain); - cutoffHz *= 4.0f; + cutoffHz *= 4.0f; gain = pt3FilterGain(cutoffHz, taskIntervalSeconds); pt3FilterInit(&velocityUpsampleLpf, gain); } @@ -887,3 +888,5 @@ bool gpsRescueDisableMag(void) } #endif #endif + +#endif // !USE_WING diff --git a/src/main/flight/gps_rescue_multirotor.h b/src/main/flight/gps_rescue_multirotor.h new file mode 100644 index 0000000000..dfb2087b83 --- /dev/null +++ b/src/main/flight/gps_rescue_multirotor.h @@ -0,0 +1,61 @@ +/* + * This file is part of Betaflight. + * + * Betaflight is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * Betaflight is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Betaflight. If not, see . + */ + +#pragma once + +#ifndef USE_WING + +#include + +#include "common/axis.h" + +#include "pg/gps_rescue.h" + +#define TASK_GPS_RESCUE_RATE_HZ 100 // in sync with altitude task rate + +#ifdef USE_MAG +#define GPS_RESCUE_USE_MAG true +#else +#define GPS_RESCUE_USE_MAG false +#endif + +typedef enum { + RESCUE_SANITY_OFF = 0, + RESCUE_SANITY_ON, + RESCUE_SANITY_FS_ONLY, + RESCUE_SANITY_COUNT +} gpsRescueSanity_e; + +typedef enum { + GPS_RESCUE_ALT_MODE_MAX = 0, + GPS_RESCUE_ALT_MODE_FIXED, + GPS_RESCUE_ALT_MODE_CURRENT, + GPS_RESCUE_ALT_MODE_COUNT +} gpsRescueAltitudeMode_e; + +extern float gpsRescueAngle[RP_AXIS_COUNT]; // NOTE: ANGLES ARE IN CENTIDEGREES + +void gpsRescueInit(void); +void gpsRescueUpdate(void); +float gpsRescueGetYawRate(void); +bool gpsRescueIsConfigured(void); +bool gpsRescueIsAvailable(void); +bool gpsRescueIsDisabled(void); +bool gpsRescueDisableMag(void); +float gpsRescueGetImuYawCogGain(void); + +#endif // !USE_WING diff --git a/src/main/flight/gps_rescue_wing.c b/src/main/flight/gps_rescue_wing.c new file mode 100644 index 0000000000..218e0c41b6 --- /dev/null +++ b/src/main/flight/gps_rescue_wing.c @@ -0,0 +1,100 @@ +/* + * This file is part of Betaflight. + * + * Betaflight is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * Betaflight is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Betaflight. If not, see . + */ + +#include +#include +#include + +#include "platform.h" + +#ifdef USE_WING +#ifdef USE_GPS_RESCUE + +#include "build/debug.h" + +#include "common/axis.h" +#include "common/filter.h" +#include "common/maths.h" +#include "common/utils.h" + +#include "config/config.h" +#include "drivers/time.h" + +#include "fc/core.h" +#include "fc/rc_controls.h" +#include "fc/rc_modes.h" +#include "fc/runtime_config.h" + +#include "flight/autopilot.h" +#include "flight/failsafe.h" +#include "flight/imu.h" +#include "flight/pid.h" +#include "flight/position.h" + +#include "io/gps.h" +#include "rx/rx.h" +#include "pg/autopilot.h" +#include "sensors/acceleration.h" + +#include "gps_rescue.h" + +float gpsRescueAngle[RP_AXIS_COUNT] = { 0, 0 }; + +void gpsRescueInit(void) +{ +} + +void gpsRescueUpdate(void) +// runs at gpsRescueTaskIntervalSeconds, and runs whether or not rescue is active +{ +} + +float gpsRescueGetYawRate(void) +{ + return 0.0f; // the control yaw value for rc.c to be used while flightMode gps_rescue is active. +} + +float gpsRescueGetImuYawCogGain(void) +{ + return 1.0f; +} + +bool gpsRescueIsConfigured(void) +{ + return false; +} + +bool gpsRescueIsAvailable(void) +{ + return false; +} + +bool gpsRescueIsDisabled(void) +{ + return true; +} + +#ifdef USE_MAG +bool gpsRescueDisableMag(void) +{ + return true; +} +#endif + +#endif // USE_GPS_RESCUE + +#endif // USE_WING diff --git a/src/main/flight/gps_rescue_wing.h b/src/main/flight/gps_rescue_wing.h new file mode 100644 index 0000000000..fbaa001236 --- /dev/null +++ b/src/main/flight/gps_rescue_wing.h @@ -0,0 +1,41 @@ +/* + * This file is part of Betaflight. + * + * Betaflight is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * Betaflight is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Betaflight. If not, see . + */ + +#pragma once + +#ifdef USE_WING + +#include + +#include "common/axis.h" + +#include "pg/gps_rescue.h" + +#define TASK_GPS_RESCUE_RATE_HZ 100 // in sync with altitude task rate + +extern float gpsRescueAngle[RP_AXIS_COUNT]; // NOTE: ANGLES ARE IN CENTIDEGREES + +void gpsRescueInit(void); +void gpsRescueUpdate(void); +float gpsRescueGetYawRate(void); +bool gpsRescueIsConfigured(void); +bool gpsRescueIsAvailable(void); +bool gpsRescueIsDisabled(void); +bool gpsRescueDisableMag(void); +float gpsRescueGetImuYawCogGain(void); + +#endif // USE_WING diff --git a/src/main/flight/pid.c b/src/main/flight/pid.c index 094ff0aea4..4d5f0dad80 100644 --- a/src/main/flight/pid.c +++ b/src/main/flight/pid.c @@ -570,7 +570,7 @@ STATIC_UNIT_TESTED FAST_CODE_NOINLINE float pidLevel(int axis, const pidProfile_ #ifdef USE_GPS_RESCUE angleTarget += gpsRescueAngle[axis] / 100.0f; // Angle is in centidegrees, stepped on roll at 10Hz but not on pitch #endif -#ifdef USE_POSITION_HOLD +#if defined(USE_POSITION_HOLD) && !defined(USE_WING) if (FLIGHT_MODE(POS_HOLD_MODE)) { angleFeedforward = 0.0f; // otherwise the lag of the PT3 carries recent stick inputs into the hold if (isAutopilotInControl()) { @@ -1127,7 +1127,7 @@ void FAST_CODE pidController(const pidProfile_t *pidProfile, timeUs_t currentTim || FLIGHT_MODE(ALT_HOLD_MODE) // todo - check if this is needed #endif #ifdef USE_POSITION_HOLD - || FLIGHT_MODE(POS_HOLD_MODE) + || FLIGHT_MODE(POS_HOLD_MODE) #endif ; levelMode_e levelMode; diff --git a/src/main/flight/pos_hold.h b/src/main/flight/pos_hold.h index 97ddb7bdbd..a777c05c0d 100644 --- a/src/main/flight/pos_hold.h +++ b/src/main/flight/pos_hold.h @@ -17,17 +17,5 @@ #pragma once -// #include "pg/pos_hold.h" - -#ifdef USE_POSITION_HOLD -#include "common/time.h" -#include "io/gps.h" - -#define POSHOLD_TASK_RATE_HZ 100 // hz - -void posHoldInit(void); -void updatePosHold(timeUs_t currentTimeUs); - -bool posHoldFailure(void); - -#endif +#include "flight/pos_hold_multirotor.h" +#include "flight/pos_hold_wing.h" diff --git a/src/main/flight/pos_hold.c b/src/main/flight/pos_hold_multirotor.c similarity index 95% rename from src/main/flight/pos_hold.c rename to src/main/flight/pos_hold_multirotor.c index 38e07a8455..a3723885e4 100644 --- a/src/main/flight/pos_hold.c +++ b/src/main/flight/pos_hold_multirotor.c @@ -17,6 +17,8 @@ #include "platform.h" +#ifndef USE_WING + #ifdef USE_POSITION_HOLD #include "math.h" @@ -55,7 +57,7 @@ void posHoldInit(void) void posHoldCheckSticks(void) { - // if failsafe is active, eg landing mode, don't update the original start point + // if failsafe is active, eg landing mode, don't update the original start point if (!failsafeIsActive() && posHold.useStickAdjustment) { const bool sticksDeflected = (getRcDeflectionAbs(FD_ROLL) > posHold.deadband) || (getRcDeflectionAbs(FD_PITCH) > posHold.deadband); setSticksActiveStatus(sticksDeflected); @@ -65,20 +67,20 @@ void posHoldCheckSticks(void) bool sensorsOk(void) { if (!STATE(GPS_FIX)) { - return false; + return false; } if ( #ifdef USE_MAG !compassIsHealthy() && #endif (!posHoldConfig()->pos_hold_without_mag || !canUseGPSHeading)) { - return false; + return false; } return true; } void updatePosHold(timeUs_t currentTimeUs) { - UNUSED(currentTimeUs); + UNUSED(currentTimeUs); if (FLIGHT_MODE(POS_HOLD_MODE)) { if (!posHold.isEnabled) { resetPositionControl(&gpsSol.llh, POSHOLD_TASK_RATE_HZ); // sets target location to current location @@ -104,3 +106,5 @@ bool posHoldFailure(void) { } #endif // USE_POS_HOLD + +#endif // !USE_WING diff --git a/src/main/flight/pos_hold_multirotor.h b/src/main/flight/pos_hold_multirotor.h new file mode 100644 index 0000000000..9b3e078419 --- /dev/null +++ b/src/main/flight/pos_hold_multirotor.h @@ -0,0 +1,37 @@ +/* + * This file is part of Betaflight. + * + * Betaflight is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * Betaflight is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Betaflight. If not, see . + */ + +#pragma once + +#ifndef USE_WING + +// #include "pg/pos_hold.h" + +#ifdef USE_POSITION_HOLD +#include "common/time.h" +#include "io/gps.h" + +#define POSHOLD_TASK_RATE_HZ 100 // hz + +void posHoldInit(void); +void updatePosHold(timeUs_t currentTimeUs); + +bool posHoldFailure(void); + +#endif // USE_POSITION_HOLD + +#endif // !USE_WING diff --git a/src/main/flight/pos_hold_wing.c b/src/main/flight/pos_hold_wing.c new file mode 100644 index 0000000000..fac189426f --- /dev/null +++ b/src/main/flight/pos_hold_wing.c @@ -0,0 +1,57 @@ +/* + * This file is part of Betaflight. + * + * Betaflight is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * Betaflight is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Betaflight. If not, see . + */ + +#include "platform.h" + +#ifdef USE_WING + +#ifdef USE_POSITION_HOLD + +#include "math.h" +#include "build/debug.h" +#include "common/maths.h" + +#include "config/config.h" +#include "fc/core.h" +#include "fc/runtime_config.h" +#include "fc/rc.h" +#include "flight/autopilot.h" +#include "flight/failsafe.h" +#include "flight/imu.h" +#include "flight/position.h" +#include "rx/rx.h" +#include "sensors/compass.h" + +#include "pg/pos_hold.h" +#include "pos_hold.h" + +void posHoldInit(void) +{ +} + +void updatePosHold(timeUs_t currentTimeUs) { + UNUSED(currentTimeUs); +} + +bool posHoldFailure(void) { + // used only to display warning in OSD if requested but failing + return true; +} + +#endif // USE_POS_HOLD + +#endif // USE_WING diff --git a/src/main/flight/pos_hold_wing.h b/src/main/flight/pos_hold_wing.h new file mode 100644 index 0000000000..3ab33e2c69 --- /dev/null +++ b/src/main/flight/pos_hold_wing.h @@ -0,0 +1,37 @@ +/* + * This file is part of Betaflight. + * + * Betaflight is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * Betaflight is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Betaflight. If not, see . + */ + +#pragma once + +#ifdef USE_WING + +// #include "pg/pos_hold.h" + +#ifdef USE_POSITION_HOLD +#include "common/time.h" +#include "io/gps.h" + +#define POSHOLD_TASK_RATE_HZ 100 // hz + +void posHoldInit(void); +void updatePosHold(timeUs_t currentTimeUs); + +bool posHoldFailure(void); + +#endif + +#endif // USE_WING diff --git a/src/main/msp/msp.c b/src/main/msp/msp.c index f41866de0f..d0bf9e563a 100644 --- a/src/main/msp/msp.c +++ b/src/main/msp/msp.c @@ -1533,6 +1533,7 @@ case MSP_NAME: break; #ifdef USE_GPS_RESCUE +#ifndef USE_WING case MSP_GPS_RESCUE: sbufWriteU16(dst, gpsRescueConfig()->maxRescueAngle); sbufWriteU16(dst, gpsRescueConfig()->returnAltitudeM); @@ -1565,6 +1566,7 @@ case MSP_NAME: sbufWriteU16(dst, gpsRescueConfig()->velD); sbufWriteU16(dst, gpsRescueConfig()->yawP); break; +#endif // !USE_WING #endif #endif @@ -1802,7 +1804,7 @@ case MSP_NAME: case MSP_RC_DEADBAND: sbufWriteU8(dst, rcControlsConfig()->deadband); sbufWriteU8(dst, rcControlsConfig()->yaw_deadband); -#ifdef USE_POSITION_HOLD +#if defined(USE_POSITION_HOLD) && !defined(USE_WING) sbufWriteU8(dst, posHoldConfig()->pos_hold_deadband); #else sbufWriteU8(dst, 0); @@ -2879,6 +2881,7 @@ static mspResult_e mspProcessInCommand(mspDescriptor_t srcDesc, int16_t cmdMSP, #ifdef USE_GPS #ifdef USE_GPS_RESCUE +#ifndef USE_WING case MSP_SET_GPS_RESCUE: gpsRescueConfigMutable()->maxRescueAngle = sbufReadU16(src); gpsRescueConfigMutable()->returnAltitudeM = sbufReadU16(src); @@ -2916,6 +2919,7 @@ static mspResult_e mspProcessInCommand(mspDescriptor_t srcDesc, int16_t cmdMSP, gpsRescueConfigMutable()->velD = sbufReadU16(src); gpsRescueConfigMutable()->yawP = sbufReadU16(src); break; +#endif // !USE_WING #endif #endif @@ -2971,7 +2975,7 @@ static mspResult_e mspProcessInCommand(mspDescriptor_t srcDesc, int16_t cmdMSP, case MSP_SET_RC_DEADBAND: rcControlsConfigMutable()->deadband = sbufReadU8(src); rcControlsConfigMutable()->yaw_deadband = sbufReadU8(src); -#ifdef USE_POSITION_HOLD +#if defined(USE_POSITION_HOLD) && !defined(USE_WING) posHoldConfigMutable()->pos_hold_deadband = sbufReadU8(src); #else sbufReadU8(src); diff --git a/src/main/pg/alt_hold.h b/src/main/pg/alt_hold.h index 9c24f6c275..869cd4c8d1 100644 --- a/src/main/pg/alt_hold.h +++ b/src/main/pg/alt_hold.h @@ -21,13 +21,5 @@ #pragma once -#include - -#include "pg/pg.h" - -typedef struct altHoldConfig_s { - uint8_t alt_hold_adjust_rate; - uint8_t alt_hold_deadband; -} altHoldConfig_t; - -PG_DECLARE(altHoldConfig_t, altHoldConfig); +#include "pg/alt_hold_multirotor.h" +#include "pg/alt_hold_wing.h" diff --git a/src/main/pg/alt_hold.c b/src/main/pg/alt_hold_multirotor.c similarity index 96% rename from src/main/pg/alt_hold.c rename to src/main/pg/alt_hold_multirotor.c index 716fd18a50..c229fcf66a 100644 --- a/src/main/pg/alt_hold.c +++ b/src/main/pg/alt_hold_multirotor.c @@ -21,6 +21,8 @@ #include "platform.h" +#ifndef USE_WING + #ifdef USE_ALTITUDE_HOLD #include "flight/alt_hold.h" @@ -37,3 +39,5 @@ PG_RESET_TEMPLATE(altHoldConfig_t, altHoldConfig, .alt_hold_deadband = 20, // throttle deadband in percent of stick travel ); #endif + +#endif // USE_WING diff --git a/src/main/pg/alt_hold_multirotor.h b/src/main/pg/alt_hold_multirotor.h new file mode 100644 index 0000000000..88f0933b0c --- /dev/null +++ b/src/main/pg/alt_hold_multirotor.h @@ -0,0 +1,37 @@ +/* + * This file is part of Betaflight. + * + * Betaflight is free software. You can redistribute this software + * and/or modify this software under the terms of the GNU General + * Public License as published by the Free Software Foundation, + * either version 3 of the License, or (at your option) any later + * version. + * + * Betaflight is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * See the GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this software. + * + * If not, see . + */ + +#pragma once + +#ifndef USE_WING + +#include + +#include "pg/pg.h" + +typedef struct altHoldConfig_s { + uint8_t alt_hold_adjust_rate; + uint8_t alt_hold_deadband; +} altHoldConfig_t; + +PG_DECLARE(altHoldConfig_t, altHoldConfig); + +#endif // !USE_WING diff --git a/src/main/pg/alt_hold_wing.c b/src/main/pg/alt_hold_wing.c new file mode 100644 index 0000000000..7b59cbce5a --- /dev/null +++ b/src/main/pg/alt_hold_wing.c @@ -0,0 +1,41 @@ +/* + * This file is part of Betaflight. + * + * Betaflight is free software. You can redistribute this software + * and/or modify this software under the terms of the GNU General + * Public License as published by the Free Software Foundation, + * either version 3 of the License, or (at your option) any later + * version. + * + * Betaflight is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * See the GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this software. + * + * If not, see . + */ + +#include "platform.h" + +#ifdef USE_WING + +#ifdef USE_ALTITUDE_HOLD + +#include "flight/alt_hold.h" + +#include "pg/pg.h" +#include "pg/pg_ids.h" + +#include "alt_hold.h" + +PG_REGISTER_WITH_RESET_TEMPLATE(altHoldConfig_t, altHoldConfig, PG_ALTHOLD_CONFIG, 4); + +PG_RESET_TEMPLATE(altHoldConfig_t, altHoldConfig, +); +#endif + +#endif // USE_WING diff --git a/src/main/pg/alt_hold_wing.h b/src/main/pg/alt_hold_wing.h new file mode 100644 index 0000000000..d3ca1754a0 --- /dev/null +++ b/src/main/pg/alt_hold_wing.h @@ -0,0 +1,36 @@ +/* + * This file is part of Betaflight. + * + * Betaflight is free software. You can redistribute this software + * and/or modify this software under the terms of the GNU General + * Public License as published by the Free Software Foundation, + * either version 3 of the License, or (at your option) any later + * version. + * + * Betaflight is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * See the GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this software. + * + * If not, see . + */ + +#pragma once + +#ifdef USE_WING + +#include + +#include "pg/pg.h" + +typedef struct altHoldConfig_s { + uint8_t dummy; +} altHoldConfig_t; + +PG_DECLARE(altHoldConfig_t, altHoldConfig); + +#endif // USE_WING diff --git a/src/main/pg/autopilot.h b/src/main/pg/autopilot.h index 018498dfba..720dcea2e3 100644 --- a/src/main/pg/autopilot.h +++ b/src/main/pg/autopilot.h @@ -21,26 +21,5 @@ #pragma once -#include - -#include "pg/pg.h" - -typedef struct apConfig_s { - uint8_t landing_altitude_m; // altitude below which landing behaviours can change, metres - uint16_t hover_throttle; // value used at the start of a rescue or position hold - uint16_t throttle_min; - uint16_t throttle_max; - uint8_t altitude_P; - uint8_t altitude_I; - uint8_t altitude_D; - uint8_t altitude_F; - uint8_t position_P; - uint8_t position_I; - uint8_t position_D; - uint8_t position_A; - uint8_t position_cutoff; - uint8_t max_angle; -} apConfig_t; - -PG_DECLARE(apConfig_t, apConfig); - +#include "pg/autopilot_multirotor.h" +#include "pg/autopilot_wing.h" diff --git a/src/main/pg/autopilot.c b/src/main/pg/autopilot_multirotor.c similarity index 97% rename from src/main/pg/autopilot.c rename to src/main/pg/autopilot_multirotor.c index 6b0fa1564b..898cfdc205 100644 --- a/src/main/pg/autopilot.c +++ b/src/main/pg/autopilot_multirotor.c @@ -21,6 +21,8 @@ #include "platform.h" +#ifndef USE_WING + #include "flight/autopilot.h" #include "pg/pg.h" @@ -46,3 +48,5 @@ PG_RESET_TEMPLATE(apConfig_t, apConfig, .position_cutoff = 80, .max_angle = 50, ); + +#endif // !USE_WING diff --git a/src/main/pg/autopilot_multirotor.h b/src/main/pg/autopilot_multirotor.h new file mode 100644 index 0000000000..6e1f6cfecd --- /dev/null +++ b/src/main/pg/autopilot_multirotor.h @@ -0,0 +1,49 @@ +/* + * This file is part of Betaflight. + * + * Betaflight is free software. You can redistribute this software + * and/or modify this software under the terms of the GNU General + * Public License as published by the Free Software Foundation, + * either version 3 of the License, or (at your option) any later + * version. + * + * Betaflight is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * See the GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this software. + * + * If not, see . + */ + +#pragma once + +#ifndef USE_WING + +#include + +#include "pg/pg.h" + +typedef struct apConfig_s { + uint8_t landing_altitude_m; // altitude below which landing behaviours can change, metres + uint16_t hover_throttle; // value used at the start of a rescue or position hold + uint16_t throttle_min; + uint16_t throttle_max; + uint8_t altitude_P; + uint8_t altitude_I; + uint8_t altitude_D; + uint8_t altitude_F; + uint8_t position_P; + uint8_t position_I; + uint8_t position_D; + uint8_t position_A; + uint8_t position_cutoff; + uint8_t max_angle; +} apConfig_t; + +PG_DECLARE(apConfig_t, apConfig); + +#endif // !USE_WING diff --git a/src/main/pg/autopilot_wing.c b/src/main/pg/autopilot_wing.c new file mode 100644 index 0000000000..06dc476c1c --- /dev/null +++ b/src/main/pg/autopilot_wing.c @@ -0,0 +1,38 @@ +/* + * This file is part of Betaflight. + * + * Betaflight is free software. You can redistribute this software + * and/or modify this software under the terms of the GNU General + * Public License as published by the Free Software Foundation, + * either version 3 of the License, or (at your option) any later + * version. + * + * Betaflight is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * See the GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this software. + * + * If not, see . + */ + +#include "platform.h" + +#ifdef USE_WING + +#include "flight/autopilot.h" + +#include "pg/pg.h" +#include "pg/pg_ids.h" + +#include "autopilot.h" + +PG_REGISTER_WITH_RESET_TEMPLATE(apConfig_t, apConfig, PG_AUTOPILOT, 2); + +PG_RESET_TEMPLATE(apConfig_t, apConfig, +); + +#endif // USE_WING diff --git a/src/main/pg/autopilot_wing.h b/src/main/pg/autopilot_wing.h new file mode 100644 index 0000000000..ee01e0a6f9 --- /dev/null +++ b/src/main/pg/autopilot_wing.h @@ -0,0 +1,36 @@ +/* + * This file is part of Betaflight. + * + * Betaflight is free software. You can redistribute this software + * and/or modify this software under the terms of the GNU General + * Public License as published by the Free Software Foundation, + * either version 3 of the License, or (at your option) any later + * version. + * + * Betaflight is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * See the GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this software. + * + * If not, see . + */ + +#pragma once + +#ifdef USE_WING + +#include + +#include "pg/pg.h" + +typedef struct apConfig_s { + uint8_t dummy; +} apConfig_t; + +PG_DECLARE(apConfig_t, apConfig); + +#endif // USE_WING diff --git a/src/main/pg/gps_rescue.h b/src/main/pg/gps_rescue.h index b2bfc3c83d..558d891127 100644 --- a/src/main/pg/gps_rescue.h +++ b/src/main/pg/gps_rescue.h @@ -1,50 +1,21 @@ /* - * This file is part of Cleanflight and Betaflight. + * This file is part of Betaflight. * - * Cleanflight and Betaflight are free software. You can redistribute - * this software and/or modify this software under the terms of the - * GNU General Public License as published by the Free Software - * Foundation, either version 3 of the License, or (at your option) - * any later version. + * Betaflight is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. * - * Cleanflight and Betaflight are distributed in the hope that they - * will be useful, but WITHOUT ANY WARRANTY; without even the implied - * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * See the GNU General Public License for more details. + * Betaflight is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License - * along with this software. - * - * If not, see . + * along with Betaflight. If not, see . */ #pragma once -#include - -#include "pg/pg.h" - -typedef struct gpsRescue_s { - - uint16_t maxRescueAngle; // degrees - uint16_t returnAltitudeM; // meters - uint16_t descentDistanceM; // meters - uint16_t groundSpeedCmS; // centimeters per second - uint8_t yawP; - uint8_t minSats; - uint8_t velP, velI, velD; - uint16_t minStartDistM; // meters - uint8_t sanityChecks; - uint8_t allowArmingWithoutFix; - uint8_t useMag; - uint8_t altitudeMode; - uint16_t ascendRate; - uint16_t descendRate; - uint16_t initialClimbM; // meters - uint8_t rollMix; - uint8_t disarmThreshold; - uint8_t pitchCutoffHz; - uint8_t imuYawGain; -} gpsRescueConfig_t; - -PG_DECLARE(gpsRescueConfig_t, gpsRescueConfig); +#include "pg/gps_rescue_multirotor.h" +#include "pg/gps_rescue_wing.h" diff --git a/src/main/pg/gps_rescue.c b/src/main/pg/gps_rescue_multirotor.c similarity index 97% rename from src/main/pg/gps_rescue.c rename to src/main/pg/gps_rescue_multirotor.c index 1fd66bbbeb..7767d9bc5c 100644 --- a/src/main/pg/gps_rescue.c +++ b/src/main/pg/gps_rescue_multirotor.c @@ -20,6 +20,8 @@ #include "platform.h" +#ifndef USE_WING + #ifdef USE_GPS_RESCUE #include "flight/gps_rescue.h" @@ -62,3 +64,5 @@ PG_RESET_TEMPLATE(gpsRescueConfig_t, gpsRescueConfig, ); #endif // USE_GPS_RESCUE + +#endif // !USE_WING diff --git a/src/main/pg/gps_rescue_multirotor.h b/src/main/pg/gps_rescue_multirotor.h new file mode 100644 index 0000000000..28ff8b52ae --- /dev/null +++ b/src/main/pg/gps_rescue_multirotor.h @@ -0,0 +1,54 @@ +/* + * This file is part of Cleanflight and Betaflight. + * + * Cleanflight and Betaflight are free software. You can redistribute + * this software and/or modify this software under the terms of the + * GNU General Public License as published by the Free Software + * Foundation, either version 3 of the License, or (at your option) + * any later version. + * + * Cleanflight and Betaflight are distributed in the hope that they + * will be useful, but WITHOUT ANY WARRANTY; without even the implied + * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * See the GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this software. + * + * If not, see . + */ + +#pragma once + +#ifndef USE_WING + +#include + +#include "pg/pg.h" + +typedef struct gpsRescue_s { + + uint16_t maxRescueAngle; // degrees + uint16_t returnAltitudeM; // meters + uint16_t descentDistanceM; // meters + uint16_t groundSpeedCmS; // centimeters per second + uint8_t yawP; + uint8_t minSats; + uint8_t velP, velI, velD; + uint16_t minStartDistM; // meters + uint8_t sanityChecks; + uint8_t allowArmingWithoutFix; + uint8_t useMag; + uint8_t altitudeMode; + uint16_t ascendRate; + uint16_t descendRate; + uint16_t initialClimbM; // meters + uint8_t rollMix; + uint8_t disarmThreshold; + uint8_t pitchCutoffHz; + uint8_t imuYawGain; +} gpsRescueConfig_t; + +PG_DECLARE(gpsRescueConfig_t, gpsRescueConfig); + +#endif // !USE_WING diff --git a/src/main/pg/gps_rescue_wing.c b/src/main/pg/gps_rescue_wing.c new file mode 100644 index 0000000000..cea370130a --- /dev/null +++ b/src/main/pg/gps_rescue_wing.c @@ -0,0 +1,40 @@ +/* + * This file is part of Betaflight. + * + * Betaflight is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * Betaflight is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Betaflight. If not, see . + */ + +#include "platform.h" + +#ifdef USE_WING + +#ifdef USE_GPS_RESCUE + +#include "flight/gps_rescue.h" + +#include "pg/pg.h" +#include "pg/pg_ids.h" + +#include "gps_rescue.h" + +PG_REGISTER_WITH_RESET_TEMPLATE(gpsRescueConfig_t, gpsRescueConfig, PG_GPS_RESCUE, 7); + +PG_RESET_TEMPLATE(gpsRescueConfig_t, gpsRescueConfig, + .allowArmingWithoutFix = false, + .minSats = 8, +); + +#endif // USE_GPS_RESCUE + +#endif // USE_WING diff --git a/src/main/pg/gps_rescue_wing.h b/src/main/pg/gps_rescue_wing.h new file mode 100644 index 0000000000..b53ff6ba48 --- /dev/null +++ b/src/main/pg/gps_rescue_wing.h @@ -0,0 +1,33 @@ +/* + * This file is part of Betaflight. + * + * Betaflight is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * Betaflight is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Betaflight. If not, see . + */ + +#pragma once + +#ifdef USE_WING + +#include + +#include "pg/pg.h" + +typedef struct gpsRescue_s { + uint8_t allowArmingWithoutFix; + uint8_t minSats; +} gpsRescueConfig_t; + +PG_DECLARE(gpsRescueConfig_t, gpsRescueConfig); + +#endif // USE_WING diff --git a/src/main/pg/pos_hold.h b/src/main/pg/pos_hold.h index eedf9e1a3d..c4019ad42f 100644 --- a/src/main/pg/pos_hold.h +++ b/src/main/pg/pos_hold.h @@ -21,13 +21,5 @@ #pragma once -#include - -#include "pg/pg.h" - -typedef struct posHoldConfig_s { - bool pos_hold_without_mag; - uint8_t pos_hold_deadband; -} posHoldConfig_t; - -PG_DECLARE(posHoldConfig_t, posHoldConfig); +#include "pg/pos_hold_multirotor.h" +#include "pg/pos_hold_wing.h" diff --git a/src/main/pg/pos_hold.c b/src/main/pg/pos_hold_multirotor.c similarity index 97% rename from src/main/pg/pos_hold.c rename to src/main/pg/pos_hold_multirotor.c index df291446ab..2a7a332241 100644 --- a/src/main/pg/pos_hold.c +++ b/src/main/pg/pos_hold_multirotor.c @@ -21,6 +21,8 @@ #include "platform.h" +#ifndef USE_WING + #ifdef USE_POSITION_HOLD #include "flight/pos_hold.h" @@ -37,3 +39,5 @@ PG_RESET_TEMPLATE(posHoldConfig_t, posHoldConfig, .pos_hold_deadband = 5, // deadband in percent of stick travel for roll and pitch. Must be non-zero, and exceeded, for target location to be changed with sticks ); #endif + +#endif // !USE_WING diff --git a/src/main/pg/pos_hold_multirotor.h b/src/main/pg/pos_hold_multirotor.h new file mode 100644 index 0000000000..6187d9ba62 --- /dev/null +++ b/src/main/pg/pos_hold_multirotor.h @@ -0,0 +1,37 @@ +/* + * This file is part of Betaflight. + * + * Betaflight is free software. You can redistribute this software + * and/or modify this software under the terms of the GNU General + * Public License as published by the Free Software Foundation, + * either version 3 of the License, or (at your option) any later + * version. + * + * Betaflight is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * See the GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this software. + * + * If not, see . + */ + +#pragma once + +#ifndef USE_WING + +#include + +#include "pg/pg.h" + +typedef struct posHoldConfig_s { + bool pos_hold_without_mag; + uint8_t pos_hold_deadband; +} posHoldConfig_t; + +PG_DECLARE(posHoldConfig_t, posHoldConfig); + +#endif // !USE_WING diff --git a/src/main/pg/pos_hold_wing.c b/src/main/pg/pos_hold_wing.c new file mode 100644 index 0000000000..f90579f534 --- /dev/null +++ b/src/main/pg/pos_hold_wing.c @@ -0,0 +1,41 @@ +/* + * This file is part of Betaflight. + * + * Betaflight is free software. You can redistribute this software + * and/or modify this software under the terms of the GNU General + * Public License as published by the Free Software Foundation, + * either version 3 of the License, or (at your option) any later + * version. + * + * Betaflight is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * See the GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this software. + * + * If not, see . + */ + +#include "platform.h" + +#ifdef USE_WING + +#ifdef USE_POSITION_HOLD + +#include "flight/pos_hold.h" + +#include "pg/pg.h" +#include "pg/pg_ids.h" + +#include "pos_hold.h" + +PG_REGISTER_WITH_RESET_TEMPLATE(posHoldConfig_t, posHoldConfig, PG_POSHOLD_CONFIG, 0); + +PG_RESET_TEMPLATE(posHoldConfig_t, posHoldConfig, +); +#endif + +#endif // USE_WING diff --git a/src/main/pg/pos_hold_wing.h b/src/main/pg/pos_hold_wing.h new file mode 100644 index 0000000000..c194a488a9 --- /dev/null +++ b/src/main/pg/pos_hold_wing.h @@ -0,0 +1,36 @@ +/* + * This file is part of Betaflight. + * + * Betaflight is free software. You can redistribute this software + * and/or modify this software under the terms of the GNU General + * Public License as published by the Free Software Foundation, + * either version 3 of the License, or (at your option) any later + * version. + * + * Betaflight is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * See the GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this software. + * + * If not, see . + */ + +#pragma once + +#ifdef USE_WING + +#include + +#include "pg/pg.h" + +typedef struct posHoldConfig_s { + uint8_t dummy; +} posHoldConfig_t; + +PG_DECLARE(posHoldConfig_t, posHoldConfig); + +#endif // !USE_WING diff --git a/src/test/Makefile b/src/test/Makefile index ca4c302b83..b6d2153b97 100644 --- a/src/test/Makefile +++ b/src/test/Makefile @@ -37,8 +37,8 @@ alignsensor_unittest_SRC := \ $(USER_DIR)/common/vector.c althold_unittest_SRC := \ - $(USER_DIR)/flight/alt_hold.c \ - $(USER_DIR)/flight/autopilot.c \ + $(USER_DIR)/flight/alt_hold_multirotor.c \ + $(USER_DIR)/flight/autopilot_multirotor.c \ $(USER_DIR)/common/maths.c \ $(USER_DIR)/common/vector.c \ $(USER_DIR)/common/filter.c \ @@ -56,8 +56,8 @@ arming_prevention_unittest_SRC := \ $(USER_DIR)/fc/rc_controls.c \ $(USER_DIR)/fc/rc_modes.c \ $(USER_DIR)/fc/runtime_config.c \ - $(USER_DIR)/flight/autopilot.c \ - $(USER_DIR)/flight/gps_rescue.c + $(USER_DIR)/flight/autopilot_multirotor.c \ + $(USER_DIR)/flight/gps_rescue_multirotor.c arming_prevention_unittest_DEFINES := \ USE_GPS_RESCUE= From 38928085f26d7e0d1d5825100b69b2fe68bff004 Mon Sep 17 00:00:00 2001 From: Mark Haslinghuis Date: Tue, 31 Dec 2024 20:06:39 +0100 Subject: [PATCH 017/244] Adds missing ACCGYRO defines and remove legacy drivers (#14087) --- mk/source.mk | 20 - src/main/cli/settings.c | 43 +- src/main/drivers/accgyro/accgyro.h | 3 +- src/main/drivers/accgyro/accgyro_mpu.c | 2 - src/main/drivers/accgyro/accgyro_mpu3050.c | 114 ----- src/main/drivers/accgyro/accgyro_mpu3050.h | 32 -- src/main/drivers/accgyro/accgyro_mpu6500.c | 7 + .../drivers/accgyro/accgyro_spi_icm20689.c | 4 + .../drivers/accgyro/accgyro_spi_mpu6500.c | 4 + .../drivers/accgyro/accgyro_spi_mpu9250.c | 4 + .../drivers/accgyro/legacy/accgyro_adxl345.c | 139 ------ .../drivers/accgyro/legacy/accgyro_adxl345.h | 28 -- .../drivers/accgyro/legacy/accgyro_bma280.c | 76 --- .../drivers/accgyro/legacy/accgyro_bma280.h | 23 - .../drivers/accgyro/legacy/accgyro_l3g4200d.c | 119 ----- .../drivers/accgyro/legacy/accgyro_l3g4200d.h | 23 - .../accgyro/legacy/accgyro_lsm303dlhc.c | 171 ------- .../accgyro/legacy/accgyro_lsm303dlhc.h | 434 ------------------ .../drivers/accgyro/legacy/accgyro_mma845x.c | 144 ------ .../drivers/accgyro/legacy/accgyro_mma845x.h | 23 - src/main/sensors/acceleration.c | 2 +- src/main/sensors/acceleration.h | 5 +- src/main/sensors/acceleration_init.c | 82 +--- src/main/sensors/acceleration_init.h | 2 +- src/main/sensors/gyro_init.c | 48 +- src/main/target/common_post.h | 45 +- 26 files changed, 114 insertions(+), 1483 deletions(-) delete mode 100644 src/main/drivers/accgyro/accgyro_mpu3050.c delete mode 100644 src/main/drivers/accgyro/accgyro_mpu3050.h delete mode 100644 src/main/drivers/accgyro/legacy/accgyro_adxl345.c delete mode 100644 src/main/drivers/accgyro/legacy/accgyro_adxl345.h delete mode 100644 src/main/drivers/accgyro/legacy/accgyro_bma280.c delete mode 100644 src/main/drivers/accgyro/legacy/accgyro_bma280.h delete mode 100644 src/main/drivers/accgyro/legacy/accgyro_l3g4200d.c delete mode 100644 src/main/drivers/accgyro/legacy/accgyro_l3g4200d.h delete mode 100644 src/main/drivers/accgyro/legacy/accgyro_lsm303dlhc.c delete mode 100644 src/main/drivers/accgyro/legacy/accgyro_lsm303dlhc.h delete mode 100644 src/main/drivers/accgyro/legacy/accgyro_mma845x.c delete mode 100644 src/main/drivers/accgyro/legacy/accgyro_mma845x.h diff --git a/mk/source.mk b/mk/source.mk index e4c60d55cb..a9a8ed0e49 100644 --- a/mk/source.mk +++ b/mk/source.mk @@ -290,7 +290,6 @@ ifneq ($(SIMULATOR_BUILD),yes) COMMON_SRC += \ drivers/bus_spi.c \ drivers/serial_uart.c \ - drivers/accgyro/accgyro_mpu3050.c \ drivers/accgyro/accgyro_mpu6050.c \ drivers/accgyro/accgyro_mpu6500.c \ drivers/accgyro/accgyro_mpu.c \ @@ -332,24 +331,6 @@ COMMON_SRC += \ drivers/vtx_rtc6705.c \ drivers/vtx_rtc6705_soft_spi.c -ifneq ($(GYRO_DEFINE),) - -LEGACY_GYRO_DEFINES := USE_GYRO_L3GD20 -ifneq ($(findstring $(GYRO_DEFINE),$(LEGACY_GYRO_DEFINES)),) - -LEGACY_SRC := \ - drivers/accgyro/legacy/accgyro_adxl345.c \ - drivers/accgyro/legacy/accgyro_bma280.c \ - drivers/accgyro/legacy/accgyro_l3g4200d.c \ - drivers/accgyro/legacy/accgyro_lsm303dlhc.c \ - drivers/accgyro/legacy/accgyro_mma845x.c - -COMMON_SRC += $(LEGACY_SRC) -SPEED_OPTIMISED_SRC += $(LEGACY_SRC) - -endif -endif - RX_SRC = \ drivers/rx/expresslrs_driver.c \ drivers/rx/rx_a7105.c \ @@ -425,7 +406,6 @@ SPEED_OPTIMISED_SRC += \ drivers/bus_spi.c \ drivers/serial_uart.c \ drivers/accgyro/accgyro_mpu.c \ - drivers/accgyro/accgyro_mpu3050.c \ drivers/accgyro/accgyro_spi_bmi160.c \ drivers/accgyro/accgyro_spi_bmi270.c \ drivers/accgyro/accgyro_spi_lsm6dso.c diff --git a/src/main/cli/settings.c b/src/main/cli/settings.c index 1bfe829b79..9a9a749093 100644 --- a/src/main/cli/settings.c +++ b/src/main/cli/settings.c @@ -143,16 +143,47 @@ // Sensor names (used in lookup tables for *_hardware settings and in status command output) // sync with accelerationSensor_e const char * const lookupTableAccHardware[] = { - "AUTO", "NONE", "ADXL345", "MPU6050", "MMA8452", "BMA280", "LSM303DLHC", - "MPU6000", "MPU6500", "MPU9250", "ICM20601", "ICM20602", "ICM20608G", "ICM20649", "ICM20689", "ICM42605", "ICM42688P", - "BMI160", "BMI270", "LSM6DSO", "LSM6DSV16X", "VIRTUAL" + "AUTO", + "NONE", + "MPU6050", + "MPU6000", + "MPU6500", + "MPU9250", + "ICM20601", + "ICM20602", + "ICM20608G", + "ICM20649", + "ICM20689", + "ICM42605", + "ICM42688P", + "BMI160", + "BMI270", + "LSM6DSO", + "LSM6DSV16X", + "VIRTUAL" }; // sync with gyroHardware_e const char * const lookupTableGyroHardware[] = { - "AUTO", "NONE", "MPU6050", "L3G4200D", "MPU3050", "L3GD20", - "MPU6000", "MPU6500", "MPU9250", "ICM20601", "ICM20602", "ICM20608G", "ICM20649", "ICM20689", "ICM42605", "ICM42688P", - "BMI160", "BMI270", "LSM6DSO", "LSM6DSV16X", "VIRTUAL" + "AUTO", + "NONE", + "MPU6050", + "L3GD20", + "MPU6000", + "MPU6500", + "MPU9250", + "ICM20601", + "ICM20602", + "ICM20608G", + "ICM20649", + "ICM20689", + "ICM42605", + "ICM42688P", + "BMI160", + "BMI270", + "LSM6DSO", + "LSM6DSV16X", + "VIRTUAL" }; #if defined(USE_SENSOR_NAMES) || defined(USE_BARO) diff --git a/src/main/drivers/accgyro/accgyro.h b/src/main/drivers/accgyro/accgyro.h index e4d6926031..0c63a8258f 100644 --- a/src/main/drivers/accgyro/accgyro.h +++ b/src/main/drivers/accgyro/accgyro.h @@ -41,12 +41,11 @@ #define GYRO_SCALE_2000DPS (2000.0f / (1 << 15)) // 16.384 dps/lsb scalefactor for 2000dps sensors #define GYRO_SCALE_4000DPS (4000.0f / (1 << 15)) // 8.192 dps/lsb scalefactor for 4000dps sensors +// Gyro hardware types were updated in PR #14087 (removed GYRO_L3G4200D, GYRO_MPU3050) typedef enum { GYRO_NONE = 0, GYRO_DEFAULT, GYRO_MPU6050, - GYRO_L3G4200D, - GYRO_MPU3050, GYRO_L3GD20, GYRO_MPU6000, GYRO_MPU6500, diff --git a/src/main/drivers/accgyro/accgyro_mpu.c b/src/main/drivers/accgyro/accgyro_mpu.c index 4febfe2382..d1ebe2857a 100644 --- a/src/main/drivers/accgyro/accgyro_mpu.c +++ b/src/main/drivers/accgyro/accgyro_mpu.c @@ -43,7 +43,6 @@ #include "drivers/time.h" #include "drivers/accgyro/accgyro.h" -#include "drivers/accgyro/accgyro_mpu3050.h" #include "drivers/accgyro/accgyro_mpu6050.h" #include "drivers/accgyro/accgyro_mpu6500.h" #include "drivers/accgyro/accgyro_spi_bmi160.h" @@ -452,7 +451,6 @@ bool mpuDetect(gyroDev_t *gyro, const gyroDeviceConfig_t *config) if (ack) { busDeviceRegister(&gyro->dev); - // If an MPU3050 is connected sig will contain 0. uint8_t inquiryResult; ack = busReadRegisterBuffer(&gyro->dev, MPU_RA_WHO_AM_I_LEGACY, &inquiryResult, 1); inquiryResult &= MPU_INQUIRY_MASK; diff --git a/src/main/drivers/accgyro/accgyro_mpu3050.c b/src/main/drivers/accgyro/accgyro_mpu3050.c deleted file mode 100644 index a52b1a7984..0000000000 --- a/src/main/drivers/accgyro/accgyro_mpu3050.c +++ /dev/null @@ -1,114 +0,0 @@ -/* - * This file is part of Cleanflight and Betaflight. - * - * Cleanflight and Betaflight are free software. You can redistribute - * this software and/or modify this software under the terms of the - * GNU General Public License as published by the Free Software - * Foundation, either version 3 of the License, or (at your option) - * any later version. - * - * Cleanflight and Betaflight are distributed in the hope that they - * will be useful, but WITHOUT ANY WARRANTY; without even the implied - * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * See the GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this software. - * - * If not, see . - */ - -// NOTE: This gyro is considered obsolete and may be removed in the future. - -#include -#include - -#include "platform.h" - -#ifdef USE_GYRO_MPU3050 - -#include "common/maths.h" -#include "common/utils.h" - -#include "drivers/bus_i2c.h" -#include "drivers/exti.h" -#include "drivers/sensor.h" -#include "drivers/system.h" -#include "drivers/time.h" - -#include "accgyro.h" -#include "accgyro_mpu.h" -#include "accgyro_mpu3050.h" - -// MPU3050, Standard address 0x68 -#define MPU3050_ADDRESS 0x68 - -// Bits -#define MPU3050_FS_SEL_2000DPS 0x18 -#define MPU3050_DLPF_10HZ 0x05 -#define MPU3050_DLPF_20HZ 0x04 -#define MPU3050_DLPF_42HZ 0x03 -#define MPU3050_DLPF_98HZ 0x02 -#define MPU3050_DLPF_188HZ 0x01 -#define MPU3050_DLPF_256HZ 0x00 - -#define MPU3050_USER_RESET 0x01 -#define MPU3050_CLK_SEL_PLL_GX 0x01 - -static void mpu3050Init(gyroDev_t *gyro) -{ - delay(25); // datasheet page 13 says 20ms. other stuff could have been running meanwhile. but we'll be safe - - const bool ack = busWriteRegister(&gyro->bus, MPU3050_SMPLRT_DIV, 0); - if (!ack) { - failureMode(FAILURE_ACC_INIT); - } - - busWriteRegister(&gyro->bus, MPU3050_DLPF_FS_SYNC, MPU3050_FS_SEL_2000DPS | MPU3050_DLPF_256HZ); - busWriteRegister(&gyro->bus, MPU3050_INT_CFG, 0); - busWriteRegister(&gyro->bus, MPU3050_USER_CTRL, MPU3050_USER_RESET); - busWriteRegister(&gyro->bus, MPU3050_PWR_MGM, MPU3050_CLK_SEL_PLL_GX); -} - -static bool mpu3050GyroRead(gyroDev_t *gyro) -{ - uint8_t data[6]; - - const bool ack = busReadRegisterBuffer(&gyro->bus, MPU3050_GYRO_OUT, data, 6); - if (!ack) { - return false; - } - - gyro->gyroADCRaw[X] = (int16_t)((data[0] << 8) | data[1]); - gyro->gyroADCRaw[Y] = (int16_t)((data[2] << 8) | data[3]); - gyro->gyroADCRaw[Z] = (int16_t)((data[4] << 8) | data[5]); - - return true; -} - -static bool mpu3050ReadTemperature(gyroDev_t *gyro, int16_t *tempData) -{ - uint8_t buf[2]; - if (!busReadRegisterBuffer(&gyro->bus, MPU3050_TEMP_OUT, buf, 2)) { - return false; - } - - *tempData = 35 + ((int32_t)(buf[0] << 8 | buf[1]) + 13200) / 280; - - return true; -} - -bool mpu3050Detect(gyroDev_t *gyro) -{ - if (gyro->mpuDetectionResult.sensor != MPU_3050) { - return false; - } - gyro->initFn = mpu3050Init; - gyro->readFn = mpu3050GyroRead; - gyro->temperatureFn = mpu3050ReadTemperature; - - gyro->scale = GYRO_SCALE_2000DPS; - - return true; -} -#endif diff --git a/src/main/drivers/accgyro/accgyro_mpu3050.h b/src/main/drivers/accgyro/accgyro_mpu3050.h deleted file mode 100644 index 3de31fae84..0000000000 --- a/src/main/drivers/accgyro/accgyro_mpu3050.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * This file is part of Cleanflight and Betaflight. - * - * Cleanflight and Betaflight are free software. You can redistribute - * this software and/or modify this software under the terms of the - * GNU General Public License as published by the Free Software - * Foundation, either version 3 of the License, or (at your option) - * any later version. - * - * Cleanflight and Betaflight are distributed in the hope that they - * will be useful, but WITHOUT ANY WARRANTY; without even the implied - * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * See the GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this software. - * - * If not, see . - */ - -#pragma once - -// Registers -#define MPU3050_SMPLRT_DIV 0x15 -#define MPU3050_DLPF_FS_SYNC 0x16 -#define MPU3050_INT_CFG 0x17 -#define MPU3050_TEMP_OUT 0x1B -#define MPU3050_GYRO_OUT 0x1D -#define MPU3050_USER_CTRL 0x3D -#define MPU3050_PWR_MGM 0x3E - -bool mpu3050Detect(gyroDev_t *gyro); diff --git a/src/main/drivers/accgyro/accgyro_mpu6500.c b/src/main/drivers/accgyro/accgyro_mpu6500.c index e4a0c86dfc..ae607d303a 100644 --- a/src/main/drivers/accgyro/accgyro_mpu6500.c +++ b/src/main/drivers/accgyro/accgyro_mpu6500.c @@ -24,6 +24,11 @@ #include "platform.h" +#if defined(USE_ACC_SPI_MPU6500) \ + || defined(USE_GYRO_SPI_MPU6500) \ + || defined(USE_ACC_MPU6500) \ + || defined(USE_GYRO_MPU6500) + #include "common/axis.h" #include "common/maths.h" @@ -108,3 +113,5 @@ bool mpu6500GyroDetect(gyroDev_t *gyro) return true; } + +#endif // USE_ACC_SPI_MPU6500 || USE_GYRO_SPI_MPU6500 || USE_ACC_MPU6500 || USE_GYRO_MPU6500 diff --git a/src/main/drivers/accgyro/accgyro_spi_icm20689.c b/src/main/drivers/accgyro/accgyro_spi_icm20689.c index ada4dadf78..3a15d0f057 100644 --- a/src/main/drivers/accgyro/accgyro_spi_icm20689.c +++ b/src/main/drivers/accgyro/accgyro_spi_icm20689.c @@ -24,6 +24,8 @@ #include "platform.h" +#if defined(USE_ACC_SPI_ICM20689) || defined(USE_GYRO_SPI_ICM20689) + #include "common/axis.h" #include "common/maths.h" @@ -187,3 +189,5 @@ bool icm20689SpiGyroDetect(gyroDev_t *gyro) return true; } + +#endif // USE_ACC_SPI_ICM20689 || USE_GYRO_SPI_ICM20689 diff --git a/src/main/drivers/accgyro/accgyro_spi_mpu6500.c b/src/main/drivers/accgyro/accgyro_spi_mpu6500.c index 9691c77818..7a2e02408b 100644 --- a/src/main/drivers/accgyro/accgyro_spi_mpu6500.c +++ b/src/main/drivers/accgyro/accgyro_spi_mpu6500.c @@ -23,6 +23,8 @@ #include "platform.h" +#if defined(USE_ACC_SPI_MPU6500) || defined(USE_GYRO_SPI_MPU6500) + #include "common/axis.h" #include "common/maths.h" @@ -146,3 +148,5 @@ bool mpu6500SpiGyroDetect(gyroDev_t *gyro) return true; } + +#endif // USE_ACC_SPI_MPU6500 || USE_GYRO_SPI_MPU6500 diff --git a/src/main/drivers/accgyro/accgyro_spi_mpu9250.c b/src/main/drivers/accgyro/accgyro_spi_mpu9250.c index 633a614d29..eca0f03b6d 100644 --- a/src/main/drivers/accgyro/accgyro_spi_mpu9250.c +++ b/src/main/drivers/accgyro/accgyro_spi_mpu9250.c @@ -30,6 +30,8 @@ #include "platform.h" +#ifdef USE_ACC_SPI_MPU9250 + #include "common/axis.h" #include "common/maths.h" @@ -173,3 +175,5 @@ bool mpu9250SpiGyroDetect(gyroDev_t *gyro) return true; } + +#endif // USE_ACC_SPI_MPU9250 diff --git a/src/main/drivers/accgyro/legacy/accgyro_adxl345.c b/src/main/drivers/accgyro/legacy/accgyro_adxl345.c deleted file mode 100644 index d64cd9fccb..0000000000 --- a/src/main/drivers/accgyro/legacy/accgyro_adxl345.c +++ /dev/null @@ -1,139 +0,0 @@ -/* - * This file is part of Cleanflight and Betaflight. - * - * Cleanflight and Betaflight are free software. You can redistribute - * this software and/or modify this software under the terms of the - * GNU General Public License as published by the Free Software - * Foundation, either version 3 of the License, or (at your option) - * any later version. - * - * Cleanflight and Betaflight are distributed in the hope that they - * will be useful, but WITHOUT ANY WARRANTY; without even the implied - * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * See the GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this software. - * - * If not, see . - */ - -#include -#include - -#include "platform.h" - -#ifdef USE_ACC_ADXL345 - -#include "drivers/bus_i2c.h" - -#include "drivers/sensor.h" -#include "drivers/accgyro/accgyro.h" -#include "accgyro_adxl345.h" - -// ADXL345, Alternative address mode 0x53 -#define ADXL345_ADDRESS 0x53 - -// Registers -#define ADXL345_BW_RATE 0x2C -#define ADXL345_POWER_CTL 0x2D -#define ADXL345_INT_ENABLE 0x2E -#define ADXL345_DATA_FORMAT 0x31 -#define ADXL345_DATA_OUT 0x32 -#define ADXL345_FIFO_CTL 0x38 - -// BW_RATE values -#define ADXL345_RATE_50 0x09 -#define ADXL345_RATE_100 0x0A -#define ADXL345_RATE_200 0x0B -#define ADXL345_RATE_400 0x0C -#define ADXL345_RATE_800 0x0D -#define ADXL345_RATE_1600 0x0E -#define ADXL345_RATE_3200 0x0F - -// various register values -#define ADXL345_POWER_MEAS 0x08 -#define ADXL345_FULL_RANGE 0x08 -#define ADXL345_RANGE_2G 0x00 -#define ADXL345_RANGE_4G 0x01 -#define ADXL345_RANGE_8G 0x02 -#define ADXL345_RANGE_16G 0x03 -#define ADXL345_FIFO_STREAM 0x80 - -static bool useFifo = false; - -static void adxl345Init(accDev_t *acc) -{ - if (useFifo) { - uint8_t fifoDepth = 16; - i2cWrite(MPU_I2C_INSTANCE, ADXL345_ADDRESS, ADXL345_POWER_CTL, ADXL345_POWER_MEAS); - i2cWrite(MPU_I2C_INSTANCE, ADXL345_ADDRESS, ADXL345_DATA_FORMAT, ADXL345_FULL_RANGE | ADXL345_RANGE_8G); - i2cWrite(MPU_I2C_INSTANCE, ADXL345_ADDRESS, ADXL345_BW_RATE, ADXL345_RATE_400); - i2cWrite(MPU_I2C_INSTANCE, ADXL345_ADDRESS, ADXL345_FIFO_CTL, (fifoDepth & 0x1F) | ADXL345_FIFO_STREAM); - } else { - i2cWrite(MPU_I2C_INSTANCE, ADXL345_ADDRESS, ADXL345_POWER_CTL, ADXL345_POWER_MEAS); - i2cWrite(MPU_I2C_INSTANCE, ADXL345_ADDRESS, ADXL345_DATA_FORMAT, ADXL345_FULL_RANGE | ADXL345_RANGE_8G); - i2cWrite(MPU_I2C_INSTANCE, ADXL345_ADDRESS, ADXL345_BW_RATE, ADXL345_RATE_100); - } - acc->acc_1G = 256; // 3.3V operation -} - -uint8_t acc_samples = 0; - -static bool adxl345Read(accDev_t *acc) -{ - uint8_t buf[8]; - - if (useFifo) { - int32_t x = 0; - int32_t y = 0; - int32_t z = 0; - uint8_t i = 0; - uint8_t samples_remaining; - - do { - i++; - - if (!i2cRead(MPU_I2C_INSTANCE, ADXL345_ADDRESS, ADXL345_DATA_OUT, 8, buf)) { - return false; - } - - x += (int16_t)(buf[0] + (buf[1] << 8)); - y += (int16_t)(buf[2] + (buf[3] << 8)); - z += (int16_t)(buf[4] + (buf[5] << 8)); - samples_remaining = buf[7] & 0x7F; - } while ((i < 32) && (samples_remaining > 0)); - acc->ADCRaw[0] = x / i; - acc->ADCRaw[1] = y / i; - acc->ADCRaw[2] = z / i; - acc_samples = i; - } else { - - if (!i2cRead(MPU_I2C_INSTANCE, ADXL345_ADDRESS, ADXL345_DATA_OUT, 6, buf)) { - return false; - } - - acc->ADCRaw[0] = buf[0] + (buf[1] << 8); - acc->ADCRaw[1] = buf[2] + (buf[3] << 8); - acc->ADCRaw[2] = buf[4] + (buf[5] << 8); - } - - return true; -} - -bool adxl345Detect(drv_adxl345_config_t *init, accDev_t *acc) -{ - uint8_t sig = 0; - bool ack = i2cRead(MPU_I2C_INSTANCE, ADXL345_ADDRESS, 0x00, 1, &sig); - - if (!ack || sig != 0xE5) - return false; - - // use ADXL345's fifo to filter data or not - useFifo = init->useFifo; - - acc->initFn = adxl345Init; - acc->readFn = adxl345Read; - return true; -} -#endif diff --git a/src/main/drivers/accgyro/legacy/accgyro_adxl345.h b/src/main/drivers/accgyro/legacy/accgyro_adxl345.h deleted file mode 100644 index 27ad0e5b04..0000000000 --- a/src/main/drivers/accgyro/legacy/accgyro_adxl345.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * This file is part of Cleanflight and Betaflight. - * - * Cleanflight and Betaflight are free software. You can redistribute - * this software and/or modify this software under the terms of the - * GNU General Public License as published by the Free Software - * Foundation, either version 3 of the License, or (at your option) - * any later version. - * - * Cleanflight and Betaflight are distributed in the hope that they - * will be useful, but WITHOUT ANY WARRANTY; without even the implied - * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * See the GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this software. - * - * If not, see . - */ - -#pragma once - -typedef struct drv_adxl345_config_s { - uint16_t dataRate; - bool useFifo; -} drv_adxl345_config_t; - -bool adxl345Detect(drv_adxl345_config_t *init, accDev_t *acc); diff --git a/src/main/drivers/accgyro/legacy/accgyro_bma280.c b/src/main/drivers/accgyro/legacy/accgyro_bma280.c deleted file mode 100644 index 5eab61d8ec..0000000000 --- a/src/main/drivers/accgyro/legacy/accgyro_bma280.c +++ /dev/null @@ -1,76 +0,0 @@ -/* - * This file is part of Cleanflight and Betaflight. - * - * Cleanflight and Betaflight are free software. You can redistribute - * this software and/or modify this software under the terms of the - * GNU General Public License as published by the Free Software - * Foundation, either version 3 of the License, or (at your option) - * any later version. - * - * Cleanflight and Betaflight are distributed in the hope that they - * will be useful, but WITHOUT ANY WARRANTY; without even the implied - * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * See the GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this software. - * - * If not, see . - */ - -#include -#include - -#include "platform.h" - -#ifdef USE_ACC_BMA280 - -#include "drivers/bus_i2c.h" - -#include "drivers/sensor.h" -#include "drivers/accgyro/accgyro.h" -#include "accgyro_bma280.h" - -// BMA280, default I2C address mode 0x18 -#define BMA280_ADDRESS 0x18 -#define BMA280_ACC_X_LSB 0x02 -#define BMA280_PMU_BW 0x10 -#define BMA280_PMU_RANGE 0x0F - -static void bma280Init(accDev_t *acc) -{ - i2cWrite(MPU_I2C_INSTANCE, BMA280_ADDRESS, BMA280_PMU_RANGE, 0x08); // +-8g range - i2cWrite(MPU_I2C_INSTANCE, BMA280_ADDRESS, BMA280_PMU_BW, 0x0E); // 500Hz BW - - acc->acc_1G = 512 * 8; -} - -static bool bma280Read(accDev_t *acc) -{ - uint8_t buf[6]; - - if (!i2cRead(MPU_I2C_INSTANCE, BMA280_ADDRESS, BMA280_ACC_X_LSB, 6, buf)) { - return false; - } - - // Data format is lsb<5:0> | msb<13:6> - acc->ADCRaw[0] = (int16_t)((buf[0] >> 2) + (buf[1] << 8)); - acc->ADCRaw[1] = (int16_t)((buf[2] >> 2) + (buf[3] << 8)); - acc->ADCRaw[2] = (int16_t)((buf[4] >> 2) + (buf[5] << 8)); - - return true; -} - -bool bma280Detect(accDev_t *acc) -{ - uint8_t sig = 0; - bool ack = i2cRead(MPU_I2C_INSTANCE, BMA280_ADDRESS, 0x00, 1, &sig); - - if (!ack || sig != 0xFB) - return false; - - acc->initFn = bma280Init; - acc->readFn = bma280Read; - return true; -} -#endif diff --git a/src/main/drivers/accgyro/legacy/accgyro_bma280.h b/src/main/drivers/accgyro/legacy/accgyro_bma280.h deleted file mode 100644 index 93fac71f40..0000000000 --- a/src/main/drivers/accgyro/legacy/accgyro_bma280.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * This file is part of Cleanflight and Betaflight. - * - * Cleanflight and Betaflight are free software. You can redistribute - * this software and/or modify this software under the terms of the - * GNU General Public License as published by the Free Software - * Foundation, either version 3 of the License, or (at your option) - * any later version. - * - * Cleanflight and Betaflight are distributed in the hope that they - * will be useful, but WITHOUT ANY WARRANTY; without even the implied - * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * See the GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this software. - * - * If not, see . - */ - -#pragma once - -bool bma280Detect(accDev_t *acc); diff --git a/src/main/drivers/accgyro/legacy/accgyro_l3g4200d.c b/src/main/drivers/accgyro/legacy/accgyro_l3g4200d.c deleted file mode 100644 index 6dbcf4b96c..0000000000 --- a/src/main/drivers/accgyro/legacy/accgyro_l3g4200d.c +++ /dev/null @@ -1,119 +0,0 @@ -/* - * This file is part of Cleanflight and Betaflight. - * - * Cleanflight and Betaflight are free software. You can redistribute - * this software and/or modify this software under the terms of the - * GNU General Public License as published by the Free Software - * Foundation, either version 3 of the License, or (at your option) - * any later version. - * - * Cleanflight and Betaflight are distributed in the hope that they - * will be useful, but WITHOUT ANY WARRANTY; without even the implied - * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * See the GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this software. - * - * If not, see . - */ - -// NOTE: This gyro is considered obsolete and may be removed in the future. - -#include -#include - -#include "platform.h" - -#ifdef USE_GYRO_L3G4200D - -#include "drivers/accgyro/accgyro.h" -#include "accgyro_l3g4200d.h" - -#include "common/maths.h" -#include "common/axis.h" - -#include "drivers/bus_i2c.h" -#include "drivers/time.h" -#include "drivers/sensor.h" -#include "drivers/system.h" - -// L3G4200D, Standard address 0x68 -#define L3G4200D_ADDRESS 0x68 -#define L3G4200D_ID 0xD3 -#define L3G4200D_AUTOINCR 0x80 - -// Registers -#define L3G4200D_WHO_AM_I 0x0F -#define L3G4200D_CTRL_REG1 0x20 -#define L3G4200D_CTRL_REG2 0x21 -#define L3G4200D_CTRL_REG3 0x22 -#define L3G4200D_CTRL_REG4 0x23 -#define L3G4200D_CTRL_REG5 0x24 -#define L3G4200D_REFERENCE 0x25 -#define L3G4200D_STATUS_REG 0x27 -#define L3G4200D_GYRO_OUT 0x28 - -// Bits -#define L3G4200D_POWER_ON 0x0F -#define L3G4200D_FS_SEL_2000DPS 0xF0 -#define L3G4200D_DLPF_32HZ 0x00 -#define L3G4200D_DLPF_54HZ 0x40 -#define L3G4200D_DLPF_78HZ 0x80 -#define L3G4200D_DLPF_93HZ 0xC0 - -static void l3g4200dInit(gyroDev_t *gyro) -{ - bool ack; - - // Removed lowpass filter selection and just default to 32Hz regardless of gyro->hardware_lpf - // The previous selection was broken anyway as the old gyro->lpf values ranged from 0-7 and - // the switch statement would have always taken the default and used L3G4200D_DLPF_32HZ - - delay(100); - - ack = i2cWrite(MPU_I2C_INSTANCE, L3G4200D_ADDRESS, L3G4200D_CTRL_REG4, L3G4200D_FS_SEL_2000DPS); - if (!ack) - failureMode(FAILURE_ACC_INIT); - - delay(5); - i2cWrite(MPU_I2C_INSTANCE, L3G4200D_ADDRESS, L3G4200D_CTRL_REG1, L3G4200D_POWER_ON | L3G4200D_DLPF_32HZ); - - UNUSED(gyro); -} - -// Read 3 gyro values into user-provided buffer. No overrun checking is done. -static bool l3g4200dRead(gyroDev_t *gyro) -{ - uint8_t buf[6]; - - if (!i2cRead(MPU_I2C_INSTANCE, L3G4200D_ADDRESS, L3G4200D_AUTOINCR | L3G4200D_GYRO_OUT, 6, buf)) { - return false; - } - - gyro->gyroADCRaw[X] = (int16_t)((buf[0] << 8) | buf[1]); - gyro->gyroADCRaw[Y] = (int16_t)((buf[2] << 8) | buf[3]); - gyro->gyroADCRaw[Z] = (int16_t)((buf[4] << 8) | buf[5]); - - return true; -} - -bool l3g4200dDetect(gyroDev_t *gyro) -{ - uint8_t deviceid; - - delay(25); - - i2cRead(MPU_I2C_INSTANCE, L3G4200D_ADDRESS, L3G4200D_WHO_AM_I, 1, &deviceid); - if (deviceid != L3G4200D_ID) - return false; - - gyro->initFn = l3g4200dInit; - gyro->readFn = l3g4200dRead; - - // 14.2857dps/lsb scalefactor - gyro->scale = 1.0f / 14.2857f; - - return true; -} -#endif diff --git a/src/main/drivers/accgyro/legacy/accgyro_l3g4200d.h b/src/main/drivers/accgyro/legacy/accgyro_l3g4200d.h deleted file mode 100644 index 258cc2eeb3..0000000000 --- a/src/main/drivers/accgyro/legacy/accgyro_l3g4200d.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * This file is part of Cleanflight and Betaflight. - * - * Cleanflight and Betaflight are free software. You can redistribute - * this software and/or modify this software under the terms of the - * GNU General Public License as published by the Free Software - * Foundation, either version 3 of the License, or (at your option) - * any later version. - * - * Cleanflight and Betaflight are distributed in the hope that they - * will be useful, but WITHOUT ANY WARRANTY; without even the implied - * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * See the GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this software. - * - * If not, see . - */ - -#pragma once - -bool l3g4200dDetect(gyroDev_t *gyro); diff --git a/src/main/drivers/accgyro/legacy/accgyro_lsm303dlhc.c b/src/main/drivers/accgyro/legacy/accgyro_lsm303dlhc.c deleted file mode 100644 index 21a8831244..0000000000 --- a/src/main/drivers/accgyro/legacy/accgyro_lsm303dlhc.c +++ /dev/null @@ -1,171 +0,0 @@ -/* - * This file is part of Cleanflight and Betaflight. - * - * Cleanflight and Betaflight are free software. You can redistribute - * this software and/or modify this software under the terms of the - * GNU General Public License as published by the Free Software - * Foundation, either version 3 of the License, or (at your option) - * any later version. - * - * Cleanflight and Betaflight are distributed in the hope that they - * will be useful, but WITHOUT ANY WARRANTY; without even the implied - * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * See the GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this software. - * - * If not, see . - */ - -#include -#include - -#include "platform.h" - -#ifdef USE_ACC_LSM303DLHC - -#include "build/debug.h" - -#include "common/maths.h" -#include "common/axis.h" - -#include "drivers/time.h" -#include "drivers/io.h" -#include "drivers/bus_i2c.h" - -#include "drivers/sensor.h" -#include "drivers/accgyro/accgyro.h" -#include "accgyro_lsm303dlhc.h" - -// Addresses (7 bit address format) - -#define LSM303DLHC_ACCEL_ADDRESS 0x19 -#define LSM303DLHC_MAG_ADDRESS 0x1E - -/** - * Address Auto Increment - See LSM303DLHC datasheet, Section 5.1.1 I2C operation. - * http://www.st.com/web/en/resource/technical/document/datasheet/DM00027543.pdf - * - * "The I2C embedded inside the LSM303DLHC behaves like a slave device and the following protocol must be adhered to. - * After the START condition (ST) a slave address is sent, once a slave acknowledge (SAK) has been returned, an 8-bit - * sub-address (SUB) is transmitted; the 7 LSBs represent the actual register address while the MSB enables address - * autoincrement. - * - * If the MSB of the SUB field is ‘1’, the SUB (register address) is automatically increased to allow multiple data - * Read/Write. - * - * To minimize the communication between the master and magnetic digital interface of LSM303DLHC, the address pointer - * updates automatically without master intervention. This automatic address pointer update has two additional - * features. First, when address 12 or higher is accessed, the pointer updates to address 00, and secondly, when - * address 08 is reached, the pointer rolls back to address 03. Logically, the address pointer operation functions - * as shown below. - * 1) If (address pointer = 08) then the address pointer = 03 - * Or else, if (address pointer >= 12) then the address pointer = 0 - * Or else, (address pointer) = (address pointer) + 1 - * - * The address pointer value itself cannot be read via the I2C bus" - */ -#define AUTO_INCREMENT_ENABLE 0x80 - -// Registers - -#define CTRL_REG1_A 0x20 -#define CTRL_REG4_A 0x23 -#define CTRL_REG5_A 0x24 -#define OUT_X_L_A 0x28 -#define CRA_REG_M 0x00 -#define CRB_REG_M 0x01 -#define MR_REG_M 0x02 -#define OUT_X_H_M 0x03 - -/////////////////////////////////////// - -#define ODR_1344_HZ 0x90 -#define AXES_ENABLE 0x07 - -#define FULLSCALE_2G 0x00 -#define FULLSCALE_4G 0x10 -#define FULLSCALE_8G 0x20 -#define FULLSCALE_16G 0x30 - -#define BOOT 0x80 - -/////////////////////////////////////// - -#define ODR_75_HZ 0x18 -#define ODR_15_HZ 0x10 - -#define FS_1P3_GA 0x20 -#define FS_1P9_GA 0x40 -#define FS_2P5_GA 0x60 -#define FS_4P0_GA 0x80 -#define FS_4P7_GA 0xA0 -#define FS_5P6_GA 0xC0 -#define FS_8P1_GA 0xE0 - -#define CONTINUOUS_CONVERSION 0x00 - -uint8_t accelCalibrating = false; - -float accelOneG = 9.8065; - -int32_t accelSum100Hz[3] = { 0, 0, 0 }; - -int32_t accelSum500Hz[3] = { 0, 0, 0 }; - -int32_t accelSummedSamples100Hz[3]; - -int32_t accelSummedSamples500Hz[3]; - -void lsm303dlhcAccInit(accDev_t *acc) -{ - i2cWrite(MPU_I2C_INSTANCE, LSM303DLHC_ACCEL_ADDRESS, CTRL_REG5_A, BOOT); - - delay(100); - - i2cWrite(MPU_I2C_INSTANCE, LSM303DLHC_ACCEL_ADDRESS, CTRL_REG1_A, ODR_1344_HZ | AXES_ENABLE); - - delay(10); - - i2cWrite(MPU_I2C_INSTANCE, LSM303DLHC_ACCEL_ADDRESS, CTRL_REG4_A, FULLSCALE_4G); - - delay(100); - - acc->acc_1G = 512 * 8; -} - -// Read 3 gyro values into user-provided buffer. No overrun checking is done. -static bool lsm303dlhcAccRead(accDev_t *acc) -{ - uint8_t buf[6]; - - bool ack = i2cRead(MPU_I2C_INSTANCE, LSM303DLHC_ACCEL_ADDRESS, AUTO_INCREMENT_ENABLE | OUT_X_L_A, 6, buf); - - if (!ack) { - return false; - } - - // the values range from -8192 to +8191 - acc->ADCRaw[X] = (int16_t)((buf[1] << 8) | buf[0]) / 2; - acc->ADCRaw[Y] = (int16_t)((buf[3] << 8) | buf[2]) / 2; - acc->ADCRaw[Z] = (int16_t)((buf[5] << 8) | buf[4]) / 2; - - return true; -} - -bool lsm303dlhcAccDetect(accDev_t *acc) -{ - bool ack; - uint8_t status; - - ack = i2cRead(MPU_I2C_INSTANCE, LSM303DLHC_ACCEL_ADDRESS, LSM303DLHC_STATUS_REG_A, 1, &status); - if (!ack) { - return false; - } - - acc->initFn = lsm303dlhcAccInit; - acc->readFn = lsm303dlhcAccRead; - return true; -} -#endif diff --git a/src/main/drivers/accgyro/legacy/accgyro_lsm303dlhc.h b/src/main/drivers/accgyro/legacy/accgyro_lsm303dlhc.h deleted file mode 100644 index f8024ddcf1..0000000000 --- a/src/main/drivers/accgyro/legacy/accgyro_lsm303dlhc.h +++ /dev/null @@ -1,434 +0,0 @@ -/* - * This file is part of Cleanflight and Betaflight. - * - * Cleanflight and Betaflight are free software. You can redistribute - * this software and/or modify this software under the terms of the - * GNU General Public License as published by the Free Software - * Foundation, either version 3 of the License, or (at your option) - * any later version. - * - * Cleanflight and Betaflight are distributed in the hope that they - * will be useful, but WITHOUT ANY WARRANTY; without even the implied - * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * See the GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this software. - * - * If not, see . - */ - -#pragma once - -/** - * @brief LSM303DLHC Status - */ - -/* LSM303DLHC ACC struct */ -typedef struct { - uint8_t Power_Mode; /* Power-down/Normal Mode */ - uint8_t AccOutput_DataRate; /* OUT data rate */ - uint8_t Axes_Enable; /* Axes enable */ - uint8_t High_Resolution; /* High Resolution enabling/disabling */ - uint8_t BlockData_Update; /* Block Data Update */ - uint8_t Endianness; /* Endian Data selection */ - uint8_t AccFull_Scale; /* Full Scale selection */ -} LSM303DLHCAcc_InitTypeDef; - -/* LSM303DLHC Acc High Pass Filter struct */ -typedef struct { - uint8_t HighPassFilter_Mode_Selection; /* Internal filter mode */ - uint8_t HighPassFilter_CutOff_Frequency; /* High pass filter cut-off frequency */ - uint8_t HighPassFilter_AOI1; /* HPF_enabling/disabling for AOI function on interrupt 1 */ - uint8_t HighPassFilter_AOI2; /* HPF_enabling/disabling for AOI function on interrupt 2 */ -} LSM303DLHCAcc_FilterConfigTypeDef; - -/* LSM303DLHC Mag struct */ -typedef struct { - uint8_t Temperature_Sensor; /* Temperature sensor enable/disable */ - uint8_t MagOutput_DataRate; /* OUT data rate */ - uint8_t Working_Mode; /* operating mode */ - uint8_t MagFull_Scale; /* Full Scale selection */ -} LSM303DLHCMag_InitTypeDef; -/** - * @} - */ - -/** @defgroup STM32F3_DISCOVERY_LSM303DLHC_Exported_Constants - * @{ - */ -#define LSM303DLHC_OK ((uint32_t) 0) -#define LSM303DLHC_FAIL ((uint32_t) 0) - -/* Uncomment the following line to use the default LSM303DLHC_TIMEOUT_UserCallback() - function implemented in stm32f3_discovery_lgd20.c file. - LSM303DLHC_TIMEOUT_UserCallback() function is called whenever a timeout condition - occure during communication (waiting transmit data register empty flag(TXE) - or waiting receive data register is not empty flag (RXNE)). */ -// #define USE_DEFAULT_TIMEOUT_CALLBACK - -/* Maximum Timeout values for flags waiting loops. These timeouts are not based - on accurate values, they just guarantee that the application will not remain - stuck if the I2C communication is corrupted. - You may modify these timeout values depending on CPU frequency and application - conditions (interrupts routines ...). */ -#define LSM303DLHC_FLAG_TIMEOUT ((uint32_t)0x1000) -#define LSM303DLHC_LONG_TIMEOUT ((uint32_t)(10 * LSM303DLHC_FLAG_TIMEOUT)) - -/******************************************************************************/ -/*************************** START REGISTER MAPPING **************************/ -/******************************************************************************/ -/* Acceleration Registers */ -#define LSM303DLHC_CTRL_REG1_A 0x20 /* Control register 1 acceleration */ -#define LSM303DLHC_CTRL_REG2_A 0x21 /* Control register 2 acceleration */ -#define LSM303DLHC_CTRL_REG3_A 0x22 /* Control register 3 acceleration */ -#define LSM303DLHC_CTRL_REG4_A 0x23 /* Control register 4 acceleration */ -#define LSM303DLHC_CTRL_REG5_A 0x24 /* Control register 5 acceleration */ -#define LSM303DLHC_CTRL_REG6_A 0x25 /* Control register 6 acceleration */ -#define LSM303DLHC_REFERENCE_A 0x26 /* Reference register acceleration */ -#define LSM303DLHC_STATUS_REG_A 0x27 /* Status register acceleration */ -#define LSM303DLHC_OUT_X_L_A 0x28 /* Output Register X acceleration */ -#define LSM303DLHC_OUT_X_H_A 0x29 /* Output Register X acceleration */ -#define LSM303DLHC_OUT_Y_L_A 0x2A /* Output Register Y acceleration */ -#define LSM303DLHC_OUT_Y_H_A 0x2B /* Output Register Y acceleration */ -#define LSM303DLHC_OUT_Z_L_A 0x2C /* Output Register Z acceleration */ -#define LSM303DLHC_OUT_Z_H_A 0x2D /* Output Register Z acceleration */ -#define LSM303DLHC_FIFO_CTRL_REG_A 0x2E /* Fifo control Register acceleration */ -#define LSM303DLHC_FIFO_SRC_REG_A 0x2F /* Fifo src Register acceleration */ - -#define LSM303DLHC_INT1_CFG_A 0x30 /* Interrupt 1 configuration Register acceleration */ -#define LSM303DLHC_INT1_SOURCE_A 0x31 /* Interrupt 1 source Register acceleration */ -#define LSM303DLHC_INT1_THS_A 0x32 /* Interrupt 1 Threshold register acceleration */ -#define LSM303DLHC_INT1_DURATION_A 0x33 /* Interrupt 1 DURATION register acceleration */ - -#define LSM303DLHC_INT2_CFG_A 0x34 /* Interrupt 2 configuration Register acceleration */ -#define LSM303DLHC_INT2_SOURCE_A 0x35 /* Interrupt 2 source Register acceleration */ -#define LSM303DLHC_INT2_THS_A 0x36 /* Interrupt 2 Threshold register acceleration */ -#define LSM303DLHC_INT2_DURATION_A 0x37 /* Interrupt 2 DURATION register acceleration */ - -#define LSM303DLHC_CLICK_CFG_A 0x38 /* Click configuration Register acceleration */ -#define LSM303DLHC_CLICK_SOURCE_A 0x39 /* Click 2 source Register acceleration */ -#define LSM303DLHC_CLICK_THS_A 0x3A /* Click 2 Threshold register acceleration */ - -#define LSM303DLHC_TIME_LIMIT_A 0x3B /* Time Limit Register acceleration */ -#define LSM303DLHC_TIME_LATENCY_A 0x3C /* Time Latency Register acceleration */ -#define LSM303DLHC_TIME_WINDOW_A 0x3D /* Time window register acceleration */ - -/* Magnetic field Registers */ -#define LSM303DLHC_CRA_REG_M 0x00 /* Control register A magnetic field */ -#define LSM303DLHC_CRB_REG_M 0x01 /* Control register B magnetic field */ -#define LSM303DLHC_MR_REG_M 0x02 /* Control register MR magnetic field */ -#define LSM303DLHC_OUT_X_H_M 0x03 /* Output Register X magnetic field */ -#define LSM303DLHC_OUT_X_L_M 0x04 /* Output Register X magnetic field */ -#define LSM303DLHC_OUT_Z_H_M 0x05 /* Output Register Z magnetic field */ -#define LSM303DLHC_OUT_Z_L_M 0x06 /* Output Register Z magnetic field */ -#define LSM303DLHC_OUT_Y_H_M 0x07 /* Output Register Y magnetic field */ -#define LSM303DLHC_OUT_Y_L_M 0x08 /* Output Register Y magnetic field */ - -#define LSM303DLHC_SR_REG_M 0x09 /* Status Register magnetic field */ -#define LSM303DLHC_IRA_REG_M 0x0A /* IRA Register magnetic field */ -#define LSM303DLHC_IRB_REG_M 0x0B /* IRB Register magnetic field */ -#define LSM303DLHC_IRC_REG_M 0x0C /* IRC Register magnetic field */ - -#define LSM303DLHC_TEMP_OUT_H_M 0x31 /* Temperature Register magnetic field */ -#define LSM303DLHC_TEMP_OUT_L_M 0x32 /* Temperature Register magnetic field */ -/******************************************************************************/ -/**************************** END REGISTER MAPPING ***************************/ -/******************************************************************************/ - -#define ACC_I2C_ADDRESS 0x32 -#define MAG_I2C_ADDRESS 0x3C - -/** @defgroup Acc_Power_Mode_selection - * @{ - */ -#define LSM303DLHC_NORMAL_MODE ((uint8_t)0x00) -#define LSM303DLHC_LOWPOWER_MODE ((uint8_t)0x08) -/** - * @} - */ - -/** @defgroup Acc_OutPut_DataRate_Selection - * @{ - */ -#define LSM303DLHC_ODR_1_HZ ((uint8_t)0x10) /*!< Output Data Rate = 1 Hz */ -#define LSM303DLHC_ODR_10_HZ ((uint8_t)0x20) /*!< Output Data Rate = 10 Hz */ -#define LSM303DLHC_ODR_25_HZ ((uint8_t)0x30) /*!< Output Data Rate = 25 Hz */ -#define LSM303DLHC_ODR_50_HZ ((uint8_t)0x40) /*!< Output Data Rate = 50 Hz */ -#define LSM303DLHC_ODR_100_HZ ((uint8_t)0x50) /*!< Output Data Rate = 100 Hz */ -#define LSM303DLHC_ODR_200_HZ ((uint8_t)0x60) /*!< Output Data Rate = 200 Hz */ -#define LSM303DLHC_ODR_400_HZ ((uint8_t)0x70) /*!< Output Data Rate = 400 Hz */ -#define LSM303DLHC_ODR_1620_HZ_LP ((uint8_t)0x80) /*!< Output Data Rate = 1620 Hz only in Low Power Mode */ -#define LSM303DLHC_ODR_1344_HZ ((uint8_t)0x90) /*!< Output Data Rate = 1344 Hz in Normal mode and 5376 Hz in Low Power Mode */ - -/** - * @} - */ - -/** @defgroup Acc_Axes_Selection - * @{ - */ -#define LSM303DLHC_X_ENABLE ((uint8_t)0x01) -#define LSM303DLHC_Y_ENABLE ((uint8_t)0x02) -#define LSM303DLHC_Z_ENABLE ((uint8_t)0x04) -#define LSM303DLHC_AXES_ENABLE ((uint8_t)0x07) -#define LSM303DLHC_AXES_DISABLE ((uint8_t)0x00) -/** - * @} - */ - -/** @defgroup Acc_High_Resolution - * @{ - */ -#define LSM303DLHC_HR_ENABLE ((uint8_t)0x08) -#define LSM303DLHC_HR_DISABLE ((uint8_t)0x00) -/** - * @} - */ - -/** @defgroup Acc_Full_Scale_Selection - * @{ - */ -#define LSM303DLHC_FULLSCALE_2G ((uint8_t)0x00) /*!< +/-2 g */ -#define LSM303DLHC_FULLSCALE_4G ((uint8_t)0x10) /*!< +/-4 g */ -#define LSM303DLHC_FULLSCALE_8G ((uint8_t)0x20) /*!< +/-8 g */ -#define LSM303DLHC_FULLSCALE_16G ((uint8_t)0x30) /*!< +/-16 g */ -/** - * @} - */ - -/** @defgroup Acc_Block_Data_Update - * @{ - */ -#define LSM303DLHC_BlockUpdate_Continous ((uint8_t)0x00) /*!< Continuos Update */ -#define LSM303DLHC_BlockUpdate_Single ((uint8_t)0x80) /*!< Single Update: output registers not updated until MSB and LSB reading */ -/** - * @} - */ - -/** @defgroup Acc_Endian_Data_selection - * @{ - */ -#define LSM303DLHC_BLE_LSB ((uint8_t)0x00) /*!< Little Endian: data LSB @ lower address */ -#define LSM303DLHC_BLE_MSB ((uint8_t)0x40) /*!< Big Endian: data MSB @ lower address */ -/** - * @} - */ - -/** @defgroup Acc_Boot_Mode_selection - * @{ - */ -#define LSM303DLHC_BOOT_NORMALMODE ((uint8_t)0x00) -#define LSM303DLHC_BOOT_REBOOTMEMORY ((uint8_t)0x80) -/** - * @} - */ - -/** @defgroup Acc_High_Pass_Filter_Mode - * @{ - */ -#define LSM303DLHC_HPM_NORMAL_MODE_RES ((uint8_t)0x00) -#define LSM303DLHC_HPM_REF_SIGNAL ((uint8_t)0x40) -#define LSM303DLHC_HPM_NORMAL_MODE ((uint8_t)0x80) -#define LSM303DLHC_HPM_AUTORESET_INT ((uint8_t)0xC0) -/** - * @} - */ - -/** @defgroup Acc_High_Pass_CUT OFF_Frequency - * @{ - */ -#define LSM303DLHC_HPFCF_8 ((uint8_t)0x00) -#define LSM303DLHC_HPFCF_16 ((uint8_t)0x10) -#define LSM303DLHC_HPFCF_32 ((uint8_t)0x20) -#define LSM303DLHC_HPFCF_64 ((uint8_t)0x30) -/** - * @} - */ - -/** @defgroup Acc_High_Pass_Filter_status - * @{ - */ -#define LSM303DLHC_HIGHPASSFILTER_DISABLE ((uint8_t)0x00) -#define LSM303DLHC_HIGHPASSFILTER_ENABLE ((uint8_t)0x08) -/** - * @} - */ - -/** @defgroup Acc_High_Pass_Filter_Click_status - * @{ - */ -#define LSM303DLHC_HPF_CLICK_DISABLE ((uint8_t)0x00) -#define LSM303DLHC_HPF_CLICK_ENABLE ((uint8_t)0x04) -/** - * @} - */ - -/** @defgroup Acc_High_Pass_Filter_AOI1_status - * @{ - */ -#define LSM303DLHC_HPF_AOI1_DISABLE ((uint8_t)0x00) -#define LSM303DLHC_HPF_AOI1_ENABLE ((uint8_t)0x01) -/** - * @} - */ - -/** @defgroup Acc_High_Pass_Filter_AOI2_status - * @{ - */ -#define LSM303DLHC_HPF_AOI2_DISABLE ((uint8_t)0x00) -#define LSM303DLHC_HPF_AOI2_ENABLE ((uint8_t)0x02) -/** - * @} - */ - -/** @defgroup Acc_LSM303DLHC_Interrupt1_Configuration_definition - * @{ - */ -#define LSM303DLHC_IT1_CLICK ((uint8_t)0x80) -#define LSM303DLHC_IT1_AOI1 ((uint8_t)0x40) -#define LSM303DLHC_IT1_AOI2 ((uint8_t)0x20) -#define LSM303DLHC_IT1_DRY1 ((uint8_t)0x10) -#define LSM303DLHC_IT1_DRY2 ((uint8_t)0x08) -#define LSM303DLHC_IT1_WTM ((uint8_t)0x04) -#define LSM303DLHC_IT1_OVERRUN ((uint8_t)0x02) -/** - * @} - */ - -/** @defgroup Acc_LSM303DLHC_Interrupt2_Configuration_definition - * @{ - */ -#define LSM303DLHC_IT2_CLICK ((uint8_t)0x80) -#define LSM303DLHC_IT2_INT1 ((uint8_t)0x40) -#define LSM303DLHC_IT2_INT2 ((uint8_t)0x20) -#define LSM303DLHC_IT2_BOOT ((uint8_t)0x10) -#define LSM303DLHC_IT2_ACT ((uint8_t)0x08) -#define LSM303DLHC_IT2_HLACTIVE ((uint8_t)0x02) -/** - * @} - */ - -/** @defgroup Acc_INT_Combination_Status - * @{ - */ -#define LSM303DLHC_OR_COMBINATION ((uint8_t)0x00) /*!< OR combination of enabled IRQs */ -#define LSM303DLHC_AND_COMBINATION ((uint8_t)0x80) /*!< AND combination of enabled IRQs */ -#define LSM303DLHC_MOV_RECOGNITION ((uint8_t)0x40) /*!< 6D movement recognition */ -#define LSM303DLHC_POS_RECOGNITION ((uint8_t)0xC0) /*!< 6D position recognition */ -/** - * @} - */ - -/** @defgroup Acc_INT_Axes - * @{ - */ -#define LSM303DLHC_Z_HIGH ((uint8_t)0x20) /*!< Z High enabled IRQs */ -#define LSM303DLHC_Z_LOW ((uint8_t)0x10) /*!< Z low enabled IRQs */ -#define LSM303DLHC_Y_HIGH ((uint8_t)0x08) /*!< Y High enabled IRQs */ -#define LSM303DLHC_Y_LOW ((uint8_t)0x04) /*!< Y low enabled IRQs */ -#define LSM303DLHC_X_HIGH ((uint8_t)0x02) /*!< X High enabled IRQs */ -#define LSM303DLHC_X_LOW ((uint8_t)0x01) /*!< X low enabled IRQs */ -/** - * @} - */ - -/** @defgroup Acc_INT_Click - * @{ - */ -#define LSM303DLHC_Z_DOUBLE_CLICK ((uint8_t)0x20) /*!< Z double click IRQs */ -#define LSM303DLHC_Z_SINGLE_CLICK ((uint8_t)0x10) /*!< Z single click IRQs */ -#define LSM303DLHC_Y_DOUBLE_CLICK ((uint8_t)0x08) /*!< Y double click IRQs */ -#define LSM303DLHC_Y_SINGLE_CLICK ((uint8_t)0x04) /*!< Y single click IRQs */ -#define LSM303DLHC_X_DOUBLE_CLICK ((uint8_t)0x02) /*!< X double click IRQs */ -#define LSM303DLHC_X_SINGLE_CLICK ((uint8_t)0x01) /*!< X single click IRQs */ -/** - * @} - */ - -/** @defgroup Acc_INT1_Interrupt_status - * @{ - */ -#define LSM303DLHC_INT1INTERRUPT_DISABLE ((uint8_t)0x00) -#define LSM303DLHC_INT1INTERRUPT_ENABLE ((uint8_t)0x80) -/** - * @} - */ - -/** @defgroup Acc_INT1_Interrupt_ActiveEdge - * @{ - */ -#define LSM303DLHC_INT1INTERRUPT_LOW_EDGE ((uint8_t)0x20) -#define LSM303DLHC_INT1INTERRUPT_HIGH_EDGE ((uint8_t)0x00) -/** - * @} - */ - -/** @defgroup Mag_Data_Rate - * @{ - */ -#define LSM303DLHC_ODR_0_75_HZ ((uint8_t) 0x00) /*!< Output Data Rate = 0.75 Hz */ -#define LSM303DLHC_ODR_1_5_HZ ((uint8_t) 0x04) /*!< Output Data Rate = 1.5 Hz */ -#define LSM303DLHC_ODR_3_0_HZ ((uint8_t) 0x08) /*!< Output Data Rate = 3 Hz */ -#define LSM303DLHC_ODR_7_5_HZ ((uint8_t) 0x0C) /*!< Output Data Rate = 7.5 Hz */ -#define LSM303DLHC_ODR_15_HZ ((uint8_t) 0x10) /*!< Output Data Rate = 15 Hz */ -#define LSM303DLHC_ODR_30_HZ ((uint8_t) 0x14) /*!< Output Data Rate = 30 Hz */ -#define LSM303DLHC_ODR_75_HZ ((uint8_t) 0x18) /*!< Output Data Rate = 75 Hz */ -#define LSM303DLHC_ODR_220_HZ ((uint8_t) 0x1C) /*!< Output Data Rate = 220 Hz */ -/** - * @} - */ - -/** @defgroup Mag_Full_Scale - * @{ - */ -#define LSM303DLHC_FS_1_3_GA ((uint8_t) 0x20) /*!< Full scale = +/-1.3 Gauss */ -#define LSM303DLHC_FS_1_9_GA ((uint8_t) 0x40) /*!< Full scale = +/-1.9 Gauss */ -#define LSM303DLHC_FS_2_5_GA ((uint8_t) 0x60) /*!< Full scale = +/-2.5 Gauss */ -#define LSM303DLHC_FS_4_0_GA ((uint8_t) 0x80) /*!< Full scale = +/-4.0 Gauss */ -#define LSM303DLHC_FS_4_7_GA ((uint8_t) 0xA0) /*!< Full scale = +/-4.7 Gauss */ -#define LSM303DLHC_FS_5_6_GA ((uint8_t) 0xC0) /*!< Full scale = +/-5.6 Gauss */ -#define LSM303DLHC_FS_8_1_GA ((uint8_t) 0xE0) /*!< Full scale = +/-8.1 Gauss */ -/** - * @} - */ - -/** - * @defgroup Magnetometer_Sensitivity - * @{ - */ -#define LSM303DLHC_M_SENSITIVITY_XY_1_3Ga 1100 /*!< magnetometer X Y axes sensitivity for 1.3 Ga full scale [LSB/Ga] */ -#define LSM303DLHC_M_SENSITIVITY_XY_1_9Ga 855 /*!< magnetometer X Y axes sensitivity for 1.9 Ga full scale [LSB/Ga] */ -#define LSM303DLHC_M_SENSITIVITY_XY_2_5Ga 670 /*!< magnetometer X Y axes sensitivity for 2.5 Ga full scale [LSB/Ga] */ -#define LSM303DLHC_M_SENSITIVITY_XY_4Ga 450 /*!< magnetometer X Y axes sensitivity for 4 Ga full scale [LSB/Ga] */ -#define LSM303DLHC_M_SENSITIVITY_XY_4_7Ga 400 /*!< magnetometer X Y axes sensitivity for 4.7 Ga full scale [LSB/Ga] */ -#define LSM303DLHC_M_SENSITIVITY_XY_5_6Ga 330 /*!< magnetometer X Y axes sensitivity for 5.6 Ga full scale [LSB/Ga] */ -#define LSM303DLHC_M_SENSITIVITY_XY_8_1Ga 230 /*!< magnetometer X Y axes sensitivity for 8.1 Ga full scale [LSB/Ga] */ -#define LSM303DLHC_M_SENSITIVITY_Z_1_3Ga 980 /*!< magnetometer Z axis sensitivity for 1.3 Ga full scale [LSB/Ga] */ -#define LSM303DLHC_M_SENSITIVITY_Z_1_9Ga 760 /*!< magnetometer Z axis sensitivity for 1.9 Ga full scale [LSB/Ga] */ -#define LSM303DLHC_M_SENSITIVITY_Z_2_5Ga 600 /*!< magnetometer Z axis sensitivity for 2.5 Ga full scale [LSB/Ga] */ -#define LSM303DLHC_M_SENSITIVITY_Z_4Ga 400 /*!< magnetometer Z axis sensitivity for 4 Ga full scale [LSB/Ga] */ -#define LSM303DLHC_M_SENSITIVITY_Z_4_7Ga 355 /*!< magnetometer Z axis sensitivity for 4.7 Ga full scale [LSB/Ga] */ -#define LSM303DLHC_M_SENSITIVITY_Z_5_6Ga 295 /*!< magnetometer Z axis sensitivity for 5.6 Ga full scale [LSB/Ga] */ -#define LSM303DLHC_M_SENSITIVITY_Z_8_1Ga 205 /*!< magnetometer Z axis sensitivity for 8.1 Ga full scale [LSB/Ga] */ -/** - * @} - */ - -/** @defgroup Mag_Working_Mode - * @{ - */ -#define LSM303DLHC_CONTINUOS_CONVERSION ((uint8_t) 0x00) /*!< Continuous-Conversion Mode */ -#define LSM303DLHC_SINGLE_CONVERSION ((uint8_t) 0x01) /*!< Single-Conversion Mode */ -#define LSM303DLHC_SLEEP ((uint8_t) 0x02) /*!< Sleep Mode */ -/** - * @} - */ - -/** @defgroup Mag_Temperature_Sensor - * @{ - */ -#define LSM303DLHC_TEMPSENSOR_ENABLE ((uint8_t) 0x80) /*!< Temp sensor Enable */ -#define LSM303DLHC_TEMPSENSOR_DISABLE ((uint8_t) 0x00) /*!< Temp sensor Disable */ - -bool lsm303dlhcAccDetect(accDev_t *acc); diff --git a/src/main/drivers/accgyro/legacy/accgyro_mma845x.c b/src/main/drivers/accgyro/legacy/accgyro_mma845x.c deleted file mode 100644 index 1b51e7adab..0000000000 --- a/src/main/drivers/accgyro/legacy/accgyro_mma845x.c +++ /dev/null @@ -1,144 +0,0 @@ -/* - * This file is part of Cleanflight and Betaflight. - * - * Cleanflight and Betaflight are free software. You can redistribute - * this software and/or modify this software under the terms of the - * GNU General Public License as published by the Free Software - * Foundation, either version 3 of the License, or (at your option) - * any later version. - * - * Cleanflight and Betaflight are distributed in the hope that they - * will be useful, but WITHOUT ANY WARRANTY; without even the implied - * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * See the GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this software. - * - * If not, see . - */ - -#include -#include - -#include "platform.h" - -#ifdef USE_ACC_MMA8452 - -#include "drivers/io.h" -#include "drivers/bus_i2c.h" - -#include "drivers/sensor.h" -#include "drivers/accgyro/accgyro.h" -#include "accgyro_mma845x.h" - -#ifndef MMA8452_I2C_INSTANCE -#define MMA8452_I2C_INSTANCE I2CDEV_1 -#endif - -// MMA8452QT, Standard address 0x1C -// ACC_INT2 routed to PA5 - -#define MMA8452_ADDRESS 0x1C - -#define MMA8452_DEVICE_SIGNATURE 0x2A -#define MMA8451_DEVICE_SIGNATURE 0x1A - -#define MMA8452_STATUS 0x00 -#define MMA8452_OUT_X_MSB 0x01 -#define MMA8452_WHO_AM_I 0x0D -#define MMA8452_XYZ_DATA_CFG 0x0E -#define MMA8452_HP_FILTER_CUTOFF 0x0F -#define MMA8452_CTRL_REG1 0x2A -#define MMA8452_CTRL_REG2 0x2B -#define MMA8452_CTRL_REG3 0x2C -#define MMA8452_CTRL_REG4 0x2D -#define MMA8452_CTRL_REG5 0x2E - -#define MMA8452_FS_RANGE_8G 0x02 -#define MMA8452_FS_RANGE_4G 0x01 -#define MMA8452_FS_RANGE_2G 0x00 - -#define MMA8452_HPF_CUTOFF_LV1 0x00 -#define MMA8452_HPF_CUTOFF_LV2 0x01 -#define MMA8452_HPF_CUTOFF_LV3 0x02 -#define MMA8452_HPF_CUTOFF_LV4 0x03 - -#define MMA8452_CTRL_REG2_B7_ST 0x80 -#define MMA8452_CTRL_REG2_B6_RST 0x40 -#define MMA8452_CTRL_REG2_B4_SMODS1 0x10 -#define MMA8452_CTRL_REG2_B3_SMODS0 0x08 -#define MMA8452_CTRL_REG2_B2_SLPE 0x04 -#define MMA8452_CTRL_REG2_B1_MODS1 0x02 -#define MMA8452_CTRL_REG2_B0_MODS0 0x01 - -#define MMA8452_CTRL_REG2_MODS_LP 0x03 -#define MMA8452_CTRL_REG2_MODS_HR 0x02 -#define MMA8452_CTRL_REG2_MODS_LNLP 0x01 -#define MMA8452_CTRL_REG2_MODS_NOR 0x00 - -#define MMA8452_CTRL_REG3_IPOL 0x02 -#define MMA8452_CTRL_REG4_INT_EN_DRDY 0x01 - -#define MMA8452_CTRL_REG1_LNOISE 0x04 -#define MMA8452_CTRL_REG1_ACTIVE 0x01 - -static uint8_t device_id; - -static inline void mma8451ConfigureInterrupt(void) -{ -#ifdef MMA8451_INT_PIN - IOInit(IOGetByTag(IO_TAG(MMA8451_INT_PIN)), OWNER_GYRO_EXTI, 0); - // TODO - maybe pullup / pulldown ? - IOConfigGPIO(IOGetByTag(IO_TAG(MMA8451_INT_PIN)), IOCFG_IN_FLOATING); -#endif - - i2cWrite(MPU_I2C_INSTANCE, MMA8452_ADDRESS, MMA8452_CTRL_REG3, MMA8452_CTRL_REG3_IPOL); // Interrupt polarity (active HIGH) - i2cWrite(MPU_I2C_INSTANCE, MMA8452_ADDRESS, MMA8452_CTRL_REG4, MMA8452_CTRL_REG4_INT_EN_DRDY); // Enable DRDY interrupt (unused by this driver) - i2cWrite(MPU_I2C_INSTANCE, MMA8452_ADDRESS, MMA8452_CTRL_REG5, 0); // DRDY routed to INT2 -} - -static void mma8452Init(accDev_t *acc) -{ - - i2cWrite(MPU_I2C_INSTANCE, MMA8452_ADDRESS, MMA8452_CTRL_REG1, 0); // Put device in standby to configure stuff - i2cWrite(MPU_I2C_INSTANCE, MMA8452_ADDRESS, MMA8452_XYZ_DATA_CFG, MMA8452_FS_RANGE_8G); - i2cWrite(MPU_I2C_INSTANCE, MMA8452_ADDRESS, MMA8452_HP_FILTER_CUTOFF, MMA8452_HPF_CUTOFF_LV4); - i2cWrite(MPU_I2C_INSTANCE, MMA8452_ADDRESS, MMA8452_CTRL_REG2, MMA8452_CTRL_REG2_MODS_HR | MMA8452_CTRL_REG2_MODS_HR << 3); // High resolution measurement in both sleep and active modes - - mma8451ConfigureInterrupt(); - - i2cWrite(MPU_I2C_INSTANCE, MMA8452_ADDRESS, MMA8452_CTRL_REG1, MMA8452_CTRL_REG1_LNOISE | MMA8452_CTRL_REG1_ACTIVE); // Turn on measurements, low noise at max scale mode, Data Rate 800Hz. LNoise mode makes range +-4G. - - acc->acc_1G = 256; -} - -static bool mma8452Read(accDev_t *acc) -{ - uint8_t buf[6]; - - if (!i2cRead(MPU_I2C_INSTANCE, MMA8452_ADDRESS, MMA8452_OUT_X_MSB, 6, buf)) { - return false; - } - - acc->ADCRaw[0] = ((int16_t)((buf[0] << 8) | buf[1]) >> 2) / 4; - acc->ADCRaw[1] = ((int16_t)((buf[2] << 8) | buf[3]) >> 2) / 4; - acc->ADCRaw[2] = ((int16_t)((buf[4] << 8) | buf[5]) >> 2) / 4; - - return true; -} - -bool mma8452Detect(accDev_t *acc) -{ - uint8_t sig = 0; - bool ack = i2cRead(MPU_I2C_INSTANCE, MMA8452_ADDRESS, MMA8452_WHO_AM_I, 1, &sig); - - if (!ack || (sig != MMA8452_DEVICE_SIGNATURE && sig != MMA8451_DEVICE_SIGNATURE)) - return false; - - acc->initFn = mma8452Init; - acc->readFn = mma8452Read; - device_id = sig; - return true; -} -#endif diff --git a/src/main/drivers/accgyro/legacy/accgyro_mma845x.h b/src/main/drivers/accgyro/legacy/accgyro_mma845x.h deleted file mode 100644 index 445bc08ee2..0000000000 --- a/src/main/drivers/accgyro/legacy/accgyro_mma845x.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * This file is part of Cleanflight and Betaflight. - * - * Cleanflight and Betaflight are free software. You can redistribute - * this software and/or modify this software under the terms of the - * GNU General Public License as published by the Free Software - * Foundation, either version 3 of the License, or (at your option) - * any later version. - * - * Cleanflight and Betaflight are distributed in the hope that they - * will be useful, but WITHOUT ANY WARRANTY; without even the implied - * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * See the GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this software. - * - * If not, see . - */ - -#pragma once - -bool mma8452Detect(accDev_t *acc); diff --git a/src/main/sensors/acceleration.c b/src/main/sensors/acceleration.c index fd81054a28..208dc798ee 100644 --- a/src/main/sensors/acceleration.c +++ b/src/main/sensors/acceleration.c @@ -57,7 +57,7 @@ static inline void calibrateAccelerometer(void) { if (!accIsCalibrationComplete()) { // acc.accADC is held at 0 until calibration is completed - performAcclerationCalibration(&accelerometerConfigMutable()->accelerometerTrims); + performAccelerometerCalibration(&accelerometerConfigMutable()->accelerometerTrims); } if (featureIsEnabled(FEATURE_INFLIGHT_ACC_CAL)) { diff --git a/src/main/sensors/acceleration.h b/src/main/sensors/acceleration.h index df9168ebae..66a139d664 100644 --- a/src/main/sensors/acceleration.h +++ b/src/main/sensors/acceleration.h @@ -31,14 +31,11 @@ #include "sensors/sensors.h" // Type of accelerometer used/detected +// Acc hardware types were updated in PR #14087 (removed ACC_ADXL345, ACC_MMA8452, ACC_BMA280, ACC_LSM303DLHC) typedef enum { ACC_DEFAULT, ACC_NONE, - ACC_ADXL345, ACC_MPU6050, - ACC_MMA8452, - ACC_BMA280, - ACC_LSM303DLHC, ACC_MPU6000, ACC_MPU6500, ACC_MPU9250, diff --git a/src/main/sensors/acceleration_init.c b/src/main/sensors/acceleration_init.c index 62ce093395..127ea4a80c 100644 --- a/src/main/sensors/acceleration_init.c +++ b/src/main/sensors/acceleration_init.c @@ -35,37 +35,25 @@ #include "config/feature.h" #include "drivers/accgyro/accgyro.h" -#include "drivers/accgyro/accgyro_virtual.h" #include "drivers/accgyro/accgyro_mpu.h" -#include "drivers/accgyro/accgyro_mpu3050.h" +#include "drivers/accgyro/accgyro_virtual.h" + #include "drivers/accgyro/accgyro_mpu6050.h" #include "drivers/accgyro/accgyro_mpu6500.h" + #include "drivers/accgyro/accgyro_spi_bmi160.h" #include "drivers/accgyro/accgyro_spi_bmi270.h" + #include "drivers/accgyro/accgyro_spi_icm20649.h" #include "drivers/accgyro/accgyro_spi_icm20689.h" #include "drivers/accgyro/accgyro_spi_icm426xx.h" + #include "drivers/accgyro/accgyro_spi_lsm6dso.h" +#include "drivers/accgyro/accgyro_spi_lsm6dsv16x.h" + #include "drivers/accgyro/accgyro_spi_mpu6000.h" #include "drivers/accgyro/accgyro_spi_mpu6500.h" #include "drivers/accgyro/accgyro_spi_mpu9250.h" -#include "drivers/accgyro/accgyro_spi_lsm6dsv16x.h" - -#ifdef USE_ACC_ADXL345 -#include "drivers/accgyro/legacy/accgyro_adxl345.h" -#endif - -#ifdef USE_ACC_BMA280 -#include "drivers/accgyro/legacy/accgyro_bma280.h" -#endif - -#ifdef USE_ACC_LSM303DLHC -#include "drivers/accgyro/legacy/accgyro_lsm303dlhc.h" -#endif - -#ifdef USE_ACC_MMA8452 -#include "drivers/accgyro/legacy/accgyro_mma845x.h" -#endif #include "config/config.h" @@ -85,18 +73,6 @@ #include "acceleration_init.h" -#if !defined(USE_ACC_ADXL345) && !defined(USE_ACC_BMA280) && !defined(USE_ACC_LSM303DLHC) \ - && !defined(USE_ACC_MMA8452) && !defined(USE_ACC_LSM303DLHC) \ - && !defined(USE_ACC_MPU6000) && !defined(USE_ACC_MPU6050) && !defined(USE_ACC_MPU6500) \ - && !defined(USE_ACC_SPI_MPU6000) && !defined(USE_ACC_SPI_MPU6500) && !defined(USE_ACC_SPI_MPU9250) \ - && !defined(USE_ACC_SPI_ICM20602) && !defined(USE_ACC_SPI_ICM20649) && !defined(USE_ACC_SPI_ICM20689) \ - && !defined(USE_ACCGYRO_BMI160) && !defined(USE_ACCGYRO_BMI270) \ - && !defined(USE_ACC_SPI_ICM42605) && !defined(USE_ACC_SPI_ICM42688P) \ - && !defined(USE_ACCGYRO_LSM6DSO) && !defined(USE_ACCGYRO_LSM6DSV16X) \ - && !defined(USE_VIRTUAL_ACC) -#error At least one USE_ACC device definition required -#endif - #define CALIBRATING_ACC_CYCLES 400 FAST_DATA_ZERO_INIT accelerationRuntime_t accelerationRuntime; @@ -158,36 +134,12 @@ bool accDetect(accDev_t *dev, accelerationSensor_e accHardwareToUse) { accelerationSensor_e accHardware = ACC_NONE; -#ifdef USE_ACC_ADXL345 - drv_adxl345_config_t acc_params; -#endif - retry: switch (accHardwareToUse) { case ACC_DEFAULT: FALLTHROUGH; -#ifdef USE_ACC_ADXL345 - case ACC_ADXL345: // ADXL345 - acc_params.useFifo = false; - acc_params.dataRate = 800; // unused currently - if (adxl345Detect(&acc_params, dev)) { - accHardware = ACC_ADXL345; - break; - } - FALLTHROUGH; -#endif - -#ifdef USE_ACC_LSM303DLHC - case ACC_LSM303DLHC: - if (lsm303dlhcAccDetect(dev)) { - accHardware = ACC_LSM303DLHC; - break; - } - FALLTHROUGH; -#endif - #ifdef USE_ACC_MPU6050 case ACC_MPU6050: // MPU6050 if (mpu6050AccDetect(dev)) { @@ -197,24 +149,6 @@ retry: FALLTHROUGH; #endif -#ifdef USE_ACC_MMA8452 - case ACC_MMA8452: // MMA8452 - if (mma8452Detect(dev)) { - accHardware = ACC_MMA8452; - break; - } - FALLTHROUGH; -#endif - -#ifdef USE_ACC_BMA280 - case ACC_BMA280: // BMA280 - if (bma280Detect(dev)) { - accHardware = ACC_BMA280; - break; - } - FALLTHROUGH; -#endif - #ifdef USE_ACC_SPI_MPU6000 case ACC_MPU6000: if (mpu6000SpiAccDetect(dev)) { @@ -438,7 +372,7 @@ static bool isOnFirstAccelerationCalibrationCycle(void) return accelerationRuntime.calibratingA == CALIBRATING_ACC_CYCLES; } -void performAcclerationCalibration(rollAndPitchTrims_t *rollAndPitchTrims) +void performAccelerometerCalibration(rollAndPitchTrims_t *rollAndPitchTrims) { static int32_t a[3]; diff --git a/src/main/sensors/acceleration_init.h b/src/main/sensors/acceleration_init.h index d40b10f0b4..d87c03a7f7 100644 --- a/src/main/sensors/acceleration_init.h +++ b/src/main/sensors/acceleration_init.h @@ -37,5 +37,5 @@ typedef struct accelerationRuntime_s { extern accelerationRuntime_t accelerationRuntime; -void performAcclerationCalibration(rollAndPitchTrims_t *rollAndPitchTrims); +void performAccelerometerCalibration(rollAndPitchTrims_t *rollAndPitchTrims); void performInflightAccelerationCalibration(rollAndPitchTrims_t *rollAndPitchTrims); diff --git a/src/main/sensors/gyro_init.c b/src/main/sensors/gyro_init.c index 6ec8dc791d..c09d466e5a 100644 --- a/src/main/sensors/gyro_init.c +++ b/src/main/sensors/gyro_init.c @@ -37,27 +37,24 @@ #include "drivers/accgyro/accgyro.h" #include "drivers/accgyro/accgyro_virtual.h" #include "drivers/accgyro/accgyro_mpu.h" -#include "drivers/accgyro/accgyro_mpu3050.h" + #include "drivers/accgyro/accgyro_mpu6050.h" #include "drivers/accgyro/accgyro_mpu6500.h" + #include "drivers/accgyro/accgyro_spi_bmi160.h" #include "drivers/accgyro/accgyro_spi_bmi270.h" + #include "drivers/accgyro/accgyro_spi_icm20649.h" #include "drivers/accgyro/accgyro_spi_icm20689.h" #include "drivers/accgyro/accgyro_spi_icm426xx.h" + +#include "drivers/accgyro/accgyro_spi_l3gd20.h" #include "drivers/accgyro/accgyro_spi_lsm6dso.h" +#include "drivers/accgyro/accgyro_spi_lsm6dsv16x.h" + #include "drivers/accgyro/accgyro_spi_mpu6000.h" #include "drivers/accgyro/accgyro_spi_mpu6500.h" #include "drivers/accgyro/accgyro_spi_mpu9250.h" -#include "drivers/accgyro/accgyro_spi_lsm6dsv16x.h" - -#ifdef USE_GYRO_L3GD20 -#include "drivers/accgyro/accgyro_spi_l3gd20.h" -#endif - -#ifdef USE_GYRO_L3G4200D -#include "drivers/accgyro/legacy/accgyro_l3g4200d.h" -#endif #include "drivers/accgyro/gyro_sync.h" @@ -72,17 +69,6 @@ #include "sensors/gyro.h" #include "sensors/sensors.h" -#if !defined(USE_GYRO_L3G4200D) && !defined(USE_GYRO_L3GD20) \ - && !defined(USE_GYRO_MPU3050) && !defined(USE_GYRO_MPU6050) && !defined(USE_GYRO_MPU6500) \ - && !defined(USE_GYRO_SPI_MPU6000) && !defined(USE_GYRO_SPI_MPU6500) && !defined(USE_GYRO_SPI_MPU9250) \ - && !defined(USE_GYRO_SPI_ICM20602) && !defined(USE_GYRO_SPI_ICM20649) && !defined(USE_GYRO_SPI_ICM20689) \ - && !defined(USE_ACCGYRO_BMI160) && !defined(USE_ACCGYRO_BMI270) \ - && !defined(USE_GYRO_SPI_ICM42605) && !defined(USE_GYRO_SPI_ICM42688P) \ - && !defined(USE_ACCGYRO_LSM6DSO) && !defined(USE_ACCGYRO_LSM6DSV16X) \ - && !defined(USE_VIRTUAL_GYRO) -#error At least one USE_GYRO device definition required -#endif - #ifdef USE_MULTI_GYRO #define ACTIVE_GYRO ((gyro.gyroToUse == GYRO_CONFIG_USE_GYRO_2) ? &gyro.gyroSensor2 : &gyro.gyroSensor1) #else @@ -319,8 +305,6 @@ void gyroInitSensor(gyroSensor_t *gyroSensor, const gyroDeviceConfig_t *config) case GYRO_DEFAULT: case GYRO_VIRTUAL: case GYRO_MPU6050: - case GYRO_L3G4200D: - case GYRO_MPU3050: case GYRO_L3GD20: case GYRO_BMI160: case GYRO_BMI270: @@ -367,24 +351,6 @@ STATIC_UNIT_TESTED gyroHardware_e gyroDetect(gyroDev_t *dev) FALLTHROUGH; #endif -#ifdef USE_GYRO_L3G4200D - case GYRO_L3G4200D: - if (l3g4200dDetect(dev)) { - gyroHardware = GYRO_L3G4200D; - break; - } - FALLTHROUGH; -#endif - -#ifdef USE_GYRO_MPU3050 - case GYRO_MPU3050: - if (mpu3050Detect(dev)) { - gyroHardware = GYRO_MPU3050; - break; - } - FALLTHROUGH; -#endif - #ifdef USE_GYRO_L3GD20 case GYRO_L3GD20: if (l3gd20GyroDetect(dev)) { diff --git a/src/main/target/common_post.h b/src/main/target/common_post.h index 508453ab7e..a69492dcf2 100644 --- a/src/main/target/common_post.h +++ b/src/main/target/common_post.h @@ -91,6 +91,45 @@ // normalize serial ports definitions #include "serial_post.h" +#if defined(USE_ACC) \ + && !defined(USE_ACC_MPU6000) \ + && !defined(USE_ACC_MPU6050) \ + && !defined(USE_ACC_MPU6500) \ + && !defined(USE_ACCGYRO_BMI160) \ + && !defined(USE_ACCGYRO_BMI270) \ + && !defined(USE_ACC_SPI_ICM20602) \ + && !defined(USE_ACC_SPI_ICM20649) \ + && !defined(USE_ACC_SPI_ICM20689) \ + && !defined(USE_ACC_SPI_ICM42605) \ + && !defined(USE_ACC_SPI_ICM42688P) \ + && !defined(USE_ACCGYRO_LSM6DSO) \ + && !defined(USE_ACCGYRO_LSM6DSV16X) \ + && !defined(USE_ACC_SPI_MPU6000) \ + && !defined(USE_ACC_SPI_MPU6500) \ + && !defined(USE_ACC_SPI_MPU9250) \ + && !defined(USE_VIRTUAL_ACC) +#error At least one USE_ACC device definition required +#endif + +#if defined(USE_GYRO) \ + && !defined(USE_GYRO_MPU6050) \ + && !defined(USE_GYRO_MPU6500) \ + && !defined(USE_ACCGYRO_BMI160) \ + && !defined(USE_ACCGYRO_BMI270) \ + && !defined(USE_GYRO_SPI_ICM20602) \ + && !defined(USE_GYRO_SPI_ICM20649) \ + && !defined(USE_GYRO_SPI_ICM20689) \ + && !defined(USE_GYRO_SPI_ICM42605) \ + && !defined(USE_GYRO_SPI_ICM42688P) \ + && !defined(USE_ACCGYRO_LSM6DSO) \ + && !defined(USE_ACCGYRO_LSM6DSV16X) \ + && !defined(USE_GYRO_SPI_MPU6000) \ + && !defined(USE_GYRO_SPI_MPU6500) \ + && !defined(USE_GYRO_SPI_MPU9250) \ + && !defined(USE_VIRTUAL_GYRO) +#error At least one USE_GYRO device definition required +#endif + #if defined(USE_MAG) && !defined(USE_VIRTUAL_MAG) #ifndef USE_MAG_DATA_READY_SIGNAL @@ -426,12 +465,6 @@ #endif // Generate USE_SPI_GYRO or USE_I2C_GYRO -#if defined(USE_GYRO_L3G4200D) || defined(USE_GYRO_MPU3050) || defined(USE_GYRO_MPU6000) || defined(USE_GYRO_MPU6050) || defined(USE_GYRO_MPU6500) -#ifndef USE_I2C_GYRO -#define USE_I2C_GYRO -#endif -#endif - #if defined(USE_GYRO_SPI_ICM20689) || defined(USE_GYRO_SPI_MPU6000) || defined(USE_GYRO_SPI_MPU6500) || defined(USE_GYRO_SPI_MPU9250) \ || defined(USE_GYRO_L3GD20) || defined(USE_GYRO_SPI_ICM42605) || defined(USE_GYRO_SPI_ICM42688P) || defined(USE_ACCGYRO_BMI160) \ || defined(USE_ACCGYRO_BMI270) || defined(USE_ACCGYRO_LSM6DSV16X) || defined(USE_ACCGYRO_LSM6DSO) From ee9e349febddd61bc4d7b91eedd4d392edc6dbe1 Mon Sep 17 00:00:00 2001 From: Jay Blackman Date: Wed, 1 Jan 2025 06:23:51 +1100 Subject: [PATCH 018/244] Update actions to ubuntu-latest (#14114) Merging to ensure completed before change over to runners. --- .github/workflows/auto-close.yml | 2 +- .github/workflows/build-release.yml | 2 +- .github/workflows/ci.yml | 8 ++++---- .github/workflows/nightly.yml | 2 +- .github/workflows/pr-cloud-comment.yml | 2 +- 5 files changed, 8 insertions(+), 8 deletions(-) diff --git a/.github/workflows/auto-close.yml b/.github/workflows/auto-close.yml index d0f3223b50..da3784700a 100644 --- a/.github/workflows/auto-close.yml +++ b/.github/workflows/auto-close.yml @@ -11,7 +11,7 @@ permissions: jobs: close-pr: - runs-on: ubuntu-22.04 + runs-on: ubuntu-latest steps: - name: Code Checkout uses: actions/checkout@v4 diff --git a/.github/workflows/build-release.yml b/.github/workflows/build-release.yml index c535943b1a..4d74930cb7 100644 --- a/.github/workflows/build-release.yml +++ b/.github/workflows/build-release.yml @@ -14,7 +14,7 @@ jobs: release: name: Release needs: ci - runs-on: ubuntu-22.04 + runs-on: ubuntu-latest steps: - name: Code Checkout uses: actions/checkout@v4 diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index bfa8d3471d..45e8c5bbcb 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -15,7 +15,7 @@ on: jobs: setup: name: Setup - runs-on: ubuntu-22.04 + runs-on: ubuntu-latest outputs: targets: ${{ steps.get-targets.outputs.targets }} steps: @@ -43,7 +43,7 @@ jobs: build: name: Build needs: setup - runs-on: ubuntu-22.04 + runs-on: ubuntu-latest strategy: matrix: target: ${{ fromJson(needs.setup.outputs.targets) }} @@ -79,7 +79,7 @@ jobs: test: name: Test - runs-on: ubuntu-22.04 + runs-on: ubuntu-latest steps: - uses: actions/checkout@v4 @@ -96,7 +96,7 @@ jobs: name: Complete needs: [build, test] if: ${{ always() }} - runs-on: ubuntu-22.04 + runs-on: ubuntu-latest steps: - name: Check build matrix result if: ${{ needs.build.result != 'success' }} diff --git a/.github/workflows/nightly.yml b/.github/workflows/nightly.yml index e5e9f5d335..943edaec4e 100644 --- a/.github/workflows/nightly.yml +++ b/.github/workflows/nightly.yml @@ -29,7 +29,7 @@ jobs: release: name: Nightly release needs: ci - runs-on: ubuntu-22.04 + runs-on: ubuntu-latest steps: - name: Code Checkout uses: actions/checkout@v4 diff --git a/.github/workflows/pr-cloud-comment.yml b/.github/workflows/pr-cloud-comment.yml index efd42da5fa..18401a4aa5 100644 --- a/.github/workflows/pr-cloud-comment.yml +++ b/.github/workflows/pr-cloud-comment.yml @@ -11,7 +11,7 @@ permissions: jobs: comment-pr: - runs-on: ubuntu-22.04 + runs-on: ubuntu-latest steps: - name: Add comment about cloud build uses: thollander/actions-comment-pull-request@v2 From b1604e8459eeb17a8424dd44efeb86e69e60c55a Mon Sep 17 00:00:00 2001 From: Steve Evans Date: Thu, 2 Jan 2025 19:04:58 +0000 Subject: [PATCH 019/244] AT32F435 SD card support (#14018) Support either USE_FLASH or USE_SDCARD on AT32F435 --- .../middlewares/usbd_class/msc/msc_bot_scsi.c | 3 ++ src/platform/AT32/mk/AT32F4.mk | 3 +- src/platform/AT32/usb_msc_at32f43x.c | 35 +++++++++++++++++-- 3 files changed, 37 insertions(+), 4 deletions(-) diff --git a/lib/main/AT32F43x/middlewares/usbd_class/msc/msc_bot_scsi.c b/lib/main/AT32F43x/middlewares/usbd_class/msc/msc_bot_scsi.c index 8e8e740ff8..3b79860b32 100644 --- a/lib/main/AT32F43x/middlewares/usbd_class/msc/msc_bot_scsi.c +++ b/lib/main/AT32F43x/middlewares/usbd_class/msc/msc_bot_scsi.c @@ -23,6 +23,7 @@ */ #include "msc_bot_scsi.h" #include "msc_diskio.h" +#include "usbd_msc_mem.h" /** @addtogroup AT32F435_437_middlewares_usbd_class * @{ @@ -112,6 +113,8 @@ void bot_scsi_init(void *udev) pmsc->csw_struct.dCSWSignature = 0; pmsc->csw_struct.dCSWTag = CSW_BCSWSTATUS_PASS; + USBD_STORAGE_fops->Init(0); + usbd_flush_tx_fifo(pudev, USBD_MSC_BULK_IN_EPT&0x7F); /* set out endpoint to receive status */ diff --git a/src/platform/AT32/mk/AT32F4.mk b/src/platform/AT32/mk/AT32F4.mk index 66c04b4af3..610bb463be 100644 --- a/src/platform/AT32/mk/AT32F4.mk +++ b/src/platform/AT32/mk/AT32F4.mk @@ -124,7 +124,8 @@ MCU_COMMON_SRC = \ msc/usbd_storage.c \ msc/usbd_storage_emfat.c \ msc/emfat.c \ - msc/emfat_file.c + msc/emfat_file.c \ + msc/usbd_storage_sd_spi.c SPEED_OPTIMISED_SRC += \ common/stm32/system.c diff --git a/src/platform/AT32/usb_msc_at32f43x.c b/src/platform/AT32/usb_msc_at32f43x.c index 6a06dd8c16..42e7ec32ea 100644 --- a/src/platform/AT32/usb_msc_at32f43x.c +++ b/src/platform/AT32/usb_msc_at32f43x.c @@ -179,6 +179,35 @@ uint8_t mscStart(void) IOInit(IOGetByTag(IO_TAG(PA11)), OWNER_USB, 0); IOInit(IOGetByTag(IO_TAG(PA12)), OWNER_USB, 0); + switch (blackboxConfig()->device) { +#ifdef USE_SDCARD + case BLACKBOX_DEVICE_SDCARD: + switch (sdcardConfig()->mode) { +#ifdef USE_SDCARD_SDIO + case SDCARD_MODE_SDIO: + USBD_STORAGE_fops = &USBD_MSC_MICRO_SDIO_fops; + break; +#endif +#ifdef USE_SDCARD_SPI + case SDCARD_MODE_SPI: + USBD_STORAGE_fops = &USBD_MSC_MICRO_SD_SPI_fops; + break; +#endif + default: + return 1; + } + break; +#endif + +#ifdef USE_FLASHFS + case BLACKBOX_DEVICE_FLASH: + USBD_STORAGE_fops = &USBD_MSC_EMFAT_fops; + break; +#endif + default: + return 1; + } + msc_usb_gpio_config(); crm_periph_clock_enable(OTG_CLOCK, TRUE); msc_usb_clock48m_select(USB_CLK_HEXT); @@ -199,7 +228,7 @@ uint8_t mscStart(void) int8_t msc_disk_capacity(uint8_t lun, uint32_t *block_num, uint32_t *block_size) { - return USBD_MSC_EMFAT_fops.GetCapacity(lun, block_num, block_size); + return USBD_STORAGE_fops->GetCapacity(lun, block_num, block_size); } int8_t msc_disk_read( @@ -208,7 +237,7 @@ int8_t msc_disk_read( uint8_t *buf, // Pointer to the buffer to save data uint16_t blk_len) // number of blocks to be read { - return USBD_MSC_EMFAT_fops.Read(lun, buf, blk_addr, blk_len); + return USBD_STORAGE_fops->Read(lun, buf, blk_addr, blk_len); } int8_t msc_disk_write(uint8_t lun, @@ -228,7 +257,7 @@ uint8_t *get_inquiry(uint8_t lun) { UNUSED(lun); - return (uint8_t *)USBD_MSC_EMFAT_fops.pInquiry; + return (uint8_t *)USBD_STORAGE_fops->pInquiry; } uint8_t msc_get_readonly(uint8_t lun) From 456d9fd4a30eada623590b22e2f2bbd7d215ec9e Mon Sep 17 00:00:00 2001 From: Jay Blackman Date: Sat, 4 Jan 2025 00:22:25 +1100 Subject: [PATCH 020/244] Moving io_def_generated to platform (#14120) --- src/platform/APM32/mk/APM32F4.mk | 1 + src/platform/AT32/mk/AT32F4.mk | 1 + src/platform/SIMULATOR/io_def_generated.h | 25 ++++++++++++++++++ src/platform/STM32/mk/STM32F4.mk | 2 ++ src/platform/STM32/mk/STM32F7.mk | 2 ++ src/platform/STM32/mk/STM32G4.mk | 2 ++ src/platform/STM32/mk/STM32H5.mk | 2 ++ src/platform/STM32/mk/STM32H7.mk | 2 ++ src/platform/STM32/mk/STM32_COMMON.mk | 2 ++ .../common/stm32}/io_def_generated.h | 0 src/test/unit/io_def_generated.h | 26 +++++++++++++++++++ src/test/unit/rx_spi_expresslrs_unittest.cc | 2 +- src/test/unit/rx_spi_spektrum_unittest.cc | 2 +- 13 files changed, 67 insertions(+), 2 deletions(-) create mode 100644 src/platform/SIMULATOR/io_def_generated.h create mode 100644 src/platform/STM32/mk/STM32_COMMON.mk rename src/{main/drivers => platform/common/stm32}/io_def_generated.h (100%) create mode 100644 src/test/unit/io_def_generated.h diff --git a/src/platform/APM32/mk/APM32F4.mk b/src/platform/APM32/mk/APM32F4.mk index 6172080a02..42896d0957 100644 --- a/src/platform/APM32/mk/APM32F4.mk +++ b/src/platform/APM32/mk/APM32F4.mk @@ -113,6 +113,7 @@ VPATH := $(VPATH):$(LIB_MAIN_DIR)/APM32F4/Libraries/Device/Geehy/APM32F4xx INCLUDE_DIRS += \ $(TARGET_PLATFORM_DIR)/startup \ $(TARGET_PLATFORM_DIR) \ + $(PLATFORM_DIR)/common/stm32 \ $(STDPERIPH_DIR)/Include \ $(LIB_MAIN_DIR)/$(USBCORE_DIR)/Inc \ $(LIB_MAIN_DIR)/$(USBCDC_DIR)/Inc \ diff --git a/src/platform/AT32/mk/AT32F4.mk b/src/platform/AT32/mk/AT32F4.mk index 610bb463be..60711a67c0 100644 --- a/src/platform/AT32/mk/AT32F4.mk +++ b/src/platform/AT32/mk/AT32F4.mk @@ -63,6 +63,7 @@ DEVICE_STDPERIPH_SRC = $(STDPERIPH_SRC) INCLUDE_DIRS := $(INCLUDE_DIRS) \ $(TARGET_PLATFORM_DIR)/startup \ $(TARGET_PLATFORM_DIR) \ + $(PLATFORM_DIR)/common/stm32 \ $(STDPERIPH_DIR)/inc \ $(CMSIS_DIR)/cm4/core_support \ $(CMSIS_DIR)/cm4 \ diff --git a/src/platform/SIMULATOR/io_def_generated.h b/src/platform/SIMULATOR/io_def_generated.h new file mode 100644 index 0000000000..e127e5721f --- /dev/null +++ b/src/platform/SIMULATOR/io_def_generated.h @@ -0,0 +1,25 @@ +/* + * This file is part of Betaflight. + * + * Betaflight is free software. You can redistribute this software + * and/or modify this software under the terms of the GNU General + * Public License as published by the Free Software Foundation, + * either version 3 of the License, or (at your option) any later + * version. + * + * Betaflight is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * See the GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this software. + * + * If not, see . + */ + +#pragma once + +#define DEFIO_PORT_USED_COUNT 0 +#define DEFIO_IO_USED_COUNT 0 diff --git a/src/platform/STM32/mk/STM32F4.mk b/src/platform/STM32/mk/STM32F4.mk index 712940f561..a4b5aecfa3 100644 --- a/src/platform/STM32/mk/STM32F4.mk +++ b/src/platform/STM32/mk/STM32F4.mk @@ -252,3 +252,5 @@ MSC_SRC = \ DSP_LIB := $(LIB_MAIN_DIR)/CMSIS/DSP DEVICE_FLAGS += -DARM_MATH_MATRIX_CHECK -DARM_MATH_ROUNDING -D__FPU_PRESENT=1 -DUNALIGNED_SUPPORT_DISABLE -DARM_MATH_CM4 + +include $(TARGET_PLATFORM_DIR)/mk/STM32_COMMON.mk diff --git a/src/platform/STM32/mk/STM32F7.mk b/src/platform/STM32/mk/STM32F7.mk index 2cf48120cc..c8f1852ff4 100644 --- a/src/platform/STM32/mk/STM32F7.mk +++ b/src/platform/STM32/mk/STM32F7.mk @@ -211,3 +211,5 @@ SIZE_OPTIMISED_SRC += \ DSP_LIB := $(LIB_MAIN_DIR)/CMSIS/DSP DEVICE_FLAGS += -DARM_MATH_MATRIX_CHECK -DARM_MATH_ROUNDING -D__FPU_PRESENT=1 -DUNALIGNED_SUPPORT_DISABLE -DARM_MATH_CM7 + +include $(TARGET_PLATFORM_DIR)/mk/STM32_COMMON.mk diff --git a/src/platform/STM32/mk/STM32G4.mk b/src/platform/STM32/mk/STM32G4.mk index 2c10613da3..bd904c2dd9 100644 --- a/src/platform/STM32/mk/STM32G4.mk +++ b/src/platform/STM32/mk/STM32G4.mk @@ -184,3 +184,5 @@ SIZE_OPTIMISED_SRC += \ DSP_LIB := $(LIB_MAIN_DIR)/CMSIS/DSP DEVICE_FLAGS += -DARM_MATH_MATRIX_CHECK -DARM_MATH_ROUNDING -D__FPU_PRESENT=1 -DUNALIGNED_SUPPORT_DISABLE -DARM_MATH_CM4 + +include $(TARGET_PLATFORM_DIR)/mk/STM32_COMMON.mk diff --git a/src/platform/STM32/mk/STM32H5.mk b/src/platform/STM32/mk/STM32H5.mk index 21c0bd5a95..ee80cde798 100644 --- a/src/platform/STM32/mk/STM32H5.mk +++ b/src/platform/STM32/mk/STM32H5.mk @@ -218,3 +218,5 @@ SIZE_OPTIMISED_SRC += \ DSP_LIB := $(LIB_MAIN_DIR)/CMSIS/DSP DEVICE_FLAGS += -DARM_MATH_MATRIX_CHECK -DARM_MATH_ROUNDING -DUNALIGNED_SUPPORT_DISABLE -DARM_MATH_CM7 + +include $(TARGET_PLATFORM_DIR)/mk/STM32_COMMON.mk diff --git a/src/platform/STM32/mk/STM32H7.mk b/src/platform/STM32/mk/STM32H7.mk index 2129a1e11a..29d2a67930 100644 --- a/src/platform/STM32/mk/STM32H7.mk +++ b/src/platform/STM32/mk/STM32H7.mk @@ -333,3 +333,5 @@ SIZE_OPTIMISED_SRC += \ DSP_LIB := $(LIB_MAIN_DIR)/CMSIS/DSP DEVICE_FLAGS += -DARM_MATH_MATRIX_CHECK -DARM_MATH_ROUNDING -D__FPU_PRESENT=1 -DUNALIGNED_SUPPORT_DISABLE -DARM_MATH_CM7 + +include $(TARGET_PLATFORM_DIR)/mk/STM32_COMMON.mk diff --git a/src/platform/STM32/mk/STM32_COMMON.mk b/src/platform/STM32/mk/STM32_COMMON.mk new file mode 100644 index 0000000000..f109837f3a --- /dev/null +++ b/src/platform/STM32/mk/STM32_COMMON.mk @@ -0,0 +1,2 @@ + +INCLUDE_DIRS += $(PLATFORM_DIR)/common/stm32 diff --git a/src/main/drivers/io_def_generated.h b/src/platform/common/stm32/io_def_generated.h similarity index 100% rename from src/main/drivers/io_def_generated.h rename to src/platform/common/stm32/io_def_generated.h diff --git a/src/test/unit/io_def_generated.h b/src/test/unit/io_def_generated.h new file mode 100644 index 0000000000..30834f14a2 --- /dev/null +++ b/src/test/unit/io_def_generated.h @@ -0,0 +1,26 @@ +/* + * This file is part of Betaflight. + * + * Betaflight is free software. You can redistribute this software + * and/or modify this software under the terms of the GNU General + * Public License as published by the Free Software Foundation, + * either version 3 of the License, or (at your option) any later + * version. + * + * Betaflight is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * See the GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this software. + * + * If not, see . + */ + +#pragma once + +#define DEFIO_PORT_USED_COUNT 0 +#define DEFIO_IO_USED_COUNT 0 +#define IO_TAG_NONE 0 diff --git a/src/test/unit/rx_spi_expresslrs_unittest.cc b/src/test/unit/rx_spi_expresslrs_unittest.cc index d1cf06679e..e0f25393ed 100644 --- a/src/test/unit/rx_spi_expresslrs_unittest.cc +++ b/src/test/unit/rx_spi_expresslrs_unittest.cc @@ -54,7 +54,7 @@ extern "C" { static rxRuntimeState_t config = rxRuntimeState_t(); static rxSpiExtiConfig_t extiConfig; static const rxSpiConfig_t injectedConfig = { - .extiIoTag = IO_TAG(PA0), + .extiIoTag = IO_TAG_NONE, }; } diff --git a/src/test/unit/rx_spi_spektrum_unittest.cc b/src/test/unit/rx_spi_spektrum_unittest.cc index 03d6251273..acb1a59e1b 100644 --- a/src/test/unit/rx_spi_spektrum_unittest.cc +++ b/src/test/unit/rx_spi_spektrum_unittest.cc @@ -135,7 +135,7 @@ extern "C" { } static const rxSpiConfig_t injectedConfig = { - .extiIoTag = IO_TAG(PA0), + .extiIoTag = IO_TAG_NONE, }; } From d6739ed5667a774cd5f7097155e14d246b0b225c Mon Sep 17 00:00:00 2001 From: Ivan Efimov <2925027+limonspb@users.noreply.github.com> Date: Fri, 3 Jan 2025 07:23:13 -0600 Subject: [PATCH 021/244] Initialize all assigned servos even if some are missing (fix) (#14121) --- src/platform/STM32/pwm_output.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/platform/STM32/pwm_output.c b/src/platform/STM32/pwm_output.c index 5c996b7bbd..0e7f5b2f8a 100644 --- a/src/platform/STM32/pwm_output.c +++ b/src/platform/STM32/pwm_output.c @@ -291,7 +291,7 @@ void servoDevInit(const servoDevConfig_t *servoConfig) const ioTag_t tag = servoConfig->ioTags[servoIndex]; if (!tag) { - break; + continue; } servos[servoIndex].io = IOGetByTag(tag); From f6985a8bfaf33a09e28dd82eaea7a55950e90472 Mon Sep 17 00:00:00 2001 From: Mark Haslinghuis Date: Fri, 3 Jan 2025 14:43:33 +0100 Subject: [PATCH 022/244] Bump clang version to 18 (#14116) --- src/test/Makefile | 13 ++++++------ src/test/unit/cms_unittest.cc | 1 + src/test/unit/pg_unittest.cc | 18 ++++++++++++++++- src/test/unit/rc_controls_unittest.cc | 14 ++++++++++++- src/test/unit/rx_ibus_unittest.cc | 16 ++++----------- src/test/unit/rx_spi_expresslrs_unittest.cc | 8 ++++++++ src/test/unit/rx_spi_spektrum_unittest.cc | 8 ++++++++ src/test/unit/rx_sumd_unittest.cc | 16 ++++----------- src/test/unit/scheduler_unittest.cc | 4 +--- src/test/unit/telemetry_ibus_unittest.cc | 4 ++++ src/test/unit/unittest_displayport.h | 22 ++++++++++++++++++++- 11 files changed, 87 insertions(+), 37 deletions(-) diff --git a/src/test/Makefile b/src/test/Makefile index b6d2153b97..c4d12bf929 100644 --- a/src/test/Makefile +++ b/src/test/Makefile @@ -515,9 +515,9 @@ GTEST_DIR = ../../lib/test/gtest # Use clang/clang++ by default -CC := clang-15 -CXX := clang++-15 -ifeq ($(shell which $(CC) 2>/dev/null),) +CC := clang-18 +CXX := clang++-18 +ifeq ($(and $(shell which $(CC) 2>/dev/null), $(shell which $(CXX) 2>/dev/null)),) $(info Falling back to 'clang') CC := clang CXX := clang++ @@ -539,11 +539,10 @@ CXX_VERSION = $(shell $(CXX) -dumpversion) ifeq ($(shell $(CC) -v 2>&1 | grep -q "clang version" && echo "clang"),clang) -# Please revisit versions when new clang version arrive. Supported versions: { Linux / OSX: 7 - 16 } -# Travis reports CC_VERSION of 4.2.1 +# Please revisit versions when new clang version arrive. Supported versions: { Linux / OSX: 7 - 18 } CC_VERSION_MAJOR := $(firstword $(subst ., ,$(CC_VERSION))) CC_VERSION_CHECK_MIN := 7 -CC_VERSION_CHECK_MAX := 16 +CC_VERSION_CHECK_MAX := 18 # c99-designator is fine, code is not expected to be clean C++ COMMON_FLAGS += -Wno-c99-designator @@ -552,7 +551,7 @@ COMMON_FLAGS += -Wno-c99-designator COMMON_FLAGS += -Werror ifeq ($(shell expr $(CC_VERSION_MAJOR) \< $(CC_VERSION_CHECK_MIN) \| $(CC_VERSION_MAJOR) \> $(CC_VERSION_CHECK_MAX)),1) -$(error $(CC) $(CC_VERSION) is not supported. The officially supported version of clang is 'clang-15'. If this is not found, 'clang' is used as a fallback. The version of the compiler must be between $(CC_VERSION_CHECK_MIN) and $(CC_VERSION_CHECK_MAX).) +$(error $(CC) $(CC_VERSION) is not supported. The officially supported version of clang is 'clang-18'. If this is not found, 'clang' is used as a fallback. The version of the compiler must be between $(CC_VERSION_CHECK_MIN) and $(CC_VERSION_CHECK_MAX).) endif COMMON_FLAGS += -fblocks diff --git a/src/test/unit/cms_unittest.cc b/src/test/unit/cms_unittest.cc index 7d439ee7dc..b44c6401de 100644 --- a/src/test/unit/cms_unittest.cc +++ b/src/test/unit/cms_unittest.cc @@ -146,6 +146,7 @@ CMS_Menu cmsx_menuMain = { #endif .onEnter = NULL, .onExit = NULL, + .onDisplayUpdate = NULL, .entries = menuMainEntries, }; uint8_t armingFlags; diff --git a/src/test/unit/pg_unittest.cc b/src/test/unit/pg_unittest.cc index 8746dd34e6..23ce0c7fb8 100644 --- a/src/test/unit/pg_unittest.cc +++ b/src/test/unit/pg_unittest.cc @@ -35,9 +35,25 @@ extern "C" { PG_REGISTER_WITH_RESET_TEMPLATE(motorConfig_t, motorConfig, PG_MOTOR_CONFIG, 1); PG_RESET_TEMPLATE(motorConfig_t, motorConfig, - .dev = {.motorPwmRate = 400}, + .dev = { + .motorPwmRate = 400, + .motorPwmProtocol = 0, + .motorPwmInversion = 0, + .useUnsyncedPwm = 0, + .useBurstDshot = 0, + .useDshotTelemetry = 0, + .useDshotEdt = 0, + .ioTags = {IO_TAG_NONE, IO_TAG_NONE, IO_TAG_NONE, IO_TAG_NONE}, + .motorTransportProtocol = 0, + .useDshotBitbang = 0, + .useDshotBitbangedTimer = 0, + .motorOutputReordering = {0, 1, 2, 3}, + }, + .motorIdle = 0, .maxthrottle = 1850, .mincommand = 1000, + .kv = 1000, + .motorPoleCount = 14, ); } diff --git a/src/test/unit/rc_controls_unittest.cc b/src/test/unit/rc_controls_unittest.cc index 862c43119d..7120aa97d8 100644 --- a/src/test/unit/rc_controls_unittest.cc +++ b/src/test/unit/rc_controls_unittest.cc @@ -262,9 +262,15 @@ protected: controlRateConfig_t controlRateConfig = { .thrMid8 = 0, .thrExpo8 = 0, + .rates_type = RATES_TYPE_BETAFLIGHT, .rcRates = {[FD_ROLL] = 90, [FD_PITCH] = 90}, .rcExpo = {[FD_ROLL] = 0, [FD_PITCH] = 0, [FD_YAW] = 0}, .rates = {0, 0, 0}, + .throttle_limit_type = THROTTLE_LIMIT_TYPE_OFF, + .throttle_limit_percent = 100, + .rate_limit = {0, 0, 0}, + .profileName = "default", + .quickRatesRcExpo = 0, }; channelRange_t fullRange = { @@ -361,9 +367,15 @@ TEST_F(RcControlsAdjustmentsTest, processRcAdjustmentsWithRcRateFunctionSwitchUp controlRateConfig_t controlRateConfig = { .thrMid8 = 0, .thrExpo8 = 0, + .rates_type = RATES_TYPE_BETAFLIGHT, .rcRates = {[FD_ROLL] = 90, [FD_PITCH] = 90}, .rcExpo = {[FD_ROLL] = 0, [FD_PITCH] = 0, [FD_YAW] = 0}, - .rates = {0,0,0}, + .rates = {0, 0, 0}, + .throttle_limit_type = THROTTLE_LIMIT_TYPE_OFF, + .throttle_limit_percent = 100, + .rate_limit = {0, 0, 0}, + .profileName = "default", + .quickRatesRcExpo = 0, }; // and diff --git a/src/test/unit/rx_ibus_unittest.cc b/src/test/unit/rx_ibus_unittest.cc index b910a3a3b5..38ebf1d556 100644 --- a/src/test/unit/rx_ibus_unittest.cc +++ b/src/test/unit/rx_ibus_unittest.cc @@ -30,24 +30,12 @@ extern "C" { #include "telemetry/telemetry.h" #include "fc/rc_controls.h" #include "fc/rc_modes.h" -#include "sensors/barometer.h" #include "sensors/battery.h" } #include "unittest_macros.h" #include "gtest/gtest.h" - -extern "C" { - uint8_t batteryCellCount = 3; - float rcCommand[4] = {0, 0, 0, 0}; - int16_t telemTemperature1 = 0; - baro_t baro = { .temperature = 50 }; - telemetryConfig_t telemetryConfig_System; - timeUs_t rxFrameTimeUs(void) { return 0; } -} - - bool telemetryCheckRxPortShared(const serialPortConfig_t *portConfig) { //TODO: implement @@ -86,6 +74,10 @@ static serialPort_t serialTestInstance; static serialPortConfig_t serialTestInstanceConfig = { .functionMask = 0, .identifier = SERIAL_PORT_DUMMY_IDENTIFIER, + .msp_baudrateIndex = 0, + .gps_baudrateIndex = 0, + .blackbox_baudrateIndex = 0, + .telemetry_baudrateIndex = 0, }; static serialReceiveCallbackPtr stub_serialRxCallback; diff --git a/src/test/unit/rx_spi_expresslrs_unittest.cc b/src/test/unit/rx_spi_expresslrs_unittest.cc index e0f25393ed..90e7f6c82b 100644 --- a/src/test/unit/rx_spi_expresslrs_unittest.cc +++ b/src/test/unit/rx_spi_expresslrs_unittest.cc @@ -54,6 +54,14 @@ extern "C" { static rxRuntimeState_t config = rxRuntimeState_t(); static rxSpiExtiConfig_t extiConfig; static const rxSpiConfig_t injectedConfig = { + .rx_spi_protocol = 0, + .rx_spi_id = 0, + .rx_spi_rf_channel_count = 0, + .csnTag = IO_TAG_NONE, + .spibus = 0, + .bindIoTag = IO_TAG_NONE, + .ledIoTag = IO_TAG_NONE, + .ledInversion = 0, .extiIoTag = IO_TAG_NONE, }; } diff --git a/src/test/unit/rx_spi_spektrum_unittest.cc b/src/test/unit/rx_spi_spektrum_unittest.cc index acb1a59e1b..d9b76465f5 100644 --- a/src/test/unit/rx_spi_spektrum_unittest.cc +++ b/src/test/unit/rx_spi_spektrum_unittest.cc @@ -135,6 +135,14 @@ extern "C" { } static const rxSpiConfig_t injectedConfig = { + .rx_spi_protocol = 0, + .rx_spi_id = 0, + .rx_spi_rf_channel_count = 0, + .csnTag = IO_TAG_NONE, + .spibus = 0, + .bindIoTag = IO_TAG_NONE, + .ledIoTag = IO_TAG_NONE, + .ledInversion = 0, .extiIoTag = IO_TAG_NONE, }; } diff --git a/src/test/unit/rx_sumd_unittest.cc b/src/test/unit/rx_sumd_unittest.cc index 843d69ae71..d5f9d2a1ff 100644 --- a/src/test/unit/rx_sumd_unittest.cc +++ b/src/test/unit/rx_sumd_unittest.cc @@ -29,24 +29,12 @@ extern "C" { #include "telemetry/telemetry.h" #include "fc/rc_controls.h" #include "fc/rc_modes.h" -#include "sensors/barometer.h" #include "sensors/battery.h" } #include "unittest_macros.h" #include "gtest/gtest.h" - -extern "C" { - uint8_t batteryCellCount = 3; - float rcCommand[4] = {0, 0, 0, 0}; - int16_t telemTemperature1 = 0; - baro_t baro = { .temperature = 50 }; - telemetryConfig_t telemetryConfig_System; - timeUs_t rxFrameTimeUs(void) { return 0; } -} - - bool telemetryCheckRxPortShared(const serialPortConfig_t *portConfig, const SerialRXType serialrxProvider) { //TODO: implement @@ -88,6 +76,10 @@ static serialPort_t serialTestInstance; static serialPortConfig_t serialTestInstanceConfig = { .functionMask = 0, .identifier = SERIAL_PORT_DUMMY_IDENTIFIER, + .msp_baudrateIndex = 0, + .gps_baudrateIndex = 0, + .blackbox_baudrateIndex = 0, + .telemetry_baudrateIndex = 0, }; static serialReceiveCallbackPtr stub_serialRxCallback; diff --git a/src/test/unit/scheduler_unittest.cc b/src/test/unit/scheduler_unittest.cc index 5bb86782f5..b96a2c21cc 100644 --- a/src/test/unit/scheduler_unittest.cc +++ b/src/test/unit/scheduler_unittest.cc @@ -73,9 +73,7 @@ extern "C" { // set up tasks to take a simulated representative time to execute bool gyroFilterReady(void) { return taskFilterReady; } - gyroDev_t gyro { - .gyroModeSPI = GYRO_EXTI_NO_INT - }; + gyroDev_t gyro; gyroDev_t *gyroActiveDev(void) { return &gyro; } bool pidLoopReady(void) { return taskPidReady; } void failsafeCheckDataFailurePeriod(void) {} diff --git a/src/test/unit/telemetry_ibus_unittest.cc b/src/test/unit/telemetry_ibus_unittest.cc index 7119e11008..98d50dba1f 100644 --- a/src/test/unit/telemetry_ibus_unittest.cc +++ b/src/test/unit/telemetry_ibus_unittest.cc @@ -148,6 +148,10 @@ serialPort_t serialTestInstance; serialPortConfig_t serialTestInstanceConfig = { .functionMask = 0, .identifier = SERIAL_PORT_DUMMY_IDENTIFIER, + .msp_baudrateIndex = 5, + .gps_baudrateIndex = 5, + .blackbox_baudrateIndex = 5, + .telemetry_baudrateIndex = 5 }; static serialPortConfig_t *findSerialPortConfig_stub_retval; diff --git a/src/test/unit/unittest_displayport.h b/src/test/unit/unittest_displayport.h index 81cd715170..6c02f2770b 100644 --- a/src/test/unit/unittest_displayport.h +++ b/src/test/unit/unittest_displayport.h @@ -104,6 +104,15 @@ static void displayPortTestRedraw(displayPort_t *displayPort) UNUSED(displayPort); } +static int displayportWriteSys(displayPort_t *displayPort, uint8_t x, uint8_t y, displayPortSystemElement_e systemElement) +{ + UNUSED(displayPort); + UNUSED(x); + UNUSED(y); + UNUSED(systemElement); + return 0; +} + static uint32_t displayPortTestTxBytesFree(const displayPort_t *displayPort) { UNUSED(displayPort); @@ -116,12 +125,23 @@ static const displayPortVTable_t testDisplayPortVTable = { .clearScreen = displayPortTestClearScreen, .drawScreen = displayPortTestDrawScreen, .screenSize = displayPortTestScreenSize, + .writeSys = displayportWriteSys, .writeString = displayPortTestWriteString, .writeChar = displayPortTestWriteChar, .isTransferInProgress = displayPortTestIsTransferInProgress, .heartbeat = displayPortTestHeartbeat, .redraw = displayPortTestRedraw, - .txBytesFree = displayPortTestTxBytesFree + .isSynced = displayPortTestIsTransferInProgress, + .txBytesFree = displayPortTestTxBytesFree, + .layerSupported = NULL, + .layerSelect = NULL, + .layerCopy = NULL, + .writeFontCharacter = NULL, + .checkReady = NULL, + .beginTransaction = NULL, + .commitTransaction = NULL, + .getCanvas = NULL, + .setBackgroundType = NULL, }; displayPort_t *displayPortTestInit(void) From 60d35fa886c08f159dea79a32584199e7afe5720 Mon Sep 17 00:00:00 2001 From: Viacheslav Zhivetyev Date: Sat, 4 Jan 2025 18:22:36 +0100 Subject: [PATCH 023/244] Fixed - reset all PID controller terms when PASSTHRU_MODE is active (#14058) * [wing] reset all PID controller terms when PASSTHRU_MODE is active * Update src/main/flight/pid.c Co-authored-by: Petr Ledvina * Update src/main/flight/pid.c Co-authored-by: Mark Haslinghuis * Update src/main/flight/pid.c Co-authored-by: Mark Haslinghuis --------- Co-authored-by: Petr Ledvina Co-authored-by: Mark Haslinghuis --- src/main/flight/pid.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/src/main/flight/pid.c b/src/main/flight/pid.c index 4d5f0dad80..b0fa8fc43b 100644 --- a/src/main/flight/pid.c +++ b/src/main/flight/pid.c @@ -1475,9 +1475,19 @@ void FAST_CODE pidController(const pidProfile_t *pidProfile, timeUs_t currentTim } } +#ifdef USE_WING + // When PASSTHRU_MODE is active - reset all PIDs to zero so the aircraft won't snap out of control + // because of accumulated PIDs once PASSTHRU_MODE gets disabled. + bool isFixedWingAndPassthru = isFixedWing() && FLIGHT_MODE(PASSTHRU_MODE); +#endif // USE_WING // Disable PID control if at zero throttle or if gyro overflow detected // This may look very innefficient, but it is done on purpose to always show real CPU usage as in flight - if (!pidRuntime.pidStabilisationEnabled || gyroOverflowDetected()) { + if (!pidRuntime.pidStabilisationEnabled + || gyroOverflowDetected() +#ifdef USE_WING + || isFixedWingAndPassthru +#endif + ) { for (int axis = FD_ROLL; axis <= FD_YAW; ++axis) { pidData[axis].P = 0; pidData[axis].I = 0; From 926c21ce7d1ba5e3fa5770833319e13ddaf3f184 Mon Sep 17 00:00:00 2001 From: Jay Blackman Date: Mon, 6 Jan 2025 04:40:36 +1100 Subject: [PATCH 024/244] Move STM (and clone) related SPI implementation to platform (#14124) --- src/main/drivers/bus_spi.c | 364 +----------------- src/main/drivers/bus_spi.h | 55 +-- src/main/drivers/bus_spi_impl.h | 13 - src/platform/APM32/mk/APM32F4.mk | 6 +- src/platform/APM32/platform_mcu.h | 16 + src/platform/AT32/mk/AT32F4.mk | 6 +- src/platform/AT32/platform_mcu.h | 14 + src/platform/SIMULATOR/platform_mcu.h | 16 +- src/platform/STM32/mk/STM32F4.mk | 2 - src/platform/STM32/mk/STM32F7.mk | 2 - src/platform/STM32/mk/STM32G4.mk | 2 - src/platform/STM32/mk/STM32H5.mk | 2 - src/platform/STM32/mk/STM32H7.mk | 2 - src/platform/STM32/mk/STM32_COMMON.mk | 10 + src/platform/STM32/platform_mcu.h | 50 +++ src/platform/common/stm32/bus_spi_hw.c | 354 +++++++++++++++++ .../common/stm32}/bus_spi_pinconfig.c | 0 src/test/unit/platform.h | 1 + 18 files changed, 487 insertions(+), 428 deletions(-) create mode 100644 src/platform/common/stm32/bus_spi_hw.c rename src/{main/drivers => platform/common/stm32}/bus_spi_pinconfig.c (100%) diff --git a/src/main/drivers/bus_spi.c b/src/main/drivers/bus_spi.c index f9a9274376..f9ebf24713 100644 --- a/src/main/drivers/bus_spi.c +++ b/src/main/drivers/bus_spi.c @@ -36,15 +36,11 @@ #include "drivers/io.h" #include "drivers/motor.h" #include "drivers/rcc.h" -#include "nvic.h" +#include "drivers/nvic.h" #include "pg/bus_spi.h" #define NUM_QUEUE_SEGS 5 -#if !defined(STM32G4) && !defined(STM32H7) && !defined(AT32F435) -#define USE_TX_IRQ_HANDLER -#endif - static uint8_t spiRegisteredDeviceCount = 0; spiDevice_t spiDevice[SPIDEV_COUNT]; @@ -52,6 +48,12 @@ busDevice_t spiBusDevice[SPIDEV_COUNT]; SPIDevice spiDeviceByInstance(const SPI_TypeDef *instance) { +#ifdef USE_SPI_DEVICE_0 + if (instance == SPI0) { + return SPIDEV_0; + } +#endif + #ifdef USE_SPI_DEVICE_1 if (instance == SPI1) { return SPIDEV_1; @@ -104,57 +106,35 @@ bool spiInit(SPIDevice device) { switch (device) { case SPIINVALID: - return false; +#if !defined(USE_SPI_DEVICE_1) case SPIDEV_1: -#ifdef USE_SPI_DEVICE_1 - spiInitDevice(device); - return true; -#else - break; #endif +#if !defined(USE_SPI_DEVICE_2) case SPIDEV_2: -#ifdef USE_SPI_DEVICE_2 - spiInitDevice(device); - return true; -#else - break; #endif +#if !defined(USE_SPI_DEVICE_3) case SPIDEV_3: -#if defined(USE_SPI_DEVICE_3) - spiInitDevice(device); - return true; -#else - break; #endif +#if !defined(USE_SPI_DEVICE_4) case SPIDEV_4: -#if defined(USE_SPI_DEVICE_4) - spiInitDevice(device); - return true; -#else - break; #endif +#if !defined(USE_SPI_DEVICE_5) case SPIDEV_5: -#if defined(USE_SPI_DEVICE_5) - spiInitDevice(device); - return true; -#else - break; #endif +#if !defined(USE_SPI_DEVICE_6) case SPIDEV_6: -#if defined(USE_SPI_DEVICE_6) +#endif + return false; + default: spiInitDevice(device); return true; -#else - break; -#endif } - return false; } // Return true if DMA engine is busy @@ -356,183 +336,6 @@ uint8_t spiReadRegMsk(const extDevice_t *dev, uint8_t reg) return spiReadReg(dev, reg | 0x80); } -uint16_t spiCalculateDivider(uint32_t freq) -{ -#if defined(STM32F4) || defined(STM32G4) || defined(STM32F7) || defined(APM32F4) - uint32_t spiClk = SystemCoreClock / 2; -#elif defined(STM32H7) - uint32_t spiClk = 100000000; -#elif defined(AT32F4) - if(freq > 36000000){ - freq = 36000000; - } - - uint32_t spiClk = system_core_clock / 2; -#else -#error "Base SPI clock not defined for this architecture" -#endif - - uint16_t divisor = 2; - - spiClk >>= 1; - - for (; (spiClk > freq) && (divisor < 256); divisor <<= 1, spiClk >>= 1); - - return divisor; -} - -uint32_t spiCalculateClock(uint16_t spiClkDivisor) -{ -#if defined(STM32F4) || defined(STM32G4) || defined(STM32F7) || defined(APM32F4) - uint32_t spiClk = SystemCoreClock / 2; -#elif defined(STM32H7) - uint32_t spiClk = 100000000; -#elif defined(AT32F4) - uint32_t spiClk = system_core_clock / 2; - - if ((spiClk / spiClkDivisor) > 36000000){ - return 36000000; - } -#else -#error "Base SPI clock not defined for this architecture" -#endif - - return spiClk / spiClkDivisor; -} - -// Interrupt handler for SPI receive DMA completion -FAST_IRQ_HANDLER static void spiIrqHandler(const extDevice_t *dev) -{ - busDevice_t *bus = dev->bus; - busSegment_t *nextSegment; - - if (bus->curSegment->callback) { - switch(bus->curSegment->callback(dev->callbackArg)) { - case BUS_BUSY: - // Repeat the last DMA segment - bus->curSegment--; - // Reinitialise the cached init values as segment is not progressing - spiInternalInitStream(dev, true); - break; - - case BUS_ABORT: - // Skip to the end of the segment list - nextSegment = (busSegment_t *)bus->curSegment + 1; - while (nextSegment->len != 0) { - bus->curSegment = nextSegment; - nextSegment = (busSegment_t *)bus->curSegment + 1; - } - break; - - case BUS_READY: - default: - // Advance to the next DMA segment - break; - } - } - - // Advance through the segment list - // OK to discard the volatile qualifier here - nextSegment = (busSegment_t *)bus->curSegment + 1; - - if (nextSegment->len == 0) { - // If a following transaction has been linked, start it - if (nextSegment->u.link.dev) { - const extDevice_t *nextDev = nextSegment->u.link.dev; - busSegment_t *nextSegments = (busSegment_t *)nextSegment->u.link.segments; - // The end of the segment list has been reached - bus->curSegment = nextSegments; - nextSegment->u.link.dev = NULL; - nextSegment->u.link.segments = NULL; - spiSequenceStart(nextDev); - } else { - // The end of the segment list has been reached, so mark transactions as complete - bus->curSegment = (busSegment_t *)BUS_SPI_FREE; - } - } else { - // Do as much processing as possible before asserting CS to avoid violating minimum high time - bool negateCS = bus->curSegment->negateCS; - - bus->curSegment = nextSegment; - - // After the completion of the first segment setup the init structure for the subsequent segment - if (bus->initSegment) { - spiInternalInitStream(dev, false); - bus->initSegment = false; - } - - if (negateCS) { - // Assert Chip Select - it's costly so only do so if necessary - IOLo(dev->busType_u.spi.csnPin); - } - - // Launch the next transfer - spiInternalStartDMA(dev); - - // Prepare the init structures ready for the next segment to reduce inter-segment time - spiInternalInitStream(dev, true); - } -} - -// Interrupt handler for SPI receive DMA completion -FAST_IRQ_HANDLER static void spiRxIrqHandler(dmaChannelDescriptor_t* descriptor) -{ - const extDevice_t *dev = (const extDevice_t *)descriptor->userParam; - - if (!dev) { - return; - } - - busDevice_t *bus = dev->bus; - - if (bus->curSegment->negateCS) { - // Negate Chip Select - IOHi(dev->busType_u.spi.csnPin); - } - - spiInternalStopDMA(dev); - -#ifdef __DCACHE_PRESENT -#ifdef STM32H7 - if (bus->curSegment->u.buffers.rxData && - ((bus->curSegment->u.buffers.rxData < &_dmaram_start__) || (bus->curSegment->u.buffers.rxData >= &_dmaram_end__))) { -#else - if (bus->curSegment->u.buffers.rxData) { -#endif - // Invalidate the D cache covering the area into which data has been read - SCB_InvalidateDCache_by_Addr( - (uint32_t *)((uint32_t)bus->curSegment->u.buffers.rxData & ~CACHE_LINE_MASK), - (((uint32_t)bus->curSegment->u.buffers.rxData & CACHE_LINE_MASK) + - bus->curSegment->len - 1 + CACHE_LINE_SIZE) & ~CACHE_LINE_MASK); - } -#endif // __DCACHE_PRESENT - - spiIrqHandler(dev); -} - -#ifdef USE_TX_IRQ_HANDLER -// Interrupt handler for SPI transmit DMA completion -FAST_IRQ_HANDLER static void spiTxIrqHandler(dmaChannelDescriptor_t* descriptor) -{ - const extDevice_t *dev = (const extDevice_t *)descriptor->userParam; - - if (!dev) { - return; - } - - busDevice_t *bus = dev->bus; - - spiInternalStopDMA(dev); - - if (bus->curSegment->negateCS) { - // Negate Chip Select - IOHi(dev->busType_u.spi.csnPin); - } - - spiIrqHandler(dev); -} -#endif - // Mark this bus as being SPI and record the first owner to use it bool spiSetBusInstance(extDevice_t *dev, uint32_t device) { @@ -568,141 +371,6 @@ bool spiSetBusInstance(extDevice_t *dev, uint32_t device) return true; } -void spiInitBusDMA(void) -{ - uint32_t device; -#if (defined(STM32F4) || defined(APM32F4)) && defined(USE_DSHOT_BITBANG) - /* Check https://www.st.com/resource/en/errata_sheet/dm00037591-stm32f405407xx-and-stm32f415417xx-device-limitations-stmicroelectronics.pdf - * section 2.1.10 which reports an errata that corruption may occurs on DMA2 if AHB peripherals (eg GPIO ports) are - * access concurrently with APB peripherals (eg SPI busses). Bitbang DSHOT uses DMA2 to write to GPIO ports. If this - * is enabled, then don't enable DMA on an SPI bus using DMA2 - */ - const bool dshotBitbangActive = isDshotBitbangActive(&motorConfig()->dev); -#endif - - for (device = 0; device < SPIDEV_COUNT; device++) { - busDevice_t *bus = &spiBusDevice[device]; - - if (bus->busType != BUS_TYPE_SPI) { - // This bus is not in use - continue; - } - - dmaIdentifier_e dmaTxIdentifier = DMA_NONE; - dmaIdentifier_e dmaRxIdentifier = DMA_NONE; - - int8_t txDmaopt = spiPinConfig(device)->txDmaopt; - uint8_t txDmaoptMin = 0; - uint8_t txDmaoptMax = MAX_PERIPHERAL_DMA_OPTIONS - 1; - - if (txDmaopt != -1) { - txDmaoptMin = txDmaopt; - txDmaoptMax = txDmaopt; - } - - for (uint8_t opt = txDmaoptMin; opt <= txDmaoptMax; opt++) { - const dmaChannelSpec_t *dmaTxChannelSpec = dmaGetChannelSpecByPeripheral(DMA_PERIPH_SPI_SDO, device, opt); - - if (dmaTxChannelSpec) { - dmaTxIdentifier = dmaGetIdentifier(dmaTxChannelSpec->ref); -#if (defined(STM32F4) || defined(APM32F4)) && defined(USE_DSHOT_BITBANG) - if (dshotBitbangActive && (DMA_DEVICE_NO(dmaTxIdentifier) == 2)) { - dmaTxIdentifier = DMA_NONE; - break; - } -#endif - if (!dmaAllocate(dmaTxIdentifier, OWNER_SPI_SDO, device + 1)) { - dmaTxIdentifier = DMA_NONE; - continue; - } - bus->dmaTx = dmaGetDescriptorByIdentifier(dmaTxIdentifier); -#if defined(STM32F4) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) || defined(APM32F4) - bus->dmaTx->stream = DMA_DEVICE_INDEX(dmaTxIdentifier); - bus->dmaTx->channel = dmaTxChannelSpec->channel; -#endif - - dmaEnable(dmaTxIdentifier); -#if defined(USE_ATBSP_DRIVER) - dmaMuxEnable(dmaTxIdentifier,dmaTxChannelSpec->dmaMuxId); -#endif - break; - } - } - - int8_t rxDmaopt = spiPinConfig(device)->rxDmaopt; - uint8_t rxDmaoptMin = 0; - uint8_t rxDmaoptMax = MAX_PERIPHERAL_DMA_OPTIONS - 1; - - if (rxDmaopt != -1) { - rxDmaoptMin = rxDmaopt; - rxDmaoptMax = rxDmaopt; - } - - for (uint8_t opt = rxDmaoptMin; opt <= rxDmaoptMax; opt++) { - const dmaChannelSpec_t *dmaRxChannelSpec = dmaGetChannelSpecByPeripheral(DMA_PERIPH_SPI_SDI, device, opt); - - if (dmaRxChannelSpec) { - dmaRxIdentifier = dmaGetIdentifier(dmaRxChannelSpec->ref); -#if (defined(STM32F4) || defined(APM32F4)) && defined(USE_DSHOT_BITBANG) - if (dshotBitbangActive && (DMA_DEVICE_NO(dmaRxIdentifier) == 2)) { - dmaRxIdentifier = DMA_NONE; - break; - } -#endif - if (!dmaAllocate(dmaRxIdentifier, OWNER_SPI_SDI, device + 1)) { - dmaRxIdentifier = DMA_NONE; - continue; - } - bus->dmaRx = dmaGetDescriptorByIdentifier(dmaRxIdentifier); -#if defined(STM32F4) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) || defined(APM32F4) - bus->dmaRx->stream = DMA_DEVICE_INDEX(dmaRxIdentifier); - bus->dmaRx->channel = dmaRxChannelSpec->channel; -#endif - - dmaEnable(dmaRxIdentifier); -#if defined(USE_ATBSP_DRIVER) - dmaMuxEnable(dmaRxIdentifier,dmaRxChannelSpec->dmaMuxId); -#endif - break; - } - } - - if (dmaTxIdentifier && dmaRxIdentifier) { - // Ensure streams are disabled - spiInternalResetStream(bus->dmaRx); - spiInternalResetStream(bus->dmaTx); - - spiInternalResetDescriptors(bus); - - /* Note that this driver may be called both from the normal thread of execution, or from USB interrupt - * handlers, so the DMA completion interrupt must be at a higher priority - */ - dmaSetHandler(dmaRxIdentifier, spiRxIrqHandler, NVIC_PRIO_SPI_DMA, 0); - - bus->useDMA = true; -#ifdef USE_TX_IRQ_HANDLER - } else if (dmaTxIdentifier) { - // Transmit on DMA is adequate for OSD so worth having - bus->dmaTx = dmaGetDescriptorByIdentifier(dmaTxIdentifier); - bus->dmaRx = (dmaChannelDescriptor_t *)NULL; - - // Ensure streams are disabled - spiInternalResetStream(bus->dmaTx); - - spiInternalResetDescriptors(bus); - - dmaSetHandler(dmaTxIdentifier, spiTxIrqHandler, NVIC_PRIO_SPI_DMA, 0); - - bus->useDMA = true; -#endif - } else { - // Disassociate channels from bus - bus->dmaRx = (dmaChannelDescriptor_t *)NULL; - bus->dmaTx = (dmaChannelDescriptor_t *)NULL; - } - } -} - void spiSetClkDivisor(const extDevice_t *dev, uint16_t divisor) { ((extDevice_t *)dev)->busType_u.spi.speed = divisor; diff --git a/src/main/drivers/bus_spi.h b/src/main/drivers/bus_spi.h index 48f48cedb5..530d38899a 100644 --- a/src/main/drivers/bus_spi.h +++ b/src/main/drivers/bus_spi.h @@ -20,36 +20,15 @@ #pragma once +#include "platform.h" + #include "drivers/bus.h" #include "drivers/io_types.h" #include "drivers/bus.h" -#include "drivers/rcc_types.h" #include "pg/pg.h" #include "pg/pg_ids.h" -#if defined(STM32F4) -#define SPI_IO_AF_CFG IO_CONFIG(GPIO_Mode_AF, GPIO_Speed_50MHz, GPIO_OType_PP, GPIO_PuPd_NOPULL) -#define SPI_IO_AF_SCK_CFG IO_CONFIG(GPIO_Mode_AF, GPIO_Speed_50MHz, GPIO_OType_PP, GPIO_PuPd_DOWN) -#define SPI_IO_AF_SDI_CFG IO_CONFIG(GPIO_Mode_AF, GPIO_Speed_50MHz, GPIO_OType_PP, GPIO_PuPd_UP) -#define SPI_IO_CS_CFG IO_CONFIG(GPIO_Mode_OUT, GPIO_Speed_50MHz, GPIO_OType_PP, GPIO_PuPd_NOPULL) -#define SPI_IO_CS_HIGH_CFG IO_CONFIG(GPIO_Mode_IN, GPIO_Speed_50MHz, GPIO_OType_PP, GPIO_PuPd_UP) -#elif defined(STM32F7) || defined(STM32H7) || defined(STM32G4) || defined(APM32F4) -#define SPI_IO_AF_CFG IO_CONFIG(GPIO_MODE_AF_PP, GPIO_SPEED_FREQ_VERY_HIGH, GPIO_NOPULL) -#define SPI_IO_AF_SCK_CFG_HIGH IO_CONFIG(GPIO_MODE_AF_PP, GPIO_SPEED_FREQ_VERY_HIGH, GPIO_PULLUP) -#define SPI_IO_AF_SCK_CFG_LOW IO_CONFIG(GPIO_MODE_AF_PP, GPIO_SPEED_FREQ_VERY_HIGH, GPIO_PULLDOWN) -#define SPI_IO_AF_SDI_CFG IO_CONFIG(GPIO_MODE_AF_PP, GPIO_SPEED_FREQ_VERY_HIGH, GPIO_PULLUP) -#define SPI_IO_CS_CFG IO_CONFIG(GPIO_MODE_OUTPUT_PP, GPIO_SPEED_FREQ_VERY_HIGH, GPIO_NOPULL) -#define SPI_IO_CS_HIGH_CFG IO_CONFIG(GPIO_MODE_INPUT, GPIO_SPEED_FREQ_VERY_HIGH, GPIO_PULLUP) -#elif defined(AT32F4) -#define SPI_IO_AF_CFG IO_CONFIG(GPIO_MODE_MUX, GPIO_DRIVE_STRENGTH_STRONGER, GPIO_OUTPUT_PUSH_PULL, GPIO_PULL_NONE) -#define SPI_IO_AF_SCK_CFG_HIGH IO_CONFIG(GPIO_MODE_MUX, GPIO_DRIVE_STRENGTH_STRONGER, GPIO_OUTPUT_PUSH_PULL, GPIO_PULL_UP) -#define SPI_IO_AF_SCK_CFG_LOW IO_CONFIG(GPIO_MODE_MUX, GPIO_DRIVE_STRENGTH_STRONGER, GPIO_OUTPUT_PUSH_PULL, GPIO_PULL_DOWN) -#define SPI_IO_AF_SDI_CFG IO_CONFIG(GPIO_MODE_MUX, GPIO_DRIVE_STRENGTH_STRONGER, GPIO_OUTPUT_PUSH_PULL, GPIO_PULL_UP) -#define SPI_IO_CS_CFG IO_CONFIG(GPIO_MODE_OUTPUT, GPIO_DRIVE_STRENGTH_STRONGER, GPIO_OUTPUT_PUSH_PULL, GPIO_PULL_NONE) -#define SPI_IO_CS_HIGH_CFG IO_CONFIG(GPIO_MODE_INPUT, GPIO_DRIVE_STRENGTH_STRONGER, GPIO_OUTPUT_PUSH_PULL, GPIO_PULL_UP) -#endif - // De facto standard mode // See https://en.wikipedia.org/wiki/Serial_Peripheral_Interface // @@ -67,7 +46,13 @@ typedef enum { typedef enum SPIDevice { SPIINVALID = -1, - SPIDEV_1 = 0, + SPIDEV_FIRST = 0, +#if defined(USE_SPI_DEVICE_0) + SPIDEV_0 = SPIDEV_FIRST, + SPIDEV_1, +#else + SPIDEV_1 = SPIDEV_FIRST, +#endif SPIDEV_2, SPIDEV_3, SPIDEV_4, @@ -75,31 +60,10 @@ typedef enum SPIDevice { SPIDEV_6 } SPIDevice; -#if defined(STM32F4) -#define SPIDEV_COUNT 3 -#elif defined(STM32F7) -#define SPIDEV_COUNT 4 -#elif defined(STM32H7) -#define SPIDEV_COUNT 6 -#elif defined(APM32F4) -#define SPIDEV_COUNT 3 -#else -#define SPIDEV_COUNT 4 -#endif - // Macros to convert between CLI bus number and SPIDevice. #define SPI_CFG_TO_DEV(x) ((x) - 1) #define SPI_DEV_TO_CFG(x) ((x) + 1) -// Work around different check routines in the libraries for different MCU types -#if defined(STM32H7) -#define CHECK_SPI_RX_DATA_AVAILABLE(instance) LL_SPI_IsActiveFlag_RXWNE(instance) -#define SPI_RX_DATA_REGISTER(base) ((base)->RXDR) -#else -#define CHECK_SPI_RX_DATA_AVAILABLE(instance) LL_SPI_IsActiveFlag_RXNE(instance) -#define SPI_RX_DATA_REGISTER(base) ((base)->DR) -#endif - void spiPreinit(void); void spiPreinitRegister(ioTag_t iotag, uint8_t iocfg, uint8_t init); void spiPreinitByIO(const IO_t io); @@ -180,4 +144,3 @@ bool spiUseSDO_DMA(const extDevice_t *dev); void spiBusDeviceRegister(const extDevice_t *dev); uint8_t spiGetRegisteredDeviceCount(void); uint8_t spiGetExtDeviceCount(const extDevice_t *dev); - diff --git a/src/main/drivers/bus_spi_impl.h b/src/main/drivers/bus_spi_impl.h index 11ce5d9f79..c75c117c65 100644 --- a/src/main/drivers/bus_spi_impl.h +++ b/src/main/drivers/bus_spi_impl.h @@ -22,18 +22,6 @@ #define SPI_TIMEOUT_US 10000 -#if defined(STM32F4) || defined(STM32G4) -#define MAX_SPI_PIN_SEL 2 -#elif defined(STM32F7) || defined(AT32F4) -#define MAX_SPI_PIN_SEL 4 -#elif defined(STM32H7) -#define MAX_SPI_PIN_SEL 5 -#elif defined(APM32F4) -#define MAX_SPI_PIN_SEL 2 -#else -#error Unknown MCU family -#endif - #define BUS_SPI_FREE 0x0 typedef struct spiPinDef_s { @@ -92,4 +80,3 @@ void spiInternalStopDMA (const extDevice_t *dev); void spiInternalResetStream(dmaChannelDescriptor_t *descriptor); void spiInternalResetDescriptors(busDevice_t *bus); void spiSequenceStart(const extDevice_t *dev); - diff --git a/src/platform/APM32/mk/APM32F4.mk b/src/platform/APM32/mk/APM32F4.mk index 42896d0957..c222e67ec0 100644 --- a/src/platform/APM32/mk/APM32F4.mk +++ b/src/platform/APM32/mk/APM32F4.mk @@ -176,7 +176,8 @@ MCU_COMMON_SRC = \ drivers/adc.c \ drivers/bus_i2c_config.c \ drivers/bus_spi_config.c \ - drivers/bus_spi_pinconfig.c \ + common/stm32/bus_spi_pinconfig.c \ + common/stm32/bus_spi_hw.c \ drivers/serial_escserial.c \ drivers/serial_pinconfig.c \ drivers/serial_uart_pinconfig.c \ @@ -202,6 +203,7 @@ MSC_SRC = \ msc/usbd_storage_sdio.c SPEED_OPTIMISED_SRC += \ + common/stm32/bus_spi_hw.c \ common/stm32/system.c SIZE_OPTIMISED_SRC += \ @@ -209,7 +211,7 @@ SIZE_OPTIMISED_SRC += \ drivers/inverter.c \ drivers/bus_i2c_config.c \ drivers/bus_spi_config.c \ - drivers/bus_spi_pinconfig.c \ + common/stm32/bus_spi_pinconfig.c \ drivers/serial_escserial.c \ drivers/serial_pinconfig.c \ drivers/serial_uart_pinconfig.c diff --git a/src/platform/APM32/platform_mcu.h b/src/platform/APM32/platform_mcu.h index a70dd37c9f..769d1cc3ed 100644 --- a/src/platform/APM32/platform_mcu.h +++ b/src/platform/APM32/platform_mcu.h @@ -171,4 +171,20 @@ #define IO_CONFIG_GET_OTYPE(cfg) (((cfg) >> 4) & 0x01) #define IO_CONFIG_GET_PULL(cfg) (((cfg) >> 5) & 0x03) +#define SPI_IO_AF_CFG IO_CONFIG(GPIO_MODE_AF_PP, GPIO_SPEED_FREQ_VERY_HIGH, GPIO_NOPULL) +#define SPI_IO_AF_SCK_CFG_HIGH IO_CONFIG(GPIO_MODE_AF_PP, GPIO_SPEED_FREQ_VERY_HIGH, GPIO_PULLUP) +#define SPI_IO_AF_SCK_CFG_LOW IO_CONFIG(GPIO_MODE_AF_PP, GPIO_SPEED_FREQ_VERY_HIGH, GPIO_PULLDOWN) +#define SPI_IO_AF_SDI_CFG IO_CONFIG(GPIO_MODE_AF_PP, GPIO_SPEED_FREQ_VERY_HIGH, GPIO_PULLUP) +#define SPI_IO_CS_CFG IO_CONFIG(GPIO_MODE_OUTPUT_PP, GPIO_SPEED_FREQ_VERY_HIGH, GPIO_NOPULL) +#define SPI_IO_CS_HIGH_CFG IO_CONFIG(GPIO_MODE_INPUT, GPIO_SPEED_FREQ_VERY_HIGH, GPIO_PULLUP) + +#define SPIDEV_COUNT 3 + +#define CHECK_SPI_RX_DATA_AVAILABLE(instance) LL_SPI_IsActiveFlag_RXNE(instance) +#define SPI_RX_DATA_REGISTER(base) ((base)->DR) + +#define MAX_SPI_PIN_SEL 2 + +#define USE_TX_IRQ_HANDLER + #endif diff --git a/src/platform/AT32/mk/AT32F4.mk b/src/platform/AT32/mk/AT32F4.mk index 60711a67c0..3053712fdd 100644 --- a/src/platform/AT32/mk/AT32F4.mk +++ b/src/platform/AT32/mk/AT32F4.mk @@ -118,7 +118,8 @@ MCU_COMMON_SRC = \ drivers/adc.c \ drivers/bus_i2c_config.c \ drivers/bus_spi_config.c \ - drivers/bus_spi_pinconfig.c \ + common/stm32/bus_spi_pinconfig.c \ + common/stm32/bus_spi_hw.c \ drivers/serial_escserial.c \ drivers/serial_pinconfig.c \ drivers/serial_uart_pinconfig.c \ @@ -129,6 +130,7 @@ MCU_COMMON_SRC = \ msc/usbd_storage_sd_spi.c SPEED_OPTIMISED_SRC += \ + common/stm32/bus_spi_hw.c \ common/stm32/system.c SIZE_OPTIMISED_SRC += \ @@ -136,7 +138,7 @@ SIZE_OPTIMISED_SRC += \ drivers/inverter.c \ drivers/bus_i2c_config.c \ drivers/bus_spi_config.c \ - drivers/bus_spi_pinconfig.c \ + common/stm32/bus_spi_pinconfig.c \ drivers/serial_escserial.c \ drivers/serial_pinconfig.c \ drivers/serial_uart_pinconfig.c diff --git a/src/platform/AT32/platform_mcu.h b/src/platform/AT32/platform_mcu.h index a65401fef4..36baa0f7fc 100644 --- a/src/platform/AT32/platform_mcu.h +++ b/src/platform/AT32/platform_mcu.h @@ -127,4 +127,18 @@ typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; #define IO_CONFIG_GET_OTYPE(cfg) (((cfg) >> 4) & 0x01) #define IO_CONFIG_GET_PULL(cfg) (((cfg) >> 5) & 0x03) +#define SPI_IO_AF_CFG IO_CONFIG(GPIO_MODE_MUX, GPIO_DRIVE_STRENGTH_STRONGER, GPIO_OUTPUT_PUSH_PULL, GPIO_PULL_NONE) +#define SPI_IO_AF_SCK_CFG_HIGH IO_CONFIG(GPIO_MODE_MUX, GPIO_DRIVE_STRENGTH_STRONGER, GPIO_OUTPUT_PUSH_PULL, GPIO_PULL_UP) +#define SPI_IO_AF_SCK_CFG_LOW IO_CONFIG(GPIO_MODE_MUX, GPIO_DRIVE_STRENGTH_STRONGER, GPIO_OUTPUT_PUSH_PULL, GPIO_PULL_DOWN) +#define SPI_IO_AF_SDI_CFG IO_CONFIG(GPIO_MODE_MUX, GPIO_DRIVE_STRENGTH_STRONGER, GPIO_OUTPUT_PUSH_PULL, GPIO_PULL_UP) +#define SPI_IO_CS_CFG IO_CONFIG(GPIO_MODE_OUTPUT, GPIO_DRIVE_STRENGTH_STRONGER, GPIO_OUTPUT_PUSH_PULL, GPIO_PULL_NONE) +#define SPI_IO_CS_HIGH_CFG IO_CONFIG(GPIO_MODE_INPUT, GPIO_DRIVE_STRENGTH_STRONGER, GPIO_OUTPUT_PUSH_PULL, GPIO_PULL_UP) + +#define SPIDEV_COUNT 4 + +#define CHECK_SPI_RX_DATA_AVAILABLE(instance) LL_SPI_IsActiveFlag_RXNE(instance) +#define SPI_RX_DATA_REGISTER(base) ((base)->DR) + +#define MAX_SPI_PIN_SEL 4 + #endif diff --git a/src/platform/SIMULATOR/platform_mcu.h b/src/platform/SIMULATOR/platform_mcu.h index effbc91aab..5e9fb85ac6 100644 --- a/src/platform/SIMULATOR/platform_mcu.h +++ b/src/platform/SIMULATOR/platform_mcu.h @@ -21,10 +21,12 @@ #pragma once -#define IOCFG_OUT_PP 0 -#define IOCFG_OUT_OD 0 -#define IOCFG_AF_PP 0 -#define IOCFG_AF_OD 0 -#define IOCFG_IPD 0 -#define IOCFG_IPU 0 -#define IOCFG_IN_FLOATING 0 +#define IOCFG_OUT_PP 0 +#define IOCFG_OUT_OD 0 +#define IOCFG_AF_PP 0 +#define IOCFG_AF_OD 0 +#define IOCFG_IPD 0 +#define IOCFG_IPU 0 +#define IOCFG_IN_FLOATING 0 + +#define SPIDEV_COUNT 0 diff --git a/src/platform/STM32/mk/STM32F4.mk b/src/platform/STM32/mk/STM32F4.mk index a4b5aecfa3..43fc7b16b7 100644 --- a/src/platform/STM32/mk/STM32F4.mk +++ b/src/platform/STM32/mk/STM32F4.mk @@ -202,7 +202,6 @@ MCU_COMMON_SRC = \ drivers/adc.c \ drivers/bus_i2c_config.c \ drivers/bus_spi_config.c \ - drivers/bus_spi_pinconfig.c \ drivers/serial_escserial.c \ drivers/serial_pinconfig.c \ drivers/serial_uart_pinconfig.c \ @@ -217,7 +216,6 @@ SIZE_OPTIMISED_SRC += \ drivers/inverter.c \ drivers/bus_i2c_config.c \ drivers/bus_spi_config.c \ - drivers/bus_spi_pinconfig.c \ drivers/serial_escserial.c \ drivers/serial_pinconfig.c diff --git a/src/platform/STM32/mk/STM32F7.mk b/src/platform/STM32/mk/STM32F7.mk index c8f1852ff4..b0341b7c75 100644 --- a/src/platform/STM32/mk/STM32F7.mk +++ b/src/platform/STM32/mk/STM32F7.mk @@ -173,7 +173,6 @@ MCU_COMMON_SRC = \ drivers/adc.c \ drivers/bus_i2c_config.c \ drivers/bus_spi_config.c \ - drivers/bus_spi_pinconfig.c \ drivers/serial_escserial.c \ drivers/serial_pinconfig.c \ drivers/serial_uart_pinconfig.c \ @@ -204,7 +203,6 @@ SIZE_OPTIMISED_SRC += \ STM32/serial_usb_vcp.c \ drivers/bus_i2c_config.c \ drivers/bus_spi_config.c \ - drivers/bus_spi_pinconfig.c \ drivers/serial_escserial.c \ drivers/serial_pinconfig.c \ drivers/serial_uart_pinconfig.c diff --git a/src/platform/STM32/mk/STM32G4.mk b/src/platform/STM32/mk/STM32G4.mk index bd904c2dd9..8acdd13fca 100644 --- a/src/platform/STM32/mk/STM32G4.mk +++ b/src/platform/STM32/mk/STM32G4.mk @@ -150,7 +150,6 @@ MCU_COMMON_SRC = \ drivers/adc.c \ drivers/bus_i2c_config.c \ drivers/bus_spi_config.c \ - drivers/bus_spi_pinconfig.c \ drivers/serial_escserial.c \ drivers/serial_pinconfig.c \ drivers/serial_uart_pinconfig.c \ @@ -177,7 +176,6 @@ SIZE_OPTIMISED_SRC += \ STM32/serial_usb_vcp.c \ drivers/bus_i2c_config.c \ drivers/bus_spi_config.c \ - drivers/bus_spi_pinconfig.c \ drivers/serial_escserial.c \ drivers/serial_pinconfig.c \ drivers/serial_uart_pinconfig.c diff --git a/src/platform/STM32/mk/STM32H5.mk b/src/platform/STM32/mk/STM32H5.mk index ee80cde798..3aade083b1 100644 --- a/src/platform/STM32/mk/STM32H5.mk +++ b/src/platform/STM32/mk/STM32H5.mk @@ -176,7 +176,6 @@ MCU_COMMON_SRC = \ drivers/adc.c \ drivers/bus_i2c_config.c \ drivers/bus_spi_config.c \ - drivers/bus_spi_pinconfig.c \ drivers/serial_escserial.c \ drivers/serial_pinconfig.c \ drivers/serial_uart_pinconfig.c \ @@ -211,7 +210,6 @@ SIZE_OPTIMISED_SRC += \ STM32/serial_usb_vcp.c \ drivers/bus_i2c_config.c \ drivers/bus_spi_config.c \ - drivers/bus_spi_pinconfig.c \ drivers/serial_escserial.c \ drivers/serial_pinconfig.c \ drivers/serial_uart_pinconfig.c diff --git a/src/platform/STM32/mk/STM32H7.mk b/src/platform/STM32/mk/STM32H7.mk index 29d2a67930..c8ba1550d3 100644 --- a/src/platform/STM32/mk/STM32H7.mk +++ b/src/platform/STM32/mk/STM32H7.mk @@ -300,7 +300,6 @@ MCU_COMMON_SRC = \ drivers/adc.c \ drivers/bus_i2c_config.c \ drivers/bus_spi_config.c \ - drivers/bus_spi_pinconfig.c \ drivers/serial_escserial.c \ drivers/serial_pinconfig.c \ drivers/serial_uart_pinconfig.c \ @@ -326,7 +325,6 @@ SIZE_OPTIMISED_SRC += \ STM32/serial_usb_vcp.c \ drivers/bus_i2c_config.c \ drivers/bus_spi_config.c \ - drivers/bus_spi_pinconfig.c \ drivers/serial_escserial.c \ drivers/serial_pinconfig.c \ drivers/serial_uart_pinconfig.c diff --git a/src/platform/STM32/mk/STM32_COMMON.mk b/src/platform/STM32/mk/STM32_COMMON.mk index f109837f3a..24950c9e5f 100644 --- a/src/platform/STM32/mk/STM32_COMMON.mk +++ b/src/platform/STM32/mk/STM32_COMMON.mk @@ -1,2 +1,12 @@ INCLUDE_DIRS += $(PLATFORM_DIR)/common/stm32 + +MCU_COMMON_SRC += \ + common/stm32/bus_spi_pinconfig.c \ + common/stm32/bus_spi_hw.c \ + +SIZE_OPTIMISED_SRC += \ + common/stm32/bus_spi_pinconfig.c + +SPEED_OPTIMISED_SRC += \ + common/stm32/bus_spi_hw.c diff --git a/src/platform/STM32/platform_mcu.h b/src/platform/STM32/platform_mcu.h index e903cb1153..a620f27932 100644 --- a/src/platform/STM32/platform_mcu.h +++ b/src/platform/STM32/platform_mcu.h @@ -301,3 +301,53 @@ extern uint8_t _dmaram_end__; #define IO_CONFIG_GET_PULL(cfg) (((cfg) >> 5) & 0x03) #endif + +#if defined(STM32F4) +#define SPI_IO_AF_CFG IO_CONFIG(GPIO_Mode_AF, GPIO_Speed_50MHz, GPIO_OType_PP, GPIO_PuPd_NOPULL) +#define SPI_IO_AF_SCK_CFG IO_CONFIG(GPIO_Mode_AF, GPIO_Speed_50MHz, GPIO_OType_PP, GPIO_PuPd_DOWN) +#define SPI_IO_AF_SDI_CFG IO_CONFIG(GPIO_Mode_AF, GPIO_Speed_50MHz, GPIO_OType_PP, GPIO_PuPd_UP) +#define SPI_IO_CS_CFG IO_CONFIG(GPIO_Mode_OUT, GPIO_Speed_50MHz, GPIO_OType_PP, GPIO_PuPd_NOPULL) +#define SPI_IO_CS_HIGH_CFG IO_CONFIG(GPIO_Mode_IN, GPIO_Speed_50MHz, GPIO_OType_PP, GPIO_PuPd_UP) +#elif defined(STM32F7) || defined(STM32H7) || defined(STM32G4) +#define SPI_IO_AF_CFG IO_CONFIG(GPIO_MODE_AF_PP, GPIO_SPEED_FREQ_VERY_HIGH, GPIO_NOPULL) +#define SPI_IO_AF_SCK_CFG_HIGH IO_CONFIG(GPIO_MODE_AF_PP, GPIO_SPEED_FREQ_VERY_HIGH, GPIO_PULLUP) +#define SPI_IO_AF_SCK_CFG_LOW IO_CONFIG(GPIO_MODE_AF_PP, GPIO_SPEED_FREQ_VERY_HIGH, GPIO_PULLDOWN) +#define SPI_IO_AF_SDI_CFG IO_CONFIG(GPIO_MODE_AF_PP, GPIO_SPEED_FREQ_VERY_HIGH, GPIO_PULLUP) +#define SPI_IO_CS_CFG IO_CONFIG(GPIO_MODE_OUTPUT_PP, GPIO_SPEED_FREQ_VERY_HIGH, GPIO_NOPULL) +#define SPI_IO_CS_HIGH_CFG IO_CONFIG(GPIO_MODE_INPUT, GPIO_SPEED_FREQ_VERY_HIGH, GPIO_PULLUP) +#else +#error "Invalid STM MCU defined - requires SPI implementation" +#endif + +#if defined(STM32F4) +#define SPIDEV_COUNT 3 +#elif defined(STM32F7) +#define SPIDEV_COUNT 4 +#elif defined(STM32H7) +#define SPIDEV_COUNT 6 +#else +#define SPIDEV_COUNT 4 +#endif + +// Work around different check routines in the libraries for different MCU types +#if defined(STM32H7) +#define CHECK_SPI_RX_DATA_AVAILABLE(instance) LL_SPI_IsActiveFlag_RXWNE(instance) +#define SPI_RX_DATA_REGISTER(base) ((base)->RXDR) +#else +#define CHECK_SPI_RX_DATA_AVAILABLE(instance) LL_SPI_IsActiveFlag_RXNE(instance) +#define SPI_RX_DATA_REGISTER(base) ((base)->DR) +#endif + +#if defined(STM32F4) || defined(STM32G4) +#define MAX_SPI_PIN_SEL 2 +#elif defined(STM32F7) +#define MAX_SPI_PIN_SEL 4 +#elif defined(STM32H7) +#define MAX_SPI_PIN_SEL 5 +#else +#error Unknown MCU family +#endif + +#if !defined(STM32G4) && !defined(STM32H7) +#define USE_TX_IRQ_HANDLER +#endif diff --git a/src/platform/common/stm32/bus_spi_hw.c b/src/platform/common/stm32/bus_spi_hw.c new file mode 100644 index 0000000000..b0befd8c34 --- /dev/null +++ b/src/platform/common/stm32/bus_spi_hw.c @@ -0,0 +1,354 @@ +/* + * This file is part of Betaflight. + * + * Betaflight is free software. You can redistribute this software + * and/or modify this software under the terms of the GNU General + * Public License as published by the Free Software Foundation, + * either version 3 of the License, or (at your option) any later + * version. + * + * Betaflight is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * See the GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this software. + * + * If not, see . + */ + +#include +#include + +#include "platform.h" + +#include "build/atomic.h" + +#ifdef USE_SPI + +#include "drivers/bus.h" +#include "drivers/bus_spi.h" +#include "drivers/bus_spi_impl.h" +#include "drivers/dma_reqmap.h" +#include "drivers/motor.h" +#include "drivers/nvic.h" +#include "pg/bus_spi.h" + +extern spiDevice_t spiDevice[SPIDEV_COUNT]; +extern busDevice_t spiBusDevice[SPIDEV_COUNT]; + +// Interrupt handler for SPI receive DMA completion +FAST_IRQ_HANDLER static void spiIrqHandler(const extDevice_t *dev) +{ + busDevice_t *bus = dev->bus; + busSegment_t *nextSegment; + + if (bus->curSegment->callback) { + switch(bus->curSegment->callback(dev->callbackArg)) { + case BUS_BUSY: + // Repeat the last DMA segment + bus->curSegment--; + // Reinitialise the cached init values as segment is not progressing + spiInternalInitStream(dev, true); + break; + + case BUS_ABORT: + // Skip to the end of the segment list + nextSegment = (busSegment_t *)bus->curSegment + 1; + while (nextSegment->len != 0) { + bus->curSegment = nextSegment; + nextSegment = (busSegment_t *)bus->curSegment + 1; + } + break; + + case BUS_READY: + default: + // Advance to the next DMA segment + break; + } + } + + // Advance through the segment list + // OK to discard the volatile qualifier here + nextSegment = (busSegment_t *)bus->curSegment + 1; + + if (nextSegment->len == 0) { + // If a following transaction has been linked, start it + if (nextSegment->u.link.dev) { + const extDevice_t *nextDev = nextSegment->u.link.dev; + busSegment_t *nextSegments = (busSegment_t *)nextSegment->u.link.segments; + // The end of the segment list has been reached + bus->curSegment = nextSegments; + nextSegment->u.link.dev = NULL; + nextSegment->u.link.segments = NULL; + spiSequenceStart(nextDev); + } else { + // The end of the segment list has been reached, so mark transactions as complete + bus->curSegment = (busSegment_t *)BUS_SPI_FREE; + } + } else { + // Do as much processing as possible before asserting CS to avoid violating minimum high time + bool negateCS = bus->curSegment->negateCS; + + bus->curSegment = nextSegment; + + // After the completion of the first segment setup the init structure for the subsequent segment + if (bus->initSegment) { + spiInternalInitStream(dev, false); + bus->initSegment = false; + } + + if (negateCS) { + // Assert Chip Select - it's costly so only do so if necessary + IOLo(dev->busType_u.spi.csnPin); + } + + // Launch the next transfer + spiInternalStartDMA(dev); + + // Prepare the init structures ready for the next segment to reduce inter-segment time + spiInternalInitStream(dev, true); + } +} + +// Interrupt handler for SPI receive DMA completion +FAST_IRQ_HANDLER static void spiRxIrqHandler(dmaChannelDescriptor_t* descriptor) +{ + const extDevice_t *dev = (const extDevice_t *)descriptor->userParam; + + if (!dev) { + return; + } + + busDevice_t *bus = dev->bus; + + if (bus->curSegment->negateCS) { + // Negate Chip Select + IOHi(dev->busType_u.spi.csnPin); + } + + spiInternalStopDMA(dev); + +#ifdef __DCACHE_PRESENT +#ifdef STM32H7 + if (bus->curSegment->u.buffers.rxData && + ((bus->curSegment->u.buffers.rxData < &_dmaram_start__) || (bus->curSegment->u.buffers.rxData >= &_dmaram_end__))) { +#else + if (bus->curSegment->u.buffers.rxData) { +#endif + // Invalidate the D cache covering the area into which data has been read + SCB_InvalidateDCache_by_Addr( + (uint32_t *)((uint32_t)bus->curSegment->u.buffers.rxData & ~CACHE_LINE_MASK), + (((uint32_t)bus->curSegment->u.buffers.rxData & CACHE_LINE_MASK) + + bus->curSegment->len - 1 + CACHE_LINE_SIZE) & ~CACHE_LINE_MASK); + } +#endif // __DCACHE_PRESENT + + spiIrqHandler(dev); +} + +#ifdef USE_TX_IRQ_HANDLER +// Interrupt handler for SPI transmit DMA completion +FAST_IRQ_HANDLER static void spiTxIrqHandler(dmaChannelDescriptor_t* descriptor) +{ + const extDevice_t *dev = (const extDevice_t *)descriptor->userParam; + + if (!dev) { + return; + } + + busDevice_t *bus = dev->bus; + + spiInternalStopDMA(dev); + + if (bus->curSegment->negateCS) { + // Negate Chip Select + IOHi(dev->busType_u.spi.csnPin); + } + + spiIrqHandler(dev); +} +#endif + +uint16_t spiCalculateDivider(uint32_t freq) +{ +#if defined(STM32F4) || defined(STM32G4) || defined(STM32F7) || defined(APM32F4) + uint32_t spiClk = SystemCoreClock / 2; +#elif defined(STM32H7) + uint32_t spiClk = 100000000; +#elif defined(AT32F4) + if(freq > 36000000){ + freq = 36000000; + } + + uint32_t spiClk = system_core_clock / 2; +#else +#error "Base SPI clock not defined for this architecture" +#endif + + uint16_t divisor = 2; + + spiClk >>= 1; + + for (; (spiClk > freq) && (divisor < 256); divisor <<= 1, spiClk >>= 1); + + return divisor; +} + +uint32_t spiCalculateClock(uint16_t spiClkDivisor) +{ +#if defined(STM32F4) || defined(STM32G4) || defined(STM32F7) || defined(APM32F4) + uint32_t spiClk = SystemCoreClock / 2; +#elif defined(STM32H7) + uint32_t spiClk = 100000000; +#elif defined(AT32F4) + uint32_t spiClk = system_core_clock / 2; + + if ((spiClk / spiClkDivisor) > 36000000){ + return 36000000; + } +#else +#error "Base SPI clock not defined for this architecture" +#endif + + return spiClk / spiClkDivisor; +} + +void spiInitBusDMA(void) +{ + uint32_t device; +#if (defined(STM32F4) || defined(APM32F4)) && defined(USE_DSHOT_BITBANG) + /* Check https://www.st.com/resource/en/errata_sheet/dm00037591-stm32f405407xx-and-stm32f415417xx-device-limitations-stmicroelectronics.pdf + * section 2.1.10 which reports an errata that corruption may occurs on DMA2 if AHB peripherals (eg GPIO ports) are + * access concurrently with APB peripherals (eg SPI busses). Bitbang DSHOT uses DMA2 to write to GPIO ports. If this + * is enabled, then don't enable DMA on an SPI bus using DMA2 + */ + const bool dshotBitbangActive = isDshotBitbangActive(&motorConfig()->dev); +#endif + + for (device = 0; device < SPIDEV_COUNT; device++) { + busDevice_t *bus = &spiBusDevice[device]; + + if (bus->busType != BUS_TYPE_SPI) { + // This bus is not in use + continue; + } + + dmaIdentifier_e dmaTxIdentifier = DMA_NONE; + dmaIdentifier_e dmaRxIdentifier = DMA_NONE; + + int8_t txDmaopt = spiPinConfig(device)->txDmaopt; + uint8_t txDmaoptMin = 0; + uint8_t txDmaoptMax = MAX_PERIPHERAL_DMA_OPTIONS - 1; + + if (txDmaopt != -1) { + txDmaoptMin = txDmaopt; + txDmaoptMax = txDmaopt; + } + + for (uint8_t opt = txDmaoptMin; opt <= txDmaoptMax; opt++) { + const dmaChannelSpec_t *dmaTxChannelSpec = dmaGetChannelSpecByPeripheral(DMA_PERIPH_SPI_SDO, device, opt); + + if (dmaTxChannelSpec) { + dmaTxIdentifier = dmaGetIdentifier(dmaTxChannelSpec->ref); +#if (defined(STM32F4) || defined(APM32F4)) && defined(USE_DSHOT_BITBANG) + if (dshotBitbangActive && (DMA_DEVICE_NO(dmaTxIdentifier) == 2)) { + dmaTxIdentifier = DMA_NONE; + break; + } +#endif + if (!dmaAllocate(dmaTxIdentifier, OWNER_SPI_SDO, device + 1)) { + dmaTxIdentifier = DMA_NONE; + continue; + } + bus->dmaTx = dmaGetDescriptorByIdentifier(dmaTxIdentifier); +#if defined(STM32F4) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) || defined(APM32F4) + bus->dmaTx->stream = DMA_DEVICE_INDEX(dmaTxIdentifier); + bus->dmaTx->channel = dmaTxChannelSpec->channel; +#endif + + dmaEnable(dmaTxIdentifier); +#if defined(USE_ATBSP_DRIVER) + dmaMuxEnable(dmaTxIdentifier,dmaTxChannelSpec->dmaMuxId); +#endif + break; + } + } + + int8_t rxDmaopt = spiPinConfig(device)->rxDmaopt; + uint8_t rxDmaoptMin = 0; + uint8_t rxDmaoptMax = MAX_PERIPHERAL_DMA_OPTIONS - 1; + + if (rxDmaopt != -1) { + rxDmaoptMin = rxDmaopt; + rxDmaoptMax = rxDmaopt; + } + + for (uint8_t opt = rxDmaoptMin; opt <= rxDmaoptMax; opt++) { + const dmaChannelSpec_t *dmaRxChannelSpec = dmaGetChannelSpecByPeripheral(DMA_PERIPH_SPI_SDI, device, opt); + + if (dmaRxChannelSpec) { + dmaRxIdentifier = dmaGetIdentifier(dmaRxChannelSpec->ref); +#if (defined(STM32F4) || defined(APM32F4)) && defined(USE_DSHOT_BITBANG) + if (dshotBitbangActive && (DMA_DEVICE_NO(dmaRxIdentifier) == 2)) { + dmaRxIdentifier = DMA_NONE; + break; + } +#endif + if (!dmaAllocate(dmaRxIdentifier, OWNER_SPI_SDI, device + 1)) { + dmaRxIdentifier = DMA_NONE; + continue; + } + bus->dmaRx = dmaGetDescriptorByIdentifier(dmaRxIdentifier); +#if defined(STM32F4) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) || defined(APM32F4) + bus->dmaRx->stream = DMA_DEVICE_INDEX(dmaRxIdentifier); + bus->dmaRx->channel = dmaRxChannelSpec->channel; +#endif + + dmaEnable(dmaRxIdentifier); +#if defined(USE_ATBSP_DRIVER) + dmaMuxEnable(dmaRxIdentifier,dmaRxChannelSpec->dmaMuxId); +#endif + break; + } + } + + if (dmaTxIdentifier && dmaRxIdentifier) { + // Ensure streams are disabled + spiInternalResetStream(bus->dmaRx); + spiInternalResetStream(bus->dmaTx); + + spiInternalResetDescriptors(bus); + + /* Note that this driver may be called both from the normal thread of execution, or from USB interrupt + * handlers, so the DMA completion interrupt must be at a higher priority + */ + dmaSetHandler(dmaRxIdentifier, spiRxIrqHandler, NVIC_PRIO_SPI_DMA, 0); + + bus->useDMA = true; +#ifdef USE_TX_IRQ_HANDLER + } else if (dmaTxIdentifier) { + // Transmit on DMA is adequate for OSD so worth having + bus->dmaTx = dmaGetDescriptorByIdentifier(dmaTxIdentifier); + bus->dmaRx = (dmaChannelDescriptor_t *)NULL; + + // Ensure streams are disabled + spiInternalResetStream(bus->dmaTx); + + spiInternalResetDescriptors(bus); + + dmaSetHandler(dmaTxIdentifier, spiTxIrqHandler, NVIC_PRIO_SPI_DMA, 0); + + bus->useDMA = true; +#endif + } else { + // Disassociate channels from bus + bus->dmaRx = (dmaChannelDescriptor_t *)NULL; + bus->dmaTx = (dmaChannelDescriptor_t *)NULL; + } + } +} + +#endif diff --git a/src/main/drivers/bus_spi_pinconfig.c b/src/platform/common/stm32/bus_spi_pinconfig.c similarity index 100% rename from src/main/drivers/bus_spi_pinconfig.c rename to src/platform/common/stm32/bus_spi_pinconfig.c diff --git a/src/test/unit/platform.h b/src/test/unit/platform.h index f5b7c63a56..d7d5eb505e 100644 --- a/src/test/unit/platform.h +++ b/src/test/unit/platform.h @@ -123,6 +123,7 @@ typedef struct void* test; } ADC_TypeDef; +#define SPIDEV_COUNT 0 #define WS2811_DMA_TC_FLAG (void *)1 #define WS2811_DMA_HANDLER_IDENTIFER 0 #define NVIC_PriorityGroup_2 0x500 From d82cd5a28ab5c68f6aaf72119a160ab779c7e768 Mon Sep 17 00:00:00 2001 From: Jay Blackman Date: Mon, 6 Jan 2025 04:51:45 +1100 Subject: [PATCH 025/244] Move STM (and clone) specific IO initialisation to platform (#14123) * Move stm (and clone) specific io initialisation to platform * Removed unused includes and implemented get by tag for SITL * Update sitl.c Corrected return value * Update io_impl.c Corrected licence file --- src/main/drivers/io.c | 44 ----------------- src/platform/APM32/mk/APM32F4.mk | 1 + src/platform/AT32/mk/AT32F4.mk | 1 + src/platform/SIMULATOR/sitl.c | 11 +++++ src/platform/STM32/mk/STM32_COMMON.mk | 5 +- src/platform/common/stm32/io_impl.c | 70 +++++++++++++++++++++++++++ 6 files changed, 87 insertions(+), 45 deletions(-) create mode 100644 src/platform/common/stm32/io_impl.c diff --git a/src/main/drivers/io.c b/src/main/drivers/io.c index bd11be4de1..66c82aa2ba 100644 --- a/src/main/drivers/io.c +++ b/src/main/drivers/io.c @@ -129,14 +129,6 @@ bool IOIsFreeOrPreinit(IO_t io) return false; } -#if DEFIO_PORT_USED_COUNT > 0 -static const uint16_t ioDefUsedMask[DEFIO_PORT_USED_COUNT] = { DEFIO_PORT_USED_LIST }; -static const uint8_t ioDefUsedOffset[DEFIO_PORT_USED_COUNT] = { DEFIO_PORT_OFFSET_LIST }; -#else -// Avoid -Wpedantic warning -static const uint16_t ioDefUsedMask[1] = {0}; -static const uint8_t ioDefUsedOffset[1] = {0}; -#endif #if DEFIO_IO_USED_COUNT ioRec_t ioRecs[DEFIO_IO_USED_COUNT]; #else @@ -144,42 +136,6 @@ ioRec_t ioRecs[DEFIO_IO_USED_COUNT]; ioRec_t ioRecs[1]; #endif -// initialize all ioRec_t structures from ROM -// currently only bitmask is used, this may change in future -void IOInitGlobal(void) -{ - ioRec_t *ioRec = ioRecs; - - for (unsigned port = 0; port < ARRAYLEN(ioDefUsedMask); port++) { - for (unsigned pin = 0; pin < sizeof(ioDefUsedMask[0]) * 8; pin++) { - if (ioDefUsedMask[port] & (1 << pin)) { - ioRec->gpio = (GPIO_TypeDef *)(GPIOA_BASE + (port << 10)); // ports are 0x400 apart - ioRec->pin = 1 << pin; - ioRec++; - } - } - } -} - -IO_t IOGetByTag(ioTag_t tag) -{ - const int portIdx = DEFIO_TAG_GPIOID(tag); - const int pinIdx = DEFIO_TAG_PIN(tag); - - if (portIdx < 0 || portIdx >= DEFIO_PORT_USED_COUNT) { - return NULL; - } - // check if pin exists - if (!(ioDefUsedMask[portIdx] & (1 << pinIdx))) { - return NULL; - } - // count bits before this pin on single port - int offset = popcount(((1 << pinIdx) - 1) & ioDefUsedMask[portIdx]); - // and add port offset - offset += ioDefUsedOffset[portIdx]; - return ioRecs + offset; -} - void IOTraversePins(IOTraverseFuncPtr_t fnPtr) { for (int i = 0; i < DEFIO_IO_USED_COUNT; i++) { diff --git a/src/platform/APM32/mk/APM32F4.mk b/src/platform/APM32/mk/APM32F4.mk index c222e67ec0..9ea1025baf 100644 --- a/src/platform/APM32/mk/APM32F4.mk +++ b/src/platform/APM32/mk/APM32F4.mk @@ -147,6 +147,7 @@ endif MCU_COMMON_SRC = \ common/stm32/system.c \ + common/stm32/io_impl.c \ APM32/startup/system_apm32f4xx.c \ drivers/inverter.c \ drivers/dshot_bitbang_decode.c \ diff --git a/src/platform/AT32/mk/AT32F4.mk b/src/platform/AT32/mk/AT32F4.mk index 3053712fdd..cc5f9955f1 100644 --- a/src/platform/AT32/mk/AT32F4.mk +++ b/src/platform/AT32/mk/AT32F4.mk @@ -82,6 +82,7 @@ DEVICE_FLAGS += -DUSE_ATBSP_DRIVER -DAT32F43x -DHSE_VALUE=$(HSE_VALUE) -DAT32 MCU_COMMON_SRC = \ common/stm32/system.c \ + common/stm32/io_impl.c \ AT32/startup/at32f435_437_clock.c \ AT32/startup/system_at32f435_437.c \ AT32/adc_at32f43x.c \ diff --git a/src/platform/SIMULATOR/sitl.c b/src/platform/SIMULATOR/sitl.c index f53482f8f6..c96c268fed 100644 --- a/src/platform/SIMULATOR/sitl.c +++ b/src/platform/SIMULATOR/sitl.c @@ -757,3 +757,14 @@ void IOLo(IO_t io) { UNUSED(io); } + +void IOInitGlobal(void) +{ + // NOOP +} + +IO_t IOGetByTag(ioTag_t tag) +{ + UNUSED(tag); + return NULL; +} diff --git a/src/platform/STM32/mk/STM32_COMMON.mk b/src/platform/STM32/mk/STM32_COMMON.mk index 24950c9e5f..1e45a60ae2 100644 --- a/src/platform/STM32/mk/STM32_COMMON.mk +++ b/src/platform/STM32/mk/STM32_COMMON.mk @@ -4,9 +4,12 @@ INCLUDE_DIRS += $(PLATFORM_DIR)/common/stm32 MCU_COMMON_SRC += \ common/stm32/bus_spi_pinconfig.c \ common/stm32/bus_spi_hw.c \ + common/stm32/io_impl.c SIZE_OPTIMISED_SRC += \ common/stm32/bus_spi_pinconfig.c SPEED_OPTIMISED_SRC += \ - common/stm32/bus_spi_hw.c + common/stm32/bus_spi_hw.c \ + common/stm32/io_impl.c + diff --git a/src/platform/common/stm32/io_impl.c b/src/platform/common/stm32/io_impl.c new file mode 100644 index 0000000000..da511e06d7 --- /dev/null +++ b/src/platform/common/stm32/io_impl.c @@ -0,0 +1,70 @@ +/* + * This file is part of Betaflight. + * + * Betaflight is free software. You can redistribute this software + * and/or modify this software under the terms of the GNU General + * Public License as published by the Free Software Foundation, + * either version 3 of the License, or (at your option) any later + * version. + * + * Betaflight is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * See the GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this software. + * + * If not, see . + */ + +#include "platform.h" + +#include "drivers/io.h" +#include "drivers/io_impl.h" + +#if DEFIO_PORT_USED_COUNT > 0 +static const uint16_t ioDefUsedMask[DEFIO_PORT_USED_COUNT] = { DEFIO_PORT_USED_LIST }; +static const uint8_t ioDefUsedOffset[DEFIO_PORT_USED_COUNT] = { DEFIO_PORT_OFFSET_LIST }; +#else +// Avoid -Wpedantic warning +static const uint16_t ioDefUsedMask[1] = {0}; +static const uint8_t ioDefUsedOffset[1] = {0}; +#endif + +// initialize all ioRec_t structures from ROM +// currently only bitmask is used, this may change in future +void IOInitGlobal(void) +{ + ioRec_t *ioRec = ioRecs; + + for (unsigned port = 0; port < ARRAYLEN(ioDefUsedMask); port++) { + for (unsigned pin = 0; pin < sizeof(ioDefUsedMask[0]) * 8; pin++) { + if (ioDefUsedMask[port] & (1 << pin)) { + ioRec->gpio = (GPIO_TypeDef *)(GPIOA_BASE + (port << 10)); // ports are 0x400 apart + ioRec->pin = 1 << pin; + ioRec++; + } + } + } +} + +IO_t IOGetByTag(ioTag_t tag) +{ + const int portIdx = DEFIO_TAG_GPIOID(tag); + const int pinIdx = DEFIO_TAG_PIN(tag); + + if (portIdx < 0 || portIdx >= DEFIO_PORT_USED_COUNT) { + return NULL; + } + // check if pin exists + if (!(ioDefUsedMask[portIdx] & (1 << pinIdx))) { + return NULL; + } + // count bits before this pin on single port + int offset = popcount(((1 << pinIdx) - 1) & ioDefUsedMask[portIdx]); + // and add port offset + offset += ioDefUsedOffset[portIdx]; + return ioRecs + offset; +} From 69f8f71b7761612a86f33cde5aa77f956eebb16c Mon Sep 17 00:00:00 2001 From: Jay Blackman Date: Mon, 6 Jan 2025 06:01:00 +1100 Subject: [PATCH 026/244] Moved IO_GPIOPortIdx to platform (#14127) --- src/main/drivers/io.c | 8 -------- src/platform/common/stm32/io_impl.c | 8 ++++++++ 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/src/main/drivers/io.c b/src/main/drivers/io.c index 66c82aa2ba..fcd8cb4c79 100644 --- a/src/main/drivers/io.c +++ b/src/main/drivers/io.c @@ -52,14 +52,6 @@ uint16_t IO_Pin(IO_t io) return ioRec->pin; } -int IO_GPIOPortIdx(IO_t io) -{ - if (!io) { - return -1; - } - return (((size_t)IO_GPIO(io) - GPIOA_BASE) >> 10); -} - int IO_EXTI_PortSourceGPIO(IO_t io) { return IO_GPIOPortIdx(io); diff --git a/src/platform/common/stm32/io_impl.c b/src/platform/common/stm32/io_impl.c index da511e06d7..c2a98ad40f 100644 --- a/src/platform/common/stm32/io_impl.c +++ b/src/platform/common/stm32/io_impl.c @@ -68,3 +68,11 @@ IO_t IOGetByTag(ioTag_t tag) offset += ioDefUsedOffset[portIdx]; return ioRecs + offset; } + +int IO_GPIOPortIdx(IO_t io) +{ + if (!io) { + return -1; + } + return (((size_t)IO_GPIO(io) - GPIOA_BASE) >> 10); +} From 02432af6fa855ca39f27419fb8524ca21ea0a5ad Mon Sep 17 00:00:00 2001 From: Jay Blackman Date: Mon, 6 Jan 2025 19:36:24 +1100 Subject: [PATCH 027/244] Move STM (and clone) related config in flash implementation to platform (#14103) --- src/main/config/config_eeprom.c | 16 +- src/main/config/config_eeprom_impl.h | 25 + src/main/config/config_streamer.c | 486 ++------------------ src/main/config/config_streamer.h | 62 ++- src/main/config/config_streamer_impl.h | 29 ++ src/main/drivers/system.h | 2 + src/platform/APM32/mk/APM32F4.mk | 4 +- src/platform/APM32/platform_mcu.h | 4 + src/platform/AT32/mk/AT32F4.mk | 1 + src/platform/AT32/platform_mcu.h | 2 + src/platform/SIMULATOR/sitl.c | 43 +- src/platform/SIMULATOR/target/SITL/target.h | 14 - src/platform/STM32/mk/STM32F4.mk | 1 + src/platform/STM32/mk/STM32F7.mk | 2 - src/platform/STM32/mk/STM32G4.mk | 2 - src/platform/STM32/mk/STM32H5.mk | 2 - src/platform/STM32/mk/STM32H7.mk | 2 - src/platform/STM32/mk/STM32_COMMON.mk | 4 + src/platform/STM32/platform_mcu.h | 12 + src/platform/common/stm32/config_flash.c | 475 +++++++++++++++++++ 20 files changed, 653 insertions(+), 535 deletions(-) create mode 100644 src/main/config/config_eeprom_impl.h create mode 100644 src/main/config/config_streamer_impl.h create mode 100644 src/platform/common/stm32/config_flash.c diff --git a/src/main/config/config_eeprom.c b/src/main/config/config_eeprom.c index f77586d3d8..83e2d79fa2 100644 --- a/src/main/config/config_eeprom.c +++ b/src/main/config/config_eeprom.c @@ -30,7 +30,10 @@ #include "common/utils.h" #include "config/config_eeprom.h" +#include "config/config_eeprom_impl.h" #include "config/config_streamer.h" +#include "config/config_streamer_impl.h" + #include "pg/pg.h" #include "config/config.h" @@ -283,13 +286,6 @@ bool loadEEPROMFromSDCard(void) } #endif -#ifdef CONFIG_IN_FILE -void loadEEPROMFromFile(void) -{ - FLASH_Unlock(); // load existing config file into eepromData -} -#endif - void initEEPROM(void) { // Verify that this architecture packs as expected. @@ -301,7 +297,11 @@ void initEEPROM(void) STATIC_ASSERT(sizeof(configRecord_t) == 6, record_size_failed); #if defined(CONFIG_IN_FILE) - loadEEPROMFromFile(); + bool eepromLoaded = loadEEPROMFromFile(); + if (!eepromLoaded) { + // File read failed - just die now + failureMode(FAILURE_FILE_READ_FAILED); + } #elif defined(CONFIG_IN_EXTERNAL_FLASH) || defined(CONFIG_IN_MEMORY_MAPPED_FLASH) bool eepromLoaded = loadEEPROMFromExternalFlash(); if (!eepromLoaded) { diff --git a/src/main/config/config_eeprom_impl.h b/src/main/config/config_eeprom_impl.h new file mode 100644 index 0000000000..40ec540bfe --- /dev/null +++ b/src/main/config/config_eeprom_impl.h @@ -0,0 +1,25 @@ +/* + * This file is part of Betaflight. + * + * Betaflight is free software. You can redistribute this software + * and/or modify this software under the terms of the GNU General + * Public License as published by the Free Software Foundation, + * either version 3 of the License, or (at your option) any later + * version. + * + * Betaflight is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * See the GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this software. + * + * If not, see . + */ + +#pragma once + +// TODO: potentially move sdcard and external flash also +bool loadEEPROMFromFile(void); diff --git a/src/main/config/config_streamer.c b/src/main/config/config_streamer.c index fc5ab25696..d519d61b42 100644 --- a/src/main/config/config_streamer.c +++ b/src/main/config/config_streamer.c @@ -27,6 +27,7 @@ #include "config/config_eeprom.h" #include "config/config_streamer.h" +#include "config/config_streamer_impl.h" #if !defined(CONFIG_IN_FLASH) #if defined(CONFIG_IN_RAM) && defined(PERSISTENT) @@ -45,7 +46,7 @@ void config_streamer_init(config_streamer_t *c) memset(c, 0, sizeof(*c)); } -void config_streamer_start(config_streamer_t *c, uintptr_t base, int size) +void config_streamer_start(config_streamer_t *c, uintptr_t base, size_t size) { // base must start at FLASH_PAGE_SIZE boundary when using embedded flash. c->address = base; @@ -53,16 +54,8 @@ void config_streamer_start(config_streamer_t *c, uintptr_t base, int size) if (!c->unlocked) { #if defined(CONFIG_IN_RAM) || defined(CONFIG_IN_EXTERNAL_FLASH) || defined(CONFIG_IN_SDCARD) // NOP -#elif defined(CONFIG_IN_FLASH) || defined(CONFIG_IN_FILE) -#if defined(STM32F7) || defined(STM32H7) || defined(STM32G4) - HAL_FLASH_Unlock(); -#elif defined(APM32F4) - DAL_FLASH_Unlock(); -#elif defined(AT32F4) - flash_unlock(); -#else - FLASH_Unlock(); -#endif +#elif defined(CONFIG_IN_FILE) || defined(CONFIG_IN_FLASH) + configUnlock(); #endif c->unlocked = true; } @@ -70,314 +63,20 @@ void config_streamer_start(config_streamer_t *c, uintptr_t base, int size) #if defined(CONFIG_IN_RAM) || defined(CONFIG_IN_FILE) || defined(CONFIG_IN_EXTERNAL_FLASH) // NOP #elif defined(CONFIG_IN_FLASH) -#if defined(STM32F4) - FLASH_ClearFlag(FLASH_FLAG_EOP | FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | FLASH_FLAG_PGPERR | FLASH_FLAG_PGSERR); -#elif defined(STM32F7) - // NOP -#elif defined(STM32H7) - // NOP -#elif defined(STM32G4) - // NOP -#elif defined(AT32F4) - flash_flag_clear(FLASH_ODF_FLAG | FLASH_PRGMERR_FLAG | FLASH_EPPERR_FLAG); -#elif defined(APM32F4) - __DAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | FLASH_FLAG_PGPERR | FLASH_FLAG_PGSERR); -#elif defined(UNIT_TEST) || defined(SIMULATOR_BUILD) - // NOP -#else -# error "Unsupported CPU" + configClearFlags(); #endif -#endif - c->err = 0; + c->err = CONFIG_RESULT_SUCCESS; } #if defined(CONFIG_IN_RAM) || defined(CONFIG_IN_EXTERNAL_FLASH) || defined(CONFIG_IN_SDCARD) // No flash sector method required. #elif defined(CONFIG_IN_FLASH) -#if defined(STM32F745xx) || defined(STM32F746xx) || defined(STM32F765xx) -/* -Sector 0 0x08000000 - 0x08007FFF 32 Kbytes -Sector 1 0x08008000 - 0x0800FFFF 32 Kbytes -Sector 2 0x08010000 - 0x08017FFF 32 Kbytes -Sector 3 0x08018000 - 0x0801FFFF 32 Kbytes -Sector 4 0x08020000 - 0x0803FFFF 128 Kbytes -Sector 5 0x08040000 - 0x0807FFFF 256 Kbytes -Sector 6 0x08080000 - 0x080BFFFF 256 Kbytes -Sector 7 0x080C0000 - 0x080FFFFF 256 Kbytes - -F7X5XI device with 2M flash -Sector 8 0x08100000 - 0x0813FFFF 256 Kbytes -Sector 9 0x08140000 - 0x0817FFFF 256 Kbytes -Sector 10 0x08180000 - 0x081BFFFF 256 Kbytes -Sector 11 0x081C0000 - 0x081FFFFF 256 Kbytes -*/ - -static uint32_t getFLASHSectorForEEPROM(void) -{ - if ((uint32_t)&__config_start <= 0x08007FFF) - return FLASH_SECTOR_0; - if ((uint32_t)&__config_start <= 0x0800FFFF) - return FLASH_SECTOR_1; - if ((uint32_t)&__config_start <= 0x08017FFF) - return FLASH_SECTOR_2; - if ((uint32_t)&__config_start <= 0x0801FFFF) - return FLASH_SECTOR_3; - if ((uint32_t)&__config_start <= 0x0803FFFF) - return FLASH_SECTOR_4; - if ((uint32_t)&__config_start <= 0x0807FFFF) - return FLASH_SECTOR_5; - if ((uint32_t)&__config_start <= 0x080BFFFF) - return FLASH_SECTOR_6; - if ((uint32_t)&__config_start <= 0x080FFFFF) - return FLASH_SECTOR_7; -#if defined(STM32F765xx) - if ((uint32_t)&__config_start <= 0x0813FFFF) - return FLASH_SECTOR_8; - if ((uint32_t)&__config_start <= 0x0817FFFF) - return FLASH_SECTOR_9; - if ((uint32_t)&__config_start <= 0x081BFFFF) - return FLASH_SECTOR_10; - if ((uint32_t)&__config_start <= 0x081FFFFF) - return FLASH_SECTOR_11; +uint32_t getFLASHSectorForEEPROM(void); #endif - // Not good - while (1) { - failureMode(FAILURE_CONFIG_STORE_FAILURE); - } -} - -#elif defined(STM32F722xx) -/* -Sector 0 0x08000000 - 0x08003FFF 16 Kbytes -Sector 1 0x08004000 - 0x08007FFF 16 Kbytes -Sector 2 0x08008000 - 0x0800BFFF 16 Kbytes -Sector 3 0x0800C000 - 0x0800FFFF 16 Kbytes -Sector 4 0x08010000 - 0x0801FFFF 64 Kbytes -Sector 5 0x08020000 - 0x0803FFFF 128 Kbytes -Sector 6 0x08040000 - 0x0805FFFF 128 Kbytes -Sector 7 0x08060000 - 0x0807FFFF 128 Kbytes -*/ - -static uint32_t getFLASHSectorForEEPROM(void) +static int write_word(config_streamer_t *c, config_streamer_buffer_type_t *buffer) { - if ((uint32_t)&__config_start <= 0x08003FFF) - return FLASH_SECTOR_0; - if ((uint32_t)&__config_start <= 0x08007FFF) - return FLASH_SECTOR_1; - if ((uint32_t)&__config_start <= 0x0800BFFF) - return FLASH_SECTOR_2; - if ((uint32_t)&__config_start <= 0x0800FFFF) - return FLASH_SECTOR_3; - if ((uint32_t)&__config_start <= 0x0801FFFF) - return FLASH_SECTOR_4; - if ((uint32_t)&__config_start <= 0x0803FFFF) - return FLASH_SECTOR_5; - if ((uint32_t)&__config_start <= 0x0805FFFF) - return FLASH_SECTOR_6; - if ((uint32_t)&__config_start <= 0x0807FFFF) - return FLASH_SECTOR_7; - - // Not good - while (1) { - failureMode(FAILURE_CONFIG_STORE_FAILURE); - } -} - -#elif defined(STM32F4) -/* -Sector 0 0x08000000 - 0x08003FFF 16 Kbytes -Sector 1 0x08004000 - 0x08007FFF 16 Kbytes -Sector 2 0x08008000 - 0x0800BFFF 16 Kbytes -Sector 3 0x0800C000 - 0x0800FFFF 16 Kbytes -Sector 4 0x08010000 - 0x0801FFFF 64 Kbytes -Sector 5 0x08020000 - 0x0803FFFF 128 Kbytes -Sector 6 0x08040000 - 0x0805FFFF 128 Kbytes -Sector 7 0x08060000 - 0x0807FFFF 128 Kbytes -Sector 8 0x08080000 - 0x0809FFFF 128 Kbytes -Sector 9 0x080A0000 - 0x080BFFFF 128 Kbytes -Sector 10 0x080C0000 - 0x080DFFFF 128 Kbytes -Sector 11 0x080E0000 - 0x080FFFFF 128 Kbytes -*/ - -static uint32_t getFLASHSectorForEEPROM(void) -{ - if ((uint32_t)&__config_start <= 0x08003FFF) - return FLASH_Sector_0; - if ((uint32_t)&__config_start <= 0x08007FFF) - return FLASH_Sector_1; - if ((uint32_t)&__config_start <= 0x0800BFFF) - return FLASH_Sector_2; - if ((uint32_t)&__config_start <= 0x0800FFFF) - return FLASH_Sector_3; - if ((uint32_t)&__config_start <= 0x0801FFFF) - return FLASH_Sector_4; - if ((uint32_t)&__config_start <= 0x0803FFFF) - return FLASH_Sector_5; - if ((uint32_t)&__config_start <= 0x0805FFFF) - return FLASH_Sector_6; - if ((uint32_t)&__config_start <= 0x0807FFFF) - return FLASH_Sector_7; - if ((uint32_t)&__config_start <= 0x0809FFFF) - return FLASH_Sector_8; - if ((uint32_t)&__config_start <= 0x080DFFFF) - return FLASH_Sector_9; - if ((uint32_t)&__config_start <= 0x080BFFFF) - return FLASH_Sector_10; - if ((uint32_t)&__config_start <= 0x080FFFFF) - return FLASH_Sector_11; - - // Not good - while (1) { - failureMode(FAILURE_CONFIG_STORE_FAILURE); - } -} - -#elif defined(STM32H743xx) || defined(STM32G4) || defined(STM32H7A3xx) || defined(STM32H7A3xxQ) || defined(STM32H723xx) || defined(STM32H725xx) -/* -MCUs with uniform array of equal size sectors, handled in two banks having contiguous address. -(Devices with non-contiguous flash layout is not currently useful anyways.) - -H743 -2 bank * 8 sector/bank * 128K/sector (2MB) -Bank 1 0x08000000 - 0x080FFFFF 128KB * 8 -Bank 2 0x08100000 - 0x081FFFFF 128KB * 8 - -H743 -1 bank * 8 sector/bank * 128K/sector (1MB) -Bank 1 0x08000000 - 0x080FFFFF 128KB * 8 - -H7A3 -2 bank * 128 sector/bank * 8KB/sector (2MB) -Bank 1 0x08000000 - 0x080FFFFF 8KB * 128 -Bank 2 0x08100000 - 0x081FFFFF 8KB * 128 - -G473/474 in dual bank mode -2 bank * 128 sector/bank * 2KB/sector (512KB) -Bank 1 0x08000000 - 0x0803FFFF 2KB * 128 -Bank 2 0x08040000 - 0x0807FFFF 2KB * 128 - -Note that FLASH_BANK_SIZE constant used in the following code changes depending on -bank operation mode. The code assumes dual bank operation, in which case the -FLASH_BANK_SIZE constant is set to one half of the available flash size in HAL. -*/ - -#if defined(STM32H743xx) || defined(STM32H723xx) || defined(STM32H725xx) -#define FLASH_PAGE_PER_BANK 8 -#elif defined(STM32H7A3xx) || defined(STM32H7A3xxQ) -#define FLASH_PAGE_PER_BANK 128 -#elif defined(STM32G4) -#define FLASH_PAGE_PER_BANK 128 -// These are not defined in CMSIS like H7 -#define FLASH_BANK1_BASE FLASH_BASE -#define FLASH_BANK2_BASE (FLASH_BANK1_BASE + FLASH_BANK_SIZE) -#endif - -static void getFLASHSectorForEEPROM(uint32_t address, uint32_t *bank, uint32_t *sector) -{ -#if defined(FLASH_BANK2_BASE) - if (address >= FLASH_BANK1_BASE && address < FLASH_BANK2_BASE) { - *bank = FLASH_BANK_1; - } else if (address >= FLASH_BANK2_BASE && address < FLASH_BANK2_BASE + FLASH_BANK_SIZE) { - *bank = FLASH_BANK_2; - address -= FLASH_BANK_SIZE; - } -#else - if (address >= FLASH_BANK1_BASE && address < FLASH_BANK1_BASE + FLASH_BANK_SIZE) { - *bank = FLASH_BANK_1; - } -#endif - else { - // Not good - while (1) { - failureMode(FAILURE_CONFIG_STORE_FAILURE); - } - } - - address -= FLASH_BANK1_BASE; - *sector = address / FLASH_PAGE_SIZE; -} -#elif defined(STM32H750xx) -/* -The memory map supports 2 banks of 8 128k sectors like the H743xx, but there is only one 128K sector so we save some code -space by using a smaller function. - -Bank 1 -Sector 0 0x08000000 - 0x0801FFFF 128 Kbytes - -*/ - -static void getFLASHSectorForEEPROM(uint32_t *bank, uint32_t *sector) -{ - - uint32_t start = (uint32_t)&__config_start; - - if (start == FLASH_BANK1_BASE) { - *sector = FLASH_SECTOR_0; - *bank = FLASH_BANK_1; - } else { - // Not good - while (1) { - failureMode(FAILURE_CONFIG_STORE_FAILURE); - } - } -} -#elif defined(APM32F4) -/* -Sector 0 0x08000000 - 0x08003FFF 16 Kbytes -Sector 1 0x08004000 - 0x08007FFF 16 Kbytes -Sector 2 0x08008000 - 0x0800BFFF 16 Kbytes -Sector 3 0x0800C000 - 0x0800FFFF 16 Kbytes -Sector 4 0x08010000 - 0x0801FFFF 64 Kbytes -Sector 5 0x08020000 - 0x0803FFFF 128 Kbytes -Sector 6 0x08040000 - 0x0805FFFF 128 Kbytes -Sector 7 0x08060000 - 0x0807FFFF 128 Kbytes -Sector 8 0x08080000 - 0x0809FFFF 128 Kbytes -Sector 9 0x080A0000 - 0x080BFFFF 128 Kbytes -Sector 10 0x080C0000 - 0x080DFFFF 128 Kbytes -Sector 11 0x080E0000 - 0x080FFFFF 128 Kbytes -*/ - -static uint32_t getFLASHSectorForEEPROM(void) -{ - if ((uint32_t)&__config_start <= 0x08003FFF) - return FLASH_SECTOR_0; - if ((uint32_t)&__config_start <= 0x08007FFF) - return FLASH_SECTOR_1; - if ((uint32_t)&__config_start <= 0x0800BFFF) - return FLASH_SECTOR_2; - if ((uint32_t)&__config_start <= 0x0800FFFF) - return FLASH_SECTOR_3; - if ((uint32_t)&__config_start <= 0x0801FFFF) - return FLASH_SECTOR_4; - if ((uint32_t)&__config_start <= 0x0803FFFF) - return FLASH_SECTOR_5; - if ((uint32_t)&__config_start <= 0x0805FFFF) - return FLASH_SECTOR_6; - if ((uint32_t)&__config_start <= 0x0807FFFF) - return FLASH_SECTOR_7; - if ((uint32_t)&__config_start <= 0x0809FFFF) - return FLASH_SECTOR_8; - if ((uint32_t)&__config_start <= 0x080DFFFF) - return FLASH_SECTOR_9; - if ((uint32_t)&__config_start <= 0x080BFFFF) - return FLASH_SECTOR_10; - if ((uint32_t)&__config_start <= 0x080FFFFF) - return FLASH_SECTOR_11; - - // Not good - while (1) { - failureMode(FAILURE_CONFIG_STORE_FAILURE); - } -} - -#endif -#endif // CONFIG_IN_FLASH - -// FIXME the return values are currently magic numbers -static int write_word(config_streamer_t *c, config_streamer_buffer_align_type_t *buffer) -{ - if (c->err != 0) { + if (c->err != CONFIG_RESULT_SUCCESS) { return c->err; } #if defined(CONFIG_IN_EXTERNAL_FLASH) @@ -392,7 +91,7 @@ static int write_word(config_streamer_t *c, config_streamer_buffer_align_type_t uint32_t flashAddress = flashStartAddress + dataOffset; if (flashAddress + CONFIG_STREAMER_BUFFER_SIZE > flashOverflowAddress) { - return -3; // address is past end of partition + return CONFIG_RESULT_ADDRESS_INVALID; // address is past end of partition } uint32_t flashSectorSize = flashGeometry->sectorSize; @@ -415,7 +114,7 @@ static int write_word(config_streamer_t *c, config_streamer_buffer_align_type_t flashPageProgramBegin(flashAddress, NULL); } - buffers[0] = (uint8_t *)buffer; + buffers[0] = (uint8_t*)buffer; bufferSizes[0] = CONFIG_STREAMER_BUFFER_SIZE; flashPageProgramContinue(buffers, bufferSizes, 1); @@ -425,179 +124,56 @@ static int write_word(config_streamer_t *c, config_streamer_buffer_align_type_t memset(eepromData, 0, sizeof(eepromData)); } - uint64_t *dest_addr = (uint64_t *)c->address; + uint64_t *dest_addr = (uint64_t*)c->address; uint64_t *src_addr = (uint64_t*)buffer; uint8_t row_index = CONFIG_STREAMER_BUFFER_SIZE / sizeof(uint64_t); STATIC_ASSERT(CONFIG_STREAMER_BUFFER_SIZE % sizeof(uint64_t) == 0, "CONFIG_STREAMER_BUFFER_SIZE does not match written size"); /* copy the 256 bits flash word */ - do - { + do { *dest_addr++ = *src_addr++; } while (--row_index != 0); -#elif defined(CONFIG_IN_FILE) +#elif defined(CONFIG_IN_FLASH) || defined(CONFIG_IN_FILE) - if (c->address % FLASH_PAGE_SIZE == 0) { - const FLASH_Status status = FLASH_ErasePage(c->address); - if (status != FLASH_COMPLETE) { - return -1; - } - } - STATIC_ASSERT(CONFIG_STREAMER_BUFFER_SIZE == sizeof(uint32_t), "CONFIG_STREAMER_BUFFER_SIZE does not match written size"); - const FLASH_Status status = FLASH_ProgramWord(c->address, *buffer); - if (status != FLASH_COMPLETE) { - return -2; + configStreamerResult_e result = configWriteWord(c->address, buffer); + if (result != CONFIG_RESULT_SUCCESS) { + return result; } -#elif defined(CONFIG_IN_FLASH) - -#if defined(STM32H7) - if (c->address % FLASH_PAGE_SIZE == 0) { - FLASH_EraseInitTypeDef EraseInitStruct = { - .TypeErase = FLASH_TYPEERASE_SECTORS, -#if !(defined(STM32H7A3xx) || defined(STM32H7A3xxQ)) - .VoltageRange = FLASH_VOLTAGE_RANGE_3, // 2.7-3.6V -#endif - .NbSectors = 1 - }; - getFLASHSectorForEEPROM(c->address, &EraseInitStruct.Banks, &EraseInitStruct.Sector); - uint32_t SECTORError; - const HAL_StatusTypeDef status = HAL_FLASHEx_Erase(&EraseInitStruct, &SECTORError); - if (status != HAL_OK) { - return -1; - } - } - - // For H7 - // HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t DataAddress); - STATIC_ASSERT(CONFIG_STREAMER_BUFFER_SIZE == sizeof(uint32_t) * FLASH_NB_32BITWORD_IN_FLASHWORD, "CONFIG_STREAMER_BUFFER_SIZE does not match written size"); - const HAL_StatusTypeDef status = HAL_FLASH_Program(FLASH_TYPEPROGRAM_FLASHWORD, c->address, (uint64_t)(uint32_t)buffer); - if (status != HAL_OK) { - return -2; - } -#elif defined(STM32F7) - if (c->address % FLASH_PAGE_SIZE == 0) { - FLASH_EraseInitTypeDef EraseInitStruct = { - .TypeErase = FLASH_TYPEERASE_SECTORS, - .VoltageRange = FLASH_VOLTAGE_RANGE_3, // 2.7-3.6V - .NbSectors = 1 - }; - EraseInitStruct.Sector = getFLASHSectorForEEPROM(); - uint32_t SECTORError; - const HAL_StatusTypeDef status = HAL_FLASHEx_Erase(&EraseInitStruct, &SECTORError); - if (status != HAL_OK) { - return -1; - } - } - - STATIC_ASSERT(CONFIG_STREAMER_BUFFER_SIZE == sizeof(uint32_t) * 1, "CONFIG_STREAMER_BUFFER_SIZE does not match written size"); - // For F7 - // HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data); - const HAL_StatusTypeDef status = HAL_FLASH_Program(FLASH_TYPEPROGRAM_WORD, c->address, (uint64_t)*buffer); - if (status != HAL_OK) { - return -2; - } -#elif defined(STM32G4) - if (c->address % FLASH_PAGE_SIZE == 0) { - - FLASH_EraseInitTypeDef EraseInitStruct = { - .TypeErase = FLASH_TYPEERASE_PAGES, - .NbPages = 1 - }; - getFLASHSectorForEEPROM(c->address, &EraseInitStruct.Banks, &EraseInitStruct.Page); - uint32_t SECTORError; - const HAL_StatusTypeDef status = HAL_FLASHEx_Erase(&EraseInitStruct, &SECTORError); - if (status != HAL_OK) { - return -1; - } - } - - STATIC_ASSERT(CONFIG_STREAMER_BUFFER_SIZE == sizeof(uint32_t) * 2, "CONFIG_STREAMER_BUFFER_SIZE does not match written size"); - const HAL_StatusTypeDef status = HAL_FLASH_Program(FLASH_TYPEPROGRAM_DOUBLEWORD, c->address, (uint64_t)*buffer); - if (status != HAL_OK) { - return -2; - } -#elif defined(AT32F4) - if (c->address % FLASH_PAGE_SIZE == 0) { - const flash_status_type status = flash_sector_erase(c->address); - if (status != FLASH_OPERATE_DONE) { - return -1; - } - } - - STATIC_ASSERT(CONFIG_STREAMER_BUFFER_SIZE == sizeof(uint32_t) * 1, "CONFIG_STREAMER_BUFFER_SIZE does not match written size"); - const flash_status_type status = flash_word_program(c->address, (uint32_t)*buffer); - if (status != FLASH_OPERATE_DONE) { - return -2; - } -#elif defined(APM32F4) - if (c->address % FLASH_PAGE_SIZE == 0) { - FLASH_EraseInitTypeDef EraseInitStruct = { - .TypeErase = FLASH_TYPEERASE_SECTORS, - .VoltageRange = FLASH_VOLTAGE_RANGE_3, // 2.7-3.6V - .NbSectors = 1 - }; - EraseInitStruct.Sector = getFLASHSectorForEEPROM(); - uint32_t SECTORError; - const DAL_StatusTypeDef status = DAL_FLASHEx_Erase(&EraseInitStruct, &SECTORError); - if (status != DAL_OK) { - return -1; - } - } - - STATIC_ASSERT(CONFIG_STREAMER_BUFFER_SIZE == sizeof(uint32_t) * 1, "CONFIG_STREAMER_BUFFER_SIZE does not match written size"); - const DAL_StatusTypeDef status = DAL_FLASH_Program(FLASH_TYPEPROGRAM_WORD, c->address, (uint64_t)*buffer); - if (status != DAL_OK) { - return -2; - } -#else // !STM32H7 && !STM32F7 && !STM32G4 - if (c->address % FLASH_PAGE_SIZE == 0) { - const FLASH_Status status = FLASH_EraseSector(getFLASHSectorForEEPROM(), VoltageRange_3); //0x08080000 to 0x080A0000 - if (status != FLASH_COMPLETE) { - return -1; - } - } - - STATIC_ASSERT(CONFIG_STREAMER_BUFFER_SIZE == sizeof(uint32_t) * 1, "CONFIG_STREAMER_BUFFER_SIZE does not match written size"); - const FLASH_Status status = FLASH_ProgramWord(c->address, *buffer); - if (status != FLASH_COMPLETE) { - return -2; - } -#endif #endif c->address += CONFIG_STREAMER_BUFFER_SIZE; - return 0; + return CONFIG_RESULT_SUCCESS; } -int config_streamer_write(config_streamer_t *c, const uint8_t *p, uint32_t size) +configStreamerResult_e config_streamer_write(config_streamer_t *c, const uint8_t *p, size_t size) { for (const uint8_t *pat = p; pat != (uint8_t*)p + size; pat++) { c->buffer.b[c->at++] = *pat; if (c->at == sizeof(c->buffer)) { - c->err = write_word(c, &c->buffer.w); + c->err = write_word(c, c->buffer.w); c->at = 0; } } return c->err; } -int config_streamer_status(config_streamer_t *c) +configStreamerResult_e config_streamer_status(config_streamer_t *c) { return c->err; } -int config_streamer_flush(config_streamer_t *c) +configStreamerResult_e config_streamer_flush(config_streamer_t *c) { if (c->at != 0) { memset(c->buffer.b + c->at, 0, sizeof(c->buffer) - c->at); - c->err = write_word(c, &c->buffer.w); + c->err = write_word(c, c->buffer.w); c->at = 0; } return c->err; } -int config_streamer_finish(config_streamer_t *c) +configStreamerResult_e config_streamer_finish(config_streamer_t *c) { if (c->unlocked) { #if defined(CONFIG_IN_SDCARD) @@ -608,18 +184,8 @@ int config_streamer_finish(config_streamer_t *c) saveEEPROMToMemoryMappedFlash(); #elif defined(CONFIG_IN_RAM) // NOP -#elif defined(CONFIG_IN_FILE) - FLASH_Lock(); -#elif defined(CONFIG_IN_FLASH) -#if defined(STM32F7) || defined(STM32H7) || defined(STM32G4) - HAL_FLASH_Lock(); -#elif defined(AT32F4) - flash_lock(); -#elif defined(APM32F4) - DAL_FLASH_Lock(); -#else - FLASH_Lock(); -#endif +#elif defined(CONFIG_IN_FILE) || defined(CONFIG_IN_FLASH) + configLock(); #endif c->unlocked = false; } diff --git a/src/main/config/config_streamer.h b/src/main/config/config_streamer.h index 930dcbe50b..df1ba4a03c 100644 --- a/src/main/config/config_streamer.h +++ b/src/main/config/config_streamer.h @@ -23,49 +23,63 @@ #include #include +#include "platform.h" + // Streams data out to the EEPROM, padding to the write size as // needed, and updating the checksum as it goes. #if defined(CONFIG_IN_EXTERNAL_FLASH) || defined(CONFIG_IN_MEMORY_MAPPED_FLASH) #define CONFIG_STREAMER_BUFFER_SIZE 8 // Must not be greater than the smallest flash page size of all compiled-in flash devices. -typedef uint32_t config_streamer_buffer_align_type_t; +#define CONFIG_BUFFER_TYPE uint32_t #elif defined(CONFIG_IN_RAM) || defined(CONFIG_IN_SDCARD) #define CONFIG_STREAMER_BUFFER_SIZE 32 -typedef uint64_t config_streamer_buffer_align_type_t; -#elif defined(STM32H743xx) || defined(STM32H750xx) || defined(STM32H723xx) || defined(STM32H725xx) -#define CONFIG_STREAMER_BUFFER_SIZE 32 // Flash word = 256-bits -typedef uint64_t config_streamer_buffer_align_type_t; -#elif defined(STM32H7A3xx) || defined(STM32H7A3xxQ) -#define CONFIG_STREAMER_BUFFER_SIZE 16 // Flash word = 128-bits -typedef uint64_t config_streamer_buffer_align_type_t; -#elif defined(STM32G4) -#define CONFIG_STREAMER_BUFFER_SIZE 8 // Flash word = 64-bits -typedef uint64_t config_streamer_buffer_align_type_t; -#elif defined(APM32F4) -#define CONFIG_STREAMER_BUFFER_SIZE 4 // Flash word = 32-bits -typedef uint32_t config_streamer_buffer_align_type_t; -#else -#define CONFIG_STREAMER_BUFFER_SIZE 4 -typedef uint32_t config_streamer_buffer_align_type_t; +#define CONFIG_BUFFER_TYPE uint64_t +#elif defined(CONFIG_IN_FILE) +#define CONFIG_BUFFER_TYPE uint32_t +#elif defined(CONFIG_IN_FLASH) +#if defined(FLASH_CONFIG_STREAMER_BUFFER_SIZE) +#define CONFIG_STREAMER_BUFFER_SIZE FLASH_CONFIG_STREAMER_BUFFER_SIZE #endif +#define CONFIG_BUFFER_TYPE FLASH_CONFIG_BUFFER_TYPE +#endif + +#if !defined(CONFIG_BUFFER_TYPE) +#error "No config buffer alignment set" +#endif + +#if !defined(CONFIG_STREAMER_BUFFER_SIZE) +#define CONFIG_STREAMER_BUFFER_SIZE sizeof(CONFIG_BUFFER_TYPE) +#endif + +typedef enum { + CONFIG_RESULT_TIMEOUT = -4, + CONFIG_RESULT_ADDRESS_INVALID = -3, + CONFIG_RESULT_INCOMPLETE = -2, + CONFIG_RESULT_FAILURE = -1, + CONFIG_RESULT_SUCCESS = 0 +} configStreamerResult_e; + +typedef CONFIG_BUFFER_TYPE config_streamer_buffer_type_t; +STATIC_ASSERT(CONFIG_STREAMER_BUFFER_SIZE % sizeof(config_streamer_buffer_type_t) == 0, "CONFIG_STREAMER_BUFFER_SIZE does not fit to FLASH WORD size"); typedef struct config_streamer_s { uintptr_t address; int size; union { uint8_t b[CONFIG_STREAMER_BUFFER_SIZE]; - config_streamer_buffer_align_type_t w; + config_streamer_buffer_type_t w[CONFIG_STREAMER_BUFFER_SIZE / sizeof(config_streamer_buffer_type_t)]; } buffer; int at; - int err; + configStreamerResult_e err; bool unlocked; } config_streamer_t; void config_streamer_init(config_streamer_t *c); -void config_streamer_start(config_streamer_t *c, uintptr_t base, int size); -int config_streamer_write(config_streamer_t *c, const uint8_t *p, uint32_t size); -int config_streamer_flush(config_streamer_t *c); +void config_streamer_start(config_streamer_t *c, uintptr_t base, size_t size); +configStreamerResult_e config_streamer_write(config_streamer_t *c, const uint8_t *p, size_t size); +configStreamerResult_e config_streamer_flush(config_streamer_t *c); + +configStreamerResult_e config_streamer_finish(config_streamer_t *c); +configStreamerResult_e config_streamer_status(config_streamer_t *c); -int config_streamer_finish(config_streamer_t *c); -int config_streamer_status(config_streamer_t *c); diff --git a/src/main/config/config_streamer_impl.h b/src/main/config/config_streamer_impl.h new file mode 100644 index 0000000000..12fda926c6 --- /dev/null +++ b/src/main/config/config_streamer_impl.h @@ -0,0 +1,29 @@ +/* + * This file is part of Betaflight. + * + * Betaflight is free software. You can redistribute this software + * and/or modify this software under the terms of the GNU General + * Public License as published by the Free Software Foundation, + * either version 3 of the License, or (at your option) any later + * version. + * + * Betaflight is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * See the GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this software. + * + * If not, see . + */ + +#pragma once + +#include "config_streamer.h" + +void configUnlock(void); +void configLock(void); +void configClearFlags(void); +configStreamerResult_e configWriteWord(uintptr_t address, config_streamer_buffer_type_t *buffer); diff --git a/src/main/drivers/system.h b/src/main/drivers/system.h index f76229d253..ff106bbc38 100644 --- a/src/main/drivers/system.h +++ b/src/main/drivers/system.h @@ -43,6 +43,8 @@ typedef enum { FAILURE_SDCARD_WRITE_FAILED, FAILURE_SDCARD_INITIALISATION_FAILED, FAILURE_SDCARD_REQUIRED, + FAILURE_FILE_READ_FAILED, + FAILURE_FILE_WRITE_FAILED, } failureMode_e; #define WARNING_FLASH_DURATION_MS 50 diff --git a/src/platform/APM32/mk/APM32F4.mk b/src/platform/APM32/mk/APM32F4.mk index 9ea1025baf..4b3a3cee21 100644 --- a/src/platform/APM32/mk/APM32F4.mk +++ b/src/platform/APM32/mk/APM32F4.mk @@ -148,6 +148,7 @@ endif MCU_COMMON_SRC = \ common/stm32/system.c \ common/stm32/io_impl.c \ + common/stm32/config_flash.c \ APM32/startup/system_apm32f4xx.c \ drivers/inverter.c \ drivers/dshot_bitbang_decode.c \ @@ -177,8 +178,8 @@ MCU_COMMON_SRC = \ drivers/adc.c \ drivers/bus_i2c_config.c \ drivers/bus_spi_config.c \ - common/stm32/bus_spi_pinconfig.c \ common/stm32/bus_spi_hw.c \ + common/stm32/bus_spi_pinconfig.c \ drivers/serial_escserial.c \ drivers/serial_pinconfig.c \ drivers/serial_uart_pinconfig.c \ @@ -204,7 +205,6 @@ MSC_SRC = \ msc/usbd_storage_sdio.c SPEED_OPTIMISED_SRC += \ - common/stm32/bus_spi_hw.c \ common/stm32/system.c SIZE_OPTIMISED_SRC += \ diff --git a/src/platform/APM32/platform_mcu.h b/src/platform/APM32/platform_mcu.h index 769d1cc3ed..8e0aa79749 100644 --- a/src/platform/APM32/platform_mcu.h +++ b/src/platform/APM32/platform_mcu.h @@ -188,3 +188,7 @@ #define USE_TX_IRQ_HANDLER #endif + +#if defined(APM32F4) +#define FLASH_CONFIG_BUFFER_TYPE uint32_t +#endif diff --git a/src/platform/AT32/mk/AT32F4.mk b/src/platform/AT32/mk/AT32F4.mk index cc5f9955f1..0c0ff8be39 100644 --- a/src/platform/AT32/mk/AT32F4.mk +++ b/src/platform/AT32/mk/AT32F4.mk @@ -83,6 +83,7 @@ DEVICE_FLAGS += -DUSE_ATBSP_DRIVER -DAT32F43x -DHSE_VALUE=$(HSE_VALUE) -DAT32 MCU_COMMON_SRC = \ common/stm32/system.c \ common/stm32/io_impl.c \ + common/stm32/config_flash.c \ AT32/startup/at32f435_437_clock.c \ AT32/startup/system_at32f435_437.c \ AT32/adc_at32f43x.c \ diff --git a/src/platform/AT32/platform_mcu.h b/src/platform/AT32/platform_mcu.h index 36baa0f7fc..9a42c16cfc 100644 --- a/src/platform/AT32/platform_mcu.h +++ b/src/platform/AT32/platform_mcu.h @@ -142,3 +142,5 @@ typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; #define MAX_SPI_PIN_SEL 4 #endif + +#define FLASH_CONFIG_BUFFER_TYPE uint32_t diff --git a/src/platform/SIMULATOR/sitl.c b/src/platform/SIMULATOR/sitl.c index c96c268fed..65752866c6 100644 --- a/src/platform/SIMULATOR/sitl.c +++ b/src/platform/SIMULATOR/sitl.c @@ -48,6 +48,8 @@ #include "config/feature.h" #include "config/config.h" +#include "config/config_streamer.h" + #include "scheduler/scheduler.h" #include "pg/rx.h" @@ -659,18 +661,18 @@ char _Min_Stack_Size; // virtual EEPROM static FILE *eepromFd = NULL; -void FLASH_Unlock(void) +bool loadEEPROMFromFile(void) { if (eepromFd != NULL) { fprintf(stderr, "[FLASH_Unlock] eepromFd != NULL\n"); - return; + return false; } // open or create - eepromFd = fopen(EEPROM_FILENAME,"r+"); + eepromFd = fopen(EEPROM_FILENAME, "r+"); if (eepromFd != NULL) { // obtain file size: - fseek(eepromFd , 0 , SEEK_END); + fseek(eepromFd, 0, SEEK_END); size_t lSize = ftell(eepromFd); rewind(eepromFd); @@ -679,21 +681,29 @@ void FLASH_Unlock(void) printf("[FLASH_Unlock] loaded '%s', size = %ld / %ld\n", EEPROM_FILENAME, lSize, sizeof(eepromData)); } else { fprintf(stderr, "[FLASH_Unlock] failed to load '%s'\n", EEPROM_FILENAME); - return; + return false; } } else { printf("[FLASH_Unlock] created '%s', size = %ld\n", EEPROM_FILENAME, sizeof(eepromData)); if ((eepromFd = fopen(EEPROM_FILENAME, "w+")) == NULL) { fprintf(stderr, "[FLASH_Unlock] failed to create '%s'\n", EEPROM_FILENAME); - return; + return false; } + if (fwrite(eepromData, sizeof(eepromData), 1, eepromFd) != 1) { fprintf(stderr, "[FLASH_Unlock] write failed: %s\n", strerror(errno)); + return false; } } + return true; } -void FLASH_Lock(void) +void configUnlock(void) +{ + loadEEPROMFromFile(); +} + +void configLock(void) { // flush & close if (eepromFd != NULL) { @@ -707,22 +717,17 @@ void FLASH_Lock(void) } } -FLASH_Status FLASH_ErasePage(uintptr_t Page_Address) +configStreamerResult_e configWriteWord(uintptr_t address, config_streamer_buffer_type_t *buffer) { - UNUSED(Page_Address); -// printf("[FLASH_ErasePage]%x\n", Page_Address); - return FLASH_COMPLETE; -} + STATIC_ASSERT(CONFIG_STREAMER_BUFFER_SIZE == sizeof(uint32_t), "CONFIG_STREAMER_BUFFER_SIZE does not match written size"); -FLASH_Status FLASH_ProgramWord(uintptr_t addr, uint32_t value) -{ - if ((addr >= (uintptr_t)eepromData) && (addr < (uintptr_t)ARRAYEND(eepromData))) { - *((uint32_t*)addr) = value; - printf("[FLASH_ProgramWord]%p = %08x\n", (void*)addr, *((uint32_t*)addr)); + if ((address >= (uintptr_t)eepromData) && (address + sizeof(uint32_t) <= (uintptr_t)ARRAYEND(eepromData))) { + memcpy((void*)address, buffer, sizeof(config_streamer_buffer_type_t)); + printf("[FLASH_ProgramWord]%p = %08x\n", (void*)address, *((uint32_t*)address)); } else { - printf("[FLASH_ProgramWord]%p out of range!\n", (void*)addr); + printf("[FLASH_ProgramWord]%p out of range!\n", (void*)address); } - return FLASH_COMPLETE; + return CONFIG_RESULT_SUCCESS; } void IOConfigGPIO(IO_t io, ioConfig_t cfg) diff --git a/src/platform/SIMULATOR/target/SITL/target.h b/src/platform/SIMULATOR/target/SITL/target.h index e620fa9a40..5a75501c8f 100644 --- a/src/platform/SIMULATOR/target/SITL/target.h +++ b/src/platform/SIMULATOR/target/SITL/target.h @@ -236,15 +236,6 @@ typedef struct void* test; } I2C_TypeDef; -typedef enum -{ - FLASH_BUSY = 1, - FLASH_ERROR_PG, - FLASH_ERROR_WRP, - FLASH_COMPLETE, - FLASH_TIMEOUT -} FLASH_Status; - typedef struct { double timestamp; // in seconds double imu_angular_velocity_rpy[3]; // rad/s -> range: +/- 8192; +/- 2000 deg/se @@ -269,11 +260,6 @@ typedef struct { float pwm_output_raw[SIMULATOR_MAX_PWM_CHANNELS]; // Raw PWM from 1100 to 1900 } servo_packet_raw; -void FLASH_Unlock(void); -void FLASH_Lock(void); -FLASH_Status FLASH_ErasePage(uintptr_t Page_Address); -FLASH_Status FLASH_ProgramWord(uintptr_t addr, uint32_t Data); - uint64_t nanos64_real(void); uint64_t micros64_real(void); uint64_t millis64_real(void); diff --git a/src/platform/STM32/mk/STM32F4.mk b/src/platform/STM32/mk/STM32F4.mk index 43fc7b16b7..28bf0fecb6 100644 --- a/src/platform/STM32/mk/STM32F4.mk +++ b/src/platform/STM32/mk/STM32F4.mk @@ -171,6 +171,7 @@ DEVICE_FLAGS += -DHSE_VALUE=$(HSE_VALUE) -DSTM32 MCU_COMMON_SRC = \ common/stm32/system.c \ + common/stm32/config_flash.c \ drivers/accgyro/accgyro_mpu.c \ drivers/dshot_bitbang_decode.c \ drivers/inverter.c \ diff --git a/src/platform/STM32/mk/STM32F7.mk b/src/platform/STM32/mk/STM32F7.mk index b0341b7c75..b197c92774 100644 --- a/src/platform/STM32/mk/STM32F7.mk +++ b/src/platform/STM32/mk/STM32F7.mk @@ -140,7 +140,6 @@ VCP_SRC = \ drivers/usb_io.c MCU_COMMON_SRC = \ - common/stm32/system.c \ drivers/accgyro/accgyro_mpu.c \ drivers/bus_i2c_timing.c \ drivers/dshot_bitbang_decode.c \ @@ -189,7 +188,6 @@ MSC_SRC = \ msc/usbd_storage_sd_spi.c SPEED_OPTIMISED_SRC += \ - common/stm32/system.c \ STM32/bus_i2c_hal.c \ STM32/bus_spi_ll.c \ drivers/max7456.c \ diff --git a/src/platform/STM32/mk/STM32G4.mk b/src/platform/STM32/mk/STM32G4.mk index 8acdd13fca..41b1ba1a45 100644 --- a/src/platform/STM32/mk/STM32G4.mk +++ b/src/platform/STM32/mk/STM32G4.mk @@ -117,7 +117,6 @@ VCP_SRC = \ drivers/usb_io.c MCU_COMMON_SRC = \ - common/stm32/system.c \ drivers/accgyro/accgyro_mpu.c \ drivers/bus_i2c_timing.c \ drivers/dshot_bitbang_decode.c \ @@ -167,7 +166,6 @@ MSC_SRC = \ msc/usbd_storage_sd_spi.c SPEED_OPTIMISED_SRC += \ - common/stm32/system.c \ STM32/exti.c SIZE_OPTIMISED_SRC += \ diff --git a/src/platform/STM32/mk/STM32H5.mk b/src/platform/STM32/mk/STM32H5.mk index 3aade083b1..b8fb8511d2 100644 --- a/src/platform/STM32/mk/STM32H5.mk +++ b/src/platform/STM32/mk/STM32H5.mk @@ -148,7 +148,6 @@ VCP_SRC = drivers/usb_io.c MCU_COMMON_SRC = \ - common/stm32/system.c \ drivers/bus_i2c_timing.c \ drivers/bus_quadspi.c \ drivers/dshot_bitbang_decode.c \ @@ -201,7 +200,6 @@ MSC_SRC = msc/usbd_storage_sdio.c SPEED_OPTIMISED_SRC += \ - common/stm32/system.c \ STM32/exti.c SIZE_OPTIMISED_SRC += \ diff --git a/src/platform/STM32/mk/STM32H7.mk b/src/platform/STM32/mk/STM32H7.mk index c8ba1550d3..ffa2bf5b6f 100644 --- a/src/platform/STM32/mk/STM32H7.mk +++ b/src/platform/STM32/mk/STM32H7.mk @@ -263,7 +263,6 @@ VCP_SRC = \ drivers/usb_io.c MCU_COMMON_SRC = \ - common/stm32/system.c \ drivers/bus_i2c_timing.c \ drivers/bus_quadspi.c \ drivers/dshot_bitbang_decode.c \ @@ -316,7 +315,6 @@ MSC_SRC = \ msc/usbd_storage_sdio.c SPEED_OPTIMISED_SRC += \ - common/stm32/system.c \ STM32/exti.c SIZE_OPTIMISED_SRC += \ diff --git a/src/platform/STM32/mk/STM32_COMMON.mk b/src/platform/STM32/mk/STM32_COMMON.mk index 1e45a60ae2..e8f7914941 100644 --- a/src/platform/STM32/mk/STM32_COMMON.mk +++ b/src/platform/STM32/mk/STM32_COMMON.mk @@ -2,14 +2,18 @@ INCLUDE_DIRS += $(PLATFORM_DIR)/common/stm32 MCU_COMMON_SRC += \ + common/stm32/system.c \ + common/stm32/config_flash.c \ common/stm32/bus_spi_pinconfig.c \ common/stm32/bus_spi_hw.c \ common/stm32/io_impl.c SIZE_OPTIMISED_SRC += \ + common/stm32/config_flash.c \ common/stm32/bus_spi_pinconfig.c SPEED_OPTIMISED_SRC += \ + common/stm32/system.c \ common/stm32/bus_spi_hw.c \ common/stm32/io_impl.c diff --git a/src/platform/STM32/platform_mcu.h b/src/platform/STM32/platform_mcu.h index a620f27932..1f69a3cfc9 100644 --- a/src/platform/STM32/platform_mcu.h +++ b/src/platform/STM32/platform_mcu.h @@ -302,6 +302,18 @@ extern uint8_t _dmaram_end__; #endif +#if defined(STM32H743xx) || defined(STM32H750xx) || defined(STM32H723xx) || defined(STM32H725xx) +#define FLASH_CONFIG_STREAMER_BUFFER_SIZE 32 // Flash word = 256-bits (8 rows, uint32_t per row - 8 x 32) +#define FLASH_CONFIG_BUFFER_TYPE uint32_t +#elif defined(STM32H7A3xx) || defined(STM32H7A3xxQ) +#define FLASH_CONFIG_STREAMER_BUFFER_SIZE 16 // Flash word = 128-bits (4 rows, uint32_t per row - 4 x 32) +#define FLASH_CONFIG_BUFFER_TYPE uint32_t +#elif defined(STM32G4) +#define FLASH_CONFIG_BUFFER_TYPE uint64_t +#else +#define FLASH_CONFIG_BUFFER_TYPE uint32_t +#endif + #if defined(STM32F4) #define SPI_IO_AF_CFG IO_CONFIG(GPIO_Mode_AF, GPIO_Speed_50MHz, GPIO_OType_PP, GPIO_PuPd_NOPULL) #define SPI_IO_AF_SCK_CFG IO_CONFIG(GPIO_Mode_AF, GPIO_Speed_50MHz, GPIO_OType_PP, GPIO_PuPd_DOWN) diff --git a/src/platform/common/stm32/config_flash.c b/src/platform/common/stm32/config_flash.c new file mode 100644 index 0000000000..e1f6b484ed --- /dev/null +++ b/src/platform/common/stm32/config_flash.c @@ -0,0 +1,475 @@ +/* + * This file is part of Betaflight. + * + * Betaflight is free software. You can redistribute this software + * and/or modify this software under the terms of the GNU General + * Public License as published by the Free Software Foundation, + * either version 3 of the License, or (at your option) any later + * version. + * + * Betaflight is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * See the GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this software. + * + * If not, see . + */ + +#include + +#include "platform.h" +#include "drivers/system.h" +#include "config/config_streamer.h" + +#if defined(CONFIG_IN_FLASH) + +#if defined(STM32F745xx) || defined(STM32F746xx) || defined(STM32F765xx) +/* +Sector 0 0x08000000 - 0x08007FFF 32 Kbytes +Sector 1 0x08008000 - 0x0800FFFF 32 Kbytes +Sector 2 0x08010000 - 0x08017FFF 32 Kbytes +Sector 3 0x08018000 - 0x0801FFFF 32 Kbytes +Sector 4 0x08020000 - 0x0803FFFF 128 Kbytes +Sector 5 0x08040000 - 0x0807FFFF 256 Kbytes +Sector 6 0x08080000 - 0x080BFFFF 256 Kbytes +Sector 7 0x080C0000 - 0x080FFFFF 256 Kbytes + +F7X5XI device with 2M flash +Sector 8 0x08100000 - 0x0813FFFF 256 Kbytes +Sector 9 0x08140000 - 0x0817FFFF 256 Kbytes +Sector 10 0x08180000 - 0x081BFFFF 256 Kbytes +Sector 11 0x081C0000 - 0x081FFFFF 256 Kbytes +*/ + +uint32_t getFLASHSectorForEEPROM(void) +{ + if ((uint32_t)&__config_start <= 0x08007FFF) + return FLASH_SECTOR_0; + if ((uint32_t)&__config_start <= 0x0800FFFF) + return FLASH_SECTOR_1; + if ((uint32_t)&__config_start <= 0x08017FFF) + return FLASH_SECTOR_2; + if ((uint32_t)&__config_start <= 0x0801FFFF) + return FLASH_SECTOR_3; + if ((uint32_t)&__config_start <= 0x0803FFFF) + return FLASH_SECTOR_4; + if ((uint32_t)&__config_start <= 0x0807FFFF) + return FLASH_SECTOR_5; + if ((uint32_t)&__config_start <= 0x080BFFFF) + return FLASH_SECTOR_6; + if ((uint32_t)&__config_start <= 0x080FFFFF) + return FLASH_SECTOR_7; +#if defined(STM32F765xx) + if ((uint32_t)&__config_start <= 0x0813FFFF) + return FLASH_SECTOR_8; + if ((uint32_t)&__config_start <= 0x0817FFFF) + return FLASH_SECTOR_9; + if ((uint32_t)&__config_start <= 0x081BFFFF) + return FLASH_SECTOR_10; + if ((uint32_t)&__config_start <= 0x081FFFFF) + return FLASH_SECTOR_11; +#endif + + // Not good + while (1) { + failureMode(FAILURE_CONFIG_STORE_FAILURE); + } +} + +#elif defined(STM32F722xx) +/* +Sector 0 0x08000000 - 0x08003FFF 16 Kbytes +Sector 1 0x08004000 - 0x08007FFF 16 Kbytes +Sector 2 0x08008000 - 0x0800BFFF 16 Kbytes +Sector 3 0x0800C000 - 0x0800FFFF 16 Kbytes +Sector 4 0x08010000 - 0x0801FFFF 64 Kbytes +Sector 5 0x08020000 - 0x0803FFFF 128 Kbytes +Sector 6 0x08040000 - 0x0805FFFF 128 Kbytes +Sector 7 0x08060000 - 0x0807FFFF 128 Kbytes +*/ + +uint32_t getFLASHSectorForEEPROM(void) +{ + if ((uint32_t)&__config_start <= 0x08003FFF) + return FLASH_SECTOR_0; + if ((uint32_t)&__config_start <= 0x08007FFF) + return FLASH_SECTOR_1; + if ((uint32_t)&__config_start <= 0x0800BFFF) + return FLASH_SECTOR_2; + if ((uint32_t)&__config_start <= 0x0800FFFF) + return FLASH_SECTOR_3; + if ((uint32_t)&__config_start <= 0x0801FFFF) + return FLASH_SECTOR_4; + if ((uint32_t)&__config_start <= 0x0803FFFF) + return FLASH_SECTOR_5; + if ((uint32_t)&__config_start <= 0x0805FFFF) + return FLASH_SECTOR_6; + if ((uint32_t)&__config_start <= 0x0807FFFF) + return FLASH_SECTOR_7; + + // Not good + while (1) { + failureMode(FAILURE_CONFIG_STORE_FAILURE); + } +} + +#elif defined(STM32F4) +/* +Sector 0 0x08000000 - 0x08003FFF 16 Kbytes +Sector 1 0x08004000 - 0x08007FFF 16 Kbytes +Sector 2 0x08008000 - 0x0800BFFF 16 Kbytes +Sector 3 0x0800C000 - 0x0800FFFF 16 Kbytes +Sector 4 0x08010000 - 0x0801FFFF 64 Kbytes +Sector 5 0x08020000 - 0x0803FFFF 128 Kbytes +Sector 6 0x08040000 - 0x0805FFFF 128 Kbytes +Sector 7 0x08060000 - 0x0807FFFF 128 Kbytes +Sector 8 0x08080000 - 0x0809FFFF 128 Kbytes +Sector 9 0x080A0000 - 0x080BFFFF 128 Kbytes +Sector 10 0x080C0000 - 0x080DFFFF 128 Kbytes +Sector 11 0x080E0000 - 0x080FFFFF 128 Kbytes +*/ + +uint32_t getFLASHSectorForEEPROM(void) +{ + if ((uint32_t)&__config_start <= 0x08003FFF) + return FLASH_Sector_0; + if ((uint32_t)&__config_start <= 0x08007FFF) + return FLASH_Sector_1; + if ((uint32_t)&__config_start <= 0x0800BFFF) + return FLASH_Sector_2; + if ((uint32_t)&__config_start <= 0x0800FFFF) + return FLASH_Sector_3; + if ((uint32_t)&__config_start <= 0x0801FFFF) + return FLASH_Sector_4; + if ((uint32_t)&__config_start <= 0x0803FFFF) + return FLASH_Sector_5; + if ((uint32_t)&__config_start <= 0x0805FFFF) + return FLASH_Sector_6; + if ((uint32_t)&__config_start <= 0x0807FFFF) + return FLASH_Sector_7; + if ((uint32_t)&__config_start <= 0x0809FFFF) + return FLASH_Sector_8; + if ((uint32_t)&__config_start <= 0x080DFFFF) + return FLASH_Sector_9; + if ((uint32_t)&__config_start <= 0x080BFFFF) + return FLASH_Sector_10; + if ((uint32_t)&__config_start <= 0x080FFFFF) + return FLASH_Sector_11; + + // Not good + while (1) { + failureMode(FAILURE_CONFIG_STORE_FAILURE); + } +} + +#elif defined(STM32H743xx) || defined(STM32G4) || defined(STM32H7A3xx) || defined(STM32H7A3xxQ) || defined(STM32H723xx) || defined(STM32H725xx) +/* +MCUs with uniform array of equal size sectors, handled in two banks having contiguous address. +(Devices with non-contiguous flash layout is not currently useful anyways.) + +H743 +2 bank * 8 sector/bank * 128K/sector (2MB) +Bank 1 0x08000000 - 0x080FFFFF 128KB * 8 +Bank 2 0x08100000 - 0x081FFFFF 128KB * 8 + +H743 +1 bank * 8 sector/bank * 128K/sector (1MB) +Bank 1 0x08000000 - 0x080FFFFF 128KB * 8 + +H7A3 +2 bank * 128 sector/bank * 8KB/sector (2MB) +Bank 1 0x08000000 - 0x080FFFFF 8KB * 128 +Bank 2 0x08100000 - 0x081FFFFF 8KB * 128 + +G473/474 in dual bank mode +2 bank * 128 sector/bank * 2KB/sector (512KB) +Bank 1 0x08000000 - 0x0803FFFF 2KB * 128 +Bank 2 0x08040000 - 0x0807FFFF 2KB * 128 + +Note that FLASH_BANK_SIZE constant used in the following code changes depending on +bank operation mode. The code assumes dual bank operation, in which case the +FLASH_BANK_SIZE constant is set to one half of the available flash size in HAL. +*/ + +#if defined(STM32H743xx) || defined(STM32H723xx) || defined(STM32H725xx) +#define FLASH_PAGE_PER_BANK 8 +#elif defined(STM32H7A3xx) || defined(STM32H7A3xxQ) +#define FLASH_PAGE_PER_BANK 128 +#elif defined(STM32G4) +#define FLASH_PAGE_PER_BANK 128 +// These are not defined in CMSIS like H7 +#define FLASH_BANK1_BASE FLASH_BASE +#define FLASH_BANK2_BASE (FLASH_BANK1_BASE + FLASH_BANK_SIZE) +#endif + +void getFLASHSectorForEEPROM(uint32_t address, uint32_t *bank, uint32_t *sector) +{ +#if defined(FLASH_BANK2_BASE) + if (address >= FLASH_BANK1_BASE && address < FLASH_BANK2_BASE) { + *bank = FLASH_BANK_1; + } else if (address >= FLASH_BANK2_BASE && address < FLASH_BANK2_BASE + FLASH_BANK_SIZE) { + *bank = FLASH_BANK_2; + address -= FLASH_BANK_SIZE; + } +#else + if (address >= FLASH_BANK1_BASE && address < FLASH_BANK1_BASE + FLASH_BANK_SIZE) { + *bank = FLASH_BANK_1; + } +#endif + else { + // Not good + while (1) { + failureMode(FAILURE_CONFIG_STORE_FAILURE); + } + } + + address -= FLASH_BANK1_BASE; + *sector = address / FLASH_PAGE_SIZE; +} +#elif defined(STM32H750xx) +/* +The memory map supports 2 banks of 8 128k sectors like the H743xx, but there is only one 128K sector so we save some code +space by using a smaller function. + +Bank 1 +Sector 0 0x08000000 - 0x0801FFFF 128 Kbytes + +*/ + +void getFLASHSectorForEEPROM(uint32_t *bank, uint32_t *sector) +{ + + uint32_t start = (uint32_t)&__config_start; + + if (start == FLASH_BANK1_BASE) { + *sector = FLASH_SECTOR_0; + *bank = FLASH_BANK_1; + } else { + // Not good + while (1) { + failureMode(FAILURE_CONFIG_STORE_FAILURE); + } + } +} +#elif defined(APM32F4) +/* +Sector 0 0x08000000 - 0x08003FFF 16 Kbytes +Sector 1 0x08004000 - 0x08007FFF 16 Kbytes +Sector 2 0x08008000 - 0x0800BFFF 16 Kbytes +Sector 3 0x0800C000 - 0x0800FFFF 16 Kbytes +Sector 4 0x08010000 - 0x0801FFFF 64 Kbytes +Sector 5 0x08020000 - 0x0803FFFF 128 Kbytes +Sector 6 0x08040000 - 0x0805FFFF 128 Kbytes +Sector 7 0x08060000 - 0x0807FFFF 128 Kbytes +Sector 8 0x08080000 - 0x0809FFFF 128 Kbytes +Sector 9 0x080A0000 - 0x080BFFFF 128 Kbytes +Sector 10 0x080C0000 - 0x080DFFFF 128 Kbytes +Sector 11 0x080E0000 - 0x080FFFFF 128 Kbytes +*/ + +uint32_t getFLASHSectorForEEPROM(void) +{ + if ((uint32_t)&__config_start <= 0x08003FFF) + return FLASH_SECTOR_0; + if ((uint32_t)&__config_start <= 0x08007FFF) + return FLASH_SECTOR_1; + if ((uint32_t)&__config_start <= 0x0800BFFF) + return FLASH_SECTOR_2; + if ((uint32_t)&__config_start <= 0x0800FFFF) + return FLASH_SECTOR_3; + if ((uint32_t)&__config_start <= 0x0801FFFF) + return FLASH_SECTOR_4; + if ((uint32_t)&__config_start <= 0x0803FFFF) + return FLASH_SECTOR_5; + if ((uint32_t)&__config_start <= 0x0805FFFF) + return FLASH_SECTOR_6; + if ((uint32_t)&__config_start <= 0x0807FFFF) + return FLASH_SECTOR_7; + if ((uint32_t)&__config_start <= 0x0809FFFF) + return FLASH_SECTOR_8; + if ((uint32_t)&__config_start <= 0x080DFFFF) + return FLASH_SECTOR_9; + if ((uint32_t)&__config_start <= 0x080BFFFF) + return FLASH_SECTOR_10; + if ((uint32_t)&__config_start <= 0x080FFFFF) + return FLASH_SECTOR_11; + + // Not good + while (1) { + failureMode(FAILURE_CONFIG_STORE_FAILURE); + } +} +#endif + +void configUnlock(void) +{ +#if defined(STM32F7) || defined(STM32H7) || defined(STM32G4) + HAL_FLASH_Unlock(); +#elif defined(APM32F4) + DAL_FLASH_Unlock(); +#elif defined(AT32F4) + flash_unlock(); +#else + FLASH_Unlock(); +#endif +} + +void configLock(void) +{ +#if defined(STM32F7) || defined(STM32H7) || defined(STM32G4) + HAL_FLASH_Lock(); +#elif defined(AT32F4) + flash_lock(); +#elif defined(APM32F4) + DAL_FLASH_Lock(); +#else + FLASH_Lock(); +#endif +} + +void configClearFlags(void) +{ +#if defined(STM32F4) + FLASH_ClearFlag(FLASH_FLAG_EOP | FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | FLASH_FLAG_PGPERR | FLASH_FLAG_PGSERR); +#elif defined(STM32F7) + // NOP +#elif defined(STM32H7) + // NOP +#elif defined(STM32G4) + // NOP +#elif defined(AT32F4) + flash_flag_clear(FLASH_ODF_FLAG | FLASH_PRGMERR_FLAG | FLASH_EPPERR_FLAG); +#elif defined(APM32F4) + __DAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | FLASH_FLAG_PGPERR | FLASH_FLAG_PGSERR); +#elif defined(UNIT_TEST) || defined(SIMULATOR_BUILD) + // NOP +#else +# error "Unsupported CPU" +#endif +} + +configStreamerResult_e configWriteWord(uintptr_t address, config_streamer_buffer_type_t *buffer) +{ +#if defined(STM32H7) + if (address % FLASH_PAGE_SIZE == 0) { + FLASH_EraseInitTypeDef EraseInitStruct = { + .TypeErase = FLASH_TYPEERASE_SECTORS, +#if !(defined(STM32H7A3xx) || defined(STM32H7A3xxQ)) + .VoltageRange = FLASH_VOLTAGE_RANGE_3, // 2.7-3.6V +#endif + .NbSectors = 1 + }; + getFLASHSectorForEEPROM(address, &EraseInitStruct.Banks, &EraseInitStruct.Sector); + uint32_t SECTORError; + const HAL_StatusTypeDef status = HAL_FLASHEx_Erase(&EraseInitStruct, &SECTORError); + if (status != HAL_OK) { + return CONFIG_RESULT_FAILURE; + } + } + + // For H7 + // HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint32_t DataAddress); + STATIC_ASSERT(CONFIG_STREAMER_BUFFER_SIZE == sizeof(uint32_t) * FLASH_NB_32BITWORD_IN_FLASHWORD, "CONFIG_STREAMER_BUFFER_SIZE does not match written size"); + const HAL_StatusTypeDef status = HAL_FLASH_Program(FLASH_TYPEPROGRAM_FLASHWORD, address, (uint32_t)buffer); + if (status != HAL_OK) { + return CONFIG_RESULT_ADDRESS_INVALID; + } +#elif defined(STM32F7) + if (address % FLASH_PAGE_SIZE == 0) { + FLASH_EraseInitTypeDef EraseInitStruct = { + .TypeErase = FLASH_TYPEERASE_SECTORS, + .VoltageRange = FLASH_VOLTAGE_RANGE_3, // 2.7-3.6V + .NbSectors = 1 + }; + EraseInitStruct.Sector = getFLASHSectorForEEPROM(); + uint32_t SECTORError; + const HAL_StatusTypeDef status = HAL_FLASHEx_Erase(&EraseInitStruct, &SECTORError); + if (status != HAL_OK) { + return CONFIG_RESULT_FAILURE; + } + } + + STATIC_ASSERT(CONFIG_STREAMER_BUFFER_SIZE == sizeof(uint32_t), "CONFIG_STREAMER_BUFFER_SIZE does not match written size"); + // For F7 + // HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data); + const HAL_StatusTypeDef status = HAL_FLASH_Program(FLASH_TYPEPROGRAM_WORD, address, *buffer); + if (status != HAL_OK) { + return CONFIG_RESULT_INCOMPLETE; + } +#elif defined(STM32G4) + if (address % FLASH_PAGE_SIZE == 0) { + + FLASH_EraseInitTypeDef EraseInitStruct = { + .TypeErase = FLASH_TYPEERASE_PAGES, + .NbPages = 1 + }; + getFLASHSectorForEEPROM(address, &EraseInitStruct.Banks, &EraseInitStruct.Page); + uint32_t SECTORError; + const HAL_StatusTypeDef status = HAL_FLASHEx_Erase(&EraseInitStruct, &SECTORError); + if (status != HAL_OK) { + return CONFIG_RESULT_FAILURE; + } + } + + STATIC_ASSERT(CONFIG_STREAMER_BUFFER_SIZE == sizeof(uint64_t), "CONFIG_STREAMER_BUFFER_SIZE does not match written size"); + const HAL_StatusTypeDef status = HAL_FLASH_Program(FLASH_TYPEPROGRAM_DOUBLEWORD, address, *buffer); + if (status != HAL_OK) { + return CONFIG_RESULT_ADDRESS_INVALID; + } +#elif defined(AT32F4) + if (address % FLASH_PAGE_SIZE == 0) { + const flash_status_type status = flash_sector_erase(address); + if (status != FLASH_OPERATE_DONE) { + return CONFIG_RESULT_FAILURE; + } + } + + STATIC_ASSERT(CONFIG_STREAMER_BUFFER_SIZE == sizeof(uint32_t), "CONFIG_STREAMER_BUFFER_SIZE does not match written size"); + const flash_status_type status = flash_word_program(address, *buffer); + if (status != FLASH_OPERATE_DONE) { + return CONFIG_RESULT_ADDRESS_INVALID; + } +#elif defined(APM32F4) + if (address % FLASH_PAGE_SIZE == 0) { + FLASH_EraseInitTypeDef EraseInitStruct = { + .TypeErase = FLASH_TYPEERASE_SECTORS, + .VoltageRange = FLASH_VOLTAGE_RANGE_3, // 2.7-3.6V + .NbSectors = 1 + }; + EraseInitStruct.Sector = getFLASHSectorForEEPROM(); + uint32_t SECTORError; + const DAL_StatusTypeDef status = DAL_FLASHEx_Erase(&EraseInitStruct, &SECTORError); + if (status != DAL_OK) { + return CONFIG_RESULT_FAILURE; + } + } + + STATIC_ASSERT(CONFIG_STREAMER_BUFFER_SIZE == sizeof(uint32_t), "CONFIG_STREAMER_BUFFER_SIZE does not match written size"); + const DAL_StatusTypeDef status = DAL_FLASH_Program(FLASH_TYPEPROGRAM_WORD, address, *buffer); + if (status != DAL_OK) { + return CONFIG_RESULT_ADDRESS_INVALID; + } +#elif defined(STM32F4) + if (address % FLASH_PAGE_SIZE == 0) { + const FLASH_Status status = FLASH_EraseSector(getFLASHSectorForEEPROM(), VoltageRange_3); //0x08080000 to 0x080A0000 + if (status != FLASH_COMPLETE) { + return CONFIG_RESULT_FAILURE; + } + } + + STATIC_ASSERT(CONFIG_STREAMER_BUFFER_SIZE == sizeof(uint32_t), "CONFIG_STREAMER_BUFFER_SIZE does not match written size"); + const FLASH_Status status = FLASH_ProgramWord(address, *buffer); + if (status != FLASH_COMPLETE) { + return CONFIG_RESULT_ADDRESS_INVALID; + } +#else +#error "MCU not catered for in configWriteWord for config_streamer" +#endif + return CONFIG_RESULT_SUCCESS; +} + +#endif // CONFIG_IN_FLASH From b1298262e1be09dc8b945b4340b02a39bc5b07bb Mon Sep 17 00:00:00 2001 From: Jay Blackman Date: Tue, 7 Jan 2025 11:27:38 +1100 Subject: [PATCH 028/244] FIX: Flash page size check is STM (or clone) specific (#14130) --- src/main/config/config_streamer.c | 4 ---- src/platform/common/stm32/config_flash.c | 4 ++++ 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/main/config/config_streamer.c b/src/main/config/config_streamer.c index d519d61b42..74961fb3c3 100644 --- a/src/main/config/config_streamer.c +++ b/src/main/config/config_streamer.c @@ -37,10 +37,6 @@ uint8_t eepromData[EEPROM_SIZE]; #endif #endif -#if !defined(FLASH_PAGE_SIZE) -#error "Flash page size not defined for target." -#endif - void config_streamer_init(config_streamer_t *c) { memset(c, 0, sizeof(*c)); diff --git a/src/platform/common/stm32/config_flash.c b/src/platform/common/stm32/config_flash.c index e1f6b484ed..c94fb082b1 100644 --- a/src/platform/common/stm32/config_flash.c +++ b/src/platform/common/stm32/config_flash.c @@ -27,6 +27,10 @@ #if defined(CONFIG_IN_FLASH) +#if !defined(FLASH_PAGE_SIZE) +#error "Flash page size not defined for STM (or clone) target." +#endif + #if defined(STM32F745xx) || defined(STM32F746xx) || defined(STM32F765xx) /* Sector 0 0x08000000 - 0x08007FFF 32 Kbytes From 4357ca36564455314604e50f747e223ee964f105 Mon Sep 17 00:00:00 2001 From: Jay Blackman Date: Wed, 8 Jan 2025 10:20:49 +1100 Subject: [PATCH 029/244] FIX: explicit specification of float (build for RPI) (#14132) --- src/main/flight/alt_hold_multirotor.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/flight/alt_hold_multirotor.c b/src/main/flight/alt_hold_multirotor.c index 7c089cb165..e1547638f7 100644 --- a/src/main/flight/alt_hold_multirotor.c +++ b/src/main/flight/alt_hold_multirotor.c @@ -128,7 +128,7 @@ void altHoldUpdateTargetAltitude(void) // using maxVelocity means the stick can bring altitude target to current within 1s // this constrains the P and I response to user target changes, but not D of F responses // Range is compared to distance that might be traveled in one second - if (fabsf(getAltitudeCm() - altHold.targetAltitudeCm) < altHold.maxVelocity * 1.0 /* s */) { + if (fabsf(getAltitudeCm() - altHold.targetAltitudeCm) < altHold.maxVelocity * 1.0f /* s */) { altHold.targetAltitudeCm += altHold.targetVelocity * taskIntervalSeconds; } } From 67bb6f88b7d606846ec98efb43e1bbe9b70398f2 Mon Sep 17 00:00:00 2001 From: Jay Blackman Date: Wed, 8 Jan 2025 10:25:34 +1100 Subject: [PATCH 030/244] FIX: Adding init for SPIDEV_0 (#14134) --- src/main/fc/init.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/main/fc/init.c b/src/main/fc/init.c index 67c21d7f20..e6e90800fe 100644 --- a/src/main/fc/init.c +++ b/src/main/fc/init.c @@ -211,6 +211,9 @@ static void configureSPIBusses(void) #ifdef USE_SPI spiPreinit(); +#ifdef USE_SPI_DEVICE_0 + spiInit(SPIDEV_0); +#endif #ifdef USE_SPI_DEVICE_1 spiInit(SPIDEV_1); #endif From a8d599e187904dcade6bad3f95f711b93f502a2b Mon Sep 17 00:00:00 2001 From: Jay Blackman Date: Fri, 10 Jan 2025 06:29:43 +1100 Subject: [PATCH 031/244] FIX: Adding USE_DMA wrapper around those only available with USE_DMA active (#14133) * FIX: Adding USE_DMA wrapper around those only available with USE_DMA active * Additional condition * Renaming to dmaInitRx and dmaInitTx --- src/main/drivers/bus.h | 18 +++--- src/main/drivers/bus_spi.c | 6 +- src/platform/APM32/bus_spi_apm32.c | 68 +++++++++++----------- src/platform/AT32/bus_spi_at32bsp.c | 64 ++++++++++----------- src/platform/STM32/bus_spi_ll.c | 80 +++++++++++++------------- src/platform/STM32/bus_spi_stdperiph.c | 74 ++++++++++++------------ 6 files changed, 156 insertions(+), 154 deletions(-) diff --git a/src/main/drivers/bus.h b/src/main/drivers/bus.h index 3c4801146a..1a35baad44 100644 --- a/src/main/drivers/bus.h +++ b/src/main/drivers/bus.h @@ -62,16 +62,16 @@ typedef struct busDevice_s { } busType_u; bool useDMA; uint8_t deviceCount; +#ifdef USE_DMA dmaChannelDescriptor_t *dmaTx; dmaChannelDescriptor_t *dmaRx; -#ifdef USE_DMA // Use a reference here as this saves RAM for unused descriptors #if defined(USE_FULL_LL_DRIVER) - LL_DMA_InitTypeDef *initTx; - LL_DMA_InitTypeDef *initRx; + LL_DMA_InitTypeDef *dmaInitTx; + LL_DMA_InitTypeDef *dmaInitRx; #else - DMA_InitTypeDef *initTx; - DMA_InitTypeDef *initRx; + DMA_InitTypeDef *dmaInitTx; + DMA_InitTypeDef *dmaInitRx; #endif #endif // USE_DMA volatile struct busSegment_s* volatile curSegment; @@ -97,11 +97,11 @@ typedef struct extDevice_s { #ifdef USE_DMA // Cache the init structure for the next DMA transfer to reduce inter-segment delay #if defined(USE_FULL_LL_DRIVER) - LL_DMA_InitTypeDef initTx; - LL_DMA_InitTypeDef initRx; + LL_DMA_InitTypeDef dmaInitTx; + LL_DMA_InitTypeDef dmaInitRx; #else - DMA_InitTypeDef initTx; - DMA_InitTypeDef initRx; + DMA_InitTypeDef dmaInitTx; + DMA_InitTypeDef dmaInitRx; #endif #endif // USE_DMA // Support disabling DMA on a per device basis diff --git a/src/main/drivers/bus_spi.c b/src/main/drivers/bus_spi.c index f9ebf24713..ae82bbcd63 100644 --- a/src/main/drivers/bus_spi.c +++ b/src/main/drivers/bus_spi.c @@ -365,8 +365,10 @@ bool spiSetBusInstance(extDevice_t *dev, uint32_t device) bus->busType = BUS_TYPE_SPI; bus->useDMA = false; bus->deviceCount = 1; - bus->initTx = &dev->initTx; - bus->initRx = &dev->initRx; +#ifdef USE_DMA + bus->dmaInitTx = &dev->dmaInitTx; + bus->dmaInitRx = &dev->dmaInitRx; +#endif return true; } diff --git a/src/platform/APM32/bus_spi_apm32.c b/src/platform/APM32/bus_spi_apm32.c index 831796331f..8f09a3489a 100644 --- a/src/platform/APM32/bus_spi_apm32.c +++ b/src/platform/APM32/bus_spi_apm32.c @@ -99,31 +99,31 @@ void spiInitDevice(SPIDevice device) void spiInternalResetDescriptors(busDevice_t *bus) { - DDL_DMA_InitTypeDef *initTx = bus->initTx; + DDL_DMA_InitTypeDef *dmaInitTx = bus->dmaInitTx; - DDL_DMA_StructInit(initTx); + DDL_DMA_StructInit(dmaInitTx); - initTx->Channel = bus->dmaTx->channel; - initTx->Mode = DDL_DMA_MODE_NORMAL; - initTx->Direction = DDL_DMA_DIRECTION_MEMORY_TO_PERIPH; - initTx->PeriphOrM2MSrcAddress = (uint32_t)&bus->busType_u.spi.instance->DATA; - initTx->Priority = DDL_DMA_PRIORITY_LOW; - initTx->PeriphOrM2MSrcIncMode = DDL_DMA_PERIPH_NOINCREMENT; - initTx->PeriphOrM2MSrcDataSize = DDL_DMA_PDATAALIGN_BYTE; - initTx->MemoryOrM2MDstDataSize = DDL_DMA_MDATAALIGN_BYTE; + dmaInitTx->Channel = bus->dmaTx->channel; + dmaInitTx->Mode = DDL_DMA_MODE_NORMAL; + dmaInitTx->Direction = DDL_DMA_DIRECTION_MEMORY_TO_PERIPH; + dmaInitTx->PeriphOrM2MSrcAddress = (uint32_t)&bus->busType_u.spi.instance->DATA; + dmaInitTx->Priority = DDL_DMA_PRIORITY_LOW; + dmaInitTx->PeriphOrM2MSrcIncMode = DDL_DMA_PERIPH_NOINCREMENT; + dmaInitTx->PeriphOrM2MSrcDataSize = DDL_DMA_PDATAALIGN_BYTE; + dmaInitTx->MemoryOrM2MDstDataSize = DDL_DMA_MDATAALIGN_BYTE; if (bus->dmaRx) { - DDL_DMA_InitTypeDef *initRx = bus->initRx; + DDL_DMA_InitTypeDef *dmaInitRx = bus->dmaInitRx; - DDL_DMA_StructInit(initRx); + DDL_DMA_StructInit(dmaInitRx); - initRx->Channel = bus->dmaRx->channel; - initRx->Mode = DDL_DMA_MODE_NORMAL; - initRx->Direction = DDL_DMA_DIRECTION_PERIPH_TO_MEMORY; - initRx->PeriphOrM2MSrcAddress = (uint32_t)&bus->busType_u.spi.instance->DATA; - initRx->Priority = DDL_DMA_PRIORITY_LOW; - initRx->PeriphOrM2MSrcIncMode = DDL_DMA_PERIPH_NOINCREMENT; - initRx->PeriphOrM2MSrcDataSize = DDL_DMA_PDATAALIGN_BYTE; + dmaInitRx->Channel = bus->dmaRx->channel; + dmaInitRx->Mode = DDL_DMA_MODE_NORMAL; + dmaInitRx->Direction = DDL_DMA_DIRECTION_PERIPH_TO_MEMORY; + dmaInitRx->PeriphOrM2MSrcAddress = (uint32_t)&bus->busType_u.spi.instance->DATA; + dmaInitRx->Priority = DDL_DMA_PRIORITY_LOW; + dmaInitRx->PeriphOrM2MSrcIncMode = DDL_DMA_PERIPH_NOINCREMENT; + dmaInitRx->PeriphOrM2MSrcDataSize = DDL_DMA_PDATAALIGN_BYTE; } } @@ -175,34 +175,34 @@ void spiInternalInitStream(const extDevice_t *dev, bool preInit) int len = segment->len; uint8_t *txData = segment->u.buffers.txData; - DDL_DMA_InitTypeDef *initTx = bus->initTx; + DDL_DMA_InitTypeDef *dmaInitTx = bus->dmaInitTx; if (txData) { - initTx->MemoryOrM2MDstAddress = (uint32_t)txData; - initTx->MemoryOrM2MDstIncMode = DDL_DMA_MEMORY_INCREMENT; + dmaInitTx->MemoryOrM2MDstAddress = (uint32_t)txData; + dmaInitTx->MemoryOrM2MDstIncMode = DDL_DMA_MEMORY_INCREMENT; } else { dummyTxByte = 0xff; - initTx->MemoryOrM2MDstAddress = (uint32_t)&dummyTxByte; - initTx->MemoryOrM2MDstIncMode = DDL_DMA_MEMORY_NOINCREMENT; + dmaInitTx->MemoryOrM2MDstAddress = (uint32_t)&dummyTxByte; + dmaInitTx->MemoryOrM2MDstIncMode = DDL_DMA_MEMORY_NOINCREMENT; } - initTx->NbData = len; + dmaInitTx->NbData = len; if (dev->bus->dmaRx) { uint8_t *rxData = segment->u.buffers.rxData; - DDL_DMA_InitTypeDef *initRx = bus->initRx; + DDL_DMA_InitTypeDef *dmaInitRx = bus->dmaInitRx; if (rxData) { /* Flush the D cache for the start and end of the receive buffer as * the cache will be invalidated after the transfer and any valid data * just before/after must be in memory at that point */ - initRx->MemoryOrM2MDstAddress = (uint32_t)rxData; - initRx->MemoryOrM2MDstIncMode = DDL_DMA_MEMORY_INCREMENT; + dmaInitRx->MemoryOrM2MDstAddress = (uint32_t)rxData; + dmaInitRx->MemoryOrM2MDstIncMode = DDL_DMA_MEMORY_INCREMENT; } else { - initRx->MemoryOrM2MDstAddress = (uint32_t)&dummyRxByte; - initRx->MemoryOrM2MDstIncMode = DDL_DMA_MEMORY_NOINCREMENT; + dmaInitRx->MemoryOrM2MDstAddress = (uint32_t)&dummyRxByte; + dmaInitRx->MemoryOrM2MDstIncMode = DDL_DMA_MEMORY_NOINCREMENT; } - initRx->NbData = len; + dmaInitRx->NbData = len; } } @@ -235,8 +235,8 @@ void spiInternalStartDMA(const extDevice_t *dev) DDL_EX_DMA_EnableIT_TC(streamRegsRx); // Update streams - DDL_DMA_Init(dmaTx->dma, dmaTx->stream, bus->initTx); - DDL_DMA_Init(dmaRx->dma, dmaRx->stream, bus->initRx); + DDL_DMA_Init(dmaTx->dma, dmaTx->stream, bus->dmaInitTx); + DDL_DMA_Init(dmaRx->dma, dmaRx->stream, bus->dmaInitRx); /* Note from AN4031 * @@ -265,7 +265,7 @@ void spiInternalStartDMA(const extDevice_t *dev) DDL_EX_DMA_EnableIT_TC(streamRegsTx); // Update streams - DDL_DMA_Init(dmaTx->dma, dmaTx->stream, bus->initTx); + DDL_DMA_Init(dmaTx->dma, dmaTx->stream, bus->dmaInitTx); /* Note from AN4031 * diff --git a/src/platform/AT32/bus_spi_at32bsp.c b/src/platform/AT32/bus_spi_at32bsp.c index d8978298db..b76303d5af 100644 --- a/src/platform/AT32/bus_spi_at32bsp.c +++ b/src/platform/AT32/bus_spi_at32bsp.c @@ -100,29 +100,29 @@ void spiInitDevice(SPIDevice device) void spiInternalResetDescriptors(busDevice_t *bus) { - dma_init_type *initTx = bus->initTx; + dma_init_type *dmaInitTx = bus->dmaInitTx; - dma_default_para_init(initTx); + dma_default_para_init(dmaInitTx); - initTx->direction=DMA_DIR_MEMORY_TO_PERIPHERAL; - initTx->loop_mode_enable=FALSE; - initTx->peripheral_base_addr=(uint32_t)&bus->busType_u.spi.instance->dt ; - initTx->priority =DMA_PRIORITY_LOW; - initTx->peripheral_inc_enable =FALSE; - initTx->peripheral_data_width = DMA_PERIPHERAL_DATA_WIDTH_BYTE; - initTx->memory_data_width = DMA_MEMORY_DATA_WIDTH_BYTE; + dmaInitTx->direction=DMA_DIR_MEMORY_TO_PERIPHERAL; + dmaInitTx->loop_mode_enable=FALSE; + dmaInitTx->peripheral_base_addr=(uint32_t)&bus->busType_u.spi.instance->dt ; + dmaInitTx->priority =DMA_PRIORITY_LOW; + dmaInitTx->peripheral_inc_enable =FALSE; + dmaInitTx->peripheral_data_width = DMA_PERIPHERAL_DATA_WIDTH_BYTE; + dmaInitTx->memory_data_width = DMA_MEMORY_DATA_WIDTH_BYTE; if (bus->dmaRx) { - dma_init_type *initRx = bus->initRx; + dma_init_type *dmaInitRx = bus->dmaInitRx; - dma_default_para_init(initRx); + dma_default_para_init(dmaInitRx); - initRx->direction = DMA_DIR_PERIPHERAL_TO_MEMORY; - initRx->loop_mode_enable = FALSE; - initRx->peripheral_base_addr = (uint32_t)&bus->busType_u.spi.instance->dt; - initRx->priority = DMA_PRIORITY_LOW; - initRx->peripheral_inc_enable = FALSE; - initRx->peripheral_data_width = DMA_PERIPHERAL_DATA_WIDTH_BYTE; + dmaInitRx->direction = DMA_DIR_PERIPHERAL_TO_MEMORY; + dmaInitRx->loop_mode_enable = FALSE; + dmaInitRx->peripheral_base_addr = (uint32_t)&bus->busType_u.spi.instance->dt; + dmaInitRx->priority = DMA_PRIORITY_LOW; + dmaInitRx->peripheral_inc_enable = FALSE; + dmaInitRx->peripheral_data_width = DMA_PERIPHERAL_DATA_WIDTH_BYTE; } } @@ -175,31 +175,31 @@ void spiInternalInitStream(const extDevice_t *dev, bool preInit) int len = segment->len; uint8_t *txData = segment->u.buffers.txData; - dma_init_type *initTx = bus->initTx; + dma_init_type *dmaInitTx = bus->dmaInitTx; if (txData) { - initTx->memory_base_addr = (uint32_t)txData; - initTx->memory_inc_enable =TRUE; + dmaInitTx->memory_base_addr = (uint32_t)txData; + dmaInitTx->memory_inc_enable =TRUE; } else { dummyTxByte = 0xff; - initTx->memory_base_addr = (uint32_t)&dummyTxByte; - initTx->memory_inc_enable =FALSE; + dmaInitTx->memory_base_addr = (uint32_t)&dummyTxByte; + dmaInitTx->memory_inc_enable =FALSE; } - initTx->buffer_size =len; + dmaInitTx->buffer_size =len; if (dev->bus->dmaRx) { uint8_t *rxData = segment->u.buffers.rxData; - dma_init_type *initRx = bus->initRx; + dma_init_type *dmaInitRx = bus->dmaInitRx; if (rxData) { - initRx->memory_base_addr= (uint32_t)rxData; - initRx->memory_inc_enable = TRUE; + dmaInitRx->memory_base_addr= (uint32_t)rxData; + dmaInitRx->memory_inc_enable = TRUE; } else { - initRx->memory_base_addr = (uint32_t)&dummyRxByte; - initRx->memory_inc_enable = FALSE; + dmaInitRx->memory_base_addr = (uint32_t)&dummyRxByte; + dmaInitRx->memory_inc_enable = FALSE; } - initRx->buffer_size = len; + dmaInitRx->buffer_size = len; } } @@ -229,8 +229,8 @@ void spiInternalStartDMA(const extDevice_t *dev) xDMA_ITConfig(streamRegsRx, DMA_IT_TCIF, TRUE); // Update streams - xDMA_Init(streamRegsTx, dev->bus->initTx); - xDMA_Init(streamRegsRx, dev->bus->initRx); + xDMA_Init(streamRegsTx, dev->bus->dmaInitTx); + xDMA_Init(streamRegsRx, dev->bus->dmaInitRx); // Enable streams xDMA_Cmd(streamRegsRx, TRUE); @@ -253,7 +253,7 @@ void spiInternalStartDMA(const extDevice_t *dev) xDMA_Cmd(streamRegsTx, FALSE); // Update stream - xDMA_Init(streamRegsTx, dev->bus->initTx); + xDMA_Init(streamRegsTx, dev->bus->dmaInitTx); // Enable stream xDMA_Cmd(streamRegsTx, TRUE); diff --git a/src/platform/STM32/bus_spi_ll.c b/src/platform/STM32/bus_spi_ll.c index da00e15d3f..77707ad260 100644 --- a/src/platform/STM32/bus_spi_ll.c +++ b/src/platform/STM32/bus_spi_ll.c @@ -146,45 +146,45 @@ void spiInitDevice(SPIDevice device) void spiInternalResetDescriptors(busDevice_t *bus) { - LL_DMA_InitTypeDef *initTx = bus->initTx; + LL_DMA_InitTypeDef *dmaInitTx = bus->dmaInitTx; - LL_DMA_StructInit(initTx); + LL_DMA_StructInit(dmaInitTx); #if defined(STM32G4) || defined(STM32H7) - initTx->PeriphRequest = bus->dmaTx->channel; + dmaInitTx->PeriphRequest = bus->dmaTx->channel; #else - initTx->Channel = bus->dmaTx->channel; + dmaInitTx->Channel = bus->dmaTx->channel; #endif - initTx->Mode = LL_DMA_MODE_NORMAL; - initTx->Direction = LL_DMA_DIRECTION_MEMORY_TO_PERIPH; + dmaInitTx->Mode = LL_DMA_MODE_NORMAL; + dmaInitTx->Direction = LL_DMA_DIRECTION_MEMORY_TO_PERIPH; #if defined(STM32H7) - initTx->PeriphOrM2MSrcAddress = (uint32_t)&bus->busType_u.spi.instance->TXDR; + dmaInitTx->PeriphOrM2MSrcAddress = (uint32_t)&bus->busType_u.spi.instance->TXDR; #else - initTx->PeriphOrM2MSrcAddress = (uint32_t)&bus->busType_u.spi.instance->DR; + dmaInitTx->PeriphOrM2MSrcAddress = (uint32_t)&bus->busType_u.spi.instance->DR; #endif - initTx->Priority = LL_DMA_PRIORITY_LOW; - initTx->PeriphOrM2MSrcIncMode = LL_DMA_PERIPH_NOINCREMENT; - initTx->PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_BYTE; - initTx->MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_BYTE; + dmaInitTx->Priority = LL_DMA_PRIORITY_LOW; + dmaInitTx->PeriphOrM2MSrcIncMode = LL_DMA_PERIPH_NOINCREMENT; + dmaInitTx->PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_BYTE; + dmaInitTx->MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_BYTE; if (bus->dmaRx) { - LL_DMA_InitTypeDef *initRx = bus->initRx; + LL_DMA_InitTypeDef *dmaInitRx = bus->dmaInitRx; - LL_DMA_StructInit(initRx); + LL_DMA_StructInit(dmaInitRx); #if defined(STM32G4) || defined(STM32H7) - initRx->PeriphRequest = bus->dmaRx->channel; + dmaInitRx->PeriphRequest = bus->dmaRx->channel; #else - initRx->Channel = bus->dmaRx->channel; + dmaInitRx->Channel = bus->dmaRx->channel; #endif - initRx->Mode = LL_DMA_MODE_NORMAL; - initRx->Direction = LL_DMA_DIRECTION_PERIPH_TO_MEMORY; + dmaInitRx->Mode = LL_DMA_MODE_NORMAL; + dmaInitRx->Direction = LL_DMA_DIRECTION_PERIPH_TO_MEMORY; #if defined(STM32H7) - initRx->PeriphOrM2MSrcAddress = (uint32_t)&bus->busType_u.spi.instance->RXDR; + dmaInitRx->PeriphOrM2MSrcAddress = (uint32_t)&bus->busType_u.spi.instance->RXDR; #else - initRx->PeriphOrM2MSrcAddress = (uint32_t)&bus->busType_u.spi.instance->DR; + dmaInitRx->PeriphOrM2MSrcAddress = (uint32_t)&bus->busType_u.spi.instance->DR; #endif - initRx->Priority = LL_DMA_PRIORITY_LOW; - initRx->PeriphOrM2MSrcIncMode = LL_DMA_PERIPH_NOINCREMENT; - initRx->PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_BYTE; + dmaInitRx->Priority = LL_DMA_PRIORITY_LOW; + dmaInitRx->PeriphOrM2MSrcIncMode = LL_DMA_PERIPH_NOINCREMENT; + dmaInitRx->PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_BYTE; } } @@ -285,7 +285,7 @@ void spiInternalInitStream(const extDevice_t *dev, bool preInit) int len = segment->len; uint8_t *txData = segment->u.buffers.txData; - LL_DMA_InitTypeDef *initTx = bus->initTx; + LL_DMA_InitTypeDef *dmaInitTx = bus->dmaInitTx; if (txData) { #ifdef __DCACHE_PRESENT @@ -301,19 +301,19 @@ void spiInternalInitStream(const extDevice_t *dev, bool preInit) (((uint32_t)txData & CACHE_LINE_MASK) + len - 1 + CACHE_LINE_SIZE) & ~CACHE_LINE_MASK); } #endif // __DCACHE_PRESENT - initTx->MemoryOrM2MDstAddress = (uint32_t)txData; - initTx->MemoryOrM2MDstIncMode = LL_DMA_MEMORY_INCREMENT; + dmaInitTx->MemoryOrM2MDstAddress = (uint32_t)txData; + dmaInitTx->MemoryOrM2MDstIncMode = LL_DMA_MEMORY_INCREMENT; } else { - initTx->MemoryOrM2MDstAddress = (uint32_t)&dummyTxByte; - initTx->MemoryOrM2MDstIncMode = LL_DMA_MEMORY_NOINCREMENT; + dmaInitTx->MemoryOrM2MDstAddress = (uint32_t)&dummyTxByte; + dmaInitTx->MemoryOrM2MDstIncMode = LL_DMA_MEMORY_NOINCREMENT; } - initTx->NbData = len; + dmaInitTx->NbData = len; #if !defined(STM32G4) && !defined(STM32H7) if (dev->bus->dmaRx) { #endif uint8_t *rxData = segment->u.buffers.rxData; - LL_DMA_InitTypeDef *initRx = bus->initRx; + LL_DMA_InitTypeDef *dmaInitRx = bus->dmaInitRx; if (rxData) { /* Flush the D cache for the start and end of the receive buffer as @@ -333,13 +333,13 @@ void spiInternalInitStream(const extDevice_t *dev, bool preInit) (((uint32_t)rxData & CACHE_LINE_MASK) + len - 1 + CACHE_LINE_SIZE) & ~CACHE_LINE_MASK); } #endif // __DCACHE_PRESENT - initRx->MemoryOrM2MDstAddress = (uint32_t)rxData; - initRx->MemoryOrM2MDstIncMode = LL_DMA_MEMORY_INCREMENT; + dmaInitRx->MemoryOrM2MDstAddress = (uint32_t)rxData; + dmaInitRx->MemoryOrM2MDstIncMode = LL_DMA_MEMORY_INCREMENT; } else { - initRx->MemoryOrM2MDstAddress = (uint32_t)&dummyRxByte; - initRx->MemoryOrM2MDstIncMode = LL_DMA_MEMORY_NOINCREMENT; + dmaInitRx->MemoryOrM2MDstAddress = (uint32_t)&dummyRxByte; + dmaInitRx->MemoryOrM2MDstIncMode = LL_DMA_MEMORY_NOINCREMENT; } - initRx->NbData = len; + dmaInitRx->NbData = len; #if !defined(STM32G4) && !defined(STM32H7) } #endif @@ -373,8 +373,8 @@ void spiInternalStartDMA(const extDevice_t *dev) LL_DMA_EnableIT_TC(dmaRx->dma, dmaRx->stream); // Update channels - LL_DMA_Init(dmaTx->dma, dmaTx->stream, bus->initTx); - LL_DMA_Init(dmaRx->dma, dmaRx->stream, bus->initRx); + LL_DMA_Init(dmaTx->dma, dmaTx->stream, bus->dmaInitTx); + LL_DMA_Init(dmaRx->dma, dmaRx->stream, bus->dmaInitRx); // Enable channels LL_DMA_EnableChannel(dmaTx->dma, dmaTx->stream); @@ -395,8 +395,8 @@ void spiInternalStartDMA(const extDevice_t *dev) LL_EX_DMA_EnableIT_TC(streamRegsRx); // Update streams - LL_DMA_Init(dmaTx->dma, dmaTx->stream, bus->initTx); - LL_DMA_Init(dmaRx->dma, dmaRx->stream, bus->initRx); + LL_DMA_Init(dmaTx->dma, dmaTx->stream, bus->dmaInitTx); + LL_DMA_Init(dmaRx->dma, dmaRx->stream, bus->dmaInitRx); /* Note from AN4031 * @@ -436,7 +436,7 @@ void spiInternalStartDMA(const extDevice_t *dev) LL_EX_DMA_EnableIT_TC(streamRegsTx); // Update streams - LL_DMA_Init(dmaTx->dma, dmaTx->stream, bus->initTx); + LL_DMA_Init(dmaTx->dma, dmaTx->stream, bus->dmaInitTx); /* Note from AN4031 * diff --git a/src/platform/STM32/bus_spi_stdperiph.c b/src/platform/STM32/bus_spi_stdperiph.c index 04a8e63af7..7b74aa6b0f 100644 --- a/src/platform/STM32/bus_spi_stdperiph.c +++ b/src/platform/STM32/bus_spi_stdperiph.c @@ -106,29 +106,29 @@ void spiInitDevice(SPIDevice device) void spiInternalResetDescriptors(busDevice_t *bus) { - DMA_InitTypeDef *initTx = bus->initTx; + DMA_InitTypeDef *dmaInitTx = bus->dmaInitTx; - DMA_StructInit(initTx); - initTx->DMA_Channel = bus->dmaTx->channel; - initTx->DMA_DIR = DMA_DIR_MemoryToPeripheral; - initTx->DMA_Mode = DMA_Mode_Normal; - initTx->DMA_PeripheralBaseAddr = (uint32_t)&bus->busType_u.spi.instance->DR; - initTx->DMA_Priority = DMA_Priority_Low; - initTx->DMA_PeripheralInc = DMA_PeripheralInc_Disable; - initTx->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte; - initTx->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; + DMA_StructInit(dmaInitTx); + dmaInitTx->DMA_Channel = bus->dmaTx->channel; + dmaInitTx->DMA_DIR = DMA_DIR_MemoryToPeripheral; + dmaInitTx->DMA_Mode = DMA_Mode_Normal; + dmaInitTx->DMA_PeripheralBaseAddr = (uint32_t)&bus->busType_u.spi.instance->DR; + dmaInitTx->DMA_Priority = DMA_Priority_Low; + dmaInitTx->DMA_PeripheralInc = DMA_PeripheralInc_Disable; + dmaInitTx->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte; + dmaInitTx->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; if (bus->dmaRx) { - DMA_InitTypeDef *initRx = bus->initRx; + DMA_InitTypeDef *dmaInitRx = bus->dmaInitRx; - DMA_StructInit(initRx); - initRx->DMA_Channel = bus->dmaRx->channel; - initRx->DMA_DIR = DMA_DIR_PeripheralToMemory; - initRx->DMA_Mode = DMA_Mode_Normal; - initRx->DMA_PeripheralBaseAddr = (uint32_t)&bus->busType_u.spi.instance->DR; - initRx->DMA_Priority = DMA_Priority_Low; - initRx->DMA_PeripheralInc = DMA_PeripheralInc_Disable; - initRx->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte; + DMA_StructInit(dmaInitRx); + dmaInitRx->DMA_Channel = bus->dmaRx->channel; + dmaInitRx->DMA_DIR = DMA_DIR_PeripheralToMemory; + dmaInitRx->DMA_Mode = DMA_Mode_Normal; + dmaInitRx->DMA_PeripheralBaseAddr = (uint32_t)&bus->busType_u.spi.instance->DR; + dmaInitRx->DMA_Priority = DMA_Priority_Low; + dmaInitRx->DMA_PeripheralInc = DMA_PeripheralInc_Disable; + dmaInitRx->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte; } } @@ -182,36 +182,36 @@ void spiInternalInitStream(const extDevice_t *dev, bool preInit) int len = segment->len; uint8_t *txData = segment->u.buffers.txData; - DMA_InitTypeDef *initTx = bus->initTx; + DMA_InitTypeDef *dmaInitTx = bus->dmaInitTx; if (txData) { - initTx->DMA_Memory0BaseAddr = (uint32_t)txData; - initTx->DMA_MemoryInc = DMA_MemoryInc_Enable; + dmaInitTx->DMA_Memory0BaseAddr = (uint32_t)txData; + dmaInitTx->DMA_MemoryInc = DMA_MemoryInc_Enable; } else { dummyTxByte = 0xff; - initTx->DMA_Memory0BaseAddr = (uint32_t)&dummyTxByte; - initTx->DMA_MemoryInc = DMA_MemoryInc_Disable; + dmaInitTx->DMA_Memory0BaseAddr = (uint32_t)&dummyTxByte; + dmaInitTx->DMA_MemoryInc = DMA_MemoryInc_Disable; } - initTx->DMA_BufferSize = len; + dmaInitTx->DMA_BufferSize = len; if (dev->bus->dmaRx) { uint8_t *rxData = segment->u.buffers.rxData; - DMA_InitTypeDef *initRx = bus->initRx; + DMA_InitTypeDef *dmaInitRx = bus->dmaInitRx; if (rxData) { - initRx->DMA_Memory0BaseAddr = (uint32_t)rxData; - initRx->DMA_MemoryInc = DMA_MemoryInc_Enable; + dmaInitRx->DMA_Memory0BaseAddr = (uint32_t)rxData; + dmaInitRx->DMA_MemoryInc = DMA_MemoryInc_Enable; } else { - initRx->DMA_Memory0BaseAddr = (uint32_t)&dummyRxByte; - initRx->DMA_MemoryInc = DMA_MemoryInc_Disable; + dmaInitRx->DMA_Memory0BaseAddr = (uint32_t)&dummyRxByte; + dmaInitRx->DMA_MemoryInc = DMA_MemoryInc_Disable; } // If possible use 16 bit memory writes to prevent atomic access issues on gyro data - if ((initRx->DMA_Memory0BaseAddr & 0x1) || (len & 0x1)) { - initRx->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; + if ((dmaInitRx->DMA_Memory0BaseAddr & 0x1) || (len & 0x1)) { + dmaInitRx->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; } else { - initRx->DMA_MemoryDataSize = DMA_MemoryDataSize_HalfWord; + dmaInitRx->DMA_MemoryDataSize = DMA_MemoryDataSize_HalfWord; } - initRx->DMA_BufferSize = len; + dmaInitRx->DMA_BufferSize = len; } } @@ -240,8 +240,8 @@ void spiInternalStartDMA(const extDevice_t *dev) DMA_ITConfig(streamRegsRx, DMA_IT_TC, ENABLE); // Update streams - DMA_Init(streamRegsTx, dev->bus->initTx); - DMA_Init(streamRegsRx, dev->bus->initRx); + DMA_Init(streamRegsTx, dev->bus->dmaInitTx); + DMA_Init(streamRegsRx, dev->bus->dmaInitRx); /* Note from AN4031 * @@ -269,7 +269,7 @@ void spiInternalStartDMA(const extDevice_t *dev) DMA_ITConfig(streamRegsTx, DMA_IT_TC, ENABLE); // Update stream - DMA_Init(streamRegsTx, dev->bus->initTx); + DMA_Init(streamRegsTx, dev->bus->dmaInitTx); /* Note from AN4031 * From 51c09efe6970b0f2b5cabc83821972e8bc326093 Mon Sep 17 00:00:00 2001 From: Mark Haslinghuis Date: Thu, 9 Jan 2025 22:41:41 +0100 Subject: [PATCH 032/244] Add gyro and magnetic custom alignment to MSP (#14019) * Add magnetic dip and alignment to MSP * Update PG * Revert inclination addition * Revert heading units * space * Use MSP_SENSOR_ALIGNMENT * Missed bracket * Adjust mag_declination range * Add gyro custom alignment * Remove precision from declination * Revert remove precision from declination --- src/main/cli/settings.c | 2 +- src/main/fc/parameter_names.h | 1 + src/main/flight/imu.c | 2 +- src/main/flight/imu.h | 3 +- src/main/msp/msp.c | 57 ++++++++++++++++++++++++++++++++++- 5 files changed, 60 insertions(+), 5 deletions(-) diff --git a/src/main/cli/settings.c b/src/main/cli/settings.c index 9a9a749093..ebc5b894e4 100644 --- a/src/main/cli/settings.c +++ b/src/main/cli/settings.c @@ -1081,7 +1081,7 @@ const clivalue_t valueTable[] = { { PARAM_NAME_IMU_SMALL_ANGLE, VAR_UINT8 | MASTER_VALUE, .config.minmaxUnsigned = { 0, 180 }, PG_IMU_CONFIG, offsetof(imuConfig_t, small_angle) }, { PARAM_NAME_IMU_PROCESS_DENOM, VAR_UINT8 | MASTER_VALUE, .config.minmaxUnsigned = { 1, 4 }, PG_IMU_CONFIG, offsetof(imuConfig_t, imu_process_denom) }, #ifdef USE_MAG - { PARAM_NAME_IMU_MAG_DECLINATION, VAR_UINT16 | MASTER_VALUE, .config.minmaxUnsigned = { 0, 3599 }, PG_IMU_CONFIG, offsetof(imuConfig_t, mag_declination) }, + { PARAM_NAME_IMU_MAG_DECLINATION, VAR_INT16 | MASTER_VALUE, .config.minmaxUnsigned = { -300, 300 }, PG_IMU_CONFIG, offsetof(imuConfig_t, mag_declination) }, #endif // PG_ARMING_CONFIG diff --git a/src/main/fc/parameter_names.h b/src/main/fc/parameter_names.h index 930a8ee9e2..43624e06ea 100644 --- a/src/main/fc/parameter_names.h +++ b/src/main/fc/parameter_names.h @@ -262,6 +262,7 @@ #define PARAM_NAME_IMU_DCM_KI "imu_dcm_ki" #define PARAM_NAME_IMU_SMALL_ANGLE "small_angle" #define PARAM_NAME_IMU_PROCESS_DENOM "imu_process_denom" + #ifdef USE_MAG #define PARAM_NAME_IMU_MAG_DECLINATION "mag_declination" #endif diff --git a/src/main/flight/imu.c b/src/main/flight/imu.c index e353ae3b84..014052cf56 100644 --- a/src/main/flight/imu.c +++ b/src/main/flight/imu.c @@ -125,7 +125,7 @@ PG_RESET_TEMPLATE(imuConfig_t, imuConfig, .imu_dcm_ki = 0, // 0.003 * 10000 .small_angle = DEFAULT_SMALL_ANGLE, .imu_process_denom = 2, - .mag_declination = 0 + .mag_declination = 0, ); static void imuQuaternionComputeProducts(quaternion_t *quat, quaternionProducts *quatProd) diff --git a/src/main/flight/imu.h b/src/main/flight/imu.h index 3ab4f3cbd6..ef0d297233 100644 --- a/src/main/flight/imu.h +++ b/src/main/flight/imu.h @@ -63,7 +63,7 @@ typedef struct imuConfig_s { uint16_t imu_dcm_ki; // DCM filter integral gain ( x 10000) uint8_t small_angle; uint8_t imu_process_denom; - uint16_t mag_declination; // Magnetic declination in degrees * 10 + int16_t mag_declination; // Magnetic declination in degrees * 10 } imuConfig_t; PG_DECLARE(imuConfig_t, imuConfig); @@ -92,5 +92,4 @@ void imuSetHasNewData(uint32_t dt); bool imuQuaternionHeadfreeOffsetSet(void); void imuQuaternionHeadfreeTransformVectorEarthToBody(vector3_t *v); -bool shouldInitializeGPSHeading(void); bool isUpright(void); diff --git a/src/main/msp/msp.c b/src/main/msp/msp.c index d0bf9e563a..891a5cf7da 100644 --- a/src/main/msp/msp.c +++ b/src/main/msp/msp.c @@ -1847,7 +1847,33 @@ case MSP_NAME: sbufWriteU8(dst, gyroDeviceConfig(0)->alignment); sbufWriteU8(dst, ALIGN_DEFAULT); #endif + // Added in MSP API 1.47 + switch (gyroConfig()->gyro_to_use) { +#ifdef USE_MULTI_GYRO + case GYRO_CONFIG_USE_GYRO_2: + sbufWriteU16(dst, gyroDeviceConfig(1)->customAlignment.roll); + sbufWriteU16(dst, gyroDeviceConfig(1)->customAlignment.pitch); + sbufWriteU16(dst, gyroDeviceConfig(1)->customAlignment.yaw); + break; +#endif + case GYRO_CONFIG_USE_GYRO_BOTH: + // for dual-gyro in "BOTH" mode we only read/write gyro 0 + default: + sbufWriteU16(dst, gyroDeviceConfig(0)->customAlignment.roll); + sbufWriteU16(dst, gyroDeviceConfig(0)->customAlignment.pitch); + sbufWriteU16(dst, gyroDeviceConfig(0)->customAlignment.yaw); + break; + } +#ifdef USE_MAG + sbufWriteU16(dst, compassConfig()->mag_customAlignment.roll); + sbufWriteU16(dst, compassConfig()->mag_customAlignment.pitch); + sbufWriteU16(dst, compassConfig()->mag_customAlignment.yaw); +#else + sbufWriteU16(dst, 0); + sbufWriteU16(dst, 0); + sbufWriteU16(dst, 0); +#endif break; } case MSP_ADVANCED_CONFIG: @@ -3024,7 +3050,36 @@ static mspResult_e mspProcessInCommand(mspDescriptor_t srcDesc, int16_t cmdMSP, #else gyroDeviceConfigMutable(0)->alignment = gyroAlignment; #endif - + } + // Added in API 1.47 + if (sbufBytesRemaining(src) >= 6) { + switch (gyroConfig()->gyro_to_use) { +#ifdef USE_MULTI_GYRO + case GYRO_CONFIG_USE_GYRO_2: + gyroDeviceConfigMutable(1)->customAlignment.roll = sbufReadU16(src); + gyroDeviceConfigMutable(1)->customAlignment.pitch = sbufReadU16(src); + gyroDeviceConfigMutable(1)->customAlignment.yaw = sbufReadU16(src); + break; +#endif + case GYRO_CONFIG_USE_GYRO_BOTH: + // For dual-gyro in "BOTH" mode we'll only update gyro 0 + default: + gyroDeviceConfigMutable(0)->customAlignment.roll = sbufReadU16(src); + gyroDeviceConfigMutable(0)->customAlignment.pitch = sbufReadU16(src); + gyroDeviceConfigMutable(0)->customAlignment.yaw = sbufReadU16(src); + break; + } + } + if (sbufBytesRemaining(src) >= 6) { +#ifdef USE_MAG + compassConfigMutable()->mag_customAlignment.roll = sbufReadU16(src); + compassConfigMutable()->mag_customAlignment.pitch = sbufReadU16(src); + compassConfigMutable()->mag_customAlignment.yaw = sbufReadU16(src); +#else + sbufReadU16(src); + sbufReadU16(src); + sbufReadU16(src); +#endif } break; } From 4069fde56ed694075412d417a32823dbecac83fa Mon Sep 17 00:00:00 2001 From: Jay Blackman Date: Fri, 10 Jan 2025 16:13:15 +1100 Subject: [PATCH 033/244] Move STM (and clone) related UART implementation to platform (#14128) --- mk/source.mk | 1 - src/main/drivers/serial_uart.c | 122 +----------------- src/main/drivers/serial_uart_impl.h | 106 +-------------- src/main/drivers/serial_usb_vcp.h | 13 -- src/platform/APM32/mk/APM32F4.mk | 2 + src/platform/APM32/platform_mcu.h | 12 ++ src/platform/AT32/mk/AT32F4.mk | 1 + src/platform/AT32/platform_mcu.h | 17 ++- src/platform/STM32/mk/STM32_COMMON.mk | 3 +- src/platform/STM32/platform_mcu.h | 53 +++++++- .../STM32/vcp_hal/usbd_cdc_interface.h | 1 + .../common/stm32}/serial_uart_hw.c | 108 +++++++++++++++- 12 files changed, 201 insertions(+), 238 deletions(-) rename src/{main/drivers => platform/common/stm32}/serial_uart_hw.c (65%) diff --git a/mk/source.mk b/mk/source.mk index a9a8ed0e49..9b981c05cb 100644 --- a/mk/source.mk +++ b/mk/source.mk @@ -112,7 +112,6 @@ COMMON_SRC = \ drivers/resource.c \ drivers/serial.c \ drivers/serial_impl.c \ - drivers/serial_uart_hw.c \ drivers/sound_beeper.c \ drivers/stack_check.c \ drivers/timer_common.c \ diff --git a/src/main/drivers/serial_uart.c b/src/main/drivers/serial_uart.c index d4c530d889..4e99137a6e 100644 --- a/src/main/drivers/serial_uart.c +++ b/src/main/drivers/serial_uart.c @@ -50,19 +50,7 @@ #include "pg/serial_uart.h" -#if defined(STM32H7) -#define UART_TX_BUFFER_ATTRIBUTE DMA_RAM // D2 SRAM -#define UART_RX_BUFFER_ATTRIBUTE DMA_RAM // D2 SRAM -#elif defined(STM32G4) -#define UART_TX_BUFFER_ATTRIBUTE DMA_RAM_W // SRAM MPU NOT_BUFFERABLE -#define UART_RX_BUFFER_ATTRIBUTE DMA_RAM_R // SRAM MPU NOT CACHABLE -#elif defined(STM32F7) -#define UART_TX_BUFFER_ATTRIBUTE FAST_DATA_ZERO_INIT // DTCM RAM -#define UART_RX_BUFFER_ATTRIBUTE FAST_DATA_ZERO_INIT // DTCM RAM -#elif defined(STM32F4) || defined(AT32F4) || defined(APM32F4) -#define UART_TX_BUFFER_ATTRIBUTE // NONE -#define UART_RX_BUFFER_ATTRIBUTE // NONE -#else +#if !defined(UART_TX_BUFFER_ATTRIBUTE) || !defined(UART_RX_BUFFER_ATTRIBUTE) #error Undefined UART_{TX,RX}_BUFFER_ATTRIBUTE for this MCU #endif @@ -377,13 +365,7 @@ static void uartWrite(serialPort_t *instance, uint8_t ch) } else #endif { -#if defined(USE_HAL_DRIVER) - __HAL_UART_ENABLE_IT(&uartPort->Handle, UART_IT_TXE); -#elif defined(USE_ATBSP_DRIVER) - usart_interrupt_enable(uartPort->USARTx, USART_TDBE_INT, TRUE); -#else - USART_ITConfig(uartPort->USARTx, USART_IT_TXE, ENABLE); -#endif + uartEnableTxInterrupt(uartPort); } } @@ -442,13 +424,7 @@ static void uartEndWrite(serialPort_t *instance) } else #endif { -#if defined(USE_HAL_DRIVER) - __HAL_UART_ENABLE_IT(&uartPort->Handle, UART_IT_TXE); -#elif defined(USE_ATBSP_DRIVER) - usart_interrupt_enable(uartPort->USARTx, USART_TDBE_INT, TRUE); -#else - USART_ITConfig(uartPort->USARTx, USART_IT_TXE, ENABLE); -#endif + uartEnableTxInterrupt(uartPort); } } @@ -469,98 +445,6 @@ const struct serialPortVTable uartVTable[] = { } }; -// TODO - move to serial_uart_hw.c -#ifdef USE_DMA -void uartConfigureDma(uartDevice_t *uartdev) -{ - uartPort_t *uartPort = &(uartdev->port); - const uartHardware_t *hardware = uartdev->hardware; - -#ifdef USE_DMA_SPEC - const serialPortIdentifier_e uartPortIdentifier = hardware->identifier; - const uartDeviceIdx_e uartDeviceIdx = uartDeviceIdxFromIdentifier(uartPortIdentifier); - if (uartDeviceIdx == UARTDEV_INVALID) { - return; - } - const int resourceIdx = serialResourceIndex(uartPortIdentifier); - const int ownerIndex = serialOwnerIndex(uartPortIdentifier); - const resourceOwner_e ownerTxRx = serialOwnerTxRx(uartPortIdentifier); // rx is always +1 - - const dmaChannelSpec_t *dmaChannelSpec; - const serialUartConfig_t *cfg = serialUartConfig(resourceIdx); - if (!cfg) { - return; - } - if (cfg->txDmaopt != DMA_OPT_UNUSED) { - dmaChannelSpec = dmaGetChannelSpecByPeripheral(DMA_PERIPH_UART_TX, uartDeviceIdx, cfg->txDmaopt); - if (dmaChannelSpec) { - uartPort->txDMAResource = dmaChannelSpec->ref; -#if defined(STM32F4) || defined(STM32F7) || defined(STM32H7) || defined(STM32G4) || defined(APM32F4) - uartPort->txDMAChannel = dmaChannelSpec->channel; -#elif defined(AT32F4) - uartPort->txDMAMuxId = dmaChannelSpec->dmaMuxId; -#endif - } - } - - if (cfg->rxDmaopt != DMA_OPT_UNUSED) { - dmaChannelSpec = dmaGetChannelSpecByPeripheral(DMA_PERIPH_UART_RX, uartDeviceIdx, cfg->txDmaopt); - if (dmaChannelSpec) { - uartPort->rxDMAResource = dmaChannelSpec->ref; -#if defined(STM32F4) || defined(STM32F7) || defined(STM32H7) || defined(STM32G4) || defined(APM32F4) - uartPort->rxDMAChannel = dmaChannelSpec->channel; -#elif defined(AT32F4) - uartPort->rxDMAMuxId = dmaChannelSpec->dmaMuxId; -#endif - } - } -#else /* USE_DMA_SPEC */ - // Non USE_DMA_SPEC does not support configurable ON/OFF of UART DMA - - if (hardware->rxDMAResource) { - uartPort->rxDMAResource = hardware->rxDMAResource; -#if defined(STM32F4) || defined(STM32F7) || defined(STM32H7) || defined(STM32G4) || defined(APM32F4) - uartPort->rxDMAChannel = hardware->rxDMAChannel; -#elif defined(AT32F4) - uartPort->rxDMAMuxId = hardware->rxDMAMuxId; -#endif - } - - if (hardware->txDMAResource) { - uartPort->txDMAResource = hardware->txDMAResource; -#if defined(STM32F4) || defined(STM32F7) || defined(STM32H7) || defined(STM32G4) || defined(APM32F4) - uartPort->txDMAChannel = hardware->txDMAChannel; -#elif defined(AT32F4) - uartPort->txDMAMuxId = hardware->txDMAMuxId; -#endif - } -#endif /* USE_DMA_SPEC */ - - if (uartPort->txDMAResource) { - const dmaIdentifier_e identifier = dmaGetIdentifier(uartPort->txDMAResource); - if (dmaAllocate(identifier, ownerTxRx, ownerIndex)) { - dmaEnable(identifier); -#if defined(AT32F4) - dmaMuxEnable(identifier, uartPort->txDMAMuxId); -#endif - dmaSetHandler(identifier, uartDmaIrqHandler, hardware->txPriority, (uint32_t)uartdev); - uartPort->txDMAPeripheralBaseAddr = (uint32_t)&UART_REG_TXD(hardware->reg); - } - } - - if (uartPort->rxDMAResource) { - const dmaIdentifier_e identifier = dmaGetIdentifier(uartPort->rxDMAResource); - if (dmaAllocate(identifier, ownerTxRx + 1, ownerIndex)) { - dmaEnable(identifier); -#if defined(AT32F4) - dmaMuxEnable(identifier, uartPort->rxDMAMuxId); -#endif - uartPort->rxDMAPeripheralBaseAddr = (uint32_t)&UART_REG_RXD(hardware->reg); - } - } -} -#endif - #define UART_IRQHandler(type, number, dev) \ FAST_IRQ_HANDLER void type ## number ## _IRQHandler(void) \ { \ diff --git a/src/main/drivers/serial_uart_impl.h b/src/main/drivers/serial_uart_impl.h index 94b679e505..42e199c5ad 100644 --- a/src/main/drivers/serial_uart_impl.h +++ b/src/main/drivers/serial_uart_impl.h @@ -31,20 +31,8 @@ // Various serial routines return the buffer occupied size as uint8_t which would need to be extended in order to // increase size further. -// define some common UART features -#if defined(STM32F7) || defined(STM32H7) || defined(STM32G4) || defined(AT32F43x) -#define UART_TRAIT_AF_PIN 1 // pin AF mode is configured for each pin individually -#else -#define UART_TRAIT_AF_PORT 1 // all pins on given uart use same AF -#endif +#include "platform.h" -#if !defined(STM32F4) || !defined(APM32F4) // all others support pinswap -#define UART_TRAIT_PINSWAP 1 -#endif - -#if defined(STM32F4) - -#define UARTHARDWARE_MAX_PINS 4 #ifndef UART_RX_BUFFER_SIZE #define UART_RX_BUFFER_SIZE 256 #endif @@ -56,77 +44,8 @@ #endif #endif -#elif defined(STM32F7) - -#define UARTHARDWARE_MAX_PINS 4 -#ifndef UART_RX_BUFFER_SIZE -#define UART_RX_BUFFER_SIZE 256 -#endif -#ifndef UART_TX_BUFFER_SIZE -#ifdef USE_MSP_DISPLAYPORT -#define UART_TX_BUFFER_SIZE 1280 -#else -#define UART_TX_BUFFER_SIZE 256 -#endif -#endif - -#elif defined(STM32H7) - -#define UARTHARDWARE_MAX_PINS 5 -#ifndef UART_RX_BUFFER_SIZE -#define UART_RX_BUFFER_SIZE 256 -#endif -#ifndef UART_TX_BUFFER_SIZE -#ifdef USE_MSP_DISPLAYPORT -#define UART_TX_BUFFER_SIZE 1280 -#else -#define UART_TX_BUFFER_SIZE 256 -#endif -#endif - -#elif defined(STM32G4) - -#define UARTHARDWARE_MAX_PINS 3 -#ifndef UART_RX_BUFFER_SIZE -#define UART_RX_BUFFER_SIZE 256 -#endif -#ifndef UART_TX_BUFFER_SIZE -#ifdef USE_MSP_DISPLAYPORT -#define UART_TX_BUFFER_SIZE 1280 -#else -#define UART_TX_BUFFER_SIZE 256 -#endif -#endif - -#elif defined(AT32F4) - -#define UARTHARDWARE_MAX_PINS 5 -#ifndef UART_RX_BUFFER_SIZE -#define UART_RX_BUFFER_SIZE 256 -#endif -#ifndef UART_TX_BUFFER_SIZE -#ifdef USE_MSP_DISPLAYPORT -#define UART_TX_BUFFER_SIZE 1280 -#else -#define UART_TX_BUFFER_SIZE 256 -#endif -#endif -#elif defined(APM32F4) - -#define UARTHARDWARE_MAX_PINS 4 -#ifndef UART_RX_BUFFER_SIZE -#define UART_RX_BUFFER_SIZE 256 -#endif -#ifndef UART_TX_BUFFER_SIZE -#ifdef USE_MSP_DISPLAYPORT -#define UART_TX_BUFFER_SIZE 1280 -#else -#define UART_TX_BUFFER_SIZE 256 -#endif -#endif - -#else -#error unknown MCU family +#if !UART_TRAIT_AF_PIN && !UART_TRAIT_AF_PORT +#error "Must specify either AF mode for MCU" #endif // compressed index of UART/LPUART. Direct index into uartDevice[] @@ -188,10 +107,10 @@ typedef struct uartHardware_s { // For H7 and G4 , {tx|rx}DMAChannel are DMAMUX input index for peripherals (DMA_REQUEST_xxx); H7:RM0433 Table 110, G4:RM0440 Table 80. // For F4 and F7, these are 32-bit channel identifiers (DMA_CHANNEL_x) // For at32f435/7 DmaChannel is the dmamux, need to call dmamuxenable using dmamuxid -#if defined(STM32F4) || defined(STM32F7) || defined(STM32H7) || defined(STM32G4) || defined(APM32F4) +#if DMA_TRAIT_CHANNEL uint32_t txDMAChannel; uint32_t rxDMAChannel; -#elif defined(AT32F4) +#elif DMA_TRAIT_MUX uint32_t txDMAMuxId;//for dmaspec->dmamux and using dmaMuxEnable(dmax,muxid) uint32_t rxDMAMuxId; #endif @@ -257,6 +176,7 @@ uartPort_t *serialUART(uartDevice_t *uart, uint32_t baudRate, portMode_e mode, p void uartConfigureExternalPinInversion(uartPort_t *uartPort); void uartIrqHandler(uartPort_t *s); +void uartEnableTxInterrupt(uartPort_t *uartPort); void uartReconfigure(uartPort_t *uartPort); @@ -267,20 +187,6 @@ void uartDmaIrqHandler(dmaChannelDescriptor_t* descriptor); bool checkUsartTxOutput(uartPort_t *s); void uartTxMonitor(uartPort_t *s); -#if defined(STM32F7) || defined(STM32H7) || defined(STM32G4) -#define UART_REG_RXD(base) ((base)->RDR) -#define UART_REG_TXD(base) ((base)->TDR) -#elif defined(STM32F4) -#define UART_REG_RXD(base) ((base)->DR) -#define UART_REG_TXD(base) ((base)->DR) -#elif defined(AT32F43x) -#define UART_REG_RXD(base) ((base)->dt) -#define UART_REG_TXD(base) ((base)->dt) -#elif defined(APM32F4) -#define UART_REG_RXD(base) ((base)->DATA) -#define UART_REG_TXD(base) ((base)->DATA) -#endif - #define UART_BUFFER(type, n, rxtx) type volatile uint8_t uart ## n ## rxtx ## xBuffer[UART_ ## rxtx ## X_BUFFER_SIZE] #define UART_BUFFERS_EXTERN(n) \ diff --git a/src/main/drivers/serial_usb_vcp.h b/src/main/drivers/serial_usb_vcp.h index 1a9bc30494..daeaa2ce22 100644 --- a/src/main/drivers/serial_usb_vcp.h +++ b/src/main/drivers/serial_usb_vcp.h @@ -22,19 +22,6 @@ #include "drivers/serial.h" -#if defined(STM32F7) -#include "common/maths.h" - -#include "usbd_cdc.h" - -extern USBD_HandleTypeDef USBD_Device; - -#elif defined(STM32H7) || defined(STM32G4) -#include "usbd_cdc.h" - -extern USBD_HandleTypeDef USBD_Device; -#endif - typedef struct { serialPort_t port; diff --git a/src/platform/APM32/mk/APM32F4.mk b/src/platform/APM32/mk/APM32F4.mk index 4b3a3cee21..5203bf6781 100644 --- a/src/platform/APM32/mk/APM32F4.mk +++ b/src/platform/APM32/mk/APM32F4.mk @@ -180,6 +180,7 @@ MCU_COMMON_SRC = \ drivers/bus_spi_config.c \ common/stm32/bus_spi_hw.c \ common/stm32/bus_spi_pinconfig.c \ + common/stm32/serial_uart_hw.c \ drivers/serial_escserial.c \ drivers/serial_pinconfig.c \ drivers/serial_uart_pinconfig.c \ @@ -205,6 +206,7 @@ MSC_SRC = \ msc/usbd_storage_sdio.c SPEED_OPTIMISED_SRC += \ + common/stm32/bus_spi_hw.c \ common/stm32/system.c SIZE_OPTIMISED_SRC += \ diff --git a/src/platform/APM32/platform_mcu.h b/src/platform/APM32/platform_mcu.h index 8e0aa79749..71833d55ce 100644 --- a/src/platform/APM32/platform_mcu.h +++ b/src/platform/APM32/platform_mcu.h @@ -187,6 +187,18 @@ #define USE_TX_IRQ_HANDLER +#define UART_TX_BUFFER_ATTRIBUTE /* NONE */ +#define UART_RX_BUFFER_ATTRIBUTE /* NONE */ + +#define UART_TRAIT_AF_PORT 1 + +#define UARTHARDWARE_MAX_PINS 4 + +#define UART_REG_RXD(base) ((base)->DATA) +#define UART_REG_TXD(base) ((base)->DATA) + +#define DMA_TRAIT_CHANNEL 1 + #endif #if defined(APM32F4) diff --git a/src/platform/AT32/mk/AT32F4.mk b/src/platform/AT32/mk/AT32F4.mk index 0c0ff8be39..759c36ad60 100644 --- a/src/platform/AT32/mk/AT32F4.mk +++ b/src/platform/AT32/mk/AT32F4.mk @@ -122,6 +122,7 @@ MCU_COMMON_SRC = \ drivers/bus_spi_config.c \ common/stm32/bus_spi_pinconfig.c \ common/stm32/bus_spi_hw.c \ + common/stm32/serial_uart_hw.c \ drivers/serial_escserial.c \ drivers/serial_pinconfig.c \ drivers/serial_uart_pinconfig.c \ diff --git a/src/platform/AT32/platform_mcu.h b/src/platform/AT32/platform_mcu.h index 9a42c16cfc..97ee59aa1d 100644 --- a/src/platform/AT32/platform_mcu.h +++ b/src/platform/AT32/platform_mcu.h @@ -134,12 +134,25 @@ typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; #define SPI_IO_CS_CFG IO_CONFIG(GPIO_MODE_OUTPUT, GPIO_DRIVE_STRENGTH_STRONGER, GPIO_OUTPUT_PUSH_PULL, GPIO_PULL_NONE) #define SPI_IO_CS_HIGH_CFG IO_CONFIG(GPIO_MODE_INPUT, GPIO_DRIVE_STRENGTH_STRONGER, GPIO_OUTPUT_PUSH_PULL, GPIO_PULL_UP) -#define SPIDEV_COUNT 4 +#define SPIDEV_COUNT 4 #define CHECK_SPI_RX_DATA_AVAILABLE(instance) LL_SPI_IsActiveFlag_RXNE(instance) #define SPI_RX_DATA_REGISTER(base) ((base)->DR) -#define MAX_SPI_PIN_SEL 4 +#define MAX_SPI_PIN_SEL 4 + +#define UART_TX_BUFFER_ATTRIBUTE // NONE +#define UART_RX_BUFFER_ATTRIBUTE // NONE + +#define UART_TRAIT_AF_PIN 1 +#define UART_TRAIT_PINSWAP 1 + +#define UARTHARDWARE_MAX_PINS 5 + +#define UART_REG_RXD(base) ((base)->dt) +#define UART_REG_TXD(base) ((base)->dt) + +#define DMA_TRAIT_MUX 1 #endif diff --git a/src/platform/STM32/mk/STM32_COMMON.mk b/src/platform/STM32/mk/STM32_COMMON.mk index e8f7914941..8106ccf43d 100644 --- a/src/platform/STM32/mk/STM32_COMMON.mk +++ b/src/platform/STM32/mk/STM32_COMMON.mk @@ -6,7 +6,8 @@ MCU_COMMON_SRC += \ common/stm32/config_flash.c \ common/stm32/bus_spi_pinconfig.c \ common/stm32/bus_spi_hw.c \ - common/stm32/io_impl.c + common/stm32/io_impl.c \ + common/stm32/serial_uart_hw.c SIZE_OPTIMISED_SRC += \ common/stm32/config_flash.c \ diff --git a/src/platform/STM32/platform_mcu.h b/src/platform/STM32/platform_mcu.h index 1f69a3cfc9..2f7e24993c 100644 --- a/src/platform/STM32/platform_mcu.h +++ b/src/platform/STM32/platform_mcu.h @@ -360,6 +360,57 @@ extern uint8_t _dmaram_end__; #error Unknown MCU family #endif -#if !defined(STM32G4) && !defined(STM32H7) +#if defined(STM32F4) || defined(STM32F7) #define USE_TX_IRQ_HANDLER #endif + +#if defined(STM32H7) +#define UART_TX_BUFFER_ATTRIBUTE DMA_RAM /* D2 SRAM */ +#define UART_RX_BUFFER_ATTRIBUTE DMA_RAM /* D2 SRAM */ +#elif defined(STM32G4) +#define UART_TX_BUFFER_ATTRIBUTE DMA_RAM_W /* SRAM MPU NOT_BUFFERABLE */ +#define UART_RX_BUFFER_ATTRIBUTE DMA_RAM_R /* SRAM MPU NOT CACHABLE */ +#elif defined(STM32F7) +#define UART_TX_BUFFER_ATTRIBUTE FAST_DATA_ZERO_INIT /* DTCM RAM */ +#define UART_RX_BUFFER_ATTRIBUTE FAST_DATA_ZERO_INIT /* DTCM RAM */ +#elif defined(STM32F4) +#define UART_TX_BUFFER_ATTRIBUTE /* EMPTY */ +#define UART_RX_BUFFER_ATTRIBUTE /* EMPTY */ +#endif + +#if defined(STM32F7) || defined(STM32H7) || defined(STM32G4) + // pin AF mode is configured for each pin individually +#define UART_TRAIT_AF_PIN 1 +#elif defined(STM32F4) +// all pins on given uart use same AF +#define UART_TRAIT_AF_PORT 1 +#else +#error Unknown STM MCU when defining UART_TRAIT_x +#endif + +#if defined(STM32F7) || defined(STM32H7) || defined(STM32G4) +#define UART_TRAIT_PINSWAP 1 +#endif + +#if defined(STM32F4) +#define UARTHARDWARE_MAX_PINS 4 +#elif defined(STM32F7) +#define UARTHARDWARE_MAX_PINS 4 +#elif defined(STM32H7) +#define UARTHARDWARE_MAX_PINS 5 +#elif defined(STM32G4) +#define UARTHARDWARE_MAX_PINS 3 +#endif + +#if defined(STM32F7) || defined(STM32H7) || defined(STM32G4) +#define UART_REG_RXD(base) ((base)->RDR) +#define UART_REG_TXD(base) ((base)->TDR) +#elif defined(STM32F4) +#define UART_REG_RXD(base) ((base)->DR) +#define UART_REG_TXD(base) ((base)->DR) +#endif + + +#if defined(STM32F4) || defined(STM32F7) || defined(STM32H7) || defined(STM32G4) +#define DMA_TRAIT_CHANNEL 1 +#endif diff --git a/src/platform/STM32/vcp_hal/usbd_cdc_interface.h b/src/platform/STM32/vcp_hal/usbd_cdc_interface.h index 4a4d81d0ca..2c8e7a34f1 100644 --- a/src/platform/STM32/vcp_hal/usbd_cdc_interface.h +++ b/src/platform/STM32/vcp_hal/usbd_cdc_interface.h @@ -83,6 +83,7 @@ typedef struct __attribute__ ((packed)) } LINE_CODING; extern USBD_CDC_ItfTypeDef USBD_CDC_fops; +extern USBD_HandleTypeDef USBD_Device; uint32_t CDC_Send_DATA(const uint8_t *ptrBuffer, uint32_t sendLength); uint32_t CDC_Send_FreeBytes(void); diff --git a/src/main/drivers/serial_uart_hw.c b/src/platform/common/stm32/serial_uart_hw.c similarity index 65% rename from src/main/drivers/serial_uart_hw.c rename to src/platform/common/stm32/serial_uart_hw.c index 91e42c005f..74e32147cf 100644 --- a/src/main/drivers/serial_uart_hw.c +++ b/src/platform/common/stm32/serial_uart_hw.c @@ -28,7 +28,7 @@ #include "platform.h" -#if defined(USE_UART) && !defined(SIMULATOR_BUILD) +#if defined(USE_UART) #include "build/build_config.h" @@ -39,6 +39,10 @@ #include "drivers/serial_impl.h" #include "drivers/serial_uart.h" #include "drivers/serial_uart_impl.h" +#include "drivers/dma.h" +#include "drivers/dma_reqmap.h" + +#include "pg/serial_uart.h" // TODO: split this function into mcu-specific UART files ? static void enableRxIrq(const uartHardware_t *hardware) @@ -207,4 +211,106 @@ void uartConfigureExternalPinInversion(uartPort_t *uartPort) #endif } +#ifdef USE_DMA +void uartConfigureDma(uartDevice_t *uartdev) +{ + uartPort_t *uartPort = &(uartdev->port); + const uartHardware_t *hardware = uartdev->hardware; + +#ifdef USE_DMA_SPEC + const serialPortIdentifier_e uartPortIdentifier = hardware->identifier; + const uartDeviceIdx_e uartDeviceIdx = uartDeviceIdxFromIdentifier(uartPortIdentifier); + if (uartDeviceIdx == UARTDEV_INVALID) { + return; + } + const int resourceIdx = serialResourceIndex(uartPortIdentifier); + const int ownerIndex = serialOwnerIndex(uartPortIdentifier); + const resourceOwner_e ownerTxRx = serialOwnerTxRx(uartPortIdentifier); // rx is always +1 + + const dmaChannelSpec_t *dmaChannelSpec; + const serialUartConfig_t *cfg = serialUartConfig(resourceIdx); + if (!cfg) { + return; + } + if (cfg->txDmaopt != DMA_OPT_UNUSED) { + dmaChannelSpec = dmaGetChannelSpecByPeripheral(DMA_PERIPH_UART_TX, uartDeviceIdx, cfg->txDmaopt); + if (dmaChannelSpec) { + uartPort->txDMAResource = dmaChannelSpec->ref; +#if DMA_TRAIT_CHANNEL + uartPort->txDMAChannel = dmaChannelSpec->channel; +#elif DMA_TRAIT_MUX + uartPort->txDMAMuxId = dmaChannelSpec->dmaMuxId; +#endif + } + } + + if (cfg->rxDmaopt != DMA_OPT_UNUSED) { + dmaChannelSpec = dmaGetChannelSpecByPeripheral(DMA_PERIPH_UART_RX, uartDeviceIdx, cfg->txDmaopt); + if (dmaChannelSpec) { + uartPort->rxDMAResource = dmaChannelSpec->ref; +#if DMA_TRAIT_CHANNEL + uartPort->rxDMAChannel = dmaChannelSpec->channel; +#elif DMA_TRAIT_MUX + uartPort->rxDMAMuxId = dmaChannelSpec->dmaMuxId; +#endif + } + } +#else /* USE_DMA_SPEC */ + // Non USE_DMA_SPEC does not support configurable ON/OFF of UART DMA + + if (hardware->rxDMAResource) { + uartPort->rxDMAResource = hardware->rxDMAResource; +#if DMA_TRAIT_CHANNEL + uartPort->rxDMAChannel = hardware->rxDMAChannel; +#elif DMA_TRAIT_MUX + uartPort->rxDMAMuxId = hardware->rxDMAMuxId; +#endif + } + + if (hardware->txDMAResource) { + uartPort->txDMAResource = hardware->txDMAResource; +#if DMA_TRAIT_CHANNEL + uartPort->txDMAChannel = hardware->txDMAChannel; +#elif DMA_TRAIT_MUX + uartPort->txDMAMuxId = hardware->txDMAMuxId; +#endif + } +#endif /* USE_DMA_SPEC */ + + if (uartPort->txDMAResource) { + const dmaIdentifier_e identifier = dmaGetIdentifier(uartPort->txDMAResource); + if (dmaAllocate(identifier, ownerTxRx, ownerIndex)) { + dmaEnable(identifier); +#if DMA_TRAIT_MUX + dmaMuxEnable(identifier, uartPort->txDMAMuxId); +#endif + dmaSetHandler(identifier, uartDmaIrqHandler, hardware->txPriority, (uint32_t)uartdev); + uartPort->txDMAPeripheralBaseAddr = (uint32_t)&UART_REG_TXD(hardware->reg); + } + } + + if (uartPort->rxDMAResource) { + const dmaIdentifier_e identifier = dmaGetIdentifier(uartPort->rxDMAResource); + if (dmaAllocate(identifier, ownerTxRx + 1, ownerIndex)) { + dmaEnable(identifier); +#if DMA_TRAIT_MUX + dmaMuxEnable(identifier, uartPort->rxDMAMuxId); +#endif + uartPort->rxDMAPeripheralBaseAddr = (uint32_t)&UART_REG_RXD(hardware->reg); + } + } +} +#endif + +void uartEnableTxInterrupt(uartPort_t *uartPort) +{ +#if defined(USE_HAL_DRIVER) + __HAL_UART_ENABLE_IT(&uartPort->Handle, UART_IT_TXE); +#elif defined(USE_ATBSP_DRIVER) + usart_interrupt_enable(uartPort->USARTx, USART_TDBE_INT, TRUE); +#else + USART_ITConfig(uartPort->USARTx, USART_IT_TXE, ENABLE); +#endif +} + #endif /* USE_UART */ From 076d8d20ece2fe4258978c61279230992e836140 Mon Sep 17 00:00:00 2001 From: Jay Blackman Date: Fri, 10 Jan 2025 19:48:44 +1100 Subject: [PATCH 034/244] FIX: Makefile such that `make CONFIG=config-target` works as expected (#14129) --- Makefile | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/Makefile b/Makefile index b8cfc77eab..46c822012e 100644 --- a/Makefile +++ b/Makefile @@ -123,7 +123,6 @@ FC_VER := $(FC_VER_MAJOR).$(FC_VER_MINOR).$(FC_VER_PATCH) # import config handling include $(MAKE_SCRIPT_DIR)/config.mk - # default xtal value HSE_VALUE ?= 8000000 @@ -220,7 +219,15 @@ endif # TARGET specified # openocd specific includes include $(MAKE_SCRIPT_DIR)/openocd.mk +ifeq ($(CONFIG),) +ifeq ($(TARGET),) .DEFAULT_GOAL := all +else +.DEFAULT_GOAL := hex +endif +else +.DEFAULT_GOAL := hex +endif INCLUDE_DIRS := $(INCLUDE_DIRS) \ $(ROOT)/lib/main/MAVLink From c91e4214ebd435653873c7c40ac20ffddf555b4b Mon Sep 17 00:00:00 2001 From: Jay Blackman Date: Sat, 11 Jan 2025 06:01:04 +1100 Subject: [PATCH 035/244] FIX: Adding RP2350B as MCU type and correcting lookup table error (#14138) --- src/main/build/build_config.c | 14 ++++++++++---- src/main/build/build_config.h | 8 ++++++-- src/main/cli/cli.c | 6 ++++-- 3 files changed, 20 insertions(+), 8 deletions(-) diff --git a/src/main/build/build_config.c b/src/main/build/build_config.c index d6d92e65e5..70117e0407 100644 --- a/src/main/build/build_config.c +++ b/src/main/build/build_config.c @@ -68,10 +68,16 @@ mcuTypeId_e getMcuTypeId(void) return MCU_TYPE_H723_725; #elif defined(STM32G474xx) return MCU_TYPE_G474; -#elif defined(AT32F435) - return MCU_TYPE_AT32; -#elif defined(APM32F4) - return MCU_TYPE_APM32F40X; +#elif defined(AT32F435G) + return MCU_TYPE_AT32F435G; +#elif defined(AT32F435M) + return MCU_TYPE_AT32F435M; +#elif defined(APM32F405) + return MCU_TYPE_APM32F405; +#elif defined(APM32F407) + return MCU_TYPE_APM32F407; +#elif defined(RP2350B) + return MCU_TYPE_RP2350B; #else return MCU_TYPE_UNKNOWN; #endif diff --git a/src/main/build/build_config.h b/src/main/build/build_config.h index cd77a4b849..b187d06de1 100644 --- a/src/main/build/build_config.h +++ b/src/main/build/build_config.h @@ -59,8 +59,12 @@ typedef enum { MCU_TYPE_H723_725, MCU_TYPE_G474, MCU_TYPE_H730, - MCU_TYPE_AT32, - MCU_TYPE_APM32F40X, + MCU_TYPE_AT32F435G, + MCU_TYPE_APM32F405, + MCU_TYPE_APM32F407, + MCU_TYPE_AT32F435M, + MCU_TYPE_RP2350B, + MCU_TYPE_COUNT, MCU_TYPE_UNKNOWN = 255, } mcuTypeId_e; diff --git a/src/main/cli/cli.c b/src/main/cli/cli.c index a174fe8cf5..12dd19cd87 100644 --- a/src/main/cli/cli.c +++ b/src/main/cli/cli.c @@ -280,7 +280,7 @@ static const char * const *sensorHardwareNames[] = { #endif // USE_SENSOR_NAMES // Needs to be aligned with mcuTypeId_e -static const char *mcuTypeNames[] = { +static const char *mcuTypeNames[MCU_TYPE_COUNT] = { "SIMULATOR", "F40X", "F411", @@ -298,9 +298,11 @@ static const char *mcuTypeNames[] = { "H723/H725", "G474", "H730", - "AT32F435", + "AT32F435G", "APM32F405", "APM32F407", + "AT32F435M", + "RP2350B", }; static const char *configurationStates[] = { From 016d5764c8b8fdc7c4353a011828dd98362a24fd Mon Sep 17 00:00:00 2001 From: Jay Blackman Date: Sat, 11 Jan 2025 06:10:06 +1100 Subject: [PATCH 036/244] FIX: RCC is platform specific (#14137) * FIX: RCC is platform specific * Renamed to PLATFORM_TRAIT_RCC --- src/main/drivers/serial_uart_impl.h | 2 ++ src/platform/APM32/platform_mcu.h | 1 + src/platform/AT32/platform_mcu.h | 1 + src/platform/STM32/platform_mcu.h | 4 +++- 4 files changed, 7 insertions(+), 1 deletion(-) diff --git a/src/main/drivers/serial_uart_impl.h b/src/main/drivers/serial_uart_impl.h index 42e199c5ad..9a6304129c 100644 --- a/src/main/drivers/serial_uart_impl.h +++ b/src/main/drivers/serial_uart_impl.h @@ -120,7 +120,9 @@ typedef struct uartHardware_s { uartPinDef_t rxPins[UARTHARDWARE_MAX_PINS]; uartPinDef_t txPins[UARTHARDWARE_MAX_PINS]; +#if PLATFORM_TRAIT_RCC rccPeriphTag_t rcc; +#endif #if UART_TRAIT_AF_PORT uint8_t af; diff --git a/src/platform/APM32/platform_mcu.h b/src/platform/APM32/platform_mcu.h index 71833d55ce..ae0417a628 100644 --- a/src/platform/APM32/platform_mcu.h +++ b/src/platform/APM32/platform_mcu.h @@ -190,6 +190,7 @@ #define UART_TX_BUFFER_ATTRIBUTE /* NONE */ #define UART_RX_BUFFER_ATTRIBUTE /* NONE */ +#define PLATFORM_TRAIT_RCC 1 #define UART_TRAIT_AF_PORT 1 #define UARTHARDWARE_MAX_PINS 4 diff --git a/src/platform/AT32/platform_mcu.h b/src/platform/AT32/platform_mcu.h index 97ee59aa1d..0e5ff69102 100644 --- a/src/platform/AT32/platform_mcu.h +++ b/src/platform/AT32/platform_mcu.h @@ -144,6 +144,7 @@ typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; #define UART_TX_BUFFER_ATTRIBUTE // NONE #define UART_RX_BUFFER_ATTRIBUTE // NONE +#define PLATFORM_TRAIT_RCC 1 #define UART_TRAIT_AF_PIN 1 #define UART_TRAIT_PINSWAP 1 diff --git a/src/platform/STM32/platform_mcu.h b/src/platform/STM32/platform_mcu.h index 2f7e24993c..637799c29c 100644 --- a/src/platform/STM32/platform_mcu.h +++ b/src/platform/STM32/platform_mcu.h @@ -385,9 +385,11 @@ extern uint8_t _dmaram_end__; // all pins on given uart use same AF #define UART_TRAIT_AF_PORT 1 #else -#error Unknown STM MCU when defining UART_TRAIT_x +#error Unknown STM MCU when defining UART_TRAIT_x #endif +#define PLATFORM_TRAIT_RCC 1 + #if defined(STM32F7) || defined(STM32H7) || defined(STM32G4) #define UART_TRAIT_PINSWAP 1 #endif From aef3e721576697bbc6b5b750cd78b9ace7755b08 Mon Sep 17 00:00:00 2001 From: Jay Blackman Date: Sat, 11 Jan 2025 06:12:01 +1100 Subject: [PATCH 037/244] FIX: Missing USE_DMA conditions (#14139) * FIX: Missing USE_DMA conditions * Minor change as per @ledvinap feedback --- src/main/drivers/accgyro/accgyro_mpu.c | 5 ++++- src/main/drivers/accgyro/accgyro_spi_bmi160.c | 5 ++++- src/main/drivers/accgyro/accgyro_spi_bmi270.c | 5 ++++- src/main/drivers/accgyro/accgyro_spi_lsm6dsv16x.c | 5 ++++- src/main/drivers/bus_spi.c | 3 ++- src/main/drivers/compass/compass_ak8963.c | 2 ++ src/main/drivers/max7456.c | 9 +++++++-- src/main/drivers/rx/rx_spi.c | 4 ++++ 8 files changed, 31 insertions(+), 7 deletions(-) diff --git a/src/main/drivers/accgyro/accgyro_mpu.c b/src/main/drivers/accgyro/accgyro_mpu.c index d1ebe2857a..5e37cd5286 100644 --- a/src/main/drivers/accgyro/accgyro_mpu.c +++ b/src/main/drivers/accgyro/accgyro_mpu.c @@ -273,6 +273,7 @@ bool mpuGyroReadSPI(gyroDev_t *gyro) // We need some offset from the gyro interrupts to ensure sampling after the interrupt gyro->gyroDmaMaxDuration = 5; if (gyro->detectedEXTI > GYRO_EXTI_DETECT_THRESHOLD) { +#ifdef USE_DMA if (spiUseDMA(&gyro->dev)) { gyro->dev.callbackArg = (uint32_t)gyro; gyro->dev.txBuf[0] = gyro->accDataReg | 0x80; @@ -282,7 +283,9 @@ bool mpuGyroReadSPI(gyroDev_t *gyro) gyro->segments[0].u.buffers.rxData = &gyro->dev.rxBuf[1]; gyro->segments[0].negateCS = true; gyro->gyroModeSPI = GYRO_EXTI_INT_DMA; - } else { + } else +#endif + { // Interrupts are present, but no DMA gyro->gyroModeSPI = GYRO_EXTI_INT; } diff --git a/src/main/drivers/accgyro/accgyro_spi_bmi160.c b/src/main/drivers/accgyro/accgyro_spi_bmi160.c index 108efcbbd7..206417d188 100644 --- a/src/main/drivers/accgyro/accgyro_spi_bmi160.c +++ b/src/main/drivers/accgyro/accgyro_spi_bmi160.c @@ -380,6 +380,7 @@ static bool bmi160GyroRead(gyroDev_t *gyro) gyro->gyroDmaMaxDuration = 5; // Using DMA for gyro access upsets the scheduler on the F4 if (gyro->detectedEXTI > GYRO_EXTI_DETECT_THRESHOLD) { +#ifdef USE_DMA if (spiUseDMA(dev)) { dev->callbackArg = (uint32_t)gyro; dev->txBuf[1] = BMI160_REG_GYR_DATA_X_LSB | 0x80; @@ -389,7 +390,9 @@ static bool bmi160GyroRead(gyroDev_t *gyro) gyro->segments[0].u.buffers.rxData = &dev->rxBuf[1]; gyro->segments[0].negateCS = true; gyro->gyroModeSPI = GYRO_EXTI_INT_DMA; - } else { + } else +#endif + { // Interrupts are present, but no DMA gyro->gyroModeSPI = GYRO_EXTI_INT; } diff --git a/src/main/drivers/accgyro/accgyro_spi_bmi270.c b/src/main/drivers/accgyro/accgyro_spi_bmi270.c index 4156d98710..79ab79077e 100644 --- a/src/main/drivers/accgyro/accgyro_spi_bmi270.c +++ b/src/main/drivers/accgyro/accgyro_spi_bmi270.c @@ -389,6 +389,7 @@ static bool bmi270GyroReadRegister(gyroDev_t *gyro) gyro->gyroDmaMaxDuration = 5; // Using DMA for gyro access upsets the scheduler on the F4 if (gyro->detectedEXTI > GYRO_EXTI_DETECT_THRESHOLD) { +#ifdef USE_DMA if (spiUseDMA(dev)) { dev->callbackArg = (uint32_t)gyro; dev->txBuf[0] = BMI270_REG_ACC_DATA_X_LSB | 0x80; @@ -398,7 +399,9 @@ static bool bmi270GyroReadRegister(gyroDev_t *gyro) gyro->segments[0].u.buffers.rxData = dev->rxBuf; gyro->segments[0].negateCS = true; gyro->gyroModeSPI = GYRO_EXTI_INT_DMA; - } else { + } else +#endif + { // Interrupts are present, but no DMA gyro->gyroModeSPI = GYRO_EXTI_INT; } diff --git a/src/main/drivers/accgyro/accgyro_spi_lsm6dsv16x.c b/src/main/drivers/accgyro/accgyro_spi_lsm6dsv16x.c index a4ae648ed7..21f33a7a35 100644 --- a/src/main/drivers/accgyro/accgyro_spi_lsm6dsv16x.c +++ b/src/main/drivers/accgyro/accgyro_spi_lsm6dsv16x.c @@ -1023,6 +1023,7 @@ bool lsm6dsv16xGyroReadSPI(gyroDev_t *gyro) // We need some offset from the gyro interrupts to ensure sampling after the interrupt gyro->gyroDmaMaxDuration = 5; if (gyro->detectedEXTI > GYRO_EXTI_DETECT_THRESHOLD) { +#ifdef USE_DMA if (spiUseDMA(&gyro->dev)) { gyro->dev.callbackArg = (uint32_t)gyro; gyro->dev.txBuf[0] = LSM6DSV_OUTX_L_G | 0x80; @@ -1033,7 +1034,9 @@ bool lsm6dsv16xGyroReadSPI(gyroDev_t *gyro) gyro->segments[0].u.buffers.rxData = &gyro->dev.rxBuf[1]; gyro->segments[0].negateCS = true; gyro->gyroModeSPI = GYRO_EXTI_INT_DMA; - } else { + } else +#endif + { // Interrupts are present, but no DMA gyro->gyroModeSPI = GYRO_EXTI_INT; } diff --git a/src/main/drivers/bus_spi.c b/src/main/drivers/bus_spi.c index ae82bbcd63..5cb2359c11 100644 --- a/src/main/drivers/bus_spi.c +++ b/src/main/drivers/bus_spi.c @@ -35,7 +35,6 @@ #include "drivers/exti.h" #include "drivers/io.h" #include "drivers/motor.h" -#include "drivers/rcc.h" #include "drivers/nvic.h" #include "pg/bus_spi.h" @@ -384,6 +383,7 @@ void spiSetClkPhasePolarity(const extDevice_t *dev, bool leadingEdge) ((extDevice_t *)dev)->busType_u.spi.leadingEdge = leadingEdge; } +#ifdef USE_DMA // Enable/disable DMA on a specific device. Enabled by default. void spiDmaEnable(const extDevice_t *dev, bool enable) { @@ -400,6 +400,7 @@ bool spiUseSDO_DMA(const extDevice_t *dev) { return dev->bus->useDMA && dev->useDMA; } +#endif void spiBusDeviceRegister(const extDevice_t *dev) { diff --git a/src/main/drivers/compass/compass_ak8963.c b/src/main/drivers/compass/compass_ak8963.c index b5984d624d..6fea1b3132 100644 --- a/src/main/drivers/compass/compass_ak8963.c +++ b/src/main/drivers/compass/compass_ak8963.c @@ -393,8 +393,10 @@ void ak8963BusInit(const extDevice_t *dev) #if defined(USE_MAG_AK8963) && (defined(USE_GYRO_SPI_MPU6500) || defined(USE_GYRO_SPI_MPU9250)) case BUS_TYPE_MPU_SLAVE: +#ifdef USE_DMA // Disable DMA on gyro as this upsets slave access timing spiDmaEnable(dev->bus->busType_u.mpuSlave.master, false); +#endif // initialize I2C master via SPI bus ak8963SpiWriteRegisterDelay(dev->bus->busType_u.mpuSlave.master, MPU_RA_INT_PIN_CFG, MPU6500_BIT_INT_ANYRD_2CLEAR | MPU6500_BIT_BYPASS_EN); diff --git a/src/main/drivers/max7456.c b/src/main/drivers/max7456.c index 50b82151fc..b0cc1ba22d 100644 --- a/src/main/drivers/max7456.c +++ b/src/main/drivers/max7456.c @@ -640,8 +640,13 @@ bool max7456DrawScreen(void) bool autoInc = false; int posLimit = pos + (maxScreenSize / 2); - maxSpiBufStartIndex = spiUseSDO_DMA(dev) ? MAX_BYTES2SEND : MAX_BYTES2SEND_POLLED; - maxEncodeTime = spiUseSDO_DMA(dev) ? MAX_ENCODE_US : MAX_ENCODE_US_POLLED; +#ifdef USE_DMA + const bool useDma = spiUseSDO_DMA(dev); +#else + const bool useDma = false; +#endif + maxSpiBufStartIndex = useDma ? MAX_BYTES2SEND : MAX_BYTES2SEND_POLLED; + maxEncodeTime = useDma ? MAX_ENCODE_US : MAX_ENCODE_US_POLLED; // Abort for now if the bus is still busy if (spiIsBusy(dev)) { diff --git a/src/main/drivers/rx/rx_spi.c b/src/main/drivers/rx/rx_spi.c index 1755a06bb7..c025fdf296 100644 --- a/src/main/drivers/rx/rx_spi.c +++ b/src/main/drivers/rx/rx_spi.c @@ -149,7 +149,11 @@ void rxSpiExtiInit(ioConfig_t rxSpiExtiPinConfig, extiTrigger_t rxSpiExtiPinTrig void rxSpiDmaEnable(bool enable) { +#ifdef USE_DMA spiDmaEnable(dev, enable); +#else + UNUSED(enable); +#endif } uint8_t rxSpiTransferByte(uint8_t data) From 8375e4e0024f60b237533ffb3aa465cf071f792b Mon Sep 17 00:00:00 2001 From: Steve Evans Date: Fri, 10 Jan 2025 22:04:50 +0000 Subject: [PATCH 038/244] Leave SPI CPOL/CPHA at default for SD card (#14142) --- src/main/drivers/sdcard_spi.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/src/main/drivers/sdcard_spi.c b/src/main/drivers/sdcard_spi.c index 33a038eb8a..65e7157e5b 100644 --- a/src/main/drivers/sdcard_spi.c +++ b/src/main/drivers/sdcard_spi.c @@ -566,9 +566,6 @@ static void sdcardSpi_init(const sdcardConfig_t *config, const spiPinConfig_t *s } sdcard.dev.busType_u.spi.csnPin = chipSelectIO; - // Set the clock phase/polarity - spiSetClkPhasePolarity(&sdcard.dev, true); - // Set the callback argument when calling back to this driver for DMA completion sdcard.dev.callbackArg = (uint32_t)&sdcard; From 07e4b4f1adacfd6b966eda8a84c08fe995c8d765 Mon Sep 17 00:00:00 2001 From: Jay Blackman Date: Sun, 12 Jan 2025 07:45:08 +1100 Subject: [PATCH 039/244] Adding ability to configure USB positive data pin (PA12 is STM specific) (#14141) --- src/main/drivers/usb_io.c | 13 ++++++++----- src/platform/APM32/platform_mcu.h | 3 +-- src/platform/AT32/platform_mcu.h | 2 ++ src/platform/STM32/platform_mcu.h | 2 ++ 4 files changed, 13 insertions(+), 7 deletions(-) diff --git a/src/main/drivers/usb_io.c b/src/main/drivers/usb_io.c index 4ca071a1a9..f6972a8789 100644 --- a/src/main/drivers/usb_io.c +++ b/src/main/drivers/usb_io.c @@ -67,14 +67,17 @@ bool usbCableIsInserted(void) void usbGenerateDisconnectPulse(void) { - /* Pull down PA12 to create USB disconnect pulse */ - IO_t usbPin = IOGetByTag(IO_TAG(PA12)); +#ifdef USB_DP_PIN + /* Pull down USB_DP_PIN to create USB disconnect pulse */ + IO_t usbPin = IOGetByTag(IO_TAG(USB_DP_PIN)); + if (!usbPin) { + return; + } + IOConfigGPIO(usbPin, IOCFG_OUT_OD); - IOLo(usbPin); - delay(200); - IOHi(usbPin); +#endif } #endif diff --git a/src/platform/APM32/platform_mcu.h b/src/platform/APM32/platform_mcu.h index ae0417a628..2962b97218 100644 --- a/src/platform/APM32/platform_mcu.h +++ b/src/platform/APM32/platform_mcu.h @@ -200,8 +200,7 @@ #define DMA_TRAIT_CHANNEL 1 -#endif +#define USB_DP_PIN PA12 -#if defined(APM32F4) #define FLASH_CONFIG_BUFFER_TYPE uint32_t #endif diff --git a/src/platform/AT32/platform_mcu.h b/src/platform/AT32/platform_mcu.h index 0e5ff69102..7dbc1c7adf 100644 --- a/src/platform/AT32/platform_mcu.h +++ b/src/platform/AT32/platform_mcu.h @@ -158,3 +158,5 @@ typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; #endif #define FLASH_CONFIG_BUFFER_TYPE uint32_t + +#define USB_DP_PIN PA12 diff --git a/src/platform/STM32/platform_mcu.h b/src/platform/STM32/platform_mcu.h index 637799c29c..69522ba54a 100644 --- a/src/platform/STM32/platform_mcu.h +++ b/src/platform/STM32/platform_mcu.h @@ -416,3 +416,5 @@ extern uint8_t _dmaram_end__; #if defined(STM32F4) || defined(STM32F7) || defined(STM32H7) || defined(STM32G4) #define DMA_TRAIT_CHANNEL 1 #endif + +#define USB_DP_PIN PA12 From c513b102b6f2af9aa0390cfa7ef908ec652552fc Mon Sep 17 00:00:00 2001 From: Jay Blackman Date: Sun, 12 Jan 2025 07:47:22 +1100 Subject: [PATCH 040/244] FIX: Invalid references when neither DSHOT nor PWM_OUTPUT is defined. (#14135) --- src/main/drivers/motor.c | 27 +++++++++++++++----------- src/platform/APM32/pwm_output_apm32.c | 2 ++ src/platform/AT32/dshot_bitbang.c | 2 +- src/platform/AT32/pwm_output_at32bsp.c | 2 ++ src/platform/STM32/pwm_output.c | 2 ++ 5 files changed, 23 insertions(+), 12 deletions(-) diff --git a/src/main/drivers/motor.c b/src/main/drivers/motor.c index 6d53560b0c..62d472e7ed 100644 --- a/src/main/drivers/motor.c +++ b/src/main/drivers/motor.c @@ -317,26 +317,31 @@ bool isMotorProtocolBidirDshot(void) void motorDevInit(const motorDevConfig_t *motorDevConfig, uint16_t idlePulse, uint8_t motorCount) { - memset(motors, 0, sizeof(motors)); - +#if defined(USE_PWM_OUTPUT) || defined(USE_DSHOT) bool useUnsyncedPwm = motorDevConfig->useUnsyncedPwm; +#else + UNUSED(idlePulse); + UNUSED(motorDevConfig); +#endif if (isMotorProtocolEnabled()) { - if (!isMotorProtocolDshot()) { - motorDevice = motorPwmDevInit(motorDevConfig, idlePulse, motorCount, useUnsyncedPwm); - } + do { + if (!isMotorProtocolDshot()) { +#ifdef USE_PWM_OUTPUT + motorDevice = motorPwmDevInit(motorDevConfig, idlePulse, motorCount, useUnsyncedPwm); +#endif + break; + } #ifdef USE_DSHOT - else { #ifdef USE_DSHOT_BITBANG if (isDshotBitbangActive(motorDevConfig)) { motorDevice = dshotBitbangDevInit(motorDevConfig, motorCount); - } else -#endif - { - motorDevice = dshotPwmDevInit(motorDevConfig, idlePulse, motorCount, useUnsyncedPwm); + break; } - } #endif + motorDevice = dshotPwmDevInit(motorDevConfig, idlePulse, motorCount, useUnsyncedPwm); +#endif + } while(0); } if (motorDevice) { diff --git a/src/platform/APM32/pwm_output_apm32.c b/src/platform/APM32/pwm_output_apm32.c index 7a3ce77f32..c0f40dd948 100644 --- a/src/platform/APM32/pwm_output_apm32.c +++ b/src/platform/APM32/pwm_output_apm32.c @@ -155,6 +155,8 @@ static motorVTable_t motorPwmVTable = { motorDevice_t *motorPwmDevInit(const motorDevConfig_t *motorConfig, uint16_t idlePulse, uint8_t motorCount, bool useUnsyncedPwm) { + memset(motors, 0, sizeof(motors)); + motorPwmDevice.vTable = motorPwmVTable; float sMin = 0; diff --git a/src/platform/AT32/dshot_bitbang.c b/src/platform/AT32/dshot_bitbang.c index a57b65f4c8..9ea68bba43 100644 --- a/src/platform/AT32/dshot_bitbang.c +++ b/src/platform/AT32/dshot_bitbang.c @@ -756,7 +756,7 @@ motorDevice_t *dshotBitbangDevInit(const motorDevConfig_t *motorConfig, uint8_t IOHi(io); } - // Fill in motors structure for 4way access (XXX Should be refactored) + // Fill in motors structure for 4way access (TODO: Should be refactored) motors[motorIndex].io = bbMotors[motorIndex].io; } diff --git a/src/platform/AT32/pwm_output_at32bsp.c b/src/platform/AT32/pwm_output_at32bsp.c index 8be48f3179..62a4e4ac6b 100644 --- a/src/platform/AT32/pwm_output_at32bsp.c +++ b/src/platform/AT32/pwm_output_at32bsp.c @@ -151,6 +151,8 @@ static motorVTable_t motorPwmVTable = { motorDevice_t *motorPwmDevInit(const motorDevConfig_t *motorConfig, uint16_t idlePulse, uint8_t motorCount, bool useUnsyncedPwm) { + memset(motors, 0, sizeof(motors)); + motorPwmDevice.vTable = motorPwmVTable; float sMin = 0; diff --git a/src/platform/STM32/pwm_output.c b/src/platform/STM32/pwm_output.c index 0e7f5b2f8a..3def265a14 100644 --- a/src/platform/STM32/pwm_output.c +++ b/src/platform/STM32/pwm_output.c @@ -183,6 +183,8 @@ static motorVTable_t motorPwmVTable = { motorDevice_t *motorPwmDevInit(const motorDevConfig_t *motorConfig, uint16_t idlePulse, uint8_t motorCount, bool useUnsyncedPwm) { + memset(motors, 0, sizeof(motors)); + motorPwmDevice.vTable = motorPwmVTable; float sMin = 0; From 8966558d3e8f91b63521958a48c05e43569c6627 Mon Sep 17 00:00:00 2001 From: Jacob Dahl <37091262+dakejahl@users.noreply.github.com> Date: Mon, 13 Jan 2025 05:57:05 -0900 Subject: [PATCH 041/244] h7: spi: SPI1 MISO add PG9 as AF option (#14144) --- src/platform/common/stm32/bus_spi_pinconfig.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/platform/common/stm32/bus_spi_pinconfig.c b/src/platform/common/stm32/bus_spi_pinconfig.c index 10c6d76ae2..ee59d7cd24 100644 --- a/src/platform/common/stm32/bus_spi_pinconfig.c +++ b/src/platform/common/stm32/bus_spi_pinconfig.c @@ -184,6 +184,7 @@ const spiHardware_t spiHardware[] = { .misoPins = { { DEFIO_TAG_E(PA6), GPIO_AF5_SPI1 }, { DEFIO_TAG_E(PB4), GPIO_AF5_SPI1 }, + { DEFIO_TAG_E(PG9), GPIO_AF5_SPI1 }, }, .mosiPins = { { DEFIO_TAG_E(PA7), GPIO_AF5_SPI1 }, From b7bd378f9c7c3bd8b2162d8435405164fde92e64 Mon Sep 17 00:00:00 2001 From: Jacob Dahl <37091262+dakejahl@users.noreply.github.com> Date: Mon, 13 Jan 2025 06:12:05 -0900 Subject: [PATCH 042/244] h7: sdmmc: add SDIO_USE_PULLUP option for config.h (#14147) --- src/platform/STM32/sdio_h7xx.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/platform/STM32/sdio_h7xx.c b/src/platform/STM32/sdio_h7xx.c index a5d1bb5aff..554b832cb5 100644 --- a/src/platform/STM32/sdio_h7xx.c +++ b/src/platform/STM32/sdio_h7xx.c @@ -160,7 +160,11 @@ void sdioPinConfigure(void) #undef SDIOFINDPIN +#if defined(USE_SDIO_PULLUP) +#define IOCFG_SDMMC IO_CONFIG(GPIO_MODE_AF_PP, GPIO_SPEED_FREQ_VERY_HIGH, GPIO_PULLUP) +#else #define IOCFG_SDMMC IO_CONFIG(GPIO_MODE_AF_PP, GPIO_SPEED_FREQ_VERY_HIGH, GPIO_NOPULL) +#endif void HAL_SD_MspInit(SD_HandleTypeDef* hsd) { From 889aa9f9dac8a2fa38e327145955db4ee11d9894 Mon Sep 17 00:00:00 2001 From: Jacob Dahl <37091262+dakejahl@users.noreply.github.com> Date: Mon, 13 Jan 2025 07:35:51 -0900 Subject: [PATCH 043/244] h7: sdmmc: add PG11 for SDIO_D2_PIN (#14146) h7: sdmmc: add AF options --- src/platform/STM32/sdio_h7xx.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/src/platform/STM32/sdio_h7xx.c b/src/platform/STM32/sdio_h7xx.c index 554b832cb5..8d643672bb 100644 --- a/src/platform/STM32/sdio_h7xx.c +++ b/src/platform/STM32/sdio_h7xx.c @@ -103,12 +103,12 @@ static const sdioHardware_t sdioPinHardware[SDIODEV_COUNT] = { { .instance = SDMMC2, .irqn = SDMMC2_IRQn, - .sdioPinCK = { PINDEF(2, PC1, 9), PINDEF(2, PD6, 11) }, - .sdioPinCMD = { PINDEF(2, PA0, 9), PINDEF(2, PD7, 11) }, - .sdioPinD0 = { PINDEF(2, PB14, 9) }, - .sdioPinD1 = { PINDEF(2, PB15, 9) }, - .sdioPinD2 = { PINDEF(2, PB3, 9) }, - .sdioPinD3 = { PINDEF(2, PB4, 9) }, + .sdioPinCK = { PINDEF(2, PC1, 9), PINDEF(2, PD6, 11) }, + .sdioPinCMD = { PINDEF(2, PA0, 9), PINDEF(2, PD7, 11) }, + .sdioPinD0 = { PINDEF(2, PB14, 9), }, + .sdioPinD1 = { PINDEF(2, PB15, 9), }, + .sdioPinD2 = { PINDEF(2, PB3, 9), PINDEF(2, PG11, 10) }, + .sdioPinD3 = { PINDEF(2, PB4, 9), }, } }; From 2163e44df344b419ca56443d1f9e5fc1d028f7a7 Mon Sep 17 00:00:00 2001 From: Steve Evans Date: Tue, 14 Jan 2025 13:06:22 +0000 Subject: [PATCH 044/244] Don't waste time displaying an empty OSD string (#14152) --- src/main/drivers/display.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/main/drivers/display.c b/src/main/drivers/display.c index d9b90bf387..fc2ce74709 100644 --- a/src/main/drivers/display.c +++ b/src/main/drivers/display.c @@ -93,6 +93,12 @@ int displayWrite(displayPort_t *instance, uint8_t x, uint8_t y, uint8_t attr, co { instance->posX = x + strlen(text); instance->posY = y; + + if (strlen(text) == 0) { + // No point sending a message to do nothing + return 0; + } + return instance->vTable->writeString(instance, x, y, attr, text); } From 4a6e3bbe0643f2fa4c7366a162a6d871106354cf Mon Sep 17 00:00:00 2001 From: Jacob Dahl <37091262+dakejahl@users.noreply.github.com> Date: Tue, 14 Jan 2025 10:38:37 -0900 Subject: [PATCH 045/244] lis2mdl: fix align define typo (#14154) --- src/main/sensors/compass.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/sensors/compass.c b/src/main/sensors/compass.c index f5fdcaed61..e5f5c9332f 100644 --- a/src/main/sensors/compass.c +++ b/src/main/sensors/compass.c @@ -237,7 +237,7 @@ bool compassDetect(magDev_t *magDev, uint8_t *alignment) } if (lis2mdlDetect(magDev)) { -#ifdef MAG_LIS3MDL_ALIGN +#ifdef MAG_LIS2MDL_ALIGN *alignment = MAG_LIS2MDL_ALIGN; #endif magHardware = MAG_LIS2MDL; From 7a44f1bdce530e0dbf36c3a6acc794914bd3f790 Mon Sep 17 00:00:00 2001 From: Jacob Dahl <37091262+dakejahl@users.noreply.github.com> Date: Tue, 14 Jan 2025 12:11:25 -0900 Subject: [PATCH 046/244] Add IIM42653 IMU support (#14095) * drivers: accgyro: iim42653 IMU support * reorder accgyro enums, update comment about IIM42653 * remove comma after VIRTUAL in enum --- src/main/cli/settings.c | 2 ++ src/main/drivers/accgyro/accgyro.h | 1 + src/main/drivers/accgyro/accgyro_mpu.c | 2 +- src/main/drivers/accgyro/accgyro_mpu.h | 4 +++ .../drivers/accgyro/accgyro_spi_icm426xx.c | 36 ++++++++++++------- src/main/sensors/acceleration.h | 1 + src/main/sensors/acceleration_init.c | 6 +++- src/main/sensors/gyro_init.c | 7 +++- src/main/target/common_post.h | 10 +++--- src/main/target/common_pre.h | 1 + 10 files changed, 51 insertions(+), 19 deletions(-) diff --git a/src/main/cli/settings.c b/src/main/cli/settings.c index ebc5b894e4..243317c808 100644 --- a/src/main/cli/settings.c +++ b/src/main/cli/settings.c @@ -160,6 +160,7 @@ const char * const lookupTableAccHardware[] = { "BMI270", "LSM6DSO", "LSM6DSV16X", + "IIM42653", "VIRTUAL" }; @@ -183,6 +184,7 @@ const char * const lookupTableGyroHardware[] = { "BMI270", "LSM6DSO", "LSM6DSV16X", + "IIM42653", "VIRTUAL" }; diff --git a/src/main/drivers/accgyro/accgyro.h b/src/main/drivers/accgyro/accgyro.h index 0c63a8258f..51a7672b1f 100644 --- a/src/main/drivers/accgyro/accgyro.h +++ b/src/main/drivers/accgyro/accgyro.h @@ -61,6 +61,7 @@ typedef enum { GYRO_BMI270, GYRO_LSM6DSO, GYRO_LSM6DSV16X, + GYRO_IIM42653, GYRO_VIRTUAL } gyroHardware_e; diff --git a/src/main/drivers/accgyro/accgyro_mpu.c b/src/main/drivers/accgyro/accgyro_mpu.c index 5e37cd5286..1f1943dc3b 100644 --- a/src/main/drivers/accgyro/accgyro_mpu.c +++ b/src/main/drivers/accgyro/accgyro_mpu.c @@ -365,7 +365,7 @@ static gyroSpiDetectFn_t gyroSpiDetectFnTable[] = { #ifdef USE_ACCGYRO_BMI270 bmi270Detect, #endif -#if defined(USE_GYRO_SPI_ICM42605) || defined(USE_GYRO_SPI_ICM42688P) +#if defined(USE_GYRO_SPI_ICM42605) || defined(USE_GYRO_SPI_ICM42688P) || defined(USE_ACCGYRO_IIM42653) icm426xxSpiDetect, #endif #ifdef USE_GYRO_SPI_ICM20649 diff --git a/src/main/drivers/accgyro/accgyro_mpu.h b/src/main/drivers/accgyro/accgyro_mpu.h index eebb76e8f2..3c06a02ba2 100644 --- a/src/main/drivers/accgyro/accgyro_mpu.h +++ b/src/main/drivers/accgyro/accgyro_mpu.h @@ -45,6 +45,7 @@ #define ICM20689_WHO_AM_I_CONST (0x98) #define ICM42605_WHO_AM_I_CONST (0x42) #define ICM42688P_WHO_AM_I_CONST (0x47) +#define IIM42653_WHO_AM_I_CONST (0x56) #define LSM6DSV16X_WHO_AM_I_CONST (0x70) // RA = Register Address @@ -146,6 +147,7 @@ enum gyro_fsr_e { INV_FSR_500DPS, INV_FSR_1000DPS, INV_FSR_2000DPS, + INV_FSR_4000DPS, NUM_GYRO_FSR }; @@ -168,6 +170,7 @@ enum accel_fsr_e { INV_FSR_4G, INV_FSR_8G, INV_FSR_16G, + INV_FSR_32G, NUM_ACCEL_FSR }; @@ -201,6 +204,7 @@ typedef enum { ICM_20689_SPI, ICM_42605_SPI, ICM_42688P_SPI, + IIM_42653_SPI, BMI_160_SPI, BMI_270_SPI, LSM6DSO_SPI, diff --git a/src/main/drivers/accgyro/accgyro_spi_icm426xx.c b/src/main/drivers/accgyro/accgyro_spi_icm426xx.c index 1063ae4eef..29dabbcb98 100644 --- a/src/main/drivers/accgyro/accgyro_spi_icm426xx.c +++ b/src/main/drivers/accgyro/accgyro_spi_icm426xx.c @@ -28,7 +28,7 @@ #include "platform.h" -#if defined(USE_GYRO_SPI_ICM42605) || defined(USE_GYRO_SPI_ICM42688P) +#if defined(USE_GYRO_SPI_ICM42605) || defined(USE_GYRO_SPI_ICM42688P) || defined(USE_ACCGYRO_IIM42653) #include "common/axis.h" #include "common/utils.h" @@ -269,6 +269,9 @@ uint8_t icm426xxSpiDetect(const extDevice_t *dev) case ICM42688P_WHO_AM_I_CONST: icmDetected = ICM_42688P_SPI; break; + case IIM42653_WHO_AM_I_CONST: + icmDetected = IIM_42653_SPI; + break; default: icmDetected = MPU_NONE; break; @@ -286,15 +289,22 @@ uint8_t icm426xxSpiDetect(const extDevice_t *dev) void icm426xxAccInit(accDev_t *acc) { - acc->acc_1G = 512 * 4; + switch (acc->mpuDetectionResult.sensor) { + case IIM_42653_SPI: + acc->acc_1G = 512 * 2; // Accel scale 32g (1024 LSB/g) + break; + default: + acc->acc_1G = 512 * 4; // Accel scale 16g (2048 LSB/g) + break; + } } bool icm426xxSpiAccDetect(accDev_t *acc) { switch (acc->mpuDetectionResult.sensor) { case ICM_42605_SPI: - break; case ICM_42688P_SPI: + case IIM_42653_SPI: break; default: return false; @@ -386,12 +396,12 @@ void icm426xxGyroInit(gyroDev_t *gyro) gyro->gyroRateKHz = GYRO_RATE_1_kHz; } - STATIC_ASSERT(INV_FSR_2000DPS == 3, "INV_FSR_2000DPS must be 3 to generate correct value"); - spiWriteReg(dev, ICM426XX_RA_GYRO_CONFIG0, (3 - INV_FSR_2000DPS) << 5 | (odrConfig & 0x0F)); + // This sets the gyro/accel to the maximum FSR, depending on the chip + // ICM42605, ICM_42688P: 2000DPS and 16G. + // IIM42653: 4000DPS and 32G + spiWriteReg(dev, ICM426XX_RA_GYRO_CONFIG0, (0 << 5) | (odrConfig & 0x0F)); delay(15); - - STATIC_ASSERT(INV_FSR_16G == 3, "INV_FSR_16G must be 3 to generate correct value"); - spiWriteReg(dev, ICM426XX_RA_ACCEL_CONFIG0, (3 - INV_FSR_16G) << 5 | (odrConfig & 0x0F)); + spiWriteReg(dev, ICM426XX_RA_ACCEL_CONFIG0, (0 << 5) | (odrConfig & 0x0F)); delay(15); } @@ -399,8 +409,11 @@ bool icm426xxSpiGyroDetect(gyroDev_t *gyro) { switch (gyro->mpuDetectionResult.sensor) { case ICM_42605_SPI: - break; case ICM_42688P_SPI: + gyro->scale = GYRO_SCALE_2000DPS; + break; + case IIM_42653_SPI: + gyro->scale = GYRO_SCALE_4000DPS; break; default: return false; @@ -409,8 +422,6 @@ bool icm426xxSpiGyroDetect(gyroDev_t *gyro) gyro->initFn = icm426xxGyroInit; gyro->readFn = mpuGyroReadSPI; - gyro->scale = GYRO_SCALE_2000DPS; - return true; } @@ -430,6 +441,7 @@ static aafConfig_t getGyroAafConfig(const mpuSensor_e gyroModel, const aafConfig } case ICM_42688P_SPI: + case IIM_42653_SPI: default: switch (config) { case GYRO_HARDWARE_LPF_NORMAL: @@ -448,4 +460,4 @@ static aafConfig_t getGyroAafConfig(const mpuSensor_e gyroModel, const aafConfig } } -#endif // USE_GYRO_SPI_ICM42605 || USE_GYRO_SPI_ICM42688P +#endif // USE_GYRO_SPI_ICM42605 || USE_GYRO_SPI_ICM42688P || USE_ACCGYRO_IIM42653 diff --git a/src/main/sensors/acceleration.h b/src/main/sensors/acceleration.h index 66a139d664..2f28e6879f 100644 --- a/src/main/sensors/acceleration.h +++ b/src/main/sensors/acceleration.h @@ -50,6 +50,7 @@ typedef enum { ACC_BMI270, ACC_LSM6DSO, ACC_LSM6DSV16X, + ACC_IIM42653, ACC_VIRTUAL } accelerationSensor_e; diff --git a/src/main/sensors/acceleration_init.c b/src/main/sensors/acceleration_init.c index 127ea4a80c..812ab21f6d 100644 --- a/src/main/sensors/acceleration_init.c +++ b/src/main/sensors/acceleration_init.c @@ -216,9 +216,10 @@ retry: FALLTHROUGH; #endif -#if defined(USE_ACC_SPI_ICM42605) || defined(USE_ACC_SPI_ICM42688P) +#if defined(USE_ACC_SPI_ICM42605) || defined(USE_ACC_SPI_ICM42688P) || defined(USE_ACCGYRO_IIM42653) case ACC_ICM42605: case ACC_ICM42688P: + case ACC_IIM42653: if (icm426xxSpiAccDetect(dev)) { switch (dev->mpuDetectionResult.sensor) { case ICM_42605_SPI: @@ -227,6 +228,9 @@ retry: case ICM_42688P_SPI: accHardware = ACC_ICM42688P; break; + case IIM_42653_SPI: + accHardware = ACC_IIM42653; + break; default: accHardware = ACC_NONE; break; diff --git a/src/main/sensors/gyro_init.c b/src/main/sensors/gyro_init.c index c09d466e5a..4ebc9153e7 100644 --- a/src/main/sensors/gyro_init.c +++ b/src/main/sensors/gyro_init.c @@ -314,6 +314,7 @@ void gyroInitSensor(gyroSensor_t *gyroSensor, const gyroDeviceConfig_t *config) case GYRO_LSM6DSO: case GYRO_LSM6DSV16X: case GYRO_ICM42688P: + case GYRO_IIM42653: case GYRO_ICM42605: gyroSensor->gyroDev.gyroHasOverflowProtection = true; break; @@ -427,9 +428,10 @@ STATIC_UNIT_TESTED gyroHardware_e gyroDetect(gyroDev_t *dev) FALLTHROUGH; #endif -#if defined(USE_GYRO_SPI_ICM42605) || defined(USE_GYRO_SPI_ICM42688P) +#if defined(USE_GYRO_SPI_ICM42605) || defined(USE_GYRO_SPI_ICM42688P) || defined(USE_ACCGYRO_IIM42653) case GYRO_ICM42605: case GYRO_ICM42688P: + case GYRO_IIM42653: if (icm426xxSpiGyroDetect(dev)) { switch (dev->mpuDetectionResult.sensor) { case ICM_42605_SPI: @@ -438,6 +440,9 @@ STATIC_UNIT_TESTED gyroHardware_e gyroDetect(gyroDev_t *dev) case ICM_42688P_SPI: gyroHardware = GYRO_ICM42688P; break; + case IIM_42653_SPI: + gyroHardware = GYRO_IIM42653; + break; default: gyroHardware = GYRO_NONE; break; diff --git a/src/main/target/common_post.h b/src/main/target/common_post.h index a69492dcf2..976ba8e7c3 100644 --- a/src/main/target/common_post.h +++ b/src/main/target/common_post.h @@ -107,7 +107,8 @@ && !defined(USE_ACC_SPI_MPU6000) \ && !defined(USE_ACC_SPI_MPU6500) \ && !defined(USE_ACC_SPI_MPU9250) \ - && !defined(USE_VIRTUAL_ACC) + && !defined(USE_VIRTUAL_ACC) \ + && !defined(USE_ACCGYRO_IIM42653) #error At least one USE_ACC device definition required #endif @@ -126,7 +127,8 @@ && !defined(USE_GYRO_SPI_MPU6000) \ && !defined(USE_GYRO_SPI_MPU6500) \ && !defined(USE_GYRO_SPI_MPU9250) \ - && !defined(USE_VIRTUAL_GYRO) + && !defined(USE_VIRTUAL_GYRO) \ + && !defined(USE_ACCGYRO_IIM42653) #error At least one USE_GYRO device definition required #endif @@ -466,8 +468,8 @@ // Generate USE_SPI_GYRO or USE_I2C_GYRO #if defined(USE_GYRO_SPI_ICM20689) || defined(USE_GYRO_SPI_MPU6000) || defined(USE_GYRO_SPI_MPU6500) || defined(USE_GYRO_SPI_MPU9250) \ - || defined(USE_GYRO_L3GD20) || defined(USE_GYRO_SPI_ICM42605) || defined(USE_GYRO_SPI_ICM42688P) || defined(USE_ACCGYRO_BMI160) \ - || defined(USE_ACCGYRO_BMI270) || defined(USE_ACCGYRO_LSM6DSV16X) || defined(USE_ACCGYRO_LSM6DSO) + || defined(USE_GYRO_L3GD20) || defined(USE_GYRO_SPI_ICM42605) || defined(USE_GYRO_SPI_ICM42688P) || defined(USE_ACCGYRO_IIM42653) \ + || defined(USE_ACCGYRO_BMI160) || defined(USE_ACCGYRO_BMI270) || defined(USE_ACCGYRO_LSM6DSV16X) || defined(USE_ACCGYRO_LSM6DSO) #ifndef USE_SPI_GYRO #define USE_SPI_GYRO #endif diff --git a/src/main/target/common_pre.h b/src/main/target/common_pre.h index 0db3a0d1dc..1220594f3d 100644 --- a/src/main/target/common_pre.h +++ b/src/main/target/common_pre.h @@ -114,6 +114,7 @@ #define USE_ACCGYRO_BMI270 #define USE_GYRO_SPI_ICM42605 #define USE_GYRO_SPI_ICM42688P +#define USE_ACCGYRO_IIM42653 #define USE_ACC_SPI_ICM42605 #define USE_ACC_SPI_ICM42688P #define USE_ACCGYRO_LSM6DSV16X From 029f2eea81ff55b8e5452d00c04ad3ba86f6496f Mon Sep 17 00:00:00 2001 From: Jacob Dahl <37091262+dakejahl@users.noreply.github.com> Date: Tue, 14 Jan 2025 12:36:34 -0900 Subject: [PATCH 047/244] mag: lis2mdl: fix axes (#14155) * mag: lis2mdl: fix axes from LH to RH, match LIS3MDL axes * fix spelling Co-authored-by: Mark Haslinghuis --------- Co-authored-by: Mark Haslinghuis --- src/main/drivers/compass/compass_lis2mdl.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/src/main/drivers/compass/compass_lis2mdl.c b/src/main/drivers/compass/compass_lis2mdl.c index fb97536abd..c6c3f27a17 100644 --- a/src/main/drivers/compass/compass_lis2mdl.c +++ b/src/main/drivers/compass/compass_lis2mdl.c @@ -136,9 +136,15 @@ static bool lis2mdlRead(magDev_t * mag, int16_t *magData) return false; } - magData[X] = (int16_t)(buf[1] << 8 | buf[0]); - magData[Y] = (int16_t)(buf[3] << 8 | buf[2]); - magData[Z] = (int16_t)(buf[5] << 8 | buf[4]); + int16_t x = (int16_t)(buf[1] << 8 | buf[0]); + int16_t y = (int16_t)(buf[3] << 8 | buf[2]); + int16_t z = (int16_t)(buf[5] << 8 | buf[4]); + + // adapt LIS2MDL left-handed frame to common sensor axis orientation (match LIS3MDL) + // pin 1 mark becomes +X -Y + magData[X] = -x; + magData[Y] = y; + magData[Z] = z; pendingRead = true; From bdd2a2863d5682e5994498a9926cabd309e4c079 Mon Sep 17 00:00:00 2001 From: Vladimir Demidov Date: Wed, 15 Jan 2025 00:42:58 +0300 Subject: [PATCH 048/244] The imitation of GPS is added for SITL (#14131) * virtual gps module is added * USE_VIRTUAL_GPS definition is added to sitl/target.h * Virtual GPS using are added into sitl and gps modules * Added settings values for lat, lon, alt, speed, speed3D, course in SITL * setVirtualGPS function parameters are changed to double * Code style improvement Co-authored-by: Petr Ledvina * code style improvement: undue space symbol deleted Co-authored-by: Petr Ledvina * Code style improvement Co-authored-by: Petr Ledvina * Code style improvement * The getVirtualGPS() function declarations is edited * getVirtualGPS() functions declaration improvement * Code style improvement Co-authored-by: Petr Ledvina * define USE_VIRTUAL_GPS is removed from sitl/target.h * Revert "define USE_VIRTUAL_GPS is removed from sitl/target.h" This reverts commit 2e610339c4f4c9fef3008e03e08a5cf38375da0a. * virtual gps for SITL is made as special GPS_VIRTUAL provider * Code style improvement. The LF code symbol is added Co-authored-by: Mark Haslinghuis * the license is changed * The license is edited in gps_virtual.c Co-authored-by: Mark Haslinghuis * The license is edited in gps_virtual.h Co-authored-by: Mark Haslinghuis * Code style improvement * Virtual gps provider work improvement * Code style improvement Co-authored-by: Petr Ledvina * Code style improvement Co-authored-by: Petr Ledvina * Code refactoring in io/gps.c * SITL define issue is resolved Co-authored-by: Mark Haslinghuis * Extra line is removed Co-authored-by: Mark Haslinghuis * The VIRTUAL option is added into cli looktable * switch case tab alignment refactoring in io\gps.c * wrong indent resolved * bugfix NMEA and UBLOX GPS mode for SITL (SIMULATOR_BUILD) builds target --------- Co-authored-by: Petr Ledvina Co-authored-by: Mark Haslinghuis --- src/main/cli/settings.c | 2 +- src/main/drivers/serial.c | 5 +- src/main/flight/imu.c | 8 +- src/main/io/gps.c | 112 +++++++++++++------ src/main/io/gps.h | 3 +- src/main/io/gps_virtual.c | 52 +++++++++ src/main/io/gps_virtual.h | 26 +++++ src/main/pg/gps.c | 4 + src/platform/SIMULATOR/sitl.c | 16 +++ src/platform/SIMULATOR/target/SITL/target.h | 8 +- src/platform/SIMULATOR/target/SITL/target.mk | 3 +- 11 files changed, 200 insertions(+), 39 deletions(-) create mode 100644 src/main/io/gps_virtual.c create mode 100644 src/main/io/gps_virtual.h diff --git a/src/main/cli/settings.c b/src/main/cli/settings.c index 243317c808..3e79fc4d78 100644 --- a/src/main/cli/settings.c +++ b/src/main/cli/settings.c @@ -244,7 +244,7 @@ static const char * const lookupTableGyro[] = { #ifdef USE_GPS static const char * const lookupTableGpsProvider[] = { - "NMEA", "UBLOX", "MSP" + "NMEA", "UBLOX", "MSP", "VIRTUAL" }; static const char * const lookupTableGpsSbasMode[] = { diff --git a/src/main/drivers/serial.c b/src/main/drivers/serial.c index ea772a6cb0..6fae5d7e59 100644 --- a/src/main/drivers/serial.c +++ b/src/main/drivers/serial.c @@ -76,7 +76,10 @@ uint8_t serialRead(serialPort_t *instance) void serialSetBaudRate(serialPort_t *instance, uint32_t baudRate) { - instance->vTable->serialSetBaudRate(instance, baudRate); + //vTable->serialSetBaudRate is NULL for SIMULATOR_BUILD, because the TCP port is used + if (instance->vTable->serialSetBaudRate != NULL) { + instance->vTable->serialSetBaudRate(instance, baudRate); + } } bool isSerialTransmitBufferEmpty(const serialPort_t *instance) diff --git a/src/main/flight/imu.c b/src/main/flight/imu.c index 014052cf56..894658f368 100644 --- a/src/main/flight/imu.c +++ b/src/main/flight/imu.c @@ -603,8 +603,14 @@ static void imuCalculateEstimatedAttitude(timeUs_t currentTimeUs) UNUSED(canUseGPSHeading); UNUSED(imuCalcKpGain); UNUSED(imuCalcMagErr); - UNUSED(currentTimeUs); + +#if defined(USE_GPS) + UNUSED(imuComputeQuaternionFromRPY); + UNUSED(imuDebug_GPS_RESCUE_HEADING); + UNUSED(imuCalcCourseErr); + UNUSED(imuCalcGroundspeedGain); +#endif } #else diff --git a/src/main/io/gps.c b/src/main/io/gps.c index 29a80ec3d4..4584360d07 100644 --- a/src/main/io/gps.c +++ b/src/main/io/gps.c @@ -45,7 +45,10 @@ #ifdef USE_DASHBOARD #include "io/dashboard.h" #endif + #include "io/gps.h" +#include "io/gps_virtual.h" + #include "io/serial.h" #include "config/config.h" @@ -407,7 +410,7 @@ void gpsInit(void) // init gpsData structure. if we're not actually enabled, don't bother doing anything else gpsSetState(GPS_STATE_UNKNOWN); - if (gpsConfig()->provider == GPS_MSP) { // no serial ports used when GPS_MSP is configured + if (gpsConfig()->provider == GPS_MSP || gpsConfig()->provider == GPS_VIRTUAL) { // no serial ports used when GPS_MSP or GPS_VIRTUAL is configured gpsSetState(GPS_STATE_INITIALIZED); return; } @@ -1337,6 +1340,38 @@ static void calculateNavInterval (void) gpsSol.navIntervalMs = constrain(navDeltaTimeMs, 50, 2500); } +#if defined(USE_VIRTUAL_GPS) +static void updateVirtualGPS(void) +{ + const uint32_t updateInterval = 100; // 100ms 10Hz update time interval + static uint32_t nextUpdateTime = 0; + + if (cmp32(gpsData.now, nextUpdateTime) > 0) { + if (gpsData.state == GPS_STATE_INITIALIZED) { + gpsSetState(GPS_STATE_RECEIVING_DATA); + } + + getVirtualGPS(&gpsSol); + gpsSol.time = gpsData.now; + + gpsData.lastNavMessage = gpsData.now; + sensorsSet(SENSOR_GPS); + + if (gpsSol.numSat > 3) { + gpsSetFixState(GPS_FIX); + } else { + gpsSetFixState(0); + } + GPS_update ^= GPS_DIRECT_TICK; + + calculateNavInterval(); + onGpsNewData(); + + nextUpdateTime = gpsData.now + updateInterval; + } +} +#endif + void gpsUpdate(timeUs_t currentTimeUs) { static timeDelta_t gpsStateDurationFractionUs[GPS_STATE_COUNT]; @@ -1344,7 +1379,12 @@ void gpsUpdate(timeUs_t currentTimeUs) gpsState_e gpsCurrentState = gpsData.state; gpsData.now = millis(); - if (gpsPort) { + switch (gpsConfig()->provider) { + case GPS_UBLOX: + case GPS_NMEA: + if (!gpsPort) { + break; + } DEBUG_SET(DEBUG_GPS_CONNECTION, 7, serialRxBytesWaiting(gpsPort)); static uint8_t wait = 0; static bool isFast = false; @@ -1368,7 +1408,9 @@ void gpsUpdate(timeUs_t currentTimeUs) isFast = false; rescheduleTask(TASK_SELF, TASK_PERIOD_HZ(TASK_GPS_RATE)); } - } else if (gpsConfig()->provider == GPS_MSP) { + break; + + case GPS_MSP: if (GPS_update & GPS_MSP_UPDATE) { // GPS data received via MSP if (gpsData.state == GPS_STATE_INITIALIZED) { gpsSetState(GPS_STATE_RECEIVING_DATA); @@ -1391,45 +1433,51 @@ void gpsUpdate(timeUs_t currentTimeUs) gpsSetState(GPS_STATE_LOST_COMMUNICATION); } } + break; +#if defined(USE_VIRTUAL_GPS) + case GPS_VIRTUAL: + updateVirtualGPS(); + break; +#endif } switch (gpsData.state) { - case GPS_STATE_UNKNOWN: - case GPS_STATE_INITIALIZED: - break; + case GPS_STATE_UNKNOWN: + case GPS_STATE_INITIALIZED: + break; - case GPS_STATE_DETECT_BAUD: - case GPS_STATE_CHANGE_BAUD: - case GPS_STATE_CONFIGURE: - gpsConfigureHardware(); - break; + case GPS_STATE_DETECT_BAUD: + case GPS_STATE_CHANGE_BAUD: + case GPS_STATE_CONFIGURE: + gpsConfigureHardware(); + break; - case GPS_STATE_LOST_COMMUNICATION: - gpsData.timeouts++; - // previously we would attempt a different baud rate here if gps auto-baud was enabled. that code has been removed. - gpsSol.numSat = 0; - DISABLE_STATE(GPS_FIX); - gpsSetState(GPS_STATE_DETECT_BAUD); - break; + case GPS_STATE_LOST_COMMUNICATION: + gpsData.timeouts++; + // previously we would attempt a different baud rate here if gps auto-baud was enabled. that code has been removed. + gpsSol.numSat = 0; + DISABLE_STATE(GPS_FIX); + gpsSetState(GPS_STATE_DETECT_BAUD); + break; - case GPS_STATE_RECEIVING_DATA: + case GPS_STATE_RECEIVING_DATA: #ifdef USE_GPS_UBLOX - if (gpsConfig()->provider != GPS_MSP) { - if (gpsConfig()->autoConfig == GPS_AUTOCONFIG_ON) { - // when we are connected up, and get a 3D fix, enable the 'flight' fix model - if (!gpsData.ubloxUsingFlightModel && STATE(GPS_FIX)) { - gpsData.ubloxUsingFlightModel = true; - ubloxSendNAV5Message(gpsConfig()->gps_ublox_flight_model); - } + if (gpsConfig()->provider == GPS_UBLOX || gpsConfig()->provider == GPS_NMEA) { // TODO Send ublox message to nmea GPS? + if (gpsConfig()->autoConfig == GPS_AUTOCONFIG_ON) { + // when we are connected up, and get a 3D fix, enable the 'flight' fix model + if (!gpsData.ubloxUsingFlightModel && STATE(GPS_FIX)) { + gpsData.ubloxUsingFlightModel = true; + ubloxSendNAV5Message(gpsConfig()->gps_ublox_flight_model); } } + } #endif - DEBUG_SET(DEBUG_GPS_CONNECTION, 2, gpsData.now - gpsData.lastNavMessage); // time since last Nav data, updated each GPS task interval - // check for no data/gps timeout/cable disconnection etc - if (cmp32(gpsData.now, gpsData.lastNavMessage) > GPS_TIMEOUT_MS) { - gpsSetState(GPS_STATE_LOST_COMMUNICATION); - } - break; + DEBUG_SET(DEBUG_GPS_CONNECTION, 2, gpsData.now - gpsData.lastNavMessage); // time since last Nav data, updated each GPS task interval + // check for no data/gps timeout/cable disconnection etc + if (cmp32(gpsData.now, gpsData.lastNavMessage) > GPS_TIMEOUT_MS) { + gpsSetState(GPS_STATE_LOST_COMMUNICATION); + } + break; } DEBUG_SET(DEBUG_GPS_CONNECTION, 4, (gpsData.state * 100 + gpsData.state_position)); diff --git a/src/main/io/gps.h b/src/main/io/gps.h index c80b9e8f46..fb88128900 100644 --- a/src/main/io/gps.h +++ b/src/main/io/gps.h @@ -177,7 +177,8 @@ typedef enum { typedef enum { GPS_NMEA = 0, GPS_UBLOX, - GPS_MSP + GPS_MSP, + GPS_VIRTUAL, } gpsProvider_e; typedef enum { diff --git a/src/main/io/gps_virtual.c b/src/main/io/gps_virtual.c new file mode 100644 index 0000000000..3f65fca8f2 --- /dev/null +++ b/src/main/io/gps_virtual.c @@ -0,0 +1,52 @@ +/* + * This file is part of Betaflight. + * + * Betaflight is free software. You can redistribute this software + * and/or modify this software under the terms of the GNU General + * Public License as published by the Free Software Foundation, + * either version 3 of the License, or (at your option) any later + * version. + * + * Betaflight is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * See the GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this software. + * + * If not, see . + */ + +#include +#include + +#include "platform.h" + +#ifdef USE_VIRTUAL_GPS + +#include "io/gps_virtual.h" + +static gpsSolutionData_t gpsVirtualData; + +void setVirtualGPS(double latitude, double longitude, double altiutude, double speed, double speed3D, double course) +{ + gpsVirtualData.numSat = 12; // satellites_in_view + gpsVirtualData.acc.hAcc = 500; // horizontal_pos_accuracy - convert cm to mm + gpsVirtualData.acc.vAcc = 500; // vertical_pos_accuracy - convert cm to mm + gpsVirtualData.acc.sAcc = 400; // horizontal_vel_accuracy - convert cm to mm + gpsVirtualData.dop.pdop = 10; // hdop in 4.4 and earlier, pdop in 4.5 and above + gpsVirtualData.llh.lon = (int32_t)(longitude * GPS_DEGREES_DIVIDER); + gpsVirtualData.llh.lat = (int32_t)(latitude * GPS_DEGREES_DIVIDER); + gpsVirtualData.llh.altCm = (int32_t)(altiutude * 100.0); // alt, cm + gpsVirtualData.groundSpeed = (uint16_t)(speed * 100.0); // cm/sec + gpsVirtualData.speed3d = (uint16_t)(speed3D * 100.0); // cm/sec + gpsVirtualData.groundCourse = (uint16_t)(course * 10.0); // decidegrees +} + +void getVirtualGPS(gpsSolutionData_t *gpsSolData) +{ + *gpsSolData = gpsVirtualData; +} +#endif diff --git a/src/main/io/gps_virtual.h b/src/main/io/gps_virtual.h new file mode 100644 index 0000000000..6f53b7c4a5 --- /dev/null +++ b/src/main/io/gps_virtual.h @@ -0,0 +1,26 @@ +/* + * This file is part of Betaflight. + * + * Betaflight is free software. You can redistribute this software + * and/or modify this software under the terms of the GNU General + * Public License as published by the Free Software Foundation, + * either version 3 of the License, or (at your option) any later + * version. + * + * Betaflight is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * See the GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this software. + * + * If not, see . + */ + +#pragma once + +#include "io/gps.h" +void setVirtualGPS(double latitude, double longitude, double altiutude, double velocity, double velocity3D, double course); +void getVirtualGPS(gpsSolutionData_t *gpsSolData); diff --git a/src/main/pg/gps.c b/src/main/pg/gps.c index d7d7b202ab..81f9e0e396 100644 --- a/src/main/pg/gps.c +++ b/src/main/pg/gps.c @@ -32,7 +32,11 @@ PG_REGISTER_WITH_RESET_TEMPLATE(gpsConfig_t, gpsConfig, PG_GPS_CONFIG, 4); PG_RESET_TEMPLATE(gpsConfig_t, gpsConfig, +#if defined(SIMULATOR_BUILD) && defined(USE_VIRTUAL_GPS) + .provider = GPS_VIRTUAL, +#else .provider = GPS_UBLOX, +#endif .sbasMode = SBAS_NONE, .autoConfig = GPS_AUTOCONFIG_ON, .autoBaud = GPS_AUTOBAUD_OFF, diff --git a/src/platform/SIMULATOR/sitl.c b/src/platform/SIMULATOR/sitl.c index 65752866c6..4a7ab2daca 100644 --- a/src/platform/SIMULATOR/sitl.c +++ b/src/platform/SIMULATOR/sitl.c @@ -57,6 +57,9 @@ #include "rx/rx.h" +#include "io/gps.h" +#include "io/gps_virtual.h" + #include "dyad.h" #include "udplink.h" @@ -180,6 +183,19 @@ void updateState(const fdm_packet* pkt) #endif #endif +#if defined(USE_VIRTUAL_GPS) + const double longitude = pkt->position_xyz[0]; + const double latitude = pkt->position_xyz[1]; + const double altitude = pkt->position_xyz[2]; + const double speed = sqrt(sq(pkt->velocity_xyz[0]) + sq(pkt->velocity_xyz[1])); + const double speed3D = sqrt(sq(pkt->velocity_xyz[0]) + sq(pkt->velocity_xyz[1]) + sq(pkt->velocity_xyz[2])); + double course = atan2(pkt->velocity_xyz[0], pkt->velocity_xyz[1]) * RAD2DEG; + if (course < 0.0) { + course += 360.0; + } + setVirtualGPS(latitude, longitude, altitude, speed, speed3D, course); +#endif + #if defined(SIMULATOR_IMU_SYNC) imuSetHasNewData(deltaSim*1e6); imuUpdateAttitude(micros()); diff --git a/src/platform/SIMULATOR/target/SITL/target.h b/src/platform/SIMULATOR/target/SITL/target.h index 5a75501c8f..6fee3baee9 100644 --- a/src/platform/SIMULATOR/target/SITL/target.h +++ b/src/platform/SIMULATOR/target/SITL/target.h @@ -95,6 +95,10 @@ #define DEFAULT_RX_FEATURE FEATURE_RX_MSP #define DEFAULT_FEATURES (FEATURE_GPS | FEATURE_TELEMETRY) +#ifdef USE_GPS +#define USE_VIRTUAL_GPS +#endif + #define USE_PARAMETER_GROUPS #ifndef USE_PWM_OUTPUT @@ -241,8 +245,8 @@ typedef struct { double imu_angular_velocity_rpy[3]; // rad/s -> range: +/- 8192; +/- 2000 deg/se double imu_linear_acceleration_xyz[3]; // m/s/s NED, body frame -> sim 1G = 9.80665, FC 1G = 256 double imu_orientation_quat[4]; //w, x, y, z - double velocity_xyz[3]; // m/s, earth frame - double position_xyz[3]; // meters, NED from origin + double velocity_xyz[3]; // m/s, earth frame. ENU (Ve, Vn, Vup) for virtual GPS mode (USE_VIRTUAL_GPS)! + double position_xyz[3]; // meters, NED from origin. Longitude, Latitude, Altitude (ENU) for virtual GPS mode (USE_VIRTUAL_GPS)! double pressure; } fdm_packet; diff --git a/src/platform/SIMULATOR/target/SITL/target.mk b/src/platform/SIMULATOR/target/SITL/target.mk index c314728e48..23d7794138 100644 --- a/src/platform/SIMULATOR/target/SITL/target.mk +++ b/src/platform/SIMULATOR/target/SITL/target.mk @@ -6,7 +6,8 @@ TARGET_SRC = \ drivers/accgyro/accgyro_virtual.c \ drivers/barometer/barometer_virtual.c \ drivers/compass/compass_virtual.c \ - drivers/serial_tcp.c + drivers/serial_tcp.c \ + io/gps_virtual.c SIZE_OPTIMISED_SRC += \ drivers/serial_tcp.c From 701ffb95d8e52af3b19aa7994482f7c72ec564f7 Mon Sep 17 00:00:00 2001 From: Steve Evans Date: Wed, 15 Jan 2025 20:34:28 +0000 Subject: [PATCH 049/244] Fix STM32G4 SPI2/SPI3 busses running at double intended clock rate (#14160) --- src/platform/STM32/bus_spi_ll.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/src/platform/STM32/bus_spi_ll.c b/src/platform/STM32/bus_spi_ll.c index 77707ad260..16ae9b5980 100644 --- a/src/platform/STM32/bus_spi_ll.c +++ b/src/platform/STM32/bus_spi_ll.c @@ -76,13 +76,16 @@ static LL_SPI_InitTypeDef defaultInit = static uint32_t spiDivisorToBRbits(const SPI_TypeDef *instance, uint16_t divisor) { -#if !defined(STM32H7) - // SPI2 and SPI3 are on APB1/AHB1 which PCLK is half that of APB2/AHB2. - +#if defined(STM32F7) + /* On F7 we run SPI2 and SPI3 (on the APB1 bus) at a division of PCLK1 which is + * half that of HCLK driving the APB2 bus and SPI1. So we need to reduce the + * division factors for SPI2/3 by a corresponding factor of 2. + */ if (instance == SPI2 || instance == SPI3) { divisor /= 2; // Safe for divisor == 0 or 1 } #else + // On the G4 and H7 processors the SPI busses are all derived from the same base frequency UNUSED(instance); #endif From 892da2d46edff7ad2e244557268309f92f7a0f60 Mon Sep 17 00:00:00 2001 From: Petr Ledvina Date: Thu, 16 Jan 2025 19:14:43 +0100 Subject: [PATCH 050/244] Add betaflight/config as submodule (#14158) --- .gitignore | 5 +++-- .gitmodules | 3 +++ mk/config.mk | 7 ++++++- src/config | 1 + 4 files changed, 13 insertions(+), 3 deletions(-) create mode 100644 .gitmodules create mode 160000 src/config diff --git a/.gitignore b/.gitignore index af249aa66c..89126f12e8 100644 --- a/.gitignore +++ b/.gitignore @@ -43,7 +43,7 @@ stm32.mak # artefacts for VS Code /.vscode/ -# artefacts for Visual Studio +# artefacts for Visual Studio /.vs # artefacts for CLion @@ -57,5 +57,6 @@ ubuntu*.log eeprom.bin # config used for building targets -/src/config +# changed to submodule +#/src/config diff --git a/.gitmodules b/.gitmodules new file mode 100644 index 0000000000..d663ecb86f --- /dev/null +++ b/.gitmodules @@ -0,0 +1,3 @@ +[submodule "config"] + path = src/config + url = https://github.com/betaflight/config.git diff --git a/mk/config.mk b/mk/config.mk index ab2386da40..0cbe356da3 100644 --- a/mk/config.mk +++ b/mk/config.mk @@ -1,6 +1,7 @@ CONFIGS_REPO_URL ?= https://github.com/betaflight/config - +# handle only this directory as config submodule +CONFIGS_SUBMODULE_DIR = src/config BASE_CONFIGS = $(sort $(notdir $(patsubst %/,%,$(dir $(wildcard $(CONFIG_DIR)/configs/*/config.h))))) ifneq ($(filter-out %_install test% %_clean clean% %-print %.hex %.h hex checks help configs $(BASE_TARGETS) $(BASE_CONFIGS),$(MAKECMDGOALS)),) @@ -50,12 +51,16 @@ endif #config .PHONY: configs configs: +ifeq ($(shell realpath $(CONFIG_DIR)),$(shell realpath $(CONFIGS_SUBMODULE_DIR))) + git submodule update --init -- $(CONFIGS_SUBMODULE_DIR) +else ifeq ($(wildcard $(CONFIG_DIR)),) @echo "Hydrating clone for configs: $(CONFIG_DIR)" $(V0) git clone $(CONFIGS_REPO_URL) $(CONFIG_DIR) else $(V0) git -C $(CONFIG_DIR) pull origin endif +endif $(BASE_CONFIGS): @echo "Building target config $@" diff --git a/src/config b/src/config new file mode 160000 index 0000000000..b0f3ab0cc9 --- /dev/null +++ b/src/config @@ -0,0 +1 @@ +Subproject commit b0f3ab0cc91f80ab930d599da03446f8c54feb8c From 83beeafb0bae397e801245c54e4a29ae1070c677 Mon Sep 17 00:00:00 2001 From: Jacob Dahl <37091262+dakejahl@users.noreply.github.com> Date: Thu, 16 Jan 2025 11:16:05 -0900 Subject: [PATCH 051/244] h7: sdio: allow custom clock divider (#14167) * add SDIO_CLOCK_DIV define to allow compatibility with a wide range of SD cards * Update src/platform/STM32/sdio_h7xx.c Co-authored-by: Petr Ledvina --------- Co-authored-by: Petr Ledvina --- src/platform/STM32/sdio_h7xx.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/src/platform/STM32/sdio_h7xx.c b/src/platform/STM32/sdio_h7xx.c index 8d643672bb..0a847898b0 100644 --- a/src/platform/STM32/sdio_h7xx.c +++ b/src/platform/STM32/sdio_h7xx.c @@ -285,11 +285,14 @@ static SD_Error_t SD_DoInit(void) hsd1.Init.BusWide = SDMMC_BUS_WIDE_1B; // FIXME untested } hsd1.Init.HardwareFlowControl = SDMMC_HARDWARE_FLOW_CONTROL_ENABLE; -#if defined(STM32H730xx) - hsd1.Init.ClockDiv = 2; // 200Mhz / (2 * 2 ) = 50Mhz, used for "UltraHigh speed SD card" only, see HAL_SD_ConfigWideBusOperation, SDMMC_HSpeed_CLK_DIV, SDMMC_NSpeed_CLK_DIV -#else - hsd1.Init.ClockDiv = 1; // 200Mhz / (2 * 1 ) = 100Mhz, used for "UltraHigh speed SD card" only, see HAL_SD_ConfigWideBusOperation, SDMMC_HSpeed_CLK_DIV, SDMMC_NSpeed_CLK_DIV +#if !defined(SDIO_CLOCK_DIV) +# if defined(STM32H730xx) +# define SDIO_CLOCK_DIV 2 // 200Mhz / (2 * 2 ) = 50Mhz, used for "UltraHigh speed SD card" only, see HAL_SD_ConfigWideBusOperation, SDMMC_HSpeed_CLK_DIV, SDMMC_NSpeed_CLK_DIV +# else +# define SDIO_CLOCK_DIV 1 // 200Mhz / (2 * 1 ) = 100Mhz, used for "UltraHigh speed SD card" only, see HAL_SD_ConfigWideBusOperation, SDMMC_HSpeed_CLK_DIV, SDMMC_NSpeed_CLK_DIV +# endif #endif + hsd1.Init.ClockDiv = SDIO_CLOCK_DIV; status = HAL_SD_Init(&hsd1); // Will call HAL_SD_MspInit if (status != HAL_OK) { From 3a2ed13ab0b21897bf45caefd51528fca29208c1 Mon Sep 17 00:00:00 2001 From: Petr Ledvina Date: Thu, 16 Jan 2025 21:16:49 +0100 Subject: [PATCH 052/244] Serial - BUGFIX - USART10 instead of UART10 (#14171) --- src/main/drivers/serial_uart.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/drivers/serial_uart.c b/src/main/drivers/serial_uart.c index 4e99137a6e..fb5c5291e3 100644 --- a/src/main/drivers/serial_uart.c +++ b/src/main/drivers/serial_uart.c @@ -490,7 +490,7 @@ UART_IRQHandler(UART, 9, UARTDEV_9) // UART9 Rx/Tx IRQ Handler #endif #ifdef USE_UART10 -UART_IRQHandler(UART, 10, UARTDEV_10) // UART10 Rx/Tx IRQ Handler +UART_IRQHandler(USART, 10, UARTDEV_10) // UART10 Rx/Tx IRQ Handler #endif #ifdef USE_LPUART1 From ca72f2724eccf2d3dc547245c43415a7316f580e Mon Sep 17 00:00:00 2001 From: Petr Ledvina Date: Thu, 16 Jan 2025 21:22:14 +0100 Subject: [PATCH 053/244] AT32 - invalid names of timer IRQ handlers (#14172) --- src/platform/AT32/timer_at32bsp.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/src/platform/AT32/timer_at32bsp.c b/src/platform/AT32/timer_at32bsp.c index 8aaf1b22c5..eb7547ebda 100644 --- a/src/platform/AT32/timer_at32bsp.c +++ b/src/platform/AT32/timer_at32bsp.c @@ -646,29 +646,29 @@ _TIM_IRQ_HANDLER(TMR7_GLOBAL_IRQHandler, 7); #endif #if USED_TIMERS & TIM_N(8) -_TIM_IRQ_HANDLER(TMR8_CH_IRQnHandler, 8); +_TIM_IRQ_HANDLER(TMR8_CH_IRQHandler, 8); #endif #if USED_TIMERS & TIM_N(9) -_TIM_IRQ_HANDLER(TMR1_BRK_TMR9_IRQnHandler, 9); +_TIM_IRQ_HANDLER(TMR1_BRK_TMR9_IRQHandler, 9); #endif //TODO: there may be a bug #if USED_TIMERS & TIM_N(10) -_TIM_IRQ_HANDLER2(TMR1_OVF_TMR10_IRQnHandler, 1,10); +_TIM_IRQ_HANDLER2(TMR1_OVF_TMR10_IRQHandler, 1,10); #endif # if USED_TIMERS & TIM_N(11) -_TIM_IRQ_HANDLER(TMR1_TRG_HALL_TMR11_IRQnHandler, 11); +_TIM_IRQ_HANDLER(TMR1_TRG_HALL_TMR11_IRQHandler, 11); # endif #if USED_TIMERS & TIM_N(12) -_TIM_IRQ_HANDLER(TMR8_BRK_TMR12_IRQnHandler, 12); +_TIM_IRQ_HANDLER(TMR8_BRK_TMR12_IRQHandler, 12); #endif #if USED_TIMERS & TIM_N(13) -_TIM_IRQ_HANDLER(TMR8_OVF_TMR13_IRQnHandler, 13); +_TIM_IRQ_HANDLER(TMR8_OVF_TMR13_IRQHandler, 13); #endif #if USED_TIMERS & TIM_N(14) -_TIM_IRQ_HANDLER(TMR8_TRG_HALL_TMR14_IRQnHandler, 14); +_TIM_IRQ_HANDLER(TMR8_TRG_HALL_TMR14_IRQHandler, 14); #endif #if USED_TIMERS & TIM_N(20) -_TIM_IRQ_HANDLER(TMR20_CH_IRQnHandler, 20); +_TIM_IRQ_HANDLER(TMR20_CH_IRQHandler, 20); #endif void timerInit(void) From d8bdb23e9cebad3b9c949b57a9c1fae3fd0f6101 Mon Sep 17 00:00:00 2001 From: Jay Blackman Date: Fri, 17 Jan 2025 20:55:04 +1100 Subject: [PATCH 054/244] Fix license header for files in AT and APM directories (#14162) --- src/platform/APM32/adc_apm32f4xx.c | 23 ++++++++++--------- src/platform/APM32/apm32f4xx_ddl_ex.h | 23 ++++++++++--------- src/platform/APM32/bus_i2c_apm32.c | 23 ++++++++++--------- src/platform/APM32/bus_i2c_apm32_init.c | 23 ++++++++++--------- src/platform/APM32/bus_spi_apm32.c | 23 ++++++++++--------- src/platform/APM32/dma_apm32.h | 23 ++++++++++--------- src/platform/APM32/dma_apm32f4xx.c | 23 ++++++++++--------- src/platform/APM32/dma_reqmap_mcu.c | 23 ++++++++++--------- src/platform/APM32/dshot_bitbang.c | 23 ++++++++++--------- src/platform/APM32/dshot_bitbang_ddl.c | 23 ++++++++++--------- src/platform/APM32/eint_apm32.c | 23 ++++++++++--------- src/platform/APM32/io_apm32.c | 23 ++++++++++--------- src/platform/APM32/light_ws2811strip_apm32.c | 23 ++++++++++--------- src/platform/APM32/persistent_apm32.c | 23 ++++++++++--------- src/platform/APM32/pwm_output_apm32.c | 23 ++++++++++--------- src/platform/APM32/pwm_output_dshot_apm32.c | 23 ++++++++++--------- src/platform/APM32/rcm_apm32.c | 23 ++++++++++--------- src/platform/APM32/serial_uart_apm32.c | 23 ++++++++++--------- src/platform/APM32/serial_uart_apm32f4xx.c | 23 ++++++++++--------- src/platform/APM32/system_apm32f4xx.c | 23 ++++++++++--------- src/platform/APM32/target/APM32F405/target.h | 23 ++++++++++--------- src/platform/APM32/target/APM32F407/target.h | 23 ++++++++++--------- src/platform/APM32/timer_apm32.c | 23 ++++++++++--------- src/platform/APM32/timer_apm32f4xx.c | 23 ++++++++++--------- src/platform/APM32/timer_def.h | 23 ++++++++++--------- src/platform/APM32/transponder_ir_io_apm32.c | 23 ++++++++++--------- .../APM32/usb/msc/usb_msc_apm32f4xx.c | 23 ++++++++++--------- src/platform/APM32/usb/vcp/serial_usb_vcp.c | 23 ++++++++++--------- src/platform/AT32/adc_at32f43x.c | 23 ++++++++++--------- src/platform/AT32/bus_i2c_atbsp.c | 23 ++++++++++--------- src/platform/AT32/bus_i2c_atbsp_init.c | 23 ++++++++++--------- src/platform/AT32/bus_spi_at32bsp.c | 23 ++++++++++--------- src/platform/AT32/dma_at32f43x.c | 23 ++++++++++--------- src/platform/AT32/dma_atbsp.h | 23 ++++++++++--------- src/platform/AT32/dshot_bitbang.c | 23 ++++++++++--------- src/platform/AT32/exti_at32.c | 23 ++++++++++--------- src/platform/AT32/io_at32.c | 23 ++++++++++--------- .../AT32/light_ws2811strip_at32f43x.c | 23 ++++++++++--------- src/platform/AT32/persistent_at32bsp.c | 23 ++++++++++--------- src/platform/AT32/pwm_output_at32bsp.c | 23 ++++++++++--------- src/platform/AT32/pwm_output_dshot.c | 23 ++++++++++--------- src/platform/AT32/serial_uart_at32bsp.c | 23 ++++++++++--------- src/platform/AT32/serial_usb_vcp_at32f4.c | 23 ++++++++++--------- src/platform/AT32/system_at32f43x.c | 23 ++++++++++--------- src/platform/AT32/target/AT32F435G/target.h | 23 ++++++++++--------- src/platform/AT32/target/AT32F435M/target.h | 23 ++++++++++--------- src/platform/AT32/timer_at32bsp.c | 23 ++++++++++--------- src/platform/AT32/timer_at32f43x.c | 23 ++++++++++--------- src/platform/AT32/usb_msc_at32f43x.c | 23 ++++++++++--------- 49 files changed, 588 insertions(+), 539 deletions(-) diff --git a/src/platform/APM32/adc_apm32f4xx.c b/src/platform/APM32/adc_apm32f4xx.c index b9407e836b..3359b90678 100644 --- a/src/platform/APM32/adc_apm32f4xx.c +++ b/src/platform/APM32/adc_apm32f4xx.c @@ -1,19 +1,20 @@ /* - * This file is part of Cleanflight and Betaflight. + * This file is part of Betaflight. * - * Cleanflight and Betaflight are free software. You can redistribute - * this software and/or modify this software under the terms of the - * GNU General Public License as published by the Free Software - * Foundation, either version 3 of the License, or (at your option) - * any later version. + * Betaflight is free software. You can redistribute this software + * and/or modify this software under the terms of the GNU General + * Public License as published by the Free Software Foundation, + * either version 3 of the License, or (at your option) any later + * version. + * + * Betaflight is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. * - * Cleanflight and Betaflight are distributed in the hope that they - * will be useful, but WITHOUT ANY WARRANTY; without even the implied - * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. * See the GNU General Public License for more details. * - * You should have received a copy of the GNU General Public License - * along with this software. + * You should have received a copy of the GNU General Public + * License along with this software. * * If not, see . */ diff --git a/src/platform/APM32/apm32f4xx_ddl_ex.h b/src/platform/APM32/apm32f4xx_ddl_ex.h index da6f28a284..187448df8d 100644 --- a/src/platform/APM32/apm32f4xx_ddl_ex.h +++ b/src/platform/APM32/apm32f4xx_ddl_ex.h @@ -1,19 +1,20 @@ /* - * This file is part of Cleanflight and Betaflight. + * This file is part of Betaflight. * - * Cleanflight and Betaflight are free software. You can redistribute - * this software and/or modify this software under the terms of the - * GNU General Public License as published by the Free Software - * Foundation, either version 3 of the License, or (at your option) - * any later version. + * Betaflight is free software. You can redistribute this software + * and/or modify this software under the terms of the GNU General + * Public License as published by the Free Software Foundation, + * either version 3 of the License, or (at your option) any later + * version. + * + * Betaflight is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. * - * Cleanflight and Betaflight are distributed in the hope that they - * will be useful, but WITHOUT ANY WARRANTY; without even the implied - * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. * See the GNU General Public License for more details. * - * You should have received a copy of the GNU General Public License - * along with this software. + * You should have received a copy of the GNU General Public + * License along with this software. * * If not, see . */ diff --git a/src/platform/APM32/bus_i2c_apm32.c b/src/platform/APM32/bus_i2c_apm32.c index 338ded478d..12eb1d803a 100644 --- a/src/platform/APM32/bus_i2c_apm32.c +++ b/src/platform/APM32/bus_i2c_apm32.c @@ -1,19 +1,20 @@ /* - * This file is part of Cleanflight and Betaflight. + * This file is part of Betaflight. * - * Cleanflight and Betaflight are free software. You can redistribute - * this software and/or modify this software under the terms of the - * GNU General Public License as published by the Free Software - * Foundation, either version 3 of the License, or (at your option) - * any later version. + * Betaflight is free software. You can redistribute this software + * and/or modify this software under the terms of the GNU General + * Public License as published by the Free Software Foundation, + * either version 3 of the License, or (at your option) any later + * version. + * + * Betaflight is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. * - * Cleanflight and Betaflight are distributed in the hope that they - * will be useful, but WITHOUT ANY WARRANTY; without even the implied - * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. * See the GNU General Public License for more details. * - * You should have received a copy of the GNU General Public License - * along with this software. + * You should have received a copy of the GNU General Public + * License along with this software. * * If not, see . */ diff --git a/src/platform/APM32/bus_i2c_apm32_init.c b/src/platform/APM32/bus_i2c_apm32_init.c index 9db60f71ab..12dd1227d8 100644 --- a/src/platform/APM32/bus_i2c_apm32_init.c +++ b/src/platform/APM32/bus_i2c_apm32_init.c @@ -1,19 +1,20 @@ /* - * This file is part of Cleanflight and Betaflight. + * This file is part of Betaflight. * - * Cleanflight and Betaflight are free software. You can redistribute - * this software and/or modify this software under the terms of the - * GNU General Public License as published by the Free Software - * Foundation, either version 3 of the License, or (at your option) - * any later version. + * Betaflight is free software. You can redistribute this software + * and/or modify this software under the terms of the GNU General + * Public License as published by the Free Software Foundation, + * either version 3 of the License, or (at your option) any later + * version. + * + * Betaflight is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. * - * Cleanflight and Betaflight are distributed in the hope that they - * will be useful, but WITHOUT ANY WARRANTY; without even the implied - * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. * See the GNU General Public License for more details. * - * You should have received a copy of the GNU General Public License - * along with this software. + * You should have received a copy of the GNU General Public + * License along with this software. * * If not, see . */ diff --git a/src/platform/APM32/bus_spi_apm32.c b/src/platform/APM32/bus_spi_apm32.c index 8f09a3489a..43e215851f 100644 --- a/src/platform/APM32/bus_spi_apm32.c +++ b/src/platform/APM32/bus_spi_apm32.c @@ -1,19 +1,20 @@ /* - * This file is part of Cleanflight and Betaflight. + * This file is part of Betaflight. * - * Cleanflight and Betaflight are free software. You can redistribute - * this software and/or modify this software under the terms of the - * GNU General Public License as published by the Free Software - * Foundation, either version 3 of the License, or (at your option) - * any later version. + * Betaflight is free software. You can redistribute this software + * and/or modify this software under the terms of the GNU General + * Public License as published by the Free Software Foundation, + * either version 3 of the License, or (at your option) any later + * version. + * + * Betaflight is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. * - * Cleanflight and Betaflight are distributed in the hope that they - * will be useful, but WITHOUT ANY WARRANTY; without even the implied - * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. * See the GNU General Public License for more details. * - * You should have received a copy of the GNU General Public License - * along with this software. + * You should have received a copy of the GNU General Public + * License along with this software. * * If not, see . */ diff --git a/src/platform/APM32/dma_apm32.h b/src/platform/APM32/dma_apm32.h index accfb132f3..a719782180 100644 --- a/src/platform/APM32/dma_apm32.h +++ b/src/platform/APM32/dma_apm32.h @@ -1,19 +1,20 @@ /* - * This file is part of Cleanflight and Betaflight. + * This file is part of Betaflight. * - * Cleanflight and Betaflight are free software. You can redistribute - * this software and/or modify this software under the terms of the - * GNU General Public License as published by the Free Software - * Foundation, either version 3 of the License, or (at your option) - * any later version. + * Betaflight is free software. You can redistribute this software + * and/or modify this software under the terms of the GNU General + * Public License as published by the Free Software Foundation, + * either version 3 of the License, or (at your option) any later + * version. + * + * Betaflight is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. * - * Cleanflight and Betaflight are distributed in the hope that they - * will be useful, but WITHOUT ANY WARRANTY; without even the implied - * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. * See the GNU General Public License for more details. * - * You should have received a copy of the GNU General Public License - * along with this software. + * You should have received a copy of the GNU General Public + * License along with this software. * * If not, see . */ diff --git a/src/platform/APM32/dma_apm32f4xx.c b/src/platform/APM32/dma_apm32f4xx.c index 723838c06b..3c571a75e5 100644 --- a/src/platform/APM32/dma_apm32f4xx.c +++ b/src/platform/APM32/dma_apm32f4xx.c @@ -1,19 +1,20 @@ /* - * This file is part of Cleanflight and Betaflight. + * This file is part of Betaflight. * - * Cleanflight and Betaflight are free software. You can redistribute - * this software and/or modify this software under the terms of the - * GNU General Public License as published by the Free Software - * Foundation, either version 3 of the License, or (at your option) - * any later version. + * Betaflight is free software. You can redistribute this software + * and/or modify this software under the terms of the GNU General + * Public License as published by the Free Software Foundation, + * either version 3 of the License, or (at your option) any later + * version. + * + * Betaflight is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. * - * Cleanflight and Betaflight are distributed in the hope that they - * will be useful, but WITHOUT ANY WARRANTY; without even the implied - * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. * See the GNU General Public License for more details. * - * You should have received a copy of the GNU General Public License - * along with this software. + * You should have received a copy of the GNU General Public + * License along with this software. * * If not, see . */ diff --git a/src/platform/APM32/dma_reqmap_mcu.c b/src/platform/APM32/dma_reqmap_mcu.c index 892341af71..2d36c8e795 100644 --- a/src/platform/APM32/dma_reqmap_mcu.c +++ b/src/platform/APM32/dma_reqmap_mcu.c @@ -1,19 +1,20 @@ /* - * This file is part of Cleanflight and Betaflight. + * This file is part of Betaflight. * - * Cleanflight and Betaflight are free software. You can redistribute - * this software and/or modify this software under the terms of the - * GNU General Public License as published by the Free Software - * Foundation, either version 3 of the License, or (at your option) - * any later version. + * Betaflight is free software. You can redistribute this software + * and/or modify this software under the terms of the GNU General + * Public License as published by the Free Software Foundation, + * either version 3 of the License, or (at your option) any later + * version. + * + * Betaflight is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. * - * Cleanflight and Betaflight are distributed in the hope that they - * will be useful, but WITHOUT ANY WARRANTY; without even the implied - * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. * See the GNU General Public License for more details. * - * You should have received a copy of the GNU General Public License - * along with this software. + * You should have received a copy of the GNU General Public + * License along with this software. * * If not, see . */ diff --git a/src/platform/APM32/dshot_bitbang.c b/src/platform/APM32/dshot_bitbang.c index d128aec8f2..92de301f43 100644 --- a/src/platform/APM32/dshot_bitbang.c +++ b/src/platform/APM32/dshot_bitbang.c @@ -1,19 +1,20 @@ /* - * This file is part of Cleanflight and Betaflight. + * This file is part of Betaflight. * - * Cleanflight and Betaflight are free software. You can redistribute - * this software and/or modify this software under the terms of the - * GNU General Public License as published by the Free Software - * Foundation, either version 3 of the License, or (at your option) - * any later version. + * Betaflight is free software. You can redistribute this software + * and/or modify this software under the terms of the GNU General + * Public License as published by the Free Software Foundation, + * either version 3 of the License, or (at your option) any later + * version. + * + * Betaflight is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. * - * Cleanflight and Betaflight are distributed in the hope that they - * will be useful, but WITHOUT ANY WARRANTY; without even the implied - * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. * See the GNU General Public License for more details. * - * You should have received a copy of the GNU General Public License - * along with this software. + * You should have received a copy of the GNU General Public + * License along with this software. * * If not, see . */ diff --git a/src/platform/APM32/dshot_bitbang_ddl.c b/src/platform/APM32/dshot_bitbang_ddl.c index f26a21966f..c03e02ff9b 100644 --- a/src/platform/APM32/dshot_bitbang_ddl.c +++ b/src/platform/APM32/dshot_bitbang_ddl.c @@ -1,19 +1,20 @@ /* - * This file is part of Cleanflight and Betaflight. + * This file is part of Betaflight. * - * Cleanflight and Betaflight are free software. You can redistribute - * this software and/or modify this software under the terms of the - * GNU General Public License as published by the Free Software - * Foundation, either version 3 of the License, or (at your option) - * any later version. + * Betaflight is free software. You can redistribute this software + * and/or modify this software under the terms of the GNU General + * Public License as published by the Free Software Foundation, + * either version 3 of the License, or (at your option) any later + * version. + * + * Betaflight is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. * - * Cleanflight and Betaflight are distributed in the hope that they - * will be useful, but WITHOUT ANY WARRANTY; without even the implied - * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. * See the GNU General Public License for more details. * - * You should have received a copy of the GNU General Public License - * along with this software. + * You should have received a copy of the GNU General Public + * License along with this software. * * If not, see . */ diff --git a/src/platform/APM32/eint_apm32.c b/src/platform/APM32/eint_apm32.c index c3e0d8bf9a..fd39b93094 100644 --- a/src/platform/APM32/eint_apm32.c +++ b/src/platform/APM32/eint_apm32.c @@ -1,19 +1,20 @@ /* - * This file is part of Cleanflight and Betaflight. + * This file is part of Betaflight. * - * Cleanflight and Betaflight are free software. You can redistribute - * this software and/or modify this software under the terms of the - * GNU General Public License as published by the Free Software - * Foundation, either version 3 of the License, or (at your option) - * any later version. + * Betaflight is free software. You can redistribute this software + * and/or modify this software under the terms of the GNU General + * Public License as published by the Free Software Foundation, + * either version 3 of the License, or (at your option) any later + * version. + * + * Betaflight is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. * - * Cleanflight and Betaflight are distributed in the hope that they - * will be useful, but WITHOUT ANY WARRANTY; without even the implied - * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. * See the GNU General Public License for more details. * - * You should have received a copy of the GNU General Public License - * along with this software. + * You should have received a copy of the GNU General Public + * License along with this software. * * If not, see . */ diff --git a/src/platform/APM32/io_apm32.c b/src/platform/APM32/io_apm32.c index 1bfdefc8a7..d744117646 100644 --- a/src/platform/APM32/io_apm32.c +++ b/src/platform/APM32/io_apm32.c @@ -1,19 +1,20 @@ /* - * This file is part of Cleanflight and Betaflight. + * This file is part of Betaflight. * - * Cleanflight and Betaflight are free software. You can redistribute - * this software and/or modify this software under the terms of the - * GNU General Public License as published by the Free Software - * Foundation, either version 3 of the License, or (at your option) - * any later version. + * Betaflight is free software. You can redistribute this software + * and/or modify this software under the terms of the GNU General + * Public License as published by the Free Software Foundation, + * either version 3 of the License, or (at your option) any later + * version. + * + * Betaflight is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. * - * Cleanflight and Betaflight are distributed in the hope that they - * will be useful, but WITHOUT ANY WARRANTY; without even the implied - * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. * See the GNU General Public License for more details. * - * You should have received a copy of the GNU General Public License - * along with this software. + * You should have received a copy of the GNU General Public + * License along with this software. * * If not, see . */ diff --git a/src/platform/APM32/light_ws2811strip_apm32.c b/src/platform/APM32/light_ws2811strip_apm32.c index a96d3a9bc4..676f719470 100644 --- a/src/platform/APM32/light_ws2811strip_apm32.c +++ b/src/platform/APM32/light_ws2811strip_apm32.c @@ -1,19 +1,20 @@ /* - * This file is part of Cleanflight and Betaflight. + * This file is part of Betaflight. * - * Cleanflight and Betaflight are free software. You can redistribute - * this software and/or modify this software under the terms of the - * GNU General Public License as published by the Free Software - * Foundation, either version 3 of the License, or (at your option) - * any later version. + * Betaflight is free software. You can redistribute this software + * and/or modify this software under the terms of the GNU General + * Public License as published by the Free Software Foundation, + * either version 3 of the License, or (at your option) any later + * version. + * + * Betaflight is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. * - * Cleanflight and Betaflight are distributed in the hope that they - * will be useful, but WITHOUT ANY WARRANTY; without even the implied - * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. * See the GNU General Public License for more details. * - * You should have received a copy of the GNU General Public License - * along with this software. + * You should have received a copy of the GNU General Public + * License along with this software. * * If not, see . */ diff --git a/src/platform/APM32/persistent_apm32.c b/src/platform/APM32/persistent_apm32.c index 4d5caeecbd..20a367ad6f 100644 --- a/src/platform/APM32/persistent_apm32.c +++ b/src/platform/APM32/persistent_apm32.c @@ -1,19 +1,20 @@ /* - * This file is part of Cleanflight and Betaflight. + * This file is part of Betaflight. * - * Cleanflight and Betaflight are free software. You can redistribute - * this software and/or modify this software under the terms of the - * GNU General Public License as published by the Free Software - * Foundation, either version 3 of the License, or (at your option) - * any later version. + * Betaflight is free software. You can redistribute this software + * and/or modify this software under the terms of the GNU General + * Public License as published by the Free Software Foundation, + * either version 3 of the License, or (at your option) any later + * version. + * + * Betaflight is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. * - * Cleanflight and Betaflight are distributed in the hope that they - * will be useful, but WITHOUT ANY WARRANTY; without even the implied - * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. * See the GNU General Public License for more details. * - * You should have received a copy of the GNU General Public License - * along with this software. + * You should have received a copy of the GNU General Public + * License along with this software. * * If not, see . */ diff --git a/src/platform/APM32/pwm_output_apm32.c b/src/platform/APM32/pwm_output_apm32.c index c0f40dd948..a2d3254fe7 100644 --- a/src/platform/APM32/pwm_output_apm32.c +++ b/src/platform/APM32/pwm_output_apm32.c @@ -1,19 +1,20 @@ /* - * This file is part of Cleanflight and Betaflight. + * This file is part of Betaflight. * - * Cleanflight and Betaflight are free software. You can redistribute - * this software and/or modify this software under the terms of the - * GNU General Public License as published by the Free Software - * Foundation, either version 3 of the License, or (at your option) - * any later version. + * Betaflight is free software. You can redistribute this software + * and/or modify this software under the terms of the GNU General + * Public License as published by the Free Software Foundation, + * either version 3 of the License, or (at your option) any later + * version. + * + * Betaflight is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. * - * Cleanflight and Betaflight are distributed in the hope that they - * will be useful, but WITHOUT ANY WARRANTY; without even the implied - * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. * See the GNU General Public License for more details. * - * You should have received a copy of the GNU General Public License - * along with this software. + * You should have received a copy of the GNU General Public + * License along with this software. * * If not, see . */ diff --git a/src/platform/APM32/pwm_output_dshot_apm32.c b/src/platform/APM32/pwm_output_dshot_apm32.c index 02189569f8..4025aa531c 100644 --- a/src/platform/APM32/pwm_output_dshot_apm32.c +++ b/src/platform/APM32/pwm_output_dshot_apm32.c @@ -1,19 +1,20 @@ /* - * This file is part of Cleanflight and Betaflight. + * This file is part of Betaflight. * - * Cleanflight and Betaflight are free software. You can redistribute - * this software and/or modify this software under the terms of the - * GNU General Public License as published by the Free Software - * Foundation, either version 3 of the License, or (at your option) - * any later version. + * Betaflight is free software. You can redistribute this software + * and/or modify this software under the terms of the GNU General + * Public License as published by the Free Software Foundation, + * either version 3 of the License, or (at your option) any later + * version. + * + * Betaflight is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. * - * Cleanflight and Betaflight are distributed in the hope that they - * will be useful, but WITHOUT ANY WARRANTY; without even the implied - * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. * See the GNU General Public License for more details. * - * You should have received a copy of the GNU General Public License - * along with this software. + * You should have received a copy of the GNU General Public + * License along with this software. * * If not, see . */ diff --git a/src/platform/APM32/rcm_apm32.c b/src/platform/APM32/rcm_apm32.c index 9f86cf594c..96ecd59ac5 100644 --- a/src/platform/APM32/rcm_apm32.c +++ b/src/platform/APM32/rcm_apm32.c @@ -1,19 +1,20 @@ /* - * This file is part of Cleanflight and Betaflight. + * This file is part of Betaflight. * - * Cleanflight and Betaflight are free software. You can redistribute - * this software and/or modify this software under the terms of the - * GNU General Public License as published by the Free Software - * Foundation, either version 3 of the License, or (at your option) - * any later version. + * Betaflight is free software. You can redistribute this software + * and/or modify this software under the terms of the GNU General + * Public License as published by the Free Software Foundation, + * either version 3 of the License, or (at your option) any later + * version. + * + * Betaflight is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. * - * Cleanflight and Betaflight are distributed in the hope that they - * will be useful, but WITHOUT ANY WARRANTY; without even the implied - * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. * See the GNU General Public License for more details. * - * You should have received a copy of the GNU General Public License - * along with this software. + * You should have received a copy of the GNU General Public + * License along with this software. * * If not, see . */ diff --git a/src/platform/APM32/serial_uart_apm32.c b/src/platform/APM32/serial_uart_apm32.c index 43344e2317..e676ca2f93 100644 --- a/src/platform/APM32/serial_uart_apm32.c +++ b/src/platform/APM32/serial_uart_apm32.c @@ -1,19 +1,20 @@ /* - * This file is part of Cleanflight and Betaflight. + * This file is part of Betaflight. * - * Cleanflight and Betaflight are free software. You can redistribute - * this software and/or modify this software under the terms of the - * GNU General Public License as published by the Free Software - * Foundation, either version 3 of the License, or (at your option) - * any later version. + * Betaflight is free software. You can redistribute this software + * and/or modify this software under the terms of the GNU General + * Public License as published by the Free Software Foundation, + * either version 3 of the License, or (at your option) any later + * version. + * + * Betaflight is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. * - * Cleanflight and Betaflight are distributed in the hope that they - * will be useful, but WITHOUT ANY WARRANTY; without even the implied - * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. * See the GNU General Public License for more details. * - * You should have received a copy of the GNU General Public License - * along with this software. + * You should have received a copy of the GNU General Public + * License along with this software. * * If not, see . */ diff --git a/src/platform/APM32/serial_uart_apm32f4xx.c b/src/platform/APM32/serial_uart_apm32f4xx.c index 1dde4d9682..2c5151b62f 100644 --- a/src/platform/APM32/serial_uart_apm32f4xx.c +++ b/src/platform/APM32/serial_uart_apm32f4xx.c @@ -1,19 +1,20 @@ /* - * This file is part of Cleanflight and Betaflight. + * This file is part of Betaflight. * - * Cleanflight and Betaflight are free software. You can redistribute - * this software and/or modify this software under the terms of the - * GNU General Public License as published by the Free Software - * Foundation, either version 3 of the License, or (at your option) - * any later version. + * Betaflight is free software. You can redistribute this software + * and/or modify this software under the terms of the GNU General + * Public License as published by the Free Software Foundation, + * either version 3 of the License, or (at your option) any later + * version. + * + * Betaflight is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. * - * Cleanflight and Betaflight are distributed in the hope that they - * will be useful, but WITHOUT ANY WARRANTY; without even the implied - * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. * See the GNU General Public License for more details. * - * You should have received a copy of the GNU General Public License - * along with this software. + * You should have received a copy of the GNU General Public + * License along with this software. * * If not, see . */ diff --git a/src/platform/APM32/system_apm32f4xx.c b/src/platform/APM32/system_apm32f4xx.c index 25bdeff99b..0bf5b42231 100644 --- a/src/platform/APM32/system_apm32f4xx.c +++ b/src/platform/APM32/system_apm32f4xx.c @@ -1,19 +1,20 @@ /* - * This file is part of Cleanflight and Betaflight. + * This file is part of Betaflight. * - * Cleanflight and Betaflight are free software. You can redistribute - * this software and/or modify this software under the terms of the - * GNU General Public License as published by the Free Software - * Foundation, either version 3 of the License, or (at your option) - * any later version. + * Betaflight is free software. You can redistribute this software + * and/or modify this software under the terms of the GNU General + * Public License as published by the Free Software Foundation, + * either version 3 of the License, or (at your option) any later + * version. + * + * Betaflight is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. * - * Cleanflight and Betaflight are distributed in the hope that they - * will be useful, but WITHOUT ANY WARRANTY; without even the implied - * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. * See the GNU General Public License for more details. * - * You should have received a copy of the GNU General Public License - * along with this software. + * You should have received a copy of the GNU General Public + * License along with this software. * * If not, see . */ diff --git a/src/platform/APM32/target/APM32F405/target.h b/src/platform/APM32/target/APM32F405/target.h index 367ab649ad..b23694d80e 100644 --- a/src/platform/APM32/target/APM32F405/target.h +++ b/src/platform/APM32/target/APM32F405/target.h @@ -1,19 +1,20 @@ /* - * This file is part of Cleanflight and Betaflight. + * This file is part of Betaflight. * - * Cleanflight and Betaflight are free software. You can redistribute - * this software and/or modify this software under the terms of the - * GNU General Public License as published by the Free Software - * Foundation, either version 3 of the License, or (at your option) - * any later version. + * Betaflight is free software. You can redistribute this software + * and/or modify this software under the terms of the GNU General + * Public License as published by the Free Software Foundation, + * either version 3 of the License, or (at your option) any later + * version. + * + * Betaflight is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. * - * Cleanflight and Betaflight are distributed in the hope that they - * will be useful, but WITHOUT ANY WARRANTY; without even the implied - * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. * See the GNU General Public License for more details. * - * You should have received a copy of the GNU General Public License - * along with this software. + * You should have received a copy of the GNU General Public + * License along with this software. * * If not, see . */ diff --git a/src/platform/APM32/target/APM32F407/target.h b/src/platform/APM32/target/APM32F407/target.h index a88cea7e6e..c529d6d366 100644 --- a/src/platform/APM32/target/APM32F407/target.h +++ b/src/platform/APM32/target/APM32F407/target.h @@ -1,19 +1,20 @@ /* - * This file is part of Cleanflight and Betaflight. + * This file is part of Betaflight. * - * Cleanflight and Betaflight are free software. You can redistribute - * this software and/or modify this software under the terms of the - * GNU General Public License as published by the Free Software - * Foundation, either version 3 of the License, or (at your option) - * any later version. + * Betaflight is free software. You can redistribute this software + * and/or modify this software under the terms of the GNU General + * Public License as published by the Free Software Foundation, + * either version 3 of the License, or (at your option) any later + * version. + * + * Betaflight is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. * - * Cleanflight and Betaflight are distributed in the hope that they - * will be useful, but WITHOUT ANY WARRANTY; without even the implied - * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. * See the GNU General Public License for more details. * - * You should have received a copy of the GNU General Public License - * along with this software. + * You should have received a copy of the GNU General Public + * License along with this software. * * If not, see . */ diff --git a/src/platform/APM32/timer_apm32.c b/src/platform/APM32/timer_apm32.c index 58cb219166..df3aff9adb 100644 --- a/src/platform/APM32/timer_apm32.c +++ b/src/platform/APM32/timer_apm32.c @@ -1,19 +1,20 @@ /* - * This file is part of Cleanflight and Betaflight. + * This file is part of Betaflight. * - * Cleanflight and Betaflight are free software. You can redistribute - * this software and/or modify this software under the terms of the - * GNU General Public License as published by the Free Software - * Foundation, either version 3 of the License, or (at your option) - * any later version. + * Betaflight is free software. You can redistribute this software + * and/or modify this software under the terms of the GNU General + * Public License as published by the Free Software Foundation, + * either version 3 of the License, or (at your option) any later + * version. + * + * Betaflight is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. * - * Cleanflight and Betaflight are distributed in the hope that they - * will be useful, but WITHOUT ANY WARRANTY; without even the implied - * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. * See the GNU General Public License for more details. * - * You should have received a copy of the GNU General Public License - * along with this software. + * You should have received a copy of the GNU General Public + * License along with this software. * * If not, see . */ diff --git a/src/platform/APM32/timer_apm32f4xx.c b/src/platform/APM32/timer_apm32f4xx.c index df020c0afd..708e6f3e29 100644 --- a/src/platform/APM32/timer_apm32f4xx.c +++ b/src/platform/APM32/timer_apm32f4xx.c @@ -1,19 +1,20 @@ /* - * This file is part of Cleanflight and Betaflight. + * This file is part of Betaflight. * - * Cleanflight and Betaflight are free software. You can redistribute - * this software and/or modify this software under the terms of the - * GNU General Public License as published by the Free Software - * Foundation, either version 3 of the License, or (at your option) - * any later version. + * Betaflight is free software. You can redistribute this software + * and/or modify this software under the terms of the GNU General + * Public License as published by the Free Software Foundation, + * either version 3 of the License, or (at your option) any later + * version. + * + * Betaflight is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. * - * Cleanflight and Betaflight are distributed in the hope that they - * will be useful, but WITHOUT ANY WARRANTY; without even the implied - * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. * See the GNU General Public License for more details. * - * You should have received a copy of the GNU General Public License - * along with this software. + * You should have received a copy of the GNU General Public + * License along with this software. * * If not, see . */ diff --git a/src/platform/APM32/timer_def.h b/src/platform/APM32/timer_def.h index 54949a4de8..157fe314f6 100644 --- a/src/platform/APM32/timer_def.h +++ b/src/platform/APM32/timer_def.h @@ -1,19 +1,20 @@ /* - * This file is part of Cleanflight and Betaflight. + * This file is part of Betaflight. * - * Cleanflight and Betaflight are free software. You can redistribute - * this software and/or modify this software under the terms of the - * GNU General Public License as published by the Free Software - * Foundation, either version 3 of the License, or (at your option) - * any later version. + * Betaflight is free software. You can redistribute this software + * and/or modify this software under the terms of the GNU General + * Public License as published by the Free Software Foundation, + * either version 3 of the License, or (at your option) any later + * version. + * + * Betaflight is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. * - * Cleanflight and Betaflight are distributed in the hope that they - * will be useful, but WITHOUT ANY WARRANTY; without even the implied - * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. * See the GNU General Public License for more details. * - * You should have received a copy of the GNU General Public License - * along with this software. + * You should have received a copy of the GNU General Public + * License along with this software. * * If not, see . */ diff --git a/src/platform/APM32/transponder_ir_io_apm32.c b/src/platform/APM32/transponder_ir_io_apm32.c index 738f88f333..799ccb8494 100644 --- a/src/platform/APM32/transponder_ir_io_apm32.c +++ b/src/platform/APM32/transponder_ir_io_apm32.c @@ -1,19 +1,20 @@ /* - * This file is part of Cleanflight and Betaflight. + * This file is part of Betaflight. * - * Cleanflight and Betaflight are free software. You can redistribute - * this software and/or modify this software under the terms of the - * GNU General Public License as published by the Free Software - * Foundation, either version 3 of the License, or (at your option) - * any later version. + * Betaflight is free software. You can redistribute this software + * and/or modify this software under the terms of the GNU General + * Public License as published by the Free Software Foundation, + * either version 3 of the License, or (at your option) any later + * version. + * + * Betaflight is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. * - * Cleanflight and Betaflight are distributed in the hope that they - * will be useful, but WITHOUT ANY WARRANTY; without even the implied - * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. * See the GNU General Public License for more details. * - * You should have received a copy of the GNU General Public License - * along with this software. + * You should have received a copy of the GNU General Public + * License along with this software. * * If not, see . */ diff --git a/src/platform/APM32/usb/msc/usb_msc_apm32f4xx.c b/src/platform/APM32/usb/msc/usb_msc_apm32f4xx.c index 8d0227572b..a7a0155dd2 100644 --- a/src/platform/APM32/usb/msc/usb_msc_apm32f4xx.c +++ b/src/platform/APM32/usb/msc/usb_msc_apm32f4xx.c @@ -1,19 +1,20 @@ /* - * This file is part of Cleanflight and Betaflight. + * This file is part of Betaflight. * - * Cleanflight and Betaflight are free software. You can redistribute - * this software and/or modify this software under the terms of the - * GNU General Public License as published by the Free Software - * Foundation, either version 3 of the License, or (at your option) - * any later version. + * Betaflight is free software. You can redistribute this software + * and/or modify this software under the terms of the GNU General + * Public License as published by the Free Software Foundation, + * either version 3 of the License, or (at your option) any later + * version. + * + * Betaflight is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. * - * Cleanflight and Betaflight are distributed in the hope that they - * will be useful, but WITHOUT ANY WARRANTY; without even the implied - * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. * See the GNU General Public License for more details. * - * You should have received a copy of the GNU General Public License - * along with this software. + * You should have received a copy of the GNU General Public + * License along with this software. * * If not, see . */ diff --git a/src/platform/APM32/usb/vcp/serial_usb_vcp.c b/src/platform/APM32/usb/vcp/serial_usb_vcp.c index 26b44d12f3..ff7e77c1a5 100644 --- a/src/platform/APM32/usb/vcp/serial_usb_vcp.c +++ b/src/platform/APM32/usb/vcp/serial_usb_vcp.c @@ -1,19 +1,20 @@ /* - * This file is part of Cleanflight and Betaflight. + * This file is part of Betaflight. * - * Cleanflight and Betaflight are free software. You can redistribute - * this software and/or modify this software under the terms of the - * GNU General Public License as published by the Free Software - * Foundation, either version 3 of the License, or (at your option) - * any later version. + * Betaflight is free software. You can redistribute this software + * and/or modify this software under the terms of the GNU General + * Public License as published by the Free Software Foundation, + * either version 3 of the License, or (at your option) any later + * version. + * + * Betaflight is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. * - * Cleanflight and Betaflight are distributed in the hope that they - * will be useful, but WITHOUT ANY WARRANTY; without even the implied - * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. * See the GNU General Public License for more details. * - * You should have received a copy of the GNU General Public License - * along with this software. + * You should have received a copy of the GNU General Public + * License along with this software. * * If not, see . */ diff --git a/src/platform/AT32/adc_at32f43x.c b/src/platform/AT32/adc_at32f43x.c index 46b3ae714c..9cc7ea6225 100644 --- a/src/platform/AT32/adc_at32f43x.c +++ b/src/platform/AT32/adc_at32f43x.c @@ -1,19 +1,20 @@ /* - * This file is part of Cleanflight and Betaflight. + * This file is part of Betaflight. * - * Cleanflight and Betaflight are free software. You can redistribute - * this software and/or modify this software under the terms of the - * GNU General Public License as published by the Free Software - * Foundation, either version 3 of the License, or (at your option) - * any later version. + * Betaflight is free software. You can redistribute this software + * and/or modify this software under the terms of the GNU General + * Public License as published by the Free Software Foundation, + * either version 3 of the License, or (at your option) any later + * version. + * + * Betaflight is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. * - * Cleanflight and Betaflight are distributed in the hope that they - * will be useful, but WITHOUT ANY WARRANTY; without even the implied - * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. * See the GNU General Public License for more details. * - * You should have received a copy of the GNU General Public License - * along with this software. + * You should have received a copy of the GNU General Public + * License along with this software. * * If not, see . */ diff --git a/src/platform/AT32/bus_i2c_atbsp.c b/src/platform/AT32/bus_i2c_atbsp.c index a8d1bf6470..daa9f4bc9a 100644 --- a/src/platform/AT32/bus_i2c_atbsp.c +++ b/src/platform/AT32/bus_i2c_atbsp.c @@ -1,19 +1,20 @@ /* - * This file is part of Cleanflight and Betaflight. + * This file is part of Betaflight. * - * Cleanflight and Betaflight are free software. You can redistribute - * this software and/or modify this software under the terms of the - * GNU General Public License as published by the Free Software - * Foundation, either version 3 of the License, or (at your option) - * any later version. + * Betaflight is free software. You can redistribute this software + * and/or modify this software under the terms of the GNU General + * Public License as published by the Free Software Foundation, + * either version 3 of the License, or (at your option) any later + * version. + * + * Betaflight is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. * - * Cleanflight and Betaflight are distributed in the hope that they - * will be useful, but WITHOUT ANY WARRANTY; without even the implied - * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. * See the GNU General Public License for more details. * - * You should have received a copy of the GNU General Public License - * along with this software. + * You should have received a copy of the GNU General Public + * License along with this software. * * If not, see . */ diff --git a/src/platform/AT32/bus_i2c_atbsp_init.c b/src/platform/AT32/bus_i2c_atbsp_init.c index 79582e0ada..0d3d4c2542 100644 --- a/src/platform/AT32/bus_i2c_atbsp_init.c +++ b/src/platform/AT32/bus_i2c_atbsp_init.c @@ -1,19 +1,20 @@ /* - * This file is part of Cleanflight and Betaflight. + * This file is part of Betaflight. * - * Cleanflight and Betaflight are free software. You can redistribute - * this software and/or modify this software under the terms of the - * GNU General Public License as published by the Free Software - * Foundation, either version 3 of the License, or (at your option) - * any later version. + * Betaflight is free software. You can redistribute this software + * and/or modify this software under the terms of the GNU General + * Public License as published by the Free Software Foundation, + * either version 3 of the License, or (at your option) any later + * version. + * + * Betaflight is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. * - * Cleanflight and Betaflight are distributed in the hope that they - * will be useful, but WITHOUT ANY WARRANTY; without even the implied - * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. * See the GNU General Public License for more details. * - * You should have received a copy of the GNU General Public License - * along with this software. + * You should have received a copy of the GNU General Public + * License along with this software. * * If not, see . */ diff --git a/src/platform/AT32/bus_spi_at32bsp.c b/src/platform/AT32/bus_spi_at32bsp.c index b76303d5af..5c643198bb 100644 --- a/src/platform/AT32/bus_spi_at32bsp.c +++ b/src/platform/AT32/bus_spi_at32bsp.c @@ -1,19 +1,20 @@ /* - * This file is part of Cleanflight and Betaflight. + * This file is part of Betaflight. * - * Cleanflight and Betaflight are free software. You can redistribute - * this software and/or modify this software under the terms of the - * GNU General Public License as published by the Free Software - * Foundation, either version 3 of the License, or (at your option) - * any later version. + * Betaflight is free software. You can redistribute this software + * and/or modify this software under the terms of the GNU General + * Public License as published by the Free Software Foundation, + * either version 3 of the License, or (at your option) any later + * version. + * + * Betaflight is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. * - * Cleanflight and Betaflight are distributed in the hope that they - * will be useful, but WITHOUT ANY WARRANTY; without even the implied - * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. * See the GNU General Public License for more details. * - * You should have received a copy of the GNU General Public License - * along with this software. + * You should have received a copy of the GNU General Public + * License along with this software. * * If not, see . */ diff --git a/src/platform/AT32/dma_at32f43x.c b/src/platform/AT32/dma_at32f43x.c index e3f3d9863c..e233713a42 100644 --- a/src/platform/AT32/dma_at32f43x.c +++ b/src/platform/AT32/dma_at32f43x.c @@ -1,19 +1,20 @@ /* - * This file is part of Cleanflight and Betaflight. + * This file is part of Betaflight. * - * Cleanflight and Betaflight are free software. You can redistribute - * this software and/or modify this software under the terms of the - * GNU General Public License as published by the Free Software - * Foundation, either version 3 of the License, or (at your option) - * any later version. + * Betaflight is free software. You can redistribute this software + * and/or modify this software under the terms of the GNU General + * Public License as published by the Free Software Foundation, + * either version 3 of the License, or (at your option) any later + * version. + * + * Betaflight is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. * - * Cleanflight and Betaflight are distributed in the hope that they - * will be useful, but WITHOUT ANY WARRANTY; without even the implied - * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. * See the GNU General Public License for more details. * - * You should have received a copy of the GNU General Public License - * along with this software. + * You should have received a copy of the GNU General Public + * License along with this software. * * If not, see . */ diff --git a/src/platform/AT32/dma_atbsp.h b/src/platform/AT32/dma_atbsp.h index 49b452558e..1cf03115c1 100644 --- a/src/platform/AT32/dma_atbsp.h +++ b/src/platform/AT32/dma_atbsp.h @@ -1,19 +1,20 @@ /* - * This file is part of Cleanflight and Betaflight. + * This file is part of Betaflight. * - * Cleanflight and Betaflight are free software. You can redistribute - * this software and/or modify this software under the terms of the - * GNU General Public License as published by the Free Software - * Foundation, either version 3 of the License, or (at your option) - * any later version. + * Betaflight is free software. You can redistribute this software + * and/or modify this software under the terms of the GNU General + * Public License as published by the Free Software Foundation, + * either version 3 of the License, or (at your option) any later + * version. + * + * Betaflight is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. * - * Cleanflight and Betaflight are distributed in the hope that they - * will be useful, but WITHOUT ANY WARRANTY; without even the implied - * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. * See the GNU General Public License for more details. * - * You should have received a copy of the GNU General Public License - * along with this software. + * You should have received a copy of the GNU General Public + * License along with this software. * * If not, see . */ diff --git a/src/platform/AT32/dshot_bitbang.c b/src/platform/AT32/dshot_bitbang.c index 9ea68bba43..ccff17ae91 100644 --- a/src/platform/AT32/dshot_bitbang.c +++ b/src/platform/AT32/dshot_bitbang.c @@ -1,19 +1,20 @@ /* - * This file is part of Cleanflight and Betaflight. + * This file is part of Betaflight. * - * Cleanflight and Betaflight are free software. You can redistribute - * this software and/or modify this software under the terms of the - * GNU General Public License as published by the Free Software - * Foundation, either version 3 of the License, or (at your option) - * any later version. + * Betaflight is free software. You can redistribute this software + * and/or modify this software under the terms of the GNU General + * Public License as published by the Free Software Foundation, + * either version 3 of the License, or (at your option) any later + * version. + * + * Betaflight is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. * - * Cleanflight and Betaflight are distributed in the hope that they - * will be useful, but WITHOUT ANY WARRANTY; without even the implied - * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. * See the GNU General Public License for more details. * - * You should have received a copy of the GNU General Public License - * along with this software. + * You should have received a copy of the GNU General Public + * License along with this software. * * If not, see . */ diff --git a/src/platform/AT32/exti_at32.c b/src/platform/AT32/exti_at32.c index 78f40edea5..5bbe0bde50 100644 --- a/src/platform/AT32/exti_at32.c +++ b/src/platform/AT32/exti_at32.c @@ -1,19 +1,20 @@ /* - * This file is part of Cleanflight and Betaflight. + * This file is part of Betaflight. * - * Cleanflight and Betaflight are free software. You can redistribute - * this software and/or modify this software under the terms of the - * GNU General Public License as published by the Free Software - * Foundation, either version 3 of the License, or (at your option) - * any later version. + * Betaflight is free software. You can redistribute this software + * and/or modify this software under the terms of the GNU General + * Public License as published by the Free Software Foundation, + * either version 3 of the License, or (at your option) any later + * version. + * + * Betaflight is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. * - * Cleanflight and Betaflight are distributed in the hope that they - * will be useful, but WITHOUT ANY WARRANTY; without even the implied - * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. * See the GNU General Public License for more details. * - * You should have received a copy of the GNU General Public License - * along with this software. + * You should have received a copy of the GNU General Public + * License along with this software. * * If not, see . */ diff --git a/src/platform/AT32/io_at32.c b/src/platform/AT32/io_at32.c index 321c32f868..231f9e5e47 100644 --- a/src/platform/AT32/io_at32.c +++ b/src/platform/AT32/io_at32.c @@ -1,19 +1,20 @@ /* - * This file is part of Cleanflight and Betaflight. + * This file is part of Betaflight. * - * Cleanflight and Betaflight are free software. You can redistribute - * this software and/or modify this software under the terms of the - * GNU General Public License as published by the Free Software - * Foundation, either version 3 of the License, or (at your option) - * any later version. + * Betaflight is free software. You can redistribute this software + * and/or modify this software under the terms of the GNU General + * Public License as published by the Free Software Foundation, + * either version 3 of the License, or (at your option) any later + * version. + * + * Betaflight is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. * - * Cleanflight and Betaflight are distributed in the hope that they - * will be useful, but WITHOUT ANY WARRANTY; without even the implied - * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. * See the GNU General Public License for more details. * - * You should have received a copy of the GNU General Public License - * along with this software. + * You should have received a copy of the GNU General Public + * License along with this software. * * If not, see . */ diff --git a/src/platform/AT32/light_ws2811strip_at32f43x.c b/src/platform/AT32/light_ws2811strip_at32f43x.c index 1adfd990d6..1827556d30 100644 --- a/src/platform/AT32/light_ws2811strip_at32f43x.c +++ b/src/platform/AT32/light_ws2811strip_at32f43x.c @@ -1,19 +1,20 @@ /* - * This file is part of Cleanflight and Betaflight. + * This file is part of Betaflight. * - * Cleanflight and Betaflight are free software. You can redistribute - * this software and/or modify this software under the terms of the - * GNU General Public License as published by the Free Software - * Foundation, either version 3 of the License, or (at your option) - * any later version. + * Betaflight is free software. You can redistribute this software + * and/or modify this software under the terms of the GNU General + * Public License as published by the Free Software Foundation, + * either version 3 of the License, or (at your option) any later + * version. + * + * Betaflight is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. * - * Cleanflight and Betaflight are distributed in the hope that they - * will be useful, but WITHOUT ANY WARRANTY; without even the implied - * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. * See the GNU General Public License for more details. * - * You should have received a copy of the GNU General Public License - * along with this software. + * You should have received a copy of the GNU General Public + * License along with this software. * * If not, see . */ diff --git a/src/platform/AT32/persistent_at32bsp.c b/src/platform/AT32/persistent_at32bsp.c index ab497fcc23..b79c5b67ad 100644 --- a/src/platform/AT32/persistent_at32bsp.c +++ b/src/platform/AT32/persistent_at32bsp.c @@ -1,19 +1,20 @@ /* - * This file is part of Cleanflight and Betaflight. + * This file is part of Betaflight. * - * Cleanflight and Betaflight are free software. You can redistribute - * this software and/or modify this software under the terms of the - * GNU General Public License as published by the Free Software - * Foundation, either version 3 of the License, or (at your option) - * any later version. + * Betaflight is free software. You can redistribute this software + * and/or modify this software under the terms of the GNU General + * Public License as published by the Free Software Foundation, + * either version 3 of the License, or (at your option) any later + * version. + * + * Betaflight is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. * - * Cleanflight and Betaflight are distributed in the hope that they - * will be useful, but WITHOUT ANY WARRANTY; without even the implied - * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. * See the GNU General Public License for more details. * - * You should have received a copy of the GNU General Public License - * along with this software. + * You should have received a copy of the GNU General Public + * License along with this software. * * If not, see . */ diff --git a/src/platform/AT32/pwm_output_at32bsp.c b/src/platform/AT32/pwm_output_at32bsp.c index 62a4e4ac6b..3f67b8676c 100644 --- a/src/platform/AT32/pwm_output_at32bsp.c +++ b/src/platform/AT32/pwm_output_at32bsp.c @@ -1,19 +1,20 @@ /* - * This file is part of Cleanflight and Betaflight. + * This file is part of Betaflight. * - * Cleanflight and Betaflight are free software. You can redistribute - * this software and/or modify this software under the terms of the - * GNU General Public License as published by the Free Software - * Foundation, either version 3 of the License, or (at your option) - * any later version. + * Betaflight is free software. You can redistribute this software + * and/or modify this software under the terms of the GNU General + * Public License as published by the Free Software Foundation, + * either version 3 of the License, or (at your option) any later + * version. + * + * Betaflight is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. * - * Cleanflight and Betaflight are distributed in the hope that they - * will be useful, but WITHOUT ANY WARRANTY; without even the implied - * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. * See the GNU General Public License for more details. * - * You should have received a copy of the GNU General Public License - * along with this software. + * You should have received a copy of the GNU General Public + * License along with this software. * * If not, see . */ diff --git a/src/platform/AT32/pwm_output_dshot.c b/src/platform/AT32/pwm_output_dshot.c index ddaf7ed3e9..0998db708d 100644 --- a/src/platform/AT32/pwm_output_dshot.c +++ b/src/platform/AT32/pwm_output_dshot.c @@ -1,19 +1,20 @@ /* - * This file is part of Cleanflight and Betaflight. + * This file is part of Betaflight. * - * Cleanflight and Betaflight are free software. You can redistribute - * this software and/or modify this software under the terms of the - * GNU General Public License as published by the Free Software - * Foundation, either version 3 of the License, or (at your option) - * any later version. + * Betaflight is free software. You can redistribute this software + * and/or modify this software under the terms of the GNU General + * Public License as published by the Free Software Foundation, + * either version 3 of the License, or (at your option) any later + * version. + * + * Betaflight is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. * - * Cleanflight and Betaflight are distributed in the hope that they - * will be useful, but WITHOUT ANY WARRANTY; without even the implied - * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. * See the GNU General Public License for more details. * - * You should have received a copy of the GNU General Public License - * along with this software. + * You should have received a copy of the GNU General Public + * License along with this software. * * If not, see . */ diff --git a/src/platform/AT32/serial_uart_at32bsp.c b/src/platform/AT32/serial_uart_at32bsp.c index f2f6233723..0875364108 100644 --- a/src/platform/AT32/serial_uart_at32bsp.c +++ b/src/platform/AT32/serial_uart_at32bsp.c @@ -1,19 +1,20 @@ /* - * This file is part of Cleanflight and Betaflight. + * This file is part of Betaflight. * - * Cleanflight and Betaflight are free software. You can redistribute - * this software and/or modify this software under the terms of the - * GNU General Public License as published by the Free Software - * Foundation, either version 3 of the License, or (at your option) - * any later version. + * Betaflight is free software. You can redistribute this software + * and/or modify this software under the terms of the GNU General + * Public License as published by the Free Software Foundation, + * either version 3 of the License, or (at your option) any later + * version. + * + * Betaflight is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. * - * Cleanflight and Betaflight are distributed in the hope that they - * will be useful, but WITHOUT ANY WARRANTY; without even the implied - * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. * See the GNU General Public License for more details. * - * You should have received a copy of the GNU General Public License - * along with this software. + * You should have received a copy of the GNU General Public + * License along with this software. * * If not, see . */ diff --git a/src/platform/AT32/serial_usb_vcp_at32f4.c b/src/platform/AT32/serial_usb_vcp_at32f4.c index 5fa490b933..f0fc0ce44d 100644 --- a/src/platform/AT32/serial_usb_vcp_at32f4.c +++ b/src/platform/AT32/serial_usb_vcp_at32f4.c @@ -1,19 +1,20 @@ /* - * This file is part of Cleanflight and Betaflight. + * This file is part of Betaflight. * - * Cleanflight and Betaflight are free software. You can redistribute - * this software and/or modify this software under the terms of the - * GNU General Public License as published by the Free Software - * Foundation, either version 3 of the License, or (at your option) - * any later version. + * Betaflight is free software. You can redistribute this software + * and/or modify this software under the terms of the GNU General + * Public License as published by the Free Software Foundation, + * either version 3 of the License, or (at your option) any later + * version. + * + * Betaflight is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. * - * Cleanflight and Betaflight are distributed in the hope that they - * will be useful, but WITHOUT ANY WARRANTY; without even the implied - * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. * See the GNU General Public License for more details. * - * You should have received a copy of the GNU General Public License - * along with this software. + * You should have received a copy of the GNU General Public + * License along with this software. * * If not, see . */ diff --git a/src/platform/AT32/system_at32f43x.c b/src/platform/AT32/system_at32f43x.c index 35188ae848..8f4f7d76af 100644 --- a/src/platform/AT32/system_at32f43x.c +++ b/src/platform/AT32/system_at32f43x.c @@ -1,19 +1,20 @@ /* - * This file is part of Cleanflight and Betaflight. + * This file is part of Betaflight. * - * Cleanflight and Betaflight are free software. You can redistribute - * this software and/or modify this software under the terms of the - * GNU General Public License as published by the Free Software - * Foundation, either version 3 of the License, or (at your option) - * any later version. + * Betaflight is free software. You can redistribute this software + * and/or modify this software under the terms of the GNU General + * Public License as published by the Free Software Foundation, + * either version 3 of the License, or (at your option) any later + * version. + * + * Betaflight is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. * - * Cleanflight and Betaflight are distributed in the hope that they - * will be useful, but WITHOUT ANY WARRANTY; without even the implied - * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. * See the GNU General Public License for more details. * - * You should have received a copy of the GNU General Public License - * along with this software. + * You should have received a copy of the GNU General Public + * License along with this software. * * If not, see . */ diff --git a/src/platform/AT32/target/AT32F435G/target.h b/src/platform/AT32/target/AT32F435G/target.h index 2399974ad8..76a4e039dc 100644 --- a/src/platform/AT32/target/AT32F435G/target.h +++ b/src/platform/AT32/target/AT32F435G/target.h @@ -1,19 +1,20 @@ /* - * This file is part of Cleanflight and Betaflight. + * This file is part of Betaflight. * - * Cleanflight and Betaflight are free software. You can redistribute - * this software and/or modify this software under the terms of the - * GNU General Public License as published by the Free Software - * Foundation, either version 3 of the License, or (at your option) - * any later version. + * Betaflight is free software. You can redistribute this software + * and/or modify this software under the terms of the GNU General + * Public License as published by the Free Software Foundation, + * either version 3 of the License, or (at your option) any later + * version. + * + * Betaflight is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. * - * Cleanflight and Betaflight are distributed in the hope that they - * will be useful, but WITHOUT ANY WARRANTY; without even the implied - * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. * See the GNU General Public License for more details. * - * You should have received a copy of the GNU General Public License - * along with this software. + * You should have received a copy of the GNU General Public + * License along with this software. * * If not, see . */ diff --git a/src/platform/AT32/target/AT32F435M/target.h b/src/platform/AT32/target/AT32F435M/target.h index 1a25cb9f35..3429a10876 100644 --- a/src/platform/AT32/target/AT32F435M/target.h +++ b/src/platform/AT32/target/AT32F435M/target.h @@ -1,19 +1,20 @@ /* - * This file is part of Cleanflight and Betaflight. + * This file is part of Betaflight. * - * Cleanflight and Betaflight are free software. You can redistribute - * this software and/or modify this software under the terms of the - * GNU General Public License as published by the Free Software - * Foundation, either version 3 of the License, or (at your option) - * any later version. + * Betaflight is free software. You can redistribute this software + * and/or modify this software under the terms of the GNU General + * Public License as published by the Free Software Foundation, + * either version 3 of the License, or (at your option) any later + * version. + * + * Betaflight is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. * - * Cleanflight and Betaflight are distributed in the hope that they - * will be useful, but WITHOUT ANY WARRANTY; without even the implied - * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. * See the GNU General Public License for more details. * - * You should have received a copy of the GNU General Public License - * along with this software. + * You should have received a copy of the GNU General Public + * License along with this software. * * If not, see . */ diff --git a/src/platform/AT32/timer_at32bsp.c b/src/platform/AT32/timer_at32bsp.c index eb7547ebda..b0a584b83e 100644 --- a/src/platform/AT32/timer_at32bsp.c +++ b/src/platform/AT32/timer_at32bsp.c @@ -1,19 +1,20 @@ /* - * This file is part of Cleanflight and Betaflight. + * This file is part of Betaflight. * - * Cleanflight and Betaflight are free software. You can redistribute - * this software and/or modify this software under the terms of the - * GNU General Public License as published by the Free Software - * Foundation, either version 3 of the License, or (at your option) - * any later version. + * Betaflight is free software. You can redistribute this software + * and/or modify this software under the terms of the GNU General + * Public License as published by the Free Software Foundation, + * either version 3 of the License, or (at your option) any later + * version. + * + * Betaflight is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. * - * Cleanflight and Betaflight are distributed in the hope that they - * will be useful, but WITHOUT ANY WARRANTY; without even the implied - * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. * See the GNU General Public License for more details. * - * You should have received a copy of the GNU General Public License - * along with this software. + * You should have received a copy of the GNU General Public + * License along with this software. * * If not, see . */ diff --git a/src/platform/AT32/timer_at32f43x.c b/src/platform/AT32/timer_at32f43x.c index 8a4e39004d..13c4b99b87 100644 --- a/src/platform/AT32/timer_at32f43x.c +++ b/src/platform/AT32/timer_at32f43x.c @@ -1,19 +1,20 @@ /* - * This file is part of Cleanflight and Betaflight. + * This file is part of Betaflight. * - * Cleanflight and Betaflight are free software. You can redistribute - * this software and/or modify this software under the terms of the - * GNU General Public License as published by the Free Software - * Foundation, either version 3 of the License, or (at your option) - * any later version. + * Betaflight is free software. You can redistribute this software + * and/or modify this software under the terms of the GNU General + * Public License as published by the Free Software Foundation, + * either version 3 of the License, or (at your option) any later + * version. + * + * Betaflight is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. * - * Cleanflight and Betaflight are distributed in the hope that they - * will be useful, but WITHOUT ANY WARRANTY; without even the implied - * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. * See the GNU General Public License for more details. * - * You should have received a copy of the GNU General Public License - * along with this software. + * You should have received a copy of the GNU General Public + * License along with this software. * * If not, see . */ diff --git a/src/platform/AT32/usb_msc_at32f43x.c b/src/platform/AT32/usb_msc_at32f43x.c index 42e7ec32ea..007dd07b0b 100644 --- a/src/platform/AT32/usb_msc_at32f43x.c +++ b/src/platform/AT32/usb_msc_at32f43x.c @@ -1,19 +1,20 @@ /* - * This file is part of Cleanflight and Betaflight. + * This file is part of Betaflight. * - * Cleanflight and Betaflight are free software. You can redistribute - * this software and/or modify this software under the terms of the - * GNU General Public License as published by the Free Software - * Foundation, either version 3 of the License, or (at your option) - * any later version. + * Betaflight is free software. You can redistribute this software + * and/or modify this software under the terms of the GNU General + * Public License as published by the Free Software Foundation, + * either version 3 of the License, or (at your option) any later + * version. + * + * Betaflight is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. * - * Cleanflight and Betaflight are distributed in the hope that they - * will be useful, but WITHOUT ANY WARRANTY; without even the implied - * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. * See the GNU General Public License for more details. * - * You should have received a copy of the GNU General Public License - * along with this software. + * You should have received a copy of the GNU General Public + * License along with this software. * * If not, see . */ From 578ddd16ce71bbc15457ca7fcc24d7fff4c81b1c Mon Sep 17 00:00:00 2001 From: Mark Haslinghuis Date: Fri, 17 Jan 2025 12:38:09 +0100 Subject: [PATCH 055/244] Refactor compass align defines (#14159) * Remove unused compass align defines * Use ALIGN_DEFAULT * Use single define for custom alignment * Unify custom alignment --- src/main/sensors/compass.c | 27 +++++---------------------- 1 file changed, 5 insertions(+), 22 deletions(-) diff --git a/src/main/sensors/compass.c b/src/main/sensors/compass.c index e5f5c9332f..4a1bfc99d3 100644 --- a/src/main/sensors/compass.c +++ b/src/main/sensors/compass.c @@ -158,7 +158,11 @@ void compassPreInit(void) #if !defined(SIMULATOR_BUILD) bool compassDetect(magDev_t *magDev, uint8_t *alignment) { - *alignment = ALIGN_DEFAULT; // may be overridden if target specifies MAG_*_ALIGN +#ifdef MAG_ALIGN + *alignment = MAG_ALIGN; +#else + *alignment = ALIGN_DEFAULT; +#endif magSensor_e magHardware = MAG_NONE; @@ -221,9 +225,6 @@ bool compassDetect(magDev_t *magDev, uint8_t *alignment) } if (hmc5883lDetect(magDev)) { -#ifdef MAG_HMC5883_ALIGN - *alignment = MAG_HMC5883_ALIGN; -#endif magHardware = MAG_HMC5883; break; } @@ -237,9 +238,6 @@ bool compassDetect(magDev_t *magDev, uint8_t *alignment) } if (lis2mdlDetect(magDev)) { -#ifdef MAG_LIS2MDL_ALIGN - *alignment = MAG_LIS2MDL_ALIGN; -#endif magHardware = MAG_LIS2MDL; break; } @@ -253,9 +251,6 @@ bool compassDetect(magDev_t *magDev, uint8_t *alignment) } if (lis3mdlDetect(magDev)) { -#ifdef MAG_LIS3MDL_ALIGN - *alignment = MAG_LIS3MDL_ALIGN; -#endif magHardware = MAG_LIS3MDL; break; } @@ -269,9 +264,6 @@ bool compassDetect(magDev_t *magDev, uint8_t *alignment) } if (ak8975Detect(magDev)) { -#ifdef MAG_AK8975_ALIGN - *alignment = MAG_AK8975_ALIGN; -#endif magHardware = MAG_AK8975; break; } @@ -290,9 +282,6 @@ bool compassDetect(magDev_t *magDev, uint8_t *alignment) } if (ak8963Detect(magDev)) { -#ifdef MAG_AK8963_ALIGN - *alignment = MAG_AK8963_ALIGN; -#endif magHardware = MAG_AK8963; break; } @@ -306,9 +295,6 @@ bool compassDetect(magDev_t *magDev, uint8_t *alignment) } if (qmc5883lDetect(magDev)) { -#ifdef MAG_QMC5883L_ALIGN - *alignment = MAG_QMC5883L_ALIGN; -#endif magHardware = MAG_QMC5883; break; } @@ -322,9 +308,6 @@ bool compassDetect(magDev_t *magDev, uint8_t *alignment) } if (ist8310Detect(magDev)) { -#ifdef MAG_IST8310_ALIGN - *alignment = MAG_IST8310_ALIGN; -#endif magHardware = MAG_IST8310; break; } From 6d5ed84f96891ce327f22197d1186468d3e83efa Mon Sep 17 00:00:00 2001 From: Mark Haslinghuis Date: Fri, 17 Jan 2025 17:26:21 +0100 Subject: [PATCH 056/244] Flip FM priority for ALTH / POSH (OSD, CRSF, LTM) (#14165) Flip FM priority for ALTH / POSH --- src/main/osd/osd_elements.c | 4 ++-- src/main/telemetry/crsf.c | 4 ++-- src/main/telemetry/ltm.c | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/src/main/osd/osd_elements.c b/src/main/osd/osd_elements.c index 23ddd5c9e4..1edd59843b 100644 --- a/src/main/osd/osd_elements.c +++ b/src/main/osd/osd_elements.c @@ -1074,10 +1074,10 @@ static void osdElementFlymode(osdElementParms_t *element) strcpy(element->buff, "HEAD"); } else if (FLIGHT_MODE(PASSTHRU_MODE)) { strcpy(element->buff, "PASS"); - } else if (FLIGHT_MODE(ALT_HOLD_MODE)) { - strcpy(element->buff, "ALTH"); } else if (FLIGHT_MODE(POS_HOLD_MODE)) { strcpy(element->buff, "POSH"); + } else if (FLIGHT_MODE(ALT_HOLD_MODE)) { + strcpy(element->buff, "ALTH"); } else if (FLIGHT_MODE(ANGLE_MODE)) { strcpy(element->buff, "ANGL"); } else if (FLIGHT_MODE(HORIZON_MODE)) { diff --git a/src/main/telemetry/crsf.c b/src/main/telemetry/crsf.c index b2e48657ef..68d654831b 100644 --- a/src/main/telemetry/crsf.c +++ b/src/main/telemetry/crsf.c @@ -457,10 +457,10 @@ void crsfFrameFlightMode(sbuf_t *dst) flightMode = "PASS"; } else if (FLIGHT_MODE(ANGLE_MODE)) { flightMode = "ANGL"; - } else if (FLIGHT_MODE(ALT_HOLD_MODE)) { - flightMode = "ALTH"; } else if (FLIGHT_MODE(POS_HOLD_MODE)) { flightMode = "POSH"; + } else if (FLIGHT_MODE(ALT_HOLD_MODE)) { + flightMode = "ALTH"; } else if (FLIGHT_MODE(HORIZON_MODE)) { flightMode = "HOR"; } else if (isAirmodeEnabled()) { diff --git a/src/main/telemetry/ltm.c b/src/main/telemetry/ltm.c index 733477b3ec..7322a7eb11 100644 --- a/src/main/telemetry/ltm.c +++ b/src/main/telemetry/ltm.c @@ -175,10 +175,10 @@ static void ltm_sframe(void) lt_flightmode = 2; else if (FLIGHT_MODE(HORIZON_MODE)) lt_flightmode = 3; - else if (FLIGHT_MODE(ALT_HOLD_MODE)) - lt_flightmode = 8; else if (FLIGHT_MODE(POS_HOLD_MODE)) lt_flightmode = 9; + else if (FLIGHT_MODE(ALT_HOLD_MODE)) + lt_flightmode = 8; else if (FLIGHT_MODE(GPS_RESCUE_MODE)) lt_flightmode = 13; else From cec5d00bbf7fb517285554c6f677d0a373d86227 Mon Sep 17 00:00:00 2001 From: Jay Blackman Date: Sat, 18 Jan 2025 04:17:57 +1100 Subject: [PATCH 057/244] Remove MCU name table from CLI (rely on build info), add MCU info MSP2 command (#14148) --- src/main/build/build_config.c | 58 +--- src/main/build/build_config.h | 7 + src/main/cli/cli.c | 37 +-- src/main/common/streambuf.c | 8 + src/main/common/streambuf.h | 1 + src/main/msp/msp.c | 311 +++++++++++----------- src/main/msp/msp_protocol_v2_betaflight.h | 1 + src/platform/SIMULATOR/sitl.c | 6 + src/platform/common/stm32/system.c | 63 +++++ src/test/unit/cli_unittest.cc | 3 +- 10 files changed, 246 insertions(+), 249 deletions(-) diff --git a/src/main/build/build_config.c b/src/main/build/build_config.c index 70117e0407..1754fe3558 100644 --- a/src/main/build/build_config.c +++ b/src/main/build/build_config.c @@ -31,54 +31,12 @@ mcuTypeId_e getMcuTypeId(void) { -#if defined(SIMULATOR_BUILD) - return MCU_TYPE_SIMULATOR; -#elif defined(STM32F40_41xxx) - return MCU_TYPE_F40X; -#elif defined(STM32F411xE) - return MCU_TYPE_F411; -#elif defined(STM32F446xx) - return MCU_TYPE_F446; -#elif defined(STM32F722xx) - return MCU_TYPE_F722; -#elif defined(STM32F745xx) - return MCU_TYPE_F745; -#elif defined(STM32F746xx) - return MCU_TYPE_F746; -#elif defined(STM32F765xx) - return MCU_TYPE_F765; -#elif defined(STM32H750xx) - return MCU_TYPE_H750; -#elif defined(STM32H730xx) - return MCU_TYPE_H730; -#elif defined(STM32H743xx) - switch (HAL_GetREVID()) { - case REV_ID_Y: - return MCU_TYPE_H743_REV_Y; - case REV_ID_X: - return MCU_TYPE_H743_REV_X; - case REV_ID_V: - return MCU_TYPE_H743_REV_V; - default: - return MCU_TYPE_H743_REV_UNKNOWN; - } -#elif defined(STM32H7A3xx) || defined(STM32H7A3xxQ) - return MCU_TYPE_H7A3; -#elif defined(STM32H723xx) || defined(STM32H725xx) - return MCU_TYPE_H723_725; -#elif defined(STM32G474xx) - return MCU_TYPE_G474; -#elif defined(AT32F435G) - return MCU_TYPE_AT32F435G; -#elif defined(AT32F435M) - return MCU_TYPE_AT32F435M; -#elif defined(APM32F405) - return MCU_TYPE_APM32F405; -#elif defined(APM32F407) - return MCU_TYPE_APM32F407; -#elif defined(RP2350B) - return MCU_TYPE_RP2350B; -#else - return MCU_TYPE_UNKNOWN; -#endif + const mcuTypeInfo_t *mcuTypeInfo = getMcuTypeInfo(); + return mcuTypeInfo ? mcuTypeInfo->id : MCU_TYPE_UNKNOWN; +} + +const char *getMcuTypeName(void) +{ + const mcuTypeInfo_t *mcuTypeInfo = getMcuTypeInfo(); + return mcuTypeInfo ? mcuTypeInfo->name : "Unknown"; } diff --git a/src/main/build/build_config.h b/src/main/build/build_config.h index b187d06de1..4665627e47 100644 --- a/src/main/build/build_config.h +++ b/src/main/build/build_config.h @@ -68,4 +68,11 @@ typedef enum { MCU_TYPE_UNKNOWN = 255, } mcuTypeId_e; +typedef struct mcuTypeInfo_s { + mcuTypeId_e id; + const char *name; +} mcuTypeInfo_t; + +const mcuTypeInfo_t *getMcuTypeInfo(void); mcuTypeId_e getMcuTypeId(void); +const char *getMcuTypeName(void); diff --git a/src/main/cli/cli.c b/src/main/cli/cli.c index 12dd19cd87..ce5dbddab7 100644 --- a/src/main/cli/cli.c +++ b/src/main/cli/cli.c @@ -279,32 +279,6 @@ static const char * const *sensorHardwareNames[] = { }; #endif // USE_SENSOR_NAMES -// Needs to be aligned with mcuTypeId_e -static const char *mcuTypeNames[MCU_TYPE_COUNT] = { - "SIMULATOR", - "F40X", - "F411", - "F446", - "F722", - "F745", - "F746", - "F765", - "H750", - "H743 (Rev Unknown)", - "H743 (Rev.Y)", - "H743 (Rev.X)", - "H743 (Rev.V)", - "H7A3", - "H723/H725", - "G474", - "H730", - "AT32F435G", - "APM32F405", - "APM32F407", - "AT32F435M", - "RP2350B", -}; - static const char *configurationStates[] = { [CONFIGURATION_STATE_UNCONFIGURED] = "UNCONFIGURED", [CONFIGURATION_STATE_CONFIGURED] = "CONFIGURED" @@ -4692,15 +4666,6 @@ STATIC_UNIT_TESTED void cliSet(const char *cmdName, char *cmdline) } } -static const char *getMcuTypeById(mcuTypeId_e id) -{ - if (id < ARRAYLEN(mcuTypeNames)) { - return mcuTypeNames[id]; - } else { - return "UNKNOWN"; - } -} - static void cliStatus(const char *cmdName, char *cmdline) { UNUSED(cmdName); @@ -4708,7 +4673,7 @@ static void cliStatus(const char *cmdName, char *cmdline) // MCU type, clock, vrefint, core temperature - cliPrintf("MCU %s Clock=%dMHz", getMcuTypeById(getMcuTypeId()), (SystemCoreClock / 1000000)); + cliPrintf("MCU %s Clock=%dMHz", getMcuTypeName(), (SystemCoreClock / 1000000)); #if defined(STM32F4) || defined(STM32G4) || defined(APM32F4) // Only F4 and G4 is capable of switching between HSE/HSI (for now) diff --git a/src/main/common/streambuf.c b/src/main/common/streambuf.c index 0268b6db32..f208907cf5 100644 --- a/src/main/common/streambuf.c +++ b/src/main/common/streambuf.c @@ -24,6 +24,7 @@ #include "platform.h" #include "streambuf.h" +#include "common/maths.h" sbuf_t *sbufInit(sbuf_t *sbuf, uint8_t *ptr, uint8_t *end) { @@ -82,6 +83,13 @@ void sbufWriteString(sbuf_t *dst, const char *string) sbufWriteData(dst, string, strlen(string)); } +void sbufWritePString(sbuf_t *dst, const char *string) +{ + const int length = MIN((int)strlen(string), 255); + sbufWriteU8(dst, length); + sbufWriteData(dst, string, length); +} + void sbufWriteStringWithZeroTerminator(sbuf_t *dst, const char *string) { sbufWriteData(dst, string, strlen(string) + 1); diff --git a/src/main/common/streambuf.h b/src/main/common/streambuf.h index 3eff560e98..7a5b0831a7 100644 --- a/src/main/common/streambuf.h +++ b/src/main/common/streambuf.h @@ -39,6 +39,7 @@ void sbufWriteU32BigEndian(sbuf_t *dst, uint32_t val); void sbufFill(sbuf_t *dst, uint8_t data, int len); void sbufWriteData(sbuf_t *dst, const void *data, int len); void sbufWriteString(sbuf_t *dst, const char *string); +void sbufWritePString(sbuf_t *dst, const char *string); void sbufWriteStringWithZeroTerminator(sbuf_t *dst, const char *string); uint8_t sbufReadU8(sbuf_t *src); diff --git a/src/main/msp/msp.c b/src/main/msp/msp.c index 891a5cf7da..4b83a4708c 100644 --- a/src/main/msp/msp.c +++ b/src/main/msp/msp.c @@ -409,8 +409,7 @@ void mspReboot(dispatchEntry_t* self) mspRebootFn(NULL); } -dispatchEntry_t mspRebootEntry = -{ +dispatchEntry_t mspRebootEntry = { mspReboot, 0, NULL, false }; @@ -433,8 +432,7 @@ void writeReadEeprom(dispatchEntry_t* self) #endif } -dispatchEntry_t writeReadEepromEntry = -{ +dispatchEntry_t writeReadEepromEntry = { writeReadEeprom, 0, NULL, false }; @@ -643,8 +641,13 @@ static bool mspCommonProcessOutCommand(int16_t cmdMSP, sbuf_t *dst, mspPostProce sbufWriteU8(dst, FC_VERSION_PATCH_LEVEL); break; - case MSP_BOARD_INFO: - { + case MSP2_MCU_INFO: { + sbufWriteU8(dst, getMcuTypeId()); + sbufWritePString(dst, getMcuTypeName()); + break; + } + + case MSP_BOARD_INFO: { sbufWriteData(dst, systemConfig()->boardIdentifier, BOARD_IDENTIFIER_LENGTH); #ifdef USE_HARDWARE_REVISION_DETECTION sbufWriteU16(dst, hardwareRevision); @@ -682,19 +685,14 @@ static bool mspCommonProcessOutCommand(int16_t cmdMSP, sbuf_t *dst, mspPostProce sbufWriteU8(dst, targetCapabilities); // Target name with explicit length - sbufWriteU8(dst, strlen(targetName)); - sbufWriteData(dst, targetName, strlen(targetName)); + sbufWritePString(dst, targetName); #if defined(USE_BOARD_INFO) // Board name with explicit length - char *value = getBoardName(); - sbufWriteU8(dst, strlen(value)); - sbufWriteString(dst, value); + sbufWritePString(dst, getBoardName()); // Manufacturer id with explicit length - value = getManufacturerId(); - sbufWriteU8(dst, strlen(value)); - sbufWriteString(dst, value); + sbufWritePString(dst, getManufacturerId()); #else sbufWriteU8(dst, 0); sbufWriteU8(dst, 0); @@ -845,28 +843,27 @@ static bool mspCommonProcessOutCommand(int16_t cmdMSP, sbuf_t *dst, mspPostProce break; } - case MSP_VOLTAGE_METER_CONFIG: - { - // by using a sensor type and a sub-frame length it's possible to configure any type of voltage meter, - // e.g. an i2c/spi/can sensor or any sensor not built directly into the FC such as ESC/RX/SPort/SBus that has - // different configuration requirements. - STATIC_ASSERT(VOLTAGE_SENSOR_ADC_VBAT == 0, VOLTAGE_SENSOR_ADC_VBAT_incorrect); // VOLTAGE_SENSOR_ADC_VBAT should be the first index - sbufWriteU8(dst, MAX_VOLTAGE_SENSOR_ADC); // voltage meters in payload - for (int i = VOLTAGE_SENSOR_ADC_VBAT; i < MAX_VOLTAGE_SENSOR_ADC; i++) { - const uint8_t adcSensorSubframeLength = 1 + 1 + 1 + 1 + 1; // length of id, type, vbatscale, vbatresdivval, vbatresdivmultipler, in bytes - sbufWriteU8(dst, adcSensorSubframeLength); // ADC sensor sub-frame length + case MSP_VOLTAGE_METER_CONFIG: { + // by using a sensor type and a sub-frame length it's possible to configure any type of voltage meter, + // e.g. an i2c/spi/can sensor or any sensor not built directly into the FC such as ESC/RX/SPort/SBus that has + // different configuration requirements. + STATIC_ASSERT(VOLTAGE_SENSOR_ADC_VBAT == 0, VOLTAGE_SENSOR_ADC_VBAT_incorrect); // VOLTAGE_SENSOR_ADC_VBAT should be the first index + sbufWriteU8(dst, MAX_VOLTAGE_SENSOR_ADC); // voltage meters in payload + for (int i = VOLTAGE_SENSOR_ADC_VBAT; i < MAX_VOLTAGE_SENSOR_ADC; i++) { + const uint8_t adcSensorSubframeLength = 1 + 1 + 1 + 1 + 1; // length of id, type, vbatscale, vbatresdivval, vbatresdivmultipler, in bytes + sbufWriteU8(dst, adcSensorSubframeLength); // ADC sensor sub-frame length - sbufWriteU8(dst, voltageMeterADCtoIDMap[i]); // id of the sensor - sbufWriteU8(dst, VOLTAGE_SENSOR_TYPE_ADC_RESISTOR_DIVIDER); // indicate the type of sensor that the next part of the payload is for + sbufWriteU8(dst, voltageMeterADCtoIDMap[i]); // id of the sensor + sbufWriteU8(dst, VOLTAGE_SENSOR_TYPE_ADC_RESISTOR_DIVIDER); // indicate the type of sensor that the next part of the payload is for - sbufWriteU8(dst, voltageSensorADCConfig(i)->vbatscale); - sbufWriteU8(dst, voltageSensorADCConfig(i)->vbatresdivval); - sbufWriteU8(dst, voltageSensorADCConfig(i)->vbatresdivmultiplier); - } - // if we had any other voltage sensors, this is where we would output any needed configuration + sbufWriteU8(dst, voltageSensorADCConfig(i)->vbatscale); + sbufWriteU8(dst, voltageSensorADCConfig(i)->vbatresdivval); + sbufWriteU8(dst, voltageSensorADCConfig(i)->vbatresdivmultiplier); } - + // if we had any other voltage sensors, this is where we would output any needed configuration break; + } + case MSP_CURRENT_METER_CONFIG: { // the ADC and VIRTUAL sensors have the same configuration requirements, however this API reflects // that this situation may change and allows us to support configuration of any current sensor with @@ -1085,78 +1082,75 @@ static bool mspProcessOutCommand(mspDescriptor_t srcDesc, int16_t cmdMSP, sbuf_t switch (cmdMSP) { case MSP_STATUS_EX: - case MSP_STATUS: - { - boxBitmask_t flightModeFlags; - const int flagBits = packFlightModeFlags(&flightModeFlags); + case MSP_STATUS: { + boxBitmask_t flightModeFlags; + const int flagBits = packFlightModeFlags(&flightModeFlags); - sbufWriteU16(dst, getTaskDeltaTimeUs(TASK_PID)); + sbufWriteU16(dst, getTaskDeltaTimeUs(TASK_PID)); #ifdef USE_I2C - sbufWriteU16(dst, i2cGetErrorCounter()); + sbufWriteU16(dst, i2cGetErrorCounter()); #else - sbufWriteU16(dst, 0); + sbufWriteU16(dst, 0); #endif - sbufWriteU16(dst, sensors(SENSOR_ACC) | sensors(SENSOR_BARO) << 1 | sensors(SENSOR_MAG) << 2 | sensors(SENSOR_GPS) << 3 | sensors(SENSOR_RANGEFINDER) << 4 | sensors(SENSOR_GYRO) << 5); - sbufWriteData(dst, &flightModeFlags, 4); // unconditional part of flags, first 32 bits - sbufWriteU8(dst, getCurrentPidProfileIndex()); - sbufWriteU16(dst, constrain(getAverageSystemLoadPercent(), 0, LOAD_PERCENTAGE_ONE)); - if (cmdMSP == MSP_STATUS_EX) { - sbufWriteU8(dst, PID_PROFILE_COUNT); - sbufWriteU8(dst, getCurrentControlRateProfileIndex()); - } else { // MSP_STATUS - sbufWriteU16(dst, 0); // gyro cycle time - } + sbufWriteU16(dst, sensors(SENSOR_ACC) | sensors(SENSOR_BARO) << 1 | sensors(SENSOR_MAG) << 2 | sensors(SENSOR_GPS) << 3 | sensors(SENSOR_RANGEFINDER) << 4 | sensors(SENSOR_GYRO) << 5); + sbufWriteData(dst, &flightModeFlags, 4); // unconditional part of flags, first 32 bits + sbufWriteU8(dst, getCurrentPidProfileIndex()); + sbufWriteU16(dst, constrain(getAverageSystemLoadPercent(), 0, LOAD_PERCENTAGE_ONE)); + if (cmdMSP == MSP_STATUS_EX) { + sbufWriteU8(dst, PID_PROFILE_COUNT); + sbufWriteU8(dst, getCurrentControlRateProfileIndex()); + } else { // MSP_STATUS + sbufWriteU16(dst, 0); // gyro cycle time + } - // write flightModeFlags header. Lowest 4 bits contain number of bytes that follow - // header is emited even when all bits fit into 32 bits to allow future extension - int byteCount = (flagBits - 32 + 7) / 8; // 32 already stored, round up - byteCount = constrain(byteCount, 0, 15); // limit to 16 bytes (128 bits) - sbufWriteU8(dst, byteCount); - sbufWriteData(dst, ((uint8_t*)&flightModeFlags) + 4, byteCount); + // write flightModeFlags header. Lowest 4 bits contain number of bytes that follow + // header is emited even when all bits fit into 32 bits to allow future extension + int byteCount = (flagBits - 32 + 7) / 8; // 32 already stored, round up + byteCount = constrain(byteCount, 0, 15); // limit to 16 bytes (128 bits) + sbufWriteU8(dst, byteCount); + sbufWriteData(dst, ((uint8_t*)&flightModeFlags) + 4, byteCount); - // Write arming disable flags - // 1 byte, flag count - sbufWriteU8(dst, ARMING_DISABLE_FLAGS_COUNT); - // 4 bytes, flags - const uint32_t armingDisableFlags = getArmingDisableFlags(); - sbufWriteU32(dst, armingDisableFlags); + // Write arming disable flags + // 1 byte, flag count + sbufWriteU8(dst, ARMING_DISABLE_FLAGS_COUNT); + // 4 bytes, flags + const uint32_t armingDisableFlags = getArmingDisableFlags(); + sbufWriteU32(dst, armingDisableFlags); - // config state flags - bits to indicate the state of the configuration, reboot required, etc. - // other flags can be added as needed - sbufWriteU8(dst, (getRebootRequired() << 0)); + // config state flags - bits to indicate the state of the configuration, reboot required, etc. + // other flags can be added as needed + sbufWriteU8(dst, (getRebootRequired() << 0)); - // Added in API version 1.46 - // Write CPU temp + // Added in API version 1.46 + // Write CPU temp #ifdef USE_ADC_INTERNAL - sbufWriteU16(dst, getCoreTemperatureCelsius()); + sbufWriteU16(dst, getCoreTemperatureCelsius()); +#else + sbufWriteU16(dst, 0); +#endif + break; + } + + case MSP_RAW_IMU: { + for (int i = 0; i < 3; i++) { +#if defined(USE_ACC) + sbufWriteU16(dst, lrintf(acc.accADC.v[i])); +#else + sbufWriteU16(dst, 0); +#endif + } + for (int i = 0; i < 3; i++) { + sbufWriteU16(dst, gyroRateDps(i)); + } + for (int i = 0; i < 3; i++) { +#if defined(USE_MAG) + sbufWriteU16(dst, lrintf(mag.magADC.v[i])); #else sbufWriteU16(dst, 0); #endif } break; - - case MSP_RAW_IMU: - { - - for (int i = 0; i < 3; i++) { -#if defined(USE_ACC) - sbufWriteU16(dst, lrintf(acc.accADC.v[i])); -#else - sbufWriteU16(dst, 0); -#endif - } - for (int i = 0; i < 3; i++) { - sbufWriteU16(dst, gyroRateDps(i)); - } - for (int i = 0; i < 3; i++) { -#if defined(USE_MAG) - sbufWriteU16(dst, lrintf(mag.magADC.v[i])); -#else - sbufWriteU16(dst, 0); -#endif - } - } - break; + } case MSP_NAME: sbufWriteString(dst, pilotConfig()->craftName); @@ -1203,7 +1197,6 @@ case MSP_NAME: sbufWriteU16(dst, 0); #endif } - break; // Added in API version 1.42 @@ -1285,32 +1278,29 @@ case MSP_NAME: break; #ifdef USE_VTX_COMMON - case MSP2_GET_VTX_DEVICE_STATUS: - { - const vtxDevice_t *vtxDevice = vtxCommonDevice(); - vtxCommonSerializeDeviceStatus(vtxDevice, dst); - } + case MSP2_GET_VTX_DEVICE_STATUS: { + const vtxDevice_t *vtxDevice = vtxCommonDevice(); + vtxCommonSerializeDeviceStatus(vtxDevice, dst); break; + } #endif #ifdef USE_OSD - case MSP2_GET_OSD_WARNINGS: - { - bool isBlinking; - uint8_t displayAttr; - char warningsBuffer[OSD_WARNINGS_MAX_SIZE + 1]; + case MSP2_GET_OSD_WARNINGS: { + bool isBlinking; + uint8_t displayAttr; + char warningsBuffer[OSD_WARNINGS_MAX_SIZE + 1]; - renderOsdWarning(warningsBuffer, &isBlinking, &displayAttr); - const uint8_t warningsLen = strlen(warningsBuffer); + renderOsdWarning(warningsBuffer, &isBlinking, &displayAttr); - if (isBlinking) { - displayAttr |= DISPLAYPORT_BLINK; - } - sbufWriteU8(dst, displayAttr); // see displayPortSeverity_e - sbufWriteU8(dst, warningsLen); // length byte followed by the actual characters - sbufWriteData(dst, warningsBuffer, warningsLen); - break; + if (isBlinking) { + displayAttr |= DISPLAYPORT_BLINK; } + sbufWriteU8(dst, displayAttr); // see displayPortSeverity_e + sbufWritePString(dst, warningsBuffer); + + break; + } #endif case MSP_RC: @@ -1687,6 +1677,7 @@ case MSP_NAME: sbufWriteU8(dst, serialConfig()->portConfigs[i].blackbox_baudrateIndex); } break; + case MSP2_COMMON_SERIAL_CONFIG: { uint8_t count = 0; for (int i = 0; i < SERIAL_PORT_COUNT; i++) { @@ -1876,6 +1867,7 @@ case MSP_NAME: #endif break; } + case MSP_ADVANCED_CONFIG: sbufWriteU8(dst, 1); // was gyroConfig()->gyro_sync_denom - removed in API 1.43 sbufWriteU8(dst, pidConfig()->pid_process_denom); @@ -1894,9 +1886,9 @@ case MSP_NAME: //Added in MSP API 1.42 sbufWriteU8(dst, systemConfig()->debug_mode); sbufWriteU8(dst, DEBUG_COUNT); - break; - case MSP_FILTER_CONFIG : + + case MSP_FILTER_CONFIG: sbufWriteU8(dst, gyroConfig()->gyro_lpf1_static_hz); sbufWriteU16(dst, currentPidProfile->dterm_lpf1_static_hz); sbufWriteU16(dst, currentPidProfile->yaw_lowpass_hz); @@ -1963,8 +1955,8 @@ case MSP_NAME: #else sbufWriteU8(dst, 0); #endif - break; + case MSP_PID_ADVANCED: sbufWriteU16(dst, 0); sbufWriteU16(dst, 0); @@ -2147,44 +2139,43 @@ case MSP_NAME: break; #if defined(USE_VTX_COMMON) - case MSP_VTX_CONFIG: - { - const vtxDevice_t *vtxDevice = vtxCommonDevice(); - unsigned vtxStatus = 0; - vtxDevType_e vtxType = VTXDEV_UNKNOWN; - uint8_t deviceIsReady = 0; - if (vtxDevice) { - vtxCommonGetStatus(vtxDevice, &vtxStatus); - vtxType = vtxCommonGetDeviceType(vtxDevice); - deviceIsReady = vtxCommonDeviceIsReady(vtxDevice) ? 1 : 0; - } - sbufWriteU8(dst, vtxType); - sbufWriteU8(dst, vtxSettingsConfig()->band); - sbufWriteU8(dst, vtxSettingsConfig()->channel); - sbufWriteU8(dst, vtxSettingsConfig()->power); - sbufWriteU8(dst, (vtxStatus & VTX_STATUS_PIT_MODE) ? 1 : 0); - sbufWriteU16(dst, vtxSettingsConfig()->freq); - sbufWriteU8(dst, deviceIsReady); - sbufWriteU8(dst, vtxSettingsConfig()->lowPowerDisarm); + case MSP_VTX_CONFIG: { + const vtxDevice_t *vtxDevice = vtxCommonDevice(); + unsigned vtxStatus = 0; + vtxDevType_e vtxType = VTXDEV_UNKNOWN; + uint8_t deviceIsReady = 0; + if (vtxDevice) { + vtxCommonGetStatus(vtxDevice, &vtxStatus); + vtxType = vtxCommonGetDeviceType(vtxDevice); + deviceIsReady = vtxCommonDeviceIsReady(vtxDevice) ? 1 : 0; + } + sbufWriteU8(dst, vtxType); + sbufWriteU8(dst, vtxSettingsConfig()->band); + sbufWriteU8(dst, vtxSettingsConfig()->channel); + sbufWriteU8(dst, vtxSettingsConfig()->power); + sbufWriteU8(dst, (vtxStatus & VTX_STATUS_PIT_MODE) ? 1 : 0); + sbufWriteU16(dst, vtxSettingsConfig()->freq); + sbufWriteU8(dst, deviceIsReady); + sbufWriteU8(dst, vtxSettingsConfig()->lowPowerDisarm); - // API version 1.42 - sbufWriteU16(dst, vtxSettingsConfig()->pitModeFreq); + // API version 1.42 + sbufWriteU16(dst, vtxSettingsConfig()->pitModeFreq); #ifdef USE_VTX_TABLE - sbufWriteU8(dst, 1); // vtxtable is available - sbufWriteU8(dst, vtxTableConfig()->bands); - sbufWriteU8(dst, vtxTableConfig()->channels); - sbufWriteU8(dst, vtxTableConfig()->powerLevels); + sbufWriteU8(dst, 1); // vtxtable is available + sbufWriteU8(dst, vtxTableConfig()->bands); + sbufWriteU8(dst, vtxTableConfig()->channels); + sbufWriteU8(dst, vtxTableConfig()->powerLevels); #else - sbufWriteU8(dst, 0); - sbufWriteU8(dst, 0); - sbufWriteU8(dst, 0); - sbufWriteU8(dst, 0); + sbufWriteU8(dst, 0); + sbufWriteU8(dst, 0); + sbufWriteU8(dst, 0); + sbufWriteU8(dst, 0); #endif #ifdef USE_VTX_MSP - setMspVtxDeviceStatusReady(srcDesc); + setMspVtxDeviceStatusReady(srcDesc); #endif - } break; + } #endif case MSP_TX_INFO: @@ -2199,25 +2190,24 @@ case MSP_NAME: rtcDateTimeIsSet = RTC_NOT_SUPPORTED; #endif sbufWriteU8(dst, rtcDateTimeIsSet); - break; + #ifdef USE_RTC_TIME - case MSP_RTC: - { - dateTime_t dt; - if (rtcGetDateTime(&dt)) { - sbufWriteU16(dst, dt.year); - sbufWriteU8(dst, dt.month); - sbufWriteU8(dst, dt.day); - sbufWriteU8(dst, dt.hours); - sbufWriteU8(dst, dt.minutes); - sbufWriteU8(dst, dt.seconds); - sbufWriteU16(dst, dt.millis); - } + case MSP_RTC: { + dateTime_t dt; + if (rtcGetDateTime(&dt)) { + sbufWriteU16(dst, dt.year); + sbufWriteU8(dst, dt.month); + sbufWriteU8(dst, dt.day); + sbufWriteU8(dst, dt.hours); + sbufWriteU8(dst, dt.minutes); + sbufWriteU8(dst, dt.seconds); + sbufWriteU16(dst, dt.millis); } - break; + } #endif + default: unsupportedCommand = true; } @@ -2629,12 +2619,9 @@ static mspResult_e mspFcProcessOutCommandWithArg(mspDescriptor_t srcDesc, int16_ if (!textVar) return MSP_RESULT_ERROR; - const uint8_t textLength = strlen(textVar); - // type byte, then length byte followed by the actual characters sbufWriteU8(dst, textType); - sbufWriteU8(dst, textLength); - sbufWriteData(dst, textVar, textLength); + sbufWritePString(dst, textVar); } break; #ifdef USE_LED_STRIP diff --git a/src/main/msp/msp_protocol_v2_betaflight.h b/src/main/msp/msp_protocol_v2_betaflight.h index beefb27f2f..7a4a6c5758 100644 --- a/src/main/msp/msp_protocol_v2_betaflight.h +++ b/src/main/msp/msp_protocol_v2_betaflight.h @@ -30,6 +30,7 @@ #define MSP2_SET_LED_STRIP_CONFIG_VALUES 0x3009 #define MSP2_SENSOR_CONFIG_ACTIVE 0x300A #define MSP2_SENSOR_OPTICALFLOW 0x300B +#define MSP2_MCU_INFO 0x300C // MSP2_SET_TEXT and MSP2_GET_TEXT variable types #define MSP2TEXT_PILOT_NAME 1 diff --git a/src/platform/SIMULATOR/sitl.c b/src/platform/SIMULATOR/sitl.c index 4a7ab2daca..2325107ae2 100644 --- a/src/platform/SIMULATOR/sitl.c +++ b/src/platform/SIMULATOR/sitl.c @@ -789,3 +789,9 @@ IO_t IOGetByTag(ioTag_t tag) UNUSED(tag); return NULL; } + +const mcuTypeInfo_t *getMcuTypeInfo(void) +{ + static const mcuTypeInfo_t info = { .id = MCU_TYPE_SIMULATOR, .name = "SIMULATOR" }; + return &info; +} diff --git a/src/platform/common/stm32/system.c b/src/platform/common/stm32/system.c index 634fd07b17..d21e0ee956 100644 --- a/src/platform/common/stm32/system.c +++ b/src/platform/common/stm32/system.c @@ -322,3 +322,66 @@ void unusedPinsInit(void) { IOTraversePins(unusedPinInit); } + +const mcuTypeInfo_t *getMcuTypeInfo(void) +{ + static const mcuTypeInfo_t info[] = { +#if defined(STM32H743xx) + { .id = MCU_TYPE_H743_REV_UNKNOWN, .name = "STM32H743 (Rev Unknown)" }, + { .id = MCU_TYPE_H743_REV_Y, .name = "STM32H743 (Rev.Y)" }, + { .id = MCU_TYPE_H743_REV_X, .name = "STM32H743 (Rev.X)" }, + { .id = MCU_TYPE_H743_REV_V, .name = "STM32H743 (Rev.V)" }, +#elif defined(STM32F40_41xxx) + { .id = MCU_TYPE_F40X, .name = "STM32F40X" }, +#elif defined(STM32F411xE) + { .id = MCU_TYPE_F411, .name = "STM32F411" }, +#elif defined(STM32F446xx) + { .id = MCU_TYPE_F446, .name = "STM32F446" }, +#elif defined(STM32F722xx) + { .id = MCU_TYPE_F722, .name = "STM32F722" }, +#elif defined(STM32F745xx) + { .id = MCU_TYPE_F745, .name = "STM32F745" }, +#elif defined(STM32F746xx) + { .id = MCU_TYPE_F746, .name = "STM32F746" }, +#elif defined(STM32F765xx) + { .id = MCU_TYPE_F765, .name = "STM32F765" }, +#elif defined(STM32H750xx) + { .id = MCU_TYPE_H750, .name = "STM32H750" }, +#elif defined(STM32H730xx) + { .id = MCU_TYPE_H730, .name = "STM32H730" }, +#elif defined(STM32H7A3xx) || defined(STM32H7A3xxQ) + { .id = MCU_TYPE_H7A3, .name = "STM32H7A3" }, +#elif defined(STM32H723xx) || defined(STM32H725xx) + { .id = MCU_TYPE_H723_725, .name = "STM32H723/H725" }, +#elif defined(STM32G474xx) + { .id = MCU_TYPE_G474, .name = "STM32G474" }, +#elif defined(AT32F435G) + { .id = MCU_TYPE_AT32F435G, .name = "AT32F435G" }, +#elif defined(AT32F435M) + { .id = MCU_TYPE_AT32F435M, .name = "AT32F435M" }, +#elif defined(APM32F405) + { .id = MCU_TYPE_APM32F405, .name = "APM32F405" }, +#elif defined(APM32F407) + { .id = MCU_TYPE_APM32F407, .name = "APM32F407" }, +#else +#error MCU Type info not defined for STM (or clone) +#endif + }; + unsigned revision = 0; +#if defined(STM32H743xx) + switch (HAL_GetREVID()) { + case REV_ID_Y: + revision = 1; + break; + case REV_ID_X: + revision = 2; + break; + case REV_ID_V: + revision = 3; + break; + default: + revision = 0; + } +#endif + return info + revision; +} diff --git a/src/test/unit/cli_unittest.cc b/src/test/unit/cli_unittest.cc index c756929c8c..4b8417148d 100644 --- a/src/test/unit/cli_unittest.cc +++ b/src/test/unit/cli_unittest.cc @@ -342,7 +342,7 @@ void schedulerResetTaskMaxExecutionTime(taskId_e) {} void schedulerResetCheckFunctionMaxExecutionTime(void) {} const char * const targetName = "UNITTEST"; -const char* const buildDate = "Jan 01 2017"; +const char * const buildDate = "Jan 01 2017"; const char * const buildTime = "00:00:00"; const char * const shortGitRevision = "MASTER"; @@ -401,6 +401,7 @@ bool isModeActivationConditionConfigured(const modeActivationCondition_t *, cons void delay(uint32_t) {} displayPort_t *osdGetDisplayPort(osdDisplayPortDevice_e *) { return NULL; } mcuTypeId_e getMcuTypeId(void) { return MCU_TYPE_UNKNOWN; } +const char *getMcuTypeName(void) { return targetName; } uint16_t getCurrentRxRateHz(void) { return 0; } uint16_t getAverageSystemLoadPercent(void) { return 0; } bool getRxRateValid(void) { return false; } From 9168569d9077b1ae633f648ad9f760a7111bb960 Mon Sep 17 00:00:00 2001 From: Petr Ledvina Date: Fri, 17 Jan 2025 18:34:57 +0100 Subject: [PATCH 058/244] config submodule - follow master (#14175) --- .gitmodules | 1 + mk/config.mk | 2 +- src/config | 2 +- 3 files changed, 3 insertions(+), 2 deletions(-) diff --git a/.gitmodules b/.gitmodules index d663ecb86f..fc19f2d6b8 100644 --- a/.gitmodules +++ b/.gitmodules @@ -1,3 +1,4 @@ [submodule "config"] path = src/config url = https://github.com/betaflight/config.git + branch = master diff --git a/mk/config.mk b/mk/config.mk index 0cbe356da3..adbd3d7c52 100644 --- a/mk/config.mk +++ b/mk/config.mk @@ -52,7 +52,7 @@ endif #config .PHONY: configs configs: ifeq ($(shell realpath $(CONFIG_DIR)),$(shell realpath $(CONFIGS_SUBMODULE_DIR))) - git submodule update --init -- $(CONFIGS_SUBMODULE_DIR) + git submodule update --init --remote -- $(CONFIGS_SUBMODULE_DIR) else ifeq ($(wildcard $(CONFIG_DIR)),) @echo "Hydrating clone for configs: $(CONFIG_DIR)" diff --git a/src/config b/src/config index b0f3ab0cc9..d6644d10a6 160000 --- a/src/config +++ b/src/config @@ -1 +1 @@ -Subproject commit b0f3ab0cc91f80ab930d599da03446f8c54feb8c +Subproject commit d6644d10a62c706075aa5ae328f4e553e620e0a5 From 86b6953a5b39a115b0555c70065100ff02c9dd33 Mon Sep 17 00:00:00 2001 From: "Git bot (blckmn)" Date: Fri, 17 Jan 2025 18:31:32 +0000 Subject: [PATCH 059/244] Auto updated submodule references --- src/config | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/config b/src/config index d6644d10a6..47cacc174e 160000 --- a/src/config +++ b/src/config @@ -1 +1 @@ -Subproject commit d6644d10a62c706075aa5ae328f4e553e620e0a5 +Subproject commit 47cacc174e62ab8c71cc5d16f4f367009065086e From c188a03beb351ccf3a7efaa0d0007b5f4d059a0b Mon Sep 17 00:00:00 2001 From: Mark Haslinghuis Date: Fri, 17 Jan 2025 20:37:26 +0100 Subject: [PATCH 060/244] Fix missing ACCGYRO custom alignment defines (used in config) (#14092) --- src/main/common/sensor_alignment.h | 29 ++++++---- src/main/common/sensor_alignment_impl.h | 11 +++- src/main/pg/gyrodev.c | 73 +++++++++++++++++++------ 3 files changed, 84 insertions(+), 29 deletions(-) diff --git a/src/main/common/sensor_alignment.h b/src/main/common/sensor_alignment.h index b1c7fd9ddf..d9186048e3 100644 --- a/src/main/common/sensor_alignment.h +++ b/src/main/common/sensor_alignment.h @@ -55,20 +55,25 @@ typedef union sensorAlignment_u { }; } sensorAlignment_t; -#define SENSOR_ALIGNMENT(ROLL, PITCH, YAW) ((sensorAlignment_t){\ - .roll = DEGREES_TO_DECIDEGREES(ROLL), \ - .pitch = DEGREES_TO_DECIDEGREES(PITCH), \ - .yaw = DEGREES_TO_DECIDEGREES(YAW), \ +#define SENSOR_ALIGNMENT(ROLL, PITCH, YAW) ((const sensorAlignment_t) { \ + .roll = DEGREES_TO_DECIDEGREES(ROLL), \ + .pitch = DEGREES_TO_DECIDEGREES(PITCH), \ + .yaw = DEGREES_TO_DECIDEGREES(YAW), \ }) -#define CUSTOM_ALIGN_CW0_DEG SENSOR_ALIGNMENT( 0, 0, 0) -#define CUSTOM_ALIGN_CW90_DEG SENSOR_ALIGNMENT( 0, 0, 90) -#define CUSTOM_ALIGN_CW180_DEG SENSOR_ALIGNMENT( 0, 0, 180) -#define CUSTOM_ALIGN_CW270_DEG SENSOR_ALIGNMENT( 0, 0, 270) -#define CUSTOM_ALIGN_CW0_DEG_FLIP SENSOR_ALIGNMENT( 0, 180, 0) -#define CUSTOM_ALIGN_CW90_DEG_FLIP SENSOR_ALIGNMENT( 0, 180, 90) -#define CUSTOM_ALIGN_CW180_DEG_FLIP SENSOR_ALIGNMENT( 0, 180, 180) -#define CUSTOM_ALIGN_CW270_DEG_FLIP SENSOR_ALIGNMENT( 0, 180, 270) +#define CUSTOM_ALIGN_CW(deg) SENSOR_ALIGNMENT( 0, 0, (deg) ) +#define CUSTOM_ALIGN_CW_FLIP(deg) SENSOR_ALIGNMENT( 0, 180, (deg) ) + +#define CUSTOM_ALIGN_CW0_DEG CUSTOM_ALIGN_CW( 0 ) +#define CUSTOM_ALIGN_CW45_DEG CUSTOM_ALIGN_CW( 45 ) +#define CUSTOM_ALIGN_CW90_DEG CUSTOM_ALIGN_CW( 90 ) +#define CUSTOM_ALIGN_CW180_DEG CUSTOM_ALIGN_CW( 180 ) +#define CUSTOM_ALIGN_CW270_DEG CUSTOM_ALIGN_CW( 270 ) +#define CUSTOM_ALIGN_CW0_DEG_FLIP CUSTOM_ALIGN_CW_FLIP( 0 ) +#define CUSTOM_ALIGN_CW45_DEG_FLIP CUSTOM_ALIGN_CW_FLIP( 45 ) +#define CUSTOM_ALIGN_CW90_DEG_FLIP CUSTOM_ALIGN_CW_FLIP( 90 ) +#define CUSTOM_ALIGN_CW180_DEG_FLIP CUSTOM_ALIGN_CW_FLIP( 180 ) +#define CUSTOM_ALIGN_CW270_DEG_FLIP CUSTOM_ALIGN_CW_FLIP( 270 ) void buildRotationMatrixFromAngles(matrix33_t *rm, const sensorAlignment_t *rpy); void buildAlignmentFromStandardAlignment(sensorAlignment_t *rpy, sensor_align_e stdAlignment); diff --git a/src/main/common/sensor_alignment_impl.h b/src/main/common/sensor_alignment_impl.h index 0e8e0b832d..47b289905d 100644 --- a/src/main/common/sensor_alignment_impl.h +++ b/src/main/common/sensor_alignment_impl.h @@ -45,4 +45,13 @@ // [1:0] count of 90 degree rotations from 0 // [3:2] indicates 90 degree rotations on pitch // [5:4] indicates 90 degree rotations on roll -#define ALIGNMENT_TO_BITMASK(alignment) ((alignment - CW0_DEG) & 0x3) | (((alignment - CW0_DEG) & 0x4) << 1) +#define ALIGNMENT_TO_BITMASK(alignment) (((alignment - CW0_DEG) & 0x3) | (((alignment - CW0_DEG) & 0x4) << 1)) + +// build sensorAlignment_t from sensor_align_e as compile-time constant +#define SENSOR_ALIGNMENT_FROM_STD(std_) \ + ( ((std_) >= CW0_DEG && (std_) <= CW270_DEG_FLIP) \ + ? SENSOR_ALIGNMENT(ALIGNMENT_ROLL_ROTATIONS(ALIGNMENT_TO_BITMASK(std_)) * 90, \ + ALIGNMENT_PITCH_ROTATIONS(ALIGNMENT_TO_BITMASK(std_)) * 90, \ + ALIGNMENT_YAW_ROTATIONS(ALIGNMENT_TO_BITMASK(std_)) * 90) \ + : SENSOR_ALIGNMENT(0, 0, 0) ) \ + /**/ diff --git a/src/main/pg/gyrodev.c b/src/main/pg/gyrodev.c index 16e2321e8d..67d2d7d442 100644 --- a/src/main/pg/gyrodev.c +++ b/src/main/pg/gyrodev.c @@ -24,6 +24,7 @@ #include "platform.h" #include "common/sensor_alignment.h" +#include "common/sensor_alignment_impl.h" #include "pg/pg.h" #include "pg/pg_ids.h" @@ -67,13 +68,67 @@ // gyro alignments +#if defined(GYRO_1_ALIGN_ROLL) || defined(GYRO_1_ALIGN_PITCH) || defined(GYRO_1_ALIGN_YAW) +#ifndef GYRO_1_ALIGN_ROLL +#define GYRO_1_ALIGN_ROLL 0 +#endif +#ifndef GYRO_1_ALIGN_PITCH +#define GYRO_1_ALIGN_PITCH 0 +#endif +#ifndef GYRO_1_ALIGN_YAW +#define GYRO_1_ALIGN_YAW 0 +#endif +#ifndef GYRO_1_CUSTOM_ALIGN +#define GYRO_1_CUSTOM_ALIGN SENSOR_ALIGNMENT( GYRO_1_ALIGN_ROLL / 10, GYRO_1_ALIGN_PITCH / 10, GYRO_1_ALIGN_YAW / 10 ) +#else +#error "GYRO_1_ALIGN_x and GYRO_1_CUSTOM_ALIGN are mutually exclusive" +#endif +#endif // GYRO_1_ALIGN_ROLL || GYRO_1_ALIGN_PITCH || GYRO_1_ALIGN_YAW + +#if defined(GYRO_2_ALIGN_ROLL) || defined(GYRO_2_ALIGN_PITCH) || defined(GYRO_2_ALIGN_YAW) +#ifndef GYRO_2_ALIGN_ROLL +#define GYRO_2_ALIGN_ROLL 0 +#endif +#ifndef GYRO_2_ALIGN_PITCH +#define GYRO_2_ALIGN_PITCH 0 +#endif +#ifndef GYRO_2_ALIGN_YAW +#define GYRO_2_ALIGN_YAW 0 +#endif +#ifndef GYRO_2_CUSTOM_ALIGN +#define GYRO_2_CUSTOM_ALIGN SENSOR_ALIGNMENT( GYRO_2_ALIGN_ROLL / 10, GYRO_2_ALIGN_PITCH / 10, GYRO_2_ALIGN_YAW / 10 ) +#else +#error "GYRO_2_ALIGN_x and GYRO_2_CUSTOM_ALIGN are mutually exclusive" +#endif +#endif // GYRO_2_ALIGN_ROLL || GYRO_2_ALIGN_PITCH || GYRO_2_ALIGN_YAW + #ifndef GYRO_1_ALIGN +#ifdef GYRO_1_CUSTOM_ALIGN +#define GYRO_1_ALIGN ALIGN_CUSTOM +#else #define GYRO_1_ALIGN CW0_DEG #endif +#endif // GYRO_1_ALIGN + +#ifndef GYRO_1_CUSTOM_ALIGN +#define GYRO_1_CUSTOM_ALIGN SENSOR_ALIGNMENT_FROM_STD(GYRO_1_ALIGN) +#else +STATIC_ASSERT(GYRO_1_ALIGN == ALIGN_CUSTOM, "GYRO_1_ALIGN and GYRO_1_CUSTOM_ALIGN mixed"); +#endif // GYRO_1_CUSTOM_ALIGN #ifndef GYRO_2_ALIGN +#ifdef GYRO_2_CUSTOM_ALIGN +#define GYRO_2_ALIGN ALIGN_CUSTOM +#else #define GYRO_2_ALIGN CW0_DEG #endif +#endif // GYRO_2_ALIGN + +#ifndef GYRO_2_CUSTOM_ALIGN +#define GYRO_2_CUSTOM_ALIGN SENSOR_ALIGNMENT_FROM_STD(GYRO_2_ALIGN) +#else +STATIC_ASSERT(GYRO_2_ALIGN == ALIGN_CUSTOM, "GYRO_2_ALIGN and GYRO_2_CUSTOM_ALIGN mixed"); +#endif // GYRO_2_CUSTOM_ALIGN #if defined(USE_SPI_GYRO) && (defined(GYRO_1_SPI_INSTANCE) || defined(GYRO_2_SPI_INSTANCE)) static void gyroResetSpiDeviceConfig(gyroDeviceConfig_t *devconf, SPI_TypeDef *instance, ioTag_t csnTag, ioTag_t extiTag, ioTag_t clkInTag, uint8_t alignment, sensorAlignment_t customAlignment) @@ -105,32 +160,18 @@ PG_REGISTER_ARRAY_WITH_RESET_FN(gyroDeviceConfig_t, MAX_GYRODEV_COUNT, gyroDevic void pgResetFn_gyroDeviceConfig(gyroDeviceConfig_t *devconf) { devconf[0].index = 0; - sensorAlignment_t customAlignment1 = CUSTOM_ALIGN_CW0_DEG; -#ifdef GYRO_1_CUSTOM_ALIGN - customAlignment1 = GYRO_1_CUSTOM_ALIGN; -#else - buildAlignmentFromStandardAlignment(&customAlignment1, GYRO_1_ALIGN); -#endif // GYRO_1_CUSTOM_ALIGN - // All multi-gyro boards use SPI based gyros. #ifdef USE_SPI_GYRO #ifdef GYRO_1_SPI_INSTANCE - gyroResetSpiDeviceConfig(&devconf[0], GYRO_1_SPI_INSTANCE, IO_TAG(GYRO_1_CS_PIN), IO_TAG(GYRO_1_EXTI_PIN), IO_TAG(GYRO_1_CLKIN_PIN), GYRO_1_ALIGN, customAlignment1); + gyroResetSpiDeviceConfig(&devconf[0], GYRO_1_SPI_INSTANCE, IO_TAG(GYRO_1_CS_PIN), IO_TAG(GYRO_1_EXTI_PIN), IO_TAG(GYRO_1_CLKIN_PIN), GYRO_1_ALIGN, GYRO_1_CUSTOM_ALIGN); #else devconf[0].busType = BUS_TYPE_NONE; #endif #ifdef USE_MULTI_GYRO devconf[1].index = 1; - sensorAlignment_t customAlignment2 = CUSTOM_ALIGN_CW0_DEG; -#ifdef GYRO_2_CUSTOM_ALIGN - customAlignment2 = GYRO_2_CUSTOM_ALIGN; -#else - buildAlignmentFromStandardAlignment(&customAlignment2, GYRO_2_ALIGN); -#endif // GYRO_2_CUSTOM_ALIGN - #ifdef GYRO_2_SPI_INSTANCE // TODO: CLKIN gyro 2 on separate pin is not supported yet. need to implement it - gyroResetSpiDeviceConfig(&devconf[1], GYRO_2_SPI_INSTANCE, IO_TAG(GYRO_2_CS_PIN), IO_TAG(GYRO_2_EXTI_PIN), IO_TAG(GYRO_2_CLKIN_PIN), GYRO_2_ALIGN, customAlignment2); + gyroResetSpiDeviceConfig(&devconf[1], GYRO_2_SPI_INSTANCE, IO_TAG(GYRO_2_CS_PIN), IO_TAG(GYRO_2_EXTI_PIN), IO_TAG(GYRO_2_CLKIN_PIN), GYRO_2_ALIGN, GYRO_2_CUSTOM_ALIGN); #else devconf[1].busType = BUS_TYPE_NONE; #endif From 994b41735f7238bdfa52a7d6978895a55a007465 Mon Sep 17 00:00:00 2001 From: Jacob Dahl <37091262+dakejahl@users.noreply.github.com> Date: Fri, 17 Jan 2025 11:22:08 -0900 Subject: [PATCH 061/244] lis2mdl: Enable OFF_CANC and BDU (#14176) --- src/main/drivers/compass/compass_lis2mdl.c | 183 +++++++-------------- 1 file changed, 61 insertions(+), 122 deletions(-) diff --git a/src/main/drivers/compass/compass_lis2mdl.c b/src/main/drivers/compass/compass_lis2mdl.c index c6c3f27a17..80fb4b87ea 100644 --- a/src/main/drivers/compass/compass_lis2mdl.c +++ b/src/main/drivers/compass/compass_lis2mdl.c @@ -28,114 +28,73 @@ #if defined(USE_MAG_LIS2MDL) +// LIS2MDL, IIS2MDC, LSM303AGR and LSM303AH are firmware and pin-to-pin compatible solutions +// https://www.st.com/resource/en/design_tip/dt0131-digital-magnetometer-and-ecompass-efficient-design-tips--stmicroelectronics.pdf + #include "compass.h" #include "drivers/time.h" #include "common/axis.h" -#define LIS2MDL_MAG_I2C_ADDRESS 0x1E +#define LIS2MDL_MAG_I2C_ADDRESS 0x1E -// Macros to encode/decode multi-bit values -#define LIS2MDL_ENCODE_BITS(val, mask, shift) ((val << shift) & mask) -#define LIS2MDL_DECODE_BITS(val, mask, shift) ((val & mask) >> shift) +// LIS2MDL Registers +#define LIS2MDL_ADDR_CFG_REG_A 0x60 +#define LIS2MDL_ADDR_CFG_REG_B 0x61 +#define LIS2MDL_ADDR_CFG_REG_C 0x62 +#define LIS2MDL_ADDR_STATUS_REG 0x67 +#define LIS2MDL_ADDR_OUTX_L_REG 0x68 +#define LIS2MDL_ADDR_WHO_AM_I 0x4F -#define LIS2MDL_OFFSET_X_REG_L 0x45 -#define LIS2MDL_OFFSET_X_REG_H 0x46 -#define LIS2MDL_OFFSET_Y_REG_L 0x47 -#define LIS2MDL_OFFSET_Y_REG_H 0x48 -#define LIS2MDL_OFFSET_Z_REG_L 0x49 -#define LIS2MDL_OFFSET_Z_REG_H 0x4A +// LIS2MDL Definitions +#define LIS2MDL_WHO_AM_I 0x40 +#define LIS2MDL_STATUS_REG_READY 0x0F +#define CFGA_MD_CONTINUOUS (0 << 0) +#define CFGA_ODR_100 ((1 << 3) | (1 << 2)) +#define CFGA_COMP_TEMP_EN (1 << 7) +#define CFGB_OFF_CANC (1 << 1) +#define CFGC_BDU (1 << 4) -#define LIS2MDL_REG_WHO_AM_I 0x4F -#define LIS2MDL_DEVICE_ID 0x40 - -#define LIS2MDL_CFG_REG_A 0x60 -#define LIS2MDL_CFG_REG_A_COMP_TEMP_EN 0x80 -#define LIS2MDL_CFG_REG_A_REBOOT 0x40 -#define LIS2MDL_CFG_REG_A_SOFT_RST 0x20 -#define LIS2MDL_CFG_REG_A_LP 0x10 -#define LIS2MDL_CFG_REG_A_ODR_MASK 0x0c -#define LIS2MDL_CFG_REG_A_ODR_SHIFT 2 -#define LIS2MDL_CFG_REG_A_ODR_10 0 -#define LIS2MDL_CFG_REG_A_ODR_20 1 -#define LIS2MDL_CFG_REG_A_ODR_50 2 -#define LIS2MDL_CFG_REG_A_ODR_100 3 -#define LIS2MDL_CFG_REG_A_MD_MASK 0x03 -#define LIS2MDL_CFG_REG_A_MD_SHIFT 0 -#define LIS2MDL_CFG_REG_A_MD_CONT 0 -#define LIS2MDL_CFG_REG_A_MD_SINGLE 1 -#define LIS2MDL_CFG_REG_A_MD_IDLE 3 - -#define LIS2MDL_CFG_REG_B 0x61 -#define LIS2MDL_CFG_REG_B_OFF_CANC_ONE_SHOT 0x10 -#define LIS2MDL_CFG_REG_B_INT_ON_DATA_OFF 0x08 -#define LIS2MDL_CFG_REG_B_SET_FREQ 0x04 -#define LIS2MDL_CFG_REG_B_OFF_CANC 0x02 -#define LIS2MDL_CFG_REG_B_LPF 0x01 - -#define LIS2MDL_CFG_REG_C 0x62 -#define LIS2MDL_CFG_REG_C_INT_ON_PIN 0x40 -#define LIS2MDL_CFG_REG_C_I2C_DIS 0x20 -#define LIS2MDL_CFG_REG_C_BDU 0x10 -#define LIS2MDL_CFG_REG_C_BLE 0x08 -#define LIS2MDL_CFG_REG_C_4WSPI 0x04 -#define LIS2MDL_CFG_REG_C_SELF_TEST 0x02 -#define LIS2MDL_CFG_REG_C_DRDY_ON_PIN 0x01 - -#define LIS2MDL_INT_CTRL_REG 0x63 -#define LIS2MDL_INT_CTRL_REG_XIEN 0x80 -#define LIS2MDL_INT_CTRL_REG_YIEN 0x40 -#define LIS2MDL_INT_CTRL_REG_ZIEN 0x20 -#define LIS2MDL_INT_CTRL_REG_IEA 0x04 -#define LIS2MDL_INT_CTRL_REG_IEL 0x02 -#define LIS2MDL_INT_CTRL_REG_IEN 0x01 - -#define LIS2MDL_INT_SOURCE_REG 0x64 -#define LIS2MDL_INT_SOURCE_REG_P_TH_S_X 0x80 -#define LIS2MDL_INT_SOURCE_REG_P_TH_S_Y 0x40 -#define LIS2MDL_INT_SOURCE_REG_P_TH_S_Z 0x20 -#define LIS2MDL_INT_SOURCE_REG_N_TH_S_X 0x10 -#define LIS2MDL_INT_SOURCE_REG_N_TH_S_Y 0x08 -#define LIS2MDL_INT_SOURCE_REG_N_TH_S_Z 0x04 -#define LIS2MDL_INT_SOURCE_REG_MROI 0x02 -#define LIS2MDL_INT_SOURCE_REG_INT 0x01 - -#define LIS2MDL_INT_THS_L_REG 0x65 -#define LIS2MDL_INT_THS_H_REG 0x66 - -#define LIS2MDL_STATUS_REG 0x67 -#define LIS2MDL_STATUS_REG_ZXYOR 0x80 -#define LIS2MDL_STATUS_REG_ZOR 0x40 -#define LIS2MDL_STATUS_REG_YOR 0x20 -#define LIS2MDL_STATUS_REG_XOR 0x10 -#define LIS2MDL_STATUS_REG_ZXYDA 0x08 -#define LIS2MDL_STATUS_REG_ZDA 0x04 -#define LIS2MDL_STATUS_REG_YDA 0x02 -#define LIS2MDL_STATUS_REG_XDA 0x01 - -#define LIS2MDL_OUTX_L_REG 0x68 -#define LIS2MDL_OUTX_H_REG 0x69 -#define LIS2MDL_OUTY_L_REG 0x6A -#define LIS2MDL_OUTY_H_REG 0x6B -#define LIS2MDL_OUTZ_L_REG 0x6C -#define LIS2MDL_OUTZ_H_REG 0x6D - -#define LIS2MDL_TEMP_OUT_L_REG 0x6E -#define LIS2MDL_TEMP_OUT_H_REG 0x6F - -static bool lis2mdlRead(magDev_t * mag, int16_t *magData) +static bool lis2mdlInit(magDev_t *mag) { - static uint8_t buf[6]; - static bool pendingRead = true; + bool ack = true; + extDevice_t *dev = &mag->dev; + + busDeviceRegister(dev); + + ack = ack && busWriteRegister(dev, LIS2MDL_ADDR_CFG_REG_A, CFGA_MD_CONTINUOUS | CFGA_ODR_100 | CFGA_COMP_TEMP_EN); + ack = ack && busWriteRegister(dev, LIS2MDL_ADDR_CFG_REG_B, CFGB_OFF_CANC); + ack = ack && busWriteRegister(dev, LIS2MDL_ADDR_CFG_REG_C, CFGC_BDU); + + if (!ack) { + return false; + } + + mag->magOdrHz = 100; + return true; +} + +static bool lis2mdlRead(magDev_t *mag, int16_t *magData) +{ + uint8_t status = 0; + uint8_t buf[6]; extDevice_t *dev = &mag->dev; - if (pendingRead) { - if (busReadRegisterBufferStart(dev, LIS2MDL_OUTX_L_REG, buf, sizeof(buf))) { - pendingRead = false; - } + if (!busReadRegisterBuffer(dev, LIS2MDL_ADDR_STATUS_REG, &status, sizeof(status))) { return false; } + if (!(status & LIS2MDL_STATUS_REG_READY)) { + return false; + } + + if (!busReadRegisterBuffer(dev, LIS2MDL_ADDR_OUTX_L_REG, (uint8_t *)&buf, sizeof(buf))) { + return false; + } + + // Sensitivity is +/- 50,000 milligauss, 16bit + // e.g. gauss = val * (100.f / 65.535f) + int16_t x = (int16_t)(buf[1] << 8 | buf[0]); int16_t y = (int16_t)(buf[3] << 8 | buf[2]); int16_t z = (int16_t)(buf[5] << 8 | buf[4]); @@ -146,46 +105,26 @@ static bool lis2mdlRead(magDev_t * mag, int16_t *magData) magData[Y] = y; magData[Z] = z; - pendingRead = true; - return true; } -static bool lis2mdlInit(magDev_t *mag) +bool lis2mdlDetect(magDev_t *mag) { extDevice_t *dev = &mag->dev; - busDeviceRegister(dev); - - busWriteRegister(dev, LIS2MDL_CFG_REG_A, - LIS2MDL_CFG_REG_A_COMP_TEMP_EN | - LIS2MDL_ENCODE_BITS(LIS2MDL_CFG_REG_A_ODR_100, LIS2MDL_CFG_REG_A_ODR_MASK, LIS2MDL_CFG_REG_A_ODR_SHIFT) | - LIS2MDL_ENCODE_BITS(LIS2MDL_CFG_REG_A_MD_CONT, LIS2MDL_CFG_REG_A_MD_MASK, LIS2MDL_CFG_REG_A_MD_SHIFT)); - - delay(100); - - return true; -} - -bool lis2mdlDetect(magDev_t * mag) -{ - extDevice_t *dev = &mag->dev; - - uint8_t sig = 0; - if (dev->bus->busType == BUS_TYPE_I2C && dev->busType_u.i2c.address == 0) { dev->busType_u.i2c.address = LIS2MDL_MAG_I2C_ADDRESS; } - bool ack = busReadRegisterBuffer(&mag->dev, LIS2MDL_REG_WHO_AM_I, &sig, 1); + uint8_t whoami; + bool ack = busReadRegisterBuffer(dev, LIS2MDL_ADDR_WHO_AM_I, &whoami, sizeof(whoami)); - if (!ack || sig != LIS2MDL_DEVICE_ID) { - return false; + if (ack && whoami == LIS2MDL_WHO_AM_I) { + mag->init = lis2mdlInit; + mag->read = lis2mdlRead; + return true; } - mag->init = lis2mdlInit; - mag->read = lis2mdlRead; - - return true; + return false; } #endif From 98283ff279c8e36c9f83474b97bbd622b6e39e83 Mon Sep 17 00:00:00 2001 From: Steve Evans Date: Sat, 18 Jan 2025 02:08:47 +0000 Subject: [PATCH 062/244] Tidy up MSP protocol header (#14166) --- src/main/msp/msp_protocol.h | 430 +++++++++++++++--------------------- 1 file changed, 178 insertions(+), 252 deletions(-) diff --git a/src/main/msp/msp_protocol.h b/src/main/msp/msp_protocol.h index 1114ebdf34..da4027a3cf 100644 --- a/src/main/msp/msp_protocol.h +++ b/src/main/msp/msp_protocol.h @@ -55,15 +55,11 @@ #pragma once -/* Protocol numbers used both by the wire format, config system, and - field setters. -*/ - +// Protocol numbers used both by the wire format, config system, and field setters. #define MSP_PROTOCOL_VERSION 0 -#define API_VERSION_MAJOR 1 // increment when major changes are made -#define API_VERSION_MINOR 47 // increment after a release, to set the version for all changes to go into the following release (if no changes to MSP are made between the releases, this can be reverted before the release) - +#define API_VERSION_MAJOR 1 +#define API_VERSION_MINOR 47 #define API_VERSION_LENGTH 2 #define MULTIWII_IDENTIFIER "MWII"; @@ -95,258 +91,188 @@ #define CAP_NAVCAP ((uint32_t)1 << 4) #define CAP_EXTAUX ((uint32_t)1 << 5) -#define MSP_API_VERSION 1 //out message -#define MSP_FC_VARIANT 2 //out message -#define MSP_FC_VERSION 3 //out message -#define MSP_BOARD_INFO 4 //out message -#define MSP_BUILD_INFO 5 //out message +#define MSP_API_VERSION 1 // out message: Get API version +#define MSP_FC_VARIANT 2 // out message: Get flight controller variant +#define MSP_FC_VERSION 3 // out message: Get flight controller version +#define MSP_BOARD_INFO 4 // out message: Get board information +#define MSP_BUILD_INFO 5 // out message: Get build information -#define MSP_NAME 10 //out message Returns user set board name - betaflight -#define MSP_SET_NAME 11 //in message Sets board name - betaflight +#define MSP_NAME 10 // out message: Returns user set board name - betaflight +#define MSP_SET_NAME 11 // in message: Sets board name - betaflight -// -// MSP commands for Cleanflight original features -// -#define MSP_BATTERY_CONFIG 32 -#define MSP_SET_BATTERY_CONFIG 33 +// Cleanflight original features (32-62) +#define MSP_BATTERY_CONFIG 32 // out message: Get battery configuration +#define MSP_SET_BATTERY_CONFIG 33 // in message: Set battery configuration +#define MSP_MODE_RANGES 34 // out message: Returns all mode ranges +#define MSP_SET_MODE_RANGE 35 // in message: Sets a single mode range +#define MSP_FEATURE_CONFIG 36 // out message: Get feature configuration +#define MSP_SET_FEATURE_CONFIG 37 // in message: Set feature configuration +#define MSP_BOARD_ALIGNMENT_CONFIG 38 // out message: Get board alignment configuration +#define MSP_SET_BOARD_ALIGNMENT_CONFIG 39 // in message: Set board alignment configuration +#define MSP_CURRENT_METER_CONFIG 40 // out message: Get current meter configuration +#define MSP_SET_CURRENT_METER_CONFIG 41 // in message: Set current meter configuration +#define MSP_MIXER_CONFIG 42 // out message: Get mixer configuration +#define MSP_SET_MIXER_CONFIG 43 // in message: Set mixer configuration +#define MSP_RX_CONFIG 44 // out message: Get RX configuration +#define MSP_SET_RX_CONFIG 45 // in message: Set RX configuration +#define MSP_LED_COLORS 46 // out message: Get LED colors +#define MSP_SET_LED_COLORS 47 // in message: Set LED colors +#define MSP_LED_STRIP_CONFIG 48 // out message: Get LED strip configuration +#define MSP_SET_LED_STRIP_CONFIG 49 // in message: Set LED strip configuration +#define MSP_RSSI_CONFIG 50 // out message: Get RSSI configuration +#define MSP_SET_RSSI_CONFIG 51 // in message: Set RSSI configuration +#define MSP_ADJUSTMENT_RANGES 52 // out message: Get adjustment ranges +#define MSP_SET_ADJUSTMENT_RANGE 53 // in message: Set adjustment range +#define MSP_CF_SERIAL_CONFIG 54 // out message: Get Cleanflight serial configuration +#define MSP_SET_CF_SERIAL_CONFIG 55 // in message: Set Cleanflight serial configuration +#define MSP_VOLTAGE_METER_CONFIG 56 // out message: Get voltage meter configuration +#define MSP_SET_VOLTAGE_METER_CONFIG 57 // in message: Set voltage meter configuration +#define MSP_SONAR_ALTITUDE 58 // out message: Get sonar altitude [cm] +#define MSP_PID_CONTROLLER 59 // out message: Get PID controller +#define MSP_SET_PID_CONTROLLER 60 // in message: Set PID controller +#define MSP_ARMING_CONFIG 61 // out message: Get arming configuration +#define MSP_SET_ARMING_CONFIG 62 // in message: Set arming configuration -#define MSP_MODE_RANGES 34 //out message Returns all mode ranges -#define MSP_SET_MODE_RANGE 35 //in message Sets a single mode range +// Baseflight MSP commands (64-89) +#define MSP_RX_MAP 64 // out message: Get RX map (also returns number of channels total) +#define MSP_SET_RX_MAP 65 // in message: Set RX map, numchannels to set comes from MSP_RX_MAP +#define MSP_REBOOT 68 // in message: Reboot settings +#define MSP_DATAFLASH_SUMMARY 70 // out message: Get description of dataflash chip +#define MSP_DATAFLASH_READ 71 // out message: Get content of dataflash chip +#define MSP_DATAFLASH_ERASE 72 // in message: Erase dataflash chip +#define MSP_FAILSAFE_CONFIG 75 // out message: Get failsafe settings +#define MSP_SET_FAILSAFE_CONFIG 76 // in message: Set failsafe settings +#define MSP_RXFAIL_CONFIG 77 // out message: Get RX failsafe settings +#define MSP_SET_RXFAIL_CONFIG 78 // in message: Set RX failsafe settings +#define MSP_SDCARD_SUMMARY 79 // out message: Get SD card state +#define MSP_BLACKBOX_CONFIG 80 // out message: Get blackbox settings +#define MSP_SET_BLACKBOX_CONFIG 81 // in message: Set blackbox settings +#define MSP_TRANSPONDER_CONFIG 82 // out message: Get transponder settings +#define MSP_SET_TRANSPONDER_CONFIG 83 // in message: Set transponder settings +#define MSP_OSD_CONFIG 84 // out message: Get OSD settings +#define MSP_SET_OSD_CONFIG 85 // in message: Set OSD settings +#define MSP_OSD_CHAR_READ 86 // out message: Get OSD characters +#define MSP_OSD_CHAR_WRITE 87 // in message: Set OSD characters +#define MSP_VTX_CONFIG 88 // out message: Get VTX settings +#define MSP_SET_VTX_CONFIG 89 // in message: Set VTX settings -#define MSP_FEATURE_CONFIG 36 -#define MSP_SET_FEATURE_CONFIG 37 +// Betaflight Additional Commands (90-99) +#define MSP_ADVANCED_CONFIG 90 // out message: Get advanced configuration +#define MSP_SET_ADVANCED_CONFIG 91 // in message: Set advanced configuration +#define MSP_FILTER_CONFIG 92 // out message: Get filter configuration +#define MSP_SET_FILTER_CONFIG 93 // in message: Set filter configuration +#define MSP_PID_ADVANCED 94 // out message: Get advanced PID settings +#define MSP_SET_PID_ADVANCED 95 // in message: Set advanced PID settings +#define MSP_SENSOR_CONFIG 96 // out message: Get sensor configuration +#define MSP_SET_SENSOR_CONFIG 97 // in message: Set sensor configuration +#define MSP_CAMERA_CONTROL 98 // in/out message: Camera control +#define MSP_SET_ARMING_DISABLED 99 // in message: Enable/disable arming -#define MSP_BOARD_ALIGNMENT_CONFIG 38 -#define MSP_SET_BOARD_ALIGNMENT_CONFIG 39 +// Multiwii original MSP commands (101-139) +#define MSP_STATUS 101 // out message: Cycletime & errors_count & sensor present & box activation & current setting number +#define MSP_RAW_IMU 102 // out message: 9 DOF +#define MSP_SERVO 103 // out message: Servos +#define MSP_MOTOR 104 // out message: Motors +#define MSP_RC 105 // out message: RC channels and more +#define MSP_RAW_GPS 106 // out message: Fix, numsat, lat, lon, alt, speed, ground course +#define MSP_COMP_GPS 107 // out message: Distance home, direction home +#define MSP_ATTITUDE 108 // out message: 2 angles 1 heading +#define MSP_ALTITUDE 109 // out message: Altitude, variometer +#define MSP_ANALOG 110 // out message: Vbat, powermetersum, rssi if available on RX +#define MSP_RC_TUNING 111 // out message: RC rate, rc expo, rollpitch rate, yaw rate, dyn throttle PID +#define MSP_PID 112 // out message: P I D coeff (9 are used currently) +#define MSP_BOXNAMES 116 // out message: The aux switch names +#define MSP_PIDNAMES 117 // out message: The PID names +#define MSP_WP 118 // out message: Get a WP, WP# is in the payload, returns (WP#, lat, lon, alt, flags) WP#0-home, WP#16-poshold +#define MSP_BOXIDS 119 // out message: Get the permanent IDs associated to BOXes +#define MSP_SERVO_CONFIGURATIONS 120 // out message: All servo configurations +#define MSP_NAV_STATUS 121 // out message: Returns navigation status +#define MSP_NAV_CONFIG 122 // out message: Returns navigation parameters +#define MSP_MOTOR_3D_CONFIG 124 // out message: Settings needed for reversible ESCs +#define MSP_RC_DEADBAND 125 // out message: Deadbands for yaw alt pitch roll +#define MSP_SENSOR_ALIGNMENT 126 // out message: Orientation of acc,gyro,mag +#define MSP_LED_STRIP_MODECOLOR 127 // out message: Get LED strip mode_color settings +#define MSP_VOLTAGE_METERS 128 // out message: Voltage (per meter) +#define MSP_CURRENT_METERS 129 // out message: Amperage (per meter) +#define MSP_BATTERY_STATE 130 // out message: Connected/Disconnected, Voltage, Current Used +#define MSP_MOTOR_CONFIG 131 // out message: Motor configuration (min/max throttle, etc) +#define MSP_GPS_CONFIG 132 // out message: GPS configuration +#define MSP_COMPASS_CONFIG 133 // out message: Compass configuration +#define MSP_ESC_SENSOR_DATA 134 // out message: Extra ESC data from 32-Bit ESCs (Temperature, RPM) +#define MSP_GPS_RESCUE 135 // out message: GPS Rescue angle, returnAltitude, descentDistance, groundSpeed, sanityChecks and minSats +#define MSP_GPS_RESCUE_PIDS 136 // out message: GPS Rescue throttleP and velocity PIDS + yaw P +#define MSP_VTXTABLE_BAND 137 // out message: VTX table band/channel data +#define MSP_VTXTABLE_POWERLEVEL 138 // out message: VTX table powerLevel data +#define MSP_MOTOR_TELEMETRY 139 // out message: Per-motor telemetry data (RPM, packet stats, ESC temp, etc.) -#define MSP_CURRENT_METER_CONFIG 40 -#define MSP_SET_CURRENT_METER_CONFIG 41 +// Simplified tuning commands (140-145) +#define MSP_SIMPLIFIED_TUNING 140 // out message: Get simplified tuning values and enabled state +#define MSP_SET_SIMPLIFIED_TUNING 141 // in message: Set simplified tuning positions and apply calculated tuning +#define MSP_CALCULATE_SIMPLIFIED_PID 142 // out message: Calculate PID values based on sliders without saving +#define MSP_CALCULATE_SIMPLIFIED_GYRO 143 // out message: Calculate gyro filter values based on sliders without saving +#define MSP_CALCULATE_SIMPLIFIED_DTERM 144 // out message: Calculate D term filter values based on sliders without saving +#define MSP_VALIDATE_SIMPLIFIED_TUNING 145 // out message: Returns array of true/false showing which simplified tuning groups match values -#define MSP_MIXER_CONFIG 42 -#define MSP_SET_MIXER_CONFIG 43 +// Additional non-MultiWii commands (150-166) +#define MSP_STATUS_EX 150 // out message: Cycletime, errors_count, CPU load, sensor present etc +#define MSP_UID 160 // out message: Unique device ID +#define MSP_GPSSVINFO 164 // out message: Get Signal Strength (only U-Blox) +#define MSP_GPSSTATISTICS 166 // out message: Get GPS debugging data -#define MSP_RX_CONFIG 44 -#define MSP_SET_RX_CONFIG 45 +// OSD specific commands (180-189) +#define MSP_OSD_VIDEO_CONFIG 180 // out message: Get OSD video settings +#define MSP_SET_OSD_VIDEO_CONFIG 181 // in message: Set OSD video settings +#define MSP_DISPLAYPORT 182 // out message: External OSD displayport mode +#define MSP_COPY_PROFILE 183 // in message: Copy settings between profiles +#define MSP_BEEPER_CONFIG 184 // out message: Get beeper configuration +#define MSP_SET_BEEPER_CONFIG 185 // in message: Set beeper configuration +#define MSP_SET_TX_INFO 186 // in message: Set runtime information from TX lua scripts +#define MSP_TX_INFO 187 // out message: Get runtime information for TX lua scripts +#define MSP_SET_OSD_CANVAS 188 // in message: Set OSD canvas size COLSxROWS +#define MSP_OSD_CANVAS 189 // out message: Get OSD canvas size COLSxROWS -#define MSP_LED_COLORS 46 -#define MSP_SET_LED_COLORS 47 +// Set commands (200-229) +#define MSP_SET_RAW_RC 200 // in message: 8 rc chan +#define MSP_SET_RAW_GPS 201 // in message: Fix, numsat, lat, lon, alt, speed +#define MSP_SET_PID 202 // in message: P I D coeff (9 are used currently) +#define MSP_SET_RC_TUNING 204 // in message: RC rate, rc expo, rollpitch rate, yaw rate, dyn throttle PID, yaw expo +#define MSP_ACC_CALIBRATION 205 // in message: No param - calibrate accelerometer +#define MSP_MAG_CALIBRATION 206 // in message: No param - calibrate magnetometer +#define MSP_RESET_CONF 208 // in message: No param - reset settings +#define MSP_SET_WP 209 // in message: Sets a given WP (WP#,lat, lon, alt, flags) +#define MSP_SELECT_SETTING 210 // in message: Select setting number (0-2) +#define MSP_SET_HEADING 211 // in message: Define a new heading hold direction +#define MSP_SET_SERVO_CONFIGURATION 212 // in message: Servo settings +#define MSP_SET_MOTOR 214 // in message: PropBalance function +#define MSP_SET_NAV_CONFIG 215 // in message: Sets nav config parameters +#define MSP_SET_MOTOR_3D_CONFIG 217 // in message: Settings needed for reversible ESCs +#define MSP_SET_RC_DEADBAND 218 // in message: Deadbands for yaw alt pitch roll +#define MSP_SET_RESET_CURR_PID 219 // in message: Reset current PID profile to defaults +#define MSP_SET_SENSOR_ALIGNMENT 220 // in message: Set the orientation of acc,gyro,mag +#define MSP_SET_LED_STRIP_MODECOLOR 221 // in message: Set LED strip mode_color settings +#define MSP_SET_MOTOR_CONFIG 222 // in message: Motor configuration (min/max throttle, etc) +#define MSP_SET_GPS_CONFIG 223 // in message: GPS configuration +#define MSP_SET_COMPASS_CONFIG 224 // in message: Compass configuration +#define MSP_SET_GPS_RESCUE 225 // in message: Set GPS Rescue parameters +#define MSP_SET_GPS_RESCUE_PIDS 226 // in message: Set GPS Rescue PID values +#define MSP_SET_VTXTABLE_BAND 227 // in message: Set vtxTable band/channel data +#define MSP_SET_VTXTABLE_POWERLEVEL 228 // in message: Set vtxTable powerLevel data -#define MSP_LED_STRIP_CONFIG 48 -#define MSP_SET_LED_STRIP_CONFIG 49 - -#define MSP_RSSI_CONFIG 50 -#define MSP_SET_RSSI_CONFIG 51 - -#define MSP_ADJUSTMENT_RANGES 52 -#define MSP_SET_ADJUSTMENT_RANGE 53 - -// private - only to be used by the configurator, the commands are likely to change -#define MSP_CF_SERIAL_CONFIG 54 -#define MSP_SET_CF_SERIAL_CONFIG 55 - -#define MSP_VOLTAGE_METER_CONFIG 56 -#define MSP_SET_VOLTAGE_METER_CONFIG 57 - -#define MSP_SONAR_ALTITUDE 58 //out message get sonar altitude [cm] - -#define MSP_PID_CONTROLLER 59 -#define MSP_SET_PID_CONTROLLER 60 - -#define MSP_ARMING_CONFIG 61 -#define MSP_SET_ARMING_CONFIG 62 - -// -// Baseflight MSP commands (if enabled they exist in Cleanflight) -// -#define MSP_RX_MAP 64 //out message get channel map (also returns number of channels total) -#define MSP_SET_RX_MAP 65 //in message set rx map, numchannels to set comes from MSP_RX_MAP - -// DEPRECATED - DO NOT USE "MSP_BF_CONFIG" and MSP_SET_BF_CONFIG. In Cleanflight, isolated commands already exist and should be used instead. -// DEPRECATED - #define MSP_BF_CONFIG 66 //out message baseflight-specific settings that aren't covered elsewhere -// DEPRECATED - #define MSP_SET_BF_CONFIG 67 //in message baseflight-specific settings save - -#define MSP_REBOOT 68 //in message reboot settings - -// Use MSP_BUILD_INFO instead -// DEPRECATED - #define MSP_BF_BUILD_INFO 69 //out message build date as well as some space for future expansion - -#define MSP_DATAFLASH_SUMMARY 70 //out message - get description of dataflash chip -#define MSP_DATAFLASH_READ 71 //out message - get content of dataflash chip -#define MSP_DATAFLASH_ERASE 72 //in message - erase dataflash chip - -// No-longer needed -// DEPRECATED - #define MSP_LOOP_TIME 73 //out message Returns FC cycle time i.e looptime parameter // DEPRECATED -// DEPRECATED - #define MSP_SET_LOOP_TIME 74 //in message Sets FC cycle time i.e looptime parameter // DEPRECATED - -#define MSP_FAILSAFE_CONFIG 75 //out message Returns FC Fail-Safe settings -#define MSP_SET_FAILSAFE_CONFIG 76 //in message Sets FC Fail-Safe settings - -#define MSP_RXFAIL_CONFIG 77 //out message Returns RXFAIL settings -#define MSP_SET_RXFAIL_CONFIG 78 //in message Sets RXFAIL settings - -#define MSP_SDCARD_SUMMARY 79 //out message Get the state of the SD card - -#define MSP_BLACKBOX_CONFIG 80 //out message Get blackbox settings -#define MSP_SET_BLACKBOX_CONFIG 81 //in message Set blackbox settings - -#define MSP_TRANSPONDER_CONFIG 82 //out message Get transponder settings -#define MSP_SET_TRANSPONDER_CONFIG 83 //in message Set transponder settings - -#define MSP_OSD_CONFIG 84 //out message Get osd settings - betaflight -#define MSP_SET_OSD_CONFIG 85 //in message Set osd settings - betaflight - -#define MSP_OSD_CHAR_READ 86 //out message Get osd settings - betaflight -#define MSP_OSD_CHAR_WRITE 87 //in message Set osd settings - betaflight - -#define MSP_VTX_CONFIG 88 //out message Get vtx settings - betaflight -#define MSP_SET_VTX_CONFIG 89 //in message Set vtx settings - betaflight - -// Betaflight Additional Commands -#define MSP_ADVANCED_CONFIG 90 -#define MSP_SET_ADVANCED_CONFIG 91 - -#define MSP_FILTER_CONFIG 92 -#define MSP_SET_FILTER_CONFIG 93 - -#define MSP_PID_ADVANCED 94 -#define MSP_SET_PID_ADVANCED 95 - -#define MSP_SENSOR_CONFIG 96 -#define MSP_SET_SENSOR_CONFIG 97 - -#define MSP_CAMERA_CONTROL 98 - -#define MSP_SET_ARMING_DISABLED 99 - -// -// OSD specific -// -#define MSP_OSD_VIDEO_CONFIG 180 -#define MSP_SET_OSD_VIDEO_CONFIG 181 - -// External OSD displayport mode messages -#define MSP_DISPLAYPORT 182 - -#define MSP_COPY_PROFILE 183 - -#define MSP_BEEPER_CONFIG 184 -#define MSP_SET_BEEPER_CONFIG 185 - -#define MSP_SET_TX_INFO 186 // in message Used to send runtime information from TX lua scripts to the firmware -#define MSP_TX_INFO 187 // out message Used by TX lua scripts to read information from the firmware - -#define MSP_SET_OSD_CANVAS 188 // in message Set osd canvas size COLSxROWS -#define MSP_OSD_CANVAS 189 // out message Get osd canvas size COLSxROWS - -// -// Multwii original MSP commands -// - -// See MSP_API_VERSION and MSP_MIXER_CONFIG -//DEPRECATED - #define MSP_IDENT 100 //out message mixerMode + multiwii version + protocol version + capability variable - -#define MSP_STATUS 101 //out message cycletime & errors_count & sensor present & box activation & current setting number -#define MSP_RAW_IMU 102 //out message 9 DOF -#define MSP_SERVO 103 //out message servos -#define MSP_MOTOR 104 //out message motors -#define MSP_RC 105 //out message rc channels and more -#define MSP_RAW_GPS 106 //out message fix, numsat, lat, lon, alt, speed, ground course -#define MSP_COMP_GPS 107 //out message distance home, direction home -#define MSP_ATTITUDE 108 //out message 2 angles 1 heading -#define MSP_ALTITUDE 109 //out message altitude, variometer -#define MSP_ANALOG 110 //out message vbat, powermetersum, rssi if available on RX -#define MSP_RC_TUNING 111 //out message rc rate, rc expo, rollpitch rate, yaw rate, dyn throttle PID -#define MSP_PID 112 //out message P I D coeff (9 are used currently) -// Legacy Multiicommand that was never used. -//DEPRECATED - #define MSP_BOX 113 //out message BOX setup (number is dependant of your setup) -// Legacy command that was under constant change due to the naming vagueness, avoid at all costs - use more specific commands instead. -//DEPRECATED - #define MSP_MISC 114 //out message powermeter trig -// Legacy Multiicommand that was never used and always wrong -//DEPRECATED - #define MSP_MOTOR_PINS 115 //out message which pins are in use for motors & servos, for GUI -#define MSP_BOXNAMES 116 //out message the aux switch names -#define MSP_PIDNAMES 117 //out message the PID names -#define MSP_WP 118 //out message get a WP, WP# is in the payload, returns (WP#, lat, lon, alt, flags) WP#0-home, WP#16-poshold -#define MSP_BOXIDS 119 //out message get the permanent IDs associated to BOXes -#define MSP_SERVO_CONFIGURATIONS 120 //out message All servo configurations. -#define MSP_NAV_STATUS 121 //out message Returns navigation status -#define MSP_NAV_CONFIG 122 //out message Returns navigation parameters -#define MSP_MOTOR_3D_CONFIG 124 //out message Settings needed for reversible ESCs -#define MSP_RC_DEADBAND 125 //out message deadbands for yaw alt pitch roll -#define MSP_SENSOR_ALIGNMENT 126 //out message orientation of acc,gyro,mag -#define MSP_LED_STRIP_MODECOLOR 127 //out message Get LED strip mode_color settings -#define MSP_VOLTAGE_METERS 128 //out message Voltage (per meter) -#define MSP_CURRENT_METERS 129 //out message Amperage (per meter) -#define MSP_BATTERY_STATE 130 //out message Connected/Disconnected, Voltage, Current Used -#define MSP_MOTOR_CONFIG 131 //out message Motor configuration (min/max throttle, etc) -#define MSP_GPS_CONFIG 132 //out message GPS configuration -#define MSP_COMPASS_CONFIG 133 //out message Compass configuration -#define MSP_ESC_SENSOR_DATA 134 //out message Extra ESC data from 32-Bit ESCs (Temperature, RPM) -#define MSP_GPS_RESCUE 135 //out message GPS Rescue angle, returnAltitude, descentDistance, groundSpeed, sanityChecks and minSats -#define MSP_GPS_RESCUE_PIDS 136 //out message GPS Rescue throttleP and velocity PIDS + yaw P -#define MSP_VTXTABLE_BAND 137 //out message vtxTable band/channel data -#define MSP_VTXTABLE_POWERLEVEL 138 //out message vtxTable powerLevel data -#define MSP_MOTOR_TELEMETRY 139 //out message Per-motor telemetry data (RPM, packet stats, ESC temp, etc.) - -#define MSP_SIMPLIFIED_TUNING 140 //out message Simplified tuning values and enabled state -#define MSP_SET_SIMPLIFIED_TUNING 141 //in message Set simplified tuning positions and apply the calculated tuning -#define MSP_CALCULATE_SIMPLIFIED_PID 142 //out message Requests calculations of PID values based on sliders. Sends the calculated values back. But don't save anything to the firmware -#define MSP_CALCULATE_SIMPLIFIED_GYRO 143 //out message Requests calculations of gyro filter values based on sliders. Sends the calculated values back. But don't save anything to the firmware -#define MSP_CALCULATE_SIMPLIFIED_DTERM 144 //out message Requests calculations of gyro filter values based on sliders. Sends the calculated values back. But don't save anything to the firmware -#define MSP_VALIDATE_SIMPLIFIED_TUNING 145 //out message Returns an array of true/false showing which simpligfied tuning groups are matching with value and which are not - -#define MSP_SET_RAW_RC 200 //in message 8 rc chan -#define MSP_SET_RAW_GPS 201 //in message fix, numsat, lat, lon, alt, speed -#define MSP_SET_PID 202 //in message P I D coeff (9 are used currently) -// Legacy multiiwii command that was never used. -//DEPRECATED - #define MSP_SET_BOX 203 //in message BOX setup (number is dependant of your setup) -#define MSP_SET_RC_TUNING 204 //in message rc rate, rc expo, rollpitch rate, yaw rate, dyn throttle PID, yaw expo -#define MSP_ACC_CALIBRATION 205 //in message no param -#define MSP_MAG_CALIBRATION 206 //in message no param -// Legacy command that was under constant change due to the naming vagueness, avoid at all costs - use more specific commands instead. -//DEPRECATED - #define MSP_SET_MISC 207 //in message powermeter trig + 8 free for future use -#define MSP_RESET_CONF 208 //in message no param -#define MSP_SET_WP 209 //in message sets a given WP (WP#,lat, lon, alt, flags) -#define MSP_SELECT_SETTING 210 //in message Select Setting Number (0-2) -#define MSP_SET_HEADING 211 //in message define a new heading hold direction -#define MSP_SET_SERVO_CONFIGURATION 212 //in message Servo settings -#define MSP_SET_MOTOR 214 //in message PropBalance function -#define MSP_SET_NAV_CONFIG 215 //in message Sets nav config parameters - write to the eeprom -#define MSP_SET_MOTOR_3D_CONFIG 217 //in message Settings needed for reversible ESCs -#define MSP_SET_RC_DEADBAND 218 //in message deadbands for yaw alt pitch roll -#define MSP_SET_RESET_CURR_PID 219 //in message resetting the current pid profile to defaults -#define MSP_SET_SENSOR_ALIGNMENT 220 //in message set the orientation of the acc,gyro,mag -#define MSP_SET_LED_STRIP_MODECOLOR 221 //in message Set LED strip mode_color settings -#define MSP_SET_MOTOR_CONFIG 222 //out message Motor configuration (min/max throttle, etc) -#define MSP_SET_GPS_CONFIG 223 //out message GPS configuration -#define MSP_SET_COMPASS_CONFIG 224 //out message Compass configuration -#define MSP_SET_GPS_RESCUE 225 //in message GPS Rescue angle, returnAltitude, descentDistance, groundSpeed and sanityChecks -#define MSP_SET_GPS_RESCUE_PIDS 226 //in message GPS Rescue throttleP and velocity PIDS + yaw P -#define MSP_SET_VTXTABLE_BAND 227 //in message set vtxTable band/channel data (one band at a time) -#define MSP_SET_VTXTABLE_POWERLEVEL 228 //in message set vtxTable powerLevel data (one powerLevel at a time) - -// #define MSP_BIND 240 //in message no param -// #define MSP_ALARMS 242 - -#define MSP_EEPROM_WRITE 250 //in message no param -#define MSP_RESERVE_1 251 //reserved for system usage -#define MSP_RESERVE_2 252 //reserved for system usage -#define MSP_DEBUGMSG 253 //out message debug string buffer -#define MSP_DEBUG 254 //out message debug1,debug2,debug3,debug4 -#define MSP_V2_FRAME 255 //MSPv2 payload indicator - -// Additional commands that are not compatible with MultiWii -#define MSP_STATUS_EX 150 //out message cycletime, errors_count, CPU load, CPU temperature, sensor present etc -#define MSP_UID 160 //out message Unique device ID -#define MSP_GPSSVINFO 164 //out message get Signal Strength (only U-Blox) -#define MSP_GPSSTATISTICS 166 //out message get GPS debugging data -#define MSP_MULTIPLE_MSP 230 //out message request multiple MSPs in one request - limit is the TX buffer; returns each MSP in the order they were requested starting with length of MSP; MSPs with input arguments are not supported -#define MSP_MODE_RANGES_EXTRA 238 //out message Reads the extra mode range data -#define MSP_ACC_TRIM 240 //out message get acc angle trim values -#define MSP_SET_ACC_TRIM 239 //in message set acc angle trim values -#define MSP_SERVO_MIX_RULES 241 //out message Returns servo mixer configuration -#define MSP_SET_SERVO_MIX_RULE 242 //in message Sets servo mixer configuration -#define MSP_SET_PASSTHROUGH 245 //in message Sets up passthrough to different peripherals (4way interface, uart, etc...) -#define MSP_SET_RTC 246 //in message Sets the RTC clock -#define MSP_RTC 247 //out message Gets the RTC clock -#define MSP_SET_BOARD_INFO 248 //in message Sets the board information for this board -#define MSP_SET_SIGNATURE 249 //in message Sets the signature of the board and serial number +// Multiple MSP and special commands (230-255) +#define MSP_MULTIPLE_MSP 230 // out message: Request multiple MSPs in one request +#define MSP_MODE_RANGES_EXTRA 238 // out message: Extra mode range data +#define MSP_SET_ACC_TRIM 239 // in message: Set acc angle trim values +#define MSP_ACC_TRIM 240 // out message: Get acc angle trim values +#define MSP_SERVO_MIX_RULES 241 // out message: Get servo mixer configuration +#define MSP_SET_SERVO_MIX_RULE 242 // in message: Set servo mixer configuration +#define MSP_SET_PASSTHROUGH 245 // in message: Set passthrough to peripherals +#define MSP_SET_RTC 246 // in message: Set the RTC clock +#define MSP_RTC 247 // out message: Get the RTC clock +#define MSP_SET_BOARD_INFO 248 // in message: Set the board information +#define MSP_SET_SIGNATURE 249 // in message: Set the signature of the board and serial number +#define MSP_EEPROM_WRITE 250 // in message: Write settings to EEPROM +#define MSP_RESERVE_1 251 // reserved for system usage +#define MSP_RESERVE_2 252 // reserved for system usage +#define MSP_DEBUGMSG 253 // out message: debug string buffer +#define MSP_DEBUG 254 // out message: debug1,debug2,debug3,debug4 +#define MSP_V2_FRAME 255 // MSPv2 payload indicator From b2bafa1a8cbae59232966ea90ca75bad6aaa06da Mon Sep 17 00:00:00 2001 From: Jay Blackman Date: Sun, 19 Jan 2025 09:22:37 +1100 Subject: [PATCH 063/244] FIX: USE_STDPERIPH_DRIVER incorrectly defined for all targets (legacy) (#14181) --- Makefile | 1 - src/platform/STM32/mk/STM32F4.mk | 12 ++++++++---- 2 files changed, 8 insertions(+), 5 deletions(-) diff --git a/Makefile b/Makefile index 46c822012e..8af2116909 100644 --- a/Makefile +++ b/Makefile @@ -299,7 +299,6 @@ CFLAGS += $(ARCH_FLAGS) \ $(TEMPORARY_FLAGS) \ $(DEVICE_FLAGS) \ -D_GNU_SOURCE \ - -DUSE_STDPERIPH_DRIVER \ -D$(TARGET) \ $(TARGET_FLAGS) \ -D'__FORKNAME__="$(FORKNAME)"' \ diff --git a/src/platform/STM32/mk/STM32F4.mk b/src/platform/STM32/mk/STM32F4.mk index 28bf0fecb6..9d1f404557 100644 --- a/src/platform/STM32/mk/STM32F4.mk +++ b/src/platform/STM32/mk/STM32F4.mk @@ -42,6 +42,8 @@ STDPERIPH_SRC = \ VPATH := $(VPATH):$(STDPERIPH_DIR)/src endif +DEVICE_FLAGS = -DSTM32F4 + ifneq ($(TARGET_MCU),$(filter $(TARGET_MCU),STM32F411xE STM32F446xx)) STDPERIPH_SRC += stm32f4xx_fsmc.c endif @@ -141,25 +143,27 @@ INCLUDE_DIRS := \ $(CMSIS_DIR)/Core/Include \ $(LIB_MAIN_DIR)/STM32F4/Drivers/CMSIS/Device/ST/STM32F4xx \ $(TARGET_PLATFORM_DIR)/vcpf4 + +DEVICE_FLAGS += -DUSE_STDPERIPH_DRIVER endif #Flags ARCH_FLAGS = -mthumb -mcpu=cortex-m4 -march=armv7e-m -mfloat-abi=hard -mfpu=fpv4-sp-d16 -fsingle-precision-constant ifeq ($(TARGET_MCU),STM32F411xE) -DEVICE_FLAGS = -DSTM32F411xE -finline-limit=20 +DEVICE_FLAGS += -DSTM32F411xE -finline-limit=20 LD_SCRIPT = $(LINKER_DIR)/stm32_flash_f411.ld STARTUP_SRC = STM32/startup/startup_stm32f411xe.s MCU_FLASH_SIZE := 512 else ifeq ($(TARGET_MCU),STM32F405xx) -DEVICE_FLAGS = -DSTM32F40_41xxx -DSTM32F405xx +DEVICE_FLAGS += -DSTM32F40_41xxx -DSTM32F405xx LD_SCRIPT = $(LINKER_DIR)/stm32_flash_f405.ld STARTUP_SRC = STM32/startup/startup_stm32f40xx.s MCU_FLASH_SIZE := 1024 else ifeq ($(TARGET_MCU),STM32F446xx) -DEVICE_FLAGS = -DSTM32F446xx +DEVICE_FLAGS += -DSTM32F446xx LD_SCRIPT = $(LINKER_DIR)/stm32_flash_f446.ld STARTUP_SRC = STM32/startup/startup_stm32f446xx.s MCU_FLASH_SIZE := 512 @@ -167,7 +171,7 @@ MCU_FLASH_SIZE := 512 else $(error Unknown MCU for F4 target) endif -DEVICE_FLAGS += -DHSE_VALUE=$(HSE_VALUE) -DSTM32 +DEVICE_FLAGS += -DHSE_VALUE=$(HSE_VALUE) MCU_COMMON_SRC = \ common/stm32/system.c \ From 98b1b93199d4fd783d236437080b4664aaeef510 Mon Sep 17 00:00:00 2001 From: "Git bot (blckmn)" Date: Sat, 18 Jan 2025 23:40:31 +0000 Subject: [PATCH 064/244] Auto updated submodule references [18-01-2025] --- src/config | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/config b/src/config index 47cacc174e..fc3d6cb563 160000 --- a/src/config +++ b/src/config @@ -1 +1 @@ -Subproject commit 47cacc174e62ab8c71cc5d16f4f367009065086e +Subproject commit fc3d6cb563ca116c348cc5ed93b0a199dff7a36e From 123faebacfd7a3d34988aaee74b9d42850337c27 Mon Sep 17 00:00:00 2001 From: Kevin Plaizier <46289813+Quick-Flash@users.noreply.github.com> Date: Mon, 20 Jan 2025 13:26:52 -0700 Subject: [PATCH 065/244] Improve accuracy of dT used to update RPM filter (#14150) Improve RPM filter accuracy by using the true looprate when updating it --- src/main/flight/rpm_filter.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/main/flight/rpm_filter.c b/src/main/flight/rpm_filter.c index feb71ec1b3..a95cab2555 100644 --- a/src/main/flight/rpm_filter.c +++ b/src/main/flight/rpm_filter.c @@ -121,6 +121,9 @@ FAST_CODE_NOINLINE void rpmFilterUpdate(void) return; } + const float dtCompensation = schedulerGetCycleTimeMultiplier(); + const float correctedLooptime = rpmFilter.looptimeUs * dtCompensation; + // update RPM notches for (int i = 0; i < notchUpdatesPerIteration; i++) { @@ -143,7 +146,7 @@ FAST_CODE_NOINLINE void rpmFilterUpdate(void) weight *= rpmFilter.weights[harmonicIndex]; // update notch - biquadFilterUpdate(template, frequencyHz, rpmFilter.looptimeUs, rpmFilter.q, FILTER_NOTCH, weight); + biquadFilterUpdate(template, frequencyHz, correctedLooptime, rpmFilter.q, FILTER_NOTCH, weight); // copy notch properties to corresponding notches on PITCH and YAW for (int axis = 1; axis < XYZ_AXIS_COUNT; axis++) { From 5e815ba60859134591cb90cef0e6ac0a57485986 Mon Sep 17 00:00:00 2001 From: Jay Blackman Date: Tue, 21 Jan 2025 10:58:26 +1100 Subject: [PATCH 066/244] Add ability to specify a config.c file for a config target (#14180) - adding configTargetPreInit() method to execute code for the config target --- mk/config.mk | 27 +++++++++++++++++---------- mk/source.mk | 18 +++++++----------- src/main/config/config.h | 1 + src/main/fc/init.c | 8 ++++---- 4 files changed, 29 insertions(+), 25 deletions(-) diff --git a/mk/config.mk b/mk/config.mk index adbd3d7c52..95c4d585f0 100644 --- a/mk/config.mk +++ b/mk/config.mk @@ -16,10 +16,17 @@ ifneq ($(TARGET),) $(error TARGET or CONFIG should be specified. Not both.) endif -CONFIG_FILE = $(CONFIG_DIR)/configs/$(CONFIG)/config.h -INCLUDE_DIRS += $(CONFIG_DIR)/configs/$(CONFIG) +CONFIG_HEADER_FILE = $(CONFIG_DIR)/configs/$(CONFIG)/config.h +CONFIG_SOURCE_FILE = $(CONFIG_DIR)/configs/$(CONFIG)/config.c +INCLUDE_DIRS += $(CONFIG_DIR)/configs/$(CONFIG) -ifneq ($(wildcard $(CONFIG_FILE)),) +ifneq ($(wildcard $(CONFIG_HEADER_FILE)),) + +CONFIG_SRC := +ifneq ($(wildcard $(CONFIG_SOURCE_FILE)),) +CONFIG_SRC += $(CONFIG_SOURCE_FILE) +TARGET_FLAGS += -DUSE_CONFIG_SOURCE +endif CONFIG_REVISION := norevision ifeq ($(shell git -C $(CONFIG_DIR) diff --shortstat),) @@ -27,26 +34,26 @@ CONFIG_REVISION := $(shell git -C $(CONFIG_DIR) log -1 --format="%h") CONFIG_REVISION_DEFINE := -D'__CONFIG_REVISION__="$(CONFIG_REVISION)"' endif -TARGET := $(shell grep " FC_TARGET_MCU" $(CONFIG_FILE) | awk '{print $$3}' ) -HSE_VALUE_MHZ := $(shell grep " SYSTEM_HSE_MHZ" $(CONFIG_FILE) | awk '{print $$3}' ) +TARGET := $(shell grep " FC_TARGET_MCU" $(CONFIG_HEADER_FILE) | awk '{print $$3}' ) +HSE_VALUE_MHZ := $(shell grep " SYSTEM_HSE_MHZ" $(CONFIG_HEADER_FILE) | awk '{print $$3}' ) ifneq ($(HSE_VALUE_MHZ),) HSE_VALUE := $(shell echo $$(( $(HSE_VALUE_MHZ) * 1000000 )) ) endif -GYRO_DEFINE := $(shell grep " USE_GYRO_" $(CONFIG_FILE) | awk '{print $$2}' ) +GYRO_DEFINE := $(shell grep " USE_GYRO_" $(CONFIG_HEADER_FILE) | awk '{print $$2}' ) ifeq ($(TARGET),) -$(error No TARGET identified. Is the $(CONFIG_FILE) valid for $(CONFIG)?) +$(error No TARGET identified. Is the $(CONFIG_HEADER_FILE) valid for $(CONFIG)?) endif -EXST_ADJUST_VMA := $(shell grep " FC_VMA_ADDRESS" $(CONFIG_FILE) | awk '{print $$3}' ) +EXST_ADJUST_VMA := $(shell grep " FC_VMA_ADDRESS" $(CONFIG_HEADER_FILE) | awk '{print $$3}' ) ifneq ($(EXST_ADJUST_VMA),) EXST = yes endif else #exists -$(error `$(CONFIG_FILE)` not found. Have you hydrated configuration using: 'make configs'?) -endif #config_file exists +$(error `$(CONFIG_HEADER_FILE)` not found. Have you hydrated configuration using: 'make configs'?) +endif #CONFIG_HEADER_FILE exists endif #config .PHONY: configs diff --git a/mk/source.mk b/mk/source.mk index 9b981c05cb..9f837c9caa 100644 --- a/mk/source.mk +++ b/mk/source.mk @@ -56,7 +56,6 @@ COMMON_SRC = \ build/debug_pin.c \ build/version.c \ main.c \ - $(PG_SRC) \ common/bitarray.c \ common/colorconversion.c \ common/crc.c \ @@ -369,9 +368,8 @@ SDCARD_SRC += \ io/asyncfatfs/asyncfatfs.c \ io/asyncfatfs/fat_standard.c -INCLUDE_DIRS := $(INCLUDE_DIRS) \ - $(FATFS_DIR) -VPATH := $(VPATH):$(FATFS_DIR) +INCLUDE_DIRS += $(FATFS_DIR) +VPATH := $(VPATH):$(FATFS_DIR) # Gyro driver files that only contain initialization and configuration code - not runtime code SIZE_OPTIMISED_SRC += \ @@ -411,22 +409,20 @@ SPEED_OPTIMISED_SRC += \ endif -COMMON_DEVICE_SRC = \ - $(CMSIS_SRC) \ - $(DEVICE_STDPERIPH_SRC) +COMMON_DEVICE_SRC = $(CMSIS_SRC) $(DEVICE_STDPERIPH_SRC) -COMMON_SRC := $(COMMON_SRC) $(COMMON_DEVICE_SRC) $(RX_SRC) +COMMON_SRC += $(CONFIG_SRC) $(PG_SRC) $(COMMON_DEVICE_SRC) $(RX_SRC) ifeq ($(EXST),yes) -TARGET_FLAGS := -DUSE_EXST $(TARGET_FLAGS) +TARGET_FLAGS += -DUSE_EXST endif ifeq ($(RAM_BASED),yes) -TARGET_FLAGS := -DUSE_EXST -DCONFIG_IN_RAM -DRAMBASED $(TARGET_FLAGS) +TARGET_FLAGS += -DUSE_EXST -DCONFIG_IN_RAM -DRAMBASED endif ifeq ($(SIMULATOR_BUILD),yes) -TARGET_FLAGS := -DSIMULATOR_BUILD $(TARGET_FLAGS) +TARGET_FLAGS += -DSIMULATOR_BUILD endif SPEED_OPTIMISED_SRC += \ diff --git a/src/main/config/config.h b/src/main/config/config.h index 17f35ee36c..2c049f0945 100644 --- a/src/main/config/config.h +++ b/src/main/config/config.h @@ -77,6 +77,7 @@ bool canSoftwareSerialBeUsed(void); void resetConfig(void); void targetConfiguration(void); void targetValidateConfiguration(void); +void configTargetPreInit(void); bool isSystemConfigured(void); void setRebootRequired(void); diff --git a/src/main/fc/init.c b/src/main/fc/init.c index e6e90800fe..becf43fa18 100644 --- a/src/main/fc/init.c +++ b/src/main/fc/init.c @@ -278,15 +278,15 @@ void init(void) // initialize IO (needed for all IO operations) IOInitGlobal(); -#ifdef USE_HARDWARE_REVISION_DETECTION - detectHardwareRevision(); -#endif - #if defined(USE_TARGET_CONFIG) // Call once before the config is loaded for any target specific configuration required to support loading the config targetConfiguration(); #endif +#if defined(USE_CONFIG_TARGET_PREINIT) + configTargetPreInit(); +#endif + enum { FLASH_INIT_ATTEMPTED = (1 << 0), SD_INIT_ATTEMPTED = (1 << 1), From cfb4f8fe08bab122f49d505241958a75929772b5 Mon Sep 17 00:00:00 2001 From: "Git bot (blckmn)" Date: Tue, 21 Jan 2025 06:25:04 +0000 Subject: [PATCH 067/244] Auto updated submodule references [21-01-2025] --- src/config | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/config b/src/config index fc3d6cb563..6e28391b80 160000 --- a/src/config +++ b/src/config @@ -1 +1 @@ -Subproject commit fc3d6cb563ca116c348cc5ed93b0a199dff7a36e +Subproject commit 6e28391b808e2cb63bb25334eab960ec1b85be28 From 899ce6731d5f94b4c17a9b42690bd9df0c82b908 Mon Sep 17 00:00:00 2001 From: pichim <93905657+pichim@users.noreply.github.com> Date: Tue, 21 Jan 2025 11:22:35 +0100 Subject: [PATCH 068/244] Chirp signal generator as flight mode (#13105) --- mk/source.mk | 1 + src/main/blackbox/blackbox.c | 11 ++++ src/main/build/debug.c | 1 + src/main/build/debug.h | 1 + src/main/cli/settings.c | 11 ++++ src/main/common/chirp.c | 94 +++++++++++++++++++++++++++++++++++ src/main/common/chirp.h | 37 ++++++++++++++ src/main/fc/core.c | 10 ++++ src/main/fc/parameter_names.h | 9 ++++ src/main/fc/rc_modes.h | 1 + src/main/fc/runtime_config.h | 3 +- src/main/flight/pid.c | 58 +++++++++++++++++++++ src/main/flight/pid.h | 24 +++++++++ src/main/flight/pid_init.c | 19 +++++++ src/main/msp/msp_box.c | 5 ++ src/main/osd/osd_elements.c | 5 ++ src/main/osd/osd_warnings.c | 10 ++++ src/main/telemetry/crsf.c | 2 + 18 files changed, 301 insertions(+), 1 deletion(-) create mode 100644 src/main/common/chirp.c create mode 100644 src/main/common/chirp.h diff --git a/mk/source.mk b/mk/source.mk index 9f837c9caa..8fe65dde2f 100644 --- a/mk/source.mk +++ b/mk/source.mk @@ -57,6 +57,7 @@ COMMON_SRC = \ build/version.c \ main.c \ common/bitarray.c \ + common/chirp.c \ common/colorconversion.c \ common/crc.c \ common/encoding.c \ diff --git a/src/main/blackbox/blackbox.c b/src/main/blackbox/blackbox.c index c8f359b924..acebd8c2c2 100644 --- a/src/main/blackbox/blackbox.c +++ b/src/main/blackbox/blackbox.c @@ -1642,6 +1642,17 @@ static bool blackboxWriteSysinfo(void) BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_S_YAW, "%d", currentPidProfile->pid[PID_YAW].S); #endif // USE_WING +#ifdef USE_CHIRP + BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_CHIRP_LAG_FREQ_HZ, "%d", currentPidProfile->chirp_lag_freq_hz); + BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_CHIRP_LEAD_FREQ_HZ, "%d", currentPidProfile->chirp_lead_freq_hz); + BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_CHIRP_AMPLITUDE_ROLL, "%d", currentPidProfile->chirp_amplitude_roll); + BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_CHIRP_AMPLITUDE_PITCH, "%d", currentPidProfile->chirp_amplitude_pitch); + BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_CHIRP_AMPLITUDE_YAW, "%d", currentPidProfile->chirp_amplitude_yaw); + BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_CHIRP_FREQUENCY_START_DECI_HZ, "%d", currentPidProfile->chirp_frequency_start_deci_hz); + BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_CHIRP_FREQUENCY_END_DECI_HZ, "%d", currentPidProfile->chirp_frequency_end_deci_hz); + BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_CHIRP_TIME_SECONDS, "%d", currentPidProfile->chirp_time_seconds); +#endif // USE_CHIRP + // End of Betaflight controller parameters BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_DEADBAND, "%d", rcControlsConfig()->deadband); diff --git a/src/main/build/debug.c b/src/main/build/debug.c index 3d67bae371..fb8795bd42 100644 --- a/src/main/build/debug.c +++ b/src/main/build/debug.c @@ -124,4 +124,5 @@ const char * const debugModeNames[DEBUG_COUNT] = { [DEBUG_GIMBAL] = "GIMBAL", [DEBUG_WING_SETPOINT] = "WING_SETPOINT", [DEBUG_AUTOPILOT_POSITION] = "AUTOPILOT_POSITION", + [DEBUG_CHIRP] = "CHIRP", }; diff --git a/src/main/build/debug.h b/src/main/build/debug.h index 6e6e43a67a..b72ebdb496 100644 --- a/src/main/build/debug.h +++ b/src/main/build/debug.h @@ -126,6 +126,7 @@ typedef enum { DEBUG_GIMBAL, DEBUG_WING_SETPOINT, DEBUG_AUTOPILOT_POSITION, + DEBUG_CHIRP, DEBUG_COUNT } debugType_e; diff --git a/src/main/cli/settings.c b/src/main/cli/settings.c index 3e79fc4d78..3db4343db9 100644 --- a/src/main/cli/settings.c +++ b/src/main/cli/settings.c @@ -1263,6 +1263,17 @@ const clivalue_t valueTable[] = { { PARAM_NAME_HORIZON_IGNORE_STICKS, VAR_UINT8 | PROFILE_VALUE | MODE_LOOKUP, .config.lookup = { TABLE_OFF_ON }, PG_PID_PROFILE, offsetof(pidProfile_t, horizon_ignore_sticks) }, { PARAM_NAME_HORIZON_DELAY_MS, VAR_UINT16 | PROFILE_VALUE, .config.minmaxUnsigned = { 10, 5000 }, PG_PID_PROFILE, offsetof(pidProfile_t, horizon_delay_ms) }, +#ifdef USE_CHIRP + { PARAM_NAME_CHIRP_LAG_FREQ_HZ, VAR_UINT8 | PROFILE_VALUE, .config.minmaxUnsigned = { 0, 255 }, PG_PID_PROFILE, offsetof(pidProfile_t, chirp_lag_freq_hz) }, + { PARAM_NAME_CHIRP_LEAD_FREQ_HZ, VAR_UINT8 | PROFILE_VALUE, .config.minmaxUnsigned = { 0, 255 }, PG_PID_PROFILE, offsetof(pidProfile_t, chirp_lead_freq_hz) }, + { PARAM_NAME_CHIRP_AMPLITUDE_ROLL, VAR_UINT16 | PROFILE_VALUE, .config.minmaxUnsigned = { 0, 500 }, PG_PID_PROFILE, offsetof(pidProfile_t, chirp_amplitude_roll) }, + { PARAM_NAME_CHIRP_AMPLITUDE_PITCH, VAR_UINT16 | PROFILE_VALUE, .config.minmaxUnsigned = { 0, 500 }, PG_PID_PROFILE, offsetof(pidProfile_t, chirp_amplitude_pitch) }, + { PARAM_NAME_CHIRP_AMPLITUDE_YAW, VAR_UINT16 | PROFILE_VALUE, .config.minmaxUnsigned = { 0, 500 }, PG_PID_PROFILE, offsetof(pidProfile_t, chirp_amplitude_yaw) }, + { PARAM_NAME_CHIRP_FREQUENCY_START_DECI_HZ, VAR_UINT16 | PROFILE_VALUE, .config.minmaxUnsigned = { 1, 1000 }, PG_PID_PROFILE, offsetof(pidProfile_t, chirp_frequency_start_deci_hz) }, + { PARAM_NAME_CHIRP_FREQUENCY_END_DECI_HZ, VAR_UINT16 | PROFILE_VALUE, .config.minmaxUnsigned = { 1, 10000 }, PG_PID_PROFILE, offsetof(pidProfile_t, chirp_frequency_end_deci_hz) }, + { PARAM_NAME_CHIRP_TIME_SECONDS, VAR_UINT8 | PROFILE_VALUE, .config.minmaxUnsigned = { 1, 255 }, PG_PID_PROFILE, offsetof(pidProfile_t, chirp_time_seconds) }, +#endif + #if defined(USE_ABSOLUTE_CONTROL) { PARAM_NAME_ABS_CONTROL_GAIN, VAR_UINT8 | PROFILE_VALUE, .config.minmaxUnsigned = { 0, 20 }, PG_PID_PROFILE, offsetof(pidProfile_t, abs_control_gain) }, { "abs_control_limit", VAR_UINT8 | PROFILE_VALUE, .config.minmaxUnsigned = { 10, 255 }, PG_PID_PROFILE, offsetof(pidProfile_t, abs_control_limit) }, diff --git a/src/main/common/chirp.c b/src/main/common/chirp.c new file mode 100644 index 0000000000..20aff3db14 --- /dev/null +++ b/src/main/common/chirp.c @@ -0,0 +1,94 @@ +/* + * This file is part of Betaflight. + * + * Betaflight is free software. You can redistribute this software + * and/or modify this software under the terms of the GNU General + * Public License as published by the Free Software Foundation, + * either version 3 of the License, or (at your option) any later + * version. + * + * Betaflight is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * See the GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this software. + * + * If not, see . + */ + +#include + +#include "platform.h" + +#include "maths.h" + +#include "chirp.h" + +// initialize the chirp signal generator +// f0: start frequency in Hz +// f1: end frequency in Hz +// t1: signal length in seconds +// looptimeUs: loop time in microseconds +void chirpInit(chirp_t *chirp, const float f0, const float f1, const float t1, const uint32_t looptimeUs) +{ + chirp->f0 = f0; + chirp->Ts = looptimeUs * 1e-6f; + chirp->N = (uint32_t)(t1 / chirp->Ts); + chirp->beta = pow_approx(f1 / f0, 1.0f / t1); + chirp->k0 = 2.0f * M_PIf / log_approx(chirp->beta); + chirp->k1 = chirp->k0 * f0; + chirpReset(chirp); +} + +// reset the chirp signal generator fully +void chirpReset(chirp_t *chirp) +{ + chirp->count = 0; + chirp->isFinished = false; + chirpResetSignals(chirp); +} + +// reset the chirp signal generator signals +void chirpResetSignals(chirp_t *chirp) +{ + chirp->exc = 0.0f; + chirp->fchirp = 0.0f; + chirp->sinarg = 0.0f; +} + +// update the chirp signal generator +bool chirpUpdate(chirp_t *chirp) +{ + if (chirp->isFinished) { + + return false; + + } else if (chirp->count == chirp->N) { + + chirp->isFinished = true; + chirpResetSignals(chirp); + return false; + + } else { + + chirp->fchirp = chirp->f0 * pow_approx(chirp->beta, (float)(chirp->count) * chirp->Ts); + chirp->sinarg = chirp->k0 * chirp->fchirp - chirp->k1; + + // wrap sinarg to 0...2*pi + chirp->sinarg = fmodf(chirp->sinarg, 2.0f * M_PIf); + + // use cosine so that the angle will oscillate around 0 (integral of gyro) + chirp->exc = cos_approx(chirp->sinarg); + + // frequencies below 1 Hz will lead to the same angle magnitude as at 1 Hz (integral of gyro) + if (chirp->fchirp < 1.0f) { + chirp->exc = chirp->fchirp * chirp->exc; + } + chirp->count++; + + return true; + } +} diff --git a/src/main/common/chirp.h b/src/main/common/chirp.h new file mode 100644 index 0000000000..211a7c66e1 --- /dev/null +++ b/src/main/common/chirp.h @@ -0,0 +1,37 @@ +/* + * This file is part of Betaflight. + * + * Betaflight is free software. You can redistribute this software + * and/or modify this software under the terms of the GNU General + * Public License as published by the Free Software Foundation, + * either version 3 of the License, or (at your option) any later + * version. + * + * Betaflight is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * See the GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this software. + * + * If not, see . + */ + +#pragma once + +#include +#include + +typedef struct chirp_s { + float f0, Ts, beta, k0, k1; + uint32_t count, N; + float exc, fchirp, sinarg; + bool isFinished; +} chirp_t; + +void chirpInit(chirp_t *chirp, const float f0, const float f1, const float t1, const uint32_t looptimeUs); +void chirpReset(chirp_t *chirp); +void chirpResetSignals(chirp_t *chirp); +bool chirpUpdate(chirp_t *chirp); diff --git a/src/main/fc/core.c b/src/main/fc/core.c index 889204938b..75bd3100d0 100644 --- a/src/main/fc/core.c +++ b/src/main/fc/core.c @@ -1092,6 +1092,16 @@ void processRxModes(timeUs_t currentTimeUs) } #endif +#ifdef USE_CHIRP + if (IS_RC_MODE_ACTIVE(BOXCHIRP) && !FLIGHT_MODE(FAILSAFE_MODE) && !FLIGHT_MODE(GPS_RESCUE_MODE)) { + if (!FLIGHT_MODE(CHIRP_MODE)) { + ENABLE_FLIGHT_MODE(CHIRP_MODE); + } + } else { + DISABLE_FLIGHT_MODE(CHIRP_MODE); + } +#endif + if (FLIGHT_MODE(ANGLE_MODE | ALT_HOLD_MODE | POS_HOLD_MODE | HORIZON_MODE)) { LED1_ON; // increase frequency of attitude task to reduce drift when in angle or horizon mode diff --git a/src/main/fc/parameter_names.h b/src/main/fc/parameter_names.h index 43624e06ea..e677b6fe26 100644 --- a/src/main/fc/parameter_names.h +++ b/src/main/fc/parameter_names.h @@ -192,6 +192,15 @@ #define PARAM_NAME_HORIZON_IGNORE_STICKS "horizon_ignore_sticks" #define PARAM_NAME_HORIZON_DELAY_MS "horizon_delay_ms" +#define PARAM_NAME_CHIRP_LAG_FREQ_HZ "chirp_lag_freq_hz" +#define PARAM_NAME_CHIRP_LEAD_FREQ_HZ "chirp_lead_freq_hz" +#define PARAM_NAME_CHIRP_AMPLITUDE_ROLL "chirp_amplitude_roll" +#define PARAM_NAME_CHIRP_AMPLITUDE_PITCH "chirp_amplitude_pitch" +#define PARAM_NAME_CHIRP_AMPLITUDE_YAW "chirp_amplitude_yaw" +#define PARAM_NAME_CHIRP_FREQUENCY_START_DECI_HZ "chirp_frequency_start_deci_hz" +#define PARAM_NAME_CHIRP_FREQUENCY_END_DECI_HZ "chirp_frequency_end_deci_hz" +#define PARAM_NAME_CHIRP_TIME_SECONDS "chirp_time_seconds" + #ifdef USE_GPS #define PARAM_NAME_GPS_PROVIDER "gps_provider" #define PARAM_NAME_GPS_SBAS_MODE "gps_sbas_mode" diff --git a/src/main/fc/rc_modes.h b/src/main/fc/rc_modes.h index 04bd4f2f3a..13838c1c23 100644 --- a/src/main/fc/rc_modes.h +++ b/src/main/fc/rc_modes.h @@ -35,6 +35,7 @@ typedef enum { BOXMAG, BOXALTHOLD, BOXHEADFREE, + BOXCHIRP, BOXPASSTHRU, BOXFAILSAFE, BOXPOSHOLD, diff --git a/src/main/fc/runtime_config.h b/src/main/fc/runtime_config.h index 9d3512ca41..a1df79b426 100644 --- a/src/main/fc/runtime_config.h +++ b/src/main/fc/runtime_config.h @@ -87,7 +87,7 @@ typedef enum { // GPS_HOME_MODE = (1 << 4), POS_HOLD_MODE = (1 << 5), HEADFREE_MODE = (1 << 6), -// UNUSED_MODE = (1 << 7), // old autotune + CHIRP_MODE = (1 << 7), // old autotune PASSTHRU_MODE = (1 << 8), // RANGEFINDER_MODE= (1 << 9), FAILSAFE_MODE = (1 << 10), @@ -109,6 +109,7 @@ extern uint16_t flightModeFlags; [BOXALTHOLD] = LOG2(ALT_HOLD_MODE), \ [BOXPOSHOLD] = LOG2(POS_HOLD_MODE), \ [BOXHEADFREE] = LOG2(HEADFREE_MODE), \ + [BOXCHIRP] = LOG2(CHIRP_MODE), \ [BOXPASSTHRU] = LOG2(PASSTHRU_MODE), \ [BOXFAILSAFE] = LOG2(FAILSAFE_MODE), \ [BOXGPSRESCUE] = LOG2(GPS_RESCUE_MODE), \ diff --git a/src/main/flight/pid.c b/src/main/flight/pid.c index b0fa8fc43b..071c1feaf2 100644 --- a/src/main/flight/pid.c +++ b/src/main/flight/pid.c @@ -260,6 +260,14 @@ void resetPidProfile(pidProfile_t *pidProfile) .tpa_speed_pitch_offset = 0, .yaw_type = YAW_TYPE_RUDDER, .angle_pitch_offset = 0, + .chirp_lag_freq_hz = 3, + .chirp_lead_freq_hz = 30, + .chirp_amplitude_roll = 230, + .chirp_amplitude_pitch = 230, + .chirp_amplitude_yaw = 180, + .chirp_frequency_start_deci_hz = 2, + .chirp_frequency_end_deci_hz = 6000, + .chirp_time_seconds = 20, ); } @@ -1200,9 +1208,49 @@ void FAST_CODE pidController(const pidProfile_t *pidProfile, timeUs_t currentTim disarmOnImpact(); } +#ifdef USE_CHIRP + + static int chirpAxis = 0; + static bool shouldChirpAxisToggle = false; + + float chirp = 0.0f; + float sinarg = 0.0f; + if (FLIGHT_MODE(CHIRP_MODE)) { + shouldChirpAxisToggle = true; // advance chirp axis on next !CHIRP_MODE + // update chirp signal + if (chirpUpdate(&pidRuntime.chirp)) { + chirp = pidRuntime.chirp.exc; + sinarg = pidRuntime.chirp.sinarg; + } + } else { + if (shouldChirpAxisToggle) { + // toggle chirp signal logic and increment to next axis for next run + shouldChirpAxisToggle = false; + chirpAxis = (++chirpAxis > FD_YAW) ? 0 : chirpAxis; + // reset chirp signal generator + chirpReset(&pidRuntime.chirp); + } + } + + // input / excitation shaping + float chirpFiltered = phaseCompApply(&pidRuntime.chirpFilter, chirp); + + // ToDo: check if this can be reconstructed offline for rotating filter and if so, remove the debug + // fit (0...2*pi) into int16_t (-32768 to 32767) + DEBUG_SET(DEBUG_CHIRP, 0, lrintf(5.0e3f * sinarg)); + +#endif // USE_CHIRP + // ----------PID controller---------- for (int axis = FD_ROLL; axis <= FD_YAW; ++axis) { +#ifdef USE_CHIRP + float currentChirp = 0.0f; + if(axis == chirpAxis){ + currentChirp = pidRuntime.chirpAmplitude[axis] * chirpFiltered; + } +#endif // USE_CHIRP + float currentPidSetpoint = getSetpointRate(axis); if (pidRuntime.maxVelocity[axis]) { currentPidSetpoint = accelerationLimit(axis, currentPidSetpoint); @@ -1263,6 +1311,9 @@ void FAST_CODE pidController(const pidProfile_t *pidProfile, timeUs_t currentTim // -----calculate error rate const float gyroRate = gyro.gyroADCf[axis]; // Process variable from gyro output in deg/sec +#ifdef USE_CHIRP + currentPidSetpoint += currentChirp; +#endif // USE_CHIRP float errorRate = currentPidSetpoint - gyroRate; // r - y #if defined(USE_ACC) handleCrashRecovery( @@ -1596,3 +1647,10 @@ float pidGetPidFrequency(void) { return pidRuntime.pidFrequency; } + +#ifdef USE_CHIRP +bool pidChirpIsFinished(void) +{ + return pidRuntime.chirp.isFinished; +} +#endif diff --git a/src/main/flight/pid.h b/src/main/flight/pid.h index f1d077bf6b..8c217dd03c 100644 --- a/src/main/flight/pid.h +++ b/src/main/flight/pid.h @@ -23,6 +23,7 @@ #include #include "common/axis.h" +#include "common/chirp.h" #include "common/filter.h" #include "common/pwl.h" #include "common/time.h" @@ -322,6 +323,15 @@ typedef struct pidProfile_s { int16_t tpa_speed_pitch_offset; // For wings: pitch offset in degrees*10 for craft speed estimation uint8_t yaw_type; // For wings: type of yaw (rudder or differential thrust) int16_t angle_pitch_offset; // For wings: pitch offset for angle modes; in decidegrees; positive values tilting the wing down + + uint8_t chirp_lag_freq_hz; // leadlag1Filter cutoff/pole to shape the excitation signal + uint8_t chirp_lead_freq_hz; // leadlag1Filter cutoff/zero + uint16_t chirp_amplitude_roll; // amplitude roll in degree/second + uint16_t chirp_amplitude_pitch; // amplitude pitch in degree/second + uint16_t chirp_amplitude_yaw; // amplitude yaw in degree/second + uint16_t chirp_frequency_start_deci_hz; // start frequency in units of 0.1 hz + uint16_t chirp_frequency_end_deci_hz; // end frequency in units of 0.1 hz + uint8_t chirp_time_seconds; // excitation time } pidProfile_t; PG_DECLARE_ARRAY(pidProfile_t, PID_PROFILE_COUNT, pidProfiles); @@ -529,6 +539,17 @@ typedef struct pidRuntime_s { float tpaCurvePwl_yValues[TPA_CURVE_PWL_SIZE]; tpaCurveType_t tpaCurveType; #endif // USE_ADVANCED_TPA + +#ifdef USE_CHIRP + chirp_t chirp; + phaseComp_t chirpFilter; + float chirpLagFreqHz; + float chirpLeadFreqHz; + float chirpAmplitude[3]; + float chirpFrequencyStartHz; + float chirpFrequencyEndHz; + float chirpTimeSeconds; +#endif // USE_CHIRP } pidRuntime_t; extern pidRuntime_t pidRuntime; @@ -585,3 +606,6 @@ float pidGetDT(); float pidGetPidFrequency(); float dynLpfCutoffFreq(float throttle, uint16_t dynLpfMin, uint16_t dynLpfMax, uint8_t expo); +#ifdef USE_CHIRP +bool pidChirpIsFinished(); +#endif diff --git a/src/main/flight/pid_init.c b/src/main/flight/pid_init.c index e8ab4ab91f..d8dc0484a2 100644 --- a/src/main/flight/pid_init.c +++ b/src/main/flight/pid_init.c @@ -317,6 +317,14 @@ void pidInitFilters(const pidProfile_t *pidProfile) pidRuntime.angleYawSetpoint = 0.0f; #endif +#ifdef USE_CHIRP + const float alpha = pidRuntime.chirpLeadFreqHz / pidRuntime.chirpLagFreqHz; + const float centerFreqHz = pidRuntime.chirpLagFreqHz * sqrtf(alpha); + const float centerPhaseDeg = asinf( (1.0f - alpha) / (1.0f + alpha) ) / RAD; + phaseCompInit(&pidRuntime.chirpFilter, centerFreqHz, centerPhaseDeg, targetPidLooptime); + chirpInit(&pidRuntime.chirp, pidRuntime.chirpFrequencyStartHz, pidRuntime.chirpFrequencyEndHz, pidRuntime.chirpTimeSeconds, targetPidLooptime); +#endif + pt2FilterInit(&pidRuntime.antiGravityLpf, pt2FilterGain(pidProfile->anti_gravity_cutoff_hz, pidRuntime.dT)); #ifdef USE_WING for (int axis = 0; axis < XYZ_AXIS_COUNT; axis++) { @@ -411,6 +419,17 @@ void pidInitConfig(const pidProfile_t *pidProfile) pidRuntime.horizonDelayMs = pidProfile->horizon_delay_ms; #endif +#ifdef USE_CHIRP + pidRuntime.chirpLagFreqHz = pidProfile->chirp_lag_freq_hz; + pidRuntime.chirpLeadFreqHz = pidProfile->chirp_lead_freq_hz; + pidRuntime.chirpAmplitude[FD_ROLL] = pidProfile->chirp_amplitude_roll; + pidRuntime.chirpAmplitude[FD_PITCH] = pidProfile->chirp_amplitude_pitch; + pidRuntime.chirpAmplitude[FD_YAW]= pidProfile->chirp_amplitude_yaw; + pidRuntime.chirpFrequencyStartHz = pidProfile->chirp_frequency_start_deci_hz / 10.0f; + pidRuntime.chirpFrequencyEndHz = pidProfile->chirp_frequency_end_deci_hz / 10.0f; + pidRuntime.chirpTimeSeconds = pidProfile->chirp_time_seconds; +#endif + pidRuntime.maxVelocity[FD_ROLL] = pidRuntime.maxVelocity[FD_PITCH] = pidProfile->rateAccelLimit * 100 * pidRuntime.dT; pidRuntime.maxVelocity[FD_YAW] = pidProfile->yawRateAccelLimit * 100 * pidRuntime.dT; pidRuntime.antiGravityGain = pidProfile->anti_gravity_gain; diff --git a/src/main/msp/msp_box.c b/src/main/msp/msp_box.c index 7477a5337d..e816db02d9 100644 --- a/src/main/msp/msp_box.c +++ b/src/main/msp/msp_box.c @@ -101,6 +101,7 @@ static const box_t boxes[CHECKBOX_ITEM_COUNT] = { { .boxId = BOXBEEPERMUTE, .boxName = "BEEPER MUTE", .permanentId = 52}, { .boxId = BOXREADY, .boxName = "READY", .permanentId = 53}, { .boxId = BOXLAPTIMERRESET, .boxName = "LAP TIMER RESET", .permanentId = 54}, + { .boxId = BOXCHIRP, .boxName = "CHIRP", .permanentId = 55} }; // mask of enabled IDs, calculated on startup based on enabled features. boxId_e is used as bit index @@ -365,6 +366,10 @@ void initActiveBoxIds(void) BME(BOXLAPTIMERRESET); #endif +#if defined(USE_CHIRP) + BME(BOXCHIRP); +#endif + #undef BME // check that all enabled IDs are in boxes array (check may be skipped when using findBoxById() functions) for (boxId_e boxId = 0; boxId < CHECKBOX_ITEM_COUNT; boxId++) diff --git a/src/main/osd/osd_elements.c b/src/main/osd/osd_elements.c index 1edd59843b..43855697a1 100644 --- a/src/main/osd/osd_elements.c +++ b/src/main/osd/osd_elements.c @@ -1084,6 +1084,11 @@ static void osdElementFlymode(osdElementParms_t *element) strcpy(element->buff, "HOR "); } else if (IS_RC_MODE_ACTIVE(BOXACROTRAINER)) { strcpy(element->buff, "ATRN"); +#ifdef USE_CHIRP + // the additional check for pidChirpIsFinished() is to have visual feedback for user that don't have warnings enabled in their googles + } else if (FLIGHT_MODE(CHIRP_MODE) && !pidChirpIsFinished()) { +#endif + strcpy(element->buff, "CHIR"); } else if (isAirmodeEnabled()) { strcpy(element->buff, "AIR "); } else { diff --git a/src/main/osd/osd_warnings.c b/src/main/osd/osd_warnings.c index bf6b8e1c07..3c983946b0 100644 --- a/src/main/osd/osd_warnings.c +++ b/src/main/osd/osd_warnings.c @@ -432,6 +432,16 @@ void renderOsdWarning(char *warningText, bool *blinking, uint8_t *displayAttr) return; } +#ifdef USE_CHIRP + // Visual info that chirp excitation is finished + if (pidChirpIsFinished()) { + tfp_sprintf(warningText, "CHIRP EXC FINISHED"); + *displayAttr = DISPLAYPORT_SEVERITY_INFO; + *blinking = true; + return; + } +#endif // USE_CHIRP + } #endif // USE_OSD diff --git a/src/main/telemetry/crsf.c b/src/main/telemetry/crsf.c index 68d654831b..48140efae8 100644 --- a/src/main/telemetry/crsf.c +++ b/src/main/telemetry/crsf.c @@ -463,6 +463,8 @@ void crsfFrameFlightMode(sbuf_t *dst) flightMode = "ALTH"; } else if (FLIGHT_MODE(HORIZON_MODE)) { flightMode = "HOR"; + } else if (FLIGHT_MODE(CHIRP_MODE)) { + flightMode = "CHIR"; } else if (isAirmodeEnabled()) { flightMode = "AIR"; } From 1aa71452fb64d9e2f8d6a9b03f8525b6faba5d7e Mon Sep 17 00:00:00 2001 From: Steve Evans Date: Tue, 21 Jan 2025 20:42:42 +0000 Subject: [PATCH 069/244] By default mark OSD element as rendered in case it's in the off blink state (#14188) (#14189) * By default render OSD element in a single cycle * Use return value of osdDrawSingleElement and double check activeElement.rendered --- src/main/osd/osd_elements.c | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/src/main/osd/osd_elements.c b/src/main/osd/osd_elements.c index 43855697a1..99cc5484f4 100644 --- a/src/main/osd/osd_elements.c +++ b/src/main/osd/osd_elements.c @@ -2128,6 +2128,9 @@ void osdAddActiveElements(void) static bool osdDrawSingleElement(displayPort_t *osdDisplayPort, uint8_t item) { + // By default mark the element as rendered in case it's in the off blink state + activeElement.rendered = true; + if (!osdElementDrawFunction[item]) { // Element has no drawing function return true; @@ -2148,7 +2151,6 @@ static bool osdDrawSingleElement(displayPort_t *osdDisplayPort, uint8_t item) activeElement.buff = elementBuff; activeElement.osdDisplayPort = osdDisplayPort; activeElement.drawElement = true; - activeElement.rendered = true; activeElement.attr = DISPLAYPORT_SEVERITY_NORMAL; // Call the element drawing function @@ -2272,14 +2274,13 @@ bool osdDrawNextActiveElement(displayPort_t *osdDisplayPort) // Only advance to the next element if rendering is complete if (osdDrawSingleElement(osdDisplayPort, item)) { // If rendering is complete then advance to the next element - if (activeElement.rendered) { - // Prepare to render the background of the next element - backgroundRendered = false; - if (++activeElementNumber >= activeOsdElementCount) { - activeElementNumber = 0; - return false; - } + // Prepare to render the background of the next element + backgroundRendered = false; + + if (++activeElementNumber >= activeOsdElementCount) { + activeElementNumber = 0; + return false; } } From 2b6df7aafe3873bbaaf72c713160093be2cebf9b Mon Sep 17 00:00:00 2001 From: "Git bot (blckmn)" Date: Wed, 22 Jan 2025 06:25:03 +0000 Subject: [PATCH 070/244] Auto updated submodule references [22-01-2025] --- src/config | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/config b/src/config index 6e28391b80..3f3dd34c73 160000 --- a/src/config +++ b/src/config @@ -1 +1 @@ -Subproject commit 6e28391b808e2cb63bb25334eab960ec1b85be28 +Subproject commit 3f3dd34c7368e5ec6c2eb5634ac638d706b1d4a8 From 01af6d13bf216a5d96f106c22edfec0688fea439 Mon Sep 17 00:00:00 2001 From: Mark Haslinghuis Date: Wed, 22 Jan 2025 17:37:13 +0100 Subject: [PATCH 071/244] Ignore submodule (#14190) --- .gitmodules | 1 + 1 file changed, 1 insertion(+) diff --git a/.gitmodules b/.gitmodules index fc19f2d6b8..70c3f1c3ee 100644 --- a/.gitmodules +++ b/.gitmodules @@ -2,3 +2,4 @@ path = src/config url = https://github.com/betaflight/config.git branch = master + ignore = dirty From 908a347d2f7a3b5fa8862ca63fd9bd8b2baba89d Mon Sep 17 00:00:00 2001 From: Jay Blackman Date: Fri, 24 Jan 2025 08:17:28 +1100 Subject: [PATCH 072/244] Refactor SPI pre init to make it generic and usable from io.h (#14174) --- mk/source.mk | 1 + src/main/drivers/accgyro/accgyro_mpu.c | 6 +- .../drivers/barometer/barometer_2smpb_02b.c | 2 +- src/main/drivers/barometer/barometer_bmp280.c | 2 +- src/main/drivers/barometer/barometer_bmp388.c | 2 +- src/main/drivers/barometer/barometer_dps310.c | 2 +- .../drivers/barometer/barometer_lps22df.c | 2 +- src/main/drivers/barometer/barometer_ms5611.c | 2 +- src/main/drivers/bus_spi.h | 4 -- src/main/drivers/bus_spi_config.c | 64 ++----------------- src/main/drivers/compass/compass_ak8963.c | 2 +- src/main/drivers/flash/flash.c | 7 +- src/main/drivers/flash/flash.h | 2 +- src/main/drivers/io.h | 9 +++ src/main/drivers/io_preinit.c | 58 +++++++++++++++++ src/main/drivers/max7456.c | 4 +- src/main/drivers/max7456.h | 2 +- src/main/drivers/rx/rx_spi.c | 4 +- src/main/drivers/rx/rx_spi.h | 2 +- src/main/drivers/sdcard.c | 4 +- src/main/drivers/sdcard.h | 2 +- src/main/drivers/sdcard_impl.h | 2 +- src/main/drivers/sdcard_spi.c | 6 +- src/main/sensors/barometer.c | 2 +- src/main/sensors/compass.c | 2 +- src/main/target/common_post.h | 8 --- src/platform/STM32/mk/STM32F4.mk | 4 -- src/platform/STM32/mk/STM32F7.mk | 4 -- src/platform/STM32/mk/STM32G4.mk | 4 -- src/platform/STM32/mk/STM32H5.mk | 4 -- src/platform/STM32/mk/STM32H7.mk | 4 -- src/platform/STM32/mk/STM32_COMMON.mk | 4 ++ src/test/unit/baro_bmp280_unittest.cc | 2 +- src/test/unit/baro_bmp388_unittest.cc | 2 +- src/test/unit/baro_ms5611_unittest.cc | 2 +- 35 files changed, 107 insertions(+), 126 deletions(-) create mode 100644 src/main/drivers/io_preinit.c diff --git a/mk/source.mk b/mk/source.mk index 8fe65dde2f..f455771251 100644 --- a/mk/source.mk +++ b/mk/source.mk @@ -104,6 +104,7 @@ COMMON_SRC = \ drivers/display_canvas.c \ drivers/dma_common.c \ drivers/io.c \ + drivers/io_preinit.c \ drivers/light_led.c \ drivers/mco.c \ drivers/motor.c \ diff --git a/src/main/drivers/accgyro/accgyro_mpu.c b/src/main/drivers/accgyro/accgyro_mpu.c index 1f1943dc3b..415e0af98b 100644 --- a/src/main/drivers/accgyro/accgyro_mpu.c +++ b/src/main/drivers/accgyro/accgyro_mpu.c @@ -410,9 +410,7 @@ static bool detectSPISensorsAndUpdateDetectionResult(gyroDev_t *gyro, const gyro } // Detection failed, disable CS pin again - - spiPreinitByTag(config->csnTag); - + ioPreinitByIO(gyro->dev.busType_u.spi.csnPin, IOCFG_IPU, PREINIT_PIN_STATE_HIGH); return false; } #endif @@ -420,7 +418,7 @@ static bool detectSPISensorsAndUpdateDetectionResult(gyroDev_t *gyro, const gyro void mpuPreInit(const struct gyroDeviceConfig_s *config) { #ifdef USE_SPI_GYRO - spiPreinitRegister(config->csnTag, IOCFG_IPU, 1); + ioPreinitByTag(config->csnTag, IOCFG_IPU, PREINIT_PIN_STATE_HIGH); #else UNUSED(config); #endif diff --git a/src/main/drivers/barometer/barometer_2smpb_02b.c b/src/main/drivers/barometer/barometer_2smpb_02b.c index 0af77c4b9d..a54a930159 100644 --- a/src/main/drivers/barometer/barometer_2smpb_02b.c +++ b/src/main/drivers/barometer/barometer_2smpb_02b.c @@ -192,7 +192,7 @@ static void busDeviceDeInit(const extDevice_t *dev) { #ifdef USE_BARO_SPI_2SMBP_02B if (dev->bus->busType == BUS_TYPE_SPI) { - spiPreinitByIO(dev->busType_u.spi.csnPin); + ioPreinitByIO(dev->busType_u.spi.csnPin, IOCFG_IPU, PREINIT_PIN_STATE_HIGH); } #else UNUSED(dev); diff --git a/src/main/drivers/barometer/barometer_bmp280.c b/src/main/drivers/barometer/barometer_bmp280.c index 77773888e0..4dc55468e5 100644 --- a/src/main/drivers/barometer/barometer_bmp280.c +++ b/src/main/drivers/barometer/barometer_bmp280.c @@ -135,7 +135,7 @@ void bmp280BusDeinit(const extDevice_t *dev) { #ifdef USE_BARO_SPI_BMP280 if (dev->bus->busType == BUS_TYPE_SPI) { - spiPreinitByIO(dev->busType_u.spi.csnPin); + ioPreinitByIO(dev->busType_u.spi.csnPin, IOCFG_IPU, PREINIT_PIN_STATE_HIGH); } #else UNUSED(dev); diff --git a/src/main/drivers/barometer/barometer_bmp388.c b/src/main/drivers/barometer/barometer_bmp388.c index c7dfbb8dd7..6fa2e1efb7 100644 --- a/src/main/drivers/barometer/barometer_bmp388.c +++ b/src/main/drivers/barometer/barometer_bmp388.c @@ -230,7 +230,7 @@ void bmp388BusDeinit(const extDevice_t *dev) { #ifdef USE_BARO_SPI_BMP388 if (dev->bus->busType == BUS_TYPE_SPI) { - spiPreinitByIO(dev->busType_u.spi.csnPin); + ioPreinitByIO(dev->busType_u.spi.csnPin, IOCFG_IPU, PREINIT_PIN_STATE_HIGH); } #else UNUSED(dev); diff --git a/src/main/drivers/barometer/barometer_dps310.c b/src/main/drivers/barometer/barometer_dps310.c index 9653f95d0a..23e5e0923a 100644 --- a/src/main/drivers/barometer/barometer_dps310.c +++ b/src/main/drivers/barometer/barometer_dps310.c @@ -377,7 +377,7 @@ static void deviceDeInit(const extDevice_t *dev) { #ifdef USE_BARO_SPI_DPS310 if (dev->bus->busType == BUS_TYPE_SPI) { - spiPreinitByIO(dev->busType_u.spi.csnPin); + ioPreinitByIO(dev->busType_u.spi.csnPin, IOCFG_IPU, PREINIT_PIN_STATE_HIGH); } #else UNUSED(dev); diff --git a/src/main/drivers/barometer/barometer_lps22df.c b/src/main/drivers/barometer/barometer_lps22df.c index 31771e6616..4ab3620e6c 100644 --- a/src/main/drivers/barometer/barometer_lps22df.c +++ b/src/main/drivers/barometer/barometer_lps22df.c @@ -245,7 +245,7 @@ void lps22dfBusDeinit(const extDevice_t *dev) { #ifdef USE_BARO_SPI_LPS22DF if (dev->bus->busType == BUS_TYPE_SPI) { - spiPreinitByIO(dev->busType_u.spi.csnPin); + ioPreinitByIO(dev->busType_u.spi.csnPin, IOCFG_IPU, PREINIT_PIN_STATE_HIGH); } #else UNUSED(dev); diff --git a/src/main/drivers/barometer/barometer_ms5611.c b/src/main/drivers/barometer/barometer_ms5611.c index 41af52619b..3223cde2c2 100644 --- a/src/main/drivers/barometer/barometer_ms5611.c +++ b/src/main/drivers/barometer/barometer_ms5611.c @@ -80,7 +80,7 @@ void ms5611BusDeinit(const extDevice_t *dev) { #ifdef USE_BARO_SPI_MS5611 if (dev->bus->busType == BUS_TYPE_SPI) { - spiPreinitByIO(dev->busType_u.spi.csnPin); + ioPreinitByIO(dev->busType_u.spi.csnPin, IOCFG_IPU, PREINIT_PIN_STATE_HIGH); } #else UNUSED(dev); diff --git a/src/main/drivers/bus_spi.h b/src/main/drivers/bus_spi.h index 530d38899a..b355cbaab3 100644 --- a/src/main/drivers/bus_spi.h +++ b/src/main/drivers/bus_spi.h @@ -65,10 +65,6 @@ typedef enum SPIDevice { #define SPI_DEV_TO_CFG(x) ((x) + 1) void spiPreinit(void); -void spiPreinitRegister(ioTag_t iotag, uint8_t iocfg, uint8_t init); -void spiPreinitByIO(const IO_t io); -void spiPreinitByTag(ioTag_t tag); - bool spiInit(SPIDevice device); // Called after all devices are initialised to enable SPI DMA where streams are available. diff --git a/src/main/drivers/bus_spi_config.c b/src/main/drivers/bus_spi_config.c index 8e96b9d49b..d27605dcca 100644 --- a/src/main/drivers/bus_spi_config.c +++ b/src/main/drivers/bus_spi_config.c @@ -39,48 +39,10 @@ #include "pg/rx_spi.h" #include "pg/sdcard.h" -typedef struct spiPreinit_s { - ioTag_t iotag; - uint8_t iocfg; - bool init; -} spiPreinit_t; - -static spiPreinit_t spiPreinitArray[SPI_PREINIT_COUNT]; -static int spiPreinitCount = 0; - -void spiPreinitRegister(ioTag_t iotag, uint8_t iocfg, bool init) -{ - if (!iotag) { - return; - } - - if (spiPreinitCount == SPI_PREINIT_COUNT) { - indicateFailure(FAILURE_DEVELOPER, 5); - return; - } - - spiPreinitArray[spiPreinitCount].iotag = iotag; - spiPreinitArray[spiPreinitCount].iocfg = iocfg; - spiPreinitArray[spiPreinitCount].init = init; - ++spiPreinitCount; -} - -static void spiPreinitPin(spiPreinit_t *preinit, int index) -{ - IO_t io = IOGetByTag(preinit->iotag); - IOInit(io, OWNER_PREINIT, RESOURCE_INDEX(index)); - IOConfigGPIO(io, preinit->iocfg); - if (preinit->init) { - IOHi(io); - } else { - IOLo(io); - } -} - void spiPreinit(void) { #ifdef USE_SDCARD_SPI - sdcard_preInit(sdcardConfig()); + sdcard_preinit(sdcardConfig()); #endif #if defined(RTC6705_CS_PIN) && !defined(USE_VTX_RTC6705_SOFTSPI) // RTC6705 soft SPI initialisation handled elsewhere. @@ -88,34 +50,16 @@ void spiPreinit(void) #endif #ifdef USE_FLASH_CHIP - flashPreInit(flashConfig()); + flashPreinit(flashConfig()); #endif #if defined(USE_RX_SPI) - rxSpiDevicePreInit(rxSpiConfig()); + rxSpiDevicePreinit(rxSpiConfig()); #endif #ifdef USE_MAX7456 - max7456PreInit(max7456Config()); + max7456Preinit(max7456Config()); #endif - - for (int i = 0; i < spiPreinitCount; i++) { - spiPreinitPin(&spiPreinitArray[i], i); - } } -void spiPreinitByIO(const IO_t io) -{ - for (int i = 0; i < spiPreinitCount; i++) { - if (io == IOGetByTag(spiPreinitArray[i].iotag)) { - spiPreinitPin(&spiPreinitArray[i], i); - return; - } - } -} - -void spiPreinitByTag(ioTag_t tag) -{ - spiPreinitByIO(IOGetByTag(tag)); -} #endif diff --git a/src/main/drivers/compass/compass_ak8963.c b/src/main/drivers/compass/compass_ak8963.c index 6fea1b3132..e744deb276 100644 --- a/src/main/drivers/compass/compass_ak8963.c +++ b/src/main/drivers/compass/compass_ak8963.c @@ -420,7 +420,7 @@ void ak8963BusDeInit(const extDevice_t *dev) #ifdef USE_MAG_SPI_AK8963 case BUS_TYPE_SPI: - spiPreinitByIO(dev->busType_u.spi.csnPin); + ioPreinitByIO(dev->busType_u.spi.csnPin, IOCFG_IPU, PREINIT_PIN_STATE_HIGH); break; #endif diff --git a/src/main/drivers/flash/flash.c b/src/main/drivers/flash/flash.c index 884e2d4eaf..8e48f07a92 100644 --- a/src/main/drivers/flash/flash.c +++ b/src/main/drivers/flash/flash.c @@ -350,15 +350,14 @@ static bool flashSpiInit(const flashConfig_t *flashConfig) return detected; } - spiPreinitByTag(flashConfig->csTag); - + ioPreinitByTag(flashConfig->csTag, IOCFG_IPU, PREINIT_PIN_STATE_HIGH); return false; } #endif // USE_FLASH_SPI -void flashPreInit(const flashConfig_t *flashConfig) +void flashPreinit(const flashConfig_t *flashConfig) { - spiPreinitRegister(flashConfig->csTag, IOCFG_IPU, 1); + ioPreinitByTag(flashConfig->csTag, IOCFG_IPU, PREINIT_PIN_STATE_HIGH); } bool flashDeviceInit(const flashConfig_t *flashConfig) diff --git a/src/main/drivers/flash/flash.h b/src/main/drivers/flash/flash.h index 964ba549c4..8ef8144a24 100644 --- a/src/main/drivers/flash/flash.h +++ b/src/main/drivers/flash/flash.h @@ -57,7 +57,7 @@ typedef enum { FLASH_CF_SYSTEM_IS_MEMORY_MAPPED = (1 << 0), } flashConfigurationFlags_e; -void flashPreInit(const flashConfig_t *flashConfig); +void flashPreinit(const flashConfig_t *flashConfig); bool flashInit(const flashConfig_t *flashConfig); bool flashIsReady(void); diff --git a/src/main/drivers/io.h b/src/main/drivers/io.h index 9994ccf544..620ae613f0 100644 --- a/src/main/drivers/io.h +++ b/src/main/drivers/io.h @@ -64,3 +64,12 @@ void IOTraversePins(IOTraverseFuncPtr_t func); GPIO_TypeDef* IO_GPIO(IO_t io); uint16_t IO_Pin(IO_t io); + +typedef enum { + PREINIT_PIN_STATE_NOCHANGE = 0, + PREINIT_PIN_STATE_LOW, + PREINIT_PIN_STATE_HIGH, +} ioPreinitPinState_e; + +void ioPreinitByIO(const IO_t io, uint8_t iocfg, ioPreinitPinState_e init); +void ioPreinitByTag(ioTag_t tag, uint8_t iocfg, ioPreinitPinState_e init); diff --git a/src/main/drivers/io_preinit.c b/src/main/drivers/io_preinit.c new file mode 100644 index 0000000000..81ca43d420 --- /dev/null +++ b/src/main/drivers/io_preinit.c @@ -0,0 +1,58 @@ +/* + * This file is part of Betaflight. + * + * Betaflight is free software. You can redistribute this software + * and/or modify this software under the terms of the GNU General + * Public License as published by the Free Software Foundation, + * either version 3 of the License, or (at your option) any later + * version. + * + * Betaflight is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * See the GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this software. + * + * If not, see . + */ + +#include +#include + +#include "platform.h" + +#include "drivers/io.h" +#include "drivers/resource.h" +#include "drivers/system.h" + +static unsigned preinitIndex = 0; + +void ioPreinitByIO(const IO_t io, uint8_t iocfg, ioPreinitPinState_e init) +{ + if (!io) { + return; + } + preinitIndex++; + + IOInit(io, OWNER_PREINIT, preinitIndex); + IOConfigGPIO(io, iocfg); + + switch(init) { + case PREINIT_PIN_STATE_LOW: + IOLo(io); + break; + case PREINIT_PIN_STATE_HIGH: + IOHi(io); + break; + default: + // Do nothing + } +} + +void ioPreinitByTag(ioTag_t tag, uint8_t iocfg, ioPreinitPinState_e init) +{ + ioPreinitByIO(IOGetByTag(tag), iocfg, init); +} diff --git a/src/main/drivers/max7456.c b/src/main/drivers/max7456.c index b0cc1ba22d..42341a4ff1 100644 --- a/src/main/drivers/max7456.c +++ b/src/main/drivers/max7456.c @@ -330,9 +330,9 @@ void max7456ReInit(void) max7456ClearShadowBuffer(); } -void max7456PreInit(const max7456Config_t *max7456Config) +void max7456Preinit(const max7456Config_t *max7456Config) { - spiPreinitRegister(max7456Config->csTag, max7456Config->preInitOPU ? IOCFG_OUT_PP : IOCFG_IPU, 1); + ioPreinitByTag(max7456Config->csTag, max7456Config->preInitOPU ? IOCFG_OUT_PP : IOCFG_IPU, PREINIT_PIN_STATE_HIGH); } // Here we init only CS and try to init MAX for first time. diff --git a/src/main/drivers/max7456.h b/src/main/drivers/max7456.h index 154fa9e206..e836595602 100644 --- a/src/main/drivers/max7456.h +++ b/src/main/drivers/max7456.h @@ -43,7 +43,7 @@ extern uint16_t maxScreenSize; struct vcdProfile_s; void max7456HardwareReset(void); struct max7456Config_s; -void max7456PreInit(const struct max7456Config_s *max7456Config); +void max7456Preinit(const struct max7456Config_s *max7456Config); max7456InitStatus_e max7456Init(const struct max7456Config_s *max7456Config, const struct vcdProfile_s *vcdProfile, bool cpuOverclock); void max7456Invert(bool invert); void max7456Brightness(uint8_t black, uint8_t white); diff --git a/src/main/drivers/rx/rx_spi.c b/src/main/drivers/rx/rx_spi.c index c025fdf296..e21dd78fcd 100644 --- a/src/main/drivers/rx/rx_spi.c +++ b/src/main/drivers/rx/rx_spi.c @@ -70,9 +70,9 @@ extDevice_t *rxSpiGetDevice(void) return dev; } -void rxSpiDevicePreInit(const rxSpiConfig_t *rxSpiConfig) +void rxSpiDevicePreinit(const rxSpiConfig_t *rxSpiConfig) { - spiPreinitRegister(rxSpiConfig->csnTag, IOCFG_IPU, 1); + ioPreinitByTag(rxSpiConfig->csnTag, IOCFG_IPU, PREINIT_PIN_STATE_HIGH); } void rxSpiExtiHandler(extiCallbackRec_t* callback) diff --git a/src/main/drivers/rx/rx_spi.h b/src/main/drivers/rx/rx_spi.h index d8eb59b0fd..ab51a760cc 100644 --- a/src/main/drivers/rx/rx_spi.h +++ b/src/main/drivers/rx/rx_spi.h @@ -32,7 +32,7 @@ struct rxSpiConfig_s; extDevice_t *rxSpiGetDevice(void); -void rxSpiDevicePreInit(const struct rxSpiConfig_s *rxSpiConfig); +void rxSpiDevicePreinit(const struct rxSpiConfig_s *rxSpiConfig); bool rxSpiDeviceInit(const struct rxSpiConfig_s *rxSpiConfig); void rxSpiSetNormalSpeedMhz(uint32_t mhz); void rxSpiNormalSpeed(); diff --git a/src/main/drivers/sdcard.c b/src/main/drivers/sdcard.c index 1cc4c7595a..c333d493cc 100644 --- a/src/main/drivers/sdcard.c +++ b/src/main/drivers/sdcard.c @@ -103,10 +103,10 @@ bool sdcard_isInserted(void) */ sdcardVTable_t *sdcardVTable; -void sdcard_preInit(const sdcardConfig_t *config) +void sdcard_preinit(const sdcardConfig_t *config) { #ifdef USE_SDCARD_SPI - sdcardSpiVTable.sdcard_preInit(config); + sdcardSpiVTable.sdcard_preinit(config); #else UNUSED(config); #endif diff --git a/src/main/drivers/sdcard.h b/src/main/drivers/sdcard.h index 11c9fac4d3..7b647252c8 100644 --- a/src/main/drivers/sdcard.h +++ b/src/main/drivers/sdcard.h @@ -57,7 +57,7 @@ typedef void(*sdcard_operationCompleteCallback_c)(sdcardBlockOperation_e operati typedef void(*sdcard_profilerCallback_c)(sdcardBlockOperation_e operation, uint32_t blockIndex, uint32_t duration); -void sdcard_preInit(const sdcardConfig_t *config); +void sdcard_preinit(const sdcardConfig_t *config); void sdcard_init(const sdcardConfig_t *config); bool sdcard_readBlock(uint32_t blockIndex, uint8_t *buffer, sdcard_operationCompleteCallback_c callback, uint32_t callbackData); diff --git a/src/main/drivers/sdcard_impl.h b/src/main/drivers/sdcard_impl.h index 79a605f837..e65a7d4eb3 100644 --- a/src/main/drivers/sdcard_impl.h +++ b/src/main/drivers/sdcard_impl.h @@ -109,7 +109,7 @@ STATIC_ASSERT(sizeof(sdcardCSD_t) == 16, sdcard_csd_bitfields_didnt_pack_properl bool sdcard_isInserted(void); typedef struct sdcardVTable_s { - void (*sdcard_preInit)(const sdcardConfig_t *config); + void (*sdcard_preinit)(const sdcardConfig_t *config); void (*sdcard_init)(const sdcardConfig_t *config, const spiPinConfig_t *spiConfig); bool (*sdcard_readBlock)(uint32_t blockIndex, uint8_t *buffer, sdcard_operationCompleteCallback_c callback, uint32_t callbackData); sdcardOperationStatus_e (*sdcard_beginWriteBlocks)(uint32_t blockIndex, uint32_t blockCount); diff --git a/src/main/drivers/sdcard_spi.c b/src/main/drivers/sdcard_spi.c index 65e7157e5b..40c9a646b1 100644 --- a/src/main/drivers/sdcard_spi.c +++ b/src/main/drivers/sdcard_spi.c @@ -536,9 +536,9 @@ static bool sdcard_checkInitDone(void) return status == 0x00; } -void sdcardSpi_preInit(const sdcardConfig_t *config) +void sdcardSpi_preinit(const sdcardConfig_t *config) { - spiPreinitRegister(config->chipSelectTag, IOCFG_IPU, 1); + ioPreinitByTag(config->chipSelectTag, IOCFG_IPU, PREINIT_PIN_STATE_HIGH); } /** @@ -1101,7 +1101,7 @@ static void sdcardSpi_setProfilerCallback(sdcard_profilerCallback_c callback) #endif sdcardVTable_t sdcardSpiVTable = { - sdcardSpi_preInit, + sdcardSpi_preinit, sdcardSpi_init, sdcardSpi_readBlock, sdcardSpi_beginWriteBlocks, diff --git a/src/main/sensors/barometer.c b/src/main/sensors/barometer.c index cce06233d9..9e375a6f47 100644 --- a/src/main/sensors/barometer.c +++ b/src/main/sensors/barometer.c @@ -180,7 +180,7 @@ void baroPreInit(void) { #ifdef USE_SPI if (barometerConfig()->baro_busType == BUS_TYPE_SPI) { - spiPreinitRegister(barometerConfig()->baro_spi_csn, IOCFG_IPU, 1); + ioPreinitByTag(barometerConfig()->baro_spi_csn, IOCFG_IPU, PREINIT_PIN_STATE_HIGH); } #endif } diff --git a/src/main/sensors/compass.c b/src/main/sensors/compass.c index 4a1bfc99d3..2ca1b0f689 100644 --- a/src/main/sensors/compass.c +++ b/src/main/sensors/compass.c @@ -150,7 +150,7 @@ void compassPreInit(void) { #ifdef USE_SPI if (compassConfig()->mag_busType == BUS_TYPE_SPI) { - spiPreinitRegister(compassConfig()->mag_spi_csn, IOCFG_IPU, 1); + ioPreinitByTag(compassConfig()->mag_spi_csn, IOCFG_IPU, PREINIT_PIN_STATE_HIGH); } #endif } diff --git a/src/main/target/common_post.h b/src/main/target/common_post.h index 976ba8e7c3..76d872128d 100644 --- a/src/main/target/common_post.h +++ b/src/main/target/common_post.h @@ -498,14 +498,6 @@ #define SYSTEM_HSE_MHZ 0 #endif -// Number of pins that needs pre-init -#ifdef USE_SPI -#ifndef SPI_PREINIT_COUNT -// 2 x 8 (GYROx2, BARO, MAG, MAX, FLASHx2, RX) -#define SPI_PREINIT_COUNT 16 -#endif -#endif - #ifndef USE_BLACKBOX #undef USE_USB_MSC #endif diff --git a/src/platform/STM32/mk/STM32F4.mk b/src/platform/STM32/mk/STM32F4.mk index 9d1f404557..09ac1e719d 100644 --- a/src/platform/STM32/mk/STM32F4.mk +++ b/src/platform/STM32/mk/STM32F4.mk @@ -205,8 +205,6 @@ MCU_COMMON_SRC = \ STM32/usbd_msc_desc.c \ STM32/camera_control_stm32.c \ drivers/adc.c \ - drivers/bus_i2c_config.c \ - drivers/bus_spi_config.c \ drivers/serial_escserial.c \ drivers/serial_pinconfig.c \ drivers/serial_uart_pinconfig.c \ @@ -219,8 +217,6 @@ SPEED_OPTIMISED_SRC += \ SIZE_OPTIMISED_SRC += \ STM32/serial_usb_vcp.c \ drivers/inverter.c \ - drivers/bus_i2c_config.c \ - drivers/bus_spi_config.c \ drivers/serial_escserial.c \ drivers/serial_pinconfig.c diff --git a/src/platform/STM32/mk/STM32F7.mk b/src/platform/STM32/mk/STM32F7.mk index b197c92774..5e035639c2 100644 --- a/src/platform/STM32/mk/STM32F7.mk +++ b/src/platform/STM32/mk/STM32F7.mk @@ -170,8 +170,6 @@ MCU_COMMON_SRC = \ STM32/transponder_ir_io_hal.c \ STM32/camera_control_stm32.c \ drivers/adc.c \ - drivers/bus_i2c_config.c \ - drivers/bus_spi_config.c \ drivers/serial_escserial.c \ drivers/serial_pinconfig.c \ drivers/serial_uart_pinconfig.c \ @@ -199,8 +197,6 @@ SIZE_OPTIMISED_SRC += \ drivers/bus_i2c_timing.c \ STM32/bus_i2c_hal_init.c \ STM32/serial_usb_vcp.c \ - drivers/bus_i2c_config.c \ - drivers/bus_spi_config.c \ drivers/serial_escserial.c \ drivers/serial_pinconfig.c \ drivers/serial_uart_pinconfig.c diff --git a/src/platform/STM32/mk/STM32G4.mk b/src/platform/STM32/mk/STM32G4.mk index 41b1ba1a45..2761c42bea 100644 --- a/src/platform/STM32/mk/STM32G4.mk +++ b/src/platform/STM32/mk/STM32G4.mk @@ -147,8 +147,6 @@ MCU_COMMON_SRC = \ STM32/transponder_ir_io_hal.c \ STM32/camera_control_stm32.c \ drivers/adc.c \ - drivers/bus_i2c_config.c \ - drivers/bus_spi_config.c \ drivers/serial_escserial.c \ drivers/serial_pinconfig.c \ drivers/serial_uart_pinconfig.c \ @@ -172,8 +170,6 @@ SIZE_OPTIMISED_SRC += \ drivers/bus_i2c_timing.c \ STM32/bus_i2c_hal_init.c \ STM32/serial_usb_vcp.c \ - drivers/bus_i2c_config.c \ - drivers/bus_spi_config.c \ drivers/serial_escserial.c \ drivers/serial_pinconfig.c \ drivers/serial_uart_pinconfig.c diff --git a/src/platform/STM32/mk/STM32H5.mk b/src/platform/STM32/mk/STM32H5.mk index b8fb8511d2..4cfd67a706 100644 --- a/src/platform/STM32/mk/STM32H5.mk +++ b/src/platform/STM32/mk/STM32H5.mk @@ -173,8 +173,6 @@ MCU_COMMON_SRC = \ STM32/camera_control_stm32.c \ STM32/system_stm32h5xx.c \ drivers/adc.c \ - drivers/bus_i2c_config.c \ - drivers/bus_spi_config.c \ drivers/serial_escserial.c \ drivers/serial_pinconfig.c \ drivers/serial_uart_pinconfig.c \ @@ -206,8 +204,6 @@ SIZE_OPTIMISED_SRC += \ drivers/bus_i2c_timing.c \ STM32/bus_i2c_hal_init.c \ STM32/serial_usb_vcp.c \ - drivers/bus_i2c_config.c \ - drivers/bus_spi_config.c \ drivers/serial_escserial.c \ drivers/serial_pinconfig.c \ drivers/serial_uart_pinconfig.c diff --git a/src/platform/STM32/mk/STM32H7.mk b/src/platform/STM32/mk/STM32H7.mk index ffa2bf5b6f..8302a6733b 100644 --- a/src/platform/STM32/mk/STM32H7.mk +++ b/src/platform/STM32/mk/STM32H7.mk @@ -297,8 +297,6 @@ MCU_COMMON_SRC = \ STM32/transponder_ir_io_hal.c \ STM32/camera_control_stm32.c \ drivers/adc.c \ - drivers/bus_i2c_config.c \ - drivers/bus_spi_config.c \ drivers/serial_escserial.c \ drivers/serial_pinconfig.c \ drivers/serial_uart_pinconfig.c \ @@ -321,8 +319,6 @@ SIZE_OPTIMISED_SRC += \ drivers/bus_i2c_timing.c \ STM32/bus_i2c_hal_init.c \ STM32/serial_usb_vcp.c \ - drivers/bus_i2c_config.c \ - drivers/bus_spi_config.c \ drivers/serial_escserial.c \ drivers/serial_pinconfig.c \ drivers/serial_uart_pinconfig.c diff --git a/src/platform/STM32/mk/STM32_COMMON.mk b/src/platform/STM32/mk/STM32_COMMON.mk index 8106ccf43d..fe3da3c251 100644 --- a/src/platform/STM32/mk/STM32_COMMON.mk +++ b/src/platform/STM32/mk/STM32_COMMON.mk @@ -5,11 +5,15 @@ MCU_COMMON_SRC += \ common/stm32/system.c \ common/stm32/config_flash.c \ common/stm32/bus_spi_pinconfig.c \ + drivers/bus_i2c_config.c \ + drivers/bus_spi_config.c \ common/stm32/bus_spi_hw.c \ common/stm32/io_impl.c \ common/stm32/serial_uart_hw.c SIZE_OPTIMISED_SRC += \ + drivers/bus_i2c_config.c \ + drivers/bus_spi_config.c \ common/stm32/config_flash.c \ common/stm32/bus_spi_pinconfig.c diff --git a/src/test/unit/baro_bmp280_unittest.cc b/src/test/unit/baro_bmp280_unittest.cc index cb66be7432..d63768ddef 100644 --- a/src/test/unit/baro_bmp280_unittest.cc +++ b/src/test/unit/baro_bmp280_unittest.cc @@ -163,7 +163,7 @@ void spiSetClkDivisor() { } -void spiPreinitByIO() +void ioPreinitByIO() { } diff --git a/src/test/unit/baro_bmp388_unittest.cc b/src/test/unit/baro_bmp388_unittest.cc index e07109debe..6a112109d8 100644 --- a/src/test/unit/baro_bmp388_unittest.cc +++ b/src/test/unit/baro_bmp388_unittest.cc @@ -160,7 +160,7 @@ void spiSetClkDivisor() { } -void spiPreinitByIO(IO_t) +void ioPreinitByIO() { } diff --git a/src/test/unit/baro_ms5611_unittest.cc b/src/test/unit/baro_ms5611_unittest.cc index 9896335555..fd422434d4 100644 --- a/src/test/unit/baro_ms5611_unittest.cc +++ b/src/test/unit/baro_ms5611_unittest.cc @@ -162,7 +162,7 @@ void spiSetClkDivisor() { } -void spiPreinitByIO() +void ioPreinitByIO() { } From ae8d57bb0640ba67af9319101dcff4f259f275a3 Mon Sep 17 00:00:00 2001 From: Stepandrr <50844323+Stepandrr@users.noreply.github.com> Date: Fri, 24 Jan 2025 00:56:17 +0300 Subject: [PATCH 073/244] FIX: REVISION length not more than 7 symbols (#14151) * FIX: REVISION length not more than 7 symbols * FIX: REVISION length changed to 9 symbols * FIX: Updated GIT_SHORT_REVISION_LENGTH to 9 * Revert "FIX: Updated GIT_SHORT_REVISION_LENGTH to 9" This reverts commit ec01012e4423e88d77a14409aa6e84d1d9037c5f. * Deleted REVISION cut --------- Co-authored-by: s.salov --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 8af2116909..56495baac1 100644 --- a/Makefile +++ b/Makefile @@ -139,7 +139,7 @@ endif REVISION := norevision ifeq ($(shell git diff --shortstat),) -REVISION := $(shell git log -1 --format="%h") +REVISION := $(shell git rev-parse --short=9 HEAD) endif LD_FLAGS := From 9db36f66d919536928bdbd8bbc0fe55a423f41cf Mon Sep 17 00:00:00 2001 From: Mark Haslinghuis Date: Thu, 23 Jan 2025 23:03:00 +0100 Subject: [PATCH 074/244] Fix GPS UART representation (status command) (#14193) Fix GPS UART representation --- src/main/cli/cli.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/cli/cli.c b/src/main/cli/cli.c index ce5dbddab7..2d5769b454 100644 --- a/src/main/cli/cli.c +++ b/src/main/cli/cli.c @@ -4851,7 +4851,7 @@ if (buildKey) { if (!gpsPortConfig) { cliPrint("NO PORT, "); } else { - cliPrintf("UART%d %ld (set to ", (gpsPortConfig->identifier + 1), baudRates[getGpsPortActualBaudRateIndex()]); + cliPrintf("%s %ld (set to ", serialName(gpsPortConfig->identifier, invalidName), baudRates[getGpsPortActualBaudRateIndex()]); if (gpsConfig()->autoBaud == GPS_AUTOBAUD_ON) { cliPrint("AUTO"); } else { From 2ced38e28f01075bb1dae26e73eb62b0513825f1 Mon Sep 17 00:00:00 2001 From: Petr Ledvina Date: Thu, 23 Jan 2025 23:07:57 +0100 Subject: [PATCH 075/244] GPS - simplify GPS baudrate handling (#14195) - remove unused gpsBaudRate_e - remove index from gpsInitData_t - use gpsInitData for baudrate iteration --- src/main/io/gps.c | 13 ++++++------- src/main/io/gps.h | 10 ---------- 2 files changed, 6 insertions(+), 17 deletions(-) diff --git a/src/main/io/gps.c b/src/main/io/gps.c index 4584360d07..6e652dd117 100644 --- a/src/main/io/gps.c +++ b/src/main/io/gps.c @@ -101,18 +101,17 @@ static float gpsDataFrequencyHz = 10.0f; static uint16_t currentGpsStamp = 0; // logical timer for received position update typedef struct gpsInitData_s { - uint8_t index; uint8_t baudrateIndex; // see baudRate_e const char *ubx; } gpsInitData_t; // UBX will cycle through these until valid data is received static const gpsInitData_t gpsInitData[] = { - { GPS_BAUDRATE_115200, BAUD_115200, "$PUBX,41,1,0003,0001,115200,0*1E\r\n" }, - { GPS_BAUDRATE_57600, BAUD_57600, "$PUBX,41,1,0003,0001,57600,0*2D\r\n" }, - { GPS_BAUDRATE_38400, BAUD_38400, "$PUBX,41,1,0003,0001,38400,0*26\r\n" }, - { GPS_BAUDRATE_19200, BAUD_19200, "$PUBX,41,1,0003,0001,19200,0*23\r\n" }, - { GPS_BAUDRATE_9600, BAUD_9600, "$PUBX,41,1,0003,0001,9600,0*16\r\n" } + { BAUD_115200, "$PUBX,41,1,0003,0001,115200,0*1E\r\n" }, + { BAUD_57600, "$PUBX,41,1,0003,0001,57600,0*2D\r\n" }, + { BAUD_38400, "$PUBX,41,1,0003,0001,38400,0*26\r\n" }, + { BAUD_19200, "$PUBX,41,1,0003,0001,19200,0*23\r\n" }, + { BAUD_9600, "$PUBX,41,1,0003,0001,9600,0*16\r\n" } }; #define DEFAULT_BAUD_RATE_INDEX 0 @@ -1081,7 +1080,7 @@ void gpsConfigureUblox(void) // failed to connect at that rate after five attempts // try other GPS baudrates, starting at 9600 and moving up if (gpsData.tempBaudRateIndex == 0) { - gpsData.tempBaudRateIndex = GPS_BAUDRATE_MAX; // slowest baud rate 9600 + gpsData.tempBaudRateIndex = ARRAYLEN(gpsInitData) - 1; // slowest baud rate (9600) } else { gpsData.tempBaudRateIndex--; } diff --git a/src/main/io/gps.h b/src/main/io/gps.h index fb88128900..06d6a56366 100644 --- a/src/main/io/gps.h +++ b/src/main/io/gps.h @@ -192,14 +192,6 @@ typedef enum { #define SBAS_MODE_MAX SBAS_GAGAN -typedef enum { - GPS_BAUDRATE_115200 = 0, - GPS_BAUDRATE_57600, - GPS_BAUDRATE_38400, - GPS_BAUDRATE_19200, - GPS_BAUDRATE_9600 -} gpsBaudRate_e; - typedef enum { GPS_AUTOCONFIG_OFF = 0, GPS_AUTOCONFIG_ON @@ -217,8 +209,6 @@ typedef enum { UBLOX_ACK_GOT_NACK } ubloxAckState_e; -#define GPS_BAUDRATE_MAX GPS_BAUDRATE_9600 - typedef struct gpsCoordinateDDDMMmmmm_s { int16_t dddmm; int16_t mmmm; From 6e9e9e39b6f155405243bdf5a9e9fd77d2e51f71 Mon Sep 17 00:00:00 2001 From: Mark Haslinghuis Date: Thu, 23 Jan 2025 23:36:36 +0100 Subject: [PATCH 076/244] Add make preview and extend CI coverage (#14187) Add make common --- Makefile | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 56495baac1..d7e2136d4e 100644 --- a/Makefile +++ b/Makefile @@ -127,7 +127,9 @@ include $(MAKE_SCRIPT_DIR)/config.mk HSE_VALUE ?= 8000000 CI_EXCLUDED_TARGETS := $(sort $(notdir $(patsubst %/,%,$(dir $(wildcard $(PLATFORM_DIR)/*/target/*/.exclude))))) -CI_TARGETS := $(filter-out $(CI_EXCLUDED_TARGETS), $(BASE_TARGETS)) $(filter STM32F4DISCOVERY CRAZYBEEF4SX1280 CRAZYBEEF4FR IFLIGHT_BLITZ_F722 NUCLEOF446 SPRACINGH7EXTREME SPRACINGH7RF, $(BASE_CONFIGS)) +CI_COMMON_TARGETS := STM32F4DISCOVERY CRAZYBEEF4SX1280 CRAZYBEEF4FR MATEKF405TE AIRBOTG4AIO TBS_LUCID_FC IFLIGHT_BLITZ_F722 NUCLEOF446 SPRACINGH7EXTREME SPRACINGH7RF +CI_TARGETS := $(filter-out $(CI_EXCLUDED_TARGETS), $(BASE_TARGETS)) $(filter $(CI_COMMON_TARGETS), $(BASE_CONFIGS)) +PREVIEW_TARGETS := MATEKF411 AIKONF4V2 AIRBOTG4AIO ZEEZF7V3 FOXEERF745V4_AIO KAKUTEH7 TBS_LUCID_FC SITL SPRACINGH7EXTREME SPRACINGH7RF TARGET_PLATFORM := $(notdir $(patsubst %/,%,$(subst target/$(TARGET)/,, $(dir $(wildcard $(PLATFORM_DIR)/*/target/$(TARGET)/target.mk))))) TARGET_PLATFORM_DIR := $(PLATFORM_DIR)/$(TARGET_PLATFORM) @@ -548,6 +550,9 @@ $(CONFIGS_CLEAN): ## clean_all : clean all targets clean_all: $(TARGETS_CLEAN) test_clean +## preview : build one target for each platform and execute make test +preview: $(PREVIEW_TARGETS) test + ## all_configs : Build all configs all_configs: $(BASE_CONFIGS) @@ -655,9 +660,13 @@ help: Makefile mk/tools.mk ## targets : print a list of all valid target platforms (for consumption by scripts) targets: + @echo "Platforms: $(PLATFORMS)" @echo "Valid targets: $(BASE_TARGETS)" @echo "Built targets: $(CI_TARGETS)" @echo "Default target: $(TARGET)" + @echo "CI common targets: $(CI_COMMON_TARGETS)" + @echo "CI excluded targets: $(CI_EXCLUDED_TARGETS)" + @echo "Preview targets: $(PREVIEW_TARGETS)" targets-ci-print: @echo $(CI_TARGETS) From 7ed1b4b71f36a48eca6c3682c20b6cab0a9acadf Mon Sep 17 00:00:00 2001 From: "Git bot (blckmn)" Date: Fri, 24 Jan 2025 06:25:06 +0000 Subject: [PATCH 077/244] Auto updated submodule references [24-01-2025] --- src/config | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/config b/src/config index 3f3dd34c73..be3155b97a 160000 --- a/src/config +++ b/src/config @@ -1 +1 @@ -Subproject commit 3f3dd34c7368e5ec6c2eb5634ac638d706b1d4a8 +Subproject commit be3155b97a9d33fb34e181c15de891f6f72bef5d From c2768d0409a6dd6487bc88a0952079e3048ba43a Mon Sep 17 00:00:00 2001 From: Jay Blackman Date: Fri, 24 Jan 2025 18:37:20 +1100 Subject: [PATCH 078/244] Refactoring motor to simplify implementation on other platforms (#14156) --- mk/source.mk | 2 +- src/main/blackbox/blackbox.c | 4 +- src/main/cli/cli.c | 2 - src/main/cli/settings.c | 6 +- src/main/cms/cms_menu_imu.c | 2 - src/main/cms/cms_menu_quick.c | 2 +- src/main/config/config.c | 31 +- .../drivers/accgyro/accgyro_spi_icm426xx.c | 1 - src/main/drivers/dshot.c | 15 +- src/main/drivers/dshot.h | 22 + src/main/drivers/dshot_bitbang.h | 17 +- src/main/drivers/dshot_command.c | 18 +- src/main/drivers/dshot_command.h | 4 +- src/main/drivers/light_ws2811strip.c | 4 - src/main/drivers/motor.c | 393 ++++++++++-------- src/main/drivers/motor.h | 68 +-- src/main/drivers/motor_impl.h | 31 ++ src/main/drivers/motor_types.h | 78 ++++ src/main/drivers/pwm_output.c | 51 +++ src/main/drivers/pwm_output.h | 16 +- src/main/drivers/serial_escserial.c | 4 - src/main/drivers/serial_escserial.h | 2 - src/main/fc/init.c | 12 +- src/main/flight/mixer.h | 2 +- src/main/flight/pid.c | 1 - src/main/io/serial_4way.c | 2 +- src/main/msp/msp.c | 12 +- src/main/pg/motor.c | 35 +- src/main/pg/motor.h | 25 +- src/main/sensors/esc_sensor.c | 4 +- src/platform/APM32/dshot_bitbang.c | 82 ++-- src/platform/APM32/dshot_bitbang_ddl.c | 2 +- src/platform/APM32/mk/APM32F4.mk | 6 +- src/platform/APM32/pwm_output_apm32.c | 92 ++-- src/platform/APM32/pwm_output_dshot_apm32.c | 18 +- src/platform/AT32/dshot_bitbang.c | 79 ++-- src/platform/AT32/dshot_bitbang_stdperiph.c | 3 +- src/platform/AT32/mk/AT32F4.mk | 6 +- src/platform/AT32/pwm_output_at32bsp.c | 83 ++-- src/platform/AT32/pwm_output_dshot.c | 20 +- src/platform/SIMULATOR/sitl.c | 55 +-- src/platform/STM32/dshot_bitbang.c | 89 ++-- src/platform/STM32/dshot_bitbang_ll.c | 3 +- src/platform/STM32/dshot_bitbang_stdperiph.c | 3 +- src/platform/STM32/mk/STM32F4.mk | 2 - src/platform/STM32/mk/STM32F7.mk | 3 - src/platform/STM32/mk/STM32G4.mk | 2 - src/platform/STM32/mk/STM32H5.mk | 2 - src/platform/STM32/mk/STM32H7.mk | 2 - src/platform/STM32/mk/STM32_COMMON.mk | 9 +- src/platform/STM32/pwm_output_dshot.c | 18 +- src/platform/STM32/pwm_output_dshot_hal.c | 18 +- .../STM32/{pwm_output.c => pwm_output_hw.c} | 81 ++-- src/platform/STM32/target/STM32F411/target.h | 2 +- src/platform/common/stm32/bus_spi_hw.c | 2 +- .../common/stm32}/dshot_bitbang_impl.h | 12 +- .../common/stm32/dshot_bitbang_shared.c | 68 +++ .../common/stm32}/dshot_dpwm.c | 61 ++- .../common/stm32}/dshot_dpwm.h | 15 +- .../common/stm32}/pwm_output_dshot_shared.c | 46 +- .../common/stm32}/pwm_output_dshot_shared.h | 29 +- src/test/unit/pg_unittest.cc | 6 +- 62 files changed, 975 insertions(+), 810 deletions(-) create mode 100644 src/main/drivers/motor_impl.h create mode 100644 src/main/drivers/motor_types.h create mode 100644 src/main/drivers/pwm_output.c rename src/platform/STM32/{pwm_output.c => pwm_output_hw.c} (82%) rename src/{main/drivers => platform/common/stm32}/dshot_bitbang_impl.h (96%) create mode 100644 src/platform/common/stm32/dshot_bitbang_shared.c rename src/{main/drivers => platform/common/stm32}/dshot_dpwm.c (79%) rename src/{main/drivers => platform/common/stm32}/dshot_dpwm.h (91%) rename src/{main/drivers => platform/common/stm32}/pwm_output_dshot_shared.c (89%) rename src/{main/drivers => platform/common/stm32}/pwm_output_dshot_shared.h (69%) diff --git a/mk/source.mk b/mk/source.mk index f455771251..b0606dbd6e 100644 --- a/mk/source.mk +++ b/mk/source.mk @@ -89,7 +89,6 @@ COMMON_SRC = \ cli/settings.c \ config/config.c \ drivers/dshot.c \ - drivers/dshot_dpwm.c \ drivers/dshot_command.c \ drivers/buf_writer.c \ drivers/bus.c \ @@ -110,6 +109,7 @@ COMMON_SRC = \ drivers/motor.c \ drivers/pinio.c \ drivers/pin_pull_up_down.c \ + drivers/pwm_output.c \ drivers/resource.c \ drivers/serial.c \ drivers/serial_impl.c \ diff --git a/src/main/blackbox/blackbox.c b/src/main/blackbox/blackbox.c index acebd8c2c2..ba8db32289 100644 --- a/src/main/blackbox/blackbox.c +++ b/src/main/blackbox/blackbox.c @@ -1730,8 +1730,8 @@ static bool blackboxWriteSysinfo(void) BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_GYRO_CAL_ON_FIRST_ARM, "%d", armingConfig()->gyro_cal_on_first_arm); BLACKBOX_PRINT_HEADER_LINE("airmode_activate_throttle", "%d", rxConfig()->airModeActivateThreshold); BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_SERIAL_RX_PROVIDER, "%d", rxConfig()->serialrx_provider); - BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_USE_UNSYNCED_PWM, "%d", motorConfig()->dev.useUnsyncedPwm); - BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_MOTOR_PWM_PROTOCOL, "%d", motorConfig()->dev.motorPwmProtocol); + BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_USE_UNSYNCED_PWM, "%d", motorConfig()->dev.useContinuousUpdate); + BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_MOTOR_PWM_PROTOCOL, "%d", motorConfig()->dev.motorProtocol); BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_MOTOR_PWM_RATE, "%d", motorConfig()->dev.motorPwmRate); BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_MOTOR_IDLE, "%d", motorConfig()->motorIdle); BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_DEBUG_MODE, "%d", debugMode); diff --git a/src/main/cli/cli.c b/src/main/cli/cli.c index 2d5769b454..7fb1c481d3 100644 --- a/src/main/cli/cli.c +++ b/src/main/cli/cli.c @@ -68,8 +68,6 @@ bool cliMode = false; #include "drivers/dma_reqmap.h" #include "drivers/dshot.h" #include "drivers/dshot_command.h" -#include "drivers/dshot_dpwm.h" -#include "drivers/pwm_output_dshot_shared.h" #include "drivers/camera_control_impl.h" #include "drivers/compass/compass.h" #include "drivers/display.h" diff --git a/src/main/cli/settings.c b/src/main/cli/settings.c index 3db4343db9..d9ba4c1455 100644 --- a/src/main/cli/settings.c +++ b/src/main/cli/settings.c @@ -936,10 +936,10 @@ const clivalue_t valueTable[] = { { "dshot_bitbang_timer", VAR_UINT8 | HARDWARE_VALUE | MODE_LOOKUP, .config.lookup = { TABLE_DSHOT_BITBANGED_TIMER }, PG_MOTOR_CONFIG, offsetof(motorConfig_t, dev.useDshotBitbangedTimer) }, #endif #endif // USE_DSHOT - { PARAM_NAME_USE_UNSYNCED_PWM, VAR_UINT8 | MASTER_VALUE | MODE_LOOKUP, .config.lookup = { TABLE_OFF_ON }, PG_MOTOR_CONFIG, offsetof(motorConfig_t, dev.useUnsyncedPwm) }, - { PARAM_NAME_MOTOR_PWM_PROTOCOL, VAR_UINT8 | MASTER_VALUE | MODE_LOOKUP, .config.lookup = { TABLE_MOTOR_PWM_PROTOCOL }, PG_MOTOR_CONFIG, offsetof(motorConfig_t, dev.motorPwmProtocol) }, + { PARAM_NAME_USE_UNSYNCED_PWM, VAR_UINT8 | MASTER_VALUE | MODE_LOOKUP, .config.lookup = { TABLE_OFF_ON }, PG_MOTOR_CONFIG, offsetof(motorConfig_t, dev.useContinuousUpdate) }, + { PARAM_NAME_MOTOR_PWM_PROTOCOL, VAR_UINT8 | MASTER_VALUE | MODE_LOOKUP, .config.lookup = { TABLE_MOTOR_PWM_PROTOCOL }, PG_MOTOR_CONFIG, offsetof(motorConfig_t, dev.motorProtocol) }, { PARAM_NAME_MOTOR_PWM_RATE, VAR_UINT16 | MASTER_VALUE, .config.minmaxUnsigned = { 200, 32000 }, PG_MOTOR_CONFIG, offsetof(motorConfig_t, dev.motorPwmRate) }, - { "motor_pwm_inversion", VAR_UINT8 | MASTER_VALUE | MODE_LOOKUP, .config.lookup = { TABLE_OFF_ON }, PG_MOTOR_CONFIG, offsetof(motorConfig_t, dev.motorPwmInversion) }, + { "motor_pwm_inversion", VAR_UINT8 | MASTER_VALUE | MODE_LOOKUP, .config.lookup = { TABLE_OFF_ON }, PG_MOTOR_CONFIG, offsetof(motorConfig_t, dev.motorInversion) }, { PARAM_NAME_MOTOR_POLES, VAR_UINT8 | MASTER_VALUE, .config.minmaxUnsigned = { 4, UINT8_MAX }, PG_MOTOR_CONFIG, offsetof(motorConfig_t, motorPoleCount) }, { "motor_output_reordering", VAR_UINT8 | MASTER_VALUE | MODE_ARRAY, .config.array.length = MAX_SUPPORTED_MOTORS, PG_MOTOR_CONFIG, offsetof(motorConfig_t, dev.motorOutputReordering)}, diff --git a/src/main/cms/cms_menu_imu.c b/src/main/cms/cms_menu_imu.c index aa5929bf6e..d10e386652 100644 --- a/src/main/cms/cms_menu_imu.c +++ b/src/main/cms/cms_menu_imu.c @@ -42,8 +42,6 @@ #include "config/feature.h" #include "config/simplified_tuning.h" -#include "drivers/pwm_output.h" - #include "config/config.h" #include "fc/controlrate_profile.h" #include "fc/core.h" diff --git a/src/main/cms/cms_menu_quick.c b/src/main/cms/cms_menu_quick.c index b8cda64562..0c53c094a2 100644 --- a/src/main/cms/cms_menu_quick.c +++ b/src/main/cms/cms_menu_quick.c @@ -35,7 +35,7 @@ #include "common/printf.h" #include "config/config.h" -#include "drivers/pwm_output.h" +#include "drivers/motor_types.h" #include "fc/controlrate_profile.h" #include "fc/core.h" diff --git a/src/main/config/config.c b/src/main/config/config.c index aedfdb12d1..2c8295ebcc 100644 --- a/src/main/config/config.c +++ b/src/main/config/config.c @@ -36,6 +36,7 @@ #include "config/config_eeprom.h" #include "config/feature.h" +#include "drivers/dshot.h" #include "drivers/dshot_command.h" #include "drivers/motor.h" #include "drivers/system.h" @@ -92,8 +93,6 @@ #include "config.h" -#include "drivers/dshot.h" - static bool configIsDirty; /* someone indicated that the config is modified and it is not yet saved */ static bool rebootRequired = false; // set if a config change requires a reboot to take effect @@ -277,7 +276,7 @@ static void validateAndFixConfig(void) #endif } - if (motorConfig()->dev.motorPwmProtocol == PWM_TYPE_BRUSHED) { + if (motorConfig()->dev.motorProtocol == MOTOR_PROTOCOL_BRUSHED) { featureDisableImmediate(FEATURE_3D); if (motorConfig()->mincommand < 1000) { @@ -285,7 +284,7 @@ static void validateAndFixConfig(void) } } - if ((motorConfig()->dev.motorPwmProtocol == PWM_TYPE_STANDARD) && (motorConfig()->dev.motorPwmRate > BRUSHLESS_MOTORS_PWM_RATE)) { + if ((motorConfig()->dev.motorProtocol == MOTOR_PROTOCOL_PWM ) && (motorConfig()->dev.motorPwmRate > BRUSHLESS_MOTORS_PWM_RATE)) { motorConfigMutable()->dev.motorPwmRate = BRUSHLESS_MOTORS_PWM_RATE; } @@ -381,7 +380,7 @@ static void validateAndFixConfig(void) } #if defined(USE_DSHOT_TELEMETRY) && defined(USE_DSHOT_BITBANG) - if (motorConfig()->dev.motorPwmProtocol == PWM_TYPE_PROSHOT1000 && motorConfig()->dev.useDshotTelemetry && + if (motorConfig()->dev.motorProtocol == MOTOR_PROTOCOL_PROSHOT1000 && motorConfig()->dev.useDshotTelemetry && motorConfig()->dev.useDshotBitbang == DSHOT_BITBANG_ON) { motorConfigMutable()->dev.useDshotBitbang = DSHOT_BITBANG_AUTO; } @@ -450,7 +449,7 @@ static void validateAndFixConfig(void) #if defined(USE_DSHOT) // If using DSHOT protocol disable unsynched PWM as it's meaningless if (configuredMotorProtocolDshot) { - motorConfigMutable()->dev.useUnsyncedPwm = false; + motorConfigMutable()->dev.useContinuousUpdate = false; } #if defined(USE_DSHOT_TELEMETRY) @@ -590,29 +589,29 @@ void validateAndFixGyroConfig(void) #endif && motorConfig()->dev.useDshotTelemetry ) { - if (motorConfig()->dev.motorPwmProtocol == PWM_TYPE_DSHOT600) { - motorConfigMutable()->dev.motorPwmProtocol = PWM_TYPE_DSHOT300; + if (motorConfig()->dev.motorProtocol == MOTOR_PROTOCOL_DSHOT600) { + motorConfigMutable()->dev.motorProtocol = MOTOR_PROTOCOL_DSHOT300; } if (gyro.sampleRateHz > 4000) { pidConfigMutable()->pid_process_denom = MAX(2, pidConfig()->pid_process_denom); } } #endif // USE_DSHOT && USE_PID_DENOM_CHECK - switch (motorConfig()->dev.motorPwmProtocol) { - case PWM_TYPE_STANDARD: + switch (motorConfig()->dev.motorProtocol) { + case MOTOR_PROTOCOL_PWM : motorUpdateRestriction = 1.0f / BRUSHLESS_MOTORS_PWM_RATE; break; - case PWM_TYPE_ONESHOT125: + case MOTOR_PROTOCOL_ONESHOT125: motorUpdateRestriction = 0.0005f; break; - case PWM_TYPE_ONESHOT42: + case MOTOR_PROTOCOL_ONESHOT42: motorUpdateRestriction = 0.0001f; break; #ifdef USE_DSHOT - case PWM_TYPE_DSHOT150: + case MOTOR_PROTOCOL_DSHOT150: motorUpdateRestriction = 0.000250f; break; - case PWM_TYPE_DSHOT300: + case MOTOR_PROTOCOL_DSHOT300: motorUpdateRestriction = 0.0001f; break; #endif @@ -621,11 +620,11 @@ void validateAndFixGyroConfig(void) break; } - if (motorConfig()->dev.useUnsyncedPwm) { + if (motorConfig()->dev.useContinuousUpdate) { bool configuredMotorProtocolDshot = false; checkMotorProtocolEnabled(&motorConfig()->dev, &configuredMotorProtocolDshot); // Prevent overriding the max rate of motors - if (!configuredMotorProtocolDshot && motorConfig()->dev.motorPwmProtocol != PWM_TYPE_STANDARD) { + if (!configuredMotorProtocolDshot && motorConfig()->dev.motorProtocol != MOTOR_PROTOCOL_PWM ) { const uint32_t maxEscRate = lrintf(1.0f / motorUpdateRestriction); motorConfigMutable()->dev.motorPwmRate = MIN(motorConfig()->dev.motorPwmRate, maxEscRate); } diff --git a/src/main/drivers/accgyro/accgyro_spi_icm426xx.c b/src/main/drivers/accgyro/accgyro_spi_icm426xx.c index 29dabbcb98..7d87a00383 100644 --- a/src/main/drivers/accgyro/accgyro_spi_icm426xx.c +++ b/src/main/drivers/accgyro/accgyro_spi_icm426xx.c @@ -42,7 +42,6 @@ #include "drivers/io.h" #include "drivers/sensor.h" #include "drivers/time.h" -#include "drivers/pwm_output.h" #include "sensors/gyro.h" #include "pg/gyrodev.h" diff --git a/src/main/drivers/dshot.c b/src/main/drivers/dshot.c index 623bf04290..ec73e04327 100644 --- a/src/main/drivers/dshot.c +++ b/src/main/drivers/dshot.c @@ -39,13 +39,12 @@ #include "config/feature.h" -#include "drivers/motor.h" +#include "drivers/motor_types.h" #include "drivers/timer.h" #include "drivers/dshot_command.h" #include "drivers/nvic.h" -#include "flight/mixer.h" #include "pg/rpm_filter.h" @@ -55,6 +54,8 @@ #define ERPM_PER_LSB 100.0f +FAST_DATA_ZERO_INIT uint8_t dshotMotorCount = 0; + void dshotInitEndpoints(const motorConfig_t *motorConfig, float outputLimit, float *outputLow, float *outputHigh, float *disarm, float *deadbandMotor3dHigh, float *deadbandMotor3dLow) { float outputLimitOffset = DSHOT_RANGE * (1 - outputLimit); @@ -162,7 +163,7 @@ void initDshotTelemetry(const timeUs_t looptimeUs) if (motorConfig()->dev.useDshotTelemetry) { // init LPFs for RPM data - for (int i = 0; i < getMotorCount(); i++) { + for (unsigned i = 0; i < dshotMotorCount; i++) { pt1FilterInit(&motorFreqLpf[i], pt1FilterGain(rpmFilterConfig()->rpm_filter_lpf_hz, looptimeUs * 1e-6f)); } } @@ -188,7 +189,7 @@ static uint32_t dshot_decode_eRPM_telemetry_value(uint16_t value) static void dshot_decode_telemetry_value(uint8_t motorIndex, uint32_t *pDecoded, dshotTelemetryType_t *pType) { uint16_t value = dshotTelemetryState.motorState[motorIndex].rawValue; - const unsigned motorCount = motorDeviceCount(); + const unsigned motorCount = dshotMotorCount; if (dshotTelemetryState.motorState[motorIndex].telemetryTypes == DSHOT_NORMAL_TELEMETRY_MASK) { /* Check DSHOT_TELEMETRY_TYPE_eRPM mask */ // Decode eRPM telemetry @@ -301,7 +302,7 @@ FAST_CODE_NOINLINE void updateDshotTelemetry(void) return; } - const unsigned motorCount = motorDeviceCount(); + const unsigned motorCount = dshotMotorCount; uint32_t erpmTotal = 0; uint32_t rpmSamples = 0; @@ -330,7 +331,7 @@ FAST_CODE_NOINLINE void updateDshotTelemetry(void) // update filtered rotation speed of motors for features (e.g. "RPM filter") minMotorFrequencyHz = FLT_MAX; - for (int motor = 0; motor < getMotorCount(); motor++) { + for (unsigned motor = 0; motor < dshotMotorCount; motor++) { motorFrequencyHz[motor] = pt1FilterApply(&motorFreqLpf[motor], erpmToHz * getDshotErpm(motor)); minMotorFrequencyHz = MIN(minMotorFrequencyHz, motorFrequencyHz[motor]); } @@ -371,7 +372,7 @@ bool isDshotMotorTelemetryActive(uint8_t motorIndex) bool isDshotTelemetryActive(void) { - const unsigned motorCount = motorDeviceCount(); + const unsigned motorCount = dshotMotorCount; if (motorCount) { for (unsigned i = 0; i < motorCount; i++) { if (!isDshotMotorTelemetryActive(i)) { diff --git a/src/main/drivers/dshot.h b/src/main/drivers/dshot.h index 40f592d832..19105b0659 100644 --- a/src/main/drivers/dshot.h +++ b/src/main/drivers/dshot.h @@ -26,6 +26,9 @@ #include "common/time.h" #include "pg/motor.h" +#include "drivers/motor_types.h" +// TODO: move bitbang as implementation detail of dshot (i.e. dshot should be the interface) +#include "drivers/dshot_bitbang.h" #define DSHOT_MIN_THROTTLE (48) #define DSHOT_MAX_THROTTLE (2047) @@ -90,6 +93,7 @@ uint16_t dshotConvertToExternal(float motorValue); uint16_t prepareDshotPacket(dshotProtocolControl_t *pcb); extern bool useDshotTelemetry; +extern uint8_t dshotMotorCount; #ifdef USE_DSHOT_TELEMETRY @@ -109,6 +113,22 @@ typedef struct dshotTelemetryState_s { dshotRawValueState_t rawValueState; } dshotTelemetryState_t; +#ifdef USE_DSHOT_TELEMETRY +extern uint32_t readDoneCount; + +FAST_DATA_ZERO_INIT extern uint32_t inputStampUs; + +typedef struct dshotTelemetryCycleCounters_s { + uint32_t irqAt; + uint32_t changeDirectionCompletedAt; +} dshotTelemetryCycleCounters_t; + +FAST_DATA_ZERO_INIT extern dshotTelemetryCycleCounters_t dshotDMAHandlerCycleCounters; + +#endif + +bool dshotPwmDevInit(motorDevice_t *device, const motorDevConfig_t *motorConfig); + extern dshotTelemetryState_t dshotTelemetryState; #ifdef USE_DSHOT_TELEMETRY_STATS @@ -119,6 +139,8 @@ void updateDshotTelemetryQuality(dshotTelemetryQuality_t *qualityStats, bool pac void initDshotTelemetry(const timeUs_t looptimeUs); void updateDshotTelemetry(void); +bool isDshotBitbangActive(const motorDevConfig_t *motorDevConfig); + uint16_t getDshotErpm(uint8_t motorIndex); float getDshotRpm(uint8_t motorIndex); float getDshotRpmAverage(void); diff --git a/src/main/drivers/dshot_bitbang.h b/src/main/drivers/dshot_bitbang.h index b24a8f446b..b791240815 100644 --- a/src/main/drivers/dshot_bitbang.h +++ b/src/main/drivers/dshot_bitbang.h @@ -20,13 +20,16 @@ #pragma once +#include "platform.h" + +#include "common/time.h" + +#include "drivers/dma.h" +#include "drivers/io_types.h" +#include "drivers/motor_types.h" #include "drivers/timer.h" -typedef enum { - DSHOT_BITBANG_OFF, - DSHOT_BITBANG_ON, - DSHOT_BITBANG_AUTO, -} dshotBitbangMode_e; +#include "pg/motor.h" typedef enum { DSHOT_BITBANG_STATUS_OK, @@ -35,9 +38,7 @@ typedef enum { DSHOT_BITBANG_STATUS_TOO_MANY_PORTS, } dshotBitbangStatus_e; -struct motorDevConfig_s; -struct motorDevice_s; -struct motorDevice_s *dshotBitbangDevInit(const struct motorDevConfig_s *motorConfig, uint8_t motorCount); +bool dshotBitbangDevInit(motorDevice_t *device, const motorDevConfig_t *motorConfig); dshotBitbangStatus_e dshotBitbangGetStatus(); const timerHardware_t *dshotBitbangTimerGetAllocatedByNumberAndChannel(int8_t timerNumber, uint16_t timerChannel); const resourceOwner_t *dshotBitbangTimerGetOwner(const timerHardware_t *timer); diff --git a/src/main/drivers/dshot_command.c b/src/main/drivers/dshot_command.c index a66e0454e6..90f80185d8 100644 --- a/src/main/drivers/dshot_command.c +++ b/src/main/drivers/dshot_command.c @@ -30,13 +30,9 @@ #include "drivers/io.h" #include "drivers/motor.h" #include "drivers/time.h" -#include "drivers/timer.h" #include "drivers/dshot.h" -#include "drivers/dshot_dpwm.h" -#include "drivers/pwm_output.h" - -#include "dshot_command.h" +#include "drivers/dshot_command.h" #define DSHOT_PROTOCOL_DETECTION_DELAY_MS 3000 #define DSHOT_INITIAL_DELAY_US 10000 @@ -143,8 +139,7 @@ static dshotCommandControl_t* addCommand(void) static bool allMotorsAreIdle(void) { for (unsigned i = 0; i < motorDeviceCount(); i++) { - const motorDmaOutput_t *motor = getMotorDmaOutput(i); - if (motor->protocolControl.value) { + if (!motorIsMotorIdle(i)) { return false; } } @@ -182,7 +177,7 @@ void dshotCommandWrite(uint8_t index, uint8_t motorCount, uint8_t command, dshot uint8_t repeats = 1; timeUs_t delayAfterCommandUs = DSHOT_COMMAND_DELAY_US; - motorVTable_t *vTable = motorGetVTable(); + const motorVTable_t *vTable = motorGetVTable(); switch (command) { case DSHOT_CMD_SPIN_DIRECTION_1: @@ -232,8 +227,7 @@ void dshotCommandWrite(uint8_t index, uint8_t motorCount, uint8_t command, dshot } for (uint8_t i = 0; i < motorDeviceCount(); i++) { - motorDmaOutput_t *const motor = getMotorDmaOutput(i); - motor->protocolControl.requestTelemetry = true; + vTable->requestTelemetry(i); vTable->writeInt(i, (i == index || index == ALL_MOTORS) ? command : DSHOT_CMD_MOTOR_STOP); } @@ -280,7 +274,7 @@ void dshotCommandWrite(uint8_t index, uint8_t motorCount, uint8_t command, dshot } } -uint8_t dshotCommandGetCurrent(uint8_t index) +uint8_t dshotCommandGetCurrent(unsigned index) { return commandQueue[commandQueueTail].command[index]; } @@ -290,7 +284,7 @@ uint8_t dshotCommandGetCurrent(uint8_t index) // allows the motor output to be sent, "false" means delay until next loop. So take // the example of a dshot command that needs to repeat 10 times at 1ms intervals. // If we have a 8KHz PID loop we'll end up sending the dshot command every 8th motor output. -FAST_CODE_NOINLINE bool dshotCommandOutputIsEnabled(uint8_t motorCount) +FAST_CODE_NOINLINE bool dshotCommandOutputIsEnabled(unsigned motorCount) { UNUSED(motorCount); diff --git a/src/main/drivers/dshot_command.h b/src/main/drivers/dshot_command.h index 9ade0d459f..aa9b0d2b16 100644 --- a/src/main/drivers/dshot_command.h +++ b/src/main/drivers/dshot_command.h @@ -71,6 +71,6 @@ void dshotCommandWrite(uint8_t index, uint8_t motorCount, uint8_t command, dshot void dshotSetPidLoopTime(uint32_t pidLoopTime); bool dshotCommandQueueEmpty(void); bool dshotCommandIsProcessing(void); -uint8_t dshotCommandGetCurrent(uint8_t index); -bool dshotCommandOutputIsEnabled(uint8_t motorCount); +uint8_t dshotCommandGetCurrent(unsigned index); +bool dshotCommandOutputIsEnabled(unsigned motorCount); bool dshotStreamingCommandsAreEnabled(void); diff --git a/src/main/drivers/light_ws2811strip.c b/src/main/drivers/light_ws2811strip.c index bbd59e2ba2..9547eda9c9 100644 --- a/src/main/drivers/light_ws2811strip.c +++ b/src/main/drivers/light_ws2811strip.c @@ -60,11 +60,7 @@ #define WS2811_DMA_BUF_CACHE_ALIGN_LENGTH (WS2811_DMA_BUF_CACHE_ALIGN_BYTES / sizeof(uint32_t)) DMA_RW_AXI __attribute__((aligned(32))) uint32_t ledStripDMABuffer[WS2811_DMA_BUF_CACHE_ALIGN_LENGTH]; #else -#if defined(STM32F7) FAST_DATA_ZERO_INIT uint32_t ledStripDMABuffer[WS2811_DMA_BUFFER_SIZE]; -#else -uint32_t ledStripDMABuffer[WS2811_DMA_BUFFER_SIZE]; -#endif #endif static ioTag_t ledStripIoTag; diff --git a/src/main/drivers/motor.c b/src/main/drivers/motor.c index 62d472e7ed..124554928e 100644 --- a/src/main/drivers/motor.c +++ b/src/main/drivers/motor.c @@ -32,10 +32,10 @@ #include "config/feature.h" -#include "drivers/dshot.h" // for DSHOT_ constants in initEscEndpoints; may be gone in the future -#include "drivers/dshot_bitbang.h" -#include "drivers/dshot_dpwm.h" -#include "drivers/pwm_output.h" // for PWM_TYPE_* and others +#include "drivers/dshot.h" +#include "drivers/dshot_bitbang.h" // TODO: bitbang should be behind the veil of dshot (it is an implementation) +#include "drivers/pwm_output.h" + #include "drivers/time.h" #include "fc/rc_controls.h" // for flight3DConfig_t @@ -44,7 +44,7 @@ #include "motor.h" -static FAST_DATA_ZERO_INIT motorDevice_t *motorDevice; +static FAST_DATA_ZERO_INIT motorDevice_t motorDevice; static bool motorProtocolEnabled = false; static bool motorProtocolDshot = false; @@ -52,16 +52,16 @@ static bool motorProtocolDshot = false; void motorShutdown(void) { uint32_t shutdownDelayUs = 1500; - motorDevice->vTable.shutdown(); - motorDevice->enabled = false; - motorDevice->motorEnableTimeMs = 0; - motorDevice->initialized = false; + motorDevice.vTable->shutdown(); + motorDevice.enabled = false; + motorDevice.motorEnableTimeMs = 0; + motorDevice.initialized = false; - switch (motorConfig()->dev.motorPwmProtocol) { - case PWM_TYPE_STANDARD: - case PWM_TYPE_ONESHOT125: - case PWM_TYPE_ONESHOT42: - case PWM_TYPE_MULTISHOT: + switch (motorConfig()->dev.motorProtocol) { + case MOTOR_PROTOCOL_PWM : + case MOTOR_PROTOCOL_ONESHOT125: + case MOTOR_PROTOCOL_ONESHOT42: + case MOTOR_PROTOCOL_MULTISHOT: // Delay 500ms will disarm esc which can prevent motor spin while reboot shutdownDelayUs += 500 * 1000; break; @@ -75,31 +75,33 @@ void motorShutdown(void) void motorWriteAll(float *values) { #ifdef USE_PWM_OUTPUT - if (motorDevice->enabled) { + if (motorDevice.enabled) { #ifdef USE_DSHOT_BITBANG if (isDshotBitbangActive(&motorConfig()->dev)) { // Initialise the output buffers - if (motorDevice->vTable.updateInit) { - motorDevice->vTable.updateInit(); + if (motorDevice.vTable->updateInit) { + motorDevice.vTable->updateInit(); } // Update the motor data - for (int i = 0; i < motorDevice->count; i++) { - motorDevice->vTable.write(i, values[i]); + for (int i = 0; i < motorDevice.count; i++) { + motorDevice.vTable->write(i, values[i]); } // Don't attempt to write commands to the motors if telemetry is still being received - if (motorDevice->vTable.telemetryWait) { - (void)motorDevice->vTable.telemetryWait(); + if (motorDevice.vTable->telemetryWait) { + (void)motorDevice.vTable->telemetryWait(); } // Trigger the transmission of the motor data - motorDevice->vTable.updateComplete(); + motorDevice.vTable->updateComplete(); // Perform the decode of the last data received // New data will be received once the send of motor data, triggered above, completes #if defined(USE_DSHOT) && defined(USE_DSHOT_TELEMETRY) - motorDevice->vTable.decodeTelemetry(); + if (motorDevice.vTable->decodeTelemetry) { + motorDevice.vTable->decodeTelemetry(); + } #endif } else #endif @@ -107,17 +109,16 @@ void motorWriteAll(float *values) // Perform the decode of the last data received // New data will be received once the send of motor data, triggered above, completes #if defined(USE_DSHOT) && defined(USE_DSHOT_TELEMETRY) - motorDevice->vTable.decodeTelemetry(); + motorDevice.vTable->decodeTelemetry(); #endif // Update the motor data - for (int i = 0; i < motorDevice->count; i++) { - motorDevice->vTable.write(i, values[i]); + for (int i = 0; i < motorDevice.count; i++) { + motorDevice.vTable->write(i, values[i]); } // Trigger the transmission of the motor data - motorDevice->vTable.updateComplete(); - + motorDevice.vTable->updateComplete(); } } #else @@ -125,32 +126,25 @@ void motorWriteAll(float *values) #endif } +void motorRequestTelemetry(unsigned index) +{ + if (index >= motorDevice.count) { + return; + } + + if (motorDevice.vTable->requestTelemetry) { + motorDevice.vTable->requestTelemetry(index); + } +} + unsigned motorDeviceCount(void) { - return motorDevice->count; + return motorDevice.count; } -motorVTable_t *motorGetVTable(void) +const motorVTable_t *motorGetVTable(void) { - return &motorDevice->vTable; -} - -// This is not motor generic anymore; should be moved to analog pwm module -static void analogInitEndpoints(const motorConfig_t *motorConfig, float outputLimit, float *outputLow, float *outputHigh, float *disarm, float *deadbandMotor3dHigh, float *deadbandMotor3dLow) -{ - if (featureIsEnabled(FEATURE_3D)) { - float outputLimitOffset = (flight3DConfig()->limit3d_high - flight3DConfig()->limit3d_low) * (1 - outputLimit) / 2; - *disarm = flight3DConfig()->neutral3d; - *outputLow = flight3DConfig()->limit3d_low + outputLimitOffset; - *outputHigh = flight3DConfig()->limit3d_high - outputLimitOffset; - *deadbandMotor3dHigh = flight3DConfig()->deadband3d_high; - *deadbandMotor3dLow = flight3DConfig()->deadband3d_low; - } else { - *disarm = motorConfig->mincommand; - const float minThrottle = motorConfig->mincommand + motorConfig->motorIdle * 0.1f; - *outputLow = minThrottle; - *outputHigh = motorConfig->maxthrottle - ((motorConfig->maxthrottle - minThrottle) * (1 - outputLimit)); - } + return motorDevice.vTable; } bool checkMotorProtocolEnabled(const motorDevConfig_t *motorDevConfig, bool *isProtocolDshot) @@ -158,20 +152,20 @@ bool checkMotorProtocolEnabled(const motorDevConfig_t *motorDevConfig, bool *isP bool enabled = false; bool isDshot = false; - switch (motorDevConfig->motorPwmProtocol) { - case PWM_TYPE_STANDARD: - case PWM_TYPE_ONESHOT125: - case PWM_TYPE_ONESHOT42: - case PWM_TYPE_MULTISHOT: - case PWM_TYPE_BRUSHED: + switch (motorDevConfig->motorProtocol) { + case MOTOR_PROTOCOL_PWM : + case MOTOR_PROTOCOL_ONESHOT125: + case MOTOR_PROTOCOL_ONESHOT42: + case MOTOR_PROTOCOL_MULTISHOT: + case MOTOR_PROTOCOL_BRUSHED: enabled = true; break; #ifdef USE_DSHOT - case PWM_TYPE_DSHOT150: - case PWM_TYPE_DSHOT300: - case PWM_TYPE_DSHOT600: - case PWM_TYPE_PROSHOT1000: + case MOTOR_PROTOCOL_DSHOT150: + case MOTOR_PROTOCOL_DSHOT300: + case MOTOR_PROTOCOL_DSHOT600: + case MOTOR_PROTOCOL_PROSHOT1000: enabled = true; isDshot = true; break; @@ -187,6 +181,29 @@ bool checkMotorProtocolEnabled(const motorDevConfig_t *motorDevConfig, bool *isP return enabled; } +motorProtocolFamily_e motorGetProtocolFamily(void) +{ + switch (motorConfig()->dev.motorProtocol) { +#ifdef USE_PWMOUTPUT + case MOTOR_PROTOCOL_PWM : + case MOTOR_PROTOCOL_ONESHOT125: + case MOTOR_PROTOCOL_ONESHOT42: + case MOTOR_PROTOCOL_MULTISHOT: + case MOTOR_PROTOCOL_BRUSHED: + return MOTOR_PROTOCOL_FAMILY_PWM; +#endif +#ifdef USE_DSHOT + case MOTOR_PROTOCOL_DSHOT150: + case MOTOR_PROTOCOL_DSHOT300: + case MOTOR_PROTOCOL_DSHOT600: + case MOTOR_PROTOCOL_PROSHOT1000: + return MOTOR_PROTOCOL_FAMILY_DSHOT; +#endif + default: + return MOTOR_PROTOCOL_FAMILY_UNKNOWN; + } +} + static void checkMotorProtocol(const motorDevConfig_t *motorDevConfig) { motorProtocolEnabled = checkMotorProtocolEnabled(motorDevConfig, &motorProtocolDshot); @@ -198,32 +215,154 @@ void motorInitEndpoints(const motorConfig_t *motorConfig, float outputLimit, flo checkMotorProtocol(&motorConfig->dev); if (isMotorProtocolEnabled()) { - if (!isMotorProtocolDshot()) { + switch (motorGetProtocolFamily()) { +#ifdef USE_PWM_OUTPUT + case MOTOR_PROTOCOL_FAMILY_PWM: analogInitEndpoints(motorConfig, outputLimit, outputLow, outputHigh, disarm, deadbandMotor3dHigh, deadbandMotor3dLow); - } -#ifdef USE_DSHOT - else { - dshotInitEndpoints(motorConfig, outputLimit, outputLow, outputHigh, disarm, deadbandMotor3dHigh, deadbandMotor3dLow); - } + break; #endif +#ifdef USE_DSHOT + case MOTOR_PROTOCOL_FAMILY_DSHOT: + dshotInitEndpoints(motorConfig, outputLimit, outputLow, outputHigh, disarm, deadbandMotor3dHigh, deadbandMotor3dLow); + break; +#endif + default: + // TODO: perhaps a failure mode here? + break; + } } } float motorConvertFromExternal(uint16_t externalValue) { - return motorDevice->vTable.convertExternalToMotor(externalValue); + return motorDevice.vTable->convertExternalToMotor(externalValue); } uint16_t motorConvertToExternal(float motorValue) { - return motorDevice->vTable.convertMotorToExternal(motorValue); + return motorDevice.vTable->convertMotorToExternal(motorValue); } void motorPostInit(void) { - motorDevice->vTable.postInit(); + if (motorDevice.vTable->postInit) { + motorDevice.vTable->postInit(); + } } +bool isMotorProtocolEnabled(void) +{ + return motorProtocolEnabled; +} + +bool isMotorProtocolDshot(void) +{ + return motorProtocolDshot; +} + +bool isMotorProtocolBidirDshot(void) +{ + return isMotorProtocolDshot() && useDshotTelemetry; +} + +void motorNullDevInit(motorDevice_t *device); + +void motorDevInit(unsigned motorCount) +{ +#if defined(USE_PWM_OUTPUT) || defined(USE_DSHOT) + const motorDevConfig_t *motorDevConfig = &motorConfig()->dev; +#endif + +#if defined(USE_PWM_OUTPUT) + uint16_t idlePulse = motorConfig()->mincommand; + if (featureIsEnabled(FEATURE_3D)) { + idlePulse = flight3DConfig()->neutral3d; + } + if (motorConfig()->dev.motorProtocol == MOTOR_PROTOCOL_BRUSHED) { + idlePulse = 0; // brushed motors + } +#endif + + bool success = false; + motorDevice.count = motorCount; + if (isMotorProtocolEnabled()) { + do { + if (!isMotorProtocolDshot()) { +#ifdef USE_PWM_OUTPUT + success = motorPwmDevInit(&motorDevice, motorDevConfig, idlePulse); +#endif + break; + } +#ifdef USE_DSHOT +#ifdef USE_DSHOT_BITBANG + if (isDshotBitbangActive(motorDevConfig)) { + success = dshotBitbangDevInit(&motorDevice, motorDevConfig); + break; + } +#endif + success = dshotPwmDevInit(&motorDevice, motorDevConfig); +#endif + } while(0); + } + + // if the VTable has been populated, the device is initialized. + if (success) { + motorDevice.initialized = true; + motorDevice.motorEnableTimeMs = 0; + motorDevice.enabled = false; + } else { + motorNullDevInit(&motorDevice); + } +} + +void motorDisable(void) +{ + motorDevice.vTable->disable(); + motorDevice.enabled = false; + motorDevice.motorEnableTimeMs = 0; +} + +void motorEnable(void) +{ + if (motorDevice.initialized && motorDevice.vTable->enable()) { + motorDevice.enabled = true; + motorDevice.motorEnableTimeMs = millis(); + } +} + +float motorEstimateMaxRpm(void) +{ + // Empirical testing found this relationship between estimated max RPM without props attached + // (unloaded) and measured max RPM with props attached (loaded), independent from prop size + float unloadedMaxRpm = 0.01f * getBatteryVoltage() * motorConfig()->kv; + float loadDerating = -5.44e-6f * unloadedMaxRpm + 0.944f; + + return unloadedMaxRpm * loadDerating; +} + +bool motorIsEnabled(void) +{ + return motorDevice.enabled; +} + +bool motorIsMotorEnabled(unsigned index) +{ + return motorDevice.vTable->isMotorEnabled(index); +} + +bool motorIsMotorIdle(unsigned index) +{ + return motorDevice.vTable->isMotorIdle ? motorDevice.vTable->isMotorIdle(index) : false; +} + +#ifdef USE_DSHOT +timeMs_t motorGetMotorEnableTimeMs(void) +{ + return motorDevice.motorEnableTimeMs; +} +#endif + +/* functions below for empty methods and no active motors */ void motorPostInitNull(void) { } @@ -237,10 +376,9 @@ static void motorDisableNull(void) { } -static bool motorIsEnabledNull(uint8_t index) +static bool motorIsEnabledNull(unsigned index) { UNUSED(index); - return false; } @@ -293,120 +431,15 @@ static const motorVTable_t motorNullVTable = { .convertExternalToMotor = motorConvertFromExternalNull, .convertMotorToExternal = motorConvertToExternalNull, .shutdown = motorShutdownNull, + .requestTelemetry = NULL, + .isMotorIdle = NULL, }; -static motorDevice_t motorNullDevice = { - .initialized = false, - .enabled = false, -}; - -bool isMotorProtocolEnabled(void) +void motorNullDevInit(motorDevice_t *device) { - return motorProtocolEnabled; + device->vTable = &motorNullVTable; + device->count = 0; } -bool isMotorProtocolDshot(void) -{ - return motorProtocolDshot; -} -bool isMotorProtocolBidirDshot(void) -{ - return isMotorProtocolDshot() && useDshotTelemetry; -} - -void motorDevInit(const motorDevConfig_t *motorDevConfig, uint16_t idlePulse, uint8_t motorCount) -{ -#if defined(USE_PWM_OUTPUT) || defined(USE_DSHOT) - bool useUnsyncedPwm = motorDevConfig->useUnsyncedPwm; -#else - UNUSED(idlePulse); - UNUSED(motorDevConfig); -#endif - - if (isMotorProtocolEnabled()) { - do { - if (!isMotorProtocolDshot()) { -#ifdef USE_PWM_OUTPUT - motorDevice = motorPwmDevInit(motorDevConfig, idlePulse, motorCount, useUnsyncedPwm); -#endif - break; - } -#ifdef USE_DSHOT -#ifdef USE_DSHOT_BITBANG - if (isDshotBitbangActive(motorDevConfig)) { - motorDevice = dshotBitbangDevInit(motorDevConfig, motorCount); - break; - } -#endif - motorDevice = dshotPwmDevInit(motorDevConfig, idlePulse, motorCount, useUnsyncedPwm); -#endif - } while(0); - } - - if (motorDevice) { - motorDevice->count = motorCount; - motorDevice->initialized = true; - motorDevice->motorEnableTimeMs = 0; - motorDevice->enabled = false; - } else { - motorNullDevice.vTable = motorNullVTable; - motorDevice = &motorNullDevice; - } -} - -void motorDisable(void) -{ - motorDevice->vTable.disable(); - motorDevice->enabled = false; - motorDevice->motorEnableTimeMs = 0; -} - -void motorEnable(void) -{ - if (motorDevice->initialized && motorDevice->vTable.enable()) { - motorDevice->enabled = true; - motorDevice->motorEnableTimeMs = millis(); - } -} - -float motorEstimateMaxRpm(void) -{ - // Empirical testing found this relationship between estimated max RPM without props attached - // (unloaded) and measured max RPM with props attached (loaded), independent from prop size - float unloadedMaxRpm = 0.01f * getBatteryVoltage() * motorConfig()->kv; - float loadDerating = -5.44e-6f * unloadedMaxRpm + 0.944f; - - return unloadedMaxRpm * loadDerating; -} - -bool motorIsEnabled(void) -{ - return motorDevice->enabled; -} - -bool motorIsMotorEnabled(uint8_t index) -{ - return motorDevice->vTable.isMotorEnabled(index); -} - -#ifdef USE_DSHOT -timeMs_t motorGetMotorEnableTimeMs(void) -{ - return motorDevice->motorEnableTimeMs; -} -#endif - -#ifdef USE_DSHOT_BITBANG -bool isDshotBitbangActive(const motorDevConfig_t *motorDevConfig) -{ -#if defined(STM32F4) || defined(APM32F4) - return motorDevConfig->useDshotBitbang == DSHOT_BITBANG_ON || - (motorDevConfig->useDshotBitbang == DSHOT_BITBANG_AUTO && motorDevConfig->useDshotTelemetry && motorDevConfig->motorPwmProtocol != PWM_TYPE_PROSHOT1000); -#else - return motorDevConfig->useDshotBitbang == DSHOT_BITBANG_ON || - (motorDevConfig->useDshotBitbang == DSHOT_BITBANG_AUTO && motorDevConfig->motorPwmProtocol != PWM_TYPE_PROSHOT1000); -#endif -} -#endif #endif // USE_MOTOR diff --git a/src/main/drivers/motor.h b/src/main/drivers/motor.h index 2203ce7c2b..d43f430446 100644 --- a/src/main/drivers/motor.h +++ b/src/main/drivers/motor.h @@ -26,67 +26,24 @@ #include "pg/motor.h" -typedef enum { - PWM_TYPE_STANDARD = 0, - PWM_TYPE_ONESHOT125, - PWM_TYPE_ONESHOT42, - PWM_TYPE_MULTISHOT, - PWM_TYPE_BRUSHED, - PWM_TYPE_DSHOT150, - PWM_TYPE_DSHOT300, - PWM_TYPE_DSHOT600, -// PWM_TYPE_DSHOT1200, removed - PWM_TYPE_PROSHOT1000, - PWM_TYPE_DISABLED, - PWM_TYPE_MAX -} motorPwmProtocolTypes_e; +#include "drivers/motor_types.h" -typedef struct motorVTable_s { - // Common - void (*postInit)(void); - float (*convertExternalToMotor)(uint16_t externalValue); - uint16_t (*convertMotorToExternal)(float motorValue); - bool (*enable)(void); - void (*disable)(void); - bool (*isMotorEnabled)(uint8_t index); - bool (*telemetryWait)(void); - bool (*decodeTelemetry)(void); - void (*updateInit)(void); - void (*write)(uint8_t index, float value); - void (*writeInt)(uint8_t index, uint16_t value); - void (*updateComplete)(void); - void (*shutdown)(void); - - // Digital commands - -} motorVTable_t; - -typedef struct motorDevice_s { - motorVTable_t vTable; - uint8_t count; - bool initialized; - bool enabled; - timeMs_t motorEnableTimeMs; -} motorDevice_t; - -void motorPostInitNull(); -void motorWriteNull(uint8_t index, float value); -bool motorDecodeTelemetryNull(void); -void motorUpdateCompleteNull(void); - -void motorPostInit(); +void motorPostInit(void); void motorWriteAll(float *values); +void motorRequestTelemetry(unsigned index); void motorInitEndpoints(const motorConfig_t *motorConfig, float outputLimit, float *outputLow, float *outputHigh, float *disarm, float *deadbandMotor3DHigh, float *deadbandMotor3DLow); float motorConvertFromExternal(uint16_t externalValue); uint16_t motorConvertToExternal(float motorValue); -struct motorDevConfig_s; // XXX Shouldn't be needed once pwm_output* is really cleaned up. -void motorDevInit(const struct motorDevConfig_s *motorConfig, uint16_t idlePulse, uint8_t motorCount); +void motorDevInit(unsigned motorCount); unsigned motorDeviceCount(void); -motorVTable_t *motorGetVTable(void); +const motorVTable_t *motorGetVTable(void); bool checkMotorProtocolEnabled(const motorDevConfig_t *motorConfig, bool *protocolIsDshot); + +motorProtocolFamily_e motorGetProtocolFamily(void); + bool isMotorProtocolDshot(void); bool isMotorProtocolBidirDshot(void); bool isMotorProtocolEnabled(void); @@ -95,12 +52,7 @@ void motorDisable(void); void motorEnable(void); float motorEstimateMaxRpm(void); bool motorIsEnabled(void); -bool motorIsMotorEnabled(uint8_t index); +bool motorIsMotorEnabled(unsigned index); +bool motorIsMotorIdle(unsigned index); timeMs_t motorGetMotorEnableTimeMs(void); void motorShutdown(void); // Replaces stopPwmAllMotors - -#ifdef USE_DSHOT_BITBANG -struct motorDevConfig_s; -typedef struct motorDevConfig_s motorDevConfig_t; -bool isDshotBitbangActive(const motorDevConfig_t *motorConfig); -#endif diff --git a/src/main/drivers/motor_impl.h b/src/main/drivers/motor_impl.h new file mode 100644 index 0000000000..c5defbc451 --- /dev/null +++ b/src/main/drivers/motor_impl.h @@ -0,0 +1,31 @@ +/* + * This file is part of Betaflight. + * + * Betaflight is free software. You can redistribute this software + * and/or modify this software under the terms of the GNU General + * Public License as published by the Free Software Foundation, + * either version 3 of the License, or (at your option) any later + * version. + * + * Betaflight is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * See the GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this software. + * + * If not, see . + */ + +#pragma once + +#include "drivers/motor_types.h" + +void motorPostInitNull(void); +void motorWriteNull(uint8_t index, float value); +bool motorDecodeTelemetryNull(void); +void motorUpdateCompleteNull(void); + +void motorNullDevInit(motorDevice_t *device); diff --git a/src/main/drivers/motor_types.h b/src/main/drivers/motor_types.h new file mode 100644 index 0000000000..c70fcee0b0 --- /dev/null +++ b/src/main/drivers/motor_types.h @@ -0,0 +1,78 @@ +/* + * This file is part of Betaflight. + * + * Betaflight is free software. You can redistribute this software + * and/or modify this software under the terms of the GNU General + * Public License as published by the Free Software Foundation, + * either version 3 of the License, or (at your option) any later + * version. + * + * Betaflight is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * See the GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this software. + * + * If not, see . + */ + +#pragma once + +#include "common/time.h" + +#define ALL_MOTORS 255 +#define MOTOR_OUTPUT_LIMIT_PERCENT_MIN 1 +#define MOTOR_OUTPUT_LIMIT_PERCENT_MAX 100 + +typedef enum { + MOTOR_PROTOCOL_FAMILY_UNKNOWN = 0, + MOTOR_PROTOCOL_FAMILY_PWM, + MOTOR_PROTOCOL_FAMILY_DSHOT, +} motorProtocolFamily_e; + +typedef enum { + MOTOR_PROTOCOL_PWM = 0, + MOTOR_PROTOCOL_ONESHOT125, + MOTOR_PROTOCOL_ONESHOT42, + MOTOR_PROTOCOL_MULTISHOT, + MOTOR_PROTOCOL_BRUSHED, + MOTOR_PROTOCOL_DSHOT150, + MOTOR_PROTOCOL_DSHOT300, + MOTOR_PROTOCOL_DSHOT600, +/* MOTOR_PROTOCOL_DSHOT1200, removed */ + MOTOR_PROTOCOL_PROSHOT1000, + MOTOR_PROTOCOL_DISABLED, + MOTOR_PROTOCOL_MAX +} motorProtocolTypes_e; + +typedef struct motorVTable_s { + // Common + void (*postInit)(void); + float (*convertExternalToMotor)(uint16_t externalValue); + uint16_t (*convertMotorToExternal)(float motorValue); + bool (*enable)(void); + void (*disable)(void); + bool (*isMotorEnabled)(unsigned index); + bool (*telemetryWait)(void); + bool (*decodeTelemetry)(void); + void (*updateInit)(void); + void (*write)(uint8_t index, float value); + void (*writeInt)(uint8_t index, uint16_t value); + void (*updateComplete)(void); + void (*shutdown)(void); + bool (*isMotorIdle)(unsigned index); + + // Digital commands + void (*requestTelemetry)(unsigned index); +} motorVTable_t; + +typedef struct motorDevice_s { + const motorVTable_t *vTable; + uint8_t count; + bool initialized; + bool enabled; + timeMs_t motorEnableTimeMs; +} motorDevice_t; diff --git a/src/main/drivers/pwm_output.c b/src/main/drivers/pwm_output.c new file mode 100644 index 0000000000..813b97e856 --- /dev/null +++ b/src/main/drivers/pwm_output.c @@ -0,0 +1,51 @@ +/* + * This file is part of Betaflight. + * + * Betaflight is free software. You can redistribute this software + * and/or modify this software under the terms of the GNU General + * Public License as published by the Free Software Foundation, + * either version 3 of the License, or (at your option) any later + * version. + * + * Betaflight is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * See the GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this software. + * + * If not, see . + */ + +#include "platform.h" + +#include "pg/motor.h" +#include "fc/rc_controls.h" // for flight3DConfig_t +#include "config/feature.h" +#include "drivers/pwm_output.h" + +#if defined(USE_PWM_OUTPUT) && defined(USE_MOTOR) + +FAST_DATA_ZERO_INIT pwmOutputPort_t motors[MAX_SUPPORTED_MOTORS]; +FAST_DATA_ZERO_INIT uint8_t pwmMotorCount; + +void analogInitEndpoints(const motorConfig_t *motorConfig, float outputLimit, float *outputLow, float *outputHigh, float *disarm, float *deadbandMotor3dHigh, float *deadbandMotor3dLow) +{ + if (featureIsEnabled(FEATURE_3D)) { + const float outputLimitOffset = (flight3DConfig()->limit3d_high - flight3DConfig()->limit3d_low) * (1 - outputLimit) / 2; + *disarm = flight3DConfig()->neutral3d; + *outputLow = flight3DConfig()->limit3d_low + outputLimitOffset; + *outputHigh = flight3DConfig()->limit3d_high - outputLimitOffset; + *deadbandMotor3dHigh = flight3DConfig()->deadband3d_high; + *deadbandMotor3dLow = flight3DConfig()->deadband3d_low; + } else { + *disarm = motorConfig->mincommand; + const float minThrottle = motorConfig->mincommand + motorConfig->motorIdle * 0.1f; + *outputLow = minThrottle; + *outputHigh = motorConfig->maxthrottle - ((motorConfig->maxthrottle - minThrottle) * (1 - outputLimit)); + } +} + +#endif diff --git a/src/main/drivers/pwm_output.h b/src/main/drivers/pwm_output.h index 21b7de0078..644e2415cc 100644 --- a/src/main/drivers/pwm_output.h +++ b/src/main/drivers/pwm_output.h @@ -26,19 +26,14 @@ #include "drivers/dma.h" #include "drivers/io_types.h" -#include "drivers/motor.h" +#include "drivers/motor_types.h" #include "drivers/timer.h" -#define BRUSHED_MOTORS_PWM_RATE 16000 -#define BRUSHLESS_MOTORS_PWM_RATE 480 - -#define ALL_MOTORS 255 - -#define MOTOR_OUTPUT_LIMIT_PERCENT_MIN 1 -#define MOTOR_OUTPUT_LIMIT_PERCENT_MAX 100 +#include "pg/motor.h" #define PWM_TIMER_1MHZ MHZ_TO_HZ(1) +// TODO: move the implementation defintions to impl header (platform) struct timerHardware_s; typedef struct { @@ -56,9 +51,9 @@ typedef struct { } pwmOutputPort_t; extern FAST_DATA_ZERO_INIT pwmOutputPort_t motors[MAX_SUPPORTED_MOTORS]; +extern FAST_DATA_ZERO_INIT uint8_t pwmMotorCount; -struct motorDevConfig_s; -motorDevice_t *motorPwmDevInit(const struct motorDevConfig_s *motorDevConfig, uint16_t idlePulse, uint8_t motorCount, bool useUnsyncedPwm); +bool motorPwmDevInit(motorDevice_t *device, const motorDevConfig_t *motorDevConfig, uint16_t idlePulse); typedef struct servoDevConfig_s { // PWM values, in milliseconds, common range is 1000-2000 (1ms to 2ms) @@ -77,3 +72,4 @@ void pwmWriteServo(uint8_t index, float value); pwmOutputPort_t *pwmGetMotors(void); bool pwmIsSynced(void); +void analogInitEndpoints(const motorConfig_t *motorConfig, float outputLimit, float *outputLow, float *outputHigh, float *disarm, float *deadbandMotor3dHigh, float *deadbandMotor3dLow); diff --git a/src/main/drivers/serial_escserial.c b/src/main/drivers/serial_escserial.c index 369851d05d..b0d7424a1b 100644 --- a/src/main/drivers/serial_escserial.c +++ b/src/main/drivers/serial_escserial.c @@ -181,11 +181,7 @@ static void escSerialGPIOConfig(const timerHardware_t *timhw, ioConfig_t cfg) } IOInit(IOGetByTag(tag), OWNER_MOTOR, 0); -#if defined(STM32F7) || defined(STM32H7) IOConfigGPIOAF(IOGetByTag(tag), cfg, timhw->alternateFunction); -#else - IOConfigGPIO(IOGetByTag(tag), cfg); -#endif } static void escSerialInputPortConfig(const timerHardware_t *timerHardwarePtr) diff --git a/src/main/drivers/serial_escserial.h b/src/main/drivers/serial_escserial.h index ca1448409b..1efa9b808b 100644 --- a/src/main/drivers/serial_escserial.h +++ b/src/main/drivers/serial_escserial.h @@ -20,8 +20,6 @@ #pragma once -#include "drivers/pwm_output.h" - #define ESCSERIAL_BUFFER_SIZE 1024 typedef enum { diff --git a/src/main/fc/init.c b/src/main/fc/init.c index becf43fa18..8e1646411b 100644 --- a/src/main/fc/init.c +++ b/src/main/fc/init.c @@ -64,7 +64,6 @@ #include "drivers/nvic.h" #include "drivers/persistent.h" #include "drivers/pin_pull_up_down.h" -#include "drivers/pwm_output.h" #include "drivers/rx/rx_pwm.h" #include "drivers/sensor.h" #include "drivers/serial.h" @@ -541,21 +540,12 @@ void init(void) mixerInit(mixerConfig()->mixerMode); - uint16_t idlePulse = motorConfig()->mincommand; - if (featureIsEnabled(FEATURE_3D)) { - idlePulse = flight3DConfig()->neutral3d; - } - if (motorConfig()->dev.motorPwmProtocol == PWM_TYPE_BRUSHED) { - idlePulse = 0; // brushed motors - } #ifdef USE_MOTOR /* Motors needs to be initialized soon as posible because hardware initialization * may send spurious pulses to esc's causing their early initialization. Also ppm * receiver may share timer with motors so motors MUST be initialized here. */ - motorDevInit(&motorConfig()->dev, idlePulse, getMotorCount()); + motorDevInit(getMotorCount()); systemState |= SYSTEM_STATE_MOTORS_READY; -#else - UNUSED(idlePulse); #endif if (0) {} diff --git a/src/main/flight/mixer.h b/src/main/flight/mixer.h index 7371f9bdee..c6e1afa326 100644 --- a/src/main/flight/mixer.h +++ b/src/main/flight/mixer.h @@ -30,7 +30,7 @@ #include "pg/pg.h" #include "drivers/io_types.h" -#include "drivers/pwm_output.h" +#include "drivers/motor.h" #define QUAD_MOTOR_COUNT 4 diff --git a/src/main/flight/pid.c b/src/main/flight/pid.c index 071c1feaf2..2635692f1a 100644 --- a/src/main/flight/pid.c +++ b/src/main/flight/pid.c @@ -36,7 +36,6 @@ #include "config/config_reset.h" #include "config/simplified_tuning.h" -#include "drivers/pwm_output.h" #include "drivers/sound_beeper.h" #include "drivers/time.h" diff --git a/src/main/io/serial_4way.c b/src/main/io/serial_4way.c index 6482febc27..5dda23f3b9 100644 --- a/src/main/io/serial_4way.c +++ b/src/main/io/serial_4way.c @@ -36,7 +36,7 @@ #include "drivers/time.h" #include "drivers/timer.h" #include "drivers/light_led.h" - +#include "drivers/pwm_output.h" #include "flight/mixer.h" #include "io/beeper.h" diff --git a/src/main/msp/msp.c b/src/main/msp/msp.c index 4b83a4708c..fdb95d7cd1 100644 --- a/src/main/msp/msp.c +++ b/src/main/msp/msp.c @@ -1871,12 +1871,12 @@ case MSP_NAME: case MSP_ADVANCED_CONFIG: sbufWriteU8(dst, 1); // was gyroConfig()->gyro_sync_denom - removed in API 1.43 sbufWriteU8(dst, pidConfig()->pid_process_denom); - sbufWriteU8(dst, motorConfig()->dev.useUnsyncedPwm); - sbufWriteU8(dst, motorConfig()->dev.motorPwmProtocol); + sbufWriteU8(dst, motorConfig()->dev.useContinuousUpdate); + sbufWriteU8(dst, motorConfig()->dev.motorProtocol); sbufWriteU16(dst, motorConfig()->dev.motorPwmRate); sbufWriteU16(dst, motorConfig()->motorIdle); sbufWriteU8(dst, 0); // DEPRECATED: gyro_use_32kHz - sbufWriteU8(dst, motorConfig()->dev.motorPwmInversion); + sbufWriteU8(dst, motorConfig()->dev.motorInversion); sbufWriteU8(dst, gyroConfig()->gyro_to_use); sbufWriteU8(dst, gyroConfig()->gyro_high_fsr); sbufWriteU8(dst, gyroConfig()->gyroMovementCalibrationThreshold); @@ -3074,8 +3074,8 @@ static mspResult_e mspProcessInCommand(mspDescriptor_t srcDesc, int16_t cmdMSP, case MSP_SET_ADVANCED_CONFIG: sbufReadU8(src); // was gyroConfigMutable()->gyro_sync_denom - removed in API 1.43 pidConfigMutable()->pid_process_denom = sbufReadU8(src); - motorConfigMutable()->dev.useUnsyncedPwm = sbufReadU8(src); - motorConfigMutable()->dev.motorPwmProtocol = sbufReadU8(src); + motorConfigMutable()->dev.useContinuousUpdate = sbufReadU8(src); + motorConfigMutable()->dev.motorProtocol = sbufReadU8(src); motorConfigMutable()->dev.motorPwmRate = sbufReadU16(src); if (sbufBytesRemaining(src) >= 2) { motorConfigMutable()->motorIdle = sbufReadU16(src); @@ -3084,7 +3084,7 @@ static mspResult_e mspProcessInCommand(mspDescriptor_t srcDesc, int16_t cmdMSP, sbufReadU8(src); // DEPRECATED: gyro_use_32khz } if (sbufBytesRemaining(src)) { - motorConfigMutable()->dev.motorPwmInversion = sbufReadU8(src); + motorConfigMutable()->dev.motorInversion = sbufReadU8(src); } if (sbufBytesRemaining(src) >= 8) { gyroConfigMutable()->gyro_to_use = sbufReadU8(src); diff --git a/src/main/pg/motor.c b/src/main/pg/motor.c index e89a9fbca4..d546ed1137 100644 --- a/src/main/pg/motor.c +++ b/src/main/pg/motor.c @@ -25,7 +25,7 @@ #ifdef USE_MOTOR -#include "drivers/pwm_output.h" +#include "drivers/motor_types.h" #include "pg/pg.h" #include "pg/pg_ids.h" @@ -51,31 +51,28 @@ PG_REGISTER_WITH_RESET_FN(motorConfig_t, motorConfig, PG_MOTOR_CONFIG, 3); void pgResetFn_motorConfig(motorConfig_t *motorConfig) { -#ifdef BRUSHED_MOTORS +#if defined(USE_BRUSHED_MOTORS) motorConfig->dev.motorPwmRate = BRUSHED_MOTORS_PWM_RATE; - motorConfig->dev.motorPwmProtocol = PWM_TYPE_BRUSHED; - motorConfig->dev.useUnsyncedPwm = true; + motorConfig->dev.motorProtocol = MOTOR_PROTOCOL_BRUSHED; + motorConfig->dev.useContinuousUpdate = true; + motorConfig->motorIdle = 700; // historical default minThrottle for brushed was 1070 #else motorConfig->dev.motorPwmRate = BRUSHLESS_MOTORS_PWM_RATE; -#ifndef USE_DSHOT - if (motorConfig->dev.motorPwmProtocol == PWM_TYPE_STANDARD) { - motorConfig->dev.useUnsyncedPwm = true; - } - motorConfig->dev.motorPwmProtocol = PWM_TYPE_DISABLED; -#elif defined(DEFAULT_MOTOR_DSHOT_SPEED) - motorConfig->dev.motorPwmProtocol = DEFAULT_MOTOR_DSHOT_SPEED; + motorConfig->motorIdle = 550; +#if !defined(USE_DSHOT) && defined(USE_PWM_OUTPUT) + motorConfig->dev.motorProtocol = MOTOR_PROTOCOL_PWM; + motorConfig->dev.useContinuousUpdate = true; +#elif defined(USE_DSHOT) && defined(DEFAULT_MOTOR_DSHOT_SPEED) + motorConfig->dev.motorProtocol = DEFAULT_MOTOR_DSHOT_SPEED; +#elif defined(USE_DSHOT) + motorConfig->dev.motorProtocol = MOTOR_PROTOCOL_DSHOT600; #else - motorConfig->dev.motorPwmProtocol = PWM_TYPE_DSHOT600; -#endif // USE_DSHOT -#endif // BRUSHED_MOTORS + motorConfig->dev.motorProtocol = MOTOR_PROTOCOL_DISABLED; +#endif // protocol selection +#endif // brushed motors motorConfig->maxthrottle = 2000; motorConfig->mincommand = 1000; -#ifdef BRUSHED_MOTORS - motorConfig->motorIdle = 700; // historical default minThrottle for brushed was 1070 -#else - motorConfig->motorIdle = 550; -#endif // BRUSHED_MOTORS motorConfig->kv = 1960; #ifdef USE_TIMER diff --git a/src/main/pg/motor.h b/src/main/pg/motor.h index c4fca53b2f..1b8564862a 100644 --- a/src/main/pg/motor.h +++ b/src/main/pg/motor.h @@ -23,30 +23,45 @@ #include "pg/pg.h" #include "drivers/io.h" -#include "drivers/dshot_bitbang.h" +#if !defined(BRUSHED_MOTORS_PWM_RATE) +#define BRUSHED_MOTORS_PWM_RATE 16000 +#endif + +#if !defined(BRUSHLESS_MOTORS_PWM_RATE) +#define BRUSHLESS_MOTORS_PWM_RATE 480 +#endif + +//TODO: Timers are platform specific. This should be moved to platform specific code. typedef enum { DSHOT_BITBANGED_TIMER_AUTO = 0, DSHOT_BITBANGED_TIMER_TIM1, DSHOT_BITBANGED_TIMER_TIM8, } dshotBitbangedTimer_e; +//TODO: DMAR is platform specific. This should be moved to platform specific code. typedef enum { DSHOT_DMAR_OFF, DSHOT_DMAR_ON, DSHOT_DMAR_AUTO } dshotDmar_e; +typedef enum { + DSHOT_BITBANG_OFF, + DSHOT_BITBANG_ON, + DSHOT_BITBANG_AUTO, +} dshotBitbangMode_e; + typedef enum { DSHOT_TELEMETRY_OFF, DSHOT_TELEMETRY_ON, } dshotTelemetry_e; typedef struct motorDevConfig_s { - uint16_t motorPwmRate; // The update rate of motor outputs (50-498Hz) - uint8_t motorPwmProtocol; // Pwm Protocol - uint8_t motorPwmInversion; // Active-High vs Active-Low. Useful for brushed FCs converted for brushless operation - uint8_t useUnsyncedPwm; + uint16_t motorPwmRate; // The update rate of motor outputs (50-498Hz) + uint8_t motorProtocol; // Pwm Protocol + uint8_t motorInversion; // Active-High vs Active-Low. Useful for brushed FCs converted for brushless operation + uint8_t useContinuousUpdate; uint8_t useBurstDshot; uint8_t useDshotTelemetry; uint8_t useDshotEdt; diff --git a/src/main/sensors/esc_sensor.c b/src/main/sensors/esc_sensor.c index 06bed65e2b..067a889c1c 100644 --- a/src/main/sensors/esc_sensor.c +++ b/src/main/sensors/esc_sensor.c @@ -42,7 +42,6 @@ #include "drivers/timer.h" #include "drivers/motor.h" #include "drivers/dshot.h" -#include "drivers/dshot_dpwm.h" #include "drivers/serial.h" #include "drivers/serial_uart.h" @@ -321,8 +320,7 @@ void escSensorProcess(timeUs_t currentTimeUs) escTriggerTimestamp = currentTimeMs; startEscDataRead(telemetryBuffer, TELEMETRY_FRAME_SIZE); - motorDmaOutput_t * const motor = getMotorDmaOutput(escSensorMotor); - motor->protocolControl.requestTelemetry = true; + motorRequestTelemetry(escSensorMotor); escSensorTriggerState = ESC_SENSOR_TRIGGER_PENDING; DEBUG_SET(DEBUG_ESC_SENSOR, DEBUG_ESC_MOTOR_INDEX, escSensorMotor + 1); diff --git a/src/platform/APM32/dshot_bitbang.c b/src/platform/APM32/dshot_bitbang.c index 92de301f43..5776305d62 100644 --- a/src/platform/APM32/dshot_bitbang.c +++ b/src/platform/APM32/dshot_bitbang.c @@ -36,15 +36,14 @@ #include "drivers/dma_reqmap.h" #include "drivers/dshot.h" #include "drivers/dshot_bitbang.h" -#include "drivers/dshot_bitbang_impl.h" +#include "dshot_bitbang_impl.h" #include "drivers/dshot_command.h" #include "drivers/motor.h" #include "drivers/nvic.h" -#include "drivers/pwm_output.h" // XXX for pwmOutputPort_t motors[]; should go away with refactoring -#include "drivers/dshot_dpwm.h" // XXX for motorDmaOutput_t *getMotorDmaOutput(uint8_t index); should go away with refactoring #include "drivers/dshot_bitbang_decode.h" #include "drivers/time.h" #include "drivers/timer.h" +#include "pwm_output_dshot_shared.h" #include "pg/motor.h" #include "pg/pinio.h" @@ -58,17 +57,6 @@ // Maximum time to wait for telemetry reception to complete #define DSHOT_TELEMETRY_TIMEOUT 2000 -FAST_DATA_ZERO_INIT bbPacer_t bbPacers[MAX_MOTOR_PACERS]; // TIM1 or TIM8 -FAST_DATA_ZERO_INIT int usedMotorPacers = 0; - -FAST_DATA_ZERO_INIT bbPort_t bbPorts[MAX_SUPPORTED_MOTOR_PORTS]; -FAST_DATA_ZERO_INIT int usedMotorPorts; - -FAST_DATA_ZERO_INIT bbMotor_t bbMotors[MAX_SUPPORTED_MOTORS]; - -static FAST_DATA_ZERO_INIT int motorCount; -dshotBitbangStatus_e bbStatus; - // For MCUs that use MPU to control DMA coherency, there might be a performance hit // on manipulating input buffer content especially if it is read multiple times, // as the buffer region is attributed as not cachable. @@ -106,10 +94,9 @@ const timerHardware_t bbTimerHardware[] = { #endif }; -static FAST_DATA_ZERO_INIT motorDevice_t bbDevice; static FAST_DATA_ZERO_INIT timeUs_t lastSendUs; -static motorPwmProtocolTypes_e motorPwmProtocol; +static motorProtocolTypes_e motorProtocol; // DMA GPIO output buffer formatting @@ -259,15 +246,15 @@ const resourceOwner_t *dshotBitbangTimerGetOwner(const timerHardware_t *timer) // Return frequency of smallest change [state/sec] -static uint32_t getDshotBaseFrequency(motorPwmProtocolTypes_e pwmProtocolType) +static uint32_t getDshotBaseFrequency(motorProtocolTypes_e pwmProtocolType) { switch (pwmProtocolType) { - case(PWM_TYPE_DSHOT600): + case(MOTOR_PROTOCOL_DSHOT600): return MOTOR_DSHOT600_SYMBOL_RATE * MOTOR_DSHOT_STATE_PER_SYMBOL; - case(PWM_TYPE_DSHOT300): + case(MOTOR_PROTOCOL_DSHOT300): return MOTOR_DSHOT300_SYMBOL_RATE * MOTOR_DSHOT_STATE_PER_SYMBOL; default: - case(PWM_TYPE_DSHOT150): + case(MOTOR_PROTOCOL_DSHOT150): return MOTOR_DSHOT150_SYMBOL_RATE * MOTOR_DSHOT_STATE_PER_SYMBOL; } } @@ -380,7 +367,7 @@ static void bbFindPacerTimer(void) } } -static void bbTimebaseSetup(bbPort_t *bbPort, motorPwmProtocolTypes_e dshotProtocolType) +static void bbTimebaseSetup(bbPort_t *bbPort, motorProtocolTypes_e dshotProtocolType) { uint32_t timerclock = timerClock(bbPort->timhw->tim); @@ -398,7 +385,7 @@ static void bbTimebaseSetup(bbPort_t *bbPort, motorPwmProtocolTypes_e dshotProto // it does not use the timer channel associated with the pin. // -static bool bbMotorConfig(IO_t io, uint8_t motorIndex, motorPwmProtocolTypes_e pwmProtocolType, uint8_t output) +static bool bbMotorConfig(IO_t io, uint8_t motorIndex, motorProtocolTypes_e pwmProtocolType, uint8_t output) { // Return if no GPIO is specified if (!io) { @@ -430,10 +417,6 @@ static bool bbMotorConfig(IO_t io, uint8_t motorIndex, motorPwmProtocolTypes_e p } if (!bbPort || !dmaAllocate(dmaGetIdentifier(bbPort->dmaResource), bbPort->owner.owner, bbPort->owner.resourceIndex)) { - bbDevice.vTable.write = motorWriteNull; - bbDevice.vTable.decodeTelemetry = motorDecodeTelemetryNull; - bbDevice.vTable.updateComplete = motorUpdateCompleteNull; - return false; } @@ -531,7 +514,7 @@ static bool bbDecodeTelemetry(void) SCB_InvalidateDCache_by_Addr((uint32_t *)bbPort->portInputBuffer, DSHOT_BB_PORT_IP_BUF_CACHE_ALIGN_BYTES); } #endif - for (int motorIndex = 0; motorIndex < MAX_SUPPORTED_MOTORS && motorIndex < motorCount; motorIndex++) { + for (int motorIndex = 0; motorIndex < MAX_SUPPORTED_MOTORS && motorIndex < dshotMotorCount; motorIndex++) { #ifdef APM32F4 uint32_t rawValue = decode_bb_bitband( bbMotors[motorIndex].bbPort->portInputBuffer, @@ -614,7 +597,7 @@ static void bbUpdateComplete(void) // If there is a dshot command loaded up, time it correctly with motor update if (!dshotCommandQueueEmpty()) { - if (!dshotCommandOutputIsEnabled(bbDevice.count)) { + if (!dshotCommandOutputIsEnabled(dshotMotorCount)) { return; } } @@ -649,7 +632,7 @@ static void bbUpdateComplete(void) static bool bbEnableMotors(void) { - for (int i = 0; i < motorCount; i++) { + for (int i = 0; i < dshotMotorCount; i++) { if (bbMotors[i].configured) { IOConfigGPIO(bbMotors[i].io, bbMotors[i].iocfg); } @@ -667,7 +650,7 @@ static void bbShutdown(void) return; } -static bool bbIsMotorEnabled(uint8_t index) +static bool bbIsMotorEnabled(unsigned index) { return bbMotors[index].enabled; } @@ -676,17 +659,13 @@ static void bbPostInit(void) { bbFindPacerTimer(); - for (int motorIndex = 0; motorIndex < MAX_SUPPORTED_MOTORS && motorIndex < motorCount; motorIndex++) { + for (int motorIndex = 0; motorIndex < MAX_SUPPORTED_MOTORS && motorIndex < dshotMotorCount; motorIndex++) { - if (!bbMotorConfig(bbMotors[motorIndex].io, motorIndex, motorPwmProtocol, bbMotors[motorIndex].output)) { + if (!bbMotorConfig(bbMotors[motorIndex].io, motorIndex, motorProtocol, bbMotors[motorIndex].output)) { return; } bbMotors[motorIndex].enabled = true; - - // Fill in motors structure for 4way access (XXX Should be refactored) - - motors[motorIndex].enabled = true; } } @@ -704,6 +683,8 @@ static motorVTable_t bbVTable = { .convertExternalToMotor = dshotConvertFromExternal, .convertMotorToExternal = dshotConvertToExternal, .shutdown = bbShutdown, + .isMotorIdle = bbDshotIsMotorIdle, + .requestTelemetry = bbDshotRequestTelemetry, }; dshotBitbangStatus_e dshotBitbangGetStatus(void) @@ -711,14 +692,18 @@ dshotBitbangStatus_e dshotBitbangGetStatus(void) return bbStatus; } -motorDevice_t *dshotBitbangDevInit(const motorDevConfig_t *motorConfig, uint8_t count) +bool dshotBitbangDevInit(motorDevice_t *device, const motorDevConfig_t *motorConfig) { dbgPinLo(0); dbgPinLo(1); - motorPwmProtocol = motorConfig->motorPwmProtocol; - bbDevice.vTable = bbVTable; - motorCount = count; + if (!device || !motorConfig) { + return false; + } + + motorProtocol = motorConfig->motorProtocol; + device->vTable = &bbVTable; + dshotMotorCount = device->count; bbStatus = DSHOT_BITBANG_STATUS_OK; #ifdef USE_DSHOT_TELEMETRY @@ -727,12 +712,12 @@ motorDevice_t *dshotBitbangDevInit(const motorDevConfig_t *motorConfig, uint8_t memset(bbOutputBuffer, 0, sizeof(bbOutputBuffer)); - for (int motorIndex = 0; motorIndex < MAX_SUPPORTED_MOTORS && motorIndex < motorCount; motorIndex++) { + for (int motorIndex = 0; motorIndex < MAX_SUPPORTED_MOTORS && motorIndex < dshotMotorCount; motorIndex++) { const unsigned reorderedMotorIndex = motorConfig->motorOutputReordering[motorIndex]; const timerHardware_t *timerHardware = timerGetConfiguredByTag(motorConfig->ioTags[reorderedMotorIndex]); const IO_t io = IOGetByTag(motorConfig->ioTags[reorderedMotorIndex]); - uint8_t output = motorConfig->motorPwmInversion ? timerHardware->output ^ TIMER_OUTPUT_INVERTED : timerHardware->output; + uint8_t output = motorConfig->motorInversion ? timerHardware->output ^ TIMER_OUTPUT_INVERTED : timerHardware->output; bbPuPdMode = (output & TIMER_OUTPUT_INVERTED) ? BB_GPIO_PULLDOWN : BB_GPIO_PULLUP; #ifdef USE_DSHOT_TELEMETRY @@ -743,11 +728,10 @@ motorDevice_t *dshotBitbangDevInit(const motorDevConfig_t *motorConfig, uint8_t if (!IOIsFreeOrPreinit(io)) { /* not enough motors initialised for the mixer or a break in the motors */ - bbDevice.vTable.write = motorWriteNull; - bbDevice.vTable.decodeTelemetry = motorDecodeTelemetryNull; - bbDevice.vTable.updateComplete = motorUpdateCompleteNull; + device->vTable = NULL; + dshotMotorCount = 0; bbStatus = DSHOT_BITBANG_STATUS_MOTOR_PIN_CONFLICT; - return NULL; + return false; } int pinIndex = IO_GPIOPinIdx(io); @@ -766,12 +750,8 @@ motorDevice_t *dshotBitbangDevInit(const motorDevConfig_t *motorConfig, uint8_t } else { IOHi(io); } - - // Fill in motors structure for 4way access (XXX Should be refactored) - motors[motorIndex].io = bbMotors[motorIndex].io; } - - return &bbDevice; + return true; } #endif // USE_DSHOT_BITBANG diff --git a/src/platform/APM32/dshot_bitbang_ddl.c b/src/platform/APM32/dshot_bitbang_ddl.c index c03e02ff9b..50d53cf7e8 100644 --- a/src/platform/APM32/dshot_bitbang_ddl.c +++ b/src/platform/APM32/dshot_bitbang_ddl.c @@ -35,7 +35,7 @@ #include "drivers/dma.h" #include "drivers/dma_reqmap.h" #include "drivers/dshot.h" -#include "drivers/dshot_bitbang_impl.h" +#include "dshot_bitbang_impl.h" #include "drivers/dshot_command.h" #include "drivers/motor.h" #include "drivers/nvic.h" diff --git a/src/platform/APM32/mk/APM32F4.mk b/src/platform/APM32/mk/APM32F4.mk index 5203bf6781..b82d82cf56 100644 --- a/src/platform/APM32/mk/APM32F4.mk +++ b/src/platform/APM32/mk/APM32F4.mk @@ -152,7 +152,9 @@ MCU_COMMON_SRC = \ APM32/startup/system_apm32f4xx.c \ drivers/inverter.c \ drivers/dshot_bitbang_decode.c \ - drivers/pwm_output_dshot_shared.c \ + common/stm32/pwm_output_dshot_shared.c \ + common/stm32/dshot_dpwm.c \ + common/stm32/dshot_bitbang_shared.c \ APM32/bus_spi_apm32.c \ APM32/bus_i2c_apm32.c \ APM32/bus_i2c_apm32_init.c \ @@ -206,6 +208,8 @@ MSC_SRC = \ msc/usbd_storage_sdio.c SPEED_OPTIMISED_SRC += \ + common/stm32/dshot_bitbang_shared.c \ + common/stm32/pwm_output_dshot_shared.c \ common/stm32/bus_spi_hw.c \ common/stm32/system.c diff --git a/src/platform/APM32/pwm_output_apm32.c b/src/platform/APM32/pwm_output_apm32.c index a2d3254fe7..a49c58d748 100644 --- a/src/platform/APM32/pwm_output_apm32.c +++ b/src/platform/APM32/pwm_output_apm32.c @@ -36,12 +36,12 @@ #include "pg/motor.h" -FAST_DATA_ZERO_INIT pwmOutputPort_t motors[MAX_SUPPORTED_MOTORS]; - static void pwmOCConfig(TMR_TypeDef *tim, uint8_t channel, uint16_t value, uint8_t output) { TMR_HandleTypeDef* Handle = timerFindTimerHandle(tim); - if (Handle == NULL) return; + if (Handle == NULL) { + return; + } TMR_OC_InitTypeDef TMR_OCInitStructure; @@ -59,7 +59,9 @@ static void pwmOCConfig(TMR_TypeDef *tim, uint8_t channel, uint16_t value, uint8 void pwmOutConfig(timerChannel_t *channel, const timerHardware_t *timerHardware, uint32_t hz, uint16_t period, uint16_t value, uint8_t inversion) { TMR_HandleTypeDef* Handle = timerFindTimerHandle(timerHardware->tim); - if (Handle == NULL) return; + if (Handle == NULL) { + return; + } configTimeBase(timerHardware->tim, period, hz); pwmOCConfig(timerHardware->tim, @@ -68,10 +70,11 @@ void pwmOutConfig(timerChannel_t *channel, const timerHardware_t *timerHardware, inversion ? timerHardware->output ^ TIMER_OUTPUT_INVERTED : timerHardware->output ); - if (timerHardware->output & TIMER_OUTPUT_N_CHANNEL) + if (timerHardware->output & TIMER_OUTPUT_N_CHANNEL) { DAL_TMREx_PWMN_Start(Handle, timerHardware->channel); - else + } else { DAL_TMR_PWM_Start(Handle, timerHardware->channel); + } DAL_TMR_Base_Start(Handle); channel->ccr = timerChCCR(timerHardware); @@ -81,13 +84,7 @@ void pwmOutConfig(timerChannel_t *channel, const timerHardware_t *timerHardware, *channel->ccr = 0; } -static FAST_DATA_ZERO_INIT motorDevice_t motorPwmDevice; - -static void pwmWriteUnused(uint8_t index, float value) -{ - UNUSED(index); - UNUSED(value); -} +static bool useContinuousUpdate = true; static void pwmWriteStandard(uint8_t index, float value) { @@ -97,7 +94,7 @@ static void pwmWriteStandard(uint8_t index, float value) void pwmShutdownPulsesForAllMotors(void) { - for (int index = 0; index < motorPwmDevice.count; index++) { + for (int index = 0; index < pwmMotorCount; index++) { // Set the compare register to 0, which stops the output pulsing if the timer overflows if (motors[index].channel.ccr) { *motors[index].channel.ccr = 0; @@ -114,17 +111,21 @@ static motorVTable_t motorPwmVTable; bool pwmEnableMotors(void) { /* check motors can be enabled */ - return (motorPwmVTable.write != &pwmWriteUnused); + return pwmMotorCount > 0; } -bool pwmIsMotorEnabled(uint8_t index) +bool pwmIsMotorEnabled(unsigned index) { return motors[index].enabled; } -static void pwmCompleteOneshotMotorUpdate(void) +static void pwmCompleteMotorUpdate(void) { - for (int index = 0; index < motorPwmDevice.count; index++) { + if (useContinuousUpdate) { + return; + } + + for (int index = 0; index < pwmMotorCount; index++) { if (motors[index].forceOverflow) { timerForceOverflow(motors[index].channel.tim); } @@ -145,65 +146,72 @@ static uint16_t pwmConvertToExternal(float motorValue) } static motorVTable_t motorPwmVTable = { - .postInit = motorPostInitNull, + .postInit = NULL, .enable = pwmEnableMotors, .disable = pwmDisableMotors, .isMotorEnabled = pwmIsMotorEnabled, .shutdown = pwmShutdownPulsesForAllMotors, .convertExternalToMotor = pwmConvertFromExternal, .convertMotorToExternal = pwmConvertToExternal, + .write = pwmWriteStandard, + .decodeTelemetry = NULL, + .updateComplete = pwmCompleteMotorUpdate, + .requestTelemetry = NULL, + .isMotorIdle = NULL, }; -motorDevice_t *motorPwmDevInit(const motorDevConfig_t *motorConfig, uint16_t idlePulse, uint8_t motorCount, bool useUnsyncedPwm) +bool motorPwmDevInit(motorDevice_t *device, const motorDevConfig_t *motorConfig, uint16_t idlePulse) { memset(motors, 0, sizeof(motors)); - motorPwmDevice.vTable = motorPwmVTable; + if (!device || !motorConfig) { + return false; + } + pwmMotorCount = device->count; + device->vTable = &motorPwmVTable; + + useContinuousUpdate = motorConfig->useContinuousUpdate; float sMin = 0; float sLen = 0; - switch (motorConfig->motorPwmProtocol) { + switch (motorConfig->motorProtocol) { default: - case PWM_TYPE_ONESHOT125: + case MOTOR_PROTOCOL_ONESHOT125: sMin = 125e-6f; sLen = 125e-6f; break; - case PWM_TYPE_ONESHOT42: + case MOTOR_PROTOCOL_ONESHOT42: sMin = 42e-6f; sLen = 42e-6f; break; - case PWM_TYPE_MULTISHOT: + case MOTOR_PROTOCOL_MULTISHOT: sMin = 5e-6f; sLen = 20e-6f; break; - case PWM_TYPE_BRUSHED: + case MOTOR_PROTOCOL_BRUSHED: sMin = 0; - useUnsyncedPwm = true; + useContinuousUpdate = true; idlePulse = 0; break; - case PWM_TYPE_STANDARD: + case MOTOR_PROTOCOL_PWM : sMin = 1e-3f; sLen = 1e-3f; - useUnsyncedPwm = true; + useContinuousUpdate = true; idlePulse = 0; break; } - motorPwmDevice.vTable.write = pwmWriteStandard; - motorPwmDevice.vTable.decodeTelemetry = motorDecodeTelemetryNull; - motorPwmDevice.vTable.updateComplete = useUnsyncedPwm ? motorUpdateCompleteNull : pwmCompleteOneshotMotorUpdate; - - for (int motorIndex = 0; motorIndex < MAX_SUPPORTED_MOTORS && motorIndex < motorCount; motorIndex++) { + for (int motorIndex = 0; motorIndex < MAX_SUPPORTED_MOTORS && motorIndex < pwmMotorCount; motorIndex++) { const unsigned reorderedMotorIndex = motorConfig->motorOutputReordering[motorIndex]; const ioTag_t tag = motorConfig->ioTags[reorderedMotorIndex]; const timerHardware_t *timerHardware = timerAllocate(tag, OWNER_MOTOR, RESOURCE_INDEX(reorderedMotorIndex)); if (timerHardware == NULL) { /* not enough motors initialised for the mixer or a break in the motors */ - motorPwmDevice.vTable.write = &pwmWriteUnused; - motorPwmDevice.vTable.updateComplete = motorUpdateCompleteNull; + device->vTable = NULL; + pwmMotorCount = 0; /* TODO: block arming and add reason system cannot arm */ - return NULL; + return false; } motors[motorIndex].io = IOGetByTag(tag); @@ -213,23 +221,23 @@ motorDevice_t *motorPwmDevInit(const motorDevConfig_t *motorConfig, uint16_t idl /* standard PWM outputs */ // margin of safety is 4 periods when unsynced - const unsigned pwmRateHz = useUnsyncedPwm ? motorConfig->motorPwmRate : ceilf(1 / ((sMin + sLen) * 4)); + const unsigned pwmRateHz = useContinuousUpdate ? motorConfig->motorPwmRate : ceilf(1 / ((sMin + sLen) * 4)); const uint32_t clock = timerClock(timerHardware->tim); /* used to find the desired timer frequency for max resolution */ const unsigned prescaler = ((clock / pwmRateHz) + 0xffff) / 0x10000; /* rounding up */ const uint32_t hz = clock / prescaler; - const unsigned period = useUnsyncedPwm ? hz / pwmRateHz : 0xffff; + const unsigned period = useContinuousUpdate ? hz / pwmRateHz : 0xffff; /* if brushed then it is the entire length of the period. TODO: this can be moved back to periodMin and periodLen once mixer outputs a 0..1 float value. */ - motors[motorIndex].pulseScale = ((motorConfig->motorPwmProtocol == PWM_TYPE_BRUSHED) ? period : (sLen * hz)) / 1000.0f; + motors[motorIndex].pulseScale = ((motorConfig->motorProtocol == MOTOR_PROTOCOL_BRUSHED) ? period : (sLen * hz)) / 1000.0f; motors[motorIndex].pulseOffset = (sMin * hz) - (motors[motorIndex].pulseScale * 1000); - pwmOutConfig(&motors[motorIndex].channel, timerHardware, hz, period, idlePulse, motorConfig->motorPwmInversion); + pwmOutConfig(&motors[motorIndex].channel, timerHardware, hz, period, idlePulse, motorConfig->motorInversion); bool timerAlreadyUsed = false; for (int i = 0; i < motorIndex; i++) { @@ -242,7 +250,7 @@ motorDevice_t *motorPwmDevInit(const motorDevConfig_t *motorConfig, uint16_t idl motors[motorIndex].enabled = true; } - return &motorPwmDevice; + return true; } pwmOutputPort_t *pwmGetMotors(void) diff --git a/src/platform/APM32/pwm_output_dshot_apm32.c b/src/platform/APM32/pwm_output_dshot_apm32.c index 4025aa531c..499897394f 100644 --- a/src/platform/APM32/pwm_output_dshot_apm32.c +++ b/src/platform/APM32/pwm_output_dshot_apm32.c @@ -34,13 +34,13 @@ #include "drivers/dma.h" #include "drivers/dma_reqmap.h" #include "drivers/dshot.h" -#include "drivers/dshot_dpwm.h" +#include "dshot_dpwm.h" #include "drivers/dshot_command.h" #include "drivers/io.h" #include "drivers/nvic.h" #include "drivers/motor.h" #include "drivers/pwm_output.h" -#include "drivers/pwm_output_dshot_shared.h" +#include "pwm_output_dshot_shared.h" #include "drivers/rcc.h" #include "drivers/time.h" #include "drivers/timer.h" @@ -48,9 +48,9 @@ #ifdef USE_DSHOT_TELEMETRY -void dshotEnableChannels(uint8_t motorCount) +void dshotEnableChannels(unsigned motorCount) { - for (int i = 0; i < motorCount; i++) { + for (unsigned i = 0; i < motorCount; i++) { if (dmaMotors[i].output & TIMER_OUTPUT_N_CHANNEL) { DDL_TMR_CC_EnableChannel(dmaMotors[i].timerHardware->tim, dmaMotors[i].llChannel << 4); } else { @@ -128,7 +128,7 @@ FAST_CODE static void pwmDshotSetDirectionInput( FAST_CODE void pwmCompleteDshotMotorUpdate(void) { /* If there is a dshot command loaded up, time it correctly with motor update*/ - if (!dshotCommandQueueEmpty() && !dshotCommandOutputIsEnabled(dshotPwmDevice.count)) { + if (!dshotCommandQueueEmpty() && !dshotCommandOutputIsEnabled(dshotMotorCount)) { return; } @@ -188,7 +188,7 @@ FAST_CODE static void motor_DMA_IRQHandler(dmaChannelDescriptor_t* descriptor) } } -bool pwmDshotMotorHardwareConfig(const timerHardware_t *timerHardware, uint8_t motorIndex, uint8_t reorderedMotorIndex, motorPwmProtocolTypes_e pwmProtocolType, uint8_t output) +bool pwmDshotMotorHardwareConfig(const timerHardware_t *timerHardware, uint8_t motorIndex, uint8_t reorderedMotorIndex, motorProtocolTypes_e pwmProtocolType, uint8_t output) { #ifdef USE_DSHOT_TELEMETRY #define OCINIT motor->ocInitStruct @@ -276,7 +276,7 @@ bool pwmDshotMotorHardwareConfig(const timerHardware_t *timerHardware, uint8_t m DDL_TMR_DisableCounter(timer); init.Prescaler = (uint16_t)(lrintf((float) timerClock(timer) / getDshotHz(pwmProtocolType) + 0.01f) - 1); - init.Autoreload = (pwmProtocolType == PWM_TYPE_PROSHOT1000 ? MOTOR_NIBBLE_LENGTH_PROSHOT : MOTOR_BITLENGTH) - 1; + init.Autoreload = (pwmProtocolType == MOTOR_PROTOCOL_PROSHOT1000 ? MOTOR_NIBBLE_LENGTH_PROSHOT : MOTOR_BITLENGTH) - 1; init.ClockDivision = DDL_TMR_CLOCKDIVISION_DIV1; init.RepetitionCounter = 0; init.CounterMode = DDL_TMR_COUNTERMODE_UP; @@ -356,7 +356,7 @@ bool pwmDshotMotorHardwareConfig(const timerHardware_t *timerHardware, uint8_t m DMAINIT.FIFOMode = DDL_DMA_FIFOMODE_ENABLE; DMAINIT.MemBurst = DDL_DMA_MBURST_SINGLE; DMAINIT.PeriphBurst = DDL_DMA_PBURST_SINGLE; - DMAINIT.NbData = pwmProtocolType == PWM_TYPE_PROSHOT1000 ? PROSHOT_DMA_BUFFER_SIZE : DSHOT_DMA_BUFFER_SIZE; + DMAINIT.NbData = pwmProtocolType == MOTOR_PROTOCOL_PROSHOT1000 ? PROSHOT_DMA_BUFFER_SIZE : DSHOT_DMA_BUFFER_SIZE; DMAINIT.PeriphOrM2MSrcIncMode = DDL_DMA_PERIPH_NOINCREMENT; DMAINIT.MemoryOrM2MDstIncMode = DDL_DMA_MEMORY_INCREMENT; DMAINIT.PeriphOrM2MSrcDataSize = DDL_DMA_PDATAALIGN_WORD; @@ -374,7 +374,7 @@ bool pwmDshotMotorHardwareConfig(const timerHardware_t *timerHardware, uint8_t m #ifdef USE_DSHOT_TELEMETRY motor->dshotTelemetryDeadtimeUs = DSHOT_TELEMETRY_DEADTIME_US + 1000000 * ( 16 * MOTOR_BITLENGTH) / getDshotHz(pwmProtocolType); - motor->timer->outputPeriod = (pwmProtocolType == PWM_TYPE_PROSHOT1000 ? (MOTOR_NIBBLE_LENGTH_PROSHOT) : MOTOR_BITLENGTH) - 1; + motor->timer->outputPeriod = (pwmProtocolType == MOTOR_PROTOCOL_PROSHOT1000 ? (MOTOR_NIBBLE_LENGTH_PROSHOT) : MOTOR_BITLENGTH) - 1; pwmDshotSetDirectionOutput(motor); #else pwmDshotSetDirectionOutput(motor, &OCINIT, &DMAINIT); diff --git a/src/platform/AT32/dshot_bitbang.c b/src/platform/AT32/dshot_bitbang.c index ccff17ae91..d3ac4f2e88 100644 --- a/src/platform/AT32/dshot_bitbang.c +++ b/src/platform/AT32/dshot_bitbang.c @@ -36,12 +36,11 @@ #include "drivers/dma_reqmap.h" #include "drivers/dshot.h" #include "drivers/dshot_bitbang.h" -#include "drivers/dshot_bitbang_impl.h" +#include "dshot_bitbang_impl.h" #include "drivers/dshot_command.h" #include "drivers/motor.h" #include "drivers/nvic.h" -#include "drivers/pwm_output.h" // XXX for pwmOutputPort_t motors[]; should go away with refactoring -#include "drivers/dshot_dpwm.h" // XXX for motorDmaOutput_t *getMotorDmaOutput(uint8_t index); should go away with refactoring +#include "pwm_output_dshot_shared.h" #include "drivers/dshot_bitbang_decode.h" #include "drivers/time.h" #include "drivers/timer.h" @@ -51,17 +50,6 @@ // Maximum time to wait for telemetry reception to complete #define DSHOT_TELEMETRY_TIMEOUT 2000 -FAST_DATA_ZERO_INIT bbPacer_t bbPacers[MAX_MOTOR_PACERS]; // TIM1 or TIM8 -FAST_DATA_ZERO_INIT int usedMotorPacers = 0; - -FAST_DATA_ZERO_INIT bbPort_t bbPorts[MAX_SUPPORTED_MOTOR_PORTS]; -FAST_DATA_ZERO_INIT int usedMotorPorts; - -FAST_DATA_ZERO_INIT bbMotor_t bbMotors[MAX_SUPPORTED_MOTORS]; - -static FAST_DATA_ZERO_INIT int motorCount; -dshotBitbangStatus_e bbStatus; - // For MCUs that use MPU to control DMA coherency, there might be a performance hit // on manipulating input buffer content especially if it is read multiple times, // as the buffer region is attributed as not cachable. @@ -91,10 +79,9 @@ const timerHardware_t bbTimerHardware[] = { DEF_TIM(TMR1, CH4, NONE, 0, 3, 0), }; -static FAST_DATA_ZERO_INIT motorDevice_t bbDevice; static FAST_DATA_ZERO_INIT timeUs_t lastSendUs; -static motorPwmProtocolTypes_e motorPwmProtocol; +static motorProtocolTypes_e motorProtocol; // DMA GPIO output buffer formatting @@ -244,15 +231,15 @@ const resourceOwner_t *dshotBitbangTimerGetOwner(const timerHardware_t *timer) // Return frequency of smallest change [state/sec] -static uint32_t getDshotBaseFrequency(motorPwmProtocolTypes_e pwmProtocolType) +static uint32_t getDshotBaseFrequency(motorProtocolTypes_e pwmProtocolType) { switch (pwmProtocolType) { - case(PWM_TYPE_DSHOT600): + case(MOTOR_PROTOCOL_DSHOT600): return MOTOR_DSHOT600_SYMBOL_RATE * MOTOR_DSHOT_STATE_PER_SYMBOL; - case(PWM_TYPE_DSHOT300): + case(MOTOR_PROTOCOL_DSHOT300): return MOTOR_DSHOT300_SYMBOL_RATE * MOTOR_DSHOT_STATE_PER_SYMBOL; default: - case(PWM_TYPE_DSHOT150): + case(MOTOR_PROTOCOL_DSHOT150): return MOTOR_DSHOT150_SYMBOL_RATE * MOTOR_DSHOT_STATE_PER_SYMBOL; } } @@ -365,7 +352,7 @@ static void bbFindPacerTimer(void) } } -static void bbTimebaseSetup(bbPort_t *bbPort, motorPwmProtocolTypes_e dshotProtocolType) +static void bbTimebaseSetup(bbPort_t *bbPort, motorProtocolTypes_e dshotProtocolType) { uint32_t timerclock = timerClock(bbPort->timhw->tim); @@ -383,7 +370,7 @@ static void bbTimebaseSetup(bbPort_t *bbPort, motorPwmProtocolTypes_e dshotProto // it does not use the timer channel associated with the pin. // -static bool bbMotorConfig(IO_t io, uint8_t motorIndex, motorPwmProtocolTypes_e pwmProtocolType, uint8_t output) +static bool bbMotorConfig(IO_t io, uint8_t motorIndex, motorProtocolTypes_e pwmProtocolType, uint8_t output) { int pinIndex = IO_GPIOPinIdx(io); int portIndex = IO_GPIOPortIdx(io); @@ -410,10 +397,6 @@ static bool bbMotorConfig(IO_t io, uint8_t motorIndex, motorPwmProtocolTypes_e p } if (!bbPort || !dmaAllocate(dmaGetIdentifier(bbPort->dmaResource), bbPort->owner.owner, bbPort->owner.resourceIndex)) { - bbDevice.vTable.write = motorWriteNull; - bbDevice.vTable.decodeTelemetry = motorDecodeTelemetryNull; - bbDevice.vTable.updateComplete = motorUpdateCompleteNull; - return false; } @@ -511,7 +494,7 @@ static bool bbDecodeTelemetry(void) SCB_InvalidateDCache_by_Addr((uint32_t *)bbPort->portInputBuffer, DSHOT_BB_PORT_IP_BUF_CACHE_ALIGN_BYTES); } #endif - for (int motorIndex = 0; motorIndex < MAX_SUPPORTED_MOTORS && motorIndex < motorCount; motorIndex++) { + for (int motorIndex = 0; motorIndex < MAX_SUPPORTED_MOTORS && motorIndex < dshotMotorCount; motorIndex++) { uint32_t rawValue = decode_bb_bitband( bbMotors[motorIndex].bbPort->portInputBuffer, @@ -594,7 +577,7 @@ static void bbUpdateComplete(void) // If there is a dshot command loaded up, time it correctly with motor update if (!dshotCommandQueueEmpty()) { - if (!dshotCommandOutputIsEnabled(bbDevice.count)) { + if (!dshotCommandOutputIsEnabled(dshotMotorCount)) { return; } } @@ -641,7 +624,7 @@ static void bbUpdateComplete(void) static bool bbEnableMotors(void) { - for (int i = 0; i < motorCount; i++) { + for (int i = 0; i < dshotMotorCount; i++) { if (bbMotors[i].configured) { IOConfigGPIO(bbMotors[i].io, bbMotors[i].iocfg); } @@ -659,7 +642,7 @@ static void bbShutdown(void) return; } -static bool bbIsMotorEnabled(uint8_t index) +static bool bbIsMotorEnabled(unsigned index) { return bbMotors[index].enabled; } @@ -668,17 +651,13 @@ static void bbPostInit(void) { bbFindPacerTimer(); - for (int motorIndex = 0; motorIndex < MAX_SUPPORTED_MOTORS && motorIndex < motorCount; motorIndex++) { + for (int motorIndex = 0; motorIndex < MAX_SUPPORTED_MOTORS && motorIndex < dshotMotorCount; motorIndex++) { - if (!bbMotorConfig(bbMotors[motorIndex].io, motorIndex, motorPwmProtocol, bbMotors[motorIndex].output)) { + if (!bbMotorConfig(bbMotors[motorIndex].io, motorIndex, motorProtocol, bbMotors[motorIndex].output)) { return; } bbMotors[motorIndex].enabled = true; - - // Fill in motors structure for 4way access (XXX Should be refactored) - - motors[motorIndex].enabled = true; } } @@ -696,6 +675,8 @@ static motorVTable_t bbVTable = { .convertExternalToMotor = dshotConvertFromExternal, .convertMotorToExternal = dshotConvertToExternal, .shutdown = bbShutdown, + .isMotorIdle = bbDshotIsMotorIdle, + .requestTelemetry = bbDshotRequestTelemetry, }; dshotBitbangStatus_e dshotBitbangGetStatus(void) @@ -703,14 +684,15 @@ dshotBitbangStatus_e dshotBitbangGetStatus(void) return bbStatus; } -motorDevice_t *dshotBitbangDevInit(const motorDevConfig_t *motorConfig, uint8_t count) +bool dshotBitbangDevInit(motorDevice_t *device, const motorDevConfig_t *motorConfig) { dbgPinLo(0); dbgPinLo(1); - motorPwmProtocol = motorConfig->motorPwmProtocol; - bbDevice.vTable = bbVTable; - motorCount = count; + motorProtocol = motorConfig->motorProtocol; + device->vTable = &bbVTable; + dshotMotorCount = device->count; + bbStatus = DSHOT_BITBANG_STATUS_OK; #ifdef USE_DSHOT_TELEMETRY @@ -719,12 +701,12 @@ motorDevice_t *dshotBitbangDevInit(const motorDevConfig_t *motorConfig, uint8_t memset(bbOutputBuffer, 0, sizeof(bbOutputBuffer)); - for (int motorIndex = 0; motorIndex < MAX_SUPPORTED_MOTORS && motorIndex < motorCount; motorIndex++) { + for (int motorIndex = 0; motorIndex < MAX_SUPPORTED_MOTORS && motorIndex < dshotMotorCount; motorIndex++) { const unsigned reorderedMotorIndex = motorConfig->motorOutputReordering[motorIndex]; const timerHardware_t *timerHardware = timerGetConfiguredByTag(motorConfig->ioTags[reorderedMotorIndex]); const IO_t io = IOGetByTag(motorConfig->ioTags[reorderedMotorIndex]); - uint8_t output = motorConfig->motorPwmInversion ? timerHardware->output ^ TIMER_OUTPUT_INVERTED : timerHardware->output; + uint8_t output = motorConfig->motorInversion ? timerHardware->output ^ TIMER_OUTPUT_INVERTED : timerHardware->output; bbPuPdMode = (output & TIMER_OUTPUT_INVERTED) ? BB_GPIO_PULLDOWN : BB_GPIO_PULLUP; #ifdef USE_DSHOT_TELEMETRY @@ -735,11 +717,10 @@ motorDevice_t *dshotBitbangDevInit(const motorDevConfig_t *motorConfig, uint8_t if (!IOIsFreeOrPreinit(io)) { /* not enough motors initialised for the mixer or a break in the motors */ - bbDevice.vTable.write = motorWriteNull; - bbDevice.vTable.decodeTelemetry = motorDecodeTelemetryNull; - bbDevice.vTable.updateComplete = motorUpdateCompleteNull; bbStatus = DSHOT_BITBANG_STATUS_MOTOR_PIN_CONFLICT; - return NULL; + device->vTable = NULL; + dshotMotorCount = 0; + return false; } int pinIndex = IO_GPIOPinIdx(io); @@ -756,12 +737,8 @@ motorDevice_t *dshotBitbangDevInit(const motorDevConfig_t *motorConfig, uint8_t } else { IOHi(io); } - - // Fill in motors structure for 4way access (TODO: Should be refactored) - motors[motorIndex].io = bbMotors[motorIndex].io; } - - return &bbDevice; + return true; } #endif // USE_DSHOT_BB diff --git a/src/platform/AT32/dshot_bitbang_stdperiph.c b/src/platform/AT32/dshot_bitbang_stdperiph.c index 356e4c29ae..927eae2684 100644 --- a/src/platform/AT32/dshot_bitbang_stdperiph.c +++ b/src/platform/AT32/dshot_bitbang_stdperiph.c @@ -36,11 +36,10 @@ #include "drivers/dma.h" #include "drivers/dma_reqmap.h" #include "drivers/dshot.h" -#include "drivers/dshot_bitbang_impl.h" +#include "dshot_bitbang_impl.h" #include "drivers/dshot_command.h" #include "drivers/motor.h" #include "drivers/nvic.h" -#include "drivers/pwm_output.h" // XXX for pwmOutputPort_t motors[]; should go away with refactoring #include "drivers/time.h" #include "drivers/timer.h" diff --git a/src/platform/AT32/mk/AT32F4.mk b/src/platform/AT32/mk/AT32F4.mk index 759c36ad60..2a0149017e 100644 --- a/src/platform/AT32/mk/AT32F4.mk +++ b/src/platform/AT32/mk/AT32F4.mk @@ -113,7 +113,9 @@ MCU_COMMON_SRC = \ drivers/accgyro/accgyro_mpu.c \ drivers/dshot_bitbang_decode.c \ drivers/inverter.c \ - drivers/pwm_output_dshot_shared.c \ + common/stm32/pwm_output_dshot_shared.c \ + common/stm32/dshot_dpwm.c \ + common/stm32/dshot_bitbang_shared.c \ $(MIDDLEWARES_DIR)/i2c_application_library/i2c_application.c \ drivers/bus_i2c_timing.c \ drivers/usb_msc_common.c \ @@ -133,6 +135,8 @@ MCU_COMMON_SRC = \ msc/usbd_storage_sd_spi.c SPEED_OPTIMISED_SRC += \ + common/stm32/dshot_bitbang_shared.c \ + common/stm32/pwm_output_dshot_shared.c \ common/stm32/bus_spi_hw.c \ common/stm32/system.c diff --git a/src/platform/AT32/pwm_output_at32bsp.c b/src/platform/AT32/pwm_output_at32bsp.c index 3f67b8676c..382dbd0925 100644 --- a/src/platform/AT32/pwm_output_at32bsp.c +++ b/src/platform/AT32/pwm_output_at32bsp.c @@ -29,15 +29,13 @@ #ifdef USE_PWM_OUTPUT #include "drivers/io.h" -#include "drivers/motor.h" +#include "drivers/motor_impl.h" #include "drivers/pwm_output.h" #include "drivers/time.h" #include "drivers/timer.h" #include "pg/motor.h" -FAST_DATA_ZERO_INIT pwmOutputPort_t motors[MAX_SUPPORTED_MOTORS]; - static void pwmOCConfig(tmr_type *tim, uint8_t channel, uint16_t value, uint8_t output) { tmr_output_config_type tmr_OCInitStruct; @@ -77,13 +75,7 @@ void pwmOutConfig(timerChannel_t *channel, const timerHardware_t *timerHardware, *channel->ccr = 0; } -static FAST_DATA_ZERO_INIT motorDevice_t motorPwmDevice; - -static void pwmWriteUnused(uint8_t index, float value) -{ - UNUSED(index); - UNUSED(value); -} +static FAST_DATA_ZERO_INIT motorDevice_t *pwmMotorDevice; static void pwmWriteStandard(uint8_t index, float value) { @@ -93,7 +85,7 @@ static void pwmWriteStandard(uint8_t index, float value) void pwmShutdownPulsesForAllMotors(void) { - for (int index = 0; index < motorPwmDevice.count; index++) { + for (int index = 0; index < pwmMotorCount; index++) { // Set the compare register to 0, which stops the output pulsing if the timer overflows if (motors[index].channel.ccr) { *motors[index].channel.ccr = 0; @@ -110,17 +102,23 @@ static motorVTable_t motorPwmVTable; bool pwmEnableMotors(void) { /* check motors can be enabled */ - return (motorPwmVTable.write != &pwmWriteUnused); + return (pwmMotorDevice->vTable); } -bool pwmIsMotorEnabled(uint8_t index) +bool pwmIsMotorEnabled(unsigned index) { return motors[index].enabled; } -static void pwmCompleteOneshotMotorUpdate(void) +static bool useContinuousUpdate = true; + +static void pwmCompleteMotorUpdate(void) { - for (int index = 0; index < motorPwmDevice.count; index++) { + if (useContinuousUpdate) { + return; + } + + for (int index = 0; index < pwmMotorCount; index++) { if (motors[index].forceOverflow) { timerForceOverflow(motors[index].channel.tim); } @@ -148,58 +146,66 @@ static motorVTable_t motorPwmVTable = { .shutdown = pwmShutdownPulsesForAllMotors, .convertExternalToMotor = pwmConvertFromExternal, .convertMotorToExternal = pwmConvertToExternal, + .write = pwmWriteStandard, + .decodeTelemetry = motorDecodeTelemetryNull, + .updateComplete = pwmCompleteMotorUpdate, + .requestTelemetry = NULL, + .isMotorIdle = NULL, }; -motorDevice_t *motorPwmDevInit(const motorDevConfig_t *motorConfig, uint16_t idlePulse, uint8_t motorCount, bool useUnsyncedPwm) +bool motorPwmDevInit(motorDevice_t *device, const motorDevConfig_t *motorConfig, uint16_t idlePulse) { memset(motors, 0, sizeof(motors)); - motorPwmDevice.vTable = motorPwmVTable; + if (!device) { + return false; + } + + device->vTable = &motorPwmVTable; + pwmMotorDevice = device; + pwmMotorCount = device->count; + useContinuousUpdate = motorConfig->useContinuousUpdate; float sMin = 0; float sLen = 0; - switch (motorConfig->motorPwmProtocol) { + switch (motorConfig->motorProtocol) { default: - case PWM_TYPE_ONESHOT125: + case MOTOR_PROTOCOL_ONESHOT125: sMin = 125e-6f; sLen = 125e-6f; break; - case PWM_TYPE_ONESHOT42: + case MOTOR_PROTOCOL_ONESHOT42: sMin = 42e-6f; sLen = 42e-6f; break; - case PWM_TYPE_MULTISHOT: + case MOTOR_PROTOCOL_MULTISHOT: sMin = 5e-6f; sLen = 20e-6f; break; - case PWM_TYPE_BRUSHED: + case MOTOR_PROTOCOL_BRUSHED: sMin = 0; - useUnsyncedPwm = true; + useContinuousUpdate = true; idlePulse = 0; break; - case PWM_TYPE_STANDARD: + case MOTOR_PROTOCOL_PWM : sMin = 1e-3f; sLen = 1e-3f; - useUnsyncedPwm = true; + useContinuousUpdate = true; idlePulse = 0; break; } - motorPwmDevice.vTable.write = pwmWriteStandard; - motorPwmDevice.vTable.decodeTelemetry = motorDecodeTelemetryNull; - motorPwmDevice.vTable.updateComplete = useUnsyncedPwm ? motorUpdateCompleteNull : pwmCompleteOneshotMotorUpdate; - - for (int motorIndex = 0; motorIndex < MAX_SUPPORTED_MOTORS && motorIndex < motorCount; motorIndex++) { + for (int motorIndex = 0; motorIndex < MAX_SUPPORTED_MOTORS && motorIndex < pwmMotorCount; motorIndex++) { const unsigned reorderedMotorIndex = motorConfig->motorOutputReordering[motorIndex]; const ioTag_t tag = motorConfig->ioTags[reorderedMotorIndex]; const timerHardware_t *timerHardware = timerAllocate(tag, OWNER_MOTOR, RESOURCE_INDEX(reorderedMotorIndex)); if (timerHardware == NULL) { /* not enough motors initialised for the mixer or a break in the motors */ - motorPwmDevice.vTable.write = &pwmWriteUnused; - motorPwmDevice.vTable.updateComplete = motorUpdateCompleteNull; + device->vTable = NULL; + pwmMotorCount = 0; /* TODO: block arming and add reason system cannot arm */ - return NULL; + return false; } motors[motorIndex].io = IOGetByTag(tag); @@ -209,23 +215,23 @@ motorDevice_t *motorPwmDevInit(const motorDevConfig_t *motorConfig, uint16_t idl /* standard PWM outputs */ // margin of safety is 4 periods when unsynced - const unsigned pwmRateHz = useUnsyncedPwm ? motorConfig->motorPwmRate : ceilf(1 / ((sMin + sLen) * 4)); + const unsigned pwmRateHz = useContinuousUpdate ? motorConfig->motorPwmRate : ceilf(1 / ((sMin + sLen) * 4)); const uint32_t clock = timerClock(timerHardware->tim); /* used to find the desired timer frequency for max resolution */ const unsigned prescaler = ((clock / pwmRateHz) + 0xffff) / 0x10000; /* rounding up */ const uint32_t hz = clock / prescaler; - const unsigned period = useUnsyncedPwm ? hz / pwmRateHz : 0xffff; + const unsigned period = useContinuousUpdate ? hz / pwmRateHz : 0xffff; /* if brushed then it is the entire length of the period. TODO: this can be moved back to periodMin and periodLen once mixer outputs a 0..1 float value. */ - motors[motorIndex].pulseScale = ((motorConfig->motorPwmProtocol == PWM_TYPE_BRUSHED) ? period : (sLen * hz)) / 1000.0f; + motors[motorIndex].pulseScale = ((motorConfig->motorProtocol == MOTOR_PROTOCOL_BRUSHED) ? period : (sLen * hz)) / 1000.0f; motors[motorIndex].pulseOffset = (sMin * hz) - (motors[motorIndex].pulseScale * 1000); - pwmOutConfig(&motors[motorIndex].channel, timerHardware, hz, period, idlePulse, motorConfig->motorPwmInversion); + pwmOutConfig(&motors[motorIndex].channel, timerHardware, hz, period, idlePulse, motorConfig->motorInversion); bool timerAlreadyUsed = false; for (int i = 0; i < motorIndex; i++) { @@ -237,8 +243,7 @@ motorDevice_t *motorPwmDevInit(const motorDevConfig_t *motorConfig, uint16_t idl motors[motorIndex].forceOverflow = !timerAlreadyUsed; motors[motorIndex].enabled = true; } - - return &motorPwmDevice; + return true; } pwmOutputPort_t *pwmGetMotors(void) diff --git a/src/platform/AT32/pwm_output_dshot.c b/src/platform/AT32/pwm_output_dshot.c index 0998db708d..57b88f8efd 100644 --- a/src/platform/AT32/pwm_output_dshot.c +++ b/src/platform/AT32/pwm_output_dshot.c @@ -40,9 +40,9 @@ #include "drivers/pwm_output.h" #include "drivers/dshot.h" -#include "drivers/dshot_dpwm.h" +#include "dshot_dpwm.h" #include "drivers/dshot_command.h" -#include "drivers/pwm_output_dshot_shared.h" +#include "pwm_output_dshot_shared.h" /** * Convert from BF channel to AT32 constants for timer output channels @@ -115,9 +115,9 @@ tmr_channel_select_type toCHSelectType(const uint8_t bfChannel, const bool useNC * Called once for every dshot update if telemetry is being used (not just enabled by #def) * Called from pwm_output_dshot_shared.c pwmTelemetryDecode */ -void dshotEnableChannels(uint8_t motorCount) +void dshotEnableChannels(unsigned motorCount) { - for (int i = 0; i < motorCount; i++) { + for (unsigned i = 0; i < motorCount; i++) { tmr_primary_mode_select(dmaMotors[i].timerHardware->tim, TMR_PRIMARY_SEL_COMPARE); tmr_channel_select_type atCh = toCHSelectType(dmaMotors[i].timerHardware->channel, dmaMotors[i].output & TIMER_OUTPUT_N_CHANNEL); @@ -131,7 +131,7 @@ void dshotEnableChannels(uint8_t motorCount) * Set the timer and dma of the specified motor for use as an output * * Called from pwmDshotMotorHardwareConfig in this file and also from - * pwmTelemetryDecode in src/main/drivers/pwm_output_dshot_shared.c + * pwmTelemetryDecode in src/main/common/stm32/pwm_output_dshot_shared.c */ FAST_CODE void pwmDshotSetDirectionOutput( motorDmaOutput_t * const motor @@ -250,7 +250,7 @@ void pwmCompleteDshotMotorUpdate(void) { // If there is a dshot command loaded up, time it correctly with motor update if (!dshotCommandQueueEmpty()) { - if (!dshotCommandOutputIsEnabled(dshotPwmDevice.count)) { + if (!dshotCommandOutputIsEnabled(dshotMotorCount)) { return; } } @@ -361,7 +361,7 @@ FAST_CODE static void motor_DMA_IRQHandler(dmaChannelDescriptor_t *descriptor) } bool pwmDshotMotorHardwareConfig(const timerHardware_t *timerHardware, uint8_t motorIndex, uint8_t reorderedMotorIndex, - motorPwmProtocolTypes_e pwmProtocolType, uint8_t output) + motorProtocolTypes_e pwmProtocolType, uint8_t output) { #ifdef USE_DSHOT_TELEMETRY #define OCINIT motor->ocInitStruct @@ -451,7 +451,7 @@ bool pwmDshotMotorHardwareConfig(const timerHardware_t *timerHardware, uint8_t m tmr_counter_enable(timer, FALSE); uint32_t prescaler = (uint16_t)(lrintf((float) timerClock(timer) / getDshotHz(pwmProtocolType) + 0.01f) - 1); - uint32_t period = (pwmProtocolType == PWM_TYPE_PROSHOT1000 ? (MOTOR_NIBBLE_LENGTH_PROSHOT) : MOTOR_BITLENGTH) - 1; + uint32_t period = (pwmProtocolType == MOTOR_PROTOCOL_PROSHOT1000 ? (MOTOR_NIBBLE_LENGTH_PROSHOT) : MOTOR_BITLENGTH) - 1; tmr_clock_source_div_set(timer, TMR_CLOCK_DIV1); tmr_repetition_counter_set(timer, 0); @@ -523,7 +523,7 @@ bool pwmDshotMotorHardwareConfig(const timerHardware_t *timerHardware, uint8_t m DMAINIT.DMA_PeripheralBurst = DMA_PeripheralBurst_Single; DMAINIT.DMA_PeripheralBaseAddr = (uint32_t)&timerHardware->tim->DMAR; - DMAINIT.DMA_BufferSize = (pwmProtocolType == PWM_TYPE_PROSHOT1000) ? PROSHOT_DMA_BUFFER_SIZE : DSHOT_DMA_BUFFER_SIZE; // XXX + DMAINIT.DMA_BufferSize = (pwmProtocolType == MOTOR_PROTOCOL_PROSHOT1000) ? PROSHOT_DMA_BUFFER_SIZE : DSHOT_DMA_BUFFER_SIZE; // XXX DMAINIT.DMA_PeripheralInc = DMA_PeripheralInc_Disable; DMAINIT.DMA_MemoryInc = DMA_MemoryInc_Enable; DMAINIT.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Word; @@ -551,7 +551,7 @@ bool pwmDshotMotorHardwareConfig(const timerHardware_t *timerHardware, uint8_t m #ifdef USE_DSHOT_TELEMETRY motor->dshotTelemetryDeadtimeUs = DSHOT_TELEMETRY_DEADTIME_US + 1000000 * (16 * MOTOR_BITLENGTH) / getDshotHz(pwmProtocolType); - motor->timer->outputPeriod = (pwmProtocolType == PWM_TYPE_PROSHOT1000 ? (MOTOR_NIBBLE_LENGTH_PROSHOT) : MOTOR_BITLENGTH) - 1; + motor->timer->outputPeriod = (pwmProtocolType == MOTOR_PROTOCOL_PROSHOT1000 ? (MOTOR_NIBBLE_LENGTH_PROSHOT) : MOTOR_BITLENGTH) - 1; pwmDshotSetDirectionOutput(motor); #else pwmDshotSetDirectionOutput(motor, &OCINIT, &DMAINIT); diff --git a/src/platform/SIMULATOR/sitl.c b/src/platform/SIMULATOR/sitl.c index 2325107ae2..f4c9980d63 100644 --- a/src/platform/SIMULATOR/sitl.c +++ b/src/platform/SIMULATOR/sitl.c @@ -32,7 +32,7 @@ #include "drivers/io.h" #include "drivers/dma.h" -#include "drivers/motor.h" +#include "drivers/motor_impl.h" #include "drivers/serial.h" #include "drivers/serial_tcp.h" #include "drivers/system.h" @@ -520,7 +520,6 @@ int timeval_sub(struct timespec *result, struct timespec *x, struct timespec *y) } // PWM part -pwmOutputPort_t motors[MAX_SUPPORTED_MOTORS]; static pwmOutputPort_t servos[MAX_SUPPORTED_SERVOS]; // real value to send @@ -537,7 +536,7 @@ void servoDevInit(const servoDevConfig_t *servoConfig) } } -static motorDevice_t motorPwmDevice; // Forward +static motorDevice_t pwmMotorDevice; // Forward pwmOutputPort_t *pwmGetMotors(void) { @@ -556,12 +555,12 @@ static uint16_t pwmConvertToExternal(float motorValue) static void pwmDisableMotors(void) { - motorPwmDevice.enabled = false; + pwmMotorDevice.enabled = false; } static bool pwmEnableMotors(void) { - motorPwmDevice.enabled = true; + pwmMotorDevice.enabled = true; return true; } @@ -588,10 +587,10 @@ static void pwmWriteMotorInt(uint8_t index, uint16_t value) static void pwmShutdownPulsesForAllMotors(void) { - motorPwmDevice.enabled = false; + pwmMotorDevice.enabled = false; } -bool pwmIsMotorEnabled(uint8_t index) +bool pwmIsMotorEnabled(unsigned index) { return motors[index].enabled; } @@ -627,27 +626,32 @@ void pwmWriteServo(uint8_t index, float value) } } -static motorDevice_t motorPwmDevice = { - .vTable = { - .postInit = motorPostInitNull, - .convertExternalToMotor = pwmConvertFromExternal, - .convertMotorToExternal = pwmConvertToExternal, - .enable = pwmEnableMotors, - .disable = pwmDisableMotors, - .isMotorEnabled = pwmIsMotorEnabled, - .decodeTelemetry = motorDecodeTelemetryNull, - .write = pwmWriteMotor, - .writeInt = pwmWriteMotorInt, - .updateComplete = pwmCompleteMotorUpdate, - .shutdown = pwmShutdownPulsesForAllMotors, - } +static const motorVTable_t vTable = { + .postInit = motorPostInitNull, + .convertExternalToMotor = pwmConvertFromExternal, + .convertMotorToExternal = pwmConvertToExternal, + .enable = pwmEnableMotors, + .disable = pwmDisableMotors, + .isMotorEnabled = pwmIsMotorEnabled, + .decodeTelemetry = motorDecodeTelemetryNull, + .write = pwmWriteMotor, + .writeInt = pwmWriteMotorInt, + .updateComplete = pwmCompleteMotorUpdate, + .shutdown = pwmShutdownPulsesForAllMotors, + .requestTelemetry = NULL, + .isMotorIdle = NULL, + }; -motorDevice_t *motorPwmDevInit(const motorDevConfig_t *motorConfig, uint16_t _idlePulse, uint8_t motorCount, bool useUnsyncedPwm) +bool motorPwmDevInit(motorDevice_t *device, const motorDevConfig_t *motorConfig, uint16_t _idlePulse) { UNUSED(motorConfig); - UNUSED(useUnsyncedPwm); + if (!device) { + return false; + } + device->vTable = &vTable; + const uint8_t motorCount = device->count; printf("Initialized motor count %d\n", motorCount); pwmRawPkt.motorCount = motorCount; @@ -656,11 +660,8 @@ motorDevice_t *motorPwmDevInit(const motorDevConfig_t *motorConfig, uint16_t _id for (int motorIndex = 0; motorIndex < MAX_SUPPORTED_MOTORS && motorIndex < motorCount; motorIndex++) { motors[motorIndex].enabled = true; } - motorPwmDevice.count = motorCount; // Never used, but seemingly a right thing to set it anyways. - motorPwmDevice.initialized = true; - motorPwmDevice.enabled = false; - return &motorPwmDevice; + return true; } // ADC part diff --git a/src/platform/STM32/dshot_bitbang.c b/src/platform/STM32/dshot_bitbang.c index b6d98d3fc8..3cf7db42ce 100644 --- a/src/platform/STM32/dshot_bitbang.c +++ b/src/platform/STM32/dshot_bitbang.c @@ -35,12 +35,11 @@ #include "drivers/dma_reqmap.h" #include "drivers/dshot.h" #include "drivers/dshot_bitbang.h" -#include "drivers/dshot_bitbang_impl.h" +#include "dshot_bitbang_impl.h" #include "drivers/dshot_command.h" #include "drivers/motor.h" #include "drivers/nvic.h" -#include "drivers/pwm_output.h" // XXX for pwmOutputPort_t motors[]; should go away with refactoring -#include "drivers/dshot_dpwm.h" // XXX for motorDmaOutput_t *getMotorDmaOutput(uint8_t index); should go away with refactoring +#include "pwm_output_dshot_shared.h" #include "drivers/dshot_bitbang_decode.h" #include "drivers/time.h" #include "drivers/timer.h" @@ -57,17 +56,6 @@ // Maximum time to wait for telemetry reception to complete #define DSHOT_TELEMETRY_TIMEOUT 2000 -FAST_DATA_ZERO_INIT bbPacer_t bbPacers[MAX_MOTOR_PACERS]; // TIM1 or TIM8 -FAST_DATA_ZERO_INIT int usedMotorPacers = 0; - -FAST_DATA_ZERO_INIT bbPort_t bbPorts[MAX_SUPPORTED_MOTOR_PORTS]; -FAST_DATA_ZERO_INIT int usedMotorPorts; - -FAST_DATA_ZERO_INIT bbMotor_t bbMotors[MAX_SUPPORTED_MOTORS]; - -static FAST_DATA_ZERO_INIT int motorCount; -dshotBitbangStatus_e bbStatus; - // For MCUs that use MPU to control DMA coherency, there might be a performance hit // on manipulating input buffer content especially if it is read multiple times, // as the buffer region is attributed as not cachable. @@ -134,10 +122,9 @@ const timerHardware_t bbTimerHardware[] = { #endif }; -static FAST_DATA_ZERO_INIT motorDevice_t bbDevice; static FAST_DATA_ZERO_INIT timeUs_t lastSendUs; -static motorPwmProtocolTypes_e motorPwmProtocol; +static motorProtocolTypes_e motorProtocol; // DMA GPIO output buffer formatting @@ -287,15 +274,15 @@ const resourceOwner_t *dshotBitbangTimerGetOwner(const timerHardware_t *timer) // Return frequency of smallest change [state/sec] -static uint32_t getDshotBaseFrequency(motorPwmProtocolTypes_e pwmProtocolType) +static uint32_t getDshotBaseFrequency(motorProtocolTypes_e pwmProtocolType) { switch (pwmProtocolType) { - case(PWM_TYPE_DSHOT600): + case(MOTOR_PROTOCOL_DSHOT600): return MOTOR_DSHOT600_SYMBOL_RATE * MOTOR_DSHOT_STATE_PER_SYMBOL; - case(PWM_TYPE_DSHOT300): + case(MOTOR_PROTOCOL_DSHOT300): return MOTOR_DSHOT300_SYMBOL_RATE * MOTOR_DSHOT_STATE_PER_SYMBOL; default: - case(PWM_TYPE_DSHOT150): + case(MOTOR_PROTOCOL_DSHOT150): return MOTOR_DSHOT150_SYMBOL_RATE * MOTOR_DSHOT_STATE_PER_SYMBOL; } } @@ -408,7 +395,7 @@ static void bbFindPacerTimer(void) } } -static void bbTimebaseSetup(bbPort_t *bbPort, motorPwmProtocolTypes_e dshotProtocolType) +static void bbTimebaseSetup(bbPort_t *bbPort, motorProtocolTypes_e dshotProtocolType) { uint32_t timerclock = timerClock(bbPort->timhw->tim); @@ -426,7 +413,7 @@ static void bbTimebaseSetup(bbPort_t *bbPort, motorPwmProtocolTypes_e dshotProto // it does not use the timer channel associated with the pin. // -static bool bbMotorConfig(IO_t io, uint8_t motorIndex, motorPwmProtocolTypes_e pwmProtocolType, uint8_t output) +static bool bbMotorConfig(IO_t io, uint8_t motorIndex, motorProtocolTypes_e pwmProtocolType, uint8_t output) { // Return if no GPIO is specified if (!io) { @@ -458,10 +445,6 @@ static bool bbMotorConfig(IO_t io, uint8_t motorIndex, motorPwmProtocolTypes_e p } if (!bbPort || !dmaAllocate(dmaGetIdentifier(bbPort->dmaResource), bbPort->owner.owner, bbPort->owner.resourceIndex)) { - bbDevice.vTable.write = motorWriteNull; - bbDevice.vTable.decodeTelemetry = motorDecodeTelemetryNull; - bbDevice.vTable.updateComplete = motorUpdateCompleteNull; - return false; } @@ -559,7 +542,7 @@ static bool bbDecodeTelemetry(void) SCB_InvalidateDCache_by_Addr((uint32_t *)bbPort->portInputBuffer, DSHOT_BB_PORT_IP_BUF_CACHE_ALIGN_BYTES); } #endif - for (int motorIndex = 0; motorIndex < MAX_SUPPORTED_MOTORS && motorIndex < motorCount; motorIndex++) { + for (int motorIndex = 0; motorIndex < MAX_SUPPORTED_MOTORS && motorIndex < dshotMotorCount; motorIndex++) { #ifdef STM32F4 uint32_t rawValue = decode_bb_bitband( bbMotors[motorIndex].bbPort->portInputBuffer, @@ -608,11 +591,6 @@ static void bbWriteInt(uint8_t motorIndex, uint16_t value) return; } - // fetch requestTelemetry from motors. Needs to be refactored. - motorDmaOutput_t * const motor = getMotorDmaOutput(motorIndex); - bbmotor->protocolControl.requestTelemetry = motor->protocolControl.requestTelemetry; - motor->protocolControl.requestTelemetry = false; - // If there is a command ready to go overwrite the value and send that instead if (dshotCommandIsProcessing()) { value = dshotCommandGetCurrent(motorIndex); @@ -647,7 +625,7 @@ static void bbUpdateComplete(void) // If there is a dshot command loaded up, time it correctly with motor update if (!dshotCommandQueueEmpty()) { - if (!dshotCommandOutputIsEnabled(bbDevice.count)) { + if (!dshotCommandOutputIsEnabled(dshotMotorCount)) { return; } } @@ -685,7 +663,7 @@ static void bbUpdateComplete(void) static bool bbEnableMotors(void) { - for (int i = 0; i < motorCount; i++) { + for (int i = 0; i < dshotMotorCount; i++) { if (bbMotors[i].configured) { IOConfigGPIO(bbMotors[i].io, bbMotors[i].iocfg); } @@ -703,7 +681,7 @@ static void bbShutdown(void) return; } -static bool bbIsMotorEnabled(uint8_t index) +static bool bbIsMotorEnabled(unsigned index) { return bbMotors[index].enabled; } @@ -712,21 +690,17 @@ static void bbPostInit(void) { bbFindPacerTimer(); - for (int motorIndex = 0; motorIndex < MAX_SUPPORTED_MOTORS && motorIndex < motorCount; motorIndex++) { + for (int motorIndex = 0; motorIndex < MAX_SUPPORTED_MOTORS && motorIndex < dshotMotorCount; motorIndex++) { - if (!bbMotorConfig(bbMotors[motorIndex].io, motorIndex, motorPwmProtocol, bbMotors[motorIndex].output)) { + if (!bbMotorConfig(bbMotors[motorIndex].io, motorIndex, motorProtocol, bbMotors[motorIndex].output)) { return; } bbMotors[motorIndex].enabled = true; - - // Fill in motors structure for 4way access (XXX Should be refactored) - - motors[motorIndex].enabled = true; } } -static motorVTable_t bbVTable = { +static const motorVTable_t bbVTable = { .postInit = bbPostInit, .enable = bbEnableMotors, .disable = bbDisableMotors, @@ -740,6 +714,8 @@ static motorVTable_t bbVTable = { .convertExternalToMotor = dshotConvertFromExternal, .convertMotorToExternal = dshotConvertToExternal, .shutdown = bbShutdown, + .isMotorIdle = bbDshotIsMotorIdle, + .requestTelemetry = bbDshotRequestTelemetry, }; dshotBitbangStatus_e dshotBitbangGetStatus(void) @@ -747,14 +723,19 @@ dshotBitbangStatus_e dshotBitbangGetStatus(void) return bbStatus; } -motorDevice_t *dshotBitbangDevInit(const motorDevConfig_t *motorConfig, uint8_t count) +bool dshotBitbangDevInit(motorDevice_t *device, const motorDevConfig_t *motorConfig) { dbgPinLo(0); dbgPinLo(1); - motorPwmProtocol = motorConfig->motorPwmProtocol; - bbDevice.vTable = bbVTable; - motorCount = count; + if (!device || !motorConfig) { + return false; + } + + motorProtocol = motorConfig->motorProtocol; + device->vTable = &bbVTable; + + dshotMotorCount = device->count; bbStatus = DSHOT_BITBANG_STATUS_OK; #ifdef USE_DSHOT_TELEMETRY @@ -763,12 +744,12 @@ motorDevice_t *dshotBitbangDevInit(const motorDevConfig_t *motorConfig, uint8_t memset(bbOutputBuffer, 0, sizeof(bbOutputBuffer)); - for (int motorIndex = 0; motorIndex < MAX_SUPPORTED_MOTORS && motorIndex < motorCount; motorIndex++) { + for (int motorIndex = 0; motorIndex < MAX_SUPPORTED_MOTORS && motorIndex < dshotMotorCount; motorIndex++) { const unsigned reorderedMotorIndex = motorConfig->motorOutputReordering[motorIndex]; const timerHardware_t *timerHardware = timerGetConfiguredByTag(motorConfig->ioTags[reorderedMotorIndex]); const IO_t io = IOGetByTag(motorConfig->ioTags[reorderedMotorIndex]); - uint8_t output = motorConfig->motorPwmInversion ? timerHardware->output ^ TIMER_OUTPUT_INVERTED : timerHardware->output; + uint8_t output = motorConfig->motorInversion ? timerHardware->output ^ TIMER_OUTPUT_INVERTED : timerHardware->output; bbPuPdMode = (output & TIMER_OUTPUT_INVERTED) ? BB_GPIO_PULLDOWN : BB_GPIO_PULLUP; #ifdef USE_DSHOT_TELEMETRY @@ -779,11 +760,10 @@ motorDevice_t *dshotBitbangDevInit(const motorDevConfig_t *motorConfig, uint8_t if (!IOIsFreeOrPreinit(io)) { /* not enough motors initialised for the mixer or a break in the motors */ - bbDevice.vTable.write = motorWriteNull; - bbDevice.vTable.decodeTelemetry = motorDecodeTelemetryNull; - bbDevice.vTable.updateComplete = motorUpdateCompleteNull; + device->vTable = NULL; + dshotMotorCount = 0; bbStatus = DSHOT_BITBANG_STATUS_MOTOR_PIN_CONFLICT; - return NULL; + return false; } int pinIndex = IO_GPIOPinIdx(io); @@ -804,12 +784,9 @@ motorDevice_t *dshotBitbangDevInit(const motorDevConfig_t *motorConfig, uint8_t } else { IOHi(io); } - - // Fill in motors structure for 4way access (XXX Should be refactored) - motors[motorIndex].io = bbMotors[motorIndex].io; } - return &bbDevice; + return true; } #endif // USE_DSHOT_BB diff --git a/src/platform/STM32/dshot_bitbang_ll.c b/src/platform/STM32/dshot_bitbang_ll.c index 2c6014fb97..dffd0ed77c 100644 --- a/src/platform/STM32/dshot_bitbang_ll.c +++ b/src/platform/STM32/dshot_bitbang_ll.c @@ -34,13 +34,14 @@ #include "drivers/dma.h" #include "drivers/dma_reqmap.h" #include "drivers/dshot.h" -#include "drivers/dshot_bitbang_impl.h" +#include "dshot_bitbang_impl.h" #include "drivers/dshot_command.h" #include "drivers/motor.h" #include "drivers/nvic.h" #include "drivers/pwm_output.h" // XXX for pwmOutputPort_t motors[]; should go away with refactoring #include "drivers/time.h" #include "drivers/timer.h" +#include "pwm_output_dshot_shared.h" #include "pg/motor.h" diff --git a/src/platform/STM32/dshot_bitbang_stdperiph.c b/src/platform/STM32/dshot_bitbang_stdperiph.c index bafe2671ce..122f2f5718 100644 --- a/src/platform/STM32/dshot_bitbang_stdperiph.c +++ b/src/platform/STM32/dshot_bitbang_stdperiph.c @@ -35,11 +35,10 @@ #include "drivers/dma.h" #include "drivers/dma_reqmap.h" #include "drivers/dshot.h" -#include "drivers/dshot_bitbang_impl.h" +#include "dshot_bitbang_impl.h" #include "drivers/dshot_command.h" #include "drivers/motor.h" #include "drivers/nvic.h" -#include "drivers/pwm_output.h" // XXX for pwmOutputPort_t motors[]; should go away with refactoring #include "drivers/time.h" #include "drivers/timer.h" diff --git a/src/platform/STM32/mk/STM32F4.mk b/src/platform/STM32/mk/STM32F4.mk index 09ac1e719d..e41e3db33b 100644 --- a/src/platform/STM32/mk/STM32F4.mk +++ b/src/platform/STM32/mk/STM32F4.mk @@ -179,7 +179,6 @@ MCU_COMMON_SRC = \ drivers/accgyro/accgyro_mpu.c \ drivers/dshot_bitbang_decode.c \ drivers/inverter.c \ - drivers/pwm_output_dshot_shared.c \ STM32/pwm_output_dshot.c \ STM32/adc_stm32f4xx.c \ STM32/bus_i2c_stm32f4xx.c \ @@ -193,7 +192,6 @@ MCU_COMMON_SRC = \ STM32/io_stm32.c \ STM32/light_ws2811strip_stdperiph.c \ STM32/persistent.c \ - STM32/pwm_output.c \ STM32/rcc_stm32.c \ STM32/sdio_f4xx.c \ STM32/serial_uart_stdperiph.c \ diff --git a/src/platform/STM32/mk/STM32F7.mk b/src/platform/STM32/mk/STM32F7.mk index 5e035639c2..f68fd69525 100644 --- a/src/platform/STM32/mk/STM32F7.mk +++ b/src/platform/STM32/mk/STM32F7.mk @@ -143,7 +143,6 @@ MCU_COMMON_SRC = \ drivers/accgyro/accgyro_mpu.c \ drivers/bus_i2c_timing.c \ drivers/dshot_bitbang_decode.c \ - drivers/pwm_output_dshot_shared.c \ STM32/adc_stm32f7xx.c \ STM32/audio_stm32f7xx.c \ STM32/bus_i2c_hal_init.c \ @@ -158,7 +157,6 @@ MCU_COMMON_SRC = \ STM32/io_stm32.c \ STM32/light_ws2811strip_hal.c \ STM32/persistent.c \ - STM32/pwm_output.c \ STM32/pwm_output_dshot_hal.c \ STM32/rcc_stm32.c \ STM32/sdio_f7xx.c \ @@ -189,7 +187,6 @@ SPEED_OPTIMISED_SRC += \ STM32/bus_i2c_hal.c \ STM32/bus_spi_ll.c \ drivers/max7456.c \ - drivers/pwm_output_dshot_shared.c \ STM32/pwm_output_dshot_hal.c \ STM32/exti.c diff --git a/src/platform/STM32/mk/STM32G4.mk b/src/platform/STM32/mk/STM32G4.mk index 2761c42bea..38cf7cdbdd 100644 --- a/src/platform/STM32/mk/STM32G4.mk +++ b/src/platform/STM32/mk/STM32G4.mk @@ -120,7 +120,6 @@ MCU_COMMON_SRC = \ drivers/accgyro/accgyro_mpu.c \ drivers/bus_i2c_timing.c \ drivers/dshot_bitbang_decode.c \ - drivers/pwm_output_dshot_shared.c \ STM32/adc_stm32g4xx.c \ STM32/bus_i2c_hal_init.c \ STM32/bus_i2c_hal.c \ @@ -136,7 +135,6 @@ MCU_COMMON_SRC = \ STM32/memprot_hal.c \ STM32/memprot_stm32g4xx.c \ STM32/persistent.c \ - STM32/pwm_output.c \ STM32/pwm_output_dshot_hal.c \ STM32/rcc_stm32.c \ STM32/serial_uart_hal.c \ diff --git a/src/platform/STM32/mk/STM32H5.mk b/src/platform/STM32/mk/STM32H5.mk index 4cfd67a706..90a30cc32b 100644 --- a/src/platform/STM32/mk/STM32H5.mk +++ b/src/platform/STM32/mk/STM32H5.mk @@ -151,7 +151,6 @@ MCU_COMMON_SRC = \ drivers/bus_i2c_timing.c \ drivers/bus_quadspi.c \ drivers/dshot_bitbang_decode.c \ - drivers/pwm_output_dshot_shared.c \ STM32/bus_i2c_hal_init.c \ STM32/bus_i2c_hal.c \ STM32/bus_spi_ll.c \ @@ -164,7 +163,6 @@ MCU_COMMON_SRC = \ STM32/io_stm32.c \ STM32/light_ws2811strip_hal.c \ STM32/persistent.c \ - STM32/pwm_output.c \ STM32/pwm_output_dshot_hal.c \ STM32/rcc_stm32.c \ STM32/serial_uart_hal.c \ diff --git a/src/platform/STM32/mk/STM32H7.mk b/src/platform/STM32/mk/STM32H7.mk index 8302a6733b..edcd2c27b8 100644 --- a/src/platform/STM32/mk/STM32H7.mk +++ b/src/platform/STM32/mk/STM32H7.mk @@ -266,7 +266,6 @@ MCU_COMMON_SRC = \ drivers/bus_i2c_timing.c \ drivers/bus_quadspi.c \ drivers/dshot_bitbang_decode.c \ - drivers/pwm_output_dshot_shared.c \ STM32/adc_stm32h7xx.c \ STM32/audio_stm32h7xx.c \ STM32/bus_i2c_hal_init.c \ @@ -285,7 +284,6 @@ MCU_COMMON_SRC = \ STM32/memprot_hal.c \ STM32/memprot_stm32h7xx.c \ STM32/persistent.c \ - STM32/pwm_output.c \ STM32/pwm_output_dshot_hal.c \ STM32/rcc_stm32.c \ STM32/sdio_h7xx.c \ diff --git a/src/platform/STM32/mk/STM32_COMMON.mk b/src/platform/STM32/mk/STM32_COMMON.mk index fe3da3c251..a70deb0de2 100644 --- a/src/platform/STM32/mk/STM32_COMMON.mk +++ b/src/platform/STM32/mk/STM32_COMMON.mk @@ -9,7 +9,11 @@ MCU_COMMON_SRC += \ drivers/bus_spi_config.c \ common/stm32/bus_spi_hw.c \ common/stm32/io_impl.c \ - common/stm32/serial_uart_hw.c + common/stm32/serial_uart_hw.c \ + common/stm32/dshot_dpwm.c \ + STM32/pwm_output_hw.c \ + common/stm32/pwm_output_dshot_shared.c \ + common/stm32/dshot_bitbang_shared.c SIZE_OPTIMISED_SRC += \ drivers/bus_i2c_config.c \ @@ -20,5 +24,8 @@ SIZE_OPTIMISED_SRC += \ SPEED_OPTIMISED_SRC += \ common/stm32/system.c \ common/stm32/bus_spi_hw.c \ + common/stm32/pwm_output_dshot_shared.c \ + STM32/pwm_output_hw.c \ + common/stm32/dshot_bitbang_shared.c \ common/stm32/io_impl.c diff --git a/src/platform/STM32/pwm_output_dshot.c b/src/platform/STM32/pwm_output_dshot.c index 033a10907c..dcf2bba859 100644 --- a/src/platform/STM32/pwm_output_dshot.c +++ b/src/platform/STM32/pwm_output_dshot.c @@ -42,15 +42,15 @@ #include "drivers/pwm_output.h" #include "drivers/dshot.h" -#include "drivers/dshot_dpwm.h" +#include "dshot_dpwm.h" #include "drivers/dshot_command.h" -#include "drivers/pwm_output_dshot_shared.h" +#include "pwm_output_dshot_shared.h" #ifdef USE_DSHOT_TELEMETRY -void dshotEnableChannels(uint8_t motorCount) +void dshotEnableChannels(unsigned motorCount) { - for (int i = 0; i < motorCount; i++) { + for (unsigned i = 0; i < motorCount; i++) { if (dmaMotors[i].output & TIMER_OUTPUT_N_CHANNEL) { TIM_CCxNCmd(dmaMotors[i].timerHardware->tim, dmaMotors[i].timerHardware->channel, TIM_CCxN_Enable); } else { @@ -144,7 +144,7 @@ void pwmCompleteDshotMotorUpdate(void) { /* If there is a dshot command loaded up, time it correctly with motor update*/ if (!dshotCommandQueueEmpty()) { - if (!dshotCommandOutputIsEnabled(dshotPwmDevice.count)) { + if (!dshotCommandOutputIsEnabled(pwmMotorCount)) { return; } } @@ -200,7 +200,7 @@ FAST_CODE static void motor_DMA_IRQHandler(dmaChannelDescriptor_t *descriptor) } } -bool pwmDshotMotorHardwareConfig(const timerHardware_t *timerHardware, uint8_t motorIndex, uint8_t reorderedMotorIndex, motorPwmProtocolTypes_e pwmProtocolType, uint8_t output) +bool pwmDshotMotorHardwareConfig(const timerHardware_t *timerHardware, uint8_t motorIndex, uint8_t reorderedMotorIndex, motorProtocolTypes_e pwmProtocolType, uint8_t output) { #ifdef USE_DSHOT_TELEMETRY #define OCINIT motor->ocInitStruct @@ -299,7 +299,7 @@ bool pwmDshotMotorHardwareConfig(const timerHardware_t *timerHardware, uint8_t m TIM_Cmd(timer, DISABLE); TIM_TimeBaseStructure.TIM_Prescaler = (uint16_t)(lrintf((float) timerClock(timer) / getDshotHz(pwmProtocolType) + 0.01f) - 1); - TIM_TimeBaseStructure.TIM_Period = (pwmProtocolType == PWM_TYPE_PROSHOT1000 ? (MOTOR_NIBBLE_LENGTH_PROSHOT) : MOTOR_BITLENGTH) - 1; + TIM_TimeBaseStructure.TIM_Period = (pwmProtocolType == MOTOR_PROTOCOL_PROSHOT1000 ? (MOTOR_NIBBLE_LENGTH_PROSHOT) : MOTOR_BITLENGTH) - 1; TIM_TimeBaseStructure.TIM_ClockDivision = TIM_CKD_DIV1; TIM_TimeBaseStructure.TIM_RepetitionCounter = 0; TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up; @@ -359,7 +359,7 @@ bool pwmDshotMotorHardwareConfig(const timerHardware_t *timerHardware, uint8_t m DMAINIT.DMA_PeripheralBurst = DMA_PeripheralBurst_Single; DMAINIT.DMA_PeripheralBaseAddr = (uint32_t)&timerHardware->tim->DMAR; - DMAINIT.DMA_BufferSize = (pwmProtocolType == PWM_TYPE_PROSHOT1000) ? PROSHOT_DMA_BUFFER_SIZE : DSHOT_DMA_BUFFER_SIZE; // XXX + DMAINIT.DMA_BufferSize = (pwmProtocolType == MOTOR_PROTOCOL_PROSHOT1000) ? PROSHOT_DMA_BUFFER_SIZE : DSHOT_DMA_BUFFER_SIZE; // XXX DMAINIT.DMA_PeripheralInc = DMA_PeripheralInc_Disable; DMAINIT.DMA_MemoryInc = DMA_MemoryInc_Enable; DMAINIT.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Word; @@ -396,7 +396,7 @@ bool pwmDshotMotorHardwareConfig(const timerHardware_t *timerHardware, uint8_t m #ifdef USE_DSHOT_TELEMETRY motor->dshotTelemetryDeadtimeUs = DSHOT_TELEMETRY_DEADTIME_US + 1000000 * (16 * MOTOR_BITLENGTH) / getDshotHz(pwmProtocolType); - motor->timer->outputPeriod = (pwmProtocolType == PWM_TYPE_PROSHOT1000 ? (MOTOR_NIBBLE_LENGTH_PROSHOT) : MOTOR_BITLENGTH) - 1; + motor->timer->outputPeriod = (pwmProtocolType == MOTOR_PROTOCOL_PROSHOT1000 ? (MOTOR_NIBBLE_LENGTH_PROSHOT) : MOTOR_BITLENGTH) - 1; pwmDshotSetDirectionOutput(motor); #else pwmDshotSetDirectionOutput(motor, &OCINIT, &DMAINIT); diff --git a/src/platform/STM32/pwm_output_dshot_hal.c b/src/platform/STM32/pwm_output_dshot_hal.c index 15d5a31fe2..3e6fe722a3 100644 --- a/src/platform/STM32/pwm_output_dshot_hal.c +++ b/src/platform/STM32/pwm_output_dshot_hal.c @@ -33,13 +33,13 @@ #include "drivers/dma.h" #include "drivers/dma_reqmap.h" #include "drivers/dshot.h" -#include "drivers/dshot_dpwm.h" +#include "dshot_dpwm.h" #include "drivers/dshot_command.h" #include "drivers/io.h" #include "drivers/nvic.h" #include "drivers/motor.h" #include "drivers/pwm_output.h" -#include "drivers/pwm_output_dshot_shared.h" +#include "pwm_output_dshot_shared.h" #include "drivers/rcc.h" #include "drivers/time.h" #include "drivers/timer.h" @@ -47,9 +47,9 @@ #ifdef USE_DSHOT_TELEMETRY -void dshotEnableChannels(uint8_t motorCount) +void dshotEnableChannels(unsigned motorCount) { - for (int i = 0; i < motorCount; i++) { + for (unsigned i = 0; i < motorCount; i++) { if (dmaMotors[i].output & TIMER_OUTPUT_N_CHANNEL) { LL_EX_TIM_CC_EnableNChannel(dmaMotors[i].timerHardware->tim, dmaMotors[i].llChannel); } else { @@ -138,7 +138,7 @@ FAST_CODE static void pwmDshotSetDirectionInput( FAST_CODE void pwmCompleteDshotMotorUpdate(void) { /* If there is a dshot command loaded up, time it correctly with motor update*/ - if (!dshotCommandQueueEmpty() && !dshotCommandOutputIsEnabled(dshotPwmDevice.count)) { + if (!dshotCommandQueueEmpty() && !dshotCommandOutputIsEnabled(dshotMotorCount)) { return; } @@ -200,7 +200,7 @@ FAST_CODE static void motor_DMA_IRQHandler(dmaChannelDescriptor_t* descriptor) } } -bool pwmDshotMotorHardwareConfig(const timerHardware_t *timerHardware, uint8_t motorIndex, uint8_t reorderedMotorIndex, motorPwmProtocolTypes_e pwmProtocolType, uint8_t output) +bool pwmDshotMotorHardwareConfig(const timerHardware_t *timerHardware, uint8_t motorIndex, uint8_t reorderedMotorIndex, motorProtocolTypes_e pwmProtocolType, uint8_t output) { #ifdef USE_DSHOT_TELEMETRY #define OCINIT motor->ocInitStruct @@ -297,7 +297,7 @@ bool pwmDshotMotorHardwareConfig(const timerHardware_t *timerHardware, uint8_t m LL_TIM_DisableCounter(timer); init.Prescaler = (uint16_t)(lrintf((float) timerClock(timer) / getDshotHz(pwmProtocolType) + 0.01f) - 1); - init.Autoreload = (pwmProtocolType == PWM_TYPE_PROSHOT1000 ? MOTOR_NIBBLE_LENGTH_PROSHOT : MOTOR_BITLENGTH) - 1; + init.Autoreload = (pwmProtocolType == MOTOR_PROTOCOL_PROSHOT1000 ? MOTOR_NIBBLE_LENGTH_PROSHOT : MOTOR_BITLENGTH) - 1; init.ClockDivision = LL_TIM_CLOCKDIVISION_DIV1; init.RepetitionCounter = 0; init.CounterMode = LL_TIM_COUNTERMODE_UP; @@ -391,7 +391,7 @@ bool pwmDshotMotorHardwareConfig(const timerHardware_t *timerHardware, uint8_t m DMAINIT.MemBurst = LL_DMA_MBURST_SINGLE; DMAINIT.PeriphBurst = LL_DMA_PBURST_SINGLE; #endif - DMAINIT.NbData = pwmProtocolType == PWM_TYPE_PROSHOT1000 ? PROSHOT_DMA_BUFFER_SIZE : DSHOT_DMA_BUFFER_SIZE; + DMAINIT.NbData = pwmProtocolType == MOTOR_PROTOCOL_PROSHOT1000 ? PROSHOT_DMA_BUFFER_SIZE : DSHOT_DMA_BUFFER_SIZE; DMAINIT.PeriphOrM2MSrcIncMode = LL_DMA_PERIPH_NOINCREMENT; DMAINIT.MemoryOrM2MDstIncMode = LL_DMA_MEMORY_INCREMENT; DMAINIT.PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_WORD; @@ -409,7 +409,7 @@ bool pwmDshotMotorHardwareConfig(const timerHardware_t *timerHardware, uint8_t m #ifdef USE_DSHOT_TELEMETRY motor->dshotTelemetryDeadtimeUs = DSHOT_TELEMETRY_DEADTIME_US + 1000000 * ( 16 * MOTOR_BITLENGTH) / getDshotHz(pwmProtocolType); - motor->timer->outputPeriod = (pwmProtocolType == PWM_TYPE_PROSHOT1000 ? (MOTOR_NIBBLE_LENGTH_PROSHOT) : MOTOR_BITLENGTH) - 1; + motor->timer->outputPeriod = (pwmProtocolType == MOTOR_PROTOCOL_PROSHOT1000 ? (MOTOR_NIBBLE_LENGTH_PROSHOT) : MOTOR_BITLENGTH) - 1; pwmDshotSetDirectionOutput(motor); #else pwmDshotSetDirectionOutput(motor, &OCINIT, &DMAINIT); diff --git a/src/platform/STM32/pwm_output.c b/src/platform/STM32/pwm_output_hw.c similarity index 82% rename from src/platform/STM32/pwm_output.c rename to src/platform/STM32/pwm_output_hw.c index 3def265a14..67284840cb 100644 --- a/src/platform/STM32/pwm_output.c +++ b/src/platform/STM32/pwm_output_hw.c @@ -28,14 +28,13 @@ #ifdef USE_PWM_OUTPUT #include "drivers/io.h" -#include "drivers/motor.h" #include "drivers/pwm_output.h" #include "drivers/time.h" #include "drivers/timer.h" -#include "pg/motor.h" +#include "drivers/motor_impl.h" -FAST_DATA_ZERO_INIT pwmOutputPort_t motors[MAX_SUPPORTED_MOTORS]; +static bool useContinuousUpdate = true; static void pwmOCConfig(TIM_TypeDef *tim, uint8_t channel, uint16_t value, uint8_t output) { @@ -108,14 +107,6 @@ void pwmOutConfig(timerChannel_t *channel, const timerHardware_t *timerHardware, *channel->ccr = 0; } -static FAST_DATA_ZERO_INIT motorDevice_t motorPwmDevice; - -static void pwmWriteUnused(uint8_t index, float value) -{ - UNUSED(index); - UNUSED(value); -} - static void pwmWriteStandard(uint8_t index, float value) { /* TODO: move value to be a number between 0-1 (i.e. percent throttle from mixer) */ @@ -124,7 +115,7 @@ static void pwmWriteStandard(uint8_t index, float value) void pwmShutdownPulsesForAllMotors(void) { - for (int index = 0; index < motorPwmDevice.count; index++) { + for (int index = 0; pwmMotorCount; index++) { // Set the compare register to 0, which stops the output pulsing if the timer overflows if (motors[index].channel.ccr) { *motors[index].channel.ccr = 0; @@ -137,21 +128,24 @@ void pwmDisableMotors(void) pwmShutdownPulsesForAllMotors(); } -static motorVTable_t motorPwmVTable; bool pwmEnableMotors(void) { /* check motors can be enabled */ - return (motorPwmVTable.write != &pwmWriteUnused); + return pwmMotorCount > 0; } -bool pwmIsMotorEnabled(uint8_t index) +bool pwmIsMotorEnabled(unsigned index) { return motors[index].enabled; } -static void pwmCompleteOneshotMotorUpdate(void) +static void pwmCompleteMotorUpdate(void) { - for (int index = 0; index < motorPwmDevice.count; index++) { + if (useContinuousUpdate) { + return; + } + + for (int index = 0; pwmMotorCount; index++) { if (motors[index].forceOverflow) { timerForceOverflow(motors[index].channel.tim); } @@ -171,66 +165,69 @@ static uint16_t pwmConvertToExternal(float motorValue) return (uint16_t)motorValue; } -static motorVTable_t motorPwmVTable = { - .postInit = motorPostInitNull, +static const motorVTable_t motorPwmVTable = { + .postInit = NULL, .enable = pwmEnableMotors, .disable = pwmDisableMotors, .isMotorEnabled = pwmIsMotorEnabled, .shutdown = pwmShutdownPulsesForAllMotors, .convertExternalToMotor = pwmConvertFromExternal, .convertMotorToExternal = pwmConvertToExternal, + .write = pwmWriteStandard, + .decodeTelemetry = NULL, + .updateComplete = pwmCompleteMotorUpdate, + .requestTelemetry = NULL, + .isMotorIdle = NULL, }; -motorDevice_t *motorPwmDevInit(const motorDevConfig_t *motorConfig, uint16_t idlePulse, uint8_t motorCount, bool useUnsyncedPwm) +bool motorPwmDevInit(motorDevice_t *device, const motorDevConfig_t *motorConfig, uint16_t idlePulse) { memset(motors, 0, sizeof(motors)); - motorPwmDevice.vTable = motorPwmVTable; + pwmMotorCount = device->count; + device->vTable = &motorPwmVTable; + useContinuousUpdate = motorConfig->useContinuousUpdate; float sMin = 0; float sLen = 0; - switch (motorConfig->motorPwmProtocol) { + switch (motorConfig->motorProtocol) { default: - case PWM_TYPE_ONESHOT125: + case MOTOR_PROTOCOL_ONESHOT125: sMin = 125e-6f; sLen = 125e-6f; break; - case PWM_TYPE_ONESHOT42: + case MOTOR_PROTOCOL_ONESHOT42: sMin = 42e-6f; sLen = 42e-6f; break; - case PWM_TYPE_MULTISHOT: + case MOTOR_PROTOCOL_MULTISHOT: sMin = 5e-6f; sLen = 20e-6f; break; - case PWM_TYPE_BRUSHED: + case MOTOR_PROTOCOL_BRUSHED: sMin = 0; - useUnsyncedPwm = true; + useContinuousUpdate = true; idlePulse = 0; break; - case PWM_TYPE_STANDARD: + case MOTOR_PROTOCOL_PWM : sMin = 1e-3f; sLen = 1e-3f; - useUnsyncedPwm = true; + useContinuousUpdate = true; idlePulse = 0; break; } - motorPwmDevice.vTable.write = pwmWriteStandard; - motorPwmDevice.vTable.decodeTelemetry = motorDecodeTelemetryNull; - motorPwmDevice.vTable.updateComplete = useUnsyncedPwm ? motorUpdateCompleteNull : pwmCompleteOneshotMotorUpdate; - - for (int motorIndex = 0; motorIndex < MAX_SUPPORTED_MOTORS && motorIndex < motorCount; motorIndex++) { + for (int motorIndex = 0; motorIndex < MAX_SUPPORTED_MOTORS && motorIndex < pwmMotorCount; motorIndex++) { const unsigned reorderedMotorIndex = motorConfig->motorOutputReordering[motorIndex]; const ioTag_t tag = motorConfig->ioTags[reorderedMotorIndex]; const timerHardware_t *timerHardware = timerAllocate(tag, OWNER_MOTOR, RESOURCE_INDEX(reorderedMotorIndex)); if (timerHardware == NULL) { /* not enough motors initialised for the mixer or a break in the motors */ - motorPwmDevice.vTable.write = &pwmWriteUnused; - motorPwmDevice.vTable.updateComplete = motorUpdateCompleteNull; + device->vTable = NULL; + pwmMotorCount = 0; /* TODO: block arming and add reason system cannot arm */ - return NULL; + return false; } motors[motorIndex].io = IOGetByTag(tag); @@ -240,23 +237,23 @@ motorDevice_t *motorPwmDevInit(const motorDevConfig_t *motorConfig, uint16_t idl /* standard PWM outputs */ // margin of safety is 4 periods when unsynced - const unsigned pwmRateHz = useUnsyncedPwm ? motorConfig->motorPwmRate : ceilf(1 / ((sMin + sLen) * 4)); + const unsigned pwmRateHz = useContinuousUpdate ? motorConfig->motorPwmRate : ceilf(1 / ((sMin + sLen) * 4)); const uint32_t clock = timerClock(timerHardware->tim); /* used to find the desired timer frequency for max resolution */ const unsigned prescaler = ((clock / pwmRateHz) + 0xffff) / 0x10000; /* rounding up */ const uint32_t hz = clock / prescaler; - const unsigned period = useUnsyncedPwm ? hz / pwmRateHz : 0xffff; + const unsigned period = useContinuousUpdate ? hz / pwmRateHz : 0xffff; /* if brushed then it is the entire length of the period. TODO: this can be moved back to periodMin and periodLen once mixer outputs a 0..1 float value. */ - motors[motorIndex].pulseScale = ((motorConfig->motorPwmProtocol == PWM_TYPE_BRUSHED) ? period : (sLen * hz)) / 1000.0f; + motors[motorIndex].pulseScale = ((motorConfig->motorProtocol == MOTOR_PROTOCOL_BRUSHED) ? period : (sLen * hz)) / 1000.0f; motors[motorIndex].pulseOffset = (sMin * hz) - (motors[motorIndex].pulseScale * 1000); - pwmOutConfig(&motors[motorIndex].channel, timerHardware, hz, period, idlePulse, motorConfig->motorPwmInversion); + pwmOutConfig(&motors[motorIndex].channel, timerHardware, hz, period, idlePulse, motorConfig->motorInversion); bool timerAlreadyUsed = false; for (int i = 0; i < motorIndex; i++) { @@ -269,7 +266,7 @@ motorDevice_t *motorPwmDevInit(const motorDevConfig_t *motorConfig, uint16_t idl motors[motorIndex].enabled = true; } - return &motorPwmDevice; + return true; } pwmOutputPort_t *pwmGetMotors(void) diff --git a/src/platform/STM32/target/STM32F411/target.h b/src/platform/STM32/target/STM32F411/target.h index 0c93771a80..3eb65afac9 100644 --- a/src/platform/STM32/target/STM32F411/target.h +++ b/src/platform/STM32/target/STM32F411/target.h @@ -57,7 +57,7 @@ #define USE_BEEPER -#define DEFAULT_MOTOR_DSHOT_SPEED PWM_TYPE_DSHOT300 +#define DEFAULT_MOTOR_DSHOT_SPEED MOTOR_PROTOCOL_DSHOT300 #ifdef USE_SDCARD #define USE_SDCARD_SPI diff --git a/src/platform/common/stm32/bus_spi_hw.c b/src/platform/common/stm32/bus_spi_hw.c index b0befd8c34..653690ecfe 100644 --- a/src/platform/common/stm32/bus_spi_hw.c +++ b/src/platform/common/stm32/bus_spi_hw.c @@ -32,7 +32,7 @@ #include "drivers/bus_spi.h" #include "drivers/bus_spi_impl.h" #include "drivers/dma_reqmap.h" -#include "drivers/motor.h" +#include "drivers/dshot.h" #include "drivers/nvic.h" #include "pg/bus_spi.h" diff --git a/src/main/drivers/dshot_bitbang_impl.h b/src/platform/common/stm32/dshot_bitbang_impl.h similarity index 96% rename from src/main/drivers/dshot_bitbang_impl.h rename to src/platform/common/stm32/dshot_bitbang_impl.h index 0139c24257..4e062e86c2 100644 --- a/src/main/drivers/dshot_bitbang_impl.h +++ b/src/platform/common/stm32/dshot_bitbang_impl.h @@ -20,8 +20,14 @@ #pragma once +#include "platform.h" + #include "common/time.h" -#include "drivers/motor.h" + +#include "drivers/timer.h" +#include "drivers/motor_types.h" +#include "drivers/dshot.h" +#include "pg/motor.h" #define USE_DMA_REGISTER_CACHE @@ -223,6 +229,7 @@ extern FAST_DATA_ZERO_INIT int usedMotorPorts; extern FAST_DATA_ZERO_INIT bbMotor_t bbMotors[MAX_SUPPORTED_MOTORS]; extern uint8_t bbPuPdMode; +extern dshotBitbangStatus_e bbStatus; // DMA buffers // Note that we are not sharing input and output buffers, @@ -275,3 +282,6 @@ void bbDMA_Cmd(bbPort_t *bbPort, confirm_state NewState); void bbDMA_Cmd(bbPort_t *bbPort, FunctionalState NewState); #endif int bbDMA_Count(bbPort_t *bbPort); + +void bbDshotRequestTelemetry(unsigned motorIndex); +bool bbDshotIsMotorIdle(unsigned motorIndex); diff --git a/src/platform/common/stm32/dshot_bitbang_shared.c b/src/platform/common/stm32/dshot_bitbang_shared.c new file mode 100644 index 0000000000..c5152d59f3 --- /dev/null +++ b/src/platform/common/stm32/dshot_bitbang_shared.c @@ -0,0 +1,68 @@ +/* + * This file is part of Betaflight. + * + * Betaflight is free software. You can redistribute this software + * and/or modify this software under the terms of the GNU General + * Public License as published by the Free Software Foundation, + * either version 3 of the License, or (at your option) any later + * version. + * + * Betaflight is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * See the GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this software. + * + * If not, see . + */ + +#include "dshot_bitbang_impl.h" + +FAST_DATA_ZERO_INIT bbPacer_t bbPacers[MAX_MOTOR_PACERS]; // TIM1 or TIM8 +FAST_DATA_ZERO_INIT int usedMotorPacers = 0; + +FAST_DATA_ZERO_INIT bbPort_t bbPorts[MAX_SUPPORTED_MOTOR_PORTS]; +FAST_DATA_ZERO_INIT int usedMotorPorts; + +FAST_DATA_ZERO_INIT bbMotor_t bbMotors[MAX_SUPPORTED_MOTORS]; + +dshotBitbangStatus_e bbStatus; + +void bbDshotRequestTelemetry(unsigned motorIndex) +{ + if (motorIndex >= ARRAYLEN(bbMotors)) { + return; + } + bbMotor_t *const bbmotor = &bbMotors[motorIndex]; + + if (!bbmotor->configured) { + return; + } + bbmotor->protocolControl.requestTelemetry = true; +} + +bool bbDshotIsMotorIdle(unsigned motorIndex) +{ + if (motorIndex >= ARRAYLEN(bbMotors)) { + return false; + } + + bbMotor_t *const bbmotor = &bbMotors[motorIndex]; + return bbmotor->protocolControl.value == 0; +} + +#ifdef USE_DSHOT_BITBANG +bool isDshotBitbangActive(const motorDevConfig_t *motorDevConfig) +{ +#if defined(STM32F4) || defined(APM32F4) + return motorDevConfig->useDshotBitbang == DSHOT_BITBANG_ON || + (motorDevConfig->useDshotBitbang == DSHOT_BITBANG_AUTO && motorDevConfig->useDshotTelemetry && motorDevConfig->motorProtocol != MOTOR_PROTOCOL_PROSHOT1000); +#else + return motorDevConfig->useDshotBitbang == DSHOT_BITBANG_ON || + (motorDevConfig->useDshotBitbang == DSHOT_BITBANG_AUTO && motorDevConfig->motorProtocol != MOTOR_PROTOCOL_PROSHOT1000); +#endif +} +#endif diff --git a/src/main/drivers/dshot_dpwm.c b/src/platform/common/stm32/dshot_dpwm.c similarity index 79% rename from src/main/drivers/dshot_dpwm.c rename to src/platform/common/stm32/dshot_dpwm.c index a7ab462f51..cee7aa6003 100644 --- a/src/main/drivers/dshot_dpwm.c +++ b/src/platform/common/stm32/dshot_dpwm.c @@ -30,9 +30,10 @@ #ifdef USE_DSHOT #include "drivers/pwm_output.h" +#include "pwm_output_dshot_shared.h" #include "drivers/dshot.h" -#include "drivers/dshot_dpwm.h" -#include "drivers/motor.h" +#include "dshot_dpwm.h" +#include "drivers/motor_impl.h" #include "pg/motor.h" @@ -79,17 +80,17 @@ FAST_CODE_NOINLINE uint8_t loadDmaBufferProshot(uint32_t *dmaBuffer, int stride, return PROSHOT_DMA_BUFFER_SIZE; } -uint32_t getDshotHz(motorPwmProtocolTypes_e pwmProtocolType) +uint32_t getDshotHz(motorProtocolTypes_e pwmProtocolType) { switch (pwmProtocolType) { - case(PWM_TYPE_PROSHOT1000): + case(MOTOR_PROTOCOL_PROSHOT1000): return MOTOR_PROSHOT1000_HZ; - case(PWM_TYPE_DSHOT600): + case(MOTOR_PROTOCOL_DSHOT600): return MOTOR_DSHOT600_HZ; - case(PWM_TYPE_DSHOT300): + case(MOTOR_PROTOCOL_DSHOT300): return MOTOR_DSHOT300_HZ; default: - case(PWM_TYPE_DSHOT150): + case(MOTOR_PROTOCOL_DSHOT150): return MOTOR_DSHOT150_HZ; } } @@ -110,7 +111,7 @@ static void dshotPwmDisableMotors(void) static bool dshotPwmEnableMotors(void) { - for (int i = 0; i < dshotPwmDevice.count; i++) { + for (int i = 0; i < dshotMotorCount; i++) { motorDmaOutput_t *motor = getMotorDmaOutput(i); const IO_t motorIO = IOGetByTag(motor->timerHardware->tag); IOConfigGPIOAF(motorIO, motor->iocfg, motor->timerHardware->alternateFunction); @@ -120,7 +121,7 @@ static bool dshotPwmEnableMotors(void) return true; } -static bool dshotPwmIsMotorEnabled(uint8_t index) +static bool dshotPwmIsMotorEnabled(unsigned index) { return motors[index].enabled; } @@ -135,41 +136,37 @@ static FAST_CODE void dshotWrite(uint8_t index, float value) pwmWriteDshotInt(index, lrintf(value)); } -static motorVTable_t dshotPwmVTable = { +static const motorVTable_t dshotPwmVTable = { .postInit = motorPostInitNull, .enable = dshotPwmEnableMotors, .disable = dshotPwmDisableMotors, .isMotorEnabled = dshotPwmIsMotorEnabled, - .decodeTelemetry = motorDecodeTelemetryNull, // May be updated after copying + .decodeTelemetry = pwmTelemetryDecode, .write = dshotWrite, .writeInt = dshotWriteInt, .updateComplete = pwmCompleteDshotMotorUpdate, .convertExternalToMotor = dshotConvertFromExternal, .convertMotorToExternal = dshotConvertToExternal, .shutdown = dshotPwmShutdown, + .requestTelemetry = pwmDshotRequestTelemetry, + .isMotorIdle = pwmDshotIsMotorIdle, }; -FAST_DATA_ZERO_INIT motorDevice_t dshotPwmDevice; - -motorDevice_t *dshotPwmDevInit(const motorDevConfig_t *motorConfig, uint16_t idlePulse, uint8_t motorCount, bool useUnsyncedPwm) +bool dshotPwmDevInit(motorDevice_t *device, const motorDevConfig_t *motorConfig) { - UNUSED(idlePulse); - UNUSED(useUnsyncedPwm); - - dshotPwmDevice.vTable = dshotPwmVTable; - + device->vTable = &dshotPwmVTable; + dshotMotorCount = device->count; #ifdef USE_DSHOT_TELEMETRY useDshotTelemetry = motorConfig->useDshotTelemetry; - dshotPwmDevice.vTable.decodeTelemetry = pwmTelemetryDecode; #endif - switch (motorConfig->motorPwmProtocol) { - case PWM_TYPE_PROSHOT1000: + switch (motorConfig->motorProtocol) { + case MOTOR_PROTOCOL_PROSHOT1000: loadDmaBuffer = loadDmaBufferProshot; break; - case PWM_TYPE_DSHOT600: - case PWM_TYPE_DSHOT300: - case PWM_TYPE_DSHOT150: + case MOTOR_PROTOCOL_DSHOT600: + case MOTOR_PROTOCOL_DSHOT300: + case MOTOR_PROTOCOL_DSHOT150: loadDmaBuffer = loadDmaBufferDshot; #ifdef USE_DSHOT_DMAR useBurstDshot = motorConfig->useBurstDshot == DSHOT_DMAR_ON || @@ -178,7 +175,7 @@ motorDevice_t *dshotPwmDevInit(const motorDevConfig_t *motorConfig, uint16_t idl break; } - for (int motorIndex = 0; motorIndex < MAX_SUPPORTED_MOTORS && motorIndex < motorCount; motorIndex++) { + for (int motorIndex = 0; motorIndex < MAX_SUPPORTED_MOTORS && motorIndex < dshotMotorCount; motorIndex++) { const unsigned reorderedMotorIndex = motorConfig->motorOutputReordering[motorIndex]; const ioTag_t tag = motorConfig->ioTags[reorderedMotorIndex]; const timerHardware_t *timerHardware = timerAllocate(tag, OWNER_MOTOR, RESOURCE_INDEX(reorderedMotorIndex)); @@ -190,8 +187,8 @@ motorDevice_t *dshotPwmDevInit(const motorDevConfig_t *motorConfig, uint16_t idl if (pwmDshotMotorHardwareConfig(timerHardware, motorIndex, reorderedMotorIndex, - motorConfig->motorPwmProtocol, - motorConfig->motorPwmInversion ? timerHardware->output ^ TIMER_OUTPUT_INVERTED : timerHardware->output)) { + motorConfig->motorProtocol, + motorConfig->motorInversion ? timerHardware->output ^ TIMER_OUTPUT_INVERTED : timerHardware->output)) { motors[motorIndex].enabled = true; continue; @@ -199,14 +196,12 @@ motorDevice_t *dshotPwmDevInit(const motorDevConfig_t *motorConfig, uint16_t idl } /* not enough motors initialised for the mixer or a break in the motors */ - dshotPwmDevice.vTable.write = motorWriteNull; - dshotPwmDevice.vTable.updateComplete = motorUpdateCompleteNull; - + dshotMotorCount = 0; /* TODO: block arming and add reason system cannot arm */ - return NULL; + return false; } - return &dshotPwmDevice; + return true; } #endif // USE_DSHOT diff --git a/src/main/drivers/dshot_dpwm.h b/src/platform/common/stm32/dshot_dpwm.h similarity index 91% rename from src/main/drivers/dshot_dpwm.h rename to src/platform/common/stm32/dshot_dpwm.h index 1c6a7400fb..0cdf3cf41b 100644 --- a/src/main/drivers/dshot_dpwm.h +++ b/src/platform/common/stm32/dshot_dpwm.h @@ -23,7 +23,7 @@ #pragma once #include "drivers/dshot.h" -#include "drivers/motor.h" +#include "drivers/motor_types.h" // Timer clock frequency for the dshot speeds #define MOTOR_DSHOT600_HZ MHZ_TO_HZ(12) @@ -47,10 +47,7 @@ extern FAST_DATA_ZERO_INIT loadDmaBufferFn *loadDmaBuffer; uint8_t loadDmaBufferDshot(uint32_t *dmaBuffer, int stride, uint16_t packet); uint8_t loadDmaBufferProshot(uint32_t *dmaBuffer, int stride, uint16_t packet); -uint32_t getDshotHz(motorPwmProtocolTypes_e pwmProtocolType); - -struct motorDevConfig_s; -motorDevice_t *dshotPwmDevInit(const struct motorDevConfig_s *motorConfig, uint16_t idlePulse, uint8_t motorCount, bool useUnsyncedPwm); +uint32_t getDshotHz(motorProtocolTypes_e pwmProtocolType); /* Motor DMA related, moved from pwm_output.h */ @@ -70,7 +67,7 @@ motorDevice_t *dshotPwmDevInit(const struct motorDevConfig_s *motorConfig, uint1 #elif defined(STM32F7) #define DSHOT_DMA_BUFFER_ATTRIBUTE FAST_DATA_ZERO_INIT #else -#define DSHOT_DMA_BUFFER_ATTRIBUTE // None +#define DSHOT_DMA_BUFFER_ATTRIBUTE /* Empty */ #endif #if defined(STM32F4) || defined(STM32F7) || defined(STM32H7) || defined(STM32G4) || defined(AT32F435) || defined(APM32F4) @@ -156,15 +153,13 @@ typedef struct motorDmaOutput_s { DSHOT_DMA_BUFFER_UNIT *dmaBuffer; } motorDmaOutput_t; -motorDmaOutput_t *getMotorDmaOutput(uint8_t index); +motorDmaOutput_t *getMotorDmaOutput(unsigned index); void pwmWriteDshotInt(uint8_t index, uint16_t value); -bool pwmDshotMotorHardwareConfig(const timerHardware_t *timerHardware, uint8_t motorIndex, uint8_t reorderedMotorIndex, motorPwmProtocolTypes_e pwmProtocolType, uint8_t output); +bool pwmDshotMotorHardwareConfig(const timerHardware_t *timerHardware, uint8_t motorIndex, uint8_t reorderedMotorIndex, motorProtocolTypes_e pwmProtocolType, uint8_t output); #ifdef USE_DSHOT_TELEMETRY bool pwmTelemetryDecode(void); #endif void pwmCompleteDshotMotorUpdate(void); extern bool useBurstDshot; - -extern motorDevice_t dshotPwmDevice; diff --git a/src/main/drivers/pwm_output_dshot_shared.c b/src/platform/common/stm32/pwm_output_dshot_shared.c similarity index 89% rename from src/main/drivers/pwm_output_dshot_shared.c rename to src/platform/common/stm32/pwm_output_dshot_shared.c index 998112becf..ccf2ab661d 100644 --- a/src/main/drivers/pwm_output_dshot_shared.c +++ b/src/platform/common/stm32/pwm_output_dshot_shared.c @@ -40,15 +40,16 @@ #include "stm32f4xx.h" #endif -#include "pwm_output.h" +#include "drivers/pwm_output.h" #include "drivers/dshot.h" -#include "drivers/dshot_dpwm.h" +#include "dshot_dpwm.h" #include "drivers/dshot_command.h" #include "drivers/motor.h" #include "pwm_output_dshot_shared.h" FAST_DATA_ZERO_INIT uint8_t dmaMotorTimerCount = 0; + #ifdef STM32F7 FAST_DATA_ZERO_INIT motorDmaTimer_t dmaMotorTimers[MAX_DMA_TIMERS]; FAST_DATA_ZERO_INIT motorDmaOutput_t dmaMotors[MAX_SUPPORTED_MOTORS]; @@ -60,14 +61,31 @@ motorDmaOutput_t dmaMotors[MAX_SUPPORTED_MOTORS]; #ifdef USE_DSHOT_TELEMETRY FAST_DATA_ZERO_INIT uint32_t inputStampUs; -FAST_DATA_ZERO_INIT dshotDMAHandlerCycleCounters_t dshotDMAHandlerCycleCounters; +FAST_DATA_ZERO_INIT dshotTelemetryCycleCounters_t dshotDMAHandlerCycleCounters; #endif -motorDmaOutput_t *getMotorDmaOutput(uint8_t index) +motorDmaOutput_t *getMotorDmaOutput(unsigned index) { + if (index >= ARRAYLEN(dmaMotors)) { + return NULL; + } return &dmaMotors[index]; } +bool pwmDshotIsMotorIdle(unsigned index) +{ + const motorDmaOutput_t *motor = getMotorDmaOutput(index); + return motor && motor->protocolControl.value == 0; +} + +void pwmDshotRequestTelemetry(unsigned index) +{ + motorDmaOutput_t * const motor = getMotorDmaOutput(index); + if (motor) { + motor->protocolControl.requestTelemetry = true; + } +} + uint8_t getTimerIndex(TIM_TypeDef *timer) { for (int i = 0; i < dmaMotorTimerCount; i++) { @@ -127,12 +145,12 @@ FAST_CODE void pwmWriteDshotInt(uint8_t index, uint16_t value) #else xDMA_SetCurrDataCounter(motor->dmaRef, bufferSize); - // XXX we can remove this ifdef if we add a new macro for the TRUE/ENABLE constants - #ifdef AT32F435 +// XXX we can remove this ifdef if we add a new macro for the TRUE/ENABLE constants +#ifdef AT32F435 xDMA_Cmd(motor->dmaRef, TRUE); - #else +#else xDMA_Cmd(motor->dmaRef, ENABLE); - #endif +#endif #endif // USE_FULL_LL_DRIVER } @@ -141,7 +159,7 @@ FAST_CODE void pwmWriteDshotInt(uint8_t index, uint16_t value) #ifdef USE_DSHOT_TELEMETRY -void dshotEnableChannels(uint8_t motorCount); +void dshotEnableChannels(unsigned motorCount); static uint32_t decodeTelemetryPacket(const uint32_t buffer[], uint32_t count) { @@ -191,13 +209,15 @@ static uint32_t decodeTelemetryPacket(const uint32_t buffer[], uint32_t count) #endif -#ifdef USE_DSHOT_TELEMETRY /** * Process dshot telemetry packets before switching the channels back to outputs * */ FAST_CODE_NOINLINE bool pwmTelemetryDecode(void) { +#ifndef USE_DSHOT_TELEMETRY + return true; +#else if (!useDshotTelemetry) { return true; } @@ -207,7 +227,7 @@ FAST_CODE_NOINLINE bool pwmTelemetryDecode(void) #endif const timeUs_t currentUs = micros(); - for (int i = 0; i < dshotPwmDevice.count; i++) { + for (int i = 0; i < dshotMotorCount; i++) { timeDelta_t usSinceInput = cmpTimeUs(currentUs, inputStampUs); if (usSinceInput >= 0 && usSinceInput < dmaMotors[i].dshotTelemetryDeadtimeUs) { return false; @@ -257,9 +277,9 @@ FAST_CODE_NOINLINE bool pwmTelemetryDecode(void) dshotTelemetryState.rawValueState = DSHOT_RAW_VALUE_STATE_NOT_PROCESSED; inputStampUs = 0; - dshotEnableChannels(dshotPwmDevice.count); + dshotEnableChannels(dshotMotorCount); return true; +#endif // USE_DSHOT_TELEMETRY } -#endif // USE_DSHOT_TELEMETRY #endif // USE_DSHOT diff --git a/src/main/drivers/pwm_output_dshot_shared.h b/src/platform/common/stm32/pwm_output_dshot_shared.h similarity index 69% rename from src/main/drivers/pwm_output_dshot_shared.h rename to src/platform/common/stm32/pwm_output_dshot_shared.h index 7c282d5008..38f226b305 100644 --- a/src/main/drivers/pwm_output_dshot_shared.h +++ b/src/platform/common/stm32/pwm_output_dshot_shared.h @@ -20,32 +20,17 @@ #ifdef USE_DSHOT +#include "drivers/dshot.h" +#include "dshot_dpwm.h" + extern FAST_DATA_ZERO_INIT uint8_t dmaMotorTimerCount; -#if defined(STM32F7) || defined(STM32H7) + extern FAST_DATA_ZERO_INIT motorDmaTimer_t dmaMotorTimers[MAX_DMA_TIMERS]; extern FAST_DATA_ZERO_INIT motorDmaOutput_t dmaMotors[MAX_SUPPORTED_MOTORS]; -#else -extern motorDmaTimer_t dmaMotorTimers[MAX_DMA_TIMERS]; -extern motorDmaOutput_t dmaMotors[MAX_SUPPORTED_MOTORS]; -#endif - -#ifdef USE_DSHOT_TELEMETRY -extern uint32_t readDoneCount; - -FAST_DATA_ZERO_INIT extern uint32_t inputStampUs; - -typedef struct dshotDMAHandlerCycleCounters_s { - uint32_t irqAt; - uint32_t changeDirectionCompletedAt; -} dshotDMAHandlerCycleCounters_t; - -FAST_DATA_ZERO_INIT extern dshotDMAHandlerCycleCounters_t dshotDMAHandlerCycleCounters; - -#endif uint8_t getTimerIndex(TIM_TypeDef *timer); -motorDmaOutput_t *getMotorDmaOutput(uint8_t index); -void dshotEnableChannels(uint8_t motorCount); +motorDmaOutput_t *getMotorDmaOutput(unsigned index); +void dshotEnableChannels(unsigned motorCount); #ifdef USE_DSHOT_TELEMETRY void pwmDshotSetDirectionOutput( @@ -59,6 +44,8 @@ void pwmDshotSetDirectionOutput( #endif ); +void pwmDshotRequestTelemetry(unsigned index); +bool pwmDshotIsMotorIdle(unsigned index); bool pwmTelemetryDecode(void); #endif diff --git a/src/test/unit/pg_unittest.cc b/src/test/unit/pg_unittest.cc index 23ce0c7fb8..8d0fd935db 100644 --- a/src/test/unit/pg_unittest.cc +++ b/src/test/unit/pg_unittest.cc @@ -37,9 +37,9 @@ PG_REGISTER_WITH_RESET_TEMPLATE(motorConfig_t, motorConfig, PG_MOTOR_CONFIG, 1); PG_RESET_TEMPLATE(motorConfig_t, motorConfig, .dev = { .motorPwmRate = 400, - .motorPwmProtocol = 0, - .motorPwmInversion = 0, - .useUnsyncedPwm = 0, + .motorProtocol = 0, + .motorInversion = 0, + .useContinuousUpdate = 0, .useBurstDshot = 0, .useDshotTelemetry = 0, .useDshotEdt = 0, From bbaf961edb3acbf6b4eaf7e3cedb6733fdb1aaa9 Mon Sep 17 00:00:00 2001 From: Mark Haslinghuis Date: Fri, 24 Jan 2025 18:15:54 +0100 Subject: [PATCH 079/244] Add 230K4 baudrate support for GPS (#14192) * Add support for 230K baudrate for GPS * Update CLI * Use invalidName for all instances --- src/main/cli/cli.c | 4 ++-- src/main/io/gps.c | 1 + 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/src/main/cli/cli.c b/src/main/cli/cli.c index 7fb1c481d3..cb8c116594 100644 --- a/src/main/cli/cli.c +++ b/src/main/cli/cli.c @@ -1348,7 +1348,7 @@ static void cliSerial(const char *cmdName, char *cmdline) portConfig.msp_baudrateIndex = baudRateIndex; break; case 1: - if (baudRateIndex < BAUD_9600 || baudRateIndex > BAUD_115200) { + if (baudRateIndex < BAUD_9600 || baudRateIndex > BAUD_230400) { continue; } portConfig.gps_baudrateIndex = baudRateIndex; @@ -1528,7 +1528,7 @@ static void cliSerialPassthrough(const char *cmdName, char *cmdline) cliPrintLinef("Invalid port%d %d", i + 1, ports[i].id); return; } else { - cliPrintLinef("Port%d: %s", i + 1, serialName(ports[i].id, "")); + cliPrintLinef("Port%d: %s", i + 1, serialName(ports[i].id, invalidName)); } } diff --git a/src/main/io/gps.c b/src/main/io/gps.c index 6e652dd117..8401c5f4b0 100644 --- a/src/main/io/gps.c +++ b/src/main/io/gps.c @@ -107,6 +107,7 @@ typedef struct gpsInitData_s { // UBX will cycle through these until valid data is received static const gpsInitData_t gpsInitData[] = { + { BAUD_230400, "$PUBX,41,1,0003,0001,230400,0*1C\r\n" }, { BAUD_115200, "$PUBX,41,1,0003,0001,115200,0*1E\r\n" }, { BAUD_57600, "$PUBX,41,1,0003,0001,57600,0*2D\r\n" }, { BAUD_38400, "$PUBX,41,1,0003,0001,38400,0*26\r\n" }, From 5fd0f2df04ba94dfe954aa1b6f3496d55325bcc0 Mon Sep 17 00:00:00 2001 From: Jacob Dahl <37091262+dakejahl@users.noreply.github.com> Date: Sat, 25 Jan 2025 08:00:18 -0900 Subject: [PATCH 080/244] h7: enable ports H and I (#14199) * h7: enable ports H and I * Update src/platform/STM32/target/STM32H743/target.h Co-authored-by: Mark Haslinghuis --------- Co-authored-by: Mark Haslinghuis --- src/platform/STM32/target/STM32H743/target.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/platform/STM32/target/STM32H743/target.h b/src/platform/STM32/target/STM32H743/target.h index a1ed4202de..cca95f214f 100644 --- a/src/platform/STM32/target/STM32H743/target.h +++ b/src/platform/STM32/target/STM32H743/target.h @@ -59,6 +59,8 @@ #define TARGET_IO_PORTE 0xffff #define TARGET_IO_PORTF 0xffff #define TARGET_IO_PORTG 0xffff +#define TARGET_IO_PORTH 0xffff +#define TARGET_IO_PORTI 0xffff #define USE_I2C #define I2C_FULL_RECONFIGURABILITY From deb691bfc87b09fd678d482abef19d1d7a0c28aa Mon Sep 17 00:00:00 2001 From: Jay Blackman Date: Sun, 26 Jan 2025 04:01:17 +1100 Subject: [PATCH 081/244] FIX: Missing IFDEF USE_TIMER and USE_RPM_FILTER (#14201) --- src/main/config/config.c | 2 +- src/main/drivers/dshot.c | 4 ++++ 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/src/main/config/config.c b/src/main/config/config.c index 2c8295ebcc..002797cec0 100644 --- a/src/main/config/config.c +++ b/src/main/config/config.c @@ -452,7 +452,7 @@ static void validateAndFixConfig(void) motorConfigMutable()->dev.useContinuousUpdate = false; } -#if defined(USE_DSHOT_TELEMETRY) +#if defined(USE_DSHOT_TELEMETRY) && defined(USE_TIMER) bool nChannelTimerUsed = false; for (unsigned i = 0; i < getMotorCount(); i++) { const ioTag_t tag = motorConfig()->dev.ioTags[i]; diff --git a/src/main/drivers/dshot.c b/src/main/drivers/dshot.c index ec73e04327..d433240539 100644 --- a/src/main/drivers/dshot.c +++ b/src/main/drivers/dshot.c @@ -161,12 +161,16 @@ void initDshotTelemetry(const timeUs_t looptimeUs) // erpmToHz is used by bidir dshot and ESC telemetry erpmToHz = ERPM_PER_LSB / SECONDS_PER_MINUTE / (motorConfig()->motorPoleCount / 2.0f); +#ifdef USE_RPM_FILTER if (motorConfig()->dev.useDshotTelemetry) { // init LPFs for RPM data for (unsigned i = 0; i < dshotMotorCount; i++) { pt1FilterInit(&motorFreqLpf[i], pt1FilterGain(rpmFilterConfig()->rpm_filter_lpf_hz, looptimeUs * 1e-6f)); } } +#else + UNUSED(looptimeUs); +#endif } static uint32_t dshot_decode_eRPM_telemetry_value(uint16_t value) From 4db3cad503e37439442e77b2a3bdc3723fc5795e Mon Sep 17 00:00:00 2001 From: ctzsnooze Date: Sun, 26 Jan 2025 13:33:22 +0100 Subject: [PATCH 082/244] Remove unused timer related defines (#14197) Remove unused timer remapping defines without matching functions --- src/platform/STM32/exti.c | 6 ------ 1 file changed, 6 deletions(-) diff --git a/src/platform/STM32/exti.c b/src/platform/STM32/exti.c index bc9c6c464c..8dbf14ad84 100644 --- a/src/platform/STM32/exti.c +++ b/src/platform/STM32/exti.c @@ -88,12 +88,6 @@ void EXTIInit(void) #if defined(STM32F4) /* Enable SYSCFG clock otherwise the EXTI irq handlers are not called */ RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE); -#ifdef REMAP_TIM16_DMA - SYSCFG_DMAChannelRemapConfig(SYSCFG_DMARemap_TIM16, ENABLE); -#endif -#ifdef REMAP_TIM17_DMA - SYSCFG_DMAChannelRemapConfig(SYSCFG_DMARemap_TIM17, ENABLE); -#endif #endif memset(extiChannelRecs, 0, sizeof(extiChannelRecs)); memset(extiGroupPriority, 0xff, sizeof(extiGroupPriority)); From 986a5f119adb966abf4e22e45fb5bd9828c8cb9d Mon Sep 17 00:00:00 2001 From: ctzsnooze Date: Sun, 26 Jan 2025 17:17:25 +0100 Subject: [PATCH 083/244] Remove PARTIAL_REMAP_TIM3 defines for AT32 and STM32 (#14198) remove PARTIAL_REMAP_TIM3 code --- src/platform/AT32/timer_at32bsp.c | 4 ---- src/platform/STM32/timer_stdperiph.c | 4 ---- 2 files changed, 8 deletions(-) diff --git a/src/platform/AT32/timer_at32bsp.c b/src/platform/AT32/timer_at32bsp.c index b0a584b83e..46efb390ce 100644 --- a/src/platform/AT32/timer_at32bsp.c +++ b/src/platform/AT32/timer_at32bsp.c @@ -676,10 +676,6 @@ void timerInit(void) { memset(timerConfig, 0, sizeof(timerConfig)); -#if defined(PARTIAL_REMAP_TIM3) - GPIO_PinRemapConfig(GPIO_PartialRemap_TIM3, ENABLE); -#endif - #ifdef USE_TIMER_MGMT /* enable the timer peripherals */ for (unsigned i = 0; i < TIMER_CHANNEL_COUNT; i++) { diff --git a/src/platform/STM32/timer_stdperiph.c b/src/platform/STM32/timer_stdperiph.c index b225072caa..33f1a27acd 100644 --- a/src/platform/STM32/timer_stdperiph.c +++ b/src/platform/STM32/timer_stdperiph.c @@ -837,10 +837,6 @@ void timerInit(void) { memset(timerConfig, 0, sizeof(timerConfig)); -#if defined(PARTIAL_REMAP_TIM3) - GPIO_PinRemapConfig(GPIO_PartialRemap_TIM3, ENABLE); -#endif - /* enable the timer peripherals */ for (unsigned i = 0; i < TIMER_CHANNEL_COUNT; i++) { RCC_ClockCmd(timerRCC(TIMER_HARDWARE[i].tim), ENABLE); From e760bfa68716bf27466ac4aea9784d37eb5f0356 Mon Sep 17 00:00:00 2001 From: "Git bot (blckmn)" Date: Mon, 27 Jan 2025 06:25:04 +0000 Subject: [PATCH 084/244] Auto updated submodule references [27-01-2025] --- src/config | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/config b/src/config index be3155b97a..254ebace60 160000 --- a/src/config +++ b/src/config @@ -1 +1 @@ -Subproject commit be3155b97a9d33fb34e181c15de891f6f72bef5d +Subproject commit 254ebace60b95e608861c42acc95481226b5f1e8 From 07082de41ed6be36310f093d8938a9b8d12e1967 Mon Sep 17 00:00:00 2001 From: ot0tot <36753790+ot0tot@users.noreply.github.com> Date: Mon, 27 Jan 2025 08:07:25 -0500 Subject: [PATCH 085/244] Update mag_declination range in settings.c (#14206) * Update mag_declination range in settings.c * Update src/main/cli/settings.c Co-authored-by: Mark Haslinghuis --------- Co-authored-by: Mark Haslinghuis --- src/main/cli/settings.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/cli/settings.c b/src/main/cli/settings.c index d9ba4c1455..82df9227dd 100644 --- a/src/main/cli/settings.c +++ b/src/main/cli/settings.c @@ -1083,7 +1083,7 @@ const clivalue_t valueTable[] = { { PARAM_NAME_IMU_SMALL_ANGLE, VAR_UINT8 | MASTER_VALUE, .config.minmaxUnsigned = { 0, 180 }, PG_IMU_CONFIG, offsetof(imuConfig_t, small_angle) }, { PARAM_NAME_IMU_PROCESS_DENOM, VAR_UINT8 | MASTER_VALUE, .config.minmaxUnsigned = { 1, 4 }, PG_IMU_CONFIG, offsetof(imuConfig_t, imu_process_denom) }, #ifdef USE_MAG - { PARAM_NAME_IMU_MAG_DECLINATION, VAR_INT16 | MASTER_VALUE, .config.minmaxUnsigned = { -300, 300 }, PG_IMU_CONFIG, offsetof(imuConfig_t, mag_declination) }, + { PARAM_NAME_IMU_MAG_DECLINATION, VAR_INT16 | MASTER_VALUE, .config.minmax = { -300, 300 }, PG_IMU_CONFIG, offsetof(imuConfig_t, mag_declination) }, #endif // PG_ARMING_CONFIG From 3d9dcbc9b122f670288dc3eac01dc0a473594be6 Mon Sep 17 00:00:00 2001 From: Steve Evans Date: Mon, 27 Jan 2025 13:39:28 +0000 Subject: [PATCH 086/244] Fix G4 SPI clock being double what it should be (#14207) * Fix G4 SPI clock being double what it should be * Aligned to master --- src/platform/common/stm32/bus_spi_hw.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/platform/common/stm32/bus_spi_hw.c b/src/platform/common/stm32/bus_spi_hw.c index 653690ecfe..d294455298 100644 --- a/src/platform/common/stm32/bus_spi_hw.c +++ b/src/platform/common/stm32/bus_spi_hw.c @@ -174,10 +174,12 @@ FAST_IRQ_HANDLER static void spiTxIrqHandler(dmaChannelDescriptor_t* descriptor) uint16_t spiCalculateDivider(uint32_t freq) { -#if defined(STM32F4) || defined(STM32G4) || defined(STM32F7) || defined(APM32F4) +#if defined(STM32F4) || defined(STM32F7) || defined(APM32F4) uint32_t spiClk = SystemCoreClock / 2; #elif defined(STM32H7) uint32_t spiClk = 100000000; +#elif defined(STM32G4) + uint32_t spiClk = SystemCoreClock; #elif defined(AT32F4) if(freq > 36000000){ freq = 36000000; From 9ab3aa1048d1f9baad28843c7924559ae8c3ba4c Mon Sep 17 00:00:00 2001 From: Jacob Dahl <37091262+dakejahl@users.noreply.github.com> Date: Mon, 27 Jan 2025 06:34:29 -0900 Subject: [PATCH 087/244] h7: add timer pins (#14153) --- src/platform/STM32/timer_def.h | 7 +++++- src/platform/STM32/timer_stm32h7xx.c | 35 ++++++++++++++++------------ 2 files changed, 26 insertions(+), 16 deletions(-) diff --git a/src/platform/STM32/timer_def.h b/src/platform/STM32/timer_def.h index c8aae1f128..d31af27c39 100644 --- a/src/platform/STM32/timer_def.h +++ b/src/platform/STM32/timer_def.h @@ -747,6 +747,11 @@ #define DEF_TIM_AF__PB14__TCH_TIM12_CH1 D(2, 12) #define DEF_TIM_AF__PB15__TCH_TIM12_CH2 D(2, 12) +#define DEF_TIM_AF__PB0__TCH_TIM8_CH2N D(3, 8) +#define DEF_TIM_AF__PB1__TCH_TIM8_CH3N D(3, 8) +#define DEF_TIM_AF__PB14__TCH_TIM8_CH2N D(3, 8) +#define DEF_TIM_AF__PB15__TCH_TIM8_CH3N D(3, 8) + //PORTC #define DEF_TIM_AF__PC6__TCH_TIM3_CH1 D(2, 3) #define DEF_TIM_AF__PC7__TCH_TIM3_CH2 D(2, 3) @@ -1142,7 +1147,7 @@ #elif defined(STM32H7) -#define FULL_TIMER_CHANNEL_COUNT 87 +#define FULL_TIMER_CHANNEL_COUNT 91 #define USED_TIMERS ( TIM_N(1) | TIM_N(2) | TIM_N(3) | TIM_N(4) | TIM_N(5) | TIM_N(6) | TIM_N(7) | TIM_N(8) | TIM_N(12) | TIM_N(13) | TIM_N(14) | TIM_N(15) | TIM_N(16) | TIM_N(17) ) #define HARDWARE_TIMER_DEFINITION_COUNT 17 #define TIMUP_TIMERS ( BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) | BIT(15) | BIT(16) | BIT(17) ) diff --git a/src/platform/STM32/timer_stm32h7xx.c b/src/platform/STM32/timer_stm32h7xx.c index 78e066ca8e..3462e9d7f2 100644 --- a/src/platform/STM32/timer_stm32h7xx.c +++ b/src/platform/STM32/timer_stm32h7xx.c @@ -71,10 +71,8 @@ const timerHardware_t fullTimerHardware[FULL_TIMER_CHANNEL_COUNT] = { DEF_TIM(TIM5, CH4, PA3, 0, 0, 0), DEF_TIM(TIM3, CH1, PA6, 0, 0, 0), DEF_TIM(TIM3, CH2, PA7, 0, 0, 0), - DEF_TIM(TIM8, CH1N, PA5, 0, 0, 0), DEF_TIM(TIM8, CH1N, PA7, 0, 0, 0), - DEF_TIM(TIM13, CH1, PA6, 0, 0, 0), DEF_TIM(TIM14, CH1, PA7, 0, 0, 0), @@ -104,16 +102,19 @@ const timerHardware_t fullTimerHardware[FULL_TIMER_CHANNEL_COUNT] = { DEF_TIM(TIM4, CH2, PB7, 0, 0, 0), DEF_TIM(TIM4, CH3, PB8, 0, 0, 0), DEF_TIM(TIM4, CH4, PB9, 0, 0, 0), - DEF_TIM(TIM12, CH1, PB14, 0, 0, 0), DEF_TIM(TIM12, CH2, PB15, 0, 0, 0), + DEF_TIM(TIM8, CH2N, PB0, 0, 0, 0), + DEF_TIM(TIM8, CH3N, PB1, 0, 0, 0), + DEF_TIM(TIM8, CH2N, PB14, 0, 0, 0), + DEF_TIM(TIM8, CH3N, PB15, 0, 0, 0), + // Port C DEF_TIM(TIM3, CH1, PC6, 0, 0, 0), DEF_TIM(TIM3, CH2, PC7, 0, 0, 0), DEF_TIM(TIM3, CH3, PC8, 0, 0, 0), DEF_TIM(TIM3, CH4, PC9, 0, 0, 0), - DEF_TIM(TIM8, CH1, PC6, 0, 0, 0), DEF_TIM(TIM8, CH2, PC7, 0, 0, 0), DEF_TIM(TIM8, CH3, PC8, 0, 0, 0), @@ -133,7 +134,6 @@ const timerHardware_t fullTimerHardware[FULL_TIMER_CHANNEL_COUNT] = { DEF_TIM(TIM1, CH3N, PE12, 0, 0, 0), DEF_TIM(TIM1, CH3, PE13, 0, 0, 0), DEF_TIM(TIM1, CH4, PE14, 0, 0, 0), - DEF_TIM(TIM15, CH1N, PE4, 0, 0, 0), DEF_TIM(TIM15, CH1, PE5, 0, 0, 0), DEF_TIM(TIM15, CH2, PE6, 0, 0, 0), @@ -143,20 +143,25 @@ const timerHardware_t fullTimerHardware[FULL_TIMER_CHANNEL_COUNT] = { DEF_TIM(TIM17, CH1, PF7, 0, 0, 0), DEF_TIM(TIM16, CH1N, PF8, 0, 0, 0), DEF_TIM(TIM17, CH1N, PF9, 0, 0, 0), - DEF_TIM(TIM13, CH1N, PF8, 0, 0, 0), DEF_TIM(TIM14, CH1N, PF9, 0, 0, 0), // Port H -// Port H is not available for LPQFP-100 or 144 and TFBGA-100 package -// DEF_TIM(TIM12, CH1, PH6, 0, 0, 0), -// DEF_TIM(TIM12, CH2, PH9, 0, 0, 0), -// DEF_TIM(TIM5, CH1, PH10, 0, 0, 0), -// DEF_TIM(TIM5, CH2, PH11, 0, 0, 0), -// DEF_TIM(TIM5, CH3, PH12, 0, 0, 0), -// DEF_TIM(TIM8, CH1N, PH13, 0, 0, 0), -// DEF_TIM(TIM8, CH2N, PH14, 0, 0, 0), -// DEF_TIM(TIM8, CH3N, PH15, 0, 0, 0), + DEF_TIM(TIM5, CH1, PH10, 0, 0, 0), + DEF_TIM(TIM5, CH2, PH11, 0, 0, 0), + DEF_TIM(TIM5, CH3, PH12, 0, 0, 0), + DEF_TIM(TIM8, CH1N, PH13, 0, 0, 0), + DEF_TIM(TIM8, CH2N, PH14, 0, 0, 0), + DEF_TIM(TIM8, CH3N, PH15, 0, 0, 0), + DEF_TIM(TIM12, CH1, PH6, 0, 0, 0), + DEF_TIM(TIM12, CH2, PH9, 0, 0, 0), + +// Port I + DEF_TIM(TIM5, CH4, PI0, 0, 0, 0), + DEF_TIM(TIM8, CH4, PI2, 0, 0, 0), + DEF_TIM(TIM8, CH1, PI5, 0, 0, 0), + DEF_TIM(TIM8, CH2, PI6, 0, 0, 0), + DEF_TIM(TIM8, CH3, PI7, 0, 0, 0), }; #endif From c12a57e2ad41f676745a2df540e6ae619bcd3ef2 Mon Sep 17 00:00:00 2001 From: ggabriel Date: Mon, 27 Jan 2025 21:17:42 +0100 Subject: [PATCH 088/244] fix: STM32H5 makefile oop debug (#14212) --- src/platform/STM32/mk/STM32H5.mk | 10 +++------- 1 file changed, 3 insertions(+), 7 deletions(-) diff --git a/src/platform/STM32/mk/STM32H5.mk b/src/platform/STM32/mk/STM32H5.mk index 90a30cc32b..13c5a59cb3 100644 --- a/src/platform/STM32/mk/STM32H5.mk +++ b/src/platform/STM32/mk/STM32H5.mk @@ -112,22 +112,18 @@ DEFAULT_LD_SCRIPT = $(LINKER_DIR)/stm32_flash_h563_2m.ld STARTUP_SRC = STM32/startup/startup_stm32h563xx.s MCU_FLASH_SIZE := 2048 DEVICE_FLAGS += -DMAX_MPU_REGIONS=16 - # end H563xx - +else +$(error Unknown MCU for STM32H5 target) +endif ifneq ($(DEBUG),GDB) OPTIMISE_DEFAULT := -Os OPTIMISE_SPEED := -Os OPTIMISE_SIZE := -Os - LTO_FLAGS := $(OPTIMISATION_BASE) $(OPTIMISE_DEFAULT) endif -else -$(error Unknown MCU for STM32H5 target) -endif - ifeq ($(LD_SCRIPT),) LD_SCRIPT = $(DEFAULT_LD_SCRIPT) endif From 059ada4e4b9a27182d287df02fdc57327288f9aa Mon Sep 17 00:00:00 2001 From: ke deng Date: Tue, 28 Jan 2025 04:46:41 +0800 Subject: [PATCH 089/244] Filter comment line while try to get SYSTEM_HSE_MHZ value. (#14194) * Filter comment line while try to get SYSTEM_HSE_MHZ value. * use sed to find correct SYSTEM_HSE_MHZ * get TARGET EXST_ADJUST_VMA value through sed and remove GYRO_DEFINE * improve get FC_VMA_ADDRESS regex to fit more condition --- mk/config.mk | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/mk/config.mk b/mk/config.mk index 95c4d585f0..edd101b6d2 100644 --- a/mk/config.mk +++ b/mk/config.mk @@ -34,19 +34,17 @@ CONFIG_REVISION := $(shell git -C $(CONFIG_DIR) log -1 --format="%h") CONFIG_REVISION_DEFINE := -D'__CONFIG_REVISION__="$(CONFIG_REVISION)"' endif -TARGET := $(shell grep " FC_TARGET_MCU" $(CONFIG_HEADER_FILE) | awk '{print $$3}' ) -HSE_VALUE_MHZ := $(shell grep " SYSTEM_HSE_MHZ" $(CONFIG_HEADER_FILE) | awk '{print $$3}' ) +HSE_VALUE_MHZ := $(shell sed -E -n "/^\s*#\s*define\s+SYSTEM_HSE_MHZ\s+([0-9]+).*/s//\1/p" $(CONFIG_HEADER_FILE)) ifneq ($(HSE_VALUE_MHZ),) HSE_VALUE := $(shell echo $$(( $(HSE_VALUE_MHZ) * 1000000 )) ) endif -GYRO_DEFINE := $(shell grep " USE_GYRO_" $(CONFIG_HEADER_FILE) | awk '{print $$2}' ) - +TARGET := $(shell sed -E -n "/^\s*#\s*define\s+FC_TARGET_MCU\s+(\w+).*/s//\1/p" $(CONFIG_HEADER_FILE)) ifeq ($(TARGET),) $(error No TARGET identified. Is the $(CONFIG_HEADER_FILE) valid for $(CONFIG)?) endif -EXST_ADJUST_VMA := $(shell grep " FC_VMA_ADDRESS" $(CONFIG_HEADER_FILE) | awk '{print $$3}' ) +EXST_ADJUST_VMA := $(shell sed -E -n "/^\s*#\s*define\s+FC_VMA_ADDRESS\s+((0[xX])?[[:xdigit:]]+).*/s//\1/p" $(CONFIG_HEADER_FILE)) ifneq ($(EXST_ADJUST_VMA),) EXST = yes endif From c6a891e57e3b51056fbcd22a5d976054c8bd4de1 Mon Sep 17 00:00:00 2001 From: Mark Haslinghuis Date: Tue, 28 Jan 2025 01:32:08 +0100 Subject: [PATCH 090/244] Fix GYRO_CLKIN (#14213) * Fix GYRO_CLKIN * Update src/main/drivers/accgyro/accgyro_spi_icm426xx.c Co-authored-by: Petr Ledvina --------- Co-authored-by: Petr Ledvina --- src/main/drivers/accgyro/accgyro_spi_icm426xx.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/main/drivers/accgyro/accgyro_spi_icm426xx.c b/src/main/drivers/accgyro/accgyro_spi_icm426xx.c index 7d87a00383..5e8e4cc574 100644 --- a/src/main/drivers/accgyro/accgyro_spi_icm426xx.c +++ b/src/main/drivers/accgyro/accgyro_spi_icm426xx.c @@ -40,6 +40,7 @@ #include "drivers/bus_spi.h" #include "drivers/exti.h" #include "drivers/io.h" +#include "drivers/pwm_output.h" #include "drivers/sensor.h" #include "drivers/time.h" From 2d63010dc802745ad31825899bf262ecf6671aff Mon Sep 17 00:00:00 2001 From: Jay Blackman Date: Tue, 28 Jan 2025 11:37:57 +1100 Subject: [PATCH 091/244] Remove redundant SITL ioPortDef_s array definition (#14202) * Remove redundant SITL ioPortDef_s array definition * Minor cleanup of some logic where SIMULATOR is in ./src/main * Updated based on feedback from @ledvinap * Reducing scope as per @ledvinap * Fix unit test * Removing serial port avoidance in totality (unused). TODO: Remove PWM/PPM radio inputs in another PR. --- src/main/drivers/io.c | 4 --- src/main/drivers/serial_pinconfig.c | 2 +- src/main/fc/init.c | 35 +++++++++--------------- src/main/io/serial.c | 39 +++++++++------------------ src/main/io/serial.h | 2 +- src/platform/APM32/platform_mcu.h | 1 + src/platform/AT32/platform_mcu.h | 1 + src/platform/SIMULATOR/platform_mcu.h | 3 +++ src/platform/STM32/platform_mcu.h | 1 + src/test/unit/io_serial_unittest.cc | 4 +-- 10 files changed, 34 insertions(+), 58 deletions(-) diff --git a/src/main/drivers/io.c b/src/main/drivers/io.c index fcd8cb4c79..128d0afe69 100644 --- a/src/main/drivers/io.c +++ b/src/main/drivers/io.c @@ -31,10 +31,6 @@ struct ioPortDef_s { rccPeriphTag_t rcc; }; -#if defined(SITL) -const struct ioPortDef_s ioPortDefs[] = { 0 }; -#endif - ioRec_t* IO_Rec(IO_t io) { return io; diff --git a/src/main/drivers/serial_pinconfig.c b/src/main/drivers/serial_pinconfig.c index d72c8dbbff..97ce26bb58 100644 --- a/src/main/drivers/serial_pinconfig.c +++ b/src/main/drivers/serial_pinconfig.c @@ -24,7 +24,7 @@ #include "platform.h" -#if defined(USE_UART) || defined(USE_LPUART) || defined(USE_SOFTSERIAL) +#if SERIAL_TRAIT_PIN_CONFIG #include "build/build_config.h" diff --git a/src/main/fc/init.c b/src/main/fc/init.c index 8e1646411b..bc0726fbbc 100644 --- a/src/main/fc/init.c +++ b/src/main/fc/init.c @@ -521,22 +521,7 @@ void init(void) uartPinConfigure(serialPinConfig()); #endif -#if defined(AVOID_UART1_FOR_PWM_PPM) -# define SERIALPORT_TO_AVOID SERIAL_PORT_USART1 -#elif defined(AVOID_UART2_FOR_PWM_PPM) -# define SERIALPORT_TO_AVOID SERIAL_PORT_USART2 -#elif defined(AVOID_UART3_FOR_PWM_PPM) -# define SERIALPORT_TO_AVOID SERIAL_PORT_USART3 -#endif - { - serialPortIdentifier_e serialPortToAvoid = SERIAL_PORT_NONE; -#if defined(SERIALPORT_TO_AVOID) - if (featureIsEnabled(FEATURE_RX_PPM) || featureIsEnabled(FEATURE_RX_PARALLEL_PWM)) { - serialPortToAvoid = SERIALPORT_TO_AVOID; - } -#endif - serialInit(featureIsEnabled(FEATURE_SOFTSERIAL), serialPortToAvoid); - } + serialInit(featureIsEnabled(FEATURE_SOFTSERIAL)); mixerInit(mixerConfig()->mixerMode); @@ -545,20 +530,24 @@ void init(void) * may send spurious pulses to esc's causing their early initialization. Also ppm * receiver may share timer with motors so motors MUST be initialized here. */ motorDevInit(getMotorCount()); + // TODO: add check here that motors actually initialised correctly systemState |= SYSTEM_STATE_MOTORS_READY; #endif - if (0) {} + do { #if defined(USE_RX_PPM) - else if (featureIsEnabled(FEATURE_RX_PPM)) { - ppmRxInit(ppmConfig()); - } + if (featureIsEnabled(FEATURE_RX_PPM)) { + ppmRxInit(ppmConfig()); + break; + } #endif #if defined(USE_RX_PWM) - else if (featureIsEnabled(FEATURE_RX_PARALLEL_PWM)) { - pwmRxInit(pwmConfig()); - } + if (featureIsEnabled(FEATURE_RX_PARALLEL_PWM)) { + pwmRxInit(pwmConfig()); + break; + } #endif + } while (false); #ifdef USE_BEEPER beeperInit(beeperDevConfig()); diff --git a/src/main/io/serial.c b/src/main/io/serial.c index a97d8260a5..46dd18c269 100644 --- a/src/main/io/serial.c +++ b/src/main/io/serial.c @@ -572,41 +572,26 @@ void closeSerialPort(serialPort_t *serialPort) serialPortUsage->serialPort = NULL; } -void serialInit(bool softserialEnabled, serialPortIdentifier_e serialPortToDisable) +void serialInit(bool softserialEnabled) { -#if !defined(USE_SOFTSERIAL) - UNUSED(softserialEnabled); -#endif - memset(&serialPortUsageList, 0, sizeof(serialPortUsageList)); for (int index = 0; index < SERIAL_PORT_COUNT; index++) { serialPortUsageList[index].identifier = serialPortIdentifiers[index]; - if (serialPortToDisable != SERIAL_PORT_NONE - && serialPortUsageList[index].identifier == serialPortToDisable) { - serialPortUsageList[index].identifier = SERIAL_PORT_NONE; - continue; // this index is deleted +#if SERIAL_TRAIT_PIN_CONFIG + const int resourceIndex = serialResourceIndex(serialPortUsageList[index].identifier); + if (resourceIndex >= 0 && !(serialPinConfig()->ioTagTx[resourceIndex] || serialPinConfig()->ioTagRx[resourceIndex])) { + // resource exists but no pin is assigned + serialPortUsageList[index].identifier = SERIAL_PORT_NONE; + continue; } - { -#if !defined(SIMULATOR_BUILD) // no serialPinConfig on SITL - const int resourceIndex = serialResourceIndex(serialPortUsageList[index].identifier); - if (resourceIndex >= 0 // resource exists - && !(serialPinConfig()->ioTagTx[resourceIndex] || serialPinConfig()->ioTagRx[resourceIndex])) { - serialPortUsageList[index].identifier = SERIAL_PORT_NONE; - continue; - } #endif - } - if (serialType(serialPortUsageList[index].identifier) == SERIALTYPE_SOFTSERIAL) { - if (true -#ifdef USE_SOFTSERIAL - && !softserialEnabled -#endif - ) { - serialPortUsageList[index].identifier = SERIAL_PORT_NONE; - continue; - } + + if (serialType(serialPortUsageList[index].identifier) == SERIALTYPE_SOFTSERIAL && !softserialEnabled) { + // soft serial is not enabled, or not built into the firmware + serialPortUsageList[index].identifier = SERIAL_PORT_NONE; + continue; } } } diff --git a/src/main/io/serial.h b/src/main/io/serial.h index 4943597eaa..2f6e98c16f 100644 --- a/src/main/io/serial.h +++ b/src/main/io/serial.h @@ -171,7 +171,7 @@ typedef void serialConsumer(uint8_t); // // configuration // -void serialInit(bool softserialEnabled, serialPortIdentifier_e serialPortToDisable); +void serialInit(bool softserialEnabled); void serialRemovePort(serialPortIdentifier_e identifier); bool serialIsPortAvailable(serialPortIdentifier_e identifier); bool isSerialConfigValid(serialConfig_t *serialConfig); diff --git a/src/platform/APM32/platform_mcu.h b/src/platform/APM32/platform_mcu.h index 2962b97218..10299b6d5c 100644 --- a/src/platform/APM32/platform_mcu.h +++ b/src/platform/APM32/platform_mcu.h @@ -192,6 +192,7 @@ #define PLATFORM_TRAIT_RCC 1 #define UART_TRAIT_AF_PORT 1 +#define SERIAL_TRAIT_PIN_CONFIG 1 #define UARTHARDWARE_MAX_PINS 4 diff --git a/src/platform/AT32/platform_mcu.h b/src/platform/AT32/platform_mcu.h index 7dbc1c7adf..dc2e81e248 100644 --- a/src/platform/AT32/platform_mcu.h +++ b/src/platform/AT32/platform_mcu.h @@ -147,6 +147,7 @@ typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; #define PLATFORM_TRAIT_RCC 1 #define UART_TRAIT_AF_PIN 1 #define UART_TRAIT_PINSWAP 1 +#define SERIAL_TRAIT_PIN_CONFIG 1 #define UARTHARDWARE_MAX_PINS 5 diff --git a/src/platform/SIMULATOR/platform_mcu.h b/src/platform/SIMULATOR/platform_mcu.h index 5e9fb85ac6..be11284f04 100644 --- a/src/platform/SIMULATOR/platform_mcu.h +++ b/src/platform/SIMULATOR/platform_mcu.h @@ -30,3 +30,6 @@ #define IOCFG_IN_FLOATING 0 #define SPIDEV_COUNT 0 + +// no serial pins are defined for the simulator +#define SERIAL_TRAIT_PIN_CONFIG 0 diff --git a/src/platform/STM32/platform_mcu.h b/src/platform/STM32/platform_mcu.h index 69522ba54a..9dd2114b98 100644 --- a/src/platform/STM32/platform_mcu.h +++ b/src/platform/STM32/platform_mcu.h @@ -417,4 +417,5 @@ extern uint8_t _dmaram_end__; #define DMA_TRAIT_CHANNEL 1 #endif +#define SERIAL_TRAIT_PIN_CONFIG 1 #define USB_DP_PIN PA12 diff --git a/src/test/unit/io_serial_unittest.cc b/src/test/unit/io_serial_unittest.cc index 4f5a199894..c0f5975052 100644 --- a/src/test/unit/io_serial_unittest.cc +++ b/src/test/unit/io_serial_unittest.cc @@ -33,7 +33,7 @@ extern "C" { #include "pg/pg_ids.h" #include "pg/rx.h" - void serialInit(bool softserialEnabled, serialPortIdentifier_e serialPortToDisable); + void serialInit(bool softserialEnabled); PG_REGISTER(rxConfig_t, rxConfig, PG_RX_CONFIG, 0); PG_REGISTER(serialPinConfig_t, serialPinConfig, PG_SERIAL_PIN_CONFIG, 0); @@ -45,7 +45,7 @@ extern "C" { TEST(IoSerialTest, TestFindPortConfig) { // given - serialInit(false, SERIAL_PORT_NONE); + serialInit(false); // when const serialPortConfig_t *portConfig = findSerialPortConfig(FUNCTION_MSP); From 25f65cbc01ba4ea315f43a2b77fe7c8e235e3137 Mon Sep 17 00:00:00 2001 From: "Git bot (blckmn)" Date: Tue, 28 Jan 2025 06:25:04 +0000 Subject: [PATCH 092/244] Auto updated submodule references [28-01-2025] --- src/config | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/config b/src/config index 254ebace60..5e33fe422e 160000 --- a/src/config +++ b/src/config @@ -1 +1 @@ -Subproject commit 254ebace60b95e608861c42acc95481226b5f1e8 +Subproject commit 5e33fe422e2c1fb095db84508a9e3ebb465a80a4 From b277364b2cd79d7d7d7192c8a48603fe38638f67 Mon Sep 17 00:00:00 2001 From: Petr Ledvina Date: Tue, 28 Jan 2025 20:20:12 +0100 Subject: [PATCH 093/244] Refactor missing prototypes 2 (#14170) --- src/main/build/debug_pin.c | 4 +- src/main/cli/cli.c | 30 ++++++++----- src/main/cms/cms.c | 2 +- src/main/cms/cms_menu_vtx_msp.c | 2 + src/main/cms/cms_menu_vtx_smartaudio.h | 2 +- src/main/cms/cms_menu_vtx_tramp.c | 2 + src/main/common/explog_approx.c | 2 + src/main/common/gps_conversion.c | 2 + src/main/common/strtol.c | 4 +- src/main/common/typeconversion.c | 6 ++- src/main/common/utils.h | 3 ++ src/main/config/config.c | 2 +- src/main/config/config_eeprom.c | 2 +- src/main/drivers/accgyro/accgyro_spi_bmi160.c | 8 ++-- src/main/drivers/accgyro/accgyro_spi_bmi270.c | 4 +- .../drivers/accgyro/accgyro_spi_lsm6dsv16x.c | 6 +-- .../drivers/accgyro/accgyro_spi_mpu6000.c | 4 +- .../drivers/accgyro/accgyro_spi_mpu9250.c | 4 +- src/main/drivers/adc_impl.h | 4 ++ src/main/drivers/barometer/barometer_bmp280.c | 4 +- src/main/drivers/barometer/barometer_bmp388.c | 8 ++-- src/main/drivers/barometer/barometer_lps.c | 6 +-- .../drivers/barometer/barometer_lps22df.c | 4 +- src/main/drivers/barometer/barometer_ms5611.c | 4 +- .../drivers/barometer/barometer_qmp6988.c | 4 +- src/main/drivers/bus_i2c_busdev.c | 1 + src/main/drivers/bus_i2c_busdev.h | 2 +- src/main/drivers/bus_i2c_timing.c | 2 + src/main/drivers/bus_spi.h | 2 +- src/main/drivers/bus_spi_config.c | 1 + src/main/drivers/compass/compass_ak8963.c | 4 +- src/main/drivers/compass/compass_lis2mdl.c | 2 + src/main/drivers/compass/compass_lis3mdl.c | 2 + src/main/drivers/dshot.c | 4 +- src/main/drivers/dshot_bitbang.h | 2 +- src/main/drivers/flash/flash.c | 2 +- src/main/drivers/flash/flash_m25p16.c | 8 ++-- src/main/drivers/flash/flash_w25m.c | 18 ++++---- src/main/drivers/flash/flash_w25n.c | 44 +++++++++---------- src/main/drivers/flash/flash_w25q128fv.c | 10 ++--- src/main/drivers/io.c | 4 ++ src/main/drivers/light_led.c | 5 ++- src/main/drivers/light_led.h | 4 +- src/main/drivers/max7456.c | 4 +- src/main/drivers/pin_pull_up_down.h | 2 +- .../drivers/rangefinder/rangefinder_hcsr04.c | 10 ++--- .../drivers/rangefinder/rangefinder_lidarmt.c | 2 +- .../drivers/rangefinder/rangefinder_lidartf.c | 6 +-- src/main/drivers/rx/rx_cc2500.c | 4 +- src/main/drivers/rx/rx_pwm.c | 11 +++-- src/main/drivers/rx/rx_spi.c | 2 +- src/main/drivers/rx/rx_spi.h | 4 +- src/main/drivers/rx/rx_sx1280.c | 2 +- src/main/drivers/rx/rx_sx1280.h | 2 +- src/main/drivers/sdcard_sdio_baremetal.c | 6 +-- src/main/drivers/sdcard_spi.c | 8 ++-- src/main/drivers/sdio.h | 2 +- src/main/drivers/serial.h | 2 +- src/main/drivers/serial_impl.h | 3 ++ src/main/drivers/serial_softserial.c | 14 +++--- src/main/drivers/serial_tcp.c | 10 ++--- src/main/drivers/vtx_rtc6705_soft_spi.c | 2 + src/main/drivers/vtx_table.c | 2 +- src/main/fc/board_info.c | 1 + src/main/fc/board_info.h | 12 ++--- src/main/fc/core.c | 4 +- src/main/fc/core.h | 6 +-- src/main/fc/gps_lap_timer.c | 2 +- src/main/fc/rc.c | 14 +++--- src/main/fc/rc_controls.h | 2 +- src/main/fc/rc_modes.c | 4 +- src/main/fc/tasks.c | 4 +- src/main/fc/tasks.h | 2 +- src/main/flight/alt_hold_multirotor.c | 8 ++-- src/main/flight/alt_hold_wing.c | 2 +- src/main/flight/autopilot_multirotor.c | 4 +- src/main/flight/failsafe.c | 2 +- src/main/flight/gps_rescue_multirotor.c | 6 +-- src/main/flight/imu.c | 2 +- src/main/flight/mixer_init.c | 2 +- src/main/flight/pid.c | 2 +- src/main/flight/pid.h | 6 +-- src/main/flight/pid_init.c | 12 ++--- src/main/flight/pos_hold_multirotor.c | 4 +- src/main/flight/servos.c | 2 +- src/main/io/dashboard.c | 4 +- src/main/io/displayport_hott.c | 2 + src/main/io/displayport_hott.h | 4 +- src/main/io/displayport_max7456.c | 2 +- src/main/io/displayport_oled.c | 2 + src/main/io/flashfs.c | 2 +- src/main/io/gps.c | 8 ++-- src/main/io/ledstrip.c | 4 +- src/main/io/pidaudio.c | 4 +- src/main/io/rcdevice.h | 2 +- src/main/io/serial.c | 2 +- src/main/io/serial.h | 1 - src/main/io/serial_4way.c | 2 +- src/main/io/serial_resource.c | 2 + src/main/io/spektrum_rssi.c | 2 +- src/main/io/spektrum_vtx_control.c | 2 +- src/main/io/statusindicator.c | 2 +- src/main/io/usb_cdc_hid.h | 2 +- src/main/io/usb_msc.c | 1 + src/main/io/vtx_smartaudio.c | 2 +- src/main/io/vtx_tramp.h | 4 +- src/main/msc/emfat.c | 20 ++++----- src/main/msp/msp.c | 4 +- src/main/msp/msp_serial.c | 2 +- src/main/osd/osd.c | 6 +-- src/main/osd/osd_elements.c | 2 +- src/main/pg/bus_i2c.c | 4 +- src/main/pg/pg.h | 2 +- src/main/rx/cc2500_frsky_x.c | 2 +- src/main/rx/cc2500_redpine.c | 4 +- src/main/rx/cc2500_sfhss.c | 4 +- src/main/rx/cyrf6936_spektrum.c | 2 +- src/main/rx/expresslrs.c | 2 +- src/main/rx/jetiexbus.c | 4 +- src/main/rx/msp.h | 2 +- src/main/rx/rx.c | 2 +- src/main/rx/spektrum.c | 2 +- src/main/rx/spektrum.h | 2 +- src/main/rx/srxl2.c | 10 ++--- src/main/scheduler/scheduler.c | 12 ++--- src/main/scheduler/scheduler.h | 8 ++-- src/main/sensors/acceleration_init.c | 6 +-- src/main/sensors/adcinternal.c | 4 +- src/main/sensors/battery.c | 2 +- src/main/sensors/compass.c | 4 +- src/main/sensors/esc_sensor.c | 2 +- src/main/sensors/gyro.c | 6 +-- src/main/sensors/gyro_init.c | 2 + src/main/sensors/opticalflow.c | 2 +- src/main/sensors/rangefinder.c | 2 +- src/main/sensors/voltage.c | 2 +- src/main/telemetry/crsf.c | 24 +++++----- src/main/telemetry/frsky_hub.c | 2 +- src/main/telemetry/ghst.c | 8 ++-- src/main/telemetry/hott.c | 4 +- src/main/telemetry/hott.h | 6 +-- src/main/telemetry/jetiexbus.c | 14 +++--- src/main/telemetry/mavlink.c | 12 ++--- src/main/telemetry/msp_shared.c | 2 +- src/main/telemetry/srxl.c | 14 +++--- src/platform/APM32/adc_apm32f4xx.c | 4 +- src/platform/APM32/dshot_bitbang_ddl.c | 2 +- src/platform/APM32/eint_apm32.c | 2 +- src/platform/APM32/light_ws2811strip_apm32.c | 2 +- src/platform/APM32/persistent_apm32.c | 2 +- src/platform/APM32/pwm_output_apm32.c | 8 ++-- src/platform/APM32/startup/system_apm32f4xx.c | 2 +- src/platform/APM32/timer_apm32.c | 2 +- src/platform/AT32/adc_at32f43x.c | 8 ++-- src/platform/AT32/dshot_bitbang_stdperiph.c | 2 +- src/platform/AT32/exti_at32.c | 2 +- src/platform/AT32/persistent_at32bsp.c | 2 +- src/platform/AT32/pwm_output_at32bsp.c | 8 ++-- src/platform/AT32/pwm_output_dshot.c | 2 +- src/platform/AT32/serial_usb_vcp_at32f4.c | 6 +-- src/platform/AT32/system_at32f43x.c | 2 +- src/platform/AT32/timer_at32bsp.c | 2 +- src/platform/AT32/usb_msc_at32f43x.c | 5 ++- src/platform/SIMULATOR/sitl.c | 15 +++++-- src/platform/STM32/adc_stm32f4xx.c | 4 +- src/platform/STM32/adc_stm32f7xx.c | 4 +- src/platform/STM32/adc_stm32g4xx.c | 8 ++-- src/platform/STM32/adc_stm32h7xx.c | 8 ++-- src/platform/STM32/bus_i2c_stm32f4xx.c | 2 +- src/platform/STM32/bus_octospi_stm32h7xx.c | 14 +++--- src/platform/STM32/bus_quadspi_hal.c | 8 ++-- src/platform/STM32/dma_stm32f4xx.c | 2 +- src/platform/STM32/dshot_bitbang_ll.c | 2 +- src/platform/STM32/dshot_bitbang_stdperiph.c | 2 +- src/platform/STM32/exti.c | 2 +- src/platform/STM32/light_ws2811strip_hal.c | 2 +- src/platform/STM32/pwm_output_hw.c | 8 ++-- src/platform/STM32/sdio_f4xx.c | 6 +-- src/platform/STM32/sdio_f7xx.c | 2 +- src/platform/STM32/startup/system_stm32f4xx.c | 2 +- src/platform/STM32/startup/system_stm32h7xx.c | 6 ++- src/platform/STM32/system_stm32g4xx.c | 2 +- src/platform/STM32/system_stm32h7xx.c | 4 +- src/platform/STM32/timer_hal.c | 2 +- src/platform/STM32/timer_stdperiph.c | 2 +- src/platform/STM32/vcp_hal/usbd_cdc_hid.c | 2 + .../STM32/vcp_hal/usbd_conf_stm32g4xx.c | 4 +- src/platform/STM32/vcpf4/usb_bsp.c | 4 +- src/platform/STM32/vcpf4/usb_cdc_hid.c | 2 + src/platform/STM32/vcpf4/usbd_cdc_vcp.c | 2 +- src/platform/common/stm32/config_flash.c | 1 + src/platform/common/stm32/system.c | 1 + 192 files changed, 487 insertions(+), 410 deletions(-) diff --git a/src/main/build/debug_pin.c b/src/main/build/debug_pin.c index c3017a00f0..eb070f369f 100644 --- a/src/main/build/debug_pin.c +++ b/src/main/build/debug_pin.c @@ -20,13 +20,13 @@ #include "platform.h" +#include "debug_pin.h" + #ifdef USE_DEBUG_PIN #include "drivers/io.h" #include "drivers/io_impl.h" -#include "debug_pin.h" - typedef struct dbgPinState_s { GPIO_TypeDef *gpio; uint32_t setBSRR; diff --git a/src/main/cli/cli.c b/src/main/cli/cli.c index cb8c116594..a619f06a83 100644 --- a/src/main/cli/cli.c +++ b/src/main/cli/cli.c @@ -339,31 +339,37 @@ static void cliWriterFlush(void) cliWriterFlushInternal(cliWriter); } -void cliPrint(const char *str) +#ifdef USE_CLI_DEBUG_PRINT +#define CLI_DEBUG_EXPORT /* empty */ +#else +#define CLI_DEBUG_EXPORT static +#endif + +CLI_DEBUG_EXPORT void cliPrint(const char *str) { cliPrintInternal(cliWriter, str); } -void cliPrintLinefeed(void) +CLI_DEBUG_EXPORT void cliPrintLinefeed(void) { cliPrint("\r\n"); } -void cliPrintLine(const char *str) +CLI_DEBUG_EXPORT void cliPrintLine(const char *str) { cliPrint(str); cliPrintLinefeed(); } -#ifdef MINIMAL_CLI -#define cliPrintHashLine(str) -#else static void cliPrintHashLine(const char *str) { +#ifndef MINIMAL_CLI cliPrint("\r\n# "); cliPrintLine(str); -} +#else + UNUSED(str); #endif +} static void cliPutp(void *p, char ch) { @@ -415,7 +421,7 @@ static bool cliDefaultPrintLinef(dumpFlags_t dumpMask, bool equalsDefault, const } } -void cliPrintf(const char *format, ...) +CLI_DEBUG_EXPORT void cliPrintf(const char *format, ...) { va_list va; va_start(va, format); @@ -423,7 +429,7 @@ void cliPrintf(const char *format, ...) va_end(va); } -void cliPrintLinef(const char *format, ...) +CLI_DEBUG_EXPORT void cliPrintLinef(const char *format, ...) { va_list va; va_start(va, format); @@ -3228,7 +3234,7 @@ static void cliManufacturerId(const char *cmdName, char *cmdline) } #if defined(USE_SIGNATURE) -static void writeSignature(char *signatureStr, uint8_t *signature) +static void writeSignature(char *signatureStr, const uint8_t *signature) { for (unsigned i = 0; i < SIGNATURE_LENGTH; i++) { tfp_sprintf(&signatureStr[2 * i], "%02x", signature[i]); @@ -4269,7 +4275,7 @@ static bool prepareSave(void) return true; } -bool tryPrepareSave(const char *cmdName) +static bool tryPrepareSave(const char *cmdName) { bool success = prepareSave(); #if defined(USE_CLI_BATCH) @@ -4443,7 +4449,7 @@ static uint8_t getWordLength(const char *bufBegin, const char *bufEnd) return bufEnd - bufBegin; } -uint16_t cliGetSettingIndex(const char *name, size_t length) +STATIC_UNIT_TESTED uint16_t cliGetSettingIndex(const char *name, size_t length) { for (uint32_t i = 0; i < valueTableEntryCount; i++) { const char *settingName = valueTable[i].name; diff --git a/src/main/cms/cms.c b/src/main/cms/cms.c index af8f84622f..24c0daab01 100644 --- a/src/main/cms/cms.c +++ b/src/main/cms/cms.c @@ -1375,7 +1375,7 @@ void cmsSetExternKey(cms_key_e extKey) externKey = extKey; } -uint16_t cmsHandleKeyWithRepeat(displayPort_t *pDisplay, cms_key_e key, int repeatCount) +static uint16_t cmsHandleKeyWithRepeat(displayPort_t *pDisplay, cms_key_e key, int repeatCount) { uint16_t ret = 0; diff --git a/src/main/cms/cms_menu_vtx_msp.c b/src/main/cms/cms_menu_vtx_msp.c index 6f1cd42b63..288887f767 100644 --- a/src/main/cms/cms_menu_vtx_msp.c +++ b/src/main/cms/cms_menu_vtx_msp.c @@ -41,6 +41,8 @@ #include "io/vtx_msp.h" #include "io/vtx.h" +#include "cms_menu_vtx_msp.h" + char mspCmsStatusString[31] = "- -- ---- ----"; // m bc ffff tppp // 01234567890123 diff --git a/src/main/cms/cms_menu_vtx_smartaudio.h b/src/main/cms/cms_menu_vtx_smartaudio.h index 3140ffa3aa..7291660cdd 100644 --- a/src/main/cms/cms_menu_vtx_smartaudio.h +++ b/src/main/cms/cms_menu_vtx_smartaudio.h @@ -27,4 +27,4 @@ extern CMS_Menu cmsx_menuVtxSmartAudio; void saCmsUpdate(void); void saUpdateStatusString(void); -void saCmsResetOpmodel(); +void saCmsResetOpmodel(void); diff --git a/src/main/cms/cms_menu_vtx_tramp.c b/src/main/cms/cms_menu_vtx_tramp.c index c3a1f3a385..0a0cea8e4e 100644 --- a/src/main/cms/cms_menu_vtx_tramp.c +++ b/src/main/cms/cms_menu_vtx_tramp.c @@ -41,6 +41,8 @@ #include "io/vtx_tramp.h" #include "io/vtx.h" +#include "cms_menu_vtx_tramp.h" + char trampCmsStatusString[31] = "- -- ---- ----"; // m bc ffff tppp // 01234567890123 diff --git a/src/main/common/explog_approx.c b/src/main/common/explog_approx.c index b2eae4468e..ff50937801 100644 --- a/src/main/common/explog_approx.c +++ b/src/main/common/explog_approx.c @@ -32,6 +32,8 @@ Stripped down for BF use #include "platform.h" +#include "common/maths.h" + /* Workaround a lack of optimization in gcc */ float exp_cst1 = 2139095040.f; float exp_cst2 = 0.f; diff --git a/src/main/common/gps_conversion.c b/src/main/common/gps_conversion.c index 33fe1778f8..7b88e93aff 100644 --- a/src/main/common/gps_conversion.c +++ b/src/main/common/gps_conversion.c @@ -25,6 +25,8 @@ #include "platform.h" +#include "gps_conversion.h" + #ifdef USE_GPS #define DIGIT_TO_VAL(_x) (_x - '0') diff --git a/src/main/common/strtol.c b/src/main/common/strtol.c index 1d1e0413ff..f94f3fc38d 100644 --- a/src/main/common/strtol.c +++ b/src/main/common/strtol.c @@ -26,9 +26,11 @@ #include "common/utils.h" +#include "strtol.h" + #define _STRTO_ENDPTR 1 -unsigned long _strto_l(const char * str, char ** endptr, int base, int sflag) +static unsigned long _strto_l(const char * str, char ** endptr, int base, int sflag) { unsigned long number, cutoff; #if _STRTO_ENDPTR diff --git a/src/main/common/typeconversion.c b/src/main/common/typeconversion.c index 166339b300..1e2636c4b0 100644 --- a/src/main/common/typeconversion.c +++ b/src/main/common/typeconversion.c @@ -26,7 +26,9 @@ #include "platform.h" #include "build/build_config.h" -#include "maths.h" +#include "common/maths.h" + +#include "typeconversion.h" #ifdef REQUIRE_PRINTF_LONG_SUPPORT @@ -86,7 +88,7 @@ void i2a(int num, char *bf) ui2a(num, 10, 0, bf); } -int a2d(char ch) +static int a2d(char ch) { if (ch >= '0' && ch <= '9') return ch - '0'; diff --git a/src/main/common/utils.h b/src/main/common/utils.h index 3ec18bdd06..c23155cfa1 100644 --- a/src/main/common/utils.h +++ b/src/main/common/utils.h @@ -58,6 +58,9 @@ #define UNUSED(x) (void)(x) // Variables and parameters that are not used #endif +#define MAYBE_UNUSED __attribute__ ((unused)) +#define LOCAL_UNUSED_FUNCTION __attribute__ ((unused, deprecated ("function is marked as LOCAL_UNUSED_FUNCTION"))) + #define DISCARD(x) (void)(x) // To explicitly ignore result of x (usually an I/O register access). #ifndef __cplusplus diff --git a/src/main/config/config.c b/src/main/config/config.c index 002797cec0..16250fa3eb 100644 --- a/src/main/config/config.c +++ b/src/main/config/config.c @@ -217,7 +217,7 @@ static void validateAndFixConfig(void) #endif if (!isSerialConfigValid(serialConfigMutable())) { - pgResetFn_serialConfig(serialConfigMutable()); + PG_RESET(serialConfig); } #if defined(USE_GPS) diff --git a/src/main/config/config_eeprom.c b/src/main/config/config_eeprom.c index 83e2d79fa2..4b48a3914d 100644 --- a/src/main/config/config_eeprom.c +++ b/src/main/config/config_eeprom.c @@ -87,7 +87,7 @@ typedef struct { } PG_PACKED packingTest_t; #if defined(CONFIG_IN_EXTERNAL_FLASH) || defined(CONFIG_IN_MEMORY_MAPPED_FLASH) -MMFLASH_CODE bool loadEEPROMFromExternalFlash(void) +static MMFLASH_CODE bool loadEEPROMFromExternalFlash(void) { const flashPartition_t *flashPartition = flashPartitionFindByType(FLASH_PARTITION_TYPE_CONFIG); const flashGeometry_t *flashGeometry = flashGetGeometry(); diff --git a/src/main/drivers/accgyro/accgyro_spi_bmi160.c b/src/main/drivers/accgyro/accgyro_spi_bmi160.c index 206417d188..31260a0f96 100644 --- a/src/main/drivers/accgyro/accgyro_spi_bmi160.c +++ b/src/main/drivers/accgyro/accgyro_spi_bmi160.c @@ -267,7 +267,7 @@ extiCallbackRec_t bmi160IntCallbackRec; // Called in ISR context // Gyro read has just completed -busStatus_e bmi160Intcallback(uint32_t arg) +static busStatus_e bmi160Intcallback(uint32_t arg) { gyroDev_t *gyro = (gyroDev_t *)arg; int32_t gyroDmaDuration = cmpTimeCycles(getCycleCounter(), gyro->gyroLastEXTI); @@ -281,7 +281,7 @@ busStatus_e bmi160Intcallback(uint32_t arg) return BUS_READY; } -void bmi160ExtiHandler(extiCallbackRec_t *cb) +static void bmi160ExtiHandler(extiCallbackRec_t *cb) { gyroDev_t *gyro = container_of(cb, gyroDev_t, exti); extDevice_t *dev = &gyro->dev; @@ -440,7 +440,7 @@ static bool bmi160GyroRead(gyroDev_t *gyro) return true; } -void bmi160SpiGyroInit(gyroDev_t *gyro) +static void bmi160SpiGyroInit(gyroDev_t *gyro) { extDevice_t *dev = &gyro->dev; @@ -450,7 +450,7 @@ void bmi160SpiGyroInit(gyroDev_t *gyro) spiSetClkDivisor(dev, spiCalculateDivider(BMI160_MAX_SPI_CLK_HZ)); } -void bmi160SpiAccInit(accDev_t *acc) +static void bmi160SpiAccInit(accDev_t *acc) { acc->acc_1G = 512 * 8; } diff --git a/src/main/drivers/accgyro/accgyro_spi_bmi270.c b/src/main/drivers/accgyro/accgyro_spi_bmi270.c index 79ab79077e..f13f39c75f 100644 --- a/src/main/drivers/accgyro/accgyro_spi_bmi270.c +++ b/src/main/drivers/accgyro/accgyro_spi_bmi270.c @@ -278,7 +278,7 @@ extiCallbackRec_t bmi270IntCallbackRec; */ // Called in ISR context // Gyro read has just completed -busStatus_e bmi270Intcallback(uint32_t arg) +static busStatus_e bmi270Intcallback(uint32_t arg) { gyroDev_t *gyro = (gyroDev_t *)arg; int32_t gyroDmaDuration = cmpTimeCycles(getCycleCounter(), gyro->gyroLastEXTI); @@ -292,7 +292,7 @@ busStatus_e bmi270Intcallback(uint32_t arg) return BUS_READY; } -void bmi270ExtiHandler(extiCallbackRec_t *cb) +static void bmi270ExtiHandler(extiCallbackRec_t *cb) { gyroDev_t *gyro = container_of(cb, gyroDev_t, exti); extDevice_t *dev = &gyro->dev; diff --git a/src/main/drivers/accgyro/accgyro_spi_lsm6dsv16x.c b/src/main/drivers/accgyro/accgyro_spi_lsm6dsv16x.c index 21f33a7a35..c29aa85e68 100644 --- a/src/main/drivers/accgyro/accgyro_spi_lsm6dsv16x.c +++ b/src/main/drivers/accgyro/accgyro_spi_lsm6dsv16x.c @@ -856,7 +856,7 @@ uint8_t lsm6dsv16xSpiDetect(const extDevice_t *dev) return LSM6DSV16X_SPI; } -void lsm6dsv16xAccInit(accDev_t *acc) +static void lsm6dsv16xAccInit(accDev_t *acc) { // ±16G mode acc->acc_1G = 512 * 4; @@ -924,7 +924,7 @@ bool lsm6dsv16xSpiAccDetect(accDev_t *acc) return true; } -void lsm6dsv16xGyroInit(gyroDev_t *gyro) +static void lsm6dsv16xGyroInit(gyroDev_t *gyro) { const extDevice_t *dev = &gyro->dev; // Set default LPF1 filter bandwidth to be as close as possible to MPU6000's 250Hz cutoff @@ -1009,7 +1009,7 @@ void lsm6dsv16xGyroInit(gyroDev_t *gyro) mpuGyroInit(gyro); } -bool lsm6dsv16xGyroReadSPI(gyroDev_t *gyro) +static bool lsm6dsv16xGyroReadSPI(gyroDev_t *gyro) { int16_t *gyroData = (int16_t *)gyro->dev.rxBuf; switch (gyro->gyroModeSPI) { diff --git a/src/main/drivers/accgyro/accgyro_spi_mpu6000.c b/src/main/drivers/accgyro/accgyro_spi_mpu6000.c index b94293758d..07f436c54d 100644 --- a/src/main/drivers/accgyro/accgyro_spi_mpu6000.c +++ b/src/main/drivers/accgyro/accgyro_spi_mpu6000.c @@ -100,7 +100,7 @@ static void mpu6000AccAndGyroInit(gyroDev_t *gyro); #define MPU6000_REV_D9 0x59 #define MPU6000_REV_D10 0x5A -void mpu6000SpiGyroInit(gyroDev_t *gyro) +static void mpu6000SpiGyroInit(gyroDev_t *gyro) { extDevice_t *dev = &gyro->dev; @@ -121,7 +121,7 @@ void mpu6000SpiGyroInit(gyroDev_t *gyro) } } -void mpu6000SpiAccInit(accDev_t *acc) +static void mpu6000SpiAccInit(accDev_t *acc) { acc->acc_1G = 512 * 4; } diff --git a/src/main/drivers/accgyro/accgyro_spi_mpu9250.c b/src/main/drivers/accgyro/accgyro_spi_mpu9250.c index eca0f03b6d..7ebc32b201 100644 --- a/src/main/drivers/accgyro/accgyro_spi_mpu9250.c +++ b/src/main/drivers/accgyro/accgyro_spi_mpu9250.c @@ -69,7 +69,7 @@ static bool mpu9250SpiSlowReadRegisterBuffer(const extDevice_t *dev, uint8_t reg return true; } -void mpu9250SpiGyroInit(gyroDev_t *gyro) +static void mpu9250SpiGyroInit(gyroDev_t *gyro) { extDevice_t *dev = &gyro->dev; @@ -86,7 +86,7 @@ void mpu9250SpiGyroInit(gyroDev_t *gyro) } } -void mpu9250SpiAccInit(accDev_t *acc) +static void mpu9250SpiAccInit(accDev_t *acc) { acc->acc_1G = 512 * 4; } diff --git a/src/main/drivers/adc_impl.h b/src/main/drivers/adc_impl.h index d9b337b45e..66baa5da9c 100644 --- a/src/main/drivers/adc_impl.h +++ b/src/main/drivers/adc_impl.h @@ -73,8 +73,10 @@ typedef struct adcTagMap_s { #define ADC_DEVICES_345 ((1 << ADCDEV_3)|(1 << ADCDEV_4)|(1 << ADCDEV_5)) typedef struct adcDevice_s { +#if !defined(SIMULATOR_BUILD) ADC_TypeDef* ADCx; rccPeriphTag_t rccADC; +#endif #if !defined(USE_DMA_SPEC) dmaResource_t* dmaResource; #if defined(STM32F4) || defined(STM32F7) || defined(STM32H7) || defined(STM32G4) || defined(APM32F4) @@ -104,7 +106,9 @@ extern adcOperatingConfig_t adcOperatingConfig[ADC_CHANNEL_COUNT]; extern volatile uint16_t adcValues[ADC_CHANNEL_COUNT]; uint8_t adcChannelByTag(ioTag_t ioTag); +#if !defined(SIMULATOR_BUILD) ADCDevice adcDeviceByInstance(const ADC_TypeDef *instance); +#endif bool adcVerifyPin(ioTag_t tag, ADCDevice device); // Marshall values in DMA instance/channel based order to adcChannel based order. diff --git a/src/main/drivers/barometer/barometer_bmp280.c b/src/main/drivers/barometer/barometer_bmp280.c index 4dc55468e5..efaaff941b 100644 --- a/src/main/drivers/barometer/barometer_bmp280.c +++ b/src/main/drivers/barometer/barometer_bmp280.c @@ -117,7 +117,7 @@ static bool bmp280GetUP(baroDev_t *baro); STATIC_UNIT_TESTED void bmp280Calculate(int32_t *pressure, int32_t *temperature); -void bmp280BusInit(const extDevice_t *dev) +static void bmp280BusInit(const extDevice_t *dev) { #ifdef USE_BARO_SPI_BMP280 if (dev->bus->busType == BUS_TYPE_SPI) { @@ -131,7 +131,7 @@ void bmp280BusInit(const extDevice_t *dev) #endif } -void bmp280BusDeinit(const extDevice_t *dev) +static void bmp280BusDeinit(const extDevice_t *dev) { #ifdef USE_BARO_SPI_BMP280 if (dev->bus->busType == BUS_TYPE_SPI) { diff --git a/src/main/drivers/barometer/barometer_bmp388.c b/src/main/drivers/barometer/barometer_bmp388.c index 6fa2e1efb7..a00c1fbccb 100644 --- a/src/main/drivers/barometer/barometer_bmp388.c +++ b/src/main/drivers/barometer/barometer_bmp388.c @@ -198,7 +198,7 @@ static bool bmp388ReadRegisterBuffer(const extDevice_t *dev, uint8_t reg, uint8_ } } -void bmp388_extiHandler(extiCallbackRec_t* cb) +static void bmp388_extiHandler(extiCallbackRec_t* cb) { #ifdef DEBUG static uint32_t bmp388ExtiCallbackCounter = 0; @@ -212,7 +212,7 @@ void bmp388_extiHandler(extiCallbackRec_t* cb) bmp388ReadRegisterBuffer(&baro->dev, BMP388_INT_STATUS_REG, &intStatus, 1); } -void bmp388BusInit(const extDevice_t *dev) +static void bmp388BusInit(const extDevice_t *dev) { #ifdef USE_BARO_SPI_BMP388 if (dev->bus->busType == BUS_TYPE_SPI) { @@ -226,7 +226,7 @@ void bmp388BusInit(const extDevice_t *dev) #endif } -void bmp388BusDeinit(const extDevice_t *dev) +static void bmp388BusDeinit(const extDevice_t *dev) { #ifdef USE_BARO_SPI_BMP388 if (dev->bus->busType == BUS_TYPE_SPI) { @@ -237,7 +237,7 @@ void bmp388BusDeinit(const extDevice_t *dev) #endif } -bool bmp388BeginForcedMeasurement(const extDevice_t *dev) +static bool bmp388BeginForcedMeasurement(const extDevice_t *dev) { // enable pressure measurement, temperature measurement, set power mode and start sampling uint8_t mode = BMP388_MODE_FORCED << 4 | 1 << 1 | 1 << 0; diff --git a/src/main/drivers/barometer/barometer_lps.c b/src/main/drivers/barometer/barometer_lps.c index 021c784cfc..11591d32af 100644 --- a/src/main/drivers/barometer/barometer_lps.c +++ b/src/main/drivers/barometer/barometer_lps.c @@ -191,17 +191,17 @@ static uint32_t rawP = 0; static uint16_t rawT = 0; -bool lpsWriteCommand(const extDevice_t *dev, uint8_t cmd, uint8_t byte) +static bool lpsWriteCommand(const extDevice_t *dev, uint8_t cmd, uint8_t byte) { return spiWriteRegRB(dev, cmd, byte); } -bool lpsReadCommand(const extDevice_t *dev, uint8_t cmd, uint8_t *data, uint8_t len) +static bool lpsReadCommand(const extDevice_t *dev, uint8_t cmd, uint8_t *data, uint8_t len) { return spiReadRegMskBufRB(dev, cmd | 0x80 | 0x40, data, len); } -bool lpsWriteVerify(const extDevice_t *dev, uint8_t cmd, uint8_t byte) +static bool lpsWriteVerify(const extDevice_t *dev, uint8_t cmd, uint8_t byte) { uint8_t temp = 0xff; spiWriteReg(dev, cmd, byte); diff --git a/src/main/drivers/barometer/barometer_lps22df.c b/src/main/drivers/barometer/barometer_lps22df.c index 4ab3620e6c..c5e773943b 100644 --- a/src/main/drivers/barometer/barometer_lps22df.c +++ b/src/main/drivers/barometer/barometer_lps22df.c @@ -227,7 +227,7 @@ static bool lps22dfGetUP(baroDev_t *baro); STATIC_UNIT_TESTED void lps22dfCalculate(int32_t *pressure, int32_t *temperature); -void lps22dfBusInit(const extDevice_t *dev) +static void lps22dfBusInit(const extDevice_t *dev) { #ifdef USE_BARO_SPI_LPS22DF if (dev->bus->busType == BUS_TYPE_SPI) { @@ -241,7 +241,7 @@ void lps22dfBusInit(const extDevice_t *dev) #endif } -void lps22dfBusDeinit(const extDevice_t *dev) +static void lps22dfBusDeinit(const extDevice_t *dev) { #ifdef USE_BARO_SPI_LPS22DF if (dev->bus->busType == BUS_TYPE_SPI) { diff --git a/src/main/drivers/barometer/barometer_ms5611.c b/src/main/drivers/barometer/barometer_ms5611.c index 3223cde2c2..c301e9fc5f 100644 --- a/src/main/drivers/barometer/barometer_ms5611.c +++ b/src/main/drivers/barometer/barometer_ms5611.c @@ -62,7 +62,7 @@ static uint8_t ms5611_osr = CMD_ADC_4096; #define MS5611_DATA_FRAME_SIZE 3 static DMA_DATA_ZERO_INIT uint8_t sensor_data[MS5611_DATA_FRAME_SIZE]; -void ms5611BusInit(const extDevice_t *dev) +static void ms5611BusInit(const extDevice_t *dev) { #ifdef USE_BARO_SPI_MS5611 if (dev->bus->busType == BUS_TYPE_SPI) { @@ -76,7 +76,7 @@ void ms5611BusInit(const extDevice_t *dev) #endif } -void ms5611BusDeinit(const extDevice_t *dev) +static void ms5611BusDeinit(const extDevice_t *dev) { #ifdef USE_BARO_SPI_MS5611 if (dev->bus->busType == BUS_TYPE_SPI) { diff --git a/src/main/drivers/barometer/barometer_qmp6988.c b/src/main/drivers/barometer/barometer_qmp6988.c index 5887d8462f..6369891185 100644 --- a/src/main/drivers/barometer/barometer_qmp6988.c +++ b/src/main/drivers/barometer/barometer_qmp6988.c @@ -105,7 +105,7 @@ static bool qmp6988GetUP(baroDev_t *baro); STATIC_UNIT_TESTED void qmp6988Calculate(int32_t *pressure, int32_t *temperature); -void qmp6988BusInit(const extDevice_t *dev) +static void qmp6988BusInit(const extDevice_t *dev) { #ifdef USE_BARO_SPI_QMP6988 if (dev->bus->busType == BUS_TYPE_SPI) { @@ -119,7 +119,7 @@ void qmp6988BusInit(const extDevice_t *dev) #endif } -void qmp6988BusDeinit(const extDevice_t *dev) +static void qmp6988BusDeinit(const extDevice_t *dev) { #ifdef USE_BARO_SPI_QMP6988 if (dev->bus->busType == BUS_TYPE_SPI) { diff --git a/src/main/drivers/bus_i2c_busdev.c b/src/main/drivers/bus_i2c_busdev.c index 720a898ac9..c2e7e9d74a 100644 --- a/src/main/drivers/bus_i2c_busdev.c +++ b/src/main/drivers/bus_i2c_busdev.c @@ -28,6 +28,7 @@ #include "drivers/bus.h" #include "drivers/bus_i2c.h" +#include "drivers/bus_i2c_busdev.h" static uint8_t i2cRegisteredDeviceCount = 0; diff --git a/src/main/drivers/bus_i2c_busdev.h b/src/main/drivers/bus_i2c_busdev.h index 1f2149ff70..4d3d638c70 100644 --- a/src/main/drivers/bus_i2c_busdev.h +++ b/src/main/drivers/bus_i2c_busdev.h @@ -27,5 +27,5 @@ uint8_t i2cBusReadRegister(const extDevice_t *dev, uint8_t reg); bool i2cBusReadRegisterBufferStart(const extDevice_t *dev, uint8_t reg, uint8_t *data, uint8_t length); bool i2cBusBusy(const extDevice_t *dev, bool *error); // Associate a device with an I2C bus -bool i2cBusSetInstance(const extDevice_t *dev, uint32_t device); +bool i2cBusSetInstance(extDevice_t *dev, uint32_t device); void i2cBusDeviceRegister(const extDevice_t *dev); diff --git a/src/main/drivers/bus_i2c_timing.c b/src/main/drivers/bus_i2c_timing.c index ed3b959cac..f196fd385f 100644 --- a/src/main/drivers/bus_i2c_timing.c +++ b/src/main/drivers/bus_i2c_timing.c @@ -22,6 +22,8 @@ #include "platform.h" +#include "bus_i2c_timing.h" + /* * Compute SCLDEL, SDADEL, SCLH and SCLL for TIMINGR register according to reference manuals. */ diff --git a/src/main/drivers/bus_spi.h b/src/main/drivers/bus_spi.h index b355cbaab3..5723b6202c 100644 --- a/src/main/drivers/bus_spi.h +++ b/src/main/drivers/bus_spi.h @@ -68,7 +68,7 @@ void spiPreinit(void); bool spiInit(SPIDevice device); // Called after all devices are initialised to enable SPI DMA where streams are available. -void spiInitBusDMA(); +void spiInitBusDMA(void); SPIDevice spiDeviceByInstance(const SPI_TypeDef *instance); SPI_TypeDef *spiInstanceByDevice(SPIDevice device); diff --git a/src/main/drivers/bus_spi_config.c b/src/main/drivers/bus_spi_config.c index d27605dcca..0fd6999dbe 100644 --- a/src/main/drivers/bus_spi_config.c +++ b/src/main/drivers/bus_spi_config.c @@ -25,6 +25,7 @@ #ifdef USE_SPI +#include "drivers/bus_spi.h" #include "drivers/io.h" #include "drivers/resource.h" #include "drivers/system.h" diff --git a/src/main/drivers/compass/compass_ak8963.c b/src/main/drivers/compass/compass_ak8963.c index e744deb276..14796f9c0b 100644 --- a/src/main/drivers/compass/compass_ak8963.c +++ b/src/main/drivers/compass/compass_ak8963.c @@ -372,7 +372,7 @@ static bool ak8963Init(magDev_t *mag) return true; } -void ak8963BusInit(const extDevice_t *dev) +static void ak8963BusInit(const extDevice_t *dev) { switch (dev->bus->busType) { #ifdef USE_MAG_AK8963 @@ -409,7 +409,7 @@ void ak8963BusInit(const extDevice_t *dev) } } -void ak8963BusDeInit(const extDevice_t *dev) +static void ak8963BusDeInit(const extDevice_t *dev) { switch (dev->bus->busType) { #ifdef USE_MAG_AK8963 diff --git a/src/main/drivers/compass/compass_lis2mdl.c b/src/main/drivers/compass/compass_lis2mdl.c index 80fb4b87ea..f270b3ca29 100644 --- a/src/main/drivers/compass/compass_lis2mdl.c +++ b/src/main/drivers/compass/compass_lis2mdl.c @@ -35,6 +35,8 @@ #include "drivers/time.h" #include "common/axis.h" +#include "compass_lis2mdl.h" + #define LIS2MDL_MAG_I2C_ADDRESS 0x1E // LIS2MDL Registers diff --git a/src/main/drivers/compass/compass_lis3mdl.c b/src/main/drivers/compass/compass_lis3mdl.c index 530275c40f..ec67056e21 100644 --- a/src/main/drivers/compass/compass_lis3mdl.c +++ b/src/main/drivers/compass/compass_lis3mdl.c @@ -31,6 +31,8 @@ #include "drivers/time.h" #include "common/axis.h" +#include "compass_lis3mdl.h" + #define LIS3MDL_MAG_I2C_ADDRESS 0x1E #define LIS3MDL_DEVICE_ID 0x3D diff --git a/src/main/drivers/dshot.c b/src/main/drivers/dshot.c index d433240539..54bfe2a4ed 100644 --- a/src/main/drivers/dshot.c +++ b/src/main/drivers/dshot.c @@ -29,6 +29,8 @@ #include "platform.h" +#include "dshot.h" + #ifdef USE_DSHOT #include "build/debug.h" @@ -50,8 +52,6 @@ #include "rx/rx.h" -#include "dshot.h" - #define ERPM_PER_LSB 100.0f FAST_DATA_ZERO_INIT uint8_t dshotMotorCount = 0; diff --git a/src/main/drivers/dshot_bitbang.h b/src/main/drivers/dshot_bitbang.h index b791240815..115d3de906 100644 --- a/src/main/drivers/dshot_bitbang.h +++ b/src/main/drivers/dshot_bitbang.h @@ -39,6 +39,6 @@ typedef enum { } dshotBitbangStatus_e; bool dshotBitbangDevInit(motorDevice_t *device, const motorDevConfig_t *motorConfig); -dshotBitbangStatus_e dshotBitbangGetStatus(); +dshotBitbangStatus_e dshotBitbangGetStatus(void); const timerHardware_t *dshotBitbangTimerGetAllocatedByNumberAndChannel(int8_t timerNumber, uint16_t timerChannel); const resourceOwner_t *dshotBitbangTimerGetOwner(const timerHardware_t *timer); diff --git a/src/main/drivers/flash/flash.c b/src/main/drivers/flash/flash.c index 8e48f07a92..a91cfd19dc 100644 --- a/src/main/drivers/flash/flash.c +++ b/src/main/drivers/flash/flash.c @@ -360,7 +360,7 @@ void flashPreinit(const flashConfig_t *flashConfig) ioPreinitByTag(flashConfig->csTag, IOCFG_IPU, PREINIT_PIN_STATE_HIGH); } -bool flashDeviceInit(const flashConfig_t *flashConfig) +static bool flashDeviceInit(const flashConfig_t *flashConfig) { bool haveFlash = false; diff --git a/src/main/drivers/flash/flash_m25p16.c b/src/main/drivers/flash/flash_m25p16.c index 8194ffd47e..1fcc66197e 100644 --- a/src/main/drivers/flash/flash_m25p16.c +++ b/src/main/drivers/flash/flash_m25p16.c @@ -248,7 +248,7 @@ bool m25p16_identify(flashDevice_t *fdevice, uint32_t jedecID) return true; } -void m25p16_configure(flashDevice_t *fdevice, uint32_t configurationFlags) +static void m25p16_configure(flashDevice_t *fdevice, uint32_t configurationFlags) { if (configurationFlags & FLASH_CF_SYSTEM_IS_MEMORY_MAPPED) { return; @@ -289,7 +289,7 @@ static void m25p16_setCommandAddress(uint8_t *buf, uint32_t address, bool useLon // Called in ISR context // A write enable has just been issued -busStatus_e m25p16_callbackWriteEnable(uint32_t arg) +static busStatus_e m25p16_callbackWriteEnable(uint32_t arg) { flashDevice_t *fdevice = (flashDevice_t *)arg; @@ -301,7 +301,7 @@ busStatus_e m25p16_callbackWriteEnable(uint32_t arg) // Called in ISR context // Write operation has just completed -busStatus_e m25p16_callbackWriteComplete(uint32_t arg) +static busStatus_e m25p16_callbackWriteComplete(uint32_t arg) { flashDevice_t *fdevice = (flashDevice_t *)arg; @@ -317,7 +317,7 @@ busStatus_e m25p16_callbackWriteComplete(uint32_t arg) // Called in ISR context // Check if the status was busy and if so repeat the poll -busStatus_e m25p16_callbackReady(uint32_t arg) +static busStatus_e m25p16_callbackReady(uint32_t arg) { flashDevice_t *fdevice = (flashDevice_t *)arg; extDevice_t *dev = fdevice->io.handle.dev; diff --git a/src/main/drivers/flash/flash_w25m.c b/src/main/drivers/flash/flash_w25m.c index d0024e050f..4b6b8ea786 100644 --- a/src/main/drivers/flash/flash_w25m.c +++ b/src/main/drivers/flash/flash_w25m.c @@ -171,7 +171,7 @@ bool w25m_identify(flashDevice_t *fdevice, uint32_t jedecID) return true; } -void w25m_configure(flashDevice_t *fdevice, uint32_t configurationFlags) +static void w25m_configure(flashDevice_t *fdevice, uint32_t configurationFlags) { for (int dieNumber = 0 ; dieNumber < dieCount ; dieNumber++) { w25m_dieSelect(fdevice->io.handle.dev, dieNumber); @@ -179,7 +179,7 @@ void w25m_configure(flashDevice_t *fdevice, uint32_t configurationFlags) } } -void w25m_eraseSector(flashDevice_t *fdevice, uint32_t address) +static void w25m_eraseSector(flashDevice_t *fdevice, uint32_t address) { int dieNumber = address / dieSize; @@ -188,7 +188,7 @@ void w25m_eraseSector(flashDevice_t *fdevice, uint32_t address) dieDevice[dieNumber].vTable->eraseSector(&dieDevice[dieNumber], address % dieSize); } -void w25m_eraseCompletely(flashDevice_t *fdevice) +static void w25m_eraseCompletely(flashDevice_t *fdevice) { for (int dieNumber = 0 ; dieNumber < dieCount ; dieNumber++) { w25m_dieSelect(fdevice->io.handle.dev, dieNumber); @@ -199,7 +199,7 @@ void w25m_eraseCompletely(flashDevice_t *fdevice) static uint32_t currentWriteAddress; static int currentWriteDie; -void w25m_pageProgramBegin(flashDevice_t *fdevice, uint32_t address, void (*callback)(uint32_t length)) +static void w25m_pageProgramBegin(flashDevice_t *fdevice, uint32_t address, void (*callback)(uint32_t length)) { currentWriteDie = address / dieSize; w25m_dieSelect(fdevice->io.handle.dev, currentWriteDie); @@ -207,21 +207,21 @@ void w25m_pageProgramBegin(flashDevice_t *fdevice, uint32_t address, void (*call dieDevice[currentWriteDie].vTable->pageProgramBegin(&dieDevice[currentWriteDie], address, callback); } -uint32_t w25m_pageProgramContinue(flashDevice_t *fdevice, uint8_t const **buffers, const uint32_t *bufferSizes, uint32_t bufferCount) +static uint32_t w25m_pageProgramContinue(flashDevice_t *fdevice, uint8_t const **buffers, const uint32_t *bufferSizes, uint32_t bufferCount) { UNUSED(fdevice); return dieDevice[currentWriteDie].vTable->pageProgramContinue(&dieDevice[currentWriteDie], buffers, bufferSizes, bufferCount); } -void w25m_pageProgramFinish(flashDevice_t *fdevice) +static void w25m_pageProgramFinish(flashDevice_t *fdevice) { UNUSED(fdevice); dieDevice[currentWriteDie].vTable->pageProgramFinish(&dieDevice[currentWriteDie]); } -void w25m_pageProgram(flashDevice_t *fdevice, uint32_t address, const uint8_t *data, uint32_t length, void (*callback)(uint32_t length)) +static void w25m_pageProgram(flashDevice_t *fdevice, uint32_t address, const uint8_t *data, uint32_t length, void (*callback)(uint32_t length)) { w25m_pageProgramBegin(fdevice, address, callback); @@ -230,7 +230,7 @@ void w25m_pageProgram(flashDevice_t *fdevice, uint32_t address, const uint8_t *d w25m_pageProgramFinish(fdevice); } -int w25m_readBytes(flashDevice_t *fdevice, uint32_t address, uint8_t *buffer, uint32_t length) +static int w25m_readBytes(flashDevice_t *fdevice, uint32_t address, uint8_t *buffer, uint32_t length) { int rlen; // remaining length int tlen; // transfer length for a round @@ -258,7 +258,7 @@ int w25m_readBytes(flashDevice_t *fdevice, uint32_t address, uint8_t *buffer, ui return length; } -const flashGeometry_t* w25m_getGeometry(flashDevice_t *fdevice) +static const flashGeometry_t* w25m_getGeometry(flashDevice_t *fdevice) { return &fdevice->geometry; } diff --git a/src/main/drivers/flash/flash_w25n.c b/src/main/drivers/flash/flash_w25n.c index f91c87d70d..685b8fb66f 100644 --- a/src/main/drivers/flash/flash_w25n.c +++ b/src/main/drivers/flash/flash_w25n.c @@ -288,7 +288,7 @@ static void w25n_deviceReset(flashDevice_t *fdevice) w25n_writeRegister(io, W25N_CONF_REG, W25N_CONFIG_ECC_ENABLE|W25N_CONFIG_BUFFER_READ_MODE); } -bool w25n_isReady(flashDevice_t *fdevice) +static bool w25n_isReady(flashDevice_t *fdevice) { // If we're waiting on DMA completion, then SPI is busy if (fdevice->io.mode == FLASHIO_SPI) { @@ -372,7 +372,7 @@ bool w25n_identify(flashDevice_t *fdevice, uint32_t jedecID) static void w25n_deviceInit(flashDevice_t *flashdev); -void w25n_configure(flashDevice_t *fdevice, uint32_t configurationFlags) +static void w25n_configure(flashDevice_t *fdevice, uint32_t configurationFlags) { if (configurationFlags & FLASH_CF_SYSTEM_IS_MEMORY_MAPPED) { return; @@ -404,7 +404,7 @@ void w25n_configure(flashDevice_t *fdevice, uint32_t configurationFlags) /** * Erase a sector full of bytes to all 1's at the given byte offset in the flash chip. */ -void w25n_eraseSector(flashDevice_t *fdevice, uint32_t address) +static void w25n_eraseSector(flashDevice_t *fdevice, uint32_t address) { w25n_waitForReady(fdevice); @@ -420,7 +420,7 @@ void w25n_eraseSector(flashDevice_t *fdevice, uint32_t address) // W25N01G does not support full chip erase. // Call eraseSector repeatedly. -void w25n_eraseCompletely(flashDevice_t *fdevice) +static void w25n_eraseCompletely(flashDevice_t *fdevice) { for (uint32_t block = 0; block < fdevice->geometry.sectors; block++) { w25n_eraseSector(fdevice, W25N_BLOCK_TO_LINEAR(block)); @@ -537,7 +537,7 @@ bool bufferDirty = false; // Called in ISR context // Check if the status was busy and if so repeat the poll -busStatus_e w25n_callbackReady(uint32_t arg) +static busStatus_e w25n_callbackReady(uint32_t arg) { flashDevice_t *fdevice = (flashDevice_t *)arg; extDevice_t *dev = fdevice->io.handle.dev; @@ -557,7 +557,7 @@ busStatus_e w25n_callbackReady(uint32_t arg) #ifdef USE_QUADSPI bool isProgramming = false; -void w25n_pageProgramBegin(flashDevice_t *fdevice, uint32_t address, void (*callback)(uint32_t length)) +static void w25n_pageProgramBegin(flashDevice_t *fdevice, uint32_t address, void (*callback)(uint32_t length)) { fdevice->callback = callback; @@ -579,7 +579,7 @@ void w25n_pageProgramBegin(flashDevice_t *fdevice, uint32_t address, void (*call } } -uint32_t w25n_pageProgramContinue(flashDevice_t *fdevice, uint8_t const **buffers, const uint32_t *bufferSizes, uint32_t bufferCount) +static uint32_t w25n_pageProgramContinue(flashDevice_t *fdevice, uint8_t const **buffers, const uint32_t *bufferSizes, uint32_t bufferCount) { if (bufferCount < 1) { fdevice->callback(0); @@ -612,7 +612,7 @@ uint32_t w25n_pageProgramContinue(flashDevice_t *fdevice, uint8_t const **buffer static uint32_t currentPage = UINT32_MAX; -void w25n_pageProgramFinish(flashDevice_t *fdevice) +static void w25n_pageProgramFinish(flashDevice_t *fdevice) { if (bufferDirty && W25N_LINEAR_TO_COLUMN(programLoadAddress) == 0) { @@ -627,7 +627,7 @@ void w25n_pageProgramFinish(flashDevice_t *fdevice) } } #else -void w25n_pageProgramBegin(flashDevice_t *fdevice, uint32_t address, void (*callback)(uint32_t length)) +static void w25n_pageProgramBegin(flashDevice_t *fdevice, uint32_t address, void (*callback)(uint32_t length)) { fdevice->callback = callback; fdevice->currentWriteAddress = address; @@ -638,7 +638,7 @@ static uint32_t currentPage = UINT32_MAX; // Called in ISR context // A write enable has just been issued -busStatus_e w25n_callbackWriteEnable(uint32_t arg) +static busStatus_e w25n_callbackWriteEnable(uint32_t arg) { flashDevice_t *fdevice = (flashDevice_t *)arg; @@ -650,7 +650,7 @@ busStatus_e w25n_callbackWriteEnable(uint32_t arg) // Called in ISR context // Write operation has just completed -busStatus_e w25n_callbackWriteComplete(uint32_t arg) +static busStatus_e w25n_callbackWriteComplete(uint32_t arg) { flashDevice_t *fdevice = (flashDevice_t *)arg; @@ -663,7 +663,7 @@ busStatus_e w25n_callbackWriteComplete(uint32_t arg) return BUS_READY; } -uint32_t w25n_pageProgramContinue(flashDevice_t *fdevice, uint8_t const **buffers, const uint32_t *bufferSizes, uint32_t bufferCount) +static uint32_t w25n_pageProgramContinue(flashDevice_t *fdevice, uint8_t const **buffers, const uint32_t *bufferSizes, uint32_t bufferCount) { if (bufferCount < 1) { fdevice->callback(0); @@ -771,7 +771,7 @@ uint32_t w25n_pageProgramContinue(flashDevice_t *fdevice, uint8_t const **buffer return fdevice->callbackArg; } -void w25n_pageProgramFinish(flashDevice_t *fdevice) +static void w25n_pageProgramFinish(flashDevice_t *fdevice) { UNUSED(fdevice); } @@ -793,14 +793,14 @@ void w25n_pageProgramFinish(flashDevice_t *fdevice) * break this operation up into one beginProgram call, one or more continueProgram calls, and one finishProgram call. */ -void w25n_pageProgram(flashDevice_t *fdevice, uint32_t address, const uint8_t *data, uint32_t length, void (*callback)(uint32_t length)) +static void w25n_pageProgram(flashDevice_t *fdevice, uint32_t address, const uint8_t *data, uint32_t length, void (*callback)(uint32_t length)) { w25n_pageProgramBegin(fdevice, address, callback); w25n_pageProgramContinue(fdevice, &data, &length, 1); w25n_pageProgramFinish(fdevice); } -void w25n_flush(flashDevice_t *fdevice) +static void w25n_flush(flashDevice_t *fdevice) { if (bufferDirty) { currentPage = W25N_LINEAR_TO_PAGE(programStartAddress); // reset page to the page being written @@ -811,7 +811,7 @@ void w25n_flush(flashDevice_t *fdevice) } } -void w25n_addError(uint32_t address, uint8_t code) +static void w25n_addError(uint32_t address, uint8_t code) { UNUSED(address); UNUSED(code); @@ -837,7 +837,7 @@ void w25n_addError(uint32_t address, uint8_t code) // (3) Issue READ_DATA on column address. // (4) Return transferLength. -int w25n_readBytes(flashDevice_t *fdevice, uint32_t address, uint8_t *buffer, uint32_t length) +static int w25n_readBytes(flashDevice_t *fdevice, uint32_t address, uint8_t *buffer, uint32_t length) { uint32_t targetPage = W25N_LINEAR_TO_PAGE(address); @@ -928,7 +928,7 @@ int w25n_readBytes(flashDevice_t *fdevice, uint32_t address, uint8_t *buffer, ui return transferLength; } -int w25n_readExtensionBytes(flashDevice_t *fdevice, uint32_t address, uint8_t *buffer, int length) +LOCAL_UNUSED_FUNCTION static int w25n_readExtensionBytes(flashDevice_t *fdevice, uint32_t address, uint8_t *buffer, int length) { if (!w25n_waitForReady(fdevice)) { @@ -981,7 +981,7 @@ int w25n_readExtensionBytes(flashDevice_t *fdevice, uint32_t address, uint8_t *b * * Can be called before calling w25n_init() (the result would have totalSize = 0). */ -const flashGeometry_t* w25n_getGeometry(flashDevice_t *fdevice) +static const flashGeometry_t* w25n_getGeometry(flashDevice_t *fdevice) { return &fdevice->geometry; } @@ -1010,7 +1010,7 @@ typedef volatile struct cb_context_s { // Called in ISR context // Read of BBLUT entry has just completed -busStatus_e w25n_readBBLUTCallback(uint32_t arg) +static busStatus_e w25n_readBBLUTCallback(uint32_t arg) { cb_context_t *cb_context = (cb_context_t *)arg; flashDevice_t *fdevice = cb_context->fdevice; @@ -1027,7 +1027,7 @@ busStatus_e w25n_readBBLUTCallback(uint32_t arg) return BUS_READY; // All done } -void w25n_readBBLUT(flashDevice_t *fdevice, bblut_t *bblut, int lutsize) +LOCAL_UNUSED_FUNCTION static void w25n_readBBLUT(flashDevice_t *fdevice, bblut_t *bblut, int lutsize) { cb_context_t cb_context; uint8_t in[4]; @@ -1078,7 +1078,7 @@ void w25n_readBBLUT(flashDevice_t *fdevice, bblut_t *bblut, int lutsize) #endif } -void w25n_writeBBLUT(flashDevice_t *fdevice, uint16_t lba, uint16_t pba) +LOCAL_UNUSED_FUNCTION static void w25n_writeBBLUT(flashDevice_t *fdevice, uint16_t lba, uint16_t pba) { w25n_waitForReady(fdevice); diff --git a/src/main/drivers/flash/flash_w25q128fv.c b/src/main/drivers/flash/flash_w25q128fv.c index 4205c5a8de..59e282003e 100644 --- a/src/main/drivers/flash/flash_w25q128fv.c +++ b/src/main/drivers/flash/flash_w25q128fv.c @@ -228,7 +228,7 @@ static void w25q128fv_deviceReset(flashDevice_t *fdevice) #endif } -MMFLASH_CODE bool w25q128fv_isReady(flashDevice_t *fdevice) +static MMFLASH_CODE bool w25q128fv_isReady(flashDevice_t *fdevice) { uint8_t status = w25q128fv_readRegister(&fdevice->io, W25Q128FV_INSTRUCTION_READ_STATUS1_REG); @@ -246,7 +246,7 @@ MMFLASH_CODE static bool w25q128fv_isWritable(flashDevice_t *fdevice) return writable; } -MMFLASH_CODE bool w25q128fv_hasTimedOut(flashDevice_t *fdevice) +static MMFLASH_CODE bool w25q128fv_hasTimedOut(flashDevice_t *fdevice) { uint32_t nowMs = microsISR() / 1000; if (cmp32(nowMs, fdevice->timeoutAt) >= 0) { @@ -335,7 +335,7 @@ MMFLASH_CODE_NOINLINE bool w25q128fv_identify(flashDevice_t *fdevice, uint32_t j return true; } -void w25q128fv_configure(flashDevice_t *fdevice, uint32_t configurationFlags) +static void w25q128fv_configure(flashDevice_t *fdevice, uint32_t configurationFlags) { if (configurationFlags & FLASH_CF_SYSTEM_IS_MEMORY_MAPPED) { return; @@ -437,7 +437,7 @@ MMFLASH_CODE static void w25q128fv_pageProgram(flashDevice_t *fdevice, uint32_t w25q128fv_pageProgramFinish(fdevice); } -MMFLASH_CODE void w25q128fv_flush(flashDevice_t *fdevice) +static MMFLASH_CODE void w25q128fv_flush(flashDevice_t *fdevice) { UNUSED(fdevice); } @@ -473,7 +473,7 @@ MMFLASH_CODE static int w25q128fv_readBytes(flashDevice_t *fdevice, uint32_t add return length; } -const flashGeometry_t* w25q128fv_getGeometry(flashDevice_t *fdevice) +static const flashGeometry_t* w25q128fv_getGeometry(flashDevice_t *fdevice) { return &fdevice->geometry; } diff --git a/src/main/drivers/io.c b/src/main/drivers/io.c index 128d0afe69..7c8dc12203 100644 --- a/src/main/drivers/io.c +++ b/src/main/drivers/io.c @@ -48,10 +48,12 @@ uint16_t IO_Pin(IO_t io) return ioRec->pin; } +#if defined(STM32F4) || defined(APM32F4) int IO_EXTI_PortSourceGPIO(IO_t io) { return IO_GPIOPortIdx(io); } +#endif int IO_GPIO_PortSource(IO_t io) { @@ -67,10 +69,12 @@ int IO_GPIOPinIdx(IO_t io) return 31 - __builtin_clz(IO_Pin(io)); } +#if defined(STM32F4) || defined(APM32F4) int IO_EXTI_PinSource(IO_t io) { return IO_GPIOPinIdx(io); } +#endif int IO_GPIO_PinSource(IO_t io) { diff --git a/src/main/drivers/light_led.c b/src/main/drivers/light_led.c index 6c15b34dcf..e0be78bd97 100644 --- a/src/main/drivers/light_led.c +++ b/src/main/drivers/light_led.c @@ -23,10 +23,12 @@ #include "pg/pg_ids.h" #include "drivers/io.h" -#include "io_impl.h" +#include "drivers/io_impl.h" #include "light_led.h" +#if !(defined(UNIT_TEST) || defined(USE_VIRTUAL_LED)) + PG_REGISTER_WITH_RESET_FN(statusLedConfig_t, statusLedConfig, PG_STATUS_LED_CONFIG, 0); static IO_t leds[STATUS_LED_NUMBER]; @@ -91,3 +93,4 @@ void ledSet(int led, bool on) const bool inverted = (1 << (led)) & ledInversion; IOWrite(leds[led], on ? inverted : !inverted); } +#endif diff --git a/src/main/drivers/light_led.h b/src/main/drivers/light_led.h index 13834f93a4..0543f0478d 100644 --- a/src/main/drivers/light_led.h +++ b/src/main/drivers/light_led.h @@ -31,8 +31,6 @@ typedef struct statusLedConfig_s { uint8_t inversion; } statusLedConfig_t; -PG_DECLARE(statusLedConfig_t, statusLedConfig); - // Helpful macros #if defined(UNIT_TEST) || defined(USE_VIRTUAL_LED) @@ -50,6 +48,8 @@ PG_DECLARE(statusLedConfig_t, statusLedConfig); #else +PG_DECLARE(statusLedConfig_t, statusLedConfig); + #define LED0_TOGGLE ledToggle(0) #define LED0_OFF ledSet(0, false) #define LED0_ON ledSet(0, true) diff --git a/src/main/drivers/max7456.c b/src/main/drivers/max7456.c index 42341a4ff1..f5963daae6 100644 --- a/src/main/drivers/max7456.c +++ b/src/main/drivers/max7456.c @@ -281,7 +281,7 @@ static void max7456ClearLayer(displayPortLayer_e layer) memset(getLayerBuffer(layer), 0x20, VIDEO_BUFFER_CHARS_PAL); } -void max7456ReInit(void) +static void max7456ReInit(void) { uint8_t srdata = 0; @@ -612,7 +612,7 @@ bool max7456ReInitIfRequired(bool forceStallCheck) } // Called in ISR context -busStatus_e max7456_callbackReady(uint32_t arg) +static busStatus_e max7456_callbackReady(uint32_t arg) { UNUSED(arg); diff --git a/src/main/drivers/pin_pull_up_down.h b/src/main/drivers/pin_pull_up_down.h index 36a458c5db..c259a11c60 100644 --- a/src/main/drivers/pin_pull_up_down.h +++ b/src/main/drivers/pin_pull_up_down.h @@ -28,4 +28,4 @@ struct pinPullUpDownConfig_s; -void pinPullupPulldownInit(); +void pinPullupPulldownInit(void); diff --git a/src/main/drivers/rangefinder/rangefinder_hcsr04.c b/src/main/drivers/rangefinder/rangefinder_hcsr04.c index a8192c08ca..72d3e201b8 100644 --- a/src/main/drivers/rangefinder/rangefinder_hcsr04.c +++ b/src/main/drivers/rangefinder/rangefinder_hcsr04.c @@ -61,7 +61,7 @@ static IO_t echoIO; static IO_t triggerIO; #if !defined(UNIT_TEST) -void hcsr04_extiHandler(extiCallbackRec_t* cb) +static void hcsr04_extiHandler(extiCallbackRec_t* cb) { UNUSED(cb); @@ -81,7 +81,7 @@ void hcsr04_extiHandler(extiCallbackRec_t* cb) } #endif -void hcsr04_init(rangefinderDev_t *dev) +static void hcsr04_init(rangefinderDev_t *dev) { UNUSED(dev); } @@ -93,7 +93,7 @@ void hcsr04_init(rangefinderDev_t *dev) * Called periodically by the scheduler * Measurement reading is done asynchronously, using interrupt */ -void hcsr04_start_reading(void) +static void hcsr04_start_reading(void) { #if !defined(UNIT_TEST) IOHi(triggerIO); @@ -102,7 +102,7 @@ void hcsr04_start_reading(void) #endif } -void hcsr04_update(rangefinderDev_t *dev) +static void hcsr04_update(rangefinderDev_t *dev) { UNUSED(dev); @@ -136,7 +136,7 @@ void hcsr04_update(rangefinderDev_t *dev) /** * Get the distance that was measured by the last pulse, in centimeters. */ -int32_t hcsr04_get_distance(rangefinderDev_t *dev) +static int32_t hcsr04_get_distance(rangefinderDev_t *dev) { UNUSED(dev); diff --git a/src/main/drivers/rangefinder/rangefinder_lidarmt.c b/src/main/drivers/rangefinder/rangefinder_lidarmt.c index 8204547d1a..bf9e57dad5 100644 --- a/src/main/drivers/rangefinder/rangefinder_lidarmt.c +++ b/src/main/drivers/rangefinder/rangefinder_lidarmt.c @@ -115,7 +115,7 @@ const MTRangefinderConfig* getMTRangefinderDeviceConf(rangefinderType_e mtRangef return NULL; } -const mtRangefinderData_t * getMTRangefinderData(void) { +static const mtRangefinderData_t * getMTRangefinderData(void) { return &rfSensorData; } diff --git a/src/main/drivers/rangefinder/rangefinder_lidartf.c b/src/main/drivers/rangefinder/rangefinder_lidartf.c index 76e97d052b..07d0c330ed 100644 --- a/src/main/drivers/rangefinder/rangefinder_lidartf.c +++ b/src/main/drivers/rangefinder/rangefinder_lidartf.c @@ -128,7 +128,7 @@ static void lidarTFSendCommand(void) } } -void lidarTFInit(rangefinderDev_t *dev) +static void lidarTFInit(rangefinderDev_t *dev) { UNUSED(dev); @@ -136,7 +136,7 @@ void lidarTFInit(rangefinderDev_t *dev) tfReceivePosition = 0; } -void lidarTFUpdate(rangefinderDev_t *dev) +static void lidarTFUpdate(rangefinderDev_t *dev) { UNUSED(dev); static timeMs_t lastFrameReceivedMs = 0; @@ -232,7 +232,7 @@ void lidarTFUpdate(rangefinderDev_t *dev) // Return most recent device output in cm -int32_t lidarTFGetDistance(rangefinderDev_t *dev) +static int32_t lidarTFGetDistance(rangefinderDev_t *dev) { UNUSED(dev); diff --git a/src/main/drivers/rx/rx_cc2500.c b/src/main/drivers/rx/rx_cc2500.c index 487b2eb780..db3b6e14b0 100644 --- a/src/main/drivers/rx/rx_cc2500.c +++ b/src/main/drivers/rx/rx_cc2500.c @@ -48,12 +48,12 @@ void cc2500ReadFifo(uint8_t *dpbuffer, uint8_t len) rxSpiReadCommandMulti(CC2500_3F_RXFIFO | CC2500_READ_BURST, NOP, dpbuffer, len); } -void cc2500WriteCommand(uint8_t command, uint8_t data) +static void cc2500WriteCommand(uint8_t command, uint8_t data) { rxSpiWriteCommand(command, data); } -void cc2500WriteCommandMulti(uint8_t command, const uint8_t *data, uint8_t length) +static void cc2500WriteCommandMulti(uint8_t command, const uint8_t *data, uint8_t length) { rxSpiWriteCommandMulti(command, data, length); } diff --git a/src/main/drivers/rx/rx_pwm.c b/src/main/drivers/rx/rx_pwm.c index c42c7d3c67..5042c73445 100644 --- a/src/main/drivers/rx/rx_pwm.c +++ b/src/main/drivers/rx/rx_pwm.c @@ -125,12 +125,15 @@ void resetPPMDataReceivedState(void) #define MIN_CHANNELS_BEFORE_PPM_FRAME_CONSIDERED_VALID 4 -#ifdef DEBUG_PPM_ISR typedef enum { SOURCE_OVERFLOW = 0, SOURCE_EDGE = 1 } eventSource_e; +static void ppmISREvent(eventSource_e source, uint32_t capture); + +#ifdef DEBUG_PPM_ISR + typedef struct ppmISREvent_s { uint32_t capture; eventSource_e source; @@ -139,7 +142,7 @@ typedef struct ppmISREvent_s { static ppmISREvent_t ppmEvents[20]; static uint8_t ppmEventIndex = 0; -void ppmISREvent(eventSource_e source, uint32_t capture) +static void ppmISREvent(eventSource_e source, uint32_t capture) { ppmEventIndex = (ppmEventIndex + 1) % ARRAYLEN(ppmEvents); @@ -147,7 +150,7 @@ void ppmISREvent(eventSource_e source, uint32_t capture) ppmEvents[ppmEventIndex].capture = capture; } #else -void ppmISREvent(eventSource_e source, uint32_t capture) {} +static void ppmISREvent(eventSource_e source, uint32_t capture) {} #endif static void ppmResetDevice(void) @@ -403,7 +406,7 @@ void pwmRxInit(const pwmConfig_t *pwmConfig) #define FIRST_PWM_PORT 0 #ifdef USE_PWM_OUTPUT -void ppmAvoidPWMTimerClash(TIM_TypeDef *pwmTimer) +static void ppmAvoidPWMTimerClash(TIM_TypeDef *pwmTimer) { pwmOutputPort_t *motors = pwmGetMotors(); for (int motorIndex = 0; motorIndex < MAX_SUPPORTED_MOTORS; motorIndex++) { diff --git a/src/main/drivers/rx/rx_spi.c b/src/main/drivers/rx/rx_spi.c index e21dd78fcd..05c6e803ea 100644 --- a/src/main/drivers/rx/rx_spi.c +++ b/src/main/drivers/rx/rx_spi.c @@ -75,7 +75,7 @@ void rxSpiDevicePreinit(const rxSpiConfig_t *rxSpiConfig) ioPreinitByTag(rxSpiConfig->csnTag, IOCFG_IPU, PREINIT_PIN_STATE_HIGH); } -void rxSpiExtiHandler(extiCallbackRec_t* callback) +static void rxSpiExtiHandler(extiCallbackRec_t* callback) { UNUSED(callback); diff --git a/src/main/drivers/rx/rx_spi.h b/src/main/drivers/rx/rx_spi.h index ab51a760cc..92e1ab0dcc 100644 --- a/src/main/drivers/rx/rx_spi.h +++ b/src/main/drivers/rx/rx_spi.h @@ -35,8 +35,8 @@ extDevice_t *rxSpiGetDevice(void); void rxSpiDevicePreinit(const struct rxSpiConfig_s *rxSpiConfig); bool rxSpiDeviceInit(const struct rxSpiConfig_s *rxSpiConfig); void rxSpiSetNormalSpeedMhz(uint32_t mhz); -void rxSpiNormalSpeed(); -void rxSpiStartupSpeed(); +void rxSpiNormalSpeed(void); +void rxSpiStartupSpeed(void); void rxSpiDmaEnable(bool enable); uint8_t rxSpiTransferByte(uint8_t data); void rxSpiWriteByte(uint8_t data); diff --git a/src/main/drivers/rx/rx_sx1280.c b/src/main/drivers/rx/rx_sx1280.c index 38d1ff1b6c..1e3c4b05f9 100644 --- a/src/main/drivers/rx/rx_sx1280.c +++ b/src/main/drivers/rx/rx_sx1280.c @@ -591,7 +591,7 @@ void sx1280GetLastPacketStats(int8_t *rssi, int8_t *snr) } } -void sx1280DoFHSS(void) +LOCAL_UNUSED_FUNCTION static void sx1280DoFHSS(void) { return; } diff --git a/src/main/drivers/rx/rx_sx1280.h b/src/main/drivers/rx/rx_sx1280.h index 11d38cd609..5dc496a374 100644 --- a/src/main/drivers/rx/rx_sx1280.h +++ b/src/main/drivers/rx/rx_sx1280.h @@ -353,7 +353,7 @@ void sx1280SetDioIrqParams(const uint16_t irqMask, const uint16_t dio1Mask, cons void sx1280ClearIrqStatus(const uint16_t irqMask); void sx1280GetIrqReason(void); -void sx1280HandleFromTock(); +void sx1280HandleFromTock(void); void sx1280TransmitData(const uint8_t *data, const uint8_t length); void sx1280ReceiveData(uint8_t *data, const uint8_t length); diff --git a/src/main/drivers/sdcard_sdio_baremetal.c b/src/main/drivers/sdcard_sdio_baremetal.c index 3342e3bc14..772223cd30 100644 --- a/src/main/drivers/sdcard_sdio_baremetal.c +++ b/src/main/drivers/sdcard_sdio_baremetal.c @@ -48,7 +48,7 @@ uint8_t writeCache[512 * FATFS_BLOCK_CACHE_SIZE] __attribute__ ((aligned (4))); uint32_t cacheCount = 0; -void cache_write(uint8_t *buffer) +static void cache_write(uint8_t *buffer) { if (cacheCount == sizeof(writeCache)) { // Prevents overflow @@ -58,12 +58,12 @@ void cache_write(uint8_t *buffer) cacheCount += 512; } -uint16_t cache_getCount(void) +static uint16_t cache_getCount(void) { return (cacheCount / 512); } -void cache_reset(void) +static void cache_reset(void) { cacheCount = 0; } diff --git a/src/main/drivers/sdcard_spi.c b/src/main/drivers/sdcard_spi.c index 40c9a646b1..b09698df91 100644 --- a/src/main/drivers/sdcard_spi.c +++ b/src/main/drivers/sdcard_spi.c @@ -112,7 +112,7 @@ static void sdcard_reset(void) // Called in ISR context // Wait until idle indicated by a read value of SDCARD_IDLE_TOKEN -busStatus_e sdcard_callbackIdle(uint32_t arg) +static busStatus_e sdcard_callbackIdle(uint32_t arg) { sdcard_t *sdcard = (sdcard_t *)arg; extDevice_t *dev = &sdcard->dev; @@ -135,7 +135,7 @@ busStatus_e sdcard_callbackIdle(uint32_t arg) // Called in ISR context // Wait until idle is no longer indicated by a read value of SDCARD_IDLE_TOKEN -busStatus_e sdcard_callbackNotIdle(uint32_t arg) +static busStatus_e sdcard_callbackNotIdle(uint32_t arg) { sdcard_t *sdcard = (sdcard_t *)arg; extDevice_t *dev = &sdcard->dev; @@ -340,7 +340,7 @@ typedef enum { /// Called in ISR context // Wait until the arrival of the SDCARD_SINGLE_BLOCK_READ_START_TOKEN token -busStatus_e sdcard_callbackNotIdleDataBlock(uint32_t arg) +static busStatus_e sdcard_callbackNotIdleDataBlock(uint32_t arg) { sdcard_t *sdcard = (sdcard_t *)arg; extDevice_t *dev = &sdcard->dev; @@ -536,7 +536,7 @@ static bool sdcard_checkInitDone(void) return status == 0x00; } -void sdcardSpi_preinit(const sdcardConfig_t *config) +static void sdcardSpi_preinit(const sdcardConfig_t *config) { ioPreinitByTag(config->chipSelectTag, IOCFG_IPU, PREINIT_PIN_STATE_HIGH); } diff --git a/src/main/drivers/sdio.h b/src/main/drivers/sdio.h index cd60548123..2464e1594d 100644 --- a/src/main/drivers/sdio.h +++ b/src/main/drivers/sdio.h @@ -30,6 +30,6 @@ typedef enum { #define SDIODEV_COUNT 2 #if defined(STM32H7) -void sdioPinConfigure(); +void sdioPinConfigure(void); void SDIO_GPIO_Init(void); #endif diff --git a/src/main/drivers/serial.h b/src/main/drivers/serial.h index 1dc1a39146..f5f21bb74e 100644 --- a/src/main/drivers/serial.h +++ b/src/main/drivers/serial.h @@ -73,7 +73,7 @@ typedef enum { #define CTRL_LINE_STATE_RTS (1 << 1) typedef void (*serialReceiveCallbackPtr)(uint16_t data, void *rxCallbackData); // used by serial drivers to return frames to app -typedef void (*serialIdleCallbackPtr)(); +typedef void (*serialIdleCallbackPtr)(void); typedef struct serialPort_s { diff --git a/src/main/drivers/serial_impl.h b/src/main/drivers/serial_impl.h index 029eed4147..f9d8f03c3b 100644 --- a/src/main/drivers/serial_impl.h +++ b/src/main/drivers/serial_impl.h @@ -23,6 +23,9 @@ #include +#include "drivers/resource.h" +#include "io/serial.h" + /* * common functions related to serial port implementation */ diff --git a/src/main/drivers/serial_softserial.c b/src/main/drivers/serial_softserial.c index dbaf5d75e6..13fe8bb682 100644 --- a/src/main/drivers/serial_softserial.c +++ b/src/main/drivers/serial_softserial.c @@ -195,7 +195,7 @@ static void resetBuffers(softSerial_t *softSerial) softSerial->port.txBufferHead = 0; } -softSerial_t* softSerialFromIdentifier(serialPortIdentifier_e identifier) +static softSerial_t* softSerialFromIdentifier(serialPortIdentifier_e identifier) { if (identifier >= SERIAL_PORT_SOFTSERIAL_FIRST && identifier < SERIAL_PORT_SOFTSERIAL_FIRST + SERIAL_SOFTSERIAL_COUNT) { return &softSerialPorts[identifier - SERIAL_PORT_SOFTSERIAL_FIRST]; @@ -330,7 +330,7 @@ serialPort_t *softSerialOpen(serialPortIdentifier_e identifier, serialReceiveCal * Serial Engine */ -void processTxState(softSerial_t *softSerial) +static void processTxState(softSerial_t *softSerial) { if (!softSerial->isTransmittingData) { if (isSoftSerialTransmitBufferEmpty((serialPort_t *)softSerial)) { @@ -387,7 +387,7 @@ enum { LEADING }; -void applyChangedBits(softSerial_t *softSerial) +static void applyChangedBits(softSerial_t *softSerial) { if (softSerial->rxEdge == TRAILING) { for (unsigned bitToSet = softSerial->rxLastLeadingEdgeAtBitIndex; bitToSet < softSerial->rxBitIndex; bitToSet++) { @@ -396,7 +396,7 @@ void applyChangedBits(softSerial_t *softSerial) } } -void prepareForNextRxByte(softSerial_t *softSerial) +static void prepareForNextRxByte(softSerial_t *softSerial) { // prepare for next byte softSerial->rxBitIndex = 0; @@ -411,7 +411,7 @@ void prepareForNextRxByte(softSerial_t *softSerial) #define STOP_BIT_MASK (1 << 0) #define START_BIT_MASK (1 << (RX_TOTAL_BITS - 1)) -void extractAndStoreRxByte(softSerial_t *softSerial) +static void extractAndStoreRxByte(softSerial_t *softSerial) { if ((softSerial->port.mode & MODE_RX) == 0) { return; @@ -435,7 +435,7 @@ void extractAndStoreRxByte(softSerial_t *softSerial) } } -void processRxState(softSerial_t *softSerial) +static void processRxState(softSerial_t *softSerial) { if (softSerial->isSearchingForStartBit) { return; @@ -597,7 +597,7 @@ void softSerialSetBaudRate(serialPort_t *s, uint32_t baudRate) serialTimerConfigureTimebase(softSerial->timerHardware, baudRate); } -void softSerialSetMode(serialPort_t *instance, portMode_e mode) +static void softSerialSetMode(serialPort_t *instance, portMode_e mode) { instance->mode = mode; } diff --git a/src/main/drivers/serial_tcp.c b/src/main/drivers/serial_tcp.c index bc6f6d37ff..a922cc7674 100644 --- a/src/main/drivers/serial_tcp.c +++ b/src/main/drivers/serial_tcp.c @@ -158,7 +158,7 @@ serialPort_t *serTcpOpen(serialPortIdentifier_e identifier, serialReceiveCallbac return (serialPort_t *)s; } -uint32_t tcpTotalRxBytesWaiting(const serialPort_t *instance) +static uint32_t tcpTotalRxBytesWaiting(const serialPort_t *instance) { tcpPort_t *s = (tcpPort_t*)instance; uint32_t count; @@ -173,7 +173,7 @@ uint32_t tcpTotalRxBytesWaiting(const serialPort_t *instance) return count; } -uint32_t tcpTotalTxBytesFree(const serialPort_t *instance) +static uint32_t tcpTotalTxBytesFree(const serialPort_t *instance) { tcpPort_t *s = (tcpPort_t*)instance; uint32_t bytesUsed; @@ -190,7 +190,7 @@ uint32_t tcpTotalTxBytesFree(const serialPort_t *instance) return bytesFree; } -bool isTcpTransmitBufferEmpty(const serialPort_t *instance) +static bool isTcpTransmitBufferEmpty(const serialPort_t *instance) { tcpPort_t *s = (tcpPort_t *)instance; pthread_mutex_lock(&s->txLock); @@ -199,7 +199,7 @@ bool isTcpTransmitBufferEmpty(const serialPort_t *instance) return isEmpty; } -uint8_t tcpRead(serialPort_t *instance) +static uint8_t tcpRead(serialPort_t *instance) { uint8_t ch; tcpPort_t *s = (tcpPort_t *)instance; @@ -216,7 +216,7 @@ uint8_t tcpRead(serialPort_t *instance) return ch; } -void tcpWrite(serialPort_t *instance, uint8_t ch) +static void tcpWrite(serialPort_t *instance, uint8_t ch) { tcpPort_t *s = (tcpPort_t *)instance; pthread_mutex_lock(&s->txLock); diff --git a/src/main/drivers/vtx_rtc6705_soft_spi.c b/src/main/drivers/vtx_rtc6705_soft_spi.c index 6adc3606f9..d16ff2348d 100644 --- a/src/main/drivers/vtx_rtc6705_soft_spi.c +++ b/src/main/drivers/vtx_rtc6705_soft_spi.c @@ -31,6 +31,8 @@ #include "drivers/time.h" #include "drivers/vtx_rtc6705.h" +#include "vtx_rtc6705_soft_spi.h" + #define DP_5G_MASK 0x7000 #define PA5G_BS_MASK 0x0E00 #define PA5G_PW_MASK 0x0180 diff --git a/src/main/drivers/vtx_table.c b/src/main/drivers/vtx_table.c index 5e29e5a548..b97e93c59c 100644 --- a/src/main/drivers/vtx_table.c +++ b/src/main/drivers/vtx_table.c @@ -159,7 +159,7 @@ void vtxTableConfigClearChannels(vtxTableConfig_t *config, int band, int channel } // Clear a channel name for "channel" -void vtxTableConfigClearChannelNames(vtxTableConfig_t *config, int channel) +static void vtxTableConfigClearChannelNames(vtxTableConfig_t *config, int channel) { tfp_sprintf(config->channelNames[channel], "%d", channel + 1); } diff --git a/src/main/fc/board_info.c b/src/main/fc/board_info.c index 729b93d84a..f66ab3acca 100644 --- a/src/main/fc/board_info.c +++ b/src/main/fc/board_info.c @@ -25,6 +25,7 @@ #if defined(USE_BOARD_INFO) #include "pg/board.h" +#include "board_info.h" #if !defined(BOARD_NAME) static bool boardInformationSet = false; diff --git a/src/main/fc/board_info.h b/src/main/fc/board_info.h index b855d50c59..c7ec54fa27 100644 --- a/src/main/fc/board_info.h +++ b/src/main/fc/board_info.h @@ -22,16 +22,16 @@ void initBoardInformation(void); -char *getBoardName(void); -char *getManufacturerId(void); +const char *getBoardName(void); +const char *getManufacturerId(void); bool boardInformationIsSet(void); -bool setBoardName(char *newBoardName); -bool setManufacturerId(char *newManufacturerId); +bool setBoardName(const char *newBoardName); +bool setManufacturerId(const char *newManufacturerId); bool persistBoardInformation(void); -uint8_t * getSignature(void); +const uint8_t * getSignature(void); bool signatureIsSet(void); -bool setSignature(uint8_t *newSignature); +bool setSignature(const uint8_t *newSignature); bool persistSignature(void); diff --git a/src/main/fc/core.c b/src/main/fc/core.c index 75bd3100d0..fc123e52a5 100644 --- a/src/main/fc/core.c +++ b/src/main/fc/core.c @@ -197,7 +197,7 @@ static bool isCalibrating(void) } #ifdef USE_LAUNCH_CONTROL -bool canUseLaunchControl(void) +static bool canUseLaunchControl(void) { if (!isFixedWing() && !isUsingSticksForArming() // require switch arming for safety @@ -212,7 +212,7 @@ bool canUseLaunchControl(void) #endif #ifdef USE_DSHOT -void setMotorSpinDirection(uint8_t spinDirection) +static void setMotorSpinDirection(uint8_t spinDirection) { if (isMotorProtocolDshot() && !featureIsEnabled(FEATURE_3D)) { dshotCommandWrite(ALL_MOTORS, getMotorCount(), spinDirection, DSHOT_CMD_TYPE_INLINE); diff --git a/src/main/fc/core.h b/src/main/fc/core.h index a7aefac35a..45988459e1 100644 --- a/src/main/fc/core.h +++ b/src/main/fc/core.h @@ -91,10 +91,10 @@ int8_t calculateThrottlePercent(void); uint8_t calculateThrottlePercentAbs(void); bool areSticksActive(uint8_t stickPercentLimit); void runawayTakeoffTemporaryDisable(uint8_t disableFlag); -bool wasThrottleRaised(); +bool wasThrottleRaised(void); timeUs_t getLastDisarmTimeUs(void); -bool isTryingToArm(); -void resetTryingToArm(); +bool isTryingToArm(void); +void resetTryingToArm(void); void subTaskTelemetryPollSensors(timeUs_t currentTimeUs); diff --git a/src/main/fc/gps_lap_timer.c b/src/main/fc/gps_lap_timer.c index dc13c930d5..438d64cfdd 100644 --- a/src/main/fc/gps_lap_timer.c +++ b/src/main/fc/gps_lap_timer.c @@ -69,7 +69,7 @@ void gpsLapTimerStartSetGate(void) gpsLapTimerData.numberOfSetReadings = 0; } -void gpsLapTimerProcessSettingGate(void) +static void gpsLapTimerProcessSettingGate(void) { if (gpsLapTimerData.numberOfSetReadings < MAX_GATE_SET_READINGS){ gateSetLatReadings += gpsSol.llh.lat; diff --git a/src/main/fc/rc.c b/src/main/fc/rc.c index e2485640a5..80c284191a 100644 --- a/src/main/fc/rc.c +++ b/src/main/fc/rc.c @@ -166,7 +166,7 @@ STATIC_ASSERT(CONTROL_RATE_CONFIG_RATE_LIMIT_MAX <= (uint16_t)SETPOINT_RATE_LIMI #define RC_RATE_INCREMENTAL 14.54f -float applyBetaflightRates(const int axis, float rcCommandf, const float rcCommandfAbs) +static float applyBetaflightRates(const int axis, float rcCommandf, const float rcCommandfAbs) { if (currentControlRateProfile->rcExpo[axis]) { const float expof = currentControlRateProfile->rcExpo[axis] / 100.0f; @@ -186,7 +186,7 @@ float applyBetaflightRates(const int axis, float rcCommandf, const float rcComma return angleRate; } -float applyRaceFlightRates(const int axis, float rcCommandf, const float rcCommandfAbs) +static float applyRaceFlightRates(const int axis, float rcCommandf, const float rcCommandfAbs) { // -1.0 to 1.0 ranged and curved rcCommandf = ((1.0f + 0.01f * currentControlRateProfile->rcExpo[axis] * (rcCommandf * rcCommandf - 1.0f)) * rcCommandf); @@ -197,7 +197,7 @@ float applyRaceFlightRates(const int axis, float rcCommandf, const float rcComma return angleRate; } -float applyKissRates(const int axis, float rcCommandf, const float rcCommandfAbs) +static float applyKissRates(const int axis, float rcCommandf, const float rcCommandfAbs) { const float rcCurvef = currentControlRateProfile->rcExpo[axis] / 100.0f; @@ -208,7 +208,7 @@ float applyKissRates(const int axis, float rcCommandf, const float rcCommandfAbs return kissAngle; } -float applyActualRates(const int axis, float rcCommandf, const float rcCommandfAbs) +static float applyActualRates(const int axis, float rcCommandf, const float rcCommandfAbs) { float expof = currentControlRateProfile->rcExpo[axis] / 100.0f; expof = rcCommandfAbs * (power5(rcCommandf) * expof + rcCommandf * (1 - expof)); @@ -220,7 +220,7 @@ float applyActualRates(const int axis, float rcCommandf, const float rcCommandfA return angleRate; } -float applyQuickRates(const int axis, float rcCommandf, const float rcCommandfAbs) +static float applyQuickRates(const int axis, float rcCommandf, const float rcCommandfAbs) { const uint16_t rcRate = currentControlRateProfile->rcRates[axis] * 2; const uint16_t maxDPS = MAX(currentControlRateProfile->rates[axis] * 10, rcRate); @@ -322,7 +322,7 @@ bool getRxRateValid(void) // Initialize or update the filters base on either the manually selected cutoff, or // the auto-calculated cutoff frequency based on detected rx frame rate. -FAST_CODE_NOINLINE void rcSmoothingSetFilterCutoffs(rcSmoothingFilter_t *smoothingData) +static FAST_CODE_NOINLINE void rcSmoothingSetFilterCutoffs(rcSmoothingFilter_t *smoothingData) { // in auto mode, calculate the RC smoothing cutoff from the smoothed Rx link frequency const uint16_t oldSetpointCutoff = smoothingData->setpointCutoffFrequency; @@ -518,7 +518,7 @@ static FAST_CODE void processRcSmoothingFilter(void) #endif // USE_RC_SMOOTHING_FILTER #ifdef USE_FEEDFORWARD -FAST_CODE_NOINLINE void calculateFeedforward(const pidRuntime_t *pid, flight_dynamics_index_t axis) +static FAST_CODE_NOINLINE void calculateFeedforward(const pidRuntime_t *pid, flight_dynamics_index_t axis) { const float rxInterval = currentRxIntervalUs * 1e-6f; // seconds float rxRate = currentRxRateHz; // 1e6f / currentRxIntervalUs; diff --git a/src/main/fc/rc_controls.h b/src/main/fc/rc_controls.h index 52ffce90f4..70a3657d02 100644 --- a/src/main/fc/rc_controls.h +++ b/src/main/fc/rc_controls.h @@ -139,7 +139,7 @@ PG_DECLARE(armingConfig_t, armingConfig); bool areUsingSticksToArm(void); throttleStatus_e calculateThrottleStatus(void); -void processRcStickPositions(); +void processRcStickPositions(void); bool isUsingSticksForArming(void); diff --git a/src/main/fc/rc_modes.c b/src/main/fc/rc_modes.c index 6407db0fce..03d7433aa6 100644 --- a/src/main/fc/rc_modes.c +++ b/src/main/fc/rc_modes.c @@ -99,7 +99,7 @@ bool isRangeActive(uint8_t auxChannelIndex, const channelRange_t *range) * T F - all previous AND macs active, no previous active OR macs * T T - at least 1 previous inactive AND mac, no previous active OR macs */ -void updateMasksForMac(const modeActivationCondition_t *mac, boxBitmask_t *andMask, boxBitmask_t *newMask, bool bActive) +static void updateMasksForMac(const modeActivationCondition_t *mac, boxBitmask_t *andMask, boxBitmask_t *newMask, bool bActive) { if (bitArrayGet(andMask, mac->modeId) || !bitArrayGet(newMask, mac->modeId)) { bool bAnd = mac->modeLogic == MODELOGIC_AND; @@ -118,7 +118,7 @@ void updateMasksForMac(const modeActivationCondition_t *mac, boxBitmask_t *andMa } } -void updateMasksForStickyModes(const modeActivationCondition_t *mac, boxBitmask_t *andMask, boxBitmask_t *newMask) +static void updateMasksForStickyModes(const modeActivationCondition_t *mac, boxBitmask_t *andMask, boxBitmask_t *newMask) { if (IS_RC_MODE_ACTIVE(mac->modeId)) { bitArrayClr(andMask, mac->modeId); diff --git a/src/main/fc/tasks.c b/src/main/fc/tasks.c index 62885df0fa..5be00a3ee2 100644 --- a/src/main/fc/tasks.c +++ b/src/main/fc/tasks.c @@ -289,7 +289,7 @@ static void taskCalculateAltitude(timeUs_t currentTimeUs) #endif // USE_BARO || USE_GPS #if defined(USE_RANGEFINDER) -void taskUpdateRangefinder(timeUs_t currentTimeUs) +static void taskUpdateRangefinder(timeUs_t currentTimeUs) { UNUSED(currentTimeUs); @@ -304,7 +304,7 @@ void taskUpdateRangefinder(timeUs_t currentTimeUs) #endif #ifdef USE_OPTICALFLOW -void taskUpdateOpticalflow(timeUs_t currentTimeUs) +static void taskUpdateOpticalflow(timeUs_t currentTimeUs) { UNUSED(currentTimeUs); diff --git a/src/main/fc/tasks.h b/src/main/fc/tasks.h index 1d6b409ede..05280be2ef 100644 --- a/src/main/fc/tasks.h +++ b/src/main/fc/tasks.h @@ -26,5 +26,5 @@ void tasksInitData(void); void tasksInit(void); task_t *getTask(unsigned taskId); -bool taskUpdateRxMainInProgress(); +bool taskUpdateRxMainInProgress(void); diff --git a/src/main/flight/alt_hold_multirotor.c b/src/main/flight/alt_hold_multirotor.c index e1547638f7..68db59a12c 100644 --- a/src/main/flight/alt_hold_multirotor.c +++ b/src/main/flight/alt_hold_multirotor.c @@ -52,7 +52,7 @@ typedef struct { altHoldState_t altHold; -void altHoldReset(void) +static void altHoldReset(void) { resetAltitudeControl(); altHold.targetAltitudeCm = getAltitudeCm(); @@ -68,7 +68,7 @@ void altHoldInit(void) altHoldReset(); } -void altHoldProcessTransitions(void) { +static void altHoldProcessTransitions(void) { if (FLIGHT_MODE(ALT_HOLD_MODE)) { if (!altHold.isActive) { @@ -90,7 +90,7 @@ void altHoldProcessTransitions(void) { // user throttle must be not more than half way out from hover for a stable hold } -void altHoldUpdateTargetAltitude(void) +static void altHoldUpdateTargetAltitude(void) { // User can adjust the target altitude with throttle, but only when // - throttle is outside deadband, and @@ -133,7 +133,7 @@ void altHoldUpdateTargetAltitude(void) } } -void altHoldUpdate(void) +static void altHoldUpdate(void) { // check if the user has changed the target altitude using sticks if (altHoldConfig()->alt_hold_adjust_rate) { diff --git a/src/main/flight/alt_hold_wing.c b/src/main/flight/alt_hold_wing.c index 05b0db18c2..c2fb806c8b 100644 --- a/src/main/flight/alt_hold_wing.c +++ b/src/main/flight/alt_hold_wing.c @@ -39,7 +39,7 @@ #include "alt_hold.h" -void altHoldReset(void) +LOCAL_UNUSED_FUNCTION static void altHoldReset(void) { } diff --git a/src/main/flight/autopilot_multirotor.c b/src/main/flight/autopilot_multirotor.c index c70635599a..00eff1555b 100644 --- a/src/main/flight/autopilot_multirotor.c +++ b/src/main/flight/autopilot_multirotor.c @@ -98,7 +98,7 @@ static void resetEFAxisFilters(efPidAxis_t* efAxis, const float vaGain) pt1FilterInit(&efAxis->accelerationLpf, vaGain); } -void resetEFAxisParams(efPidAxis_t *efAxis, const float vaGain) +static void resetEFAxisParams(efPidAxis_t *efAxis, const float vaGain) { // at start only resetEFAxisFilters(efAxis, vaGain); @@ -223,7 +223,7 @@ void setSticksActiveStatus(bool areSticksActive) ap.sticksActive = areSticksActive; } -void setTargetLocationByAxis(const gpsLocation_t* newTargetLocation, axisEF_e efAxisIdx) +static void setTargetLocationByAxis(const gpsLocation_t* newTargetLocation, axisEF_e efAxisIdx) // not used at present but needed by upcoming GPS code { if (efAxisIdx == LON) { diff --git a/src/main/flight/failsafe.c b/src/main/flight/failsafe.c index 28af2d6aac..41f7c9d243 100644 --- a/src/main/flight/failsafe.c +++ b/src/main/flight/failsafe.c @@ -219,7 +219,7 @@ void failsafeCheckDataFailurePeriod(void) } } -uint32_t failsafeFailurePeriodMs(void) +LOCAL_UNUSED_FUNCTION static uint32_t failsafeFailurePeriodMs(void) { return failsafeState.rxDataFailurePeriod; } diff --git a/src/main/flight/gps_rescue_multirotor.c b/src/main/flight/gps_rescue_multirotor.c index c88295d9dc..cfb3b83feb 100644 --- a/src/main/flight/gps_rescue_multirotor.c +++ b/src/main/flight/gps_rescue_multirotor.c @@ -617,7 +617,7 @@ static bool checkGPSRescueIsAvailable(void) return result; } -void disarmOnImpact(void) +static void disarmOnImpact(void) { if (acc.accMagnitude > rescueState.intent.disarmThreshold) { setArmingDisabled(ARMING_DISABLED_ARM_SWITCH); @@ -626,7 +626,7 @@ void disarmOnImpact(void) } } -void descend(bool newGpsData) +static void descend(bool newGpsData) { if (newGpsData) { // consider landing area to be a circle half landing height around home, to avoid overshooting home point @@ -672,7 +672,7 @@ void descend(bool newGpsData) rescueState.intent.targetAltitudeCm -= altitudeStepCm; } -void initialiseRescueValues (void) +static void initialiseRescueValues (void) { rescueState.intent.secondsFailing = 0; // reset the sanity check timer rescueState.intent.yawAttenuator = 0.0f; // no yaw in the climb diff --git a/src/main/flight/imu.c b/src/main/flight/imu.c index 894658f368..2b77a36871 100644 --- a/src/main/flight/imu.c +++ b/src/main/flight/imu.c @@ -854,7 +854,7 @@ bool imuQuaternionHeadfreeOffsetSet(void) } } -void imuQuaternionMultiplication(quaternion_t *q1, quaternion_t *q2, quaternion_t *result) +static void imuQuaternionMultiplication(quaternion_t *q1, quaternion_t *q2, quaternion_t *result) { const float A = (q1->w + q1->x) * (q2->w + q2->x); const float B = (q1->z - q1->y) * (q2->y - q2->z); diff --git a/src/main/flight/mixer_init.c b/src/main/flight/mixer_init.c index b3124be593..be226230f8 100644 --- a/src/main/flight/mixer_init.c +++ b/src/main/flight/mixer_init.c @@ -396,7 +396,7 @@ void mixerResetRpmLimiter(void) // Create a custom mixer for launch control based on the current settings // but disable the front motors. We don't care about roll or yaw because they // are limited in the PID controller. -void loadLaunchControlMixer(void) +static void loadLaunchControlMixer(void) { for (int i = 0; i < MAX_SUPPORTED_MOTORS; i++) { mixerRuntime.launchControlMixer[i] = mixerRuntime.currentMixer[i]; diff --git a/src/main/flight/pid.c b/src/main/flight/pid.c index 2635692f1a..dbc9b08da0 100644 --- a/src/main/flight/pid.c +++ b/src/main/flight/pid.c @@ -416,7 +416,7 @@ static float wingAdjustSetpoint(float currentPidSetpoint, int axis) #endif // USE_WING } -float getTpaFactorClassic(float tpaArgument) +static float getTpaFactorClassic(float tpaArgument) { static bool isTpaLowFaded = false; bool isThrottlePastTpaLowBreakpoint = (tpaArgument >= pidRuntime.tpaLowBreakpoint || pidRuntime.tpaLowBreakpoint <= 0.01f); diff --git a/src/main/flight/pid.h b/src/main/flight/pid.h index 8c217dd03c..360a805370 100644 --- a/src/main/flight/pid.h +++ b/src/main/flight/pid.h @@ -584,7 +584,7 @@ float pidCompensateThrustLinearization(float throttle); #ifdef USE_AIRMODE_LPF void pidUpdateAirmodeLpf(float currentOffset); -float pidGetAirmodeThrottleOffset(); +float pidGetAirmodeThrottleOffset(void); #endif #ifdef UNIT_TEST @@ -602,8 +602,8 @@ float calcHorizonLevelStrength(void); void dynLpfDTermUpdate(float throttle); void pidSetItermReset(bool enabled); float pidGetPreviousSetpoint(int axis); -float pidGetDT(); -float pidGetPidFrequency(); +float pidGetDT(void); +float pidGetPidFrequency(void); float dynLpfCutoffFreq(float throttle, uint16_t dynLpfMin, uint16_t dynLpfMax, uint8_t expo); #ifdef USE_CHIRP diff --git a/src/main/flight/pid_init.c b/src/main/flight/pid_init.c index d8dc0484a2..799ee18605 100644 --- a/src/main/flight/pid_init.c +++ b/src/main/flight/pid_init.c @@ -69,7 +69,7 @@ static void pidSetTargetLooptime(uint32_t pidLooptime) } #ifdef USE_WING -void tpaSpeedBasicInit(const pidProfile_t *pidProfile) +static void tpaSpeedBasicInit(const pidProfile_t *pidProfile) { // basic model assumes prop pitch speed is inf const float gravityFactor = pidProfile->tpa_speed_basic_gravity / 100.0f; @@ -82,7 +82,7 @@ void tpaSpeedBasicInit(const pidProfile_t *pidProfile) pidRuntime.tpaSpeed.inversePropMaxSpeed = 0.0f; } -void tpaSpeedAdvancedInit(const pidProfile_t *pidProfile) +static void tpaSpeedAdvancedInit(const pidProfile_t *pidProfile) { // Advanced model uses prop pitch speed, and is quite limited when craft speed is far above prop pitch speed. pidRuntime.tpaSpeed.twr = (float)pidProfile->tpa_speed_adv_thrust / (float)pidProfile->tpa_speed_adv_mass; @@ -109,7 +109,7 @@ void tpaSpeedAdvancedInit(const pidProfile_t *pidProfile) UNUSED(pidProfile); } -void tpaSpeedInit(const pidProfile_t *pidProfile) +static void tpaSpeedInit(const pidProfile_t *pidProfile) { pidRuntime.tpaSpeed.speed = 0.0f; pidRuntime.tpaSpeed.maxVoltage = pidProfile->tpa_speed_max_voltage / 100.0f; @@ -334,7 +334,7 @@ void pidInitFilters(const pidProfile_t *pidProfile) } #ifdef USE_ADVANCED_TPA -float tpaCurveHyperbolicFunction(float x, void *args) +static float tpaCurveHyperbolicFunction(float x, void *args) { const pidProfile_t *pidProfile = (const pidProfile_t*)args; @@ -356,13 +356,13 @@ float tpaCurveHyperbolicFunction(float x, void *args) return pidThr0 / divisor; } -void tpaCurveHyperbolicInit(const pidProfile_t *pidProfile) +static void tpaCurveHyperbolicInit(const pidProfile_t *pidProfile) { pwlInitialize(&pidRuntime.tpaCurvePwl, pidRuntime.tpaCurvePwl_yValues, TPA_CURVE_PWL_SIZE, 0.0f, 1.0f); pwlFill(&pidRuntime.tpaCurvePwl, tpaCurveHyperbolicFunction, (void*)pidProfile); } -void tpaCurveInit(const pidProfile_t *pidProfile) +static void tpaCurveInit(const pidProfile_t *pidProfile) { pidRuntime.tpaCurveType = pidProfile->tpa_curve_type; switch (pidRuntime.tpaCurveType) { diff --git a/src/main/flight/pos_hold_multirotor.c b/src/main/flight/pos_hold_multirotor.c index a3723885e4..de4147a2df 100644 --- a/src/main/flight/pos_hold_multirotor.c +++ b/src/main/flight/pos_hold_multirotor.c @@ -55,7 +55,7 @@ void posHoldInit(void) posHold.useStickAdjustment = posHoldConfig()->pos_hold_deadband; } -void posHoldCheckSticks(void) +static void posHoldCheckSticks(void) { // if failsafe is active, eg landing mode, don't update the original start point if (!failsafeIsActive() && posHold.useStickAdjustment) { @@ -64,7 +64,7 @@ void posHoldCheckSticks(void) } } -bool sensorsOk(void) +static bool sensorsOk(void) { if (!STATE(GPS_FIX)) { return false; diff --git a/src/main/flight/servos.c b/src/main/flight/servos.c index bbc3b22c81..31a49fac9d 100644 --- a/src/main/flight/servos.c +++ b/src/main/flight/servos.c @@ -204,7 +204,7 @@ const mixerRules_t servoMixers[] = { { 0, NULL }, }; -int16_t determineServoMiddleOrForwardFromChannel(servoIndex_e servoIndex) +static int16_t determineServoMiddleOrForwardFromChannel(servoIndex_e servoIndex) { const uint8_t channelToForwardFrom = servoParams(servoIndex)->forwardFromChannel; diff --git a/src/main/io/dashboard.c b/src/main/io/dashboard.c index a76d858001..e685b04971 100644 --- a/src/main/io/dashboard.c +++ b/src/main/io/dashboard.c @@ -131,7 +131,7 @@ static void resetDisplay(void) dashboardPresent = ug2864hsweg01InitI2C(dev); } -void LCDprint(uint8_t i) +static void LCDprint(uint8_t i) { i2c_OLED_send_char(dev, i); } @@ -628,7 +628,7 @@ static const pageEntry_t pages[PAGE_COUNT] = { #endif }; -void dashboardSetPage(pageId_e pageId) +static void dashboardSetPage(pageId_e pageId) { for (int i = 0; i < PAGE_COUNT; i++) { const pageEntry_t *candidatePage = &pages[i]; diff --git a/src/main/io/displayport_hott.c b/src/main/io/displayport_hott.c index 8b163f537e..0a84f3e9fd 100644 --- a/src/main/io/displayport_hott.c +++ b/src/main/io/displayport_hott.c @@ -30,6 +30,8 @@ #include "cms/cms.h" #include "telemetry/hott.h" +#include "displayport_hott.h" + displayPort_t hottDisplayPort; static bool hottDrawScreen(displayPort_t *displayPort) diff --git a/src/main/io/displayport_hott.h b/src/main/io/displayport_hott.h index 6814bc32e3..affef31fd3 100644 --- a/src/main/io/displayport_hott.h +++ b/src/main/io/displayport_hott.h @@ -21,6 +21,6 @@ #pragma once #include "drivers/display.h" -void hottDisplayportRegister(); -void hottCmsOpen(); +void hottDisplayportRegister(void); +void hottCmsOpen(void); void hottSetCmsKey(uint8_t hottKey, bool esc); diff --git a/src/main/io/displayport_max7456.c b/src/main/io/displayport_max7456.c index 3e937a14ef..aa342773bc 100644 --- a/src/main/io/displayport_max7456.c +++ b/src/main/io/displayport_max7456.c @@ -185,7 +185,7 @@ static bool checkReady(displayPort_t *displayPort, bool rescan) return true; } -void setBackgroundType(displayPort_t *displayPort, displayPortBackground_e backgroundType) +static void setBackgroundType(displayPort_t *displayPort, displayPortBackground_e backgroundType) { UNUSED(displayPort); max7456SetBackgroundType(backgroundType); diff --git a/src/main/io/displayport_oled.c b/src/main/io/displayport_oled.c index 96087c95b7..b590c1b8ce 100644 --- a/src/main/io/displayport_oled.c +++ b/src/main/io/displayport_oled.c @@ -28,6 +28,8 @@ #include "drivers/display.h" #include "drivers/display_ug2864hsweg01.h" +#include "displayport_oled.h" + static displayPort_t oledDisplayPort; static int oledGrab(displayPort_t *displayPort) diff --git a/src/main/io/flashfs.c b/src/main/io/flashfs.c index 1c84fef9c2..fc84c83a76 100644 --- a/src/main/io/flashfs.c +++ b/src/main/io/flashfs.c @@ -282,7 +282,7 @@ static void flashfsAdvanceTailInBuffer(uint32_t delta) * * Returns the number of bytes written */ -void flashfsWriteCallback(uint32_t arg) +static void flashfsWriteCallback(uint32_t arg) { // Advance the cursor in the file system to match the bytes we wrote flashfsSetTailAddress(tailAddress + arg); diff --git a/src/main/io/gps.c b/src/main/io/gps.c index 8401c5f4b0..129592a005 100644 --- a/src/main/io/gps.c +++ b/src/main/io/gps.c @@ -958,7 +958,7 @@ static void setSatInfoMessageRate(uint8_t divisor) #endif // USE_GPS_UBLOX #ifdef USE_GPS_NMEA -void gpsConfigureNmea(void) +static void gpsConfigureNmea(void) { // minimal support for NMEA, we only: // - set the FC's GPS port to the user's configured rate, and @@ -1031,7 +1031,7 @@ void gpsConfigureNmea(void) #ifdef USE_GPS_UBLOX -void gpsConfigureUblox(void) +static void gpsConfigureUblox(void) { // Wait until GPS transmit buffer is empty @@ -1302,7 +1302,7 @@ void gpsConfigureUblox(void) } #endif // USE_GPS_UBLOX -void gpsConfigureHardware(void) +static void gpsConfigureHardware(void) { switch (gpsConfig()->provider) { case GPS_NMEA: @@ -2628,7 +2628,7 @@ void GPS_distance_cm_bearing(const gpsLocation_t *from, const gpsLocation_t* to, } } -void GPS_calculateDistanceAndDirectionToHome(void) +static void GPS_calculateDistanceAndDirectionToHome(void) { if (STATE(GPS_FIX_HOME)) { uint32_t dist; diff --git a/src/main/io/ledstrip.c b/src/main/io/ledstrip.c index 03dd8b4bf7..74917f1c87 100644 --- a/src/main/io/ledstrip.c +++ b/src/main/io/ledstrip.c @@ -286,7 +286,7 @@ enum ledBarIds { }; static uint8_t ledBarStates[LED_BAR_COUNT] = {0}; -void updateLedBars(void) +static void updateLedBars(void) { memset(ledBarStates, 0, sizeof(ledBarStates)); for (int ledIndex = 0; ledIndex < ledCounts.count; ledIndex++) { @@ -1193,7 +1193,7 @@ static applyLayerFn_timed* layerTable[] = { [timRing] = &applyLedThrustRingLayer }; -bool isOverlayTypeUsed(ledOverlayId_e overlayType) +static bool isOverlayTypeUsed(ledOverlayId_e overlayType) { for (int ledIndex = 0; ledIndex < ledCounts.count; ledIndex++) { const ledConfig_t *ledConfig = &ledStripStatusModeConfig()->ledConfigs[ledIndex]; diff --git a/src/main/io/pidaudio.c b/src/main/io/pidaudio.c index 26be198290..88ade28418 100644 --- a/src/main/io/pidaudio.c +++ b/src/main/io/pidaudio.c @@ -44,12 +44,12 @@ void pidAudioInit(void) audioSetupIO(); } -void pidAudioStart(void) +static void pidAudioStart(void) { audioGenerateWhiteNoise(); } -void pidAudioStop(void) +static void pidAudioStop(void) { audioSilence(); } diff --git a/src/main/io/rcdevice.h b/src/main/io/rcdevice.h index 80e786f462..b57a468432 100644 --- a/src/main/io/rcdevice.h +++ b/src/main/io/rcdevice.h @@ -172,4 +172,4 @@ void runcamDeviceSimulate5KeyOSDCableButtonRelease(runcamDevice_t *device, rcdev void runcamDeviceSendAttitude(runcamDevice_t *device); -runcamDeviceRequest_t* rcdeviceGetRequest(); +runcamDeviceRequest_t* rcdeviceGetRequest(void); diff --git a/src/main/io/serial.c b/src/main/io/serial.c index 46dd18c269..516915e56b 100644 --- a/src/main/io/serial.c +++ b/src/main/io/serial.c @@ -338,7 +338,7 @@ serialPortUsage_t *findSerialPortUsageByIdentifier(serialPortIdentifier_e identi return NULL; } -serialPortUsage_t *findSerialPortUsageByPort(const serialPort_t *serialPort) +static serialPortUsage_t *findSerialPortUsageByPort(const serialPort_t *serialPort) { for (serialPortUsage_t* usage = serialPortUsageList; usage < ARRAYEND(serialPortUsageList); usage++) { if (usage->serialPort == serialPort) { diff --git a/src/main/io/serial.h b/src/main/io/serial.h index 2f6e98c16f..3c583574ee 100644 --- a/src/main/io/serial.h +++ b/src/main/io/serial.h @@ -184,7 +184,6 @@ const serialPortConfig_t *findNextSerialPortConfig(serialPortFunction_e function portSharing_e determinePortSharing(const serialPortConfig_t *portConfig, serialPortFunction_e function); bool isSerialPortShared(const serialPortConfig_t *portConfig, uint16_t functionMask, serialPortFunction_e sharedWithFunction); -void pgResetFn_serialConfig(serialConfig_t *serialConfig); //!!TODO remove need for this serialPortUsage_t *findSerialPortUsageByIdentifier(serialPortIdentifier_e identifier); int findSerialPortIndexByIdentifier(serialPortIdentifier_e identifier); serialPortIdentifier_e findSerialPortByName(const char* portName, int (*cmp)(const char *portName, const char *candidate)); diff --git a/src/main/io/serial_4way.c b/src/main/io/serial_4way.c index 5dda23f3b9..552fc5d58c 100644 --- a/src/main/io/serial_4way.c +++ b/src/main/io/serial_4way.c @@ -318,7 +318,7 @@ void esc4wayRelease(void) CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -uint16_t _crc_xmodem_update (uint16_t crc, uint8_t data) +static uint16_t _crc_xmodem_update (uint16_t crc, uint8_t data) { int i; diff --git a/src/main/io/serial_resource.c b/src/main/io/serial_resource.c index 878968d0bf..b353d1daff 100644 --- a/src/main/io/serial_resource.c +++ b/src/main/io/serial_resource.c @@ -25,6 +25,8 @@ #include "platform.h" +#include "drivers/serial_impl.h" + #include "io/serial.h" // convert identifier into port type diff --git a/src/main/io/spektrum_rssi.c b/src/main/io/spektrum_rssi.c index a9d65caef7..77519691cd 100644 --- a/src/main/io/spektrum_rssi.c +++ b/src/main/io/spektrum_rssi.c @@ -50,7 +50,7 @@ static uint16_t spek_fade_last_sec_count = 0; // Stores the fade count at the la #endif // Linear mapping and interpolation function -int32_t map(int32_t x, int32_t in_min, int32_t in_max, int32_t out_min, int32_t out_max) +static int32_t map(int32_t x, int32_t in_min, int32_t in_max, int32_t out_min, int32_t out_max) { return (x - in_min) * (out_max - out_min) / (in_max - in_min) + out_min; } diff --git a/src/main/io/spektrum_vtx_control.c b/src/main/io/spektrum_vtx_control.c index 910fcf5257..3582c3ec68 100644 --- a/src/main/io/spektrum_vtx_control.c +++ b/src/main/io/spektrum_vtx_control.c @@ -98,7 +98,7 @@ const uint8_t vtxSaPi[SPEKTRUM_VTX_POWER_COUNT] = { }; #endif // USE_VTX_SMARTAUDIO -uint8_t convertSpektrumVtxPowerIndex(uint8_t sPower) +static uint8_t convertSpektrumVtxPowerIndex(uint8_t sPower) { uint8_t devicePower = 0; diff --git a/src/main/io/statusindicator.c b/src/main/io/statusindicator.c index 137535c444..fcd1bb58f7 100644 --- a/src/main/io/statusindicator.c +++ b/src/main/io/statusindicator.c @@ -38,7 +38,7 @@ typedef enum { static warningLedState_e warningLedState = WARNING_LED_OFF; -void warningLedResetTimer(void) +LOCAL_UNUSED_FUNCTION static void warningLedResetTimer(void) { uint32_t now = millis(); warningLedTimer = now + 500000; diff --git a/src/main/io/usb_cdc_hid.h b/src/main/io/usb_cdc_hid.h index ca65b8cffc..fa0c1dc255 100644 --- a/src/main/io/usb_cdc_hid.h +++ b/src/main/io/usb_cdc_hid.h @@ -21,6 +21,6 @@ #pragma once void sendRcDataToHid(void); -bool cdcDeviceIsMayBeActive(); +bool cdcDeviceIsMayBeActive(void); void sendReport(uint8_t *report, uint8_t len); uint8_t usbIsConnected(void); diff --git a/src/main/io/usb_msc.c b/src/main/io/usb_msc.c index 524f40f791..5ec1d2826f 100644 --- a/src/main/io/usb_msc.c +++ b/src/main/io/usb_msc.c @@ -27,6 +27,7 @@ #include "drivers/sdcard.h" #include "io/flashfs.h" +#include "usb_msc.h" #if defined(USE_USB_MSC) diff --git a/src/main/io/vtx_smartaudio.c b/src/main/io/vtx_smartaudio.c index 6e9d3ea362..df3a48fc6c 100644 --- a/src/main/io/vtx_smartaudio.c +++ b/src/main/io/vtx_smartaudio.c @@ -854,7 +854,7 @@ static void vtxSAProcess(vtxDevice_t *vtxDevice, timeUs_t currentTimeUs) #ifdef USE_VTX_COMMON // Interface to common VTX API -vtxDevType_e vtxSAGetDeviceType(const vtxDevice_t *vtxDevice) +static vtxDevType_e vtxSAGetDeviceType(const vtxDevice_t *vtxDevice) { UNUSED(vtxDevice); return VTXDEV_SMARTAUDIO; diff --git a/src/main/io/vtx_tramp.h b/src/main/io/vtx_tramp.h index a56410490f..cf04bb3f2a 100644 --- a/src/main/io/vtx_tramp.h +++ b/src/main/io/vtx_tramp.h @@ -29,5 +29,5 @@ bool vtxTrampInit(void); -uint16_t vtxTrampGetCurrentActualPower(); -uint16_t vtxTrampGetCurrentTemp(); +uint16_t vtxTrampGetCurrentActualPower(void); +uint16_t vtxTrampGetCurrentTemp(void); diff --git a/src/main/msc/emfat.c b/src/main/msc/emfat.c index f1db3b6cc8..7e7bfe7c26 100644 --- a/src/main/msc/emfat.c +++ b/src/main/msc/emfat.c @@ -217,7 +217,7 @@ typedef struct #pragma pack(pop) -bool emfat_init_entries(emfat_entry_t *entries) +static bool emfat_init_entries(emfat_entry_t *entries) { emfat_entry_t *e; int i, n; @@ -339,7 +339,7 @@ bool emfat_init(emfat_t *emfat, const char *label, emfat_entry_t *entries) return true; } -void read_mbr_sector(const emfat_t *emfat, uint8_t *sect) +static void read_mbr_sector(const emfat_t *emfat, uint8_t *sect) { mbr_t *mbr; memset(sect, 0, SECT); @@ -356,7 +356,7 @@ void read_mbr_sector(const emfat_t *emfat, uint8_t *sect) mbr->BootSignature[1] = 0xAA; } -void read_boot_sector(const emfat_t *emfat, uint8_t *sect) +static void read_boot_sector(const emfat_t *emfat, uint8_t *sect) { boot_sector *bs; memset(sect, 0, SECT); @@ -398,7 +398,7 @@ void read_boot_sector(const emfat_t *emfat, uint8_t *sect) #define IS_CLUST_OF(clust, entry) ((clust) >= (entry)->priv.first_clust && (clust) <= (entry)->priv.last_reserved) -emfat_entry_t *find_entry(const emfat_t *emfat, uint32_t clust, emfat_entry_t *nearest) +static emfat_entry_t *find_entry(const emfat_t *emfat, uint32_t clust, emfat_entry_t *nearest) { if (nearest == NULL) { nearest = emfat->priv.entries; @@ -420,7 +420,7 @@ emfat_entry_t *find_entry(const emfat_t *emfat, uint32_t clust, emfat_entry_t *n return NULL; } -void read_fsinfo_sector(const emfat_t *emfat, uint8_t *sect) +static void read_fsinfo_sector(const emfat_t *emfat, uint8_t *sect) { UNUSED(emfat); @@ -436,7 +436,7 @@ void read_fsinfo_sector(const emfat_t *emfat, uint8_t *sect) info->signature3 = 0xAA550000; } -void read_fat_sector(emfat_t *emfat, uint8_t *sect, uint32_t index) +static void read_fat_sector(emfat_t *emfat, uint8_t *sect, uint32_t index) { emfat_entry_t *le; uint32_t *values; @@ -489,7 +489,7 @@ void read_fat_sector(emfat_t *emfat, uint8_t *sect, uint32_t index) emfat->priv.last_entry = le; } -void fill_entry(dir_entry *entry, const char *name, uint8_t attr, uint32_t clust, const uint32_t cma[3], uint32_t size) +static void fill_entry(dir_entry *entry, const char *name, uint8_t attr, uint32_t clust, const uint32_t cma[3], uint32_t size) { int i, l, l1, l2; int dot_pos; @@ -553,7 +553,7 @@ void fill_entry(dir_entry *entry, const char *name, uint8_t attr, uint32_t clust return; } -void fill_dir_sector(emfat_t *emfat, uint8_t *data, emfat_entry_t *entry, uint32_t rel_sect) +static void fill_dir_sector(emfat_t *emfat, uint8_t *data, emfat_entry_t *entry, uint32_t rel_sect) { dir_entry *de; uint32_t avail; @@ -600,7 +600,7 @@ void fill_dir_sector(emfat_t *emfat, uint8_t *data, emfat_entry_t *entry, uint32 } } -void read_data_sector(emfat_t *emfat, uint8_t *data, uint32_t rel_sect) +static void read_data_sector(emfat_t *emfat, uint8_t *data, uint32_t rel_sect) { emfat_entry_t *le; uint32_t cluster; @@ -659,7 +659,7 @@ void emfat_read(emfat_t *emfat, uint8_t *data, uint32_t sector, int num_sectors) } } -void write_data_sector(emfat_t *emfat, const uint8_t *data, uint32_t rel_sect) +LOCAL_UNUSED_FUNCTION static void write_data_sector(emfat_t *emfat, const uint8_t *data, uint32_t rel_sect) { emfat_entry_t *le; uint32_t cluster; diff --git a/src/main/msp/msp.c b/src/main/msp/msp.c index fdb95d7cd1..df8e717cb9 100644 --- a/src/main/msp/msp.c +++ b/src/main/msp/msp.c @@ -398,7 +398,7 @@ static void mspRebootFn(serialPort_t *serialPort) #define MSP_DISPATCH_DELAY_US 1000000 -void mspReboot(dispatchEntry_t* self) +static void mspReboot(dispatchEntry_t* self) { UNUSED(self); @@ -413,7 +413,7 @@ dispatchEntry_t mspRebootEntry = { mspReboot, 0, NULL, false }; -void writeReadEeprom(dispatchEntry_t* self) +static void writeReadEeprom(dispatchEntry_t* self) { UNUSED(self); diff --git a/src/main/msp/msp_serial.c b/src/main/msp/msp_serial.c index 00601c56b9..4cf5b6d46e 100644 --- a/src/main/msp/msp_serial.c +++ b/src/main/msp/msp_serial.c @@ -483,7 +483,7 @@ static void mspSerialProcessReceivedReply(mspPort_t *msp, mspProcessReplyFnPtr m mspProcessReplyFn(&reply); } -void mspProcessPacket(mspPort_t *mspPort, mspProcessCommandFnPtr mspProcessCommandFn, mspProcessReplyFnPtr mspProcessReplyFn) +static void mspProcessPacket(mspPort_t *mspPort, mspProcessCommandFnPtr mspProcessCommandFn, mspProcessReplyFnPtr mspProcessReplyFn) { mspPostProcessFnPtr mspPostProcessFn = NULL; diff --git a/src/main/osd/osd.c b/src/main/osd/osd.c index 3b65452492..7e4ab9057b 100644 --- a/src/main/osd/osd.c +++ b/src/main/osd/osd.c @@ -278,7 +278,7 @@ bool osdWarnGetState(uint8_t warningIndex) } #ifdef USE_OSD_PROFILES -void setOsdProfile(uint8_t value) +static void setOsdProfile(uint8_t value) { // 1 ->> 001 // 2 ->> 010 @@ -1279,7 +1279,7 @@ STATIC_UNIT_TESTED bool osdProcessStats1(timeUs_t currentTimeUs) return refreshStatsRequired; } -void osdProcessStats2(timeUs_t currentTimeUs) +static void osdProcessStats2(timeUs_t currentTimeUs) { displayBeginTransaction(osdDisplayPort, DISPLAY_TRANSACTION_OPT_RESET_DRAWING); @@ -1307,7 +1307,7 @@ void osdProcessStats2(timeUs_t currentTimeUs) #endif } -void osdProcessStats3(void) +static void osdProcessStats3(void) { #if defined(USE_ACC) osdGForce = 0.0f; diff --git a/src/main/osd/osd_elements.c b/src/main/osd/osd_elements.c index 99cc5484f4..07844d0ea2 100644 --- a/src/main/osd/osd_elements.c +++ b/src/main/osd/osd_elements.c @@ -644,7 +644,7 @@ char osdGetSpeedToSelectedUnitSymbol(void) } } -char osdGetVarioToSelectedUnitSymbol(void) +MAYBE_UNUSED static char osdGetVarioToSelectedUnitSymbol(void) { switch (osdConfig()->units) { case UNIT_IMPERIAL: diff --git a/src/main/pg/bus_i2c.c b/src/main/pg/bus_i2c.c index 1e70c23ccd..20ce63365d 100644 --- a/src/main/pg/bus_i2c.c +++ b/src/main/pg/bus_i2c.c @@ -39,6 +39,8 @@ #include "pg/bus_i2c.h" +PG_REGISTER_ARRAY_WITH_RESET_FN(i2cConfig_t, I2CDEV_COUNT, i2cConfig, PG_I2C_CONFIG, 1); + #ifndef I2C1_SCL_PIN #define I2C1_SCL_PIN NONE #endif @@ -100,6 +102,4 @@ void pgResetFn_i2cConfig(i2cConfig_t *i2cConfig) } } -PG_REGISTER_ARRAY_WITH_RESET_FN(i2cConfig_t, I2CDEV_COUNT, i2cConfig, PG_I2C_CONFIG, 1); - #endif // defined(USE_I2C) && !defined(USE_SOFT_I2C) diff --git a/src/main/pg/pg.h b/src/main/pg/pg.h index d7a2333e5b..8159a443d7 100644 --- a/src/main/pg/pg.h +++ b/src/main/pg/pg.h @@ -139,7 +139,7 @@ extern const uint8_t __pg_resetdata_end[]; /**/ #define PG_REGISTER_WITH_RESET_FN(_type, _name, _pgn, _version) \ - extern void pgResetFn_ ## _name(_type *); \ + static void pgResetFn_ ## _name(_type *); \ PG_REGISTER_I(_type, _name, _pgn, _version, .reset = {.fn = (pgResetFunc*)&pgResetFn_ ## _name }) \ /**/ diff --git a/src/main/rx/cc2500_frsky_x.c b/src/main/rx/cc2500_frsky_x.c index 133a10ea81..63dfb48ee1 100644 --- a/src/main/rx/cc2500_frsky_x.c +++ b/src/main/rx/cc2500_frsky_x.c @@ -298,7 +298,7 @@ void frSkyXSetRcData(uint16_t *rcData, const uint8_t *packet) } } -bool isValidPacket(const uint8_t *packet) +static bool isValidPacket(const uint8_t *packet) { bool useBindTxId2 = false; diff --git a/src/main/rx/cc2500_redpine.c b/src/main/rx/cc2500_redpine.c index 7d96f338ea..44bcb5e742 100644 --- a/src/main/rx/cc2500_redpine.c +++ b/src/main/rx/cc2500_redpine.c @@ -86,7 +86,7 @@ static void initBindTuneRx(void); static bool tuneRx1(uint8_t *packet); static bool tuneRx2(uint8_t *packet); static bool tuneRx3(uint8_t *packet); -static void nextChannel(); +static void nextChannel(void); static bool redpineRxPacketBind(uint8_t *packet); static bool isRedpineFast(void); @@ -389,7 +389,7 @@ static bool isRedpineFast(void) return (redpineFast); } -void switchRedpineMode(void) +static void switchRedpineMode(void) { redpineFast = !redpineFast; } diff --git a/src/main/rx/cc2500_sfhss.c b/src/main/rx/cc2500_sfhss.c index 640dd646d7..ac1ef25368 100644 --- a/src/main/rx/cc2500_sfhss.c +++ b/src/main/rx/cc2500_sfhss.c @@ -188,7 +188,7 @@ static bool sfhssPacketParse(uint8_t *packet, bool check_txid) return true; } -void sfhssRx(void) +static void sfhssRx(void) { cc2500Strobe(CC2500_SIDLE); cc2500WriteReg(CC2500_23_FSCAL3, calData[sfhss_channel][0]); @@ -278,7 +278,7 @@ static bool tune3Rx(uint8_t *packet) return false; } -void sfhssnextChannel(void) +static void sfhssnextChannel(void) { do { sfhss_channel += sfhss_code + 2; diff --git a/src/main/rx/cyrf6936_spektrum.c b/src/main/rx/cyrf6936_spektrum.c index b23a261e8e..d368ba920f 100644 --- a/src/main/rx/cyrf6936_spektrum.c +++ b/src/main/rx/cyrf6936_spektrum.c @@ -506,7 +506,7 @@ static bool isValidPacket(const uint8_t *packet) return true; } -rx_spi_received_e spektrumReadPacket(uint8_t *payload, const uint32_t timeStamp) +static rx_spi_received_e spektrumReadPacket(uint8_t *payload, const uint32_t timeStamp) { rx_spi_received_e result = RX_SPI_RECEIVED_NONE; diff --git a/src/main/rx/expresslrs.c b/src/main/rx/expresslrs.c index c71a196933..514c662f90 100644 --- a/src/main/rx/expresslrs.c +++ b/src/main/rx/expresslrs.c @@ -520,7 +520,7 @@ void expressLrsOnTimerTockISR(void) static uint16_t lostConnectionCounter = 0; -void lostConnection(void) +static void lostConnection(void) { lostConnectionCounter++; diff --git a/src/main/rx/jetiexbus.c b/src/main/rx/jetiexbus.c index e17029d976..4cbcf158f8 100644 --- a/src/main/rx/jetiexbus.c +++ b/src/main/rx/jetiexbus.c @@ -102,7 +102,7 @@ uint16_t jetiExBusCalcCRC16(const uint8_t *pt, uint8_t msgLen) return(crc16_data); } -void jetiExBusDecodeChannelFrame(uint8_t *exBusFrame) +static void jetiExBusDecodeChannelFrame(uint8_t *exBusFrame) { uint16_t value; uint8_t frameAddr; @@ -123,7 +123,7 @@ void jetiExBusDecodeChannelFrame(uint8_t *exBusFrame) } } -void jetiExBusFrameReset(void) +static void jetiExBusFrameReset(void) { jetiExBusFramePosition = 0; jetiExBusFrameLength = EXBUS_MAX_CHANNEL_FRAME_SIZE; diff --git a/src/main/rx/msp.h b/src/main/rx/msp.h index cb80ac4c30..601af9d917 100644 --- a/src/main/rx/msp.h +++ b/src/main/rx/msp.h @@ -25,4 +25,4 @@ struct rxRuntimeState_s; float rxMspReadRawRC(const rxRuntimeState_t *rxRuntimeState, uint8_t chan); void rxMspInit(const struct rxConfig_s *rxConfig, struct rxRuntimeState_s *rxRuntimeState); void rxMspFrameReceive(const uint16_t *frame, int channelCount); -uint8_t rxMspOverrideFrameStatus(); +uint8_t rxMspOverrideFrameStatus(void); diff --git a/src/main/rx/rx.c b/src/main/rx/rx.c index 77fdf27ca8..b063da354d 100644 --- a/src/main/rx/rx.c +++ b/src/main/rx/rx.c @@ -682,7 +682,7 @@ static void readRxChannelsApplyRanges(void) } } -void detectAndApplySignalLossBehaviour(void) +static void detectAndApplySignalLossBehaviour(void) { const uint32_t currentTimeMs = millis(); const bool boxFailsafeSwitchIsOn = IS_RC_MODE_ACTIVE(BOXFAILSAFE); diff --git a/src/main/rx/spektrum.c b/src/main/rx/spektrum.c index f291bb5fec..4889499a45 100644 --- a/src/main/rx/spektrum.c +++ b/src/main/rx/spektrum.c @@ -190,7 +190,7 @@ static float spektrumReadRawRC(const rxRuntimeState_t *rxRuntimeState, uint8_t c #ifdef USE_SPEKTRUM_BIND -bool spekShouldBind(uint8_t spektrum_sat_bind) +static bool spekShouldBind(uint8_t spektrum_sat_bind) { #ifdef USE_SPEKTRUM_BIND_PLUG IO_t BindPlug = IOGetByTag(rxConfig()->spektrum_bind_plug_ioTag); diff --git a/src/main/rx/spektrum.h b/src/main/rx/spektrum.h index 256b42053c..c35a8c2f6b 100644 --- a/src/main/rx/spektrum.h +++ b/src/main/rx/spektrum.h @@ -50,6 +50,6 @@ extern uint8_t rssi_channel; // Stores the RX RSSI channel. void spektrumBind(rxConfig_t *rxConfig); bool spektrumInit(const rxConfig_t *rxConfig, rxRuntimeState_t *rxRuntimeState); -bool srxlTelemetryBufferEmpty(); +bool srxlTelemetryBufferEmpty(void); void srxlRxWriteTelemetryData(const void *data, int len); bool srxlRxIsActive(void); diff --git a/src/main/rx/srxl2.c b/src/main/rx/srxl2.c index 1b5366fc22..d12a2792d6 100644 --- a/src/main/rx/srxl2.c +++ b/src/main/rx/srxl2.c @@ -124,7 +124,7 @@ uint8_t globalResult = 0; // if 50ms with not activity, go to default baudrate and to step 1 -bool srxl2ProcessHandshake(const Srxl2Header* header) +static bool srxl2ProcessHandshake(const Srxl2Header* header) { const Srxl2HandshakeSubHeader* handshake = (Srxl2HandshakeSubHeader*)(header + 1); if (handshake->destinationDeviceId == Broadcast) { @@ -164,7 +164,7 @@ bool srxl2ProcessHandshake(const Srxl2Header* header) return true; } -void srxl2ProcessChannelData(const Srxl2ChannelDataHeader* channelData, rxRuntimeState_t *rxRuntimeState) +static void srxl2ProcessChannelData(const Srxl2ChannelDataHeader* channelData, rxRuntimeState_t *rxRuntimeState) { globalResult = RX_FRAME_COMPLETE; @@ -191,7 +191,7 @@ void srxl2ProcessChannelData(const Srxl2ChannelDataHeader* channelData, rxRuntim DEBUG_PRINTF("channel data: %d %d %x\r\n", channelData_header->rssi, channelData_header->frameLosses, channelData_header->channelMask.u32); } -bool srxl2ProcessControlData(const Srxl2Header* header, rxRuntimeState_t *rxRuntimeState) +static bool srxl2ProcessControlData(const Srxl2Header* header, rxRuntimeState_t *rxRuntimeState) { const Srxl2ControlDataSubHeader* controlData = (Srxl2ControlDataSubHeader*)(header + 1); const uint8_t ownId = (FlightController << 4) | unitId; @@ -237,7 +237,7 @@ bool srxl2ProcessControlData(const Srxl2Header* header, rxRuntimeState_t *rxRunt return true; } -bool srxl2ProcessPacket(const Srxl2Header* header, rxRuntimeState_t *rxRuntimeState) +static bool srxl2ProcessPacket(const Srxl2Header* header, rxRuntimeState_t *rxRuntimeState) { switch (header->packetType) { case Handshake: @@ -253,7 +253,7 @@ bool srxl2ProcessPacket(const Srxl2Header* header, rxRuntimeState_t *rxRuntimeSt } // @note assumes packet is fully there -void srxl2Process(rxRuntimeState_t *rxRuntimeState) +static void srxl2Process(rxRuntimeState_t *rxRuntimeState) { if (processBufferPtr->packet.header.id != SRXL2_ID || processBufferPtr->len != processBufferPtr->packet.header.length) { DEBUG_PRINTF("invalid header id: %x, or length: %x received vs %x expected \r\n", processBufferPtr->packet.header.id, processBufferPtr->len, processBufferPtr->packet.header.length); diff --git a/src/main/scheduler/scheduler.c b/src/main/scheduler/scheduler.c index ffac17ec45..70a947a666 100644 --- a/src/main/scheduler/scheduler.c +++ b/src/main/scheduler/scheduler.c @@ -136,14 +136,14 @@ static timeMs_t lastFailsafeCheckMs = 0; #endif STATIC_UNIT_TESTED FAST_DATA_ZERO_INIT task_t* taskQueueArray[TASK_COUNT + 1 + TASK_QUEUE_RESERVE]; // extra item for NULL pointer at end of queue (+ overflow check in UNTT_TEST) -void queueClear(void) +STATIC_UNIT_TESTED void queueClear(void) { memset(taskQueueArray, 0, sizeof(taskQueueArray)); taskQueuePos = 0; taskQueueSize = 0; } -bool queueContains(const task_t *task) +static bool queueContains(const task_t *task) { for (int ii = 0; ii < taskQueueSize; ++ii) { if (taskQueueArray[ii] == task) { @@ -153,7 +153,7 @@ bool queueContains(const task_t *task) return false; } -bool queueAdd(task_t *task) +STATIC_UNIT_TESTED bool queueAdd(task_t *task) { if ((taskQueueSize >= TASK_COUNT) || queueContains(task)) { return false; @@ -169,7 +169,7 @@ bool queueAdd(task_t *task) return false; } -bool queueRemove(task_t *task) +STATIC_UNIT_TESTED bool queueRemove(task_t *task) { for (int ii = 0; ii < taskQueueSize; ++ii) { if (taskQueueArray[ii] == task) { @@ -184,7 +184,7 @@ bool queueRemove(task_t *task) /* * Returns first item queue or NULL if queue empty */ -FAST_CODE task_t *queueFirst(void) +STATIC_UNIT_TESTED FAST_CODE task_t *queueFirst(void) { taskQueuePos = 0; return taskQueueArray[0]; // guaranteed to be NULL if queue is empty @@ -193,7 +193,7 @@ FAST_CODE task_t *queueFirst(void) /* * Returns next item in queue or NULL if at end of queue */ -FAST_CODE task_t *queueNext(void) +STATIC_UNIT_TESTED FAST_CODE task_t *queueNext(void) { return taskQueueArray[++taskQueuePos]; // guaranteed to be NULL at end of queue } diff --git a/src/main/scheduler/scheduler.h b/src/main/scheduler/scheduler.h index 9e190994cc..8728c16b26 100644 --- a/src/main/scheduler/scheduler.h +++ b/src/main/scheduler/scheduler.h @@ -242,10 +242,10 @@ void getTaskInfo(taskId_e taskId, taskInfo_t *taskInfo); void rescheduleTask(taskId_e taskId, timeDelta_t newPeriodUs); void setTaskEnabled(taskId_e taskId, bool newEnabledState); timeDelta_t getTaskDeltaTimeUs(taskId_e taskId); -void schedulerIgnoreTaskStateTime(); -void schedulerIgnoreTaskExecRate(); -void schedulerIgnoreTaskExecTime(); -bool schedulerGetIgnoreTaskExecTime(); +void schedulerIgnoreTaskStateTime(void); +void schedulerIgnoreTaskExecRate(void); +void schedulerIgnoreTaskExecTime(void); +bool schedulerGetIgnoreTaskExecTime(void); void schedulerResetTaskStatistics(taskId_e taskId); void schedulerResetTaskMaxExecutionTime(taskId_e taskId); void schedulerResetCheckFunctionMaxExecutionTime(void); diff --git a/src/main/sensors/acceleration_init.c b/src/main/sensors/acceleration_init.c index 812ab21f6d..1488b8b28a 100644 --- a/src/main/sensors/acceleration_init.c +++ b/src/main/sensors/acceleration_init.c @@ -99,7 +99,7 @@ bool accHasBeenCalibrated(void) #endif } -void accResetRollAndPitchTrims(void) +LOCAL_UNUSED_FUNCTION static void accResetRollAndPitchTrims(void) { resetRollAndPitchTrims(&accelerometerConfigMutable()->accelerometerTrims); } @@ -112,7 +112,7 @@ static void resetFlightDynamicsTrims(flightDynamicsTrims_t *accZero) accZero->values.calibrationCompleted = 0; } -void pgResetFn_accelerometerConfig(accelerometerConfig_t *instance) +static void pgResetFn_accelerometerConfig(accelerometerConfig_t *instance) { RESET_CONFIG_2(accelerometerConfig_t, instance, .acc_lpf_hz = 25, // ATTITUDE/IMU runs at 100Hz (acro) or 500Hz (level modes) so we need to set 50 Hz (or lower) to avoid aliasing @@ -130,7 +130,7 @@ extern bool AccInflightCalibrationMeasurementDone; extern bool AccInflightCalibrationSavetoEEProm; extern bool AccInflightCalibrationActive; -bool accDetect(accDev_t *dev, accelerationSensor_e accHardwareToUse) +static bool accDetect(accDev_t *dev, accelerationSensor_e accHardwareToUse) { accelerationSensor_e accHardware = ACC_NONE; diff --git a/src/main/sensors/adcinternal.c b/src/main/sensors/adcinternal.c index cad059dc89..908d1d9ed8 100644 --- a/src/main/sensors/adcinternal.c +++ b/src/main/sensors/adcinternal.c @@ -23,6 +23,8 @@ #include "platform.h" +#include "adcinternal.h" + #if defined(USE_ADC_INTERNAL) #include "build/debug.h" @@ -38,7 +40,7 @@ typedef struct movingAverageStateUint16_s { uint8_t pos; } movingAverageStateUint16_t; -uint16_t updateMovingAverageUint16(movingAverageStateUint16_t *state, uint16_t newValue) +static uint16_t updateMovingAverageUint16(movingAverageStateUint16_t *state, uint16_t newValue) { state->sum -= state->values[state->pos]; state->values[state->pos] = newValue; diff --git a/src/main/sensors/battery.c b/src/main/sensors/battery.c index 62b684466f..43e7463a66 100644 --- a/src/main/sensors/battery.c +++ b/src/main/sensors/battery.c @@ -246,7 +246,7 @@ void batteryUpdatePresence(void) } } -void batteryUpdateWhDrawn(void) +static void batteryUpdateWhDrawn(void) { static int32_t mAhDrawnPrev = 0; const int32_t mAhDrawnCurrent = getMAhDrawn(); diff --git a/src/main/sensors/compass.c b/src/main/sensors/compass.c index 2ca1b0f689..281aa27ba7 100644 --- a/src/main/sensors/compass.c +++ b/src/main/sensors/compass.c @@ -156,7 +156,7 @@ void compassPreInit(void) } #if !defined(SIMULATOR_BUILD) -bool compassDetect(magDev_t *magDev, uint8_t *alignment) +static bool compassDetect(magDev_t *magDev, uint8_t *alignment) { #ifdef MAG_ALIGN *alignment = MAG_ALIGN; @@ -340,7 +340,7 @@ bool compassDetect(magDev_t *magDev, uint8_t *alignment) return true; } #else -bool compassDetect(magDev_t *dev, sensor_align_e *alignment) +static bool compassDetect(magDev_t *dev, sensor_align_e *alignment) { UNUSED(dev); UNUSED(alignment); diff --git a/src/main/sensors/esc_sensor.c b/src/main/sensors/esc_sensor.c index 067a889c1c..5a43c91eb9 100644 --- a/src/main/sensors/esc_sensor.c +++ b/src/main/sensors/esc_sensor.c @@ -147,7 +147,7 @@ static bool isFrameComplete(void) return bufferPosition == bufferSize; } -bool isEscSensorActive(void) +LOCAL_UNUSED_FUNCTION static bool isEscSensorActive(void) { return escSensorPort != NULL; } diff --git a/src/main/sensors/gyro.c b/src/main/sensors/gyro.c index 659028559c..26b8d6a26c 100644 --- a/src/main/sensors/gyro.c +++ b/src/main/sensors/gyro.c @@ -132,7 +132,7 @@ void pgResetFn_gyroConfig(gyroConfig_t *gyroConfig) gyroConfig->simplified_gyro_filter_multiplier = SIMPLIFIED_TUNING_DEFAULT; } -bool isGyroSensorCalibrationComplete(const gyroSensor_t *gyroSensor) +static bool isGyroSensorCalibrationComplete(const gyroSensor_t *gyroSensor) { return gyroSensor->calibration.cyclesRemaining == 0; } @@ -259,7 +259,7 @@ STATIC_UNIT_TESTED NOINLINE void performGyroCalibration(gyroSensor_t *gyroSensor } #if defined(USE_GYRO_SLEW_LIMITER) -FAST_CODE int32_t gyroSlewLimiter(gyroSensor_t *gyroSensor, int axis) +static FAST_CODE int32_t gyroSlewLimiter(gyroSensor_t *gyroSensor, int axis) { int32_t ret = (int32_t)gyroSensor->gyroDev.gyroADCRaw[axis]; if (gyroConfig()->checkOverflow || gyro.gyroHasOverflowProtection) { @@ -546,7 +546,7 @@ float gyroGetFilteredDownsampled(int axis) return gyroFilteredDownsampled[axis]; } -int16_t gyroReadSensorTemperature(gyroSensor_t gyroSensor) +static int16_t gyroReadSensorTemperature(gyroSensor_t gyroSensor) { if (gyroSensor.gyroDev.temperatureFn) { gyroSensor.gyroDev.temperatureFn(&gyroSensor.gyroDev, &gyroSensor.gyroDev.temperature); diff --git a/src/main/sensors/gyro_init.c b/src/main/sensors/gyro_init.c index 4ebc9153e7..4e09d73c18 100644 --- a/src/main/sensors/gyro_init.c +++ b/src/main/sensors/gyro_init.c @@ -69,6 +69,8 @@ #include "sensors/gyro.h" #include "sensors/sensors.h" +#include "gyro_init.h" + #ifdef USE_MULTI_GYRO #define ACTIVE_GYRO ((gyro.gyroToUse == GYRO_CONFIG_USE_GYRO_2) ? &gyro.gyroSensor2 : &gyro.gyroSensor1) #else diff --git a/src/main/sensors/opticalflow.c b/src/main/sensors/opticalflow.c index 37f45161a7..27dc57e970 100644 --- a/src/main/sensors/opticalflow.c +++ b/src/main/sensors/opticalflow.c @@ -186,7 +186,7 @@ static void applyLPF(vector2_t * flowRates) { flowRates->y = pt2FilterApply(&yFlowLpf, flowRates->y); } -const opticalflow_t * getLatestFlowOpticalflowData(void) { +LOCAL_UNUSED_FUNCTION static const opticalflow_t * getLatestFlowOpticalflowData(void) { return &opticalflow; } diff --git a/src/main/sensors/rangefinder.c b/src/main/sensors/rangefinder.c index 16bf42b000..62790f036d 100644 --- a/src/main/sensors/rangefinder.c +++ b/src/main/sensors/rangefinder.c @@ -243,7 +243,7 @@ void rangefinderUpdate(void) } } -bool isSurfaceAltitudeValid(void) +static bool isSurfaceAltitudeValid(void) { /* diff --git a/src/main/sensors/voltage.c b/src/main/sensors/voltage.c index d0c5728962..7af2caa091 100644 --- a/src/main/sensors/voltage.c +++ b/src/main/sensors/voltage.c @@ -127,7 +127,7 @@ voltageMeterADCState_t voltageMeterADCStates[MAX_VOLTAGE_SENSOR_ADC]; static bool sagCompensationConfigured; -voltageMeterADCState_t *getVoltageMeterADC(uint8_t index) +LOCAL_UNUSED_FUNCTION static voltageMeterADCState_t *getVoltageMeterADC(uint8_t index) { return &voltageMeterADCStates[index]; } diff --git a/src/main/telemetry/crsf.c b/src/main/telemetry/crsf.c index 48140efae8..0c095d7087 100644 --- a/src/main/telemetry/crsf.c +++ b/src/main/telemetry/crsf.c @@ -133,7 +133,7 @@ uint32_t getCrsfCachedBaudrate(void) return CRSF_BAUDRATE; } -bool checkCrsfCustomizedSpeed(void) +static bool checkCrsfCustomizedSpeed(void) { return crsfSpeed.index < BAUD_COUNT ? true : false; } @@ -246,7 +246,7 @@ uint16_t GPS heading ( degree / 100 ) uint16 Altitude ( meter ­1000m offset ) uint8_t Satellites in use ( counter ) */ -void crsfFrameGps(sbuf_t *dst) +MAYBE_UNUSED static void crsfFrameGps(sbuf_t *dst) { // use sbufWrite since CRC does not include frame length sbufWriteU8(dst, CRSF_FRAME_GPS_PAYLOAD_SIZE + CRSF_FRAME_LENGTH_TYPE_CRC); @@ -265,7 +265,7 @@ void crsfFrameGps(sbuf_t *dst) Payload: int16_t Vertical speed ( cm/s ) */ -void crsfFrameVarioSensor(sbuf_t *dst) +MAYBE_UNUSED static void crsfFrameVarioSensor(sbuf_t *dst) { // use sbufWrite since CRC does not include frame length sbufWriteU8(dst, CRSF_FRAME_VARIO_SENSOR_PAYLOAD_SIZE + CRSF_FRAME_LENGTH_TYPE_CRC); @@ -281,7 +281,7 @@ uint16_t Current ( mA * 100 ) uint24_t Fuel ( drawn mAh ) uint8_t Battery remaining ( percent ) */ -void crsfFrameBatterySensor(sbuf_t *dst) +static void crsfFrameBatterySensor(sbuf_t *dst) { // use sbufWrite since CRC does not include frame length sbufWriteU8(dst, CRSF_FRAME_BATTERY_SENSOR_PAYLOAD_SIZE + CRSF_FRAME_LENGTH_TYPE_CRC); @@ -359,7 +359,8 @@ static void crsfFrameAltitude(sbuf_t *dst) Payload: int16_t origin_add ( Origin Device address ) */ -void crsfFrameHeartbeat(sbuf_t *dst) + +MAYBE_UNUSED static void crsfFrameHeartbeat(sbuf_t *dst) { sbufWriteU8(dst, CRSF_FRAME_HEARTBEAT_PAYLOAD_SIZE + CRSF_FRAME_LENGTH_TYPE_CRC); sbufWriteU8(dst, CRSF_FRAMETYPE_HEARTBEAT); @@ -372,7 +373,8 @@ Payload: int8_t destination_add ( Destination Device address ) int8_t origin_add ( Origin Device address ) */ -void crsfFramePing(sbuf_t *dst) + +MAYBE_UNUSED static void crsfFramePing(sbuf_t *dst) { sbufWriteU8(dst, CRSF_FRAME_DEVICE_PING_PAYLOAD_SIZE + CRSF_FRAME_LENGTH_TYPE_CRC); sbufWriteU8(dst, CRSF_FRAMETYPE_DEVICE_PING); @@ -424,7 +426,7 @@ static int16_t decidegrees2Radians10000(int16_t angle_decidegree) } // fill dst buffer with crsf-attitude telemetry frame -void crsfFrameAttitude(sbuf_t *dst) +static void crsfFrameAttitude(sbuf_t *dst) { sbufWriteU8(dst, CRSF_FRAME_ATTITUDE_PAYLOAD_SIZE + CRSF_FRAME_LENGTH_TYPE_CRC); sbufWriteU8(dst, CRSF_FRAMETYPE_ATTITUDE); @@ -438,7 +440,7 @@ void crsfFrameAttitude(sbuf_t *dst) Payload: char[] Flight mode ( Null terminated string ) */ -void crsfFrameFlightMode(sbuf_t *dst) +static void crsfFrameFlightMode(sbuf_t *dst) { // write zero for frame length, since we don't know it yet uint8_t *lengthPtr = sbufPtr(dst); @@ -499,7 +501,7 @@ uint32_t Null Bytes uint8_t 255 (Max MSP Parameter) uint8_t 0x01 (Parameter version 1) */ -void crsfFrameDeviceInfo(sbuf_t *dst) +static void crsfFrameDeviceInfo(sbuf_t *dst) { char buff[30]; tfp_sprintf(buff, "%s %s: %s", FC_FIRMWARE_NAME, FC_VERSION_STRING, systemConfig()->boardIdentifier); @@ -519,7 +521,7 @@ void crsfFrameDeviceInfo(sbuf_t *dst) } #if defined(USE_CRSF_V3) -void crsfFrameSpeedNegotiationResponse(sbuf_t *dst, bool reply) +static void crsfFrameSpeedNegotiationResponse(sbuf_t *dst, bool reply) { uint8_t *lengthPtr = sbufPtr(dst); sbufWriteU8(dst, 0); @@ -547,7 +549,7 @@ static void crsfProcessSpeedNegotiationCmd(const uint8_t *frameStart) crsfSpeed.index = ii; } -void crsfScheduleSpeedNegotiationResponse(void) +static void crsfScheduleSpeedNegotiationResponse(void) { crsfSpeed.hasPendingReply = true; crsfSpeed.isNewSpeedValid = false; diff --git a/src/main/telemetry/frsky_hub.c b/src/main/telemetry/frsky_hub.c index 88b369dc93..06e8aa5bbe 100644 --- a/src/main/telemetry/frsky_hub.c +++ b/src/main/telemetry/frsky_hub.c @@ -478,7 +478,7 @@ bool initFrSkyHubTelemetryExternal(frSkyHubWriteByteFn *frSkyHubWriteByteExterna return false; } -void freeFrSkyHubTelemetryPort(void) +static void freeFrSkyHubTelemetryPort(void) { closeSerialPort(frSkyHubPort); frSkyHubPort = NULL; diff --git a/src/main/telemetry/ghst.c b/src/main/telemetry/ghst.c index d90b0947a9..ea4315c7d0 100644 --- a/src/main/telemetry/ghst.c +++ b/src/main/telemetry/ghst.c @@ -96,7 +96,7 @@ static void ghstFinalize(sbuf_t *dst) } // Battery (Pack) status -void ghstFramePackTelemetry(sbuf_t *dst) +static void ghstFramePackTelemetry(sbuf_t *dst) { // use sbufWrite since CRC does not include frame length sbufWriteU8(dst, GHST_FRAME_PACK_PAYLOAD_SIZE + GHST_FRAME_LENGTH_CRC + GHST_FRAME_LENGTH_TYPE); @@ -119,7 +119,7 @@ void ghstFramePackTelemetry(sbuf_t *dst) } // GPS data, primary, positional data -void ghstFrameGpsPrimaryTelemetry(sbuf_t *dst) +MAYBE_UNUSED static void ghstFrameGpsPrimaryTelemetry(sbuf_t *dst) { // use sbufWrite since CRC does not include frame length sbufWriteU8(dst, GHST_FRAME_GPS_PAYLOAD_SIZE + GHST_FRAME_LENGTH_CRC + GHST_FRAME_LENGTH_TYPE); @@ -138,7 +138,7 @@ void ghstFrameGpsPrimaryTelemetry(sbuf_t *dst) } // GPS data, secondary, auxiliary data -void ghstFrameGpsSecondaryTelemetry(sbuf_t *dst) +MAYBE_UNUSED static void ghstFrameGpsSecondaryTelemetry(sbuf_t *dst) { // use sbufWrite since CRC does not include frame length sbufWriteU8(dst, GHST_FRAME_GPS_PAYLOAD_SIZE + GHST_FRAME_LENGTH_CRC + GHST_FRAME_LENGTH_TYPE); @@ -162,7 +162,7 @@ void ghstFrameGpsSecondaryTelemetry(sbuf_t *dst) } // Mag, Baro (and Vario) data -void ghstFrameMagBaro(sbuf_t *dst) +static void ghstFrameMagBaro(sbuf_t *dst) { int16_t vario = 0; int16_t altitude = 0; diff --git a/src/main/telemetry/hott.c b/src/main/telemetry/hott.c index 343777bfe0..fa0d8a325f 100644 --- a/src/main/telemetry/hott.c +++ b/src/main/telemetry/hott.c @@ -181,7 +181,7 @@ static void initialiseMessages(void) } #ifdef USE_GPS -void addGPSCoordinates(HOTT_GPS_MSG_t *hottGPSMessage, int32_t latitude, int32_t longitude) +STATIC_UNIT_TESTED void addGPSCoordinates(HOTT_GPS_MSG_t *hottGPSMessage, int32_t latitude, int32_t longitude) { int16_t deg = latitude / GPS_DEGREES_DIVIDER; int32_t sec = (latitude - (deg * GPS_DEGREES_DIVIDER)) * 6; @@ -311,7 +311,7 @@ static inline void hottEAMUpdateClimbrate(HOTT_EAM_MSG_t *hottEAMMessage) } #endif -void hottPrepareEAMResponse(HOTT_EAM_MSG_t *hottEAMMessage) +static void hottPrepareEAMResponse(HOTT_EAM_MSG_t *hottEAMMessage) { // Reset alarms hottEAMMessage->warning_beeps = 0x0; diff --git a/src/main/telemetry/hott.h b/src/main/telemetry/hott.h index a2e446d3ca..81d43b2c2d 100644 --- a/src/main/telemetry/hott.h +++ b/src/main/telemetry/hott.h @@ -499,9 +499,9 @@ void configureHoTTTelemetryPort(void); void freeHoTTTelemetryPort(void); #if defined(USE_HOTT_TEXTMODE) && defined(USE_CMS) -bool hottTextmodeIsAlive(); -void hottTextmodeGrab(); -void hottTextmodeExit(); +bool hottTextmodeIsAlive(void); +void hottTextmodeGrab(void); +void hottTextmodeExit(void); void hottTextmodeWriteChar(uint8_t column, uint8_t row, char c); #endif diff --git a/src/main/telemetry/jetiexbus.c b/src/main/telemetry/jetiexbus.c index 07dc7fe2e6..e76a19e16e 100644 --- a/src/main/telemetry/jetiexbus.c +++ b/src/main/telemetry/jetiexbus.c @@ -181,7 +181,7 @@ static uint8_t sendJetiExBusTelemetry(uint8_t packetID, uint8_t item); static uint8_t getNextActiveSensor(uint8_t currentSensor); // Jeti Ex Telemetry CRC calculations for a frame -uint8_t calcCRC8(const uint8_t *pt, uint8_t msgLen) +static uint8_t calcCRC8(const uint8_t *pt, uint8_t msgLen) { uint8_t crc=0; for (uint8_t mlen = 0; mlen < msgLen; mlen++) { @@ -191,7 +191,7 @@ uint8_t calcCRC8(const uint8_t *pt, uint8_t msgLen) return(crc); } -void enableGpsTelemetry(bool enable) +static void enableGpsTelemetry(bool enable) { if (enable) { bitArraySet(&exSensorEnabled, EX_GPS_SATS); @@ -269,7 +269,7 @@ void initJetiExBusTelemetry(void) firstActiveSensor = getNextActiveSensor(0); // find the first active sensor } -void createExTelemetryTextMessage(uint8_t *exMessage, uint8_t messageID, const exBusSensor_t *sensor) +static void createExTelemetryTextMessage(uint8_t *exMessage, uint8_t messageID, const exBusSensor_t *sensor) { uint8_t labelLength = strlen(sensor->label); uint8_t unitLength = strlen(sensor->unit); @@ -285,7 +285,7 @@ void createExTelemetryTextMessage(uint8_t *exMessage, uint8_t messageID, const e exMessage[exMessage[EXTEL_HEADER_TYPE_LEN] + EXTEL_CRC_LEN] = calcCRC8(&exMessage[EXTEL_HEADER_TYPE_LEN], exMessage[EXTEL_HEADER_TYPE_LEN]); } -uint32_t calcGpsDDMMmmm(int32_t value, bool isLong) +static uint32_t calcGpsDDMMmmm(int32_t value, bool isLong) { uint32_t absValue = abs(value); uint16_t deg16 = absValue / GPS_DEGREES_DIVIDER; @@ -300,7 +300,7 @@ uint32_t calcGpsDDMMmmm(int32_t value, bool isLong) return exGps.vInt; } -int32_t getSensorValue(uint8_t sensor) +static int32_t getSensorValue(uint8_t sensor) { switch (sensor) { case EX_VOLTAGE: @@ -407,7 +407,7 @@ uint8_t getNextActiveSensor(uint8_t currentSensor) return currentSensor; } -uint8_t createExTelemetryValueMessage(uint8_t *exMessage, uint8_t item) +static uint8_t createExTelemetryValueMessage(uint8_t *exMessage, uint8_t item) { uint8_t startItem = item; uint8_t sensorItemMaxGroup = (item & 0xF0) + 0x10; @@ -452,7 +452,7 @@ uint8_t createExTelemetryValueMessage(uint8_t *exMessage, uint8_t item) return item; // return the next item } -void createExBusMessage(uint8_t *exBusMessage, const uint8_t *exMessage, uint8_t packetID) +static void createExBusMessage(uint8_t *exBusMessage, const uint8_t *exMessage, uint8_t packetID) { uint16_t crc16; diff --git a/src/main/telemetry/mavlink.c b/src/main/telemetry/mavlink.c index 9fd41091af..497f29e75a 100644 --- a/src/main/telemetry/mavlink.c +++ b/src/main/telemetry/mavlink.c @@ -200,7 +200,7 @@ void checkMAVLinkTelemetryState(void) } } -void mavlinkSendSystemStatus(void) +static void mavlinkSendSystemStatus(void) { uint16_t msgLength; @@ -265,7 +265,7 @@ void mavlinkSendSystemStatus(void) mavlinkSerialWrite(mavBuffer, msgLength); } -void mavlinkSendRCChannelsAndRSSI(void) +static void mavlinkSendRCChannelsAndRSSI(void) { uint16_t msgLength; mavlink_msg_rc_channels_raw_pack(0, 200, &mavMsg, @@ -296,7 +296,7 @@ void mavlinkSendRCChannelsAndRSSI(void) } #if defined(USE_GPS) -void mavlinkSendPosition(void) +static void mavlinkSendPosition(void) { uint16_t msgLength; uint8_t gpsFixType = 0; @@ -376,7 +376,7 @@ void mavlinkSendPosition(void) } #endif -void mavlinkSendAttitude(void) +static void mavlinkSendAttitude(void) { uint16_t msgLength; mavlink_msg_attitude_pack(0, 200, &mavMsg, @@ -398,7 +398,7 @@ void mavlinkSendAttitude(void) mavlinkSerialWrite(mavBuffer, msgLength); } -void mavlinkSendHUDAndHeartbeat(void) +static void mavlinkSendHUDAndHeartbeat(void) { uint16_t msgLength; float mavAltitude = 0; @@ -508,7 +508,7 @@ void mavlinkSendHUDAndHeartbeat(void) mavlinkSerialWrite(mavBuffer, msgLength); } -void processMAVLinkTelemetry(void) +static void processMAVLinkTelemetry(void) { // is executed @ TELEMETRY_MAVLINK_MAXRATE rate if (mavlinkStreamTrigger(MAV_DATA_STREAM_EXTENDED_STATUS)) { diff --git a/src/main/telemetry/msp_shared.c b/src/main/telemetry/msp_shared.c index b0993d175c..42670e69d4 100644 --- a/src/main/telemetry/msp_shared.c +++ b/src/main/telemetry/msp_shared.c @@ -159,7 +159,7 @@ static void processMspPacket(void) sbufSwitchToReader(&responsePacket.buf, responseBuffer); } -void sendMspErrorResponse(uint8_t error, int16_t cmd) +static void sendMspErrorResponse(uint8_t error, int16_t cmd) { responsePacket.cmd = cmd; responsePacket.result = 0; diff --git a/src/main/telemetry/srxl.c b/src/main/telemetry/srxl.c index 304b670bd1..c349da7e74 100644 --- a/src/main/telemetry/srxl.c +++ b/src/main/telemetry/srxl.c @@ -141,7 +141,7 @@ typedef struct #define STRU_TELE_QOS_EMPTY_FIELDS_COUNT 14 #define STRU_TELE_QOS_EMPTY_FIELDS_VALUE 0xff -bool srxlFrameQos(sbuf_t *dst, timeUs_t currentTimeUs) +static bool srxlFrameQos(sbuf_t *dst, timeUs_t currentTimeUs) { UNUSED(currentTimeUs); @@ -181,7 +181,7 @@ typedef struct #define SPEKTRUM_MIN_RPM 999 // Min RPM to show the user, indicating RPM is really below 999 #define SPEKTRUM_MAX_RPM 60000000 -uint16_t getMotorAveragePeriod(void) +static uint16_t getMotorAveragePeriod(void) { #if defined( USE_ESC_SENSOR_TELEMETRY) || defined( USE_DSHOT_TELEMETRY) @@ -214,7 +214,7 @@ uint16_t getMotorAveragePeriod(void) #endif } -bool srxlFrameRpm(sbuf_t *dst, timeUs_t currentTimeUs) +static bool srxlFrameRpm(sbuf_t *dst, timeUs_t currentTimeUs) { int16_t coreTemp = SPEKTRUM_TEMP_UNUSED; #if defined(USE_ADC_INTERNAL) @@ -290,7 +290,7 @@ typedef struct #define GPS_FLAGS_3D_FIX_BIT 0x20 #define GPS_FLAGS_NEGATIVE_ALT_BIT 0x80 -bool srxlFrameGpsLoc(sbuf_t *dst, timeUs_t currentTimeUs) +static bool srxlFrameGpsLoc(sbuf_t *dst, timeUs_t currentTimeUs) { UNUSED(currentTimeUs); gpsCoordinateDDDMMmmmm_t coordinate; @@ -358,7 +358,7 @@ typedef struct #define STRU_TELE_GPS_STAT_EMPTY_FIELDS_COUNT 6 #define SPEKTRUM_TIME_UNKNOWN 0xFFFFFFFF -bool srxlFrameGpsStat(sbuf_t *dst, timeUs_t currentTimeUs) +static bool srxlFrameGpsStat(sbuf_t *dst, timeUs_t currentTimeUs) { UNUSED(currentTimeUs); uint32_t timeBcd; @@ -431,7 +431,7 @@ typedef struct #define FP_MAH_KEEPALIVE_TIME_OUT 2000000 // 2s -bool srxlFrameFlightPackCurrent(sbuf_t *dst, timeUs_t currentTimeUs) +static bool srxlFrameFlightPackCurrent(sbuf_t *dst, timeUs_t currentTimeUs) { uint16_t amps = getAmperage() / 10; uint16_t mah = getMAhDrawn(); @@ -505,7 +505,7 @@ int spektrumTmTextGenPutChar(uint8_t col, uint8_t row, char c) } //************************************************************************** -bool srxlFrameText(sbuf_t *dst, timeUs_t currentTimeUs) +static bool srxlFrameText(sbuf_t *dst, timeUs_t currentTimeUs) { UNUSED(currentTimeUs); static uint8_t lineNo = 0; diff --git a/src/platform/APM32/adc_apm32f4xx.c b/src/platform/APM32/adc_apm32f4xx.c index 3359b90678..2b93c1eba6 100644 --- a/src/platform/APM32/adc_apm32f4xx.c +++ b/src/platform/APM32/adc_apm32f4xx.c @@ -97,7 +97,7 @@ const adcTagMap_t adcTagMap[] = { { DEFIO_TAG_E__PA7, ADC_DEVICES_12, ADC_CHANNEL_7 }, }; -void adcInitDevice(adcDevice_t *adcdev, int channelCount) +static void adcInitDevice(adcDevice_t *adcdev, int channelCount) { ADC_HandleTypeDef *hadc = &adcdev->ADCHandle; @@ -133,7 +133,7 @@ static adcDevice_t adc; static adcDevice_t adcInternal; static ADC_HandleTypeDef *adcInternalHandle; -void adcInitInternalInjected(adcDevice_t *adcdev) +static void adcInitInternalInjected(adcDevice_t *adcdev) { adcInternalHandle = &adcdev->ADCHandle; diff --git a/src/platform/APM32/dshot_bitbang_ddl.c b/src/platform/APM32/dshot_bitbang_ddl.c index 50d53cf7e8..dc7301c491 100644 --- a/src/platform/APM32/dshot_bitbang_ddl.c +++ b/src/platform/APM32/dshot_bitbang_ddl.c @@ -114,7 +114,7 @@ void bbTimerChannelInit(bbPort_t *bbPort) } #ifdef USE_DMA_REGISTER_CACHE -void bbLoadDMARegs(dmaResource_t *dmaResource, dmaRegCache_t *dmaRegCache) +static void bbLoadDMARegs(dmaResource_t *dmaResource, dmaRegCache_t *dmaRegCache) { ((DMA_ARCH_TYPE *)dmaResource)->SCFG = dmaRegCache->SCFG; ((DMA_ARCH_TYPE *)dmaResource)->FCTRL = dmaRegCache->FCTRL; diff --git a/src/platform/APM32/eint_apm32.c b/src/platform/APM32/eint_apm32.c index fd39b93094..151dd437d2 100644 --- a/src/platform/APM32/eint_apm32.c +++ b/src/platform/APM32/eint_apm32.c @@ -165,7 +165,7 @@ void EXTIDisable(IO_t io) #define EXTI_EVENT_MASK 0xFFFF // first 16 bits only, see also definition of extiChannelRecs. -void EXTI_IRQHandler(uint32_t mask) +static void EXTI_IRQHandler(uint32_t mask) { uint32_t exti_active = (EXTI_REG_IMR & EXTI_REG_PR) & mask; diff --git a/src/platform/APM32/light_ws2811strip_apm32.c b/src/platform/APM32/light_ws2811strip_apm32.c index 676f719470..2ef5cbcb30 100644 --- a/src/platform/APM32/light_ws2811strip_apm32.c +++ b/src/platform/APM32/light_ws2811strip_apm32.c @@ -43,7 +43,7 @@ static IO_t ws2811IO = IO_NONE; static TMR_HandleTypeDef TmrHandle; static uint16_t timerChannel = 0; -FAST_IRQ_HANDLER void WS2811_DMA_IRQHandler(dmaChannelDescriptor_t* descriptor) +static FAST_IRQ_HANDLER void WS2811_DMA_IRQHandler(dmaChannelDescriptor_t* descriptor) { DAL_DMA_IRQHandler(TmrHandle.hdma[descriptor->userParam]); TIM_DMACmd(&TmrHandle, timerChannel, DISABLE); diff --git a/src/platform/APM32/persistent_apm32.c b/src/platform/APM32/persistent_apm32.c index 20a367ad6f..0a9bda61f0 100644 --- a/src/platform/APM32/persistent_apm32.c +++ b/src/platform/APM32/persistent_apm32.c @@ -59,7 +59,7 @@ void persistentObjectWrite(persistentObjectId_e id, uint32_t value) #endif } -void persistentObjectRTCEnable(void) +static void persistentObjectRTCEnable(void) { RTC_HandleTypeDef rtcHandle = { .Instance = RTC }; diff --git a/src/platform/APM32/pwm_output_apm32.c b/src/platform/APM32/pwm_output_apm32.c index a49c58d748..d3de5ba53a 100644 --- a/src/platform/APM32/pwm_output_apm32.c +++ b/src/platform/APM32/pwm_output_apm32.c @@ -92,7 +92,7 @@ static void pwmWriteStandard(uint8_t index, float value) *motors[index].channel.ccr = lrintf((value * motors[index].pulseScale) + motors[index].pulseOffset); } -void pwmShutdownPulsesForAllMotors(void) +static void pwmShutdownPulsesForAllMotors(void) { for (int index = 0; index < pwmMotorCount; index++) { // Set the compare register to 0, which stops the output pulsing if the timer overflows @@ -102,19 +102,19 @@ void pwmShutdownPulsesForAllMotors(void) } } -void pwmDisableMotors(void) +static void pwmDisableMotors(void) { pwmShutdownPulsesForAllMotors(); } static motorVTable_t motorPwmVTable; -bool pwmEnableMotors(void) +static bool pwmEnableMotors(void) { /* check motors can be enabled */ return pwmMotorCount > 0; } -bool pwmIsMotorEnabled(unsigned index) +static bool pwmIsMotorEnabled(unsigned index) { return motors[index].enabled; } diff --git a/src/platform/APM32/startup/system_apm32f4xx.c b/src/platform/APM32/startup/system_apm32f4xx.c index bdebc6cc7d..02a935aa8e 100644 --- a/src/platform/APM32/startup/system_apm32f4xx.c +++ b/src/platform/APM32/startup/system_apm32f4xx.c @@ -343,7 +343,7 @@ void DAL_ErrorHandler(void) } } -void AssertFailedHandler(uint8_t *file, uint32_t line) +LOCAL_UNUSED_FUNCTION static void AssertFailedHandler(uint8_t *file, uint32_t line) { /* When the function is needed, this function could be implemented in the user file diff --git a/src/platform/APM32/timer_apm32.c b/src/platform/APM32/timer_apm32.c index df3aff9adb..b113bc5f07 100644 --- a/src/platform/APM32/timer_apm32.c +++ b/src/platform/APM32/timer_apm32.c @@ -321,7 +321,7 @@ uint8_t timerInputIrq(const TMR_TypeDef *tim) return 0; } -void timerNVICConfigure(uint8_t irq) +static void timerNVICConfigure(uint8_t irq) { DAL_NVIC_SetPriority(irq, NVIC_PRIORITY_BASE(NVIC_PRIO_TIMER), NVIC_PRIORITY_SUB(NVIC_PRIO_TIMER)); DAL_NVIC_EnableIRQ(irq); diff --git a/src/platform/AT32/adc_at32f43x.c b/src/platform/AT32/adc_at32f43x.c index 9cc7ea6225..31b6a45b55 100644 --- a/src/platform/AT32/adc_at32f43x.c +++ b/src/platform/AT32/adc_at32f43x.c @@ -130,7 +130,7 @@ static volatile DMA_DATA uint32_t adcConversionBuffer[ADC_CHANNEL_COUNT]; * @param channelCount how many channels to repeat over * */ -void adcInitDevice(const adc_type *dev, const int channelCount) +static void adcInitDevice(const adc_type *dev, const int channelCount) { adc_base_config_type adc_base_struct; @@ -150,7 +150,7 @@ void adcInitDevice(const adc_type *dev, const int channelCount) * @param tag the ioTag to search for * @return the index in adcTagMap corresponding to the given ioTag or -1 if not found */ -int adcFindTagMapEntry(const ioTag_t tag) +static int adcFindTagMapEntry(const ioTag_t tag) { for (int i = 0; i < ADC_TAG_MAP_COUNT; i++) { if (adcTagMap[i].tag == tag) { @@ -174,7 +174,7 @@ int adcFindTagMapEntry(const ioTag_t tag) * the datasheet when defining those values, so here we have to convert to what's expected in * adcInternalComputeTemperature. */ -void setScalingFactors(void) +static void setScalingFactors(void) { // The expected reading for 1.2V internal reference if external vref+ was 3.3V adcVREFINTCAL = VREFINT_EXPECTED; @@ -448,7 +448,7 @@ void adcInternalStartConversion(void) /** * Reads a given channel from the DMA buffer */ -uint16_t adcInternalRead(int channel) +static uint16_t adcInternalRead(int channel) { const int dmaIndex = adcOperatingConfig[channel].dmaIndex; return adcConversionBuffer[dmaIndex]; diff --git a/src/platform/AT32/dshot_bitbang_stdperiph.c b/src/platform/AT32/dshot_bitbang_stdperiph.c index 927eae2684..972b090fdd 100644 --- a/src/platform/AT32/dshot_bitbang_stdperiph.c +++ b/src/platform/AT32/dshot_bitbang_stdperiph.c @@ -117,7 +117,7 @@ void bbTimerChannelInit(bbPort_t *bbPort) #ifdef USE_DMA_REGISTER_CACHE -void bbLoadDMARegs(dmaResource_t *dmaResource, dmaRegCache_t *dmaRegCache) +static void bbLoadDMARegs(dmaResource_t *dmaResource, dmaRegCache_t *dmaRegCache) { ((DMA_ARCH_TYPE *)dmaResource)->ctrl = dmaRegCache->CCR; ((DMA_ARCH_TYPE *)dmaResource)->dtcnt = dmaRegCache->CNDTR; diff --git a/src/platform/AT32/exti_at32.c b/src/platform/AT32/exti_at32.c index 5bbe0bde50..c0e2d3dafc 100644 --- a/src/platform/AT32/exti_at32.c +++ b/src/platform/AT32/exti_at32.c @@ -155,7 +155,7 @@ void EXTIDisable(IO_t io) #define EXTI_EVENT_MASK 0xFFFF -void EXTI_IRQHandler(uint32_t mask) +static void EXTI_IRQHandler(uint32_t mask) { uint32_t exti_active = (EXTI_REG_IMR & EXTI_REG_PR) & mask; diff --git a/src/platform/AT32/persistent_at32bsp.c b/src/platform/AT32/persistent_at32bsp.c index b79c5b67ad..691bc564cf 100644 --- a/src/platform/AT32/persistent_at32bsp.c +++ b/src/platform/AT32/persistent_at32bsp.c @@ -45,7 +45,7 @@ void persistentObjectWrite(persistentObjectId_e id, uint32_t value) ertc_write_protect_enable(); } -void persistentObjectRTCEnable(void) +static void persistentObjectRTCEnable(void) { crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); pwc_battery_powered_domain_access(TRUE); diff --git a/src/platform/AT32/pwm_output_at32bsp.c b/src/platform/AT32/pwm_output_at32bsp.c index 382dbd0925..8ebc593340 100644 --- a/src/platform/AT32/pwm_output_at32bsp.c +++ b/src/platform/AT32/pwm_output_at32bsp.c @@ -83,7 +83,7 @@ static void pwmWriteStandard(uint8_t index, float value) *motors[index].channel.ccr = lrintf((value * motors[index].pulseScale) + motors[index].pulseOffset); } -void pwmShutdownPulsesForAllMotors(void) +static void pwmShutdownPulsesForAllMotors(void) { for (int index = 0; index < pwmMotorCount; index++) { // Set the compare register to 0, which stops the output pulsing if the timer overflows @@ -93,19 +93,19 @@ void pwmShutdownPulsesForAllMotors(void) } } -void pwmDisableMotors(void) +static void pwmDisableMotors(void) { pwmShutdownPulsesForAllMotors(); } static motorVTable_t motorPwmVTable; -bool pwmEnableMotors(void) +static bool pwmEnableMotors(void) { /* check motors can be enabled */ return (pwmMotorDevice->vTable); } -bool pwmIsMotorEnabled(unsigned index) +static bool pwmIsMotorEnabled(unsigned index) { return motors[index].enabled; } diff --git a/src/platform/AT32/pwm_output_dshot.c b/src/platform/AT32/pwm_output_dshot.c index 57b88f8efd..2d4722da04 100644 --- a/src/platform/AT32/pwm_output_dshot.c +++ b/src/platform/AT32/pwm_output_dshot.c @@ -57,7 +57,7 @@ * * @see TIM_CH_TO_SELCHANNEL macro */ -tmr_channel_select_type toCHSelectType(const uint8_t bfChannel, const bool useNChannel) +static tmr_channel_select_type toCHSelectType(const uint8_t bfChannel, const bool useNChannel) { tmr_channel_select_type result = TMR_SELECT_CHANNEL_1; // XXX I don't like using ch 1 as a default result, but what to do? if (useNChannel) diff --git a/src/platform/AT32/serial_usb_vcp_at32f4.c b/src/platform/AT32/serial_usb_vcp_at32f4.c index f0fc0ce44d..0cb3288b71 100644 --- a/src/platform/AT32/serial_usb_vcp_at32f4.c +++ b/src/platform/AT32/serial_usb_vcp_at32f4.c @@ -93,7 +93,7 @@ void CDC_SetCtrlLineStateCb(void (*cb)(void *context, uint16_t ctrlLineState), v ctrlLineStateCb = cb; } -void usb_clock48m_select(usb_clk48_s clk_s) +static void usb_clock48m_select(usb_clk48_s clk_s) { if(clk_s == USB_CLK_HICK) { @@ -174,7 +174,7 @@ void usb_clock48m_select(usb_clk48_s clk_s) } } -void usb_gpio_config(void) +static void usb_gpio_config(void) { gpio_init_type gpio_init_struct; @@ -256,7 +256,7 @@ uint32_t CDC_Send_DATA(const uint8_t *ptrBuffer, uint32_t sendLength) return sendLength; } -void TxTimerConfig(void) +static void TxTimerConfig(void) { tmr_base_init(usbTxTmr, (CDC_POLLING_INTERVAL - 1), ((system_core_clock)/1000 - 1)); tmr_clock_source_div_set(usbTxTmr, TMR_CLOCK_DIV1); diff --git a/src/platform/AT32/system_at32f43x.c b/src/platform/AT32/system_at32f43x.c index 8f4f7d76af..ccde9850f6 100644 --- a/src/platform/AT32/system_at32f43x.c +++ b/src/platform/AT32/system_at32f43x.c @@ -122,7 +122,7 @@ typedef struct isrVector_s { resetHandler_t *resetHandler; } isrVector_t; -void checkForBootLoaderRequest(void) +static void checkForBootLoaderRequest(void) { volatile uint32_t bootloaderRequest = persistentObjectRead(PERSISTENT_OBJECT_RESET_REASON); diff --git a/src/platform/AT32/timer_at32bsp.c b/src/platform/AT32/timer_at32bsp.c index 46efb390ce..f76a417152 100644 --- a/src/platform/AT32/timer_at32bsp.c +++ b/src/platform/AT32/timer_at32bsp.c @@ -321,7 +321,7 @@ uint8_t timerInputIrq(const tmr_type *tim) return 0; } -void timerNVICConfigure(uint8_t irq) +static void timerNVICConfigure(uint8_t irq) { nvic_irq_enable(irq,NVIC_PRIORITY_BASE(NVIC_PRIO_TIMER),NVIC_PRIORITY_SUB(NVIC_PRIO_TIMER)); } diff --git a/src/platform/AT32/usb_msc_at32f43x.c b/src/platform/AT32/usb_msc_at32f43x.c index 007dd07b0b..fefe8049b1 100644 --- a/src/platform/AT32/usb_msc_at32f43x.c +++ b/src/platform/AT32/usb_msc_at32f43x.c @@ -55,12 +55,13 @@ #include "usbd_int.h" #include "msc_class.h" #include "msc_desc.h" +#include "msc_diskio.h" #include "drivers/usb_io.h" extern otg_core_type otg_core_struct; -void msc_usb_gpio_config(void) +static void msc_usb_gpio_config(void) { gpio_init_type gpio_init_struct; @@ -95,7 +96,7 @@ void msc_usb_gpio_config(void) } -void msc_usb_clock48m_select(usb_clk48_s clk_s) +static void msc_usb_clock48m_select(usb_clk48_s clk_s) { if(clk_s == USB_CLK_HICK) { crm_usb_clock_source_select(CRM_USB_CLOCK_SOURCE_HICK); diff --git a/src/platform/SIMULATOR/sitl.c b/src/platform/SIMULATOR/sitl.c index f4c9980d63..bd52fe2564 100644 --- a/src/platform/SIMULATOR/sitl.c +++ b/src/platform/SIMULATOR/sitl.c @@ -30,12 +30,16 @@ #include "common/maths.h" +#include "build/debug.h" + +#include "drivers/adc_impl.h" #include "drivers/io.h" #include "drivers/dma.h" #include "drivers/motor_impl.h" #include "drivers/serial.h" #include "drivers/serial_tcp.h" #include "drivers/system.h" +#include "drivers/time.h" #include "drivers/pwm_output.h" #include "drivers/light_led.h" @@ -49,6 +53,8 @@ #include "config/feature.h" #include "config/config.h" #include "config/config_streamer.h" +#include "config/config_streamer_impl.h" +#include "config/config_eeprom_impl.h" #include "scheduler/scheduler.h" @@ -56,6 +62,7 @@ #include "pg/motor.h" #include "rx/rx.h" +#include "rx/spektrum.h" #include "io/gps.h" #include "io/gps_virtual.h" @@ -110,12 +117,12 @@ int lockMainPID(void) #define ACC_SCALE (256 / 9.80665) #define GYRO_SCALE (16.4) -void sendMotorUpdate(void) +static void sendMotorUpdate(void) { udpSend(&pwmLink, &pwmPkt, sizeof(servo_packet)); } -void updateState(const fdm_packet* pkt) +static void updateState(const fdm_packet* pkt) { static double last_timestamp = 0; // in seconds static uint64_t last_realtime = 0; // in uS @@ -469,7 +476,7 @@ uint32_t getCycleCounter(void) return (uint32_t) (micros64() & 0xFFFFFFFF); } -void microsleep(uint32_t usec) +static void microsleep(uint32_t usec) { struct timespec ts; ts.tv_sec = 0; @@ -590,7 +597,7 @@ static void pwmShutdownPulsesForAllMotors(void) pwmMotorDevice.enabled = false; } -bool pwmIsMotorEnabled(unsigned index) +static bool pwmIsMotorEnabled(unsigned index) { return motors[index].enabled; } diff --git a/src/platform/STM32/adc_stm32f4xx.c b/src/platform/STM32/adc_stm32f4xx.c index 0ce2a8e075..1a9de8f69d 100644 --- a/src/platform/STM32/adc_stm32f4xx.c +++ b/src/platform/STM32/adc_stm32f4xx.c @@ -126,7 +126,7 @@ const adcTagMap_t adcTagMap[] = { #define TS_CAL1_ADDR 0x1FFF7A2C #define TS_CAL2_ADDR 0x1FFF7A2E -void adcInitDevice(ADC_TypeDef *adcdev, int channelCount) +static void adcInitDevice(ADC_TypeDef *adcdev, int channelCount) { ADC_InitTypeDef ADC_InitStructure; @@ -150,7 +150,7 @@ void adcInitDevice(ADC_TypeDef *adcdev, int channelCount) } #ifdef USE_ADC_INTERNAL -void adcInitInternalInjected(const adcConfig_t *config) +static void adcInitInternalInjected(const adcConfig_t *config) { ADC_TempSensorVrefintCmd(ENABLE); ADC_InjectedDiscModeCmd(ADC1, DISABLE); diff --git a/src/platform/STM32/adc_stm32f7xx.c b/src/platform/STM32/adc_stm32f7xx.c index b26e0295bc..f631543c47 100644 --- a/src/platform/STM32/adc_stm32f7xx.c +++ b/src/platform/STM32/adc_stm32f7xx.c @@ -95,7 +95,7 @@ const adcTagMap_t adcTagMap[] = { { DEFIO_TAG_E__PA7, ADC_DEVICES_12, ADC_CHANNEL_7 }, }; -void adcInitDevice(adcDevice_t *adcdev, int channelCount) +static void adcInitDevice(adcDevice_t *adcdev, int channelCount) { adcdev->ADCHandle.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV8; adcdev->ADCHandle.Init.ContinuousConvMode = ENABLE; @@ -130,7 +130,7 @@ static adcDevice_t adc; static adcDevice_t adcInternal; static ADC_HandleTypeDef *adcInternalHandle; -void adcInitInternalInjected(adcDevice_t *adcdev) +static void adcInitInternalInjected(adcDevice_t *adcdev) { adcInternalHandle = &adcdev->ADCHandle; diff --git a/src/platform/STM32/adc_stm32g4xx.c b/src/platform/STM32/adc_stm32g4xx.c index 34aa689edf..26e6ac9e6b 100644 --- a/src/platform/STM32/adc_stm32g4xx.c +++ b/src/platform/STM32/adc_stm32g4xx.c @@ -199,7 +199,7 @@ static void handleError(void) // Temperature sensor has minimum sample time of 9us. // With prescaler = 4 at 200MHz (AHB1), fADC = 50MHz (tcycle = 0.02us), 9us = 450cycles < 810 -void adcInitDevice(adcDevice_t *adcdev, int channelCount) +static void adcInitDevice(adcDevice_t *adcdev, int channelCount) { ADC_HandleTypeDef *hadc = &adcdev->ADCHandle; // For clarity @@ -232,7 +232,7 @@ void adcInitDevice(adcDevice_t *adcdev, int channelCount) } } -int adcFindTagMapEntry(ioTag_t tag) +static int adcFindTagMapEntry(ioTag_t tag) { for (int i = 0; i < ADC_TAG_MAP_COUNT; i++) { if (adcTagMap[i].tag == tag) { @@ -242,7 +242,7 @@ int adcFindTagMapEntry(ioTag_t tag) return -1; } -void adcInitCalibrationValues(void) +static void adcInitCalibrationValues(void) { adcVREFINTCAL = *(uint16_t *)VREFINT_CAL_ADDR; adcTSCAL1 = *TEMPSENSOR_CAL1_ADDR; @@ -504,7 +504,7 @@ void adcInternalStartConversion(void) return; } -uint16_t adcInternalRead(int channel) +static uint16_t adcInternalRead(int channel) { int dmaIndex = adcOperatingConfig[channel].dmaIndex; diff --git a/src/platform/STM32/adc_stm32h7xx.c b/src/platform/STM32/adc_stm32h7xx.c index 8f17237e55..643fff600e 100644 --- a/src/platform/STM32/adc_stm32h7xx.c +++ b/src/platform/STM32/adc_stm32h7xx.c @@ -192,7 +192,7 @@ static void errorHandler(void) { while (1) { } } // Temperature sensor has minimum sample time of 9us. // With prescaler = 4 at 200MHz (AHB1), fADC = 50MHz (tcycle = 0.02us), 9us = 450cycles < 810 -void adcInitDevice(adcDevice_t *adcdev, int channelCount) +static void adcInitDevice(adcDevice_t *adcdev, int channelCount) { ADC_HandleTypeDef *hadc = &adcdev->ADCHandle; // For clarity @@ -240,7 +240,7 @@ void adcInitDevice(adcDevice_t *adcdev, int channelCount) } } -int adcFindTagMapEntry(ioTag_t tag) +static int adcFindTagMapEntry(ioTag_t tag) { for (int i = 0; i < ADC_TAG_MAP_COUNT; i++) { if (adcTagMap[i].tag == tag) { @@ -260,7 +260,7 @@ int adcFindTagMapEntry(ioTag_t tag) #error Unknown MCU #endif -void adcInitCalibrationValues(void) +static void adcInitCalibrationValues(void) { adcVREFINTCAL = *VREFINT_CAL_ADDR >> VREFINT_CAL_SHIFT; adcTSCAL1 = *TEMPSENSOR_CAL1_ADDR >> VREFINT_CAL_SHIFT; @@ -560,7 +560,7 @@ void adcInternalStartConversion(void) return; } -uint16_t adcInternalRead(int channel) +static uint16_t adcInternalRead(int channel) { int dmaIndex = adcOperatingConfig[channel].dmaIndex; diff --git a/src/platform/STM32/bus_i2c_stm32f4xx.c b/src/platform/STM32/bus_i2c_stm32f4xx.c index 26ea2e5d96..34a0c02802 100644 --- a/src/platform/STM32/bus_i2c_stm32f4xx.c +++ b/src/platform/STM32/bus_i2c_stm32f4xx.c @@ -212,7 +212,7 @@ bool i2cBusy(I2CDevice device, bool *error) return state->busy; } -bool i2cWait(I2CDevice device) +static bool i2cWait(I2CDevice device) { i2cState_t *state = &i2cDevice[device].state; timeUs_t timeoutStartUs = microsISR(); diff --git a/src/platform/STM32/bus_octospi_stm32h7xx.c b/src/platform/STM32/bus_octospi_stm32h7xx.c index 484283f45b..ffd803f49f 100644 --- a/src/platform/STM32/bus_octospi_stm32h7xx.c +++ b/src/platform/STM32/bus_octospi_stm32h7xx.c @@ -113,7 +113,7 @@ #define OSPI_SIOO_INST_EVERY_CMD ((uint32_t)0x00000000U) #define OSPI_SIOO_INST_ONLY_FIRST_CMD ((uint32_t)OCTOSPI_CCR_SIOO) -MMFLASH_CODE_NOINLINE static void Error_Handler(void) { +static MMFLASH_CODE_NOINLINE void Error_Handler(void) { while (1) { NOOP; } @@ -303,7 +303,7 @@ MMFLASH_CODE_NOINLINE static ErrorStatus octoSpiConfigureCommand(OCTOSPI_TypeDef return status; } -MMFLASH_CODE_NOINLINE ErrorStatus octoSpiCommand(OCTOSPI_TypeDef *instance, OSPI_Command_t *cmd) +static MMFLASH_CODE_NOINLINE ErrorStatus octoSpiCommand(OCTOSPI_TypeDef *instance, OSPI_Command_t *cmd) { octoSpiWaitStatusFlags(instance, OCTOSPI_SR_BUSY, RESET); @@ -325,7 +325,7 @@ MMFLASH_CODE_NOINLINE ErrorStatus octoSpiCommand(OCTOSPI_TypeDef *instance, OSPI * * Call optoSpiCommand first to configure the transaction stages. */ -MMFLASH_CODE_NOINLINE ErrorStatus octoSpiTransmit(OCTOSPI_TypeDef *instance, uint8_t *data) +static MMFLASH_CODE_NOINLINE ErrorStatus octoSpiTransmit(OCTOSPI_TypeDef *instance, uint8_t *data) { if (data == NULL) { return ERROR; @@ -357,7 +357,7 @@ MMFLASH_CODE_NOINLINE ErrorStatus octoSpiTransmit(OCTOSPI_TypeDef *instance, uin * * Call optoSpiCommand first to configure the transaction stages. */ -MMFLASH_CODE_NOINLINE ErrorStatus octoSpiReceive(OCTOSPI_TypeDef *instance, uint8_t *data) +static MMFLASH_CODE_NOINLINE ErrorStatus octoSpiReceive(OCTOSPI_TypeDef *instance, uint8_t *data) { if (data == NULL) { return ERROR; @@ -415,7 +415,7 @@ typedef struct octoSpiMemoryMappedModeConfigurationRegisterBackup_t ospiMMMCRBackups[OCTOSPI_INTERFACE_COUNT]; -void octoSpiBackupMemoryMappedModeConfiguration(OCTOSPI_TypeDef *instance) +static void octoSpiBackupMemoryMappedModeConfiguration(OCTOSPI_TypeDef *instance) { OCTOSPIDevice device = octoSpiDeviceByInstance(instance); if (device == OCTOSPIINVALID) { @@ -435,7 +435,7 @@ void octoSpiBackupMemoryMappedModeConfiguration(OCTOSPI_TypeDef *instance) ospiMMMCRBackup->ABR = instance->ABR; } -MMFLASH_CODE_NOINLINE void octoSpiRestoreMemoryMappedModeConfiguration(OCTOSPI_TypeDef *instance) +static MMFLASH_CODE_NOINLINE void octoSpiRestoreMemoryMappedModeConfiguration(OCTOSPI_TypeDef *instance) { OCTOSPIDevice device = octoSpiDeviceByInstance(instance); if (device == OCTOSPIINVALID) { @@ -516,7 +516,7 @@ MMFLASH_CODE_NOINLINE void octoSpiEnableMemoryMappedMode(OCTOSPI_TypeDef *instan octoSpiRestoreMemoryMappedModeConfiguration(instance); } -MMFLASH_CODE_NOINLINE void octoSpiTestEnableDisableMemoryMappedMode(octoSpiDevice_t *octoSpi) +static MMFLASH_CODE_NOINLINE void octoSpiTestEnableDisableMemoryMappedMode(octoSpiDevice_t *octoSpi) { OCTOSPI_TypeDef *instance = octoSpi->dev; diff --git a/src/platform/STM32/bus_quadspi_hal.c b/src/platform/STM32/bus_quadspi_hal.c index 5c93f1f3a6..bc119ee796 100644 --- a/src/platform/STM32/bus_quadspi_hal.c +++ b/src/platform/STM32/bus_quadspi_hal.c @@ -37,7 +37,7 @@ #include "pg/bus_quadspi.h" -static void Error_Handler(void) { while (1) { } } +static void Error_Handler(void) { while (1); } void quadSpiInitDevice(QUADSPIDevice device) { @@ -134,7 +134,7 @@ static uint32_t quadSpi_addressSizeFromValue(uint8_t addressSize) /** * Return true if the bus is currently in the middle of a transmission. */ -bool quadSpiIsBusBusy(QUADSPI_TypeDef *instance) +LOCAL_UNUSED_FUNCTION static bool quadSpiIsBusBusy(QUADSPI_TypeDef *instance) { QUADSPIDevice device = quadSpiDeviceByInstance(instance); if(quadSpiDevice[device].hquadSpi.State == HAL_QSPI_STATE_BUSY) @@ -145,7 +145,7 @@ bool quadSpiIsBusBusy(QUADSPI_TypeDef *instance) #define QUADSPI_DEFAULT_TIMEOUT 10 -void quadSpiSelectDevice(QUADSPI_TypeDef *instance) +static void quadSpiSelectDevice(QUADSPI_TypeDef *instance) { QUADSPIDevice device = quadSpiDeviceByInstance(instance); @@ -174,7 +174,7 @@ void quadSpiSelectDevice(QUADSPI_TypeDef *instance) } } -void quadSpiDeselectDevice(QUADSPI_TypeDef *instance) +static void quadSpiDeselectDevice(QUADSPI_TypeDef *instance) { QUADSPIDevice device = quadSpiDeviceByInstance(instance); diff --git a/src/platform/STM32/dma_stm32f4xx.c b/src/platform/STM32/dma_stm32f4xx.c index 97311e2c06..6f948a039e 100644 --- a/src/platform/STM32/dma_stm32f4xx.c +++ b/src/platform/STM32/dma_stm32f4xx.c @@ -82,7 +82,7 @@ void dmaEnable(dmaIdentifier_e identifier) #define RETURN_TCIF_FLAG(s, n) if (s == DMA1_Stream ## n || s == DMA2_Stream ## n) return DMA_IT_TCIF ## n -uint32_t dmaFlag_IT_TCIF(const dmaResource_t *stream) +static uint32_t dmaFlag_IT_TCIF(const dmaResource_t *stream) { RETURN_TCIF_FLAG((DMA_ARCH_TYPE *)stream, 0); RETURN_TCIF_FLAG((DMA_ARCH_TYPE *)stream, 1); diff --git a/src/platform/STM32/dshot_bitbang_ll.c b/src/platform/STM32/dshot_bitbang_ll.c index dffd0ed77c..8a39c2d3b8 100644 --- a/src/platform/STM32/dshot_bitbang_ll.c +++ b/src/platform/STM32/dshot_bitbang_ll.c @@ -124,7 +124,7 @@ void bbTimerChannelInit(bbPort_t *bbPort) } #ifdef USE_DMA_REGISTER_CACHE -void bbLoadDMARegs(dmaResource_t *dmaResource, dmaRegCache_t *dmaRegCache) +static void bbLoadDMARegs(dmaResource_t *dmaResource, dmaRegCache_t *dmaRegCache) { #if defined(STM32F7) || defined(STM32H7) ((DMA_ARCH_TYPE *)dmaResource)->CR = dmaRegCache->CR; diff --git a/src/platform/STM32/dshot_bitbang_stdperiph.c b/src/platform/STM32/dshot_bitbang_stdperiph.c index 122f2f5718..32fdffa28a 100644 --- a/src/platform/STM32/dshot_bitbang_stdperiph.c +++ b/src/platform/STM32/dshot_bitbang_stdperiph.c @@ -107,7 +107,7 @@ void bbTimerChannelInit(bbPort_t *bbPort) #ifdef USE_DMA_REGISTER_CACHE -void bbLoadDMARegs(dmaResource_t *dmaResource, dmaRegCache_t *dmaRegCache) +static void bbLoadDMARegs(dmaResource_t *dmaResource, dmaRegCache_t *dmaRegCache) { ((DMA_Stream_TypeDef *)dmaResource)->CR = dmaRegCache->CR; ((DMA_Stream_TypeDef *)dmaResource)->FCR = dmaRegCache->FCR; diff --git a/src/platform/STM32/exti.c b/src/platform/STM32/exti.c index 8dbf14ad84..3f76ab8987 100644 --- a/src/platform/STM32/exti.c +++ b/src/platform/STM32/exti.c @@ -205,7 +205,7 @@ void EXTIDisable(IO_t io) #define EXTI_EVENT_MASK 0xFFFF // first 16 bits only, see also definition of extiChannelRecs. -void EXTI_IRQHandler(uint32_t mask) +static void EXTI_IRQHandler(uint32_t mask) { uint32_t exti_active = (EXTI_REG_IMR & EXTI_REG_PR) & mask; diff --git a/src/platform/STM32/light_ws2811strip_hal.c b/src/platform/STM32/light_ws2811strip_hal.c index 6a654f4ea6..bdb9487851 100644 --- a/src/platform/STM32/light_ws2811strip_hal.c +++ b/src/platform/STM32/light_ws2811strip_hal.c @@ -42,7 +42,7 @@ static IO_t ws2811IO = IO_NONE; static TIM_HandleTypeDef TimHandle; static uint16_t timerChannel = 0; -FAST_IRQ_HANDLER void WS2811_DMA_IRQHandler(dmaChannelDescriptor_t* descriptor) +static FAST_IRQ_HANDLER void WS2811_DMA_IRQHandler(dmaChannelDescriptor_t* descriptor) { HAL_DMA_IRQHandler(TimHandle.hdma[descriptor->userParam]); TIM_DMACmd(&TimHandle, timerChannel, DISABLE); diff --git a/src/platform/STM32/pwm_output_hw.c b/src/platform/STM32/pwm_output_hw.c index 67284840cb..99a2a3ce69 100644 --- a/src/platform/STM32/pwm_output_hw.c +++ b/src/platform/STM32/pwm_output_hw.c @@ -113,7 +113,7 @@ static void pwmWriteStandard(uint8_t index, float value) *motors[index].channel.ccr = lrintf((value * motors[index].pulseScale) + motors[index].pulseOffset); } -void pwmShutdownPulsesForAllMotors(void) +static void pwmShutdownPulsesForAllMotors(void) { for (int index = 0; pwmMotorCount; index++) { // Set the compare register to 0, which stops the output pulsing if the timer overflows @@ -123,18 +123,18 @@ void pwmShutdownPulsesForAllMotors(void) } } -void pwmDisableMotors(void) +static void pwmDisableMotors(void) { pwmShutdownPulsesForAllMotors(); } -bool pwmEnableMotors(void) +static bool pwmEnableMotors(void) { /* check motors can be enabled */ return pwmMotorCount > 0; } -bool pwmIsMotorEnabled(unsigned index) +static bool pwmIsMotorEnabled(unsigned index) { return motors[index].enabled; } diff --git a/src/platform/STM32/sdio_f4xx.c b/src/platform/STM32/sdio_f4xx.c index 6f9b7cd1fe..6b944a020b 100644 --- a/src/platform/STM32/sdio_f4xx.c +++ b/src/platform/STM32/sdio_f4xx.c @@ -1113,7 +1113,7 @@ static SD_Error_t SD_WideBusOperationConfig(uint32_t WideMode) * This API must be used after "Transfer State" * @retval SD Card error state */ -SD_Error_t SD_HighSpeed(void) +static SD_Error_t SD_HighSpeed(void) { SD_Error_t ErrorState; uint8_t SD_hs[64] = {0}; @@ -1192,7 +1192,7 @@ SD_Error_t SD_HighSpeed(void) * @brief Gets the current card's data status. * @retval Data Transfer state */ -SD_Error_t SD_GetStatus(void) +static SD_Error_t SD_GetStatus(void) { SD_Error_t ErrorState; uint32_t Response1; @@ -1697,7 +1697,7 @@ SD_Error_t SD_Init(void) /** * @brief This function handles SD card interrupt request. */ -void SDIO_IRQHandler(void) +LOCAL_UNUSED_FUNCTION static void SDIO_IRQHandler(void) { // Check for SDIO interrupt flags if ((SDIO->STA & SDIO_STA_DATAEND) != 0) { diff --git a/src/platform/STM32/sdio_f7xx.c b/src/platform/STM32/sdio_f7xx.c index d3edd83df8..2f1bc62b5c 100644 --- a/src/platform/STM32/sdio_f7xx.c +++ b/src/platform/STM32/sdio_f7xx.c @@ -1178,7 +1178,7 @@ SD_Error_t HAL_SD_HighSpeed(void) * @brief Gets the current card's data status. * @retval Data Transfer state */ -SD_Error_t SD_GetStatus(void) +static SD_Error_t SD_GetStatus(void) { SD_Error_t ErrorState; uint32_t Response1; diff --git a/src/platform/STM32/startup/system_stm32f4xx.c b/src/platform/STM32/startup/system_stm32f4xx.c index dc8306d008..59283846c4 100644 --- a/src/platform/STM32/startup/system_stm32f4xx.c +++ b/src/platform/STM32/startup/system_stm32f4xx.c @@ -460,7 +460,7 @@ static const pllConfig_t overclockLevels[] = { #define PLL_R 7 // PLL_R output is not used, can be any descent number #endif -void SystemInitPLLParameters(void) +static void SystemInitPLLParameters(void) { /* PLL setting for overclocking */ diff --git a/src/platform/STM32/startup/system_stm32h7xx.c b/src/platform/STM32/startup/system_stm32h7xx.c index 312f3569aa..809bbea326 100644 --- a/src/platform/STM32/startup/system_stm32h7xx.c +++ b/src/platform/STM32/startup/system_stm32h7xx.c @@ -76,6 +76,8 @@ #include "drivers/memprot.h" #include "drivers/system.h" +#include "system_stm32f7xx.h" + #define HSI_FREQ ((uint32_t)64000000) // Frequency of HSI is 64Mhz on all H7 variants. // If `HSE_VALUE` isn't specified, use HSI. This allows HSI to be selected as the PLL source @@ -176,7 +178,7 @@ static void ErrorHandler(void) while (1); } -void HandleStuckSysTick(void) +static void HandleStuckSysTick(void) { uint32_t tickStart = HAL_GetTick(); uint32_t tickEnd = 0; @@ -707,7 +709,7 @@ void CRS_IRQHandler(void) } #endif -void initialiseD2MemorySections(void) +static void initialiseD2MemorySections(void) { /* Load DMA_DATA variable intializers into D2 RAM */ extern uint8_t _sdmaram_bss; diff --git a/src/platform/STM32/system_stm32g4xx.c b/src/platform/STM32/system_stm32g4xx.c index 313ff9dcdc..b05e6f66d7 100644 --- a/src/platform/STM32/system_stm32g4xx.c +++ b/src/platform/STM32/system_stm32g4xx.c @@ -110,7 +110,7 @@ typedef struct isrVector_s { resetHandler_t *resetHandler; } isrVector_t; -void systemJumpToBootloader(void) +static void systemJumpToBootloader(void) { //DeInit all used peripherals HAL_RCC_DeInit(); diff --git a/src/platform/STM32/system_stm32h7xx.c b/src/platform/STM32/system_stm32h7xx.c index 29ae3bef79..69871c1695 100644 --- a/src/platform/STM32/system_stm32h7xx.c +++ b/src/platform/STM32/system_stm32h7xx.c @@ -30,7 +30,7 @@ void SystemClock_Config(void); -void configureMasterClockOutputs(void) +LOCAL_UNUSED_FUNCTION static void configureMasterClockOutputs(void) { // Initialize pins for MCO1 and MCO2 for clock testing/verification @@ -180,7 +180,7 @@ void systemResetToBootloader(bootloaderRequestType_e requestType) typedef void *(*bootJumpPtr)(void); -void systemJumpToBootloader(void) +static void systemJumpToBootloader(void) { __SYSCFG_CLK_ENABLE(); diff --git a/src/platform/STM32/timer_hal.c b/src/platform/STM32/timer_hal.c index 242ac89141..9f68624eca 100644 --- a/src/platform/STM32/timer_hal.c +++ b/src/platform/STM32/timer_hal.c @@ -329,7 +329,7 @@ uint8_t timerInputIrq(const TIM_TypeDef *tim) return 0; } -void timerNVICConfigure(uint8_t irq) +static void timerNVICConfigure(uint8_t irq) { HAL_NVIC_SetPriority(irq, NVIC_PRIORITY_BASE(NVIC_PRIO_TIMER), NVIC_PRIORITY_SUB(NVIC_PRIO_TIMER)); HAL_NVIC_EnableIRQ(irq); diff --git a/src/platform/STM32/timer_stdperiph.c b/src/platform/STM32/timer_stdperiph.c index 33f1a27acd..f12fd5547b 100644 --- a/src/platform/STM32/timer_stdperiph.c +++ b/src/platform/STM32/timer_stdperiph.c @@ -310,7 +310,7 @@ uint8_t timerInputIrq(const TIM_TypeDef *tim) return 0; } -void timerNVICConfigure(uint8_t irq) +static void timerNVICConfigure(uint8_t irq) { NVIC_InitTypeDef NVIC_InitStructure; diff --git a/src/platform/STM32/vcp_hal/usbd_cdc_hid.c b/src/platform/STM32/vcp_hal/usbd_cdc_hid.c index 4727b4a29f..fd17d8ea19 100644 --- a/src/platform/STM32/vcp_hal/usbd_cdc_hid.c +++ b/src/platform/STM32/vcp_hal/usbd_cdc_hid.c @@ -37,6 +37,8 @@ #include "usbd_hid.h" #include "vcp_hal/usbd_cdc_interface.h" +#include "io/usb_cdc_hid.h" + #define USB_HID_CDC_CONFIG_DESC_SIZ (USB_HID_CONFIG_DESC_SIZ - 9 + USB_CDC_CONFIG_DESC_SIZ + 8) #define HID_INTERFACE 0x0 diff --git a/src/platform/STM32/vcp_hal/usbd_conf_stm32g4xx.c b/src/platform/STM32/vcp_hal/usbd_conf_stm32g4xx.c index 3e139a813e..d10ea4f3bd 100644 --- a/src/platform/STM32/vcp_hal/usbd_conf_stm32g4xx.c +++ b/src/platform/STM32/vcp_hal/usbd_conf_stm32g4xx.c @@ -714,7 +714,7 @@ void USBD_LL_Delay(uint32_t Delay) * @param size: Size of allocated memory * @retval None */ -void *USBD_static_malloc(uint32_t size) +LOCAL_UNUSED_FUNCTION static void *USBD_static_malloc(uint32_t size) { UNUSED(size); @@ -727,7 +727,7 @@ void *USBD_static_malloc(uint32_t size) * @param p: Pointer to allocated memory address * @retval None */ -void USBD_static_free(void *p) +LOCAL_UNUSED_FUNCTION static void USBD_static_free(void *p) { UNUSED(p); } diff --git a/src/platform/STM32/vcpf4/usb_bsp.c b/src/platform/STM32/vcpf4/usb_bsp.c index 28da4eff32..af871b15d3 100644 --- a/src/platform/STM32/vcpf4/usb_bsp.c +++ b/src/platform/STM32/vcpf4/usb_bsp.c @@ -30,12 +30,12 @@ #include "drivers/nvic.h" #include "drivers/io.h" -void USB_OTG_BSP_ConfigVBUS(USB_OTG_CORE_HANDLE *pdev) +LOCAL_UNUSED_FUNCTION static void USB_OTG_BSP_ConfigVBUS(USB_OTG_CORE_HANDLE *pdev) { (void)pdev; } -void USB_OTG_BSP_DriveVBUS(USB_OTG_CORE_HANDLE *pdev,uint8_t state) +LOCAL_UNUSED_FUNCTION static void USB_OTG_BSP_DriveVBUS(USB_OTG_CORE_HANDLE *pdev,uint8_t state) { (void)pdev; (void)state; diff --git a/src/platform/STM32/vcpf4/usb_cdc_hid.c b/src/platform/STM32/vcpf4/usb_cdc_hid.c index 8c4b604593..637260fc4b 100644 --- a/src/platform/STM32/vcpf4/usb_cdc_hid.c +++ b/src/platform/STM32/vcpf4/usb_cdc_hid.c @@ -25,6 +25,8 @@ #ifdef USE_USB_CDC_HID #include "vcpf4/usbd_cdc_vcp.h" +#include "io/usb_cdc_hid.h" + #include "usbd_hid_core.h" void sendReport(uint8_t *report, uint8_t len) diff --git a/src/platform/STM32/vcpf4/usbd_cdc_vcp.c b/src/platform/STM32/vcpf4/usbd_cdc_vcp.c index d3c641e020..d27b9589af 100644 --- a/src/platform/STM32/vcpf4/usbd_cdc_vcp.c +++ b/src/platform/STM32/vcpf4/usbd_cdc_vcp.c @@ -101,7 +101,7 @@ static uint16_t VCP_DeInit(void) return USBD_OK; } -void ust_cpy(LINE_CODING* plc2, const LINE_CODING* plc1) +static void ust_cpy(LINE_CODING* plc2, const LINE_CODING* plc1) { plc2->bitrate = plc1->bitrate; plc2->format = plc1->format; diff --git a/src/platform/common/stm32/config_flash.c b/src/platform/common/stm32/config_flash.c index c94fb082b1..4e79ef7a4f 100644 --- a/src/platform/common/stm32/config_flash.c +++ b/src/platform/common/stm32/config_flash.c @@ -24,6 +24,7 @@ #include "platform.h" #include "drivers/system.h" #include "config/config_streamer.h" +#include "config/config_streamer_impl.h" #if defined(CONFIG_IN_FLASH) diff --git a/src/platform/common/stm32/system.c b/src/platform/common/stm32/system.c index d21e0ee956..aa663e2950 100644 --- a/src/platform/common/stm32/system.c +++ b/src/platform/common/stm32/system.c @@ -31,6 +31,7 @@ #include "drivers/nvic.h" #include "drivers/resource.h" #include "drivers/sound_beeper.h" +#include "drivers/time.h" #include "drivers/system.h" From cd84e10fa5e75494d8a29330ed488fd32c9810f4 Mon Sep 17 00:00:00 2001 From: Jay Blackman Date: Thu, 30 Jan 2025 00:49:11 +1100 Subject: [PATCH 094/244] FIX: Serial ESC communication when using digital protocols (#14214) * FIX: Serial ESC communication when using digital protocols * Fix error following rebase, and amending based on comments from @ledvinap --- src/main/drivers/motor.c | 9 +++++++++ src/main/drivers/motor.h | 2 ++ src/main/drivers/motor_types.h | 2 ++ src/main/drivers/pwm_output.c | 19 +++++++++++++++++ src/main/drivers/pwm_output_impl.h | 28 ++++++++++++++++++++++++++ src/main/io/serial_4way.c | 24 +++++++++++----------- src/platform/APM32/dshot_bitbang.c | 9 +++++++++ src/platform/APM32/pwm_output_apm32.c | 12 ++--------- src/platform/AT32/pwm_output_at32bsp.c | 14 ++----------- src/platform/SIMULATOR/sitl.c | 21 ++++--------------- src/platform/STM32/pwm_output_hw.c | 13 ++---------- src/platform/common/stm32/dshot_dpwm.c | 9 +++++++++ 12 files changed, 100 insertions(+), 62 deletions(-) create mode 100644 src/main/drivers/pwm_output_impl.h diff --git a/src/main/drivers/motor.c b/src/main/drivers/motor.c index 124554928e..22f2415a11 100644 --- a/src/main/drivers/motor.c +++ b/src/main/drivers/motor.c @@ -362,6 +362,14 @@ timeMs_t motorGetMotorEnableTimeMs(void) } #endif +IO_t motorGetIo(unsigned index) +{ + if (index >= motorDevice.count) { + return IO_NONE; + } + return motorDevice.vTable->getMotorIO ? motorDevice.vTable->getMotorIO(index) : IO_NONE; +} + /* functions below for empty methods and no active motors */ void motorPostInitNull(void) { @@ -433,6 +441,7 @@ static const motorVTable_t motorNullVTable = { .shutdown = motorShutdownNull, .requestTelemetry = NULL, .isMotorIdle = NULL, + .getMotorIO = NULL, }; void motorNullDevInit(motorDevice_t *device) diff --git a/src/main/drivers/motor.h b/src/main/drivers/motor.h index d43f430446..c4a39877f6 100644 --- a/src/main/drivers/motor.h +++ b/src/main/drivers/motor.h @@ -54,5 +54,7 @@ float motorEstimateMaxRpm(void); bool motorIsEnabled(void); bool motorIsMotorEnabled(unsigned index); bool motorIsMotorIdle(unsigned index); +IO_t motorGetIo(unsigned index); + timeMs_t motorGetMotorEnableTimeMs(void); void motorShutdown(void); // Replaces stopPwmAllMotors diff --git a/src/main/drivers/motor_types.h b/src/main/drivers/motor_types.h index c70fcee0b0..f3a88eb7c1 100644 --- a/src/main/drivers/motor_types.h +++ b/src/main/drivers/motor_types.h @@ -22,6 +22,7 @@ #pragma once #include "common/time.h" +#include "drivers/io_types.h" #define ALL_MOTORS 255 #define MOTOR_OUTPUT_LIMIT_PERCENT_MIN 1 @@ -64,6 +65,7 @@ typedef struct motorVTable_s { void (*updateComplete)(void); void (*shutdown)(void); bool (*isMotorIdle)(unsigned index); + IO_t (*getMotorIO)(unsigned index); // Digital commands void (*requestTelemetry)(unsigned index); diff --git a/src/main/drivers/pwm_output.c b/src/main/drivers/pwm_output.c index 813b97e856..e8ae90887b 100644 --- a/src/main/drivers/pwm_output.c +++ b/src/main/drivers/pwm_output.c @@ -48,4 +48,23 @@ void analogInitEndpoints(const motorConfig_t *motorConfig, float outputLimit, fl } } +IO_t pwmGetMotorIO(unsigned index) +{ + if (index >= pwmMotorCount) { + return IO_NONE; + } + return motors[index].io; +} + +bool pwmIsMotorEnabled(unsigned index) +{ + return motors[index].enabled; +} + +bool pwmEnableMotors(void) +{ + /* check motors can be enabled */ + return pwmMotorCount > 0; +} + #endif diff --git a/src/main/drivers/pwm_output_impl.h b/src/main/drivers/pwm_output_impl.h new file mode 100644 index 0000000000..403bf4782e --- /dev/null +++ b/src/main/drivers/pwm_output_impl.h @@ -0,0 +1,28 @@ +/* + * This file is part of Betaflight. + * + * Betaflight is free software. You can redistribute this software + * and/or modify this software under the terms of the GNU General + * Public License as published by the Free Software Foundation, + * either version 3 of the License, or (at your option) any later + * version. + * + * Betaflight is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * See the GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this software. + * + * If not, see . + */ + +#pragma once + +#include "drivers/io_types.h" + +IO_t pwmGetMotorIO(unsigned index); +bool pwmIsMotorEnabled(unsigned index); +bool pwmEnableMotors(void); diff --git a/src/main/io/serial_4way.c b/src/main/io/serial_4way.c index 552fc5d58c..644e37cbb0 100644 --- a/src/main/io/serial_4way.c +++ b/src/main/io/serial_4way.c @@ -36,7 +36,7 @@ #include "drivers/time.h" #include "drivers/timer.h" #include "drivers/light_led.h" -#include "drivers/pwm_output.h" +#include "drivers/motor.h" #include "flight/mixer.h" #include "io/beeper.h" @@ -143,23 +143,23 @@ inline void setEscOutput(uint8_t selEsc) uint8_t esc4wayInit(void) { - // StopPwmAllMotors(); - // XXX Review effect of motor refactor - //pwmDisableMotors(); - escCount = 0; + motorShutdown(); + uint8_t escIndex = 0; + memset(&escHardware, 0, sizeof(escHardware)); - pwmOutputPort_t *pwmMotors = pwmGetMotors(); for (volatile uint8_t i = 0; i < MAX_SUPPORTED_MOTORS; i++) { - if (pwmMotors[i].enabled) { - if (pwmMotors[i].io != IO_NONE) { - escHardware[escCount].io = pwmMotors[i].io; - setEscInput(escCount); - setEscHi(escCount); - escCount++; + if (motorIsMotorEnabled(i)) { + const IO_t io = motorGetIo(i); + if (io != IO_NONE) { + escHardware[escIndex].io = io; + setEscInput(escIndex); + setEscHi(escIndex); + escIndex++; } } } motorDisable(); + escCount = escIndex; return escCount; } diff --git a/src/platform/APM32/dshot_bitbang.c b/src/platform/APM32/dshot_bitbang.c index 5776305d62..33b114fbc0 100644 --- a/src/platform/APM32/dshot_bitbang.c +++ b/src/platform/APM32/dshot_bitbang.c @@ -669,6 +669,14 @@ static void bbPostInit(void) } } +static IO_t bbGetMotorIO(unsigned index) +{ + if (index >= dshotMotorCount) { + return IO_NONE; + } + return bbMotors[index].io; +} + static motorVTable_t bbVTable = { .postInit = bbPostInit, .enable = bbEnableMotors, @@ -685,6 +693,7 @@ static motorVTable_t bbVTable = { .shutdown = bbShutdown, .isMotorIdle = bbDshotIsMotorIdle, .requestTelemetry = bbDshotRequestTelemetry, + .getMotorIO = bbGetMotorIO, }; dshotBitbangStatus_e dshotBitbangGetStatus(void) diff --git a/src/platform/APM32/pwm_output_apm32.c b/src/platform/APM32/pwm_output_apm32.c index d3de5ba53a..706591e0a0 100644 --- a/src/platform/APM32/pwm_output_apm32.c +++ b/src/platform/APM32/pwm_output_apm32.c @@ -31,6 +31,7 @@ #include "drivers/io.h" #include "drivers/motor.h" #include "drivers/pwm_output.h" +#include "drivers/pwm_output_impl.h" #include "drivers/time.h" #include "drivers/timer.h" @@ -108,16 +109,6 @@ static void pwmDisableMotors(void) } static motorVTable_t motorPwmVTable; -static bool pwmEnableMotors(void) -{ - /* check motors can be enabled */ - return pwmMotorCount > 0; -} - -static bool pwmIsMotorEnabled(unsigned index) -{ - return motors[index].enabled; -} static void pwmCompleteMotorUpdate(void) { @@ -158,6 +149,7 @@ static motorVTable_t motorPwmVTable = { .updateComplete = pwmCompleteMotorUpdate, .requestTelemetry = NULL, .isMotorIdle = NULL, + .getMotorIO = pwmGetMotorIO, }; bool motorPwmDevInit(motorDevice_t *device, const motorDevConfig_t *motorConfig, uint16_t idlePulse) diff --git a/src/platform/AT32/pwm_output_at32bsp.c b/src/platform/AT32/pwm_output_at32bsp.c index 8ebc593340..e04b39fc82 100644 --- a/src/platform/AT32/pwm_output_at32bsp.c +++ b/src/platform/AT32/pwm_output_at32bsp.c @@ -31,6 +31,7 @@ #include "drivers/io.h" #include "drivers/motor_impl.h" #include "drivers/pwm_output.h" +#include "drivers/pwm_output_impl.h" #include "drivers/time.h" #include "drivers/timer.h" @@ -98,18 +99,6 @@ static void pwmDisableMotors(void) pwmShutdownPulsesForAllMotors(); } -static motorVTable_t motorPwmVTable; -static bool pwmEnableMotors(void) -{ - /* check motors can be enabled */ - return (pwmMotorDevice->vTable); -} - -static bool pwmIsMotorEnabled(unsigned index) -{ - return motors[index].enabled; -} - static bool useContinuousUpdate = true; static void pwmCompleteMotorUpdate(void) @@ -151,6 +140,7 @@ static motorVTable_t motorPwmVTable = { .updateComplete = pwmCompleteMotorUpdate, .requestTelemetry = NULL, .isMotorIdle = NULL, + .getMotorIO = pwmGetMotorIO, }; bool motorPwmDevInit(motorDevice_t *device, const motorDevConfig_t *motorConfig, uint16_t idlePulse) diff --git a/src/platform/SIMULATOR/sitl.c b/src/platform/SIMULATOR/sitl.c index bd52fe2564..aa58bc45a8 100644 --- a/src/platform/SIMULATOR/sitl.c +++ b/src/platform/SIMULATOR/sitl.c @@ -41,6 +41,7 @@ #include "drivers/system.h" #include "drivers/time.h" #include "drivers/pwm_output.h" +#include "drivers/pwm_output_impl.h" #include "drivers/light_led.h" #include "drivers/timer.h" @@ -543,8 +544,6 @@ void servoDevInit(const servoDevConfig_t *servoConfig) } } -static motorDevice_t pwmMotorDevice; // Forward - pwmOutputPort_t *pwmGetMotors(void) { return motors; @@ -562,14 +561,7 @@ static uint16_t pwmConvertToExternal(float motorValue) static void pwmDisableMotors(void) { - pwmMotorDevice.enabled = false; -} - -static bool pwmEnableMotors(void) -{ - pwmMotorDevice.enabled = true; - - return true; + // NOOP } static void pwmWriteMotor(uint8_t index, float value) @@ -594,12 +586,7 @@ static void pwmWriteMotorInt(uint8_t index, uint16_t value) static void pwmShutdownPulsesForAllMotors(void) { - pwmMotorDevice.enabled = false; -} - -static bool pwmIsMotorEnabled(unsigned index) -{ - return motors[index].enabled; + // NOOP } static void pwmCompleteMotorUpdate(void) @@ -647,7 +634,7 @@ static const motorVTable_t vTable = { .shutdown = pwmShutdownPulsesForAllMotors, .requestTelemetry = NULL, .isMotorIdle = NULL, - + .getMotorIO = NULL, }; bool motorPwmDevInit(motorDevice_t *device, const motorDevConfig_t *motorConfig, uint16_t _idlePulse) diff --git a/src/platform/STM32/pwm_output_hw.c b/src/platform/STM32/pwm_output_hw.c index 99a2a3ce69..aed9bda188 100644 --- a/src/platform/STM32/pwm_output_hw.c +++ b/src/platform/STM32/pwm_output_hw.c @@ -29,6 +29,7 @@ #include "drivers/io.h" #include "drivers/pwm_output.h" +#include "drivers/pwm_output_impl.h" #include "drivers/time.h" #include "drivers/timer.h" @@ -128,17 +129,6 @@ static void pwmDisableMotors(void) pwmShutdownPulsesForAllMotors(); } -static bool pwmEnableMotors(void) -{ - /* check motors can be enabled */ - return pwmMotorCount > 0; -} - -static bool pwmIsMotorEnabled(unsigned index) -{ - return motors[index].enabled; -} - static void pwmCompleteMotorUpdate(void) { if (useContinuousUpdate) { @@ -178,6 +168,7 @@ static const motorVTable_t motorPwmVTable = { .updateComplete = pwmCompleteMotorUpdate, .requestTelemetry = NULL, .isMotorIdle = NULL, + .getMotorIO = pwmGetMotorIO, }; bool motorPwmDevInit(motorDevice_t *device, const motorDevConfig_t *motorConfig, uint16_t idlePulse) diff --git a/src/platform/common/stm32/dshot_dpwm.c b/src/platform/common/stm32/dshot_dpwm.c index cee7aa6003..29c099396e 100644 --- a/src/platform/common/stm32/dshot_dpwm.c +++ b/src/platform/common/stm32/dshot_dpwm.c @@ -126,6 +126,14 @@ static bool dshotPwmIsMotorEnabled(unsigned index) return motors[index].enabled; } +static IO_t pwmDshotGetMotorIO(unsigned index) +{ + if (index >= dshotMotorCount) { + return IO_NONE; + } + return motors[index].io; +} + static FAST_CODE void dshotWriteInt(uint8_t index, uint16_t value) { pwmWriteDshotInt(index, value); @@ -150,6 +158,7 @@ static const motorVTable_t dshotPwmVTable = { .shutdown = dshotPwmShutdown, .requestTelemetry = pwmDshotRequestTelemetry, .isMotorIdle = pwmDshotIsMotorIdle, + .getMotorIO = pwmDshotGetMotorIO, }; bool dshotPwmDevInit(motorDevice_t *device, const motorDevConfig_t *motorConfig) From bfea69a04f80ff9766decd6c7fbbf4e15fbc1832 Mon Sep 17 00:00:00 2001 From: blckmn Date: Thu, 30 Jan 2025 20:33:37 +1100 Subject: [PATCH 095/244] STM32H5: adding MCU_TYPE --- src/platform/common/stm32/system.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/platform/common/stm32/system.c b/src/platform/common/stm32/system.c index aa663e2950..a2424f20a8 100644 --- a/src/platform/common/stm32/system.c +++ b/src/platform/common/stm32/system.c @@ -346,6 +346,8 @@ const mcuTypeInfo_t *getMcuTypeInfo(void) { .id = MCU_TYPE_F746, .name = "STM32F746" }, #elif defined(STM32F765xx) { .id = MCU_TYPE_F765, .name = "STM32F765" }, +#elif defined(STM32H563xx) + { .id = MCU_TYPE_H563, .name = "STM32H563" }, #elif defined(STM32H750xx) { .id = MCU_TYPE_H750, .name = "STM32H750" }, #elif defined(STM32H730xx) From 3dba5e65e4ab237e328b021b69df80d3109d2315 Mon Sep 17 00:00:00 2001 From: Jay Blackman Date: Fri, 31 Jan 2025 06:54:23 +1100 Subject: [PATCH 096/244] FIX: AT32 not reading ESC (#14220) --- src/main/drivers/pwm_output.c | 6 ++-- src/main/drivers/pwm_output.h | 2 +- src/platform/APM32/dshot_bitbang.c | 8 ----- src/platform/APM32/pwm_output_apm32.c | 34 +++++++++---------- src/platform/AT32/dshot_bitbang.c | 3 +- src/platform/AT32/io_at32.c | 12 +------ src/platform/AT32/pwm_output_at32bsp.c | 34 +++++++++---------- src/platform/SIMULATOR/sitl.c | 4 +-- src/platform/STM32/dshot_bitbang.c | 1 + src/platform/STM32/pwm_output_hw.c | 34 +++++++++---------- .../common/stm32/dshot_bitbang_impl.h | 1 + .../common/stm32/dshot_bitbang_shared.c | 8 +++++ src/platform/common/stm32/dshot_dpwm.c | 10 +++--- 13 files changed, 75 insertions(+), 82 deletions(-) diff --git a/src/main/drivers/pwm_output.c b/src/main/drivers/pwm_output.c index e8ae90887b..901e9e1773 100644 --- a/src/main/drivers/pwm_output.c +++ b/src/main/drivers/pwm_output.c @@ -28,7 +28,7 @@ #if defined(USE_PWM_OUTPUT) && defined(USE_MOTOR) -FAST_DATA_ZERO_INIT pwmOutputPort_t motors[MAX_SUPPORTED_MOTORS]; +FAST_DATA_ZERO_INIT pwmOutputPort_t pwmMotors[MAX_SUPPORTED_MOTORS]; FAST_DATA_ZERO_INIT uint8_t pwmMotorCount; void analogInitEndpoints(const motorConfig_t *motorConfig, float outputLimit, float *outputLow, float *outputHigh, float *disarm, float *deadbandMotor3dHigh, float *deadbandMotor3dLow) @@ -53,12 +53,12 @@ IO_t pwmGetMotorIO(unsigned index) if (index >= pwmMotorCount) { return IO_NONE; } - return motors[index].io; + return pwmMotors[index].io; } bool pwmIsMotorEnabled(unsigned index) { - return motors[index].enabled; + return pwmMotors[index].enabled; } bool pwmEnableMotors(void) diff --git a/src/main/drivers/pwm_output.h b/src/main/drivers/pwm_output.h index 644e2415cc..38198a1837 100644 --- a/src/main/drivers/pwm_output.h +++ b/src/main/drivers/pwm_output.h @@ -50,7 +50,7 @@ typedef struct { IO_t io; } pwmOutputPort_t; -extern FAST_DATA_ZERO_INIT pwmOutputPort_t motors[MAX_SUPPORTED_MOTORS]; +extern FAST_DATA_ZERO_INIT pwmOutputPort_t pwmMotors[MAX_SUPPORTED_MOTORS]; extern FAST_DATA_ZERO_INIT uint8_t pwmMotorCount; bool motorPwmDevInit(motorDevice_t *device, const motorDevConfig_t *motorDevConfig, uint16_t idlePulse); diff --git a/src/platform/APM32/dshot_bitbang.c b/src/platform/APM32/dshot_bitbang.c index 33b114fbc0..cf971adf97 100644 --- a/src/platform/APM32/dshot_bitbang.c +++ b/src/platform/APM32/dshot_bitbang.c @@ -669,14 +669,6 @@ static void bbPostInit(void) } } -static IO_t bbGetMotorIO(unsigned index) -{ - if (index >= dshotMotorCount) { - return IO_NONE; - } - return bbMotors[index].io; -} - static motorVTable_t bbVTable = { .postInit = bbPostInit, .enable = bbEnableMotors, diff --git a/src/platform/APM32/pwm_output_apm32.c b/src/platform/APM32/pwm_output_apm32.c index 706591e0a0..cdec437029 100644 --- a/src/platform/APM32/pwm_output_apm32.c +++ b/src/platform/APM32/pwm_output_apm32.c @@ -90,15 +90,15 @@ static bool useContinuousUpdate = true; static void pwmWriteStandard(uint8_t index, float value) { /* TODO: move value to be a number between 0-1 (i.e. percent throttle from mixer) */ - *motors[index].channel.ccr = lrintf((value * motors[index].pulseScale) + motors[index].pulseOffset); + *pwmMotors[index].channel.ccr = lrintf((value * pwmMotors[index].pulseScale) + pwmMotors[index].pulseOffset); } static void pwmShutdownPulsesForAllMotors(void) { for (int index = 0; index < pwmMotorCount; index++) { // Set the compare register to 0, which stops the output pulsing if the timer overflows - if (motors[index].channel.ccr) { - *motors[index].channel.ccr = 0; + if (pwmMotors[index].channel.ccr) { + *pwmMotors[index].channel.ccr = 0; } } } @@ -117,12 +117,12 @@ static void pwmCompleteMotorUpdate(void) } for (int index = 0; index < pwmMotorCount; index++) { - if (motors[index].forceOverflow) { - timerForceOverflow(motors[index].channel.tim); + if (pwmMotors[index].forceOverflow) { + timerForceOverflow(pwmMotors[index].channel.tim); } // Set the compare register to 0, which stops the output pulsing if the timer overflows before the main loop completes again. // This compare register will be set to the output value on the next main loop. - *motors[index].channel.ccr = 0; + *pwmMotors[index].channel.ccr = 0; } } @@ -154,7 +154,7 @@ static motorVTable_t motorPwmVTable = { bool motorPwmDevInit(motorDevice_t *device, const motorDevConfig_t *motorConfig, uint16_t idlePulse) { - memset(motors, 0, sizeof(motors)); + memset(pwmMotors, 0, sizeof(pwmMotors)); if (!device || !motorConfig) { return false; @@ -206,10 +206,10 @@ bool motorPwmDevInit(motorDevice_t *device, const motorDevConfig_t *motorConfig, return false; } - motors[motorIndex].io = IOGetByTag(tag); - IOInit(motors[motorIndex].io, OWNER_MOTOR, RESOURCE_INDEX(reorderedMotorIndex)); + pwmMotors[motorIndex].io = IOGetByTag(tag); + IOInit(pwmMotors[motorIndex].io, OWNER_MOTOR, RESOURCE_INDEX(reorderedMotorIndex)); - IOConfigGPIOAF(motors[motorIndex].io, IOCFG_AF_PP, timerHardware->alternateFunction); + IOConfigGPIOAF(pwmMotors[motorIndex].io, IOCFG_AF_PP, timerHardware->alternateFunction); /* standard PWM outputs */ // margin of safety is 4 periods when unsynced @@ -226,20 +226,20 @@ bool motorPwmDevInit(motorDevice_t *device, const motorDevConfig_t *motorConfig, TODO: this can be moved back to periodMin and periodLen once mixer outputs a 0..1 float value. */ - motors[motorIndex].pulseScale = ((motorConfig->motorProtocol == MOTOR_PROTOCOL_BRUSHED) ? period : (sLen * hz)) / 1000.0f; - motors[motorIndex].pulseOffset = (sMin * hz) - (motors[motorIndex].pulseScale * 1000); + pwmMotors[motorIndex].pulseScale = ((motorConfig->motorProtocol == MOTOR_PROTOCOL_BRUSHED) ? period : (sLen * hz)) / 1000.0f; + pwmMotors[motorIndex].pulseOffset = (sMin * hz) - (pwmMotors[motorIndex].pulseScale * 1000); - pwmOutConfig(&motors[motorIndex].channel, timerHardware, hz, period, idlePulse, motorConfig->motorInversion); + pwmOutConfig(&pwmMotors[motorIndex].channel, timerHardware, hz, period, idlePulse, motorConfig->motorInversion); bool timerAlreadyUsed = false; for (int i = 0; i < motorIndex; i++) { - if (motors[i].channel.tim == motors[motorIndex].channel.tim) { + if (pwmMotors[i].channel.tim == pwmMotors[motorIndex].channel.tim) { timerAlreadyUsed = true; break; } } - motors[motorIndex].forceOverflow = !timerAlreadyUsed; - motors[motorIndex].enabled = true; + pwmMotors[motorIndex].forceOverflow = !timerAlreadyUsed; + pwmMotors[motorIndex].enabled = true; } return true; @@ -247,7 +247,7 @@ bool motorPwmDevInit(motorDevice_t *device, const motorDevConfig_t *motorConfig, pwmOutputPort_t *pwmGetMotors(void) { - return motors; + return pwmMotors; } #ifdef USE_SERVOS diff --git a/src/platform/AT32/dshot_bitbang.c b/src/platform/AT32/dshot_bitbang.c index d3ac4f2e88..fff7eea8b8 100644 --- a/src/platform/AT32/dshot_bitbang.c +++ b/src/platform/AT32/dshot_bitbang.c @@ -583,7 +583,7 @@ static void bbUpdateComplete(void) } #ifdef USE_DSHOT_CACHE_MGMT - for (int motorIndex = 0; motorIndex < MAX_SUPPORTED_MOTORS && motorIndex < motorCount; motorIndex++) { + for (int motorIndex = 0; motorIndex < MAX_SUPPORTED_MOTORS && motorIndex < dshotMotorCount; motorIndex++) { // Only clean each buffer once. If all motors are on a common port they'll share a buffer. bool clean = false; for (int i = 0; i < motorIndex; i++) { @@ -677,6 +677,7 @@ static motorVTable_t bbVTable = { .shutdown = bbShutdown, .isMotorIdle = bbDshotIsMotorIdle, .requestTelemetry = bbDshotRequestTelemetry, + .getMotorIO = bbGetMotorIO, }; dshotBitbangStatus_e dshotBitbangGetStatus(void) diff --git a/src/platform/AT32/io_at32.c b/src/platform/AT32/io_at32.c index 231f9e5e47..5905f4055f 100644 --- a/src/platform/AT32/io_at32.c +++ b/src/platform/AT32/io_at32.c @@ -122,16 +122,6 @@ void IOConfigGPIOAF(IO_t io, ioConfig_t cfg, uint8_t af) return; } - const rccPeriphTag_t rcc = ioPortDefs[IO_GPIOPortIdx(io)].rcc; - RCC_ClockCmd(rcc, ENABLE); - - gpio_init_type init = { - .gpio_pins = IO_Pin(io), - .gpio_mode = (cfg >> 0) & 0x03, - .gpio_drive_strength = (cfg >> 2) & 0x03, - .gpio_out_type = (cfg >> 4) & 0x01, - .gpio_pull = (cfg >> 5) & 0x03, - }; - gpio_init(IO_GPIO(io), &init); + IOConfigGPIO(io, cfg); gpio_pin_mux_config(IO_GPIO(io), IO_GPIO_PinSource(io), af); } diff --git a/src/platform/AT32/pwm_output_at32bsp.c b/src/platform/AT32/pwm_output_at32bsp.c index e04b39fc82..82c1332cb6 100644 --- a/src/platform/AT32/pwm_output_at32bsp.c +++ b/src/platform/AT32/pwm_output_at32bsp.c @@ -81,15 +81,15 @@ static FAST_DATA_ZERO_INIT motorDevice_t *pwmMotorDevice; static void pwmWriteStandard(uint8_t index, float value) { /* TODO: move value to be a number between 0-1 (i.e. percent throttle from mixer) */ - *motors[index].channel.ccr = lrintf((value * motors[index].pulseScale) + motors[index].pulseOffset); + *pwmMotors[index].channel.ccr = lrintf((value * pwmMotors[index].pulseScale) + pwmMotors[index].pulseOffset); } static void pwmShutdownPulsesForAllMotors(void) { for (int index = 0; index < pwmMotorCount; index++) { // Set the compare register to 0, which stops the output pulsing if the timer overflows - if (motors[index].channel.ccr) { - *motors[index].channel.ccr = 0; + if (pwmMotors[index].channel.ccr) { + *pwmMotors[index].channel.ccr = 0; } } } @@ -108,12 +108,12 @@ static void pwmCompleteMotorUpdate(void) } for (int index = 0; index < pwmMotorCount; index++) { - if (motors[index].forceOverflow) { - timerForceOverflow(motors[index].channel.tim); + if (pwmMotors[index].forceOverflow) { + timerForceOverflow(pwmMotors[index].channel.tim); } // Set the compare register to 0, which stops the output pulsing if the timer overflows before the main loop completes again. // This compare register will be set to the output value on the next main loop. - *motors[index].channel.ccr = 0; + *pwmMotors[index].channel.ccr = 0; } } @@ -145,7 +145,7 @@ static motorVTable_t motorPwmVTable = { bool motorPwmDevInit(motorDevice_t *device, const motorDevConfig_t *motorConfig, uint16_t idlePulse) { - memset(motors, 0, sizeof(motors)); + memset(pwmMotors, 0, sizeof(pwmMotors)); if (!device) { return false; @@ -198,10 +198,10 @@ bool motorPwmDevInit(motorDevice_t *device, const motorDevConfig_t *motorConfig, return false; } - motors[motorIndex].io = IOGetByTag(tag); - IOInit(motors[motorIndex].io, OWNER_MOTOR, RESOURCE_INDEX(reorderedMotorIndex)); + pwmMotors[motorIndex].io = IOGetByTag(tag); + IOInit(pwmMotors[motorIndex].io, OWNER_MOTOR, RESOURCE_INDEX(reorderedMotorIndex)); - IOConfigGPIOAF(motors[motorIndex].io, IOCFG_AF_PP, timerHardware->alternateFunction); + IOConfigGPIOAF(pwmMotors[motorIndex].io, IOCFG_AF_PP, timerHardware->alternateFunction); /* standard PWM outputs */ // margin of safety is 4 periods when unsynced @@ -218,27 +218,27 @@ bool motorPwmDevInit(motorDevice_t *device, const motorDevConfig_t *motorConfig, TODO: this can be moved back to periodMin and periodLen once mixer outputs a 0..1 float value. */ - motors[motorIndex].pulseScale = ((motorConfig->motorProtocol == MOTOR_PROTOCOL_BRUSHED) ? period : (sLen * hz)) / 1000.0f; - motors[motorIndex].pulseOffset = (sMin * hz) - (motors[motorIndex].pulseScale * 1000); + pwmMotors[motorIndex].pulseScale = ((motorConfig->motorProtocol == MOTOR_PROTOCOL_BRUSHED) ? period : (sLen * hz)) / 1000.0f; + pwmMotors[motorIndex].pulseOffset = (sMin * hz) - (pwmMotors[motorIndex].pulseScale * 1000); - pwmOutConfig(&motors[motorIndex].channel, timerHardware, hz, period, idlePulse, motorConfig->motorInversion); + pwmOutConfig(&pwmMotors[motorIndex].channel, timerHardware, hz, period, idlePulse, motorConfig->motorInversion); bool timerAlreadyUsed = false; for (int i = 0; i < motorIndex; i++) { - if (motors[i].channel.tim == motors[motorIndex].channel.tim) { + if (pwmMotors[i].channel.tim == pwmMotors[motorIndex].channel.tim) { timerAlreadyUsed = true; break; } } - motors[motorIndex].forceOverflow = !timerAlreadyUsed; - motors[motorIndex].enabled = true; + pwmMotors[motorIndex].forceOverflow = !timerAlreadyUsed; + pwmMotors[motorIndex].enabled = true; } return true; } pwmOutputPort_t *pwmGetMotors(void) { - return motors; + return pwmMotors; } #ifdef USE_SERVOS diff --git a/src/platform/SIMULATOR/sitl.c b/src/platform/SIMULATOR/sitl.c index aa58bc45a8..862d2835fd 100644 --- a/src/platform/SIMULATOR/sitl.c +++ b/src/platform/SIMULATOR/sitl.c @@ -546,7 +546,7 @@ void servoDevInit(const servoDevConfig_t *servoConfig) pwmOutputPort_t *pwmGetMotors(void) { - return motors; + return pwmMotors; } static float pwmConvertFromExternal(uint16_t externalValue) @@ -652,7 +652,7 @@ bool motorPwmDevInit(motorDevice_t *device, const motorDevConfig_t *motorConfig, idlePulse = _idlePulse; for (int motorIndex = 0; motorIndex < MAX_SUPPORTED_MOTORS && motorIndex < motorCount; motorIndex++) { - motors[motorIndex].enabled = true; + pwmMotors[motorIndex].enabled = true; } return true; diff --git a/src/platform/STM32/dshot_bitbang.c b/src/platform/STM32/dshot_bitbang.c index 3cf7db42ce..38f895b1ba 100644 --- a/src/platform/STM32/dshot_bitbang.c +++ b/src/platform/STM32/dshot_bitbang.c @@ -716,6 +716,7 @@ static const motorVTable_t bbVTable = { .shutdown = bbShutdown, .isMotorIdle = bbDshotIsMotorIdle, .requestTelemetry = bbDshotRequestTelemetry, + .getMotorIO = bbGetMotorIO, }; dshotBitbangStatus_e dshotBitbangGetStatus(void) diff --git a/src/platform/STM32/pwm_output_hw.c b/src/platform/STM32/pwm_output_hw.c index aed9bda188..ae8c6a21af 100644 --- a/src/platform/STM32/pwm_output_hw.c +++ b/src/platform/STM32/pwm_output_hw.c @@ -111,15 +111,15 @@ void pwmOutConfig(timerChannel_t *channel, const timerHardware_t *timerHardware, static void pwmWriteStandard(uint8_t index, float value) { /* TODO: move value to be a number between 0-1 (i.e. percent throttle from mixer) */ - *motors[index].channel.ccr = lrintf((value * motors[index].pulseScale) + motors[index].pulseOffset); + *pwmMotors[index].channel.ccr = lrintf((value * pwmMotors[index].pulseScale) + pwmMotors[index].pulseOffset); } static void pwmShutdownPulsesForAllMotors(void) { for (int index = 0; pwmMotorCount; index++) { // Set the compare register to 0, which stops the output pulsing if the timer overflows - if (motors[index].channel.ccr) { - *motors[index].channel.ccr = 0; + if (pwmMotors[index].channel.ccr) { + *pwmMotors[index].channel.ccr = 0; } } } @@ -136,12 +136,12 @@ static void pwmCompleteMotorUpdate(void) } for (int index = 0; pwmMotorCount; index++) { - if (motors[index].forceOverflow) { - timerForceOverflow(motors[index].channel.tim); + if (pwmMotors[index].forceOverflow) { + timerForceOverflow(pwmMotors[index].channel.tim); } // Set the compare register to 0, which stops the output pulsing if the timer overflows before the main loop completes again. // This compare register will be set to the output value on the next main loop. - *motors[index].channel.ccr = 0; + *pwmMotors[index].channel.ccr = 0; } } @@ -173,7 +173,7 @@ static const motorVTable_t motorPwmVTable = { bool motorPwmDevInit(motorDevice_t *device, const motorDevConfig_t *motorConfig, uint16_t idlePulse) { - memset(motors, 0, sizeof(motors)); + memset(pwmMotors, 0, sizeof(pwmMotors)); pwmMotorCount = device->count; device->vTable = &motorPwmVTable; @@ -221,10 +221,10 @@ bool motorPwmDevInit(motorDevice_t *device, const motorDevConfig_t *motorConfig, return false; } - motors[motorIndex].io = IOGetByTag(tag); - IOInit(motors[motorIndex].io, OWNER_MOTOR, RESOURCE_INDEX(reorderedMotorIndex)); + pwmMotors[motorIndex].io = IOGetByTag(tag); + IOInit(pwmMotors[motorIndex].io, OWNER_MOTOR, RESOURCE_INDEX(reorderedMotorIndex)); - IOConfigGPIOAF(motors[motorIndex].io, IOCFG_AF_PP, timerHardware->alternateFunction); + IOConfigGPIOAF(pwmMotors[motorIndex].io, IOCFG_AF_PP, timerHardware->alternateFunction); /* standard PWM outputs */ // margin of safety is 4 periods when unsynced @@ -241,20 +241,20 @@ bool motorPwmDevInit(motorDevice_t *device, const motorDevConfig_t *motorConfig, TODO: this can be moved back to periodMin and periodLen once mixer outputs a 0..1 float value. */ - motors[motorIndex].pulseScale = ((motorConfig->motorProtocol == MOTOR_PROTOCOL_BRUSHED) ? period : (sLen * hz)) / 1000.0f; - motors[motorIndex].pulseOffset = (sMin * hz) - (motors[motorIndex].pulseScale * 1000); + pwmMotors[motorIndex].pulseScale = ((motorConfig->motorProtocol == MOTOR_PROTOCOL_BRUSHED) ? period : (sLen * hz)) / 1000.0f; + pwmMotors[motorIndex].pulseOffset = (sMin * hz) - (pwmMotors[motorIndex].pulseScale * 1000); - pwmOutConfig(&motors[motorIndex].channel, timerHardware, hz, period, idlePulse, motorConfig->motorInversion); + pwmOutConfig(&pwmMotors[motorIndex].channel, timerHardware, hz, period, idlePulse, motorConfig->motorInversion); bool timerAlreadyUsed = false; for (int i = 0; i < motorIndex; i++) { - if (motors[i].channel.tim == motors[motorIndex].channel.tim) { + if (pwmMotors[i].channel.tim == pwmMotors[motorIndex].channel.tim) { timerAlreadyUsed = true; break; } } - motors[motorIndex].forceOverflow = !timerAlreadyUsed; - motors[motorIndex].enabled = true; + pwmMotors[motorIndex].forceOverflow = !timerAlreadyUsed; + pwmMotors[motorIndex].enabled = true; } return true; @@ -262,7 +262,7 @@ bool motorPwmDevInit(motorDevice_t *device, const motorDevConfig_t *motorConfig, pwmOutputPort_t *pwmGetMotors(void) { - return motors; + return pwmMotors; } #ifdef USE_SERVOS diff --git a/src/platform/common/stm32/dshot_bitbang_impl.h b/src/platform/common/stm32/dshot_bitbang_impl.h index 4e062e86c2..76b6b06196 100644 --- a/src/platform/common/stm32/dshot_bitbang_impl.h +++ b/src/platform/common/stm32/dshot_bitbang_impl.h @@ -285,3 +285,4 @@ int bbDMA_Count(bbPort_t *bbPort); void bbDshotRequestTelemetry(unsigned motorIndex); bool bbDshotIsMotorIdle(unsigned motorIndex); +IO_t bbGetMotorIO(unsigned index); diff --git a/src/platform/common/stm32/dshot_bitbang_shared.c b/src/platform/common/stm32/dshot_bitbang_shared.c index c5152d59f3..3339df045b 100644 --- a/src/platform/common/stm32/dshot_bitbang_shared.c +++ b/src/platform/common/stm32/dshot_bitbang_shared.c @@ -54,6 +54,14 @@ bool bbDshotIsMotorIdle(unsigned motorIndex) return bbmotor->protocolControl.value == 0; } +IO_t bbGetMotorIO(unsigned index) +{ + if (index >= dshotMotorCount) { + return IO_NONE; + } + return bbMotors[index].io; +} + #ifdef USE_DSHOT_BITBANG bool isDshotBitbangActive(const motorDevConfig_t *motorDevConfig) { diff --git a/src/platform/common/stm32/dshot_dpwm.c b/src/platform/common/stm32/dshot_dpwm.c index 29c099396e..2e2186a1ac 100644 --- a/src/platform/common/stm32/dshot_dpwm.c +++ b/src/platform/common/stm32/dshot_dpwm.c @@ -123,7 +123,7 @@ static bool dshotPwmEnableMotors(void) static bool dshotPwmIsMotorEnabled(unsigned index) { - return motors[index].enabled; + return pwmMotors[index].enabled; } static IO_t pwmDshotGetMotorIO(unsigned index) @@ -131,7 +131,7 @@ static IO_t pwmDshotGetMotorIO(unsigned index) if (index >= dshotMotorCount) { return IO_NONE; } - return motors[index].io; + return pwmMotors[index].io; } static FAST_CODE void dshotWriteInt(uint8_t index, uint16_t value) @@ -190,15 +190,15 @@ bool dshotPwmDevInit(motorDevice_t *device, const motorDevConfig_t *motorConfig) const timerHardware_t *timerHardware = timerAllocate(tag, OWNER_MOTOR, RESOURCE_INDEX(reorderedMotorIndex)); if (timerHardware != NULL) { - motors[motorIndex].io = IOGetByTag(tag); - IOInit(motors[motorIndex].io, OWNER_MOTOR, RESOURCE_INDEX(reorderedMotorIndex)); + pwmMotors[motorIndex].io = IOGetByTag(tag); + IOInit(pwmMotors[motorIndex].io, OWNER_MOTOR, RESOURCE_INDEX(reorderedMotorIndex)); if (pwmDshotMotorHardwareConfig(timerHardware, motorIndex, reorderedMotorIndex, motorConfig->motorProtocol, motorConfig->motorInversion ? timerHardware->output ^ TIMER_OUTPUT_INVERTED : timerHardware->output)) { - motors[motorIndex].enabled = true; + pwmMotors[motorIndex].enabled = true; continue; } From 7cc8ee9a5470cb0b72900df88ff2be6a05f0cd0a Mon Sep 17 00:00:00 2001 From: "Git bot (blckmn)" Date: Sat, 1 Feb 2025 06:25:03 +0000 Subject: [PATCH 097/244] Auto updated submodule references [01-02-2025] --- src/config | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/config b/src/config index 5e33fe422e..33605beffb 160000 --- a/src/config +++ b/src/config @@ -1 +1 @@ -Subproject commit 5e33fe422e2c1fb095db84508a9e3ebb465a80a4 +Subproject commit 33605beffbd9b39aa3f6aa957a2d65ecd9edf365 From 79ecc1ac74574b23123b84597aeaa93c3a09dc41 Mon Sep 17 00:00:00 2001 From: Jeff Haynes Date: Sat, 1 Feb 2025 15:59:24 -0500 Subject: [PATCH 098/244] Fix MSP memory issue (#14221) * fixes #14219 * Update src/main/msp/msp.c Co-authored-by: Petr Ledvina --------- Co-authored-by: Petr Ledvina --- src/main/msp/msp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/msp/msp.c b/src/main/msp/msp.c index df8e717cb9..38d5d126ba 100644 --- a/src/main/msp/msp.c +++ b/src/main/msp/msp.c @@ -4147,7 +4147,7 @@ static mspResult_e mspProcessInCommand(mspDescriptor_t srcDesc, int16_t cmdMSP, } const unsigned textLength = MIN(textSpace, sbufReadU8(src)); - memset(textVar, 0, strlen(textVar)); + textVar[textLength] = '\0'; sbufReadData(src, textVar, textLength); #ifdef USE_OSD From e7f0486ebe259bfc937b4d211c302abde4df8688 Mon Sep 17 00:00:00 2001 From: Petr Ledvina Date: Sat, 1 Feb 2025 22:45:21 +0100 Subject: [PATCH 099/244] fix compilation without ACC (#14218) * fix compilation without ACC - compilatiopn may fail with cryptic message when no ACC is selected (unused variable `dev`). Mark dev as unused - MPU6500 is handled differently than all other accs (it is only driver that adds case labels) - also make dev UNUSED for gyro * Update src/main/sensors/acceleration_init.c --------- Co-authored-by: Mark Haslinghuis --- src/main/sensors/acceleration_init.c | 5 +++-- src/main/sensors/gyro_init.c | 1 + 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/src/main/sensors/acceleration_init.c b/src/main/sensors/acceleration_init.c index 1488b8b28a..6624253658 100644 --- a/src/main/sensors/acceleration_init.c +++ b/src/main/sensors/acceleration_init.c @@ -167,11 +167,11 @@ retry: FALLTHROUGH; #endif +#if defined(USE_ACC_MPU6500) || defined(USE_ACC_SPI_MPU6500) case ACC_MPU6500: case ACC_ICM20601: case ACC_ICM20602: case ACC_ICM20608G: -#if defined(USE_ACC_MPU6500) || defined(USE_ACC_SPI_MPU6500) #ifdef USE_ACC_SPI_MPU6500 if (mpu6500SpiAccDetect(dev)) { #else @@ -195,8 +195,8 @@ retry: } break; } -#endif FALLTHROUGH; +#endif #ifdef USE_ACC_SPI_ICM20649 case ACC_ICM20649: @@ -287,6 +287,7 @@ retry: default: case ACC_NONE: // disable ACC + UNUSED(dev); accHardware = ACC_NONE; break; } diff --git a/src/main/sensors/gyro_init.c b/src/main/sensors/gyro_init.c index 4e09d73c18..151d9f8aeb 100644 --- a/src/main/sensors/gyro_init.c +++ b/src/main/sensors/gyro_init.c @@ -500,6 +500,7 @@ STATIC_UNIT_TESTED gyroHardware_e gyroDetect(gyroDev_t *dev) #endif default: + UNUSED(dev); gyroHardware = GYRO_NONE; } From bde342c8cbd18613e164054c84d5d76da183eb48 Mon Sep 17 00:00:00 2001 From: Mark Haslinghuis Date: Mon, 3 Feb 2025 12:07:44 +0100 Subject: [PATCH 100/244] Fix PG ID and corruption in MSP_SET_SENSOR_CONFIG (#14230) * Fix PG ID * Fix corruption in MSP_SET_SENSOR_CONFIG * No need to specify ammount of bytes remaining * Update after review from @ledvinap * Remove unused PG_BETAFLIGHT_END --- src/main/msp/msp.c | 13 +++++++++---- src/main/pg/pg_ids.h | 1 - src/main/sensors/opticalflow.c | 4 ++-- 3 files changed, 11 insertions(+), 7 deletions(-) diff --git a/src/main/msp/msp.c b/src/main/msp/msp.c index 38d5d126ba..3738779796 100644 --- a/src/main/msp/msp.c +++ b/src/main/msp/msp.c @@ -3350,18 +3350,23 @@ static mspResult_e mspProcessInCommand(mspDescriptor_t srcDesc, int16_t cmdMSP, sbufReadU8(src); #endif + if (sbufBytesRemaining(src) >= 1) { #ifdef USE_RANGEFINDER - rangefinderConfigMutable()->rangefinder_hardware = sbufReadU8(src); + rangefinderConfigMutable()->rangefinder_hardware = sbufReadU8(src); #else - sbufReadU8(src); + sbufReadU8(src); #endif + } + if (sbufBytesRemaining(src) >= 1) { #ifdef USE_OPTICALFLOW - opticalflowConfigMutable()->opticalflow_hardware = sbufReadU8(src); + opticalflowConfigMutable()->opticalflow_hardware = sbufReadU8(src); #else - sbufReadU8(src); + sbufReadU8(src); #endif + } break; + #ifdef USE_ACC case MSP_ACC_CALIBRATION: if (!ARMING_FLAG(ARMED)) diff --git a/src/main/pg/pg_ids.h b/src/main/pg/pg_ids.h index 97e3d125d9..ee9fee1a0b 100644 --- a/src/main/pg/pg_ids.h +++ b/src/main/pg/pg_ids.h @@ -159,7 +159,6 @@ //#define PG_SOFTSERIAL_PIN_CONFIG 558 // removed, merged into SERIAL_PIN_CONFIG #define PG_GIMBAL_TRACK_CONFIG 559 #define PG_OPTICALFLOW_CONFIG 560 -#define PG_BETAFLIGHT_END 560 // OSD configuration (subject to change) diff --git a/src/main/sensors/opticalflow.c b/src/main/sensors/opticalflow.c index 27dc57e970..796e5383ad 100644 --- a/src/main/sensors/opticalflow.c +++ b/src/main/sensors/opticalflow.c @@ -68,8 +68,8 @@ PG_REGISTER_WITH_RESET_TEMPLATE(opticalflowConfig_t, opticalflowConfig, PG_OPTIC PG_RESET_TEMPLATE(opticalflowConfig_t, opticalflowConfig, .opticalflow_hardware = OPTICALFLOW_NONE, .rotation = 0, - .flow_lpf = 0, - .flip_x = 0 + .flip_x = 0, + .flow_lpf = 0 ); static opticalflow_t opticalflow; From f2e9dac32200076e92b4d37f7d357478f0b63afe Mon Sep 17 00:00:00 2001 From: "Git bot (blckmn)" Date: Tue, 4 Feb 2025 06:25:05 +0000 Subject: [PATCH 101/244] Auto updated submodule references [04-02-2025] --- src/config | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/config b/src/config index 33605beffb..760a18fe97 160000 --- a/src/config +++ b/src/config @@ -1 +1 @@ -Subproject commit 33605beffbd9b39aa3f6aa957a2d65ecd9edf365 +Subproject commit 760a18fe97a25c4b987b4b8a5c7fb4826f0e5736 From 896bf03b4ec7f240c1b16d7862a6528d915e7478 Mon Sep 17 00:00:00 2001 From: Jacob Dahl <37091262+dakejahl@users.noreply.github.com> Date: Tue, 4 Feb 2025 10:00:11 -0900 Subject: [PATCH 102/244] lis2mdl: fix read (#14227) * lis2mdl: revert reading status register, use measure/collect paradigm * Update src/main/drivers/compass/compass_lis2mdl.c Co-authored-by: Mark Haslinghuis * fix typo * fixed borked logic --------- Co-authored-by: Mark Haslinghuis --- src/main/drivers/compass/compass_lis2mdl.c | 19 ++++++++----------- 1 file changed, 8 insertions(+), 11 deletions(-) diff --git a/src/main/drivers/compass/compass_lis2mdl.c b/src/main/drivers/compass/compass_lis2mdl.c index f270b3ca29..f2c1d75730 100644 --- a/src/main/drivers/compass/compass_lis2mdl.c +++ b/src/main/drivers/compass/compass_lis2mdl.c @@ -77,20 +77,15 @@ static bool lis2mdlInit(magDev_t *mag) static bool lis2mdlRead(magDev_t *mag, int16_t *magData) { - uint8_t status = 0; - uint8_t buf[6]; + static uint8_t buf[6]; + static bool pendingRead = true; extDevice_t *dev = &mag->dev; - if (!busReadRegisterBuffer(dev, LIS2MDL_ADDR_STATUS_REG, &status, sizeof(status))) { - return false; - } - - if (!(status & LIS2MDL_STATUS_REG_READY)) { - return false; - } - - if (!busReadRegisterBuffer(dev, LIS2MDL_ADDR_OUTX_L_REG, (uint8_t *)&buf, sizeof(buf))) { + if (pendingRead) { + if (busReadRegisterBufferStart(dev, LIS2MDL_ADDR_OUTX_L_REG, (uint8_t *)buf, sizeof(buf))) { + pendingRead = false; + } return false; } @@ -107,6 +102,8 @@ static bool lis2mdlRead(magDev_t *mag, int16_t *magData) magData[Y] = y; magData[Z] = z; + pendingRead = true; + return true; } From caa8935e61f44d696d30676760ac98dae290c644 Mon Sep 17 00:00:00 2001 From: "Git bot (blckmn)" Date: Wed, 5 Feb 2025 06:25:04 +0000 Subject: [PATCH 103/244] Auto updated submodule references [05-02-2025] --- src/config | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/config b/src/config index 760a18fe97..1ea2d4e896 160000 --- a/src/config +++ b/src/config @@ -1 +1 @@ -Subproject commit 760a18fe97a25c4b987b4b8a5c7fb4826f0e5736 +Subproject commit 1ea2d4e896f3c4854c26108e938e76f31bcd0441 From 54cee626999e59bf5bc6ba446844838ec8cacaa5 Mon Sep 17 00:00:00 2001 From: Mark Haslinghuis Date: Wed, 5 Feb 2025 21:12:15 +0100 Subject: [PATCH 104/244] Fix opticalflow detection (msp) (#14241) * Fix opticalflow detection (msp) * Add opticalflow to detected sensors in MSP_STATUS_EX --- src/main/msp/msp.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/main/msp/msp.c b/src/main/msp/msp.c index 3738779796..e537abbfd1 100644 --- a/src/main/msp/msp.c +++ b/src/main/msp/msp.c @@ -1092,7 +1092,7 @@ static bool mspProcessOutCommand(mspDescriptor_t srcDesc, int16_t cmdMSP, sbuf_t #else sbufWriteU16(dst, 0); #endif - sbufWriteU16(dst, sensors(SENSOR_ACC) | sensors(SENSOR_BARO) << 1 | sensors(SENSOR_MAG) << 2 | sensors(SENSOR_GPS) << 3 | sensors(SENSOR_RANGEFINDER) << 4 | sensors(SENSOR_GYRO) << 5); + sbufWriteU16(dst, sensors(SENSOR_ACC) | sensors(SENSOR_BARO) << 1 | sensors(SENSOR_MAG) << 2 | sensors(SENSOR_GPS) << 3 | sensors(SENSOR_RANGEFINDER) << 4 | sensors(SENSOR_GYRO) << 5 | sensors(SENSOR_OPTICALFLOW) << 6); sbufWriteData(dst, &flightModeFlags, 4); // unconditional part of flags, first 32 bits sbufWriteU8(dst, getCurrentPidProfileIndex()); sbufWriteU16(dst, constrain(getAverageSystemLoadPercent(), 0, LOAD_PERCENTAGE_ONE)); @@ -2131,7 +2131,7 @@ case MSP_NAME: #else sbufWriteU8(dst, SENSOR_NOT_AVAILABLE); #endif -#ifdef USE_OPTICAL_FLOW +#ifdef USE_OPTICALFLOW sbufWriteU8(dst, detectedSensors[SENSOR_INDEX_OPTICALFLOW]); #else sbufWriteU8(dst, SENSOR_NOT_AVAILABLE); From 39f82e79df119cc191b27199077b0908c80f32db Mon Sep 17 00:00:00 2001 From: ke deng Date: Thu, 6 Feb 2025 05:16:36 +0800 Subject: [PATCH 105/244] Change sed search regex to be compatible with BSD sed (#14233) Change sed search regex to be compatible with BSD sed, # symbol should be escaped. --- mk/config.mk | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/mk/config.mk b/mk/config.mk index edd101b6d2..5f85d4987d 100644 --- a/mk/config.mk +++ b/mk/config.mk @@ -34,17 +34,17 @@ CONFIG_REVISION := $(shell git -C $(CONFIG_DIR) log -1 --format="%h") CONFIG_REVISION_DEFINE := -D'__CONFIG_REVISION__="$(CONFIG_REVISION)"' endif -HSE_VALUE_MHZ := $(shell sed -E -n "/^\s*#\s*define\s+SYSTEM_HSE_MHZ\s+([0-9]+).*/s//\1/p" $(CONFIG_HEADER_FILE)) +HSE_VALUE_MHZ := $(shell sed -E -n "/^[[:space:]]*\#[[:space:]]*define[[:space:]]+SYSTEM_HSE_MHZ[[:space:]]+([0-9]+).*/s//\1/p" $(CONFIG_HEADER_FILE)) ifneq ($(HSE_VALUE_MHZ),) HSE_VALUE := $(shell echo $$(( $(HSE_VALUE_MHZ) * 1000000 )) ) endif -TARGET := $(shell sed -E -n "/^\s*#\s*define\s+FC_TARGET_MCU\s+(\w+).*/s//\1/p" $(CONFIG_HEADER_FILE)) +TARGET := $(shell sed -E -n "/^[[:space:]]*\#[[:space:]]*define[[:space:]]+FC_TARGET_MCU[[:space:]]+([[:alnum:]_]+).*/s//\1/p" $(CONFIG_HEADER_FILE)) ifeq ($(TARGET),) $(error No TARGET identified. Is the $(CONFIG_HEADER_FILE) valid for $(CONFIG)?) endif -EXST_ADJUST_VMA := $(shell sed -E -n "/^\s*#\s*define\s+FC_VMA_ADDRESS\s+((0[xX])?[[:xdigit:]]+).*/s//\1/p" $(CONFIG_HEADER_FILE)) +EXST_ADJUST_VMA := $(shell sed -E -n "/^[[:space:]]*\#[[:space:]]*define[[:space:]]+FC_VMA_ADDRESS[[:space:]]+((0[xX])?[[:xdigit:]]+).*/s//\1/p" $(CONFIG_HEADER_FILE)) ifneq ($(EXST_ADJUST_VMA),) EXST = yes endif From c2381fb98f1f41160e20601fa1dc35b7bf261e9b Mon Sep 17 00:00:00 2001 From: Mark Haslinghuis Date: Thu, 6 Feb 2025 22:11:05 +0100 Subject: [PATCH 106/244] Make number of rate profiles conditional using define (#14239) * Revert reducing number of rate profiles * Add CONTROL_RATE_PROFILE_COUNT to STATUS_EX (msp) * Update src/main/target/common_pre.h Co-authored-by: Petr Ledvina * Update src/test/unit/platform.h Co-authored-by: Petr Ledvina --------- Co-authored-by: Petr Ledvina --- src/main/msp/msp.c | 1 + src/main/target/common_pre.h | 4 +++- src/test/unit/platform.h | 2 +- 3 files changed, 5 insertions(+), 2 deletions(-) diff --git a/src/main/msp/msp.c b/src/main/msp/msp.c index e537abbfd1..0d39f90533 100644 --- a/src/main/msp/msp.c +++ b/src/main/msp/msp.c @@ -1128,6 +1128,7 @@ static bool mspProcessOutCommand(mspDescriptor_t srcDesc, int16_t cmdMSP, sbuf_t #else sbufWriteU16(dst, 0); #endif + sbufWriteU8(dst, CONTROL_RATE_PROFILE_COUNT); break; } diff --git a/src/main/target/common_pre.h b/src/main/target/common_pre.h index 1220594f3d..b616303190 100644 --- a/src/main/target/common_pre.h +++ b/src/main/target/common_pre.h @@ -301,7 +301,9 @@ #define USE_HUFFMAN #define PID_PROFILE_COUNT 4 -#define CONTROL_RATE_PROFILE_COUNT 4 +#ifndef CONTROL_RATE_PROFILE_COUNT +#define CONTROL_RATE_PROFILE_COUNT 4 // or maybe 6 +#endif #define USE_CLI_BATCH #define USE_RESOURCE_MGMT diff --git a/src/test/unit/platform.h b/src/test/unit/platform.h index d7d5eb505e..dd03dce802 100644 --- a/src/test/unit/platform.h +++ b/src/test/unit/platform.h @@ -43,7 +43,7 @@ #define PID_PROFILE_COUNT 4 -#define CONTROL_RATE_PROFILE_COUNT 4 +#define CONTROL_RATE_PROFILE_COUNT 4 #define USE_MAG #define USE_BARO #define USE_GPS From a45f74047b61b24738bc397953853b5303fdb202 Mon Sep 17 00:00:00 2001 From: "Git bot (blckmn)" Date: Fri, 7 Feb 2025 06:25:04 +0000 Subject: [PATCH 107/244] Auto updated submodule references [07-02-2025] --- src/config | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/config b/src/config index 1ea2d4e896..ebfa401cb2 160000 --- a/src/config +++ b/src/config @@ -1 +1 @@ -Subproject commit 1ea2d4e896f3c4854c26108e938e76f31bcd0441 +Subproject commit ebfa401cb2a458f80018e45bcdbbcacd19304736 From 6d7425bfa3d823ffd6c94d9fdeeebc9af88a8a59 Mon Sep 17 00:00:00 2001 From: "Git bot (blckmn)" Date: Sat, 8 Feb 2025 06:25:03 +0000 Subject: [PATCH 108/244] Auto updated submodule references [08-02-2025] --- src/config | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/config b/src/config index ebfa401cb2..fd1c46d757 160000 --- a/src/config +++ b/src/config @@ -1 +1 @@ -Subproject commit ebfa401cb2a458f80018e45bcdbbcacd19304736 +Subproject commit fd1c46d757eeaaa6389ac4764ca9de6a8e5c0810 From 9ef4857eebe1cbe777091f4e198b68fbde519eea Mon Sep 17 00:00:00 2001 From: "Git bot (blckmn)" Date: Sun, 9 Feb 2025 06:25:03 +0000 Subject: [PATCH 109/244] Auto updated submodule references [09-02-2025] --- src/config | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/config b/src/config index fd1c46d757..64337752ec 160000 --- a/src/config +++ b/src/config @@ -1 +1 @@ -Subproject commit fd1c46d757eeaaa6389ac4764ca9de6a8e5c0810 +Subproject commit 64337752ec6af16a8663b4df48d8a9eb8fb1fbdb From 86767ba112fa05722a0eeee1ca53a6034a890d1e Mon Sep 17 00:00:00 2001 From: ctzsnooze Date: Sun, 9 Feb 2025 23:34:12 +0100 Subject: [PATCH 110/244] Consistent autopilot variable names, use alt_hold_climb_rate (#14136) * consistent autopilot parameter names - add colons after each blackbox header line - change alt_hold_throttle_response to alt_hold_climb_rate - don't use cfg abbreviation for apConfig() because it is harder to search * enforce semicolon with do... while (0) * don't abbreviate autopilotConfig to apConfig * remove semicolon after break to enforce semicolon at input line ending * explanatory message * fix copy and paste errors * restore local cfg alias in place of autopilotConfig() * struct name formatting as requested by blckmn Co-Authored-By: Jay Blackman * underscore the CLI names, fix prev commit Co-Authored-By: Jay Blackman * Update src/main/fc/parameter_names.h * Update src/main/fc/parameter_names.h --------- Co-authored-by: Jay Blackman Co-authored-by: Mark Haslinghuis --- src/main/blackbox/blackbox.c | 99 ++++++++++--------- src/main/cli/settings.c | 36 +++---- src/main/cms/cms_menu_gps_rescue_multirotor.c | 58 +++++------ src/main/fc/parameter_names.h | 30 +++--- src/main/flight/alt_hold_multirotor.c | 14 +-- src/main/flight/autopilot_multirotor.c | 29 +++--- src/main/flight/gps_rescue_multirotor.c | 2 +- src/main/flight/pid.c | 2 +- src/main/flight/pos_hold_multirotor.c | 6 +- src/main/msp/msp.c | 28 +++--- src/main/pg/alt_hold_multirotor.c | 4 +- src/main/pg/alt_hold_multirotor.h | 4 +- src/main/pg/autopilot_multirotor.c | 32 +++--- src/main/pg/autopilot_multirotor.h | 34 +++---- src/main/pg/autopilot_wing.c | 4 +- src/main/pg/autopilot_wing.h | 6 +- src/main/pg/pos_hold_multirotor.c | 4 +- src/main/pg/pos_hold_multirotor.h | 4 +- src/test/unit/althold_unittest.cc | 2 +- src/test/unit/arming_prevention_unittest.cc | 2 +- src/test/unit/flight_imu_unittest.cc | 2 +- 21 files changed, 202 insertions(+), 200 deletions(-) diff --git a/src/main/blackbox/blackbox.c b/src/main/blackbox/blackbox.c index ba8db32289..42d274979f 100644 --- a/src/main/blackbox/blackbox.c +++ b/src/main/blackbox/blackbox.c @@ -1441,12 +1441,15 @@ STATIC_UNIT_TESTED char *blackboxGetStartDateTime(char *buf) } #ifndef BLACKBOX_PRINT_HEADER_LINE -#define BLACKBOX_PRINT_HEADER_LINE(name, format, ...) case __COUNTER__: \ - blackboxPrintfHeaderLine(name, format, __VA_ARGS__); \ - break; -#define BLACKBOX_PRINT_HEADER_LINE_CUSTOM(...) case __COUNTER__: \ - {__VA_ARGS__}; \ - break; +#define BLACKBOX_PRINT_HEADER_LINE(name, format, ...) \ + case __COUNTER__: { \ + blackboxPrintfHeaderLine(name, format, __VA_ARGS__); \ + } break // absence of semicolon on this line is what enforces the presence of a semicolon at the end of each input line + +#define BLACKBOX_PRINT_HEADER_LINE_CUSTOM(...) \ + case __COUNTER__: { \ + __VA_ARGS__; \ + } break #endif /** @@ -1707,20 +1710,20 @@ static bool blackboxWriteSysinfo(void) BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_ALTITUDE_D_LPF, "%d", positionConfig()->altitude_d_lpf); #ifndef USE_WING - BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_LANDING_ALTITUDE, "%d", apConfig()->landing_altitude_m); - BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_HOVER_THROTTLE, "%d", apConfig()->hover_throttle); - BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_THROTTLE_MIN, "%d", apConfig()->throttle_min); - BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_THROTTLE_MAX, "%d", apConfig()->throttle_max); - BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_ALTITUDE_P, "%d", apConfig()->altitude_P); - BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_ALTITUDE_I, "%d", apConfig()->altitude_I); - BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_ALTITUDE_D, "%d", apConfig()->altitude_D); - BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_ALTITUDE_F, "%d", apConfig()->altitude_F); - BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_POSITION_P, "%d", apConfig()->position_P); - BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_POSITION_I, "%d", apConfig()->position_I); - BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_POSITION_D, "%d", apConfig()->position_D); - BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_POSITION_A, "%d", apConfig()->position_A); - BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_POSITION_CUTOFF, "%d", apConfig()->position_cutoff); - BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_AP_MAX_ANGLE, "%d", apConfig()->max_angle); + BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_AP_LANDING_ALTITUDE_M, "%d", autopilotConfig()->landingAltitudeM); + BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_AP_HOVER_THROTTLE, "%d", autopilotConfig()->hoverThrottle); + BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_AP_THROTTLE_MIN, "%d", autopilotConfig()->throttleMin); + BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_AP_THROTTLE_MAX, "%d", autopilotConfig()->throttleMax); + BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_AP_ALTITUDE_P, "%d", autopilotConfig()->altitudeP); + BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_AP_ALTITUDE_I, "%d", autopilotConfig()->altitudeI); + BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_AP_ALTITUDE_D, "%d", autopilotConfig()->altitudeD); + BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_AP_ALTITUDE_F, "%d", autopilotConfig()->altitudeF); + BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_AP_POSITION_P, "%d", autopilotConfig()->positionP); + BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_AP_POSITION_I, "%d", autopilotConfig()->positionI); + BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_AP_POSITION_D, "%d", autopilotConfig()->positionD); + BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_AP_POSITION_A, "%d", autopilotConfig()->positionA); + BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_AP_POSITION_CUTOFF, "%d", autopilotConfig()->positionCutoff); + BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_AP_MAX_ANGLE, "%d", autopilotConfig()->maxAngle); #endif // !USE_WING #ifdef USE_MAG @@ -1793,38 +1796,38 @@ static bool blackboxWriteSysinfo(void) BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_THRUST_LINEARIZATION, "%d", currentPidProfile->thrustLinearization); #ifdef USE_GPS - BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_GPS_PROVIDER, "%d", gpsConfig()->provider) - BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_GPS_SET_HOME_POINT_ONCE, "%d", gpsConfig()->gps_set_home_point_once) - BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_GPS_USE_3D_SPEED, "%d", gpsConfig()->gps_use_3d_speed) + BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_GPS_PROVIDER, "%d", gpsConfig()->provider); + BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_GPS_SET_HOME_POINT_ONCE, "%d", gpsConfig()->gps_set_home_point_once); + BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_GPS_USE_3D_SPEED, "%d", gpsConfig()->gps_use_3d_speed); #ifdef USE_GPS_RESCUE #ifndef USE_WING - BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_GPS_RESCUE_MIN_START_DIST, "%d", gpsRescueConfig()->minStartDistM) - BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_GPS_RESCUE_ALT_MODE, "%d", gpsRescueConfig()->altitudeMode) - BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_GPS_RESCUE_INITIAL_CLIMB, "%d", gpsRescueConfig()->initialClimbM) - BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_GPS_RESCUE_ASCEND_RATE, "%d", gpsRescueConfig()->ascendRate) + BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_GPS_RESCUE_MIN_START_DIST, "%d", gpsRescueConfig()->minStartDistM); + BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_GPS_RESCUE_ALT_MODE, "%d", gpsRescueConfig()->altitudeMode); + BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_GPS_RESCUE_INITIAL_CLIMB, "%d", gpsRescueConfig()->initialClimbM); + BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_GPS_RESCUE_ASCEND_RATE, "%d", gpsRescueConfig()->ascendRate); - BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_GPS_RESCUE_RETURN_ALT, "%d", gpsRescueConfig()->returnAltitudeM) - BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_GPS_RESCUE_GROUND_SPEED, "%d", gpsRescueConfig()->groundSpeedCmS) - BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_GPS_RESCUE_MAX_RESCUE_ANGLE, "%d", gpsRescueConfig()->maxRescueAngle) - BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_GPS_RESCUE_ROLL_MIX, "%d", gpsRescueConfig()->rollMix) - BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_GPS_RESCUE_PITCH_CUTOFF, "%d", gpsRescueConfig()->pitchCutoffHz) - BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_GPS_RESCUE_IMU_YAW_GAIN, "%d", gpsRescueConfig()->imuYawGain) + BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_GPS_RESCUE_RETURN_ALT, "%d", gpsRescueConfig()->returnAltitudeM); + BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_GPS_RESCUE_GROUND_SPEED, "%d", gpsRescueConfig()->groundSpeedCmS); + BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_GPS_RESCUE_MAX_RESCUE_ANGLE, "%d", gpsRescueConfig()->maxRescueAngle); + BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_GPS_RESCUE_ROLL_MIX, "%d", gpsRescueConfig()->rollMix); + BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_GPS_RESCUE_PITCH_CUTOFF, "%d", gpsRescueConfig()->pitchCutoffHz); + BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_GPS_RESCUE_IMU_YAW_GAIN, "%d", gpsRescueConfig()->imuYawGain); - BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_GPS_RESCUE_DESCENT_DIST, "%d", gpsRescueConfig()->descentDistanceM) - BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_GPS_RESCUE_DESCEND_RATE, "%d", gpsRescueConfig()->descendRate) - BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_GPS_RESCUE_DISARM_THRESHOLD, "%d", gpsRescueConfig()->disarmThreshold) + BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_GPS_RESCUE_DESCENT_DIST, "%d", gpsRescueConfig()->descentDistanceM); + BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_GPS_RESCUE_DESCEND_RATE, "%d", gpsRescueConfig()->descendRate); + BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_GPS_RESCUE_DISARM_THRESHOLD, "%d", gpsRescueConfig()->disarmThreshold); - BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_GPS_RESCUE_SANITY_CHECKS, "%d", gpsRescueConfig()->sanityChecks) - BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_GPS_RESCUE_MIN_SATS, "%d", gpsRescueConfig()->minSats) - BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_GPS_RESCUE_ALLOW_ARMING_WITHOUT_FIX, "%d", gpsRescueConfig()->allowArmingWithoutFix) + BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_GPS_RESCUE_SANITY_CHECKS, "%d", gpsRescueConfig()->sanityChecks); + BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_GPS_RESCUE_MIN_SATS, "%d", gpsRescueConfig()->minSats); + BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_GPS_RESCUE_ALLOW_ARMING_WITHOUT_FIX, "%d", gpsRescueConfig()->allowArmingWithoutFix); - BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_GPS_RESCUE_VELOCITY_P, "%d", gpsRescueConfig()->velP) - BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_GPS_RESCUE_VELOCITY_I, "%d", gpsRescueConfig()->velI) - BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_GPS_RESCUE_VELOCITY_D, "%d", gpsRescueConfig()->velD) - BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_GPS_RESCUE_YAW_P, "%d", gpsRescueConfig()->yawP) + BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_GPS_RESCUE_VELOCITY_P, "%d", gpsRescueConfig()->velP); + BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_GPS_RESCUE_VELOCITY_I, "%d", gpsRescueConfig()->velI); + BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_GPS_RESCUE_VELOCITY_D, "%d", gpsRescueConfig()->velD); + BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_GPS_RESCUE_YAW_P, "%d", gpsRescueConfig()->yawP); #ifdef USE_MAG - BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_GPS_RESCUE_USE_MAG, "%d", gpsRescueConfig()->useMag) + BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_GPS_RESCUE_USE_MAG, "%d", gpsRescueConfig()->useMag); #endif // USE_MAG #endif // !USE_WING #endif // USE_GPS_RESCUE @@ -1832,15 +1835,15 @@ static bool blackboxWriteSysinfo(void) #ifdef USE_ALTITUDE_HOLD #ifndef USE_WING - BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_ALT_HOLD_THROTTLE_RESPONSE, "%d", altHoldConfig()->alt_hold_adjust_rate); - BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_ALT_HOLD_DEADBAND, "%d", altHoldConfig()->alt_hold_deadband); + BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_ALT_HOLD_CLIMB_RATE, "%d", altHoldConfig()->climbRate); + BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_ALT_HOLD_DEADBAND, "%d", altHoldConfig()->deadband); #endif // !USE_WING #endif // USE_ALTITUDE_HOLD #ifdef USE_POSITION_HOLD #ifndef USE_WING - BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_POS_HOLD_WITHOUT_MAG, "%d", posHoldConfig()->pos_hold_without_mag); - BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_POS_HOLD_DEADBAND, "%d", posHoldConfig()->pos_hold_deadband); + BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_POS_HOLD_WITHOUT_MAG, "%d", posHoldConfig()->posHoldWithoutMag); + BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_POS_HOLD_DEADBAND, "%d", posHoldConfig()->deadband); #endif // !USE_WING #endif diff --git a/src/main/cli/settings.c b/src/main/cli/settings.c index 82df9227dd..cc5ef8571d 100644 --- a/src/main/cli/settings.c +++ b/src/main/cli/settings.c @@ -1155,15 +1155,15 @@ const clivalue_t valueTable[] = { #ifdef USE_ALTITUDE_HOLD #ifndef USE_WING - { PARAM_NAME_ALT_HOLD_THROTTLE_RESPONSE, VAR_UINT8 | MASTER_VALUE, .config.minmaxUnsigned = { 0, 200 }, PG_ALTHOLD_CONFIG, offsetof(altHoldConfig_t, alt_hold_adjust_rate) }, - { PARAM_NAME_ALT_HOLD_DEADBAND, VAR_UINT8 | MASTER_VALUE, .config.minmaxUnsigned = { 0, 70 }, PG_ALTHOLD_CONFIG, offsetof(altHoldConfig_t, alt_hold_deadband) }, + { PARAM_NAME_ALT_HOLD_CLIMB_RATE, VAR_UINT8 | MASTER_VALUE, .config.minmaxUnsigned = { 0, 200 }, PG_ALTHOLD_CONFIG, offsetof(altHoldConfig_t, climbRate) }, + { PARAM_NAME_ALT_HOLD_DEADBAND, VAR_UINT8 | MASTER_VALUE, .config.minmaxUnsigned = { 0, 70 }, PG_ALTHOLD_CONFIG, offsetof(altHoldConfig_t, deadband) }, #endif // !USE_WING #endif // USE_ALTITUDE_HOLD #ifdef USE_POSITION_HOLD #ifndef USE_WING - { PARAM_NAME_POS_HOLD_WITHOUT_MAG, VAR_UINT8 | MASTER_VALUE | MODE_LOOKUP, .config.lookup = { TABLE_OFF_ON }, PG_POSHOLD_CONFIG, offsetof(posHoldConfig_t, pos_hold_without_mag) }, - { PARAM_NAME_POS_HOLD_DEADBAND, VAR_UINT8 | MASTER_VALUE, .config.minmaxUnsigned = { 0, 50 }, PG_POSHOLD_CONFIG, offsetof(posHoldConfig_t, pos_hold_deadband) }, + { PARAM_NAME_POS_HOLD_WITHOUT_MAG, VAR_UINT8 | MASTER_VALUE | MODE_LOOKUP, .config.lookup = { TABLE_OFF_ON }, PG_POSHOLD_CONFIG, offsetof(posHoldConfig_t, posHoldWithoutMag) }, + { PARAM_NAME_POS_HOLD_DEADBAND, VAR_UINT8 | MASTER_VALUE, .config.minmaxUnsigned = { 0, 50 }, PG_POSHOLD_CONFIG, offsetof(posHoldConfig_t, deadband) }, #endif // !USE_WING #endif // USE_POSITION_HOLD @@ -1918,20 +1918,20 @@ const clivalue_t valueTable[] = { // PG_AUTOPILOT #ifndef USE_WING - { PARAM_NAME_LANDING_ALTITUDE, VAR_UINT8 | MASTER_VALUE, .config.minmaxUnsigned = { 0, 200 }, PG_AUTOPILOT, offsetof(apConfig_t, landing_altitude_m) }, - { PARAM_NAME_HOVER_THROTTLE, VAR_UINT16 | MASTER_VALUE, .config.minmaxUnsigned = { 1100, 1700 }, PG_AUTOPILOT, offsetof(apConfig_t, hover_throttle) }, - { PARAM_NAME_THROTTLE_MIN, VAR_UINT16 | MASTER_VALUE, .config.minmaxUnsigned = { 1050, 1400 }, PG_AUTOPILOT, offsetof(apConfig_t, throttle_min) }, - { PARAM_NAME_THROTTLE_MAX, VAR_UINT16 | MASTER_VALUE, .config.minmaxUnsigned = { 1400, 2000 }, PG_AUTOPILOT, offsetof(apConfig_t, throttle_max) }, - { PARAM_NAME_ALTITUDE_P, VAR_UINT8 | MASTER_VALUE, .config.minmaxUnsigned = { 0, 200 }, PG_AUTOPILOT, offsetof(apConfig_t, altitude_P) }, - { PARAM_NAME_ALTITUDE_I, VAR_UINT8 | MASTER_VALUE, .config.minmaxUnsigned = { 0, 200 }, PG_AUTOPILOT, offsetof(apConfig_t, altitude_I) }, - { PARAM_NAME_ALTITUDE_D, VAR_UINT8 | MASTER_VALUE, .config.minmaxUnsigned = { 0, 200 }, PG_AUTOPILOT, offsetof(apConfig_t, altitude_D) }, - { PARAM_NAME_ALTITUDE_F, VAR_UINT8 | MASTER_VALUE, .config.minmaxUnsigned = { 0, 200 }, PG_AUTOPILOT, offsetof(apConfig_t, altitude_F) }, - { PARAM_NAME_POSITION_P, VAR_UINT8 | MASTER_VALUE, .config.minmaxUnsigned = { 0, 200 }, PG_AUTOPILOT, offsetof(apConfig_t, position_P) }, - { PARAM_NAME_POSITION_I, VAR_UINT8 | MASTER_VALUE, .config.minmaxUnsigned = { 0, 200 }, PG_AUTOPILOT, offsetof(apConfig_t, position_I) }, - { PARAM_NAME_POSITION_D, VAR_UINT8 | MASTER_VALUE, .config.minmaxUnsigned = { 0, 200 }, PG_AUTOPILOT, offsetof(apConfig_t, position_D) }, - { PARAM_NAME_POSITION_A, VAR_UINT8 | MASTER_VALUE, .config.minmaxUnsigned = { 0, 200 }, PG_AUTOPILOT, offsetof(apConfig_t, position_A) }, - { PARAM_NAME_POSITION_CUTOFF, VAR_UINT8 | MASTER_VALUE, .config.minmaxUnsigned = { 10, 250 }, PG_AUTOPILOT, offsetof(apConfig_t, position_cutoff) }, - { PARAM_NAME_AP_MAX_ANGLE, VAR_UINT8 | MASTER_VALUE, .config.minmaxUnsigned = { 10, 70 }, PG_AUTOPILOT, offsetof(apConfig_t, max_angle) }, + { PARAM_NAME_AP_LANDING_ALTITUDE_M, VAR_UINT8 | MASTER_VALUE, .config.minmaxUnsigned = { 0, 200 }, PG_AUTOPILOT, offsetof(autopilotConfig_t, landingAltitudeM) }, + { PARAM_NAME_AP_HOVER_THROTTLE, VAR_UINT16 | MASTER_VALUE, .config.minmaxUnsigned = { 1100, 1700 }, PG_AUTOPILOT, offsetof(autopilotConfig_t, hoverThrottle) }, + { PARAM_NAME_AP_THROTTLE_MIN, VAR_UINT16 | MASTER_VALUE, .config.minmaxUnsigned = { 1050, 1400 }, PG_AUTOPILOT, offsetof(autopilotConfig_t, throttleMin) }, + { PARAM_NAME_AP_THROTTLE_MAX, VAR_UINT16 | MASTER_VALUE, .config.minmaxUnsigned = { 1400, 2000 }, PG_AUTOPILOT, offsetof(autopilotConfig_t, throttleMax) }, + { PARAM_NAME_AP_ALTITUDE_P, VAR_UINT8 | MASTER_VALUE, .config.minmaxUnsigned = { 0, 200 }, PG_AUTOPILOT, offsetof(autopilotConfig_t, altitudeP) }, + { PARAM_NAME_AP_ALTITUDE_I, VAR_UINT8 | MASTER_VALUE, .config.minmaxUnsigned = { 0, 200 }, PG_AUTOPILOT, offsetof(autopilotConfig_t, altitudeI) }, + { PARAM_NAME_AP_ALTITUDE_D, VAR_UINT8 | MASTER_VALUE, .config.minmaxUnsigned = { 0, 200 }, PG_AUTOPILOT, offsetof(autopilotConfig_t, altitudeD) }, + { PARAM_NAME_AP_ALTITUDE_F, VAR_UINT8 | MASTER_VALUE, .config.minmaxUnsigned = { 0, 200 }, PG_AUTOPILOT, offsetof(autopilotConfig_t, altitudeF) }, + { PARAM_NAME_AP_POSITION_P, VAR_UINT8 | MASTER_VALUE, .config.minmaxUnsigned = { 0, 200 }, PG_AUTOPILOT, offsetof(autopilotConfig_t, positionP) }, + { PARAM_NAME_AP_POSITION_I, VAR_UINT8 | MASTER_VALUE, .config.minmaxUnsigned = { 0, 200 }, PG_AUTOPILOT, offsetof(autopilotConfig_t, positionI) }, + { PARAM_NAME_AP_POSITION_D, VAR_UINT8 | MASTER_VALUE, .config.minmaxUnsigned = { 0, 200 }, PG_AUTOPILOT, offsetof(autopilotConfig_t, positionD) }, + { PARAM_NAME_AP_POSITION_A, VAR_UINT8 | MASTER_VALUE, .config.minmaxUnsigned = { 0, 200 }, PG_AUTOPILOT, offsetof(autopilotConfig_t, positionA) }, + { PARAM_NAME_AP_POSITION_CUTOFF, VAR_UINT8 | MASTER_VALUE, .config.minmaxUnsigned = { 10, 250 }, PG_AUTOPILOT, offsetof(autopilotConfig_t, positionCutoff) }, + { PARAM_NAME_AP_MAX_ANGLE, VAR_UINT8 | MASTER_VALUE, .config.minmaxUnsigned = { 10, 70 }, PG_AUTOPILOT, offsetof(autopilotConfig_t, maxAngle) }, #endif // !USE_WING // PG_MODE_ACTIVATION_CONFIG diff --git a/src/main/cms/cms_menu_gps_rescue_multirotor.c b/src/main/cms/cms_menu_gps_rescue_multirotor.c index a6520d0734..d4826c3d4d 100644 --- a/src/main/cms/cms_menu_gps_rescue_multirotor.c +++ b/src/main/cms/cms_menu_gps_rescue_multirotor.c @@ -55,16 +55,16 @@ static uint8_t gpsRescueConfig_angle; //degrees static uint16_t gpsRescueConfig_descentDistanceM; //meters static uint16_t gpsRescueConfig_descendRate; -static uint8_t apConfig_landingAltitudeM; +static uint8_t autopilotConfig_landingAltitudeM; -static uint16_t apConfig_throttleMin; -static uint16_t apConfig_throttleMax; -static uint16_t apConfig_hoverThrottle; +static uint16_t autopilotConfig_throttleMin; +static uint16_t autopilotConfig_throttleMax; +static uint16_t autopilotConfig_hoverThrottle; static uint8_t gpsRescueConfig_minSats; static uint8_t gpsRescueConfig_allowArmingWithoutFix; -static uint8_t apConfig_altitude_P, apConfig_altitude_I, apConfig_altitude_D, apConfig_altitude_F; +static uint8_t autopilotConfig_altitude_P, autopilotConfig_altitude_I, autopilotConfig_altitude_D, autopilotConfig_altitude_F; static uint8_t gpsRescueConfig_yawP; static uint8_t gpsRescueConfig_velP, gpsRescueConfig_velI, gpsRescueConfig_velD; @@ -75,10 +75,10 @@ static const void *cms_menuGpsRescuePidOnEnter(displayPort_t *pDisp) { UNUSED(pDisp); - apConfig_altitude_P = apConfig()->altitude_P; - apConfig_altitude_I = apConfig()->altitude_I; - apConfig_altitude_D = apConfig()->altitude_D; - apConfig_altitude_F = apConfig()->altitude_F; + autopilotConfig_altitude_P = autopilotConfig()->altitudeP; + autopilotConfig_altitude_I = autopilotConfig()->altitudeI; + autopilotConfig_altitude_D = autopilotConfig()->altitudeD; + autopilotConfig_altitude_F = autopilotConfig()->altitudeF; gpsRescueConfig_yawP = gpsRescueConfig()->yawP; @@ -97,10 +97,10 @@ static const void *cms_menuGpsRescuePidOnExit(displayPort_t *pDisp, const OSD_En UNUSED(pDisp); UNUSED(self); - apConfigMutable()->altitude_P = apConfig_altitude_P; - apConfigMutable()->altitude_I = apConfig_altitude_I; - apConfigMutable()->altitude_D = apConfig_altitude_D; - apConfigMutable()->altitude_F = apConfig_altitude_F; + autopilotConfigMutable()->altitudeP = autopilotConfig_altitude_P; + autopilotConfigMutable()->altitudeI = autopilotConfig_altitude_I; + autopilotConfigMutable()->altitudeD = autopilotConfig_altitude_D; + autopilotConfigMutable()->altitudeF = autopilotConfig_altitude_F; gpsRescueConfigMutable()->yawP = gpsRescueConfig_yawP; @@ -118,10 +118,10 @@ const OSD_Entry cms_menuGpsRescuePidEntries[] = { {"--- GPS RESCUE PID---", OME_Label, NULL, NULL}, - { "ALTITUDE P", OME_UINT8 | REBOOT_REQUIRED, NULL, &(OSD_UINT8_t){ &apConfig_altitude_P, 0, 200, 1 } }, - { "ALTITUDE I", OME_UINT8 | REBOOT_REQUIRED, NULL, &(OSD_UINT8_t){ &apConfig_altitude_I, 0, 200, 1 } }, - { "ALTITUDE D", OME_UINT8 | REBOOT_REQUIRED, NULL, &(OSD_UINT8_t){ &apConfig_altitude_D, 0, 200, 1 } }, - { "ALTITUDE F", OME_UINT8 | REBOOT_REQUIRED, NULL, &(OSD_UINT8_t){ &apConfig_altitude_F, 0, 200, 1 } }, + { "ALTITUDE P", OME_UINT8 | REBOOT_REQUIRED, NULL, &(OSD_UINT8_t){ &autopilotConfig_altitude_P, 0, 200, 1 } }, + { "ALTITUDE I", OME_UINT8 | REBOOT_REQUIRED, NULL, &(OSD_UINT8_t){ &autopilotConfig_altitude_I, 0, 200, 1 } }, + { "ALTITUDE D", OME_UINT8 | REBOOT_REQUIRED, NULL, &(OSD_UINT8_t){ &autopilotConfig_altitude_D, 0, 200, 1 } }, + { "ALTITUDE F", OME_UINT8 | REBOOT_REQUIRED, NULL, &(OSD_UINT8_t){ &autopilotConfig_altitude_F, 0, 200, 1 } }, { "YAW P", OME_UINT8 | REBOOT_REQUIRED, NULL, &(OSD_UINT8_t){ &gpsRescueConfig_yawP, 0, 200, 1 } }, @@ -162,11 +162,11 @@ static const void *cmsx_menuGpsRescueOnEnter(displayPort_t *pDisp) gpsRescueConfig_descentDistanceM = gpsRescueConfig()->descentDistanceM; gpsRescueConfig_descendRate = gpsRescueConfig()->descendRate; - apConfig_landingAltitudeM = apConfig()->landing_altitude_m; + autopilotConfig_landingAltitudeM = autopilotConfig()->landingAltitudeM; - apConfig_throttleMin = apConfig()->throttle_min; - apConfig_throttleMax = apConfig()->throttle_max; - apConfig_hoverThrottle = apConfig()->hover_throttle; + autopilotConfig_throttleMin = autopilotConfig()->throttleMin; + autopilotConfig_throttleMax = autopilotConfig()->throttleMax; + autopilotConfig_hoverThrottle = autopilotConfig()->hoverThrottle; gpsRescueConfig_minSats = gpsRescueConfig()->minSats; gpsRescueConfig_allowArmingWithoutFix = gpsRescueConfig()->allowArmingWithoutFix; @@ -190,11 +190,11 @@ static const void *cmsx_menuGpsRescueOnExit(displayPort_t *pDisp, const OSD_Entr gpsRescueConfigMutable()->descentDistanceM = gpsRescueConfig_descentDistanceM; gpsRescueConfigMutable()->descendRate = gpsRescueConfig_descendRate; - apConfigMutable()->landing_altitude_m = apConfig_landingAltitudeM; + autopilotConfigMutable()->landingAltitudeM = autopilotConfig_landingAltitudeM; - apConfigMutable()->throttle_min = apConfig_throttleMin; - apConfigMutable()->throttle_max = apConfig_throttleMax; - apConfigMutable()->hover_throttle = apConfig_hoverThrottle; + autopilotConfigMutable()->throttleMin = autopilotConfig_throttleMin; + autopilotConfigMutable()->throttleMax = autopilotConfig_throttleMax; + autopilotConfigMutable()->hoverThrottle = autopilotConfig_hoverThrottle; gpsRescueConfigMutable()->minSats = gpsRescueConfig_minSats; gpsRescueConfigMutable()->allowArmingWithoutFix = gpsRescueConfig_allowArmingWithoutFix; @@ -217,11 +217,11 @@ const OSD_Entry cmsx_menuGpsRescueEntries[] = { "DESCENT DIST M", OME_UINT16 | REBOOT_REQUIRED, NULL, &(OSD_UINT16_t){ &gpsRescueConfig_descentDistanceM, 5, 500, 1 } }, { "DESCENT RATE CM/S", OME_UINT16 | REBOOT_REQUIRED, NULL, &(OSD_UINT16_t){ &gpsRescueConfig_descendRate, 25, 500, 1 } }, - { "LANDING ALT M", OME_UINT8 | REBOOT_REQUIRED, NULL, &(OSD_UINT8_t) { &apConfig_landingAltitudeM, 1, 15, 1 } }, + { "LANDING ALT M", OME_UINT8 | REBOOT_REQUIRED, NULL, &(OSD_UINT8_t) { &autopilotConfig_landingAltitudeM, 1, 15, 1 } }, - { "THROTTLE MIN", OME_UINT16 | REBOOT_REQUIRED, NULL, &(OSD_UINT16_t){ &apConfig_throttleMin, 1050, 1400, 1 } }, - { "THROTTLE MAX", OME_UINT16 | REBOOT_REQUIRED, NULL, &(OSD_UINT16_t){ &apConfig_throttleMax, 1400, 2000, 1 } }, - { "THROTTLE HOV", OME_UINT16 | REBOOT_REQUIRED, NULL, &(OSD_UINT16_t){ &apConfig_hoverThrottle, 1100, 1700, 1 } }, + { "THROTTLE MIN", OME_UINT16 | REBOOT_REQUIRED, NULL, &(OSD_UINT16_t){ &autopilotConfig_throttleMin, 1050, 1400, 1 } }, + { "THROTTLE MAX", OME_UINT16 | REBOOT_REQUIRED, NULL, &(OSD_UINT16_t){ &autopilotConfig_throttleMax, 1400, 2000, 1 } }, + { "THROTTLE HOV", OME_UINT16 | REBOOT_REQUIRED, NULL, &(OSD_UINT16_t){ &autopilotConfig_hoverThrottle, 1100, 1700, 1 } }, { "SATS REQUIRED", OME_UINT8 | REBOOT_REQUIRED, NULL, &(OSD_UINT8_t){ &gpsRescueConfig_minSats, 5, 50, 1 } }, { "ARM WITHOUT FIX", OME_Bool | REBOOT_REQUIRED, NULL, &gpsRescueConfig_allowArmingWithoutFix }, diff --git a/src/main/fc/parameter_names.h b/src/main/fc/parameter_names.h index e677b6fe26..070a516d6e 100644 --- a/src/main/fc/parameter_names.h +++ b/src/main/fc/parameter_names.h @@ -161,20 +161,20 @@ #define PARAM_NAME_ALTITUDE_LPF "altitude_lpf" #define PARAM_NAME_ALTITUDE_D_LPF "altitude_d_lpf" -#define PARAM_NAME_HOVER_THROTTLE "hover_throttle" -#define PARAM_NAME_LANDING_ALTITUDE "landing_altitude_m" -#define PARAM_NAME_THROTTLE_MIN "autopilot_throttle_min" -#define PARAM_NAME_THROTTLE_MAX "autopilot_throttle_max" -#define PARAM_NAME_ALTITUDE_P "autopilot_altitude_P" -#define PARAM_NAME_ALTITUDE_I "autopilot_altitude_I" -#define PARAM_NAME_ALTITUDE_D "autopilot_altitude_D" -#define PARAM_NAME_ALTITUDE_F "autopilot_altitude_F" -#define PARAM_NAME_POSITION_P "autopilot_position_P" -#define PARAM_NAME_POSITION_I "autopilot_position_I" -#define PARAM_NAME_POSITION_D "autopilot_position_D" -#define PARAM_NAME_POSITION_A "autopilot_position_A" -#define PARAM_NAME_POSITION_CUTOFF "autopilot_position_cutoff" -#define PARAM_NAME_AP_MAX_ANGLE "autopilot_max_angle" +#define PARAM_NAME_AP_LANDING_ALTITUDE_M "ap_landing_altitude_m" +#define PARAM_NAME_AP_HOVER_THROTTLE "ap_hover_throttle" +#define PARAM_NAME_AP_THROTTLE_MIN "ap_throttle_min" +#define PARAM_NAME_AP_THROTTLE_MAX "ap_throttle_max" +#define PARAM_NAME_AP_ALTITUDE_P "ap_altitude_p" +#define PARAM_NAME_AP_ALTITUDE_I "ap_altitude_i" +#define PARAM_NAME_AP_ALTITUDE_D "ap_altitude_d" +#define PARAM_NAME_AP_ALTITUDE_F "ap_altitude_f" +#define PARAM_NAME_AP_POSITION_P "ap_position_p" +#define PARAM_NAME_AP_POSITION_I "ap_position_i" +#define PARAM_NAME_AP_POSITION_D "ap_position_d" +#define PARAM_NAME_AP_POSITION_A "ap_position_a" +#define PARAM_NAME_AP_POSITION_CUTOFF "ap_position_cutoff" +#define PARAM_NAME_AP_MAX_ANGLE "ap_max_angle" #define PARAM_NAME_ANGLE_FEEDFORWARD "angle_feedforward" #define PARAM_NAME_ANGLE_FF_SMOOTHING_MS "angle_feedforward_smoothing_ms" @@ -259,7 +259,7 @@ #ifdef USE_ALTITUDE_HOLD #define PARAM_NAME_ALT_HOLD_DEADBAND "alt_hold_deadband" -#define PARAM_NAME_ALT_HOLD_THROTTLE_RESPONSE "alt_hold_throttle_response" +#define PARAM_NAME_ALT_HOLD_CLIMB_RATE "alt_hold_climb_rate" #endif #ifdef USE_POSITION_HOLD diff --git a/src/main/flight/alt_hold_multirotor.c b/src/main/flight/alt_hold_multirotor.c index 68db59a12c..ff04c70f9a 100644 --- a/src/main/flight/alt_hold_multirotor.c +++ b/src/main/flight/alt_hold_multirotor.c @@ -62,9 +62,9 @@ static void altHoldReset(void) void altHoldInit(void) { altHold.isActive = false; - altHold.deadband = altHoldConfig()->alt_hold_deadband / 100.0f; - altHold.allowStickAdjustment = altHoldConfig()->alt_hold_deadband; - altHold.maxVelocity = altHoldConfig()->alt_hold_adjust_rate * 10.0f; // 50 in CLI means 500cm/s + altHold.deadband = altHoldConfig()->deadband / 100.0f; + altHold.allowStickAdjustment = altHoldConfig()->deadband; + altHold.maxVelocity = altHoldConfig()->climbRate * 10.0f; // 50 in CLI means 500cm/s altHoldReset(); } @@ -81,7 +81,7 @@ static void altHoldProcessTransitions(void) { // ** the transition out of alt hold (exiting altHold) may be rough. Some notes... ** // The original PR had a gradual transition from hold throttle to pilot control throttle - // using !(altHoldRequested && altHold.isAltHoldActive) to run an exit function + // using !(altHoldRequested && altHold.isActive) to run an exit function // a cross-fade factor was sent to mixer.c based on time since the flight mode request was terminated // it was removed primarily to simplify this PR @@ -101,8 +101,8 @@ static void altHoldUpdateTargetAltitude(void) if (altHold.allowStickAdjustment && calculateThrottleStatus() != THROTTLE_LOW) { const float rcThrottle = rcCommand[THROTTLE]; - const float lowThreshold = apConfig()->hover_throttle - altHold.deadband * (apConfig()->hover_throttle - PWM_RANGE_MIN); - const float highThreshold = apConfig()->hover_throttle + altHold.deadband * (PWM_RANGE_MAX - apConfig()->hover_throttle); + const float lowThreshold = autopilotConfig()->hoverThrottle - altHold.deadband * (autopilotConfig()->hoverThrottle - PWM_RANGE_MIN); + const float highThreshold = autopilotConfig()->hoverThrottle + altHold.deadband * (PWM_RANGE_MAX - autopilotConfig()->hoverThrottle); if (rcThrottle < lowThreshold) { stickFactor = scaleRangef(rcThrottle, PWM_RANGE_MIN, lowThreshold, -1.0f, 0.0f); @@ -136,7 +136,7 @@ static void altHoldUpdateTargetAltitude(void) static void altHoldUpdate(void) { // check if the user has changed the target altitude using sticks - if (altHoldConfig()->alt_hold_adjust_rate) { + if (altHoldConfig()->climbRate) { altHoldUpdateTargetAltitude(); } altitudeControl(altHold.targetAltitudeCm, taskIntervalSeconds, altHold.targetVelocity); diff --git a/src/main/flight/autopilot_multirotor.c b/src/main/flight/autopilot_multirotor.c index 00eff1555b..cd42049226 100644 --- a/src/main/flight/autopilot_multirotor.c +++ b/src/main/flight/autopilot_multirotor.c @@ -138,23 +138,22 @@ void resetPositionControl(const gpsLocation_t *initialTargetLocation, unsigned t void autopilotInit(void) { - const apConfig_t *cfg = apConfig(); - + const autopilotConfig_t *cfg = autopilotConfig(); ap.sticksActive = false; - ap.maxAngle = cfg->max_angle; - altitudePidCoeffs.Kp = cfg->altitude_P * ALTITUDE_P_SCALE; - altitudePidCoeffs.Ki = cfg->altitude_I * ALTITUDE_I_SCALE; - altitudePidCoeffs.Kd = cfg->altitude_D * ALTITUDE_D_SCALE; - altitudePidCoeffs.Kf = cfg->altitude_F * ALTITUDE_F_SCALE; - positionPidCoeffs.Kp = cfg->position_P * POSITION_P_SCALE; - positionPidCoeffs.Ki = cfg->position_I * POSITION_I_SCALE; - positionPidCoeffs.Kd = cfg->position_D * POSITION_D_SCALE; - positionPidCoeffs.Kf = cfg->position_A * POSITION_A_SCALE; // Kf used for acceleration + ap.maxAngle = cfg->maxAngle; + altitudePidCoeffs.Kp = cfg->altitudeP * ALTITUDE_P_SCALE; + altitudePidCoeffs.Ki = cfg->altitudeI * ALTITUDE_I_SCALE; + altitudePidCoeffs.Kd = cfg->altitudeD * ALTITUDE_D_SCALE; + altitudePidCoeffs.Kf = cfg->altitudeF * ALTITUDE_F_SCALE; + positionPidCoeffs.Kp = cfg->positionP * POSITION_P_SCALE; + positionPidCoeffs.Ki = cfg->positionI * POSITION_I_SCALE; + positionPidCoeffs.Kd = cfg->positionD * POSITION_D_SCALE; + positionPidCoeffs.Kf = cfg->positionA * POSITION_A_SCALE; // Kf used for acceleration // initialise filters with approximate filter gains; location isn't used at this point. ap.upsampleLpfGain = pt3FilterGain(UPSAMPLING_CUTOFF_HZ, 0.01f); // 5Hz, assuming 100Hz task rate at init resetUpsampleFilters(); // Initialise PT1 filters for velocity and acceleration in earth frame axes - ap.vaLpfCutoff = cfg->position_cutoff * 0.01f; + ap.vaLpfCutoff = cfg->positionCutoff * 0.01f; const float vaGain = pt1FilterGain(ap.vaLpfCutoff, 0.1f); // assume 10Hz GPS connection at start; value is overwritten before first filter use for (unsigned i = 0; i < ARRAYLEN(ap.efAxis); i++) { resetEFAxisFilters(&ap.efAxis[i], vaGain); @@ -193,7 +192,7 @@ void altitudeControl(float targetAltitudeCm, float taskIntervalS, float targetAl const float altitudeF = targetAltitudeStep * altitudePidCoeffs.Kf; - const float hoverOffset = apConfig()->hover_throttle - PWM_RANGE_MIN; + const float hoverOffset = autopilotConfig()->hoverThrottle - PWM_RANGE_MIN; float throttleOffset = altitudeP + altitudeI - altitudeD + altitudeF + hoverOffset; const float tiltMultiplier = 1.0f / fmaxf(getCosTiltAngle(), 0.5f); @@ -203,7 +202,7 @@ void altitudeControl(float targetAltitudeCm, float taskIntervalS, float targetAl throttleOffset *= tiltMultiplier; float newThrottle = PWM_RANGE_MIN + throttleOffset; - newThrottle = constrainf(newThrottle, apConfig()->throttle_min, apConfig()->throttle_max); + newThrottle = constrainf(newThrottle, autopilotConfig()->throttleMin, autopilotConfig()->throttleMax); DEBUG_SET(DEBUG_AUTOPILOT_ALTITUDE, 0, lrintf(newThrottle)); // normal range 1000-2000 but is before constraint newThrottle = scaleRangef(newThrottle, MAX(rxConfig()->mincheck, PWM_RANGE_MIN), PWM_RANGE_MAX, 0.0f, 1.0f); @@ -386,7 +385,7 @@ bool positionControl(void) bool isBelowLandingAltitude(void) { - return getAltitudeCm() < 100.0f * apConfig()->landing_altitude_m; + return getAltitudeCm() < 100.0f * autopilotConfig()->landingAltitudeM; } float getAutopilotThrottle(void) diff --git a/src/main/flight/gps_rescue_multirotor.c b/src/main/flight/gps_rescue_multirotor.c index cfb3b83feb..2321629ad0 100644 --- a/src/main/flight/gps_rescue_multirotor.c +++ b/src/main/flight/gps_rescue_multirotor.c @@ -630,7 +630,7 @@ static void descend(bool newGpsData) { if (newGpsData) { // consider landing area to be a circle half landing height around home, to avoid overshooting home point - const float distanceToLandingAreaM = rescueState.sensor.distanceToHomeM - (0.5f * apConfig()->landing_altitude_m); + const float distanceToLandingAreaM = rescueState.sensor.distanceToHomeM - (0.5f * autopilotConfig()->landingAltitudeM); const float proximityToLandingArea = constrainf(distanceToLandingAreaM / rescueState.intent.descentDistanceM, 0.0f, 1.0f); // increase the velocity lowpass filter cutoff for more aggressive responses when descending, especially close to home diff --git a/src/main/flight/pid.c b/src/main/flight/pid.c index dbc9b08da0..38dfdee169 100644 --- a/src/main/flight/pid.c +++ b/src/main/flight/pid.c @@ -586,7 +586,7 @@ STATIC_UNIT_TESTED FAST_CODE_NOINLINE float pidLevel(int axis, const pidProfile_ angleLimit = 85.0f; // allow autopilot to use whatever angle it needs to stop } // limit pilot requested angle to half the autopilot angle to avoid excess speed and chaotic stops - angleLimit = fminf(0.5f * apConfig()->max_angle, angleLimit); + angleLimit = fminf(0.5f * autopilotConfig()->maxAngle, angleLimit); } #endif diff --git a/src/main/flight/pos_hold_multirotor.c b/src/main/flight/pos_hold_multirotor.c index de4147a2df..ba977d8589 100644 --- a/src/main/flight/pos_hold_multirotor.c +++ b/src/main/flight/pos_hold_multirotor.c @@ -51,8 +51,8 @@ static posHoldState_t posHold; void posHoldInit(void) { - posHold.deadband = posHoldConfig()->pos_hold_deadband * 0.01f; - posHold.useStickAdjustment = posHoldConfig()->pos_hold_deadband; + posHold.deadband = posHoldConfig()->deadband * 0.01f; + posHold.useStickAdjustment = posHoldConfig()->deadband; } static void posHoldCheckSticks(void) @@ -73,7 +73,7 @@ static bool sensorsOk(void) #ifdef USE_MAG !compassIsHealthy() && #endif - (!posHoldConfig()->pos_hold_without_mag || !canUseGPSHeading)) { + (!posHoldConfig()->posHoldWithoutMag || !canUseGPSHeading)) { return false; } return true; diff --git a/src/main/msp/msp.c b/src/main/msp/msp.c index 0d39f90533..025df2fc7b 100644 --- a/src/main/msp/msp.c +++ b/src/main/msp/msp.c @@ -1530,9 +1530,9 @@ case MSP_NAME: sbufWriteU16(dst, gpsRescueConfig()->returnAltitudeM); sbufWriteU16(dst, gpsRescueConfig()->descentDistanceM); sbufWriteU16(dst, gpsRescueConfig()->groundSpeedCmS); - sbufWriteU16(dst, apConfig()->throttle_min); - sbufWriteU16(dst, apConfig()->throttle_max); - sbufWriteU16(dst, apConfig()->hover_throttle); + sbufWriteU16(dst, autopilotConfig()->throttleMin); + sbufWriteU16(dst, autopilotConfig()->throttleMax); + sbufWriteU16(dst, autopilotConfig()->hoverThrottle); sbufWriteU8(dst, gpsRescueConfig()->sanityChecks); sbufWriteU8(dst, gpsRescueConfig()->minSats); @@ -1548,9 +1548,9 @@ case MSP_NAME: break; case MSP_GPS_RESCUE_PIDS: - sbufWriteU16(dst, apConfig()->altitude_P); - sbufWriteU16(dst, apConfig()->altitude_I); - sbufWriteU16(dst, apConfig()->altitude_D); + sbufWriteU16(dst, autopilotConfig()->altitudeP); + sbufWriteU16(dst, autopilotConfig()->altitudeI); + sbufWriteU16(dst, autopilotConfig()->altitudeD); // altitude_F not implemented yet sbufWriteU16(dst, gpsRescueConfig()->velP); sbufWriteU16(dst, gpsRescueConfig()->velI); @@ -1797,7 +1797,7 @@ case MSP_NAME: sbufWriteU8(dst, rcControlsConfig()->deadband); sbufWriteU8(dst, rcControlsConfig()->yaw_deadband); #if defined(USE_POSITION_HOLD) && !defined(USE_WING) - sbufWriteU8(dst, posHoldConfig()->pos_hold_deadband); + sbufWriteU8(dst, posHoldConfig()->deadband); #else sbufWriteU8(dst, 0); #endif @@ -2901,9 +2901,9 @@ static mspResult_e mspProcessInCommand(mspDescriptor_t srcDesc, int16_t cmdMSP, gpsRescueConfigMutable()->returnAltitudeM = sbufReadU16(src); gpsRescueConfigMutable()->descentDistanceM = sbufReadU16(src); gpsRescueConfigMutable()->groundSpeedCmS = sbufReadU16(src); - apConfigMutable()->throttle_min = sbufReadU16(src); - apConfigMutable()->throttle_max = sbufReadU16(src); - apConfigMutable()->hover_throttle = sbufReadU16(src); + autopilotConfigMutable()->throttleMin = sbufReadU16(src); + autopilotConfigMutable()->throttleMax = sbufReadU16(src); + autopilotConfigMutable()->hoverThrottle = sbufReadU16(src); gpsRescueConfigMutable()->sanityChecks = sbufReadU8(src); gpsRescueConfigMutable()->minSats = sbufReadU8(src); if (sbufBytesRemaining(src) >= 6) { @@ -2924,9 +2924,9 @@ static mspResult_e mspProcessInCommand(mspDescriptor_t srcDesc, int16_t cmdMSP, break; case MSP_SET_GPS_RESCUE_PIDS: - apConfigMutable()->altitude_P = sbufReadU16(src); - apConfigMutable()->altitude_I = sbufReadU16(src); - apConfigMutable()->altitude_D = sbufReadU16(src); + autopilotConfigMutable()->altitudeP = sbufReadU16(src); + autopilotConfigMutable()->altitudeI = sbufReadU16(src); + autopilotConfigMutable()->altitudeD = sbufReadU16(src); // altitude_F not included in msp yet gpsRescueConfigMutable()->velP = sbufReadU16(src); gpsRescueConfigMutable()->velI = sbufReadU16(src); @@ -2990,7 +2990,7 @@ static mspResult_e mspProcessInCommand(mspDescriptor_t srcDesc, int16_t cmdMSP, rcControlsConfigMutable()->deadband = sbufReadU8(src); rcControlsConfigMutable()->yaw_deadband = sbufReadU8(src); #if defined(USE_POSITION_HOLD) && !defined(USE_WING) - posHoldConfigMutable()->pos_hold_deadband = sbufReadU8(src); + posHoldConfigMutable()->deadband = sbufReadU8(src); #else sbufReadU8(src); #endif diff --git a/src/main/pg/alt_hold_multirotor.c b/src/main/pg/alt_hold_multirotor.c index c229fcf66a..5c29527219 100644 --- a/src/main/pg/alt_hold_multirotor.c +++ b/src/main/pg/alt_hold_multirotor.c @@ -35,8 +35,8 @@ PG_REGISTER_WITH_RESET_TEMPLATE(altHoldConfig_t, altHoldConfig, PG_ALTHOLD_CONFIG, 4); PG_RESET_TEMPLATE(altHoldConfig_t, altHoldConfig, - .alt_hold_adjust_rate = 50, // max vertical velocity change at full/zero throttle. 50 means 5 m/s - .alt_hold_deadband = 20, // throttle deadband in percent of stick travel + .climbRate = 50, // max vertical velocity change at full/zero throttle. 50 means 5 m/s + .deadband = 20, // throttle deadband in percent of stick travel ); #endif diff --git a/src/main/pg/alt_hold_multirotor.h b/src/main/pg/alt_hold_multirotor.h index 88f0933b0c..2310328fe0 100644 --- a/src/main/pg/alt_hold_multirotor.h +++ b/src/main/pg/alt_hold_multirotor.h @@ -28,8 +28,8 @@ #include "pg/pg.h" typedef struct altHoldConfig_s { - uint8_t alt_hold_adjust_rate; - uint8_t alt_hold_deadband; + uint8_t climbRate; + uint8_t deadband; } altHoldConfig_t; PG_DECLARE(altHoldConfig_t, altHoldConfig); diff --git a/src/main/pg/autopilot_multirotor.c b/src/main/pg/autopilot_multirotor.c index 898cfdc205..7854c33c4b 100644 --- a/src/main/pg/autopilot_multirotor.c +++ b/src/main/pg/autopilot_multirotor.c @@ -30,23 +30,23 @@ #include "autopilot.h" -PG_REGISTER_WITH_RESET_TEMPLATE(apConfig_t, apConfig, PG_AUTOPILOT, 2); +PG_REGISTER_WITH_RESET_TEMPLATE(autopilotConfig_t, autopilotConfig, PG_AUTOPILOT, 2); -PG_RESET_TEMPLATE(apConfig_t, apConfig, - .landing_altitude_m = 4, - .hover_throttle = 1275, - .throttle_min = 1100, - .throttle_max = 1700, - .altitude_P = 15, - .altitude_I = 15, - .altitude_D = 15, - .altitude_F = 15, - .position_P = 30, - .position_I = 30, - .position_D = 30, - .position_A = 30, - .position_cutoff = 80, - .max_angle = 50, +PG_RESET_TEMPLATE(autopilotConfig_t, autopilotConfig, + .landingAltitudeM = 4, + .hoverThrottle = 1275, + .throttleMin = 1100, + .throttleMax = 1700, + .altitudeP = 15, + .altitudeI = 15, + .altitudeD = 15, + .altitudeF = 15, + .positionP = 30, + .positionI = 30, + .positionD = 30, + .positionA = 30, + .positionCutoff = 80, + .maxAngle = 50, ); #endif // !USE_WING diff --git a/src/main/pg/autopilot_multirotor.h b/src/main/pg/autopilot_multirotor.h index 6e1f6cfecd..978c9a0c92 100644 --- a/src/main/pg/autopilot_multirotor.h +++ b/src/main/pg/autopilot_multirotor.h @@ -27,23 +27,23 @@ #include "pg/pg.h" -typedef struct apConfig_s { - uint8_t landing_altitude_m; // altitude below which landing behaviours can change, metres - uint16_t hover_throttle; // value used at the start of a rescue or position hold - uint16_t throttle_min; - uint16_t throttle_max; - uint8_t altitude_P; - uint8_t altitude_I; - uint8_t altitude_D; - uint8_t altitude_F; - uint8_t position_P; - uint8_t position_I; - uint8_t position_D; - uint8_t position_A; - uint8_t position_cutoff; - uint8_t max_angle; -} apConfig_t; +typedef struct autopilotConfig_s { + uint8_t landingAltitudeM; // altitude below which landing behaviours can change, metres + uint16_t hoverThrottle; // value used at the start of a rescue or position hold + uint16_t throttleMin; + uint16_t throttleMax; + uint8_t altitudeP; + uint8_t altitudeI; + uint8_t altitudeD; + uint8_t altitudeF; + uint8_t positionP; + uint8_t positionI; + uint8_t positionD; + uint8_t positionA; + uint8_t positionCutoff; + uint8_t maxAngle; +} autopilotConfig_t; -PG_DECLARE(apConfig_t, apConfig); +PG_DECLARE(autopilotConfig_t, autopilotConfig); #endif // !USE_WING diff --git a/src/main/pg/autopilot_wing.c b/src/main/pg/autopilot_wing.c index 06dc476c1c..73a351f45f 100644 --- a/src/main/pg/autopilot_wing.c +++ b/src/main/pg/autopilot_wing.c @@ -30,9 +30,9 @@ #include "autopilot.h" -PG_REGISTER_WITH_RESET_TEMPLATE(apConfig_t, apConfig, PG_AUTOPILOT, 2); +PG_REGISTER_WITH_RESET_TEMPLATE(autopilotConfig_t, autopilotConfig, PG_AUTOPILOT, 2); -PG_RESET_TEMPLATE(apConfig_t, apConfig, +PG_RESET_TEMPLATE(autopilotConfig_t, autopilotConfig, ); #endif // USE_WING diff --git a/src/main/pg/autopilot_wing.h b/src/main/pg/autopilot_wing.h index ee01e0a6f9..567db81cc3 100644 --- a/src/main/pg/autopilot_wing.h +++ b/src/main/pg/autopilot_wing.h @@ -27,10 +27,10 @@ #include "pg/pg.h" -typedef struct apConfig_s { +typedef struct autopilotConfig_s { uint8_t dummy; -} apConfig_t; +} autopilotConfig_t; -PG_DECLARE(apConfig_t, apConfig); +PG_DECLARE(autopilotConfig_t, autopilotConfig); #endif // USE_WING diff --git a/src/main/pg/pos_hold_multirotor.c b/src/main/pg/pos_hold_multirotor.c index 2a7a332241..68e907165f 100644 --- a/src/main/pg/pos_hold_multirotor.c +++ b/src/main/pg/pos_hold_multirotor.c @@ -35,8 +35,8 @@ PG_REGISTER_WITH_RESET_TEMPLATE(posHoldConfig_t, posHoldConfig, PG_POSHOLD_CONFIG, 0); PG_RESET_TEMPLATE(posHoldConfig_t, posHoldConfig, - .pos_hold_without_mag = false, // position hold within this percentage stick deflection - .pos_hold_deadband = 5, // deadband in percent of stick travel for roll and pitch. Must be non-zero, and exceeded, for target location to be changed with sticks + .posHoldWithoutMag = false, // position hold within this percentage stick deflection + .deadband = 5, // deadband in percent of stick travel for roll and pitch. Must be non-zero, and exceeded, for target location to be changed with sticks ); #endif diff --git a/src/main/pg/pos_hold_multirotor.h b/src/main/pg/pos_hold_multirotor.h index 6187d9ba62..64f8f26716 100644 --- a/src/main/pg/pos_hold_multirotor.h +++ b/src/main/pg/pos_hold_multirotor.h @@ -28,8 +28,8 @@ #include "pg/pg.h" typedef struct posHoldConfig_s { - bool pos_hold_without_mag; - uint8_t pos_hold_deadband; + bool posHoldWithoutMag; + uint8_t deadband; } posHoldConfig_t; PG_DECLARE(posHoldConfig_t, posHoldConfig); diff --git a/src/test/unit/althold_unittest.cc b/src/test/unit/althold_unittest.cc index 4dbba143bb..98e1d93abc 100644 --- a/src/test/unit/althold_unittest.cc +++ b/src/test/unit/althold_unittest.cc @@ -50,7 +50,7 @@ extern "C" { PG_REGISTER(accelerometerConfig_t, accelerometerConfig, PG_ACCELEROMETER_CONFIG, 0); PG_REGISTER(altHoldConfig_t, altHoldConfig, PG_ALTHOLD_CONFIG, 0); - PG_REGISTER(apConfig_t, apConfig, PG_AUTOPILOT, 0); + PG_REGISTER(autopilotConfig_t, autopilotConfig, PG_AUTOPILOT, 0); PG_REGISTER(gyroConfig_t, gyroConfig, PG_GYRO_CONFIG, 0); PG_REGISTER(positionConfig_t, positionConfig, PG_POSITION, 0); PG_REGISTER(rcControlsConfig_t, rcControlsConfig, PG_RC_CONTROLS_CONFIG, 0); diff --git a/src/test/unit/arming_prevention_unittest.cc b/src/test/unit/arming_prevention_unittest.cc index 82b0df4ac1..8b92be036f 100644 --- a/src/test/unit/arming_prevention_unittest.cc +++ b/src/test/unit/arming_prevention_unittest.cc @@ -79,7 +79,7 @@ extern "C" { PG_REGISTER(gpsConfig_t, gpsConfig, PG_GPS_CONFIG, 0); PG_REGISTER(gpsRescueConfig_t, gpsRescueConfig, PG_GPS_RESCUE, 0); PG_REGISTER(positionConfig_t, positionConfig, PG_POSITION, 0); - PG_REGISTER(apConfig_t, apConfig, PG_AUTOPILOT, 0); + PG_REGISTER(autopilotConfig_t, autopilotConfig, PG_AUTOPILOT, 0); float rcData[MAX_SUPPORTED_RC_CHANNEL_COUNT]; uint16_t averageSystemLoadPercent = 0; diff --git a/src/test/unit/flight_imu_unittest.cc b/src/test/unit/flight_imu_unittest.cc index b8c1dda675..af839a3266 100644 --- a/src/test/unit/flight_imu_unittest.cc +++ b/src/test/unit/flight_imu_unittest.cc @@ -75,7 +75,7 @@ extern "C" { PG_REGISTER(rcControlsConfig_t, rcControlsConfig, PG_RC_CONTROLS_CONFIG, 0); PG_REGISTER(barometerConfig_t, barometerConfig, PG_BAROMETER_CONFIG, 0); PG_REGISTER(gpsConfig_t, gpsConfig, PG_GPS_CONFIG, 0); - PG_REGISTER(apConfig_t, apConfig, PG_AUTOPILOT, 0); + PG_REGISTER(autopilotConfig_t, autopilotConfig, PG_AUTOPILOT, 0); PG_RESET_TEMPLATE(featureConfig_t, featureConfig, .enabledFeatures = 0 From 6df8d0edda8bf5d32abea601b6ba43e66792c67d Mon Sep 17 00:00:00 2001 From: Mark Haslinghuis Date: Mon, 10 Feb 2025 15:38:25 +0100 Subject: [PATCH 111/244] Fix codestyle (#14245) Fix codestyle and prevent loop when commandLen is zero --- src/main/io/gps.c | 1299 +++++++++++++++++++++++---------------------- 1 file changed, 650 insertions(+), 649 deletions(-) diff --git a/src/main/io/gps.c b/src/main/io/gps.c index 129592a005..1343d5bb3a 100644 --- a/src/main/io/gps.c +++ b/src/main/io/gps.c @@ -425,10 +425,10 @@ void gpsInit(void) initBaudRateCycleCount = 0; gpsData.userBaudRateIndex = DEFAULT_BAUD_RATE_INDEX; for (unsigned i = 0; i < ARRAYLEN(gpsInitData); i++) { - if (gpsInitData[i].baudrateIndex == gpsPortConfig->gps_baudrateIndex) { - gpsData.userBaudRateIndex = i; - break; - } + if (gpsInitData[i].baudrateIndex == gpsPortConfig->gps_baudrateIndex) { + gpsData.userBaudRateIndex = i; + break; + } } // the user's intended baud rate will be used as the initial baud rate when connecting gpsData.tempBaudRateIndex = gpsData.userBaudRateIndex; @@ -462,44 +462,45 @@ void gpsInit(void) #ifdef USE_GPS_UBLOX const uint8_t ubloxUTCStandardConfig_int[5] = { - UBLOX_UTC_STANDARD_AUTO, - UBLOX_UTC_STANDARD_USNO, - UBLOX_UTC_STANDARD_EU, - UBLOX_UTC_STANDARD_SU, - UBLOX_UTC_STANDARD_NTSC + UBLOX_UTC_STANDARD_AUTO, + UBLOX_UTC_STANDARD_USNO, + UBLOX_UTC_STANDARD_EU, + UBLOX_UTC_STANDARD_SU, + UBLOX_UTC_STANDARD_NTSC }; struct ubloxVersion_s ubloxVersionMap[] = { - [UBX_VERSION_UNDEF] = {~0, "UNKNOWN"}, - [UBX_VERSION_M5] = {0x00040005, "M5"}, - [UBX_VERSION_M6] = {0x00040007, "M6"}, - [UBX_VERSION_M7] = {0x00070000, "M7"}, - [UBX_VERSION_M8] = {0x00080000, "M8"}, - [UBX_VERSION_M9] = {0x00190000, "M9"}, - [UBX_VERSION_M10] = {0x000A0000, "M10"}, + [UBX_VERSION_UNDEF] = { ~0, "UNKNOWN" }, + [UBX_VERSION_M5] = { 0x00040005, "M5" }, + [UBX_VERSION_M6] = { 0x00040007, "M6" }, + [UBX_VERSION_M7] = { 0x00070000, "M7" }, + [UBX_VERSION_M8] = { 0x00080000, "M8" }, + [UBX_VERSION_M9] = { 0x00190000, "M9" }, + [UBX_VERSION_M10] = { 0x000A0000, "M10" }, }; -static uint8_t ubloxAddValSet(ubxMessage_t * tx_buffer, ubxValGetSetBytes_e key, const uint8_t * payload, const uint8_t offset) { +static uint8_t ubloxAddValSet(ubxMessage_t * tx_buffer, ubxValGetSetBytes_e key, const uint8_t * payload, const uint8_t offset) +{ size_t len; switch((key >> (8 * 3)) & 0xff) { - case 0x10: - case 0x20: - len = 1; - break; - case 0x30: - len = 2; - break; - case 0x40: - len = 4; - break; - case 0x50: - len = 8; - break; - default: - return 0; + case 0x10: + case 0x20: + len = 1; + break; + case 0x30: + len = 2; + break; + case 0x40: + len = 4; + break; + case 0x50: + len = 8; + break; + default: + return 0; } - if (offset + 4 + len > MAX_VALSET_SIZE) - { + + if (offset + 4 + len > MAX_VALSET_SIZE) { return 0; } @@ -538,7 +539,8 @@ static size_t ubloxValGet(ubxMessage_t * tx_buffer, ubxValGetSetBytes_e key, ubl } #endif // not used -static uint8_t ubloxValSet(ubxMessage_t * tx_buffer, ubxValGetSetBytes_e key, uint8_t * payload, ubloxValLayer_e layer) { +static uint8_t ubloxValSet(ubxMessage_t * tx_buffer, ubxValGetSetBytes_e key, uint8_t * payload, ubloxValLayer_e layer) +{ memset(&tx_buffer->payload.cfg_valset, 0, sizeof(ubxCfgValSet_t)); // tx_buffer->payload.cfg_valset.version = 0; @@ -615,7 +617,8 @@ static void ubloxSendPollMessage(uint8_t msg_id) ubloxSendMessage(&msg, false); } -static void ubloxSendNAV5Message(uint8_t model) { +static void ubloxSendNAV5Message(uint8_t model) +{ DEBUG_SET(DEBUG_GPS_CONNECTION, 0, model); ubxMessage_t tx_buffer; if (gpsData.ubloxM9orAbove) { @@ -875,21 +878,21 @@ static void ubloxSetSbas(void) uint64_t mask = SBAS_SEARCH_ALL; switch (gpsConfig()->sbasMode) { - case SBAS_EGNOS: - mask = SBAS_SEARCH_PRN(123) | SBAS_SEARCH_PRN(126) | SBAS_SEARCH_PRN(136); - break; - case SBAS_WAAS: - mask = SBAS_SEARCH_PRN(131) | SBAS_SEARCH_PRN(133) | SBAS_SEARCH_PRN(135) | SBAS_SEARCH_PRN(138); - break; - case SBAS_MSAS: - mask = SBAS_SEARCH_PRN(129) | SBAS_SEARCH_PRN(137); - break; - case SBAS_GAGAN: - mask = SBAS_SEARCH_PRN(127) | SBAS_SEARCH_PRN(128) | SBAS_SEARCH_PRN(132); - break; - case SBAS_AUTO: - default: - break; + case SBAS_EGNOS: + mask = SBAS_SEARCH_PRN(123) | SBAS_SEARCH_PRN(126) | SBAS_SEARCH_PRN(136); + break; + case SBAS_WAAS: + mask = SBAS_SEARCH_PRN(131) | SBAS_SEARCH_PRN(133) | SBAS_SEARCH_PRN(135) | SBAS_SEARCH_PRN(138); + break; + case SBAS_MSAS: + mask = SBAS_SEARCH_PRN(129) | SBAS_SEARCH_PRN(137); + break; + case SBAS_GAGAN: + mask = SBAS_SEARCH_PRN(127) | SBAS_SEARCH_PRN(128) | SBAS_SEARCH_PRN(132); + break; + case SBAS_AUTO: + default: + break; } payload[0] = (uint8_t)(mask >> (8 * 0)); @@ -920,24 +923,24 @@ static void ubloxSetSbas(void) tx_buffer.payload.cfg_sbas.maxSBAS = 3; tx_buffer.payload.cfg_sbas.scanmode2 = 0; switch (gpsConfig()->sbasMode) { - case SBAS_AUTO: - tx_buffer.payload.cfg_sbas.scanmode1 = 0; - break; - case SBAS_EGNOS: - tx_buffer.payload.cfg_sbas.scanmode1 = 0x00010048; //PRN123, PRN126, PRN136 - break; - case SBAS_WAAS: - tx_buffer.payload.cfg_sbas.scanmode1 = 0x0004A800; //PRN131, PRN133, PRN135, PRN138 - break; - case SBAS_MSAS: - tx_buffer.payload.cfg_sbas.scanmode1 = 0x00020200; //PRN129, PRN137 - break; - case SBAS_GAGAN: - tx_buffer.payload.cfg_sbas.scanmode1 = 0x00001180; //PRN127, PRN128, PRN132 - break; - default: - tx_buffer.payload.cfg_sbas.scanmode1 = 0; - break; + case SBAS_AUTO: + tx_buffer.payload.cfg_sbas.scanmode1 = 0; + break; + case SBAS_EGNOS: + tx_buffer.payload.cfg_sbas.scanmode1 = 0x00010048; //PRN123, PRN126, PRN136 + break; + case SBAS_WAAS: + tx_buffer.payload.cfg_sbas.scanmode1 = 0x0004A800; //PRN131, PRN133, PRN135, PRN138 + break; + case SBAS_MSAS: + tx_buffer.payload.cfg_sbas.scanmode1 = 0x00020200; //PRN129, PRN137 + break; + case SBAS_GAGAN: + tx_buffer.payload.cfg_sbas.scanmode1 = 0x00001180; //PRN127, PRN128, PRN132 + break; + default: + tx_buffer.payload.cfg_sbas.scanmode1 = 0; + break; } ubloxSendConfigMessage(&tx_buffer, MSG_CFG_SBAS, sizeof(ubxCfgSbas_t), false); } @@ -980,51 +983,51 @@ static void gpsConfigureNmea(void) switch (gpsData.state) { - case GPS_STATE_DETECT_BAUD: - // no attempt to read the baud rate of the GPS module, or change it - gpsSetState(GPS_STATE_CHANGE_BAUD); - break; + case GPS_STATE_DETECT_BAUD: + // no attempt to read the baud rate of the GPS module, or change it + gpsSetState(GPS_STATE_CHANGE_BAUD); + break; - case GPS_STATE_CHANGE_BAUD: + case GPS_STATE_CHANGE_BAUD: #if !defined(GPS_NMEA_TX_ONLY) - if (gpsData.state_position < 1) { - // set the FC's baud rate to the user's configured baud rate - serialSetBaudRate(gpsPort, baudRates[gpsInitData[gpsData.userBaudRateIndex].baudrateIndex]); - gpsData.state_position++; - } else if (gpsData.state_position < 2) { - // send NMEA custom commands to select which messages being sent, data rate etc - // use PUBX, MTK, SiRF or GTK format commands, depending on module type - static int commandOffset = 0; - const char *commands = gpsConfig()->nmeaCustomCommands; - const char *cmd = commands + commandOffset; - // skip leading whitespaces and get first command length - int commandLen; - while (*cmd && (commandLen = strcspn(cmd, " \0")) == 0) { - cmd++; // skip separators - } - if (*cmd) { - // Send the current command to the GPS - serialWriteBuf(gpsPort, (uint8_t *)cmd, commandLen); - serialWriteBuf(gpsPort, (uint8_t *)"\r\n", 2); - // Move to the next command - cmd += commandLen; - } - // skip trailing whitespaces - while (*cmd && strcspn(cmd, " \0") == 0) cmd++; - if (*cmd) { - // more commands to send - commandOffset = cmd - commands; - } else { - gpsData.state_position++; - commandOffset = 0; - } - gpsData.state_position++; - gpsSetState(GPS_STATE_RECEIVING_DATA); + if (gpsData.state_position < 1) { + // set the FC's baud rate to the user's configured baud rate + serialSetBaudRate(gpsPort, baudRates[gpsInitData[gpsData.userBaudRateIndex].baudrateIndex]); + gpsData.state_position++; + } else if (gpsData.state_position < 2) { + // send NMEA custom commands to select which messages being sent, data rate etc + // use PUBX, MTK, SiRF or GTK format commands, depending on module type + static int commandOffset = 0; + const char *commands = gpsConfig()->nmeaCustomCommands; + const char *cmd = commands + commandOffset; + // skip leading whitespaces and get first command length + int commandLen; + while (*cmd && (commandLen = strcspn(cmd, " \0")) == 0) { + cmd++; // skip separators } -#else // !GPS_NMEA_TX_ONLY + if (*cmd) { + // Send the current command to the GPS + serialWriteBuf(gpsPort, (uint8_t *)cmd, commandLen); + serialWriteBuf(gpsPort, (uint8_t *)"\r\n", 2); + // Move to the next command + cmd += commandLen; + } + // skip trailing whitespaces + while (*cmd && strcspn(cmd, " \0") == 0) cmd++; + if (*cmd) { + // more commands to send + commandOffset = cmd - commands; + } else { + gpsData.state_position++; + commandOffset = 0; + } + gpsData.state_position++; gpsSetState(GPS_STATE_RECEIVING_DATA); + } +#else // !GPS_NMEA_TX_ONLY + gpsSetState(GPS_STATE_RECEIVING_DATA); #endif // !GPS_NMEA_TX_ONLY - break; + break; } } #endif // USE_GPS_NMEA @@ -1040,136 +1043,136 @@ static void gpsConfigureUblox(void) } switch (gpsData.state) { - case GPS_STATE_DETECT_BAUD: + case GPS_STATE_DETECT_BAUD: - DEBUG_SET(DEBUG_GPS_CONNECTION, 3, baudRates[gpsInitData[gpsData.tempBaudRateIndex].baudrateIndex] / 100); + DEBUG_SET(DEBUG_GPS_CONNECTION, 3, baudRates[gpsInitData[gpsData.tempBaudRateIndex].baudrateIndex] / 100); - // check to see if there has been a response to the version command - // initially the FC will be at the user-configured baud rate. - if (gpsData.platformVersion > UBX_VERSION_UNDEF) { - // set the GPS module's serial port to the user's intended baud rate - serialPrint(gpsPort, gpsInitData[gpsData.userBaudRateIndex].ubx); - // use this baud rate for re-connections - gpsData.tempBaudRateIndex = gpsData.userBaudRateIndex; - // we're done here, let's move the the next state - gpsSetState(GPS_STATE_CHANGE_BAUD); + // check to see if there has been a response to the version command + // initially the FC will be at the user-configured baud rate. + if (gpsData.platformVersion > UBX_VERSION_UNDEF) { + // set the GPS module's serial port to the user's intended baud rate + serialPrint(gpsPort, gpsInitData[gpsData.userBaudRateIndex].ubx); + // use this baud rate for re-connections + gpsData.tempBaudRateIndex = gpsData.userBaudRateIndex; + // we're done here, let's move the the next state + gpsSetState(GPS_STATE_CHANGE_BAUD); + return; + } + + // Send MON-VER messages at GPS_CONFIG_BAUD_CHANGE_INTERVAL for GPS_BAUDRATE_TEST_COUNT times + static bool messageSent = false; + static uint8_t messageCounter = 0; + DEBUG_SET(DEBUG_GPS_CONNECTION, 2, initBaudRateCycleCount * 100 + messageCounter); + + if (messageCounter < GPS_BAUDRATE_TEST_COUNT) { + if (!messageSent) { + gpsData.platformVersion = UBX_VERSION_UNDEF; + ubloxSendClassMessage(CLASS_MON, MSG_MON_VER, 0); + gpsData.ackState = UBLOX_ACK_IDLE; // ignore ACK for this message + messageSent = true; + } + if (cmp32(gpsData.now, gpsData.state_ts) > GPS_CONFIG_BAUD_CHANGE_INTERVAL) { + gpsData.state_ts = gpsData.now; + messageSent = false; + messageCounter++; + } + return; + } + messageCounter = 0; + gpsData.state_ts = gpsData.now; + + // failed to connect at that rate after five attempts + // try other GPS baudrates, starting at 9600 and moving up + if (gpsData.tempBaudRateIndex == 0) { + gpsData.tempBaudRateIndex = ARRAYLEN(gpsInitData) - 1; // slowest baud rate (9600) + } else { + gpsData.tempBaudRateIndex--; + } + // set the FC baud rate to the new temp baud rate + serialSetBaudRate(gpsPort, baudRates[gpsInitData[gpsData.tempBaudRateIndex].baudrateIndex]); + initBaudRateCycleCount++; + + break; + + case GPS_STATE_CHANGE_BAUD: + // give time for the GPS module's serial port to settle + // very important for M8 to give the module a lot of time before sending commands + // M10 only need about 200ms but M8 and below sometimes need as long as 1000ms + if (cmp32(gpsData.now, gpsData.state_ts) < (3 * GPS_CONFIG_BAUD_CHANGE_INTERVAL)) { + return; + } + // set the FC's serial port to the configured rate + serialSetBaudRate(gpsPort, baudRates[gpsInitData[gpsData.userBaudRateIndex].baudrateIndex]); + DEBUG_SET(DEBUG_GPS_CONNECTION, 3, baudRates[gpsInitData[gpsData.userBaudRateIndex].baudrateIndex] / 100); + // then start sending configuration settings + gpsSetState(GPS_STATE_CONFIGURE); + break; + + case GPS_STATE_CONFIGURE: + // Either use specific config file for GPS or let dynamically upload config + if (gpsConfig()->autoConfig == GPS_AUTOCONFIG_OFF) { + gpsSetState(GPS_STATE_RECEIVING_DATA); + break; + } + + // Add delay to stabilize the connection + if (cmp32(gpsData.now, gpsData.state_ts) < 1000) { + return; + } + + if (gpsData.ackState == UBLOX_ACK_IDLE) { + + // short delay before between commands, including the first command + static uint32_t last_state_position_time = 0; + if (last_state_position_time == 0) { + last_state_position_time = gpsData.now; + } + if (cmp32(gpsData.now, last_state_position_time) < GPS_CONFIG_CHANGE_INTERVAL) { return; } + last_state_position_time = gpsData.now; - // Send MON-VER messages at GPS_CONFIG_BAUD_CHANGE_INTERVAL for GPS_BAUDRATE_TEST_COUNT times - static bool messageSent = false; - static uint8_t messageCounter = 0; - DEBUG_SET(DEBUG_GPS_CONNECTION, 2, initBaudRateCycleCount * 100 + messageCounter); - - if (messageCounter < GPS_BAUDRATE_TEST_COUNT) { - if (!messageSent) { - gpsData.platformVersion = UBX_VERSION_UNDEF; + switch (gpsData.state_position) { + // if a UBX command is sent, ack is supposed to give position++ once the reply happens + case UBLOX_DETECT_UNIT: // 400 in debug + if (gpsData.platformVersion == UBX_VERSION_UNDEF) { ubloxSendClassMessage(CLASS_MON, MSG_MON_VER, 0); - gpsData.ackState = UBLOX_ACK_IDLE; // ignore ACK for this message - messageSent = true; + } else { + gpsData.state_position++; } - if (cmp32(gpsData.now, gpsData.state_ts) > GPS_CONFIG_BAUD_CHANGE_INTERVAL) { - gpsData.state_ts = gpsData.now; - messageSent = false; - messageCounter++; - } - return; - } - messageCounter = 0; - gpsData.state_ts = gpsData.now; - - // failed to connect at that rate after five attempts - // try other GPS baudrates, starting at 9600 and moving up - if (gpsData.tempBaudRateIndex == 0) { - gpsData.tempBaudRateIndex = ARRAYLEN(gpsInitData) - 1; // slowest baud rate (9600) - } else { - gpsData.tempBaudRateIndex--; - } - // set the FC baud rate to the new temp baud rate - serialSetBaudRate(gpsPort, baudRates[gpsInitData[gpsData.tempBaudRateIndex].baudrateIndex]); - initBaudRateCycleCount++; - - break; - - case GPS_STATE_CHANGE_BAUD: - // give time for the GPS module's serial port to settle - // very important for M8 to give the module a lot of time before sending commands - // M10 only need about 200ms but M8 and below sometimes need as long as 1000ms - if (cmp32(gpsData.now, gpsData.state_ts) < (3 * GPS_CONFIG_BAUD_CHANGE_INTERVAL)) { - return; - } - // set the FC's serial port to the configured rate - serialSetBaudRate(gpsPort, baudRates[gpsInitData[gpsData.userBaudRateIndex].baudrateIndex]); - DEBUG_SET(DEBUG_GPS_CONNECTION, 3, baudRates[gpsInitData[gpsData.userBaudRateIndex].baudrateIndex] / 100); - // then start sending configuration settings - gpsSetState(GPS_STATE_CONFIGURE); - break; - - case GPS_STATE_CONFIGURE: - // Either use specific config file for GPS or let dynamically upload config - if (gpsConfig()->autoConfig == GPS_AUTOCONFIG_OFF) { - gpsSetState(GPS_STATE_RECEIVING_DATA); break; - } - - // Add delay to stabilize the connection - if (cmp32(gpsData.now, gpsData.state_ts) < 1000) { - return; - } - - if (gpsData.ackState == UBLOX_ACK_IDLE) { - - // short delay before between commands, including the first command - static uint32_t last_state_position_time = 0; - if (last_state_position_time == 0) { - last_state_position_time = gpsData.now; + case UBLOX_SLOW_NAV_RATE: // 401 in debug + ubloxSetNavRate(1, 1, 1); // throttle nav data rate to one per second, until configured + break; + case UBLOX_MSG_DISABLE_NMEA: + if (gpsData.ubloxM9orAbove) { + ubloxDisableNMEAValSet(); + gpsData.state_position = UBLOX_MSG_RMC; // skip UBX NMEA entries - goes to RMC plus one, or ACQUIRE_MODEL + } else { + gpsData.state_position++; } - if (cmp32(gpsData.now, last_state_position_time) < GPS_CONFIG_CHANGE_INTERVAL) { - return; - } - last_state_position_time = gpsData.now; - - switch (gpsData.state_position) { - // if a UBX command is sent, ack is supposed to give position++ once the reply happens - case UBLOX_DETECT_UNIT: // 400 in debug - if (gpsData.platformVersion == UBX_VERSION_UNDEF) { - ubloxSendClassMessage(CLASS_MON, MSG_MON_VER, 0); - } else { - gpsData.state_position++; - } - break; - case UBLOX_SLOW_NAV_RATE: // 401 in debug - ubloxSetNavRate(1, 1, 1); // throttle nav data rate to one per second, until configured - break; - case UBLOX_MSG_DISABLE_NMEA: - if (gpsData.ubloxM9orAbove) { - ubloxDisableNMEAValSet(); - gpsData.state_position = UBLOX_MSG_RMC; // skip UBX NMEA entries - goes to RMC plus one, or ACQUIRE_MODEL - } else { - gpsData.state_position++; - } - break; - case UBLOX_MSG_VGS: //Disable NMEA Messages - ubloxSetMessageRate(CLASS_NMEA_STD, MSG_NMEA_VTG, 0); // VGS: Course over ground and Ground speed - break; - case UBLOX_MSG_GSV: - ubloxSetMessageRate(CLASS_NMEA_STD, MSG_NMEA_GSV, 0); // GSV: GNSS Satellites in View - break; - case UBLOX_MSG_GLL: - ubloxSetMessageRate(CLASS_NMEA_STD, MSG_NMEA_GLL, 0); // GLL: Latitude and longitude, with time of position fix and status - break; - case UBLOX_MSG_GGA: - ubloxSetMessageRate(CLASS_NMEA_STD, MSG_NMEA_GGA, 0); // GGA: Global positioning system fix data - break; - case UBLOX_MSG_GSA: - ubloxSetMessageRate(CLASS_NMEA_STD, MSG_NMEA_GSA, 0); // GSA: GNSS DOP and Active Satellites - break; - case UBLOX_MSG_RMC: - ubloxSetMessageRate(CLASS_NMEA_STD, MSG_NMEA_RMC, 0); // RMC: Recommended Minimum data - break; - case UBLOX_ACQUIRE_MODEL: - ubloxSendNAV5Message(gpsConfig()->gps_ublox_acquire_model); - break; + break; + case UBLOX_MSG_VGS: //Disable NMEA Messages + ubloxSetMessageRate(CLASS_NMEA_STD, MSG_NMEA_VTG, 0); // VGS: Course over ground and Ground speed + break; + case UBLOX_MSG_GSV: + ubloxSetMessageRate(CLASS_NMEA_STD, MSG_NMEA_GSV, 0); // GSV: GNSS Satellites in View + break; + case UBLOX_MSG_GLL: + ubloxSetMessageRate(CLASS_NMEA_STD, MSG_NMEA_GLL, 0); // GLL: Latitude and longitude, with time of position fix and status + break; + case UBLOX_MSG_GGA: + ubloxSetMessageRate(CLASS_NMEA_STD, MSG_NMEA_GGA, 0); // GGA: Global positioning system fix data + break; + case UBLOX_MSG_GSA: + ubloxSetMessageRate(CLASS_NMEA_STD, MSG_NMEA_GSA, 0); // GSA: GNSS DOP and Active Satellites + break; + case UBLOX_MSG_RMC: + ubloxSetMessageRate(CLASS_NMEA_STD, MSG_NMEA_RMC, 0); // RMC: Recommended Minimum data + break; + case UBLOX_ACQUIRE_MODEL: + ubloxSendNAV5Message(gpsConfig()->gps_ublox_acquire_model); + break; // *** temporarily disabled // case UBLOX_CFG_ANA: // i f (gpsData.ubloxM7orAbove) { // NavX5 support existed in M5 - in theory we could remove that check @@ -1178,126 +1181,126 @@ static void gpsConfigureUblox(void) // gpsData.state_position++; // } // break; - case UBLOX_SET_SBAS: - ubloxSetSbas(); - break; - case UBLOX_SET_PMS: - if (gpsData.ubloxM8orAbove) { - ubloxSendPowerMode(); - } else { - gpsData.state_position++; - } - break; - case UBLOX_MSG_NAV_PVT: //Enable NAV-PVT Messages - if (gpsData.ubloxM9orAbove) { - ubloxSetMessageRateValSet(CFG_MSGOUT_UBX_NAV_PVT_UART1, 1); - } else if (gpsData.ubloxM7orAbove) { - ubloxSetMessageRate(CLASS_NAV, MSG_NAV_PVT, 1); - } else { - gpsData.state_position++; - } - break; - // if NAV-PVT is enabled, we don't need the older nav messages - case UBLOX_MSG_SOL: - if (gpsData.ubloxM9orAbove) { - // SOL is deprecated above M8 - gpsData.state_position++; - } else if (gpsData.ubloxM7orAbove) { - // use NAV-PVT, so don't use NAV-SOL - ubloxSetMessageRate(CLASS_NAV, MSG_NAV_SOL, 0); - } else { - // Only use NAV-SOL below M7 - ubloxSetMessageRate(CLASS_NAV, MSG_NAV_SOL, 1); - } - break; - case UBLOX_MSG_POSLLH: - if (gpsData.ubloxM7orAbove) { - ubloxSetMessageRate(CLASS_NAV, MSG_NAV_POSLLH, 0); - } else { - ubloxSetMessageRate(CLASS_NAV, MSG_NAV_POSLLH, 1); - } - break; - case UBLOX_MSG_STATUS: - if (gpsData.ubloxM7orAbove) { - ubloxSetMessageRate(CLASS_NAV, MSG_NAV_STATUS, 0); - } else { - ubloxSetMessageRate(CLASS_NAV, MSG_NAV_STATUS, 1); - } - break; - case UBLOX_MSG_VELNED: - if (gpsData.ubloxM7orAbove) { - ubloxSetMessageRate(CLASS_NAV, MSG_NAV_VELNED, 0); - } else { - ubloxSetMessageRate(CLASS_NAV, MSG_NAV_VELNED, 1); - } - break; - case UBLOX_MSG_DOP: - // nav-pvt has what we need and is available M7 and above - if (gpsData.ubloxM9orAbove) { - ubloxSetMessageRateValSet(CFG_MSGOUT_UBX_NAV_DOP_UART1, 0); - } else if (gpsData.ubloxM7orAbove) { - ubloxSetMessageRate(CLASS_NAV, MSG_NAV_DOP, 0); - } else { - ubloxSetMessageRate(CLASS_NAV, MSG_NAV_DOP, 1); - } - break; - case UBLOX_SAT_INFO: - // enable by default, turned off when armed and receiving data to reduce in-flight traffic - setSatInfoMessageRate(5); - break; - case UBLOX_SET_NAV_RATE: - // set the nav solution rate to the user's configured update rate - gpsData.updateRateHz = gpsConfig()->gps_update_rate_hz; - ubloxSetNavRate(gpsData.updateRateHz, 1, 1); - break; - case UBLOX_MSG_CFG_GNSS: - if ((gpsConfig()->sbasMode == SBAS_NONE) || (gpsConfig()->gps_ublox_use_galileo)) { - ubloxSendPollMessage(MSG_CFG_GNSS); // poll messages wait for ACK - } else { - gpsData.state_position++; - } - break; - case UBLOX_CONFIG_COMPLETE: - gpsSetState(GPS_STATE_RECEIVING_DATA); - break; - // TO DO: (separate PR) add steps that remove I2C or SPI data on ValSet aware units, eg - // ubloxSetMessageRateValSet(CFG_MSGOUT_UBX_NAV_SAT_I2C, 0); - // ubloxSetMessageRateValSet(CFG_MSGOUT_UBX_NAV_SAT_SPI, 0); - default: - break; - } - } - - // check the ackState after changing CONFIG state, or every iteration while not UBLOX_ACK_IDLE - switch (gpsData.ackState) { - case UBLOX_ACK_IDLE: - break; - case UBLOX_ACK_WAITING: - if (cmp32(gpsData.now, gpsData.lastMessageSent) > UBLOX_ACK_TIMEOUT_MS){ - // give up, treat it like receiving ack - gpsData.ackState = UBLOX_ACK_GOT_ACK; - } - break; - case UBLOX_ACK_GOT_ACK: - // move forward one position, and clear the ack state + case UBLOX_SET_SBAS: + ubloxSetSbas(); + break; + case UBLOX_SET_PMS: + if (gpsData.ubloxM8orAbove) { + ubloxSendPowerMode(); + } else { gpsData.state_position++; - gpsData.ackState = UBLOX_ACK_IDLE; - break; - case UBLOX_ACK_GOT_NACK: - // this is the tricky bit - // and we absolutely must get the unit type right - if (gpsData.state_position == UBLOX_DETECT_UNIT) { - gpsSetState(GPS_STATE_CONFIGURE); - gpsData.ackState = UBLOX_ACK_IDLE; - } else { - // otherwise, for testing: just ignore nacks - gpsData.state_position++; - gpsData.ackState = UBLOX_ACK_IDLE; - } - break; - default: - break; + } + break; + case UBLOX_MSG_NAV_PVT: //Enable NAV-PVT Messages + if (gpsData.ubloxM9orAbove) { + ubloxSetMessageRateValSet(CFG_MSGOUT_UBX_NAV_PVT_UART1, 1); + } else if (gpsData.ubloxM7orAbove) { + ubloxSetMessageRate(CLASS_NAV, MSG_NAV_PVT, 1); + } else { + gpsData.state_position++; + } + break; + // if NAV-PVT is enabled, we don't need the older nav messages + case UBLOX_MSG_SOL: + if (gpsData.ubloxM9orAbove) { + // SOL is deprecated above M8 + gpsData.state_position++; + } else if (gpsData.ubloxM7orAbove) { + // use NAV-PVT, so don't use NAV-SOL + ubloxSetMessageRate(CLASS_NAV, MSG_NAV_SOL, 0); + } else { + // Only use NAV-SOL below M7 + ubloxSetMessageRate(CLASS_NAV, MSG_NAV_SOL, 1); + } + break; + case UBLOX_MSG_POSLLH: + if (gpsData.ubloxM7orAbove) { + ubloxSetMessageRate(CLASS_NAV, MSG_NAV_POSLLH, 0); + } else { + ubloxSetMessageRate(CLASS_NAV, MSG_NAV_POSLLH, 1); + } + break; + case UBLOX_MSG_STATUS: + if (gpsData.ubloxM7orAbove) { + ubloxSetMessageRate(CLASS_NAV, MSG_NAV_STATUS, 0); + } else { + ubloxSetMessageRate(CLASS_NAV, MSG_NAV_STATUS, 1); + } + break; + case UBLOX_MSG_VELNED: + if (gpsData.ubloxM7orAbove) { + ubloxSetMessageRate(CLASS_NAV, MSG_NAV_VELNED, 0); + } else { + ubloxSetMessageRate(CLASS_NAV, MSG_NAV_VELNED, 1); + } + break; + case UBLOX_MSG_DOP: + // nav-pvt has what we need and is available M7 and above + if (gpsData.ubloxM9orAbove) { + ubloxSetMessageRateValSet(CFG_MSGOUT_UBX_NAV_DOP_UART1, 0); + } else if (gpsData.ubloxM7orAbove) { + ubloxSetMessageRate(CLASS_NAV, MSG_NAV_DOP, 0); + } else { + ubloxSetMessageRate(CLASS_NAV, MSG_NAV_DOP, 1); + } + break; + case UBLOX_SAT_INFO: + // enable by default, turned off when armed and receiving data to reduce in-flight traffic + setSatInfoMessageRate(5); + break; + case UBLOX_SET_NAV_RATE: + // set the nav solution rate to the user's configured update rate + gpsData.updateRateHz = gpsConfig()->gps_update_rate_hz; + ubloxSetNavRate(gpsData.updateRateHz, 1, 1); + break; + case UBLOX_MSG_CFG_GNSS: + if ((gpsConfig()->sbasMode == SBAS_NONE) || (gpsConfig()->gps_ublox_use_galileo)) { + ubloxSendPollMessage(MSG_CFG_GNSS); // poll messages wait for ACK + } else { + gpsData.state_position++; + } + break; + case UBLOX_CONFIG_COMPLETE: + gpsSetState(GPS_STATE_RECEIVING_DATA); + break; + // TO DO: (separate PR) add steps that remove I2C or SPI data on ValSet aware units, eg + // ubloxSetMessageRateValSet(CFG_MSGOUT_UBX_NAV_SAT_I2C, 0); + // ubloxSetMessageRateValSet(CFG_MSGOUT_UBX_NAV_SAT_SPI, 0); + default: + break; } + } + + // check the ackState after changing CONFIG state, or every iteration while not UBLOX_ACK_IDLE + switch (gpsData.ackState) { + case UBLOX_ACK_IDLE: + break; + case UBLOX_ACK_WAITING: + if (cmp32(gpsData.now, gpsData.lastMessageSent) > UBLOX_ACK_TIMEOUT_MS){ + // give up, treat it like receiving ack + gpsData.ackState = UBLOX_ACK_GOT_ACK; + } + break; + case UBLOX_ACK_GOT_ACK: + // move forward one position, and clear the ack state + gpsData.state_position++; + gpsData.ackState = UBLOX_ACK_IDLE; + break; + case UBLOX_ACK_GOT_NACK: + // this is the tricky bit + // and we absolutely must get the unit type right + if (gpsData.state_position == UBLOX_DETECT_UNIT) { + gpsSetState(GPS_STATE_CONFIGURE); + gpsData.ackState = UBLOX_ACK_IDLE; + } else { + // otherwise, for testing: just ignore nacks + gpsData.state_position++; + gpsData.ackState = UBLOX_ACK_IDLE; + } + break; + default: + break; + } } } #endif // USE_GPS_UBLOX @@ -1538,7 +1541,8 @@ static void gpsNewData(uint16_t c) } #ifdef USE_GPS_UBLOX -static ubloxVersion_e ubloxParseVersion(const uint32_t version) { +static ubloxVersion_e ubloxParseVersion(const uint32_t version) +{ for (size_t i = 0; i < ARRAYLEN(ubloxVersionMap); ++i) { if (version == ubloxVersionMap[i].hw) { return (ubloxVersion_e) i; @@ -1687,113 +1691,113 @@ static void parseFieldNmea(gpsDataNmea_t *data, char *str, uint8_t gpsFrame, uin switch (gpsFrame) { - case FRAME_GGA: //************* GPGGA FRAME parsing - switch (idx) { - case 1: - data->time = ((uint8_t)(str[5] - '0') * 10 + (uint8_t)(str[7] - '0')) * 100; - break; - case 2: - data->latitude = GPS_coord_to_degrees(str); - break; - case 3: - if (str[0] == 'S') data->latitude *= -1; - break; - case 4: - data->longitude = GPS_coord_to_degrees(str); - break; - case 5: - if (str[0] == 'W') data->longitude *= -1; - break; - case 6: - gpsSetFixState(str[0] > '0'); - break; - case 7: - data->numSat = grab_fields(str, 0); - break; - case 9: - data->altitudeCm = grab_fields(str, 1) * 10; // altitude in centimeters. Note: NMEA delivers altitude with 1 or 3 decimals. It's safer to cut at 0.1m and multiply by 10 - break; - } + case FRAME_GGA: //************* GPGGA FRAME parsing + switch (idx) { + case 1: + data->time = ((uint8_t)(str[5] - '0') * 10 + (uint8_t)(str[7] - '0')) * 100; + break; + case 2: + data->latitude = GPS_coord_to_degrees(str); + break; + case 3: + if (str[0] == 'S') data->latitude *= -1; + break; + case 4: + data->longitude = GPS_coord_to_degrees(str); + break; + case 5: + if (str[0] == 'W') data->longitude *= -1; + break; + case 6: + gpsSetFixState(str[0] > '0'); + break; + case 7: + data->numSat = grab_fields(str, 0); + break; + case 9: + data->altitudeCm = grab_fields(str, 1) * 10; // altitude in centimeters. Note: NMEA delivers altitude with 1 or 3 decimals. It's safer to cut at 0.1m and multiply by 10 + break; + } + break; + + case FRAME_RMC: //************* GPRMC FRAME parsing + switch (idx) { + case 1: + data->time = grab_fields(str, 2); // UTC time hhmmss.ss + break; + case 7: + data->speed = ((grab_fields(str, 1) * 5144L) / 1000L); // speed in cm/s added by Mis + break; + case 8: + data->ground_course = (grab_fields(str, 1)); // ground course deg * 10 + break; + case 9: + data->date = grab_fields(str, 0); // date dd/mm/yy + break; + } + break; + + case FRAME_GSV: + switch (idx) { + /*case 1: + // Total number of messages of this type in this cycle + break; */ + case 2: + // Message number + svMessageNum = grab_fields(str, 0); + break; + case 3: + // Total number of SVs visible + GPS_numCh = MIN(grab_fields(str, 0), GPS_SV_MAXSATS_LEGACY); + break; + } + if (idx < 4) break; - case FRAME_RMC: //************* GPRMC FRAME parsing - switch (idx) { - case 1: - data->time = grab_fields(str, 2); // UTC time hhmmss.ss - break; - case 7: - data->speed = ((grab_fields(str, 1) * 5144L) / 1000L); // speed in cm/s added by Mis - break; - case 8: - data->ground_course = (grab_fields(str, 1)); // ground course deg * 10 - break; - case 9: - data->date = grab_fields(str, 0); // date dd/mm/yy - break; - } + svPacketIdx = (idx - 4) / 4 + 1; // satellite number in packet, 1-4 + svSatNum = svPacketIdx + (4 * (svMessageNum - 1)); // global satellite number + svSatParam = idx - 3 - (4 * (svPacketIdx - 1)); // parameter number for satellite + + if (svSatNum > GPS_SV_MAXSATS_LEGACY) break; - case FRAME_GSV: - switch (idx) { - /*case 1: - // Total number of messages of this type in this cycle - break; */ - case 2: - // Message number - svMessageNum = grab_fields(str, 0); - break; - case 3: - // Total number of SVs visible - GPS_numCh = MIN(grab_fields(str, 0), GPS_SV_MAXSATS_LEGACY); - break; - } - if (idx < 4) - break; - - svPacketIdx = (idx - 4) / 4 + 1; // satellite number in packet, 1-4 - svSatNum = svPacketIdx + (4 * (svMessageNum - 1)); // global satellite number - svSatParam = idx - 3 - (4 * (svPacketIdx - 1)); // parameter number for satellite - - if (svSatNum > GPS_SV_MAXSATS_LEGACY) - break; - - switch (svSatParam) { - case 1: - // SV PRN number - GPS_svinfo[svSatNum - 1].chn = svSatNum; - GPS_svinfo[svSatNum - 1].svid = grab_fields(str, 0); - break; - /*case 2: - // Elevation, in degrees, 90 maximum - break; - case 3: - // Azimuth, degrees from True North, 000 through 359 - break; */ - case 4: - // SNR, 00 through 99 dB (null when not tracking) - GPS_svinfo[svSatNum - 1].cno = grab_fields(str, 0); - GPS_svinfo[svSatNum - 1].quality = 0; // only used by ublox - break; - } + switch (svSatParam) { + case 1: + // SV PRN number + GPS_svinfo[svSatNum - 1].chn = svSatNum; + GPS_svinfo[svSatNum - 1].svid = grab_fields(str, 0); + break; + /*case 2: + // Elevation, in degrees, 90 maximum + break; + case 3: + // Azimuth, degrees from True North, 000 through 359 + break; */ + case 4: + // SNR, 00 through 99 dB (null when not tracking) + GPS_svinfo[svSatNum - 1].cno = grab_fields(str, 0); + GPS_svinfo[svSatNum - 1].quality = 0; // only used by ublox + break; + } #ifdef USE_DASHBOARD - dashboardGpsNavSvInfoRcvCount++; + dashboardGpsNavSvInfoRcvCount++; #endif - break; + break; - case FRAME_GSA: - switch (idx) { - case 15: - data->pdop = grab_fields(str, 2); // pDOP * 100 - break; - case 16: - data->hdop = grab_fields(str, 2); // hDOP * 100 - break; - case 17: - data->vdop = grab_fields(str, 2); // vDOP * 100 - break; - } + case FRAME_GSA: + switch (idx) { + case 15: + data->pdop = grab_fields(str, 2); // pDOP * 100 break; + case 16: + data->hdop = grab_fields(str, 2); // hDOP * 100 + break; + case 17: + data->vdop = grab_fields(str, 2); // vDOP * 100 + break; + } + break; } } @@ -1803,55 +1807,55 @@ static bool writeGpsSolutionNmea(gpsSolutionData_t *sol, const gpsDataNmea_t *da const uint32_t msInTenSeconds = 10000; switch (gpsFrame) { - case FRAME_GGA: + case FRAME_GGA: #ifdef USE_DASHBOARD - *dashboardGpsPacketLogCurrentChar = DASHBOARD_LOG_NMEA_GGA; + *dashboardGpsPacketLogCurrentChar = DASHBOARD_LOG_NMEA_GGA; #endif - if (STATE(GPS_FIX)) { - sol->llh.lat = data->latitude; - sol->llh.lon = data->longitude; - sol->numSat = data->numSat; - sol->llh.altCm = data->altitudeCm; - } - navDeltaTimeMs = (msInTenSeconds + data->time - gpsData.lastNavSolTs) % msInTenSeconds; - gpsData.lastNavSolTs = data->time; - sol->navIntervalMs = constrain(navDeltaTimeMs, 50, 2500); - // return only one true statement to trigger one "newGpsDataReady" flag per GPS loop - return true; + if (STATE(GPS_FIX)) { + sol->llh.lat = data->latitude; + sol->llh.lon = data->longitude; + sol->numSat = data->numSat; + sol->llh.altCm = data->altitudeCm; + } + navDeltaTimeMs = (msInTenSeconds + data->time - gpsData.lastNavSolTs) % msInTenSeconds; + gpsData.lastNavSolTs = data->time; + sol->navIntervalMs = constrain(navDeltaTimeMs, 50, 2500); + // return only one true statement to trigger one "newGpsDataReady" flag per GPS loop + return true; - case FRAME_GSA: + case FRAME_GSA: #ifdef USE_DASHBOARD - *dashboardGpsPacketLogCurrentChar = DASHBOARD_LOG_NMEA_GSA; + *dashboardGpsPacketLogCurrentChar = DASHBOARD_LOG_NMEA_GSA; #endif - sol->dop.pdop = data->pdop; - sol->dop.hdop = data->hdop; - sol->dop.vdop = data->vdop; - return false; + sol->dop.pdop = data->pdop; + sol->dop.hdop = data->hdop; + sol->dop.vdop = data->vdop; + return false; - case FRAME_RMC: + case FRAME_RMC: #ifdef USE_DASHBOARD - *dashboardGpsPacketLogCurrentChar = DASHBOARD_LOG_NMEA_RMC; + *dashboardGpsPacketLogCurrentChar = DASHBOARD_LOG_NMEA_RMC; #endif - sol->groundSpeed = data->speed; - sol->groundCourse = data->ground_course; + sol->groundSpeed = data->speed; + sol->groundCourse = data->ground_course; #ifdef USE_RTC_TIME - // This check will miss 00:00:00.00, but we shouldn't care - next report will be valid - if(!rtcHasTime() && data->date != 0 && data->time != 0) { - dateTime_t temp_time; - temp_time.year = (data->date % 100) + 2000; - temp_time.month = (data->date / 100) % 100; - temp_time.day = (data->date / 10000) % 100; - temp_time.hours = (data->time / 1000000) % 100; - temp_time.minutes = (data->time / 10000) % 100; - temp_time.seconds = (data->time / 100) % 100; - temp_time.millis = (data->time & 100) * 10; - rtcSetDateTime(&temp_time); - } + // This check will miss 00:00:00.00, but we shouldn't care - next report will be valid + if (!rtcHasTime() && data->date != 0 && data->time != 0) { + dateTime_t temp_time; + temp_time.year = (data->date % 100) + 2000; + temp_time.month = (data->date / 100) % 100; + temp_time.day = (data->date / 10000) % 100; + temp_time.hours = (data->time / 1000000) % 100; + temp_time.minutes = (data->time / 10000) % 100; + temp_time.seconds = (data->time / 100) % 100; + temp_time.millis = (data->time & 100) * 10; + rtcSetDateTime(&temp_time); + } #endif - return false; + return false; - default: - return false; + default: + return false; } } @@ -1865,68 +1869,68 @@ static bool gpsNewFrameNMEA(char c) switch (c) { - case '$': - param = 0; - offset = 0; - parity = 0; - break; + case '$': + param = 0; + offset = 0; + parity = 0; + break; - case ',': - case '*': - string[offset] = 0; - if (param == 0) { // frame identification (5 chars, e.g. "GPGGA", "GNGGA", "GLGGA", ...) - gps_frame = NO_FRAME; - if (strcmp(&string[2], "GGA") == 0) { - gps_frame = FRAME_GGA; - } else if (strcmp(&string[2], "RMC") == 0) { - gps_frame = FRAME_RMC; - } else if (strcmp(&string[2], "GSV") == 0) { - gps_frame = FRAME_GSV; - } else if (strcmp(&string[2], "GSA") == 0) { - gps_frame = FRAME_GSA; - } + case ',': + case '*': + string[offset] = 0; + if (param == 0) { // frame identification (5 chars, e.g. "GPGGA", "GNGGA", "GLGGA", ...) + gps_frame = NO_FRAME; + if (strcmp(&string[2], "GGA") == 0) { + gps_frame = FRAME_GGA; + } else if (strcmp(&string[2], "RMC") == 0) { + gps_frame = FRAME_RMC; + } else if (strcmp(&string[2], "GSV") == 0) { + gps_frame = FRAME_GSV; + } else if (strcmp(&string[2], "GSA") == 0) { + gps_frame = FRAME_GSA; } + } - // parse string and write data into gps_msg - parseFieldNmea(&gps_msg, string, gps_frame, param); + // parse string and write data into gps_msg + parseFieldNmea(&gps_msg, string, gps_frame, param); - param++; - offset = 0; - if (c == '*') - checksum_param = 1; - else - parity ^= c; - break; + param++; + offset = 0; + if (c == '*') + checksum_param = 1; + else + parity ^= c; + break; - case '\r': - case '\n': - if (checksum_param) { //parity checksum + case '\r': + case '\n': + if (checksum_param) { //parity checksum #ifdef USE_DASHBOARD - shiftPacketLog(); + shiftPacketLog(); #endif - uint8_t checksum = 16 * ((string[0] >= 'A') ? string[0] - 'A' + 10 : string[0] - '0') + ((string[1] >= 'A') ? string[1] - 'A' + 10 : string[1] - '0'); - if (checksum == parity) { + uint8_t checksum = 16 * ((string[0] >= 'A') ? string[0] - 'A' + 10 : string[0] - '0') + ((string[1] >= 'A') ? string[1] - 'A' + 10 : string[1] - '0'); + if (checksum == parity) { #ifdef USE_DASHBOARD - *dashboardGpsPacketLogCurrentChar = DASHBOARD_LOG_IGNORED; - dashboardGpsPacketCount++; -#endif - receivedNavMessage = writeGpsSolutionNmea(&gpsSol, &gps_msg, gps_frame); // // write gps_msg into gpsSol - } -#ifdef USE_DASHBOARD - else { - *dashboardGpsPacketLogCurrentChar = DASHBOARD_LOG_ERROR; - } + *dashboardGpsPacketLogCurrentChar = DASHBOARD_LOG_IGNORED; + dashboardGpsPacketCount++; #endif + receivedNavMessage = writeGpsSolutionNmea(&gpsSol, &gps_msg, gps_frame); // // write gps_msg into gpsSol } - checksum_param = 0; - break; +#ifdef USE_DASHBOARD + else { + *dashboardGpsPacketLogCurrentChar = DASHBOARD_LOG_ERROR; + } +#endif + } + checksum_param = 0; + break; - default: - if (offset < 15) - string[offset++] = c; - if (!checksum_param) - parity ^= c; - break; + default: + if (offset < 15) + string[offset++] = c; + if (!checksum_param) + parity ^= c; + break; } return receivedNavMessage; @@ -2387,112 +2391,52 @@ static bool gpsNewFrameUBLOX(uint8_t data) bool newPositionDataReceived = false; switch (ubxFrameParseState) { - case UBX_PARSE_PREAMBLE_SYNC_1: - if (PREAMBLE1 == data) { - // Might be a new UBX message, go on to look for next preamble byte. - ubxFrameParseState = UBX_PARSE_PREAMBLE_SYNC_2; - break; - } - // Not a new UBX message, stay in this state for the next incoming byte. + case UBX_PARSE_PREAMBLE_SYNC_1: + if (PREAMBLE1 == data) { + // Might be a new UBX message, go on to look for next preamble byte. + ubxFrameParseState = UBX_PARSE_PREAMBLE_SYNC_2; break; - case UBX_PARSE_PREAMBLE_SYNC_2: - if (PREAMBLE2 == data) { - // Matches the two-byte preamble, seems to be a legit message, go on to process the rest of the message. - ubxFrameParseState = UBX_PARSE_MESSAGE_CLASS; - break; - } - // False start, if this byte is not a preamble 1, restart new message parsing. - // If this byte is a preamble 1, we might have gotten two in a row, so stay here and look for preamble 2 again. - if (PREAMBLE1 != data) { - ubxFrameParseState = UBX_PARSE_PREAMBLE_SYNC_1; - } + } + // Not a new UBX message, stay in this state for the next incoming byte. + break; + case UBX_PARSE_PREAMBLE_SYNC_2: + if (PREAMBLE2 == data) { + // Matches the two-byte preamble, seems to be a legit message, go on to process the rest of the message. + ubxFrameParseState = UBX_PARSE_MESSAGE_CLASS; break; - case UBX_PARSE_MESSAGE_CLASS: - ubxRcvMsgChecksumB = ubxRcvMsgChecksumA = data; // Reset & start the checksum A & B accumulators. - ubxRcvMsgClass = data; - ubxFrameParseState = UBX_PARSE_MESSAGE_ID; + } + // False start, if this byte is not a preamble 1, restart new message parsing. + // If this byte is a preamble 1, we might have gotten two in a row, so stay here and look for preamble 2 again. + if (PREAMBLE1 != data) { + ubxFrameParseState = UBX_PARSE_PREAMBLE_SYNC_1; + } + break; + case UBX_PARSE_MESSAGE_CLASS: + ubxRcvMsgChecksumB = ubxRcvMsgChecksumA = data; // Reset & start the checksum A & B accumulators. + ubxRcvMsgClass = data; + ubxFrameParseState = UBX_PARSE_MESSAGE_ID; + break; + case UBX_PARSE_MESSAGE_ID: + ubxRcvMsgChecksumB += (ubxRcvMsgChecksumA += data); // Accumulate both checksums. + ubxRcvMsgID = data; + ubxFrameParseState = UBX_PARSE_PAYLOAD_LENGTH_LSB; + break; + case UBX_PARSE_PAYLOAD_LENGTH_LSB: + ubxRcvMsgChecksumB += (ubxRcvMsgChecksumA += data); + ubxRcvMsgPayloadLength = data; // Payload length LSB. + ubxFrameParseState = UBX_PARSE_PAYLOAD_LENGTH_MSB; + break; + case UBX_PARSE_PAYLOAD_LENGTH_MSB: + ubxRcvMsgChecksumB += (ubxRcvMsgChecksumA += data); // Accumulate both checksums. + ubxRcvMsgPayloadLength += (uint16_t)(data << 8); //Payload length MSB. + if (ubxRcvMsgPayloadLength == 0) { + // No payload for this message, skip to checksum checking. + ubxFrameParseState = UBX_PARSE_CHECKSUM_A; break; - case UBX_PARSE_MESSAGE_ID: - ubxRcvMsgChecksumB += (ubxRcvMsgChecksumA += data); // Accumulate both checksums. - ubxRcvMsgID = data; - ubxFrameParseState = UBX_PARSE_PAYLOAD_LENGTH_LSB; - break; - case UBX_PARSE_PAYLOAD_LENGTH_LSB: - ubxRcvMsgChecksumB += (ubxRcvMsgChecksumA += data); - ubxRcvMsgPayloadLength = data; // Payload length LSB. - ubxFrameParseState = UBX_PARSE_PAYLOAD_LENGTH_MSB; - break; - case UBX_PARSE_PAYLOAD_LENGTH_MSB: - ubxRcvMsgChecksumB += (ubxRcvMsgChecksumA += data); // Accumulate both checksums. - ubxRcvMsgPayloadLength += (uint16_t)(data << 8); //Payload length MSB. - if (ubxRcvMsgPayloadLength == 0) { - // No payload for this message, skip to checksum checking. - ubxFrameParseState = UBX_PARSE_CHECKSUM_A; - break; - } - if (ubxRcvMsgPayloadLength > UBLOX_MAX_PAYLOAD_SANITY_SIZE) { - // Payload length is not reasonable, treat as a bad packet, restart new message parsing. - // Note that we do not parse the rest of the message, better to leave it and look for a new message. -#ifdef USE_DASHBOARD - logErrorToPacketLog(); -#endif - if (PREAMBLE1 == data) { - // If this byte is a preamble 1 value, it might be a new message, so look for preamble 2 instead of starting over. - ubxFrameParseState = UBX_PARSE_PREAMBLE_SYNC_2; - } else { - ubxFrameParseState = UBX_PARSE_PREAMBLE_SYNC_1; - } - break; - } - // Payload length seems legit, go on to receive the payload content. - ubxFrameParsePayloadCounter = 0; - ubxFrameParseState = UBX_PARSE_PAYLOAD_CONTENT; - break; - case UBX_PARSE_PAYLOAD_CONTENT: - ubxRcvMsgChecksumB += (ubxRcvMsgChecksumA += data); // Accumulate both checksums. - if (ubxFrameParsePayloadCounter < UBLOX_PAYLOAD_SIZE) { - // Only add bytes to the buffer if we haven't reached the max supported payload size. - // Note that we still read & checksum every byte so the checksum calculates correctly. - ubxRcvMsgPayload.rawBytes[ubxFrameParsePayloadCounter] = data; - } - if (++ubxFrameParsePayloadCounter >= ubxRcvMsgPayloadLength) { - // All bytes for payload length processed. - ubxFrameParseState = UBX_PARSE_CHECKSUM_A; - break; - } - // More payload content left, stay in this state. - break; - case UBX_PARSE_CHECKSUM_A: - if (ubxRcvMsgChecksumA == data) { - // Checksum A matches, go on to checksum B. - ubxFrameParseState = UBX_PARSE_CHECKSUM_B; - break; - } - // Bad checksum A, restart new message parsing. - // Note that we do not parse checksum B, new message processing will handle skipping it if needed. -#ifdef USE_DASHBOARD - logErrorToPacketLog(); -#endif - if (PREAMBLE1 == data) { - // If this byte is a preamble 1 value, it might be a new message, so look for preamble 2 instead of starting over. - ubxFrameParseState = UBX_PARSE_PREAMBLE_SYNC_2; - } else { - ubxFrameParseState = UBX_PARSE_PREAMBLE_SYNC_1; - } - break; - case UBX_PARSE_CHECKSUM_B: - if (ubxRcvMsgChecksumB == data) { - // Checksum B also matches, successfully received a new full packet! -#ifdef USE_DASHBOARD - dashboardGpsPacketCount++; // Packet counter used by dashboard device. - shiftPacketLog(); // Make space for message handling to add the message type char to the dashboard device packet log. -#endif - // Handle the parsed message. Note this is a questionable inverted call dependency, but something for a later refactoring. - newPositionDataReceived = UBLOX_parse_gps(); // True only when we have new position data from the parsed message. - ubxFrameParseState = UBX_PARSE_PREAMBLE_SYNC_1; // Restart new message parsing. - break; - } - // Bad checksum B, restart new message parsing. + } + if (ubxRcvMsgPayloadLength > UBLOX_MAX_PAYLOAD_SANITY_SIZE) { + // Payload length is not reasonable, treat as a bad packet, restart new message parsing. + // Note that we do not parse the rest of the message, better to leave it and look for a new message. #ifdef USE_DASHBOARD logErrorToPacketLog(); #endif @@ -2504,6 +2448,66 @@ static bool gpsNewFrameUBLOX(uint8_t data) } break; } + // Payload length seems legit, go on to receive the payload content. + ubxFrameParsePayloadCounter = 0; + ubxFrameParseState = UBX_PARSE_PAYLOAD_CONTENT; + break; + case UBX_PARSE_PAYLOAD_CONTENT: + ubxRcvMsgChecksumB += (ubxRcvMsgChecksumA += data); // Accumulate both checksums. + if (ubxFrameParsePayloadCounter < UBLOX_PAYLOAD_SIZE) { + // Only add bytes to the buffer if we haven't reached the max supported payload size. + // Note that we still read & checksum every byte so the checksum calculates correctly. + ubxRcvMsgPayload.rawBytes[ubxFrameParsePayloadCounter] = data; + } + if (++ubxFrameParsePayloadCounter >= ubxRcvMsgPayloadLength) { + // All bytes for payload length processed. + ubxFrameParseState = UBX_PARSE_CHECKSUM_A; + break; + } + // More payload content left, stay in this state. + break; + case UBX_PARSE_CHECKSUM_A: + if (ubxRcvMsgChecksumA == data) { + // Checksum A matches, go on to checksum B. + ubxFrameParseState = UBX_PARSE_CHECKSUM_B; + break; + } + // Bad checksum A, restart new message parsing. + // Note that we do not parse checksum B, new message processing will handle skipping it if needed. +#ifdef USE_DASHBOARD + logErrorToPacketLog(); +#endif + if (PREAMBLE1 == data) { + // If this byte is a preamble 1 value, it might be a new message, so look for preamble 2 instead of starting over. + ubxFrameParseState = UBX_PARSE_PREAMBLE_SYNC_2; + } else { + ubxFrameParseState = UBX_PARSE_PREAMBLE_SYNC_1; + } + break; + case UBX_PARSE_CHECKSUM_B: + if (ubxRcvMsgChecksumB == data) { + // Checksum B also matches, successfully received a new full packet! +#ifdef USE_DASHBOARD + dashboardGpsPacketCount++; // Packet counter used by dashboard device. + shiftPacketLog(); // Make space for message handling to add the message type char to the dashboard device packet log. +#endif + // Handle the parsed message. Note this is a questionable inverted call dependency, but something for a later refactoring. + newPositionDataReceived = UBLOX_parse_gps(); // True only when we have new position data from the parsed message. + ubxFrameParseState = UBX_PARSE_PREAMBLE_SYNC_1; // Restart new message parsing. + break; + } + // Bad checksum B, restart new message parsing. +#ifdef USE_DASHBOARD + logErrorToPacketLog(); +#endif + if (PREAMBLE1 == data) { + // If this byte is a preamble 1 value, it might be a new message, so look for preamble 2 instead of starting over. + ubxFrameParseState = UBX_PARSE_PREAMBLE_SYNC_2; + } else { + ubxFrameParseState = UBX_PARSE_PREAMBLE_SYNC_1; + } + break; + } // Note this function returns if UBLOX_parse_gps() found new position data, NOT whether this function successfully parsed the frame or not. return newPositionDataReceived; @@ -2567,15 +2571,13 @@ static void GPS_calculateDistanceFlown(bool initialize) if (initialize) { GPS_distanceFlownInCm = 0; - } else { - if (STATE(GPS_FIX_HOME) && ARMING_FLAG(ARMED)) { - uint16_t speed = gpsConfig()->gps_use_3d_speed ? gpsSol.speed3d : gpsSol.groundSpeed; - // Only add up movement when speed is faster than minimum threshold - if (speed > GPS_DISTANCE_FLOWN_MIN_SPEED_THRESHOLD_CM_S) { - uint32_t dist; - GPS_distance_cm_bearing(&gpsSol.llh, &lastLLH, gpsConfig()->gps_use_3d_speed, &dist, NULL); - GPS_distanceFlownInCm += dist; - } + } else if (STATE(GPS_FIX_HOME) && ARMING_FLAG(ARMED)) { + uint16_t speed = gpsConfig()->gps_use_3d_speed ? gpsSol.speed3d : gpsSol.groundSpeed; + // Only add up movement when speed is faster than minimum threshold + if (speed > GPS_DISTANCE_FLOWN_MIN_SPEED_THRESHOLD_CM_S) { + uint32_t dist; + GPS_distance_cm_bearing(&gpsSol.llh, &lastLLH, gpsConfig()->gps_use_3d_speed, &dist, NULL); + GPS_distanceFlownInCm += dist; } } lastLLH = gpsSol.llh; @@ -2724,4 +2726,3 @@ baudRate_e getGpsPortActualBaudRateIndex(void) } #endif // USE_GPS - From d63726f92878bb5f0adf388c30231cd2bd4e32ff Mon Sep 17 00:00:00 2001 From: "Git bot (blckmn)" Date: Tue, 11 Feb 2025 06:25:04 +0000 Subject: [PATCH 112/244] Auto updated submodule references [11-02-2025] --- src/config | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/config b/src/config index 64337752ec..5ce9d40849 160000 --- a/src/config +++ b/src/config @@ -1 +1 @@ -Subproject commit 64337752ec6af16a8663b4df48d8a9eb8fb1fbdb +Subproject commit 5ce9d4084986d511d606cce66320fc028ec9483a From b96c0b69cbe0678dcec981363203937feebb5782 Mon Sep 17 00:00:00 2001 From: Petr Ledvina Date: Tue, 11 Feb 2025 15:57:21 +0100 Subject: [PATCH 113/244] CLI - prevent serial overflow (#14251) use serialWriteBufBlocking for cli, busy-waiting if TX buffer is full --- src/main/cli/cli.c | 2 +- src/main/drivers/serial.c | 12 ++++++++++++ src/main/drivers/serial.h | 1 + 3 files changed, 14 insertions(+), 1 deletion(-) diff --git a/src/main/cli/cli.c b/src/main/cli/cli.c index a619f06a83..40e080bdd3 100644 --- a/src/main/cli/cli.c +++ b/src/main/cli/cli.c @@ -6896,7 +6896,7 @@ void cliEnter(serialPort_t *serialPort, bool interactive) setPrintfSerialPort(cliPort); } - bufWriterInit(&cliWriterDesc, cliWriteBuffer, sizeof(cliWriteBuffer), (bufWrite_t)serialWriteBufShim, serialPort); + bufWriterInit(&cliWriterDesc, cliWriteBuffer, sizeof(cliWriteBuffer), (bufWrite_t)serialWriteBufBlockingShim, serialPort); cliErrorWriter = cliWriter = &cliWriterDesc; if (interactive) { diff --git a/src/main/drivers/serial.c b/src/main/drivers/serial.c index 6fae5d7e59..d8bf92474a 100644 --- a/src/main/drivers/serial.c +++ b/src/main/drivers/serial.c @@ -129,8 +129,20 @@ void serialWriteBuf(serialPort_t *instance, const uint8_t *data, int count) serialEndWrite(instance); } +void serialWriteBufBlocking(serialPort_t *instance, const uint8_t *data, int count) +{ + while (serialTxBytesFree(instance) < (uint32_t)count) /* NOP */; + serialWriteBuf(instance, data, count); +} + void serialWriteBufShim(void *instance, const uint8_t *data, int count) { serialWriteBuf((serialPort_t *)instance, data, count); } +void serialWriteBufBlockingShim(void *instance, const uint8_t *data, int count) +{ + serialWriteBufBlocking(instance, data, count); +} + + diff --git a/src/main/drivers/serial.h b/src/main/drivers/serial.h index f5f21bb74e..ce9a8ca1f9 100644 --- a/src/main/drivers/serial.h +++ b/src/main/drivers/serial.h @@ -150,5 +150,6 @@ uint32_t serialGetBaudRate(serialPort_t *instance); // A shim that adapts the bufWriter API to the serialWriteBuf() API. void serialWriteBufShim(void *instance, const uint8_t *data, int count); +void serialWriteBufBlockingShim(void *instance, const uint8_t *data, int count); void serialBeginWrite(serialPort_t *instance); void serialEndWrite(serialPort_t *instance); From eae7e350029a783e8c9c18d55b94c9ed1c8afc18 Mon Sep 17 00:00:00 2001 From: "Git bot (blckmn)" Date: Fri, 14 Feb 2025 06:25:04 +0000 Subject: [PATCH 114/244] Auto updated submodule references [14-02-2025] --- src/config | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/config b/src/config index 5ce9d40849..cab072104b 160000 --- a/src/config +++ b/src/config @@ -1 +1 @@ -Subproject commit 5ce9d4084986d511d606cce66320fc028ec9483a +Subproject commit cab072104b28b92a7b6c2946c4de1e76648e570f From b6cfe2e2074ddae4bb9455dc2bca7470164add65 Mon Sep 17 00:00:00 2001 From: Mark Haslinghuis Date: Fri, 14 Feb 2025 10:03:28 +0100 Subject: [PATCH 115/244] Add SPI_DEVICE_4 to AT32 targets (#14255) --- src/platform/AT32/target/AT32F435G/target.h | 1 + src/platform/AT32/target/AT32F435M/target.h | 1 + 2 files changed, 2 insertions(+) diff --git a/src/platform/AT32/target/AT32F435G/target.h b/src/platform/AT32/target/AT32F435G/target.h index 76a4e039dc..b76a523cd4 100644 --- a/src/platform/AT32/target/AT32F435G/target.h +++ b/src/platform/AT32/target/AT32F435G/target.h @@ -60,6 +60,7 @@ #define USE_SPI_DEVICE_1 #define USE_SPI_DEVICE_2 #define USE_SPI_DEVICE_3 +#define USE_SPI_DEVICE_4 #define USE_SPI_DMA_ENABLE_LATE #define USE_EXTI diff --git a/src/platform/AT32/target/AT32F435M/target.h b/src/platform/AT32/target/AT32F435M/target.h index 3429a10876..fb52e7fcea 100644 --- a/src/platform/AT32/target/AT32F435M/target.h +++ b/src/platform/AT32/target/AT32F435M/target.h @@ -60,6 +60,7 @@ #define USE_SPI_DEVICE_1 #define USE_SPI_DEVICE_2 #define USE_SPI_DEVICE_3 +#define USE_SPI_DEVICE_4 #define USE_SPI_DMA_ENABLE_LATE #define USE_EXTI From 1db7c1184dd29e86b049e528f82a7e6ef3af5073 Mon Sep 17 00:00:00 2001 From: Mark Haslinghuis Date: Fri, 14 Feb 2025 16:35:38 +0100 Subject: [PATCH 116/244] Reduce required motors for MIXER_CUSTOM_AIRPLANE (#14257) Update CUSTOM_AIRPLANE mixer to require one motor --- src/main/flight/mixer_init.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/flight/mixer_init.c b/src/main/flight/mixer_init.c index be226230f8..e1d0eafe39 100644 --- a/src/main/flight/mixer_init.c +++ b/src/main/flight/mixer_init.c @@ -268,7 +268,7 @@ const mixer_t mixers[] = { { 1, true, NULL }, // MIXER_SINGLECOPTER { 4, false, mixerAtail4 }, // MIXER_ATAIL4 { 0, false, NULL }, // MIXER_CUSTOM - { 2, true, NULL }, // MIXER_CUSTOM_AIRPLANE + { 1, true, NULL }, // MIXER_CUSTOM_AIRPLANE { 3, true, NULL }, // MIXER_CUSTOM_TRI { 4, false, mixerQuadX1234 }, // MIXER_QUADX_1234 { 8, false, mixerOctoX8P }, // MIXER_OCTOX8P From 66ce15c74e9b1172fa6619769490b23c4c35c6c4 Mon Sep 17 00:00:00 2001 From: "Git bot (blckmn)" Date: Sat, 15 Feb 2025 06:25:03 +0000 Subject: [PATCH 117/244] Auto updated submodule references [15-02-2025] --- src/config | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/config b/src/config index cab072104b..ff6095ae17 160000 --- a/src/config +++ b/src/config @@ -1 +1 @@ -Subproject commit cab072104b28b92a7b6c2946c4de1e76648e570f +Subproject commit ff6095ae177dc7f729dd827fdd9584bf28995cec From 95b43ec175b774d5362dd099afdddf0983a6b8b1 Mon Sep 17 00:00:00 2001 From: "Git bot (blckmn)" Date: Mon, 17 Feb 2025 06:25:03 +0000 Subject: [PATCH 118/244] Auto updated submodule references [17-02-2025] --- src/config | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/config b/src/config index ff6095ae17..bd712ef4cc 160000 --- a/src/config +++ b/src/config @@ -1 +1 @@ -Subproject commit ff6095ae177dc7f729dd827fdd9584bf28995cec +Subproject commit bd712ef4cc19d400f715aabd9b96777739ae00fc From 7789ecafe3aa58c29a47da8f023bc891788cd468 Mon Sep 17 00:00:00 2001 From: kensherman <17434103+kensherman@users.noreply.github.com> Date: Mon, 17 Feb 2025 14:30:35 -0600 Subject: [PATCH 119/244] increasing number of msp ports (#14263) * increasing number of msp ports * Adding custom define and bumping to 6 ports * reverting msp ports to allow to be bumped at build time * Update src/main/msp/msp_serial.h Co-authored-by: Mark Haslinghuis * reset src/config --------- Co-authored-by: nerdCopter <56646290+nerdCopter@users.noreply.github.com> Co-authored-by: Mark Haslinghuis --- src/main/msp/msp_serial.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/main/msp/msp_serial.h b/src/main/msp/msp_serial.h index a080408fc7..315e003060 100644 --- a/src/main/msp/msp_serial.h +++ b/src/main/msp/msp_serial.h @@ -27,7 +27,9 @@ #include "msp/msp.h" // Each MSP port requires state and a receive buffer, revisit this default if someone needs more than 3 MSP ports. +#ifndef MAX_MSP_PORT_COUNT #define MAX_MSP_PORT_COUNT 3 +#endif typedef enum { PORT_IDLE, From 1b36ccc063c1544c4f3d2b135f548f04a90fcc61 Mon Sep 17 00:00:00 2001 From: "Git bot (blckmn)" Date: Tue, 18 Feb 2025 06:25:04 +0000 Subject: [PATCH 120/244] Auto updated submodule references [18-02-2025] --- src/config | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/config b/src/config index bd712ef4cc..651512d6e3 160000 --- a/src/config +++ b/src/config @@ -1 +1 @@ -Subproject commit bd712ef4cc19d400f715aabd9b96777739ae00fc +Subproject commit 651512d6e33e346aed88a58e0f5f2e6025cc2592 From 094d36bb6f86c3a037538c15d3b2ceb381d85474 Mon Sep 17 00:00:00 2001 From: crteensy Date: Tue, 18 Feb 2025 20:16:04 +0100 Subject: [PATCH 121/244] STM32G4: Add option to use external 26 MHz clock (#14261) --- src/main/fc/init.c | 2 +- src/platform/STM32/startup/system_stm32g4xx.c | 16 +++++++++++++--- 2 files changed, 14 insertions(+), 4 deletions(-) diff --git a/src/main/fc/init.c b/src/main/fc/init.c index bc0726fbbc..d48b5d6128 100644 --- a/src/main/fc/init.c +++ b/src/main/fc/init.c @@ -485,7 +485,7 @@ void init(void) #if defined(STM32F4) || defined(STM32G4) || defined(APM32F4) // F4 has non-8MHz boards - // G4 for Betaflight allow 24 or 27MHz oscillator + // G4 for Betaflight allow 8, 16, 24, 26 or 27MHz oscillator systemClockSetHSEValue(systemConfig()->hseMhz * 1000000U); #endif diff --git a/src/platform/STM32/startup/system_stm32g4xx.c b/src/platform/STM32/startup/system_stm32g4xx.c index 9874d2d1f1..5690987942 100644 --- a/src/platform/STM32/startup/system_stm32g4xx.c +++ b/src/platform/STM32/startup/system_stm32g4xx.c @@ -225,6 +225,7 @@ void Error_Handler(void) // Target frequencies for cpu_overclock (Levels 0 through 3) uint16_t sysclkSeries8[] = { 168, 192, 216, 240 }; +uint16_t sysclkSeries26[] = { 169, 195, 221, 247 }; uint16_t sysclkSeries27[] = { 171, 198, 225, 252 }; #define OVERCLOCK_LEVELS ARRAYLEN(sysclkSeries8) @@ -247,6 +248,13 @@ static bool systemComputePLLParameters(uint8_t src, uint16_t target, int *sysclk multDiff = vcoDiff / 16 * 2; *plln = 42 + multDiff; vcoFreq = 8 * *plln; + } else if (src == 26) { + *pllm = 2; + vcoBase = 169 * 2; + vcoDiff = vcoTarget - vcoBase; + multDiff = vcoDiff / 26 * 2; + *plln = 26 + multDiff; + vcoFreq = 13 * *plln; } else if (src == 27) { *pllm = 3; vcoBase = 171 * 2; @@ -289,8 +297,10 @@ static bool systemClock_PLLConfig(int overclockLevel) pllSrc = RCC_PLLSOURCE_HSE; if (pllInput == 8 || pllInput == 16 || pllInput == 24) { targetMhz = sysclkSeries8[overclockLevel]; + } else if (pllInput == 26) { + targetMhz = sysclkSeries26[overclockLevel]; } else if (pllInput == 27) { - targetMhz = sysclkSeries8[overclockLevel]; + targetMhz = sysclkSeries27[overclockLevel]; } else { return false; } @@ -303,9 +313,9 @@ void systemClockSetHSEValue(uint32_t frequency) { uint32_t freqMhz = frequency / 1000000; - // Only supported HSE crystal/resonator is 27MHz or integer multiples of 8MHz + // Only supported HSE crystal/resonator is 27MHz, 26 MHz or integer multiples of 8MHz - if (freqMhz != 27 && (freqMhz / 8) * 8 != freqMhz) { + if (freqMhz != 27 && freqMhz != 26 && (freqMhz / 8) * 8 != freqMhz) { return; } From df8beeeea8a549db7ca7822ac6b520ad827d4d3d Mon Sep 17 00:00:00 2001 From: "Git bot (blckmn)" Date: Wed, 19 Feb 2025 06:25:03 +0000 Subject: [PATCH 122/244] Auto updated submodule references [19-02-2025] --- src/config | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/config b/src/config index 651512d6e3..7fbb6e044c 160000 --- a/src/config +++ b/src/config @@ -1 +1 @@ -Subproject commit 651512d6e33e346aed88a58e0f5f2e6025cc2592 +Subproject commit 7fbb6e044c343825d9075950273c9d5518a03d14 From c91e3d1050b60bacdf1d03d93be66517467fccb3 Mon Sep 17 00:00:00 2001 From: "Git bot (blckmn)" Date: Thu, 20 Feb 2025 06:25:03 +0000 Subject: [PATCH 123/244] Auto updated submodule references [20-02-2025] --- src/config | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/config b/src/config index 7fbb6e044c..9a226da8fb 160000 --- a/src/config +++ b/src/config @@ -1 +1 @@ -Subproject commit 7fbb6e044c343825d9075950273c9d5518a03d14 +Subproject commit 9a226da8fbbcf2f17ddebf131cb668a782c18696 From 1359b40ee7aadf32a9b22feb99799633499f9b51 Mon Sep 17 00:00:00 2001 From: Steve Evans Date: Sat, 22 Feb 2025 16:17:48 +0000 Subject: [PATCH 124/244] Maintain state for i2c_ev_handler() for each i2c bus (#14268) --- src/platform/STM32/bus_i2c_stm32f4xx.c | 75 ++++++++++++++------------ 1 file changed, 41 insertions(+), 34 deletions(-) diff --git a/src/platform/STM32/bus_i2c_stm32f4xx.c b/src/platform/STM32/bus_i2c_stm32f4xx.c index 34a0c02802..2d7be2dfb5 100644 --- a/src/platform/STM32/bus_i2c_stm32f4xx.c +++ b/src/platform/STM32/bus_i2c_stm32f4xx.c @@ -116,6 +116,14 @@ const i2cHardware_t i2cHardware[I2CDEV_COUNT] = { i2cDevice_t i2cDevice[I2CDEV_COUNT]; +// State used by event handler ISR +typedef struct { + uint8_t subaddress_sent; // flag to indicate if subaddess sent + uint8_t final_stop; // flag to indicate final bus condition + int8_t index; // index is signed -1 == send the subaddress +} i2cEvState_t; +static i2cEvState_t i2c_ev_state[I2CDEV_COUNT]; + static volatile uint16_t i2cErrorCount = 0; void I2C1_ER_IRQHandler(void) @@ -316,18 +324,17 @@ void i2c_ev_handler(I2CDevice device) { I2C_TypeDef *I2Cx = i2cDevice[device].hardware->reg; + i2cEvState_t *ev_state = &i2c_ev_state[device]; i2cState_t *state = &i2cDevice[device].state; - static uint8_t subaddress_sent, final_stop; // flag to indicate if subaddess sent, flag to indicate final bus condition - static int8_t index; // index is signed -1 == send the subaddress uint8_t SReg_1 = I2Cx->SR1; // read the status register here if (SReg_1 & I2C_SR1_SB) { // we just sent a start - EV5 in ref manual I2Cx->CR1 &= ~I2C_CR1_POS; // reset the POS bit so ACK/NACK applied to the current byte I2C_AcknowledgeConfig(I2Cx, ENABLE); // make sure ACK is on - index = 0; // reset the index - if (state->reading && (subaddress_sent || 0xFF == state->reg)) { // we have sent the subaddr - subaddress_sent = 1; // make sure this is set in case of no subaddress, so following code runs correctly + ev_state->index = 0; // reset the index + if (state->reading && (ev_state->subaddress_sent || 0xFF == state->reg)) { // we have sent the subaddr + ev_state->subaddress_sent = 1; // make sure this is set in case of no subaddress, so following code runs correctly if (state->bytes == 2) I2Cx->CR1 |= I2C_CR1_POS; // set the POS bit so NACK applied to the final byte in the two byte read I2C_Send7bitAddress(I2Cx, state->addr, I2C_Direction_Receiver); // send the address and set hardware mode @@ -335,93 +342,93 @@ void i2c_ev_handler(I2CDevice device) else { // direction is Tx, or we havent sent the sub and rep start I2C_Send7bitAddress(I2Cx, state->addr, I2C_Direction_Transmitter); // send the address and set hardware mode if (state->reg != 0xFF) // 0xFF as subaddress means it will be ignored, in Tx or Rx mode - index = -1; // send a subaddress + ev_state->index = -1; // send a subaddress } } else if (SReg_1 & I2C_SR1_ADDR) { // we just sent the address - EV6 in ref manual // Read SR1,2 to clear ADDR __DMB(); // memory fence to control hardware - if (state->bytes == 1 && state->reading && subaddress_sent) { // we are receiving 1 byte - EV6_3 + if (state->bytes == 1 && state->reading && ev_state->subaddress_sent) { // we are receiving 1 byte - EV6_3 I2C_AcknowledgeConfig(I2Cx, DISABLE); // turn off ACK __DMB(); (void)I2Cx->SR2; // clear ADDR after ACK is turned off I2C_GenerateSTOP(I2Cx, ENABLE); // program the stop - final_stop = 1; + ev_state->final_stop = 1; I2C_ITConfig(I2Cx, I2C_IT_BUF, ENABLE); // allow us to have an EV7 } else { // EV6 and EV6_1 (void)I2Cx->SR2; // clear the ADDR here __DMB(); - if (state->bytes == 2 && state->reading && subaddress_sent) { // rx 2 bytes - EV6_1 + if (state->bytes == 2 && state->reading && ev_state->subaddress_sent) { // rx 2 bytes - EV6_1 I2C_AcknowledgeConfig(I2Cx, DISABLE); // turn off ACK I2C_ITConfig(I2Cx, I2C_IT_BUF, DISABLE); // disable TXE to allow the buffer to fill } - else if (state->bytes == 3 && state->reading && subaddress_sent) // rx 3 bytes + else if (state->bytes == 3 && state->reading && ev_state->subaddress_sent) // rx 3 bytes I2C_ITConfig(I2Cx, I2C_IT_BUF, DISABLE); // make sure RXNE disabled so we get a BTF in two bytes time else // receiving greater than three bytes, sending subaddress, or transmitting I2C_ITConfig(I2Cx, I2C_IT_BUF, ENABLE); } } else if (SReg_1 & I2C_SR1_BTF) { // Byte transfer finished - EV7_2, EV7_3 or EV8_2 - final_stop = 1; - if (state->reading && subaddress_sent) { // EV7_2, EV7_3 + ev_state->final_stop = 1; + if (state->reading && ev_state->subaddress_sent) { // EV7_2, EV7_3 if (state->bytes > 2) { // EV7_2 I2C_AcknowledgeConfig(I2Cx, DISABLE); // turn off ACK - state->read_p[index++] = (uint8_t)I2Cx->DR; // read data N-2 + state->read_p[ev_state->index++] = (uint8_t)I2Cx->DR; // read data N-2 I2C_GenerateSTOP(I2Cx, ENABLE); // program the Stop - final_stop = 1; // required to fix hardware - state->read_p[index++] = (uint8_t)I2Cx->DR; // read data N - 1 + ev_state->final_stop = 1; // required to fix hardware + state->read_p[ev_state->index++] = (uint8_t)I2Cx->DR; // read data N - 1 I2C_ITConfig(I2Cx, I2C_IT_BUF, ENABLE); // enable TXE to allow the final EV7 } else { // EV7_3 - if (final_stop) + if (ev_state->final_stop) I2C_GenerateSTOP(I2Cx, ENABLE); // program the Stop else I2C_GenerateSTART(I2Cx, ENABLE); // program a rep start - state->read_p[index++] = (uint8_t)I2Cx->DR; // read data N - 1 - state->read_p[index++] = (uint8_t)I2Cx->DR; // read data N - index++; // to show job completed + state->read_p[ev_state->index++] = (uint8_t)I2Cx->DR; // read data N - 1 + state->read_p[ev_state->index++] = (uint8_t)I2Cx->DR; // read data N + ev_state->index++; // to show job completed } } else { // EV8_2, which may be due to a subaddress sent or a write completion - if (subaddress_sent || (state->writing)) { - if (final_stop) + if (ev_state->subaddress_sent || (state->writing)) { + if (ev_state->final_stop) I2C_GenerateSTOP(I2Cx, ENABLE); // program the Stop else I2C_GenerateSTART(I2Cx, ENABLE); // program a rep start - index++; // to show that the job is complete + ev_state->index++; // to show that the job is complete } else { // We need to send a subaddress I2C_GenerateSTART(I2Cx, ENABLE); // program the repeated Start - subaddress_sent = 1; // this is set back to zero upon completion of the current task + ev_state->subaddress_sent = 1; // this is set back to zero upon completion of the current task } } // we must wait for the start to clear, otherwise we get constant BTF while (I2Cx->CR1 & I2C_CR1_START) {; } } else if (SReg_1 & I2C_SR1_RXNE) { // Byte received - EV7 - state->read_p[index++] = (uint8_t)I2Cx->DR; - if (state->bytes == (index + 3)) + state->read_p[ev_state->index++] = (uint8_t)I2Cx->DR; + if (state->bytes == (ev_state->index + 3)) I2C_ITConfig(I2Cx, I2C_IT_BUF, DISABLE); // disable TXE to allow the buffer to flush so we can get an EV7_2 - if (state->bytes == index) // We have completed a final EV7 - index++; // to show job is complete + if (state->bytes == ev_state->index) // We have completed a final EV7 + ev_state->index++; // to show job is complete } else if (SReg_1 & I2C_SR1_TXE) { // Byte transmitted EV8 / EV8_1 - if (index != -1) { // we dont have a subaddress to send - I2Cx->DR = state->write_p[index++]; - if (state->bytes == index) // we have sent all the data + if (ev_state->index != -1) { // we dont have a subaddress to send + I2Cx->DR = state->write_p[ev_state->index++]; + if (state->bytes == ev_state->index) // we have sent all the data I2C_ITConfig(I2Cx, I2C_IT_BUF, DISABLE); // disable TXE to allow the buffer to flush } else { - index++; + ev_state->index++; I2Cx->DR = state->reg; // send the subaddress if (state->reading || !(state->bytes)) // if receiving or sending 0 bytes, flush now I2C_ITConfig(I2Cx, I2C_IT_BUF, DISABLE); // disable TXE to allow the buffer to flush } } - if (index == state->bytes + 1) { // we have completed the current job - subaddress_sent = 0; // reset this here - if (final_stop) // If there is a final stop and no more jobs, bus is inactive, disable interrupts to prevent BTF + if (ev_state->index == state->bytes + 1) { // we have completed the current job + ev_state->subaddress_sent = 0; // reset this here + if (ev_state->final_stop) // If there is a final stop and no more jobs, bus is inactive, disable interrupts to prevent BTF I2C_ITConfig(I2Cx, I2C_IT_EVT | I2C_IT_ERR, DISABLE); // Disable EVT and ERR interrupts while bus inactive state->busy = 0; } From 6948fb75e995db7060ea0c5eafecd4f8177986f8 Mon Sep 17 00:00:00 2001 From: Petr Ledvina Date: Sat, 22 Feb 2025 18:02:57 +0100 Subject: [PATCH 125/244] Blackbox - IMU quaternion - fix case when w is negative (#14275) quaternion w can ce negative, causing problem with unit quaternion reconstruction. Send inverted quaternion in negative-w case (q and -q are identical rotations) --- src/main/blackbox/blackbox.c | 20 ++++++++++++++------ 1 file changed, 14 insertions(+), 6 deletions(-) diff --git a/src/main/blackbox/blackbox.c b/src/main/blackbox/blackbox.c index 42d274979f..7ece9940ca 100644 --- a/src/main/blackbox/blackbox.c +++ b/src/main/blackbox/blackbox.c @@ -365,7 +365,7 @@ typedef struct blackboxMainState_s { int16_t gyroUnfilt[XYZ_AXIS_COUNT]; #ifdef USE_ACC int16_t accADC[XYZ_AXIS_COUNT]; - int16_t imuAttitudeQuaternion[XYZ_AXIS_COUNT]; + int16_t imuAttitudeQuaternion3[XYZ_AXIS_COUNT]; // only x,y,z is stored; w is always positive #endif int16_t debug[DEBUG16_VALUE_COUNT]; int16_t motor[MAX_SUPPORTED_MOTORS]; @@ -747,7 +747,7 @@ static void writeIntraframe(void) } if (testBlackboxCondition(CONDITION(ATTITUDE))) { - blackboxWriteSigned16VBArray(blackboxCurrent->imuAttitudeQuaternion, XYZ_AXIS_COUNT); + blackboxWriteSigned16VBArray(blackboxCurrent->imuAttitudeQuaternion3, XYZ_AXIS_COUNT); } #endif @@ -932,7 +932,7 @@ static void writeInterframe(void) } if (testBlackboxCondition(CONDITION(ATTITUDE))) { - blackboxWriteMainStateArrayUsingAveragePredictor(offsetof(blackboxMainState_t, imuAttitudeQuaternion), XYZ_AXIS_COUNT); + blackboxWriteMainStateArrayUsingAveragePredictor(offsetof(blackboxMainState_t, imuAttitudeQuaternion3), XYZ_AXIS_COUNT); } #endif @@ -1250,14 +1250,22 @@ static void loadMainState(timeUs_t currentTimeUs) #if defined(USE_ACC) blackboxCurrent->accADC[i] = lrintf(acc.accADC.v[i]); - STATIC_ASSERT(offsetof(quaternion_t, w) == 0, "Code expects quaternion in w, x, y, z order"); - blackboxCurrent->imuAttitudeQuaternion[i] = lrintf(imuAttitudeQuaternion.v[i + 1] * 0x7FFF); //Scale to int16 by value 0x7FFF = 2^15 - 1; Use i+1 index for x,y,z components access, [0] - w #endif #ifdef USE_MAG blackboxCurrent->magADC[i] = lrintf(mag.magADC.v[i]); #endif } - +#if defined(USE_ACC) // IMU quaternion + { + // write x,y,z of IMU quaternion. Make sure that w is always positive + STATIC_ASSERT(offsetof(quaternion_t, w) == 0, "Code expects quaternion in w, x, y, z order"); + const float q_sign = imuAttitudeQuaternion.w < 0 ? -1 : 1; // invert quaternion if w is negative + const float q_scale = q_sign * 0x7FFF; // Scale to int16 by value 0x7FFF = 2^15 - 1 (-1 <= x,y,z <= 1) + for (int i = 0; i < XYZ_AXIS_COUNT; i++) { + blackboxCurrent->imuAttitudeQuaternion3[i] = lrintf(imuAttitudeQuaternion.v[i + 1] * q_scale); // Use i+1 index for x,y,z components access, [0] - w + } + } +#endif for (int i = 0; i < 4; i++) { blackboxCurrent->rcCommand[i] = lrintf(rcCommand[i] * blackboxHighResolutionScale); } From 611ad5907ccb8529a55021c760f821248e8bd56b Mon Sep 17 00:00:00 2001 From: Mark Haslinghuis Date: Sun, 23 Feb 2025 21:56:03 +0100 Subject: [PATCH 126/244] Update io_preinit.c (#14273) --- src/main/drivers/io_preinit.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/drivers/io_preinit.c b/src/main/drivers/io_preinit.c index 81ca43d420..98ab4fc29b 100644 --- a/src/main/drivers/io_preinit.c +++ b/src/main/drivers/io_preinit.c @@ -48,7 +48,7 @@ void ioPreinitByIO(const IO_t io, uint8_t iocfg, ioPreinitPinState_e init) IOHi(io); break; default: - // Do nothing + break; } } From c80de5c62af44d61f3e3e1c27b1bf448bacb3a52 Mon Sep 17 00:00:00 2001 From: "Git bot (blckmn)" Date: Tue, 25 Feb 2025 06:25:03 +0000 Subject: [PATCH 127/244] Auto updated submodule references [25-02-2025] --- src/config | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/config b/src/config index 9a226da8fb..b4ba6f92c2 160000 --- a/src/config +++ b/src/config @@ -1 +1 @@ -Subproject commit 9a226da8fbbcf2f17ddebf131cb668a782c18696 +Subproject commit b4ba6f92c25d995e0277712c901fd644124715cf From a779ffaff70ed1bbd4eede60fc28e6e1df767a36 Mon Sep 17 00:00:00 2001 From: "Git bot (blckmn)" Date: Wed, 26 Feb 2025 06:25:03 +0000 Subject: [PATCH 128/244] Auto updated submodule references [26-02-2025] --- src/config | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/config b/src/config index b4ba6f92c2..3d55cd45bd 160000 --- a/src/config +++ b/src/config @@ -1 +1 @@ -Subproject commit b4ba6f92c25d995e0277712c901fd644124715cf +Subproject commit 3d55cd45bdc6ba9dad631e4021c52037b8f3d127 From 84c11a5009aa0465aa5aea1e53e3f3a242a0b177 Mon Sep 17 00:00:00 2001 From: Jay Blackman Date: Thu, 27 Feb 2025 03:21:05 +1100 Subject: [PATCH 129/244] FIX: PWM motor output stopped working after #14156 (#14280) FIX: https://github.com/betaflight/betaflight/issues/14265 --- src/main/drivers/motor.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/drivers/motor.c b/src/main/drivers/motor.c index 22f2415a11..9060316a62 100644 --- a/src/main/drivers/motor.c +++ b/src/main/drivers/motor.c @@ -184,7 +184,7 @@ bool checkMotorProtocolEnabled(const motorDevConfig_t *motorDevConfig, bool *isP motorProtocolFamily_e motorGetProtocolFamily(void) { switch (motorConfig()->dev.motorProtocol) { -#ifdef USE_PWMOUTPUT +#ifdef USE_PWM_OUTPUT case MOTOR_PROTOCOL_PWM : case MOTOR_PROTOCOL_ONESHOT125: case MOTOR_PROTOCOL_ONESHOT42: From a801aadf9cc1bea189c147f7a0c1f1655297e15f Mon Sep 17 00:00:00 2001 From: "Git bot (blckmn)" Date: Thu, 27 Feb 2025 06:25:03 +0000 Subject: [PATCH 130/244] Auto updated submodule references [27-02-2025] --- src/config | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/config b/src/config index 3d55cd45bd..5f4908dd85 160000 --- a/src/config +++ b/src/config @@ -1 +1 @@ -Subproject commit 3d55cd45bdc6ba9dad631e4021c52037b8f3d127 +Subproject commit 5f4908dd859e413b90d9362230f81d48727cedaa From d8cd6b743be808278115f55cb0383671fb188ce9 Mon Sep 17 00:00:00 2001 From: crteensy Date: Thu, 27 Feb 2025 13:46:26 +0100 Subject: [PATCH 131/244] Properly handle HSI if selected (#14259) * Properly handle HSI if selected In some places, PERSISTENT_OBJECT_HSE_VALUE being zero is used to imply that the MCU should be clocked from HSI, but the code doesn't really follow through and results in an invalid clock tree setup. The proposed changes should fix this. * Apply suggestions from code review Co-authored-by: Mark Haslinghuis * Update system_stm32g4xx.c HSI should now be implicitly selected when SYSTEM_HSE_MHZ is defined as 0 or omitted in the target config. USE_CLOCK_SOURCE_HSI is not necessary. * Update src/platform/STM32/startup/system_stm32g4xx.c Co-authored-by: Petr Ledvina * Update src/platform/STM32/startup/system_stm32g4xx.c Co-authored-by: Mark Haslinghuis --------- Co-authored-by: Mark Haslinghuis Co-authored-by: Petr Ledvina --- src/platform/STM32/startup/system_stm32g4xx.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/src/platform/STM32/startup/system_stm32g4xx.c b/src/platform/STM32/startup/system_stm32g4xx.c index 5690987942..9a35bdef64 100644 --- a/src/platform/STM32/startup/system_stm32g4xx.c +++ b/src/platform/STM32/startup/system_stm32g4xx.c @@ -118,7 +118,6 @@ void SystemInit(void) void SystemCoreClockUpdate(void) { uint32_t hse_value = persistentObjectRead(PERSISTENT_OBJECT_HSE_VALUE); - uint32_t tmp, pllvco, pllr, pllsource, pllm; /* Get SYSCLK source -------------------------------------------------------*/ @@ -381,10 +380,12 @@ void SystemClock_Config(void) // Initializes the CPU, AHB and APB busses clocks - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI|RCC_OSCILLATORTYPE_HSI48 - |RCC_OSCILLATORTYPE_LSI|RCC_OSCILLATORTYPE_HSE; - - RCC_OscInitStruct.HSEState = RCC_HSE_ON; + const bool useHse = persistentObjectRead(PERSISTENT_OBJECT_HSE_VALUE) != 0; + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSI48 + | RCC_OSCILLATORTYPE_LSI + | (useHse ? RCC_OSCILLATORTYPE_HSE : 0); + RCC_OscInitStruct.HSEState = useHse ? RCC_HSE_ON : RCC_HSE_OFF; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; RCC_OscInitStruct.LSIState = RCC_LSI_ON; From 0b4b1123cd822d0285a846bd7bcbabdfa3e6dc3d Mon Sep 17 00:00:00 2001 From: "Git bot (blckmn)" Date: Fri, 28 Feb 2025 06:25:03 +0000 Subject: [PATCH 132/244] Auto updated submodule references [28-02-2025] --- src/config | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/config b/src/config index 5f4908dd85..337bf96ddc 160000 --- a/src/config +++ b/src/config @@ -1 +1 @@ -Subproject commit 5f4908dd859e413b90d9362230f81d48727cedaa +Subproject commit 337bf96ddc627c3d87c6294fda966f01acb760e6 From 99e8dd8840877e2b30fa14756b1fd9b7fd0fdf8f Mon Sep 17 00:00:00 2001 From: Petr Ledvina Date: Sat, 1 Mar 2025 07:40:02 +0100 Subject: [PATCH 133/244] Fix virtualled (#14276) --- src/main/cli/cli.c | 4 ++- src/main/cli/settings.c | 4 ++- src/main/drivers/light_led.c | 60 +++++++++++++++++------------------- src/main/drivers/light_led.h | 40 ++++++++++-------------- src/test/unit/target.h | 1 + 5 files changed, 52 insertions(+), 57 deletions(-) diff --git a/src/main/cli/cli.c b/src/main/cli/cli.c index 40e080bdd3..b9539389ec 100644 --- a/src/main/cli/cli.c +++ b/src/main/cli/cli.c @@ -5096,7 +5096,9 @@ const cliResourceValue_t resourceTable[] = { DEFW( OWNER_I2C_SCL, PG_I2C_CONFIG, i2cConfig_t, ioTagScl, I2CDEV_COUNT ), DEFW( OWNER_I2C_SDA, PG_I2C_CONFIG, i2cConfig_t, ioTagSda, I2CDEV_COUNT ), #endif - DEFA( OWNER_LED, PG_STATUS_LED_CONFIG, statusLedConfig_t, ioTags[0], STATUS_LED_NUMBER ), +#if !defined(USE_VIRTUAL_LED) + DEFA( OWNER_LED, PG_STATUS_LED_CONFIG, statusLedConfig_t, ioTags[0], STATUS_LED_COUNT ), +#endif #ifdef USE_SPEKTRUM_BIND DEFS( OWNER_RX_BIND, PG_RX_CONFIG, rxConfig_t, spektrum_bind_pin_override_ioTag ), DEFS( OWNER_RX_BIND_PLUG, PG_RX_CONFIG, rxConfig_t, spektrum_bind_plug_ioTag ), diff --git a/src/main/cli/settings.c b/src/main/cli/settings.c index cc5ef8571d..e1b9bdd91e 100644 --- a/src/main/cli/settings.c +++ b/src/main/cli/settings.c @@ -1749,7 +1749,9 @@ const clivalue_t valueTable[] = { { "frsky_spi_a1_source", VAR_UINT8 | MASTER_VALUE | MODE_LOOKUP, .config.lookup = { TABLE_RX_FRSKY_SPI_A1_SOURCE }, PG_RX_CC2500_SPI_CONFIG, offsetof(rxCc2500SpiConfig_t, a1Source) }, { "cc2500_spi_chip_detect", VAR_UINT8 | HARDWARE_VALUE | MODE_LOOKUP, .config.lookup = { TABLE_OFF_ON }, PG_RX_CC2500_SPI_CONFIG, offsetof(rxCc2500SpiConfig_t, chipDetectEnabled) }, #endif - { "led_inversion", VAR_UINT8 | HARDWARE_VALUE, .config.minmaxUnsigned = { 0, ((1 << STATUS_LED_NUMBER) - 1) }, PG_STATUS_LED_CONFIG, offsetof(statusLedConfig_t, inversion) }, +#if !defined(USE_VIRTUAL_LED) + { "led_inversion", VAR_UINT8 | HARDWARE_VALUE, .config.minmaxUnsigned = { 0, ((1 << STATUS_LED_COUNT) - 1) }, PG_STATUS_LED_CONFIG, offsetof(statusLedConfig_t, inversion) }, +#endif #ifdef USE_DASHBOARD { "dashboard_i2c_bus", VAR_UINT8 | HARDWARE_VALUE, .config.minmaxUnsigned = { 0, I2CDEV_COUNT }, PG_DASHBOARD_CONFIG, offsetof(dashboardConfig_t, device) }, { "dashboard_i2c_addr", VAR_UINT8 | HARDWARE_VALUE, .config.minmaxUnsigned = { I2C_ADDR7_MIN, I2C_ADDR7_MAX }, PG_DASHBOARD_CONFIG, offsetof(dashboardConfig_t, address) }, diff --git a/src/main/drivers/light_led.c b/src/main/drivers/light_led.c index e0be78bd97..ca8917bdd1 100644 --- a/src/main/drivers/light_led.c +++ b/src/main/drivers/light_led.c @@ -27,32 +27,26 @@ #include "light_led.h" -#if !(defined(UNIT_TEST) || defined(USE_VIRTUAL_LED)) +#if !defined(USE_VIRTUAL_LED) -PG_REGISTER_WITH_RESET_FN(statusLedConfig_t, statusLedConfig, PG_STATUS_LED_CONFIG, 0); - -static IO_t leds[STATUS_LED_NUMBER]; +static IO_t leds[STATUS_LED_COUNT]; static uint8_t ledInversion = 0; -#ifndef LED0_PIN -#define LED0_PIN NONE +PG_REGISTER_WITH_RESET_TEMPLATE(statusLedConfig_t, statusLedConfig, PG_STATUS_LED_CONFIG, 0); + +PG_RESET_TEMPLATE(statusLedConfig_t, statusLedConfig, + .ioTags = { +#if STATUS_LED_COUNT > 0 && defined(LED0_PIN) + [0] = IO_TAG(LED0_PIN), #endif - -#ifndef LED1_PIN -#define LED1_PIN NONE +#if STATUS_LED_COUNT > 1 && defined(LED1_PIN) + [1] = IO_TAG(LED1_PIN), #endif - -#ifndef LED2_PIN -#define LED2_PIN NONE +#if STATUS_LED_COUNT > 2 && defined(LED2_PIN) + [2] = IO_TAG(LED2_PIN), #endif - -void pgResetFn_statusLedConfig(statusLedConfig_t *statusLedConfig) -{ - statusLedConfig->ioTags[0] = IO_TAG(LED0_PIN); - statusLedConfig->ioTags[1] = IO_TAG(LED1_PIN); - statusLedConfig->ioTags[2] = IO_TAG(LED2_PIN); - - statusLedConfig->inversion = 0 + }, + .inversion = 0 #ifdef LED0_INVERTED | BIT(0) #endif @@ -62,35 +56,37 @@ void pgResetFn_statusLedConfig(statusLedConfig_t *statusLedConfig) #ifdef LED2_INVERTED | BIT(2) #endif - ; -} + , +); void ledInit(const statusLedConfig_t *statusLedConfig) { ledInversion = statusLedConfig->inversion; - for (int i = 0; i < STATUS_LED_NUMBER; i++) { - if (statusLedConfig->ioTags[i]) { - leds[i] = IOGetByTag(statusLedConfig->ioTags[i]); + for (int i = 0; i < (int)ARRAYLEN(leds); i++) { + leds[i] = IOGetByTag(statusLedConfig->ioTags[i]); + if (leds[i]) { IOInit(leds[i], OWNER_LED, RESOURCE_INDEX(i)); IOConfigGPIO(leds[i], IOCFG_OUT_PP); - } else { - leds[i] = IO_NONE; } + ledSet(i, false); } - - LED0_OFF; - LED1_OFF; - LED2_OFF; } void ledToggle(int led) { + if (led < 0 || led >= (int)ARRAYLEN(leds)) { + return; + } IOToggle(leds[led]); } void ledSet(int led, bool on) { - const bool inverted = (1 << (led)) & ledInversion; + if (led < 0 || led >= (int)ARRAYLEN(leds)) { + return; + } + const bool inverted = ledInversion & (1 << led); IOWrite(leds[led], on ? inverted : !inverted); } + #endif diff --git a/src/main/drivers/light_led.h b/src/main/drivers/light_led.h index 0543f0478d..8d995e7edc 100644 --- a/src/main/drivers/light_led.h +++ b/src/main/drivers/light_led.h @@ -24,31 +24,9 @@ #include "drivers/io_types.h" #include "common/utils.h" -#define STATUS_LED_NUMBER 3 - -typedef struct statusLedConfig_s { - ioTag_t ioTags[STATUS_LED_NUMBER]; - uint8_t inversion; -} statusLedConfig_t; +#define STATUS_LED_COUNT 3 // Helpful macros -#if defined(UNIT_TEST) || defined(USE_VIRTUAL_LED) - -#define LED0_TOGGLE NOOP -#define LED0_OFF NOOP -#define LED0_ON NOOP - -#define LED1_TOGGLE NOOP -#define LED1_OFF NOOP -#define LED1_ON NOOP - -#define LED2_TOGGLE NOOP -#define LED2_OFF NOOP -#define LED2_ON NOOP - -#else - -PG_DECLARE(statusLedConfig_t, statusLedConfig); #define LED0_TOGGLE ledToggle(0) #define LED0_OFF ledSet(0, false) @@ -62,6 +40,22 @@ PG_DECLARE(statusLedConfig_t, statusLedConfig); #define LED2_OFF ledSet(2, false) #define LED2_ON ledSet(2, true) +// use dummy functions for unittest +#if defined(USE_VIRTUAL_LED) + +// ledInit is missing intentionally +static inline void ledToggle(int led) { UNUSED(led); } +static inline void ledSet(int led, bool state) { UNUSED(led); UNUSED(state); } + +#else + +typedef struct statusLedConfig_s { + ioTag_t ioTags[STATUS_LED_COUNT]; + uint8_t inversion; +} statusLedConfig_t; + +PG_DECLARE(statusLedConfig_t, statusLedConfig); + void ledInit(const statusLedConfig_t *statusLedConfig); void ledToggle(int led); void ledSet(int led, bool state); diff --git a/src/test/unit/target.h b/src/test/unit/target.h index 866d9afe9a..068e96fe2b 100644 --- a/src/test/unit/target.h +++ b/src/test/unit/target.h @@ -58,6 +58,7 @@ #define USE_LED_STRIP_STATUS_MODE #define USE_SERVOS #define USE_TRANSPONDER +#define USE_VIRTUAL_LED #define USE_VCP #define USE_UART1 #define USE_UART2 From 9e53f4ad5b87a762b608c6d6b0f6b765e20c0cae Mon Sep 17 00:00:00 2001 From: "Git bot (blckmn)" Date: Thu, 6 Mar 2025 06:25:03 +0000 Subject: [PATCH 134/244] Auto updated submodule references [06-03-2025] --- src/config | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/config b/src/config index 337bf96ddc..c4353ec9c9 160000 --- a/src/config +++ b/src/config @@ -1 +1 @@ -Subproject commit 337bf96ddc627c3d87c6294fda966f01acb760e6 +Subproject commit c4353ec9c9772c7bfb14caa5a22bfd30b7109de8 From f33e1614edd57429657a35f1fc53f379e1c793ba Mon Sep 17 00:00:00 2001 From: Mark Haslinghuis Date: Tue, 11 Mar 2025 17:07:43 +0100 Subject: [PATCH 135/244] Fix typo in accgyro_spi_icm426xx.c (#14290) --- src/main/drivers/accgyro/accgyro_spi_icm426xx.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/drivers/accgyro/accgyro_spi_icm426xx.c b/src/main/drivers/accgyro/accgyro_spi_icm426xx.c index 5e8e4cc574..204b547c56 100644 --- a/src/main/drivers/accgyro/accgyro_spi_icm426xx.c +++ b/src/main/drivers/accgyro/accgyro_spi_icm426xx.c @@ -169,7 +169,7 @@ static aafConfig_t aafLUT42688[AAF_CONFIG_COUNT] = { // see table in section 5. [AAF_CONFIG_1962HZ] = { 37, 1376, 4 }, }; -// Possible gyro Anti-Alias Filter (AAF) cutoffs for ICM-42688P +// Possible gyro Anti-Alias Filter (AAF) cutoffs for ICM-42605 // actual cutoff differs slightly from those of the 42688P static aafConfig_t aafLUT42605[AAF_CONFIG_COUNT] = { // see table in section 5.3 [AAF_CONFIG_258HZ] = { 21, 440, 6 }, // actually 249 Hz From 225bb21e9c42d591400ff43aa55e32d247ad4ae9 Mon Sep 17 00:00:00 2001 From: "Git bot (blckmn)" Date: Thu, 13 Mar 2025 06:25:03 +0000 Subject: [PATCH 136/244] Auto updated submodule references [13-03-2025] --- src/config | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/config b/src/config index c4353ec9c9..ed54f70c18 160000 --- a/src/config +++ b/src/config @@ -1 +1 @@ -Subproject commit c4353ec9c9772c7bfb14caa5a22bfd30b7109de8 +Subproject commit ed54f70c185e2779288fad07199cd4b533318bb7 From f5404097688d86cf0a296e1cf3811839f09909d2 Mon Sep 17 00:00:00 2001 From: fluke9 Date: Thu, 13 Mar 2025 19:30:14 +0100 Subject: [PATCH 137/244] fix: led strip not working (#14279) (#14286) * fix: led strip not working (#14279) * fix: led strip not working reworked (#14279) * Revert src/platform/STM32/target/STM32F745/target.h * Revert src/platform/STM32/target/STM32F7X2/target.h * Fix per review ledvinap --------- Co-authored-by: Mark Haslinghuis --- src/main/drivers/light_ws2811strip.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/drivers/light_ws2811strip.c b/src/main/drivers/light_ws2811strip.c index 9547eda9c9..b69b87ca58 100644 --- a/src/main/drivers/light_ws2811strip.c +++ b/src/main/drivers/light_ws2811strip.c @@ -60,7 +60,7 @@ #define WS2811_DMA_BUF_CACHE_ALIGN_LENGTH (WS2811_DMA_BUF_CACHE_ALIGN_BYTES / sizeof(uint32_t)) DMA_RW_AXI __attribute__((aligned(32))) uint32_t ledStripDMABuffer[WS2811_DMA_BUF_CACHE_ALIGN_LENGTH]; #else -FAST_DATA_ZERO_INIT uint32_t ledStripDMABuffer[WS2811_DMA_BUFFER_SIZE]; +DMA_DATA_ZERO_INIT uint32_t ledStripDMABuffer[WS2811_DMA_BUFFER_SIZE]; #endif static ioTag_t ledStripIoTag; From a7323389051d03390a0c36a84164f9b5eac3bd7d Mon Sep 17 00:00:00 2001 From: "Git bot (blckmn)" Date: Fri, 14 Mar 2025 06:25:03 +0000 Subject: [PATCH 138/244] Auto updated submodule references [14-03-2025] --- src/config | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/config b/src/config index ed54f70c18..595cf6f71a 160000 --- a/src/config +++ b/src/config @@ -1 +1 @@ -Subproject commit ed54f70c185e2779288fad07199cd4b533318bb7 +Subproject commit 595cf6f71a16c8d411f7ece975e7a5e273c5e837 From 92c59091cee24c48d0cf142b8ee0b0b5dfc07c2e Mon Sep 17 00:00:00 2001 From: Mark Haslinghuis Date: Fri, 14 Mar 2025 22:27:17 +0100 Subject: [PATCH 139/244] Change airborne default (#14271) --- src/main/pg/gps.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/pg/gps.c b/src/main/pg/gps.c index 81f9e0e396..c8d5df62f8 100644 --- a/src/main/pg/gps.c +++ b/src/main/pg/gps.c @@ -41,7 +41,7 @@ PG_RESET_TEMPLATE(gpsConfig_t, gpsConfig, .autoConfig = GPS_AUTOCONFIG_ON, .autoBaud = GPS_AUTOBAUD_OFF, .gps_ublox_acquire_model = UBLOX_MODEL_STATIONARY, - .gps_ublox_flight_model = UBLOX_MODEL_AIRBORNE_4G, + .gps_ublox_flight_model = UBLOX_MODEL_AIRBORNE_1G, .gps_update_rate_hz = 10, .gps_ublox_use_galileo = false, .gps_set_home_point_once = false, From 0350bd3188504ef065beaa56de273a65326e1fc0 Mon Sep 17 00:00:00 2001 From: "Git bot (blckmn)" Date: Sat, 15 Mar 2025 06:25:03 +0000 Subject: [PATCH 140/244] Auto updated submodule references [15-03-2025] --- src/config | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/config b/src/config index 595cf6f71a..3c65ad85a6 160000 --- a/src/config +++ b/src/config @@ -1 +1 @@ -Subproject commit 595cf6f71a16c8d411f7ece975e7a5e273c5e837 +Subproject commit 3c65ad85a6c25f83944f4e491b7a5ee6644d71c6 From 7e47905132fa3eb587ba07f61eddf79e646de10c Mon Sep 17 00:00:00 2001 From: "Git bot (blckmn)" Date: Tue, 18 Mar 2025 06:25:03 +0000 Subject: [PATCH 141/244] Auto updated submodule references [18-03-2025] --- src/config | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/config b/src/config index 3c65ad85a6..0f78778100 160000 --- a/src/config +++ b/src/config @@ -1 +1 @@ -Subproject commit 3c65ad85a6c25f83944f4e491b7a5ee6644d71c6 +Subproject commit 0f7877810016660eb0cace94211d8077bf51ac75 From 8dafdbce41460c01dc8f552d2b2aa330949a0485 Mon Sep 17 00:00:00 2001 From: "Git bot (blckmn)" Date: Fri, 21 Mar 2025 06:25:03 +0000 Subject: [PATCH 142/244] Auto updated submodule references [21-03-2025] --- src/config | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/config b/src/config index 0f78778100..3eedb40cf0 160000 --- a/src/config +++ b/src/config @@ -1 +1 @@ -Subproject commit 0f7877810016660eb0cace94211d8077bf51ac75 +Subproject commit 3eedb40cf07dc40c246cd0416d04464aeb7c73c6 From 9c8f84f62d75d9025c8bbda8af5664c141ef67fe Mon Sep 17 00:00:00 2001 From: nerdCopter <56646290+nerdCopter@users.noreply.github.com> Date: Fri, 21 Mar 2025 17:27:40 -0500 Subject: [PATCH 143/244] Fix gimbalCmdIn.u.crc to gimbalCmdIn.u.gimbalCmd.crc (#14311) --- src/main/io/gimbal_control.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/io/gimbal_control.c b/src/main/io/gimbal_control.c index 73a89f3c55..a9948abee8 100644 --- a/src/main/io/gimbal_control.c +++ b/src/main/io/gimbal_control.c @@ -288,7 +288,7 @@ void gimbalUpdate(timeUs_t currentTimeUs) if (gimbalInCount == sizeof(gimbalCmdIn.u.gimbalCmd)) { uint16_t crc = gimbalCrc((uint8_t *)&gimbalCmdIn, sizeof(gimbalCmdIn) - 2); // Only use the data if the CRC is correct - if (gimbalCmdIn.u.crc == crc) { + if (gimbalCmdIn.u.gimbalCmd.crc == crc) { gimbalCmdOut = gimbalCmdIn.u.gimbalCmd; gimbalSet(gimbalCmdIn.u.gimbalCmd.roll, gimbalCmdIn.u.gimbalCmd.pitch, gimbalCmdIn.u.gimbalCmd.yaw); serialWriteBuf(gimbalSerialPort, (uint8_t *)&gimbalCmdOut, sizeof(gimbalCmdOut)); From 3ae8056ec6178b589f2f61a499f11643defb949f Mon Sep 17 00:00:00 2001 From: Mark Haslinghuis Date: Fri, 21 Mar 2025 23:32:42 +0100 Subject: [PATCH 144/244] Fix typos (#14315) --- src/main/flight/pos_hold_multirotor.c | 2 +- src/main/flight/pos_hold_wing.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/main/flight/pos_hold_multirotor.c b/src/main/flight/pos_hold_multirotor.c index ba977d8589..e811b433da 100644 --- a/src/main/flight/pos_hold_multirotor.c +++ b/src/main/flight/pos_hold_multirotor.c @@ -105,6 +105,6 @@ bool posHoldFailure(void) { return FLIGHT_MODE(POS_HOLD_MODE) && (!posHold.isControlOk || !posHold.areSensorsOk); } -#endif // USE_POS_HOLD +#endif // USE_POSITION_HOLD #endif // !USE_WING diff --git a/src/main/flight/pos_hold_wing.c b/src/main/flight/pos_hold_wing.c index fac189426f..211645565e 100644 --- a/src/main/flight/pos_hold_wing.c +++ b/src/main/flight/pos_hold_wing.c @@ -52,6 +52,6 @@ bool posHoldFailure(void) { return true; } -#endif // USE_POS_HOLD +#endif // USE_POSITION_HOLD #endif // USE_WING From bf4a1a24969f26d9a1bc87cc990e8e3877bf7726 Mon Sep 17 00:00:00 2001 From: "Git bot (blckmn)" Date: Mon, 24 Mar 2025 06:25:03 +0000 Subject: [PATCH 145/244] Auto updated submodule references [24-03-2025] --- src/config | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/config b/src/config index 3eedb40cf0..db74441b1c 160000 --- a/src/config +++ b/src/config @@ -1 +1 @@ -Subproject commit 3eedb40cf07dc40c246cd0416d04464aeb7c73c6 +Subproject commit db74441b1cb1ed96c63aee1288516c876250495e From 28848d1324fbcb773ab043dbf9479ca318860509 Mon Sep 17 00:00:00 2001 From: "Git bot (blckmn)" Date: Wed, 26 Mar 2025 06:25:03 +0000 Subject: [PATCH 146/244] Auto updated submodule references [26-03-2025] --- src/config | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/config b/src/config index db74441b1c..48588b79d3 160000 --- a/src/config +++ b/src/config @@ -1 +1 @@ -Subproject commit db74441b1cb1ed96c63aee1288516c876250495e +Subproject commit 48588b79d31428620af4d0629c57cc1894dd3542 From ad58b69c20f9f2d304a75ff0871526f3f6b848cc Mon Sep 17 00:00:00 2001 From: ke deng Date: Thu, 27 Mar 2025 05:20:53 +0800 Subject: [PATCH 147/244] Add NULL check for vTable->decodeTelemetry (#14321) --- src/main/drivers/motor.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/main/drivers/motor.c b/src/main/drivers/motor.c index 9060316a62..2fa45124cb 100644 --- a/src/main/drivers/motor.c +++ b/src/main/drivers/motor.c @@ -109,7 +109,9 @@ void motorWriteAll(float *values) // Perform the decode of the last data received // New data will be received once the send of motor data, triggered above, completes #if defined(USE_DSHOT) && defined(USE_DSHOT_TELEMETRY) - motorDevice.vTable->decodeTelemetry(); + if (motorDevice.vTable->decodeTelemetry) { + motorDevice.vTable->decodeTelemetry(); + } #endif // Update the motor data From 06844745f63f48cb9074d2173f8290ff206ee75c Mon Sep 17 00:00:00 2001 From: AJ Date: Wed, 26 Mar 2025 22:25:24 +0100 Subject: [PATCH 148/244] fix: missing sitl motor count (#14319) - other platforms set it, sitl does not and configurator complains --- src/platform/SIMULATOR/sitl.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/src/platform/SIMULATOR/sitl.c b/src/platform/SIMULATOR/sitl.c index 862d2835fd..2fc992cb45 100644 --- a/src/platform/SIMULATOR/sitl.c +++ b/src/platform/SIMULATOR/sitl.c @@ -644,14 +644,16 @@ bool motorPwmDevInit(motorDevice_t *device, const motorDevConfig_t *motorConfig, if (!device) { return false; } + + pwmMotorCount = device->count; device->vTable = &vTable; - const uint8_t motorCount = device->count; - printf("Initialized motor count %d\n", motorCount); - pwmRawPkt.motorCount = motorCount; + + printf("Initialized motor count %d\n", pwmMotorCount); + pwmRawPkt.motorCount = pwmMotorCount; idlePulse = _idlePulse; - for (int motorIndex = 0; motorIndex < MAX_SUPPORTED_MOTORS && motorIndex < motorCount; motorIndex++) { + for (int motorIndex = 0; motorIndex < MAX_SUPPORTED_MOTORS && motorIndex < pwmMotorCount; motorIndex++) { pwmMotors[motorIndex].enabled = true; } From 268952eeb54573b9ccf6c86ef2edc58a7255d068 Mon Sep 17 00:00:00 2001 From: Jay Blackman Date: Fri, 28 Mar 2025 21:31:30 +1100 Subject: [PATCH 149/244] Adding simplified timer calls for enabling ESC Serial and Soft Serial for AT32 (#14228) --- src/main/drivers/rx/expresslrs_driver.c | 55 ++++----------------- src/main/drivers/serial_escserial.c | 33 ++++--------- src/main/drivers/serial_softserial.c | 6 +-- src/main/drivers/timer.h | 9 ++++ src/platform/APM32/timer_apm32.c | 42 +++++++++++++++- src/platform/AT32/target/AT32F435G/target.h | 1 + src/platform/AT32/target/AT32F435M/target.h | 1 + src/platform/AT32/timer_at32bsp.c | 46 +++++++++++++++++ src/platform/STM32/timer_hal.c | 39 +++++++++++++++ src/platform/STM32/timer_stdperiph.c | 39 +++++++++++++++ 10 files changed, 195 insertions(+), 76 deletions(-) diff --git a/src/main/drivers/rx/expresslrs_driver.c b/src/main/drivers/rx/expresslrs_driver.c index 610c7ea286..e61d8bd033 100644 --- a/src/main/drivers/rx/expresslrs_driver.c +++ b/src/main/drivers/rx/expresslrs_driver.c @@ -101,13 +101,8 @@ void expressLrsUpdateTimerInterval(uint16_t intervalUs) timerState.intervalUs = intervalUs; expressLrsRecalculatePhaseShiftLimits(); -#ifdef USE_HAL_DRIVER timerReconfigureTimeBase(timer, expressLrsCalculateMaximumExpectedPeriod(timerState.intervalUs), MHZ_TO_HZ(1)); - LL_TIM_SetAutoReload(timer, (timerState.intervalUs / TICK_TOCK_COUNT) - 1); -#else - configTimeBase(timer, expressLrsCalculateMaximumExpectedPeriod(timerState.intervalUs), MHZ_TO_HZ(1)); - TIM_SetAutoreload(timer, (timerState.intervalUs / TICK_TOCK_COUNT) - 1); -#endif + timerSetPeriod(timer, (timerState.intervalUs / TICK_TOCK_COUNT) - 1); } void expressLrsUpdatePhaseShift(int32_t newPhaseShift) @@ -140,11 +135,7 @@ static void expressLrsOnTimerUpdate(timerOvrHandlerRec_t *cbRec, captureCompare_ uint32_t adjustedPeriod = (timerState.intervalUs / TICK_TOCK_COUNT) + timerState.frequencyOffsetTicks; -#ifdef USE_HAL_DRIVER - LL_TIM_SetAutoReload(timer, adjustedPeriod - 1); -#else - TIM_SetAutoreload(timer, adjustedPeriod - 1); -#endif + timerSetPeriod(timer, adjustedPeriod - 1); expressLrsOnTimerTickISR(); @@ -154,11 +145,7 @@ static void expressLrsOnTimerUpdate(timerOvrHandlerRec_t *cbRec, captureCompare_ uint32_t adjustedPeriod = (timerState.intervalUs / TICK_TOCK_COUNT) + timerState.phaseShiftUs + timerState.frequencyOffsetTicks; -#ifdef USE_HAL_DRIVER - LL_TIM_SetAutoReload(timer, adjustedPeriod - 1); -#else - TIM_SetAutoreload(timer, adjustedPeriod - 1); -#endif + timerSetPeriod(timer, adjustedPeriod - 1); timerState.phaseShiftUs = 0; @@ -175,15 +162,8 @@ bool expressLrsTimerIsRunning(void) void expressLrsTimerStop(void) { -#ifdef USE_HAL_DRIVER - LL_TIM_DisableIT_UPDATE(timer); - LL_TIM_DisableCounter(timer); - LL_TIM_SetCounter(timer, 0); -#else - TIM_ITConfig(timer, TIM_IT_Update, DISABLE); - TIM_Cmd(timer, DISABLE); - TIM_SetCounter(timer, 0); -#endif + timerDisable(timer); + timerSetCounter(timer, 0); timerState.running = false; } @@ -191,29 +171,12 @@ void expressLrsTimerResume(void) { timerState.tickTock = TOCK; -#ifdef USE_HAL_DRIVER - LL_TIM_SetAutoReload(timer, (timerState.intervalUs / TICK_TOCK_COUNT)); - LL_TIM_SetCounter(timer, 0); - - LL_TIM_ClearFlag_UPDATE(timer); - LL_TIM_EnableIT_UPDATE(timer); -#else - TIM_SetAutoreload(timer, (timerState.intervalUs / TICK_TOCK_COUNT)); - TIM_SetCounter(timer, 0); - - TIM_ClearFlag(timer, TIM_FLAG_Update); - TIM_ITConfig(timer, TIM_IT_Update, ENABLE); -#endif + timerSetPeriod(timer, (timerState.intervalUs / TICK_TOCK_COUNT)); + timerSetCounter(timer, 0); + timerEnableInterrupt(timer); timerState.running = true; - -#ifdef USE_HAL_DRIVER - LL_TIM_EnableCounter(timer); - LL_TIM_GenerateEvent_UPDATE(timer); -#else - TIM_Cmd(timer, ENABLE); - TIM_GenerateEvent(timer, TIM_EventSource_Update); -#endif + timerEnable(timer); } void expressLrsInitialiseTimer(TIM_TypeDef *t, timerOvrHandlerRec_t *timerUpdateCb) diff --git a/src/main/drivers/serial_escserial.c b/src/main/drivers/serial_escserial.c index b0d7424a1b..6067dfde22 100644 --- a/src/main/drivers/serial_escserial.c +++ b/src/main/drivers/serial_escserial.c @@ -134,13 +134,6 @@ enum { #define STOP_BIT_MASK (1 << 0) #define START_BIT_MASK (1 << (RX_TOTAL_BITS - 1)) -#ifdef USE_HAL_DRIVER -static void TIM_DeInit(TIM_TypeDef *tim) -{ - LL_TIM_DeInit(tim); -} -#endif - static void setTxSignalEsc(escSerial_t *escSerial, uint8_t state) { if (escSerial->mode == PROTOCOL_KISSALL) @@ -343,7 +336,7 @@ static void serialTimerTxConfigBL(const timerHardware_t *timerHardwarePtr, uint8 { uint32_t clock = SystemCoreClock/2; uint32_t timerPeriod; - TIM_DeInit(timerHardwarePtr->tim); + timerReset(timerHardwarePtr->tim); do { timerPeriod = clock / baud; if (isTimerPeriodTooLarge(timerPeriod)) { @@ -377,11 +370,8 @@ static void onSerialRxPinChangeBL(timerCCHandlerRec_t *cbRec, captureCompare_t c // Adjust the timing so it will interrupt on the middle. // This is clobbers transmission, but it is okay because we are // always half-duplex. -#ifdef USE_HAL_DRIVER - __HAL_TIM_SetCounter(escSerial->txTimerHandle, __HAL_TIM_GetAutoreload(escSerial->txTimerHandle) / 2); -#else - TIM_SetCounter(escSerial->txTimerHardware->tim, escSerial->txTimerHardware->tim->ARR / 2); -#endif + timerSetCounter(escSerial->txTimerHardware->tim, timerGetPeriod(escSerial->txTimerHardware->tim) / 2); + if (escSerial->isTransmittingData) { escSerial->transmissionErrors++; } @@ -414,7 +404,7 @@ static void onSerialRxPinChangeBL(timerCCHandlerRec_t *cbRec, captureCompare_t c static void serialTimerRxConfigBL(const timerHardware_t *timerHardwarePtr, uint8_t reference, portOptions_e options) { // start bit is usually a FALLING signal - TIM_DeInit(timerHardwarePtr->tim); + timerReset(timerHardwarePtr->tim); timerReconfigureTimeBase(timerHardwarePtr->tim, 0xFFFF, SystemCoreClock / 2); timerChConfigIC(timerHardwarePtr, (options & SERIAL_INVERTED) ? ICPOLARITY_RISING : ICPOLARITY_FALLING, 0); timerChCCHandlerInit(&escSerialPorts[reference].edgeCb, onSerialRxPinChangeBL); @@ -538,7 +528,7 @@ static void onSerialTimerEsc(timerCCHandlerRec_t *cbRec, captureCompare_t captur static void escSerialTimerTxConfig(const timerHardware_t *timerHardwarePtr, uint8_t reference) { uint32_t timerPeriod = 34; - TIM_DeInit(timerHardwarePtr->tim); + timerReset(timerHardwarePtr->tim); timerReconfigureTimeBase(timerHardwarePtr->tim, timerPeriod, MHZ_TO_HZ(1)); timerChCCHandlerInit(&escSerialPorts[reference].timerCb, onSerialTimerEsc); timerChConfigCallbacks(timerHardwarePtr, &escSerialPorts[reference].timerCb, NULL); @@ -570,12 +560,7 @@ static void onSerialRxPinChangeEsc(timerCCHandlerRec_t *cbRec, captureCompare_t escSerial_t *escSerial = container_of(cbRec, escSerial_t, edgeCb); - //clear timer -#ifdef USE_HAL_DRIVER - __HAL_TIM_SetCounter(escSerial->rxTimerHandle, 0); -#else - TIM_SetCounter(escSerial->rxTimerHardware->tim,0); -#endif + timerSetCounter(escSerial->rxTimerHardware->tim, 0); if (capture > 40 && capture < 90) { @@ -628,7 +613,7 @@ static void onSerialRxPinChangeEsc(timerCCHandlerRec_t *cbRec, captureCompare_t static void escSerialTimerRxConfig(const timerHardware_t *timerHardwarePtr, uint8_t reference) { // start bit is usually a FALLING signal - TIM_DeInit(timerHardwarePtr->tim); + timerReset(timerHardwarePtr->tim); timerReconfigureTimeBase(timerHardwarePtr->tim, 0xFFFF, MHZ_TO_HZ(1)); timerChConfigIC(timerHardwarePtr, ICPOLARITY_FALLING, 0); timerChCCHandlerInit(&escSerialPorts[reference].edgeCb, onSerialRxPinChangeEsc); @@ -786,11 +771,11 @@ static void closeEscSerial(escSerialPortIndex_e portIndex, uint8_t mode) if (mode != PROTOCOL_KISSALL) { escSerialInputPortDeConfig(escSerial->rxTimerHardware); timerChConfigCallbacks(escSerial->rxTimerHardware,NULL,NULL); - TIM_DeInit(escSerial->rxTimerHardware->tim); + timerReset(escSerial->rxTimerHardware->tim); } timerChConfigCallbacks(escSerial->txTimerHardware,NULL,NULL); - TIM_DeInit(escSerial->txTimerHardware->tim); + timerReset(escSerial->txTimerHardware->tim); } static uint32_t escSerialTotalBytesWaiting(const serialPort_t *instance) diff --git a/src/main/drivers/serial_softserial.c b/src/main/drivers/serial_softserial.c index 13fe8bb682..0f69dee869 100644 --- a/src/main/drivers/serial_softserial.c +++ b/src/main/drivers/serial_softserial.c @@ -487,11 +487,7 @@ void onSerialRxPinChange(timerCCHandlerRec_t *cbRec, captureCompare_t capture) // Synchronize the bit timing so that it will interrupt at the center // of the bit period. -#ifdef USE_HAL_DRIVER - __HAL_TIM_SetCounter(self->timerHandle, __HAL_TIM_GetAutoreload(self->timerHandle) / 2); -#else - TIM_SetCounter(self->timerHardware->tim, self->timerHardware->tim->ARR / 2); -#endif + timerSetCounter(self->timerHardware->tim, timerGetPeriod(self->timerHardware->tim) / 2); // For a mono-timer full duplex configuration, this may clobber the // transmission because the next callback to the onSerialTimerOverflow diff --git a/src/main/drivers/timer.h b/src/main/drivers/timer.h index 28ed1872b3..40bae0689c 100644 --- a/src/main/drivers/timer.h +++ b/src/main/drivers/timer.h @@ -216,3 +216,12 @@ uint16_t timerGetPeriodByPrescaler(TIM_TypeDef *tim, uint16_t prescaler, uint32_ int8_t timerGetNumberByIndex(uint8_t index); int8_t timerGetTIMNumber(const TIM_TypeDef *tim); uint8_t timerLookupChannelIndex(const uint16_t channel); + +// TODO: replace TIM_TypeDef with alternate +void timerReset(TIM_TypeDef *timer); +void timerSetPeriod(TIM_TypeDef *timer, uint32_t period); +uint32_t timerGetPeriod(TIM_TypeDef *timer); +void timerSetCounter(TIM_TypeDef *timer, uint32_t counter); +void timerDisable(TIM_TypeDef *timer); +void timerEnable(TIM_TypeDef *timer); +void timerEnableInterrupt(TIM_TypeDef *timer); diff --git a/src/platform/APM32/timer_apm32.c b/src/platform/APM32/timer_apm32.c index b113bc5f07..12ef8f197b 100644 --- a/src/platform/APM32/timer_apm32.c +++ b/src/platform/APM32/timer_apm32.c @@ -330,8 +330,9 @@ static void timerNVICConfigure(uint8_t irq) TMR_HandleTypeDef* timerFindTimerHandle(TMR_TypeDef *tim) { uint8_t timerIndex = lookupTimerIndex(tim); - if (timerIndex >= USED_TIMER_COUNT) + if (timerIndex >= USED_TIMER_COUNT) { return NULL; + } return &timerHandle[timerIndex].Handle; } @@ -1196,4 +1197,43 @@ DAL_StatusTypeDef DMA_SetCurrDataCounter(TMR_HandleTypeDef *htim, uint32_t Chann /* Return function status */ return DAL_OK; } + +void timerReset(TIM_TypeDef *timer) +{ + DDL_TMR_DeInit(timer); +} + +void timerSetPeriod(TIM_TypeDef *timer, uint32_t period) +{ + timer->AUTORLD = period; +} + +uint32_t timerGetPeriod(TIM_TypeDef *timer) +{ + return timer->AUTORLD; +} + +void timerSetCounter(TIM_TypeDef *timer, uint32_t counter) +{ + timer->CNT = counter; +} + +void timerDisable(TIM_TypeDef *timer) +{ + DDL_TMR_DisableIT_UPDATE(timer); + DDL_TMR_DisableCounter(timer); +} + +void timerEnable(TIM_TypeDef *timer) +{ + DDL_TMR_EnableCounter(timer); + DDL_TMR_GenerateEvent_UPDATE(timer); +} + +void timerEnableInterrupt(TIM_TypeDef *timer) +{ + DDL_TMR_ClearFlag_UPDATE(timer); + DDL_TMR_EnableIT_UPDATE(timer); +} + #endif diff --git a/src/platform/AT32/target/AT32F435G/target.h b/src/platform/AT32/target/AT32F435G/target.h index b76a523cd4..e9dbcebed6 100644 --- a/src/platform/AT32/target/AT32F435G/target.h +++ b/src/platform/AT32/target/AT32F435G/target.h @@ -97,5 +97,6 @@ #undef USE_RX_EXPRESSLRS // #undef USE_SERIAL_4WAY_BLHELI_BOOTLOADER #undef USE_SERIAL_4WAY_SK_BOOTLOADER +#define USE_ESCSERIAL #define FLASH_PAGE_SIZE ((uint32_t)0x0800) // 2K sectors diff --git a/src/platform/AT32/target/AT32F435M/target.h b/src/platform/AT32/target/AT32F435M/target.h index fb52e7fcea..3ee3ca1928 100644 --- a/src/platform/AT32/target/AT32F435M/target.h +++ b/src/platform/AT32/target/AT32F435M/target.h @@ -97,5 +97,6 @@ #undef USE_RX_EXPRESSLRS // #undef USE_SERIAL_4WAY_BLHELI_BOOTLOADER #undef USE_SERIAL_4WAY_SK_BOOTLOADER +#define USE_ESCSERIAL #define FLASH_PAGE_SIZE ((uint32_t)0x1000) // 4K sectors diff --git a/src/platform/AT32/timer_at32bsp.c b/src/platform/AT32/timer_at32bsp.c index f76a417152..6336ad1a2a 100644 --- a/src/platform/AT32/timer_at32bsp.c +++ b/src/platform/AT32/timer_at32bsp.c @@ -777,4 +777,50 @@ uint16_t timerGetPrescalerByDesiredHertz(tmr_type *tim, uint32_t hz) } return (uint16_t)((timerClock(tim) + hz / 2 ) / hz) - 1; } + +void timerReset(tmr_type *timer) +{ + ATOMIC_BLOCK(NVIC_PRIO_TIMER) { + tmr_counter_enable(timer, FALSE); + } +} + +void timerSetPeriod(tmr_type *timer, uint32_t period) +{ + tmr_period_value_set(timer, period); +} + +uint32_t timerGetPeriod(tmr_type *timer) +{ + return tmr_period_value_get(timer); +} + +void timerSetCounter(tmr_type *timer, uint32_t counter) +{ + tmr_counter_value_set(timer, counter); +} + +void timerReconfigureTimeBase(tmr_type *timer, uint16_t period, uint32_t hz) +{ + configTimeBase(timer, period, hz); +} + +void timerDisable(TIM_TypeDef *timer) +{ + tmr_interrupt_enable(timer, TMR_OVF_INT, FALSE); + tmr_counter_enable(timer, FALSE); +} + +void timerEnable(TIM_TypeDef *timer) +{ + tmr_counter_enable(timer, TRUE); + tmr_overflow_event_disable(timer, TRUE); +} + +void timerEnableInterrupt(TIM_TypeDef *timer) +{ + tmr_flag_clear(timer, TMR_OVF_FLAG); + tmr_interrupt_enable(timer, TMR_OVF_INT, TRUE); +} + #endif diff --git a/src/platform/STM32/timer_hal.c b/src/platform/STM32/timer_hal.c index 9f68624eca..c9e9180f6c 100644 --- a/src/platform/STM32/timer_hal.c +++ b/src/platform/STM32/timer_hal.c @@ -1251,4 +1251,43 @@ HAL_StatusTypeDef DMA_SetCurrDataCounter(TIM_HandleTypeDef *htim, uint32_t Chann /* Return function status */ return HAL_OK; } + +void timerReset(TIM_TypeDef *timer) +{ + LL_TIM_DeInit(timer); +} + +void timerSetPeriod(TIM_TypeDef *timer, uint32_t period) +{ + timer->ARR = period; +} + +uint32_t timerGetPeriod(TIM_TypeDef *timer) +{ + return timer->ARR; +} + +void timerSetCounter(TIM_TypeDef *timer, uint32_t counter) +{ + timer->CNT = counter; +} + +void timerDisable(TIM_TypeDef *timer) +{ + LL_TIM_DisableIT_UPDATE(timer); + LL_TIM_DisableCounter(timer); +} + +void timerEnable(TIM_TypeDef *timer) +{ + LL_TIM_EnableCounter(timer); + LL_TIM_GenerateEvent_UPDATE(timer); +} + +void timerEnableInterrupt(TIM_TypeDef *timer) +{ + LL_TIM_ClearFlag_UPDATE(timer); + LL_TIM_EnableIT_UPDATE(timer); +} + #endif diff --git a/src/platform/STM32/timer_stdperiph.c b/src/platform/STM32/timer_stdperiph.c index f12fd5547b..8e0c2bc95a 100644 --- a/src/platform/STM32/timer_stdperiph.c +++ b/src/platform/STM32/timer_stdperiph.c @@ -954,4 +954,43 @@ uint16_t timerGetPrescalerByDesiredHertz(TIM_TypeDef *tim, uint32_t hz) } return (uint16_t)((timerClock(tim) + hz / 2 ) / hz) - 1; } + +void timerReset(TIM_TypeDef *timer) +{ + TIM_DeInit(timer); +} + +void timerSetPeriod(TIM_TypeDef *timer, uint32_t period) +{ + timer->ARR = period; +} + +uint32_t timerGetPeriod(TIM_TypeDef *timer) +{ + return timer->ARR; +} + +void timerSetCounter(TIM_TypeDef *timer, uint32_t counter) +{ + timer->CNT = counter; +} + +void timerDisable(TIM_TypeDef *timer) +{ + TIM_ITConfig(timer, TIM_IT_Update, DISABLE); + TIM_Cmd(timer, DISABLE); +} + +void timerEnable(TIM_TypeDef *timer) +{ + TIM_Cmd(timer, ENABLE); + TIM_GenerateEvent(timer, TIM_EventSource_Update); +} + +void timerEnableInterrupt(TIM_TypeDef *timer) +{ + TIM_ClearFlag(timer, TIM_FLAG_Update); + TIM_ITConfig(timer, TIM_IT_Update, ENABLE); +} + #endif From 107bab5ed3dfb1a35a9e99e9f5a430b6182d5727 Mon Sep 17 00:00:00 2001 From: "Git bot (blckmn)" Date: Tue, 1 Apr 2025 06:25:03 +0000 Subject: [PATCH 150/244] Auto updated submodule references [01-04-2025] --- src/config | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/config b/src/config index 48588b79d3..b606002103 160000 --- a/src/config +++ b/src/config @@ -1 +1 @@ -Subproject commit 48588b79d31428620af4d0629c57cc1894dd3542 +Subproject commit b60600210384d1da4621cc35a0632d9cca8a62b7 From 1d3c661c06e2dd88d6a508ccc1e693dabe33ee76 Mon Sep 17 00:00:00 2001 From: Jay Blackman Date: Tue, 1 Apr 2025 22:17:25 +1100 Subject: [PATCH 151/244] REFACTOR: Moving platform specific DMA code to include/platform (#14320) * REFACTOR: Moving platform specific DMA code to include/platform * Cleanup --- src/main/drivers/dma.h | 239 +----------------- .../{dma_apm32.h => include/platform/dma.h} | 20 ++ src/platform/APM32/mk/APM32F4.mk | 3 +- .../{dma_atbsp.h => include/platform/dma.h} | 9 + src/platform/AT32/mk/AT32F4.mk | 3 +- src/platform/SIMULATOR/include/platform/dma.h | 27 ++ src/platform/SIMULATOR/mk/SITL.mk | 1 + src/platform/STM32/include/platform/dma.h | 238 +++++++++++++++++ src/platform/STM32/mk/STM32F4.mk | 2 + src/platform/STM32/mk/STM32F7.mk | 1 + src/platform/STM32/mk/STM32G4.mk | 1 + src/platform/STM32/mk/STM32H5.mk | 1 + src/platform/STM32/mk/STM32H7.mk | 1 + src/test/unit/platform/dma.h | 27 ++ 14 files changed, 335 insertions(+), 238 deletions(-) rename src/platform/APM32/{dma_apm32.h => include/platform/dma.h} (78%) rename src/platform/AT32/{dma_atbsp.h => include/platform/dma.h} (94%) create mode 100644 src/platform/SIMULATOR/include/platform/dma.h create mode 100644 src/platform/STM32/include/platform/dma.h create mode 100644 src/test/unit/platform/dma.h diff --git a/src/main/drivers/dma.h b/src/main/drivers/dma.h index ec93c09a78..39ce91552c 100644 --- a/src/main/drivers/dma.h +++ b/src/main/drivers/dma.h @@ -22,13 +22,7 @@ #include "drivers/resource.h" -#if defined(USE_ATBSP_DRIVER) -#include "dma_atbsp.h" -#endif - -#if defined(APM32F4) -#include "dma_apm32.h" -#endif +#include "platform/dma.h" #define CACHE_LINE_SIZE 32 #define CACHE_LINE_MASK (CACHE_LINE_SIZE - 1) @@ -42,26 +36,13 @@ typedef struct dmaResource_s dmaResource_t; -#if defined(STM32F4) || defined(STM32F7) -#define DMA_ARCH_TYPE DMA_Stream_TypeDef -#elif defined(STM32H7) -// H7 has stream based DMA and channel based BDMA, but we ignore BDMA (for now). -#define DMA_ARCH_TYPE DMA_Stream_TypeDef -#elif defined(AT32F435) -#define DMA_ARCH_TYPE dma_channel_type -#elif defined(APM32F4) -#define DMA_ARCH_TYPE DMA_Stream_TypeDef -#else -#define DMA_ARCH_TYPE DMA_Channel_TypeDef -#endif - struct dmaChannelDescriptor_s; typedef void (*dmaCallbackHandlerFuncPtr)(struct dmaChannelDescriptor_s *channelDescriptor); typedef struct dmaChannelDescriptor_s { DMA_TypeDef* dma; dmaResource_t *ref; -#if defined(STM32F4) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) || defined(APM32F4) +#if PLATFORM_TRAIT_DMA_STREAM_REQUIRED uint8_t stream; #endif uint32_t channel; @@ -72,198 +53,15 @@ typedef struct dmaChannelDescriptor_s { resourceOwner_t owner; uint8_t resourceIndex; uint32_t completeFlag; -#if defined(USE_ATBSP_DRIVER) +#if PLATFORM_TRAIT_DMA_MUX_REQUIRED dmamux_channel_type *dmamux; #endif } dmaChannelDescriptor_t; #define DMA_IDENTIFIER_TO_INDEX(x) ((x) - 1) -#if defined(USE_ATBSP_DRIVER) - -#elif defined(APM32F4) -// dma_apm32.h - -#elif defined(STM32F4) || defined(STM32F7) || defined(STM32H7) - -typedef enum { - DMA_NONE = 0, - DMA1_ST0_HANDLER = 1, - DMA1_ST1_HANDLER, - DMA1_ST2_HANDLER, - DMA1_ST3_HANDLER, - DMA1_ST4_HANDLER, - DMA1_ST5_HANDLER, - DMA1_ST6_HANDLER, - DMA1_ST7_HANDLER, - DMA2_ST0_HANDLER, - DMA2_ST1_HANDLER, - DMA2_ST2_HANDLER, - DMA2_ST3_HANDLER, - DMA2_ST4_HANDLER, - DMA2_ST5_HANDLER, - DMA2_ST6_HANDLER, - DMA2_ST7_HANDLER, - DMA_LAST_HANDLER = DMA2_ST7_HANDLER -} dmaIdentifier_e; - -#define DMA_DEVICE_NO(x) ((((x)-1) / 8) + 1) -#define DMA_DEVICE_INDEX(x) ((((x)-1) % 8)) -#define DMA_OUTPUT_INDEX 0 -#define DMA_OUTPUT_STRING "DMA%d Stream %d:" -#define DMA_INPUT_STRING "DMA%d_ST%d" - -#define DEFINE_DMA_CHANNEL(d, s, f) { \ - .dma = d, \ - .ref = (dmaResource_t *)d ## _Stream ## s, \ - .stream = s, \ - .irqHandlerCallback = NULL, \ - .flagsShift = f, \ - .irqN = d ## _Stream ## s ## _IRQn, \ - .userParam = 0, \ - .owner.owner = 0, \ - .owner.resourceIndex = 0 \ - } - -#define DEFINE_DMA_IRQ_HANDLER(d, s, i) FAST_IRQ_HANDLER void DMA ## d ## _Stream ## s ## _IRQHandler(void) {\ - const uint8_t index = DMA_IDENTIFIER_TO_INDEX(i); \ - dmaCallbackHandlerFuncPtr handler = dmaDescriptors[index].irqHandlerCallback; \ - if (handler) \ - handler(&dmaDescriptors[index]); \ - } - -#define DMA_CLEAR_FLAG(d, flag) if (d->flagsShift > 31) d->dma->HIFCR = (flag << (d->flagsShift - 32)); else d->dma->LIFCR = (flag << d->flagsShift) -#define DMA_GET_FLAG_STATUS(d, flag) (d->flagsShift > 31 ? d->dma->HISR & (flag << (d->flagsShift - 32)): d->dma->LISR & (flag << d->flagsShift)) - -#define DMA_IT_TCIF ((uint32_t)0x00000020) -#define DMA_IT_HTIF ((uint32_t)0x00000010) -#define DMA_IT_TEIF ((uint32_t)0x00000008) -#define DMA_IT_DMEIF ((uint32_t)0x00000004) -#define DMA_IT_FEIF ((uint32_t)0x00000001) - void dmaMuxEnable(dmaIdentifier_e identifier, uint32_t dmaMuxId); -#else - -#if defined(STM32G4) - -typedef enum { - DMA_NONE = 0, - DMA1_CH1_HANDLER = 1, - DMA1_CH2_HANDLER, - DMA1_CH3_HANDLER, - DMA1_CH4_HANDLER, - DMA1_CH5_HANDLER, - DMA1_CH6_HANDLER, - DMA1_CH7_HANDLER, - DMA1_CH8_HANDLER, - DMA2_CH1_HANDLER, - DMA2_CH2_HANDLER, - DMA2_CH3_HANDLER, - DMA2_CH4_HANDLER, - DMA2_CH5_HANDLER, - DMA2_CH6_HANDLER, - DMA2_CH7_HANDLER, - DMA2_CH8_HANDLER, - DMA_LAST_HANDLER = DMA2_CH8_HANDLER -} dmaIdentifier_e; - -#define DMA_DEVICE_NO(x) ((((x)-1) / 8) + 1) -#define DMA_DEVICE_INDEX(x) ((((x)-1) % 8) + 1) - -uint32_t dmaGetChannel(const uint8_t channel); - -#else // !STM32G4 - -typedef enum { - DMA_NONE = 0, - DMA1_CH1_HANDLER = 1, - DMA1_CH2_HANDLER, - DMA1_CH3_HANDLER, - DMA1_CH4_HANDLER, - DMA1_CH5_HANDLER, - DMA1_CH6_HANDLER, - DMA1_CH7_HANDLER, - DMA_LAST_HANDLER = DMA1_CH7_HANDLER -} dmaIdentifier_e; - -#define DMA_DEVICE_NO(x) ((((x)-1) / 7) + 1) -#define DMA_DEVICE_INDEX(x) ((((x)-1) % 7) + 1) - -#endif // STM32G4 - -#define DMA_OUTPUT_INDEX 0 -#define DMA_OUTPUT_STRING "DMA%d Channel %d:" -#define DMA_INPUT_STRING "DMA%d_CH%d" - -#define DEFINE_DMA_CHANNEL(d, c, f) { \ - .dma = d, \ - .ref = (dmaResource_t *)d ## _Channel ## c, \ - .irqHandlerCallback = NULL, \ - .flagsShift = f, \ - .irqN = d ## _Channel ## c ## _IRQn, \ - .userParam = 0, \ - .owner.owner = 0, \ - .owner.resourceIndex = 0 \ - } - -#define DMA_HANDLER_CODE - -#define DEFINE_DMA_IRQ_HANDLER(d, c, i) DMA_HANDLER_CODE void DMA ## d ## _Channel ## c ## _IRQHandler(void) {\ - const uint8_t index = DMA_IDENTIFIER_TO_INDEX(i); \ - dmaCallbackHandlerFuncPtr handler = dmaDescriptors[index].irqHandlerCallback; \ - if (handler) \ - handler(&dmaDescriptors[index]); \ - } - -#define DMA_CLEAR_FLAG(d, flag) d->dma->IFCR = (flag << d->flagsShift) -#define DMA_GET_FLAG_STATUS(d, flag) (d->dma->ISR & (flag << d->flagsShift)) - -#define DMA_IT_TCIF ((uint32_t)0x00000002) -#define DMA_IT_HTIF ((uint32_t)0x00000004) -#define DMA_IT_TEIF ((uint32_t)0x00000008) -#endif - -// Macros to avoid direct register and register bit access - -#if defined(STM32F4) || defined(STM32F7) -#define IS_DMA_ENABLED(reg) (((DMA_ARCH_TYPE *)(reg))->CR & DMA_SxCR_EN) -#define REG_NDTR NDTR -#elif defined(STM32H7) -// For H7, we have to differenciate DMA1/2 and BDMA for access to the control register. -// HAL library has a macro for this, but it is extremely inefficient in that it compares -// the address against all possible values. -// Here, we just compare the address against regions of memory. -#if defined(STM32H7A3xx) || defined(STM32H7A3xxQ) -// For H7A3, if it's lower than CD_AHB2PERIPH_BASE, then it's DMA1/2 and it's stream based. -// If not, it's BDMA and it's channel based. -#define IS_DMA_ENABLED(reg) \ - ((uint32_t)(reg) < CD_AHB2PERIPH_BASE) ? \ - (((DMA_Stream_TypeDef *)(reg))->CR & DMA_SxCR_EN) : \ - (((BDMA_Channel_TypeDef *)(reg))->CCR & BDMA_CCR_EN) -#else -// For H743 and H750, if it's not in D3 peripheral area, then it's DMA1/2 and it's stream based. -// If not, it's BDMA and it's channel based. -#define IS_DMA_ENABLED(reg) \ - ((uint32_t)(reg) < D3_AHB1PERIPH_BASE) ? \ - (((DMA_Stream_TypeDef *)(reg))->CR & DMA_SxCR_EN) : \ - (((BDMA_Channel_TypeDef *)(reg))->CCR & BDMA_CCR_EN) -#endif -#elif defined(STM32G4) -#define IS_DMA_ENABLED(reg) (((DMA_ARCH_TYPE *)(reg))->CCR & DMA_CCR_EN) -// Missing __HAL_DMA_SET_COUNTER in FW library V1.0.0 -#define __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNDTR = (uint16_t)(__COUNTER__)) -#elif defined(AT32F4) -#define DMA_CCR_EN 1 -#define IS_DMA_ENABLED(reg) (((DMA_ARCH_TYPE *)(reg))->ctrl_bit.chen & DMA_CCR_EN) -#elif defined(APM32F4) -#define IS_DMA_ENABLED(reg) (((DMA_ARCH_TYPE *)(reg))->SCFG & DMA_SCFGx_EN) -#define REG_NDTR NDATA -#else -#define IS_DMA_ENABLED(reg) (((DMA_ARCH_TYPE *)(reg))->CCR & DMA_CCR_EN) -#define DMAx_SetMemoryAddress(reg, address) ((DMA_ARCH_TYPE *)(reg))->CMAR = (uint32_t)&s->port.txBuffer[s->port.txBufferTail] -#endif - dmaIdentifier_e dmaAllocate(dmaIdentifier_e identifier, resourceOwner_e owner, uint8_t resourceIndex); void dmaEnable(dmaIdentifier_e identifier); void dmaSetHandler(dmaIdentifier_e identifier, dmaCallbackHandlerFuncPtr callback, uint32_t priority, uint32_t userParam); @@ -273,34 +71,3 @@ const resourceOwner_t *dmaGetOwner(dmaIdentifier_e identifier); dmaChannelDescriptor_t* dmaGetDescriptorByIdentifier(const dmaIdentifier_e identifier); uint32_t dmaGetChannel(const uint8_t channel); -// -// Wrapper macros to cast dmaResource_t back into DMA_ARCH_TYPE -// - -#if defined(USE_HAL_DRIVER) - -// We actually need these LL case only - -#define xLL_EX_DMA_DeInit(dmaResource) LL_EX_DMA_DeInit((DMA_ARCH_TYPE *)(dmaResource)) -#define xLL_EX_DMA_Init(dmaResource, initstruct) LL_EX_DMA_Init((DMA_ARCH_TYPE *)(dmaResource), initstruct) -#define xLL_EX_DMA_DisableResource(dmaResource) LL_EX_DMA_DisableResource((DMA_ARCH_TYPE *)(dmaResource)) -#define xLL_EX_DMA_EnableResource(dmaResource) LL_EX_DMA_EnableResource((DMA_ARCH_TYPE *)(dmaResource)) -#define xLL_EX_DMA_GetDataLength(dmaResource) LL_EX_DMA_GetDataLength((DMA_ARCH_TYPE *)(dmaResource)) -#define xLL_EX_DMA_SetDataLength(dmaResource, length) LL_EX_DMA_SetDataLength((DMA_ARCH_TYPE *)(dmaResource), length) -#define xLL_EX_DMA_EnableIT_TC(dmaResource) LL_EX_DMA_EnableIT_TC((DMA_ARCH_TYPE *)(dmaResource)) - -#elif defined(USE_ATBSP_DRIVER) - -#else - -#define xDMA_Init(dmaResource, initStruct) DMA_Init((DMA_ARCH_TYPE *)(dmaResource), initStruct) -#define xDMA_DeInit(dmaResource) DMA_DeInit((DMA_ARCH_TYPE *)(dmaResource)) -#define xDMA_Cmd(dmaResource, newState) DMA_Cmd((DMA_ARCH_TYPE *)(dmaResource), newState) -#define xDMA_ITConfig(dmaResource, flags, newState) DMA_ITConfig((DMA_ARCH_TYPE *)(dmaResource), flags, newState) -#define xDMA_GetCurrDataCounter(dmaResource) DMA_GetCurrDataCounter((DMA_ARCH_TYPE *)(dmaResource)) -#define xDMA_SetCurrDataCounter(dmaResource, count) DMA_SetCurrDataCounter((DMA_ARCH_TYPE *)(dmaResource), count) -#define xDMA_GetFlagStatus(dmaResource, flags) DMA_GetFlagStatus((DMA_ARCH_TYPE *)(dmaResource), flags) -#define xDMA_ClearFlag(dmaResource, flags) DMA_ClearFlag((DMA_ARCH_TYPE *)(dmaResource), flags) -#define xDMA_MemoryTargetConfig(dmaResource, address, target) DMA_MemoryTargetConfig((DMA_ARCH_TYPE *)(dmaResource), address, target) - -#endif diff --git a/src/platform/APM32/dma_apm32.h b/src/platform/APM32/include/platform/dma.h similarity index 78% rename from src/platform/APM32/dma_apm32.h rename to src/platform/APM32/include/platform/dma.h index a719782180..0b20062250 100644 --- a/src/platform/APM32/dma_apm32.h +++ b/src/platform/APM32/include/platform/dma.h @@ -24,6 +24,12 @@ #include "platform.h" #include "drivers/resource.h" +#if defined(APM32F4) +#define PLATFORM_TRAIT_DMA_STREAM_REQUIRED 1 +#endif + +#define DMA_ARCH_TYPE DMA_Stream_TypeDef + typedef enum { DMA_NONE = 0, DMA1_ST0_HANDLER = 1, @@ -88,3 +94,17 @@ typedef enum { #define DMA_IT_FEIF ((uint32_t)0x00000001) void dmaMuxEnable(dmaIdentifier_e identifier, uint32_t dmaMuxId); + +#define IS_DMA_ENABLED(reg) (((DMA_ARCH_TYPE *)(reg))->SCFG & DMA_SCFGx_EN) +#define REG_NDTR NDATA + +#if defined(USE_HAL_DRIVER) +// We actually need these LL case only +#define xLL_EX_DMA_DeInit(dmaResource) LL_EX_DMA_DeInit((DMA_ARCH_TYPE *)(dmaResource)) +#define xLL_EX_DMA_Init(dmaResource, initstruct) LL_EX_DMA_Init((DMA_ARCH_TYPE *)(dmaResource), initstruct) +#define xLL_EX_DMA_DisableResource(dmaResource) LL_EX_DMA_DisableResource((DMA_ARCH_TYPE *)(dmaResource)) +#define xLL_EX_DMA_EnableResource(dmaResource) LL_EX_DMA_EnableResource((DMA_ARCH_TYPE *)(dmaResource)) +#define xLL_EX_DMA_GetDataLength(dmaResource) LL_EX_DMA_GetDataLength((DMA_ARCH_TYPE *)(dmaResource)) +#define xLL_EX_DMA_SetDataLength(dmaResource, length) LL_EX_DMA_SetDataLength((DMA_ARCH_TYPE *)(dmaResource), length) +#define xLL_EX_DMA_EnableIT_TC(dmaResource) LL_EX_DMA_EnableIT_TC((DMA_ARCH_TYPE *)(dmaResource)) +#endif diff --git a/src/platform/APM32/mk/APM32F4.mk b/src/platform/APM32/mk/APM32F4.mk index b82d82cf56..c0b9a27c91 100644 --- a/src/platform/APM32/mk/APM32F4.mk +++ b/src/platform/APM32/mk/APM32F4.mk @@ -111,8 +111,9 @@ DEVICE_STDPERIPH_SRC := \ VPATH := $(VPATH):$(LIB_MAIN_DIR)/APM32F4/Libraries/Device/Geehy/APM32F4xx INCLUDE_DIRS += \ - $(TARGET_PLATFORM_DIR)/startup \ $(TARGET_PLATFORM_DIR) \ + $(TARGET_PLATFORM_DIR)/include \ + $(TARGET_PLATFORM_DIR)/startup \ $(PLATFORM_DIR)/common/stm32 \ $(STDPERIPH_DIR)/Include \ $(LIB_MAIN_DIR)/$(USBCORE_DIR)/Inc \ diff --git a/src/platform/AT32/dma_atbsp.h b/src/platform/AT32/include/platform/dma.h similarity index 94% rename from src/platform/AT32/dma_atbsp.h rename to src/platform/AT32/include/platform/dma.h index 1cf03115c1..adb08d3843 100644 --- a/src/platform/AT32/dma_atbsp.h +++ b/src/platform/AT32/include/platform/dma.h @@ -24,6 +24,12 @@ #include "platform.h" #include "drivers/resource.h" +#if defined(USE_ATBSP_DRIVER) +#define PLATFORM_TRAIT_DMA_MUX_REQUIRED 1 +#endif + +#define DMA_ARCH_TYPE dma_channel_type + typedef enum { DMA_NONE = 0, DMA1_CH1_HANDLER = 1, @@ -90,3 +96,6 @@ void dmaMuxEnable(dmaIdentifier_e identifier, uint32_t dmaMuxId); #define xDMA_SetCurrDataCounter(dmaResource, count) dma_data_number_set((DMA_ARCH_TYPE *)(dmaResource), count) #define xDMA_GetFlagStatus(dmaResource, flags) dma_flag_get((DMA_ARCH_TYPE *)(dmaResource), flags) #define xDMA_ClearFlag(dmaResource, flags) dma_flag_clear((DMA_ARCH_TYPE *)(dmaResource), flags) + +#define DMA_CCR_EN 1 +#define IS_DMA_ENABLED(reg) (((DMA_ARCH_TYPE *)(reg))->ctrl_bit.chen & DMA_CCR_EN) diff --git a/src/platform/AT32/mk/AT32F4.mk b/src/platform/AT32/mk/AT32F4.mk index 2a0149017e..ec377078aa 100644 --- a/src/platform/AT32/mk/AT32F4.mk +++ b/src/platform/AT32/mk/AT32F4.mk @@ -61,8 +61,9 @@ VCP_INCLUDES = \ DEVICE_STDPERIPH_SRC = $(STDPERIPH_SRC) INCLUDE_DIRS := $(INCLUDE_DIRS) \ - $(TARGET_PLATFORM_DIR)/startup \ $(TARGET_PLATFORM_DIR) \ + $(TARGET_PLATFORM_DIR)/include \ + $(TARGET_PLATFORM_DIR)/startup \ $(PLATFORM_DIR)/common/stm32 \ $(STDPERIPH_DIR)/inc \ $(CMSIS_DIR)/cm4/core_support \ diff --git a/src/platform/SIMULATOR/include/platform/dma.h b/src/platform/SIMULATOR/include/platform/dma.h new file mode 100644 index 0000000000..f199deeed6 --- /dev/null +++ b/src/platform/SIMULATOR/include/platform/dma.h @@ -0,0 +1,27 @@ +/* + * This file is part of Betaflight. + * + * Betaflight is free software. You can redistribute this software + * and/or modify this software under the terms of the GNU General + * Public License as published by the Free Software Foundation, + * either version 3 of the License, or (at your option) any later + * version. + * + * Betaflight is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * See the GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this software. + * + * If not, see . + */ + + #pragma once + + typedef enum { + DMA_NONE = 0, + DMA_LAST_HANDLER = DMA_NONE +} dmaIdentifier_e; diff --git a/src/platform/SIMULATOR/mk/SITL.mk b/src/platform/SIMULATOR/mk/SITL.mk index 6a2d8e8b9d..001255826e 100644 --- a/src/platform/SIMULATOR/mk/SITL.mk +++ b/src/platform/SIMULATOR/mk/SITL.mk @@ -2,6 +2,7 @@ INCLUDE_DIRS := \ $(INCLUDE_DIRS) \ $(TARGET_PLATFORM_DIR) \ + $(TARGET_PLATFORM_DIR)/include \ $(LIB_MAIN_DIR)/dyad MCU_COMMON_SRC := \ diff --git a/src/platform/STM32/include/platform/dma.h b/src/platform/STM32/include/platform/dma.h new file mode 100644 index 0000000000..fbd9f5f1cb --- /dev/null +++ b/src/platform/STM32/include/platform/dma.h @@ -0,0 +1,238 @@ +/* + * This file is part of Betaflight. + * + * Betaflight is free software. You can redistribute this software + * and/or modify this software under the terms of the GNU General + * Public License as published by the Free Software Foundation, + * either version 3 of the License, or (at your option) any later + * version. + * + * Betaflight is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * See the GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this software. + * + * If not, see . + */ + +#pragma once + +#include "platform.h" + +#if defined(STM32F4) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) || defined(APM32F4) +#define PLATFORM_TRAIT_DMA_STREAM_REQUIRED 1 +#endif + +#if defined(STM32F4) || defined(STM32F7) +#define DMA_ARCH_TYPE DMA_Stream_TypeDef +#elif defined(STM32H7) +// H7 has stream based DMA and channel based BDMA, but we ignore BDMA (for now). +#define DMA_ARCH_TYPE DMA_Stream_TypeDef +#else +#define DMA_ARCH_TYPE DMA_Channel_TypeDef +#endif + +#if defined(STM32F4) || defined(STM32F7) || defined(STM32H7) + +typedef enum { + DMA_NONE = 0, + DMA1_ST0_HANDLER = 1, + DMA1_ST1_HANDLER, + DMA1_ST2_HANDLER, + DMA1_ST3_HANDLER, + DMA1_ST4_HANDLER, + DMA1_ST5_HANDLER, + DMA1_ST6_HANDLER, + DMA1_ST7_HANDLER, + DMA2_ST0_HANDLER, + DMA2_ST1_HANDLER, + DMA2_ST2_HANDLER, + DMA2_ST3_HANDLER, + DMA2_ST4_HANDLER, + DMA2_ST5_HANDLER, + DMA2_ST6_HANDLER, + DMA2_ST7_HANDLER, + DMA_LAST_HANDLER = DMA2_ST7_HANDLER +} dmaIdentifier_e; + +#define DMA_DEVICE_NO(x) ((((x)-1) / 8) + 1) +#define DMA_DEVICE_INDEX(x) ((((x)-1) % 8)) +#define DMA_OUTPUT_INDEX 0 +#define DMA_OUTPUT_STRING "DMA%d Stream %d:" +#define DMA_INPUT_STRING "DMA%d_ST%d" + +#define DEFINE_DMA_CHANNEL(d, s, f) { \ + .dma = d, \ + .ref = (dmaResource_t *)d ## _Stream ## s, \ + .stream = s, \ + .irqHandlerCallback = NULL, \ + .flagsShift = f, \ + .irqN = d ## _Stream ## s ## _IRQn, \ + .userParam = 0, \ + .owner.owner = 0, \ + .owner.resourceIndex = 0 \ + } + +#define DEFINE_DMA_IRQ_HANDLER(d, s, i) FAST_IRQ_HANDLER void DMA ## d ## _Stream ## s ## _IRQHandler(void) {\ + const uint8_t index = DMA_IDENTIFIER_TO_INDEX(i); \ + dmaCallbackHandlerFuncPtr handler = dmaDescriptors[index].irqHandlerCallback; \ + if (handler) \ + handler(&dmaDescriptors[index]); \ + } + +#define DMA_CLEAR_FLAG(d, flag) if (d->flagsShift > 31) d->dma->HIFCR = (flag << (d->flagsShift - 32)); else d->dma->LIFCR = (flag << d->flagsShift) +#define DMA_GET_FLAG_STATUS(d, flag) (d->flagsShift > 31 ? d->dma->HISR & (flag << (d->flagsShift - 32)): d->dma->LISR & (flag << d->flagsShift)) + +#define DMA_IT_TCIF ((uint32_t)0x00000020) +#define DMA_IT_HTIF ((uint32_t)0x00000010) +#define DMA_IT_TEIF ((uint32_t)0x00000008) +#define DMA_IT_DMEIF ((uint32_t)0x00000004) +#define DMA_IT_FEIF ((uint32_t)0x00000001) + +void dmaMuxEnable(dmaIdentifier_e identifier, uint32_t dmaMuxId); + +#else + +#if defined(STM32G4) + +typedef enum { + DMA_NONE = 0, + DMA1_CH1_HANDLER = 1, + DMA1_CH2_HANDLER, + DMA1_CH3_HANDLER, + DMA1_CH4_HANDLER, + DMA1_CH5_HANDLER, + DMA1_CH6_HANDLER, + DMA1_CH7_HANDLER, + DMA1_CH8_HANDLER, + DMA2_CH1_HANDLER, + DMA2_CH2_HANDLER, + DMA2_CH3_HANDLER, + DMA2_CH4_HANDLER, + DMA2_CH5_HANDLER, + DMA2_CH6_HANDLER, + DMA2_CH7_HANDLER, + DMA2_CH8_HANDLER, + DMA_LAST_HANDLER = DMA2_CH8_HANDLER +} dmaIdentifier_e; + +#define DMA_DEVICE_NO(x) ((((x)-1) / 8) + 1) +#define DMA_DEVICE_INDEX(x) ((((x)-1) % 8) + 1) + +uint32_t dmaGetChannel(const uint8_t channel); + +#else // !STM32G4 + +typedef enum { + DMA_NONE = 0, + DMA1_CH1_HANDLER = 1, + DMA1_CH2_HANDLER, + DMA1_CH3_HANDLER, + DMA1_CH4_HANDLER, + DMA1_CH5_HANDLER, + DMA1_CH6_HANDLER, + DMA1_CH7_HANDLER, + DMA_LAST_HANDLER = DMA1_CH7_HANDLER +} dmaIdentifier_e; + +#define DMA_DEVICE_NO(x) ((((x)-1) / 7) + 1) +#define DMA_DEVICE_INDEX(x) ((((x)-1) % 7) + 1) + +#endif // STM32G4 + +#define DMA_OUTPUT_INDEX 0 +#define DMA_OUTPUT_STRING "DMA%d Channel %d:" +#define DMA_INPUT_STRING "DMA%d_CH%d" + +#define DEFINE_DMA_CHANNEL(d, c, f) { \ + .dma = d, \ + .ref = (dmaResource_t *)d ## _Channel ## c, \ + .irqHandlerCallback = NULL, \ + .flagsShift = f, \ + .irqN = d ## _Channel ## c ## _IRQn, \ + .userParam = 0, \ + .owner.owner = 0, \ + .owner.resourceIndex = 0 \ + } + +#define DMA_HANDLER_CODE + +#define DEFINE_DMA_IRQ_HANDLER(d, c, i) DMA_HANDLER_CODE void DMA ## d ## _Channel ## c ## _IRQHandler(void) {\ + const uint8_t index = DMA_IDENTIFIER_TO_INDEX(i); \ + dmaCallbackHandlerFuncPtr handler = dmaDescriptors[index].irqHandlerCallback; \ + if (handler) \ + handler(&dmaDescriptors[index]); \ + } + +#define DMA_CLEAR_FLAG(d, flag) d->dma->IFCR = (flag << d->flagsShift) +#define DMA_GET_FLAG_STATUS(d, flag) (d->dma->ISR & (flag << d->flagsShift)) + +#define DMA_IT_TCIF ((uint32_t)0x00000002) +#define DMA_IT_HTIF ((uint32_t)0x00000004) +#define DMA_IT_TEIF ((uint32_t)0x00000008) + +#endif + +// Macros to avoid direct register and register bit access + +#if defined(STM32F4) || defined(STM32F7) +#define IS_DMA_ENABLED(reg) (((DMA_ARCH_TYPE *)(reg))->CR & DMA_SxCR_EN) +#define REG_NDTR NDTR +#elif defined(STM32H7) +// For H7, we have to differenciate DMA1/2 and BDMA for access to the control register. +// HAL library has a macro for this, but it is extremely inefficient in that it compares +// the address against all possible values. +// Here, we just compare the address against regions of memory. +#if defined(STM32H7A3xx) || defined(STM32H7A3xxQ) +// For H7A3, if it's lower than CD_AHB2PERIPH_BASE, then it's DMA1/2 and it's stream based. +// If not, it's BDMA and it's channel based. +#define IS_DMA_ENABLED(reg) \ + ((uint32_t)(reg) < CD_AHB2PERIPH_BASE) ? \ + (((DMA_Stream_TypeDef *)(reg))->CR & DMA_SxCR_EN) : \ + (((BDMA_Channel_TypeDef *)(reg))->CCR & BDMA_CCR_EN) +#else +// For H743 and H750, if it's not in D3 peripheral area, then it's DMA1/2 and it's stream based. +// If not, it's BDMA and it's channel based. +#define IS_DMA_ENABLED(reg) \ + ((uint32_t)(reg) < D3_AHB1PERIPH_BASE) ? \ + (((DMA_Stream_TypeDef *)(reg))->CR & DMA_SxCR_EN) : \ + (((BDMA_Channel_TypeDef *)(reg))->CCR & BDMA_CCR_EN) +#endif +#elif defined(STM32G4) +#define IS_DMA_ENABLED(reg) (((DMA_ARCH_TYPE *)(reg))->CCR & DMA_CCR_EN) +// Missing __HAL_DMA_SET_COUNTER in FW library V1.0.0 +#define __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNDTR = (uint16_t)(__COUNTER__)) +#else +#define IS_DMA_ENABLED(reg) (((DMA_ARCH_TYPE *)(reg))->CCR & DMA_CCR_EN) +#define DMAx_SetMemoryAddress(reg, address) ((DMA_ARCH_TYPE *)(reg))->CMAR = (uint32_t)&s->port.txBuffer[s->port.txBufferTail] +#endif + +#if defined(USE_HAL_DRIVER) + +// We actually need these LL case only + +#define xLL_EX_DMA_DeInit(dmaResource) LL_EX_DMA_DeInit((DMA_ARCH_TYPE *)(dmaResource)) +#define xLL_EX_DMA_Init(dmaResource, initstruct) LL_EX_DMA_Init((DMA_ARCH_TYPE *)(dmaResource), initstruct) +#define xLL_EX_DMA_DisableResource(dmaResource) LL_EX_DMA_DisableResource((DMA_ARCH_TYPE *)(dmaResource)) +#define xLL_EX_DMA_EnableResource(dmaResource) LL_EX_DMA_EnableResource((DMA_ARCH_TYPE *)(dmaResource)) +#define xLL_EX_DMA_GetDataLength(dmaResource) LL_EX_DMA_GetDataLength((DMA_ARCH_TYPE *)(dmaResource)) +#define xLL_EX_DMA_SetDataLength(dmaResource, length) LL_EX_DMA_SetDataLength((DMA_ARCH_TYPE *)(dmaResource), length) +#define xLL_EX_DMA_EnableIT_TC(dmaResource) LL_EX_DMA_EnableIT_TC((DMA_ARCH_TYPE *)(dmaResource)) + +#else + +#define xDMA_Init(dmaResource, initStruct) DMA_Init((DMA_ARCH_TYPE *)(dmaResource), initStruct) +#define xDMA_DeInit(dmaResource) DMA_DeInit((DMA_ARCH_TYPE *)(dmaResource)) +#define xDMA_Cmd(dmaResource, newState) DMA_Cmd((DMA_ARCH_TYPE *)(dmaResource), newState) +#define xDMA_ITConfig(dmaResource, flags, newState) DMA_ITConfig((DMA_ARCH_TYPE *)(dmaResource), flags, newState) +#define xDMA_GetCurrDataCounter(dmaResource) DMA_GetCurrDataCounter((DMA_ARCH_TYPE *)(dmaResource)) +#define xDMA_SetCurrDataCounter(dmaResource, count) DMA_SetCurrDataCounter((DMA_ARCH_TYPE *)(dmaResource), count) +#define xDMA_GetFlagStatus(dmaResource, flags) DMA_GetFlagStatus((DMA_ARCH_TYPE *)(dmaResource), flags) +#define xDMA_ClearFlag(dmaResource, flags) DMA_ClearFlag((DMA_ARCH_TYPE *)(dmaResource), flags) +#define xDMA_MemoryTargetConfig(dmaResource, address, target) DMA_MemoryTargetConfig((DMA_ARCH_TYPE *)(dmaResource), address, target) + +#endif diff --git a/src/platform/STM32/mk/STM32F4.mk b/src/platform/STM32/mk/STM32F4.mk index e41e3db33b..aa4b1d6249 100644 --- a/src/platform/STM32/mk/STM32F4.mk +++ b/src/platform/STM32/mk/STM32F4.mk @@ -117,6 +117,7 @@ CMSIS_SRC := INCLUDE_DIRS := \ $(INCLUDE_DIRS) \ $(TARGET_PLATFORM_DIR) \ + $(TARGET_PLATFORM_DIR)/include \ $(TARGET_PLATFORM_DIR)/startup \ $(STDPERIPH_DIR)/Inc \ $(LIB_MAIN_DIR)/$(USBCORE_DIR)/Inc \ @@ -132,6 +133,7 @@ CMSIS_SRC := \ INCLUDE_DIRS := \ $(INCLUDE_DIRS) \ $(TARGET_PLATFORM_DIR) \ + $(TARGET_PLATFORM_DIR)/include \ $(TARGET_PLATFORM_DIR)/startup \ $(STDPERIPH_DIR)/inc \ $(LIB_MAIN_DIR)/$(USBOTG_DIR)/inc \ diff --git a/src/platform/STM32/mk/STM32F7.mk b/src/platform/STM32/mk/STM32F7.mk index f68fd69525..90c3291cec 100644 --- a/src/platform/STM32/mk/STM32F7.mk +++ b/src/platform/STM32/mk/STM32F7.mk @@ -85,6 +85,7 @@ VPATH := $(VPATH):$(CMSIS_DIR)/Include:$(CMSIS_DIR)/Device/ST/STM32F7x CMSIS_SRC := INCLUDE_DIRS := $(INCLUDE_DIRS) \ $(TARGET_PLATFORM_DIR) \ + $(TARGET_PLATFORM_DIR)/include \ $(TARGET_PLATFORM_DIR)/startup \ $(STDPERIPH_DIR)/Inc \ $(LIB_MAIN_DIR)/$(USBCORE_DIR)/Inc \ diff --git a/src/platform/STM32/mk/STM32G4.mk b/src/platform/STM32/mk/STM32G4.mk index 38cf7cdbdd..0706aff8fd 100644 --- a/src/platform/STM32/mk/STM32G4.mk +++ b/src/platform/STM32/mk/STM32G4.mk @@ -78,6 +78,7 @@ CMSIS_SRC := INCLUDE_DIRS := \ $(INCLUDE_DIRS) \ $(TARGET_PLATFORM_DIR) \ + $(TARGET_PLATFORM_DIR)/include \ $(TARGET_PLATFORM_DIR)/startup \ $(STDPERIPH_DIR)/Inc \ $(LIB_MAIN_DIR)/$(USBCORE_DIR)/Inc \ diff --git a/src/platform/STM32/mk/STM32H5.mk b/src/platform/STM32/mk/STM32H5.mk index 13c5a59cb3..a9080ba2ed 100644 --- a/src/platform/STM32/mk/STM32H5.mk +++ b/src/platform/STM32/mk/STM32H5.mk @@ -87,6 +87,7 @@ VPATH := $(VPATH):$(CMSIS_DIR)/Include:$(CMSIS_DIR)/Device/ST/STM32H5x CMSIS_SRC := INCLUDE_DIRS := $(INCLUDE_DIRS) \ $(TARGET_PLATFORM_DIR) \ + $(TARGET_PLATFORM_DIR)/include \ $(TARGET_PLATFORM_DIR)/startup \ $(STDPERIPH_DIR)/Inc \ $(LIB_MAIN_DIR)/$(USBCORE_DIR)/Inc \ diff --git a/src/platform/STM32/mk/STM32H7.mk b/src/platform/STM32/mk/STM32H7.mk index edcd2c27b8..7d192ff057 100644 --- a/src/platform/STM32/mk/STM32H7.mk +++ b/src/platform/STM32/mk/STM32H7.mk @@ -91,6 +91,7 @@ VPATH := $(VPATH):$(CMSIS_DIR)/Include:$(CMSIS_DIR)/Device/ST/STM32H7x CMSIS_SRC := INCLUDE_DIRS := $(INCLUDE_DIRS) \ $(TARGET_PLATFORM_DIR) \ + $(TARGET_PLATFORM_DIR)/include \ $(TARGET_PLATFORM_DIR)/startup \ $(STDPERIPH_DIR)/Inc \ $(LIB_MAIN_DIR)/$(USBCORE_DIR)/Inc \ diff --git a/src/test/unit/platform/dma.h b/src/test/unit/platform/dma.h new file mode 100644 index 0000000000..f199deeed6 --- /dev/null +++ b/src/test/unit/platform/dma.h @@ -0,0 +1,27 @@ +/* + * This file is part of Betaflight. + * + * Betaflight is free software. You can redistribute this software + * and/or modify this software under the terms of the GNU General + * Public License as published by the Free Software Foundation, + * either version 3 of the License, or (at your option) any later + * version. + * + * Betaflight is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * See the GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this software. + * + * If not, see . + */ + + #pragma once + + typedef enum { + DMA_NONE = 0, + DMA_LAST_HANDLER = DMA_NONE +} dmaIdentifier_e; From 472cc2b84a0e49a06f87153c248f2478e52fabbc Mon Sep 17 00:00:00 2001 From: "Git bot (blckmn)" Date: Wed, 2 Apr 2025 06:25:03 +0000 Subject: [PATCH 152/244] Auto updated submodule references [02-04-2025] --- src/config | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/config b/src/config index b606002103..b084af24b5 160000 --- a/src/config +++ b/src/config @@ -1 +1 @@ -Subproject commit b60600210384d1da4621cc35a0632d9cca8a62b7 +Subproject commit b084af24b5de9e430ff92b0d0e3b5ef8b4f6ed0d From ab5449c9b15ecefae9aee452dda41ecaa950d59f Mon Sep 17 00:00:00 2001 From: Mark Haslinghuis Date: Wed, 2 Apr 2025 19:16:36 +0200 Subject: [PATCH 153/244] Add PB0 to AT32 SPI3 mosi pins (#14324) --- src/platform/AT32/platform_mcu.h | 2 +- src/platform/common/stm32/bus_spi_pinconfig.c | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/src/platform/AT32/platform_mcu.h b/src/platform/AT32/platform_mcu.h index dc2e81e248..2c55895061 100644 --- a/src/platform/AT32/platform_mcu.h +++ b/src/platform/AT32/platform_mcu.h @@ -139,7 +139,7 @@ typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; #define CHECK_SPI_RX_DATA_AVAILABLE(instance) LL_SPI_IsActiveFlag_RXNE(instance) #define SPI_RX_DATA_REGISTER(base) ((base)->DR) -#define MAX_SPI_PIN_SEL 4 +#define MAX_SPI_PIN_SEL 5 #define UART_TX_BUFFER_ATTRIBUTE // NONE #define UART_RX_BUFFER_ATTRIBUTE // NONE diff --git a/src/platform/common/stm32/bus_spi_pinconfig.c b/src/platform/common/stm32/bus_spi_pinconfig.c index ee59d7cd24..59c68b214a 100644 --- a/src/platform/common/stm32/bus_spi_pinconfig.c +++ b/src/platform/common/stm32/bus_spi_pinconfig.c @@ -403,6 +403,7 @@ const spiHardware_t spiHardware[] = { { DEFIO_TAG_E(PC11), GPIO_MUX_6}, }, .mosiPins = { + { DEFIO_TAG_E(PB0), GPIO_MUX_7}, { DEFIO_TAG_E(PB2), GPIO_MUX_7}, { DEFIO_TAG_E(PB5), GPIO_MUX_6}, { DEFIO_TAG_E(PC12), GPIO_MUX_6}, From 088620ce358753a70966220aac1e3c50dd05dba5 Mon Sep 17 00:00:00 2001 From: "Git bot (blckmn)" Date: Thu, 3 Apr 2025 06:25:03 +0000 Subject: [PATCH 154/244] Auto updated submodule references [03-04-2025] --- src/config | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/config b/src/config index b084af24b5..d279f4dec3 160000 --- a/src/config +++ b/src/config @@ -1 +1 @@ -Subproject commit b084af24b5de9e430ff92b0d0e3b5ef8b4f6ed0d +Subproject commit d279f4dec311175f312213e987b11ceda5877ef9 From df2e99b95321754459bf153051907ae72b0fd7b8 Mon Sep 17 00:00:00 2001 From: Vladimir Demidov Date: Fri, 4 Apr 2025 22:57:44 +0300 Subject: [PATCH 155/244] Added virtual blackbox for SITL (#14325) * Added virtual black box for SITL * Update src/main/blackbox/blackbox_virtual.c The platform.h is added into blackbox_virtual,c Co-authored-by: Mark Haslinghuis * Virtual blackbox code style improvement * Resolved issue of log files counter * Added logs file name length checking in virtual blackbox * Added open directory function result checking Co-authored-by: Mark Haslinghuis * Added computing of const log file neme length * Improved virtual blackbox file name generation * Edited errors description in case of using virtual blackbox for non SITL build * Removed extra #ifdef Co-authored-by: Mark Haslinghuis * Apply USE_BLACKBOX, USE_BLACKBOX_VIRTUAL define for SITL build * Code style improvement Co-authored-by: Jan Post * Code style improvement Co-authored-by: Jan Post * Code style improvement Co-authored-by: Jan Post * Code style improvement Co-authored-by: Jan Post * Code style improvement Co-authored-by: Jan Post * Code style improvement Co-authored-by: Jan Post * Added USE_BLACKBOX_VIRTUAL checking for #error message --------- Co-authored-by: Mark Haslinghuis Co-authored-by: Jan Post --- src/main/blackbox/blackbox.c | 3 + src/main/blackbox/blackbox.h | 3 +- src/main/blackbox/blackbox_io.c | 73 +++++++++++- src/main/blackbox/blackbox_virtual.c | 117 +++++++++++++++++++ src/main/blackbox/blackbox_virtual.h | 35 ++++++ src/main/cli/settings.c | 8 +- src/platform/SIMULATOR/target/SITL/target.h | 3 + src/platform/SIMULATOR/target/SITL/target.mk | 3 +- 8 files changed, 240 insertions(+), 5 deletions(-) create mode 100644 src/main/blackbox/blackbox_virtual.c create mode 100644 src/main/blackbox/blackbox_virtual.h diff --git a/src/main/blackbox/blackbox.c b/src/main/blackbox/blackbox.c index 7ece9940ca..1e4b2725fc 100644 --- a/src/main/blackbox/blackbox.c +++ b/src/main/blackbox/blackbox.c @@ -1050,6 +1050,9 @@ void blackboxValidateConfig(void) #endif #ifdef USE_SDCARD case BLACKBOX_DEVICE_SDCARD: +#endif +#ifdef USE_BLACKBOX_VIRTUAL + case BLACKBOX_DEVICE_VIRTUAL: #endif case BLACKBOX_DEVICE_SERIAL: // Device supported, leave the setting alone diff --git a/src/main/blackbox/blackbox.h b/src/main/blackbox/blackbox.h index 6738f37d45..b65e67db67 100644 --- a/src/main/blackbox/blackbox.h +++ b/src/main/blackbox/blackbox.h @@ -29,7 +29,8 @@ typedef enum BlackboxDevice { BLACKBOX_DEVICE_NONE = 0, BLACKBOX_DEVICE_FLASH = 1, BLACKBOX_DEVICE_SDCARD = 2, - BLACKBOX_DEVICE_SERIAL = 3 + BLACKBOX_DEVICE_SERIAL = 3, + BLACKBOX_DEVICE_VIRTUAL = 4, } BlackboxDevice_e; typedef enum BlackboxMode { diff --git a/src/main/blackbox/blackbox_io.c b/src/main/blackbox/blackbox_io.c index b981c2840d..cef7be8036 100644 --- a/src/main/blackbox/blackbox_io.c +++ b/src/main/blackbox/blackbox_io.c @@ -59,6 +59,8 @@ #include "drivers/sdcard.h" #endif +#include "blackbox_virtual.h" + #define BLACKBOX_SERIAL_PORT_MODE MODE_TX // How many bytes can we transmit per loop iteration when writing headers? @@ -124,6 +126,11 @@ void blackboxWrite(uint8_t value) case BLACKBOX_DEVICE_SDCARD: afatfs_fputc(blackboxSDCard.logFile, value); break; +#endif +#ifdef USE_BLACKBOX_VIRTUAL + case BLACKBOX_DEVICE_VIRTUAL: + blackboxVirtualPutChar(value); + break; #endif case BLACKBOX_DEVICE_SERIAL: default: @@ -185,6 +192,13 @@ int blackboxWriteString(const char *s) break; #endif // USE_SDCARD +#ifdef USE_BLACKBOX_VIRTUAL + case BLACKBOX_DEVICE_VIRTUAL: + length = strlen(s); + blackboxVirtualWrite((const uint8_t*) s, length); + break; +#endif + case BLACKBOX_DEVICE_SERIAL: default: pos = (uint8_t*) s; @@ -217,6 +231,11 @@ void blackboxDeviceFlush(void) flashfsFlushAsync(false); break; #endif // USE_FLASHFS +#ifdef USE_BLACKBOX_VIRTUAL + case BLACKBOX_DEVICE_VIRTUAL: + blackboxVirtualFlush(); + break; +#endif default: ; @@ -249,6 +268,10 @@ bool blackboxDeviceFlushForce(void) // been physically written to the SD card yet. return afatfs_flush(); #endif // USE_SDCARD +#ifdef USE_BLACKBOX_VIRTUAL + case BLACKBOX_DEVICE_VIRTUAL: + return blackboxVirtualFlush(); +#endif default: return false; @@ -269,6 +292,11 @@ bool blackboxDeviceFlushForceComplete(void) return false; } #endif // USE_SDCARD +#ifdef USE_BLACKBOX_VIRTUAL + case BLACKBOX_DEVICE_VIRTUAL: + blackboxVirtualFlush(); + return true; +#endif default: return blackboxDeviceFlushForce(); @@ -360,6 +388,11 @@ bool blackboxDeviceOpen(void) return true; break; #endif // USE_SDCARD +#ifdef USE_BLACKBOX_VIRTUAL + case BLACKBOX_DEVICE_VIRTUAL: + return blackboxVirtualOpen(); + +#endif default: return false; } @@ -428,6 +461,11 @@ void blackboxDeviceClose(void) // Some flash device, e.g., NAND devices, require explicit close to flush internally buffered data. flashfsClose(); break; +#endif +#ifdef USE_BLACKBOX_VIRTUAL + case BLACKBOX_DEVICE_VIRTUAL: + blackboxVirtualClose(); + break; #endif default: ; @@ -564,6 +602,10 @@ bool blackboxDeviceBeginLog(void) case BLACKBOX_DEVICE_SDCARD: return blackboxSDCardBeginLog(); #endif // USE_SDCARD +#ifdef USE_BLACKBOX_VIRTUAL + case BLACKBOX_DEVICE_VIRTUAL: + return blackboxVirtualBeginLog(); +#endif default: return true; } @@ -598,6 +640,13 @@ bool blackboxDeviceEndLog(bool retainLog) } return false; #endif // USE_SDCARD + +#ifdef USE_BLACKBOX_VIRTUAL + case BLACKBOX_DEVICE_VIRTUAL: + blackboxVirtualEndLog(); + return true; +#endif + default: return true; } @@ -640,6 +689,11 @@ bool isBlackboxDeviceWorking(void) return flashfsIsReady(); #endif +#ifdef USE_BLACKBOX_VIRTUAL + case BLACKBOX_DEVICE_VIRTUAL: + return true; +#endif + default: return false; } @@ -653,6 +707,12 @@ int32_t blackboxGetLogNumber(void) return blackboxSDCard.largestLogFileNumber; #endif +#ifdef USE_BLACKBOX_VIRTUAL + case BLACKBOX_DEVICE_VIRTUAL: + return blackboxVirtualLogFileNumber(); + break; +#endif + default: return -1; } @@ -679,6 +739,11 @@ void blackboxReplenishHeaderBudget(void) case BLACKBOX_DEVICE_SDCARD: freeSpace = afatfs_getFreeBufferSpace(); break; +#endif +#ifdef USE_BLACKBOX_VIRTUAL + case BLACKBOX_DEVICE_VIRTUAL: + blackboxHeaderBudget = 1024*8; + return; #endif default: freeSpace = 0; @@ -745,6 +810,12 @@ blackboxBufferReserveStatus_e blackboxDeviceReserveBufferSpace(int32_t bytes) return BLACKBOX_RESERVE_TEMPORARY_FAILURE; #endif // USE_SDCARD +#ifdef USE_BLACKBOX_VIRTUAL + case BLACKBOX_DEVICE_VIRTUAL: + return BLACKBOX_RESERVE_TEMPORARY_FAILURE; +#endif + + default: return BLACKBOX_RESERVE_PERMANENT_FAILURE; } @@ -752,7 +823,6 @@ blackboxBufferReserveStatus_e blackboxDeviceReserveBufferSpace(int32_t bytes) int8_t blackboxGetLogFileNo(void) { -#ifdef USE_BLACKBOX #ifdef USE_SDCARD // return current file number or -1 if (blackboxSDCard.state == BLACKBOX_SDCARD_READY_TO_LOG) { @@ -764,6 +834,5 @@ int8_t blackboxGetLogFileNo(void) // will be implemented later for flash based storage return -1; #endif -#endif } #endif // BLACKBOX diff --git a/src/main/blackbox/blackbox_virtual.c b/src/main/blackbox/blackbox_virtual.c new file mode 100644 index 0000000000..d607e6f125 --- /dev/null +++ b/src/main/blackbox/blackbox_virtual.c @@ -0,0 +1,117 @@ +/* + * This file is part of Betaflight. + * + * Betaflight is free software. You can redistribute this software + * and/or modify this software under the terms of the GNU General + * Public License as published by the Free Software Foundation, + * either version 3 of the License, or (at your option) any later + * version. + * + * Betaflight is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * See the GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this software. + * + * If not, see . + */ + +#include "platform.h" +#include +#include +#include +#include +#include +#include +#include + +#define LOGFILE_PREFIX "LOG" +#define LOGFILE_SUFFIX "BFL" + +static FILE *blackboxVirtualFile = NULL; +static int32_t largestLogFileNumber = 0; + +bool blackboxVirtualOpen(void) +{ + const size_t log_name_length = strlen(LOGFILE_PREFIX) + 5 + strlen(LOGFILE_SUFFIX) + 1; //file name template: LOG00001.BFL + DIR *dir = opendir("."); + if (!dir) { + return false; // Failed to open directory + } + + struct dirent *entry; + while ((entry = readdir(dir)) != NULL) { + if (strlen(entry->d_name) == log_name_length + && strncmp(entry->d_name, LOGFILE_PREFIX, strlen(LOGFILE_PREFIX)) == 0 + && strncmp(entry->d_name + 9, LOGFILE_SUFFIX, strlen(LOGFILE_SUFFIX)) == 0) { + + char logSequenceNumberString[6]; + memcpy(logSequenceNumberString, entry->d_name + 3, 5); + logSequenceNumberString[5] = '\0'; + largestLogFileNumber = MAX((int32_t)atoi(logSequenceNumberString), largestLogFileNumber); + } + } + closedir(dir); + return true; +} + +void blackboxVirtualPutChar(uint8_t value) +{ + if (blackboxVirtualFile != NULL) { + fputc(value, blackboxVirtualFile); + } +} + +void blackboxVirtualWrite(const uint8_t *buffer, uint32_t len) +{ + if (blackboxVirtualFile != NULL) { + fwrite(buffer, len, 1, blackboxVirtualFile); + } +} + +bool blackboxVirtualFlush(void) +{ + if (blackboxVirtualFile != NULL) { + fflush(blackboxVirtualFile); + return true; + } else { + return false; + } +} + +bool blackboxVirtualBeginLog(void) +{ + if (blackboxVirtualFile != NULL) { + return false; + } + const size_t name_buffer_length = strlen(LOGFILE_PREFIX) + 5 + strlen(LOGFILE_SUFFIX) + 2; //file name template: LOG00001.BFL + char filename[name_buffer_length]; + sprintf(filename, "%s%05i.%s", LOGFILE_PREFIX, largestLogFileNumber + 1, LOGFILE_SUFFIX); + blackboxVirtualFile = fopen(filename, "w"); + if (blackboxVirtualFile != NULL) { + largestLogFileNumber++; + } + return blackboxVirtualFile != NULL; +} + +bool blackboxVirtualEndLog(void) +{ + if (blackboxVirtualFile != NULL) { + fclose(blackboxVirtualFile); + blackboxVirtualFile = NULL; + } + return true; +} + +void blackboxVirtualClose(void) +{ + blackboxVirtualEndLog(); +} + +uint32_t blackboxVirtualLogFileNumber(void) +{ + return largestLogFileNumber; +} diff --git a/src/main/blackbox/blackbox_virtual.h b/src/main/blackbox/blackbox_virtual.h new file mode 100644 index 0000000000..7f2eb0ee71 --- /dev/null +++ b/src/main/blackbox/blackbox_virtual.h @@ -0,0 +1,35 @@ +/* + * This file is part of Betaflight. + * + * Betaflight is free software. You can redistribute this software + * and/or modify this software under the terms of the GNU General + * Public License as published by the Free Software Foundation, + * either version 3 of the License, or (at your option) any later + * version. + * + * Betaflight is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * See the GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this software. + * + * If not, see . + */ + +#pragma once + +#if defined(USE_BLACKBOX_VIRTUAL) && !defined(SIMULATOR_BUILD) +#error "USE_BLACKBOX_VIRTUAL valid for SITL build only" +#endif + +bool blackboxVirtualOpen(void); +void blackboxVirtualPutChar(uint8_t value); +void blackboxVirtualWrite(const uint8_t *buffer, uint32_t len); +bool blackboxVirtualFlush(void); +bool blackboxVirtualBeginLog(void); +bool blackboxVirtualEndLog(void); +void blackboxVirtualClose(void); +uint32_t blackboxVirtualLogFileNumber(void); diff --git a/src/main/cli/settings.c b/src/main/cli/settings.c index e1b9bdd91e..96df532868 100644 --- a/src/main/cli/settings.c +++ b/src/main/cli/settings.c @@ -268,7 +268,13 @@ static const char * const lookupTableGimbalMode[] = { #ifdef USE_BLACKBOX static const char * const lookupTableBlackboxDevice[] = { - "NONE", "SPIFLASH", "SDCARD", "SERIAL" + "NONE", + "SPIFLASH", + "SDCARD", + "SERIAL", +#ifdef USE_BLACKBOX_VIRTUAL + "VIRTUAL", +#endif }; static const char * const lookupTableBlackboxMode[] = { diff --git a/src/platform/SIMULATOR/target/SITL/target.h b/src/platform/SIMULATOR/target/SITL/target.h index 6fee3baee9..01f6518613 100644 --- a/src/platform/SIMULATOR/target/SITL/target.h +++ b/src/platform/SIMULATOR/target/SITL/target.h @@ -105,6 +105,9 @@ #define USE_PWM_OUTPUT #endif +#define USE_BLACKBOX +#define USE_BLACKBOX_VIRTUAL + #undef USE_STACK_CHECK // I think SITL don't need this #undef USE_DASHBOARD #undef USE_TELEMETRY_LTM diff --git a/src/platform/SIMULATOR/target/SITL/target.mk b/src/platform/SIMULATOR/target/SITL/target.mk index 23d7794138..d46536b9a2 100644 --- a/src/platform/SIMULATOR/target/SITL/target.mk +++ b/src/platform/SIMULATOR/target/SITL/target.mk @@ -7,7 +7,8 @@ TARGET_SRC = \ drivers/barometer/barometer_virtual.c \ drivers/compass/compass_virtual.c \ drivers/serial_tcp.c \ - io/gps_virtual.c + io/gps_virtual.c \ + blackbox/blackbox_virtual.c SIZE_OPTIMISED_SRC += \ drivers/serial_tcp.c From eb36e9e11a48bc777f984853cb93f29849811428 Mon Sep 17 00:00:00 2001 From: "Git bot (blckmn)" Date: Sat, 5 Apr 2025 06:25:03 +0000 Subject: [PATCH 156/244] Auto updated submodule references [05-04-2025] --- src/config | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/config b/src/config index d279f4dec3..2f948c91e9 160000 --- a/src/config +++ b/src/config @@ -1 +1 @@ -Subproject commit d279f4dec311175f312213e987b11ceda5877ef9 +Subproject commit 2f948c91e9344975e1fdfc1c9bfd34a082724423 From c55d7c5c318623df15d781e0cf1df3cd77a238a4 Mon Sep 17 00:00:00 2001 From: Mark Haslinghuis Date: Mon, 7 Apr 2025 01:27:02 +0200 Subject: [PATCH 157/244] Revert GPS flight model change (#14333) --- src/main/pg/gps.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/pg/gps.c b/src/main/pg/gps.c index c8d5df62f8..81f9e0e396 100644 --- a/src/main/pg/gps.c +++ b/src/main/pg/gps.c @@ -41,7 +41,7 @@ PG_RESET_TEMPLATE(gpsConfig_t, gpsConfig, .autoConfig = GPS_AUTOCONFIG_ON, .autoBaud = GPS_AUTOBAUD_OFF, .gps_ublox_acquire_model = UBLOX_MODEL_STATIONARY, - .gps_ublox_flight_model = UBLOX_MODEL_AIRBORNE_1G, + .gps_ublox_flight_model = UBLOX_MODEL_AIRBORNE_4G, .gps_update_rate_hz = 10, .gps_ublox_use_galileo = false, .gps_set_home_point_once = false, From d9f418dd06ccac4b8944966229ac033d004a04a4 Mon Sep 17 00:00:00 2001 From: Jay Blackman Date: Wed, 9 Apr 2025 03:25:14 +1000 Subject: [PATCH 158/244] Jetiexbus -> function unused without GPS enabled. (#14336) --- src/main/telemetry/jetiexbus.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/main/telemetry/jetiexbus.c b/src/main/telemetry/jetiexbus.c index e76a19e16e..a03021921a 100644 --- a/src/main/telemetry/jetiexbus.c +++ b/src/main/telemetry/jetiexbus.c @@ -285,6 +285,7 @@ static void createExTelemetryTextMessage(uint8_t *exMessage, uint8_t messageID, exMessage[exMessage[EXTEL_HEADER_TYPE_LEN] + EXTEL_CRC_LEN] = calcCRC8(&exMessage[EXTEL_HEADER_TYPE_LEN], exMessage[EXTEL_HEADER_TYPE_LEN]); } +#ifdef USE_GPS static uint32_t calcGpsDDMMmmm(int32_t value, bool isLong) { uint32_t absValue = abs(value); @@ -299,6 +300,7 @@ static uint32_t calcGpsDDMMmmm(int32_t value, bool isLong) return exGps.vInt; } +#endif static int32_t getSensorValue(uint8_t sensor) { From 609533a73704f9c9173d57af0c85cd403272d778 Mon Sep 17 00:00:00 2001 From: "Git bot (blckmn)" Date: Wed, 9 Apr 2025 06:25:03 +0000 Subject: [PATCH 159/244] Auto updated submodule references [09-04-2025] --- src/config | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/config b/src/config index 2f948c91e9..467f87b950 160000 --- a/src/config +++ b/src/config @@ -1 +1 @@ -Subproject commit 2f948c91e9344975e1fdfc1c9bfd34a082724423 +Subproject commit 467f87b950f406bd34e0075ac2438a2e06f5ed63 From fd3a131797a1079ade6670117a54bf05b085b0b2 Mon Sep 17 00:00:00 2001 From: LiuYongNan <89908604+LYNHQQ@users.noreply.github.com> Date: Wed, 9 Apr 2025 21:25:27 +0800 Subject: [PATCH 160/244] fix rtc6705 drive (#14296) * fix rtc6705 drive * Update rt6705 request suggestion --- src/main/drivers/vtx_rtc6705.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/src/main/drivers/vtx_rtc6705.c b/src/main/drivers/vtx_rtc6705.c index 091d874884..37fcd8bab2 100644 --- a/src/main/drivers/vtx_rtc6705.c +++ b/src/main/drivers/vtx_rtc6705.c @@ -95,7 +95,6 @@ static uint32_t reverse32(uint32_t in) bool rtc6705IOInit(const vtxIOConfig_t *vtxIOConfig) { static extDevice_t devInstance; - IO_t csnPin = IOGetByTag(vtxIOConfig->csTag); if (!csnPin) { return false; @@ -112,15 +111,16 @@ bool rtc6705IOInit(const vtxIOConfig_t *vtxIOConfig) // RTC6705 when using SOFT SPI driver doesn't use an SPI device, so don't attempt to initialise an spiInstance. SPI_TypeDef *spiInstance = spiInstanceByDevice(SPI_CFG_TO_DEV(vtxIOConfig->spiDevice)); - if (spiInstance && spiSetBusInstance(dev, vtxIOConfig->spiDevice)) { - devInstance.busType_u.spi.csnPin = csnPin; - IOInit(devInstance.busType_u.spi.csnPin, OWNER_VTX_CS, 0); - + if (spiInstance && spiSetBusInstance(&devInstance, vtxIOConfig->spiDevice)) { + dev = &devInstance; + dev->busType_u.spi.csnPin = csnPin; + IOInit(dev->busType_u.spi.csnPin, OWNER_VTX_CS, 0); DISABLE_RTC6705(); // GPIO bit is enabled so here so the output is not pulled low when the GPIO is set in output mode. // Note: It's critical to ensure that incorrect signals are not sent to the VTX. - IOConfigGPIO(devInstance.busType_u.spi.csnPin, IOCFG_OUT_PP); + IOConfigGPIO(dev->busType_u.spi.csnPin, IOCFG_OUT_PP); + spiSetBusInstance(dev, vtxIOConfig->spiDevice); return true; #if defined(USE_VTX_RTC6705_SOFTSPI) } else { @@ -141,6 +141,8 @@ static void rtc6705Transfer(uint32_t command) // Perform bitwise reverse of the command. command = reverse32(command); + command = ((command >> 24) & 0xFF) | (((command >> 16) & 0xFF) << 8) | (((command >> 8) & 0xFF) << 16) | (((command >> 0) & 0xFF) << 24); + spiReadWriteBuf(dev, (uint8_t *)&command, NULL, sizeof(command)); delayMicroseconds(2); From 4ae22e9f8eb149a758b4847ae692990f5be1eb7f Mon Sep 17 00:00:00 2001 From: Marc Frank Date: Thu, 10 Apr 2025 14:39:36 +0200 Subject: [PATCH 161/244] hover point throttle curve adjustment (#14229) * hover point throttle curve adjustment * Update src/main/fc/rc.c Co-authored-by: Mark Haslinghuis * Update src/main/fc/rc.c Co-authored-by: Petr Ledvina * Update src/main/fc/rc.c Co-authored-by: Petr Ledvina * refactor lookup calculation and move hover to end of controlRateConfig_s struct * moved sbufReadU8 to the bottom * added sbufBytesRemaining check * update controlRateProfile version from 6 to 7 * moved thrHover8 declaration position * revert variable declaration position change * fixed tests --------- Co-authored-by: Mark Haslinghuis Co-authored-by: Petr Ledvina --- src/main/blackbox/blackbox.c | 1 + src/main/cli/settings.c | 1 + src/main/cms/cms_menu_imu.c | 1 + src/main/fc/controlrate_profile.c | 3 +- src/main/fc/controlrate_profile.h | 1 + src/main/fc/parameter_names.h | 1 + src/main/fc/rc.c | 49 ++++++++++++++++++++++----- src/main/msp/msp.c | 10 +++++- src/test/unit/rc_controls_unittest.cc | 3 ++ 9 files changed, 60 insertions(+), 10 deletions(-) diff --git a/src/main/blackbox/blackbox.c b/src/main/blackbox/blackbox.c index 1e4b2725fc..b4d7f02e7e 100644 --- a/src/main/blackbox/blackbox.c +++ b/src/main/blackbox/blackbox.c @@ -1530,6 +1530,7 @@ static bool blackboxWriteSysinfo(void) BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_PID_PROCESS_DENOM, "%d", activePidLoopDenom); BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_THR_MID, "%d", currentControlRateProfile->thrMid8); BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_THR_EXPO, "%d", currentControlRateProfile->thrExpo8); + BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_THR_HOVER, "%d", currentControlRateProfile->thrHover8); BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_TPA_MODE, "%d", currentPidProfile->tpa_mode); BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_TPA_RATE, "%d", currentPidProfile->tpa_rate); BLACKBOX_PRINT_HEADER_LINE(PARAM_NAME_TPA_BREAKPOINT, "%d", currentPidProfile->tpa_breakpoint); diff --git a/src/main/cli/settings.c b/src/main/cli/settings.c index 96df532868..b0ad031be9 100644 --- a/src/main/cli/settings.c +++ b/src/main/cli/settings.c @@ -1062,6 +1062,7 @@ const clivalue_t valueTable[] = { #endif { PARAM_NAME_THR_MID, VAR_UINT8 | PROFILE_RATE_VALUE, .config.minmaxUnsigned = { 0, 100 }, PG_CONTROL_RATE_PROFILES, offsetof(controlRateConfig_t, thrMid8) }, { PARAM_NAME_THR_EXPO, VAR_UINT8 | PROFILE_RATE_VALUE, .config.minmaxUnsigned = { 0, 100 }, PG_CONTROL_RATE_PROFILES, offsetof(controlRateConfig_t, thrExpo8) }, + { PARAM_NAME_THR_HOVER, VAR_UINT8 | PROFILE_RATE_VALUE, .config.minmaxUnsigned = { 0, 100 }, PG_CONTROL_RATE_PROFILES, offsetof(controlRateConfig_t, thrHover8) }, { PARAM_NAME_RATES_TYPE, VAR_UINT8 | PROFILE_RATE_VALUE | MODE_LOOKUP, .config.lookup = { TABLE_RATES_TYPE }, PG_CONTROL_RATE_PROFILES, offsetof(controlRateConfig_t, rates_type) }, { "quickrates_rc_expo", VAR_UINT8 | PROFILE_RATE_VALUE | MODE_LOOKUP, .config.lookup = { TABLE_OFF_ON }, PG_CONTROL_RATE_PROFILES, offsetof(controlRateConfig_t, quickRatesRcExpo) }, { "roll_rc_rate", VAR_UINT8 | PROFILE_RATE_VALUE, .config.minmaxUnsigned = { 1, CONTROL_RATE_CONFIG_RC_RATES_MAX }, PG_CONTROL_RATE_PROFILES, offsetof(controlRateConfig_t, rcRates[FD_ROLL]) }, diff --git a/src/main/cms/cms_menu_imu.c b/src/main/cms/cms_menu_imu.c index d10e386652..2c48e6106d 100644 --- a/src/main/cms/cms_menu_imu.c +++ b/src/main/cms/cms_menu_imu.c @@ -429,6 +429,7 @@ static const OSD_Entry cmsx_menuRateProfileEntries[] = { "THR MID", OME_UINT8, NULL, &(OSD_UINT8_t) { &rateProfile.thrMid8, 0, 100, 1} }, { "THR EXPO", OME_UINT8, NULL, &(OSD_UINT8_t) { &rateProfile.thrExpo8, 0, 100, 1} }, + { "THR HOVER", OME_UINT8, NULL, &(OSD_UINT8_t) { &rateProfile.thrHover8, 0, 100, 1} }, { "THR LIM TYPE",OME_TAB, NULL, &(OSD_TAB_t) { &rateProfile.throttle_limit_type, THROTTLE_LIMIT_TYPE_COUNT - 1, lookupTableThrottleLimitType} }, { "THR LIM %", OME_UINT8, NULL, &(OSD_UINT8_t) { &rateProfile.throttle_limit_percent, 25, 100, 1} }, diff --git a/src/main/fc/controlrate_profile.c b/src/main/fc/controlrate_profile.c index 0add5622b5..6fb219fbb5 100644 --- a/src/main/fc/controlrate_profile.c +++ b/src/main/fc/controlrate_profile.c @@ -37,7 +37,7 @@ controlRateConfig_t *currentControlRateProfile; -PG_REGISTER_ARRAY_WITH_RESET_FN(controlRateConfig_t, CONTROL_RATE_PROFILE_COUNT, controlRateProfiles, PG_CONTROL_RATE_PROFILES, 6); +PG_REGISTER_ARRAY_WITH_RESET_FN(controlRateConfig_t, CONTROL_RATE_PROFILE_COUNT, controlRateProfiles, PG_CONTROL_RATE_PROFILES, 7); void pgResetFn_controlRateProfiles(controlRateConfig_t *controlRateConfig) { @@ -62,6 +62,7 @@ void pgResetFn_controlRateProfiles(controlRateConfig_t *controlRateConfig) .rate_limit[FD_YAW] = CONTROL_RATE_CONFIG_RATE_LIMIT_MAX, .profileName = { 0 }, .quickRatesRcExpo = 0, + .thrHover8 = 50, ); } } diff --git a/src/main/fc/controlrate_profile.h b/src/main/fc/controlrate_profile.h index 6a2a05d415..61607f4b83 100644 --- a/src/main/fc/controlrate_profile.h +++ b/src/main/fc/controlrate_profile.h @@ -60,6 +60,7 @@ typedef struct controlRateConfig_s { uint16_t rate_limit[3]; // Sets the maximum rate for the axes char profileName[MAX_RATE_PROFILE_NAME_LENGTH + 1]; // Descriptive name for rate profile uint8_t quickRatesRcExpo; // Sets expo on rc command for quick rates + uint8_t thrHover8; } controlRateConfig_t; PG_DECLARE_ARRAY(controlRateConfig_t, CONTROL_RATE_PROFILE_COUNT, controlRateProfiles); diff --git a/src/main/fc/parameter_names.h b/src/main/fc/parameter_names.h index 070a516d6e..8d9c812183 100644 --- a/src/main/fc/parameter_names.h +++ b/src/main/fc/parameter_names.h @@ -51,6 +51,7 @@ #define PARAM_NAME_MOTOR_POLES "motor_poles" #define PARAM_NAME_THR_MID "thr_mid" #define PARAM_NAME_THR_EXPO "thr_expo" +#define PARAM_NAME_THR_HOVER "thr_hover" #define PARAM_NAME_RATES_TYPE "rates_type" #define PARAM_NAME_TPA_RATE "tpa_rate" #define PARAM_NAME_TPA_BREAKPOINT "tpa_breakpoint" diff --git a/src/main/fc/rc.c b/src/main/fc/rc.c index 80c284191a..f10752fecc 100644 --- a/src/main/fc/rc.c +++ b/src/main/fc/rc.c @@ -823,20 +823,53 @@ bool isMotorsReversed(void) return reverseMotors; } +static float quadraticBezier(float t, float p0, float p1, float p2) { + return (1.0f - t) * (1.0f - t) * p0 + 2.0f * (1.0f - t) * t * p1 + t * t * p2; +} + void initRcProcessing(void) { rcCommandDivider = 500.0f - rcControlsConfig()->deadband; rcCommandYawDivider = 500.0f - rcControlsConfig()->yaw_deadband; + float thrMid = currentControlRateProfile->thrMid8 / 100.0f; // normalized x coordinate for hover point + float expo = currentControlRateProfile->thrExpo8 / 100.0f; // normalized expo (0.0 .. 1.0) + float thrHover = currentControlRateProfile->thrHover8 / 100.0f; // normalized y coordinate for hover point + + /* + Algorithm Overview: + - thrMid and thrHover define a key point (hover point) in the throttle curve. + • thrMid is the normalized x-coordinate at which the curve reaches the hover point. + • thrHover is the normalized y-coordinate at that point. + - The curve is built in two segments using quadratic Bezier interpolation: + Segment 1: from (0, 0) to (thrMid, thrHover) + • ymin = 0, ymid = thrHover. + • The control point cp1y blends between (thrHover/2) for expo=0 and thrHover for expo=1. + Segment 2: from (thrMid, thrHover) to (1, 1) + • ymid = thrHover, ymax = 1. + • The control point cp2y blends between [thrHover + (1 - thrHover) / 2] for expo=0 and thrHover for expo=1. + - The output y is mapped from [0,1] to the PWM range. + */ + for (int i = 0; i < THROTTLE_LOOKUP_LENGTH; i++) { - const int16_t tmp = 10 * i - currentControlRateProfile->thrMid8; - uint8_t y = 1; - if (tmp > 0) - y = 100 - currentControlRateProfile->thrMid8; - if (tmp < 0) - y = currentControlRateProfile->thrMid8; - lookupThrottleRC[i] = 10 * currentControlRateProfile->thrMid8 + tmp * (100 - currentControlRateProfile->thrExpo8 + (int32_t) currentControlRateProfile->thrExpo8 * (tmp * tmp) / (y * y)) / 10; - lookupThrottleRC[i] = PWM_RANGE_MIN + PWM_RANGE * lookupThrottleRC[i] / 1000; // [MINTHROTTLE;MAXTHROTTLE] + float x = (float)i / (THROTTLE_LOOKUP_LENGTH - 1); + float y = 0.0f; + + if (x <= thrMid) { + float t = (thrMid > 0.0f) ? x / thrMid : 0.0f; + float ymin = 0.0f; + float ymid = thrHover; + float cp1y = (thrHover / 2.0f) * (1.0f - expo) + thrHover * expo; + y = quadraticBezier(t, ymin, cp1y, ymid); + } else { + float t = ((1.0f - thrMid) > 0.0f) ? (x - thrMid) / (1.0f - thrMid) : 0.0f; + float ymid = thrHover; + float ymax = 1.0f; + float cp2y = (thrHover + (1.0f - thrHover) / 2.0f) * (1.0f - expo) + thrHover * expo; + y = quadraticBezier(t, ymid, cp2y, ymax); + } + + lookupThrottleRC[i] = lrintf(scaleRangef(y, 0.0f, 1.0f, PWM_RANGE_MIN, PWM_RANGE_MAX)); } switch (currentControlRateProfile->rates_type) { diff --git a/src/main/msp/msp.c b/src/main/msp/msp.c index 025df2fc7b..3f6aeca7b2 100644 --- a/src/main/msp/msp.c +++ b/src/main/msp/msp.c @@ -1372,7 +1372,10 @@ case MSP_NAME: // added in 1.43 sbufWriteU8(dst, currentControlRateProfile->rates_type); - + + // added in 1.47 + sbufWriteU8(dst, currentControlRateProfile->thrHover8); + break; case MSP_PID: @@ -2851,6 +2854,11 @@ static mspResult_e mspProcessInCommand(mspDescriptor_t srcDesc, int16_t cmdMSP, currentControlRateProfile->rates_type = sbufReadU8(src); } + // version 1.47 + if (sbufBytesRemaining(src) >= 1) { + currentControlRateProfile->thrHover8 = sbufReadU8(src); + } + initRcProcessing(); } else { return MSP_RESULT_ERROR; diff --git a/src/test/unit/rc_controls_unittest.cc b/src/test/unit/rc_controls_unittest.cc index 7120aa97d8..cf16c68aee 100644 --- a/src/test/unit/rc_controls_unittest.cc +++ b/src/test/unit/rc_controls_unittest.cc @@ -271,6 +271,7 @@ protected: .rate_limit = {0, 0, 0}, .profileName = "default", .quickRatesRcExpo = 0, + .thrHover8 = 0, }; channelRange_t fullRange = { @@ -292,6 +293,7 @@ protected: controlRateConfig.rcExpo[FD_PITCH] = 0; controlRateConfig.thrMid8 = 0; controlRateConfig.thrExpo8 = 0; + controlRateConfig.thrHover8 = 0; controlRateConfig.rcExpo[FD_YAW] = 0; controlRateConfig.rates[0] = 0; controlRateConfig.rates[1] = 0; @@ -376,6 +378,7 @@ TEST_F(RcControlsAdjustmentsTest, processRcAdjustmentsWithRcRateFunctionSwitchUp .rate_limit = {0, 0, 0}, .profileName = "default", .quickRatesRcExpo = 0, + .thrHover8 = 0, }; // and From b2c939e899a6acc20995c1fa020e34177a1f8278 Mon Sep 17 00:00:00 2001 From: hhhh hgfh <118007458+Claucdan@users.noreply.github.com> Date: Fri, 11 Apr 2025 00:31:06 +0300 Subject: [PATCH 162/244] Add Launch Timer (#14332) * feat: add launch timer to osd timer type * fix: fix code style * Update src/main/osd/osd.c fix: code style Co-authored-by: Mark Haslinghuis * Update src/main/osd/osd.c fix: adding a comma after "LAUNCH TIME" Co-authored-by: Jan Post * Update src/main/osd/osd.c fix: added free space Co-authored-by: Jan Post * Update src/main/osd/osd.h fix: added free space after declaration Co-authored-by: Jan Post * Update src/main/osd/osd.c fix: added timer reset when switching to LAUNCH mode again Co-authored-by: Jan Post --------- Co-authored-by: Mark Haslinghuis Co-authored-by: Jan Post --- src/main/osd/osd.c | 12 +++++++++++- src/main/osd/osd.h | 5 ++++- src/main/osd/osd_elements.c | 4 ++++ 3 files changed, 19 insertions(+), 2 deletions(-) diff --git a/src/main/osd/osd.c b/src/main/osd/osd.c index 7e4ab9057b..0b2cbaef24 100644 --- a/src/main/osd/osd.c +++ b/src/main/osd/osd.c @@ -114,7 +114,8 @@ const char * const osdTimerSourceNames[] = { "ON TIME ", "TOTAL ARM", "LAST ARM ", - "ON/ARM " + "ON/ARM ", + "LAUNCH TIME", }; #define OSD_LOGO_ROWS 4 @@ -127,6 +128,8 @@ const char * const osdTimerSourceNames[] = { #define IS_MID(X) (rcData[X] > 1250 && rcData[X] < 1750) timeUs_t osdFlyTime = 0; +timeUs_t osdLaunchTime = 0; + #if defined(USE_ACC) float osdGForce = 0; #endif @@ -1243,6 +1246,13 @@ STATIC_UNIT_TESTED bool osdProcessStats1(timeUs_t currentTimeUs) timeUs_t deltaT = currentTimeUs - lastTimeUs; osdFlyTime += deltaT; stats.armed_time += deltaT; +#ifdef USE_LAUNCH_CONTROL + if (!isLaunchControlActive()) { + osdLaunchTime += deltaT; + } else { + osdLaunchTime = 0; + } +#endif } else if (osdStatsEnabled) { // handle showing/hiding stats based on OSD disable switch position if (displayIsGrabbed(osdDisplayPort)) { osdStatsEnabled = false; diff --git a/src/main/osd/osd.h b/src/main/osd/osd.h index c311bb1f45..eabb04d543 100644 --- a/src/main/osd/osd.h +++ b/src/main/osd/osd.h @@ -29,7 +29,7 @@ #include "sensors/esc_sensor.h" -#define OSD_NUM_TIMER_TYPES 4 +#define OSD_NUM_TIMER_TYPES 5 extern const char * const osdTimerSourceNames[OSD_NUM_TIMER_TYPES]; #define OSD_ELEMENT_BUFFER_LENGTH 32 @@ -257,6 +257,7 @@ typedef enum { OSD_TIMER_SRC_TOTAL_ARMED, OSD_TIMER_SRC_LAST_ARMED, OSD_TIMER_SRC_ON_OR_ARMED, + OSD_TIMER_SRC_LAUNCH_TIME, OSD_TIMER_SRC_COUNT } osd_timer_source_e; @@ -392,6 +393,8 @@ typedef struct statistic_s { extern timeUs_t resumeRefreshAt; extern timeUs_t osdFlyTime; +extern timeUs_t osdLaunchTime; + #if defined(USE_ACC) extern float osdGForce; #endif diff --git a/src/main/osd/osd_elements.c b/src/main/osd/osd_elements.c index 07844d0ea2..64bae571c1 100644 --- a/src/main/osd/osd_elements.c +++ b/src/main/osd/osd_elements.c @@ -515,6 +515,8 @@ static char osdGetTimerSymbol(osd_timer_source_e src) return SYM_FLY_M; case OSD_TIMER_SRC_ON_OR_ARMED: return ARMING_FLAG(ARMED) ? SYM_FLY_M : SYM_ON_M; + case OSD_TIMER_SRC_LAUNCH_TIME: + return 'L'; default: return ' '; } @@ -533,6 +535,8 @@ static timeUs_t osdGetTimerValue(osd_timer_source_e src) } case OSD_TIMER_SRC_ON_OR_ARMED: return ARMING_FLAG(ARMED) ? osdFlyTime : micros(); + case OSD_TIMER_SRC_LAUNCH_TIME: + return osdLaunchTime; default: return 0; } From 21dec1d7643d7887dc42d39ed77e4f5c7e3ea986 Mon Sep 17 00:00:00 2001 From: "Git bot (blckmn)" Date: Fri, 11 Apr 2025 06:25:03 +0000 Subject: [PATCH 163/244] Auto updated submodule references [11-04-2025] --- src/config | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/config b/src/config index 467f87b950..d7bf978fc6 160000 --- a/src/config +++ b/src/config @@ -1 +1 @@ -Subproject commit 467f87b950f406bd34e0075ac2438a2e06f5ed63 +Subproject commit d7bf978fc6168f798c0281eb08ff39b2fbf1e0fe From 38007f8b597f28ae354e54321f869b938c8b7e07 Mon Sep 17 00:00:00 2001 From: Thisas <59698123+The-Real-Thisas@users.noreply.github.com> Date: Fri, 11 Apr 2025 22:13:09 +0400 Subject: [PATCH 164/244] Fix SITL for MacOS M1 (#14284) * Fix SITL for MacOS M1 * move macos m1 SITL fix into SITL.mk and extract warnings flags from cflags into WARNING_FLAGS varible * add back -Werror * add warning about potencial issues with PG on SITL builds for MacOS apple silicon * removed override and added CFLAGS_DISABLED and OPTIMISATION_DISABLED * change OPTIMISATION_DISABLED to OPTIMISATIONS_DISABLED and also use it for CC_DEBUG_OPTIMISATION * fix building useless hex * copy instead of move * clean new artifacts from SITL * fix clean * fix issue where in SITL_STATIC will build properly * building static does not seem to work on macos * building static does not seem to work on macos * building static is not possible on macos * fix issue where make TARGET=SITL still builds hex * Move everything to CFLAGS_DISABLED and use else if chaning * add SITL to CI_TARGETS * add rev to SITL * add changes suggested by ledvinap * Update Makefile Co-authored-by: Mark Haslinghuis * Update src/platform/SIMULATOR/mk/SITL.mk * Add EXE_TARGET_REVISION --------- Co-authored-by: Mark Haslinghuis --- Makefile | 48 ++++++++++++++++++++++++++----- src/platform/SIMULATOR/mk/SITL.mk | 25 +++++++++++++--- 2 files changed, 62 insertions(+), 11 deletions(-) diff --git a/Makefile b/Makefile index d7e2136d4e..456dc49dbc 100644 --- a/Makefile +++ b/Makefile @@ -15,7 +15,7 @@ # Things that the user might override on the commandline # -# The target to build, see BASE_TARGETS below +# The target to build, see BASE_TARGETS/EXE_TARGETS below TARGET ?= CONFIG ?= @@ -47,6 +47,9 @@ SERIAL_DEVICE ?= $(firstword $(wildcard /dev/ttyACM*) $(firstword $(wildcard / # Flash size (KB). Some low-end chips actually have more flash than advertised, use this to override. FLASH_SIZE ?= +# Disabled build flags +CFLAGS_DISABLED := + ############################################################################### # Things that need to be maintained as the source changes # @@ -87,9 +90,12 @@ MAKE_PARALLEL = $(if $(filter -j%, $(MAKEFLAGS)),$(EMPTY),-j$(DEFAULT_PAR # pre-build sanity checks include $(MAKE_SCRIPT_DIR)/checks.mk +# list of targets that are executed on host (using exe as goal) +EXE_TARGETS := SITL + # basic target list PLATFORMS := $(sort $(notdir $(patsubst /%,%, $(wildcard $(PLATFORM_DIR)/*)))) -BASE_TARGETS := $(sort $(notdir $(patsubst %/,%,$(dir $(wildcard $(PLATFORM_DIR)/*/target/*/target.mk))))) +BASE_TARGETS := $(filter-out $(EXE_TARGETS),$(sort $(notdir $(patsubst %/,%,$(dir $(wildcard $(PLATFORM_DIR)/*/target/*/target.mk)))))) # configure some directories that are relative to wherever ROOT_DIR is located TOOLS_DIR ?= $(ROOT)/tools @@ -128,7 +134,7 @@ HSE_VALUE ?= 8000000 CI_EXCLUDED_TARGETS := $(sort $(notdir $(patsubst %/,%,$(dir $(wildcard $(PLATFORM_DIR)/*/target/*/.exclude))))) CI_COMMON_TARGETS := STM32F4DISCOVERY CRAZYBEEF4SX1280 CRAZYBEEF4FR MATEKF405TE AIRBOTG4AIO TBS_LUCID_FC IFLIGHT_BLITZ_F722 NUCLEOF446 SPRACINGH7EXTREME SPRACINGH7RF -CI_TARGETS := $(filter-out $(CI_EXCLUDED_TARGETS), $(BASE_TARGETS)) $(filter $(CI_COMMON_TARGETS), $(BASE_CONFIGS)) +CI_TARGETS := $(filter-out $(CI_EXCLUDED_TARGETS), $(BASE_TARGETS) $(EXE_TARGETS)) $(filter $(CI_COMMON_TARGETS), $(BASE_CONFIGS)) PREVIEW_TARGETS := MATEKF411 AIKONF4V2 AIRBOTG4AIO ZEEZF7V3 FOXEERF745V4_AIO KAKUTEH7 TBS_LUCID_FC SITL SPRACINGH7EXTREME SPRACINGH7RF TARGET_PLATFORM := $(notdir $(patsubst %/,%,$(subst target/$(TARGET)/,, $(dir $(wildcard $(PLATFORM_DIR)/*/target/$(TARGET)/target.mk))))) @@ -224,10 +230,12 @@ include $(MAKE_SCRIPT_DIR)/openocd.mk ifeq ($(CONFIG),) ifeq ($(TARGET),) .DEFAULT_GOAL := all +else ifneq ($(filter $(TARGET),$(EXE_TARGETS)),) +.DEFAULT_GOAL := exe else .DEFAULT_GOAL := hex endif -else +else # ifeq ($(CONFIG),) .DEFAULT_GOAL := hex endif @@ -281,6 +289,12 @@ CC_SPEED_OPTIMISATION := $(OPTIMISATION_BASE) $(OPTIMISE_SPEED) CC_SIZE_OPTIMISATION := $(OPTIMISATION_BASE) $(OPTIMISE_SIZE) CC_NO_OPTIMISATION := +CC_DEBUG_OPTIMISATION := $(filter-out $(CFLAGS_DISABLED), $(CC_DEBUG_OPTIMISATION)) +CC_DEFAULT_OPTIMISATION := $(filter-out $(CFLAGS_DISABLED), $(CC_DEFAULT_OPTIMISATION)) +CC_SPEED_OPTIMISATION := $(filter-out $(CFLAGS_DISABLED), $(CC_SPEED_OPTIMISATION)) +CC_SIZE_OPTIMISATION := $(filter-out $(CFLAGS_DISABLED), $(CC_SIZE_OPTIMISATION)) +CC_NO_OPTIMISATION := $(filter-out $(CFLAGS_DISABLED), $(CC_NO_OPTIMISATION)) + # # Added after GCC version update, remove once the warnings have been fixed # @@ -311,6 +325,8 @@ CFLAGS += $(ARCH_FLAGS) \ -MMD -MP \ $(EXTRA_FLAGS) +CFLAGS := $(filter-out $(CFLAGS_DISABLED), $(CFLAGS)) + ASFLAGS = $(ARCH_FLAGS) \ $(DEBUG_FLAGS) \ -x assembler-with-cpp \ @@ -361,6 +377,7 @@ TARGET_FULLNAME = $(FORKNAME)_$(FC_VER)_$(TARGET_NAME) # TARGET_BIN = $(BIN_DIR)/$(TARGET_FULLNAME).bin TARGET_HEX = $(BIN_DIR)/$(TARGET_FULLNAME).hex +TARGET_EXE = $(BIN_DIR)/$(TARGET_FULLNAME) TARGET_DFU = $(BIN_DIR)/$(TARGET_FULLNAME).dfu TARGET_ZIP = $(BIN_DIR)/$(TARGET_FULLNAME).zip TARGET_OBJ_DIR = $(OBJECT_DIR)/$(TARGET_NAME) @@ -462,6 +479,10 @@ $(TARGET_ELF): $(TARGET_OBJS) $(LD_SCRIPT) $(LD_SCRIPTS) $(V1) $(CROSS_CC) -o $@ $(filter-out %.ld,$^) $(LD_FLAGS) $(V1) $(SIZE) $(TARGET_ELF) +$(TARGET_EXE): $(TARGET_ELF) + @echo Copy $< to $@ "$(STDOUT)" + $(V1) cp $< $@ + # Compile ## compile_file takes two arguments: (1) optimisation description string and (2) optimisation compiler flag @@ -512,7 +533,6 @@ $(TARGET_OBJ_DIR)/%.o: %.S @echo "%% $(notdir $<)" "$(STDOUT)" $(V1) $(CROSS_CC) -c -o $@ $(ASFLAGS) $< - ## all : Build all currently built targets all: $(CI_TARGETS) @@ -521,7 +541,12 @@ $(BASE_TARGETS): $(MAKE) hex TARGET=$@ && \ echo "Building $@ succeeded." -TARGETS_CLEAN = $(addsuffix _clean,$(BASE_TARGETS)) +$(EXE_TARGETS): + $(V0) @echo "Building executable target $@" && \ + $(MAKE) exe TARGET=$@ && \ + echo "Building $@ succeeded." + +TARGETS_CLEAN = $(addsuffix _clean,$(BASE_TARGETS) $(EXE_TARGETS)) CONFIGS_CLEAN = $(addsuffix _clean,$(BASE_CONFIGS)) @@ -610,11 +635,19 @@ binary: hex: $(V0) $(MAKE) $(MAKE_PARALLEL) $(TARGET_HEX) +.phony: exe +exe: $(TARGET_EXE) + TARGETS_REVISION = $(addsuffix _rev,$(BASE_TARGETS)) ## _rev : build target and add revision to filename $(TARGETS_REVISION): $(V0) $(MAKE) hex REV=yes TARGET=$(subst _rev,,$@) +EXE_TARGETS_REVISION = $(addsuffix _rev,$(EXE_TARGETS)) +## _rev : build executable target and add revision to filename +$(EXE_TARGETS_REVISION): + $(V0) $(MAKE) exe REV=yes TARGET=$(subst _rev,,$@) + all_rev: $(addsuffix _rev,$(CI_TARGETS)) unbrick_$(TARGET): $(TARGET_HEX) @@ -654,7 +687,7 @@ help: Makefile mk/tools.mk @echo "To populate configuration targets:" @echo " make configs" @echo "" - @echo "Valid TARGET values are: $(BASE_TARGETS)" + @echo "Valid TARGET values are: $(EXE_TARGETS) $(BASE_TARGETS)" @echo "" @sed -n 's/^## //p' $? @@ -662,6 +695,7 @@ help: Makefile mk/tools.mk targets: @echo "Platforms: $(PLATFORMS)" @echo "Valid targets: $(BASE_TARGETS)" + @echo "Executable targets: $(EXE_TARGETS)" @echo "Built targets: $(CI_TARGETS)" @echo "Default target: $(TARGET)" @echo "CI common targets: $(CI_COMMON_TARGETS)" diff --git a/src/platform/SIMULATOR/mk/SITL.mk b/src/platform/SIMULATOR/mk/SITL.mk index 001255826e..989306556f 100644 --- a/src/platform/SIMULATOR/mk/SITL.mk +++ b/src/platform/SIMULATOR/mk/SITL.mk @@ -30,11 +30,11 @@ MCU_EXCLUDES = \ TARGET_MAP = $(OBJECT_DIR)/$(FORKNAME)_$(TARGET).map +LIBS = -lm -lpthread -lc -lrt + +# overriden on Apple silicon macosx LD_FLAGS := \ - -lm \ - -lpthread \ - -lc \ - -lrt \ + $(LIBS) \ $(ARCH_FLAGS) \ $(LTO_FLAGS) \ $(DEBUG_FLAGS) \ @@ -56,3 +56,20 @@ OPTIMISE_SIZE := -Os LTO_FLAGS := $(OPTIMISATION_BASE) $(OPTIMISE_SPEED) endif + +ifneq ($(filter macosx-arm%,$(OSFAMILY)-$(ARCHFAMILY)),) + + CFLAGS_DISABLED := -Werror -Wunsafe-loop-optimizations -fuse-linker-plugin + + ifneq ($(filter SITL_STATIC,$(OPTIONS)),) + $(error Static builds are not supported on MacOS) + endif + + # This removes the linker script for MacOS apple silicon builds and may cause issues with PG. + LD_FLAGS := \ + $(filter-out -lrt, $(LIBS)) \ + $(ARCH_FLAGS) \ + $(LTO_FLAGS) \ + $(DEBUG_FLAGS) \ + -Wl,-map,$(TARGET_MAP) +endif From 9e73f08e34fb9e09102024ecae76636dc8163d7d Mon Sep 17 00:00:00 2001 From: Steve Evans Date: Sat, 12 Apr 2025 07:00:03 +0100 Subject: [PATCH 165/244] Properly handle USE_BARO_LPS22DF (#14340) --- src/main/sensors/barometer.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/main/sensors/barometer.c b/src/main/sensors/barometer.c index 9e375a6f47..ed73ba7278 100644 --- a/src/main/sensors/barometer.c +++ b/src/main/sensors/barometer.c @@ -143,7 +143,7 @@ void pgResetFn_barometerConfig(barometerConfig_t *barometerConfig) barometerConfig->baro_spi_csn = IO_TAG(BARO_CS_PIN); barometerConfig->baro_i2c_device = I2C_DEV_TO_CFG(I2CINVALID); barometerConfig->baro_i2c_address = 0; -#elif defined(DEFAULT_BARO_MS5611) || defined(DEFAULT_BARO_BMP388) || defined(DEFAULT_BARO_BMP280) || defined(DEFAULT_BARO_BMP085) ||defined(DEFAULT_BARO_QMP6988) || defined(DEFAULT_BARO_DPS310) || defined(DEFAULT_BARO_2SMBP_02B) +#elif defined(DEFAULT_BARO_MS5611) || defined(DEFAULT_BARO_BMP388) || defined(DEFAULT_BARO_BMP280) || defined(DEFAULT_BARO_BMP085) ||defined(DEFAULT_BARO_QMP6988) || defined(DEFAULT_BARO_DPS310) || defined(DEFAULT_BARO_2SMBP_02B) || defined(USE_BARO_LPS22DF) // All I2C devices shares a default config with address = 0 (per device default) barometerConfig->baro_busType = BUS_TYPE_I2C; barometerConfig->baro_i2c_device = I2C_DEV_TO_CFG(BARO_I2C_INSTANCE); @@ -193,7 +193,7 @@ static bool baroDetect(baroDev_t *baroDev, baroSensor_e baroHardwareToUse) baroSensor_e baroHardware = baroHardwareToUse; -#if !defined(USE_BARO_BMP085) && !defined(USE_BARO_MS5611) && !defined(USE_BARO_SPI_MS5611) && !defined(USE_BARO_BMP388) && !defined(USE_BARO_BMP280) && !defined(USE_BARO_SPI_BMP280)&& !defined(USE_BARO_QMP6988) && !defined(USE_BARO_SPI_QMP6988) && !defined(USE_BARO_DPS310) && !defined(USE_BARO_SPI_DPS310) && !defined(DEFAULT_BARO_SPI_2SMBP_02B) && !defined(DEFAULT_BARO_2SMBP_02B) +#if !defined(USE_BARO_BMP085) && !defined(USE_BARO_MS5611) && !defined(USE_BARO_SPI_MS5611) && !defined(USE_BARO_BMP388) && !defined(USE_BARO_BMP280) && !defined(USE_BARO_SPI_BMP280)&& !defined(USE_BARO_QMP6988) && !defined(USE_BARO_SPI_QMP6988) && !defined(USE_BARO_DPS310) && !defined(USE_BARO_SPI_DPS310) && !defined(DEFAULT_BARO_SPI_2SMBP_02B) && !defined(DEFAULT_BARO_2SMBP_02B) && !defined(USE_BARO_LPS22DF) UNUSED(dev); #endif From 2b1566b2f06aff1269c5adcc22d5bf28fc92fd3c Mon Sep 17 00:00:00 2001 From: "Git bot (blckmn)" Date: Sat, 12 Apr 2025 06:25:03 +0000 Subject: [PATCH 166/244] Auto updated submodule references [12-04-2025] --- src/config | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/config b/src/config index d7bf978fc6..d01892da28 160000 --- a/src/config +++ b/src/config @@ -1 +1 @@ -Subproject commit d7bf978fc6168f798c0281eb08ff39b2fbf1e0fe +Subproject commit d01892da28fb33274941b10fbf2f92e6f033305c From 9f18593be7f88a50cbb3bcc40b0b5a3502b40cc7 Mon Sep 17 00:00:00 2001 From: "Git bot (blckmn)" Date: Tue, 15 Apr 2025 06:25:03 +0000 Subject: [PATCH 167/244] Auto updated submodule references [15-04-2025] --- src/config | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/config b/src/config index d01892da28..8f1c5a32b7 160000 --- a/src/config +++ b/src/config @@ -1 +1 @@ -Subproject commit d01892da28fb33274941b10fbf2f92e6f033305c +Subproject commit 8f1c5a32b71d8ffeac5a7facc43147fd60adfdc1 From 9eb7d1920be06ab9fb1e25f6febfc813995038c4 Mon Sep 17 00:00:00 2001 From: Alex Klimaj Date: Tue, 15 Apr 2025 04:15:15 -0600 Subject: [PATCH 168/244] STM32H7 add UART4 pins (#14341) * stm32h7: add uart4 ph13 and ph14 * stm32h7: increase UARTHARDWARE_MAX_PINS * Update src/platform/STM32/serial_uart_stm32h7xx.c Co-authored-by: Petr Ledvina * Update src/platform/STM32/serial_uart_stm32h7xx.c Co-authored-by: Petr Ledvina --------- Co-authored-by: Mark Haslinghuis Co-authored-by: Petr Ledvina --- src/platform/STM32/platform_mcu.h | 2 +- src/platform/STM32/serial_uart_stm32h7xx.c | 7 +++++-- 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/src/platform/STM32/platform_mcu.h b/src/platform/STM32/platform_mcu.h index 9dd2114b98..f8c2e75d80 100644 --- a/src/platform/STM32/platform_mcu.h +++ b/src/platform/STM32/platform_mcu.h @@ -399,7 +399,7 @@ extern uint8_t _dmaram_end__; #elif defined(STM32F7) #define UARTHARDWARE_MAX_PINS 4 #elif defined(STM32H7) -#define UARTHARDWARE_MAX_PINS 5 +#define UARTHARDWARE_MAX_PINS 6 #elif defined(STM32G4) #define UARTHARDWARE_MAX_PINS 3 #endif diff --git a/src/platform/STM32/serial_uart_stm32h7xx.c b/src/platform/STM32/serial_uart_stm32h7xx.c index c892077b85..bbed4b6ed0 100644 --- a/src/platform/STM32/serial_uart_stm32h7xx.c +++ b/src/platform/STM32/serial_uart_stm32h7xx.c @@ -207,14 +207,17 @@ const uartHardware_t uartHardware[UARTDEV_COUNT] = { { DEFIO_TAG_E(PA11), GPIO_AF6_UART4 }, { DEFIO_TAG_E(PB8), GPIO_AF8_UART4 }, { DEFIO_TAG_E(PC11), GPIO_AF8_UART4 }, - { DEFIO_TAG_E(PD0), GPIO_AF8_UART4 } + { DEFIO_TAG_E(PD0), GPIO_AF8_UART4 }, + { DEFIO_TAG_E(PH14), GPIO_AF8_UART4 }, + }, .txPins = { { DEFIO_TAG_E(PA0), GPIO_AF8_UART4 }, { DEFIO_TAG_E(PA12), GPIO_AF6_UART4 }, { DEFIO_TAG_E(PB9), GPIO_AF8_UART4 }, { DEFIO_TAG_E(PC10), GPIO_AF8_UART4 }, - { DEFIO_TAG_E(PD1), GPIO_AF8_UART4 } + { DEFIO_TAG_E(PD1), GPIO_AF8_UART4 }, + { DEFIO_TAG_E(PH13), GPIO_AF8_UART4 }, }, .rcc = RCC_APB1L(UART4), .irqn = UART4_IRQn, From f336df392e3d89a84e34dce2c2b3f597ae0d2cdd Mon Sep 17 00:00:00 2001 From: "Git bot (blckmn)" Date: Wed, 16 Apr 2025 06:25:03 +0000 Subject: [PATCH 169/244] Auto updated submodule references [16-04-2025] --- src/config | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/config b/src/config index 8f1c5a32b7..b9f4b9fbf6 160000 --- a/src/config +++ b/src/config @@ -1 +1 @@ -Subproject commit 8f1c5a32b71d8ffeac5a7facc43147fd60adfdc1 +Subproject commit b9f4b9fbf6152de333b552abff40057e03882f5d From 22f8b1b2b34492f5d9e7c4ea16f9286c10598ee1 Mon Sep 17 00:00:00 2001 From: "Git bot (blckmn)" Date: Thu, 17 Apr 2025 06:25:03 +0000 Subject: [PATCH 170/244] Auto updated submodule references [17-04-2025] --- src/config | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/config b/src/config index b9f4b9fbf6..dbdf60571a 160000 --- a/src/config +++ b/src/config @@ -1 +1 @@ -Subproject commit b9f4b9fbf6152de333b552abff40057e03882f5d +Subproject commit dbdf60571a9d1729890dfca3183a1f899d052ffb From 8657a6ae12fa4930bbf52b9622081b1fd51d9ff4 Mon Sep 17 00:00:00 2001 From: "Git bot (blckmn)" Date: Fri, 18 Apr 2025 06:25:02 +0000 Subject: [PATCH 171/244] Auto updated submodule references [18-04-2025] --- src/config | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/config b/src/config index dbdf60571a..049ac0d6b4 160000 --- a/src/config +++ b/src/config @@ -1 +1 @@ -Subproject commit dbdf60571a9d1729890dfca3183a1f899d052ffb +Subproject commit 049ac0d6b4a19e830733309347f5fa75f2ded967 From d6219861fba308c130577c80ba3e7ec62df9af4a Mon Sep 17 00:00:00 2001 From: Jay Blackman Date: Sat, 19 Apr 2025 20:31:15 +1000 Subject: [PATCH 172/244] REFACTOR: Remove unused drivers/dma.c file (#14346) Remove unused drivers/dma.c file --- src/main/drivers/dma.c | 101 ----------------------------------------- 1 file changed, 101 deletions(-) delete mode 100644 src/main/drivers/dma.c diff --git a/src/main/drivers/dma.c b/src/main/drivers/dma.c deleted file mode 100644 index 73f2626816..0000000000 --- a/src/main/drivers/dma.c +++ /dev/null @@ -1,101 +0,0 @@ -/* - * This file is part of Cleanflight and Betaflight. - * - * Cleanflight and Betaflight are free software. You can redistribute - * this software and/or modify this software under the terms of the - * GNU General Public License as published by the Free Software - * Foundation, either version 3 of the License, or (at your option) - * any later version. - * - * Cleanflight and Betaflight are distributed in the hope that they - * will be useful, but WITHOUT ANY WARRANTY; without even the implied - * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * See the GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this software. - * - * If not, see . - */ - -#include -#include -#include - -#include "platform.h" - -#ifdef USE_DMA - -#include "drivers/nvic.h" -#include "dma.h" - -/* - * DMA descriptors. - */ -dmaChannelDescriptor_t dmaDescriptors[DMA_LAST_HANDLER] = { - DEFINE_DMA_CHANNEL(DMA1, 1, 0), - DEFINE_DMA_CHANNEL(DMA1, 2, 4), - DEFINE_DMA_CHANNEL(DMA1, 3, 8), - DEFINE_DMA_CHANNEL(DMA1, 4, 12), - DEFINE_DMA_CHANNEL(DMA1, 5, 16), - DEFINE_DMA_CHANNEL(DMA1, 6, 20), - DEFINE_DMA_CHANNEL(DMA1, 7, 24), -}; - -/* - * DMA IRQ Handlers - */ - -DEFINE_DMA_IRQ_HANDLER(1, 1, DMA1_CH1_HANDLER) -DEFINE_DMA_IRQ_HANDLER(1, 2, DMA1_CH2_HANDLER) -DEFINE_DMA_IRQ_HANDLER(1, 3, DMA1_CH3_HANDLER) -DEFINE_DMA_IRQ_HANDLER(1, 4, DMA1_CH4_HANDLER) -DEFINE_DMA_IRQ_HANDLER(1, 5, DMA1_CH5_HANDLER) -DEFINE_DMA_IRQ_HANDLER(1, 6, DMA1_CH6_HANDLER) -DEFINE_DMA_IRQ_HANDLER(1, 7, DMA1_CH7_HANDLER) - -#define RETURN_TCIF_FLAG(s, d, n) if (s == DMA ## d ## _Channel ## n) return DMA ## d ## _FLAG_TC ## n - -uint32_t dmaFlag_IT_TCIF(const dmaResource_t *channel) -{ - RETURN_TCIF_FLAG((DMA_ARCH_TYPE *)channel, 1, 1); - RETURN_TCIF_FLAG((DMA_ARCH_TYPE *)channel, 1, 2); - RETURN_TCIF_FLAG((DMA_ARCH_TYPE *)channel, 1, 3); - RETURN_TCIF_FLAG((DMA_ARCH_TYPE *)channel, 1, 4); - RETURN_TCIF_FLAG((DMA_ARCH_TYPE *)channel, 1, 5); - RETURN_TCIF_FLAG((DMA_ARCH_TYPE *)channel, 1, 6); - RETURN_TCIF_FLAG((DMA_ARCH_TYPE *)channel, 1, 7); - RETURN_TCIF_FLAG((DMA_ARCH_TYPE *)channel, 2, 1); - RETURN_TCIF_FLAG((DMA_ARCH_TYPE *)channel, 2, 2); - RETURN_TCIF_FLAG((DMA_ARCH_TYPE *)channel, 2, 3); - RETURN_TCIF_FLAG((DMA_ARCH_TYPE *)channel, 2, 4); - RETURN_TCIF_FLAG((DMA_ARCH_TYPE *)channel, 2, 5); - return 0; -} - -#define DMA_RCC(x) ((x) == DMA1 ? RCC_AHBPeriph_DMA1 : RCC_AHBPeriph_DMA2) -void dmaEnable(dmaIdentifier_e identifier) -{ - const int index = DMA_IDENTIFIER_TO_INDEX(identifier); - - RCC_AHBPeriphClockCmd(DMA_RCC(dmaDescriptors[index].dma), ENABLE); -} - -void dmaSetHandler(dmaIdentifier_e identifier, dmaCallbackHandlerFuncPtr callback, uint32_t priority, uint32_t userParam) -{ - NVIC_InitTypeDef NVIC_InitStructure; - - const int index = DMA_IDENTIFIER_TO_INDEX(identifier); - /* TODO: remove this - enforce the init */ - RCC_AHBPeriphClockCmd(DMA_RCC(dmaDescriptors[index].dma), ENABLE); - dmaDescriptors[index].irqHandlerCallback = callback; - dmaDescriptors[index].userParam = userParam; - dmaDescriptors[index].completeFlag = dmaFlag_IT_TCIF(dmaDescriptors[index].ref); - - NVIC_InitStructure.NVIC_IRQChannel = dmaDescriptors[index].irqN; - NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = NVIC_PRIORITY_BASE(priority); - NVIC_InitStructure.NVIC_IRQChannelSubPriority = NVIC_PRIORITY_SUB(priority); - NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; - NVIC_Init(&NVIC_InitStructure); -} -#endif From 1abe5f93ea158de599dc715593658a62668844c7 Mon Sep 17 00:00:00 2001 From: "Git bot (blckmn)" Date: Tue, 22 Apr 2025 06:25:03 +0000 Subject: [PATCH 173/244] Auto updated submodule references [22-04-2025] --- src/config | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/config b/src/config index 049ac0d6b4..3029a1e695 160000 --- a/src/config +++ b/src/config @@ -1 +1 @@ -Subproject commit 049ac0d6b4a19e830733309347f5fa75f2ded967 +Subproject commit 3029a1e695a43eab7101f65aaa243840cd8d678e From 66c33f4c657ace9154e52f1f3393e88277d0bcf7 Mon Sep 17 00:00:00 2001 From: "Git bot (blckmn)" Date: Wed, 23 Apr 2025 06:25:03 +0000 Subject: [PATCH 174/244] Auto updated submodule references [23-04-2025] --- src/config | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/config b/src/config index 3029a1e695..ad70d2a88f 160000 --- a/src/config +++ b/src/config @@ -1 +1 @@ -Subproject commit 3029a1e695a43eab7101f65aaa243840cd8d678e +Subproject commit ad70d2a88ff301173fc9e2b57c298b472a978848 From eb7814d1970dc791a5d821cb40c9e07c7e00acc0 Mon Sep 17 00:00:00 2001 From: Mark Haslinghuis Date: Wed, 23 Apr 2025 12:04:19 +0200 Subject: [PATCH 175/244] Add variant for RTC OSD element (#14344) * Add variant for RTC OSD element * Update src/main/osd/osd_elements.c Co-authored-by: Petr Ledvina * Be more explicit :) Co-authored-by: Petr Ledvina --------- Co-authored-by: Petr Ledvina --- src/main/osd/osd_elements.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/src/main/osd/osd_elements.c b/src/main/osd/osd_elements.c index 64bae571c1..4b9aa162f4 100644 --- a/src/main/osd/osd_elements.c +++ b/src/main/osd/osd_elements.c @@ -473,7 +473,15 @@ bool osdFormatRtcDateTime(char *buffer) return false; } - dateTimeFormatLocalShort(buffer, &dateTime); + switch (activeElement.type) { + case OSD_ELEMENT_TYPE_2: + tfp_sprintf(buffer, "%02d.%02d %02d:%02d", dateTime.month, dateTime.day, dateTime.hours, dateTime.minutes); + break; + case OSD_ELEMENT_TYPE_1: + default: + dateTimeFormatLocalShort(buffer, &dateTime); + break; + } return true; } From d6966be79f8297635c757b2fc90fb2e0d3a5034d Mon Sep 17 00:00:00 2001 From: mjs1441 Date: Wed, 23 Apr 2025 17:27:44 +0100 Subject: [PATCH 176/244] REFACTOR: SPI segment handling (#14345) * Move common code (spiIrqHandler) from src/platform/common/stm32/ to src/main/drivers/bus_spi.c * Move repeated code from inside spiSequenceStart to bus_spi.c as spiProcessSegmentsDMA, spiProcessSegmentsPolled * spiInternalReadWriteBufPolled becomes non-static Co-authored-by: Matthew Selby --- src/main/drivers/bus_spi.c | 153 +++++++++++++++++++++++++ src/main/drivers/bus_spi.h | 7 ++ src/main/drivers/bus_spi_impl.h | 1 + src/platform/APM32/bus_spi_apm32.c | 71 +----------- src/platform/AT32/bus_spi_at32bsp.c | 70 +---------- src/platform/STM32/bus_spi_ll.c | 71 +----------- src/platform/STM32/bus_spi_stdperiph.c | 71 +----------- src/platform/common/stm32/bus_spi_hw.c | 74 ------------ 8 files changed, 173 insertions(+), 345 deletions(-) diff --git a/src/main/drivers/bus_spi.c b/src/main/drivers/bus_spi.c index 5cb2359c11..615470aeb4 100644 --- a/src/main/drivers/bus_spi.c +++ b/src/main/drivers/bus_spi.c @@ -485,4 +485,157 @@ void spiSequence(const extDevice_t *dev, busSegment_t *segments) spiSequenceStart(dev); } + +// Process segments using DMA - expects DMA irq handler to have been set up to feed into spiIrqHandler. +FAST_CODE void spiProcessSegmentsDMA(const extDevice_t *dev) +{ + // Intialise the init structures for the first transfer + spiInternalInitStream(dev, false); + + // Assert Chip Select + IOLo(dev->busType_u.spi.csnPin); + + // Start the transfers + spiInternalStartDMA(dev); +} + +// Interrupt handler common code for SPI receive DMA completion. +// Proceed to next segment as required. +FAST_IRQ_HANDLER void spiIrqHandler(const extDevice_t *dev) +{ + busDevice_t *bus = dev->bus; + busSegment_t *nextSegment; + + if (bus->curSegment->callback) { + switch(bus->curSegment->callback(dev->callbackArg)) { + case BUS_BUSY: + // Repeat the last DMA segment + bus->curSegment--; + // Reinitialise the cached init values as segment is not progressing + spiInternalInitStream(dev, true); + break; + + case BUS_ABORT: + // Skip to the end of the segment list + nextSegment = (busSegment_t *)bus->curSegment + 1; + while (nextSegment->len != 0) { + bus->curSegment = nextSegment; + nextSegment = (busSegment_t *)bus->curSegment + 1; + } + break; + + case BUS_READY: + default: + // Advance to the next DMA segment + break; + } + } + + // Advance through the segment list + // OK to discard the volatile qualifier here + nextSegment = (busSegment_t *)bus->curSegment + 1; + + if (nextSegment->len == 0) { + // If a following transaction has been linked, start it + if (nextSegment->u.link.dev) { + const extDevice_t *nextDev = nextSegment->u.link.dev; + busSegment_t *nextSegments = (busSegment_t *)nextSegment->u.link.segments; + // The end of the segment list has been reached + bus->curSegment = nextSegments; + nextSegment->u.link.dev = NULL; + nextSegment->u.link.segments = NULL; + spiSequenceStart(nextDev); + } else { + // The end of the segment list has been reached, so mark transactions as complete + bus->curSegment = (busSegment_t *)BUS_SPI_FREE; + } + } else { + // Do as much processing as possible before asserting CS to avoid violating minimum high time + bool negateCS = bus->curSegment->negateCS; + + bus->curSegment = nextSegment; + + // After the completion of the first segment setup the init structure for the subsequent segment + if (bus->initSegment) { + spiInternalInitStream(dev, false); + bus->initSegment = false; + } + + if (negateCS) { + // Assert Chip Select - it's costly so only do so if necessary + IOLo(dev->busType_u.spi.csnPin); + } + + // Launch the next transfer + spiInternalStartDMA(dev); + + // Prepare the init structures ready for the next segment to reduce inter-segment time + spiInternalInitStream(dev, true); + } +} + +FAST_CODE void spiProcessSegmentsPolled(const extDevice_t *dev) +{ + busDevice_t *bus = dev->bus; + busSegment_t *lastSegment = NULL; + bool segmentComplete; + + // Manually work through the segment list performing a transfer for each + while (bus->curSegment->len) { + if (!lastSegment || lastSegment->negateCS) { + // Assert Chip Select if necessary - it's costly so only do so if necessary + IOLo(dev->busType_u.spi.csnPin); + } + + spiInternalReadWriteBufPolled( + bus->busType_u.spi.instance, + bus->curSegment->u.buffers.txData, + bus->curSegment->u.buffers.rxData, + bus->curSegment->len); + + if (bus->curSegment->negateCS) { + // Negate Chip Select + IOHi(dev->busType_u.spi.csnPin); + } + + segmentComplete = true; + if (bus->curSegment->callback) { + switch(bus->curSegment->callback(dev->callbackArg)) { + case BUS_BUSY: + // Repeat the last DMA segment + segmentComplete = false; + break; + + case BUS_ABORT: + bus->curSegment = (busSegment_t *)BUS_SPI_FREE; + segmentComplete = false; + return; + + case BUS_READY: + default: + // Advance to the next DMA segment + break; + } + } + if (segmentComplete) { + lastSegment = (busSegment_t *)bus->curSegment; + bus->curSegment++; + } + } + + // If a following transaction has been linked, start it + if (bus->curSegment->u.link.dev) { + busSegment_t *endSegment = (busSegment_t *)bus->curSegment; + const extDevice_t *nextDev = endSegment->u.link.dev; + busSegment_t *nextSegments = (busSegment_t *)endSegment->u.link.segments; + bus->curSegment = nextSegments; + endSegment->u.link.dev = NULL; + endSegment->u.link.segments = NULL; + spiSequenceStart(nextDev); + } else { + // The end of the segment list has been reached, so mark transactions as complete + bus->curSegment = (busSegment_t *)BUS_SPI_FREE; + } +} + #endif diff --git a/src/main/drivers/bus_spi.h b/src/main/drivers/bus_spi.h index 5723b6202c..f592aa19ee 100644 --- a/src/main/drivers/bus_spi.h +++ b/src/main/drivers/bus_spi.h @@ -140,3 +140,10 @@ bool spiUseSDO_DMA(const extDevice_t *dev); void spiBusDeviceRegister(const extDevice_t *dev); uint8_t spiGetRegisteredDeviceCount(void); uint8_t spiGetExtDeviceCount(const extDevice_t *dev); + +// Common code to process linked segments, to be called from spiSequenceStart. +// DMA path makes use of spiInternalInitStream, spiInternalStartDMA. +void spiProcessSegmentsDMA(const extDevice_t *dev); +void spiIrqHandler(const extDevice_t *dev); +// Polling code calls spiInternalReadWriteBufPolled. +void spiProcessSegmentsPolled(const extDevice_t *dev); diff --git a/src/main/drivers/bus_spi_impl.h b/src/main/drivers/bus_spi_impl.h index c75c117c65..cccca9a73d 100644 --- a/src/main/drivers/bus_spi_impl.h +++ b/src/main/drivers/bus_spi_impl.h @@ -79,4 +79,5 @@ void spiInternalStartDMA(const extDevice_t *dev); void spiInternalStopDMA (const extDevice_t *dev); void spiInternalResetStream(dmaChannelDescriptor_t *descriptor); void spiInternalResetDescriptors(busDevice_t *bus); +bool spiInternalReadWriteBufPolled(SPI_TypeDef *instance, const uint8_t *txData, uint8_t *rxData, int len); void spiSequenceStart(const extDevice_t *dev); diff --git a/src/platform/APM32/bus_spi_apm32.c b/src/platform/APM32/bus_spi_apm32.c index 43e215851f..6b15adf29d 100644 --- a/src/platform/APM32/bus_spi_apm32.c +++ b/src/platform/APM32/bus_spi_apm32.c @@ -138,7 +138,7 @@ void spiInternalResetStream(dmaChannelDescriptor_t *descriptor) DMA_CLEAR_FLAG(descriptor, DMA_IT_HTIF | DMA_IT_TEIF | DMA_IT_TCIF); } -FAST_CODE static bool spiInternalReadWriteBufPolled(SPI_TypeDef *instance, const uint8_t *txData, uint8_t *rxData, int len) +FAST_CODE bool spiInternalReadWriteBufPolled(SPI_TypeDef *instance, const uint8_t *txData, uint8_t *rxData, int len) { while (len) { while (!DDL_SPI_IsActiveFlag_TXE(instance)); @@ -377,74 +377,9 @@ FAST_CODE void spiSequenceStart(const extDevice_t *dev) if (bus->useDMA && dmaSafe && ((segmentCount > 1) || (xferLen >= SPI_DMA_THRESHOLD) || !bus->curSegment[segmentCount].negateCS)) { - // Intialise the init structures for the first transfer - spiInternalInitStream(dev, false); - - // Assert Chip Select - IOLo(dev->busType_u.spi.csnPin); - - // Start the transfers - spiInternalStartDMA(dev); + spiProcessSegmentsDMA(dev); } else { - busSegment_t *lastSegment = NULL; - bool segmentComplete; - - // Manually work through the segment list performing a transfer for each - while (bus->curSegment->len) { - if (!lastSegment || lastSegment->negateCS) { - // Assert Chip Select if necessary - it's costly so only do so if necessary - IOLo(dev->busType_u.spi.csnPin); - } - - spiInternalReadWriteBufPolled( - bus->busType_u.spi.instance, - bus->curSegment->u.buffers.txData, - bus->curSegment->u.buffers.rxData, - bus->curSegment->len); - - if (bus->curSegment->negateCS) { - // Negate Chip Select - IOHi(dev->busType_u.spi.csnPin); - } - - segmentComplete = true; - if (bus->curSegment->callback) { - switch(bus->curSegment->callback(dev->callbackArg)) { - case BUS_BUSY: - // Repeat the last DMA segment - segmentComplete = false; - break; - - case BUS_ABORT: - bus->curSegment = (busSegment_t *)BUS_SPI_FREE; - segmentComplete = false; - return; - - case BUS_READY: - default: - // Advance to the next DMA segment - break; - } - } - if (segmentComplete) { - lastSegment = (busSegment_t *)bus->curSegment; - bus->curSegment++; - } - } - - // If a following transaction has been linked, start it - if (bus->curSegment->u.link.dev) { - busSegment_t *endSegment = (busSegment_t *)bus->curSegment; - const extDevice_t *nextDev = endSegment->u.link.dev; - busSegment_t *nextSegments = (busSegment_t *)endSegment->u.link.segments; - bus->curSegment = nextSegments; - endSegment->u.link.dev = NULL; - endSegment->u.link.segments = NULL; - spiSequenceStart(nextDev); - } else { - // The end of the segment list has been reached, so mark transactions as complete - bus->curSegment = (busSegment_t *)BUS_SPI_FREE; - } + spiProcessSegmentsPolled(dev); } } #endif diff --git a/src/platform/AT32/bus_spi_at32bsp.c b/src/platform/AT32/bus_spi_at32bsp.c index 5c643198bb..4182e195f1 100644 --- a/src/platform/AT32/bus_spi_at32bsp.c +++ b/src/platform/AT32/bus_spi_at32bsp.c @@ -135,7 +135,7 @@ void spiInternalResetStream(dmaChannelDescriptor_t *descriptor) DMA_CLEAR_FLAG(descriptor, DMA_IT_HTIF | DMA_IT_TEIF | DMA_IT_TCIF); } -static bool spiInternalReadWriteBufPolled(spi_type *instance, const uint8_t *txData, uint8_t *rxData, int len) +bool spiInternalReadWriteBufPolled(spi_type *instance, const uint8_t *txData, uint8_t *rxData, int len) { uint8_t b; @@ -345,73 +345,9 @@ void spiSequenceStart(const extDevice_t *dev) if (bus->useDMA && dmaSafe && ((segmentCount > 1) || (xferLen >= SPI_DMA_THRESHOLD) || !bus->curSegment[segmentCount].negateCS)) { - // Intialise the init structures for the first transfer - spiInternalInitStream(dev, false); - - // Assert Chip Select - IOLo(dev->busType_u.spi.csnPin); - - // Start the transfers - spiInternalStartDMA(dev); + spiProcessSegmentsDMA(dev); } else { - busSegment_t *lastSegment = NULL; - bool segmentComplete; - - // Manually work through the segment list performing a transfer for each - while (bus->curSegment->len) { - if (!lastSegment || lastSegment->negateCS) { - // Assert Chip Select if necessary - it's costly so only do so if necessary - IOLo(dev->busType_u.spi.csnPin); - } - - spiInternalReadWriteBufPolled(bus->busType_u.spi.instance, - bus->curSegment->u.buffers.txData, - bus->curSegment->u.buffers.rxData, - bus->curSegment->len); - - if (bus->curSegment->negateCS) { - // Negate Chip Select - IOHi(dev->busType_u.spi.csnPin); - } - - segmentComplete = true; - if (bus->curSegment->callback) { - switch(bus->curSegment->callback(dev->callbackArg)) { - case BUS_BUSY: - // Repeat the last DMA segment - segmentComplete = false; - break; - - case BUS_ABORT: - bus->curSegment = (busSegment_t *)BUS_SPI_FREE; - segmentComplete = false; - return; - - case BUS_READY: - default: - // Advance to the next DMA segment - break; - } - } - if (segmentComplete) { - lastSegment = (busSegment_t *)bus->curSegment; - bus->curSegment++; - } - } - - // If a following transaction has been linked, start it - if (bus->curSegment->u.link.dev) { - const extDevice_t *nextDev = bus->curSegment->u.link.dev; - busSegment_t *nextSegments = (busSegment_t *)bus->curSegment->u.link.segments; - busSegment_t *endSegment = (busSegment_t *)bus->curSegment; - bus->curSegment = nextSegments; - endSegment->u.link.dev = NULL; - endSegment->u.link.segments = NULL; - spiSequenceStart(nextDev); - } else { - // The end of the segment list has been reached, so mark transactions as complete - bus->curSegment = (busSegment_t *)BUS_SPI_FREE; - } + spiProcessSegmentsPolled(dev); } } #endif diff --git a/src/platform/STM32/bus_spi_ll.c b/src/platform/STM32/bus_spi_ll.c index 16ae9b5980..9e3d3ea21c 100644 --- a/src/platform/STM32/bus_spi_ll.c +++ b/src/platform/STM32/bus_spi_ll.c @@ -206,7 +206,7 @@ void spiInternalResetStream(dmaChannelDescriptor_t *descriptor) DMA_CLEAR_FLAG(descriptor, DMA_IT_HTIF | DMA_IT_TEIF | DMA_IT_TCIF); } -FAST_CODE static bool spiInternalReadWriteBufPolled(SPI_TypeDef *instance, const uint8_t *txData, uint8_t *rxData, int len) +FAST_CODE bool spiInternalReadWriteBufPolled(SPI_TypeDef *instance, const uint8_t *txData, uint8_t *rxData, int len) { #if defined(STM32H7) LL_SPI_SetTransferSize(instance, len); @@ -618,74 +618,9 @@ FAST_CODE void spiSequenceStart(const extDevice_t *dev) if (bus->useDMA && dmaSafe && ((segmentCount > 1) || (xferLen >= SPI_DMA_THRESHOLD) || !bus->curSegment[segmentCount].negateCS)) { - // Intialise the init structures for the first transfer - spiInternalInitStream(dev, false); - - // Assert Chip Select - IOLo(dev->busType_u.spi.csnPin); - - // Start the transfers - spiInternalStartDMA(dev); + spiProcessSegmentsDMA(dev); } else { - busSegment_t *lastSegment = NULL; - bool segmentComplete; - - // Manually work through the segment list performing a transfer for each - while (bus->curSegment->len) { - if (!lastSegment || lastSegment->negateCS) { - // Assert Chip Select if necessary - it's costly so only do so if necessary - IOLo(dev->busType_u.spi.csnPin); - } - - spiInternalReadWriteBufPolled( - bus->busType_u.spi.instance, - bus->curSegment->u.buffers.txData, - bus->curSegment->u.buffers.rxData, - bus->curSegment->len); - - if (bus->curSegment->negateCS) { - // Negate Chip Select - IOHi(dev->busType_u.spi.csnPin); - } - - segmentComplete = true; - if (bus->curSegment->callback) { - switch(bus->curSegment->callback(dev->callbackArg)) { - case BUS_BUSY: - // Repeat the last DMA segment - segmentComplete = false; - break; - - case BUS_ABORT: - bus->curSegment = (busSegment_t *)BUS_SPI_FREE; - segmentComplete = false; - return; - - case BUS_READY: - default: - // Advance to the next DMA segment - break; - } - } - if (segmentComplete) { - lastSegment = (busSegment_t *)bus->curSegment; - bus->curSegment++; - } - } - - // If a following transaction has been linked, start it - if (bus->curSegment->u.link.dev) { - busSegment_t *endSegment = (busSegment_t *)bus->curSegment; - const extDevice_t *nextDev = endSegment->u.link.dev; - busSegment_t *nextSegments = (busSegment_t *)endSegment->u.link.segments; - bus->curSegment = nextSegments; - endSegment->u.link.dev = NULL; - endSegment->u.link.segments = NULL; - spiSequenceStart(nextDev); - } else { - // The end of the segment list has been reached, so mark transactions as complete - bus->curSegment = (busSegment_t *)BUS_SPI_FREE; - } + spiProcessSegmentsPolled(dev); } } #endif diff --git a/src/platform/STM32/bus_spi_stdperiph.c b/src/platform/STM32/bus_spi_stdperiph.c index 7b74aa6b0f..5fcf671528 100644 --- a/src/platform/STM32/bus_spi_stdperiph.c +++ b/src/platform/STM32/bus_spi_stdperiph.c @@ -143,7 +143,7 @@ void spiInternalResetStream(dmaChannelDescriptor_t *descriptor) DMA_CLEAR_FLAG(descriptor, DMA_IT_HTIF | DMA_IT_TEIF | DMA_IT_TCIF); } -static bool spiInternalReadWriteBufPolled(SPI_TypeDef *instance, const uint8_t *txData, uint8_t *rxData, int len) +bool spiInternalReadWriteBufPolled(SPI_TypeDef *instance, const uint8_t *txData, uint8_t *rxData, int len) { uint8_t b; @@ -369,74 +369,9 @@ void spiSequenceStart(const extDevice_t *dev) if (bus->useDMA && dmaSafe && ((segmentCount > 1) || (xferLen >= SPI_DMA_THRESHOLD) || !bus->curSegment[segmentCount].negateCS)) { - // Intialise the init structures for the first transfer - spiInternalInitStream(dev, false); - - // Assert Chip Select - IOLo(dev->busType_u.spi.csnPin); - - // Start the transfers - spiInternalStartDMA(dev); + spiProcessSegmentsDMA(dev); } else { - busSegment_t *lastSegment = NULL; - bool segmentComplete; - - // Manually work through the segment list performing a transfer for each - while (bus->curSegment->len) { - if (!lastSegment || lastSegment->negateCS) { - // Assert Chip Select if necessary - it's costly so only do so if necessary - IOLo(dev->busType_u.spi.csnPin); - } - - spiInternalReadWriteBufPolled( - bus->busType_u.spi.instance, - bus->curSegment->u.buffers.txData, - bus->curSegment->u.buffers.rxData, - bus->curSegment->len); - - if (bus->curSegment->negateCS) { - // Negate Chip Select - IOHi(dev->busType_u.spi.csnPin); - } - - segmentComplete = true; - if (bus->curSegment->callback) { - switch(bus->curSegment->callback(dev->callbackArg)) { - case BUS_BUSY: - // Repeat the last DMA segment - segmentComplete = false; - break; - - case BUS_ABORT: - bus->curSegment = (busSegment_t *)BUS_SPI_FREE; - segmentComplete = false; - return; - - case BUS_READY: - default: - // Advance to the next DMA segment - break; - } - } - if (segmentComplete) { - lastSegment = (busSegment_t *)bus->curSegment; - bus->curSegment++; - } - } - - // If a following transaction has been linked, start it - if (bus->curSegment->u.link.dev) { - busSegment_t *endSegment = (busSegment_t *)bus->curSegment; - const extDevice_t *nextDev = endSegment->u.link.dev; - busSegment_t *nextSegments = (busSegment_t *)endSegment->u.link.segments; - bus->curSegment = nextSegments; - endSegment->u.link.dev = NULL; - endSegment->u.link.segments = NULL; - spiSequenceStart(nextDev); - } else { - // The end of the segment list has been reached, so mark transactions as complete - bus->curSegment = (busSegment_t *)BUS_SPI_FREE; - } + spiProcessSegmentsPolled(dev); } } #endif diff --git a/src/platform/common/stm32/bus_spi_hw.c b/src/platform/common/stm32/bus_spi_hw.c index d294455298..f15e226968 100644 --- a/src/platform/common/stm32/bus_spi_hw.c +++ b/src/platform/common/stm32/bus_spi_hw.c @@ -39,80 +39,6 @@ extern spiDevice_t spiDevice[SPIDEV_COUNT]; extern busDevice_t spiBusDevice[SPIDEV_COUNT]; -// Interrupt handler for SPI receive DMA completion -FAST_IRQ_HANDLER static void spiIrqHandler(const extDevice_t *dev) -{ - busDevice_t *bus = dev->bus; - busSegment_t *nextSegment; - - if (bus->curSegment->callback) { - switch(bus->curSegment->callback(dev->callbackArg)) { - case BUS_BUSY: - // Repeat the last DMA segment - bus->curSegment--; - // Reinitialise the cached init values as segment is not progressing - spiInternalInitStream(dev, true); - break; - - case BUS_ABORT: - // Skip to the end of the segment list - nextSegment = (busSegment_t *)bus->curSegment + 1; - while (nextSegment->len != 0) { - bus->curSegment = nextSegment; - nextSegment = (busSegment_t *)bus->curSegment + 1; - } - break; - - case BUS_READY: - default: - // Advance to the next DMA segment - break; - } - } - - // Advance through the segment list - // OK to discard the volatile qualifier here - nextSegment = (busSegment_t *)bus->curSegment + 1; - - if (nextSegment->len == 0) { - // If a following transaction has been linked, start it - if (nextSegment->u.link.dev) { - const extDevice_t *nextDev = nextSegment->u.link.dev; - busSegment_t *nextSegments = (busSegment_t *)nextSegment->u.link.segments; - // The end of the segment list has been reached - bus->curSegment = nextSegments; - nextSegment->u.link.dev = NULL; - nextSegment->u.link.segments = NULL; - spiSequenceStart(nextDev); - } else { - // The end of the segment list has been reached, so mark transactions as complete - bus->curSegment = (busSegment_t *)BUS_SPI_FREE; - } - } else { - // Do as much processing as possible before asserting CS to avoid violating minimum high time - bool negateCS = bus->curSegment->negateCS; - - bus->curSegment = nextSegment; - - // After the completion of the first segment setup the init structure for the subsequent segment - if (bus->initSegment) { - spiInternalInitStream(dev, false); - bus->initSegment = false; - } - - if (negateCS) { - // Assert Chip Select - it's costly so only do so if necessary - IOLo(dev->busType_u.spi.csnPin); - } - - // Launch the next transfer - spiInternalStartDMA(dev); - - // Prepare the init structures ready for the next segment to reduce inter-segment time - spiInternalInitStream(dev, true); - } -} - // Interrupt handler for SPI receive DMA completion FAST_IRQ_HANDLER static void spiRxIrqHandler(dmaChannelDescriptor_t* descriptor) { From 5a6d13c1a6207021ce77e4e53d0ba2fe689c4516 Mon Sep 17 00:00:00 2001 From: "Git bot (blckmn)" Date: Thu, 24 Apr 2025 06:25:02 +0000 Subject: [PATCH 177/244] Auto updated submodule references [24-04-2025] --- src/config | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/config b/src/config index ad70d2a88f..b78b689b88 160000 --- a/src/config +++ b/src/config @@ -1 +1 @@ -Subproject commit ad70d2a88ff301173fc9e2b57c298b472a978848 +Subproject commit b78b689b8864e1c27815c379de288541d034f1bb From f1923d349898ae6121b067387b06294ecc7e1e31 Mon Sep 17 00:00:00 2001 From: "Git bot (blckmn)" Date: Fri, 25 Apr 2025 06:26:19 +0000 Subject: [PATCH 178/244] Auto updated submodule references [25-04-2025] --- src/config | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/config b/src/config index b78b689b88..70f3fa0765 160000 --- a/src/config +++ b/src/config @@ -1 +1 @@ -Subproject commit b78b689b8864e1c27815c379de288541d034f1bb +Subproject commit 70f3fa07653c6fe30d1bd584e6e5fc1f6b79218a From 948dfd79dd6e7cd80a69398e6874e8d51abef9f4 Mon Sep 17 00:00:00 2001 From: "Git bot (blckmn)" Date: Sat, 26 Apr 2025 06:25:02 +0000 Subject: [PATCH 179/244] Auto updated submodule references [26-04-2025] --- src/config | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/config b/src/config index 70f3fa0765..cbc4b7ed33 160000 --- a/src/config +++ b/src/config @@ -1 +1 @@ -Subproject commit 70f3fa07653c6fe30d1bd584e6e5fc1f6b79218a +Subproject commit cbc4b7ed331786a448cd5bc0671dbecd3439059e From 5b82a6aa2d0f839e67569064eaeeea6556d4ea3d Mon Sep 17 00:00:00 2001 From: Mark Haslinghuis Date: Tue, 29 Apr 2025 06:43:18 +0200 Subject: [PATCH 180/244] Fix ATRN (#14360) * Fix ATRN - Fixes: #14359 * Fix typo --- src/main/osd/osd_elements.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/main/osd/osd_elements.c b/src/main/osd/osd_elements.c index 4b9aa162f4..47d42eecd6 100644 --- a/src/main/osd/osd_elements.c +++ b/src/main/osd/osd_elements.c @@ -1097,10 +1097,10 @@ static void osdElementFlymode(osdElementParms_t *element) } else if (IS_RC_MODE_ACTIVE(BOXACROTRAINER)) { strcpy(element->buff, "ATRN"); #ifdef USE_CHIRP - // the additional check for pidChirpIsFinished() is to have visual feedback for user that don't have warnings enabled in their googles + // the additional check for pidChirpIsFinished() is to have visual feedback for user that don't have warnings enabled in their goggles } else if (FLIGHT_MODE(CHIRP_MODE) && !pidChirpIsFinished()) { -#endif strcpy(element->buff, "CHIR"); +#endif } else if (isAirmodeEnabled()) { strcpy(element->buff, "AIR "); } else { From 8e40eed8063b9b48813894ae5ad2c14458004dd2 Mon Sep 17 00:00:00 2001 From: Mark Haslinghuis Date: Wed, 30 Apr 2025 01:39:23 +0200 Subject: [PATCH 181/244] Fix turtle mode motor direction on rearm (#14362) * Fix turtle mode direction on rearm * Set motor direction on disarm too * Refactor per review ledvinap * remove added space * update logic --- src/main/fc/core.c | 10 ++-------- 1 file changed, 2 insertions(+), 8 deletions(-) diff --git a/src/main/fc/core.c b/src/main/fc/core.c index fc123e52a5..cab68d4d30 100644 --- a/src/main/fc/core.c +++ b/src/main/fc/core.c @@ -557,7 +557,6 @@ void tryArm(void) } } #endif - // choose crashflip outcome on arming // disarm can arise in processRx() if the crashflip switch is reversed while in crashflip mode // if we were unsuccessful, or cannot determin success, arming will be blocked and we can't get here @@ -570,14 +569,9 @@ void tryArm(void) // when arming and not in crashflip mode, block entry to crashflip if delayed by the dshot beeper, // otherwise consider only the switch position crashFlipModeActive = (tryingToArm == ARMING_DELAYED_CRASHFLIP) ? false : IS_RC_MODE_ACTIVE(BOXCRASHFLIP); -#ifdef USE_DSHOT - // previous disarm will have set direction to normal - // at this point we only need to reverse the motors if crashflipMode is active - if (crashFlipModeActive) { - setMotorSpinDirection(DSHOT_CMD_SPIN_DIRECTION_REVERSED); - } -#endif } + + setMotorSpinDirection(crashFlipModeActive ? DSHOT_CMD_SPIN_DIRECTION_REVERSED : DSHOT_CMD_SPIN_DIRECTION_NORMAL); } #endif // USE_DSHOT From 696c90ba0f901a94d7d72f472b062531eca7b9b4 Mon Sep 17 00:00:00 2001 From: "Git bot (blckmn)" Date: Mon, 5 May 2025 06:25:03 +0000 Subject: [PATCH 182/244] Auto updated submodule references [05-05-2025] --- src/config | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/config b/src/config index cbc4b7ed33..91480413da 160000 --- a/src/config +++ b/src/config @@ -1 +1 @@ -Subproject commit cbc4b7ed331786a448cd5bc0671dbecd3439059e +Subproject commit 91480413da093895e056654dfc7fdc5c8bd6390b From 26f7acfef8f80c50a94c31e4d9f4536d0a64de53 Mon Sep 17 00:00:00 2001 From: "Git bot (blckmn)" Date: Tue, 6 May 2025 06:25:03 +0000 Subject: [PATCH 183/244] Auto updated submodule references [06-05-2025] --- src/config | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/config b/src/config index 91480413da..3be1afda9a 160000 --- a/src/config +++ b/src/config @@ -1 +1 @@ -Subproject commit 91480413da093895e056654dfc7fdc5c8bd6390b +Subproject commit 3be1afda9a7b1605a16dbef13e0e4bdc72219f5d From 43965b7de7a900d6b9299a5b2e4241d1097c595a Mon Sep 17 00:00:00 2001 From: "Git bot (blckmn)" Date: Thu, 8 May 2025 06:25:03 +0000 Subject: [PATCH 184/244] Auto updated submodule references [08-05-2025] --- src/config | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/config b/src/config index 3be1afda9a..8fd62d5ed1 160000 --- a/src/config +++ b/src/config @@ -1 +1 @@ -Subproject commit 3be1afda9a7b1605a16dbef13e0e4bdc72219f5d +Subproject commit 8fd62d5ed18312e0539d87e1fe7b612d04dd128b From 6377188324286be21dd8b4d3061d4a8a8e62ed8e Mon Sep 17 00:00:00 2001 From: Marc Frank Date: Fri, 9 May 2025 22:33:36 +0200 Subject: [PATCH 185/244] throttle lookup table increase size, fix linear interpolation and improve bezier interpolation logic (#14356) * throttle lookup table increase size, fix linear interpolation and improve bezier interpolation logic * Refactor quadraticBezier function to calculate y-coordinate from x-coordinate * Update src/main/fc/rc.c Co-authored-by: Mark Haslinghuis * Update src/main/fc/rc.c Co-authored-by: Petr Ledvina * Update src/main/fc/rc.c Co-authored-by: Petr Ledvina * revert comment strip * Update src/main/fc/rc.c Co-authored-by: Petr Ledvina * add handling of negative index in rcLookupThrottle function * refine comments in quadraticBezier function for clarity * Update src/main/fc/rc.c Co-authored-by: nerdCopter <56646290+nerdCopter@users.noreply.github.com> * revert control point movement to 4.5 method * Update src/main/fc/rc.c Co-authored-by: Mark Haslinghuis --------- Co-authored-by: Mark Haslinghuis Co-authored-by: Petr Ledvina Co-authored-by: nerdCopter <56646290+nerdCopter@users.noreply.github.com> --- src/main/fc/rc.c | 102 ++++++++++++++++++++++++++++++++++++----------- 1 file changed, 79 insertions(+), 23 deletions(-) diff --git a/src/main/fc/rc.c b/src/main/fc/rc.c index f10752fecc..16216ad695 100644 --- a/src/main/fc/rc.c +++ b/src/main/fc/rc.c @@ -150,14 +150,29 @@ float getMaxRcDeflectionAbs(void) return maxRcDeflectionAbs; } -#define THROTTLE_LOOKUP_LENGTH 12 +#ifndef THROTTLE_LOOKUP_LENGTH +# define THROTTLE_LOOKUP_LENGTH 12 +#endif static int16_t lookupThrottleRC[THROTTLE_LOOKUP_LENGTH]; // lookup table for expo & mid THROTTLE static int16_t rcLookupThrottle(int32_t tmp) { - const int32_t tmp2 = tmp / 100; - // [0;1000] -> expo -> [MINTHROTTLE;MAXTHROTTLE] - return lookupThrottleRC[tmp2] + (tmp - tmp2 * 100) * (lookupThrottleRC[tmp2 + 1] - lookupThrottleRC[tmp2]) / 100; + // tmp is 0…PWM_RANGE + // Spread that range evenly over THROTTLE_LOOKUP_LENGTH-1 steps + const int32_t steps = THROTTLE_LOOKUP_LENGTH - 1; + const int32_t scaled = tmp * steps; // 0…PWM_RANGE*steps + const int32_t idx = scaled / PWM_RANGE; // 0…steps + const int32_t rem = scaled % PWM_RANGE; // for interpolation + + // If index goes outside the valid range, clamp it + if (idx >= steps) { + return lookupThrottleRC[steps]; + } else if (idx < 0) { + return lookupThrottleRC[0]; + } + + // Otherwise linearly interpolate between lookupThrottleRC[idx] and [idx+1] + return scaleRange(rem, 0, PWM_RANGE, lookupThrottleRC[idx], lookupThrottleRC[idx + 1]); } #define SETPOINT_RATE_LIMIT_MIN -1998.0f @@ -823,8 +838,48 @@ bool isMotorsReversed(void) return reverseMotors; } -static float quadraticBezier(float t, float p0, float p1, float p2) { - return (1.0f - t) * (1.0f - t) * p0 + 2.0f * (1.0f - t) * t * p1 + t * t * p2; +// Calculates the y-coordinate of a point on a quadratic Bezier curve for a given x-coordinate. +// It first solves for the parameter t such that Bezier_x(t) = x, using the x control points (p0x, p1x, p2x). +// Then, it calculates the y-coordinate using the found t and the y control points (p0y, p1y, p2y). +static float quadraticBezier(float x, float p0x, float p1x, float p2x, float p0y, float p1y, float p2y) +{ + // Solve for t such that Bezier_x(t) = x + // Bezier_x(t) = (1-t)^2*p0x + 2*(1-t)*t*p1x + t^2*p2x + // Rearranging into A*t^2 + B*t + C = 0, where C = p0x - x + float a = p0x - 2.0f * p1x + p2x; + float b = 2.0f * p1x - 2.0f * p0x; + float c = p0x - x; + float t = 0.0f; // Default t + + // Solve the quadratic equation for t + if (fabsf(a) < 1e-6f) { // Linear equation case (a is close to zero) + if (fabsf(b) > 1e-6f) { + t = -c / b; + } + // If both a and b are zero, t = 0 (degenerate case) + } else { + float disc = b * b - 4.0f * a * c; + if (disc >= 0.0f) { // Real roots exist + float sqrtD = sqrtf(disc); + float t1 = (-b + sqrtD) / (2.0f * a); + float t2 = (-b - sqrtD) / (2.0f * a); + + // Select the root within [0, 1], preferring t1 if both are valid. + // Replicates the original solveQuadratic logic: use t1 if valid, otherwise use t2. + if (t1 >= 0.0f && t1 <= 1.0f) { + t = t1; + } else { + t = t2; // Use t2 even if it's outside [0, 1] as per original logic + } + } + // If disc < 0, no real roots, t = 0. + } + + // Clamp t to the valid range [0, 1] before calculating y + t = constrainf(t, 0.0f, 1.0f); + + // Calculate y using the parameter t and y-control points + return (1.0f - t) * (1.0f - t) * p0y + 2.0f * (1.0f - t) * t * p1y + t * t * p2y; } void initRcProcessing(void) @@ -839,34 +894,35 @@ void initRcProcessing(void) /* Algorithm Overview: - thrMid and thrHover define a key point (hover point) in the throttle curve. - • thrMid is the normalized x-coordinate at which the curve reaches the hover point. - • thrHover is the normalized y-coordinate at that point. + - thrMid is the normalized x-coordinate at which the curve reaches the hover point. + - thrHover is the normalized y-coordinate at that point. - The curve is built in two segments using quadratic Bezier interpolation: Segment 1: from (0, 0) to (thrMid, thrHover) - • ymin = 0, ymid = thrHover. - • The control point cp1y blends between (thrHover/2) for expo=0 and thrHover for expo=1. + - ymin = 0, ymid = thrHover. + - The control point cp1y blends between (thrHover/2) for expo=0 and thrHover for expo=1. Segment 2: from (thrMid, thrHover) to (1, 1) - • ymid = thrHover, ymax = 1. - • The control point cp2y blends between [thrHover + (1 - thrHover) / 2] for expo=0 and thrHover for expo=1. + - ymid = thrHover, ymax = 1. + - The control point cp2y blends between [thrHover + (1 - thrHover) / 2] for expo=0 and thrHover for expo=1. - The output y is mapped from [0,1] to the PWM range. */ + // control points: move between 'on the diagonal' and 'at the same height as the hover point' + float cp1x = thrMid * 0.5f; + float cp1y = thrHover * 0.5f * (1.0f + expo); + float cp2x = (1.0f + thrMid) * 0.5f; + float cp2y = (1.0f + ((thrHover - 1.0f) * 0.5f * (1.0f + expo))); + + // build throttle lookup table by solving for t so that Bézier_x(t)=x for (int i = 0; i < THROTTLE_LOOKUP_LENGTH; i++) { float x = (float)i / (THROTTLE_LOOKUP_LENGTH - 1); - float y = 0.0f; + float y; if (x <= thrMid) { - float t = (thrMid > 0.0f) ? x / thrMid : 0.0f; - float ymin = 0.0f; - float ymid = thrHover; - float cp1y = (thrHover / 2.0f) * (1.0f - expo) + thrHover * expo; - y = quadraticBezier(t, ymin, cp1y, ymid); + // Segment 1: Control points (0,0), (cp1x, cp1y), (thrMid, thrHover) + y = quadraticBezier(x, 0.0f, cp1x, thrMid, 0.0f, cp1y, thrHover); } else { - float t = ((1.0f - thrMid) > 0.0f) ? (x - thrMid) / (1.0f - thrMid) : 0.0f; - float ymid = thrHover; - float ymax = 1.0f; - float cp2y = (thrHover + (1.0f - thrHover) / 2.0f) * (1.0f - expo) + thrHover * expo; - y = quadraticBezier(t, ymid, cp2y, ymax); + // Segment 2: Control points (thrMid, thrHover), (cp2x, cp2y), (1, 1) + y = quadraticBezier(x, thrMid, cp2x, 1.0f, thrHover, cp2y, 1.0f); } lookupThrottleRC[i] = lrintf(scaleRangef(y, 0.0f, 1.0f, PWM_RANGE_MIN, PWM_RANGE_MAX)); From 32a7fbef5dcb669e193ceae8fcfff8da39491404 Mon Sep 17 00:00:00 2001 From: "Git bot (blckmn)" Date: Sat, 10 May 2025 06:25:03 +0000 Subject: [PATCH 186/244] Auto updated submodule references [10-05-2025] --- src/config | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/config b/src/config index 8fd62d5ed1..53e2e0aa71 160000 --- a/src/config +++ b/src/config @@ -1 +1 @@ -Subproject commit 8fd62d5ed18312e0539d87e1fe7b612d04dd128b +Subproject commit 53e2e0aa717c138ae46a20a373f32da1e871ee2a From 37c921cdf0b36afefc73eaa000ecd38301192bd2 Mon Sep 17 00:00:00 2001 From: Leo Garcia <34465410+DrAtomic@users.noreply.github.com> Date: Mon, 12 May 2025 10:34:57 -0700 Subject: [PATCH 187/244] fix format overflow in blackboxVirtualBeginLog (#14373) * cast largestLogFileNumber to 16bits to prevent format overflow * Update src/main/blackbox/blackbox_virtual.c remove uint16 cast Co-authored-by: Petr Ledvina * Update src/main/blackbox/blackbox_virtual.c use snprintf instead of strlen Co-authored-by: Petr Ledvina --------- Co-authored-by: Petr Ledvina --- src/main/blackbox/blackbox_virtual.c | 6 +++--- src/main/blackbox/blackbox_virtual.h | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/main/blackbox/blackbox_virtual.c b/src/main/blackbox/blackbox_virtual.c index d607e6f125..7a5a76e6b1 100644 --- a/src/main/blackbox/blackbox_virtual.c +++ b/src/main/blackbox/blackbox_virtual.c @@ -87,9 +87,9 @@ bool blackboxVirtualBeginLog(void) if (blackboxVirtualFile != NULL) { return false; } - const size_t name_buffer_length = strlen(LOGFILE_PREFIX) + 5 + strlen(LOGFILE_SUFFIX) + 2; //file name template: LOG00001.BFL + const size_t name_buffer_length = snprintf(NULL, 0, "%s%05u.%s", LOGFILE_PREFIX, (largestLogFileNumber + 1) % 100000, LOGFILE_SUFFIX); char filename[name_buffer_length]; - sprintf(filename, "%s%05i.%s", LOGFILE_PREFIX, largestLogFileNumber + 1, LOGFILE_SUFFIX); + snprintf(filename, sizeof(filename), "%s%05u.%s", LOGFILE_PREFIX, (largestLogFileNumber + 1) % 100000, LOGFILE_SUFFIX); blackboxVirtualFile = fopen(filename, "w"); if (blackboxVirtualFile != NULL) { largestLogFileNumber++; @@ -111,7 +111,7 @@ void blackboxVirtualClose(void) blackboxVirtualEndLog(); } -uint32_t blackboxVirtualLogFileNumber(void) +int32_t blackboxVirtualLogFileNumber(void) { return largestLogFileNumber; } diff --git a/src/main/blackbox/blackbox_virtual.h b/src/main/blackbox/blackbox_virtual.h index 7f2eb0ee71..770bfc3c78 100644 --- a/src/main/blackbox/blackbox_virtual.h +++ b/src/main/blackbox/blackbox_virtual.h @@ -32,4 +32,4 @@ bool blackboxVirtualFlush(void); bool blackboxVirtualBeginLog(void); bool blackboxVirtualEndLog(void); void blackboxVirtualClose(void); -uint32_t blackboxVirtualLogFileNumber(void); +int32_t blackboxVirtualLogFileNumber(void); From f612b28a863bf7ec0d9d17c77d30a7eef81f7da0 Mon Sep 17 00:00:00 2001 From: Petr Ledvina Date: Tue, 13 May 2025 12:02:28 +0200 Subject: [PATCH 188/244] Use opaque struct to define linker symbols for eeprom (#14382) This way code must be explicit when using linker-defined memory. --- src/main/config/config_eeprom.c | 16 ++++++++-------- src/main/target/common_post.h | 5 +++-- 2 files changed, 11 insertions(+), 10 deletions(-) diff --git a/src/main/config/config_eeprom.c b/src/main/config/config_eeprom.c index 4b48a3914d..afe9e5c579 100644 --- a/src/main/config/config_eeprom.c +++ b/src/main/config/config_eeprom.c @@ -319,7 +319,7 @@ void initEEPROM(void) bool isEEPROMVersionValid(void) { - const uint8_t *p = &__config_start; + const uint8_t *p = (const uint8_t*)&__config_start; const configHeader_t *header = (const configHeader_t *)p; if (header->eepromConfigVersion != EEPROM_CONF_VERSION) { @@ -332,7 +332,7 @@ bool isEEPROMVersionValid(void) // Scan the EEPROM config. Returns true if the config is valid. bool isEEPROMStructureValid(void) { - const uint8_t *p = &__config_start; + const uint8_t *p = (const uint8_t*)&__config_start; const configHeader_t *header = (const configHeader_t *)p; if (header->magic_be != 0xBE) { @@ -350,7 +350,7 @@ bool isEEPROMStructureValid(void) // Found the end. Stop scanning. break; } - if (p + record->size >= &__config_end + if (p + record->size >= (const uint8_t*)&__config_end || record->size < sizeof(*record)) { // Too big or too small. return false; @@ -370,7 +370,7 @@ bool isEEPROMStructureValid(void) crc = crc16_ccitt_update(crc, storedCrc, sizeof(*storedCrc)); p += sizeof(storedCrc); - eepromConfigSize = p - &__config_start; + eepromConfigSize = p - (const uint8_t*)&__config_start; // CRC has the property that if the CRC itself is included in the calculation the resulting CRC will have constant value return crc == CRC_CHECK_VALUE; @@ -391,7 +391,7 @@ size_t getEEPROMStorageSize(void) #ifdef CONFIG_IN_RAM return EEPROM_SIZE; #else - return &__config_end - &__config_start; + return (const uint8_t*)&__config_end - (const uint8_t*)&__config_start; #endif } @@ -400,12 +400,12 @@ size_t getEEPROMStorageSize(void) // this function assumes that EEPROM content is valid static const configRecord_t *findEEPROM(const pgRegistry_t *reg, configRecordFlags_e classification) { - const uint8_t *p = &__config_start; + const uint8_t *p = (const uint8_t*)&__config_start; p += sizeof(configHeader_t); // skip header while (true) { const configRecord_t *record = (const configRecord_t *)p; if (record->size == 0 - || p + record->size >= &__config_end + || p + record->size >= (const uint8_t*)&__config_end || record->size < sizeof(*record)) break; if (pgN(reg) == record->pgn @@ -462,7 +462,7 @@ static bool writeSettingsToEEPROM(void) config_streamer_t streamer; config_streamer_init(&streamer); - config_streamer_start(&streamer, (uintptr_t)&__config_start, &__config_end - &__config_start); + config_streamer_start(&streamer, (uintptr_t)&__config_start, (const uint8_t*)&__config_end - (const uint8_t*)&__config_start); config_streamer_write(&streamer, (uint8_t *)&header, sizeof(header)); uint16_t crc = CRC_START_VALUE; diff --git a/src/main/target/common_post.h b/src/main/target/common_post.h index 76d872128d..cf35e11de9 100644 --- a/src/main/target/common_post.h +++ b/src/main/target/common_post.h @@ -612,8 +612,9 @@ extern uint8_t eepromData[EEPROM_SIZE]; #ifndef CONFIG_IN_FLASH #define CONFIG_IN_FLASH #endif -extern uint8_t __config_start; // configured via linker script when building binaries. -extern uint8_t __config_end; +struct linker_symbol; +extern struct linker_symbol __config_start; // configured via linker script when building binaries. +extern struct linker_symbol __config_end; #endif #if defined(USE_EXST) && !defined(RAMBASED) From 0136c5a54ccc5ab076728806c687f2d5629d263e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?hamza=20=C3=B6zkan?= Date: Tue, 13 May 2025 21:30:14 +0300 Subject: [PATCH 189/244] Update pwm_output_hw.c (#14385) --- src/platform/STM32/pwm_output_hw.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/platform/STM32/pwm_output_hw.c b/src/platform/STM32/pwm_output_hw.c index ae8c6a21af..8824e16320 100644 --- a/src/platform/STM32/pwm_output_hw.c +++ b/src/platform/STM32/pwm_output_hw.c @@ -116,7 +116,7 @@ static void pwmWriteStandard(uint8_t index, float value) static void pwmShutdownPulsesForAllMotors(void) { - for (int index = 0; pwmMotorCount; index++) { + for (int index = 0; index < pwmMotorCount; index++) { // Set the compare register to 0, which stops the output pulsing if the timer overflows if (pwmMotors[index].channel.ccr) { *pwmMotors[index].channel.ccr = 0; @@ -135,7 +135,7 @@ static void pwmCompleteMotorUpdate(void) return; } - for (int index = 0; pwmMotorCount; index++) { + for (int index = 0; index < pwmMotorCount; index++) { if (pwmMotors[index].forceOverflow) { timerForceOverflow(pwmMotors[index].channel.tim); } From a98645b44a68aa94baeb82952d47fa11af005add Mon Sep 17 00:00:00 2001 From: mjs1441 Date: Tue, 13 May 2025 19:35:05 +0100 Subject: [PATCH 190/244] Fix compiler errors if you remove -flto=auto from standard build flags (#14381) --- src/main/drivers/dshot.c | 2 +- src/main/pg/board.c | 6 ++++-- src/platform/STM32/sdio_f4xx.c | 2 +- 3 files changed, 6 insertions(+), 4 deletions(-) diff --git a/src/main/drivers/dshot.c b/src/main/drivers/dshot.c index 54bfe2a4ed..d39a5531f1 100644 --- a/src/main/drivers/dshot.c +++ b/src/main/drivers/dshot.c @@ -306,7 +306,7 @@ FAST_CODE_NOINLINE void updateDshotTelemetry(void) return; } - const unsigned motorCount = dshotMotorCount; + const unsigned motorCount = MIN(MAX_SUPPORTED_MOTORS, dshotMotorCount); uint32_t erpmTotal = 0; uint32_t rpmSamples = 0; diff --git a/src/main/pg/board.c b/src/main/pg/board.c index ace8621eef..607a2e6964 100644 --- a/src/main/pg/board.c +++ b/src/main/pg/board.c @@ -38,8 +38,10 @@ PG_REGISTER_WITH_RESET_FN(boardConfig_t, boardConfig, PG_BOARD_CONFIG, 0); void pgResetFn_boardConfig(boardConfig_t *boardConfig) { if (boardInformationIsSet()) { - strncpy(boardConfig->manufacturerId, getManufacturerId(), MAX_MANUFACTURER_ID_LENGTH + 1); - strncpy(boardConfig->boardName, getBoardName(), MAX_BOARD_NAME_LENGTH + 1); + strncpy(boardConfig->manufacturerId, getManufacturerId(), sizeof(boardConfig->manufacturerId) - 1); + boardConfig->manufacturerId[sizeof(boardConfig->manufacturerId) - 1] = 0; // ensure zero-termination of string + strncpy(boardConfig->boardName, getBoardName(), sizeof(boardConfig->boardName) - 1); + boardConfig->boardName[sizeof(boardConfig->boardName) - 1] = 0; // ensure zero-termination of string boardConfig->boardInformationSet = true; } else { boardConfig->boardInformationSet = false; diff --git a/src/platform/STM32/sdio_f4xx.c b/src/platform/STM32/sdio_f4xx.c index 6b944a020b..ec64647c3f 100644 --- a/src/platform/STM32/sdio_f4xx.c +++ b/src/platform/STM32/sdio_f4xx.c @@ -1359,7 +1359,7 @@ SD_Error_t SD_GetCardStatus(SD_CardStatus_t* pCardStatus) static SD_Error_t SD_PowerON(void) { SD_Error_t ErrorState; - uint32_t Response; + uint32_t Response = 0; // Avoid (invalid) maybe-unitialized compiler error. uint32_t Count; uint32_t ValidVoltage; uint32_t SD_Type; From f7c8b3a776060b630b70176dc798df66c13bc785 Mon Sep 17 00:00:00 2001 From: mjs1441 Date: Tue, 13 May 2025 19:38:35 +0100 Subject: [PATCH 191/244] Add support for SPI_DEVICE_0 (#14384) --- src/main/pg/bus_spi.c | 11 +++++++++++ src/main/target/common_defaults_post.h | 8 ++++++++ 2 files changed, 19 insertions(+) diff --git a/src/main/pg/bus_spi.c b/src/main/pg/bus_spi.c index 1a24e9a5b7..578a386b7b 100644 --- a/src/main/pg/bus_spi.c +++ b/src/main/pg/bus_spi.c @@ -31,6 +31,14 @@ #include "bus_spi.h" +#ifdef USE_SPI_DEVICE_0 +#ifndef SPI0_SCK_PIN +#define SPI0_SCK_PIN NONE +#define SPI0_SDI_PIN NONE +#define SPI0_SDO_PIN NONE +#endif +#endif + #ifndef SPI1_SCK_PIN #define SPI1_SCK_PIN NONE #define SPI1_SDI_PIN NONE @@ -77,6 +85,9 @@ typedef struct spiDefaultConfig_s { } spiDefaultConfig_t; const spiDefaultConfig_t spiDefaultConfig[] = { +#ifdef USE_SPI_DEVICE_0 + { SPIDEV_0, IO_TAG(SPI0_SCK_PIN), IO_TAG(SPI0_SDI_PIN ), IO_TAG(SPI0_SDO_PIN ), SPI0_TX_DMA_OPT, SPI0_RX_DMA_OPT }, +#endif #ifdef USE_SPI_DEVICE_1 { SPIDEV_1, IO_TAG(SPI1_SCK_PIN), IO_TAG(SPI1_SDI_PIN ), IO_TAG(SPI1_SDO_PIN ), SPI1_TX_DMA_OPT, SPI1_RX_DMA_OPT }, #endif diff --git a/src/main/target/common_defaults_post.h b/src/main/target/common_defaults_post.h index 820eba0677..e8b06bdf41 100644 --- a/src/main/target/common_defaults_post.h +++ b/src/main/target/common_defaults_post.h @@ -161,6 +161,14 @@ #endif // USE_ADC #ifdef USE_SPI +#ifdef USE_SPI_DEVICE_0 +#ifndef SPI0_TX_DMA_OPT +#define SPI0_TX_DMA_OPT (DMA_OPT_UNUSED) +#endif +#ifndef SPI0_RX_DMA_OPT +#define SPI0_RX_DMA_OPT (DMA_OPT_UNUSED) +#endif +#endif #ifdef USE_SPI_DEVICE_1 #ifndef SPI1_TX_DMA_OPT #define SPI1_TX_DMA_OPT (DMA_OPT_UNUSED) From ad0c3ef97f66a3849eeffa56b52e87410a3d4c00 Mon Sep 17 00:00:00 2001 From: "Git bot (blckmn)" Date: Thu, 15 May 2025 06:25:03 +0000 Subject: [PATCH 192/244] Auto updated submodule references [15-05-2025] --- src/config | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/config b/src/config index 53e2e0aa71..3377c6c462 160000 --- a/src/config +++ b/src/config @@ -1 +1 @@ -Subproject commit 53e2e0aa717c138ae46a20a373f32da1e871ee2a +Subproject commit 3377c6c462425267f009f4609e75fbe005655e12 From 144314b8204b92922db72ae3ed9d863166479673 Mon Sep 17 00:00:00 2001 From: mjs1441 Date: Thu, 15 May 2025 18:39:59 +0100 Subject: [PATCH 193/244] Remove #ifdef USE_TIMER from motorConfig reset function. (#14389) --- src/main/pg/motor.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/main/pg/motor.c b/src/main/pg/motor.c index d546ed1137..b9c65a69f8 100644 --- a/src/main/pg/motor.c +++ b/src/main/pg/motor.c @@ -75,7 +75,6 @@ void pgResetFn_motorConfig(motorConfig_t *motorConfig) motorConfig->mincommand = 1000; motorConfig->kv = 1960; -#ifdef USE_TIMER #ifdef MOTOR1_PIN motorConfig->dev.ioTags[0] = IO_TAG(MOTOR1_PIN); #endif @@ -99,7 +98,6 @@ void pgResetFn_motorConfig(motorConfig_t *motorConfig) #endif #ifdef MOTOR8_PIN motorConfig->dev.ioTags[7] = IO_TAG(MOTOR8_PIN); -#endif #endif motorConfig->motorPoleCount = 14; // Most brushless motors that we use are 14 poles From b845d6dfd8e3d80d02dd54e50129ae7fbfcfc533 Mon Sep 17 00:00:00 2001 From: mjs1441 Date: Thu, 15 May 2025 21:11:29 +0100 Subject: [PATCH 194/244] Add SYS_INCLUDE_DIRS to top level Makefile. (#14388) Add directories in $(SYS_INCLUDE_DIRS) to the search path via -isystem. This allows a workaround for https://github.com/raspberrypi/pico-sdk/issues/2451 by using system headers, which are more tolerant of macro redefinitions. Co-authored-by: Matthew Selby --- Makefile | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Makefile b/Makefile index 456dc49dbc..7be4e6a6d2 100644 --- a/Makefile +++ b/Makefile @@ -305,6 +305,7 @@ EXTRA_WARNING_FLAGS := -Wold-style-definition CFLAGS += $(ARCH_FLAGS) \ $(addprefix -D,$(OPTIONS)) \ $(addprefix -I,$(INCLUDE_DIRS)) \ + $(addprefix -isystem,$(SYS_INCLUDE_DIRS)) \ $(DEBUG_FLAGS) \ -std=gnu17 \ -Wall -Wextra -Werror -Wunsafe-loop-optimizations -Wdouble-promotion \ @@ -331,6 +332,7 @@ ASFLAGS = $(ARCH_FLAGS) \ $(DEBUG_FLAGS) \ -x assembler-with-cpp \ $(addprefix -I,$(INCLUDE_DIRS)) \ + $(addprefix -isystem,$(SYS_INCLUDE_DIRS)) \ -MMD -MP ifeq ($(LD_FLAGS),) @@ -359,6 +361,7 @@ endif CPPCHECK = cppcheck $(CSOURCES) --enable=all --platform=unix64 \ --std=c99 --inline-suppr --quiet --force \ $(addprefix -I,$(INCLUDE_DIRS)) \ + $(addprefix -isystem,$(SYS_INCLUDE_DIRS)) \ -I/usr/include -I/usr/include/linux TARGET_NAME := $(TARGET) From 7d88e7d27fb08a72a5809bd68d30f54acadbcb7a Mon Sep 17 00:00:00 2001 From: Mark Haslinghuis Date: Thu, 15 May 2025 22:51:29 +0200 Subject: [PATCH 195/244] Fix osd_esc_rpm_alarm (#14361) * Fix osd_esc_rpm_alarm * Should be >= ??? * Add edt condition to pass * Revert 349 --- src/main/osd/osd_warnings.c | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/src/main/osd/osd_warnings.c b/src/main/osd/osd_warnings.c index 3c983946b0..4fac86d0f2 100644 --- a/src/main/osd/osd_warnings.c +++ b/src/main/osd/osd_warnings.c @@ -336,11 +336,6 @@ void renderOsdWarning(char *warningText, bool *blinking, uint8_t *displayAttr) warningText[dshotEscErrorLength++] = 'C'; for (uint8_t k = 0; k < getMotorCount(); k++) { - // Skip if no extended telemetry at all - if ((dshotTelemetryState.motorState[k].telemetryTypes & DSHOT_EXTENDED_TELEMETRY_MASK) == 0) { - continue; - } - // Remember text index before writing warnings dshotEscErrorLengthMotorBegin = dshotEscErrorLength; @@ -354,12 +349,16 @@ void renderOsdWarning(char *warningText, bool *blinking, uint8_t *displayAttr) && (dshotTelemetryState.motorState[k].telemetryData[DSHOT_TELEMETRY_TYPE_eRPM] * 100 * 2 / motorConfig()->motorPoleCount) <= osdConfig()->esc_rpm_alarm) { warningText[dshotEscErrorLength++] = 'R'; } - if (osdConfig()->esc_temp_alarm != ESC_TEMP_ALARM_OFF + + // Skip if no extended telemetry available + bool edt = (dshotTelemetryState.motorState[k].telemetryTypes & DSHOT_EXTENDED_TELEMETRY_MASK) != 0; + + if (edt && osdConfig()->esc_temp_alarm != ESC_TEMP_ALARM_OFF && (dshotTelemetryState.motorState[k].telemetryTypes & (1 << DSHOT_TELEMETRY_TYPE_TEMPERATURE)) != 0 && dshotTelemetryState.motorState[k].telemetryData[DSHOT_TELEMETRY_TYPE_TEMPERATURE] >= osdConfig()->esc_temp_alarm) { warningText[dshotEscErrorLength++] = 'T'; } - if (osdConfig()->esc_current_alarm != ESC_CURRENT_ALARM_OFF + if (edt && osdConfig()->esc_current_alarm != ESC_CURRENT_ALARM_OFF && (dshotTelemetryState.motorState[k].telemetryTypes & (1 << DSHOT_TELEMETRY_TYPE_CURRENT)) != 0 && dshotTelemetryState.motorState[k].telemetryData[DSHOT_TELEMETRY_TYPE_CURRENT] >= osdConfig()->esc_current_alarm) { warningText[dshotEscErrorLength++] = 'C'; From aa9fb836bbff349902e27490a13d2e3fc5e3f18b Mon Sep 17 00:00:00 2001 From: Jay Blackman Date: Sat, 17 May 2025 08:59:06 +1000 Subject: [PATCH 196/244] Create .coderabbit.yaml (#14390) --- .coderabbit.yaml | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) create mode 100644 .coderabbit.yaml diff --git a/.coderabbit.yaml b/.coderabbit.yaml new file mode 100644 index 0000000000..0b3809a5df --- /dev/null +++ b/.coderabbit.yaml @@ -0,0 +1,16 @@ +# yaml-language-server: $schema=https://coderabbit.ai/integrations/schema.v2.json +language: "en-US" +early_access: false +reviews: + profile: "chill" + request_changes_workflow: true + high_level_summary: true + poem: false + review_status: true + collapse_walkthrough: false + disable_placeholder_comment_notifications: true + auto_review: + enabled: true + drafts: false +chat: + auto_reply: true From 8f3c02f403ee6235c68d16d7a7998cac15f410b3 Mon Sep 17 00:00:00 2001 From: Jay Blackman Date: Sat, 17 May 2025 20:49:12 +1000 Subject: [PATCH 197/244] Update .coderabbit.yaml due to invalid parameter (#14393) --- .coderabbit.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.coderabbit.yaml b/.coderabbit.yaml index 0b3809a5df..566ca78b9e 100644 --- a/.coderabbit.yaml +++ b/.coderabbit.yaml @@ -5,10 +5,10 @@ reviews: profile: "chill" request_changes_workflow: true high_level_summary: true + high_level_summary_placeholder: "" poem: false review_status: true collapse_walkthrough: false - disable_placeholder_comment_notifications: true auto_review: enabled: true drafts: false From 7ef4e092c9a8bd20f5c28e64e5fb37c82bdba1f9 Mon Sep 17 00:00:00 2001 From: heronprecision-1 <170825275+heronprecision-1@users.noreply.github.com> Date: Sat, 17 May 2025 16:10:11 -0400 Subject: [PATCH 198/244] Increase the PINIO Limit to 8 (#14378) * awful but it does it * increased pinio limit to 8 * reverted erroneously modified files * updated piniobox.c to mirror pinio changes * updated array size * Update src/main/pg/pinio.c Conditional pinioN if greater than 4. Co-authored-by: Petr Ledvina * Update src/main/pg/pinio.c conditionally assign more pinio boxes if more than 4 Co-authored-by: Petr Ledvina * Update pinio.h revert to default of 4 pinio pins * Update src/main/pg/piniobox.c Co-authored-by: Petr Ledvina --------- Co-authored-by: Anonymous Co-authored-by: Anonymous Co-authored-by: Petr Ledvina --- src/main/pg/pinio.c | 40 ++++++++++++++++++++++++++++++++++++++++ src/main/pg/piniobox.c | 20 ++++++++++++++++++++ 2 files changed, 60 insertions(+) diff --git a/src/main/pg/pinio.c b/src/main/pg/pinio.c index ac706e3eeb..c08033778b 100644 --- a/src/main/pg/pinio.c +++ b/src/main/pg/pinio.c @@ -38,6 +38,20 @@ #ifndef PINIO4_PIN #define PINIO4_PIN NONE #endif +#if PINIO_COUNT > 4 +#ifndef PINIO5_PIN +#define PINIO5_PIN NONE +#endif +#ifndef PINIO6_PIN +#define PINIO6_PIN NONE +#endif +#ifndef PINIO7_PIN +#define PINIO7_PIN NONE +#endif +#ifndef PINIO8_PIN +#define PINIO8_PIN NONE +#endif +#endif #ifndef PINIO1_CONFIG #define PINIO1_CONFIG PINIO_CONFIG_MODE_OUT_PP @@ -55,6 +69,22 @@ #define PINIO4_CONFIG PINIO_CONFIG_MODE_OUT_PP #endif +#ifndef PINIO5_CONFIG +#define PINIO5_CONFIG PINIO_CONFIG_MODE_OUT_PP +#endif + +#ifndef PINIO6_CONFIG +#define PINIO6_CONFIG PINIO_CONFIG_MODE_OUT_PP +#endif + +#ifndef PINIO7_CONFIG +#define PINIO7_CONFIG PINIO_CONFIG_MODE_OUT_PP +#endif + +#ifndef PINIO8_CONFIG +#define PINIO8_CONFIG PINIO_CONFIG_MODE_OUT_PP +#endif + PG_REGISTER_WITH_RESET_FN(pinioConfig_t, pinioConfig, PG_PINIO_CONFIG, 0); void pgResetFn_pinioConfig(pinioConfig_t *config) @@ -63,10 +93,20 @@ void pgResetFn_pinioConfig(pinioConfig_t *config) config->ioTag[1] = IO_TAG(PINIO2_PIN); config->ioTag[2] = IO_TAG(PINIO3_PIN); config->ioTag[3] = IO_TAG(PINIO4_PIN); +#if PINIO_COUNT > 4 + config->ioTag[4] = IO_TAG(PINIO5_PIN); + config->ioTag[5] = IO_TAG(PINIO6_PIN); + config->ioTag[6] = IO_TAG(PINIO7_PIN); + config->ioTag[7] = IO_TAG(PINIO8_PIN); +#endif config->config[0] = PINIO1_CONFIG; config->config[1] = PINIO2_CONFIG; config->config[2] = PINIO3_CONFIG; config->config[3] = PINIO4_CONFIG; + config->config[4] = PINIO5_CONFIG; + config->config[5] = PINIO6_CONFIG; + config->config[6] = PINIO7_CONFIG; + config->config[7] = PINIO8_CONFIG; } #endif diff --git a/src/main/pg/piniobox.c b/src/main/pg/piniobox.c index ca158da75b..fddcf864b5 100644 --- a/src/main/pg/piniobox.c +++ b/src/main/pg/piniobox.c @@ -46,6 +46,22 @@ #define PINIO4_BOX PERMANENT_ID_NONE #endif +#ifndef PINIO5_BOX +#define PINIO5_BOX PERMANENT_ID_NONE +#endif + +#ifndef PINIO6_BOX +#define PINIO6_BOX PERMANENT_ID_NONE +#endif + +#ifndef PINIO7_BOX +#define PINIO7_BOX PERMANENT_ID_NONE +#endif + +#ifndef PINIO8_BOX +#define PINIO8_BOX PERMANENT_ID_NONE +#endif + PG_REGISTER_WITH_RESET_FN(pinioBoxConfig_t, pinioBoxConfig, PG_PINIOBOX_CONFIG, 1); void pgResetFn_pinioBoxConfig(pinioBoxConfig_t *config) @@ -54,6 +70,10 @@ void pgResetFn_pinioBoxConfig(pinioBoxConfig_t *config) config->permanentId[1] = PINIO2_BOX; config->permanentId[2] = PINIO3_BOX; config->permanentId[3] = PINIO4_BOX; + // rest is reset to NONE + for (unsigned i = 4; i < PINIO_COUNT; i++) { + config->permanentId[i] = PERMANENT_ID_NONE; + } } #endif From 45f311b3c1a8f59feb3ee32bae4df69993781124 Mon Sep 17 00:00:00 2001 From: Jay Blackman Date: Sun, 18 May 2025 13:26:14 +1000 Subject: [PATCH 199/244] Delete .github/workflows/nightly.yml (#14392) --- .github/workflows/nightly.yml | 73 ----------------------------------- 1 file changed, 73 deletions(-) delete mode 100644 .github/workflows/nightly.yml diff --git a/.github/workflows/nightly.yml b/.github/workflows/nightly.yml deleted file mode 100644 index 943edaec4e..0000000000 --- a/.github/workflows/nightly.yml +++ /dev/null @@ -1,73 +0,0 @@ -# You'll need to setup the follwing environment variables: -# env.repo_nightly - The repository to release nightly builds to e.g. betaflight-nightly -# env.release_notes - The release notes to be published as part of the github release -# env.debug_release_notes - The release notes to be published as part of the github debug release -# secrets.REPO_TOKEN - A GitHub token with permissions to push and publish releases to the nightly repo - -env: - repo_nightly: betaflight/betaflight-nightlies - debug_release_notes: > - This is an automated development build. - It may be unstable and result in craft loss or damage. - **Use only for testing.** - release_notes: This is a release build. - -name: Nightly - -on: - push: - branches: - - master - -jobs: - ci: - name: CI - uses: ./.github/workflows/ci.yml - with: - release_build: false - - release: - name: Nightly release - needs: ci - runs-on: ubuntu-latest - steps: - - name: Code Checkout - uses: actions/checkout@v4 - - - name: Fetch build artifacts - uses: actions/download-artifact@v4 - - - name: Select release notes - id: notes - run: | - set -- ./*/*.hex - echo "notes=$(test -e "$1" && echo '${{ env.debug_release_notes }}' || echo '${{ env.release_notes }}')" >> $GITHUB_OUTPUT - - - name: Get current date - id: date - run: echo "today=$(date '+%Y%m%d')" >> $GITHUB_OUTPUT - - - name: Release - uses: softprops/action-gh-release@v2 - with: - token: ${{ secrets.REPO_TOKEN }} - repository: ${{ env.repo_nightly }} - tag_name: v${{ steps.date.outputs.today }}.${{ github.run_number }} - files: ./*/*.hex - draft: false - prerelease: false - fail_on_unmatched_files: true - body: | - ${{ steps.notes.outputs.notes }} - - ### Repository: - ${{ github.repository }} ([link](${{ github.event.repository.html_url }})) - - ### Branch: - ${{ github.ref_name }} ([link](${{ github.event.repository.html_url }}/tree/${{ github.ref_name }})) - - ### Latest changeset: - ${{ github.event.head_commit.id }} ([link](${{ github.event.head_commit.url }})) - - ### Changes: - ${{ github.event.head_commit.message }} From 8950483a6a16c9c5a36ae406fb1e6c8121435c2d Mon Sep 17 00:00:00 2001 From: "Git bot (blckmn)" Date: Sun, 18 May 2025 06:25:02 +0000 Subject: [PATCH 200/244] Auto updated submodule references [18-05-2025] --- src/config | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/config b/src/config index 3377c6c462..7b13be1c42 160000 --- a/src/config +++ b/src/config @@ -1 +1 @@ -Subproject commit 3377c6c462425267f009f4609e75fbe005655e12 +Subproject commit 7b13be1c424203bfe80830cec7666b5f6075604e From 0679832760d1109ed9d2ff65d053f3a4f91ebedd Mon Sep 17 00:00:00 2001 From: "Git bot (blckmn)" Date: Mon, 19 May 2025 06:25:03 +0000 Subject: [PATCH 201/244] Auto updated submodule references [19-05-2025] --- src/config | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/config b/src/config index 7b13be1c42..7db4179ef7 160000 --- a/src/config +++ b/src/config @@ -1 +1 @@ -Subproject commit 7b13be1c424203bfe80830cec7666b5f6075604e +Subproject commit 7db4179ef7159138deebf5f671373e7a46a8a162 From 4c9c8106c83a5b1e7475baa37786e0b149efaf64 Mon Sep 17 00:00:00 2001 From: Eric Katzfey <53063038+katzfey@users.noreply.github.com> Date: Tue, 20 May 2025 15:39:54 -0700 Subject: [PATCH 202/244] Changed logical OR to bitwise OR in register value definitions (#14395) for icm426xx SPI driver. Also fixed the incorrect bit setting for one of the definitions --- src/main/drivers/accgyro/accgyro_spi_icm426xx.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/main/drivers/accgyro/accgyro_spi_icm426xx.c b/src/main/drivers/accgyro/accgyro_spi_icm426xx.c index 204b547c56..2a3a327e4d 100644 --- a/src/main/drivers/accgyro/accgyro_spi_icm426xx.c +++ b/src/main/drivers/accgyro/accgyro_spi_icm426xx.c @@ -107,10 +107,10 @@ #define ICM426XX_INT1_POLARITY_ACTIVE_HIGH (1 << 0) #define ICM426XX_RA_INT_CONFIG0 0x63 // User Bank 0 -#define ICM426XX_UI_DRDY_INT_CLEAR_ON_SBR ((0 << 5) || (0 << 4)) -#define ICM426XX_UI_DRDY_INT_CLEAR_ON_SBR_DUPLICATE ((0 << 5) || (0 << 4)) // duplicate settings in datasheet, Rev 1.2. -#define ICM426XX_UI_DRDY_INT_CLEAR_ON_F1BR ((1 << 5) || (0 << 4)) -#define ICM426XX_UI_DRDY_INT_CLEAR_ON_SBR_AND_F1BR ((1 << 5) || (1 << 4)) +#define ICM426XX_UI_DRDY_INT_CLEAR_ON_SBR ((0 << 5) | (0 << 4)) +#define ICM426XX_UI_DRDY_INT_CLEAR_ON_SBR_DUPLICATE ((0 << 5) | (1 << 4)) // duplicate setting in datasheet, Rev 1.8 +#define ICM426XX_UI_DRDY_INT_CLEAR_ON_F1BR ((1 << 5) | (0 << 4)) +#define ICM426XX_UI_DRDY_INT_CLEAR_ON_SBR_AND_F1BR ((1 << 5) | (1 << 4)) #define ICM426XX_RA_INT_CONFIG1 0x64 // User Bank 0 #define ICM426XX_INT_ASYNC_RESET_BIT 4 From 6c127426bdeb0bf16e298a1e3e537d9372fb8455 Mon Sep 17 00:00:00 2001 From: "Git bot (blckmn)" Date: Wed, 21 May 2025 06:25:03 +0000 Subject: [PATCH 203/244] Auto updated submodule references [21-05-2025] --- src/config | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/config b/src/config index 7db4179ef7..17892ac1bd 160000 --- a/src/config +++ b/src/config @@ -1 +1 @@ -Subproject commit 7db4179ef7159138deebf5f671373e7a46a8a162 +Subproject commit 17892ac1bd9bc74f77870c14a2da386a1c614dd3 From 51c8296f25bea598d88f3bf3e0f22fa72ad13cc2 Mon Sep 17 00:00:00 2001 From: Eric Katzfey <53063038+katzfey@users.noreply.github.com> Date: Wed, 21 May 2025 04:48:36 -0700 Subject: [PATCH 204/244] Added float specifier to literal to prevent compile error (#14396) --- src/main/flight/imu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/flight/imu.c b/src/main/flight/imu.c index 2b77a36871..ec797ac6bd 100644 --- a/src/main/flight/imu.c +++ b/src/main/flight/imu.c @@ -625,7 +625,7 @@ static void updateGpsHeadingUsable(float groundspeedGain, float imuCourseError, gpsHeadingConfidence += fmaxf(groundspeedGain - fabsf(imuCourseError), 0.0f) * dt; // recenter at 2.5s time constant // TODO: intent is to match IMU time constant, approximately, but I don't exactly know how to do that - gpsHeadingConfidence -= 0.4 * dt * gpsHeadingConfidence; + gpsHeadingConfidence -= 0.4f * dt * gpsHeadingConfidence; // if we accumulate enough 'points' over time, the IMU probably is OK // will need to reaccumulate after a disarm (will be retained partly for very brief disarms) canUseGPSHeading = gpsHeadingConfidence > 2.0f; From b03b57bd90805d3486bb7168c4c82ee8eeba9e18 Mon Sep 17 00:00:00 2001 From: Eric Katzfey <53063038+katzfey@users.noreply.github.com> Date: Wed, 21 May 2025 06:53:43 -0700 Subject: [PATCH 205/244] Added missing GCC diagnostic push pragma (#14397) Replaced faulty #pragma GCC diagnostic ignored "-Wunused-function" with the more elegant MAYBE_UNUSED macro --- src/main/msp/msp.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/src/main/msp/msp.c b/src/main/msp/msp.c index 3f6aeca7b2..de6d7d2492 100644 --- a/src/main/msp/msp.c +++ b/src/main/msp/msp.c @@ -343,16 +343,13 @@ static void mspFcSetPassthroughCommand(sbuf_t *dst, sbuf_t *src, mspPostProcessF } } -// TODO: Remove the pragma once this is called from unconditional code -#pragma GCC diagnostic ignored "-Wunused-function" -static void configRebootUpdateCheckU8(uint8_t *parm, uint8_t value) +MAYBE_UNUSED static void configRebootUpdateCheckU8(uint8_t *parm, uint8_t value) { if (*parm != value) { setRebootRequired(); } *parm = value; } -#pragma GCC diagnostic pop static void mspRebootFn(serialPort_t *serialPort) { From aa8701ef87d768b41ddcc50e473792bceba67fce Mon Sep 17 00:00:00 2001 From: Mark Haslinghuis Date: Thu, 22 May 2025 00:12:24 +0200 Subject: [PATCH 206/244] Fix inevitable timer overflow (#14374) * Fix beacon timer overflow * fix possible overflow in rc_stats * fix possible overflow in mixer.c * fix possible overflow in osd.c * Update src/main/osd/osd_warnings.c Co-authored-by: Petr Ledvina * Update src/main/osd/osd_warnings.c Co-authored-by: Petr Ledvina * Update src/main/rx/rc_stats.c Co-authored-by: Petr Ledvina * fix typo * Update src/main/osd/osd.c Co-authored-by: Petr Ledvina --------- Co-authored-by: Petr Ledvina --- src/main/flight/mixer.c | 2 +- src/main/osd/osd.c | 2 +- src/main/osd/osd_warnings.c | 10 ++++------ src/main/rx/rc_stats.c | 2 +- 4 files changed, 7 insertions(+), 9 deletions(-) diff --git a/src/main/flight/mixer.c b/src/main/flight/mixer.c index 97dabc3bc8..a2d5bc8b98 100644 --- a/src/main/flight/mixer.c +++ b/src/main/flight/mixer.c @@ -219,7 +219,7 @@ static void calculateThrottleAndCurrentMotorEndpoints(timeUs_t currentTimeUs) throttle = 0; currentThrottleInputRange = rcCommandThrottleRange3dHigh; } - if (currentTimeUs - reversalTimeUs < 250000) { + if (cmpTimeUs(currentTimeUs, reversalTimeUs) < 250000) { // keep iterm zero for 250ms after motor reversal pidResetIterm(); } diff --git a/src/main/osd/osd.c b/src/main/osd/osd.c index 0b2cbaef24..6825191585 100644 --- a/src/main/osd/osd.c +++ b/src/main/osd/osd.c @@ -1243,7 +1243,7 @@ STATIC_UNIT_TESTED bool osdProcessStats1(timeUs_t currentTimeUs) if (ARMING_FLAG(ARMED)) { osdUpdateStats(); - timeUs_t deltaT = currentTimeUs - lastTimeUs; + int deltaT = cmpTimeUs(currentTimeUs, lastTimeUs); osdFlyTime += deltaT; stats.armed_time += deltaT; #ifdef USE_LAUNCH_CONTROL diff --git a/src/main/osd/osd_warnings.c b/src/main/osd/osd_warnings.c index 4fac86d0f2..7390d94a02 100644 --- a/src/main/osd/osd_warnings.c +++ b/src/main/osd/osd_warnings.c @@ -115,12 +115,10 @@ void renderOsdWarning(char *warningText, bool *blinking, uint8_t *displayAttr) #ifdef USE_DSHOT if (isTryingToArm() && !ARMING_FLAG(ARMED)) { - int armingDelayTime = (getLastDshotBeaconCommandTimeUs() + DSHOT_BEACON_GUARD_DELAY_US - currentTimeUs) / 1e5; - if (armingDelayTime < 0) { - armingDelayTime = 0; - } - if (armingDelayTime >= (DSHOT_BEACON_GUARD_DELAY_US / 1e5 - 5)) { - tfp_sprintf(warningText, " BEACON ON"); // Display this message for the first 0.5 seconds + const int beaconGuard = cmpTimeUs(currentTimeUs, getLastDshotBeaconCommandTimeUs()); + const int armingDelayTime = MAX(DSHOT_BEACON_GUARD_DELAY_US - beaconGuard, 0) / 100000; // time remaining until BEACON_GUARD_DELAY, in tenths of second + if (beaconGuard < 500 * 1000) { // first 0.5s since beacon + tfp_sprintf(warningText, " BEACON ON"); } else { tfp_sprintf(warningText, "ARM IN %d.%d", armingDelayTime / 10, armingDelayTime % 10); } diff --git a/src/main/rx/rc_stats.c b/src/main/rx/rc_stats.c index bf0ecf415f..13b943da69 100644 --- a/src/main/rx/rc_stats.c +++ b/src/main/rx/rc_stats.c @@ -44,7 +44,7 @@ int8_t previousThrottlePercent = 0; void rcStatsUpdate(timeUs_t currentTimeUs) { - uint32_t deltaT = currentTimeUs - previousTimeUs; + uint32_t deltaT = cmpTimeUs(currentTimeUs, previousTimeUs); previousTimeUs = currentTimeUs; const int8_t throttlePercent = calculateThrottlePercent(); From da30581cebffcb0cab673868b9514fa53486ae7c Mon Sep 17 00:00:00 2001 From: Eric Katzfey <53063038+katzfey@users.noreply.github.com> Date: Thu, 22 May 2025 16:07:00 -0700 Subject: [PATCH 207/244] Initialized a local variable that could otherwise be used uninitialized (#14399) --- src/main/osd/osd_elements.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/main/osd/osd_elements.c b/src/main/osd/osd_elements.c index 47d42eecd6..c4f92181b4 100644 --- a/src/main/osd/osd_elements.c +++ b/src/main/osd/osd_elements.c @@ -2508,7 +2508,7 @@ void osdUpdateAlarms(void) #endif #if defined(USE_ESC_SENSOR) || defined(USE_DSHOT_TELEMETRY) - bool blink; + bool blink = false; #if defined(USE_ESC_SENSOR) if (featureIsEnabled(FEATURE_ESC_SENSOR)) { @@ -2518,7 +2518,6 @@ void osdUpdateAlarms(void) #endif #if defined(USE_DSHOT_TELEMETRY) { - blink = false; if (osdConfig()->esc_temp_alarm != ESC_TEMP_ALARM_OFF) { for (uint32_t k = 0; !blink && (k < getMotorCount()); k++) { blink = (dshotTelemetryState.motorState[k].telemetryTypes & (1 << DSHOT_TELEMETRY_TYPE_TEMPERATURE)) != 0 && From e9adc03a978c6904569c497dcf0cba8c62476b62 Mon Sep 17 00:00:00 2001 From: Osiris Inferi Date: Fri, 23 May 2025 18:15:49 +0200 Subject: [PATCH 208/244] Move flash_read arguments around in CLI help (#14404) --- src/main/cli/cli.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/cli/cli.c b/src/main/cli/cli.c index b9539389ec..8fd7d3aee2 100644 --- a/src/main/cli/cli.c +++ b/src/main/cli/cli.c @@ -6589,7 +6589,7 @@ const clicmd_t cmdTable[] = { #endif CLI_COMMAND_DEF("flash_info", "show flash chip info", NULL, cliFlashInfo), #if defined(USE_FLASH_TOOLS) && defined(USE_FLASHFS) - CLI_COMMAND_DEF("flash_read", NULL, "
", cliFlashRead), + CLI_COMMAND_DEF("flash_read", NULL, "
", cliFlashRead), CLI_COMMAND_DEF("flash_scan", "scan flash device for errors", NULL, cliFlashVerify), CLI_COMMAND_DEF("flash_write", NULL, "
", cliFlashWrite), #endif From e97fa11163d20d267a3273897520eb9b2d9672b5 Mon Sep 17 00:00:00 2001 From: Steve Evans Date: Fri, 23 May 2025 17:18:33 +0100 Subject: [PATCH 209/244] EXTI priority (#14401) Make NVIC_PRIO_MPU_INT_EXTI top priority --- src/main/drivers/nvic.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/drivers/nvic.h b/src/main/drivers/nvic.h index fa9efee185..e3b1ef17be 100644 --- a/src/main/drivers/nvic.h +++ b/src/main/drivers/nvic.h @@ -32,7 +32,7 @@ #define NVIC_PRIO_RX_INT_EXTI NVIC_BUILD_PRIORITY(3, 0x0f) #define NVIC_PRIO_RX_BUSY_EXTI NVIC_BUILD_PRIORITY(3, 0x0f) -#define NVIC_PRIO_MPU_INT_EXTI NVIC_BUILD_PRIORITY(0x0f, 0x0f) +#define NVIC_PRIO_MPU_INT_EXTI NVIC_BUILD_PRIORITY(0, 0) // This must be high priority as it drives the scheduler timing #define NVIC_PRIO_MAG_INT_EXTI NVIC_BUILD_PRIORITY(0x0f, 0x0f) #define NVIC_PRIO_WS2811_DMA NVIC_BUILD_PRIORITY(1, 2) // TODO - is there some reason to use high priority? #define NVIC_PRIO_SERIALUART_TXDMA NVIC_BUILD_PRIORITY(1, 1) // Highest of all SERIALUARTx_TXDMA From 748217f4244dc55711956d9bc54eeb37838837bf Mon Sep 17 00:00:00 2001 From: Jay Blackman Date: Sat, 24 May 2025 07:54:47 +1000 Subject: [PATCH 210/244] PICO: Adding pico-sdk as sub module (#14400) --- .gitmodules | 5 + lib/main/pico-sdk | 1 + lib/main/pico-sdk/common/README.md | 3 - .../include/boot/picobin.h | 171 - .../include/boot/picoboot.h | 175 - .../include/boot/picoboot_constants.h | 42 - .../boot_uf2_headers/include/boot/uf2.h | 53 - .../pico-sdk/common/hardware_claim/claim.c | 56 - .../hardware_claim/include/hardware/claim.h | 108 - .../generate_config_header.cmake | 33 - .../common/pico_base_headers/include/pico.h | 38 - .../pico_base_headers/include/pico/assert.h | 52 - .../pico_base_headers/include/pico/config.h | 26 - .../pico_base_headers/include/pico/error.h | 50 - .../pico_base_headers/include/pico/types.h | 121 - .../include/pico/version.h.in | 19 - .../include/pico/binary_info.h | 31 - .../include/pico/binary_info/code.h | 269 - .../include/pico/binary_info/defs.h | 43 - .../include/pico/binary_info/structure.h | 181 - .../include/pico/bit_ops.h | 45 - .../include/pico/divider.h | 323 - .../pico_stdlib_headers/include/pico/stdlib.h | 90 - .../common/pico_sync/critical_section.c | 25 - .../pico_sync/include/pico/critical_section.h | 98 - .../common/pico_sync/include/pico/lock_core.h | 199 - .../common/pico_sync/include/pico/mutex.h | 313 - .../common/pico_sync/include/pico/sem.h | 139 - .../common/pico_sync/include/pico/sync.h | 19 - .../pico-sdk/common/pico_sync/lock_core.c | 13 - lib/main/pico-sdk/common/pico_sync/mutex.c | 228 - lib/main/pico-sdk/common/pico_sync/sem.c | 95 - .../common/pico_time/include/pico/time.h | 844 - .../pico_time/include/pico/timeout_helper.h | 30 - lib/main/pico-sdk/common/pico_time/time.c | 570 - .../common/pico_time/timeout_helper.c | 32 - .../include/pico/usb_reset_interface.h | 28 - lib/main/pico-sdk/common/pico_util/datetime.c | 95 - lib/main/pico-sdk/common/pico_util/doc.h | 4 - .../pico_util/include/pico/util/datetime.h | 47 - .../pico_util/include/pico/util/pheap.h | 309 - .../pico_util/include/pico/util/queue.h | 227 - lib/main/pico-sdk/common/pico_util/pheap.c | 138 - lib/main/pico-sdk/common/pico_util/queue.c | 123 - lib/main/pico-sdk/host/README.md | 14 - lib/main/pico-sdk/host/boot_stage2.c | 3 - .../pico-sdk/host/hardware_divider/divider.c | 9 - .../include/hardware/divider.h | 331 - lib/main/pico-sdk/host/hardware_gpio/gpio.c | 147 - .../hardware_gpio/include/hardware/gpio.h | 172 - .../host/hardware_irq/include/hardware/irq.h | 381 - lib/main/pico-sdk/host/hardware_irq/irq.c | 125 - .../hardware_sync/include/hardware/sync.h | 154 - .../host/hardware_sync/sync_core0_only.c | 140 - .../hardware_timer/include/hardware/timer.h | 48 - lib/main/pico-sdk/host/hardware_timer/timer.c | 125 - .../hardware_uart/include/hardware/uart.h | 100 - lib/main/pico-sdk/host/hardware_uart/uart.c | 130 - lib/main/pico-sdk/host/pico_bit_ops/bit_ops.c | 22 - lib/main/pico-sdk/host/pico_divider/divider.c | 114 - .../pico_multicore/include/pico/multicore.h | 45 - .../include/hardware/platform_defs.h | 31 - .../pico_platform/include/pico/platform.h | 159 - .../host/pico_platform/platform_base.c | 54 - .../host/pico_runtime/include/pico/runtime.h | 36 - .../pico_runtime/include/pico/runtime_init.h | 61 - lib/main/pico-sdk/host/pico_runtime/runtime.c | 11 - .../host/pico_stdio/include/pico/stdio.h | 24 - lib/main/pico-sdk/host/pico_stdio/stdio.c | 23 - lib/main/pico-sdk/host/pico_stdlib/stdlib.c | 27 - .../include/pico/time_adapter.h | 35 - .../host/pico_time_adapter/time_adapter.c | 71 - lib/main/pico-sdk/rp2040/README.md | 6 - .../boot2_helpers/exit_from_boot2.S | 28 - .../boot2_helpers/read_flash_sreg.S | 30 - .../asminclude/boot2_helpers/wait_ssi_ready.S | 26 - .../rp2040/boot_stage2/boot2_at25sf128a.S | 282 - .../rp2040/boot_stage2/boot2_generic_03h.S | 106 - .../rp2040/boot_stage2/boot2_is25lp080.S | 264 - .../rp2040/boot_stage2/boot2_usb_blinky.S | 50 - .../rp2040/boot_stage2/boot2_w25q080.S | 284 - .../rp2040/boot_stage2/boot2_w25x10cl.S | 197 - .../rp2040/boot_stage2/boot_stage2.ld | 13 - .../rp2040/boot_stage2/compile_time_choice.S | 19 - lib/main/pico-sdk/rp2040/boot_stage2/doc.h | 4 - .../boot_stage2/include/boot_stage2/config.h | 91 - .../pico-sdk/rp2040/boot_stage2/pad_checksum | 55 - .../pico-sdk/rp2040/hardware_regs/RP2040.svd | 51025 ------- .../include/hardware/platform_defs.h | 119 - .../hardware_regs/include/hardware/regs/adc.h | 314 - .../include/hardware/regs/addressmap.h | 81 - .../include/hardware/regs/busctrl.h | 327 - .../include/hardware/regs/clocks.h | 2262 - .../hardware_regs/include/hardware/regs/dma.h | 5301 - .../include/hardware/regs/dreq.h | 117 - .../hardware_regs/include/hardware/regs/i2c.h | 2700 - .../include/hardware/regs/intctrl.h | 106 - .../include/hardware/regs/io_bank0.h | 13649 -- .../include/hardware/regs/io_qspi.h | 2675 - .../include/hardware/regs/m0plus.h | 1151 - .../include/hardware/regs/pads_bank0.h | 2302 - .../include/hardware/regs/pads_qspi.h | 456 - .../hardware_regs/include/hardware/regs/pio.h | 2678 - .../hardware_regs/include/hardware/regs/pll.h | 137 - .../hardware_regs/include/hardware/regs/psm.h | 518 - .../hardware_regs/include/hardware/regs/pwm.h | 1420 - .../include/hardware/regs/resets.h | 564 - .../include/hardware/regs/rosc.h | 314 - .../hardware_regs/include/hardware/regs/rtc.h | 396 - .../hardware_regs/include/hardware/regs/sio.h | 1659 - .../hardware_regs/include/hardware/regs/spi.h | 523 - .../hardware_regs/include/hardware/regs/ssi.h | 808 - .../include/hardware/regs/syscfg.h | 252 - .../include/hardware/regs/sysinfo.h | 74 - .../include/hardware/regs/tbman.h | 41 - .../include/hardware/regs/timer.h | 319 - .../include/hardware/regs/uart.h | 1150 - .../hardware_regs/include/hardware/regs/usb.h | 3453 - .../include/hardware/regs/usb_device_dpram.h | 6753 - .../hardware/regs/vreg_and_chip_reset.h | 154 - .../include/hardware/regs/watchdog.h | 226 - .../hardware_regs/include/hardware/regs/xip.h | 190 - .../include/hardware/regs/xosc.h | 165 - .../include/hardware/structs/adc.h | 96 - .../include/hardware/structs/bus_ctrl.h | 9 - .../include/hardware/structs/busctrl.h | 85 - .../include/hardware/structs/clocks.h | 504 - .../include/hardware/structs/dma.h | 239 - .../include/hardware/structs/dma_debug.h | 47 - .../include/hardware/structs/i2c.h | 338 - .../include/hardware/structs/interp.h | 86 - .../include/hardware/structs/io_bank0.h | 236 - .../include/hardware/structs/io_qspi.h | 189 - .../include/hardware/structs/iobank0.h | 9 - .../include/hardware/structs/ioqspi.h | 9 - .../include/hardware/structs/m0plus.h | 197 - .../include/hardware/structs/mpu.h | 66 - .../include/hardware/structs/nvic.h | 69 - .../include/hardware/structs/pads_bank0.h | 49 - .../include/hardware/structs/pads_qspi.h | 49 - .../include/hardware/structs/padsbank0.h | 9 - .../include/hardware/structs/pio.h | 343 - .../include/hardware/structs/pll.h | 61 - .../include/hardware/structs/psm.h | 116 - .../include/hardware/structs/pwm.h | 172 - .../include/hardware/structs/resets.h | 153 - .../include/hardware/structs/rosc.h | 92 - .../include/hardware/structs/rtc.h | 119 - .../include/hardware/structs/scb.h | 74 - .../include/hardware/structs/sio.h | 200 - .../include/hardware/structs/spi.h | 105 - .../include/hardware/structs/ssi.h | 215 - .../include/hardware/structs/syscfg.h | 84 - .../include/hardware/structs/sysinfo.h | 52 - .../include/hardware/structs/systick.h | 57 - .../include/hardware/structs/tbman.h | 38 - .../include/hardware/structs/timer.h | 116 - .../include/hardware/structs/uart.h | 182 - .../include/hardware/structs/usb.h | 476 - .../include/hardware/structs/usb_dpram.h | 128 - .../hardware/structs/vreg_and_chip_reset.h | 54 - .../include/hardware/structs/watchdog.h | 67 - .../include/hardware/structs/xip.h | 76 - .../include/hardware/structs/xip_ctrl.h | 11 - .../include/hardware/structs/xosc.h | 66 - .../pico_platform/include/pico/asm_helper.S | 52 - .../pico_platform/include/pico/platform.h | 210 - .../include/pico/platform/cpu_regs.h | 28 - .../pico-sdk/rp2040/pico_platform/platform.c | 39 - .../rp2040/rp2040_interface_pins.json | 95 - lib/main/pico-sdk/rp2350/README.md | 6 - .../boot2_helpers/exit_from_boot2.S | 20 - .../boot2_helpers/read_flash_sreg.S | 49 - .../asminclude/boot2_helpers/wait_qmi_ready.S | 34 - .../rp2350/boot_stage2/boot2_at25sf128a.S | 278 - .../rp2350/boot_stage2/boot2_generic_03h.S | 121 - .../rp2350/boot_stage2/boot2_is25lp080.S | 260 - .../rp2350/boot_stage2/boot2_usb_blinky.S | 51 - .../rp2350/boot_stage2/boot2_w25q080.S | 343 - .../rp2350/boot_stage2/boot2_w25x10cl.S | 193 - .../rp2350/boot_stage2/boot_stage2.ld | 13 - .../rp2350/boot_stage2/compile_time_choice.S | 19 - lib/main/pico-sdk/rp2350/boot_stage2/doc.h | 4 - .../boot_stage2/include/boot_stage2/config.h | 97 - .../pico-sdk/rp2350/boot_stage2/pad_checksum | 56 - .../pico-sdk/rp2350/hardware_regs/RP2350.svd | 105849 --------------- .../include/hardware/platform_defs.h | 163 - .../include/hardware/regs/accessctrl.h | 4953 - .../hardware_regs/include/hardware/regs/adc.h | 316 - .../include/hardware/regs/addressmap.h | 112 - .../include/hardware/regs/bootram.h | 130 - .../include/hardware/regs/busctrl.h | 753 - .../include/hardware/regs/clocks.h | 2764 - .../include/hardware/regs/coresight_trace.h | 85 - .../hardware_regs/include/hardware/regs/dma.h | 9914 -- .../include/hardware/regs/dreq.h | 147 - .../include/hardware/regs/glitch_detector.h | 213 - .../include/hardware/regs/hstx_ctrl.h | 609 - .../include/hardware/regs/hstx_fifo.h | 62 - .../hardware_regs/include/hardware/regs/i2c.h | 2700 - .../include/hardware/regs/intctrl.h | 184 - .../include/hardware/regs/io_bank0.h | 22339 --- .../include/hardware/regs/io_qspi.h | 3663 - .../hardware_regs/include/hardware/regs/m33.h | 8988 -- .../include/hardware/regs/m33_eppb.h | 80 - .../hardware_regs/include/hardware/regs/otp.h | 3467 - .../include/hardware/regs/otp_data.h | 12373 -- .../include/hardware/regs/pads_bank0.h | 3980 - .../include/hardware/regs/pads_qspi.h | 504 - .../hardware_regs/include/hardware/regs/pio.h | 3417 - .../hardware_regs/include/hardware/regs/pll.h | 199 - .../include/hardware/regs/powman.h | 2194 - .../hardware_regs/include/hardware/regs/psm.h | 741 - .../hardware_regs/include/hardware/regs/pwm.h | 2374 - .../hardware_regs/include/hardware/regs/qmi.h | 1781 - .../include/hardware/regs/resets.h | 641 - .../include/hardware/regs/riscv_dm.h | 1025 - .../include/hardware/regs/rosc.h | 345 - .../include/hardware/regs/rp_ap.h | 729 - .../include/hardware/regs/rvcsr.h | 3154 - .../include/hardware/regs/sha256.h | 228 - .../hardware_regs/include/hardware/regs/sio.h | 2461 - .../hardware_regs/include/hardware/regs/spi.h | 523 - .../include/hardware/regs/syscfg.h | 279 - .../include/hardware/regs/sysinfo.h | 111 - .../include/hardware/regs/tbman.h | 48 - .../include/hardware/regs/ticks.h | 275 - .../include/hardware/regs/timer.h | 346 - .../include/hardware/regs/trng.h | 625 - .../include/hardware/regs/uart.h | 1150 - .../hardware_regs/include/hardware/regs/usb.h | 4209 - .../include/hardware/regs/usb_device_dpram.h | 6753 - .../include/hardware/regs/watchdog.h | 192 - .../hardware_regs/include/hardware/regs/xip.h | 313 - .../include/hardware/regs/xip_aux.h | 123 - .../include/hardware/regs/xosc.h | 175 - .../include/hardware/structs/accessctrl.h | 519 - .../include/hardware/structs/adc.h | 96 - .../include/hardware/structs/bootram.h | 49 - .../include/hardware/structs/bus_ctrl.h | 9 - .../include/hardware/structs/busctrl.h | 90 - .../include/hardware/structs/clocks.h | 580 - .../hardware/structs/coresight_trace.h | 43 - .../include/hardware/structs/dma.h | 336 - .../include/hardware/structs/dma_debug.h | 47 - .../hardware/structs/glitch_detector.h | 71 - .../include/hardware/structs/hstx_ctrl.h | 70 - .../include/hardware/structs/hstx_fifo.h | 45 - .../include/hardware/structs/i2c.h | 338 - .../include/hardware/structs/interp.h | 87 - .../include/hardware/structs/io_bank0.h | 452 - .../include/hardware/structs/io_qspi.h | 316 - .../include/hardware/structs/iobank0.h | 9 - .../include/hardware/structs/ioqspi.h | 9 - .../include/hardware/structs/m33.h | 1651 - .../include/hardware/structs/m33_eppb.h | 50 - .../include/hardware/structs/mpu.h | 126 - .../include/hardware/structs/nvic.h | 94 - .../include/hardware/structs/otp.h | 192 - .../include/hardware/structs/pads_bank0.h | 49 - .../include/hardware/structs/pads_qspi.h | 49 - .../include/hardware/structs/padsbank0.h | 9 - .../include/hardware/structs/pio.h | 380 - .../include/hardware/structs/pll.h | 82 - .../include/hardware/structs/powman.h | 338 - .../include/hardware/structs/psm.h | 148 - .../include/hardware/structs/pwm.h | 252 - .../include/hardware/structs/qmi.h | 125 - .../include/hardware/structs/resets.h | 166 - .../include/hardware/structs/rosc.h | 99 - .../include/hardware/structs/sau.h | 65 - .../include/hardware/structs/scb.h | 264 - .../include/hardware/structs/sha256.h | 53 - .../include/hardware/structs/sio.h | 336 - .../include/hardware/structs/spi.h | 105 - .../include/hardware/structs/syscfg.h | 83 - .../include/hardware/structs/sysinfo.h | 60 - .../include/hardware/structs/systick.h | 62 - .../include/hardware/structs/tbman.h | 39 - .../include/hardware/structs/ticks.h | 63 - .../include/hardware/structs/timer.h | 127 - .../include/hardware/structs/tmds_encode.h | 92 - .../include/hardware/structs/trng.h | 153 - .../include/hardware/structs/uart.h | 182 - .../include/hardware/structs/usb.h | 602 - .../include/hardware/structs/usb_dpram.h | 128 - .../include/hardware/structs/watchdog.h | 59 - .../include/hardware/structs/xip.h | 79 - .../include/hardware/structs/xip_aux.h | 51 - .../include/hardware/structs/xip_ctrl.h | 11 - .../include/hardware/structs/xosc.h | 64 - .../pico_platform/include/pico/asm_helper.S | 71 - .../pico_platform/include/pico/platform.h | 282 - .../include/pico/platform/cpu_regs.h | 30 - .../pico-sdk/rp2350/pico_platform/platform.c | 44 - .../rp2350/rp2350a_interface_pins.json | 95 - .../rp2350/rp2350b_interface_pins.json | 111 - lib/main/pico-sdk/rp2_common/README.md | 7 - .../include/boot/bootrom_constants.h | 340 - .../cmsis/include/cmsis/rename_exceptions.h | 106 - .../stub/CMSIS/Core/Include/cmsis_armcc.h | 885 - .../stub/CMSIS/Core/Include/cmsis_armclang.h | 707 - .../CMSIS/Core/Include/cmsis_armclang_ltm.h | 1928 - .../stub/CMSIS/Core/Include/cmsis_clang.h | 708 - .../stub/CMSIS/Core/Include/cmsis_compiler.h | 292 - .../cmsis/stub/CMSIS/Core/Include/cmsis_gcc.h | 1006 - .../stub/CMSIS/Core/Include/cmsis_iccarm.h | 1002 - .../stub/CMSIS/Core/Include/cmsis_version.h | 44 - .../stub/CMSIS/Core/Include/core_cm0plus.h | 1103 - .../cmsis/stub/CMSIS/Core/Include/core_cm33.h | 3245 - .../Core/Include/m-profile/armv7m_cachel1.h | 439 - .../CMSIS/Core/Include/m-profile/armv7m_mpu.h | 273 - .../Core/Include/m-profile/armv81m_pac.h | 203 - .../CMSIS/Core/Include/m-profile/armv8m_mpu.h | 421 - .../CMSIS/Core/Include/m-profile/armv8m_pmu.h | 335 - .../Core/Include/m-profile/cmsis_armclang_m.h | 818 - .../Core/Include/m-profile/cmsis_clang_m.h | 824 - .../Core/Include/m-profile/cmsis_gcc_m.h | 717 - .../Core/Include/m-profile/cmsis_iccarm_m.h | 1043 - .../Include/m-profile/cmsis_tiarmclang_m.h | 1451 - .../cmsis/stub/CMSIS/Core/Include/mpu_armv7.h | 275 - .../cmsis/stub/CMSIS/Core/Include/mpu_armv8.h | 352 - .../stub/CMSIS/Core/Include/tz_context.h | 68 - .../stub/CMSIS/Device/RP2040/Include/RP2040.h | 2673 - .../Device/RP2040/Include/system_RP2040.h | 65 - .../Device/RP2040/Source/system_RP2040.c | 52 - .../stub/CMSIS/Device/RP2350/Include/RP2350.h | 6068 - .../Device/RP2350/Include/system_RP2350.h | 65 - .../Device/RP2350/Source/system_RP2350.c | 52 - .../rp2_common/cmsis/stub/CMSIS/LICENSE.txt | 201 - .../pico-sdk/rp2_common/hardware_adc/adc.c | 22 - .../hardware_adc/include/hardware/adc.h | 309 - .../include/hardware/address_mapped.h | 184 - .../rp2_common/hardware_boot_lock/boot_lock.c | 35 - .../include/hardware/boot_lock.h | 144 - .../rp2_common/hardware_clocks/clocks.c | 435 - .../hardware_clocks/include/hardware/clocks.h | 473 - .../hardware_clocks/scripts/vcocalc.py | 84 - .../pico-sdk/rp2_common/hardware_dcp/doc.h | 4 - .../include/hardware/dcp_canned.inc.S | 420 - .../include/hardware/dcp_instr.inc.S | 232 - .../rp2_common/hardware_divider/divider.S | 59 - .../rp2_common/hardware_divider/divider.c | 11 - .../include/hardware/divider.h | 515 - .../include/hardware/divider_helper.S | 68 - .../pico-sdk/rp2_common/hardware_dma/dma.c | 112 - .../hardware_dma/include/hardware/dma.h | 948 - .../rp2_common/hardware_exception/exception.c | 105 - .../exception_table_riscv.S | 135 - .../include/hardware/exception.h | 194 - .../rp2_common/hardware_flash/flash.c | 221 - .../hardware_flash/include/hardware/flash.h | 128 - .../pico-sdk/rp2_common/hardware_gpio/gpio.c | 316 - .../hardware_gpio/include/hardware/gpio.h | 1435 - .../include/hardware/gpio_coproc.h | 465 - .../include/hardware/hazard3.h | 62 - .../include/hardware/hazard3/features.h | 29 - .../include/hardware/hazard3/instructions.h | 152 - .../pico-sdk/rp2_common/hardware_i2c/i2c.c | 355 - .../hardware_i2c/include/hardware/i2c.h | 466 - .../hardware_interp/include/hardware/interp.h | 462 - .../rp2_common/hardware_interp/interp.c | 66 - .../hardware_irq/include/hardware/irq.h | 496 - .../pico-sdk/rp2_common/hardware_irq/irq.c | 709 - .../hardware_irq/irq_handler_chain.S | 94 - .../hardware_pio/include/hardware/pio.h | 1889 - .../include/hardware/pio_instructions.h | 484 - .../pico-sdk/rp2_common/hardware_pio/pio.c | 396 - .../hardware_pll/include/hardware/pll.h | 90 - .../pico-sdk/rp2_common/hardware_pll/pll.c | 76 - .../hardware_powman/include/hardware/powman.h | 275 - .../rp2_common/hardware_powman/powman.c | 259 - .../hardware_pwm/include/hardware/pwm.h | 822 - .../hardware_rcp/include/hardware/rcp.h | 1005 - .../hardware_resets/include/hardware/resets.h | 178 - .../hardware_riscv/include/hardware/riscv.h | 179 - .../include/hardware/riscv_platform_timer.h | 145 - .../hardware_rtc/include/hardware/rtc.h | 95 - .../pico-sdk/rp2_common/hardware_rtc/rtc.c | 190 - .../hardware_sha256/include/hardware/sha256.h | 220 - .../rp2_common/hardware_sha256/sha256.c | 15 - .../hardware_spi/include/hardware/spi.h | 436 - .../pico-sdk/rp2_common/hardware_spi/spi.c | 220 - .../hardware_sync/include/hardware/sync.h | 343 - .../pico-sdk/rp2_common/hardware_sync/sync.c | 51 - .../include/hardware/sync/spin_lock.h | 352 - .../hardware_sync_spin_lock/sync_spin_lock.c | 44 - .../hardware_ticks/include/hardware/ticks.h | 78 - .../rp2_common/hardware_ticks/ticks.c | 45 - .../hardware_timer/include/hardware/timer.h | 598 - .../rp2_common/hardware_timer/timer.c | 295 - .../hardware_uart/include/hardware/uart.h | 619 - .../pico-sdk/rp2_common/hardware_uart/uart.c | 237 - .../hardware_vreg/include/hardware/vreg.h | 99 - .../pico-sdk/rp2_common/hardware_vreg/vreg.c | 50 - .../include/hardware/watchdog.h | 143 - .../rp2_common/hardware_watchdog/watchdog.c | 125 - .../hardware_xosc/include/hardware/xosc.h | 59 - .../pico-sdk/rp2_common/hardware_xosc/xosc.c | 63 - .../rp2_common/pico_aon_timer/aon_timer.c | 167 - .../pico_aon_timer/include/pico/aon_timer.h | 128 - .../pico_async_context/async_context_base.c | 123 - .../async_context_freertos.c | 295 - .../pico_async_context/async_context_poll.c | 73 - .../async_context_threadsafe_background.c | 370 - .../include/pico/async_context.h | 471 - .../include/pico/async_context_base.h | 33 - .../include/pico/async_context_freertos.h | 129 - .../include/pico/async_context_poll.h | 49 - .../async_context_threadsafe_background.h | 112 - .../pico-sdk/rp2_common/pico_atomic/atomic.c | 217 - .../pico_atomic/include/stdatomic.h | 49 - .../rp2_common/pico_bit_ops/bit_ops_aeabi.S | 190 - .../rp2_common/pico_bootrom/bootrom.c | 102 - .../rp2_common/pico_bootrom/bootrom_lock.c | 21 - .../pico_bootrom/include/pico/bootrom.h | 1081 - .../pico_bootrom/include/pico/bootrom/lock.h | 69 - .../include/pico/bootrom/sf_table.h | 50 - .../include/pico/bootrom_constants.h | 8 - .../pico_bootsel_via_double_reset.c | 89 - .../rp2_common/pico_btstack/LICENSE.RP | 30 - .../rp2_common/pico_btstack/btstack.BUILD | 197 - .../pico_btstack/btstack_flash_bank.c | 178 - .../btstack_run_loop_async_context.c | 155 - .../pico_btstack/btstack_stdin_pico.c | 60 - .../pico-sdk/rp2_common/pico_btstack/doc.h | 27 - .../include/pico/btstack_flash_bank.h | 39 - .../pico/btstack_run_loop_async_context.h | 29 - .../rp2_common/pico_clib_interface/doc.h | 4 - .../include/llvm_libc/sys/cdefs.h | 30 - .../include/llvm_libc/sys/stat.h | 14 - .../include/llvm_libc/sys/time.h | 34 - .../include/llvm_libc/sys/times.h | 23 - .../include/llvm_libc/sys/types.h | 10 - .../include/llvm_libc/time.h | 23 - .../include/llvm_libc/unistd.h | 20 - .../pico_clib_interface/llvm_libc_interface.c | 110 - .../pico_clib_interface/newlib_interface.c | 199 - .../pico_clib_interface/picolibc_interface.c | 138 - lib/main/pico-sdk/rp2_common/pico_crt0/crt0.S | 544 - .../rp2_common/pico_crt0/crt0_riscv.S | 593 - lib/main/pico-sdk/rp2_common/pico_crt0/doc.h | 8 - .../pico_crt0/embedded_end_block.inc.S | 17 - .../pico_crt0/embedded_start_block.inc.S | 109 - .../pico_crt0/rp2040/memmap_blocked_ram.ld | 286 - .../pico_crt0/rp2040/memmap_copy_to_ram.ld | 287 - .../pico_crt0/rp2040/memmap_default.ld | 286 - .../pico_crt0/rp2040/memmap_no_flash.ld | 249 - .../pico_crt0/rp2350/memmap_copy_to_ram.ld | 309 - .../pico_crt0/rp2350/memmap_default.ld | 302 - .../pico_crt0/rp2350/memmap_no_flash.ld | 256 - .../rp2_common/pico_cxx_options/doc.h | 4 - .../pico_cxx_options/new_delete.cpp | 36 - .../rp2_common/pico_cyw43_arch/cyw43_arch.c | 188 - .../pico_cyw43_arch/cyw43_arch_freertos.c | 84 - .../pico_cyw43_arch/cyw43_arch_poll.c | 76 - .../cyw43_arch_threadsafe_background.c | 81 - .../pico_cyw43_arch/include/pico/cyw43_arch.h | 508 - .../include/pico/cyw43_arch/arch_freertos.h | 20 - .../include/pico/cyw43_arch/arch_poll.h | 12 - .../cyw43_arch/arch_threadsafe_background.h | 12 - .../pico_cyw43_driver/btstack_chipset_cyw43.c | 26 - .../pico_cyw43_driver/btstack_cyw43.c | 74 - .../btstack_hci_transport_cyw43.c | 159 - .../cybt_shared_bus/cybt_shared_bus.c | 431 - .../cybt_shared_bus/cybt_shared_bus_driver.c | 721 - .../cybt_shared_bus/cybt_shared_bus_driver.h | 81 - .../pico_cyw43_driver/cyw43-driver.BUILD | 31 - .../pico_cyw43_driver/cyw43_bus_pio_spi.c | 599 - .../pico_cyw43_driver/cyw43_bus_pio_spi.pio | 61 - .../pico_cyw43_driver/cyw43_driver.c | 200 - .../include/cyw43_configport.h | 236 - .../include/pico/btstack_chipset_cyw43.h | 18 - .../include/pico/btstack_cyw43.h | 44 - .../pico/btstack_hci_transport_cyw43.h | 31 - .../include/pico/cyw43_driver.h | 98 - .../pico_divider/divider_compiler.c | 116 - .../pico_divider/divider_hardware.S | 877 - .../rp2_common/pico_double/double_aeabi_dcp.S | 266 - .../pico_double/double_aeabi_rp2040.S | 847 - .../rp2_common/pico_double/double_conv_m33.S | 387 - .../rp2_common/pico_double/double_fma_dcp.S | 608 - .../pico_double/double_init_rom_rp2040.c | 72 - .../rp2_common/pico_double/double_math.c | 626 - .../rp2_common/pico_double/double_none.S | 85 - .../rp2_common/pico_double/double_sci_m33.S | 1518 - .../pico_double/double_v1_rom_shim_rp2040.S | 2174 - .../pico_double/include/pico/double.h | 79 - .../pico/fix/rp2040_usb_device_enumeration.h | 17 - .../rp2040_usb_device_enumeration.c | 154 - .../pico-sdk/rp2_common/pico_flash/flash.c | 220 - .../pico_flash/include/pico/flash.h | 139 - .../rp2_common/pico_float/float_aeabi_dcp.S | 253 - .../pico_float/float_aeabi_rp2040.S | 776 - .../rp2_common/pico_float/float_conv_m33.S | 369 - .../pico_float/float_init_rom_rp2040.c | 70 - .../rp2_common/pico_float/float_math.c | 582 - .../rp2_common/pico_float/float_none.S | 82 - .../rp2_common/pico_float/float_sci_m33.S | 801 - .../rp2_common/pico_float/float_sci_m33_vfp.S | 856 - .../pico_float/float_single_hazard3.S | 318 - .../pico_float/float_v1_rom_shim_rp2040.S | 346 - .../pico_float/include/pico/float.h | 90 - .../rp2_common/pico_i2c_slave/i2c_slave.c | 98 - .../pico_i2c_slave/include/pico/i2c_slave.h | 75 - .../pico_int64_ops/include/pico/int64_ops.h | 20 - .../pico_int64_ops/pico_int64_ops_aeabi.S | 46 - lib/main/pico-sdk/rp2_common/pico_lwip/doc.h | 46 - .../rp2_common/pico_lwip/include/arch/cc.h | 102 - .../pico_lwip/include/pico/lwip_freertos.h | 52 - .../pico_lwip/include/pico/lwip_nosys.h | 50 - .../pico-sdk/rp2_common/pico_lwip/lwip.BUILD | 181 - .../rp2_common/pico_lwip/lwip_freertos.c | 63 - .../rp2_common/pico_lwip/lwip_nosys.c | 74 - .../rp2_common/pico_lwip/tools/makefsdata.py | 159 - .../pico_malloc/include/pico/malloc.h | 38 - .../pico-sdk/rp2_common/pico_malloc/malloc.c | 100 - .../pico_mbedtls/include/sha256_alt.h | 16 - .../rp2_common/pico_mbedtls/pico_mbedtls.c | 57 - .../pico_mem_ops/include/pico/mem_ops.h | 23 - .../rp2_common/pico_mem_ops/mem_ops.c | 7 - .../rp2_common/pico_mem_ops/mem_ops_aeabi.S | 98 - .../pico_multicore/include/pico/multicore.h | 514 - .../rp2_common/pico_multicore/multicore.c | 385 - .../include/pico/platform/compiler.h | 208 - .../include/pico/platform/panic.h | 44 - .../rp2_common/pico_platform_panic/panic.c | 85 - .../include/pico/platform/sections.h | 185 - .../pico-sdk/rp2_common/pico_printf/LICENSE | 22 - .../pico_printf/include/pico/printf.h | 93 - .../pico-sdk/rp2_common/pico_printf/printf.c | 941 - .../rp2_common/pico_printf/printf_none.S | 29 - .../rp2_common/pico_rand/include/pico/rand.h | 217 - lib/main/pico-sdk/rp2_common/pico_rand/rand.c | 381 - .../pico_runtime/include/pico/runtime.h | 70 - .../rp2_common/pico_runtime/runtime.c | 50 - .../include/pico/runtime_init.h | 455 - .../pico_runtime_init/runtime_init.c | 224 - .../pico_runtime_init/runtime_init_clocks.c | 148 - .../runtime_init_stack_guard.c | 77 - .../pico_sha256/include/pico/sha256.h | 150 - .../pico-sdk/rp2_common/pico_sha256/sha256.c | 185 - .../pico_standard_binary_info/doc.h | 19 - .../standard_binary_info.c | 98 - .../rp2_common/pico_standard_link/doc.h | 10 - .../pico_flash_region.template.ld | 1 - .../pico_stdio/include/pico/stdio.h | 228 - .../pico_stdio/include/pico/stdio/driver.h | 24 - .../pico-sdk/rp2_common/pico_stdio/stdio.c | 391 - .../SEGGER/Config/SEGGER_RTT_Conf.h | 429 - .../pico_stdio_rtt/SEGGER/RTT/SEGGER_RTT.c | 2105 - .../pico_stdio_rtt/SEGGER/RTT/SEGGER_RTT.h | 493 - .../pico_stdio_rtt/include/pico/stdio_rtt.h | 49 - .../rp2_common/pico_stdio_rtt/stdio_rtt.c | 42 - .../include/pico/stdio_semihosting.h | 49 - .../stdio_semihosting.c | 77 - .../pico_stdio_uart/include/pico/stdio_uart.h | 108 - .../rp2_common/pico_stdio_uart/stdio_uart.c | 202 - .../pico_stdio_usb/include/pico/stdio_usb.h | 163 - .../include/pico/stdio_usb/reset_interface.h | 13 - .../pico_stdio_usb/include/tusb_config.h | 50 - .../pico_stdio_usb/reset_interface.c | 185 - .../rp2_common/pico_stdio_usb/stdio_usb.c | 305 - .../pico_stdio_usb/stdio_usb_descriptors.c | 188 - .../pico-sdk/rp2_common/pico_stdlib/stdlib.c | 26 - .../include/pico/time_adapter.h | 103 - .../pico_unique_id/include/pico/unique_id.h | 107 - .../rp2_common/pico_unique_id/unique_id.c | 61 - lib/main/pico-sdk/rp2_common/tinyusb/doc.h | 7 - .../rp2_common/tinyusb/include/bsp/board.h | 11 - .../pico-sdk/rp2_common/tinyusb/tinyusb.BUILD | 42 - 571 files changed, 6 insertions(+), 434481 deletions(-) create mode 160000 lib/main/pico-sdk delete mode 100644 lib/main/pico-sdk/common/README.md delete mode 100644 lib/main/pico-sdk/common/boot_picobin_headers/include/boot/picobin.h delete mode 100644 lib/main/pico-sdk/common/boot_picoboot_headers/include/boot/picoboot.h delete mode 100644 lib/main/pico-sdk/common/boot_picoboot_headers/include/boot/picoboot_constants.h delete mode 100644 lib/main/pico-sdk/common/boot_uf2_headers/include/boot/uf2.h delete mode 100644 lib/main/pico-sdk/common/hardware_claim/claim.c delete mode 100644 lib/main/pico-sdk/common/hardware_claim/include/hardware/claim.h delete mode 100644 lib/main/pico-sdk/common/pico_base_headers/generate_config_header.cmake delete mode 100644 lib/main/pico-sdk/common/pico_base_headers/include/pico.h delete mode 100644 lib/main/pico-sdk/common/pico_base_headers/include/pico/assert.h delete mode 100644 lib/main/pico-sdk/common/pico_base_headers/include/pico/config.h delete mode 100644 lib/main/pico-sdk/common/pico_base_headers/include/pico/error.h delete mode 100644 lib/main/pico-sdk/common/pico_base_headers/include/pico/types.h delete mode 100644 lib/main/pico-sdk/common/pico_base_headers/include/pico/version.h.in delete mode 100644 lib/main/pico-sdk/common/pico_binary_info/include/pico/binary_info.h delete mode 100644 lib/main/pico-sdk/common/pico_binary_info/include/pico/binary_info/code.h delete mode 100644 lib/main/pico-sdk/common/pico_binary_info/include/pico/binary_info/defs.h delete mode 100644 lib/main/pico-sdk/common/pico_binary_info/include/pico/binary_info/structure.h delete mode 100644 lib/main/pico-sdk/common/pico_bit_ops_headers/include/pico/bit_ops.h delete mode 100644 lib/main/pico-sdk/common/pico_divider_headers/include/pico/divider.h delete mode 100644 lib/main/pico-sdk/common/pico_stdlib_headers/include/pico/stdlib.h delete mode 100644 lib/main/pico-sdk/common/pico_sync/critical_section.c delete mode 100644 lib/main/pico-sdk/common/pico_sync/include/pico/critical_section.h delete mode 100644 lib/main/pico-sdk/common/pico_sync/include/pico/lock_core.h delete mode 100644 lib/main/pico-sdk/common/pico_sync/include/pico/mutex.h delete mode 100644 lib/main/pico-sdk/common/pico_sync/include/pico/sem.h delete mode 100644 lib/main/pico-sdk/common/pico_sync/include/pico/sync.h delete mode 100644 lib/main/pico-sdk/common/pico_sync/lock_core.c delete mode 100644 lib/main/pico-sdk/common/pico_sync/mutex.c delete mode 100644 lib/main/pico-sdk/common/pico_sync/sem.c delete mode 100644 lib/main/pico-sdk/common/pico_time/include/pico/time.h delete mode 100644 lib/main/pico-sdk/common/pico_time/include/pico/timeout_helper.h delete mode 100644 lib/main/pico-sdk/common/pico_time/time.c delete mode 100644 lib/main/pico-sdk/common/pico_time/timeout_helper.c delete mode 100644 lib/main/pico-sdk/common/pico_usb_reset_interface_headers/include/pico/usb_reset_interface.h delete mode 100644 lib/main/pico-sdk/common/pico_util/datetime.c delete mode 100644 lib/main/pico-sdk/common/pico_util/doc.h delete mode 100644 lib/main/pico-sdk/common/pico_util/include/pico/util/datetime.h delete mode 100644 lib/main/pico-sdk/common/pico_util/include/pico/util/pheap.h delete mode 100644 lib/main/pico-sdk/common/pico_util/include/pico/util/queue.h delete mode 100644 lib/main/pico-sdk/common/pico_util/pheap.c delete mode 100644 lib/main/pico-sdk/common/pico_util/queue.c delete mode 100644 lib/main/pico-sdk/host/README.md delete mode 100644 lib/main/pico-sdk/host/boot_stage2.c delete mode 100644 lib/main/pico-sdk/host/hardware_divider/divider.c delete mode 100644 lib/main/pico-sdk/host/hardware_divider/include/hardware/divider.h delete mode 100644 lib/main/pico-sdk/host/hardware_gpio/gpio.c delete mode 100644 lib/main/pico-sdk/host/hardware_gpio/include/hardware/gpio.h delete mode 100644 lib/main/pico-sdk/host/hardware_irq/include/hardware/irq.h delete mode 100644 lib/main/pico-sdk/host/hardware_irq/irq.c delete mode 100644 lib/main/pico-sdk/host/hardware_sync/include/hardware/sync.h delete mode 100644 lib/main/pico-sdk/host/hardware_sync/sync_core0_only.c delete mode 100644 lib/main/pico-sdk/host/hardware_timer/include/hardware/timer.h delete mode 100644 lib/main/pico-sdk/host/hardware_timer/timer.c delete mode 100644 lib/main/pico-sdk/host/hardware_uart/include/hardware/uart.h delete mode 100644 lib/main/pico-sdk/host/hardware_uart/uart.c delete mode 100644 lib/main/pico-sdk/host/pico_bit_ops/bit_ops.c delete mode 100644 lib/main/pico-sdk/host/pico_divider/divider.c delete mode 100644 lib/main/pico-sdk/host/pico_multicore/include/pico/multicore.h delete mode 100644 lib/main/pico-sdk/host/pico_platform/include/hardware/platform_defs.h delete mode 100644 lib/main/pico-sdk/host/pico_platform/include/pico/platform.h delete mode 100644 lib/main/pico-sdk/host/pico_platform/platform_base.c delete mode 100644 lib/main/pico-sdk/host/pico_runtime/include/pico/runtime.h delete mode 100644 lib/main/pico-sdk/host/pico_runtime/include/pico/runtime_init.h delete mode 100644 lib/main/pico-sdk/host/pico_runtime/runtime.c delete mode 100644 lib/main/pico-sdk/host/pico_stdio/include/pico/stdio.h delete mode 100644 lib/main/pico-sdk/host/pico_stdio/stdio.c delete mode 100644 lib/main/pico-sdk/host/pico_stdlib/stdlib.c delete mode 100644 lib/main/pico-sdk/host/pico_time_adapter/include/pico/time_adapter.h delete mode 100644 lib/main/pico-sdk/host/pico_time_adapter/time_adapter.c delete mode 100644 lib/main/pico-sdk/rp2040/README.md delete mode 100644 lib/main/pico-sdk/rp2040/boot_stage2/asminclude/boot2_helpers/exit_from_boot2.S delete mode 100644 lib/main/pico-sdk/rp2040/boot_stage2/asminclude/boot2_helpers/read_flash_sreg.S delete mode 100644 lib/main/pico-sdk/rp2040/boot_stage2/asminclude/boot2_helpers/wait_ssi_ready.S delete mode 100644 lib/main/pico-sdk/rp2040/boot_stage2/boot2_at25sf128a.S delete mode 100644 lib/main/pico-sdk/rp2040/boot_stage2/boot2_generic_03h.S delete mode 100644 lib/main/pico-sdk/rp2040/boot_stage2/boot2_is25lp080.S delete mode 100644 lib/main/pico-sdk/rp2040/boot_stage2/boot2_usb_blinky.S delete mode 100644 lib/main/pico-sdk/rp2040/boot_stage2/boot2_w25q080.S delete mode 100644 lib/main/pico-sdk/rp2040/boot_stage2/boot2_w25x10cl.S delete mode 100644 lib/main/pico-sdk/rp2040/boot_stage2/boot_stage2.ld delete mode 100644 lib/main/pico-sdk/rp2040/boot_stage2/compile_time_choice.S delete mode 100644 lib/main/pico-sdk/rp2040/boot_stage2/doc.h delete mode 100644 lib/main/pico-sdk/rp2040/boot_stage2/include/boot_stage2/config.h delete mode 100644 lib/main/pico-sdk/rp2040/boot_stage2/pad_checksum delete mode 100644 lib/main/pico-sdk/rp2040/hardware_regs/RP2040.svd delete mode 100644 lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/platform_defs.h delete mode 100644 lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/adc.h delete mode 100644 lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/addressmap.h delete mode 100644 lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/busctrl.h delete mode 100644 lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/clocks.h delete mode 100644 lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/dma.h delete mode 100644 lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/dreq.h delete mode 100644 lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/i2c.h delete mode 100644 lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/intctrl.h delete mode 100644 lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/io_bank0.h delete mode 100644 lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/io_qspi.h delete mode 100644 lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/m0plus.h delete mode 100644 lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/pads_bank0.h delete mode 100644 lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/pads_qspi.h delete mode 100644 lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/pio.h delete mode 100644 lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/pll.h delete mode 100644 lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/psm.h delete mode 100644 lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/pwm.h delete mode 100644 lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/resets.h delete mode 100644 lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/rosc.h delete mode 100644 lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/rtc.h delete mode 100644 lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/sio.h delete mode 100644 lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/spi.h delete mode 100644 lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/ssi.h delete mode 100644 lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/syscfg.h delete mode 100644 lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/sysinfo.h delete mode 100644 lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/tbman.h delete mode 100644 lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/timer.h delete mode 100644 lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/uart.h delete mode 100644 lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/usb.h delete mode 100644 lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/usb_device_dpram.h delete mode 100644 lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/vreg_and_chip_reset.h delete mode 100644 lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/watchdog.h delete mode 100644 lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/xip.h delete mode 100644 lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/xosc.h delete mode 100644 lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/adc.h delete mode 100644 lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/bus_ctrl.h delete mode 100644 lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/busctrl.h delete mode 100644 lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/clocks.h delete mode 100644 lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/dma.h delete mode 100644 lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/dma_debug.h delete mode 100644 lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/i2c.h delete mode 100644 lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/interp.h delete mode 100644 lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/io_bank0.h delete mode 100644 lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/io_qspi.h delete mode 100644 lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/iobank0.h delete mode 100644 lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/ioqspi.h delete mode 100644 lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/m0plus.h delete mode 100644 lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/mpu.h delete mode 100644 lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/nvic.h delete mode 100644 lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/pads_bank0.h delete mode 100644 lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/pads_qspi.h delete mode 100644 lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/padsbank0.h delete mode 100644 lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/pio.h delete mode 100644 lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/pll.h delete mode 100644 lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/psm.h delete mode 100644 lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/pwm.h delete mode 100644 lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/resets.h delete mode 100644 lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/rosc.h delete mode 100644 lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/rtc.h delete mode 100644 lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/scb.h delete mode 100644 lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/sio.h delete mode 100644 lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/spi.h delete mode 100644 lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/ssi.h delete mode 100644 lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/syscfg.h delete mode 100644 lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/sysinfo.h delete mode 100644 lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/systick.h delete mode 100644 lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/tbman.h delete mode 100644 lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/timer.h delete mode 100644 lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/uart.h delete mode 100644 lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/usb.h delete mode 100644 lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/usb_dpram.h delete mode 100644 lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/vreg_and_chip_reset.h delete mode 100644 lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/watchdog.h delete mode 100644 lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/xip.h delete mode 100644 lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/xip_ctrl.h delete mode 100644 lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/xosc.h delete mode 100644 lib/main/pico-sdk/rp2040/pico_platform/include/pico/asm_helper.S delete mode 100644 lib/main/pico-sdk/rp2040/pico_platform/include/pico/platform.h delete mode 100644 lib/main/pico-sdk/rp2040/pico_platform/include/pico/platform/cpu_regs.h delete mode 100644 lib/main/pico-sdk/rp2040/pico_platform/platform.c delete mode 100644 lib/main/pico-sdk/rp2040/rp2040_interface_pins.json delete mode 100644 lib/main/pico-sdk/rp2350/README.md delete mode 100644 lib/main/pico-sdk/rp2350/boot_stage2/asminclude/boot2_helpers/exit_from_boot2.S delete mode 100644 lib/main/pico-sdk/rp2350/boot_stage2/asminclude/boot2_helpers/read_flash_sreg.S delete mode 100644 lib/main/pico-sdk/rp2350/boot_stage2/asminclude/boot2_helpers/wait_qmi_ready.S delete mode 100644 lib/main/pico-sdk/rp2350/boot_stage2/boot2_at25sf128a.S delete mode 100644 lib/main/pico-sdk/rp2350/boot_stage2/boot2_generic_03h.S delete mode 100644 lib/main/pico-sdk/rp2350/boot_stage2/boot2_is25lp080.S delete mode 100644 lib/main/pico-sdk/rp2350/boot_stage2/boot2_usb_blinky.S delete mode 100644 lib/main/pico-sdk/rp2350/boot_stage2/boot2_w25q080.S delete mode 100644 lib/main/pico-sdk/rp2350/boot_stage2/boot2_w25x10cl.S delete mode 100644 lib/main/pico-sdk/rp2350/boot_stage2/boot_stage2.ld delete mode 100644 lib/main/pico-sdk/rp2350/boot_stage2/compile_time_choice.S delete mode 100644 lib/main/pico-sdk/rp2350/boot_stage2/doc.h delete mode 100644 lib/main/pico-sdk/rp2350/boot_stage2/include/boot_stage2/config.h delete mode 100644 lib/main/pico-sdk/rp2350/boot_stage2/pad_checksum delete mode 100644 lib/main/pico-sdk/rp2350/hardware_regs/RP2350.svd delete mode 100644 lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/platform_defs.h delete mode 100644 lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/accessctrl.h delete mode 100644 lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/adc.h delete mode 100644 lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/addressmap.h delete mode 100644 lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/bootram.h delete mode 100644 lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/busctrl.h delete mode 100644 lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/clocks.h delete mode 100644 lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/coresight_trace.h delete mode 100644 lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/dma.h delete mode 100644 lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/dreq.h delete mode 100644 lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/glitch_detector.h delete mode 100644 lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/hstx_ctrl.h delete mode 100644 lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/hstx_fifo.h delete mode 100644 lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/i2c.h delete mode 100644 lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/intctrl.h delete mode 100644 lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/io_bank0.h delete mode 100644 lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/io_qspi.h delete mode 100644 lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/m33.h delete mode 100644 lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/m33_eppb.h delete mode 100644 lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/otp.h delete mode 100644 lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/otp_data.h delete mode 100644 lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/pads_bank0.h delete mode 100644 lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/pads_qspi.h delete mode 100644 lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/pio.h delete mode 100644 lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/pll.h delete mode 100644 lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/powman.h delete mode 100644 lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/psm.h delete mode 100644 lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/pwm.h delete mode 100644 lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/qmi.h delete mode 100644 lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/resets.h delete mode 100644 lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/riscv_dm.h delete mode 100644 lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/rosc.h delete mode 100644 lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/rp_ap.h delete mode 100644 lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/rvcsr.h delete mode 100644 lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/sha256.h delete mode 100644 lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/sio.h delete mode 100644 lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/spi.h delete mode 100644 lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/syscfg.h delete mode 100644 lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/sysinfo.h delete mode 100644 lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/tbman.h delete mode 100644 lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/ticks.h delete mode 100644 lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/timer.h delete mode 100644 lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/trng.h delete mode 100644 lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/uart.h delete mode 100644 lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/usb.h delete mode 100644 lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/usb_device_dpram.h delete mode 100644 lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/watchdog.h delete mode 100644 lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/xip.h delete mode 100644 lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/xip_aux.h delete mode 100644 lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/xosc.h delete mode 100644 lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/accessctrl.h delete mode 100644 lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/adc.h delete mode 100644 lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/bootram.h delete mode 100644 lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/bus_ctrl.h delete mode 100644 lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/busctrl.h delete mode 100644 lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/clocks.h delete mode 100644 lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/coresight_trace.h delete mode 100644 lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/dma.h delete mode 100644 lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/dma_debug.h delete mode 100644 lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/glitch_detector.h delete mode 100644 lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/hstx_ctrl.h delete mode 100644 lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/hstx_fifo.h delete mode 100644 lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/i2c.h delete mode 100644 lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/interp.h delete mode 100644 lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/io_bank0.h delete mode 100644 lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/io_qspi.h delete mode 100644 lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/iobank0.h delete mode 100644 lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/ioqspi.h delete mode 100644 lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/m33.h delete mode 100644 lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/m33_eppb.h delete mode 100644 lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/mpu.h delete mode 100644 lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/nvic.h delete mode 100644 lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/otp.h delete mode 100644 lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/pads_bank0.h delete mode 100644 lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/pads_qspi.h delete mode 100644 lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/padsbank0.h delete mode 100644 lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/pio.h delete mode 100644 lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/pll.h delete mode 100644 lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/powman.h delete mode 100644 lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/psm.h delete mode 100644 lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/pwm.h delete mode 100644 lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/qmi.h delete mode 100644 lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/resets.h delete mode 100644 lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/rosc.h delete mode 100644 lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/sau.h delete mode 100644 lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/scb.h delete mode 100644 lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/sha256.h delete mode 100644 lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/sio.h delete mode 100644 lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/spi.h delete mode 100644 lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/syscfg.h delete mode 100644 lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/sysinfo.h delete mode 100644 lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/systick.h delete mode 100644 lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/tbman.h delete mode 100644 lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/ticks.h delete mode 100644 lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/timer.h delete mode 100644 lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/tmds_encode.h delete mode 100644 lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/trng.h delete mode 100644 lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/uart.h delete mode 100644 lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/usb.h delete mode 100644 lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/usb_dpram.h delete mode 100644 lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/watchdog.h delete mode 100644 lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/xip.h delete mode 100644 lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/xip_aux.h delete mode 100644 lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/xip_ctrl.h delete mode 100644 lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/xosc.h delete mode 100644 lib/main/pico-sdk/rp2350/pico_platform/include/pico/asm_helper.S delete mode 100644 lib/main/pico-sdk/rp2350/pico_platform/include/pico/platform.h delete mode 100644 lib/main/pico-sdk/rp2350/pico_platform/include/pico/platform/cpu_regs.h delete mode 100644 lib/main/pico-sdk/rp2350/pico_platform/platform.c delete mode 100644 lib/main/pico-sdk/rp2350/rp2350a_interface_pins.json delete mode 100644 lib/main/pico-sdk/rp2350/rp2350b_interface_pins.json delete mode 100644 lib/main/pico-sdk/rp2_common/README.md delete mode 100644 lib/main/pico-sdk/rp2_common/boot_bootrom_headers/include/boot/bootrom_constants.h delete mode 100644 lib/main/pico-sdk/rp2_common/cmsis/include/cmsis/rename_exceptions.h delete mode 100644 lib/main/pico-sdk/rp2_common/cmsis/stub/CMSIS/Core/Include/cmsis_armcc.h delete mode 100644 lib/main/pico-sdk/rp2_common/cmsis/stub/CMSIS/Core/Include/cmsis_armclang.h delete mode 100644 lib/main/pico-sdk/rp2_common/cmsis/stub/CMSIS/Core/Include/cmsis_armclang_ltm.h delete mode 100644 lib/main/pico-sdk/rp2_common/cmsis/stub/CMSIS/Core/Include/cmsis_clang.h delete mode 100644 lib/main/pico-sdk/rp2_common/cmsis/stub/CMSIS/Core/Include/cmsis_compiler.h delete mode 100644 lib/main/pico-sdk/rp2_common/cmsis/stub/CMSIS/Core/Include/cmsis_gcc.h delete mode 100644 lib/main/pico-sdk/rp2_common/cmsis/stub/CMSIS/Core/Include/cmsis_iccarm.h delete mode 100644 lib/main/pico-sdk/rp2_common/cmsis/stub/CMSIS/Core/Include/cmsis_version.h delete mode 100644 lib/main/pico-sdk/rp2_common/cmsis/stub/CMSIS/Core/Include/core_cm0plus.h delete mode 100644 lib/main/pico-sdk/rp2_common/cmsis/stub/CMSIS/Core/Include/core_cm33.h delete mode 100644 lib/main/pico-sdk/rp2_common/cmsis/stub/CMSIS/Core/Include/m-profile/armv7m_cachel1.h delete mode 100644 lib/main/pico-sdk/rp2_common/cmsis/stub/CMSIS/Core/Include/m-profile/armv7m_mpu.h delete mode 100644 lib/main/pico-sdk/rp2_common/cmsis/stub/CMSIS/Core/Include/m-profile/armv81m_pac.h delete mode 100644 lib/main/pico-sdk/rp2_common/cmsis/stub/CMSIS/Core/Include/m-profile/armv8m_mpu.h delete mode 100644 lib/main/pico-sdk/rp2_common/cmsis/stub/CMSIS/Core/Include/m-profile/armv8m_pmu.h delete mode 100644 lib/main/pico-sdk/rp2_common/cmsis/stub/CMSIS/Core/Include/m-profile/cmsis_armclang_m.h delete mode 100644 lib/main/pico-sdk/rp2_common/cmsis/stub/CMSIS/Core/Include/m-profile/cmsis_clang_m.h delete mode 100644 lib/main/pico-sdk/rp2_common/cmsis/stub/CMSIS/Core/Include/m-profile/cmsis_gcc_m.h delete mode 100644 lib/main/pico-sdk/rp2_common/cmsis/stub/CMSIS/Core/Include/m-profile/cmsis_iccarm_m.h delete mode 100644 lib/main/pico-sdk/rp2_common/cmsis/stub/CMSIS/Core/Include/m-profile/cmsis_tiarmclang_m.h delete mode 100644 lib/main/pico-sdk/rp2_common/cmsis/stub/CMSIS/Core/Include/mpu_armv7.h delete mode 100644 lib/main/pico-sdk/rp2_common/cmsis/stub/CMSIS/Core/Include/mpu_armv8.h delete mode 100644 lib/main/pico-sdk/rp2_common/cmsis/stub/CMSIS/Core/Include/tz_context.h delete mode 100644 lib/main/pico-sdk/rp2_common/cmsis/stub/CMSIS/Device/RP2040/Include/RP2040.h delete mode 100644 lib/main/pico-sdk/rp2_common/cmsis/stub/CMSIS/Device/RP2040/Include/system_RP2040.h delete mode 100644 lib/main/pico-sdk/rp2_common/cmsis/stub/CMSIS/Device/RP2040/Source/system_RP2040.c delete mode 100644 lib/main/pico-sdk/rp2_common/cmsis/stub/CMSIS/Device/RP2350/Include/RP2350.h delete mode 100644 lib/main/pico-sdk/rp2_common/cmsis/stub/CMSIS/Device/RP2350/Include/system_RP2350.h delete mode 100644 lib/main/pico-sdk/rp2_common/cmsis/stub/CMSIS/Device/RP2350/Source/system_RP2350.c delete mode 100644 lib/main/pico-sdk/rp2_common/cmsis/stub/CMSIS/LICENSE.txt delete mode 100644 lib/main/pico-sdk/rp2_common/hardware_adc/adc.c delete mode 100644 lib/main/pico-sdk/rp2_common/hardware_adc/include/hardware/adc.h delete mode 100644 lib/main/pico-sdk/rp2_common/hardware_base/include/hardware/address_mapped.h delete mode 100644 lib/main/pico-sdk/rp2_common/hardware_boot_lock/boot_lock.c delete mode 100644 lib/main/pico-sdk/rp2_common/hardware_boot_lock/include/hardware/boot_lock.h delete mode 100644 lib/main/pico-sdk/rp2_common/hardware_clocks/clocks.c delete mode 100644 lib/main/pico-sdk/rp2_common/hardware_clocks/include/hardware/clocks.h delete mode 100644 lib/main/pico-sdk/rp2_common/hardware_clocks/scripts/vcocalc.py delete mode 100644 lib/main/pico-sdk/rp2_common/hardware_dcp/doc.h delete mode 100644 lib/main/pico-sdk/rp2_common/hardware_dcp/include/hardware/dcp_canned.inc.S delete mode 100644 lib/main/pico-sdk/rp2_common/hardware_dcp/include/hardware/dcp_instr.inc.S delete mode 100644 lib/main/pico-sdk/rp2_common/hardware_divider/divider.S delete mode 100644 lib/main/pico-sdk/rp2_common/hardware_divider/divider.c delete mode 100644 lib/main/pico-sdk/rp2_common/hardware_divider/include/hardware/divider.h delete mode 100644 lib/main/pico-sdk/rp2_common/hardware_divider/include/hardware/divider_helper.S delete mode 100644 lib/main/pico-sdk/rp2_common/hardware_dma/dma.c delete mode 100644 lib/main/pico-sdk/rp2_common/hardware_dma/include/hardware/dma.h delete mode 100644 lib/main/pico-sdk/rp2_common/hardware_exception/exception.c delete mode 100644 lib/main/pico-sdk/rp2_common/hardware_exception/exception_table_riscv.S delete mode 100644 lib/main/pico-sdk/rp2_common/hardware_exception/include/hardware/exception.h delete mode 100644 lib/main/pico-sdk/rp2_common/hardware_flash/flash.c delete mode 100644 lib/main/pico-sdk/rp2_common/hardware_flash/include/hardware/flash.h delete mode 100644 lib/main/pico-sdk/rp2_common/hardware_gpio/gpio.c delete mode 100644 lib/main/pico-sdk/rp2_common/hardware_gpio/include/hardware/gpio.h delete mode 100644 lib/main/pico-sdk/rp2_common/hardware_gpio/include/hardware/gpio_coproc.h delete mode 100644 lib/main/pico-sdk/rp2_common/hardware_hazard3/include/hardware/hazard3.h delete mode 100644 lib/main/pico-sdk/rp2_common/hardware_hazard3/include/hardware/hazard3/features.h delete mode 100644 lib/main/pico-sdk/rp2_common/hardware_hazard3/include/hardware/hazard3/instructions.h delete mode 100644 lib/main/pico-sdk/rp2_common/hardware_i2c/i2c.c delete mode 100644 lib/main/pico-sdk/rp2_common/hardware_i2c/include/hardware/i2c.h delete mode 100644 lib/main/pico-sdk/rp2_common/hardware_interp/include/hardware/interp.h delete mode 100644 lib/main/pico-sdk/rp2_common/hardware_interp/interp.c delete mode 100644 lib/main/pico-sdk/rp2_common/hardware_irq/include/hardware/irq.h delete mode 100644 lib/main/pico-sdk/rp2_common/hardware_irq/irq.c delete mode 100644 lib/main/pico-sdk/rp2_common/hardware_irq/irq_handler_chain.S delete mode 100644 lib/main/pico-sdk/rp2_common/hardware_pio/include/hardware/pio.h delete mode 100644 lib/main/pico-sdk/rp2_common/hardware_pio/include/hardware/pio_instructions.h delete mode 100644 lib/main/pico-sdk/rp2_common/hardware_pio/pio.c delete mode 100644 lib/main/pico-sdk/rp2_common/hardware_pll/include/hardware/pll.h delete mode 100644 lib/main/pico-sdk/rp2_common/hardware_pll/pll.c delete mode 100644 lib/main/pico-sdk/rp2_common/hardware_powman/include/hardware/powman.h delete mode 100644 lib/main/pico-sdk/rp2_common/hardware_powman/powman.c delete mode 100644 lib/main/pico-sdk/rp2_common/hardware_pwm/include/hardware/pwm.h delete mode 100644 lib/main/pico-sdk/rp2_common/hardware_rcp/include/hardware/rcp.h delete mode 100644 lib/main/pico-sdk/rp2_common/hardware_resets/include/hardware/resets.h delete mode 100644 lib/main/pico-sdk/rp2_common/hardware_riscv/include/hardware/riscv.h delete mode 100644 lib/main/pico-sdk/rp2_common/hardware_riscv_platform_timer/include/hardware/riscv_platform_timer.h delete mode 100644 lib/main/pico-sdk/rp2_common/hardware_rtc/include/hardware/rtc.h delete mode 100644 lib/main/pico-sdk/rp2_common/hardware_rtc/rtc.c delete mode 100644 lib/main/pico-sdk/rp2_common/hardware_sha256/include/hardware/sha256.h delete mode 100644 lib/main/pico-sdk/rp2_common/hardware_sha256/sha256.c delete mode 100644 lib/main/pico-sdk/rp2_common/hardware_spi/include/hardware/spi.h delete mode 100644 lib/main/pico-sdk/rp2_common/hardware_spi/spi.c delete mode 100644 lib/main/pico-sdk/rp2_common/hardware_sync/include/hardware/sync.h delete mode 100644 lib/main/pico-sdk/rp2_common/hardware_sync/sync.c delete mode 100644 lib/main/pico-sdk/rp2_common/hardware_sync_spin_lock/include/hardware/sync/spin_lock.h delete mode 100644 lib/main/pico-sdk/rp2_common/hardware_sync_spin_lock/sync_spin_lock.c delete mode 100644 lib/main/pico-sdk/rp2_common/hardware_ticks/include/hardware/ticks.h delete mode 100644 lib/main/pico-sdk/rp2_common/hardware_ticks/ticks.c delete mode 100644 lib/main/pico-sdk/rp2_common/hardware_timer/include/hardware/timer.h delete mode 100644 lib/main/pico-sdk/rp2_common/hardware_timer/timer.c delete mode 100644 lib/main/pico-sdk/rp2_common/hardware_uart/include/hardware/uart.h delete mode 100644 lib/main/pico-sdk/rp2_common/hardware_uart/uart.c delete mode 100644 lib/main/pico-sdk/rp2_common/hardware_vreg/include/hardware/vreg.h delete mode 100644 lib/main/pico-sdk/rp2_common/hardware_vreg/vreg.c delete mode 100644 lib/main/pico-sdk/rp2_common/hardware_watchdog/include/hardware/watchdog.h delete mode 100644 lib/main/pico-sdk/rp2_common/hardware_watchdog/watchdog.c delete mode 100644 lib/main/pico-sdk/rp2_common/hardware_xosc/include/hardware/xosc.h delete mode 100644 lib/main/pico-sdk/rp2_common/hardware_xosc/xosc.c delete mode 100644 lib/main/pico-sdk/rp2_common/pico_aon_timer/aon_timer.c delete mode 100644 lib/main/pico-sdk/rp2_common/pico_aon_timer/include/pico/aon_timer.h delete mode 100644 lib/main/pico-sdk/rp2_common/pico_async_context/async_context_base.c delete mode 100644 lib/main/pico-sdk/rp2_common/pico_async_context/async_context_freertos.c delete mode 100644 lib/main/pico-sdk/rp2_common/pico_async_context/async_context_poll.c delete mode 100644 lib/main/pico-sdk/rp2_common/pico_async_context/async_context_threadsafe_background.c delete mode 100644 lib/main/pico-sdk/rp2_common/pico_async_context/include/pico/async_context.h delete mode 100644 lib/main/pico-sdk/rp2_common/pico_async_context/include/pico/async_context_base.h delete mode 100644 lib/main/pico-sdk/rp2_common/pico_async_context/include/pico/async_context_freertos.h delete mode 100644 lib/main/pico-sdk/rp2_common/pico_async_context/include/pico/async_context_poll.h delete mode 100644 lib/main/pico-sdk/rp2_common/pico_async_context/include/pico/async_context_threadsafe_background.h delete mode 100644 lib/main/pico-sdk/rp2_common/pico_atomic/atomic.c delete mode 100644 lib/main/pico-sdk/rp2_common/pico_atomic/include/stdatomic.h delete mode 100644 lib/main/pico-sdk/rp2_common/pico_bit_ops/bit_ops_aeabi.S delete mode 100644 lib/main/pico-sdk/rp2_common/pico_bootrom/bootrom.c delete mode 100644 lib/main/pico-sdk/rp2_common/pico_bootrom/bootrom_lock.c delete mode 100644 lib/main/pico-sdk/rp2_common/pico_bootrom/include/pico/bootrom.h delete mode 100644 lib/main/pico-sdk/rp2_common/pico_bootrom/include/pico/bootrom/lock.h delete mode 100644 lib/main/pico-sdk/rp2_common/pico_bootrom/include/pico/bootrom/sf_table.h delete mode 100644 lib/main/pico-sdk/rp2_common/pico_bootrom/include/pico/bootrom_constants.h delete mode 100644 lib/main/pico-sdk/rp2_common/pico_bootsel_via_double_reset/pico_bootsel_via_double_reset.c delete mode 100644 lib/main/pico-sdk/rp2_common/pico_btstack/LICENSE.RP delete mode 100644 lib/main/pico-sdk/rp2_common/pico_btstack/btstack.BUILD delete mode 100644 lib/main/pico-sdk/rp2_common/pico_btstack/btstack_flash_bank.c delete mode 100644 lib/main/pico-sdk/rp2_common/pico_btstack/btstack_run_loop_async_context.c delete mode 100644 lib/main/pico-sdk/rp2_common/pico_btstack/btstack_stdin_pico.c delete mode 100644 lib/main/pico-sdk/rp2_common/pico_btstack/doc.h delete mode 100644 lib/main/pico-sdk/rp2_common/pico_btstack/include/pico/btstack_flash_bank.h delete mode 100644 lib/main/pico-sdk/rp2_common/pico_btstack/include/pico/btstack_run_loop_async_context.h delete mode 100644 lib/main/pico-sdk/rp2_common/pico_clib_interface/doc.h delete mode 100644 lib/main/pico-sdk/rp2_common/pico_clib_interface/include/llvm_libc/sys/cdefs.h delete mode 100644 lib/main/pico-sdk/rp2_common/pico_clib_interface/include/llvm_libc/sys/stat.h delete mode 100644 lib/main/pico-sdk/rp2_common/pico_clib_interface/include/llvm_libc/sys/time.h delete mode 100644 lib/main/pico-sdk/rp2_common/pico_clib_interface/include/llvm_libc/sys/times.h delete mode 100644 lib/main/pico-sdk/rp2_common/pico_clib_interface/include/llvm_libc/sys/types.h delete mode 100644 lib/main/pico-sdk/rp2_common/pico_clib_interface/include/llvm_libc/time.h delete mode 100644 lib/main/pico-sdk/rp2_common/pico_clib_interface/include/llvm_libc/unistd.h delete mode 100644 lib/main/pico-sdk/rp2_common/pico_clib_interface/llvm_libc_interface.c delete mode 100644 lib/main/pico-sdk/rp2_common/pico_clib_interface/newlib_interface.c delete mode 100644 lib/main/pico-sdk/rp2_common/pico_clib_interface/picolibc_interface.c delete mode 100644 lib/main/pico-sdk/rp2_common/pico_crt0/crt0.S delete mode 100644 lib/main/pico-sdk/rp2_common/pico_crt0/crt0_riscv.S delete mode 100644 lib/main/pico-sdk/rp2_common/pico_crt0/doc.h delete mode 100644 lib/main/pico-sdk/rp2_common/pico_crt0/embedded_end_block.inc.S delete mode 100644 lib/main/pico-sdk/rp2_common/pico_crt0/embedded_start_block.inc.S delete mode 100644 lib/main/pico-sdk/rp2_common/pico_crt0/rp2040/memmap_blocked_ram.ld delete mode 100644 lib/main/pico-sdk/rp2_common/pico_crt0/rp2040/memmap_copy_to_ram.ld delete mode 100644 lib/main/pico-sdk/rp2_common/pico_crt0/rp2040/memmap_default.ld delete mode 100644 lib/main/pico-sdk/rp2_common/pico_crt0/rp2040/memmap_no_flash.ld delete mode 100644 lib/main/pico-sdk/rp2_common/pico_crt0/rp2350/memmap_copy_to_ram.ld delete mode 100644 lib/main/pico-sdk/rp2_common/pico_crt0/rp2350/memmap_default.ld delete mode 100644 lib/main/pico-sdk/rp2_common/pico_crt0/rp2350/memmap_no_flash.ld delete mode 100644 lib/main/pico-sdk/rp2_common/pico_cxx_options/doc.h delete mode 100644 lib/main/pico-sdk/rp2_common/pico_cxx_options/new_delete.cpp delete mode 100644 lib/main/pico-sdk/rp2_common/pico_cyw43_arch/cyw43_arch.c delete mode 100644 lib/main/pico-sdk/rp2_common/pico_cyw43_arch/cyw43_arch_freertos.c delete mode 100644 lib/main/pico-sdk/rp2_common/pico_cyw43_arch/cyw43_arch_poll.c delete mode 100644 lib/main/pico-sdk/rp2_common/pico_cyw43_arch/cyw43_arch_threadsafe_background.c delete mode 100644 lib/main/pico-sdk/rp2_common/pico_cyw43_arch/include/pico/cyw43_arch.h delete mode 100644 lib/main/pico-sdk/rp2_common/pico_cyw43_arch/include/pico/cyw43_arch/arch_freertos.h delete mode 100644 lib/main/pico-sdk/rp2_common/pico_cyw43_arch/include/pico/cyw43_arch/arch_poll.h delete mode 100644 lib/main/pico-sdk/rp2_common/pico_cyw43_arch/include/pico/cyw43_arch/arch_threadsafe_background.h delete mode 100644 lib/main/pico-sdk/rp2_common/pico_cyw43_driver/btstack_chipset_cyw43.c delete mode 100644 lib/main/pico-sdk/rp2_common/pico_cyw43_driver/btstack_cyw43.c delete mode 100644 lib/main/pico-sdk/rp2_common/pico_cyw43_driver/btstack_hci_transport_cyw43.c delete mode 100644 lib/main/pico-sdk/rp2_common/pico_cyw43_driver/cybt_shared_bus/cybt_shared_bus.c delete mode 100644 lib/main/pico-sdk/rp2_common/pico_cyw43_driver/cybt_shared_bus/cybt_shared_bus_driver.c delete mode 100644 lib/main/pico-sdk/rp2_common/pico_cyw43_driver/cybt_shared_bus/cybt_shared_bus_driver.h delete mode 100644 lib/main/pico-sdk/rp2_common/pico_cyw43_driver/cyw43-driver.BUILD delete mode 100644 lib/main/pico-sdk/rp2_common/pico_cyw43_driver/cyw43_bus_pio_spi.c delete mode 100644 lib/main/pico-sdk/rp2_common/pico_cyw43_driver/cyw43_bus_pio_spi.pio delete mode 100644 lib/main/pico-sdk/rp2_common/pico_cyw43_driver/cyw43_driver.c delete mode 100644 lib/main/pico-sdk/rp2_common/pico_cyw43_driver/include/cyw43_configport.h delete mode 100644 lib/main/pico-sdk/rp2_common/pico_cyw43_driver/include/pico/btstack_chipset_cyw43.h delete mode 100644 lib/main/pico-sdk/rp2_common/pico_cyw43_driver/include/pico/btstack_cyw43.h delete mode 100644 lib/main/pico-sdk/rp2_common/pico_cyw43_driver/include/pico/btstack_hci_transport_cyw43.h delete mode 100644 lib/main/pico-sdk/rp2_common/pico_cyw43_driver/include/pico/cyw43_driver.h delete mode 100644 lib/main/pico-sdk/rp2_common/pico_divider/divider_compiler.c delete mode 100644 lib/main/pico-sdk/rp2_common/pico_divider/divider_hardware.S delete mode 100644 lib/main/pico-sdk/rp2_common/pico_double/double_aeabi_dcp.S delete mode 100644 lib/main/pico-sdk/rp2_common/pico_double/double_aeabi_rp2040.S delete mode 100644 lib/main/pico-sdk/rp2_common/pico_double/double_conv_m33.S delete mode 100644 lib/main/pico-sdk/rp2_common/pico_double/double_fma_dcp.S delete mode 100644 lib/main/pico-sdk/rp2_common/pico_double/double_init_rom_rp2040.c delete mode 100644 lib/main/pico-sdk/rp2_common/pico_double/double_math.c delete mode 100644 lib/main/pico-sdk/rp2_common/pico_double/double_none.S delete mode 100644 lib/main/pico-sdk/rp2_common/pico_double/double_sci_m33.S delete mode 100644 lib/main/pico-sdk/rp2_common/pico_double/double_v1_rom_shim_rp2040.S delete mode 100644 lib/main/pico-sdk/rp2_common/pico_double/include/pico/double.h delete mode 100644 lib/main/pico-sdk/rp2_common/pico_fix/rp2040_usb_device_enumeration/include/pico/fix/rp2040_usb_device_enumeration.h delete mode 100644 lib/main/pico-sdk/rp2_common/pico_fix/rp2040_usb_device_enumeration/rp2040_usb_device_enumeration.c delete mode 100644 lib/main/pico-sdk/rp2_common/pico_flash/flash.c delete mode 100644 lib/main/pico-sdk/rp2_common/pico_flash/include/pico/flash.h delete mode 100644 lib/main/pico-sdk/rp2_common/pico_float/float_aeabi_dcp.S delete mode 100644 lib/main/pico-sdk/rp2_common/pico_float/float_aeabi_rp2040.S delete mode 100644 lib/main/pico-sdk/rp2_common/pico_float/float_conv_m33.S delete mode 100644 lib/main/pico-sdk/rp2_common/pico_float/float_init_rom_rp2040.c delete mode 100644 lib/main/pico-sdk/rp2_common/pico_float/float_math.c delete mode 100644 lib/main/pico-sdk/rp2_common/pico_float/float_none.S delete mode 100644 lib/main/pico-sdk/rp2_common/pico_float/float_sci_m33.S delete mode 100644 lib/main/pico-sdk/rp2_common/pico_float/float_sci_m33_vfp.S delete mode 100644 lib/main/pico-sdk/rp2_common/pico_float/float_single_hazard3.S delete mode 100644 lib/main/pico-sdk/rp2_common/pico_float/float_v1_rom_shim_rp2040.S delete mode 100644 lib/main/pico-sdk/rp2_common/pico_float/include/pico/float.h delete mode 100644 lib/main/pico-sdk/rp2_common/pico_i2c_slave/i2c_slave.c delete mode 100644 lib/main/pico-sdk/rp2_common/pico_i2c_slave/include/pico/i2c_slave.h delete mode 100644 lib/main/pico-sdk/rp2_common/pico_int64_ops/include/pico/int64_ops.h delete mode 100644 lib/main/pico-sdk/rp2_common/pico_int64_ops/pico_int64_ops_aeabi.S delete mode 100644 lib/main/pico-sdk/rp2_common/pico_lwip/doc.h delete mode 100644 lib/main/pico-sdk/rp2_common/pico_lwip/include/arch/cc.h delete mode 100644 lib/main/pico-sdk/rp2_common/pico_lwip/include/pico/lwip_freertos.h delete mode 100644 lib/main/pico-sdk/rp2_common/pico_lwip/include/pico/lwip_nosys.h delete mode 100644 lib/main/pico-sdk/rp2_common/pico_lwip/lwip.BUILD delete mode 100644 lib/main/pico-sdk/rp2_common/pico_lwip/lwip_freertos.c delete mode 100644 lib/main/pico-sdk/rp2_common/pico_lwip/lwip_nosys.c delete mode 100644 lib/main/pico-sdk/rp2_common/pico_lwip/tools/makefsdata.py delete mode 100644 lib/main/pico-sdk/rp2_common/pico_malloc/include/pico/malloc.h delete mode 100644 lib/main/pico-sdk/rp2_common/pico_malloc/malloc.c delete mode 100644 lib/main/pico-sdk/rp2_common/pico_mbedtls/include/sha256_alt.h delete mode 100644 lib/main/pico-sdk/rp2_common/pico_mbedtls/pico_mbedtls.c delete mode 100644 lib/main/pico-sdk/rp2_common/pico_mem_ops/include/pico/mem_ops.h delete mode 100644 lib/main/pico-sdk/rp2_common/pico_mem_ops/mem_ops.c delete mode 100644 lib/main/pico-sdk/rp2_common/pico_mem_ops/mem_ops_aeabi.S delete mode 100644 lib/main/pico-sdk/rp2_common/pico_multicore/include/pico/multicore.h delete mode 100644 lib/main/pico-sdk/rp2_common/pico_multicore/multicore.c delete mode 100644 lib/main/pico-sdk/rp2_common/pico_platform_compiler/include/pico/platform/compiler.h delete mode 100644 lib/main/pico-sdk/rp2_common/pico_platform_panic/include/pico/platform/panic.h delete mode 100644 lib/main/pico-sdk/rp2_common/pico_platform_panic/panic.c delete mode 100644 lib/main/pico-sdk/rp2_common/pico_platform_sections/include/pico/platform/sections.h delete mode 100644 lib/main/pico-sdk/rp2_common/pico_printf/LICENSE delete mode 100644 lib/main/pico-sdk/rp2_common/pico_printf/include/pico/printf.h delete mode 100644 lib/main/pico-sdk/rp2_common/pico_printf/printf.c delete mode 100644 lib/main/pico-sdk/rp2_common/pico_printf/printf_none.S delete mode 100644 lib/main/pico-sdk/rp2_common/pico_rand/include/pico/rand.h delete mode 100644 lib/main/pico-sdk/rp2_common/pico_rand/rand.c delete mode 100644 lib/main/pico-sdk/rp2_common/pico_runtime/include/pico/runtime.h delete mode 100644 lib/main/pico-sdk/rp2_common/pico_runtime/runtime.c delete mode 100644 lib/main/pico-sdk/rp2_common/pico_runtime_init/include/pico/runtime_init.h delete mode 100644 lib/main/pico-sdk/rp2_common/pico_runtime_init/runtime_init.c delete mode 100644 lib/main/pico-sdk/rp2_common/pico_runtime_init/runtime_init_clocks.c delete mode 100644 lib/main/pico-sdk/rp2_common/pico_runtime_init/runtime_init_stack_guard.c delete mode 100644 lib/main/pico-sdk/rp2_common/pico_sha256/include/pico/sha256.h delete mode 100644 lib/main/pico-sdk/rp2_common/pico_sha256/sha256.c delete mode 100644 lib/main/pico-sdk/rp2_common/pico_standard_binary_info/doc.h delete mode 100644 lib/main/pico-sdk/rp2_common/pico_standard_binary_info/standard_binary_info.c delete mode 100644 lib/main/pico-sdk/rp2_common/pico_standard_link/doc.h delete mode 100644 lib/main/pico-sdk/rp2_common/pico_standard_link/pico_flash_region.template.ld delete mode 100644 lib/main/pico-sdk/rp2_common/pico_stdio/include/pico/stdio.h delete mode 100644 lib/main/pico-sdk/rp2_common/pico_stdio/include/pico/stdio/driver.h delete mode 100644 lib/main/pico-sdk/rp2_common/pico_stdio/stdio.c delete mode 100644 lib/main/pico-sdk/rp2_common/pico_stdio_rtt/SEGGER/Config/SEGGER_RTT_Conf.h delete mode 100644 lib/main/pico-sdk/rp2_common/pico_stdio_rtt/SEGGER/RTT/SEGGER_RTT.c delete mode 100644 lib/main/pico-sdk/rp2_common/pico_stdio_rtt/SEGGER/RTT/SEGGER_RTT.h delete mode 100644 lib/main/pico-sdk/rp2_common/pico_stdio_rtt/include/pico/stdio_rtt.h delete mode 100644 lib/main/pico-sdk/rp2_common/pico_stdio_rtt/stdio_rtt.c delete mode 100644 lib/main/pico-sdk/rp2_common/pico_stdio_semihosting/include/pico/stdio_semihosting.h delete mode 100644 lib/main/pico-sdk/rp2_common/pico_stdio_semihosting/stdio_semihosting.c delete mode 100644 lib/main/pico-sdk/rp2_common/pico_stdio_uart/include/pico/stdio_uart.h delete mode 100644 lib/main/pico-sdk/rp2_common/pico_stdio_uart/stdio_uart.c delete mode 100644 lib/main/pico-sdk/rp2_common/pico_stdio_usb/include/pico/stdio_usb.h delete mode 100644 lib/main/pico-sdk/rp2_common/pico_stdio_usb/include/pico/stdio_usb/reset_interface.h delete mode 100644 lib/main/pico-sdk/rp2_common/pico_stdio_usb/include/tusb_config.h delete mode 100644 lib/main/pico-sdk/rp2_common/pico_stdio_usb/reset_interface.c delete mode 100644 lib/main/pico-sdk/rp2_common/pico_stdio_usb/stdio_usb.c delete mode 100644 lib/main/pico-sdk/rp2_common/pico_stdio_usb/stdio_usb_descriptors.c delete mode 100644 lib/main/pico-sdk/rp2_common/pico_stdlib/stdlib.c delete mode 100644 lib/main/pico-sdk/rp2_common/pico_time_adapter/include/pico/time_adapter.h delete mode 100644 lib/main/pico-sdk/rp2_common/pico_unique_id/include/pico/unique_id.h delete mode 100644 lib/main/pico-sdk/rp2_common/pico_unique_id/unique_id.c delete mode 100644 lib/main/pico-sdk/rp2_common/tinyusb/doc.h delete mode 100644 lib/main/pico-sdk/rp2_common/tinyusb/include/bsp/board.h delete mode 100644 lib/main/pico-sdk/rp2_common/tinyusb/tinyusb.BUILD diff --git a/.gitmodules b/.gitmodules index 70c3f1c3ee..cd7739f398 100644 --- a/.gitmodules +++ b/.gitmodules @@ -3,3 +3,8 @@ url = https://github.com/betaflight/config.git branch = master ignore = dirty +[submodule "lib/main/pico-sdk"] + path = lib/main/pico-sdk + url = https://github.com/raspberrypi/pico-sdk.git + branch = master + ignore = dirty diff --git a/lib/main/pico-sdk b/lib/main/pico-sdk new file mode 160000 index 0000000000..ee68c78d0a --- /dev/null +++ b/lib/main/pico-sdk @@ -0,0 +1 @@ +Subproject commit ee68c78d0afae2b69c03ae1a72bf5cc267a2d94c diff --git a/lib/main/pico-sdk/common/README.md b/lib/main/pico-sdk/common/README.md deleted file mode 100644 index 0f30a4211e..0000000000 --- a/lib/main/pico-sdk/common/README.md +++ /dev/null @@ -1,3 +0,0 @@ -This directory code that is common to all builds regardless of `PICO_PLATFORM`. It is a mix -of common header files, or high level functionality built entirely using `hardware_` or `pico_` libraries provided -by the actual target `PICO_PLATFORM`` \ No newline at end of file diff --git a/lib/main/pico-sdk/common/boot_picobin_headers/include/boot/picobin.h b/lib/main/pico-sdk/common/boot_picobin_headers/include/boot/picobin.h deleted file mode 100644 index 40a0580075..0000000000 --- a/lib/main/pico-sdk/common/boot_picobin_headers/include/boot/picobin.h +++ /dev/null @@ -1,171 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _BOOT_PICOBIN_H -#define _BOOT_PICOBIN_H - -#ifndef NO_PICO_PLATFORM -#include "pico/platform.h" -#else -#ifndef _u -#ifdef __ASSEMBLER__ -#define _u(x) x -#else -#define _u(x) x ## u -#endif -#endif -#endif - -/** \file picobin.h -* \defgroup boot_picobin_headers boot_picobin_headers -* -* \brief Constants for PICOBIN format -*/ - -// these are designed to not look like (likely) 16/32-bit ARM or RISC-V instructions or look like valid pointers -#define PICOBIN_BLOCK_MARKER_START _u(0xffffded3) -#define PICOBIN_BLOCK_MARKER_END _u(0xab123579) - -#define PICOBIN_MAX_BLOCK_SIZE _u(0x280) -#define PICOBIN_MAX_IMAGE_DEF_BLOCK_SIZE _u(0x180) -#define PICOBIN_MAX_PARTITION_TABLE_BLOCK_SIZE _u(0x280) - -// note bit 6 is used to make parity even -#define PICOBIN_BLOCK_ITEM_1BS_NEXT_BLOCK_OFFSET _u(0x41) -#define PICOBIN_BLOCK_ITEM_1BS_IMAGE_TYPE _u(0x42) -#define PICOBIN_BLOCK_ITEM_1BS_VECTOR_TABLE _u(0x03) -#define PICOBIN_BLOCK_ITEM_1BS_ENTRY_POINT _u(0x44) -#define PICOBIN_BLOCK_ITEM_1BS_ROLLING_WINDOW_DELTA _u(0x05) -#define PICOBIN_BLOCK_ITEM_LOAD_MAP _u(0x06) -#define PICOBIN_BLOCK_ITEM_1BS_HASH_DEF _u(0x47) -#define PICOBIN_BLOCK_ITEM_1BS_VERSION _u(0x48) -#define PICOBIN_BLOCK_ITEM_SIGNATURE _u(0x09) -#define PICOBIN_BLOCK_ITEM_PARTITION_TABLE _u(0x0a) -#define PICOBIN_BLOCK_ITEM_HASH_VALUE _u(0x4b) -#define PICOBIN_BLOCK_ITEM_SALT _u(0x0c) - -#define PICOBIN_BLOCK_ITEM_2BS_IGNORED (_u(0x80) | _u(0x7e)) -#define PICOBIN_BLOCK_ITEM_2BS_LAST (_u(0x80) | _u(0x7f)) - -// ---- - -#define PICOBIN_INDEX_TO_BITS(y, x) (y ## _ ## x << y ## _LSB) - -#define PICOBIN_IMAGE_TYPE_IMAGE_TYPE_LSB _u(0) -#define PICOBIN_IMAGE_TYPE_IMAGE_TYPE_BITS _u(0x000f) -#define PICOBIN_IMAGE_TYPE_IMAGE_TYPE_INVALID _u(0x0) -#define PICOBIN_IMAGE_TYPE_IMAGE_TYPE_EXE _u(0x1) -#define PICOBIN_IMAGE_TYPE_IMAGE_TYPE_DATA _u(0x2) -#define PICOBIN_IMAGE_TYPE_IMAGE_TYPE_AS_BITS(x) PICOBIN_INDEX_TO_BITS(PICOBIN_IMAGE_TYPE_IMAGE_TYPE, x) - -#define PICOBIN_IMAGE_TYPE_EXE_SECURITY_LSB _u(4) -#define PICOBIN_IMAGE_TYPE_EXE_SECURITY_BITS _u(0x0030) -#define PICOBIN_IMAGE_TYPE_EXE_SECURITY_UNSPECIFIED _u(0x0) -#define PICOBIN_IMAGE_TYPE_EXE_SECURITY_NS _u(0x1) -#define PICOBIN_IMAGE_TYPE_EXE_SECURITY_S _u(0x2) -#define PICOBIN_IMAGE_TYPE_EXE_SECURITY_AS_BITS(x) PICOBIN_INDEX_TO_BITS(PICOBIN_IMAGE_TYPE_EXE_SECURITY, x) - -#define PICOBIN_IMAGE_TYPE_EXE_CPU_LSB _u(8) -#define PICOBIN_IMAGE_TYPE_EXE_CPU_BITS _u(0x0700) -#define PICOBIN_IMAGE_TYPE_EXE_CPU_ARM _u(0) -#define PICOBIN_IMAGE_TYPE_EXE_CPU_RISCV _u(1) -#define PICOBIN_IMAGE_TYPE_EXE_CPU_VARMULET _u(2) -#define PICOBIN_IMAGE_TYPE_EXE_CPU_AS_BITS(x) PICOBIN_INDEX_TO_BITS(PICOBIN_IMAGE_TYPE_EXE_CPU, x) - -#define PICOBIN_IMAGE_TYPE_EXE_CHIP_LSB _u(12) -#define PICOBIN_IMAGE_TYPE_EXE_CHIP_BITS _u(0x7000) -#define PICOBIN_IMAGE_TYPE_EXE_CHIP_RP2040 _u(0) -#define PICOBIN_IMAGE_TYPE_EXE_CHIP_RP2350 _u(1) -#define PICOBIN_IMAGE_TYPE_EXE_CHIP_AS_BITS(x) PICOBIN_INDEX_TO_BITS(PICOBIN_IMAGE_TYPE_EXE_CHIP, x) - -#define PICOBIN_IMAGE_TYPE_EXE_TBYB_BITS _u(0x8000) - -// todo assert no overlap ^ - -#define PICOBIN_PARTITION_PERMISSIONS_LSB _u(26) -#define PICOBIN_PARTITION_PERMISSIONS_BITS _u(0xfc000000) - -#define PICOBIN_PARTITION_PERMISSION_S_R_BITS _u(0x04000000) -#define PICOBIN_PARTITION_PERMISSION_S_W_BITS _u(0x08000000) -#define PICOBIN_PARTITION_PERMISSION_NS_R_BITS _u(0x10000000) -#define PICOBIN_PARTITION_PERMISSION_NS_W_BITS _u(0x20000000) -#define PICOBIN_PARTITION_PERMISSION_NSBOOT_R_BITS _u(0x40000000) -#define PICOBIN_PARTITION_PERMISSION_NSBOOT_W_BITS _u(0x80000000) - -#define PICOBIN_PARTITION_LOCATION_FIRST_SECTOR_LSB _u(0) -#define PICOBIN_PARTITION_LOCATION_FIRST_SECTOR_BITS _u(0x00001fff) -#define PICOBIN_PARTITION_LOCATION_LAST_SECTOR_LSB _u(13) -#define PICOBIN_PARTITION_LOCATION_LAST_SECTOR_BITS _u(0x03ffe000) - -#define PICOBIN_PARTITION_FLAGS_HAS_ID_BITS _u(0x00000001) -#define PICOBIN_PARTITION_FLAGS_LINK_TYPE_LSB _u(1) -#define PICOBIN_PARTITION_FLAGS_LINK_TYPE_BITS _u(0x00000006) -#define PICOBIN_PARTITION_FLAGS_LINK_VALUE_LSB _u(3) -#define PICOBIN_PARTITION_FLAGS_LINK_VALUE_BITS _u(0x00000078) - -#define PICOBIN_PARTITION_MAX_EXTRA_FAMILIES _u(3) -#define PICOBIN_PARTITION_FLAGS_ACCEPTS_NUM_EXTRA_FAMILIES_LSB _u(7) -#define PICOBIN_PARTITION_FLAGS_ACCEPTS_NUM_EXTRA_FAMILIES_BITS _u(0x00000180) -// these are an optimization when booting in either ARM or RISC-V, to avoid looking at partitions -// which are known not to contain the right sort of binary, OR as a way to prevent -// auto-architecture-switch. NOTE: the first partition that can be booted, will be, -// so if you have a RISC-V binary in the first partition, and auto-arhcitecture-switch enabled, then -// even if booting under ARM, with an ARM binary in a later partition, the RISC-V binary -// will be booted by default; setting PICOBIN_PARTITION_FLAGS_IGNORED_DURING_ARM_BOOT_BITS -// on the partition, will have the RISC-V binary containing partition ignored under ARM -// boot -#define PICOBIN_PARTITION_FLAGS_IGNORED_DURING_ARM_BOOT_BITS _u(0x00000200) -#define PICOBIN_PARTITION_FLAGS_IGNORED_DURING_RISCV_BOOT_BITS _u(0x00000400) -#define PICOBIN_PARTITION_FLAGS_UF2_DOWNLOAD_AB_NON_BOOTABLE_OWNER_AFFINITY _u(0x00000800) -#define PICOBIN_PARTITION_FLAGS_HAS_NAME_BITS _u(0x00001000) -#define PICOBIN_PARTITION_FLAGS_UF2_DOWNLOAD_NO_REBOOT_BITS _u(0x00002000) -// we have a bit for each well known family-id .. note we expect there to be more in the future with new chips, -// but we have plenty of space for now. -#define PICOBIN_PARTITION_FLAGS_ACCEPTS_DEFAULT_FAMILIES_LSB _u(14) -#define PICOBIN_PARTITION_FLAGS_ACCEPTS_DEFAULT_FAMILY_RP2040_BITS _u(0x00004000) -#define PICOBIN_PARTITION_FLAGS_ACCEPTS_DEFAULT_FAMILY_ABSOLUTE_BITS _u(0x00008000) -#define PICOBIN_PARTITION_FLAGS_ACCEPTS_DEFAULT_FAMILY_DATA_BITS _u(0x00010000) -#define PICOBIN_PARTITION_FLAGS_ACCEPTS_DEFAULT_FAMILY_RP2350_ARM_S_BITS _u(0x00020000) -#define PICOBIN_PARTITION_FLAGS_ACCEPTS_DEFAULT_FAMILY_RP2350_RISCV_BITS _u(0x00040000) -#define PICOBIN_PARTITION_FLAGS_ACCEPTS_DEFAULT_FAMILY_RP2350_ARM_NS_BITS _u(0x00080000) - -#define PICOBIN_PARTITION_FLAGS_LINK_TYPE_NONE _u(0) -#define PICOBIN_PARTITION_FLAGS_LINK_TYPE_A_PARTITION _u(1) -#define PICOBIN_PARTITION_FLAGS_LINK_TYPE_OWNER_PARTITION _u(2) -#define PICOBIN_PARTITION_FLAGS_LINK_TYPE_AS_BITS(x) PICOBIN_INDEX_TO_BITS(PICOBIN_PARTITION_FLAGS_LINK_TYPE, x) - - -#define PICOBIN_HASH_SHA256 _u(0x01) - -#define PICOBIN_SIGNATURE_SECP256K1 _u(0x01) - -#ifndef __ASSEMBLER__ - -#include - -typedef struct { - // these must all be word aligned - uint32_t storage_address_rel; - uint32_t runtime_address; - uint32_t size; -} picobin_load_map_entry; - -typedef struct { - uint32_t header; - picobin_load_map_entry entries[]; -} picobin_load_map; - -static inline unsigned int picobin_load_map_entry_count(const picobin_load_map *lm) { - return (lm->header << 1) >> 25; -} - -static inline bool picobin_load_map_is_relative(const picobin_load_map *lm) { - return (int32_t)lm->header >= 0; -} - -#endif - -#endif diff --git a/lib/main/pico-sdk/common/boot_picoboot_headers/include/boot/picoboot.h b/lib/main/pico-sdk/common/boot_picoboot_headers/include/boot/picoboot.h deleted file mode 100644 index 8645d52d73..0000000000 --- a/lib/main/pico-sdk/common/boot_picoboot_headers/include/boot/picoboot.h +++ /dev/null @@ -1,175 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _BOOT_PICOBOOT_H -#define _BOOT_PICOBOOT_H - -#include -#include -#include - -#ifndef NO_PICO_PLATFORM -#include "pico/platform.h" -#endif - -/** \file picoboot.h -* \defgroup boot_picoboot_headers boot_picoboot_headers -* -* \brief Header file for the PICOBOOT USB interface exposed by an RP2xxx chip in BOOTSEL mode -*/ - -#include "picoboot_constants.h" - -#define PICOBOOT_MAGIC 0x431fd10bu - -// -------------------------------------------- -// CONTROL REQUESTS FOR THE PICOBOOT INTERFACE -// -------------------------------------------- - -// size 0 OUT - un-stall EPs and reset -#define PICOBOOT_IF_RESET 0x41 - -// size 16 IN - return the status of the last command -#define PICOBOOT_IF_CMD_STATUS 0x42 - -// -------------------------------------------------- -// COMMAND REQUESTS SENT TO THE PICOBOOT OUT ENDPOINT -// -------------------------------------------------- -// -// picoboot_cmd structure of size 32 is sent to OUT endpoint -// transfer_length bytes are transferred via IN/OUT -// device responds on success with 0 length ACK packet set via OUT/IN -// device may stall the transferring endpoint in case of error - -enum picoboot_cmd_id { - PC_EXCLUSIVE_ACCESS = 0x1, - PC_REBOOT = 0x2, - PC_FLASH_ERASE = 0x3, - PC_READ = 0x84, // either RAM or FLASH - PC_WRITE = 0x5, // either RAM or FLASH (does no erase) - PC_EXIT_XIP = 0x6, - PC_ENTER_CMD_XIP = 0x7, - PC_EXEC = 0x8, - PC_VECTORIZE_FLASH = 0x9, - // RP2350 only below here - PC_REBOOT2 = 0xa, - PC_GET_INFO = 0x8b, - PC_OTP_READ = 0x8c, - PC_OTP_WRITE = 0xd, - //PC_EXEC2 = 0xe, // currently unused -}; - -enum picoboot_status { - PICOBOOT_OK = 0, - PICOBOOT_UNKNOWN_CMD = 1, - PICOBOOT_INVALID_CMD_LENGTH = 2, - PICOBOOT_INVALID_TRANSFER_LENGTH = 3, - PICOBOOT_INVALID_ADDRESS = 4, - PICOBOOT_BAD_ALIGNMENT = 5, - PICOBOOT_INTERLEAVED_WRITE = 6, - PICOBOOT_REBOOTING = 7, - PICOBOOT_UNKNOWN_ERROR = 8, - PICOBOOT_INVALID_STATE = 9, - PICOBOOT_NOT_PERMITTED = 10, - PICOBOOT_INVALID_ARG = 11, - PICOBOOT_BUFFER_TOO_SMALL = 12, - PICOBOOT_PRECONDITION_NOT_MET = 13, - PICOBOOT_MODIFIED_DATA = 14, - PICOBOOT_INVALID_DATA = 15, - PICOBOOT_NOT_FOUND = 16, - PICOBOOT_UNSUPPORTED_MODIFICATION = 17, -}; - -struct __packed picoboot_reboot_cmd { - uint32_t dPC; // 0 means reset into regular boot path - uint32_t dSP; - uint32_t dDelayMS; -}; - - -// note this (with pc_sp) union member has the same layout as picoboot_reboot_cmd except with extra dFlags -struct __packed picoboot_reboot2_cmd { - uint32_t dFlags; - uint32_t dDelayMS; - uint32_t dParam0; - uint32_t dParam1; -}; - -// used for EXEC, VECTORIZE_FLASH -struct __packed picoboot_address_only_cmd { - uint32_t dAddr; -}; - -// used for READ, WRITE, FLASH_ERASE -struct __packed picoboot_range_cmd { - uint32_t dAddr; - uint32_t dSize; -}; - -struct __packed picoboot_exec2_cmd { - uint32_t image_base; - uint32_t image_size; - uint32_t workarea_base; - uint32_t workarea_size; -}; - -enum picoboot_exclusive_type { - NOT_EXCLUSIVE = 0, - EXCLUSIVE, - EXCLUSIVE_AND_EJECT -}; - -struct __packed picoboot_exclusive_cmd { - uint8_t bExclusive; -}; - -struct __packed picoboot_otp_cmd { - uint16_t wRow; // OTP row - uint16_t wRowCount; // number of rows to transfer - uint8_t bEcc; // use error correction (16 bit per register vs 24 (stored as 32) bit raw) -}; - - -struct __packed picoboot_get_info_cmd { - uint8_t bType; - uint8_t bParam; - uint16_t wParam; - uint32_t dParams[3]; -}; - -// little endian -struct __packed __aligned(4) picoboot_cmd { - uint32_t dMagic; - uint32_t dToken; // an identifier for this token to correlate with a status response - uint8_t bCmdId; // top bit set for IN - uint8_t bCmdSize; // bytes of actual data in the arg part of this structure - uint16_t _unused; - uint32_t dTransferLength; // length of IN/OUT transfer (or 0) if none - union { - uint8_t args[16]; - struct picoboot_reboot_cmd reboot_cmd; - struct picoboot_range_cmd range_cmd; - struct picoboot_address_only_cmd address_only_cmd; - struct picoboot_exclusive_cmd exclusive_cmd; - struct picoboot_reboot2_cmd reboot2_cmd; - struct picoboot_otp_cmd otp_cmd; - struct picoboot_get_info_cmd get_info_cmd; - struct picoboot_exec2_cmd exec2_cmd; - }; -}; -static_assert(32 == sizeof(struct picoboot_cmd), "picoboot_cmd must be 32 bytes big"); - -struct __packed __aligned(4) picoboot_cmd_status { - uint32_t dToken; - uint32_t dStatusCode; - uint8_t bCmdId; - uint8_t bInProgress; - uint8_t _pad[6]; -}; - -static_assert(16 == sizeof(struct picoboot_cmd_status), "picoboot_cmd_status must be 16 bytes big"); - -#endif diff --git a/lib/main/pico-sdk/common/boot_picoboot_headers/include/boot/picoboot_constants.h b/lib/main/pico-sdk/common/boot_picoboot_headers/include/boot/picoboot_constants.h deleted file mode 100644 index ac78ea2135..0000000000 --- a/lib/main/pico-sdk/common/boot_picoboot_headers/include/boot/picoboot_constants.h +++ /dev/null @@ -1,42 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _BOOT_PICOBOOT_CONSTANTS_H -#define _BOOT_PICOBOOT_CONSTANTS_H - -#define REBOOT2_TYPE_MASK 0x0f - -// note these match REBOOT_TYPE in pico/bootrom_constants.h (also 0 is used for PC_SP for backwards compatibility with RP2040) -// values 0-7 are secure/non-secure -#define REBOOT2_FLAG_REBOOT_TYPE_NORMAL 0x0 // param0 = diagnostic partition -#define REBOOT2_FLAG_REBOOT_TYPE_BOOTSEL 0x2 // param0 = bootsel_flags, param1 = gpio_config -#define REBOOT2_FLAG_REBOOT_TYPE_RAM_IMAGE 0x3 // param0 = image_base, param1 = image_end -#define REBOOT2_FLAG_REBOOT_TYPE_FLASH_UPDATE 0x4 // param0 = update_base - -// values 8-15 are secure only -#define REBOOT2_FLAG_REBOOT_TYPE_PC_SP 0xd - -#define REBOOT2_FLAG_REBOOT_TO_ARM 0x10 -#define REBOOT2_FLAG_REBOOT_TO_RISCV 0x20 - -#define REBOOT2_FLAG_NO_RETURN_ON_SUCCESS 0x100 - -#define BOOTSEL_FLAG_DISABLE_MSD_INTERFACE 0x01 -#define BOOTSEL_FLAG_DISABLE_PICOBOOT_INTERFACE 0x02 -#define BOOTSEL_FLAG_GPIO_PIN_ACTIVE_LOW 0x10 -#define BOOTSEL_FLAG_GPIO_PIN_SPECIFIED 0x20 - -#define PICOBOOT_GET_INFO_SYS 1 -#define PICOBOOT_GET_INFO_PARTTION_TABLE 2 -#define PICOBOOT_GET_INFO_UF2_TARGET_PARTITION 3 -#define PICOBOOT_GET_INFO_UF2_STATUS 4 - -#define UF2_STATUS_IGNORED_FAMILY 0x01 -#define UF2_STATUS_ABORT_EXCLUSIVELY_LOCKED 0x10 -#define UF2_STATUS_ABORT_BAD_ADDRESS 0x20 -#define UF2_STATUS_ABORT_WRITE_ERROR 0x40 -#define UF2_STATUS_ABORT_REBOOT_FAILED 0x80 -#endif \ No newline at end of file diff --git a/lib/main/pico-sdk/common/boot_uf2_headers/include/boot/uf2.h b/lib/main/pico-sdk/common/boot_uf2_headers/include/boot/uf2.h deleted file mode 100644 index 271540a205..0000000000 --- a/lib/main/pico-sdk/common/boot_uf2_headers/include/boot/uf2.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _BOOT_UF2_H -#define _BOOT_UF2_H - -#include -#include - -/** \file uf2.h -* \defgroup boot_uf2_headers boot_uf2_headers -* -* \brief Header file for the UF2 format supported by a RP2xxx chip in BOOTSEL mode -*/ - -#define UF2_MAGIC_START0 0x0A324655u -#define UF2_MAGIC_START1 0x9E5D5157u -#define UF2_MAGIC_END 0x0AB16F30u - -#define UF2_FLAG_NOT_MAIN_FLASH 0x00000001u -#define UF2_FLAG_FILE_CONTAINER 0x00001000u -#define UF2_FLAG_FAMILY_ID_PRESENT 0x00002000u -#define UF2_FLAG_MD5_PRESENT 0x00004000u - -#define RP2040_FAMILY_ID 0xe48bff56u -#define ABSOLUTE_FAMILY_ID 0xe48bff57u -#define DATA_FAMILY_ID 0xe48bff58u -#define RP2350_ARM_S_FAMILY_ID 0xe48bff59u -#define RP2350_RISCV_FAMILY_ID 0xe48bff5au -#define RP2350_ARM_NS_FAMILY_ID 0xe48bff5bu -#define FAMILY_ID_MAX 0xe48bff5bu - - -struct uf2_block { - // 32 byte header - uint32_t magic_start0; - uint32_t magic_start1; - uint32_t flags; - uint32_t target_addr; - uint32_t payload_size; - uint32_t block_no; - uint32_t num_blocks; - uint32_t file_size; // or familyID; - uint8_t data[476]; - uint32_t magic_end; -}; - -static_assert(sizeof(struct uf2_block) == 512, "uf2_block not sector sized"); - -#endif diff --git a/lib/main/pico-sdk/common/hardware_claim/claim.c b/lib/main/pico-sdk/common/hardware_claim/claim.c deleted file mode 100644 index 1636855c17..0000000000 --- a/lib/main/pico-sdk/common/hardware_claim/claim.c +++ /dev/null @@ -1,56 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "hardware/claim.h" - -uint32_t hw_claim_lock(void) { - return spin_lock_blocking(spin_lock_instance(PICO_SPINLOCK_ID_HARDWARE_CLAIM)); -} - -void hw_claim_unlock(uint32_t save) { - spin_unlock(spin_lock_instance(PICO_SPINLOCK_ID_HARDWARE_CLAIM), save); -} - -inline bool hw_is_claimed(const uint8_t *bits, uint bit_index) { - return (bits[bit_index >> 3u] & (1u << (bit_index & 7u))); -} - -void hw_claim_or_assert(uint8_t *bits, uint bit_index, const char *message) { - uint32_t save = hw_claim_lock(); - if (hw_is_claimed(bits, bit_index)) { - panic(message, bit_index); - } else { - bits[bit_index >> 3u] |= (uint8_t)(1u << (bit_index & 7u)); - } - hw_claim_unlock(save); -} - -int hw_claim_unused_from_range(uint8_t *bits, bool required, uint bit_lsb, uint bit_msb, const char *message) { - // don't bother check lsb / msb order as if wrong, then it'll fail anyway - uint32_t save = hw_claim_lock(); - int found_bit = -1; - for(uint bit=bit_lsb; bit <= bit_msb; bit++) { - if (!hw_is_claimed(bits, bit)) { - bits[bit >> 3u] |= (uint8_t)(1u << (bit & 7u)); - found_bit = (int)bit; - break; - } - } - hw_claim_unlock(save); - if (found_bit < 0 && required) { - panic(message); - } - return found_bit; -} - -void hw_claim_clear(uint8_t *bits, uint bit_index) { - uint32_t save = hw_claim_lock(); - assert(hw_is_claimed(bits, bit_index)); - bits[bit_index >> 3u] &= (uint8_t) ~(1u << (bit_index & 7u)); - hw_claim_unlock(save); -} - - diff --git a/lib/main/pico-sdk/common/hardware_claim/include/hardware/claim.h b/lib/main/pico-sdk/common/hardware_claim/include/hardware/claim.h deleted file mode 100644 index f9501440c6..0000000000 --- a/lib/main/pico-sdk/common/hardware_claim/include/hardware/claim.h +++ /dev/null @@ -1,108 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _HARDWARE_CLAIM_H -#define _HARDWARE_CLAIM_H - -#include "pico.h" -#include "hardware/sync.h" - -/** \file claim.h - * \defgroup hardware_claim hardware_claim - * \brief Lightweight hardware resource management API - * - * `hardware_claim` provides a simple API for management of hardware resources at runtime. - * - * This API is usually called by other hardware specific _claiming_ APIs and provides simple - * multi-core safe methods to manipulate compact bit-sets representing hardware resources. - * - * This API allows any other library to cooperatively participate in a scheme by which - * both compile time and runtime allocation of resources can co-exist, and conflicts - * can be avoided or detected (depending on the use case) without the libraries having - * any other knowledge of each other. - * - * Facilities are providing for: - * - * 1. Claiming resources (and asserting if they are already claimed) - * 2. Freeing (unclaiming) resources - * 3. Finding unused resources - */ - -#ifdef __cplusplus -extern "C" { -#endif - -/*! \brief Atomically claim a resource, panicking if it is already in use - * \ingroup hardware_claim - * - * The resource ownership is indicated by the bit_index bit in an array of bits. - * - * \param bits pointer to an array of bits (8 bits per byte) - * \param bit_index resource to claim (bit index into array of bits) - * \param message string to display if the bit cannot be claimed; note this may have a single printf format "%d" for the bit - */ -void hw_claim_or_assert(uint8_t *bits, uint bit_index, const char *message); - -/*! \brief Atomically claim one resource out of a range of resources, optionally asserting if none are free - * \ingroup hardware_claim - * - * \param bits pointer to an array of bits (8 bits per byte) - * \param required true if this method should panic if the resource is not free - * \param bit_lsb the lower bound (inclusive) of the resource range to claim from - * \param bit_msb the upper bound (inclusive) of the resource range to claim from - * \param message string to display if the bit cannot be claimed - * \return the bit index representing the claimed or -1 if none are available in the range, and required = false - */ -int hw_claim_unused_from_range(uint8_t *bits, bool required, uint bit_lsb, uint bit_msb, const char *message); - -/*! \brief Determine if a resource is claimed at the time of the call - * \ingroup hardware_claim - * - * The resource ownership is indicated by the bit_index bit in an array of bits. - * - * \param bits pointer to an array of bits (8 bits per byte) - * \param bit_index resource to check (bit index into array of bits) - * \return true if the resource is claimed - */ -bool hw_is_claimed(const uint8_t *bits, uint bit_index); - -/*! \brief Atomically unclaim a resource - * \ingroup hardware_claim - * - * The resource ownership is indicated by the bit_index bit in an array of bits. - * - * \param bits pointer to an array of bits (8 bits per byte) - * \param bit_index resource to unclaim (bit index into array of bits) - */ -void hw_claim_clear(uint8_t *bits, uint bit_index); - -/*! \brief Acquire the runtime mutual exclusion lock provided by the `hardware_claim` library - * \ingroup hardware_claim - * - * This method is called automatically by the other `hw_claim_` methods, however it is provided as a convenience - * to code that might want to protect other hardware initialization code from concurrent use. - * - * \note hw_claim_lock() uses a spin lock internally, so disables interrupts on the calling core, and will deadlock - * if the calling core already owns the lock. - * - * \return a token to pass to hw_claim_unlock() - */ -uint32_t hw_claim_lock(void); - -/*! \brief Release the runtime mutual exclusion lock provided by the `hardware_claim` library - * \ingroup hardware_claim - * - * \note This method MUST be called from the same core that call hw_claim_lock() - * - * \param token the token returned by the corresponding call to hw_claim_lock() - */ -void hw_claim_unlock(uint32_t token); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/lib/main/pico-sdk/common/pico_base_headers/generate_config_header.cmake b/lib/main/pico-sdk/common/pico_base_headers/generate_config_header.cmake deleted file mode 100644 index 46b4e13ef0..0000000000 --- a/lib/main/pico-sdk/common/pico_base_headers/generate_config_header.cmake +++ /dev/null @@ -1,33 +0,0 @@ -# build the auto gen config headers - -set(header_content "// AUTOGENERATED FROM PICO_CONFIG_HEADER_FILES and then PICO__CONFIG_HEADER_FILES\n// DO NOT EDIT!\n") -string(TOUPPER ${PICO_PLATFORM} PICO_PLATFORM_UPPER) -string(REGEX REPLACE "-" "_" PICO_PLATFORM_UPPER "${PICO_PLATFORM_UPPER}") - -macro(add_header_content_from_var VAR) - set(header_content "${header_content}\n\n// based on ${VAR}:\n") - foreach(var IN LISTS ${VAR}) - set(header_content "${header_content}\n#include \"${var}\"") - endforeach() -endmacro() - -# PICO_CMAKE_CONFIG: PICO_CONFIG_HEADER_FILES, List of extra header files to include from pico/config.h for all platforms, type=list, group=pico_base -add_header_content_from_var(PICO_CONFIG_HEADER_FILES) - -# PICO_CMAKE_CONFIG: PICO_RP2040_CONFIG_HEADER_FILES, List of extra header files to include from pico/config.h for the rp2040 platform only, type=list, group=pico_base -# PICO_CMAKE_CONFIG: PICO_RP2350_ARM_S_CONFIG_HEADER_FILES, List of extra header files to include from pico/config.h for the rp2350-arm-s platform only, type=list, group=pico_base -# PICO_CMAKE_CONFIG: PICO_RP2350_RISCV_CONFIG_HEADER_FILES, List of extra header files to include from pico/config.h for the riscv platform only, type=list, group=pico_base -# PICO_CMAKE_CONFIG: PICO_HOST_CONFIG_HEADER_FILES, List of extra header files to include from pico/config.h for the host platform only, type=list, group=pico_base -add_header_content_from_var(PICO_${PICO_PLATFORM_UPPER}_CONFIG_HEADER_FILES) -pico_register_common_scope_var(PICO_${PICO_PLATFORM_UPPER}_CONFIG_HEADER_FILES) - -file(GENERATE - OUTPUT ${CMAKE_BINARY_DIR}/generated/pico_base/pico/config_autogen.h - CONTENT "${header_content}" - ) - -configure_file( ${CMAKE_CURRENT_LIST_DIR}/include/pico/version.h.in ${CMAKE_BINARY_DIR}/generated/pico_base/pico/version.h) - -foreach(DIR IN LISTS PICO_INCLUDE_DIRS) - target_include_directories(pico_base_headers SYSTEM INTERFACE ${DIR}) -endforeach() diff --git a/lib/main/pico-sdk/common/pico_base_headers/include/pico.h b/lib/main/pico-sdk/common/pico_base_headers/include/pico.h deleted file mode 100644 index 3b0f2f14ad..0000000000 --- a/lib/main/pico-sdk/common/pico_base_headers/include/pico.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _PICO_H -#define _PICO_H - -/** \file pico.h - * \defgroup pico_base pico_base - * - * \brief Core types and macros for the Raspberry Pi Pico SDK. - * - * This header is intended to be included by all source code - * as it includes configuration headers and overrides in the correct order - * - * This header may be included by assembly code -*/ - -// We may be included by assembly which can't include -#define __PICO_STRING(x) #x -#define __PICO_XSTRING(x) __PICO_STRING(x) -#define __PICO_CONCAT1(x, y) x ## y - -#include "pico/types.h" -#include "pico/version.h" - -// PICO_CONFIG: PICO_CONFIG_HEADER, Unquoted path to header include in place of the default pico/config.h which may be desirable for build systems which can't easily generate the config_autogen header, group=pico_base -#ifdef PICO_CONFIG_HEADER -#include __PICO_XSTRING(PICO_CONFIG_HEADER) -#else -#include "pico/config.h" -#endif -#include "pico/platform.h" -#include "pico/error.h" - -#endif diff --git a/lib/main/pico-sdk/common/pico_base_headers/include/pico/assert.h b/lib/main/pico-sdk/common/pico_base_headers/include/pico/assert.h deleted file mode 100644 index 36e25efae3..0000000000 --- a/lib/main/pico-sdk/common/pico_base_headers/include/pico/assert.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _PICO_ASSERT_H -#define _PICO_ASSERT_H - -#include - -#ifdef __cplusplus - -#include - -extern "C" { -#else -#include -#endif - -// PICO_CONFIG: PARAM_ASSERTIONS_ENABLE_ALL, Global assert enable, type=bool, default=0, group=pico_base -// PICO_CONFIG: PARAM_ASSERTIONS_DISABLE_ALL, Global assert disable, type=bool, default=0, group=pico_base - -#ifndef PARAM_ASSERTIONS_ENABLE_ALL -#define PARAM_ASSERTIONS_ENABLE_ALL 0 -#endif - -#ifndef PARAM_ASSERTIONS_DISABLE_ALL -#define PARAM_ASSERTIONS_DISABLE_ALL 0 -#endif - -#define PARAM_ASSERTIONS_ENABLED(x) ((PARAM_ASSERTIONS_ENABLED_ ## x || PARAM_ASSERTIONS_ENABLE_ALL) && !PARAM_ASSERTIONS_DISABLE_ALL) - -#define invalid_params_if(x, test) ({if (PARAM_ASSERTIONS_ENABLED(x)) assert(!(test));}) -#define valid_params_if(x, test) ({if (PARAM_ASSERTIONS_ENABLED(x)) assert(test);}) -#define hard_assert_if(x, test) ({if (PARAM_ASSERTIONS_ENABLED(x)) hard_assert(!(test));}) -#define invalid_params_if_and_return(x, test, rc) ({/*if (PARAM_ASSERTIONS_ENABLED(x)) assert(!(test)); */ if (test) return rc; }) - -#ifdef NDEBUG -extern void hard_assertion_failure(void); -static inline void hard_assert(bool condition, ...) { - if (!condition) - hard_assertion_failure(); -} -#else -#define hard_assert assert -#endif - -#ifdef __cplusplus -} -#endif -#endif diff --git a/lib/main/pico-sdk/common/pico_base_headers/include/pico/config.h b/lib/main/pico-sdk/common/pico_base_headers/include/pico/config.h deleted file mode 100644 index df0a04347b..0000000000 --- a/lib/main/pico-sdk/common/pico_base_headers/include/pico/config.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _PICO_CONFIG_H -#define _PICO_CONFIG_H - -// ----------------------------------------------------- -// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLY CODE SO -// SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES -// OR USE #ifndef __ASSEMBLER__ guards -// ------------- - -// PICO_CONFIG_HEADER_FILES and then PICO_SDK__CONFIG_INCLUDE_FILES -// entries are dumped in order at build time into this generated header - -#include "pico/config_autogen.h" - -// PICO_CONFIG: PICO_CONFIG_RTOS_ADAPTER_HEADER, Unquoted path to header include in the default pico/config.h for RTOS integration defines that must be included in all sources, group=pico_base -#ifdef PICO_CONFIG_RTOS_ADAPTER_HEADER -#include __PICO_XSTRING(PICO_CONFIG_RTOS_ADAPTER_HEADER) -#endif - -#endif diff --git a/lib/main/pico-sdk/common/pico_base_headers/include/pico/error.h b/lib/main/pico-sdk/common/pico_base_headers/include/pico/error.h deleted file mode 100644 index 9212eda81a..0000000000 --- a/lib/main/pico-sdk/common/pico_base_headers/include/pico/error.h +++ /dev/null @@ -1,50 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _PICO_ERROR_H -#define _PICO_ERROR_H - -#ifndef __ASSEMBLER__ - -/*! - * \brief Common return codes from pico_sdk methods that return a status - * - * All `PICO_ERROR_` values are negative so they can be returned from functions that also - * want to return a zero or positive value on success. - * - * Note these error codes may be returned via bootrom functions too. - * - * \ingroup pico_base - */ -enum pico_error_codes { - PICO_OK = 0, ///< No error; the operation succeeded - PICO_ERROR_NONE = 0, ///< No error; the operation succeeded - PICO_ERROR_GENERIC = -1, ///< An unspecified error occurred - PICO_ERROR_TIMEOUT = -2, ///< The function failed due to timeout - PICO_ERROR_NO_DATA = -3, ///< Attempt for example to read from an empty buffer/FIFO - PICO_ERROR_NOT_PERMITTED = -4, ///< Permission violation e.g. write to read-only flash partition, or security violation - PICO_ERROR_INVALID_ARG = -5, ///< Argument is outside of range of supported values` - PICO_ERROR_IO = -6, ///< An I/O error occurred - PICO_ERROR_BADAUTH = -7, ///< The authorization failed due to bad credentials - PICO_ERROR_CONNECT_FAILED = -8, ///< The connection failed - PICO_ERROR_INSUFFICIENT_RESOURCES = -9, ///< Dynamic allocation of resources failed - PICO_ERROR_INVALID_ADDRESS = -10, ///< Address argument was out-of-bounds or was determined to be an address that the caller may not access - PICO_ERROR_BAD_ALIGNMENT = -11, ///< Address was mis-aligned (usually not on word boundary) - PICO_ERROR_INVALID_STATE = -12, ///< Something happened or failed to happen in the past, and consequently we (currently) can't service the request - PICO_ERROR_BUFFER_TOO_SMALL = -13, ///< A user-allocated buffer was too small to hold the result or working state of this function - PICO_ERROR_PRECONDITION_NOT_MET = -14, ///< The call failed because another function must be called first - PICO_ERROR_MODIFIED_DATA = -15, ///< Cached data was determined to be inconsistent with the actual version of the data - PICO_ERROR_INVALID_DATA = -16, ///< A data structure failed to validate - PICO_ERROR_NOT_FOUND = -17, ///< Attempted to access something that does not exist; or, a search failed - PICO_ERROR_UNSUPPORTED_MODIFICATION = -18, ///< Write is impossible based on previous writes; e.g. attempted to clear an OTP bit - PICO_ERROR_LOCK_REQUIRED = -19, ///< A required lock is not owned - PICO_ERROR_VERSION_MISMATCH = -20, ///< A version mismatch occurred (e.g. trying to run PIO version 1 code on RP2040) - PICO_ERROR_RESOURCE_IN_USE = -21 ///< The call could not proceed because requires resourcesw were unavailable -}; - -#endif // !__ASSEMBLER__ - -#endif \ No newline at end of file diff --git a/lib/main/pico-sdk/common/pico_base_headers/include/pico/types.h b/lib/main/pico-sdk/common/pico_base_headers/include/pico/types.h deleted file mode 100644 index 2e9c39642b..0000000000 --- a/lib/main/pico-sdk/common/pico_base_headers/include/pico/types.h +++ /dev/null @@ -1,121 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _PICO_TYPES_H -#define _PICO_TYPES_H - -#ifndef __ASSEMBLER__ - -#include "pico/assert.h" - -#include -#include -#include - -typedef unsigned int uint; - -// PICO_CONFIG: PICO_OPAQUE_ABSOLUTE_TIME_T, Enable opaque type for absolute_time_t to help catch inadvertent confusing uint64_t delays with absolute times, default=0, advanced=true, group=pico_base -#ifndef PICO_OPAQUE_ABSOLUTE_TIME_T -#define PICO_OPAQUE_ABSOLUTE_TIME_T 0 -#endif - -/*! \typedef absolute_time_t - \brief An opaque 64 bit timestamp in microseconds - - The type is used instead of a raw uint64_t to prevent accidentally passing relative times or times in the wrong - time units where an absolute time is required. - - note: As of SDK 2.0.0 this type defaults to being a uin64_t (i.e. no protection); it is enabled - by setting PICO_OPAQUE_ABSOLUTE_TIME_T to 1 - - \see to_us_since_boot() - \see update_us_since_boot() - \ingroup timestamp -*/ -#if PICO_OPAQUE_ABSOLUTE_TIME_T -typedef struct { - uint64_t _private_us_since_boot; -} absolute_time_t; -#else -typedef uint64_t absolute_time_t; -#endif - -/*! fn to_us_since_boot - * \brief convert an absolute_time_t into a number of microseconds since boot. - * \param t the absolute time to convert - * \return a number of microseconds since boot, equivalent to t - * \ingroup timestamp - */ -static inline uint64_t to_us_since_boot(absolute_time_t t) { -#ifdef PICO_DEBUG_ABSOLUTE_TIME_T - return t._private_us_since_boot; -#else - return t; -#endif -} - -/*! fn update_us_since_boot - * \brief update an absolute_time_t value to represent a given number of microseconds since boot - * \param t the absolute time value to update - * \param us_since_boot the number of microseconds since boot to represent. Note this should be representable - * as a signed 64 bit integer - * \ingroup timestamp - */ -static inline void update_us_since_boot(absolute_time_t *t, uint64_t us_since_boot) { -#ifdef PICO_DEBUG_ABSOLUTE_TIME_T - assert(us_since_boot <= INT64_MAX); - t->_private_us_since_boot = us_since_boot; -#else - *t = us_since_boot; -#endif -} - -/*! fn from_us_since_boot - * \brief convert a number of microseconds since boot to an absolute_time_t - * \param us_since_boot number of microseconds since boot - * \return an absolute time equivalent to us_since_boot - * \ingroup timestamp - */ -static inline absolute_time_t from_us_since_boot(uint64_t us_since_boot) { - absolute_time_t t; - update_us_since_boot(&t, us_since_boot); - return t; -} - -#ifdef NDEBUG -#define ABSOLUTE_TIME_INITIALIZED_VAR(name, value) name = value -#else -#define ABSOLUTE_TIME_INITIALIZED_VAR(name, value) name = {value} -#endif - -// PICO_CONFIG: PICO_INCLUDE_RTC_DATETIME, Whether to include the datetime_t type used with the RP2040 RTC hardware, default=1 on RP2040, group=util_datetime -#ifndef PICO_INCLUDE_RTC_DATETIME -#define PICO_INCLUDE_RTC_DATETIME PICO_RP2040 -#endif - -#if PICO_INCLUDE_RTC_DATETIME -/** \struct datetime_t - * \ingroup util_datetime - * \brief Structure containing date and time information - * - * When setting an RTC alarm, set a field to -1 tells - * the RTC to not match on this field - */ -typedef struct { - int16_t year; ///< 0..4095 - int8_t month; ///< 1..12, 1 is January - int8_t day; ///< 1..28,29,30,31 depending on month - int8_t dotw; ///< 0..6, 0 is Sunday - int8_t hour; ///< 0..23 - int8_t min; ///< 0..59 - int8_t sec; ///< 0..59 -} datetime_t; -#endif - -#define bool_to_bit(x) ((uint)!!(x)) - -#endif -#endif diff --git a/lib/main/pico-sdk/common/pico_base_headers/include/pico/version.h.in b/lib/main/pico-sdk/common/pico_base_headers/include/pico/version.h.in deleted file mode 100644 index 08fbfb52e5..0000000000 --- a/lib/main/pico-sdk/common/pico_base_headers/include/pico/version.h.in +++ /dev/null @@ -1,19 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -// --------------------------------------- -// THIS FILE IS AUTOGENERATED; DO NOT EDIT -// --------------------------------------- - -#ifndef _PICO_VERSION_H -#define _PICO_VERSION_H - -#define PICO_SDK_VERSION_MAJOR ${PICO_SDK_VERSION_MAJOR} -#define PICO_SDK_VERSION_MINOR ${PICO_SDK_VERSION_MINOR} -#define PICO_SDK_VERSION_REVISION ${PICO_SDK_VERSION_REVISION} -#define PICO_SDK_VERSION_STRING "${PICO_SDK_VERSION_STRING}" - -#endif diff --git a/lib/main/pico-sdk/common/pico_binary_info/include/pico/binary_info.h b/lib/main/pico-sdk/common/pico_binary_info/include/pico/binary_info.h deleted file mode 100644 index 594e8f7024..0000000000 --- a/lib/main/pico-sdk/common/pico_binary_info/include/pico/binary_info.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _PICO_BINARY_INFO_H -#define _PICO_BINARY_INFO_H - -/** \file binary_info.h - * \defgroup pico_binary_info pico_binary_info - * - * \brief Binary info is intended for embedding machine readable information with the binary in FLASH - * - * Example uses include: - * - * - Program identification / information - * - Pin layouts - * - Included features - * - Identifying flash regions used as block devices/storage - */ - -#include "pico/binary_info/defs.h" -#include "pico/binary_info/structure.h" - -// PICO_CONFIG: PICO_NO_BINARY_INFO, Don't include "binary info" in the output binary, type=bool, default=0 except for `PICO_PLATFORM` `host`, group=pico_runtime_init -#if !PICO_ON_DEVICE && !defined(PICO_NO_BINARY_INFO) -#define PICO_NO_BINARY_INFO 1 -#endif -#include "pico/binary_info/code.h" -#endif diff --git a/lib/main/pico-sdk/common/pico_binary_info/include/pico/binary_info/code.h b/lib/main/pico-sdk/common/pico_binary_info/include/pico/binary_info/code.h deleted file mode 100644 index 63239a9637..0000000000 --- a/lib/main/pico-sdk/common/pico_binary_info/include/pico/binary_info/code.h +++ /dev/null @@ -1,269 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _PICO_BINARY_INFO_CODE_H -#define _PICO_BINARY_INFO_CODE_H - -// pico.h is not available when PICO_NO_BINARY_INFO=1 is used for builds outside of the SDK (e.g. picotool) -// and only needed anyway (because of macro definitions) in PICO_NO_BINARY_INFO=0 builds -#if !PICO_NO_BINARY_INFO -#include "pico.h" -#endif - -#include "pico/binary_info/structure.h" - -#if !PICO_NO_BINARY_INFO -#define __bi_decl(name, bi, section_prefix, attr) static const attr __attribute__((section(section_prefix __STRING(name)))) struct _binary_info_core *const name = bi -#define __bi_lineno_var_name __CONCAT(__bi_, __LINE__) -#define __bi_ptr_lineno_var_name __CONCAT(__bi_ptr, __LINE__) -#define __bi_enclosure_check_lineno_var_name __CONCAT(_error_bi_is_missing_enclosing_decl_,__LINE__) -#define __bi_mark_enclosure static const __unused int __bi_enclosure_check_lineno_var_name=0; -#if __cplusplus || __GNUC__ >= 8 -#define __bi_enclosure_check(x) (x + __bi_enclosure_check_lineno_var_name) -#else -// skip the version check on older GCC non C++, as it doesn't compile.. this is only here to catch the -// user accidentally forgetting to enclose the binary item with bi_decl -#define __bi_enclosure_check(x) (x) -#endif -/** - * \brief Declare some binary information that will be included if the contain source file/line is compiled into the binary - * \ingroup pico_binary_info - */ -#define bi_decl(_decl) __bi_mark_enclosure _decl; __bi_decl(__bi_ptr_lineno_var_name, &__bi_lineno_var_name.core, ".binary_info.keep.", __used); -/** - * \brief Declare some binary information that will be included if the function containing the decl is linked into the binary. - * The SDK uses --gc-sections, so functions that are never called will be removed by the linker, and any associated - * binary information declared this way will also be stripped - * \ingroup pico_binary_info - */ -#define bi_decl_if_func_used(_decl) ({__bi_mark_enclosure _decl; __bi_decl(__bi_ptr_lineno_var_name, &__bi_lineno_var_name.core, ".binary_info.", ); *(const volatile uint8_t *)&__bi_ptr_lineno_var_name;}); - -#define bi_decl_with_attr(_decl, _attr) __bi_mark_enclosure _attr _decl; __bi_decl(__bi_ptr_lineno_var_name, &__bi_lineno_var_name.core, ".binary_info.keep.", __used); -#define bi_decl_if_func_used_with_attr(_decl, _attr) ({__bi_mark_enclosure _attr _decl; __bi_decl(__bi_ptr_lineno_var_name, &__bi_lineno_var_name.core, ".binary_info.", ); *(const volatile uint8_t *)&__bi_ptr_lineno_var_name;}); -#else -#define __bi_decl(bi, name, attr) -#define bi_decl_with_attr(_decl, _attr) -#define bi_decl(_decl) -#define bi_decl_if_func_used_with_attr(_decl, _attr) ((void)0); -#define bi_decl_if_func_used(_decl) ((void)0); -#endif - -#define bi_int(_tag, _id, _value) \ - static const struct _binary_info_id_and_int __bi_lineno_var_name = { \ - .core = { \ - .type = __bi_enclosure_check(BINARY_INFO_TYPE_ID_AND_INT), \ - .tag = _tag, \ - },\ - .id = _id, \ - .value = _value \ - }; - -#define bi_string(_tag, _id, _value) \ - static const struct _binary_info_id_and_string __bi_lineno_var_name = { \ - .core = { \ - .type = __bi_enclosure_check(BINARY_INFO_TYPE_ID_AND_STRING), \ - .tag = _tag, \ - },\ - .id = _id, \ - .value = _value, \ - } - -#define __bi_ptr_int32_with_name(_tag, _id, _label, _value) \ - static const struct _binary_info_ptr_int32_with_name __bi_lineno_var_name = { \ - .core = { \ - .type = __bi_enclosure_check(BINARY_INFO_TYPE_PTR_INT32_WITH_NAME), \ - .tag = _tag, \ - },\ - .id = _id, \ - .value = &_value, \ - .label = _label, \ - } - -#define bi_ptr_int32(_tag, _id, _var, _default) __attribute__((section(".data"))) static int _var = _default; __bi_ptr_int32_with_name(_tag, _id, __STRING(_var), _var) - -#define __bi_ptr_string_with_name(_tag, _id, _label, _value, _len) \ - static const struct _binary_info_ptr_string_with_name __bi_lineno_var_name = { \ - .core = { \ - .type = __bi_enclosure_check(BINARY_INFO_TYPE_PTR_STRING_WITH_NAME), \ - .tag = _tag, \ - },\ - .id = _id, \ - .value = _value, \ - .label = _label, \ - .len = _len, \ - } - -#define bi_ptr_string(_tag, _id, _var, _default, _max_len) static char _var[_max_len] = _default; __bi_ptr_string_with_name(_tag, _id, __STRING(_var), _var, _max_len) - -#define bi_block_device(_tag, _name, _address, _size, _extra, _flags) \ - static const struct _binary_info_block_device __bi_lineno_var_name = { \ - .core = { \ - .type = __bi_enclosure_check(BINARY_INFO_TYPE_BLOCK_DEVICE), \ - .tag = _tag, \ - },\ - .name = _name, \ - .address = _address, \ - .size = _size, \ - .extra = _extra, \ - .flags = _flags, \ - } - -#define __bi_encoded_pins_with_func(_encoding) \ - static const struct _binary_info_pins_with_func __bi_lineno_var_name = { \ - .core = { \ - .type = __bi_enclosure_check(BINARY_INFO_TYPE_PINS_WITH_FUNC), \ - .tag = BINARY_INFO_TAG_RASPBERRY_PI, \ - },\ - .pin_encoding = _encoding \ - } - -#define __bi_encoded_pins_64_with_func(_encoding) \ - static const struct _binary_info_pins64_with_func __bi_lineno_var_name = { \ - .core = { \ - .type = __bi_enclosure_check(BINARY_INFO_TYPE_PINS64_WITH_FUNC), \ - .tag = BINARY_INFO_TAG_RASPBERRY_PI, \ - },\ - .pin_encoding = _encoding \ - } - -#define __bi_pins_with_name(_mask, _label) \ - static const struct _binary_info_pins_with_name __bi_lineno_var_name = { \ - .core = { \ - .type = __bi_enclosure_check(BINARY_INFO_TYPE_PINS_WITH_NAME), \ - .tag = BINARY_INFO_TAG_RASPBERRY_PI, \ - },\ - .pin_mask = _mask, \ - .label = _label \ - } - -#define __bi_pins_64_with_name(_mask, _label) \ - static const struct _binary_info_pins64_with_name __bi_lineno_var_name = { \ - .core = { \ - .type = __bi_enclosure_check(BINARY_INFO_TYPE_PINS64_WITH_NAME), \ - .tag = BINARY_INFO_TAG_RASPBERRY_PI, \ - },\ - .pin_mask = _mask, \ - .label = _label \ - } - -#define __bi_named_group(_parent_tag, _parent_id, _group_tag, _group_id, _label, _flags) \ -static const struct _binary_info_named_group __bi_lineno_var_name = { \ - .core = { \ - .type = __bi_enclosure_check(BINARY_INFO_TYPE_NAMED_GROUP), \ - .tag = _parent_tag, \ - },\ - .parent_id = _parent_id, \ - .group_tag = _group_tag, \ - .flags = _flags, \ - .group_id = _group_id, \ - .label = _label \ - } - -#define bi_binary_end(end) bi_int(BINARY_INFO_TAG_RASPBERRY_PI, BINARY_INFO_ID_RP_BINARY_END, end) -#define bi_program_name(name) bi_string(BINARY_INFO_TAG_RASPBERRY_PI, BINARY_INFO_ID_RP_PROGRAM_NAME, name) -#define bi_program_description(description) bi_string(BINARY_INFO_TAG_RASPBERRY_PI, BINARY_INFO_ID_RP_PROGRAM_DESCRIPTION, description) -#define bi_program_version_string(version_string) bi_string(BINARY_INFO_TAG_RASPBERRY_PI, BINARY_INFO_ID_RP_PROGRAM_VERSION_STRING, version_string) -#define bi_program_build_date_string(date_string) bi_string(BINARY_INFO_TAG_RASPBERRY_PI, BINARY_INFO_ID_RP_PROGRAM_BUILD_DATE_STRING, date_string) -#define bi_program_url(url) bi_string(BINARY_INFO_TAG_RASPBERRY_PI, BINARY_INFO_ID_RP_PROGRAM_URL, url) -// multiple of these may be added -#define bi_program_feature(feature) bi_string(BINARY_INFO_TAG_RASPBERRY_PI, BINARY_INFO_ID_RP_PROGRAM_FEATURE, feature) -#define bi_program_build_attribute(attr) bi_string(BINARY_INFO_TAG_RASPBERRY_PI, BINARY_INFO_ID_RP_PROGRAM_BUILD_ATTRIBUTE, attr) -#define bi_program_feature_group(tag, id, name) __bi_named_group(BINARY_INFO_TAG_RASPBERRY_PI, BINARY_INFO_ID_RP_PROGRAM_FEATURE, tag, id, name, 0) -#define bi_program_feature_group_with_flags(tag, id, name, flags) __bi_named_group(BINARY_INFO_TAG_RASPBERRY_PI, BINARY_INFO_ID_RP_PROGRAM_FEATURE, tag, id, name, flags) - - -#ifndef PICO_BINARY_INFO_USE_PINS_64 -#define PICO_BINARY_INFO_USE_PINS_64 (NUM_BANK0_GPIOS > 32) -#endif - -#if !PICO_BINARY_INFO_USE_PINS_64 -#define bi_1pin_with_func(p0, func) __bi_encoded_pins_with_func(BI_PINS_ENCODING_MULTI | ((func << 3)) | ((p0) << 7) | ((p0) << 12)) -#define bi_2pins_with_func(p0, p1, func) __bi_encoded_pins_with_func(BI_PINS_ENCODING_MULTI | ((func << 3)) | ((p0) << 7) | ((p1) << 12) | ((p1) << 17)) -#define bi_3pins_with_func(p0, p1, p2, func) __bi_encoded_pins_with_func(BI_PINS_ENCODING_MULTI | ((func << 3)) | ((p0) << 7) | ((p1) << 12) | ((p2) << 17) | ((p2) << 22)) -#define bi_4pins_with_func(p0, p1, p2, p3, func) __bi_encoded_pins_with_func(BI_PINS_ENCODING_MULTI | ((func << 3)) | ((p0) << 7) | ((p1) << 12) | ((p2) << 17) | ((p3) << 22) | ((p3) << 27)) -#define bi_5pins_with_func(p0, p1, p2, p3, p4, func) __bi_encoded_pins_with_func(BI_PINS_ENCODING_MULTI | ((func << 3)) | ((p0) << 7) | ((p1) << 12) | ((p2) << 17) | ((p3) << 22) | ((p4) << 27)) -#define bi_pin_range_with_func(plo, phi, func) __bi_encoded_pins_with_func(BI_PINS_ENCODING_RANGE | ((func << 3)) | ((plo) << 7) | ((phi) << 12)) - -#define bi_pin_mask_with_name(pmask, label) __bi_pins_with_name((pmask), (label)) -// names are separated by | ... i.e. "name1|name2|name3" -#define bi_pin_mask_with_names(pmask, label) __bi_pins_with_name((pmask), (label)) -#else -#define bi_1pin_with_func(p0, func) __bi_encoded_pins_64_with_func(BI_PINS_ENCODING_MULTI | ((func << 3)) | ((p0) << 8) | ((p0) << 16)) -#define bi_2pins_with_func(p0, p1, func) __bi_encoded_pins_64_with_func(BI_PINS_ENCODING_MULTI | ((func << 3)) | ((p0) << 8) | ((p1) << 16) | ((p1) << 24)) -#define bi_3pins_with_func(p0, p1, p2, func) __bi_encoded_pins_64_with_func(BI_PINS_ENCODING_MULTI | ((func << 3)) | ((p0) << 8) | ((p1) << 16) | ((p2) << 24) | ((uint64_t)(p2) << 32)) -#define bi_4pins_with_func(p0, p1, p2, p3, func) __bi_encoded_pins_64_with_func(BI_PINS_ENCODING_MULTI | ((func << 3)) | ((p0) << 8) | ((p1) << 16) | ((p2) << 24) | ((uint64_t)(p3) << 32) | ((uint64_t)(p3) << 40)) -#define bi_5pins_with_func(p0, p1, p2, p3, p4, func) __bi_encoded_pins_64_with_func(BI_PINS_ENCODING_MULTI | ((func << 3)) | ((p0) << 8) | ((p1) << 16) | ((p2) << 24) | ((uint64_t)(p3) << 32) | ((uint64_t)(p4) << 40) | ((uint64_t)(p4) << 48)) -#define bi_pin_range_with_func(plo, phi, func) __bi_encoded_pins_64_with_func(BI_PINS_ENCODING_RANGE | ((func << 3)) | ((plo) << 8) | ((phi) << 16)) - -#define bi_pin_mask_with_name(pmask, label) __bi_pins_64_with_name((uint64_t)(pmask), (label)) -// names are separated by | ... i.e. "name1|name2|name3" -#define bi_pin_mask_with_names(pmask, label) __bi_pins_64_with_name((uint64_t)(pmask), (label)) -#endif - -// 6 and 7 pins require pins_64 -#define bi_6pins_with_func(p0, p1, p2, p3, p4, p5, func) __bi_encoded_pins_64_with_func(BI_PINS_ENCODING_MULTI | ((func << 3)) | ((p0) << 8) | ((p1) << 16) | ((p2) << 24) | ((uint64_t)(p3) << 32) | ((uint64_t)(p4) << 40) | ((uint64_t)(p5) << 48) | ((uint64_t)(p5) << 56)) -#define bi_7pins_with_func(p0, p1, p2, p3, p4, p5, p6,func) __bi_encoded_pins_64_with_func(BI_PINS_ENCODING_MULTI | ((func << 3)) | ((p0) << 8) | ((p1) << 16) | ((p2) << 24) | ((uint64_t)(p3) << 32) | ((uint64_t)(p4) << 40) | ((uint64_t)(p5) << 48) | ((uint64_t)(p6) << 56)) - -#define bi_1pin_with_name(p0, name) bi_pin_mask_with_name(1ull << (p0), name) -#define bi_2pins_with_names(p0, name0, p1, name1) bi_pin_mask_with_names((1ull << (p0)) | (1ull << (p1)), p0 < p1 ? name0 "|" name1 : name1 "|" name0) -#define bi_3pins_with_names(p0, name0, p1, name1, p2, name2) bi_pin_mask_with_names((1ull << (p0)) | (1ull << (p1)) | (1ull << (p2)),\ - p0 < p1 ?\ - (p1 < p2 ?\ - name0 "|" name1 "|" name2:\ - (p0 < p2 ? name0 "|" name2 "|" name1 : name2 "|" name0 "|" name1)):\ - (p1 < p2 ?\ - (p0 < p2 ? name1 "|" name0 "|" name2 : name1 "|" name2 "|" name0) :\ - name2 "|" name1 "|" name0)) -#define bi_4pins_with_names(p0, name0, p1, name1, p2, name2, p3, name3) bi_pin_mask_with_names((1ull << (p0)) | (1ull << (p1)) | (1ull << (p2)) | (1ull << (p3)),\ - p0 < p1 ?\ - (p1 < p2 ?\ - (p2 < p3 ?\ - name0 "|" name1 "|" name2 "|" name3:\ - (p0 < p3 ?\ - (p1 < p3 ?\ - name0 "|" name1 "|" name3 "|" name2:\ - name0 "|" name3 "|" name1 "|" name2):\ - name3 "|" name0 "|" name1 "|" name2)):\ - (p2 < p3 ?\ - (p0 < p2 ?\ - (p1 < p3 ?\ - name0 "|" name2 "|" name1 "|" name3:\ - name0 "|" name2 "|" name3 "|" name1):\ - (p0 < p3 ?\ - (p1 < p3 ?\ - name2 "|" name0 "|" name1 "|" name3:\ - name2 "|" name0 "|" name3 "|" name1):\ - name2 "|" name3 "|" name0 "|" name1)):\ - (p0 < p2 ?\ - (p0 < p3 ?\ - name0 "|" name3 "|" name2 "|" name1:\ - name3 "|" name0 "|" name2 "|" name1):\ - name3 "|" name2 "|" name0 "|" name1))):\ - (p1 < p2 ?\ - (p2 < p3 ?\ - (p0 < p2 ?\ - name1 "|" name0 "|" name2 "|" name3:\ - (p0 < p3 ?\ - name1 "|" name2 "|" name0 "|" name3:\ - name1 "|" name2 "|" name3 "|" name0)):\ - (p0 < p2 ?\ - (p0 < p3 ?\ - name1 "|" name0 "|" name3 "|" name2:\ - (p1 < p3 ?\ - name1 "|" name3 "|" name0 "|" name2:\ - name3 "|" name1 "|" name0 "|" name2)):\ - (p1 < p3 ?\ - name1 "|" name3 "|" name2 "|" name0:\ - name3 "|" name1 "|" name2 "|" name0))):\ - (p2 < p3 ?\ - (p0 < p3 ?\ - name2 "|" name1 "|" name0 "|" name3:\ - (p1 < p3 ?\ - name2 "|" name1 "|" name3 "|" name0:\ - name2 "|" name3 "|" name1 "|" name0)):\ - name3 "|" name2 "|" name1 "|" name0))) - -#endif diff --git a/lib/main/pico-sdk/common/pico_binary_info/include/pico/binary_info/defs.h b/lib/main/pico-sdk/common/pico_binary_info/include/pico/binary_info/defs.h deleted file mode 100644 index 774992fa3f..0000000000 --- a/lib/main/pico-sdk/common/pico_binary_info/include/pico/binary_info/defs.h +++ /dev/null @@ -1,43 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _PICO_BINARY_INFO_DEFS_H -#define _PICO_BINARY_INFO_DEFS_H - -// this file is for pre-processor definitions only - -// should be found within the first 256 bytes of the real binary (i.e. after the flash second stage if a flash binary) -// -// Note the layout is: -// -// addr : BINARY_INFO_MARKER_START -// addr+0x04 : __binary_info_start -// addr+0x08 : __binary_info_end -// addr+0x0c : __address_mapping_table -// addr+0x10 | BINARY_INFO_MARKER_END -// -// __binary_info_start to __binary_info_end are the start, end (non inclusive) of an array -// of pointers to binary_info_t structures -// -// __address_mapping_table is an array of the following items: -// -// uint32_t source_addr_start -// uint32_t dest_addr_start -// uint32_t dest_addr_end -// -// representing a mapping from the stored address in the binary/flash to addresses at runtime. -// The linker will store pointers within the binary using their runtime values, however because of -// "AT" mapping in the link script these addresses actually correspond to a different address in the binary -// image. This mapping (which in the case of crt0.S is simply the data copy table used at initialization -// to copy data into its runtime location) can be used by picotool or others to reverse the mapping to find data -// within the binary. -// -// Note the above array is terminated with a NULL source_addr_start - -#define BINARY_INFO_MARKER_START 0x7188ebf2 -#define BINARY_INFO_MARKER_END 0xe71aa390 - -#endif diff --git a/lib/main/pico-sdk/common/pico_binary_info/include/pico/binary_info/structure.h b/lib/main/pico-sdk/common/pico_binary_info/include/pico/binary_info/structure.h deleted file mode 100644 index 1cda5a9bb3..0000000000 --- a/lib/main/pico-sdk/common/pico_binary_info/include/pico/binary_info/structure.h +++ /dev/null @@ -1,181 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _PICO_BINARY_INFO_STRUCTURE_H -#define _PICO_BINARY_INFO_STRUCTURE_H - -// NOTE: This file may be included by non SDK code, so does not use SDK includes - -// NOTE: ALL CHANGES MUST BE BACKWARDS COMPATIBLE - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -#ifndef __packed -#define __packed __attribute__((packed)) -#endif - -typedef struct _binary_info_core binary_info_t; - -#define BINARY_INFO_TYPE_RAW_DATA 1 -#define BINARY_INFO_TYPE_SIZED_DATA 2 -#define BINARY_INFO_TYPE_BINARY_INFO_LIST_ZERO_TERMINATED 3 -#define BINARY_INFO_TYPE_BSON 4 -#define BINARY_INFO_TYPE_ID_AND_INT 5 -#define BINARY_INFO_TYPE_ID_AND_STRING 6 -// traditional block device -#define BINARY_INFO_TYPE_BLOCK_DEVICE 7 -#define BINARY_INFO_TYPE_PINS_WITH_FUNC 8 -#define BINARY_INFO_TYPE_PINS_WITH_NAME 9 -#define BINARY_INFO_TYPE_NAMED_GROUP 10 -#define BINARY_INFO_TYPE_PTR_INT32_WITH_NAME 11 -#define BINARY_INFO_TYPE_PTR_STRING_WITH_NAME 12 -#define BINARY_INFO_TYPE_PINS64_WITH_FUNC 13 -#define BINARY_INFO_TYPE_PINS64_WITH_NAME 14 - -// note plan is to reserve c1 = 0->31 for "collision tags"; i.e. -// for which you should always use random IDs with the binary_info, -// giving you 4 + 8 + 32 = 44 bits to avoid collisions -#define BINARY_INFO_MAKE_TAG(c1, c2) ((((uint)c2&0xffu)<<8u)|((uint)c1&0xffu)) - -// Raspberry Pi defined. do not use -#define BINARY_INFO_TAG_RASPBERRY_PI BINARY_INFO_MAKE_TAG('R','P') - -#define BINARY_INFO_ID_RP_PROGRAM_NAME 0x02031c86 -#define BINARY_INFO_ID_RP_PROGRAM_VERSION_STRING 0x11a9bc3a -#define BINARY_INFO_ID_RP_PROGRAM_BUILD_DATE_STRING 0x9da22254 -#define BINARY_INFO_ID_RP_BINARY_END 0x68f465de -#define BINARY_INFO_ID_RP_PROGRAM_URL 0x1856239a -#define BINARY_INFO_ID_RP_PROGRAM_DESCRIPTION 0xb6a07c19 -#define BINARY_INFO_ID_RP_PROGRAM_FEATURE 0xa1f4b453 -#define BINARY_INFO_ID_RP_PROGRAM_BUILD_ATTRIBUTE 0x4275f0d3 -#define BINARY_INFO_ID_RP_SDK_VERSION 0x5360b3ab -#define BINARY_INFO_ID_RP_PICO_BOARD 0xb63cffbb -#define BINARY_INFO_ID_RP_BOOT2_NAME 0x7f8882e1 - -#if PICO_ON_DEVICE -#define bi_ptr_of(x) x * -#else -#define bi_ptr_of(x) uint32_t -#endif -typedef struct __packed _binary_info_core { - uint16_t type; - uint16_t tag; -} binary_info_core_t; - -typedef struct __packed _binary_info_raw_data { - struct _binary_info_core core; - uint8_t bytes[1]; -} binary_info_raw_data_t; - -typedef struct __packed _binary_info_sized_data { - struct _binary_info_core core; - uint32_t length; - uint8_t bytes[1]; -} binary_info_sized_data_t; - -typedef struct __packed _binary_info_list_zero_terminated { - struct _binary_info_core core; - bi_ptr_of(binary_info_t) list; -} binary_info_list_zero_terminated_t; - -typedef struct __packed _binary_info_id_and_int { - struct _binary_info_core core; - uint32_t id; - int32_t value; -} binary_info_id_and_int_t; - -typedef struct __packed _binary_info_id_and_string { - struct _binary_info_core core; - uint32_t id; - bi_ptr_of(const char) value; -} binary_info_id_and_string_t; - -typedef struct __packed _binary_info_ptr_int32_with_name { - struct _binary_info_core core; - int32_t id; - bi_ptr_of(const int) value; - bi_ptr_of(const char) label; -} binary_info_ptr_int32_with_name_t; - -typedef struct __packed _binary_info_ptr_string_with_name { - struct _binary_info_core core; - int32_t id; - bi_ptr_of(const char) value; - bi_ptr_of(const char) label; - uint32_t len; -} binary_info_ptr_string_with_name_t; - -typedef struct __packed _binary_info_block_device { - struct _binary_info_core core; - bi_ptr_of(const char) name; // optional static name (independent of what is formatted) - uint32_t address; - uint32_t size; - bi_ptr_of(binary_info_t) extra; // additional info - uint16_t flags; -} binary_info_block_device_t; - -#define BI_PINS_ENCODING_RANGE 1 -#define BI_PINS_ENCODING_MULTI 2 - -typedef struct __packed _binary_info_pins_with_func { - struct _binary_info_core core; - // p4_5 : p3_5 : p2_5 : p1_5 : p0_5 : func_4 : 010_3 //individual pins p0,p1,p2,p3,p4 ... if fewer than 5 then duplicate p - // phi_5 : plo_5 : func_4 : 001_3 // pin range plo-phi inclusive - uint32_t pin_encoding; -} binary_info_pins_with_func_t; - -typedef struct __packed _binary_info_pins64_with_func { - struct _binary_info_core core; - // p6_8 : p5_8 : p4_8 : p3_8 : p2_8 : p1_8 : p0_8 : func_5 : 010_3 //individual pins p0,p1,p2 ... if fewer than 7 then duplicate p - // phi_8 : plo_8 : func_5 : 001_3 // pin range plo-phi inclusive - uint64_t pin_encoding; -} binary_info_pins64_with_func_t; - -typedef struct __packed _binary_info_pins_with_name { - struct _binary_info_core core; - uint32_t pin_mask; - bi_ptr_of(const char) label; -} binary_info_pins_with_name_t; - -typedef struct __packed _binary_info_pins64_with_name { - struct _binary_info_core core; - uint64_t pin_mask; - bi_ptr_of(const char) label; -} binary_info_pins64_with_name_t; - -#define BI_NAMED_GROUP_SHOW_IF_EMPTY 0x0001 // default is to hide -#define BI_NAMED_GROUP_SEPARATE_COMMAS 0x0002 // default is newlines -#define BI_NAMED_GROUP_SORT_ALPHA 0x0004 // default is no sort -#define BI_NAMED_GROUP_ADVANCED 0x0008 // if set, then only shown in say info -a - -typedef struct __packed _binary_info_named_group { - struct _binary_info_core core; - uint32_t parent_id; - uint16_t flags; - uint16_t group_tag; - uint32_t group_id; - bi_ptr_of(const char) label; -} binary_info_named_group_t; - -enum { - BINARY_INFO_BLOCK_DEV_FLAG_READ = 1 << 0, // if not readable, then it is basically hidden, but tools may choose to avoid overwriting it - BINARY_INFO_BLOCK_DEV_FLAG_WRITE = 1 << 1, - BINARY_INFO_BLOCK_DEV_FLAG_REFORMAT = 1 << 2, // may be reformatted.. - - BINARY_INFO_BLOCK_DEV_FLAG_PT_UNKNOWN = 0 << 4, // unknown free to look - BINARY_INFO_BLOCK_DEV_FLAG_PT_MBR = 1 << 4, // expect MBR - BINARY_INFO_BLOCK_DEV_FLAG_PT_GPT = 2 << 4, // expect GPT - BINARY_INFO_BLOCK_DEV_FLAG_PT_NONE = 3 << 4, // no partition table -}; - -#ifdef __cplusplus -} -#endif -#endif diff --git a/lib/main/pico-sdk/common/pico_bit_ops_headers/include/pico/bit_ops.h b/lib/main/pico-sdk/common/pico_bit_ops_headers/include/pico/bit_ops.h deleted file mode 100644 index 4324e52468..0000000000 --- a/lib/main/pico-sdk/common/pico_bit_ops_headers/include/pico/bit_ops.h +++ /dev/null @@ -1,45 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _PICO_BIT_OPS_H -#define _PICO_BIT_OPS_H - -#include "pico.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** \file bit_ops.h -* \defgroup pico_bit_ops pico_bit_ops -* -* \brief Optimized bit manipulation functions -* -* Additionally provides replacement implementations of the compiler built-ins __builtin_popcount, __builtin_clz -* and __bulitin_ctz -*/ - -/*! \brief Reverse the bits in a 32 bit word - * \ingroup pico_bit_ops - * - * \param bits 32 bit input - * \return the 32 input bits reversed - */ -uint32_t __rev(uint32_t bits); - -/*! \brief Reverse the bits in a 64 bit double word - * \ingroup pico_bit_ops - * - * \param bits 64 bit input - * \return the 64 input bits reversed - */ -uint64_t __revll(uint64_t bits); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/lib/main/pico-sdk/common/pico_divider_headers/include/pico/divider.h b/lib/main/pico-sdk/common/pico_divider_headers/include/pico/divider.h deleted file mode 100644 index 45c448db87..0000000000 --- a/lib/main/pico-sdk/common/pico_divider_headers/include/pico/divider.h +++ /dev/null @@ -1,323 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _PICO_DIVIDER_H -#define _PICO_DIVIDER_H - -#include "pico.h" -#include "hardware/divider.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \defgroup pico_divider pico_divider - * \brief Optimized 32 and 64 bit division functions accelerated by the RP2040 hardware divider - * - * Additionally provides integration with the C `/` and `%` operators - */ - -/** \file pico/divider.h -* \brief High level APIs including combined quotient and remainder functions for 32 and 64 bit accelerated by the hardware divider -* \ingroup pico_divider -* -* These functions all call __aeabi_idiv0 or __aebi_ldiv0 on division by zero -* passing the largest applicably signed value -* -* Functions with unsafe in their name do not save/restore divider state, so are unsafe to call from interrupts. Unsafe functions are slightly faster. -*/ - -/** - * \brief Integer divide of two signed 32-bit values - * \ingroup pico_divider - * - * \param a Dividend - * \param b Divisor - * \return quotient - */ -int32_t div_s32s32(int32_t a, int32_t b); - -/** - * \brief Integer divide of two signed 32-bit values, with remainder - * \ingroup pico_divider - * - * \param a Dividend - * \param b Divisor - * \param [out] rem The remainder of dividend/divisor - * \return Quotient result of dividend/divisor - */ -static inline int32_t divmod_s32s32_rem(int32_t a, int32_t b, int32_t *rem) { - divmod_result_t r = hw_divider_divmod_s32(a, b); - *rem = to_remainder_s32(r); - return to_quotient_s32(r); -} - -/** - * \brief Integer divide of two signed 32-bit values - * \ingroup pico_divider - * - * \param a Dividend - * \param b Divisor - * \return quotient in low word/r0, remainder in high word/r1 - */ -divmod_result_t divmod_s32s32(int32_t a, int32_t b); - -/** - * \brief Integer divide of two unsigned 32-bit values - * \ingroup pico_divider - * - * \param a Dividend - * \param b Divisor - * \return Quotient - */ -uint32_t div_u32u32(uint32_t a, uint32_t b); - -/** - * \brief Integer divide of two unsigned 32-bit values, with remainder - * \ingroup pico_divider - * - * \param a Dividend - * \param b Divisor - * \param [out] rem The remainder of dividend/divisor - * \return Quotient result of dividend/divisor - */ -static inline uint32_t divmod_u32u32_rem(uint32_t a, uint32_t b, uint32_t *rem) { - divmod_result_t r = hw_divider_divmod_u32(a, b); - *rem = to_remainder_u32(r); - return to_quotient_u32(r); -} - -/** - * \brief Integer divide of two unsigned 32-bit values - * \ingroup pico_divider - * - * \param a Dividend - * \param b Divisor - * \return quotient in low word/r0, remainder in high word/r1 - */ -divmod_result_t divmod_u32u32(uint32_t a, uint32_t b); - -/** - * \brief Integer divide of two signed 64-bit values - * \ingroup pico_divider - * - * \param a Dividend - * \param b Divisor - * \return Quotient - */ -int64_t div_s64s64(int64_t a, int64_t b); - -/** - * \brief Integer divide of two signed 64-bit values, with remainder - * \ingroup pico_divider - * - * \param a Dividend - * \param b Divisor - * \param [out] rem The remainder of dividend/divisor - * \return Quotient result of dividend/divisor - */ -int64_t divmod_s64s64_rem(int64_t a, int64_t b, int64_t *rem); - -/** - * \brief Integer divide of two signed 64-bit values - * \ingroup pico_divider - * - * \param a Dividend - * \param b Divisor - * \return quotient in result (r0,r1), remainder in regs (r2, r3) - */ -int64_t divmod_s64s64(int64_t a, int64_t b); - -/** - * \brief Integer divide of two unsigned 64-bit values - * \ingroup pico_divider - * - * \param a Dividend - * \param b Divisor - * \return Quotient - */ -uint64_t div_u64u64(uint64_t a, uint64_t b); - -/** - * \brief Integer divide of two unsigned 64-bit values, with remainder - * \ingroup pico_divider - * - * \param a Dividend - * \param b Divisor - * \param [out] rem The remainder of dividend/divisor - * \return Quotient result of dividend/divisor - */ -uint64_t divmod_u64u64_rem(uint64_t a, uint64_t b, uint64_t *rem); - - -/** - * \brief Integer divide of two signed 64-bit values - * \ingroup pico_divider - * - * \param a Dividend - * \param b Divisor - * \return quotient in result (r0,r1), remainder in regs (r2, r3) - */ -uint64_t divmod_u64u64(uint64_t a, uint64_t b); - -// ----------------------------------------------------------------------- -// these "unsafe" functions are slightly faster, but do not save the divider state, -// so are not generally safe to be called from interrupts -// ----------------------------------------------------------------------- - -/** - * \brief Unsafe integer divide of two signed 32-bit values - * \ingroup pico_divider - * - * \param a Dividend - * \param b Divisor - * \return quotient - * - * Do not use in interrupts - */ -int32_t div_s32s32_unsafe(int32_t a, int32_t b); - -/** - * \brief Unsafe integer divide of two signed 32-bit values, with remainder - * \ingroup pico_divider - * - * \param a Dividend - * \param b Divisor - * \param [out] rem The remainder of dividend/divisor - * \return Quotient result of dividend/divisor - * - * Do not use in interrupts - */ -int32_t divmod_s32s32_rem_unsafe(int32_t a, int32_t b, int32_t *rem); - -/** - * \brief Unsafe integer divide of two unsigned 32-bit values - * \ingroup pico_divider - * - * \param a Dividend - * \param b Divisor - * \return quotient in low word/r0, remainder in high word/r1 - * - * Do not use in interrupts - */ -divmod_result_t divmod_s32s32_unsafe(int32_t a, int32_t b); - -/** - * \brief Unsafe integer divide of two unsigned 32-bit values - * \ingroup pico_divider - * - * \param a Dividend - * \param b Divisor - * \return Quotient - * - * Do not use in interrupts - */ -uint32_t div_u32u32_unsafe(uint32_t a, uint32_t b); - -/** - * \brief Unsafe integer divide of two unsigned 32-bit values, with remainder - * \ingroup pico_divider - * - * \param a Dividend - * \param b Divisor - * \param [out] rem The remainder of dividend/divisor - * \return Quotient result of dividend/divisor - * - * Do not use in interrupts - */ -uint32_t divmod_u32u32_rem_unsafe(uint32_t a, uint32_t b, uint32_t *rem); - -/** - * \brief Unsafe integer divide of two unsigned 32-bit values - * \ingroup pico_divider - * - * \param a Dividend - * \param b Divisor - * \return quotient in low word/r0, remainder in high word/r1 - * - * Do not use in interrupts - */ -divmod_result_t divmod_u32u32_unsafe(uint32_t a, uint32_t b); - -/** - * \brief Unsafe integer divide of two signed 64-bit values - * \ingroup pico_divider - * - * \param a Dividend - * \param b Divisor - * \return Quotient - * - * Do not use in interrupts - */ -int64_t div_s64s64_unsafe(int64_t a, int64_t b); - -/** - * \brief Unsafe integer divide of two signed 64-bit values, with remainder - * \ingroup pico_divider - * - * \param a Dividend - * \param b Divisor - * \param [out] rem The remainder of dividend/divisor - * \return Quotient result of dividend/divisor - * - * Do not use in interrupts - */ -int64_t divmod_s64s64_rem_unsafe(int64_t a, int64_t b, int64_t *rem); - -/** - * \brief Unsafe integer divide of two signed 64-bit values - * \ingroup pico_divider - * - * \param a Dividend - * \param b Divisor - * \return quotient in result (r0,r1), remainder in regs (r2, r3) - * - * Do not use in interrupts - */ -int64_t divmod_s64s64_unsafe(int64_t a, int64_t b); - -/** - * \brief Unsafe integer divide of two unsigned 64-bit values - * \ingroup pico_divider - * - * \param a Dividend - * \param b Divisor - * \return Quotient - * - * Do not use in interrupts - */ -uint64_t div_u64u64_unsafe(uint64_t a, uint64_t b); - -/** - * \brief Unsafe integer divide of two unsigned 64-bit values, with remainder - * \ingroup pico_divider - * - * \param a Dividend - * \param b Divisor - * \param [out] rem The remainder of dividend/divisor - * \return Quotient result of dividend/divisor - * - * Do not use in interrupts - */ -uint64_t divmod_u64u64_rem_unsafe(uint64_t a, uint64_t b, uint64_t *rem); - -/** - * \brief Unsafe integer divide of two signed 64-bit values - * \ingroup pico_divider - * - * \param a Dividend - * \param b Divisor - * \return quotient in result (r0,r1), remainder in regs (r2, r3) - * - * Do not use in interrupts - */ -uint64_t divmod_u64u64_unsafe(uint64_t a, uint64_t b); - -#ifdef __cplusplus -} -#endif -#endif diff --git a/lib/main/pico-sdk/common/pico_stdlib_headers/include/pico/stdlib.h b/lib/main/pico-sdk/common/pico_stdlib_headers/include/pico/stdlib.h deleted file mode 100644 index 811f565c90..0000000000 --- a/lib/main/pico-sdk/common/pico_stdlib_headers/include/pico/stdlib.h +++ /dev/null @@ -1,90 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _PICO_STDLIB_H -#define _PICO_STDLIB_H - -#include "pico.h" -#include "pico/stdio.h" -#include "pico/time.h" -#include "hardware/gpio.h" -#include "hardware/uart.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** \file stdlib.h - * \defgroup pico_stdlib pico_stdlib - * - * \brief Aggregation of a core subset of Raspberry Pi Pico SDK libraries used by most executables along with some additional - * utility methods - * - * Including pico_stdlib gives you everything you need to get a basic program running - * which prints to stdout or flashes a LED - * - * This library aggregates: - * - @ref hardware_divider - * - @ref hardware_gpio - * - @ref hardware_uart - * - @ref pico_runtime - * - @ref pico_platform - * - @ref pico_stdio - * - @ref pico_time - * - @ref pico_util - * - * There are some basic default values used by these functions that will default to - * usable values, however, they can be customised in a board definition header via - * config.h or similar - */ - -// Note PICO_STDIO_UART, PICO_STDIO_USB, PICO_STDIO_SEMIHOSTING are set by the -// respective INTERFACE libraries, so these defines are set if the library -// is included for the target executable - -#if LIB_PICO_STDIO_UART -#include "pico/stdio_uart.h" -#endif - -#if LIB_PICO_STDIO_USB -#include "pico/stdio_usb.h" -#endif - -#if LIB_PICO_STDIO_SEMIHOSTING -#include "pico/stdio_semihosting.h" -#endif - -// PICO_CONFIG: PICO_DEFAULT_LED_PIN, Optionally define a pin that drives a regular LED on the board, default=Usually provided via board header, group=pico_stdlib - -// PICO_CONFIG: PICO_DEFAULT_LED_PIN_INVERTED, 1 if LED is inverted or 0 if not, type=int, default=0, group=pico_stdlib -#ifndef PICO_DEFAULT_LED_PIN_INVERTED -#define PICO_DEFAULT_LED_PIN_INVERTED 0 -#endif - -// PICO_CONFIG: PICO_DEFAULT_WS2812_PIN, Optionally define a pin that controls data to a WS2812 compatible LED on the board, group=pico_stdlib -// PICO_CONFIG: PICO_DEFAULT_WS2812_POWER_PIN, Optionally define a pin that controls power to a WS2812 compatible LED on the board, group=pico_stdlib - -/*! \brief Set up the default UART and assign it to the default GPIOs - * \ingroup pico_stdlib - * - * By default this will use UART 0, with TX to pin GPIO 0, - * RX to pin GPIO 1, and the baudrate to 115200 - * - * Calling this method also initializes stdin/stdout over UART if the - * @ref pico_stdio_uart library is linked. - * - * Defaults can be changed using configuration defines, - * PICO_DEFAULT_UART_INSTANCE, - * PICO_DEFAULT_UART_BAUD_RATE - * PICO_DEFAULT_UART_TX_PIN - * PICO_DEFAULT_UART_RX_PIN - */ -void setup_default_uart(void); - -#ifdef __cplusplus -} -#endif -#endif diff --git a/lib/main/pico-sdk/common/pico_sync/critical_section.c b/lib/main/pico-sdk/common/pico_sync/critical_section.c deleted file mode 100644 index d51bf76f2a..0000000000 --- a/lib/main/pico-sdk/common/pico_sync/critical_section.c +++ /dev/null @@ -1,25 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "pico/critical_section.h" - -#if PICO_32BIT -static_assert(sizeof(critical_section_t) == 8, ""); -#endif - -void critical_section_init(critical_section_t *crit_sec) { - critical_section_init_with_lock_num(crit_sec, (uint)spin_lock_claim_unused(true)); -} - -void critical_section_init_with_lock_num(critical_section_t *crit_sec, uint lock_num) { - crit_sec->spin_lock = spin_lock_instance(lock_num); - __mem_fence_release(); -} - -void critical_section_deinit(critical_section_t *crit_sec) { - spin_lock_unclaim(spin_lock_get_num(crit_sec->spin_lock)); - crit_sec->spin_lock = NULL; -} \ No newline at end of file diff --git a/lib/main/pico-sdk/common/pico_sync/include/pico/critical_section.h b/lib/main/pico-sdk/common/pico_sync/include/pico/critical_section.h deleted file mode 100644 index 0e9907a9c0..0000000000 --- a/lib/main/pico-sdk/common/pico_sync/include/pico/critical_section.h +++ /dev/null @@ -1,98 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _PICO_CRITICAL_SECTION_H -#define _PICO_CRITICAL_SECTION_H - -#include "pico/lock_core.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** \file critical_section.h - * \defgroup critical_section critical_section - * \ingroup pico_sync - * \brief Critical Section API for short-lived mutual exclusion safe for IRQ and multi-core - * - * A critical section is non-reentrant, and provides mutual exclusion using a spin-lock to prevent access - * from the other core, and from (higher priority) interrupts on the same core. It does the former - * using a spin lock and the latter by disabling interrupts on the calling core. - * - * Because interrupts are disabled when a critical_section is owned, uses of the critical_section - * should be as short as possible. - */ - -typedef struct __packed_aligned critical_section { - spin_lock_t *spin_lock; - uint32_t save; -} critical_section_t; - -/*! \brief Initialise a critical_section structure allowing the system to assign a spin lock number - * \ingroup critical_section - * - * The critical section is initialized ready for use, and will use a (possibly shared) spin lock - * number assigned by the system. Note that in general it is unlikely that you would be nesting - * critical sections, however if you do so you *must* use \ref critical_section_init_with_lock_num - * to ensure that the spin locks used are different. - * - * \param crit_sec Pointer to critical_section structure - */ -void critical_section_init(critical_section_t *crit_sec); - -/*! \brief Initialise a critical_section structure assigning a specific spin lock number - * \ingroup critical_section - * \param crit_sec Pointer to critical_section structure - * \param lock_num the specific spin lock number to use - */ -void critical_section_init_with_lock_num(critical_section_t *crit_sec, uint lock_num); - -/*! \brief Enter a critical_section - * \ingroup critical_section - * - * If the spin lock associated with this critical section is in use, then this - * method will block until it is released. - * - * \param crit_sec Pointer to critical_section structure - */ -static inline void critical_section_enter_blocking(critical_section_t *crit_sec) { - crit_sec->save = spin_lock_blocking(crit_sec->spin_lock); -} - -/*! \brief Release a critical_section - * \ingroup critical_section - * - * \param crit_sec Pointer to critical_section structure - */ -static inline void critical_section_exit(critical_section_t *crit_sec) { - spin_unlock(crit_sec->spin_lock, crit_sec->save); -} - -/*! \brief De-Initialise a critical_section created by the critical_section_init method - * \ingroup critical_section - * - * This method is only used to free the associated spin lock allocated via - * the critical_section_init method (it should not be used to de-initialize a spin lock - * created via critical_section_init_with_lock_num). After this call, the critical section is invalid - * - * \param crit_sec Pointer to critical_section structure - */ -void critical_section_deinit(critical_section_t *crit_sec); - -/*! \brief Test whether a critical_section has been initialized - * \ingroup mutex - * - * \param crit_sec Pointer to critical_section structure - * \return true if the critical section is initialized, false otherwise - */ -static inline bool critical_section_is_initialized(critical_section_t *crit_sec) { - return crit_sec->spin_lock != 0; -} - -#ifdef __cplusplus -} -#endif -#endif diff --git a/lib/main/pico-sdk/common/pico_sync/include/pico/lock_core.h b/lib/main/pico-sdk/common/pico_sync/include/pico/lock_core.h deleted file mode 100644 index babd285957..0000000000 --- a/lib/main/pico-sdk/common/pico_sync/include/pico/lock_core.h +++ /dev/null @@ -1,199 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _PICO_LOCK_CORE_H -#define _PICO_LOCK_CORE_H - -#include "pico.h" -#include "pico/time.h" -#include "hardware/sync.h" - -/** \file lock_core.h - * \defgroup lock_core lock_core - * \ingroup pico_sync - * \brief base synchronization/lock primitive support. - * - * Most of the pico_sync locking primitives contain a lock_core_t structure member. This currently just holds a spin - * lock which is used only to protect the contents of the rest of the structure as part of implementing the synchronization - * primitive. As such, the spin_lock member of lock core is never still held on return from any function for the primitive. - * - * \ref critical_section is an exceptional case in that it does not have a lock_core_t and simply wraps a spin lock, providing - * methods to lock and unlock said spin lock. - * - * lock_core based structures work by locking the spin lock, checking state, and then deciding whether they additionally need to block - * or notify when the spin lock is released. In the blocking case, they will wake up again in the future, and try the process again. - * - * By default the SDK just uses the processors' events via SEV and WEV for notification and blocking as these are sufficient for - * cross core, and notification from interrupt handlers. However macros are defined in this file that abstract the wait - * and notify mechanisms to allow the SDK locking functions to effectively be used within an RTOS or other environment. - * - * When implementing an RTOS, it is desirable for the SDK synchronization primitives that wait, to block the calling task (and immediately yield), - * and those that notify, to wake a blocked task which isn't on processor. At least the wait macro implementation needs to be atomic with the protecting - * spin_lock unlock from the callers point of view; i.e. the task should unlock the spin lock when it starts its wait. Such implementation is - * up to the RTOS integration, however the macros are defined such that such operations are always combined into a single call - * (so they can be performed atomically) even though the default implementation does not need this, as a WFE which starts - * following the corresponding SEV is not missed. - */ - -// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_LOCK_CORE, Enable/disable assertions in the lock core, type=bool, default=0, group=pico_sync -#ifndef PARAM_ASSERTIONS_ENABLED_LOCK_CORE -#define PARAM_ASSERTIONS_ENABLED_LOCK_CORE 0 -#endif - -/** \file lock_core.h - * \ingroup lock_core - * - * Base implementation for locking primitives protected by a spin lock. The spin lock is only used to protect - * access to the remaining lock state (in primitives using lock_core); it is never left locked outside - * of the function implementations - */ -struct lock_core { - // spin lock protecting this lock's state - spin_lock_t *spin_lock; - - // note any lock members in containing structures need not be volatile; - // they are protected by memory/compiler barriers when gaining and release spin locks -}; - -typedef struct lock_core lock_core_t; - -/*! \brief Initialise a lock structure - * \ingroup lock_core - * - * Inititalize a lock structure, providing the spin lock number to use for protecting internal state. - * - * \param core Pointer to the lock_core to initialize - * \param lock_num Spin lock number to use for the lock. As the spin lock is only used internally to the locking primitive - * method implementations, this does not need to be globally unique, however could suffer contention - */ -void lock_init(lock_core_t *core, uint lock_num); - -#ifndef lock_owner_id_t -/*! \brief type to use to store the 'owner' of a lock. - * \ingroup lock_core - * - * By default this is int8_t as it only needs to store the core number or -1, however it may be - * overridden if a larger type is required (e.g. for an RTOS task id) - */ -#define lock_owner_id_t int8_t -#endif - -#ifndef LOCK_INVALID_OWNER_ID -/*! \brief marker value to use for a lock_owner_id_t which does not refer to any valid owner - * \ingroup lock_core - */ -#define LOCK_INVALID_OWNER_ID ((lock_owner_id_t)-1) -#endif - -#ifndef lock_get_caller_owner_id -/*! \brief return the owner id for the caller - * \ingroup lock_core - * - * By default this returns the calling core number, but may be overridden (e.g. to return an RTOS task id) - */ -#define lock_get_caller_owner_id() ((lock_owner_id_t)get_core_num()) -#ifndef lock_is_owner_id_valid -#define lock_is_owner_id_valid(id) ((id)>=0) -#endif -#endif - -#ifndef lock_is_owner_id_valid -#define lock_is_owner_id_valid(id) ((id) != LOCK_INVALID_OWNER_ID) -#endif - -#ifndef lock_internal_spin_unlock_with_wait -/*! \brief Atomically unlock the lock's spin lock, and wait for a notification. - * \ingroup lock_core - * - * _Atomic_ here refers to the fact that it should not be possible for a concurrent lock_internal_spin_unlock_with_notify - * to insert itself between the spin unlock and this wait in a way that the wait does not see the notification (i.e. causing - * a missed notification). In other words this method should always wake up in response to a lock_internal_spin_unlock_with_notify - * for the same lock, which completes after this call starts. - * - * In an ideal implementation, this method would return exactly after the corresponding lock_internal_spin_unlock_with_notify - * has subsequently been called on the same lock instance, however this method is free to return at _any_ point before that; - * this macro is _always_ used in a loop which locks the spin lock, checks the internal locking primitive state and then - * waits again if the calling thread should not proceed. - * - * By default this macro simply unlocks the spin lock, and then performs a WFE, but may be overridden - * (e.g. to actually block the RTOS task). - * - * \param lock the lock_core for the primitive which needs to block - * \param save the uint32_t value that should be passed to spin_unlock when the spin lock is unlocked. (i.e. the `PRIMASK` - * state when the spin lock was acquire - */ -#define lock_internal_spin_unlock_with_wait(lock, save) spin_unlock((lock)->spin_lock, save), __wfe() -#endif - -#ifndef lock_internal_spin_unlock_with_notify -/*! \brief Atomically unlock the lock's spin lock, and send a notification - * \ingroup lock_core - * - * _Atomic_ here refers to the fact that it should not be possible for this notification to happen during a - * lock_internal_spin_unlock_with_wait in a way that that wait does not see the notification (i.e. causing - * a missed notification). In other words this method should always wake up any lock_internal_spin_unlock_with_wait - * which started before this call completes. - * - * In an ideal implementation, this method would wake up only the corresponding lock_internal_spin_unlock_with_wait - * that has been called on the same lock instance, however it is free to wake up any of them, as they will check - * their condition and then re-wait if necessary/ - * - * By default this macro simply unlocks the spin lock, and then performs a SEV, but may be overridden - * (e.g. to actually un-block RTOS task(s)). - * - * \param lock the lock_core for the primitive which needs to block - * \param save the uint32_t value that should be passed to spin_unlock when the spin lock is unlocked. (i.e. the PRIMASK - * state when the spin lock was acquire) - */ -#define lock_internal_spin_unlock_with_notify(lock, save) spin_unlock((lock)->spin_lock, save), __sev() -#endif - -#ifndef lock_internal_spin_unlock_with_best_effort_wait_or_timeout -/*! \brief Atomically unlock the lock's spin lock, and wait for a notification or a timeout - * \ingroup lock_core - * - * _Atomic_ here refers to the fact that it should not be possible for a concurrent lock_internal_spin_unlock_with_notify - * to insert itself between the spin unlock and this wait in a way that the wait does not see the notification (i.e. causing - * a missed notification). In other words this method should always wake up in response to a lock_internal_spin_unlock_with_notify - * for the same lock, which completes after this call starts. - * - * In an ideal implementation, this method would return exactly after the corresponding lock_internal_spin_unlock_with_notify - * has subsequently been called on the same lock instance or the timeout has been reached, however this method is free to return - * at _any_ point before that; this macro is _always_ used in a loop which locks the spin lock, checks the internal locking - * primitive state and then waits again if the calling thread should not proceed. - * - * By default this simply unlocks the spin lock, and then calls \ref best_effort_wfe_or_timeout - * but may be overridden (e.g. to actually block the RTOS task with a timeout). - * - * \param lock the lock_core for the primitive which needs to block - * \param save the uint32_t value that should be passed to spin_unlock when the spin lock is unlocked. (i.e. the PRIMASK - * state when the spin lock was acquire) - * \param until the \ref absolute_time_t value - * \return true if the timeout has been reached - */ -#define lock_internal_spin_unlock_with_best_effort_wait_or_timeout(lock, save, until) ({ \ - spin_unlock((lock)->spin_lock, save); \ - best_effort_wfe_or_timeout(until); \ -}) -#endif - -#ifndef sync_internal_yield_until_before -/*! \brief yield to other processing until some time before the requested time - * \ingroup lock_core - * - * This method is provided for cases where the caller has no useful work to do - * until the specified time. - * - * By default this method does nothing, however it can be overridden (for example by an - * RTOS which is able to block the current task until the scheduler tick before - * the given time) - * - * \param until the \ref absolute_time_t value - */ -#define sync_internal_yield_until_before(until) ((void)0) -#endif - -#endif diff --git a/lib/main/pico-sdk/common/pico_sync/include/pico/mutex.h b/lib/main/pico-sdk/common/pico_sync/include/pico/mutex.h deleted file mode 100644 index 32eb7a0790..0000000000 --- a/lib/main/pico-sdk/common/pico_sync/include/pico/mutex.h +++ /dev/null @@ -1,313 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _PICO_MUTEX_H -#define _PICO_MUTEX_H - -#include "pico/lock_core.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** \file mutex.h - * \defgroup mutex mutex - * \ingroup pico_sync - * \brief Mutex API for non IRQ mutual exclusion between cores - * - * Mutexes are application level locks usually used protecting data structures that might be used by - * multiple threads of execution. Unlike critical sections, the mutex protected code is not necessarily - * required/expected to complete quickly, as no other system wide locks are held on account of an acquired mutex. - * - * When acquired, the mutex has an owner (see \ref lock_get_caller_owner_id) which with the plain SDK is just - * the acquiring core, but in an RTOS it could be a task, or an IRQ handler context. - * - * Two variants of mutex are provided; \ref mutex_t (and associated mutex_ functions) is a regular mutex that cannot - * be acquired recursively by the same owner (a deadlock will occur if you try). \ref recursive_mutex_t - * (and associated recursive_mutex_ functions) is a recursive mutex that can be recursively obtained by - * the same caller, at the expense of some more overhead when acquiring and releasing. - * - * It is generally a bad idea to call blocking mutex_ or recursive_mutex_ functions from within an IRQ handler. - * It is valid to call \ref mutex_try_enter or \ref recursive_mutex_try_enter from within an IRQ handler, if the operation - * that would be conducted under lock can be skipped if the mutex is locked (at least by the same owner). - * - * NOTE: For backwards compatibility with version 1.2.0 of the SDK, if the define - * PICO_MUTEX_ENABLE_SDK120_COMPATIBILITY is set to 1, then the the regular mutex_ functions - * may also be used for recursive mutexes. This flag will be removed in a future version of the SDK. - * - * See \ref critical_section.h for protecting access between multiple cores AND IRQ handlers - */ - -/*! \brief recursive mutex instance - * \ingroup mutex - */ -typedef struct { - lock_core_t core; - lock_owner_id_t owner; //! owner id LOCK_INVALID_OWNER_ID for unowned - uint8_t enter_count; //! ownership count -#if PICO_MUTEX_ENABLE_SDK120_COMPATIBILITY - bool recursive; -#endif -} recursive_mutex_t; - -/*! \brief regular (non recursive) mutex instance - * \ingroup mutex - */ -#if !PICO_MUTEX_ENABLE_SDK120_COMPATIBILITY -typedef struct mutex { - lock_core_t core; - lock_owner_id_t owner; //! owner id LOCK_INVALID_OWNER_ID for unowned -} mutex_t; -#else -typedef recursive_mutex_t mutex_t; // they are one and the same when backwards compatible with SDK1.2.0 -#endif - -/*! \brief Initialise a mutex structure - * \ingroup mutex - * - * \param mtx Pointer to mutex structure - */ -void mutex_init(mutex_t *mtx); - -/*! \brief Initialise a recursive mutex structure - * \ingroup mutex - * - * A recursive mutex may be entered in a nested fashion by the same owner - * - * \param mtx Pointer to recursive mutex structure - */ -void recursive_mutex_init(recursive_mutex_t *mtx); - -/*! \brief Take ownership of a mutex - * \ingroup mutex - * - * This function will block until the caller can be granted ownership of the mutex. - * On return the caller owns the mutex - * - * \param mtx Pointer to mutex structure - */ -void mutex_enter_blocking(mutex_t *mtx); - -/*! \brief Take ownership of a recursive mutex - * \ingroup mutex - * - * This function will block until the caller can be granted ownership of the mutex. - * On return the caller owns the mutex - * - * \param mtx Pointer to recursive mutex structure - */ -void recursive_mutex_enter_blocking(recursive_mutex_t *mtx); - -/*! \brief Attempt to take ownership of a mutex - * \ingroup mutex - * - * If the mutex wasn't owned, this will claim the mutex for the caller and return true. - * Otherwise (if the mutex was already owned) this will return false and the - * caller will NOT own the mutex. - * - * \param mtx Pointer to mutex structure - * \param owner_out If mutex was already owned, and this pointer is non-zero, it will be filled in with the owner id of the current owner of the mutex - * \return true if mutex now owned, false otherwise - */ -bool mutex_try_enter(mutex_t *mtx, uint32_t *owner_out); - -/*! \brief Attempt to take ownership of a mutex until the specified time - * \ingroup mutex - * - * If the mutex wasn't owned, this method will immediately claim the mutex for the caller and return true. - * If the mutex is owned by the caller, this method will immediately return false, - * If the mutex is owned by someone else, this method will try to claim it until the specified time, returning - * true if it succeeds, or false on timeout - * - * \param mtx Pointer to mutex structure - * \param until The time after which to return if the caller cannot be granted ownership of the mutex - * \return true if mutex now owned, false otherwise - */ -bool mutex_try_enter_block_until(mutex_t *mtx, absolute_time_t until); - -/*! \brief Attempt to take ownership of a recursive mutex - * \ingroup mutex - * - * If the mutex wasn't owned or was owned by the caller, this will claim the mutex and return true. - * Otherwise (if the mutex was already owned by another owner) this will return false and the - * caller will NOT own the mutex. - * - * \param mtx Pointer to recursive mutex structure - * \param owner_out If mutex was already owned by another owner, and this pointer is non-zero, - * it will be filled in with the owner id of the current owner of the mutex - * \return true if the recursive mutex (now) owned, false otherwise - */ -bool recursive_mutex_try_enter(recursive_mutex_t *mtx, uint32_t *owner_out); - -/*! \brief Wait for mutex with timeout - * \ingroup mutex - * - * Wait for up to the specific time to take ownership of the mutex. If the caller - * can be granted ownership of the mutex before the timeout expires, then true will be returned - * and the caller will own the mutex, otherwise false will be returned and the caller will NOT own the mutex. - * - * \param mtx Pointer to mutex structure - * \param timeout_ms The timeout in milliseconds. - * \return true if mutex now owned, false if timeout occurred before ownership could be granted - */ -bool mutex_enter_timeout_ms(mutex_t *mtx, uint32_t timeout_ms); - -/*! \brief Wait for recursive mutex with timeout - * \ingroup mutex - * - * Wait for up to the specific time to take ownership of the recursive mutex. If the caller - * already has ownership of the mutex or can be granted ownership of the mutex before the timeout expires, - * then true will be returned and the caller will own the mutex, otherwise false will be returned and the caller - * will NOT own the mutex. - * - * \param mtx Pointer to recursive mutex structure - * \param timeout_ms The timeout in milliseconds. - * \return true if the recursive mutex (now) owned, false if timeout occurred before ownership could be granted - */ -bool recursive_mutex_enter_timeout_ms(recursive_mutex_t *mtx, uint32_t timeout_ms); - -/*! \brief Wait for mutex with timeout - * \ingroup mutex - * - * Wait for up to the specific time to take ownership of the mutex. If the caller - * can be granted ownership of the mutex before the timeout expires, then true will be returned - * and the caller will own the mutex, otherwise false will be returned and the caller - * will NOT own the mutex. - * - * \param mtx Pointer to mutex structure - * \param timeout_us The timeout in microseconds. - * \return true if mutex now owned, false if timeout occurred before ownership could be granted - */ -bool mutex_enter_timeout_us(mutex_t *mtx, uint32_t timeout_us); - -/*! \brief Wait for recursive mutex with timeout - * \ingroup mutex - * - * Wait for up to the specific time to take ownership of the recursive mutex. If the caller - * already has ownership of the mutex or can be granted ownership of the mutex before the timeout expires, - * then true will be returned and the caller will own the mutex, otherwise false will be returned and the caller - * will NOT own the mutex. - * - * \param mtx Pointer to mutex structure - * \param timeout_us The timeout in microseconds. - * \return true if the recursive mutex (now) owned, false if timeout occurred before ownership could be granted - */ -bool recursive_mutex_enter_timeout_us(recursive_mutex_t *mtx, uint32_t timeout_us); - -/*! \brief Wait for mutex until a specific time - * \ingroup mutex - * - * Wait until the specific time to take ownership of the mutex. If the caller - * can be granted ownership of the mutex before the timeout expires, then true will be returned - * and the caller will own the mutex, otherwise false will be returned and the caller - * will NOT own the mutex. - * - * \param mtx Pointer to mutex structure - * \param until The time after which to return if the caller cannot be granted ownership of the mutex - * \return true if mutex now owned, false if timeout occurred before ownership could be granted - */ -bool mutex_enter_block_until(mutex_t *mtx, absolute_time_t until); - -/*! \brief Wait for mutex until a specific time - * \ingroup mutex - * - * Wait until the specific time to take ownership of the mutex. If the caller - * already has ownership of the mutex or can be granted ownership of the mutex before the timeout expires, - * then true will be returned and the caller will own the mutex, otherwise false will be returned and the caller - * will NOT own the mutex. - * - * \param mtx Pointer to recursive mutex structure - * \param until The time after which to return if the caller cannot be granted ownership of the mutex - * \return true if the recursive mutex (now) owned, false if timeout occurred before ownership could be granted - */ -bool recursive_mutex_enter_block_until(recursive_mutex_t *mtx, absolute_time_t until); - -/*! \brief Release ownership of a mutex - * \ingroup mutex - * - * \param mtx Pointer to mutex structure - */ -void mutex_exit(mutex_t *mtx); - -/*! \brief Release ownership of a recursive mutex - * \ingroup mutex - * - * \param mtx Pointer to recursive mutex structure - */ -void recursive_mutex_exit(recursive_mutex_t *mtx); - -/*! \brief Test for mutex initialized state - * \ingroup mutex - * - * \param mtx Pointer to mutex structure - * \return true if the mutex is initialized, false otherwise - */ -static inline bool mutex_is_initialized(mutex_t *mtx) { - return mtx->core.spin_lock != 0; -} - -/*! \brief Test for recursive mutex initialized state - * \ingroup mutex - * - * \param mtx Pointer to recursive mutex structure - * \return true if the recursive mutex is initialized, false otherwise - */ -static inline bool recursive_mutex_is_initialized(recursive_mutex_t *mtx) { - return mtx->core.spin_lock != 0; -} - -/*! \brief Helper macro for static definition of mutexes - * \ingroup mutex - * - * A mutex defined as follows: - * - * ```c - * auto_init_mutex(my_mutex); - * ``` - * - * Is equivalent to doing - * - * ```c - * static mutex_t my_mutex; - * - * void my_init_function() { - * mutex_init(&my_mutex); - * } - * ``` - * - * But the initialization of the mutex is performed automatically during runtime initialization - */ -#define auto_init_mutex(name) static __attribute__((section(".mutex_array"))) mutex_t name - -/*! \brief Helper macro for static definition of recursive mutexes - * \ingroup mutex - * - * A recursive mutex defined as follows: - * - * ```c - * auto_init_recursive_mutex(my_recursive_mutex); - * ``` - * - * Is equivalent to doing - * - * ```c - * static recursive_mutex_t my_recursive_mutex; - * - * void my_init_function() { - * recursive_mutex_init(&my_recursive_mutex); - * } - * ``` - * - * But the initialization of the mutex is performed automatically during runtime initialization - */ -#define auto_init_recursive_mutex(name) static __attribute__((section(".mutex_array"))) recursive_mutex_t name = { .core = { .spin_lock = (spin_lock_t *)1 /* marker for runtime_init */ }, .owner = 0, .enter_count = 0 } - -void runtime_init_mutex(void); - -#ifdef __cplusplus -} -#endif -#endif diff --git a/lib/main/pico-sdk/common/pico_sync/include/pico/sem.h b/lib/main/pico-sdk/common/pico_sync/include/pico/sem.h deleted file mode 100644 index 832f1499bb..0000000000 --- a/lib/main/pico-sdk/common/pico_sync/include/pico/sem.h +++ /dev/null @@ -1,139 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _PICO_SEM_H -#define _PICO_SEM_H - -#include "pico/lock_core.h" - -/** \file sem.h - * \defgroup sem sem - * \ingroup pico_sync - * \brief Semaphore API for restricting access to a resource - * - * A semaphore holds a number of available permits. `sem_acquire` methods will acquire a permit if available - * (reducing the available count by 1) or block if the number of available permits is 0. - * \ref sem_release() increases the number of available permits by one potentially unblocking a `sem_acquire` method. - * - * Note that \ref sem_release() may be called an arbitrary number of times, however the number of available - * permits is capped to the max_permit value specified during semaphore initialization. - * - * Although these semaphore related functions can be used from IRQ handlers, it is obviously preferable to only - * release semaphores from within an IRQ handler (i.e. avoid blocking) - */ - -#ifdef __cplusplus -extern "C" { -#endif -typedef struct semaphore { - struct lock_core core; - int16_t permits; - int16_t max_permits; -} semaphore_t; - - -/*! \brief Initialise a semaphore structure - * \ingroup sem - * - * \param sem Pointer to semaphore structure - * \param initial_permits How many permits are initially acquired - * \param max_permits Total number of permits allowed for this semaphore - */ -void sem_init(semaphore_t *sem, int16_t initial_permits, int16_t max_permits); - -/*! \brief Return number of available permits on the semaphore - * \ingroup sem - * - * \param sem Pointer to semaphore structure - * \return The number of permits available on the semaphore. - */ -int sem_available(semaphore_t *sem); - -/*! \brief Release a permit on a semaphore - * \ingroup sem - * - * Increases the number of permits by one (unless the number of permits is already at the maximum). - * A blocked `sem_acquire` will be released if the number of permits is increased. - * - * \param sem Pointer to semaphore structure - * \return true if the number of permits available was increased. - */ -bool sem_release(semaphore_t *sem); - -/*! \brief Reset semaphore to a specific number of available permits - * \ingroup sem - * - * Reset value should be from 0 to the max_permits specified in the init function - * - * \param sem Pointer to semaphore structure - * \param permits the new number of available permits - */ -void sem_reset(semaphore_t *sem, int16_t permits); - -/*! \brief Acquire a permit from the semaphore - * \ingroup sem - * - * This function will block and wait if no permits are available. - * - * \param sem Pointer to semaphore structure - */ -void sem_acquire_blocking(semaphore_t *sem); - -/*! \brief Acquire a permit from a semaphore, with timeout - * \ingroup sem - * - * This function will block and wait if no permits are available, until the - * defined timeout has been reached. If the timeout is reached the function will - * return false, otherwise it will return true. - * - * \param sem Pointer to semaphore structure - * \param timeout_ms Time to wait to acquire the semaphore, in milliseconds. - * \return false if timeout reached, true if permit was acquired. - */ -bool sem_acquire_timeout_ms(semaphore_t *sem, uint32_t timeout_ms); - -/*! \brief Acquire a permit from a semaphore, with timeout - * \ingroup sem - * - * This function will block and wait if no permits are available, until the - * defined timeout has been reached. If the timeout is reached the function will - * return false, otherwise it will return true. - * - * \param sem Pointer to semaphore structure - * \param timeout_us Time to wait to acquire the semaphore, in microseconds. - * \return false if timeout reached, true if permit was acquired. - */ -bool sem_acquire_timeout_us(semaphore_t *sem, uint32_t timeout_us); - -/*! \brief Wait to acquire a permit from a semaphore until a specific time - * \ingroup sem - * - * This function will block and wait if no permits are available, until the - * specified timeout time. If the timeout is reached the function will - * return false, otherwise it will return true. - * - * \param sem Pointer to semaphore structure - * \param until The time after which to return if the sem is not available. - * \return true if permit was acquired, false if the until time was reached before - * acquiring. - */ -bool sem_acquire_block_until(semaphore_t *sem, absolute_time_t until); - -/*! \brief Attempt to acquire a permit from a semaphore without blocking - * \ingroup sem - * - * This function will return false without blocking if no permits are - * available, otherwise it will acquire a permit and return true. - * - * \param sem Pointer to semaphore structure - * \return true if permit was acquired. - */ -bool sem_try_acquire(semaphore_t *sem); - -#ifdef __cplusplus -} -#endif -#endif diff --git a/lib/main/pico-sdk/common/pico_sync/include/pico/sync.h b/lib/main/pico-sdk/common/pico_sync/include/pico/sync.h deleted file mode 100644 index 3ee97bbcb2..0000000000 --- a/lib/main/pico-sdk/common/pico_sync/include/pico/sync.h +++ /dev/null @@ -1,19 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _PICO_SYNC_H -#define _PICO_SYNC_H - -/** \file pico/sync.h - * \defgroup pico_sync pico_sync - * \brief Synchronization primitives and mutual exclusion - */ - -#include "pico/sem.h" -#include "pico/mutex.h" -#include "pico/critical_section.h" - -#endif diff --git a/lib/main/pico-sdk/common/pico_sync/lock_core.c b/lib/main/pico-sdk/common/pico_sync/lock_core.c deleted file mode 100644 index 1bc8df9d56..0000000000 --- a/lib/main/pico-sdk/common/pico_sync/lock_core.c +++ /dev/null @@ -1,13 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "pico/lock_core.h" - -void lock_init(lock_core_t *core, uint lock_num) { - valid_params_if(LOCK_CORE, lock_num < NUM_SPIN_LOCKS); - core->spin_lock = spin_lock_instance(lock_num); -} - diff --git a/lib/main/pico-sdk/common/pico_sync/mutex.c b/lib/main/pico-sdk/common/pico_sync/mutex.c deleted file mode 100644 index 66e947687a..0000000000 --- a/lib/main/pico-sdk/common/pico_sync/mutex.c +++ /dev/null @@ -1,228 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "pico/mutex.h" -#include "pico/time.h" -#include "pico/runtime_init.h" - -#if !PICO_RUNTIME_NO_INIT_MUTEX -void __weak runtime_init_mutex(void) { - // this is an array of either mutex_t or recursive_mutex_t (i.e. not necessarily the same size) - // however each starts with a lock_core_t, and the spin_lock is initialized to address 1 for a recursive - // spinlock and 0 for a regular one. - - static_assert(!(sizeof(mutex_t)&3), ""); - static_assert(!(sizeof(recursive_mutex_t)&3), ""); - static_assert(!offsetof(mutex_t, core), ""); - static_assert(!offsetof(recursive_mutex_t, core), ""); - extern lock_core_t __mutex_array_start; - extern lock_core_t __mutex_array_end; - - for (lock_core_t *l = &__mutex_array_start; l < &__mutex_array_end; ) { - if (l->spin_lock) { - assert(1 == (uintptr_t)l->spin_lock); // indicator for a recursive mutex - recursive_mutex_t *rm = (recursive_mutex_t *)l; - recursive_mutex_init(rm); - l = &rm[1].core; // next - } else { - mutex_t *m = (mutex_t *)l; - mutex_init(m); - l = &m[1].core; // next - } - } -} -#endif - -#if defined(PICO_RUNTIME_INIT_MUTEX) && !PICO_RUNTIME_SKIP_INIT_MUTEX -PICO_RUNTIME_INIT_FUNC_RUNTIME(runtime_init_mutex, PICO_RUNTIME_INIT_MUTEX); -#endif - -void mutex_init(mutex_t *mtx) { - lock_init(&mtx->core, next_striped_spin_lock_num()); - mtx->owner = LOCK_INVALID_OWNER_ID; -#if PICO_MUTEX_ENABLE_SDK120_COMPATIBILITY - mtx->recursive = false; -#endif - __mem_fence_release(); -} - -void recursive_mutex_init(recursive_mutex_t *mtx) { - lock_init(&mtx->core, next_striped_spin_lock_num()); - mtx->owner = LOCK_INVALID_OWNER_ID; - mtx->enter_count = 0; -#if PICO_MUTEX_ENABLE_SDK120_COMPATIBILITY - mtx->recursive = true; -#endif - __mem_fence_release(); -} - -void __time_critical_func(mutex_enter_blocking)(mutex_t *mtx) { -#if PICO_MUTEX_ENABLE_SDK120_COMPATIBILITY - if (mtx->recursive) { - recursive_mutex_enter_blocking(mtx); - return; - } -#endif - lock_owner_id_t caller = lock_get_caller_owner_id(); - do { - uint32_t save = spin_lock_blocking(mtx->core.spin_lock); - if (!lock_is_owner_id_valid(mtx->owner)) { - mtx->owner = caller; - spin_unlock(mtx->core.spin_lock, save); - break; - } - lock_internal_spin_unlock_with_wait(&mtx->core, save); - } while (true); -} - -void __time_critical_func(recursive_mutex_enter_blocking)(recursive_mutex_t *mtx) { - lock_owner_id_t caller = lock_get_caller_owner_id(); - do { - uint32_t save = spin_lock_blocking(mtx->core.spin_lock); - if (mtx->owner == caller || !lock_is_owner_id_valid(mtx->owner)) { - mtx->owner = caller; - uint __unused total = ++mtx->enter_count; - spin_unlock(mtx->core.spin_lock, save); - assert(total); // check for overflow - return; - } else { - lock_internal_spin_unlock_with_wait(&mtx->core, save); - } - } while (true); -} - -bool __time_critical_func(mutex_try_enter)(mutex_t *mtx, uint32_t *owner_out) { -#if PICO_MUTEX_ENABLE_SDK120_COMPATIBILITY - if (mtx->recursive) { - return recursive_mutex_try_enter(mtx, owner_out); - } -#endif - bool entered; - uint32_t save = spin_lock_blocking(mtx->core.spin_lock); - if (!lock_is_owner_id_valid(mtx->owner)) { - mtx->owner = lock_get_caller_owner_id(); - entered = true; - } else { - if (owner_out) *owner_out = (uint32_t) mtx->owner; - entered = false; - } - spin_unlock(mtx->core.spin_lock, save); - return entered; -} - -bool __time_critical_func(mutex_try_enter_block_until)(mutex_t *mtx, absolute_time_t until) { - // not using lock_owner_id_t to avoid backwards incompatibility change to mutex_try_enter API - static_assert(sizeof(lock_owner_id_t) <= 4, ""); - uint32_t owner; - if (!mutex_try_enter(mtx, &owner)) { - if ((lock_owner_id_t)owner == lock_get_caller_owner_id()) return false; // deadlock, so we can never own it - return mutex_enter_block_until(mtx, until); - } - return true; -} - -bool __time_critical_func(recursive_mutex_try_enter)(recursive_mutex_t *mtx, uint32_t *owner_out) { - bool entered; - lock_owner_id_t caller = lock_get_caller_owner_id(); - uint32_t save = spin_lock_blocking(mtx->core.spin_lock); - if (!lock_is_owner_id_valid(mtx->owner) || mtx->owner == caller) { - mtx->owner = caller; - uint __unused total = ++mtx->enter_count; - assert(total); // check for overflow - entered = true; - } else { - if (owner_out) *owner_out = (uint32_t) mtx->owner; - entered = false; - } - spin_unlock(mtx->core.spin_lock, save); - return entered; -} - -bool __time_critical_func(mutex_enter_timeout_ms)(mutex_t *mtx, uint32_t timeout_ms) { - return mutex_enter_block_until(mtx, make_timeout_time_ms(timeout_ms)); -} - -bool __time_critical_func(recursive_mutex_enter_timeout_ms)(recursive_mutex_t *mtx, uint32_t timeout_ms) { - return recursive_mutex_enter_block_until(mtx, make_timeout_time_ms(timeout_ms)); -} - -bool __time_critical_func(mutex_enter_timeout_us)(mutex_t *mtx, uint32_t timeout_us) { - return mutex_enter_block_until(mtx, make_timeout_time_us(timeout_us)); -} - -bool __time_critical_func(recursive_mutex_enter_timeout_us)(recursive_mutex_t *mtx, uint32_t timeout_us) { - return recursive_mutex_enter_block_until(mtx, make_timeout_time_us(timeout_us)); -} - -bool __time_critical_func(mutex_enter_block_until)(mutex_t *mtx, absolute_time_t until) { -#if PICO_MUTEX_ENABLE_SDK120_COMPATIBILITY - if (mtx->recursive) { - return recursive_mutex_enter_block_until(mtx, until); - } -#endif - assert(mtx->core.spin_lock); - lock_owner_id_t caller = lock_get_caller_owner_id(); - do { - uint32_t save = spin_lock_blocking(mtx->core.spin_lock); - if (!lock_is_owner_id_valid(mtx->owner)) { - mtx->owner = caller; - spin_unlock(mtx->core.spin_lock, save); - return true; - } else { - if (lock_internal_spin_unlock_with_best_effort_wait_or_timeout(&mtx->core, save, until)) { - // timed out - return false; - } - // not timed out; spin lock already unlocked, so loop again - } - } while (true); -} - -bool __time_critical_func(recursive_mutex_enter_block_until)(recursive_mutex_t *mtx, absolute_time_t until) { - assert(mtx->core.spin_lock); - lock_owner_id_t caller = lock_get_caller_owner_id(); - do { - uint32_t save = spin_lock_blocking(mtx->core.spin_lock); - if (!lock_is_owner_id_valid(mtx->owner) || mtx->owner == caller) { - mtx->owner = caller; - uint __unused total = ++mtx->enter_count; - spin_unlock(mtx->core.spin_lock, save); - assert(total); // check for overflow - return true; - } else { - if (lock_internal_spin_unlock_with_best_effort_wait_or_timeout(&mtx->core, save, until)) { - // timed out - return false; - } - // not timed out; spin lock already unlocked, so loop again - } - } while (true); -} - -void __time_critical_func(mutex_exit)(mutex_t *mtx) { -#if PICO_MUTEX_ENABLE_SDK120_COMPATIBILITY - if (mtx->recursive) { - recursive_mutex_exit(mtx); - return; - } -#endif - uint32_t save = spin_lock_blocking(mtx->core.spin_lock); - assert(lock_is_owner_id_valid(mtx->owner)); - mtx->owner = LOCK_INVALID_OWNER_ID; - lock_internal_spin_unlock_with_notify(&mtx->core, save); -} - -void __time_critical_func(recursive_mutex_exit)(recursive_mutex_t *mtx) { - uint32_t save = spin_lock_blocking(mtx->core.spin_lock); - assert(lock_is_owner_id_valid(mtx->owner)); - assert(mtx->enter_count); - if (!--mtx->enter_count) { - mtx->owner = LOCK_INVALID_OWNER_ID; - lock_internal_spin_unlock_with_notify(&mtx->core, save); - } else { - spin_unlock(mtx->core.spin_lock, save); - } -} \ No newline at end of file diff --git a/lib/main/pico-sdk/common/pico_sync/sem.c b/lib/main/pico-sdk/common/pico_sync/sem.c deleted file mode 100644 index 9044817061..0000000000 --- a/lib/main/pico-sdk/common/pico_sync/sem.c +++ /dev/null @@ -1,95 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "pico/sem.h" -#include "pico/time.h" - -void sem_init(semaphore_t *sem, int16_t initial_permits, int16_t max_permits) { - lock_init(&sem->core, next_striped_spin_lock_num()); - sem->permits = initial_permits; - sem->max_permits = max_permits; - __mem_fence_release(); -} - -int __time_critical_func(sem_available)(semaphore_t *sem) { -#ifdef __GNUC__ - return *(volatile typeof(sem->permits) *) &sem->permits; -#else - static_assert(sizeof(sem->permits) == 2, ""); - return *(volatile int16_t *) &sem->permits; -#endif -} - -void __time_critical_func(sem_acquire_blocking)(semaphore_t *sem) { - do { - uint32_t save = spin_lock_blocking(sem->core.spin_lock); - if (sem->permits > 0) { - sem->permits--; - spin_unlock(sem->core.spin_lock, save); - break; - } - lock_internal_spin_unlock_with_wait(&sem->core, save); - } while (true); -} - -bool __time_critical_func(sem_acquire_timeout_ms)(semaphore_t *sem, uint32_t timeout_ms) { - return sem_acquire_block_until(sem, make_timeout_time_ms(timeout_ms)); -} - -bool __time_critical_func(sem_acquire_timeout_us)(semaphore_t *sem, uint32_t timeout_us) { - return sem_acquire_block_until(sem, make_timeout_time_us(timeout_us)); -} - -bool __time_critical_func(sem_acquire_block_until)(semaphore_t *sem, absolute_time_t until) { - do { - uint32_t save = spin_lock_blocking(sem->core.spin_lock); - if (sem->permits > 0) { - sem->permits--; - spin_unlock(sem->core.spin_lock, save); - return true; - } - if (lock_internal_spin_unlock_with_best_effort_wait_or_timeout(&sem->core, save, until)) { - return false; - } - } while (true); -} - -bool __time_critical_func(sem_try_acquire)(semaphore_t *sem) { - uint32_t save = spin_lock_blocking(sem->core.spin_lock); - if (sem->permits > 0) { - sem->permits--; - spin_unlock(sem->core.spin_lock, save); - return true; - } - spin_unlock(sem->core.spin_lock, save); - return false; -} - -// todo this should really have a blocking variant for when permits are maxed out -bool __time_critical_func(sem_release)(semaphore_t *sem) { - uint32_t save = spin_lock_blocking(sem->core.spin_lock); - int32_t count = sem->permits; - if (count < sem->max_permits) { - sem->permits = (int16_t)(count + 1); - lock_internal_spin_unlock_with_notify(&sem->core, save); - return true; - } else { - spin_unlock(sem->core.spin_lock, save); - return false; - } -} - -void __time_critical_func(sem_reset)(semaphore_t *sem, int16_t permits) { - assert(permits >= 0 && permits <= sem->max_permits); - uint32_t save = spin_lock_blocking(sem->core.spin_lock); - if (permits > sem->permits) { - sem->permits = permits; - lock_internal_spin_unlock_with_notify(&sem->core, save); - } else { - sem->permits = permits; - spin_unlock(sem->core.spin_lock, save); - } -} diff --git a/lib/main/pico-sdk/common/pico_time/include/pico/time.h b/lib/main/pico-sdk/common/pico_time/include/pico/time.h deleted file mode 100644 index 53a606bcb5..0000000000 --- a/lib/main/pico-sdk/common/pico_time/include/pico/time.h +++ /dev/null @@ -1,844 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _PICO_TIME_H -#define _PICO_TIME_H - -#include "pico.h" -#include "hardware/timer.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** \file time.h - * \defgroup pico_time pico_time - * - * \brief API for accurate timestamps, sleeping, and time based callbacks - * - * \note The functions defined here provide a much more powerful and user friendly wrapping around the - * low level hardware timer functionality. For these functions (and any other SDK functionality - * e.g. timeouts, that relies on them) to work correctly, the hardware timer should not be modified. i.e. it is expected - * to be monotonically increasing once per microsecond. Fortunately there is no need to modify the hardware - * timer as any functionality you can think of that isn't already covered here can easily be modelled - * by adding or subtracting a constant value from the unmodified hardware timer. - * - * \sa \ref hardware_timer - */ - -// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_PICO_TIME, Enable/disable assertions in the pico_time module, type=bool, default=0, group=pico_time -#ifndef PARAM_ASSERTIONS_ENABLED_PICO_TIME -#ifdef PARAM_ASSERTIONS_ENABLED_PICO_TIME // backwards compatibility with SDK < 2.0.0 -#define PARAM_ASSERTIONS_ENABLED_PICO_TIME PARAM_ASSERTIONS_ENABLED_TIME -#else -#define PARAM_ASSERTIONS_ENABLED_PICO_TIME 0 -#endif -#endif - -// PICO_CONFIG: PICO_TIME_SLEEP_OVERHEAD_ADJUST_US, How many microseconds to wake up early (and then busy_wait) to account for timer overhead when sleeping in low power mode, type=int, default=6, group=pico_time -#ifndef PICO_TIME_SLEEP_OVERHEAD_ADJUST_US -#define PICO_TIME_SLEEP_OVERHEAD_ADJUST_US 6 -#endif - -/*! - * \defgroup timestamp timestamp - * \ingroup pico_time - * \brief Timestamp functions relating to points in time (including the current time). - * - * These are functions for dealing with timestamps (i.e. instants in time) represented by the type absolute_time_t. This opaque - * type is provided to help prevent accidental mixing of timestamps and relative time values. - */ - -/*! \brief Return a representation of the current time. - * \ingroup timestamp - * - * Returns an opaque high fidelity representation of the current time sampled during the call. - * - * \return the absolute time (now) of the hardware timer - * - * \sa absolute_time_t - * \sa sleep_until() - * \sa time_us_64() - */ -static inline absolute_time_t get_absolute_time(void) { - absolute_time_t t; - update_us_since_boot(&t, time_us_64()); - return t; -} - -static inline uint32_t us_to_ms(uint64_t us) { - if (us >> 32u) { - return (uint32_t)(us / 1000u); - } else { - return ((uint32_t)us) / 1000u; - } -} - -/*! fn to_ms_since_boot - * \ingroup timestamp - * \brief Convert a timestamp into a number of milliseconds since boot. - * \param t an absolute_time_t value to convert - * \return the number of milliseconds since boot represented by t - * \sa to_us_since_boot() - */ -static inline uint32_t to_ms_since_boot(absolute_time_t t) { - uint64_t us = to_us_since_boot(t); - return us_to_ms(us); -} - -/*! \brief Return a timestamp value obtained by adding a number of microseconds to another timestamp - * \ingroup timestamp - * - * \param t the base timestamp - * \param us the number of microseconds to add - * \return the timestamp representing the resulting time - */ -static inline absolute_time_t delayed_by_us(const absolute_time_t t, uint64_t us) { - absolute_time_t t2; - uint64_t base = to_us_since_boot(t); - uint64_t delayed = base + us; - if ((int64_t)delayed < 0) { - // absolute_time_t (to allow for signed time deltas) is never greater than INT64_MAX which == at_the_end_of_time - delayed = INT64_MAX; - } - update_us_since_boot(&t2, delayed); - return t2; -} - -/*! \brief Return a timestamp value obtained by adding a number of milliseconds to another timestamp - * \ingroup timestamp - * - * \param t the base timestamp - * \param ms the number of milliseconds to add - * \return the timestamp representing the resulting time - */ -static inline absolute_time_t delayed_by_ms(const absolute_time_t t, uint32_t ms) { - absolute_time_t t2; - uint64_t base = to_us_since_boot(t); - uint64_t delayed = base + ms * 1000ull; - if ((int64_t)delayed < 0) { - // absolute_time_t (to allow for signed time deltas) is never greater than INT64_MAX which == at_the_end_of_time - delayed = INT64_MAX; - } - update_us_since_boot(&t2, delayed); - return t2; -} - -/*! \brief Convenience method to get the timestamp a number of microseconds from the current time - * \ingroup timestamp - * - * \param us the number of microseconds to add to the current timestamp - * \return the future timestamp - */ -static inline absolute_time_t make_timeout_time_us(uint64_t us) { - return delayed_by_us(get_absolute_time(), us); -} - -/*! \brief Convenience method to get the timestamp a number of milliseconds from the current time - * \ingroup timestamp - * - * \param ms the number of milliseconds to add to the current timestamp - * \return the future timestamp - */ -static inline absolute_time_t make_timeout_time_ms(uint32_t ms) { - return delayed_by_ms(get_absolute_time(), ms); -} - -/*! \brief Return the difference in microseconds between two timestamps - * \ingroup timestamp - * - * \note be careful when diffing against large timestamps (e.g. \ref at_the_end_of_time) - * as the signed integer may overflow. - * - * \param from the first timestamp - * \param to the second timestamp - * \return the number of microseconds between the two timestamps (positive if `to` is after `from` except - * in case of overflow) - */ -static inline int64_t absolute_time_diff_us(absolute_time_t from, absolute_time_t to) { - return (int64_t)(to_us_since_boot(to) - to_us_since_boot(from)); -} - -/*! \brief Return the earlier of two timestamps - * \ingroup timestamp - * - * \param a the first timestamp - * \param b the second timestamp - * \return the earlier of the two timestamps - */ -static inline absolute_time_t absolute_time_min(absolute_time_t a, absolute_time_t b) { - return to_us_since_boot(a) < to_us_since_boot(b) ? a : b; -} - -/*! \brief The timestamp representing the end of time; this is actually not the maximum possible - * timestamp, but is set to 0x7fffffff_ffffffff microseconds to avoid sign overflows with time - * arithmetic. This is almost 300,000 years, so should be sufficient. - * \ingroup timestamp - */ -extern const absolute_time_t at_the_end_of_time; - -/*! \brief Determine if the given timestamp is "at_the_end_of_time" - * \ingroup timestamp - * \param t the timestamp - * \return true if the timestamp is at_the_end_of_time - * \sa at_the_end_of_time - */ -static inline bool is_at_the_end_of_time(absolute_time_t t) { - return to_us_since_boot(t) == to_us_since_boot(at_the_end_of_time); -} - -/*! \brief The timestamp representing a null timestamp - * \ingroup timestamp - */ -extern const absolute_time_t nil_time; - -/*! \brief Determine if the given timestamp is nil - * \ingroup timestamp - * \param t the timestamp - * \return true if the timestamp is nil - * \sa nil_time - */ -static inline bool is_nil_time(absolute_time_t t) { - return !to_us_since_boot(t); -} - -/*! - * \defgroup sleep sleep - * \ingroup pico_time - * \brief Sleep functions for delaying execution in a lower power state. - * - * These functions allow the calling core to sleep. This is a lower powered sleep; waking and re-checking time on every processor - * event (WFE) - * - * \note These functions should not be called from an IRQ handler. - * - * \note Lower powered sleep requires use of the \link alarm_pool_get_default default alarm pool\endlink which may - * be disabled by the PICO_TIME_DEFAULT_ALARM_POOL_DISABLED #define or currently full in which case these functions - * become busy waits instead. - * - * \note Whilst \a sleep_ functions are preferable to \a busy_wait functions from a power perspective, the \a busy_wait equivalent function - * may return slightly sooner after the target is reached. - * - * \sa busy_wait_until() \sa busy_wait_us() \sa busy_wait_us_32() - */ - -/*! \brief Wait until after the given timestamp to return - * \ingroup sleep - * - * \note This method attempts to perform a lower power (WFE) sleep - * - * \param target the time after which to return - * \sa sleep_us() - * \sa busy_wait_until() - * */ -void sleep_until(absolute_time_t target); - -/*! \brief Wait for the given number of microseconds before returning - * \ingroup sleep - * - * \note This method attempts to perform a lower power (WFE) sleep - * - * \param us the number of microseconds to sleep - * \sa busy_wait_us() - */ -void sleep_us(uint64_t us); - -/*! \brief Wait for the given number of milliseconds before returning - * \ingroup sleep - * - * \note This method attempts to perform a lower power sleep (using WFE) as much as possible. - * - * \param ms the number of milliseconds to sleep - */ -void sleep_ms(uint32_t ms); - -/*! \brief Helper method for blocking on a timeout - * \ingroup sleep - * - * This method will return in response to an event (as per __wfe) or - * when the target time is reached, or at any point before. - * - * This method can be used to implement a lower power polling loop waiting on - * some condition signalled by an event (__sev()). - * - * This is called \a best_effort because under certain circumstances (notably the default timer pool - * being disabled or full) the best effort is simply to return immediately without a __wfe, thus turning the calling - * code into a busy wait. - * - * Example usage: - * ```c - * bool my_function_with_timeout_us(uint64_t timeout_us) { - * absolute_time_t timeout_time = make_timeout_time_us(timeout_us); - * do { - * // each time round the loop, we check to see if the condition - * // we are waiting on has happened - * if (my_check_done()) { - * // do something - * return true; - * } - * // will try to sleep until timeout or the next processor event - * } while (!best_effort_wfe_or_timeout(timeout_time)); - * return false; // timed out - * } - * ``` - * NOTE: This method should always be used in a loop associated with checking another "event" variable, since - * processor events are a shared resource and can happen for a large number of reasons. - * - * @param timeout_timestamp the timeout time - * @return true if the target time is reached, false otherwise - */ -bool best_effort_wfe_or_timeout(absolute_time_t timeout_timestamp); - -/*! - * \defgroup alarm alarm - * \ingroup pico_time - * \brief Alarm functions for scheduling future execution - * - * Alarms are added to alarm pools, which may hold a certain fixed number of active alarms. Each alarm pool - * utilizes one of four underlying timer_alarms, thus you may have up to four alarm pools. An alarm pool - * calls (except when the callback would happen before or during being set) the callback on the core from which - * the alarm pool was created. Callbacks are called from the timer_alarm IRQ handler, so care must - * be taken in their implementation. - * - * A default pool is created the core specified by PICO_TIME_DEFAULT_ALARM_POOL_HARDWARE_ALARM_NUM - * on core 0, and may be used by the method variants that take no alarm pool parameter. - * - * \sa struct alarm_pool - * \sa hardware_timer - */ - -// PICO_CONFIG: PICO_TIME_DEFAULT_ALARM_POOL_DISABLED, Disable the default alarm pool, type=bool, default=0, advanced=true, group=pico_time -#ifndef PICO_TIME_DEFAULT_ALARM_POOL_DISABLED -/*! - * \brief If 1 then the default alarm pool is disabled (so no timer_alarm is claimed for the pool) - * - * \note Setting to 1 may cause some code not to compile as default timer pool related methods are removed - * - * \note When the default alarm pool is disabled, \a sleep_ methods and timeouts are no longer lower powered - * (they become \a busy_wait_) - * - * \ingroup alarm - * \sa #PICO_TIME_DEFAULT_ALARM_POOL_HARDWARE_ALARM_NUM - * \sa alarm_pool_get_default() - */ -#define PICO_TIME_DEFAULT_ALARM_POOL_DISABLED 0 -#endif - -// PICO_CONFIG: PICO_TIME_DEFAULT_ALARM_POOL_HARDWARE_ALARM_NUM, Select which HW alarm is used for the default alarm pool, min=0, max=3, default=3, advanced=true, group=pico_time -#ifndef PICO_TIME_DEFAULT_ALARM_POOL_HARDWARE_ALARM_NUM -/*! - * \brief Selects which timer_alarm is used for the default alarm pool - * \ingroup alarm - * \sa alarm_pool_get_default() - */ -#define PICO_TIME_DEFAULT_ALARM_POOL_HARDWARE_ALARM_NUM 3 -#endif - -// PICO_CONFIG: PICO_TIME_DEFAULT_ALARM_POOL_MAX_TIMERS, Selects the maximum number of concurrent timers in the default alarm pool, min=0, max=255, default=16, advanced=true, group=pico_time -#ifndef PICO_TIME_DEFAULT_ALARM_POOL_MAX_TIMERS -/*! - * \brief Selects the maximum number of concurrent timers in the default alarm pool - * \ingroup alarm - * - * \note For implementation reasons this is limited to PICO_PHEAP_MAX_ENTRIES which defaults to 255 - * \sa #PICO_TIME_DEFAULT_ALARM_POOL_HARDWARE_ALARM_NUM - * \sa alarm_pool_get_default() - */ -#define PICO_TIME_DEFAULT_ALARM_POOL_MAX_TIMERS 16 -#endif - -/** - * \brief The identifier for an alarm - * - * \note this identifier is signed because <0 is used as an error condition when creating alarms - * - * \note alarm ids may be reused, however for convenience the implementation makes an attempt to defer - * reusing as long as possible. You should certainly expect it to be hundreds of ids before one is - * reused, although in most cases it is more. Nonetheless care must still be taken when cancelling - * alarms or other functionality based on alarms when the alarm may have expired, as eventually - * the alarm id may be reused for another alarm. - * - * \see pico_error_codes - * \ingroup alarm - */ -typedef int32_t alarm_id_t; // note this is signed because we use <0 as a meaningful error value - -/** - * \brief User alarm callback - * \ingroup alarm - * \param id the alarm_id as returned when the alarm was added - * \param user_data the user data passed when the alarm was added - * \return <0 to reschedule the same alarm this many us from the time the alarm was previously scheduled to fire - * \return >0 to reschedule the same alarm this many us from the time this method returns - * \return 0 to not reschedule the alarm - */ -typedef int64_t (*alarm_callback_t)(alarm_id_t id, void *user_data); - -typedef struct alarm_pool alarm_pool_t; -typedef void alarm_pool_timer_t; - -/** - * \brief Create the default alarm pool (if not already created or disabled) - * \ingroup alarm - */ -void alarm_pool_init_default(void); -void runtime_init_default_alarm_pool(void); - -#if !PICO_TIME_DEFAULT_ALARM_POOL_DISABLED -/*! - * \brief The default alarm pool used when alarms are added without specifying an alarm pool, - * and also used by the SDK to support lower power sleeps and timeouts. - * - * \ingroup alarm - * \sa #PICO_TIME_DEFAULT_ALARM_POOL_HARDWARE_ALARM_NUM - */ -alarm_pool_t *alarm_pool_get_default(void); -#endif - -alarm_pool_t *alarm_pool_create_on_timer(alarm_pool_timer_t *timer, uint timer_alarm_num, uint max_timers); - -alarm_pool_timer_t *alarm_pool_timer_for_timer_num(uint timer_num); - -alarm_pool_timer_t *alarm_pool_get_default_timer(void); - -/** - * \brief Create an alarm pool - * - * The alarm pool will call callbacks from an alarm IRQ Handler on the core of this function is called from. - * - * In many situations there is never any need for anything other than the default alarm pool, however you - * might want to create another if you want alarm callbacks on core 1 or require alarm pools of - * different priority (IRQ priority based preemption of callbacks) - * - * \note This method will hard assert if the timer_alarm is already claimed. - * - * \ingroup alarm - * \param timer_alarm_num the timer_alarm to use to back this pool - * \param max_timers the maximum number of timers - * \note For implementation reasons this is limited to PICO_PHEAP_MAX_ENTRIES which defaults to 255 - * \sa alarm_pool_get_default() - * \sa hardware_claiming - */ -static inline alarm_pool_t *alarm_pool_create(uint timer_alarm_num, uint max_timers) { - return alarm_pool_create_on_timer(alarm_pool_get_default_timer(), timer_alarm_num, max_timers); -} - -alarm_pool_t *alarm_pool_create_on_timer_with_unused_hardware_alarm(alarm_pool_timer_t *timer, uint max_timers); - -/** - * \brief Create an alarm pool, claiming an used timer_alarm to back it. - * - * The alarm pool will call callbacks from an alarm IRQ Handler on the core of this function is called from. - * - * In many situations there is never any need for anything other than the default alarm pool, however you - * might want to create another if you want alarm callbacks on core 1 or require alarm pools of - * different priority (IRQ priority based preemption of callbacks) - * - * \note This method will hard assert if the there is no free hardware to claim. - * - * \ingroup alarm - * \param max_timers the maximum number of timers - * \note For implementation reasons this is limited to PICO_PHEAP_MAX_ENTRIES which defaults to 255 - * \sa alarm_pool_get_default() - * \sa hardware_claiming - */ -static inline alarm_pool_t *alarm_pool_create_with_unused_hardware_alarm(uint max_timers) { - return alarm_pool_create_on_timer_with_unused_hardware_alarm(alarm_pool_get_default_timer(), max_timers); -} - -/** - * \brief Return the timer alarm used by an alarm pool - * \ingroup alarm - * \param pool the pool - * \return the timer_alarm used by the pool - */ -uint alarm_pool_timer_alarm_num(alarm_pool_t *pool); -// backwards compatibility -static inline uint alarm_pool_hardware_alarm_num(alarm_pool_t *pool) { - return alarm_pool_timer_alarm_num(pool); -} -/** - * \brief Return the core number the alarm pool was initialized on (and hence callbacks are called on) - * \ingroup alarm - * \param pool the pool - * \return the core used by the pool - */ -uint alarm_pool_core_num(alarm_pool_t *pool); - -/** - * \brief Destroy the alarm pool, cancelling all alarms and freeing up the underlying timer_alarm - * \ingroup alarm - * \param pool the pool - */ -void alarm_pool_destroy(alarm_pool_t *pool); - -/*! - * \brief Add an alarm callback to be called at a specific time - * \ingroup alarm - * - * Generally the callback is called as soon as possible after the time specified from an IRQ handler - * on the core the alarm pool was created on. If the callback is in the past or happens before - * the alarm setup could be completed, then this method will optionally call the callback itself - * and then return a return code to indicate that the target time has passed. - * - * \note It is safe to call this method from an IRQ handler (including alarm callbacks), and from either core. - * - * @param pool the alarm pool to use for scheduling the callback (this determines which timer_alarm is used, and which core calls the callback) - * @param time the timestamp when (after which) the callback should fire - * @param callback the callback function - * @param user_data user data to pass to the callback function - * @param fire_if_past if true, and the alarm time falls before or during this call before the alarm can be set, - * then the callback should be called during (by) this function instead - * @return >0 the alarm id for an active (at the time of return) alarm - * @return 0 if the alarm time passed before or during the call and fire_if_past was false - * @return <0 if there were no alarm slots available, or other error occurred - */ -alarm_id_t alarm_pool_add_alarm_at(alarm_pool_t *pool, absolute_time_t time, alarm_callback_t callback, void *user_data, bool fire_if_past); - -/*! - * \brief Add an alarm callback to be called at or after a specific time - * \ingroup alarm - * - * The callback is called as soon as possible after the time specified from an IRQ handler - * on the core the alarm pool was created on. Unlike \ref alarm_pool_add_alarm_at, this method - * guarantees to call the callback from that core even if the time is during this method call or in the past. - * - * \note It is safe to call this method from an IRQ handler (including alarm callbacks), and from either core. - * - * @param pool the alarm pool to use for scheduling the callback (this determines which timer_alarm is used, and which core calls the callback) - * @param time the timestamp when (after which) the callback should fire - * @param callback the callback function - * @param user_data user data to pass to the callback function - * @return >0 the alarm id for an active (at the time of return) alarm - * @return <0 if there were no alarm slots available, or other error occurred - */ -alarm_id_t alarm_pool_add_alarm_at_force_in_context(alarm_pool_t *pool, absolute_time_t time, alarm_callback_t callback, - void *user_data); -/*! - * \brief Add an alarm callback to be called after a delay specified in microseconds - * \ingroup alarm - * - * Generally the callback is called as soon as possible after the time specified from an IRQ handler - * on the core the alarm pool was created on. If the callback is in the past or happens before - * the alarm setup could be completed, then this method will optionally call the callback itself - * and then return a return code to indicate that the target time has passed. - * - * \note It is safe to call this method from an IRQ handler (including alarm callbacks), and from either core. - * - * @param pool the alarm pool to use for scheduling the callback (this determines which timer_alarm is used, and which core calls the callback) - * @param us the delay (from now) in microseconds when (after which) the callback should fire - * @param callback the callback function - * @param user_data user data to pass to the callback function - * @param fire_if_past if true, and the alarm time falls during this call before the alarm can be set, - * then the callback should be called during (by) this function instead - * @return >0 the alarm id - * @return 0 if the alarm time passed before or during the call and fire_if_past was false - * @return <0 if there were no alarm slots available, or other error occurred - */ -static inline alarm_id_t alarm_pool_add_alarm_in_us(alarm_pool_t *pool, uint64_t us, alarm_callback_t callback, void *user_data, bool fire_if_past) { - return alarm_pool_add_alarm_at(pool, delayed_by_us(get_absolute_time(), us), callback, user_data, fire_if_past); -} - -/*! - * \brief Add an alarm callback to be called after a delay specified in milliseconds - * \ingroup alarm - * - * Generally the callback is called as soon as possible after the time specified from an IRQ handler - * on the core the alarm pool was created on. If the callback is in the past or happens before - * the alarm setup could be completed, then this method will optionally call the callback itself - * and then return a return code to indicate that the target time has passed. - * - * \note It is safe to call this method from an IRQ handler (including alarm callbacks), and from either core. - * - * @param pool the alarm pool to use for scheduling the callback (this determines which timer_alarm is used, and which core calls the callback) - * @param ms the delay (from now) in milliseconds when (after which) the callback should fire - * @param callback the callback function - * @param user_data user data to pass to the callback function - * @param fire_if_past if true, and the alarm time falls before or during this call before the alarm can be set, - * then the callback should be called during (by) this function instead - * @return >0 the alarm id - * @return 0 if the alarm time passed before or during the call and fire_if_past was false - * @return <0 if there were no alarm slots available, or other error occurred - */ -static inline alarm_id_t alarm_pool_add_alarm_in_ms(alarm_pool_t *pool, uint32_t ms, alarm_callback_t callback, void *user_data, bool fire_if_past) { - return alarm_pool_add_alarm_at(pool, delayed_by_ms(get_absolute_time(), ms), callback, user_data, fire_if_past); -} - -/*! - * \brief Return the time remaining before the next trigger of an alarm - * \ingroup alarm - * - * @param pool the alarm_pool containing the alarm - * @param alarm_id the alarm - * - * @return >=0 the number of microseconds before the next trigger - * @return <0 if either the given alarm is not in progress or it has passed - */ -int64_t alarm_pool_remaining_alarm_time_us(alarm_pool_t *pool, alarm_id_t alarm_id); - -/*! - * \brief Return the time remaining before the next trigger of an alarm - * \ingroup alarm - * - * @param pool the alarm_pool containing the alarm - * @param alarm_id the alarm - * - * @return >=0 the number of milliseconds before the next trigger (INT32_MAX if the number of ms is higher than can be represented0 - * @return <0 if either the given alarm is not in progress or it has passed - */ -int32_t alarm_pool_remaining_alarm_time_ms(alarm_pool_t *pool, alarm_id_t alarm_id); - -/*! - * \brief Cancel an alarm - * \ingroup alarm - * \param pool the alarm_pool containing the alarm - * \param alarm_id the alarm - * \return true if the alarm was cancelled, false if it didn't exist - * \sa alarm_id_t for a note on reuse of IDs - */ -bool alarm_pool_cancel_alarm(alarm_pool_t *pool, alarm_id_t alarm_id); - -#if !PICO_TIME_DEFAULT_ALARM_POOL_DISABLED -/*! - * \brief Add an alarm callback to be called at a specific time - * \ingroup alarm - * - * Generally the callback is called as soon as possible after the time specified from an IRQ handler - * on the core of the default alarm pool (generally core 0). If the callback is in the past or happens before - * the alarm setup could be completed, then this method will optionally call the callback itself - * and then return a return code to indicate that the target time has passed. - * - * \note It is safe to call this method from an IRQ handler (including alarm callbacks), and from either core. - * - * @param time the timestamp when (after which) the callback should fire - * @param callback the callback function - * @param user_data user data to pass to the callback function - * @param fire_if_past if true, and the alarm time falls before or during this call before the alarm can be set, - * then the callback should be called during (by) this function instead - * @return >0 the alarm id - * @return 0 if the alarm time passed before or during the call and fire_if_past was false - * @return <0 if there were no alarm slots available, or other error occurred - */ -static inline alarm_id_t add_alarm_at(absolute_time_t time, alarm_callback_t callback, void *user_data, bool fire_if_past) { - return alarm_pool_add_alarm_at(alarm_pool_get_default(), time, callback, user_data, fire_if_past); -} - -/*! - * \brief Add an alarm callback to be called after a delay specified in microseconds - * \ingroup alarm - * - * Generally the callback is called as soon as possible after the time specified from an IRQ handler - * on the core of the default alarm pool (generally core 0). If the callback is in the past or happens before - * the alarm setup could be completed, then this method will optionally call the callback itself - * and then return a return code to indicate that the target time has passed. - * - * \note It is safe to call this method from an IRQ handler (including alarm callbacks), and from either core. - * - * @param us the delay (from now) in microseconds when (after which) the callback should fire - * @param callback the callback function - * @param user_data user data to pass to the callback function - * @param fire_if_past if true, and the alarm time falls during this call before the alarm can be set, - * then the callback should be called during (by) this function instead - * @return >0 the alarm id - * @return 0 if the alarm time passed before or during the call and fire_if_past was false - * @return <0 if there were no alarm slots available, or other error occurred - */ -static inline alarm_id_t add_alarm_in_us(uint64_t us, alarm_callback_t callback, void *user_data, bool fire_if_past) { - return alarm_pool_add_alarm_in_us(alarm_pool_get_default(), us, callback, user_data, fire_if_past); -} - -/*! - * \brief Add an alarm callback to be called after a delay specified in milliseconds - * \ingroup alarm - * - * Generally the callback is called as soon as possible after the time specified from an IRQ handler - * on the core of the default alarm pool (generally core 0). If the callback is in the past or happens before - * the alarm setup could be completed, then this method will optionally call the callback itself - * and then return a return code to indicate that the target time has passed. - * - * \note It is safe to call this method from an IRQ handler (including alarm callbacks), and from either core. - * - * @param ms the delay (from now) in milliseconds when (after which) the callback should fire - * @param callback the callback function - * @param user_data user data to pass to the callback function - * @param fire_if_past if true, and the alarm time falls during this call before the alarm can be set, - * then the callback should be called during (by) this function instead - * @return >0 the alarm id - * @return 0 if the alarm time passed before or during the call and fire_if_past was false - * @return <0 if there were no alarm slots available, or other error occurred - */ -static inline alarm_id_t add_alarm_in_ms(uint32_t ms, alarm_callback_t callback, void *user_data, bool fire_if_past) { - return alarm_pool_add_alarm_in_ms(alarm_pool_get_default(), ms, callback, user_data, fire_if_past); -} -/*! - * \brief Cancel an alarm from the default alarm pool - * \ingroup alarm - * \param alarm_id the alarm - * \return true if the alarm was cancelled, false if it didn't exist - * \sa alarm_id_t for a note on reuse of IDs - */ -static inline bool cancel_alarm(alarm_id_t alarm_id) { - return alarm_pool_cancel_alarm(alarm_pool_get_default(), alarm_id); -} - -/*! - * \brief Return the time remaining before the next trigger of an alarm - * \ingroup alarm - * - * @param pool the alarm_pool containing the alarm - * @param alarm_id the alarm - * - * @return >=0 the number of microseconds before the next trigger - * @return <0 if either the given alarm is not in progress or it has passed - */ -int64_t remaining_alarm_time_us(alarm_id_t alarm_id); - -/*! - * \brief Return the time remaining before the next trigger of an alarm - * \ingroup alarm - * - * @param alarm_id the alarm - * - * @return >=0 the number of milliseconds before the next trigger (INT32_MAX if the number of ms is higher than can be represented0 - * @return <0 if either the given alarm is not in progress or it has passed - */ -int32_t remaining_alarm_time_ms(alarm_id_t alarm_id); - -#endif - -/*! - * \defgroup repeating_timer repeating_timer - * \ingroup pico_time - * \brief Repeating Timer functions for simple scheduling of repeated execution - * - * \note The regular \a alarm_ functionality can be used to make repeating alarms (by return non zero from the callback), - * however these methods abstract that further (at the cost of a user structure to store the repeat delay in (which - * the alarm framework does not have space for). - */ - -typedef struct repeating_timer repeating_timer_t; - -/** - * \brief Callback for a repeating timer - * \ingroup repeating_timer - * \param rt repeating time structure containing information about the repeating time. user_data is of primary important to the user - * \return true to continue repeating, false to stop. - */ -typedef bool (*repeating_timer_callback_t)(repeating_timer_t *rt); - -/** - * \brief Information about a repeating timer - * \ingroup repeating_timer - * \return - */ -struct repeating_timer { - int64_t delay_us; - alarm_pool_t *pool; - alarm_id_t alarm_id; - repeating_timer_callback_t callback; - void *user_data; -}; - -/*! - * \brief Add a repeating timer that is called repeatedly at the specified interval in microseconds - * \ingroup repeating_timer - * - * Generally the callback is called as soon as possible after the time specified from an IRQ handler - * on the core the alarm pool was created on. If the callback is in the past or happens before - * the alarm setup could be completed, then this method will optionally call the callback itself - * and then return a return code to indicate that the target time has passed. - * - * \note It is safe to call this method from an IRQ handler (including alarm callbacks), and from either core. - * - * @param pool the alarm pool to use for scheduling the repeating timer (this determines which timer_alarm is used, and which core calls the callback) - * @param delay_us the repeat delay in microseconds; if >0 then this is the delay between one callback ending and the next starting; if <0 then this is the negative of the time between the starts of the callbacks. The value of 0 is treated as 1 - * @param callback the repeating timer callback function - * @param user_data user data to pass to store in the repeating_timer structure for use by the callback. - * @param out the pointer to the user owned structure to store the repeating timer info in. BEWARE this storage location must outlive the repeating timer, so be careful of using stack space - * @return false if there were no alarm slots available to create the timer, true otherwise. - */ -bool alarm_pool_add_repeating_timer_us(alarm_pool_t *pool, int64_t delay_us, repeating_timer_callback_t callback, void *user_data, repeating_timer_t *out); - -/*! - * \brief Add a repeating timer that is called repeatedly at the specified interval in milliseconds - * \ingroup repeating_timer - * - * Generally the callback is called as soon as possible after the time specified from an IRQ handler - * on the core the alarm pool was created on. If the callback is in the past or happens before - * the alarm setup could be completed, then this method will optionally call the callback itself - * and then return a return code to indicate that the target time has passed. - * - * \note It is safe to call this method from an IRQ handler (including alarm callbacks), and from either core. - * - * @param pool the alarm pool to use for scheduling the repeating timer (this determines which timer_alarm is used, and which core calls the callback) - * @param delay_ms the repeat delay in milliseconds; if >0 then this is the delay between one callback ending and the next starting; if <0 then this is the negative of the time between the starts of the callbacks. The value of 0 is treated as 1 microsecond - * @param callback the repeating timer callback function - * @param user_data user data to pass to store in the repeating_timer structure for use by the callback. - * @param out the pointer to the user owned structure to store the repeating timer info in. BEWARE this storage location must outlive the repeating timer, so be careful of using stack space - * @return false if there were no alarm slots available to create the timer, true otherwise. - */ -static inline bool alarm_pool_add_repeating_timer_ms(alarm_pool_t *pool, int32_t delay_ms, repeating_timer_callback_t callback, void *user_data, repeating_timer_t *out) { - return alarm_pool_add_repeating_timer_us(pool, delay_ms * (int64_t)1000, callback, user_data, out); -} - -#if !PICO_TIME_DEFAULT_ALARM_POOL_DISABLED -/*! - * \brief Add a repeating timer that is called repeatedly at the specified interval in microseconds - * \ingroup repeating_timer - * - * Generally the callback is called as soon as possible after the time specified from an IRQ handler - * on the core of the default alarm pool (generally core 0). If the callback is in the past or happens before - * the alarm setup could be completed, then this method will optionally call the callback itself - * and then return a return code to indicate that the target time has passed. - * - * \note It is safe to call this method from an IRQ handler (including alarm callbacks), and from either core. - * - * @param delay_us the repeat delay in microseconds; if >0 then this is the delay between one callback ending and the next starting; if <0 then this is the negative of the time between the starts of the callbacks. The value of 0 is treated as 1 - * @param callback the repeating timer callback function - * @param user_data user data to pass to store in the repeating_timer structure for use by the callback. - * @param out the pointer to the user owned structure to store the repeating timer info in. BEWARE this storage location must outlive the repeating timer, so be careful of using stack space - * @return false if there were no alarm slots available to create the timer, true otherwise. - */ -static inline bool add_repeating_timer_us(int64_t delay_us, repeating_timer_callback_t callback, void *user_data, repeating_timer_t *out) { - return alarm_pool_add_repeating_timer_us(alarm_pool_get_default(), delay_us, callback, user_data, out); -} - -/*! - * \brief Add a repeating timer that is called repeatedly at the specified interval in milliseconds - * \ingroup repeating_timer - * - * Generally the callback is called as soon as possible after the time specified from an IRQ handler - * on the core of the default alarm pool (generally core 0). If the callback is in the past or happens before - * the alarm setup could be completed, then this method will optionally call the callback itself - * and then return a return code to indicate that the target time has passed. - * - * \note It is safe to call this method from an IRQ handler (including alarm callbacks), and from either core. - * - * @param delay_ms the repeat delay in milliseconds; if >0 then this is the delay between one callback ending and the next starting; if <0 then this is the negative of the time between the starts of the callbacks. The value of 0 is treated as 1 microsecond - * @param callback the repeating timer callback function - * @param user_data user data to pass to store in the repeating_timer structure for use by the callback. - * @param out the pointer to the user owned structure to store the repeating timer info in. BEWARE this storage location must outlive the repeating timer, so be careful of using stack space - * @return false if there were no alarm slots available to create the timer, true otherwise. - */ -static inline bool add_repeating_timer_ms(int32_t delay_ms, repeating_timer_callback_t callback, void *user_data, repeating_timer_t *out) { - return alarm_pool_add_repeating_timer_us(alarm_pool_get_default(), delay_ms * (int64_t)1000, callback, user_data, out); -} -#endif - -/** - * \brief Cancel a repeating timer - * \ingroup repeating_timer - * \param timer the repeating timer to cancel - * \return true if the repeating timer was cancelled, false if it didn't exist - * \sa alarm_id_t for a note on reuse of IDs - */ -bool cancel_repeating_timer(repeating_timer_t *timer); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/lib/main/pico-sdk/common/pico_time/include/pico/timeout_helper.h b/lib/main/pico-sdk/common/pico_time/include/pico/timeout_helper.h deleted file mode 100644 index 88de8d85d7..0000000000 --- a/lib/main/pico-sdk/common/pico_time/include/pico/timeout_helper.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _PICO_TIMEOUT_HELPER_H -#define _PICO_TIMEOUT_HELPER_H - -#include "pico/time.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef struct timeout_state { - absolute_time_t next_timeout; - uint64_t param; -} timeout_state_t; - -typedef bool (*check_timeout_fn)(timeout_state_t *ts, bool reset); - -check_timeout_fn init_single_timeout_until(timeout_state_t *ts, absolute_time_t target); -check_timeout_fn init_per_iteration_timeout_us(timeout_state_t *ts, uint64_t per_iteration_timeout_us); - -#ifdef __cplusplus -} -#endif - -#endif \ No newline at end of file diff --git a/lib/main/pico-sdk/common/pico_time/time.c b/lib/main/pico-sdk/common/pico_time/time.c deleted file mode 100644 index 78ad26f072..0000000000 --- a/lib/main/pico-sdk/common/pico_time/time.c +++ /dev/null @@ -1,570 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include "pico.h" -#include "pico/time.h" -#include "pico/sync.h" -#include "pico/runtime_init.h" - -const absolute_time_t ABSOLUTE_TIME_INITIALIZED_VAR(nil_time, 0); -const absolute_time_t ABSOLUTE_TIME_INITIALIZED_VAR(at_the_end_of_time, INT64_MAX); - -typedef struct alarm_pool_entry { - // next entry link or -1 - int16_t next; - // low 15 bits are a sequence number used in the low word of the alarm_id so that - // the alarm_id for this entry only repeats every 32767 adds (note this value is never zero) - // the top bit is a cancellation flag. - volatile uint16_t sequence; - int64_t target; - alarm_callback_t callback; - void *user_data; -} alarm_pool_entry_t; - -struct alarm_pool { - uint8_t timer_alarm_num; - uint8_t core_num; - // this is protected by the lock (threads allocate from it, and the IRQ handler adds back to it) - int16_t free_head; - // this is protected by the lock (threads add to it, the IRQ handler removes from it) - volatile int16_t new_head; - volatile bool has_pending_cancellations; - - // this is owned by the IRQ handler so doesn't need additional locking - int16_t ordered_head; - uint16_t num_entries; - alarm_pool_timer_t *timer; - spin_lock_t *lock; - alarm_pool_entry_t *entries; -}; - -#if !PICO_TIME_DEFAULT_ALARM_POOL_DISABLED -// To avoid bringing in calloc, we statically allocate the arrays and the heap -static alarm_pool_entry_t default_alarm_pool_entries[PICO_TIME_DEFAULT_ALARM_POOL_MAX_TIMERS]; - -static alarm_pool_t default_alarm_pool = { - .entries = default_alarm_pool_entries, -}; - -static inline bool default_alarm_pool_initialized(void) { - return default_alarm_pool.lock != NULL; -} - -static lock_core_t sleep_notifier; -#endif - -#include "pico/time_adapter.h" - -static alarm_pool_t *pools[TA_NUM_TIMERS][TA_NUM_TIMER_ALARMS]; - -static void alarm_pool_post_alloc_init(alarm_pool_t *pool, alarm_pool_timer_t *timer, uint hardware_alarm_num, uint max_timers); - -static inline int16_t alarm_index(alarm_id_t id) { - return (int16_t)(id >> 16); -} - -static inline uint16_t alarm_sequence(alarm_id_t id) { - return (uint16_t)id; -} - -static alarm_id_t make_alarm_id(int index, uint16_t counter) { - return index << 16 | counter; -} - -#if !PICO_RUNTIME_NO_INIT_DEFAULT_ALARM_POOL -void __weak runtime_init_default_alarm_pool(void) { -#if !PICO_TIME_DEFAULT_ALARM_POOL_DISABLED - // allow multiple calls for ease of use from host tests - if (!default_alarm_pool_initialized()) { - alarm_pool_timer_t *timer = alarm_pool_get_default_timer(); - ta_hardware_alarm_claim(timer, PICO_TIME_DEFAULT_ALARM_POOL_HARDWARE_ALARM_NUM); - alarm_pool_post_alloc_init(&default_alarm_pool, - timer, - PICO_TIME_DEFAULT_ALARM_POOL_HARDWARE_ALARM_NUM, - PICO_TIME_DEFAULT_ALARM_POOL_MAX_TIMERS); - } - lock_init(&sleep_notifier, PICO_SPINLOCK_ID_TIMER); -#endif -} -#endif - -void alarm_pool_init_default(void) { - runtime_init_default_alarm_pool(); -} - -#if !PICO_TIME_DEFAULT_ALARM_POOL_DISABLED -alarm_pool_t *alarm_pool_get_default(void) { - assert(default_alarm_pool_initialized()); - return &default_alarm_pool; -} - -#if defined(PICO_RUNTIME_INIT_DEFAULT_ALARM_POOL) && !PICO_RUNTIME_SKIP_INIT_DEFAULT_ALARM_POOL -PICO_RUNTIME_INIT_FUNC_RUNTIME(runtime_init_default_alarm_pool, PICO_RUNTIME_INIT_DEFAULT_ALARM_POOL); -#endif -#endif - -// note the timer is created with IRQs on this core -alarm_pool_t *alarm_pool_create_on_timer(alarm_pool_timer_t *timer, uint hardware_alarm_num, uint max_timers) { - alarm_pool_t *pool = (alarm_pool_t *) malloc(sizeof(alarm_pool_t)); - if (pool) { - pool->entries = (alarm_pool_entry_t *) calloc(max_timers, sizeof(alarm_pool_entry_t)); - ta_hardware_alarm_claim(timer, hardware_alarm_num); - alarm_pool_post_alloc_init(pool, timer, hardware_alarm_num, max_timers); - } - return pool; -} - -alarm_pool_t *alarm_pool_create_on_timer_with_unused_hardware_alarm(alarm_pool_timer_t *timer, uint max_timers) { - alarm_pool_t *pool = (alarm_pool_t *) malloc(sizeof(alarm_pool_t)); - if (pool) { - pool->entries = (alarm_pool_entry_t *) calloc(max_timers, sizeof(alarm_pool_entry_t)); - alarm_pool_post_alloc_init(pool, timer, (uint) ta_hardware_alarm_claim_unused(timer, true), max_timers); - } - return pool; -} - -static void alarm_pool_irq_handler(void); - -// marker which we can use in place of handler function to indicate we are a repeating timer - -#define repeating_timer_marker ((alarm_callback_t)alarm_pool_irq_handler) -#include "hardware/gpio.h" -static void alarm_pool_irq_handler(void) { - // This IRQ handler does the main work, as it always (assuming the IRQ hasn't been enabled on both cores - // which is unsupported) run on the alarm pool's core, and can't be preempted by itself, meaning - // that it doesn't need locks except to protect against linked list, or other state access. - // This simplifies the code considerably, and makes it much faster in general, even though we are forced to take - // two IRQs per alarm. - uint timer_alarm_num; - alarm_pool_timer_t *timer = ta_from_current_irq(&timer_alarm_num); - uint timer_num = ta_timer_num(timer); - alarm_pool_t *pool = pools[timer_num][timer_alarm_num]; - assert(pool->timer_alarm_num == timer_alarm_num); - int64_t earliest_target; - // 1. clear force bits if we were forced (do this outside the loop, as forcing is hopefully rare) - ta_clear_force_irq(timer, timer_alarm_num); - do { - // 2. clear the IRQ if it was fired - ta_clear_irq(timer, timer_alarm_num); - // 3. we look at the earliest existing alarm first; the reasoning here is that we - // don't want to delay an existing callback because a later one is added, and - // if both are due now, then we have a race anyway (but we prefer to fire existing - // timers before new ones anyway. - int16_t earliest_index = pool->ordered_head; - // by default, we loop if there was any event pending (we will mark it false - // later if there is no work to do) - if (earliest_index >= 0) { - alarm_pool_entry_t *earliest_entry = &pool->entries[earliest_index]; - earliest_target = earliest_entry->target; - if (((int64_t)ta_time_us_64(timer) - earliest_target) >= 0) { - // time to call the callback now (or in the past) - // note that an entry->target of < 0 means the entry has been canceled (not this is set - // by this function, in response to the entry having been queued by the cancel_alarm API - // meaning that we don't need to worry about tearing of the 64 bit value) - int64_t delta; - if (earliest_target >= 0) { - // special case repeating timer without making another function call which adds overhead - if (earliest_entry->callback == repeating_timer_marker) { - repeating_timer_t *rpt = (repeating_timer_t *)earliest_entry->user_data; - delta = rpt->callback(rpt) ? rpt->delay_us : 0; - } else { - alarm_id_t id = make_alarm_id(pool->ordered_head, earliest_entry->sequence); - delta = earliest_entry->callback(id, earliest_entry->user_data); - } - } else { - // negative target means cancel alarm - delta = 0; - } - if (delta) { - int64_t next_time; - if (delta < 0) { - // delta is (positive) delta from last fire time - next_time = earliest_target - delta; - } else { - // delta is relative to now - next_time = (int64_t) ta_time_us_64(timer) + delta; - } - earliest_entry->target = next_time; - // need to re-add, unless we are the only entry or already at the front - if (earliest_entry->next >= 0 && next_time - pool->entries[earliest_entry->next].target >= 0) { - // unlink this item - pool->ordered_head = earliest_entry->next; - int16_t *prev = &pool->ordered_head; - // find insertion point; note >= as if we add a new item for the same time as another, then it follows - while (*prev >= 0 && (next_time - pool->entries[*prev].target) >= 0) { - prev = &pool->entries[*prev].next; - } - earliest_entry->next = *prev; - *prev = earliest_index; - } - } else { - // need to remove the item - pool->ordered_head = earliest_entry->next; - // and add it back to the free list (under lock) - uint32_t save = spin_lock_blocking(pool->lock); - earliest_entry->next = pool->free_head; - pool->free_head = earliest_index; - spin_unlock(pool->lock, save); - } - } - } - // if we have any new alarms, add them to the ordered list - if (pool->new_head >= 0) { - uint32_t save = spin_lock_blocking(pool->lock); - // must re-read new head under lock - int16_t new_index = pool->new_head; - // clear the list - pool->new_head = -1; - spin_unlock(pool->lock, save); - // insert each of the new items - while (new_index >= 0) { - alarm_pool_entry_t *new_entry = &pool->entries[new_index]; - int64_t new_entry_time = new_entry->target; - int16_t *prev = &pool->ordered_head; - // find insertion point; note >= as if we add a new item for the same time as another, then it follows - while (*prev >= 0 && (new_entry_time - pool->entries[*prev].target) >= 0) { - prev = &pool->entries[*prev].next; - } - int16_t next = *prev; - *prev = new_index; - new_index = new_entry->next; - new_entry->next = next; - } - } - // if we have any canceled alarms, then mark them for removal by setting their due time to -1 (which will - // cause them to be handled the next time round and removed) - if (pool->has_pending_cancellations) { - pool->has_pending_cancellations = false; - __compiler_memory_barrier(); - int16_t *prev = &pool->ordered_head; - // set target for canceled items to -1, and move to front of the list - for(int16_t index = pool->ordered_head; index != -1; ) { - alarm_pool_entry_t *entry = &pool->entries[index]; - int16_t next = entry->next; - if ((int16_t)entry->sequence < 0) { - // mark for deletion - entry->target = -1; - if (index != pool->ordered_head) { - // move to start of queue - *prev = entry->next; - entry->next = pool->ordered_head; - pool->ordered_head = index; - } - } else { - prev = &entry->next; - } - index = next; - } - } - earliest_index = pool->ordered_head; - if (earliest_index < 0) break; - // need to wait - alarm_pool_entry_t *earliest_entry = &pool->entries[earliest_index]; - earliest_target = earliest_entry->target; - // we are leaving a timeout every 2^32 microseconds anyway if there is no valid target, so we can choose any value. - // best_effort_wfe_or_timeout now relies on it being the last value set, and arguably this is the - // best value anyway, as it is the furthest away from the last fire. - if (earliest_target != -1) { // cancelled alarm has target of -1 - ta_set_timeout(timer, timer_alarm_num, earliest_target); - } - // check we haven't now passed the target time; if not we don't want to loop again - } while ((earliest_target - (int64_t)ta_time_us_64(timer)) <= 0); - // We always want the timer IRQ to wake a WFE so that best_effort_wfe_or_timeout() will wake up. It will wake - // a WFE on its own core by nature of having taken an IRQ, but we do an explicit SEV so it wakes the other core - __sev(); -} - -void alarm_pool_post_alloc_init(alarm_pool_t *pool, alarm_pool_timer_t *timer, uint hardware_alarm_num, uint max_timers) { - pool->timer = timer; - pool->lock = spin_lock_instance(next_striped_spin_lock_num()); - pool->timer_alarm_num = (uint8_t) hardware_alarm_num; - invalid_params_if(PICO_TIME, max_timers > 65536); - pool->num_entries = (uint16_t)max_timers; - pool->core_num = (uint8_t) get_core_num(); - pool->new_head = pool->ordered_head = -1; - pool->free_head = (int16_t)(max_timers - 1); - for(uint i=0;ientries[i].next = (int16_t)(i-1); - } - pools[ta_timer_num(timer)][hardware_alarm_num] = pool; - - ta_enable_irq_handler(timer, hardware_alarm_num, alarm_pool_irq_handler); -} - -void alarm_pool_destroy(alarm_pool_t *pool) { -#if !PICO_TIME_DEFAULT_ALARM_POOL_DISABLED - if (pool == &default_alarm_pool) { - assert(false); // attempt to delete default alarm pool - return; - } -#endif - ta_disable_irq_handler(pool->timer, pool->timer_alarm_num, alarm_pool_irq_handler); - assert(pools[ta_timer_num(pool->timer)][pool->timer_alarm_num] == pool); - pools[ta_timer_num(pool->timer)][pool->timer_alarm_num] = NULL; - free(pool->entries); - free(pool); -} - -alarm_id_t alarm_pool_add_alarm_at(alarm_pool_t *pool, absolute_time_t time, alarm_callback_t callback, - void *user_data, bool fire_if_past) { - if (!fire_if_past) { - absolute_time_t t = get_absolute_time(); - if (absolute_time_diff_us(t, time) < 0) return 0; - } - return alarm_pool_add_alarm_at_force_in_context(pool, time, callback, user_data); -} - -alarm_id_t alarm_pool_add_alarm_at_force_in_context(alarm_pool_t *pool, absolute_time_t time, alarm_callback_t callback, - void *user_data) { - // ---- take a free pool entry - uint32_t save = spin_lock_blocking(pool->lock); - int16_t index = pool->free_head; - alarm_pool_entry_t *entry = &pool->entries[index]; - if (index >= 0) { - // remove from free list - pool->free_head = entry->next; - } - spin_unlock(pool->lock, save); - if (index < 0) return PICO_ERROR_GENERIC; // PICO_ERROR_INSUFFICIENT_RESOURCES - not using to preserve previous -1 return code - - // ---- initialize the pool entry - entry->callback = callback; - entry->user_data = user_data; - entry->target = (int64_t)to_us_since_boot(time); - uint16_t next_sequence = (entry->sequence + 1) & 0x7fff; - if (!next_sequence) next_sequence = 1; // zero is not allowed - entry->sequence = next_sequence; - alarm_id_t id = make_alarm_id(index, next_sequence); - - // ---- and add it to the new list - save = spin_lock_blocking(pool->lock); - entry->next = pool->new_head; - pool->new_head = index; - spin_unlock(pool->lock, save); - - // force the IRQ - ta_force_irq(pool->timer, pool->timer_alarm_num); - return id; -} - -bool alarm_pool_cancel_alarm(alarm_pool_t *pool, alarm_id_t alarm_id) { - int16_t index = alarm_index(alarm_id); - if (index >= pool->num_entries) return false; - uint16_t sequence = alarm_sequence(alarm_id); - bool canceled = false; - alarm_pool_entry_t *entry = &pool->entries[index]; - uint32_t save = spin_lock_blocking(pool->lock); - // note this will not be true if the entry is already canceled (as the entry->sequence - // will have the top bit set) - uint current_sequence = entry->sequence; - if (sequence == current_sequence) { - entry->sequence = (uint16_t)(current_sequence | 0x8000); - __compiler_memory_barrier(); - pool->has_pending_cancellations = true; - canceled = true; - } - spin_unlock(pool->lock, save); - // force the IRQ if we need to clean up an alarm id - if (canceled) ta_force_irq(pool->timer, pool->timer_alarm_num); - return canceled; -} - -uint alarm_pool_timer_alarm_num(alarm_pool_t *pool) { - return pool->timer_alarm_num; -} - -uint alarm_pool_core_num(alarm_pool_t *pool) { - return pool->core_num; -} - -#if !PICO_TIME_DEFAULT_ALARM_POOL_DISABLED -static int64_t sleep_until_callback(__unused alarm_id_t id, __unused void *user_data) { - uint32_t save = spin_lock_blocking(sleep_notifier.spin_lock); - lock_internal_spin_unlock_with_notify(&sleep_notifier, save); - return 0; -} -#endif - -void sleep_until(absolute_time_t t) { -#if PICO_ON_DEVICE && !defined(NDEBUG) - if (__get_current_exception()) { - panic("Attempted to sleep inside of an exception handler; use busy_wait if you must"); - } -#endif -#if !PICO_TIME_DEFAULT_ALARM_POOL_DISABLED - uint64_t t_us = to_us_since_boot(t); - uint64_t t_before_us = t_us - PICO_TIME_SLEEP_OVERHEAD_ADJUST_US; - // needs to work in the first PICO_TIME_SLEEP_OVERHEAD_ADJUST_US of boot - if (t_before_us > t_us) t_before_us = 0; - absolute_time_t t_before; - update_us_since_boot(&t_before, t_before_us); - if (absolute_time_diff_us(get_absolute_time(), t_before) > 0) { - if (add_alarm_at(t_before, sleep_until_callback, NULL, false) >= 0) { - // able to add alarm for just before the time - while (!time_reached(t_before)) { - uint32_t save = spin_lock_blocking(sleep_notifier.spin_lock); - lock_internal_spin_unlock_with_wait(&sleep_notifier, save); - } - } - } -#else - // hook in case we're in RTOS; note we assume using the alarm pool is better always if available. - sync_internal_yield_until_before(t); -#endif - // now wait until the exact time - busy_wait_until(t); -} - -void sleep_us(uint64_t us) { -#if !PICO_TIME_DEFAULT_ALARM_POOL_DISABLED - sleep_until(make_timeout_time_us(us)); -#else - if (us < PICO_TIME_SLEEP_OVERHEAD_ADJUST_US) { - busy_wait_us(us); - } else { - // hook in case we're in RTOS; note we assume using the alarm pool is better always if available. - absolute_time_t t = make_timeout_time_us(us - PICO_TIME_SLEEP_OVERHEAD_ADJUST_US); - sync_internal_yield_until_before(t); - - // then wait the rest of the way - busy_wait_until(t); - } -#endif -} - -void sleep_ms(uint32_t ms) { - sleep_us(ms * 1000ull); -} - -bool best_effort_wfe_or_timeout(absolute_time_t timeout_timestamp) { -#if !PICO_TIME_DEFAULT_ALARM_POOL_DISABLED - if (__get_current_exception()) { - tight_loop_contents(); - return time_reached(timeout_timestamp); - } else { - alarm_id_t id; - // note that as of SDK 2.0.0 calling add_alarm_at always causes a SEV. What we really - // want to do is cause an IRQ at the specified time in the future if there is not - // an IRQ already happening before then. The problem is that the IRQ may be happening on the - // other core, so taking an IRQ is the only way to get the state protection. - // - // Therefore, we make a compromise; we will set the alarm, if we won't wake up before the right time - // already. This means that repeated calls to this function with the same timeout will work correctly - // after the first one! This is fine, because we ask callers to use a polling loop on another - // event variable when using this function. - // - // For this to work, we require that once we have set an alarm, an SEV happens no later than that, even - // if we cancel the alarm as we do below. Therefore, the IRQ handler (which is always enabled) will - // never set its wakeup time to a later value, but instead wake up once and then wake up again. - // - // This overhead when canceling alarms is a small price to pay for the much simpler/faster/cleaner - // implementation that relies on the IRQ handler (on a single core) being the only state accessor. - // - // Note also, that the use of software spin locks on RP2350 to access state would always cause a SEV - // due to use of LDREX etc., so actually using spin locks to protect the state would be worse. - if (ta_wakes_up_on_or_before(alarm_pool_get_default()->timer, alarm_pool_get_default()->timer_alarm_num, - (int64_t)to_us_since_boot(timeout_timestamp))) { - // we already are waking up at or before when we want to (possibly due to us having been called - // before in a loop), so we can do an actual WFE. Note we rely on the fact that the alarm pool IRQ - // handler always does an explicit SEV, since it may be on the other core. - __wfe(); - return time_reached(timeout_timestamp); - } else { - id = add_alarm_at(timeout_timestamp, sleep_until_callback, NULL, false); - if (id <= 0) { - tight_loop_contents(); - return time_reached(timeout_timestamp); - } else { - if (!time_reached(timeout_timestamp)) { - // ^ at the point above the timer hadn't fired, so it is safe - // to wait; the event will happen due to IRQ at some point between - // then and the correct wakeup time - __wfe(); - } - // we need to clean up if it wasn't us that caused the wfe; if it was this will be a noop. - cancel_alarm(id); - return time_reached(timeout_timestamp); - } - } - } -#else - tight_loop_contents(); - return time_reached(timeout_timestamp); -#endif -} - -bool alarm_pool_add_repeating_timer_us(alarm_pool_t *pool, int64_t delay_us, repeating_timer_callback_t callback, void *user_data, repeating_timer_t *out) { - if (!delay_us) delay_us = 1; - out->pool = pool; - out->callback = callback; - out->delay_us = delay_us; - out->user_data = user_data; - out->alarm_id = alarm_pool_add_alarm_at(pool, make_timeout_time_us((uint64_t)(delay_us >= 0 ? delay_us : -delay_us)), - repeating_timer_marker, out, true); - return out->alarm_id > 0; -} - -bool cancel_repeating_timer(repeating_timer_t *timer) { - bool rc = false; - if (timer->alarm_id) { - rc = alarm_pool_cancel_alarm(timer->pool, timer->alarm_id); - timer->alarm_id = 0; - } - return rc; -} - -alarm_pool_timer_t *alarm_pool_timer_for_timer_num(uint timer_num) { - return ta_timer_instance(timer_num); -} - -alarm_pool_timer_t *alarm_pool_get_default_timer(void) { - return ta_default_timer_instance(); -} - -int64_t alarm_pool_remaining_alarm_time_us(alarm_pool_t *pool, alarm_id_t alarm_id) { - // note there is no point distinguishing between invalid alarm_id and timer passed, - // since an alarm_id that has fired without being re-enabled becomes logically invalid after - // that point anyway - int64_t rc = -1; - int16_t index = alarm_index(alarm_id); - if ((uint16_t)index < pool->num_entries) { - uint16_t sequence = alarm_sequence(alarm_id); - alarm_pool_entry_t *entry = &pool->entries[index]; - if (entry->sequence == sequence) { - uint32_t save = spin_lock_blocking(pool->lock); - int16_t search_index = pool->ordered_head; - while (search_index >= 0) { - entry = &pool->entries[search_index]; - if (index == search_index) { - if (entry->sequence == sequence) { - rc = entry->target - (int64_t) ta_time_us_64(pool->timer); - } - break; - } - search_index = entry->next; - } - spin_unlock(pool->lock, save); - } - } - return rc; -} - -int32_t alarm_pool_remaining_alarm_time_ms(alarm_pool_t *pool, alarm_id_t alarm_id) { - int64_t rc = alarm_pool_remaining_alarm_time_us(pool, alarm_id); - if (rc >= 0) rc /= 1000; - return rc >= INT32_MAX ? INT32_MAX : (int32_t) rc; -} - -#if !PICO_TIME_DEFAULT_ALARM_POOL_DISABLED -int64_t remaining_alarm_time_us(alarm_id_t alarm_id) { - return alarm_pool_remaining_alarm_time_us(alarm_pool_get_default(), alarm_id); -} - -int32_t remaining_alarm_time_ms(alarm_id_t alarm_id) { - return alarm_pool_remaining_alarm_time_ms(alarm_pool_get_default(), alarm_id); -} -#endif \ No newline at end of file diff --git a/lib/main/pico-sdk/common/pico_time/timeout_helper.c b/lib/main/pico-sdk/common/pico_time/timeout_helper.c deleted file mode 100644 index 3f22457431..0000000000 --- a/lib/main/pico-sdk/common/pico_time/timeout_helper.c +++ /dev/null @@ -1,32 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "pico/timeout_helper.h" - -static bool check_single_timeout_us(timeout_state_t *ts, __unused bool reset) { - return time_reached(ts->next_timeout); -} - -check_timeout_fn init_single_timeout_until(timeout_state_t *ts, absolute_time_t target) { - ts->next_timeout = target; - return check_single_timeout_us; -} - -static bool check_per_iteration_timeout_us(timeout_state_t *ts, bool reset) { - if (reset) { - ts->next_timeout = make_timeout_time_us(ts->param); - } - if (time_reached(ts->next_timeout)) { - return true; - } - return false; -} - -check_timeout_fn init_per_iteration_timeout_us(timeout_state_t *ts, uint64_t per_iteration_timeout_us) { - ts->next_timeout = make_timeout_time_us(per_iteration_timeout_us); - ts->param = per_iteration_timeout_us; - return check_per_iteration_timeout_us; -} \ No newline at end of file diff --git a/lib/main/pico-sdk/common/pico_usb_reset_interface_headers/include/pico/usb_reset_interface.h b/lib/main/pico-sdk/common/pico_usb_reset_interface_headers/include/pico/usb_reset_interface.h deleted file mode 100644 index d5269ecf82..0000000000 --- a/lib/main/pico-sdk/common/pico_usb_reset_interface_headers/include/pico/usb_reset_interface.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _PICO_USB_RESET_INTERFACE_H -#define _PICO_USB_RESET_INTERFACE_H - -/** \file usb_reset_interface.h - * \defgroup pico_usb_reset_interface_headers pico_usb_reset_interface_headers - * - * \brief Definition for the reset interface that may be exposed by the pico_stdio_usb library - */ - -// VENDOR sub-class for the reset interface -#define RESET_INTERFACE_SUBCLASS 0x00 -// VENDOR protocol for the reset interface -#define RESET_INTERFACE_PROTOCOL 0x01 - -// CONTROL requests: - -// reset to BOOTSEL -#define RESET_REQUEST_BOOTSEL 0x01 -// regular flash boot -#define RESET_REQUEST_FLASH 0x02 - -#endif \ No newline at end of file diff --git a/lib/main/pico-sdk/common/pico_util/datetime.c b/lib/main/pico-sdk/common/pico_util/datetime.c deleted file mode 100644 index c113ce4662..0000000000 --- a/lib/main/pico-sdk/common/pico_util/datetime.c +++ /dev/null @@ -1,95 +0,0 @@ -#include "pico/util/datetime.h" - -#include - -#if PICO_INCLUDE_RTC_DATETIME -static const char *DATETIME_MONTHS[12] = { - "January", - "February", - "March", - "April", - "May", - "June", - "July", - "August", - "September", - "October", - "November", - "December" -}; - -static const char *DATETIME_DOWS[7] = { - "Sunday", - "Monday", - "Tuesday", - "Wednesday", - "Thursday", - "Friday", - "Saturday", -}; - -void datetime_to_str(char *buf, uint buf_size, const datetime_t *t) { - snprintf(buf, - buf_size, - "%s %d %s %d:%02d:%02d %d", - DATETIME_DOWS[t->dotw], - t->day, - DATETIME_MONTHS[t->month - 1], - t->hour, - t->min, - t->sec, - t->year); -}; - - -bool time_to_datetime(time_t time, datetime_t *dt) { - struct tm local; - if (localtime_r(&time, &local)) { - dt->year = (int16_t) (local.tm_year + 1900); // 0..4095 - dt->month = (int8_t) (local.tm_mon + 1); // 1..12, 1 is January - dt->day = (int8_t) local.tm_mday; // 1..28,29,30,31 depending on month - dt->dotw = (int8_t) local.tm_wday; // 0..6, 0 is Sunday - dt->hour = (int8_t) local.tm_hour; // 0..23 - dt->min = (int8_t) local.tm_min; // 0..59 - dt->sec = (int8_t) local.tm_sec; // 0..59 - return true; - } - return false; -} - -bool datetime_to_time(const datetime_t *dt, time_t *time) { - struct tm local; - local.tm_year = dt->year - 1900; - local.tm_mon = dt->month - 1; - local.tm_mday = dt->day; - local.tm_hour = dt->hour; - local.tm_min = dt->min; - local.tm_sec = dt->sec; - *time = mktime(&local); - return *time >= 0; -} - -#endif - -uint64_t timespec_to_ms(const struct timespec *ts) { - int64_t rc = ts->tv_sec * 1000; - rc += ts->tv_nsec / 1000000; - return (uint64_t) rc; -} - -void ms_to_timespec(uint64_t ms, struct timespec *ts) { - ts->tv_sec = (time_t)((int64_t)ms / 1000); - ts->tv_nsec = ((long)((int64_t)ms % 1000)) * 1000000; -} - -uint64_t timespec_to_us(const struct timespec *ts) { - int64_t rc = ts->tv_sec * 1000000; - rc += ts->tv_nsec / 1000; - return (uint64_t) rc; -} - -void us_to_timespec(uint64_t ms, struct timespec *ts) { - ts->tv_sec = (time_t)((int64_t)ms / 1000000); - ts->tv_nsec = ((long)((int64_t)ms % 1000000)) * 1000; -} - diff --git a/lib/main/pico-sdk/common/pico_util/doc.h b/lib/main/pico-sdk/common/pico_util/doc.h deleted file mode 100644 index 4485b5d5ff..0000000000 --- a/lib/main/pico-sdk/common/pico_util/doc.h +++ /dev/null @@ -1,4 +0,0 @@ -/** - * \defgroup pico_util pico_util - * \brief Useful data structures and utility functions - */ diff --git a/lib/main/pico-sdk/common/pico_util/include/pico/util/datetime.h b/lib/main/pico-sdk/common/pico_util/include/pico/util/datetime.h deleted file mode 100644 index 92e6d6460f..0000000000 --- a/lib/main/pico-sdk/common/pico_util/include/pico/util/datetime.h +++ /dev/null @@ -1,47 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _PICO_UTIL_DATETIME_H -#define _PICO_UTIL_DATETIME_H - -#include "pico.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** \file datetime.h - * \defgroup util_datetime datetime - * \brief Date/Time formatting - * \ingroup pico_util - */ - -#if PICO_INCLUDE_RTC_DATETIME -#include - -/*! \brief Convert a datetime_t structure to a string - * \ingroup util_datetime - * - * \param buf character buffer to accept generated string - * \param buf_size The size of the passed in buffer - * \param t The datetime to be converted. - */ -void datetime_to_str(char *buf, uint buf_size, const datetime_t *t); - -bool time_to_datetime(time_t time, datetime_t *dt); -bool datetime_to_time(const datetime_t *dt, time_t *time); -#endif - -#include -uint64_t timespec_to_ms(const struct timespec *ts); -uint64_t timespec_to_us(const struct timespec *ts); -void ms_to_timespec(uint64_t ms, struct timespec *ts); -void us_to_timespec(uint64_t ms, struct timespec *ts); - -#ifdef __cplusplus -} -#endif -#endif diff --git a/lib/main/pico-sdk/common/pico_util/include/pico/util/pheap.h b/lib/main/pico-sdk/common/pico_util/include/pico/util/pheap.h deleted file mode 100644 index 402d9cb3a0..0000000000 --- a/lib/main/pico-sdk/common/pico_util/include/pico/util/pheap.h +++ /dev/null @@ -1,309 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _PICO_UTIL_PHEAP_H -#define _PICO_UTIL_PHEAP_H - -#include "pico.h" - -#ifdef __cplusplus -extern "C" { -#endif - -// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_PHEAP, Enable/disable assertions in the pheap module, type=bool, default=0, group=pico_util -#ifndef PARAM_ASSERTIONS_ENABLED_PHEAP -#define PARAM_ASSERTIONS_ENABLED_PHEAP 0 -#endif - -/** - * \file pheap.h - * \defgroup util_pheap pheap - * \brief Pairing Heap Implementation - * \ingroup pico_util - * - * pheap defines a simple pairing heap. The implementation simply tracks array indexes, it is up to - * the user to provide storage for heap entries and a comparison function. - * - * NOTE: This class is not safe for concurrent usage. It should be externally protected. Furthermore - * if used concurrently, the caller needs to protect around their use of the returned id. - * For example, ph_remove_and_free_head returns the id of an element that is no longer in the heap. - * The user can still use this to look at the data in their companion array, however obviously further operations - * on the heap may cause them to overwrite that data as the id may be reused on subsequent operations - * - */ -// PICO_CONFIG: PICO_PHEAP_MAX_ENTRIES, Maximum number of entries in the pheap, min=1, max=65534, default=255, group=pico_util -#ifndef PICO_PHEAP_MAX_ENTRIES -#define PICO_PHEAP_MAX_ENTRIES 255 -#endif - -// public heap_node ids are numbered from 1 (0 means none) -#if PICO_PHEAP_MAX_ENTRIES < 256 -typedef uint8_t pheap_node_id_t; -#elif PICO_PHEAP_MAX_ENTRIES < 65535 -typedef uint16_t pheap_node_id_t; -#else -#error invalid PICO_PHEAP_MAX_ENTRIES -#endif - -typedef struct pheap_node { - pheap_node_id_t child, sibling, parent; -} pheap_node_t; - -/** - * \brief A user comparator function for nodes in a pairing heap. - * \ingroup util_pheap - * - * \return true if a < b in natural order. Note this relative ordering must be stable from call to call. - */ -typedef bool (*pheap_comparator)(void *user_data, pheap_node_id_t a, pheap_node_id_t b); - -typedef struct pheap { - pheap_node_t *nodes; - pheap_comparator comparator; - void *user_data; - pheap_node_id_t max_nodes; - pheap_node_id_t root_id; - // we remove from head and add to tail to stop reusing the same ids - pheap_node_id_t free_head_id; - pheap_node_id_t free_tail_id; -} pheap_t; - -/** - * \brief Create a pairing heap, which effectively maintains an efficient sorted ordering - * of nodes. The heap itself stores no user per-node state, it is expected - * that the user maintains a companion array. A comparator function must - * be provided so that the heap implementation can determine the relative ordering of nodes - * \ingroup util_pheap - * - * \param max_nodes the maximum number of nodes that may be in the heap (this is bounded by - * PICO_PHEAP_MAX_ENTRIES which defaults to 255 to be able to store indexes - * in a single byte). - * \param comparator the node comparison function - * \param user_data a user data pointer associated with the heap that is provided in callbacks - * \return a newly allocated and initialized heap - */ -pheap_t *ph_create(uint max_nodes, pheap_comparator comparator, void *user_data); - -/** - * \brief Removes all nodes from the pairing heap - * \ingroup util_pheap - * \param heap the heap - */ -void ph_clear(pheap_t *heap); - -/** - * \brief De-allocates a pairing heap - * \ingroup util_pheap - * - * Note this method must *ONLY* be called on heaps created by ph_create() - * \param heap the heap - */ -void ph_destroy(pheap_t *heap); - -// internal method -static inline pheap_node_t *ph_get_node(pheap_t *heap, pheap_node_id_t id) { - assert(id && id <= heap->max_nodes); - return heap->nodes + id - 1; -} - -// internal method -static void ph_add_child_node(pheap_t *heap, pheap_node_id_t parent_id, pheap_node_id_t child_id) { - pheap_node_t *n = ph_get_node(heap, parent_id); - assert(parent_id); - assert(child_id); - assert(parent_id != child_id); - pheap_node_t *c = ph_get_node(heap, child_id); - c->parent = parent_id; - if (!n->child) { - n->child = child_id; - } else { - c->sibling = n->child; - n->child = child_id; - } -} - -// internal method -static pheap_node_id_t ph_merge_nodes(pheap_t *heap, pheap_node_id_t a, pheap_node_id_t b) { - if (!a) return b; - if (!b) return a; - if (heap->comparator(heap->user_data, a, b)) { - ph_add_child_node(heap, a, b); - return a; - } else { - ph_add_child_node(heap, b, a); - return b; - } -} - -/** - * \brief Allocate a new node from the unused space in the heap - * \ingroup util_pheap - * - * \param heap the heap - * \return an identifier for the node, or 0 if the heap is full - */ -static inline pheap_node_id_t ph_new_node(pheap_t *heap) { - if (!heap->free_head_id) return 0; - pheap_node_id_t id = heap->free_head_id; - pheap_node_t *hn = ph_get_node(heap, id); - heap->free_head_id = hn->sibling; - if (!heap->free_head_id) heap->free_tail_id = 0; - hn->child = hn->sibling = hn->parent = 0; - return id; -} - -/** - * \brief Inserts a node into the heap. - * \ingroup util_pheap - * - * This method inserts a node (previously allocated by ph_new_node()) - * into the heap, determining the correct order by calling - * the heap's comparator - * - * \param heap the heap - * \param id the id of the node to insert - * \return the id of the new head of the pairing heap (i.e. node that compares first) - */ -static inline pheap_node_id_t ph_insert_node(pheap_t *heap, pheap_node_id_t id) { - assert(id); - pheap_node_t *hn = ph_get_node(heap, id); - hn->child = hn->sibling = hn->parent = 0; - heap->root_id = ph_merge_nodes(heap, heap->root_id, id); - return heap->root_id; -} - -/** - * \brief Returns the head node in the heap, i.e. the node - * which compares first, but without removing it from the heap. - * \ingroup util_pheap - * - * \param heap the heap - * \return the current head node id - */ -static inline pheap_node_id_t ph_peek_head(pheap_t *heap) { - return heap->root_id; -} - -/** - * \brief Remove the head node from the pairing heap. This head node is - * the node which compares first in the logical ordering provided - * by the comparator. - * \ingroup util_pheap - * - * Note that in the case of free == true, the returned id is no longer - * allocated and may be re-used by future node allocations, so the caller - * should retrieve any per node state from the companion array before modifying - * the heap further. - * - * @param heap the heap - * @param free true if the id is also to be freed; false if not - useful if the caller - * may wish to re-insert an item with the same id) - * @return the old head node id. - */ -pheap_node_id_t ph_remove_head(pheap_t *heap, bool free); - -/** - * \brief Remove the head node from the pairing heap. This head node is - * the node which compares first in the logical ordering provided - * by the comparator. - * \ingroup util_pheap - * - * Note that the returned id will be freed, and thus may be re-used by future node allocations, - * so the caller should retrieve any per node state from the companion array before modifying - * the heap further. - * - * @param heap the heap - * @return the old head node id. - */ -static inline pheap_node_id_t ph_remove_and_free_head(pheap_t *heap) { - return ph_remove_head(heap, true); -} - -/** - * \brief Remove and free an arbitrary node from the pairing heap. This is a more - * costly operation than removing the head via ph_remove_and_free_head() - * \ingroup util_pheap - * - * @param heap the heap - * @param id the id of the node to free - * @return true if the the node was in the heap, false otherwise - */ -bool ph_remove_and_free_node(pheap_t *heap, pheap_node_id_t id); - -/** - * \brief Determine if the heap contains a given node. Note containment refers - * to whether the node is inserted (ph_insert_node()) vs allocated (ph_new_node()) - * \ingroup util_pheap - * - * @param heap the heap - * @param id the id of the node - * @return true if the heap contains a node with the given id, false otherwise. - */ -static inline bool ph_contains_node(pheap_t *heap, pheap_node_id_t id) { - return id == heap->root_id || ph_get_node(heap, id)->parent; -} - - -/** - * \brief Free a node that is not currently in the heap, but has been allocated - * \ingroup util_pheap - * - * @param heap the heap - * @param id the id of the node - */ -static inline void ph_free_node(pheap_t *heap, pheap_node_id_t id) { - assert(id && !ph_contains_node(heap, id)); - if (heap->free_tail_id) { - ph_get_node(heap, heap->free_tail_id)->sibling = id; - } - if (!heap->free_head_id) { - assert(!heap->free_tail_id); - heap->free_head_id = id; - } - heap->free_tail_id = id; -} - -/** - * \brief Print a representation of the heap for debugging - * \ingroup util_pheap - * - * @param heap the heap - * @param dump_key a method to print a node value - * @param user_data the user data to pass to the dump_key method - */ -void ph_dump(pheap_t *heap, void (*dump_key)(pheap_node_id_t id, void *user_data), void *user_data); - -/** - * \brief Initialize a statically allocated heap (ph_create() using the C heap). - * The heap member `nodes` must be allocated of size max_nodes. - * \ingroup util_pheap - * - * @param heap the heap - * @param max_nodes the max number of nodes in the heap (matching the size of the heap's nodes array) - * @param comparator the comparator for the heap - * @param user_data the user data for the heap. - */ -void ph_post_alloc_init(pheap_t *heap, uint max_nodes, pheap_comparator comparator, void *user_data); - -/** - * \brief Define a statically allocated pairing heap. This must be initialized - * by ph_post_alloc_init - * \ingroup util_pheap - */ -#define PHEAP_DEFINE_STATIC(name, _max_nodes) \ - static_assert(_max_nodes && _max_nodes < (1u << (8 * sizeof(pheap_node_id_t))), ""); \ - static pheap_node_t name ## _nodes[_max_nodes]; \ - static pheap_t name = { \ - .nodes = name ## _nodes, \ - .max_nodes = _max_nodes \ - }; - - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/lib/main/pico-sdk/common/pico_util/include/pico/util/queue.h b/lib/main/pico-sdk/common/pico_util/include/pico/util/queue.h deleted file mode 100644 index 998b434dc7..0000000000 --- a/lib/main/pico-sdk/common/pico_util/include/pico/util/queue.h +++ /dev/null @@ -1,227 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _PICO_UTIL_QUEUE_H -#define _PICO_UTIL_QUEUE_H - -#include "pico.h" -#include "hardware/sync.h" - -// PICO_CONFIG: PICO_QUEUE_MAX_LEVEL, Maintain a field for the highest level that has been reached by a queue, type=bool, default=0, advanced=true, group=queue -#ifndef PICO_QUEUE_MAX_LEVEL -#define PICO_QUEUE_MAX_LEVEL 0 -#endif - -/** \file queue.h - * \defgroup queue queue - * \brief Multi-core and IRQ safe queue implementation - * - * Note that this queue stores values of a specified size, and pushed values are copied into the queue - * \ingroup pico_util - */ - -#ifdef __cplusplus -extern "C" { -#endif - -#include "pico/lock_core.h" - -typedef struct { - lock_core_t core; - uint8_t *data; - uint16_t wptr; - uint16_t rptr; - uint16_t element_size; - uint16_t element_count; -#if PICO_QUEUE_MAX_LEVEL - uint16_t max_level; -#endif -} queue_t; - -/*! \brief Initialise a queue with a specific spinlock for concurrency protection - * \ingroup queue - * - * \param q Pointer to a queue_t structure, used as a handle - * \param element_size Size of each value in the queue - * \param element_count Maximum number of entries in the queue - * \param spinlock_num The spin ID used to protect the queue - */ -void queue_init_with_spinlock(queue_t *q, uint element_size, uint element_count, uint spinlock_num); - -/*! \brief Initialise a queue, allocating a (possibly shared) spinlock - * \ingroup queue - * - * \param q Pointer to a queue_t structure, used as a handle - * \param element_size Size of each value in the queue - * \param element_count Maximum number of entries in the queue - */ -static inline void queue_init(queue_t *q, uint element_size, uint element_count) { - queue_init_with_spinlock(q, element_size, element_count, next_striped_spin_lock_num()); -} - -/*! \brief Destroy the specified queue. - * \ingroup queue - * - * \param q Pointer to a queue_t structure, used as a handle - * - * Does not deallocate the queue_t structure itself. - */ -void queue_free(queue_t *q); - -/*! \brief Unsafe check of level of the specified queue. - * \ingroup queue - * - * \param q Pointer to a queue_t structure, used as a handle - * \return Number of entries in the queue - * - * This does not use the spinlock, so may return incorrect results if the - * spin lock is not externally locked - */ -static inline uint queue_get_level_unsafe(queue_t *q) { - int32_t rc = (int32_t)q->wptr - (int32_t)q->rptr; - if (rc < 0) { - rc += q->element_count + 1; - } - return (uint)rc; -} - -/*! \brief Check of level of the specified queue. - * \ingroup queue - * - * \param q Pointer to a queue_t structure, used as a handle - * \return Number of entries in the queue - */ -static inline uint queue_get_level(queue_t *q) { - uint32_t save = spin_lock_blocking(q->core.spin_lock); - uint level = queue_get_level_unsafe(q); - spin_unlock(q->core.spin_lock, save); - return level; -} - -#if PICO_QUEUE_MAX_LEVEL -/*! \brief Returns the highest level reached by the specified queue since it was created - * or since the max level was reset - * \ingroup queue - * - * \param q Pointer to a queue_t structure, used as a handle - * \return Maximum level of the queue - */ -static inline uint queue_get_max_level(queue_t *q) { - return q->max_level; -} -#endif - -#if PICO_QUEUE_MAX_LEVEL -/*! \brief Reset the highest level reached of the specified queue. - * \ingroup queue - * - * \param q Pointer to a queue_t structure, used as a handle - */ -static inline void queue_reset_max_level(queue_t *q) { - uint32_t save = spin_lock_blocking(q->core.spin_lock); - q->max_level = queue_get_level_unsafe(q); - spin_unlock(q->core.spin_lock, save); -} -#endif - -/*! \brief Check if queue is empty - * \ingroup queue - * - * \param q Pointer to a queue_t structure, used as a handle - * \return true if queue is empty, false otherwise - * - * This function is interrupt and multicore safe. - */ -static inline bool queue_is_empty(queue_t *q) { - return queue_get_level(q) == 0; -} - -/*! \brief Check if queue is full - * \ingroup queue - * - * \param q Pointer to a queue_t structure, used as a handle - * \return true if queue is full, false otherwise - * - * This function is interrupt and multicore safe. - */ -static inline bool queue_is_full(queue_t *q) { - return queue_get_level(q) == q->element_count; -} - -// nonblocking queue access functions: - -/*! \brief Non-blocking add value queue if not full - * \ingroup queue - * - * \param q Pointer to a queue_t structure, used as a handle - * \param data Pointer to value to be copied into the queue - * \return true if the value was added - * - * If the queue is full this function will return immediately with false, otherwise - * the data is copied into a new value added to the queue, and this function will return true. - */ -bool queue_try_add(queue_t *q, const void *data); - -/*! \brief Non-blocking removal of entry from the queue if non empty - * \ingroup queue - * - * \param q Pointer to a queue_t structure, used as a handle - * \param data Pointer to the location to receive the removed value, or NULL if the data isn't required - * \return true if a value was removed - * - * If the queue is not empty function will copy the removed value into the location provided and return - * immediately with true, otherwise the function will return immediately with false. - */ -bool queue_try_remove(queue_t *q, void *data); - -/*! \brief Non-blocking peek at the next item to be removed from the queue - * \ingroup queue - * - * \param q Pointer to a queue_t structure, used as a handle - * \param data Pointer to the location to receive the peeked value, or NULL if the data isn't required - * \return true if there was a value to peek - * - * If the queue is not empty this function will return immediately with true with the peeked entry - * copied into the location specified by the data parameter, otherwise the function will return false. - */ -bool queue_try_peek(queue_t *q, void *data); - -// blocking queue access functions: - -/*! \brief Blocking add of value to queue - * \ingroup queue - * - * \param q Pointer to a queue_t structure, used as a handle - * \param data Pointer to value to be copied into the queue - * - * If the queue is full this function will block, until a removal happens on the queue - */ -void queue_add_blocking(queue_t *q, const void *data); - -/*! \brief Blocking remove entry from queue - * \ingroup queue - * - * \param q Pointer to a queue_t structure, used as a handle - * \param data Pointer to the location to receive the removed value, or NULL if the data isn't required - * - * If the queue is empty this function will block until a value is added. - */ -void queue_remove_blocking(queue_t *q, void *data); - -/*! \brief Blocking peek at next value to be removed from queue - * \ingroup queue - * - * \param q Pointer to a queue_t structure, used as a handle - * \param data Pointer to the location to receive the peeked value, or NULL if the data isn't required - * - * If the queue is empty function will block until a value is added - */ -void queue_peek_blocking(queue_t *q, void *data); - -#ifdef __cplusplus -} -#endif -#endif diff --git a/lib/main/pico-sdk/common/pico_util/pheap.c b/lib/main/pico-sdk/common/pico_util/pheap.c deleted file mode 100644 index c7c9575ea8..0000000000 --- a/lib/main/pico-sdk/common/pico_util/pheap.c +++ /dev/null @@ -1,138 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include -#include "pico/util/pheap.h" - -pheap_t *ph_create(uint max_nodes, pheap_comparator comparator, void *user_data) { - invalid_params_if(PHEAP, !max_nodes || max_nodes >= (1u << (8 * sizeof(pheap_node_id_t)))); - pheap_t *heap = calloc(1, sizeof(pheap_t)); - heap->nodes = calloc(max_nodes, sizeof(pheap_node_t)); - ph_post_alloc_init(heap, max_nodes, comparator, user_data); - return heap; -} - -void ph_post_alloc_init(pheap_t *heap, uint max_nodes, pheap_comparator comparator, void *user_data) { - invalid_params_if(PHEAP, !max_nodes || max_nodes >= (1u << (8 * sizeof(pheap_node_id_t)))); - heap->max_nodes = (pheap_node_id_t) max_nodes; - heap->comparator = comparator; - heap->user_data = user_data; - ph_clear(heap); -} - -void ph_clear(pheap_t *heap) { - heap->root_id = 0; - heap->free_head_id = 1; - heap->free_tail_id = heap->max_nodes; - for(pheap_node_id_t i = 1; i < heap->max_nodes; i++) { - ph_get_node(heap, i)->sibling = (pheap_node_id_t)(i + 1); - } - ph_get_node(heap, heap->max_nodes)->sibling = 0; -} - -void ph_destroy(pheap_t *heap) { - free(heap->nodes); - free(heap); -} - -pheap_node_id_t ph_merge_two_pass(pheap_t *heap, pheap_node_id_t id) { - if (!id || !ph_get_node(heap, id)->sibling) { - return id; - } else { - pheap_node_id_t a, b, new_node; - a = id; - b = ph_get_node(heap, id)->sibling; - new_node = ph_get_node(heap, b)->sibling; - ph_get_node(heap, a)->sibling = ph_get_node(heap, b)->sibling = 0; - return ph_merge_nodes(heap, ph_merge_nodes(heap, a, b), ph_merge_two_pass(heap, new_node)); - } -} - -static pheap_node_id_t ph_remove_any_head(pheap_t *heap, pheap_node_id_t root_id, bool free) { - assert(root_id); -// printf("Removing head %d (parent %d sibling %d)\n", root_id, ph_get_node(heap, root_id)->parent, ph_get_node(heap, root_id)->sibling); - assert(!ph_get_node(heap, root_id)->sibling); - assert(!ph_get_node(heap, root_id)->parent); - pheap_node_id_t new_root_id = ph_merge_two_pass(heap, ph_get_node(heap, root_id)->child); - if (free) { - if (heap->free_tail_id) { - ph_get_node(heap, heap->free_tail_id)->sibling = root_id; - } - if (!heap->free_head_id) { - assert(!heap->free_tail_id); - heap->free_head_id = root_id; - } - heap->free_tail_id = root_id; - } - if (new_root_id) ph_get_node(heap, new_root_id)->parent = 0; - ph_get_node(heap, root_id)->sibling = 0; - return new_root_id; -} - -pheap_node_id_t ph_remove_head(pheap_t *heap, bool free) { - pheap_node_id_t old_root_id = ph_peek_head(heap); - heap->root_id = ph_remove_any_head(heap, old_root_id, free); - return old_root_id; -} - -bool ph_remove_and_free_node(pheap_t *heap, pheap_node_id_t id) { - // 1) trivial cases - if (!id) return false; - if (id == heap->root_id) { - ph_remove_and_free_head(heap); - return true; - } - // 2) unlink the node from the tree - pheap_node_t *node = ph_get_node(heap, id); - if (!node->parent) return false; // not in tree - pheap_node_t *parent = ph_get_node(heap, node->parent); - if (parent->child == id) { - parent->child = node->sibling; - } else { - pheap_node_id_t prev_sibling_id = parent->child; - bool __unused found = false; - do { - pheap_node_t *prev_sibling = ph_get_node(heap, prev_sibling_id); - if (prev_sibling->sibling == id) { - prev_sibling->sibling = node->sibling; - found = true; - break; - } - prev_sibling_id = prev_sibling->sibling; - } while (prev_sibling_id); - assert(found); - } - node->sibling = node->parent = 0; -// ph_dump(heap, NULL, NULL); - // 3) remove it from the head of its own subtree - pheap_node_id_t new_sub_tree = ph_remove_any_head(heap, id, true); - assert(new_sub_tree != heap->root_id); - heap->root_id = ph_merge_nodes(heap, heap->root_id, new_sub_tree); - return true; -} - -static uint ph_dump_node(pheap_t *heap, pheap_node_id_t id, void (*dump_key)(pheap_node_id_t, void *), void *user_data, uint indent) { - uint count = 0; - if (id) { - count++; - for (uint i = 0; i < indent * 2; i++) { - putchar(' '); - } - pheap_node_t *node = ph_get_node(heap, id); - printf("%d (c=%d s=%d p=%d) ", id, node->child, node->sibling, node->parent); - if (dump_key) dump_key(id, user_data); - printf("\n"); - count += ph_dump_node(heap, node->child, dump_key, user_data, indent + 1); - count += ph_dump_node(heap, node->sibling, dump_key, user_data, indent); - } - return count; -} - -void ph_dump(pheap_t *heap, void (*dump_key)(pheap_node_id_t, void *), void *user_data) { - uint count = ph_dump_node(heap, heap->root_id, dump_key, user_data, 0); - printf("node_count %d\n", count); -} \ No newline at end of file diff --git a/lib/main/pico-sdk/common/pico_util/queue.c b/lib/main/pico-sdk/common/pico_util/queue.c deleted file mode 100644 index 9209407d5a..0000000000 --- a/lib/main/pico-sdk/common/pico_util/queue.c +++ /dev/null @@ -1,123 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include -#include "pico/util/queue.h" - -void queue_init_with_spinlock(queue_t *q, uint element_size, uint element_count, uint spinlock_num) { - lock_init(&q->core, spinlock_num); - q->data = (uint8_t *)calloc(element_count + 1, element_size); - q->element_count = (uint16_t)element_count; - q->element_size = (uint16_t)element_size; - q->wptr = 0; - q->rptr = 0; -} - -void queue_free(queue_t *q) { - free(q->data); -} - -static inline void *element_ptr(queue_t *q, uint index) { - assert(index <= q->element_count); - return q->data + index * q->element_size; -} - -static inline uint16_t inc_index(queue_t *q, uint16_t index) { - if (++index > q->element_count) { // > because we have element_count + 1 elements - index = 0; - } - -#if PICO_QUEUE_MAX_LEVEL - uint16_t level = queue_get_level_unsafe(q); - if (level > q->max_level) { - q->max_level = level; - } -#endif - - return index; -} - -static bool queue_add_internal(queue_t *q, const void *data, bool block) { - do { - uint32_t save = spin_lock_blocking(q->core.spin_lock); - if (queue_get_level_unsafe(q) != q->element_count) { - memcpy(element_ptr(q, q->wptr), data, q->element_size); - q->wptr = inc_index(q, q->wptr); - lock_internal_spin_unlock_with_notify(&q->core, save); - return true; - } - if (block) { - lock_internal_spin_unlock_with_wait(&q->core, save); - } else { - spin_unlock(q->core.spin_lock, save); - return false; - } - } while (true); -} - -static bool queue_remove_internal(queue_t *q, void *data, bool block) { - do { - uint32_t save = spin_lock_blocking(q->core.spin_lock); - if (queue_get_level_unsafe(q) != 0) { - if (data) { - memcpy(data, element_ptr(q, q->rptr), q->element_size); - } - q->rptr = inc_index(q, q->rptr); - lock_internal_spin_unlock_with_notify(&q->core, save); - return true; - } - if (block) { - lock_internal_spin_unlock_with_wait(&q->core, save); - } else { - spin_unlock(q->core.spin_lock, save); - return false; - } - } while (true); -} - -static bool queue_peek_internal(queue_t *q, void *data, bool block) { - do { - uint32_t save = spin_lock_blocking(q->core.spin_lock); - if (queue_get_level_unsafe(q) != 0) { - if (data) { - memcpy(data, element_ptr(q, q->rptr), q->element_size); - } - lock_internal_spin_unlock_with_notify(&q->core, save); - return true; - } - if (block) { - lock_internal_spin_unlock_with_wait(&q->core, save); - } else { - spin_unlock(q->core.spin_lock, save); - return false; - } - } while (true); -} - -bool queue_try_add(queue_t *q, const void *data) { - return queue_add_internal(q, data, false); -} - -bool queue_try_remove(queue_t *q, void *data) { - return queue_remove_internal(q, data, false); -} - -bool queue_try_peek(queue_t *q, void *data) { - return queue_peek_internal(q, data, false); -} - -void queue_add_blocking(queue_t *q, const void *data) { - queue_add_internal(q, data, true); -} - -void queue_remove_blocking(queue_t *q, void *data) { - queue_remove_internal(q, data, true); -} - -void queue_peek_blocking(queue_t *q, void *data) { - queue_peek_internal(q, data, true); -} diff --git a/lib/main/pico-sdk/host/README.md b/lib/main/pico-sdk/host/README.md deleted file mode 100644 index cc2c1f9f0b..0000000000 --- a/lib/main/pico-sdk/host/README.md +++ /dev/null @@ -1,14 +0,0 @@ -This is a basic set of replacement library implementations sufficient to get simple applications -running on your computer (Raspberry Pi OS, Linux, macOS or Windows using Cygwin or Windows Subsystem for Linux). -It is selected by `PICO_PLATFORM=host` in your CMake build - -This can be extremely useful for testing and debugging higher level application code, or porting code which is not yet small enough -to run on the RP2040 or RP2350 device itself. - -This base level host library provides a minimal environment to compile programs, but is likely sufficient for programs -that don't access hardware directly. - -It is possible however to inject additional SDK library implementations/simulations to provide -more complete functionality. For an example of this see the [pico-host-sdl](https://github.com/raspberrypi/pico-host-sdl) -which uses the SDL2 library to add additional library support for pico_multicore, timers/alarms in pico-time and -pico-audio/pico-scanvideo from [pico-extras](https://github.com/raspberrypi/pico-extras) diff --git a/lib/main/pico-sdk/host/boot_stage2.c b/lib/main/pico-sdk/host/boot_stage2.c deleted file mode 100644 index 704dacc68c..0000000000 --- a/lib/main/pico-sdk/host/boot_stage2.c +++ /dev/null @@ -1,3 +0,0 @@ -int main() { - -} \ No newline at end of file diff --git a/lib/main/pico-sdk/host/hardware_divider/divider.c b/lib/main/pico-sdk/host/hardware_divider/divider.c deleted file mode 100644 index a133179984..0000000000 --- a/lib/main/pico-sdk/host/hardware_divider/divider.c +++ /dev/null @@ -1,9 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "hardware/divider.h" - -__thread uint64_t hw_divider_result_threadlocal; diff --git a/lib/main/pico-sdk/host/hardware_divider/include/hardware/divider.h b/lib/main/pico-sdk/host/hardware_divider/include/hardware/divider.h deleted file mode 100644 index 6e546ea3c4..0000000000 --- a/lib/main/pico-sdk/host/hardware_divider/include/hardware/divider.h +++ /dev/null @@ -1,331 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _HARDWARE_DIVIDER_H -#define _HARDWARE_DIVIDER_H - -#include "pico.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef uint64_t divmod_result_t; - -static inline int __sign_of(int32_t v) { - return v > 0 ? 1 : (v < 0 ? -1 : 0); -} - -/*! \brief Do an unsigned HW divide and wait for result - * \ingroup hardware_divider - * - * Divide \p a by \p b, wait for calculation to complete, return result as a fixed point 32p32 value. - * - * \param a The dividend - * \param b The divisor - * \return Results of divide as a 32p32 fixed point value. - */ -static inline divmod_result_t hw_divider_divmod_u32(uint32_t a, uint32_t b) { - if (!b) return (((uint64_t)a)<<32u) | (uint32_t)(-1); // todo check this - return (((uint64_t)(a%b))<<32u) | (a/b); -} - -/*! \brief Do a signed HW divide and wait for result - * \ingroup hardware_divider - * - * Divide \p a by \p b, wait for calculation to complete, return result as a fixed point 32p32 value. - * - * \param a The dividend - * \param b The divisor - * \return Results of divide as a 32p32 fixed point value. - */ -static inline divmod_result_t hw_divider_divmod_s32(int32_t a, int32_t b) { - if (!b) return (((uint64_t)a)<<32u) | (uint32_t)(-__sign_of(a)); - return (((uint64_t)(a%b))<<32u) | (uint32_t)(a/b); -} - -extern __thread divmod_result_t hw_divider_result_threadlocal; - -/*! \brief Start a signed asynchronous divide - * \ingroup hardware_divider - * - * Start a divide of the specified signed parameters. You should wait for 8 cycles (__div_pause()) or wait for the ready bit to be set - * (hw_divider_wait_ready()) prior to reading the results. - * - * \param a The dividend - * \param b The divisor - */ -static inline void hw_divider_divmod_s32_start(int32_t a, int32_t b) { - hw_divider_result_threadlocal = hw_divider_divmod_s32(a, b); -} - -/*! \brief Start an unsigned asynchronous divide - * \ingroup hardware_divider - * - * Start a divide of the specified unsigned parameters. You should wait for 8 cycles (__div_pause()) or wait for the ready bit to be set - * (hw_divider_wait_ready()) prior to reading the results. - * - * \param a The dividend - * \param b The divisor - */ -static inline void hw_divider_divmod_u32_start(uint32_t a, uint32_t b) { - hw_divider_result_threadlocal = hw_divider_divmod_u32(a, b); -} - -/*! \brief Return result of last asynchronous HW divide - * \ingroup hardware_divider - * - * This function waits for the result to be ready by calling hw_divider_wait_ready(). - * - * \return Current result. Most significant 32 bits are the remainder, lower 32 bits are the quotient. - */ -static inline divmod_result_t hw_divider_result_wait(void) { - return hw_divider_result_threadlocal; -} - -/*! \brief Return result of HW divide, nowait - * \ingroup hardware_divider - * - * \note This is UNSAFE in that the calculation may not have been completed. - * - * \return Current result. Most significant 32 bits are the remainder, lower 32 bits are the quotient. - */ -static inline divmod_result_t hw_divider_result_nowait(void) { - return hw_divider_result_threadlocal; -} - -/*! \brief Wait for a divide to complete - * \ingroup hardware_divider - * - * Wait for a divide to complete - */ -static inline void hw_divider_wait_ready(void) {} - - -/*! \brief Efficient extraction of unsigned quotient from 32p32 fixed point - * \ingroup hardware_divider - * - * \param r 32p32 fixed point value. - * \return Unsigned quotient - */ -inline static uint32_t to_quotient_u32(divmod_result_t r) { - return (uint32_t) r; -} - -/*! \brief Efficient extraction of signed quotient from 32p32 fixed point - * \ingroup hardware_divider - * - * \param r 32p32 fixed point value. - * \return Unsigned quotient - */ -inline static int32_t to_quotient_s32(divmod_result_t r) { - return (int32_t)(uint32_t)r; -} - -/*! \brief Efficient extraction of unsigned remainder from 32p32 fixed point - * \ingroup hardware_divider - * - * \param r 32p32 fixed point value. - * \return Unsigned remainder - * - * \note On Arm this is just a 32 bit register move or a nop - */ -inline static uint32_t to_remainder_u32(divmod_result_t r) { - return (uint32_t)(r >> 32u); -} - -/*! \brief Efficient extraction of signed remainder from 32p32 fixed point - * \ingroup hardware_divider - * - * \param r 32p32 fixed point value. - * \return Signed remainder - * - * \note On arm this is just a 32 bit register move or a nop - */ -inline static int32_t to_remainder_s32(divmod_result_t r) { - return (int32_t)(r >> 32u); -} - -static inline void hw_divider_pause(void) {} - -/*! \brief Do an unsigned HW divide, wait for result, return quotient - * \ingroup hardware_divider - * - * Divide \p a by \p b, wait for calculation to complete, return quotient. - * - * \param a The dividend - * \param b The divisor - * \return Quotient results of the divide - */ -static inline uint32_t hw_divider_u32_quotient(uint32_t a, uint32_t b) { - return b ? (a / b) : (uint32_t)(-1); -} - -/*! \brief Do an unsigned HW divide, wait for result, return remainder - * \ingroup hardware_divider - * - * Divide \p a by \p b, wait for calculation to complete, return remainder. - * - * \param a The dividend - * \param b The divisor - * \return Remainder results of the divide - */ -static inline uint32_t hw_divider_u32_remainder(uint32_t a, uint32_t b) { - return b ? (a % b) : a; -} - -/*! \brief Do a signed HW divide, wait for result, return quotient - * \ingroup hardware_divider - * - * Divide \p a by \p b, wait for calculation to complete, return quotient. - * - * \param a The dividend - * \param b The divisor - * \return Quotient results of the divide - */ -static inline int32_t hw_divider_quotient_s32(int32_t a, int32_t b) { - return to_quotient_s32(hw_divider_divmod_s32(a, b)); -} - -/*! \brief Do a signed HW divide, wait for result, return remainder - * \ingroup hardware_divider - * - * Divide \p a by \p b, wait for calculation to complete, return remainder. - * - * \param a The dividend - * \param b The divisor - * \return Remainder results of the divide - */ -static inline int32_t hw_divider_remainder_s32(int32_t a, int32_t b) { - return b ? (a % b) : a; -} - -/*! \brief Return result of last asynchronous HW divide, unsigned quotient only - * \ingroup hardware_divider - * - * This function waits for the result to be ready by calling hw_divider_wait_ready(). - * - * \return Current unsigned quotient result. - */ -static inline uint32_t hw_divider_u32_quotient_wait(void) { - return to_quotient_u32(hw_divider_result_wait()); -} - -/*! \brief Return result of last asynchronous HW divide, signed quotient only - * \ingroup hardware_divider - * - * This function waits for the result to be ready by calling hw_divider_wait_ready(). - * - * \return Current signed quotient result. - */ -static inline int32_t hw_divider_s32_quotient_wait(void) { - return to_remainder_u32(hw_divider_result_wait()); -} - -/*! \brief Return result of last asynchronous HW divide, unsigned remainder only - * \ingroup hardware_divider - * - * This function waits for the result to be ready by calling hw_divider_wait_ready(). - * - * \return Current unsigned remainder result. - */ -static inline uint32_t hw_divider_u32_remainder_wait(void) { - return to_quotient_s32(hw_divider_result_wait()); -} - -/*! \brief Return result of last asynchronous HW divide, signed remainder only - * \ingroup hardware_divider - * - * This function waits for the result to be ready by calling hw_divider_wait_ready(). - * - * \return Current remainder results. - */ -static inline int32_t hw_divider_s32_remainder_wait(void) { - return to_remainder_s32(hw_divider_result_wait()); -} - -/*! \brief Do a hardware unsigned HW divide, wait for result, return quotient - * \ingroup hardware_divider - * - * Divide \p a by \p b, wait for calculation to complete, return quotient. - * - * \param a The dividend - * \param b The divisor - * \return Quotient result of the divide - */ -static inline uint32_t hw_divider_u32_quotient_inlined(uint32_t a, uint32_t b) { - return hw_divider_u32_quotient(a,b); -} - -/*! \brief Do a hardware unsigned HW divide, wait for result, return remainder - * \ingroup hardware_divider - * - * Divide \p a by \p b, wait for calculation to complete, return remainder. - * - * \param a The dividend - * \param b The divisor - * \return Remainder result of the divide - */ -static inline uint32_t hw_divider_u32_remainder_inlined(uint32_t a, uint32_t b) { - return hw_divider_u32_remainder(a,b); -} - -/*! \brief Do a hardware signed HW divide, wait for result, return quotient - * \ingroup hardware_divider - * - * Divide \p a by \p b, wait for calculation to complete, return quotient. - * - * \param a The dividend - * \param b The divisor - * \return Quotient result of the divide - */ -static inline int32_t hw_divider_s32_quotient_inlined(int32_t a, int32_t b) { - return hw_divider_quotient_s32(a,b); -} - -/*! \brief Do a hardware signed HW divide, wait for result, return remainder - * \ingroup hardware_divider - * - * Divide \p a by \p b, wait for calculation to complete, return remainder. - * - * \param a The dividend - * \param b The divisor - * \return Remainder result of the divide - */ -static inline int32_t hw_divider_s32_remainder_inlined(int32_t a, int32_t b) { - return hw_divider_remainder_s32(a,b); -} - -typedef uint64_t hw_divider_state_t; - -/*! \brief Save the calling cores hardware divider state - * \ingroup hardware_divider - * - * Copy the current core's hardware divider state into the provided structure. This method - * waits for the divider results to be stable, then copies them to memory. - * They can be restored via hw_divider_restore_state() - * - * \param dest the location to store the divider state - */ - static inline void hw_divider_save_state(hw_divider_state_t *dest) { - *dest = hw_divider_result_threadlocal; -} - -/*! \brief Load a saved hardware divider state into the current core's hardware divider - * \ingroup hardware_divider - * - * Copy the passed hardware divider state into the hardware divider. - * - * \param src the location to load the divider state from - */ - static inline void hw_divider_restore_state(hw_divider_state_t *src) { - hw_divider_result_threadlocal = *src; -} - -#ifdef __cplusplus -} -#endif -#endif // _HARDWARE_DIVIDER_H diff --git a/lib/main/pico-sdk/host/hardware_gpio/gpio.c b/lib/main/pico-sdk/host/hardware_gpio/gpio.c deleted file mode 100644 index 1cbcbed309..0000000000 --- a/lib/main/pico-sdk/host/hardware_gpio/gpio.c +++ /dev/null @@ -1,147 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "hardware/gpio.h" - -// todo weak or replace? probably weak -void gpio_set_function(uint gpio, enum gpio_function fn) { - -} - -void gpio_pull_up(uint gpio) { - -} - -void gpio_pull_down(uint gpio) { - -} - -void gpio_disable_pulls(uint gpio) { - -} - -void gpio_set_pulls(uint gpio, bool up, bool down) { - -} - -void gpio_set_irqover(uint gpio, uint value) { - -} - -void gpio_set_outover(uint gpio, uint value) { - -} - -void gpio_set_inover(uint gpio, uint value) { - -} - -void gpio_set_oeover(uint gpio, uint value) { - -} - -void gpio_set_input_hysteresis_enabled(uint gpio, bool enabled){ - -} - -bool gpio_is_input_hysteresis_enabled(uint gpio){ - return true; -} - -void gpio_set_slew_rate(uint gpio, enum gpio_slew_rate slew){ - -} - -enum gpio_slew_rate gpio_get_slew_rate(uint gpio){ - return GPIO_SLEW_RATE_FAST; -} - -void gpio_set_drive_strength(uint gpio, enum gpio_drive_strength drive){ - -} - -enum gpio_drive_strength gpio_get_drive_strength(uint gpio){ - return GPIO_DRIVE_STRENGTH_4MA; -} - - -void gpio_set_irq_enabled(uint gpio, uint32_t events, bool enable) { - -} - -void gpio_acknowledge_irq(uint gpio, uint32_t events) { - -} - -void gpio_init(uint gpio) { - -} - -PICO_WEAK_FUNCTION_DEF(gpio_get) - -bool PICO_WEAK_FUNCTION_IMPL_NAME(gpio_get)(uint gpio) { - return 0; -} - -uint32_t gpio_get_all() { - return 0; -} - -void gpio_set_mask(uint32_t mask) { - -} - -void gpio_clr_mask(uint32_t mask) { - -} - -void gpio_xor_mask(uint32_t mask) { - -} - -void gpio_put_masked(uint32_t mask, uint32_t value) { - -} - -void gpio_put_all(uint32_t value) { - -} - -void gpio_put(uint gpio, int value) { - -} - -void gpio_set_dir_out_masked(uint32_t mask) { - -} - -void gpio_set_dir_in_masked(uint32_t mask) { - -} - -void gpio_set_dir_masked(uint32_t mask, uint32_t value) { - -} - -void gpio_set_dir_all_bits(uint32_t value) { - -} - -void gpio_set_dir(uint gpio, bool out) { - -} - -void gpio_debug_pins_init() { - -} - -void gpio_set_input_enabled(uint gpio, bool enable) { - -} - -void gpio_init_mask(uint gpio_mask) { - -} diff --git a/lib/main/pico-sdk/host/hardware_gpio/include/hardware/gpio.h b/lib/main/pico-sdk/host/hardware_gpio/include/hardware/gpio.h deleted file mode 100644 index 592a562af8..0000000000 --- a/lib/main/pico-sdk/host/hardware_gpio/include/hardware/gpio.h +++ /dev/null @@ -1,172 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _HARDWARE_GPIO_H -#define _HARDWARE_GPIO_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include "pico.h" - -enum gpio_function { - GPIO_FUNC_XIP = 0, - GPIO_FUNC_SPI = 1, - GPIO_FUNC_UART = 2, - GPIO_FUNC_I2C = 3, - GPIO_FUNC_PWM = 4, - GPIO_FUNC_SIO = 5, - GPIO_FUNC_PIO0 = 6, - GPIO_FUNC_PIO1 = 7, - GPIO_FUNC_GPCK = 8, - GPIO_FUNC_USB = 9, - GPIO_FUNC_NULL = 0xf, -}; - -enum gpio_slew_rate { - GPIO_SLEW_RATE_SLOW = 0, ///< Slew rate limiting enabled - GPIO_SLEW_RATE_FAST = 1 ///< Slew rate limiting disabled -}; - -enum gpio_drive_strength { - GPIO_DRIVE_STRENGTH_2MA = 0, ///< 2 mA nominal drive strength - GPIO_DRIVE_STRENGTH_4MA = 1, ///< 4 mA nominal drive strength - GPIO_DRIVE_STRENGTH_8MA = 2, ///< 8 mA nominal drive strength - GPIO_DRIVE_STRENGTH_12MA = 3 ///< 12 mA nominal drive strength -}; - -#define GPIO_OUT 1 -#define GPIO_IN 0 - -// ---------------------------------------------------------------------------- -// Pad Controls + IO Muxing -// ---------------------------------------------------------------------------- -// Declarations for gpio.c - -void gpio_set_function(uint gpio, enum gpio_function fn); - -enum gpio_function gpio_get_function(uint gpio); - -void gpio_pull_up(uint gpio); - -void gpio_pull_down(uint gpio); - -void gpio_disable_pulls(uint gpio); - -void gpio_set_pulls(uint gpio, bool up, bool down); - -void gpio_set_irqover(uint gpio, uint value); - -void gpio_set_outover(uint gpio, uint value); - -void gpio_set_inover(uint gpio, uint value); - -void gpio_set_oeover(uint gpio, uint value); - -void gpio_set_input_enabled(uint gpio, bool enable); - -void gpio_set_input_hysteresis_enabled(uint gpio, bool enabled); - -bool gpio_is_input_hysteresis_enabled(uint gpio); - -void gpio_set_slew_rate(uint gpio, enum gpio_slew_rate slew); - -enum gpio_slew_rate gpio_get_slew_rate(uint gpio); - -void gpio_set_drive_strength(uint gpio, enum gpio_drive_strength drive); - -enum gpio_drive_strength gpio_get_drive_strength(uint gpio); - -// Configure a GPIO for direct input/output from software -void gpio_init(uint gpio); - -void gpio_init_mask(uint gpio_mask); - -// ---------------------------------------------------------------------------- -// Input -// ---------------------------------------------------------------------------- - -// Get the value of a single GPIO -bool gpio_get(uint gpio); - -// Get raw value of all -uint32_t gpio_get_all(); - -// ---------------------------------------------------------------------------- -// Output -// ---------------------------------------------------------------------------- - -// Drive high every GPIO appearing in mask -void gpio_set_mask(uint32_t mask); - -void gpio_clr_mask(uint32_t mask); - -// Toggle every GPIO appearing in mask -void gpio_xor_mask(uint32_t mask); - - -// For each 1 bit in "mask", drive that pin to the value given by -// corresponding bit in "value", leaving other pins unchanged. -// Since this uses the TOGL alias, it is concurrency-safe with e.g. an IRQ -// bashing different pins from the same core. -void gpio_put_masked(uint32_t mask, uint32_t value); - -// Drive all pins simultaneously -void gpio_put_all(uint32_t value); - - -// Drive a single GPIO high/low -void gpio_put(uint gpio, int value); - -// ---------------------------------------------------------------------------- -// Direction -// ---------------------------------------------------------------------------- - -// Switch all GPIOs in "mask" to output -void gpio_set_dir_out_masked(uint32_t mask); - -// Switch all GPIOs in "mask" to input -void gpio_set_dir_in_masked(uint32_t mask); - -// For each 1 bit in "mask", switch that pin to the direction given by -// corresponding bit in "value", leaving other pins unchanged. -// E.g. gpio_set_dir_masked(0x3, 0x2); -> set pin 0 to input, pin 1 to output, -// simultaneously. -void gpio_set_dir_masked(uint32_t mask, uint32_t value); - -// Set direction of all pins simultaneously. -// For each bit in value, -// 1 = out -// 0 = in -void gpio_set_dir_all_bits(uint32_t value); - -// Set a single GPIO to input/output. -// true = out -// 0 = in -void gpio_set_dir(uint gpio, bool out); - -// debugging -#ifndef PICO_DEBUG_PIN_BASE -#define PICO_DEBUG_PIN_BASE 19u -#endif - -// note these two macros may only be used once per compilation unit -#define CU_REGISTER_DEBUG_PINS(p, ...) -#define CU_SELECT_DEBUG_PINS(x) -#define DEBUG_PINS_ENABLED(p) false - -#define DEBUG_PINS_SET(p, v) ((void)0) -#define DEBUG_PINS_CLR(p, v) ((void)0) -#define DEBUG_PINS_XOR(p, v) ((void)0) - -void gpio_debug_pins_init(); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/lib/main/pico-sdk/host/hardware_irq/include/hardware/irq.h b/lib/main/pico-sdk/host/hardware_irq/include/hardware/irq.h deleted file mode 100644 index 0e881b7a7b..0000000000 --- a/lib/main/pico-sdk/host/hardware_irq/include/hardware/irq.h +++ /dev/null @@ -1,381 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _HARDWARE_IRQ_H -#define _HARDWARE_IRQ_H - -// These two config items are also used by assembler, so keeping separate -// PICO_CONFIG: PICO_MAX_SHARED_IRQ_HANDLERS, Maximum number of shared IRQ handlers, default=4, advanced=true, group=hardware_irq -#ifndef PICO_MAX_SHARED_IRQ_HANDLERS -#define PICO_MAX_SHARED_IRQ_HANDLERS 4 -#endif - -// PICO_CONFIG: PICO_DISABLE_SHARED_IRQ_HANDLERS, Disable shared IRQ handlers, type=bool, default=0, group=hardware_irq -#ifndef PICO_DISABLE_SHARED_IRQ_HANDLERS -#define PICO_DISABLE_SHARED_IRQ_HANDLERS 0 -#endif - -// PICO_CONFIG: PICO_VTABLE_PER_CORE, User is using separate vector tables per core, type=bool, default=0, group=hardware_irq -#ifndef PICO_VTABLE_PER_CORE -#define PICO_VTABLE_PER_CORE 0 -#endif - -#include "pico.h" -#include "hardware/regs/intctrl.h" - -/** \file irq.h - * \defgroup hardware_irq hardware_irq - * - * \brief Hardware interrupt handling - * - * The RP2040 uses the standard ARM nested vectored interrupt controller (NVIC). - * - * Interrupts are identified by a number from 0 to 31. - * - * On the RP2040, only the lower 26 IRQ signals are connected on the NVIC; IRQs 26 to 31 are tied to zero (never firing). - * - * There is one NVIC per core, and each core's NVIC has the same hardware interrupt lines routed to it, with the exception of the IO interrupts - * where there is one IO interrupt per bank, per core. These are completely independent, so, for example, processor 0 can be - * interrupted by GPIO 0 in bank 0, and processor 1 by GPIO 1 in the same bank. - * - * \note That all IRQ APIs affect the executing core only (i.e. the core calling the function). - * - * \note You should not enable the same (shared) IRQ number on both cores, as this will lead to race conditions - * or starvation of one of the cores. Additionally, don't forget that disabling interrupts on one core does not disable interrupts - * on the other core. - * - * There are three different ways to set handlers for an IRQ: - * - Calling irq_add_shared_handler() at runtime to add a handler for a multiplexed interrupt (e.g. GPIO bank) on the current core. Each handler, should check and clear the relevant hardware interrupt source - * - Calling irq_set_exclusive_handler() at runtime to install a single handler for the interrupt on the current core - * - Defining the interrupt handler explicitly in your application (e.g. by defining void `isr_dma_0` will make that function the handler for the DMA_IRQ_0 on core 0, and - * you will not be able to change it using the above APIs at runtime). Using this method can cause link conflicts at runtime, and offers no runtime performance benefit (i.e, it should not generally be used). - * - * \note If an IRQ is enabled and fires with no handler installed, a breakpoint will be hit and the IRQ number will - * be in register r0. - * - * \section interrupt_nums Interrupt Numbers - * - * Interrupts are numbered as follows, a set of defines is available (intctrl.h) with these names to avoid using the numbers directly. - * - * IRQ | Interrupt Source - * ----|----------------- - * 0 | TIMER_IRQ_0 - * 1 | TIMER_IRQ_1 - * 2 | TIMER_IRQ_2 - * 3 | TIMER_IRQ_3 - * 4 | PWM_IRQ_WRAP - * 5 | USBCTRL_IRQ - * 6 | XIP_IRQ - * 7 | PIO0_IRQ_0 - * 8 | PIO0_IRQ_1 - * 9 | PIO1_IRQ_0 - * 10 | PIO1_IRQ_1 - * 11 | DMA_IRQ_0 - * 12 | DMA_IRQ_1 - * 13 | IO_IRQ_BANK0 - * 14 | IO_IRQ_QSPI - * 15 | SIO_IRQ_PROC0 - * 16 | SIO_IRQ_PROC1 - * 17 | CLOCKS_IRQ - * 18 | SPI0_IRQ - * 19 | SPI1_IRQ - * 20 | UART0_IRQ - * 21 | UART1_IRQ - * 22 | ADC0_IRQ_FIFO - * 23 | I2C0_IRQ - * 24 | I2C1_IRQ - * 25 | RTC_IRQ - * - */ - -// PICO_CONFIG: PICO_DEFAULT_IRQ_PRIORITY, Define the default IRQ priority, default=0x80, group=hardware_irq -#ifndef PICO_DEFAULT_IRQ_PRIORITY -#define PICO_DEFAULT_IRQ_PRIORITY 0x80 -#endif - -#define PICO_LOWEST_IRQ_PRIORITY 0xff -#define PICO_HIGHEST_IRQ_PRIORITY 0x00 - -// PICO_CONFIG: PICO_SHARED_IRQ_HANDLER_DEFAULT_ORDER_PRIORITY, Set default shared IRQ order priority, default=0x80, group=hardware_irq -#ifndef PICO_SHARED_IRQ_HANDLER_DEFAULT_ORDER_PRIORITY -#define PICO_SHARED_IRQ_HANDLER_DEFAULT_ORDER_PRIORITY 0x80 -#endif - -#define PICO_SHARED_IRQ_HANDLER_HIGHEST_ORDER_PRIORITY 0xff -#define PICO_SHARED_IRQ_HANDLER_LOWEST_ORDER_PRIORITY 0x00 - -// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_HARDWARE_IRQ, Enable/disable assertions in the hardware_irq module, type=bool, default=0, group=hardware_irq -#ifndef PARAM_ASSERTIONS_ENABLED_HARDWARE_IRQ -#ifdef PARAM_ASSERTIONS_ENABLED_IRQ // backwards compatibility with SDK < 2.0.0 -#define PARAM_ASSERTIONS_ENABLED_HARDWARE_IRQ PARAM_ASSERTIONS_ENABLED_IRQ -#else -#define PARAM_ASSERTIONS_ENABLED_HARDWARE_IRQ 0 -#endif -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -/*! \brief Interrupt handler function type - * \ingroup hardware_irq - * - * All interrupts handlers should be of this type, and follow normal ARM EABI register saving conventions - */ -typedef void (*irq_handler_t)(void); - -static inline void check_irq_param(__unused uint num) { - invalid_params_if(HARDWARE_IRQ, num >= NUM_IRQS); -} - -/*! \brief Set specified interrupt's priority - * \ingroup hardware_irq - * - * \param num Interrupt number \ref interrupt_nums - * \param hardware_priority Priority to set. - * Numerically-lower values indicate a higher priority. Hardware priorities - * range from 0 (highest priority) to 255 (lowest priority) though only the - * top 2 bits are significant on ARM Cortex-M0+. To make it easier to specify - * higher or lower priorities than the default, all IRQ priorities are - * initialized to PICO_DEFAULT_IRQ_PRIORITY by the SDK runtime at startup. - * PICO_DEFAULT_IRQ_PRIORITY defaults to 0x80 - */ -void irq_set_priority(uint num, uint8_t hardware_priority); - -/*! \brief Get specified interrupt's priority - * \ingroup hardware_irq - * - * Numerically-lower values indicate a higher priority. Hardware priorities - * range from 0 (highest priority) to 255 (lowest priority) though only the - * top 2 bits are significant on ARM Cortex-M0+. To make it easier to specify - * higher or lower priorities than the default, all IRQ priorities are - * initialized to PICO_DEFAULT_IRQ_PRIORITY by the SDK runtime at startup. - * PICO_DEFAULT_IRQ_PRIORITY defaults to 0x80 - * - * \param num Interrupt number \ref interrupt_nums - * \return the IRQ priority - */ -uint irq_get_priority(uint num); - -/*! \brief Enable or disable a specific interrupt on the executing core - * \ingroup hardware_irq - * - * \param num Interrupt number \ref interrupt_nums - * \param enabled true to enable the interrupt, false to disable - */ -void irq_set_enabled(uint num, bool enabled); - -/*! \brief Determine if a specific interrupt is enabled on the executing core - * \ingroup hardware_irq - * - * \param num Interrupt number \ref interrupt_nums - * \return true if the interrupt is enabled - */ -bool irq_is_enabled(uint num); - -/*! \brief Enable/disable multiple interrupts on the executing core - * \ingroup hardware_irq - * - * \param mask 32-bit mask with one bits set for the interrupts to enable/disable \ref interrupt_nums - * \param enabled true to enable the interrupts, false to disable them. - */ -void irq_set_mask_enabled(uint32_t mask, bool enabled); - -/*! \brief Enable/disable multiple interrupts on the executing core - * \ingroup hardware_irq - * - * \param n the index of the mask to update. n == 0 means 0->31, n == 1 mean 32->63 etc. - * \param mask 32-bit mask with one bits set for the interrupts to enable/disable \ref interrupt_nums - * \param enabled true to enable the interrupts, false to disable them. - */ -void irq_set_mask_n_enabled(uint n, uint32_t mask, bool enabled); - -/*! \brief Set an exclusive interrupt handler for an interrupt on the executing core. - * \ingroup hardware_irq - * - * Use this method to set a handler for single IRQ source interrupts, or when - * your code, use case or performance requirements dictate that there should - * no other handlers for the interrupt. - * - * This method will assert if there is already any sort of interrupt handler installed - * for the specified irq number. - * - * \param num Interrupt number \ref interrupt_nums - * \param handler The handler to set. See \ref irq_handler_t - * \see irq_add_shared_handler() - */ -void irq_set_exclusive_handler(uint num, irq_handler_t handler); - -/*! \brief Get the exclusive interrupt handler for an interrupt on the executing core. - * \ingroup hardware_irq - * - * This method will return an exclusive IRQ handler set on this core - * by irq_set_exclusive_handler if there is one. - * - * \param num Interrupt number \ref interrupt_nums - * \see irq_set_exclusive_handler() - * \return handler The handler if an exclusive handler is set for the IRQ, - * NULL if no handler is set or shared/shareable handlers are installed - */ -irq_handler_t irq_get_exclusive_handler(uint num); - -/*! \brief Add a shared interrupt handler for an interrupt on the executing core - * \ingroup hardware_irq - * - * Use this method to add a handler on an irq number shared between multiple distinct hardware sources (e.g. GPIO, DMA or PIO IRQs). - * Handlers added by this method will all be called in sequence from highest order_priority to lowest. The - * irq_set_exclusive_handler() method should be used instead if you know there will or should only ever be one handler for the interrupt. - * - * This method will assert if there is an exclusive interrupt handler set for this irq number on this core, or if - * the (total across all IRQs on both cores) maximum (configurable via PICO_MAX_SHARED_IRQ_HANDLERS) number of shared handlers - * would be exceeded. - * - * \param num Interrupt number \ref interrupt_nums - * \param handler The handler to set. See \ref irq_handler_t - * \param order_priority The order priority controls the order that handlers for the same IRQ number on the core are called. - * The shared irq handlers for an interrupt are all called when an IRQ fires, however the order of the calls is based - * on the order_priority (higher priorities are called first, identical priorities are called in undefined order). A good - * rule of thumb is to use PICO_SHARED_IRQ_HANDLER_DEFAULT_ORDER_PRIORITY if you don't much care, as it is in the middle of - * the priority range by default. - * - * \note The order_priority uses \em higher values for higher priorities which is the \em opposite of the CPU interrupt priorities passed - * to irq_set_priority() which use lower values for higher priorities. - * - * \see irq_set_exclusive_handler() - */ -void irq_add_shared_handler(uint num, irq_handler_t handler, uint8_t order_priority); - -/*! \brief Remove a specific interrupt handler for the given irq number on the executing core - * \ingroup hardware_irq - * - * This method may be used to remove an irq set via either irq_set_exclusive_handler() or - * irq_add_shared_handler(), and will assert if the handler is not currently installed for the given - * IRQ number - * - * \note This method may *only* be called from user (non IRQ code) or from within the handler - * itself (i.e. an IRQ handler may remove itself as part of handling the IRQ). Attempts to call - * from another IRQ will cause an assertion. - * - * \param num Interrupt number \ref interrupt_nums - * \param handler The handler to removed. - * \see irq_set_exclusive_handler() - * \see irq_add_shared_handler() - */ -void irq_remove_handler(uint num, irq_handler_t handler); - -/*! \brief Determine if the current handler for the given number is shared - * \ingroup hardware_irq - * - * \param num Interrupt number \ref interrupt_nums - * \return true if the specified IRQ has a shared handler - */ -bool irq_has_shared_handler(uint num); - -/*! \brief Get the current IRQ handler for the specified IRQ from the currently installed hardware vector table (VTOR) - * of the execution core - * \ingroup hardware_irq - * - * \param num Interrupt number \ref interrupt_nums - * \return the address stored in the VTABLE for the given irq number - */ -irq_handler_t irq_get_vtable_handler(uint num); - -/*! \brief Clear a specific interrupt on the executing core - * \ingroup hardware_irq - * - * This method is only useful for "software" IRQs that are not connected to hardware (i.e. IRQs 26-31) - * as the the NVIC always reflects the current state of the IRQ state of the hardware for hardware IRQs, and clearing - * of the IRQ state of the hardware is performed via the hardware's registers instead. - * - * \param int_num Interrupt number \ref interrupt_nums - */ -void irq_clear(uint int_num); - -/*! \brief Force an interrupt to be pending on the executing core - * \ingroup hardware_irq - * - * This should generally not be used for IRQs connected to hardware. - * - * \param num Interrupt number \ref interrupt_nums - */ -void irq_set_pending(uint num); - - -/*! \brief Perform IRQ priority initialization for the current core - * - * \note This is an internal method and user should generally not call it. - */ -void irq_init_priorities(void); - -/*! \brief Claim ownership of a user IRQ on the calling core - * \ingroup hardware_irq - * - * User IRQs are numbered 26-31 and are not connected to any hardware, but can be triggered by \ref irq_set_pending. - * - * \note User IRQs are a core local feature; they cannot be used to communicate between cores. Therefore all functions - * dealing with Uer IRQs affect only the calling core - * - * This method explicitly claims ownership of a user IRQ, so other code can know it is being used. - * - * \param irq_num the user IRQ to claim - */ -void user_irq_claim(uint irq_num); - -/*! \brief Mark a user IRQ as no longer used on the calling core - * \ingroup hardware_irq - * - * User IRQs are numbered 26-31 and are not connected to any hardware, but can be triggered by \ref irq_set_pending. - * - * \note User IRQs are a core local feature; they cannot be used to communicate between cores. Therefore all functions - * dealing with Uer IRQs affect only the calling core - * - * This method explicitly releases ownership of a user IRQ, so other code can know it is free to use. - * - * \note it is customary to have disabled the irq and removed the handler prior to calling this method. - * - * \param irq_num the irq irq_num to unclaim - */ -void user_irq_unclaim(uint irq_num); - -/*! \brief Claim ownership of a free user IRQ on the calling core - * \ingroup hardware_irq - * - * User IRQs are numbered 26-31 and are not connected to any hardware, but can be triggered by \ref irq_set_pending. - * - * \note User IRQs are a core local feature; they cannot be used to communicate between cores. Therefore all functions - * dealing with Uer IRQs affect only the calling core - * - * This method explicitly claims ownership of an unused user IRQ if there is one, so other code can know it is being used. - * - * \param required if true the function will panic if none are available - * \return the user IRQ number or -1 if required was false, and none were free - */ -int user_irq_claim_unused(bool required); - -/* -*! \brief Check if a user IRQ is in use on the calling core - * \ingroup hardware_irq - * - * User IRQs are numbered 26-31 and are not connected to any hardware, but can be triggered by \ref irq_set_pending. - * - * \note User IRQs are a core local feature; they cannot be used to communicate between cores. Therefore all functions - * dealing with Uer IRQs affect only the calling core - * - * \param irq_num the irq irq_num - * \return true if the irq_num is claimed, false otherwise - * \sa user_irq_claim - * \sa user_irq_unclaim - * \sa user_irq_claim_unused - */ -bool user_irq_is_claimed(uint irq_num); - -void __unhandled_user_irq(void); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/lib/main/pico-sdk/host/hardware_irq/irq.c b/lib/main/pico-sdk/host/hardware_irq/irq.c deleted file mode 100644 index ad793c19d1..0000000000 --- a/lib/main/pico-sdk/host/hardware_irq/irq.c +++ /dev/null @@ -1,125 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "hardware/irq.h" -#include "hardware/claim.h" - -// totally non-functional IRQ - -#if PICO_VTABLE_PER_CORE -static uint8_t user_irq_claimed[NUM_CORES]; -static inline uint8_t *user_irq_claimed_ptr(void) { - return &user_irq_claimed[get_core_num()]; -} -#else -static uint8_t user_irq_claimed; -static inline uint8_t *user_irq_claimed_ptr(void) { - return &user_irq_claimed; -} -#endif - -PICO_WEAK_FUNCTION_DEF(irq_set_enabled) -void PICO_WEAK_FUNCTION_IMPL_NAME(irq_set_enabled)(uint num, bool enabled) { - panic_unsupported(); -} - -PICO_WEAK_FUNCTION_DEF(irq_is_enabled) -bool PICO_WEAK_FUNCTION_IMPL_NAME(irq_is_enabled)(uint num) { - return false; -} - -PICO_WEAK_FUNCTION_DEF(irq_set_mask_enabled) -void PICO_WEAK_FUNCTION_IMPL_NAME(irq_set_mask_enabled)(uint32_t mask, bool enabled) { - panic_unsupported(); -} - -PICO_WEAK_FUNCTION_DEF(irq_set_mask_n_enabled) -void PICO_WEAK_FUNCTION_IMPL_NAME(irq_set_mask_n_enabled)(uint n, uint32_t mask, bool enabled) { - panic_unsupported(); -} - -PICO_WEAK_FUNCTION_DEF(irq_set_pending) -void PICO_WEAK_FUNCTION_IMPL_NAME(irq_set_pending)(uint num) { - panic_unsupported(); -} - -PICO_WEAK_FUNCTION_DEF(irq_has_shared_handler) -bool PICO_WEAK_FUNCTION_IMPL_NAME(irq_has_shared_handler)(uint irq_num) { - return false; -} - -PICO_WEAK_FUNCTION_DEF(irq_get_vtable_handler) -irq_handler_t PICO_WEAK_FUNCTION_IMPL_NAME(irq_get_vtable_handler)(uint num) { - panic_unsupported(); -} - -PICO_WEAK_FUNCTION_DEF(irq_set_exclusive_handler) -void PICO_WEAK_FUNCTION_IMPL_NAME(irq_set_exclusive_handler)(uint num, irq_handler_t handler) { - panic_unsupported(); -} - -PICO_WEAK_FUNCTION_DEF(irq_get_exclusive_handler) -irq_handler_t PICO_WEAK_FUNCTION_IMPL_NAME(irq_get_exclusive_handler)(uint num) { - panic_unsupported(); -} - -PICO_WEAK_FUNCTION_DEF(irq_add_shared_handler) -void PICO_WEAK_FUNCTION_IMPL_NAME(irq_add_shared_handler)(uint num, irq_handler_t handler, uint8_t order_priority) { - panic_unsupported(); -} - -PICO_WEAK_FUNCTION_DEF(irq_remove_handler) -void PICO_WEAK_FUNCTION_IMPL_NAME(irq_remove_handler)(uint num, irq_handler_t handler) { - panic_unsupported(); -} - -PICO_WEAK_FUNCTION_DEF(irq_set_priority) -void PICO_WEAK_FUNCTION_IMPL_NAME(irq_set_priority)(uint num, uint8_t hardware_priority) { - panic_unsupported(); -} - -PICO_WEAK_FUNCTION_DEF(irq_get_priority) -uint PICO_WEAK_FUNCTION_IMPL_NAME(irq_get_priority)(uint num) { - panic_unsupported(); -} - -PICO_WEAK_FUNCTION_DEF(irq_clear) -void PICO_WEAK_FUNCTION_IMPL_NAME(irq_clear)(uint int_num) { - panic_unsupported(); -} - -PICO_WEAK_FUNCTION_DEF(irq_init_priorities) -void PICO_WEAK_FUNCTION_IMPL_NAME(irq_init_priorities)() { -} - -static uint get_user_irq_claim_index(uint irq_num) { - invalid_params_if(HARDWARE_IRQ, irq_num < FIRST_USER_IRQ || irq_num >= NUM_IRQS); - // we count backwards from the last, to match the existing hard coded uses of user IRQs in the SDK which were previously using 31 - static_assert(NUM_IRQS - FIRST_USER_IRQ <= 8, ""); // we only use a single byte's worth of claim bits today. - return NUM_IRQS - irq_num - 1u; -} - -PICO_WEAK_FUNCTION_DEF(user_irq_claim) -void PICO_WEAK_FUNCTION_IMPL_NAME(user_irq_claim)(uint irq_num) { - hw_claim_or_assert(user_irq_claimed_ptr(), get_user_irq_claim_index(irq_num), "User IRQ is already claimed"); -} - -PICO_WEAK_FUNCTION_DEF(user_irq_unclaim) -void PICO_WEAK_FUNCTION_IMPL_NAME(user_irq_unclaim)(uint irq_num) { - hw_claim_clear(user_irq_claimed_ptr(), get_user_irq_claim_index(irq_num)); -} - -PICO_WEAK_FUNCTION_DEF(user_irq_claim_unused) -int PICO_WEAK_FUNCTION_IMPL_NAME(user_irq_claim_unused)(bool required) { - int bit = hw_claim_unused_from_range(user_irq_claimed_ptr(), required, 0, NUM_USER_IRQS - 1, "No user IRQs are available"); - if (bit >= 0) bit = (int)NUM_IRQS - bit - 1; - return bit; -} - -PICO_WEAK_FUNCTION_DEF(user_irq_is_claimed) -bool PICO_WEAK_FUNCTION_IMPL_NAME(user_irq_is_claimed)(uint irq_num) { - return hw_is_claimed(user_irq_claimed_ptr(), get_user_irq_claim_index(irq_num)); -} diff --git a/lib/main/pico-sdk/host/hardware_sync/include/hardware/sync.h b/lib/main/pico-sdk/host/hardware_sync/include/hardware/sync.h deleted file mode 100644 index ffbc08032c..0000000000 --- a/lib/main/pico-sdk/host/hardware_sync/include/hardware/sync.h +++ /dev/null @@ -1,154 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _HARDWARE_SYNC_H -#define _HARDWARE_SYNC_H - -#include "pico.h" - -#ifndef __cplusplus - -#if (__STDC_VERSION__ >= 201112L) -#include -#else -enum { - memory_order_acquire, memory_order_release -}; -static inline void atomic_thread_fence(uint x) {} -#endif - -#else - -#include - -#endif - -// PICO_CONFIG: PICO_SPINLOCK_ID_ATOMIC, Spinlock ID for atomics, min=0, max=31, default=8, group=hardware_sync -#ifndef PICO_SPINLOCK_ID_ATOMIC -#define PICO_SPINLOCK_ID_ATOMIC 8 -#endif - -// PICO_CONFIG: PICO_SPINLOCK_ID_IRQ, Spinlock ID for IRQ protection, min=0, max=31, default=9, group=hardware_sync -#ifndef PICO_SPINLOCK_ID_IRQ -#define PICO_SPINLOCK_ID_IRQ 9 -#endif - -// PICO_CONFIG: PICO_SPINLOCK_ID_TIMER, Spinlock ID for Timer protection, min=0, max=31, default=10, group=hardware_sync -#ifndef PICO_SPINLOCK_ID_TIMER -#define PICO_SPINLOCK_ID_TIMER 10 -#endif - -// PICO_CONFIG: PICO_SPINLOCK_ID_HARDWARE_CLAIM, Spinlock ID for Hardware claim protection, min=0, max=31, default=11, group=hardware_sync -#ifndef PICO_SPINLOCK_ID_HARDWARE_CLAIM -#define PICO_SPINLOCK_ID_HARDWARE_CLAIM 11 -#endif - -// PICO_CONFIG: PICO_SPINLOCK_ID_RAND, Spinlock ID for Random Number Generator, min=0, max=31, default=12, group=hardware_sync -#ifndef PICO_SPINLOCK_ID_RAND -#define PICO_SPINLOCK_ID_RAND 12 -#endif - -// PICO_CONFIG: PICO_SPINLOCK_ID_OS1, First Spinlock ID reserved for use by low level OS style software, min=0, max=31, default=14, group=hardware_sync -#ifndef PICO_SPINLOCK_ID_OS1 -#define PICO_SPINLOCK_ID_OS1 14 -#endif - -// PICO_CONFIG: PICO_SPINLOCK_ID_OS2, Second Spinlock ID reserved for use by low level OS style software, min=0, max=31, default=15, group=hardware_sync -#ifndef PICO_SPINLOCK_ID_OS2 -#define PICO_SPINLOCK_ID_OS2 15 -#endif - -// PICO_CONFIG: PICO_SPINLOCK_ID_STRIPED_FIRST, Lowest Spinlock ID in the 'striped' range, min=0, max=31, default=16, group=hardware_sync -#ifndef PICO_SPINLOCK_ID_STRIPED_FIRST -#define PICO_SPINLOCK_ID_STRIPED_FIRST 16 -#endif - -// PICO_CONFIG: PICO_SPINLOCK_ID_STRIPED_LAST, Highest Spinlock ID in the 'striped' range, min=0, max=31, default=23, group=hardware_sync -#ifndef PICO_SPINLOCK_ID_STRIPED_LAST -#define PICO_SPINLOCK_ID_STRIPED_LAST 23 -#endif - -// PICO_CONFIG: PICO_SPINLOCK_ID_CLAIM_FREE_FIRST, Lowest Spinlock ID in the 'claim free' range, min=0, max=31, default=24, group=hardware_sync -#ifndef PICO_SPINLOCK_ID_CLAIM_FREE_FIRST -#define PICO_SPINLOCK_ID_CLAIM_FREE_FIRST 24 -#endif - -#ifdef PICO_SPINLOCK_ID_CLAIM_FREE_END -#warning PICO_SPINLOCK_ID_CLAIM_FREE_END has been renamed to PICO_SPINLOCK_ID_CLAIM_FREE_LAST -#endif - -// PICO_CONFIG: PICO_SPINLOCK_ID_CLAIM_FREE_LAST, Highest Spinlock ID in the 'claim free' range, min=0, max=31, default=31, group=hardware_sync -#ifndef PICO_SPINLOCK_ID_CLAIM_FREE_LAST -#define PICO_SPINLOCK_ID_CLAIM_FREE_LAST 31 -#endif - -typedef struct _spin_lock_t spin_lock_t; - -inline static void __mem_fence_acquire() { -#ifndef __cplusplus - atomic_thread_fence(memory_order_acquire); -#else - std::atomic_thread_fence(std::memory_order_acquire); -#endif -} - -inline static void __mem_fence_release() { -#ifndef __cplusplus - atomic_thread_fence(memory_order_release); -#else - std::atomic_thread_fence(std::memory_order_release); -#endif -} - -#ifdef __cplusplus -extern "C" { -#endif - -void __sev(); - -void __wev(); - -void __wfi(); - -void __wfe(); - -uint32_t save_and_disable_interrupts(); - -void restore_interrupts(uint32_t status); - -void restore_interrupts_from_disabled(uint32_t status); - -uint spin_lock_get_num(spin_lock_t *lock); - -spin_lock_t *spin_lock_instance(uint lock_num); - -void spin_lock_unsafe_blocking(spin_lock_t *lock); - -void spin_unlock_unsafe(spin_lock_t *lock); - -uint32_t spin_lock_blocking(spin_lock_t *lock); - -bool is_spin_locked(const spin_lock_t *lock); - -void spin_unlock(spin_lock_t *lock, uint32_t saved_irq); - -spin_lock_t *spin_lock_init(uint lock_num); - -void clear_spin_locks(void); -#define spin_locks_reset() clear_spin_locks() - -uint next_striped_spin_lock_num(); - -void spin_lock_claim(uint lock_num); -void spin_lock_claim_mask(uint32_t lock_num_mask); -void spin_lock_unclaim(uint lock_num); -int spin_lock_claim_unused(bool required); -uint spin_lock_num(spin_lock_t *lock); - -#ifdef __cplusplus -} -#endif -#endif diff --git a/lib/main/pico-sdk/host/hardware_sync/sync_core0_only.c b/lib/main/pico-sdk/host/hardware_sync/sync_core0_only.c deleted file mode 100644 index 47d0f2f5bb..0000000000 --- a/lib/main/pico-sdk/host/hardware_sync/sync_core0_only.c +++ /dev/null @@ -1,140 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "hardware/sync.h" -#include "hardware/platform_defs.h" - -// This is a dummy implementation that is single threaded - -static struct _spin_lock_t { - bool locked; -} _spinlocks[NUM_SPIN_LOCKS]; - -PICO_WEAK_FUNCTION_DEF(save_and_disable_interrupts) - -//static uint8_t striped_spin_lock_num; - -uint32_t PICO_WEAK_FUNCTION_IMPL_NAME(save_and_disable_interrupts)() { - return 0; -} - -PICO_WEAK_FUNCTION_DEF(restore_interrupts) - -void PICO_WEAK_FUNCTION_IMPL_NAME(restore_interrupts)(uint32_t status) { -} - -PICO_WEAK_FUNCTION_DEF(restore_interrupts_from_disabled) - -void PICO_WEAK_FUNCTION_IMPL_NAME(restore_interrupts_from_disabled)(uint32_t status) { -} - - -PICO_WEAK_FUNCTION_DEF(spin_lock_instance) - -spin_lock_t *PICO_WEAK_FUNCTION_IMPL_NAME(spin_lock_instance)(uint lock_num) { - assert(lock_num < NUM_SPIN_LOCKS); - return &_spinlocks[lock_num]; -} - -PICO_WEAK_FUNCTION_DEF(spin_lock_get_num) - -uint PICO_WEAK_FUNCTION_IMPL_NAME(spin_lock_get_num)(spin_lock_t *lock) { - return lock - _spinlocks; -} - -PICO_WEAK_FUNCTION_DEF(spin_lock_init) - -spin_lock_t *PICO_WEAK_FUNCTION_IMPL_NAME(spin_lock_init)(uint lock_num) { - spin_lock_t *lock = spin_lock_instance(lock_num); - spin_unlock_unsafe(lock); - return lock; -} - -PICO_WEAK_FUNCTION_DEF(spin_lock_unsafe_blocking) - -void PICO_WEAK_FUNCTION_IMPL_NAME(spin_lock_unsafe_blocking)(spin_lock_t *lock) { - lock->locked = true; -} - -PICO_WEAK_FUNCTION_DEF(spin_lock_blocking) - -uint32_t PICO_WEAK_FUNCTION_IMPL_NAME(spin_lock_blocking)(spin_lock_t *lock) { - spin_lock_unsafe_blocking(lock); - return 1; // todo wrong value -} - -PICO_WEAK_FUNCTION_DEF(is_spin_locked) - -bool PICO_WEAK_FUNCTION_IMPL_NAME(is_spin_locked)(const spin_lock_t *lock) { - return lock->locked; -} - -PICO_WEAK_FUNCTION_DEF(spin_unlock_unsafe) - -void PICO_WEAK_FUNCTION_IMPL_NAME(spin_unlock_unsafe)(spin_lock_t *lock) { - lock->locked = false; -} - -PICO_WEAK_FUNCTION_DEF(spin_unlock) - -void PICO_WEAK_FUNCTION_IMPL_NAME(spin_unlock)(spin_lock_t *lock, uint32_t saved_irq) { - spin_unlock_unsafe(lock); -} - -PICO_WEAK_FUNCTION_DEF(__sev) - -volatile bool event_fired; - -void PICO_WEAK_FUNCTION_IMPL_NAME(__sev)() { - event_fired = true; -} - -PICO_WEAK_FUNCTION_DEF(__wfi) - -void PICO_WEAK_FUNCTION_IMPL_NAME(__wfi)() { - panic("Can't wait on irq for host core0 only implementation"); -} - -PICO_WEAK_FUNCTION_DEF(__wfe) - -void PICO_WEAK_FUNCTION_IMPL_NAME(__wfe)() { - while (!event_fired) tight_loop_contents(); -} - -PICO_WEAK_FUNCTION_DEF(clear_spin_locks) - -void PICO_WEAK_FUNCTION_IMPL_NAME(clear_spin_locks)(void) { - for (uint i = 0; i < NUM_SPIN_LOCKS; i++) { - spin_unlock_unsafe(spin_lock_instance(i)); - } -} - -PICO_WEAK_FUNCTION_DEF(next_striped_spin_lock_num) -uint PICO_WEAK_FUNCTION_IMPL_NAME(next_striped_spin_lock_num)() { - return 0; -} - -PICO_WEAK_FUNCTION_DEF(spin_lock_claim) -void PICO_WEAK_FUNCTION_IMPL_NAME(spin_lock_claim)(uint lock_num) { -} - -PICO_WEAK_FUNCTION_DEF(spin_lock_claim_mask) -void PICO_WEAK_FUNCTION_IMPL_NAME(spin_lock_claim_mask)(uint32_t mask) { -} - -PICO_WEAK_FUNCTION_DEF(spin_lock_unclaim) -void PICO_WEAK_FUNCTION_IMPL_NAME(spin_lock_unclaim)(uint lock_num) { -} - -PICO_WEAK_FUNCTION_DEF(spin_lock_claim_unused) -int PICO_WEAK_FUNCTION_IMPL_NAME(spin_lock_claim_unused)(bool required) { - return 0; -} - -PICO_WEAK_FUNCTION_DEF(spin_lock_num) -uint PICO_WEAK_FUNCTION_IMPL_NAME(spin_lock_num)(spin_lock_t *lock) { - return 0; -} \ No newline at end of file diff --git a/lib/main/pico-sdk/host/hardware_timer/include/hardware/timer.h b/lib/main/pico-sdk/host/hardware_timer/include/hardware/timer.h deleted file mode 100644 index 6bb592321b..0000000000 --- a/lib/main/pico-sdk/host/hardware_timer/include/hardware/timer.h +++ /dev/null @@ -1,48 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _HARDWARE_TIMER_H -#define _HARDWARE_TIMER_H - -#include "pico.h" - -#ifdef __cplusplus -extern "C" { -#endif - -// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_HARDWARE_TIMER, Enable/disable assertions in the hardware_timer module, type=bool, default=0, group=hardware_timer -#ifndef PARAM_ASSERTIONS_ENABLED_HARDWARE_TIMER -#ifdef PARAM_ASSERTIONS_ENABLED_TIMER // backwards compatibility with SDK < 2.0.0 -#define PARAM_ASSERTIONS_ENABLED_HARDWARE_TIMER PARAM_ASSERTIONS_ENABLED_TIMER -#else -#define PARAM_ASSERTIONS_ENABLED_HARDWARE_TIMER 0 -#endif -#endif - -static inline void check_hardware_alarm_num_param(uint alarm_num) { - invalid_params_if(HARDWARE_TIMER, alarm_num >= NUM_ALARMS); -} - -uint32_t time_us_32(); -uint64_t time_us_64(); -void busy_wait_us_32(uint32_t delay_us); -void busy_wait_us(uint64_t delay_us); -void busy_wait_ms(uint32_t delay_m); -void busy_wait_until(absolute_time_t t); -bool time_reached(absolute_time_t t); -typedef void (*hardware_alarm_callback_t)(uint alarm_num); -void hardware_alarm_claim(uint alarm_num); -void hardware_alarm_unclaim(uint alarm_num); -int hardware_alarm_claim_unused(bool required); -void hardware_alarm_set_callback(uint alarm_num, hardware_alarm_callback_t callback); -bool hardware_alarm_set_target(uint alarm_num, absolute_time_t t); -void hardware_alarm_cancel(uint alarm_num); -void hardware_alarm_force_irq(uint alarm_num); -#ifdef __cplusplus -} -#endif - -#endif diff --git a/lib/main/pico-sdk/host/hardware_timer/timer.c b/lib/main/pico-sdk/host/hardware_timer/timer.c deleted file mode 100644 index a110be27ed..0000000000 --- a/lib/main/pico-sdk/host/hardware_timer/timer.c +++ /dev/null @@ -1,125 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "hardware/timer.h" -#if defined(__unix__) || defined(__APPLE__) -#include -#include -#include - -#endif - -// in our case not a busy wait -PICO_WEAK_FUNCTION_DEF(busy_wait_us_32) -void PICO_WEAK_FUNCTION_IMPL_NAME(busy_wait_us_32)(uint32_t delay_us) { -#if defined(__unix__) || defined(__APPLE__) - usleep(delay_us); -#else - assert(false); -#endif -} - -PICO_WEAK_FUNCTION_DEF(busy_wait_us) -void PICO_WEAK_FUNCTION_IMPL_NAME(busy_wait_us)(uint64_t delay_us) { - absolute_time_t t; - update_us_since_boot(&t, time_us_64() + delay_us); - busy_wait_until(t); -} - -PICO_WEAK_FUNCTION_DEF(busy_wait_ms) -void PICO_WEAK_FUNCTION_IMPL_NAME(busy_wait_ms)(uint32_t delay_ms) { -#if defined(__unix__) || defined(__APPLE__) - usleep(delay_ms * 1000); -#else - assert(false); -#endif -} - -// this may or may not wrap -PICO_WEAK_FUNCTION_DEF(time_us_64) -uint64_t PICO_WEAK_FUNCTION_IMPL_NAME(time_us_64)() { -#if defined(__unix__) || defined(__APPLE__) -// struct timeval tv; -// gettimeofday(&tv, NULL); -// return tv.tv_sec * (uint64_t) 1000000 + tv.tv_usec; - struct timespec ts; - clock_gettime(CLOCK_MONOTONIC, &ts); - return ts.tv_sec * (uint64_t) 1000000 + ts.tv_nsec / 1000; -#else - panic_unsupported(); -#endif -} - -PICO_WEAK_FUNCTION_DEF(timer_us_32) -uint32_t PICO_WEAK_FUNCTION_IMPL_NAME(timer_us_32)() { - return (uint32_t) time_us_64(); -} - -PICO_WEAK_FUNCTION_DEF(time_reached) -bool PICO_WEAK_FUNCTION_IMPL_NAME(time_reached)(absolute_time_t t) { - uint64_t target = to_us_since_boot(t); - return time_us_64() >= target; -} - -PICO_WEAK_FUNCTION_DEF(busy_wait_until) -void PICO_WEAK_FUNCTION_IMPL_NAME(busy_wait_until)(absolute_time_t target) { -#if defined(__unix__) - struct timespec tspec; - tspec.tv_sec = to_us_since_boot(target) / 1000000; - tspec.tv_nsec = (to_us_since_boot(target) % 1000000) * 1000; - clock_nanosleep(CLOCK_MONOTONIC, TIMER_ABSTIME, &tspec, NULL); -#else - const int chunk = 1u<<30u; - uint64_t target_us = to_us_since_boot(target); - uint64_t time_us = time_us_64(); - while ((int64_t)(target_us - time_us) >= chunk) { - busy_wait_us_32(chunk); - time_us = time_us_64(); - } - if (target_us > time_us) { - busy_wait_us_32(target_us - time_us); - } -#endif -} - -static uint8_t claimed_alarms; - -void hardware_alarm_claim(uint alarm_num) { - assert(!(claimed_alarms & (1u << alarm_num))); - claimed_alarms |= 1u <= NUM_ALARMS) return -1; - claimed_alarms |= 1u << alarm_id; - return alarm_id; -} - -PICO_WEAK_FUNCTION_DEF(hardware_alarm_set_callback) -void PICO_WEAK_FUNCTION_IMPL_NAME(hardware_alarm_set_callback)(uint alarm_num, hardware_alarm_callback_t callback) { - panic_unsupported(); -} - -PICO_WEAK_FUNCTION_DEF(hardware_alarm_set_target) -bool PICO_WEAK_FUNCTION_IMPL_NAME(hardware_alarm_set_target)(uint alarm_num, absolute_time_t target) { - panic_unsupported(); -} - -PICO_WEAK_FUNCTION_DEF(hardware_alarm_cancel) -void PICO_WEAK_FUNCTION_IMPL_NAME(hardware_alarm_cancel)(uint alarm_num) { - panic_unsupported(); -} - -PICO_WEAK_FUNCTION_DEF(hardware_alarm_force_irq) -void PICO_WEAK_FUNCTION_IMPL_NAME(hardware_alarm_force_irq)(uint alarm_num) { - panic_unsupported(); -} diff --git a/lib/main/pico-sdk/host/hardware_uart/include/hardware/uart.h b/lib/main/pico-sdk/host/hardware_uart/include/hardware/uart.h deleted file mode 100644 index b0fa974bcc..0000000000 --- a/lib/main/pico-sdk/host/hardware_uart/include/hardware/uart.h +++ /dev/null @@ -1,100 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _HARDWARE_UART_H -#define _HARDWARE_UART_H - -#include "pico.h" - -// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_HARDWARE_UART, Enable/disable assertions in the hardware_uart module, type=bool, default=0, group=hardware_uart -#ifndef PARAM_ASSERTIONS_ENABLED_HARDWARE_UART -#ifdef PARAM_ASSERTIONS_ENABLED_UART // backwards compatibility with SDK < 2.0.0 -#define PARAM_ASSERTIONS_ENABLED_HARDWARE_UART PARAM_ASSERTIONS_ENABLED_UART -#else -#define PARAM_ASSERTIONS_ENABLED_HARDWARE_UART 0 -#endif -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -typedef struct uart_inst uart_inst_t; - -extern uart_inst_t * const uart0; -extern uart_inst_t * const uart1; -#define uart_default uart0 - -typedef enum { - UART_PARITY_NONE, - UART_PARITY_EVEN, - UART_PARITY_ODD -} uart_parity_t; - -// ---------------------------------------------------------------------------- -// Setup - -// Put the UART into a known state, and enable it. Must be called before other -// functions. -uint uart_init(uart_inst_t *uart, uint baudrate); - -// Disable the UART if it is no longer used. Must be reinitialised before -// being used again. -void uart_deinit(uart_inst_t *uart); - -// Set baud rate as close as possible to requested, and return actual rate. -uint uart_set_baudrate(uart_inst_t *uart, uint baudrate); - -// cts: enable flow control of TX by clear-to-send input -// rts: enable assertion of request-to-send output by RX flow control -void uart_set_hw_flow(uart_inst_t *uart, bool cts, bool rts); - -// Configure how the UART serialises and deserialises data on the wire -void uart_set_format(uart_inst_t *uart, uint data_bits, uint stop_bits, uart_parity_t parity); - -// Enable the UART's interrupt output. Need to install an interrupt handler first. -void uart_set_irqs_enabled(uart_inst_t *uart, bool rx_has_data, bool tx_needs_data); - -// ---------------------------------------------------------------------------- -// Generic input/output - -// If returns 0, no space is available in the UART to write more data. -// If returns nonzero, at least that many bytes can be written without blocking. -bool uart_is_writable(uart_inst_t *uart); - -// If returns 0, no data is available to be read from UART. -// If returns nonzero, at least that many bytes can be written without blocking. -bool uart_is_readable(uart_inst_t *uart); - -// Write len bytes directly from src to the UART -void uart_write_blocking(uart_inst_t *uart, const uint8_t *src, size_t len); - -// Read len bytes directly from the UART to dst -void uart_read_blocking(uart_inst_t *uart, uint8_t *dst, size_t len); - -// ---------------------------------------------------------------------------- -// UART-specific operations and aliases - -void uart_putc(uart_inst_t *uart, char c); - -void uart_putc_raw(uart_inst_t *uart, char c); - -void uart_puts(uart_inst_t *uart, const char *s); - -char uart_getc(uart_inst_t *uart); - -// en: assert break condition (TX held low) if true. Clear break condition if false. -void uart_set_break(uart_inst_t *uart, bool en); - -void uart_default_tx_wait_blocking(); - -#define UART_FUNCSEL_NUM(uart, gpio) 0 - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/lib/main/pico-sdk/host/hardware_uart/uart.c b/lib/main/pico-sdk/host/hardware_uart/uart.c deleted file mode 100644 index 066714547d..0000000000 --- a/lib/main/pico-sdk/host/hardware_uart/uart.c +++ /dev/null @@ -1,130 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include "hardware/uart.h" - -#if defined(__unix) || defined(__APPLE__) -#define _XOPEN_SOURCE 600 /* for ONLCR */ -#define __BSD_VISIBLE 1 /* for ONLCR in *BSD */ - -#include -#include -#include -#include - -#ifndef FNONBLOCK -#define FNONBLOCK O_NONBLOCK -#endif - -struct termios _tty; -static tcflag_t _res_oflg = 0; -static tcflag_t _res_lflg = 0; - -void _resettty(void) { - if (!isatty(STDIN_FILENO)) - return; - - /* reset tty: */ - _tty.c_oflag = _res_oflg; - _tty.c_lflag = _res_lflg; - tcsetattr(STDIN_FILENO, TCSADRAIN, &_tty); -} - -void _inittty(void) { - if (!isatty(STDIN_FILENO)) - return; - - /* save tty: */ - tcgetattr(STDIN_FILENO, &_tty); - _res_oflg = _tty.c_oflag; - _res_lflg = _tty.c_lflag; - - /* set raw: */ - _tty.c_lflag &= ~(ICANON | ICRNL);// | ISIG); - //_tty.c_oflag &= ~ONLCR; - tcsetattr(STDIN_FILENO, TCSANOW, &_tty); - - fcntl(STDIN_FILENO, F_SETFL, FNONBLOCK); - atexit(_resettty); -} - -#else -void _inittty() {} -#endif - -typedef struct { - bool dummy; -} uart_hw_t; - -uart_inst_t *const uart0; -uart_inst_t *const uart1; - -static int _nextchar = EOF; - -static bool _peekchar() { - if (_nextchar == EOF) { - _nextchar = getchar(); - } - return _nextchar != EOF; -} - -uint uart_init(uart_inst_t *uart, uint baud_rate) { - _inittty(); - return baud_rate; -} - -bool uart_is_writable(uart_inst_t *uart) { - return 1; -} - -// If returns 0, no data is available to be read from UART. -// If returns nonzero, at least that many bytes can be written without blocking. -bool uart_is_readable(uart_inst_t *uart) { - return _peekchar() ? 1 : 0; -} - -// Write len bytes directly from src to the UART -void uart_write_blocking(uart_inst_t *uart, const uint8_t *src, size_t len) { - for (size_t i = 0; i < len; i++) { - uart_putc(uart, src[i]); - } -} - -// Read len bytes directly from the UART to dst -void uart_read_blocking(uart_inst_t *uart, uint8_t *dst, size_t len) { - for (size_t i = 0; i < len; i++) { - dst[i] = uart_getc(uart); - } -} - -// ---------------------------------------------------------------------------- -// UART-specific operations and aliases - -void uart_putc(uart_inst_t *uart, char c) { - putchar(c); -} - -void uart_putc_raw(uart_inst_t *uart, char c) { - putchar(c); -} - -void uart_puts(uart_inst_t *uart, const char *s) { - puts(s); -} - -char uart_getc(uart_inst_t *uart) { - while (!_peekchar()) { - tight_loop_contents(); - } - char rc = (char) _nextchar; - _nextchar = EOF; - return rc; -} - -void uart_default_tx_wait_blocking() { - -} diff --git a/lib/main/pico-sdk/host/pico_bit_ops/bit_ops.c b/lib/main/pico-sdk/host/pico_bit_ops/bit_ops.c deleted file mode 100644 index 11f69fe636..0000000000 --- a/lib/main/pico-sdk/host/pico_bit_ops/bit_ops.c +++ /dev/null @@ -1,22 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "pico/bit_ops.h" - -uint32_t __rev(uint32_t v) { - v = ((v & 0x55555555u) << 1u) | ((v >> 1u) & 0x55555555u); - v = ((v & 0x33333333u) << 2u) | ((v >> 2u) & 0x33333333u); - v = ((v & 0x0f0f0f0fu) << 4u) | ((v >> 4u) & 0x0f0f0f0fu); - return (v << 24u) | ((v & 0xff00u) << 8u) | ((v >> 8u) & 0xff00u) | (v >> 24u); -} - -uint64_t __revll(uint64_t v) { - v = ((v & 0x5555555555555555u) << 1u) | ((v >> 1u) & 0x5555555555555555u); - v = ((v & 0x3333333333333333u) << 2u) | ((v >> 2u) & 0x3333333333333333u); - v = ((v & 0x0f0f0f0f0f0f0f0fu) << 4u) | ((v >> 4u) & 0x0f0f0f0f0f0f0f0fu); - v = ((v & 0x00ff00ff00ff00ffu) << 8u) | ((v >> 8u) & 0x00ff00ff00ff00ffu); - return (v << 48u) | ((v & 0xffff0000u) << 16u) | ((v >> 16u) & 0xffff0000u) | (v >> 48u); -} diff --git a/lib/main/pico-sdk/host/pico_divider/divider.c b/lib/main/pico-sdk/host/pico_divider/divider.c deleted file mode 100644 index 709e3bba85..0000000000 --- a/lib/main/pico-sdk/host/pico_divider/divider.c +++ /dev/null @@ -1,114 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "pico/divider.h" - -// These functions save/restore divider state, so are safe to call from interrupts -int32_t div_s32s32(int32_t a, int32_t b) { - return hw_divider_quotient_s32(a, b); -} - -divmod_result_t divmod_s32s32(int32_t a, int32_t b) { - return hw_divider_divmod_s32(a, b); -} - -uint32_t div_u32u32(uint32_t a, uint32_t b) { - return hw_divider_u32_quotient(a, b); -} - -divmod_result_t divmod_u32u32(uint32_t a, uint32_t b) { - return hw_divider_divmod_u32(a, b); -} - -static inline int __sign_of_64(int32_t v) { - return v > 0 ? 1 : (v < 0 ? -1 : 0); -} - -typedef struct { - uint64_t quotient; - uint64_t remainder; -} qr_u64; - -typedef struct { - int64_t quotient; - int64_t remainder; -} qr_s64; - -// divides unsigned values a by b... (a/b) returned in low 32 bits, (a%b) in high 32 bits... results undefined for b==0 -static inline qr_u64 udiv64(uint64_t a, uint64_t b) { - qr_u64 rc; - if (!b) { - rc.quotient = (uint64_t)-1; // todo check this - rc.remainder = a; - } else { - rc.quotient = a/b; - rc.remainder = a%b; - } - return rc; -} - -// divides signed values a by b... (a/b) returned in low 32 bits, (a%b) in high 32 bits... results undefined for b==0 -static inline qr_s64 div64(int64_t a, int64_t b) { - qr_s64 rc; - if (!b) { - rc.quotient = (uint64_t)(-__sign_of_64(a)); - rc.remainder = a; - } else { - rc.quotient = a/b; - rc.remainder = a%b; - } - return rc; -} - -int64_t div_s64s64(int64_t a, int64_t b) { - qr_s64 qr = div64(a, b); - return qr.quotient; -} - -int64_t divmod_s64s64_rem(int64_t a, int64_t b, int64_t *rem) { - qr_s64 qr = div64(a, b); - *rem = qr.remainder; - return qr.quotient; -} - -int64_t divmod_s64s64(int64_t a, int64_t b) { - qr_s64 qr = div64(a, b); - return qr.quotient; -} - -uint64_t div_u64u64(uint64_t a, uint64_t b) { - qr_u64 qr = udiv64(a, b); - return qr.quotient; -} - -uint64_t divmod_u64u64_rem(uint64_t a, uint64_t b, uint64_t *rem) { - qr_u64 qr = udiv64(a, b); - *rem = qr.remainder; - return qr.quotient; -} - -uint64_t divmod_u64u64(uint64_t a, uint64_t b) { - qr_u64 qr = udiv64(a, b); - return qr.quotient; -} - -// these functions are slightly faster, but unsafe the divider state, so are not generally safe to be called from interrupts - -int32_t div_s32s32_unsafe(int32_t a, int32_t b) { return div_s32s32(a,b); } -int32_t divmod_s32s32_rem_unsafe(int32_t a, int32_t b, int32_t *rem) { return divmod_s32s32_rem(a, b, rem); } -divmod_result_t divmod_s32s32_unsafe(int32_t a, int32_t b) { return divmod_s32s32(a, b); } - -uint32_t div_u32u32_unsafe(uint32_t a, uint32_t b) { return div_u32u32(a, b); } -uint32_t divmod_u32u32_rem_unsafe(uint32_t a, uint32_t b, uint32_t *rem) { return divmod_u32u32_rem(a, b, rem); } -uint64_t divmod_u32u32_unsafe(uint32_t a, uint32_t b) { return divmod_u32u32(a, b); } - -int64_t div_s64s64_unsafe(int64_t a, int64_t b) { return div_s64s64(a, b); } -int64_t divmod_s64s64_rem_unsafe(int64_t a, int64_t b, int64_t *rem) { return divmod_s64s64_rem(a, b, rem); } -int64_t divmod_s64s64_unsafe(int64_t a, int64_t b) { return divmod_s64s64(a, b); } - -uint64_t div_u64u64_unsafe(uint64_t a, uint64_t b) { return div_u64u64(a, b); } -uint64_t divmod_u64u64_rem_unsafe(uint64_t a, uint64_t b, uint64_t *rem) { return divmod_u64u64_rem(a, b, rem); } -uint64_t divmod_u64u64_unsafe(uint64_t a, uint64_t b) { return divmod_u64u64(a, b); } diff --git a/lib/main/pico-sdk/host/pico_multicore/include/pico/multicore.h b/lib/main/pico-sdk/host/pico_multicore/include/pico/multicore.h deleted file mode 100644 index 1be1694899..0000000000 --- a/lib/main/pico-sdk/host/pico_multicore/include/pico/multicore.h +++ /dev/null @@ -1,45 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _PICO_MULTICORE_H -#define _PICO_MULTICORE_H - -#include "pico/types.h" - -#ifdef __cplusplus -extern "C" { -#endif - -void multicore_reset_core1(void); -void multicore_launch_core1(void (*entry)(void)); -void multicore_launch_core1_with_stack(void (*entry)(void), uint32_t *stack_bottom, size_t stack_size_bytes); -void multicore_launch_core1_raw(void (*entry)(void), uint32_t *sp, uint32_t vector_table); - -bool multicore_fifo_rvalid(void); -bool multicore_fifo_wready(void); -void multicore_fifo_push_blocking(uint32_t data); -bool multicore_fifo_push_timeout_us(uint32_t data, uint64_t timeout_us); -uint32_t multicore_fifo_pop_blocking(); -bool multicore_fifo_pop_timeout_us(uint64_t timeout_us, uint32_t *out); -void multicore_fifo_drain(void); -void multicore_fifo_clear_irq(void); -uint32_t multicore_fifo_get_status(void); - -// call this from the lockout victim thread -void multicore_lockout_victim_init(void); - -// start locking out the other core (it will be -bool multicore_lockout_start_timeout_us(uint64_t timeout_us); -void multicore_lockout_start_blocking(void); - -bool multicore_lockout_end_timeout_us(uint64_t timeout_us); -void multicore_lockout_end_blocking(void); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/lib/main/pico-sdk/host/pico_platform/include/hardware/platform_defs.h b/lib/main/pico-sdk/host/pico_platform/include/hardware/platform_defs.h deleted file mode 100644 index 924336a924..0000000000 --- a/lib/main/pico-sdk/host/pico_platform/include/hardware/platform_defs.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _HARDWARE_PLATFORM_DEFS_H -#define _HARDWARE_PLATFORM_DEFS_H - -#define NUM_CORES 2u - -#define NUM_DMA_CHANNELS 12u - -#define NUM_GENERIC_TIMERS 1u -#define NUM_ALARMS 4u - -#define NUM_IRQS 32u - -#define NUM_SPIN_LOCKS 32u - -#define XOSC_HZ 12000000u - -#define NUM_SPIN_LOCKS 32u - -#define NUM_BANK0_GPIOS 30 - -#ifndef _u -#define _u(x) x ## u -#endif - -#endif diff --git a/lib/main/pico-sdk/host/pico_platform/include/pico/platform.h b/lib/main/pico-sdk/host/pico_platform/include/pico/platform.h deleted file mode 100644 index ab7c031f05..0000000000 --- a/lib/main/pico-sdk/host/pico_platform/include/pico/platform.h +++ /dev/null @@ -1,159 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _PICO_PLATFORM_H -#define _PICO_PLATFORM_H - -#include "hardware/platform_defs.h" -#include -#include - -#ifdef __unix__ - -#include - -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -#define __not_in_flash(group) -#define __not_in_flash_func(func) func -#define __no_inline_not_in_flash_func(func) func -#define __in_flash(group) -#define __scratch_x(group) -#define __scratch_y(group) - -#ifndef _MSC_VER -#define __packed __attribute__((packed)) -#define __packed_aligned __packed __attribute((aligned)) -#else -// MSVC requires #pragma pack which isn't compatible with a single attribute style define -#define __packed -#define __packed_aligned -#endif - -#define __time_critical_func(x) x -#define __after_data(group) - -//int running_on_fpga() { return false; } -extern void tight_loop_contents(); - -#ifndef __STRING -#define __STRING(x) #x -#endif - -#if !defined(_MSC_VER) || defined(__clang__) -#ifndef __noreturn -#define __noreturn __attribute((noreturn)) -#endif - -#ifndef __unused -#define __unused __attribute__((unused)) -#endif - -#ifndef __noinline -#define __noinline __attribute__((noinline)) -#endif - -#ifndef __aligned -#define __aligned(x) __attribute__((aligned(x))) -#endif - -#define PICO_WEAK_FUNCTION_DEF(x) _Pragma(__STRING(weak x)) -#define PICO_WEAK_FUNCTION_IMPL_NAME(x) x - -#ifndef __weak -#define __weak __attribute__((weak)) -#endif -#else -#ifndef __noreturn -#define __noreturn __declspec(noreturn) -#endif - -#ifndef __unused -#define __unused -#endif - -#ifndef __noinline -#define __noinline __declspec(noinline) -#endif - -#ifndef __aligned -#define __aligned(x) __declspec(align(x)) -#endif - -#ifndef __CONCAT -#define __CONCAT(x,y) x ## y -#endif - -#define __thread __declspec( thread ) - -#define PICO_WEAK_FUNCTION_DEF(x) __pragma(comment(linker, __STRING(/alternatename:_##x=_##x##__weak))); -#define PICO_WEAK_FUNCTION_IMPL_NAME(x) x ## __weak - -static __noreturn void __builtin_unreachable() { -} - -#include -#define __builtin_clz __lzcnt -#endif - -#ifndef count_of -#define count_of(a) (sizeof(a)/sizeof((a)[0])) -#endif - -#ifndef MAX -#define MAX(a, b) ((a)>(b)?(a):(b)) -#endif - -#ifndef MIN -#define MIN(a, b) ((b)>(a)?(a):(b)) -#endif - -// abort in our case -void __noreturn __breakpoint(); - -void __noreturn panic_unsupported(); - -void __noreturn panic(const char *fmt, ...); - -// arggggghhhh there is a weak function called sem_init used by SDL -#define sem_init sem_init_alternative - -extern uint32_t host_safe_hw_ptr_impl(uintptr_t x); -// return a 32 bit handle for a raw ptr; DMA chaining for example embeds pointers in 32 bit values -// which of course does not work if we're running the code natively on a 64 bit platforms. Therefore -// we provide this macro which allows that code to provide a 64->32 bit mapping in host mode -#define host_safe_hw_ptr(x) host_safe_hw_ptr_impl((uintptr_t)(x)) -void *decode_host_safe_hw_ptr(uint32_t ptr); - -#define __fast_mul(a,b) ((a)*(b)) - -typedef unsigned int uint; - -static inline int32_t __mul_instruction(int32_t a,int32_t b) -{ - return a*b; -} - -static inline void __compiler_memory_barrier(void) { -} - -uint get_core_num(); - -static inline uint __get_current_exception(void) { - return 0; - -} - -void busy_wait_at_least_cycles(uint32_t minimum_cycles); - -#ifdef __cplusplus -} -#endif -#endif diff --git a/lib/main/pico-sdk/host/pico_platform/platform_base.c b/lib/main/pico-sdk/host/pico_platform/platform_base.c deleted file mode 100644 index f7d2c95ff9..0000000000 --- a/lib/main/pico-sdk/host/pico_platform/platform_base.c +++ /dev/null @@ -1,54 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#include -#include - -#include "pico.h" -#include "hardware/timer.h" - -PICO_WEAK_FUNCTION_DEF(tight_loop_contents) -void PICO_WEAK_FUNCTION_IMPL_NAME(tight_loop_contents)() { - -} - - -PICO_WEAK_FUNCTION_DEF(get_core_num) -uint PICO_WEAK_FUNCTION_IMPL_NAME(get_core_num)() { - return 0; -} - -void __noreturn panic_unsupported() { - panic("not supported"); -} - -void panic(const char *fmt, ...) { - va_list args; - - puts("*** PANIC ***\n"); - if (fmt) { - va_start(args, fmt); - vprintf(fmt, args); - va_end(args); - } - - puts("\n"); - - __breakpoint(); -} - -void __breakpoint() { - #ifdef _MSC_VER - __debugbreak(); - #else - __builtin_trap(); - #endif -} - -PICO_WEAK_FUNCTION_DEF(busy_wait_at_least_cycles) -void PICO_WEAK_FUNCTION_IMPL_NAME(busy_wait_at_least_cycles)(uint32_t cycles) { - // fairly arbitrary; we'll use 125Mhz as a reference - busy_wait_us((cycles + 124)/125); -} diff --git a/lib/main/pico-sdk/host/pico_runtime/include/pico/runtime.h b/lib/main/pico-sdk/host/pico_runtime/include/pico/runtime.h deleted file mode 100644 index 90d83f5a0f..0000000000 --- a/lib/main/pico-sdk/host/pico_runtime/include/pico/runtime.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _PICO_RUNTIME_H -#define _PICO_RUNTIME_H - -#include "pico.h" - -/** \file runtime.h -* \defgroup pico_runtime pico_runtime -* \brief Basic runtime support for running pre-main initializers provided by other libraries -*/ - -#ifdef __cplusplus -extern "C" { -#endif - -#define PICO_RUNTIME_INIT_TYPE_HW 0 -#define PICO_RUNTIME_INIT_TYPE_RUNTIME 1 -#define PICO_RUNTIME_INIT_TYPE_PER_CORE 2 - -#ifndef PICO_RUNTIME_INIT_FUNC_FLAGS -#define PICO_RUNTIME_INIT_FUNC_FLAGS(func, flags, priority_string1, priority_string2) -#endif -#define PICO_RUNTIME_INIT_FUNC_HW(func, priority_string1, priority_string2) PICO_RUNTIME_INIT_FUNC_FLAGS(func, PICO_RUNTIME_INIT_TYPE_HW, priority_string1, priority_string2) -#define PICO_RUNTIME_INIT_FUNC_RUNTIME(func, priority_string1, priority_string2) PICO_RUNTIME_INIT_FUNC_FLAGS(func, PICO_RUNTIME_INIT_TYPE_RUNTIME, priority_string1, priority_string2) -#define PICO_RUNTIME_INIT_FUNC_PER_CORE(func, priority_string1, priority_string2) PICO_RUNTIME_INIT_FUNC_FLAGS(func, PICO_RUNTIME_INIT_TYPE_PER_CORE, priority_string1, priority_string2) - -#ifdef __cplusplus -} -#endif - -#endif \ No newline at end of file diff --git a/lib/main/pico-sdk/host/pico_runtime/include/pico/runtime_init.h b/lib/main/pico-sdk/host/pico_runtime/include/pico/runtime_init.h deleted file mode 100644 index 9cccc27bbb..0000000000 --- a/lib/main/pico-sdk/host/pico_runtime/include/pico/runtime_init.h +++ /dev/null @@ -1,61 +0,0 @@ -/* - * Copyright (c) 2024 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _PICO_RUNTIME_INIT_H -#define _PICO_RUNTIME_INIT_H - -#include "pico.h" -#include "pico/runtime.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * The runtime initialization is registration based. - * - * For each step of the initialization there is a 5 digit ordinal which indicates - * the ordering (alphabetic increasing sort of the 5 digits) of the steps. - * - * e.g. for the step "bootrom_reset", there is: - * - * \code - * #ifndef PICO_RUNTIME_INIT_BOOTROM_RESET - * #define PICO_RUNTIME_INIT_BOOTROM_RESET "00050" - * #endif - * \endcode - * - * The user can override the order if they wish, by redefining PICO_RUNTIME_INIT_BOOTROM_RESET - * - * For each step, the automatic initialization may be skipped by defining (in this case) - * PICO_RUNTIME_SKIP_INIT_BOOTROM_RESET = 1. The user can then choose to either omit the step - * completely or register their own replacement initialization. - * - * The default method used to perform the initialization is provided, in case the user - * wishes to call it manually; in this case: - * - * \code - * void runtime_init_bootrom_reset(void); - * \endcode - * - * If PICO_RUNTIME_NO_INIT_BOOTOROM_RESET define is set (NO vs SKIP above), then the function - * is not defined, allowing the user to provide a replacement (and also avoiding - * cases where the default implementation won't compile due to missing dependencies) - */ - -// must have no dependency on any other initialization code -#define PICO_RUNTIME_INIT_EARLIEST "00001" - -#define PICO_RUNTIME_INIT_LATEST "99999" - -// not supported on host at, (needs custom section) -#define PICO_RUNTIME_NO_INIT_MUTEX 1 - -#ifdef __cplusplus -} -#endif - -#endif \ No newline at end of file diff --git a/lib/main/pico-sdk/host/pico_runtime/runtime.c b/lib/main/pico-sdk/host/pico_runtime/runtime.c deleted file mode 100644 index 02d82daf85..0000000000 --- a/lib/main/pico-sdk/host/pico_runtime/runtime.c +++ /dev/null @@ -1,11 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "pico/runtime.h" - -void __weak hard_assertion_failure(void) { - panic("Hard assert"); -} diff --git a/lib/main/pico-sdk/host/pico_stdio/include/pico/stdio.h b/lib/main/pico-sdk/host/pico_stdio/include/pico/stdio.h deleted file mode 100644 index de0bde1673..0000000000 --- a/lib/main/pico-sdk/host/pico_stdio/include/pico/stdio.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _PICO_STDIO_H -#define _PICO_STDIO_H - -typedef struct stdio_driver stdio_driver_t; - -#define STDIO_ERROR -1 -#define STDIO_NO_INPUT -2 - -static inline void stdio_usb_init() {} -void stdio_uart_init(); -static inline void stdio_init_all() { stdio_uart_init(); } -static inline void stdio_filter_driver(stdio_driver_t *driver) {} -static inline void stdio_set_translate_crlf(stdio_driver_t *driver, bool enabled) {} -static inline bool stdio_usb_connected(void) { return true; } -int getchar_timeout_us(uint32_t timeout_us); -#define puts_raw puts -#define putchar_raw putchar - -#endif diff --git a/lib/main/pico-sdk/host/pico_stdio/stdio.c b/lib/main/pico-sdk/host/pico_stdio/stdio.c deleted file mode 100644 index 87be91da3e..0000000000 --- a/lib/main/pico-sdk/host/pico_stdio/stdio.c +++ /dev/null @@ -1,23 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "pico/stdlib.h" -#include "hardware/uart.h" - -int getchar_timeout_us(uint32_t timeout_us) { - absolute_time_t t = make_timeout_time_us(timeout_us); - while (!uart_is_readable(uart_default)) { - if (absolute_time_diff_us(t, get_absolute_time()) > 0) { - return STDIO_NO_INPUT; - } - sleep_ms(1); - } - return uart_getc(uart_default); -} - -void stdio_uart_init() { - uart_init(uart_default, 0); -} \ No newline at end of file diff --git a/lib/main/pico-sdk/host/pico_stdlib/stdlib.c b/lib/main/pico-sdk/host/pico_stdlib/stdlib.c deleted file mode 100644 index 166bd5fed2..0000000000 --- a/lib/main/pico-sdk/host/pico_stdlib/stdlib.c +++ /dev/null @@ -1,27 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "pico/stdlib.h" - -void setup_default_uart() { - -} - -void set_sys_clock_48mhz() { - -} - -bool check_sys_clock_khz(uint32_t freq_khz, uint *vco_out, uint *postdiv1_out, uint *postdiv2_out) { - *vco_out = 1000000; - *postdiv1_out = 0; - *postdiv2_out = 0; - return true; -} - -void set_sys_clock_pll(__unused uint32_t vco_freq, __unused uint post_div1, __unused uint post_div2) { - -} - diff --git a/lib/main/pico-sdk/host/pico_time_adapter/include/pico/time_adapter.h b/lib/main/pico-sdk/host/pico_time_adapter/include/pico/time_adapter.h deleted file mode 100644 index c60c66420d..0000000000 --- a/lib/main/pico-sdk/host/pico_time_adapter/include/pico/time_adapter.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * Copyright (c) 2024 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _PICO_TIME_ADAPTER_H -#define _PICO_TIME_ADAPTER_H - -#ifndef TA_NUM_TIMERS -#define TA_NUM_TIMERS 1 -#endif - -#ifndef TA_NUM_TIMER_ALARMS -#define TA_NUM_TIMER_ALARMS 4 -#endif - -void ta_clear_force_irq(alarm_pool_timer_t *timer, uint hardware_alarm_num); -void ta_clear_irq(alarm_pool_timer_t *timer, uint hardware_alarm_num); -void ta_force_irq(alarm_pool_timer_t *timer, uint hardware_alarm_num); -void ta_set_timeout(alarm_pool_timer_t *timer, uint hardware_alarm_num, int64_t target); -void ta_wakes_up_on_or_before(alarm_pool_timer_t *timer, uint alarm_num, int64_t target); -void ta_enable_irq_handler(alarm_pool_timer_t *timer, uint hardware_alarm_num, void (*irq_handler)(void)); -void ta_disable_irq_handler(alarm_pool_timer_t *timer, uint hardware_alarm_num, void (*irq_handler)(void)); -void ta_hardware_alarm_claim(alarm_pool_timer_t *timer, uint hardware_alarm_num); -int ta_hardware_alarm_claim_unused(alarm_pool_timer_t *timer, bool required); -alarm_pool_timer_t *ta_from_current_irq(uint *alarm_num); -uint ta_timer_num(alarm_pool_timer_t *timer); -static inline uint64_t ta_time_us_64(__unused alarm_pool_timer_t *timer) { - return time_us_64(); -} -alarm_pool_timer_t *ta_timer_instance(uint instance_num); -alarm_pool_timer_t *ta_default_timer_instance(void); - -#endif diff --git a/lib/main/pico-sdk/host/pico_time_adapter/time_adapter.c b/lib/main/pico-sdk/host/pico_time_adapter/time_adapter.c deleted file mode 100644 index ff8433d743..0000000000 --- a/lib/main/pico-sdk/host/pico_time_adapter/time_adapter.c +++ /dev/null @@ -1,71 +0,0 @@ -/* - * Copyright (c) 2024 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "pico/time.h" -#include "pico/time_adapter.h" - -PICO_WEAK_FUNCTION_DEF(ta_clear_force_irq) -void PICO_WEAK_FUNCTION_IMPL_NAME(ta_clear_force_irq)(alarm_pool_timer_t *timer, uint hardware_alarm_num) { - panic_unsupported(); -} -PICO_WEAK_FUNCTION_DEF(ta_clear_irq) -void PICO_WEAK_FUNCTION_IMPL_NAME(ta_clear_irq)(alarm_pool_timer_t *timer, uint hardware_alarm_num) { - panic_unsupported(); -} -PICO_WEAK_FUNCTION_DEF(ta_force_irq) -void PICO_WEAK_FUNCTION_IMPL_NAME(ta_force_irq)(alarm_pool_timer_t *timer, uint hardware_alarm_num) { - panic_unsupported(); -} -PICO_WEAK_FUNCTION_DEF(ta_get_handler_hardware_alarm_num) -int PICO_WEAK_FUNCTION_IMPL_NAME(ta_get_handler_hardware_alarm_num)() { - panic_unsupported(); -} -PICO_WEAK_FUNCTION_DEF(ta_set_timeout) -void PICO_WEAK_FUNCTION_IMPL_NAME(ta_set_timeout)(alarm_pool_timer_t *timer, uint hardware_alarm_num, int64_t target) { - panic_unsupported(); -} -PICO_WEAK_FUNCTION_DEF(ta_wakes_up_on_or_before) -void PICO_WEAK_FUNCTION_IMPL_NAME(ta_wakes_up_on_or_before)(alarm_pool_timer_t *timer, uint hardware_alarm_num, int64_t target) { - panic_unsupported(); -} -PICO_WEAK_FUNCTION_DEF(ta_enable_irq_handler) -void PICO_WEAK_FUNCTION_IMPL_NAME(ta_enable_irq_handler)(alarm_pool_timer_t *timer, uint hardware_alarm_num, void (*irq_handler)(void)) { - panic_unsupported(); -} -PICO_WEAK_FUNCTION_DEF(ta_disable_irq_handler) -void PICO_WEAK_FUNCTION_IMPL_NAME(ta_disable_irq_handler)(alarm_pool_timer_t *timer, uint hardware_alarm_num, void (*irq_handler)(void)) { - panic_unsupported(); -} -PICO_WEAK_FUNCTION_DEF(ta_hardware_alarm_claim) -void PICO_WEAK_FUNCTION_IMPL_NAME(ta_hardware_alarm_claim)(alarm_pool_timer_t *timer, uint hardware_alaram_num) { - panic_unsupported(); -} -PICO_WEAK_FUNCTION_DEF(ta_hardware_alarm_claim_unused) -int PICO_WEAK_FUNCTION_IMPL_NAME(ta_hardware_alarm_claim_unused)(alarm_pool_timer_t *timer, bool required) { - panic_unsupported(); -} - -PICO_WEAK_FUNCTION_DEF(ta_from_current_irq); -alarm_pool_timer_t *PICO_WEAK_FUNCTION_IMPL_NAME(ta_from_current_irq)(uint *alarm_num) { - panic_unsupported(); -} - -PICO_WEAK_FUNCTION_DEF(ta_timer_num); -uint ta_timer_num(alarm_pool_timer_t *timer) { - panic_unsupported(); -} - -PICO_WEAK_FUNCTION_DEF(ta_timer_instance); -alarm_pool_timer_t *ta_timer_instance(uint instance_num) { - panic_unsupported(); -} - -PICO_WEAK_FUNCTION_DEF(ta_default_timer_instance); -alarm_pool_timer_t *ta_default_timer_instance(void) { - panic_unsupported(); - -} - diff --git a/lib/main/pico-sdk/rp2040/README.md b/lib/main/pico-sdk/rp2040/README.md deleted file mode 100644 index 06b86be59b..0000000000 --- a/lib/main/pico-sdk/rp2040/README.md +++ /dev/null @@ -1,6 +0,0 @@ -This directory contains files specific to the RP2040 hardware. It is only used when building for the RP2040 platforms i.e. `PICO_PLATFORM=rp2040` - -`hardware_regs` contains low level hardware register #defines autogenerated from the RP2040 chip definition itself. - -`hardware_structs` contains C structures for accessing memory mapped registers - diff --git a/lib/main/pico-sdk/rp2040/boot_stage2/asminclude/boot2_helpers/exit_from_boot2.S b/lib/main/pico-sdk/rp2040/boot_stage2/asminclude/boot2_helpers/exit_from_boot2.S deleted file mode 100644 index 6f06fc1d78..0000000000 --- a/lib/main/pico-sdk/rp2040/boot_stage2/asminclude/boot2_helpers/exit_from_boot2.S +++ /dev/null @@ -1,28 +0,0 @@ -/* - * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _BOOT2_HELPER_EXIT_FROM_BOOT2 -#define _BOOT2_HELPER_EXIT_FROM_BOOT2 - -#include "hardware/regs/m0plus.h" - -// If entered from the bootrom, lr (which we earlier pushed) will be 0, -// and we vector through the table at the start of the main flash image. -// Any regular function call will have a nonzero value for lr. -check_return: - pop {r0} - cmp r0, #0 - beq vector_into_flash - bx r0 -vector_into_flash: - ldr r0, =(XIP_BASE + 0x100) - ldr r1, =(PPB_BASE + M0PLUS_VTOR_OFFSET) - str r0, [r1] - ldmia r0, {r0, r1} - msr msp, r0 - bx r1 - -#endif diff --git a/lib/main/pico-sdk/rp2040/boot_stage2/asminclude/boot2_helpers/read_flash_sreg.S b/lib/main/pico-sdk/rp2040/boot_stage2/asminclude/boot2_helpers/read_flash_sreg.S deleted file mode 100644 index 83698ed601..0000000000 --- a/lib/main/pico-sdk/rp2040/boot_stage2/asminclude/boot2_helpers/read_flash_sreg.S +++ /dev/null @@ -1,30 +0,0 @@ -/* - * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _BOOT2_HELPER_READ_FLASH_SREG -#define _BOOT2_HELPER_READ_FLASH_SREG - -#include "boot2_helpers/wait_ssi_ready.S" - -// Pass status read cmd into r0. -// Returns status value in r0. -.global read_flash_sreg -.type read_flash_sreg,%function -.thumb_func -read_flash_sreg: - push {r1, lr} - str r0, [r3, #SSI_DR0_OFFSET] - // Dummy byte: - str r0, [r3, #SSI_DR0_OFFSET] - - bl wait_ssi_ready - // Discard first byte and combine the next two - ldr r0, [r3, #SSI_DR0_OFFSET] - ldr r0, [r3, #SSI_DR0_OFFSET] - - pop {r1, pc} - -#endif diff --git a/lib/main/pico-sdk/rp2040/boot_stage2/asminclude/boot2_helpers/wait_ssi_ready.S b/lib/main/pico-sdk/rp2040/boot_stage2/asminclude/boot2_helpers/wait_ssi_ready.S deleted file mode 100644 index 2e49b6489d..0000000000 --- a/lib/main/pico-sdk/rp2040/boot_stage2/asminclude/boot2_helpers/wait_ssi_ready.S +++ /dev/null @@ -1,26 +0,0 @@ -/* - * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _BOOT2_HELPER_WAIT_SSI_READY -#define _BOOT2_HELPER_WAIT_SSI_READY - -wait_ssi_ready: - push {r0, r1, lr} - - // Command is complete when there is nothing left to send - // (TX FIFO empty) and SSI is no longer busy (CSn deasserted) -1: - ldr r1, [r3, #SSI_SR_OFFSET] - movs r0, #SSI_SR_TFE_BITS - tst r1, r0 - beq 1b - movs r0, #SSI_SR_BUSY_BITS - tst r1, r0 - bne 1b - - pop {r0, r1, pc} - -#endif diff --git a/lib/main/pico-sdk/rp2040/boot_stage2/boot2_at25sf128a.S b/lib/main/pico-sdk/rp2040/boot_stage2/boot2_at25sf128a.S deleted file mode 100644 index 72f751ed98..0000000000 --- a/lib/main/pico-sdk/rp2040/boot_stage2/boot2_at25sf128a.S +++ /dev/null @@ -1,282 +0,0 @@ -// ---------------------------------------------------------------------------- -// Second stage boot code -// Copyright (c) 2019-2021 Raspberry Pi (Trading) Ltd. -// SPDX-License-Identifier: BSD-3-Clause -// -// Device: Adesto AT25SF128A -// Based on W25Q080 code: main difference is the QE bit is being set -// via command 0x31 -// -// Description: Configures AT25SF128A to run in Quad I/O continuous read XIP mode -// -// Details: * Check status register 2 to determine if QSPI mode is enabled, -// and perform an SR2 programming cycle if necessary. -// * Use SSI to perform a dummy 0xEB read command, with the mode -// continuation bits set, so that the flash will not require -// 0xEB instruction prefix on subsequent reads. -// * Configure SSI to write address, mode bits, but no instruction. -// SSI + flash are now jointly in a state where continuous reads -// can take place. -// * Jump to exit pointer passed in via lr. Bootrom passes null, -// in which case this code uses a default 256 byte flash offset -// -// Building: * This code must be position-independent, and use stack only -// * The code will be padded to a size of 256 bytes, including a -// 4-byte checksum. Therefore code size cannot exceed 252 bytes. -// ---------------------------------------------------------------------------- - -#include "pico/asm_helper.S" -#include "hardware/regs/addressmap.h" -#include "hardware/regs/ssi.h" -#include "hardware/regs/pads_qspi.h" - -// ---------------------------------------------------------------------------- -// Config section -// ---------------------------------------------------------------------------- -// It should be possible to support most flash devices by modifying this section - -// The serial flash interface will run at clk_sys/PICO_FLASH_SPI_CLKDIV. -// This must be a positive, even integer. -// The bootrom is very conservative with SPI frequency, but here we should be -// as aggressive as possible. - -#ifndef PICO_FLASH_SPI_CLKDIV -#define PICO_FLASH_SPI_CLKDIV 4 -#endif -#if PICO_FLASH_SPI_CLKDIV & 1 -#error PICO_FLASH_SPI_CLKDIV must be even -#endif - -// Define interface width: single/dual/quad IO -#define FRAME_FORMAT SSI_CTRLR0_SPI_FRF_VALUE_QUAD - -// For W25Q080 this is the "Read data fast quad IO" instruction: -#define CMD_READ 0xeb - -// "Mode bits" are 8 special bits sent immediately after -// the address bits in a "Read Data Fast Quad I/O" command sequence. -// On W25Q080, the four LSBs are don't care, and if MSBs == 0xa, the -// next read does not require the 0xeb instruction prefix. -#define MODE_CONTINUOUS_READ 0x20 - -// The number of address + mode bits, divided by 4 (always 4, not function of -// interface width). -#define ADDR_L 8 - -// How many clocks of Hi-Z following the mode bits. For W25Q080, 4 dummy cycles -// are required. -#define WAIT_CYCLES 4 - -// If defined, we will read status reg, compare to SREG_DATA, and overwrite -// with our value if the SR doesn't match. -// We do a two-byte write to SR1 (01h cmd) rather than a one-byte write to -// SR2 (31h cmd) as the latter command isn't supported by WX25Q080. -// This isn't great because it will remove block protections. -// A better solution is to use a volatile SR write if your device supports it. -#define PROGRAM_STATUS_REG - -#define CMD_WRITE_ENABLE 0x06 -#define CMD_READ_STATUS 0x05 -#define CMD_READ_STATUS2 0x35 -#define CMD_WRITE_STATUS 0x01 -#define CMD_WRITE_STATUS2 0x31 -#define SREG_DATA 0x02 // Enable quad-SPI mode - -// ---------------------------------------------------------------------------- -// Start of 2nd Stage Boot Code -// ---------------------------------------------------------------------------- - -pico_default_asm_setup - -.section .text - -// lr will be zero on entry if entered from the bootrom, and the boot_stage2 is expected -// to continue into the binary via the vector table at 0x10000100. -// -// lr will be non-zero on entry if this code has been copied into RAM by user code and called -// from there, and the boot_stage2 should just return normally. -// -// r3 holds SSI base, r0...2 used as temporaries. Other GPRs not used. -regular_func _stage2_boot - push {lr} - - // Set pad configuration: - // - SCLK 8mA drive, no slew limiting - // - SDx disable input Schmitt to reduce delay - - ldr r3, =PADS_QSPI_BASE - movs r0, #(2 << PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_LSB | PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_BITS) - str r0, [r3, #PADS_QSPI_GPIO_QSPI_SCLK_OFFSET] - ldr r0, [r3, #PADS_QSPI_GPIO_QSPI_SD0_OFFSET] - movs r1, #PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_BITS - bics r0, r1 - str r0, [r3, #PADS_QSPI_GPIO_QSPI_SD0_OFFSET] - str r0, [r3, #PADS_QSPI_GPIO_QSPI_SD1_OFFSET] - str r0, [r3, #PADS_QSPI_GPIO_QSPI_SD2_OFFSET] - str r0, [r3, #PADS_QSPI_GPIO_QSPI_SD3_OFFSET] - - ldr r3, =XIP_SSI_BASE - - // Disable SSI to allow further config - movs r1, #0 - str r1, [r3, #SSI_SSIENR_OFFSET] - - // Set baud rate - movs r1, #PICO_FLASH_SPI_CLKDIV - str r1, [r3, #SSI_BAUDR_OFFSET] - - // Set 1-cycle sample delay. If PICO_FLASH_SPI_CLKDIV == 2 then this means, - // if the flash launches data on SCLK posedge, we capture it at the time that - // the next SCLK posedge is launched. This is shortly before that posedge - // arrives at the flash, so data hold time should be ok. For - // PICO_FLASH_SPI_CLKDIV > 2 this pretty much has no effect. - - movs r1, #1 - movs r2, #SSI_RX_SAMPLE_DLY_OFFSET // == 0xf0 so need 8 bits of offset significance - str r1, [r3, r2] - - -// On QSPI parts we usually need a 01h SR-write command to enable QSPI mode -// (i.e. turn WPn and HOLDn into IO2/IO3) -#ifdef PROGRAM_STATUS_REG -program_sregs: -#define CTRL0_SPI_TXRX \ - (7 << SSI_CTRLR0_DFS_32_LSB) | /* 8 bits per data frame */ \ - (SSI_CTRLR0_TMOD_VALUE_TX_AND_RX << SSI_CTRLR0_TMOD_LSB) - - ldr r1, =(CTRL0_SPI_TXRX) - str r1, [r3, #SSI_CTRLR0_OFFSET] - - // Enable SSI and select slave 0 - movs r1, #1 - str r1, [r3, #SSI_SSIENR_OFFSET] - - // Check whether SR needs updating - movs r0, #CMD_READ_STATUS2 - bl read_flash_sreg - movs r2, #SREG_DATA - cmp r0, r2 - beq skip_sreg_programming - - // Send write enable command - movs r1, #CMD_WRITE_ENABLE - str r1, [r3, #SSI_DR0_OFFSET] - - // Poll for completion and discard RX - bl wait_ssi_ready - ldr r1, [r3, #SSI_DR0_OFFSET] - - // Send status write command followed by data bytes - movs r1, #CMD_WRITE_STATUS2 - str r1, [r3, #SSI_DR0_OFFSET] - str r2, [r3, #SSI_DR0_OFFSET] - - bl wait_ssi_ready - ldr r1, [r3, #SSI_DR0_OFFSET] - ldr r1, [r3, #SSI_DR0_OFFSET] - ldr r1, [r3, #SSI_DR0_OFFSET] - - // Poll status register for write completion -1: - movs r0, #CMD_READ_STATUS - bl read_flash_sreg - movs r1, #1 - tst r0, r1 - bne 1b - -skip_sreg_programming: - - // Disable SSI again so that it can be reconfigured - movs r1, #0 - str r1, [r3, #SSI_SSIENR_OFFSET] -#endif - -// Currently the flash expects an 8 bit serial command prefix on every -// transfer, which is a waste of cycles. Perform a dummy Fast Read Quad I/O -// command, with mode bits set such that the flash will not expect a serial -// command prefix on *subsequent* transfers. We don't care about the results -// of the read, the important part is the mode bits. - -dummy_read: -#define CTRLR0_ENTER_XIP \ - (FRAME_FORMAT /* Quad I/O mode */ \ - << SSI_CTRLR0_SPI_FRF_LSB) | \ - (31 << SSI_CTRLR0_DFS_32_LSB) | /* 32 data bits */ \ - (SSI_CTRLR0_TMOD_VALUE_EEPROM_READ /* Send INST/ADDR, Receive Data */ \ - << SSI_CTRLR0_TMOD_LSB) - - ldr r1, =(CTRLR0_ENTER_XIP) - str r1, [r3, #SSI_CTRLR0_OFFSET] - - movs r1, #0x0 // NDF=0 (single 32b read) - str r1, [r3, #SSI_CTRLR1_OFFSET] - -#define SPI_CTRLR0_ENTER_XIP \ - (ADDR_L << SSI_SPI_CTRLR0_ADDR_L_LSB) | /* Address + mode bits */ \ - (WAIT_CYCLES << SSI_SPI_CTRLR0_WAIT_CYCLES_LSB) | /* Hi-Z dummy clocks following address + mode */ \ - (SSI_SPI_CTRLR0_INST_L_VALUE_8B \ - << SSI_SPI_CTRLR0_INST_L_LSB) | /* 8-bit instruction */ \ - (SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_1C2A /* Send Command in serial mode then address in Quad I/O mode */ \ - << SSI_SPI_CTRLR0_TRANS_TYPE_LSB) - - ldr r1, =(SPI_CTRLR0_ENTER_XIP) - ldr r0, =(XIP_SSI_BASE + SSI_SPI_CTRLR0_OFFSET) // SPI_CTRL0 Register - str r1, [r0] - - movs r1, #1 // Re-enable SSI - str r1, [r3, #SSI_SSIENR_OFFSET] - - movs r1, #CMD_READ - str r1, [r3, #SSI_DR0_OFFSET] // Push SPI command into TX FIFO - movs r1, #MODE_CONTINUOUS_READ // 32-bit: 24 address bits (we don't care, so 0) and M[7:4]=1010 - str r1, [r3, #SSI_DR0_OFFSET] // Push Address into TX FIFO - this will trigger the transaction - - // Poll for completion - bl wait_ssi_ready - -// The flash is in a state where we can blast addresses in parallel, and get -// parallel data back. Now configure the SSI to translate XIP bus accesses -// into QSPI transfers of this form. - - movs r1, #0 - str r1, [r3, #SSI_SSIENR_OFFSET] // Disable SSI (and clear FIFO) to allow further config - -// Note that the INST_L field is used to select what XIP data gets pushed into -// the TX FIFO: -// INST_L_0_BITS {ADDR[23:0],XIP_CMD[7:0]} Load "mode bits" into XIP_CMD -// Anything else {XIP_CMD[7:0],ADDR[23:0]} Load SPI command into XIP_CMD -configure_ssi: -#define SPI_CTRLR0_XIP \ - (MODE_CONTINUOUS_READ /* Mode bits to keep flash in continuous read mode */ \ - << SSI_SPI_CTRLR0_XIP_CMD_LSB) | \ - (ADDR_L << SSI_SPI_CTRLR0_ADDR_L_LSB) | /* Total number of address + mode bits */ \ - (WAIT_CYCLES << SSI_SPI_CTRLR0_WAIT_CYCLES_LSB) | /* Hi-Z dummy clocks following address + mode */ \ - (SSI_SPI_CTRLR0_INST_L_VALUE_NONE /* Do not send a command, instead send XIP_CMD as mode bits after address */ \ - << SSI_SPI_CTRLR0_INST_L_LSB) | \ - (SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_2C2A /* Send Address in Quad I/O mode (and Command but that is zero bits long) */ \ - << SSI_SPI_CTRLR0_TRANS_TYPE_LSB) - - ldr r1, =(SPI_CTRLR0_XIP) - ldr r0, =(XIP_SSI_BASE + SSI_SPI_CTRLR0_OFFSET) - str r1, [r0] - - movs r1, #1 - str r1, [r3, #SSI_SSIENR_OFFSET] // Re-enable SSI - -// Bus accesses to the XIP window will now be transparently serviced by the -// external flash on cache miss. We are ready to run code from flash. - -// Pull in standard exit routine -#include "boot2_helpers/exit_from_boot2.S" - -// Common functions -#include "boot2_helpers/wait_ssi_ready.S" -#ifdef PROGRAM_STATUS_REG -#include "boot2_helpers/read_flash_sreg.S" -#endif - -.global literals -literals: -.ltorg - -.end diff --git a/lib/main/pico-sdk/rp2040/boot_stage2/boot2_generic_03h.S b/lib/main/pico-sdk/rp2040/boot_stage2/boot2_generic_03h.S deleted file mode 100644 index effef930b1..0000000000 --- a/lib/main/pico-sdk/rp2040/boot_stage2/boot2_generic_03h.S +++ /dev/null @@ -1,106 +0,0 @@ -// ---------------------------------------------------------------------------- -// Second stage boot code -// Copyright (c) 2019-2021 Raspberry Pi (Trading) Ltd. -// SPDX-License-Identifier: BSD-3-Clause -// -// Device: Anything which responds to 03h serial read command -// -// Details: * Configure SSI to translate each APB read into a 03h command -// * 8 command clocks, 24 address clocks and 32 data clocks -// * This enables you to boot from almost anything: you can pretty -// much solder a potato to your PCB, or a piece of cheese -// * The tradeoff is performance around 3x worse than QSPI XIP -// -// Building: * This code must be position-independent, and use stack only -// * The code will be padded to a size of 256 bytes, including a -// 4-byte checksum. Therefore code size cannot exceed 252 bytes. -// ---------------------------------------------------------------------------- - -#include "pico/asm_helper.S" -#include "hardware/regs/addressmap.h" -#include "hardware/regs/ssi.h" - -pico_default_asm_setup - -// ---------------------------------------------------------------------------- -// Config section -// ---------------------------------------------------------------------------- -// It should be possible to support most flash devices by modifying this section - -// The serial flash interface will run at clk_sys/PICO_FLASH_SPI_CLKDIV. -// This must be a positive, even integer. -// The bootrom is very conservative with SPI frequency, but here we should be -// as aggressive as possible. -#ifndef PICO_FLASH_SPI_CLKDIV -#define PICO_FLASH_SPI_CLKDIV 4 -#endif - -#define CMD_READ 0x03 - -// Value is number of address bits divided by 4 -#define ADDR_L 6 - -#define CTRLR0_XIP \ - (SSI_CTRLR0_SPI_FRF_VALUE_STD << SSI_CTRLR0_SPI_FRF_LSB) | /* Standard 1-bit SPI serial frames */ \ - (31 << SSI_CTRLR0_DFS_32_LSB) | /* 32 clocks per data frame */ \ - (SSI_CTRLR0_TMOD_VALUE_EEPROM_READ << SSI_CTRLR0_TMOD_LSB) /* Send instr + addr, receive data */ - -#define SPI_CTRLR0_XIP \ - (CMD_READ << SSI_SPI_CTRLR0_XIP_CMD_LSB) | /* Value of instruction prefix */ \ - (ADDR_L << SSI_SPI_CTRLR0_ADDR_L_LSB) | /* Total number of address + mode bits */ \ - (2 << SSI_SPI_CTRLR0_INST_L_LSB) | /* 8 bit command prefix (field value is bits divided by 4) */ \ - (SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_1C1A << SSI_SPI_CTRLR0_TRANS_TYPE_LSB) /* command and address both in serial format */ - -// ---------------------------------------------------------------------------- -// Start of 2nd Stage Boot Code -// ---------------------------------------------------------------------------- - -.section .text - -// lr will be zero on entry if entered from the bootrom, and the boot_stage2 is expected -// to continue into the binary via the vector table at 0x10000100. -// -// lr will be non-zero on entry if this code has been copied into RAM by user code and called -// from there, and the boot_stage2 should just return normally. -// -// r3 holds SSI base, r0...2 used as temporaries. Other GPRs not used. -regular_func _stage2_boot - push {lr} - - ldr r3, =XIP_SSI_BASE // Use as base address where possible - - // Disable SSI to allow further config - movs r1, #0 - str r1, [r3, #SSI_SSIENR_OFFSET] - - // Set baud rate - movs r1, #PICO_FLASH_SPI_CLKDIV - str r1, [r3, #SSI_BAUDR_OFFSET] - - ldr r1, =(CTRLR0_XIP) - str r1, [r3, #SSI_CTRLR0_OFFSET] - - ldr r1, =(SPI_CTRLR0_XIP) - ldr r0, =(XIP_SSI_BASE + SSI_SPI_CTRLR0_OFFSET) - str r1, [r0] - - // NDF=0 (single 32b read) - movs r1, #0x0 - str r1, [r3, #SSI_CTRLR1_OFFSET] - - // Re-enable SSI - movs r1, #1 - str r1, [r3, #SSI_SSIENR_OFFSET] - -// We are now in XIP mode. Any bus accesses to the XIP address window will be -// translated by the SSI into 03h read commands to the external flash (if cache is missed), -// and the data will be returned to the bus. - -// Pull in standard exit routine -#include "boot2_helpers/exit_from_boot2.S" - -.global literals -literals: -.ltorg - -.end diff --git a/lib/main/pico-sdk/rp2040/boot_stage2/boot2_is25lp080.S b/lib/main/pico-sdk/rp2040/boot_stage2/boot2_is25lp080.S deleted file mode 100644 index fda0f992f8..0000000000 --- a/lib/main/pico-sdk/rp2040/boot_stage2/boot2_is25lp080.S +++ /dev/null @@ -1,264 +0,0 @@ -// ---------------------------------------------------------------------------- -// Copyright (c) 2019-2021 Raspberry Pi (Trading) Ltd. -// SPDX-License-Identifier: BSD-3-Clause -// -// Device: ISSI IS25LP080D -// Based on W25Q080 code: main difference is the QE bit being in -// SR1 instead of SR2. -// -// Description: Configures IS25LP080D to run in Quad I/O continuous read XIP mode -// -// Details: * Check status register to determine if QSPI mode is enabled, -// and perform an SR programming cycle if necessary. -// * Use SSI to perform a dummy 0xEB read command, with the mode -// continuation bits set, so that the flash will not require -// 0xEB instruction prefix on subsequent reads. -// * Configure SSI to write address, mode bits, but no instruction. -// SSI + flash are now jointly in a state where continuous reads -// can take place. -// * Set VTOR = 0x10000100 (user vector table immediately after -// this boot2 image). -// * Read stack pointer (MSP) and reset vector from the flash -// vector table; set SP and jump, as though the processor had -// booted directly from flash. -// -// Building: * This code must be linked to run at 0x20027f00 -// * The code will be padded to a size of 256 bytes, including a -// 4-byte checksum. Therefore code size cannot exceed 252 bytes. -// ---------------------------------------------------------------------------- - -#include "pico/asm_helper.S" -#include "hardware/regs/addressmap.h" -#include "hardware/regs/ssi.h" - -// ---------------------------------------------------------------------------- -// Config section -// ---------------------------------------------------------------------------- -// It should be possible to support most flash devices by modifying this section - -// The serial flash interface will run at clk_sys/PICO_FLASH_SPI_CLKDIV. -// This must be a positive, even integer. -// The bootrom is very conservative with SPI frequency, but here we should be -// as aggressive as possible. -#ifndef PICO_FLASH_SPI_CLKDIV -#define PICO_FLASH_SPI_CLKDIV 4 -#endif - - -// Define interface width: single/dual/quad IO -#define FRAME_FORMAT SSI_CTRLR0_SPI_FRF_VALUE_QUAD - -// For W25Q080 this is the "Read data fast quad IO" instruction: -#define CMD_READ 0xeb - -// "Mode bits" are 8 special bits sent immediately after -// the address bits in a "Read Data Fast Quad I/O" command sequence. -// On W25Q080, the four LSBs are don't care, and if MSBs == 0xa, the -// next read does not require the 0xeb instruction prefix. -#define MODE_CONTINUOUS_READ 0xa0 - -// The number of address + mode bits, divided by 4 (always 4, not function of -// interface width). -#define ADDR_L 8 - -// How many clocks of Hi-Z following the mode bits. For W25Q080, 4 dummy cycles -// are required. -#define WAIT_CYCLES 4 - -// If defined, we will read status reg, compare to SREG_DATA, and overwrite -// with our value if the SR doesn't match. -// This isn't great because it will remove block protections. -// A better solution is to use a volatile SR write if your device supports it. -#define PROGRAM_STATUS_REG - -#define CMD_WRITE_ENABLE 0x06 -#define CMD_READ_STATUS 0x05 -#define CMD_WRITE_STATUS 0x01 -#define SREG_DATA 0x40 // Enable quad-SPI mode - -// ---------------------------------------------------------------------------- -// Start of 2nd Stage Boot Code -// ---------------------------------------------------------------------------- - -pico_default_asm_setup - -.section .text -// lr will be zero on entry if entered from the bootrom, and the boot_stage2 is expected -// to continue into the binary via the vector table at 0x10000100. -// -// lr will be non-zero on entry if this code has been copied into RAM by user code and called -// from there, and the boot_stage2 should just return normally. -// -// r3 holds SSI base, r0...2 used as temporaries. Other GPRs not used. -regular_func _stage2_boot - push {lr} - - ldr r3, =XIP_SSI_BASE // Use as base address where possible - - // Disable SSI to allow further config - movs r1, #0 - str r1, [r3, #SSI_SSIENR_OFFSET] - - // Set baud rate - movs r1, #PICO_FLASH_SPI_CLKDIV - str r1, [r3, #SSI_BAUDR_OFFSET] - -// On QSPI parts we usually need a 01h SR-write command to enable QSPI mode -// (i.e. turn WPn and HOLDn into IO2/IO3) -#ifdef PROGRAM_STATUS_REG -program_sregs: -#define CTRL0_SPI_TXRX \ - (7 << SSI_CTRLR0_DFS_32_LSB) | /* 8 bits per data frame */ \ - (SSI_CTRLR0_TMOD_VALUE_TX_AND_RX << SSI_CTRLR0_TMOD_LSB) - - ldr r1, =(CTRL0_SPI_TXRX) - str r1, [r3, #SSI_CTRLR0_OFFSET] - - // Enable SSI and select slave 0 - movs r1, #1 - str r1, [r3, #SSI_SSIENR_OFFSET] - - // Check whether SR needs updating - ldr r0, =CMD_READ_STATUS - bl read_flash_sreg - ldr r2, =SREG_DATA - cmp r0, r2 - beq skip_sreg_programming - - // Send write enable command - movs r1, #CMD_WRITE_ENABLE - str r1, [r3, #SSI_DR0_OFFSET] - - // Poll for completion and discard RX - bl wait_ssi_ready - ldr r1, [r3, #SSI_DR0_OFFSET] - - // Send status write command followed by data bytes - movs r1, #CMD_WRITE_STATUS - str r1, [r3, #SSI_DR0_OFFSET] - movs r0, #0 - str r2, [r3, #SSI_DR0_OFFSET] - - bl wait_ssi_ready - ldr r1, [r3, #SSI_DR0_OFFSET] - ldr r1, [r3, #SSI_DR0_OFFSET] - - // Poll status register for write completion -1: - ldr r0, =CMD_READ_STATUS - bl read_flash_sreg - movs r1, #1 - tst r0, r1 - bne 1b - -skip_sreg_programming: - - // Send a 0xA3 high-performance-mode instruction -// ldr r1, =0xa3 -// str r1, [r3, #SSI_DR0_OFFSET] -// bl wait_ssi_ready - - // Disable SSI again so that it can be reconfigured - movs r1, #0 - str r1, [r3, #SSI_SSIENR_OFFSET] -#endif - - -// First we need to send the initial command to get us in to Fast Read Quad I/O -// mode. As this transaction requires a command, we can't send it in XIP mode. -// To enter Continuous Read mode as well we need to append 4'b0010 to the address -// bits and then add a further 4 don't care bits. We will construct this by -// specifying a 28-bit address, with the least significant bits being 4'b0010. -// This is just a dummy transaction so we'll perform a read from address zero -// and then discard what comes back. All we really care about is that at the -// end of the transaction, the flash device is in Continuous Read mode -// and from then on will only expect to receive addresses. -dummy_read: -#define CTRLR0_ENTER_XIP \ - (FRAME_FORMAT /* Quad I/O mode */ \ - << SSI_CTRLR0_SPI_FRF_LSB) | \ - (31 << SSI_CTRLR0_DFS_32_LSB) | /* 32 data bits */ \ - (SSI_CTRLR0_TMOD_VALUE_EEPROM_READ /* Send INST/ADDR, Receive Data */ \ - << SSI_CTRLR0_TMOD_LSB) - - ldr r1, =(CTRLR0_ENTER_XIP) - str r1, [r3, #SSI_CTRLR0_OFFSET] - - movs r1, #0x0 // NDF=0 (single 32b read) - str r1, [r3, #SSI_CTRLR1_OFFSET] - -#define SPI_CTRLR0_ENTER_XIP \ - (ADDR_L << SSI_SPI_CTRLR0_ADDR_L_LSB) | /* Address + mode bits */ \ - (WAIT_CYCLES << SSI_SPI_CTRLR0_WAIT_CYCLES_LSB) | /* Hi-Z dummy clocks following address + mode */ \ - (SSI_SPI_CTRLR0_INST_L_VALUE_8B \ - << SSI_SPI_CTRLR0_INST_L_LSB) | /* 8-bit instruction */ \ - (SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_1C2A /* Send Command in serial mode then address in Quad I/O mode */ \ - << SSI_SPI_CTRLR0_TRANS_TYPE_LSB) - - ldr r1, =(SPI_CTRLR0_ENTER_XIP) - ldr r0, =(XIP_SSI_BASE + SSI_SPI_CTRLR0_OFFSET) // SPI_CTRL0 Register - str r1, [r0] - - movs r1, #1 // Re-enable SSI - str r1, [r3, #SSI_SSIENR_OFFSET] - - movs r1, #CMD_READ - str r1, [r3, #SSI_DR0_OFFSET] // Push SPI command into TX FIFO - movs r1, #MODE_CONTINUOUS_READ // 32-bit: 24 address bits (we don't care, so 0) and M[7:4]=1010 - str r1, [r3, #SSI_DR0_OFFSET] // Push Address into TX FIFO - this will trigger the transaction - - // Poll for completion - bl wait_ssi_ready - -// At this point CN# will be deasserted and the SPI clock will not be running. -// The Winbond WX25X10CL device will be in continuous read, dual I/O mode and -// only expecting address bits after the next CN# assertion. So long as we -// send 4'b0010 (and 4 more dummy HiZ bits) after every subsequent 24b address -// then the Winbond device will remain in continuous read mode. This is the -// ideal mode for Execute-In-Place. -// (If we want to exit continuous read mode then we will need to switch back -// to APM mode and generate a 28-bit address phase with the extra nibble set -// to 4'b0000). - - movs r1, #0 - str r1, [r3, #SSI_SSIENR_OFFSET] // Disable SSI (and clear FIFO) to allow further config - -// Note that the INST_L field is used to select what XIP data gets pushed into -// the TX FIFO: -// INST_L_0_BITS {ADDR[23:0],XIP_CMD[7:0]} Load "mode bits" into XIP_CMD -// Anything else {XIP_CMD[7:0],ADDR[23:0]} Load SPI command into XIP_CMD -configure_ssi: -#define SPI_CTRLR0_XIP \ - (MODE_CONTINUOUS_READ /* Mode bits to keep flash in continuous read mode */ \ - << SSI_SPI_CTRLR0_XIP_CMD_LSB) | \ - (ADDR_L << SSI_SPI_CTRLR0_ADDR_L_LSB) | /* Total number of address + mode bits */ \ - (WAIT_CYCLES << SSI_SPI_CTRLR0_WAIT_CYCLES_LSB) | /* Hi-Z dummy clocks following address + mode */ \ - (SSI_SPI_CTRLR0_INST_L_VALUE_NONE /* Do not send a command, instead send XIP_CMD as mode bits after address */ \ - << SSI_SPI_CTRLR0_INST_L_LSB) | \ - (SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_2C2A /* Send Address in Quad I/O mode (and Command but that is zero bits long) */ \ - << SSI_SPI_CTRLR0_TRANS_TYPE_LSB) - - ldr r1, =(SPI_CTRLR0_XIP) - ldr r0, =(XIP_SSI_BASE + SSI_SPI_CTRLR0_OFFSET) - str r1, [r0] - - movs r1, #1 - str r1, [r3, #SSI_SSIENR_OFFSET] // Re-enable SSI - -// We are now in XIP mode, with all transactions using Dual I/O and only -// needing to send 24-bit addresses (plus mode bits) for each read transaction. - -// Pull in standard exit routine -#include "boot2_helpers/exit_from_boot2.S" - -// Common functions -#include "boot2_helpers/wait_ssi_ready.S" -#ifdef PROGRAM_STATUS_REG -#include "boot2_helpers/read_flash_sreg.S" -#endif - -.global literals -literals: -.ltorg - -.end diff --git a/lib/main/pico-sdk/rp2040/boot_stage2/boot2_usb_blinky.S b/lib/main/pico-sdk/rp2040/boot_stage2/boot2_usb_blinky.S deleted file mode 100644 index 0249a455a5..0000000000 --- a/lib/main/pico-sdk/rp2040/boot_stage2/boot2_usb_blinky.S +++ /dev/null @@ -1,50 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "pico/asm_helper.S" - -// Stub second stage which calls into USB bootcode, with parameters. -// USB boot takes two parameters: -// - A GPIO mask for activity LED -- if mask is 0, don't touch GPIOs at all -// - A mask of interfaces to disable. Bit 0 disables MSC, bit 1 disables PICOBoot -// The bootrom passes 0 for both of these parameters, but user code (or this -// second stage) can pass anything. - -#define USB_BOOT_MSD_AND_PICOBOOT 0x0 -#define USB_BOOT_MSD_ONLY 0x2 -#define USB_BOOT_PICOBOOT_ONLY 0x1 - -// Config -#define ACTIVITY_LED 0 -#define BOOT_MODE USB_BOOT_MSD_AND_PICOBOOT - -pico_default_asm_setup - -.section .text - -regular_func _stage2_boot - movs r7, #0x14 // Pointer to _well_known pointer table in ROM - ldrh r0, [r7, #0] // Offset 0 is 16 bit pointer to function table - ldrh r7, [r7, #4] // Offset 4 is 16 bit pointer to table lookup routine - ldr r1, =('U' | ('B' << 8)) // Symbol for USB Boot - blx r7 - cmp r0, #0 - beq dead - - mov r7, r0 - ldr r0, =(1u << ACTIVITY_LED) // Mask of which GPIO (or GPIOs) to use - movs r1, #BOOT_MODE - blx r7 - -dead: - wfi - b dead - -.global literals -literals: -.ltorg - -.end diff --git a/lib/main/pico-sdk/rp2040/boot_stage2/boot2_w25q080.S b/lib/main/pico-sdk/rp2040/boot_stage2/boot2_w25q080.S deleted file mode 100644 index c35fb81fa3..0000000000 --- a/lib/main/pico-sdk/rp2040/boot_stage2/boot2_w25q080.S +++ /dev/null @@ -1,284 +0,0 @@ -// ---------------------------------------------------------------------------- -// Second stage boot code -// Copyright (c) 2019-2021 Raspberry Pi (Trading) Ltd. -// SPDX-License-Identifier: BSD-3-Clause -// -// Device: Winbond W25Q080 -// Also supports W25Q16JV (which has some different SR instructions) -// Also supports AT25SF081 -// Also supports S25FL132K0 -// -// Description: Configures W25Q080 to run in Quad I/O continuous read XIP mode -// -// Details: * Check status register 2 to determine if QSPI mode is enabled, -// and perform an SR2 programming cycle if necessary. -// * Use SSI to perform a dummy 0xEB read command, with the mode -// continuation bits set, so that the flash will not require -// 0xEB instruction prefix on subsequent reads. -// * Configure SSI to write address, mode bits, but no instruction. -// SSI + flash are now jointly in a state where continuous reads -// can take place. -// * Jump to exit pointer passed in via lr. Bootrom passes null, -// in which case this code uses a default 256 byte flash offset -// -// Building: * This code must be position-independent, and use stack only -// * The code will be padded to a size of 256 bytes, including a -// 4-byte checksum. Therefore code size cannot exceed 252 bytes. -// ---------------------------------------------------------------------------- - -#include "pico/asm_helper.S" -#include "hardware/regs/addressmap.h" -#include "hardware/regs/ssi.h" -#include "hardware/regs/pads_qspi.h" - -// ---------------------------------------------------------------------------- -// Config section -// ---------------------------------------------------------------------------- -// It should be possible to support most flash devices by modifying this section - -// The serial flash interface will run at clk_sys/PICO_FLASH_SPI_CLKDIV. -// This must be a positive, even integer. -// The bootrom is very conservative with SPI frequency, but here we should be -// as aggressive as possible. - -#ifndef PICO_FLASH_SPI_CLKDIV -#define PICO_FLASH_SPI_CLKDIV 4 -#endif -#if PICO_FLASH_SPI_CLKDIV & 1 -#error PICO_FLASH_SPI_CLKDIV must be even -#endif - -// Define interface width: single/dual/quad IO -#define FRAME_FORMAT SSI_CTRLR0_SPI_FRF_VALUE_QUAD - -// For W25Q080 this is the "Read data fast quad IO" instruction: -#define CMD_READ 0xeb - -// "Mode bits" are 8 special bits sent immediately after -// the address bits in a "Read Data Fast Quad I/O" command sequence. -// On W25Q080, the four LSBs are don't care, and if MSBs == 0xa, the -// next read does not require the 0xeb instruction prefix. -#define MODE_CONTINUOUS_READ 0xa0 - -// The number of address + mode bits, divided by 4 (always 4, not function of -// interface width). -#define ADDR_L 8 - -// How many clocks of Hi-Z following the mode bits. For W25Q080, 4 dummy cycles -// are required. -#define WAIT_CYCLES 4 - -// If defined, we will read status reg, compare to SREG_DATA, and overwrite -// with our value if the SR doesn't match. -// We do a two-byte write to SR1 (01h cmd) rather than a one-byte write to -// SR2 (31h cmd) as the latter command isn't supported by WX25Q080. -// This isn't great because it will remove block protections. -// A better solution is to use a volatile SR write if your device supports it. -#define PROGRAM_STATUS_REG - -#define CMD_WRITE_ENABLE 0x06 -#define CMD_READ_STATUS 0x05 -#define CMD_READ_STATUS2 0x35 -#define CMD_WRITE_STATUS 0x01 -#define SREG_DATA 0x02 // Enable quad-SPI mode - -// ---------------------------------------------------------------------------- -// Start of 2nd Stage Boot Code -// ---------------------------------------------------------------------------- - -pico_default_asm_setup - -.section .text - -// lr will be zero on entry if entered from the bootrom, and the boot_stage2 is expected -// to continue into the binary via the vector table at 0x10000100. -// -// lr will be non-zero on entry if this code has been copied into RAM by user code and called -// from there, and the boot_stage2 should just return normally. -// -// r3 holds SSI base, r0...2 used as temporaries. Other GPRs not used. -regular_func _stage2_boot - push {lr} - - // Set pad configuration: - // - SCLK 8mA drive, no slew limiting - // - SDx disable input Schmitt to reduce delay - - ldr r3, =PADS_QSPI_BASE - movs r0, #(2 << PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_LSB | PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_BITS) - str r0, [r3, #PADS_QSPI_GPIO_QSPI_SCLK_OFFSET] - ldr r0, [r3, #PADS_QSPI_GPIO_QSPI_SD0_OFFSET] - movs r1, #PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_BITS - bics r0, r1 - str r0, [r3, #PADS_QSPI_GPIO_QSPI_SD0_OFFSET] - str r0, [r3, #PADS_QSPI_GPIO_QSPI_SD1_OFFSET] - str r0, [r3, #PADS_QSPI_GPIO_QSPI_SD2_OFFSET] - str r0, [r3, #PADS_QSPI_GPIO_QSPI_SD3_OFFSET] - - ldr r3, =XIP_SSI_BASE - - // Disable SSI to allow further config - movs r1, #0 - str r1, [r3, #SSI_SSIENR_OFFSET] - - // Set baud rate - movs r1, #PICO_FLASH_SPI_CLKDIV - str r1, [r3, #SSI_BAUDR_OFFSET] - - // Set 1-cycle sample delay. If PICO_FLASH_SPI_CLKDIV == 2 then this means, - // if the flash launches data on SCLK posedge, we capture it at the time that - // the next SCLK posedge is launched. This is shortly before that posedge - // arrives at the flash, so data hold time should be ok. For - // PICO_FLASH_SPI_CLKDIV > 2 this pretty much has no effect. - - movs r1, #1 - movs r2, #SSI_RX_SAMPLE_DLY_OFFSET // == 0xf0 so need 8 bits of offset significance - str r1, [r3, r2] - - -// On QSPI parts we usually need a 01h SR-write command to enable QSPI mode -// (i.e. turn WPn and HOLDn into IO2/IO3) -#ifdef PROGRAM_STATUS_REG -program_sregs: -#define CTRL0_SPI_TXRX \ - (7 << SSI_CTRLR0_DFS_32_LSB) | /* 8 bits per data frame */ \ - (SSI_CTRLR0_TMOD_VALUE_TX_AND_RX << SSI_CTRLR0_TMOD_LSB) - - ldr r1, =(CTRL0_SPI_TXRX) - str r1, [r3, #SSI_CTRLR0_OFFSET] - - // Enable SSI and select slave 0 - movs r1, #1 - str r1, [r3, #SSI_SSIENR_OFFSET] - - // Check whether SR needs updating - movs r0, #CMD_READ_STATUS2 - bl read_flash_sreg - movs r2, #SREG_DATA - cmp r0, r2 - beq skip_sreg_programming - - // Send write enable command - movs r1, #CMD_WRITE_ENABLE - str r1, [r3, #SSI_DR0_OFFSET] - - // Poll for completion and discard RX - bl wait_ssi_ready - ldr r1, [r3, #SSI_DR0_OFFSET] - - // Send status write command followed by data bytes - movs r1, #CMD_WRITE_STATUS - str r1, [r3, #SSI_DR0_OFFSET] - movs r0, #0 - str r0, [r3, #SSI_DR0_OFFSET] - str r2, [r3, #SSI_DR0_OFFSET] - - bl wait_ssi_ready - ldr r1, [r3, #SSI_DR0_OFFSET] - ldr r1, [r3, #SSI_DR0_OFFSET] - ldr r1, [r3, #SSI_DR0_OFFSET] - - // Poll status register for write completion -1: - movs r0, #CMD_READ_STATUS - bl read_flash_sreg - movs r1, #1 - tst r0, r1 - bne 1b - -skip_sreg_programming: - - // Disable SSI again so that it can be reconfigured - movs r1, #0 - str r1, [r3, #SSI_SSIENR_OFFSET] -#endif - -// Currently the flash expects an 8 bit serial command prefix on every -// transfer, which is a waste of cycles. Perform a dummy Fast Read Quad I/O -// command, with mode bits set such that the flash will not expect a serial -// command prefix on *subsequent* transfers. We don't care about the results -// of the read, the important part is the mode bits. - -dummy_read: -#define CTRLR0_ENTER_XIP \ - (FRAME_FORMAT /* Quad I/O mode */ \ - << SSI_CTRLR0_SPI_FRF_LSB) | \ - (31 << SSI_CTRLR0_DFS_32_LSB) | /* 32 data bits */ \ - (SSI_CTRLR0_TMOD_VALUE_EEPROM_READ /* Send INST/ADDR, Receive Data */ \ - << SSI_CTRLR0_TMOD_LSB) - - ldr r1, =(CTRLR0_ENTER_XIP) - str r1, [r3, #SSI_CTRLR0_OFFSET] - - movs r1, #0x0 // NDF=0 (single 32b read) - str r1, [r3, #SSI_CTRLR1_OFFSET] - -#define SPI_CTRLR0_ENTER_XIP \ - (ADDR_L << SSI_SPI_CTRLR0_ADDR_L_LSB) | /* Address + mode bits */ \ - (WAIT_CYCLES << SSI_SPI_CTRLR0_WAIT_CYCLES_LSB) | /* Hi-Z dummy clocks following address + mode */ \ - (SSI_SPI_CTRLR0_INST_L_VALUE_8B \ - << SSI_SPI_CTRLR0_INST_L_LSB) | /* 8-bit instruction */ \ - (SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_1C2A /* Send Command in serial mode then address in Quad I/O mode */ \ - << SSI_SPI_CTRLR0_TRANS_TYPE_LSB) - - ldr r1, =(SPI_CTRLR0_ENTER_XIP) - ldr r0, =(XIP_SSI_BASE + SSI_SPI_CTRLR0_OFFSET) // SPI_CTRL0 Register - str r1, [r0] - - movs r1, #1 // Re-enable SSI - str r1, [r3, #SSI_SSIENR_OFFSET] - - movs r1, #CMD_READ - str r1, [r3, #SSI_DR0_OFFSET] // Push SPI command into TX FIFO - movs r1, #MODE_CONTINUOUS_READ // 32-bit: 24 address bits (we don't care, so 0) and M[7:4]=1010 - str r1, [r3, #SSI_DR0_OFFSET] // Push Address into TX FIFO - this will trigger the transaction - - // Poll for completion - bl wait_ssi_ready - -// The flash is in a state where we can blast addresses in parallel, and get -// parallel data back. Now configure the SSI to translate XIP bus accesses -// into QSPI transfers of this form. - - movs r1, #0 - str r1, [r3, #SSI_SSIENR_OFFSET] // Disable SSI (and clear FIFO) to allow further config - -// Note that the INST_L field is used to select what XIP data gets pushed into -// the TX FIFO: -// INST_L_0_BITS {ADDR[23:0],XIP_CMD[7:0]} Load "mode bits" into XIP_CMD -// Anything else {XIP_CMD[7:0],ADDR[23:0]} Load SPI command into XIP_CMD -configure_ssi: -#define SPI_CTRLR0_XIP \ - (MODE_CONTINUOUS_READ /* Mode bits to keep flash in continuous read mode */ \ - << SSI_SPI_CTRLR0_XIP_CMD_LSB) | \ - (ADDR_L << SSI_SPI_CTRLR0_ADDR_L_LSB) | /* Total number of address + mode bits */ \ - (WAIT_CYCLES << SSI_SPI_CTRLR0_WAIT_CYCLES_LSB) | /* Hi-Z dummy clocks following address + mode */ \ - (SSI_SPI_CTRLR0_INST_L_VALUE_NONE /* Do not send a command, instead send XIP_CMD as mode bits after address */ \ - << SSI_SPI_CTRLR0_INST_L_LSB) | \ - (SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_2C2A /* Send Address in Quad I/O mode (and Command but that is zero bits long) */ \ - << SSI_SPI_CTRLR0_TRANS_TYPE_LSB) - - ldr r1, =(SPI_CTRLR0_XIP) - ldr r0, =(XIP_SSI_BASE + SSI_SPI_CTRLR0_OFFSET) - str r1, [r0] - - movs r1, #1 - str r1, [r3, #SSI_SSIENR_OFFSET] // Re-enable SSI - -// Bus accesses to the XIP window will now be transparently serviced by the -// external flash on cache miss. We are ready to run code from flash. - -// Pull in standard exit routine -#include "boot2_helpers/exit_from_boot2.S" - -// Common functions -#include "boot2_helpers/wait_ssi_ready.S" -#ifdef PROGRAM_STATUS_REG -#include "boot2_helpers/read_flash_sreg.S" -#endif - -.global literals -literals: -.ltorg - -.end diff --git a/lib/main/pico-sdk/rp2040/boot_stage2/boot2_w25x10cl.S b/lib/main/pico-sdk/rp2040/boot_stage2/boot2_w25x10cl.S deleted file mode 100644 index 9aa51ac576..0000000000 --- a/lib/main/pico-sdk/rp2040/boot_stage2/boot2_w25x10cl.S +++ /dev/null @@ -1,197 +0,0 @@ -// ---------------------------------------------------------------------------- -// Second stage boot code -// Copyright (c) 2019-2021 Raspberry Pi (Trading) Ltd. -// SPDX-License-Identifier: BSD-3-Clause -// -// Device: Winbond W25X10CL -// -// Description: Configures W25X10CL to run in Dual I/O continuous read XIP mode -// -// Details: * Disable SSI -// * Configure SSI to generate 8b command + 28b address + 2 wait, -// with address and data using dual SPI mode -// * Enable SSI -// * Generate dummy read with command = 0xBB, top 24b of address -// of 0x000000 followed by M[7:0]=0010zzzz (with the HiZ being -// generated by 2 wait cycles). This leaves the W25X10CL in -// continuous read mode -// * Disable SSI -// * Configure SSI to generate 0b command + 28b address + 2 wait, -// with the extra 4 bits of address LSB being 0x2 to keep the -// W25X10CL in continuous read mode forever -// * Enable SSI -// * Set VTOR = 0x10000100 -// * Read MSP reset vector from 0x10000100 and write to MSP (this -// will also enable XIP mode in the SSI wrapper) -// * Read PC reset vector from 0x10000104 and jump to it -// -// Building: * This code must be linked to run at 0x20000000 -// * The code will be padded to a size of 256 bytes, including a -// 4-byte checksum. Therefore code size cannot exceed 252 bytes. -// ---------------------------------------------------------------------------- - -#include "pico/asm_helper.S" -#include "hardware/regs/addressmap.h" -#include "hardware/regs/ssi.h" - -// The serial flash interface will run at clk_sys/PICO_FLASH_SPI_CLKDIV. -// This must be an even number. -#ifndef PICO_FLASH_SPI_CLKDIV -#define PICO_FLASH_SPI_CLKDIV 4 -#endif - -pico_default_asm_setup - -// ---------------------------------------------------------------------------- -// The "System Control Block" is a set of internal Cortex-M0+ control registers -// that are memory mapped and accessed like any other H/W register. They have -// fixed addresses in the address map of every Cortex-M0+ system. -// ---------------------------------------------------------------------------- - -.equ SCB_VTOR, 0xE000ED08 // RW Vector Table Offset Register - -// ---------------------------------------------------------------------------- -// Winbond W25X10CL Supported Commands -// Taken from "w25x10cl_reg_021714.pdf" -// ---------------------------------------------------------------------------- - -.equ W25X10CL_CMD_READ_DATA_FAST_DUAL_IO, 0xbb - -// ---------------------------------------------------------------------------- -// Winbond W25X10CL "Mode bits" are 8 special bits sent immediately after -// the address bits in a "Read Data Fast Dual I/O" command sequence. -// Of M[7:4], they say M[7:6] are reserved (set to zero), and bits M[3:0] -// are don't care (we HiZ). Only M[5:4] are used, and they must be set -// to M[5:4] = 2'b10 to enable continuous read mode. -// ---------------------------------------------------------------------------- - -.equ W25X10CL_MODE_CONTINUOUS_READ, 0x20 - -// ---------------------------------------------------------------------------- -// Start of 2nd Stage Boot Code -// ---------------------------------------------------------------------------- - -.org 0 - -.section .text - -// lr will be zero on entry if entered from the bootrom, and the boot_stage2 is expected -// to continue into the binary via the vector table at 0x10000100. -// -// lr will be non-zero on entry if this code has been copied into RAM by user code and called -// from there, and the boot_stage2 should just return normally. -// -// r3 holds SSI base, r0...2 used as temporaries. Other GPRs not used. -regular_func _stage2_boot - push {lr} - ldr r3, =XIP_SSI_BASE // Use as base address where possible - -// We are primarily interested in setting up Flash for DSPI XIP w/ continuous read - - movs r1, #0 - str r1, [r3, #SSI_SSIENR_OFFSET] // Disable SSI to allow further config - -// The Boot ROM sets a very conservative SPI clock frequency to be sure it can -// read the initial 256 bytes from any device. Here we can be more aggressive. - - movs r1, #PICO_FLASH_SPI_CLKDIV - str r1, [r3, #SSI_BAUDR_OFFSET] // Set SSI Clock - -// First we need to send the initial command to get us in to Fast Read Dual I/O -// mode. As this transaction requires a command, we can't send it in XIP mode. -// To enter Continuous Read mode as well we need to append 4'b0010 to the address -// bits and then add a further 4 don't care bits. We will construct this by -// specifying a 28-bit address, with the least significant bits being 4'b0010. -// This is just a dummy transaction so we'll perform a read from address zero -// and then discard what comes back. All we really care about is that at the -// end of the transaction, the Winbond W25X10CL device is in Continuous Read mode -// and from then on will only expect to receive addresses. - -#define CTRLR0_ENTER_XIP \ - (SSI_CTRLR0_SPI_FRF_VALUE_DUAL /* Dual I/O mode */ \ - << SSI_CTRLR0_SPI_FRF_LSB) | \ - (31 << SSI_CTRLR0_DFS_32_LSB) | /* 32 data bits */ \ - (SSI_CTRLR0_TMOD_VALUE_EEPROM_READ /* Send INST/ADDR, Receive Data */ \ - << SSI_CTRLR0_TMOD_LSB) - - ldr r1, =(CTRLR0_ENTER_XIP) - str r1, [r3, #SSI_CTRLR0_OFFSET] - - movs r1, #0x0 // NDF=0 (single 32b read) - str r1, [r3, #SSI_CTRLR1_OFFSET] - -#define SPI_CTRLR0_ENTER_XIP \ - (7 << SSI_SPI_CTRLR0_ADDR_L_LSB) | /* Send 28 bits (24 address + 4 mode) */ \ - (2 << SSI_SPI_CTRLR0_WAIT_CYCLES_LSB) | /* Hi-Z the other 4 mode bits (2 cycles @ dual I/O = 4 bits) */ \ - (SSI_SPI_CTRLR0_INST_L_VALUE_8B \ - << SSI_SPI_CTRLR0_INST_L_LSB) | /* 8-bit instruction */ \ - (SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_1C2A /* Send Command in serial mode then address in Dual I/O mode */ \ - << SSI_SPI_CTRLR0_TRANS_TYPE_LSB) - - ldr r1, =(SPI_CTRLR0_ENTER_XIP) - ldr r0, =(XIP_SSI_BASE + SSI_SPI_CTRLR0_OFFSET) // SPI_CTRL0 Register - str r1, [r0] - - movs r1, #1 // Re-enable SSI - str r1, [r3, #SSI_SSIENR_OFFSET] - - movs r1, #W25X10CL_CMD_READ_DATA_FAST_DUAL_IO // 8b command = 0xBB - str r1, [r3, #SSI_DR0_OFFSET] // Push SPI command into TX FIFO - movs r1, #0x0000002 // 28-bit Address for dummy read = 0x000000 + 0x2 Mode bits to set M[5:4]=10 - str r1, [r3, #SSI_DR0_OFFSET] // Push Address into TX FIFO - this will trigger the transaction - -// Now we wait for the read transaction to complete by monitoring the SSI -// status register and checking for the "RX FIFO Not Empty" flag to assert. - - movs r1, #SSI_SR_RFNE_BITS -00: - ldr r0, [r3, #SSI_SR_OFFSET] // Read status register - tst r0, r1 // RFNE status flag set? - beq 00b // If not then wait - -// At this point CN# will be deasserted and the SPI clock will not be running. -// The Winbond WX25X10CL device will be in continuous read, dual I/O mode and -// only expecting address bits after the next CN# assertion. So long as we -// send 4'b0010 (and 4 more dummy HiZ bits) after every subsequent 24b address -// then the Winbond device will remain in continuous read mode. This is the -// ideal mode for Execute-In-Place. -// (If we want to exit continuous read mode then we will need to switch back -// to APM mode and generate a 28-bit address phase with the extra nibble set -// to 4'b0000). - - movs r1, #0 - str r1, [r3, #SSI_SSIENR_OFFSET] // Disable SSI (and clear FIFO) to allow further config - -// Note that the INST_L field is used to select what XIP data gets pushed into -// the TX FIFO: -// INST_L_0_BITS {ADDR[23:0],XIP_CMD[7:0]} Load "mode bits" into XIP_CMD -// Anything else {XIP_CMD[7:0],ADDR[23:0]} Load SPI command into XIP_CMD - -#define SPI_CTRLR0_XIP \ - (W25X10CL_MODE_CONTINUOUS_READ /* Mode bits to keep Winbond in continuous read mode */ \ - << SSI_SPI_CTRLR0_XIP_CMD_LSB) | \ - (7 << SSI_SPI_CTRLR0_ADDR_L_LSB) | /* Send 28 bits (24 address + 4 mode) */ \ - (2 << SSI_SPI_CTRLR0_WAIT_CYCLES_LSB) | /* Hi-Z the other 4 mode bits (2 cycles @ dual I/O = 4 bits) */ \ - (SSI_SPI_CTRLR0_INST_L_VALUE_NONE /* Do not send a command, instead send XIP_CMD as mode bits after address */ \ - << SSI_SPI_CTRLR0_INST_L_LSB) | \ - (SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_2C2A /* Send Address in Dual I/O mode (and Command but that is zero bits long) */ \ - << SSI_SPI_CTRLR0_TRANS_TYPE_LSB) - - ldr r1, =(SPI_CTRLR0_XIP) - ldr r0, =(XIP_SSI_BASE + SSI_SPI_CTRLR0_OFFSET) - str r1, [r0] - - movs r1, #1 - str r1, [r3, #SSI_SSIENR_OFFSET] // Re-enable SSI - -// We are now in XIP mode, with all transactions using Dual I/O and only -// needing to send 24-bit addresses (plus mode bits) for each read transaction. - -// Pull in standard exit routine -#include "boot2_helpers/exit_from_boot2.S" - -.global literals -literals: -.ltorg - -.end diff --git a/lib/main/pico-sdk/rp2040/boot_stage2/boot_stage2.ld b/lib/main/pico-sdk/rp2040/boot_stage2/boot_stage2.ld deleted file mode 100644 index f8669ab64c..0000000000 --- a/lib/main/pico-sdk/rp2040/boot_stage2/boot_stage2.ld +++ /dev/null @@ -1,13 +0,0 @@ -MEMORY { - /* We are loaded to the top 256 bytes of SRAM, which is above the bootrom - stack. Note 4 bytes occupied by checksum. */ - SRAM(rx) : ORIGIN = 0x20041f00, LENGTH = 252 -} - -SECTIONS { - . = ORIGIN(SRAM); - .text : { - *(.entry) - *(.text) - } >SRAM -} diff --git a/lib/main/pico-sdk/rp2040/boot_stage2/compile_time_choice.S b/lib/main/pico-sdk/rp2040/boot_stage2/compile_time_choice.S deleted file mode 100644 index 5aa2b96cd6..0000000000 --- a/lib/main/pico-sdk/rp2040/boot_stage2/compile_time_choice.S +++ /dev/null @@ -1,19 +0,0 @@ -// ---------------------------------------------------------------------------- -// Second stage boot code -// Copyright (c) 2019-2021 Raspberry Pi (Trading) Ltd. -// SPDX-License-Identifier: BSD-3-Clause -// ---------------------------------------------------------------------------- -// -// This implementation uses the PICO_BOOT_STAGE2_CHOOSE_ preprocessor defines to pick -// amongst a menu of known boot stage 2 implementations, allowing the board -// configuration header to be able to specify the boot stage 2 - -#include "boot_stage2/config.h" - -#ifdef PICO_BUILD_BOOT_STAGE2_NAME - // boot stage 2 is configured by cmake, so use the name specified there - #error PICO_BUILD_BOOT_STAGE2_NAME should not be defined for compile_time_choice builds -#else - // boot stage 2 is selected by board config header, and PICO_BOOT_STAGE2_ASM is set in boot_stage2/config.h - #include PICO_BOOT_STAGE2_ASM -#endif diff --git a/lib/main/pico-sdk/rp2040/boot_stage2/doc.h b/lib/main/pico-sdk/rp2040/boot_stage2/doc.h deleted file mode 100644 index 483dd682ff..0000000000 --- a/lib/main/pico-sdk/rp2040/boot_stage2/doc.h +++ /dev/null @@ -1,4 +0,0 @@ -/** - * \defgroup boot_stage2 boot_stage2 - * \brief Second stage boot loaders responsible for setting up external flash - */ diff --git a/lib/main/pico-sdk/rp2040/boot_stage2/include/boot_stage2/config.h b/lib/main/pico-sdk/rp2040/boot_stage2/include/boot_stage2/config.h deleted file mode 100644 index ba9bb1f8b0..0000000000 --- a/lib/main/pico-sdk/rp2040/boot_stage2/include/boot_stage2/config.h +++ /dev/null @@ -1,91 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _BOOT_STAGE2_CONFIG_H -#define _BOOT_STAGE2_CONFIG_H - -// NOTE THIS HEADER IS INCLUDED FROM ASSEMBLY - -#include "pico.h" - -// PICO_CONFIG: PICO_BUILD_BOOT_STAGE2_NAME, Name of the boot stage 2 if selected in the build system, group=boot_stage2 -#ifdef PICO_BUILD_BOOT_STAGE2_NAME - #define _BOOT_STAGE2_SELECTED -#else - // check that multiple boot stage 2 options haven't been set... - -// PICO_CONFIG: PICO_BOOT_STAGE2_CHOOSE_IS25LP080, Select boot2_is25lp080 as the boot stage 2 when no boot stage 2 selection is made by the CMake build, type=bool, default=0, group=boot_stage2 -#ifndef PICO_BOOT_STAGE2_CHOOSE_IS25LP080 - #define PICO_BOOT_STAGE2_CHOOSE_IS25LP080 0 -#elif PICO_BOOT_STAGE2_CHOOSE_IS25LP080 - #ifdef _BOOT_STAGE2_SELECTED - #error multiple boot stage 2 options chosen - #endif - #define _BOOT_STAGE2_SELECTED -#endif -// PICO_CONFIG: PICO_BOOT_STAGE2_CHOOSE_W25Q080, Select boot2_w25q080 as the boot stage 2 when no boot stage 2 selection is made by the CMake build, type=bool, default=0, group=boot_stage2 -#ifndef PICO_BOOT_STAGE2_CHOOSE_W25Q080 - #define PICO_BOOT_STAGE2_CHOOSE_W25Q080 0 -#elif PICO_BOOT_STAGE2_CHOOSE_W25Q080 - #ifdef _BOOT_STAGE2_SELECTED - #error multiple boot stage 2 options chosen - #endif - #define _BOOT_STAGE2_SELECTED -#endif -// PICO_CONFIG: PICO_BOOT_STAGE2_CHOOSE_W25X10CL, Select boot2_w25x10cl as the boot stage 2 when no boot stage 2 selection is made by the CMake build, type=bool, default=0, group=boot_stage2 -#ifndef PICO_BOOT_STAGE2_CHOOSE_W25X10CL - #define PICO_BOOT_STAGE2_CHOOSE_W25X10CL 0 -#elif PICO_BOOT_STAGE2_CHOOSE_W25X10CL - #ifdef _BOOT_STAGE2_SELECTED - #error multiple boot stage 2 options chosen - #endif - #define _BOOT_STAGE2_SELECTED -#endif -// PICO_CONFIG: PICO_BOOT_STAGE2_CHOOSE_AT25SF128A, Select boot2_at25sf128a as the boot stage 2 when no boot stage 2 selection is made by the CMake build, type=bool, default=0, group=boot_stage2 -#ifndef PICO_BOOT_STAGE2_CHOOSE_AT25SF128A - #define PICO_BOOT_STAGE2_CHOOSE_AT25SF128A 0 -#elif PICO_BOOT_STAGE2_CHOOSE_AT25SF128A - #ifdef _BOOT_STAGE2_SELECTED - #error multiple boot stage 2 options chosen - #endif - #define _BOOT_STAGE2_SELECTED -#endif - -// PICO_CONFIG: PICO_BOOT_STAGE2_CHOOSE_GENERIC_03H, Select boot2_generic_03h as the boot stage 2 when no boot stage 2 selection is made by the CMake build, type=bool, default=1, group=boot_stage2 -#if defined(PICO_BOOT_STAGE2_CHOOSE_GENERIC_03H) && PICO_BOOT_STAGE2_CHOOSE_GENERIC_03H - #ifdef _BOOT_STAGE2_SELECTED - #error multiple boot stage 2 options chosen - #endif - #define _BOOT_STAGE2_SELECTED -#endif - -#endif // PICO_BUILD_BOOT_STAGE2_NAME - -#ifdef PICO_BUILD_BOOT_STAGE2_NAME - // boot stage 2 is configured by cmake, so use the name specified there - #define PICO_BOOT_STAGE2_NAME PICO_BUILD_BOOT_STAGE2_NAME -#else - // boot stage 2 is selected by board config header, so we have to do some work - #if PICO_BOOT_STAGE2_CHOOSE_IS25LP080 - #define _BOOT_STAGE2 boot2_is25lp080 - #elif PICO_BOOT_STAGE2_CHOOSE_W25Q080 - #define _BOOT_STAGE2 boot2_w25q080 - #elif PICO_BOOT_STAGE2_CHOOSE_W25X10CL - #define _BOOT_STAGE2 boot2_w25x10cl - #elif PICO_BOOT_STAGE2_CHOOSE_AT25SF128A - #define _BOOT_STAGE2 boot2_at25sf128a - #elif !defined(PICO_BOOT_STAGE2_CHOOSE_GENERIC_03H) || PICO_BOOT_STAGE2_CHOOSE_GENERIC_03H - #undef PICO_BOOT_STAGE2_CHOOSE_GENERIC_03H - #define PICO_BOOT_STAGE2_CHOOSE_GENERIC_03H 1 - #define _BOOT_STAGE2 boot2_generic_03h - #else - #error no boot stage 2 is defined by PICO_BOOT_STAGE2_CHOOSE_ macro - #endif - // we can't include cdefs in assembly, so define our own, but avoid conflict with real ones for c inclusion - #define PICO_BOOT_STAGE2_NAME __PICO_XSTRING(_BOOT_STAGE2) - #define PICO_BOOT_STAGE2_ASM __PICO_XSTRING(__PICO_CONCAT1(_BOOT_STAGE2,.S)) -#endif -#endif diff --git a/lib/main/pico-sdk/rp2040/boot_stage2/pad_checksum b/lib/main/pico-sdk/rp2040/boot_stage2/pad_checksum deleted file mode 100644 index d301756826..0000000000 --- a/lib/main/pico-sdk/rp2040/boot_stage2/pad_checksum +++ /dev/null @@ -1,55 +0,0 @@ -#!/usr/bin/env python3 - -import argparse -import binascii -import struct -import sys - - -def any_int(x): - try: - return int(x, 0) - except: - raise argparse.ArgumentTypeError("expected an integer, not '{!r}'".format(x)) - - -def bitrev(x, width): - return int("{:0{w}b}".format(x, w=width)[::-1], 2) - - -parser = argparse.ArgumentParser() -parser.add_argument("ifile", help="Input file (binary)") -parser.add_argument("ofile", help="Output file (assembly)") -parser.add_argument("-p", "--pad", help="Padded size (bytes), including 4-byte checksum, default 256", - type=any_int, default=256) -parser.add_argument("-s", "--seed", help="Checksum seed value, default 0", - type=any_int, default=0) -args = parser.parse_args() - -try: - idata = open(args.ifile, "rb").read() -except: - sys.exit("Could not open input file '{}'".format(args.ifile)) - -if len(idata) > args.pad - 4: - sys.exit("Input file size ({} bytes) too large for final size ({} bytes)".format(len(idata), args.pad)) - -idata_padded = idata + bytes(args.pad - 4 - len(idata)) - -# Our bootrom CRC32 is slightly bass-ackward but it's best to work around for now (FIXME) -# 100% worth it to save two Thumb instructions -checksum = bitrev( - (binascii.crc32(bytes(bitrev(b, 8) for b in idata_padded), args.seed ^ 0xffffffff) ^ 0xffffffff) & 0xffffffff, 32) -odata = idata_padded + struct.pack(" - - - Raspberry Pi - RP2040 - RP - 0.1 - - Dual-core Arm Cortex-M0+ processor, flexible clock running up to 133 MHz - 264KB on-chip SRAM - 2 x UART, 2 x SPI controllers, 2 x I2C controllers, 16 x PWM channels - 1 x USB 1.1 controller and PHY, with host and device support - 8 x Programmable I/O (PIO) state machines for custom peripheral support - Supported input power 1.8-5.5V DC - Operating temperature -20C to +85C - Drag-and-drop programming using mass storage over USB - Low-power sleep and dormant modes - Accurate on-chip clock - Temperature sensor - Accelerated integer and floating-point libraries on-chip - - 32 - 32 - 0xffffffff - 0x00000000 - read-write - - Copyright (c) 2024 Raspberry Pi Ltd. - - SPDX-License-Identifier: BSD-3-Clause - - - CM0PLUS - r0p1 - little - true - false - 1 - 2 - false - 26 - - 8 - - - RESETS - 0x4000c000 - - 0 - 12 - registers - - - - RESET - 0x00000000 - Reset control. If a bit is set it means the peripheral is in reset. 0 means the peripheral's reset is deasserted. - 0x01ffffff - - - USBCTRL - [24:24] - read-write - - - UART1 - [23:23] - read-write - - - UART0 - [22:22] - read-write - - - TIMER - [21:21] - read-write - - - TBMAN - [20:20] - read-write - - - SYSINFO - [19:19] - read-write - - - SYSCFG - [18:18] - read-write - - - SPI1 - [17:17] - read-write - - - SPI0 - [16:16] - read-write - - - RTC - [15:15] - read-write - - - PWM - [14:14] - read-write - - - PLL_USB - [13:13] - read-write - - - PLL_SYS - [12:12] - read-write - - - PIO1 - [11:11] - read-write - - - PIO0 - [10:10] - read-write - - - PADS_QSPI - [9:9] - read-write - - - PADS_BANK0 - [8:8] - read-write - - - JTAG - [7:7] - read-write - - - IO_QSPI - [6:6] - read-write - - - IO_BANK0 - [5:5] - read-write - - - I2C1 - [4:4] - read-write - - - I2C0 - [3:3] - read-write - - - DMA - [2:2] - read-write - - - BUSCTRL - [1:1] - read-write - - - ADC - [0:0] - read-write - - - - - WDSEL - 0x00000004 - Watchdog select. If a bit is set then the watchdog will reset this peripheral when the watchdog fires. - 0x00000000 - - - USBCTRL - [24:24] - read-write - - - UART1 - [23:23] - read-write - - - UART0 - [22:22] - read-write - - - TIMER - [21:21] - read-write - - - TBMAN - [20:20] - read-write - - - SYSINFO - [19:19] - read-write - - - SYSCFG - [18:18] - read-write - - - SPI1 - [17:17] - read-write - - - SPI0 - [16:16] - read-write - - - RTC - [15:15] - read-write - - - PWM - [14:14] - read-write - - - PLL_USB - [13:13] - read-write - - - PLL_SYS - [12:12] - read-write - - - PIO1 - [11:11] - read-write - - - PIO0 - [10:10] - read-write - - - PADS_QSPI - [9:9] - read-write - - - PADS_BANK0 - [8:8] - read-write - - - JTAG - [7:7] - read-write - - - IO_QSPI - [6:6] - read-write - - - IO_BANK0 - [5:5] - read-write - - - I2C1 - [4:4] - read-write - - - I2C0 - [3:3] - read-write - - - DMA - [2:2] - read-write - - - BUSCTRL - [1:1] - read-write - - - ADC - [0:0] - read-write - - - - - RESET_DONE - 0x00000008 - Reset done. If a bit is set then a reset done signal has been returned by the peripheral. This indicates that the peripheral's registers are ready to be accessed. - 0x00000000 - - - USBCTRL - [24:24] - read-only - - - UART1 - [23:23] - read-only - - - UART0 - [22:22] - read-only - - - TIMER - [21:21] - read-only - - - TBMAN - [20:20] - read-only - - - SYSINFO - [19:19] - read-only - - - SYSCFG - [18:18] - read-only - - - SPI1 - [17:17] - read-only - - - SPI0 - [16:16] - read-only - - - RTC - [15:15] - read-only - - - PWM - [14:14] - read-only - - - PLL_USB - [13:13] - read-only - - - PLL_SYS - [12:12] - read-only - - - PIO1 - [11:11] - read-only - - - PIO0 - [10:10] - read-only - - - PADS_QSPI - [9:9] - read-only - - - PADS_BANK0 - [8:8] - read-only - - - JTAG - [7:7] - read-only - - - IO_QSPI - [6:6] - read-only - - - IO_BANK0 - [5:5] - read-only - - - I2C1 - [4:4] - read-only - - - I2C0 - [3:3] - read-only - - - DMA - [2:2] - read-only - - - BUSCTRL - [1:1] - read-only - - - ADC - [0:0] - read-only - - - - - - - PSM - 0x40010000 - - 0 - 16 - registers - - - - FRCE_ON - 0x00000000 - Force block out of reset (i.e. power it on) - 0x00000000 - - - PROC1 - [16:16] - read-write - - - PROC0 - [15:15] - read-write - - - SIO - [14:14] - read-write - - - VREG_AND_CHIP_RESET - [13:13] - read-write - - - XIP - [12:12] - read-write - - - SRAM5 - [11:11] - read-write - - - SRAM4 - [10:10] - read-write - - - SRAM3 - [9:9] - read-write - - - SRAM2 - [8:8] - read-write - - - SRAM1 - [7:7] - read-write - - - SRAM0 - [6:6] - read-write - - - ROM - [5:5] - read-write - - - BUSFABRIC - [4:4] - read-write - - - RESETS - [3:3] - read-write - - - CLOCKS - [2:2] - read-write - - - XOSC - [1:1] - read-write - - - ROSC - [0:0] - read-write - - - - - FRCE_OFF - 0x00000004 - Force into reset (i.e. power it off) - 0x00000000 - - - PROC1 - [16:16] - read-write - - - PROC0 - [15:15] - read-write - - - SIO - [14:14] - read-write - - - VREG_AND_CHIP_RESET - [13:13] - read-write - - - XIP - [12:12] - read-write - - - SRAM5 - [11:11] - read-write - - - SRAM4 - [10:10] - read-write - - - SRAM3 - [9:9] - read-write - - - SRAM2 - [8:8] - read-write - - - SRAM1 - [7:7] - read-write - - - SRAM0 - [6:6] - read-write - - - ROM - [5:5] - read-write - - - BUSFABRIC - [4:4] - read-write - - - RESETS - [3:3] - read-write - - - CLOCKS - [2:2] - read-write - - - XOSC - [1:1] - read-write - - - ROSC - [0:0] - read-write - - - - - WDSEL - 0x00000008 - Set to 1 if this peripheral should be reset when the watchdog fires. - 0x00000000 - - - PROC1 - [16:16] - read-write - - - PROC0 - [15:15] - read-write - - - SIO - [14:14] - read-write - - - VREG_AND_CHIP_RESET - [13:13] - read-write - - - XIP - [12:12] - read-write - - - SRAM5 - [11:11] - read-write - - - SRAM4 - [10:10] - read-write - - - SRAM3 - [9:9] - read-write - - - SRAM2 - [8:8] - read-write - - - SRAM1 - [7:7] - read-write - - - SRAM0 - [6:6] - read-write - - - ROM - [5:5] - read-write - - - BUSFABRIC - [4:4] - read-write - - - RESETS - [3:3] - read-write - - - CLOCKS - [2:2] - read-write - - - XOSC - [1:1] - read-write - - - ROSC - [0:0] - read-write - - - - - DONE - 0x0000000c - Indicates the peripheral's registers are ready to access. - 0x00000000 - - - PROC1 - [16:16] - read-only - - - PROC0 - [15:15] - read-only - - - SIO - [14:14] - read-only - - - VREG_AND_CHIP_RESET - [13:13] - read-only - - - XIP - [12:12] - read-only - - - SRAM5 - [11:11] - read-only - - - SRAM4 - [10:10] - read-only - - - SRAM3 - [9:9] - read-only - - - SRAM2 - [8:8] - read-only - - - SRAM1 - [7:7] - read-only - - - SRAM0 - [6:6] - read-only - - - ROM - [5:5] - read-only - - - BUSFABRIC - [4:4] - read-only - - - RESETS - [3:3] - read-only - - - CLOCKS - [2:2] - read-only - - - XOSC - [1:1] - read-only - - - ROSC - [0:0] - read-only - - - - - - - CLOCKS - 0x40008000 - - 0 - 200 - registers - - - CLOCKS_IRQ - 17 - - - - CLK_GPOUT0_CTRL - 0x00000000 - Clock control, can be changed on-the-fly (except for auxsrc) - 0x00000000 - - - NUDGE - An edge on this signal shifts the phase of the output by 1 cycle of the input clock - This can be done at any time - [20:20] - read-write - - - PHASE - This delays the enable signal by up to 3 cycles of the input clock - This must be set before the clock is enabled to have any effect - [17:16] - read-write - - - DC50 - Enables duty cycle correction for odd divisors - [12:12] - read-write - - - ENABLE - Starts and stops the clock generator cleanly - [11:11] - read-write - - - KILL - Asynchronously kills the clock generator - [10:10] - read-write - - - AUXSRC - Selects the auxiliary clock source, will glitch when switching - [8:5] - read-write - - - clksrc_pll_sys - 0 - - - clksrc_gpin0 - 1 - - - clksrc_gpin1 - 2 - - - clksrc_pll_usb - 3 - - - rosc_clksrc - 4 - - - xosc_clksrc - 5 - - - clk_sys - 6 - - - clk_usb - 7 - - - clk_adc - 8 - - - clk_rtc - 9 - - - clk_ref - 10 - - - - - - - CLK_GPOUT0_DIV - 0x00000004 - Clock divisor, can be changed on-the-fly - 0x00000100 - - - INT - Integer component of the divisor, 0 -> divide by 2^16 - [31:8] - read-write - - - FRAC - Fractional component of the divisor - [7:0] - read-write - - - - - CLK_GPOUT0_SELECTED - 0x00000008 - Indicates which SRC is currently selected by the glitchless mux (one-hot). - 0x00000001 - - - CLK_GPOUT0_SELECTED - This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. - [31:0] - read-only - - - - - CLK_GPOUT1_CTRL - 0x0000000c - Clock control, can be changed on-the-fly (except for auxsrc) - 0x00000000 - - - NUDGE - An edge on this signal shifts the phase of the output by 1 cycle of the input clock - This can be done at any time - [20:20] - read-write - - - PHASE - This delays the enable signal by up to 3 cycles of the input clock - This must be set before the clock is enabled to have any effect - [17:16] - read-write - - - DC50 - Enables duty cycle correction for odd divisors - [12:12] - read-write - - - ENABLE - Starts and stops the clock generator cleanly - [11:11] - read-write - - - KILL - Asynchronously kills the clock generator - [10:10] - read-write - - - AUXSRC - Selects the auxiliary clock source, will glitch when switching - [8:5] - read-write - - - clksrc_pll_sys - 0 - - - clksrc_gpin0 - 1 - - - clksrc_gpin1 - 2 - - - clksrc_pll_usb - 3 - - - rosc_clksrc - 4 - - - xosc_clksrc - 5 - - - clk_sys - 6 - - - clk_usb - 7 - - - clk_adc - 8 - - - clk_rtc - 9 - - - clk_ref - 10 - - - - - - - CLK_GPOUT1_DIV - 0x00000010 - Clock divisor, can be changed on-the-fly - 0x00000100 - - - INT - Integer component of the divisor, 0 -> divide by 2^16 - [31:8] - read-write - - - FRAC - Fractional component of the divisor - [7:0] - read-write - - - - - CLK_GPOUT1_SELECTED - 0x00000014 - Indicates which SRC is currently selected by the glitchless mux (one-hot). - 0x00000001 - - - CLK_GPOUT1_SELECTED - This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. - [31:0] - read-only - - - - - CLK_GPOUT2_CTRL - 0x00000018 - Clock control, can be changed on-the-fly (except for auxsrc) - 0x00000000 - - - NUDGE - An edge on this signal shifts the phase of the output by 1 cycle of the input clock - This can be done at any time - [20:20] - read-write - - - PHASE - This delays the enable signal by up to 3 cycles of the input clock - This must be set before the clock is enabled to have any effect - [17:16] - read-write - - - DC50 - Enables duty cycle correction for odd divisors - [12:12] - read-write - - - ENABLE - Starts and stops the clock generator cleanly - [11:11] - read-write - - - KILL - Asynchronously kills the clock generator - [10:10] - read-write - - - AUXSRC - Selects the auxiliary clock source, will glitch when switching - [8:5] - read-write - - - clksrc_pll_sys - 0 - - - clksrc_gpin0 - 1 - - - clksrc_gpin1 - 2 - - - clksrc_pll_usb - 3 - - - rosc_clksrc_ph - 4 - - - xosc_clksrc - 5 - - - clk_sys - 6 - - - clk_usb - 7 - - - clk_adc - 8 - - - clk_rtc - 9 - - - clk_ref - 10 - - - - - - - CLK_GPOUT2_DIV - 0x0000001c - Clock divisor, can be changed on-the-fly - 0x00000100 - - - INT - Integer component of the divisor, 0 -> divide by 2^16 - [31:8] - read-write - - - FRAC - Fractional component of the divisor - [7:0] - read-write - - - - - CLK_GPOUT2_SELECTED - 0x00000020 - Indicates which SRC is currently selected by the glitchless mux (one-hot). - 0x00000001 - - - CLK_GPOUT2_SELECTED - This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. - [31:0] - read-only - - - - - CLK_GPOUT3_CTRL - 0x00000024 - Clock control, can be changed on-the-fly (except for auxsrc) - 0x00000000 - - - NUDGE - An edge on this signal shifts the phase of the output by 1 cycle of the input clock - This can be done at any time - [20:20] - read-write - - - PHASE - This delays the enable signal by up to 3 cycles of the input clock - This must be set before the clock is enabled to have any effect - [17:16] - read-write - - - DC50 - Enables duty cycle correction for odd divisors - [12:12] - read-write - - - ENABLE - Starts and stops the clock generator cleanly - [11:11] - read-write - - - KILL - Asynchronously kills the clock generator - [10:10] - read-write - - - AUXSRC - Selects the auxiliary clock source, will glitch when switching - [8:5] - read-write - - - clksrc_pll_sys - 0 - - - clksrc_gpin0 - 1 - - - clksrc_gpin1 - 2 - - - clksrc_pll_usb - 3 - - - rosc_clksrc_ph - 4 - - - xosc_clksrc - 5 - - - clk_sys - 6 - - - clk_usb - 7 - - - clk_adc - 8 - - - clk_rtc - 9 - - - clk_ref - 10 - - - - - - - CLK_GPOUT3_DIV - 0x00000028 - Clock divisor, can be changed on-the-fly - 0x00000100 - - - INT - Integer component of the divisor, 0 -> divide by 2^16 - [31:8] - read-write - - - FRAC - Fractional component of the divisor - [7:0] - read-write - - - - - CLK_GPOUT3_SELECTED - 0x0000002c - Indicates which SRC is currently selected by the glitchless mux (one-hot). - 0x00000001 - - - CLK_GPOUT3_SELECTED - This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. - [31:0] - read-only - - - - - CLK_REF_CTRL - 0x00000030 - Clock control, can be changed on-the-fly (except for auxsrc) - 0x00000000 - - - AUXSRC - Selects the auxiliary clock source, will glitch when switching - [6:5] - read-write - - - clksrc_pll_usb - 0 - - - clksrc_gpin0 - 1 - - - clksrc_gpin1 - 2 - - - - - SRC - Selects the clock source glitchlessly, can be changed on-the-fly - [1:0] - read-write - - - rosc_clksrc_ph - 0 - - - clksrc_clk_ref_aux - 1 - - - xosc_clksrc - 2 - - - - - - - CLK_REF_DIV - 0x00000034 - Clock divisor, can be changed on-the-fly - 0x00000100 - - - INT - Integer component of the divisor, 0 -> divide by 2^16 - [9:8] - read-write - - - - - CLK_REF_SELECTED - 0x00000038 - Indicates which SRC is currently selected by the glitchless mux (one-hot). - 0x00000001 - - - CLK_REF_SELECTED - The glitchless multiplexer does not switch instantaneously (to avoid glitches), so software should poll this register to wait for the switch to complete. This register contains one decoded bit for each of the clock sources enumerated in the CTRL SRC field. At most one of these bits will be set at any time, indicating that clock is currently present at the output of the glitchless mux. Whilst switching is in progress, this register may briefly show all-0s. - [31:0] - read-only - - - - - CLK_SYS_CTRL - 0x0000003c - Clock control, can be changed on-the-fly (except for auxsrc) - 0x00000000 - - - AUXSRC - Selects the auxiliary clock source, will glitch when switching - [7:5] - read-write - - - clksrc_pll_sys - 0 - - - clksrc_pll_usb - 1 - - - rosc_clksrc - 2 - - - xosc_clksrc - 3 - - - clksrc_gpin0 - 4 - - - clksrc_gpin1 - 5 - - - - - SRC - Selects the clock source glitchlessly, can be changed on-the-fly - [0:0] - read-write - - - clk_ref - 0 - - - clksrc_clk_sys_aux - 1 - - - - - - - CLK_SYS_DIV - 0x00000040 - Clock divisor, can be changed on-the-fly - 0x00000100 - - - INT - Integer component of the divisor, 0 -> divide by 2^16 - [31:8] - read-write - - - FRAC - Fractional component of the divisor - [7:0] - read-write - - - - - CLK_SYS_SELECTED - 0x00000044 - Indicates which SRC is currently selected by the glitchless mux (one-hot). - 0x00000001 - - - CLK_SYS_SELECTED - The glitchless multiplexer does not switch instantaneously (to avoid glitches), so software should poll this register to wait for the switch to complete. This register contains one decoded bit for each of the clock sources enumerated in the CTRL SRC field. At most one of these bits will be set at any time, indicating that clock is currently present at the output of the glitchless mux. Whilst switching is in progress, this register may briefly show all-0s. - [31:0] - read-only - - - - - CLK_PERI_CTRL - 0x00000048 - Clock control, can be changed on-the-fly (except for auxsrc) - 0x00000000 - - - ENABLE - Starts and stops the clock generator cleanly - [11:11] - read-write - - - KILL - Asynchronously kills the clock generator - [10:10] - read-write - - - AUXSRC - Selects the auxiliary clock source, will glitch when switching - [7:5] - read-write - - - clk_sys - 0 - - - clksrc_pll_sys - 1 - - - clksrc_pll_usb - 2 - - - rosc_clksrc_ph - 3 - - - xosc_clksrc - 4 - - - clksrc_gpin0 - 5 - - - clksrc_gpin1 - 6 - - - - - - - CLK_PERI_DIV - 0x0000004c - Clock divisor, can be changed on-the-fly - 0x00000100 - - - INT - Integer component of the divisor, 0 -> divide by 2^16 - [31:8] - read-write - - - FRAC - Fractional component of the divisor - [7:0] - read-write - - - - - CLK_PERI_SELECTED - 0x00000050 - Indicates which SRC is currently selected by the glitchless mux (one-hot). - 0x00000001 - - - CLK_PERI_SELECTED - This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. - [31:0] - read-only - - - - - CLK_USB_CTRL - 0x00000054 - Clock control, can be changed on-the-fly (except for auxsrc) - 0x00000000 - - - NUDGE - An edge on this signal shifts the phase of the output by 1 cycle of the input clock - This can be done at any time - [20:20] - read-write - - - PHASE - This delays the enable signal by up to 3 cycles of the input clock - This must be set before the clock is enabled to have any effect - [17:16] - read-write - - - ENABLE - Starts and stops the clock generator cleanly - [11:11] - read-write - - - KILL - Asynchronously kills the clock generator - [10:10] - read-write - - - AUXSRC - Selects the auxiliary clock source, will glitch when switching - [7:5] - read-write - - - clksrc_pll_usb - 0 - - - clksrc_pll_sys - 1 - - - rosc_clksrc_ph - 2 - - - xosc_clksrc - 3 - - - clksrc_gpin0 - 4 - - - clksrc_gpin1 - 5 - - - - - - - CLK_USB_DIV - 0x00000058 - Clock divisor, can be changed on-the-fly - 0x00000100 - - - INT - Integer component of the divisor, 0 -> divide by 2^16 - [9:8] - read-write - - - - - CLK_USB_SELECTED - 0x0000005c - Indicates which SRC is currently selected by the glitchless mux (one-hot). - 0x00000001 - - - CLK_USB_SELECTED - This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. - [31:0] - read-only - - - - - CLK_ADC_CTRL - 0x00000060 - Clock control, can be changed on-the-fly (except for auxsrc) - 0x00000000 - - - NUDGE - An edge on this signal shifts the phase of the output by 1 cycle of the input clock - This can be done at any time - [20:20] - read-write - - - PHASE - This delays the enable signal by up to 3 cycles of the input clock - This must be set before the clock is enabled to have any effect - [17:16] - read-write - - - ENABLE - Starts and stops the clock generator cleanly - [11:11] - read-write - - - KILL - Asynchronously kills the clock generator - [10:10] - read-write - - - AUXSRC - Selects the auxiliary clock source, will glitch when switching - [7:5] - read-write - - - clksrc_pll_usb - 0 - - - clksrc_pll_sys - 1 - - - rosc_clksrc_ph - 2 - - - xosc_clksrc - 3 - - - clksrc_gpin0 - 4 - - - clksrc_gpin1 - 5 - - - - - - - CLK_ADC_DIV - 0x00000064 - Clock divisor, can be changed on-the-fly - 0x00000100 - - - INT - Integer component of the divisor, 0 -> divide by 2^16 - [9:8] - read-write - - - - - CLK_ADC_SELECTED - 0x00000068 - Indicates which SRC is currently selected by the glitchless mux (one-hot). - 0x00000001 - - - CLK_ADC_SELECTED - This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. - [31:0] - read-only - - - - - CLK_RTC_CTRL - 0x0000006c - Clock control, can be changed on-the-fly (except for auxsrc) - 0x00000000 - - - NUDGE - An edge on this signal shifts the phase of the output by 1 cycle of the input clock - This can be done at any time - [20:20] - read-write - - - PHASE - This delays the enable signal by up to 3 cycles of the input clock - This must be set before the clock is enabled to have any effect - [17:16] - read-write - - - ENABLE - Starts and stops the clock generator cleanly - [11:11] - read-write - - - KILL - Asynchronously kills the clock generator - [10:10] - read-write - - - AUXSRC - Selects the auxiliary clock source, will glitch when switching - [7:5] - read-write - - - clksrc_pll_usb - 0 - - - clksrc_pll_sys - 1 - - - rosc_clksrc_ph - 2 - - - xosc_clksrc - 3 - - - clksrc_gpin0 - 4 - - - clksrc_gpin1 - 5 - - - - - - - CLK_RTC_DIV - 0x00000070 - Clock divisor, can be changed on-the-fly - 0x00000100 - - - INT - Integer component of the divisor, 0 -> divide by 2^16 - [31:8] - read-write - - - FRAC - Fractional component of the divisor - [7:0] - read-write - - - - - CLK_RTC_SELECTED - 0x00000074 - Indicates which SRC is currently selected by the glitchless mux (one-hot). - 0x00000001 - - - CLK_RTC_SELECTED - This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. - [31:0] - read-only - - - - - CLK_SYS_RESUS_CTRL - 0x00000078 - 0x000000ff - - - CLEAR - For clearing the resus after the fault that triggered it has been corrected - [16:16] - read-write - - - FRCE - Force a resus, for test purposes only - [12:12] - read-write - - - ENABLE - Enable resus - [8:8] - read-write - - - TIMEOUT - This is expressed as a number of clk_ref cycles - and must be >= 2x clk_ref_freq/min_clk_tst_freq - [7:0] - read-write - - - - - CLK_SYS_RESUS_STATUS - 0x0000007c - 0x00000000 - - - RESUSSED - Clock has been resuscitated, correct the error then send ctrl_clear=1 - [0:0] - read-only - - - - - FC0_REF_KHZ - 0x00000080 - Reference clock frequency in kHz - 0x00000000 - - - FC0_REF_KHZ - [19:0] - read-write - - - - - FC0_MIN_KHZ - 0x00000084 - Minimum pass frequency in kHz. This is optional. Set to 0 if you are not using the pass/fail flags - 0x00000000 - - - FC0_MIN_KHZ - [24:0] - read-write - - - - - FC0_MAX_KHZ - 0x00000088 - Maximum pass frequency in kHz. This is optional. Set to 0x1ffffff if you are not using the pass/fail flags - 0x01ffffff - - - FC0_MAX_KHZ - [24:0] - read-write - - - - - FC0_DELAY - 0x0000008c - Delays the start of frequency counting to allow the mux to settle - Delay is measured in multiples of the reference clock period - 0x00000001 - - - FC0_DELAY - [2:0] - read-write - - - - - FC0_INTERVAL - 0x00000090 - The test interval is 0.98us * 2**interval, but let's call it 1us * 2**interval - The default gives a test interval of 250us - 0x00000008 - - - FC0_INTERVAL - [3:0] - read-write - - - - - FC0_SRC - 0x00000094 - Clock sent to frequency counter, set to 0 when not required - Writing to this register initiates the frequency count - 0x00000000 - - - FC0_SRC - [7:0] - read-write - - - NULL - 0 - - - pll_sys_clksrc_primary - 1 - - - pll_usb_clksrc_primary - 2 - - - rosc_clksrc - 3 - - - rosc_clksrc_ph - 4 - - - xosc_clksrc - 5 - - - clksrc_gpin0 - 6 - - - clksrc_gpin1 - 7 - - - clk_ref - 8 - - - clk_sys - 9 - - - clk_peri - 10 - - - clk_usb - 11 - - - clk_adc - 12 - - - clk_rtc - 13 - - - - - - - FC0_STATUS - 0x00000098 - Frequency counter status - 0x00000000 - - - DIED - Test clock stopped during test - [28:28] - read-only - - - FAST - Test clock faster than expected, only valid when status_done=1 - [24:24] - read-only - - - SLOW - Test clock slower than expected, only valid when status_done=1 - [20:20] - read-only - - - FAIL - Test failed - [16:16] - read-only - - - WAITING - Waiting for test clock to start - [12:12] - read-only - - - RUNNING - Test running - [8:8] - read-only - - - DONE - Test complete - [4:4] - read-only - - - PASS - Test passed - [0:0] - read-only - - - - - FC0_RESULT - 0x0000009c - Result of frequency measurement, only valid when status_done=1 - 0x00000000 - - - KHZ - [29:5] - read-only - - - FRAC - [4:0] - read-only - - - - - WAKE_EN0 - 0x000000a0 - enable clock in wake mode - 0xffffffff - - - CLK_SYS_SRAM3 - [31:31] - read-write - - - CLK_SYS_SRAM2 - [30:30] - read-write - - - CLK_SYS_SRAM1 - [29:29] - read-write - - - CLK_SYS_SRAM0 - [28:28] - read-write - - - CLK_SYS_SPI1 - [27:27] - read-write - - - CLK_PERI_SPI1 - [26:26] - read-write - - - CLK_SYS_SPI0 - [25:25] - read-write - - - CLK_PERI_SPI0 - [24:24] - read-write - - - CLK_SYS_SIO - [23:23] - read-write - - - CLK_SYS_RTC - [22:22] - read-write - - - CLK_RTC_RTC - [21:21] - read-write - - - CLK_SYS_ROSC - [20:20] - read-write - - - CLK_SYS_ROM - [19:19] - read-write - - - CLK_SYS_RESETS - [18:18] - read-write - - - CLK_SYS_PWM - [17:17] - read-write - - - CLK_SYS_PSM - [16:16] - read-write - - - CLK_SYS_PLL_USB - [15:15] - read-write - - - CLK_SYS_PLL_SYS - [14:14] - read-write - - - CLK_SYS_PIO1 - [13:13] - read-write - - - CLK_SYS_PIO0 - [12:12] - read-write - - - CLK_SYS_PADS - [11:11] - read-write - - - CLK_SYS_VREG_AND_CHIP_RESET - [10:10] - read-write - - - CLK_SYS_JTAG - [9:9] - read-write - - - CLK_SYS_IO - [8:8] - read-write - - - CLK_SYS_I2C1 - [7:7] - read-write - - - CLK_SYS_I2C0 - [6:6] - read-write - - - CLK_SYS_DMA - [5:5] - read-write - - - CLK_SYS_BUSFABRIC - [4:4] - read-write - - - CLK_SYS_BUSCTRL - [3:3] - read-write - - - CLK_SYS_ADC - [2:2] - read-write - - - CLK_ADC_ADC - [1:1] - read-write - - - CLK_SYS_CLOCKS - [0:0] - read-write - - - - - WAKE_EN1 - 0x000000a4 - enable clock in wake mode - 0x00007fff - - - CLK_SYS_XOSC - [14:14] - read-write - - - CLK_SYS_XIP - [13:13] - read-write - - - CLK_SYS_WATCHDOG - [12:12] - read-write - - - CLK_USB_USBCTRL - [11:11] - read-write - - - CLK_SYS_USBCTRL - [10:10] - read-write - - - CLK_SYS_UART1 - [9:9] - read-write - - - CLK_PERI_UART1 - [8:8] - read-write - - - CLK_SYS_UART0 - [7:7] - read-write - - - CLK_PERI_UART0 - [6:6] - read-write - - - CLK_SYS_TIMER - [5:5] - read-write - - - CLK_SYS_TBMAN - [4:4] - read-write - - - CLK_SYS_SYSINFO - [3:3] - read-write - - - CLK_SYS_SYSCFG - [2:2] - read-write - - - CLK_SYS_SRAM5 - [1:1] - read-write - - - CLK_SYS_SRAM4 - [0:0] - read-write - - - - - SLEEP_EN0 - 0x000000a8 - enable clock in sleep mode - 0xffffffff - - - CLK_SYS_SRAM3 - [31:31] - read-write - - - CLK_SYS_SRAM2 - [30:30] - read-write - - - CLK_SYS_SRAM1 - [29:29] - read-write - - - CLK_SYS_SRAM0 - [28:28] - read-write - - - CLK_SYS_SPI1 - [27:27] - read-write - - - CLK_PERI_SPI1 - [26:26] - read-write - - - CLK_SYS_SPI0 - [25:25] - read-write - - - CLK_PERI_SPI0 - [24:24] - read-write - - - CLK_SYS_SIO - [23:23] - read-write - - - CLK_SYS_RTC - [22:22] - read-write - - - CLK_RTC_RTC - [21:21] - read-write - - - CLK_SYS_ROSC - [20:20] - read-write - - - CLK_SYS_ROM - [19:19] - read-write - - - CLK_SYS_RESETS - [18:18] - read-write - - - CLK_SYS_PWM - [17:17] - read-write - - - CLK_SYS_PSM - [16:16] - read-write - - - CLK_SYS_PLL_USB - [15:15] - read-write - - - CLK_SYS_PLL_SYS - [14:14] - read-write - - - CLK_SYS_PIO1 - [13:13] - read-write - - - CLK_SYS_PIO0 - [12:12] - read-write - - - CLK_SYS_PADS - [11:11] - read-write - - - CLK_SYS_VREG_AND_CHIP_RESET - [10:10] - read-write - - - CLK_SYS_JTAG - [9:9] - read-write - - - CLK_SYS_IO - [8:8] - read-write - - - CLK_SYS_I2C1 - [7:7] - read-write - - - CLK_SYS_I2C0 - [6:6] - read-write - - - CLK_SYS_DMA - [5:5] - read-write - - - CLK_SYS_BUSFABRIC - [4:4] - read-write - - - CLK_SYS_BUSCTRL - [3:3] - read-write - - - CLK_SYS_ADC - [2:2] - read-write - - - CLK_ADC_ADC - [1:1] - read-write - - - CLK_SYS_CLOCKS - [0:0] - read-write - - - - - SLEEP_EN1 - 0x000000ac - enable clock in sleep mode - 0x00007fff - - - CLK_SYS_XOSC - [14:14] - read-write - - - CLK_SYS_XIP - [13:13] - read-write - - - CLK_SYS_WATCHDOG - [12:12] - read-write - - - CLK_USB_USBCTRL - [11:11] - read-write - - - CLK_SYS_USBCTRL - [10:10] - read-write - - - CLK_SYS_UART1 - [9:9] - read-write - - - CLK_PERI_UART1 - [8:8] - read-write - - - CLK_SYS_UART0 - [7:7] - read-write - - - CLK_PERI_UART0 - [6:6] - read-write - - - CLK_SYS_TIMER - [5:5] - read-write - - - CLK_SYS_TBMAN - [4:4] - read-write - - - CLK_SYS_SYSINFO - [3:3] - read-write - - - CLK_SYS_SYSCFG - [2:2] - read-write - - - CLK_SYS_SRAM5 - [1:1] - read-write - - - CLK_SYS_SRAM4 - [0:0] - read-write - - - - - ENABLED0 - 0x000000b0 - indicates the state of the clock enable - 0x00000000 - - - CLK_SYS_SRAM3 - [31:31] - read-only - - - CLK_SYS_SRAM2 - [30:30] - read-only - - - CLK_SYS_SRAM1 - [29:29] - read-only - - - CLK_SYS_SRAM0 - [28:28] - read-only - - - CLK_SYS_SPI1 - [27:27] - read-only - - - CLK_PERI_SPI1 - [26:26] - read-only - - - CLK_SYS_SPI0 - [25:25] - read-only - - - CLK_PERI_SPI0 - [24:24] - read-only - - - CLK_SYS_SIO - [23:23] - read-only - - - CLK_SYS_RTC - [22:22] - read-only - - - CLK_RTC_RTC - [21:21] - read-only - - - CLK_SYS_ROSC - [20:20] - read-only - - - CLK_SYS_ROM - [19:19] - read-only - - - CLK_SYS_RESETS - [18:18] - read-only - - - CLK_SYS_PWM - [17:17] - read-only - - - CLK_SYS_PSM - [16:16] - read-only - - - CLK_SYS_PLL_USB - [15:15] - read-only - - - CLK_SYS_PLL_SYS - [14:14] - read-only - - - CLK_SYS_PIO1 - [13:13] - read-only - - - CLK_SYS_PIO0 - [12:12] - read-only - - - CLK_SYS_PADS - [11:11] - read-only - - - CLK_SYS_VREG_AND_CHIP_RESET - [10:10] - read-only - - - CLK_SYS_JTAG - [9:9] - read-only - - - CLK_SYS_IO - [8:8] - read-only - - - CLK_SYS_I2C1 - [7:7] - read-only - - - CLK_SYS_I2C0 - [6:6] - read-only - - - CLK_SYS_DMA - [5:5] - read-only - - - CLK_SYS_BUSFABRIC - [4:4] - read-only - - - CLK_SYS_BUSCTRL - [3:3] - read-only - - - CLK_SYS_ADC - [2:2] - read-only - - - CLK_ADC_ADC - [1:1] - read-only - - - CLK_SYS_CLOCKS - [0:0] - read-only - - - - - ENABLED1 - 0x000000b4 - indicates the state of the clock enable - 0x00000000 - - - CLK_SYS_XOSC - [14:14] - read-only - - - CLK_SYS_XIP - [13:13] - read-only - - - CLK_SYS_WATCHDOG - [12:12] - read-only - - - CLK_USB_USBCTRL - [11:11] - read-only - - - CLK_SYS_USBCTRL - [10:10] - read-only - - - CLK_SYS_UART1 - [9:9] - read-only - - - CLK_PERI_UART1 - [8:8] - read-only - - - CLK_SYS_UART0 - [7:7] - read-only - - - CLK_PERI_UART0 - [6:6] - read-only - - - CLK_SYS_TIMER - [5:5] - read-only - - - CLK_SYS_TBMAN - [4:4] - read-only - - - CLK_SYS_SYSINFO - [3:3] - read-only - - - CLK_SYS_SYSCFG - [2:2] - read-only - - - CLK_SYS_SRAM5 - [1:1] - read-only - - - CLK_SYS_SRAM4 - [0:0] - read-only - - - - - INTR - 0x000000b8 - Raw Interrupts - 0x00000000 - - - CLK_SYS_RESUS - [0:0] - read-only - - - - - INTE - 0x000000bc - Interrupt Enable - 0x00000000 - - - CLK_SYS_RESUS - [0:0] - read-write - - - - - INTF - 0x000000c0 - Interrupt Force - 0x00000000 - - - CLK_SYS_RESUS - [0:0] - read-write - - - - - INTS - 0x000000c4 - Interrupt status after masking & forcing - 0x00000000 - - - CLK_SYS_RESUS - [0:0] - read-only - - - - - - - PADS_BANK0 - 0x4001c000 - - 0 - 132 - registers - - - - VOLTAGE_SELECT - 0x00000000 - Voltage select. Per bank control - 0x00000000 - - - VOLTAGE_SELECT - [0:0] - read-write - - - 3v3 - 0 - Set voltage to 3.3V (DVDD >= 2V5) - - - 1v8 - 1 - Set voltage to 1.8V (DVDD <= 1V8) - - - - - - - GPIO0 - 0x00000004 - Pad control register - 0x00000056 - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - GPIO1 - 0x00000008 - Pad control register - 0x00000056 - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - GPIO2 - 0x0000000c - Pad control register - 0x00000056 - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - GPIO3 - 0x00000010 - Pad control register - 0x00000056 - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - GPIO4 - 0x00000014 - Pad control register - 0x00000056 - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - GPIO5 - 0x00000018 - Pad control register - 0x00000056 - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - GPIO6 - 0x0000001c - Pad control register - 0x00000056 - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - GPIO7 - 0x00000020 - Pad control register - 0x00000056 - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - GPIO8 - 0x00000024 - Pad control register - 0x00000056 - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - GPIO9 - 0x00000028 - Pad control register - 0x00000056 - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - GPIO10 - 0x0000002c - Pad control register - 0x00000056 - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - GPIO11 - 0x00000030 - Pad control register - 0x00000056 - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - GPIO12 - 0x00000034 - Pad control register - 0x00000056 - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - GPIO13 - 0x00000038 - Pad control register - 0x00000056 - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - GPIO14 - 0x0000003c - Pad control register - 0x00000056 - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - GPIO15 - 0x00000040 - Pad control register - 0x00000056 - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - GPIO16 - 0x00000044 - Pad control register - 0x00000056 - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - GPIO17 - 0x00000048 - Pad control register - 0x00000056 - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - GPIO18 - 0x0000004c - Pad control register - 0x00000056 - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - GPIO19 - 0x00000050 - Pad control register - 0x00000056 - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - GPIO20 - 0x00000054 - Pad control register - 0x00000056 - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - GPIO21 - 0x00000058 - Pad control register - 0x00000056 - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - GPIO22 - 0x0000005c - Pad control register - 0x00000056 - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - GPIO23 - 0x00000060 - Pad control register - 0x00000056 - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - GPIO24 - 0x00000064 - Pad control register - 0x00000056 - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - GPIO25 - 0x00000068 - Pad control register - 0x00000056 - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - GPIO26 - 0x0000006c - Pad control register - 0x00000056 - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - GPIO27 - 0x00000070 - Pad control register - 0x00000056 - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - GPIO28 - 0x00000074 - Pad control register - 0x00000056 - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - GPIO29 - 0x00000078 - Pad control register - 0x00000056 - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - SWCLK - 0x0000007c - Pad control register - 0x000000da - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - SWD - 0x00000080 - Pad control register - 0x0000005a - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - - - PADS_QSPI - 0x40020000 - - 0 - 28 - registers - - - - VOLTAGE_SELECT - 0x00000000 - Voltage select. Per bank control - 0x00000000 - - - VOLTAGE_SELECT - [0:0] - read-write - - - 3v3 - 0 - Set voltage to 3.3V (DVDD >= 2V5) - - - 1v8 - 1 - Set voltage to 1.8V (DVDD <= 1V8) - - - - - - - GPIO_QSPI_SCLK - 0x00000004 - Pad control register - 0x00000056 - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - GPIO_QSPI_SD0 - 0x00000008 - Pad control register - 0x00000052 - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - GPIO_QSPI_SD1 - 0x0000000c - Pad control register - 0x00000052 - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - GPIO_QSPI_SD2 - 0x00000010 - Pad control register - 0x00000052 - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - GPIO_QSPI_SD3 - 0x00000014 - Pad control register - 0x00000052 - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - GPIO_QSPI_SS - 0x00000018 - Pad control register - 0x0000005a - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - - - IO_QSPI - 0x40018000 - - 0 - 88 - registers - - - IO_IRQ_QSPI - 14 - - - - GPIO_QSPI_SCLK_STATUS - 0x00000000 - GPIO status - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - IRQFROMPAD - interrupt from pad before override is applied - [24:24] - read-only - - - INTOPERI - input signal to peripheral, after override is applied - [19:19] - read-only - - - INFROMPAD - input signal from pad, before override is applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OEFROMPERI - output enable from selected peripheral, before register override is applied - [12:12] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - OUTFROMPERI - output signal from selected peripheral, before register override is applied - [8:8] - read-only - - - - - GPIO_QSPI_SCLK_CTRL - 0x00000004 - GPIO control including function select and overrides. - 0x0000001f - - - IRQOVER - [29:28] - read-write - - - NORMAL - 0 - don't invert the interrupt - - - INVERT - 1 - invert the interrupt - - - LOW - 2 - drive interrupt low - - - HIGH - 3 - drive interrupt high - - - - - INOVER - [17:16] - read-write - - - NORMAL - 0 - don't invert the peri input - - - INVERT - 1 - invert the peri input - - - LOW - 2 - drive peri input low - - - HIGH - 3 - drive peri input high - - - - - OEOVER - [13:12] - read-write - - - NORMAL - 0 - drive output enable from peripheral signal selected by funcsel - - - INVERT - 1 - drive output enable from inverse of peripheral signal selected by funcsel - - - DISABLE - 2 - disable output - - - ENABLE - 3 - enable output - - - - - OUTOVER - [9:8] - read-write - - - NORMAL - 0 - drive output from peripheral signal selected by funcsel - - - INVERT - 1 - drive output from inverse of peripheral signal selected by funcsel - - - LOW - 2 - drive output low - - - HIGH - 3 - drive output high - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table - 31 == NULL - [4:0] - read-write - - - xip_sclk - 0 - - - sio_30 - 5 - - - null - 31 - - - - - - - GPIO_QSPI_SS_STATUS - 0x00000008 - GPIO status - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - IRQFROMPAD - interrupt from pad before override is applied - [24:24] - read-only - - - INTOPERI - input signal to peripheral, after override is applied - [19:19] - read-only - - - INFROMPAD - input signal from pad, before override is applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OEFROMPERI - output enable from selected peripheral, before register override is applied - [12:12] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - OUTFROMPERI - output signal from selected peripheral, before register override is applied - [8:8] - read-only - - - - - GPIO_QSPI_SS_CTRL - 0x0000000c - GPIO control including function select and overrides. - 0x0000001f - - - IRQOVER - [29:28] - read-write - - - NORMAL - 0 - don't invert the interrupt - - - INVERT - 1 - invert the interrupt - - - LOW - 2 - drive interrupt low - - - HIGH - 3 - drive interrupt high - - - - - INOVER - [17:16] - read-write - - - NORMAL - 0 - don't invert the peri input - - - INVERT - 1 - invert the peri input - - - LOW - 2 - drive peri input low - - - HIGH - 3 - drive peri input high - - - - - OEOVER - [13:12] - read-write - - - NORMAL - 0 - drive output enable from peripheral signal selected by funcsel - - - INVERT - 1 - drive output enable from inverse of peripheral signal selected by funcsel - - - DISABLE - 2 - disable output - - - ENABLE - 3 - enable output - - - - - OUTOVER - [9:8] - read-write - - - NORMAL - 0 - drive output from peripheral signal selected by funcsel - - - INVERT - 1 - drive output from inverse of peripheral signal selected by funcsel - - - LOW - 2 - drive output low - - - HIGH - 3 - drive output high - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table - 31 == NULL - [4:0] - read-write - - - xip_ss_n - 0 - - - sio_31 - 5 - - - null - 31 - - - - - - - GPIO_QSPI_SD0_STATUS - 0x00000010 - GPIO status - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - IRQFROMPAD - interrupt from pad before override is applied - [24:24] - read-only - - - INTOPERI - input signal to peripheral, after override is applied - [19:19] - read-only - - - INFROMPAD - input signal from pad, before override is applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OEFROMPERI - output enable from selected peripheral, before register override is applied - [12:12] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - OUTFROMPERI - output signal from selected peripheral, before register override is applied - [8:8] - read-only - - - - - GPIO_QSPI_SD0_CTRL - 0x00000014 - GPIO control including function select and overrides. - 0x0000001f - - - IRQOVER - [29:28] - read-write - - - NORMAL - 0 - don't invert the interrupt - - - INVERT - 1 - invert the interrupt - - - LOW - 2 - drive interrupt low - - - HIGH - 3 - drive interrupt high - - - - - INOVER - [17:16] - read-write - - - NORMAL - 0 - don't invert the peri input - - - INVERT - 1 - invert the peri input - - - LOW - 2 - drive peri input low - - - HIGH - 3 - drive peri input high - - - - - OEOVER - [13:12] - read-write - - - NORMAL - 0 - drive output enable from peripheral signal selected by funcsel - - - INVERT - 1 - drive output enable from inverse of peripheral signal selected by funcsel - - - DISABLE - 2 - disable output - - - ENABLE - 3 - enable output - - - - - OUTOVER - [9:8] - read-write - - - NORMAL - 0 - drive output from peripheral signal selected by funcsel - - - INVERT - 1 - drive output from inverse of peripheral signal selected by funcsel - - - LOW - 2 - drive output low - - - HIGH - 3 - drive output high - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table - 31 == NULL - [4:0] - read-write - - - xip_sd0 - 0 - - - sio_32 - 5 - - - null - 31 - - - - - - - GPIO_QSPI_SD1_STATUS - 0x00000018 - GPIO status - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - IRQFROMPAD - interrupt from pad before override is applied - [24:24] - read-only - - - INTOPERI - input signal to peripheral, after override is applied - [19:19] - read-only - - - INFROMPAD - input signal from pad, before override is applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OEFROMPERI - output enable from selected peripheral, before register override is applied - [12:12] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - OUTFROMPERI - output signal from selected peripheral, before register override is applied - [8:8] - read-only - - - - - GPIO_QSPI_SD1_CTRL - 0x0000001c - GPIO control including function select and overrides. - 0x0000001f - - - IRQOVER - [29:28] - read-write - - - NORMAL - 0 - don't invert the interrupt - - - INVERT - 1 - invert the interrupt - - - LOW - 2 - drive interrupt low - - - HIGH - 3 - drive interrupt high - - - - - INOVER - [17:16] - read-write - - - NORMAL - 0 - don't invert the peri input - - - INVERT - 1 - invert the peri input - - - LOW - 2 - drive peri input low - - - HIGH - 3 - drive peri input high - - - - - OEOVER - [13:12] - read-write - - - NORMAL - 0 - drive output enable from peripheral signal selected by funcsel - - - INVERT - 1 - drive output enable from inverse of peripheral signal selected by funcsel - - - DISABLE - 2 - disable output - - - ENABLE - 3 - enable output - - - - - OUTOVER - [9:8] - read-write - - - NORMAL - 0 - drive output from peripheral signal selected by funcsel - - - INVERT - 1 - drive output from inverse of peripheral signal selected by funcsel - - - LOW - 2 - drive output low - - - HIGH - 3 - drive output high - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table - 31 == NULL - [4:0] - read-write - - - xip_sd1 - 0 - - - sio_33 - 5 - - - null - 31 - - - - - - - GPIO_QSPI_SD2_STATUS - 0x00000020 - GPIO status - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - IRQFROMPAD - interrupt from pad before override is applied - [24:24] - read-only - - - INTOPERI - input signal to peripheral, after override is applied - [19:19] - read-only - - - INFROMPAD - input signal from pad, before override is applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OEFROMPERI - output enable from selected peripheral, before register override is applied - [12:12] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - OUTFROMPERI - output signal from selected peripheral, before register override is applied - [8:8] - read-only - - - - - GPIO_QSPI_SD2_CTRL - 0x00000024 - GPIO control including function select and overrides. - 0x0000001f - - - IRQOVER - [29:28] - read-write - - - NORMAL - 0 - don't invert the interrupt - - - INVERT - 1 - invert the interrupt - - - LOW - 2 - drive interrupt low - - - HIGH - 3 - drive interrupt high - - - - - INOVER - [17:16] - read-write - - - NORMAL - 0 - don't invert the peri input - - - INVERT - 1 - invert the peri input - - - LOW - 2 - drive peri input low - - - HIGH - 3 - drive peri input high - - - - - OEOVER - [13:12] - read-write - - - NORMAL - 0 - drive output enable from peripheral signal selected by funcsel - - - INVERT - 1 - drive output enable from inverse of peripheral signal selected by funcsel - - - DISABLE - 2 - disable output - - - ENABLE - 3 - enable output - - - - - OUTOVER - [9:8] - read-write - - - NORMAL - 0 - drive output from peripheral signal selected by funcsel - - - INVERT - 1 - drive output from inverse of peripheral signal selected by funcsel - - - LOW - 2 - drive output low - - - HIGH - 3 - drive output high - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table - 31 == NULL - [4:0] - read-write - - - xip_sd2 - 0 - - - sio_34 - 5 - - - null - 31 - - - - - - - GPIO_QSPI_SD3_STATUS - 0x00000028 - GPIO status - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - IRQFROMPAD - interrupt from pad before override is applied - [24:24] - read-only - - - INTOPERI - input signal to peripheral, after override is applied - [19:19] - read-only - - - INFROMPAD - input signal from pad, before override is applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OEFROMPERI - output enable from selected peripheral, before register override is applied - [12:12] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - OUTFROMPERI - output signal from selected peripheral, before register override is applied - [8:8] - read-only - - - - - GPIO_QSPI_SD3_CTRL - 0x0000002c - GPIO control including function select and overrides. - 0x0000001f - - - IRQOVER - [29:28] - read-write - - - NORMAL - 0 - don't invert the interrupt - - - INVERT - 1 - invert the interrupt - - - LOW - 2 - drive interrupt low - - - HIGH - 3 - drive interrupt high - - - - - INOVER - [17:16] - read-write - - - NORMAL - 0 - don't invert the peri input - - - INVERT - 1 - invert the peri input - - - LOW - 2 - drive peri input low - - - HIGH - 3 - drive peri input high - - - - - OEOVER - [13:12] - read-write - - - NORMAL - 0 - drive output enable from peripheral signal selected by funcsel - - - INVERT - 1 - drive output enable from inverse of peripheral signal selected by funcsel - - - DISABLE - 2 - disable output - - - ENABLE - 3 - enable output - - - - - OUTOVER - [9:8] - read-write - - - NORMAL - 0 - drive output from peripheral signal selected by funcsel - - - INVERT - 1 - drive output from inverse of peripheral signal selected by funcsel - - - LOW - 2 - drive output low - - - HIGH - 3 - drive output high - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table - 31 == NULL - [4:0] - read-write - - - xip_sd3 - 0 - - - sio_35 - 5 - - - null - 31 - - - - - - - INTR - 0x00000030 - Raw Interrupts - 0x00000000 - - - GPIO_QSPI_SD3_EDGE_HIGH - [23:23] - read-write - oneToClear - - - GPIO_QSPI_SD3_EDGE_LOW - [22:22] - read-write - oneToClear - - - GPIO_QSPI_SD3_LEVEL_HIGH - [21:21] - read-only - - - GPIO_QSPI_SD3_LEVEL_LOW - [20:20] - read-only - - - GPIO_QSPI_SD2_EDGE_HIGH - [19:19] - read-write - oneToClear - - - GPIO_QSPI_SD2_EDGE_LOW - [18:18] - read-write - oneToClear - - - GPIO_QSPI_SD2_LEVEL_HIGH - [17:17] - read-only - - - GPIO_QSPI_SD2_LEVEL_LOW - [16:16] - read-only - - - GPIO_QSPI_SD1_EDGE_HIGH - [15:15] - read-write - oneToClear - - - GPIO_QSPI_SD1_EDGE_LOW - [14:14] - read-write - oneToClear - - - GPIO_QSPI_SD1_LEVEL_HIGH - [13:13] - read-only - - - GPIO_QSPI_SD1_LEVEL_LOW - [12:12] - read-only - - - GPIO_QSPI_SD0_EDGE_HIGH - [11:11] - read-write - oneToClear - - - GPIO_QSPI_SD0_EDGE_LOW - [10:10] - read-write - oneToClear - - - GPIO_QSPI_SD0_LEVEL_HIGH - [9:9] - read-only - - - GPIO_QSPI_SD0_LEVEL_LOW - [8:8] - read-only - - - GPIO_QSPI_SS_EDGE_HIGH - [7:7] - read-write - oneToClear - - - GPIO_QSPI_SS_EDGE_LOW - [6:6] - read-write - oneToClear - - - GPIO_QSPI_SS_LEVEL_HIGH - [5:5] - read-only - - - GPIO_QSPI_SS_LEVEL_LOW - [4:4] - read-only - - - GPIO_QSPI_SCLK_EDGE_HIGH - [3:3] - read-write - oneToClear - - - GPIO_QSPI_SCLK_EDGE_LOW - [2:2] - read-write - oneToClear - - - GPIO_QSPI_SCLK_LEVEL_HIGH - [1:1] - read-only - - - GPIO_QSPI_SCLK_LEVEL_LOW - [0:0] - read-only - - - - - PROC0_INTE - 0x00000034 - Interrupt Enable for proc0 - 0x00000000 - - - GPIO_QSPI_SD3_EDGE_HIGH - [23:23] - read-write - - - GPIO_QSPI_SD3_EDGE_LOW - [22:22] - read-write - - - GPIO_QSPI_SD3_LEVEL_HIGH - [21:21] - read-write - - - GPIO_QSPI_SD3_LEVEL_LOW - [20:20] - read-write - - - GPIO_QSPI_SD2_EDGE_HIGH - [19:19] - read-write - - - GPIO_QSPI_SD2_EDGE_LOW - [18:18] - read-write - - - GPIO_QSPI_SD2_LEVEL_HIGH - [17:17] - read-write - - - GPIO_QSPI_SD2_LEVEL_LOW - [16:16] - read-write - - - GPIO_QSPI_SD1_EDGE_HIGH - [15:15] - read-write - - - GPIO_QSPI_SD1_EDGE_LOW - [14:14] - read-write - - - GPIO_QSPI_SD1_LEVEL_HIGH - [13:13] - read-write - - - GPIO_QSPI_SD1_LEVEL_LOW - [12:12] - read-write - - - GPIO_QSPI_SD0_EDGE_HIGH - [11:11] - read-write - - - GPIO_QSPI_SD0_EDGE_LOW - [10:10] - read-write - - - GPIO_QSPI_SD0_LEVEL_HIGH - [9:9] - read-write - - - GPIO_QSPI_SD0_LEVEL_LOW - [8:8] - read-write - - - GPIO_QSPI_SS_EDGE_HIGH - [7:7] - read-write - - - GPIO_QSPI_SS_EDGE_LOW - [6:6] - read-write - - - GPIO_QSPI_SS_LEVEL_HIGH - [5:5] - read-write - - - GPIO_QSPI_SS_LEVEL_LOW - [4:4] - read-write - - - GPIO_QSPI_SCLK_EDGE_HIGH - [3:3] - read-write - - - GPIO_QSPI_SCLK_EDGE_LOW - [2:2] - read-write - - - GPIO_QSPI_SCLK_LEVEL_HIGH - [1:1] - read-write - - - GPIO_QSPI_SCLK_LEVEL_LOW - [0:0] - read-write - - - - - PROC0_INTF - 0x00000038 - Interrupt Force for proc0 - 0x00000000 - - - GPIO_QSPI_SD3_EDGE_HIGH - [23:23] - read-write - - - GPIO_QSPI_SD3_EDGE_LOW - [22:22] - read-write - - - GPIO_QSPI_SD3_LEVEL_HIGH - [21:21] - read-write - - - GPIO_QSPI_SD3_LEVEL_LOW - [20:20] - read-write - - - GPIO_QSPI_SD2_EDGE_HIGH - [19:19] - read-write - - - GPIO_QSPI_SD2_EDGE_LOW - [18:18] - read-write - - - GPIO_QSPI_SD2_LEVEL_HIGH - [17:17] - read-write - - - GPIO_QSPI_SD2_LEVEL_LOW - [16:16] - read-write - - - GPIO_QSPI_SD1_EDGE_HIGH - [15:15] - read-write - - - GPIO_QSPI_SD1_EDGE_LOW - [14:14] - read-write - - - GPIO_QSPI_SD1_LEVEL_HIGH - [13:13] - read-write - - - GPIO_QSPI_SD1_LEVEL_LOW - [12:12] - read-write - - - GPIO_QSPI_SD0_EDGE_HIGH - [11:11] - read-write - - - GPIO_QSPI_SD0_EDGE_LOW - [10:10] - read-write - - - GPIO_QSPI_SD0_LEVEL_HIGH - [9:9] - read-write - - - GPIO_QSPI_SD0_LEVEL_LOW - [8:8] - read-write - - - GPIO_QSPI_SS_EDGE_HIGH - [7:7] - read-write - - - GPIO_QSPI_SS_EDGE_LOW - [6:6] - read-write - - - GPIO_QSPI_SS_LEVEL_HIGH - [5:5] - read-write - - - GPIO_QSPI_SS_LEVEL_LOW - [4:4] - read-write - - - GPIO_QSPI_SCLK_EDGE_HIGH - [3:3] - read-write - - - GPIO_QSPI_SCLK_EDGE_LOW - [2:2] - read-write - - - GPIO_QSPI_SCLK_LEVEL_HIGH - [1:1] - read-write - - - GPIO_QSPI_SCLK_LEVEL_LOW - [0:0] - read-write - - - - - PROC0_INTS - 0x0000003c - Interrupt status after masking & forcing for proc0 - 0x00000000 - - - GPIO_QSPI_SD3_EDGE_HIGH - [23:23] - read-only - - - GPIO_QSPI_SD3_EDGE_LOW - [22:22] - read-only - - - GPIO_QSPI_SD3_LEVEL_HIGH - [21:21] - read-only - - - GPIO_QSPI_SD3_LEVEL_LOW - [20:20] - read-only - - - GPIO_QSPI_SD2_EDGE_HIGH - [19:19] - read-only - - - GPIO_QSPI_SD2_EDGE_LOW - [18:18] - read-only - - - GPIO_QSPI_SD2_LEVEL_HIGH - [17:17] - read-only - - - GPIO_QSPI_SD2_LEVEL_LOW - [16:16] - read-only - - - GPIO_QSPI_SD1_EDGE_HIGH - [15:15] - read-only - - - GPIO_QSPI_SD1_EDGE_LOW - [14:14] - read-only - - - GPIO_QSPI_SD1_LEVEL_HIGH - [13:13] - read-only - - - GPIO_QSPI_SD1_LEVEL_LOW - [12:12] - read-only - - - GPIO_QSPI_SD0_EDGE_HIGH - [11:11] - read-only - - - GPIO_QSPI_SD0_EDGE_LOW - [10:10] - read-only - - - GPIO_QSPI_SD0_LEVEL_HIGH - [9:9] - read-only - - - GPIO_QSPI_SD0_LEVEL_LOW - [8:8] - read-only - - - GPIO_QSPI_SS_EDGE_HIGH - [7:7] - read-only - - - GPIO_QSPI_SS_EDGE_LOW - [6:6] - read-only - - - GPIO_QSPI_SS_LEVEL_HIGH - [5:5] - read-only - - - GPIO_QSPI_SS_LEVEL_LOW - [4:4] - read-only - - - GPIO_QSPI_SCLK_EDGE_HIGH - [3:3] - read-only - - - GPIO_QSPI_SCLK_EDGE_LOW - [2:2] - read-only - - - GPIO_QSPI_SCLK_LEVEL_HIGH - [1:1] - read-only - - - GPIO_QSPI_SCLK_LEVEL_LOW - [0:0] - read-only - - - - - PROC1_INTE - 0x00000040 - Interrupt Enable for proc1 - 0x00000000 - - - GPIO_QSPI_SD3_EDGE_HIGH - [23:23] - read-write - - - GPIO_QSPI_SD3_EDGE_LOW - [22:22] - read-write - - - GPIO_QSPI_SD3_LEVEL_HIGH - [21:21] - read-write - - - GPIO_QSPI_SD3_LEVEL_LOW - [20:20] - read-write - - - GPIO_QSPI_SD2_EDGE_HIGH - [19:19] - read-write - - - GPIO_QSPI_SD2_EDGE_LOW - [18:18] - read-write - - - GPIO_QSPI_SD2_LEVEL_HIGH - [17:17] - read-write - - - GPIO_QSPI_SD2_LEVEL_LOW - [16:16] - read-write - - - GPIO_QSPI_SD1_EDGE_HIGH - [15:15] - read-write - - - GPIO_QSPI_SD1_EDGE_LOW - [14:14] - read-write - - - GPIO_QSPI_SD1_LEVEL_HIGH - [13:13] - read-write - - - GPIO_QSPI_SD1_LEVEL_LOW - [12:12] - read-write - - - GPIO_QSPI_SD0_EDGE_HIGH - [11:11] - read-write - - - GPIO_QSPI_SD0_EDGE_LOW - [10:10] - read-write - - - GPIO_QSPI_SD0_LEVEL_HIGH - [9:9] - read-write - - - GPIO_QSPI_SD0_LEVEL_LOW - [8:8] - read-write - - - GPIO_QSPI_SS_EDGE_HIGH - [7:7] - read-write - - - GPIO_QSPI_SS_EDGE_LOW - [6:6] - read-write - - - GPIO_QSPI_SS_LEVEL_HIGH - [5:5] - read-write - - - GPIO_QSPI_SS_LEVEL_LOW - [4:4] - read-write - - - GPIO_QSPI_SCLK_EDGE_HIGH - [3:3] - read-write - - - GPIO_QSPI_SCLK_EDGE_LOW - [2:2] - read-write - - - GPIO_QSPI_SCLK_LEVEL_HIGH - [1:1] - read-write - - - GPIO_QSPI_SCLK_LEVEL_LOW - [0:0] - read-write - - - - - PROC1_INTF - 0x00000044 - Interrupt Force for proc1 - 0x00000000 - - - GPIO_QSPI_SD3_EDGE_HIGH - [23:23] - read-write - - - GPIO_QSPI_SD3_EDGE_LOW - [22:22] - read-write - - - GPIO_QSPI_SD3_LEVEL_HIGH - [21:21] - read-write - - - GPIO_QSPI_SD3_LEVEL_LOW - [20:20] - read-write - - - GPIO_QSPI_SD2_EDGE_HIGH - [19:19] - read-write - - - GPIO_QSPI_SD2_EDGE_LOW - [18:18] - read-write - - - GPIO_QSPI_SD2_LEVEL_HIGH - [17:17] - read-write - - - GPIO_QSPI_SD2_LEVEL_LOW - [16:16] - read-write - - - GPIO_QSPI_SD1_EDGE_HIGH - [15:15] - read-write - - - GPIO_QSPI_SD1_EDGE_LOW - [14:14] - read-write - - - GPIO_QSPI_SD1_LEVEL_HIGH - [13:13] - read-write - - - GPIO_QSPI_SD1_LEVEL_LOW - [12:12] - read-write - - - GPIO_QSPI_SD0_EDGE_HIGH - [11:11] - read-write - - - GPIO_QSPI_SD0_EDGE_LOW - [10:10] - read-write - - - GPIO_QSPI_SD0_LEVEL_HIGH - [9:9] - read-write - - - GPIO_QSPI_SD0_LEVEL_LOW - [8:8] - read-write - - - GPIO_QSPI_SS_EDGE_HIGH - [7:7] - read-write - - - GPIO_QSPI_SS_EDGE_LOW - [6:6] - read-write - - - GPIO_QSPI_SS_LEVEL_HIGH - [5:5] - read-write - - - GPIO_QSPI_SS_LEVEL_LOW - [4:4] - read-write - - - GPIO_QSPI_SCLK_EDGE_HIGH - [3:3] - read-write - - - GPIO_QSPI_SCLK_EDGE_LOW - [2:2] - read-write - - - GPIO_QSPI_SCLK_LEVEL_HIGH - [1:1] - read-write - - - GPIO_QSPI_SCLK_LEVEL_LOW - [0:0] - read-write - - - - - PROC1_INTS - 0x00000048 - Interrupt status after masking & forcing for proc1 - 0x00000000 - - - GPIO_QSPI_SD3_EDGE_HIGH - [23:23] - read-only - - - GPIO_QSPI_SD3_EDGE_LOW - [22:22] - read-only - - - GPIO_QSPI_SD3_LEVEL_HIGH - [21:21] - read-only - - - GPIO_QSPI_SD3_LEVEL_LOW - [20:20] - read-only - - - GPIO_QSPI_SD2_EDGE_HIGH - [19:19] - read-only - - - GPIO_QSPI_SD2_EDGE_LOW - [18:18] - read-only - - - GPIO_QSPI_SD2_LEVEL_HIGH - [17:17] - read-only - - - GPIO_QSPI_SD2_LEVEL_LOW - [16:16] - read-only - - - GPIO_QSPI_SD1_EDGE_HIGH - [15:15] - read-only - - - GPIO_QSPI_SD1_EDGE_LOW - [14:14] - read-only - - - GPIO_QSPI_SD1_LEVEL_HIGH - [13:13] - read-only - - - GPIO_QSPI_SD1_LEVEL_LOW - [12:12] - read-only - - - GPIO_QSPI_SD0_EDGE_HIGH - [11:11] - read-only - - - GPIO_QSPI_SD0_EDGE_LOW - [10:10] - read-only - - - GPIO_QSPI_SD0_LEVEL_HIGH - [9:9] - read-only - - - GPIO_QSPI_SD0_LEVEL_LOW - [8:8] - read-only - - - GPIO_QSPI_SS_EDGE_HIGH - [7:7] - read-only - - - GPIO_QSPI_SS_EDGE_LOW - [6:6] - read-only - - - GPIO_QSPI_SS_LEVEL_HIGH - [5:5] - read-only - - - GPIO_QSPI_SS_LEVEL_LOW - [4:4] - read-only - - - GPIO_QSPI_SCLK_EDGE_HIGH - [3:3] - read-only - - - GPIO_QSPI_SCLK_EDGE_LOW - [2:2] - read-only - - - GPIO_QSPI_SCLK_LEVEL_HIGH - [1:1] - read-only - - - GPIO_QSPI_SCLK_LEVEL_LOW - [0:0] - read-only - - - - - DORMANT_WAKE_INTE - 0x0000004c - Interrupt Enable for dormant_wake - 0x00000000 - - - GPIO_QSPI_SD3_EDGE_HIGH - [23:23] - read-write - - - GPIO_QSPI_SD3_EDGE_LOW - [22:22] - read-write - - - GPIO_QSPI_SD3_LEVEL_HIGH - [21:21] - read-write - - - GPIO_QSPI_SD3_LEVEL_LOW - [20:20] - read-write - - - GPIO_QSPI_SD2_EDGE_HIGH - [19:19] - read-write - - - GPIO_QSPI_SD2_EDGE_LOW - [18:18] - read-write - - - GPIO_QSPI_SD2_LEVEL_HIGH - [17:17] - read-write - - - GPIO_QSPI_SD2_LEVEL_LOW - [16:16] - read-write - - - GPIO_QSPI_SD1_EDGE_HIGH - [15:15] - read-write - - - GPIO_QSPI_SD1_EDGE_LOW - [14:14] - read-write - - - GPIO_QSPI_SD1_LEVEL_HIGH - [13:13] - read-write - - - GPIO_QSPI_SD1_LEVEL_LOW - [12:12] - read-write - - - GPIO_QSPI_SD0_EDGE_HIGH - [11:11] - read-write - - - GPIO_QSPI_SD0_EDGE_LOW - [10:10] - read-write - - - GPIO_QSPI_SD0_LEVEL_HIGH - [9:9] - read-write - - - GPIO_QSPI_SD0_LEVEL_LOW - [8:8] - read-write - - - GPIO_QSPI_SS_EDGE_HIGH - [7:7] - read-write - - - GPIO_QSPI_SS_EDGE_LOW - [6:6] - read-write - - - GPIO_QSPI_SS_LEVEL_HIGH - [5:5] - read-write - - - GPIO_QSPI_SS_LEVEL_LOW - [4:4] - read-write - - - GPIO_QSPI_SCLK_EDGE_HIGH - [3:3] - read-write - - - GPIO_QSPI_SCLK_EDGE_LOW - [2:2] - read-write - - - GPIO_QSPI_SCLK_LEVEL_HIGH - [1:1] - read-write - - - GPIO_QSPI_SCLK_LEVEL_LOW - [0:0] - read-write - - - - - DORMANT_WAKE_INTF - 0x00000050 - Interrupt Force for dormant_wake - 0x00000000 - - - GPIO_QSPI_SD3_EDGE_HIGH - [23:23] - read-write - - - GPIO_QSPI_SD3_EDGE_LOW - [22:22] - read-write - - - GPIO_QSPI_SD3_LEVEL_HIGH - [21:21] - read-write - - - GPIO_QSPI_SD3_LEVEL_LOW - [20:20] - read-write - - - GPIO_QSPI_SD2_EDGE_HIGH - [19:19] - read-write - - - GPIO_QSPI_SD2_EDGE_LOW - [18:18] - read-write - - - GPIO_QSPI_SD2_LEVEL_HIGH - [17:17] - read-write - - - GPIO_QSPI_SD2_LEVEL_LOW - [16:16] - read-write - - - GPIO_QSPI_SD1_EDGE_HIGH - [15:15] - read-write - - - GPIO_QSPI_SD1_EDGE_LOW - [14:14] - read-write - - - GPIO_QSPI_SD1_LEVEL_HIGH - [13:13] - read-write - - - GPIO_QSPI_SD1_LEVEL_LOW - [12:12] - read-write - - - GPIO_QSPI_SD0_EDGE_HIGH - [11:11] - read-write - - - GPIO_QSPI_SD0_EDGE_LOW - [10:10] - read-write - - - GPIO_QSPI_SD0_LEVEL_HIGH - [9:9] - read-write - - - GPIO_QSPI_SD0_LEVEL_LOW - [8:8] - read-write - - - GPIO_QSPI_SS_EDGE_HIGH - [7:7] - read-write - - - GPIO_QSPI_SS_EDGE_LOW - [6:6] - read-write - - - GPIO_QSPI_SS_LEVEL_HIGH - [5:5] - read-write - - - GPIO_QSPI_SS_LEVEL_LOW - [4:4] - read-write - - - GPIO_QSPI_SCLK_EDGE_HIGH - [3:3] - read-write - - - GPIO_QSPI_SCLK_EDGE_LOW - [2:2] - read-write - - - GPIO_QSPI_SCLK_LEVEL_HIGH - [1:1] - read-write - - - GPIO_QSPI_SCLK_LEVEL_LOW - [0:0] - read-write - - - - - DORMANT_WAKE_INTS - 0x00000054 - Interrupt status after masking & forcing for dormant_wake - 0x00000000 - - - GPIO_QSPI_SD3_EDGE_HIGH - [23:23] - read-only - - - GPIO_QSPI_SD3_EDGE_LOW - [22:22] - read-only - - - GPIO_QSPI_SD3_LEVEL_HIGH - [21:21] - read-only - - - GPIO_QSPI_SD3_LEVEL_LOW - [20:20] - read-only - - - GPIO_QSPI_SD2_EDGE_HIGH - [19:19] - read-only - - - GPIO_QSPI_SD2_EDGE_LOW - [18:18] - read-only - - - GPIO_QSPI_SD2_LEVEL_HIGH - [17:17] - read-only - - - GPIO_QSPI_SD2_LEVEL_LOW - [16:16] - read-only - - - GPIO_QSPI_SD1_EDGE_HIGH - [15:15] - read-only - - - GPIO_QSPI_SD1_EDGE_LOW - [14:14] - read-only - - - GPIO_QSPI_SD1_LEVEL_HIGH - [13:13] - read-only - - - GPIO_QSPI_SD1_LEVEL_LOW - [12:12] - read-only - - - GPIO_QSPI_SD0_EDGE_HIGH - [11:11] - read-only - - - GPIO_QSPI_SD0_EDGE_LOW - [10:10] - read-only - - - GPIO_QSPI_SD0_LEVEL_HIGH - [9:9] - read-only - - - GPIO_QSPI_SD0_LEVEL_LOW - [8:8] - read-only - - - GPIO_QSPI_SS_EDGE_HIGH - [7:7] - read-only - - - GPIO_QSPI_SS_EDGE_LOW - [6:6] - read-only - - - GPIO_QSPI_SS_LEVEL_HIGH - [5:5] - read-only - - - GPIO_QSPI_SS_LEVEL_LOW - [4:4] - read-only - - - GPIO_QSPI_SCLK_EDGE_HIGH - [3:3] - read-only - - - GPIO_QSPI_SCLK_EDGE_LOW - [2:2] - read-only - - - GPIO_QSPI_SCLK_LEVEL_HIGH - [1:1] - read-only - - - GPIO_QSPI_SCLK_LEVEL_LOW - [0:0] - read-only - - - - - - - IO_BANK0 - 0x40014000 - - 0 - 400 - registers - - - IO_IRQ_BANK0 - 13 - - - - GPIO0_STATUS - 0x00000000 - GPIO status - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - IRQFROMPAD - interrupt from pad before override is applied - [24:24] - read-only - - - INTOPERI - input signal to peripheral, after override is applied - [19:19] - read-only - - - INFROMPAD - input signal from pad, before override is applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OEFROMPERI - output enable from selected peripheral, before register override is applied - [12:12] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - OUTFROMPERI - output signal from selected peripheral, before register override is applied - [8:8] - read-only - - - - - GPIO0_CTRL - 0x00000004 - GPIO control including function select and overrides. - 0x0000001f - - - IRQOVER - [29:28] - read-write - - - NORMAL - 0 - don't invert the interrupt - - - INVERT - 1 - invert the interrupt - - - LOW - 2 - drive interrupt low - - - HIGH - 3 - drive interrupt high - - - - - INOVER - [17:16] - read-write - - - NORMAL - 0 - don't invert the peri input - - - INVERT - 1 - invert the peri input - - - LOW - 2 - drive peri input low - - - HIGH - 3 - drive peri input high - - - - - OEOVER - [13:12] - read-write - - - NORMAL - 0 - drive output enable from peripheral signal selected by funcsel - - - INVERT - 1 - drive output enable from inverse of peripheral signal selected by funcsel - - - DISABLE - 2 - disable output - - - ENABLE - 3 - enable output - - - - - OUTOVER - [9:8] - read-write - - - NORMAL - 0 - drive output from peripheral signal selected by funcsel - - - INVERT - 1 - drive output from inverse of peripheral signal selected by funcsel - - - LOW - 2 - drive output low - - - HIGH - 3 - drive output high - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table - 31 == NULL - [4:0] - read-write - - - jtag_tck - 0 - - - spi0_rx - 1 - - - uart0_tx - 2 - - - i2c0_sda - 3 - - - pwm_a_0 - 4 - - - sio_0 - 5 - - - pio0_0 - 6 - - - pio1_0 - 7 - - - usb_muxing_overcurr_detect - 9 - - - null - 31 - - - - - - - GPIO1_STATUS - 0x00000008 - GPIO status - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - IRQFROMPAD - interrupt from pad before override is applied - [24:24] - read-only - - - INTOPERI - input signal to peripheral, after override is applied - [19:19] - read-only - - - INFROMPAD - input signal from pad, before override is applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OEFROMPERI - output enable from selected peripheral, before register override is applied - [12:12] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - OUTFROMPERI - output signal from selected peripheral, before register override is applied - [8:8] - read-only - - - - - GPIO1_CTRL - 0x0000000c - GPIO control including function select and overrides. - 0x0000001f - - - IRQOVER - [29:28] - read-write - - - NORMAL - 0 - don't invert the interrupt - - - INVERT - 1 - invert the interrupt - - - LOW - 2 - drive interrupt low - - - HIGH - 3 - drive interrupt high - - - - - INOVER - [17:16] - read-write - - - NORMAL - 0 - don't invert the peri input - - - INVERT - 1 - invert the peri input - - - LOW - 2 - drive peri input low - - - HIGH - 3 - drive peri input high - - - - - OEOVER - [13:12] - read-write - - - NORMAL - 0 - drive output enable from peripheral signal selected by funcsel - - - INVERT - 1 - drive output enable from inverse of peripheral signal selected by funcsel - - - DISABLE - 2 - disable output - - - ENABLE - 3 - enable output - - - - - OUTOVER - [9:8] - read-write - - - NORMAL - 0 - drive output from peripheral signal selected by funcsel - - - INVERT - 1 - drive output from inverse of peripheral signal selected by funcsel - - - LOW - 2 - drive output low - - - HIGH - 3 - drive output high - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table - 31 == NULL - [4:0] - read-write - - - jtag_tms - 0 - - - spi0_ss_n - 1 - - - uart0_rx - 2 - - - i2c0_scl - 3 - - - pwm_b_0 - 4 - - - sio_1 - 5 - - - pio0_1 - 6 - - - pio1_1 - 7 - - - usb_muxing_vbus_detect - 9 - - - null - 31 - - - - - - - GPIO2_STATUS - 0x00000010 - GPIO status - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - IRQFROMPAD - interrupt from pad before override is applied - [24:24] - read-only - - - INTOPERI - input signal to peripheral, after override is applied - [19:19] - read-only - - - INFROMPAD - input signal from pad, before override is applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OEFROMPERI - output enable from selected peripheral, before register override is applied - [12:12] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - OUTFROMPERI - output signal from selected peripheral, before register override is applied - [8:8] - read-only - - - - - GPIO2_CTRL - 0x00000014 - GPIO control including function select and overrides. - 0x0000001f - - - IRQOVER - [29:28] - read-write - - - NORMAL - 0 - don't invert the interrupt - - - INVERT - 1 - invert the interrupt - - - LOW - 2 - drive interrupt low - - - HIGH - 3 - drive interrupt high - - - - - INOVER - [17:16] - read-write - - - NORMAL - 0 - don't invert the peri input - - - INVERT - 1 - invert the peri input - - - LOW - 2 - drive peri input low - - - HIGH - 3 - drive peri input high - - - - - OEOVER - [13:12] - read-write - - - NORMAL - 0 - drive output enable from peripheral signal selected by funcsel - - - INVERT - 1 - drive output enable from inverse of peripheral signal selected by funcsel - - - DISABLE - 2 - disable output - - - ENABLE - 3 - enable output - - - - - OUTOVER - [9:8] - read-write - - - NORMAL - 0 - drive output from peripheral signal selected by funcsel - - - INVERT - 1 - drive output from inverse of peripheral signal selected by funcsel - - - LOW - 2 - drive output low - - - HIGH - 3 - drive output high - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table - 31 == NULL - [4:0] - read-write - - - jtag_tdi - 0 - - - spi0_sclk - 1 - - - uart0_cts - 2 - - - i2c1_sda - 3 - - - pwm_a_1 - 4 - - - sio_2 - 5 - - - pio0_2 - 6 - - - pio1_2 - 7 - - - usb_muxing_vbus_en - 9 - - - null - 31 - - - - - - - GPIO3_STATUS - 0x00000018 - GPIO status - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - IRQFROMPAD - interrupt from pad before override is applied - [24:24] - read-only - - - INTOPERI - input signal to peripheral, after override is applied - [19:19] - read-only - - - INFROMPAD - input signal from pad, before override is applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OEFROMPERI - output enable from selected peripheral, before register override is applied - [12:12] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - OUTFROMPERI - output signal from selected peripheral, before register override is applied - [8:8] - read-only - - - - - GPIO3_CTRL - 0x0000001c - GPIO control including function select and overrides. - 0x0000001f - - - IRQOVER - [29:28] - read-write - - - NORMAL - 0 - don't invert the interrupt - - - INVERT - 1 - invert the interrupt - - - LOW - 2 - drive interrupt low - - - HIGH - 3 - drive interrupt high - - - - - INOVER - [17:16] - read-write - - - NORMAL - 0 - don't invert the peri input - - - INVERT - 1 - invert the peri input - - - LOW - 2 - drive peri input low - - - HIGH - 3 - drive peri input high - - - - - OEOVER - [13:12] - read-write - - - NORMAL - 0 - drive output enable from peripheral signal selected by funcsel - - - INVERT - 1 - drive output enable from inverse of peripheral signal selected by funcsel - - - DISABLE - 2 - disable output - - - ENABLE - 3 - enable output - - - - - OUTOVER - [9:8] - read-write - - - NORMAL - 0 - drive output from peripheral signal selected by funcsel - - - INVERT - 1 - drive output from inverse of peripheral signal selected by funcsel - - - LOW - 2 - drive output low - - - HIGH - 3 - drive output high - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table - 31 == NULL - [4:0] - read-write - - - jtag_tdo - 0 - - - spi0_tx - 1 - - - uart0_rts - 2 - - - i2c1_scl - 3 - - - pwm_b_1 - 4 - - - sio_3 - 5 - - - pio0_3 - 6 - - - pio1_3 - 7 - - - usb_muxing_overcurr_detect - 9 - - - null - 31 - - - - - - - GPIO4_STATUS - 0x00000020 - GPIO status - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - IRQFROMPAD - interrupt from pad before override is applied - [24:24] - read-only - - - INTOPERI - input signal to peripheral, after override is applied - [19:19] - read-only - - - INFROMPAD - input signal from pad, before override is applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OEFROMPERI - output enable from selected peripheral, before register override is applied - [12:12] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - OUTFROMPERI - output signal from selected peripheral, before register override is applied - [8:8] - read-only - - - - - GPIO4_CTRL - 0x00000024 - GPIO control including function select and overrides. - 0x0000001f - - - IRQOVER - [29:28] - read-write - - - NORMAL - 0 - don't invert the interrupt - - - INVERT - 1 - invert the interrupt - - - LOW - 2 - drive interrupt low - - - HIGH - 3 - drive interrupt high - - - - - INOVER - [17:16] - read-write - - - NORMAL - 0 - don't invert the peri input - - - INVERT - 1 - invert the peri input - - - LOW - 2 - drive peri input low - - - HIGH - 3 - drive peri input high - - - - - OEOVER - [13:12] - read-write - - - NORMAL - 0 - drive output enable from peripheral signal selected by funcsel - - - INVERT - 1 - drive output enable from inverse of peripheral signal selected by funcsel - - - DISABLE - 2 - disable output - - - ENABLE - 3 - enable output - - - - - OUTOVER - [9:8] - read-write - - - NORMAL - 0 - drive output from peripheral signal selected by funcsel - - - INVERT - 1 - drive output from inverse of peripheral signal selected by funcsel - - - LOW - 2 - drive output low - - - HIGH - 3 - drive output high - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table - 31 == NULL - [4:0] - read-write - - - spi0_rx - 1 - - - uart1_tx - 2 - - - i2c0_sda - 3 - - - pwm_a_2 - 4 - - - sio_4 - 5 - - - pio0_4 - 6 - - - pio1_4 - 7 - - - usb_muxing_vbus_detect - 9 - - - null - 31 - - - - - - - GPIO5_STATUS - 0x00000028 - GPIO status - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - IRQFROMPAD - interrupt from pad before override is applied - [24:24] - read-only - - - INTOPERI - input signal to peripheral, after override is applied - [19:19] - read-only - - - INFROMPAD - input signal from pad, before override is applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OEFROMPERI - output enable from selected peripheral, before register override is applied - [12:12] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - OUTFROMPERI - output signal from selected peripheral, before register override is applied - [8:8] - read-only - - - - - GPIO5_CTRL - 0x0000002c - GPIO control including function select and overrides. - 0x0000001f - - - IRQOVER - [29:28] - read-write - - - NORMAL - 0 - don't invert the interrupt - - - INVERT - 1 - invert the interrupt - - - LOW - 2 - drive interrupt low - - - HIGH - 3 - drive interrupt high - - - - - INOVER - [17:16] - read-write - - - NORMAL - 0 - don't invert the peri input - - - INVERT - 1 - invert the peri input - - - LOW - 2 - drive peri input low - - - HIGH - 3 - drive peri input high - - - - - OEOVER - [13:12] - read-write - - - NORMAL - 0 - drive output enable from peripheral signal selected by funcsel - - - INVERT - 1 - drive output enable from inverse of peripheral signal selected by funcsel - - - DISABLE - 2 - disable output - - - ENABLE - 3 - enable output - - - - - OUTOVER - [9:8] - read-write - - - NORMAL - 0 - drive output from peripheral signal selected by funcsel - - - INVERT - 1 - drive output from inverse of peripheral signal selected by funcsel - - - LOW - 2 - drive output low - - - HIGH - 3 - drive output high - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table - 31 == NULL - [4:0] - read-write - - - spi0_ss_n - 1 - - - uart1_rx - 2 - - - i2c0_scl - 3 - - - pwm_b_2 - 4 - - - sio_5 - 5 - - - pio0_5 - 6 - - - pio1_5 - 7 - - - usb_muxing_vbus_en - 9 - - - null - 31 - - - - - - - GPIO6_STATUS - 0x00000030 - GPIO status - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - IRQFROMPAD - interrupt from pad before override is applied - [24:24] - read-only - - - INTOPERI - input signal to peripheral, after override is applied - [19:19] - read-only - - - INFROMPAD - input signal from pad, before override is applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OEFROMPERI - output enable from selected peripheral, before register override is applied - [12:12] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - OUTFROMPERI - output signal from selected peripheral, before register override is applied - [8:8] - read-only - - - - - GPIO6_CTRL - 0x00000034 - GPIO control including function select and overrides. - 0x0000001f - - - IRQOVER - [29:28] - read-write - - - NORMAL - 0 - don't invert the interrupt - - - INVERT - 1 - invert the interrupt - - - LOW - 2 - drive interrupt low - - - HIGH - 3 - drive interrupt high - - - - - INOVER - [17:16] - read-write - - - NORMAL - 0 - don't invert the peri input - - - INVERT - 1 - invert the peri input - - - LOW - 2 - drive peri input low - - - HIGH - 3 - drive peri input high - - - - - OEOVER - [13:12] - read-write - - - NORMAL - 0 - drive output enable from peripheral signal selected by funcsel - - - INVERT - 1 - drive output enable from inverse of peripheral signal selected by funcsel - - - DISABLE - 2 - disable output - - - ENABLE - 3 - enable output - - - - - OUTOVER - [9:8] - read-write - - - NORMAL - 0 - drive output from peripheral signal selected by funcsel - - - INVERT - 1 - drive output from inverse of peripheral signal selected by funcsel - - - LOW - 2 - drive output low - - - HIGH - 3 - drive output high - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table - 31 == NULL - [4:0] - read-write - - - spi0_sclk - 1 - - - uart1_cts - 2 - - - i2c1_sda - 3 - - - pwm_a_3 - 4 - - - sio_6 - 5 - - - pio0_6 - 6 - - - pio1_6 - 7 - - - usb_muxing_extphy_softcon - 8 - - - usb_muxing_overcurr_detect - 9 - - - null - 31 - - - - - - - GPIO7_STATUS - 0x00000038 - GPIO status - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - IRQFROMPAD - interrupt from pad before override is applied - [24:24] - read-only - - - INTOPERI - input signal to peripheral, after override is applied - [19:19] - read-only - - - INFROMPAD - input signal from pad, before override is applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OEFROMPERI - output enable from selected peripheral, before register override is applied - [12:12] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - OUTFROMPERI - output signal from selected peripheral, before register override is applied - [8:8] - read-only - - - - - GPIO7_CTRL - 0x0000003c - GPIO control including function select and overrides. - 0x0000001f - - - IRQOVER - [29:28] - read-write - - - NORMAL - 0 - don't invert the interrupt - - - INVERT - 1 - invert the interrupt - - - LOW - 2 - drive interrupt low - - - HIGH - 3 - drive interrupt high - - - - - INOVER - [17:16] - read-write - - - NORMAL - 0 - don't invert the peri input - - - INVERT - 1 - invert the peri input - - - LOW - 2 - drive peri input low - - - HIGH - 3 - drive peri input high - - - - - OEOVER - [13:12] - read-write - - - NORMAL - 0 - drive output enable from peripheral signal selected by funcsel - - - INVERT - 1 - drive output enable from inverse of peripheral signal selected by funcsel - - - DISABLE - 2 - disable output - - - ENABLE - 3 - enable output - - - - - OUTOVER - [9:8] - read-write - - - NORMAL - 0 - drive output from peripheral signal selected by funcsel - - - INVERT - 1 - drive output from inverse of peripheral signal selected by funcsel - - - LOW - 2 - drive output low - - - HIGH - 3 - drive output high - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table - 31 == NULL - [4:0] - read-write - - - spi0_tx - 1 - - - uart1_rts - 2 - - - i2c1_scl - 3 - - - pwm_b_3 - 4 - - - sio_7 - 5 - - - pio0_7 - 6 - - - pio1_7 - 7 - - - usb_muxing_extphy_oe_n - 8 - - - usb_muxing_vbus_detect - 9 - - - null - 31 - - - - - - - GPIO8_STATUS - 0x00000040 - GPIO status - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - IRQFROMPAD - interrupt from pad before override is applied - [24:24] - read-only - - - INTOPERI - input signal to peripheral, after override is applied - [19:19] - read-only - - - INFROMPAD - input signal from pad, before override is applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OEFROMPERI - output enable from selected peripheral, before register override is applied - [12:12] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - OUTFROMPERI - output signal from selected peripheral, before register override is applied - [8:8] - read-only - - - - - GPIO8_CTRL - 0x00000044 - GPIO control including function select and overrides. - 0x0000001f - - - IRQOVER - [29:28] - read-write - - - NORMAL - 0 - don't invert the interrupt - - - INVERT - 1 - invert the interrupt - - - LOW - 2 - drive interrupt low - - - HIGH - 3 - drive interrupt high - - - - - INOVER - [17:16] - read-write - - - NORMAL - 0 - don't invert the peri input - - - INVERT - 1 - invert the peri input - - - LOW - 2 - drive peri input low - - - HIGH - 3 - drive peri input high - - - - - OEOVER - [13:12] - read-write - - - NORMAL - 0 - drive output enable from peripheral signal selected by funcsel - - - INVERT - 1 - drive output enable from inverse of peripheral signal selected by funcsel - - - DISABLE - 2 - disable output - - - ENABLE - 3 - enable output - - - - - OUTOVER - [9:8] - read-write - - - NORMAL - 0 - drive output from peripheral signal selected by funcsel - - - INVERT - 1 - drive output from inverse of peripheral signal selected by funcsel - - - LOW - 2 - drive output low - - - HIGH - 3 - drive output high - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table - 31 == NULL - [4:0] - read-write - - - spi1_rx - 1 - - - uart1_tx - 2 - - - i2c0_sda - 3 - - - pwm_a_4 - 4 - - - sio_8 - 5 - - - pio0_8 - 6 - - - pio1_8 - 7 - - - usb_muxing_extphy_rcv - 8 - - - usb_muxing_vbus_en - 9 - - - null - 31 - - - - - - - GPIO9_STATUS - 0x00000048 - GPIO status - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - IRQFROMPAD - interrupt from pad before override is applied - [24:24] - read-only - - - INTOPERI - input signal to peripheral, after override is applied - [19:19] - read-only - - - INFROMPAD - input signal from pad, before override is applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OEFROMPERI - output enable from selected peripheral, before register override is applied - [12:12] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - OUTFROMPERI - output signal from selected peripheral, before register override is applied - [8:8] - read-only - - - - - GPIO9_CTRL - 0x0000004c - GPIO control including function select and overrides. - 0x0000001f - - - IRQOVER - [29:28] - read-write - - - NORMAL - 0 - don't invert the interrupt - - - INVERT - 1 - invert the interrupt - - - LOW - 2 - drive interrupt low - - - HIGH - 3 - drive interrupt high - - - - - INOVER - [17:16] - read-write - - - NORMAL - 0 - don't invert the peri input - - - INVERT - 1 - invert the peri input - - - LOW - 2 - drive peri input low - - - HIGH - 3 - drive peri input high - - - - - OEOVER - [13:12] - read-write - - - NORMAL - 0 - drive output enable from peripheral signal selected by funcsel - - - INVERT - 1 - drive output enable from inverse of peripheral signal selected by funcsel - - - DISABLE - 2 - disable output - - - ENABLE - 3 - enable output - - - - - OUTOVER - [9:8] - read-write - - - NORMAL - 0 - drive output from peripheral signal selected by funcsel - - - INVERT - 1 - drive output from inverse of peripheral signal selected by funcsel - - - LOW - 2 - drive output low - - - HIGH - 3 - drive output high - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table - 31 == NULL - [4:0] - read-write - - - spi1_ss_n - 1 - - - uart1_rx - 2 - - - i2c0_scl - 3 - - - pwm_b_4 - 4 - - - sio_9 - 5 - - - pio0_9 - 6 - - - pio1_9 - 7 - - - usb_muxing_extphy_vp - 8 - - - usb_muxing_overcurr_detect - 9 - - - null - 31 - - - - - - - GPIO10_STATUS - 0x00000050 - GPIO status - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - IRQFROMPAD - interrupt from pad before override is applied - [24:24] - read-only - - - INTOPERI - input signal to peripheral, after override is applied - [19:19] - read-only - - - INFROMPAD - input signal from pad, before override is applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OEFROMPERI - output enable from selected peripheral, before register override is applied - [12:12] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - OUTFROMPERI - output signal from selected peripheral, before register override is applied - [8:8] - read-only - - - - - GPIO10_CTRL - 0x00000054 - GPIO control including function select and overrides. - 0x0000001f - - - IRQOVER - [29:28] - read-write - - - NORMAL - 0 - don't invert the interrupt - - - INVERT - 1 - invert the interrupt - - - LOW - 2 - drive interrupt low - - - HIGH - 3 - drive interrupt high - - - - - INOVER - [17:16] - read-write - - - NORMAL - 0 - don't invert the peri input - - - INVERT - 1 - invert the peri input - - - LOW - 2 - drive peri input low - - - HIGH - 3 - drive peri input high - - - - - OEOVER - [13:12] - read-write - - - NORMAL - 0 - drive output enable from peripheral signal selected by funcsel - - - INVERT - 1 - drive output enable from inverse of peripheral signal selected by funcsel - - - DISABLE - 2 - disable output - - - ENABLE - 3 - enable output - - - - - OUTOVER - [9:8] - read-write - - - NORMAL - 0 - drive output from peripheral signal selected by funcsel - - - INVERT - 1 - drive output from inverse of peripheral signal selected by funcsel - - - LOW - 2 - drive output low - - - HIGH - 3 - drive output high - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table - 31 == NULL - [4:0] - read-write - - - spi1_sclk - 1 - - - uart1_cts - 2 - - - i2c1_sda - 3 - - - pwm_a_5 - 4 - - - sio_10 - 5 - - - pio0_10 - 6 - - - pio1_10 - 7 - - - usb_muxing_extphy_vm - 8 - - - usb_muxing_vbus_detect - 9 - - - null - 31 - - - - - - - GPIO11_STATUS - 0x00000058 - GPIO status - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - IRQFROMPAD - interrupt from pad before override is applied - [24:24] - read-only - - - INTOPERI - input signal to peripheral, after override is applied - [19:19] - read-only - - - INFROMPAD - input signal from pad, before override is applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OEFROMPERI - output enable from selected peripheral, before register override is applied - [12:12] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - OUTFROMPERI - output signal from selected peripheral, before register override is applied - [8:8] - read-only - - - - - GPIO11_CTRL - 0x0000005c - GPIO control including function select and overrides. - 0x0000001f - - - IRQOVER - [29:28] - read-write - - - NORMAL - 0 - don't invert the interrupt - - - INVERT - 1 - invert the interrupt - - - LOW - 2 - drive interrupt low - - - HIGH - 3 - drive interrupt high - - - - - INOVER - [17:16] - read-write - - - NORMAL - 0 - don't invert the peri input - - - INVERT - 1 - invert the peri input - - - LOW - 2 - drive peri input low - - - HIGH - 3 - drive peri input high - - - - - OEOVER - [13:12] - read-write - - - NORMAL - 0 - drive output enable from peripheral signal selected by funcsel - - - INVERT - 1 - drive output enable from inverse of peripheral signal selected by funcsel - - - DISABLE - 2 - disable output - - - ENABLE - 3 - enable output - - - - - OUTOVER - [9:8] - read-write - - - NORMAL - 0 - drive output from peripheral signal selected by funcsel - - - INVERT - 1 - drive output from inverse of peripheral signal selected by funcsel - - - LOW - 2 - drive output low - - - HIGH - 3 - drive output high - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table - 31 == NULL - [4:0] - read-write - - - spi1_tx - 1 - - - uart1_rts - 2 - - - i2c1_scl - 3 - - - pwm_b_5 - 4 - - - sio_11 - 5 - - - pio0_11 - 6 - - - pio1_11 - 7 - - - usb_muxing_extphy_suspnd - 8 - - - usb_muxing_vbus_en - 9 - - - null - 31 - - - - - - - GPIO12_STATUS - 0x00000060 - GPIO status - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - IRQFROMPAD - interrupt from pad before override is applied - [24:24] - read-only - - - INTOPERI - input signal to peripheral, after override is applied - [19:19] - read-only - - - INFROMPAD - input signal from pad, before override is applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OEFROMPERI - output enable from selected peripheral, before register override is applied - [12:12] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - OUTFROMPERI - output signal from selected peripheral, before register override is applied - [8:8] - read-only - - - - - GPIO12_CTRL - 0x00000064 - GPIO control including function select and overrides. - 0x0000001f - - - IRQOVER - [29:28] - read-write - - - NORMAL - 0 - don't invert the interrupt - - - INVERT - 1 - invert the interrupt - - - LOW - 2 - drive interrupt low - - - HIGH - 3 - drive interrupt high - - - - - INOVER - [17:16] - read-write - - - NORMAL - 0 - don't invert the peri input - - - INVERT - 1 - invert the peri input - - - LOW - 2 - drive peri input low - - - HIGH - 3 - drive peri input high - - - - - OEOVER - [13:12] - read-write - - - NORMAL - 0 - drive output enable from peripheral signal selected by funcsel - - - INVERT - 1 - drive output enable from inverse of peripheral signal selected by funcsel - - - DISABLE - 2 - disable output - - - ENABLE - 3 - enable output - - - - - OUTOVER - [9:8] - read-write - - - NORMAL - 0 - drive output from peripheral signal selected by funcsel - - - INVERT - 1 - drive output from inverse of peripheral signal selected by funcsel - - - LOW - 2 - drive output low - - - HIGH - 3 - drive output high - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table - 31 == NULL - [4:0] - read-write - - - spi1_rx - 1 - - - uart0_tx - 2 - - - i2c0_sda - 3 - - - pwm_a_6 - 4 - - - sio_12 - 5 - - - pio0_12 - 6 - - - pio1_12 - 7 - - - usb_muxing_extphy_speed - 8 - - - usb_muxing_overcurr_detect - 9 - - - null - 31 - - - - - - - GPIO13_STATUS - 0x00000068 - GPIO status - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - IRQFROMPAD - interrupt from pad before override is applied - [24:24] - read-only - - - INTOPERI - input signal to peripheral, after override is applied - [19:19] - read-only - - - INFROMPAD - input signal from pad, before override is applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OEFROMPERI - output enable from selected peripheral, before register override is applied - [12:12] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - OUTFROMPERI - output signal from selected peripheral, before register override is applied - [8:8] - read-only - - - - - GPIO13_CTRL - 0x0000006c - GPIO control including function select and overrides. - 0x0000001f - - - IRQOVER - [29:28] - read-write - - - NORMAL - 0 - don't invert the interrupt - - - INVERT - 1 - invert the interrupt - - - LOW - 2 - drive interrupt low - - - HIGH - 3 - drive interrupt high - - - - - INOVER - [17:16] - read-write - - - NORMAL - 0 - don't invert the peri input - - - INVERT - 1 - invert the peri input - - - LOW - 2 - drive peri input low - - - HIGH - 3 - drive peri input high - - - - - OEOVER - [13:12] - read-write - - - NORMAL - 0 - drive output enable from peripheral signal selected by funcsel - - - INVERT - 1 - drive output enable from inverse of peripheral signal selected by funcsel - - - DISABLE - 2 - disable output - - - ENABLE - 3 - enable output - - - - - OUTOVER - [9:8] - read-write - - - NORMAL - 0 - drive output from peripheral signal selected by funcsel - - - INVERT - 1 - drive output from inverse of peripheral signal selected by funcsel - - - LOW - 2 - drive output low - - - HIGH - 3 - drive output high - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table - 31 == NULL - [4:0] - read-write - - - spi1_ss_n - 1 - - - uart0_rx - 2 - - - i2c0_scl - 3 - - - pwm_b_6 - 4 - - - sio_13 - 5 - - - pio0_13 - 6 - - - pio1_13 - 7 - - - usb_muxing_extphy_vpo - 8 - - - usb_muxing_vbus_detect - 9 - - - null - 31 - - - - - - - GPIO14_STATUS - 0x00000070 - GPIO status - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - IRQFROMPAD - interrupt from pad before override is applied - [24:24] - read-only - - - INTOPERI - input signal to peripheral, after override is applied - [19:19] - read-only - - - INFROMPAD - input signal from pad, before override is applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OEFROMPERI - output enable from selected peripheral, before register override is applied - [12:12] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - OUTFROMPERI - output signal from selected peripheral, before register override is applied - [8:8] - read-only - - - - - GPIO14_CTRL - 0x00000074 - GPIO control including function select and overrides. - 0x0000001f - - - IRQOVER - [29:28] - read-write - - - NORMAL - 0 - don't invert the interrupt - - - INVERT - 1 - invert the interrupt - - - LOW - 2 - drive interrupt low - - - HIGH - 3 - drive interrupt high - - - - - INOVER - [17:16] - read-write - - - NORMAL - 0 - don't invert the peri input - - - INVERT - 1 - invert the peri input - - - LOW - 2 - drive peri input low - - - HIGH - 3 - drive peri input high - - - - - OEOVER - [13:12] - read-write - - - NORMAL - 0 - drive output enable from peripheral signal selected by funcsel - - - INVERT - 1 - drive output enable from inverse of peripheral signal selected by funcsel - - - DISABLE - 2 - disable output - - - ENABLE - 3 - enable output - - - - - OUTOVER - [9:8] - read-write - - - NORMAL - 0 - drive output from peripheral signal selected by funcsel - - - INVERT - 1 - drive output from inverse of peripheral signal selected by funcsel - - - LOW - 2 - drive output low - - - HIGH - 3 - drive output high - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table - 31 == NULL - [4:0] - read-write - - - spi1_sclk - 1 - - - uart0_cts - 2 - - - i2c1_sda - 3 - - - pwm_a_7 - 4 - - - sio_14 - 5 - - - pio0_14 - 6 - - - pio1_14 - 7 - - - usb_muxing_extphy_vmo - 8 - - - usb_muxing_vbus_en - 9 - - - null - 31 - - - - - - - GPIO15_STATUS - 0x00000078 - GPIO status - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - IRQFROMPAD - interrupt from pad before override is applied - [24:24] - read-only - - - INTOPERI - input signal to peripheral, after override is applied - [19:19] - read-only - - - INFROMPAD - input signal from pad, before override is applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OEFROMPERI - output enable from selected peripheral, before register override is applied - [12:12] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - OUTFROMPERI - output signal from selected peripheral, before register override is applied - [8:8] - read-only - - - - - GPIO15_CTRL - 0x0000007c - GPIO control including function select and overrides. - 0x0000001f - - - IRQOVER - [29:28] - read-write - - - NORMAL - 0 - don't invert the interrupt - - - INVERT - 1 - invert the interrupt - - - LOW - 2 - drive interrupt low - - - HIGH - 3 - drive interrupt high - - - - - INOVER - [17:16] - read-write - - - NORMAL - 0 - don't invert the peri input - - - INVERT - 1 - invert the peri input - - - LOW - 2 - drive peri input low - - - HIGH - 3 - drive peri input high - - - - - OEOVER - [13:12] - read-write - - - NORMAL - 0 - drive output enable from peripheral signal selected by funcsel - - - INVERT - 1 - drive output enable from inverse of peripheral signal selected by funcsel - - - DISABLE - 2 - disable output - - - ENABLE - 3 - enable output - - - - - OUTOVER - [9:8] - read-write - - - NORMAL - 0 - drive output from peripheral signal selected by funcsel - - - INVERT - 1 - drive output from inverse of peripheral signal selected by funcsel - - - LOW - 2 - drive output low - - - HIGH - 3 - drive output high - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table - 31 == NULL - [4:0] - read-write - - - spi1_tx - 1 - - - uart0_rts - 2 - - - i2c1_scl - 3 - - - pwm_b_7 - 4 - - - sio_15 - 5 - - - pio0_15 - 6 - - - pio1_15 - 7 - - - usb_muxing_digital_dp - 8 - - - usb_muxing_overcurr_detect - 9 - - - null - 31 - - - - - - - GPIO16_STATUS - 0x00000080 - GPIO status - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - IRQFROMPAD - interrupt from pad before override is applied - [24:24] - read-only - - - INTOPERI - input signal to peripheral, after override is applied - [19:19] - read-only - - - INFROMPAD - input signal from pad, before override is applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OEFROMPERI - output enable from selected peripheral, before register override is applied - [12:12] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - OUTFROMPERI - output signal from selected peripheral, before register override is applied - [8:8] - read-only - - - - - GPIO16_CTRL - 0x00000084 - GPIO control including function select and overrides. - 0x0000001f - - - IRQOVER - [29:28] - read-write - - - NORMAL - 0 - don't invert the interrupt - - - INVERT - 1 - invert the interrupt - - - LOW - 2 - drive interrupt low - - - HIGH - 3 - drive interrupt high - - - - - INOVER - [17:16] - read-write - - - NORMAL - 0 - don't invert the peri input - - - INVERT - 1 - invert the peri input - - - LOW - 2 - drive peri input low - - - HIGH - 3 - drive peri input high - - - - - OEOVER - [13:12] - read-write - - - NORMAL - 0 - drive output enable from peripheral signal selected by funcsel - - - INVERT - 1 - drive output enable from inverse of peripheral signal selected by funcsel - - - DISABLE - 2 - disable output - - - ENABLE - 3 - enable output - - - - - OUTOVER - [9:8] - read-write - - - NORMAL - 0 - drive output from peripheral signal selected by funcsel - - - INVERT - 1 - drive output from inverse of peripheral signal selected by funcsel - - - LOW - 2 - drive output low - - - HIGH - 3 - drive output high - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table - 31 == NULL - [4:0] - read-write - - - spi0_rx - 1 - - - uart0_tx - 2 - - - i2c0_sda - 3 - - - pwm_a_0 - 4 - - - sio_16 - 5 - - - pio0_16 - 6 - - - pio1_16 - 7 - - - usb_muxing_digital_dm - 8 - - - usb_muxing_vbus_detect - 9 - - - null - 31 - - - - - - - GPIO17_STATUS - 0x00000088 - GPIO status - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - IRQFROMPAD - interrupt from pad before override is applied - [24:24] - read-only - - - INTOPERI - input signal to peripheral, after override is applied - [19:19] - read-only - - - INFROMPAD - input signal from pad, before override is applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OEFROMPERI - output enable from selected peripheral, before register override is applied - [12:12] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - OUTFROMPERI - output signal from selected peripheral, before register override is applied - [8:8] - read-only - - - - - GPIO17_CTRL - 0x0000008c - GPIO control including function select and overrides. - 0x0000001f - - - IRQOVER - [29:28] - read-write - - - NORMAL - 0 - don't invert the interrupt - - - INVERT - 1 - invert the interrupt - - - LOW - 2 - drive interrupt low - - - HIGH - 3 - drive interrupt high - - - - - INOVER - [17:16] - read-write - - - NORMAL - 0 - don't invert the peri input - - - INVERT - 1 - invert the peri input - - - LOW - 2 - drive peri input low - - - HIGH - 3 - drive peri input high - - - - - OEOVER - [13:12] - read-write - - - NORMAL - 0 - drive output enable from peripheral signal selected by funcsel - - - INVERT - 1 - drive output enable from inverse of peripheral signal selected by funcsel - - - DISABLE - 2 - disable output - - - ENABLE - 3 - enable output - - - - - OUTOVER - [9:8] - read-write - - - NORMAL - 0 - drive output from peripheral signal selected by funcsel - - - INVERT - 1 - drive output from inverse of peripheral signal selected by funcsel - - - LOW - 2 - drive output low - - - HIGH - 3 - drive output high - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table - 31 == NULL - [4:0] - read-write - - - spi0_ss_n - 1 - - - uart0_rx - 2 - - - i2c0_scl - 3 - - - pwm_b_0 - 4 - - - sio_17 - 5 - - - pio0_17 - 6 - - - pio1_17 - 7 - - - usb_muxing_vbus_en - 9 - - - null - 31 - - - - - - - GPIO18_STATUS - 0x00000090 - GPIO status - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - IRQFROMPAD - interrupt from pad before override is applied - [24:24] - read-only - - - INTOPERI - input signal to peripheral, after override is applied - [19:19] - read-only - - - INFROMPAD - input signal from pad, before override is applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OEFROMPERI - output enable from selected peripheral, before register override is applied - [12:12] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - OUTFROMPERI - output signal from selected peripheral, before register override is applied - [8:8] - read-only - - - - - GPIO18_CTRL - 0x00000094 - GPIO control including function select and overrides. - 0x0000001f - - - IRQOVER - [29:28] - read-write - - - NORMAL - 0 - don't invert the interrupt - - - INVERT - 1 - invert the interrupt - - - LOW - 2 - drive interrupt low - - - HIGH - 3 - drive interrupt high - - - - - INOVER - [17:16] - read-write - - - NORMAL - 0 - don't invert the peri input - - - INVERT - 1 - invert the peri input - - - LOW - 2 - drive peri input low - - - HIGH - 3 - drive peri input high - - - - - OEOVER - [13:12] - read-write - - - NORMAL - 0 - drive output enable from peripheral signal selected by funcsel - - - INVERT - 1 - drive output enable from inverse of peripheral signal selected by funcsel - - - DISABLE - 2 - disable output - - - ENABLE - 3 - enable output - - - - - OUTOVER - [9:8] - read-write - - - NORMAL - 0 - drive output from peripheral signal selected by funcsel - - - INVERT - 1 - drive output from inverse of peripheral signal selected by funcsel - - - LOW - 2 - drive output low - - - HIGH - 3 - drive output high - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table - 31 == NULL - [4:0] - read-write - - - spi0_sclk - 1 - - - uart0_cts - 2 - - - i2c1_sda - 3 - - - pwm_a_1 - 4 - - - sio_18 - 5 - - - pio0_18 - 6 - - - pio1_18 - 7 - - - usb_muxing_overcurr_detect - 9 - - - null - 31 - - - - - - - GPIO19_STATUS - 0x00000098 - GPIO status - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - IRQFROMPAD - interrupt from pad before override is applied - [24:24] - read-only - - - INTOPERI - input signal to peripheral, after override is applied - [19:19] - read-only - - - INFROMPAD - input signal from pad, before override is applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OEFROMPERI - output enable from selected peripheral, before register override is applied - [12:12] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - OUTFROMPERI - output signal from selected peripheral, before register override is applied - [8:8] - read-only - - - - - GPIO19_CTRL - 0x0000009c - GPIO control including function select and overrides. - 0x0000001f - - - IRQOVER - [29:28] - read-write - - - NORMAL - 0 - don't invert the interrupt - - - INVERT - 1 - invert the interrupt - - - LOW - 2 - drive interrupt low - - - HIGH - 3 - drive interrupt high - - - - - INOVER - [17:16] - read-write - - - NORMAL - 0 - don't invert the peri input - - - INVERT - 1 - invert the peri input - - - LOW - 2 - drive peri input low - - - HIGH - 3 - drive peri input high - - - - - OEOVER - [13:12] - read-write - - - NORMAL - 0 - drive output enable from peripheral signal selected by funcsel - - - INVERT - 1 - drive output enable from inverse of peripheral signal selected by funcsel - - - DISABLE - 2 - disable output - - - ENABLE - 3 - enable output - - - - - OUTOVER - [9:8] - read-write - - - NORMAL - 0 - drive output from peripheral signal selected by funcsel - - - INVERT - 1 - drive output from inverse of peripheral signal selected by funcsel - - - LOW - 2 - drive output low - - - HIGH - 3 - drive output high - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table - 31 == NULL - [4:0] - read-write - - - spi0_tx - 1 - - - uart0_rts - 2 - - - i2c1_scl - 3 - - - pwm_b_1 - 4 - - - sio_19 - 5 - - - pio0_19 - 6 - - - pio1_19 - 7 - - - usb_muxing_vbus_detect - 9 - - - null - 31 - - - - - - - GPIO20_STATUS - 0x000000a0 - GPIO status - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - IRQFROMPAD - interrupt from pad before override is applied - [24:24] - read-only - - - INTOPERI - input signal to peripheral, after override is applied - [19:19] - read-only - - - INFROMPAD - input signal from pad, before override is applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OEFROMPERI - output enable from selected peripheral, before register override is applied - [12:12] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - OUTFROMPERI - output signal from selected peripheral, before register override is applied - [8:8] - read-only - - - - - GPIO20_CTRL - 0x000000a4 - GPIO control including function select and overrides. - 0x0000001f - - - IRQOVER - [29:28] - read-write - - - NORMAL - 0 - don't invert the interrupt - - - INVERT - 1 - invert the interrupt - - - LOW - 2 - drive interrupt low - - - HIGH - 3 - drive interrupt high - - - - - INOVER - [17:16] - read-write - - - NORMAL - 0 - don't invert the peri input - - - INVERT - 1 - invert the peri input - - - LOW - 2 - drive peri input low - - - HIGH - 3 - drive peri input high - - - - - OEOVER - [13:12] - read-write - - - NORMAL - 0 - drive output enable from peripheral signal selected by funcsel - - - INVERT - 1 - drive output enable from inverse of peripheral signal selected by funcsel - - - DISABLE - 2 - disable output - - - ENABLE - 3 - enable output - - - - - OUTOVER - [9:8] - read-write - - - NORMAL - 0 - drive output from peripheral signal selected by funcsel - - - INVERT - 1 - drive output from inverse of peripheral signal selected by funcsel - - - LOW - 2 - drive output low - - - HIGH - 3 - drive output high - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table - 31 == NULL - [4:0] - read-write - - - spi0_rx - 1 - - - uart1_tx - 2 - - - i2c0_sda - 3 - - - pwm_a_2 - 4 - - - sio_20 - 5 - - - pio0_20 - 6 - - - pio1_20 - 7 - - - clocks_gpin_0 - 8 - - - usb_muxing_vbus_en - 9 - - - null - 31 - - - - - - - GPIO21_STATUS - 0x000000a8 - GPIO status - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - IRQFROMPAD - interrupt from pad before override is applied - [24:24] - read-only - - - INTOPERI - input signal to peripheral, after override is applied - [19:19] - read-only - - - INFROMPAD - input signal from pad, before override is applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OEFROMPERI - output enable from selected peripheral, before register override is applied - [12:12] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - OUTFROMPERI - output signal from selected peripheral, before register override is applied - [8:8] - read-only - - - - - GPIO21_CTRL - 0x000000ac - GPIO control including function select and overrides. - 0x0000001f - - - IRQOVER - [29:28] - read-write - - - NORMAL - 0 - don't invert the interrupt - - - INVERT - 1 - invert the interrupt - - - LOW - 2 - drive interrupt low - - - HIGH - 3 - drive interrupt high - - - - - INOVER - [17:16] - read-write - - - NORMAL - 0 - don't invert the peri input - - - INVERT - 1 - invert the peri input - - - LOW - 2 - drive peri input low - - - HIGH - 3 - drive peri input high - - - - - OEOVER - [13:12] - read-write - - - NORMAL - 0 - drive output enable from peripheral signal selected by funcsel - - - INVERT - 1 - drive output enable from inverse of peripheral signal selected by funcsel - - - DISABLE - 2 - disable output - - - ENABLE - 3 - enable output - - - - - OUTOVER - [9:8] - read-write - - - NORMAL - 0 - drive output from peripheral signal selected by funcsel - - - INVERT - 1 - drive output from inverse of peripheral signal selected by funcsel - - - LOW - 2 - drive output low - - - HIGH - 3 - drive output high - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table - 31 == NULL - [4:0] - read-write - - - spi0_ss_n - 1 - - - uart1_rx - 2 - - - i2c0_scl - 3 - - - pwm_b_2 - 4 - - - sio_21 - 5 - - - pio0_21 - 6 - - - pio1_21 - 7 - - - clocks_gpout_0 - 8 - - - usb_muxing_overcurr_detect - 9 - - - null - 31 - - - - - - - GPIO22_STATUS - 0x000000b0 - GPIO status - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - IRQFROMPAD - interrupt from pad before override is applied - [24:24] - read-only - - - INTOPERI - input signal to peripheral, after override is applied - [19:19] - read-only - - - INFROMPAD - input signal from pad, before override is applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OEFROMPERI - output enable from selected peripheral, before register override is applied - [12:12] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - OUTFROMPERI - output signal from selected peripheral, before register override is applied - [8:8] - read-only - - - - - GPIO22_CTRL - 0x000000b4 - GPIO control including function select and overrides. - 0x0000001f - - - IRQOVER - [29:28] - read-write - - - NORMAL - 0 - don't invert the interrupt - - - INVERT - 1 - invert the interrupt - - - LOW - 2 - drive interrupt low - - - HIGH - 3 - drive interrupt high - - - - - INOVER - [17:16] - read-write - - - NORMAL - 0 - don't invert the peri input - - - INVERT - 1 - invert the peri input - - - LOW - 2 - drive peri input low - - - HIGH - 3 - drive peri input high - - - - - OEOVER - [13:12] - read-write - - - NORMAL - 0 - drive output enable from peripheral signal selected by funcsel - - - INVERT - 1 - drive output enable from inverse of peripheral signal selected by funcsel - - - DISABLE - 2 - disable output - - - ENABLE - 3 - enable output - - - - - OUTOVER - [9:8] - read-write - - - NORMAL - 0 - drive output from peripheral signal selected by funcsel - - - INVERT - 1 - drive output from inverse of peripheral signal selected by funcsel - - - LOW - 2 - drive output low - - - HIGH - 3 - drive output high - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table - 31 == NULL - [4:0] - read-write - - - spi0_sclk - 1 - - - uart1_cts - 2 - - - i2c1_sda - 3 - - - pwm_a_3 - 4 - - - sio_22 - 5 - - - pio0_22 - 6 - - - pio1_22 - 7 - - - clocks_gpin_1 - 8 - - - usb_muxing_vbus_detect - 9 - - - null - 31 - - - - - - - GPIO23_STATUS - 0x000000b8 - GPIO status - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - IRQFROMPAD - interrupt from pad before override is applied - [24:24] - read-only - - - INTOPERI - input signal to peripheral, after override is applied - [19:19] - read-only - - - INFROMPAD - input signal from pad, before override is applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OEFROMPERI - output enable from selected peripheral, before register override is applied - [12:12] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - OUTFROMPERI - output signal from selected peripheral, before register override is applied - [8:8] - read-only - - - - - GPIO23_CTRL - 0x000000bc - GPIO control including function select and overrides. - 0x0000001f - - - IRQOVER - [29:28] - read-write - - - NORMAL - 0 - don't invert the interrupt - - - INVERT - 1 - invert the interrupt - - - LOW - 2 - drive interrupt low - - - HIGH - 3 - drive interrupt high - - - - - INOVER - [17:16] - read-write - - - NORMAL - 0 - don't invert the peri input - - - INVERT - 1 - invert the peri input - - - LOW - 2 - drive peri input low - - - HIGH - 3 - drive peri input high - - - - - OEOVER - [13:12] - read-write - - - NORMAL - 0 - drive output enable from peripheral signal selected by funcsel - - - INVERT - 1 - drive output enable from inverse of peripheral signal selected by funcsel - - - DISABLE - 2 - disable output - - - ENABLE - 3 - enable output - - - - - OUTOVER - [9:8] - read-write - - - NORMAL - 0 - drive output from peripheral signal selected by funcsel - - - INVERT - 1 - drive output from inverse of peripheral signal selected by funcsel - - - LOW - 2 - drive output low - - - HIGH - 3 - drive output high - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table - 31 == NULL - [4:0] - read-write - - - spi0_tx - 1 - - - uart1_rts - 2 - - - i2c1_scl - 3 - - - pwm_b_3 - 4 - - - sio_23 - 5 - - - pio0_23 - 6 - - - pio1_23 - 7 - - - clocks_gpout_1 - 8 - - - usb_muxing_vbus_en - 9 - - - null - 31 - - - - - - - GPIO24_STATUS - 0x000000c0 - GPIO status - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - IRQFROMPAD - interrupt from pad before override is applied - [24:24] - read-only - - - INTOPERI - input signal to peripheral, after override is applied - [19:19] - read-only - - - INFROMPAD - input signal from pad, before override is applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OEFROMPERI - output enable from selected peripheral, before register override is applied - [12:12] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - OUTFROMPERI - output signal from selected peripheral, before register override is applied - [8:8] - read-only - - - - - GPIO24_CTRL - 0x000000c4 - GPIO control including function select and overrides. - 0x0000001f - - - IRQOVER - [29:28] - read-write - - - NORMAL - 0 - don't invert the interrupt - - - INVERT - 1 - invert the interrupt - - - LOW - 2 - drive interrupt low - - - HIGH - 3 - drive interrupt high - - - - - INOVER - [17:16] - read-write - - - NORMAL - 0 - don't invert the peri input - - - INVERT - 1 - invert the peri input - - - LOW - 2 - drive peri input low - - - HIGH - 3 - drive peri input high - - - - - OEOVER - [13:12] - read-write - - - NORMAL - 0 - drive output enable from peripheral signal selected by funcsel - - - INVERT - 1 - drive output enable from inverse of peripheral signal selected by funcsel - - - DISABLE - 2 - disable output - - - ENABLE - 3 - enable output - - - - - OUTOVER - [9:8] - read-write - - - NORMAL - 0 - drive output from peripheral signal selected by funcsel - - - INVERT - 1 - drive output from inverse of peripheral signal selected by funcsel - - - LOW - 2 - drive output low - - - HIGH - 3 - drive output high - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table - 31 == NULL - [4:0] - read-write - - - spi1_rx - 1 - - - uart1_tx - 2 - - - i2c0_sda - 3 - - - pwm_a_4 - 4 - - - sio_24 - 5 - - - pio0_24 - 6 - - - pio1_24 - 7 - - - clocks_gpout_2 - 8 - - - usb_muxing_overcurr_detect - 9 - - - null - 31 - - - - - - - GPIO25_STATUS - 0x000000c8 - GPIO status - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - IRQFROMPAD - interrupt from pad before override is applied - [24:24] - read-only - - - INTOPERI - input signal to peripheral, after override is applied - [19:19] - read-only - - - INFROMPAD - input signal from pad, before override is applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OEFROMPERI - output enable from selected peripheral, before register override is applied - [12:12] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - OUTFROMPERI - output signal from selected peripheral, before register override is applied - [8:8] - read-only - - - - - GPIO25_CTRL - 0x000000cc - GPIO control including function select and overrides. - 0x0000001f - - - IRQOVER - [29:28] - read-write - - - NORMAL - 0 - don't invert the interrupt - - - INVERT - 1 - invert the interrupt - - - LOW - 2 - drive interrupt low - - - HIGH - 3 - drive interrupt high - - - - - INOVER - [17:16] - read-write - - - NORMAL - 0 - don't invert the peri input - - - INVERT - 1 - invert the peri input - - - LOW - 2 - drive peri input low - - - HIGH - 3 - drive peri input high - - - - - OEOVER - [13:12] - read-write - - - NORMAL - 0 - drive output enable from peripheral signal selected by funcsel - - - INVERT - 1 - drive output enable from inverse of peripheral signal selected by funcsel - - - DISABLE - 2 - disable output - - - ENABLE - 3 - enable output - - - - - OUTOVER - [9:8] - read-write - - - NORMAL - 0 - drive output from peripheral signal selected by funcsel - - - INVERT - 1 - drive output from inverse of peripheral signal selected by funcsel - - - LOW - 2 - drive output low - - - HIGH - 3 - drive output high - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table - 31 == NULL - [4:0] - read-write - - - spi1_ss_n - 1 - - - uart1_rx - 2 - - - i2c0_scl - 3 - - - pwm_b_4 - 4 - - - sio_25 - 5 - - - pio0_25 - 6 - - - pio1_25 - 7 - - - clocks_gpout_3 - 8 - - - usb_muxing_vbus_detect - 9 - - - null - 31 - - - - - - - GPIO26_STATUS - 0x000000d0 - GPIO status - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - IRQFROMPAD - interrupt from pad before override is applied - [24:24] - read-only - - - INTOPERI - input signal to peripheral, after override is applied - [19:19] - read-only - - - INFROMPAD - input signal from pad, before override is applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OEFROMPERI - output enable from selected peripheral, before register override is applied - [12:12] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - OUTFROMPERI - output signal from selected peripheral, before register override is applied - [8:8] - read-only - - - - - GPIO26_CTRL - 0x000000d4 - GPIO control including function select and overrides. - 0x0000001f - - - IRQOVER - [29:28] - read-write - - - NORMAL - 0 - don't invert the interrupt - - - INVERT - 1 - invert the interrupt - - - LOW - 2 - drive interrupt low - - - HIGH - 3 - drive interrupt high - - - - - INOVER - [17:16] - read-write - - - NORMAL - 0 - don't invert the peri input - - - INVERT - 1 - invert the peri input - - - LOW - 2 - drive peri input low - - - HIGH - 3 - drive peri input high - - - - - OEOVER - [13:12] - read-write - - - NORMAL - 0 - drive output enable from peripheral signal selected by funcsel - - - INVERT - 1 - drive output enable from inverse of peripheral signal selected by funcsel - - - DISABLE - 2 - disable output - - - ENABLE - 3 - enable output - - - - - OUTOVER - [9:8] - read-write - - - NORMAL - 0 - drive output from peripheral signal selected by funcsel - - - INVERT - 1 - drive output from inverse of peripheral signal selected by funcsel - - - LOW - 2 - drive output low - - - HIGH - 3 - drive output high - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table - 31 == NULL - [4:0] - read-write - - - spi1_sclk - 1 - - - uart1_cts - 2 - - - i2c1_sda - 3 - - - pwm_a_5 - 4 - - - sio_26 - 5 - - - pio0_26 - 6 - - - pio1_26 - 7 - - - usb_muxing_vbus_en - 9 - - - null - 31 - - - - - - - GPIO27_STATUS - 0x000000d8 - GPIO status - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - IRQFROMPAD - interrupt from pad before override is applied - [24:24] - read-only - - - INTOPERI - input signal to peripheral, after override is applied - [19:19] - read-only - - - INFROMPAD - input signal from pad, before override is applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OEFROMPERI - output enable from selected peripheral, before register override is applied - [12:12] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - OUTFROMPERI - output signal from selected peripheral, before register override is applied - [8:8] - read-only - - - - - GPIO27_CTRL - 0x000000dc - GPIO control including function select and overrides. - 0x0000001f - - - IRQOVER - [29:28] - read-write - - - NORMAL - 0 - don't invert the interrupt - - - INVERT - 1 - invert the interrupt - - - LOW - 2 - drive interrupt low - - - HIGH - 3 - drive interrupt high - - - - - INOVER - [17:16] - read-write - - - NORMAL - 0 - don't invert the peri input - - - INVERT - 1 - invert the peri input - - - LOW - 2 - drive peri input low - - - HIGH - 3 - drive peri input high - - - - - OEOVER - [13:12] - read-write - - - NORMAL - 0 - drive output enable from peripheral signal selected by funcsel - - - INVERT - 1 - drive output enable from inverse of peripheral signal selected by funcsel - - - DISABLE - 2 - disable output - - - ENABLE - 3 - enable output - - - - - OUTOVER - [9:8] - read-write - - - NORMAL - 0 - drive output from peripheral signal selected by funcsel - - - INVERT - 1 - drive output from inverse of peripheral signal selected by funcsel - - - LOW - 2 - drive output low - - - HIGH - 3 - drive output high - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table - 31 == NULL - [4:0] - read-write - - - spi1_tx - 1 - - - uart1_rts - 2 - - - i2c1_scl - 3 - - - pwm_b_5 - 4 - - - sio_27 - 5 - - - pio0_27 - 6 - - - pio1_27 - 7 - - - usb_muxing_overcurr_detect - 9 - - - null - 31 - - - - - - - GPIO28_STATUS - 0x000000e0 - GPIO status - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - IRQFROMPAD - interrupt from pad before override is applied - [24:24] - read-only - - - INTOPERI - input signal to peripheral, after override is applied - [19:19] - read-only - - - INFROMPAD - input signal from pad, before override is applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OEFROMPERI - output enable from selected peripheral, before register override is applied - [12:12] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - OUTFROMPERI - output signal from selected peripheral, before register override is applied - [8:8] - read-only - - - - - GPIO28_CTRL - 0x000000e4 - GPIO control including function select and overrides. - 0x0000001f - - - IRQOVER - [29:28] - read-write - - - NORMAL - 0 - don't invert the interrupt - - - INVERT - 1 - invert the interrupt - - - LOW - 2 - drive interrupt low - - - HIGH - 3 - drive interrupt high - - - - - INOVER - [17:16] - read-write - - - NORMAL - 0 - don't invert the peri input - - - INVERT - 1 - invert the peri input - - - LOW - 2 - drive peri input low - - - HIGH - 3 - drive peri input high - - - - - OEOVER - [13:12] - read-write - - - NORMAL - 0 - drive output enable from peripheral signal selected by funcsel - - - INVERT - 1 - drive output enable from inverse of peripheral signal selected by funcsel - - - DISABLE - 2 - disable output - - - ENABLE - 3 - enable output - - - - - OUTOVER - [9:8] - read-write - - - NORMAL - 0 - drive output from peripheral signal selected by funcsel - - - INVERT - 1 - drive output from inverse of peripheral signal selected by funcsel - - - LOW - 2 - drive output low - - - HIGH - 3 - drive output high - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table - 31 == NULL - [4:0] - read-write - - - spi1_rx - 1 - - - uart0_tx - 2 - - - i2c0_sda - 3 - - - pwm_a_6 - 4 - - - sio_28 - 5 - - - pio0_28 - 6 - - - pio1_28 - 7 - - - usb_muxing_vbus_detect - 9 - - - null - 31 - - - - - - - GPIO29_STATUS - 0x000000e8 - GPIO status - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - IRQFROMPAD - interrupt from pad before override is applied - [24:24] - read-only - - - INTOPERI - input signal to peripheral, after override is applied - [19:19] - read-only - - - INFROMPAD - input signal from pad, before override is applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OEFROMPERI - output enable from selected peripheral, before register override is applied - [12:12] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - OUTFROMPERI - output signal from selected peripheral, before register override is applied - [8:8] - read-only - - - - - GPIO29_CTRL - 0x000000ec - GPIO control including function select and overrides. - 0x0000001f - - - IRQOVER - [29:28] - read-write - - - NORMAL - 0 - don't invert the interrupt - - - INVERT - 1 - invert the interrupt - - - LOW - 2 - drive interrupt low - - - HIGH - 3 - drive interrupt high - - - - - INOVER - [17:16] - read-write - - - NORMAL - 0 - don't invert the peri input - - - INVERT - 1 - invert the peri input - - - LOW - 2 - drive peri input low - - - HIGH - 3 - drive peri input high - - - - - OEOVER - [13:12] - read-write - - - NORMAL - 0 - drive output enable from peripheral signal selected by funcsel - - - INVERT - 1 - drive output enable from inverse of peripheral signal selected by funcsel - - - DISABLE - 2 - disable output - - - ENABLE - 3 - enable output - - - - - OUTOVER - [9:8] - read-write - - - NORMAL - 0 - drive output from peripheral signal selected by funcsel - - - INVERT - 1 - drive output from inverse of peripheral signal selected by funcsel - - - LOW - 2 - drive output low - - - HIGH - 3 - drive output high - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table - 31 == NULL - [4:0] - read-write - - - spi1_ss_n - 1 - - - uart0_rx - 2 - - - i2c0_scl - 3 - - - pwm_b_6 - 4 - - - sio_29 - 5 - - - pio0_29 - 6 - - - pio1_29 - 7 - - - usb_muxing_vbus_en - 9 - - - null - 31 - - - - - - - INTR0 - 0x000000f0 - Raw Interrupts - 0x00000000 - - - GPIO7_EDGE_HIGH - [31:31] - read-write - oneToClear - - - GPIO7_EDGE_LOW - [30:30] - read-write - oneToClear - - - GPIO7_LEVEL_HIGH - [29:29] - read-only - - - GPIO7_LEVEL_LOW - [28:28] - read-only - - - GPIO6_EDGE_HIGH - [27:27] - read-write - oneToClear - - - GPIO6_EDGE_LOW - [26:26] - read-write - oneToClear - - - GPIO6_LEVEL_HIGH - [25:25] - read-only - - - GPIO6_LEVEL_LOW - [24:24] - read-only - - - GPIO5_EDGE_HIGH - [23:23] - read-write - oneToClear - - - GPIO5_EDGE_LOW - [22:22] - read-write - oneToClear - - - GPIO5_LEVEL_HIGH - [21:21] - read-only - - - GPIO5_LEVEL_LOW - [20:20] - read-only - - - GPIO4_EDGE_HIGH - [19:19] - read-write - oneToClear - - - GPIO4_EDGE_LOW - [18:18] - read-write - oneToClear - - - GPIO4_LEVEL_HIGH - [17:17] - read-only - - - GPIO4_LEVEL_LOW - [16:16] - read-only - - - GPIO3_EDGE_HIGH - [15:15] - read-write - oneToClear - - - GPIO3_EDGE_LOW - [14:14] - read-write - oneToClear - - - GPIO3_LEVEL_HIGH - [13:13] - read-only - - - GPIO3_LEVEL_LOW - [12:12] - read-only - - - GPIO2_EDGE_HIGH - [11:11] - read-write - oneToClear - - - GPIO2_EDGE_LOW - [10:10] - read-write - oneToClear - - - GPIO2_LEVEL_HIGH - [9:9] - read-only - - - GPIO2_LEVEL_LOW - [8:8] - read-only - - - GPIO1_EDGE_HIGH - [7:7] - read-write - oneToClear - - - GPIO1_EDGE_LOW - [6:6] - read-write - oneToClear - - - GPIO1_LEVEL_HIGH - [5:5] - read-only - - - GPIO1_LEVEL_LOW - [4:4] - read-only - - - GPIO0_EDGE_HIGH - [3:3] - read-write - oneToClear - - - GPIO0_EDGE_LOW - [2:2] - read-write - oneToClear - - - GPIO0_LEVEL_HIGH - [1:1] - read-only - - - GPIO0_LEVEL_LOW - [0:0] - read-only - - - - - INTR1 - 0x000000f4 - Raw Interrupts - 0x00000000 - - - GPIO15_EDGE_HIGH - [31:31] - read-write - oneToClear - - - GPIO15_EDGE_LOW - [30:30] - read-write - oneToClear - - - GPIO15_LEVEL_HIGH - [29:29] - read-only - - - GPIO15_LEVEL_LOW - [28:28] - read-only - - - GPIO14_EDGE_HIGH - [27:27] - read-write - oneToClear - - - GPIO14_EDGE_LOW - [26:26] - read-write - oneToClear - - - GPIO14_LEVEL_HIGH - [25:25] - read-only - - - GPIO14_LEVEL_LOW - [24:24] - read-only - - - GPIO13_EDGE_HIGH - [23:23] - read-write - oneToClear - - - GPIO13_EDGE_LOW - [22:22] - read-write - oneToClear - - - GPIO13_LEVEL_HIGH - [21:21] - read-only - - - GPIO13_LEVEL_LOW - [20:20] - read-only - - - GPIO12_EDGE_HIGH - [19:19] - read-write - oneToClear - - - GPIO12_EDGE_LOW - [18:18] - read-write - oneToClear - - - GPIO12_LEVEL_HIGH - [17:17] - read-only - - - GPIO12_LEVEL_LOW - [16:16] - read-only - - - GPIO11_EDGE_HIGH - [15:15] - read-write - oneToClear - - - GPIO11_EDGE_LOW - [14:14] - read-write - oneToClear - - - GPIO11_LEVEL_HIGH - [13:13] - read-only - - - GPIO11_LEVEL_LOW - [12:12] - read-only - - - GPIO10_EDGE_HIGH - [11:11] - read-write - oneToClear - - - GPIO10_EDGE_LOW - [10:10] - read-write - oneToClear - - - GPIO10_LEVEL_HIGH - [9:9] - read-only - - - GPIO10_LEVEL_LOW - [8:8] - read-only - - - GPIO9_EDGE_HIGH - [7:7] - read-write - oneToClear - - - GPIO9_EDGE_LOW - [6:6] - read-write - oneToClear - - - GPIO9_LEVEL_HIGH - [5:5] - read-only - - - GPIO9_LEVEL_LOW - [4:4] - read-only - - - GPIO8_EDGE_HIGH - [3:3] - read-write - oneToClear - - - GPIO8_EDGE_LOW - [2:2] - read-write - oneToClear - - - GPIO8_LEVEL_HIGH - [1:1] - read-only - - - GPIO8_LEVEL_LOW - [0:0] - read-only - - - - - INTR2 - 0x000000f8 - Raw Interrupts - 0x00000000 - - - GPIO23_EDGE_HIGH - [31:31] - read-write - oneToClear - - - GPIO23_EDGE_LOW - [30:30] - read-write - oneToClear - - - GPIO23_LEVEL_HIGH - [29:29] - read-only - - - GPIO23_LEVEL_LOW - [28:28] - read-only - - - GPIO22_EDGE_HIGH - [27:27] - read-write - oneToClear - - - GPIO22_EDGE_LOW - [26:26] - read-write - oneToClear - - - GPIO22_LEVEL_HIGH - [25:25] - read-only - - - GPIO22_LEVEL_LOW - [24:24] - read-only - - - GPIO21_EDGE_HIGH - [23:23] - read-write - oneToClear - - - GPIO21_EDGE_LOW - [22:22] - read-write - oneToClear - - - GPIO21_LEVEL_HIGH - [21:21] - read-only - - - GPIO21_LEVEL_LOW - [20:20] - read-only - - - GPIO20_EDGE_HIGH - [19:19] - read-write - oneToClear - - - GPIO20_EDGE_LOW - [18:18] - read-write - oneToClear - - - GPIO20_LEVEL_HIGH - [17:17] - read-only - - - GPIO20_LEVEL_LOW - [16:16] - read-only - - - GPIO19_EDGE_HIGH - [15:15] - read-write - oneToClear - - - GPIO19_EDGE_LOW - [14:14] - read-write - oneToClear - - - GPIO19_LEVEL_HIGH - [13:13] - read-only - - - GPIO19_LEVEL_LOW - [12:12] - read-only - - - GPIO18_EDGE_HIGH - [11:11] - read-write - oneToClear - - - GPIO18_EDGE_LOW - [10:10] - read-write - oneToClear - - - GPIO18_LEVEL_HIGH - [9:9] - read-only - - - GPIO18_LEVEL_LOW - [8:8] - read-only - - - GPIO17_EDGE_HIGH - [7:7] - read-write - oneToClear - - - GPIO17_EDGE_LOW - [6:6] - read-write - oneToClear - - - GPIO17_LEVEL_HIGH - [5:5] - read-only - - - GPIO17_LEVEL_LOW - [4:4] - read-only - - - GPIO16_EDGE_HIGH - [3:3] - read-write - oneToClear - - - GPIO16_EDGE_LOW - [2:2] - read-write - oneToClear - - - GPIO16_LEVEL_HIGH - [1:1] - read-only - - - GPIO16_LEVEL_LOW - [0:0] - read-only - - - - - INTR3 - 0x000000fc - Raw Interrupts - 0x00000000 - - - GPIO29_EDGE_HIGH - [23:23] - read-write - oneToClear - - - GPIO29_EDGE_LOW - [22:22] - read-write - oneToClear - - - GPIO29_LEVEL_HIGH - [21:21] - read-only - - - GPIO29_LEVEL_LOW - [20:20] - read-only - - - GPIO28_EDGE_HIGH - [19:19] - read-write - oneToClear - - - GPIO28_EDGE_LOW - [18:18] - read-write - oneToClear - - - GPIO28_LEVEL_HIGH - [17:17] - read-only - - - GPIO28_LEVEL_LOW - [16:16] - read-only - - - GPIO27_EDGE_HIGH - [15:15] - read-write - oneToClear - - - GPIO27_EDGE_LOW - [14:14] - read-write - oneToClear - - - GPIO27_LEVEL_HIGH - [13:13] - read-only - - - GPIO27_LEVEL_LOW - [12:12] - read-only - - - GPIO26_EDGE_HIGH - [11:11] - read-write - oneToClear - - - GPIO26_EDGE_LOW - [10:10] - read-write - oneToClear - - - GPIO26_LEVEL_HIGH - [9:9] - read-only - - - GPIO26_LEVEL_LOW - [8:8] - read-only - - - GPIO25_EDGE_HIGH - [7:7] - read-write - oneToClear - - - GPIO25_EDGE_LOW - [6:6] - read-write - oneToClear - - - GPIO25_LEVEL_HIGH - [5:5] - read-only - - - GPIO25_LEVEL_LOW - [4:4] - read-only - - - GPIO24_EDGE_HIGH - [3:3] - read-write - oneToClear - - - GPIO24_EDGE_LOW - [2:2] - read-write - oneToClear - - - GPIO24_LEVEL_HIGH - [1:1] - read-only - - - GPIO24_LEVEL_LOW - [0:0] - read-only - - - - - PROC0_INTE0 - 0x00000100 - Interrupt Enable for proc0 - 0x00000000 - - - GPIO7_EDGE_HIGH - [31:31] - read-write - - - GPIO7_EDGE_LOW - [30:30] - read-write - - - GPIO7_LEVEL_HIGH - [29:29] - read-write - - - GPIO7_LEVEL_LOW - [28:28] - read-write - - - GPIO6_EDGE_HIGH - [27:27] - read-write - - - GPIO6_EDGE_LOW - [26:26] - read-write - - - GPIO6_LEVEL_HIGH - [25:25] - read-write - - - GPIO6_LEVEL_LOW - [24:24] - read-write - - - GPIO5_EDGE_HIGH - [23:23] - read-write - - - GPIO5_EDGE_LOW - [22:22] - read-write - - - GPIO5_LEVEL_HIGH - [21:21] - read-write - - - GPIO5_LEVEL_LOW - [20:20] - read-write - - - GPIO4_EDGE_HIGH - [19:19] - read-write - - - GPIO4_EDGE_LOW - [18:18] - read-write - - - GPIO4_LEVEL_HIGH - [17:17] - read-write - - - GPIO4_LEVEL_LOW - [16:16] - read-write - - - GPIO3_EDGE_HIGH - [15:15] - read-write - - - GPIO3_EDGE_LOW - [14:14] - read-write - - - GPIO3_LEVEL_HIGH - [13:13] - read-write - - - GPIO3_LEVEL_LOW - [12:12] - read-write - - - GPIO2_EDGE_HIGH - [11:11] - read-write - - - GPIO2_EDGE_LOW - [10:10] - read-write - - - GPIO2_LEVEL_HIGH - [9:9] - read-write - - - GPIO2_LEVEL_LOW - [8:8] - read-write - - - GPIO1_EDGE_HIGH - [7:7] - read-write - - - GPIO1_EDGE_LOW - [6:6] - read-write - - - GPIO1_LEVEL_HIGH - [5:5] - read-write - - - GPIO1_LEVEL_LOW - [4:4] - read-write - - - GPIO0_EDGE_HIGH - [3:3] - read-write - - - GPIO0_EDGE_LOW - [2:2] - read-write - - - GPIO0_LEVEL_HIGH - [1:1] - read-write - - - GPIO0_LEVEL_LOW - [0:0] - read-write - - - - - PROC0_INTE1 - 0x00000104 - Interrupt Enable for proc0 - 0x00000000 - - - GPIO15_EDGE_HIGH - [31:31] - read-write - - - GPIO15_EDGE_LOW - [30:30] - read-write - - - GPIO15_LEVEL_HIGH - [29:29] - read-write - - - GPIO15_LEVEL_LOW - [28:28] - read-write - - - GPIO14_EDGE_HIGH - [27:27] - read-write - - - GPIO14_EDGE_LOW - [26:26] - read-write - - - GPIO14_LEVEL_HIGH - [25:25] - read-write - - - GPIO14_LEVEL_LOW - [24:24] - read-write - - - GPIO13_EDGE_HIGH - [23:23] - read-write - - - GPIO13_EDGE_LOW - [22:22] - read-write - - - GPIO13_LEVEL_HIGH - [21:21] - read-write - - - GPIO13_LEVEL_LOW - [20:20] - read-write - - - GPIO12_EDGE_HIGH - [19:19] - read-write - - - GPIO12_EDGE_LOW - [18:18] - read-write - - - GPIO12_LEVEL_HIGH - [17:17] - read-write - - - GPIO12_LEVEL_LOW - [16:16] - read-write - - - GPIO11_EDGE_HIGH - [15:15] - read-write - - - GPIO11_EDGE_LOW - [14:14] - read-write - - - GPIO11_LEVEL_HIGH - [13:13] - read-write - - - GPIO11_LEVEL_LOW - [12:12] - read-write - - - GPIO10_EDGE_HIGH - [11:11] - read-write - - - GPIO10_EDGE_LOW - [10:10] - read-write - - - GPIO10_LEVEL_HIGH - [9:9] - read-write - - - GPIO10_LEVEL_LOW - [8:8] - read-write - - - GPIO9_EDGE_HIGH - [7:7] - read-write - - - GPIO9_EDGE_LOW - [6:6] - read-write - - - GPIO9_LEVEL_HIGH - [5:5] - read-write - - - GPIO9_LEVEL_LOW - [4:4] - read-write - - - GPIO8_EDGE_HIGH - [3:3] - read-write - - - GPIO8_EDGE_LOW - [2:2] - read-write - - - GPIO8_LEVEL_HIGH - [1:1] - read-write - - - GPIO8_LEVEL_LOW - [0:0] - read-write - - - - - PROC0_INTE2 - 0x00000108 - Interrupt Enable for proc0 - 0x00000000 - - - GPIO23_EDGE_HIGH - [31:31] - read-write - - - GPIO23_EDGE_LOW - [30:30] - read-write - - - GPIO23_LEVEL_HIGH - [29:29] - read-write - - - GPIO23_LEVEL_LOW - [28:28] - read-write - - - GPIO22_EDGE_HIGH - [27:27] - read-write - - - GPIO22_EDGE_LOW - [26:26] - read-write - - - GPIO22_LEVEL_HIGH - [25:25] - read-write - - - GPIO22_LEVEL_LOW - [24:24] - read-write - - - GPIO21_EDGE_HIGH - [23:23] - read-write - - - GPIO21_EDGE_LOW - [22:22] - read-write - - - GPIO21_LEVEL_HIGH - [21:21] - read-write - - - GPIO21_LEVEL_LOW - [20:20] - read-write - - - GPIO20_EDGE_HIGH - [19:19] - read-write - - - GPIO20_EDGE_LOW - [18:18] - read-write - - - GPIO20_LEVEL_HIGH - [17:17] - read-write - - - GPIO20_LEVEL_LOW - [16:16] - read-write - - - GPIO19_EDGE_HIGH - [15:15] - read-write - - - GPIO19_EDGE_LOW - [14:14] - read-write - - - GPIO19_LEVEL_HIGH - [13:13] - read-write - - - GPIO19_LEVEL_LOW - [12:12] - read-write - - - GPIO18_EDGE_HIGH - [11:11] - read-write - - - GPIO18_EDGE_LOW - [10:10] - read-write - - - GPIO18_LEVEL_HIGH - [9:9] - read-write - - - GPIO18_LEVEL_LOW - [8:8] - read-write - - - GPIO17_EDGE_HIGH - [7:7] - read-write - - - GPIO17_EDGE_LOW - [6:6] - read-write - - - GPIO17_LEVEL_HIGH - [5:5] - read-write - - - GPIO17_LEVEL_LOW - [4:4] - read-write - - - GPIO16_EDGE_HIGH - [3:3] - read-write - - - GPIO16_EDGE_LOW - [2:2] - read-write - - - GPIO16_LEVEL_HIGH - [1:1] - read-write - - - GPIO16_LEVEL_LOW - [0:0] - read-write - - - - - PROC0_INTE3 - 0x0000010c - Interrupt Enable for proc0 - 0x00000000 - - - GPIO29_EDGE_HIGH - [23:23] - read-write - - - GPIO29_EDGE_LOW - [22:22] - read-write - - - GPIO29_LEVEL_HIGH - [21:21] - read-write - - - GPIO29_LEVEL_LOW - [20:20] - read-write - - - GPIO28_EDGE_HIGH - [19:19] - read-write - - - GPIO28_EDGE_LOW - [18:18] - read-write - - - GPIO28_LEVEL_HIGH - [17:17] - read-write - - - GPIO28_LEVEL_LOW - [16:16] - read-write - - - GPIO27_EDGE_HIGH - [15:15] - read-write - - - GPIO27_EDGE_LOW - [14:14] - read-write - - - GPIO27_LEVEL_HIGH - [13:13] - read-write - - - GPIO27_LEVEL_LOW - [12:12] - read-write - - - GPIO26_EDGE_HIGH - [11:11] - read-write - - - GPIO26_EDGE_LOW - [10:10] - read-write - - - GPIO26_LEVEL_HIGH - [9:9] - read-write - - - GPIO26_LEVEL_LOW - [8:8] - read-write - - - GPIO25_EDGE_HIGH - [7:7] - read-write - - - GPIO25_EDGE_LOW - [6:6] - read-write - - - GPIO25_LEVEL_HIGH - [5:5] - read-write - - - GPIO25_LEVEL_LOW - [4:4] - read-write - - - GPIO24_EDGE_HIGH - [3:3] - read-write - - - GPIO24_EDGE_LOW - [2:2] - read-write - - - GPIO24_LEVEL_HIGH - [1:1] - read-write - - - GPIO24_LEVEL_LOW - [0:0] - read-write - - - - - PROC0_INTF0 - 0x00000110 - Interrupt Force for proc0 - 0x00000000 - - - GPIO7_EDGE_HIGH - [31:31] - read-write - - - GPIO7_EDGE_LOW - [30:30] - read-write - - - GPIO7_LEVEL_HIGH - [29:29] - read-write - - - GPIO7_LEVEL_LOW - [28:28] - read-write - - - GPIO6_EDGE_HIGH - [27:27] - read-write - - - GPIO6_EDGE_LOW - [26:26] - read-write - - - GPIO6_LEVEL_HIGH - [25:25] - read-write - - - GPIO6_LEVEL_LOW - [24:24] - read-write - - - GPIO5_EDGE_HIGH - [23:23] - read-write - - - GPIO5_EDGE_LOW - [22:22] - read-write - - - GPIO5_LEVEL_HIGH - [21:21] - read-write - - - GPIO5_LEVEL_LOW - [20:20] - read-write - - - GPIO4_EDGE_HIGH - [19:19] - read-write - - - GPIO4_EDGE_LOW - [18:18] - read-write - - - GPIO4_LEVEL_HIGH - [17:17] - read-write - - - GPIO4_LEVEL_LOW - [16:16] - read-write - - - GPIO3_EDGE_HIGH - [15:15] - read-write - - - GPIO3_EDGE_LOW - [14:14] - read-write - - - GPIO3_LEVEL_HIGH - [13:13] - read-write - - - GPIO3_LEVEL_LOW - [12:12] - read-write - - - GPIO2_EDGE_HIGH - [11:11] - read-write - - - GPIO2_EDGE_LOW - [10:10] - read-write - - - GPIO2_LEVEL_HIGH - [9:9] - read-write - - - GPIO2_LEVEL_LOW - [8:8] - read-write - - - GPIO1_EDGE_HIGH - [7:7] - read-write - - - GPIO1_EDGE_LOW - [6:6] - read-write - - - GPIO1_LEVEL_HIGH - [5:5] - read-write - - - GPIO1_LEVEL_LOW - [4:4] - read-write - - - GPIO0_EDGE_HIGH - [3:3] - read-write - - - GPIO0_EDGE_LOW - [2:2] - read-write - - - GPIO0_LEVEL_HIGH - [1:1] - read-write - - - GPIO0_LEVEL_LOW - [0:0] - read-write - - - - - PROC0_INTF1 - 0x00000114 - Interrupt Force for proc0 - 0x00000000 - - - GPIO15_EDGE_HIGH - [31:31] - read-write - - - GPIO15_EDGE_LOW - [30:30] - read-write - - - GPIO15_LEVEL_HIGH - [29:29] - read-write - - - GPIO15_LEVEL_LOW - [28:28] - read-write - - - GPIO14_EDGE_HIGH - [27:27] - read-write - - - GPIO14_EDGE_LOW - [26:26] - read-write - - - GPIO14_LEVEL_HIGH - [25:25] - read-write - - - GPIO14_LEVEL_LOW - [24:24] - read-write - - - GPIO13_EDGE_HIGH - [23:23] - read-write - - - GPIO13_EDGE_LOW - [22:22] - read-write - - - GPIO13_LEVEL_HIGH - [21:21] - read-write - - - GPIO13_LEVEL_LOW - [20:20] - read-write - - - GPIO12_EDGE_HIGH - [19:19] - read-write - - - GPIO12_EDGE_LOW - [18:18] - read-write - - - GPIO12_LEVEL_HIGH - [17:17] - read-write - - - GPIO12_LEVEL_LOW - [16:16] - read-write - - - GPIO11_EDGE_HIGH - [15:15] - read-write - - - GPIO11_EDGE_LOW - [14:14] - read-write - - - GPIO11_LEVEL_HIGH - [13:13] - read-write - - - GPIO11_LEVEL_LOW - [12:12] - read-write - - - GPIO10_EDGE_HIGH - [11:11] - read-write - - - GPIO10_EDGE_LOW - [10:10] - read-write - - - GPIO10_LEVEL_HIGH - [9:9] - read-write - - - GPIO10_LEVEL_LOW - [8:8] - read-write - - - GPIO9_EDGE_HIGH - [7:7] - read-write - - - GPIO9_EDGE_LOW - [6:6] - read-write - - - GPIO9_LEVEL_HIGH - [5:5] - read-write - - - GPIO9_LEVEL_LOW - [4:4] - read-write - - - GPIO8_EDGE_HIGH - [3:3] - read-write - - - GPIO8_EDGE_LOW - [2:2] - read-write - - - GPIO8_LEVEL_HIGH - [1:1] - read-write - - - GPIO8_LEVEL_LOW - [0:0] - read-write - - - - - PROC0_INTF2 - 0x00000118 - Interrupt Force for proc0 - 0x00000000 - - - GPIO23_EDGE_HIGH - [31:31] - read-write - - - GPIO23_EDGE_LOW - [30:30] - read-write - - - GPIO23_LEVEL_HIGH - [29:29] - read-write - - - GPIO23_LEVEL_LOW - [28:28] - read-write - - - GPIO22_EDGE_HIGH - [27:27] - read-write - - - GPIO22_EDGE_LOW - [26:26] - read-write - - - GPIO22_LEVEL_HIGH - [25:25] - read-write - - - GPIO22_LEVEL_LOW - [24:24] - read-write - - - GPIO21_EDGE_HIGH - [23:23] - read-write - - - GPIO21_EDGE_LOW - [22:22] - read-write - - - GPIO21_LEVEL_HIGH - [21:21] - read-write - - - GPIO21_LEVEL_LOW - [20:20] - read-write - - - GPIO20_EDGE_HIGH - [19:19] - read-write - - - GPIO20_EDGE_LOW - [18:18] - read-write - - - GPIO20_LEVEL_HIGH - [17:17] - read-write - - - GPIO20_LEVEL_LOW - [16:16] - read-write - - - GPIO19_EDGE_HIGH - [15:15] - read-write - - - GPIO19_EDGE_LOW - [14:14] - read-write - - - GPIO19_LEVEL_HIGH - [13:13] - read-write - - - GPIO19_LEVEL_LOW - [12:12] - read-write - - - GPIO18_EDGE_HIGH - [11:11] - read-write - - - GPIO18_EDGE_LOW - [10:10] - read-write - - - GPIO18_LEVEL_HIGH - [9:9] - read-write - - - GPIO18_LEVEL_LOW - [8:8] - read-write - - - GPIO17_EDGE_HIGH - [7:7] - read-write - - - GPIO17_EDGE_LOW - [6:6] - read-write - - - GPIO17_LEVEL_HIGH - [5:5] - read-write - - - GPIO17_LEVEL_LOW - [4:4] - read-write - - - GPIO16_EDGE_HIGH - [3:3] - read-write - - - GPIO16_EDGE_LOW - [2:2] - read-write - - - GPIO16_LEVEL_HIGH - [1:1] - read-write - - - GPIO16_LEVEL_LOW - [0:0] - read-write - - - - - PROC0_INTF3 - 0x0000011c - Interrupt Force for proc0 - 0x00000000 - - - GPIO29_EDGE_HIGH - [23:23] - read-write - - - GPIO29_EDGE_LOW - [22:22] - read-write - - - GPIO29_LEVEL_HIGH - [21:21] - read-write - - - GPIO29_LEVEL_LOW - [20:20] - read-write - - - GPIO28_EDGE_HIGH - [19:19] - read-write - - - GPIO28_EDGE_LOW - [18:18] - read-write - - - GPIO28_LEVEL_HIGH - [17:17] - read-write - - - GPIO28_LEVEL_LOW - [16:16] - read-write - - - GPIO27_EDGE_HIGH - [15:15] - read-write - - - GPIO27_EDGE_LOW - [14:14] - read-write - - - GPIO27_LEVEL_HIGH - [13:13] - read-write - - - GPIO27_LEVEL_LOW - [12:12] - read-write - - - GPIO26_EDGE_HIGH - [11:11] - read-write - - - GPIO26_EDGE_LOW - [10:10] - read-write - - - GPIO26_LEVEL_HIGH - [9:9] - read-write - - - GPIO26_LEVEL_LOW - [8:8] - read-write - - - GPIO25_EDGE_HIGH - [7:7] - read-write - - - GPIO25_EDGE_LOW - [6:6] - read-write - - - GPIO25_LEVEL_HIGH - [5:5] - read-write - - - GPIO25_LEVEL_LOW - [4:4] - read-write - - - GPIO24_EDGE_HIGH - [3:3] - read-write - - - GPIO24_EDGE_LOW - [2:2] - read-write - - - GPIO24_LEVEL_HIGH - [1:1] - read-write - - - GPIO24_LEVEL_LOW - [0:0] - read-write - - - - - PROC0_INTS0 - 0x00000120 - Interrupt status after masking & forcing for proc0 - 0x00000000 - - - GPIO7_EDGE_HIGH - [31:31] - read-only - - - GPIO7_EDGE_LOW - [30:30] - read-only - - - GPIO7_LEVEL_HIGH - [29:29] - read-only - - - GPIO7_LEVEL_LOW - [28:28] - read-only - - - GPIO6_EDGE_HIGH - [27:27] - read-only - - - GPIO6_EDGE_LOW - [26:26] - read-only - - - GPIO6_LEVEL_HIGH - [25:25] - read-only - - - GPIO6_LEVEL_LOW - [24:24] - read-only - - - GPIO5_EDGE_HIGH - [23:23] - read-only - - - GPIO5_EDGE_LOW - [22:22] - read-only - - - GPIO5_LEVEL_HIGH - [21:21] - read-only - - - GPIO5_LEVEL_LOW - [20:20] - read-only - - - GPIO4_EDGE_HIGH - [19:19] - read-only - - - GPIO4_EDGE_LOW - [18:18] - read-only - - - GPIO4_LEVEL_HIGH - [17:17] - read-only - - - GPIO4_LEVEL_LOW - [16:16] - read-only - - - GPIO3_EDGE_HIGH - [15:15] - read-only - - - GPIO3_EDGE_LOW - [14:14] - read-only - - - GPIO3_LEVEL_HIGH - [13:13] - read-only - - - GPIO3_LEVEL_LOW - [12:12] - read-only - - - GPIO2_EDGE_HIGH - [11:11] - read-only - - - GPIO2_EDGE_LOW - [10:10] - read-only - - - GPIO2_LEVEL_HIGH - [9:9] - read-only - - - GPIO2_LEVEL_LOW - [8:8] - read-only - - - GPIO1_EDGE_HIGH - [7:7] - read-only - - - GPIO1_EDGE_LOW - [6:6] - read-only - - - GPIO1_LEVEL_HIGH - [5:5] - read-only - - - GPIO1_LEVEL_LOW - [4:4] - read-only - - - GPIO0_EDGE_HIGH - [3:3] - read-only - - - GPIO0_EDGE_LOW - [2:2] - read-only - - - GPIO0_LEVEL_HIGH - [1:1] - read-only - - - GPIO0_LEVEL_LOW - [0:0] - read-only - - - - - PROC0_INTS1 - 0x00000124 - Interrupt status after masking & forcing for proc0 - 0x00000000 - - - GPIO15_EDGE_HIGH - [31:31] - read-only - - - GPIO15_EDGE_LOW - [30:30] - read-only - - - GPIO15_LEVEL_HIGH - [29:29] - read-only - - - GPIO15_LEVEL_LOW - [28:28] - read-only - - - GPIO14_EDGE_HIGH - [27:27] - read-only - - - GPIO14_EDGE_LOW - [26:26] - read-only - - - GPIO14_LEVEL_HIGH - [25:25] - read-only - - - GPIO14_LEVEL_LOW - [24:24] - read-only - - - GPIO13_EDGE_HIGH - [23:23] - read-only - - - GPIO13_EDGE_LOW - [22:22] - read-only - - - GPIO13_LEVEL_HIGH - [21:21] - read-only - - - GPIO13_LEVEL_LOW - [20:20] - read-only - - - GPIO12_EDGE_HIGH - [19:19] - read-only - - - GPIO12_EDGE_LOW - [18:18] - read-only - - - GPIO12_LEVEL_HIGH - [17:17] - read-only - - - GPIO12_LEVEL_LOW - [16:16] - read-only - - - GPIO11_EDGE_HIGH - [15:15] - read-only - - - GPIO11_EDGE_LOW - [14:14] - read-only - - - GPIO11_LEVEL_HIGH - [13:13] - read-only - - - GPIO11_LEVEL_LOW - [12:12] - read-only - - - GPIO10_EDGE_HIGH - [11:11] - read-only - - - GPIO10_EDGE_LOW - [10:10] - read-only - - - GPIO10_LEVEL_HIGH - [9:9] - read-only - - - GPIO10_LEVEL_LOW - [8:8] - read-only - - - GPIO9_EDGE_HIGH - [7:7] - read-only - - - GPIO9_EDGE_LOW - [6:6] - read-only - - - GPIO9_LEVEL_HIGH - [5:5] - read-only - - - GPIO9_LEVEL_LOW - [4:4] - read-only - - - GPIO8_EDGE_HIGH - [3:3] - read-only - - - GPIO8_EDGE_LOW - [2:2] - read-only - - - GPIO8_LEVEL_HIGH - [1:1] - read-only - - - GPIO8_LEVEL_LOW - [0:0] - read-only - - - - - PROC0_INTS2 - 0x00000128 - Interrupt status after masking & forcing for proc0 - 0x00000000 - - - GPIO23_EDGE_HIGH - [31:31] - read-only - - - GPIO23_EDGE_LOW - [30:30] - read-only - - - GPIO23_LEVEL_HIGH - [29:29] - read-only - - - GPIO23_LEVEL_LOW - [28:28] - read-only - - - GPIO22_EDGE_HIGH - [27:27] - read-only - - - GPIO22_EDGE_LOW - [26:26] - read-only - - - GPIO22_LEVEL_HIGH - [25:25] - read-only - - - GPIO22_LEVEL_LOW - [24:24] - read-only - - - GPIO21_EDGE_HIGH - [23:23] - read-only - - - GPIO21_EDGE_LOW - [22:22] - read-only - - - GPIO21_LEVEL_HIGH - [21:21] - read-only - - - GPIO21_LEVEL_LOW - [20:20] - read-only - - - GPIO20_EDGE_HIGH - [19:19] - read-only - - - GPIO20_EDGE_LOW - [18:18] - read-only - - - GPIO20_LEVEL_HIGH - [17:17] - read-only - - - GPIO20_LEVEL_LOW - [16:16] - read-only - - - GPIO19_EDGE_HIGH - [15:15] - read-only - - - GPIO19_EDGE_LOW - [14:14] - read-only - - - GPIO19_LEVEL_HIGH - [13:13] - read-only - - - GPIO19_LEVEL_LOW - [12:12] - read-only - - - GPIO18_EDGE_HIGH - [11:11] - read-only - - - GPIO18_EDGE_LOW - [10:10] - read-only - - - GPIO18_LEVEL_HIGH - [9:9] - read-only - - - GPIO18_LEVEL_LOW - [8:8] - read-only - - - GPIO17_EDGE_HIGH - [7:7] - read-only - - - GPIO17_EDGE_LOW - [6:6] - read-only - - - GPIO17_LEVEL_HIGH - [5:5] - read-only - - - GPIO17_LEVEL_LOW - [4:4] - read-only - - - GPIO16_EDGE_HIGH - [3:3] - read-only - - - GPIO16_EDGE_LOW - [2:2] - read-only - - - GPIO16_LEVEL_HIGH - [1:1] - read-only - - - GPIO16_LEVEL_LOW - [0:0] - read-only - - - - - PROC0_INTS3 - 0x0000012c - Interrupt status after masking & forcing for proc0 - 0x00000000 - - - GPIO29_EDGE_HIGH - [23:23] - read-only - - - GPIO29_EDGE_LOW - [22:22] - read-only - - - GPIO29_LEVEL_HIGH - [21:21] - read-only - - - GPIO29_LEVEL_LOW - [20:20] - read-only - - - GPIO28_EDGE_HIGH - [19:19] - read-only - - - GPIO28_EDGE_LOW - [18:18] - read-only - - - GPIO28_LEVEL_HIGH - [17:17] - read-only - - - GPIO28_LEVEL_LOW - [16:16] - read-only - - - GPIO27_EDGE_HIGH - [15:15] - read-only - - - GPIO27_EDGE_LOW - [14:14] - read-only - - - GPIO27_LEVEL_HIGH - [13:13] - read-only - - - GPIO27_LEVEL_LOW - [12:12] - read-only - - - GPIO26_EDGE_HIGH - [11:11] - read-only - - - GPIO26_EDGE_LOW - [10:10] - read-only - - - GPIO26_LEVEL_HIGH - [9:9] - read-only - - - GPIO26_LEVEL_LOW - [8:8] - read-only - - - GPIO25_EDGE_HIGH - [7:7] - read-only - - - GPIO25_EDGE_LOW - [6:6] - read-only - - - GPIO25_LEVEL_HIGH - [5:5] - read-only - - - GPIO25_LEVEL_LOW - [4:4] - read-only - - - GPIO24_EDGE_HIGH - [3:3] - read-only - - - GPIO24_EDGE_LOW - [2:2] - read-only - - - GPIO24_LEVEL_HIGH - [1:1] - read-only - - - GPIO24_LEVEL_LOW - [0:0] - read-only - - - - - PROC1_INTE0 - 0x00000130 - Interrupt Enable for proc1 - 0x00000000 - - - GPIO7_EDGE_HIGH - [31:31] - read-write - - - GPIO7_EDGE_LOW - [30:30] - read-write - - - GPIO7_LEVEL_HIGH - [29:29] - read-write - - - GPIO7_LEVEL_LOW - [28:28] - read-write - - - GPIO6_EDGE_HIGH - [27:27] - read-write - - - GPIO6_EDGE_LOW - [26:26] - read-write - - - GPIO6_LEVEL_HIGH - [25:25] - read-write - - - GPIO6_LEVEL_LOW - [24:24] - read-write - - - GPIO5_EDGE_HIGH - [23:23] - read-write - - - GPIO5_EDGE_LOW - [22:22] - read-write - - - GPIO5_LEVEL_HIGH - [21:21] - read-write - - - GPIO5_LEVEL_LOW - [20:20] - read-write - - - GPIO4_EDGE_HIGH - [19:19] - read-write - - - GPIO4_EDGE_LOW - [18:18] - read-write - - - GPIO4_LEVEL_HIGH - [17:17] - read-write - - - GPIO4_LEVEL_LOW - [16:16] - read-write - - - GPIO3_EDGE_HIGH - [15:15] - read-write - - - GPIO3_EDGE_LOW - [14:14] - read-write - - - GPIO3_LEVEL_HIGH - [13:13] - read-write - - - GPIO3_LEVEL_LOW - [12:12] - read-write - - - GPIO2_EDGE_HIGH - [11:11] - read-write - - - GPIO2_EDGE_LOW - [10:10] - read-write - - - GPIO2_LEVEL_HIGH - [9:9] - read-write - - - GPIO2_LEVEL_LOW - [8:8] - read-write - - - GPIO1_EDGE_HIGH - [7:7] - read-write - - - GPIO1_EDGE_LOW - [6:6] - read-write - - - GPIO1_LEVEL_HIGH - [5:5] - read-write - - - GPIO1_LEVEL_LOW - [4:4] - read-write - - - GPIO0_EDGE_HIGH - [3:3] - read-write - - - GPIO0_EDGE_LOW - [2:2] - read-write - - - GPIO0_LEVEL_HIGH - [1:1] - read-write - - - GPIO0_LEVEL_LOW - [0:0] - read-write - - - - - PROC1_INTE1 - 0x00000134 - Interrupt Enable for proc1 - 0x00000000 - - - GPIO15_EDGE_HIGH - [31:31] - read-write - - - GPIO15_EDGE_LOW - [30:30] - read-write - - - GPIO15_LEVEL_HIGH - [29:29] - read-write - - - GPIO15_LEVEL_LOW - [28:28] - read-write - - - GPIO14_EDGE_HIGH - [27:27] - read-write - - - GPIO14_EDGE_LOW - [26:26] - read-write - - - GPIO14_LEVEL_HIGH - [25:25] - read-write - - - GPIO14_LEVEL_LOW - [24:24] - read-write - - - GPIO13_EDGE_HIGH - [23:23] - read-write - - - GPIO13_EDGE_LOW - [22:22] - read-write - - - GPIO13_LEVEL_HIGH - [21:21] - read-write - - - GPIO13_LEVEL_LOW - [20:20] - read-write - - - GPIO12_EDGE_HIGH - [19:19] - read-write - - - GPIO12_EDGE_LOW - [18:18] - read-write - - - GPIO12_LEVEL_HIGH - [17:17] - read-write - - - GPIO12_LEVEL_LOW - [16:16] - read-write - - - GPIO11_EDGE_HIGH - [15:15] - read-write - - - GPIO11_EDGE_LOW - [14:14] - read-write - - - GPIO11_LEVEL_HIGH - [13:13] - read-write - - - GPIO11_LEVEL_LOW - [12:12] - read-write - - - GPIO10_EDGE_HIGH - [11:11] - read-write - - - GPIO10_EDGE_LOW - [10:10] - read-write - - - GPIO10_LEVEL_HIGH - [9:9] - read-write - - - GPIO10_LEVEL_LOW - [8:8] - read-write - - - GPIO9_EDGE_HIGH - [7:7] - read-write - - - GPIO9_EDGE_LOW - [6:6] - read-write - - - GPIO9_LEVEL_HIGH - [5:5] - read-write - - - GPIO9_LEVEL_LOW - [4:4] - read-write - - - GPIO8_EDGE_HIGH - [3:3] - read-write - - - GPIO8_EDGE_LOW - [2:2] - read-write - - - GPIO8_LEVEL_HIGH - [1:1] - read-write - - - GPIO8_LEVEL_LOW - [0:0] - read-write - - - - - PROC1_INTE2 - 0x00000138 - Interrupt Enable for proc1 - 0x00000000 - - - GPIO23_EDGE_HIGH - [31:31] - read-write - - - GPIO23_EDGE_LOW - [30:30] - read-write - - - GPIO23_LEVEL_HIGH - [29:29] - read-write - - - GPIO23_LEVEL_LOW - [28:28] - read-write - - - GPIO22_EDGE_HIGH - [27:27] - read-write - - - GPIO22_EDGE_LOW - [26:26] - read-write - - - GPIO22_LEVEL_HIGH - [25:25] - read-write - - - GPIO22_LEVEL_LOW - [24:24] - read-write - - - GPIO21_EDGE_HIGH - [23:23] - read-write - - - GPIO21_EDGE_LOW - [22:22] - read-write - - - GPIO21_LEVEL_HIGH - [21:21] - read-write - - - GPIO21_LEVEL_LOW - [20:20] - read-write - - - GPIO20_EDGE_HIGH - [19:19] - read-write - - - GPIO20_EDGE_LOW - [18:18] - read-write - - - GPIO20_LEVEL_HIGH - [17:17] - read-write - - - GPIO20_LEVEL_LOW - [16:16] - read-write - - - GPIO19_EDGE_HIGH - [15:15] - read-write - - - GPIO19_EDGE_LOW - [14:14] - read-write - - - GPIO19_LEVEL_HIGH - [13:13] - read-write - - - GPIO19_LEVEL_LOW - [12:12] - read-write - - - GPIO18_EDGE_HIGH - [11:11] - read-write - - - GPIO18_EDGE_LOW - [10:10] - read-write - - - GPIO18_LEVEL_HIGH - [9:9] - read-write - - - GPIO18_LEVEL_LOW - [8:8] - read-write - - - GPIO17_EDGE_HIGH - [7:7] - read-write - - - GPIO17_EDGE_LOW - [6:6] - read-write - - - GPIO17_LEVEL_HIGH - [5:5] - read-write - - - GPIO17_LEVEL_LOW - [4:4] - read-write - - - GPIO16_EDGE_HIGH - [3:3] - read-write - - - GPIO16_EDGE_LOW - [2:2] - read-write - - - GPIO16_LEVEL_HIGH - [1:1] - read-write - - - GPIO16_LEVEL_LOW - [0:0] - read-write - - - - - PROC1_INTE3 - 0x0000013c - Interrupt Enable for proc1 - 0x00000000 - - - GPIO29_EDGE_HIGH - [23:23] - read-write - - - GPIO29_EDGE_LOW - [22:22] - read-write - - - GPIO29_LEVEL_HIGH - [21:21] - read-write - - - GPIO29_LEVEL_LOW - [20:20] - read-write - - - GPIO28_EDGE_HIGH - [19:19] - read-write - - - GPIO28_EDGE_LOW - [18:18] - read-write - - - GPIO28_LEVEL_HIGH - [17:17] - read-write - - - GPIO28_LEVEL_LOW - [16:16] - read-write - - - GPIO27_EDGE_HIGH - [15:15] - read-write - - - GPIO27_EDGE_LOW - [14:14] - read-write - - - GPIO27_LEVEL_HIGH - [13:13] - read-write - - - GPIO27_LEVEL_LOW - [12:12] - read-write - - - GPIO26_EDGE_HIGH - [11:11] - read-write - - - GPIO26_EDGE_LOW - [10:10] - read-write - - - GPIO26_LEVEL_HIGH - [9:9] - read-write - - - GPIO26_LEVEL_LOW - [8:8] - read-write - - - GPIO25_EDGE_HIGH - [7:7] - read-write - - - GPIO25_EDGE_LOW - [6:6] - read-write - - - GPIO25_LEVEL_HIGH - [5:5] - read-write - - - GPIO25_LEVEL_LOW - [4:4] - read-write - - - GPIO24_EDGE_HIGH - [3:3] - read-write - - - GPIO24_EDGE_LOW - [2:2] - read-write - - - GPIO24_LEVEL_HIGH - [1:1] - read-write - - - GPIO24_LEVEL_LOW - [0:0] - read-write - - - - - PROC1_INTF0 - 0x00000140 - Interrupt Force for proc1 - 0x00000000 - - - GPIO7_EDGE_HIGH - [31:31] - read-write - - - GPIO7_EDGE_LOW - [30:30] - read-write - - - GPIO7_LEVEL_HIGH - [29:29] - read-write - - - GPIO7_LEVEL_LOW - [28:28] - read-write - - - GPIO6_EDGE_HIGH - [27:27] - read-write - - - GPIO6_EDGE_LOW - [26:26] - read-write - - - GPIO6_LEVEL_HIGH - [25:25] - read-write - - - GPIO6_LEVEL_LOW - [24:24] - read-write - - - GPIO5_EDGE_HIGH - [23:23] - read-write - - - GPIO5_EDGE_LOW - [22:22] - read-write - - - GPIO5_LEVEL_HIGH - [21:21] - read-write - - - GPIO5_LEVEL_LOW - [20:20] - read-write - - - GPIO4_EDGE_HIGH - [19:19] - read-write - - - GPIO4_EDGE_LOW - [18:18] - read-write - - - GPIO4_LEVEL_HIGH - [17:17] - read-write - - - GPIO4_LEVEL_LOW - [16:16] - read-write - - - GPIO3_EDGE_HIGH - [15:15] - read-write - - - GPIO3_EDGE_LOW - [14:14] - read-write - - - GPIO3_LEVEL_HIGH - [13:13] - read-write - - - GPIO3_LEVEL_LOW - [12:12] - read-write - - - GPIO2_EDGE_HIGH - [11:11] - read-write - - - GPIO2_EDGE_LOW - [10:10] - read-write - - - GPIO2_LEVEL_HIGH - [9:9] - read-write - - - GPIO2_LEVEL_LOW - [8:8] - read-write - - - GPIO1_EDGE_HIGH - [7:7] - read-write - - - GPIO1_EDGE_LOW - [6:6] - read-write - - - GPIO1_LEVEL_HIGH - [5:5] - read-write - - - GPIO1_LEVEL_LOW - [4:4] - read-write - - - GPIO0_EDGE_HIGH - [3:3] - read-write - - - GPIO0_EDGE_LOW - [2:2] - read-write - - - GPIO0_LEVEL_HIGH - [1:1] - read-write - - - GPIO0_LEVEL_LOW - [0:0] - read-write - - - - - PROC1_INTF1 - 0x00000144 - Interrupt Force for proc1 - 0x00000000 - - - GPIO15_EDGE_HIGH - [31:31] - read-write - - - GPIO15_EDGE_LOW - [30:30] - read-write - - - GPIO15_LEVEL_HIGH - [29:29] - read-write - - - GPIO15_LEVEL_LOW - [28:28] - read-write - - - GPIO14_EDGE_HIGH - [27:27] - read-write - - - GPIO14_EDGE_LOW - [26:26] - read-write - - - GPIO14_LEVEL_HIGH - [25:25] - read-write - - - GPIO14_LEVEL_LOW - [24:24] - read-write - - - GPIO13_EDGE_HIGH - [23:23] - read-write - - - GPIO13_EDGE_LOW - [22:22] - read-write - - - GPIO13_LEVEL_HIGH - [21:21] - read-write - - - GPIO13_LEVEL_LOW - [20:20] - read-write - - - GPIO12_EDGE_HIGH - [19:19] - read-write - - - GPIO12_EDGE_LOW - [18:18] - read-write - - - GPIO12_LEVEL_HIGH - [17:17] - read-write - - - GPIO12_LEVEL_LOW - [16:16] - read-write - - - GPIO11_EDGE_HIGH - [15:15] - read-write - - - GPIO11_EDGE_LOW - [14:14] - read-write - - - GPIO11_LEVEL_HIGH - [13:13] - read-write - - - GPIO11_LEVEL_LOW - [12:12] - read-write - - - GPIO10_EDGE_HIGH - [11:11] - read-write - - - GPIO10_EDGE_LOW - [10:10] - read-write - - - GPIO10_LEVEL_HIGH - [9:9] - read-write - - - GPIO10_LEVEL_LOW - [8:8] - read-write - - - GPIO9_EDGE_HIGH - [7:7] - read-write - - - GPIO9_EDGE_LOW - [6:6] - read-write - - - GPIO9_LEVEL_HIGH - [5:5] - read-write - - - GPIO9_LEVEL_LOW - [4:4] - read-write - - - GPIO8_EDGE_HIGH - [3:3] - read-write - - - GPIO8_EDGE_LOW - [2:2] - read-write - - - GPIO8_LEVEL_HIGH - [1:1] - read-write - - - GPIO8_LEVEL_LOW - [0:0] - read-write - - - - - PROC1_INTF2 - 0x00000148 - Interrupt Force for proc1 - 0x00000000 - - - GPIO23_EDGE_HIGH - [31:31] - read-write - - - GPIO23_EDGE_LOW - [30:30] - read-write - - - GPIO23_LEVEL_HIGH - [29:29] - read-write - - - GPIO23_LEVEL_LOW - [28:28] - read-write - - - GPIO22_EDGE_HIGH - [27:27] - read-write - - - GPIO22_EDGE_LOW - [26:26] - read-write - - - GPIO22_LEVEL_HIGH - [25:25] - read-write - - - GPIO22_LEVEL_LOW - [24:24] - read-write - - - GPIO21_EDGE_HIGH - [23:23] - read-write - - - GPIO21_EDGE_LOW - [22:22] - read-write - - - GPIO21_LEVEL_HIGH - [21:21] - read-write - - - GPIO21_LEVEL_LOW - [20:20] - read-write - - - GPIO20_EDGE_HIGH - [19:19] - read-write - - - GPIO20_EDGE_LOW - [18:18] - read-write - - - GPIO20_LEVEL_HIGH - [17:17] - read-write - - - GPIO20_LEVEL_LOW - [16:16] - read-write - - - GPIO19_EDGE_HIGH - [15:15] - read-write - - - GPIO19_EDGE_LOW - [14:14] - read-write - - - GPIO19_LEVEL_HIGH - [13:13] - read-write - - - GPIO19_LEVEL_LOW - [12:12] - read-write - - - GPIO18_EDGE_HIGH - [11:11] - read-write - - - GPIO18_EDGE_LOW - [10:10] - read-write - - - GPIO18_LEVEL_HIGH - [9:9] - read-write - - - GPIO18_LEVEL_LOW - [8:8] - read-write - - - GPIO17_EDGE_HIGH - [7:7] - read-write - - - GPIO17_EDGE_LOW - [6:6] - read-write - - - GPIO17_LEVEL_HIGH - [5:5] - read-write - - - GPIO17_LEVEL_LOW - [4:4] - read-write - - - GPIO16_EDGE_HIGH - [3:3] - read-write - - - GPIO16_EDGE_LOW - [2:2] - read-write - - - GPIO16_LEVEL_HIGH - [1:1] - read-write - - - GPIO16_LEVEL_LOW - [0:0] - read-write - - - - - PROC1_INTF3 - 0x0000014c - Interrupt Force for proc1 - 0x00000000 - - - GPIO29_EDGE_HIGH - [23:23] - read-write - - - GPIO29_EDGE_LOW - [22:22] - read-write - - - GPIO29_LEVEL_HIGH - [21:21] - read-write - - - GPIO29_LEVEL_LOW - [20:20] - read-write - - - GPIO28_EDGE_HIGH - [19:19] - read-write - - - GPIO28_EDGE_LOW - [18:18] - read-write - - - GPIO28_LEVEL_HIGH - [17:17] - read-write - - - GPIO28_LEVEL_LOW - [16:16] - read-write - - - GPIO27_EDGE_HIGH - [15:15] - read-write - - - GPIO27_EDGE_LOW - [14:14] - read-write - - - GPIO27_LEVEL_HIGH - [13:13] - read-write - - - GPIO27_LEVEL_LOW - [12:12] - read-write - - - GPIO26_EDGE_HIGH - [11:11] - read-write - - - GPIO26_EDGE_LOW - [10:10] - read-write - - - GPIO26_LEVEL_HIGH - [9:9] - read-write - - - GPIO26_LEVEL_LOW - [8:8] - read-write - - - GPIO25_EDGE_HIGH - [7:7] - read-write - - - GPIO25_EDGE_LOW - [6:6] - read-write - - - GPIO25_LEVEL_HIGH - [5:5] - read-write - - - GPIO25_LEVEL_LOW - [4:4] - read-write - - - GPIO24_EDGE_HIGH - [3:3] - read-write - - - GPIO24_EDGE_LOW - [2:2] - read-write - - - GPIO24_LEVEL_HIGH - [1:1] - read-write - - - GPIO24_LEVEL_LOW - [0:0] - read-write - - - - - PROC1_INTS0 - 0x00000150 - Interrupt status after masking & forcing for proc1 - 0x00000000 - - - GPIO7_EDGE_HIGH - [31:31] - read-only - - - GPIO7_EDGE_LOW - [30:30] - read-only - - - GPIO7_LEVEL_HIGH - [29:29] - read-only - - - GPIO7_LEVEL_LOW - [28:28] - read-only - - - GPIO6_EDGE_HIGH - [27:27] - read-only - - - GPIO6_EDGE_LOW - [26:26] - read-only - - - GPIO6_LEVEL_HIGH - [25:25] - read-only - - - GPIO6_LEVEL_LOW - [24:24] - read-only - - - GPIO5_EDGE_HIGH - [23:23] - read-only - - - GPIO5_EDGE_LOW - [22:22] - read-only - - - GPIO5_LEVEL_HIGH - [21:21] - read-only - - - GPIO5_LEVEL_LOW - [20:20] - read-only - - - GPIO4_EDGE_HIGH - [19:19] - read-only - - - GPIO4_EDGE_LOW - [18:18] - read-only - - - GPIO4_LEVEL_HIGH - [17:17] - read-only - - - GPIO4_LEVEL_LOW - [16:16] - read-only - - - GPIO3_EDGE_HIGH - [15:15] - read-only - - - GPIO3_EDGE_LOW - [14:14] - read-only - - - GPIO3_LEVEL_HIGH - [13:13] - read-only - - - GPIO3_LEVEL_LOW - [12:12] - read-only - - - GPIO2_EDGE_HIGH - [11:11] - read-only - - - GPIO2_EDGE_LOW - [10:10] - read-only - - - GPIO2_LEVEL_HIGH - [9:9] - read-only - - - GPIO2_LEVEL_LOW - [8:8] - read-only - - - GPIO1_EDGE_HIGH - [7:7] - read-only - - - GPIO1_EDGE_LOW - [6:6] - read-only - - - GPIO1_LEVEL_HIGH - [5:5] - read-only - - - GPIO1_LEVEL_LOW - [4:4] - read-only - - - GPIO0_EDGE_HIGH - [3:3] - read-only - - - GPIO0_EDGE_LOW - [2:2] - read-only - - - GPIO0_LEVEL_HIGH - [1:1] - read-only - - - GPIO0_LEVEL_LOW - [0:0] - read-only - - - - - PROC1_INTS1 - 0x00000154 - Interrupt status after masking & forcing for proc1 - 0x00000000 - - - GPIO15_EDGE_HIGH - [31:31] - read-only - - - GPIO15_EDGE_LOW - [30:30] - read-only - - - GPIO15_LEVEL_HIGH - [29:29] - read-only - - - GPIO15_LEVEL_LOW - [28:28] - read-only - - - GPIO14_EDGE_HIGH - [27:27] - read-only - - - GPIO14_EDGE_LOW - [26:26] - read-only - - - GPIO14_LEVEL_HIGH - [25:25] - read-only - - - GPIO14_LEVEL_LOW - [24:24] - read-only - - - GPIO13_EDGE_HIGH - [23:23] - read-only - - - GPIO13_EDGE_LOW - [22:22] - read-only - - - GPIO13_LEVEL_HIGH - [21:21] - read-only - - - GPIO13_LEVEL_LOW - [20:20] - read-only - - - GPIO12_EDGE_HIGH - [19:19] - read-only - - - GPIO12_EDGE_LOW - [18:18] - read-only - - - GPIO12_LEVEL_HIGH - [17:17] - read-only - - - GPIO12_LEVEL_LOW - [16:16] - read-only - - - GPIO11_EDGE_HIGH - [15:15] - read-only - - - GPIO11_EDGE_LOW - [14:14] - read-only - - - GPIO11_LEVEL_HIGH - [13:13] - read-only - - - GPIO11_LEVEL_LOW - [12:12] - read-only - - - GPIO10_EDGE_HIGH - [11:11] - read-only - - - GPIO10_EDGE_LOW - [10:10] - read-only - - - GPIO10_LEVEL_HIGH - [9:9] - read-only - - - GPIO10_LEVEL_LOW - [8:8] - read-only - - - GPIO9_EDGE_HIGH - [7:7] - read-only - - - GPIO9_EDGE_LOW - [6:6] - read-only - - - GPIO9_LEVEL_HIGH - [5:5] - read-only - - - GPIO9_LEVEL_LOW - [4:4] - read-only - - - GPIO8_EDGE_HIGH - [3:3] - read-only - - - GPIO8_EDGE_LOW - [2:2] - read-only - - - GPIO8_LEVEL_HIGH - [1:1] - read-only - - - GPIO8_LEVEL_LOW - [0:0] - read-only - - - - - PROC1_INTS2 - 0x00000158 - Interrupt status after masking & forcing for proc1 - 0x00000000 - - - GPIO23_EDGE_HIGH - [31:31] - read-only - - - GPIO23_EDGE_LOW - [30:30] - read-only - - - GPIO23_LEVEL_HIGH - [29:29] - read-only - - - GPIO23_LEVEL_LOW - [28:28] - read-only - - - GPIO22_EDGE_HIGH - [27:27] - read-only - - - GPIO22_EDGE_LOW - [26:26] - read-only - - - GPIO22_LEVEL_HIGH - [25:25] - read-only - - - GPIO22_LEVEL_LOW - [24:24] - read-only - - - GPIO21_EDGE_HIGH - [23:23] - read-only - - - GPIO21_EDGE_LOW - [22:22] - read-only - - - GPIO21_LEVEL_HIGH - [21:21] - read-only - - - GPIO21_LEVEL_LOW - [20:20] - read-only - - - GPIO20_EDGE_HIGH - [19:19] - read-only - - - GPIO20_EDGE_LOW - [18:18] - read-only - - - GPIO20_LEVEL_HIGH - [17:17] - read-only - - - GPIO20_LEVEL_LOW - [16:16] - read-only - - - GPIO19_EDGE_HIGH - [15:15] - read-only - - - GPIO19_EDGE_LOW - [14:14] - read-only - - - GPIO19_LEVEL_HIGH - [13:13] - read-only - - - GPIO19_LEVEL_LOW - [12:12] - read-only - - - GPIO18_EDGE_HIGH - [11:11] - read-only - - - GPIO18_EDGE_LOW - [10:10] - read-only - - - GPIO18_LEVEL_HIGH - [9:9] - read-only - - - GPIO18_LEVEL_LOW - [8:8] - read-only - - - GPIO17_EDGE_HIGH - [7:7] - read-only - - - GPIO17_EDGE_LOW - [6:6] - read-only - - - GPIO17_LEVEL_HIGH - [5:5] - read-only - - - GPIO17_LEVEL_LOW - [4:4] - read-only - - - GPIO16_EDGE_HIGH - [3:3] - read-only - - - GPIO16_EDGE_LOW - [2:2] - read-only - - - GPIO16_LEVEL_HIGH - [1:1] - read-only - - - GPIO16_LEVEL_LOW - [0:0] - read-only - - - - - PROC1_INTS3 - 0x0000015c - Interrupt status after masking & forcing for proc1 - 0x00000000 - - - GPIO29_EDGE_HIGH - [23:23] - read-only - - - GPIO29_EDGE_LOW - [22:22] - read-only - - - GPIO29_LEVEL_HIGH - [21:21] - read-only - - - GPIO29_LEVEL_LOW - [20:20] - read-only - - - GPIO28_EDGE_HIGH - [19:19] - read-only - - - GPIO28_EDGE_LOW - [18:18] - read-only - - - GPIO28_LEVEL_HIGH - [17:17] - read-only - - - GPIO28_LEVEL_LOW - [16:16] - read-only - - - GPIO27_EDGE_HIGH - [15:15] - read-only - - - GPIO27_EDGE_LOW - [14:14] - read-only - - - GPIO27_LEVEL_HIGH - [13:13] - read-only - - - GPIO27_LEVEL_LOW - [12:12] - read-only - - - GPIO26_EDGE_HIGH - [11:11] - read-only - - - GPIO26_EDGE_LOW - [10:10] - read-only - - - GPIO26_LEVEL_HIGH - [9:9] - read-only - - - GPIO26_LEVEL_LOW - [8:8] - read-only - - - GPIO25_EDGE_HIGH - [7:7] - read-only - - - GPIO25_EDGE_LOW - [6:6] - read-only - - - GPIO25_LEVEL_HIGH - [5:5] - read-only - - - GPIO25_LEVEL_LOW - [4:4] - read-only - - - GPIO24_EDGE_HIGH - [3:3] - read-only - - - GPIO24_EDGE_LOW - [2:2] - read-only - - - GPIO24_LEVEL_HIGH - [1:1] - read-only - - - GPIO24_LEVEL_LOW - [0:0] - read-only - - - - - DORMANT_WAKE_INTE0 - 0x00000160 - Interrupt Enable for dormant_wake - 0x00000000 - - - GPIO7_EDGE_HIGH - [31:31] - read-write - - - GPIO7_EDGE_LOW - [30:30] - read-write - - - GPIO7_LEVEL_HIGH - [29:29] - read-write - - - GPIO7_LEVEL_LOW - [28:28] - read-write - - - GPIO6_EDGE_HIGH - [27:27] - read-write - - - GPIO6_EDGE_LOW - [26:26] - read-write - - - GPIO6_LEVEL_HIGH - [25:25] - read-write - - - GPIO6_LEVEL_LOW - [24:24] - read-write - - - GPIO5_EDGE_HIGH - [23:23] - read-write - - - GPIO5_EDGE_LOW - [22:22] - read-write - - - GPIO5_LEVEL_HIGH - [21:21] - read-write - - - GPIO5_LEVEL_LOW - [20:20] - read-write - - - GPIO4_EDGE_HIGH - [19:19] - read-write - - - GPIO4_EDGE_LOW - [18:18] - read-write - - - GPIO4_LEVEL_HIGH - [17:17] - read-write - - - GPIO4_LEVEL_LOW - [16:16] - read-write - - - GPIO3_EDGE_HIGH - [15:15] - read-write - - - GPIO3_EDGE_LOW - [14:14] - read-write - - - GPIO3_LEVEL_HIGH - [13:13] - read-write - - - GPIO3_LEVEL_LOW - [12:12] - read-write - - - GPIO2_EDGE_HIGH - [11:11] - read-write - - - GPIO2_EDGE_LOW - [10:10] - read-write - - - GPIO2_LEVEL_HIGH - [9:9] - read-write - - - GPIO2_LEVEL_LOW - [8:8] - read-write - - - GPIO1_EDGE_HIGH - [7:7] - read-write - - - GPIO1_EDGE_LOW - [6:6] - read-write - - - GPIO1_LEVEL_HIGH - [5:5] - read-write - - - GPIO1_LEVEL_LOW - [4:4] - read-write - - - GPIO0_EDGE_HIGH - [3:3] - read-write - - - GPIO0_EDGE_LOW - [2:2] - read-write - - - GPIO0_LEVEL_HIGH - [1:1] - read-write - - - GPIO0_LEVEL_LOW - [0:0] - read-write - - - - - DORMANT_WAKE_INTE1 - 0x00000164 - Interrupt Enable for dormant_wake - 0x00000000 - - - GPIO15_EDGE_HIGH - [31:31] - read-write - - - GPIO15_EDGE_LOW - [30:30] - read-write - - - GPIO15_LEVEL_HIGH - [29:29] - read-write - - - GPIO15_LEVEL_LOW - [28:28] - read-write - - - GPIO14_EDGE_HIGH - [27:27] - read-write - - - GPIO14_EDGE_LOW - [26:26] - read-write - - - GPIO14_LEVEL_HIGH - [25:25] - read-write - - - GPIO14_LEVEL_LOW - [24:24] - read-write - - - GPIO13_EDGE_HIGH - [23:23] - read-write - - - GPIO13_EDGE_LOW - [22:22] - read-write - - - GPIO13_LEVEL_HIGH - [21:21] - read-write - - - GPIO13_LEVEL_LOW - [20:20] - read-write - - - GPIO12_EDGE_HIGH - [19:19] - read-write - - - GPIO12_EDGE_LOW - [18:18] - read-write - - - GPIO12_LEVEL_HIGH - [17:17] - read-write - - - GPIO12_LEVEL_LOW - [16:16] - read-write - - - GPIO11_EDGE_HIGH - [15:15] - read-write - - - GPIO11_EDGE_LOW - [14:14] - read-write - - - GPIO11_LEVEL_HIGH - [13:13] - read-write - - - GPIO11_LEVEL_LOW - [12:12] - read-write - - - GPIO10_EDGE_HIGH - [11:11] - read-write - - - GPIO10_EDGE_LOW - [10:10] - read-write - - - GPIO10_LEVEL_HIGH - [9:9] - read-write - - - GPIO10_LEVEL_LOW - [8:8] - read-write - - - GPIO9_EDGE_HIGH - [7:7] - read-write - - - GPIO9_EDGE_LOW - [6:6] - read-write - - - GPIO9_LEVEL_HIGH - [5:5] - read-write - - - GPIO9_LEVEL_LOW - [4:4] - read-write - - - GPIO8_EDGE_HIGH - [3:3] - read-write - - - GPIO8_EDGE_LOW - [2:2] - read-write - - - GPIO8_LEVEL_HIGH - [1:1] - read-write - - - GPIO8_LEVEL_LOW - [0:0] - read-write - - - - - DORMANT_WAKE_INTE2 - 0x00000168 - Interrupt Enable for dormant_wake - 0x00000000 - - - GPIO23_EDGE_HIGH - [31:31] - read-write - - - GPIO23_EDGE_LOW - [30:30] - read-write - - - GPIO23_LEVEL_HIGH - [29:29] - read-write - - - GPIO23_LEVEL_LOW - [28:28] - read-write - - - GPIO22_EDGE_HIGH - [27:27] - read-write - - - GPIO22_EDGE_LOW - [26:26] - read-write - - - GPIO22_LEVEL_HIGH - [25:25] - read-write - - - GPIO22_LEVEL_LOW - [24:24] - read-write - - - GPIO21_EDGE_HIGH - [23:23] - read-write - - - GPIO21_EDGE_LOW - [22:22] - read-write - - - GPIO21_LEVEL_HIGH - [21:21] - read-write - - - GPIO21_LEVEL_LOW - [20:20] - read-write - - - GPIO20_EDGE_HIGH - [19:19] - read-write - - - GPIO20_EDGE_LOW - [18:18] - read-write - - - GPIO20_LEVEL_HIGH - [17:17] - read-write - - - GPIO20_LEVEL_LOW - [16:16] - read-write - - - GPIO19_EDGE_HIGH - [15:15] - read-write - - - GPIO19_EDGE_LOW - [14:14] - read-write - - - GPIO19_LEVEL_HIGH - [13:13] - read-write - - - GPIO19_LEVEL_LOW - [12:12] - read-write - - - GPIO18_EDGE_HIGH - [11:11] - read-write - - - GPIO18_EDGE_LOW - [10:10] - read-write - - - GPIO18_LEVEL_HIGH - [9:9] - read-write - - - GPIO18_LEVEL_LOW - [8:8] - read-write - - - GPIO17_EDGE_HIGH - [7:7] - read-write - - - GPIO17_EDGE_LOW - [6:6] - read-write - - - GPIO17_LEVEL_HIGH - [5:5] - read-write - - - GPIO17_LEVEL_LOW - [4:4] - read-write - - - GPIO16_EDGE_HIGH - [3:3] - read-write - - - GPIO16_EDGE_LOW - [2:2] - read-write - - - GPIO16_LEVEL_HIGH - [1:1] - read-write - - - GPIO16_LEVEL_LOW - [0:0] - read-write - - - - - DORMANT_WAKE_INTE3 - 0x0000016c - Interrupt Enable for dormant_wake - 0x00000000 - - - GPIO29_EDGE_HIGH - [23:23] - read-write - - - GPIO29_EDGE_LOW - [22:22] - read-write - - - GPIO29_LEVEL_HIGH - [21:21] - read-write - - - GPIO29_LEVEL_LOW - [20:20] - read-write - - - GPIO28_EDGE_HIGH - [19:19] - read-write - - - GPIO28_EDGE_LOW - [18:18] - read-write - - - GPIO28_LEVEL_HIGH - [17:17] - read-write - - - GPIO28_LEVEL_LOW - [16:16] - read-write - - - GPIO27_EDGE_HIGH - [15:15] - read-write - - - GPIO27_EDGE_LOW - [14:14] - read-write - - - GPIO27_LEVEL_HIGH - [13:13] - read-write - - - GPIO27_LEVEL_LOW - [12:12] - read-write - - - GPIO26_EDGE_HIGH - [11:11] - read-write - - - GPIO26_EDGE_LOW - [10:10] - read-write - - - GPIO26_LEVEL_HIGH - [9:9] - read-write - - - GPIO26_LEVEL_LOW - [8:8] - read-write - - - GPIO25_EDGE_HIGH - [7:7] - read-write - - - GPIO25_EDGE_LOW - [6:6] - read-write - - - GPIO25_LEVEL_HIGH - [5:5] - read-write - - - GPIO25_LEVEL_LOW - [4:4] - read-write - - - GPIO24_EDGE_HIGH - [3:3] - read-write - - - GPIO24_EDGE_LOW - [2:2] - read-write - - - GPIO24_LEVEL_HIGH - [1:1] - read-write - - - GPIO24_LEVEL_LOW - [0:0] - read-write - - - - - DORMANT_WAKE_INTF0 - 0x00000170 - Interrupt Force for dormant_wake - 0x00000000 - - - GPIO7_EDGE_HIGH - [31:31] - read-write - - - GPIO7_EDGE_LOW - [30:30] - read-write - - - GPIO7_LEVEL_HIGH - [29:29] - read-write - - - GPIO7_LEVEL_LOW - [28:28] - read-write - - - GPIO6_EDGE_HIGH - [27:27] - read-write - - - GPIO6_EDGE_LOW - [26:26] - read-write - - - GPIO6_LEVEL_HIGH - [25:25] - read-write - - - GPIO6_LEVEL_LOW - [24:24] - read-write - - - GPIO5_EDGE_HIGH - [23:23] - read-write - - - GPIO5_EDGE_LOW - [22:22] - read-write - - - GPIO5_LEVEL_HIGH - [21:21] - read-write - - - GPIO5_LEVEL_LOW - [20:20] - read-write - - - GPIO4_EDGE_HIGH - [19:19] - read-write - - - GPIO4_EDGE_LOW - [18:18] - read-write - - - GPIO4_LEVEL_HIGH - [17:17] - read-write - - - GPIO4_LEVEL_LOW - [16:16] - read-write - - - GPIO3_EDGE_HIGH - [15:15] - read-write - - - GPIO3_EDGE_LOW - [14:14] - read-write - - - GPIO3_LEVEL_HIGH - [13:13] - read-write - - - GPIO3_LEVEL_LOW - [12:12] - read-write - - - GPIO2_EDGE_HIGH - [11:11] - read-write - - - GPIO2_EDGE_LOW - [10:10] - read-write - - - GPIO2_LEVEL_HIGH - [9:9] - read-write - - - GPIO2_LEVEL_LOW - [8:8] - read-write - - - GPIO1_EDGE_HIGH - [7:7] - read-write - - - GPIO1_EDGE_LOW - [6:6] - read-write - - - GPIO1_LEVEL_HIGH - [5:5] - read-write - - - GPIO1_LEVEL_LOW - [4:4] - read-write - - - GPIO0_EDGE_HIGH - [3:3] - read-write - - - GPIO0_EDGE_LOW - [2:2] - read-write - - - GPIO0_LEVEL_HIGH - [1:1] - read-write - - - GPIO0_LEVEL_LOW - [0:0] - read-write - - - - - DORMANT_WAKE_INTF1 - 0x00000174 - Interrupt Force for dormant_wake - 0x00000000 - - - GPIO15_EDGE_HIGH - [31:31] - read-write - - - GPIO15_EDGE_LOW - [30:30] - read-write - - - GPIO15_LEVEL_HIGH - [29:29] - read-write - - - GPIO15_LEVEL_LOW - [28:28] - read-write - - - GPIO14_EDGE_HIGH - [27:27] - read-write - - - GPIO14_EDGE_LOW - [26:26] - read-write - - - GPIO14_LEVEL_HIGH - [25:25] - read-write - - - GPIO14_LEVEL_LOW - [24:24] - read-write - - - GPIO13_EDGE_HIGH - [23:23] - read-write - - - GPIO13_EDGE_LOW - [22:22] - read-write - - - GPIO13_LEVEL_HIGH - [21:21] - read-write - - - GPIO13_LEVEL_LOW - [20:20] - read-write - - - GPIO12_EDGE_HIGH - [19:19] - read-write - - - GPIO12_EDGE_LOW - [18:18] - read-write - - - GPIO12_LEVEL_HIGH - [17:17] - read-write - - - GPIO12_LEVEL_LOW - [16:16] - read-write - - - GPIO11_EDGE_HIGH - [15:15] - read-write - - - GPIO11_EDGE_LOW - [14:14] - read-write - - - GPIO11_LEVEL_HIGH - [13:13] - read-write - - - GPIO11_LEVEL_LOW - [12:12] - read-write - - - GPIO10_EDGE_HIGH - [11:11] - read-write - - - GPIO10_EDGE_LOW - [10:10] - read-write - - - GPIO10_LEVEL_HIGH - [9:9] - read-write - - - GPIO10_LEVEL_LOW - [8:8] - read-write - - - GPIO9_EDGE_HIGH - [7:7] - read-write - - - GPIO9_EDGE_LOW - [6:6] - read-write - - - GPIO9_LEVEL_HIGH - [5:5] - read-write - - - GPIO9_LEVEL_LOW - [4:4] - read-write - - - GPIO8_EDGE_HIGH - [3:3] - read-write - - - GPIO8_EDGE_LOW - [2:2] - read-write - - - GPIO8_LEVEL_HIGH - [1:1] - read-write - - - GPIO8_LEVEL_LOW - [0:0] - read-write - - - - - DORMANT_WAKE_INTF2 - 0x00000178 - Interrupt Force for dormant_wake - 0x00000000 - - - GPIO23_EDGE_HIGH - [31:31] - read-write - - - GPIO23_EDGE_LOW - [30:30] - read-write - - - GPIO23_LEVEL_HIGH - [29:29] - read-write - - - GPIO23_LEVEL_LOW - [28:28] - read-write - - - GPIO22_EDGE_HIGH - [27:27] - read-write - - - GPIO22_EDGE_LOW - [26:26] - read-write - - - GPIO22_LEVEL_HIGH - [25:25] - read-write - - - GPIO22_LEVEL_LOW - [24:24] - read-write - - - GPIO21_EDGE_HIGH - [23:23] - read-write - - - GPIO21_EDGE_LOW - [22:22] - read-write - - - GPIO21_LEVEL_HIGH - [21:21] - read-write - - - GPIO21_LEVEL_LOW - [20:20] - read-write - - - GPIO20_EDGE_HIGH - [19:19] - read-write - - - GPIO20_EDGE_LOW - [18:18] - read-write - - - GPIO20_LEVEL_HIGH - [17:17] - read-write - - - GPIO20_LEVEL_LOW - [16:16] - read-write - - - GPIO19_EDGE_HIGH - [15:15] - read-write - - - GPIO19_EDGE_LOW - [14:14] - read-write - - - GPIO19_LEVEL_HIGH - [13:13] - read-write - - - GPIO19_LEVEL_LOW - [12:12] - read-write - - - GPIO18_EDGE_HIGH - [11:11] - read-write - - - GPIO18_EDGE_LOW - [10:10] - read-write - - - GPIO18_LEVEL_HIGH - [9:9] - read-write - - - GPIO18_LEVEL_LOW - [8:8] - read-write - - - GPIO17_EDGE_HIGH - [7:7] - read-write - - - GPIO17_EDGE_LOW - [6:6] - read-write - - - GPIO17_LEVEL_HIGH - [5:5] - read-write - - - GPIO17_LEVEL_LOW - [4:4] - read-write - - - GPIO16_EDGE_HIGH - [3:3] - read-write - - - GPIO16_EDGE_LOW - [2:2] - read-write - - - GPIO16_LEVEL_HIGH - [1:1] - read-write - - - GPIO16_LEVEL_LOW - [0:0] - read-write - - - - - DORMANT_WAKE_INTF3 - 0x0000017c - Interrupt Force for dormant_wake - 0x00000000 - - - GPIO29_EDGE_HIGH - [23:23] - read-write - - - GPIO29_EDGE_LOW - [22:22] - read-write - - - GPIO29_LEVEL_HIGH - [21:21] - read-write - - - GPIO29_LEVEL_LOW - [20:20] - read-write - - - GPIO28_EDGE_HIGH - [19:19] - read-write - - - GPIO28_EDGE_LOW - [18:18] - read-write - - - GPIO28_LEVEL_HIGH - [17:17] - read-write - - - GPIO28_LEVEL_LOW - [16:16] - read-write - - - GPIO27_EDGE_HIGH - [15:15] - read-write - - - GPIO27_EDGE_LOW - [14:14] - read-write - - - GPIO27_LEVEL_HIGH - [13:13] - read-write - - - GPIO27_LEVEL_LOW - [12:12] - read-write - - - GPIO26_EDGE_HIGH - [11:11] - read-write - - - GPIO26_EDGE_LOW - [10:10] - read-write - - - GPIO26_LEVEL_HIGH - [9:9] - read-write - - - GPIO26_LEVEL_LOW - [8:8] - read-write - - - GPIO25_EDGE_HIGH - [7:7] - read-write - - - GPIO25_EDGE_LOW - [6:6] - read-write - - - GPIO25_LEVEL_HIGH - [5:5] - read-write - - - GPIO25_LEVEL_LOW - [4:4] - read-write - - - GPIO24_EDGE_HIGH - [3:3] - read-write - - - GPIO24_EDGE_LOW - [2:2] - read-write - - - GPIO24_LEVEL_HIGH - [1:1] - read-write - - - GPIO24_LEVEL_LOW - [0:0] - read-write - - - - - DORMANT_WAKE_INTS0 - 0x00000180 - Interrupt status after masking & forcing for dormant_wake - 0x00000000 - - - GPIO7_EDGE_HIGH - [31:31] - read-only - - - GPIO7_EDGE_LOW - [30:30] - read-only - - - GPIO7_LEVEL_HIGH - [29:29] - read-only - - - GPIO7_LEVEL_LOW - [28:28] - read-only - - - GPIO6_EDGE_HIGH - [27:27] - read-only - - - GPIO6_EDGE_LOW - [26:26] - read-only - - - GPIO6_LEVEL_HIGH - [25:25] - read-only - - - GPIO6_LEVEL_LOW - [24:24] - read-only - - - GPIO5_EDGE_HIGH - [23:23] - read-only - - - GPIO5_EDGE_LOW - [22:22] - read-only - - - GPIO5_LEVEL_HIGH - [21:21] - read-only - - - GPIO5_LEVEL_LOW - [20:20] - read-only - - - GPIO4_EDGE_HIGH - [19:19] - read-only - - - GPIO4_EDGE_LOW - [18:18] - read-only - - - GPIO4_LEVEL_HIGH - [17:17] - read-only - - - GPIO4_LEVEL_LOW - [16:16] - read-only - - - GPIO3_EDGE_HIGH - [15:15] - read-only - - - GPIO3_EDGE_LOW - [14:14] - read-only - - - GPIO3_LEVEL_HIGH - [13:13] - read-only - - - GPIO3_LEVEL_LOW - [12:12] - read-only - - - GPIO2_EDGE_HIGH - [11:11] - read-only - - - GPIO2_EDGE_LOW - [10:10] - read-only - - - GPIO2_LEVEL_HIGH - [9:9] - read-only - - - GPIO2_LEVEL_LOW - [8:8] - read-only - - - GPIO1_EDGE_HIGH - [7:7] - read-only - - - GPIO1_EDGE_LOW - [6:6] - read-only - - - GPIO1_LEVEL_HIGH - [5:5] - read-only - - - GPIO1_LEVEL_LOW - [4:4] - read-only - - - GPIO0_EDGE_HIGH - [3:3] - read-only - - - GPIO0_EDGE_LOW - [2:2] - read-only - - - GPIO0_LEVEL_HIGH - [1:1] - read-only - - - GPIO0_LEVEL_LOW - [0:0] - read-only - - - - - DORMANT_WAKE_INTS1 - 0x00000184 - Interrupt status after masking & forcing for dormant_wake - 0x00000000 - - - GPIO15_EDGE_HIGH - [31:31] - read-only - - - GPIO15_EDGE_LOW - [30:30] - read-only - - - GPIO15_LEVEL_HIGH - [29:29] - read-only - - - GPIO15_LEVEL_LOW - [28:28] - read-only - - - GPIO14_EDGE_HIGH - [27:27] - read-only - - - GPIO14_EDGE_LOW - [26:26] - read-only - - - GPIO14_LEVEL_HIGH - [25:25] - read-only - - - GPIO14_LEVEL_LOW - [24:24] - read-only - - - GPIO13_EDGE_HIGH - [23:23] - read-only - - - GPIO13_EDGE_LOW - [22:22] - read-only - - - GPIO13_LEVEL_HIGH - [21:21] - read-only - - - GPIO13_LEVEL_LOW - [20:20] - read-only - - - GPIO12_EDGE_HIGH - [19:19] - read-only - - - GPIO12_EDGE_LOW - [18:18] - read-only - - - GPIO12_LEVEL_HIGH - [17:17] - read-only - - - GPIO12_LEVEL_LOW - [16:16] - read-only - - - GPIO11_EDGE_HIGH - [15:15] - read-only - - - GPIO11_EDGE_LOW - [14:14] - read-only - - - GPIO11_LEVEL_HIGH - [13:13] - read-only - - - GPIO11_LEVEL_LOW - [12:12] - read-only - - - GPIO10_EDGE_HIGH - [11:11] - read-only - - - GPIO10_EDGE_LOW - [10:10] - read-only - - - GPIO10_LEVEL_HIGH - [9:9] - read-only - - - GPIO10_LEVEL_LOW - [8:8] - read-only - - - GPIO9_EDGE_HIGH - [7:7] - read-only - - - GPIO9_EDGE_LOW - [6:6] - read-only - - - GPIO9_LEVEL_HIGH - [5:5] - read-only - - - GPIO9_LEVEL_LOW - [4:4] - read-only - - - GPIO8_EDGE_HIGH - [3:3] - read-only - - - GPIO8_EDGE_LOW - [2:2] - read-only - - - GPIO8_LEVEL_HIGH - [1:1] - read-only - - - GPIO8_LEVEL_LOW - [0:0] - read-only - - - - - DORMANT_WAKE_INTS2 - 0x00000188 - Interrupt status after masking & forcing for dormant_wake - 0x00000000 - - - GPIO23_EDGE_HIGH - [31:31] - read-only - - - GPIO23_EDGE_LOW - [30:30] - read-only - - - GPIO23_LEVEL_HIGH - [29:29] - read-only - - - GPIO23_LEVEL_LOW - [28:28] - read-only - - - GPIO22_EDGE_HIGH - [27:27] - read-only - - - GPIO22_EDGE_LOW - [26:26] - read-only - - - GPIO22_LEVEL_HIGH - [25:25] - read-only - - - GPIO22_LEVEL_LOW - [24:24] - read-only - - - GPIO21_EDGE_HIGH - [23:23] - read-only - - - GPIO21_EDGE_LOW - [22:22] - read-only - - - GPIO21_LEVEL_HIGH - [21:21] - read-only - - - GPIO21_LEVEL_LOW - [20:20] - read-only - - - GPIO20_EDGE_HIGH - [19:19] - read-only - - - GPIO20_EDGE_LOW - [18:18] - read-only - - - GPIO20_LEVEL_HIGH - [17:17] - read-only - - - GPIO20_LEVEL_LOW - [16:16] - read-only - - - GPIO19_EDGE_HIGH - [15:15] - read-only - - - GPIO19_EDGE_LOW - [14:14] - read-only - - - GPIO19_LEVEL_HIGH - [13:13] - read-only - - - GPIO19_LEVEL_LOW - [12:12] - read-only - - - GPIO18_EDGE_HIGH - [11:11] - read-only - - - GPIO18_EDGE_LOW - [10:10] - read-only - - - GPIO18_LEVEL_HIGH - [9:9] - read-only - - - GPIO18_LEVEL_LOW - [8:8] - read-only - - - GPIO17_EDGE_HIGH - [7:7] - read-only - - - GPIO17_EDGE_LOW - [6:6] - read-only - - - GPIO17_LEVEL_HIGH - [5:5] - read-only - - - GPIO17_LEVEL_LOW - [4:4] - read-only - - - GPIO16_EDGE_HIGH - [3:3] - read-only - - - GPIO16_EDGE_LOW - [2:2] - read-only - - - GPIO16_LEVEL_HIGH - [1:1] - read-only - - - GPIO16_LEVEL_LOW - [0:0] - read-only - - - - - DORMANT_WAKE_INTS3 - 0x0000018c - Interrupt status after masking & forcing for dormant_wake - 0x00000000 - - - GPIO29_EDGE_HIGH - [23:23] - read-only - - - GPIO29_EDGE_LOW - [22:22] - read-only - - - GPIO29_LEVEL_HIGH - [21:21] - read-only - - - GPIO29_LEVEL_LOW - [20:20] - read-only - - - GPIO28_EDGE_HIGH - [19:19] - read-only - - - GPIO28_EDGE_LOW - [18:18] - read-only - - - GPIO28_LEVEL_HIGH - [17:17] - read-only - - - GPIO28_LEVEL_LOW - [16:16] - read-only - - - GPIO27_EDGE_HIGH - [15:15] - read-only - - - GPIO27_EDGE_LOW - [14:14] - read-only - - - GPIO27_LEVEL_HIGH - [13:13] - read-only - - - GPIO27_LEVEL_LOW - [12:12] - read-only - - - GPIO26_EDGE_HIGH - [11:11] - read-only - - - GPIO26_EDGE_LOW - [10:10] - read-only - - - GPIO26_LEVEL_HIGH - [9:9] - read-only - - - GPIO26_LEVEL_LOW - [8:8] - read-only - - - GPIO25_EDGE_HIGH - [7:7] - read-only - - - GPIO25_EDGE_LOW - [6:6] - read-only - - - GPIO25_LEVEL_HIGH - [5:5] - read-only - - - GPIO25_LEVEL_LOW - [4:4] - read-only - - - GPIO24_EDGE_HIGH - [3:3] - read-only - - - GPIO24_EDGE_LOW - [2:2] - read-only - - - GPIO24_LEVEL_HIGH - [1:1] - read-only - - - GPIO24_LEVEL_LOW - [0:0] - read-only - - - - - - - SYSINFO - 0x40000000 - - 0 - 20 - registers - - - - CHIP_ID - 0x00000000 - JEDEC JEP-106 compliant chip identifier. - 0x00000000 - - - REVISION - [31:28] - read-only - - - PART - [27:12] - read-only - - - MANUFACTURER - [11:0] - read-only - - - - - PLATFORM - 0x00000004 - Platform register. Allows software to know what environment it is running in. - 0x00000000 - - - ASIC - [1:1] - read-only - - - FPGA - [0:0] - read-only - - - - - GITREF_RP2040 - 0x00000010 - Git hash of the chip source. Used to identify chip version. - 0x00000000 - - - GITREF_RP2040 - [31:0] - read-only - - - - - - - PPB - 0xe0000000 - - 0 - 60836 - registers - - - - SYST_CSR - 0x0000e010 - Use the SysTick Control and Status Register to enable the SysTick features. - 0x00000000 - - - COUNTFLAG - Returns 1 if timer counted to 0 since last time this was read. Clears on read by application or debugger. - [16:16] - read-only - - - CLKSOURCE - SysTick clock source. Always reads as one if SYST_CALIB reports NOREF. - Selects the SysTick timer clock source: - 0 = External reference clock. - 1 = Processor clock. - [2:2] - read-write - - - TICKINT - Enables SysTick exception request: - 0 = Counting down to zero does not assert the SysTick exception request. - 1 = Counting down to zero to asserts the SysTick exception request. - [1:1] - read-write - - - ENABLE - Enable SysTick counter: - 0 = Counter disabled. - 1 = Counter enabled. - [0:0] - read-write - - - - - SYST_RVR - 0x0000e014 - Use the SysTick Reload Value Register to specify the start value to load into the current value register when the counter reaches 0. It can be any value between 0 and 0x00FFFFFF. A start value of 0 is possible, but has no effect because the SysTick interrupt and COUNTFLAG are activated when counting from 1 to 0. The reset value of this register is UNKNOWN. - To generate a multi-shot timer with a period of N processor clock cycles, use a RELOAD value of N-1. For example, if the SysTick interrupt is required every 100 clock pulses, set RELOAD to 99. - 0x00000000 - - - RELOAD - Value to load into the SysTick Current Value Register when the counter reaches 0. - [23:0] - read-write - - - - - SYST_CVR - 0x0000e018 - Use the SysTick Current Value Register to find the current value in the register. The reset value of this register is UNKNOWN. - 0x00000000 - - - CURRENT - Reads return the current value of the SysTick counter. This register is write-clear. Writing to it with any value clears the register to 0. Clearing this register also clears the COUNTFLAG bit of the SysTick Control and Status Register. - [23:0] - read-write - - - - - SYST_CALIB - 0x0000e01c - Use the SysTick Calibration Value Register to enable software to scale to any required speed using divide and multiply. - 0x00000000 - - - NOREF - If reads as 1, the Reference clock is not provided - the CLKSOURCE bit of the SysTick Control and Status register will be forced to 1 and cannot be cleared to 0. - [31:31] - read-only - - - SKEW - If reads as 1, the calibration value for 10ms is inexact (due to clock frequency). - [30:30] - read-only - - - TENMS - An optional Reload value to be used for 10ms (100Hz) timing, subject to system clock skew errors. If the value reads as 0, the calibration value is not known. - [23:0] - read-only - - - - - NVIC_ISER - 0x0000e100 - Use the Interrupt Set-Enable Register to enable interrupts and determine which interrupts are currently enabled. - If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. If an interrupt is not enabled, asserting its interrupt signal changes the interrupt state to pending, but the NVIC never activates the interrupt, regardless of its priority. - 0x00000000 - - - SETENA - Interrupt set-enable bits. - Write: - 0 = No effect. - 1 = Enable interrupt. - Read: - 0 = Interrupt disabled. - 1 = Interrupt enabled. - [31:0] - read-write - - - - - NVIC_ICER - 0x0000e180 - Use the Interrupt Clear-Enable Registers to disable interrupts and determine which interrupts are currently enabled. - 0x00000000 - - - CLRENA - Interrupt clear-enable bits. - Write: - 0 = No effect. - 1 = Disable interrupt. - Read: - 0 = Interrupt disabled. - 1 = Interrupt enabled. - [31:0] - read-write - - - - - NVIC_ISPR - 0x0000e200 - The NVIC_ISPR forces interrupts into the pending state, and shows which interrupts are pending. - 0x00000000 - - - SETPEND - Interrupt set-pending bits. - Write: - 0 = No effect. - 1 = Changes interrupt state to pending. - Read: - 0 = Interrupt is not pending. - 1 = Interrupt is pending. - Note: Writing 1 to the NVIC_ISPR bit corresponding to: - An interrupt that is pending has no effect. - A disabled interrupt sets the state of that interrupt to pending. - [31:0] - read-write - - - - - NVIC_ICPR - 0x0000e280 - Use the Interrupt Clear-Pending Register to clear pending interrupts and determine which interrupts are currently pending. - 0x00000000 - - - CLRPEND - Interrupt clear-pending bits. - Write: - 0 = No effect. - 1 = Removes pending state and interrupt. - Read: - 0 = Interrupt is not pending. - 1 = Interrupt is pending. - [31:0] - read-write - - - - - NVIC_IPR0 - 0x0000e400 - Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest. - Note: Writing 1 to an NVIC_ICPR bit does not affect the active state of the corresponding interrupt. - These registers are only word-accessible - 0x00000000 - - - IP_3 - Priority of interrupt 3 - [31:30] - read-write - - - IP_2 - Priority of interrupt 2 - [23:22] - read-write - - - IP_1 - Priority of interrupt 1 - [15:14] - read-write - - - IP_0 - Priority of interrupt 0 - [7:6] - read-write - - - - - NVIC_IPR1 - 0x0000e404 - Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest. - 0x00000000 - - - IP_7 - Priority of interrupt 7 - [31:30] - read-write - - - IP_6 - Priority of interrupt 6 - [23:22] - read-write - - - IP_5 - Priority of interrupt 5 - [15:14] - read-write - - - IP_4 - Priority of interrupt 4 - [7:6] - read-write - - - - - NVIC_IPR2 - 0x0000e408 - Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest. - 0x00000000 - - - IP_11 - Priority of interrupt 11 - [31:30] - read-write - - - IP_10 - Priority of interrupt 10 - [23:22] - read-write - - - IP_9 - Priority of interrupt 9 - [15:14] - read-write - - - IP_8 - Priority of interrupt 8 - [7:6] - read-write - - - - - NVIC_IPR3 - 0x0000e40c - Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest. - 0x00000000 - - - IP_15 - Priority of interrupt 15 - [31:30] - read-write - - - IP_14 - Priority of interrupt 14 - [23:22] - read-write - - - IP_13 - Priority of interrupt 13 - [15:14] - read-write - - - IP_12 - Priority of interrupt 12 - [7:6] - read-write - - - - - NVIC_IPR4 - 0x0000e410 - Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest. - 0x00000000 - - - IP_19 - Priority of interrupt 19 - [31:30] - read-write - - - IP_18 - Priority of interrupt 18 - [23:22] - read-write - - - IP_17 - Priority of interrupt 17 - [15:14] - read-write - - - IP_16 - Priority of interrupt 16 - [7:6] - read-write - - - - - NVIC_IPR5 - 0x0000e414 - Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest. - 0x00000000 - - - IP_23 - Priority of interrupt 23 - [31:30] - read-write - - - IP_22 - Priority of interrupt 22 - [23:22] - read-write - - - IP_21 - Priority of interrupt 21 - [15:14] - read-write - - - IP_20 - Priority of interrupt 20 - [7:6] - read-write - - - - - NVIC_IPR6 - 0x0000e418 - Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest. - 0x00000000 - - - IP_27 - Priority of interrupt 27 - [31:30] - read-write - - - IP_26 - Priority of interrupt 26 - [23:22] - read-write - - - IP_25 - Priority of interrupt 25 - [15:14] - read-write - - - IP_24 - Priority of interrupt 24 - [7:6] - read-write - - - - - NVIC_IPR7 - 0x0000e41c - Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest. - 0x00000000 - - - IP_31 - Priority of interrupt 31 - [31:30] - read-write - - - IP_30 - Priority of interrupt 30 - [23:22] - read-write - - - IP_29 - Priority of interrupt 29 - [15:14] - read-write - - - IP_28 - Priority of interrupt 28 - [7:6] - read-write - - - - - CPUID - 0x0000ed00 - Read the CPU ID Base Register to determine: the ID number of the processor core, the version number of the processor core, the implementation details of the processor core. - 0x410cc601 - - - IMPLEMENTER - Implementor code: 0x41 = ARM - [31:24] - read-only - - - VARIANT - Major revision number n in the rnpm revision status: - 0x0 = Revision 0. - [23:20] - read-only - - - ARCHITECTURE - Constant that defines the architecture of the processor: - 0xC = ARMv6-M architecture. - [19:16] - read-only - - - PARTNO - Number of processor within family: 0xC60 = Cortex-M0+ - [15:4] - read-only - - - REVISION - Minor revision number m in the rnpm revision status: - 0x1 = Patch 1. - [3:0] - read-only - - - - - ICSR - 0x0000ed04 - Use the Interrupt Control State Register to set a pending Non-Maskable Interrupt (NMI), set or clear a pending PendSV, set or clear a pending SysTick, check for pending exceptions, check the vector number of the highest priority pended exception, check the vector number of the active exception. - 0x00000000 - - - NMIPENDSET - Setting this bit will activate an NMI. Since NMI is the highest priority exception, it will activate as soon as it is registered. - NMI set-pending bit. - Write: - 0 = No effect. - 1 = Changes NMI exception state to pending. - Read: - 0 = NMI exception is not pending. - 1 = NMI exception is pending. - Because NMI is the highest-priority exception, normally the processor enters the NMI - exception handler as soon as it detects a write of 1 to this bit. Entering the handler then clears - this bit to 0. This means a read of this bit by the NMI exception handler returns 1 only if the - NMI signal is reasserted while the processor is executing that handler. - [31:31] - read-write - - - PENDSVSET - PendSV set-pending bit. - Write: - 0 = No effect. - 1 = Changes PendSV exception state to pending. - Read: - 0 = PendSV exception is not pending. - 1 = PendSV exception is pending. - Writing 1 to this bit is the only way to set the PendSV exception state to pending. - [28:28] - read-write - - - PENDSVCLR - PendSV clear-pending bit. - Write: - 0 = No effect. - 1 = Removes the pending state from the PendSV exception. - [27:27] - read-write - - - PENDSTSET - SysTick exception set-pending bit. - Write: - 0 = No effect. - 1 = Changes SysTick exception state to pending. - Read: - 0 = SysTick exception is not pending. - 1 = SysTick exception is pending. - [26:26] - read-write - - - PENDSTCLR - SysTick exception clear-pending bit. - Write: - 0 = No effect. - 1 = Removes the pending state from the SysTick exception. - This bit is WO. On a register read its value is Unknown. - [25:25] - read-write - - - ISRPREEMPT - The system can only access this bit when the core is halted. It indicates that a pending interrupt is to be taken in the next running cycle. If C_MASKINTS is clear in the Debug Halting Control and Status Register, the interrupt is serviced. - [23:23] - read-only - - - ISRPENDING - External interrupt pending flag - [22:22] - read-only - - - VECTPENDING - Indicates the exception number for the highest priority pending exception: 0 = no pending exceptions. Non zero = The pending state includes the effect of memory-mapped enable and mask registers. It does not include the PRIMASK special-purpose register qualifier. - [20:12] - read-only - - - VECTACTIVE - Active exception number field. Reset clears the VECTACTIVE field. - [8:0] - read-only - - - - - VTOR - 0x0000ed08 - The VTOR holds the vector table offset address. - 0x00000000 - - - TBLOFF - Bits [31:8] of the indicate the vector table offset address. - [31:8] - read-write - - - - - AIRCR - 0x0000ed0c - Use the Application Interrupt and Reset Control Register to: determine data endianness, clear all active state information from debug halt mode, request a system reset. - 0x00000000 - - - VECTKEY - Register key: - Reads as Unknown - On writes, write 0x05FA to VECTKEY, otherwise the write is ignored. - [31:16] - read-write - - - ENDIANESS - Data endianness implemented: - 0 = Little-endian. - [15:15] - read-only - - - SYSRESETREQ - Writing 1 to this bit causes the SYSRESETREQ signal to the outer system to be asserted to request a reset. The intention is to force a large system reset of all major components except for debug. The C_HALT bit in the DHCSR is cleared as a result of the system reset requested. The debugger does not lose contact with the device. - [2:2] - read-write - - - VECTCLRACTIVE - Clears all active state information for fixed and configurable exceptions. This bit: is self-clearing, can only be set by the DAP when the core is halted. When set: clears all active exception status of the processor, forces a return to Thread mode, forces an IPSR of 0. A debugger must re-initialize the stack. - [1:1] - read-write - - - - - SCR - 0x0000ed10 - System Control Register. Use the System Control Register for power-management functions: signal to the system when the processor can enter a low power state, control how the processor enters and exits low power states. - 0x00000000 - - - SEVONPEND - Send Event on Pending bit: - 0 = Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded. - 1 = Enabled events and all interrupts, including disabled interrupts, can wakeup the processor. - When an event or interrupt becomes pending, the event signal wakes up the processor from WFE. If the - processor is not waiting for an event, the event is registered and affects the next WFE. - The processor also wakes up on execution of an SEV instruction or an external event. - [4:4] - read-write - - - SLEEPDEEP - Controls whether the processor uses sleep or deep sleep as its low power mode: - 0 = Sleep. - 1 = Deep sleep. - [2:2] - read-write - - - SLEEPONEXIT - Indicates sleep-on-exit when returning from Handler mode to Thread mode: - 0 = Do not sleep when returning to Thread mode. - 1 = Enter sleep, or deep sleep, on return from an ISR to Thread mode. - Setting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application. - [1:1] - read-write - - - - - CCR - 0x0000ed14 - The Configuration and Control Register permanently enables stack alignment and causes unaligned accesses to result in a Hard Fault. - 0x00000000 - - - STKALIGN - Always reads as one, indicates 8-byte stack alignment on exception entry. On exception entry, the processor uses bit[9] of the stacked PSR to indicate the stack alignment. On return from the exception it uses this stacked bit to restore the correct stack alignment. - [9:9] - read-only - - - UNALIGN_TRP - Always reads as one, indicates that all unaligned accesses generate a HardFault. - [3:3] - read-only - - - - - SHPR2 - 0x0000ed1c - System handlers are a special class of exception handler that can have their priority set to any of the priority levels. Use the System Handler Priority Register 2 to set the priority of SVCall. - 0x00000000 - - - PRI_11 - Priority of system handler 11, SVCall - [31:30] - read-write - - - - - SHPR3 - 0x0000ed20 - System handlers are a special class of exception handler that can have their priority set to any of the priority levels. Use the System Handler Priority Register 3 to set the priority of PendSV and SysTick. - 0x00000000 - - - PRI_15 - Priority of system handler 15, SysTick - [31:30] - read-write - - - PRI_14 - Priority of system handler 14, PendSV - [23:22] - read-write - - - - - SHCSR - 0x0000ed24 - Use the System Handler Control and State Register to determine or clear the pending status of SVCall. - 0x00000000 - - - SVCALLPENDED - Reads as 1 if SVCall is Pending. Write 1 to set pending SVCall, write 0 to clear pending SVCall. - [15:15] - read-write - - - - - MPU_TYPE - 0x0000ed90 - Read the MPU Type Register to determine if the processor implements an MPU, and how many regions the MPU supports. - 0x00000800 - - - IREGION - Instruction region. Reads as zero as ARMv6-M only supports a unified MPU. - [23:16] - read-only - - - DREGION - Number of regions supported by the MPU. - [15:8] - read-only - - - SEPARATE - Indicates support for separate instruction and data address maps. Reads as 0 as ARMv6-M only supports a unified MPU. - [0:0] - read-only - - - - - MPU_CTRL - 0x0000ed94 - Use the MPU Control Register to enable and disable the MPU, and to control whether the default memory map is enabled as a background region for privileged accesses, and whether the MPU is enabled for HardFaults and NMIs. - 0x00000000 - - - PRIVDEFENA - Controls whether the default memory map is enabled as a background region for privileged accesses. This bit is ignored when ENABLE is clear. - 0 = If the MPU is enabled, disables use of the default memory map. Any memory access to a location not - covered by any enabled region causes a fault. - 1 = If the MPU is enabled, enables use of the default memory map as a background region for privileged software accesses. - When enabled, the background region acts as if it is region number -1. Any region that is defined and enabled has priority over this default map. - [2:2] - read-write - - - HFNMIENA - Controls the use of the MPU for HardFaults and NMIs. Setting this bit when ENABLE is clear results in UNPREDICTABLE behaviour. - When the MPU is enabled: - 0 = MPU is disabled during HardFault and NMI handlers, regardless of the value of the ENABLE bit. - 1 = the MPU is enabled during HardFault and NMI handlers. - [1:1] - read-write - - - ENABLE - Enables the MPU. If the MPU is disabled, privileged and unprivileged accesses use the default memory map. - 0 = MPU disabled. - 1 = MPU enabled. - [0:0] - read-write - - - - - MPU_RNR - 0x0000ed98 - Use the MPU Region Number Register to select the region currently accessed by MPU_RBAR and MPU_RASR. - 0x00000000 - - - REGION - Indicates the MPU region referenced by the MPU_RBAR and MPU_RASR registers. - The MPU supports 8 memory regions, so the permitted values of this field are 0-7. - [3:0] - read-write - - - - - MPU_RBAR - 0x0000ed9c - Read the MPU Region Base Address Register to determine the base address of the region identified by MPU_RNR. Write to update the base address of said region or that of a specified region, with whose number MPU_RNR will also be updated. - 0x00000000 - - - ADDR - Base address of the region. - [31:8] - read-write - - - VALID - On writes, indicates whether the write must update the base address of the region identified by the REGION field, updating the MPU_RNR to indicate this new region. - Write: - 0 = MPU_RNR not changed, and the processor: - Updates the base address for the region specified in the MPU_RNR. - Ignores the value of the REGION field. - 1 = The processor: - Updates the value of the MPU_RNR to the value of the REGION field. - Updates the base address for the region specified in the REGION field. - Always reads as zero. - [4:4] - read-write - - - REGION - On writes, specifies the number of the region whose base address to update provided VALID is set written as 1. On reads, returns bits [3:0] of MPU_RNR. - [3:0] - read-write - - - - - MPU_RASR - 0x0000eda0 - Use the MPU Region Attribute and Size Register to define the size, access behaviour and memory type of the region identified by MPU_RNR, and enable that region. - 0x00000000 - - - ATTRS - The MPU Region Attribute field. Use to define the region attribute control. - 28 = XN: Instruction access disable bit: - 0 = Instruction fetches enabled. - 1 = Instruction fetches disabled. - 26:24 = AP: Access permission field - 18 = S: Shareable bit - 17 = C: Cacheable bit - 16 = B: Bufferable bit - [31:16] - read-write - - - SRD - Subregion Disable. For regions of 256 bytes or larger, each bit of this field controls whether one of the eight equal subregions is enabled. - [15:8] - read-write - - - SIZE - Indicates the region size. Region size in bytes = 2^(SIZE+1). The minimum permitted value is 7 (b00111) = 256Bytes - [5:1] - read-write - - - ENABLE - Enables the region. - [0:0] - read-write - - - - - - - SSI - DW_apb_ssi has the following features: - * APB interface – Allows for easy integration into a DesignWare Synthesizable Components for AMBA 2 implementation. - * APB3 and APB4 protocol support. - * Scalable APB data bus width – Supports APB data bus widths of 8, 16, and 32 bits. - * Serial-master or serial-slave operation – Enables serial communication with serial-master or serial-slave peripheral devices. - * Programmable Dual/Quad/Octal SPI support in Master Mode. - * Dual Data Rate (DDR) and Read Data Strobe (RDS) Support - Enables the DW_apb_ssi master to perform operations with the device in DDR and RDS modes when working in Dual/Quad/Octal mode of operation. - * Data Mask Support - Enables the DW_apb_ssi to selectively update the bytes in the device. This feature is applicable only in enhanced SPI modes. - * eXecute-In-Place (XIP) support - Enables the DW_apb_ssi master to behave as a memory mapped I/O and fetches the data from the device based on the APB read request. This feature is applicable only in enhanced SPI modes. - * DMA Controller Interface – Enables the DW_apb_ssi to interface to a DMA controller over the bus using a handshaking interface for transfer requests. - * Independent masking of interrupts – Master collision, transmit FIFO overflow, transmit FIFO empty, receive FIFO full, receive FIFO underflow, and receive FIFO overflow interrupts can all be masked independently. - * Multi-master contention detection – Informs the processor of multiple serial-master accesses on the serial bus. - * Bypass of meta-stability flip-flops for synchronous clocks – When the APB clock (pclk) and the DW_apb_ssi serial clock (ssi_clk) are synchronous, meta-stable flip-flops are not used when transferring control signals across these clock domains. - * Programmable delay on the sample time of the received serial data bit (rxd); enables programmable control of routing delays resulting in higher serial data-bit rates. - * Programmable features: - - Serial interface operation – Choice of Motorola SPI, Texas Instruments Synchronous Serial Protocol or National Semiconductor Microwire. - - Clock bit-rate – Dynamic control of the serial bit rate of the data transfer; used in only serial-master mode of operation. - - Data Item size (4 to 32 bits) – Item size of each data transfer under the control of the programmer. - * Configured features: - - FIFO depth – 16 words deep. The FIFO width is fixed at 32 bits. - - 1 slave select output. - - Hardware slave-select – Dedicated hardware slave-select line. - - Combined interrupt line - one combined interrupt line from the DW_apb_ssi to the interrupt controller. - - Interrupt polarity – active high interrupt lines. - - Serial clock polarity – low serial-clock polarity directly after reset. - - Serial clock phase – capture on first edge of serial-clock directly after reset. - 0x18000000 - - 0 - 252 - registers - - - - CTRLR0 - 0x00000000 - Control register 0 - 0x00000000 - - - SSTE - Slave select toggle enable - [24:24] - read-write - - - SPI_FRF - SPI frame format - [22:21] - read-write - - - STD - 0 - Standard 1-bit SPI frame format; 1 bit per SCK, full-duplex - - - DUAL - 1 - Dual-SPI frame format; two bits per SCK, half-duplex - - - QUAD - 2 - Quad-SPI frame format; four bits per SCK, half-duplex - - - - - DFS_32 - Data frame size in 32b transfer mode - Value of n -> n+1 clocks per frame. - [20:16] - read-write - - - CFS - Control frame size - Value of n -> n+1 clocks per frame. - [15:12] - read-write - - - SRL - Shift register loop (test mode) - [11:11] - read-write - - - SLV_OE - Slave output enable - [10:10] - read-write - - - TMOD - Transfer mode - [9:8] - read-write - - - TX_AND_RX - 0 - Both transmit and receive - - - TX_ONLY - 1 - Transmit only (not for FRF == 0, standard SPI mode) - - - RX_ONLY - 2 - Receive only (not for FRF == 0, standard SPI mode) - - - EEPROM_READ - 3 - EEPROM read mode (TX then RX; RX starts after control data TX'd) - - - - - SCPOL - Serial clock polarity - [7:7] - read-write - - - SCPH - Serial clock phase - [6:6] - read-write - - - FRF - Frame format - [5:4] - read-write - - - DFS - Data frame size - [3:0] - read-write - - - - - CTRLR1 - 0x00000004 - Master Control register 1 - 0x00000000 - - - NDF - Number of data frames - [15:0] - read-write - - - - - SSIENR - 0x00000008 - SSI Enable - 0x00000000 - - - SSI_EN - SSI enable - [0:0] - read-write - - - - - MWCR - 0x0000000c - Microwire Control - 0x00000000 - - - MHS - Microwire handshaking - [2:2] - read-write - - - MDD - Microwire control - [1:1] - read-write - - - MWMOD - Microwire transfer mode - [0:0] - read-write - - - - - SER - 0x00000010 - Slave enable - 0x00000000 - - - SER - For each bit: - 0 -> slave not selected - 1 -> slave selected - [0:0] - read-write - - - - - BAUDR - 0x00000014 - Baud rate - 0x00000000 - - - SCKDV - SSI clock divider - [15:0] - read-write - - - - - TXFTLR - 0x00000018 - TX FIFO threshold level - 0x00000000 - - - TFT - Transmit FIFO threshold - [7:0] - read-write - - - - - RXFTLR - 0x0000001c - RX FIFO threshold level - 0x00000000 - - - RFT - Receive FIFO threshold - [7:0] - read-write - - - - - TXFLR - 0x00000020 - TX FIFO level - 0x00000000 - - - TFTFL - Transmit FIFO level - [7:0] - read-only - - - - - RXFLR - 0x00000024 - RX FIFO level - 0x00000000 - - - RXTFL - Receive FIFO level - [7:0] - read-only - - - - - SR - 0x00000028 - Status register - 0x00000000 - - - DCOL - Data collision error - [6:6] - read-only - - - TXE - Transmission error - [5:5] - read-only - - - RFF - Receive FIFO full - [4:4] - read-only - - - RFNE - Receive FIFO not empty - [3:3] - read-only - - - TFE - Transmit FIFO empty - [2:2] - read-only - - - TFNF - Transmit FIFO not full - [1:1] - read-only - - - BUSY - SSI busy flag - [0:0] - read-only - - - - - IMR - 0x0000002c - Interrupt mask - 0x00000000 - - - MSTIM - Multi-master contention interrupt mask - [5:5] - read-write - - - RXFIM - Receive FIFO full interrupt mask - [4:4] - read-write - - - RXOIM - Receive FIFO overflow interrupt mask - [3:3] - read-write - - - RXUIM - Receive FIFO underflow interrupt mask - [2:2] - read-write - - - TXOIM - Transmit FIFO overflow interrupt mask - [1:1] - read-write - - - TXEIM - Transmit FIFO empty interrupt mask - [0:0] - read-write - - - - - ISR - 0x00000030 - Interrupt status - 0x00000000 - - - MSTIS - Multi-master contention interrupt status - [5:5] - read-only - - - RXFIS - Receive FIFO full interrupt status - [4:4] - read-only - - - RXOIS - Receive FIFO overflow interrupt status - [3:3] - read-only - - - RXUIS - Receive FIFO underflow interrupt status - [2:2] - read-only - - - TXOIS - Transmit FIFO overflow interrupt status - [1:1] - read-only - - - TXEIS - Transmit FIFO empty interrupt status - [0:0] - read-only - - - - - RISR - 0x00000034 - Raw interrupt status - 0x00000000 - - - MSTIR - Multi-master contention raw interrupt status - [5:5] - read-only - - - RXFIR - Receive FIFO full raw interrupt status - [4:4] - read-only - - - RXOIR - Receive FIFO overflow raw interrupt status - [3:3] - read-only - - - RXUIR - Receive FIFO underflow raw interrupt status - [2:2] - read-only - - - TXOIR - Transmit FIFO overflow raw interrupt status - [1:1] - read-only - - - TXEIR - Transmit FIFO empty raw interrupt status - [0:0] - read-only - - - - - TXOICR - 0x00000038 - TX FIFO overflow interrupt clear - 0x00000000 - - - TXOICR - Clear-on-read transmit FIFO overflow interrupt - [0:0] - read-only - - - - - RXOICR - 0x0000003c - RX FIFO overflow interrupt clear - 0x00000000 - - - RXOICR - Clear-on-read receive FIFO overflow interrupt - [0:0] - read-only - - - - - RXUICR - 0x00000040 - RX FIFO underflow interrupt clear - 0x00000000 - - - RXUICR - Clear-on-read receive FIFO underflow interrupt - [0:0] - read-only - - - - - MSTICR - 0x00000044 - Multi-master interrupt clear - 0x00000000 - - - MSTICR - Clear-on-read multi-master contention interrupt - [0:0] - read-only - - - - - ICR - 0x00000048 - Interrupt clear - 0x00000000 - - - ICR - Clear-on-read all active interrupts - [0:0] - read-only - - - - - DMACR - 0x0000004c - DMA control - 0x00000000 - - - TDMAE - Transmit DMA enable - [1:1] - read-write - - - RDMAE - Receive DMA enable - [0:0] - read-write - - - - - DMATDLR - 0x00000050 - DMA TX data level - 0x00000000 - - - DMATDL - Transmit data watermark level - [7:0] - read-write - - - - - DMARDLR - 0x00000054 - DMA RX data level - 0x00000000 - - - DMARDL - Receive data watermark level (DMARDLR+1) - [7:0] - read-write - - - - - IDR - 0x00000058 - Identification register - 0x51535049 - - - IDCODE - Peripheral dentification code - [31:0] - read-only - - - - - SSI_VERSION_ID - 0x0000005c - Version ID - 0x3430312a - - - SSI_COMP_VERSION - SNPS component version (format X.YY) - [31:0] - read-only - - - - - DR0 - 0x00000060 - Data Register 0 (of 36) - 0x00000000 - - - DR - First data register of 36 - [31:0] - read-write - - - - - RX_SAMPLE_DLY - 0x000000f0 - RX sample delay - 0x00000000 - - - RSD - RXD sample delay (in SCLK cycles) - [7:0] - read-write - - - - - SPI_CTRLR0 - 0x000000f4 - SPI control - 0x03000000 - - - XIP_CMD - SPI Command to send in XIP mode (INST_L = 8-bit) or to append to Address (INST_L = 0-bit) - [31:24] - read-write - - - SPI_RXDS_EN - Read data strobe enable - [18:18] - read-write - - - INST_DDR_EN - Instruction DDR transfer enable - [17:17] - read-write - - - SPI_DDR_EN - SPI DDR transfer enable - [16:16] - read-write - - - WAIT_CYCLES - Wait cycles between control frame transmit and data reception (in SCLK cycles) - [15:11] - read-write - - - INST_L - Instruction length (0/4/8/16b) - [9:8] - read-write - - - NONE - 0 - No instruction - - - 4B - 1 - 4-bit instruction - - - 8B - 2 - 8-bit instruction - - - 16B - 3 - 16-bit instruction - - - - - ADDR_L - Address length (0b-60b in 4b increments) - [5:2] - read-write - - - TRANS_TYPE - Address and instruction transfer format - [1:0] - read-write - - - 1C1A - 0 - Command and address both in standard SPI frame format - - - 1C2A - 1 - Command in standard SPI format, address in format specified by FRF - - - 2C2A - 2 - Command and address both in format specified by FRF (e.g. Dual-SPI) - - - - - - - TXD_DRIVE_EDGE - 0x000000f8 - TX drive edge - 0x00000000 - - - TDE - TXD drive edge - [7:0] - read-write - - - - - - - XIP_CTRL - QSPI flash execute-in-place block - 0x14000000 - - 0 - 32 - registers - - - XIP_IRQ - 6 - - - - CTRL - 0x00000000 - Cache control - 0x00000003 - - - POWER_DOWN - When 1, the cache memories are powered down. They retain state, - but can not be accessed. This reduces static power dissipation. - Writing 1 to this bit forces CTRL_EN to 0, i.e. the cache cannot - be enabled when powered down. - Cache-as-SRAM accesses will produce a bus error response when - the cache is powered down. - [3:3] - read-write - - - ERR_BADWRITE - When 1, writes to any alias other than 0x0 (caching, allocating) - will produce a bus fault. When 0, these writes are silently ignored. - In either case, writes to the 0x0 alias will deallocate on tag match, - as usual. - [1:1] - read-write - - - EN - When 1, enable the cache. When the cache is disabled, all XIP accesses - will go straight to the flash, without querying the cache. When enabled, - cacheable XIP accesses will query the cache, and the flash will - not be accessed if the tag matches and the valid bit is set. - - If the cache is enabled, cache-as-SRAM accesses have no effect on the - cache data RAM, and will produce a bus error response. - [0:0] - read-write - - - - - FLUSH - 0x00000004 - Cache Flush control - 0x00000000 - - - FLUSH - Write 1 to flush the cache. This clears the tag memory, but - the data memory retains its contents. (This means cache-as-SRAM - contents is not affected by flush or reset.) - Reading will hold the bus (stall the processor) until the flush - completes. Alternatively STAT can be polled until completion. - [0:0] - write-only - - - - - STAT - 0x00000008 - Cache Status - 0x00000002 - - - FIFO_FULL - When 1, indicates the XIP streaming FIFO is completely full. - The streaming FIFO is 2 entries deep, so the full and empty - flag allow its level to be ascertained. - [2:2] - read-only - - - FIFO_EMPTY - When 1, indicates the XIP streaming FIFO is completely empty. - [1:1] - read-only - - - FLUSH_READY - Reads as 0 while a cache flush is in progress, and 1 otherwise. - The cache is flushed whenever the XIP block is reset, and also - when requested via the FLUSH register. - [0:0] - read-only - - - - - CTR_HIT - 0x0000000c - Cache Hit counter - 0x00000000 - - - CTR_HIT - A 32 bit saturating counter that increments upon each cache hit, - i.e. when an XIP access is serviced directly from cached data. - Write any value to clear. - [31:0] - read-write - oneToClear - - - - - CTR_ACC - 0x00000010 - Cache Access counter - 0x00000000 - - - CTR_ACC - A 32 bit saturating counter that increments upon each XIP access, - whether the cache is hit or not. This includes noncacheable accesses. - Write any value to clear. - [31:0] - read-write - oneToClear - - - - - STREAM_ADDR - 0x00000014 - FIFO stream address - 0x00000000 - - - STREAM_ADDR - The address of the next word to be streamed from flash to the streaming FIFO. - Increments automatically after each flash access. - Write the initial access address here before starting a streaming read. - [31:2] - read-write - - - - - STREAM_CTR - 0x00000018 - FIFO stream control - 0x00000000 - - - STREAM_CTR - Write a nonzero value to start a streaming read. This will then - progress in the background, using flash idle cycles to transfer - a linear data block from flash to the streaming FIFO. - Decrements automatically (1 at a time) as the stream - progresses, and halts on reaching 0. - Write 0 to halt an in-progress stream, and discard any in-flight - read, so that a new stream can immediately be started (after - draining the FIFO and reinitialising STREAM_ADDR) - [21:0] - read-write - - - - - STREAM_FIFO - 0x0000001c - FIFO stream data - 0x00000000 - - - STREAM_FIFO - Streamed data is buffered here, for retrieval by the system DMA. - This FIFO can also be accessed via the XIP_AUX slave, to avoid exposing - the DMA to bus stalls caused by other XIP traffic. - [31:0] - read-only - modify - - - - - - - SYSCFG - Register block for various chip control signals - 0x40004000 - - 0 - 28 - registers - - - - PROC0_NMI_MASK - 0x00000000 - Processor core 0 NMI source mask - 0x00000000 - - - PROC0_NMI_MASK - Set a bit high to enable NMI from that IRQ - [31:0] - read-write - - - - - PROC1_NMI_MASK - 0x00000004 - Processor core 1 NMI source mask - 0x00000000 - - - PROC1_NMI_MASK - Set a bit high to enable NMI from that IRQ - [31:0] - read-write - - - - - PROC_CONFIG - 0x00000008 - Configuration for processors - 0x10000000 - - - PROC1_DAP_INSTID - Configure proc1 DAP instance ID. - Recommend that this is NOT changed until you require debug access in multi-chip environment - WARNING: do not set to 15 as this is reserved for RescueDP - [31:28] - read-write - - - PROC0_DAP_INSTID - Configure proc0 DAP instance ID. - Recommend that this is NOT changed until you require debug access in multi-chip environment - WARNING: do not set to 15 as this is reserved for RescueDP - [27:24] - read-write - - - PROC1_HALTED - Indication that proc1 has halted - [1:1] - read-only - - - PROC0_HALTED - Indication that proc0 has halted - [0:0] - read-only - - - - - PROC_IN_SYNC_BYPASS - 0x0000000c - For each bit, if 1, bypass the input synchronizer between that GPIO - and the GPIO input register in the SIO. The input synchronizers should - generally be unbypassed, to avoid injecting metastabilities into processors. - If you're feeling brave, you can bypass to save two cycles of input - latency. This register applies to GPIO 0...29. - 0x00000000 - - - PROC_IN_SYNC_BYPASS - [29:0] - read-write - - - - - PROC_IN_SYNC_BYPASS_HI - 0x00000010 - For each bit, if 1, bypass the input synchronizer between that GPIO - and the GPIO input register in the SIO. The input synchronizers should - generally be unbypassed, to avoid injecting metastabilities into processors. - If you're feeling brave, you can bypass to save two cycles of input - latency. This register applies to GPIO 30...35 (the QSPI IOs). - 0x00000000 - - - PROC_IN_SYNC_BYPASS_HI - [5:0] - read-write - - - - - DBGFORCE - 0x00000014 - Directly control the SWD debug port of either processor - 0x00000066 - - - PROC1_ATTACH - Attach processor 1 debug port to syscfg controls, and disconnect it from external SWD pads. - [7:7] - read-write - - - PROC1_SWCLK - Directly drive processor 1 SWCLK, if PROC1_ATTACH is set - [6:6] - read-write - - - PROC1_SWDI - Directly drive processor 1 SWDIO input, if PROC1_ATTACH is set - [5:5] - read-write - - - PROC1_SWDO - Observe the value of processor 1 SWDIO output. - [4:4] - read-only - - - PROC0_ATTACH - Attach processor 0 debug port to syscfg controls, and disconnect it from external SWD pads. - [3:3] - read-write - - - PROC0_SWCLK - Directly drive processor 0 SWCLK, if PROC0_ATTACH is set - [2:2] - read-write - - - PROC0_SWDI - Directly drive processor 0 SWDIO input, if PROC0_ATTACH is set - [1:1] - read-write - - - PROC0_SWDO - Observe the value of processor 0 SWDIO output. - [0:0] - read-only - - - - - MEMPOWERDOWN - 0x00000018 - Control power downs to memories. Set high to power down memories. - Use with extreme caution - 0x00000000 - - - ROM - [7:7] - read-write - - - USB - [6:6] - read-write - - - SRAM5 - [5:5] - read-write - - - SRAM4 - [4:4] - read-write - - - SRAM3 - [3:3] - read-write - - - SRAM2 - [2:2] - read-write - - - SRAM1 - [1:1] - read-write - - - SRAM0 - [0:0] - read-write - - - - - - - XOSC - Controls the crystal oscillator - 0x40024000 - - 0 - 32 - registers - - - - CTRL - 0x00000000 - Crystal Oscillator Control - 0x00000000 - - - ENABLE - On power-up this field is initialised to DISABLE and the chip runs from the ROSC. - If the chip has subsequently been programmed to run from the XOSC then DISABLE may lock-up the chip. If this is a concern then run the clk_ref from the ROSC and enable the clk_sys RESUS feature. - The 12-bit code is intended to give some protection against accidental writes. An invalid setting will enable the oscillator. - [23:12] - read-write - - - DISABLE - 3358 - - - ENABLE - 4011 - - - - - FREQ_RANGE - Frequency range. An invalid setting will retain the previous value. The actual value being used can be read from STATUS_FREQ_RANGE. This resets to 0xAA0 and cannot be changed. - [11:0] - read-write - - - 1_15MHZ - 2720 - - - RESERVED_1 - 2721 - - - RESERVED_2 - 2722 - - - RESERVED_3 - 2723 - - - - - - - STATUS - 0x00000004 - Crystal Oscillator Status - 0x00000000 - - - STABLE - Oscillator is running and stable - [31:31] - read-only - - - BADWRITE - An invalid value has been written to CTRL_ENABLE or CTRL_FREQ_RANGE or DORMANT - [24:24] - read-write - oneToClear - - - ENABLED - Oscillator is enabled but not necessarily running and stable, resets to 0 - [12:12] - read-only - - - FREQ_RANGE - The current frequency range setting, always reads 0 - [1:0] - read-only - - - 1_15MHZ - 0 - - - RESERVED_1 - 1 - - - RESERVED_2 - 2 - - - RESERVED_3 - 3 - - - - - - - DORMANT - 0x00000008 - Crystal Oscillator pause control - 0x00000000 - - - DORMANT - This is used to save power by pausing the XOSC - On power-up this field is initialised to WAKE - An invalid write will also select WAKE - Warning: stop the PLLs before selecting dormant mode - Warning: setup the irq before selecting dormant mode - [31:0] - read-write - - - dormant - 1668246881 - - - WAKE - 2002873189 - - - - - - - STARTUP - 0x0000000c - Controls the startup delay - 0x00000000 - - - X4 - Multiplies the startup_delay by 4. This is of little value to the user given that the delay can be programmed directly. - [20:20] - read-write - - - DELAY - in multiples of 256*xtal_period. The reset value of 0xc4 corresponds to approx 50 000 cycles. - [13:0] - read-write - - - - - COUNT - 0x0000001c - A down counter running at the xosc frequency which counts to zero and stops. - To start the counter write a non-zero value. - Can be used for short software pauses when setting up time sensitive hardware. - 0x00000000 - - - COUNT - [7:0] - read-write - - - - - - - PLL_SYS - 0x40028000 - - 0 - 16 - registers - - - - CS - 0x00000000 - Control and Status - GENERAL CONSTRAINTS: - Reference clock frequency min=5MHz, max=800MHz - Feedback divider min=16, max=320 - VCO frequency min=750MHz, max=1600MHz - 0x00000001 - - - LOCK - PLL is locked - [31:31] - read-only - - - BYPASS - Passes the reference clock to the output instead of the divided VCO. The VCO continues to run so the user can switch between the reference clock and the divided VCO but the output will glitch when doing so. - [8:8] - read-write - - - REFDIV - Divides the PLL input reference clock. - Behaviour is undefined for div=0. - PLL output will be unpredictable during refdiv changes, wait for lock=1 before using it. - [5:0] - read-write - - - - - PWR - 0x00000004 - Controls the PLL power modes. - 0x0000002d - - - VCOPD - PLL VCO powerdown - To save power set high when PLL output not required or bypass=1. - [5:5] - read-write - - - POSTDIVPD - PLL post divider powerdown - To save power set high when PLL output not required or bypass=1. - [3:3] - read-write - - - DSMPD - PLL DSM powerdown - Nothing is achieved by setting this low. - [2:2] - read-write - - - PD - PLL powerdown - To save power set high when PLL output not required. - [0:0] - read-write - - - - - FBDIV_INT - 0x00000008 - Feedback divisor - (note: this PLL does not support fractional division) - 0x00000000 - - - FBDIV_INT - see ctrl reg description for constraints - [11:0] - read-write - - - - - PRIM - 0x0000000c - Controls the PLL post dividers for the primary output - (note: this PLL does not have a secondary output) - the primary output is driven from VCO divided by postdiv1*postdiv2 - 0x00077000 - - - POSTDIV1 - divide by 1-7 - [18:16] - read-write - - - POSTDIV2 - divide by 1-7 - [14:12] - read-write - - - - - - - PLL_USB - 0x4002c000 - - - UART0 - 0x40034000 - - 0 - 4096 - registers - - - UART0_IRQ - 20 - - - - UARTDR - 0x00000000 - Data Register, UARTDR - 0x00000000 - - - OE - Overrun error. This bit is set to 1 if data is received and the receive FIFO is already full. This is cleared to 0 once there is an empty space in the FIFO and a new character can be written to it. - [11:11] - read-only - - - BE - Break error. This bit is set to 1 if a break condition was detected, indicating that the received data input was held LOW for longer than a full-word transmission time (defined as start, data, parity and stop bits). In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state), and the next valid start bit is received. - [10:10] - read-only - - - PE - Parity error. When set to 1, it indicates that the parity of the received data character does not match the parity that the EPS and SPS bits in the Line Control Register, UARTLCR_H. In FIFO mode, this error is associated with the character at the top of the FIFO. - [9:9] - read-only - - - FE - Framing error. When set to 1, it indicates that the received character did not have a valid stop bit (a valid stop bit is 1). In FIFO mode, this error is associated with the character at the top of the FIFO. - [8:8] - read-only - - - DATA - Receive (read) data character. Transmit (write) data character. - [7:0] - read-write - modify - - - - - UARTRSR - 0x00000004 - Receive Status Register/Error Clear Register, UARTRSR/UARTECR - 0x00000000 - - - OE - Overrun error. This bit is set to 1 if data is received and the FIFO is already full. This bit is cleared to 0 by a write to UARTECR. The FIFO contents remain valid because no more data is written when the FIFO is full, only the contents of the shift register are overwritten. The CPU must now read the data, to empty the FIFO. - [3:3] - read-write - oneToClear - - - BE - Break error. This bit is set to 1 if a break condition was detected, indicating that the received data input was held LOW for longer than a full-word transmission time (defined as start, data, parity, and stop bits). This bit is cleared to 0 after a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state) and the next valid start bit is received. - [2:2] - read-write - oneToClear - - - PE - Parity error. When set to 1, it indicates that the parity of the received data character does not match the parity that the EPS and SPS bits in the Line Control Register, UARTLCR_H. This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO. - [1:1] - read-write - oneToClear - - - FE - Framing error. When set to 1, it indicates that the received character did not have a valid stop bit (a valid stop bit is 1). This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO. - [0:0] - read-write - oneToClear - - - - - UARTFR - 0x00000018 - Flag Register, UARTFR - 0x00000090 - - - RI - Ring indicator. This bit is the complement of the UART ring indicator, nUARTRI, modem status input. That is, the bit is 1 when nUARTRI is LOW. - [8:8] - read-only - - - TXFE - Transmit FIFO empty. The meaning of this bit depends on the state of the FEN bit in the Line Control Register, UARTLCR_H. If the FIFO is disabled, this bit is set when the transmit holding register is empty. If the FIFO is enabled, the TXFE bit is set when the transmit FIFO is empty. This bit does not indicate if there is data in the transmit shift register. - [7:7] - read-only - - - RXFF - Receive FIFO full. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the receive holding register is full. If the FIFO is enabled, the RXFF bit is set when the receive FIFO is full. - [6:6] - read-only - - - TXFF - Transmit FIFO full. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the transmit holding register is full. If the FIFO is enabled, the TXFF bit is set when the transmit FIFO is full. - [5:5] - read-only - - - RXFE - Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the receive holding register is empty. If the FIFO is enabled, the RXFE bit is set when the receive FIFO is empty. - [4:4] - read-only - - - BUSY - UART busy. If this bit is set to 1, the UART is busy transmitting data. This bit remains set until the complete byte, including all the stop bits, has been sent from the shift register. This bit is set as soon as the transmit FIFO becomes non-empty, regardless of whether the UART is enabled or not. - [3:3] - read-only - - - DCD - Data carrier detect. This bit is the complement of the UART data carrier detect, nUARTDCD, modem status input. That is, the bit is 1 when nUARTDCD is LOW. - [2:2] - read-only - - - DSR - Data set ready. This bit is the complement of the UART data set ready, nUARTDSR, modem status input. That is, the bit is 1 when nUARTDSR is LOW. - [1:1] - read-only - - - CTS - Clear to send. This bit is the complement of the UART clear to send, nUARTCTS, modem status input. That is, the bit is 1 when nUARTCTS is LOW. - [0:0] - read-only - - - - - UARTILPR - 0x00000020 - IrDA Low-Power Counter Register, UARTILPR - 0x00000000 - - - ILPDVSR - 8-bit low-power divisor value. These bits are cleared to 0 at reset. - [7:0] - read-write - - - - - UARTIBRD - 0x00000024 - Integer Baud Rate Register, UARTIBRD - 0x00000000 - - - BAUD_DIVINT - The integer baud rate divisor. These bits are cleared to 0 on reset. - [15:0] - read-write - - - - - UARTFBRD - 0x00000028 - Fractional Baud Rate Register, UARTFBRD - 0x00000000 - - - BAUD_DIVFRAC - The fractional baud rate divisor. These bits are cleared to 0 on reset. - [5:0] - read-write - - - - - UARTLCR_H - 0x0000002c - Line Control Register, UARTLCR_H - 0x00000000 - - - SPS - Stick parity select. 0 = stick parity is disabled 1 = either: * if the EPS bit is 0 then the parity bit is transmitted and checked as a 1 * if the EPS bit is 1 then the parity bit is transmitted and checked as a 0. This bit has no effect when the PEN bit disables parity checking and generation. - [7:7] - read-write - - - WLEN - Word length. These bits indicate the number of data bits transmitted or received in a frame as follows: b11 = 8 bits b10 = 7 bits b01 = 6 bits b00 = 5 bits. - [6:5] - read-write - - - FEN - Enable FIFOs: 0 = FIFOs are disabled (character mode) that is, the FIFOs become 1-byte-deep holding registers 1 = transmit and receive FIFO buffers are enabled (FIFO mode). - [4:4] - read-write - - - STP2 - Two stop bits select. If this bit is set to 1, two stop bits are transmitted at the end of the frame. The receive logic does not check for two stop bits being received. - [3:3] - read-write - - - EPS - Even parity select. Controls the type of parity the UART uses during transmission and reception: 0 = odd parity. The UART generates or checks for an odd number of 1s in the data and parity bits. 1 = even parity. The UART generates or checks for an even number of 1s in the data and parity bits. This bit has no effect when the PEN bit disables parity checking and generation. - [2:2] - read-write - - - PEN - Parity enable: 0 = parity is disabled and no parity bit added to the data frame 1 = parity checking and generation is enabled. - [1:1] - read-write - - - BRK - Send break. If this bit is set to 1, a low-level is continually output on the UARTTXD output, after completing transmission of the current character. For the proper execution of the break command, the software must set this bit for at least two complete frames. For normal use, this bit must be cleared to 0. - [0:0] - read-write - - - - - UARTCR - 0x00000030 - Control Register, UARTCR - 0x00000300 - - - CTSEN - CTS hardware flow control enable. If this bit is set to 1, CTS hardware flow control is enabled. Data is only transmitted when the nUARTCTS signal is asserted. - [15:15] - read-write - - - RTSEN - RTS hardware flow control enable. If this bit is set to 1, RTS hardware flow control is enabled. Data is only requested when there is space in the receive FIFO for it to be received. - [14:14] - read-write - - - OUT2 - This bit is the complement of the UART Out2 (nUARTOut2) modem status output. That is, when the bit is programmed to a 1, the output is 0. For DTE this can be used as Ring Indicator (RI). - [13:13] - read-write - - - OUT1 - This bit is the complement of the UART Out1 (nUARTOut1) modem status output. That is, when the bit is programmed to a 1 the output is 0. For DTE this can be used as Data Carrier Detect (DCD). - [12:12] - read-write - - - RTS - Request to send. This bit is the complement of the UART request to send, nUARTRTS, modem status output. That is, when the bit is programmed to a 1 then nUARTRTS is LOW. - [11:11] - read-write - - - DTR - Data transmit ready. This bit is the complement of the UART data transmit ready, nUARTDTR, modem status output. That is, when the bit is programmed to a 1 then nUARTDTR is LOW. - [10:10] - read-write - - - RXE - Receive enable. If this bit is set to 1, the receive section of the UART is enabled. Data reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of reception, it completes the current character before stopping. - [9:9] - read-write - - - TXE - Transmit enable. If this bit is set to 1, the transmit section of the UART is enabled. Data transmission occurs for either UART signals, or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of transmission, it completes the current character before stopping. - [8:8] - read-write - - - LBE - Loopback enable. If this bit is set to 1 and the SIREN bit is set to 1 and the SIRTEST bit in the Test Control Register, UARTTCR is set to 1, then the nSIROUT path is inverted, and fed through to the SIRIN path. The SIRTEST bit in the test register must be set to 1 to override the normal half-duplex SIR operation. This must be the requirement for accessing the test registers during normal operation, and SIRTEST must be cleared to 0 when loopback testing is finished. This feature reduces the amount of external coupling required during system test. If this bit is set to 1, and the SIRTEST bit is set to 0, the UARTTXD path is fed through to the UARTRXD path. In either SIR mode or UART mode, when this bit is set, the modem outputs are also fed through to the modem inputs. This bit is cleared to 0 on reset, to disable loopback. - [7:7] - read-write - - - SIRLP - SIR low-power IrDA mode. This bit selects the IrDA encoding mode. If this bit is cleared to 0, low-level bits are transmitted as an active high pulse with a width of 3 / 16th of the bit period. If this bit is set to 1, low-level bits are transmitted with a pulse width that is 3 times the period of the IrLPBaud16 input signal, regardless of the selected bit rate. Setting this bit uses less power, but might reduce transmission distances. - [2:2] - read-write - - - SIREN - SIR enable: 0 = IrDA SIR ENDEC is disabled. nSIROUT remains LOW (no light pulse generated), and signal transitions on SIRIN have no effect. 1 = IrDA SIR ENDEC is enabled. Data is transmitted and received on nSIROUT and SIRIN. UARTTXD remains HIGH, in the marking state. Signal transitions on UARTRXD or modem status inputs have no effect. This bit has no effect if the UARTEN bit disables the UART. - [1:1] - read-write - - - UARTEN - UART enable: 0 = UART is disabled. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. 1 = the UART is enabled. Data transmission and reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit. - [0:0] - read-write - - - - - UARTIFLS - 0x00000034 - Interrupt FIFO Level Select Register, UARTIFLS - 0x00000012 - - - RXIFLSEL - Receive interrupt FIFO level select. The trigger points for the receive interrupt are as follows: b000 = Receive FIFO becomes >= 1 / 8 full b001 = Receive FIFO becomes >= 1 / 4 full b010 = Receive FIFO becomes >= 1 / 2 full b011 = Receive FIFO becomes >= 3 / 4 full b100 = Receive FIFO becomes >= 7 / 8 full b101-b111 = reserved. - [5:3] - read-write - - - TXIFLSEL - Transmit interrupt FIFO level select. The trigger points for the transmit interrupt are as follows: b000 = Transmit FIFO becomes <= 1 / 8 full b001 = Transmit FIFO becomes <= 1 / 4 full b010 = Transmit FIFO becomes <= 1 / 2 full b011 = Transmit FIFO becomes <= 3 / 4 full b100 = Transmit FIFO becomes <= 7 / 8 full b101-b111 = reserved. - [2:0] - read-write - - - - - UARTIMSC - 0x00000038 - Interrupt Mask Set/Clear Register, UARTIMSC - 0x00000000 - - - OEIM - Overrun error interrupt mask. A read returns the current mask for the UARTOEINTR interrupt. On a write of 1, the mask of the UARTOEINTR interrupt is set. A write of 0 clears the mask. - [10:10] - read-write - - - BEIM - Break error interrupt mask. A read returns the current mask for the UARTBEINTR interrupt. On a write of 1, the mask of the UARTBEINTR interrupt is set. A write of 0 clears the mask. - [9:9] - read-write - - - PEIM - Parity error interrupt mask. A read returns the current mask for the UARTPEINTR interrupt. On a write of 1, the mask of the UARTPEINTR interrupt is set. A write of 0 clears the mask. - [8:8] - read-write - - - FEIM - Framing error interrupt mask. A read returns the current mask for the UARTFEINTR interrupt. On a write of 1, the mask of the UARTFEINTR interrupt is set. A write of 0 clears the mask. - [7:7] - read-write - - - RTIM - Receive timeout interrupt mask. A read returns the current mask for the UARTRTINTR interrupt. On a write of 1, the mask of the UARTRTINTR interrupt is set. A write of 0 clears the mask. - [6:6] - read-write - - - TXIM - Transmit interrupt mask. A read returns the current mask for the UARTTXINTR interrupt. On a write of 1, the mask of the UARTTXINTR interrupt is set. A write of 0 clears the mask. - [5:5] - read-write - - - RXIM - Receive interrupt mask. A read returns the current mask for the UARTRXINTR interrupt. On a write of 1, the mask of the UARTRXINTR interrupt is set. A write of 0 clears the mask. - [4:4] - read-write - - - DSRMIM - nUARTDSR modem interrupt mask. A read returns the current mask for the UARTDSRINTR interrupt. On a write of 1, the mask of the UARTDSRINTR interrupt is set. A write of 0 clears the mask. - [3:3] - read-write - - - DCDMIM - nUARTDCD modem interrupt mask. A read returns the current mask for the UARTDCDINTR interrupt. On a write of 1, the mask of the UARTDCDINTR interrupt is set. A write of 0 clears the mask. - [2:2] - read-write - - - CTSMIM - nUARTCTS modem interrupt mask. A read returns the current mask for the UARTCTSINTR interrupt. On a write of 1, the mask of the UARTCTSINTR interrupt is set. A write of 0 clears the mask. - [1:1] - read-write - - - RIMIM - nUARTRI modem interrupt mask. A read returns the current mask for the UARTRIINTR interrupt. On a write of 1, the mask of the UARTRIINTR interrupt is set. A write of 0 clears the mask. - [0:0] - read-write - - - - - UARTRIS - 0x0000003c - Raw Interrupt Status Register, UARTRIS - 0x00000000 - - - OERIS - Overrun error interrupt status. Returns the raw interrupt state of the UARTOEINTR interrupt. - [10:10] - read-only - - - BERIS - Break error interrupt status. Returns the raw interrupt state of the UARTBEINTR interrupt. - [9:9] - read-only - - - PERIS - Parity error interrupt status. Returns the raw interrupt state of the UARTPEINTR interrupt. - [8:8] - read-only - - - FERIS - Framing error interrupt status. Returns the raw interrupt state of the UARTFEINTR interrupt. - [7:7] - read-only - - - RTRIS - Receive timeout interrupt status. Returns the raw interrupt state of the UARTRTINTR interrupt. a - [6:6] - read-only - - - TXRIS - Transmit interrupt status. Returns the raw interrupt state of the UARTTXINTR interrupt. - [5:5] - read-only - - - RXRIS - Receive interrupt status. Returns the raw interrupt state of the UARTRXINTR interrupt. - [4:4] - read-only - - - DSRRMIS - nUARTDSR modem interrupt status. Returns the raw interrupt state of the UARTDSRINTR interrupt. - [3:3] - read-only - - - DCDRMIS - nUARTDCD modem interrupt status. Returns the raw interrupt state of the UARTDCDINTR interrupt. - [2:2] - read-only - - - CTSRMIS - nUARTCTS modem interrupt status. Returns the raw interrupt state of the UARTCTSINTR interrupt. - [1:1] - read-only - - - RIRMIS - nUARTRI modem interrupt status. Returns the raw interrupt state of the UARTRIINTR interrupt. - [0:0] - read-only - - - - - UARTMIS - 0x00000040 - Masked Interrupt Status Register, UARTMIS - 0x00000000 - - - OEMIS - Overrun error masked interrupt status. Returns the masked interrupt state of the UARTOEINTR interrupt. - [10:10] - read-only - - - BEMIS - Break error masked interrupt status. Returns the masked interrupt state of the UARTBEINTR interrupt. - [9:9] - read-only - - - PEMIS - Parity error masked interrupt status. Returns the masked interrupt state of the UARTPEINTR interrupt. - [8:8] - read-only - - - FEMIS - Framing error masked interrupt status. Returns the masked interrupt state of the UARTFEINTR interrupt. - [7:7] - read-only - - - RTMIS - Receive timeout masked interrupt status. Returns the masked interrupt state of the UARTRTINTR interrupt. - [6:6] - read-only - - - TXMIS - Transmit masked interrupt status. Returns the masked interrupt state of the UARTTXINTR interrupt. - [5:5] - read-only - - - RXMIS - Receive masked interrupt status. Returns the masked interrupt state of the UARTRXINTR interrupt. - [4:4] - read-only - - - DSRMMIS - nUARTDSR modem masked interrupt status. Returns the masked interrupt state of the UARTDSRINTR interrupt. - [3:3] - read-only - - - DCDMMIS - nUARTDCD modem masked interrupt status. Returns the masked interrupt state of the UARTDCDINTR interrupt. - [2:2] - read-only - - - CTSMMIS - nUARTCTS modem masked interrupt status. Returns the masked interrupt state of the UARTCTSINTR interrupt. - [1:1] - read-only - - - RIMMIS - nUARTRI modem masked interrupt status. Returns the masked interrupt state of the UARTRIINTR interrupt. - [0:0] - read-only - - - - - UARTICR - 0x00000044 - Interrupt Clear Register, UARTICR - 0x00000000 - - - OEIC - Overrun error interrupt clear. Clears the UARTOEINTR interrupt. - [10:10] - read-write - oneToClear - - - BEIC - Break error interrupt clear. Clears the UARTBEINTR interrupt. - [9:9] - read-write - oneToClear - - - PEIC - Parity error interrupt clear. Clears the UARTPEINTR interrupt. - [8:8] - read-write - oneToClear - - - FEIC - Framing error interrupt clear. Clears the UARTFEINTR interrupt. - [7:7] - read-write - oneToClear - - - RTIC - Receive timeout interrupt clear. Clears the UARTRTINTR interrupt. - [6:6] - read-write - oneToClear - - - TXIC - Transmit interrupt clear. Clears the UARTTXINTR interrupt. - [5:5] - read-write - oneToClear - - - RXIC - Receive interrupt clear. Clears the UARTRXINTR interrupt. - [4:4] - read-write - oneToClear - - - DSRMIC - nUARTDSR modem interrupt clear. Clears the UARTDSRINTR interrupt. - [3:3] - read-write - oneToClear - - - DCDMIC - nUARTDCD modem interrupt clear. Clears the UARTDCDINTR interrupt. - [2:2] - read-write - oneToClear - - - CTSMIC - nUARTCTS modem interrupt clear. Clears the UARTCTSINTR interrupt. - [1:1] - read-write - oneToClear - - - RIMIC - nUARTRI modem interrupt clear. Clears the UARTRIINTR interrupt. - [0:0] - read-write - oneToClear - - - - - UARTDMACR - 0x00000048 - DMA Control Register, UARTDMACR - 0x00000000 - - - DMAONERR - DMA on error. If this bit is set to 1, the DMA receive request outputs, UARTRXDMASREQ or UARTRXDMABREQ, are disabled when the UART error interrupt is asserted. - [2:2] - read-write - - - TXDMAE - Transmit DMA enable. If this bit is set to 1, DMA for the transmit FIFO is enabled. - [1:1] - read-write - - - RXDMAE - Receive DMA enable. If this bit is set to 1, DMA for the receive FIFO is enabled. - [0:0] - read-write - - - - - UARTPERIPHID0 - 0x00000fe0 - UARTPeriphID0 Register - 0x00000011 - - - PARTNUMBER0 - These bits read back as 0x11 - [7:0] - read-only - - - - - UARTPERIPHID1 - 0x00000fe4 - UARTPeriphID1 Register - 0x00000010 - - - DESIGNER0 - These bits read back as 0x1 - [7:4] - read-only - - - PARTNUMBER1 - These bits read back as 0x0 - [3:0] - read-only - - - - - UARTPERIPHID2 - 0x00000fe8 - UARTPeriphID2 Register - 0x00000034 - - - REVISION - This field depends on the revision of the UART: r1p0 0x0 r1p1 0x1 r1p3 0x2 r1p4 0x2 r1p5 0x3 - [7:4] - read-only - - - DESIGNER1 - These bits read back as 0x4 - [3:0] - read-only - - - - - UARTPERIPHID3 - 0x00000fec - UARTPeriphID3 Register - 0x00000000 - - - CONFIGURATION - These bits read back as 0x00 - [7:0] - read-only - - - - - UARTPCELLID0 - 0x00000ff0 - UARTPCellID0 Register - 0x0000000d - - - UARTPCELLID0 - These bits read back as 0x0D - [7:0] - read-only - - - - - UARTPCELLID1 - 0x00000ff4 - UARTPCellID1 Register - 0x000000f0 - - - UARTPCELLID1 - These bits read back as 0xF0 - [7:0] - read-only - - - - - UARTPCELLID2 - 0x00000ff8 - UARTPCellID2 Register - 0x00000005 - - - UARTPCELLID2 - These bits read back as 0x05 - [7:0] - read-only - - - - - UARTPCELLID3 - 0x00000ffc - UARTPCellID3 Register - 0x000000b1 - - - UARTPCELLID3 - These bits read back as 0xB1 - [7:0] - read-only - - - - - - - UART1 - 0x40038000 - - UART1_IRQ - 21 - - - - ROSC - 0x40060000 - - 0 - 36 - registers - - - - CTRL - 0x00000000 - Ring Oscillator control - 0x00000aa0 - - - ENABLE - On power-up this field is initialised to ENABLE - The system clock must be switched to another source before setting this field to DISABLE otherwise the chip will lock up - The 12-bit code is intended to give some protection against accidental writes. An invalid setting will enable the oscillator. - [23:12] - read-write - - - DISABLE - 3358 - - - ENABLE - 4011 - - - - - FREQ_RANGE - Controls the number of delay stages in the ROSC ring - LOW uses stages 0 to 7 - MEDIUM uses stages 2 to 7 - HIGH uses stages 4 to 7 - TOOHIGH uses stages 6 to 7 and should not be used because its frequency exceeds design specifications - The clock output will not glitch when changing the range up one step at a time - The clock output will glitch when changing the range down - Note: the values here are gray coded which is why HIGH comes before TOOHIGH - [11:0] - read-write - - - LOW - 4004 - - - MEDIUM - 4005 - - - HIGH - 4007 - - - TOOHIGH - 4006 - - - - - - - FREQA - 0x00000004 - The FREQA & FREQB registers control the frequency by controlling the drive strength of each stage - The drive strength has 4 levels determined by the number of bits set - Increasing the number of bits set increases the drive strength and increases the oscillation frequency - 0 bits set is the default drive strength - 1 bit set doubles the drive strength - 2 bits set triples drive strength - 3 bits set quadruples drive strength - 0x00000000 - - - PASSWD - Set to 0x9696 to apply the settings - Any other value in this field will set all drive strengths to 0 - [31:16] - read-write - - - PASS - 38550 - - - - - DS3 - Stage 3 drive strength - [14:12] - read-write - - - DS2 - Stage 2 drive strength - [10:8] - read-write - - - DS1 - Stage 1 drive strength - [6:4] - read-write - - - DS0 - Stage 0 drive strength - [2:0] - read-write - - - - - FREQB - 0x00000008 - For a detailed description see freqa register - 0x00000000 - - - PASSWD - Set to 0x9696 to apply the settings - Any other value in this field will set all drive strengths to 0 - [31:16] - read-write - - - PASS - 38550 - - - - - DS7 - Stage 7 drive strength - [14:12] - read-write - - - DS6 - Stage 6 drive strength - [10:8] - read-write - - - DS5 - Stage 5 drive strength - [6:4] - read-write - - - DS4 - Stage 4 drive strength - [2:0] - read-write - - - - - DORMANT - 0x0000000c - Ring Oscillator pause control - 0x00000000 - - - DORMANT - This is used to save power by pausing the ROSC - On power-up this field is initialised to WAKE - An invalid write will also select WAKE - Warning: setup the irq before selecting dormant mode - [31:0] - read-write - - - dormant - 1668246881 - - - WAKE - 2002873189 - - - - - - - DIV - 0x00000010 - Controls the output divider - 0x00000000 - - - DIV - set to 0xaa0 + div where - div = 0 divides by 32 - div = 1-31 divides by div - any other value sets div=31 - this register resets to div=16 - [11:0] - read-write - - - PASS - 2720 - - - - - - - PHASE - 0x00000014 - Controls the phase shifted output - 0x00000008 - - - PASSWD - set to 0xaa - any other value enables the output with shift=0 - [11:4] - read-write - - - ENABLE - enable the phase-shifted output - this can be changed on-the-fly - [3:3] - read-write - - - FLIP - invert the phase-shifted output - this is ignored when div=1 - [2:2] - read-write - - - SHIFT - phase shift the phase-shifted output by SHIFT input clocks - this can be changed on-the-fly - must be set to 0 before setting div=1 - [1:0] - read-write - - - - - STATUS - 0x00000018 - Ring Oscillator Status - 0x00000000 - - - STABLE - Oscillator is running and stable - [31:31] - read-only - - - BADWRITE - An invalid value has been written to CTRL_ENABLE or CTRL_FREQ_RANGE or FREQA or FREQB or DIV or PHASE or DORMANT - [24:24] - read-write - oneToClear - - - DIV_RUNNING - post-divider is running - this resets to 0 but transitions to 1 during chip startup - [16:16] - read-only - - - ENABLED - Oscillator is enabled but not necessarily running and stable - this resets to 0 but transitions to 1 during chip startup - [12:12] - read-only - - - - - RANDOMBIT - 0x0000001c - This just reads the state of the oscillator output so randomness is compromised if the ring oscillator is stopped or run at a harmonic of the bus frequency - 0x00000001 - - - RANDOMBIT - [0:0] - read-only - - - - - COUNT - 0x00000020 - A down counter running at the ROSC frequency which counts to zero and stops. - To start the counter write a non-zero value. - Can be used for short software pauses when setting up time sensitive hardware. - 0x00000000 - - - COUNT - [7:0] - read-write - - - - - - - WATCHDOG - 0x40058000 - - 0 - 48 - registers - - - - CTRL - 0x00000000 - Watchdog control - The rst_wdsel register determines which subsystems are reset when the watchdog is triggered. - The watchdog can be triggered in software. - 0x07000000 - - - TRIGGER - Trigger a watchdog reset - [31:31] - write-only - - - ENABLE - When not enabled the watchdog timer is paused - [30:30] - read-write - - - PAUSE_DBG1 - Pause the watchdog timer when processor 1 is in debug mode - [26:26] - read-write - - - PAUSE_DBG0 - Pause the watchdog timer when processor 0 is in debug mode - [25:25] - read-write - - - PAUSE_JTAG - Pause the watchdog timer when JTAG is accessing the bus fabric - [24:24] - read-write - - - TIME - Indicates the number of ticks / 2 (see errata RP2040-E1) before a watchdog reset will be triggered - [23:0] - read-only - - - - - LOAD - 0x00000004 - Load the watchdog timer. The maximum setting is 0xffffff which corresponds to 0xffffff / 2 ticks before triggering a watchdog reset (see errata RP2040-E1). - 0x00000000 - - - LOAD - [23:0] - write-only - - - - - REASON - 0x00000008 - Logs the reason for the last reset. Both bits are zero for the case of a hardware reset. - 0x00000000 - - - FORCE - [1:1] - read-only - - - TIMER - [0:0] - read-only - - - - - SCRATCH0 - 0x0000000c - Scratch register. Information persists through soft reset of the chip. - 0x00000000 - - - SCRATCH0 - [31:0] - read-write - - - - - SCRATCH1 - 0x00000010 - Scratch register. Information persists through soft reset of the chip. - 0x00000000 - - - SCRATCH1 - [31:0] - read-write - - - - - SCRATCH2 - 0x00000014 - Scratch register. Information persists through soft reset of the chip. - 0x00000000 - - - SCRATCH2 - [31:0] - read-write - - - - - SCRATCH3 - 0x00000018 - Scratch register. Information persists through soft reset of the chip. - 0x00000000 - - - SCRATCH3 - [31:0] - read-write - - - - - SCRATCH4 - 0x0000001c - Scratch register. Information persists through soft reset of the chip. - 0x00000000 - - - SCRATCH4 - [31:0] - read-write - - - - - SCRATCH5 - 0x00000020 - Scratch register. Information persists through soft reset of the chip. - 0x00000000 - - - SCRATCH5 - [31:0] - read-write - - - - - SCRATCH6 - 0x00000024 - Scratch register. Information persists through soft reset of the chip. - 0x00000000 - - - SCRATCH6 - [31:0] - read-write - - - - - SCRATCH7 - 0x00000028 - Scratch register. Information persists through soft reset of the chip. - 0x00000000 - - - SCRATCH7 - [31:0] - read-write - - - - - TICK - 0x0000002c - Controls the tick generator - 0x00000200 - - - COUNT - Count down timer: the remaining number clk_tick cycles before the next tick is generated. - [19:11] - read-only - - - RUNNING - Is the tick generator running? - [10:10] - read-only - - - ENABLE - start / stop tick generation - [9:9] - read-write - - - CYCLES - Total number of clk_tick cycles before the next tick. - [8:0] - read-write - - - - - - - DMA - DMA with separate read and write masters - 0x50000000 - - 0 - 2760 - registers - - - DMA_IRQ_0 - 11 - - - DMA_IRQ_1 - 12 - - - - CH0_READ_ADDR - 0x00000000 - DMA Channel 0 Read Address pointer - 0x00000000 - - - CH0_READ_ADDR - This register updates automatically each time a read completes. The current value is the next address to be read by this channel. - [31:0] - read-write - - - - - CH0_WRITE_ADDR - 0x00000004 - DMA Channel 0 Write Address pointer - 0x00000000 - - - CH0_WRITE_ADDR - This register updates automatically each time a write completes. The current value is the next address to be written by this channel. - [31:0] - read-write - - - - - CH0_TRANS_COUNT - 0x00000008 - DMA Channel 0 Transfer Count - 0x00000000 - - - CH0_TRANS_COUNT - Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). - - When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. - - Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. - - The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. - [31:0] - read-write - - - - - CH0_CTRL_TRIG - 0x0000000c - DMA Channel 0 Control and Status - 0x00000000 - - - AHB_ERROR - Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. - [31:31] - read-only - - - READ_ERROR - If 1, the channel received a read bus error. Write one to clear. - READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) - [30:30] - read-write - oneToClear - - - WRITE_ERROR - If 1, the channel received a write bus error. Write one to clear. - WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) - [29:29] - read-write - oneToClear - - - BUSY - This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. - - To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. - [24:24] - read-only - - - SNIFF_EN - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. - - This allows checksum to be enabled or disabled on a per-control- block basis. - [23:23] - read-write - - - BSWAP - Apply byte-swap transformation to DMA data. - For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. - [22:22] - read-write - - - IRQ_QUIET - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. - - This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. - [21:21] - read-write - - - TREQ_SEL - Select a Transfer Request signal. - The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). - 0x0 to 0x3a -> select DREQ n as TREQ - [20:15] - read-write - - - PIO0_TX0 - 0 - Select PIO0's TX FIFO 0 as TREQ - - - PIO0_TX1 - 1 - Select PIO0's TX FIFO 1 as TREQ - - - PIO0_TX2 - 2 - Select PIO0's TX FIFO 2 as TREQ - - - PIO0_TX3 - 3 - Select PIO0's TX FIFO 3 as TREQ - - - PIO0_RX0 - 4 - Select PIO0's RX FIFO 0 as TREQ - - - PIO0_RX1 - 5 - Select PIO0's RX FIFO 1 as TREQ - - - PIO0_RX2 - 6 - Select PIO0's RX FIFO 2 as TREQ - - - PIO0_RX3 - 7 - Select PIO0's RX FIFO 3 as TREQ - - - PIO1_TX0 - 8 - Select PIO1's TX FIFO 0 as TREQ - - - PIO1_TX1 - 9 - Select PIO1's TX FIFO 1 as TREQ - - - PIO1_TX2 - 10 - Select PIO1's TX FIFO 2 as TREQ - - - PIO1_TX3 - 11 - Select PIO1's TX FIFO 3 as TREQ - - - PIO1_RX0 - 12 - Select PIO1's RX FIFO 0 as TREQ - - - PIO1_RX1 - 13 - Select PIO1's RX FIFO 1 as TREQ - - - PIO1_RX2 - 14 - Select PIO1's RX FIFO 2 as TREQ - - - PIO1_RX3 - 15 - Select PIO1's RX FIFO 3 as TREQ - - - SPI0_TX - 16 - Select SPI0's TX FIFO as TREQ - - - SPI0_RX - 17 - Select SPI0's RX FIFO as TREQ - - - SPI1_TX - 18 - Select SPI1's TX FIFO as TREQ - - - SPI1_RX - 19 - Select SPI1's RX FIFO as TREQ - - - UART0_TX - 20 - Select UART0's TX FIFO as TREQ - - - UART0_RX - 21 - Select UART0's RX FIFO as TREQ - - - UART1_TX - 22 - Select UART1's TX FIFO as TREQ - - - UART1_RX - 23 - Select UART1's RX FIFO as TREQ - - - PWM_WRAP0 - 24 - Select PWM Counter 0's Wrap Value as TREQ - - - PWM_WRAP1 - 25 - Select PWM Counter 1's Wrap Value as TREQ - - - PWM_WRAP2 - 26 - Select PWM Counter 2's Wrap Value as TREQ - - - PWM_WRAP3 - 27 - Select PWM Counter 3's Wrap Value as TREQ - - - PWM_WRAP4 - 28 - Select PWM Counter 4's Wrap Value as TREQ - - - PWM_WRAP5 - 29 - Select PWM Counter 5's Wrap Value as TREQ - - - PWM_WRAP6 - 30 - Select PWM Counter 6's Wrap Value as TREQ - - - PWM_WRAP7 - 31 - Select PWM Counter 7's Wrap Value as TREQ - - - I2C0_TX - 32 - Select I2C0's TX FIFO as TREQ - - - I2C0_RX - 33 - Select I2C0's RX FIFO as TREQ - - - I2C1_TX - 34 - Select I2C1's TX FIFO as TREQ - - - I2C1_RX - 35 - Select I2C1's RX FIFO as TREQ - - - ADC - 36 - Select the ADC as TREQ - - - XIP_STREAM - 37 - Select the XIP Streaming FIFO as TREQ - - - XIP_SSITX - 38 - Select the XIP SSI TX FIFO as TREQ - - - XIP_SSIRX - 39 - Select the XIP SSI RX FIFO as TREQ - - - TIMER0 - 59 - Select Timer 0 as TREQ - - - TIMER1 - 60 - Select Timer 1 as TREQ - - - TIMER2 - 61 - Select Timer 2 as TREQ (Optional) - - - TIMER3 - 62 - Select Timer 3 as TREQ (Optional) - - - PERMANENT - 63 - Permanent request, for unpaced transfers. - - - - - CHAIN_TO - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. - [14:11] - read-write - - - RING_SEL - Select whether RING_SIZE applies to read or write addresses. - If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. - [10:10] - read-write - - - RING_SIZE - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. - - Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. - [9:6] - read-write - - - RING_NONE - 0 - - - - - INCR_WRITE - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. - - Generally this should be disabled for memory-to-peripheral transfers. - [5:5] - read-write - - - INCR_READ - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. - - Generally this should be disabled for peripheral-to-memory transfers. - [4:4] - read-write - - - DATA_SIZE - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. - [3:2] - read-write - - - SIZE_BYTE - 0 - - - SIZE_HALFWORD - 1 - - - SIZE_WORD - 2 - - - - - HIGH_PRIORITY - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. - - This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. - [1:1] - read-write - - - EN - DMA Channel Enable. - When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) - [0:0] - read-write - - - - - CH0_AL1_CTRL - 0x00000010 - Alias for channel 0 CTRL register - 0x00000000 - - - CH0_AL1_CTRL - [31:0] - read-write - - - - - CH0_AL1_READ_ADDR - 0x00000014 - Alias for channel 0 READ_ADDR register - 0x00000000 - - - CH0_AL1_READ_ADDR - [31:0] - read-write - - - - - CH0_AL1_WRITE_ADDR - 0x00000018 - Alias for channel 0 WRITE_ADDR register - 0x00000000 - - - CH0_AL1_WRITE_ADDR - [31:0] - read-write - - - - - CH0_AL1_TRANS_COUNT_TRIG - 0x0000001c - Alias for channel 0 TRANS_COUNT register - This is a trigger register (0xc). Writing a nonzero value will - reload the channel counter and start the channel. - 0x00000000 - - - CH0_AL1_TRANS_COUNT_TRIG - [31:0] - read-write - - - - - CH0_AL2_CTRL - 0x00000020 - Alias for channel 0 CTRL register - 0x00000000 - - - CH0_AL2_CTRL - [31:0] - read-write - - - - - CH0_AL2_TRANS_COUNT - 0x00000024 - Alias for channel 0 TRANS_COUNT register - 0x00000000 - - - CH0_AL2_TRANS_COUNT - [31:0] - read-write - - - - - CH0_AL2_READ_ADDR - 0x00000028 - Alias for channel 0 READ_ADDR register - 0x00000000 - - - CH0_AL2_READ_ADDR - [31:0] - read-write - - - - - CH0_AL2_WRITE_ADDR_TRIG - 0x0000002c - Alias for channel 0 WRITE_ADDR register - This is a trigger register (0xc). Writing a nonzero value will - reload the channel counter and start the channel. - 0x00000000 - - - CH0_AL2_WRITE_ADDR_TRIG - [31:0] - read-write - - - - - CH0_AL3_CTRL - 0x00000030 - Alias for channel 0 CTRL register - 0x00000000 - - - CH0_AL3_CTRL - [31:0] - read-write - - - - - CH0_AL3_WRITE_ADDR - 0x00000034 - Alias for channel 0 WRITE_ADDR register - 0x00000000 - - - CH0_AL3_WRITE_ADDR - [31:0] - read-write - - - - - CH0_AL3_TRANS_COUNT - 0x00000038 - Alias for channel 0 TRANS_COUNT register - 0x00000000 - - - CH0_AL3_TRANS_COUNT - [31:0] - read-write - - - - - CH0_AL3_READ_ADDR_TRIG - 0x0000003c - Alias for channel 0 READ_ADDR register - This is a trigger register (0xc). Writing a nonzero value will - reload the channel counter and start the channel. - 0x00000000 - - - CH0_AL3_READ_ADDR_TRIG - [31:0] - read-write - - - - - CH1_READ_ADDR - 0x00000040 - DMA Channel 1 Read Address pointer - 0x00000000 - - - CH1_READ_ADDR - This register updates automatically each time a read completes. The current value is the next address to be read by this channel. - [31:0] - read-write - - - - - CH1_WRITE_ADDR - 0x00000044 - DMA Channel 1 Write Address pointer - 0x00000000 - - - CH1_WRITE_ADDR - This register updates automatically each time a write completes. The current value is the next address to be written by this channel. - [31:0] - read-write - - - - - CH1_TRANS_COUNT - 0x00000048 - DMA Channel 1 Transfer Count - 0x00000000 - - - CH1_TRANS_COUNT - Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). - - When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. - - Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. - - The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. - [31:0] - read-write - - - - - CH1_CTRL_TRIG - 0x0000004c - DMA Channel 1 Control and Status - 0x00000000 - - - AHB_ERROR - Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. - [31:31] - read-only - - - READ_ERROR - If 1, the channel received a read bus error. Write one to clear. - READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) - [30:30] - read-write - oneToClear - - - WRITE_ERROR - If 1, the channel received a write bus error. Write one to clear. - WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) - [29:29] - read-write - oneToClear - - - BUSY - This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. - - To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. - [24:24] - read-only - - - SNIFF_EN - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. - - This allows checksum to be enabled or disabled on a per-control- block basis. - [23:23] - read-write - - - BSWAP - Apply byte-swap transformation to DMA data. - For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. - [22:22] - read-write - - - IRQ_QUIET - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. - - This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. - [21:21] - read-write - - - TREQ_SEL - Select a Transfer Request signal. - The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). - 0x0 to 0x3a -> select DREQ n as TREQ - [20:15] - read-write - - - PIO0_TX0 - 0 - Select PIO0's TX FIFO 0 as TREQ - - - PIO0_TX1 - 1 - Select PIO0's TX FIFO 1 as TREQ - - - PIO0_TX2 - 2 - Select PIO0's TX FIFO 2 as TREQ - - - PIO0_TX3 - 3 - Select PIO0's TX FIFO 3 as TREQ - - - PIO0_RX0 - 4 - Select PIO0's RX FIFO 0 as TREQ - - - PIO0_RX1 - 5 - Select PIO0's RX FIFO 1 as TREQ - - - PIO0_RX2 - 6 - Select PIO0's RX FIFO 2 as TREQ - - - PIO0_RX3 - 7 - Select PIO0's RX FIFO 3 as TREQ - - - PIO1_TX0 - 8 - Select PIO1's TX FIFO 0 as TREQ - - - PIO1_TX1 - 9 - Select PIO1's TX FIFO 1 as TREQ - - - PIO1_TX2 - 10 - Select PIO1's TX FIFO 2 as TREQ - - - PIO1_TX3 - 11 - Select PIO1's TX FIFO 3 as TREQ - - - PIO1_RX0 - 12 - Select PIO1's RX FIFO 0 as TREQ - - - PIO1_RX1 - 13 - Select PIO1's RX FIFO 1 as TREQ - - - PIO1_RX2 - 14 - Select PIO1's RX FIFO 2 as TREQ - - - PIO1_RX3 - 15 - Select PIO1's RX FIFO 3 as TREQ - - - SPI0_TX - 16 - Select SPI0's TX FIFO as TREQ - - - SPI0_RX - 17 - Select SPI0's RX FIFO as TREQ - - - SPI1_TX - 18 - Select SPI1's TX FIFO as TREQ - - - SPI1_RX - 19 - Select SPI1's RX FIFO as TREQ - - - UART0_TX - 20 - Select UART0's TX FIFO as TREQ - - - UART0_RX - 21 - Select UART0's RX FIFO as TREQ - - - UART1_TX - 22 - Select UART1's TX FIFO as TREQ - - - UART1_RX - 23 - Select UART1's RX FIFO as TREQ - - - PWM_WRAP0 - 24 - Select PWM Counter 0's Wrap Value as TREQ - - - PWM_WRAP1 - 25 - Select PWM Counter 1's Wrap Value as TREQ - - - PWM_WRAP2 - 26 - Select PWM Counter 2's Wrap Value as TREQ - - - PWM_WRAP3 - 27 - Select PWM Counter 3's Wrap Value as TREQ - - - PWM_WRAP4 - 28 - Select PWM Counter 4's Wrap Value as TREQ - - - PWM_WRAP5 - 29 - Select PWM Counter 5's Wrap Value as TREQ - - - PWM_WRAP6 - 30 - Select PWM Counter 6's Wrap Value as TREQ - - - PWM_WRAP7 - 31 - Select PWM Counter 7's Wrap Value as TREQ - - - I2C0_TX - 32 - Select I2C0's TX FIFO as TREQ - - - I2C0_RX - 33 - Select I2C0's RX FIFO as TREQ - - - I2C1_TX - 34 - Select I2C1's TX FIFO as TREQ - - - I2C1_RX - 35 - Select I2C1's RX FIFO as TREQ - - - ADC - 36 - Select the ADC as TREQ - - - XIP_STREAM - 37 - Select the XIP Streaming FIFO as TREQ - - - XIP_SSITX - 38 - Select the XIP SSI TX FIFO as TREQ - - - XIP_SSIRX - 39 - Select the XIP SSI RX FIFO as TREQ - - - TIMER0 - 59 - Select Timer 0 as TREQ - - - TIMER1 - 60 - Select Timer 1 as TREQ - - - TIMER2 - 61 - Select Timer 2 as TREQ (Optional) - - - TIMER3 - 62 - Select Timer 3 as TREQ (Optional) - - - PERMANENT - 63 - Permanent request, for unpaced transfers. - - - - - CHAIN_TO - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. - [14:11] - read-write - - - RING_SEL - Select whether RING_SIZE applies to read or write addresses. - If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. - [10:10] - read-write - - - RING_SIZE - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. - - Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. - [9:6] - read-write - - - RING_NONE - 0 - - - - - INCR_WRITE - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. - - Generally this should be disabled for memory-to-peripheral transfers. - [5:5] - read-write - - - INCR_READ - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. - - Generally this should be disabled for peripheral-to-memory transfers. - [4:4] - read-write - - - DATA_SIZE - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. - [3:2] - read-write - - - SIZE_BYTE - 0 - - - SIZE_HALFWORD - 1 - - - SIZE_WORD - 2 - - - - - HIGH_PRIORITY - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. - - This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. - [1:1] - read-write - - - EN - DMA Channel Enable. - When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) - [0:0] - read-write - - - - - CH1_AL1_CTRL - 0x00000050 - Alias for channel 1 CTRL register - 0x00000000 - - - CH1_AL1_CTRL - [31:0] - read-write - - - - - CH1_AL1_READ_ADDR - 0x00000054 - Alias for channel 1 READ_ADDR register - 0x00000000 - - - CH1_AL1_READ_ADDR - [31:0] - read-write - - - - - CH1_AL1_WRITE_ADDR - 0x00000058 - Alias for channel 1 WRITE_ADDR register - 0x00000000 - - - CH1_AL1_WRITE_ADDR - [31:0] - read-write - - - - - CH1_AL1_TRANS_COUNT_TRIG - 0x0000005c - Alias for channel 1 TRANS_COUNT register - This is a trigger register (0xc). Writing a nonzero value will - reload the channel counter and start the channel. - 0x00000000 - - - CH1_AL1_TRANS_COUNT_TRIG - [31:0] - read-write - - - - - CH1_AL2_CTRL - 0x00000060 - Alias for channel 1 CTRL register - 0x00000000 - - - CH1_AL2_CTRL - [31:0] - read-write - - - - - CH1_AL2_TRANS_COUNT - 0x00000064 - Alias for channel 1 TRANS_COUNT register - 0x00000000 - - - CH1_AL2_TRANS_COUNT - [31:0] - read-write - - - - - CH1_AL2_READ_ADDR - 0x00000068 - Alias for channel 1 READ_ADDR register - 0x00000000 - - - CH1_AL2_READ_ADDR - [31:0] - read-write - - - - - CH1_AL2_WRITE_ADDR_TRIG - 0x0000006c - Alias for channel 1 WRITE_ADDR register - This is a trigger register (0xc). Writing a nonzero value will - reload the channel counter and start the channel. - 0x00000000 - - - CH1_AL2_WRITE_ADDR_TRIG - [31:0] - read-write - - - - - CH1_AL3_CTRL - 0x00000070 - Alias for channel 1 CTRL register - 0x00000000 - - - CH1_AL3_CTRL - [31:0] - read-write - - - - - CH1_AL3_WRITE_ADDR - 0x00000074 - Alias for channel 1 WRITE_ADDR register - 0x00000000 - - - CH1_AL3_WRITE_ADDR - [31:0] - read-write - - - - - CH1_AL3_TRANS_COUNT - 0x00000078 - Alias for channel 1 TRANS_COUNT register - 0x00000000 - - - CH1_AL3_TRANS_COUNT - [31:0] - read-write - - - - - CH1_AL3_READ_ADDR_TRIG - 0x0000007c - Alias for channel 1 READ_ADDR register - This is a trigger register (0xc). Writing a nonzero value will - reload the channel counter and start the channel. - 0x00000000 - - - CH1_AL3_READ_ADDR_TRIG - [31:0] - read-write - - - - - CH2_READ_ADDR - 0x00000080 - DMA Channel 2 Read Address pointer - 0x00000000 - - - CH2_READ_ADDR - This register updates automatically each time a read completes. The current value is the next address to be read by this channel. - [31:0] - read-write - - - - - CH2_WRITE_ADDR - 0x00000084 - DMA Channel 2 Write Address pointer - 0x00000000 - - - CH2_WRITE_ADDR - This register updates automatically each time a write completes. The current value is the next address to be written by this channel. - [31:0] - read-write - - - - - CH2_TRANS_COUNT - 0x00000088 - DMA Channel 2 Transfer Count - 0x00000000 - - - CH2_TRANS_COUNT - Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). - - When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. - - Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. - - The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. - [31:0] - read-write - - - - - CH2_CTRL_TRIG - 0x0000008c - DMA Channel 2 Control and Status - 0x00000000 - - - AHB_ERROR - Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. - [31:31] - read-only - - - READ_ERROR - If 1, the channel received a read bus error. Write one to clear. - READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) - [30:30] - read-write - oneToClear - - - WRITE_ERROR - If 1, the channel received a write bus error. Write one to clear. - WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) - [29:29] - read-write - oneToClear - - - BUSY - This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. - - To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. - [24:24] - read-only - - - SNIFF_EN - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. - - This allows checksum to be enabled or disabled on a per-control- block basis. - [23:23] - read-write - - - BSWAP - Apply byte-swap transformation to DMA data. - For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. - [22:22] - read-write - - - IRQ_QUIET - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. - - This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. - [21:21] - read-write - - - TREQ_SEL - Select a Transfer Request signal. - The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). - 0x0 to 0x3a -> select DREQ n as TREQ - [20:15] - read-write - - - PIO0_TX0 - 0 - Select PIO0's TX FIFO 0 as TREQ - - - PIO0_TX1 - 1 - Select PIO0's TX FIFO 1 as TREQ - - - PIO0_TX2 - 2 - Select PIO0's TX FIFO 2 as TREQ - - - PIO0_TX3 - 3 - Select PIO0's TX FIFO 3 as TREQ - - - PIO0_RX0 - 4 - Select PIO0's RX FIFO 0 as TREQ - - - PIO0_RX1 - 5 - Select PIO0's RX FIFO 1 as TREQ - - - PIO0_RX2 - 6 - Select PIO0's RX FIFO 2 as TREQ - - - PIO0_RX3 - 7 - Select PIO0's RX FIFO 3 as TREQ - - - PIO1_TX0 - 8 - Select PIO1's TX FIFO 0 as TREQ - - - PIO1_TX1 - 9 - Select PIO1's TX FIFO 1 as TREQ - - - PIO1_TX2 - 10 - Select PIO1's TX FIFO 2 as TREQ - - - PIO1_TX3 - 11 - Select PIO1's TX FIFO 3 as TREQ - - - PIO1_RX0 - 12 - Select PIO1's RX FIFO 0 as TREQ - - - PIO1_RX1 - 13 - Select PIO1's RX FIFO 1 as TREQ - - - PIO1_RX2 - 14 - Select PIO1's RX FIFO 2 as TREQ - - - PIO1_RX3 - 15 - Select PIO1's RX FIFO 3 as TREQ - - - SPI0_TX - 16 - Select SPI0's TX FIFO as TREQ - - - SPI0_RX - 17 - Select SPI0's RX FIFO as TREQ - - - SPI1_TX - 18 - Select SPI1's TX FIFO as TREQ - - - SPI1_RX - 19 - Select SPI1's RX FIFO as TREQ - - - UART0_TX - 20 - Select UART0's TX FIFO as TREQ - - - UART0_RX - 21 - Select UART0's RX FIFO as TREQ - - - UART1_TX - 22 - Select UART1's TX FIFO as TREQ - - - UART1_RX - 23 - Select UART1's RX FIFO as TREQ - - - PWM_WRAP0 - 24 - Select PWM Counter 0's Wrap Value as TREQ - - - PWM_WRAP1 - 25 - Select PWM Counter 1's Wrap Value as TREQ - - - PWM_WRAP2 - 26 - Select PWM Counter 2's Wrap Value as TREQ - - - PWM_WRAP3 - 27 - Select PWM Counter 3's Wrap Value as TREQ - - - PWM_WRAP4 - 28 - Select PWM Counter 4's Wrap Value as TREQ - - - PWM_WRAP5 - 29 - Select PWM Counter 5's Wrap Value as TREQ - - - PWM_WRAP6 - 30 - Select PWM Counter 6's Wrap Value as TREQ - - - PWM_WRAP7 - 31 - Select PWM Counter 7's Wrap Value as TREQ - - - I2C0_TX - 32 - Select I2C0's TX FIFO as TREQ - - - I2C0_RX - 33 - Select I2C0's RX FIFO as TREQ - - - I2C1_TX - 34 - Select I2C1's TX FIFO as TREQ - - - I2C1_RX - 35 - Select I2C1's RX FIFO as TREQ - - - ADC - 36 - Select the ADC as TREQ - - - XIP_STREAM - 37 - Select the XIP Streaming FIFO as TREQ - - - XIP_SSITX - 38 - Select the XIP SSI TX FIFO as TREQ - - - XIP_SSIRX - 39 - Select the XIP SSI RX FIFO as TREQ - - - TIMER0 - 59 - Select Timer 0 as TREQ - - - TIMER1 - 60 - Select Timer 1 as TREQ - - - TIMER2 - 61 - Select Timer 2 as TREQ (Optional) - - - TIMER3 - 62 - Select Timer 3 as TREQ (Optional) - - - PERMANENT - 63 - Permanent request, for unpaced transfers. - - - - - CHAIN_TO - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. - [14:11] - read-write - - - RING_SEL - Select whether RING_SIZE applies to read or write addresses. - If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. - [10:10] - read-write - - - RING_SIZE - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. - - Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. - [9:6] - read-write - - - RING_NONE - 0 - - - - - INCR_WRITE - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. - - Generally this should be disabled for memory-to-peripheral transfers. - [5:5] - read-write - - - INCR_READ - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. - - Generally this should be disabled for peripheral-to-memory transfers. - [4:4] - read-write - - - DATA_SIZE - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. - [3:2] - read-write - - - SIZE_BYTE - 0 - - - SIZE_HALFWORD - 1 - - - SIZE_WORD - 2 - - - - - HIGH_PRIORITY - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. - - This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. - [1:1] - read-write - - - EN - DMA Channel Enable. - When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) - [0:0] - read-write - - - - - CH2_AL1_CTRL - 0x00000090 - Alias for channel 2 CTRL register - 0x00000000 - - - CH2_AL1_CTRL - [31:0] - read-write - - - - - CH2_AL1_READ_ADDR - 0x00000094 - Alias for channel 2 READ_ADDR register - 0x00000000 - - - CH2_AL1_READ_ADDR - [31:0] - read-write - - - - - CH2_AL1_WRITE_ADDR - 0x00000098 - Alias for channel 2 WRITE_ADDR register - 0x00000000 - - - CH2_AL1_WRITE_ADDR - [31:0] - read-write - - - - - CH2_AL1_TRANS_COUNT_TRIG - 0x0000009c - Alias for channel 2 TRANS_COUNT register - This is a trigger register (0xc). Writing a nonzero value will - reload the channel counter and start the channel. - 0x00000000 - - - CH2_AL1_TRANS_COUNT_TRIG - [31:0] - read-write - - - - - CH2_AL2_CTRL - 0x000000a0 - Alias for channel 2 CTRL register - 0x00000000 - - - CH2_AL2_CTRL - [31:0] - read-write - - - - - CH2_AL2_TRANS_COUNT - 0x000000a4 - Alias for channel 2 TRANS_COUNT register - 0x00000000 - - - CH2_AL2_TRANS_COUNT - [31:0] - read-write - - - - - CH2_AL2_READ_ADDR - 0x000000a8 - Alias for channel 2 READ_ADDR register - 0x00000000 - - - CH2_AL2_READ_ADDR - [31:0] - read-write - - - - - CH2_AL2_WRITE_ADDR_TRIG - 0x000000ac - Alias for channel 2 WRITE_ADDR register - This is a trigger register (0xc). Writing a nonzero value will - reload the channel counter and start the channel. - 0x00000000 - - - CH2_AL2_WRITE_ADDR_TRIG - [31:0] - read-write - - - - - CH2_AL3_CTRL - 0x000000b0 - Alias for channel 2 CTRL register - 0x00000000 - - - CH2_AL3_CTRL - [31:0] - read-write - - - - - CH2_AL3_WRITE_ADDR - 0x000000b4 - Alias for channel 2 WRITE_ADDR register - 0x00000000 - - - CH2_AL3_WRITE_ADDR - [31:0] - read-write - - - - - CH2_AL3_TRANS_COUNT - 0x000000b8 - Alias for channel 2 TRANS_COUNT register - 0x00000000 - - - CH2_AL3_TRANS_COUNT - [31:0] - read-write - - - - - CH2_AL3_READ_ADDR_TRIG - 0x000000bc - Alias for channel 2 READ_ADDR register - This is a trigger register (0xc). Writing a nonzero value will - reload the channel counter and start the channel. - 0x00000000 - - - CH2_AL3_READ_ADDR_TRIG - [31:0] - read-write - - - - - CH3_READ_ADDR - 0x000000c0 - DMA Channel 3 Read Address pointer - 0x00000000 - - - CH3_READ_ADDR - This register updates automatically each time a read completes. The current value is the next address to be read by this channel. - [31:0] - read-write - - - - - CH3_WRITE_ADDR - 0x000000c4 - DMA Channel 3 Write Address pointer - 0x00000000 - - - CH3_WRITE_ADDR - This register updates automatically each time a write completes. The current value is the next address to be written by this channel. - [31:0] - read-write - - - - - CH3_TRANS_COUNT - 0x000000c8 - DMA Channel 3 Transfer Count - 0x00000000 - - - CH3_TRANS_COUNT - Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). - - When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. - - Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. - - The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. - [31:0] - read-write - - - - - CH3_CTRL_TRIG - 0x000000cc - DMA Channel 3 Control and Status - 0x00000000 - - - AHB_ERROR - Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. - [31:31] - read-only - - - READ_ERROR - If 1, the channel received a read bus error. Write one to clear. - READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) - [30:30] - read-write - oneToClear - - - WRITE_ERROR - If 1, the channel received a write bus error. Write one to clear. - WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) - [29:29] - read-write - oneToClear - - - BUSY - This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. - - To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. - [24:24] - read-only - - - SNIFF_EN - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. - - This allows checksum to be enabled or disabled on a per-control- block basis. - [23:23] - read-write - - - BSWAP - Apply byte-swap transformation to DMA data. - For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. - [22:22] - read-write - - - IRQ_QUIET - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. - - This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. - [21:21] - read-write - - - TREQ_SEL - Select a Transfer Request signal. - The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). - 0x0 to 0x3a -> select DREQ n as TREQ - [20:15] - read-write - - - PIO0_TX0 - 0 - Select PIO0's TX FIFO 0 as TREQ - - - PIO0_TX1 - 1 - Select PIO0's TX FIFO 1 as TREQ - - - PIO0_TX2 - 2 - Select PIO0's TX FIFO 2 as TREQ - - - PIO0_TX3 - 3 - Select PIO0's TX FIFO 3 as TREQ - - - PIO0_RX0 - 4 - Select PIO0's RX FIFO 0 as TREQ - - - PIO0_RX1 - 5 - Select PIO0's RX FIFO 1 as TREQ - - - PIO0_RX2 - 6 - Select PIO0's RX FIFO 2 as TREQ - - - PIO0_RX3 - 7 - Select PIO0's RX FIFO 3 as TREQ - - - PIO1_TX0 - 8 - Select PIO1's TX FIFO 0 as TREQ - - - PIO1_TX1 - 9 - Select PIO1's TX FIFO 1 as TREQ - - - PIO1_TX2 - 10 - Select PIO1's TX FIFO 2 as TREQ - - - PIO1_TX3 - 11 - Select PIO1's TX FIFO 3 as TREQ - - - PIO1_RX0 - 12 - Select PIO1's RX FIFO 0 as TREQ - - - PIO1_RX1 - 13 - Select PIO1's RX FIFO 1 as TREQ - - - PIO1_RX2 - 14 - Select PIO1's RX FIFO 2 as TREQ - - - PIO1_RX3 - 15 - Select PIO1's RX FIFO 3 as TREQ - - - SPI0_TX - 16 - Select SPI0's TX FIFO as TREQ - - - SPI0_RX - 17 - Select SPI0's RX FIFO as TREQ - - - SPI1_TX - 18 - Select SPI1's TX FIFO as TREQ - - - SPI1_RX - 19 - Select SPI1's RX FIFO as TREQ - - - UART0_TX - 20 - Select UART0's TX FIFO as TREQ - - - UART0_RX - 21 - Select UART0's RX FIFO as TREQ - - - UART1_TX - 22 - Select UART1's TX FIFO as TREQ - - - UART1_RX - 23 - Select UART1's RX FIFO as TREQ - - - PWM_WRAP0 - 24 - Select PWM Counter 0's Wrap Value as TREQ - - - PWM_WRAP1 - 25 - Select PWM Counter 1's Wrap Value as TREQ - - - PWM_WRAP2 - 26 - Select PWM Counter 2's Wrap Value as TREQ - - - PWM_WRAP3 - 27 - Select PWM Counter 3's Wrap Value as TREQ - - - PWM_WRAP4 - 28 - Select PWM Counter 4's Wrap Value as TREQ - - - PWM_WRAP5 - 29 - Select PWM Counter 5's Wrap Value as TREQ - - - PWM_WRAP6 - 30 - Select PWM Counter 6's Wrap Value as TREQ - - - PWM_WRAP7 - 31 - Select PWM Counter 7's Wrap Value as TREQ - - - I2C0_TX - 32 - Select I2C0's TX FIFO as TREQ - - - I2C0_RX - 33 - Select I2C0's RX FIFO as TREQ - - - I2C1_TX - 34 - Select I2C1's TX FIFO as TREQ - - - I2C1_RX - 35 - Select I2C1's RX FIFO as TREQ - - - ADC - 36 - Select the ADC as TREQ - - - XIP_STREAM - 37 - Select the XIP Streaming FIFO as TREQ - - - XIP_SSITX - 38 - Select the XIP SSI TX FIFO as TREQ - - - XIP_SSIRX - 39 - Select the XIP SSI RX FIFO as TREQ - - - TIMER0 - 59 - Select Timer 0 as TREQ - - - TIMER1 - 60 - Select Timer 1 as TREQ - - - TIMER2 - 61 - Select Timer 2 as TREQ (Optional) - - - TIMER3 - 62 - Select Timer 3 as TREQ (Optional) - - - PERMANENT - 63 - Permanent request, for unpaced transfers. - - - - - CHAIN_TO - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. - [14:11] - read-write - - - RING_SEL - Select whether RING_SIZE applies to read or write addresses. - If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. - [10:10] - read-write - - - RING_SIZE - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. - - Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. - [9:6] - read-write - - - RING_NONE - 0 - - - - - INCR_WRITE - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. - - Generally this should be disabled for memory-to-peripheral transfers. - [5:5] - read-write - - - INCR_READ - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. - - Generally this should be disabled for peripheral-to-memory transfers. - [4:4] - read-write - - - DATA_SIZE - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. - [3:2] - read-write - - - SIZE_BYTE - 0 - - - SIZE_HALFWORD - 1 - - - SIZE_WORD - 2 - - - - - HIGH_PRIORITY - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. - - This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. - [1:1] - read-write - - - EN - DMA Channel Enable. - When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) - [0:0] - read-write - - - - - CH3_AL1_CTRL - 0x000000d0 - Alias for channel 3 CTRL register - 0x00000000 - - - CH3_AL1_CTRL - [31:0] - read-write - - - - - CH3_AL1_READ_ADDR - 0x000000d4 - Alias for channel 3 READ_ADDR register - 0x00000000 - - - CH3_AL1_READ_ADDR - [31:0] - read-write - - - - - CH3_AL1_WRITE_ADDR - 0x000000d8 - Alias for channel 3 WRITE_ADDR register - 0x00000000 - - - CH3_AL1_WRITE_ADDR - [31:0] - read-write - - - - - CH3_AL1_TRANS_COUNT_TRIG - 0x000000dc - Alias for channel 3 TRANS_COUNT register - This is a trigger register (0xc). Writing a nonzero value will - reload the channel counter and start the channel. - 0x00000000 - - - CH3_AL1_TRANS_COUNT_TRIG - [31:0] - read-write - - - - - CH3_AL2_CTRL - 0x000000e0 - Alias for channel 3 CTRL register - 0x00000000 - - - CH3_AL2_CTRL - [31:0] - read-write - - - - - CH3_AL2_TRANS_COUNT - 0x000000e4 - Alias for channel 3 TRANS_COUNT register - 0x00000000 - - - CH3_AL2_TRANS_COUNT - [31:0] - read-write - - - - - CH3_AL2_READ_ADDR - 0x000000e8 - Alias for channel 3 READ_ADDR register - 0x00000000 - - - CH3_AL2_READ_ADDR - [31:0] - read-write - - - - - CH3_AL2_WRITE_ADDR_TRIG - 0x000000ec - Alias for channel 3 WRITE_ADDR register - This is a trigger register (0xc). Writing a nonzero value will - reload the channel counter and start the channel. - 0x00000000 - - - CH3_AL2_WRITE_ADDR_TRIG - [31:0] - read-write - - - - - CH3_AL3_CTRL - 0x000000f0 - Alias for channel 3 CTRL register - 0x00000000 - - - CH3_AL3_CTRL - [31:0] - read-write - - - - - CH3_AL3_WRITE_ADDR - 0x000000f4 - Alias for channel 3 WRITE_ADDR register - 0x00000000 - - - CH3_AL3_WRITE_ADDR - [31:0] - read-write - - - - - CH3_AL3_TRANS_COUNT - 0x000000f8 - Alias for channel 3 TRANS_COUNT register - 0x00000000 - - - CH3_AL3_TRANS_COUNT - [31:0] - read-write - - - - - CH3_AL3_READ_ADDR_TRIG - 0x000000fc - Alias for channel 3 READ_ADDR register - This is a trigger register (0xc). Writing a nonzero value will - reload the channel counter and start the channel. - 0x00000000 - - - CH3_AL3_READ_ADDR_TRIG - [31:0] - read-write - - - - - CH4_READ_ADDR - 0x00000100 - DMA Channel 4 Read Address pointer - 0x00000000 - - - CH4_READ_ADDR - This register updates automatically each time a read completes. The current value is the next address to be read by this channel. - [31:0] - read-write - - - - - CH4_WRITE_ADDR - 0x00000104 - DMA Channel 4 Write Address pointer - 0x00000000 - - - CH4_WRITE_ADDR - This register updates automatically each time a write completes. The current value is the next address to be written by this channel. - [31:0] - read-write - - - - - CH4_TRANS_COUNT - 0x00000108 - DMA Channel 4 Transfer Count - 0x00000000 - - - CH4_TRANS_COUNT - Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). - - When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. - - Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. - - The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. - [31:0] - read-write - - - - - CH4_CTRL_TRIG - 0x0000010c - DMA Channel 4 Control and Status - 0x00000000 - - - AHB_ERROR - Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. - [31:31] - read-only - - - READ_ERROR - If 1, the channel received a read bus error. Write one to clear. - READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) - [30:30] - read-write - oneToClear - - - WRITE_ERROR - If 1, the channel received a write bus error. Write one to clear. - WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) - [29:29] - read-write - oneToClear - - - BUSY - This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. - - To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. - [24:24] - read-only - - - SNIFF_EN - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. - - This allows checksum to be enabled or disabled on a per-control- block basis. - [23:23] - read-write - - - BSWAP - Apply byte-swap transformation to DMA data. - For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. - [22:22] - read-write - - - IRQ_QUIET - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. - - This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. - [21:21] - read-write - - - TREQ_SEL - Select a Transfer Request signal. - The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). - 0x0 to 0x3a -> select DREQ n as TREQ - [20:15] - read-write - - - PIO0_TX0 - 0 - Select PIO0's TX FIFO 0 as TREQ - - - PIO0_TX1 - 1 - Select PIO0's TX FIFO 1 as TREQ - - - PIO0_TX2 - 2 - Select PIO0's TX FIFO 2 as TREQ - - - PIO0_TX3 - 3 - Select PIO0's TX FIFO 3 as TREQ - - - PIO0_RX0 - 4 - Select PIO0's RX FIFO 0 as TREQ - - - PIO0_RX1 - 5 - Select PIO0's RX FIFO 1 as TREQ - - - PIO0_RX2 - 6 - Select PIO0's RX FIFO 2 as TREQ - - - PIO0_RX3 - 7 - Select PIO0's RX FIFO 3 as TREQ - - - PIO1_TX0 - 8 - Select PIO1's TX FIFO 0 as TREQ - - - PIO1_TX1 - 9 - Select PIO1's TX FIFO 1 as TREQ - - - PIO1_TX2 - 10 - Select PIO1's TX FIFO 2 as TREQ - - - PIO1_TX3 - 11 - Select PIO1's TX FIFO 3 as TREQ - - - PIO1_RX0 - 12 - Select PIO1's RX FIFO 0 as TREQ - - - PIO1_RX1 - 13 - Select PIO1's RX FIFO 1 as TREQ - - - PIO1_RX2 - 14 - Select PIO1's RX FIFO 2 as TREQ - - - PIO1_RX3 - 15 - Select PIO1's RX FIFO 3 as TREQ - - - SPI0_TX - 16 - Select SPI0's TX FIFO as TREQ - - - SPI0_RX - 17 - Select SPI0's RX FIFO as TREQ - - - SPI1_TX - 18 - Select SPI1's TX FIFO as TREQ - - - SPI1_RX - 19 - Select SPI1's RX FIFO as TREQ - - - UART0_TX - 20 - Select UART0's TX FIFO as TREQ - - - UART0_RX - 21 - Select UART0's RX FIFO as TREQ - - - UART1_TX - 22 - Select UART1's TX FIFO as TREQ - - - UART1_RX - 23 - Select UART1's RX FIFO as TREQ - - - PWM_WRAP0 - 24 - Select PWM Counter 0's Wrap Value as TREQ - - - PWM_WRAP1 - 25 - Select PWM Counter 1's Wrap Value as TREQ - - - PWM_WRAP2 - 26 - Select PWM Counter 2's Wrap Value as TREQ - - - PWM_WRAP3 - 27 - Select PWM Counter 3's Wrap Value as TREQ - - - PWM_WRAP4 - 28 - Select PWM Counter 4's Wrap Value as TREQ - - - PWM_WRAP5 - 29 - Select PWM Counter 5's Wrap Value as TREQ - - - PWM_WRAP6 - 30 - Select PWM Counter 6's Wrap Value as TREQ - - - PWM_WRAP7 - 31 - Select PWM Counter 7's Wrap Value as TREQ - - - I2C0_TX - 32 - Select I2C0's TX FIFO as TREQ - - - I2C0_RX - 33 - Select I2C0's RX FIFO as TREQ - - - I2C1_TX - 34 - Select I2C1's TX FIFO as TREQ - - - I2C1_RX - 35 - Select I2C1's RX FIFO as TREQ - - - ADC - 36 - Select the ADC as TREQ - - - XIP_STREAM - 37 - Select the XIP Streaming FIFO as TREQ - - - XIP_SSITX - 38 - Select the XIP SSI TX FIFO as TREQ - - - XIP_SSIRX - 39 - Select the XIP SSI RX FIFO as TREQ - - - TIMER0 - 59 - Select Timer 0 as TREQ - - - TIMER1 - 60 - Select Timer 1 as TREQ - - - TIMER2 - 61 - Select Timer 2 as TREQ (Optional) - - - TIMER3 - 62 - Select Timer 3 as TREQ (Optional) - - - PERMANENT - 63 - Permanent request, for unpaced transfers. - - - - - CHAIN_TO - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. - [14:11] - read-write - - - RING_SEL - Select whether RING_SIZE applies to read or write addresses. - If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. - [10:10] - read-write - - - RING_SIZE - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. - - Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. - [9:6] - read-write - - - RING_NONE - 0 - - - - - INCR_WRITE - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. - - Generally this should be disabled for memory-to-peripheral transfers. - [5:5] - read-write - - - INCR_READ - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. - - Generally this should be disabled for peripheral-to-memory transfers. - [4:4] - read-write - - - DATA_SIZE - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. - [3:2] - read-write - - - SIZE_BYTE - 0 - - - SIZE_HALFWORD - 1 - - - SIZE_WORD - 2 - - - - - HIGH_PRIORITY - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. - - This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. - [1:1] - read-write - - - EN - DMA Channel Enable. - When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) - [0:0] - read-write - - - - - CH4_AL1_CTRL - 0x00000110 - Alias for channel 4 CTRL register - 0x00000000 - - - CH4_AL1_CTRL - [31:0] - read-write - - - - - CH4_AL1_READ_ADDR - 0x00000114 - Alias for channel 4 READ_ADDR register - 0x00000000 - - - CH4_AL1_READ_ADDR - [31:0] - read-write - - - - - CH4_AL1_WRITE_ADDR - 0x00000118 - Alias for channel 4 WRITE_ADDR register - 0x00000000 - - - CH4_AL1_WRITE_ADDR - [31:0] - read-write - - - - - CH4_AL1_TRANS_COUNT_TRIG - 0x0000011c - Alias for channel 4 TRANS_COUNT register - This is a trigger register (0xc). Writing a nonzero value will - reload the channel counter and start the channel. - 0x00000000 - - - CH4_AL1_TRANS_COUNT_TRIG - [31:0] - read-write - - - - - CH4_AL2_CTRL - 0x00000120 - Alias for channel 4 CTRL register - 0x00000000 - - - CH4_AL2_CTRL - [31:0] - read-write - - - - - CH4_AL2_TRANS_COUNT - 0x00000124 - Alias for channel 4 TRANS_COUNT register - 0x00000000 - - - CH4_AL2_TRANS_COUNT - [31:0] - read-write - - - - - CH4_AL2_READ_ADDR - 0x00000128 - Alias for channel 4 READ_ADDR register - 0x00000000 - - - CH4_AL2_READ_ADDR - [31:0] - read-write - - - - - CH4_AL2_WRITE_ADDR_TRIG - 0x0000012c - Alias for channel 4 WRITE_ADDR register - This is a trigger register (0xc). Writing a nonzero value will - reload the channel counter and start the channel. - 0x00000000 - - - CH4_AL2_WRITE_ADDR_TRIG - [31:0] - read-write - - - - - CH4_AL3_CTRL - 0x00000130 - Alias for channel 4 CTRL register - 0x00000000 - - - CH4_AL3_CTRL - [31:0] - read-write - - - - - CH4_AL3_WRITE_ADDR - 0x00000134 - Alias for channel 4 WRITE_ADDR register - 0x00000000 - - - CH4_AL3_WRITE_ADDR - [31:0] - read-write - - - - - CH4_AL3_TRANS_COUNT - 0x00000138 - Alias for channel 4 TRANS_COUNT register - 0x00000000 - - - CH4_AL3_TRANS_COUNT - [31:0] - read-write - - - - - CH4_AL3_READ_ADDR_TRIG - 0x0000013c - Alias for channel 4 READ_ADDR register - This is a trigger register (0xc). Writing a nonzero value will - reload the channel counter and start the channel. - 0x00000000 - - - CH4_AL3_READ_ADDR_TRIG - [31:0] - read-write - - - - - CH5_READ_ADDR - 0x00000140 - DMA Channel 5 Read Address pointer - 0x00000000 - - - CH5_READ_ADDR - This register updates automatically each time a read completes. The current value is the next address to be read by this channel. - [31:0] - read-write - - - - - CH5_WRITE_ADDR - 0x00000144 - DMA Channel 5 Write Address pointer - 0x00000000 - - - CH5_WRITE_ADDR - This register updates automatically each time a write completes. The current value is the next address to be written by this channel. - [31:0] - read-write - - - - - CH5_TRANS_COUNT - 0x00000148 - DMA Channel 5 Transfer Count - 0x00000000 - - - CH5_TRANS_COUNT - Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). - - When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. - - Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. - - The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. - [31:0] - read-write - - - - - CH5_CTRL_TRIG - 0x0000014c - DMA Channel 5 Control and Status - 0x00000000 - - - AHB_ERROR - Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. - [31:31] - read-only - - - READ_ERROR - If 1, the channel received a read bus error. Write one to clear. - READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) - [30:30] - read-write - oneToClear - - - WRITE_ERROR - If 1, the channel received a write bus error. Write one to clear. - WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) - [29:29] - read-write - oneToClear - - - BUSY - This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. - - To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. - [24:24] - read-only - - - SNIFF_EN - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. - - This allows checksum to be enabled or disabled on a per-control- block basis. - [23:23] - read-write - - - BSWAP - Apply byte-swap transformation to DMA data. - For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. - [22:22] - read-write - - - IRQ_QUIET - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. - - This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. - [21:21] - read-write - - - TREQ_SEL - Select a Transfer Request signal. - The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). - 0x0 to 0x3a -> select DREQ n as TREQ - [20:15] - read-write - - - PIO0_TX0 - 0 - Select PIO0's TX FIFO 0 as TREQ - - - PIO0_TX1 - 1 - Select PIO0's TX FIFO 1 as TREQ - - - PIO0_TX2 - 2 - Select PIO0's TX FIFO 2 as TREQ - - - PIO0_TX3 - 3 - Select PIO0's TX FIFO 3 as TREQ - - - PIO0_RX0 - 4 - Select PIO0's RX FIFO 0 as TREQ - - - PIO0_RX1 - 5 - Select PIO0's RX FIFO 1 as TREQ - - - PIO0_RX2 - 6 - Select PIO0's RX FIFO 2 as TREQ - - - PIO0_RX3 - 7 - Select PIO0's RX FIFO 3 as TREQ - - - PIO1_TX0 - 8 - Select PIO1's TX FIFO 0 as TREQ - - - PIO1_TX1 - 9 - Select PIO1's TX FIFO 1 as TREQ - - - PIO1_TX2 - 10 - Select PIO1's TX FIFO 2 as TREQ - - - PIO1_TX3 - 11 - Select PIO1's TX FIFO 3 as TREQ - - - PIO1_RX0 - 12 - Select PIO1's RX FIFO 0 as TREQ - - - PIO1_RX1 - 13 - Select PIO1's RX FIFO 1 as TREQ - - - PIO1_RX2 - 14 - Select PIO1's RX FIFO 2 as TREQ - - - PIO1_RX3 - 15 - Select PIO1's RX FIFO 3 as TREQ - - - SPI0_TX - 16 - Select SPI0's TX FIFO as TREQ - - - SPI0_RX - 17 - Select SPI0's RX FIFO as TREQ - - - SPI1_TX - 18 - Select SPI1's TX FIFO as TREQ - - - SPI1_RX - 19 - Select SPI1's RX FIFO as TREQ - - - UART0_TX - 20 - Select UART0's TX FIFO as TREQ - - - UART0_RX - 21 - Select UART0's RX FIFO as TREQ - - - UART1_TX - 22 - Select UART1's TX FIFO as TREQ - - - UART1_RX - 23 - Select UART1's RX FIFO as TREQ - - - PWM_WRAP0 - 24 - Select PWM Counter 0's Wrap Value as TREQ - - - PWM_WRAP1 - 25 - Select PWM Counter 1's Wrap Value as TREQ - - - PWM_WRAP2 - 26 - Select PWM Counter 2's Wrap Value as TREQ - - - PWM_WRAP3 - 27 - Select PWM Counter 3's Wrap Value as TREQ - - - PWM_WRAP4 - 28 - Select PWM Counter 4's Wrap Value as TREQ - - - PWM_WRAP5 - 29 - Select PWM Counter 5's Wrap Value as TREQ - - - PWM_WRAP6 - 30 - Select PWM Counter 6's Wrap Value as TREQ - - - PWM_WRAP7 - 31 - Select PWM Counter 7's Wrap Value as TREQ - - - I2C0_TX - 32 - Select I2C0's TX FIFO as TREQ - - - I2C0_RX - 33 - Select I2C0's RX FIFO as TREQ - - - I2C1_TX - 34 - Select I2C1's TX FIFO as TREQ - - - I2C1_RX - 35 - Select I2C1's RX FIFO as TREQ - - - ADC - 36 - Select the ADC as TREQ - - - XIP_STREAM - 37 - Select the XIP Streaming FIFO as TREQ - - - XIP_SSITX - 38 - Select the XIP SSI TX FIFO as TREQ - - - XIP_SSIRX - 39 - Select the XIP SSI RX FIFO as TREQ - - - TIMER0 - 59 - Select Timer 0 as TREQ - - - TIMER1 - 60 - Select Timer 1 as TREQ - - - TIMER2 - 61 - Select Timer 2 as TREQ (Optional) - - - TIMER3 - 62 - Select Timer 3 as TREQ (Optional) - - - PERMANENT - 63 - Permanent request, for unpaced transfers. - - - - - CHAIN_TO - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. - [14:11] - read-write - - - RING_SEL - Select whether RING_SIZE applies to read or write addresses. - If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. - [10:10] - read-write - - - RING_SIZE - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. - - Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. - [9:6] - read-write - - - RING_NONE - 0 - - - - - INCR_WRITE - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. - - Generally this should be disabled for memory-to-peripheral transfers. - [5:5] - read-write - - - INCR_READ - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. - - Generally this should be disabled for peripheral-to-memory transfers. - [4:4] - read-write - - - DATA_SIZE - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. - [3:2] - read-write - - - SIZE_BYTE - 0 - - - SIZE_HALFWORD - 1 - - - SIZE_WORD - 2 - - - - - HIGH_PRIORITY - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. - - This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. - [1:1] - read-write - - - EN - DMA Channel Enable. - When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) - [0:0] - read-write - - - - - CH5_AL1_CTRL - 0x00000150 - Alias for channel 5 CTRL register - 0x00000000 - - - CH5_AL1_CTRL - [31:0] - read-write - - - - - CH5_AL1_READ_ADDR - 0x00000154 - Alias for channel 5 READ_ADDR register - 0x00000000 - - - CH5_AL1_READ_ADDR - [31:0] - read-write - - - - - CH5_AL1_WRITE_ADDR - 0x00000158 - Alias for channel 5 WRITE_ADDR register - 0x00000000 - - - CH5_AL1_WRITE_ADDR - [31:0] - read-write - - - - - CH5_AL1_TRANS_COUNT_TRIG - 0x0000015c - Alias for channel 5 TRANS_COUNT register - This is a trigger register (0xc). Writing a nonzero value will - reload the channel counter and start the channel. - 0x00000000 - - - CH5_AL1_TRANS_COUNT_TRIG - [31:0] - read-write - - - - - CH5_AL2_CTRL - 0x00000160 - Alias for channel 5 CTRL register - 0x00000000 - - - CH5_AL2_CTRL - [31:0] - read-write - - - - - CH5_AL2_TRANS_COUNT - 0x00000164 - Alias for channel 5 TRANS_COUNT register - 0x00000000 - - - CH5_AL2_TRANS_COUNT - [31:0] - read-write - - - - - CH5_AL2_READ_ADDR - 0x00000168 - Alias for channel 5 READ_ADDR register - 0x00000000 - - - CH5_AL2_READ_ADDR - [31:0] - read-write - - - - - CH5_AL2_WRITE_ADDR_TRIG - 0x0000016c - Alias for channel 5 WRITE_ADDR register - This is a trigger register (0xc). Writing a nonzero value will - reload the channel counter and start the channel. - 0x00000000 - - - CH5_AL2_WRITE_ADDR_TRIG - [31:0] - read-write - - - - - CH5_AL3_CTRL - 0x00000170 - Alias for channel 5 CTRL register - 0x00000000 - - - CH5_AL3_CTRL - [31:0] - read-write - - - - - CH5_AL3_WRITE_ADDR - 0x00000174 - Alias for channel 5 WRITE_ADDR register - 0x00000000 - - - CH5_AL3_WRITE_ADDR - [31:0] - read-write - - - - - CH5_AL3_TRANS_COUNT - 0x00000178 - Alias for channel 5 TRANS_COUNT register - 0x00000000 - - - CH5_AL3_TRANS_COUNT - [31:0] - read-write - - - - - CH5_AL3_READ_ADDR_TRIG - 0x0000017c - Alias for channel 5 READ_ADDR register - This is a trigger register (0xc). Writing a nonzero value will - reload the channel counter and start the channel. - 0x00000000 - - - CH5_AL3_READ_ADDR_TRIG - [31:0] - read-write - - - - - CH6_READ_ADDR - 0x00000180 - DMA Channel 6 Read Address pointer - 0x00000000 - - - CH6_READ_ADDR - This register updates automatically each time a read completes. The current value is the next address to be read by this channel. - [31:0] - read-write - - - - - CH6_WRITE_ADDR - 0x00000184 - DMA Channel 6 Write Address pointer - 0x00000000 - - - CH6_WRITE_ADDR - This register updates automatically each time a write completes. The current value is the next address to be written by this channel. - [31:0] - read-write - - - - - CH6_TRANS_COUNT - 0x00000188 - DMA Channel 6 Transfer Count - 0x00000000 - - - CH6_TRANS_COUNT - Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). - - When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. - - Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. - - The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. - [31:0] - read-write - - - - - CH6_CTRL_TRIG - 0x0000018c - DMA Channel 6 Control and Status - 0x00000000 - - - AHB_ERROR - Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. - [31:31] - read-only - - - READ_ERROR - If 1, the channel received a read bus error. Write one to clear. - READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) - [30:30] - read-write - oneToClear - - - WRITE_ERROR - If 1, the channel received a write bus error. Write one to clear. - WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) - [29:29] - read-write - oneToClear - - - BUSY - This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. - - To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. - [24:24] - read-only - - - SNIFF_EN - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. - - This allows checksum to be enabled or disabled on a per-control- block basis. - [23:23] - read-write - - - BSWAP - Apply byte-swap transformation to DMA data. - For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. - [22:22] - read-write - - - IRQ_QUIET - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. - - This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. - [21:21] - read-write - - - TREQ_SEL - Select a Transfer Request signal. - The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). - 0x0 to 0x3a -> select DREQ n as TREQ - [20:15] - read-write - - - PIO0_TX0 - 0 - Select PIO0's TX FIFO 0 as TREQ - - - PIO0_TX1 - 1 - Select PIO0's TX FIFO 1 as TREQ - - - PIO0_TX2 - 2 - Select PIO0's TX FIFO 2 as TREQ - - - PIO0_TX3 - 3 - Select PIO0's TX FIFO 3 as TREQ - - - PIO0_RX0 - 4 - Select PIO0's RX FIFO 0 as TREQ - - - PIO0_RX1 - 5 - Select PIO0's RX FIFO 1 as TREQ - - - PIO0_RX2 - 6 - Select PIO0's RX FIFO 2 as TREQ - - - PIO0_RX3 - 7 - Select PIO0's RX FIFO 3 as TREQ - - - PIO1_TX0 - 8 - Select PIO1's TX FIFO 0 as TREQ - - - PIO1_TX1 - 9 - Select PIO1's TX FIFO 1 as TREQ - - - PIO1_TX2 - 10 - Select PIO1's TX FIFO 2 as TREQ - - - PIO1_TX3 - 11 - Select PIO1's TX FIFO 3 as TREQ - - - PIO1_RX0 - 12 - Select PIO1's RX FIFO 0 as TREQ - - - PIO1_RX1 - 13 - Select PIO1's RX FIFO 1 as TREQ - - - PIO1_RX2 - 14 - Select PIO1's RX FIFO 2 as TREQ - - - PIO1_RX3 - 15 - Select PIO1's RX FIFO 3 as TREQ - - - SPI0_TX - 16 - Select SPI0's TX FIFO as TREQ - - - SPI0_RX - 17 - Select SPI0's RX FIFO as TREQ - - - SPI1_TX - 18 - Select SPI1's TX FIFO as TREQ - - - SPI1_RX - 19 - Select SPI1's RX FIFO as TREQ - - - UART0_TX - 20 - Select UART0's TX FIFO as TREQ - - - UART0_RX - 21 - Select UART0's RX FIFO as TREQ - - - UART1_TX - 22 - Select UART1's TX FIFO as TREQ - - - UART1_RX - 23 - Select UART1's RX FIFO as TREQ - - - PWM_WRAP0 - 24 - Select PWM Counter 0's Wrap Value as TREQ - - - PWM_WRAP1 - 25 - Select PWM Counter 1's Wrap Value as TREQ - - - PWM_WRAP2 - 26 - Select PWM Counter 2's Wrap Value as TREQ - - - PWM_WRAP3 - 27 - Select PWM Counter 3's Wrap Value as TREQ - - - PWM_WRAP4 - 28 - Select PWM Counter 4's Wrap Value as TREQ - - - PWM_WRAP5 - 29 - Select PWM Counter 5's Wrap Value as TREQ - - - PWM_WRAP6 - 30 - Select PWM Counter 6's Wrap Value as TREQ - - - PWM_WRAP7 - 31 - Select PWM Counter 7's Wrap Value as TREQ - - - I2C0_TX - 32 - Select I2C0's TX FIFO as TREQ - - - I2C0_RX - 33 - Select I2C0's RX FIFO as TREQ - - - I2C1_TX - 34 - Select I2C1's TX FIFO as TREQ - - - I2C1_RX - 35 - Select I2C1's RX FIFO as TREQ - - - ADC - 36 - Select the ADC as TREQ - - - XIP_STREAM - 37 - Select the XIP Streaming FIFO as TREQ - - - XIP_SSITX - 38 - Select the XIP SSI TX FIFO as TREQ - - - XIP_SSIRX - 39 - Select the XIP SSI RX FIFO as TREQ - - - TIMER0 - 59 - Select Timer 0 as TREQ - - - TIMER1 - 60 - Select Timer 1 as TREQ - - - TIMER2 - 61 - Select Timer 2 as TREQ (Optional) - - - TIMER3 - 62 - Select Timer 3 as TREQ (Optional) - - - PERMANENT - 63 - Permanent request, for unpaced transfers. - - - - - CHAIN_TO - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. - [14:11] - read-write - - - RING_SEL - Select whether RING_SIZE applies to read or write addresses. - If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. - [10:10] - read-write - - - RING_SIZE - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. - - Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. - [9:6] - read-write - - - RING_NONE - 0 - - - - - INCR_WRITE - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. - - Generally this should be disabled for memory-to-peripheral transfers. - [5:5] - read-write - - - INCR_READ - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. - - Generally this should be disabled for peripheral-to-memory transfers. - [4:4] - read-write - - - DATA_SIZE - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. - [3:2] - read-write - - - SIZE_BYTE - 0 - - - SIZE_HALFWORD - 1 - - - SIZE_WORD - 2 - - - - - HIGH_PRIORITY - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. - - This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. - [1:1] - read-write - - - EN - DMA Channel Enable. - When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) - [0:0] - read-write - - - - - CH6_AL1_CTRL - 0x00000190 - Alias for channel 6 CTRL register - 0x00000000 - - - CH6_AL1_CTRL - [31:0] - read-write - - - - - CH6_AL1_READ_ADDR - 0x00000194 - Alias for channel 6 READ_ADDR register - 0x00000000 - - - CH6_AL1_READ_ADDR - [31:0] - read-write - - - - - CH6_AL1_WRITE_ADDR - 0x00000198 - Alias for channel 6 WRITE_ADDR register - 0x00000000 - - - CH6_AL1_WRITE_ADDR - [31:0] - read-write - - - - - CH6_AL1_TRANS_COUNT_TRIG - 0x0000019c - Alias for channel 6 TRANS_COUNT register - This is a trigger register (0xc). Writing a nonzero value will - reload the channel counter and start the channel. - 0x00000000 - - - CH6_AL1_TRANS_COUNT_TRIG - [31:0] - read-write - - - - - CH6_AL2_CTRL - 0x000001a0 - Alias for channel 6 CTRL register - 0x00000000 - - - CH6_AL2_CTRL - [31:0] - read-write - - - - - CH6_AL2_TRANS_COUNT - 0x000001a4 - Alias for channel 6 TRANS_COUNT register - 0x00000000 - - - CH6_AL2_TRANS_COUNT - [31:0] - read-write - - - - - CH6_AL2_READ_ADDR - 0x000001a8 - Alias for channel 6 READ_ADDR register - 0x00000000 - - - CH6_AL2_READ_ADDR - [31:0] - read-write - - - - - CH6_AL2_WRITE_ADDR_TRIG - 0x000001ac - Alias for channel 6 WRITE_ADDR register - This is a trigger register (0xc). Writing a nonzero value will - reload the channel counter and start the channel. - 0x00000000 - - - CH6_AL2_WRITE_ADDR_TRIG - [31:0] - read-write - - - - - CH6_AL3_CTRL - 0x000001b0 - Alias for channel 6 CTRL register - 0x00000000 - - - CH6_AL3_CTRL - [31:0] - read-write - - - - - CH6_AL3_WRITE_ADDR - 0x000001b4 - Alias for channel 6 WRITE_ADDR register - 0x00000000 - - - CH6_AL3_WRITE_ADDR - [31:0] - read-write - - - - - CH6_AL3_TRANS_COUNT - 0x000001b8 - Alias for channel 6 TRANS_COUNT register - 0x00000000 - - - CH6_AL3_TRANS_COUNT - [31:0] - read-write - - - - - CH6_AL3_READ_ADDR_TRIG - 0x000001bc - Alias for channel 6 READ_ADDR register - This is a trigger register (0xc). Writing a nonzero value will - reload the channel counter and start the channel. - 0x00000000 - - - CH6_AL3_READ_ADDR_TRIG - [31:0] - read-write - - - - - CH7_READ_ADDR - 0x000001c0 - DMA Channel 7 Read Address pointer - 0x00000000 - - - CH7_READ_ADDR - This register updates automatically each time a read completes. The current value is the next address to be read by this channel. - [31:0] - read-write - - - - - CH7_WRITE_ADDR - 0x000001c4 - DMA Channel 7 Write Address pointer - 0x00000000 - - - CH7_WRITE_ADDR - This register updates automatically each time a write completes. The current value is the next address to be written by this channel. - [31:0] - read-write - - - - - CH7_TRANS_COUNT - 0x000001c8 - DMA Channel 7 Transfer Count - 0x00000000 - - - CH7_TRANS_COUNT - Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). - - When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. - - Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. - - The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. - [31:0] - read-write - - - - - CH7_CTRL_TRIG - 0x000001cc - DMA Channel 7 Control and Status - 0x00000000 - - - AHB_ERROR - Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. - [31:31] - read-only - - - READ_ERROR - If 1, the channel received a read bus error. Write one to clear. - READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) - [30:30] - read-write - oneToClear - - - WRITE_ERROR - If 1, the channel received a write bus error. Write one to clear. - WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) - [29:29] - read-write - oneToClear - - - BUSY - This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. - - To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. - [24:24] - read-only - - - SNIFF_EN - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. - - This allows checksum to be enabled or disabled on a per-control- block basis. - [23:23] - read-write - - - BSWAP - Apply byte-swap transformation to DMA data. - For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. - [22:22] - read-write - - - IRQ_QUIET - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. - - This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. - [21:21] - read-write - - - TREQ_SEL - Select a Transfer Request signal. - The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). - 0x0 to 0x3a -> select DREQ n as TREQ - [20:15] - read-write - - - PIO0_TX0 - 0 - Select PIO0's TX FIFO 0 as TREQ - - - PIO0_TX1 - 1 - Select PIO0's TX FIFO 1 as TREQ - - - PIO0_TX2 - 2 - Select PIO0's TX FIFO 2 as TREQ - - - PIO0_TX3 - 3 - Select PIO0's TX FIFO 3 as TREQ - - - PIO0_RX0 - 4 - Select PIO0's RX FIFO 0 as TREQ - - - PIO0_RX1 - 5 - Select PIO0's RX FIFO 1 as TREQ - - - PIO0_RX2 - 6 - Select PIO0's RX FIFO 2 as TREQ - - - PIO0_RX3 - 7 - Select PIO0's RX FIFO 3 as TREQ - - - PIO1_TX0 - 8 - Select PIO1's TX FIFO 0 as TREQ - - - PIO1_TX1 - 9 - Select PIO1's TX FIFO 1 as TREQ - - - PIO1_TX2 - 10 - Select PIO1's TX FIFO 2 as TREQ - - - PIO1_TX3 - 11 - Select PIO1's TX FIFO 3 as TREQ - - - PIO1_RX0 - 12 - Select PIO1's RX FIFO 0 as TREQ - - - PIO1_RX1 - 13 - Select PIO1's RX FIFO 1 as TREQ - - - PIO1_RX2 - 14 - Select PIO1's RX FIFO 2 as TREQ - - - PIO1_RX3 - 15 - Select PIO1's RX FIFO 3 as TREQ - - - SPI0_TX - 16 - Select SPI0's TX FIFO as TREQ - - - SPI0_RX - 17 - Select SPI0's RX FIFO as TREQ - - - SPI1_TX - 18 - Select SPI1's TX FIFO as TREQ - - - SPI1_RX - 19 - Select SPI1's RX FIFO as TREQ - - - UART0_TX - 20 - Select UART0's TX FIFO as TREQ - - - UART0_RX - 21 - Select UART0's RX FIFO as TREQ - - - UART1_TX - 22 - Select UART1's TX FIFO as TREQ - - - UART1_RX - 23 - Select UART1's RX FIFO as TREQ - - - PWM_WRAP0 - 24 - Select PWM Counter 0's Wrap Value as TREQ - - - PWM_WRAP1 - 25 - Select PWM Counter 1's Wrap Value as TREQ - - - PWM_WRAP2 - 26 - Select PWM Counter 2's Wrap Value as TREQ - - - PWM_WRAP3 - 27 - Select PWM Counter 3's Wrap Value as TREQ - - - PWM_WRAP4 - 28 - Select PWM Counter 4's Wrap Value as TREQ - - - PWM_WRAP5 - 29 - Select PWM Counter 5's Wrap Value as TREQ - - - PWM_WRAP6 - 30 - Select PWM Counter 6's Wrap Value as TREQ - - - PWM_WRAP7 - 31 - Select PWM Counter 7's Wrap Value as TREQ - - - I2C0_TX - 32 - Select I2C0's TX FIFO as TREQ - - - I2C0_RX - 33 - Select I2C0's RX FIFO as TREQ - - - I2C1_TX - 34 - Select I2C1's TX FIFO as TREQ - - - I2C1_RX - 35 - Select I2C1's RX FIFO as TREQ - - - ADC - 36 - Select the ADC as TREQ - - - XIP_STREAM - 37 - Select the XIP Streaming FIFO as TREQ - - - XIP_SSITX - 38 - Select the XIP SSI TX FIFO as TREQ - - - XIP_SSIRX - 39 - Select the XIP SSI RX FIFO as TREQ - - - TIMER0 - 59 - Select Timer 0 as TREQ - - - TIMER1 - 60 - Select Timer 1 as TREQ - - - TIMER2 - 61 - Select Timer 2 as TREQ (Optional) - - - TIMER3 - 62 - Select Timer 3 as TREQ (Optional) - - - PERMANENT - 63 - Permanent request, for unpaced transfers. - - - - - CHAIN_TO - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. - [14:11] - read-write - - - RING_SEL - Select whether RING_SIZE applies to read or write addresses. - If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. - [10:10] - read-write - - - RING_SIZE - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. - - Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. - [9:6] - read-write - - - RING_NONE - 0 - - - - - INCR_WRITE - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. - - Generally this should be disabled for memory-to-peripheral transfers. - [5:5] - read-write - - - INCR_READ - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. - - Generally this should be disabled for peripheral-to-memory transfers. - [4:4] - read-write - - - DATA_SIZE - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. - [3:2] - read-write - - - SIZE_BYTE - 0 - - - SIZE_HALFWORD - 1 - - - SIZE_WORD - 2 - - - - - HIGH_PRIORITY - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. - - This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. - [1:1] - read-write - - - EN - DMA Channel Enable. - When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) - [0:0] - read-write - - - - - CH7_AL1_CTRL - 0x000001d0 - Alias for channel 7 CTRL register - 0x00000000 - - - CH7_AL1_CTRL - [31:0] - read-write - - - - - CH7_AL1_READ_ADDR - 0x000001d4 - Alias for channel 7 READ_ADDR register - 0x00000000 - - - CH7_AL1_READ_ADDR - [31:0] - read-write - - - - - CH7_AL1_WRITE_ADDR - 0x000001d8 - Alias for channel 7 WRITE_ADDR register - 0x00000000 - - - CH7_AL1_WRITE_ADDR - [31:0] - read-write - - - - - CH7_AL1_TRANS_COUNT_TRIG - 0x000001dc - Alias for channel 7 TRANS_COUNT register - This is a trigger register (0xc). Writing a nonzero value will - reload the channel counter and start the channel. - 0x00000000 - - - CH7_AL1_TRANS_COUNT_TRIG - [31:0] - read-write - - - - - CH7_AL2_CTRL - 0x000001e0 - Alias for channel 7 CTRL register - 0x00000000 - - - CH7_AL2_CTRL - [31:0] - read-write - - - - - CH7_AL2_TRANS_COUNT - 0x000001e4 - Alias for channel 7 TRANS_COUNT register - 0x00000000 - - - CH7_AL2_TRANS_COUNT - [31:0] - read-write - - - - - CH7_AL2_READ_ADDR - 0x000001e8 - Alias for channel 7 READ_ADDR register - 0x00000000 - - - CH7_AL2_READ_ADDR - [31:0] - read-write - - - - - CH7_AL2_WRITE_ADDR_TRIG - 0x000001ec - Alias for channel 7 WRITE_ADDR register - This is a trigger register (0xc). Writing a nonzero value will - reload the channel counter and start the channel. - 0x00000000 - - - CH7_AL2_WRITE_ADDR_TRIG - [31:0] - read-write - - - - - CH7_AL3_CTRL - 0x000001f0 - Alias for channel 7 CTRL register - 0x00000000 - - - CH7_AL3_CTRL - [31:0] - read-write - - - - - CH7_AL3_WRITE_ADDR - 0x000001f4 - Alias for channel 7 WRITE_ADDR register - 0x00000000 - - - CH7_AL3_WRITE_ADDR - [31:0] - read-write - - - - - CH7_AL3_TRANS_COUNT - 0x000001f8 - Alias for channel 7 TRANS_COUNT register - 0x00000000 - - - CH7_AL3_TRANS_COUNT - [31:0] - read-write - - - - - CH7_AL3_READ_ADDR_TRIG - 0x000001fc - Alias for channel 7 READ_ADDR register - This is a trigger register (0xc). Writing a nonzero value will - reload the channel counter and start the channel. - 0x00000000 - - - CH7_AL3_READ_ADDR_TRIG - [31:0] - read-write - - - - - CH8_READ_ADDR - 0x00000200 - DMA Channel 8 Read Address pointer - 0x00000000 - - - CH8_READ_ADDR - This register updates automatically each time a read completes. The current value is the next address to be read by this channel. - [31:0] - read-write - - - - - CH8_WRITE_ADDR - 0x00000204 - DMA Channel 8 Write Address pointer - 0x00000000 - - - CH8_WRITE_ADDR - This register updates automatically each time a write completes. The current value is the next address to be written by this channel. - [31:0] - read-write - - - - - CH8_TRANS_COUNT - 0x00000208 - DMA Channel 8 Transfer Count - 0x00000000 - - - CH8_TRANS_COUNT - Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). - - When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. - - Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. - - The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. - [31:0] - read-write - - - - - CH8_CTRL_TRIG - 0x0000020c - DMA Channel 8 Control and Status - 0x00000000 - - - AHB_ERROR - Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. - [31:31] - read-only - - - READ_ERROR - If 1, the channel received a read bus error. Write one to clear. - READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) - [30:30] - read-write - oneToClear - - - WRITE_ERROR - If 1, the channel received a write bus error. Write one to clear. - WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) - [29:29] - read-write - oneToClear - - - BUSY - This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. - - To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. - [24:24] - read-only - - - SNIFF_EN - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. - - This allows checksum to be enabled or disabled on a per-control- block basis. - [23:23] - read-write - - - BSWAP - Apply byte-swap transformation to DMA data. - For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. - [22:22] - read-write - - - IRQ_QUIET - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. - - This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. - [21:21] - read-write - - - TREQ_SEL - Select a Transfer Request signal. - The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). - 0x0 to 0x3a -> select DREQ n as TREQ - [20:15] - read-write - - - PIO0_TX0 - 0 - Select PIO0's TX FIFO 0 as TREQ - - - PIO0_TX1 - 1 - Select PIO0's TX FIFO 1 as TREQ - - - PIO0_TX2 - 2 - Select PIO0's TX FIFO 2 as TREQ - - - PIO0_TX3 - 3 - Select PIO0's TX FIFO 3 as TREQ - - - PIO0_RX0 - 4 - Select PIO0's RX FIFO 0 as TREQ - - - PIO0_RX1 - 5 - Select PIO0's RX FIFO 1 as TREQ - - - PIO0_RX2 - 6 - Select PIO0's RX FIFO 2 as TREQ - - - PIO0_RX3 - 7 - Select PIO0's RX FIFO 3 as TREQ - - - PIO1_TX0 - 8 - Select PIO1's TX FIFO 0 as TREQ - - - PIO1_TX1 - 9 - Select PIO1's TX FIFO 1 as TREQ - - - PIO1_TX2 - 10 - Select PIO1's TX FIFO 2 as TREQ - - - PIO1_TX3 - 11 - Select PIO1's TX FIFO 3 as TREQ - - - PIO1_RX0 - 12 - Select PIO1's RX FIFO 0 as TREQ - - - PIO1_RX1 - 13 - Select PIO1's RX FIFO 1 as TREQ - - - PIO1_RX2 - 14 - Select PIO1's RX FIFO 2 as TREQ - - - PIO1_RX3 - 15 - Select PIO1's RX FIFO 3 as TREQ - - - SPI0_TX - 16 - Select SPI0's TX FIFO as TREQ - - - SPI0_RX - 17 - Select SPI0's RX FIFO as TREQ - - - SPI1_TX - 18 - Select SPI1's TX FIFO as TREQ - - - SPI1_RX - 19 - Select SPI1's RX FIFO as TREQ - - - UART0_TX - 20 - Select UART0's TX FIFO as TREQ - - - UART0_RX - 21 - Select UART0's RX FIFO as TREQ - - - UART1_TX - 22 - Select UART1's TX FIFO as TREQ - - - UART1_RX - 23 - Select UART1's RX FIFO as TREQ - - - PWM_WRAP0 - 24 - Select PWM Counter 0's Wrap Value as TREQ - - - PWM_WRAP1 - 25 - Select PWM Counter 1's Wrap Value as TREQ - - - PWM_WRAP2 - 26 - Select PWM Counter 2's Wrap Value as TREQ - - - PWM_WRAP3 - 27 - Select PWM Counter 3's Wrap Value as TREQ - - - PWM_WRAP4 - 28 - Select PWM Counter 4's Wrap Value as TREQ - - - PWM_WRAP5 - 29 - Select PWM Counter 5's Wrap Value as TREQ - - - PWM_WRAP6 - 30 - Select PWM Counter 6's Wrap Value as TREQ - - - PWM_WRAP7 - 31 - Select PWM Counter 7's Wrap Value as TREQ - - - I2C0_TX - 32 - Select I2C0's TX FIFO as TREQ - - - I2C0_RX - 33 - Select I2C0's RX FIFO as TREQ - - - I2C1_TX - 34 - Select I2C1's TX FIFO as TREQ - - - I2C1_RX - 35 - Select I2C1's RX FIFO as TREQ - - - ADC - 36 - Select the ADC as TREQ - - - XIP_STREAM - 37 - Select the XIP Streaming FIFO as TREQ - - - XIP_SSITX - 38 - Select the XIP SSI TX FIFO as TREQ - - - XIP_SSIRX - 39 - Select the XIP SSI RX FIFO as TREQ - - - TIMER0 - 59 - Select Timer 0 as TREQ - - - TIMER1 - 60 - Select Timer 1 as TREQ - - - TIMER2 - 61 - Select Timer 2 as TREQ (Optional) - - - TIMER3 - 62 - Select Timer 3 as TREQ (Optional) - - - PERMANENT - 63 - Permanent request, for unpaced transfers. - - - - - CHAIN_TO - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. - [14:11] - read-write - - - RING_SEL - Select whether RING_SIZE applies to read or write addresses. - If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. - [10:10] - read-write - - - RING_SIZE - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. - - Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. - [9:6] - read-write - - - RING_NONE - 0 - - - - - INCR_WRITE - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. - - Generally this should be disabled for memory-to-peripheral transfers. - [5:5] - read-write - - - INCR_READ - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. - - Generally this should be disabled for peripheral-to-memory transfers. - [4:4] - read-write - - - DATA_SIZE - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. - [3:2] - read-write - - - SIZE_BYTE - 0 - - - SIZE_HALFWORD - 1 - - - SIZE_WORD - 2 - - - - - HIGH_PRIORITY - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. - - This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. - [1:1] - read-write - - - EN - DMA Channel Enable. - When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) - [0:0] - read-write - - - - - CH8_AL1_CTRL - 0x00000210 - Alias for channel 8 CTRL register - 0x00000000 - - - CH8_AL1_CTRL - [31:0] - read-write - - - - - CH8_AL1_READ_ADDR - 0x00000214 - Alias for channel 8 READ_ADDR register - 0x00000000 - - - CH8_AL1_READ_ADDR - [31:0] - read-write - - - - - CH8_AL1_WRITE_ADDR - 0x00000218 - Alias for channel 8 WRITE_ADDR register - 0x00000000 - - - CH8_AL1_WRITE_ADDR - [31:0] - read-write - - - - - CH8_AL1_TRANS_COUNT_TRIG - 0x0000021c - Alias for channel 8 TRANS_COUNT register - This is a trigger register (0xc). Writing a nonzero value will - reload the channel counter and start the channel. - 0x00000000 - - - CH8_AL1_TRANS_COUNT_TRIG - [31:0] - read-write - - - - - CH8_AL2_CTRL - 0x00000220 - Alias for channel 8 CTRL register - 0x00000000 - - - CH8_AL2_CTRL - [31:0] - read-write - - - - - CH8_AL2_TRANS_COUNT - 0x00000224 - Alias for channel 8 TRANS_COUNT register - 0x00000000 - - - CH8_AL2_TRANS_COUNT - [31:0] - read-write - - - - - CH8_AL2_READ_ADDR - 0x00000228 - Alias for channel 8 READ_ADDR register - 0x00000000 - - - CH8_AL2_READ_ADDR - [31:0] - read-write - - - - - CH8_AL2_WRITE_ADDR_TRIG - 0x0000022c - Alias for channel 8 WRITE_ADDR register - This is a trigger register (0xc). Writing a nonzero value will - reload the channel counter and start the channel. - 0x00000000 - - - CH8_AL2_WRITE_ADDR_TRIG - [31:0] - read-write - - - - - CH8_AL3_CTRL - 0x00000230 - Alias for channel 8 CTRL register - 0x00000000 - - - CH8_AL3_CTRL - [31:0] - read-write - - - - - CH8_AL3_WRITE_ADDR - 0x00000234 - Alias for channel 8 WRITE_ADDR register - 0x00000000 - - - CH8_AL3_WRITE_ADDR - [31:0] - read-write - - - - - CH8_AL3_TRANS_COUNT - 0x00000238 - Alias for channel 8 TRANS_COUNT register - 0x00000000 - - - CH8_AL3_TRANS_COUNT - [31:0] - read-write - - - - - CH8_AL3_READ_ADDR_TRIG - 0x0000023c - Alias for channel 8 READ_ADDR register - This is a trigger register (0xc). Writing a nonzero value will - reload the channel counter and start the channel. - 0x00000000 - - - CH8_AL3_READ_ADDR_TRIG - [31:0] - read-write - - - - - CH9_READ_ADDR - 0x00000240 - DMA Channel 9 Read Address pointer - 0x00000000 - - - CH9_READ_ADDR - This register updates automatically each time a read completes. The current value is the next address to be read by this channel. - [31:0] - read-write - - - - - CH9_WRITE_ADDR - 0x00000244 - DMA Channel 9 Write Address pointer - 0x00000000 - - - CH9_WRITE_ADDR - This register updates automatically each time a write completes. The current value is the next address to be written by this channel. - [31:0] - read-write - - - - - CH9_TRANS_COUNT - 0x00000248 - DMA Channel 9 Transfer Count - 0x00000000 - - - CH9_TRANS_COUNT - Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). - - When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. - - Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. - - The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. - [31:0] - read-write - - - - - CH9_CTRL_TRIG - 0x0000024c - DMA Channel 9 Control and Status - 0x00000000 - - - AHB_ERROR - Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. - [31:31] - read-only - - - READ_ERROR - If 1, the channel received a read bus error. Write one to clear. - READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) - [30:30] - read-write - oneToClear - - - WRITE_ERROR - If 1, the channel received a write bus error. Write one to clear. - WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) - [29:29] - read-write - oneToClear - - - BUSY - This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. - - To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. - [24:24] - read-only - - - SNIFF_EN - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. - - This allows checksum to be enabled or disabled on a per-control- block basis. - [23:23] - read-write - - - BSWAP - Apply byte-swap transformation to DMA data. - For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. - [22:22] - read-write - - - IRQ_QUIET - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. - - This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. - [21:21] - read-write - - - TREQ_SEL - Select a Transfer Request signal. - The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). - 0x0 to 0x3a -> select DREQ n as TREQ - [20:15] - read-write - - - PIO0_TX0 - 0 - Select PIO0's TX FIFO 0 as TREQ - - - PIO0_TX1 - 1 - Select PIO0's TX FIFO 1 as TREQ - - - PIO0_TX2 - 2 - Select PIO0's TX FIFO 2 as TREQ - - - PIO0_TX3 - 3 - Select PIO0's TX FIFO 3 as TREQ - - - PIO0_RX0 - 4 - Select PIO0's RX FIFO 0 as TREQ - - - PIO0_RX1 - 5 - Select PIO0's RX FIFO 1 as TREQ - - - PIO0_RX2 - 6 - Select PIO0's RX FIFO 2 as TREQ - - - PIO0_RX3 - 7 - Select PIO0's RX FIFO 3 as TREQ - - - PIO1_TX0 - 8 - Select PIO1's TX FIFO 0 as TREQ - - - PIO1_TX1 - 9 - Select PIO1's TX FIFO 1 as TREQ - - - PIO1_TX2 - 10 - Select PIO1's TX FIFO 2 as TREQ - - - PIO1_TX3 - 11 - Select PIO1's TX FIFO 3 as TREQ - - - PIO1_RX0 - 12 - Select PIO1's RX FIFO 0 as TREQ - - - PIO1_RX1 - 13 - Select PIO1's RX FIFO 1 as TREQ - - - PIO1_RX2 - 14 - Select PIO1's RX FIFO 2 as TREQ - - - PIO1_RX3 - 15 - Select PIO1's RX FIFO 3 as TREQ - - - SPI0_TX - 16 - Select SPI0's TX FIFO as TREQ - - - SPI0_RX - 17 - Select SPI0's RX FIFO as TREQ - - - SPI1_TX - 18 - Select SPI1's TX FIFO as TREQ - - - SPI1_RX - 19 - Select SPI1's RX FIFO as TREQ - - - UART0_TX - 20 - Select UART0's TX FIFO as TREQ - - - UART0_RX - 21 - Select UART0's RX FIFO as TREQ - - - UART1_TX - 22 - Select UART1's TX FIFO as TREQ - - - UART1_RX - 23 - Select UART1's RX FIFO as TREQ - - - PWM_WRAP0 - 24 - Select PWM Counter 0's Wrap Value as TREQ - - - PWM_WRAP1 - 25 - Select PWM Counter 1's Wrap Value as TREQ - - - PWM_WRAP2 - 26 - Select PWM Counter 2's Wrap Value as TREQ - - - PWM_WRAP3 - 27 - Select PWM Counter 3's Wrap Value as TREQ - - - PWM_WRAP4 - 28 - Select PWM Counter 4's Wrap Value as TREQ - - - PWM_WRAP5 - 29 - Select PWM Counter 5's Wrap Value as TREQ - - - PWM_WRAP6 - 30 - Select PWM Counter 6's Wrap Value as TREQ - - - PWM_WRAP7 - 31 - Select PWM Counter 7's Wrap Value as TREQ - - - I2C0_TX - 32 - Select I2C0's TX FIFO as TREQ - - - I2C0_RX - 33 - Select I2C0's RX FIFO as TREQ - - - I2C1_TX - 34 - Select I2C1's TX FIFO as TREQ - - - I2C1_RX - 35 - Select I2C1's RX FIFO as TREQ - - - ADC - 36 - Select the ADC as TREQ - - - XIP_STREAM - 37 - Select the XIP Streaming FIFO as TREQ - - - XIP_SSITX - 38 - Select the XIP SSI TX FIFO as TREQ - - - XIP_SSIRX - 39 - Select the XIP SSI RX FIFO as TREQ - - - TIMER0 - 59 - Select Timer 0 as TREQ - - - TIMER1 - 60 - Select Timer 1 as TREQ - - - TIMER2 - 61 - Select Timer 2 as TREQ (Optional) - - - TIMER3 - 62 - Select Timer 3 as TREQ (Optional) - - - PERMANENT - 63 - Permanent request, for unpaced transfers. - - - - - CHAIN_TO - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. - [14:11] - read-write - - - RING_SEL - Select whether RING_SIZE applies to read or write addresses. - If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. - [10:10] - read-write - - - RING_SIZE - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. - - Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. - [9:6] - read-write - - - RING_NONE - 0 - - - - - INCR_WRITE - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. - - Generally this should be disabled for memory-to-peripheral transfers. - [5:5] - read-write - - - INCR_READ - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. - - Generally this should be disabled for peripheral-to-memory transfers. - [4:4] - read-write - - - DATA_SIZE - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. - [3:2] - read-write - - - SIZE_BYTE - 0 - - - SIZE_HALFWORD - 1 - - - SIZE_WORD - 2 - - - - - HIGH_PRIORITY - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. - - This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. - [1:1] - read-write - - - EN - DMA Channel Enable. - When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) - [0:0] - read-write - - - - - CH9_AL1_CTRL - 0x00000250 - Alias for channel 9 CTRL register - 0x00000000 - - - CH9_AL1_CTRL - [31:0] - read-write - - - - - CH9_AL1_READ_ADDR - 0x00000254 - Alias for channel 9 READ_ADDR register - 0x00000000 - - - CH9_AL1_READ_ADDR - [31:0] - read-write - - - - - CH9_AL1_WRITE_ADDR - 0x00000258 - Alias for channel 9 WRITE_ADDR register - 0x00000000 - - - CH9_AL1_WRITE_ADDR - [31:0] - read-write - - - - - CH9_AL1_TRANS_COUNT_TRIG - 0x0000025c - Alias for channel 9 TRANS_COUNT register - This is a trigger register (0xc). Writing a nonzero value will - reload the channel counter and start the channel. - 0x00000000 - - - CH9_AL1_TRANS_COUNT_TRIG - [31:0] - read-write - - - - - CH9_AL2_CTRL - 0x00000260 - Alias for channel 9 CTRL register - 0x00000000 - - - CH9_AL2_CTRL - [31:0] - read-write - - - - - CH9_AL2_TRANS_COUNT - 0x00000264 - Alias for channel 9 TRANS_COUNT register - 0x00000000 - - - CH9_AL2_TRANS_COUNT - [31:0] - read-write - - - - - CH9_AL2_READ_ADDR - 0x00000268 - Alias for channel 9 READ_ADDR register - 0x00000000 - - - CH9_AL2_READ_ADDR - [31:0] - read-write - - - - - CH9_AL2_WRITE_ADDR_TRIG - 0x0000026c - Alias for channel 9 WRITE_ADDR register - This is a trigger register (0xc). Writing a nonzero value will - reload the channel counter and start the channel. - 0x00000000 - - - CH9_AL2_WRITE_ADDR_TRIG - [31:0] - read-write - - - - - CH9_AL3_CTRL - 0x00000270 - Alias for channel 9 CTRL register - 0x00000000 - - - CH9_AL3_CTRL - [31:0] - read-write - - - - - CH9_AL3_WRITE_ADDR - 0x00000274 - Alias for channel 9 WRITE_ADDR register - 0x00000000 - - - CH9_AL3_WRITE_ADDR - [31:0] - read-write - - - - - CH9_AL3_TRANS_COUNT - 0x00000278 - Alias for channel 9 TRANS_COUNT register - 0x00000000 - - - CH9_AL3_TRANS_COUNT - [31:0] - read-write - - - - - CH9_AL3_READ_ADDR_TRIG - 0x0000027c - Alias for channel 9 READ_ADDR register - This is a trigger register (0xc). Writing a nonzero value will - reload the channel counter and start the channel. - 0x00000000 - - - CH9_AL3_READ_ADDR_TRIG - [31:0] - read-write - - - - - CH10_READ_ADDR - 0x00000280 - DMA Channel 10 Read Address pointer - 0x00000000 - - - CH10_READ_ADDR - This register updates automatically each time a read completes. The current value is the next address to be read by this channel. - [31:0] - read-write - - - - - CH10_WRITE_ADDR - 0x00000284 - DMA Channel 10 Write Address pointer - 0x00000000 - - - CH10_WRITE_ADDR - This register updates automatically each time a write completes. The current value is the next address to be written by this channel. - [31:0] - read-write - - - - - CH10_TRANS_COUNT - 0x00000288 - DMA Channel 10 Transfer Count - 0x00000000 - - - CH10_TRANS_COUNT - Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). - - When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. - - Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. - - The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. - [31:0] - read-write - - - - - CH10_CTRL_TRIG - 0x0000028c - DMA Channel 10 Control and Status - 0x00000000 - - - AHB_ERROR - Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. - [31:31] - read-only - - - READ_ERROR - If 1, the channel received a read bus error. Write one to clear. - READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) - [30:30] - read-write - oneToClear - - - WRITE_ERROR - If 1, the channel received a write bus error. Write one to clear. - WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) - [29:29] - read-write - oneToClear - - - BUSY - This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. - - To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. - [24:24] - read-only - - - SNIFF_EN - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. - - This allows checksum to be enabled or disabled on a per-control- block basis. - [23:23] - read-write - - - BSWAP - Apply byte-swap transformation to DMA data. - For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. - [22:22] - read-write - - - IRQ_QUIET - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. - - This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. - [21:21] - read-write - - - TREQ_SEL - Select a Transfer Request signal. - The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). - 0x0 to 0x3a -> select DREQ n as TREQ - [20:15] - read-write - - - PIO0_TX0 - 0 - Select PIO0's TX FIFO 0 as TREQ - - - PIO0_TX1 - 1 - Select PIO0's TX FIFO 1 as TREQ - - - PIO0_TX2 - 2 - Select PIO0's TX FIFO 2 as TREQ - - - PIO0_TX3 - 3 - Select PIO0's TX FIFO 3 as TREQ - - - PIO0_RX0 - 4 - Select PIO0's RX FIFO 0 as TREQ - - - PIO0_RX1 - 5 - Select PIO0's RX FIFO 1 as TREQ - - - PIO0_RX2 - 6 - Select PIO0's RX FIFO 2 as TREQ - - - PIO0_RX3 - 7 - Select PIO0's RX FIFO 3 as TREQ - - - PIO1_TX0 - 8 - Select PIO1's TX FIFO 0 as TREQ - - - PIO1_TX1 - 9 - Select PIO1's TX FIFO 1 as TREQ - - - PIO1_TX2 - 10 - Select PIO1's TX FIFO 2 as TREQ - - - PIO1_TX3 - 11 - Select PIO1's TX FIFO 3 as TREQ - - - PIO1_RX0 - 12 - Select PIO1's RX FIFO 0 as TREQ - - - PIO1_RX1 - 13 - Select PIO1's RX FIFO 1 as TREQ - - - PIO1_RX2 - 14 - Select PIO1's RX FIFO 2 as TREQ - - - PIO1_RX3 - 15 - Select PIO1's RX FIFO 3 as TREQ - - - SPI0_TX - 16 - Select SPI0's TX FIFO as TREQ - - - SPI0_RX - 17 - Select SPI0's RX FIFO as TREQ - - - SPI1_TX - 18 - Select SPI1's TX FIFO as TREQ - - - SPI1_RX - 19 - Select SPI1's RX FIFO as TREQ - - - UART0_TX - 20 - Select UART0's TX FIFO as TREQ - - - UART0_RX - 21 - Select UART0's RX FIFO as TREQ - - - UART1_TX - 22 - Select UART1's TX FIFO as TREQ - - - UART1_RX - 23 - Select UART1's RX FIFO as TREQ - - - PWM_WRAP0 - 24 - Select PWM Counter 0's Wrap Value as TREQ - - - PWM_WRAP1 - 25 - Select PWM Counter 1's Wrap Value as TREQ - - - PWM_WRAP2 - 26 - Select PWM Counter 2's Wrap Value as TREQ - - - PWM_WRAP3 - 27 - Select PWM Counter 3's Wrap Value as TREQ - - - PWM_WRAP4 - 28 - Select PWM Counter 4's Wrap Value as TREQ - - - PWM_WRAP5 - 29 - Select PWM Counter 5's Wrap Value as TREQ - - - PWM_WRAP6 - 30 - Select PWM Counter 6's Wrap Value as TREQ - - - PWM_WRAP7 - 31 - Select PWM Counter 7's Wrap Value as TREQ - - - I2C0_TX - 32 - Select I2C0's TX FIFO as TREQ - - - I2C0_RX - 33 - Select I2C0's RX FIFO as TREQ - - - I2C1_TX - 34 - Select I2C1's TX FIFO as TREQ - - - I2C1_RX - 35 - Select I2C1's RX FIFO as TREQ - - - ADC - 36 - Select the ADC as TREQ - - - XIP_STREAM - 37 - Select the XIP Streaming FIFO as TREQ - - - XIP_SSITX - 38 - Select the XIP SSI TX FIFO as TREQ - - - XIP_SSIRX - 39 - Select the XIP SSI RX FIFO as TREQ - - - TIMER0 - 59 - Select Timer 0 as TREQ - - - TIMER1 - 60 - Select Timer 1 as TREQ - - - TIMER2 - 61 - Select Timer 2 as TREQ (Optional) - - - TIMER3 - 62 - Select Timer 3 as TREQ (Optional) - - - PERMANENT - 63 - Permanent request, for unpaced transfers. - - - - - CHAIN_TO - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. - [14:11] - read-write - - - RING_SEL - Select whether RING_SIZE applies to read or write addresses. - If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. - [10:10] - read-write - - - RING_SIZE - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. - - Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. - [9:6] - read-write - - - RING_NONE - 0 - - - - - INCR_WRITE - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. - - Generally this should be disabled for memory-to-peripheral transfers. - [5:5] - read-write - - - INCR_READ - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. - - Generally this should be disabled for peripheral-to-memory transfers. - [4:4] - read-write - - - DATA_SIZE - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. - [3:2] - read-write - - - SIZE_BYTE - 0 - - - SIZE_HALFWORD - 1 - - - SIZE_WORD - 2 - - - - - HIGH_PRIORITY - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. - - This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. - [1:1] - read-write - - - EN - DMA Channel Enable. - When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) - [0:0] - read-write - - - - - CH10_AL1_CTRL - 0x00000290 - Alias for channel 10 CTRL register - 0x00000000 - - - CH10_AL1_CTRL - [31:0] - read-write - - - - - CH10_AL1_READ_ADDR - 0x00000294 - Alias for channel 10 READ_ADDR register - 0x00000000 - - - CH10_AL1_READ_ADDR - [31:0] - read-write - - - - - CH10_AL1_WRITE_ADDR - 0x00000298 - Alias for channel 10 WRITE_ADDR register - 0x00000000 - - - CH10_AL1_WRITE_ADDR - [31:0] - read-write - - - - - CH10_AL1_TRANS_COUNT_TRIG - 0x0000029c - Alias for channel 10 TRANS_COUNT register - This is a trigger register (0xc). Writing a nonzero value will - reload the channel counter and start the channel. - 0x00000000 - - - CH10_AL1_TRANS_COUNT_TRIG - [31:0] - read-write - - - - - CH10_AL2_CTRL - 0x000002a0 - Alias for channel 10 CTRL register - 0x00000000 - - - CH10_AL2_CTRL - [31:0] - read-write - - - - - CH10_AL2_TRANS_COUNT - 0x000002a4 - Alias for channel 10 TRANS_COUNT register - 0x00000000 - - - CH10_AL2_TRANS_COUNT - [31:0] - read-write - - - - - CH10_AL2_READ_ADDR - 0x000002a8 - Alias for channel 10 READ_ADDR register - 0x00000000 - - - CH10_AL2_READ_ADDR - [31:0] - read-write - - - - - CH10_AL2_WRITE_ADDR_TRIG - 0x000002ac - Alias for channel 10 WRITE_ADDR register - This is a trigger register (0xc). Writing a nonzero value will - reload the channel counter and start the channel. - 0x00000000 - - - CH10_AL2_WRITE_ADDR_TRIG - [31:0] - read-write - - - - - CH10_AL3_CTRL - 0x000002b0 - Alias for channel 10 CTRL register - 0x00000000 - - - CH10_AL3_CTRL - [31:0] - read-write - - - - - CH10_AL3_WRITE_ADDR - 0x000002b4 - Alias for channel 10 WRITE_ADDR register - 0x00000000 - - - CH10_AL3_WRITE_ADDR - [31:0] - read-write - - - - - CH10_AL3_TRANS_COUNT - 0x000002b8 - Alias for channel 10 TRANS_COUNT register - 0x00000000 - - - CH10_AL3_TRANS_COUNT - [31:0] - read-write - - - - - CH10_AL3_READ_ADDR_TRIG - 0x000002bc - Alias for channel 10 READ_ADDR register - This is a trigger register (0xc). Writing a nonzero value will - reload the channel counter and start the channel. - 0x00000000 - - - CH10_AL3_READ_ADDR_TRIG - [31:0] - read-write - - - - - CH11_READ_ADDR - 0x000002c0 - DMA Channel 11 Read Address pointer - 0x00000000 - - - CH11_READ_ADDR - This register updates automatically each time a read completes. The current value is the next address to be read by this channel. - [31:0] - read-write - - - - - CH11_WRITE_ADDR - 0x000002c4 - DMA Channel 11 Write Address pointer - 0x00000000 - - - CH11_WRITE_ADDR - This register updates automatically each time a write completes. The current value is the next address to be written by this channel. - [31:0] - read-write - - - - - CH11_TRANS_COUNT - 0x000002c8 - DMA Channel 11 Transfer Count - 0x00000000 - - - CH11_TRANS_COUNT - Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). - - When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. - - Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. - - The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. - [31:0] - read-write - - - - - CH11_CTRL_TRIG - 0x000002cc - DMA Channel 11 Control and Status - 0x00000000 - - - AHB_ERROR - Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. - [31:31] - read-only - - - READ_ERROR - If 1, the channel received a read bus error. Write one to clear. - READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) - [30:30] - read-write - oneToClear - - - WRITE_ERROR - If 1, the channel received a write bus error. Write one to clear. - WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) - [29:29] - read-write - oneToClear - - - BUSY - This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. - - To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. - [24:24] - read-only - - - SNIFF_EN - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. - - This allows checksum to be enabled or disabled on a per-control- block basis. - [23:23] - read-write - - - BSWAP - Apply byte-swap transformation to DMA data. - For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. - [22:22] - read-write - - - IRQ_QUIET - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. - - This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. - [21:21] - read-write - - - TREQ_SEL - Select a Transfer Request signal. - The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). - 0x0 to 0x3a -> select DREQ n as TREQ - [20:15] - read-write - - - PIO0_TX0 - 0 - Select PIO0's TX FIFO 0 as TREQ - - - PIO0_TX1 - 1 - Select PIO0's TX FIFO 1 as TREQ - - - PIO0_TX2 - 2 - Select PIO0's TX FIFO 2 as TREQ - - - PIO0_TX3 - 3 - Select PIO0's TX FIFO 3 as TREQ - - - PIO0_RX0 - 4 - Select PIO0's RX FIFO 0 as TREQ - - - PIO0_RX1 - 5 - Select PIO0's RX FIFO 1 as TREQ - - - PIO0_RX2 - 6 - Select PIO0's RX FIFO 2 as TREQ - - - PIO0_RX3 - 7 - Select PIO0's RX FIFO 3 as TREQ - - - PIO1_TX0 - 8 - Select PIO1's TX FIFO 0 as TREQ - - - PIO1_TX1 - 9 - Select PIO1's TX FIFO 1 as TREQ - - - PIO1_TX2 - 10 - Select PIO1's TX FIFO 2 as TREQ - - - PIO1_TX3 - 11 - Select PIO1's TX FIFO 3 as TREQ - - - PIO1_RX0 - 12 - Select PIO1's RX FIFO 0 as TREQ - - - PIO1_RX1 - 13 - Select PIO1's RX FIFO 1 as TREQ - - - PIO1_RX2 - 14 - Select PIO1's RX FIFO 2 as TREQ - - - PIO1_RX3 - 15 - Select PIO1's RX FIFO 3 as TREQ - - - SPI0_TX - 16 - Select SPI0's TX FIFO as TREQ - - - SPI0_RX - 17 - Select SPI0's RX FIFO as TREQ - - - SPI1_TX - 18 - Select SPI1's TX FIFO as TREQ - - - SPI1_RX - 19 - Select SPI1's RX FIFO as TREQ - - - UART0_TX - 20 - Select UART0's TX FIFO as TREQ - - - UART0_RX - 21 - Select UART0's RX FIFO as TREQ - - - UART1_TX - 22 - Select UART1's TX FIFO as TREQ - - - UART1_RX - 23 - Select UART1's RX FIFO as TREQ - - - PWM_WRAP0 - 24 - Select PWM Counter 0's Wrap Value as TREQ - - - PWM_WRAP1 - 25 - Select PWM Counter 1's Wrap Value as TREQ - - - PWM_WRAP2 - 26 - Select PWM Counter 2's Wrap Value as TREQ - - - PWM_WRAP3 - 27 - Select PWM Counter 3's Wrap Value as TREQ - - - PWM_WRAP4 - 28 - Select PWM Counter 4's Wrap Value as TREQ - - - PWM_WRAP5 - 29 - Select PWM Counter 5's Wrap Value as TREQ - - - PWM_WRAP6 - 30 - Select PWM Counter 6's Wrap Value as TREQ - - - PWM_WRAP7 - 31 - Select PWM Counter 7's Wrap Value as TREQ - - - I2C0_TX - 32 - Select I2C0's TX FIFO as TREQ - - - I2C0_RX - 33 - Select I2C0's RX FIFO as TREQ - - - I2C1_TX - 34 - Select I2C1's TX FIFO as TREQ - - - I2C1_RX - 35 - Select I2C1's RX FIFO as TREQ - - - ADC - 36 - Select the ADC as TREQ - - - XIP_STREAM - 37 - Select the XIP Streaming FIFO as TREQ - - - XIP_SSITX - 38 - Select the XIP SSI TX FIFO as TREQ - - - XIP_SSIRX - 39 - Select the XIP SSI RX FIFO as TREQ - - - TIMER0 - 59 - Select Timer 0 as TREQ - - - TIMER1 - 60 - Select Timer 1 as TREQ - - - TIMER2 - 61 - Select Timer 2 as TREQ (Optional) - - - TIMER3 - 62 - Select Timer 3 as TREQ (Optional) - - - PERMANENT - 63 - Permanent request, for unpaced transfers. - - - - - CHAIN_TO - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. - [14:11] - read-write - - - RING_SEL - Select whether RING_SIZE applies to read or write addresses. - If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. - [10:10] - read-write - - - RING_SIZE - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. - - Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. - [9:6] - read-write - - - RING_NONE - 0 - - - - - INCR_WRITE - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. - - Generally this should be disabled for memory-to-peripheral transfers. - [5:5] - read-write - - - INCR_READ - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. - - Generally this should be disabled for peripheral-to-memory transfers. - [4:4] - read-write - - - DATA_SIZE - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. - [3:2] - read-write - - - SIZE_BYTE - 0 - - - SIZE_HALFWORD - 1 - - - SIZE_WORD - 2 - - - - - HIGH_PRIORITY - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. - - This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. - [1:1] - read-write - - - EN - DMA Channel Enable. - When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) - [0:0] - read-write - - - - - CH11_AL1_CTRL - 0x000002d0 - Alias for channel 11 CTRL register - 0x00000000 - - - CH11_AL1_CTRL - [31:0] - read-write - - - - - CH11_AL1_READ_ADDR - 0x000002d4 - Alias for channel 11 READ_ADDR register - 0x00000000 - - - CH11_AL1_READ_ADDR - [31:0] - read-write - - - - - CH11_AL1_WRITE_ADDR - 0x000002d8 - Alias for channel 11 WRITE_ADDR register - 0x00000000 - - - CH11_AL1_WRITE_ADDR - [31:0] - read-write - - - - - CH11_AL1_TRANS_COUNT_TRIG - 0x000002dc - Alias for channel 11 TRANS_COUNT register - This is a trigger register (0xc). Writing a nonzero value will - reload the channel counter and start the channel. - 0x00000000 - - - CH11_AL1_TRANS_COUNT_TRIG - [31:0] - read-write - - - - - CH11_AL2_CTRL - 0x000002e0 - Alias for channel 11 CTRL register - 0x00000000 - - - CH11_AL2_CTRL - [31:0] - read-write - - - - - CH11_AL2_TRANS_COUNT - 0x000002e4 - Alias for channel 11 TRANS_COUNT register - 0x00000000 - - - CH11_AL2_TRANS_COUNT - [31:0] - read-write - - - - - CH11_AL2_READ_ADDR - 0x000002e8 - Alias for channel 11 READ_ADDR register - 0x00000000 - - - CH11_AL2_READ_ADDR - [31:0] - read-write - - - - - CH11_AL2_WRITE_ADDR_TRIG - 0x000002ec - Alias for channel 11 WRITE_ADDR register - This is a trigger register (0xc). Writing a nonzero value will - reload the channel counter and start the channel. - 0x00000000 - - - CH11_AL2_WRITE_ADDR_TRIG - [31:0] - read-write - - - - - CH11_AL3_CTRL - 0x000002f0 - Alias for channel 11 CTRL register - 0x00000000 - - - CH11_AL3_CTRL - [31:0] - read-write - - - - - CH11_AL3_WRITE_ADDR - 0x000002f4 - Alias for channel 11 WRITE_ADDR register - 0x00000000 - - - CH11_AL3_WRITE_ADDR - [31:0] - read-write - - - - - CH11_AL3_TRANS_COUNT - 0x000002f8 - Alias for channel 11 TRANS_COUNT register - 0x00000000 - - - CH11_AL3_TRANS_COUNT - [31:0] - read-write - - - - - CH11_AL3_READ_ADDR_TRIG - 0x000002fc - Alias for channel 11 READ_ADDR register - This is a trigger register (0xc). Writing a nonzero value will - reload the channel counter and start the channel. - 0x00000000 - - - CH11_AL3_READ_ADDR_TRIG - [31:0] - read-write - - - - - INTR - 0x00000400 - Interrupt Status (raw) - 0x00000000 - - - INTR - Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR, INTS0 or INTS1. - - Channel interrupts can be routed to either of two system-level IRQs based on INTE0 and INTE1. - - This can be used vector different channel interrupts to different ISRs: this might be done to allow NVIC IRQ preemption for more time-critical channels, or to spread IRQ load across different cores. - - It is also valid to ignore this behaviour and just use INTE0/INTS0/IRQ 0. - [15:0] - read-write - oneToClear - - - - - INTE0 - 0x00000404 - Interrupt Enables for IRQ 0 - 0x00000000 - - - INTE0 - Set bit n to pass interrupts from channel n to DMA IRQ 0. - [15:0] - read-write - - - - - INTF0 - 0x00000408 - Force Interrupts - 0x00000000 - - - INTF0 - Write 1s to force the corresponding bits in INTE0. The interrupt remains asserted until INTF0 is cleared. - [15:0] - read-write - - - - - INTS0 - 0x0000040c - Interrupt Status for IRQ 0 - 0x00000000 - - - INTS0 - Indicates active channel interrupt requests which are currently causing IRQ 0 to be asserted. - Channel interrupts can be cleared by writing a bit mask here. - [15:0] - read-write - oneToClear - - - - - INTR1 - 0x00000410 - Interrupt Status (raw) - 0x00000000 - - - INTR1 - Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR, INTS0 or INTS1. - - Channel interrupts can be routed to either of two system-level IRQs based on INTE0 and INTE1. - - This can be used vector different channel interrupts to different ISRs: this might be done to allow NVIC IRQ preemption for more time-critical channels, or to spread IRQ load across different cores. - - It is also valid to ignore this behaviour and just use INTE0/INTS0/IRQ 0. - [15:0] - read-write - oneToClear - - - - - INTE1 - 0x00000414 - Interrupt Enables for IRQ 1 - 0x00000000 - - - INTE1 - Set bit n to pass interrupts from channel n to DMA IRQ 1. - [15:0] - read-write - - - - - INTF1 - 0x00000418 - Force Interrupts for IRQ 1 - 0x00000000 - - - INTF1 - Write 1s to force the corresponding bits in INTE0. The interrupt remains asserted until INTF0 is cleared. - [15:0] - read-write - - - - - INTS1 - 0x0000041c - Interrupt Status (masked) for IRQ 1 - 0x00000000 - - - INTS1 - Indicates active channel interrupt requests which are currently causing IRQ 1 to be asserted. - Channel interrupts can be cleared by writing a bit mask here. - [15:0] - read-write - oneToClear - - - - - TIMER0 - 0x00000420 - Pacing (X/Y) Fractional Timer - The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. - 0x00000000 - - - X - Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer. - [31:16] - read-write - - - Y - Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer. - [15:0] - read-write - - - - - TIMER1 - 0x00000424 - Pacing (X/Y) Fractional Timer - The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. - 0x00000000 - - - X - Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer. - [31:16] - read-write - - - Y - Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer. - [15:0] - read-write - - - - - TIMER2 - 0x00000428 - Pacing (X/Y) Fractional Timer - The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. - 0x00000000 - - - X - Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer. - [31:16] - read-write - - - Y - Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer. - [15:0] - read-write - - - - - TIMER3 - 0x0000042c - Pacing (X/Y) Fractional Timer - The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. - 0x00000000 - - - X - Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer. - [31:16] - read-write - - - Y - Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer. - [15:0] - read-write - - - - - MULTI_CHAN_TRIGGER - 0x00000430 - Trigger one or more channels simultaneously - 0x00000000 - - - MULTI_CHAN_TRIGGER - Each bit in this register corresponds to a DMA channel. Writing a 1 to the relevant bit is the same as writing to that channel's trigger register; the channel will start if it is currently enabled and not already busy. - [15:0] - write-only - - - - - SNIFF_CTRL - 0x00000434 - Sniffer Control - 0x00000000 - - - OUT_INV - If set, the result appears inverted (bitwise complement) when read. This does not affect the way the checksum is calculated; the result is transformed on-the-fly between the result register and the bus. - [11:11] - read-write - - - OUT_REV - If set, the result appears bit-reversed when read. This does not affect the way the checksum is calculated; the result is transformed on-the-fly between the result register and the bus. - [10:10] - read-write - - - BSWAP - Locally perform a byte reverse on the sniffed data, before feeding into checksum. - - Note that the sniff hardware is downstream of the DMA channel byteswap performed in the read master: if channel CTRL_BSWAP and SNIFF_CTRL_BSWAP are both enabled, their effects cancel from the sniffer's point of view. - [9:9] - read-write - - - CALC - [8:5] - read-write - - - CRC32 - 0 - Calculate a CRC-32 (IEEE802.3 polynomial) - - - CRC32R - 1 - Calculate a CRC-32 (IEEE802.3 polynomial) with bit reversed data - - - CRC16 - 2 - Calculate a CRC-16-CCITT - - - CRC16R - 3 - Calculate a CRC-16-CCITT with bit reversed data - - - EVEN - 14 - XOR reduction over all data. == 1 if the total 1 population count is odd. - - - SUM - 15 - Calculate a simple 32-bit checksum (addition with a 32 bit accumulator) - - - - - DMACH - DMA channel for Sniffer to observe - [4:1] - read-write - - - EN - Enable sniffer - [0:0] - read-write - - - - - SNIFF_DATA - 0x00000438 - Data accumulator for sniff hardware - 0x00000000 - - - SNIFF_DATA - Write an initial seed value here before starting a DMA transfer on the channel indicated by SNIFF_CTRL_DMACH. The hardware will update this register each time it observes a read from the indicated channel. Once the channel completes, the final result can be read from this register. - [31:0] - read-write - - - - - FIFO_LEVELS - 0x00000440 - Debug RAF, WAF, TDF levels - 0x00000000 - - - RAF_LVL - Current Read-Address-FIFO fill level - [23:16] - read-only - - - WAF_LVL - Current Write-Address-FIFO fill level - [15:8] - read-only - - - TDF_LVL - Current Transfer-Data-FIFO fill level - [7:0] - read-only - - - - - CHAN_ABORT - 0x00000444 - Abort an in-progress transfer sequence on one or more channels - 0x00000000 - - - CHAN_ABORT - Each bit corresponds to a channel. Writing a 1 aborts whatever transfer sequence is in progress on that channel. The bit will remain high until any in-flight transfers have been flushed through the address and data FIFOs. - - After writing, this register must be polled until it returns all-zero. Until this point, it is unsafe to restart the channel. - [15:0] - write-only - - - - - N_CHANNELS - 0x00000448 - The number of channels this DMA instance is equipped with. This DMA supports up to 16 hardware channels, but can be configured with as few as one, to minimise silicon area. - 0x00000000 - - - N_CHANNELS - [4:0] - read-only - - - - - CH0_DBG_CTDREQ - 0x00000800 - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. - 0x00000000 - - - CH0_DBG_CTDREQ - [5:0] - read-write - oneToClear - - - - - CH0_DBG_TCR - 0x00000804 - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer - 0x00000000 - - - CH0_DBG_TCR - [31:0] - read-only - - - - - CH1_DBG_CTDREQ - 0x00000840 - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. - 0x00000000 - - - CH1_DBG_CTDREQ - [5:0] - read-write - oneToClear - - - - - CH1_DBG_TCR - 0x00000844 - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer - 0x00000000 - - - CH1_DBG_TCR - [31:0] - read-only - - - - - CH2_DBG_CTDREQ - 0x00000880 - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. - 0x00000000 - - - CH2_DBG_CTDREQ - [5:0] - read-write - oneToClear - - - - - CH2_DBG_TCR - 0x00000884 - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer - 0x00000000 - - - CH2_DBG_TCR - [31:0] - read-only - - - - - CH3_DBG_CTDREQ - 0x000008c0 - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. - 0x00000000 - - - CH3_DBG_CTDREQ - [5:0] - read-write - oneToClear - - - - - CH3_DBG_TCR - 0x000008c4 - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer - 0x00000000 - - - CH3_DBG_TCR - [31:0] - read-only - - - - - CH4_DBG_CTDREQ - 0x00000900 - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. - 0x00000000 - - - CH4_DBG_CTDREQ - [5:0] - read-write - oneToClear - - - - - CH4_DBG_TCR - 0x00000904 - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer - 0x00000000 - - - CH4_DBG_TCR - [31:0] - read-only - - - - - CH5_DBG_CTDREQ - 0x00000940 - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. - 0x00000000 - - - CH5_DBG_CTDREQ - [5:0] - read-write - oneToClear - - - - - CH5_DBG_TCR - 0x00000944 - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer - 0x00000000 - - - CH5_DBG_TCR - [31:0] - read-only - - - - - CH6_DBG_CTDREQ - 0x00000980 - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. - 0x00000000 - - - CH6_DBG_CTDREQ - [5:0] - read-write - oneToClear - - - - - CH6_DBG_TCR - 0x00000984 - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer - 0x00000000 - - - CH6_DBG_TCR - [31:0] - read-only - - - - - CH7_DBG_CTDREQ - 0x000009c0 - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. - 0x00000000 - - - CH7_DBG_CTDREQ - [5:0] - read-write - oneToClear - - - - - CH7_DBG_TCR - 0x000009c4 - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer - 0x00000000 - - - CH7_DBG_TCR - [31:0] - read-only - - - - - CH8_DBG_CTDREQ - 0x00000a00 - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. - 0x00000000 - - - CH8_DBG_CTDREQ - [5:0] - read-write - oneToClear - - - - - CH8_DBG_TCR - 0x00000a04 - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer - 0x00000000 - - - CH8_DBG_TCR - [31:0] - read-only - - - - - CH9_DBG_CTDREQ - 0x00000a40 - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. - 0x00000000 - - - CH9_DBG_CTDREQ - [5:0] - read-write - oneToClear - - - - - CH9_DBG_TCR - 0x00000a44 - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer - 0x00000000 - - - CH9_DBG_TCR - [31:0] - read-only - - - - - CH10_DBG_CTDREQ - 0x00000a80 - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. - 0x00000000 - - - CH10_DBG_CTDREQ - [5:0] - read-write - oneToClear - - - - - CH10_DBG_TCR - 0x00000a84 - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer - 0x00000000 - - - CH10_DBG_TCR - [31:0] - read-only - - - - - CH11_DBG_CTDREQ - 0x00000ac0 - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. - 0x00000000 - - - CH11_DBG_CTDREQ - [5:0] - read-write - oneToClear - - - - - CH11_DBG_TCR - 0x00000ac4 - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer - 0x00000000 - - - CH11_DBG_TCR - [31:0] - read-only - - - - - - - TIMER - Controls time and alarms - time is a 64 bit value indicating the time in usec since power-on - timeh is the top 32 bits of time & timel is the bottom 32 bits - to change time write to timelw before timehw - to read time read from timelr before timehr - An alarm is set by setting alarm_enable and writing to the corresponding alarm register - When an alarm is pending, the corresponding alarm_running signal will be high - An alarm can be cancelled before it has finished by clearing the alarm_enable - When an alarm fires, the corresponding alarm_irq is set and alarm_running is cleared - To clear the interrupt write a 1 to the corresponding alarm_irq - 0x40054000 - - 0 - 68 - registers - - - TIMER_IRQ_0 - 0 - - - TIMER_IRQ_1 - 1 - - - TIMER_IRQ_2 - 2 - - - TIMER_IRQ_3 - 3 - - - - TIMEHW - 0x00000000 - Write to bits 63:32 of time - always write timelw before timehw - 0x00000000 - - - TIMEHW - [31:0] - write-only - - - - - TIMELW - 0x00000004 - Write to bits 31:0 of time - writes do not get copied to time until timehw is written - 0x00000000 - - - TIMELW - [31:0] - write-only - - - - - TIMEHR - 0x00000008 - Read from bits 63:32 of time - always read timelr before timehr - 0x00000000 - - - TIMEHR - [31:0] - read-only - - - - - TIMELR - 0x0000000c - Read from bits 31:0 of time - 0x00000000 - - - TIMELR - [31:0] - read-only - modify - - - - - ALARM0 - 0x00000010 - Arm alarm 0, and configure the time it will fire. - Once armed, the alarm fires when TIMER_ALARM0 == TIMELR. - The alarm will disarm itself once it fires, and can - be disarmed early using the ARMED status register. - 0x00000000 - - - ALARM0 - [31:0] - read-write - - - - - ALARM1 - 0x00000014 - Arm alarm 1, and configure the time it will fire. - Once armed, the alarm fires when TIMER_ALARM1 == TIMELR. - The alarm will disarm itself once it fires, and can - be disarmed early using the ARMED status register. - 0x00000000 - - - ALARM1 - [31:0] - read-write - - - - - ALARM2 - 0x00000018 - Arm alarm 2, and configure the time it will fire. - Once armed, the alarm fires when TIMER_ALARM2 == TIMELR. - The alarm will disarm itself once it fires, and can - be disarmed early using the ARMED status register. - 0x00000000 - - - ALARM2 - [31:0] - read-write - - - - - ALARM3 - 0x0000001c - Arm alarm 3, and configure the time it will fire. - Once armed, the alarm fires when TIMER_ALARM3 == TIMELR. - The alarm will disarm itself once it fires, and can - be disarmed early using the ARMED status register. - 0x00000000 - - - ALARM3 - [31:0] - read-write - - - - - ARMED - 0x00000020 - Indicates the armed/disarmed status of each alarm. - A write to the corresponding ALARMx register arms the alarm. - Alarms automatically disarm upon firing, but writing ones here - will disarm immediately without waiting to fire. - 0x00000000 - - - ARMED - [3:0] - read-write - oneToClear - - - - - TIMERAWH - 0x00000024 - Raw read from bits 63:32 of time (no side effects) - 0x00000000 - - - TIMERAWH - [31:0] - read-only - - - - - TIMERAWL - 0x00000028 - Raw read from bits 31:0 of time (no side effects) - 0x00000000 - - - TIMERAWL - [31:0] - read-only - - - - - DBGPAUSE - 0x0000002c - Set bits high to enable pause when the corresponding debug ports are active - 0x00000007 - - - DBG1 - Pause when processor 1 is in debug mode - [2:2] - read-write - - - DBG0 - Pause when processor 0 is in debug mode - [1:1] - read-write - - - - - PAUSE - 0x00000030 - Set high to pause the timer - 0x00000000 - - - PAUSE - [0:0] - read-write - - - - - INTR - 0x00000034 - Raw Interrupts - 0x00000000 - - - ALARM_3 - [3:3] - read-write - oneToClear - - - ALARM_2 - [2:2] - read-write - oneToClear - - - ALARM_1 - [1:1] - read-write - oneToClear - - - ALARM_0 - [0:0] - read-write - oneToClear - - - - - INTE - 0x00000038 - Interrupt Enable - 0x00000000 - - - ALARM_3 - [3:3] - read-write - - - ALARM_2 - [2:2] - read-write - - - ALARM_1 - [1:1] - read-write - - - ALARM_0 - [0:0] - read-write - - - - - INTF - 0x0000003c - Interrupt Force - 0x00000000 - - - ALARM_3 - [3:3] - read-write - - - ALARM_2 - [2:2] - read-write - - - ALARM_1 - [1:1] - read-write - - - ALARM_0 - [0:0] - read-write - - - - - INTS - 0x00000040 - Interrupt status after masking & forcing - 0x00000000 - - - ALARM_3 - [3:3] - read-only - - - ALARM_2 - [2:2] - read-only - - - ALARM_1 - [1:1] - read-only - - - ALARM_0 - [0:0] - read-only - - - - - - - PWM - Simple PWM - 0x40050000 - - 0 - 180 - registers - - - PWM_IRQ_WRAP - 4 - - - - CH0_CSR - 0x00000000 - Control and status register - 0x00000000 - - - PH_ADV - Advance the phase of the counter by 1 count, while it is running. - Self-clearing. Write a 1, and poll until low. Counter must be running - at less than full speed (div_int + div_frac / 16 > 1) - [7:7] - write-only - - - PH_RET - Retard the phase of the counter by 1 count, while it is running. - Self-clearing. Write a 1, and poll until low. Counter must be running. - [6:6] - write-only - - - DIVMODE - [5:4] - read-write - - - div - 0 - Free-running counting at rate dictated by fractional divider - - - level - 1 - Fractional divider operation is gated by the PWM B pin. - - - rise - 2 - Counter advances with each rising edge of the PWM B pin. - - - fall - 3 - Counter advances with each falling edge of the PWM B pin. - - - - - B_INV - Invert output B - [3:3] - read-write - - - A_INV - Invert output A - [2:2] - read-write - - - PH_CORRECT - 1: Enable phase-correct modulation. 0: Trailing-edge - [1:1] - read-write - - - EN - Enable the PWM channel. - [0:0] - read-write - - - - - CH0_DIV - 0x00000004 - INT and FRAC form a fixed-point fractional number. - Counting rate is system clock frequency divided by this number. - Fractional division uses simple 1st-order sigma-delta. - 0x00000010 - - - INT - [11:4] - read-write - - - FRAC - [3:0] - read-write - - - - - CH0_CTR - 0x00000008 - Direct access to the PWM counter - 0x00000000 - - - CH0_CTR - [15:0] - read-write - - - - - CH0_CC - 0x0000000c - Counter compare values - 0x00000000 - - - B - [31:16] - read-write - - - A - [15:0] - read-write - - - - - CH0_TOP - 0x00000010 - Counter wrap value - 0x0000ffff - - - CH0_TOP - [15:0] - read-write - - - - - CH1_CSR - 0x00000014 - Control and status register - 0x00000000 - - - PH_ADV - Advance the phase of the counter by 1 count, while it is running. - Self-clearing. Write a 1, and poll until low. Counter must be running - at less than full speed (div_int + div_frac / 16 > 1) - [7:7] - write-only - - - PH_RET - Retard the phase of the counter by 1 count, while it is running. - Self-clearing. Write a 1, and poll until low. Counter must be running. - [6:6] - write-only - - - DIVMODE - [5:4] - read-write - - - div - 0 - Free-running counting at rate dictated by fractional divider - - - level - 1 - Fractional divider operation is gated by the PWM B pin. - - - rise - 2 - Counter advances with each rising edge of the PWM B pin. - - - fall - 3 - Counter advances with each falling edge of the PWM B pin. - - - - - B_INV - Invert output B - [3:3] - read-write - - - A_INV - Invert output A - [2:2] - read-write - - - PH_CORRECT - 1: Enable phase-correct modulation. 0: Trailing-edge - [1:1] - read-write - - - EN - Enable the PWM channel. - [0:0] - read-write - - - - - CH1_DIV - 0x00000018 - INT and FRAC form a fixed-point fractional number. - Counting rate is system clock frequency divided by this number. - Fractional division uses simple 1st-order sigma-delta. - 0x00000010 - - - INT - [11:4] - read-write - - - FRAC - [3:0] - read-write - - - - - CH1_CTR - 0x0000001c - Direct access to the PWM counter - 0x00000000 - - - CH1_CTR - [15:0] - read-write - - - - - CH1_CC - 0x00000020 - Counter compare values - 0x00000000 - - - B - [31:16] - read-write - - - A - [15:0] - read-write - - - - - CH1_TOP - 0x00000024 - Counter wrap value - 0x0000ffff - - - CH1_TOP - [15:0] - read-write - - - - - CH2_CSR - 0x00000028 - Control and status register - 0x00000000 - - - PH_ADV - Advance the phase of the counter by 1 count, while it is running. - Self-clearing. Write a 1, and poll until low. Counter must be running - at less than full speed (div_int + div_frac / 16 > 1) - [7:7] - write-only - - - PH_RET - Retard the phase of the counter by 1 count, while it is running. - Self-clearing. Write a 1, and poll until low. Counter must be running. - [6:6] - write-only - - - DIVMODE - [5:4] - read-write - - - div - 0 - Free-running counting at rate dictated by fractional divider - - - level - 1 - Fractional divider operation is gated by the PWM B pin. - - - rise - 2 - Counter advances with each rising edge of the PWM B pin. - - - fall - 3 - Counter advances with each falling edge of the PWM B pin. - - - - - B_INV - Invert output B - [3:3] - read-write - - - A_INV - Invert output A - [2:2] - read-write - - - PH_CORRECT - 1: Enable phase-correct modulation. 0: Trailing-edge - [1:1] - read-write - - - EN - Enable the PWM channel. - [0:0] - read-write - - - - - CH2_DIV - 0x0000002c - INT and FRAC form a fixed-point fractional number. - Counting rate is system clock frequency divided by this number. - Fractional division uses simple 1st-order sigma-delta. - 0x00000010 - - - INT - [11:4] - read-write - - - FRAC - [3:0] - read-write - - - - - CH2_CTR - 0x00000030 - Direct access to the PWM counter - 0x00000000 - - - CH2_CTR - [15:0] - read-write - - - - - CH2_CC - 0x00000034 - Counter compare values - 0x00000000 - - - B - [31:16] - read-write - - - A - [15:0] - read-write - - - - - CH2_TOP - 0x00000038 - Counter wrap value - 0x0000ffff - - - CH2_TOP - [15:0] - read-write - - - - - CH3_CSR - 0x0000003c - Control and status register - 0x00000000 - - - PH_ADV - Advance the phase of the counter by 1 count, while it is running. - Self-clearing. Write a 1, and poll until low. Counter must be running - at less than full speed (div_int + div_frac / 16 > 1) - [7:7] - write-only - - - PH_RET - Retard the phase of the counter by 1 count, while it is running. - Self-clearing. Write a 1, and poll until low. Counter must be running. - [6:6] - write-only - - - DIVMODE - [5:4] - read-write - - - div - 0 - Free-running counting at rate dictated by fractional divider - - - level - 1 - Fractional divider operation is gated by the PWM B pin. - - - rise - 2 - Counter advances with each rising edge of the PWM B pin. - - - fall - 3 - Counter advances with each falling edge of the PWM B pin. - - - - - B_INV - Invert output B - [3:3] - read-write - - - A_INV - Invert output A - [2:2] - read-write - - - PH_CORRECT - 1: Enable phase-correct modulation. 0: Trailing-edge - [1:1] - read-write - - - EN - Enable the PWM channel. - [0:0] - read-write - - - - - CH3_DIV - 0x00000040 - INT and FRAC form a fixed-point fractional number. - Counting rate is system clock frequency divided by this number. - Fractional division uses simple 1st-order sigma-delta. - 0x00000010 - - - INT - [11:4] - read-write - - - FRAC - [3:0] - read-write - - - - - CH3_CTR - 0x00000044 - Direct access to the PWM counter - 0x00000000 - - - CH3_CTR - [15:0] - read-write - - - - - CH3_CC - 0x00000048 - Counter compare values - 0x00000000 - - - B - [31:16] - read-write - - - A - [15:0] - read-write - - - - - CH3_TOP - 0x0000004c - Counter wrap value - 0x0000ffff - - - CH3_TOP - [15:0] - read-write - - - - - CH4_CSR - 0x00000050 - Control and status register - 0x00000000 - - - PH_ADV - Advance the phase of the counter by 1 count, while it is running. - Self-clearing. Write a 1, and poll until low. Counter must be running - at less than full speed (div_int + div_frac / 16 > 1) - [7:7] - write-only - - - PH_RET - Retard the phase of the counter by 1 count, while it is running. - Self-clearing. Write a 1, and poll until low. Counter must be running. - [6:6] - write-only - - - DIVMODE - [5:4] - read-write - - - div - 0 - Free-running counting at rate dictated by fractional divider - - - level - 1 - Fractional divider operation is gated by the PWM B pin. - - - rise - 2 - Counter advances with each rising edge of the PWM B pin. - - - fall - 3 - Counter advances with each falling edge of the PWM B pin. - - - - - B_INV - Invert output B - [3:3] - read-write - - - A_INV - Invert output A - [2:2] - read-write - - - PH_CORRECT - 1: Enable phase-correct modulation. 0: Trailing-edge - [1:1] - read-write - - - EN - Enable the PWM channel. - [0:0] - read-write - - - - - CH4_DIV - 0x00000054 - INT and FRAC form a fixed-point fractional number. - Counting rate is system clock frequency divided by this number. - Fractional division uses simple 1st-order sigma-delta. - 0x00000010 - - - INT - [11:4] - read-write - - - FRAC - [3:0] - read-write - - - - - CH4_CTR - 0x00000058 - Direct access to the PWM counter - 0x00000000 - - - CH4_CTR - [15:0] - read-write - - - - - CH4_CC - 0x0000005c - Counter compare values - 0x00000000 - - - B - [31:16] - read-write - - - A - [15:0] - read-write - - - - - CH4_TOP - 0x00000060 - Counter wrap value - 0x0000ffff - - - CH4_TOP - [15:0] - read-write - - - - - CH5_CSR - 0x00000064 - Control and status register - 0x00000000 - - - PH_ADV - Advance the phase of the counter by 1 count, while it is running. - Self-clearing. Write a 1, and poll until low. Counter must be running - at less than full speed (div_int + div_frac / 16 > 1) - [7:7] - write-only - - - PH_RET - Retard the phase of the counter by 1 count, while it is running. - Self-clearing. Write a 1, and poll until low. Counter must be running. - [6:6] - write-only - - - DIVMODE - [5:4] - read-write - - - div - 0 - Free-running counting at rate dictated by fractional divider - - - level - 1 - Fractional divider operation is gated by the PWM B pin. - - - rise - 2 - Counter advances with each rising edge of the PWM B pin. - - - fall - 3 - Counter advances with each falling edge of the PWM B pin. - - - - - B_INV - Invert output B - [3:3] - read-write - - - A_INV - Invert output A - [2:2] - read-write - - - PH_CORRECT - 1: Enable phase-correct modulation. 0: Trailing-edge - [1:1] - read-write - - - EN - Enable the PWM channel. - [0:0] - read-write - - - - - CH5_DIV - 0x00000068 - INT and FRAC form a fixed-point fractional number. - Counting rate is system clock frequency divided by this number. - Fractional division uses simple 1st-order sigma-delta. - 0x00000010 - - - INT - [11:4] - read-write - - - FRAC - [3:0] - read-write - - - - - CH5_CTR - 0x0000006c - Direct access to the PWM counter - 0x00000000 - - - CH5_CTR - [15:0] - read-write - - - - - CH5_CC - 0x00000070 - Counter compare values - 0x00000000 - - - B - [31:16] - read-write - - - A - [15:0] - read-write - - - - - CH5_TOP - 0x00000074 - Counter wrap value - 0x0000ffff - - - CH5_TOP - [15:0] - read-write - - - - - CH6_CSR - 0x00000078 - Control and status register - 0x00000000 - - - PH_ADV - Advance the phase of the counter by 1 count, while it is running. - Self-clearing. Write a 1, and poll until low. Counter must be running - at less than full speed (div_int + div_frac / 16 > 1) - [7:7] - write-only - - - PH_RET - Retard the phase of the counter by 1 count, while it is running. - Self-clearing. Write a 1, and poll until low. Counter must be running. - [6:6] - write-only - - - DIVMODE - [5:4] - read-write - - - div - 0 - Free-running counting at rate dictated by fractional divider - - - level - 1 - Fractional divider operation is gated by the PWM B pin. - - - rise - 2 - Counter advances with each rising edge of the PWM B pin. - - - fall - 3 - Counter advances with each falling edge of the PWM B pin. - - - - - B_INV - Invert output B - [3:3] - read-write - - - A_INV - Invert output A - [2:2] - read-write - - - PH_CORRECT - 1: Enable phase-correct modulation. 0: Trailing-edge - [1:1] - read-write - - - EN - Enable the PWM channel. - [0:0] - read-write - - - - - CH6_DIV - 0x0000007c - INT and FRAC form a fixed-point fractional number. - Counting rate is system clock frequency divided by this number. - Fractional division uses simple 1st-order sigma-delta. - 0x00000010 - - - INT - [11:4] - read-write - - - FRAC - [3:0] - read-write - - - - - CH6_CTR - 0x00000080 - Direct access to the PWM counter - 0x00000000 - - - CH6_CTR - [15:0] - read-write - - - - - CH6_CC - 0x00000084 - Counter compare values - 0x00000000 - - - B - [31:16] - read-write - - - A - [15:0] - read-write - - - - - CH6_TOP - 0x00000088 - Counter wrap value - 0x0000ffff - - - CH6_TOP - [15:0] - read-write - - - - - CH7_CSR - 0x0000008c - Control and status register - 0x00000000 - - - PH_ADV - Advance the phase of the counter by 1 count, while it is running. - Self-clearing. Write a 1, and poll until low. Counter must be running - at less than full speed (div_int + div_frac / 16 > 1) - [7:7] - write-only - - - PH_RET - Retard the phase of the counter by 1 count, while it is running. - Self-clearing. Write a 1, and poll until low. Counter must be running. - [6:6] - write-only - - - DIVMODE - [5:4] - read-write - - - div - 0 - Free-running counting at rate dictated by fractional divider - - - level - 1 - Fractional divider operation is gated by the PWM B pin. - - - rise - 2 - Counter advances with each rising edge of the PWM B pin. - - - fall - 3 - Counter advances with each falling edge of the PWM B pin. - - - - - B_INV - Invert output B - [3:3] - read-write - - - A_INV - Invert output A - [2:2] - read-write - - - PH_CORRECT - 1: Enable phase-correct modulation. 0: Trailing-edge - [1:1] - read-write - - - EN - Enable the PWM channel. - [0:0] - read-write - - - - - CH7_DIV - 0x00000090 - INT and FRAC form a fixed-point fractional number. - Counting rate is system clock frequency divided by this number. - Fractional division uses simple 1st-order sigma-delta. - 0x00000010 - - - INT - [11:4] - read-write - - - FRAC - [3:0] - read-write - - - - - CH7_CTR - 0x00000094 - Direct access to the PWM counter - 0x00000000 - - - CH7_CTR - [15:0] - read-write - - - - - CH7_CC - 0x00000098 - Counter compare values - 0x00000000 - - - B - [31:16] - read-write - - - A - [15:0] - read-write - - - - - CH7_TOP - 0x0000009c - Counter wrap value - 0x0000ffff - - - CH7_TOP - [15:0] - read-write - - - - - EN - 0x000000a0 - This register aliases the CSR_EN bits for all channels. - Writing to this register allows multiple channels to be enabled - or disabled simultaneously, so they can run in perfect sync. - For each channel, there is only one physical EN register bit, - which can be accessed through here or CHx_CSR. - 0x00000000 - - - CH7 - [7:7] - read-write - - - CH6 - [6:6] - read-write - - - CH5 - [5:5] - read-write - - - CH4 - [4:4] - read-write - - - CH3 - [3:3] - read-write - - - CH2 - [2:2] - read-write - - - CH1 - [1:1] - read-write - - - CH0 - [0:0] - read-write - - - - - INTR - 0x000000a4 - Raw Interrupts - 0x00000000 - - - CH7 - [7:7] - read-write - oneToClear - - - CH6 - [6:6] - read-write - oneToClear - - - CH5 - [5:5] - read-write - oneToClear - - - CH4 - [4:4] - read-write - oneToClear - - - CH3 - [3:3] - read-write - oneToClear - - - CH2 - [2:2] - read-write - oneToClear - - - CH1 - [1:1] - read-write - oneToClear - - - CH0 - [0:0] - read-write - oneToClear - - - - - INTE - 0x000000a8 - Interrupt Enable - 0x00000000 - - - CH7 - [7:7] - read-write - - - CH6 - [6:6] - read-write - - - CH5 - [5:5] - read-write - - - CH4 - [4:4] - read-write - - - CH3 - [3:3] - read-write - - - CH2 - [2:2] - read-write - - - CH1 - [1:1] - read-write - - - CH0 - [0:0] - read-write - - - - - INTF - 0x000000ac - Interrupt Force - 0x00000000 - - - CH7 - [7:7] - read-write - - - CH6 - [6:6] - read-write - - - CH5 - [5:5] - read-write - - - CH4 - [4:4] - read-write - - - CH3 - [3:3] - read-write - - - CH2 - [2:2] - read-write - - - CH1 - [1:1] - read-write - - - CH0 - [0:0] - read-write - - - - - INTS - 0x000000b0 - Interrupt status after masking & forcing - 0x00000000 - - - CH7 - [7:7] - read-only - - - CH6 - [6:6] - read-only - - - CH5 - [5:5] - read-only - - - CH4 - [4:4] - read-only - - - CH3 - [3:3] - read-only - - - CH2 - [2:2] - read-only - - - CH1 - [1:1] - read-only - - - CH0 - [0:0] - read-only - - - - - - - ADC - Control and data interface to SAR ADC - 0x4004c000 - - 0 - 36 - registers - - - ADC_IRQ_FIFO - 22 - - - - CS - 0x00000000 - ADC Control and Status - 0x00000000 - - - RROBIN - Round-robin sampling. 1 bit per channel. Set all bits to 0 to disable. - Otherwise, the ADC will cycle through each enabled channel in a round-robin fashion. - The first channel to be sampled will be the one currently indicated by AINSEL. - AINSEL will be updated after each conversion with the newly-selected channel. - [20:16] - read-write - - - AINSEL - Select analog mux input. Updated automatically in round-robin mode. - [14:12] - read-write - - - ERR_STICKY - Some past ADC conversion encountered an error. Write 1 to clear. - [10:10] - read-write - oneToClear - - - ERR - The most recent ADC conversion encountered an error; result is undefined or noisy. - [9:9] - read-only - - - READY - 1 if the ADC is ready to start a new conversion. Implies any previous conversion has completed. - 0 whilst conversion in progress. - [8:8] - read-only - - - START_MANY - Continuously perform conversions whilst this bit is 1. A new conversion will start immediately after the previous finishes. - [3:3] - read-write - - - START_ONCE - Start a single conversion. Self-clearing. Ignored if start_many is asserted. - [2:2] - write-only - - - TS_EN - Power on temperature sensor. 1 - enabled. 0 - disabled. - [1:1] - read-write - - - EN - Power on ADC and enable its clock. - 1 - enabled. 0 - disabled. - [0:0] - read-write - - - - - RESULT - 0x00000004 - Result of most recent ADC conversion - 0x00000000 - - - RESULT - [11:0] - read-only - - - - - FCS - 0x00000008 - FIFO control and status - 0x00000000 - - - THRESH - DREQ/IRQ asserted when level >= threshold - [27:24] - read-write - - - LEVEL - The number of conversion results currently waiting in the FIFO - [19:16] - read-only - - - OVER - 1 if the FIFO has been overflowed. Write 1 to clear. - [11:11] - read-write - oneToClear - - - UNDER - 1 if the FIFO has been underflowed. Write 1 to clear. - [10:10] - read-write - oneToClear - - - FULL - [9:9] - read-only - - - EMPTY - [8:8] - read-only - - - DREQ_EN - If 1: assert DMA requests when FIFO contains data - [3:3] - read-write - - - ERR - If 1: conversion error bit appears in the FIFO alongside the result - [2:2] - read-write - - - SHIFT - If 1: FIFO results are right-shifted to be one byte in size. Enables DMA to byte buffers. - [1:1] - read-write - - - EN - If 1: write result to the FIFO after each conversion. - [0:0] - read-write - - - - - FIFO - 0x0000000c - Conversion result FIFO - 0x00000000 - - - ERR - 1 if this particular sample experienced a conversion error. Remains in the same location if the sample is shifted. - [15:15] - read-only - modify - - - VAL - [11:0] - read-only - modify - - - - - DIV - 0x00000010 - Clock divider. If non-zero, CS_START_MANY will start conversions - at regular intervals rather than back-to-back. - The divider is reset when either of these fields are written. - Total period is 1 + INT + FRAC / 256 - 0x00000000 - - - INT - Integer part of clock divisor. - [23:8] - read-write - - - FRAC - Fractional part of clock divisor. First-order delta-sigma. - [7:0] - read-write - - - - - INTR - 0x00000014 - Raw Interrupts - 0x00000000 - - - FIFO - Triggered when the sample FIFO reaches a certain level. - This level can be programmed via the FCS_THRESH field. - [0:0] - read-only - - - - - INTE - 0x00000018 - Interrupt Enable - 0x00000000 - - - FIFO - Triggered when the sample FIFO reaches a certain level. - This level can be programmed via the FCS_THRESH field. - [0:0] - read-write - - - - - INTF - 0x0000001c - Interrupt Force - 0x00000000 - - - FIFO - Triggered when the sample FIFO reaches a certain level. - This level can be programmed via the FCS_THRESH field. - [0:0] - read-write - - - - - INTS - 0x00000020 - Interrupt status after masking & forcing - 0x00000000 - - - FIFO - Triggered when the sample FIFO reaches a certain level. - This level can be programmed via the FCS_THRESH field. - [0:0] - read-only - - - - - - - I2C0 - DW_apb_i2c address block - - List of configuration constants for the Synopsys I2C hardware (you may see references to these in I2C register header; these are *fixed* values, set at hardware design time): - - IC_ULTRA_FAST_MODE ................ 0x0 - IC_UFM_TBUF_CNT_DEFAULT ........... 0x8 - IC_UFM_SCL_LOW_COUNT .............. 0x0008 - IC_UFM_SCL_HIGH_COUNT ............. 0x0006 - IC_TX_TL .......................... 0x0 - IC_TX_CMD_BLOCK ................... 0x1 - IC_HAS_DMA ........................ 0x1 - IC_HAS_ASYNC_FIFO ................. 0x0 - IC_SMBUS_ARP ...................... 0x0 - IC_FIRST_DATA_BYTE_STATUS ......... 0x1 - IC_INTR_IO ........................ 0x1 - IC_MASTER_MODE .................... 0x1 - IC_DEFAULT_ACK_GENERAL_CALL ....... 0x1 - IC_INTR_POL ....................... 0x1 - IC_OPTIONAL_SAR ................... 0x0 - IC_DEFAULT_TAR_SLAVE_ADDR ......... 0x055 - IC_DEFAULT_SLAVE_ADDR ............. 0x055 - IC_DEFAULT_HS_SPKLEN .............. 0x1 - IC_FS_SCL_HIGH_COUNT .............. 0x0006 - IC_HS_SCL_LOW_COUNT ............... 0x0008 - IC_DEVICE_ID_VALUE ................ 0x0 - IC_10BITADDR_MASTER ............... 0x0 - IC_CLK_FREQ_OPTIMIZATION .......... 0x0 - IC_DEFAULT_FS_SPKLEN .............. 0x7 - IC_ADD_ENCODED_PARAMS ............. 0x0 - IC_DEFAULT_SDA_HOLD ............... 0x000001 - IC_DEFAULT_SDA_SETUP .............. 0x64 - IC_AVOID_RX_FIFO_FLUSH_ON_TX_ABRT . 0x0 - IC_CLOCK_PERIOD ................... 100 - IC_EMPTYFIFO_HOLD_MASTER_EN ....... 1 - IC_RESTART_EN ..................... 0x1 - IC_TX_CMD_BLOCK_DEFAULT ........... 0x0 - IC_BUS_CLEAR_FEATURE .............. 0x0 - IC_CAP_LOADING .................... 100 - IC_FS_SCL_LOW_COUNT ............... 0x000d - APB_DATA_WIDTH .................... 32 - IC_SDA_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff - IC_SLV_DATA_NACK_ONLY ............. 0x1 - IC_10BITADDR_SLAVE ................ 0x0 - IC_CLK_TYPE ....................... 0x0 - IC_SMBUS_UDID_MSB ................. 0x0 - IC_SMBUS_SUSPEND_ALERT ............ 0x0 - IC_HS_SCL_HIGH_COUNT .............. 0x0006 - IC_SLV_RESTART_DET_EN ............. 0x1 - IC_SMBUS .......................... 0x0 - IC_OPTIONAL_SAR_DEFAULT ........... 0x0 - IC_PERSISTANT_SLV_ADDR_DEFAULT .... 0x0 - IC_USE_COUNTS ..................... 0x0 - IC_RX_BUFFER_DEPTH ................ 16 - IC_SCL_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff - IC_RX_FULL_HLD_BUS_EN ............. 0x1 - IC_SLAVE_DISABLE .................. 0x1 - IC_RX_TL .......................... 0x0 - IC_DEVICE_ID ...................... 0x0 - IC_HC_COUNT_VALUES ................ 0x0 - I2C_DYNAMIC_TAR_UPDATE ............ 0 - IC_SMBUS_CLK_LOW_MEXT_DEFAULT ..... 0xffffffff - IC_SMBUS_CLK_LOW_SEXT_DEFAULT ..... 0xffffffff - IC_HS_MASTER_CODE ................. 0x1 - IC_SMBUS_RST_IDLE_CNT_DEFAULT ..... 0xffff - IC_SMBUS_UDID_LSB_DEFAULT ......... 0xffffffff - IC_SS_SCL_HIGH_COUNT .............. 0x0028 - IC_SS_SCL_LOW_COUNT ............... 0x002f - IC_MAX_SPEED_MODE ................. 0x2 - IC_STAT_FOR_CLK_STRETCH ........... 0x0 - IC_STOP_DET_IF_MASTER_ACTIVE ...... 0x0 - IC_DEFAULT_UFM_SPKLEN ............. 0x1 - IC_TX_BUFFER_DEPTH ................ 16 - 0x40044000 - - 0 - 256 - registers - - - I2C0_IRQ - 23 - - - - IC_CON - 0x00000000 - I2C Control Register. This register can be written only when the DW_apb_i2c is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect. - - Read/Write Access: - bit 10 is read only. - bit 11 is read only - bit 16 is read only - bit 17 is read only - bits 18 and 19 are read only. - 0x00000065 - - - STOP_DET_IF_MASTER_ACTIVE - Master issues the STOP_DET interrupt irrespective of whether master is active or not - [10:10] - read-only - - - RX_FIFO_FULL_HLD_CTRL - This bit controls whether DW_apb_i2c should hold the bus when the Rx FIFO is physically full to its RX_BUFFER_DEPTH, as described in the IC_RX_FULL_HLD_BUS_EN parameter. - - Reset value: 0x0. - [9:9] - read-write - - - DISABLED - 0 - Overflow when RX_FIFO is full - - - ENABLED - 1 - Hold bus when RX_FIFO is full - - - - - TX_EMPTY_CTRL - This bit controls the generation of the TX_EMPTY interrupt, as described in the IC_RAW_INTR_STAT register. - - Reset value: 0x0. - [8:8] - read-write - - - DISABLED - 0 - Default behaviour of TX_EMPTY interrupt - - - ENABLED - 1 - Controlled generation of TX_EMPTY interrupt - - - - - STOP_DET_IFADDRESSED - In slave mode: - 1'b1: issues the STOP_DET interrupt only when it is addressed. - 1'b0: issues the STOP_DET irrespective of whether it's addressed or not. Reset value: 0x0 - - NOTE: During a general call address, this slave does not issue the STOP_DET interrupt if STOP_DET_IF_ADDRESSED = 1'b1, even if the slave responds to the general call address by generating ACK. The STOP_DET interrupt is generated only when the transmitted address matches the slave address (SAR). - [7:7] - read-write - - - DISABLED - 0 - slave issues STOP_DET intr always - - - ENABLED - 1 - slave issues STOP_DET intr only if addressed - - - - - IC_SLAVE_DISABLE - This bit controls whether I2C has its slave disabled, which means once the presetn signal is applied, then this bit is set and the slave is disabled. - - If this bit is set (slave is disabled), DW_apb_i2c functions only as a master and does not perform any action that requires a slave. - - NOTE: Software should ensure that if this bit is written with 0, then bit 0 should also be written with a 0. - [6:6] - read-write - - - SLAVE_ENABLED - 0 - Slave mode is enabled - - - SLAVE_DISABLED - 1 - Slave mode is disabled - - - - - IC_RESTART_EN - Determines whether RESTART conditions may be sent when acting as a master. Some older slaves do not support handling RESTART conditions; however, RESTART conditions are used in several DW_apb_i2c operations. When RESTART is disabled, the master is prohibited from performing the following functions: - Sending a START BYTE - Performing any high-speed mode operation - High-speed mode operation - Performing direction changes in combined format mode - Performing a read operation with a 10-bit address By replacing RESTART condition followed by a STOP and a subsequent START condition, split operations are broken down into multiple DW_apb_i2c transfers. If the above operations are performed, it will result in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register. - - Reset value: ENABLED - [5:5] - read-write - - - DISABLED - 0 - Master restart disabled - - - ENABLED - 1 - Master restart enabled - - - - - IC_10BITADDR_MASTER - Controls whether the DW_apb_i2c starts its transfers in 7- or 10-bit addressing mode when acting as a master. - 0: 7-bit addressing - 1: 10-bit addressing - [4:4] - read-write - - - ADDR_7BITS - 0 - Master 7Bit addressing mode - - - ADDR_10BITS - 1 - Master 10Bit addressing mode - - - - - IC_10BITADDR_SLAVE - When acting as a slave, this bit controls whether the DW_apb_i2c responds to 7- or 10-bit addresses. - 0: 7-bit addressing. The DW_apb_i2c ignores transactions that involve 10-bit addressing; for 7-bit addressing, only the lower 7 bits of the IC_SAR register are compared. - 1: 10-bit addressing. The DW_apb_i2c responds to only 10-bit addressing transfers that match the full 10 bits of the IC_SAR register. - [3:3] - read-write - - - ADDR_7BITS - 0 - Slave 7Bit addressing - - - ADDR_10BITS - 1 - Slave 10Bit addressing - - - - - SPEED - These bits control at which speed the DW_apb_i2c operates; its setting is relevant only if one is operating the DW_apb_i2c in master mode. Hardware protects against illegal values being programmed by software. These bits must be programmed appropriately for slave mode also, as it is used to capture correct value of spike filter as per the speed mode. - - This register should be programmed only with a value in the range of 1 to IC_MAX_SPEED_MODE; otherwise, hardware updates this register with the value of IC_MAX_SPEED_MODE. - - 1: standard mode (100 kbit/s) - - 2: fast mode (<=400 kbit/s) or fast mode plus (<=1000Kbit/s) - - 3: high speed mode (3.4 Mbit/s) - - Note: This field is not applicable when IC_ULTRA_FAST_MODE=1 - [2:1] - read-write - - - STANDARD - 1 - Standard Speed mode of operation - - - FAST - 2 - Fast or Fast Plus mode of operation - - - HIGH - 3 - High Speed mode of operation - - - - - MASTER_MODE - This bit controls whether the DW_apb_i2c master is enabled. - - NOTE: Software should ensure that if this bit is written with '1' then bit 6 should also be written with a '1'. - [0:0] - read-write - - - DISABLED - 0 - Master mode is disabled - - - ENABLED - 1 - Master mode is enabled - - - - - - - IC_TAR - 0x00000004 - I2C Target Address Register - - This register is 12 bits wide, and bits 31:12 are reserved. This register can be written to only when IC_ENABLE[0] is set to 0. - - Note: If the software or application is aware that the DW_apb_i2c is not using the TAR address for the pending commands in the Tx FIFO, then it is possible to update the TAR address even while the Tx FIFO has entries (IC_STATUS[2]= 0). - It is not necessary to perform any write to this register if DW_apb_i2c is enabled as an I2C slave only. - 0x00000055 - - - SPECIAL - This bit indicates whether software performs a Device-ID or General Call or START BYTE command. - 0: ignore bit 10 GC_OR_START and use IC_TAR normally - 1: perform special I2C command as specified in Device_ID or GC_OR_START bit Reset value: 0x0 - [11:11] - read-write - - - DISABLED - 0 - Disables programming of GENERAL_CALL or START_BYTE transmission - - - ENABLED - 1 - Enables programming of GENERAL_CALL or START_BYTE transmission - - - - - GC_OR_START - If bit 11 (SPECIAL) is set to 1 and bit 13(Device-ID) is set to 0, then this bit indicates whether a General Call or START byte command is to be performed by the DW_apb_i2c. - 0: General Call Address - after issuing a General Call, only writes may be performed. Attempting to issue a read command results in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register. The DW_apb_i2c remains in General Call mode until the SPECIAL bit value (bit 11) is cleared. - 1: START BYTE Reset value: 0x0 - [10:10] - read-write - - - GENERAL_CALL - 0 - GENERAL_CALL byte transmission - - - START_BYTE - 1 - START byte transmission - - - - - IC_TAR - This is the target address for any master transaction. When transmitting a General Call, these bits are ignored. To generate a START BYTE, the CPU needs to write only once into these bits. - - If the IC_TAR and IC_SAR are the same, loopback exists but the FIFOs are shared between master and slave, so full loopback is not feasible. Only one direction loopback mode is supported (simplex), not duplex. A master cannot transmit to itself; it can transmit to only a slave. - [9:0] - read-write - - - - - IC_SAR - 0x00000008 - I2C Slave Address Register - 0x00000055 - - - IC_SAR - The IC_SAR holds the slave address when the I2C is operating as a slave. For 7-bit addressing, only IC_SAR[6:0] is used. - - This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect. - - Note: The default values cannot be any of the reserved address locations: that is, 0x00 to 0x07, or 0x78 to 0x7f. The correct operation of the device is not guaranteed if you program the IC_SAR or IC_TAR to a reserved value. Refer to <<table_I2C_firstbyte_bit_defs>> for a complete list of these reserved values. - [9:0] - read-write - - - - - IC_DATA_CMD - 0x00000010 - I2C Rx/Tx Data Buffer and Command Register; this is the register the CPU writes to when filling the TX FIFO and the CPU reads from when retrieving bytes from RX FIFO. - - The size of the register changes as follows: - - Write: - 11 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=1 - 9 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=0 Read: - 12 bits when IC_FIRST_DATA_BYTE_STATUS = 1 - 8 bits when IC_FIRST_DATA_BYTE_STATUS = 0 Note: In order for the DW_apb_i2c to continue acknowledging reads, a read command should be written for every byte that is to be received; otherwise the DW_apb_i2c will stop acknowledging. - 0x00000000 - - - FIRST_DATA_BYTE - Indicates the first data byte received after the address phase for receive transfer in Master receiver or Slave receiver mode. - - Reset value : 0x0 - - NOTE: In case of APB_DATA_WIDTH=8, - - 1. The user has to perform two APB Reads to IC_DATA_CMD in order to get status on 11 bit. - - 2. In order to read the 11 bit, the user has to perform the first data byte read [7:0] (offset 0x10) and then perform the second read [15:8] (offset 0x11) in order to know the status of 11 bit (whether the data received in previous read is a first data byte or not). - - 3. The 11th bit is an optional read field, user can ignore 2nd byte read [15:8] (offset 0x11) if not interested in FIRST_DATA_BYTE status. - [11:11] - read-only - - - INACTIVE - 0 - Sequential data byte received - - - ACTIVE - 1 - Non sequential data byte received - - - - - RESTART - This bit controls whether a RESTART is issued before the byte is sent or received. - - 1 - If IC_RESTART_EN is 1, a RESTART is issued before the data is sent/received (according to the value of CMD), regardless of whether or not the transfer direction is changing from the previous command; if IC_RESTART_EN is 0, a STOP followed by a START is issued instead. - - 0 - If IC_RESTART_EN is 1, a RESTART is issued only if the transfer direction is changing from the previous command; if IC_RESTART_EN is 0, a STOP followed by a START is issued instead. - - Reset value: 0x0 - [10:10] - write-only - - - DISABLE - 0 - Don't Issue RESTART before this command - - - ENABLE - 1 - Issue RESTART before this command - - - - - STOP - This bit controls whether a STOP is issued after the byte is sent or received. - - - 1 - STOP is issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master immediately tries to start a new transfer by issuing a START and arbitrating for the bus. - 0 - STOP is not issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master continues the current transfer by sending/receiving data bytes according to the value of the CMD bit. If the Tx FIFO is empty, the master holds the SCL line low and stalls the bus until a new command is available in the Tx FIFO. Reset value: 0x0 - [9:9] - write-only - - - DISABLE - 0 - Don't Issue STOP after this command - - - ENABLE - 1 - Issue STOP after this command - - - - - CMD - This bit controls whether a read or a write is performed. This bit does not control the direction when the DW_apb_i2con acts as a slave. It controls only the direction when it acts as a master. - - When a command is entered in the TX FIFO, this bit distinguishes the write and read commands. In slave-receiver mode, this bit is a 'don't care' because writes to this register are not required. In slave-transmitter mode, a '0' indicates that the data in IC_DATA_CMD is to be transmitted. - - When programming this bit, you should remember the following: attempting to perform a read operation after a General Call command has been sent results in a TX_ABRT interrupt (bit 6 of the IC_RAW_INTR_STAT register), unless bit 11 (SPECIAL) in the IC_TAR register has been cleared. If a '1' is written to this bit after receiving a RD_REQ interrupt, then a TX_ABRT interrupt occurs. - - Reset value: 0x0 - [8:8] - write-only - - - WRITE - 0 - Master Write Command - - - READ - 1 - Master Read Command - - - - - DAT - This register contains the data to be transmitted or received on the I2C bus. If you are writing to this register and want to perform a read, bits 7:0 (DAT) are ignored by the DW_apb_i2c. However, when you read this register, these bits return the value of data received on the DW_apb_i2c interface. - - Reset value: 0x0 - [7:0] - read-write - - - - - IC_SS_SCL_HCNT - 0x00000014 - Standard Speed I2C Clock SCL High Count Register - 0x00000028 - - - IC_SS_SCL_HCNT - This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for standard speed. For more information, refer to 'IC_CLK Frequency Configuration'. - - This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect. - - The minimum valid value is 6; hardware prevents values less than this being written, and if attempted results in 6 being set. For designs with APB_DATA_WIDTH = 8, the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed. - - NOTE: This register must not be programmed to a value higher than 65525, because DW_apb_i2c uses a 16-bit counter to flag an I2C bus idle condition when this counter reaches a value of IC_SS_SCL_HCNT + 10. - [15:0] - read-write - - - - - IC_SS_SCL_LCNT - 0x00000018 - Standard Speed I2C Clock SCL Low Count Register - 0x0000002f - - - IC_SS_SCL_LCNT - This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for standard speed. For more information, refer to 'IC_CLK Frequency Configuration' - - This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect. - - The minimum valid value is 8; hardware prevents values less than this being written, and if attempted, results in 8 being set. For designs with APB_DATA_WIDTH = 8, the order of programming is important to ensure the correct operation of DW_apb_i2c. The lower byte must be programmed first, and then the upper byte is programmed. - [15:0] - read-write - - - - - IC_FS_SCL_HCNT - 0x0000001c - Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register - 0x00000006 - - - IC_FS_SCL_HCNT - This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for fast mode or fast mode plus. It is used in high-speed mode to send the Master Code and START BYTE or General CALL. For more information, refer to 'IC_CLK Frequency Configuration'. - - This register goes away and becomes read-only returning 0s if IC_MAX_SPEED_MODE = standard. This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect. - - The minimum valid value is 6; hardware prevents values less than this being written, and if attempted results in 6 being set. For designs with APB_DATA_WIDTH == 8 the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed. - [15:0] - read-write - - - - - IC_FS_SCL_LCNT - 0x00000020 - Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register - 0x0000000d - - - IC_FS_SCL_LCNT - This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for fast speed. It is used in high-speed mode to send the Master Code and START BYTE or General CALL. For more information, refer to 'IC_CLK Frequency Configuration'. - - This register goes away and becomes read-only returning 0s if IC_MAX_SPEED_MODE = standard. - - This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect. - - The minimum valid value is 8; hardware prevents values less than this being written, and if attempted results in 8 being set. For designs with APB_DATA_WIDTH = 8 the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed. If the value is less than 8 then the count value gets changed to 8. - [15:0] - read-write - - - - - IC_INTR_STAT - 0x0000002c - I2C Interrupt Status Register - - Each bit in this register has a corresponding mask bit in the IC_INTR_MASK register. These bits are cleared by reading the matching interrupt clear register. The unmasked raw versions of these bits are available in the IC_RAW_INTR_STAT register. - 0x00000000 - - - R_RESTART_DET - See IC_RAW_INTR_STAT for a detailed description of R_RESTART_DET bit. - - Reset value: 0x0 - [12:12] - read-only - - - INACTIVE - 0 - R_RESTART_DET interrupt is inactive - - - ACTIVE - 1 - R_RESTART_DET interrupt is active - - - - - R_GEN_CALL - See IC_RAW_INTR_STAT for a detailed description of R_GEN_CALL bit. - - Reset value: 0x0 - [11:11] - read-only - - - INACTIVE - 0 - R_GEN_CALL interrupt is inactive - - - ACTIVE - 1 - R_GEN_CALL interrupt is active - - - - - R_START_DET - See IC_RAW_INTR_STAT for a detailed description of R_START_DET bit. - - Reset value: 0x0 - [10:10] - read-only - - - INACTIVE - 0 - R_START_DET interrupt is inactive - - - ACTIVE - 1 - R_START_DET interrupt is active - - - - - R_STOP_DET - See IC_RAW_INTR_STAT for a detailed description of R_STOP_DET bit. - - Reset value: 0x0 - [9:9] - read-only - - - INACTIVE - 0 - R_STOP_DET interrupt is inactive - - - ACTIVE - 1 - R_STOP_DET interrupt is active - - - - - R_ACTIVITY - See IC_RAW_INTR_STAT for a detailed description of R_ACTIVITY bit. - - Reset value: 0x0 - [8:8] - read-only - - - INACTIVE - 0 - R_ACTIVITY interrupt is inactive - - - ACTIVE - 1 - R_ACTIVITY interrupt is active - - - - - R_RX_DONE - See IC_RAW_INTR_STAT for a detailed description of R_RX_DONE bit. - - Reset value: 0x0 - [7:7] - read-only - - - INACTIVE - 0 - R_RX_DONE interrupt is inactive - - - ACTIVE - 1 - R_RX_DONE interrupt is active - - - - - R_TX_ABRT - See IC_RAW_INTR_STAT for a detailed description of R_TX_ABRT bit. - - Reset value: 0x0 - [6:6] - read-only - - - INACTIVE - 0 - R_TX_ABRT interrupt is inactive - - - ACTIVE - 1 - R_TX_ABRT interrupt is active - - - - - R_RD_REQ - See IC_RAW_INTR_STAT for a detailed description of R_RD_REQ bit. - - Reset value: 0x0 - [5:5] - read-only - - - INACTIVE - 0 - R_RD_REQ interrupt is inactive - - - ACTIVE - 1 - R_RD_REQ interrupt is active - - - - - R_TX_EMPTY - See IC_RAW_INTR_STAT for a detailed description of R_TX_EMPTY bit. - - Reset value: 0x0 - [4:4] - read-only - - - INACTIVE - 0 - R_TX_EMPTY interrupt is inactive - - - ACTIVE - 1 - R_TX_EMPTY interrupt is active - - - - - R_TX_OVER - See IC_RAW_INTR_STAT for a detailed description of R_TX_OVER bit. - - Reset value: 0x0 - [3:3] - read-only - - - INACTIVE - 0 - R_TX_OVER interrupt is inactive - - - ACTIVE - 1 - R_TX_OVER interrupt is active - - - - - R_RX_FULL - See IC_RAW_INTR_STAT for a detailed description of R_RX_FULL bit. - - Reset value: 0x0 - [2:2] - read-only - - - INACTIVE - 0 - R_RX_FULL interrupt is inactive - - - ACTIVE - 1 - R_RX_FULL interrupt is active - - - - - R_RX_OVER - See IC_RAW_INTR_STAT for a detailed description of R_RX_OVER bit. - - Reset value: 0x0 - [1:1] - read-only - - - INACTIVE - 0 - R_RX_OVER interrupt is inactive - - - ACTIVE - 1 - R_RX_OVER interrupt is active - - - - - R_RX_UNDER - See IC_RAW_INTR_STAT for a detailed description of R_RX_UNDER bit. - - Reset value: 0x0 - [0:0] - read-only - - - INACTIVE - 0 - RX_UNDER interrupt is inactive - - - ACTIVE - 1 - RX_UNDER interrupt is active - - - - - - - IC_INTR_MASK - 0x00000030 - I2C Interrupt Mask Register. - - These bits mask their corresponding interrupt status bits. This register is active low; a value of 0 masks the interrupt, whereas a value of 1 unmasks the interrupt. - 0x000008ff - - - M_RESTART_DET - This bit masks the R_RESTART_DET interrupt in IC_INTR_STAT register. - - Reset value: 0x0 - [12:12] - read-write - - - ENABLED - 0 - RESTART_DET interrupt is masked - - - DISABLED - 1 - RESTART_DET interrupt is unmasked - - - - - M_GEN_CALL - This bit masks the R_GEN_CALL interrupt in IC_INTR_STAT register. - - Reset value: 0x1 - [11:11] - read-write - - - ENABLED - 0 - GEN_CALL interrupt is masked - - - DISABLED - 1 - GEN_CALL interrupt is unmasked - - - - - M_START_DET - This bit masks the R_START_DET interrupt in IC_INTR_STAT register. - - Reset value: 0x0 - [10:10] - read-write - - - ENABLED - 0 - START_DET interrupt is masked - - - DISABLED - 1 - START_DET interrupt is unmasked - - - - - M_STOP_DET - This bit masks the R_STOP_DET interrupt in IC_INTR_STAT register. - - Reset value: 0x0 - [9:9] - read-write - - - ENABLED - 0 - STOP_DET interrupt is masked - - - DISABLED - 1 - STOP_DET interrupt is unmasked - - - - - M_ACTIVITY - This bit masks the R_ACTIVITY interrupt in IC_INTR_STAT register. - - Reset value: 0x0 - [8:8] - read-write - - - ENABLED - 0 - ACTIVITY interrupt is masked - - - DISABLED - 1 - ACTIVITY interrupt is unmasked - - - - - M_RX_DONE - This bit masks the R_RX_DONE interrupt in IC_INTR_STAT register. - - Reset value: 0x1 - [7:7] - read-write - - - ENABLED - 0 - RX_DONE interrupt is masked - - - DISABLED - 1 - RX_DONE interrupt is unmasked - - - - - M_TX_ABRT - This bit masks the R_TX_ABRT interrupt in IC_INTR_STAT register. - - Reset value: 0x1 - [6:6] - read-write - - - ENABLED - 0 - TX_ABORT interrupt is masked - - - DISABLED - 1 - TX_ABORT interrupt is unmasked - - - - - M_RD_REQ - This bit masks the R_RD_REQ interrupt in IC_INTR_STAT register. - - Reset value: 0x1 - [5:5] - read-write - - - ENABLED - 0 - RD_REQ interrupt is masked - - - DISABLED - 1 - RD_REQ interrupt is unmasked - - - - - M_TX_EMPTY - This bit masks the R_TX_EMPTY interrupt in IC_INTR_STAT register. - - Reset value: 0x1 - [4:4] - read-write - - - ENABLED - 0 - TX_EMPTY interrupt is masked - - - DISABLED - 1 - TX_EMPTY interrupt is unmasked - - - - - M_TX_OVER - This bit masks the R_TX_OVER interrupt in IC_INTR_STAT register. - - Reset value: 0x1 - [3:3] - read-write - - - ENABLED - 0 - TX_OVER interrupt is masked - - - DISABLED - 1 - TX_OVER interrupt is unmasked - - - - - M_RX_FULL - This bit masks the R_RX_FULL interrupt in IC_INTR_STAT register. - - Reset value: 0x1 - [2:2] - read-write - - - ENABLED - 0 - RX_FULL interrupt is masked - - - DISABLED - 1 - RX_FULL interrupt is unmasked - - - - - M_RX_OVER - This bit masks the R_RX_OVER interrupt in IC_INTR_STAT register. - - Reset value: 0x1 - [1:1] - read-write - - - ENABLED - 0 - RX_OVER interrupt is masked - - - DISABLED - 1 - RX_OVER interrupt is unmasked - - - - - M_RX_UNDER - This bit masks the R_RX_UNDER interrupt in IC_INTR_STAT register. - - Reset value: 0x1 - [0:0] - read-write - - - ENABLED - 0 - RX_UNDER interrupt is masked - - - DISABLED - 1 - RX_UNDER interrupt is unmasked - - - - - - - IC_RAW_INTR_STAT - 0x00000034 - I2C Raw Interrupt Status Register - - Unlike the IC_INTR_STAT register, these bits are not masked so they always show the true status of the DW_apb_i2c. - 0x00000000 - - - RESTART_DET - Indicates whether a RESTART condition has occurred on the I2C interface when DW_apb_i2c is operating in Slave mode and the slave is being addressed. Enabled only when IC_SLV_RESTART_DET_EN=1. - - Note: However, in high-speed mode or during a START BYTE transfer, the RESTART comes before the address field as per the I2C protocol. In this case, the slave is not the addressed slave when the RESTART is issued, therefore DW_apb_i2c does not generate the RESTART_DET interrupt. - - Reset value: 0x0 - [12:12] - read-only - - - INACTIVE - 0 - RESTART_DET interrupt is inactive - - - ACTIVE - 1 - RESTART_DET interrupt is active - - - - - GEN_CALL - Set only when a General Call address is received and it is acknowledged. It stays set until it is cleared either by disabling DW_apb_i2c or when the CPU reads bit 0 of the IC_CLR_GEN_CALL register. DW_apb_i2c stores the received data in the Rx buffer. - - Reset value: 0x0 - [11:11] - read-only - - - INACTIVE - 0 - GEN_CALL interrupt is inactive - - - ACTIVE - 1 - GEN_CALL interrupt is active - - - - - START_DET - Indicates whether a START or RESTART condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode. - - Reset value: 0x0 - [10:10] - read-only - - - INACTIVE - 0 - START_DET interrupt is inactive - - - ACTIVE - 1 - START_DET interrupt is active - - - - - STOP_DET - Indicates whether a STOP condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode. - - In Slave Mode: - If IC_CON[7]=1'b1 (STOP_DET_IFADDRESSED), the STOP_DET interrupt will be issued only if slave is addressed. Note: During a general call address, this slave does not issue a STOP_DET interrupt if STOP_DET_IF_ADDRESSED=1'b1, even if the slave responds to the general call address by generating ACK. The STOP_DET interrupt is generated only when the transmitted address matches the slave address (SAR). - If IC_CON[7]=1'b0 (STOP_DET_IFADDRESSED), the STOP_DET interrupt is issued irrespective of whether it is being addressed. In Master Mode: - If IC_CON[10]=1'b1 (STOP_DET_IF_MASTER_ACTIVE),the STOP_DET interrupt will be issued only if Master is active. - If IC_CON[10]=1'b0 (STOP_DET_IFADDRESSED),the STOP_DET interrupt will be issued irrespective of whether master is active or not. Reset value: 0x0 - [9:9] - read-only - - - INACTIVE - 0 - STOP_DET interrupt is inactive - - - ACTIVE - 1 - STOP_DET interrupt is active - - - - - ACTIVITY - This bit captures DW_apb_i2c activity and stays set until it is cleared. There are four ways to clear it: - Disabling the DW_apb_i2c - Reading the IC_CLR_ACTIVITY register - Reading the IC_CLR_INTR register - System reset Once this bit is set, it stays set unless one of the four methods is used to clear it. Even if the DW_apb_i2c module is idle, this bit remains set until cleared, indicating that there was activity on the bus. - - Reset value: 0x0 - [8:8] - read-only - - - INACTIVE - 0 - RAW_INTR_ACTIVITY interrupt is inactive - - - ACTIVE - 1 - RAW_INTR_ACTIVITY interrupt is active - - - - - RX_DONE - When the DW_apb_i2c is acting as a slave-transmitter, this bit is set to 1 if the master does not acknowledge a transmitted byte. This occurs on the last byte of the transmission, indicating that the transmission is done. - - Reset value: 0x0 - [7:7] - read-only - - - INACTIVE - 0 - RX_DONE interrupt is inactive - - - ACTIVE - 1 - RX_DONE interrupt is active - - - - - TX_ABRT - This bit indicates if DW_apb_i2c, as an I2C transmitter, is unable to complete the intended actions on the contents of the transmit FIFO. This situation can occur both as an I2C master or an I2C slave, and is referred to as a 'transmit abort'. When this bit is set to 1, the IC_TX_ABRT_SOURCE register indicates the reason why the transmit abort takes places. - - Note: The DW_apb_i2c flushes/resets/empties the TX_FIFO and RX_FIFO whenever there is a transmit abort caused by any of the events tracked by the IC_TX_ABRT_SOURCE register. The FIFOs remains in this flushed state until the register IC_CLR_TX_ABRT is read. Once this read is performed, the Tx FIFO is then ready to accept more data bytes from the APB interface. - - Reset value: 0x0 - [6:6] - read-only - - - INACTIVE - 0 - TX_ABRT interrupt is inactive - - - ACTIVE - 1 - TX_ABRT interrupt is active - - - - - RD_REQ - This bit is set to 1 when DW_apb_i2c is acting as a slave and another I2C master is attempting to read data from DW_apb_i2c. The DW_apb_i2c holds the I2C bus in a wait state (SCL=0) until this interrupt is serviced, which means that the slave has been addressed by a remote master that is asking for data to be transferred. The processor must respond to this interrupt and then write the requested data to the IC_DATA_CMD register. This bit is set to 0 just after the processor reads the IC_CLR_RD_REQ register. - - Reset value: 0x0 - [5:5] - read-only - - - INACTIVE - 0 - RD_REQ interrupt is inactive - - - ACTIVE - 1 - RD_REQ interrupt is active - - - - - TX_EMPTY - The behavior of the TX_EMPTY interrupt status differs based on the TX_EMPTY_CTRL selection in the IC_CON register. - When TX_EMPTY_CTRL = 0: This bit is set to 1 when the transmit buffer is at or below the threshold value set in the IC_TX_TL register. - When TX_EMPTY_CTRL = 1: This bit is set to 1 when the transmit buffer is at or below the threshold value set in the IC_TX_TL register and the transmission of the address/data from the internal shift register for the most recently popped command is completed. It is automatically cleared by hardware when the buffer level goes above the threshold. When IC_ENABLE[0] is set to 0, the TX FIFO is flushed and held in reset. There the TX FIFO looks like it has no data within it, so this bit is set to 1, provided there is activity in the master or slave state machines. When there is no longer any activity, then with ic_en=0, this bit is set to 0. - - Reset value: 0x0. - [4:4] - read-only - - - INACTIVE - 0 - TX_EMPTY interrupt is inactive - - - ACTIVE - 1 - TX_EMPTY interrupt is active - - - - - TX_OVER - Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH and the processor attempts to issue another I2C command by writing to the IC_DATA_CMD register. When the module is disabled, this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared. - - Reset value: 0x0 - [3:3] - read-only - - - INACTIVE - 0 - TX_OVER interrupt is inactive - - - ACTIVE - 1 - TX_OVER interrupt is active - - - - - RX_FULL - Set when the receive buffer reaches or goes above the RX_TL threshold in the IC_RX_TL register. It is automatically cleared by hardware when buffer level goes below the threshold. If the module is disabled (IC_ENABLE[0]=0), the RX FIFO is flushed and held in reset; therefore the RX FIFO is not full. So this bit is cleared once the IC_ENABLE bit 0 is programmed with a 0, regardless of the activity that continues. - - Reset value: 0x0 - [2:2] - read-only - - - INACTIVE - 0 - RX_FULL interrupt is inactive - - - ACTIVE - 1 - RX_FULL interrupt is active - - - - - RX_OVER - Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and an additional byte is received from an external I2C device. The DW_apb_i2c acknowledges this, but any data bytes received after the FIFO is full are lost. If the module is disabled (IC_ENABLE[0]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared. - - Note: If bit 9 of the IC_CON register (RX_FIFO_FULL_HLD_CTRL) is programmed to HIGH, then the RX_OVER interrupt never occurs, because the Rx FIFO never overflows. - - Reset value: 0x0 - [1:1] - read-only - - - INACTIVE - 0 - RX_OVER interrupt is inactive - - - ACTIVE - 1 - RX_OVER interrupt is active - - - - - RX_UNDER - Set if the processor attempts to read the receive buffer when it is empty by reading from the IC_DATA_CMD register. If the module is disabled (IC_ENABLE[0]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared. - - Reset value: 0x0 - [0:0] - read-only - - - INACTIVE - 0 - RX_UNDER interrupt is inactive - - - ACTIVE - 1 - RX_UNDER interrupt is active - - - - - - - IC_RX_TL - 0x00000038 - I2C Receive FIFO Threshold Register - 0x00000000 - - - RX_TL - Receive FIFO Threshold Level. - - Controls the level of entries (or above) that triggers the RX_FULL interrupt (bit 2 in IC_RAW_INTR_STAT register). The valid range is 0-255, with the additional restriction that hardware does not allow this value to be set to a value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 1 entry, and a value of 255 sets the threshold for 256 entries. - [7:0] - read-write - - - - - IC_TX_TL - 0x0000003c - I2C Transmit FIFO Threshold Register - 0x00000000 - - - TX_TL - Transmit FIFO Threshold Level. - - Controls the level of entries (or below) that trigger the TX_EMPTY interrupt (bit 4 in IC_RAW_INTR_STAT register). The valid range is 0-255, with the additional restriction that it may not be set to value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 0 entries, and a value of 255 sets the threshold for 255 entries. - [7:0] - read-write - - - - - IC_CLR_INTR - 0x00000040 - Clear Combined and Individual Interrupt Register - 0x00000000 - - - CLR_INTR - Read this register to clear the combined interrupt, all individual interrupts, and the IC_TX_ABRT_SOURCE register. This bit does not clear hardware clearable interrupts but software clearable interrupts. Refer to Bit 9 of the IC_TX_ABRT_SOURCE register for an exception to clearing IC_TX_ABRT_SOURCE. - - Reset value: 0x0 - [0:0] - read-only - - - - - IC_CLR_RX_UNDER - 0x00000044 - Clear RX_UNDER Interrupt Register - 0x00000000 - - - CLR_RX_UNDER - Read this register to clear the RX_UNDER interrupt (bit 0) of the IC_RAW_INTR_STAT register. - - Reset value: 0x0 - [0:0] - read-only - - - - - IC_CLR_RX_OVER - 0x00000048 - Clear RX_OVER Interrupt Register - 0x00000000 - - - CLR_RX_OVER - Read this register to clear the RX_OVER interrupt (bit 1) of the IC_RAW_INTR_STAT register. - - Reset value: 0x0 - [0:0] - read-only - - - - - IC_CLR_TX_OVER - 0x0000004c - Clear TX_OVER Interrupt Register - 0x00000000 - - - CLR_TX_OVER - Read this register to clear the TX_OVER interrupt (bit 3) of the IC_RAW_INTR_STAT register. - - Reset value: 0x0 - [0:0] - read-only - - - - - IC_CLR_RD_REQ - 0x00000050 - Clear RD_REQ Interrupt Register - 0x00000000 - - - CLR_RD_REQ - Read this register to clear the RD_REQ interrupt (bit 5) of the IC_RAW_INTR_STAT register. - - Reset value: 0x0 - [0:0] - read-only - - - - - IC_CLR_TX_ABRT - 0x00000054 - Clear TX_ABRT Interrupt Register - 0x00000000 - - - CLR_TX_ABRT - Read this register to clear the TX_ABRT interrupt (bit 6) of the IC_RAW_INTR_STAT register, and the IC_TX_ABRT_SOURCE register. This also releases the TX FIFO from the flushed/reset state, allowing more writes to the TX FIFO. Refer to Bit 9 of the IC_TX_ABRT_SOURCE register for an exception to clearing IC_TX_ABRT_SOURCE. - - Reset value: 0x0 - [0:0] - read-only - - - - - IC_CLR_RX_DONE - 0x00000058 - Clear RX_DONE Interrupt Register - 0x00000000 - - - CLR_RX_DONE - Read this register to clear the RX_DONE interrupt (bit 7) of the IC_RAW_INTR_STAT register. - - Reset value: 0x0 - [0:0] - read-only - - - - - IC_CLR_ACTIVITY - 0x0000005c - Clear ACTIVITY Interrupt Register - 0x00000000 - - - CLR_ACTIVITY - Reading this register clears the ACTIVITY interrupt if the I2C is not active anymore. If the I2C module is still active on the bus, the ACTIVITY interrupt bit continues to be set. It is automatically cleared by hardware if the module is disabled and if there is no further activity on the bus. The value read from this register to get status of the ACTIVITY interrupt (bit 8) of the IC_RAW_INTR_STAT register. - - Reset value: 0x0 - [0:0] - read-only - - - - - IC_CLR_STOP_DET - 0x00000060 - Clear STOP_DET Interrupt Register - 0x00000000 - - - CLR_STOP_DET - Read this register to clear the STOP_DET interrupt (bit 9) of the IC_RAW_INTR_STAT register. - - Reset value: 0x0 - [0:0] - read-only - - - - - IC_CLR_START_DET - 0x00000064 - Clear START_DET Interrupt Register - 0x00000000 - - - CLR_START_DET - Read this register to clear the START_DET interrupt (bit 10) of the IC_RAW_INTR_STAT register. - - Reset value: 0x0 - [0:0] - read-only - - - - - IC_CLR_GEN_CALL - 0x00000068 - Clear GEN_CALL Interrupt Register - 0x00000000 - - - CLR_GEN_CALL - Read this register to clear the GEN_CALL interrupt (bit 11) of IC_RAW_INTR_STAT register. - - Reset value: 0x0 - [0:0] - read-only - - - - - IC_ENABLE - 0x0000006c - I2C Enable Register - 0x00000000 - - - TX_CMD_BLOCK - In Master mode: - 1'b1: Blocks the transmission of data on I2C bus even if Tx FIFO has data to transmit. - 1'b0: The transmission of data starts on I2C bus automatically, as soon as the first data is available in the Tx FIFO. Note: To block the execution of Master commands, set the TX_CMD_BLOCK bit only when Tx FIFO is empty (IC_STATUS[2]==1) and Master is in Idle state (IC_STATUS[5] == 0). Any further commands put in the Tx FIFO are not executed until TX_CMD_BLOCK bit is unset. Reset value: IC_TX_CMD_BLOCK_DEFAULT - [2:2] - read-write - - - NOT_BLOCKED - 0 - Tx Command execution not blocked - - - BLOCKED - 1 - Tx Command execution blocked - - - - - ABORT - When set, the controller initiates the transfer abort. - 0: ABORT not initiated or ABORT done - 1: ABORT operation in progress The software can abort the I2C transfer in master mode by setting this bit. The software can set this bit only when ENABLE is already set; otherwise, the controller ignores any write to ABORT bit. The software cannot clear the ABORT bit once set. In response to an ABORT, the controller issues a STOP and flushes the Tx FIFO after completing the current transfer, then sets the TX_ABORT interrupt after the abort operation. The ABORT bit is cleared automatically after the abort operation. - - For a detailed description on how to abort I2C transfers, refer to 'Aborting I2C Transfers'. - - Reset value: 0x0 - [1:1] - read-write - - - DISABLE - 0 - ABORT operation not in progress - - - ENABLED - 1 - ABORT operation in progress - - - - - ENABLE - Controls whether the DW_apb_i2c is enabled. - 0: Disables DW_apb_i2c (TX and RX FIFOs are held in an erased state) - 1: Enables DW_apb_i2c Software can disable DW_apb_i2c while it is active. However, it is important that care be taken to ensure that DW_apb_i2c is disabled properly. A recommended procedure is described in 'Disabling DW_apb_i2c'. - - When DW_apb_i2c is disabled, the following occurs: - The TX FIFO and RX FIFO get flushed. - Status bits in the IC_INTR_STAT register are still active until DW_apb_i2c goes into IDLE state. If the module is transmitting, it stops as well as deletes the contents of the transmit buffer after the current transfer is complete. If the module is receiving, the DW_apb_i2c stops the current transfer at the end of the current byte and does not acknowledge the transfer. - - In systems with asynchronous pclk and ic_clk when IC_CLK_TYPE parameter set to asynchronous (1), there is a two ic_clk delay when enabling or disabling the DW_apb_i2c. For a detailed description on how to disable DW_apb_i2c, refer to 'Disabling DW_apb_i2c' - - Reset value: 0x0 - [0:0] - read-write - - - DISABLED - 0 - I2C is disabled - - - ENABLED - 1 - I2C is enabled - - - - - - - IC_STATUS - 0x00000070 - I2C Status Register - - This is a read-only register used to indicate the current transfer status and FIFO status. The status register may be read at any time. None of the bits in this register request an interrupt. - - When the I2C is disabled by writing 0 in bit 0 of the IC_ENABLE register: - Bits 1 and 2 are set to 1 - Bits 3 and 10 are set to 0 When the master or slave state machines goes to idle and ic_en=0: - Bits 5 and 6 are set to 0 - 0x00000006 - - - SLV_ACTIVITY - Slave FSM Activity Status. When the Slave Finite State Machine (FSM) is not in the IDLE state, this bit is set. - 0: Slave FSM is in IDLE state so the Slave part of DW_apb_i2c is not Active - 1: Slave FSM is not in IDLE state so the Slave part of DW_apb_i2c is Active Reset value: 0x0 - [6:6] - read-only - - - IDLE - 0 - Slave is idle - - - ACTIVE - 1 - Slave not idle - - - - - MST_ACTIVITY - Master FSM Activity Status. When the Master Finite State Machine (FSM) is not in the IDLE state, this bit is set. - 0: Master FSM is in IDLE state so the Master part of DW_apb_i2c is not Active - 1: Master FSM is not in IDLE state so the Master part of DW_apb_i2c is Active Note: IC_STATUS[0]-that is, ACTIVITY bit-is the OR of SLV_ACTIVITY and MST_ACTIVITY bits. - - Reset value: 0x0 - [5:5] - read-only - - - IDLE - 0 - Master is idle - - - ACTIVE - 1 - Master not idle - - - - - RFF - Receive FIFO Completely Full. When the receive FIFO is completely full, this bit is set. When the receive FIFO contains one or more empty location, this bit is cleared. - 0: Receive FIFO is not full - 1: Receive FIFO is full Reset value: 0x0 - [4:4] - read-only - - - NOT_FULL - 0 - Rx FIFO not full - - - FULL - 1 - Rx FIFO is full - - - - - RFNE - Receive FIFO Not Empty. This bit is set when the receive FIFO contains one or more entries; it is cleared when the receive FIFO is empty. - 0: Receive FIFO is empty - 1: Receive FIFO is not empty Reset value: 0x0 - [3:3] - read-only - - - EMPTY - 0 - Rx FIFO is empty - - - NOT_EMPTY - 1 - Rx FIFO not empty - - - - - TFE - Transmit FIFO Completely Empty. When the transmit FIFO is completely empty, this bit is set. When it contains one or more valid entries, this bit is cleared. This bit field does not request an interrupt. - 0: Transmit FIFO is not empty - 1: Transmit FIFO is empty Reset value: 0x1 - [2:2] - read-only - - - NON_EMPTY - 0 - Tx FIFO not empty - - - EMPTY - 1 - Tx FIFO is empty - - - - - TFNF - Transmit FIFO Not Full. Set when the transmit FIFO contains one or more empty locations, and is cleared when the FIFO is full. - 0: Transmit FIFO is full - 1: Transmit FIFO is not full Reset value: 0x1 - [1:1] - read-only - - - FULL - 0 - Tx FIFO is full - - - NOT_FULL - 1 - Tx FIFO not full - - - - - ACTIVITY - I2C Activity Status. Reset value: 0x0 - [0:0] - read-only - - - INACTIVE - 0 - I2C is idle - - - ACTIVE - 1 - I2C is active - - - - - - - IC_TXFLR - 0x00000074 - I2C Transmit FIFO Level Register This register contains the number of valid data entries in the transmit FIFO buffer. It is cleared whenever: - The I2C is disabled - There is a transmit abort - that is, TX_ABRT bit is set in the IC_RAW_INTR_STAT register - The slave bulk transmit mode is aborted The register increments whenever data is placed into the transmit FIFO and decrements when data is taken from the transmit FIFO. - 0x00000000 - - - TXFLR - Transmit FIFO Level. Contains the number of valid data entries in the transmit FIFO. - - Reset value: 0x0 - [4:0] - read-only - - - - - IC_RXFLR - 0x00000078 - I2C Receive FIFO Level Register This register contains the number of valid data entries in the receive FIFO buffer. It is cleared whenever: - The I2C is disabled - Whenever there is a transmit abort caused by any of the events tracked in IC_TX_ABRT_SOURCE The register increments whenever data is placed into the receive FIFO and decrements when data is taken from the receive FIFO. - 0x00000000 - - - RXFLR - Receive FIFO Level. Contains the number of valid data entries in the receive FIFO. - - Reset value: 0x0 - [4:0] - read-only - - - - - IC_SDA_HOLD - 0x0000007c - I2C SDA Hold Time Length Register - - The bits [15:0] of this register are used to control the hold time of SDA during transmit in both slave and master mode (after SCL goes from HIGH to LOW). - - The bits [23:16] of this register are used to extend the SDA transition (if any) whenever SCL is HIGH in the receiver in either master or slave mode. - - Writes to this register succeed only when IC_ENABLE[0]=0. - - The values in this register are in units of ic_clk period. The value programmed in IC_SDA_TX_HOLD must be greater than the minimum hold time in each mode (one cycle in master mode, seven cycles in slave mode) for the value to be implemented. - - The programmed SDA hold time during transmit (IC_SDA_TX_HOLD) cannot exceed at any time the duration of the low part of scl. Therefore the programmed value cannot be larger than N_SCL_LOW-2, where N_SCL_LOW is the duration of the low part of the scl period measured in ic_clk cycles. - 0x00000001 - - - IC_SDA_RX_HOLD - Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c acts as a receiver. - - Reset value: IC_DEFAULT_SDA_HOLD[23:16]. - [23:16] - read-write - - - IC_SDA_TX_HOLD - Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c acts as a transmitter. - - Reset value: IC_DEFAULT_SDA_HOLD[15:0]. - [15:0] - read-write - - - - - IC_TX_ABRT_SOURCE - 0x00000080 - I2C Transmit Abort Source Register - - This register has 32 bits that indicate the source of the TX_ABRT bit. Except for Bit 9, this register is cleared whenever the IC_CLR_TX_ABRT register or the IC_CLR_INTR register is read. To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed first; RESTART must be enabled (IC_CON[5]=1), the SPECIAL bit must be cleared (IC_TAR[11]), or the GC_OR_START bit must be cleared (IC_TAR[10]). - - Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in the same manner as other bits in this register. If the source of the ABRT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, Bit 9 clears for one cycle and is then re-asserted. - 0x00000000 - - - TX_FLUSH_CNT - This field indicates the number of Tx FIFO Data Commands which are flushed due to TX_ABRT interrupt. It is cleared whenever I2C is disabled. - - Reset value: 0x0 - - Role of DW_apb_i2c: Master-Transmitter or Slave-Transmitter - [31:23] - read-only - - - ABRT_USER_ABRT - This is a master-mode-only bit. Master has detected the transfer abort (IC_ENABLE[1]) - - Reset value: 0x0 - - Role of DW_apb_i2c: Master-Transmitter - [16:16] - read-only - - - ABRT_USER_ABRT_VOID - 0 - Transfer abort detected by master- scenario not present - - - ABRT_USER_ABRT_GENERATED - 1 - Transfer abort detected by master - - - - - ABRT_SLVRD_INTX - 1: When the processor side responds to a slave mode request for data to be transmitted to a remote master and user writes a 1 in CMD (bit 8) of IC_DATA_CMD register. - - Reset value: 0x0 - - Role of DW_apb_i2c: Slave-Transmitter - [15:15] - read-only - - - ABRT_SLVRD_INTX_VOID - 0 - Slave trying to transmit to remote master in read mode- scenario not present - - - ABRT_SLVRD_INTX_GENERATED - 1 - Slave trying to transmit to remote master in read mode - - - - - ABRT_SLV_ARBLOST - This field indicates that a Slave has lost the bus while transmitting data to a remote master. IC_TX_ABRT_SOURCE[12] is set at the same time. Note: Even though the slave never 'owns' the bus, something could go wrong on the bus. This is a fail safe check. For instance, during a data transmission at the low-to-high transition of SCL, if what is on the data bus is not what is supposed to be transmitted, then DW_apb_i2c no longer own the bus. - - Reset value: 0x0 - - Role of DW_apb_i2c: Slave-Transmitter - [14:14] - read-only - - - ABRT_SLV_ARBLOST_VOID - 0 - Slave lost arbitration to remote master- scenario not present - - - ABRT_SLV_ARBLOST_GENERATED - 1 - Slave lost arbitration to remote master - - - - - ABRT_SLVFLUSH_TXFIFO - This field specifies that the Slave has received a read command and some data exists in the TX FIFO, so the slave issues a TX_ABRT interrupt to flush old data in TX FIFO. - - Reset value: 0x0 - - Role of DW_apb_i2c: Slave-Transmitter - [13:13] - read-only - - - ABRT_SLVFLUSH_TXFIFO_VOID - 0 - Slave flushes existing data in TX-FIFO upon getting read command- scenario not present - - - ABRT_SLVFLUSH_TXFIFO_GENERATED - 1 - Slave flushes existing data in TX-FIFO upon getting read command - - - - - ARB_LOST - This field specifies that the Master has lost arbitration, or if IC_TX_ABRT_SOURCE[14] is also set, then the slave transmitter has lost arbitration. - - Reset value: 0x0 - - Role of DW_apb_i2c: Master-Transmitter or Slave-Transmitter - [12:12] - read-only - - - ABRT_LOST_VOID - 0 - Master or Slave-Transmitter lost arbitration- scenario not present - - - ABRT_LOST_GENERATED - 1 - Master or Slave-Transmitter lost arbitration - - - - - ABRT_MASTER_DIS - This field indicates that the User tries to initiate a Master operation with the Master mode disabled. - - Reset value: 0x0 - - Role of DW_apb_i2c: Master-Transmitter or Master-Receiver - [11:11] - read-only - - - ABRT_MASTER_DIS_VOID - 0 - User initiating master operation when MASTER disabled- scenario not present - - - ABRT_MASTER_DIS_GENERATED - 1 - User initiating master operation when MASTER disabled - - - - - ABRT_10B_RD_NORSTRT - This field indicates that the restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the master sends a read command in 10-bit addressing mode. - - Reset value: 0x0 - - Role of DW_apb_i2c: Master-Receiver - [10:10] - read-only - - - ABRT_10B_RD_VOID - 0 - Master not trying to read in 10Bit addressing mode when RESTART disabled - - - ABRT_10B_RD_GENERATED - 1 - Master trying to read in 10Bit addressing mode when RESTART disabled - - - - - ABRT_SBYTE_NORSTRT - To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed first; restart must be enabled (IC_CON[5]=1), the SPECIAL bit must be cleared (IC_TAR[11]), or the GC_OR_START bit must be cleared (IC_TAR[10]). Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in the same manner as other bits in this register. If the source of the ABRT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, bit 9 clears for one cycle and then gets reasserted. When this field is set to 1, the restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the user is trying to send a START Byte. - - Reset value: 0x0 - - Role of DW_apb_i2c: Master - [9:9] - read-only - - - ABRT_SBYTE_NORSTRT_VOID - 0 - User trying to send START byte when RESTART disabled- scenario not present - - - ABRT_SBYTE_NORSTRT_GENERATED - 1 - User trying to send START byte when RESTART disabled - - - - - ABRT_HS_NORSTRT - This field indicates that the restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the user is trying to use the master to transfer data in High Speed mode. - - Reset value: 0x0 - - Role of DW_apb_i2c: Master-Transmitter or Master-Receiver - [8:8] - read-only - - - ABRT_HS_NORSTRT_VOID - 0 - User trying to switch Master to HS mode when RESTART disabled- scenario not present - - - ABRT_HS_NORSTRT_GENERATED - 1 - User trying to switch Master to HS mode when RESTART disabled - - - - - ABRT_SBYTE_ACKDET - This field indicates that the Master has sent a START Byte and the START Byte was acknowledged (wrong behavior). - - Reset value: 0x0 - - Role of DW_apb_i2c: Master - [7:7] - read-only - - - ABRT_SBYTE_ACKDET_VOID - 0 - ACK detected for START byte- scenario not present - - - ABRT_SBYTE_ACKDET_GENERATED - 1 - ACK detected for START byte - - - - - ABRT_HS_ACKDET - This field indicates that the Master is in High Speed mode and the High Speed Master code was acknowledged (wrong behavior). - - Reset value: 0x0 - - Role of DW_apb_i2c: Master - [6:6] - read-only - - - ABRT_HS_ACK_VOID - 0 - HS Master code ACKed in HS Mode- scenario not present - - - ABRT_HS_ACK_GENERATED - 1 - HS Master code ACKed in HS Mode - - - - - ABRT_GCALL_READ - This field indicates that DW_apb_i2c in the master mode has sent a General Call but the user programmed the byte following the General Call to be a read from the bus (IC_DATA_CMD[9] is set to 1). - - Reset value: 0x0 - - Role of DW_apb_i2c: Master-Transmitter - [5:5] - read-only - - - ABRT_GCALL_READ_VOID - 0 - GCALL is followed by read from bus-scenario not present - - - ABRT_GCALL_READ_GENERATED - 1 - GCALL is followed by read from bus - - - - - ABRT_GCALL_NOACK - This field indicates that DW_apb_i2c in master mode has sent a General Call and no slave on the bus acknowledged the General Call. - - Reset value: 0x0 - - Role of DW_apb_i2c: Master-Transmitter - [4:4] - read-only - - - ABRT_GCALL_NOACK_VOID - 0 - GCALL not ACKed by any slave-scenario not present - - - ABRT_GCALL_NOACK_GENERATED - 1 - GCALL not ACKed by any slave - - - - - ABRT_TXDATA_NOACK - This field indicates the master-mode only bit. When the master receives an acknowledgement for the address, but when it sends data byte(s) following the address, it did not receive an acknowledge from the remote slave(s). - - Reset value: 0x0 - - Role of DW_apb_i2c: Master-Transmitter - [3:3] - read-only - - - ABRT_TXDATA_NOACK_VOID - 0 - Transmitted data non-ACKed by addressed slave-scenario not present - - - ABRT_TXDATA_NOACK_GENERATED - 1 - Transmitted data not ACKed by addressed slave - - - - - ABRT_10ADDR2_NOACK - This field indicates that the Master is in 10-bit address mode and that the second address byte of the 10-bit address was not acknowledged by any slave. - - Reset value: 0x0 - - Role of DW_apb_i2c: Master-Transmitter or Master-Receiver - [2:2] - read-only - - - INACTIVE - 0 - This abort is not generated - - - ACTIVE - 1 - Byte 2 of 10Bit Address not ACKed by any slave - - - - - ABRT_10ADDR1_NOACK - This field indicates that the Master is in 10-bit address mode and the first 10-bit address byte was not acknowledged by any slave. - - Reset value: 0x0 - - Role of DW_apb_i2c: Master-Transmitter or Master-Receiver - [1:1] - read-only - - - INACTIVE - 0 - This abort is not generated - - - ACTIVE - 1 - Byte 1 of 10Bit Address not ACKed by any slave - - - - - ABRT_7B_ADDR_NOACK - This field indicates that the Master is in 7-bit addressing mode and the address sent was not acknowledged by any slave. - - Reset value: 0x0 - - Role of DW_apb_i2c: Master-Transmitter or Master-Receiver - [0:0] - read-only - - - INACTIVE - 0 - This abort is not generated - - - ACTIVE - 1 - This abort is generated because of NOACK for 7-bit address - - - - - - - IC_SLV_DATA_NACK_ONLY - 0x00000084 - Generate Slave Data NACK Register - - The register is used to generate a NACK for the data part of a transfer when DW_apb_i2c is acting as a slave-receiver. This register only exists when the IC_SLV_DATA_NACK_ONLY parameter is set to 1. When this parameter disabled, this register does not exist and writing to the register's address has no effect. - - A write can occur on this register if both of the following conditions are met: - DW_apb_i2c is disabled (IC_ENABLE[0] = 0) - Slave part is inactive (IC_STATUS[6] = 0) Note: The IC_STATUS[6] is a register read-back location for the internal slv_activity signal; the user should poll this before writing the ic_slv_data_nack_only bit. - 0x00000000 - - - NACK - Generate NACK. This NACK generation only occurs when DW_apb_i2c is a slave-receiver. If this register is set to a value of 1, it can only generate a NACK after a data byte is received; hence, the data transfer is aborted and the data received is not pushed to the receive buffer. - - When the register is set to a value of 0, it generates NACK/ACK, depending on normal criteria. - 1: generate NACK after data byte received - 0: generate NACK/ACK normally Reset value: 0x0 - [0:0] - read-write - - - DISABLED - 0 - Slave receiver generates NACK normally - - - ENABLED - 1 - Slave receiver generates NACK upon data reception only - - - - - - - IC_DMA_CR - 0x00000088 - DMA Control Register - - The register is used to enable the DMA Controller interface operation. There is a separate bit for transmit and receive. This can be programmed regardless of the state of IC_ENABLE. - 0x00000000 - - - TDMAE - Transmit DMA Enable. This bit enables/disables the transmit FIFO DMA channel. Reset value: 0x0 - [1:1] - read-write - - - DISABLED - 0 - transmit FIFO DMA channel disabled - - - ENABLED - 1 - Transmit FIFO DMA channel enabled - - - - - RDMAE - Receive DMA Enable. This bit enables/disables the receive FIFO DMA channel. Reset value: 0x0 - [0:0] - read-write - - - DISABLED - 0 - Receive FIFO DMA channel disabled - - - ENABLED - 1 - Receive FIFO DMA channel enabled - - - - - - - IC_DMA_TDLR - 0x0000008c - DMA Transmit Data Level Register - 0x00000000 - - - DMATDL - Transmit Data Level. This bit field controls the level at which a DMA request is made by the transmit logic. It is equal to the watermark level; that is, the dma_tx_req signal is generated when the number of valid data entries in the transmit FIFO is equal to or below this field value, and TDMAE = 1. - - Reset value: 0x0 - [3:0] - read-write - - - - - IC_DMA_RDLR - 0x00000090 - I2C Receive Data Level Register - 0x00000000 - - - DMARDL - Receive Data Level. This bit field controls the level at which a DMA request is made by the receive logic. The watermark level = DMARDL+1; that is, dma_rx_req is generated when the number of valid data entries in the receive FIFO is equal to or more than this field value + 1, and RDMAE =1. For instance, when DMARDL is 0, then dma_rx_req is asserted when 1 or more data entries are present in the receive FIFO. - - Reset value: 0x0 - [3:0] - read-write - - - - - IC_SDA_SETUP - 0x00000094 - I2C SDA Setup Register - - This register controls the amount of time delay (in terms of number of ic_clk clock periods) introduced in the rising edge of SCL - relative to SDA changing - when DW_apb_i2c services a read request in a slave-transmitter operation. The relevant I2C requirement is tSU:DAT (note 4) as detailed in the I2C Bus Specification. This register must be programmed with a value equal to or greater than 2. - - Writes to this register succeed only when IC_ENABLE[0] = 0. - - Note: The length of setup time is calculated using [(IC_SDA_SETUP - 1) * (ic_clk_period)], so if the user requires 10 ic_clk periods of setup time, they should program a value of 11. The IC_SDA_SETUP register is only used by the DW_apb_i2c when operating as a slave transmitter. - 0x00000064 - - - SDA_SETUP - SDA Setup. It is recommended that if the required delay is 1000ns, then for an ic_clk frequency of 10 MHz, IC_SDA_SETUP should be programmed to a value of 11. IC_SDA_SETUP must be programmed with a minimum value of 2. - [7:0] - read-write - - - - - IC_ACK_GENERAL_CALL - 0x00000098 - I2C ACK General Call Register - - The register controls whether DW_apb_i2c responds with a ACK or NACK when it receives an I2C General Call address. - - This register is applicable only when the DW_apb_i2c is in slave mode. - 0x00000001 - - - ACK_GEN_CALL - ACK General Call. When set to 1, DW_apb_i2c responds with a ACK (by asserting ic_data_oe) when it receives a General Call. Otherwise, DW_apb_i2c responds with a NACK (by negating ic_data_oe). - [0:0] - read-write - - - DISABLED - 0 - Generate NACK for a General Call - - - ENABLED - 1 - Generate ACK for a General Call - - - - - - - IC_ENABLE_STATUS - 0x0000009c - I2C Enable Status Register - - The register is used to report the DW_apb_i2c hardware status when the IC_ENABLE[0] register is set from 1 to 0; that is, when DW_apb_i2c is disabled. - - If IC_ENABLE[0] has been set to 1, bits 2:1 are forced to 0, and bit 0 is forced to 1. - - If IC_ENABLE[0] has been set to 0, bits 2:1 is only be valid as soon as bit 0 is read as '0'. - - Note: When IC_ENABLE[0] has been set to 0, a delay occurs for bit 0 to be read as 0 because disabling the DW_apb_i2c depends on I2C bus activities. - 0x00000000 - - - SLV_RX_DATA_LOST - Slave Received Data Lost. This bit indicates if a Slave-Receiver operation has been aborted with at least one data byte received from an I2C transfer due to the setting bit 0 of IC_ENABLE from 1 to 0. When read as 1, DW_apb_i2c is deemed to have been actively engaged in an aborted I2C transfer (with matching address) and the data phase of the I2C transfer has been entered, even though a data byte has been responded with a NACK. - - Note: If the remote I2C master terminates the transfer with a STOP condition before the DW_apb_i2c has a chance to NACK a transfer, and IC_ENABLE[0] has been set to 0, then this bit is also set to 1. - - When read as 0, DW_apb_i2c is deemed to have been disabled without being actively involved in the data phase of a Slave-Receiver transfer. - - Note: The CPU can safely read this bit when IC_EN (bit 0) is read as 0. - - Reset value: 0x0 - [2:2] - read-only - - - INACTIVE - 0 - Slave RX Data is not lost - - - ACTIVE - 1 - Slave RX Data is lost - - - - - SLV_DISABLED_WHILE_BUSY - Slave Disabled While Busy (Transmit, Receive). This bit indicates if a potential or active Slave operation has been aborted due to the setting bit 0 of the IC_ENABLE register from 1 to 0. This bit is set when the CPU writes a 0 to the IC_ENABLE register while: - - (a) DW_apb_i2c is receiving the address byte of the Slave-Transmitter operation from a remote master; - - OR, - - (b) address and data bytes of the Slave-Receiver operation from a remote master. - - When read as 1, DW_apb_i2c is deemed to have forced a NACK during any part of an I2C transfer, irrespective of whether the I2C address matches the slave address set in DW_apb_i2c (IC_SAR register) OR if the transfer is completed before IC_ENABLE is set to 0 but has not taken effect. - - Note: If the remote I2C master terminates the transfer with a STOP condition before the DW_apb_i2c has a chance to NACK a transfer, and IC_ENABLE[0] has been set to 0, then this bit will also be set to 1. - - When read as 0, DW_apb_i2c is deemed to have been disabled when there is master activity, or when the I2C bus is idle. - - Note: The CPU can safely read this bit when IC_EN (bit 0) is read as 0. - - Reset value: 0x0 - [1:1] - read-only - - - INACTIVE - 0 - Slave is disabled when it is idle - - - ACTIVE - 1 - Slave is disabled when it is active - - - - - IC_EN - ic_en Status. This bit always reflects the value driven on the output port ic_en. - When read as 1, DW_apb_i2c is deemed to be in an enabled state. - When read as 0, DW_apb_i2c is deemed completely inactive. Note: The CPU can safely read this bit anytime. When this bit is read as 0, the CPU can safely read SLV_RX_DATA_LOST (bit 2) and SLV_DISABLED_WHILE_BUSY (bit 1). - - Reset value: 0x0 - [0:0] - read-only - - - DISABLED - 0 - I2C disabled - - - ENABLED - 1 - I2C enabled - - - - - - - IC_FS_SPKLEN - 0x000000a0 - I2C SS, FS or FM+ spike suppression limit - - This register is used to store the duration, measured in ic_clk cycles, of the longest spike that is filtered out by the spike suppression logic when the component is operating in SS, FS or FM+ modes. The relevant I2C requirement is tSP (table 4) as detailed in the I2C Bus Specification. This register must be programmed with a minimum value of 1. - 0x00000007 - - - IC_FS_SPKLEN - This register must be set before any I2C bus transaction can take place to ensure stable operation. This register sets the duration, measured in ic_clk cycles, of the longest spike in the SCL or SDA lines that will be filtered out by the spike suppression logic. This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect. The minimum valid value is 1; hardware prevents values less than this being written, and if attempted results in 1 being set. or more information, refer to 'Spike Suppression'. - [7:0] - read-write - - - - - IC_CLR_RESTART_DET - 0x000000a8 - Clear RESTART_DET Interrupt Register - 0x00000000 - - - CLR_RESTART_DET - Read this register to clear the RESTART_DET interrupt (bit 12) of IC_RAW_INTR_STAT register. - - Reset value: 0x0 - [0:0] - read-only - - - - - IC_COMP_PARAM_1 - 0x000000f4 - Component Parameter Register 1 - - Note This register is not implemented and therefore reads as 0. If it was implemented it would be a constant read-only register that contains encoded information about the component's parameter settings. Fields shown below are the settings for those parameters - 0x00000000 - - - TX_BUFFER_DEPTH - TX Buffer Depth = 16 - [23:16] - read-only - - - RX_BUFFER_DEPTH - RX Buffer Depth = 16 - [15:8] - read-only - - - ADD_ENCODED_PARAMS - Encoded parameters not visible - [7:7] - read-only - - - HAS_DMA - DMA handshaking signals are enabled - [6:6] - read-only - - - INTR_IO - COMBINED Interrupt outputs - [5:5] - read-only - - - HC_COUNT_VALUES - Programmable count values for each mode. - [4:4] - read-only - - - MAX_SPEED_MODE - MAX SPEED MODE = FAST MODE - [3:2] - read-only - - - APB_DATA_WIDTH - APB data bus width is 32 bits - [1:0] - read-only - - - - - IC_COMP_VERSION - 0x000000f8 - I2C Component Version Register - 0x3230312a - - - IC_COMP_VERSION - [31:0] - read-only - - - - - IC_COMP_TYPE - 0x000000fc - I2C Component Type Register - 0x44570140 - - - IC_COMP_TYPE - Designware Component Type number = 0x44_57_01_40. This assigned unique hex value is constant and is derived from the two ASCII letters 'DW' followed by a 16-bit unsigned number. - [31:0] - read-only - - - - - - - I2C1 - 0x40048000 - - I2C1_IRQ - 24 - - - - SPI0 - 0x4003c000 - - 0 - 4096 - registers - - - SPI0_IRQ - 18 - - - - SSPCR0 - 0x00000000 - Control register 0, SSPCR0 on page 3-4 - 0x00000000 - - - SCR - Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: F SSPCLK CPSDVSR x (1+SCR) where CPSDVSR is an even value from 2-254, programmed through the SSPCPSR register and SCR is a value from 0-255. - [15:8] - read-write - - - SPH - SSPCLKOUT phase, applicable to Motorola SPI frame format only. See Motorola SPI frame format on page 2-10. - [7:7] - read-write - - - SPO - SSPCLKOUT polarity, applicable to Motorola SPI frame format only. See Motorola SPI frame format on page 2-10. - [6:6] - read-write - - - FRF - Frame format: 00 Motorola SPI frame format. 01 TI synchronous serial frame format. 10 National Microwire frame format. 11 Reserved, undefined operation. - [5:4] - read-write - - - DSS - Data Size Select: 0000 Reserved, undefined operation. 0001 Reserved, undefined operation. 0010 Reserved, undefined operation. 0011 4-bit data. 0100 5-bit data. 0101 6-bit data. 0110 7-bit data. 0111 8-bit data. 1000 9-bit data. 1001 10-bit data. 1010 11-bit data. 1011 12-bit data. 1100 13-bit data. 1101 14-bit data. 1110 15-bit data. 1111 16-bit data. - [3:0] - read-write - - - - - SSPCR1 - 0x00000004 - Control register 1, SSPCR1 on page 3-5 - 0x00000000 - - - SOD - Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line: 0 SSP can drive the SSPTXD output in slave mode. 1 SSP must not drive the SSPTXD output in slave mode. - [3:3] - read-write - - - MS - Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0: 0 Device configured as master, default. 1 Device configured as slave. - [2:2] - read-write - - - SSE - Synchronous serial port enable: 0 SSP operation disabled. 1 SSP operation enabled. - [1:1] - read-write - - - LBM - Loop back mode: 0 Normal serial port operation enabled. 1 Output of transmit serial shifter is connected to input of receive serial shifter internally. - [0:0] - read-write - - - - - SSPDR - 0x00000008 - Data register, SSPDR on page 3-6 - 0x00000000 - - - DATA - Transmit/Receive FIFO: Read Receive FIFO. Write Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies. - [15:0] - read-write - modify - - - - - SSPSR - 0x0000000c - Status register, SSPSR on page 3-7 - 0x00000003 - - - BSY - PrimeCell SSP busy flag, RO: 0 SSP is idle. 1 SSP is currently transmitting and/or receiving a frame or the transmit FIFO is not empty. - [4:4] - read-only - - - RFF - Receive FIFO full, RO: 0 Receive FIFO is not full. 1 Receive FIFO is full. - [3:3] - read-only - - - RNE - Receive FIFO not empty, RO: 0 Receive FIFO is empty. 1 Receive FIFO is not empty. - [2:2] - read-only - - - TNF - Transmit FIFO not full, RO: 0 Transmit FIFO is full. 1 Transmit FIFO is not full. - [1:1] - read-only - - - TFE - Transmit FIFO empty, RO: 0 Transmit FIFO is not empty. 1 Transmit FIFO is empty. - [0:0] - read-only - - - - - SSPCPSR - 0x00000010 - Clock prescale register, SSPCPSR on page 3-8 - 0x00000000 - - - CPSDVSR - Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads. - [7:0] - read-write - - - - - SSPIMSC - 0x00000014 - Interrupt mask set or clear register, SSPIMSC on page 3-9 - 0x00000000 - - - TXIM - Transmit FIFO interrupt mask: 0 Transmit FIFO half empty or less condition interrupt is masked. 1 Transmit FIFO half empty or less condition interrupt is not masked. - [3:3] - read-write - - - RXIM - Receive FIFO interrupt mask: 0 Receive FIFO half full or less condition interrupt is masked. 1 Receive FIFO half full or less condition interrupt is not masked. - [2:2] - read-write - - - RTIM - Receive timeout interrupt mask: 0 Receive FIFO not empty and no read prior to timeout period interrupt is masked. 1 Receive FIFO not empty and no read prior to timeout period interrupt is not masked. - [1:1] - read-write - - - RORIM - Receive overrun interrupt mask: 0 Receive FIFO written to while full condition interrupt is masked. 1 Receive FIFO written to while full condition interrupt is not masked. - [0:0] - read-write - - - - - SSPRIS - 0x00000018 - Raw interrupt status register, SSPRIS on page 3-10 - 0x00000008 - - - TXRIS - Gives the raw interrupt state, prior to masking, of the SSPTXINTR interrupt - [3:3] - read-only - - - RXRIS - Gives the raw interrupt state, prior to masking, of the SSPRXINTR interrupt - [2:2] - read-only - - - RTRIS - Gives the raw interrupt state, prior to masking, of the SSPRTINTR interrupt - [1:1] - read-only - - - RORRIS - Gives the raw interrupt state, prior to masking, of the SSPRORINTR interrupt - [0:0] - read-only - - - - - SSPMIS - 0x0000001c - Masked interrupt status register, SSPMIS on page 3-11 - 0x00000000 - - - TXMIS - Gives the transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt - [3:3] - read-only - - - RXMIS - Gives the receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt - [2:2] - read-only - - - RTMIS - Gives the receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt - [1:1] - read-only - - - RORMIS - Gives the receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt - [0:0] - read-only - - - - - SSPICR - 0x00000020 - Interrupt clear register, SSPICR on page 3-11 - 0x00000000 - - - RTIC - Clears the SSPRTINTR interrupt - [1:1] - read-write - oneToClear - - - RORIC - Clears the SSPRORINTR interrupt - [0:0] - read-write - oneToClear - - - - - SSPDMACR - 0x00000024 - DMA control register, SSPDMACR on page 3-12 - 0x00000000 - - - TXDMAE - Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled. - [1:1] - read-write - - - RXDMAE - Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled. - [0:0] - read-write - - - - - SSPPERIPHID0 - 0x00000fe0 - Peripheral identification registers, SSPPeriphID0-3 on page 3-13 - 0x00000022 - - - PARTNUMBER0 - These bits read back as 0x22 - [7:0] - read-only - - - - - SSPPERIPHID1 - 0x00000fe4 - Peripheral identification registers, SSPPeriphID0-3 on page 3-13 - 0x00000010 - - - DESIGNER0 - These bits read back as 0x1 - [7:4] - read-only - - - PARTNUMBER1 - These bits read back as 0x0 - [3:0] - read-only - - - - - SSPPERIPHID2 - 0x00000fe8 - Peripheral identification registers, SSPPeriphID0-3 on page 3-13 - 0x00000034 - - - REVISION - These bits return the peripheral revision - [7:4] - read-only - - - DESIGNER1 - These bits read back as 0x4 - [3:0] - read-only - - - - - SSPPERIPHID3 - 0x00000fec - Peripheral identification registers, SSPPeriphID0-3 on page 3-13 - 0x00000000 - - - CONFIGURATION - These bits read back as 0x00 - [7:0] - read-only - - - - - SSPPCELLID0 - 0x00000ff0 - PrimeCell identification registers, SSPPCellID0-3 on page 3-16 - 0x0000000d - - - SSPPCELLID0 - These bits read back as 0x0D - [7:0] - read-only - - - - - SSPPCELLID1 - 0x00000ff4 - PrimeCell identification registers, SSPPCellID0-3 on page 3-16 - 0x000000f0 - - - SSPPCELLID1 - These bits read back as 0xF0 - [7:0] - read-only - - - - - SSPPCELLID2 - 0x00000ff8 - PrimeCell identification registers, SSPPCellID0-3 on page 3-16 - 0x00000005 - - - SSPPCELLID2 - These bits read back as 0x05 - [7:0] - read-only - - - - - SSPPCELLID3 - 0x00000ffc - PrimeCell identification registers, SSPPCellID0-3 on page 3-16 - 0x000000b1 - - - SSPPCELLID3 - These bits read back as 0xB1 - [7:0] - read-only - - - - - - - SPI1 - 0x40040000 - - SPI1_IRQ - 19 - - - - PIO0 - Programmable IO block - 0x50200000 - - 0 - 324 - registers - - - PIO0_IRQ_0 - 7 - - - PIO0_IRQ_1 - 8 - - - - CTRL - 0x00000000 - PIO control register - 0x00000000 - - - CLKDIV_RESTART - Restart a state machine's clock divider from an initial phase of 0. Clock dividers are free-running, so once started, their output (including fractional jitter) is completely determined by the integer/fractional divisor configured in SMx_CLKDIV. This means that, if multiple clock dividers with the same divisor are restarted simultaneously, by writing multiple 1 bits to this field, the execution clocks of those state machines will run in precise lockstep. - - Note that setting/clearing SM_ENABLE does not stop the clock divider from running, so once multiple state machines' clocks are synchronised, it is safe to disable/reenable a state machine, whilst keeping the clock dividers in sync. - - Note also that CLKDIV_RESTART can be written to whilst the state machine is running, and this is useful to resynchronise clock dividers after the divisors (SMx_CLKDIV) have been changed on-the-fly. - [11:8] - write-only - - - SM_RESTART - Write 1 to instantly clear internal SM state which may be otherwise difficult to access and will affect future execution. - - Specifically, the following are cleared: input and output shift counters; the contents of the input shift register; the delay counter; the waiting-on-IRQ state; any stalled instruction written to SMx_INSTR or run by OUT/MOV EXEC; any pin write left asserted due to OUT_STICKY. - - The program counter, the contents of the output shift register and the X/Y scratch registers are not affected. - [7:4] - write-only - - - SM_ENABLE - Enable/disable each of the four state machines by writing 1/0 to each of these four bits. When disabled, a state machine will cease executing instructions, except those written directly to SMx_INSTR by the system. Multiple bits can be set/cleared at once to run/halt multiple state machines simultaneously. - [3:0] - read-write - - - - - FSTAT - 0x00000004 - FIFO status register - 0x0f000f00 - - - TXEMPTY - State machine TX FIFO is empty - [27:24] - read-only - - - TXFULL - State machine TX FIFO is full - [19:16] - read-only - - - RXEMPTY - State machine RX FIFO is empty - [11:8] - read-only - - - RXFULL - State machine RX FIFO is full - [3:0] - read-only - - - - - FDEBUG - 0x00000008 - FIFO debug register - 0x00000000 - - - TXSTALL - State machine has stalled on empty TX FIFO during a blocking PULL, or an OUT with autopull enabled. Write 1 to clear. - [27:24] - read-write - oneToClear - - - TXOVER - TX FIFO overflow (i.e. write-on-full by the system) has occurred. Write 1 to clear. Note that write-on-full does not alter the state or contents of the FIFO in any way, but the data that the system attempted to write is dropped, so if this flag is set, your software has quite likely dropped some data on the floor. - [19:16] - read-write - oneToClear - - - RXUNDER - RX FIFO underflow (i.e. read-on-empty by the system) has occurred. Write 1 to clear. Note that read-on-empty does not perturb the state of the FIFO in any way, but the data returned by reading from an empty FIFO is undefined, so this flag generally only becomes set due to some kind of software error. - [11:8] - read-write - oneToClear - - - RXSTALL - State machine has stalled on full RX FIFO during a blocking PUSH, or an IN with autopush enabled. This flag is also set when a nonblocking PUSH to a full FIFO took place, in which case the state machine has dropped data. Write 1 to clear. - [3:0] - read-write - oneToClear - - - - - FLEVEL - 0x0000000c - FIFO levels - 0x00000000 - - - RX3 - [31:28] - read-only - - - TX3 - [27:24] - read-only - - - RX2 - [23:20] - read-only - - - TX2 - [19:16] - read-only - - - RX1 - [15:12] - read-only - - - TX1 - [11:8] - read-only - - - RX0 - [7:4] - read-only - - - TX0 - [3:0] - read-only - - - - - TXF0 - 0x00000010 - Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO. - 0x00000000 - - - TXF0 - [31:0] - write-only - - - - - TXF1 - 0x00000014 - Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO. - 0x00000000 - - - TXF1 - [31:0] - write-only - - - - - TXF2 - 0x00000018 - Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO. - 0x00000000 - - - TXF2 - [31:0] - write-only - - - - - TXF3 - 0x0000001c - Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO. - 0x00000000 - - - TXF3 - [31:0] - write-only - - - - - RXF0 - 0x00000020 - Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined. - 0x00000000 - - - RXF0 - [31:0] - read-only - modify - - - - - RXF1 - 0x00000024 - Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined. - 0x00000000 - - - RXF1 - [31:0] - read-only - modify - - - - - RXF2 - 0x00000028 - Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined. - 0x00000000 - - - RXF2 - [31:0] - read-only - modify - - - - - RXF3 - 0x0000002c - Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined. - 0x00000000 - - - RXF3 - [31:0] - read-only - modify - - - - - IRQ - 0x00000030 - State machine IRQ flags register. Write 1 to clear. There are 8 state machine IRQ flags, which can be set, cleared, and waited on by the state machines. There's no fixed association between flags and state machines -- any state machine can use any flag. - - Any of the 8 flags can be used for timing synchronisation between state machines, using IRQ and WAIT instructions. The lower four of these flags are also routed out to system-level interrupt requests, alongside FIFO status interrupts -- see e.g. IRQ0_INTE. - 0x00000000 - - - IRQ - [7:0] - read-write - oneToClear - - - - - IRQ_FORCE - 0x00000034 - Writing a 1 to each of these bits will forcibly assert the corresponding IRQ. Note this is different to the INTF register: writing here affects PIO internal state. INTF just asserts the processor-facing IRQ signal for testing ISRs, and is not visible to the state machines. - 0x00000000 - - - IRQ_FORCE - [7:0] - write-only - - - - - INPUT_SYNC_BYPASS - 0x00000038 - There is a 2-flipflop synchronizer on each GPIO input, which protects PIO logic from metastabilities. This increases input delay, and for fast synchronous IO (e.g. SPI) these synchronizers may need to be bypassed. Each bit in this register corresponds to one GPIO. - 0 -> input is synchronized (default) - 1 -> synchronizer is bypassed - If in doubt, leave this register as all zeroes. - 0x00000000 - - - INPUT_SYNC_BYPASS - [31:0] - read-write - - - - - DBG_PADOUT - 0x0000003c - Read to sample the pad output values PIO is currently driving to the GPIOs. On RP2040 there are 30 GPIOs, so the two most significant bits are hardwired to 0. - 0x00000000 - - - DBG_PADOUT - [31:0] - read-only - - - - - DBG_PADOE - 0x00000040 - Read to sample the pad output enables (direction) PIO is currently driving to the GPIOs. On RP2040 there are 30 GPIOs, so the two most significant bits are hardwired to 0. - 0x00000000 - - - DBG_PADOE - [31:0] - read-only - - - - - DBG_CFGINFO - 0x00000044 - The PIO hardware has some free parameters that may vary between chip products. - These should be provided in the chip datasheet, but are also exposed here. - 0x00000000 - - - IMEM_SIZE - The size of the instruction memory, measured in units of one instruction - [21:16] - read-only - - - SM_COUNT - The number of state machines this PIO instance is equipped with. - [11:8] - read-only - - - FIFO_DEPTH - The depth of the state machine TX/RX FIFOs, measured in words. - Joining fifos via SHIFTCTRL_FJOIN gives one FIFO with double - this depth. - [5:0] - read-only - - - - - INSTR_MEM0 - 0x00000048 - Write-only access to instruction memory location 0 - 0x00000000 - - - INSTR_MEM0 - [15:0] - write-only - - - - - INSTR_MEM1 - 0x0000004c - Write-only access to instruction memory location 1 - 0x00000000 - - - INSTR_MEM1 - [15:0] - write-only - - - - - INSTR_MEM2 - 0x00000050 - Write-only access to instruction memory location 2 - 0x00000000 - - - INSTR_MEM2 - [15:0] - write-only - - - - - INSTR_MEM3 - 0x00000054 - Write-only access to instruction memory location 3 - 0x00000000 - - - INSTR_MEM3 - [15:0] - write-only - - - - - INSTR_MEM4 - 0x00000058 - Write-only access to instruction memory location 4 - 0x00000000 - - - INSTR_MEM4 - [15:0] - write-only - - - - - INSTR_MEM5 - 0x0000005c - Write-only access to instruction memory location 5 - 0x00000000 - - - INSTR_MEM5 - [15:0] - write-only - - - - - INSTR_MEM6 - 0x00000060 - Write-only access to instruction memory location 6 - 0x00000000 - - - INSTR_MEM6 - [15:0] - write-only - - - - - INSTR_MEM7 - 0x00000064 - Write-only access to instruction memory location 7 - 0x00000000 - - - INSTR_MEM7 - [15:0] - write-only - - - - - INSTR_MEM8 - 0x00000068 - Write-only access to instruction memory location 8 - 0x00000000 - - - INSTR_MEM8 - [15:0] - write-only - - - - - INSTR_MEM9 - 0x0000006c - Write-only access to instruction memory location 9 - 0x00000000 - - - INSTR_MEM9 - [15:0] - write-only - - - - - INSTR_MEM10 - 0x00000070 - Write-only access to instruction memory location 10 - 0x00000000 - - - INSTR_MEM10 - [15:0] - write-only - - - - - INSTR_MEM11 - 0x00000074 - Write-only access to instruction memory location 11 - 0x00000000 - - - INSTR_MEM11 - [15:0] - write-only - - - - - INSTR_MEM12 - 0x00000078 - Write-only access to instruction memory location 12 - 0x00000000 - - - INSTR_MEM12 - [15:0] - write-only - - - - - INSTR_MEM13 - 0x0000007c - Write-only access to instruction memory location 13 - 0x00000000 - - - INSTR_MEM13 - [15:0] - write-only - - - - - INSTR_MEM14 - 0x00000080 - Write-only access to instruction memory location 14 - 0x00000000 - - - INSTR_MEM14 - [15:0] - write-only - - - - - INSTR_MEM15 - 0x00000084 - Write-only access to instruction memory location 15 - 0x00000000 - - - INSTR_MEM15 - [15:0] - write-only - - - - - INSTR_MEM16 - 0x00000088 - Write-only access to instruction memory location 16 - 0x00000000 - - - INSTR_MEM16 - [15:0] - write-only - - - - - INSTR_MEM17 - 0x0000008c - Write-only access to instruction memory location 17 - 0x00000000 - - - INSTR_MEM17 - [15:0] - write-only - - - - - INSTR_MEM18 - 0x00000090 - Write-only access to instruction memory location 18 - 0x00000000 - - - INSTR_MEM18 - [15:0] - write-only - - - - - INSTR_MEM19 - 0x00000094 - Write-only access to instruction memory location 19 - 0x00000000 - - - INSTR_MEM19 - [15:0] - write-only - - - - - INSTR_MEM20 - 0x00000098 - Write-only access to instruction memory location 20 - 0x00000000 - - - INSTR_MEM20 - [15:0] - write-only - - - - - INSTR_MEM21 - 0x0000009c - Write-only access to instruction memory location 21 - 0x00000000 - - - INSTR_MEM21 - [15:0] - write-only - - - - - INSTR_MEM22 - 0x000000a0 - Write-only access to instruction memory location 22 - 0x00000000 - - - INSTR_MEM22 - [15:0] - write-only - - - - - INSTR_MEM23 - 0x000000a4 - Write-only access to instruction memory location 23 - 0x00000000 - - - INSTR_MEM23 - [15:0] - write-only - - - - - INSTR_MEM24 - 0x000000a8 - Write-only access to instruction memory location 24 - 0x00000000 - - - INSTR_MEM24 - [15:0] - write-only - - - - - INSTR_MEM25 - 0x000000ac - Write-only access to instruction memory location 25 - 0x00000000 - - - INSTR_MEM25 - [15:0] - write-only - - - - - INSTR_MEM26 - 0x000000b0 - Write-only access to instruction memory location 26 - 0x00000000 - - - INSTR_MEM26 - [15:0] - write-only - - - - - INSTR_MEM27 - 0x000000b4 - Write-only access to instruction memory location 27 - 0x00000000 - - - INSTR_MEM27 - [15:0] - write-only - - - - - INSTR_MEM28 - 0x000000b8 - Write-only access to instruction memory location 28 - 0x00000000 - - - INSTR_MEM28 - [15:0] - write-only - - - - - INSTR_MEM29 - 0x000000bc - Write-only access to instruction memory location 29 - 0x00000000 - - - INSTR_MEM29 - [15:0] - write-only - - - - - INSTR_MEM30 - 0x000000c0 - Write-only access to instruction memory location 30 - 0x00000000 - - - INSTR_MEM30 - [15:0] - write-only - - - - - INSTR_MEM31 - 0x000000c4 - Write-only access to instruction memory location 31 - 0x00000000 - - - INSTR_MEM31 - [15:0] - write-only - - - - - SM0_CLKDIV - 0x000000c8 - Clock divisor register for state machine 0 - Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) - 0x00010000 - - - INT - Effective frequency is sysclk/(int + frac/256). - Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0. - [31:16] - read-write - - - FRAC - Fractional part of clock divisor - [15:8] - read-write - - - - - SM0_EXECCTRL - 0x000000cc - Execution/behavioural settings for state machine 0 - 0x0001f000 - - - EXEC_STALLED - If 1, an instruction written to SMx_INSTR is stalled, and latched by the state machine. Will clear to 0 once this instruction completes. - [31:31] - read-only - - - SIDE_EN - If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit. - [30:30] - read-write - - - SIDE_PINDIR - If 1, side-set data is asserted to pin directions, instead of pin values - [29:29] - read-write - - - JMP_PIN - The GPIO number to use as condition for JMP PIN. Unaffected by input mapping. - [28:24] - read-write - - - OUT_EN_SEL - Which data bit to use for inline OUT enable - [23:19] - read-write - - - INLINE_OUT_EN - If 1, use a bit of OUT data as an auxiliary write enable - When used in conjunction with OUT_STICKY, writes with an enable of 0 will - deassert the latest pin write. This can create useful masking/override behaviour - due to the priority ordering of state machine pin writes (SM0 < SM1 < ...) - [18:18] - read-write - - - OUT_STICKY - Continuously assert the most recent OUT/SET to the pins - [17:17] - read-write - - - WRAP_TOP - After reaching this address, execution is wrapped to wrap_bottom. - If the instruction is a jump, and the jump condition is true, the jump takes priority. - [16:12] - read-write - - - WRAP_BOTTOM - After reaching wrap_top, execution is wrapped to this address. - [11:7] - read-write - - - STATUS_SEL - Comparison used for the MOV x, STATUS instruction. - [4:4] - read-write - - - TXLEVEL - 0 - All-ones if TX FIFO level < N, otherwise all-zeroes - - - RXLEVEL - 1 - All-ones if RX FIFO level < N, otherwise all-zeroes - - - - - STATUS_N - Comparison level for the MOV x, STATUS instruction - [3:0] - read-write - - - - - SM0_SHIFTCTRL - 0x000000d0 - Control behaviour of the input/output shift registers for state machine 0 - 0x000c0000 - - - FJOIN_RX - When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep. - TX FIFO is disabled as a result (always reads as both full and empty). - FIFOs are flushed when this bit is changed. - [31:31] - read-write - - - FJOIN_TX - When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep. - RX FIFO is disabled as a result (always reads as both full and empty). - FIFOs are flushed when this bit is changed. - [30:30] - read-write - - - PULL_THRESH - Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place. - Write 0 for value of 32. - [29:25] - read-write - - - PUSH_THRESH - Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place. - Write 0 for value of 32. - [24:20] - read-write - - - OUT_SHIFTDIR - 1 = shift out of output shift register to right. 0 = to left. - [19:19] - read-write - - - IN_SHIFTDIR - 1 = shift input shift register to right (data enters from left). 0 = to left. - [18:18] - read-write - - - AUTOPULL - Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH. - [17:17] - read-write - - - AUTOPUSH - Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH. - [16:16] - read-write - - - - - SM0_ADDR - 0x000000d4 - Current instruction address of state machine 0 - 0x00000000 - - - SM0_ADDR - [4:0] - read-only - - - - - SM0_INSTR - 0x000000d8 - Read to see the instruction currently addressed by state machine 0's program counter - Write to execute an instruction immediately (including jumps) and then resume execution. - 0x00000000 - - - SM0_INSTR - [15:0] - read-write - - - - - SM0_PINCTRL - 0x000000dc - State machine pin control - 0x14000000 - - - SIDESET_COUNT - The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no delay). - [31:29] - read-write - - - SET_COUNT - The number of pins asserted by a SET. In the range 0 to 5 inclusive. - [28:26] - read-write - - - OUT_COUNT - The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive. - [25:20] - read-write - - - IN_BASE - The pin which is mapped to the least-significant bit of a state machine's IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits, with a modulo of 32 applied to pin number. - [19:15] - read-write - - - SIDESET_BASE - The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction's side-set/delay field (up to 5, determined by SIDESET_COUNT) are used for side-set data, with the remaining LSBs used for delay. The least-significant bit of the side-set portion is the bit written to this pin, with more-significant bits written to higher-numbered pins. - [14:10] - read-write - - - SET_BASE - The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data. - [9:5] - read-write - - - OUT_BASE - The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data. - [4:0] - read-write - - - - - SM1_CLKDIV - 0x000000e0 - Clock divisor register for state machine 1 - Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) - 0x00010000 - - - INT - Effective frequency is sysclk/(int + frac/256). - Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0. - [31:16] - read-write - - - FRAC - Fractional part of clock divisor - [15:8] - read-write - - - - - SM1_EXECCTRL - 0x000000e4 - Execution/behavioural settings for state machine 1 - 0x0001f000 - - - EXEC_STALLED - If 1, an instruction written to SMx_INSTR is stalled, and latched by the state machine. Will clear to 0 once this instruction completes. - [31:31] - read-only - - - SIDE_EN - If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit. - [30:30] - read-write - - - SIDE_PINDIR - If 1, side-set data is asserted to pin directions, instead of pin values - [29:29] - read-write - - - JMP_PIN - The GPIO number to use as condition for JMP PIN. Unaffected by input mapping. - [28:24] - read-write - - - OUT_EN_SEL - Which data bit to use for inline OUT enable - [23:19] - read-write - - - INLINE_OUT_EN - If 1, use a bit of OUT data as an auxiliary write enable - When used in conjunction with OUT_STICKY, writes with an enable of 0 will - deassert the latest pin write. This can create useful masking/override behaviour - due to the priority ordering of state machine pin writes (SM0 < SM1 < ...) - [18:18] - read-write - - - OUT_STICKY - Continuously assert the most recent OUT/SET to the pins - [17:17] - read-write - - - WRAP_TOP - After reaching this address, execution is wrapped to wrap_bottom. - If the instruction is a jump, and the jump condition is true, the jump takes priority. - [16:12] - read-write - - - WRAP_BOTTOM - After reaching wrap_top, execution is wrapped to this address. - [11:7] - read-write - - - STATUS_SEL - Comparison used for the MOV x, STATUS instruction. - [4:4] - read-write - - - TXLEVEL - 0 - All-ones if TX FIFO level < N, otherwise all-zeroes - - - RXLEVEL - 1 - All-ones if RX FIFO level < N, otherwise all-zeroes - - - - - STATUS_N - Comparison level for the MOV x, STATUS instruction - [3:0] - read-write - - - - - SM1_SHIFTCTRL - 0x000000e8 - Control behaviour of the input/output shift registers for state machine 1 - 0x000c0000 - - - FJOIN_RX - When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep. - TX FIFO is disabled as a result (always reads as both full and empty). - FIFOs are flushed when this bit is changed. - [31:31] - read-write - - - FJOIN_TX - When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep. - RX FIFO is disabled as a result (always reads as both full and empty). - FIFOs are flushed when this bit is changed. - [30:30] - read-write - - - PULL_THRESH - Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place. - Write 0 for value of 32. - [29:25] - read-write - - - PUSH_THRESH - Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place. - Write 0 for value of 32. - [24:20] - read-write - - - OUT_SHIFTDIR - 1 = shift out of output shift register to right. 0 = to left. - [19:19] - read-write - - - IN_SHIFTDIR - 1 = shift input shift register to right (data enters from left). 0 = to left. - [18:18] - read-write - - - AUTOPULL - Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH. - [17:17] - read-write - - - AUTOPUSH - Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH. - [16:16] - read-write - - - - - SM1_ADDR - 0x000000ec - Current instruction address of state machine 1 - 0x00000000 - - - SM1_ADDR - [4:0] - read-only - - - - - SM1_INSTR - 0x000000f0 - Read to see the instruction currently addressed by state machine 1's program counter - Write to execute an instruction immediately (including jumps) and then resume execution. - 0x00000000 - - - SM1_INSTR - [15:0] - read-write - - - - - SM1_PINCTRL - 0x000000f4 - State machine pin control - 0x14000000 - - - SIDESET_COUNT - The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no delay). - [31:29] - read-write - - - SET_COUNT - The number of pins asserted by a SET. In the range 0 to 5 inclusive. - [28:26] - read-write - - - OUT_COUNT - The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive. - [25:20] - read-write - - - IN_BASE - The pin which is mapped to the least-significant bit of a state machine's IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits, with a modulo of 32 applied to pin number. - [19:15] - read-write - - - SIDESET_BASE - The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction's side-set/delay field (up to 5, determined by SIDESET_COUNT) are used for side-set data, with the remaining LSBs used for delay. The least-significant bit of the side-set portion is the bit written to this pin, with more-significant bits written to higher-numbered pins. - [14:10] - read-write - - - SET_BASE - The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data. - [9:5] - read-write - - - OUT_BASE - The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data. - [4:0] - read-write - - - - - SM2_CLKDIV - 0x000000f8 - Clock divisor register for state machine 2 - Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) - 0x00010000 - - - INT - Effective frequency is sysclk/(int + frac/256). - Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0. - [31:16] - read-write - - - FRAC - Fractional part of clock divisor - [15:8] - read-write - - - - - SM2_EXECCTRL - 0x000000fc - Execution/behavioural settings for state machine 2 - 0x0001f000 - - - EXEC_STALLED - If 1, an instruction written to SMx_INSTR is stalled, and latched by the state machine. Will clear to 0 once this instruction completes. - [31:31] - read-only - - - SIDE_EN - If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit. - [30:30] - read-write - - - SIDE_PINDIR - If 1, side-set data is asserted to pin directions, instead of pin values - [29:29] - read-write - - - JMP_PIN - The GPIO number to use as condition for JMP PIN. Unaffected by input mapping. - [28:24] - read-write - - - OUT_EN_SEL - Which data bit to use for inline OUT enable - [23:19] - read-write - - - INLINE_OUT_EN - If 1, use a bit of OUT data as an auxiliary write enable - When used in conjunction with OUT_STICKY, writes with an enable of 0 will - deassert the latest pin write. This can create useful masking/override behaviour - due to the priority ordering of state machine pin writes (SM0 < SM1 < ...) - [18:18] - read-write - - - OUT_STICKY - Continuously assert the most recent OUT/SET to the pins - [17:17] - read-write - - - WRAP_TOP - After reaching this address, execution is wrapped to wrap_bottom. - If the instruction is a jump, and the jump condition is true, the jump takes priority. - [16:12] - read-write - - - WRAP_BOTTOM - After reaching wrap_top, execution is wrapped to this address. - [11:7] - read-write - - - STATUS_SEL - Comparison used for the MOV x, STATUS instruction. - [4:4] - read-write - - - TXLEVEL - 0 - All-ones if TX FIFO level < N, otherwise all-zeroes - - - RXLEVEL - 1 - All-ones if RX FIFO level < N, otherwise all-zeroes - - - - - STATUS_N - Comparison level for the MOV x, STATUS instruction - [3:0] - read-write - - - - - SM2_SHIFTCTRL - 0x00000100 - Control behaviour of the input/output shift registers for state machine 2 - 0x000c0000 - - - FJOIN_RX - When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep. - TX FIFO is disabled as a result (always reads as both full and empty). - FIFOs are flushed when this bit is changed. - [31:31] - read-write - - - FJOIN_TX - When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep. - RX FIFO is disabled as a result (always reads as both full and empty). - FIFOs are flushed when this bit is changed. - [30:30] - read-write - - - PULL_THRESH - Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place. - Write 0 for value of 32. - [29:25] - read-write - - - PUSH_THRESH - Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place. - Write 0 for value of 32. - [24:20] - read-write - - - OUT_SHIFTDIR - 1 = shift out of output shift register to right. 0 = to left. - [19:19] - read-write - - - IN_SHIFTDIR - 1 = shift input shift register to right (data enters from left). 0 = to left. - [18:18] - read-write - - - AUTOPULL - Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH. - [17:17] - read-write - - - AUTOPUSH - Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH. - [16:16] - read-write - - - - - SM2_ADDR - 0x00000104 - Current instruction address of state machine 2 - 0x00000000 - - - SM2_ADDR - [4:0] - read-only - - - - - SM2_INSTR - 0x00000108 - Read to see the instruction currently addressed by state machine 2's program counter - Write to execute an instruction immediately (including jumps) and then resume execution. - 0x00000000 - - - SM2_INSTR - [15:0] - read-write - - - - - SM2_PINCTRL - 0x0000010c - State machine pin control - 0x14000000 - - - SIDESET_COUNT - The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no delay). - [31:29] - read-write - - - SET_COUNT - The number of pins asserted by a SET. In the range 0 to 5 inclusive. - [28:26] - read-write - - - OUT_COUNT - The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive. - [25:20] - read-write - - - IN_BASE - The pin which is mapped to the least-significant bit of a state machine's IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits, with a modulo of 32 applied to pin number. - [19:15] - read-write - - - SIDESET_BASE - The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction's side-set/delay field (up to 5, determined by SIDESET_COUNT) are used for side-set data, with the remaining LSBs used for delay. The least-significant bit of the side-set portion is the bit written to this pin, with more-significant bits written to higher-numbered pins. - [14:10] - read-write - - - SET_BASE - The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data. - [9:5] - read-write - - - OUT_BASE - The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data. - [4:0] - read-write - - - - - SM3_CLKDIV - 0x00000110 - Clock divisor register for state machine 3 - Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) - 0x00010000 - - - INT - Effective frequency is sysclk/(int + frac/256). - Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0. - [31:16] - read-write - - - FRAC - Fractional part of clock divisor - [15:8] - read-write - - - - - SM3_EXECCTRL - 0x00000114 - Execution/behavioural settings for state machine 3 - 0x0001f000 - - - EXEC_STALLED - If 1, an instruction written to SMx_INSTR is stalled, and latched by the state machine. Will clear to 0 once this instruction completes. - [31:31] - read-only - - - SIDE_EN - If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit. - [30:30] - read-write - - - SIDE_PINDIR - If 1, side-set data is asserted to pin directions, instead of pin values - [29:29] - read-write - - - JMP_PIN - The GPIO number to use as condition for JMP PIN. Unaffected by input mapping. - [28:24] - read-write - - - OUT_EN_SEL - Which data bit to use for inline OUT enable - [23:19] - read-write - - - INLINE_OUT_EN - If 1, use a bit of OUT data as an auxiliary write enable - When used in conjunction with OUT_STICKY, writes with an enable of 0 will - deassert the latest pin write. This can create useful masking/override behaviour - due to the priority ordering of state machine pin writes (SM0 < SM1 < ...) - [18:18] - read-write - - - OUT_STICKY - Continuously assert the most recent OUT/SET to the pins - [17:17] - read-write - - - WRAP_TOP - After reaching this address, execution is wrapped to wrap_bottom. - If the instruction is a jump, and the jump condition is true, the jump takes priority. - [16:12] - read-write - - - WRAP_BOTTOM - After reaching wrap_top, execution is wrapped to this address. - [11:7] - read-write - - - STATUS_SEL - Comparison used for the MOV x, STATUS instruction. - [4:4] - read-write - - - TXLEVEL - 0 - All-ones if TX FIFO level < N, otherwise all-zeroes - - - RXLEVEL - 1 - All-ones if RX FIFO level < N, otherwise all-zeroes - - - - - STATUS_N - Comparison level for the MOV x, STATUS instruction - [3:0] - read-write - - - - - SM3_SHIFTCTRL - 0x00000118 - Control behaviour of the input/output shift registers for state machine 3 - 0x000c0000 - - - FJOIN_RX - When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep. - TX FIFO is disabled as a result (always reads as both full and empty). - FIFOs are flushed when this bit is changed. - [31:31] - read-write - - - FJOIN_TX - When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep. - RX FIFO is disabled as a result (always reads as both full and empty). - FIFOs are flushed when this bit is changed. - [30:30] - read-write - - - PULL_THRESH - Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place. - Write 0 for value of 32. - [29:25] - read-write - - - PUSH_THRESH - Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place. - Write 0 for value of 32. - [24:20] - read-write - - - OUT_SHIFTDIR - 1 = shift out of output shift register to right. 0 = to left. - [19:19] - read-write - - - IN_SHIFTDIR - 1 = shift input shift register to right (data enters from left). 0 = to left. - [18:18] - read-write - - - AUTOPULL - Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH. - [17:17] - read-write - - - AUTOPUSH - Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH. - [16:16] - read-write - - - - - SM3_ADDR - 0x0000011c - Current instruction address of state machine 3 - 0x00000000 - - - SM3_ADDR - [4:0] - read-only - - - - - SM3_INSTR - 0x00000120 - Read to see the instruction currently addressed by state machine 3's program counter - Write to execute an instruction immediately (including jumps) and then resume execution. - 0x00000000 - - - SM3_INSTR - [15:0] - read-write - - - - - SM3_PINCTRL - 0x00000124 - State machine pin control - 0x14000000 - - - SIDESET_COUNT - The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no delay). - [31:29] - read-write - - - SET_COUNT - The number of pins asserted by a SET. In the range 0 to 5 inclusive. - [28:26] - read-write - - - OUT_COUNT - The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive. - [25:20] - read-write - - - IN_BASE - The pin which is mapped to the least-significant bit of a state machine's IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits, with a modulo of 32 applied to pin number. - [19:15] - read-write - - - SIDESET_BASE - The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction's side-set/delay field (up to 5, determined by SIDESET_COUNT) are used for side-set data, with the remaining LSBs used for delay. The least-significant bit of the side-set portion is the bit written to this pin, with more-significant bits written to higher-numbered pins. - [14:10] - read-write - - - SET_BASE - The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data. - [9:5] - read-write - - - OUT_BASE - The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data. - [4:0] - read-write - - - - - INTR - 0x00000128 - Raw Interrupts - 0x00000000 - - - SM3 - [11:11] - read-only - - - SM2 - [10:10] - read-only - - - SM1 - [9:9] - read-only - - - SM0 - [8:8] - read-only - - - SM3_TXNFULL - [7:7] - read-only - - - SM2_TXNFULL - [6:6] - read-only - - - SM1_TXNFULL - [5:5] - read-only - - - SM0_TXNFULL - [4:4] - read-only - - - SM3_RXNEMPTY - [3:3] - read-only - - - SM2_RXNEMPTY - [2:2] - read-only - - - SM1_RXNEMPTY - [1:1] - read-only - - - SM0_RXNEMPTY - [0:0] - read-only - - - - - IRQ0_INTE - 0x0000012c - Interrupt Enable for irq0 - 0x00000000 - - - SM3 - [11:11] - read-write - - - SM2 - [10:10] - read-write - - - SM1 - [9:9] - read-write - - - SM0 - [8:8] - read-write - - - SM3_TXNFULL - [7:7] - read-write - - - SM2_TXNFULL - [6:6] - read-write - - - SM1_TXNFULL - [5:5] - read-write - - - SM0_TXNFULL - [4:4] - read-write - - - SM3_RXNEMPTY - [3:3] - read-write - - - SM2_RXNEMPTY - [2:2] - read-write - - - SM1_RXNEMPTY - [1:1] - read-write - - - SM0_RXNEMPTY - [0:0] - read-write - - - - - IRQ0_INTF - 0x00000130 - Interrupt Force for irq0 - 0x00000000 - - - SM3 - [11:11] - read-write - - - SM2 - [10:10] - read-write - - - SM1 - [9:9] - read-write - - - SM0 - [8:8] - read-write - - - SM3_TXNFULL - [7:7] - read-write - - - SM2_TXNFULL - [6:6] - read-write - - - SM1_TXNFULL - [5:5] - read-write - - - SM0_TXNFULL - [4:4] - read-write - - - SM3_RXNEMPTY - [3:3] - read-write - - - SM2_RXNEMPTY - [2:2] - read-write - - - SM1_RXNEMPTY - [1:1] - read-write - - - SM0_RXNEMPTY - [0:0] - read-write - - - - - IRQ0_INTS - 0x00000134 - Interrupt status after masking & forcing for irq0 - 0x00000000 - - - SM3 - [11:11] - read-only - - - SM2 - [10:10] - read-only - - - SM1 - [9:9] - read-only - - - SM0 - [8:8] - read-only - - - SM3_TXNFULL - [7:7] - read-only - - - SM2_TXNFULL - [6:6] - read-only - - - SM1_TXNFULL - [5:5] - read-only - - - SM0_TXNFULL - [4:4] - read-only - - - SM3_RXNEMPTY - [3:3] - read-only - - - SM2_RXNEMPTY - [2:2] - read-only - - - SM1_RXNEMPTY - [1:1] - read-only - - - SM0_RXNEMPTY - [0:0] - read-only - - - - - IRQ1_INTE - 0x00000138 - Interrupt Enable for irq1 - 0x00000000 - - - SM3 - [11:11] - read-write - - - SM2 - [10:10] - read-write - - - SM1 - [9:9] - read-write - - - SM0 - [8:8] - read-write - - - SM3_TXNFULL - [7:7] - read-write - - - SM2_TXNFULL - [6:6] - read-write - - - SM1_TXNFULL - [5:5] - read-write - - - SM0_TXNFULL - [4:4] - read-write - - - SM3_RXNEMPTY - [3:3] - read-write - - - SM2_RXNEMPTY - [2:2] - read-write - - - SM1_RXNEMPTY - [1:1] - read-write - - - SM0_RXNEMPTY - [0:0] - read-write - - - - - IRQ1_INTF - 0x0000013c - Interrupt Force for irq1 - 0x00000000 - - - SM3 - [11:11] - read-write - - - SM2 - [10:10] - read-write - - - SM1 - [9:9] - read-write - - - SM0 - [8:8] - read-write - - - SM3_TXNFULL - [7:7] - read-write - - - SM2_TXNFULL - [6:6] - read-write - - - SM1_TXNFULL - [5:5] - read-write - - - SM0_TXNFULL - [4:4] - read-write - - - SM3_RXNEMPTY - [3:3] - read-write - - - SM2_RXNEMPTY - [2:2] - read-write - - - SM1_RXNEMPTY - [1:1] - read-write - - - SM0_RXNEMPTY - [0:0] - read-write - - - - - IRQ1_INTS - 0x00000140 - Interrupt status after masking & forcing for irq1 - 0x00000000 - - - SM3 - [11:11] - read-only - - - SM2 - [10:10] - read-only - - - SM1 - [9:9] - read-only - - - SM0 - [8:8] - read-only - - - SM3_TXNFULL - [7:7] - read-only - - - SM2_TXNFULL - [6:6] - read-only - - - SM1_TXNFULL - [5:5] - read-only - - - SM0_TXNFULL - [4:4] - read-only - - - SM3_RXNEMPTY - [3:3] - read-only - - - SM2_RXNEMPTY - [2:2] - read-only - - - SM1_RXNEMPTY - [1:1] - read-only - - - SM0_RXNEMPTY - [0:0] - read-only - - - - - - - PIO1 - 0x50300000 - - PIO1_IRQ_0 - 9 - - - PIO1_IRQ_1 - 10 - - - - BUSCTRL - Register block for busfabric control signals and performance counters - 0x40030000 - - 0 - 40 - registers - - - - BUS_PRIORITY - 0x00000000 - Set the priority of each master for bus arbitration. - 0x00000000 - - - DMA_W - 0 - low priority, 1 - high priority - [12:12] - read-write - - - DMA_R - 0 - low priority, 1 - high priority - [8:8] - read-write - - - PROC1 - 0 - low priority, 1 - high priority - [4:4] - read-write - - - PROC0 - 0 - low priority, 1 - high priority - [0:0] - read-write - - - - - BUS_PRIORITY_ACK - 0x00000004 - Bus priority acknowledge - 0x00000000 - - - BUS_PRIORITY_ACK - Goes to 1 once all arbiters have registered the new global priority levels. - Arbiters update their local priority when servicing a new nonsequential access. - In normal circumstances this will happen almost immediately. - [0:0] - read-only - - - - - PERFCTR0 - 0x00000008 - Bus fabric performance counter 0 - 0x00000000 - - - PERFCTR0 - Busfabric saturating performance counter 0 - Count some event signal from the busfabric arbiters. - Write any value to clear. Select an event to count using PERFSEL0 - [23:0] - read-write - oneToClear - - - - - PERFSEL0 - 0x0000000c - Bus fabric performance event select for PERFCTR0 - 0x0000001f - - - PERFSEL0 - Select an event for PERFCTR0. Count either contested accesses, or all accesses, on a downstream port of the main crossbar. - [4:0] - read-write - - - apb_contested - 0 - - - apb - 1 - - - fastperi_contested - 2 - - - fastperi - 3 - - - sram5_contested - 4 - - - sram5 - 5 - - - sram4_contested - 6 - - - sram4 - 7 - - - sram3_contested - 8 - - - sram3 - 9 - - - sram2_contested - 10 - - - sram2 - 11 - - - sram1_contested - 12 - - - sram1 - 13 - - - sram0_contested - 14 - - - sram0 - 15 - - - xip_main_contested - 16 - - - xip_main - 17 - - - rom_contested - 18 - - - rom - 19 - - - - - - - PERFCTR1 - 0x00000010 - Bus fabric performance counter 1 - 0x00000000 - - - PERFCTR1 - Busfabric saturating performance counter 1 - Count some event signal from the busfabric arbiters. - Write any value to clear. Select an event to count using PERFSEL1 - [23:0] - read-write - oneToClear - - - - - PERFSEL1 - 0x00000014 - Bus fabric performance event select for PERFCTR1 - 0x0000001f - - - PERFSEL1 - Select an event for PERFCTR1. Count either contested accesses, or all accesses, on a downstream port of the main crossbar. - [4:0] - read-write - - - apb_contested - 0 - - - apb - 1 - - - fastperi_contested - 2 - - - fastperi - 3 - - - sram5_contested - 4 - - - sram5 - 5 - - - sram4_contested - 6 - - - sram4 - 7 - - - sram3_contested - 8 - - - sram3 - 9 - - - sram2_contested - 10 - - - sram2 - 11 - - - sram1_contested - 12 - - - sram1 - 13 - - - sram0_contested - 14 - - - sram0 - 15 - - - xip_main_contested - 16 - - - xip_main - 17 - - - rom_contested - 18 - - - rom - 19 - - - - - - - PERFCTR2 - 0x00000018 - Bus fabric performance counter 2 - 0x00000000 - - - PERFCTR2 - Busfabric saturating performance counter 2 - Count some event signal from the busfabric arbiters. - Write any value to clear. Select an event to count using PERFSEL2 - [23:0] - read-write - oneToClear - - - - - PERFSEL2 - 0x0000001c - Bus fabric performance event select for PERFCTR2 - 0x0000001f - - - PERFSEL2 - Select an event for PERFCTR2. Count either contested accesses, or all accesses, on a downstream port of the main crossbar. - [4:0] - read-write - - - apb_contested - 0 - - - apb - 1 - - - fastperi_contested - 2 - - - fastperi - 3 - - - sram5_contested - 4 - - - sram5 - 5 - - - sram4_contested - 6 - - - sram4 - 7 - - - sram3_contested - 8 - - - sram3 - 9 - - - sram2_contested - 10 - - - sram2 - 11 - - - sram1_contested - 12 - - - sram1 - 13 - - - sram0_contested - 14 - - - sram0 - 15 - - - xip_main_contested - 16 - - - xip_main - 17 - - - rom_contested - 18 - - - rom - 19 - - - - - - - PERFCTR3 - 0x00000020 - Bus fabric performance counter 3 - 0x00000000 - - - PERFCTR3 - Busfabric saturating performance counter 3 - Count some event signal from the busfabric arbiters. - Write any value to clear. Select an event to count using PERFSEL3 - [23:0] - read-write - oneToClear - - - - - PERFSEL3 - 0x00000024 - Bus fabric performance event select for PERFCTR3 - 0x0000001f - - - PERFSEL3 - Select an event for PERFCTR3. Count either contested accesses, or all accesses, on a downstream port of the main crossbar. - [4:0] - read-write - - - apb_contested - 0 - - - apb - 1 - - - fastperi_contested - 2 - - - fastperi - 3 - - - sram5_contested - 4 - - - sram5 - 5 - - - sram4_contested - 6 - - - sram4 - 7 - - - sram3_contested - 8 - - - sram3 - 9 - - - sram2_contested - 10 - - - sram2 - 11 - - - sram1_contested - 12 - - - sram1 - 13 - - - sram0_contested - 14 - - - sram0 - 15 - - - xip_main_contested - 16 - - - xip_main - 17 - - - rom_contested - 18 - - - rom - 19 - - - - - - - - - SIO - Single-cycle IO block - Provides core-local and inter-core hardware for the two processors, with single-cycle access. - 0xd0000000 - - 0 - 384 - registers - - - SIO_IRQ_PROC0 - 15 - - - SIO_IRQ_PROC1 - 16 - - - - CPUID - 0x00000000 - Processor core identifier - 0x00000000 - - - CPUID - Value is 0 when read from processor core 0, and 1 when read from processor core 1. - [31:0] - read-only - - - - - GPIO_IN - 0x00000004 - Input value for GPIO pins - 0x00000000 - - - GPIO_IN - Input value for GPIO0...29 - [29:0] - read-only - - - - - GPIO_HI_IN - 0x00000008 - Input value for QSPI pins - 0x00000000 - - - GPIO_HI_IN - Input value on QSPI IO in order 0..5: SCLK, SSn, SD0, SD1, SD2, SD3 - [5:0] - read-only - - - - - GPIO_OUT - 0x00000010 - GPIO output value - 0x00000000 - - - GPIO_OUT - Set output level (1/0 -> high/low) for GPIO0...29. - Reading back gives the last value written, NOT the input value from the pins. - If core 0 and core 1 both write to GPIO_OUT simultaneously (or to a SET/CLR/XOR alias), - the result is as though the write from core 0 took place first, - and the write from core 1 was then applied to that intermediate result. - [29:0] - read-write - - - - - GPIO_OUT_SET - 0x00000014 - GPIO output value set - 0x00000000 - - - GPIO_OUT_SET - Perform an atomic bit-set on GPIO_OUT, i.e. `GPIO_OUT |= wdata` - [29:0] - write-only - - - - - GPIO_OUT_CLR - 0x00000018 - GPIO output value clear - 0x00000000 - - - GPIO_OUT_CLR - Perform an atomic bit-clear on GPIO_OUT, i.e. `GPIO_OUT &= ~wdata` - [29:0] - write-only - - - - - GPIO_OUT_XOR - 0x0000001c - GPIO output value XOR - 0x00000000 - - - GPIO_OUT_XOR - Perform an atomic bitwise XOR on GPIO_OUT, i.e. `GPIO_OUT ^= wdata` - [29:0] - write-only - - - - - GPIO_OE - 0x00000020 - GPIO output enable - 0x00000000 - - - GPIO_OE - Set output enable (1/0 -> output/input) for GPIO0...29. - Reading back gives the last value written. - If core 0 and core 1 both write to GPIO_OE simultaneously (or to a SET/CLR/XOR alias), - the result is as though the write from core 0 took place first, - and the write from core 1 was then applied to that intermediate result. - [29:0] - read-write - - - - - GPIO_OE_SET - 0x00000024 - GPIO output enable set - 0x00000000 - - - GPIO_OE_SET - Perform an atomic bit-set on GPIO_OE, i.e. `GPIO_OE |= wdata` - [29:0] - write-only - - - - - GPIO_OE_CLR - 0x00000028 - GPIO output enable clear - 0x00000000 - - - GPIO_OE_CLR - Perform an atomic bit-clear on GPIO_OE, i.e. `GPIO_OE &= ~wdata` - [29:0] - write-only - - - - - GPIO_OE_XOR - 0x0000002c - GPIO output enable XOR - 0x00000000 - - - GPIO_OE_XOR - Perform an atomic bitwise XOR on GPIO_OE, i.e. `GPIO_OE ^= wdata` - [29:0] - write-only - - - - - GPIO_HI_OUT - 0x00000030 - QSPI output value - 0x00000000 - - - GPIO_HI_OUT - Set output level (1/0 -> high/low) for QSPI IO0...5. - Reading back gives the last value written, NOT the input value from the pins. - If core 0 and core 1 both write to GPIO_HI_OUT simultaneously (or to a SET/CLR/XOR alias), - the result is as though the write from core 0 took place first, - and the write from core 1 was then applied to that intermediate result. - [5:0] - read-write - - - - - GPIO_HI_OUT_SET - 0x00000034 - QSPI output value set - 0x00000000 - - - GPIO_HI_OUT_SET - Perform an atomic bit-set on GPIO_HI_OUT, i.e. `GPIO_HI_OUT |= wdata` - [5:0] - write-only - - - - - GPIO_HI_OUT_CLR - 0x00000038 - QSPI output value clear - 0x00000000 - - - GPIO_HI_OUT_CLR - Perform an atomic bit-clear on GPIO_HI_OUT, i.e. `GPIO_HI_OUT &= ~wdata` - [5:0] - write-only - - - - - GPIO_HI_OUT_XOR - 0x0000003c - QSPI output value XOR - 0x00000000 - - - GPIO_HI_OUT_XOR - Perform an atomic bitwise XOR on GPIO_HI_OUT, i.e. `GPIO_HI_OUT ^= wdata` - [5:0] - write-only - - - - - GPIO_HI_OE - 0x00000040 - QSPI output enable - 0x00000000 - - - GPIO_HI_OE - Set output enable (1/0 -> output/input) for QSPI IO0...5. - Reading back gives the last value written. - If core 0 and core 1 both write to GPIO_HI_OE simultaneously (or to a SET/CLR/XOR alias), - the result is as though the write from core 0 took place first, - and the write from core 1 was then applied to that intermediate result. - [5:0] - read-write - - - - - GPIO_HI_OE_SET - 0x00000044 - QSPI output enable set - 0x00000000 - - - GPIO_HI_OE_SET - Perform an atomic bit-set on GPIO_HI_OE, i.e. `GPIO_HI_OE |= wdata` - [5:0] - write-only - - - - - GPIO_HI_OE_CLR - 0x00000048 - QSPI output enable clear - 0x00000000 - - - GPIO_HI_OE_CLR - Perform an atomic bit-clear on GPIO_HI_OE, i.e. `GPIO_HI_OE &= ~wdata` - [5:0] - write-only - - - - - GPIO_HI_OE_XOR - 0x0000004c - QSPI output enable XOR - 0x00000000 - - - GPIO_HI_OE_XOR - Perform an atomic bitwise XOR on GPIO_HI_OE, i.e. `GPIO_HI_OE ^= wdata` - [5:0] - write-only - - - - - FIFO_ST - 0x00000050 - Status register for inter-core FIFOs (mailboxes). - There is one FIFO in the core 0 -> core 1 direction, and one core 1 -> core 0. Both are 32 bits wide and 8 words deep. - Core 0 can see the read side of the 1->0 FIFO (RX), and the write side of 0->1 FIFO (TX). - Core 1 can see the read side of the 0->1 FIFO (RX), and the write side of 1->0 FIFO (TX). - The SIO IRQ for each core is the logical OR of the VLD, WOF and ROE fields of its FIFO_ST register. - 0x00000002 - - - ROE - Sticky flag indicating the RX FIFO was read when empty. This read was ignored by the FIFO. - [3:3] - read-write - oneToClear - - - WOF - Sticky flag indicating the TX FIFO was written when full. This write was ignored by the FIFO. - [2:2] - read-write - oneToClear - - - RDY - Value is 1 if this core's TX FIFO is not full (i.e. if FIFO_WR is ready for more data) - [1:1] - read-only - - - VLD - Value is 1 if this core's RX FIFO is not empty (i.e. if FIFO_RD is valid) - [0:0] - read-only - - - - - FIFO_WR - 0x00000054 - Write access to this core's TX FIFO - 0x00000000 - - - FIFO_WR - [31:0] - write-only - - - - - FIFO_RD - 0x00000058 - Read access to this core's RX FIFO - 0x00000000 - - - FIFO_RD - [31:0] - read-only - modify - - - - - SPINLOCK_ST - 0x0000005c - Spinlock state - A bitmap containing the state of all 32 spinlocks (1=locked). - Mainly intended for debugging. - 0x00000000 - - - SPINLOCK_ST - [31:0] - read-only - - - - - DIV_UDIVIDEND - 0x00000060 - Divider unsigned dividend - Write to the DIVIDEND operand of the divider, i.e. the p in `p / q`. - Any operand write starts a new calculation. The results appear in QUOTIENT, REMAINDER. - UDIVIDEND/SDIVIDEND are aliases of the same internal register. The U alias starts an - unsigned calculation, and the S alias starts a signed calculation. - 0x00000000 - - - DIV_UDIVIDEND - [31:0] - read-write - - - - - DIV_UDIVISOR - 0x00000064 - Divider unsigned divisor - Write to the DIVISOR operand of the divider, i.e. the q in `p / q`. - Any operand write starts a new calculation. The results appear in QUOTIENT, REMAINDER. - UDIVISOR/SDIVISOR are aliases of the same internal register. The U alias starts an - unsigned calculation, and the S alias starts a signed calculation. - 0x00000000 - - - DIV_UDIVISOR - [31:0] - read-write - - - - - DIV_SDIVIDEND - 0x00000068 - Divider signed dividend - The same as UDIVIDEND, but starts a signed calculation, rather than unsigned. - 0x00000000 - - - DIV_SDIVIDEND - [31:0] - read-write - - - - - DIV_SDIVISOR - 0x0000006c - Divider signed divisor - The same as UDIVISOR, but starts a signed calculation, rather than unsigned. - 0x00000000 - - - DIV_SDIVISOR - [31:0] - read-write - - - - - DIV_QUOTIENT - 0x00000070 - Divider result quotient - The result of `DIVIDEND / DIVISOR` (division). Contents undefined while CSR_READY is low. - For signed calculations, QUOTIENT is negative when the signs of DIVIDEND and DIVISOR differ. - This register can be written to directly, for context save/restore purposes. This halts any - in-progress calculation and sets the CSR_READY and CSR_DIRTY flags. - Reading from QUOTIENT clears the CSR_DIRTY flag, so should read results in the order - REMAINDER, QUOTIENT if CSR_DIRTY is used. - 0x00000000 - - - DIV_QUOTIENT - [31:0] - read-write - - - - - DIV_REMAINDER - 0x00000074 - Divider result remainder - The result of `DIVIDEND % DIVISOR` (modulo). Contents undefined while CSR_READY is low. - For signed calculations, REMAINDER is negative only when DIVIDEND is negative. - This register can be written to directly, for context save/restore purposes. This halts any - in-progress calculation and sets the CSR_READY and CSR_DIRTY flags. - 0x00000000 - - - DIV_REMAINDER - [31:0] - read-write - - - - - DIV_CSR - 0x00000078 - Control and status register for divider. - 0x00000001 - - - DIRTY - Changes to 1 when any register is written, and back to 0 when QUOTIENT is read. - Software can use this flag to make save/restore more efficient (skip if not DIRTY). - If the flag is used in this way, it's recommended to either read QUOTIENT only, - or REMAINDER and then QUOTIENT, to prevent data loss on context switch. - [1:1] - read-only - - - READY - Reads as 0 when a calculation is in progress, 1 otherwise. - Writing an operand (xDIVIDEND, xDIVISOR) will immediately start a new calculation, no - matter if one is already in progress. - Writing to a result register will immediately terminate any in-progress calculation - and set the READY and DIRTY flags. - [0:0] - read-only - - - - - INTERP0_ACCUM0 - 0x00000080 - Read/write access to accumulator 0 - 0x00000000 - - - INTERP0_ACCUM0 - [31:0] - read-write - - - - - INTERP0_ACCUM1 - 0x00000084 - Read/write access to accumulator 1 - 0x00000000 - - - INTERP0_ACCUM1 - [31:0] - read-write - - - - - INTERP0_BASE0 - 0x00000088 - Read/write access to BASE0 register. - 0x00000000 - - - INTERP0_BASE0 - [31:0] - read-write - - - - - INTERP0_BASE1 - 0x0000008c - Read/write access to BASE1 register. - 0x00000000 - - - INTERP0_BASE1 - [31:0] - read-write - - - - - INTERP0_BASE2 - 0x00000090 - Read/write access to BASE2 register. - 0x00000000 - - - INTERP0_BASE2 - [31:0] - read-write - - - - - INTERP0_POP_LANE0 - 0x00000094 - Read LANE0 result, and simultaneously write lane results to both accumulators (POP). - 0x00000000 - - - INTERP0_POP_LANE0 - [31:0] - read-only - - - - - INTERP0_POP_LANE1 - 0x00000098 - Read LANE1 result, and simultaneously write lane results to both accumulators (POP). - 0x00000000 - - - INTERP0_POP_LANE1 - [31:0] - read-only - - - - - INTERP0_POP_FULL - 0x0000009c - Read FULL result, and simultaneously write lane results to both accumulators (POP). - 0x00000000 - - - INTERP0_POP_FULL - [31:0] - read-only - - - - - INTERP0_PEEK_LANE0 - 0x000000a0 - Read LANE0 result, without altering any internal state (PEEK). - 0x00000000 - - - INTERP0_PEEK_LANE0 - [31:0] - read-only - - - - - INTERP0_PEEK_LANE1 - 0x000000a4 - Read LANE1 result, without altering any internal state (PEEK). - 0x00000000 - - - INTERP0_PEEK_LANE1 - [31:0] - read-only - - - - - INTERP0_PEEK_FULL - 0x000000a8 - Read FULL result, without altering any internal state (PEEK). - 0x00000000 - - - INTERP0_PEEK_FULL - [31:0] - read-only - - - - - INTERP0_CTRL_LANE0 - 0x000000ac - Control register for lane 0 - 0x00000000 - - - OVERF - Set if either OVERF0 or OVERF1 is set. - [25:25] - read-only - - - OVERF1 - Indicates if any masked-off MSBs in ACCUM1 are set. - [24:24] - read-only - - - OVERF0 - Indicates if any masked-off MSBs in ACCUM0 are set. - [23:23] - read-only - - - BLEND - Only present on INTERP0 on each core. If BLEND mode is enabled: - - LANE1 result is a linear interpolation between BASE0 and BASE1, controlled - by the 8 LSBs of lane 1 shift and mask value (a fractional number between - 0 and 255/256ths) - - LANE0 result does not have BASE0 added (yields only the 8 LSBs of lane 1 shift+mask value) - - FULL result does not have lane 1 shift+mask value added (BASE2 + lane 0 shift+mask) - LANE1 SIGNED flag controls whether the interpolation is signed or unsigned. - [21:21] - read-write - - - FORCE_MSB - ORed into bits 29:28 of the lane result presented to the processor on the bus. - No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence - of pointers into flash or SRAM. - [20:19] - read-write - - - ADD_RAW - If 1, mask + shift is bypassed for LANE0 result. This does not affect FULL result. - [18:18] - read-write - - - CROSS_RESULT - If 1, feed the opposite lane's result into this lane's accumulator on POP. - [17:17] - read-write - - - CROSS_INPUT - If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. - Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass) - [16:16] - read-write - - - SIGNED - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits - before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor. - [15:15] - read-write - - - MASK_MSB - The most-significant bit allowed to pass by the mask (inclusive) - Setting MSB < LSB may cause chip to turn inside-out - [14:10] - read-write - - - MASK_LSB - The least-significant bit allowed to pass by the mask (inclusive) - [9:5] - read-write - - - SHIFT - Logical right-shift applied to accumulator before masking - [4:0] - read-write - - - - - INTERP0_CTRL_LANE1 - 0x000000b0 - Control register for lane 1 - 0x00000000 - - - FORCE_MSB - ORed into bits 29:28 of the lane result presented to the processor on the bus. - No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence - of pointers into flash or SRAM. - [20:19] - read-write - - - ADD_RAW - If 1, mask + shift is bypassed for LANE1 result. This does not affect FULL result. - [18:18] - read-write - - - CROSS_RESULT - If 1, feed the opposite lane's result into this lane's accumulator on POP. - [17:17] - read-write - - - CROSS_INPUT - If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. - Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass) - [16:16] - read-write - - - SIGNED - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits - before adding to BASE1, and LANE1 PEEK/POP appear extended to 32 bits when read by processor. - [15:15] - read-write - - - MASK_MSB - The most-significant bit allowed to pass by the mask (inclusive) - Setting MSB < LSB may cause chip to turn inside-out - [14:10] - read-write - - - MASK_LSB - The least-significant bit allowed to pass by the mask (inclusive) - [9:5] - read-write - - - SHIFT - Logical right-shift applied to accumulator before masking - [4:0] - read-write - - - - - INTERP0_ACCUM0_ADD - 0x000000b4 - Values written here are atomically added to ACCUM0 - Reading yields lane 0's raw shift and mask value (BASE0 not added). - 0x00000000 - - - INTERP0_ACCUM0_ADD - [23:0] - read-write - - - - - INTERP0_ACCUM1_ADD - 0x000000b8 - Values written here are atomically added to ACCUM1 - Reading yields lane 1's raw shift and mask value (BASE1 not added). - 0x00000000 - - - INTERP0_ACCUM1_ADD - [23:0] - read-write - - - - - INTERP0_BASE_1AND0 - 0x000000bc - On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously. - Each half is sign-extended to 32 bits if that lane's SIGNED flag is set. - 0x00000000 - - - INTERP0_BASE_1AND0 - [31:0] - write-only - - - - - INTERP1_ACCUM0 - 0x000000c0 - Read/write access to accumulator 0 - 0x00000000 - - - INTERP1_ACCUM0 - [31:0] - read-write - - - - - INTERP1_ACCUM1 - 0x000000c4 - Read/write access to accumulator 1 - 0x00000000 - - - INTERP1_ACCUM1 - [31:0] - read-write - - - - - INTERP1_BASE0 - 0x000000c8 - Read/write access to BASE0 register. - 0x00000000 - - - INTERP1_BASE0 - [31:0] - read-write - - - - - INTERP1_BASE1 - 0x000000cc - Read/write access to BASE1 register. - 0x00000000 - - - INTERP1_BASE1 - [31:0] - read-write - - - - - INTERP1_BASE2 - 0x000000d0 - Read/write access to BASE2 register. - 0x00000000 - - - INTERP1_BASE2 - [31:0] - read-write - - - - - INTERP1_POP_LANE0 - 0x000000d4 - Read LANE0 result, and simultaneously write lane results to both accumulators (POP). - 0x00000000 - - - INTERP1_POP_LANE0 - [31:0] - read-only - - - - - INTERP1_POP_LANE1 - 0x000000d8 - Read LANE1 result, and simultaneously write lane results to both accumulators (POP). - 0x00000000 - - - INTERP1_POP_LANE1 - [31:0] - read-only - - - - - INTERP1_POP_FULL - 0x000000dc - Read FULL result, and simultaneously write lane results to both accumulators (POP). - 0x00000000 - - - INTERP1_POP_FULL - [31:0] - read-only - - - - - INTERP1_PEEK_LANE0 - 0x000000e0 - Read LANE0 result, without altering any internal state (PEEK). - 0x00000000 - - - INTERP1_PEEK_LANE0 - [31:0] - read-only - - - - - INTERP1_PEEK_LANE1 - 0x000000e4 - Read LANE1 result, without altering any internal state (PEEK). - 0x00000000 - - - INTERP1_PEEK_LANE1 - [31:0] - read-only - - - - - INTERP1_PEEK_FULL - 0x000000e8 - Read FULL result, without altering any internal state (PEEK). - 0x00000000 - - - INTERP1_PEEK_FULL - [31:0] - read-only - - - - - INTERP1_CTRL_LANE0 - 0x000000ec - Control register for lane 0 - 0x00000000 - - - OVERF - Set if either OVERF0 or OVERF1 is set. - [25:25] - read-only - - - OVERF1 - Indicates if any masked-off MSBs in ACCUM1 are set. - [24:24] - read-only - - - OVERF0 - Indicates if any masked-off MSBs in ACCUM0 are set. - [23:23] - read-only - - - CLAMP - Only present on INTERP1 on each core. If CLAMP mode is enabled: - - LANE0 result is shifted and masked ACCUM0, clamped by a lower bound of - BASE0 and an upper bound of BASE1. - - Signedness of these comparisons is determined by LANE0_CTRL_SIGNED - [22:22] - read-write - - - FORCE_MSB - ORed into bits 29:28 of the lane result presented to the processor on the bus. - No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence - of pointers into flash or SRAM. - [20:19] - read-write - - - ADD_RAW - If 1, mask + shift is bypassed for LANE0 result. This does not affect FULL result. - [18:18] - read-write - - - CROSS_RESULT - If 1, feed the opposite lane's result into this lane's accumulator on POP. - [17:17] - read-write - - - CROSS_INPUT - If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. - Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass) - [16:16] - read-write - - - SIGNED - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits - before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor. - [15:15] - read-write - - - MASK_MSB - The most-significant bit allowed to pass by the mask (inclusive) - Setting MSB < LSB may cause chip to turn inside-out - [14:10] - read-write - - - MASK_LSB - The least-significant bit allowed to pass by the mask (inclusive) - [9:5] - read-write - - - SHIFT - Logical right-shift applied to accumulator before masking - [4:0] - read-write - - - - - INTERP1_CTRL_LANE1 - 0x000000f0 - Control register for lane 1 - 0x00000000 - - - FORCE_MSB - ORed into bits 29:28 of the lane result presented to the processor on the bus. - No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence - of pointers into flash or SRAM. - [20:19] - read-write - - - ADD_RAW - If 1, mask + shift is bypassed for LANE1 result. This does not affect FULL result. - [18:18] - read-write - - - CROSS_RESULT - If 1, feed the opposite lane's result into this lane's accumulator on POP. - [17:17] - read-write - - - CROSS_INPUT - If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. - Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass) - [16:16] - read-write - - - SIGNED - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits - before adding to BASE1, and LANE1 PEEK/POP appear extended to 32 bits when read by processor. - [15:15] - read-write - - - MASK_MSB - The most-significant bit allowed to pass by the mask (inclusive) - Setting MSB < LSB may cause chip to turn inside-out - [14:10] - read-write - - - MASK_LSB - The least-significant bit allowed to pass by the mask (inclusive) - [9:5] - read-write - - - SHIFT - Logical right-shift applied to accumulator before masking - [4:0] - read-write - - - - - INTERP1_ACCUM0_ADD - 0x000000f4 - Values written here are atomically added to ACCUM0 - Reading yields lane 0's raw shift and mask value (BASE0 not added). - 0x00000000 - - - INTERP1_ACCUM0_ADD - [23:0] - read-write - - - - - INTERP1_ACCUM1_ADD - 0x000000f8 - Values written here are atomically added to ACCUM1 - Reading yields lane 1's raw shift and mask value (BASE1 not added). - 0x00000000 - - - INTERP1_ACCUM1_ADD - [23:0] - read-write - - - - - INTERP1_BASE_1AND0 - 0x000000fc - On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously. - Each half is sign-extended to 32 bits if that lane's SIGNED flag is set. - 0x00000000 - - - INTERP1_BASE_1AND0 - [31:0] - write-only - - - - - SPINLOCK0 - 0x00000100 - Reading from a spinlock address will: - - Return 0 if lock is already locked - - Otherwise return nonzero, and simultaneously claim the lock - - Writing (any value) releases the lock. - If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. - The value returned on success is 0x1 << lock number. - 0x00000000 - - - SPINLOCK0 - [31:0] - read-write - modify - - - - - SPINLOCK1 - 0x00000104 - Reading from a spinlock address will: - - Return 0 if lock is already locked - - Otherwise return nonzero, and simultaneously claim the lock - - Writing (any value) releases the lock. - If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. - The value returned on success is 0x1 << lock number. - 0x00000000 - - - SPINLOCK1 - [31:0] - read-write - modify - - - - - SPINLOCK2 - 0x00000108 - Reading from a spinlock address will: - - Return 0 if lock is already locked - - Otherwise return nonzero, and simultaneously claim the lock - - Writing (any value) releases the lock. - If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. - The value returned on success is 0x1 << lock number. - 0x00000000 - - - SPINLOCK2 - [31:0] - read-write - modify - - - - - SPINLOCK3 - 0x0000010c - Reading from a spinlock address will: - - Return 0 if lock is already locked - - Otherwise return nonzero, and simultaneously claim the lock - - Writing (any value) releases the lock. - If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. - The value returned on success is 0x1 << lock number. - 0x00000000 - - - SPINLOCK3 - [31:0] - read-write - modify - - - - - SPINLOCK4 - 0x00000110 - Reading from a spinlock address will: - - Return 0 if lock is already locked - - Otherwise return nonzero, and simultaneously claim the lock - - Writing (any value) releases the lock. - If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. - The value returned on success is 0x1 << lock number. - 0x00000000 - - - SPINLOCK4 - [31:0] - read-write - modify - - - - - SPINLOCK5 - 0x00000114 - Reading from a spinlock address will: - - Return 0 if lock is already locked - - Otherwise return nonzero, and simultaneously claim the lock - - Writing (any value) releases the lock. - If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. - The value returned on success is 0x1 << lock number. - 0x00000000 - - - SPINLOCK5 - [31:0] - read-write - modify - - - - - SPINLOCK6 - 0x00000118 - Reading from a spinlock address will: - - Return 0 if lock is already locked - - Otherwise return nonzero, and simultaneously claim the lock - - Writing (any value) releases the lock. - If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. - The value returned on success is 0x1 << lock number. - 0x00000000 - - - SPINLOCK6 - [31:0] - read-write - modify - - - - - SPINLOCK7 - 0x0000011c - Reading from a spinlock address will: - - Return 0 if lock is already locked - - Otherwise return nonzero, and simultaneously claim the lock - - Writing (any value) releases the lock. - If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. - The value returned on success is 0x1 << lock number. - 0x00000000 - - - SPINLOCK7 - [31:0] - read-write - modify - - - - - SPINLOCK8 - 0x00000120 - Reading from a spinlock address will: - - Return 0 if lock is already locked - - Otherwise return nonzero, and simultaneously claim the lock - - Writing (any value) releases the lock. - If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. - The value returned on success is 0x1 << lock number. - 0x00000000 - - - SPINLOCK8 - [31:0] - read-write - modify - - - - - SPINLOCK9 - 0x00000124 - Reading from a spinlock address will: - - Return 0 if lock is already locked - - Otherwise return nonzero, and simultaneously claim the lock - - Writing (any value) releases the lock. - If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. - The value returned on success is 0x1 << lock number. - 0x00000000 - - - SPINLOCK9 - [31:0] - read-write - modify - - - - - SPINLOCK10 - 0x00000128 - Reading from a spinlock address will: - - Return 0 if lock is already locked - - Otherwise return nonzero, and simultaneously claim the lock - - Writing (any value) releases the lock. - If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. - The value returned on success is 0x1 << lock number. - 0x00000000 - - - SPINLOCK10 - [31:0] - read-write - modify - - - - - SPINLOCK11 - 0x0000012c - Reading from a spinlock address will: - - Return 0 if lock is already locked - - Otherwise return nonzero, and simultaneously claim the lock - - Writing (any value) releases the lock. - If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. - The value returned on success is 0x1 << lock number. - 0x00000000 - - - SPINLOCK11 - [31:0] - read-write - modify - - - - - SPINLOCK12 - 0x00000130 - Reading from a spinlock address will: - - Return 0 if lock is already locked - - Otherwise return nonzero, and simultaneously claim the lock - - Writing (any value) releases the lock. - If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. - The value returned on success is 0x1 << lock number. - 0x00000000 - - - SPINLOCK12 - [31:0] - read-write - modify - - - - - SPINLOCK13 - 0x00000134 - Reading from a spinlock address will: - - Return 0 if lock is already locked - - Otherwise return nonzero, and simultaneously claim the lock - - Writing (any value) releases the lock. - If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. - The value returned on success is 0x1 << lock number. - 0x00000000 - - - SPINLOCK13 - [31:0] - read-write - modify - - - - - SPINLOCK14 - 0x00000138 - Reading from a spinlock address will: - - Return 0 if lock is already locked - - Otherwise return nonzero, and simultaneously claim the lock - - Writing (any value) releases the lock. - If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. - The value returned on success is 0x1 << lock number. - 0x00000000 - - - SPINLOCK14 - [31:0] - read-write - modify - - - - - SPINLOCK15 - 0x0000013c - Reading from a spinlock address will: - - Return 0 if lock is already locked - - Otherwise return nonzero, and simultaneously claim the lock - - Writing (any value) releases the lock. - If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. - The value returned on success is 0x1 << lock number. - 0x00000000 - - - SPINLOCK15 - [31:0] - read-write - modify - - - - - SPINLOCK16 - 0x00000140 - Reading from a spinlock address will: - - Return 0 if lock is already locked - - Otherwise return nonzero, and simultaneously claim the lock - - Writing (any value) releases the lock. - If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. - The value returned on success is 0x1 << lock number. - 0x00000000 - - - SPINLOCK16 - [31:0] - read-write - modify - - - - - SPINLOCK17 - 0x00000144 - Reading from a spinlock address will: - - Return 0 if lock is already locked - - Otherwise return nonzero, and simultaneously claim the lock - - Writing (any value) releases the lock. - If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. - The value returned on success is 0x1 << lock number. - 0x00000000 - - - SPINLOCK17 - [31:0] - read-write - modify - - - - - SPINLOCK18 - 0x00000148 - Reading from a spinlock address will: - - Return 0 if lock is already locked - - Otherwise return nonzero, and simultaneously claim the lock - - Writing (any value) releases the lock. - If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. - The value returned on success is 0x1 << lock number. - 0x00000000 - - - SPINLOCK18 - [31:0] - read-write - modify - - - - - SPINLOCK19 - 0x0000014c - Reading from a spinlock address will: - - Return 0 if lock is already locked - - Otherwise return nonzero, and simultaneously claim the lock - - Writing (any value) releases the lock. - If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. - The value returned on success is 0x1 << lock number. - 0x00000000 - - - SPINLOCK19 - [31:0] - read-write - modify - - - - - SPINLOCK20 - 0x00000150 - Reading from a spinlock address will: - - Return 0 if lock is already locked - - Otherwise return nonzero, and simultaneously claim the lock - - Writing (any value) releases the lock. - If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. - The value returned on success is 0x1 << lock number. - 0x00000000 - - - SPINLOCK20 - [31:0] - read-write - modify - - - - - SPINLOCK21 - 0x00000154 - Reading from a spinlock address will: - - Return 0 if lock is already locked - - Otherwise return nonzero, and simultaneously claim the lock - - Writing (any value) releases the lock. - If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. - The value returned on success is 0x1 << lock number. - 0x00000000 - - - SPINLOCK21 - [31:0] - read-write - modify - - - - - SPINLOCK22 - 0x00000158 - Reading from a spinlock address will: - - Return 0 if lock is already locked - - Otherwise return nonzero, and simultaneously claim the lock - - Writing (any value) releases the lock. - If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. - The value returned on success is 0x1 << lock number. - 0x00000000 - - - SPINLOCK22 - [31:0] - read-write - modify - - - - - SPINLOCK23 - 0x0000015c - Reading from a spinlock address will: - - Return 0 if lock is already locked - - Otherwise return nonzero, and simultaneously claim the lock - - Writing (any value) releases the lock. - If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. - The value returned on success is 0x1 << lock number. - 0x00000000 - - - SPINLOCK23 - [31:0] - read-write - modify - - - - - SPINLOCK24 - 0x00000160 - Reading from a spinlock address will: - - Return 0 if lock is already locked - - Otherwise return nonzero, and simultaneously claim the lock - - Writing (any value) releases the lock. - If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. - The value returned on success is 0x1 << lock number. - 0x00000000 - - - SPINLOCK24 - [31:0] - read-write - modify - - - - - SPINLOCK25 - 0x00000164 - Reading from a spinlock address will: - - Return 0 if lock is already locked - - Otherwise return nonzero, and simultaneously claim the lock - - Writing (any value) releases the lock. - If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. - The value returned on success is 0x1 << lock number. - 0x00000000 - - - SPINLOCK25 - [31:0] - read-write - modify - - - - - SPINLOCK26 - 0x00000168 - Reading from a spinlock address will: - - Return 0 if lock is already locked - - Otherwise return nonzero, and simultaneously claim the lock - - Writing (any value) releases the lock. - If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. - The value returned on success is 0x1 << lock number. - 0x00000000 - - - SPINLOCK26 - [31:0] - read-write - modify - - - - - SPINLOCK27 - 0x0000016c - Reading from a spinlock address will: - - Return 0 if lock is already locked - - Otherwise return nonzero, and simultaneously claim the lock - - Writing (any value) releases the lock. - If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. - The value returned on success is 0x1 << lock number. - 0x00000000 - - - SPINLOCK27 - [31:0] - read-write - modify - - - - - SPINLOCK28 - 0x00000170 - Reading from a spinlock address will: - - Return 0 if lock is already locked - - Otherwise return nonzero, and simultaneously claim the lock - - Writing (any value) releases the lock. - If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. - The value returned on success is 0x1 << lock number. - 0x00000000 - - - SPINLOCK28 - [31:0] - read-write - modify - - - - - SPINLOCK29 - 0x00000174 - Reading from a spinlock address will: - - Return 0 if lock is already locked - - Otherwise return nonzero, and simultaneously claim the lock - - Writing (any value) releases the lock. - If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. - The value returned on success is 0x1 << lock number. - 0x00000000 - - - SPINLOCK29 - [31:0] - read-write - modify - - - - - SPINLOCK30 - 0x00000178 - Reading from a spinlock address will: - - Return 0 if lock is already locked - - Otherwise return nonzero, and simultaneously claim the lock - - Writing (any value) releases the lock. - If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. - The value returned on success is 0x1 << lock number. - 0x00000000 - - - SPINLOCK30 - [31:0] - read-write - modify - - - - - SPINLOCK31 - 0x0000017c - Reading from a spinlock address will: - - Return 0 if lock is already locked - - Otherwise return nonzero, and simultaneously claim the lock - - Writing (any value) releases the lock. - If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. - The value returned on success is 0x1 << lock number. - 0x00000000 - - - SPINLOCK31 - [31:0] - read-write - modify - - - - - - - USB - USB FS/LS controller device registers - 0x50110000 - - 0 - 156 - registers - - - USBCTRL_IRQ - 5 - - - - ADDR_ENDP - 0x00000000 - Device address and endpoint control - 0x00000000 - - - ENDPOINT - Device endpoint to send data to. Only valid for HOST mode. - [19:16] - read-write - - - ADDRESS - In device mode, the address that the device should respond to. Set in response to a SET_ADDR setup packet from the host. In host mode set to the address of the device to communicate with. - [6:0] - read-write - - - - - ADDR_ENDP1 - 0x00000004 - Interrupt endpoint 1. Only valid for HOST mode. - 0x00000000 - - - INTEP_PREAMBLE - Interrupt EP requires preamble (is a low speed device on a full speed hub) - [26:26] - read-write - - - INTEP_DIR - Direction of the interrupt endpoint. In=0, Out=1 - [25:25] - read-write - - - ENDPOINT - Endpoint number of the interrupt endpoint - [19:16] - read-write - - - ADDRESS - Device address - [6:0] - read-write - - - - - ADDR_ENDP2 - 0x00000008 - Interrupt endpoint 2. Only valid for HOST mode. - 0x00000000 - - - INTEP_PREAMBLE - Interrupt EP requires preamble (is a low speed device on a full speed hub) - [26:26] - read-write - - - INTEP_DIR - Direction of the interrupt endpoint. In=0, Out=1 - [25:25] - read-write - - - ENDPOINT - Endpoint number of the interrupt endpoint - [19:16] - read-write - - - ADDRESS - Device address - [6:0] - read-write - - - - - ADDR_ENDP3 - 0x0000000c - Interrupt endpoint 3. Only valid for HOST mode. - 0x00000000 - - - INTEP_PREAMBLE - Interrupt EP requires preamble (is a low speed device on a full speed hub) - [26:26] - read-write - - - INTEP_DIR - Direction of the interrupt endpoint. In=0, Out=1 - [25:25] - read-write - - - ENDPOINT - Endpoint number of the interrupt endpoint - [19:16] - read-write - - - ADDRESS - Device address - [6:0] - read-write - - - - - ADDR_ENDP4 - 0x00000010 - Interrupt endpoint 4. Only valid for HOST mode. - 0x00000000 - - - INTEP_PREAMBLE - Interrupt EP requires preamble (is a low speed device on a full speed hub) - [26:26] - read-write - - - INTEP_DIR - Direction of the interrupt endpoint. In=0, Out=1 - [25:25] - read-write - - - ENDPOINT - Endpoint number of the interrupt endpoint - [19:16] - read-write - - - ADDRESS - Device address - [6:0] - read-write - - - - - ADDR_ENDP5 - 0x00000014 - Interrupt endpoint 5. Only valid for HOST mode. - 0x00000000 - - - INTEP_PREAMBLE - Interrupt EP requires preamble (is a low speed device on a full speed hub) - [26:26] - read-write - - - INTEP_DIR - Direction of the interrupt endpoint. In=0, Out=1 - [25:25] - read-write - - - ENDPOINT - Endpoint number of the interrupt endpoint - [19:16] - read-write - - - ADDRESS - Device address - [6:0] - read-write - - - - - ADDR_ENDP6 - 0x00000018 - Interrupt endpoint 6. Only valid for HOST mode. - 0x00000000 - - - INTEP_PREAMBLE - Interrupt EP requires preamble (is a low speed device on a full speed hub) - [26:26] - read-write - - - INTEP_DIR - Direction of the interrupt endpoint. In=0, Out=1 - [25:25] - read-write - - - ENDPOINT - Endpoint number of the interrupt endpoint - [19:16] - read-write - - - ADDRESS - Device address - [6:0] - read-write - - - - - ADDR_ENDP7 - 0x0000001c - Interrupt endpoint 7. Only valid for HOST mode. - 0x00000000 - - - INTEP_PREAMBLE - Interrupt EP requires preamble (is a low speed device on a full speed hub) - [26:26] - read-write - - - INTEP_DIR - Direction of the interrupt endpoint. In=0, Out=1 - [25:25] - read-write - - - ENDPOINT - Endpoint number of the interrupt endpoint - [19:16] - read-write - - - ADDRESS - Device address - [6:0] - read-write - - - - - ADDR_ENDP8 - 0x00000020 - Interrupt endpoint 8. Only valid for HOST mode. - 0x00000000 - - - INTEP_PREAMBLE - Interrupt EP requires preamble (is a low speed device on a full speed hub) - [26:26] - read-write - - - INTEP_DIR - Direction of the interrupt endpoint. In=0, Out=1 - [25:25] - read-write - - - ENDPOINT - Endpoint number of the interrupt endpoint - [19:16] - read-write - - - ADDRESS - Device address - [6:0] - read-write - - - - - ADDR_ENDP9 - 0x00000024 - Interrupt endpoint 9. Only valid for HOST mode. - 0x00000000 - - - INTEP_PREAMBLE - Interrupt EP requires preamble (is a low speed device on a full speed hub) - [26:26] - read-write - - - INTEP_DIR - Direction of the interrupt endpoint. In=0, Out=1 - [25:25] - read-write - - - ENDPOINT - Endpoint number of the interrupt endpoint - [19:16] - read-write - - - ADDRESS - Device address - [6:0] - read-write - - - - - ADDR_ENDP10 - 0x00000028 - Interrupt endpoint 10. Only valid for HOST mode. - 0x00000000 - - - INTEP_PREAMBLE - Interrupt EP requires preamble (is a low speed device on a full speed hub) - [26:26] - read-write - - - INTEP_DIR - Direction of the interrupt endpoint. In=0, Out=1 - [25:25] - read-write - - - ENDPOINT - Endpoint number of the interrupt endpoint - [19:16] - read-write - - - ADDRESS - Device address - [6:0] - read-write - - - - - ADDR_ENDP11 - 0x0000002c - Interrupt endpoint 11. Only valid for HOST mode. - 0x00000000 - - - INTEP_PREAMBLE - Interrupt EP requires preamble (is a low speed device on a full speed hub) - [26:26] - read-write - - - INTEP_DIR - Direction of the interrupt endpoint. In=0, Out=1 - [25:25] - read-write - - - ENDPOINT - Endpoint number of the interrupt endpoint - [19:16] - read-write - - - ADDRESS - Device address - [6:0] - read-write - - - - - ADDR_ENDP12 - 0x00000030 - Interrupt endpoint 12. Only valid for HOST mode. - 0x00000000 - - - INTEP_PREAMBLE - Interrupt EP requires preamble (is a low speed device on a full speed hub) - [26:26] - read-write - - - INTEP_DIR - Direction of the interrupt endpoint. In=0, Out=1 - [25:25] - read-write - - - ENDPOINT - Endpoint number of the interrupt endpoint - [19:16] - read-write - - - ADDRESS - Device address - [6:0] - read-write - - - - - ADDR_ENDP13 - 0x00000034 - Interrupt endpoint 13. Only valid for HOST mode. - 0x00000000 - - - INTEP_PREAMBLE - Interrupt EP requires preamble (is a low speed device on a full speed hub) - [26:26] - read-write - - - INTEP_DIR - Direction of the interrupt endpoint. In=0, Out=1 - [25:25] - read-write - - - ENDPOINT - Endpoint number of the interrupt endpoint - [19:16] - read-write - - - ADDRESS - Device address - [6:0] - read-write - - - - - ADDR_ENDP14 - 0x00000038 - Interrupt endpoint 14. Only valid for HOST mode. - 0x00000000 - - - INTEP_PREAMBLE - Interrupt EP requires preamble (is a low speed device on a full speed hub) - [26:26] - read-write - - - INTEP_DIR - Direction of the interrupt endpoint. In=0, Out=1 - [25:25] - read-write - - - ENDPOINT - Endpoint number of the interrupt endpoint - [19:16] - read-write - - - ADDRESS - Device address - [6:0] - read-write - - - - - ADDR_ENDP15 - 0x0000003c - Interrupt endpoint 15. Only valid for HOST mode. - 0x00000000 - - - INTEP_PREAMBLE - Interrupt EP requires preamble (is a low speed device on a full speed hub) - [26:26] - read-write - - - INTEP_DIR - Direction of the interrupt endpoint. In=0, Out=1 - [25:25] - read-write - - - ENDPOINT - Endpoint number of the interrupt endpoint - [19:16] - read-write - - - ADDRESS - Device address - [6:0] - read-write - - - - - MAIN_CTRL - 0x00000040 - Main control register - 0x00000000 - - - SIM_TIMING - Reduced timings for simulation - [31:31] - read-write - - - HOST_NDEVICE - Device mode = 0, Host mode = 1 - [1:1] - read-write - - - CONTROLLER_EN - Enable controller - [0:0] - read-write - - - - - SOF_WR - 0x00000044 - Set the SOF (Start of Frame) frame number in the host controller. The SOF packet is sent every 1ms and the host will increment the frame number by 1 each time. - 0x00000000 - - - COUNT - [10:0] - write-only - - - - - SOF_RD - 0x00000048 - Read the last SOF (Start of Frame) frame number seen. In device mode the last SOF received from the host. In host mode the last SOF sent by the host. - 0x00000000 - - - COUNT - [10:0] - read-only - - - - - SIE_CTRL - 0x0000004c - SIE control register - 0x00000000 - - - EP0_INT_STALL - Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a STALL - [31:31] - read-write - - - EP0_DOUBLE_BUF - Device: EP0 single buffered = 0, double buffered = 1 - [30:30] - read-write - - - EP0_INT_1BUF - Device: Set bit in BUFF_STATUS for every buffer completed on EP0 - [29:29] - read-write - - - EP0_INT_2BUF - Device: Set bit in BUFF_STATUS for every 2 buffers completed on EP0 - [28:28] - read-write - - - EP0_INT_NAK - Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a NAK - [27:27] - read-write - - - DIRECT_EN - Direct bus drive enable - [26:26] - read-write - - - DIRECT_DP - Direct control of DP - [25:25] - read-write - - - DIRECT_DM - Direct control of DM - [24:24] - read-write - - - TRANSCEIVER_PD - Power down bus transceiver - [18:18] - read-write - - - RPU_OPT - Device: Pull-up strength (0=1K2, 1=2k3) - [17:17] - read-write - - - PULLUP_EN - Device: Enable pull up resistor - [16:16] - read-write - - - PULLDOWN_EN - Host: Enable pull down resistors - [15:15] - read-write - - - RESET_BUS - Host: Reset bus - [13:13] - write-only - - - RESUME - Device: Remote wakeup. Device can initiate its own resume after suspend. - [12:12] - write-only - - - VBUS_EN - Host: Enable VBUS - [11:11] - read-write - - - KEEP_ALIVE_EN - Host: Enable keep alive packet (for low speed bus) - [10:10] - read-write - - - SOF_EN - Host: Enable SOF generation (for full speed bus) - [9:9] - read-write - - - SOF_SYNC - Host: Delay packet(s) until after SOF - [8:8] - read-write - - - PREAMBLE_EN - Host: Preable enable for LS device on FS hub - [6:6] - read-write - - - STOP_TRANS - Host: Stop transaction - [4:4] - write-only - - - RECEIVE_DATA - Host: Receive transaction (IN to host) - [3:3] - read-write - - - SEND_DATA - Host: Send transaction (OUT from host) - [2:2] - read-write - - - SEND_SETUP - Host: Send Setup packet - [1:1] - read-write - - - START_TRANS - Host: Start transaction - [0:0] - write-only - - - - - SIE_STATUS - 0x00000050 - SIE status register - 0x00000000 - - - DATA_SEQ_ERROR - Data Sequence Error. - - The device can raise a sequence error in the following conditions: - - * A SETUP packet is received followed by a DATA1 packet (data phase should always be DATA0) * An OUT packet is received from the host but doesn't match the data pid in the buffer control register read from DPSRAM - - The host can raise a data sequence error in the following conditions: - - * An IN packet from the device has the wrong data PID - [31:31] - read-write - oneToClear - - - ACK_REC - ACK received. Raised by both host and device. - [30:30] - read-write - oneToClear - - - STALL_REC - Host: STALL received - [29:29] - read-write - oneToClear - - - NAK_REC - Host: NAK received - [28:28] - read-write - oneToClear - - - RX_TIMEOUT - RX timeout is raised by both the host and device if an ACK is not received in the maximum time specified by the USB spec. - [27:27] - read-write - oneToClear - - - RX_OVERFLOW - RX overflow is raised by the Serial RX engine if the incoming data is too fast. - [26:26] - read-write - oneToClear - - - BIT_STUFF_ERROR - Bit Stuff Error. Raised by the Serial RX engine. - [25:25] - read-write - oneToClear - - - CRC_ERROR - CRC Error. Raised by the Serial RX engine. - [24:24] - read-write - oneToClear - - - BUS_RESET - Device: bus reset received - [19:19] - read-write - oneToClear - - - TRANS_COMPLETE - Transaction complete. - - Raised by device if: - - * An IN or OUT packet is sent with the `LAST_BUFF` bit set in the buffer control register - - Raised by host if: - - * A setup packet is sent when no data in or data out transaction follows * An IN packet is received and the `LAST_BUFF` bit is set in the buffer control register * An IN packet is received with zero length * An OUT packet is sent and the `LAST_BUFF` bit is set - [18:18] - read-write - oneToClear - - - SETUP_REC - Device: Setup packet received - [17:17] - read-write - oneToClear - - - CONNECTED - Device: connected - [16:16] - read-only - - - RESUME - Host: Device has initiated a remote resume. Device: host has initiated a resume. - [11:11] - read-write - oneToClear - - - VBUS_OVER_CURR - VBUS over current detected - [10:10] - read-only - - - SPEED - Host: device speed. Disconnected = 00, LS = 01, FS = 10 - [9:8] - read-only - - - SUSPENDED - Bus in suspended state. Valid for device and host. Host and device will go into suspend if neither Keep Alive / SOF frames are enabled. - [4:4] - read-only - - - LINE_STATE - USB bus line state - [3:2] - read-only - - - VBUS_DETECTED - Device: VBUS Detected - [0:0] - read-only - - - - - INT_EP_CTRL - 0x00000054 - interrupt endpoint control register - 0x00000000 - - - INT_EP_ACTIVE - Host: Enable interrupt endpoint 1 => 15 - [15:1] - read-write - - - - - BUFF_STATUS - 0x00000058 - Buffer status register. A bit set here indicates that a buffer has completed on the endpoint (if the buffer interrupt is enabled). It is possible for 2 buffers to be completed, so clearing the buffer status bit may instantly re set it on the next clock cycle. - 0x00000000 - - - EP15_OUT - [31:31] - read-write - oneToClear - - - EP15_IN - [30:30] - read-write - oneToClear - - - EP14_OUT - [29:29] - read-write - oneToClear - - - EP14_IN - [28:28] - read-write - oneToClear - - - EP13_OUT - [27:27] - read-write - oneToClear - - - EP13_IN - [26:26] - read-write - oneToClear - - - EP12_OUT - [25:25] - read-write - oneToClear - - - EP12_IN - [24:24] - read-write - oneToClear - - - EP11_OUT - [23:23] - read-write - oneToClear - - - EP11_IN - [22:22] - read-write - oneToClear - - - EP10_OUT - [21:21] - read-write - oneToClear - - - EP10_IN - [20:20] - read-write - oneToClear - - - EP9_OUT - [19:19] - read-write - oneToClear - - - EP9_IN - [18:18] - read-write - oneToClear - - - EP8_OUT - [17:17] - read-write - oneToClear - - - EP8_IN - [16:16] - read-write - oneToClear - - - EP7_OUT - [15:15] - read-write - oneToClear - - - EP7_IN - [14:14] - read-write - oneToClear - - - EP6_OUT - [13:13] - read-write - oneToClear - - - EP6_IN - [12:12] - read-write - oneToClear - - - EP5_OUT - [11:11] - read-write - oneToClear - - - EP5_IN - [10:10] - read-write - oneToClear - - - EP4_OUT - [9:9] - read-write - oneToClear - - - EP4_IN - [8:8] - read-write - oneToClear - - - EP3_OUT - [7:7] - read-write - oneToClear - - - EP3_IN - [6:6] - read-write - oneToClear - - - EP2_OUT - [5:5] - read-write - oneToClear - - - EP2_IN - [4:4] - read-write - oneToClear - - - EP1_OUT - [3:3] - read-write - oneToClear - - - EP1_IN - [2:2] - read-write - oneToClear - - - EP0_OUT - [1:1] - read-write - oneToClear - - - EP0_IN - [0:0] - read-write - oneToClear - - - - - BUFF_CPU_SHOULD_HANDLE - 0x0000005c - Which of the double buffers should be handled. Only valid if using an interrupt per buffer (i.e. not per 2 buffers). Not valid for host interrupt endpoint polling because they are only single buffered. - 0x00000000 - - - EP15_OUT - [31:31] - read-only - - - EP15_IN - [30:30] - read-only - - - EP14_OUT - [29:29] - read-only - - - EP14_IN - [28:28] - read-only - - - EP13_OUT - [27:27] - read-only - - - EP13_IN - [26:26] - read-only - - - EP12_OUT - [25:25] - read-only - - - EP12_IN - [24:24] - read-only - - - EP11_OUT - [23:23] - read-only - - - EP11_IN - [22:22] - read-only - - - EP10_OUT - [21:21] - read-only - - - EP10_IN - [20:20] - read-only - - - EP9_OUT - [19:19] - read-only - - - EP9_IN - [18:18] - read-only - - - EP8_OUT - [17:17] - read-only - - - EP8_IN - [16:16] - read-only - - - EP7_OUT - [15:15] - read-only - - - EP7_IN - [14:14] - read-only - - - EP6_OUT - [13:13] - read-only - - - EP6_IN - [12:12] - read-only - - - EP5_OUT - [11:11] - read-only - - - EP5_IN - [10:10] - read-only - - - EP4_OUT - [9:9] - read-only - - - EP4_IN - [8:8] - read-only - - - EP3_OUT - [7:7] - read-only - - - EP3_IN - [6:6] - read-only - - - EP2_OUT - [5:5] - read-only - - - EP2_IN - [4:4] - read-only - - - EP1_OUT - [3:3] - read-only - - - EP1_IN - [2:2] - read-only - - - EP0_OUT - [1:1] - read-only - - - EP0_IN - [0:0] - read-only - - - - - EP_ABORT - 0x00000060 - Device only: Can be set to ignore the buffer control register for this endpoint in case you would like to revoke a buffer. A NAK will be sent for every access to the endpoint until this bit is cleared. A corresponding bit in `EP_ABORT_DONE` is set when it is safe to modify the buffer control register. - 0x00000000 - - - EP15_OUT - [31:31] - read-write - - - EP15_IN - [30:30] - read-write - - - EP14_OUT - [29:29] - read-write - - - EP14_IN - [28:28] - read-write - - - EP13_OUT - [27:27] - read-write - - - EP13_IN - [26:26] - read-write - - - EP12_OUT - [25:25] - read-write - - - EP12_IN - [24:24] - read-write - - - EP11_OUT - [23:23] - read-write - - - EP11_IN - [22:22] - read-write - - - EP10_OUT - [21:21] - read-write - - - EP10_IN - [20:20] - read-write - - - EP9_OUT - [19:19] - read-write - - - EP9_IN - [18:18] - read-write - - - EP8_OUT - [17:17] - read-write - - - EP8_IN - [16:16] - read-write - - - EP7_OUT - [15:15] - read-write - - - EP7_IN - [14:14] - read-write - - - EP6_OUT - [13:13] - read-write - - - EP6_IN - [12:12] - read-write - - - EP5_OUT - [11:11] - read-write - - - EP5_IN - [10:10] - read-write - - - EP4_OUT - [9:9] - read-write - - - EP4_IN - [8:8] - read-write - - - EP3_OUT - [7:7] - read-write - - - EP3_IN - [6:6] - read-write - - - EP2_OUT - [5:5] - read-write - - - EP2_IN - [4:4] - read-write - - - EP1_OUT - [3:3] - read-write - - - EP1_IN - [2:2] - read-write - - - EP0_OUT - [1:1] - read-write - - - EP0_IN - [0:0] - read-write - - - - - EP_ABORT_DONE - 0x00000064 - Device only: Used in conjunction with `EP_ABORT`. Set once an endpoint is idle so the programmer knows it is safe to modify the buffer control register. - 0x00000000 - - - EP15_OUT - [31:31] - read-write - oneToClear - - - EP15_IN - [30:30] - read-write - oneToClear - - - EP14_OUT - [29:29] - read-write - oneToClear - - - EP14_IN - [28:28] - read-write - oneToClear - - - EP13_OUT - [27:27] - read-write - oneToClear - - - EP13_IN - [26:26] - read-write - oneToClear - - - EP12_OUT - [25:25] - read-write - oneToClear - - - EP12_IN - [24:24] - read-write - oneToClear - - - EP11_OUT - [23:23] - read-write - oneToClear - - - EP11_IN - [22:22] - read-write - oneToClear - - - EP10_OUT - [21:21] - read-write - oneToClear - - - EP10_IN - [20:20] - read-write - oneToClear - - - EP9_OUT - [19:19] - read-write - oneToClear - - - EP9_IN - [18:18] - read-write - oneToClear - - - EP8_OUT - [17:17] - read-write - oneToClear - - - EP8_IN - [16:16] - read-write - oneToClear - - - EP7_OUT - [15:15] - read-write - oneToClear - - - EP7_IN - [14:14] - read-write - oneToClear - - - EP6_OUT - [13:13] - read-write - oneToClear - - - EP6_IN - [12:12] - read-write - oneToClear - - - EP5_OUT - [11:11] - read-write - oneToClear - - - EP5_IN - [10:10] - read-write - oneToClear - - - EP4_OUT - [9:9] - read-write - oneToClear - - - EP4_IN - [8:8] - read-write - oneToClear - - - EP3_OUT - [7:7] - read-write - oneToClear - - - EP3_IN - [6:6] - read-write - oneToClear - - - EP2_OUT - [5:5] - read-write - oneToClear - - - EP2_IN - [4:4] - read-write - oneToClear - - - EP1_OUT - [3:3] - read-write - oneToClear - - - EP1_IN - [2:2] - read-write - oneToClear - - - EP0_OUT - [1:1] - read-write - oneToClear - - - EP0_IN - [0:0] - read-write - oneToClear - - - - - EP_STALL_ARM - 0x00000068 - Device: this bit must be set in conjunction with the `STALL` bit in the buffer control register to send a STALL on EP0. The device controller clears these bits when a SETUP packet is received because the USB spec requires that a STALL condition is cleared when a SETUP packet is received. - 0x00000000 - - - EP0_OUT - [1:1] - read-write - - - EP0_IN - [0:0] - read-write - - - - - NAK_POLL - 0x0000006c - Used by the host controller. Sets the wait time in microseconds before trying again if the device replies with a NAK. - 0x00100010 - - - DELAY_FS - NAK polling interval for a full speed device - [25:16] - read-write - - - DELAY_LS - NAK polling interval for a low speed device - [9:0] - read-write - - - - - EP_STATUS_STALL_NAK - 0x00000070 - Device: bits are set when the `IRQ_ON_NAK` or `IRQ_ON_STALL` bits are set. For EP0 this comes from `SIE_CTRL`. For all other endpoints it comes from the endpoint control register. - 0x00000000 - - - EP15_OUT - [31:31] - read-write - oneToClear - - - EP15_IN - [30:30] - read-write - oneToClear - - - EP14_OUT - [29:29] - read-write - oneToClear - - - EP14_IN - [28:28] - read-write - oneToClear - - - EP13_OUT - [27:27] - read-write - oneToClear - - - EP13_IN - [26:26] - read-write - oneToClear - - - EP12_OUT - [25:25] - read-write - oneToClear - - - EP12_IN - [24:24] - read-write - oneToClear - - - EP11_OUT - [23:23] - read-write - oneToClear - - - EP11_IN - [22:22] - read-write - oneToClear - - - EP10_OUT - [21:21] - read-write - oneToClear - - - EP10_IN - [20:20] - read-write - oneToClear - - - EP9_OUT - [19:19] - read-write - oneToClear - - - EP9_IN - [18:18] - read-write - oneToClear - - - EP8_OUT - [17:17] - read-write - oneToClear - - - EP8_IN - [16:16] - read-write - oneToClear - - - EP7_OUT - [15:15] - read-write - oneToClear - - - EP7_IN - [14:14] - read-write - oneToClear - - - EP6_OUT - [13:13] - read-write - oneToClear - - - EP6_IN - [12:12] - read-write - oneToClear - - - EP5_OUT - [11:11] - read-write - oneToClear - - - EP5_IN - [10:10] - read-write - oneToClear - - - EP4_OUT - [9:9] - read-write - oneToClear - - - EP4_IN - [8:8] - read-write - oneToClear - - - EP3_OUT - [7:7] - read-write - oneToClear - - - EP3_IN - [6:6] - read-write - oneToClear - - - EP2_OUT - [5:5] - read-write - oneToClear - - - EP2_IN - [4:4] - read-write - oneToClear - - - EP1_OUT - [3:3] - read-write - oneToClear - - - EP1_IN - [2:2] - read-write - oneToClear - - - EP0_OUT - [1:1] - read-write - oneToClear - - - EP0_IN - [0:0] - read-write - oneToClear - - - - - USB_MUXING - 0x00000074 - Where to connect the USB controller. Should be to_phy by default. - 0x00000000 - - - SOFTCON - [3:3] - read-write - - - TO_DIGITAL_PAD - [2:2] - read-write - - - TO_EXTPHY - [1:1] - read-write - - - TO_PHY - [0:0] - read-write - - - - - USB_PWR - 0x00000078 - Overrides for the power signals in the event that the VBUS signals are not hooked up to GPIO. Set the value of the override and then the override enable so switch over to the override value. - 0x00000000 - - - OVERCURR_DETECT_EN - [5:5] - read-write - - - OVERCURR_DETECT - [4:4] - read-write - - - VBUS_DETECT_OVERRIDE_EN - [3:3] - read-write - - - VBUS_DETECT - [2:2] - read-write - - - VBUS_EN_OVERRIDE_EN - [1:1] - read-write - - - VBUS_EN - [0:0] - read-write - - - - - USBPHY_DIRECT - 0x0000007c - Note that most functions are driven directly from usb_fsls controller. This register allows more detailed control/status from the USB PHY. Useful for debug but not expected to be used in normal operation - Use in conjunction with usbphy_direct_override register - 0x00000000 - - - DM_OVV - Status bit from USB PHY - [22:22] - read-only - - - DP_OVV - Status bit from USB PHY - [21:21] - read-only - - - DM_OVCN - Status bit from USB PHY - [20:20] - read-only - - - DP_OVCN - Status bit from USB PHY - [19:19] - read-only - - - RX_DM - Status bit from USB PHY - DPM pin state - [18:18] - read-only - - - RX_DP - Status bit from USB PHY - DPP pin state - [17:17] - read-only - - - RX_DD - Status bit from USB PHY - RX Diff data - [16:16] - read-only - - - TX_DIFFMODE - [15:15] - read-write - - - TX_FSSLEW - [14:14] - read-write - - - TX_PD - [13:13] - read-write - - - RX_PD - [12:12] - read-write - - - TX_DM - Value to drive to USB PHY when override enable is set (which will override the default value or value driven from USB controller - TX_SEMODE=0, Ignored - TX_SEMODE=1, Drives DPM only. TX_DM_OE=1 to enable drive. DPM=TX_DM - [11:11] - read-write - - - TX_DP - Value to drive to USB PHY when override enable is set (which will override the default value or value driven from USB controller - TX_SEMODE=0, Drives DPP/DPM diff pair. TX_DP_OE=1 to enable drive. DPP=TX_DP, DPM=~TX_DP - TX_SEMODE=1, Drives DPP only. TX_DP_OE=1 to enable drive. DPP=TX_DP - [10:10] - read-write - - - TX_DM_OE - Value to drive to USB PHY when override enable is set (which will override the default value or value driven from USB controller - TX_SEMODE=0, Ignored. - TX_SEMODE=1, OE for DPM only. 0 - DPM in Hi-Z state; 1 - DPM driving - [9:9] - read-write - - - TX_DP_OE - Value to drive to USB PHY when override enable is set (which will override the default value or value driven from USB controller - TX_SEMODE=0, OE for DPP/DPM diff pair. 0 - DPP/DPM in Hi-Z state; 1 - DPP/DPM driving - TX_SEMODE=1, OE for DPP only. 0 - DPP in Hi-Z state; 1 - DPP driving - [8:8] - read-write - - - DM_PULLDN_EN - Value to drive to USB PHY when override enable is set (which will override the default value or value driven from USB controller - 1 - Enable Rpd on DPM - [6:6] - read-write - - - DM_PULLUP_EN - Value to drive to USB PHY when override enable is set (which will override the default value or value driven from USB controller - 1 - Enable Rpu on DPM - [5:5] - read-write - - - DM_PULLUP_HISEL - when dm_pullup_en is set high, this enables second resistor. 0 - Pull = Rpu2; 1 - Pull = Rpu1 + Rpu2 - [4:4] - read-write - - - DP_PULLDN_EN - Value to drive to USB PHY when override enable is set (which will override the default value or value driven from USB controller - 1 - Enable Rpd on DPP - [2:2] - read-write - - - DP_PULLUP_EN - Value to drive to USB PHY when override enable is set (which will override the default value or value driven from USB controller - [1:1] - read-write - - - DP_PULLUP_HISEL - when dp_pullup_en is set high, this enables second resistor. 0 - Pull = Rpu2; 1 - Pull = Rpu1 + Rpu2 - [0:0] - read-write - - - - - USBPHY_DIRECT_OVERRIDE - 0x00000080 - 0x00000000 - - - TX_DIFFMODE_OVERRIDE_EN - [15:15] - read-write - - - DM_PULLUP_OVERRIDE_EN - [12:12] - read-write - - - TX_FSSLEW_OVERRIDE_EN - [11:11] - read-write - - - TX_PD_OVERRIDE_EN - [10:10] - read-write - - - RX_PD_OVERRIDE_EN - [9:9] - read-write - - - TX_DM_OVERRIDE_EN - Override default value or value driven from USB Controller to PHY - [8:8] - read-write - - - TX_DP_OVERRIDE_EN - Override default value or value driven from USB Controller to PHY - [7:7] - read-write - - - TX_DM_OE_OVERRIDE_EN - Override default value or value driven from USB Controller to PHY - [6:6] - read-write - - - TX_DP_OE_OVERRIDE_EN - Override default value or value driven from USB Controller to PHY - [5:5] - read-write - - - DM_PULLDN_EN_OVERRIDE_EN - Override default value or value driven from USB Controller to PHY - [4:4] - read-write - - - DP_PULLDN_EN_OVERRIDE_EN - Override default value or value driven from USB Controller to PHY - [3:3] - read-write - - - DP_PULLUP_EN_OVERRIDE_EN - Override default value or value driven from USB Controller to PHY - [2:2] - read-write - - - DM_PULLUP_HISEL_OVERRIDE_EN - [1:1] - read-write - - - DP_PULLUP_HISEL_OVERRIDE_EN - [0:0] - read-write - - - - - USBPHY_TRIM - 0x00000084 - Note that most functions are driven directly from usb_fsls controller. This register allows more detailed control/status from the USB PHY. Useful for debug but not expected to be used in normal operation - 0x00001f1f - - - DM_PULLDN_TRIM - Value to drive to USB PHY - DM pulldown resistor trim control - Experimental data suggests that the reset value will work, but this register allows adjustment if required - [12:8] - read-write - - - DP_PULLDN_TRIM - Value to drive to USB PHY - DP pulldown resistor trim control - Experimental data suggests that the reset value will work, but this register allows adjustment if required - [4:0] - read-write - - - - - INTR - 0x0000008c - Raw Interrupts - 0x00000000 - - - EP_STALL_NAK - Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK. - [19:19] - read-only - - - ABORT_DONE - Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE. - [18:18] - read-only - - - DEV_SOF - Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD - [17:17] - read-only - - - SETUP_REQ - Device. Source: SIE_STATUS.SETUP_REC - [16:16] - read-only - - - DEV_RESUME_FROM_HOST - Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME_REMOTE - [15:15] - read-only - - - DEV_SUSPEND - Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED - [14:14] - read-only - - - DEV_CONN_DIS - Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED - [13:13] - read-only - - - BUS_RESET - Source: SIE_STATUS.BUS_RESET - [12:12] - read-only - - - VBUS_DETECT - Source: SIE_STATUS.VBUS_DETECT - [11:11] - read-only - - - STALL - Source: SIE_STATUS.STALL_REC - [10:10] - read-only - - - ERROR_CRC - Source: SIE_STATUS.CRC_ERROR - [9:9] - read-only - - - ERROR_BIT_STUFF - Source: SIE_STATUS.BIT_STUFF_ERROR - [8:8] - read-only - - - ERROR_RX_OVERFLOW - Source: SIE_STATUS.RX_OVERFLOW - [7:7] - read-only - - - ERROR_RX_TIMEOUT - Source: SIE_STATUS.RX_TIMEOUT - [6:6] - read-only - - - ERROR_DATA_SEQ - Source: SIE_STATUS.DATA_SEQ_ERROR - [5:5] - read-only - - - BUFF_STATUS - Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS. - [4:4] - read-only - - - TRANS_COMPLETE - Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit. - [3:3] - read-only - - - HOST_SOF - Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD - [2:2] - read-only - - - HOST_RESUME - Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME_REMOTE - [1:1] - read-only - - - HOST_CONN_DIS - Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED - [0:0] - read-only - - - - - INTE - 0x00000090 - Interrupt Enable - 0x00000000 - - - EP_STALL_NAK - Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK. - [19:19] - read-write - - - ABORT_DONE - Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE. - [18:18] - read-write - - - DEV_SOF - Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD - [17:17] - read-write - - - SETUP_REQ - Device. Source: SIE_STATUS.SETUP_REC - [16:16] - read-write - - - DEV_RESUME_FROM_HOST - Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME_REMOTE - [15:15] - read-write - - - DEV_SUSPEND - Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED - [14:14] - read-write - - - DEV_CONN_DIS - Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED - [13:13] - read-write - - - BUS_RESET - Source: SIE_STATUS.BUS_RESET - [12:12] - read-write - - - VBUS_DETECT - Source: SIE_STATUS.VBUS_DETECT - [11:11] - read-write - - - STALL - Source: SIE_STATUS.STALL_REC - [10:10] - read-write - - - ERROR_CRC - Source: SIE_STATUS.CRC_ERROR - [9:9] - read-write - - - ERROR_BIT_STUFF - Source: SIE_STATUS.BIT_STUFF_ERROR - [8:8] - read-write - - - ERROR_RX_OVERFLOW - Source: SIE_STATUS.RX_OVERFLOW - [7:7] - read-write - - - ERROR_RX_TIMEOUT - Source: SIE_STATUS.RX_TIMEOUT - [6:6] - read-write - - - ERROR_DATA_SEQ - Source: SIE_STATUS.DATA_SEQ_ERROR - [5:5] - read-write - - - BUFF_STATUS - Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS. - [4:4] - read-write - - - TRANS_COMPLETE - Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit. - [3:3] - read-write - - - HOST_SOF - Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD - [2:2] - read-write - - - HOST_RESUME - Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME_REMOTE - [1:1] - read-write - - - HOST_CONN_DIS - Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED - [0:0] - read-write - - - - - INTF - 0x00000094 - Interrupt Force - 0x00000000 - - - EP_STALL_NAK - Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK. - [19:19] - read-write - - - ABORT_DONE - Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE. - [18:18] - read-write - - - DEV_SOF - Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD - [17:17] - read-write - - - SETUP_REQ - Device. Source: SIE_STATUS.SETUP_REC - [16:16] - read-write - - - DEV_RESUME_FROM_HOST - Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME_REMOTE - [15:15] - read-write - - - DEV_SUSPEND - Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED - [14:14] - read-write - - - DEV_CONN_DIS - Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED - [13:13] - read-write - - - BUS_RESET - Source: SIE_STATUS.BUS_RESET - [12:12] - read-write - - - VBUS_DETECT - Source: SIE_STATUS.VBUS_DETECT - [11:11] - read-write - - - STALL - Source: SIE_STATUS.STALL_REC - [10:10] - read-write - - - ERROR_CRC - Source: SIE_STATUS.CRC_ERROR - [9:9] - read-write - - - ERROR_BIT_STUFF - Source: SIE_STATUS.BIT_STUFF_ERROR - [8:8] - read-write - - - ERROR_RX_OVERFLOW - Source: SIE_STATUS.RX_OVERFLOW - [7:7] - read-write - - - ERROR_RX_TIMEOUT - Source: SIE_STATUS.RX_TIMEOUT - [6:6] - read-write - - - ERROR_DATA_SEQ - Source: SIE_STATUS.DATA_SEQ_ERROR - [5:5] - read-write - - - BUFF_STATUS - Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS. - [4:4] - read-write - - - TRANS_COMPLETE - Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit. - [3:3] - read-write - - - HOST_SOF - Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD - [2:2] - read-write - - - HOST_RESUME - Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME_REMOTE - [1:1] - read-write - - - HOST_CONN_DIS - Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED - [0:0] - read-write - - - - - INTS - 0x00000098 - Interrupt status after masking & forcing - 0x00000000 - - - EP_STALL_NAK - Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK. - [19:19] - read-only - - - ABORT_DONE - Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE. - [18:18] - read-only - - - DEV_SOF - Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD - [17:17] - read-only - - - SETUP_REQ - Device. Source: SIE_STATUS.SETUP_REC - [16:16] - read-only - - - DEV_RESUME_FROM_HOST - Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME_REMOTE - [15:15] - read-only - - - DEV_SUSPEND - Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED - [14:14] - read-only - - - DEV_CONN_DIS - Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED - [13:13] - read-only - - - BUS_RESET - Source: SIE_STATUS.BUS_RESET - [12:12] - read-only - - - VBUS_DETECT - Source: SIE_STATUS.VBUS_DETECT - [11:11] - read-only - - - STALL - Source: SIE_STATUS.STALL_REC - [10:10] - read-only - - - ERROR_CRC - Source: SIE_STATUS.CRC_ERROR - [9:9] - read-only - - - ERROR_BIT_STUFF - Source: SIE_STATUS.BIT_STUFF_ERROR - [8:8] - read-only - - - ERROR_RX_OVERFLOW - Source: SIE_STATUS.RX_OVERFLOW - [7:7] - read-only - - - ERROR_RX_TIMEOUT - Source: SIE_STATUS.RX_TIMEOUT - [6:6] - read-only - - - ERROR_DATA_SEQ - Source: SIE_STATUS.DATA_SEQ_ERROR - [5:5] - read-only - - - BUFF_STATUS - Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS. - [4:4] - read-only - - - TRANS_COMPLETE - Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit. - [3:3] - read-only - - - HOST_SOF - Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD - [2:2] - read-only - - - HOST_RESUME - Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME_REMOTE - [1:1] - read-only - - - HOST_CONN_DIS - Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED - [0:0] - read-only - - - - - - - USB_DPRAM - DPRAM layout for USB device. - 0x50100000 - - 0 - 256 - registers - - - - SETUP_PACKET_LOW - 0x00000000 - Bytes 0-3 of the SETUP packet from the host. - 0x00000000 - - - WVALUE - [31:16] - read-write - - - BREQUEST - [15:8] - read-write - - - BMREQUESTTYPE - [7:0] - read-write - - - - - SETUP_PACKET_HIGH - 0x00000004 - Bytes 4-7 of the setup packet from the host. - 0x00000000 - - - WLENGTH - [31:16] - read-write - - - WINDEX - [15:0] - read-write - - - - - EP1_IN_CONTROL - 0x00000008 - 0x00000000 - - - ENABLE - Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. - [31:31] - read-write - - - DOUBLE_BUFFERED - This endpoint is double buffered. - [30:30] - read-write - - - INTERRUPT_PER_BUFF - Trigger an interrupt each time a buffer is done. - [29:29] - read-write - - - INTERRUPT_PER_DOUBLE_BUFF - Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. - [28:28] - read-write - - - ENDPOINT_TYPE - [27:26] - read-write - - - Control - 0 - - - Isochronous - 1 - - - Bulk - 2 - - - Interrupt - 3 - - - - - INTERRUPT_ON_STALL - Trigger an interrupt if a STALL is sent. Intended for debug only. - [17:17] - read-write - - - INTERRUPT_ON_NAK - Trigger an interrupt if a NAK is sent. Intended for debug only. - [16:16] - read-write - - - BUFFER_ADDRESS - 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. - [15:0] - read-write - - - - - EP1_OUT_CONTROL - 0x0000000c - 0x00000000 - - - ENABLE - Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. - [31:31] - read-write - - - DOUBLE_BUFFERED - This endpoint is double buffered. - [30:30] - read-write - - - INTERRUPT_PER_BUFF - Trigger an interrupt each time a buffer is done. - [29:29] - read-write - - - INTERRUPT_PER_DOUBLE_BUFF - Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. - [28:28] - read-write - - - ENDPOINT_TYPE - [27:26] - read-write - - - Control - 0 - - - Isochronous - 1 - - - Bulk - 2 - - - Interrupt - 3 - - - - - INTERRUPT_ON_STALL - Trigger an interrupt if a STALL is sent. Intended for debug only. - [17:17] - read-write - - - INTERRUPT_ON_NAK - Trigger an interrupt if a NAK is sent. Intended for debug only. - [16:16] - read-write - - - BUFFER_ADDRESS - 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. - [15:0] - read-write - - - - - EP2_IN_CONTROL - 0x00000010 - 0x00000000 - - - ENABLE - Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. - [31:31] - read-write - - - DOUBLE_BUFFERED - This endpoint is double buffered. - [30:30] - read-write - - - INTERRUPT_PER_BUFF - Trigger an interrupt each time a buffer is done. - [29:29] - read-write - - - INTERRUPT_PER_DOUBLE_BUFF - Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. - [28:28] - read-write - - - ENDPOINT_TYPE - [27:26] - read-write - - - Control - 0 - - - Isochronous - 1 - - - Bulk - 2 - - - Interrupt - 3 - - - - - INTERRUPT_ON_STALL - Trigger an interrupt if a STALL is sent. Intended for debug only. - [17:17] - read-write - - - INTERRUPT_ON_NAK - Trigger an interrupt if a NAK is sent. Intended for debug only. - [16:16] - read-write - - - BUFFER_ADDRESS - 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. - [15:0] - read-write - - - - - EP2_OUT_CONTROL - 0x00000014 - 0x00000000 - - - ENABLE - Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. - [31:31] - read-write - - - DOUBLE_BUFFERED - This endpoint is double buffered. - [30:30] - read-write - - - INTERRUPT_PER_BUFF - Trigger an interrupt each time a buffer is done. - [29:29] - read-write - - - INTERRUPT_PER_DOUBLE_BUFF - Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. - [28:28] - read-write - - - ENDPOINT_TYPE - [27:26] - read-write - - - Control - 0 - - - Isochronous - 1 - - - Bulk - 2 - - - Interrupt - 3 - - - - - INTERRUPT_ON_STALL - Trigger an interrupt if a STALL is sent. Intended for debug only. - [17:17] - read-write - - - INTERRUPT_ON_NAK - Trigger an interrupt if a NAK is sent. Intended for debug only. - [16:16] - read-write - - - BUFFER_ADDRESS - 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. - [15:0] - read-write - - - - - EP3_IN_CONTROL - 0x00000018 - 0x00000000 - - - ENABLE - Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. - [31:31] - read-write - - - DOUBLE_BUFFERED - This endpoint is double buffered. - [30:30] - read-write - - - INTERRUPT_PER_BUFF - Trigger an interrupt each time a buffer is done. - [29:29] - read-write - - - INTERRUPT_PER_DOUBLE_BUFF - Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. - [28:28] - read-write - - - ENDPOINT_TYPE - [27:26] - read-write - - - Control - 0 - - - Isochronous - 1 - - - Bulk - 2 - - - Interrupt - 3 - - - - - INTERRUPT_ON_STALL - Trigger an interrupt if a STALL is sent. Intended for debug only. - [17:17] - read-write - - - INTERRUPT_ON_NAK - Trigger an interrupt if a NAK is sent. Intended for debug only. - [16:16] - read-write - - - BUFFER_ADDRESS - 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. - [15:0] - read-write - - - - - EP3_OUT_CONTROL - 0x0000001c - 0x00000000 - - - ENABLE - Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. - [31:31] - read-write - - - DOUBLE_BUFFERED - This endpoint is double buffered. - [30:30] - read-write - - - INTERRUPT_PER_BUFF - Trigger an interrupt each time a buffer is done. - [29:29] - read-write - - - INTERRUPT_PER_DOUBLE_BUFF - Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. - [28:28] - read-write - - - ENDPOINT_TYPE - [27:26] - read-write - - - Control - 0 - - - Isochronous - 1 - - - Bulk - 2 - - - Interrupt - 3 - - - - - INTERRUPT_ON_STALL - Trigger an interrupt if a STALL is sent. Intended for debug only. - [17:17] - read-write - - - INTERRUPT_ON_NAK - Trigger an interrupt if a NAK is sent. Intended for debug only. - [16:16] - read-write - - - BUFFER_ADDRESS - 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. - [15:0] - read-write - - - - - EP4_IN_CONTROL - 0x00000020 - 0x00000000 - - - ENABLE - Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. - [31:31] - read-write - - - DOUBLE_BUFFERED - This endpoint is double buffered. - [30:30] - read-write - - - INTERRUPT_PER_BUFF - Trigger an interrupt each time a buffer is done. - [29:29] - read-write - - - INTERRUPT_PER_DOUBLE_BUFF - Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. - [28:28] - read-write - - - ENDPOINT_TYPE - [27:26] - read-write - - - Control - 0 - - - Isochronous - 1 - - - Bulk - 2 - - - Interrupt - 3 - - - - - INTERRUPT_ON_STALL - Trigger an interrupt if a STALL is sent. Intended for debug only. - [17:17] - read-write - - - INTERRUPT_ON_NAK - Trigger an interrupt if a NAK is sent. Intended for debug only. - [16:16] - read-write - - - BUFFER_ADDRESS - 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. - [15:0] - read-write - - - - - EP4_OUT_CONTROL - 0x00000024 - 0x00000000 - - - ENABLE - Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. - [31:31] - read-write - - - DOUBLE_BUFFERED - This endpoint is double buffered. - [30:30] - read-write - - - INTERRUPT_PER_BUFF - Trigger an interrupt each time a buffer is done. - [29:29] - read-write - - - INTERRUPT_PER_DOUBLE_BUFF - Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. - [28:28] - read-write - - - ENDPOINT_TYPE - [27:26] - read-write - - - Control - 0 - - - Isochronous - 1 - - - Bulk - 2 - - - Interrupt - 3 - - - - - INTERRUPT_ON_STALL - Trigger an interrupt if a STALL is sent. Intended for debug only. - [17:17] - read-write - - - INTERRUPT_ON_NAK - Trigger an interrupt if a NAK is sent. Intended for debug only. - [16:16] - read-write - - - BUFFER_ADDRESS - 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. - [15:0] - read-write - - - - - EP5_IN_CONTROL - 0x00000028 - 0x00000000 - - - ENABLE - Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. - [31:31] - read-write - - - DOUBLE_BUFFERED - This endpoint is double buffered. - [30:30] - read-write - - - INTERRUPT_PER_BUFF - Trigger an interrupt each time a buffer is done. - [29:29] - read-write - - - INTERRUPT_PER_DOUBLE_BUFF - Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. - [28:28] - read-write - - - ENDPOINT_TYPE - [27:26] - read-write - - - Control - 0 - - - Isochronous - 1 - - - Bulk - 2 - - - Interrupt - 3 - - - - - INTERRUPT_ON_STALL - Trigger an interrupt if a STALL is sent. Intended for debug only. - [17:17] - read-write - - - INTERRUPT_ON_NAK - Trigger an interrupt if a NAK is sent. Intended for debug only. - [16:16] - read-write - - - BUFFER_ADDRESS - 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. - [15:0] - read-write - - - - - EP5_OUT_CONTROL - 0x0000002c - 0x00000000 - - - ENABLE - Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. - [31:31] - read-write - - - DOUBLE_BUFFERED - This endpoint is double buffered. - [30:30] - read-write - - - INTERRUPT_PER_BUFF - Trigger an interrupt each time a buffer is done. - [29:29] - read-write - - - INTERRUPT_PER_DOUBLE_BUFF - Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. - [28:28] - read-write - - - ENDPOINT_TYPE - [27:26] - read-write - - - Control - 0 - - - Isochronous - 1 - - - Bulk - 2 - - - Interrupt - 3 - - - - - INTERRUPT_ON_STALL - Trigger an interrupt if a STALL is sent. Intended for debug only. - [17:17] - read-write - - - INTERRUPT_ON_NAK - Trigger an interrupt if a NAK is sent. Intended for debug only. - [16:16] - read-write - - - BUFFER_ADDRESS - 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. - [15:0] - read-write - - - - - EP6_IN_CONTROL - 0x00000030 - 0x00000000 - - - ENABLE - Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. - [31:31] - read-write - - - DOUBLE_BUFFERED - This endpoint is double buffered. - [30:30] - read-write - - - INTERRUPT_PER_BUFF - Trigger an interrupt each time a buffer is done. - [29:29] - read-write - - - INTERRUPT_PER_DOUBLE_BUFF - Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. - [28:28] - read-write - - - ENDPOINT_TYPE - [27:26] - read-write - - - Control - 0 - - - Isochronous - 1 - - - Bulk - 2 - - - Interrupt - 3 - - - - - INTERRUPT_ON_STALL - Trigger an interrupt if a STALL is sent. Intended for debug only. - [17:17] - read-write - - - INTERRUPT_ON_NAK - Trigger an interrupt if a NAK is sent. Intended for debug only. - [16:16] - read-write - - - BUFFER_ADDRESS - 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. - [15:0] - read-write - - - - - EP6_OUT_CONTROL - 0x00000034 - 0x00000000 - - - ENABLE - Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. - [31:31] - read-write - - - DOUBLE_BUFFERED - This endpoint is double buffered. - [30:30] - read-write - - - INTERRUPT_PER_BUFF - Trigger an interrupt each time a buffer is done. - [29:29] - read-write - - - INTERRUPT_PER_DOUBLE_BUFF - Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. - [28:28] - read-write - - - ENDPOINT_TYPE - [27:26] - read-write - - - Control - 0 - - - Isochronous - 1 - - - Bulk - 2 - - - Interrupt - 3 - - - - - INTERRUPT_ON_STALL - Trigger an interrupt if a STALL is sent. Intended for debug only. - [17:17] - read-write - - - INTERRUPT_ON_NAK - Trigger an interrupt if a NAK is sent. Intended for debug only. - [16:16] - read-write - - - BUFFER_ADDRESS - 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. - [15:0] - read-write - - - - - EP7_IN_CONTROL - 0x00000038 - 0x00000000 - - - ENABLE - Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. - [31:31] - read-write - - - DOUBLE_BUFFERED - This endpoint is double buffered. - [30:30] - read-write - - - INTERRUPT_PER_BUFF - Trigger an interrupt each time a buffer is done. - [29:29] - read-write - - - INTERRUPT_PER_DOUBLE_BUFF - Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. - [28:28] - read-write - - - ENDPOINT_TYPE - [27:26] - read-write - - - Control - 0 - - - Isochronous - 1 - - - Bulk - 2 - - - Interrupt - 3 - - - - - INTERRUPT_ON_STALL - Trigger an interrupt if a STALL is sent. Intended for debug only. - [17:17] - read-write - - - INTERRUPT_ON_NAK - Trigger an interrupt if a NAK is sent. Intended for debug only. - [16:16] - read-write - - - BUFFER_ADDRESS - 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. - [15:0] - read-write - - - - - EP7_OUT_CONTROL - 0x0000003c - 0x00000000 - - - ENABLE - Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. - [31:31] - read-write - - - DOUBLE_BUFFERED - This endpoint is double buffered. - [30:30] - read-write - - - INTERRUPT_PER_BUFF - Trigger an interrupt each time a buffer is done. - [29:29] - read-write - - - INTERRUPT_PER_DOUBLE_BUFF - Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. - [28:28] - read-write - - - ENDPOINT_TYPE - [27:26] - read-write - - - Control - 0 - - - Isochronous - 1 - - - Bulk - 2 - - - Interrupt - 3 - - - - - INTERRUPT_ON_STALL - Trigger an interrupt if a STALL is sent. Intended for debug only. - [17:17] - read-write - - - INTERRUPT_ON_NAK - Trigger an interrupt if a NAK is sent. Intended for debug only. - [16:16] - read-write - - - BUFFER_ADDRESS - 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. - [15:0] - read-write - - - - - EP8_IN_CONTROL - 0x00000040 - 0x00000000 - - - ENABLE - Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. - [31:31] - read-write - - - DOUBLE_BUFFERED - This endpoint is double buffered. - [30:30] - read-write - - - INTERRUPT_PER_BUFF - Trigger an interrupt each time a buffer is done. - [29:29] - read-write - - - INTERRUPT_PER_DOUBLE_BUFF - Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. - [28:28] - read-write - - - ENDPOINT_TYPE - [27:26] - read-write - - - Control - 0 - - - Isochronous - 1 - - - Bulk - 2 - - - Interrupt - 3 - - - - - INTERRUPT_ON_STALL - Trigger an interrupt if a STALL is sent. Intended for debug only. - [17:17] - read-write - - - INTERRUPT_ON_NAK - Trigger an interrupt if a NAK is sent. Intended for debug only. - [16:16] - read-write - - - BUFFER_ADDRESS - 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. - [15:0] - read-write - - - - - EP8_OUT_CONTROL - 0x00000044 - 0x00000000 - - - ENABLE - Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. - [31:31] - read-write - - - DOUBLE_BUFFERED - This endpoint is double buffered. - [30:30] - read-write - - - INTERRUPT_PER_BUFF - Trigger an interrupt each time a buffer is done. - [29:29] - read-write - - - INTERRUPT_PER_DOUBLE_BUFF - Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. - [28:28] - read-write - - - ENDPOINT_TYPE - [27:26] - read-write - - - Control - 0 - - - Isochronous - 1 - - - Bulk - 2 - - - Interrupt - 3 - - - - - INTERRUPT_ON_STALL - Trigger an interrupt if a STALL is sent. Intended for debug only. - [17:17] - read-write - - - INTERRUPT_ON_NAK - Trigger an interrupt if a NAK is sent. Intended for debug only. - [16:16] - read-write - - - BUFFER_ADDRESS - 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. - [15:0] - read-write - - - - - EP9_IN_CONTROL - 0x00000048 - 0x00000000 - - - ENABLE - Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. - [31:31] - read-write - - - DOUBLE_BUFFERED - This endpoint is double buffered. - [30:30] - read-write - - - INTERRUPT_PER_BUFF - Trigger an interrupt each time a buffer is done. - [29:29] - read-write - - - INTERRUPT_PER_DOUBLE_BUFF - Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. - [28:28] - read-write - - - ENDPOINT_TYPE - [27:26] - read-write - - - Control - 0 - - - Isochronous - 1 - - - Bulk - 2 - - - Interrupt - 3 - - - - - INTERRUPT_ON_STALL - Trigger an interrupt if a STALL is sent. Intended for debug only. - [17:17] - read-write - - - INTERRUPT_ON_NAK - Trigger an interrupt if a NAK is sent. Intended for debug only. - [16:16] - read-write - - - BUFFER_ADDRESS - 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. - [15:0] - read-write - - - - - EP9_OUT_CONTROL - 0x0000004c - 0x00000000 - - - ENABLE - Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. - [31:31] - read-write - - - DOUBLE_BUFFERED - This endpoint is double buffered. - [30:30] - read-write - - - INTERRUPT_PER_BUFF - Trigger an interrupt each time a buffer is done. - [29:29] - read-write - - - INTERRUPT_PER_DOUBLE_BUFF - Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. - [28:28] - read-write - - - ENDPOINT_TYPE - [27:26] - read-write - - - Control - 0 - - - Isochronous - 1 - - - Bulk - 2 - - - Interrupt - 3 - - - - - INTERRUPT_ON_STALL - Trigger an interrupt if a STALL is sent. Intended for debug only. - [17:17] - read-write - - - INTERRUPT_ON_NAK - Trigger an interrupt if a NAK is sent. Intended for debug only. - [16:16] - read-write - - - BUFFER_ADDRESS - 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. - [15:0] - read-write - - - - - EP10_IN_CONTROL - 0x00000050 - 0x00000000 - - - ENABLE - Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. - [31:31] - read-write - - - DOUBLE_BUFFERED - This endpoint is double buffered. - [30:30] - read-write - - - INTERRUPT_PER_BUFF - Trigger an interrupt each time a buffer is done. - [29:29] - read-write - - - INTERRUPT_PER_DOUBLE_BUFF - Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. - [28:28] - read-write - - - ENDPOINT_TYPE - [27:26] - read-write - - - Control - 0 - - - Isochronous - 1 - - - Bulk - 2 - - - Interrupt - 3 - - - - - INTERRUPT_ON_STALL - Trigger an interrupt if a STALL is sent. Intended for debug only. - [17:17] - read-write - - - INTERRUPT_ON_NAK - Trigger an interrupt if a NAK is sent. Intended for debug only. - [16:16] - read-write - - - BUFFER_ADDRESS - 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. - [15:0] - read-write - - - - - EP10_OUT_CONTROL - 0x00000054 - 0x00000000 - - - ENABLE - Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. - [31:31] - read-write - - - DOUBLE_BUFFERED - This endpoint is double buffered. - [30:30] - read-write - - - INTERRUPT_PER_BUFF - Trigger an interrupt each time a buffer is done. - [29:29] - read-write - - - INTERRUPT_PER_DOUBLE_BUFF - Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. - [28:28] - read-write - - - ENDPOINT_TYPE - [27:26] - read-write - - - Control - 0 - - - Isochronous - 1 - - - Bulk - 2 - - - Interrupt - 3 - - - - - INTERRUPT_ON_STALL - Trigger an interrupt if a STALL is sent. Intended for debug only. - [17:17] - read-write - - - INTERRUPT_ON_NAK - Trigger an interrupt if a NAK is sent. Intended for debug only. - [16:16] - read-write - - - BUFFER_ADDRESS - 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. - [15:0] - read-write - - - - - EP11_IN_CONTROL - 0x00000058 - 0x00000000 - - - ENABLE - Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. - [31:31] - read-write - - - DOUBLE_BUFFERED - This endpoint is double buffered. - [30:30] - read-write - - - INTERRUPT_PER_BUFF - Trigger an interrupt each time a buffer is done. - [29:29] - read-write - - - INTERRUPT_PER_DOUBLE_BUFF - Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. - [28:28] - read-write - - - ENDPOINT_TYPE - [27:26] - read-write - - - Control - 0 - - - Isochronous - 1 - - - Bulk - 2 - - - Interrupt - 3 - - - - - INTERRUPT_ON_STALL - Trigger an interrupt if a STALL is sent. Intended for debug only. - [17:17] - read-write - - - INTERRUPT_ON_NAK - Trigger an interrupt if a NAK is sent. Intended for debug only. - [16:16] - read-write - - - BUFFER_ADDRESS - 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. - [15:0] - read-write - - - - - EP11_OUT_CONTROL - 0x0000005c - 0x00000000 - - - ENABLE - Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. - [31:31] - read-write - - - DOUBLE_BUFFERED - This endpoint is double buffered. - [30:30] - read-write - - - INTERRUPT_PER_BUFF - Trigger an interrupt each time a buffer is done. - [29:29] - read-write - - - INTERRUPT_PER_DOUBLE_BUFF - Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. - [28:28] - read-write - - - ENDPOINT_TYPE - [27:26] - read-write - - - Control - 0 - - - Isochronous - 1 - - - Bulk - 2 - - - Interrupt - 3 - - - - - INTERRUPT_ON_STALL - Trigger an interrupt if a STALL is sent. Intended for debug only. - [17:17] - read-write - - - INTERRUPT_ON_NAK - Trigger an interrupt if a NAK is sent. Intended for debug only. - [16:16] - read-write - - - BUFFER_ADDRESS - 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. - [15:0] - read-write - - - - - EP12_IN_CONTROL - 0x00000060 - 0x00000000 - - - ENABLE - Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. - [31:31] - read-write - - - DOUBLE_BUFFERED - This endpoint is double buffered. - [30:30] - read-write - - - INTERRUPT_PER_BUFF - Trigger an interrupt each time a buffer is done. - [29:29] - read-write - - - INTERRUPT_PER_DOUBLE_BUFF - Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. - [28:28] - read-write - - - ENDPOINT_TYPE - [27:26] - read-write - - - Control - 0 - - - Isochronous - 1 - - - Bulk - 2 - - - Interrupt - 3 - - - - - INTERRUPT_ON_STALL - Trigger an interrupt if a STALL is sent. Intended for debug only. - [17:17] - read-write - - - INTERRUPT_ON_NAK - Trigger an interrupt if a NAK is sent. Intended for debug only. - [16:16] - read-write - - - BUFFER_ADDRESS - 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. - [15:0] - read-write - - - - - EP12_OUT_CONTROL - 0x00000064 - 0x00000000 - - - ENABLE - Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. - [31:31] - read-write - - - DOUBLE_BUFFERED - This endpoint is double buffered. - [30:30] - read-write - - - INTERRUPT_PER_BUFF - Trigger an interrupt each time a buffer is done. - [29:29] - read-write - - - INTERRUPT_PER_DOUBLE_BUFF - Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. - [28:28] - read-write - - - ENDPOINT_TYPE - [27:26] - read-write - - - Control - 0 - - - Isochronous - 1 - - - Bulk - 2 - - - Interrupt - 3 - - - - - INTERRUPT_ON_STALL - Trigger an interrupt if a STALL is sent. Intended for debug only. - [17:17] - read-write - - - INTERRUPT_ON_NAK - Trigger an interrupt if a NAK is sent. Intended for debug only. - [16:16] - read-write - - - BUFFER_ADDRESS - 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. - [15:0] - read-write - - - - - EP13_IN_CONTROL - 0x00000068 - 0x00000000 - - - ENABLE - Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. - [31:31] - read-write - - - DOUBLE_BUFFERED - This endpoint is double buffered. - [30:30] - read-write - - - INTERRUPT_PER_BUFF - Trigger an interrupt each time a buffer is done. - [29:29] - read-write - - - INTERRUPT_PER_DOUBLE_BUFF - Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. - [28:28] - read-write - - - ENDPOINT_TYPE - [27:26] - read-write - - - Control - 0 - - - Isochronous - 1 - - - Bulk - 2 - - - Interrupt - 3 - - - - - INTERRUPT_ON_STALL - Trigger an interrupt if a STALL is sent. Intended for debug only. - [17:17] - read-write - - - INTERRUPT_ON_NAK - Trigger an interrupt if a NAK is sent. Intended for debug only. - [16:16] - read-write - - - BUFFER_ADDRESS - 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. - [15:0] - read-write - - - - - EP13_OUT_CONTROL - 0x0000006c - 0x00000000 - - - ENABLE - Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. - [31:31] - read-write - - - DOUBLE_BUFFERED - This endpoint is double buffered. - [30:30] - read-write - - - INTERRUPT_PER_BUFF - Trigger an interrupt each time a buffer is done. - [29:29] - read-write - - - INTERRUPT_PER_DOUBLE_BUFF - Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. - [28:28] - read-write - - - ENDPOINT_TYPE - [27:26] - read-write - - - Control - 0 - - - Isochronous - 1 - - - Bulk - 2 - - - Interrupt - 3 - - - - - INTERRUPT_ON_STALL - Trigger an interrupt if a STALL is sent. Intended for debug only. - [17:17] - read-write - - - INTERRUPT_ON_NAK - Trigger an interrupt if a NAK is sent. Intended for debug only. - [16:16] - read-write - - - BUFFER_ADDRESS - 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. - [15:0] - read-write - - - - - EP14_IN_CONTROL - 0x00000070 - 0x00000000 - - - ENABLE - Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. - [31:31] - read-write - - - DOUBLE_BUFFERED - This endpoint is double buffered. - [30:30] - read-write - - - INTERRUPT_PER_BUFF - Trigger an interrupt each time a buffer is done. - [29:29] - read-write - - - INTERRUPT_PER_DOUBLE_BUFF - Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. - [28:28] - read-write - - - ENDPOINT_TYPE - [27:26] - read-write - - - Control - 0 - - - Isochronous - 1 - - - Bulk - 2 - - - Interrupt - 3 - - - - - INTERRUPT_ON_STALL - Trigger an interrupt if a STALL is sent. Intended for debug only. - [17:17] - read-write - - - INTERRUPT_ON_NAK - Trigger an interrupt if a NAK is sent. Intended for debug only. - [16:16] - read-write - - - BUFFER_ADDRESS - 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. - [15:0] - read-write - - - - - EP14_OUT_CONTROL - 0x00000074 - 0x00000000 - - - ENABLE - Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. - [31:31] - read-write - - - DOUBLE_BUFFERED - This endpoint is double buffered. - [30:30] - read-write - - - INTERRUPT_PER_BUFF - Trigger an interrupt each time a buffer is done. - [29:29] - read-write - - - INTERRUPT_PER_DOUBLE_BUFF - Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. - [28:28] - read-write - - - ENDPOINT_TYPE - [27:26] - read-write - - - Control - 0 - - - Isochronous - 1 - - - Bulk - 2 - - - Interrupt - 3 - - - - - INTERRUPT_ON_STALL - Trigger an interrupt if a STALL is sent. Intended for debug only. - [17:17] - read-write - - - INTERRUPT_ON_NAK - Trigger an interrupt if a NAK is sent. Intended for debug only. - [16:16] - read-write - - - BUFFER_ADDRESS - 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. - [15:0] - read-write - - - - - EP15_IN_CONTROL - 0x00000078 - 0x00000000 - - - ENABLE - Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. - [31:31] - read-write - - - DOUBLE_BUFFERED - This endpoint is double buffered. - [30:30] - read-write - - - INTERRUPT_PER_BUFF - Trigger an interrupt each time a buffer is done. - [29:29] - read-write - - - INTERRUPT_PER_DOUBLE_BUFF - Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. - [28:28] - read-write - - - ENDPOINT_TYPE - [27:26] - read-write - - - Control - 0 - - - Isochronous - 1 - - - Bulk - 2 - - - Interrupt - 3 - - - - - INTERRUPT_ON_STALL - Trigger an interrupt if a STALL is sent. Intended for debug only. - [17:17] - read-write - - - INTERRUPT_ON_NAK - Trigger an interrupt if a NAK is sent. Intended for debug only. - [16:16] - read-write - - - BUFFER_ADDRESS - 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. - [15:0] - read-write - - - - - EP15_OUT_CONTROL - 0x0000007c - 0x00000000 - - - ENABLE - Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. - [31:31] - read-write - - - DOUBLE_BUFFERED - This endpoint is double buffered. - [30:30] - read-write - - - INTERRUPT_PER_BUFF - Trigger an interrupt each time a buffer is done. - [29:29] - read-write - - - INTERRUPT_PER_DOUBLE_BUFF - Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. - [28:28] - read-write - - - ENDPOINT_TYPE - [27:26] - read-write - - - Control - 0 - - - Isochronous - 1 - - - Bulk - 2 - - - Interrupt - 3 - - - - - INTERRUPT_ON_STALL - Trigger an interrupt if a STALL is sent. Intended for debug only. - [17:17] - read-write - - - INTERRUPT_ON_NAK - Trigger an interrupt if a NAK is sent. Intended for debug only. - [16:16] - read-write - - - BUFFER_ADDRESS - 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. - [15:0] - read-write - - - - - EP0_IN_BUFFER_CONTROL - 0x00000080 - Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. - Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. - 0x00000000 - - - FULL_1 - Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [31:31] - read-write - - - LAST_1 - Buffer 1 is the last buffer of the transfer. - [30:30] - read-write - - - PID_1 - The data pid of buffer 1. - [29:29] - read-write - - - DOUBLE_BUFFER_ISO_OFFSET - The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. - For a non Isochronous endpoint the offset is always 64 bytes. - [28:27] - read-write - - - 128 - 0 - - - 256 - 1 - - - 512 - 2 - - - 1024 - 3 - - - - - AVAILABLE_1 - Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [26:26] - read-write - - - LENGTH_1 - The length of the data in buffer 1. - [25:16] - read-write - - - FULL_0 - Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [15:15] - read-write - - - LAST_0 - Buffer 0 is the last buffer of the transfer. - [14:14] - read-write - - - PID_0 - The data pid of buffer 0. - [13:13] - read-write - - - RESET - Reset the buffer selector to buffer 0. - [12:12] - read-write - - - STALL - Reply with a stall (valid for both buffers). - [11:11] - read-write - - - AVAILABLE_0 - Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [10:10] - read-write - - - LENGTH_0 - The length of the data in buffer 0. - [9:0] - read-write - - - - - EP0_OUT_BUFFER_CONTROL - 0x00000084 - Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. - Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. - 0x00000000 - - - FULL_1 - Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [31:31] - read-write - - - LAST_1 - Buffer 1 is the last buffer of the transfer. - [30:30] - read-write - - - PID_1 - The data pid of buffer 1. - [29:29] - read-write - - - DOUBLE_BUFFER_ISO_OFFSET - The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. - For a non Isochronous endpoint the offset is always 64 bytes. - [28:27] - read-write - - - 128 - 0 - - - 256 - 1 - - - 512 - 2 - - - 1024 - 3 - - - - - AVAILABLE_1 - Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [26:26] - read-write - - - LENGTH_1 - The length of the data in buffer 1. - [25:16] - read-write - - - FULL_0 - Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [15:15] - read-write - - - LAST_0 - Buffer 0 is the last buffer of the transfer. - [14:14] - read-write - - - PID_0 - The data pid of buffer 0. - [13:13] - read-write - - - RESET - Reset the buffer selector to buffer 0. - [12:12] - read-write - - - STALL - Reply with a stall (valid for both buffers). - [11:11] - read-write - - - AVAILABLE_0 - Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [10:10] - read-write - - - LENGTH_0 - The length of the data in buffer 0. - [9:0] - read-write - - - - - EP1_IN_BUFFER_CONTROL - 0x00000088 - Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. - Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. - 0x00000000 - - - FULL_1 - Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [31:31] - read-write - - - LAST_1 - Buffer 1 is the last buffer of the transfer. - [30:30] - read-write - - - PID_1 - The data pid of buffer 1. - [29:29] - read-write - - - DOUBLE_BUFFER_ISO_OFFSET - The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. - For a non Isochronous endpoint the offset is always 64 bytes. - [28:27] - read-write - - - 128 - 0 - - - 256 - 1 - - - 512 - 2 - - - 1024 - 3 - - - - - AVAILABLE_1 - Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [26:26] - read-write - - - LENGTH_1 - The length of the data in buffer 1. - [25:16] - read-write - - - FULL_0 - Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [15:15] - read-write - - - LAST_0 - Buffer 0 is the last buffer of the transfer. - [14:14] - read-write - - - PID_0 - The data pid of buffer 0. - [13:13] - read-write - - - RESET - Reset the buffer selector to buffer 0. - [12:12] - read-write - - - STALL - Reply with a stall (valid for both buffers). - [11:11] - read-write - - - AVAILABLE_0 - Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [10:10] - read-write - - - LENGTH_0 - The length of the data in buffer 0. - [9:0] - read-write - - - - - EP1_OUT_BUFFER_CONTROL - 0x0000008c - Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. - Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. - 0x00000000 - - - FULL_1 - Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [31:31] - read-write - - - LAST_1 - Buffer 1 is the last buffer of the transfer. - [30:30] - read-write - - - PID_1 - The data pid of buffer 1. - [29:29] - read-write - - - DOUBLE_BUFFER_ISO_OFFSET - The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. - For a non Isochronous endpoint the offset is always 64 bytes. - [28:27] - read-write - - - 128 - 0 - - - 256 - 1 - - - 512 - 2 - - - 1024 - 3 - - - - - AVAILABLE_1 - Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [26:26] - read-write - - - LENGTH_1 - The length of the data in buffer 1. - [25:16] - read-write - - - FULL_0 - Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [15:15] - read-write - - - LAST_0 - Buffer 0 is the last buffer of the transfer. - [14:14] - read-write - - - PID_0 - The data pid of buffer 0. - [13:13] - read-write - - - RESET - Reset the buffer selector to buffer 0. - [12:12] - read-write - - - STALL - Reply with a stall (valid for both buffers). - [11:11] - read-write - - - AVAILABLE_0 - Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [10:10] - read-write - - - LENGTH_0 - The length of the data in buffer 0. - [9:0] - read-write - - - - - EP2_IN_BUFFER_CONTROL - 0x00000090 - Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. - Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. - 0x00000000 - - - FULL_1 - Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [31:31] - read-write - - - LAST_1 - Buffer 1 is the last buffer of the transfer. - [30:30] - read-write - - - PID_1 - The data pid of buffer 1. - [29:29] - read-write - - - DOUBLE_BUFFER_ISO_OFFSET - The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. - For a non Isochronous endpoint the offset is always 64 bytes. - [28:27] - read-write - - - 128 - 0 - - - 256 - 1 - - - 512 - 2 - - - 1024 - 3 - - - - - AVAILABLE_1 - Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [26:26] - read-write - - - LENGTH_1 - The length of the data in buffer 1. - [25:16] - read-write - - - FULL_0 - Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [15:15] - read-write - - - LAST_0 - Buffer 0 is the last buffer of the transfer. - [14:14] - read-write - - - PID_0 - The data pid of buffer 0. - [13:13] - read-write - - - RESET - Reset the buffer selector to buffer 0. - [12:12] - read-write - - - STALL - Reply with a stall (valid for both buffers). - [11:11] - read-write - - - AVAILABLE_0 - Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [10:10] - read-write - - - LENGTH_0 - The length of the data in buffer 0. - [9:0] - read-write - - - - - EP2_OUT_BUFFER_CONTROL - 0x00000094 - Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. - Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. - 0x00000000 - - - FULL_1 - Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [31:31] - read-write - - - LAST_1 - Buffer 1 is the last buffer of the transfer. - [30:30] - read-write - - - PID_1 - The data pid of buffer 1. - [29:29] - read-write - - - DOUBLE_BUFFER_ISO_OFFSET - The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. - For a non Isochronous endpoint the offset is always 64 bytes. - [28:27] - read-write - - - 128 - 0 - - - 256 - 1 - - - 512 - 2 - - - 1024 - 3 - - - - - AVAILABLE_1 - Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [26:26] - read-write - - - LENGTH_1 - The length of the data in buffer 1. - [25:16] - read-write - - - FULL_0 - Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [15:15] - read-write - - - LAST_0 - Buffer 0 is the last buffer of the transfer. - [14:14] - read-write - - - PID_0 - The data pid of buffer 0. - [13:13] - read-write - - - RESET - Reset the buffer selector to buffer 0. - [12:12] - read-write - - - STALL - Reply with a stall (valid for both buffers). - [11:11] - read-write - - - AVAILABLE_0 - Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [10:10] - read-write - - - LENGTH_0 - The length of the data in buffer 0. - [9:0] - read-write - - - - - EP3_IN_BUFFER_CONTROL - 0x00000098 - Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. - Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. - 0x00000000 - - - FULL_1 - Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [31:31] - read-write - - - LAST_1 - Buffer 1 is the last buffer of the transfer. - [30:30] - read-write - - - PID_1 - The data pid of buffer 1. - [29:29] - read-write - - - DOUBLE_BUFFER_ISO_OFFSET - The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. - For a non Isochronous endpoint the offset is always 64 bytes. - [28:27] - read-write - - - 128 - 0 - - - 256 - 1 - - - 512 - 2 - - - 1024 - 3 - - - - - AVAILABLE_1 - Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [26:26] - read-write - - - LENGTH_1 - The length of the data in buffer 1. - [25:16] - read-write - - - FULL_0 - Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [15:15] - read-write - - - LAST_0 - Buffer 0 is the last buffer of the transfer. - [14:14] - read-write - - - PID_0 - The data pid of buffer 0. - [13:13] - read-write - - - RESET - Reset the buffer selector to buffer 0. - [12:12] - read-write - - - STALL - Reply with a stall (valid for both buffers). - [11:11] - read-write - - - AVAILABLE_0 - Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [10:10] - read-write - - - LENGTH_0 - The length of the data in buffer 0. - [9:0] - read-write - - - - - EP3_OUT_BUFFER_CONTROL - 0x0000009c - Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. - Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. - 0x00000000 - - - FULL_1 - Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [31:31] - read-write - - - LAST_1 - Buffer 1 is the last buffer of the transfer. - [30:30] - read-write - - - PID_1 - The data pid of buffer 1. - [29:29] - read-write - - - DOUBLE_BUFFER_ISO_OFFSET - The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. - For a non Isochronous endpoint the offset is always 64 bytes. - [28:27] - read-write - - - 128 - 0 - - - 256 - 1 - - - 512 - 2 - - - 1024 - 3 - - - - - AVAILABLE_1 - Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [26:26] - read-write - - - LENGTH_1 - The length of the data in buffer 1. - [25:16] - read-write - - - FULL_0 - Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [15:15] - read-write - - - LAST_0 - Buffer 0 is the last buffer of the transfer. - [14:14] - read-write - - - PID_0 - The data pid of buffer 0. - [13:13] - read-write - - - RESET - Reset the buffer selector to buffer 0. - [12:12] - read-write - - - STALL - Reply with a stall (valid for both buffers). - [11:11] - read-write - - - AVAILABLE_0 - Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [10:10] - read-write - - - LENGTH_0 - The length of the data in buffer 0. - [9:0] - read-write - - - - - EP4_IN_BUFFER_CONTROL - 0x000000a0 - Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. - Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. - 0x00000000 - - - FULL_1 - Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [31:31] - read-write - - - LAST_1 - Buffer 1 is the last buffer of the transfer. - [30:30] - read-write - - - PID_1 - The data pid of buffer 1. - [29:29] - read-write - - - DOUBLE_BUFFER_ISO_OFFSET - The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. - For a non Isochronous endpoint the offset is always 64 bytes. - [28:27] - read-write - - - 128 - 0 - - - 256 - 1 - - - 512 - 2 - - - 1024 - 3 - - - - - AVAILABLE_1 - Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [26:26] - read-write - - - LENGTH_1 - The length of the data in buffer 1. - [25:16] - read-write - - - FULL_0 - Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [15:15] - read-write - - - LAST_0 - Buffer 0 is the last buffer of the transfer. - [14:14] - read-write - - - PID_0 - The data pid of buffer 0. - [13:13] - read-write - - - RESET - Reset the buffer selector to buffer 0. - [12:12] - read-write - - - STALL - Reply with a stall (valid for both buffers). - [11:11] - read-write - - - AVAILABLE_0 - Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [10:10] - read-write - - - LENGTH_0 - The length of the data in buffer 0. - [9:0] - read-write - - - - - EP4_OUT_BUFFER_CONTROL - 0x000000a4 - Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. - Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. - 0x00000000 - - - FULL_1 - Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [31:31] - read-write - - - LAST_1 - Buffer 1 is the last buffer of the transfer. - [30:30] - read-write - - - PID_1 - The data pid of buffer 1. - [29:29] - read-write - - - DOUBLE_BUFFER_ISO_OFFSET - The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. - For a non Isochronous endpoint the offset is always 64 bytes. - [28:27] - read-write - - - 128 - 0 - - - 256 - 1 - - - 512 - 2 - - - 1024 - 3 - - - - - AVAILABLE_1 - Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [26:26] - read-write - - - LENGTH_1 - The length of the data in buffer 1. - [25:16] - read-write - - - FULL_0 - Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [15:15] - read-write - - - LAST_0 - Buffer 0 is the last buffer of the transfer. - [14:14] - read-write - - - PID_0 - The data pid of buffer 0. - [13:13] - read-write - - - RESET - Reset the buffer selector to buffer 0. - [12:12] - read-write - - - STALL - Reply with a stall (valid for both buffers). - [11:11] - read-write - - - AVAILABLE_0 - Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [10:10] - read-write - - - LENGTH_0 - The length of the data in buffer 0. - [9:0] - read-write - - - - - EP5_IN_BUFFER_CONTROL - 0x000000a8 - Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. - Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. - 0x00000000 - - - FULL_1 - Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [31:31] - read-write - - - LAST_1 - Buffer 1 is the last buffer of the transfer. - [30:30] - read-write - - - PID_1 - The data pid of buffer 1. - [29:29] - read-write - - - DOUBLE_BUFFER_ISO_OFFSET - The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. - For a non Isochronous endpoint the offset is always 64 bytes. - [28:27] - read-write - - - 128 - 0 - - - 256 - 1 - - - 512 - 2 - - - 1024 - 3 - - - - - AVAILABLE_1 - Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [26:26] - read-write - - - LENGTH_1 - The length of the data in buffer 1. - [25:16] - read-write - - - FULL_0 - Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [15:15] - read-write - - - LAST_0 - Buffer 0 is the last buffer of the transfer. - [14:14] - read-write - - - PID_0 - The data pid of buffer 0. - [13:13] - read-write - - - RESET - Reset the buffer selector to buffer 0. - [12:12] - read-write - - - STALL - Reply with a stall (valid for both buffers). - [11:11] - read-write - - - AVAILABLE_0 - Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [10:10] - read-write - - - LENGTH_0 - The length of the data in buffer 0. - [9:0] - read-write - - - - - EP5_OUT_BUFFER_CONTROL - 0x000000ac - Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. - Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. - 0x00000000 - - - FULL_1 - Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [31:31] - read-write - - - LAST_1 - Buffer 1 is the last buffer of the transfer. - [30:30] - read-write - - - PID_1 - The data pid of buffer 1. - [29:29] - read-write - - - DOUBLE_BUFFER_ISO_OFFSET - The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. - For a non Isochronous endpoint the offset is always 64 bytes. - [28:27] - read-write - - - 128 - 0 - - - 256 - 1 - - - 512 - 2 - - - 1024 - 3 - - - - - AVAILABLE_1 - Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [26:26] - read-write - - - LENGTH_1 - The length of the data in buffer 1. - [25:16] - read-write - - - FULL_0 - Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [15:15] - read-write - - - LAST_0 - Buffer 0 is the last buffer of the transfer. - [14:14] - read-write - - - PID_0 - The data pid of buffer 0. - [13:13] - read-write - - - RESET - Reset the buffer selector to buffer 0. - [12:12] - read-write - - - STALL - Reply with a stall (valid for both buffers). - [11:11] - read-write - - - AVAILABLE_0 - Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [10:10] - read-write - - - LENGTH_0 - The length of the data in buffer 0. - [9:0] - read-write - - - - - EP6_IN_BUFFER_CONTROL - 0x000000b0 - Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. - Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. - 0x00000000 - - - FULL_1 - Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [31:31] - read-write - - - LAST_1 - Buffer 1 is the last buffer of the transfer. - [30:30] - read-write - - - PID_1 - The data pid of buffer 1. - [29:29] - read-write - - - DOUBLE_BUFFER_ISO_OFFSET - The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. - For a non Isochronous endpoint the offset is always 64 bytes. - [28:27] - read-write - - - 128 - 0 - - - 256 - 1 - - - 512 - 2 - - - 1024 - 3 - - - - - AVAILABLE_1 - Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [26:26] - read-write - - - LENGTH_1 - The length of the data in buffer 1. - [25:16] - read-write - - - FULL_0 - Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [15:15] - read-write - - - LAST_0 - Buffer 0 is the last buffer of the transfer. - [14:14] - read-write - - - PID_0 - The data pid of buffer 0. - [13:13] - read-write - - - RESET - Reset the buffer selector to buffer 0. - [12:12] - read-write - - - STALL - Reply with a stall (valid for both buffers). - [11:11] - read-write - - - AVAILABLE_0 - Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [10:10] - read-write - - - LENGTH_0 - The length of the data in buffer 0. - [9:0] - read-write - - - - - EP6_OUT_BUFFER_CONTROL - 0x000000b4 - Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. - Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. - 0x00000000 - - - FULL_1 - Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [31:31] - read-write - - - LAST_1 - Buffer 1 is the last buffer of the transfer. - [30:30] - read-write - - - PID_1 - The data pid of buffer 1. - [29:29] - read-write - - - DOUBLE_BUFFER_ISO_OFFSET - The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. - For a non Isochronous endpoint the offset is always 64 bytes. - [28:27] - read-write - - - 128 - 0 - - - 256 - 1 - - - 512 - 2 - - - 1024 - 3 - - - - - AVAILABLE_1 - Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [26:26] - read-write - - - LENGTH_1 - The length of the data in buffer 1. - [25:16] - read-write - - - FULL_0 - Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [15:15] - read-write - - - LAST_0 - Buffer 0 is the last buffer of the transfer. - [14:14] - read-write - - - PID_0 - The data pid of buffer 0. - [13:13] - read-write - - - RESET - Reset the buffer selector to buffer 0. - [12:12] - read-write - - - STALL - Reply with a stall (valid for both buffers). - [11:11] - read-write - - - AVAILABLE_0 - Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [10:10] - read-write - - - LENGTH_0 - The length of the data in buffer 0. - [9:0] - read-write - - - - - EP7_IN_BUFFER_CONTROL - 0x000000b8 - Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. - Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. - 0x00000000 - - - FULL_1 - Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [31:31] - read-write - - - LAST_1 - Buffer 1 is the last buffer of the transfer. - [30:30] - read-write - - - PID_1 - The data pid of buffer 1. - [29:29] - read-write - - - DOUBLE_BUFFER_ISO_OFFSET - The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. - For a non Isochronous endpoint the offset is always 64 bytes. - [28:27] - read-write - - - 128 - 0 - - - 256 - 1 - - - 512 - 2 - - - 1024 - 3 - - - - - AVAILABLE_1 - Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [26:26] - read-write - - - LENGTH_1 - The length of the data in buffer 1. - [25:16] - read-write - - - FULL_0 - Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [15:15] - read-write - - - LAST_0 - Buffer 0 is the last buffer of the transfer. - [14:14] - read-write - - - PID_0 - The data pid of buffer 0. - [13:13] - read-write - - - RESET - Reset the buffer selector to buffer 0. - [12:12] - read-write - - - STALL - Reply with a stall (valid for both buffers). - [11:11] - read-write - - - AVAILABLE_0 - Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [10:10] - read-write - - - LENGTH_0 - The length of the data in buffer 0. - [9:0] - read-write - - - - - EP7_OUT_BUFFER_CONTROL - 0x000000bc - Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. - Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. - 0x00000000 - - - FULL_1 - Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [31:31] - read-write - - - LAST_1 - Buffer 1 is the last buffer of the transfer. - [30:30] - read-write - - - PID_1 - The data pid of buffer 1. - [29:29] - read-write - - - DOUBLE_BUFFER_ISO_OFFSET - The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. - For a non Isochronous endpoint the offset is always 64 bytes. - [28:27] - read-write - - - 128 - 0 - - - 256 - 1 - - - 512 - 2 - - - 1024 - 3 - - - - - AVAILABLE_1 - Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [26:26] - read-write - - - LENGTH_1 - The length of the data in buffer 1. - [25:16] - read-write - - - FULL_0 - Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [15:15] - read-write - - - LAST_0 - Buffer 0 is the last buffer of the transfer. - [14:14] - read-write - - - PID_0 - The data pid of buffer 0. - [13:13] - read-write - - - RESET - Reset the buffer selector to buffer 0. - [12:12] - read-write - - - STALL - Reply with a stall (valid for both buffers). - [11:11] - read-write - - - AVAILABLE_0 - Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [10:10] - read-write - - - LENGTH_0 - The length of the data in buffer 0. - [9:0] - read-write - - - - - EP8_IN_BUFFER_CONTROL - 0x000000c0 - Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. - Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. - 0x00000000 - - - FULL_1 - Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [31:31] - read-write - - - LAST_1 - Buffer 1 is the last buffer of the transfer. - [30:30] - read-write - - - PID_1 - The data pid of buffer 1. - [29:29] - read-write - - - DOUBLE_BUFFER_ISO_OFFSET - The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. - For a non Isochronous endpoint the offset is always 64 bytes. - [28:27] - read-write - - - 128 - 0 - - - 256 - 1 - - - 512 - 2 - - - 1024 - 3 - - - - - AVAILABLE_1 - Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [26:26] - read-write - - - LENGTH_1 - The length of the data in buffer 1. - [25:16] - read-write - - - FULL_0 - Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [15:15] - read-write - - - LAST_0 - Buffer 0 is the last buffer of the transfer. - [14:14] - read-write - - - PID_0 - The data pid of buffer 0. - [13:13] - read-write - - - RESET - Reset the buffer selector to buffer 0. - [12:12] - read-write - - - STALL - Reply with a stall (valid for both buffers). - [11:11] - read-write - - - AVAILABLE_0 - Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [10:10] - read-write - - - LENGTH_0 - The length of the data in buffer 0. - [9:0] - read-write - - - - - EP8_OUT_BUFFER_CONTROL - 0x000000c4 - Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. - Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. - 0x00000000 - - - FULL_1 - Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [31:31] - read-write - - - LAST_1 - Buffer 1 is the last buffer of the transfer. - [30:30] - read-write - - - PID_1 - The data pid of buffer 1. - [29:29] - read-write - - - DOUBLE_BUFFER_ISO_OFFSET - The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. - For a non Isochronous endpoint the offset is always 64 bytes. - [28:27] - read-write - - - 128 - 0 - - - 256 - 1 - - - 512 - 2 - - - 1024 - 3 - - - - - AVAILABLE_1 - Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [26:26] - read-write - - - LENGTH_1 - The length of the data in buffer 1. - [25:16] - read-write - - - FULL_0 - Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [15:15] - read-write - - - LAST_0 - Buffer 0 is the last buffer of the transfer. - [14:14] - read-write - - - PID_0 - The data pid of buffer 0. - [13:13] - read-write - - - RESET - Reset the buffer selector to buffer 0. - [12:12] - read-write - - - STALL - Reply with a stall (valid for both buffers). - [11:11] - read-write - - - AVAILABLE_0 - Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [10:10] - read-write - - - LENGTH_0 - The length of the data in buffer 0. - [9:0] - read-write - - - - - EP9_IN_BUFFER_CONTROL - 0x000000c8 - Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. - Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. - 0x00000000 - - - FULL_1 - Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [31:31] - read-write - - - LAST_1 - Buffer 1 is the last buffer of the transfer. - [30:30] - read-write - - - PID_1 - The data pid of buffer 1. - [29:29] - read-write - - - DOUBLE_BUFFER_ISO_OFFSET - The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. - For a non Isochronous endpoint the offset is always 64 bytes. - [28:27] - read-write - - - 128 - 0 - - - 256 - 1 - - - 512 - 2 - - - 1024 - 3 - - - - - AVAILABLE_1 - Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [26:26] - read-write - - - LENGTH_1 - The length of the data in buffer 1. - [25:16] - read-write - - - FULL_0 - Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [15:15] - read-write - - - LAST_0 - Buffer 0 is the last buffer of the transfer. - [14:14] - read-write - - - PID_0 - The data pid of buffer 0. - [13:13] - read-write - - - RESET - Reset the buffer selector to buffer 0. - [12:12] - read-write - - - STALL - Reply with a stall (valid for both buffers). - [11:11] - read-write - - - AVAILABLE_0 - Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [10:10] - read-write - - - LENGTH_0 - The length of the data in buffer 0. - [9:0] - read-write - - - - - EP9_OUT_BUFFER_CONTROL - 0x000000cc - Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. - Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. - 0x00000000 - - - FULL_1 - Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [31:31] - read-write - - - LAST_1 - Buffer 1 is the last buffer of the transfer. - [30:30] - read-write - - - PID_1 - The data pid of buffer 1. - [29:29] - read-write - - - DOUBLE_BUFFER_ISO_OFFSET - The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. - For a non Isochronous endpoint the offset is always 64 bytes. - [28:27] - read-write - - - 128 - 0 - - - 256 - 1 - - - 512 - 2 - - - 1024 - 3 - - - - - AVAILABLE_1 - Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [26:26] - read-write - - - LENGTH_1 - The length of the data in buffer 1. - [25:16] - read-write - - - FULL_0 - Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [15:15] - read-write - - - LAST_0 - Buffer 0 is the last buffer of the transfer. - [14:14] - read-write - - - PID_0 - The data pid of buffer 0. - [13:13] - read-write - - - RESET - Reset the buffer selector to buffer 0. - [12:12] - read-write - - - STALL - Reply with a stall (valid for both buffers). - [11:11] - read-write - - - AVAILABLE_0 - Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [10:10] - read-write - - - LENGTH_0 - The length of the data in buffer 0. - [9:0] - read-write - - - - - EP10_IN_BUFFER_CONTROL - 0x000000d0 - Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. - Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. - 0x00000000 - - - FULL_1 - Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [31:31] - read-write - - - LAST_1 - Buffer 1 is the last buffer of the transfer. - [30:30] - read-write - - - PID_1 - The data pid of buffer 1. - [29:29] - read-write - - - DOUBLE_BUFFER_ISO_OFFSET - The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. - For a non Isochronous endpoint the offset is always 64 bytes. - [28:27] - read-write - - - 128 - 0 - - - 256 - 1 - - - 512 - 2 - - - 1024 - 3 - - - - - AVAILABLE_1 - Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [26:26] - read-write - - - LENGTH_1 - The length of the data in buffer 1. - [25:16] - read-write - - - FULL_0 - Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [15:15] - read-write - - - LAST_0 - Buffer 0 is the last buffer of the transfer. - [14:14] - read-write - - - PID_0 - The data pid of buffer 0. - [13:13] - read-write - - - RESET - Reset the buffer selector to buffer 0. - [12:12] - read-write - - - STALL - Reply with a stall (valid for both buffers). - [11:11] - read-write - - - AVAILABLE_0 - Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [10:10] - read-write - - - LENGTH_0 - The length of the data in buffer 0. - [9:0] - read-write - - - - - EP10_OUT_BUFFER_CONTROL - 0x000000d4 - Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. - Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. - 0x00000000 - - - FULL_1 - Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [31:31] - read-write - - - LAST_1 - Buffer 1 is the last buffer of the transfer. - [30:30] - read-write - - - PID_1 - The data pid of buffer 1. - [29:29] - read-write - - - DOUBLE_BUFFER_ISO_OFFSET - The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. - For a non Isochronous endpoint the offset is always 64 bytes. - [28:27] - read-write - - - 128 - 0 - - - 256 - 1 - - - 512 - 2 - - - 1024 - 3 - - - - - AVAILABLE_1 - Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [26:26] - read-write - - - LENGTH_1 - The length of the data in buffer 1. - [25:16] - read-write - - - FULL_0 - Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [15:15] - read-write - - - LAST_0 - Buffer 0 is the last buffer of the transfer. - [14:14] - read-write - - - PID_0 - The data pid of buffer 0. - [13:13] - read-write - - - RESET - Reset the buffer selector to buffer 0. - [12:12] - read-write - - - STALL - Reply with a stall (valid for both buffers). - [11:11] - read-write - - - AVAILABLE_0 - Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [10:10] - read-write - - - LENGTH_0 - The length of the data in buffer 0. - [9:0] - read-write - - - - - EP11_IN_BUFFER_CONTROL - 0x000000d8 - Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. - Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. - 0x00000000 - - - FULL_1 - Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [31:31] - read-write - - - LAST_1 - Buffer 1 is the last buffer of the transfer. - [30:30] - read-write - - - PID_1 - The data pid of buffer 1. - [29:29] - read-write - - - DOUBLE_BUFFER_ISO_OFFSET - The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. - For a non Isochronous endpoint the offset is always 64 bytes. - [28:27] - read-write - - - 128 - 0 - - - 256 - 1 - - - 512 - 2 - - - 1024 - 3 - - - - - AVAILABLE_1 - Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [26:26] - read-write - - - LENGTH_1 - The length of the data in buffer 1. - [25:16] - read-write - - - FULL_0 - Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [15:15] - read-write - - - LAST_0 - Buffer 0 is the last buffer of the transfer. - [14:14] - read-write - - - PID_0 - The data pid of buffer 0. - [13:13] - read-write - - - RESET - Reset the buffer selector to buffer 0. - [12:12] - read-write - - - STALL - Reply with a stall (valid for both buffers). - [11:11] - read-write - - - AVAILABLE_0 - Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [10:10] - read-write - - - LENGTH_0 - The length of the data in buffer 0. - [9:0] - read-write - - - - - EP11_OUT_BUFFER_CONTROL - 0x000000dc - Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. - Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. - 0x00000000 - - - FULL_1 - Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [31:31] - read-write - - - LAST_1 - Buffer 1 is the last buffer of the transfer. - [30:30] - read-write - - - PID_1 - The data pid of buffer 1. - [29:29] - read-write - - - DOUBLE_BUFFER_ISO_OFFSET - The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. - For a non Isochronous endpoint the offset is always 64 bytes. - [28:27] - read-write - - - 128 - 0 - - - 256 - 1 - - - 512 - 2 - - - 1024 - 3 - - - - - AVAILABLE_1 - Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [26:26] - read-write - - - LENGTH_1 - The length of the data in buffer 1. - [25:16] - read-write - - - FULL_0 - Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [15:15] - read-write - - - LAST_0 - Buffer 0 is the last buffer of the transfer. - [14:14] - read-write - - - PID_0 - The data pid of buffer 0. - [13:13] - read-write - - - RESET - Reset the buffer selector to buffer 0. - [12:12] - read-write - - - STALL - Reply with a stall (valid for both buffers). - [11:11] - read-write - - - AVAILABLE_0 - Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [10:10] - read-write - - - LENGTH_0 - The length of the data in buffer 0. - [9:0] - read-write - - - - - EP12_IN_BUFFER_CONTROL - 0x000000e0 - Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. - Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. - 0x00000000 - - - FULL_1 - Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [31:31] - read-write - - - LAST_1 - Buffer 1 is the last buffer of the transfer. - [30:30] - read-write - - - PID_1 - The data pid of buffer 1. - [29:29] - read-write - - - DOUBLE_BUFFER_ISO_OFFSET - The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. - For a non Isochronous endpoint the offset is always 64 bytes. - [28:27] - read-write - - - 128 - 0 - - - 256 - 1 - - - 512 - 2 - - - 1024 - 3 - - - - - AVAILABLE_1 - Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [26:26] - read-write - - - LENGTH_1 - The length of the data in buffer 1. - [25:16] - read-write - - - FULL_0 - Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [15:15] - read-write - - - LAST_0 - Buffer 0 is the last buffer of the transfer. - [14:14] - read-write - - - PID_0 - The data pid of buffer 0. - [13:13] - read-write - - - RESET - Reset the buffer selector to buffer 0. - [12:12] - read-write - - - STALL - Reply with a stall (valid for both buffers). - [11:11] - read-write - - - AVAILABLE_0 - Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [10:10] - read-write - - - LENGTH_0 - The length of the data in buffer 0. - [9:0] - read-write - - - - - EP12_OUT_BUFFER_CONTROL - 0x000000e4 - Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. - Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. - 0x00000000 - - - FULL_1 - Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [31:31] - read-write - - - LAST_1 - Buffer 1 is the last buffer of the transfer. - [30:30] - read-write - - - PID_1 - The data pid of buffer 1. - [29:29] - read-write - - - DOUBLE_BUFFER_ISO_OFFSET - The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. - For a non Isochronous endpoint the offset is always 64 bytes. - [28:27] - read-write - - - 128 - 0 - - - 256 - 1 - - - 512 - 2 - - - 1024 - 3 - - - - - AVAILABLE_1 - Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [26:26] - read-write - - - LENGTH_1 - The length of the data in buffer 1. - [25:16] - read-write - - - FULL_0 - Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [15:15] - read-write - - - LAST_0 - Buffer 0 is the last buffer of the transfer. - [14:14] - read-write - - - PID_0 - The data pid of buffer 0. - [13:13] - read-write - - - RESET - Reset the buffer selector to buffer 0. - [12:12] - read-write - - - STALL - Reply with a stall (valid for both buffers). - [11:11] - read-write - - - AVAILABLE_0 - Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [10:10] - read-write - - - LENGTH_0 - The length of the data in buffer 0. - [9:0] - read-write - - - - - EP13_IN_BUFFER_CONTROL - 0x000000e8 - Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. - Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. - 0x00000000 - - - FULL_1 - Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [31:31] - read-write - - - LAST_1 - Buffer 1 is the last buffer of the transfer. - [30:30] - read-write - - - PID_1 - The data pid of buffer 1. - [29:29] - read-write - - - DOUBLE_BUFFER_ISO_OFFSET - The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. - For a non Isochronous endpoint the offset is always 64 bytes. - [28:27] - read-write - - - 128 - 0 - - - 256 - 1 - - - 512 - 2 - - - 1024 - 3 - - - - - AVAILABLE_1 - Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [26:26] - read-write - - - LENGTH_1 - The length of the data in buffer 1. - [25:16] - read-write - - - FULL_0 - Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [15:15] - read-write - - - LAST_0 - Buffer 0 is the last buffer of the transfer. - [14:14] - read-write - - - PID_0 - The data pid of buffer 0. - [13:13] - read-write - - - RESET - Reset the buffer selector to buffer 0. - [12:12] - read-write - - - STALL - Reply with a stall (valid for both buffers). - [11:11] - read-write - - - AVAILABLE_0 - Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [10:10] - read-write - - - LENGTH_0 - The length of the data in buffer 0. - [9:0] - read-write - - - - - EP13_OUT_BUFFER_CONTROL - 0x000000ec - Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. - Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. - 0x00000000 - - - FULL_1 - Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [31:31] - read-write - - - LAST_1 - Buffer 1 is the last buffer of the transfer. - [30:30] - read-write - - - PID_1 - The data pid of buffer 1. - [29:29] - read-write - - - DOUBLE_BUFFER_ISO_OFFSET - The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. - For a non Isochronous endpoint the offset is always 64 bytes. - [28:27] - read-write - - - 128 - 0 - - - 256 - 1 - - - 512 - 2 - - - 1024 - 3 - - - - - AVAILABLE_1 - Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [26:26] - read-write - - - LENGTH_1 - The length of the data in buffer 1. - [25:16] - read-write - - - FULL_0 - Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [15:15] - read-write - - - LAST_0 - Buffer 0 is the last buffer of the transfer. - [14:14] - read-write - - - PID_0 - The data pid of buffer 0. - [13:13] - read-write - - - RESET - Reset the buffer selector to buffer 0. - [12:12] - read-write - - - STALL - Reply with a stall (valid for both buffers). - [11:11] - read-write - - - AVAILABLE_0 - Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [10:10] - read-write - - - LENGTH_0 - The length of the data in buffer 0. - [9:0] - read-write - - - - - EP14_IN_BUFFER_CONTROL - 0x000000f0 - Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. - Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. - 0x00000000 - - - FULL_1 - Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [31:31] - read-write - - - LAST_1 - Buffer 1 is the last buffer of the transfer. - [30:30] - read-write - - - PID_1 - The data pid of buffer 1. - [29:29] - read-write - - - DOUBLE_BUFFER_ISO_OFFSET - The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. - For a non Isochronous endpoint the offset is always 64 bytes. - [28:27] - read-write - - - 128 - 0 - - - 256 - 1 - - - 512 - 2 - - - 1024 - 3 - - - - - AVAILABLE_1 - Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [26:26] - read-write - - - LENGTH_1 - The length of the data in buffer 1. - [25:16] - read-write - - - FULL_0 - Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [15:15] - read-write - - - LAST_0 - Buffer 0 is the last buffer of the transfer. - [14:14] - read-write - - - PID_0 - The data pid of buffer 0. - [13:13] - read-write - - - RESET - Reset the buffer selector to buffer 0. - [12:12] - read-write - - - STALL - Reply with a stall (valid for both buffers). - [11:11] - read-write - - - AVAILABLE_0 - Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [10:10] - read-write - - - LENGTH_0 - The length of the data in buffer 0. - [9:0] - read-write - - - - - EP14_OUT_BUFFER_CONTROL - 0x000000f4 - Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. - Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. - 0x00000000 - - - FULL_1 - Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [31:31] - read-write - - - LAST_1 - Buffer 1 is the last buffer of the transfer. - [30:30] - read-write - - - PID_1 - The data pid of buffer 1. - [29:29] - read-write - - - DOUBLE_BUFFER_ISO_OFFSET - The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. - For a non Isochronous endpoint the offset is always 64 bytes. - [28:27] - read-write - - - 128 - 0 - - - 256 - 1 - - - 512 - 2 - - - 1024 - 3 - - - - - AVAILABLE_1 - Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [26:26] - read-write - - - LENGTH_1 - The length of the data in buffer 1. - [25:16] - read-write - - - FULL_0 - Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [15:15] - read-write - - - LAST_0 - Buffer 0 is the last buffer of the transfer. - [14:14] - read-write - - - PID_0 - The data pid of buffer 0. - [13:13] - read-write - - - RESET - Reset the buffer selector to buffer 0. - [12:12] - read-write - - - STALL - Reply with a stall (valid for both buffers). - [11:11] - read-write - - - AVAILABLE_0 - Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [10:10] - read-write - - - LENGTH_0 - The length of the data in buffer 0. - [9:0] - read-write - - - - - EP15_IN_BUFFER_CONTROL - 0x000000f8 - Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. - Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. - 0x00000000 - - - FULL_1 - Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [31:31] - read-write - - - LAST_1 - Buffer 1 is the last buffer of the transfer. - [30:30] - read-write - - - PID_1 - The data pid of buffer 1. - [29:29] - read-write - - - DOUBLE_BUFFER_ISO_OFFSET - The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. - For a non Isochronous endpoint the offset is always 64 bytes. - [28:27] - read-write - - - 128 - 0 - - - 256 - 1 - - - 512 - 2 - - - 1024 - 3 - - - - - AVAILABLE_1 - Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [26:26] - read-write - - - LENGTH_1 - The length of the data in buffer 1. - [25:16] - read-write - - - FULL_0 - Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [15:15] - read-write - - - LAST_0 - Buffer 0 is the last buffer of the transfer. - [14:14] - read-write - - - PID_0 - The data pid of buffer 0. - [13:13] - read-write - - - RESET - Reset the buffer selector to buffer 0. - [12:12] - read-write - - - STALL - Reply with a stall (valid for both buffers). - [11:11] - read-write - - - AVAILABLE_0 - Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [10:10] - read-write - - - LENGTH_0 - The length of the data in buffer 0. - [9:0] - read-write - - - - - EP15_OUT_BUFFER_CONTROL - 0x000000fc - Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. - Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. - 0x00000000 - - - FULL_1 - Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [31:31] - read-write - - - LAST_1 - Buffer 1 is the last buffer of the transfer. - [30:30] - read-write - - - PID_1 - The data pid of buffer 1. - [29:29] - read-write - - - DOUBLE_BUFFER_ISO_OFFSET - The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. - For a non Isochronous endpoint the offset is always 64 bytes. - [28:27] - read-write - - - 128 - 0 - - - 256 - 1 - - - 512 - 2 - - - 1024 - 3 - - - - - AVAILABLE_1 - Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [26:26] - read-write - - - LENGTH_1 - The length of the data in buffer 1. - [25:16] - read-write - - - FULL_0 - Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [15:15] - read-write - - - LAST_0 - Buffer 0 is the last buffer of the transfer. - [14:14] - read-write - - - PID_0 - The data pid of buffer 0. - [13:13] - read-write - - - RESET - Reset the buffer selector to buffer 0. - [12:12] - read-write - - - STALL - Reply with a stall (valid for both buffers). - [11:11] - read-write - - - AVAILABLE_0 - Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [10:10] - read-write - - - LENGTH_0 - The length of the data in buffer 0. - [9:0] - read-write - - - - - - - TBMAN - Testbench manager. Allows the programmer to know what platform their software is running on. - 0x4006c000 - - 0 - 4 - registers - - - - PLATFORM - 0x00000000 - Indicates the type of platform in use - 0x00000005 - - - FPGA - Indicates the platform is an FPGA - [1:1] - read-only - - - ASIC - Indicates the platform is an ASIC - [0:0] - read-only - - - - - - - VREG_AND_CHIP_RESET - control and status for on-chip voltage regulator and chip level reset subsystem - 0x40064000 - - 0 - 12 - registers - - - - VREG - 0x00000000 - Voltage regulator control and status - 0x000000b1 - - - ROK - regulation status - 0=not in regulation, 1=in regulation - [12:12] - read-only - - - VSEL - output voltage select - 0000 to 0101 - 0.80V - 0110 - 0.85V - 0111 - 0.90V - 1000 - 0.95V - 1001 - 1.00V - 1010 - 1.05V - 1011 - 1.10V (default) - 1100 - 1.15V - 1101 - 1.20V - 1110 - 1.25V - 1111 - 1.30V - [7:4] - read-write - - - HIZ - high impedance mode select - 0=not in high impedance mode, 1=in high impedance mode - [1:1] - read-write - - - EN - enable - 0=not enabled, 1=enabled - [0:0] - read-write - - - - - BOD - 0x00000004 - brown-out detection control - 0x00000091 - - - VSEL - threshold select - 0000 - 0.473V - 0001 - 0.516V - 0010 - 0.559V - 0011 - 0.602V - 0100 - 0.645V - 0101 - 0.688V - 0110 - 0.731V - 0111 - 0.774V - 1000 - 0.817V - 1001 - 0.860V (default) - 1010 - 0.903V - 1011 - 0.946V - 1100 - 0.989V - 1101 - 1.032V - 1110 - 1.075V - 1111 - 1.118V - [7:4] - read-write - - - EN - enable - 0=not enabled, 1=enabled - [0:0] - read-write - - - - - CHIP_RESET - 0x00000008 - Chip reset control and status - 0x00000000 - - - PSM_RESTART_FLAG - This is set by psm_restart from the debugger. - Its purpose is to branch bootcode to a safe mode when the debugger has issued a psm_restart in order to recover from a boot lock-up. - In the safe mode the debugger can repair the boot code, clear this flag then reboot the processor. - [24:24] - read-write - oneToClear - - - HAD_PSM_RESTART - Last reset was from the debug port - [20:20] - read-only - - - HAD_RUN - Last reset was from the RUN pin - [16:16] - read-only - - - HAD_POR - Last reset was from the power-on reset or brown-out detection blocks - [8:8] - read-only - - - - - - - RTC - Register block to control RTC - 0x4005c000 - - 0 - 48 - registers - - - RTC_IRQ - 25 - - - - CLKDIV_M1 - 0x00000000 - Divider minus 1 for the 1 second counter. Safe to change the value when RTC is not enabled. - 0x00000000 - - - CLKDIV_M1 - [15:0] - read-write - - - - - SETUP_0 - 0x00000004 - RTC setup register 0 - 0x00000000 - - - YEAR - Year - [23:12] - read-write - - - MONTH - Month (1..12) - [11:8] - read-write - - - DAY - Day of the month (1..31) - [4:0] - read-write - - - - - SETUP_1 - 0x00000008 - RTC setup register 1 - 0x00000000 - - - DOTW - Day of the week: 1-Monday...0-Sunday ISO 8601 mod 7 - [26:24] - read-write - - - HOUR - Hours - [20:16] - read-write - - - MIN - Minutes - [13:8] - read-write - - - SEC - Seconds - [5:0] - read-write - - - - - CTRL - 0x0000000c - RTC Control and status - 0x00000000 - - - FORCE_NOTLEAPYEAR - If set, leapyear is forced off. - Useful for years divisible by 100 but not by 400 - [8:8] - read-write - - - LOAD - Load RTC - [4:4] - write-only - - - RTC_ACTIVE - RTC enabled (running) - [1:1] - read-only - - - RTC_ENABLE - Enable RTC - [0:0] - read-write - - - - - IRQ_SETUP_0 - 0x00000010 - Interrupt setup register 0 - 0x00000000 - - - MATCH_ACTIVE - [29:29] - read-only - - - MATCH_ENA - Global match enable. Don't change any other value while this one is enabled - [28:28] - read-write - - - YEAR_ENA - Enable year matching - [26:26] - read-write - - - MONTH_ENA - Enable month matching - [25:25] - read-write - - - DAY_ENA - Enable day matching - [24:24] - read-write - - - YEAR - Year - [23:12] - read-write - - - MONTH - Month (1..12) - [11:8] - read-write - - - DAY - Day of the month (1..31) - [4:0] - read-write - - - - - IRQ_SETUP_1 - 0x00000014 - Interrupt setup register 1 - 0x00000000 - - - DOTW_ENA - Enable day of the week matching - [31:31] - read-write - - - HOUR_ENA - Enable hour matching - [30:30] - read-write - - - MIN_ENA - Enable minute matching - [29:29] - read-write - - - SEC_ENA - Enable second matching - [28:28] - read-write - - - DOTW - Day of the week - [26:24] - read-write - - - HOUR - Hours - [20:16] - read-write - - - MIN - Minutes - [13:8] - read-write - - - SEC - Seconds - [5:0] - read-write - - - - - RTC_1 - 0x00000018 - RTC register 1. - 0x00000000 - - - YEAR - Year - [23:12] - read-only - - - MONTH - Month (1..12) - [11:8] - read-only - - - DAY - Day of the month (1..31) - [4:0] - read-only - - - - - RTC_0 - 0x0000001c - RTC register 0 - Read this before RTC 1! - 0x00000000 - - - DOTW - Day of the week - [26:24] - read-only - modify - - - HOUR - Hours - [20:16] - read-only - modify - - - MIN - Minutes - [13:8] - read-only - modify - - - SEC - Seconds - [5:0] - read-only - modify - - - - - INTR - 0x00000020 - Raw Interrupts - 0x00000000 - - - RTC - [0:0] - read-only - - - - - INTE - 0x00000024 - Interrupt Enable - 0x00000000 - - - RTC - [0:0] - read-write - - - - - INTF - 0x00000028 - Interrupt Force - 0x00000000 - - - RTC - [0:0] - read-write - - - - - INTS - 0x0000002c - Interrupt status after masking & forcing - 0x00000000 - - - RTC - [0:0] - read-only - - - - - - - diff --git a/lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/platform_defs.h b/lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/platform_defs.h deleted file mode 100644 index 54d9344c8c..0000000000 --- a/lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/platform_defs.h +++ /dev/null @@ -1,119 +0,0 @@ -/* - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _HARDWARE_PLATFORM_DEFS_H -#define _HARDWARE_PLATFORM_DEFS_H - -// This header is included from C and assembler - intended mostly for #defines; guard other stuff with #ifdef __ASSEMBLER__ - -#ifndef _u -#ifdef __ASSEMBLER__ -#define _u(x) x -#else -#define _u(x) x ## u -#endif -#endif - -#define NUM_CORES _u(2) -#define NUM_DMA_CHANNELS _u(12) -#define NUM_DMA_TIMERS _u(4) -#define NUM_DMA_IRQS _u(2) -#define NUM_IRQS _u(32) -#define NUM_USER_IRQS _u(6) -#define NUM_PIOS _u(2) -#define NUM_PIO_STATE_MACHINES _u(4) -#define NUM_PIO_IRQS _u(2) -#define NUM_PWM_SLICES _u(8) -#define NUM_PWM_IRQS _u(1) -#define NUM_SPIN_LOCKS _u(32) -#define NUM_UARTS _u(2) -#define NUM_I2CS _u(2) -#define NUM_SPIS _u(2) -#define NUM_GENERIC_TIMERS _u(1) -#define NUM_ALARMS _u(4) -#define ADC_BASE_PIN _u(26) -#define NUM_ADC_CHANNELS _u(5) -#define NUM_RESETS _u(24) -#define NUM_BANK0_GPIOS _u(30) -#define NUM_QSPI_GPIOS _u(6) - -#define PIO_INSTRUCTION_COUNT _u(32) - -#define USBCTRL_DPRAM_SIZE _u(4096) - -#define HAS_SIO_DIVIDER 1 -#define HAS_RP2040_RTC 1 -// PICO_CONFIG: XOSC_HZ, Crystal oscillator frequency in Hz, type=int, default=12000000, advanced=true, group=hardware_base -// NOTE: The system and USB clocks are generated from the frequency using two PLLs. -// If you override this define, or SYS_CLK_HZ/USB_CLK_HZ below, you will *also* need to add your own adjusted PLL set-up defines to -// override the defaults which live in src/rp2_common/hardware_clocks/include/hardware/clocks.h -// Please see the comments there about calculating the new PLL setting values. -#ifndef XOSC_HZ -#ifdef XOSC_KHZ -#define XOSC_HZ ((XOSC_KHZ) * _u(1000)) -#elif defined(XOSC_MHZ) -#define XOSC_HZ ((XOSC_MHZ) * _u(1000000)) -#else -#define XOSC_HZ _u(12000000) -#endif -#endif - -// PICO_CONFIG: SYS_CLK_HZ, System operating frequency in Hz, type=int, default=125000000, advanced=true, group=hardware_base -#ifndef SYS_CLK_HZ -#ifdef SYS_CLK_KHZ -#define SYS_CLK_HZ ((SYS_CLK_KHZ) * _u(1000)) -#elif defined(SYS_CLK_MHZ) -#define SYS_CLK_HZ ((SYS_CLK_MHZ) * _u(1000000)) -#else -#define SYS_CLK_HZ _u(125000000) -#endif -#endif - -// PICO_CONFIG: USB_CLK_HZ, USB clock frequency. Must be 48MHz for the USB interface to operate correctly, type=int, default=48000000, advanced=true, group=hardware_base -#ifndef USB_CLK_HZ -#ifdef USB_CLK_KHZ -#define USB_CLK_HZ ((USB_CLK_KHZ) * _u(1000)) -#elif defined(USB_CLK_MHZ) -#define USB_CLK_HZ ((USB_CLK_MHZ) * _u(1000000)) -#else -#define USB_CLK_HZ _u(48000000) -#endif -#endif - -// For backwards compatibility define XOSC_KHZ if the frequency is indeed an integer number of Khz. -#if defined(XOSC_HZ) && !defined(XOSC_KHZ) && (XOSC_HZ % 1000 == 0) -#define XOSC_KHZ (XOSC_HZ / 1000) -#endif - -// For backwards compatibility define XOSC_MHZ if the frequency is indeed an integer number of Mhz. -#if defined(XOSC_KHZ) && !defined(XOSC_MHZ) && (XOSC_KHZ % 1000 == 0) -#define XOSC_MHZ (XOSC_KHZ / 1000) -#endif - -// For backwards compatibility define SYS_CLK_KHZ if the frequency is indeed an integer number of Khz. -#if defined(SYS_CLK_HZ) && !defined(SYS_CLK_KHZ) && (SYS_CLK_HZ % 1000 == 0) -#define SYS_CLK_KHZ (SYS_CLK_HZ / 1000) -#endif - -// For backwards compatibility define SYS_CLK_MHZ if the frequency is indeed an integer number of Mhz. -#if defined(SYS_CLK_KHZ) && !defined(SYS_CLK_MHZ) && (SYS_CLK_KHZ % 1000 == 0) -#define SYS_CLK_MHZ (SYS_CLK_KHZ / 1000) -#endif - -// For backwards compatibility define USB_CLK_KHZ if the frequency is indeed an integer number of Khz. -#if defined(USB_CLK_HZ) && !defined(USB_CLK_KHZ) && (USB_CLK_HZ % 1000 == 0) -#define USB_CLK_KHZ (USB_CLK_HZ / 1000) -#endif - -// For backwards compatibility define USB_CLK_MHZ if the frequency is indeed an integer number of Mhz. -#if defined(USB_CLK_KHZ) && !defined(USB_CLK_MHZ) && (USB_CLK_KHZ % 1000 == 0) -#define USB_CLK_MHZ (USB_CLK_KHZ / 1000) -#endif - -#define FIRST_USER_IRQ (NUM_IRQS - NUM_USER_IRQS) -#define VTABLE_FIRST_IRQ 16 - -#endif diff --git a/lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/adc.h b/lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/adc.h deleted file mode 100644 index 3077f1624c..0000000000 --- a/lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/adc.h +++ /dev/null @@ -1,314 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -// ============================================================================= -// Register block : ADC -// Version : 2 -// Bus type : apb -// Description : Control and data interface to SAR ADC -// ============================================================================= -#ifndef _HARDWARE_REGS_ADC_H -#define _HARDWARE_REGS_ADC_H -// ============================================================================= -// Register : ADC_CS -// Description : ADC Control and Status -#define ADC_CS_OFFSET _u(0x00000000) -#define ADC_CS_BITS _u(0x001f770f) -#define ADC_CS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : ADC_CS_RROBIN -// Description : Round-robin sampling. 1 bit per channel. Set all bits to 0 to -// disable. -// Otherwise, the ADC will cycle through each enabled channel in a -// round-robin fashion. -// The first channel to be sampled will be the one currently -// indicated by AINSEL. -// AINSEL will be updated after each conversion with the newly- -// selected channel. -#define ADC_CS_RROBIN_RESET _u(0x00) -#define ADC_CS_RROBIN_BITS _u(0x001f0000) -#define ADC_CS_RROBIN_MSB _u(20) -#define ADC_CS_RROBIN_LSB _u(16) -#define ADC_CS_RROBIN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ADC_CS_AINSEL -// Description : Select analog mux input. Updated automatically in round-robin -// mode. -#define ADC_CS_AINSEL_RESET _u(0x0) -#define ADC_CS_AINSEL_BITS _u(0x00007000) -#define ADC_CS_AINSEL_MSB _u(14) -#define ADC_CS_AINSEL_LSB _u(12) -#define ADC_CS_AINSEL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ADC_CS_ERR_STICKY -// Description : Some past ADC conversion encountered an error. Write 1 to -// clear. -#define ADC_CS_ERR_STICKY_RESET _u(0x0) -#define ADC_CS_ERR_STICKY_BITS _u(0x00000400) -#define ADC_CS_ERR_STICKY_MSB _u(10) -#define ADC_CS_ERR_STICKY_LSB _u(10) -#define ADC_CS_ERR_STICKY_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : ADC_CS_ERR -// Description : The most recent ADC conversion encountered an error; result is -// undefined or noisy. -#define ADC_CS_ERR_RESET _u(0x0) -#define ADC_CS_ERR_BITS _u(0x00000200) -#define ADC_CS_ERR_MSB _u(9) -#define ADC_CS_ERR_LSB _u(9) -#define ADC_CS_ERR_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : ADC_CS_READY -// Description : 1 if the ADC is ready to start a new conversion. Implies any -// previous conversion has completed. -// 0 whilst conversion in progress. -#define ADC_CS_READY_RESET _u(0x0) -#define ADC_CS_READY_BITS _u(0x00000100) -#define ADC_CS_READY_MSB _u(8) -#define ADC_CS_READY_LSB _u(8) -#define ADC_CS_READY_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : ADC_CS_START_MANY -// Description : Continuously perform conversions whilst this bit is 1. A new -// conversion will start immediately after the previous finishes. -#define ADC_CS_START_MANY_RESET _u(0x0) -#define ADC_CS_START_MANY_BITS _u(0x00000008) -#define ADC_CS_START_MANY_MSB _u(3) -#define ADC_CS_START_MANY_LSB _u(3) -#define ADC_CS_START_MANY_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ADC_CS_START_ONCE -// Description : Start a single conversion. Self-clearing. Ignored if start_many -// is asserted. -#define ADC_CS_START_ONCE_RESET _u(0x0) -#define ADC_CS_START_ONCE_BITS _u(0x00000004) -#define ADC_CS_START_ONCE_MSB _u(2) -#define ADC_CS_START_ONCE_LSB _u(2) -#define ADC_CS_START_ONCE_ACCESS "SC" -// ----------------------------------------------------------------------------- -// Field : ADC_CS_TS_EN -// Description : Power on temperature sensor. 1 - enabled. 0 - disabled. -#define ADC_CS_TS_EN_RESET _u(0x0) -#define ADC_CS_TS_EN_BITS _u(0x00000002) -#define ADC_CS_TS_EN_MSB _u(1) -#define ADC_CS_TS_EN_LSB _u(1) -#define ADC_CS_TS_EN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ADC_CS_EN -// Description : Power on ADC and enable its clock. -// 1 - enabled. 0 - disabled. -#define ADC_CS_EN_RESET _u(0x0) -#define ADC_CS_EN_BITS _u(0x00000001) -#define ADC_CS_EN_MSB _u(0) -#define ADC_CS_EN_LSB _u(0) -#define ADC_CS_EN_ACCESS "RW" -// ============================================================================= -// Register : ADC_RESULT -// Description : Result of most recent ADC conversion -#define ADC_RESULT_OFFSET _u(0x00000004) -#define ADC_RESULT_BITS _u(0x00000fff) -#define ADC_RESULT_RESET _u(0x00000000) -#define ADC_RESULT_MSB _u(11) -#define ADC_RESULT_LSB _u(0) -#define ADC_RESULT_ACCESS "RO" -// ============================================================================= -// Register : ADC_FCS -// Description : FIFO control and status -#define ADC_FCS_OFFSET _u(0x00000008) -#define ADC_FCS_BITS _u(0x0f0f0f0f) -#define ADC_FCS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : ADC_FCS_THRESH -// Description : DREQ/IRQ asserted when level >= threshold -#define ADC_FCS_THRESH_RESET _u(0x0) -#define ADC_FCS_THRESH_BITS _u(0x0f000000) -#define ADC_FCS_THRESH_MSB _u(27) -#define ADC_FCS_THRESH_LSB _u(24) -#define ADC_FCS_THRESH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ADC_FCS_LEVEL -// Description : The number of conversion results currently waiting in the FIFO -#define ADC_FCS_LEVEL_RESET _u(0x0) -#define ADC_FCS_LEVEL_BITS _u(0x000f0000) -#define ADC_FCS_LEVEL_MSB _u(19) -#define ADC_FCS_LEVEL_LSB _u(16) -#define ADC_FCS_LEVEL_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : ADC_FCS_OVER -// Description : 1 if the FIFO has been overflowed. Write 1 to clear. -#define ADC_FCS_OVER_RESET _u(0x0) -#define ADC_FCS_OVER_BITS _u(0x00000800) -#define ADC_FCS_OVER_MSB _u(11) -#define ADC_FCS_OVER_LSB _u(11) -#define ADC_FCS_OVER_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : ADC_FCS_UNDER -// Description : 1 if the FIFO has been underflowed. Write 1 to clear. -#define ADC_FCS_UNDER_RESET _u(0x0) -#define ADC_FCS_UNDER_BITS _u(0x00000400) -#define ADC_FCS_UNDER_MSB _u(10) -#define ADC_FCS_UNDER_LSB _u(10) -#define ADC_FCS_UNDER_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : ADC_FCS_FULL -#define ADC_FCS_FULL_RESET _u(0x0) -#define ADC_FCS_FULL_BITS _u(0x00000200) -#define ADC_FCS_FULL_MSB _u(9) -#define ADC_FCS_FULL_LSB _u(9) -#define ADC_FCS_FULL_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : ADC_FCS_EMPTY -#define ADC_FCS_EMPTY_RESET _u(0x0) -#define ADC_FCS_EMPTY_BITS _u(0x00000100) -#define ADC_FCS_EMPTY_MSB _u(8) -#define ADC_FCS_EMPTY_LSB _u(8) -#define ADC_FCS_EMPTY_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : ADC_FCS_DREQ_EN -// Description : If 1: assert DMA requests when FIFO contains data -#define ADC_FCS_DREQ_EN_RESET _u(0x0) -#define ADC_FCS_DREQ_EN_BITS _u(0x00000008) -#define ADC_FCS_DREQ_EN_MSB _u(3) -#define ADC_FCS_DREQ_EN_LSB _u(3) -#define ADC_FCS_DREQ_EN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ADC_FCS_ERR -// Description : If 1: conversion error bit appears in the FIFO alongside the -// result -#define ADC_FCS_ERR_RESET _u(0x0) -#define ADC_FCS_ERR_BITS _u(0x00000004) -#define ADC_FCS_ERR_MSB _u(2) -#define ADC_FCS_ERR_LSB _u(2) -#define ADC_FCS_ERR_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ADC_FCS_SHIFT -// Description : If 1: FIFO results are right-shifted to be one byte in size. -// Enables DMA to byte buffers. -#define ADC_FCS_SHIFT_RESET _u(0x0) -#define ADC_FCS_SHIFT_BITS _u(0x00000002) -#define ADC_FCS_SHIFT_MSB _u(1) -#define ADC_FCS_SHIFT_LSB _u(1) -#define ADC_FCS_SHIFT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ADC_FCS_EN -// Description : If 1: write result to the FIFO after each conversion. -#define ADC_FCS_EN_RESET _u(0x0) -#define ADC_FCS_EN_BITS _u(0x00000001) -#define ADC_FCS_EN_MSB _u(0) -#define ADC_FCS_EN_LSB _u(0) -#define ADC_FCS_EN_ACCESS "RW" -// ============================================================================= -// Register : ADC_FIFO -// Description : Conversion result FIFO -#define ADC_FIFO_OFFSET _u(0x0000000c) -#define ADC_FIFO_BITS _u(0x00008fff) -#define ADC_FIFO_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : ADC_FIFO_ERR -// Description : 1 if this particular sample experienced a conversion error. -// Remains in the same location if the sample is shifted. -#define ADC_FIFO_ERR_RESET "-" -#define ADC_FIFO_ERR_BITS _u(0x00008000) -#define ADC_FIFO_ERR_MSB _u(15) -#define ADC_FIFO_ERR_LSB _u(15) -#define ADC_FIFO_ERR_ACCESS "RF" -// ----------------------------------------------------------------------------- -// Field : ADC_FIFO_VAL -#define ADC_FIFO_VAL_RESET "-" -#define ADC_FIFO_VAL_BITS _u(0x00000fff) -#define ADC_FIFO_VAL_MSB _u(11) -#define ADC_FIFO_VAL_LSB _u(0) -#define ADC_FIFO_VAL_ACCESS "RF" -// ============================================================================= -// Register : ADC_DIV -// Description : Clock divider. If non-zero, CS_START_MANY will start -// conversions -// at regular intervals rather than back-to-back. -// The divider is reset when either of these fields are written. -// Total period is 1 + INT + FRAC / 256 -#define ADC_DIV_OFFSET _u(0x00000010) -#define ADC_DIV_BITS _u(0x00ffffff) -#define ADC_DIV_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : ADC_DIV_INT -// Description : Integer part of clock divisor. -#define ADC_DIV_INT_RESET _u(0x0000) -#define ADC_DIV_INT_BITS _u(0x00ffff00) -#define ADC_DIV_INT_MSB _u(23) -#define ADC_DIV_INT_LSB _u(8) -#define ADC_DIV_INT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ADC_DIV_FRAC -// Description : Fractional part of clock divisor. First-order delta-sigma. -#define ADC_DIV_FRAC_RESET _u(0x00) -#define ADC_DIV_FRAC_BITS _u(0x000000ff) -#define ADC_DIV_FRAC_MSB _u(7) -#define ADC_DIV_FRAC_LSB _u(0) -#define ADC_DIV_FRAC_ACCESS "RW" -// ============================================================================= -// Register : ADC_INTR -// Description : Raw Interrupts -#define ADC_INTR_OFFSET _u(0x00000014) -#define ADC_INTR_BITS _u(0x00000001) -#define ADC_INTR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : ADC_INTR_FIFO -// Description : Triggered when the sample FIFO reaches a certain level. -// This level can be programmed via the FCS_THRESH field. -#define ADC_INTR_FIFO_RESET _u(0x0) -#define ADC_INTR_FIFO_BITS _u(0x00000001) -#define ADC_INTR_FIFO_MSB _u(0) -#define ADC_INTR_FIFO_LSB _u(0) -#define ADC_INTR_FIFO_ACCESS "RO" -// ============================================================================= -// Register : ADC_INTE -// Description : Interrupt Enable -#define ADC_INTE_OFFSET _u(0x00000018) -#define ADC_INTE_BITS _u(0x00000001) -#define ADC_INTE_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : ADC_INTE_FIFO -// Description : Triggered when the sample FIFO reaches a certain level. -// This level can be programmed via the FCS_THRESH field. -#define ADC_INTE_FIFO_RESET _u(0x0) -#define ADC_INTE_FIFO_BITS _u(0x00000001) -#define ADC_INTE_FIFO_MSB _u(0) -#define ADC_INTE_FIFO_LSB _u(0) -#define ADC_INTE_FIFO_ACCESS "RW" -// ============================================================================= -// Register : ADC_INTF -// Description : Interrupt Force -#define ADC_INTF_OFFSET _u(0x0000001c) -#define ADC_INTF_BITS _u(0x00000001) -#define ADC_INTF_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : ADC_INTF_FIFO -// Description : Triggered when the sample FIFO reaches a certain level. -// This level can be programmed via the FCS_THRESH field. -#define ADC_INTF_FIFO_RESET _u(0x0) -#define ADC_INTF_FIFO_BITS _u(0x00000001) -#define ADC_INTF_FIFO_MSB _u(0) -#define ADC_INTF_FIFO_LSB _u(0) -#define ADC_INTF_FIFO_ACCESS "RW" -// ============================================================================= -// Register : ADC_INTS -// Description : Interrupt status after masking & forcing -#define ADC_INTS_OFFSET _u(0x00000020) -#define ADC_INTS_BITS _u(0x00000001) -#define ADC_INTS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : ADC_INTS_FIFO -// Description : Triggered when the sample FIFO reaches a certain level. -// This level can be programmed via the FCS_THRESH field. -#define ADC_INTS_FIFO_RESET _u(0x0) -#define ADC_INTS_FIFO_BITS _u(0x00000001) -#define ADC_INTS_FIFO_MSB _u(0) -#define ADC_INTS_FIFO_LSB _u(0) -#define ADC_INTS_FIFO_ACCESS "RO" -// ============================================================================= -#endif // _HARDWARE_REGS_ADC_H - diff --git a/lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/addressmap.h b/lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/addressmap.h deleted file mode 100644 index 61da68c5be..0000000000 --- a/lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/addressmap.h +++ /dev/null @@ -1,81 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _ADDRESSMAP_H -#define _ADDRESSMAP_H - -/** - * \file rp2040/addressmap.h - */ - -#include "hardware/platform_defs.h" - -// Register address offsets for atomic RMW aliases -#define REG_ALIAS_RW_BITS (_u(0x0) << _u(12)) -#define REG_ALIAS_XOR_BITS (_u(0x1) << _u(12)) -#define REG_ALIAS_SET_BITS (_u(0x2) << _u(12)) -#define REG_ALIAS_CLR_BITS (_u(0x3) << _u(12)) - -#define ROM_BASE _u(0x00000000) -#define XIP_BASE _u(0x10000000) -#define XIP_MAIN_BASE _u(0x10000000) -#define XIP_NOALLOC_BASE _u(0x11000000) -#define XIP_NOCACHE_BASE _u(0x12000000) -#define XIP_NOCACHE_NOALLOC_BASE _u(0x13000000) -#define XIP_CTRL_BASE _u(0x14000000) -#define XIP_SRAM_BASE _u(0x15000000) -#define XIP_SRAM_END _u(0x15004000) -#define XIP_SSI_BASE _u(0x18000000) -#define SRAM_BASE _u(0x20000000) -#define SRAM_STRIPED_BASE _u(0x20000000) -#define SRAM_STRIPED_END _u(0x20040000) -#define SRAM4_BASE _u(0x20040000) -#define SRAM5_BASE _u(0x20041000) -#define SRAM_END _u(0x20042000) -#define SRAM0_BASE _u(0x21000000) -#define SRAM1_BASE _u(0x21010000) -#define SRAM2_BASE _u(0x21020000) -#define SRAM3_BASE _u(0x21030000) -#define SYSINFO_BASE _u(0x40000000) -#define SYSCFG_BASE _u(0x40004000) -#define CLOCKS_BASE _u(0x40008000) -#define RESETS_BASE _u(0x4000c000) -#define PSM_BASE _u(0x40010000) -#define IO_BANK0_BASE _u(0x40014000) -#define IO_QSPI_BASE _u(0x40018000) -#define PADS_BANK0_BASE _u(0x4001c000) -#define PADS_QSPI_BASE _u(0x40020000) -#define XOSC_BASE _u(0x40024000) -#define PLL_SYS_BASE _u(0x40028000) -#define PLL_USB_BASE _u(0x4002c000) -#define BUSCTRL_BASE _u(0x40030000) -#define UART0_BASE _u(0x40034000) -#define UART1_BASE _u(0x40038000) -#define SPI0_BASE _u(0x4003c000) -#define SPI1_BASE _u(0x40040000) -#define I2C0_BASE _u(0x40044000) -#define I2C1_BASE _u(0x40048000) -#define ADC_BASE _u(0x4004c000) -#define PWM_BASE _u(0x40050000) -#define TIMER_BASE _u(0x40054000) -#define WATCHDOG_BASE _u(0x40058000) -#define RTC_BASE _u(0x4005c000) -#define ROSC_BASE _u(0x40060000) -#define VREG_AND_CHIP_RESET_BASE _u(0x40064000) -#define TBMAN_BASE _u(0x4006c000) -#define DMA_BASE _u(0x50000000) -#define USBCTRL_DPRAM_BASE _u(0x50100000) -#define USBCTRL_BASE _u(0x50100000) -#define USBCTRL_REGS_BASE _u(0x50110000) -#define PIO0_BASE _u(0x50200000) -#define PIO1_BASE _u(0x50300000) -#define XIP_AUX_BASE _u(0x50400000) -#define SIO_BASE _u(0xd0000000) -#define PPB_BASE _u(0xe0000000) - -#endif // _ADDRESSMAP_H - diff --git a/lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/busctrl.h b/lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/busctrl.h deleted file mode 100644 index ee5f153e24..0000000000 --- a/lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/busctrl.h +++ /dev/null @@ -1,327 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -// ============================================================================= -// Register block : BUSCTRL -// Version : 1 -// Bus type : apb -// Description : Register block for busfabric control signals and performance -// counters -// ============================================================================= -#ifndef _HARDWARE_REGS_BUSCTRL_H -#define _HARDWARE_REGS_BUSCTRL_H -// ============================================================================= -// Register : BUSCTRL_BUS_PRIORITY -// Description : Set the priority of each master for bus arbitration. -#define BUSCTRL_BUS_PRIORITY_OFFSET _u(0x00000000) -#define BUSCTRL_BUS_PRIORITY_BITS _u(0x00001111) -#define BUSCTRL_BUS_PRIORITY_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : BUSCTRL_BUS_PRIORITY_DMA_W -// Description : 0 - low priority, 1 - high priority -#define BUSCTRL_BUS_PRIORITY_DMA_W_RESET _u(0x0) -#define BUSCTRL_BUS_PRIORITY_DMA_W_BITS _u(0x00001000) -#define BUSCTRL_BUS_PRIORITY_DMA_W_MSB _u(12) -#define BUSCTRL_BUS_PRIORITY_DMA_W_LSB _u(12) -#define BUSCTRL_BUS_PRIORITY_DMA_W_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : BUSCTRL_BUS_PRIORITY_DMA_R -// Description : 0 - low priority, 1 - high priority -#define BUSCTRL_BUS_PRIORITY_DMA_R_RESET _u(0x0) -#define BUSCTRL_BUS_PRIORITY_DMA_R_BITS _u(0x00000100) -#define BUSCTRL_BUS_PRIORITY_DMA_R_MSB _u(8) -#define BUSCTRL_BUS_PRIORITY_DMA_R_LSB _u(8) -#define BUSCTRL_BUS_PRIORITY_DMA_R_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : BUSCTRL_BUS_PRIORITY_PROC1 -// Description : 0 - low priority, 1 - high priority -#define BUSCTRL_BUS_PRIORITY_PROC1_RESET _u(0x0) -#define BUSCTRL_BUS_PRIORITY_PROC1_BITS _u(0x00000010) -#define BUSCTRL_BUS_PRIORITY_PROC1_MSB _u(4) -#define BUSCTRL_BUS_PRIORITY_PROC1_LSB _u(4) -#define BUSCTRL_BUS_PRIORITY_PROC1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : BUSCTRL_BUS_PRIORITY_PROC0 -// Description : 0 - low priority, 1 - high priority -#define BUSCTRL_BUS_PRIORITY_PROC0_RESET _u(0x0) -#define BUSCTRL_BUS_PRIORITY_PROC0_BITS _u(0x00000001) -#define BUSCTRL_BUS_PRIORITY_PROC0_MSB _u(0) -#define BUSCTRL_BUS_PRIORITY_PROC0_LSB _u(0) -#define BUSCTRL_BUS_PRIORITY_PROC0_ACCESS "RW" -// ============================================================================= -// Register : BUSCTRL_BUS_PRIORITY_ACK -// Description : Bus priority acknowledge -// Goes to 1 once all arbiters have registered the new global -// priority levels. -// Arbiters update their local priority when servicing a new -// nonsequential access. -// In normal circumstances this will happen almost immediately. -#define BUSCTRL_BUS_PRIORITY_ACK_OFFSET _u(0x00000004) -#define BUSCTRL_BUS_PRIORITY_ACK_BITS _u(0x00000001) -#define BUSCTRL_BUS_PRIORITY_ACK_RESET _u(0x00000000) -#define BUSCTRL_BUS_PRIORITY_ACK_MSB _u(0) -#define BUSCTRL_BUS_PRIORITY_ACK_LSB _u(0) -#define BUSCTRL_BUS_PRIORITY_ACK_ACCESS "RO" -// ============================================================================= -// Register : BUSCTRL_PERFCTR0 -// Description : Bus fabric performance counter 0 -// Busfabric saturating performance counter 0 -// Count some event signal from the busfabric arbiters. -// Write any value to clear. Select an event to count using -// PERFSEL0 -#define BUSCTRL_PERFCTR0_OFFSET _u(0x00000008) -#define BUSCTRL_PERFCTR0_BITS _u(0x00ffffff) -#define BUSCTRL_PERFCTR0_RESET _u(0x00000000) -#define BUSCTRL_PERFCTR0_MSB _u(23) -#define BUSCTRL_PERFCTR0_LSB _u(0) -#define BUSCTRL_PERFCTR0_ACCESS "WC" -// ============================================================================= -// Register : BUSCTRL_PERFSEL0 -// Description : Bus fabric performance event select for PERFCTR0 -// Select an event for PERFCTR0. Count either contested accesses, -// or all accesses, on a downstream port of the main crossbar. -// 0x00 -> apb_contested -// 0x01 -> apb -// 0x02 -> fastperi_contested -// 0x03 -> fastperi -// 0x04 -> sram5_contested -// 0x05 -> sram5 -// 0x06 -> sram4_contested -// 0x07 -> sram4 -// 0x08 -> sram3_contested -// 0x09 -> sram3 -// 0x0a -> sram2_contested -// 0x0b -> sram2 -// 0x0c -> sram1_contested -// 0x0d -> sram1 -// 0x0e -> sram0_contested -// 0x0f -> sram0 -// 0x10 -> xip_main_contested -// 0x11 -> xip_main -// 0x12 -> rom_contested -// 0x13 -> rom -#define BUSCTRL_PERFSEL0_OFFSET _u(0x0000000c) -#define BUSCTRL_PERFSEL0_BITS _u(0x0000001f) -#define BUSCTRL_PERFSEL0_RESET _u(0x0000001f) -#define BUSCTRL_PERFSEL0_MSB _u(4) -#define BUSCTRL_PERFSEL0_LSB _u(0) -#define BUSCTRL_PERFSEL0_ACCESS "RW" -#define BUSCTRL_PERFSEL0_VALUE_APB_CONTESTED _u(0x00) -#define BUSCTRL_PERFSEL0_VALUE_APB _u(0x01) -#define BUSCTRL_PERFSEL0_VALUE_FASTPERI_CONTESTED _u(0x02) -#define BUSCTRL_PERFSEL0_VALUE_FASTPERI _u(0x03) -#define BUSCTRL_PERFSEL0_VALUE_SRAM5_CONTESTED _u(0x04) -#define BUSCTRL_PERFSEL0_VALUE_SRAM5 _u(0x05) -#define BUSCTRL_PERFSEL0_VALUE_SRAM4_CONTESTED _u(0x06) -#define BUSCTRL_PERFSEL0_VALUE_SRAM4 _u(0x07) -#define BUSCTRL_PERFSEL0_VALUE_SRAM3_CONTESTED _u(0x08) -#define BUSCTRL_PERFSEL0_VALUE_SRAM3 _u(0x09) -#define BUSCTRL_PERFSEL0_VALUE_SRAM2_CONTESTED _u(0x0a) -#define BUSCTRL_PERFSEL0_VALUE_SRAM2 _u(0x0b) -#define BUSCTRL_PERFSEL0_VALUE_SRAM1_CONTESTED _u(0x0c) -#define BUSCTRL_PERFSEL0_VALUE_SRAM1 _u(0x0d) -#define BUSCTRL_PERFSEL0_VALUE_SRAM0_CONTESTED _u(0x0e) -#define BUSCTRL_PERFSEL0_VALUE_SRAM0 _u(0x0f) -#define BUSCTRL_PERFSEL0_VALUE_XIP_MAIN_CONTESTED _u(0x10) -#define BUSCTRL_PERFSEL0_VALUE_XIP_MAIN _u(0x11) -#define BUSCTRL_PERFSEL0_VALUE_ROM_CONTESTED _u(0x12) -#define BUSCTRL_PERFSEL0_VALUE_ROM _u(0x13) -// ============================================================================= -// Register : BUSCTRL_PERFCTR1 -// Description : Bus fabric performance counter 1 -// Busfabric saturating performance counter 1 -// Count some event signal from the busfabric arbiters. -// Write any value to clear. Select an event to count using -// PERFSEL1 -#define BUSCTRL_PERFCTR1_OFFSET _u(0x00000010) -#define BUSCTRL_PERFCTR1_BITS _u(0x00ffffff) -#define BUSCTRL_PERFCTR1_RESET _u(0x00000000) -#define BUSCTRL_PERFCTR1_MSB _u(23) -#define BUSCTRL_PERFCTR1_LSB _u(0) -#define BUSCTRL_PERFCTR1_ACCESS "WC" -// ============================================================================= -// Register : BUSCTRL_PERFSEL1 -// Description : Bus fabric performance event select for PERFCTR1 -// Select an event for PERFCTR1. Count either contested accesses, -// or all accesses, on a downstream port of the main crossbar. -// 0x00 -> apb_contested -// 0x01 -> apb -// 0x02 -> fastperi_contested -// 0x03 -> fastperi -// 0x04 -> sram5_contested -// 0x05 -> sram5 -// 0x06 -> sram4_contested -// 0x07 -> sram4 -// 0x08 -> sram3_contested -// 0x09 -> sram3 -// 0x0a -> sram2_contested -// 0x0b -> sram2 -// 0x0c -> sram1_contested -// 0x0d -> sram1 -// 0x0e -> sram0_contested -// 0x0f -> sram0 -// 0x10 -> xip_main_contested -// 0x11 -> xip_main -// 0x12 -> rom_contested -// 0x13 -> rom -#define BUSCTRL_PERFSEL1_OFFSET _u(0x00000014) -#define BUSCTRL_PERFSEL1_BITS _u(0x0000001f) -#define BUSCTRL_PERFSEL1_RESET _u(0x0000001f) -#define BUSCTRL_PERFSEL1_MSB _u(4) -#define BUSCTRL_PERFSEL1_LSB _u(0) -#define BUSCTRL_PERFSEL1_ACCESS "RW" -#define BUSCTRL_PERFSEL1_VALUE_APB_CONTESTED _u(0x00) -#define BUSCTRL_PERFSEL1_VALUE_APB _u(0x01) -#define BUSCTRL_PERFSEL1_VALUE_FASTPERI_CONTESTED _u(0x02) -#define BUSCTRL_PERFSEL1_VALUE_FASTPERI _u(0x03) -#define BUSCTRL_PERFSEL1_VALUE_SRAM5_CONTESTED _u(0x04) -#define BUSCTRL_PERFSEL1_VALUE_SRAM5 _u(0x05) -#define BUSCTRL_PERFSEL1_VALUE_SRAM4_CONTESTED _u(0x06) -#define BUSCTRL_PERFSEL1_VALUE_SRAM4 _u(0x07) -#define BUSCTRL_PERFSEL1_VALUE_SRAM3_CONTESTED _u(0x08) -#define BUSCTRL_PERFSEL1_VALUE_SRAM3 _u(0x09) -#define BUSCTRL_PERFSEL1_VALUE_SRAM2_CONTESTED _u(0x0a) -#define BUSCTRL_PERFSEL1_VALUE_SRAM2 _u(0x0b) -#define BUSCTRL_PERFSEL1_VALUE_SRAM1_CONTESTED _u(0x0c) -#define BUSCTRL_PERFSEL1_VALUE_SRAM1 _u(0x0d) -#define BUSCTRL_PERFSEL1_VALUE_SRAM0_CONTESTED _u(0x0e) -#define BUSCTRL_PERFSEL1_VALUE_SRAM0 _u(0x0f) -#define BUSCTRL_PERFSEL1_VALUE_XIP_MAIN_CONTESTED _u(0x10) -#define BUSCTRL_PERFSEL1_VALUE_XIP_MAIN _u(0x11) -#define BUSCTRL_PERFSEL1_VALUE_ROM_CONTESTED _u(0x12) -#define BUSCTRL_PERFSEL1_VALUE_ROM _u(0x13) -// ============================================================================= -// Register : BUSCTRL_PERFCTR2 -// Description : Bus fabric performance counter 2 -// Busfabric saturating performance counter 2 -// Count some event signal from the busfabric arbiters. -// Write any value to clear. Select an event to count using -// PERFSEL2 -#define BUSCTRL_PERFCTR2_OFFSET _u(0x00000018) -#define BUSCTRL_PERFCTR2_BITS _u(0x00ffffff) -#define BUSCTRL_PERFCTR2_RESET _u(0x00000000) -#define BUSCTRL_PERFCTR2_MSB _u(23) -#define BUSCTRL_PERFCTR2_LSB _u(0) -#define BUSCTRL_PERFCTR2_ACCESS "WC" -// ============================================================================= -// Register : BUSCTRL_PERFSEL2 -// Description : Bus fabric performance event select for PERFCTR2 -// Select an event for PERFCTR2. Count either contested accesses, -// or all accesses, on a downstream port of the main crossbar. -// 0x00 -> apb_contested -// 0x01 -> apb -// 0x02 -> fastperi_contested -// 0x03 -> fastperi -// 0x04 -> sram5_contested -// 0x05 -> sram5 -// 0x06 -> sram4_contested -// 0x07 -> sram4 -// 0x08 -> sram3_contested -// 0x09 -> sram3 -// 0x0a -> sram2_contested -// 0x0b -> sram2 -// 0x0c -> sram1_contested -// 0x0d -> sram1 -// 0x0e -> sram0_contested -// 0x0f -> sram0 -// 0x10 -> xip_main_contested -// 0x11 -> xip_main -// 0x12 -> rom_contested -// 0x13 -> rom -#define BUSCTRL_PERFSEL2_OFFSET _u(0x0000001c) -#define BUSCTRL_PERFSEL2_BITS _u(0x0000001f) -#define BUSCTRL_PERFSEL2_RESET _u(0x0000001f) -#define BUSCTRL_PERFSEL2_MSB _u(4) -#define BUSCTRL_PERFSEL2_LSB _u(0) -#define BUSCTRL_PERFSEL2_ACCESS "RW" -#define BUSCTRL_PERFSEL2_VALUE_APB_CONTESTED _u(0x00) -#define BUSCTRL_PERFSEL2_VALUE_APB _u(0x01) -#define BUSCTRL_PERFSEL2_VALUE_FASTPERI_CONTESTED _u(0x02) -#define BUSCTRL_PERFSEL2_VALUE_FASTPERI _u(0x03) -#define BUSCTRL_PERFSEL2_VALUE_SRAM5_CONTESTED _u(0x04) -#define BUSCTRL_PERFSEL2_VALUE_SRAM5 _u(0x05) -#define BUSCTRL_PERFSEL2_VALUE_SRAM4_CONTESTED _u(0x06) -#define BUSCTRL_PERFSEL2_VALUE_SRAM4 _u(0x07) -#define BUSCTRL_PERFSEL2_VALUE_SRAM3_CONTESTED _u(0x08) -#define BUSCTRL_PERFSEL2_VALUE_SRAM3 _u(0x09) -#define BUSCTRL_PERFSEL2_VALUE_SRAM2_CONTESTED _u(0x0a) -#define BUSCTRL_PERFSEL2_VALUE_SRAM2 _u(0x0b) -#define BUSCTRL_PERFSEL2_VALUE_SRAM1_CONTESTED _u(0x0c) -#define BUSCTRL_PERFSEL2_VALUE_SRAM1 _u(0x0d) -#define BUSCTRL_PERFSEL2_VALUE_SRAM0_CONTESTED _u(0x0e) -#define BUSCTRL_PERFSEL2_VALUE_SRAM0 _u(0x0f) -#define BUSCTRL_PERFSEL2_VALUE_XIP_MAIN_CONTESTED _u(0x10) -#define BUSCTRL_PERFSEL2_VALUE_XIP_MAIN _u(0x11) -#define BUSCTRL_PERFSEL2_VALUE_ROM_CONTESTED _u(0x12) -#define BUSCTRL_PERFSEL2_VALUE_ROM _u(0x13) -// ============================================================================= -// Register : BUSCTRL_PERFCTR3 -// Description : Bus fabric performance counter 3 -// Busfabric saturating performance counter 3 -// Count some event signal from the busfabric arbiters. -// Write any value to clear. Select an event to count using -// PERFSEL3 -#define BUSCTRL_PERFCTR3_OFFSET _u(0x00000020) -#define BUSCTRL_PERFCTR3_BITS _u(0x00ffffff) -#define BUSCTRL_PERFCTR3_RESET _u(0x00000000) -#define BUSCTRL_PERFCTR3_MSB _u(23) -#define BUSCTRL_PERFCTR3_LSB _u(0) -#define BUSCTRL_PERFCTR3_ACCESS "WC" -// ============================================================================= -// Register : BUSCTRL_PERFSEL3 -// Description : Bus fabric performance event select for PERFCTR3 -// Select an event for PERFCTR3. Count either contested accesses, -// or all accesses, on a downstream port of the main crossbar. -// 0x00 -> apb_contested -// 0x01 -> apb -// 0x02 -> fastperi_contested -// 0x03 -> fastperi -// 0x04 -> sram5_contested -// 0x05 -> sram5 -// 0x06 -> sram4_contested -// 0x07 -> sram4 -// 0x08 -> sram3_contested -// 0x09 -> sram3 -// 0x0a -> sram2_contested -// 0x0b -> sram2 -// 0x0c -> sram1_contested -// 0x0d -> sram1 -// 0x0e -> sram0_contested -// 0x0f -> sram0 -// 0x10 -> xip_main_contested -// 0x11 -> xip_main -// 0x12 -> rom_contested -// 0x13 -> rom -#define BUSCTRL_PERFSEL3_OFFSET _u(0x00000024) -#define BUSCTRL_PERFSEL3_BITS _u(0x0000001f) -#define BUSCTRL_PERFSEL3_RESET _u(0x0000001f) -#define BUSCTRL_PERFSEL3_MSB _u(4) -#define BUSCTRL_PERFSEL3_LSB _u(0) -#define BUSCTRL_PERFSEL3_ACCESS "RW" -#define BUSCTRL_PERFSEL3_VALUE_APB_CONTESTED _u(0x00) -#define BUSCTRL_PERFSEL3_VALUE_APB _u(0x01) -#define BUSCTRL_PERFSEL3_VALUE_FASTPERI_CONTESTED _u(0x02) -#define BUSCTRL_PERFSEL3_VALUE_FASTPERI _u(0x03) -#define BUSCTRL_PERFSEL3_VALUE_SRAM5_CONTESTED _u(0x04) -#define BUSCTRL_PERFSEL3_VALUE_SRAM5 _u(0x05) -#define BUSCTRL_PERFSEL3_VALUE_SRAM4_CONTESTED _u(0x06) -#define BUSCTRL_PERFSEL3_VALUE_SRAM4 _u(0x07) -#define BUSCTRL_PERFSEL3_VALUE_SRAM3_CONTESTED _u(0x08) -#define BUSCTRL_PERFSEL3_VALUE_SRAM3 _u(0x09) -#define BUSCTRL_PERFSEL3_VALUE_SRAM2_CONTESTED _u(0x0a) -#define BUSCTRL_PERFSEL3_VALUE_SRAM2 _u(0x0b) -#define BUSCTRL_PERFSEL3_VALUE_SRAM1_CONTESTED _u(0x0c) -#define BUSCTRL_PERFSEL3_VALUE_SRAM1 _u(0x0d) -#define BUSCTRL_PERFSEL3_VALUE_SRAM0_CONTESTED _u(0x0e) -#define BUSCTRL_PERFSEL3_VALUE_SRAM0 _u(0x0f) -#define BUSCTRL_PERFSEL3_VALUE_XIP_MAIN_CONTESTED _u(0x10) -#define BUSCTRL_PERFSEL3_VALUE_XIP_MAIN _u(0x11) -#define BUSCTRL_PERFSEL3_VALUE_ROM_CONTESTED _u(0x12) -#define BUSCTRL_PERFSEL3_VALUE_ROM _u(0x13) -// ============================================================================= -#endif // _HARDWARE_REGS_BUSCTRL_H - diff --git a/lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/clocks.h b/lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/clocks.h deleted file mode 100644 index 7c604b9b63..0000000000 --- a/lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/clocks.h +++ /dev/null @@ -1,2262 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -// ============================================================================= -// Register block : CLOCKS -// Version : 1 -// Bus type : apb -// ============================================================================= -#ifndef _HARDWARE_REGS_CLOCKS_H -#define _HARDWARE_REGS_CLOCKS_H -// ============================================================================= -// Register : CLOCKS_CLK_GPOUT0_CTRL -// Description : Clock control, can be changed on-the-fly (except for auxsrc) -#define CLOCKS_CLK_GPOUT0_CTRL_OFFSET _u(0x00000000) -#define CLOCKS_CLK_GPOUT0_CTRL_BITS _u(0x00131de0) -#define CLOCKS_CLK_GPOUT0_CTRL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_GPOUT0_CTRL_NUDGE -// Description : An edge on this signal shifts the phase of the output by 1 -// cycle of the input clock -// This can be done at any time -#define CLOCKS_CLK_GPOUT0_CTRL_NUDGE_RESET _u(0x0) -#define CLOCKS_CLK_GPOUT0_CTRL_NUDGE_BITS _u(0x00100000) -#define CLOCKS_CLK_GPOUT0_CTRL_NUDGE_MSB _u(20) -#define CLOCKS_CLK_GPOUT0_CTRL_NUDGE_LSB _u(20) -#define CLOCKS_CLK_GPOUT0_CTRL_NUDGE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_GPOUT0_CTRL_PHASE -// Description : This delays the enable signal by up to 3 cycles of the input -// clock -// This must be set before the clock is enabled to have any effect -#define CLOCKS_CLK_GPOUT0_CTRL_PHASE_RESET _u(0x0) -#define CLOCKS_CLK_GPOUT0_CTRL_PHASE_BITS _u(0x00030000) -#define CLOCKS_CLK_GPOUT0_CTRL_PHASE_MSB _u(17) -#define CLOCKS_CLK_GPOUT0_CTRL_PHASE_LSB _u(16) -#define CLOCKS_CLK_GPOUT0_CTRL_PHASE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_GPOUT0_CTRL_DC50 -// Description : Enables duty cycle correction for odd divisors -#define CLOCKS_CLK_GPOUT0_CTRL_DC50_RESET _u(0x0) -#define CLOCKS_CLK_GPOUT0_CTRL_DC50_BITS _u(0x00001000) -#define CLOCKS_CLK_GPOUT0_CTRL_DC50_MSB _u(12) -#define CLOCKS_CLK_GPOUT0_CTRL_DC50_LSB _u(12) -#define CLOCKS_CLK_GPOUT0_CTRL_DC50_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_GPOUT0_CTRL_ENABLE -// Description : Starts and stops the clock generator cleanly -#define CLOCKS_CLK_GPOUT0_CTRL_ENABLE_RESET _u(0x0) -#define CLOCKS_CLK_GPOUT0_CTRL_ENABLE_BITS _u(0x00000800) -#define CLOCKS_CLK_GPOUT0_CTRL_ENABLE_MSB _u(11) -#define CLOCKS_CLK_GPOUT0_CTRL_ENABLE_LSB _u(11) -#define CLOCKS_CLK_GPOUT0_CTRL_ENABLE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_GPOUT0_CTRL_KILL -// Description : Asynchronously kills the clock generator -#define CLOCKS_CLK_GPOUT0_CTRL_KILL_RESET _u(0x0) -#define CLOCKS_CLK_GPOUT0_CTRL_KILL_BITS _u(0x00000400) -#define CLOCKS_CLK_GPOUT0_CTRL_KILL_MSB _u(10) -#define CLOCKS_CLK_GPOUT0_CTRL_KILL_LSB _u(10) -#define CLOCKS_CLK_GPOUT0_CTRL_KILL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_GPOUT0_CTRL_AUXSRC -// Description : Selects the auxiliary clock source, will glitch when switching -// 0x0 -> clksrc_pll_sys -// 0x1 -> clksrc_gpin0 -// 0x2 -> clksrc_gpin1 -// 0x3 -> clksrc_pll_usb -// 0x4 -> rosc_clksrc -// 0x5 -> xosc_clksrc -// 0x6 -> clk_sys -// 0x7 -> clk_usb -// 0x8 -> clk_adc -// 0x9 -> clk_rtc -// 0xa -> clk_ref -#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_RESET _u(0x0) -#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_BITS _u(0x000001e0) -#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_MSB _u(8) -#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_LSB _u(5) -#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_ACCESS "RW" -#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS _u(0x0) -#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 _u(0x1) -#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 _u(0x2) -#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB _u(0x3) -#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_ROSC_CLKSRC _u(0x4) -#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_XOSC_CLKSRC _u(0x5) -#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLK_SYS _u(0x6) -#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLK_USB _u(0x7) -#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLK_ADC _u(0x8) -#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLK_RTC _u(0x9) -#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLK_REF _u(0xa) -// ============================================================================= -// Register : CLOCKS_CLK_GPOUT0_DIV -// Description : Clock divisor, can be changed on-the-fly -#define CLOCKS_CLK_GPOUT0_DIV_OFFSET _u(0x00000004) -#define CLOCKS_CLK_GPOUT0_DIV_BITS _u(0xffffffff) -#define CLOCKS_CLK_GPOUT0_DIV_RESET _u(0x00000100) -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_GPOUT0_DIV_INT -// Description : Integer component of the divisor, 0 -> divide by 2^16 -#define CLOCKS_CLK_GPOUT0_DIV_INT_RESET _u(0x000001) -#define CLOCKS_CLK_GPOUT0_DIV_INT_BITS _u(0xffffff00) -#define CLOCKS_CLK_GPOUT0_DIV_INT_MSB _u(31) -#define CLOCKS_CLK_GPOUT0_DIV_INT_LSB _u(8) -#define CLOCKS_CLK_GPOUT0_DIV_INT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_GPOUT0_DIV_FRAC -// Description : Fractional component of the divisor -#define CLOCKS_CLK_GPOUT0_DIV_FRAC_RESET _u(0x00) -#define CLOCKS_CLK_GPOUT0_DIV_FRAC_BITS _u(0x000000ff) -#define CLOCKS_CLK_GPOUT0_DIV_FRAC_MSB _u(7) -#define CLOCKS_CLK_GPOUT0_DIV_FRAC_LSB _u(0) -#define CLOCKS_CLK_GPOUT0_DIV_FRAC_ACCESS "RW" -// ============================================================================= -// Register : CLOCKS_CLK_GPOUT0_SELECTED -// Description : Indicates which SRC is currently selected by the glitchless mux -// (one-hot). -// This slice does not have a glitchless mux (only the AUX_SRC -// field is present, not SRC) so this register is hardwired to -// 0x1. -#define CLOCKS_CLK_GPOUT0_SELECTED_OFFSET _u(0x00000008) -#define CLOCKS_CLK_GPOUT0_SELECTED_BITS _u(0xffffffff) -#define CLOCKS_CLK_GPOUT0_SELECTED_RESET _u(0x00000001) -#define CLOCKS_CLK_GPOUT0_SELECTED_MSB _u(31) -#define CLOCKS_CLK_GPOUT0_SELECTED_LSB _u(0) -#define CLOCKS_CLK_GPOUT0_SELECTED_ACCESS "RO" -// ============================================================================= -// Register : CLOCKS_CLK_GPOUT1_CTRL -// Description : Clock control, can be changed on-the-fly (except for auxsrc) -#define CLOCKS_CLK_GPOUT1_CTRL_OFFSET _u(0x0000000c) -#define CLOCKS_CLK_GPOUT1_CTRL_BITS _u(0x00131de0) -#define CLOCKS_CLK_GPOUT1_CTRL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_GPOUT1_CTRL_NUDGE -// Description : An edge on this signal shifts the phase of the output by 1 -// cycle of the input clock -// This can be done at any time -#define CLOCKS_CLK_GPOUT1_CTRL_NUDGE_RESET _u(0x0) -#define CLOCKS_CLK_GPOUT1_CTRL_NUDGE_BITS _u(0x00100000) -#define CLOCKS_CLK_GPOUT1_CTRL_NUDGE_MSB _u(20) -#define CLOCKS_CLK_GPOUT1_CTRL_NUDGE_LSB _u(20) -#define CLOCKS_CLK_GPOUT1_CTRL_NUDGE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_GPOUT1_CTRL_PHASE -// Description : This delays the enable signal by up to 3 cycles of the input -// clock -// This must be set before the clock is enabled to have any effect -#define CLOCKS_CLK_GPOUT1_CTRL_PHASE_RESET _u(0x0) -#define CLOCKS_CLK_GPOUT1_CTRL_PHASE_BITS _u(0x00030000) -#define CLOCKS_CLK_GPOUT1_CTRL_PHASE_MSB _u(17) -#define CLOCKS_CLK_GPOUT1_CTRL_PHASE_LSB _u(16) -#define CLOCKS_CLK_GPOUT1_CTRL_PHASE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_GPOUT1_CTRL_DC50 -// Description : Enables duty cycle correction for odd divisors -#define CLOCKS_CLK_GPOUT1_CTRL_DC50_RESET _u(0x0) -#define CLOCKS_CLK_GPOUT1_CTRL_DC50_BITS _u(0x00001000) -#define CLOCKS_CLK_GPOUT1_CTRL_DC50_MSB _u(12) -#define CLOCKS_CLK_GPOUT1_CTRL_DC50_LSB _u(12) -#define CLOCKS_CLK_GPOUT1_CTRL_DC50_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_GPOUT1_CTRL_ENABLE -// Description : Starts and stops the clock generator cleanly -#define CLOCKS_CLK_GPOUT1_CTRL_ENABLE_RESET _u(0x0) -#define CLOCKS_CLK_GPOUT1_CTRL_ENABLE_BITS _u(0x00000800) -#define CLOCKS_CLK_GPOUT1_CTRL_ENABLE_MSB _u(11) -#define CLOCKS_CLK_GPOUT1_CTRL_ENABLE_LSB _u(11) -#define CLOCKS_CLK_GPOUT1_CTRL_ENABLE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_GPOUT1_CTRL_KILL -// Description : Asynchronously kills the clock generator -#define CLOCKS_CLK_GPOUT1_CTRL_KILL_RESET _u(0x0) -#define CLOCKS_CLK_GPOUT1_CTRL_KILL_BITS _u(0x00000400) -#define CLOCKS_CLK_GPOUT1_CTRL_KILL_MSB _u(10) -#define CLOCKS_CLK_GPOUT1_CTRL_KILL_LSB _u(10) -#define CLOCKS_CLK_GPOUT1_CTRL_KILL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_GPOUT1_CTRL_AUXSRC -// Description : Selects the auxiliary clock source, will glitch when switching -// 0x0 -> clksrc_pll_sys -// 0x1 -> clksrc_gpin0 -// 0x2 -> clksrc_gpin1 -// 0x3 -> clksrc_pll_usb -// 0x4 -> rosc_clksrc -// 0x5 -> xosc_clksrc -// 0x6 -> clk_sys -// 0x7 -> clk_usb -// 0x8 -> clk_adc -// 0x9 -> clk_rtc -// 0xa -> clk_ref -#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_RESET _u(0x0) -#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_BITS _u(0x000001e0) -#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_MSB _u(8) -#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_LSB _u(5) -#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_ACCESS "RW" -#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS _u(0x0) -#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 _u(0x1) -#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 _u(0x2) -#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB _u(0x3) -#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_ROSC_CLKSRC _u(0x4) -#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_XOSC_CLKSRC _u(0x5) -#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLK_SYS _u(0x6) -#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLK_USB _u(0x7) -#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLK_ADC _u(0x8) -#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLK_RTC _u(0x9) -#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLK_REF _u(0xa) -// ============================================================================= -// Register : CLOCKS_CLK_GPOUT1_DIV -// Description : Clock divisor, can be changed on-the-fly -#define CLOCKS_CLK_GPOUT1_DIV_OFFSET _u(0x00000010) -#define CLOCKS_CLK_GPOUT1_DIV_BITS _u(0xffffffff) -#define CLOCKS_CLK_GPOUT1_DIV_RESET _u(0x00000100) -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_GPOUT1_DIV_INT -// Description : Integer component of the divisor, 0 -> divide by 2^16 -#define CLOCKS_CLK_GPOUT1_DIV_INT_RESET _u(0x000001) -#define CLOCKS_CLK_GPOUT1_DIV_INT_BITS _u(0xffffff00) -#define CLOCKS_CLK_GPOUT1_DIV_INT_MSB _u(31) -#define CLOCKS_CLK_GPOUT1_DIV_INT_LSB _u(8) -#define CLOCKS_CLK_GPOUT1_DIV_INT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_GPOUT1_DIV_FRAC -// Description : Fractional component of the divisor -#define CLOCKS_CLK_GPOUT1_DIV_FRAC_RESET _u(0x00) -#define CLOCKS_CLK_GPOUT1_DIV_FRAC_BITS _u(0x000000ff) -#define CLOCKS_CLK_GPOUT1_DIV_FRAC_MSB _u(7) -#define CLOCKS_CLK_GPOUT1_DIV_FRAC_LSB _u(0) -#define CLOCKS_CLK_GPOUT1_DIV_FRAC_ACCESS "RW" -// ============================================================================= -// Register : CLOCKS_CLK_GPOUT1_SELECTED -// Description : Indicates which SRC is currently selected by the glitchless mux -// (one-hot). -// This slice does not have a glitchless mux (only the AUX_SRC -// field is present, not SRC) so this register is hardwired to -// 0x1. -#define CLOCKS_CLK_GPOUT1_SELECTED_OFFSET _u(0x00000014) -#define CLOCKS_CLK_GPOUT1_SELECTED_BITS _u(0xffffffff) -#define CLOCKS_CLK_GPOUT1_SELECTED_RESET _u(0x00000001) -#define CLOCKS_CLK_GPOUT1_SELECTED_MSB _u(31) -#define CLOCKS_CLK_GPOUT1_SELECTED_LSB _u(0) -#define CLOCKS_CLK_GPOUT1_SELECTED_ACCESS "RO" -// ============================================================================= -// Register : CLOCKS_CLK_GPOUT2_CTRL -// Description : Clock control, can be changed on-the-fly (except for auxsrc) -#define CLOCKS_CLK_GPOUT2_CTRL_OFFSET _u(0x00000018) -#define CLOCKS_CLK_GPOUT2_CTRL_BITS _u(0x00131de0) -#define CLOCKS_CLK_GPOUT2_CTRL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_GPOUT2_CTRL_NUDGE -// Description : An edge on this signal shifts the phase of the output by 1 -// cycle of the input clock -// This can be done at any time -#define CLOCKS_CLK_GPOUT2_CTRL_NUDGE_RESET _u(0x0) -#define CLOCKS_CLK_GPOUT2_CTRL_NUDGE_BITS _u(0x00100000) -#define CLOCKS_CLK_GPOUT2_CTRL_NUDGE_MSB _u(20) -#define CLOCKS_CLK_GPOUT2_CTRL_NUDGE_LSB _u(20) -#define CLOCKS_CLK_GPOUT2_CTRL_NUDGE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_GPOUT2_CTRL_PHASE -// Description : This delays the enable signal by up to 3 cycles of the input -// clock -// This must be set before the clock is enabled to have any effect -#define CLOCKS_CLK_GPOUT2_CTRL_PHASE_RESET _u(0x0) -#define CLOCKS_CLK_GPOUT2_CTRL_PHASE_BITS _u(0x00030000) -#define CLOCKS_CLK_GPOUT2_CTRL_PHASE_MSB _u(17) -#define CLOCKS_CLK_GPOUT2_CTRL_PHASE_LSB _u(16) -#define CLOCKS_CLK_GPOUT2_CTRL_PHASE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_GPOUT2_CTRL_DC50 -// Description : Enables duty cycle correction for odd divisors -#define CLOCKS_CLK_GPOUT2_CTRL_DC50_RESET _u(0x0) -#define CLOCKS_CLK_GPOUT2_CTRL_DC50_BITS _u(0x00001000) -#define CLOCKS_CLK_GPOUT2_CTRL_DC50_MSB _u(12) -#define CLOCKS_CLK_GPOUT2_CTRL_DC50_LSB _u(12) -#define CLOCKS_CLK_GPOUT2_CTRL_DC50_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_GPOUT2_CTRL_ENABLE -// Description : Starts and stops the clock generator cleanly -#define CLOCKS_CLK_GPOUT2_CTRL_ENABLE_RESET _u(0x0) -#define CLOCKS_CLK_GPOUT2_CTRL_ENABLE_BITS _u(0x00000800) -#define CLOCKS_CLK_GPOUT2_CTRL_ENABLE_MSB _u(11) -#define CLOCKS_CLK_GPOUT2_CTRL_ENABLE_LSB _u(11) -#define CLOCKS_CLK_GPOUT2_CTRL_ENABLE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_GPOUT2_CTRL_KILL -// Description : Asynchronously kills the clock generator -#define CLOCKS_CLK_GPOUT2_CTRL_KILL_RESET _u(0x0) -#define CLOCKS_CLK_GPOUT2_CTRL_KILL_BITS _u(0x00000400) -#define CLOCKS_CLK_GPOUT2_CTRL_KILL_MSB _u(10) -#define CLOCKS_CLK_GPOUT2_CTRL_KILL_LSB _u(10) -#define CLOCKS_CLK_GPOUT2_CTRL_KILL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_GPOUT2_CTRL_AUXSRC -// Description : Selects the auxiliary clock source, will glitch when switching -// 0x0 -> clksrc_pll_sys -// 0x1 -> clksrc_gpin0 -// 0x2 -> clksrc_gpin1 -// 0x3 -> clksrc_pll_usb -// 0x4 -> rosc_clksrc_ph -// 0x5 -> xosc_clksrc -// 0x6 -> clk_sys -// 0x7 -> clk_usb -// 0x8 -> clk_adc -// 0x9 -> clk_rtc -// 0xa -> clk_ref -#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_RESET _u(0x0) -#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_BITS _u(0x000001e0) -#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_MSB _u(8) -#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_LSB _u(5) -#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_ACCESS "RW" -#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS _u(0x0) -#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 _u(0x1) -#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 _u(0x2) -#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB _u(0x3) -#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH _u(0x4) -#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_XOSC_CLKSRC _u(0x5) -#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLK_SYS _u(0x6) -#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLK_USB _u(0x7) -#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLK_ADC _u(0x8) -#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLK_RTC _u(0x9) -#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLK_REF _u(0xa) -// ============================================================================= -// Register : CLOCKS_CLK_GPOUT2_DIV -// Description : Clock divisor, can be changed on-the-fly -#define CLOCKS_CLK_GPOUT2_DIV_OFFSET _u(0x0000001c) -#define CLOCKS_CLK_GPOUT2_DIV_BITS _u(0xffffffff) -#define CLOCKS_CLK_GPOUT2_DIV_RESET _u(0x00000100) -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_GPOUT2_DIV_INT -// Description : Integer component of the divisor, 0 -> divide by 2^16 -#define CLOCKS_CLK_GPOUT2_DIV_INT_RESET _u(0x000001) -#define CLOCKS_CLK_GPOUT2_DIV_INT_BITS _u(0xffffff00) -#define CLOCKS_CLK_GPOUT2_DIV_INT_MSB _u(31) -#define CLOCKS_CLK_GPOUT2_DIV_INT_LSB _u(8) -#define CLOCKS_CLK_GPOUT2_DIV_INT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_GPOUT2_DIV_FRAC -// Description : Fractional component of the divisor -#define CLOCKS_CLK_GPOUT2_DIV_FRAC_RESET _u(0x00) -#define CLOCKS_CLK_GPOUT2_DIV_FRAC_BITS _u(0x000000ff) -#define CLOCKS_CLK_GPOUT2_DIV_FRAC_MSB _u(7) -#define CLOCKS_CLK_GPOUT2_DIV_FRAC_LSB _u(0) -#define CLOCKS_CLK_GPOUT2_DIV_FRAC_ACCESS "RW" -// ============================================================================= -// Register : CLOCKS_CLK_GPOUT2_SELECTED -// Description : Indicates which SRC is currently selected by the glitchless mux -// (one-hot). -// This slice does not have a glitchless mux (only the AUX_SRC -// field is present, not SRC) so this register is hardwired to -// 0x1. -#define CLOCKS_CLK_GPOUT2_SELECTED_OFFSET _u(0x00000020) -#define CLOCKS_CLK_GPOUT2_SELECTED_BITS _u(0xffffffff) -#define CLOCKS_CLK_GPOUT2_SELECTED_RESET _u(0x00000001) -#define CLOCKS_CLK_GPOUT2_SELECTED_MSB _u(31) -#define CLOCKS_CLK_GPOUT2_SELECTED_LSB _u(0) -#define CLOCKS_CLK_GPOUT2_SELECTED_ACCESS "RO" -// ============================================================================= -// Register : CLOCKS_CLK_GPOUT3_CTRL -// Description : Clock control, can be changed on-the-fly (except for auxsrc) -#define CLOCKS_CLK_GPOUT3_CTRL_OFFSET _u(0x00000024) -#define CLOCKS_CLK_GPOUT3_CTRL_BITS _u(0x00131de0) -#define CLOCKS_CLK_GPOUT3_CTRL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_GPOUT3_CTRL_NUDGE -// Description : An edge on this signal shifts the phase of the output by 1 -// cycle of the input clock -// This can be done at any time -#define CLOCKS_CLK_GPOUT3_CTRL_NUDGE_RESET _u(0x0) -#define CLOCKS_CLK_GPOUT3_CTRL_NUDGE_BITS _u(0x00100000) -#define CLOCKS_CLK_GPOUT3_CTRL_NUDGE_MSB _u(20) -#define CLOCKS_CLK_GPOUT3_CTRL_NUDGE_LSB _u(20) -#define CLOCKS_CLK_GPOUT3_CTRL_NUDGE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_GPOUT3_CTRL_PHASE -// Description : This delays the enable signal by up to 3 cycles of the input -// clock -// This must be set before the clock is enabled to have any effect -#define CLOCKS_CLK_GPOUT3_CTRL_PHASE_RESET _u(0x0) -#define CLOCKS_CLK_GPOUT3_CTRL_PHASE_BITS _u(0x00030000) -#define CLOCKS_CLK_GPOUT3_CTRL_PHASE_MSB _u(17) -#define CLOCKS_CLK_GPOUT3_CTRL_PHASE_LSB _u(16) -#define CLOCKS_CLK_GPOUT3_CTRL_PHASE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_GPOUT3_CTRL_DC50 -// Description : Enables duty cycle correction for odd divisors -#define CLOCKS_CLK_GPOUT3_CTRL_DC50_RESET _u(0x0) -#define CLOCKS_CLK_GPOUT3_CTRL_DC50_BITS _u(0x00001000) -#define CLOCKS_CLK_GPOUT3_CTRL_DC50_MSB _u(12) -#define CLOCKS_CLK_GPOUT3_CTRL_DC50_LSB _u(12) -#define CLOCKS_CLK_GPOUT3_CTRL_DC50_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_GPOUT3_CTRL_ENABLE -// Description : Starts and stops the clock generator cleanly -#define CLOCKS_CLK_GPOUT3_CTRL_ENABLE_RESET _u(0x0) -#define CLOCKS_CLK_GPOUT3_CTRL_ENABLE_BITS _u(0x00000800) -#define CLOCKS_CLK_GPOUT3_CTRL_ENABLE_MSB _u(11) -#define CLOCKS_CLK_GPOUT3_CTRL_ENABLE_LSB _u(11) -#define CLOCKS_CLK_GPOUT3_CTRL_ENABLE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_GPOUT3_CTRL_KILL -// Description : Asynchronously kills the clock generator -#define CLOCKS_CLK_GPOUT3_CTRL_KILL_RESET _u(0x0) -#define CLOCKS_CLK_GPOUT3_CTRL_KILL_BITS _u(0x00000400) -#define CLOCKS_CLK_GPOUT3_CTRL_KILL_MSB _u(10) -#define CLOCKS_CLK_GPOUT3_CTRL_KILL_LSB _u(10) -#define CLOCKS_CLK_GPOUT3_CTRL_KILL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_GPOUT3_CTRL_AUXSRC -// Description : Selects the auxiliary clock source, will glitch when switching -// 0x0 -> clksrc_pll_sys -// 0x1 -> clksrc_gpin0 -// 0x2 -> clksrc_gpin1 -// 0x3 -> clksrc_pll_usb -// 0x4 -> rosc_clksrc_ph -// 0x5 -> xosc_clksrc -// 0x6 -> clk_sys -// 0x7 -> clk_usb -// 0x8 -> clk_adc -// 0x9 -> clk_rtc -// 0xa -> clk_ref -#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_RESET _u(0x0) -#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_BITS _u(0x000001e0) -#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_MSB _u(8) -#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_LSB _u(5) -#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_ACCESS "RW" -#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS _u(0x0) -#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 _u(0x1) -#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 _u(0x2) -#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB _u(0x3) -#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH _u(0x4) -#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_XOSC_CLKSRC _u(0x5) -#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLK_SYS _u(0x6) -#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLK_USB _u(0x7) -#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLK_ADC _u(0x8) -#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLK_RTC _u(0x9) -#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLK_REF _u(0xa) -// ============================================================================= -// Register : CLOCKS_CLK_GPOUT3_DIV -// Description : Clock divisor, can be changed on-the-fly -#define CLOCKS_CLK_GPOUT3_DIV_OFFSET _u(0x00000028) -#define CLOCKS_CLK_GPOUT3_DIV_BITS _u(0xffffffff) -#define CLOCKS_CLK_GPOUT3_DIV_RESET _u(0x00000100) -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_GPOUT3_DIV_INT -// Description : Integer component of the divisor, 0 -> divide by 2^16 -#define CLOCKS_CLK_GPOUT3_DIV_INT_RESET _u(0x000001) -#define CLOCKS_CLK_GPOUT3_DIV_INT_BITS _u(0xffffff00) -#define CLOCKS_CLK_GPOUT3_DIV_INT_MSB _u(31) -#define CLOCKS_CLK_GPOUT3_DIV_INT_LSB _u(8) -#define CLOCKS_CLK_GPOUT3_DIV_INT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_GPOUT3_DIV_FRAC -// Description : Fractional component of the divisor -#define CLOCKS_CLK_GPOUT3_DIV_FRAC_RESET _u(0x00) -#define CLOCKS_CLK_GPOUT3_DIV_FRAC_BITS _u(0x000000ff) -#define CLOCKS_CLK_GPOUT3_DIV_FRAC_MSB _u(7) -#define CLOCKS_CLK_GPOUT3_DIV_FRAC_LSB _u(0) -#define CLOCKS_CLK_GPOUT3_DIV_FRAC_ACCESS "RW" -// ============================================================================= -// Register : CLOCKS_CLK_GPOUT3_SELECTED -// Description : Indicates which SRC is currently selected by the glitchless mux -// (one-hot). -// This slice does not have a glitchless mux (only the AUX_SRC -// field is present, not SRC) so this register is hardwired to -// 0x1. -#define CLOCKS_CLK_GPOUT3_SELECTED_OFFSET _u(0x0000002c) -#define CLOCKS_CLK_GPOUT3_SELECTED_BITS _u(0xffffffff) -#define CLOCKS_CLK_GPOUT3_SELECTED_RESET _u(0x00000001) -#define CLOCKS_CLK_GPOUT3_SELECTED_MSB _u(31) -#define CLOCKS_CLK_GPOUT3_SELECTED_LSB _u(0) -#define CLOCKS_CLK_GPOUT3_SELECTED_ACCESS "RO" -// ============================================================================= -// Register : CLOCKS_CLK_REF_CTRL -// Description : Clock control, can be changed on-the-fly (except for auxsrc) -#define CLOCKS_CLK_REF_CTRL_OFFSET _u(0x00000030) -#define CLOCKS_CLK_REF_CTRL_BITS _u(0x00000063) -#define CLOCKS_CLK_REF_CTRL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_REF_CTRL_AUXSRC -// Description : Selects the auxiliary clock source, will glitch when switching -// 0x0 -> clksrc_pll_usb -// 0x1 -> clksrc_gpin0 -// 0x2 -> clksrc_gpin1 -#define CLOCKS_CLK_REF_CTRL_AUXSRC_RESET _u(0x0) -#define CLOCKS_CLK_REF_CTRL_AUXSRC_BITS _u(0x00000060) -#define CLOCKS_CLK_REF_CTRL_AUXSRC_MSB _u(6) -#define CLOCKS_CLK_REF_CTRL_AUXSRC_LSB _u(5) -#define CLOCKS_CLK_REF_CTRL_AUXSRC_ACCESS "RW" -#define CLOCKS_CLK_REF_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB _u(0x0) -#define CLOCKS_CLK_REF_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 _u(0x1) -#define CLOCKS_CLK_REF_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 _u(0x2) -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_REF_CTRL_SRC -// Description : Selects the clock source glitchlessly, can be changed on-the- -// fly -// 0x0 -> rosc_clksrc_ph -// 0x1 -> clksrc_clk_ref_aux -// 0x2 -> xosc_clksrc -#define CLOCKS_CLK_REF_CTRL_SRC_RESET "-" -#define CLOCKS_CLK_REF_CTRL_SRC_BITS _u(0x00000003) -#define CLOCKS_CLK_REF_CTRL_SRC_MSB _u(1) -#define CLOCKS_CLK_REF_CTRL_SRC_LSB _u(0) -#define CLOCKS_CLK_REF_CTRL_SRC_ACCESS "RW" -#define CLOCKS_CLK_REF_CTRL_SRC_VALUE_ROSC_CLKSRC_PH _u(0x0) -#define CLOCKS_CLK_REF_CTRL_SRC_VALUE_CLKSRC_CLK_REF_AUX _u(0x1) -#define CLOCKS_CLK_REF_CTRL_SRC_VALUE_XOSC_CLKSRC _u(0x2) -// ============================================================================= -// Register : CLOCKS_CLK_REF_DIV -// Description : Clock divisor, can be changed on-the-fly -#define CLOCKS_CLK_REF_DIV_OFFSET _u(0x00000034) -#define CLOCKS_CLK_REF_DIV_BITS _u(0x00000300) -#define CLOCKS_CLK_REF_DIV_RESET _u(0x00000100) -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_REF_DIV_INT -// Description : Integer component of the divisor, 0 -> divide by 2^16 -#define CLOCKS_CLK_REF_DIV_INT_RESET _u(0x1) -#define CLOCKS_CLK_REF_DIV_INT_BITS _u(0x00000300) -#define CLOCKS_CLK_REF_DIV_INT_MSB _u(9) -#define CLOCKS_CLK_REF_DIV_INT_LSB _u(8) -#define CLOCKS_CLK_REF_DIV_INT_ACCESS "RW" -// ============================================================================= -// Register : CLOCKS_CLK_REF_SELECTED -// Description : Indicates which SRC is currently selected by the glitchless mux -// (one-hot). -// The glitchless multiplexer does not switch instantaneously (to -// avoid glitches), so software should poll this register to wait -// for the switch to complete. This register contains one decoded -// bit for each of the clock sources enumerated in the CTRL SRC -// field. At most one of these bits will be set at any time, -// indicating that clock is currently present at the output of the -// glitchless mux. Whilst switching is in progress, this register -// may briefly show all-0s. -#define CLOCKS_CLK_REF_SELECTED_OFFSET _u(0x00000038) -#define CLOCKS_CLK_REF_SELECTED_BITS _u(0xffffffff) -#define CLOCKS_CLK_REF_SELECTED_RESET _u(0x00000001) -#define CLOCKS_CLK_REF_SELECTED_MSB _u(31) -#define CLOCKS_CLK_REF_SELECTED_LSB _u(0) -#define CLOCKS_CLK_REF_SELECTED_ACCESS "RO" -// ============================================================================= -// Register : CLOCKS_CLK_SYS_CTRL -// Description : Clock control, can be changed on-the-fly (except for auxsrc) -#define CLOCKS_CLK_SYS_CTRL_OFFSET _u(0x0000003c) -#define CLOCKS_CLK_SYS_CTRL_BITS _u(0x000000e1) -#define CLOCKS_CLK_SYS_CTRL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_SYS_CTRL_AUXSRC -// Description : Selects the auxiliary clock source, will glitch when switching -// 0x0 -> clksrc_pll_sys -// 0x1 -> clksrc_pll_usb -// 0x2 -> rosc_clksrc -// 0x3 -> xosc_clksrc -// 0x4 -> clksrc_gpin0 -// 0x5 -> clksrc_gpin1 -#define CLOCKS_CLK_SYS_CTRL_AUXSRC_RESET _u(0x0) -#define CLOCKS_CLK_SYS_CTRL_AUXSRC_BITS _u(0x000000e0) -#define CLOCKS_CLK_SYS_CTRL_AUXSRC_MSB _u(7) -#define CLOCKS_CLK_SYS_CTRL_AUXSRC_LSB _u(5) -#define CLOCKS_CLK_SYS_CTRL_AUXSRC_ACCESS "RW" -#define CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS _u(0x0) -#define CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB _u(0x1) -#define CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_ROSC_CLKSRC _u(0x2) -#define CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_XOSC_CLKSRC _u(0x3) -#define CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 _u(0x4) -#define CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 _u(0x5) -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_SYS_CTRL_SRC -// Description : Selects the clock source glitchlessly, can be changed on-the- -// fly -// 0x0 -> clk_ref -// 0x1 -> clksrc_clk_sys_aux -#define CLOCKS_CLK_SYS_CTRL_SRC_RESET _u(0x0) -#define CLOCKS_CLK_SYS_CTRL_SRC_BITS _u(0x00000001) -#define CLOCKS_CLK_SYS_CTRL_SRC_MSB _u(0) -#define CLOCKS_CLK_SYS_CTRL_SRC_LSB _u(0) -#define CLOCKS_CLK_SYS_CTRL_SRC_ACCESS "RW" -#define CLOCKS_CLK_SYS_CTRL_SRC_VALUE_CLK_REF _u(0x0) -#define CLOCKS_CLK_SYS_CTRL_SRC_VALUE_CLKSRC_CLK_SYS_AUX _u(0x1) -// ============================================================================= -// Register : CLOCKS_CLK_SYS_DIV -// Description : Clock divisor, can be changed on-the-fly -#define CLOCKS_CLK_SYS_DIV_OFFSET _u(0x00000040) -#define CLOCKS_CLK_SYS_DIV_BITS _u(0xffffffff) -#define CLOCKS_CLK_SYS_DIV_RESET _u(0x00000100) -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_SYS_DIV_INT -// Description : Integer component of the divisor, 0 -> divide by 2^16 -#define CLOCKS_CLK_SYS_DIV_INT_RESET _u(0x000001) -#define CLOCKS_CLK_SYS_DIV_INT_BITS _u(0xffffff00) -#define CLOCKS_CLK_SYS_DIV_INT_MSB _u(31) -#define CLOCKS_CLK_SYS_DIV_INT_LSB _u(8) -#define CLOCKS_CLK_SYS_DIV_INT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_SYS_DIV_FRAC -// Description : Fractional component of the divisor -#define CLOCKS_CLK_SYS_DIV_FRAC_RESET _u(0x00) -#define CLOCKS_CLK_SYS_DIV_FRAC_BITS _u(0x000000ff) -#define CLOCKS_CLK_SYS_DIV_FRAC_MSB _u(7) -#define CLOCKS_CLK_SYS_DIV_FRAC_LSB _u(0) -#define CLOCKS_CLK_SYS_DIV_FRAC_ACCESS "RW" -// ============================================================================= -// Register : CLOCKS_CLK_SYS_SELECTED -// Description : Indicates which SRC is currently selected by the glitchless mux -// (one-hot). -// The glitchless multiplexer does not switch instantaneously (to -// avoid glitches), so software should poll this register to wait -// for the switch to complete. This register contains one decoded -// bit for each of the clock sources enumerated in the CTRL SRC -// field. At most one of these bits will be set at any time, -// indicating that clock is currently present at the output of the -// glitchless mux. Whilst switching is in progress, this register -// may briefly show all-0s. -#define CLOCKS_CLK_SYS_SELECTED_OFFSET _u(0x00000044) -#define CLOCKS_CLK_SYS_SELECTED_BITS _u(0xffffffff) -#define CLOCKS_CLK_SYS_SELECTED_RESET _u(0x00000001) -#define CLOCKS_CLK_SYS_SELECTED_MSB _u(31) -#define CLOCKS_CLK_SYS_SELECTED_LSB _u(0) -#define CLOCKS_CLK_SYS_SELECTED_ACCESS "RO" -// ============================================================================= -// Register : CLOCKS_CLK_PERI_CTRL -// Description : Clock control, can be changed on-the-fly (except for auxsrc) -#define CLOCKS_CLK_PERI_CTRL_OFFSET _u(0x00000048) -#define CLOCKS_CLK_PERI_CTRL_BITS _u(0x00000ce0) -#define CLOCKS_CLK_PERI_CTRL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_PERI_CTRL_ENABLE -// Description : Starts and stops the clock generator cleanly -#define CLOCKS_CLK_PERI_CTRL_ENABLE_RESET _u(0x0) -#define CLOCKS_CLK_PERI_CTRL_ENABLE_BITS _u(0x00000800) -#define CLOCKS_CLK_PERI_CTRL_ENABLE_MSB _u(11) -#define CLOCKS_CLK_PERI_CTRL_ENABLE_LSB _u(11) -#define CLOCKS_CLK_PERI_CTRL_ENABLE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_PERI_CTRL_KILL -// Description : Asynchronously kills the clock generator -#define CLOCKS_CLK_PERI_CTRL_KILL_RESET _u(0x0) -#define CLOCKS_CLK_PERI_CTRL_KILL_BITS _u(0x00000400) -#define CLOCKS_CLK_PERI_CTRL_KILL_MSB _u(10) -#define CLOCKS_CLK_PERI_CTRL_KILL_LSB _u(10) -#define CLOCKS_CLK_PERI_CTRL_KILL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_PERI_CTRL_AUXSRC -// Description : Selects the auxiliary clock source, will glitch when switching -// 0x0 -> clk_sys -// 0x1 -> clksrc_pll_sys -// 0x2 -> clksrc_pll_usb -// 0x3 -> rosc_clksrc_ph -// 0x4 -> xosc_clksrc -// 0x5 -> clksrc_gpin0 -// 0x6 -> clksrc_gpin1 -#define CLOCKS_CLK_PERI_CTRL_AUXSRC_RESET _u(0x0) -#define CLOCKS_CLK_PERI_CTRL_AUXSRC_BITS _u(0x000000e0) -#define CLOCKS_CLK_PERI_CTRL_AUXSRC_MSB _u(7) -#define CLOCKS_CLK_PERI_CTRL_AUXSRC_LSB _u(5) -#define CLOCKS_CLK_PERI_CTRL_AUXSRC_ACCESS "RW" -#define CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLK_SYS _u(0x0) -#define CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS _u(0x1) -#define CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB _u(0x2) -#define CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH _u(0x3) -#define CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_XOSC_CLKSRC _u(0x4) -#define CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 _u(0x5) -#define CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 _u(0x6) -// ============================================================================= -// Register : CLOCKS_CLK_PERI_SELECTED -// Description : Indicates which SRC is currently selected by the glitchless mux -// (one-hot). -// This slice does not have a glitchless mux (only the AUX_SRC -// field is present, not SRC) so this register is hardwired to -// 0x1. -#define CLOCKS_CLK_PERI_SELECTED_OFFSET _u(0x00000050) -#define CLOCKS_CLK_PERI_SELECTED_BITS _u(0xffffffff) -#define CLOCKS_CLK_PERI_SELECTED_RESET _u(0x00000001) -#define CLOCKS_CLK_PERI_SELECTED_MSB _u(31) -#define CLOCKS_CLK_PERI_SELECTED_LSB _u(0) -#define CLOCKS_CLK_PERI_SELECTED_ACCESS "RO" -// ============================================================================= -// Register : CLOCKS_CLK_USB_CTRL -// Description : Clock control, can be changed on-the-fly (except for auxsrc) -#define CLOCKS_CLK_USB_CTRL_OFFSET _u(0x00000054) -#define CLOCKS_CLK_USB_CTRL_BITS _u(0x00130ce0) -#define CLOCKS_CLK_USB_CTRL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_USB_CTRL_NUDGE -// Description : An edge on this signal shifts the phase of the output by 1 -// cycle of the input clock -// This can be done at any time -#define CLOCKS_CLK_USB_CTRL_NUDGE_RESET _u(0x0) -#define CLOCKS_CLK_USB_CTRL_NUDGE_BITS _u(0x00100000) -#define CLOCKS_CLK_USB_CTRL_NUDGE_MSB _u(20) -#define CLOCKS_CLK_USB_CTRL_NUDGE_LSB _u(20) -#define CLOCKS_CLK_USB_CTRL_NUDGE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_USB_CTRL_PHASE -// Description : This delays the enable signal by up to 3 cycles of the input -// clock -// This must be set before the clock is enabled to have any effect -#define CLOCKS_CLK_USB_CTRL_PHASE_RESET _u(0x0) -#define CLOCKS_CLK_USB_CTRL_PHASE_BITS _u(0x00030000) -#define CLOCKS_CLK_USB_CTRL_PHASE_MSB _u(17) -#define CLOCKS_CLK_USB_CTRL_PHASE_LSB _u(16) -#define CLOCKS_CLK_USB_CTRL_PHASE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_USB_CTRL_ENABLE -// Description : Starts and stops the clock generator cleanly -#define CLOCKS_CLK_USB_CTRL_ENABLE_RESET _u(0x0) -#define CLOCKS_CLK_USB_CTRL_ENABLE_BITS _u(0x00000800) -#define CLOCKS_CLK_USB_CTRL_ENABLE_MSB _u(11) -#define CLOCKS_CLK_USB_CTRL_ENABLE_LSB _u(11) -#define CLOCKS_CLK_USB_CTRL_ENABLE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_USB_CTRL_KILL -// Description : Asynchronously kills the clock generator -#define CLOCKS_CLK_USB_CTRL_KILL_RESET _u(0x0) -#define CLOCKS_CLK_USB_CTRL_KILL_BITS _u(0x00000400) -#define CLOCKS_CLK_USB_CTRL_KILL_MSB _u(10) -#define CLOCKS_CLK_USB_CTRL_KILL_LSB _u(10) -#define CLOCKS_CLK_USB_CTRL_KILL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_USB_CTRL_AUXSRC -// Description : Selects the auxiliary clock source, will glitch when switching -// 0x0 -> clksrc_pll_usb -// 0x1 -> clksrc_pll_sys -// 0x2 -> rosc_clksrc_ph -// 0x3 -> xosc_clksrc -// 0x4 -> clksrc_gpin0 -// 0x5 -> clksrc_gpin1 -#define CLOCKS_CLK_USB_CTRL_AUXSRC_RESET _u(0x0) -#define CLOCKS_CLK_USB_CTRL_AUXSRC_BITS _u(0x000000e0) -#define CLOCKS_CLK_USB_CTRL_AUXSRC_MSB _u(7) -#define CLOCKS_CLK_USB_CTRL_AUXSRC_LSB _u(5) -#define CLOCKS_CLK_USB_CTRL_AUXSRC_ACCESS "RW" -#define CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB _u(0x0) -#define CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS _u(0x1) -#define CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH _u(0x2) -#define CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_XOSC_CLKSRC _u(0x3) -#define CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 _u(0x4) -#define CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 _u(0x5) -// ============================================================================= -// Register : CLOCKS_CLK_USB_DIV -// Description : Clock divisor, can be changed on-the-fly -#define CLOCKS_CLK_USB_DIV_OFFSET _u(0x00000058) -#define CLOCKS_CLK_USB_DIV_BITS _u(0x00000300) -#define CLOCKS_CLK_USB_DIV_RESET _u(0x00000100) -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_USB_DIV_INT -// Description : Integer component of the divisor, 0 -> divide by 2^16 -#define CLOCKS_CLK_USB_DIV_INT_RESET _u(0x1) -#define CLOCKS_CLK_USB_DIV_INT_BITS _u(0x00000300) -#define CLOCKS_CLK_USB_DIV_INT_MSB _u(9) -#define CLOCKS_CLK_USB_DIV_INT_LSB _u(8) -#define CLOCKS_CLK_USB_DIV_INT_ACCESS "RW" -// ============================================================================= -// Register : CLOCKS_CLK_USB_SELECTED -// Description : Indicates which SRC is currently selected by the glitchless mux -// (one-hot). -// This slice does not have a glitchless mux (only the AUX_SRC -// field is present, not SRC) so this register is hardwired to -// 0x1. -#define CLOCKS_CLK_USB_SELECTED_OFFSET _u(0x0000005c) -#define CLOCKS_CLK_USB_SELECTED_BITS _u(0xffffffff) -#define CLOCKS_CLK_USB_SELECTED_RESET _u(0x00000001) -#define CLOCKS_CLK_USB_SELECTED_MSB _u(31) -#define CLOCKS_CLK_USB_SELECTED_LSB _u(0) -#define CLOCKS_CLK_USB_SELECTED_ACCESS "RO" -// ============================================================================= -// Register : CLOCKS_CLK_ADC_CTRL -// Description : Clock control, can be changed on-the-fly (except for auxsrc) -#define CLOCKS_CLK_ADC_CTRL_OFFSET _u(0x00000060) -#define CLOCKS_CLK_ADC_CTRL_BITS _u(0x00130ce0) -#define CLOCKS_CLK_ADC_CTRL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_ADC_CTRL_NUDGE -// Description : An edge on this signal shifts the phase of the output by 1 -// cycle of the input clock -// This can be done at any time -#define CLOCKS_CLK_ADC_CTRL_NUDGE_RESET _u(0x0) -#define CLOCKS_CLK_ADC_CTRL_NUDGE_BITS _u(0x00100000) -#define CLOCKS_CLK_ADC_CTRL_NUDGE_MSB _u(20) -#define CLOCKS_CLK_ADC_CTRL_NUDGE_LSB _u(20) -#define CLOCKS_CLK_ADC_CTRL_NUDGE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_ADC_CTRL_PHASE -// Description : This delays the enable signal by up to 3 cycles of the input -// clock -// This must be set before the clock is enabled to have any effect -#define CLOCKS_CLK_ADC_CTRL_PHASE_RESET _u(0x0) -#define CLOCKS_CLK_ADC_CTRL_PHASE_BITS _u(0x00030000) -#define CLOCKS_CLK_ADC_CTRL_PHASE_MSB _u(17) -#define CLOCKS_CLK_ADC_CTRL_PHASE_LSB _u(16) -#define CLOCKS_CLK_ADC_CTRL_PHASE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_ADC_CTRL_ENABLE -// Description : Starts and stops the clock generator cleanly -#define CLOCKS_CLK_ADC_CTRL_ENABLE_RESET _u(0x0) -#define CLOCKS_CLK_ADC_CTRL_ENABLE_BITS _u(0x00000800) -#define CLOCKS_CLK_ADC_CTRL_ENABLE_MSB _u(11) -#define CLOCKS_CLK_ADC_CTRL_ENABLE_LSB _u(11) -#define CLOCKS_CLK_ADC_CTRL_ENABLE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_ADC_CTRL_KILL -// Description : Asynchronously kills the clock generator -#define CLOCKS_CLK_ADC_CTRL_KILL_RESET _u(0x0) -#define CLOCKS_CLK_ADC_CTRL_KILL_BITS _u(0x00000400) -#define CLOCKS_CLK_ADC_CTRL_KILL_MSB _u(10) -#define CLOCKS_CLK_ADC_CTRL_KILL_LSB _u(10) -#define CLOCKS_CLK_ADC_CTRL_KILL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_ADC_CTRL_AUXSRC -// Description : Selects the auxiliary clock source, will glitch when switching -// 0x0 -> clksrc_pll_usb -// 0x1 -> clksrc_pll_sys -// 0x2 -> rosc_clksrc_ph -// 0x3 -> xosc_clksrc -// 0x4 -> clksrc_gpin0 -// 0x5 -> clksrc_gpin1 -#define CLOCKS_CLK_ADC_CTRL_AUXSRC_RESET _u(0x0) -#define CLOCKS_CLK_ADC_CTRL_AUXSRC_BITS _u(0x000000e0) -#define CLOCKS_CLK_ADC_CTRL_AUXSRC_MSB _u(7) -#define CLOCKS_CLK_ADC_CTRL_AUXSRC_LSB _u(5) -#define CLOCKS_CLK_ADC_CTRL_AUXSRC_ACCESS "RW" -#define CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB _u(0x0) -#define CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS _u(0x1) -#define CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH _u(0x2) -#define CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_XOSC_CLKSRC _u(0x3) -#define CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 _u(0x4) -#define CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 _u(0x5) -// ============================================================================= -// Register : CLOCKS_CLK_ADC_DIV -// Description : Clock divisor, can be changed on-the-fly -#define CLOCKS_CLK_ADC_DIV_OFFSET _u(0x00000064) -#define CLOCKS_CLK_ADC_DIV_BITS _u(0x00000300) -#define CLOCKS_CLK_ADC_DIV_RESET _u(0x00000100) -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_ADC_DIV_INT -// Description : Integer component of the divisor, 0 -> divide by 2^16 -#define CLOCKS_CLK_ADC_DIV_INT_RESET _u(0x1) -#define CLOCKS_CLK_ADC_DIV_INT_BITS _u(0x00000300) -#define CLOCKS_CLK_ADC_DIV_INT_MSB _u(9) -#define CLOCKS_CLK_ADC_DIV_INT_LSB _u(8) -#define CLOCKS_CLK_ADC_DIV_INT_ACCESS "RW" -// ============================================================================= -// Register : CLOCKS_CLK_ADC_SELECTED -// Description : Indicates which SRC is currently selected by the glitchless mux -// (one-hot). -// This slice does not have a glitchless mux (only the AUX_SRC -// field is present, not SRC) so this register is hardwired to -// 0x1. -#define CLOCKS_CLK_ADC_SELECTED_OFFSET _u(0x00000068) -#define CLOCKS_CLK_ADC_SELECTED_BITS _u(0xffffffff) -#define CLOCKS_CLK_ADC_SELECTED_RESET _u(0x00000001) -#define CLOCKS_CLK_ADC_SELECTED_MSB _u(31) -#define CLOCKS_CLK_ADC_SELECTED_LSB _u(0) -#define CLOCKS_CLK_ADC_SELECTED_ACCESS "RO" -// ============================================================================= -// Register : CLOCKS_CLK_RTC_CTRL -// Description : Clock control, can be changed on-the-fly (except for auxsrc) -#define CLOCKS_CLK_RTC_CTRL_OFFSET _u(0x0000006c) -#define CLOCKS_CLK_RTC_CTRL_BITS _u(0x00130ce0) -#define CLOCKS_CLK_RTC_CTRL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_RTC_CTRL_NUDGE -// Description : An edge on this signal shifts the phase of the output by 1 -// cycle of the input clock -// This can be done at any time -#define CLOCKS_CLK_RTC_CTRL_NUDGE_RESET _u(0x0) -#define CLOCKS_CLK_RTC_CTRL_NUDGE_BITS _u(0x00100000) -#define CLOCKS_CLK_RTC_CTRL_NUDGE_MSB _u(20) -#define CLOCKS_CLK_RTC_CTRL_NUDGE_LSB _u(20) -#define CLOCKS_CLK_RTC_CTRL_NUDGE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_RTC_CTRL_PHASE -// Description : This delays the enable signal by up to 3 cycles of the input -// clock -// This must be set before the clock is enabled to have any effect -#define CLOCKS_CLK_RTC_CTRL_PHASE_RESET _u(0x0) -#define CLOCKS_CLK_RTC_CTRL_PHASE_BITS _u(0x00030000) -#define CLOCKS_CLK_RTC_CTRL_PHASE_MSB _u(17) -#define CLOCKS_CLK_RTC_CTRL_PHASE_LSB _u(16) -#define CLOCKS_CLK_RTC_CTRL_PHASE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_RTC_CTRL_ENABLE -// Description : Starts and stops the clock generator cleanly -#define CLOCKS_CLK_RTC_CTRL_ENABLE_RESET _u(0x0) -#define CLOCKS_CLK_RTC_CTRL_ENABLE_BITS _u(0x00000800) -#define CLOCKS_CLK_RTC_CTRL_ENABLE_MSB _u(11) -#define CLOCKS_CLK_RTC_CTRL_ENABLE_LSB _u(11) -#define CLOCKS_CLK_RTC_CTRL_ENABLE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_RTC_CTRL_KILL -// Description : Asynchronously kills the clock generator -#define CLOCKS_CLK_RTC_CTRL_KILL_RESET _u(0x0) -#define CLOCKS_CLK_RTC_CTRL_KILL_BITS _u(0x00000400) -#define CLOCKS_CLK_RTC_CTRL_KILL_MSB _u(10) -#define CLOCKS_CLK_RTC_CTRL_KILL_LSB _u(10) -#define CLOCKS_CLK_RTC_CTRL_KILL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_RTC_CTRL_AUXSRC -// Description : Selects the auxiliary clock source, will glitch when switching -// 0x0 -> clksrc_pll_usb -// 0x1 -> clksrc_pll_sys -// 0x2 -> rosc_clksrc_ph -// 0x3 -> xosc_clksrc -// 0x4 -> clksrc_gpin0 -// 0x5 -> clksrc_gpin1 -#define CLOCKS_CLK_RTC_CTRL_AUXSRC_RESET _u(0x0) -#define CLOCKS_CLK_RTC_CTRL_AUXSRC_BITS _u(0x000000e0) -#define CLOCKS_CLK_RTC_CTRL_AUXSRC_MSB _u(7) -#define CLOCKS_CLK_RTC_CTRL_AUXSRC_LSB _u(5) -#define CLOCKS_CLK_RTC_CTRL_AUXSRC_ACCESS "RW" -#define CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB _u(0x0) -#define CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS _u(0x1) -#define CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH _u(0x2) -#define CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_XOSC_CLKSRC _u(0x3) -#define CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 _u(0x4) -#define CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 _u(0x5) -// ============================================================================= -// Register : CLOCKS_CLK_RTC_DIV -// Description : Clock divisor, can be changed on-the-fly -#define CLOCKS_CLK_RTC_DIV_OFFSET _u(0x00000070) -#define CLOCKS_CLK_RTC_DIV_BITS _u(0xffffffff) -#define CLOCKS_CLK_RTC_DIV_RESET _u(0x00000100) -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_RTC_DIV_INT -// Description : Integer component of the divisor, 0 -> divide by 2^16 -#define CLOCKS_CLK_RTC_DIV_INT_RESET _u(0x000001) -#define CLOCKS_CLK_RTC_DIV_INT_BITS _u(0xffffff00) -#define CLOCKS_CLK_RTC_DIV_INT_MSB _u(31) -#define CLOCKS_CLK_RTC_DIV_INT_LSB _u(8) -#define CLOCKS_CLK_RTC_DIV_INT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_RTC_DIV_FRAC -// Description : Fractional component of the divisor -#define CLOCKS_CLK_RTC_DIV_FRAC_RESET _u(0x00) -#define CLOCKS_CLK_RTC_DIV_FRAC_BITS _u(0x000000ff) -#define CLOCKS_CLK_RTC_DIV_FRAC_MSB _u(7) -#define CLOCKS_CLK_RTC_DIV_FRAC_LSB _u(0) -#define CLOCKS_CLK_RTC_DIV_FRAC_ACCESS "RW" -// ============================================================================= -// Register : CLOCKS_CLK_RTC_SELECTED -// Description : Indicates which SRC is currently selected by the glitchless mux -// (one-hot). -// This slice does not have a glitchless mux (only the AUX_SRC -// field is present, not SRC) so this register is hardwired to -// 0x1. -#define CLOCKS_CLK_RTC_SELECTED_OFFSET _u(0x00000074) -#define CLOCKS_CLK_RTC_SELECTED_BITS _u(0xffffffff) -#define CLOCKS_CLK_RTC_SELECTED_RESET _u(0x00000001) -#define CLOCKS_CLK_RTC_SELECTED_MSB _u(31) -#define CLOCKS_CLK_RTC_SELECTED_LSB _u(0) -#define CLOCKS_CLK_RTC_SELECTED_ACCESS "RO" -// ============================================================================= -// Register : CLOCKS_CLK_SYS_RESUS_CTRL -#define CLOCKS_CLK_SYS_RESUS_CTRL_OFFSET _u(0x00000078) -#define CLOCKS_CLK_SYS_RESUS_CTRL_BITS _u(0x000111ff) -#define CLOCKS_CLK_SYS_RESUS_CTRL_RESET _u(0x000000ff) -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_SYS_RESUS_CTRL_CLEAR -// Description : For clearing the resus after the fault that triggered it has -// been corrected -#define CLOCKS_CLK_SYS_RESUS_CTRL_CLEAR_RESET _u(0x0) -#define CLOCKS_CLK_SYS_RESUS_CTRL_CLEAR_BITS _u(0x00010000) -#define CLOCKS_CLK_SYS_RESUS_CTRL_CLEAR_MSB _u(16) -#define CLOCKS_CLK_SYS_RESUS_CTRL_CLEAR_LSB _u(16) -#define CLOCKS_CLK_SYS_RESUS_CTRL_CLEAR_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_SYS_RESUS_CTRL_FRCE -// Description : Force a resus, for test purposes only -#define CLOCKS_CLK_SYS_RESUS_CTRL_FRCE_RESET _u(0x0) -#define CLOCKS_CLK_SYS_RESUS_CTRL_FRCE_BITS _u(0x00001000) -#define CLOCKS_CLK_SYS_RESUS_CTRL_FRCE_MSB _u(12) -#define CLOCKS_CLK_SYS_RESUS_CTRL_FRCE_LSB _u(12) -#define CLOCKS_CLK_SYS_RESUS_CTRL_FRCE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_SYS_RESUS_CTRL_ENABLE -// Description : Enable resus -#define CLOCKS_CLK_SYS_RESUS_CTRL_ENABLE_RESET _u(0x0) -#define CLOCKS_CLK_SYS_RESUS_CTRL_ENABLE_BITS _u(0x00000100) -#define CLOCKS_CLK_SYS_RESUS_CTRL_ENABLE_MSB _u(8) -#define CLOCKS_CLK_SYS_RESUS_CTRL_ENABLE_LSB _u(8) -#define CLOCKS_CLK_SYS_RESUS_CTRL_ENABLE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_SYS_RESUS_CTRL_TIMEOUT -// Description : This is expressed as a number of clk_ref cycles -// and must be >= 2x clk_ref_freq/min_clk_tst_freq -#define CLOCKS_CLK_SYS_RESUS_CTRL_TIMEOUT_RESET _u(0xff) -#define CLOCKS_CLK_SYS_RESUS_CTRL_TIMEOUT_BITS _u(0x000000ff) -#define CLOCKS_CLK_SYS_RESUS_CTRL_TIMEOUT_MSB _u(7) -#define CLOCKS_CLK_SYS_RESUS_CTRL_TIMEOUT_LSB _u(0) -#define CLOCKS_CLK_SYS_RESUS_CTRL_TIMEOUT_ACCESS "RW" -// ============================================================================= -// Register : CLOCKS_CLK_SYS_RESUS_STATUS -#define CLOCKS_CLK_SYS_RESUS_STATUS_OFFSET _u(0x0000007c) -#define CLOCKS_CLK_SYS_RESUS_STATUS_BITS _u(0x00000001) -#define CLOCKS_CLK_SYS_RESUS_STATUS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_SYS_RESUS_STATUS_RESUSSED -// Description : Clock has been resuscitated, correct the error then send -// ctrl_clear=1 -#define CLOCKS_CLK_SYS_RESUS_STATUS_RESUSSED_RESET _u(0x0) -#define CLOCKS_CLK_SYS_RESUS_STATUS_RESUSSED_BITS _u(0x00000001) -#define CLOCKS_CLK_SYS_RESUS_STATUS_RESUSSED_MSB _u(0) -#define CLOCKS_CLK_SYS_RESUS_STATUS_RESUSSED_LSB _u(0) -#define CLOCKS_CLK_SYS_RESUS_STATUS_RESUSSED_ACCESS "RO" -// ============================================================================= -// Register : CLOCKS_FC0_REF_KHZ -// Description : Reference clock frequency in kHz -#define CLOCKS_FC0_REF_KHZ_OFFSET _u(0x00000080) -#define CLOCKS_FC0_REF_KHZ_BITS _u(0x000fffff) -#define CLOCKS_FC0_REF_KHZ_RESET _u(0x00000000) -#define CLOCKS_FC0_REF_KHZ_MSB _u(19) -#define CLOCKS_FC0_REF_KHZ_LSB _u(0) -#define CLOCKS_FC0_REF_KHZ_ACCESS "RW" -// ============================================================================= -// Register : CLOCKS_FC0_MIN_KHZ -// Description : Minimum pass frequency in kHz. This is optional. Set to 0 if -// you are not using the pass/fail flags -#define CLOCKS_FC0_MIN_KHZ_OFFSET _u(0x00000084) -#define CLOCKS_FC0_MIN_KHZ_BITS _u(0x01ffffff) -#define CLOCKS_FC0_MIN_KHZ_RESET _u(0x00000000) -#define CLOCKS_FC0_MIN_KHZ_MSB _u(24) -#define CLOCKS_FC0_MIN_KHZ_LSB _u(0) -#define CLOCKS_FC0_MIN_KHZ_ACCESS "RW" -// ============================================================================= -// Register : CLOCKS_FC0_MAX_KHZ -// Description : Maximum pass frequency in kHz. This is optional. Set to -// 0x1ffffff if you are not using the pass/fail flags -#define CLOCKS_FC0_MAX_KHZ_OFFSET _u(0x00000088) -#define CLOCKS_FC0_MAX_KHZ_BITS _u(0x01ffffff) -#define CLOCKS_FC0_MAX_KHZ_RESET _u(0x01ffffff) -#define CLOCKS_FC0_MAX_KHZ_MSB _u(24) -#define CLOCKS_FC0_MAX_KHZ_LSB _u(0) -#define CLOCKS_FC0_MAX_KHZ_ACCESS "RW" -// ============================================================================= -// Register : CLOCKS_FC0_DELAY -// Description : Delays the start of frequency counting to allow the mux to -// settle -// Delay is measured in multiples of the reference clock period -#define CLOCKS_FC0_DELAY_OFFSET _u(0x0000008c) -#define CLOCKS_FC0_DELAY_BITS _u(0x00000007) -#define CLOCKS_FC0_DELAY_RESET _u(0x00000001) -#define CLOCKS_FC0_DELAY_MSB _u(2) -#define CLOCKS_FC0_DELAY_LSB _u(0) -#define CLOCKS_FC0_DELAY_ACCESS "RW" -// ============================================================================= -// Register : CLOCKS_FC0_INTERVAL -// Description : The test interval is 0.98us * 2**interval, but let's call it -// 1us * 2**interval -// The default gives a test interval of 250us -#define CLOCKS_FC0_INTERVAL_OFFSET _u(0x00000090) -#define CLOCKS_FC0_INTERVAL_BITS _u(0x0000000f) -#define CLOCKS_FC0_INTERVAL_RESET _u(0x00000008) -#define CLOCKS_FC0_INTERVAL_MSB _u(3) -#define CLOCKS_FC0_INTERVAL_LSB _u(0) -#define CLOCKS_FC0_INTERVAL_ACCESS "RW" -// ============================================================================= -// Register : CLOCKS_FC0_SRC -// Description : Clock sent to frequency counter, set to 0 when not required -// Writing to this register initiates the frequency count -// 0x00 -> NULL -// 0x01 -> pll_sys_clksrc_primary -// 0x02 -> pll_usb_clksrc_primary -// 0x03 -> rosc_clksrc -// 0x04 -> rosc_clksrc_ph -// 0x05 -> xosc_clksrc -// 0x06 -> clksrc_gpin0 -// 0x07 -> clksrc_gpin1 -// 0x08 -> clk_ref -// 0x09 -> clk_sys -// 0x0a -> clk_peri -// 0x0b -> clk_usb -// 0x0c -> clk_adc -// 0x0d -> clk_rtc -#define CLOCKS_FC0_SRC_OFFSET _u(0x00000094) -#define CLOCKS_FC0_SRC_BITS _u(0x000000ff) -#define CLOCKS_FC0_SRC_RESET _u(0x00000000) -#define CLOCKS_FC0_SRC_MSB _u(7) -#define CLOCKS_FC0_SRC_LSB _u(0) -#define CLOCKS_FC0_SRC_ACCESS "RW" -#define CLOCKS_FC0_SRC_VALUE_NULL _u(0x00) -#define CLOCKS_FC0_SRC_VALUE_PLL_SYS_CLKSRC_PRIMARY _u(0x01) -#define CLOCKS_FC0_SRC_VALUE_PLL_USB_CLKSRC_PRIMARY _u(0x02) -#define CLOCKS_FC0_SRC_VALUE_ROSC_CLKSRC _u(0x03) -#define CLOCKS_FC0_SRC_VALUE_ROSC_CLKSRC_PH _u(0x04) -#define CLOCKS_FC0_SRC_VALUE_XOSC_CLKSRC _u(0x05) -#define CLOCKS_FC0_SRC_VALUE_CLKSRC_GPIN0 _u(0x06) -#define CLOCKS_FC0_SRC_VALUE_CLKSRC_GPIN1 _u(0x07) -#define CLOCKS_FC0_SRC_VALUE_CLK_REF _u(0x08) -#define CLOCKS_FC0_SRC_VALUE_CLK_SYS _u(0x09) -#define CLOCKS_FC0_SRC_VALUE_CLK_PERI _u(0x0a) -#define CLOCKS_FC0_SRC_VALUE_CLK_USB _u(0x0b) -#define CLOCKS_FC0_SRC_VALUE_CLK_ADC _u(0x0c) -#define CLOCKS_FC0_SRC_VALUE_CLK_RTC _u(0x0d) -// ============================================================================= -// Register : CLOCKS_FC0_STATUS -// Description : Frequency counter status -#define CLOCKS_FC0_STATUS_OFFSET _u(0x00000098) -#define CLOCKS_FC0_STATUS_BITS _u(0x11111111) -#define CLOCKS_FC0_STATUS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : CLOCKS_FC0_STATUS_DIED -// Description : Test clock stopped during test -#define CLOCKS_FC0_STATUS_DIED_RESET _u(0x0) -#define CLOCKS_FC0_STATUS_DIED_BITS _u(0x10000000) -#define CLOCKS_FC0_STATUS_DIED_MSB _u(28) -#define CLOCKS_FC0_STATUS_DIED_LSB _u(28) -#define CLOCKS_FC0_STATUS_DIED_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_FC0_STATUS_FAST -// Description : Test clock faster than expected, only valid when status_done=1 -#define CLOCKS_FC0_STATUS_FAST_RESET _u(0x0) -#define CLOCKS_FC0_STATUS_FAST_BITS _u(0x01000000) -#define CLOCKS_FC0_STATUS_FAST_MSB _u(24) -#define CLOCKS_FC0_STATUS_FAST_LSB _u(24) -#define CLOCKS_FC0_STATUS_FAST_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_FC0_STATUS_SLOW -// Description : Test clock slower than expected, only valid when status_done=1 -#define CLOCKS_FC0_STATUS_SLOW_RESET _u(0x0) -#define CLOCKS_FC0_STATUS_SLOW_BITS _u(0x00100000) -#define CLOCKS_FC0_STATUS_SLOW_MSB _u(20) -#define CLOCKS_FC0_STATUS_SLOW_LSB _u(20) -#define CLOCKS_FC0_STATUS_SLOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_FC0_STATUS_FAIL -// Description : Test failed -#define CLOCKS_FC0_STATUS_FAIL_RESET _u(0x0) -#define CLOCKS_FC0_STATUS_FAIL_BITS _u(0x00010000) -#define CLOCKS_FC0_STATUS_FAIL_MSB _u(16) -#define CLOCKS_FC0_STATUS_FAIL_LSB _u(16) -#define CLOCKS_FC0_STATUS_FAIL_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_FC0_STATUS_WAITING -// Description : Waiting for test clock to start -#define CLOCKS_FC0_STATUS_WAITING_RESET _u(0x0) -#define CLOCKS_FC0_STATUS_WAITING_BITS _u(0x00001000) -#define CLOCKS_FC0_STATUS_WAITING_MSB _u(12) -#define CLOCKS_FC0_STATUS_WAITING_LSB _u(12) -#define CLOCKS_FC0_STATUS_WAITING_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_FC0_STATUS_RUNNING -// Description : Test running -#define CLOCKS_FC0_STATUS_RUNNING_RESET _u(0x0) -#define CLOCKS_FC0_STATUS_RUNNING_BITS _u(0x00000100) -#define CLOCKS_FC0_STATUS_RUNNING_MSB _u(8) -#define CLOCKS_FC0_STATUS_RUNNING_LSB _u(8) -#define CLOCKS_FC0_STATUS_RUNNING_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_FC0_STATUS_DONE -// Description : Test complete -#define CLOCKS_FC0_STATUS_DONE_RESET _u(0x0) -#define CLOCKS_FC0_STATUS_DONE_BITS _u(0x00000010) -#define CLOCKS_FC0_STATUS_DONE_MSB _u(4) -#define CLOCKS_FC0_STATUS_DONE_LSB _u(4) -#define CLOCKS_FC0_STATUS_DONE_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_FC0_STATUS_PASS -// Description : Test passed -#define CLOCKS_FC0_STATUS_PASS_RESET _u(0x0) -#define CLOCKS_FC0_STATUS_PASS_BITS _u(0x00000001) -#define CLOCKS_FC0_STATUS_PASS_MSB _u(0) -#define CLOCKS_FC0_STATUS_PASS_LSB _u(0) -#define CLOCKS_FC0_STATUS_PASS_ACCESS "RO" -// ============================================================================= -// Register : CLOCKS_FC0_RESULT -// Description : Result of frequency measurement, only valid when status_done=1 -#define CLOCKS_FC0_RESULT_OFFSET _u(0x0000009c) -#define CLOCKS_FC0_RESULT_BITS _u(0x3fffffff) -#define CLOCKS_FC0_RESULT_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : CLOCKS_FC0_RESULT_KHZ -#define CLOCKS_FC0_RESULT_KHZ_RESET _u(0x0000000) -#define CLOCKS_FC0_RESULT_KHZ_BITS _u(0x3fffffe0) -#define CLOCKS_FC0_RESULT_KHZ_MSB _u(29) -#define CLOCKS_FC0_RESULT_KHZ_LSB _u(5) -#define CLOCKS_FC0_RESULT_KHZ_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_FC0_RESULT_FRAC -#define CLOCKS_FC0_RESULT_FRAC_RESET _u(0x00) -#define CLOCKS_FC0_RESULT_FRAC_BITS _u(0x0000001f) -#define CLOCKS_FC0_RESULT_FRAC_MSB _u(4) -#define CLOCKS_FC0_RESULT_FRAC_LSB _u(0) -#define CLOCKS_FC0_RESULT_FRAC_ACCESS "RO" -// ============================================================================= -// Register : CLOCKS_WAKE_EN0 -// Description : enable clock in wake mode -#define CLOCKS_WAKE_EN0_OFFSET _u(0x000000a0) -#define CLOCKS_WAKE_EN0_BITS _u(0xffffffff) -#define CLOCKS_WAKE_EN0_RESET _u(0xffffffff) -// ----------------------------------------------------------------------------- -// Field : CLOCKS_WAKE_EN0_CLK_SYS_SRAM3 -#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM3_RESET _u(0x1) -#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM3_BITS _u(0x80000000) -#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM3_MSB _u(31) -#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM3_LSB _u(31) -#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM3_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_WAKE_EN0_CLK_SYS_SRAM2 -#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM2_RESET _u(0x1) -#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM2_BITS _u(0x40000000) -#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM2_MSB _u(30) -#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM2_LSB _u(30) -#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM2_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_WAKE_EN0_CLK_SYS_SRAM1 -#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM1_RESET _u(0x1) -#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM1_BITS _u(0x20000000) -#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM1_MSB _u(29) -#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM1_LSB _u(29) -#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_WAKE_EN0_CLK_SYS_SRAM0 -#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM0_RESET _u(0x1) -#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM0_BITS _u(0x10000000) -#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM0_MSB _u(28) -#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM0_LSB _u(28) -#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_WAKE_EN0_CLK_SYS_SPI1 -#define CLOCKS_WAKE_EN0_CLK_SYS_SPI1_RESET _u(0x1) -#define CLOCKS_WAKE_EN0_CLK_SYS_SPI1_BITS _u(0x08000000) -#define CLOCKS_WAKE_EN0_CLK_SYS_SPI1_MSB _u(27) -#define CLOCKS_WAKE_EN0_CLK_SYS_SPI1_LSB _u(27) -#define CLOCKS_WAKE_EN0_CLK_SYS_SPI1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_WAKE_EN0_CLK_PERI_SPI1 -#define CLOCKS_WAKE_EN0_CLK_PERI_SPI1_RESET _u(0x1) -#define CLOCKS_WAKE_EN0_CLK_PERI_SPI1_BITS _u(0x04000000) -#define CLOCKS_WAKE_EN0_CLK_PERI_SPI1_MSB _u(26) -#define CLOCKS_WAKE_EN0_CLK_PERI_SPI1_LSB _u(26) -#define CLOCKS_WAKE_EN0_CLK_PERI_SPI1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_WAKE_EN0_CLK_SYS_SPI0 -#define CLOCKS_WAKE_EN0_CLK_SYS_SPI0_RESET _u(0x1) -#define CLOCKS_WAKE_EN0_CLK_SYS_SPI0_BITS _u(0x02000000) -#define CLOCKS_WAKE_EN0_CLK_SYS_SPI0_MSB _u(25) -#define CLOCKS_WAKE_EN0_CLK_SYS_SPI0_LSB _u(25) -#define CLOCKS_WAKE_EN0_CLK_SYS_SPI0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_WAKE_EN0_CLK_PERI_SPI0 -#define CLOCKS_WAKE_EN0_CLK_PERI_SPI0_RESET _u(0x1) -#define CLOCKS_WAKE_EN0_CLK_PERI_SPI0_BITS _u(0x01000000) -#define CLOCKS_WAKE_EN0_CLK_PERI_SPI0_MSB _u(24) -#define CLOCKS_WAKE_EN0_CLK_PERI_SPI0_LSB _u(24) -#define CLOCKS_WAKE_EN0_CLK_PERI_SPI0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_WAKE_EN0_CLK_SYS_SIO -#define CLOCKS_WAKE_EN0_CLK_SYS_SIO_RESET _u(0x1) -#define CLOCKS_WAKE_EN0_CLK_SYS_SIO_BITS _u(0x00800000) -#define CLOCKS_WAKE_EN0_CLK_SYS_SIO_MSB _u(23) -#define CLOCKS_WAKE_EN0_CLK_SYS_SIO_LSB _u(23) -#define CLOCKS_WAKE_EN0_CLK_SYS_SIO_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_WAKE_EN0_CLK_SYS_RTC -#define CLOCKS_WAKE_EN0_CLK_SYS_RTC_RESET _u(0x1) -#define CLOCKS_WAKE_EN0_CLK_SYS_RTC_BITS _u(0x00400000) -#define CLOCKS_WAKE_EN0_CLK_SYS_RTC_MSB _u(22) -#define CLOCKS_WAKE_EN0_CLK_SYS_RTC_LSB _u(22) -#define CLOCKS_WAKE_EN0_CLK_SYS_RTC_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_WAKE_EN0_CLK_RTC_RTC -#define CLOCKS_WAKE_EN0_CLK_RTC_RTC_RESET _u(0x1) -#define CLOCKS_WAKE_EN0_CLK_RTC_RTC_BITS _u(0x00200000) -#define CLOCKS_WAKE_EN0_CLK_RTC_RTC_MSB _u(21) -#define CLOCKS_WAKE_EN0_CLK_RTC_RTC_LSB _u(21) -#define CLOCKS_WAKE_EN0_CLK_RTC_RTC_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_WAKE_EN0_CLK_SYS_ROSC -#define CLOCKS_WAKE_EN0_CLK_SYS_ROSC_RESET _u(0x1) -#define CLOCKS_WAKE_EN0_CLK_SYS_ROSC_BITS _u(0x00100000) -#define CLOCKS_WAKE_EN0_CLK_SYS_ROSC_MSB _u(20) -#define CLOCKS_WAKE_EN0_CLK_SYS_ROSC_LSB _u(20) -#define CLOCKS_WAKE_EN0_CLK_SYS_ROSC_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_WAKE_EN0_CLK_SYS_ROM -#define CLOCKS_WAKE_EN0_CLK_SYS_ROM_RESET _u(0x1) -#define CLOCKS_WAKE_EN0_CLK_SYS_ROM_BITS _u(0x00080000) -#define CLOCKS_WAKE_EN0_CLK_SYS_ROM_MSB _u(19) -#define CLOCKS_WAKE_EN0_CLK_SYS_ROM_LSB _u(19) -#define CLOCKS_WAKE_EN0_CLK_SYS_ROM_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_WAKE_EN0_CLK_SYS_RESETS -#define CLOCKS_WAKE_EN0_CLK_SYS_RESETS_RESET _u(0x1) -#define CLOCKS_WAKE_EN0_CLK_SYS_RESETS_BITS _u(0x00040000) -#define CLOCKS_WAKE_EN0_CLK_SYS_RESETS_MSB _u(18) -#define CLOCKS_WAKE_EN0_CLK_SYS_RESETS_LSB _u(18) -#define CLOCKS_WAKE_EN0_CLK_SYS_RESETS_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_WAKE_EN0_CLK_SYS_PWM -#define CLOCKS_WAKE_EN0_CLK_SYS_PWM_RESET _u(0x1) -#define CLOCKS_WAKE_EN0_CLK_SYS_PWM_BITS _u(0x00020000) -#define CLOCKS_WAKE_EN0_CLK_SYS_PWM_MSB _u(17) -#define CLOCKS_WAKE_EN0_CLK_SYS_PWM_LSB _u(17) -#define CLOCKS_WAKE_EN0_CLK_SYS_PWM_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_WAKE_EN0_CLK_SYS_PSM -#define CLOCKS_WAKE_EN0_CLK_SYS_PSM_RESET _u(0x1) -#define CLOCKS_WAKE_EN0_CLK_SYS_PSM_BITS _u(0x00010000) -#define CLOCKS_WAKE_EN0_CLK_SYS_PSM_MSB _u(16) -#define CLOCKS_WAKE_EN0_CLK_SYS_PSM_LSB _u(16) -#define CLOCKS_WAKE_EN0_CLK_SYS_PSM_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_WAKE_EN0_CLK_SYS_PLL_USB -#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_USB_RESET _u(0x1) -#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_USB_BITS _u(0x00008000) -#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_USB_MSB _u(15) -#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_USB_LSB _u(15) -#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_USB_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_WAKE_EN0_CLK_SYS_PLL_SYS -#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_SYS_RESET _u(0x1) -#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_SYS_BITS _u(0x00004000) -#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_SYS_MSB _u(14) -#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_SYS_LSB _u(14) -#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_SYS_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_WAKE_EN0_CLK_SYS_PIO1 -#define CLOCKS_WAKE_EN0_CLK_SYS_PIO1_RESET _u(0x1) -#define CLOCKS_WAKE_EN0_CLK_SYS_PIO1_BITS _u(0x00002000) -#define CLOCKS_WAKE_EN0_CLK_SYS_PIO1_MSB _u(13) -#define CLOCKS_WAKE_EN0_CLK_SYS_PIO1_LSB _u(13) -#define CLOCKS_WAKE_EN0_CLK_SYS_PIO1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_WAKE_EN0_CLK_SYS_PIO0 -#define CLOCKS_WAKE_EN0_CLK_SYS_PIO0_RESET _u(0x1) -#define CLOCKS_WAKE_EN0_CLK_SYS_PIO0_BITS _u(0x00001000) -#define CLOCKS_WAKE_EN0_CLK_SYS_PIO0_MSB _u(12) -#define CLOCKS_WAKE_EN0_CLK_SYS_PIO0_LSB _u(12) -#define CLOCKS_WAKE_EN0_CLK_SYS_PIO0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_WAKE_EN0_CLK_SYS_PADS -#define CLOCKS_WAKE_EN0_CLK_SYS_PADS_RESET _u(0x1) -#define CLOCKS_WAKE_EN0_CLK_SYS_PADS_BITS _u(0x00000800) -#define CLOCKS_WAKE_EN0_CLK_SYS_PADS_MSB _u(11) -#define CLOCKS_WAKE_EN0_CLK_SYS_PADS_LSB _u(11) -#define CLOCKS_WAKE_EN0_CLK_SYS_PADS_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_WAKE_EN0_CLK_SYS_VREG_AND_CHIP_RESET -#define CLOCKS_WAKE_EN0_CLK_SYS_VREG_AND_CHIP_RESET_RESET _u(0x1) -#define CLOCKS_WAKE_EN0_CLK_SYS_VREG_AND_CHIP_RESET_BITS _u(0x00000400) -#define CLOCKS_WAKE_EN0_CLK_SYS_VREG_AND_CHIP_RESET_MSB _u(10) -#define CLOCKS_WAKE_EN0_CLK_SYS_VREG_AND_CHIP_RESET_LSB _u(10) -#define CLOCKS_WAKE_EN0_CLK_SYS_VREG_AND_CHIP_RESET_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_WAKE_EN0_CLK_SYS_JTAG -#define CLOCKS_WAKE_EN0_CLK_SYS_JTAG_RESET _u(0x1) -#define CLOCKS_WAKE_EN0_CLK_SYS_JTAG_BITS _u(0x00000200) -#define CLOCKS_WAKE_EN0_CLK_SYS_JTAG_MSB _u(9) -#define CLOCKS_WAKE_EN0_CLK_SYS_JTAG_LSB _u(9) -#define CLOCKS_WAKE_EN0_CLK_SYS_JTAG_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_WAKE_EN0_CLK_SYS_IO -#define CLOCKS_WAKE_EN0_CLK_SYS_IO_RESET _u(0x1) -#define CLOCKS_WAKE_EN0_CLK_SYS_IO_BITS _u(0x00000100) -#define CLOCKS_WAKE_EN0_CLK_SYS_IO_MSB _u(8) -#define CLOCKS_WAKE_EN0_CLK_SYS_IO_LSB _u(8) -#define CLOCKS_WAKE_EN0_CLK_SYS_IO_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_WAKE_EN0_CLK_SYS_I2C1 -#define CLOCKS_WAKE_EN0_CLK_SYS_I2C1_RESET _u(0x1) -#define CLOCKS_WAKE_EN0_CLK_SYS_I2C1_BITS _u(0x00000080) -#define CLOCKS_WAKE_EN0_CLK_SYS_I2C1_MSB _u(7) -#define CLOCKS_WAKE_EN0_CLK_SYS_I2C1_LSB _u(7) -#define CLOCKS_WAKE_EN0_CLK_SYS_I2C1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_WAKE_EN0_CLK_SYS_I2C0 -#define CLOCKS_WAKE_EN0_CLK_SYS_I2C0_RESET _u(0x1) -#define CLOCKS_WAKE_EN0_CLK_SYS_I2C0_BITS _u(0x00000040) -#define CLOCKS_WAKE_EN0_CLK_SYS_I2C0_MSB _u(6) -#define CLOCKS_WAKE_EN0_CLK_SYS_I2C0_LSB _u(6) -#define CLOCKS_WAKE_EN0_CLK_SYS_I2C0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_WAKE_EN0_CLK_SYS_DMA -#define CLOCKS_WAKE_EN0_CLK_SYS_DMA_RESET _u(0x1) -#define CLOCKS_WAKE_EN0_CLK_SYS_DMA_BITS _u(0x00000020) -#define CLOCKS_WAKE_EN0_CLK_SYS_DMA_MSB _u(5) -#define CLOCKS_WAKE_EN0_CLK_SYS_DMA_LSB _u(5) -#define CLOCKS_WAKE_EN0_CLK_SYS_DMA_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_WAKE_EN0_CLK_SYS_BUSFABRIC -#define CLOCKS_WAKE_EN0_CLK_SYS_BUSFABRIC_RESET _u(0x1) -#define CLOCKS_WAKE_EN0_CLK_SYS_BUSFABRIC_BITS _u(0x00000010) -#define CLOCKS_WAKE_EN0_CLK_SYS_BUSFABRIC_MSB _u(4) -#define CLOCKS_WAKE_EN0_CLK_SYS_BUSFABRIC_LSB _u(4) -#define CLOCKS_WAKE_EN0_CLK_SYS_BUSFABRIC_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_WAKE_EN0_CLK_SYS_BUSCTRL -#define CLOCKS_WAKE_EN0_CLK_SYS_BUSCTRL_RESET _u(0x1) -#define CLOCKS_WAKE_EN0_CLK_SYS_BUSCTRL_BITS _u(0x00000008) -#define CLOCKS_WAKE_EN0_CLK_SYS_BUSCTRL_MSB _u(3) -#define CLOCKS_WAKE_EN0_CLK_SYS_BUSCTRL_LSB _u(3) -#define CLOCKS_WAKE_EN0_CLK_SYS_BUSCTRL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_WAKE_EN0_CLK_SYS_ADC -#define CLOCKS_WAKE_EN0_CLK_SYS_ADC_RESET _u(0x1) -#define CLOCKS_WAKE_EN0_CLK_SYS_ADC_BITS _u(0x00000004) -#define CLOCKS_WAKE_EN0_CLK_SYS_ADC_MSB _u(2) -#define CLOCKS_WAKE_EN0_CLK_SYS_ADC_LSB _u(2) -#define CLOCKS_WAKE_EN0_CLK_SYS_ADC_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_WAKE_EN0_CLK_ADC_ADC -#define CLOCKS_WAKE_EN0_CLK_ADC_ADC_RESET _u(0x1) -#define CLOCKS_WAKE_EN0_CLK_ADC_ADC_BITS _u(0x00000002) -#define CLOCKS_WAKE_EN0_CLK_ADC_ADC_MSB _u(1) -#define CLOCKS_WAKE_EN0_CLK_ADC_ADC_LSB _u(1) -#define CLOCKS_WAKE_EN0_CLK_ADC_ADC_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_WAKE_EN0_CLK_SYS_CLOCKS -#define CLOCKS_WAKE_EN0_CLK_SYS_CLOCKS_RESET _u(0x1) -#define CLOCKS_WAKE_EN0_CLK_SYS_CLOCKS_BITS _u(0x00000001) -#define CLOCKS_WAKE_EN0_CLK_SYS_CLOCKS_MSB _u(0) -#define CLOCKS_WAKE_EN0_CLK_SYS_CLOCKS_LSB _u(0) -#define CLOCKS_WAKE_EN0_CLK_SYS_CLOCKS_ACCESS "RW" -// ============================================================================= -// Register : CLOCKS_WAKE_EN1 -// Description : enable clock in wake mode -#define CLOCKS_WAKE_EN1_OFFSET _u(0x000000a4) -#define CLOCKS_WAKE_EN1_BITS _u(0x00007fff) -#define CLOCKS_WAKE_EN1_RESET _u(0x00007fff) -// ----------------------------------------------------------------------------- -// Field : CLOCKS_WAKE_EN1_CLK_SYS_XOSC -#define CLOCKS_WAKE_EN1_CLK_SYS_XOSC_RESET _u(0x1) -#define CLOCKS_WAKE_EN1_CLK_SYS_XOSC_BITS _u(0x00004000) -#define CLOCKS_WAKE_EN1_CLK_SYS_XOSC_MSB _u(14) -#define CLOCKS_WAKE_EN1_CLK_SYS_XOSC_LSB _u(14) -#define CLOCKS_WAKE_EN1_CLK_SYS_XOSC_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_WAKE_EN1_CLK_SYS_XIP -#define CLOCKS_WAKE_EN1_CLK_SYS_XIP_RESET _u(0x1) -#define CLOCKS_WAKE_EN1_CLK_SYS_XIP_BITS _u(0x00002000) -#define CLOCKS_WAKE_EN1_CLK_SYS_XIP_MSB _u(13) -#define CLOCKS_WAKE_EN1_CLK_SYS_XIP_LSB _u(13) -#define CLOCKS_WAKE_EN1_CLK_SYS_XIP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_WAKE_EN1_CLK_SYS_WATCHDOG -#define CLOCKS_WAKE_EN1_CLK_SYS_WATCHDOG_RESET _u(0x1) -#define CLOCKS_WAKE_EN1_CLK_SYS_WATCHDOG_BITS _u(0x00001000) -#define CLOCKS_WAKE_EN1_CLK_SYS_WATCHDOG_MSB _u(12) -#define CLOCKS_WAKE_EN1_CLK_SYS_WATCHDOG_LSB _u(12) -#define CLOCKS_WAKE_EN1_CLK_SYS_WATCHDOG_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_WAKE_EN1_CLK_USB_USBCTRL -#define CLOCKS_WAKE_EN1_CLK_USB_USBCTRL_RESET _u(0x1) -#define CLOCKS_WAKE_EN1_CLK_USB_USBCTRL_BITS _u(0x00000800) -#define CLOCKS_WAKE_EN1_CLK_USB_USBCTRL_MSB _u(11) -#define CLOCKS_WAKE_EN1_CLK_USB_USBCTRL_LSB _u(11) -#define CLOCKS_WAKE_EN1_CLK_USB_USBCTRL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_WAKE_EN1_CLK_SYS_USBCTRL -#define CLOCKS_WAKE_EN1_CLK_SYS_USBCTRL_RESET _u(0x1) -#define CLOCKS_WAKE_EN1_CLK_SYS_USBCTRL_BITS _u(0x00000400) -#define CLOCKS_WAKE_EN1_CLK_SYS_USBCTRL_MSB _u(10) -#define CLOCKS_WAKE_EN1_CLK_SYS_USBCTRL_LSB _u(10) -#define CLOCKS_WAKE_EN1_CLK_SYS_USBCTRL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_WAKE_EN1_CLK_SYS_UART1 -#define CLOCKS_WAKE_EN1_CLK_SYS_UART1_RESET _u(0x1) -#define CLOCKS_WAKE_EN1_CLK_SYS_UART1_BITS _u(0x00000200) -#define CLOCKS_WAKE_EN1_CLK_SYS_UART1_MSB _u(9) -#define CLOCKS_WAKE_EN1_CLK_SYS_UART1_LSB _u(9) -#define CLOCKS_WAKE_EN1_CLK_SYS_UART1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_WAKE_EN1_CLK_PERI_UART1 -#define CLOCKS_WAKE_EN1_CLK_PERI_UART1_RESET _u(0x1) -#define CLOCKS_WAKE_EN1_CLK_PERI_UART1_BITS _u(0x00000100) -#define CLOCKS_WAKE_EN1_CLK_PERI_UART1_MSB _u(8) -#define CLOCKS_WAKE_EN1_CLK_PERI_UART1_LSB _u(8) -#define CLOCKS_WAKE_EN1_CLK_PERI_UART1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_WAKE_EN1_CLK_SYS_UART0 -#define CLOCKS_WAKE_EN1_CLK_SYS_UART0_RESET _u(0x1) -#define CLOCKS_WAKE_EN1_CLK_SYS_UART0_BITS _u(0x00000080) -#define CLOCKS_WAKE_EN1_CLK_SYS_UART0_MSB _u(7) -#define CLOCKS_WAKE_EN1_CLK_SYS_UART0_LSB _u(7) -#define CLOCKS_WAKE_EN1_CLK_SYS_UART0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_WAKE_EN1_CLK_PERI_UART0 -#define CLOCKS_WAKE_EN1_CLK_PERI_UART0_RESET _u(0x1) -#define CLOCKS_WAKE_EN1_CLK_PERI_UART0_BITS _u(0x00000040) -#define CLOCKS_WAKE_EN1_CLK_PERI_UART0_MSB _u(6) -#define CLOCKS_WAKE_EN1_CLK_PERI_UART0_LSB _u(6) -#define CLOCKS_WAKE_EN1_CLK_PERI_UART0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_WAKE_EN1_CLK_SYS_TIMER -#define CLOCKS_WAKE_EN1_CLK_SYS_TIMER_RESET _u(0x1) -#define CLOCKS_WAKE_EN1_CLK_SYS_TIMER_BITS _u(0x00000020) -#define CLOCKS_WAKE_EN1_CLK_SYS_TIMER_MSB _u(5) -#define CLOCKS_WAKE_EN1_CLK_SYS_TIMER_LSB _u(5) -#define CLOCKS_WAKE_EN1_CLK_SYS_TIMER_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_WAKE_EN1_CLK_SYS_TBMAN -#define CLOCKS_WAKE_EN1_CLK_SYS_TBMAN_RESET _u(0x1) -#define CLOCKS_WAKE_EN1_CLK_SYS_TBMAN_BITS _u(0x00000010) -#define CLOCKS_WAKE_EN1_CLK_SYS_TBMAN_MSB _u(4) -#define CLOCKS_WAKE_EN1_CLK_SYS_TBMAN_LSB _u(4) -#define CLOCKS_WAKE_EN1_CLK_SYS_TBMAN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_WAKE_EN1_CLK_SYS_SYSINFO -#define CLOCKS_WAKE_EN1_CLK_SYS_SYSINFO_RESET _u(0x1) -#define CLOCKS_WAKE_EN1_CLK_SYS_SYSINFO_BITS _u(0x00000008) -#define CLOCKS_WAKE_EN1_CLK_SYS_SYSINFO_MSB _u(3) -#define CLOCKS_WAKE_EN1_CLK_SYS_SYSINFO_LSB _u(3) -#define CLOCKS_WAKE_EN1_CLK_SYS_SYSINFO_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_WAKE_EN1_CLK_SYS_SYSCFG -#define CLOCKS_WAKE_EN1_CLK_SYS_SYSCFG_RESET _u(0x1) -#define CLOCKS_WAKE_EN1_CLK_SYS_SYSCFG_BITS _u(0x00000004) -#define CLOCKS_WAKE_EN1_CLK_SYS_SYSCFG_MSB _u(2) -#define CLOCKS_WAKE_EN1_CLK_SYS_SYSCFG_LSB _u(2) -#define CLOCKS_WAKE_EN1_CLK_SYS_SYSCFG_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_WAKE_EN1_CLK_SYS_SRAM5 -#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM5_RESET _u(0x1) -#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM5_BITS _u(0x00000002) -#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM5_MSB _u(1) -#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM5_LSB _u(1) -#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM5_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_WAKE_EN1_CLK_SYS_SRAM4 -#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM4_RESET _u(0x1) -#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM4_BITS _u(0x00000001) -#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM4_MSB _u(0) -#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM4_LSB _u(0) -#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM4_ACCESS "RW" -// ============================================================================= -// Register : CLOCKS_SLEEP_EN0 -// Description : enable clock in sleep mode -#define CLOCKS_SLEEP_EN0_OFFSET _u(0x000000a8) -#define CLOCKS_SLEEP_EN0_BITS _u(0xffffffff) -#define CLOCKS_SLEEP_EN0_RESET _u(0xffffffff) -// ----------------------------------------------------------------------------- -// Field : CLOCKS_SLEEP_EN0_CLK_SYS_SRAM3 -#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM3_RESET _u(0x1) -#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM3_BITS _u(0x80000000) -#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM3_MSB _u(31) -#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM3_LSB _u(31) -#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM3_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_SLEEP_EN0_CLK_SYS_SRAM2 -#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM2_RESET _u(0x1) -#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM2_BITS _u(0x40000000) -#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM2_MSB _u(30) -#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM2_LSB _u(30) -#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM2_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_SLEEP_EN0_CLK_SYS_SRAM1 -#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM1_RESET _u(0x1) -#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM1_BITS _u(0x20000000) -#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM1_MSB _u(29) -#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM1_LSB _u(29) -#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_SLEEP_EN0_CLK_SYS_SRAM0 -#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM0_RESET _u(0x1) -#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM0_BITS _u(0x10000000) -#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM0_MSB _u(28) -#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM0_LSB _u(28) -#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_SLEEP_EN0_CLK_SYS_SPI1 -#define CLOCKS_SLEEP_EN0_CLK_SYS_SPI1_RESET _u(0x1) -#define CLOCKS_SLEEP_EN0_CLK_SYS_SPI1_BITS _u(0x08000000) -#define CLOCKS_SLEEP_EN0_CLK_SYS_SPI1_MSB _u(27) -#define CLOCKS_SLEEP_EN0_CLK_SYS_SPI1_LSB _u(27) -#define CLOCKS_SLEEP_EN0_CLK_SYS_SPI1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_SLEEP_EN0_CLK_PERI_SPI1 -#define CLOCKS_SLEEP_EN0_CLK_PERI_SPI1_RESET _u(0x1) -#define CLOCKS_SLEEP_EN0_CLK_PERI_SPI1_BITS _u(0x04000000) -#define CLOCKS_SLEEP_EN0_CLK_PERI_SPI1_MSB _u(26) -#define CLOCKS_SLEEP_EN0_CLK_PERI_SPI1_LSB _u(26) -#define CLOCKS_SLEEP_EN0_CLK_PERI_SPI1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_SLEEP_EN0_CLK_SYS_SPI0 -#define CLOCKS_SLEEP_EN0_CLK_SYS_SPI0_RESET _u(0x1) -#define CLOCKS_SLEEP_EN0_CLK_SYS_SPI0_BITS _u(0x02000000) -#define CLOCKS_SLEEP_EN0_CLK_SYS_SPI0_MSB _u(25) -#define CLOCKS_SLEEP_EN0_CLK_SYS_SPI0_LSB _u(25) -#define CLOCKS_SLEEP_EN0_CLK_SYS_SPI0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_SLEEP_EN0_CLK_PERI_SPI0 -#define CLOCKS_SLEEP_EN0_CLK_PERI_SPI0_RESET _u(0x1) -#define CLOCKS_SLEEP_EN0_CLK_PERI_SPI0_BITS _u(0x01000000) -#define CLOCKS_SLEEP_EN0_CLK_PERI_SPI0_MSB _u(24) -#define CLOCKS_SLEEP_EN0_CLK_PERI_SPI0_LSB _u(24) -#define CLOCKS_SLEEP_EN0_CLK_PERI_SPI0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_SLEEP_EN0_CLK_SYS_SIO -#define CLOCKS_SLEEP_EN0_CLK_SYS_SIO_RESET _u(0x1) -#define CLOCKS_SLEEP_EN0_CLK_SYS_SIO_BITS _u(0x00800000) -#define CLOCKS_SLEEP_EN0_CLK_SYS_SIO_MSB _u(23) -#define CLOCKS_SLEEP_EN0_CLK_SYS_SIO_LSB _u(23) -#define CLOCKS_SLEEP_EN0_CLK_SYS_SIO_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_SLEEP_EN0_CLK_SYS_RTC -#define CLOCKS_SLEEP_EN0_CLK_SYS_RTC_RESET _u(0x1) -#define CLOCKS_SLEEP_EN0_CLK_SYS_RTC_BITS _u(0x00400000) -#define CLOCKS_SLEEP_EN0_CLK_SYS_RTC_MSB _u(22) -#define CLOCKS_SLEEP_EN0_CLK_SYS_RTC_LSB _u(22) -#define CLOCKS_SLEEP_EN0_CLK_SYS_RTC_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_SLEEP_EN0_CLK_RTC_RTC -#define CLOCKS_SLEEP_EN0_CLK_RTC_RTC_RESET _u(0x1) -#define CLOCKS_SLEEP_EN0_CLK_RTC_RTC_BITS _u(0x00200000) -#define CLOCKS_SLEEP_EN0_CLK_RTC_RTC_MSB _u(21) -#define CLOCKS_SLEEP_EN0_CLK_RTC_RTC_LSB _u(21) -#define CLOCKS_SLEEP_EN0_CLK_RTC_RTC_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_SLEEP_EN0_CLK_SYS_ROSC -#define CLOCKS_SLEEP_EN0_CLK_SYS_ROSC_RESET _u(0x1) -#define CLOCKS_SLEEP_EN0_CLK_SYS_ROSC_BITS _u(0x00100000) -#define CLOCKS_SLEEP_EN0_CLK_SYS_ROSC_MSB _u(20) -#define CLOCKS_SLEEP_EN0_CLK_SYS_ROSC_LSB _u(20) -#define CLOCKS_SLEEP_EN0_CLK_SYS_ROSC_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_SLEEP_EN0_CLK_SYS_ROM -#define CLOCKS_SLEEP_EN0_CLK_SYS_ROM_RESET _u(0x1) -#define CLOCKS_SLEEP_EN0_CLK_SYS_ROM_BITS _u(0x00080000) -#define CLOCKS_SLEEP_EN0_CLK_SYS_ROM_MSB _u(19) -#define CLOCKS_SLEEP_EN0_CLK_SYS_ROM_LSB _u(19) -#define CLOCKS_SLEEP_EN0_CLK_SYS_ROM_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_SLEEP_EN0_CLK_SYS_RESETS -#define CLOCKS_SLEEP_EN0_CLK_SYS_RESETS_RESET _u(0x1) -#define CLOCKS_SLEEP_EN0_CLK_SYS_RESETS_BITS _u(0x00040000) -#define CLOCKS_SLEEP_EN0_CLK_SYS_RESETS_MSB _u(18) -#define CLOCKS_SLEEP_EN0_CLK_SYS_RESETS_LSB _u(18) -#define CLOCKS_SLEEP_EN0_CLK_SYS_RESETS_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_SLEEP_EN0_CLK_SYS_PWM -#define CLOCKS_SLEEP_EN0_CLK_SYS_PWM_RESET _u(0x1) -#define CLOCKS_SLEEP_EN0_CLK_SYS_PWM_BITS _u(0x00020000) -#define CLOCKS_SLEEP_EN0_CLK_SYS_PWM_MSB _u(17) -#define CLOCKS_SLEEP_EN0_CLK_SYS_PWM_LSB _u(17) -#define CLOCKS_SLEEP_EN0_CLK_SYS_PWM_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_SLEEP_EN0_CLK_SYS_PSM -#define CLOCKS_SLEEP_EN0_CLK_SYS_PSM_RESET _u(0x1) -#define CLOCKS_SLEEP_EN0_CLK_SYS_PSM_BITS _u(0x00010000) -#define CLOCKS_SLEEP_EN0_CLK_SYS_PSM_MSB _u(16) -#define CLOCKS_SLEEP_EN0_CLK_SYS_PSM_LSB _u(16) -#define CLOCKS_SLEEP_EN0_CLK_SYS_PSM_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_SLEEP_EN0_CLK_SYS_PLL_USB -#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_USB_RESET _u(0x1) -#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_USB_BITS _u(0x00008000) -#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_USB_MSB _u(15) -#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_USB_LSB _u(15) -#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_USB_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_SLEEP_EN0_CLK_SYS_PLL_SYS -#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_SYS_RESET _u(0x1) -#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_SYS_BITS _u(0x00004000) -#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_SYS_MSB _u(14) -#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_SYS_LSB _u(14) -#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_SYS_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_SLEEP_EN0_CLK_SYS_PIO1 -#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO1_RESET _u(0x1) -#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO1_BITS _u(0x00002000) -#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO1_MSB _u(13) -#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO1_LSB _u(13) -#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_SLEEP_EN0_CLK_SYS_PIO0 -#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO0_RESET _u(0x1) -#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO0_BITS _u(0x00001000) -#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO0_MSB _u(12) -#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO0_LSB _u(12) -#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_SLEEP_EN0_CLK_SYS_PADS -#define CLOCKS_SLEEP_EN0_CLK_SYS_PADS_RESET _u(0x1) -#define CLOCKS_SLEEP_EN0_CLK_SYS_PADS_BITS _u(0x00000800) -#define CLOCKS_SLEEP_EN0_CLK_SYS_PADS_MSB _u(11) -#define CLOCKS_SLEEP_EN0_CLK_SYS_PADS_LSB _u(11) -#define CLOCKS_SLEEP_EN0_CLK_SYS_PADS_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_SLEEP_EN0_CLK_SYS_VREG_AND_CHIP_RESET -#define CLOCKS_SLEEP_EN0_CLK_SYS_VREG_AND_CHIP_RESET_RESET _u(0x1) -#define CLOCKS_SLEEP_EN0_CLK_SYS_VREG_AND_CHIP_RESET_BITS _u(0x00000400) -#define CLOCKS_SLEEP_EN0_CLK_SYS_VREG_AND_CHIP_RESET_MSB _u(10) -#define CLOCKS_SLEEP_EN0_CLK_SYS_VREG_AND_CHIP_RESET_LSB _u(10) -#define CLOCKS_SLEEP_EN0_CLK_SYS_VREG_AND_CHIP_RESET_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_SLEEP_EN0_CLK_SYS_JTAG -#define CLOCKS_SLEEP_EN0_CLK_SYS_JTAG_RESET _u(0x1) -#define CLOCKS_SLEEP_EN0_CLK_SYS_JTAG_BITS _u(0x00000200) -#define CLOCKS_SLEEP_EN0_CLK_SYS_JTAG_MSB _u(9) -#define CLOCKS_SLEEP_EN0_CLK_SYS_JTAG_LSB _u(9) -#define CLOCKS_SLEEP_EN0_CLK_SYS_JTAG_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_SLEEP_EN0_CLK_SYS_IO -#define CLOCKS_SLEEP_EN0_CLK_SYS_IO_RESET _u(0x1) -#define CLOCKS_SLEEP_EN0_CLK_SYS_IO_BITS _u(0x00000100) -#define CLOCKS_SLEEP_EN0_CLK_SYS_IO_MSB _u(8) -#define CLOCKS_SLEEP_EN0_CLK_SYS_IO_LSB _u(8) -#define CLOCKS_SLEEP_EN0_CLK_SYS_IO_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_SLEEP_EN0_CLK_SYS_I2C1 -#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C1_RESET _u(0x1) -#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C1_BITS _u(0x00000080) -#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C1_MSB _u(7) -#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C1_LSB _u(7) -#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_SLEEP_EN0_CLK_SYS_I2C0 -#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C0_RESET _u(0x1) -#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C0_BITS _u(0x00000040) -#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C0_MSB _u(6) -#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C0_LSB _u(6) -#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_SLEEP_EN0_CLK_SYS_DMA -#define CLOCKS_SLEEP_EN0_CLK_SYS_DMA_RESET _u(0x1) -#define CLOCKS_SLEEP_EN0_CLK_SYS_DMA_BITS _u(0x00000020) -#define CLOCKS_SLEEP_EN0_CLK_SYS_DMA_MSB _u(5) -#define CLOCKS_SLEEP_EN0_CLK_SYS_DMA_LSB _u(5) -#define CLOCKS_SLEEP_EN0_CLK_SYS_DMA_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_SLEEP_EN0_CLK_SYS_BUSFABRIC -#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSFABRIC_RESET _u(0x1) -#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSFABRIC_BITS _u(0x00000010) -#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSFABRIC_MSB _u(4) -#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSFABRIC_LSB _u(4) -#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSFABRIC_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_SLEEP_EN0_CLK_SYS_BUSCTRL -#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSCTRL_RESET _u(0x1) -#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSCTRL_BITS _u(0x00000008) -#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSCTRL_MSB _u(3) -#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSCTRL_LSB _u(3) -#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSCTRL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_SLEEP_EN0_CLK_SYS_ADC -#define CLOCKS_SLEEP_EN0_CLK_SYS_ADC_RESET _u(0x1) -#define CLOCKS_SLEEP_EN0_CLK_SYS_ADC_BITS _u(0x00000004) -#define CLOCKS_SLEEP_EN0_CLK_SYS_ADC_MSB _u(2) -#define CLOCKS_SLEEP_EN0_CLK_SYS_ADC_LSB _u(2) -#define CLOCKS_SLEEP_EN0_CLK_SYS_ADC_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_SLEEP_EN0_CLK_ADC_ADC -#define CLOCKS_SLEEP_EN0_CLK_ADC_ADC_RESET _u(0x1) -#define CLOCKS_SLEEP_EN0_CLK_ADC_ADC_BITS _u(0x00000002) -#define CLOCKS_SLEEP_EN0_CLK_ADC_ADC_MSB _u(1) -#define CLOCKS_SLEEP_EN0_CLK_ADC_ADC_LSB _u(1) -#define CLOCKS_SLEEP_EN0_CLK_ADC_ADC_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_SLEEP_EN0_CLK_SYS_CLOCKS -#define CLOCKS_SLEEP_EN0_CLK_SYS_CLOCKS_RESET _u(0x1) -#define CLOCKS_SLEEP_EN0_CLK_SYS_CLOCKS_BITS _u(0x00000001) -#define CLOCKS_SLEEP_EN0_CLK_SYS_CLOCKS_MSB _u(0) -#define CLOCKS_SLEEP_EN0_CLK_SYS_CLOCKS_LSB _u(0) -#define CLOCKS_SLEEP_EN0_CLK_SYS_CLOCKS_ACCESS "RW" -// ============================================================================= -// Register : CLOCKS_SLEEP_EN1 -// Description : enable clock in sleep mode -#define CLOCKS_SLEEP_EN1_OFFSET _u(0x000000ac) -#define CLOCKS_SLEEP_EN1_BITS _u(0x00007fff) -#define CLOCKS_SLEEP_EN1_RESET _u(0x00007fff) -// ----------------------------------------------------------------------------- -// Field : CLOCKS_SLEEP_EN1_CLK_SYS_XOSC -#define CLOCKS_SLEEP_EN1_CLK_SYS_XOSC_RESET _u(0x1) -#define CLOCKS_SLEEP_EN1_CLK_SYS_XOSC_BITS _u(0x00004000) -#define CLOCKS_SLEEP_EN1_CLK_SYS_XOSC_MSB _u(14) -#define CLOCKS_SLEEP_EN1_CLK_SYS_XOSC_LSB _u(14) -#define CLOCKS_SLEEP_EN1_CLK_SYS_XOSC_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_SLEEP_EN1_CLK_SYS_XIP -#define CLOCKS_SLEEP_EN1_CLK_SYS_XIP_RESET _u(0x1) -#define CLOCKS_SLEEP_EN1_CLK_SYS_XIP_BITS _u(0x00002000) -#define CLOCKS_SLEEP_EN1_CLK_SYS_XIP_MSB _u(13) -#define CLOCKS_SLEEP_EN1_CLK_SYS_XIP_LSB _u(13) -#define CLOCKS_SLEEP_EN1_CLK_SYS_XIP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_SLEEP_EN1_CLK_SYS_WATCHDOG -#define CLOCKS_SLEEP_EN1_CLK_SYS_WATCHDOG_RESET _u(0x1) -#define CLOCKS_SLEEP_EN1_CLK_SYS_WATCHDOG_BITS _u(0x00001000) -#define CLOCKS_SLEEP_EN1_CLK_SYS_WATCHDOG_MSB _u(12) -#define CLOCKS_SLEEP_EN1_CLK_SYS_WATCHDOG_LSB _u(12) -#define CLOCKS_SLEEP_EN1_CLK_SYS_WATCHDOG_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_SLEEP_EN1_CLK_USB_USBCTRL -#define CLOCKS_SLEEP_EN1_CLK_USB_USBCTRL_RESET _u(0x1) -#define CLOCKS_SLEEP_EN1_CLK_USB_USBCTRL_BITS _u(0x00000800) -#define CLOCKS_SLEEP_EN1_CLK_USB_USBCTRL_MSB _u(11) -#define CLOCKS_SLEEP_EN1_CLK_USB_USBCTRL_LSB _u(11) -#define CLOCKS_SLEEP_EN1_CLK_USB_USBCTRL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_SLEEP_EN1_CLK_SYS_USBCTRL -#define CLOCKS_SLEEP_EN1_CLK_SYS_USBCTRL_RESET _u(0x1) -#define CLOCKS_SLEEP_EN1_CLK_SYS_USBCTRL_BITS _u(0x00000400) -#define CLOCKS_SLEEP_EN1_CLK_SYS_USBCTRL_MSB _u(10) -#define CLOCKS_SLEEP_EN1_CLK_SYS_USBCTRL_LSB _u(10) -#define CLOCKS_SLEEP_EN1_CLK_SYS_USBCTRL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_SLEEP_EN1_CLK_SYS_UART1 -#define CLOCKS_SLEEP_EN1_CLK_SYS_UART1_RESET _u(0x1) -#define CLOCKS_SLEEP_EN1_CLK_SYS_UART1_BITS _u(0x00000200) -#define CLOCKS_SLEEP_EN1_CLK_SYS_UART1_MSB _u(9) -#define CLOCKS_SLEEP_EN1_CLK_SYS_UART1_LSB _u(9) -#define CLOCKS_SLEEP_EN1_CLK_SYS_UART1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_SLEEP_EN1_CLK_PERI_UART1 -#define CLOCKS_SLEEP_EN1_CLK_PERI_UART1_RESET _u(0x1) -#define CLOCKS_SLEEP_EN1_CLK_PERI_UART1_BITS _u(0x00000100) -#define CLOCKS_SLEEP_EN1_CLK_PERI_UART1_MSB _u(8) -#define CLOCKS_SLEEP_EN1_CLK_PERI_UART1_LSB _u(8) -#define CLOCKS_SLEEP_EN1_CLK_PERI_UART1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_SLEEP_EN1_CLK_SYS_UART0 -#define CLOCKS_SLEEP_EN1_CLK_SYS_UART0_RESET _u(0x1) -#define CLOCKS_SLEEP_EN1_CLK_SYS_UART0_BITS _u(0x00000080) -#define CLOCKS_SLEEP_EN1_CLK_SYS_UART0_MSB _u(7) -#define CLOCKS_SLEEP_EN1_CLK_SYS_UART0_LSB _u(7) -#define CLOCKS_SLEEP_EN1_CLK_SYS_UART0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_SLEEP_EN1_CLK_PERI_UART0 -#define CLOCKS_SLEEP_EN1_CLK_PERI_UART0_RESET _u(0x1) -#define CLOCKS_SLEEP_EN1_CLK_PERI_UART0_BITS _u(0x00000040) -#define CLOCKS_SLEEP_EN1_CLK_PERI_UART0_MSB _u(6) -#define CLOCKS_SLEEP_EN1_CLK_PERI_UART0_LSB _u(6) -#define CLOCKS_SLEEP_EN1_CLK_PERI_UART0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_SLEEP_EN1_CLK_SYS_TIMER -#define CLOCKS_SLEEP_EN1_CLK_SYS_TIMER_RESET _u(0x1) -#define CLOCKS_SLEEP_EN1_CLK_SYS_TIMER_BITS _u(0x00000020) -#define CLOCKS_SLEEP_EN1_CLK_SYS_TIMER_MSB _u(5) -#define CLOCKS_SLEEP_EN1_CLK_SYS_TIMER_LSB _u(5) -#define CLOCKS_SLEEP_EN1_CLK_SYS_TIMER_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_SLEEP_EN1_CLK_SYS_TBMAN -#define CLOCKS_SLEEP_EN1_CLK_SYS_TBMAN_RESET _u(0x1) -#define CLOCKS_SLEEP_EN1_CLK_SYS_TBMAN_BITS _u(0x00000010) -#define CLOCKS_SLEEP_EN1_CLK_SYS_TBMAN_MSB _u(4) -#define CLOCKS_SLEEP_EN1_CLK_SYS_TBMAN_LSB _u(4) -#define CLOCKS_SLEEP_EN1_CLK_SYS_TBMAN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_SLEEP_EN1_CLK_SYS_SYSINFO -#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSINFO_RESET _u(0x1) -#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSINFO_BITS _u(0x00000008) -#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSINFO_MSB _u(3) -#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSINFO_LSB _u(3) -#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSINFO_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_SLEEP_EN1_CLK_SYS_SYSCFG -#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSCFG_RESET _u(0x1) -#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSCFG_BITS _u(0x00000004) -#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSCFG_MSB _u(2) -#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSCFG_LSB _u(2) -#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSCFG_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_SLEEP_EN1_CLK_SYS_SRAM5 -#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM5_RESET _u(0x1) -#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM5_BITS _u(0x00000002) -#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM5_MSB _u(1) -#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM5_LSB _u(1) -#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM5_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_SLEEP_EN1_CLK_SYS_SRAM4 -#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM4_RESET _u(0x1) -#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM4_BITS _u(0x00000001) -#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM4_MSB _u(0) -#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM4_LSB _u(0) -#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM4_ACCESS "RW" -// ============================================================================= -// Register : CLOCKS_ENABLED0 -// Description : indicates the state of the clock enable -#define CLOCKS_ENABLED0_OFFSET _u(0x000000b0) -#define CLOCKS_ENABLED0_BITS _u(0xffffffff) -#define CLOCKS_ENABLED0_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : CLOCKS_ENABLED0_CLK_SYS_SRAM3 -#define CLOCKS_ENABLED0_CLK_SYS_SRAM3_RESET _u(0x0) -#define CLOCKS_ENABLED0_CLK_SYS_SRAM3_BITS _u(0x80000000) -#define CLOCKS_ENABLED0_CLK_SYS_SRAM3_MSB _u(31) -#define CLOCKS_ENABLED0_CLK_SYS_SRAM3_LSB _u(31) -#define CLOCKS_ENABLED0_CLK_SYS_SRAM3_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_ENABLED0_CLK_SYS_SRAM2 -#define CLOCKS_ENABLED0_CLK_SYS_SRAM2_RESET _u(0x0) -#define CLOCKS_ENABLED0_CLK_SYS_SRAM2_BITS _u(0x40000000) -#define CLOCKS_ENABLED0_CLK_SYS_SRAM2_MSB _u(30) -#define CLOCKS_ENABLED0_CLK_SYS_SRAM2_LSB _u(30) -#define CLOCKS_ENABLED0_CLK_SYS_SRAM2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_ENABLED0_CLK_SYS_SRAM1 -#define CLOCKS_ENABLED0_CLK_SYS_SRAM1_RESET _u(0x0) -#define CLOCKS_ENABLED0_CLK_SYS_SRAM1_BITS _u(0x20000000) -#define CLOCKS_ENABLED0_CLK_SYS_SRAM1_MSB _u(29) -#define CLOCKS_ENABLED0_CLK_SYS_SRAM1_LSB _u(29) -#define CLOCKS_ENABLED0_CLK_SYS_SRAM1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_ENABLED0_CLK_SYS_SRAM0 -#define CLOCKS_ENABLED0_CLK_SYS_SRAM0_RESET _u(0x0) -#define CLOCKS_ENABLED0_CLK_SYS_SRAM0_BITS _u(0x10000000) -#define CLOCKS_ENABLED0_CLK_SYS_SRAM0_MSB _u(28) -#define CLOCKS_ENABLED0_CLK_SYS_SRAM0_LSB _u(28) -#define CLOCKS_ENABLED0_CLK_SYS_SRAM0_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_ENABLED0_CLK_SYS_SPI1 -#define CLOCKS_ENABLED0_CLK_SYS_SPI1_RESET _u(0x0) -#define CLOCKS_ENABLED0_CLK_SYS_SPI1_BITS _u(0x08000000) -#define CLOCKS_ENABLED0_CLK_SYS_SPI1_MSB _u(27) -#define CLOCKS_ENABLED0_CLK_SYS_SPI1_LSB _u(27) -#define CLOCKS_ENABLED0_CLK_SYS_SPI1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_ENABLED0_CLK_PERI_SPI1 -#define CLOCKS_ENABLED0_CLK_PERI_SPI1_RESET _u(0x0) -#define CLOCKS_ENABLED0_CLK_PERI_SPI1_BITS _u(0x04000000) -#define CLOCKS_ENABLED0_CLK_PERI_SPI1_MSB _u(26) -#define CLOCKS_ENABLED0_CLK_PERI_SPI1_LSB _u(26) -#define CLOCKS_ENABLED0_CLK_PERI_SPI1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_ENABLED0_CLK_SYS_SPI0 -#define CLOCKS_ENABLED0_CLK_SYS_SPI0_RESET _u(0x0) -#define CLOCKS_ENABLED0_CLK_SYS_SPI0_BITS _u(0x02000000) -#define CLOCKS_ENABLED0_CLK_SYS_SPI0_MSB _u(25) -#define CLOCKS_ENABLED0_CLK_SYS_SPI0_LSB _u(25) -#define CLOCKS_ENABLED0_CLK_SYS_SPI0_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_ENABLED0_CLK_PERI_SPI0 -#define CLOCKS_ENABLED0_CLK_PERI_SPI0_RESET _u(0x0) -#define CLOCKS_ENABLED0_CLK_PERI_SPI0_BITS _u(0x01000000) -#define CLOCKS_ENABLED0_CLK_PERI_SPI0_MSB _u(24) -#define CLOCKS_ENABLED0_CLK_PERI_SPI0_LSB _u(24) -#define CLOCKS_ENABLED0_CLK_PERI_SPI0_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_ENABLED0_CLK_SYS_SIO -#define CLOCKS_ENABLED0_CLK_SYS_SIO_RESET _u(0x0) -#define CLOCKS_ENABLED0_CLK_SYS_SIO_BITS _u(0x00800000) -#define CLOCKS_ENABLED0_CLK_SYS_SIO_MSB _u(23) -#define CLOCKS_ENABLED0_CLK_SYS_SIO_LSB _u(23) -#define CLOCKS_ENABLED0_CLK_SYS_SIO_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_ENABLED0_CLK_SYS_RTC -#define CLOCKS_ENABLED0_CLK_SYS_RTC_RESET _u(0x0) -#define CLOCKS_ENABLED0_CLK_SYS_RTC_BITS _u(0x00400000) -#define CLOCKS_ENABLED0_CLK_SYS_RTC_MSB _u(22) -#define CLOCKS_ENABLED0_CLK_SYS_RTC_LSB _u(22) -#define CLOCKS_ENABLED0_CLK_SYS_RTC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_ENABLED0_CLK_RTC_RTC -#define CLOCKS_ENABLED0_CLK_RTC_RTC_RESET _u(0x0) -#define CLOCKS_ENABLED0_CLK_RTC_RTC_BITS _u(0x00200000) -#define CLOCKS_ENABLED0_CLK_RTC_RTC_MSB _u(21) -#define CLOCKS_ENABLED0_CLK_RTC_RTC_LSB _u(21) -#define CLOCKS_ENABLED0_CLK_RTC_RTC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_ENABLED0_CLK_SYS_ROSC -#define CLOCKS_ENABLED0_CLK_SYS_ROSC_RESET _u(0x0) -#define CLOCKS_ENABLED0_CLK_SYS_ROSC_BITS _u(0x00100000) -#define CLOCKS_ENABLED0_CLK_SYS_ROSC_MSB _u(20) -#define CLOCKS_ENABLED0_CLK_SYS_ROSC_LSB _u(20) -#define CLOCKS_ENABLED0_CLK_SYS_ROSC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_ENABLED0_CLK_SYS_ROM -#define CLOCKS_ENABLED0_CLK_SYS_ROM_RESET _u(0x0) -#define CLOCKS_ENABLED0_CLK_SYS_ROM_BITS _u(0x00080000) -#define CLOCKS_ENABLED0_CLK_SYS_ROM_MSB _u(19) -#define CLOCKS_ENABLED0_CLK_SYS_ROM_LSB _u(19) -#define CLOCKS_ENABLED0_CLK_SYS_ROM_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_ENABLED0_CLK_SYS_RESETS -#define CLOCKS_ENABLED0_CLK_SYS_RESETS_RESET _u(0x0) -#define CLOCKS_ENABLED0_CLK_SYS_RESETS_BITS _u(0x00040000) -#define CLOCKS_ENABLED0_CLK_SYS_RESETS_MSB _u(18) -#define CLOCKS_ENABLED0_CLK_SYS_RESETS_LSB _u(18) -#define CLOCKS_ENABLED0_CLK_SYS_RESETS_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_ENABLED0_CLK_SYS_PWM -#define CLOCKS_ENABLED0_CLK_SYS_PWM_RESET _u(0x0) -#define CLOCKS_ENABLED0_CLK_SYS_PWM_BITS _u(0x00020000) -#define CLOCKS_ENABLED0_CLK_SYS_PWM_MSB _u(17) -#define CLOCKS_ENABLED0_CLK_SYS_PWM_LSB _u(17) -#define CLOCKS_ENABLED0_CLK_SYS_PWM_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_ENABLED0_CLK_SYS_PSM -#define CLOCKS_ENABLED0_CLK_SYS_PSM_RESET _u(0x0) -#define CLOCKS_ENABLED0_CLK_SYS_PSM_BITS _u(0x00010000) -#define CLOCKS_ENABLED0_CLK_SYS_PSM_MSB _u(16) -#define CLOCKS_ENABLED0_CLK_SYS_PSM_LSB _u(16) -#define CLOCKS_ENABLED0_CLK_SYS_PSM_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_ENABLED0_CLK_SYS_PLL_USB -#define CLOCKS_ENABLED0_CLK_SYS_PLL_USB_RESET _u(0x0) -#define CLOCKS_ENABLED0_CLK_SYS_PLL_USB_BITS _u(0x00008000) -#define CLOCKS_ENABLED0_CLK_SYS_PLL_USB_MSB _u(15) -#define CLOCKS_ENABLED0_CLK_SYS_PLL_USB_LSB _u(15) -#define CLOCKS_ENABLED0_CLK_SYS_PLL_USB_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_ENABLED0_CLK_SYS_PLL_SYS -#define CLOCKS_ENABLED0_CLK_SYS_PLL_SYS_RESET _u(0x0) -#define CLOCKS_ENABLED0_CLK_SYS_PLL_SYS_BITS _u(0x00004000) -#define CLOCKS_ENABLED0_CLK_SYS_PLL_SYS_MSB _u(14) -#define CLOCKS_ENABLED0_CLK_SYS_PLL_SYS_LSB _u(14) -#define CLOCKS_ENABLED0_CLK_SYS_PLL_SYS_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_ENABLED0_CLK_SYS_PIO1 -#define CLOCKS_ENABLED0_CLK_SYS_PIO1_RESET _u(0x0) -#define CLOCKS_ENABLED0_CLK_SYS_PIO1_BITS _u(0x00002000) -#define CLOCKS_ENABLED0_CLK_SYS_PIO1_MSB _u(13) -#define CLOCKS_ENABLED0_CLK_SYS_PIO1_LSB _u(13) -#define CLOCKS_ENABLED0_CLK_SYS_PIO1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_ENABLED0_CLK_SYS_PIO0 -#define CLOCKS_ENABLED0_CLK_SYS_PIO0_RESET _u(0x0) -#define CLOCKS_ENABLED0_CLK_SYS_PIO0_BITS _u(0x00001000) -#define CLOCKS_ENABLED0_CLK_SYS_PIO0_MSB _u(12) -#define CLOCKS_ENABLED0_CLK_SYS_PIO0_LSB _u(12) -#define CLOCKS_ENABLED0_CLK_SYS_PIO0_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_ENABLED0_CLK_SYS_PADS -#define CLOCKS_ENABLED0_CLK_SYS_PADS_RESET _u(0x0) -#define CLOCKS_ENABLED0_CLK_SYS_PADS_BITS _u(0x00000800) -#define CLOCKS_ENABLED0_CLK_SYS_PADS_MSB _u(11) -#define CLOCKS_ENABLED0_CLK_SYS_PADS_LSB _u(11) -#define CLOCKS_ENABLED0_CLK_SYS_PADS_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_ENABLED0_CLK_SYS_VREG_AND_CHIP_RESET -#define CLOCKS_ENABLED0_CLK_SYS_VREG_AND_CHIP_RESET_RESET _u(0x0) -#define CLOCKS_ENABLED0_CLK_SYS_VREG_AND_CHIP_RESET_BITS _u(0x00000400) -#define CLOCKS_ENABLED0_CLK_SYS_VREG_AND_CHIP_RESET_MSB _u(10) -#define CLOCKS_ENABLED0_CLK_SYS_VREG_AND_CHIP_RESET_LSB _u(10) -#define CLOCKS_ENABLED0_CLK_SYS_VREG_AND_CHIP_RESET_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_ENABLED0_CLK_SYS_JTAG -#define CLOCKS_ENABLED0_CLK_SYS_JTAG_RESET _u(0x0) -#define CLOCKS_ENABLED0_CLK_SYS_JTAG_BITS _u(0x00000200) -#define CLOCKS_ENABLED0_CLK_SYS_JTAG_MSB _u(9) -#define CLOCKS_ENABLED0_CLK_SYS_JTAG_LSB _u(9) -#define CLOCKS_ENABLED0_CLK_SYS_JTAG_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_ENABLED0_CLK_SYS_IO -#define CLOCKS_ENABLED0_CLK_SYS_IO_RESET _u(0x0) -#define CLOCKS_ENABLED0_CLK_SYS_IO_BITS _u(0x00000100) -#define CLOCKS_ENABLED0_CLK_SYS_IO_MSB _u(8) -#define CLOCKS_ENABLED0_CLK_SYS_IO_LSB _u(8) -#define CLOCKS_ENABLED0_CLK_SYS_IO_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_ENABLED0_CLK_SYS_I2C1 -#define CLOCKS_ENABLED0_CLK_SYS_I2C1_RESET _u(0x0) -#define CLOCKS_ENABLED0_CLK_SYS_I2C1_BITS _u(0x00000080) -#define CLOCKS_ENABLED0_CLK_SYS_I2C1_MSB _u(7) -#define CLOCKS_ENABLED0_CLK_SYS_I2C1_LSB _u(7) -#define CLOCKS_ENABLED0_CLK_SYS_I2C1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_ENABLED0_CLK_SYS_I2C0 -#define CLOCKS_ENABLED0_CLK_SYS_I2C0_RESET _u(0x0) -#define CLOCKS_ENABLED0_CLK_SYS_I2C0_BITS _u(0x00000040) -#define CLOCKS_ENABLED0_CLK_SYS_I2C0_MSB _u(6) -#define CLOCKS_ENABLED0_CLK_SYS_I2C0_LSB _u(6) -#define CLOCKS_ENABLED0_CLK_SYS_I2C0_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_ENABLED0_CLK_SYS_DMA -#define CLOCKS_ENABLED0_CLK_SYS_DMA_RESET _u(0x0) -#define CLOCKS_ENABLED0_CLK_SYS_DMA_BITS _u(0x00000020) -#define CLOCKS_ENABLED0_CLK_SYS_DMA_MSB _u(5) -#define CLOCKS_ENABLED0_CLK_SYS_DMA_LSB _u(5) -#define CLOCKS_ENABLED0_CLK_SYS_DMA_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_ENABLED0_CLK_SYS_BUSFABRIC -#define CLOCKS_ENABLED0_CLK_SYS_BUSFABRIC_RESET _u(0x0) -#define CLOCKS_ENABLED0_CLK_SYS_BUSFABRIC_BITS _u(0x00000010) -#define CLOCKS_ENABLED0_CLK_SYS_BUSFABRIC_MSB _u(4) -#define CLOCKS_ENABLED0_CLK_SYS_BUSFABRIC_LSB _u(4) -#define CLOCKS_ENABLED0_CLK_SYS_BUSFABRIC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_ENABLED0_CLK_SYS_BUSCTRL -#define CLOCKS_ENABLED0_CLK_SYS_BUSCTRL_RESET _u(0x0) -#define CLOCKS_ENABLED0_CLK_SYS_BUSCTRL_BITS _u(0x00000008) -#define CLOCKS_ENABLED0_CLK_SYS_BUSCTRL_MSB _u(3) -#define CLOCKS_ENABLED0_CLK_SYS_BUSCTRL_LSB _u(3) -#define CLOCKS_ENABLED0_CLK_SYS_BUSCTRL_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_ENABLED0_CLK_SYS_ADC -#define CLOCKS_ENABLED0_CLK_SYS_ADC_RESET _u(0x0) -#define CLOCKS_ENABLED0_CLK_SYS_ADC_BITS _u(0x00000004) -#define CLOCKS_ENABLED0_CLK_SYS_ADC_MSB _u(2) -#define CLOCKS_ENABLED0_CLK_SYS_ADC_LSB _u(2) -#define CLOCKS_ENABLED0_CLK_SYS_ADC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_ENABLED0_CLK_ADC_ADC -#define CLOCKS_ENABLED0_CLK_ADC_ADC_RESET _u(0x0) -#define CLOCKS_ENABLED0_CLK_ADC_ADC_BITS _u(0x00000002) -#define CLOCKS_ENABLED0_CLK_ADC_ADC_MSB _u(1) -#define CLOCKS_ENABLED0_CLK_ADC_ADC_LSB _u(1) -#define CLOCKS_ENABLED0_CLK_ADC_ADC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_ENABLED0_CLK_SYS_CLOCKS -#define CLOCKS_ENABLED0_CLK_SYS_CLOCKS_RESET _u(0x0) -#define CLOCKS_ENABLED0_CLK_SYS_CLOCKS_BITS _u(0x00000001) -#define CLOCKS_ENABLED0_CLK_SYS_CLOCKS_MSB _u(0) -#define CLOCKS_ENABLED0_CLK_SYS_CLOCKS_LSB _u(0) -#define CLOCKS_ENABLED0_CLK_SYS_CLOCKS_ACCESS "RO" -// ============================================================================= -// Register : CLOCKS_ENABLED1 -// Description : indicates the state of the clock enable -#define CLOCKS_ENABLED1_OFFSET _u(0x000000b4) -#define CLOCKS_ENABLED1_BITS _u(0x00007fff) -#define CLOCKS_ENABLED1_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : CLOCKS_ENABLED1_CLK_SYS_XOSC -#define CLOCKS_ENABLED1_CLK_SYS_XOSC_RESET _u(0x0) -#define CLOCKS_ENABLED1_CLK_SYS_XOSC_BITS _u(0x00004000) -#define CLOCKS_ENABLED1_CLK_SYS_XOSC_MSB _u(14) -#define CLOCKS_ENABLED1_CLK_SYS_XOSC_LSB _u(14) -#define CLOCKS_ENABLED1_CLK_SYS_XOSC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_ENABLED1_CLK_SYS_XIP -#define CLOCKS_ENABLED1_CLK_SYS_XIP_RESET _u(0x0) -#define CLOCKS_ENABLED1_CLK_SYS_XIP_BITS _u(0x00002000) -#define CLOCKS_ENABLED1_CLK_SYS_XIP_MSB _u(13) -#define CLOCKS_ENABLED1_CLK_SYS_XIP_LSB _u(13) -#define CLOCKS_ENABLED1_CLK_SYS_XIP_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_ENABLED1_CLK_SYS_WATCHDOG -#define CLOCKS_ENABLED1_CLK_SYS_WATCHDOG_RESET _u(0x0) -#define CLOCKS_ENABLED1_CLK_SYS_WATCHDOG_BITS _u(0x00001000) -#define CLOCKS_ENABLED1_CLK_SYS_WATCHDOG_MSB _u(12) -#define CLOCKS_ENABLED1_CLK_SYS_WATCHDOG_LSB _u(12) -#define CLOCKS_ENABLED1_CLK_SYS_WATCHDOG_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_ENABLED1_CLK_USB_USBCTRL -#define CLOCKS_ENABLED1_CLK_USB_USBCTRL_RESET _u(0x0) -#define CLOCKS_ENABLED1_CLK_USB_USBCTRL_BITS _u(0x00000800) -#define CLOCKS_ENABLED1_CLK_USB_USBCTRL_MSB _u(11) -#define CLOCKS_ENABLED1_CLK_USB_USBCTRL_LSB _u(11) -#define CLOCKS_ENABLED1_CLK_USB_USBCTRL_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_ENABLED1_CLK_SYS_USBCTRL -#define CLOCKS_ENABLED1_CLK_SYS_USBCTRL_RESET _u(0x0) -#define CLOCKS_ENABLED1_CLK_SYS_USBCTRL_BITS _u(0x00000400) -#define CLOCKS_ENABLED1_CLK_SYS_USBCTRL_MSB _u(10) -#define CLOCKS_ENABLED1_CLK_SYS_USBCTRL_LSB _u(10) -#define CLOCKS_ENABLED1_CLK_SYS_USBCTRL_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_ENABLED1_CLK_SYS_UART1 -#define CLOCKS_ENABLED1_CLK_SYS_UART1_RESET _u(0x0) -#define CLOCKS_ENABLED1_CLK_SYS_UART1_BITS _u(0x00000200) -#define CLOCKS_ENABLED1_CLK_SYS_UART1_MSB _u(9) -#define CLOCKS_ENABLED1_CLK_SYS_UART1_LSB _u(9) -#define CLOCKS_ENABLED1_CLK_SYS_UART1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_ENABLED1_CLK_PERI_UART1 -#define CLOCKS_ENABLED1_CLK_PERI_UART1_RESET _u(0x0) -#define CLOCKS_ENABLED1_CLK_PERI_UART1_BITS _u(0x00000100) -#define CLOCKS_ENABLED1_CLK_PERI_UART1_MSB _u(8) -#define CLOCKS_ENABLED1_CLK_PERI_UART1_LSB _u(8) -#define CLOCKS_ENABLED1_CLK_PERI_UART1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_ENABLED1_CLK_SYS_UART0 -#define CLOCKS_ENABLED1_CLK_SYS_UART0_RESET _u(0x0) -#define CLOCKS_ENABLED1_CLK_SYS_UART0_BITS _u(0x00000080) -#define CLOCKS_ENABLED1_CLK_SYS_UART0_MSB _u(7) -#define CLOCKS_ENABLED1_CLK_SYS_UART0_LSB _u(7) -#define CLOCKS_ENABLED1_CLK_SYS_UART0_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_ENABLED1_CLK_PERI_UART0 -#define CLOCKS_ENABLED1_CLK_PERI_UART0_RESET _u(0x0) -#define CLOCKS_ENABLED1_CLK_PERI_UART0_BITS _u(0x00000040) -#define CLOCKS_ENABLED1_CLK_PERI_UART0_MSB _u(6) -#define CLOCKS_ENABLED1_CLK_PERI_UART0_LSB _u(6) -#define CLOCKS_ENABLED1_CLK_PERI_UART0_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_ENABLED1_CLK_SYS_TIMER -#define CLOCKS_ENABLED1_CLK_SYS_TIMER_RESET _u(0x0) -#define CLOCKS_ENABLED1_CLK_SYS_TIMER_BITS _u(0x00000020) -#define CLOCKS_ENABLED1_CLK_SYS_TIMER_MSB _u(5) -#define CLOCKS_ENABLED1_CLK_SYS_TIMER_LSB _u(5) -#define CLOCKS_ENABLED1_CLK_SYS_TIMER_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_ENABLED1_CLK_SYS_TBMAN -#define CLOCKS_ENABLED1_CLK_SYS_TBMAN_RESET _u(0x0) -#define CLOCKS_ENABLED1_CLK_SYS_TBMAN_BITS _u(0x00000010) -#define CLOCKS_ENABLED1_CLK_SYS_TBMAN_MSB _u(4) -#define CLOCKS_ENABLED1_CLK_SYS_TBMAN_LSB _u(4) -#define CLOCKS_ENABLED1_CLK_SYS_TBMAN_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_ENABLED1_CLK_SYS_SYSINFO -#define CLOCKS_ENABLED1_CLK_SYS_SYSINFO_RESET _u(0x0) -#define CLOCKS_ENABLED1_CLK_SYS_SYSINFO_BITS _u(0x00000008) -#define CLOCKS_ENABLED1_CLK_SYS_SYSINFO_MSB _u(3) -#define CLOCKS_ENABLED1_CLK_SYS_SYSINFO_LSB _u(3) -#define CLOCKS_ENABLED1_CLK_SYS_SYSINFO_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_ENABLED1_CLK_SYS_SYSCFG -#define CLOCKS_ENABLED1_CLK_SYS_SYSCFG_RESET _u(0x0) -#define CLOCKS_ENABLED1_CLK_SYS_SYSCFG_BITS _u(0x00000004) -#define CLOCKS_ENABLED1_CLK_SYS_SYSCFG_MSB _u(2) -#define CLOCKS_ENABLED1_CLK_SYS_SYSCFG_LSB _u(2) -#define CLOCKS_ENABLED1_CLK_SYS_SYSCFG_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_ENABLED1_CLK_SYS_SRAM5 -#define CLOCKS_ENABLED1_CLK_SYS_SRAM5_RESET _u(0x0) -#define CLOCKS_ENABLED1_CLK_SYS_SRAM5_BITS _u(0x00000002) -#define CLOCKS_ENABLED1_CLK_SYS_SRAM5_MSB _u(1) -#define CLOCKS_ENABLED1_CLK_SYS_SRAM5_LSB _u(1) -#define CLOCKS_ENABLED1_CLK_SYS_SRAM5_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_ENABLED1_CLK_SYS_SRAM4 -#define CLOCKS_ENABLED1_CLK_SYS_SRAM4_RESET _u(0x0) -#define CLOCKS_ENABLED1_CLK_SYS_SRAM4_BITS _u(0x00000001) -#define CLOCKS_ENABLED1_CLK_SYS_SRAM4_MSB _u(0) -#define CLOCKS_ENABLED1_CLK_SYS_SRAM4_LSB _u(0) -#define CLOCKS_ENABLED1_CLK_SYS_SRAM4_ACCESS "RO" -// ============================================================================= -// Register : CLOCKS_INTR -// Description : Raw Interrupts -#define CLOCKS_INTR_OFFSET _u(0x000000b8) -#define CLOCKS_INTR_BITS _u(0x00000001) -#define CLOCKS_INTR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : CLOCKS_INTR_CLK_SYS_RESUS -#define CLOCKS_INTR_CLK_SYS_RESUS_RESET _u(0x0) -#define CLOCKS_INTR_CLK_SYS_RESUS_BITS _u(0x00000001) -#define CLOCKS_INTR_CLK_SYS_RESUS_MSB _u(0) -#define CLOCKS_INTR_CLK_SYS_RESUS_LSB _u(0) -#define CLOCKS_INTR_CLK_SYS_RESUS_ACCESS "RO" -// ============================================================================= -// Register : CLOCKS_INTE -// Description : Interrupt Enable -#define CLOCKS_INTE_OFFSET _u(0x000000bc) -#define CLOCKS_INTE_BITS _u(0x00000001) -#define CLOCKS_INTE_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : CLOCKS_INTE_CLK_SYS_RESUS -#define CLOCKS_INTE_CLK_SYS_RESUS_RESET _u(0x0) -#define CLOCKS_INTE_CLK_SYS_RESUS_BITS _u(0x00000001) -#define CLOCKS_INTE_CLK_SYS_RESUS_MSB _u(0) -#define CLOCKS_INTE_CLK_SYS_RESUS_LSB _u(0) -#define CLOCKS_INTE_CLK_SYS_RESUS_ACCESS "RW" -// ============================================================================= -// Register : CLOCKS_INTF -// Description : Interrupt Force -#define CLOCKS_INTF_OFFSET _u(0x000000c0) -#define CLOCKS_INTF_BITS _u(0x00000001) -#define CLOCKS_INTF_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : CLOCKS_INTF_CLK_SYS_RESUS -#define CLOCKS_INTF_CLK_SYS_RESUS_RESET _u(0x0) -#define CLOCKS_INTF_CLK_SYS_RESUS_BITS _u(0x00000001) -#define CLOCKS_INTF_CLK_SYS_RESUS_MSB _u(0) -#define CLOCKS_INTF_CLK_SYS_RESUS_LSB _u(0) -#define CLOCKS_INTF_CLK_SYS_RESUS_ACCESS "RW" -// ============================================================================= -// Register : CLOCKS_INTS -// Description : Interrupt status after masking & forcing -#define CLOCKS_INTS_OFFSET _u(0x000000c4) -#define CLOCKS_INTS_BITS _u(0x00000001) -#define CLOCKS_INTS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : CLOCKS_INTS_CLK_SYS_RESUS -#define CLOCKS_INTS_CLK_SYS_RESUS_RESET _u(0x0) -#define CLOCKS_INTS_CLK_SYS_RESUS_BITS _u(0x00000001) -#define CLOCKS_INTS_CLK_SYS_RESUS_MSB _u(0) -#define CLOCKS_INTS_CLK_SYS_RESUS_LSB _u(0) -#define CLOCKS_INTS_CLK_SYS_RESUS_ACCESS "RO" -// ============================================================================= -#endif // _HARDWARE_REGS_CLOCKS_H - diff --git a/lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/dma.h b/lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/dma.h deleted file mode 100644 index 62a37ec096..0000000000 --- a/lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/dma.h +++ /dev/null @@ -1,5301 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -// ============================================================================= -// Register block : DMA -// Version : 1 -// Bus type : apb -// Description : DMA with separate read and write masters -// ============================================================================= -#ifndef _HARDWARE_REGS_DMA_H -#define _HARDWARE_REGS_DMA_H -// ============================================================================= -// Register : DMA_CH0_READ_ADDR -// Description : DMA Channel 0 Read Address pointer -// This register updates automatically each time a read completes. -// The current value is the next address to be read by this -// channel. -#define DMA_CH0_READ_ADDR_OFFSET _u(0x00000000) -#define DMA_CH0_READ_ADDR_BITS _u(0xffffffff) -#define DMA_CH0_READ_ADDR_RESET _u(0x00000000) -#define DMA_CH0_READ_ADDR_MSB _u(31) -#define DMA_CH0_READ_ADDR_LSB _u(0) -#define DMA_CH0_READ_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH0_WRITE_ADDR -// Description : DMA Channel 0 Write Address pointer -// This register updates automatically each time a write -// completes. The current value is the next address to be written -// by this channel. -#define DMA_CH0_WRITE_ADDR_OFFSET _u(0x00000004) -#define DMA_CH0_WRITE_ADDR_BITS _u(0xffffffff) -#define DMA_CH0_WRITE_ADDR_RESET _u(0x00000000) -#define DMA_CH0_WRITE_ADDR_MSB _u(31) -#define DMA_CH0_WRITE_ADDR_LSB _u(0) -#define DMA_CH0_WRITE_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH0_TRANS_COUNT -// Description : DMA Channel 0 Transfer Count -// Program the number of bus transfers a channel will perform -// before halting. Note that, if transfers are larger than one -// byte in size, this is not equal to the number of bytes -// transferred (see CTRL_DATA_SIZE). -// -// When the channel is active, reading this register shows the -// number of transfers remaining, updating automatically each time -// a write transfer completes. -// -// Writing this register sets the RELOAD value for the transfer -// counter. Each time this channel is triggered, the RELOAD value -// is copied into the live transfer counter. The channel can be -// started multiple times, and will perform the same number of -// transfers each time, as programmed by most recent write. -// -// The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT -// is used as a trigger, the written value is used immediately as -// the length of the new transfer sequence, as well as being -// written to RELOAD. -#define DMA_CH0_TRANS_COUNT_OFFSET _u(0x00000008) -#define DMA_CH0_TRANS_COUNT_BITS _u(0xffffffff) -#define DMA_CH0_TRANS_COUNT_RESET _u(0x00000000) -#define DMA_CH0_TRANS_COUNT_MSB _u(31) -#define DMA_CH0_TRANS_COUNT_LSB _u(0) -#define DMA_CH0_TRANS_COUNT_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH0_CTRL_TRIG -// Description : DMA Channel 0 Control and Status -#define DMA_CH0_CTRL_TRIG_OFFSET _u(0x0000000c) -#define DMA_CH0_CTRL_TRIG_BITS _u(0xe1ffffff) -#define DMA_CH0_CTRL_TRIG_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : DMA_CH0_CTRL_TRIG_AHB_ERROR -// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel -// halts when it encounters any bus error, and always raises its -// channel IRQ flag. -#define DMA_CH0_CTRL_TRIG_AHB_ERROR_RESET _u(0x0) -#define DMA_CH0_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000) -#define DMA_CH0_CTRL_TRIG_AHB_ERROR_MSB _u(31) -#define DMA_CH0_CTRL_TRIG_AHB_ERROR_LSB _u(31) -#define DMA_CH0_CTRL_TRIG_AHB_ERROR_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : DMA_CH0_CTRL_TRIG_READ_ERROR -// Description : If 1, the channel received a read bus error. Write one to -// clear. -// READ_ADDR shows the approximate address where the bus error was -// encountered (will not be earlier, or more than 3 transfers -// later) -#define DMA_CH0_CTRL_TRIG_READ_ERROR_RESET _u(0x0) -#define DMA_CH0_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000) -#define DMA_CH0_CTRL_TRIG_READ_ERROR_MSB _u(30) -#define DMA_CH0_CTRL_TRIG_READ_ERROR_LSB _u(30) -#define DMA_CH0_CTRL_TRIG_READ_ERROR_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : DMA_CH0_CTRL_TRIG_WRITE_ERROR -// Description : If 1, the channel received a write bus error. Write one to -// clear. -// WRITE_ADDR shows the approximate address where the bus error -// was encountered (will not be earlier, or more than 5 transfers -// later) -#define DMA_CH0_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0) -#define DMA_CH0_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000) -#define DMA_CH0_CTRL_TRIG_WRITE_ERROR_MSB _u(29) -#define DMA_CH0_CTRL_TRIG_WRITE_ERROR_LSB _u(29) -#define DMA_CH0_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : DMA_CH0_CTRL_TRIG_BUSY -// Description : This flag goes high when the channel starts a new transfer -// sequence, and low when the last transfer of that sequence -// completes. Clearing EN while BUSY is high pauses the channel, -// and BUSY will stay high while paused. -// -// To terminate a sequence early (and clear the BUSY flag), see -// CHAN_ABORT. -#define DMA_CH0_CTRL_TRIG_BUSY_RESET _u(0x0) -#define DMA_CH0_CTRL_TRIG_BUSY_BITS _u(0x01000000) -#define DMA_CH0_CTRL_TRIG_BUSY_MSB _u(24) -#define DMA_CH0_CTRL_TRIG_BUSY_LSB _u(24) -#define DMA_CH0_CTRL_TRIG_BUSY_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : DMA_CH0_CTRL_TRIG_SNIFF_EN -// Description : If 1, this channel's data transfers are visible to the sniff -// hardware, and each transfer will advance the state of the -// checksum. This only applies if the sniff hardware is enabled, -// and has this channel selected. -// -// This allows checksum to be enabled or disabled on a per- -// control- block basis. -#define DMA_CH0_CTRL_TRIG_SNIFF_EN_RESET _u(0x0) -#define DMA_CH0_CTRL_TRIG_SNIFF_EN_BITS _u(0x00800000) -#define DMA_CH0_CTRL_TRIG_SNIFF_EN_MSB _u(23) -#define DMA_CH0_CTRL_TRIG_SNIFF_EN_LSB _u(23) -#define DMA_CH0_CTRL_TRIG_SNIFF_EN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH0_CTRL_TRIG_BSWAP -// Description : Apply byte-swap transformation to DMA data. -// For byte data, this has no effect. For halfword data, the two -// bytes of each halfword are swapped. For word data, the four -// bytes of each word are swapped to reverse order. -#define DMA_CH0_CTRL_TRIG_BSWAP_RESET _u(0x0) -#define DMA_CH0_CTRL_TRIG_BSWAP_BITS _u(0x00400000) -#define DMA_CH0_CTRL_TRIG_BSWAP_MSB _u(22) -#define DMA_CH0_CTRL_TRIG_BSWAP_LSB _u(22) -#define DMA_CH0_CTRL_TRIG_BSWAP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH0_CTRL_TRIG_IRQ_QUIET -// Description : In QUIET mode, the channel does not generate IRQs at the end of -// every transfer block. Instead, an IRQ is raised when NULL is -// written to a trigger register, indicating the end of a control -// block chain. -// -// This reduces the number of interrupts to be serviced by the CPU -// when transferring a DMA chain of many small control blocks. -#define DMA_CH0_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0) -#define DMA_CH0_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00200000) -#define DMA_CH0_CTRL_TRIG_IRQ_QUIET_MSB _u(21) -#define DMA_CH0_CTRL_TRIG_IRQ_QUIET_LSB _u(21) -#define DMA_CH0_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH0_CTRL_TRIG_TREQ_SEL -// Description : Select a Transfer Request signal. -// The channel uses the transfer request signal to pace its data -// transfer rate. Sources for TREQ signals are internal (TIMERS) -// or external (DREQ, a Data Request from the system). -// 0x0 to 0x3a -> select DREQ n as TREQ -// 0x3b -> Select Timer 0 as TREQ -// 0x3c -> Select Timer 1 as TREQ -// 0x3d -> Select Timer 2 as TREQ (Optional) -// 0x3e -> Select Timer 3 as TREQ (Optional) -// 0x3f -> Permanent request, for unpaced transfers. -#define DMA_CH0_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) -#define DMA_CH0_CTRL_TRIG_TREQ_SEL_BITS _u(0x001f8000) -#define DMA_CH0_CTRL_TRIG_TREQ_SEL_MSB _u(20) -#define DMA_CH0_CTRL_TRIG_TREQ_SEL_LSB _u(15) -#define DMA_CH0_CTRL_TRIG_TREQ_SEL_ACCESS "RW" -#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) -#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) -#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) -#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) -#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) -// ----------------------------------------------------------------------------- -// Field : DMA_CH0_CTRL_TRIG_CHAIN_TO -// Description : When this channel completes, it will trigger the channel -// indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this -// channel)_. -#define DMA_CH0_CTRL_TRIG_CHAIN_TO_RESET _u(0x0) -#define DMA_CH0_CTRL_TRIG_CHAIN_TO_BITS _u(0x00007800) -#define DMA_CH0_CTRL_TRIG_CHAIN_TO_MSB _u(14) -#define DMA_CH0_CTRL_TRIG_CHAIN_TO_LSB _u(11) -#define DMA_CH0_CTRL_TRIG_CHAIN_TO_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH0_CTRL_TRIG_RING_SEL -// Description : Select whether RING_SIZE applies to read or write addresses. -// If 0, read addresses are wrapped on a (1 << RING_SIZE) -// boundary. If 1, write addresses are wrapped. -#define DMA_CH0_CTRL_TRIG_RING_SEL_RESET _u(0x0) -#define DMA_CH0_CTRL_TRIG_RING_SEL_BITS _u(0x00000400) -#define DMA_CH0_CTRL_TRIG_RING_SEL_MSB _u(10) -#define DMA_CH0_CTRL_TRIG_RING_SEL_LSB _u(10) -#define DMA_CH0_CTRL_TRIG_RING_SEL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH0_CTRL_TRIG_RING_SIZE -// Description : Size of address wrap region. If 0, don't wrap. For values n > -// 0, only the lower n bits of the address will change. This wraps -// the address on a (1 << n) byte boundary, facilitating access to -// naturally-aligned ring buffers. -// -// Ring sizes between 2 and 32768 bytes are possible. This can -// apply to either read or write addresses, based on value of -// RING_SEL. -// 0x0 -> RING_NONE -#define DMA_CH0_CTRL_TRIG_RING_SIZE_RESET _u(0x0) -#define DMA_CH0_CTRL_TRIG_RING_SIZE_BITS _u(0x000003c0) -#define DMA_CH0_CTRL_TRIG_RING_SIZE_MSB _u(9) -#define DMA_CH0_CTRL_TRIG_RING_SIZE_LSB _u(6) -#define DMA_CH0_CTRL_TRIG_RING_SIZE_ACCESS "RW" -#define DMA_CH0_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0) -// ----------------------------------------------------------------------------- -// Field : DMA_CH0_CTRL_TRIG_INCR_WRITE -// Description : If 1, the write address increments with each transfer. If 0, -// each write is directed to the same, initial address. -// -// Generally this should be disabled for memory-to-peripheral -// transfers. -#define DMA_CH0_CTRL_TRIG_INCR_WRITE_RESET _u(0x0) -#define DMA_CH0_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000020) -#define DMA_CH0_CTRL_TRIG_INCR_WRITE_MSB _u(5) -#define DMA_CH0_CTRL_TRIG_INCR_WRITE_LSB _u(5) -#define DMA_CH0_CTRL_TRIG_INCR_WRITE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH0_CTRL_TRIG_INCR_READ -// Description : If 1, the read address increments with each transfer. If 0, -// each read is directed to the same, initial address. -// -// Generally this should be disabled for peripheral-to-memory -// transfers. -#define DMA_CH0_CTRL_TRIG_INCR_READ_RESET _u(0x0) -#define DMA_CH0_CTRL_TRIG_INCR_READ_BITS _u(0x00000010) -#define DMA_CH0_CTRL_TRIG_INCR_READ_MSB _u(4) -#define DMA_CH0_CTRL_TRIG_INCR_READ_LSB _u(4) -#define DMA_CH0_CTRL_TRIG_INCR_READ_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH0_CTRL_TRIG_DATA_SIZE -// Description : Set the size of each bus transfer (byte/halfword/word). -// READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) -// with each transfer. -// 0x0 -> SIZE_BYTE -// 0x1 -> SIZE_HALFWORD -// 0x2 -> SIZE_WORD -#define DMA_CH0_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) -#define DMA_CH0_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) -#define DMA_CH0_CTRL_TRIG_DATA_SIZE_MSB _u(3) -#define DMA_CH0_CTRL_TRIG_DATA_SIZE_LSB _u(2) -#define DMA_CH0_CTRL_TRIG_DATA_SIZE_ACCESS "RW" -#define DMA_CH0_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) -#define DMA_CH0_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1) -#define DMA_CH0_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) -// ----------------------------------------------------------------------------- -// Field : DMA_CH0_CTRL_TRIG_HIGH_PRIORITY -// Description : HIGH_PRIORITY gives a channel preferential treatment in issue -// scheduling: in each scheduling round, all high priority -// channels are considered first, and then only a single low -// priority channel, before returning to the high priority -// channels. -// -// This only affects the order in which the DMA schedules -// channels. The DMA's bus priority is not changed. If the DMA is -// not saturated then a low priority channel will see no loss of -// throughput. -#define DMA_CH0_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0) -#define DMA_CH0_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002) -#define DMA_CH0_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1) -#define DMA_CH0_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1) -#define DMA_CH0_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH0_CTRL_TRIG_EN -// Description : DMA Channel Enable. -// When 1, the channel will respond to triggering events, which -// will cause it to become BUSY and start transferring data. When -// 0, the channel will ignore triggers, stop issuing transfers, -// and pause the current transfer sequence (i.e. BUSY will remain -// high if already high) -#define DMA_CH0_CTRL_TRIG_EN_RESET _u(0x0) -#define DMA_CH0_CTRL_TRIG_EN_BITS _u(0x00000001) -#define DMA_CH0_CTRL_TRIG_EN_MSB _u(0) -#define DMA_CH0_CTRL_TRIG_EN_LSB _u(0) -#define DMA_CH0_CTRL_TRIG_EN_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH0_AL1_CTRL -// Description : Alias for channel 0 CTRL register -#define DMA_CH0_AL1_CTRL_OFFSET _u(0x00000010) -#define DMA_CH0_AL1_CTRL_BITS _u(0xffffffff) -#define DMA_CH0_AL1_CTRL_RESET "-" -#define DMA_CH0_AL1_CTRL_MSB _u(31) -#define DMA_CH0_AL1_CTRL_LSB _u(0) -#define DMA_CH0_AL1_CTRL_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH0_AL1_READ_ADDR -// Description : Alias for channel 0 READ_ADDR register -#define DMA_CH0_AL1_READ_ADDR_OFFSET _u(0x00000014) -#define DMA_CH0_AL1_READ_ADDR_BITS _u(0xffffffff) -#define DMA_CH0_AL1_READ_ADDR_RESET "-" -#define DMA_CH0_AL1_READ_ADDR_MSB _u(31) -#define DMA_CH0_AL1_READ_ADDR_LSB _u(0) -#define DMA_CH0_AL1_READ_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH0_AL1_WRITE_ADDR -// Description : Alias for channel 0 WRITE_ADDR register -#define DMA_CH0_AL1_WRITE_ADDR_OFFSET _u(0x00000018) -#define DMA_CH0_AL1_WRITE_ADDR_BITS _u(0xffffffff) -#define DMA_CH0_AL1_WRITE_ADDR_RESET "-" -#define DMA_CH0_AL1_WRITE_ADDR_MSB _u(31) -#define DMA_CH0_AL1_WRITE_ADDR_LSB _u(0) -#define DMA_CH0_AL1_WRITE_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH0_AL1_TRANS_COUNT_TRIG -// Description : Alias for channel 0 TRANS_COUNT register -// This is a trigger register (0xc). Writing a nonzero value will -// reload the channel counter and start the channel. -#define DMA_CH0_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x0000001c) -#define DMA_CH0_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff) -#define DMA_CH0_AL1_TRANS_COUNT_TRIG_RESET "-" -#define DMA_CH0_AL1_TRANS_COUNT_TRIG_MSB _u(31) -#define DMA_CH0_AL1_TRANS_COUNT_TRIG_LSB _u(0) -#define DMA_CH0_AL1_TRANS_COUNT_TRIG_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH0_AL2_CTRL -// Description : Alias for channel 0 CTRL register -#define DMA_CH0_AL2_CTRL_OFFSET _u(0x00000020) -#define DMA_CH0_AL2_CTRL_BITS _u(0xffffffff) -#define DMA_CH0_AL2_CTRL_RESET "-" -#define DMA_CH0_AL2_CTRL_MSB _u(31) -#define DMA_CH0_AL2_CTRL_LSB _u(0) -#define DMA_CH0_AL2_CTRL_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH0_AL2_TRANS_COUNT -// Description : Alias for channel 0 TRANS_COUNT register -#define DMA_CH0_AL2_TRANS_COUNT_OFFSET _u(0x00000024) -#define DMA_CH0_AL2_TRANS_COUNT_BITS _u(0xffffffff) -#define DMA_CH0_AL2_TRANS_COUNT_RESET "-" -#define DMA_CH0_AL2_TRANS_COUNT_MSB _u(31) -#define DMA_CH0_AL2_TRANS_COUNT_LSB _u(0) -#define DMA_CH0_AL2_TRANS_COUNT_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH0_AL2_READ_ADDR -// Description : Alias for channel 0 READ_ADDR register -#define DMA_CH0_AL2_READ_ADDR_OFFSET _u(0x00000028) -#define DMA_CH0_AL2_READ_ADDR_BITS _u(0xffffffff) -#define DMA_CH0_AL2_READ_ADDR_RESET "-" -#define DMA_CH0_AL2_READ_ADDR_MSB _u(31) -#define DMA_CH0_AL2_READ_ADDR_LSB _u(0) -#define DMA_CH0_AL2_READ_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH0_AL2_WRITE_ADDR_TRIG -// Description : Alias for channel 0 WRITE_ADDR register -// This is a trigger register (0xc). Writing a nonzero value will -// reload the channel counter and start the channel. -#define DMA_CH0_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x0000002c) -#define DMA_CH0_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff) -#define DMA_CH0_AL2_WRITE_ADDR_TRIG_RESET "-" -#define DMA_CH0_AL2_WRITE_ADDR_TRIG_MSB _u(31) -#define DMA_CH0_AL2_WRITE_ADDR_TRIG_LSB _u(0) -#define DMA_CH0_AL2_WRITE_ADDR_TRIG_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH0_AL3_CTRL -// Description : Alias for channel 0 CTRL register -#define DMA_CH0_AL3_CTRL_OFFSET _u(0x00000030) -#define DMA_CH0_AL3_CTRL_BITS _u(0xffffffff) -#define DMA_CH0_AL3_CTRL_RESET "-" -#define DMA_CH0_AL3_CTRL_MSB _u(31) -#define DMA_CH0_AL3_CTRL_LSB _u(0) -#define DMA_CH0_AL3_CTRL_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH0_AL3_WRITE_ADDR -// Description : Alias for channel 0 WRITE_ADDR register -#define DMA_CH0_AL3_WRITE_ADDR_OFFSET _u(0x00000034) -#define DMA_CH0_AL3_WRITE_ADDR_BITS _u(0xffffffff) -#define DMA_CH0_AL3_WRITE_ADDR_RESET "-" -#define DMA_CH0_AL3_WRITE_ADDR_MSB _u(31) -#define DMA_CH0_AL3_WRITE_ADDR_LSB _u(0) -#define DMA_CH0_AL3_WRITE_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH0_AL3_TRANS_COUNT -// Description : Alias for channel 0 TRANS_COUNT register -#define DMA_CH0_AL3_TRANS_COUNT_OFFSET _u(0x00000038) -#define DMA_CH0_AL3_TRANS_COUNT_BITS _u(0xffffffff) -#define DMA_CH0_AL3_TRANS_COUNT_RESET "-" -#define DMA_CH0_AL3_TRANS_COUNT_MSB _u(31) -#define DMA_CH0_AL3_TRANS_COUNT_LSB _u(0) -#define DMA_CH0_AL3_TRANS_COUNT_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH0_AL3_READ_ADDR_TRIG -// Description : Alias for channel 0 READ_ADDR register -// This is a trigger register (0xc). Writing a nonzero value will -// reload the channel counter and start the channel. -#define DMA_CH0_AL3_READ_ADDR_TRIG_OFFSET _u(0x0000003c) -#define DMA_CH0_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff) -#define DMA_CH0_AL3_READ_ADDR_TRIG_RESET "-" -#define DMA_CH0_AL3_READ_ADDR_TRIG_MSB _u(31) -#define DMA_CH0_AL3_READ_ADDR_TRIG_LSB _u(0) -#define DMA_CH0_AL3_READ_ADDR_TRIG_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH1_READ_ADDR -// Description : DMA Channel 1 Read Address pointer -// This register updates automatically each time a read completes. -// The current value is the next address to be read by this -// channel. -#define DMA_CH1_READ_ADDR_OFFSET _u(0x00000040) -#define DMA_CH1_READ_ADDR_BITS _u(0xffffffff) -#define DMA_CH1_READ_ADDR_RESET _u(0x00000000) -#define DMA_CH1_READ_ADDR_MSB _u(31) -#define DMA_CH1_READ_ADDR_LSB _u(0) -#define DMA_CH1_READ_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH1_WRITE_ADDR -// Description : DMA Channel 1 Write Address pointer -// This register updates automatically each time a write -// completes. The current value is the next address to be written -// by this channel. -#define DMA_CH1_WRITE_ADDR_OFFSET _u(0x00000044) -#define DMA_CH1_WRITE_ADDR_BITS _u(0xffffffff) -#define DMA_CH1_WRITE_ADDR_RESET _u(0x00000000) -#define DMA_CH1_WRITE_ADDR_MSB _u(31) -#define DMA_CH1_WRITE_ADDR_LSB _u(0) -#define DMA_CH1_WRITE_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH1_TRANS_COUNT -// Description : DMA Channel 1 Transfer Count -// Program the number of bus transfers a channel will perform -// before halting. Note that, if transfers are larger than one -// byte in size, this is not equal to the number of bytes -// transferred (see CTRL_DATA_SIZE). -// -// When the channel is active, reading this register shows the -// number of transfers remaining, updating automatically each time -// a write transfer completes. -// -// Writing this register sets the RELOAD value for the transfer -// counter. Each time this channel is triggered, the RELOAD value -// is copied into the live transfer counter. The channel can be -// started multiple times, and will perform the same number of -// transfers each time, as programmed by most recent write. -// -// The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT -// is used as a trigger, the written value is used immediately as -// the length of the new transfer sequence, as well as being -// written to RELOAD. -#define DMA_CH1_TRANS_COUNT_OFFSET _u(0x00000048) -#define DMA_CH1_TRANS_COUNT_BITS _u(0xffffffff) -#define DMA_CH1_TRANS_COUNT_RESET _u(0x00000000) -#define DMA_CH1_TRANS_COUNT_MSB _u(31) -#define DMA_CH1_TRANS_COUNT_LSB _u(0) -#define DMA_CH1_TRANS_COUNT_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH1_CTRL_TRIG -// Description : DMA Channel 1 Control and Status -#define DMA_CH1_CTRL_TRIG_OFFSET _u(0x0000004c) -#define DMA_CH1_CTRL_TRIG_BITS _u(0xe1ffffff) -#define DMA_CH1_CTRL_TRIG_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : DMA_CH1_CTRL_TRIG_AHB_ERROR -// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel -// halts when it encounters any bus error, and always raises its -// channel IRQ flag. -#define DMA_CH1_CTRL_TRIG_AHB_ERROR_RESET _u(0x0) -#define DMA_CH1_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000) -#define DMA_CH1_CTRL_TRIG_AHB_ERROR_MSB _u(31) -#define DMA_CH1_CTRL_TRIG_AHB_ERROR_LSB _u(31) -#define DMA_CH1_CTRL_TRIG_AHB_ERROR_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : DMA_CH1_CTRL_TRIG_READ_ERROR -// Description : If 1, the channel received a read bus error. Write one to -// clear. -// READ_ADDR shows the approximate address where the bus error was -// encountered (will not be earlier, or more than 3 transfers -// later) -#define DMA_CH1_CTRL_TRIG_READ_ERROR_RESET _u(0x0) -#define DMA_CH1_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000) -#define DMA_CH1_CTRL_TRIG_READ_ERROR_MSB _u(30) -#define DMA_CH1_CTRL_TRIG_READ_ERROR_LSB _u(30) -#define DMA_CH1_CTRL_TRIG_READ_ERROR_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : DMA_CH1_CTRL_TRIG_WRITE_ERROR -// Description : If 1, the channel received a write bus error. Write one to -// clear. -// WRITE_ADDR shows the approximate address where the bus error -// was encountered (will not be earlier, or more than 5 transfers -// later) -#define DMA_CH1_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0) -#define DMA_CH1_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000) -#define DMA_CH1_CTRL_TRIG_WRITE_ERROR_MSB _u(29) -#define DMA_CH1_CTRL_TRIG_WRITE_ERROR_LSB _u(29) -#define DMA_CH1_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : DMA_CH1_CTRL_TRIG_BUSY -// Description : This flag goes high when the channel starts a new transfer -// sequence, and low when the last transfer of that sequence -// completes. Clearing EN while BUSY is high pauses the channel, -// and BUSY will stay high while paused. -// -// To terminate a sequence early (and clear the BUSY flag), see -// CHAN_ABORT. -#define DMA_CH1_CTRL_TRIG_BUSY_RESET _u(0x0) -#define DMA_CH1_CTRL_TRIG_BUSY_BITS _u(0x01000000) -#define DMA_CH1_CTRL_TRIG_BUSY_MSB _u(24) -#define DMA_CH1_CTRL_TRIG_BUSY_LSB _u(24) -#define DMA_CH1_CTRL_TRIG_BUSY_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : DMA_CH1_CTRL_TRIG_SNIFF_EN -// Description : If 1, this channel's data transfers are visible to the sniff -// hardware, and each transfer will advance the state of the -// checksum. This only applies if the sniff hardware is enabled, -// and has this channel selected. -// -// This allows checksum to be enabled or disabled on a per- -// control- block basis. -#define DMA_CH1_CTRL_TRIG_SNIFF_EN_RESET _u(0x0) -#define DMA_CH1_CTRL_TRIG_SNIFF_EN_BITS _u(0x00800000) -#define DMA_CH1_CTRL_TRIG_SNIFF_EN_MSB _u(23) -#define DMA_CH1_CTRL_TRIG_SNIFF_EN_LSB _u(23) -#define DMA_CH1_CTRL_TRIG_SNIFF_EN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH1_CTRL_TRIG_BSWAP -// Description : Apply byte-swap transformation to DMA data. -// For byte data, this has no effect. For halfword data, the two -// bytes of each halfword are swapped. For word data, the four -// bytes of each word are swapped to reverse order. -#define DMA_CH1_CTRL_TRIG_BSWAP_RESET _u(0x0) -#define DMA_CH1_CTRL_TRIG_BSWAP_BITS _u(0x00400000) -#define DMA_CH1_CTRL_TRIG_BSWAP_MSB _u(22) -#define DMA_CH1_CTRL_TRIG_BSWAP_LSB _u(22) -#define DMA_CH1_CTRL_TRIG_BSWAP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH1_CTRL_TRIG_IRQ_QUIET -// Description : In QUIET mode, the channel does not generate IRQs at the end of -// every transfer block. Instead, an IRQ is raised when NULL is -// written to a trigger register, indicating the end of a control -// block chain. -// -// This reduces the number of interrupts to be serviced by the CPU -// when transferring a DMA chain of many small control blocks. -#define DMA_CH1_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0) -#define DMA_CH1_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00200000) -#define DMA_CH1_CTRL_TRIG_IRQ_QUIET_MSB _u(21) -#define DMA_CH1_CTRL_TRIG_IRQ_QUIET_LSB _u(21) -#define DMA_CH1_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH1_CTRL_TRIG_TREQ_SEL -// Description : Select a Transfer Request signal. -// The channel uses the transfer request signal to pace its data -// transfer rate. Sources for TREQ signals are internal (TIMERS) -// or external (DREQ, a Data Request from the system). -// 0x0 to 0x3a -> select DREQ n as TREQ -// 0x3b -> Select Timer 0 as TREQ -// 0x3c -> Select Timer 1 as TREQ -// 0x3d -> Select Timer 2 as TREQ (Optional) -// 0x3e -> Select Timer 3 as TREQ (Optional) -// 0x3f -> Permanent request, for unpaced transfers. -#define DMA_CH1_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) -#define DMA_CH1_CTRL_TRIG_TREQ_SEL_BITS _u(0x001f8000) -#define DMA_CH1_CTRL_TRIG_TREQ_SEL_MSB _u(20) -#define DMA_CH1_CTRL_TRIG_TREQ_SEL_LSB _u(15) -#define DMA_CH1_CTRL_TRIG_TREQ_SEL_ACCESS "RW" -#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) -#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) -#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) -#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) -#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) -// ----------------------------------------------------------------------------- -// Field : DMA_CH1_CTRL_TRIG_CHAIN_TO -// Description : When this channel completes, it will trigger the channel -// indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this -// channel)_. -#define DMA_CH1_CTRL_TRIG_CHAIN_TO_RESET _u(0x0) -#define DMA_CH1_CTRL_TRIG_CHAIN_TO_BITS _u(0x00007800) -#define DMA_CH1_CTRL_TRIG_CHAIN_TO_MSB _u(14) -#define DMA_CH1_CTRL_TRIG_CHAIN_TO_LSB _u(11) -#define DMA_CH1_CTRL_TRIG_CHAIN_TO_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH1_CTRL_TRIG_RING_SEL -// Description : Select whether RING_SIZE applies to read or write addresses. -// If 0, read addresses are wrapped on a (1 << RING_SIZE) -// boundary. If 1, write addresses are wrapped. -#define DMA_CH1_CTRL_TRIG_RING_SEL_RESET _u(0x0) -#define DMA_CH1_CTRL_TRIG_RING_SEL_BITS _u(0x00000400) -#define DMA_CH1_CTRL_TRIG_RING_SEL_MSB _u(10) -#define DMA_CH1_CTRL_TRIG_RING_SEL_LSB _u(10) -#define DMA_CH1_CTRL_TRIG_RING_SEL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH1_CTRL_TRIG_RING_SIZE -// Description : Size of address wrap region. If 0, don't wrap. For values n > -// 0, only the lower n bits of the address will change. This wraps -// the address on a (1 << n) byte boundary, facilitating access to -// naturally-aligned ring buffers. -// -// Ring sizes between 2 and 32768 bytes are possible. This can -// apply to either read or write addresses, based on value of -// RING_SEL. -// 0x0 -> RING_NONE -#define DMA_CH1_CTRL_TRIG_RING_SIZE_RESET _u(0x0) -#define DMA_CH1_CTRL_TRIG_RING_SIZE_BITS _u(0x000003c0) -#define DMA_CH1_CTRL_TRIG_RING_SIZE_MSB _u(9) -#define DMA_CH1_CTRL_TRIG_RING_SIZE_LSB _u(6) -#define DMA_CH1_CTRL_TRIG_RING_SIZE_ACCESS "RW" -#define DMA_CH1_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0) -// ----------------------------------------------------------------------------- -// Field : DMA_CH1_CTRL_TRIG_INCR_WRITE -// Description : If 1, the write address increments with each transfer. If 0, -// each write is directed to the same, initial address. -// -// Generally this should be disabled for memory-to-peripheral -// transfers. -#define DMA_CH1_CTRL_TRIG_INCR_WRITE_RESET _u(0x0) -#define DMA_CH1_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000020) -#define DMA_CH1_CTRL_TRIG_INCR_WRITE_MSB _u(5) -#define DMA_CH1_CTRL_TRIG_INCR_WRITE_LSB _u(5) -#define DMA_CH1_CTRL_TRIG_INCR_WRITE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH1_CTRL_TRIG_INCR_READ -// Description : If 1, the read address increments with each transfer. If 0, -// each read is directed to the same, initial address. -// -// Generally this should be disabled for peripheral-to-memory -// transfers. -#define DMA_CH1_CTRL_TRIG_INCR_READ_RESET _u(0x0) -#define DMA_CH1_CTRL_TRIG_INCR_READ_BITS _u(0x00000010) -#define DMA_CH1_CTRL_TRIG_INCR_READ_MSB _u(4) -#define DMA_CH1_CTRL_TRIG_INCR_READ_LSB _u(4) -#define DMA_CH1_CTRL_TRIG_INCR_READ_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH1_CTRL_TRIG_DATA_SIZE -// Description : Set the size of each bus transfer (byte/halfword/word). -// READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) -// with each transfer. -// 0x0 -> SIZE_BYTE -// 0x1 -> SIZE_HALFWORD -// 0x2 -> SIZE_WORD -#define DMA_CH1_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) -#define DMA_CH1_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) -#define DMA_CH1_CTRL_TRIG_DATA_SIZE_MSB _u(3) -#define DMA_CH1_CTRL_TRIG_DATA_SIZE_LSB _u(2) -#define DMA_CH1_CTRL_TRIG_DATA_SIZE_ACCESS "RW" -#define DMA_CH1_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) -#define DMA_CH1_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1) -#define DMA_CH1_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) -// ----------------------------------------------------------------------------- -// Field : DMA_CH1_CTRL_TRIG_HIGH_PRIORITY -// Description : HIGH_PRIORITY gives a channel preferential treatment in issue -// scheduling: in each scheduling round, all high priority -// channels are considered first, and then only a single low -// priority channel, before returning to the high priority -// channels. -// -// This only affects the order in which the DMA schedules -// channels. The DMA's bus priority is not changed. If the DMA is -// not saturated then a low priority channel will see no loss of -// throughput. -#define DMA_CH1_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0) -#define DMA_CH1_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002) -#define DMA_CH1_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1) -#define DMA_CH1_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1) -#define DMA_CH1_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH1_CTRL_TRIG_EN -// Description : DMA Channel Enable. -// When 1, the channel will respond to triggering events, which -// will cause it to become BUSY and start transferring data. When -// 0, the channel will ignore triggers, stop issuing transfers, -// and pause the current transfer sequence (i.e. BUSY will remain -// high if already high) -#define DMA_CH1_CTRL_TRIG_EN_RESET _u(0x0) -#define DMA_CH1_CTRL_TRIG_EN_BITS _u(0x00000001) -#define DMA_CH1_CTRL_TRIG_EN_MSB _u(0) -#define DMA_CH1_CTRL_TRIG_EN_LSB _u(0) -#define DMA_CH1_CTRL_TRIG_EN_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH1_AL1_CTRL -// Description : Alias for channel 1 CTRL register -#define DMA_CH1_AL1_CTRL_OFFSET _u(0x00000050) -#define DMA_CH1_AL1_CTRL_BITS _u(0xffffffff) -#define DMA_CH1_AL1_CTRL_RESET "-" -#define DMA_CH1_AL1_CTRL_MSB _u(31) -#define DMA_CH1_AL1_CTRL_LSB _u(0) -#define DMA_CH1_AL1_CTRL_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH1_AL1_READ_ADDR -// Description : Alias for channel 1 READ_ADDR register -#define DMA_CH1_AL1_READ_ADDR_OFFSET _u(0x00000054) -#define DMA_CH1_AL1_READ_ADDR_BITS _u(0xffffffff) -#define DMA_CH1_AL1_READ_ADDR_RESET "-" -#define DMA_CH1_AL1_READ_ADDR_MSB _u(31) -#define DMA_CH1_AL1_READ_ADDR_LSB _u(0) -#define DMA_CH1_AL1_READ_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH1_AL1_WRITE_ADDR -// Description : Alias for channel 1 WRITE_ADDR register -#define DMA_CH1_AL1_WRITE_ADDR_OFFSET _u(0x00000058) -#define DMA_CH1_AL1_WRITE_ADDR_BITS _u(0xffffffff) -#define DMA_CH1_AL1_WRITE_ADDR_RESET "-" -#define DMA_CH1_AL1_WRITE_ADDR_MSB _u(31) -#define DMA_CH1_AL1_WRITE_ADDR_LSB _u(0) -#define DMA_CH1_AL1_WRITE_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH1_AL1_TRANS_COUNT_TRIG -// Description : Alias for channel 1 TRANS_COUNT register -// This is a trigger register (0xc). Writing a nonzero value will -// reload the channel counter and start the channel. -#define DMA_CH1_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x0000005c) -#define DMA_CH1_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff) -#define DMA_CH1_AL1_TRANS_COUNT_TRIG_RESET "-" -#define DMA_CH1_AL1_TRANS_COUNT_TRIG_MSB _u(31) -#define DMA_CH1_AL1_TRANS_COUNT_TRIG_LSB _u(0) -#define DMA_CH1_AL1_TRANS_COUNT_TRIG_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH1_AL2_CTRL -// Description : Alias for channel 1 CTRL register -#define DMA_CH1_AL2_CTRL_OFFSET _u(0x00000060) -#define DMA_CH1_AL2_CTRL_BITS _u(0xffffffff) -#define DMA_CH1_AL2_CTRL_RESET "-" -#define DMA_CH1_AL2_CTRL_MSB _u(31) -#define DMA_CH1_AL2_CTRL_LSB _u(0) -#define DMA_CH1_AL2_CTRL_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH1_AL2_TRANS_COUNT -// Description : Alias for channel 1 TRANS_COUNT register -#define DMA_CH1_AL2_TRANS_COUNT_OFFSET _u(0x00000064) -#define DMA_CH1_AL2_TRANS_COUNT_BITS _u(0xffffffff) -#define DMA_CH1_AL2_TRANS_COUNT_RESET "-" -#define DMA_CH1_AL2_TRANS_COUNT_MSB _u(31) -#define DMA_CH1_AL2_TRANS_COUNT_LSB _u(0) -#define DMA_CH1_AL2_TRANS_COUNT_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH1_AL2_READ_ADDR -// Description : Alias for channel 1 READ_ADDR register -#define DMA_CH1_AL2_READ_ADDR_OFFSET _u(0x00000068) -#define DMA_CH1_AL2_READ_ADDR_BITS _u(0xffffffff) -#define DMA_CH1_AL2_READ_ADDR_RESET "-" -#define DMA_CH1_AL2_READ_ADDR_MSB _u(31) -#define DMA_CH1_AL2_READ_ADDR_LSB _u(0) -#define DMA_CH1_AL2_READ_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH1_AL2_WRITE_ADDR_TRIG -// Description : Alias for channel 1 WRITE_ADDR register -// This is a trigger register (0xc). Writing a nonzero value will -// reload the channel counter and start the channel. -#define DMA_CH1_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x0000006c) -#define DMA_CH1_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff) -#define DMA_CH1_AL2_WRITE_ADDR_TRIG_RESET "-" -#define DMA_CH1_AL2_WRITE_ADDR_TRIG_MSB _u(31) -#define DMA_CH1_AL2_WRITE_ADDR_TRIG_LSB _u(0) -#define DMA_CH1_AL2_WRITE_ADDR_TRIG_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH1_AL3_CTRL -// Description : Alias for channel 1 CTRL register -#define DMA_CH1_AL3_CTRL_OFFSET _u(0x00000070) -#define DMA_CH1_AL3_CTRL_BITS _u(0xffffffff) -#define DMA_CH1_AL3_CTRL_RESET "-" -#define DMA_CH1_AL3_CTRL_MSB _u(31) -#define DMA_CH1_AL3_CTRL_LSB _u(0) -#define DMA_CH1_AL3_CTRL_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH1_AL3_WRITE_ADDR -// Description : Alias for channel 1 WRITE_ADDR register -#define DMA_CH1_AL3_WRITE_ADDR_OFFSET _u(0x00000074) -#define DMA_CH1_AL3_WRITE_ADDR_BITS _u(0xffffffff) -#define DMA_CH1_AL3_WRITE_ADDR_RESET "-" -#define DMA_CH1_AL3_WRITE_ADDR_MSB _u(31) -#define DMA_CH1_AL3_WRITE_ADDR_LSB _u(0) -#define DMA_CH1_AL3_WRITE_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH1_AL3_TRANS_COUNT -// Description : Alias for channel 1 TRANS_COUNT register -#define DMA_CH1_AL3_TRANS_COUNT_OFFSET _u(0x00000078) -#define DMA_CH1_AL3_TRANS_COUNT_BITS _u(0xffffffff) -#define DMA_CH1_AL3_TRANS_COUNT_RESET "-" -#define DMA_CH1_AL3_TRANS_COUNT_MSB _u(31) -#define DMA_CH1_AL3_TRANS_COUNT_LSB _u(0) -#define DMA_CH1_AL3_TRANS_COUNT_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH1_AL3_READ_ADDR_TRIG -// Description : Alias for channel 1 READ_ADDR register -// This is a trigger register (0xc). Writing a nonzero value will -// reload the channel counter and start the channel. -#define DMA_CH1_AL3_READ_ADDR_TRIG_OFFSET _u(0x0000007c) -#define DMA_CH1_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff) -#define DMA_CH1_AL3_READ_ADDR_TRIG_RESET "-" -#define DMA_CH1_AL3_READ_ADDR_TRIG_MSB _u(31) -#define DMA_CH1_AL3_READ_ADDR_TRIG_LSB _u(0) -#define DMA_CH1_AL3_READ_ADDR_TRIG_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH2_READ_ADDR -// Description : DMA Channel 2 Read Address pointer -// This register updates automatically each time a read completes. -// The current value is the next address to be read by this -// channel. -#define DMA_CH2_READ_ADDR_OFFSET _u(0x00000080) -#define DMA_CH2_READ_ADDR_BITS _u(0xffffffff) -#define DMA_CH2_READ_ADDR_RESET _u(0x00000000) -#define DMA_CH2_READ_ADDR_MSB _u(31) -#define DMA_CH2_READ_ADDR_LSB _u(0) -#define DMA_CH2_READ_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH2_WRITE_ADDR -// Description : DMA Channel 2 Write Address pointer -// This register updates automatically each time a write -// completes. The current value is the next address to be written -// by this channel. -#define DMA_CH2_WRITE_ADDR_OFFSET _u(0x00000084) -#define DMA_CH2_WRITE_ADDR_BITS _u(0xffffffff) -#define DMA_CH2_WRITE_ADDR_RESET _u(0x00000000) -#define DMA_CH2_WRITE_ADDR_MSB _u(31) -#define DMA_CH2_WRITE_ADDR_LSB _u(0) -#define DMA_CH2_WRITE_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH2_TRANS_COUNT -// Description : DMA Channel 2 Transfer Count -// Program the number of bus transfers a channel will perform -// before halting. Note that, if transfers are larger than one -// byte in size, this is not equal to the number of bytes -// transferred (see CTRL_DATA_SIZE). -// -// When the channel is active, reading this register shows the -// number of transfers remaining, updating automatically each time -// a write transfer completes. -// -// Writing this register sets the RELOAD value for the transfer -// counter. Each time this channel is triggered, the RELOAD value -// is copied into the live transfer counter. The channel can be -// started multiple times, and will perform the same number of -// transfers each time, as programmed by most recent write. -// -// The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT -// is used as a trigger, the written value is used immediately as -// the length of the new transfer sequence, as well as being -// written to RELOAD. -#define DMA_CH2_TRANS_COUNT_OFFSET _u(0x00000088) -#define DMA_CH2_TRANS_COUNT_BITS _u(0xffffffff) -#define DMA_CH2_TRANS_COUNT_RESET _u(0x00000000) -#define DMA_CH2_TRANS_COUNT_MSB _u(31) -#define DMA_CH2_TRANS_COUNT_LSB _u(0) -#define DMA_CH2_TRANS_COUNT_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH2_CTRL_TRIG -// Description : DMA Channel 2 Control and Status -#define DMA_CH2_CTRL_TRIG_OFFSET _u(0x0000008c) -#define DMA_CH2_CTRL_TRIG_BITS _u(0xe1ffffff) -#define DMA_CH2_CTRL_TRIG_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : DMA_CH2_CTRL_TRIG_AHB_ERROR -// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel -// halts when it encounters any bus error, and always raises its -// channel IRQ flag. -#define DMA_CH2_CTRL_TRIG_AHB_ERROR_RESET _u(0x0) -#define DMA_CH2_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000) -#define DMA_CH2_CTRL_TRIG_AHB_ERROR_MSB _u(31) -#define DMA_CH2_CTRL_TRIG_AHB_ERROR_LSB _u(31) -#define DMA_CH2_CTRL_TRIG_AHB_ERROR_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : DMA_CH2_CTRL_TRIG_READ_ERROR -// Description : If 1, the channel received a read bus error. Write one to -// clear. -// READ_ADDR shows the approximate address where the bus error was -// encountered (will not be earlier, or more than 3 transfers -// later) -#define DMA_CH2_CTRL_TRIG_READ_ERROR_RESET _u(0x0) -#define DMA_CH2_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000) -#define DMA_CH2_CTRL_TRIG_READ_ERROR_MSB _u(30) -#define DMA_CH2_CTRL_TRIG_READ_ERROR_LSB _u(30) -#define DMA_CH2_CTRL_TRIG_READ_ERROR_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : DMA_CH2_CTRL_TRIG_WRITE_ERROR -// Description : If 1, the channel received a write bus error. Write one to -// clear. -// WRITE_ADDR shows the approximate address where the bus error -// was encountered (will not be earlier, or more than 5 transfers -// later) -#define DMA_CH2_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0) -#define DMA_CH2_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000) -#define DMA_CH2_CTRL_TRIG_WRITE_ERROR_MSB _u(29) -#define DMA_CH2_CTRL_TRIG_WRITE_ERROR_LSB _u(29) -#define DMA_CH2_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : DMA_CH2_CTRL_TRIG_BUSY -// Description : This flag goes high when the channel starts a new transfer -// sequence, and low when the last transfer of that sequence -// completes. Clearing EN while BUSY is high pauses the channel, -// and BUSY will stay high while paused. -// -// To terminate a sequence early (and clear the BUSY flag), see -// CHAN_ABORT. -#define DMA_CH2_CTRL_TRIG_BUSY_RESET _u(0x0) -#define DMA_CH2_CTRL_TRIG_BUSY_BITS _u(0x01000000) -#define DMA_CH2_CTRL_TRIG_BUSY_MSB _u(24) -#define DMA_CH2_CTRL_TRIG_BUSY_LSB _u(24) -#define DMA_CH2_CTRL_TRIG_BUSY_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : DMA_CH2_CTRL_TRIG_SNIFF_EN -// Description : If 1, this channel's data transfers are visible to the sniff -// hardware, and each transfer will advance the state of the -// checksum. This only applies if the sniff hardware is enabled, -// and has this channel selected. -// -// This allows checksum to be enabled or disabled on a per- -// control- block basis. -#define DMA_CH2_CTRL_TRIG_SNIFF_EN_RESET _u(0x0) -#define DMA_CH2_CTRL_TRIG_SNIFF_EN_BITS _u(0x00800000) -#define DMA_CH2_CTRL_TRIG_SNIFF_EN_MSB _u(23) -#define DMA_CH2_CTRL_TRIG_SNIFF_EN_LSB _u(23) -#define DMA_CH2_CTRL_TRIG_SNIFF_EN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH2_CTRL_TRIG_BSWAP -// Description : Apply byte-swap transformation to DMA data. -// For byte data, this has no effect. For halfword data, the two -// bytes of each halfword are swapped. For word data, the four -// bytes of each word are swapped to reverse order. -#define DMA_CH2_CTRL_TRIG_BSWAP_RESET _u(0x0) -#define DMA_CH2_CTRL_TRIG_BSWAP_BITS _u(0x00400000) -#define DMA_CH2_CTRL_TRIG_BSWAP_MSB _u(22) -#define DMA_CH2_CTRL_TRIG_BSWAP_LSB _u(22) -#define DMA_CH2_CTRL_TRIG_BSWAP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH2_CTRL_TRIG_IRQ_QUIET -// Description : In QUIET mode, the channel does not generate IRQs at the end of -// every transfer block. Instead, an IRQ is raised when NULL is -// written to a trigger register, indicating the end of a control -// block chain. -// -// This reduces the number of interrupts to be serviced by the CPU -// when transferring a DMA chain of many small control blocks. -#define DMA_CH2_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0) -#define DMA_CH2_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00200000) -#define DMA_CH2_CTRL_TRIG_IRQ_QUIET_MSB _u(21) -#define DMA_CH2_CTRL_TRIG_IRQ_QUIET_LSB _u(21) -#define DMA_CH2_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH2_CTRL_TRIG_TREQ_SEL -// Description : Select a Transfer Request signal. -// The channel uses the transfer request signal to pace its data -// transfer rate. Sources for TREQ signals are internal (TIMERS) -// or external (DREQ, a Data Request from the system). -// 0x0 to 0x3a -> select DREQ n as TREQ -// 0x3b -> Select Timer 0 as TREQ -// 0x3c -> Select Timer 1 as TREQ -// 0x3d -> Select Timer 2 as TREQ (Optional) -// 0x3e -> Select Timer 3 as TREQ (Optional) -// 0x3f -> Permanent request, for unpaced transfers. -#define DMA_CH2_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) -#define DMA_CH2_CTRL_TRIG_TREQ_SEL_BITS _u(0x001f8000) -#define DMA_CH2_CTRL_TRIG_TREQ_SEL_MSB _u(20) -#define DMA_CH2_CTRL_TRIG_TREQ_SEL_LSB _u(15) -#define DMA_CH2_CTRL_TRIG_TREQ_SEL_ACCESS "RW" -#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) -#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) -#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) -#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) -#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) -// ----------------------------------------------------------------------------- -// Field : DMA_CH2_CTRL_TRIG_CHAIN_TO -// Description : When this channel completes, it will trigger the channel -// indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this -// channel)_. -#define DMA_CH2_CTRL_TRIG_CHAIN_TO_RESET _u(0x0) -#define DMA_CH2_CTRL_TRIG_CHAIN_TO_BITS _u(0x00007800) -#define DMA_CH2_CTRL_TRIG_CHAIN_TO_MSB _u(14) -#define DMA_CH2_CTRL_TRIG_CHAIN_TO_LSB _u(11) -#define DMA_CH2_CTRL_TRIG_CHAIN_TO_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH2_CTRL_TRIG_RING_SEL -// Description : Select whether RING_SIZE applies to read or write addresses. -// If 0, read addresses are wrapped on a (1 << RING_SIZE) -// boundary. If 1, write addresses are wrapped. -#define DMA_CH2_CTRL_TRIG_RING_SEL_RESET _u(0x0) -#define DMA_CH2_CTRL_TRIG_RING_SEL_BITS _u(0x00000400) -#define DMA_CH2_CTRL_TRIG_RING_SEL_MSB _u(10) -#define DMA_CH2_CTRL_TRIG_RING_SEL_LSB _u(10) -#define DMA_CH2_CTRL_TRIG_RING_SEL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH2_CTRL_TRIG_RING_SIZE -// Description : Size of address wrap region. If 0, don't wrap. For values n > -// 0, only the lower n bits of the address will change. This wraps -// the address on a (1 << n) byte boundary, facilitating access to -// naturally-aligned ring buffers. -// -// Ring sizes between 2 and 32768 bytes are possible. This can -// apply to either read or write addresses, based on value of -// RING_SEL. -// 0x0 -> RING_NONE -#define DMA_CH2_CTRL_TRIG_RING_SIZE_RESET _u(0x0) -#define DMA_CH2_CTRL_TRIG_RING_SIZE_BITS _u(0x000003c0) -#define DMA_CH2_CTRL_TRIG_RING_SIZE_MSB _u(9) -#define DMA_CH2_CTRL_TRIG_RING_SIZE_LSB _u(6) -#define DMA_CH2_CTRL_TRIG_RING_SIZE_ACCESS "RW" -#define DMA_CH2_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0) -// ----------------------------------------------------------------------------- -// Field : DMA_CH2_CTRL_TRIG_INCR_WRITE -// Description : If 1, the write address increments with each transfer. If 0, -// each write is directed to the same, initial address. -// -// Generally this should be disabled for memory-to-peripheral -// transfers. -#define DMA_CH2_CTRL_TRIG_INCR_WRITE_RESET _u(0x0) -#define DMA_CH2_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000020) -#define DMA_CH2_CTRL_TRIG_INCR_WRITE_MSB _u(5) -#define DMA_CH2_CTRL_TRIG_INCR_WRITE_LSB _u(5) -#define DMA_CH2_CTRL_TRIG_INCR_WRITE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH2_CTRL_TRIG_INCR_READ -// Description : If 1, the read address increments with each transfer. If 0, -// each read is directed to the same, initial address. -// -// Generally this should be disabled for peripheral-to-memory -// transfers. -#define DMA_CH2_CTRL_TRIG_INCR_READ_RESET _u(0x0) -#define DMA_CH2_CTRL_TRIG_INCR_READ_BITS _u(0x00000010) -#define DMA_CH2_CTRL_TRIG_INCR_READ_MSB _u(4) -#define DMA_CH2_CTRL_TRIG_INCR_READ_LSB _u(4) -#define DMA_CH2_CTRL_TRIG_INCR_READ_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH2_CTRL_TRIG_DATA_SIZE -// Description : Set the size of each bus transfer (byte/halfword/word). -// READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) -// with each transfer. -// 0x0 -> SIZE_BYTE -// 0x1 -> SIZE_HALFWORD -// 0x2 -> SIZE_WORD -#define DMA_CH2_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) -#define DMA_CH2_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) -#define DMA_CH2_CTRL_TRIG_DATA_SIZE_MSB _u(3) -#define DMA_CH2_CTRL_TRIG_DATA_SIZE_LSB _u(2) -#define DMA_CH2_CTRL_TRIG_DATA_SIZE_ACCESS "RW" -#define DMA_CH2_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) -#define DMA_CH2_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1) -#define DMA_CH2_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) -// ----------------------------------------------------------------------------- -// Field : DMA_CH2_CTRL_TRIG_HIGH_PRIORITY -// Description : HIGH_PRIORITY gives a channel preferential treatment in issue -// scheduling: in each scheduling round, all high priority -// channels are considered first, and then only a single low -// priority channel, before returning to the high priority -// channels. -// -// This only affects the order in which the DMA schedules -// channels. The DMA's bus priority is not changed. If the DMA is -// not saturated then a low priority channel will see no loss of -// throughput. -#define DMA_CH2_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0) -#define DMA_CH2_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002) -#define DMA_CH2_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1) -#define DMA_CH2_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1) -#define DMA_CH2_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH2_CTRL_TRIG_EN -// Description : DMA Channel Enable. -// When 1, the channel will respond to triggering events, which -// will cause it to become BUSY and start transferring data. When -// 0, the channel will ignore triggers, stop issuing transfers, -// and pause the current transfer sequence (i.e. BUSY will remain -// high if already high) -#define DMA_CH2_CTRL_TRIG_EN_RESET _u(0x0) -#define DMA_CH2_CTRL_TRIG_EN_BITS _u(0x00000001) -#define DMA_CH2_CTRL_TRIG_EN_MSB _u(0) -#define DMA_CH2_CTRL_TRIG_EN_LSB _u(0) -#define DMA_CH2_CTRL_TRIG_EN_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH2_AL1_CTRL -// Description : Alias for channel 2 CTRL register -#define DMA_CH2_AL1_CTRL_OFFSET _u(0x00000090) -#define DMA_CH2_AL1_CTRL_BITS _u(0xffffffff) -#define DMA_CH2_AL1_CTRL_RESET "-" -#define DMA_CH2_AL1_CTRL_MSB _u(31) -#define DMA_CH2_AL1_CTRL_LSB _u(0) -#define DMA_CH2_AL1_CTRL_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH2_AL1_READ_ADDR -// Description : Alias for channel 2 READ_ADDR register -#define DMA_CH2_AL1_READ_ADDR_OFFSET _u(0x00000094) -#define DMA_CH2_AL1_READ_ADDR_BITS _u(0xffffffff) -#define DMA_CH2_AL1_READ_ADDR_RESET "-" -#define DMA_CH2_AL1_READ_ADDR_MSB _u(31) -#define DMA_CH2_AL1_READ_ADDR_LSB _u(0) -#define DMA_CH2_AL1_READ_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH2_AL1_WRITE_ADDR -// Description : Alias for channel 2 WRITE_ADDR register -#define DMA_CH2_AL1_WRITE_ADDR_OFFSET _u(0x00000098) -#define DMA_CH2_AL1_WRITE_ADDR_BITS _u(0xffffffff) -#define DMA_CH2_AL1_WRITE_ADDR_RESET "-" -#define DMA_CH2_AL1_WRITE_ADDR_MSB _u(31) -#define DMA_CH2_AL1_WRITE_ADDR_LSB _u(0) -#define DMA_CH2_AL1_WRITE_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH2_AL1_TRANS_COUNT_TRIG -// Description : Alias for channel 2 TRANS_COUNT register -// This is a trigger register (0xc). Writing a nonzero value will -// reload the channel counter and start the channel. -#define DMA_CH2_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x0000009c) -#define DMA_CH2_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff) -#define DMA_CH2_AL1_TRANS_COUNT_TRIG_RESET "-" -#define DMA_CH2_AL1_TRANS_COUNT_TRIG_MSB _u(31) -#define DMA_CH2_AL1_TRANS_COUNT_TRIG_LSB _u(0) -#define DMA_CH2_AL1_TRANS_COUNT_TRIG_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH2_AL2_CTRL -// Description : Alias for channel 2 CTRL register -#define DMA_CH2_AL2_CTRL_OFFSET _u(0x000000a0) -#define DMA_CH2_AL2_CTRL_BITS _u(0xffffffff) -#define DMA_CH2_AL2_CTRL_RESET "-" -#define DMA_CH2_AL2_CTRL_MSB _u(31) -#define DMA_CH2_AL2_CTRL_LSB _u(0) -#define DMA_CH2_AL2_CTRL_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH2_AL2_TRANS_COUNT -// Description : Alias for channel 2 TRANS_COUNT register -#define DMA_CH2_AL2_TRANS_COUNT_OFFSET _u(0x000000a4) -#define DMA_CH2_AL2_TRANS_COUNT_BITS _u(0xffffffff) -#define DMA_CH2_AL2_TRANS_COUNT_RESET "-" -#define DMA_CH2_AL2_TRANS_COUNT_MSB _u(31) -#define DMA_CH2_AL2_TRANS_COUNT_LSB _u(0) -#define DMA_CH2_AL2_TRANS_COUNT_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH2_AL2_READ_ADDR -// Description : Alias for channel 2 READ_ADDR register -#define DMA_CH2_AL2_READ_ADDR_OFFSET _u(0x000000a8) -#define DMA_CH2_AL2_READ_ADDR_BITS _u(0xffffffff) -#define DMA_CH2_AL2_READ_ADDR_RESET "-" -#define DMA_CH2_AL2_READ_ADDR_MSB _u(31) -#define DMA_CH2_AL2_READ_ADDR_LSB _u(0) -#define DMA_CH2_AL2_READ_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH2_AL2_WRITE_ADDR_TRIG -// Description : Alias for channel 2 WRITE_ADDR register -// This is a trigger register (0xc). Writing a nonzero value will -// reload the channel counter and start the channel. -#define DMA_CH2_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x000000ac) -#define DMA_CH2_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff) -#define DMA_CH2_AL2_WRITE_ADDR_TRIG_RESET "-" -#define DMA_CH2_AL2_WRITE_ADDR_TRIG_MSB _u(31) -#define DMA_CH2_AL2_WRITE_ADDR_TRIG_LSB _u(0) -#define DMA_CH2_AL2_WRITE_ADDR_TRIG_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH2_AL3_CTRL -// Description : Alias for channel 2 CTRL register -#define DMA_CH2_AL3_CTRL_OFFSET _u(0x000000b0) -#define DMA_CH2_AL3_CTRL_BITS _u(0xffffffff) -#define DMA_CH2_AL3_CTRL_RESET "-" -#define DMA_CH2_AL3_CTRL_MSB _u(31) -#define DMA_CH2_AL3_CTRL_LSB _u(0) -#define DMA_CH2_AL3_CTRL_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH2_AL3_WRITE_ADDR -// Description : Alias for channel 2 WRITE_ADDR register -#define DMA_CH2_AL3_WRITE_ADDR_OFFSET _u(0x000000b4) -#define DMA_CH2_AL3_WRITE_ADDR_BITS _u(0xffffffff) -#define DMA_CH2_AL3_WRITE_ADDR_RESET "-" -#define DMA_CH2_AL3_WRITE_ADDR_MSB _u(31) -#define DMA_CH2_AL3_WRITE_ADDR_LSB _u(0) -#define DMA_CH2_AL3_WRITE_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH2_AL3_TRANS_COUNT -// Description : Alias for channel 2 TRANS_COUNT register -#define DMA_CH2_AL3_TRANS_COUNT_OFFSET _u(0x000000b8) -#define DMA_CH2_AL3_TRANS_COUNT_BITS _u(0xffffffff) -#define DMA_CH2_AL3_TRANS_COUNT_RESET "-" -#define DMA_CH2_AL3_TRANS_COUNT_MSB _u(31) -#define DMA_CH2_AL3_TRANS_COUNT_LSB _u(0) -#define DMA_CH2_AL3_TRANS_COUNT_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH2_AL3_READ_ADDR_TRIG -// Description : Alias for channel 2 READ_ADDR register -// This is a trigger register (0xc). Writing a nonzero value will -// reload the channel counter and start the channel. -#define DMA_CH2_AL3_READ_ADDR_TRIG_OFFSET _u(0x000000bc) -#define DMA_CH2_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff) -#define DMA_CH2_AL3_READ_ADDR_TRIG_RESET "-" -#define DMA_CH2_AL3_READ_ADDR_TRIG_MSB _u(31) -#define DMA_CH2_AL3_READ_ADDR_TRIG_LSB _u(0) -#define DMA_CH2_AL3_READ_ADDR_TRIG_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH3_READ_ADDR -// Description : DMA Channel 3 Read Address pointer -// This register updates automatically each time a read completes. -// The current value is the next address to be read by this -// channel. -#define DMA_CH3_READ_ADDR_OFFSET _u(0x000000c0) -#define DMA_CH3_READ_ADDR_BITS _u(0xffffffff) -#define DMA_CH3_READ_ADDR_RESET _u(0x00000000) -#define DMA_CH3_READ_ADDR_MSB _u(31) -#define DMA_CH3_READ_ADDR_LSB _u(0) -#define DMA_CH3_READ_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH3_WRITE_ADDR -// Description : DMA Channel 3 Write Address pointer -// This register updates automatically each time a write -// completes. The current value is the next address to be written -// by this channel. -#define DMA_CH3_WRITE_ADDR_OFFSET _u(0x000000c4) -#define DMA_CH3_WRITE_ADDR_BITS _u(0xffffffff) -#define DMA_CH3_WRITE_ADDR_RESET _u(0x00000000) -#define DMA_CH3_WRITE_ADDR_MSB _u(31) -#define DMA_CH3_WRITE_ADDR_LSB _u(0) -#define DMA_CH3_WRITE_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH3_TRANS_COUNT -// Description : DMA Channel 3 Transfer Count -// Program the number of bus transfers a channel will perform -// before halting. Note that, if transfers are larger than one -// byte in size, this is not equal to the number of bytes -// transferred (see CTRL_DATA_SIZE). -// -// When the channel is active, reading this register shows the -// number of transfers remaining, updating automatically each time -// a write transfer completes. -// -// Writing this register sets the RELOAD value for the transfer -// counter. Each time this channel is triggered, the RELOAD value -// is copied into the live transfer counter. The channel can be -// started multiple times, and will perform the same number of -// transfers each time, as programmed by most recent write. -// -// The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT -// is used as a trigger, the written value is used immediately as -// the length of the new transfer sequence, as well as being -// written to RELOAD. -#define DMA_CH3_TRANS_COUNT_OFFSET _u(0x000000c8) -#define DMA_CH3_TRANS_COUNT_BITS _u(0xffffffff) -#define DMA_CH3_TRANS_COUNT_RESET _u(0x00000000) -#define DMA_CH3_TRANS_COUNT_MSB _u(31) -#define DMA_CH3_TRANS_COUNT_LSB _u(0) -#define DMA_CH3_TRANS_COUNT_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH3_CTRL_TRIG -// Description : DMA Channel 3 Control and Status -#define DMA_CH3_CTRL_TRIG_OFFSET _u(0x000000cc) -#define DMA_CH3_CTRL_TRIG_BITS _u(0xe1ffffff) -#define DMA_CH3_CTRL_TRIG_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : DMA_CH3_CTRL_TRIG_AHB_ERROR -// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel -// halts when it encounters any bus error, and always raises its -// channel IRQ flag. -#define DMA_CH3_CTRL_TRIG_AHB_ERROR_RESET _u(0x0) -#define DMA_CH3_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000) -#define DMA_CH3_CTRL_TRIG_AHB_ERROR_MSB _u(31) -#define DMA_CH3_CTRL_TRIG_AHB_ERROR_LSB _u(31) -#define DMA_CH3_CTRL_TRIG_AHB_ERROR_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : DMA_CH3_CTRL_TRIG_READ_ERROR -// Description : If 1, the channel received a read bus error. Write one to -// clear. -// READ_ADDR shows the approximate address where the bus error was -// encountered (will not be earlier, or more than 3 transfers -// later) -#define DMA_CH3_CTRL_TRIG_READ_ERROR_RESET _u(0x0) -#define DMA_CH3_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000) -#define DMA_CH3_CTRL_TRIG_READ_ERROR_MSB _u(30) -#define DMA_CH3_CTRL_TRIG_READ_ERROR_LSB _u(30) -#define DMA_CH3_CTRL_TRIG_READ_ERROR_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : DMA_CH3_CTRL_TRIG_WRITE_ERROR -// Description : If 1, the channel received a write bus error. Write one to -// clear. -// WRITE_ADDR shows the approximate address where the bus error -// was encountered (will not be earlier, or more than 5 transfers -// later) -#define DMA_CH3_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0) -#define DMA_CH3_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000) -#define DMA_CH3_CTRL_TRIG_WRITE_ERROR_MSB _u(29) -#define DMA_CH3_CTRL_TRIG_WRITE_ERROR_LSB _u(29) -#define DMA_CH3_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : DMA_CH3_CTRL_TRIG_BUSY -// Description : This flag goes high when the channel starts a new transfer -// sequence, and low when the last transfer of that sequence -// completes. Clearing EN while BUSY is high pauses the channel, -// and BUSY will stay high while paused. -// -// To terminate a sequence early (and clear the BUSY flag), see -// CHAN_ABORT. -#define DMA_CH3_CTRL_TRIG_BUSY_RESET _u(0x0) -#define DMA_CH3_CTRL_TRIG_BUSY_BITS _u(0x01000000) -#define DMA_CH3_CTRL_TRIG_BUSY_MSB _u(24) -#define DMA_CH3_CTRL_TRIG_BUSY_LSB _u(24) -#define DMA_CH3_CTRL_TRIG_BUSY_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : DMA_CH3_CTRL_TRIG_SNIFF_EN -// Description : If 1, this channel's data transfers are visible to the sniff -// hardware, and each transfer will advance the state of the -// checksum. This only applies if the sniff hardware is enabled, -// and has this channel selected. -// -// This allows checksum to be enabled or disabled on a per- -// control- block basis. -#define DMA_CH3_CTRL_TRIG_SNIFF_EN_RESET _u(0x0) -#define DMA_CH3_CTRL_TRIG_SNIFF_EN_BITS _u(0x00800000) -#define DMA_CH3_CTRL_TRIG_SNIFF_EN_MSB _u(23) -#define DMA_CH3_CTRL_TRIG_SNIFF_EN_LSB _u(23) -#define DMA_CH3_CTRL_TRIG_SNIFF_EN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH3_CTRL_TRIG_BSWAP -// Description : Apply byte-swap transformation to DMA data. -// For byte data, this has no effect. For halfword data, the two -// bytes of each halfword are swapped. For word data, the four -// bytes of each word are swapped to reverse order. -#define DMA_CH3_CTRL_TRIG_BSWAP_RESET _u(0x0) -#define DMA_CH3_CTRL_TRIG_BSWAP_BITS _u(0x00400000) -#define DMA_CH3_CTRL_TRIG_BSWAP_MSB _u(22) -#define DMA_CH3_CTRL_TRIG_BSWAP_LSB _u(22) -#define DMA_CH3_CTRL_TRIG_BSWAP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH3_CTRL_TRIG_IRQ_QUIET -// Description : In QUIET mode, the channel does not generate IRQs at the end of -// every transfer block. Instead, an IRQ is raised when NULL is -// written to a trigger register, indicating the end of a control -// block chain. -// -// This reduces the number of interrupts to be serviced by the CPU -// when transferring a DMA chain of many small control blocks. -#define DMA_CH3_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0) -#define DMA_CH3_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00200000) -#define DMA_CH3_CTRL_TRIG_IRQ_QUIET_MSB _u(21) -#define DMA_CH3_CTRL_TRIG_IRQ_QUIET_LSB _u(21) -#define DMA_CH3_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH3_CTRL_TRIG_TREQ_SEL -// Description : Select a Transfer Request signal. -// The channel uses the transfer request signal to pace its data -// transfer rate. Sources for TREQ signals are internal (TIMERS) -// or external (DREQ, a Data Request from the system). -// 0x0 to 0x3a -> select DREQ n as TREQ -// 0x3b -> Select Timer 0 as TREQ -// 0x3c -> Select Timer 1 as TREQ -// 0x3d -> Select Timer 2 as TREQ (Optional) -// 0x3e -> Select Timer 3 as TREQ (Optional) -// 0x3f -> Permanent request, for unpaced transfers. -#define DMA_CH3_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) -#define DMA_CH3_CTRL_TRIG_TREQ_SEL_BITS _u(0x001f8000) -#define DMA_CH3_CTRL_TRIG_TREQ_SEL_MSB _u(20) -#define DMA_CH3_CTRL_TRIG_TREQ_SEL_LSB _u(15) -#define DMA_CH3_CTRL_TRIG_TREQ_SEL_ACCESS "RW" -#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) -#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) -#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) -#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) -#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) -// ----------------------------------------------------------------------------- -// Field : DMA_CH3_CTRL_TRIG_CHAIN_TO -// Description : When this channel completes, it will trigger the channel -// indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this -// channel)_. -#define DMA_CH3_CTRL_TRIG_CHAIN_TO_RESET _u(0x0) -#define DMA_CH3_CTRL_TRIG_CHAIN_TO_BITS _u(0x00007800) -#define DMA_CH3_CTRL_TRIG_CHAIN_TO_MSB _u(14) -#define DMA_CH3_CTRL_TRIG_CHAIN_TO_LSB _u(11) -#define DMA_CH3_CTRL_TRIG_CHAIN_TO_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH3_CTRL_TRIG_RING_SEL -// Description : Select whether RING_SIZE applies to read or write addresses. -// If 0, read addresses are wrapped on a (1 << RING_SIZE) -// boundary. If 1, write addresses are wrapped. -#define DMA_CH3_CTRL_TRIG_RING_SEL_RESET _u(0x0) -#define DMA_CH3_CTRL_TRIG_RING_SEL_BITS _u(0x00000400) -#define DMA_CH3_CTRL_TRIG_RING_SEL_MSB _u(10) -#define DMA_CH3_CTRL_TRIG_RING_SEL_LSB _u(10) -#define DMA_CH3_CTRL_TRIG_RING_SEL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH3_CTRL_TRIG_RING_SIZE -// Description : Size of address wrap region. If 0, don't wrap. For values n > -// 0, only the lower n bits of the address will change. This wraps -// the address on a (1 << n) byte boundary, facilitating access to -// naturally-aligned ring buffers. -// -// Ring sizes between 2 and 32768 bytes are possible. This can -// apply to either read or write addresses, based on value of -// RING_SEL. -// 0x0 -> RING_NONE -#define DMA_CH3_CTRL_TRIG_RING_SIZE_RESET _u(0x0) -#define DMA_CH3_CTRL_TRIG_RING_SIZE_BITS _u(0x000003c0) -#define DMA_CH3_CTRL_TRIG_RING_SIZE_MSB _u(9) -#define DMA_CH3_CTRL_TRIG_RING_SIZE_LSB _u(6) -#define DMA_CH3_CTRL_TRIG_RING_SIZE_ACCESS "RW" -#define DMA_CH3_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0) -// ----------------------------------------------------------------------------- -// Field : DMA_CH3_CTRL_TRIG_INCR_WRITE -// Description : If 1, the write address increments with each transfer. If 0, -// each write is directed to the same, initial address. -// -// Generally this should be disabled for memory-to-peripheral -// transfers. -#define DMA_CH3_CTRL_TRIG_INCR_WRITE_RESET _u(0x0) -#define DMA_CH3_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000020) -#define DMA_CH3_CTRL_TRIG_INCR_WRITE_MSB _u(5) -#define DMA_CH3_CTRL_TRIG_INCR_WRITE_LSB _u(5) -#define DMA_CH3_CTRL_TRIG_INCR_WRITE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH3_CTRL_TRIG_INCR_READ -// Description : If 1, the read address increments with each transfer. If 0, -// each read is directed to the same, initial address. -// -// Generally this should be disabled for peripheral-to-memory -// transfers. -#define DMA_CH3_CTRL_TRIG_INCR_READ_RESET _u(0x0) -#define DMA_CH3_CTRL_TRIG_INCR_READ_BITS _u(0x00000010) -#define DMA_CH3_CTRL_TRIG_INCR_READ_MSB _u(4) -#define DMA_CH3_CTRL_TRIG_INCR_READ_LSB _u(4) -#define DMA_CH3_CTRL_TRIG_INCR_READ_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH3_CTRL_TRIG_DATA_SIZE -// Description : Set the size of each bus transfer (byte/halfword/word). -// READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) -// with each transfer. -// 0x0 -> SIZE_BYTE -// 0x1 -> SIZE_HALFWORD -// 0x2 -> SIZE_WORD -#define DMA_CH3_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) -#define DMA_CH3_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) -#define DMA_CH3_CTRL_TRIG_DATA_SIZE_MSB _u(3) -#define DMA_CH3_CTRL_TRIG_DATA_SIZE_LSB _u(2) -#define DMA_CH3_CTRL_TRIG_DATA_SIZE_ACCESS "RW" -#define DMA_CH3_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) -#define DMA_CH3_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1) -#define DMA_CH3_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) -// ----------------------------------------------------------------------------- -// Field : DMA_CH3_CTRL_TRIG_HIGH_PRIORITY -// Description : HIGH_PRIORITY gives a channel preferential treatment in issue -// scheduling: in each scheduling round, all high priority -// channels are considered first, and then only a single low -// priority channel, before returning to the high priority -// channels. -// -// This only affects the order in which the DMA schedules -// channels. The DMA's bus priority is not changed. If the DMA is -// not saturated then a low priority channel will see no loss of -// throughput. -#define DMA_CH3_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0) -#define DMA_CH3_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002) -#define DMA_CH3_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1) -#define DMA_CH3_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1) -#define DMA_CH3_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH3_CTRL_TRIG_EN -// Description : DMA Channel Enable. -// When 1, the channel will respond to triggering events, which -// will cause it to become BUSY and start transferring data. When -// 0, the channel will ignore triggers, stop issuing transfers, -// and pause the current transfer sequence (i.e. BUSY will remain -// high if already high) -#define DMA_CH3_CTRL_TRIG_EN_RESET _u(0x0) -#define DMA_CH3_CTRL_TRIG_EN_BITS _u(0x00000001) -#define DMA_CH3_CTRL_TRIG_EN_MSB _u(0) -#define DMA_CH3_CTRL_TRIG_EN_LSB _u(0) -#define DMA_CH3_CTRL_TRIG_EN_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH3_AL1_CTRL -// Description : Alias for channel 3 CTRL register -#define DMA_CH3_AL1_CTRL_OFFSET _u(0x000000d0) -#define DMA_CH3_AL1_CTRL_BITS _u(0xffffffff) -#define DMA_CH3_AL1_CTRL_RESET "-" -#define DMA_CH3_AL1_CTRL_MSB _u(31) -#define DMA_CH3_AL1_CTRL_LSB _u(0) -#define DMA_CH3_AL1_CTRL_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH3_AL1_READ_ADDR -// Description : Alias for channel 3 READ_ADDR register -#define DMA_CH3_AL1_READ_ADDR_OFFSET _u(0x000000d4) -#define DMA_CH3_AL1_READ_ADDR_BITS _u(0xffffffff) -#define DMA_CH3_AL1_READ_ADDR_RESET "-" -#define DMA_CH3_AL1_READ_ADDR_MSB _u(31) -#define DMA_CH3_AL1_READ_ADDR_LSB _u(0) -#define DMA_CH3_AL1_READ_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH3_AL1_WRITE_ADDR -// Description : Alias for channel 3 WRITE_ADDR register -#define DMA_CH3_AL1_WRITE_ADDR_OFFSET _u(0x000000d8) -#define DMA_CH3_AL1_WRITE_ADDR_BITS _u(0xffffffff) -#define DMA_CH3_AL1_WRITE_ADDR_RESET "-" -#define DMA_CH3_AL1_WRITE_ADDR_MSB _u(31) -#define DMA_CH3_AL1_WRITE_ADDR_LSB _u(0) -#define DMA_CH3_AL1_WRITE_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH3_AL1_TRANS_COUNT_TRIG -// Description : Alias for channel 3 TRANS_COUNT register -// This is a trigger register (0xc). Writing a nonzero value will -// reload the channel counter and start the channel. -#define DMA_CH3_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x000000dc) -#define DMA_CH3_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff) -#define DMA_CH3_AL1_TRANS_COUNT_TRIG_RESET "-" -#define DMA_CH3_AL1_TRANS_COUNT_TRIG_MSB _u(31) -#define DMA_CH3_AL1_TRANS_COUNT_TRIG_LSB _u(0) -#define DMA_CH3_AL1_TRANS_COUNT_TRIG_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH3_AL2_CTRL -// Description : Alias for channel 3 CTRL register -#define DMA_CH3_AL2_CTRL_OFFSET _u(0x000000e0) -#define DMA_CH3_AL2_CTRL_BITS _u(0xffffffff) -#define DMA_CH3_AL2_CTRL_RESET "-" -#define DMA_CH3_AL2_CTRL_MSB _u(31) -#define DMA_CH3_AL2_CTRL_LSB _u(0) -#define DMA_CH3_AL2_CTRL_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH3_AL2_TRANS_COUNT -// Description : Alias for channel 3 TRANS_COUNT register -#define DMA_CH3_AL2_TRANS_COUNT_OFFSET _u(0x000000e4) -#define DMA_CH3_AL2_TRANS_COUNT_BITS _u(0xffffffff) -#define DMA_CH3_AL2_TRANS_COUNT_RESET "-" -#define DMA_CH3_AL2_TRANS_COUNT_MSB _u(31) -#define DMA_CH3_AL2_TRANS_COUNT_LSB _u(0) -#define DMA_CH3_AL2_TRANS_COUNT_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH3_AL2_READ_ADDR -// Description : Alias for channel 3 READ_ADDR register -#define DMA_CH3_AL2_READ_ADDR_OFFSET _u(0x000000e8) -#define DMA_CH3_AL2_READ_ADDR_BITS _u(0xffffffff) -#define DMA_CH3_AL2_READ_ADDR_RESET "-" -#define DMA_CH3_AL2_READ_ADDR_MSB _u(31) -#define DMA_CH3_AL2_READ_ADDR_LSB _u(0) -#define DMA_CH3_AL2_READ_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH3_AL2_WRITE_ADDR_TRIG -// Description : Alias for channel 3 WRITE_ADDR register -// This is a trigger register (0xc). Writing a nonzero value will -// reload the channel counter and start the channel. -#define DMA_CH3_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x000000ec) -#define DMA_CH3_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff) -#define DMA_CH3_AL2_WRITE_ADDR_TRIG_RESET "-" -#define DMA_CH3_AL2_WRITE_ADDR_TRIG_MSB _u(31) -#define DMA_CH3_AL2_WRITE_ADDR_TRIG_LSB _u(0) -#define DMA_CH3_AL2_WRITE_ADDR_TRIG_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH3_AL3_CTRL -// Description : Alias for channel 3 CTRL register -#define DMA_CH3_AL3_CTRL_OFFSET _u(0x000000f0) -#define DMA_CH3_AL3_CTRL_BITS _u(0xffffffff) -#define DMA_CH3_AL3_CTRL_RESET "-" -#define DMA_CH3_AL3_CTRL_MSB _u(31) -#define DMA_CH3_AL3_CTRL_LSB _u(0) -#define DMA_CH3_AL3_CTRL_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH3_AL3_WRITE_ADDR -// Description : Alias for channel 3 WRITE_ADDR register -#define DMA_CH3_AL3_WRITE_ADDR_OFFSET _u(0x000000f4) -#define DMA_CH3_AL3_WRITE_ADDR_BITS _u(0xffffffff) -#define DMA_CH3_AL3_WRITE_ADDR_RESET "-" -#define DMA_CH3_AL3_WRITE_ADDR_MSB _u(31) -#define DMA_CH3_AL3_WRITE_ADDR_LSB _u(0) -#define DMA_CH3_AL3_WRITE_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH3_AL3_TRANS_COUNT -// Description : Alias for channel 3 TRANS_COUNT register -#define DMA_CH3_AL3_TRANS_COUNT_OFFSET _u(0x000000f8) -#define DMA_CH3_AL3_TRANS_COUNT_BITS _u(0xffffffff) -#define DMA_CH3_AL3_TRANS_COUNT_RESET "-" -#define DMA_CH3_AL3_TRANS_COUNT_MSB _u(31) -#define DMA_CH3_AL3_TRANS_COUNT_LSB _u(0) -#define DMA_CH3_AL3_TRANS_COUNT_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH3_AL3_READ_ADDR_TRIG -// Description : Alias for channel 3 READ_ADDR register -// This is a trigger register (0xc). Writing a nonzero value will -// reload the channel counter and start the channel. -#define DMA_CH3_AL3_READ_ADDR_TRIG_OFFSET _u(0x000000fc) -#define DMA_CH3_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff) -#define DMA_CH3_AL3_READ_ADDR_TRIG_RESET "-" -#define DMA_CH3_AL3_READ_ADDR_TRIG_MSB _u(31) -#define DMA_CH3_AL3_READ_ADDR_TRIG_LSB _u(0) -#define DMA_CH3_AL3_READ_ADDR_TRIG_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH4_READ_ADDR -// Description : DMA Channel 4 Read Address pointer -// This register updates automatically each time a read completes. -// The current value is the next address to be read by this -// channel. -#define DMA_CH4_READ_ADDR_OFFSET _u(0x00000100) -#define DMA_CH4_READ_ADDR_BITS _u(0xffffffff) -#define DMA_CH4_READ_ADDR_RESET _u(0x00000000) -#define DMA_CH4_READ_ADDR_MSB _u(31) -#define DMA_CH4_READ_ADDR_LSB _u(0) -#define DMA_CH4_READ_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH4_WRITE_ADDR -// Description : DMA Channel 4 Write Address pointer -// This register updates automatically each time a write -// completes. The current value is the next address to be written -// by this channel. -#define DMA_CH4_WRITE_ADDR_OFFSET _u(0x00000104) -#define DMA_CH4_WRITE_ADDR_BITS _u(0xffffffff) -#define DMA_CH4_WRITE_ADDR_RESET _u(0x00000000) -#define DMA_CH4_WRITE_ADDR_MSB _u(31) -#define DMA_CH4_WRITE_ADDR_LSB _u(0) -#define DMA_CH4_WRITE_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH4_TRANS_COUNT -// Description : DMA Channel 4 Transfer Count -// Program the number of bus transfers a channel will perform -// before halting. Note that, if transfers are larger than one -// byte in size, this is not equal to the number of bytes -// transferred (see CTRL_DATA_SIZE). -// -// When the channel is active, reading this register shows the -// number of transfers remaining, updating automatically each time -// a write transfer completes. -// -// Writing this register sets the RELOAD value for the transfer -// counter. Each time this channel is triggered, the RELOAD value -// is copied into the live transfer counter. The channel can be -// started multiple times, and will perform the same number of -// transfers each time, as programmed by most recent write. -// -// The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT -// is used as a trigger, the written value is used immediately as -// the length of the new transfer sequence, as well as being -// written to RELOAD. -#define DMA_CH4_TRANS_COUNT_OFFSET _u(0x00000108) -#define DMA_CH4_TRANS_COUNT_BITS _u(0xffffffff) -#define DMA_CH4_TRANS_COUNT_RESET _u(0x00000000) -#define DMA_CH4_TRANS_COUNT_MSB _u(31) -#define DMA_CH4_TRANS_COUNT_LSB _u(0) -#define DMA_CH4_TRANS_COUNT_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH4_CTRL_TRIG -// Description : DMA Channel 4 Control and Status -#define DMA_CH4_CTRL_TRIG_OFFSET _u(0x0000010c) -#define DMA_CH4_CTRL_TRIG_BITS _u(0xe1ffffff) -#define DMA_CH4_CTRL_TRIG_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : DMA_CH4_CTRL_TRIG_AHB_ERROR -// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel -// halts when it encounters any bus error, and always raises its -// channel IRQ flag. -#define DMA_CH4_CTRL_TRIG_AHB_ERROR_RESET _u(0x0) -#define DMA_CH4_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000) -#define DMA_CH4_CTRL_TRIG_AHB_ERROR_MSB _u(31) -#define DMA_CH4_CTRL_TRIG_AHB_ERROR_LSB _u(31) -#define DMA_CH4_CTRL_TRIG_AHB_ERROR_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : DMA_CH4_CTRL_TRIG_READ_ERROR -// Description : If 1, the channel received a read bus error. Write one to -// clear. -// READ_ADDR shows the approximate address where the bus error was -// encountered (will not be earlier, or more than 3 transfers -// later) -#define DMA_CH4_CTRL_TRIG_READ_ERROR_RESET _u(0x0) -#define DMA_CH4_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000) -#define DMA_CH4_CTRL_TRIG_READ_ERROR_MSB _u(30) -#define DMA_CH4_CTRL_TRIG_READ_ERROR_LSB _u(30) -#define DMA_CH4_CTRL_TRIG_READ_ERROR_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : DMA_CH4_CTRL_TRIG_WRITE_ERROR -// Description : If 1, the channel received a write bus error. Write one to -// clear. -// WRITE_ADDR shows the approximate address where the bus error -// was encountered (will not be earlier, or more than 5 transfers -// later) -#define DMA_CH4_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0) -#define DMA_CH4_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000) -#define DMA_CH4_CTRL_TRIG_WRITE_ERROR_MSB _u(29) -#define DMA_CH4_CTRL_TRIG_WRITE_ERROR_LSB _u(29) -#define DMA_CH4_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : DMA_CH4_CTRL_TRIG_BUSY -// Description : This flag goes high when the channel starts a new transfer -// sequence, and low when the last transfer of that sequence -// completes. Clearing EN while BUSY is high pauses the channel, -// and BUSY will stay high while paused. -// -// To terminate a sequence early (and clear the BUSY flag), see -// CHAN_ABORT. -#define DMA_CH4_CTRL_TRIG_BUSY_RESET _u(0x0) -#define DMA_CH4_CTRL_TRIG_BUSY_BITS _u(0x01000000) -#define DMA_CH4_CTRL_TRIG_BUSY_MSB _u(24) -#define DMA_CH4_CTRL_TRIG_BUSY_LSB _u(24) -#define DMA_CH4_CTRL_TRIG_BUSY_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : DMA_CH4_CTRL_TRIG_SNIFF_EN -// Description : If 1, this channel's data transfers are visible to the sniff -// hardware, and each transfer will advance the state of the -// checksum. This only applies if the sniff hardware is enabled, -// and has this channel selected. -// -// This allows checksum to be enabled or disabled on a per- -// control- block basis. -#define DMA_CH4_CTRL_TRIG_SNIFF_EN_RESET _u(0x0) -#define DMA_CH4_CTRL_TRIG_SNIFF_EN_BITS _u(0x00800000) -#define DMA_CH4_CTRL_TRIG_SNIFF_EN_MSB _u(23) -#define DMA_CH4_CTRL_TRIG_SNIFF_EN_LSB _u(23) -#define DMA_CH4_CTRL_TRIG_SNIFF_EN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH4_CTRL_TRIG_BSWAP -// Description : Apply byte-swap transformation to DMA data. -// For byte data, this has no effect. For halfword data, the two -// bytes of each halfword are swapped. For word data, the four -// bytes of each word are swapped to reverse order. -#define DMA_CH4_CTRL_TRIG_BSWAP_RESET _u(0x0) -#define DMA_CH4_CTRL_TRIG_BSWAP_BITS _u(0x00400000) -#define DMA_CH4_CTRL_TRIG_BSWAP_MSB _u(22) -#define DMA_CH4_CTRL_TRIG_BSWAP_LSB _u(22) -#define DMA_CH4_CTRL_TRIG_BSWAP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH4_CTRL_TRIG_IRQ_QUIET -// Description : In QUIET mode, the channel does not generate IRQs at the end of -// every transfer block. Instead, an IRQ is raised when NULL is -// written to a trigger register, indicating the end of a control -// block chain. -// -// This reduces the number of interrupts to be serviced by the CPU -// when transferring a DMA chain of many small control blocks. -#define DMA_CH4_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0) -#define DMA_CH4_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00200000) -#define DMA_CH4_CTRL_TRIG_IRQ_QUIET_MSB _u(21) -#define DMA_CH4_CTRL_TRIG_IRQ_QUIET_LSB _u(21) -#define DMA_CH4_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH4_CTRL_TRIG_TREQ_SEL -// Description : Select a Transfer Request signal. -// The channel uses the transfer request signal to pace its data -// transfer rate. Sources for TREQ signals are internal (TIMERS) -// or external (DREQ, a Data Request from the system). -// 0x0 to 0x3a -> select DREQ n as TREQ -// 0x3b -> Select Timer 0 as TREQ -// 0x3c -> Select Timer 1 as TREQ -// 0x3d -> Select Timer 2 as TREQ (Optional) -// 0x3e -> Select Timer 3 as TREQ (Optional) -// 0x3f -> Permanent request, for unpaced transfers. -#define DMA_CH4_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) -#define DMA_CH4_CTRL_TRIG_TREQ_SEL_BITS _u(0x001f8000) -#define DMA_CH4_CTRL_TRIG_TREQ_SEL_MSB _u(20) -#define DMA_CH4_CTRL_TRIG_TREQ_SEL_LSB _u(15) -#define DMA_CH4_CTRL_TRIG_TREQ_SEL_ACCESS "RW" -#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) -#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) -#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) -#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) -#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) -// ----------------------------------------------------------------------------- -// Field : DMA_CH4_CTRL_TRIG_CHAIN_TO -// Description : When this channel completes, it will trigger the channel -// indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this -// channel)_. -#define DMA_CH4_CTRL_TRIG_CHAIN_TO_RESET _u(0x0) -#define DMA_CH4_CTRL_TRIG_CHAIN_TO_BITS _u(0x00007800) -#define DMA_CH4_CTRL_TRIG_CHAIN_TO_MSB _u(14) -#define DMA_CH4_CTRL_TRIG_CHAIN_TO_LSB _u(11) -#define DMA_CH4_CTRL_TRIG_CHAIN_TO_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH4_CTRL_TRIG_RING_SEL -// Description : Select whether RING_SIZE applies to read or write addresses. -// If 0, read addresses are wrapped on a (1 << RING_SIZE) -// boundary. If 1, write addresses are wrapped. -#define DMA_CH4_CTRL_TRIG_RING_SEL_RESET _u(0x0) -#define DMA_CH4_CTRL_TRIG_RING_SEL_BITS _u(0x00000400) -#define DMA_CH4_CTRL_TRIG_RING_SEL_MSB _u(10) -#define DMA_CH4_CTRL_TRIG_RING_SEL_LSB _u(10) -#define DMA_CH4_CTRL_TRIG_RING_SEL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH4_CTRL_TRIG_RING_SIZE -// Description : Size of address wrap region. If 0, don't wrap. For values n > -// 0, only the lower n bits of the address will change. This wraps -// the address on a (1 << n) byte boundary, facilitating access to -// naturally-aligned ring buffers. -// -// Ring sizes between 2 and 32768 bytes are possible. This can -// apply to either read or write addresses, based on value of -// RING_SEL. -// 0x0 -> RING_NONE -#define DMA_CH4_CTRL_TRIG_RING_SIZE_RESET _u(0x0) -#define DMA_CH4_CTRL_TRIG_RING_SIZE_BITS _u(0x000003c0) -#define DMA_CH4_CTRL_TRIG_RING_SIZE_MSB _u(9) -#define DMA_CH4_CTRL_TRIG_RING_SIZE_LSB _u(6) -#define DMA_CH4_CTRL_TRIG_RING_SIZE_ACCESS "RW" -#define DMA_CH4_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0) -// ----------------------------------------------------------------------------- -// Field : DMA_CH4_CTRL_TRIG_INCR_WRITE -// Description : If 1, the write address increments with each transfer. If 0, -// each write is directed to the same, initial address. -// -// Generally this should be disabled for memory-to-peripheral -// transfers. -#define DMA_CH4_CTRL_TRIG_INCR_WRITE_RESET _u(0x0) -#define DMA_CH4_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000020) -#define DMA_CH4_CTRL_TRIG_INCR_WRITE_MSB _u(5) -#define DMA_CH4_CTRL_TRIG_INCR_WRITE_LSB _u(5) -#define DMA_CH4_CTRL_TRIG_INCR_WRITE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH4_CTRL_TRIG_INCR_READ -// Description : If 1, the read address increments with each transfer. If 0, -// each read is directed to the same, initial address. -// -// Generally this should be disabled for peripheral-to-memory -// transfers. -#define DMA_CH4_CTRL_TRIG_INCR_READ_RESET _u(0x0) -#define DMA_CH4_CTRL_TRIG_INCR_READ_BITS _u(0x00000010) -#define DMA_CH4_CTRL_TRIG_INCR_READ_MSB _u(4) -#define DMA_CH4_CTRL_TRIG_INCR_READ_LSB _u(4) -#define DMA_CH4_CTRL_TRIG_INCR_READ_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH4_CTRL_TRIG_DATA_SIZE -// Description : Set the size of each bus transfer (byte/halfword/word). -// READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) -// with each transfer. -// 0x0 -> SIZE_BYTE -// 0x1 -> SIZE_HALFWORD -// 0x2 -> SIZE_WORD -#define DMA_CH4_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) -#define DMA_CH4_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) -#define DMA_CH4_CTRL_TRIG_DATA_SIZE_MSB _u(3) -#define DMA_CH4_CTRL_TRIG_DATA_SIZE_LSB _u(2) -#define DMA_CH4_CTRL_TRIG_DATA_SIZE_ACCESS "RW" -#define DMA_CH4_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) -#define DMA_CH4_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1) -#define DMA_CH4_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) -// ----------------------------------------------------------------------------- -// Field : DMA_CH4_CTRL_TRIG_HIGH_PRIORITY -// Description : HIGH_PRIORITY gives a channel preferential treatment in issue -// scheduling: in each scheduling round, all high priority -// channels are considered first, and then only a single low -// priority channel, before returning to the high priority -// channels. -// -// This only affects the order in which the DMA schedules -// channels. The DMA's bus priority is not changed. If the DMA is -// not saturated then a low priority channel will see no loss of -// throughput. -#define DMA_CH4_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0) -#define DMA_CH4_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002) -#define DMA_CH4_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1) -#define DMA_CH4_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1) -#define DMA_CH4_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH4_CTRL_TRIG_EN -// Description : DMA Channel Enable. -// When 1, the channel will respond to triggering events, which -// will cause it to become BUSY and start transferring data. When -// 0, the channel will ignore triggers, stop issuing transfers, -// and pause the current transfer sequence (i.e. BUSY will remain -// high if already high) -#define DMA_CH4_CTRL_TRIG_EN_RESET _u(0x0) -#define DMA_CH4_CTRL_TRIG_EN_BITS _u(0x00000001) -#define DMA_CH4_CTRL_TRIG_EN_MSB _u(0) -#define DMA_CH4_CTRL_TRIG_EN_LSB _u(0) -#define DMA_CH4_CTRL_TRIG_EN_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH4_AL1_CTRL -// Description : Alias for channel 4 CTRL register -#define DMA_CH4_AL1_CTRL_OFFSET _u(0x00000110) -#define DMA_CH4_AL1_CTRL_BITS _u(0xffffffff) -#define DMA_CH4_AL1_CTRL_RESET "-" -#define DMA_CH4_AL1_CTRL_MSB _u(31) -#define DMA_CH4_AL1_CTRL_LSB _u(0) -#define DMA_CH4_AL1_CTRL_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH4_AL1_READ_ADDR -// Description : Alias for channel 4 READ_ADDR register -#define DMA_CH4_AL1_READ_ADDR_OFFSET _u(0x00000114) -#define DMA_CH4_AL1_READ_ADDR_BITS _u(0xffffffff) -#define DMA_CH4_AL1_READ_ADDR_RESET "-" -#define DMA_CH4_AL1_READ_ADDR_MSB _u(31) -#define DMA_CH4_AL1_READ_ADDR_LSB _u(0) -#define DMA_CH4_AL1_READ_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH4_AL1_WRITE_ADDR -// Description : Alias for channel 4 WRITE_ADDR register -#define DMA_CH4_AL1_WRITE_ADDR_OFFSET _u(0x00000118) -#define DMA_CH4_AL1_WRITE_ADDR_BITS _u(0xffffffff) -#define DMA_CH4_AL1_WRITE_ADDR_RESET "-" -#define DMA_CH4_AL1_WRITE_ADDR_MSB _u(31) -#define DMA_CH4_AL1_WRITE_ADDR_LSB _u(0) -#define DMA_CH4_AL1_WRITE_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH4_AL1_TRANS_COUNT_TRIG -// Description : Alias for channel 4 TRANS_COUNT register -// This is a trigger register (0xc). Writing a nonzero value will -// reload the channel counter and start the channel. -#define DMA_CH4_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x0000011c) -#define DMA_CH4_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff) -#define DMA_CH4_AL1_TRANS_COUNT_TRIG_RESET "-" -#define DMA_CH4_AL1_TRANS_COUNT_TRIG_MSB _u(31) -#define DMA_CH4_AL1_TRANS_COUNT_TRIG_LSB _u(0) -#define DMA_CH4_AL1_TRANS_COUNT_TRIG_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH4_AL2_CTRL -// Description : Alias for channel 4 CTRL register -#define DMA_CH4_AL2_CTRL_OFFSET _u(0x00000120) -#define DMA_CH4_AL2_CTRL_BITS _u(0xffffffff) -#define DMA_CH4_AL2_CTRL_RESET "-" -#define DMA_CH4_AL2_CTRL_MSB _u(31) -#define DMA_CH4_AL2_CTRL_LSB _u(0) -#define DMA_CH4_AL2_CTRL_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH4_AL2_TRANS_COUNT -// Description : Alias for channel 4 TRANS_COUNT register -#define DMA_CH4_AL2_TRANS_COUNT_OFFSET _u(0x00000124) -#define DMA_CH4_AL2_TRANS_COUNT_BITS _u(0xffffffff) -#define DMA_CH4_AL2_TRANS_COUNT_RESET "-" -#define DMA_CH4_AL2_TRANS_COUNT_MSB _u(31) -#define DMA_CH4_AL2_TRANS_COUNT_LSB _u(0) -#define DMA_CH4_AL2_TRANS_COUNT_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH4_AL2_READ_ADDR -// Description : Alias for channel 4 READ_ADDR register -#define DMA_CH4_AL2_READ_ADDR_OFFSET _u(0x00000128) -#define DMA_CH4_AL2_READ_ADDR_BITS _u(0xffffffff) -#define DMA_CH4_AL2_READ_ADDR_RESET "-" -#define DMA_CH4_AL2_READ_ADDR_MSB _u(31) -#define DMA_CH4_AL2_READ_ADDR_LSB _u(0) -#define DMA_CH4_AL2_READ_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH4_AL2_WRITE_ADDR_TRIG -// Description : Alias for channel 4 WRITE_ADDR register -// This is a trigger register (0xc). Writing a nonzero value will -// reload the channel counter and start the channel. -#define DMA_CH4_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x0000012c) -#define DMA_CH4_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff) -#define DMA_CH4_AL2_WRITE_ADDR_TRIG_RESET "-" -#define DMA_CH4_AL2_WRITE_ADDR_TRIG_MSB _u(31) -#define DMA_CH4_AL2_WRITE_ADDR_TRIG_LSB _u(0) -#define DMA_CH4_AL2_WRITE_ADDR_TRIG_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH4_AL3_CTRL -// Description : Alias for channel 4 CTRL register -#define DMA_CH4_AL3_CTRL_OFFSET _u(0x00000130) -#define DMA_CH4_AL3_CTRL_BITS _u(0xffffffff) -#define DMA_CH4_AL3_CTRL_RESET "-" -#define DMA_CH4_AL3_CTRL_MSB _u(31) -#define DMA_CH4_AL3_CTRL_LSB _u(0) -#define DMA_CH4_AL3_CTRL_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH4_AL3_WRITE_ADDR -// Description : Alias for channel 4 WRITE_ADDR register -#define DMA_CH4_AL3_WRITE_ADDR_OFFSET _u(0x00000134) -#define DMA_CH4_AL3_WRITE_ADDR_BITS _u(0xffffffff) -#define DMA_CH4_AL3_WRITE_ADDR_RESET "-" -#define DMA_CH4_AL3_WRITE_ADDR_MSB _u(31) -#define DMA_CH4_AL3_WRITE_ADDR_LSB _u(0) -#define DMA_CH4_AL3_WRITE_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH4_AL3_TRANS_COUNT -// Description : Alias for channel 4 TRANS_COUNT register -#define DMA_CH4_AL3_TRANS_COUNT_OFFSET _u(0x00000138) -#define DMA_CH4_AL3_TRANS_COUNT_BITS _u(0xffffffff) -#define DMA_CH4_AL3_TRANS_COUNT_RESET "-" -#define DMA_CH4_AL3_TRANS_COUNT_MSB _u(31) -#define DMA_CH4_AL3_TRANS_COUNT_LSB _u(0) -#define DMA_CH4_AL3_TRANS_COUNT_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH4_AL3_READ_ADDR_TRIG -// Description : Alias for channel 4 READ_ADDR register -// This is a trigger register (0xc). Writing a nonzero value will -// reload the channel counter and start the channel. -#define DMA_CH4_AL3_READ_ADDR_TRIG_OFFSET _u(0x0000013c) -#define DMA_CH4_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff) -#define DMA_CH4_AL3_READ_ADDR_TRIG_RESET "-" -#define DMA_CH4_AL3_READ_ADDR_TRIG_MSB _u(31) -#define DMA_CH4_AL3_READ_ADDR_TRIG_LSB _u(0) -#define DMA_CH4_AL3_READ_ADDR_TRIG_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH5_READ_ADDR -// Description : DMA Channel 5 Read Address pointer -// This register updates automatically each time a read completes. -// The current value is the next address to be read by this -// channel. -#define DMA_CH5_READ_ADDR_OFFSET _u(0x00000140) -#define DMA_CH5_READ_ADDR_BITS _u(0xffffffff) -#define DMA_CH5_READ_ADDR_RESET _u(0x00000000) -#define DMA_CH5_READ_ADDR_MSB _u(31) -#define DMA_CH5_READ_ADDR_LSB _u(0) -#define DMA_CH5_READ_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH5_WRITE_ADDR -// Description : DMA Channel 5 Write Address pointer -// This register updates automatically each time a write -// completes. The current value is the next address to be written -// by this channel. -#define DMA_CH5_WRITE_ADDR_OFFSET _u(0x00000144) -#define DMA_CH5_WRITE_ADDR_BITS _u(0xffffffff) -#define DMA_CH5_WRITE_ADDR_RESET _u(0x00000000) -#define DMA_CH5_WRITE_ADDR_MSB _u(31) -#define DMA_CH5_WRITE_ADDR_LSB _u(0) -#define DMA_CH5_WRITE_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH5_TRANS_COUNT -// Description : DMA Channel 5 Transfer Count -// Program the number of bus transfers a channel will perform -// before halting. Note that, if transfers are larger than one -// byte in size, this is not equal to the number of bytes -// transferred (see CTRL_DATA_SIZE). -// -// When the channel is active, reading this register shows the -// number of transfers remaining, updating automatically each time -// a write transfer completes. -// -// Writing this register sets the RELOAD value for the transfer -// counter. Each time this channel is triggered, the RELOAD value -// is copied into the live transfer counter. The channel can be -// started multiple times, and will perform the same number of -// transfers each time, as programmed by most recent write. -// -// The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT -// is used as a trigger, the written value is used immediately as -// the length of the new transfer sequence, as well as being -// written to RELOAD. -#define DMA_CH5_TRANS_COUNT_OFFSET _u(0x00000148) -#define DMA_CH5_TRANS_COUNT_BITS _u(0xffffffff) -#define DMA_CH5_TRANS_COUNT_RESET _u(0x00000000) -#define DMA_CH5_TRANS_COUNT_MSB _u(31) -#define DMA_CH5_TRANS_COUNT_LSB _u(0) -#define DMA_CH5_TRANS_COUNT_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH5_CTRL_TRIG -// Description : DMA Channel 5 Control and Status -#define DMA_CH5_CTRL_TRIG_OFFSET _u(0x0000014c) -#define DMA_CH5_CTRL_TRIG_BITS _u(0xe1ffffff) -#define DMA_CH5_CTRL_TRIG_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : DMA_CH5_CTRL_TRIG_AHB_ERROR -// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel -// halts when it encounters any bus error, and always raises its -// channel IRQ flag. -#define DMA_CH5_CTRL_TRIG_AHB_ERROR_RESET _u(0x0) -#define DMA_CH5_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000) -#define DMA_CH5_CTRL_TRIG_AHB_ERROR_MSB _u(31) -#define DMA_CH5_CTRL_TRIG_AHB_ERROR_LSB _u(31) -#define DMA_CH5_CTRL_TRIG_AHB_ERROR_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : DMA_CH5_CTRL_TRIG_READ_ERROR -// Description : If 1, the channel received a read bus error. Write one to -// clear. -// READ_ADDR shows the approximate address where the bus error was -// encountered (will not be earlier, or more than 3 transfers -// later) -#define DMA_CH5_CTRL_TRIG_READ_ERROR_RESET _u(0x0) -#define DMA_CH5_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000) -#define DMA_CH5_CTRL_TRIG_READ_ERROR_MSB _u(30) -#define DMA_CH5_CTRL_TRIG_READ_ERROR_LSB _u(30) -#define DMA_CH5_CTRL_TRIG_READ_ERROR_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : DMA_CH5_CTRL_TRIG_WRITE_ERROR -// Description : If 1, the channel received a write bus error. Write one to -// clear. -// WRITE_ADDR shows the approximate address where the bus error -// was encountered (will not be earlier, or more than 5 transfers -// later) -#define DMA_CH5_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0) -#define DMA_CH5_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000) -#define DMA_CH5_CTRL_TRIG_WRITE_ERROR_MSB _u(29) -#define DMA_CH5_CTRL_TRIG_WRITE_ERROR_LSB _u(29) -#define DMA_CH5_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : DMA_CH5_CTRL_TRIG_BUSY -// Description : This flag goes high when the channel starts a new transfer -// sequence, and low when the last transfer of that sequence -// completes. Clearing EN while BUSY is high pauses the channel, -// and BUSY will stay high while paused. -// -// To terminate a sequence early (and clear the BUSY flag), see -// CHAN_ABORT. -#define DMA_CH5_CTRL_TRIG_BUSY_RESET _u(0x0) -#define DMA_CH5_CTRL_TRIG_BUSY_BITS _u(0x01000000) -#define DMA_CH5_CTRL_TRIG_BUSY_MSB _u(24) -#define DMA_CH5_CTRL_TRIG_BUSY_LSB _u(24) -#define DMA_CH5_CTRL_TRIG_BUSY_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : DMA_CH5_CTRL_TRIG_SNIFF_EN -// Description : If 1, this channel's data transfers are visible to the sniff -// hardware, and each transfer will advance the state of the -// checksum. This only applies if the sniff hardware is enabled, -// and has this channel selected. -// -// This allows checksum to be enabled or disabled on a per- -// control- block basis. -#define DMA_CH5_CTRL_TRIG_SNIFF_EN_RESET _u(0x0) -#define DMA_CH5_CTRL_TRIG_SNIFF_EN_BITS _u(0x00800000) -#define DMA_CH5_CTRL_TRIG_SNIFF_EN_MSB _u(23) -#define DMA_CH5_CTRL_TRIG_SNIFF_EN_LSB _u(23) -#define DMA_CH5_CTRL_TRIG_SNIFF_EN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH5_CTRL_TRIG_BSWAP -// Description : Apply byte-swap transformation to DMA data. -// For byte data, this has no effect. For halfword data, the two -// bytes of each halfword are swapped. For word data, the four -// bytes of each word are swapped to reverse order. -#define DMA_CH5_CTRL_TRIG_BSWAP_RESET _u(0x0) -#define DMA_CH5_CTRL_TRIG_BSWAP_BITS _u(0x00400000) -#define DMA_CH5_CTRL_TRIG_BSWAP_MSB _u(22) -#define DMA_CH5_CTRL_TRIG_BSWAP_LSB _u(22) -#define DMA_CH5_CTRL_TRIG_BSWAP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH5_CTRL_TRIG_IRQ_QUIET -// Description : In QUIET mode, the channel does not generate IRQs at the end of -// every transfer block. Instead, an IRQ is raised when NULL is -// written to a trigger register, indicating the end of a control -// block chain. -// -// This reduces the number of interrupts to be serviced by the CPU -// when transferring a DMA chain of many small control blocks. -#define DMA_CH5_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0) -#define DMA_CH5_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00200000) -#define DMA_CH5_CTRL_TRIG_IRQ_QUIET_MSB _u(21) -#define DMA_CH5_CTRL_TRIG_IRQ_QUIET_LSB _u(21) -#define DMA_CH5_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH5_CTRL_TRIG_TREQ_SEL -// Description : Select a Transfer Request signal. -// The channel uses the transfer request signal to pace its data -// transfer rate. Sources for TREQ signals are internal (TIMERS) -// or external (DREQ, a Data Request from the system). -// 0x0 to 0x3a -> select DREQ n as TREQ -// 0x3b -> Select Timer 0 as TREQ -// 0x3c -> Select Timer 1 as TREQ -// 0x3d -> Select Timer 2 as TREQ (Optional) -// 0x3e -> Select Timer 3 as TREQ (Optional) -// 0x3f -> Permanent request, for unpaced transfers. -#define DMA_CH5_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) -#define DMA_CH5_CTRL_TRIG_TREQ_SEL_BITS _u(0x001f8000) -#define DMA_CH5_CTRL_TRIG_TREQ_SEL_MSB _u(20) -#define DMA_CH5_CTRL_TRIG_TREQ_SEL_LSB _u(15) -#define DMA_CH5_CTRL_TRIG_TREQ_SEL_ACCESS "RW" -#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) -#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) -#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) -#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) -#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) -// ----------------------------------------------------------------------------- -// Field : DMA_CH5_CTRL_TRIG_CHAIN_TO -// Description : When this channel completes, it will trigger the channel -// indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this -// channel)_. -#define DMA_CH5_CTRL_TRIG_CHAIN_TO_RESET _u(0x0) -#define DMA_CH5_CTRL_TRIG_CHAIN_TO_BITS _u(0x00007800) -#define DMA_CH5_CTRL_TRIG_CHAIN_TO_MSB _u(14) -#define DMA_CH5_CTRL_TRIG_CHAIN_TO_LSB _u(11) -#define DMA_CH5_CTRL_TRIG_CHAIN_TO_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH5_CTRL_TRIG_RING_SEL -// Description : Select whether RING_SIZE applies to read or write addresses. -// If 0, read addresses are wrapped on a (1 << RING_SIZE) -// boundary. If 1, write addresses are wrapped. -#define DMA_CH5_CTRL_TRIG_RING_SEL_RESET _u(0x0) -#define DMA_CH5_CTRL_TRIG_RING_SEL_BITS _u(0x00000400) -#define DMA_CH5_CTRL_TRIG_RING_SEL_MSB _u(10) -#define DMA_CH5_CTRL_TRIG_RING_SEL_LSB _u(10) -#define DMA_CH5_CTRL_TRIG_RING_SEL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH5_CTRL_TRIG_RING_SIZE -// Description : Size of address wrap region. If 0, don't wrap. For values n > -// 0, only the lower n bits of the address will change. This wraps -// the address on a (1 << n) byte boundary, facilitating access to -// naturally-aligned ring buffers. -// -// Ring sizes between 2 and 32768 bytes are possible. This can -// apply to either read or write addresses, based on value of -// RING_SEL. -// 0x0 -> RING_NONE -#define DMA_CH5_CTRL_TRIG_RING_SIZE_RESET _u(0x0) -#define DMA_CH5_CTRL_TRIG_RING_SIZE_BITS _u(0x000003c0) -#define DMA_CH5_CTRL_TRIG_RING_SIZE_MSB _u(9) -#define DMA_CH5_CTRL_TRIG_RING_SIZE_LSB _u(6) -#define DMA_CH5_CTRL_TRIG_RING_SIZE_ACCESS "RW" -#define DMA_CH5_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0) -// ----------------------------------------------------------------------------- -// Field : DMA_CH5_CTRL_TRIG_INCR_WRITE -// Description : If 1, the write address increments with each transfer. If 0, -// each write is directed to the same, initial address. -// -// Generally this should be disabled for memory-to-peripheral -// transfers. -#define DMA_CH5_CTRL_TRIG_INCR_WRITE_RESET _u(0x0) -#define DMA_CH5_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000020) -#define DMA_CH5_CTRL_TRIG_INCR_WRITE_MSB _u(5) -#define DMA_CH5_CTRL_TRIG_INCR_WRITE_LSB _u(5) -#define DMA_CH5_CTRL_TRIG_INCR_WRITE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH5_CTRL_TRIG_INCR_READ -// Description : If 1, the read address increments with each transfer. If 0, -// each read is directed to the same, initial address. -// -// Generally this should be disabled for peripheral-to-memory -// transfers. -#define DMA_CH5_CTRL_TRIG_INCR_READ_RESET _u(0x0) -#define DMA_CH5_CTRL_TRIG_INCR_READ_BITS _u(0x00000010) -#define DMA_CH5_CTRL_TRIG_INCR_READ_MSB _u(4) -#define DMA_CH5_CTRL_TRIG_INCR_READ_LSB _u(4) -#define DMA_CH5_CTRL_TRIG_INCR_READ_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH5_CTRL_TRIG_DATA_SIZE -// Description : Set the size of each bus transfer (byte/halfword/word). -// READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) -// with each transfer. -// 0x0 -> SIZE_BYTE -// 0x1 -> SIZE_HALFWORD -// 0x2 -> SIZE_WORD -#define DMA_CH5_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) -#define DMA_CH5_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) -#define DMA_CH5_CTRL_TRIG_DATA_SIZE_MSB _u(3) -#define DMA_CH5_CTRL_TRIG_DATA_SIZE_LSB _u(2) -#define DMA_CH5_CTRL_TRIG_DATA_SIZE_ACCESS "RW" -#define DMA_CH5_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) -#define DMA_CH5_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1) -#define DMA_CH5_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) -// ----------------------------------------------------------------------------- -// Field : DMA_CH5_CTRL_TRIG_HIGH_PRIORITY -// Description : HIGH_PRIORITY gives a channel preferential treatment in issue -// scheduling: in each scheduling round, all high priority -// channels are considered first, and then only a single low -// priority channel, before returning to the high priority -// channels. -// -// This only affects the order in which the DMA schedules -// channels. The DMA's bus priority is not changed. If the DMA is -// not saturated then a low priority channel will see no loss of -// throughput. -#define DMA_CH5_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0) -#define DMA_CH5_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002) -#define DMA_CH5_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1) -#define DMA_CH5_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1) -#define DMA_CH5_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH5_CTRL_TRIG_EN -// Description : DMA Channel Enable. -// When 1, the channel will respond to triggering events, which -// will cause it to become BUSY and start transferring data. When -// 0, the channel will ignore triggers, stop issuing transfers, -// and pause the current transfer sequence (i.e. BUSY will remain -// high if already high) -#define DMA_CH5_CTRL_TRIG_EN_RESET _u(0x0) -#define DMA_CH5_CTRL_TRIG_EN_BITS _u(0x00000001) -#define DMA_CH5_CTRL_TRIG_EN_MSB _u(0) -#define DMA_CH5_CTRL_TRIG_EN_LSB _u(0) -#define DMA_CH5_CTRL_TRIG_EN_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH5_AL1_CTRL -// Description : Alias for channel 5 CTRL register -#define DMA_CH5_AL1_CTRL_OFFSET _u(0x00000150) -#define DMA_CH5_AL1_CTRL_BITS _u(0xffffffff) -#define DMA_CH5_AL1_CTRL_RESET "-" -#define DMA_CH5_AL1_CTRL_MSB _u(31) -#define DMA_CH5_AL1_CTRL_LSB _u(0) -#define DMA_CH5_AL1_CTRL_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH5_AL1_READ_ADDR -// Description : Alias for channel 5 READ_ADDR register -#define DMA_CH5_AL1_READ_ADDR_OFFSET _u(0x00000154) -#define DMA_CH5_AL1_READ_ADDR_BITS _u(0xffffffff) -#define DMA_CH5_AL1_READ_ADDR_RESET "-" -#define DMA_CH5_AL1_READ_ADDR_MSB _u(31) -#define DMA_CH5_AL1_READ_ADDR_LSB _u(0) -#define DMA_CH5_AL1_READ_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH5_AL1_WRITE_ADDR -// Description : Alias for channel 5 WRITE_ADDR register -#define DMA_CH5_AL1_WRITE_ADDR_OFFSET _u(0x00000158) -#define DMA_CH5_AL1_WRITE_ADDR_BITS _u(0xffffffff) -#define DMA_CH5_AL1_WRITE_ADDR_RESET "-" -#define DMA_CH5_AL1_WRITE_ADDR_MSB _u(31) -#define DMA_CH5_AL1_WRITE_ADDR_LSB _u(0) -#define DMA_CH5_AL1_WRITE_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH5_AL1_TRANS_COUNT_TRIG -// Description : Alias for channel 5 TRANS_COUNT register -// This is a trigger register (0xc). Writing a nonzero value will -// reload the channel counter and start the channel. -#define DMA_CH5_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x0000015c) -#define DMA_CH5_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff) -#define DMA_CH5_AL1_TRANS_COUNT_TRIG_RESET "-" -#define DMA_CH5_AL1_TRANS_COUNT_TRIG_MSB _u(31) -#define DMA_CH5_AL1_TRANS_COUNT_TRIG_LSB _u(0) -#define DMA_CH5_AL1_TRANS_COUNT_TRIG_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH5_AL2_CTRL -// Description : Alias for channel 5 CTRL register -#define DMA_CH5_AL2_CTRL_OFFSET _u(0x00000160) -#define DMA_CH5_AL2_CTRL_BITS _u(0xffffffff) -#define DMA_CH5_AL2_CTRL_RESET "-" -#define DMA_CH5_AL2_CTRL_MSB _u(31) -#define DMA_CH5_AL2_CTRL_LSB _u(0) -#define DMA_CH5_AL2_CTRL_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH5_AL2_TRANS_COUNT -// Description : Alias for channel 5 TRANS_COUNT register -#define DMA_CH5_AL2_TRANS_COUNT_OFFSET _u(0x00000164) -#define DMA_CH5_AL2_TRANS_COUNT_BITS _u(0xffffffff) -#define DMA_CH5_AL2_TRANS_COUNT_RESET "-" -#define DMA_CH5_AL2_TRANS_COUNT_MSB _u(31) -#define DMA_CH5_AL2_TRANS_COUNT_LSB _u(0) -#define DMA_CH5_AL2_TRANS_COUNT_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH5_AL2_READ_ADDR -// Description : Alias for channel 5 READ_ADDR register -#define DMA_CH5_AL2_READ_ADDR_OFFSET _u(0x00000168) -#define DMA_CH5_AL2_READ_ADDR_BITS _u(0xffffffff) -#define DMA_CH5_AL2_READ_ADDR_RESET "-" -#define DMA_CH5_AL2_READ_ADDR_MSB _u(31) -#define DMA_CH5_AL2_READ_ADDR_LSB _u(0) -#define DMA_CH5_AL2_READ_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH5_AL2_WRITE_ADDR_TRIG -// Description : Alias for channel 5 WRITE_ADDR register -// This is a trigger register (0xc). Writing a nonzero value will -// reload the channel counter and start the channel. -#define DMA_CH5_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x0000016c) -#define DMA_CH5_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff) -#define DMA_CH5_AL2_WRITE_ADDR_TRIG_RESET "-" -#define DMA_CH5_AL2_WRITE_ADDR_TRIG_MSB _u(31) -#define DMA_CH5_AL2_WRITE_ADDR_TRIG_LSB _u(0) -#define DMA_CH5_AL2_WRITE_ADDR_TRIG_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH5_AL3_CTRL -// Description : Alias for channel 5 CTRL register -#define DMA_CH5_AL3_CTRL_OFFSET _u(0x00000170) -#define DMA_CH5_AL3_CTRL_BITS _u(0xffffffff) -#define DMA_CH5_AL3_CTRL_RESET "-" -#define DMA_CH5_AL3_CTRL_MSB _u(31) -#define DMA_CH5_AL3_CTRL_LSB _u(0) -#define DMA_CH5_AL3_CTRL_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH5_AL3_WRITE_ADDR -// Description : Alias for channel 5 WRITE_ADDR register -#define DMA_CH5_AL3_WRITE_ADDR_OFFSET _u(0x00000174) -#define DMA_CH5_AL3_WRITE_ADDR_BITS _u(0xffffffff) -#define DMA_CH5_AL3_WRITE_ADDR_RESET "-" -#define DMA_CH5_AL3_WRITE_ADDR_MSB _u(31) -#define DMA_CH5_AL3_WRITE_ADDR_LSB _u(0) -#define DMA_CH5_AL3_WRITE_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH5_AL3_TRANS_COUNT -// Description : Alias for channel 5 TRANS_COUNT register -#define DMA_CH5_AL3_TRANS_COUNT_OFFSET _u(0x00000178) -#define DMA_CH5_AL3_TRANS_COUNT_BITS _u(0xffffffff) -#define DMA_CH5_AL3_TRANS_COUNT_RESET "-" -#define DMA_CH5_AL3_TRANS_COUNT_MSB _u(31) -#define DMA_CH5_AL3_TRANS_COUNT_LSB _u(0) -#define DMA_CH5_AL3_TRANS_COUNT_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH5_AL3_READ_ADDR_TRIG -// Description : Alias for channel 5 READ_ADDR register -// This is a trigger register (0xc). Writing a nonzero value will -// reload the channel counter and start the channel. -#define DMA_CH5_AL3_READ_ADDR_TRIG_OFFSET _u(0x0000017c) -#define DMA_CH5_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff) -#define DMA_CH5_AL3_READ_ADDR_TRIG_RESET "-" -#define DMA_CH5_AL3_READ_ADDR_TRIG_MSB _u(31) -#define DMA_CH5_AL3_READ_ADDR_TRIG_LSB _u(0) -#define DMA_CH5_AL3_READ_ADDR_TRIG_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH6_READ_ADDR -// Description : DMA Channel 6 Read Address pointer -// This register updates automatically each time a read completes. -// The current value is the next address to be read by this -// channel. -#define DMA_CH6_READ_ADDR_OFFSET _u(0x00000180) -#define DMA_CH6_READ_ADDR_BITS _u(0xffffffff) -#define DMA_CH6_READ_ADDR_RESET _u(0x00000000) -#define DMA_CH6_READ_ADDR_MSB _u(31) -#define DMA_CH6_READ_ADDR_LSB _u(0) -#define DMA_CH6_READ_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH6_WRITE_ADDR -// Description : DMA Channel 6 Write Address pointer -// This register updates automatically each time a write -// completes. The current value is the next address to be written -// by this channel. -#define DMA_CH6_WRITE_ADDR_OFFSET _u(0x00000184) -#define DMA_CH6_WRITE_ADDR_BITS _u(0xffffffff) -#define DMA_CH6_WRITE_ADDR_RESET _u(0x00000000) -#define DMA_CH6_WRITE_ADDR_MSB _u(31) -#define DMA_CH6_WRITE_ADDR_LSB _u(0) -#define DMA_CH6_WRITE_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH6_TRANS_COUNT -// Description : DMA Channel 6 Transfer Count -// Program the number of bus transfers a channel will perform -// before halting. Note that, if transfers are larger than one -// byte in size, this is not equal to the number of bytes -// transferred (see CTRL_DATA_SIZE). -// -// When the channel is active, reading this register shows the -// number of transfers remaining, updating automatically each time -// a write transfer completes. -// -// Writing this register sets the RELOAD value for the transfer -// counter. Each time this channel is triggered, the RELOAD value -// is copied into the live transfer counter. The channel can be -// started multiple times, and will perform the same number of -// transfers each time, as programmed by most recent write. -// -// The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT -// is used as a trigger, the written value is used immediately as -// the length of the new transfer sequence, as well as being -// written to RELOAD. -#define DMA_CH6_TRANS_COUNT_OFFSET _u(0x00000188) -#define DMA_CH6_TRANS_COUNT_BITS _u(0xffffffff) -#define DMA_CH6_TRANS_COUNT_RESET _u(0x00000000) -#define DMA_CH6_TRANS_COUNT_MSB _u(31) -#define DMA_CH6_TRANS_COUNT_LSB _u(0) -#define DMA_CH6_TRANS_COUNT_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH6_CTRL_TRIG -// Description : DMA Channel 6 Control and Status -#define DMA_CH6_CTRL_TRIG_OFFSET _u(0x0000018c) -#define DMA_CH6_CTRL_TRIG_BITS _u(0xe1ffffff) -#define DMA_CH6_CTRL_TRIG_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : DMA_CH6_CTRL_TRIG_AHB_ERROR -// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel -// halts when it encounters any bus error, and always raises its -// channel IRQ flag. -#define DMA_CH6_CTRL_TRIG_AHB_ERROR_RESET _u(0x0) -#define DMA_CH6_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000) -#define DMA_CH6_CTRL_TRIG_AHB_ERROR_MSB _u(31) -#define DMA_CH6_CTRL_TRIG_AHB_ERROR_LSB _u(31) -#define DMA_CH6_CTRL_TRIG_AHB_ERROR_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : DMA_CH6_CTRL_TRIG_READ_ERROR -// Description : If 1, the channel received a read bus error. Write one to -// clear. -// READ_ADDR shows the approximate address where the bus error was -// encountered (will not be earlier, or more than 3 transfers -// later) -#define DMA_CH6_CTRL_TRIG_READ_ERROR_RESET _u(0x0) -#define DMA_CH6_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000) -#define DMA_CH6_CTRL_TRIG_READ_ERROR_MSB _u(30) -#define DMA_CH6_CTRL_TRIG_READ_ERROR_LSB _u(30) -#define DMA_CH6_CTRL_TRIG_READ_ERROR_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : DMA_CH6_CTRL_TRIG_WRITE_ERROR -// Description : If 1, the channel received a write bus error. Write one to -// clear. -// WRITE_ADDR shows the approximate address where the bus error -// was encountered (will not be earlier, or more than 5 transfers -// later) -#define DMA_CH6_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0) -#define DMA_CH6_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000) -#define DMA_CH6_CTRL_TRIG_WRITE_ERROR_MSB _u(29) -#define DMA_CH6_CTRL_TRIG_WRITE_ERROR_LSB _u(29) -#define DMA_CH6_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : DMA_CH6_CTRL_TRIG_BUSY -// Description : This flag goes high when the channel starts a new transfer -// sequence, and low when the last transfer of that sequence -// completes. Clearing EN while BUSY is high pauses the channel, -// and BUSY will stay high while paused. -// -// To terminate a sequence early (and clear the BUSY flag), see -// CHAN_ABORT. -#define DMA_CH6_CTRL_TRIG_BUSY_RESET _u(0x0) -#define DMA_CH6_CTRL_TRIG_BUSY_BITS _u(0x01000000) -#define DMA_CH6_CTRL_TRIG_BUSY_MSB _u(24) -#define DMA_CH6_CTRL_TRIG_BUSY_LSB _u(24) -#define DMA_CH6_CTRL_TRIG_BUSY_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : DMA_CH6_CTRL_TRIG_SNIFF_EN -// Description : If 1, this channel's data transfers are visible to the sniff -// hardware, and each transfer will advance the state of the -// checksum. This only applies if the sniff hardware is enabled, -// and has this channel selected. -// -// This allows checksum to be enabled or disabled on a per- -// control- block basis. -#define DMA_CH6_CTRL_TRIG_SNIFF_EN_RESET _u(0x0) -#define DMA_CH6_CTRL_TRIG_SNIFF_EN_BITS _u(0x00800000) -#define DMA_CH6_CTRL_TRIG_SNIFF_EN_MSB _u(23) -#define DMA_CH6_CTRL_TRIG_SNIFF_EN_LSB _u(23) -#define DMA_CH6_CTRL_TRIG_SNIFF_EN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH6_CTRL_TRIG_BSWAP -// Description : Apply byte-swap transformation to DMA data. -// For byte data, this has no effect. For halfword data, the two -// bytes of each halfword are swapped. For word data, the four -// bytes of each word are swapped to reverse order. -#define DMA_CH6_CTRL_TRIG_BSWAP_RESET _u(0x0) -#define DMA_CH6_CTRL_TRIG_BSWAP_BITS _u(0x00400000) -#define DMA_CH6_CTRL_TRIG_BSWAP_MSB _u(22) -#define DMA_CH6_CTRL_TRIG_BSWAP_LSB _u(22) -#define DMA_CH6_CTRL_TRIG_BSWAP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH6_CTRL_TRIG_IRQ_QUIET -// Description : In QUIET mode, the channel does not generate IRQs at the end of -// every transfer block. Instead, an IRQ is raised when NULL is -// written to a trigger register, indicating the end of a control -// block chain. -// -// This reduces the number of interrupts to be serviced by the CPU -// when transferring a DMA chain of many small control blocks. -#define DMA_CH6_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0) -#define DMA_CH6_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00200000) -#define DMA_CH6_CTRL_TRIG_IRQ_QUIET_MSB _u(21) -#define DMA_CH6_CTRL_TRIG_IRQ_QUIET_LSB _u(21) -#define DMA_CH6_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH6_CTRL_TRIG_TREQ_SEL -// Description : Select a Transfer Request signal. -// The channel uses the transfer request signal to pace its data -// transfer rate. Sources for TREQ signals are internal (TIMERS) -// or external (DREQ, a Data Request from the system). -// 0x0 to 0x3a -> select DREQ n as TREQ -// 0x3b -> Select Timer 0 as TREQ -// 0x3c -> Select Timer 1 as TREQ -// 0x3d -> Select Timer 2 as TREQ (Optional) -// 0x3e -> Select Timer 3 as TREQ (Optional) -// 0x3f -> Permanent request, for unpaced transfers. -#define DMA_CH6_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) -#define DMA_CH6_CTRL_TRIG_TREQ_SEL_BITS _u(0x001f8000) -#define DMA_CH6_CTRL_TRIG_TREQ_SEL_MSB _u(20) -#define DMA_CH6_CTRL_TRIG_TREQ_SEL_LSB _u(15) -#define DMA_CH6_CTRL_TRIG_TREQ_SEL_ACCESS "RW" -#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) -#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) -#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) -#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) -#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) -// ----------------------------------------------------------------------------- -// Field : DMA_CH6_CTRL_TRIG_CHAIN_TO -// Description : When this channel completes, it will trigger the channel -// indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this -// channel)_. -#define DMA_CH6_CTRL_TRIG_CHAIN_TO_RESET _u(0x0) -#define DMA_CH6_CTRL_TRIG_CHAIN_TO_BITS _u(0x00007800) -#define DMA_CH6_CTRL_TRIG_CHAIN_TO_MSB _u(14) -#define DMA_CH6_CTRL_TRIG_CHAIN_TO_LSB _u(11) -#define DMA_CH6_CTRL_TRIG_CHAIN_TO_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH6_CTRL_TRIG_RING_SEL -// Description : Select whether RING_SIZE applies to read or write addresses. -// If 0, read addresses are wrapped on a (1 << RING_SIZE) -// boundary. If 1, write addresses are wrapped. -#define DMA_CH6_CTRL_TRIG_RING_SEL_RESET _u(0x0) -#define DMA_CH6_CTRL_TRIG_RING_SEL_BITS _u(0x00000400) -#define DMA_CH6_CTRL_TRIG_RING_SEL_MSB _u(10) -#define DMA_CH6_CTRL_TRIG_RING_SEL_LSB _u(10) -#define DMA_CH6_CTRL_TRIG_RING_SEL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH6_CTRL_TRIG_RING_SIZE -// Description : Size of address wrap region. If 0, don't wrap. For values n > -// 0, only the lower n bits of the address will change. This wraps -// the address on a (1 << n) byte boundary, facilitating access to -// naturally-aligned ring buffers. -// -// Ring sizes between 2 and 32768 bytes are possible. This can -// apply to either read or write addresses, based on value of -// RING_SEL. -// 0x0 -> RING_NONE -#define DMA_CH6_CTRL_TRIG_RING_SIZE_RESET _u(0x0) -#define DMA_CH6_CTRL_TRIG_RING_SIZE_BITS _u(0x000003c0) -#define DMA_CH6_CTRL_TRIG_RING_SIZE_MSB _u(9) -#define DMA_CH6_CTRL_TRIG_RING_SIZE_LSB _u(6) -#define DMA_CH6_CTRL_TRIG_RING_SIZE_ACCESS "RW" -#define DMA_CH6_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0) -// ----------------------------------------------------------------------------- -// Field : DMA_CH6_CTRL_TRIG_INCR_WRITE -// Description : If 1, the write address increments with each transfer. If 0, -// each write is directed to the same, initial address. -// -// Generally this should be disabled for memory-to-peripheral -// transfers. -#define DMA_CH6_CTRL_TRIG_INCR_WRITE_RESET _u(0x0) -#define DMA_CH6_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000020) -#define DMA_CH6_CTRL_TRIG_INCR_WRITE_MSB _u(5) -#define DMA_CH6_CTRL_TRIG_INCR_WRITE_LSB _u(5) -#define DMA_CH6_CTRL_TRIG_INCR_WRITE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH6_CTRL_TRIG_INCR_READ -// Description : If 1, the read address increments with each transfer. If 0, -// each read is directed to the same, initial address. -// -// Generally this should be disabled for peripheral-to-memory -// transfers. -#define DMA_CH6_CTRL_TRIG_INCR_READ_RESET _u(0x0) -#define DMA_CH6_CTRL_TRIG_INCR_READ_BITS _u(0x00000010) -#define DMA_CH6_CTRL_TRIG_INCR_READ_MSB _u(4) -#define DMA_CH6_CTRL_TRIG_INCR_READ_LSB _u(4) -#define DMA_CH6_CTRL_TRIG_INCR_READ_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH6_CTRL_TRIG_DATA_SIZE -// Description : Set the size of each bus transfer (byte/halfword/word). -// READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) -// with each transfer. -// 0x0 -> SIZE_BYTE -// 0x1 -> SIZE_HALFWORD -// 0x2 -> SIZE_WORD -#define DMA_CH6_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) -#define DMA_CH6_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) -#define DMA_CH6_CTRL_TRIG_DATA_SIZE_MSB _u(3) -#define DMA_CH6_CTRL_TRIG_DATA_SIZE_LSB _u(2) -#define DMA_CH6_CTRL_TRIG_DATA_SIZE_ACCESS "RW" -#define DMA_CH6_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) -#define DMA_CH6_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1) -#define DMA_CH6_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) -// ----------------------------------------------------------------------------- -// Field : DMA_CH6_CTRL_TRIG_HIGH_PRIORITY -// Description : HIGH_PRIORITY gives a channel preferential treatment in issue -// scheduling: in each scheduling round, all high priority -// channels are considered first, and then only a single low -// priority channel, before returning to the high priority -// channels. -// -// This only affects the order in which the DMA schedules -// channels. The DMA's bus priority is not changed. If the DMA is -// not saturated then a low priority channel will see no loss of -// throughput. -#define DMA_CH6_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0) -#define DMA_CH6_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002) -#define DMA_CH6_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1) -#define DMA_CH6_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1) -#define DMA_CH6_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH6_CTRL_TRIG_EN -// Description : DMA Channel Enable. -// When 1, the channel will respond to triggering events, which -// will cause it to become BUSY and start transferring data. When -// 0, the channel will ignore triggers, stop issuing transfers, -// and pause the current transfer sequence (i.e. BUSY will remain -// high if already high) -#define DMA_CH6_CTRL_TRIG_EN_RESET _u(0x0) -#define DMA_CH6_CTRL_TRIG_EN_BITS _u(0x00000001) -#define DMA_CH6_CTRL_TRIG_EN_MSB _u(0) -#define DMA_CH6_CTRL_TRIG_EN_LSB _u(0) -#define DMA_CH6_CTRL_TRIG_EN_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH6_AL1_CTRL -// Description : Alias for channel 6 CTRL register -#define DMA_CH6_AL1_CTRL_OFFSET _u(0x00000190) -#define DMA_CH6_AL1_CTRL_BITS _u(0xffffffff) -#define DMA_CH6_AL1_CTRL_RESET "-" -#define DMA_CH6_AL1_CTRL_MSB _u(31) -#define DMA_CH6_AL1_CTRL_LSB _u(0) -#define DMA_CH6_AL1_CTRL_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH6_AL1_READ_ADDR -// Description : Alias for channel 6 READ_ADDR register -#define DMA_CH6_AL1_READ_ADDR_OFFSET _u(0x00000194) -#define DMA_CH6_AL1_READ_ADDR_BITS _u(0xffffffff) -#define DMA_CH6_AL1_READ_ADDR_RESET "-" -#define DMA_CH6_AL1_READ_ADDR_MSB _u(31) -#define DMA_CH6_AL1_READ_ADDR_LSB _u(0) -#define DMA_CH6_AL1_READ_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH6_AL1_WRITE_ADDR -// Description : Alias for channel 6 WRITE_ADDR register -#define DMA_CH6_AL1_WRITE_ADDR_OFFSET _u(0x00000198) -#define DMA_CH6_AL1_WRITE_ADDR_BITS _u(0xffffffff) -#define DMA_CH6_AL1_WRITE_ADDR_RESET "-" -#define DMA_CH6_AL1_WRITE_ADDR_MSB _u(31) -#define DMA_CH6_AL1_WRITE_ADDR_LSB _u(0) -#define DMA_CH6_AL1_WRITE_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH6_AL1_TRANS_COUNT_TRIG -// Description : Alias for channel 6 TRANS_COUNT register -// This is a trigger register (0xc). Writing a nonzero value will -// reload the channel counter and start the channel. -#define DMA_CH6_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x0000019c) -#define DMA_CH6_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff) -#define DMA_CH6_AL1_TRANS_COUNT_TRIG_RESET "-" -#define DMA_CH6_AL1_TRANS_COUNT_TRIG_MSB _u(31) -#define DMA_CH6_AL1_TRANS_COUNT_TRIG_LSB _u(0) -#define DMA_CH6_AL1_TRANS_COUNT_TRIG_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH6_AL2_CTRL -// Description : Alias for channel 6 CTRL register -#define DMA_CH6_AL2_CTRL_OFFSET _u(0x000001a0) -#define DMA_CH6_AL2_CTRL_BITS _u(0xffffffff) -#define DMA_CH6_AL2_CTRL_RESET "-" -#define DMA_CH6_AL2_CTRL_MSB _u(31) -#define DMA_CH6_AL2_CTRL_LSB _u(0) -#define DMA_CH6_AL2_CTRL_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH6_AL2_TRANS_COUNT -// Description : Alias for channel 6 TRANS_COUNT register -#define DMA_CH6_AL2_TRANS_COUNT_OFFSET _u(0x000001a4) -#define DMA_CH6_AL2_TRANS_COUNT_BITS _u(0xffffffff) -#define DMA_CH6_AL2_TRANS_COUNT_RESET "-" -#define DMA_CH6_AL2_TRANS_COUNT_MSB _u(31) -#define DMA_CH6_AL2_TRANS_COUNT_LSB _u(0) -#define DMA_CH6_AL2_TRANS_COUNT_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH6_AL2_READ_ADDR -// Description : Alias for channel 6 READ_ADDR register -#define DMA_CH6_AL2_READ_ADDR_OFFSET _u(0x000001a8) -#define DMA_CH6_AL2_READ_ADDR_BITS _u(0xffffffff) -#define DMA_CH6_AL2_READ_ADDR_RESET "-" -#define DMA_CH6_AL2_READ_ADDR_MSB _u(31) -#define DMA_CH6_AL2_READ_ADDR_LSB _u(0) -#define DMA_CH6_AL2_READ_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH6_AL2_WRITE_ADDR_TRIG -// Description : Alias for channel 6 WRITE_ADDR register -// This is a trigger register (0xc). Writing a nonzero value will -// reload the channel counter and start the channel. -#define DMA_CH6_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x000001ac) -#define DMA_CH6_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff) -#define DMA_CH6_AL2_WRITE_ADDR_TRIG_RESET "-" -#define DMA_CH6_AL2_WRITE_ADDR_TRIG_MSB _u(31) -#define DMA_CH6_AL2_WRITE_ADDR_TRIG_LSB _u(0) -#define DMA_CH6_AL2_WRITE_ADDR_TRIG_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH6_AL3_CTRL -// Description : Alias for channel 6 CTRL register -#define DMA_CH6_AL3_CTRL_OFFSET _u(0x000001b0) -#define DMA_CH6_AL3_CTRL_BITS _u(0xffffffff) -#define DMA_CH6_AL3_CTRL_RESET "-" -#define DMA_CH6_AL3_CTRL_MSB _u(31) -#define DMA_CH6_AL3_CTRL_LSB _u(0) -#define DMA_CH6_AL3_CTRL_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH6_AL3_WRITE_ADDR -// Description : Alias for channel 6 WRITE_ADDR register -#define DMA_CH6_AL3_WRITE_ADDR_OFFSET _u(0x000001b4) -#define DMA_CH6_AL3_WRITE_ADDR_BITS _u(0xffffffff) -#define DMA_CH6_AL3_WRITE_ADDR_RESET "-" -#define DMA_CH6_AL3_WRITE_ADDR_MSB _u(31) -#define DMA_CH6_AL3_WRITE_ADDR_LSB _u(0) -#define DMA_CH6_AL3_WRITE_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH6_AL3_TRANS_COUNT -// Description : Alias for channel 6 TRANS_COUNT register -#define DMA_CH6_AL3_TRANS_COUNT_OFFSET _u(0x000001b8) -#define DMA_CH6_AL3_TRANS_COUNT_BITS _u(0xffffffff) -#define DMA_CH6_AL3_TRANS_COUNT_RESET "-" -#define DMA_CH6_AL3_TRANS_COUNT_MSB _u(31) -#define DMA_CH6_AL3_TRANS_COUNT_LSB _u(0) -#define DMA_CH6_AL3_TRANS_COUNT_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH6_AL3_READ_ADDR_TRIG -// Description : Alias for channel 6 READ_ADDR register -// This is a trigger register (0xc). Writing a nonzero value will -// reload the channel counter and start the channel. -#define DMA_CH6_AL3_READ_ADDR_TRIG_OFFSET _u(0x000001bc) -#define DMA_CH6_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff) -#define DMA_CH6_AL3_READ_ADDR_TRIG_RESET "-" -#define DMA_CH6_AL3_READ_ADDR_TRIG_MSB _u(31) -#define DMA_CH6_AL3_READ_ADDR_TRIG_LSB _u(0) -#define DMA_CH6_AL3_READ_ADDR_TRIG_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH7_READ_ADDR -// Description : DMA Channel 7 Read Address pointer -// This register updates automatically each time a read completes. -// The current value is the next address to be read by this -// channel. -#define DMA_CH7_READ_ADDR_OFFSET _u(0x000001c0) -#define DMA_CH7_READ_ADDR_BITS _u(0xffffffff) -#define DMA_CH7_READ_ADDR_RESET _u(0x00000000) -#define DMA_CH7_READ_ADDR_MSB _u(31) -#define DMA_CH7_READ_ADDR_LSB _u(0) -#define DMA_CH7_READ_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH7_WRITE_ADDR -// Description : DMA Channel 7 Write Address pointer -// This register updates automatically each time a write -// completes. The current value is the next address to be written -// by this channel. -#define DMA_CH7_WRITE_ADDR_OFFSET _u(0x000001c4) -#define DMA_CH7_WRITE_ADDR_BITS _u(0xffffffff) -#define DMA_CH7_WRITE_ADDR_RESET _u(0x00000000) -#define DMA_CH7_WRITE_ADDR_MSB _u(31) -#define DMA_CH7_WRITE_ADDR_LSB _u(0) -#define DMA_CH7_WRITE_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH7_TRANS_COUNT -// Description : DMA Channel 7 Transfer Count -// Program the number of bus transfers a channel will perform -// before halting. Note that, if transfers are larger than one -// byte in size, this is not equal to the number of bytes -// transferred (see CTRL_DATA_SIZE). -// -// When the channel is active, reading this register shows the -// number of transfers remaining, updating automatically each time -// a write transfer completes. -// -// Writing this register sets the RELOAD value for the transfer -// counter. Each time this channel is triggered, the RELOAD value -// is copied into the live transfer counter. The channel can be -// started multiple times, and will perform the same number of -// transfers each time, as programmed by most recent write. -// -// The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT -// is used as a trigger, the written value is used immediately as -// the length of the new transfer sequence, as well as being -// written to RELOAD. -#define DMA_CH7_TRANS_COUNT_OFFSET _u(0x000001c8) -#define DMA_CH7_TRANS_COUNT_BITS _u(0xffffffff) -#define DMA_CH7_TRANS_COUNT_RESET _u(0x00000000) -#define DMA_CH7_TRANS_COUNT_MSB _u(31) -#define DMA_CH7_TRANS_COUNT_LSB _u(0) -#define DMA_CH7_TRANS_COUNT_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH7_CTRL_TRIG -// Description : DMA Channel 7 Control and Status -#define DMA_CH7_CTRL_TRIG_OFFSET _u(0x000001cc) -#define DMA_CH7_CTRL_TRIG_BITS _u(0xe1ffffff) -#define DMA_CH7_CTRL_TRIG_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : DMA_CH7_CTRL_TRIG_AHB_ERROR -// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel -// halts when it encounters any bus error, and always raises its -// channel IRQ flag. -#define DMA_CH7_CTRL_TRIG_AHB_ERROR_RESET _u(0x0) -#define DMA_CH7_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000) -#define DMA_CH7_CTRL_TRIG_AHB_ERROR_MSB _u(31) -#define DMA_CH7_CTRL_TRIG_AHB_ERROR_LSB _u(31) -#define DMA_CH7_CTRL_TRIG_AHB_ERROR_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : DMA_CH7_CTRL_TRIG_READ_ERROR -// Description : If 1, the channel received a read bus error. Write one to -// clear. -// READ_ADDR shows the approximate address where the bus error was -// encountered (will not be earlier, or more than 3 transfers -// later) -#define DMA_CH7_CTRL_TRIG_READ_ERROR_RESET _u(0x0) -#define DMA_CH7_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000) -#define DMA_CH7_CTRL_TRIG_READ_ERROR_MSB _u(30) -#define DMA_CH7_CTRL_TRIG_READ_ERROR_LSB _u(30) -#define DMA_CH7_CTRL_TRIG_READ_ERROR_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : DMA_CH7_CTRL_TRIG_WRITE_ERROR -// Description : If 1, the channel received a write bus error. Write one to -// clear. -// WRITE_ADDR shows the approximate address where the bus error -// was encountered (will not be earlier, or more than 5 transfers -// later) -#define DMA_CH7_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0) -#define DMA_CH7_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000) -#define DMA_CH7_CTRL_TRIG_WRITE_ERROR_MSB _u(29) -#define DMA_CH7_CTRL_TRIG_WRITE_ERROR_LSB _u(29) -#define DMA_CH7_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : DMA_CH7_CTRL_TRIG_BUSY -// Description : This flag goes high when the channel starts a new transfer -// sequence, and low when the last transfer of that sequence -// completes. Clearing EN while BUSY is high pauses the channel, -// and BUSY will stay high while paused. -// -// To terminate a sequence early (and clear the BUSY flag), see -// CHAN_ABORT. -#define DMA_CH7_CTRL_TRIG_BUSY_RESET _u(0x0) -#define DMA_CH7_CTRL_TRIG_BUSY_BITS _u(0x01000000) -#define DMA_CH7_CTRL_TRIG_BUSY_MSB _u(24) -#define DMA_CH7_CTRL_TRIG_BUSY_LSB _u(24) -#define DMA_CH7_CTRL_TRIG_BUSY_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : DMA_CH7_CTRL_TRIG_SNIFF_EN -// Description : If 1, this channel's data transfers are visible to the sniff -// hardware, and each transfer will advance the state of the -// checksum. This only applies if the sniff hardware is enabled, -// and has this channel selected. -// -// This allows checksum to be enabled or disabled on a per- -// control- block basis. -#define DMA_CH7_CTRL_TRIG_SNIFF_EN_RESET _u(0x0) -#define DMA_CH7_CTRL_TRIG_SNIFF_EN_BITS _u(0x00800000) -#define DMA_CH7_CTRL_TRIG_SNIFF_EN_MSB _u(23) -#define DMA_CH7_CTRL_TRIG_SNIFF_EN_LSB _u(23) -#define DMA_CH7_CTRL_TRIG_SNIFF_EN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH7_CTRL_TRIG_BSWAP -// Description : Apply byte-swap transformation to DMA data. -// For byte data, this has no effect. For halfword data, the two -// bytes of each halfword are swapped. For word data, the four -// bytes of each word are swapped to reverse order. -#define DMA_CH7_CTRL_TRIG_BSWAP_RESET _u(0x0) -#define DMA_CH7_CTRL_TRIG_BSWAP_BITS _u(0x00400000) -#define DMA_CH7_CTRL_TRIG_BSWAP_MSB _u(22) -#define DMA_CH7_CTRL_TRIG_BSWAP_LSB _u(22) -#define DMA_CH7_CTRL_TRIG_BSWAP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH7_CTRL_TRIG_IRQ_QUIET -// Description : In QUIET mode, the channel does not generate IRQs at the end of -// every transfer block. Instead, an IRQ is raised when NULL is -// written to a trigger register, indicating the end of a control -// block chain. -// -// This reduces the number of interrupts to be serviced by the CPU -// when transferring a DMA chain of many small control blocks. -#define DMA_CH7_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0) -#define DMA_CH7_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00200000) -#define DMA_CH7_CTRL_TRIG_IRQ_QUIET_MSB _u(21) -#define DMA_CH7_CTRL_TRIG_IRQ_QUIET_LSB _u(21) -#define DMA_CH7_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH7_CTRL_TRIG_TREQ_SEL -// Description : Select a Transfer Request signal. -// The channel uses the transfer request signal to pace its data -// transfer rate. Sources for TREQ signals are internal (TIMERS) -// or external (DREQ, a Data Request from the system). -// 0x0 to 0x3a -> select DREQ n as TREQ -// 0x3b -> Select Timer 0 as TREQ -// 0x3c -> Select Timer 1 as TREQ -// 0x3d -> Select Timer 2 as TREQ (Optional) -// 0x3e -> Select Timer 3 as TREQ (Optional) -// 0x3f -> Permanent request, for unpaced transfers. -#define DMA_CH7_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) -#define DMA_CH7_CTRL_TRIG_TREQ_SEL_BITS _u(0x001f8000) -#define DMA_CH7_CTRL_TRIG_TREQ_SEL_MSB _u(20) -#define DMA_CH7_CTRL_TRIG_TREQ_SEL_LSB _u(15) -#define DMA_CH7_CTRL_TRIG_TREQ_SEL_ACCESS "RW" -#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) -#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) -#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) -#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) -#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) -// ----------------------------------------------------------------------------- -// Field : DMA_CH7_CTRL_TRIG_CHAIN_TO -// Description : When this channel completes, it will trigger the channel -// indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this -// channel)_. -#define DMA_CH7_CTRL_TRIG_CHAIN_TO_RESET _u(0x0) -#define DMA_CH7_CTRL_TRIG_CHAIN_TO_BITS _u(0x00007800) -#define DMA_CH7_CTRL_TRIG_CHAIN_TO_MSB _u(14) -#define DMA_CH7_CTRL_TRIG_CHAIN_TO_LSB _u(11) -#define DMA_CH7_CTRL_TRIG_CHAIN_TO_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH7_CTRL_TRIG_RING_SEL -// Description : Select whether RING_SIZE applies to read or write addresses. -// If 0, read addresses are wrapped on a (1 << RING_SIZE) -// boundary. If 1, write addresses are wrapped. -#define DMA_CH7_CTRL_TRIG_RING_SEL_RESET _u(0x0) -#define DMA_CH7_CTRL_TRIG_RING_SEL_BITS _u(0x00000400) -#define DMA_CH7_CTRL_TRIG_RING_SEL_MSB _u(10) -#define DMA_CH7_CTRL_TRIG_RING_SEL_LSB _u(10) -#define DMA_CH7_CTRL_TRIG_RING_SEL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH7_CTRL_TRIG_RING_SIZE -// Description : Size of address wrap region. If 0, don't wrap. For values n > -// 0, only the lower n bits of the address will change. This wraps -// the address on a (1 << n) byte boundary, facilitating access to -// naturally-aligned ring buffers. -// -// Ring sizes between 2 and 32768 bytes are possible. This can -// apply to either read or write addresses, based on value of -// RING_SEL. -// 0x0 -> RING_NONE -#define DMA_CH7_CTRL_TRIG_RING_SIZE_RESET _u(0x0) -#define DMA_CH7_CTRL_TRIG_RING_SIZE_BITS _u(0x000003c0) -#define DMA_CH7_CTRL_TRIG_RING_SIZE_MSB _u(9) -#define DMA_CH7_CTRL_TRIG_RING_SIZE_LSB _u(6) -#define DMA_CH7_CTRL_TRIG_RING_SIZE_ACCESS "RW" -#define DMA_CH7_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0) -// ----------------------------------------------------------------------------- -// Field : DMA_CH7_CTRL_TRIG_INCR_WRITE -// Description : If 1, the write address increments with each transfer. If 0, -// each write is directed to the same, initial address. -// -// Generally this should be disabled for memory-to-peripheral -// transfers. -#define DMA_CH7_CTRL_TRIG_INCR_WRITE_RESET _u(0x0) -#define DMA_CH7_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000020) -#define DMA_CH7_CTRL_TRIG_INCR_WRITE_MSB _u(5) -#define DMA_CH7_CTRL_TRIG_INCR_WRITE_LSB _u(5) -#define DMA_CH7_CTRL_TRIG_INCR_WRITE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH7_CTRL_TRIG_INCR_READ -// Description : If 1, the read address increments with each transfer. If 0, -// each read is directed to the same, initial address. -// -// Generally this should be disabled for peripheral-to-memory -// transfers. -#define DMA_CH7_CTRL_TRIG_INCR_READ_RESET _u(0x0) -#define DMA_CH7_CTRL_TRIG_INCR_READ_BITS _u(0x00000010) -#define DMA_CH7_CTRL_TRIG_INCR_READ_MSB _u(4) -#define DMA_CH7_CTRL_TRIG_INCR_READ_LSB _u(4) -#define DMA_CH7_CTRL_TRIG_INCR_READ_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH7_CTRL_TRIG_DATA_SIZE -// Description : Set the size of each bus transfer (byte/halfword/word). -// READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) -// with each transfer. -// 0x0 -> SIZE_BYTE -// 0x1 -> SIZE_HALFWORD -// 0x2 -> SIZE_WORD -#define DMA_CH7_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) -#define DMA_CH7_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) -#define DMA_CH7_CTRL_TRIG_DATA_SIZE_MSB _u(3) -#define DMA_CH7_CTRL_TRIG_DATA_SIZE_LSB _u(2) -#define DMA_CH7_CTRL_TRIG_DATA_SIZE_ACCESS "RW" -#define DMA_CH7_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) -#define DMA_CH7_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1) -#define DMA_CH7_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) -// ----------------------------------------------------------------------------- -// Field : DMA_CH7_CTRL_TRIG_HIGH_PRIORITY -// Description : HIGH_PRIORITY gives a channel preferential treatment in issue -// scheduling: in each scheduling round, all high priority -// channels are considered first, and then only a single low -// priority channel, before returning to the high priority -// channels. -// -// This only affects the order in which the DMA schedules -// channels. The DMA's bus priority is not changed. If the DMA is -// not saturated then a low priority channel will see no loss of -// throughput. -#define DMA_CH7_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0) -#define DMA_CH7_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002) -#define DMA_CH7_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1) -#define DMA_CH7_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1) -#define DMA_CH7_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH7_CTRL_TRIG_EN -// Description : DMA Channel Enable. -// When 1, the channel will respond to triggering events, which -// will cause it to become BUSY and start transferring data. When -// 0, the channel will ignore triggers, stop issuing transfers, -// and pause the current transfer sequence (i.e. BUSY will remain -// high if already high) -#define DMA_CH7_CTRL_TRIG_EN_RESET _u(0x0) -#define DMA_CH7_CTRL_TRIG_EN_BITS _u(0x00000001) -#define DMA_CH7_CTRL_TRIG_EN_MSB _u(0) -#define DMA_CH7_CTRL_TRIG_EN_LSB _u(0) -#define DMA_CH7_CTRL_TRIG_EN_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH7_AL1_CTRL -// Description : Alias for channel 7 CTRL register -#define DMA_CH7_AL1_CTRL_OFFSET _u(0x000001d0) -#define DMA_CH7_AL1_CTRL_BITS _u(0xffffffff) -#define DMA_CH7_AL1_CTRL_RESET "-" -#define DMA_CH7_AL1_CTRL_MSB _u(31) -#define DMA_CH7_AL1_CTRL_LSB _u(0) -#define DMA_CH7_AL1_CTRL_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH7_AL1_READ_ADDR -// Description : Alias for channel 7 READ_ADDR register -#define DMA_CH7_AL1_READ_ADDR_OFFSET _u(0x000001d4) -#define DMA_CH7_AL1_READ_ADDR_BITS _u(0xffffffff) -#define DMA_CH7_AL1_READ_ADDR_RESET "-" -#define DMA_CH7_AL1_READ_ADDR_MSB _u(31) -#define DMA_CH7_AL1_READ_ADDR_LSB _u(0) -#define DMA_CH7_AL1_READ_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH7_AL1_WRITE_ADDR -// Description : Alias for channel 7 WRITE_ADDR register -#define DMA_CH7_AL1_WRITE_ADDR_OFFSET _u(0x000001d8) -#define DMA_CH7_AL1_WRITE_ADDR_BITS _u(0xffffffff) -#define DMA_CH7_AL1_WRITE_ADDR_RESET "-" -#define DMA_CH7_AL1_WRITE_ADDR_MSB _u(31) -#define DMA_CH7_AL1_WRITE_ADDR_LSB _u(0) -#define DMA_CH7_AL1_WRITE_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH7_AL1_TRANS_COUNT_TRIG -// Description : Alias for channel 7 TRANS_COUNT register -// This is a trigger register (0xc). Writing a nonzero value will -// reload the channel counter and start the channel. -#define DMA_CH7_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x000001dc) -#define DMA_CH7_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff) -#define DMA_CH7_AL1_TRANS_COUNT_TRIG_RESET "-" -#define DMA_CH7_AL1_TRANS_COUNT_TRIG_MSB _u(31) -#define DMA_CH7_AL1_TRANS_COUNT_TRIG_LSB _u(0) -#define DMA_CH7_AL1_TRANS_COUNT_TRIG_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH7_AL2_CTRL -// Description : Alias for channel 7 CTRL register -#define DMA_CH7_AL2_CTRL_OFFSET _u(0x000001e0) -#define DMA_CH7_AL2_CTRL_BITS _u(0xffffffff) -#define DMA_CH7_AL2_CTRL_RESET "-" -#define DMA_CH7_AL2_CTRL_MSB _u(31) -#define DMA_CH7_AL2_CTRL_LSB _u(0) -#define DMA_CH7_AL2_CTRL_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH7_AL2_TRANS_COUNT -// Description : Alias for channel 7 TRANS_COUNT register -#define DMA_CH7_AL2_TRANS_COUNT_OFFSET _u(0x000001e4) -#define DMA_CH7_AL2_TRANS_COUNT_BITS _u(0xffffffff) -#define DMA_CH7_AL2_TRANS_COUNT_RESET "-" -#define DMA_CH7_AL2_TRANS_COUNT_MSB _u(31) -#define DMA_CH7_AL2_TRANS_COUNT_LSB _u(0) -#define DMA_CH7_AL2_TRANS_COUNT_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH7_AL2_READ_ADDR -// Description : Alias for channel 7 READ_ADDR register -#define DMA_CH7_AL2_READ_ADDR_OFFSET _u(0x000001e8) -#define DMA_CH7_AL2_READ_ADDR_BITS _u(0xffffffff) -#define DMA_CH7_AL2_READ_ADDR_RESET "-" -#define DMA_CH7_AL2_READ_ADDR_MSB _u(31) -#define DMA_CH7_AL2_READ_ADDR_LSB _u(0) -#define DMA_CH7_AL2_READ_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH7_AL2_WRITE_ADDR_TRIG -// Description : Alias for channel 7 WRITE_ADDR register -// This is a trigger register (0xc). Writing a nonzero value will -// reload the channel counter and start the channel. -#define DMA_CH7_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x000001ec) -#define DMA_CH7_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff) -#define DMA_CH7_AL2_WRITE_ADDR_TRIG_RESET "-" -#define DMA_CH7_AL2_WRITE_ADDR_TRIG_MSB _u(31) -#define DMA_CH7_AL2_WRITE_ADDR_TRIG_LSB _u(0) -#define DMA_CH7_AL2_WRITE_ADDR_TRIG_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH7_AL3_CTRL -// Description : Alias for channel 7 CTRL register -#define DMA_CH7_AL3_CTRL_OFFSET _u(0x000001f0) -#define DMA_CH7_AL3_CTRL_BITS _u(0xffffffff) -#define DMA_CH7_AL3_CTRL_RESET "-" -#define DMA_CH7_AL3_CTRL_MSB _u(31) -#define DMA_CH7_AL3_CTRL_LSB _u(0) -#define DMA_CH7_AL3_CTRL_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH7_AL3_WRITE_ADDR -// Description : Alias for channel 7 WRITE_ADDR register -#define DMA_CH7_AL3_WRITE_ADDR_OFFSET _u(0x000001f4) -#define DMA_CH7_AL3_WRITE_ADDR_BITS _u(0xffffffff) -#define DMA_CH7_AL3_WRITE_ADDR_RESET "-" -#define DMA_CH7_AL3_WRITE_ADDR_MSB _u(31) -#define DMA_CH7_AL3_WRITE_ADDR_LSB _u(0) -#define DMA_CH7_AL3_WRITE_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH7_AL3_TRANS_COUNT -// Description : Alias for channel 7 TRANS_COUNT register -#define DMA_CH7_AL3_TRANS_COUNT_OFFSET _u(0x000001f8) -#define DMA_CH7_AL3_TRANS_COUNT_BITS _u(0xffffffff) -#define DMA_CH7_AL3_TRANS_COUNT_RESET "-" -#define DMA_CH7_AL3_TRANS_COUNT_MSB _u(31) -#define DMA_CH7_AL3_TRANS_COUNT_LSB _u(0) -#define DMA_CH7_AL3_TRANS_COUNT_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH7_AL3_READ_ADDR_TRIG -// Description : Alias for channel 7 READ_ADDR register -// This is a trigger register (0xc). Writing a nonzero value will -// reload the channel counter and start the channel. -#define DMA_CH7_AL3_READ_ADDR_TRIG_OFFSET _u(0x000001fc) -#define DMA_CH7_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff) -#define DMA_CH7_AL3_READ_ADDR_TRIG_RESET "-" -#define DMA_CH7_AL3_READ_ADDR_TRIG_MSB _u(31) -#define DMA_CH7_AL3_READ_ADDR_TRIG_LSB _u(0) -#define DMA_CH7_AL3_READ_ADDR_TRIG_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH8_READ_ADDR -// Description : DMA Channel 8 Read Address pointer -// This register updates automatically each time a read completes. -// The current value is the next address to be read by this -// channel. -#define DMA_CH8_READ_ADDR_OFFSET _u(0x00000200) -#define DMA_CH8_READ_ADDR_BITS _u(0xffffffff) -#define DMA_CH8_READ_ADDR_RESET _u(0x00000000) -#define DMA_CH8_READ_ADDR_MSB _u(31) -#define DMA_CH8_READ_ADDR_LSB _u(0) -#define DMA_CH8_READ_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH8_WRITE_ADDR -// Description : DMA Channel 8 Write Address pointer -// This register updates automatically each time a write -// completes. The current value is the next address to be written -// by this channel. -#define DMA_CH8_WRITE_ADDR_OFFSET _u(0x00000204) -#define DMA_CH8_WRITE_ADDR_BITS _u(0xffffffff) -#define DMA_CH8_WRITE_ADDR_RESET _u(0x00000000) -#define DMA_CH8_WRITE_ADDR_MSB _u(31) -#define DMA_CH8_WRITE_ADDR_LSB _u(0) -#define DMA_CH8_WRITE_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH8_TRANS_COUNT -// Description : DMA Channel 8 Transfer Count -// Program the number of bus transfers a channel will perform -// before halting. Note that, if transfers are larger than one -// byte in size, this is not equal to the number of bytes -// transferred (see CTRL_DATA_SIZE). -// -// When the channel is active, reading this register shows the -// number of transfers remaining, updating automatically each time -// a write transfer completes. -// -// Writing this register sets the RELOAD value for the transfer -// counter. Each time this channel is triggered, the RELOAD value -// is copied into the live transfer counter. The channel can be -// started multiple times, and will perform the same number of -// transfers each time, as programmed by most recent write. -// -// The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT -// is used as a trigger, the written value is used immediately as -// the length of the new transfer sequence, as well as being -// written to RELOAD. -#define DMA_CH8_TRANS_COUNT_OFFSET _u(0x00000208) -#define DMA_CH8_TRANS_COUNT_BITS _u(0xffffffff) -#define DMA_CH8_TRANS_COUNT_RESET _u(0x00000000) -#define DMA_CH8_TRANS_COUNT_MSB _u(31) -#define DMA_CH8_TRANS_COUNT_LSB _u(0) -#define DMA_CH8_TRANS_COUNT_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH8_CTRL_TRIG -// Description : DMA Channel 8 Control and Status -#define DMA_CH8_CTRL_TRIG_OFFSET _u(0x0000020c) -#define DMA_CH8_CTRL_TRIG_BITS _u(0xe1ffffff) -#define DMA_CH8_CTRL_TRIG_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : DMA_CH8_CTRL_TRIG_AHB_ERROR -// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel -// halts when it encounters any bus error, and always raises its -// channel IRQ flag. -#define DMA_CH8_CTRL_TRIG_AHB_ERROR_RESET _u(0x0) -#define DMA_CH8_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000) -#define DMA_CH8_CTRL_TRIG_AHB_ERROR_MSB _u(31) -#define DMA_CH8_CTRL_TRIG_AHB_ERROR_LSB _u(31) -#define DMA_CH8_CTRL_TRIG_AHB_ERROR_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : DMA_CH8_CTRL_TRIG_READ_ERROR -// Description : If 1, the channel received a read bus error. Write one to -// clear. -// READ_ADDR shows the approximate address where the bus error was -// encountered (will not be earlier, or more than 3 transfers -// later) -#define DMA_CH8_CTRL_TRIG_READ_ERROR_RESET _u(0x0) -#define DMA_CH8_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000) -#define DMA_CH8_CTRL_TRIG_READ_ERROR_MSB _u(30) -#define DMA_CH8_CTRL_TRIG_READ_ERROR_LSB _u(30) -#define DMA_CH8_CTRL_TRIG_READ_ERROR_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : DMA_CH8_CTRL_TRIG_WRITE_ERROR -// Description : If 1, the channel received a write bus error. Write one to -// clear. -// WRITE_ADDR shows the approximate address where the bus error -// was encountered (will not be earlier, or more than 5 transfers -// later) -#define DMA_CH8_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0) -#define DMA_CH8_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000) -#define DMA_CH8_CTRL_TRIG_WRITE_ERROR_MSB _u(29) -#define DMA_CH8_CTRL_TRIG_WRITE_ERROR_LSB _u(29) -#define DMA_CH8_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : DMA_CH8_CTRL_TRIG_BUSY -// Description : This flag goes high when the channel starts a new transfer -// sequence, and low when the last transfer of that sequence -// completes. Clearing EN while BUSY is high pauses the channel, -// and BUSY will stay high while paused. -// -// To terminate a sequence early (and clear the BUSY flag), see -// CHAN_ABORT. -#define DMA_CH8_CTRL_TRIG_BUSY_RESET _u(0x0) -#define DMA_CH8_CTRL_TRIG_BUSY_BITS _u(0x01000000) -#define DMA_CH8_CTRL_TRIG_BUSY_MSB _u(24) -#define DMA_CH8_CTRL_TRIG_BUSY_LSB _u(24) -#define DMA_CH8_CTRL_TRIG_BUSY_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : DMA_CH8_CTRL_TRIG_SNIFF_EN -// Description : If 1, this channel's data transfers are visible to the sniff -// hardware, and each transfer will advance the state of the -// checksum. This only applies if the sniff hardware is enabled, -// and has this channel selected. -// -// This allows checksum to be enabled or disabled on a per- -// control- block basis. -#define DMA_CH8_CTRL_TRIG_SNIFF_EN_RESET _u(0x0) -#define DMA_CH8_CTRL_TRIG_SNIFF_EN_BITS _u(0x00800000) -#define DMA_CH8_CTRL_TRIG_SNIFF_EN_MSB _u(23) -#define DMA_CH8_CTRL_TRIG_SNIFF_EN_LSB _u(23) -#define DMA_CH8_CTRL_TRIG_SNIFF_EN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH8_CTRL_TRIG_BSWAP -// Description : Apply byte-swap transformation to DMA data. -// For byte data, this has no effect. For halfword data, the two -// bytes of each halfword are swapped. For word data, the four -// bytes of each word are swapped to reverse order. -#define DMA_CH8_CTRL_TRIG_BSWAP_RESET _u(0x0) -#define DMA_CH8_CTRL_TRIG_BSWAP_BITS _u(0x00400000) -#define DMA_CH8_CTRL_TRIG_BSWAP_MSB _u(22) -#define DMA_CH8_CTRL_TRIG_BSWAP_LSB _u(22) -#define DMA_CH8_CTRL_TRIG_BSWAP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH8_CTRL_TRIG_IRQ_QUIET -// Description : In QUIET mode, the channel does not generate IRQs at the end of -// every transfer block. Instead, an IRQ is raised when NULL is -// written to a trigger register, indicating the end of a control -// block chain. -// -// This reduces the number of interrupts to be serviced by the CPU -// when transferring a DMA chain of many small control blocks. -#define DMA_CH8_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0) -#define DMA_CH8_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00200000) -#define DMA_CH8_CTRL_TRIG_IRQ_QUIET_MSB _u(21) -#define DMA_CH8_CTRL_TRIG_IRQ_QUIET_LSB _u(21) -#define DMA_CH8_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH8_CTRL_TRIG_TREQ_SEL -// Description : Select a Transfer Request signal. -// The channel uses the transfer request signal to pace its data -// transfer rate. Sources for TREQ signals are internal (TIMERS) -// or external (DREQ, a Data Request from the system). -// 0x0 to 0x3a -> select DREQ n as TREQ -// 0x3b -> Select Timer 0 as TREQ -// 0x3c -> Select Timer 1 as TREQ -// 0x3d -> Select Timer 2 as TREQ (Optional) -// 0x3e -> Select Timer 3 as TREQ (Optional) -// 0x3f -> Permanent request, for unpaced transfers. -#define DMA_CH8_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) -#define DMA_CH8_CTRL_TRIG_TREQ_SEL_BITS _u(0x001f8000) -#define DMA_CH8_CTRL_TRIG_TREQ_SEL_MSB _u(20) -#define DMA_CH8_CTRL_TRIG_TREQ_SEL_LSB _u(15) -#define DMA_CH8_CTRL_TRIG_TREQ_SEL_ACCESS "RW" -#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) -#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) -#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) -#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) -#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) -// ----------------------------------------------------------------------------- -// Field : DMA_CH8_CTRL_TRIG_CHAIN_TO -// Description : When this channel completes, it will trigger the channel -// indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this -// channel)_. -#define DMA_CH8_CTRL_TRIG_CHAIN_TO_RESET _u(0x0) -#define DMA_CH8_CTRL_TRIG_CHAIN_TO_BITS _u(0x00007800) -#define DMA_CH8_CTRL_TRIG_CHAIN_TO_MSB _u(14) -#define DMA_CH8_CTRL_TRIG_CHAIN_TO_LSB _u(11) -#define DMA_CH8_CTRL_TRIG_CHAIN_TO_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH8_CTRL_TRIG_RING_SEL -// Description : Select whether RING_SIZE applies to read or write addresses. -// If 0, read addresses are wrapped on a (1 << RING_SIZE) -// boundary. If 1, write addresses are wrapped. -#define DMA_CH8_CTRL_TRIG_RING_SEL_RESET _u(0x0) -#define DMA_CH8_CTRL_TRIG_RING_SEL_BITS _u(0x00000400) -#define DMA_CH8_CTRL_TRIG_RING_SEL_MSB _u(10) -#define DMA_CH8_CTRL_TRIG_RING_SEL_LSB _u(10) -#define DMA_CH8_CTRL_TRIG_RING_SEL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH8_CTRL_TRIG_RING_SIZE -// Description : Size of address wrap region. If 0, don't wrap. For values n > -// 0, only the lower n bits of the address will change. This wraps -// the address on a (1 << n) byte boundary, facilitating access to -// naturally-aligned ring buffers. -// -// Ring sizes between 2 and 32768 bytes are possible. This can -// apply to either read or write addresses, based on value of -// RING_SEL. -// 0x0 -> RING_NONE -#define DMA_CH8_CTRL_TRIG_RING_SIZE_RESET _u(0x0) -#define DMA_CH8_CTRL_TRIG_RING_SIZE_BITS _u(0x000003c0) -#define DMA_CH8_CTRL_TRIG_RING_SIZE_MSB _u(9) -#define DMA_CH8_CTRL_TRIG_RING_SIZE_LSB _u(6) -#define DMA_CH8_CTRL_TRIG_RING_SIZE_ACCESS "RW" -#define DMA_CH8_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0) -// ----------------------------------------------------------------------------- -// Field : DMA_CH8_CTRL_TRIG_INCR_WRITE -// Description : If 1, the write address increments with each transfer. If 0, -// each write is directed to the same, initial address. -// -// Generally this should be disabled for memory-to-peripheral -// transfers. -#define DMA_CH8_CTRL_TRIG_INCR_WRITE_RESET _u(0x0) -#define DMA_CH8_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000020) -#define DMA_CH8_CTRL_TRIG_INCR_WRITE_MSB _u(5) -#define DMA_CH8_CTRL_TRIG_INCR_WRITE_LSB _u(5) -#define DMA_CH8_CTRL_TRIG_INCR_WRITE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH8_CTRL_TRIG_INCR_READ -// Description : If 1, the read address increments with each transfer. If 0, -// each read is directed to the same, initial address. -// -// Generally this should be disabled for peripheral-to-memory -// transfers. -#define DMA_CH8_CTRL_TRIG_INCR_READ_RESET _u(0x0) -#define DMA_CH8_CTRL_TRIG_INCR_READ_BITS _u(0x00000010) -#define DMA_CH8_CTRL_TRIG_INCR_READ_MSB _u(4) -#define DMA_CH8_CTRL_TRIG_INCR_READ_LSB _u(4) -#define DMA_CH8_CTRL_TRIG_INCR_READ_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH8_CTRL_TRIG_DATA_SIZE -// Description : Set the size of each bus transfer (byte/halfword/word). -// READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) -// with each transfer. -// 0x0 -> SIZE_BYTE -// 0x1 -> SIZE_HALFWORD -// 0x2 -> SIZE_WORD -#define DMA_CH8_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) -#define DMA_CH8_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) -#define DMA_CH8_CTRL_TRIG_DATA_SIZE_MSB _u(3) -#define DMA_CH8_CTRL_TRIG_DATA_SIZE_LSB _u(2) -#define DMA_CH8_CTRL_TRIG_DATA_SIZE_ACCESS "RW" -#define DMA_CH8_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) -#define DMA_CH8_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1) -#define DMA_CH8_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) -// ----------------------------------------------------------------------------- -// Field : DMA_CH8_CTRL_TRIG_HIGH_PRIORITY -// Description : HIGH_PRIORITY gives a channel preferential treatment in issue -// scheduling: in each scheduling round, all high priority -// channels are considered first, and then only a single low -// priority channel, before returning to the high priority -// channels. -// -// This only affects the order in which the DMA schedules -// channels. The DMA's bus priority is not changed. If the DMA is -// not saturated then a low priority channel will see no loss of -// throughput. -#define DMA_CH8_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0) -#define DMA_CH8_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002) -#define DMA_CH8_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1) -#define DMA_CH8_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1) -#define DMA_CH8_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH8_CTRL_TRIG_EN -// Description : DMA Channel Enable. -// When 1, the channel will respond to triggering events, which -// will cause it to become BUSY and start transferring data. When -// 0, the channel will ignore triggers, stop issuing transfers, -// and pause the current transfer sequence (i.e. BUSY will remain -// high if already high) -#define DMA_CH8_CTRL_TRIG_EN_RESET _u(0x0) -#define DMA_CH8_CTRL_TRIG_EN_BITS _u(0x00000001) -#define DMA_CH8_CTRL_TRIG_EN_MSB _u(0) -#define DMA_CH8_CTRL_TRIG_EN_LSB _u(0) -#define DMA_CH8_CTRL_TRIG_EN_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH8_AL1_CTRL -// Description : Alias for channel 8 CTRL register -#define DMA_CH8_AL1_CTRL_OFFSET _u(0x00000210) -#define DMA_CH8_AL1_CTRL_BITS _u(0xffffffff) -#define DMA_CH8_AL1_CTRL_RESET "-" -#define DMA_CH8_AL1_CTRL_MSB _u(31) -#define DMA_CH8_AL1_CTRL_LSB _u(0) -#define DMA_CH8_AL1_CTRL_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH8_AL1_READ_ADDR -// Description : Alias for channel 8 READ_ADDR register -#define DMA_CH8_AL1_READ_ADDR_OFFSET _u(0x00000214) -#define DMA_CH8_AL1_READ_ADDR_BITS _u(0xffffffff) -#define DMA_CH8_AL1_READ_ADDR_RESET "-" -#define DMA_CH8_AL1_READ_ADDR_MSB _u(31) -#define DMA_CH8_AL1_READ_ADDR_LSB _u(0) -#define DMA_CH8_AL1_READ_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH8_AL1_WRITE_ADDR -// Description : Alias for channel 8 WRITE_ADDR register -#define DMA_CH8_AL1_WRITE_ADDR_OFFSET _u(0x00000218) -#define DMA_CH8_AL1_WRITE_ADDR_BITS _u(0xffffffff) -#define DMA_CH8_AL1_WRITE_ADDR_RESET "-" -#define DMA_CH8_AL1_WRITE_ADDR_MSB _u(31) -#define DMA_CH8_AL1_WRITE_ADDR_LSB _u(0) -#define DMA_CH8_AL1_WRITE_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH8_AL1_TRANS_COUNT_TRIG -// Description : Alias for channel 8 TRANS_COUNT register -// This is a trigger register (0xc). Writing a nonzero value will -// reload the channel counter and start the channel. -#define DMA_CH8_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x0000021c) -#define DMA_CH8_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff) -#define DMA_CH8_AL1_TRANS_COUNT_TRIG_RESET "-" -#define DMA_CH8_AL1_TRANS_COUNT_TRIG_MSB _u(31) -#define DMA_CH8_AL1_TRANS_COUNT_TRIG_LSB _u(0) -#define DMA_CH8_AL1_TRANS_COUNT_TRIG_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH8_AL2_CTRL -// Description : Alias for channel 8 CTRL register -#define DMA_CH8_AL2_CTRL_OFFSET _u(0x00000220) -#define DMA_CH8_AL2_CTRL_BITS _u(0xffffffff) -#define DMA_CH8_AL2_CTRL_RESET "-" -#define DMA_CH8_AL2_CTRL_MSB _u(31) -#define DMA_CH8_AL2_CTRL_LSB _u(0) -#define DMA_CH8_AL2_CTRL_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH8_AL2_TRANS_COUNT -// Description : Alias for channel 8 TRANS_COUNT register -#define DMA_CH8_AL2_TRANS_COUNT_OFFSET _u(0x00000224) -#define DMA_CH8_AL2_TRANS_COUNT_BITS _u(0xffffffff) -#define DMA_CH8_AL2_TRANS_COUNT_RESET "-" -#define DMA_CH8_AL2_TRANS_COUNT_MSB _u(31) -#define DMA_CH8_AL2_TRANS_COUNT_LSB _u(0) -#define DMA_CH8_AL2_TRANS_COUNT_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH8_AL2_READ_ADDR -// Description : Alias for channel 8 READ_ADDR register -#define DMA_CH8_AL2_READ_ADDR_OFFSET _u(0x00000228) -#define DMA_CH8_AL2_READ_ADDR_BITS _u(0xffffffff) -#define DMA_CH8_AL2_READ_ADDR_RESET "-" -#define DMA_CH8_AL2_READ_ADDR_MSB _u(31) -#define DMA_CH8_AL2_READ_ADDR_LSB _u(0) -#define DMA_CH8_AL2_READ_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH8_AL2_WRITE_ADDR_TRIG -// Description : Alias for channel 8 WRITE_ADDR register -// This is a trigger register (0xc). Writing a nonzero value will -// reload the channel counter and start the channel. -#define DMA_CH8_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x0000022c) -#define DMA_CH8_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff) -#define DMA_CH8_AL2_WRITE_ADDR_TRIG_RESET "-" -#define DMA_CH8_AL2_WRITE_ADDR_TRIG_MSB _u(31) -#define DMA_CH8_AL2_WRITE_ADDR_TRIG_LSB _u(0) -#define DMA_CH8_AL2_WRITE_ADDR_TRIG_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH8_AL3_CTRL -// Description : Alias for channel 8 CTRL register -#define DMA_CH8_AL3_CTRL_OFFSET _u(0x00000230) -#define DMA_CH8_AL3_CTRL_BITS _u(0xffffffff) -#define DMA_CH8_AL3_CTRL_RESET "-" -#define DMA_CH8_AL3_CTRL_MSB _u(31) -#define DMA_CH8_AL3_CTRL_LSB _u(0) -#define DMA_CH8_AL3_CTRL_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH8_AL3_WRITE_ADDR -// Description : Alias for channel 8 WRITE_ADDR register -#define DMA_CH8_AL3_WRITE_ADDR_OFFSET _u(0x00000234) -#define DMA_CH8_AL3_WRITE_ADDR_BITS _u(0xffffffff) -#define DMA_CH8_AL3_WRITE_ADDR_RESET "-" -#define DMA_CH8_AL3_WRITE_ADDR_MSB _u(31) -#define DMA_CH8_AL3_WRITE_ADDR_LSB _u(0) -#define DMA_CH8_AL3_WRITE_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH8_AL3_TRANS_COUNT -// Description : Alias for channel 8 TRANS_COUNT register -#define DMA_CH8_AL3_TRANS_COUNT_OFFSET _u(0x00000238) -#define DMA_CH8_AL3_TRANS_COUNT_BITS _u(0xffffffff) -#define DMA_CH8_AL3_TRANS_COUNT_RESET "-" -#define DMA_CH8_AL3_TRANS_COUNT_MSB _u(31) -#define DMA_CH8_AL3_TRANS_COUNT_LSB _u(0) -#define DMA_CH8_AL3_TRANS_COUNT_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH8_AL3_READ_ADDR_TRIG -// Description : Alias for channel 8 READ_ADDR register -// This is a trigger register (0xc). Writing a nonzero value will -// reload the channel counter and start the channel. -#define DMA_CH8_AL3_READ_ADDR_TRIG_OFFSET _u(0x0000023c) -#define DMA_CH8_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff) -#define DMA_CH8_AL3_READ_ADDR_TRIG_RESET "-" -#define DMA_CH8_AL3_READ_ADDR_TRIG_MSB _u(31) -#define DMA_CH8_AL3_READ_ADDR_TRIG_LSB _u(0) -#define DMA_CH8_AL3_READ_ADDR_TRIG_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH9_READ_ADDR -// Description : DMA Channel 9 Read Address pointer -// This register updates automatically each time a read completes. -// The current value is the next address to be read by this -// channel. -#define DMA_CH9_READ_ADDR_OFFSET _u(0x00000240) -#define DMA_CH9_READ_ADDR_BITS _u(0xffffffff) -#define DMA_CH9_READ_ADDR_RESET _u(0x00000000) -#define DMA_CH9_READ_ADDR_MSB _u(31) -#define DMA_CH9_READ_ADDR_LSB _u(0) -#define DMA_CH9_READ_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH9_WRITE_ADDR -// Description : DMA Channel 9 Write Address pointer -// This register updates automatically each time a write -// completes. The current value is the next address to be written -// by this channel. -#define DMA_CH9_WRITE_ADDR_OFFSET _u(0x00000244) -#define DMA_CH9_WRITE_ADDR_BITS _u(0xffffffff) -#define DMA_CH9_WRITE_ADDR_RESET _u(0x00000000) -#define DMA_CH9_WRITE_ADDR_MSB _u(31) -#define DMA_CH9_WRITE_ADDR_LSB _u(0) -#define DMA_CH9_WRITE_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH9_TRANS_COUNT -// Description : DMA Channel 9 Transfer Count -// Program the number of bus transfers a channel will perform -// before halting. Note that, if transfers are larger than one -// byte in size, this is not equal to the number of bytes -// transferred (see CTRL_DATA_SIZE). -// -// When the channel is active, reading this register shows the -// number of transfers remaining, updating automatically each time -// a write transfer completes. -// -// Writing this register sets the RELOAD value for the transfer -// counter. Each time this channel is triggered, the RELOAD value -// is copied into the live transfer counter. The channel can be -// started multiple times, and will perform the same number of -// transfers each time, as programmed by most recent write. -// -// The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT -// is used as a trigger, the written value is used immediately as -// the length of the new transfer sequence, as well as being -// written to RELOAD. -#define DMA_CH9_TRANS_COUNT_OFFSET _u(0x00000248) -#define DMA_CH9_TRANS_COUNT_BITS _u(0xffffffff) -#define DMA_CH9_TRANS_COUNT_RESET _u(0x00000000) -#define DMA_CH9_TRANS_COUNT_MSB _u(31) -#define DMA_CH9_TRANS_COUNT_LSB _u(0) -#define DMA_CH9_TRANS_COUNT_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH9_CTRL_TRIG -// Description : DMA Channel 9 Control and Status -#define DMA_CH9_CTRL_TRIG_OFFSET _u(0x0000024c) -#define DMA_CH9_CTRL_TRIG_BITS _u(0xe1ffffff) -#define DMA_CH9_CTRL_TRIG_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : DMA_CH9_CTRL_TRIG_AHB_ERROR -// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel -// halts when it encounters any bus error, and always raises its -// channel IRQ flag. -#define DMA_CH9_CTRL_TRIG_AHB_ERROR_RESET _u(0x0) -#define DMA_CH9_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000) -#define DMA_CH9_CTRL_TRIG_AHB_ERROR_MSB _u(31) -#define DMA_CH9_CTRL_TRIG_AHB_ERROR_LSB _u(31) -#define DMA_CH9_CTRL_TRIG_AHB_ERROR_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : DMA_CH9_CTRL_TRIG_READ_ERROR -// Description : If 1, the channel received a read bus error. Write one to -// clear. -// READ_ADDR shows the approximate address where the bus error was -// encountered (will not be earlier, or more than 3 transfers -// later) -#define DMA_CH9_CTRL_TRIG_READ_ERROR_RESET _u(0x0) -#define DMA_CH9_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000) -#define DMA_CH9_CTRL_TRIG_READ_ERROR_MSB _u(30) -#define DMA_CH9_CTRL_TRIG_READ_ERROR_LSB _u(30) -#define DMA_CH9_CTRL_TRIG_READ_ERROR_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : DMA_CH9_CTRL_TRIG_WRITE_ERROR -// Description : If 1, the channel received a write bus error. Write one to -// clear. -// WRITE_ADDR shows the approximate address where the bus error -// was encountered (will not be earlier, or more than 5 transfers -// later) -#define DMA_CH9_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0) -#define DMA_CH9_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000) -#define DMA_CH9_CTRL_TRIG_WRITE_ERROR_MSB _u(29) -#define DMA_CH9_CTRL_TRIG_WRITE_ERROR_LSB _u(29) -#define DMA_CH9_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : DMA_CH9_CTRL_TRIG_BUSY -// Description : This flag goes high when the channel starts a new transfer -// sequence, and low when the last transfer of that sequence -// completes. Clearing EN while BUSY is high pauses the channel, -// and BUSY will stay high while paused. -// -// To terminate a sequence early (and clear the BUSY flag), see -// CHAN_ABORT. -#define DMA_CH9_CTRL_TRIG_BUSY_RESET _u(0x0) -#define DMA_CH9_CTRL_TRIG_BUSY_BITS _u(0x01000000) -#define DMA_CH9_CTRL_TRIG_BUSY_MSB _u(24) -#define DMA_CH9_CTRL_TRIG_BUSY_LSB _u(24) -#define DMA_CH9_CTRL_TRIG_BUSY_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : DMA_CH9_CTRL_TRIG_SNIFF_EN -// Description : If 1, this channel's data transfers are visible to the sniff -// hardware, and each transfer will advance the state of the -// checksum. This only applies if the sniff hardware is enabled, -// and has this channel selected. -// -// This allows checksum to be enabled or disabled on a per- -// control- block basis. -#define DMA_CH9_CTRL_TRIG_SNIFF_EN_RESET _u(0x0) -#define DMA_CH9_CTRL_TRIG_SNIFF_EN_BITS _u(0x00800000) -#define DMA_CH9_CTRL_TRIG_SNIFF_EN_MSB _u(23) -#define DMA_CH9_CTRL_TRIG_SNIFF_EN_LSB _u(23) -#define DMA_CH9_CTRL_TRIG_SNIFF_EN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH9_CTRL_TRIG_BSWAP -// Description : Apply byte-swap transformation to DMA data. -// For byte data, this has no effect. For halfword data, the two -// bytes of each halfword are swapped. For word data, the four -// bytes of each word are swapped to reverse order. -#define DMA_CH9_CTRL_TRIG_BSWAP_RESET _u(0x0) -#define DMA_CH9_CTRL_TRIG_BSWAP_BITS _u(0x00400000) -#define DMA_CH9_CTRL_TRIG_BSWAP_MSB _u(22) -#define DMA_CH9_CTRL_TRIG_BSWAP_LSB _u(22) -#define DMA_CH9_CTRL_TRIG_BSWAP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH9_CTRL_TRIG_IRQ_QUIET -// Description : In QUIET mode, the channel does not generate IRQs at the end of -// every transfer block. Instead, an IRQ is raised when NULL is -// written to a trigger register, indicating the end of a control -// block chain. -// -// This reduces the number of interrupts to be serviced by the CPU -// when transferring a DMA chain of many small control blocks. -#define DMA_CH9_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0) -#define DMA_CH9_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00200000) -#define DMA_CH9_CTRL_TRIG_IRQ_QUIET_MSB _u(21) -#define DMA_CH9_CTRL_TRIG_IRQ_QUIET_LSB _u(21) -#define DMA_CH9_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH9_CTRL_TRIG_TREQ_SEL -// Description : Select a Transfer Request signal. -// The channel uses the transfer request signal to pace its data -// transfer rate. Sources for TREQ signals are internal (TIMERS) -// or external (DREQ, a Data Request from the system). -// 0x0 to 0x3a -> select DREQ n as TREQ -// 0x3b -> Select Timer 0 as TREQ -// 0x3c -> Select Timer 1 as TREQ -// 0x3d -> Select Timer 2 as TREQ (Optional) -// 0x3e -> Select Timer 3 as TREQ (Optional) -// 0x3f -> Permanent request, for unpaced transfers. -#define DMA_CH9_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) -#define DMA_CH9_CTRL_TRIG_TREQ_SEL_BITS _u(0x001f8000) -#define DMA_CH9_CTRL_TRIG_TREQ_SEL_MSB _u(20) -#define DMA_CH9_CTRL_TRIG_TREQ_SEL_LSB _u(15) -#define DMA_CH9_CTRL_TRIG_TREQ_SEL_ACCESS "RW" -#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) -#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) -#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) -#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) -#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) -// ----------------------------------------------------------------------------- -// Field : DMA_CH9_CTRL_TRIG_CHAIN_TO -// Description : When this channel completes, it will trigger the channel -// indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this -// channel)_. -#define DMA_CH9_CTRL_TRIG_CHAIN_TO_RESET _u(0x0) -#define DMA_CH9_CTRL_TRIG_CHAIN_TO_BITS _u(0x00007800) -#define DMA_CH9_CTRL_TRIG_CHAIN_TO_MSB _u(14) -#define DMA_CH9_CTRL_TRIG_CHAIN_TO_LSB _u(11) -#define DMA_CH9_CTRL_TRIG_CHAIN_TO_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH9_CTRL_TRIG_RING_SEL -// Description : Select whether RING_SIZE applies to read or write addresses. -// If 0, read addresses are wrapped on a (1 << RING_SIZE) -// boundary. If 1, write addresses are wrapped. -#define DMA_CH9_CTRL_TRIG_RING_SEL_RESET _u(0x0) -#define DMA_CH9_CTRL_TRIG_RING_SEL_BITS _u(0x00000400) -#define DMA_CH9_CTRL_TRIG_RING_SEL_MSB _u(10) -#define DMA_CH9_CTRL_TRIG_RING_SEL_LSB _u(10) -#define DMA_CH9_CTRL_TRIG_RING_SEL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH9_CTRL_TRIG_RING_SIZE -// Description : Size of address wrap region. If 0, don't wrap. For values n > -// 0, only the lower n bits of the address will change. This wraps -// the address on a (1 << n) byte boundary, facilitating access to -// naturally-aligned ring buffers. -// -// Ring sizes between 2 and 32768 bytes are possible. This can -// apply to either read or write addresses, based on value of -// RING_SEL. -// 0x0 -> RING_NONE -#define DMA_CH9_CTRL_TRIG_RING_SIZE_RESET _u(0x0) -#define DMA_CH9_CTRL_TRIG_RING_SIZE_BITS _u(0x000003c0) -#define DMA_CH9_CTRL_TRIG_RING_SIZE_MSB _u(9) -#define DMA_CH9_CTRL_TRIG_RING_SIZE_LSB _u(6) -#define DMA_CH9_CTRL_TRIG_RING_SIZE_ACCESS "RW" -#define DMA_CH9_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0) -// ----------------------------------------------------------------------------- -// Field : DMA_CH9_CTRL_TRIG_INCR_WRITE -// Description : If 1, the write address increments with each transfer. If 0, -// each write is directed to the same, initial address. -// -// Generally this should be disabled for memory-to-peripheral -// transfers. -#define DMA_CH9_CTRL_TRIG_INCR_WRITE_RESET _u(0x0) -#define DMA_CH9_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000020) -#define DMA_CH9_CTRL_TRIG_INCR_WRITE_MSB _u(5) -#define DMA_CH9_CTRL_TRIG_INCR_WRITE_LSB _u(5) -#define DMA_CH9_CTRL_TRIG_INCR_WRITE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH9_CTRL_TRIG_INCR_READ -// Description : If 1, the read address increments with each transfer. If 0, -// each read is directed to the same, initial address. -// -// Generally this should be disabled for peripheral-to-memory -// transfers. -#define DMA_CH9_CTRL_TRIG_INCR_READ_RESET _u(0x0) -#define DMA_CH9_CTRL_TRIG_INCR_READ_BITS _u(0x00000010) -#define DMA_CH9_CTRL_TRIG_INCR_READ_MSB _u(4) -#define DMA_CH9_CTRL_TRIG_INCR_READ_LSB _u(4) -#define DMA_CH9_CTRL_TRIG_INCR_READ_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH9_CTRL_TRIG_DATA_SIZE -// Description : Set the size of each bus transfer (byte/halfword/word). -// READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) -// with each transfer. -// 0x0 -> SIZE_BYTE -// 0x1 -> SIZE_HALFWORD -// 0x2 -> SIZE_WORD -#define DMA_CH9_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) -#define DMA_CH9_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) -#define DMA_CH9_CTRL_TRIG_DATA_SIZE_MSB _u(3) -#define DMA_CH9_CTRL_TRIG_DATA_SIZE_LSB _u(2) -#define DMA_CH9_CTRL_TRIG_DATA_SIZE_ACCESS "RW" -#define DMA_CH9_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) -#define DMA_CH9_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1) -#define DMA_CH9_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) -// ----------------------------------------------------------------------------- -// Field : DMA_CH9_CTRL_TRIG_HIGH_PRIORITY -// Description : HIGH_PRIORITY gives a channel preferential treatment in issue -// scheduling: in each scheduling round, all high priority -// channels are considered first, and then only a single low -// priority channel, before returning to the high priority -// channels. -// -// This only affects the order in which the DMA schedules -// channels. The DMA's bus priority is not changed. If the DMA is -// not saturated then a low priority channel will see no loss of -// throughput. -#define DMA_CH9_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0) -#define DMA_CH9_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002) -#define DMA_CH9_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1) -#define DMA_CH9_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1) -#define DMA_CH9_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH9_CTRL_TRIG_EN -// Description : DMA Channel Enable. -// When 1, the channel will respond to triggering events, which -// will cause it to become BUSY and start transferring data. When -// 0, the channel will ignore triggers, stop issuing transfers, -// and pause the current transfer sequence (i.e. BUSY will remain -// high if already high) -#define DMA_CH9_CTRL_TRIG_EN_RESET _u(0x0) -#define DMA_CH9_CTRL_TRIG_EN_BITS _u(0x00000001) -#define DMA_CH9_CTRL_TRIG_EN_MSB _u(0) -#define DMA_CH9_CTRL_TRIG_EN_LSB _u(0) -#define DMA_CH9_CTRL_TRIG_EN_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH9_AL1_CTRL -// Description : Alias for channel 9 CTRL register -#define DMA_CH9_AL1_CTRL_OFFSET _u(0x00000250) -#define DMA_CH9_AL1_CTRL_BITS _u(0xffffffff) -#define DMA_CH9_AL1_CTRL_RESET "-" -#define DMA_CH9_AL1_CTRL_MSB _u(31) -#define DMA_CH9_AL1_CTRL_LSB _u(0) -#define DMA_CH9_AL1_CTRL_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH9_AL1_READ_ADDR -// Description : Alias for channel 9 READ_ADDR register -#define DMA_CH9_AL1_READ_ADDR_OFFSET _u(0x00000254) -#define DMA_CH9_AL1_READ_ADDR_BITS _u(0xffffffff) -#define DMA_CH9_AL1_READ_ADDR_RESET "-" -#define DMA_CH9_AL1_READ_ADDR_MSB _u(31) -#define DMA_CH9_AL1_READ_ADDR_LSB _u(0) -#define DMA_CH9_AL1_READ_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH9_AL1_WRITE_ADDR -// Description : Alias for channel 9 WRITE_ADDR register -#define DMA_CH9_AL1_WRITE_ADDR_OFFSET _u(0x00000258) -#define DMA_CH9_AL1_WRITE_ADDR_BITS _u(0xffffffff) -#define DMA_CH9_AL1_WRITE_ADDR_RESET "-" -#define DMA_CH9_AL1_WRITE_ADDR_MSB _u(31) -#define DMA_CH9_AL1_WRITE_ADDR_LSB _u(0) -#define DMA_CH9_AL1_WRITE_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH9_AL1_TRANS_COUNT_TRIG -// Description : Alias for channel 9 TRANS_COUNT register -// This is a trigger register (0xc). Writing a nonzero value will -// reload the channel counter and start the channel. -#define DMA_CH9_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x0000025c) -#define DMA_CH9_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff) -#define DMA_CH9_AL1_TRANS_COUNT_TRIG_RESET "-" -#define DMA_CH9_AL1_TRANS_COUNT_TRIG_MSB _u(31) -#define DMA_CH9_AL1_TRANS_COUNT_TRIG_LSB _u(0) -#define DMA_CH9_AL1_TRANS_COUNT_TRIG_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH9_AL2_CTRL -// Description : Alias for channel 9 CTRL register -#define DMA_CH9_AL2_CTRL_OFFSET _u(0x00000260) -#define DMA_CH9_AL2_CTRL_BITS _u(0xffffffff) -#define DMA_CH9_AL2_CTRL_RESET "-" -#define DMA_CH9_AL2_CTRL_MSB _u(31) -#define DMA_CH9_AL2_CTRL_LSB _u(0) -#define DMA_CH9_AL2_CTRL_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH9_AL2_TRANS_COUNT -// Description : Alias for channel 9 TRANS_COUNT register -#define DMA_CH9_AL2_TRANS_COUNT_OFFSET _u(0x00000264) -#define DMA_CH9_AL2_TRANS_COUNT_BITS _u(0xffffffff) -#define DMA_CH9_AL2_TRANS_COUNT_RESET "-" -#define DMA_CH9_AL2_TRANS_COUNT_MSB _u(31) -#define DMA_CH9_AL2_TRANS_COUNT_LSB _u(0) -#define DMA_CH9_AL2_TRANS_COUNT_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH9_AL2_READ_ADDR -// Description : Alias for channel 9 READ_ADDR register -#define DMA_CH9_AL2_READ_ADDR_OFFSET _u(0x00000268) -#define DMA_CH9_AL2_READ_ADDR_BITS _u(0xffffffff) -#define DMA_CH9_AL2_READ_ADDR_RESET "-" -#define DMA_CH9_AL2_READ_ADDR_MSB _u(31) -#define DMA_CH9_AL2_READ_ADDR_LSB _u(0) -#define DMA_CH9_AL2_READ_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH9_AL2_WRITE_ADDR_TRIG -// Description : Alias for channel 9 WRITE_ADDR register -// This is a trigger register (0xc). Writing a nonzero value will -// reload the channel counter and start the channel. -#define DMA_CH9_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x0000026c) -#define DMA_CH9_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff) -#define DMA_CH9_AL2_WRITE_ADDR_TRIG_RESET "-" -#define DMA_CH9_AL2_WRITE_ADDR_TRIG_MSB _u(31) -#define DMA_CH9_AL2_WRITE_ADDR_TRIG_LSB _u(0) -#define DMA_CH9_AL2_WRITE_ADDR_TRIG_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH9_AL3_CTRL -// Description : Alias for channel 9 CTRL register -#define DMA_CH9_AL3_CTRL_OFFSET _u(0x00000270) -#define DMA_CH9_AL3_CTRL_BITS _u(0xffffffff) -#define DMA_CH9_AL3_CTRL_RESET "-" -#define DMA_CH9_AL3_CTRL_MSB _u(31) -#define DMA_CH9_AL3_CTRL_LSB _u(0) -#define DMA_CH9_AL3_CTRL_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH9_AL3_WRITE_ADDR -// Description : Alias for channel 9 WRITE_ADDR register -#define DMA_CH9_AL3_WRITE_ADDR_OFFSET _u(0x00000274) -#define DMA_CH9_AL3_WRITE_ADDR_BITS _u(0xffffffff) -#define DMA_CH9_AL3_WRITE_ADDR_RESET "-" -#define DMA_CH9_AL3_WRITE_ADDR_MSB _u(31) -#define DMA_CH9_AL3_WRITE_ADDR_LSB _u(0) -#define DMA_CH9_AL3_WRITE_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH9_AL3_TRANS_COUNT -// Description : Alias for channel 9 TRANS_COUNT register -#define DMA_CH9_AL3_TRANS_COUNT_OFFSET _u(0x00000278) -#define DMA_CH9_AL3_TRANS_COUNT_BITS _u(0xffffffff) -#define DMA_CH9_AL3_TRANS_COUNT_RESET "-" -#define DMA_CH9_AL3_TRANS_COUNT_MSB _u(31) -#define DMA_CH9_AL3_TRANS_COUNT_LSB _u(0) -#define DMA_CH9_AL3_TRANS_COUNT_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH9_AL3_READ_ADDR_TRIG -// Description : Alias for channel 9 READ_ADDR register -// This is a trigger register (0xc). Writing a nonzero value will -// reload the channel counter and start the channel. -#define DMA_CH9_AL3_READ_ADDR_TRIG_OFFSET _u(0x0000027c) -#define DMA_CH9_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff) -#define DMA_CH9_AL3_READ_ADDR_TRIG_RESET "-" -#define DMA_CH9_AL3_READ_ADDR_TRIG_MSB _u(31) -#define DMA_CH9_AL3_READ_ADDR_TRIG_LSB _u(0) -#define DMA_CH9_AL3_READ_ADDR_TRIG_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH10_READ_ADDR -// Description : DMA Channel 10 Read Address pointer -// This register updates automatically each time a read completes. -// The current value is the next address to be read by this -// channel. -#define DMA_CH10_READ_ADDR_OFFSET _u(0x00000280) -#define DMA_CH10_READ_ADDR_BITS _u(0xffffffff) -#define DMA_CH10_READ_ADDR_RESET _u(0x00000000) -#define DMA_CH10_READ_ADDR_MSB _u(31) -#define DMA_CH10_READ_ADDR_LSB _u(0) -#define DMA_CH10_READ_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH10_WRITE_ADDR -// Description : DMA Channel 10 Write Address pointer -// This register updates automatically each time a write -// completes. The current value is the next address to be written -// by this channel. -#define DMA_CH10_WRITE_ADDR_OFFSET _u(0x00000284) -#define DMA_CH10_WRITE_ADDR_BITS _u(0xffffffff) -#define DMA_CH10_WRITE_ADDR_RESET _u(0x00000000) -#define DMA_CH10_WRITE_ADDR_MSB _u(31) -#define DMA_CH10_WRITE_ADDR_LSB _u(0) -#define DMA_CH10_WRITE_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH10_TRANS_COUNT -// Description : DMA Channel 10 Transfer Count -// Program the number of bus transfers a channel will perform -// before halting. Note that, if transfers are larger than one -// byte in size, this is not equal to the number of bytes -// transferred (see CTRL_DATA_SIZE). -// -// When the channel is active, reading this register shows the -// number of transfers remaining, updating automatically each time -// a write transfer completes. -// -// Writing this register sets the RELOAD value for the transfer -// counter. Each time this channel is triggered, the RELOAD value -// is copied into the live transfer counter. The channel can be -// started multiple times, and will perform the same number of -// transfers each time, as programmed by most recent write. -// -// The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT -// is used as a trigger, the written value is used immediately as -// the length of the new transfer sequence, as well as being -// written to RELOAD. -#define DMA_CH10_TRANS_COUNT_OFFSET _u(0x00000288) -#define DMA_CH10_TRANS_COUNT_BITS _u(0xffffffff) -#define DMA_CH10_TRANS_COUNT_RESET _u(0x00000000) -#define DMA_CH10_TRANS_COUNT_MSB _u(31) -#define DMA_CH10_TRANS_COUNT_LSB _u(0) -#define DMA_CH10_TRANS_COUNT_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH10_CTRL_TRIG -// Description : DMA Channel 10 Control and Status -#define DMA_CH10_CTRL_TRIG_OFFSET _u(0x0000028c) -#define DMA_CH10_CTRL_TRIG_BITS _u(0xe1ffffff) -#define DMA_CH10_CTRL_TRIG_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : DMA_CH10_CTRL_TRIG_AHB_ERROR -// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel -// halts when it encounters any bus error, and always raises its -// channel IRQ flag. -#define DMA_CH10_CTRL_TRIG_AHB_ERROR_RESET _u(0x0) -#define DMA_CH10_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000) -#define DMA_CH10_CTRL_TRIG_AHB_ERROR_MSB _u(31) -#define DMA_CH10_CTRL_TRIG_AHB_ERROR_LSB _u(31) -#define DMA_CH10_CTRL_TRIG_AHB_ERROR_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : DMA_CH10_CTRL_TRIG_READ_ERROR -// Description : If 1, the channel received a read bus error. Write one to -// clear. -// READ_ADDR shows the approximate address where the bus error was -// encountered (will not be earlier, or more than 3 transfers -// later) -#define DMA_CH10_CTRL_TRIG_READ_ERROR_RESET _u(0x0) -#define DMA_CH10_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000) -#define DMA_CH10_CTRL_TRIG_READ_ERROR_MSB _u(30) -#define DMA_CH10_CTRL_TRIG_READ_ERROR_LSB _u(30) -#define DMA_CH10_CTRL_TRIG_READ_ERROR_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : DMA_CH10_CTRL_TRIG_WRITE_ERROR -// Description : If 1, the channel received a write bus error. Write one to -// clear. -// WRITE_ADDR shows the approximate address where the bus error -// was encountered (will not be earlier, or more than 5 transfers -// later) -#define DMA_CH10_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0) -#define DMA_CH10_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000) -#define DMA_CH10_CTRL_TRIG_WRITE_ERROR_MSB _u(29) -#define DMA_CH10_CTRL_TRIG_WRITE_ERROR_LSB _u(29) -#define DMA_CH10_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : DMA_CH10_CTRL_TRIG_BUSY -// Description : This flag goes high when the channel starts a new transfer -// sequence, and low when the last transfer of that sequence -// completes. Clearing EN while BUSY is high pauses the channel, -// and BUSY will stay high while paused. -// -// To terminate a sequence early (and clear the BUSY flag), see -// CHAN_ABORT. -#define DMA_CH10_CTRL_TRIG_BUSY_RESET _u(0x0) -#define DMA_CH10_CTRL_TRIG_BUSY_BITS _u(0x01000000) -#define DMA_CH10_CTRL_TRIG_BUSY_MSB _u(24) -#define DMA_CH10_CTRL_TRIG_BUSY_LSB _u(24) -#define DMA_CH10_CTRL_TRIG_BUSY_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : DMA_CH10_CTRL_TRIG_SNIFF_EN -// Description : If 1, this channel's data transfers are visible to the sniff -// hardware, and each transfer will advance the state of the -// checksum. This only applies if the sniff hardware is enabled, -// and has this channel selected. -// -// This allows checksum to be enabled or disabled on a per- -// control- block basis. -#define DMA_CH10_CTRL_TRIG_SNIFF_EN_RESET _u(0x0) -#define DMA_CH10_CTRL_TRIG_SNIFF_EN_BITS _u(0x00800000) -#define DMA_CH10_CTRL_TRIG_SNIFF_EN_MSB _u(23) -#define DMA_CH10_CTRL_TRIG_SNIFF_EN_LSB _u(23) -#define DMA_CH10_CTRL_TRIG_SNIFF_EN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH10_CTRL_TRIG_BSWAP -// Description : Apply byte-swap transformation to DMA data. -// For byte data, this has no effect. For halfword data, the two -// bytes of each halfword are swapped. For word data, the four -// bytes of each word are swapped to reverse order. -#define DMA_CH10_CTRL_TRIG_BSWAP_RESET _u(0x0) -#define DMA_CH10_CTRL_TRIG_BSWAP_BITS _u(0x00400000) -#define DMA_CH10_CTRL_TRIG_BSWAP_MSB _u(22) -#define DMA_CH10_CTRL_TRIG_BSWAP_LSB _u(22) -#define DMA_CH10_CTRL_TRIG_BSWAP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH10_CTRL_TRIG_IRQ_QUIET -// Description : In QUIET mode, the channel does not generate IRQs at the end of -// every transfer block. Instead, an IRQ is raised when NULL is -// written to a trigger register, indicating the end of a control -// block chain. -// -// This reduces the number of interrupts to be serviced by the CPU -// when transferring a DMA chain of many small control blocks. -#define DMA_CH10_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0) -#define DMA_CH10_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00200000) -#define DMA_CH10_CTRL_TRIG_IRQ_QUIET_MSB _u(21) -#define DMA_CH10_CTRL_TRIG_IRQ_QUIET_LSB _u(21) -#define DMA_CH10_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH10_CTRL_TRIG_TREQ_SEL -// Description : Select a Transfer Request signal. -// The channel uses the transfer request signal to pace its data -// transfer rate. Sources for TREQ signals are internal (TIMERS) -// or external (DREQ, a Data Request from the system). -// 0x0 to 0x3a -> select DREQ n as TREQ -// 0x3b -> Select Timer 0 as TREQ -// 0x3c -> Select Timer 1 as TREQ -// 0x3d -> Select Timer 2 as TREQ (Optional) -// 0x3e -> Select Timer 3 as TREQ (Optional) -// 0x3f -> Permanent request, for unpaced transfers. -#define DMA_CH10_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) -#define DMA_CH10_CTRL_TRIG_TREQ_SEL_BITS _u(0x001f8000) -#define DMA_CH10_CTRL_TRIG_TREQ_SEL_MSB _u(20) -#define DMA_CH10_CTRL_TRIG_TREQ_SEL_LSB _u(15) -#define DMA_CH10_CTRL_TRIG_TREQ_SEL_ACCESS "RW" -#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) -#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) -#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) -#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) -#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) -// ----------------------------------------------------------------------------- -// Field : DMA_CH10_CTRL_TRIG_CHAIN_TO -// Description : When this channel completes, it will trigger the channel -// indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this -// channel)_. -#define DMA_CH10_CTRL_TRIG_CHAIN_TO_RESET _u(0x0) -#define DMA_CH10_CTRL_TRIG_CHAIN_TO_BITS _u(0x00007800) -#define DMA_CH10_CTRL_TRIG_CHAIN_TO_MSB _u(14) -#define DMA_CH10_CTRL_TRIG_CHAIN_TO_LSB _u(11) -#define DMA_CH10_CTRL_TRIG_CHAIN_TO_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH10_CTRL_TRIG_RING_SEL -// Description : Select whether RING_SIZE applies to read or write addresses. -// If 0, read addresses are wrapped on a (1 << RING_SIZE) -// boundary. If 1, write addresses are wrapped. -#define DMA_CH10_CTRL_TRIG_RING_SEL_RESET _u(0x0) -#define DMA_CH10_CTRL_TRIG_RING_SEL_BITS _u(0x00000400) -#define DMA_CH10_CTRL_TRIG_RING_SEL_MSB _u(10) -#define DMA_CH10_CTRL_TRIG_RING_SEL_LSB _u(10) -#define DMA_CH10_CTRL_TRIG_RING_SEL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH10_CTRL_TRIG_RING_SIZE -// Description : Size of address wrap region. If 0, don't wrap. For values n > -// 0, only the lower n bits of the address will change. This wraps -// the address on a (1 << n) byte boundary, facilitating access to -// naturally-aligned ring buffers. -// -// Ring sizes between 2 and 32768 bytes are possible. This can -// apply to either read or write addresses, based on value of -// RING_SEL. -// 0x0 -> RING_NONE -#define DMA_CH10_CTRL_TRIG_RING_SIZE_RESET _u(0x0) -#define DMA_CH10_CTRL_TRIG_RING_SIZE_BITS _u(0x000003c0) -#define DMA_CH10_CTRL_TRIG_RING_SIZE_MSB _u(9) -#define DMA_CH10_CTRL_TRIG_RING_SIZE_LSB _u(6) -#define DMA_CH10_CTRL_TRIG_RING_SIZE_ACCESS "RW" -#define DMA_CH10_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0) -// ----------------------------------------------------------------------------- -// Field : DMA_CH10_CTRL_TRIG_INCR_WRITE -// Description : If 1, the write address increments with each transfer. If 0, -// each write is directed to the same, initial address. -// -// Generally this should be disabled for memory-to-peripheral -// transfers. -#define DMA_CH10_CTRL_TRIG_INCR_WRITE_RESET _u(0x0) -#define DMA_CH10_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000020) -#define DMA_CH10_CTRL_TRIG_INCR_WRITE_MSB _u(5) -#define DMA_CH10_CTRL_TRIG_INCR_WRITE_LSB _u(5) -#define DMA_CH10_CTRL_TRIG_INCR_WRITE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH10_CTRL_TRIG_INCR_READ -// Description : If 1, the read address increments with each transfer. If 0, -// each read is directed to the same, initial address. -// -// Generally this should be disabled for peripheral-to-memory -// transfers. -#define DMA_CH10_CTRL_TRIG_INCR_READ_RESET _u(0x0) -#define DMA_CH10_CTRL_TRIG_INCR_READ_BITS _u(0x00000010) -#define DMA_CH10_CTRL_TRIG_INCR_READ_MSB _u(4) -#define DMA_CH10_CTRL_TRIG_INCR_READ_LSB _u(4) -#define DMA_CH10_CTRL_TRIG_INCR_READ_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH10_CTRL_TRIG_DATA_SIZE -// Description : Set the size of each bus transfer (byte/halfword/word). -// READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) -// with each transfer. -// 0x0 -> SIZE_BYTE -// 0x1 -> SIZE_HALFWORD -// 0x2 -> SIZE_WORD -#define DMA_CH10_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) -#define DMA_CH10_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) -#define DMA_CH10_CTRL_TRIG_DATA_SIZE_MSB _u(3) -#define DMA_CH10_CTRL_TRIG_DATA_SIZE_LSB _u(2) -#define DMA_CH10_CTRL_TRIG_DATA_SIZE_ACCESS "RW" -#define DMA_CH10_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) -#define DMA_CH10_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1) -#define DMA_CH10_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) -// ----------------------------------------------------------------------------- -// Field : DMA_CH10_CTRL_TRIG_HIGH_PRIORITY -// Description : HIGH_PRIORITY gives a channel preferential treatment in issue -// scheduling: in each scheduling round, all high priority -// channels are considered first, and then only a single low -// priority channel, before returning to the high priority -// channels. -// -// This only affects the order in which the DMA schedules -// channels. The DMA's bus priority is not changed. If the DMA is -// not saturated then a low priority channel will see no loss of -// throughput. -#define DMA_CH10_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0) -#define DMA_CH10_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002) -#define DMA_CH10_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1) -#define DMA_CH10_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1) -#define DMA_CH10_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH10_CTRL_TRIG_EN -// Description : DMA Channel Enable. -// When 1, the channel will respond to triggering events, which -// will cause it to become BUSY and start transferring data. When -// 0, the channel will ignore triggers, stop issuing transfers, -// and pause the current transfer sequence (i.e. BUSY will remain -// high if already high) -#define DMA_CH10_CTRL_TRIG_EN_RESET _u(0x0) -#define DMA_CH10_CTRL_TRIG_EN_BITS _u(0x00000001) -#define DMA_CH10_CTRL_TRIG_EN_MSB _u(0) -#define DMA_CH10_CTRL_TRIG_EN_LSB _u(0) -#define DMA_CH10_CTRL_TRIG_EN_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH10_AL1_CTRL -// Description : Alias for channel 10 CTRL register -#define DMA_CH10_AL1_CTRL_OFFSET _u(0x00000290) -#define DMA_CH10_AL1_CTRL_BITS _u(0xffffffff) -#define DMA_CH10_AL1_CTRL_RESET "-" -#define DMA_CH10_AL1_CTRL_MSB _u(31) -#define DMA_CH10_AL1_CTRL_LSB _u(0) -#define DMA_CH10_AL1_CTRL_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH10_AL1_READ_ADDR -// Description : Alias for channel 10 READ_ADDR register -#define DMA_CH10_AL1_READ_ADDR_OFFSET _u(0x00000294) -#define DMA_CH10_AL1_READ_ADDR_BITS _u(0xffffffff) -#define DMA_CH10_AL1_READ_ADDR_RESET "-" -#define DMA_CH10_AL1_READ_ADDR_MSB _u(31) -#define DMA_CH10_AL1_READ_ADDR_LSB _u(0) -#define DMA_CH10_AL1_READ_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH10_AL1_WRITE_ADDR -// Description : Alias for channel 10 WRITE_ADDR register -#define DMA_CH10_AL1_WRITE_ADDR_OFFSET _u(0x00000298) -#define DMA_CH10_AL1_WRITE_ADDR_BITS _u(0xffffffff) -#define DMA_CH10_AL1_WRITE_ADDR_RESET "-" -#define DMA_CH10_AL1_WRITE_ADDR_MSB _u(31) -#define DMA_CH10_AL1_WRITE_ADDR_LSB _u(0) -#define DMA_CH10_AL1_WRITE_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH10_AL1_TRANS_COUNT_TRIG -// Description : Alias for channel 10 TRANS_COUNT register -// This is a trigger register (0xc). Writing a nonzero value will -// reload the channel counter and start the channel. -#define DMA_CH10_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x0000029c) -#define DMA_CH10_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff) -#define DMA_CH10_AL1_TRANS_COUNT_TRIG_RESET "-" -#define DMA_CH10_AL1_TRANS_COUNT_TRIG_MSB _u(31) -#define DMA_CH10_AL1_TRANS_COUNT_TRIG_LSB _u(0) -#define DMA_CH10_AL1_TRANS_COUNT_TRIG_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH10_AL2_CTRL -// Description : Alias for channel 10 CTRL register -#define DMA_CH10_AL2_CTRL_OFFSET _u(0x000002a0) -#define DMA_CH10_AL2_CTRL_BITS _u(0xffffffff) -#define DMA_CH10_AL2_CTRL_RESET "-" -#define DMA_CH10_AL2_CTRL_MSB _u(31) -#define DMA_CH10_AL2_CTRL_LSB _u(0) -#define DMA_CH10_AL2_CTRL_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH10_AL2_TRANS_COUNT -// Description : Alias for channel 10 TRANS_COUNT register -#define DMA_CH10_AL2_TRANS_COUNT_OFFSET _u(0x000002a4) -#define DMA_CH10_AL2_TRANS_COUNT_BITS _u(0xffffffff) -#define DMA_CH10_AL2_TRANS_COUNT_RESET "-" -#define DMA_CH10_AL2_TRANS_COUNT_MSB _u(31) -#define DMA_CH10_AL2_TRANS_COUNT_LSB _u(0) -#define DMA_CH10_AL2_TRANS_COUNT_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH10_AL2_READ_ADDR -// Description : Alias for channel 10 READ_ADDR register -#define DMA_CH10_AL2_READ_ADDR_OFFSET _u(0x000002a8) -#define DMA_CH10_AL2_READ_ADDR_BITS _u(0xffffffff) -#define DMA_CH10_AL2_READ_ADDR_RESET "-" -#define DMA_CH10_AL2_READ_ADDR_MSB _u(31) -#define DMA_CH10_AL2_READ_ADDR_LSB _u(0) -#define DMA_CH10_AL2_READ_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH10_AL2_WRITE_ADDR_TRIG -// Description : Alias for channel 10 WRITE_ADDR register -// This is a trigger register (0xc). Writing a nonzero value will -// reload the channel counter and start the channel. -#define DMA_CH10_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x000002ac) -#define DMA_CH10_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff) -#define DMA_CH10_AL2_WRITE_ADDR_TRIG_RESET "-" -#define DMA_CH10_AL2_WRITE_ADDR_TRIG_MSB _u(31) -#define DMA_CH10_AL2_WRITE_ADDR_TRIG_LSB _u(0) -#define DMA_CH10_AL2_WRITE_ADDR_TRIG_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH10_AL3_CTRL -// Description : Alias for channel 10 CTRL register -#define DMA_CH10_AL3_CTRL_OFFSET _u(0x000002b0) -#define DMA_CH10_AL3_CTRL_BITS _u(0xffffffff) -#define DMA_CH10_AL3_CTRL_RESET "-" -#define DMA_CH10_AL3_CTRL_MSB _u(31) -#define DMA_CH10_AL3_CTRL_LSB _u(0) -#define DMA_CH10_AL3_CTRL_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH10_AL3_WRITE_ADDR -// Description : Alias for channel 10 WRITE_ADDR register -#define DMA_CH10_AL3_WRITE_ADDR_OFFSET _u(0x000002b4) -#define DMA_CH10_AL3_WRITE_ADDR_BITS _u(0xffffffff) -#define DMA_CH10_AL3_WRITE_ADDR_RESET "-" -#define DMA_CH10_AL3_WRITE_ADDR_MSB _u(31) -#define DMA_CH10_AL3_WRITE_ADDR_LSB _u(0) -#define DMA_CH10_AL3_WRITE_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH10_AL3_TRANS_COUNT -// Description : Alias for channel 10 TRANS_COUNT register -#define DMA_CH10_AL3_TRANS_COUNT_OFFSET _u(0x000002b8) -#define DMA_CH10_AL3_TRANS_COUNT_BITS _u(0xffffffff) -#define DMA_CH10_AL3_TRANS_COUNT_RESET "-" -#define DMA_CH10_AL3_TRANS_COUNT_MSB _u(31) -#define DMA_CH10_AL3_TRANS_COUNT_LSB _u(0) -#define DMA_CH10_AL3_TRANS_COUNT_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH10_AL3_READ_ADDR_TRIG -// Description : Alias for channel 10 READ_ADDR register -// This is a trigger register (0xc). Writing a nonzero value will -// reload the channel counter and start the channel. -#define DMA_CH10_AL3_READ_ADDR_TRIG_OFFSET _u(0x000002bc) -#define DMA_CH10_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff) -#define DMA_CH10_AL3_READ_ADDR_TRIG_RESET "-" -#define DMA_CH10_AL3_READ_ADDR_TRIG_MSB _u(31) -#define DMA_CH10_AL3_READ_ADDR_TRIG_LSB _u(0) -#define DMA_CH10_AL3_READ_ADDR_TRIG_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH11_READ_ADDR -// Description : DMA Channel 11 Read Address pointer -// This register updates automatically each time a read completes. -// The current value is the next address to be read by this -// channel. -#define DMA_CH11_READ_ADDR_OFFSET _u(0x000002c0) -#define DMA_CH11_READ_ADDR_BITS _u(0xffffffff) -#define DMA_CH11_READ_ADDR_RESET _u(0x00000000) -#define DMA_CH11_READ_ADDR_MSB _u(31) -#define DMA_CH11_READ_ADDR_LSB _u(0) -#define DMA_CH11_READ_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH11_WRITE_ADDR -// Description : DMA Channel 11 Write Address pointer -// This register updates automatically each time a write -// completes. The current value is the next address to be written -// by this channel. -#define DMA_CH11_WRITE_ADDR_OFFSET _u(0x000002c4) -#define DMA_CH11_WRITE_ADDR_BITS _u(0xffffffff) -#define DMA_CH11_WRITE_ADDR_RESET _u(0x00000000) -#define DMA_CH11_WRITE_ADDR_MSB _u(31) -#define DMA_CH11_WRITE_ADDR_LSB _u(0) -#define DMA_CH11_WRITE_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH11_TRANS_COUNT -// Description : DMA Channel 11 Transfer Count -// Program the number of bus transfers a channel will perform -// before halting. Note that, if transfers are larger than one -// byte in size, this is not equal to the number of bytes -// transferred (see CTRL_DATA_SIZE). -// -// When the channel is active, reading this register shows the -// number of transfers remaining, updating automatically each time -// a write transfer completes. -// -// Writing this register sets the RELOAD value for the transfer -// counter. Each time this channel is triggered, the RELOAD value -// is copied into the live transfer counter. The channel can be -// started multiple times, and will perform the same number of -// transfers each time, as programmed by most recent write. -// -// The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT -// is used as a trigger, the written value is used immediately as -// the length of the new transfer sequence, as well as being -// written to RELOAD. -#define DMA_CH11_TRANS_COUNT_OFFSET _u(0x000002c8) -#define DMA_CH11_TRANS_COUNT_BITS _u(0xffffffff) -#define DMA_CH11_TRANS_COUNT_RESET _u(0x00000000) -#define DMA_CH11_TRANS_COUNT_MSB _u(31) -#define DMA_CH11_TRANS_COUNT_LSB _u(0) -#define DMA_CH11_TRANS_COUNT_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH11_CTRL_TRIG -// Description : DMA Channel 11 Control and Status -#define DMA_CH11_CTRL_TRIG_OFFSET _u(0x000002cc) -#define DMA_CH11_CTRL_TRIG_BITS _u(0xe1ffffff) -#define DMA_CH11_CTRL_TRIG_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : DMA_CH11_CTRL_TRIG_AHB_ERROR -// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel -// halts when it encounters any bus error, and always raises its -// channel IRQ flag. -#define DMA_CH11_CTRL_TRIG_AHB_ERROR_RESET _u(0x0) -#define DMA_CH11_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000) -#define DMA_CH11_CTRL_TRIG_AHB_ERROR_MSB _u(31) -#define DMA_CH11_CTRL_TRIG_AHB_ERROR_LSB _u(31) -#define DMA_CH11_CTRL_TRIG_AHB_ERROR_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : DMA_CH11_CTRL_TRIG_READ_ERROR -// Description : If 1, the channel received a read bus error. Write one to -// clear. -// READ_ADDR shows the approximate address where the bus error was -// encountered (will not be earlier, or more than 3 transfers -// later) -#define DMA_CH11_CTRL_TRIG_READ_ERROR_RESET _u(0x0) -#define DMA_CH11_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000) -#define DMA_CH11_CTRL_TRIG_READ_ERROR_MSB _u(30) -#define DMA_CH11_CTRL_TRIG_READ_ERROR_LSB _u(30) -#define DMA_CH11_CTRL_TRIG_READ_ERROR_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : DMA_CH11_CTRL_TRIG_WRITE_ERROR -// Description : If 1, the channel received a write bus error. Write one to -// clear. -// WRITE_ADDR shows the approximate address where the bus error -// was encountered (will not be earlier, or more than 5 transfers -// later) -#define DMA_CH11_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0) -#define DMA_CH11_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000) -#define DMA_CH11_CTRL_TRIG_WRITE_ERROR_MSB _u(29) -#define DMA_CH11_CTRL_TRIG_WRITE_ERROR_LSB _u(29) -#define DMA_CH11_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : DMA_CH11_CTRL_TRIG_BUSY -// Description : This flag goes high when the channel starts a new transfer -// sequence, and low when the last transfer of that sequence -// completes. Clearing EN while BUSY is high pauses the channel, -// and BUSY will stay high while paused. -// -// To terminate a sequence early (and clear the BUSY flag), see -// CHAN_ABORT. -#define DMA_CH11_CTRL_TRIG_BUSY_RESET _u(0x0) -#define DMA_CH11_CTRL_TRIG_BUSY_BITS _u(0x01000000) -#define DMA_CH11_CTRL_TRIG_BUSY_MSB _u(24) -#define DMA_CH11_CTRL_TRIG_BUSY_LSB _u(24) -#define DMA_CH11_CTRL_TRIG_BUSY_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : DMA_CH11_CTRL_TRIG_SNIFF_EN -// Description : If 1, this channel's data transfers are visible to the sniff -// hardware, and each transfer will advance the state of the -// checksum. This only applies if the sniff hardware is enabled, -// and has this channel selected. -// -// This allows checksum to be enabled or disabled on a per- -// control- block basis. -#define DMA_CH11_CTRL_TRIG_SNIFF_EN_RESET _u(0x0) -#define DMA_CH11_CTRL_TRIG_SNIFF_EN_BITS _u(0x00800000) -#define DMA_CH11_CTRL_TRIG_SNIFF_EN_MSB _u(23) -#define DMA_CH11_CTRL_TRIG_SNIFF_EN_LSB _u(23) -#define DMA_CH11_CTRL_TRIG_SNIFF_EN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH11_CTRL_TRIG_BSWAP -// Description : Apply byte-swap transformation to DMA data. -// For byte data, this has no effect. For halfword data, the two -// bytes of each halfword are swapped. For word data, the four -// bytes of each word are swapped to reverse order. -#define DMA_CH11_CTRL_TRIG_BSWAP_RESET _u(0x0) -#define DMA_CH11_CTRL_TRIG_BSWAP_BITS _u(0x00400000) -#define DMA_CH11_CTRL_TRIG_BSWAP_MSB _u(22) -#define DMA_CH11_CTRL_TRIG_BSWAP_LSB _u(22) -#define DMA_CH11_CTRL_TRIG_BSWAP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH11_CTRL_TRIG_IRQ_QUIET -// Description : In QUIET mode, the channel does not generate IRQs at the end of -// every transfer block. Instead, an IRQ is raised when NULL is -// written to a trigger register, indicating the end of a control -// block chain. -// -// This reduces the number of interrupts to be serviced by the CPU -// when transferring a DMA chain of many small control blocks. -#define DMA_CH11_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0) -#define DMA_CH11_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00200000) -#define DMA_CH11_CTRL_TRIG_IRQ_QUIET_MSB _u(21) -#define DMA_CH11_CTRL_TRIG_IRQ_QUIET_LSB _u(21) -#define DMA_CH11_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH11_CTRL_TRIG_TREQ_SEL -// Description : Select a Transfer Request signal. -// The channel uses the transfer request signal to pace its data -// transfer rate. Sources for TREQ signals are internal (TIMERS) -// or external (DREQ, a Data Request from the system). -// 0x0 to 0x3a -> select DREQ n as TREQ -// 0x3b -> Select Timer 0 as TREQ -// 0x3c -> Select Timer 1 as TREQ -// 0x3d -> Select Timer 2 as TREQ (Optional) -// 0x3e -> Select Timer 3 as TREQ (Optional) -// 0x3f -> Permanent request, for unpaced transfers. -#define DMA_CH11_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) -#define DMA_CH11_CTRL_TRIG_TREQ_SEL_BITS _u(0x001f8000) -#define DMA_CH11_CTRL_TRIG_TREQ_SEL_MSB _u(20) -#define DMA_CH11_CTRL_TRIG_TREQ_SEL_LSB _u(15) -#define DMA_CH11_CTRL_TRIG_TREQ_SEL_ACCESS "RW" -#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) -#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) -#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) -#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) -#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) -// ----------------------------------------------------------------------------- -// Field : DMA_CH11_CTRL_TRIG_CHAIN_TO -// Description : When this channel completes, it will trigger the channel -// indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this -// channel)_. -#define DMA_CH11_CTRL_TRIG_CHAIN_TO_RESET _u(0x0) -#define DMA_CH11_CTRL_TRIG_CHAIN_TO_BITS _u(0x00007800) -#define DMA_CH11_CTRL_TRIG_CHAIN_TO_MSB _u(14) -#define DMA_CH11_CTRL_TRIG_CHAIN_TO_LSB _u(11) -#define DMA_CH11_CTRL_TRIG_CHAIN_TO_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH11_CTRL_TRIG_RING_SEL -// Description : Select whether RING_SIZE applies to read or write addresses. -// If 0, read addresses are wrapped on a (1 << RING_SIZE) -// boundary. If 1, write addresses are wrapped. -#define DMA_CH11_CTRL_TRIG_RING_SEL_RESET _u(0x0) -#define DMA_CH11_CTRL_TRIG_RING_SEL_BITS _u(0x00000400) -#define DMA_CH11_CTRL_TRIG_RING_SEL_MSB _u(10) -#define DMA_CH11_CTRL_TRIG_RING_SEL_LSB _u(10) -#define DMA_CH11_CTRL_TRIG_RING_SEL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH11_CTRL_TRIG_RING_SIZE -// Description : Size of address wrap region. If 0, don't wrap. For values n > -// 0, only the lower n bits of the address will change. This wraps -// the address on a (1 << n) byte boundary, facilitating access to -// naturally-aligned ring buffers. -// -// Ring sizes between 2 and 32768 bytes are possible. This can -// apply to either read or write addresses, based on value of -// RING_SEL. -// 0x0 -> RING_NONE -#define DMA_CH11_CTRL_TRIG_RING_SIZE_RESET _u(0x0) -#define DMA_CH11_CTRL_TRIG_RING_SIZE_BITS _u(0x000003c0) -#define DMA_CH11_CTRL_TRIG_RING_SIZE_MSB _u(9) -#define DMA_CH11_CTRL_TRIG_RING_SIZE_LSB _u(6) -#define DMA_CH11_CTRL_TRIG_RING_SIZE_ACCESS "RW" -#define DMA_CH11_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0) -// ----------------------------------------------------------------------------- -// Field : DMA_CH11_CTRL_TRIG_INCR_WRITE -// Description : If 1, the write address increments with each transfer. If 0, -// each write is directed to the same, initial address. -// -// Generally this should be disabled for memory-to-peripheral -// transfers. -#define DMA_CH11_CTRL_TRIG_INCR_WRITE_RESET _u(0x0) -#define DMA_CH11_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000020) -#define DMA_CH11_CTRL_TRIG_INCR_WRITE_MSB _u(5) -#define DMA_CH11_CTRL_TRIG_INCR_WRITE_LSB _u(5) -#define DMA_CH11_CTRL_TRIG_INCR_WRITE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH11_CTRL_TRIG_INCR_READ -// Description : If 1, the read address increments with each transfer. If 0, -// each read is directed to the same, initial address. -// -// Generally this should be disabled for peripheral-to-memory -// transfers. -#define DMA_CH11_CTRL_TRIG_INCR_READ_RESET _u(0x0) -#define DMA_CH11_CTRL_TRIG_INCR_READ_BITS _u(0x00000010) -#define DMA_CH11_CTRL_TRIG_INCR_READ_MSB _u(4) -#define DMA_CH11_CTRL_TRIG_INCR_READ_LSB _u(4) -#define DMA_CH11_CTRL_TRIG_INCR_READ_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH11_CTRL_TRIG_DATA_SIZE -// Description : Set the size of each bus transfer (byte/halfword/word). -// READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) -// with each transfer. -// 0x0 -> SIZE_BYTE -// 0x1 -> SIZE_HALFWORD -// 0x2 -> SIZE_WORD -#define DMA_CH11_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) -#define DMA_CH11_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) -#define DMA_CH11_CTRL_TRIG_DATA_SIZE_MSB _u(3) -#define DMA_CH11_CTRL_TRIG_DATA_SIZE_LSB _u(2) -#define DMA_CH11_CTRL_TRIG_DATA_SIZE_ACCESS "RW" -#define DMA_CH11_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) -#define DMA_CH11_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1) -#define DMA_CH11_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) -// ----------------------------------------------------------------------------- -// Field : DMA_CH11_CTRL_TRIG_HIGH_PRIORITY -// Description : HIGH_PRIORITY gives a channel preferential treatment in issue -// scheduling: in each scheduling round, all high priority -// channels are considered first, and then only a single low -// priority channel, before returning to the high priority -// channels. -// -// This only affects the order in which the DMA schedules -// channels. The DMA's bus priority is not changed. If the DMA is -// not saturated then a low priority channel will see no loss of -// throughput. -#define DMA_CH11_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0) -#define DMA_CH11_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002) -#define DMA_CH11_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1) -#define DMA_CH11_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1) -#define DMA_CH11_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH11_CTRL_TRIG_EN -// Description : DMA Channel Enable. -// When 1, the channel will respond to triggering events, which -// will cause it to become BUSY and start transferring data. When -// 0, the channel will ignore triggers, stop issuing transfers, -// and pause the current transfer sequence (i.e. BUSY will remain -// high if already high) -#define DMA_CH11_CTRL_TRIG_EN_RESET _u(0x0) -#define DMA_CH11_CTRL_TRIG_EN_BITS _u(0x00000001) -#define DMA_CH11_CTRL_TRIG_EN_MSB _u(0) -#define DMA_CH11_CTRL_TRIG_EN_LSB _u(0) -#define DMA_CH11_CTRL_TRIG_EN_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH11_AL1_CTRL -// Description : Alias for channel 11 CTRL register -#define DMA_CH11_AL1_CTRL_OFFSET _u(0x000002d0) -#define DMA_CH11_AL1_CTRL_BITS _u(0xffffffff) -#define DMA_CH11_AL1_CTRL_RESET "-" -#define DMA_CH11_AL1_CTRL_MSB _u(31) -#define DMA_CH11_AL1_CTRL_LSB _u(0) -#define DMA_CH11_AL1_CTRL_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH11_AL1_READ_ADDR -// Description : Alias for channel 11 READ_ADDR register -#define DMA_CH11_AL1_READ_ADDR_OFFSET _u(0x000002d4) -#define DMA_CH11_AL1_READ_ADDR_BITS _u(0xffffffff) -#define DMA_CH11_AL1_READ_ADDR_RESET "-" -#define DMA_CH11_AL1_READ_ADDR_MSB _u(31) -#define DMA_CH11_AL1_READ_ADDR_LSB _u(0) -#define DMA_CH11_AL1_READ_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH11_AL1_WRITE_ADDR -// Description : Alias for channel 11 WRITE_ADDR register -#define DMA_CH11_AL1_WRITE_ADDR_OFFSET _u(0x000002d8) -#define DMA_CH11_AL1_WRITE_ADDR_BITS _u(0xffffffff) -#define DMA_CH11_AL1_WRITE_ADDR_RESET "-" -#define DMA_CH11_AL1_WRITE_ADDR_MSB _u(31) -#define DMA_CH11_AL1_WRITE_ADDR_LSB _u(0) -#define DMA_CH11_AL1_WRITE_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH11_AL1_TRANS_COUNT_TRIG -// Description : Alias for channel 11 TRANS_COUNT register -// This is a trigger register (0xc). Writing a nonzero value will -// reload the channel counter and start the channel. -#define DMA_CH11_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x000002dc) -#define DMA_CH11_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff) -#define DMA_CH11_AL1_TRANS_COUNT_TRIG_RESET "-" -#define DMA_CH11_AL1_TRANS_COUNT_TRIG_MSB _u(31) -#define DMA_CH11_AL1_TRANS_COUNT_TRIG_LSB _u(0) -#define DMA_CH11_AL1_TRANS_COUNT_TRIG_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH11_AL2_CTRL -// Description : Alias for channel 11 CTRL register -#define DMA_CH11_AL2_CTRL_OFFSET _u(0x000002e0) -#define DMA_CH11_AL2_CTRL_BITS _u(0xffffffff) -#define DMA_CH11_AL2_CTRL_RESET "-" -#define DMA_CH11_AL2_CTRL_MSB _u(31) -#define DMA_CH11_AL2_CTRL_LSB _u(0) -#define DMA_CH11_AL2_CTRL_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH11_AL2_TRANS_COUNT -// Description : Alias for channel 11 TRANS_COUNT register -#define DMA_CH11_AL2_TRANS_COUNT_OFFSET _u(0x000002e4) -#define DMA_CH11_AL2_TRANS_COUNT_BITS _u(0xffffffff) -#define DMA_CH11_AL2_TRANS_COUNT_RESET "-" -#define DMA_CH11_AL2_TRANS_COUNT_MSB _u(31) -#define DMA_CH11_AL2_TRANS_COUNT_LSB _u(0) -#define DMA_CH11_AL2_TRANS_COUNT_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH11_AL2_READ_ADDR -// Description : Alias for channel 11 READ_ADDR register -#define DMA_CH11_AL2_READ_ADDR_OFFSET _u(0x000002e8) -#define DMA_CH11_AL2_READ_ADDR_BITS _u(0xffffffff) -#define DMA_CH11_AL2_READ_ADDR_RESET "-" -#define DMA_CH11_AL2_READ_ADDR_MSB _u(31) -#define DMA_CH11_AL2_READ_ADDR_LSB _u(0) -#define DMA_CH11_AL2_READ_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH11_AL2_WRITE_ADDR_TRIG -// Description : Alias for channel 11 WRITE_ADDR register -// This is a trigger register (0xc). Writing a nonzero value will -// reload the channel counter and start the channel. -#define DMA_CH11_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x000002ec) -#define DMA_CH11_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff) -#define DMA_CH11_AL2_WRITE_ADDR_TRIG_RESET "-" -#define DMA_CH11_AL2_WRITE_ADDR_TRIG_MSB _u(31) -#define DMA_CH11_AL2_WRITE_ADDR_TRIG_LSB _u(0) -#define DMA_CH11_AL2_WRITE_ADDR_TRIG_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH11_AL3_CTRL -// Description : Alias for channel 11 CTRL register -#define DMA_CH11_AL3_CTRL_OFFSET _u(0x000002f0) -#define DMA_CH11_AL3_CTRL_BITS _u(0xffffffff) -#define DMA_CH11_AL3_CTRL_RESET "-" -#define DMA_CH11_AL3_CTRL_MSB _u(31) -#define DMA_CH11_AL3_CTRL_LSB _u(0) -#define DMA_CH11_AL3_CTRL_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH11_AL3_WRITE_ADDR -// Description : Alias for channel 11 WRITE_ADDR register -#define DMA_CH11_AL3_WRITE_ADDR_OFFSET _u(0x000002f4) -#define DMA_CH11_AL3_WRITE_ADDR_BITS _u(0xffffffff) -#define DMA_CH11_AL3_WRITE_ADDR_RESET "-" -#define DMA_CH11_AL3_WRITE_ADDR_MSB _u(31) -#define DMA_CH11_AL3_WRITE_ADDR_LSB _u(0) -#define DMA_CH11_AL3_WRITE_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH11_AL3_TRANS_COUNT -// Description : Alias for channel 11 TRANS_COUNT register -#define DMA_CH11_AL3_TRANS_COUNT_OFFSET _u(0x000002f8) -#define DMA_CH11_AL3_TRANS_COUNT_BITS _u(0xffffffff) -#define DMA_CH11_AL3_TRANS_COUNT_RESET "-" -#define DMA_CH11_AL3_TRANS_COUNT_MSB _u(31) -#define DMA_CH11_AL3_TRANS_COUNT_LSB _u(0) -#define DMA_CH11_AL3_TRANS_COUNT_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH11_AL3_READ_ADDR_TRIG -// Description : Alias for channel 11 READ_ADDR register -// This is a trigger register (0xc). Writing a nonzero value will -// reload the channel counter and start the channel. -#define DMA_CH11_AL3_READ_ADDR_TRIG_OFFSET _u(0x000002fc) -#define DMA_CH11_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff) -#define DMA_CH11_AL3_READ_ADDR_TRIG_RESET "-" -#define DMA_CH11_AL3_READ_ADDR_TRIG_MSB _u(31) -#define DMA_CH11_AL3_READ_ADDR_TRIG_LSB _u(0) -#define DMA_CH11_AL3_READ_ADDR_TRIG_ACCESS "RW" -// ============================================================================= -// Register : DMA_INTR -// Description : Interrupt Status (raw) -// Raw interrupt status for DMA Channels 0..15. Bit n corresponds -// to channel n. Ignores any masking or forcing. Channel -// interrupts can be cleared by writing a bit mask to INTR, INTS0 -// or INTS1. -// -// Channel interrupts can be routed to either of two system-level -// IRQs based on INTE0 and INTE1. -// -// This can be used vector different channel interrupts to -// different ISRs: this might be done to allow NVIC IRQ preemption -// for more time-critical channels, or to spread IRQ load across -// different cores. -// -// It is also valid to ignore this behaviour and just use -// INTE0/INTS0/IRQ 0. -#define DMA_INTR_OFFSET _u(0x00000400) -#define DMA_INTR_BITS _u(0x0000ffff) -#define DMA_INTR_RESET _u(0x00000000) -#define DMA_INTR_MSB _u(15) -#define DMA_INTR_LSB _u(0) -#define DMA_INTR_ACCESS "WC" -// ============================================================================= -// Register : DMA_INTE0 -// Description : Interrupt Enables for IRQ 0 -// Set bit n to pass interrupts from channel n to DMA IRQ 0. -#define DMA_INTE0_OFFSET _u(0x00000404) -#define DMA_INTE0_BITS _u(0x0000ffff) -#define DMA_INTE0_RESET _u(0x00000000) -#define DMA_INTE0_MSB _u(15) -#define DMA_INTE0_LSB _u(0) -#define DMA_INTE0_ACCESS "RW" -// ============================================================================= -// Register : DMA_INTF0 -// Description : Force Interrupts -// Write 1s to force the corresponding bits in INTE0. The -// interrupt remains asserted until INTF0 is cleared. -#define DMA_INTF0_OFFSET _u(0x00000408) -#define DMA_INTF0_BITS _u(0x0000ffff) -#define DMA_INTF0_RESET _u(0x00000000) -#define DMA_INTF0_MSB _u(15) -#define DMA_INTF0_LSB _u(0) -#define DMA_INTF0_ACCESS "RW" -// ============================================================================= -// Register : DMA_INTS0 -// Description : Interrupt Status for IRQ 0 -// Indicates active channel interrupt requests which are currently -// causing IRQ 0 to be asserted. -// Channel interrupts can be cleared by writing a bit mask here. -#define DMA_INTS0_OFFSET _u(0x0000040c) -#define DMA_INTS0_BITS _u(0x0000ffff) -#define DMA_INTS0_RESET _u(0x00000000) -#define DMA_INTS0_MSB _u(15) -#define DMA_INTS0_LSB _u(0) -#define DMA_INTS0_ACCESS "WC" -// ============================================================================= -// Register : DMA_INTE1 -// Description : Interrupt Enables for IRQ 1 -// Set bit n to pass interrupts from channel n to DMA IRQ 1. -#define DMA_INTE1_OFFSET _u(0x00000414) -#define DMA_INTE1_BITS _u(0x0000ffff) -#define DMA_INTE1_RESET _u(0x00000000) -#define DMA_INTE1_MSB _u(15) -#define DMA_INTE1_LSB _u(0) -#define DMA_INTE1_ACCESS "RW" -// ============================================================================= -// Register : DMA_INTF1 -// Description : Force Interrupts for IRQ 1 -// Write 1s to force the corresponding bits in INTE0. The -// interrupt remains asserted until INTF0 is cleared. -#define DMA_INTF1_OFFSET _u(0x00000418) -#define DMA_INTF1_BITS _u(0x0000ffff) -#define DMA_INTF1_RESET _u(0x00000000) -#define DMA_INTF1_MSB _u(15) -#define DMA_INTF1_LSB _u(0) -#define DMA_INTF1_ACCESS "RW" -// ============================================================================= -// Register : DMA_INTS1 -// Description : Interrupt Status (masked) for IRQ 1 -// Indicates active channel interrupt requests which are currently -// causing IRQ 1 to be asserted. -// Channel interrupts can be cleared by writing a bit mask here. -#define DMA_INTS1_OFFSET _u(0x0000041c) -#define DMA_INTS1_BITS _u(0x0000ffff) -#define DMA_INTS1_RESET _u(0x00000000) -#define DMA_INTS1_MSB _u(15) -#define DMA_INTS1_LSB _u(0) -#define DMA_INTS1_ACCESS "WC" -// ============================================================================= -// Register : DMA_TIMER0 -// Description : Pacing (X/Y) Fractional Timer -// The pacing timer produces TREQ assertions at a rate set by -// ((X/Y) * sys_clk). This equation is evaluated every sys_clk -// cycles and therefore can only generate TREQs at a rate of 1 per -// sys_clk (i.e. permanent TREQ) or less. -#define DMA_TIMER0_OFFSET _u(0x00000420) -#define DMA_TIMER0_BITS _u(0xffffffff) -#define DMA_TIMER0_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : DMA_TIMER0_X -// Description : Pacing Timer Dividend. Specifies the X value for the (X/Y) -// fractional timer. -#define DMA_TIMER0_X_RESET _u(0x0000) -#define DMA_TIMER0_X_BITS _u(0xffff0000) -#define DMA_TIMER0_X_MSB _u(31) -#define DMA_TIMER0_X_LSB _u(16) -#define DMA_TIMER0_X_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_TIMER0_Y -// Description : Pacing Timer Divisor. Specifies the Y value for the (X/Y) -// fractional timer. -#define DMA_TIMER0_Y_RESET _u(0x0000) -#define DMA_TIMER0_Y_BITS _u(0x0000ffff) -#define DMA_TIMER0_Y_MSB _u(15) -#define DMA_TIMER0_Y_LSB _u(0) -#define DMA_TIMER0_Y_ACCESS "RW" -// ============================================================================= -// Register : DMA_TIMER1 -// Description : Pacing (X/Y) Fractional Timer -// The pacing timer produces TREQ assertions at a rate set by -// ((X/Y) * sys_clk). This equation is evaluated every sys_clk -// cycles and therefore can only generate TREQs at a rate of 1 per -// sys_clk (i.e. permanent TREQ) or less. -#define DMA_TIMER1_OFFSET _u(0x00000424) -#define DMA_TIMER1_BITS _u(0xffffffff) -#define DMA_TIMER1_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : DMA_TIMER1_X -// Description : Pacing Timer Dividend. Specifies the X value for the (X/Y) -// fractional timer. -#define DMA_TIMER1_X_RESET _u(0x0000) -#define DMA_TIMER1_X_BITS _u(0xffff0000) -#define DMA_TIMER1_X_MSB _u(31) -#define DMA_TIMER1_X_LSB _u(16) -#define DMA_TIMER1_X_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_TIMER1_Y -// Description : Pacing Timer Divisor. Specifies the Y value for the (X/Y) -// fractional timer. -#define DMA_TIMER1_Y_RESET _u(0x0000) -#define DMA_TIMER1_Y_BITS _u(0x0000ffff) -#define DMA_TIMER1_Y_MSB _u(15) -#define DMA_TIMER1_Y_LSB _u(0) -#define DMA_TIMER1_Y_ACCESS "RW" -// ============================================================================= -// Register : DMA_TIMER2 -// Description : Pacing (X/Y) Fractional Timer -// The pacing timer produces TREQ assertions at a rate set by -// ((X/Y) * sys_clk). This equation is evaluated every sys_clk -// cycles and therefore can only generate TREQs at a rate of 1 per -// sys_clk (i.e. permanent TREQ) or less. -#define DMA_TIMER2_OFFSET _u(0x00000428) -#define DMA_TIMER2_BITS _u(0xffffffff) -#define DMA_TIMER2_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : DMA_TIMER2_X -// Description : Pacing Timer Dividend. Specifies the X value for the (X/Y) -// fractional timer. -#define DMA_TIMER2_X_RESET _u(0x0000) -#define DMA_TIMER2_X_BITS _u(0xffff0000) -#define DMA_TIMER2_X_MSB _u(31) -#define DMA_TIMER2_X_LSB _u(16) -#define DMA_TIMER2_X_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_TIMER2_Y -// Description : Pacing Timer Divisor. Specifies the Y value for the (X/Y) -// fractional timer. -#define DMA_TIMER2_Y_RESET _u(0x0000) -#define DMA_TIMER2_Y_BITS _u(0x0000ffff) -#define DMA_TIMER2_Y_MSB _u(15) -#define DMA_TIMER2_Y_LSB _u(0) -#define DMA_TIMER2_Y_ACCESS "RW" -// ============================================================================= -// Register : DMA_TIMER3 -// Description : Pacing (X/Y) Fractional Timer -// The pacing timer produces TREQ assertions at a rate set by -// ((X/Y) * sys_clk). This equation is evaluated every sys_clk -// cycles and therefore can only generate TREQs at a rate of 1 per -// sys_clk (i.e. permanent TREQ) or less. -#define DMA_TIMER3_OFFSET _u(0x0000042c) -#define DMA_TIMER3_BITS _u(0xffffffff) -#define DMA_TIMER3_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : DMA_TIMER3_X -// Description : Pacing Timer Dividend. Specifies the X value for the (X/Y) -// fractional timer. -#define DMA_TIMER3_X_RESET _u(0x0000) -#define DMA_TIMER3_X_BITS _u(0xffff0000) -#define DMA_TIMER3_X_MSB _u(31) -#define DMA_TIMER3_X_LSB _u(16) -#define DMA_TIMER3_X_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_TIMER3_Y -// Description : Pacing Timer Divisor. Specifies the Y value for the (X/Y) -// fractional timer. -#define DMA_TIMER3_Y_RESET _u(0x0000) -#define DMA_TIMER3_Y_BITS _u(0x0000ffff) -#define DMA_TIMER3_Y_MSB _u(15) -#define DMA_TIMER3_Y_LSB _u(0) -#define DMA_TIMER3_Y_ACCESS "RW" -// ============================================================================= -// Register : DMA_MULTI_CHAN_TRIGGER -// Description : Trigger one or more channels simultaneously -// Each bit in this register corresponds to a DMA channel. Writing -// a 1 to the relevant bit is the same as writing to that -// channel's trigger register; the channel will start if it is -// currently enabled and not already busy. -#define DMA_MULTI_CHAN_TRIGGER_OFFSET _u(0x00000430) -#define DMA_MULTI_CHAN_TRIGGER_BITS _u(0x0000ffff) -#define DMA_MULTI_CHAN_TRIGGER_RESET _u(0x00000000) -#define DMA_MULTI_CHAN_TRIGGER_MSB _u(15) -#define DMA_MULTI_CHAN_TRIGGER_LSB _u(0) -#define DMA_MULTI_CHAN_TRIGGER_ACCESS "SC" -// ============================================================================= -// Register : DMA_SNIFF_CTRL -// Description : Sniffer Control -#define DMA_SNIFF_CTRL_OFFSET _u(0x00000434) -#define DMA_SNIFF_CTRL_BITS _u(0x00000fff) -#define DMA_SNIFF_CTRL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : DMA_SNIFF_CTRL_OUT_INV -// Description : If set, the result appears inverted (bitwise complement) when -// read. This does not affect the way the checksum is calculated; -// the result is transformed on-the-fly between the result -// register and the bus. -#define DMA_SNIFF_CTRL_OUT_INV_RESET _u(0x0) -#define DMA_SNIFF_CTRL_OUT_INV_BITS _u(0x00000800) -#define DMA_SNIFF_CTRL_OUT_INV_MSB _u(11) -#define DMA_SNIFF_CTRL_OUT_INV_LSB _u(11) -#define DMA_SNIFF_CTRL_OUT_INV_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_SNIFF_CTRL_OUT_REV -// Description : If set, the result appears bit-reversed when read. This does -// not affect the way the checksum is calculated; the result is -// transformed on-the-fly between the result register and the bus. -#define DMA_SNIFF_CTRL_OUT_REV_RESET _u(0x0) -#define DMA_SNIFF_CTRL_OUT_REV_BITS _u(0x00000400) -#define DMA_SNIFF_CTRL_OUT_REV_MSB _u(10) -#define DMA_SNIFF_CTRL_OUT_REV_LSB _u(10) -#define DMA_SNIFF_CTRL_OUT_REV_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_SNIFF_CTRL_BSWAP -// Description : Locally perform a byte reverse on the sniffed data, before -// feeding into checksum. -// -// Note that the sniff hardware is downstream of the DMA channel -// byteswap performed in the read master: if channel CTRL_BSWAP -// and SNIFF_CTRL_BSWAP are both enabled, their effects cancel -// from the sniffer's point of view. -#define DMA_SNIFF_CTRL_BSWAP_RESET _u(0x0) -#define DMA_SNIFF_CTRL_BSWAP_BITS _u(0x00000200) -#define DMA_SNIFF_CTRL_BSWAP_MSB _u(9) -#define DMA_SNIFF_CTRL_BSWAP_LSB _u(9) -#define DMA_SNIFF_CTRL_BSWAP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_SNIFF_CTRL_CALC -// 0x0 -> Calculate a CRC-32 (IEEE802.3 polynomial) -// 0x1 -> Calculate a CRC-32 (IEEE802.3 polynomial) with bit reversed data -// 0x2 -> Calculate a CRC-16-CCITT -// 0x3 -> Calculate a CRC-16-CCITT with bit reversed data -// 0xe -> XOR reduction over all data. == 1 if the total 1 population count is odd. -// 0xf -> Calculate a simple 32-bit checksum (addition with a 32 bit accumulator) -#define DMA_SNIFF_CTRL_CALC_RESET _u(0x0) -#define DMA_SNIFF_CTRL_CALC_BITS _u(0x000001e0) -#define DMA_SNIFF_CTRL_CALC_MSB _u(8) -#define DMA_SNIFF_CTRL_CALC_LSB _u(5) -#define DMA_SNIFF_CTRL_CALC_ACCESS "RW" -#define DMA_SNIFF_CTRL_CALC_VALUE_CRC32 _u(0x0) -#define DMA_SNIFF_CTRL_CALC_VALUE_CRC32R _u(0x1) -#define DMA_SNIFF_CTRL_CALC_VALUE_CRC16 _u(0x2) -#define DMA_SNIFF_CTRL_CALC_VALUE_CRC16R _u(0x3) -#define DMA_SNIFF_CTRL_CALC_VALUE_EVEN _u(0xe) -#define DMA_SNIFF_CTRL_CALC_VALUE_SUM _u(0xf) -// ----------------------------------------------------------------------------- -// Field : DMA_SNIFF_CTRL_DMACH -// Description : DMA channel for Sniffer to observe -#define DMA_SNIFF_CTRL_DMACH_RESET _u(0x0) -#define DMA_SNIFF_CTRL_DMACH_BITS _u(0x0000001e) -#define DMA_SNIFF_CTRL_DMACH_MSB _u(4) -#define DMA_SNIFF_CTRL_DMACH_LSB _u(1) -#define DMA_SNIFF_CTRL_DMACH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_SNIFF_CTRL_EN -// Description : Enable sniffer -#define DMA_SNIFF_CTRL_EN_RESET _u(0x0) -#define DMA_SNIFF_CTRL_EN_BITS _u(0x00000001) -#define DMA_SNIFF_CTRL_EN_MSB _u(0) -#define DMA_SNIFF_CTRL_EN_LSB _u(0) -#define DMA_SNIFF_CTRL_EN_ACCESS "RW" -// ============================================================================= -// Register : DMA_SNIFF_DATA -// Description : Data accumulator for sniff hardware -// Write an initial seed value here before starting a DMA transfer -// on the channel indicated by SNIFF_CTRL_DMACH. The hardware will -// update this register each time it observes a read from the -// indicated channel. Once the channel completes, the final result -// can be read from this register. -#define DMA_SNIFF_DATA_OFFSET _u(0x00000438) -#define DMA_SNIFF_DATA_BITS _u(0xffffffff) -#define DMA_SNIFF_DATA_RESET _u(0x00000000) -#define DMA_SNIFF_DATA_MSB _u(31) -#define DMA_SNIFF_DATA_LSB _u(0) -#define DMA_SNIFF_DATA_ACCESS "RW" -// ============================================================================= -// Register : DMA_FIFO_LEVELS -// Description : Debug RAF, WAF, TDF levels -#define DMA_FIFO_LEVELS_OFFSET _u(0x00000440) -#define DMA_FIFO_LEVELS_BITS _u(0x00ffffff) -#define DMA_FIFO_LEVELS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : DMA_FIFO_LEVELS_RAF_LVL -// Description : Current Read-Address-FIFO fill level -#define DMA_FIFO_LEVELS_RAF_LVL_RESET _u(0x00) -#define DMA_FIFO_LEVELS_RAF_LVL_BITS _u(0x00ff0000) -#define DMA_FIFO_LEVELS_RAF_LVL_MSB _u(23) -#define DMA_FIFO_LEVELS_RAF_LVL_LSB _u(16) -#define DMA_FIFO_LEVELS_RAF_LVL_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : DMA_FIFO_LEVELS_WAF_LVL -// Description : Current Write-Address-FIFO fill level -#define DMA_FIFO_LEVELS_WAF_LVL_RESET _u(0x00) -#define DMA_FIFO_LEVELS_WAF_LVL_BITS _u(0x0000ff00) -#define DMA_FIFO_LEVELS_WAF_LVL_MSB _u(15) -#define DMA_FIFO_LEVELS_WAF_LVL_LSB _u(8) -#define DMA_FIFO_LEVELS_WAF_LVL_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : DMA_FIFO_LEVELS_TDF_LVL -// Description : Current Transfer-Data-FIFO fill level -#define DMA_FIFO_LEVELS_TDF_LVL_RESET _u(0x00) -#define DMA_FIFO_LEVELS_TDF_LVL_BITS _u(0x000000ff) -#define DMA_FIFO_LEVELS_TDF_LVL_MSB _u(7) -#define DMA_FIFO_LEVELS_TDF_LVL_LSB _u(0) -#define DMA_FIFO_LEVELS_TDF_LVL_ACCESS "RO" -// ============================================================================= -// Register : DMA_CHAN_ABORT -// Description : Abort an in-progress transfer sequence on one or more channels -// Each bit corresponds to a channel. Writing a 1 aborts whatever -// transfer sequence is in progress on that channel. The bit will -// remain high until any in-flight transfers have been flushed -// through the address and data FIFOs. -// -// After writing, this register must be polled until it returns -// all-zero. Until this point, it is unsafe to restart the -// channel. -#define DMA_CHAN_ABORT_OFFSET _u(0x00000444) -#define DMA_CHAN_ABORT_BITS _u(0x0000ffff) -#define DMA_CHAN_ABORT_RESET _u(0x00000000) -#define DMA_CHAN_ABORT_MSB _u(15) -#define DMA_CHAN_ABORT_LSB _u(0) -#define DMA_CHAN_ABORT_ACCESS "SC" -// ============================================================================= -// Register : DMA_N_CHANNELS -// Description : The number of channels this DMA instance is equipped with. This -// DMA supports up to 16 hardware channels, but can be configured -// with as few as one, to minimise silicon area. -#define DMA_N_CHANNELS_OFFSET _u(0x00000448) -#define DMA_N_CHANNELS_BITS _u(0x0000001f) -#define DMA_N_CHANNELS_RESET "-" -#define DMA_N_CHANNELS_MSB _u(4) -#define DMA_N_CHANNELS_LSB _u(0) -#define DMA_N_CHANNELS_ACCESS "RO" -// ============================================================================= -// Register : DMA_CH0_DBG_CTDREQ -// Description : Read: get channel DREQ counter (i.e. how many accesses the DMA -// expects it can perform on the peripheral without -// overflow/underflow. Write any value: clears the counter, and -// cause channel to re-initiate DREQ handshake. -#define DMA_CH0_DBG_CTDREQ_OFFSET _u(0x00000800) -#define DMA_CH0_DBG_CTDREQ_BITS _u(0x0000003f) -#define DMA_CH0_DBG_CTDREQ_RESET _u(0x00000000) -#define DMA_CH0_DBG_CTDREQ_MSB _u(5) -#define DMA_CH0_DBG_CTDREQ_LSB _u(0) -#define DMA_CH0_DBG_CTDREQ_ACCESS "WC" -// ============================================================================= -// Register : DMA_CH0_DBG_TCR -// Description : Read to get channel TRANS_COUNT reload value, i.e. the length -// of the next transfer -#define DMA_CH0_DBG_TCR_OFFSET _u(0x00000804) -#define DMA_CH0_DBG_TCR_BITS _u(0xffffffff) -#define DMA_CH0_DBG_TCR_RESET _u(0x00000000) -#define DMA_CH0_DBG_TCR_MSB _u(31) -#define DMA_CH0_DBG_TCR_LSB _u(0) -#define DMA_CH0_DBG_TCR_ACCESS "RO" -// ============================================================================= -// Register : DMA_CH1_DBG_CTDREQ -// Description : Read: get channel DREQ counter (i.e. how many accesses the DMA -// expects it can perform on the peripheral without -// overflow/underflow. Write any value: clears the counter, and -// cause channel to re-initiate DREQ handshake. -#define DMA_CH1_DBG_CTDREQ_OFFSET _u(0x00000840) -#define DMA_CH1_DBG_CTDREQ_BITS _u(0x0000003f) -#define DMA_CH1_DBG_CTDREQ_RESET _u(0x00000000) -#define DMA_CH1_DBG_CTDREQ_MSB _u(5) -#define DMA_CH1_DBG_CTDREQ_LSB _u(0) -#define DMA_CH1_DBG_CTDREQ_ACCESS "WC" -// ============================================================================= -// Register : DMA_CH1_DBG_TCR -// Description : Read to get channel TRANS_COUNT reload value, i.e. the length -// of the next transfer -#define DMA_CH1_DBG_TCR_OFFSET _u(0x00000844) -#define DMA_CH1_DBG_TCR_BITS _u(0xffffffff) -#define DMA_CH1_DBG_TCR_RESET _u(0x00000000) -#define DMA_CH1_DBG_TCR_MSB _u(31) -#define DMA_CH1_DBG_TCR_LSB _u(0) -#define DMA_CH1_DBG_TCR_ACCESS "RO" -// ============================================================================= -// Register : DMA_CH2_DBG_CTDREQ -// Description : Read: get channel DREQ counter (i.e. how many accesses the DMA -// expects it can perform on the peripheral without -// overflow/underflow. Write any value: clears the counter, and -// cause channel to re-initiate DREQ handshake. -#define DMA_CH2_DBG_CTDREQ_OFFSET _u(0x00000880) -#define DMA_CH2_DBG_CTDREQ_BITS _u(0x0000003f) -#define DMA_CH2_DBG_CTDREQ_RESET _u(0x00000000) -#define DMA_CH2_DBG_CTDREQ_MSB _u(5) -#define DMA_CH2_DBG_CTDREQ_LSB _u(0) -#define DMA_CH2_DBG_CTDREQ_ACCESS "WC" -// ============================================================================= -// Register : DMA_CH2_DBG_TCR -// Description : Read to get channel TRANS_COUNT reload value, i.e. the length -// of the next transfer -#define DMA_CH2_DBG_TCR_OFFSET _u(0x00000884) -#define DMA_CH2_DBG_TCR_BITS _u(0xffffffff) -#define DMA_CH2_DBG_TCR_RESET _u(0x00000000) -#define DMA_CH2_DBG_TCR_MSB _u(31) -#define DMA_CH2_DBG_TCR_LSB _u(0) -#define DMA_CH2_DBG_TCR_ACCESS "RO" -// ============================================================================= -// Register : DMA_CH3_DBG_CTDREQ -// Description : Read: get channel DREQ counter (i.e. how many accesses the DMA -// expects it can perform on the peripheral without -// overflow/underflow. Write any value: clears the counter, and -// cause channel to re-initiate DREQ handshake. -#define DMA_CH3_DBG_CTDREQ_OFFSET _u(0x000008c0) -#define DMA_CH3_DBG_CTDREQ_BITS _u(0x0000003f) -#define DMA_CH3_DBG_CTDREQ_RESET _u(0x00000000) -#define DMA_CH3_DBG_CTDREQ_MSB _u(5) -#define DMA_CH3_DBG_CTDREQ_LSB _u(0) -#define DMA_CH3_DBG_CTDREQ_ACCESS "WC" -// ============================================================================= -// Register : DMA_CH3_DBG_TCR -// Description : Read to get channel TRANS_COUNT reload value, i.e. the length -// of the next transfer -#define DMA_CH3_DBG_TCR_OFFSET _u(0x000008c4) -#define DMA_CH3_DBG_TCR_BITS _u(0xffffffff) -#define DMA_CH3_DBG_TCR_RESET _u(0x00000000) -#define DMA_CH3_DBG_TCR_MSB _u(31) -#define DMA_CH3_DBG_TCR_LSB _u(0) -#define DMA_CH3_DBG_TCR_ACCESS "RO" -// ============================================================================= -// Register : DMA_CH4_DBG_CTDREQ -// Description : Read: get channel DREQ counter (i.e. how many accesses the DMA -// expects it can perform on the peripheral without -// overflow/underflow. Write any value: clears the counter, and -// cause channel to re-initiate DREQ handshake. -#define DMA_CH4_DBG_CTDREQ_OFFSET _u(0x00000900) -#define DMA_CH4_DBG_CTDREQ_BITS _u(0x0000003f) -#define DMA_CH4_DBG_CTDREQ_RESET _u(0x00000000) -#define DMA_CH4_DBG_CTDREQ_MSB _u(5) -#define DMA_CH4_DBG_CTDREQ_LSB _u(0) -#define DMA_CH4_DBG_CTDREQ_ACCESS "WC" -// ============================================================================= -// Register : DMA_CH4_DBG_TCR -// Description : Read to get channel TRANS_COUNT reload value, i.e. the length -// of the next transfer -#define DMA_CH4_DBG_TCR_OFFSET _u(0x00000904) -#define DMA_CH4_DBG_TCR_BITS _u(0xffffffff) -#define DMA_CH4_DBG_TCR_RESET _u(0x00000000) -#define DMA_CH4_DBG_TCR_MSB _u(31) -#define DMA_CH4_DBG_TCR_LSB _u(0) -#define DMA_CH4_DBG_TCR_ACCESS "RO" -// ============================================================================= -// Register : DMA_CH5_DBG_CTDREQ -// Description : Read: get channel DREQ counter (i.e. how many accesses the DMA -// expects it can perform on the peripheral without -// overflow/underflow. Write any value: clears the counter, and -// cause channel to re-initiate DREQ handshake. -#define DMA_CH5_DBG_CTDREQ_OFFSET _u(0x00000940) -#define DMA_CH5_DBG_CTDREQ_BITS _u(0x0000003f) -#define DMA_CH5_DBG_CTDREQ_RESET _u(0x00000000) -#define DMA_CH5_DBG_CTDREQ_MSB _u(5) -#define DMA_CH5_DBG_CTDREQ_LSB _u(0) -#define DMA_CH5_DBG_CTDREQ_ACCESS "WC" -// ============================================================================= -// Register : DMA_CH5_DBG_TCR -// Description : Read to get channel TRANS_COUNT reload value, i.e. the length -// of the next transfer -#define DMA_CH5_DBG_TCR_OFFSET _u(0x00000944) -#define DMA_CH5_DBG_TCR_BITS _u(0xffffffff) -#define DMA_CH5_DBG_TCR_RESET _u(0x00000000) -#define DMA_CH5_DBG_TCR_MSB _u(31) -#define DMA_CH5_DBG_TCR_LSB _u(0) -#define DMA_CH5_DBG_TCR_ACCESS "RO" -// ============================================================================= -// Register : DMA_CH6_DBG_CTDREQ -// Description : Read: get channel DREQ counter (i.e. how many accesses the DMA -// expects it can perform on the peripheral without -// overflow/underflow. Write any value: clears the counter, and -// cause channel to re-initiate DREQ handshake. -#define DMA_CH6_DBG_CTDREQ_OFFSET _u(0x00000980) -#define DMA_CH6_DBG_CTDREQ_BITS _u(0x0000003f) -#define DMA_CH6_DBG_CTDREQ_RESET _u(0x00000000) -#define DMA_CH6_DBG_CTDREQ_MSB _u(5) -#define DMA_CH6_DBG_CTDREQ_LSB _u(0) -#define DMA_CH6_DBG_CTDREQ_ACCESS "WC" -// ============================================================================= -// Register : DMA_CH6_DBG_TCR -// Description : Read to get channel TRANS_COUNT reload value, i.e. the length -// of the next transfer -#define DMA_CH6_DBG_TCR_OFFSET _u(0x00000984) -#define DMA_CH6_DBG_TCR_BITS _u(0xffffffff) -#define DMA_CH6_DBG_TCR_RESET _u(0x00000000) -#define DMA_CH6_DBG_TCR_MSB _u(31) -#define DMA_CH6_DBG_TCR_LSB _u(0) -#define DMA_CH6_DBG_TCR_ACCESS "RO" -// ============================================================================= -// Register : DMA_CH7_DBG_CTDREQ -// Description : Read: get channel DREQ counter (i.e. how many accesses the DMA -// expects it can perform on the peripheral without -// overflow/underflow. Write any value: clears the counter, and -// cause channel to re-initiate DREQ handshake. -#define DMA_CH7_DBG_CTDREQ_OFFSET _u(0x000009c0) -#define DMA_CH7_DBG_CTDREQ_BITS _u(0x0000003f) -#define DMA_CH7_DBG_CTDREQ_RESET _u(0x00000000) -#define DMA_CH7_DBG_CTDREQ_MSB _u(5) -#define DMA_CH7_DBG_CTDREQ_LSB _u(0) -#define DMA_CH7_DBG_CTDREQ_ACCESS "WC" -// ============================================================================= -// Register : DMA_CH7_DBG_TCR -// Description : Read to get channel TRANS_COUNT reload value, i.e. the length -// of the next transfer -#define DMA_CH7_DBG_TCR_OFFSET _u(0x000009c4) -#define DMA_CH7_DBG_TCR_BITS _u(0xffffffff) -#define DMA_CH7_DBG_TCR_RESET _u(0x00000000) -#define DMA_CH7_DBG_TCR_MSB _u(31) -#define DMA_CH7_DBG_TCR_LSB _u(0) -#define DMA_CH7_DBG_TCR_ACCESS "RO" -// ============================================================================= -// Register : DMA_CH8_DBG_CTDREQ -// Description : Read: get channel DREQ counter (i.e. how many accesses the DMA -// expects it can perform on the peripheral without -// overflow/underflow. Write any value: clears the counter, and -// cause channel to re-initiate DREQ handshake. -#define DMA_CH8_DBG_CTDREQ_OFFSET _u(0x00000a00) -#define DMA_CH8_DBG_CTDREQ_BITS _u(0x0000003f) -#define DMA_CH8_DBG_CTDREQ_RESET _u(0x00000000) -#define DMA_CH8_DBG_CTDREQ_MSB _u(5) -#define DMA_CH8_DBG_CTDREQ_LSB _u(0) -#define DMA_CH8_DBG_CTDREQ_ACCESS "WC" -// ============================================================================= -// Register : DMA_CH8_DBG_TCR -// Description : Read to get channel TRANS_COUNT reload value, i.e. the length -// of the next transfer -#define DMA_CH8_DBG_TCR_OFFSET _u(0x00000a04) -#define DMA_CH8_DBG_TCR_BITS _u(0xffffffff) -#define DMA_CH8_DBG_TCR_RESET _u(0x00000000) -#define DMA_CH8_DBG_TCR_MSB _u(31) -#define DMA_CH8_DBG_TCR_LSB _u(0) -#define DMA_CH8_DBG_TCR_ACCESS "RO" -// ============================================================================= -// Register : DMA_CH9_DBG_CTDREQ -// Description : Read: get channel DREQ counter (i.e. how many accesses the DMA -// expects it can perform on the peripheral without -// overflow/underflow. Write any value: clears the counter, and -// cause channel to re-initiate DREQ handshake. -#define DMA_CH9_DBG_CTDREQ_OFFSET _u(0x00000a40) -#define DMA_CH9_DBG_CTDREQ_BITS _u(0x0000003f) -#define DMA_CH9_DBG_CTDREQ_RESET _u(0x00000000) -#define DMA_CH9_DBG_CTDREQ_MSB _u(5) -#define DMA_CH9_DBG_CTDREQ_LSB _u(0) -#define DMA_CH9_DBG_CTDREQ_ACCESS "WC" -// ============================================================================= -// Register : DMA_CH9_DBG_TCR -// Description : Read to get channel TRANS_COUNT reload value, i.e. the length -// of the next transfer -#define DMA_CH9_DBG_TCR_OFFSET _u(0x00000a44) -#define DMA_CH9_DBG_TCR_BITS _u(0xffffffff) -#define DMA_CH9_DBG_TCR_RESET _u(0x00000000) -#define DMA_CH9_DBG_TCR_MSB _u(31) -#define DMA_CH9_DBG_TCR_LSB _u(0) -#define DMA_CH9_DBG_TCR_ACCESS "RO" -// ============================================================================= -// Register : DMA_CH10_DBG_CTDREQ -// Description : Read: get channel DREQ counter (i.e. how many accesses the DMA -// expects it can perform on the peripheral without -// overflow/underflow. Write any value: clears the counter, and -// cause channel to re-initiate DREQ handshake. -#define DMA_CH10_DBG_CTDREQ_OFFSET _u(0x00000a80) -#define DMA_CH10_DBG_CTDREQ_BITS _u(0x0000003f) -#define DMA_CH10_DBG_CTDREQ_RESET _u(0x00000000) -#define DMA_CH10_DBG_CTDREQ_MSB _u(5) -#define DMA_CH10_DBG_CTDREQ_LSB _u(0) -#define DMA_CH10_DBG_CTDREQ_ACCESS "WC" -// ============================================================================= -// Register : DMA_CH10_DBG_TCR -// Description : Read to get channel TRANS_COUNT reload value, i.e. the length -// of the next transfer -#define DMA_CH10_DBG_TCR_OFFSET _u(0x00000a84) -#define DMA_CH10_DBG_TCR_BITS _u(0xffffffff) -#define DMA_CH10_DBG_TCR_RESET _u(0x00000000) -#define DMA_CH10_DBG_TCR_MSB _u(31) -#define DMA_CH10_DBG_TCR_LSB _u(0) -#define DMA_CH10_DBG_TCR_ACCESS "RO" -// ============================================================================= -// Register : DMA_CH11_DBG_CTDREQ -// Description : Read: get channel DREQ counter (i.e. how many accesses the DMA -// expects it can perform on the peripheral without -// overflow/underflow. Write any value: clears the counter, and -// cause channel to re-initiate DREQ handshake. -#define DMA_CH11_DBG_CTDREQ_OFFSET _u(0x00000ac0) -#define DMA_CH11_DBG_CTDREQ_BITS _u(0x0000003f) -#define DMA_CH11_DBG_CTDREQ_RESET _u(0x00000000) -#define DMA_CH11_DBG_CTDREQ_MSB _u(5) -#define DMA_CH11_DBG_CTDREQ_LSB _u(0) -#define DMA_CH11_DBG_CTDREQ_ACCESS "WC" -// ============================================================================= -// Register : DMA_CH11_DBG_TCR -// Description : Read to get channel TRANS_COUNT reload value, i.e. the length -// of the next transfer -#define DMA_CH11_DBG_TCR_OFFSET _u(0x00000ac4) -#define DMA_CH11_DBG_TCR_BITS _u(0xffffffff) -#define DMA_CH11_DBG_TCR_RESET _u(0x00000000) -#define DMA_CH11_DBG_TCR_MSB _u(31) -#define DMA_CH11_DBG_TCR_LSB _u(0) -#define DMA_CH11_DBG_TCR_ACCESS "RO" -// ============================================================================= -#endif // _HARDWARE_REGS_DMA_H - diff --git a/lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/dreq.h b/lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/dreq.h deleted file mode 100644 index d3359f846c..0000000000 --- a/lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/dreq.h +++ /dev/null @@ -1,117 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _DREQ_H -#define _DREQ_H - -/** - * \file rp2040/dreq.h - */ - -#ifdef __ASSEMBLER__ -#define DREQ_PIO0_TX0 0 -#define DREQ_PIO0_TX1 1 -#define DREQ_PIO0_TX2 2 -#define DREQ_PIO0_TX3 3 -#define DREQ_PIO0_RX0 4 -#define DREQ_PIO0_RX1 5 -#define DREQ_PIO0_RX2 6 -#define DREQ_PIO0_RX3 7 -#define DREQ_PIO1_TX0 8 -#define DREQ_PIO1_TX1 9 -#define DREQ_PIO1_TX2 10 -#define DREQ_PIO1_TX3 11 -#define DREQ_PIO1_RX0 12 -#define DREQ_PIO1_RX1 13 -#define DREQ_PIO1_RX2 14 -#define DREQ_PIO1_RX3 15 -#define DREQ_SPI0_TX 16 -#define DREQ_SPI0_RX 17 -#define DREQ_SPI1_TX 18 -#define DREQ_SPI1_RX 19 -#define DREQ_UART0_TX 20 -#define DREQ_UART0_RX 21 -#define DREQ_UART1_TX 22 -#define DREQ_UART1_RX 23 -#define DREQ_PWM_WRAP0 24 -#define DREQ_PWM_WRAP1 25 -#define DREQ_PWM_WRAP2 26 -#define DREQ_PWM_WRAP3 27 -#define DREQ_PWM_WRAP4 28 -#define DREQ_PWM_WRAP5 29 -#define DREQ_PWM_WRAP6 30 -#define DREQ_PWM_WRAP7 31 -#define DREQ_I2C0_TX 32 -#define DREQ_I2C0_RX 33 -#define DREQ_I2C1_TX 34 -#define DREQ_I2C1_RX 35 -#define DREQ_ADC 36 -#define DREQ_XIP_STREAM 37 -#define DREQ_XIP_SSITX 38 -#define DREQ_XIP_SSIRX 39 -#define DREQ_DMA_TIMER0 59 -#define DREQ_DMA_TIMER1 60 -#define DREQ_DMA_TIMER2 61 -#define DREQ_DMA_TIMER3 62 -#define DREQ_FORCE 63 -#else -/** - * \brief DREQ numbers for DMA pacing on RP2040 (used as typedef \ref dreq_num_t) - * \ingroup hardware_dma - */ -typedef enum dreq_num_rp2040 { - DREQ_PIO0_TX0 = 0, ///< Select PIO0's TX FIFO 0 as DREQ - DREQ_PIO0_TX1 = 1, ///< Select PIO0's TX FIFO 1 as DREQ - DREQ_PIO0_TX2 = 2, ///< Select PIO0's TX FIFO 2 as DREQ - DREQ_PIO0_TX3 = 3, ///< Select PIO0's TX FIFO 3 as DREQ - DREQ_PIO0_RX0 = 4, ///< Select PIO0's RX FIFO 0 as DREQ - DREQ_PIO0_RX1 = 5, ///< Select PIO0's RX FIFO 1 as DREQ - DREQ_PIO0_RX2 = 6, ///< Select PIO0's RX FIFO 2 as DREQ - DREQ_PIO0_RX3 = 7, ///< Select PIO0's RX FIFO 3 as DREQ - DREQ_PIO1_TX0 = 8, ///< Select PIO1's TX FIFO 0 as DREQ - DREQ_PIO1_TX1 = 9, ///< Select PIO1's TX FIFO 1 as DREQ - DREQ_PIO1_TX2 = 10, ///< Select PIO1's TX FIFO 2 as DREQ - DREQ_PIO1_TX3 = 11, ///< Select PIO1's TX FIFO 3 as DREQ - DREQ_PIO1_RX0 = 12, ///< Select PIO1's RX FIFO 0 as DREQ - DREQ_PIO1_RX1 = 13, ///< Select PIO1's RX FIFO 1 as DREQ - DREQ_PIO1_RX2 = 14, ///< Select PIO1's RX FIFO 2 as DREQ - DREQ_PIO1_RX3 = 15, ///< Select PIO1's RX FIFO 3 as DREQ - DREQ_SPI0_TX = 16, ///< Select SPI0's TX FIFO as DREQ - DREQ_SPI0_RX = 17, ///< Select SPI0's RX FIFO as DREQ - DREQ_SPI1_TX = 18, ///< Select SPI1's TX FIFO as DREQ - DREQ_SPI1_RX = 19, ///< Select SPI1's RX FIFO as DREQ - DREQ_UART0_TX = 20, ///< Select UART0's TX FIFO as DREQ - DREQ_UART0_RX = 21, ///< Select UART0's RX FIFO as DREQ - DREQ_UART1_TX = 22, ///< Select UART1's TX FIFO as DREQ - DREQ_UART1_RX = 23, ///< Select UART1's RX FIFO as DREQ - DREQ_PWM_WRAP0 = 24, ///< Select PWM Counter 0's Wrap Value as DREQ - DREQ_PWM_WRAP1 = 25, ///< Select PWM Counter 1's Wrap Value as DREQ - DREQ_PWM_WRAP2 = 26, ///< Select PWM Counter 2's Wrap Value as DREQ - DREQ_PWM_WRAP3 = 27, ///< Select PWM Counter 3's Wrap Value as DREQ - DREQ_PWM_WRAP4 = 28, ///< Select PWM Counter 4's Wrap Value as DREQ - DREQ_PWM_WRAP5 = 29, ///< Select PWM Counter 5's Wrap Value as DREQ - DREQ_PWM_WRAP6 = 30, ///< Select PWM Counter 6's Wrap Value as DREQ - DREQ_PWM_WRAP7 = 31, ///< Select PWM Counter 7's Wrap Value as DREQ - DREQ_I2C0_TX = 32, ///< Select I2C0's TX FIFO as DREQ - DREQ_I2C0_RX = 33, ///< Select I2C0's RX FIFO as DREQ - DREQ_I2C1_TX = 34, ///< Select I2C1's TX FIFO as DREQ - DREQ_I2C1_RX = 35, ///< Select I2C1's RX FIFO as DREQ - DREQ_ADC = 36, ///< Select the ADC as DREQ - DREQ_XIP_STREAM = 37, ///< Select the XIP Streaming FIFO as DREQ - DREQ_XIP_SSITX = 38, ///< Select the XIP SSI TX FIFO as DREQ - DREQ_XIP_SSIRX = 39, ///< Select the XIP SSI RX FIFO as DREQ - DREQ_DMA_TIMER0 = 59, ///< Select DMA_TIMER0 as DREQ - DREQ_DMA_TIMER1 = 60, ///< Select DMA_TIMER0 as DREQ - DREQ_DMA_TIMER2 = 61, ///< Select DMA_TIMER1 as DREQ - DREQ_DMA_TIMER3 = 62, ///< Select DMA_TIMER3 as DREQ - DREQ_FORCE = 63, ///< Select FORCE as DREQ - DREQ_COUNT -} dreq_num_t; -#endif - -#endif // _DREQ_H - diff --git a/lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/i2c.h b/lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/i2c.h deleted file mode 100644 index f44ceb4402..0000000000 --- a/lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/i2c.h +++ /dev/null @@ -1,2700 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -// ============================================================================= -// Register block : I2C -// Version : 1 -// Bus type : apb -// Description : DW_apb_i2c address block -// -// List of configuration constants for the Synopsys I2C -// hardware (you may see references to these in I2C register -// header; these are *fixed* values, set at hardware design -// time): -// -// IC_ULTRA_FAST_MODE ................ 0x0 -// IC_UFM_TBUF_CNT_DEFAULT ........... 0x8 -// IC_UFM_SCL_LOW_COUNT .............. 0x0008 -// IC_UFM_SCL_HIGH_COUNT ............. 0x0006 -// IC_TX_TL .......................... 0x0 -// IC_TX_CMD_BLOCK ................... 0x1 -// IC_HAS_DMA ........................ 0x1 -// IC_HAS_ASYNC_FIFO ................. 0x0 -// IC_SMBUS_ARP ...................... 0x0 -// IC_FIRST_DATA_BYTE_STATUS ......... 0x1 -// IC_INTR_IO ........................ 0x1 -// IC_MASTER_MODE .................... 0x1 -// IC_DEFAULT_ACK_GENERAL_CALL ....... 0x1 -// IC_INTR_POL ....................... 0x1 -// IC_OPTIONAL_SAR ................... 0x0 -// IC_DEFAULT_TAR_SLAVE_ADDR ......... 0x055 -// IC_DEFAULT_SLAVE_ADDR ............. 0x055 -// IC_DEFAULT_HS_SPKLEN .............. 0x1 -// IC_FS_SCL_HIGH_COUNT .............. 0x0006 -// IC_HS_SCL_LOW_COUNT ............... 0x0008 -// IC_DEVICE_ID_VALUE ................ 0x0 -// IC_10BITADDR_MASTER ............... 0x0 -// IC_CLK_FREQ_OPTIMIZATION .......... 0x0 -// IC_DEFAULT_FS_SPKLEN .............. 0x7 -// IC_ADD_ENCODED_PARAMS ............. 0x0 -// IC_DEFAULT_SDA_HOLD ............... 0x000001 -// IC_DEFAULT_SDA_SETUP .............. 0x64 -// IC_AVOID_RX_FIFO_FLUSH_ON_TX_ABRT . 0x0 -// IC_CLOCK_PERIOD ................... 100 -// IC_EMPTYFIFO_HOLD_MASTER_EN ....... 1 -// IC_RESTART_EN ..................... 0x1 -// IC_TX_CMD_BLOCK_DEFAULT ........... 0x0 -// IC_BUS_CLEAR_FEATURE .............. 0x0 -// IC_CAP_LOADING .................... 100 -// IC_FS_SCL_LOW_COUNT ............... 0x000d -// APB_DATA_WIDTH .................... 32 -// IC_SDA_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff -// IC_SLV_DATA_NACK_ONLY ............. 0x1 -// IC_10BITADDR_SLAVE ................ 0x0 -// IC_CLK_TYPE ....................... 0x0 -// IC_SMBUS_UDID_MSB ................. 0x0 -// IC_SMBUS_SUSPEND_ALERT ............ 0x0 -// IC_HS_SCL_HIGH_COUNT .............. 0x0006 -// IC_SLV_RESTART_DET_EN ............. 0x1 -// IC_SMBUS .......................... 0x0 -// IC_OPTIONAL_SAR_DEFAULT ........... 0x0 -// IC_PERSISTANT_SLV_ADDR_DEFAULT .... 0x0 -// IC_USE_COUNTS ..................... 0x0 -// IC_RX_BUFFER_DEPTH ................ 16 -// IC_SCL_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff -// IC_RX_FULL_HLD_BUS_EN ............. 0x1 -// IC_SLAVE_DISABLE .................. 0x1 -// IC_RX_TL .......................... 0x0 -// IC_DEVICE_ID ...................... 0x0 -// IC_HC_COUNT_VALUES ................ 0x0 -// I2C_DYNAMIC_TAR_UPDATE ............ 0 -// IC_SMBUS_CLK_LOW_MEXT_DEFAULT ..... 0xffffffff -// IC_SMBUS_CLK_LOW_SEXT_DEFAULT ..... 0xffffffff -// IC_HS_MASTER_CODE ................. 0x1 -// IC_SMBUS_RST_IDLE_CNT_DEFAULT ..... 0xffff -// IC_SMBUS_UDID_LSB_DEFAULT ......... 0xffffffff -// IC_SS_SCL_HIGH_COUNT .............. 0x0028 -// IC_SS_SCL_LOW_COUNT ............... 0x002f -// IC_MAX_SPEED_MODE ................. 0x2 -// IC_STAT_FOR_CLK_STRETCH ........... 0x0 -// IC_STOP_DET_IF_MASTER_ACTIVE ...... 0x0 -// IC_DEFAULT_UFM_SPKLEN ............. 0x1 -// IC_TX_BUFFER_DEPTH ................ 16 -// ============================================================================= -#ifndef _HARDWARE_REGS_I2C_H -#define _HARDWARE_REGS_I2C_H -// ============================================================================= -// Register : I2C_IC_CON -// Description : I2C Control Register. This register can be written only when -// the DW_apb_i2c is disabled, which corresponds to the -// IC_ENABLE[0] register being set to 0. Writes at other times -// have no effect. -// -// Read/Write Access: - bit 10 is read only. - bit 11 is read only -// - bit 16 is read only - bit 17 is read only - bits 18 and 19 -// are read only. -#define I2C_IC_CON_OFFSET _u(0x00000000) -#define I2C_IC_CON_BITS _u(0x000007ff) -#define I2C_IC_CON_RESET _u(0x00000065) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_CON_STOP_DET_IF_MASTER_ACTIVE -// Description : Master issues the STOP_DET interrupt irrespective of whether -// master is active or not -#define I2C_IC_CON_STOP_DET_IF_MASTER_ACTIVE_RESET _u(0x0) -#define I2C_IC_CON_STOP_DET_IF_MASTER_ACTIVE_BITS _u(0x00000400) -#define I2C_IC_CON_STOP_DET_IF_MASTER_ACTIVE_MSB _u(10) -#define I2C_IC_CON_STOP_DET_IF_MASTER_ACTIVE_LSB _u(10) -#define I2C_IC_CON_STOP_DET_IF_MASTER_ACTIVE_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL -// Description : This bit controls whether DW_apb_i2c should hold the bus when -// the Rx FIFO is physically full to its RX_BUFFER_DEPTH, as -// described in the IC_RX_FULL_HLD_BUS_EN parameter. -// -// Reset value: 0x0. -// 0x0 -> Overflow when RX_FIFO is full -// 0x1 -> Hold bus when RX_FIFO is full -#define I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_RESET _u(0x0) -#define I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_BITS _u(0x00000200) -#define I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_MSB _u(9) -#define I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_LSB _u(9) -#define I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_ACCESS "RW" -#define I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_VALUE_DISABLED _u(0x0) -#define I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_VALUE_ENABLED _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_CON_TX_EMPTY_CTRL -// Description : This bit controls the generation of the TX_EMPTY interrupt, as -// described in the IC_RAW_INTR_STAT register. -// -// Reset value: 0x0. -// 0x0 -> Default behaviour of TX_EMPTY interrupt -// 0x1 -> Controlled generation of TX_EMPTY interrupt -#define I2C_IC_CON_TX_EMPTY_CTRL_RESET _u(0x0) -#define I2C_IC_CON_TX_EMPTY_CTRL_BITS _u(0x00000100) -#define I2C_IC_CON_TX_EMPTY_CTRL_MSB _u(8) -#define I2C_IC_CON_TX_EMPTY_CTRL_LSB _u(8) -#define I2C_IC_CON_TX_EMPTY_CTRL_ACCESS "RW" -#define I2C_IC_CON_TX_EMPTY_CTRL_VALUE_DISABLED _u(0x0) -#define I2C_IC_CON_TX_EMPTY_CTRL_VALUE_ENABLED _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_CON_STOP_DET_IFADDRESSED -// Description : In slave mode: - 1'b1: issues the STOP_DET interrupt only when -// it is addressed. - 1'b0: issues the STOP_DET irrespective of -// whether it's addressed or not. Reset value: 0x0 -// -// NOTE: During a general call address, this slave does not issue -// the STOP_DET interrupt if STOP_DET_IF_ADDRESSED = 1'b1, even if -// the slave responds to the general call address by generating -// ACK. The STOP_DET interrupt is generated only when the -// transmitted address matches the slave address (SAR). -// 0x0 -> slave issues STOP_DET intr always -// 0x1 -> slave issues STOP_DET intr only if addressed -#define I2C_IC_CON_STOP_DET_IFADDRESSED_RESET _u(0x0) -#define I2C_IC_CON_STOP_DET_IFADDRESSED_BITS _u(0x00000080) -#define I2C_IC_CON_STOP_DET_IFADDRESSED_MSB _u(7) -#define I2C_IC_CON_STOP_DET_IFADDRESSED_LSB _u(7) -#define I2C_IC_CON_STOP_DET_IFADDRESSED_ACCESS "RW" -#define I2C_IC_CON_STOP_DET_IFADDRESSED_VALUE_DISABLED _u(0x0) -#define I2C_IC_CON_STOP_DET_IFADDRESSED_VALUE_ENABLED _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_CON_IC_SLAVE_DISABLE -// Description : This bit controls whether I2C has its slave disabled, which -// means once the presetn signal is applied, then this bit is set -// and the slave is disabled. -// -// If this bit is set (slave is disabled), DW_apb_i2c functions -// only as a master and does not perform any action that requires -// a slave. -// -// NOTE: Software should ensure that if this bit is written with -// 0, then bit 0 should also be written with a 0. -// 0x0 -> Slave mode is enabled -// 0x1 -> Slave mode is disabled -#define I2C_IC_CON_IC_SLAVE_DISABLE_RESET _u(0x1) -#define I2C_IC_CON_IC_SLAVE_DISABLE_BITS _u(0x00000040) -#define I2C_IC_CON_IC_SLAVE_DISABLE_MSB _u(6) -#define I2C_IC_CON_IC_SLAVE_DISABLE_LSB _u(6) -#define I2C_IC_CON_IC_SLAVE_DISABLE_ACCESS "RW" -#define I2C_IC_CON_IC_SLAVE_DISABLE_VALUE_SLAVE_ENABLED _u(0x0) -#define I2C_IC_CON_IC_SLAVE_DISABLE_VALUE_SLAVE_DISABLED _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_CON_IC_RESTART_EN -// Description : Determines whether RESTART conditions may be sent when acting -// as a master. Some older slaves do not support handling RESTART -// conditions; however, RESTART conditions are used in several -// DW_apb_i2c operations. When RESTART is disabled, the master is -// prohibited from performing the following functions: - Sending a -// START BYTE - Performing any high-speed mode operation - High- -// speed mode operation - Performing direction changes in combined -// format mode - Performing a read operation with a 10-bit address -// By replacing RESTART condition followed by a STOP and a -// subsequent START condition, split operations are broken down -// into multiple DW_apb_i2c transfers. If the above operations are -// performed, it will result in setting bit 6 (TX_ABRT) of the -// IC_RAW_INTR_STAT register. -// -// Reset value: ENABLED -// 0x0 -> Master restart disabled -// 0x1 -> Master restart enabled -#define I2C_IC_CON_IC_RESTART_EN_RESET _u(0x1) -#define I2C_IC_CON_IC_RESTART_EN_BITS _u(0x00000020) -#define I2C_IC_CON_IC_RESTART_EN_MSB _u(5) -#define I2C_IC_CON_IC_RESTART_EN_LSB _u(5) -#define I2C_IC_CON_IC_RESTART_EN_ACCESS "RW" -#define I2C_IC_CON_IC_RESTART_EN_VALUE_DISABLED _u(0x0) -#define I2C_IC_CON_IC_RESTART_EN_VALUE_ENABLED _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_CON_IC_10BITADDR_MASTER -// Description : Controls whether the DW_apb_i2c starts its transfers in 7- or -// 10-bit addressing mode when acting as a master. - 0: 7-bit -// addressing - 1: 10-bit addressing -// 0x0 -> Master 7Bit addressing mode -// 0x1 -> Master 10Bit addressing mode -#define I2C_IC_CON_IC_10BITADDR_MASTER_RESET _u(0x0) -#define I2C_IC_CON_IC_10BITADDR_MASTER_BITS _u(0x00000010) -#define I2C_IC_CON_IC_10BITADDR_MASTER_MSB _u(4) -#define I2C_IC_CON_IC_10BITADDR_MASTER_LSB _u(4) -#define I2C_IC_CON_IC_10BITADDR_MASTER_ACCESS "RW" -#define I2C_IC_CON_IC_10BITADDR_MASTER_VALUE_ADDR_7BITS _u(0x0) -#define I2C_IC_CON_IC_10BITADDR_MASTER_VALUE_ADDR_10BITS _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_CON_IC_10BITADDR_SLAVE -// Description : When acting as a slave, this bit controls whether the -// DW_apb_i2c responds to 7- or 10-bit addresses. - 0: 7-bit -// addressing. The DW_apb_i2c ignores transactions that involve -// 10-bit addressing; for 7-bit addressing, only the lower 7 bits -// of the IC_SAR register are compared. - 1: 10-bit addressing. -// The DW_apb_i2c responds to only 10-bit addressing transfers -// that match the full 10 bits of the IC_SAR register. -// 0x0 -> Slave 7Bit addressing -// 0x1 -> Slave 10Bit addressing -#define I2C_IC_CON_IC_10BITADDR_SLAVE_RESET _u(0x0) -#define I2C_IC_CON_IC_10BITADDR_SLAVE_BITS _u(0x00000008) -#define I2C_IC_CON_IC_10BITADDR_SLAVE_MSB _u(3) -#define I2C_IC_CON_IC_10BITADDR_SLAVE_LSB _u(3) -#define I2C_IC_CON_IC_10BITADDR_SLAVE_ACCESS "RW" -#define I2C_IC_CON_IC_10BITADDR_SLAVE_VALUE_ADDR_7BITS _u(0x0) -#define I2C_IC_CON_IC_10BITADDR_SLAVE_VALUE_ADDR_10BITS _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_CON_SPEED -// Description : These bits control at which speed the DW_apb_i2c operates; its -// setting is relevant only if one is operating the DW_apb_i2c in -// master mode. Hardware protects against illegal values being -// programmed by software. These bits must be programmed -// appropriately for slave mode also, as it is used to capture -// correct value of spike filter as per the speed mode. -// -// This register should be programmed only with a value in the -// range of 1 to IC_MAX_SPEED_MODE; otherwise, hardware updates -// this register with the value of IC_MAX_SPEED_MODE. -// -// 1: standard mode (100 kbit/s) -// -// 2: fast mode (<=400 kbit/s) or fast mode plus (<=1000Kbit/s) -// -// 3: high speed mode (3.4 Mbit/s) -// -// Note: This field is not applicable when IC_ULTRA_FAST_MODE=1 -// 0x1 -> Standard Speed mode of operation -// 0x2 -> Fast or Fast Plus mode of operation -// 0x3 -> High Speed mode of operation -#define I2C_IC_CON_SPEED_RESET _u(0x2) -#define I2C_IC_CON_SPEED_BITS _u(0x00000006) -#define I2C_IC_CON_SPEED_MSB _u(2) -#define I2C_IC_CON_SPEED_LSB _u(1) -#define I2C_IC_CON_SPEED_ACCESS "RW" -#define I2C_IC_CON_SPEED_VALUE_STANDARD _u(0x1) -#define I2C_IC_CON_SPEED_VALUE_FAST _u(0x2) -#define I2C_IC_CON_SPEED_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_CON_MASTER_MODE -// Description : This bit controls whether the DW_apb_i2c master is enabled. -// -// NOTE: Software should ensure that if this bit is written with -// '1' then bit 6 should also be written with a '1'. -// 0x0 -> Master mode is disabled -// 0x1 -> Master mode is enabled -#define I2C_IC_CON_MASTER_MODE_RESET _u(0x1) -#define I2C_IC_CON_MASTER_MODE_BITS _u(0x00000001) -#define I2C_IC_CON_MASTER_MODE_MSB _u(0) -#define I2C_IC_CON_MASTER_MODE_LSB _u(0) -#define I2C_IC_CON_MASTER_MODE_ACCESS "RW" -#define I2C_IC_CON_MASTER_MODE_VALUE_DISABLED _u(0x0) -#define I2C_IC_CON_MASTER_MODE_VALUE_ENABLED _u(0x1) -// ============================================================================= -// Register : I2C_IC_TAR -// Description : I2C Target Address Register -// -// This register is 12 bits wide, and bits 31:12 are reserved. -// This register can be written to only when IC_ENABLE[0] is set -// to 0. -// -// Note: If the software or application is aware that the -// DW_apb_i2c is not using the TAR address for the pending -// commands in the Tx FIFO, then it is possible to update the TAR -// address even while the Tx FIFO has entries (IC_STATUS[2]= 0). - -// It is not necessary to perform any write to this register if -// DW_apb_i2c is enabled as an I2C slave only. -#define I2C_IC_TAR_OFFSET _u(0x00000004) -#define I2C_IC_TAR_BITS _u(0x00000fff) -#define I2C_IC_TAR_RESET _u(0x00000055) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_TAR_SPECIAL -// Description : This bit indicates whether software performs a Device-ID or -// General Call or START BYTE command. - 0: ignore bit 10 -// GC_OR_START and use IC_TAR normally - 1: perform special I2C -// command as specified in Device_ID or GC_OR_START bit Reset -// value: 0x0 -// 0x0 -> Disables programming of GENERAL_CALL or START_BYTE transmission -// 0x1 -> Enables programming of GENERAL_CALL or START_BYTE transmission -#define I2C_IC_TAR_SPECIAL_RESET _u(0x0) -#define I2C_IC_TAR_SPECIAL_BITS _u(0x00000800) -#define I2C_IC_TAR_SPECIAL_MSB _u(11) -#define I2C_IC_TAR_SPECIAL_LSB _u(11) -#define I2C_IC_TAR_SPECIAL_ACCESS "RW" -#define I2C_IC_TAR_SPECIAL_VALUE_DISABLED _u(0x0) -#define I2C_IC_TAR_SPECIAL_VALUE_ENABLED _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_TAR_GC_OR_START -// Description : If bit 11 (SPECIAL) is set to 1 and bit 13(Device-ID) is set to -// 0, then this bit indicates whether a General Call or START byte -// command is to be performed by the DW_apb_i2c. - 0: General Call -// Address - after issuing a General Call, only writes may be -// performed. Attempting to issue a read command results in -// setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register. The -// DW_apb_i2c remains in General Call mode until the SPECIAL bit -// value (bit 11) is cleared. - 1: START BYTE Reset value: 0x0 -// 0x0 -> GENERAL_CALL byte transmission -// 0x1 -> START byte transmission -#define I2C_IC_TAR_GC_OR_START_RESET _u(0x0) -#define I2C_IC_TAR_GC_OR_START_BITS _u(0x00000400) -#define I2C_IC_TAR_GC_OR_START_MSB _u(10) -#define I2C_IC_TAR_GC_OR_START_LSB _u(10) -#define I2C_IC_TAR_GC_OR_START_ACCESS "RW" -#define I2C_IC_TAR_GC_OR_START_VALUE_GENERAL_CALL _u(0x0) -#define I2C_IC_TAR_GC_OR_START_VALUE_START_BYTE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_TAR_IC_TAR -// Description : This is the target address for any master transaction. When -// transmitting a General Call, these bits are ignored. To -// generate a START BYTE, the CPU needs to write only once into -// these bits. -// -// If the IC_TAR and IC_SAR are the same, loopback exists but the -// FIFOs are shared between master and slave, so full loopback is -// not feasible. Only one direction loopback mode is supported -// (simplex), not duplex. A master cannot transmit to itself; it -// can transmit to only a slave. -#define I2C_IC_TAR_IC_TAR_RESET _u(0x055) -#define I2C_IC_TAR_IC_TAR_BITS _u(0x000003ff) -#define I2C_IC_TAR_IC_TAR_MSB _u(9) -#define I2C_IC_TAR_IC_TAR_LSB _u(0) -#define I2C_IC_TAR_IC_TAR_ACCESS "RW" -// ============================================================================= -// Register : I2C_IC_SAR -// Description : I2C Slave Address Register -#define I2C_IC_SAR_OFFSET _u(0x00000008) -#define I2C_IC_SAR_BITS _u(0x000003ff) -#define I2C_IC_SAR_RESET _u(0x00000055) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_SAR_IC_SAR -// Description : The IC_SAR holds the slave address when the I2C is operating as -// a slave. For 7-bit addressing, only IC_SAR[6:0] is used. -// -// This register can be written only when the I2C interface is -// disabled, which corresponds to the IC_ENABLE[0] register being -// set to 0. Writes at other times have no effect. -// -// Note: The default values cannot be any of the reserved address -// locations: that is, 0x00 to 0x07, or 0x78 to 0x7f. The correct -// operation of the device is not guaranteed if you program the -// IC_SAR or IC_TAR to a reserved value. Refer to -// <> for a complete list of these -// reserved values. -#define I2C_IC_SAR_IC_SAR_RESET _u(0x055) -#define I2C_IC_SAR_IC_SAR_BITS _u(0x000003ff) -#define I2C_IC_SAR_IC_SAR_MSB _u(9) -#define I2C_IC_SAR_IC_SAR_LSB _u(0) -#define I2C_IC_SAR_IC_SAR_ACCESS "RW" -// ============================================================================= -// Register : I2C_IC_DATA_CMD -// Description : I2C Rx/Tx Data Buffer and Command Register; this is the -// register the CPU writes to when filling the TX FIFO and the CPU -// reads from when retrieving bytes from RX FIFO. -// -// The size of the register changes as follows: -// -// Write: - 11 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=1 - 9 bits -// when IC_EMPTYFIFO_HOLD_MASTER_EN=0 Read: - 12 bits when -// IC_FIRST_DATA_BYTE_STATUS = 1 - 8 bits when -// IC_FIRST_DATA_BYTE_STATUS = 0 Note: In order for the DW_apb_i2c -// to continue acknowledging reads, a read command should be -// written for every byte that is to be received; otherwise the -// DW_apb_i2c will stop acknowledging. -#define I2C_IC_DATA_CMD_OFFSET _u(0x00000010) -#define I2C_IC_DATA_CMD_BITS _u(0x00000fff) -#define I2C_IC_DATA_CMD_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_DATA_CMD_FIRST_DATA_BYTE -// Description : Indicates the first data byte received after the address phase -// for receive transfer in Master receiver or Slave receiver mode. -// -// Reset value : 0x0 -// -// NOTE: In case of APB_DATA_WIDTH=8, -// -// 1. The user has to perform two APB Reads to IC_DATA_CMD in -// order to get status on 11 bit. -// -// 2. In order to read the 11 bit, the user has to perform the -// first data byte read [7:0] (offset 0x10) and then perform the -// second read [15:8] (offset 0x11) in order to know the status of -// 11 bit (whether the data received in previous read is a first -// data byte or not). -// -// 3. The 11th bit is an optional read field, user can ignore 2nd -// byte read [15:8] (offset 0x11) if not interested in -// FIRST_DATA_BYTE status. -// 0x0 -> Sequential data byte received -// 0x1 -> Non sequential data byte received -#define I2C_IC_DATA_CMD_FIRST_DATA_BYTE_RESET _u(0x0) -#define I2C_IC_DATA_CMD_FIRST_DATA_BYTE_BITS _u(0x00000800) -#define I2C_IC_DATA_CMD_FIRST_DATA_BYTE_MSB _u(11) -#define I2C_IC_DATA_CMD_FIRST_DATA_BYTE_LSB _u(11) -#define I2C_IC_DATA_CMD_FIRST_DATA_BYTE_ACCESS "RO" -#define I2C_IC_DATA_CMD_FIRST_DATA_BYTE_VALUE_INACTIVE _u(0x0) -#define I2C_IC_DATA_CMD_FIRST_DATA_BYTE_VALUE_ACTIVE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_DATA_CMD_RESTART -// Description : This bit controls whether a RESTART is issued before the byte -// is sent or received. -// -// 1 - If IC_RESTART_EN is 1, a RESTART is issued before the data -// is sent/received (according to the value of CMD), regardless of -// whether or not the transfer direction is changing from the -// previous command; if IC_RESTART_EN is 0, a STOP followed by a -// START is issued instead. -// -// 0 - If IC_RESTART_EN is 1, a RESTART is issued only if the -// transfer direction is changing from the previous command; if -// IC_RESTART_EN is 0, a STOP followed by a START is issued -// instead. -// -// Reset value: 0x0 -// 0x0 -> Don't Issue RESTART before this command -// 0x1 -> Issue RESTART before this command -#define I2C_IC_DATA_CMD_RESTART_RESET _u(0x0) -#define I2C_IC_DATA_CMD_RESTART_BITS _u(0x00000400) -#define I2C_IC_DATA_CMD_RESTART_MSB _u(10) -#define I2C_IC_DATA_CMD_RESTART_LSB _u(10) -#define I2C_IC_DATA_CMD_RESTART_ACCESS "SC" -#define I2C_IC_DATA_CMD_RESTART_VALUE_DISABLE _u(0x0) -#define I2C_IC_DATA_CMD_RESTART_VALUE_ENABLE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_DATA_CMD_STOP -// Description : This bit controls whether a STOP is issued after the byte is -// sent or received. -// -// - 1 - STOP is issued after this byte, regardless of whether or -// not the Tx FIFO is empty. If the Tx FIFO is not empty, the -// master immediately tries to start a new transfer by issuing a -// START and arbitrating for the bus. - 0 - STOP is not issued -// after this byte, regardless of whether or not the Tx FIFO is -// empty. If the Tx FIFO is not empty, the master continues the -// current transfer by sending/receiving data bytes according to -// the value of the CMD bit. If the Tx FIFO is empty, the master -// holds the SCL line low and stalls the bus until a new command -// is available in the Tx FIFO. Reset value: 0x0 -// 0x0 -> Don't Issue STOP after this command -// 0x1 -> Issue STOP after this command -#define I2C_IC_DATA_CMD_STOP_RESET _u(0x0) -#define I2C_IC_DATA_CMD_STOP_BITS _u(0x00000200) -#define I2C_IC_DATA_CMD_STOP_MSB _u(9) -#define I2C_IC_DATA_CMD_STOP_LSB _u(9) -#define I2C_IC_DATA_CMD_STOP_ACCESS "SC" -#define I2C_IC_DATA_CMD_STOP_VALUE_DISABLE _u(0x0) -#define I2C_IC_DATA_CMD_STOP_VALUE_ENABLE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_DATA_CMD_CMD -// Description : This bit controls whether a read or a write is performed. This -// bit does not control the direction when the DW_apb_i2con acts -// as a slave. It controls only the direction when it acts as a -// master. -// -// When a command is entered in the TX FIFO, this bit -// distinguishes the write and read commands. In slave-receiver -// mode, this bit is a 'don't care' because writes to this -// register are not required. In slave-transmitter mode, a '0' -// indicates that the data in IC_DATA_CMD is to be transmitted. -// -// When programming this bit, you should remember the following: -// attempting to perform a read operation after a General Call -// command has been sent results in a TX_ABRT interrupt (bit 6 of -// the IC_RAW_INTR_STAT register), unless bit 11 (SPECIAL) in the -// IC_TAR register has been cleared. If a '1' is written to this -// bit after receiving a RD_REQ interrupt, then a TX_ABRT -// interrupt occurs. -// -// Reset value: 0x0 -// 0x0 -> Master Write Command -// 0x1 -> Master Read Command -#define I2C_IC_DATA_CMD_CMD_RESET _u(0x0) -#define I2C_IC_DATA_CMD_CMD_BITS _u(0x00000100) -#define I2C_IC_DATA_CMD_CMD_MSB _u(8) -#define I2C_IC_DATA_CMD_CMD_LSB _u(8) -#define I2C_IC_DATA_CMD_CMD_ACCESS "SC" -#define I2C_IC_DATA_CMD_CMD_VALUE_WRITE _u(0x0) -#define I2C_IC_DATA_CMD_CMD_VALUE_READ _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_DATA_CMD_DAT -// Description : This register contains the data to be transmitted or received -// on the I2C bus. If you are writing to this register and want to -// perform a read, bits 7:0 (DAT) are ignored by the DW_apb_i2c. -// However, when you read this register, these bits return the -// value of data received on the DW_apb_i2c interface. -// -// Reset value: 0x0 -#define I2C_IC_DATA_CMD_DAT_RESET _u(0x00) -#define I2C_IC_DATA_CMD_DAT_BITS _u(0x000000ff) -#define I2C_IC_DATA_CMD_DAT_MSB _u(7) -#define I2C_IC_DATA_CMD_DAT_LSB _u(0) -#define I2C_IC_DATA_CMD_DAT_ACCESS "RW" -// ============================================================================= -// Register : I2C_IC_SS_SCL_HCNT -// Description : Standard Speed I2C Clock SCL High Count Register -#define I2C_IC_SS_SCL_HCNT_OFFSET _u(0x00000014) -#define I2C_IC_SS_SCL_HCNT_BITS _u(0x0000ffff) -#define I2C_IC_SS_SCL_HCNT_RESET _u(0x00000028) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_SS_SCL_HCNT_IC_SS_SCL_HCNT -// Description : This register must be set before any I2C bus transaction can -// take place to ensure proper I/O timing. This register sets the -// SCL clock high-period count for standard speed. For more -// information, refer to 'IC_CLK Frequency Configuration'. -// -// This register can be written only when the I2C interface is -// disabled which corresponds to the IC_ENABLE[0] register being -// set to 0. Writes at other times have no effect. -// -// The minimum valid value is 6; hardware prevents values less -// than this being written, and if attempted results in 6 being -// set. For designs with APB_DATA_WIDTH = 8, the order of -// programming is important to ensure the correct operation of the -// DW_apb_i2c. The lower byte must be programmed first. Then the -// upper byte is programmed. -// -// NOTE: This register must not be programmed to a value higher -// than 65525, because DW_apb_i2c uses a 16-bit counter to flag an -// I2C bus idle condition when this counter reaches a value of -// IC_SS_SCL_HCNT + 10. -#define I2C_IC_SS_SCL_HCNT_IC_SS_SCL_HCNT_RESET _u(0x0028) -#define I2C_IC_SS_SCL_HCNT_IC_SS_SCL_HCNT_BITS _u(0x0000ffff) -#define I2C_IC_SS_SCL_HCNT_IC_SS_SCL_HCNT_MSB _u(15) -#define I2C_IC_SS_SCL_HCNT_IC_SS_SCL_HCNT_LSB _u(0) -#define I2C_IC_SS_SCL_HCNT_IC_SS_SCL_HCNT_ACCESS "RW" -// ============================================================================= -// Register : I2C_IC_SS_SCL_LCNT -// Description : Standard Speed I2C Clock SCL Low Count Register -#define I2C_IC_SS_SCL_LCNT_OFFSET _u(0x00000018) -#define I2C_IC_SS_SCL_LCNT_BITS _u(0x0000ffff) -#define I2C_IC_SS_SCL_LCNT_RESET _u(0x0000002f) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_SS_SCL_LCNT_IC_SS_SCL_LCNT -// Description : This register must be set before any I2C bus transaction can -// take place to ensure proper I/O timing. This register sets the -// SCL clock low period count for standard speed. For more -// information, refer to 'IC_CLK Frequency Configuration' -// -// This register can be written only when the I2C interface is -// disabled which corresponds to the IC_ENABLE[0] register being -// set to 0. Writes at other times have no effect. -// -// The minimum valid value is 8; hardware prevents values less -// than this being written, and if attempted, results in 8 being -// set. For designs with APB_DATA_WIDTH = 8, the order of -// programming is important to ensure the correct operation of -// DW_apb_i2c. The lower byte must be programmed first, and then -// the upper byte is programmed. -#define I2C_IC_SS_SCL_LCNT_IC_SS_SCL_LCNT_RESET _u(0x002f) -#define I2C_IC_SS_SCL_LCNT_IC_SS_SCL_LCNT_BITS _u(0x0000ffff) -#define I2C_IC_SS_SCL_LCNT_IC_SS_SCL_LCNT_MSB _u(15) -#define I2C_IC_SS_SCL_LCNT_IC_SS_SCL_LCNT_LSB _u(0) -#define I2C_IC_SS_SCL_LCNT_IC_SS_SCL_LCNT_ACCESS "RW" -// ============================================================================= -// Register : I2C_IC_FS_SCL_HCNT -// Description : Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register -#define I2C_IC_FS_SCL_HCNT_OFFSET _u(0x0000001c) -#define I2C_IC_FS_SCL_HCNT_BITS _u(0x0000ffff) -#define I2C_IC_FS_SCL_HCNT_RESET _u(0x00000006) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_FS_SCL_HCNT_IC_FS_SCL_HCNT -// Description : This register must be set before any I2C bus transaction can -// take place to ensure proper I/O timing. This register sets the -// SCL clock high-period count for fast mode or fast mode plus. It -// is used in high-speed mode to send the Master Code and START -// BYTE or General CALL. For more information, refer to 'IC_CLK -// Frequency Configuration'. -// -// This register goes away and becomes read-only returning 0s if -// IC_MAX_SPEED_MODE = standard. This register can be written only -// when the I2C interface is disabled, which corresponds to the -// IC_ENABLE[0] register being set to 0. Writes at other times -// have no effect. -// -// The minimum valid value is 6; hardware prevents values less -// than this being written, and if attempted results in 6 being -// set. For designs with APB_DATA_WIDTH == 8 the order of -// programming is important to ensure the correct operation of the -// DW_apb_i2c. The lower byte must be programmed first. Then the -// upper byte is programmed. -#define I2C_IC_FS_SCL_HCNT_IC_FS_SCL_HCNT_RESET _u(0x0006) -#define I2C_IC_FS_SCL_HCNT_IC_FS_SCL_HCNT_BITS _u(0x0000ffff) -#define I2C_IC_FS_SCL_HCNT_IC_FS_SCL_HCNT_MSB _u(15) -#define I2C_IC_FS_SCL_HCNT_IC_FS_SCL_HCNT_LSB _u(0) -#define I2C_IC_FS_SCL_HCNT_IC_FS_SCL_HCNT_ACCESS "RW" -// ============================================================================= -// Register : I2C_IC_FS_SCL_LCNT -// Description : Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register -#define I2C_IC_FS_SCL_LCNT_OFFSET _u(0x00000020) -#define I2C_IC_FS_SCL_LCNT_BITS _u(0x0000ffff) -#define I2C_IC_FS_SCL_LCNT_RESET _u(0x0000000d) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT -// Description : This register must be set before any I2C bus transaction can -// take place to ensure proper I/O timing. This register sets the -// SCL clock low period count for fast speed. It is used in high- -// speed mode to send the Master Code and START BYTE or General -// CALL. For more information, refer to 'IC_CLK Frequency -// Configuration'. -// -// This register goes away and becomes read-only returning 0s if -// IC_MAX_SPEED_MODE = standard. -// -// This register can be written only when the I2C interface is -// disabled, which corresponds to the IC_ENABLE[0] register being -// set to 0. Writes at other times have no effect. -// -// The minimum valid value is 8; hardware prevents values less -// than this being written, and if attempted results in 8 being -// set. For designs with APB_DATA_WIDTH = 8 the order of -// programming is important to ensure the correct operation of the -// DW_apb_i2c. The lower byte must be programmed first. Then the -// upper byte is programmed. If the value is less than 8 then the -// count value gets changed to 8. -#define I2C_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT_RESET _u(0x000d) -#define I2C_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT_BITS _u(0x0000ffff) -#define I2C_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT_MSB _u(15) -#define I2C_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT_LSB _u(0) -#define I2C_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT_ACCESS "RW" -// ============================================================================= -// Register : I2C_IC_INTR_STAT -// Description : I2C Interrupt Status Register -// -// Each bit in this register has a corresponding mask bit in the -// IC_INTR_MASK register. These bits are cleared by reading the -// matching interrupt clear register. The unmasked raw versions of -// these bits are available in the IC_RAW_INTR_STAT register. -#define I2C_IC_INTR_STAT_OFFSET _u(0x0000002c) -#define I2C_IC_INTR_STAT_BITS _u(0x00001fff) -#define I2C_IC_INTR_STAT_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_INTR_STAT_R_RESTART_DET -// Description : See IC_RAW_INTR_STAT for a detailed description of -// R_RESTART_DET bit. -// -// Reset value: 0x0 -// 0x0 -> R_RESTART_DET interrupt is inactive -// 0x1 -> R_RESTART_DET interrupt is active -#define I2C_IC_INTR_STAT_R_RESTART_DET_RESET _u(0x0) -#define I2C_IC_INTR_STAT_R_RESTART_DET_BITS _u(0x00001000) -#define I2C_IC_INTR_STAT_R_RESTART_DET_MSB _u(12) -#define I2C_IC_INTR_STAT_R_RESTART_DET_LSB _u(12) -#define I2C_IC_INTR_STAT_R_RESTART_DET_ACCESS "RO" -#define I2C_IC_INTR_STAT_R_RESTART_DET_VALUE_INACTIVE _u(0x0) -#define I2C_IC_INTR_STAT_R_RESTART_DET_VALUE_ACTIVE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_INTR_STAT_R_GEN_CALL -// Description : See IC_RAW_INTR_STAT for a detailed description of R_GEN_CALL -// bit. -// -// Reset value: 0x0 -// 0x0 -> R_GEN_CALL interrupt is inactive -// 0x1 -> R_GEN_CALL interrupt is active -#define I2C_IC_INTR_STAT_R_GEN_CALL_RESET _u(0x0) -#define I2C_IC_INTR_STAT_R_GEN_CALL_BITS _u(0x00000800) -#define I2C_IC_INTR_STAT_R_GEN_CALL_MSB _u(11) -#define I2C_IC_INTR_STAT_R_GEN_CALL_LSB _u(11) -#define I2C_IC_INTR_STAT_R_GEN_CALL_ACCESS "RO" -#define I2C_IC_INTR_STAT_R_GEN_CALL_VALUE_INACTIVE _u(0x0) -#define I2C_IC_INTR_STAT_R_GEN_CALL_VALUE_ACTIVE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_INTR_STAT_R_START_DET -// Description : See IC_RAW_INTR_STAT for a detailed description of R_START_DET -// bit. -// -// Reset value: 0x0 -// 0x0 -> R_START_DET interrupt is inactive -// 0x1 -> R_START_DET interrupt is active -#define I2C_IC_INTR_STAT_R_START_DET_RESET _u(0x0) -#define I2C_IC_INTR_STAT_R_START_DET_BITS _u(0x00000400) -#define I2C_IC_INTR_STAT_R_START_DET_MSB _u(10) -#define I2C_IC_INTR_STAT_R_START_DET_LSB _u(10) -#define I2C_IC_INTR_STAT_R_START_DET_ACCESS "RO" -#define I2C_IC_INTR_STAT_R_START_DET_VALUE_INACTIVE _u(0x0) -#define I2C_IC_INTR_STAT_R_START_DET_VALUE_ACTIVE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_INTR_STAT_R_STOP_DET -// Description : See IC_RAW_INTR_STAT for a detailed description of R_STOP_DET -// bit. -// -// Reset value: 0x0 -// 0x0 -> R_STOP_DET interrupt is inactive -// 0x1 -> R_STOP_DET interrupt is active -#define I2C_IC_INTR_STAT_R_STOP_DET_RESET _u(0x0) -#define I2C_IC_INTR_STAT_R_STOP_DET_BITS _u(0x00000200) -#define I2C_IC_INTR_STAT_R_STOP_DET_MSB _u(9) -#define I2C_IC_INTR_STAT_R_STOP_DET_LSB _u(9) -#define I2C_IC_INTR_STAT_R_STOP_DET_ACCESS "RO" -#define I2C_IC_INTR_STAT_R_STOP_DET_VALUE_INACTIVE _u(0x0) -#define I2C_IC_INTR_STAT_R_STOP_DET_VALUE_ACTIVE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_INTR_STAT_R_ACTIVITY -// Description : See IC_RAW_INTR_STAT for a detailed description of R_ACTIVITY -// bit. -// -// Reset value: 0x0 -// 0x0 -> R_ACTIVITY interrupt is inactive -// 0x1 -> R_ACTIVITY interrupt is active -#define I2C_IC_INTR_STAT_R_ACTIVITY_RESET _u(0x0) -#define I2C_IC_INTR_STAT_R_ACTIVITY_BITS _u(0x00000100) -#define I2C_IC_INTR_STAT_R_ACTIVITY_MSB _u(8) -#define I2C_IC_INTR_STAT_R_ACTIVITY_LSB _u(8) -#define I2C_IC_INTR_STAT_R_ACTIVITY_ACCESS "RO" -#define I2C_IC_INTR_STAT_R_ACTIVITY_VALUE_INACTIVE _u(0x0) -#define I2C_IC_INTR_STAT_R_ACTIVITY_VALUE_ACTIVE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_INTR_STAT_R_RX_DONE -// Description : See IC_RAW_INTR_STAT for a detailed description of R_RX_DONE -// bit. -// -// Reset value: 0x0 -// 0x0 -> R_RX_DONE interrupt is inactive -// 0x1 -> R_RX_DONE interrupt is active -#define I2C_IC_INTR_STAT_R_RX_DONE_RESET _u(0x0) -#define I2C_IC_INTR_STAT_R_RX_DONE_BITS _u(0x00000080) -#define I2C_IC_INTR_STAT_R_RX_DONE_MSB _u(7) -#define I2C_IC_INTR_STAT_R_RX_DONE_LSB _u(7) -#define I2C_IC_INTR_STAT_R_RX_DONE_ACCESS "RO" -#define I2C_IC_INTR_STAT_R_RX_DONE_VALUE_INACTIVE _u(0x0) -#define I2C_IC_INTR_STAT_R_RX_DONE_VALUE_ACTIVE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_INTR_STAT_R_TX_ABRT -// Description : See IC_RAW_INTR_STAT for a detailed description of R_TX_ABRT -// bit. -// -// Reset value: 0x0 -// 0x0 -> R_TX_ABRT interrupt is inactive -// 0x1 -> R_TX_ABRT interrupt is active -#define I2C_IC_INTR_STAT_R_TX_ABRT_RESET _u(0x0) -#define I2C_IC_INTR_STAT_R_TX_ABRT_BITS _u(0x00000040) -#define I2C_IC_INTR_STAT_R_TX_ABRT_MSB _u(6) -#define I2C_IC_INTR_STAT_R_TX_ABRT_LSB _u(6) -#define I2C_IC_INTR_STAT_R_TX_ABRT_ACCESS "RO" -#define I2C_IC_INTR_STAT_R_TX_ABRT_VALUE_INACTIVE _u(0x0) -#define I2C_IC_INTR_STAT_R_TX_ABRT_VALUE_ACTIVE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_INTR_STAT_R_RD_REQ -// Description : See IC_RAW_INTR_STAT for a detailed description of R_RD_REQ -// bit. -// -// Reset value: 0x0 -// 0x0 -> R_RD_REQ interrupt is inactive -// 0x1 -> R_RD_REQ interrupt is active -#define I2C_IC_INTR_STAT_R_RD_REQ_RESET _u(0x0) -#define I2C_IC_INTR_STAT_R_RD_REQ_BITS _u(0x00000020) -#define I2C_IC_INTR_STAT_R_RD_REQ_MSB _u(5) -#define I2C_IC_INTR_STAT_R_RD_REQ_LSB _u(5) -#define I2C_IC_INTR_STAT_R_RD_REQ_ACCESS "RO" -#define I2C_IC_INTR_STAT_R_RD_REQ_VALUE_INACTIVE _u(0x0) -#define I2C_IC_INTR_STAT_R_RD_REQ_VALUE_ACTIVE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_INTR_STAT_R_TX_EMPTY -// Description : See IC_RAW_INTR_STAT for a detailed description of R_TX_EMPTY -// bit. -// -// Reset value: 0x0 -// 0x0 -> R_TX_EMPTY interrupt is inactive -// 0x1 -> R_TX_EMPTY interrupt is active -#define I2C_IC_INTR_STAT_R_TX_EMPTY_RESET _u(0x0) -#define I2C_IC_INTR_STAT_R_TX_EMPTY_BITS _u(0x00000010) -#define I2C_IC_INTR_STAT_R_TX_EMPTY_MSB _u(4) -#define I2C_IC_INTR_STAT_R_TX_EMPTY_LSB _u(4) -#define I2C_IC_INTR_STAT_R_TX_EMPTY_ACCESS "RO" -#define I2C_IC_INTR_STAT_R_TX_EMPTY_VALUE_INACTIVE _u(0x0) -#define I2C_IC_INTR_STAT_R_TX_EMPTY_VALUE_ACTIVE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_INTR_STAT_R_TX_OVER -// Description : See IC_RAW_INTR_STAT for a detailed description of R_TX_OVER -// bit. -// -// Reset value: 0x0 -// 0x0 -> R_TX_OVER interrupt is inactive -// 0x1 -> R_TX_OVER interrupt is active -#define I2C_IC_INTR_STAT_R_TX_OVER_RESET _u(0x0) -#define I2C_IC_INTR_STAT_R_TX_OVER_BITS _u(0x00000008) -#define I2C_IC_INTR_STAT_R_TX_OVER_MSB _u(3) -#define I2C_IC_INTR_STAT_R_TX_OVER_LSB _u(3) -#define I2C_IC_INTR_STAT_R_TX_OVER_ACCESS "RO" -#define I2C_IC_INTR_STAT_R_TX_OVER_VALUE_INACTIVE _u(0x0) -#define I2C_IC_INTR_STAT_R_TX_OVER_VALUE_ACTIVE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_INTR_STAT_R_RX_FULL -// Description : See IC_RAW_INTR_STAT for a detailed description of R_RX_FULL -// bit. -// -// Reset value: 0x0 -// 0x0 -> R_RX_FULL interrupt is inactive -// 0x1 -> R_RX_FULL interrupt is active -#define I2C_IC_INTR_STAT_R_RX_FULL_RESET _u(0x0) -#define I2C_IC_INTR_STAT_R_RX_FULL_BITS _u(0x00000004) -#define I2C_IC_INTR_STAT_R_RX_FULL_MSB _u(2) -#define I2C_IC_INTR_STAT_R_RX_FULL_LSB _u(2) -#define I2C_IC_INTR_STAT_R_RX_FULL_ACCESS "RO" -#define I2C_IC_INTR_STAT_R_RX_FULL_VALUE_INACTIVE _u(0x0) -#define I2C_IC_INTR_STAT_R_RX_FULL_VALUE_ACTIVE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_INTR_STAT_R_RX_OVER -// Description : See IC_RAW_INTR_STAT for a detailed description of R_RX_OVER -// bit. -// -// Reset value: 0x0 -// 0x0 -> R_RX_OVER interrupt is inactive -// 0x1 -> R_RX_OVER interrupt is active -#define I2C_IC_INTR_STAT_R_RX_OVER_RESET _u(0x0) -#define I2C_IC_INTR_STAT_R_RX_OVER_BITS _u(0x00000002) -#define I2C_IC_INTR_STAT_R_RX_OVER_MSB _u(1) -#define I2C_IC_INTR_STAT_R_RX_OVER_LSB _u(1) -#define I2C_IC_INTR_STAT_R_RX_OVER_ACCESS "RO" -#define I2C_IC_INTR_STAT_R_RX_OVER_VALUE_INACTIVE _u(0x0) -#define I2C_IC_INTR_STAT_R_RX_OVER_VALUE_ACTIVE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_INTR_STAT_R_RX_UNDER -// Description : See IC_RAW_INTR_STAT for a detailed description of R_RX_UNDER -// bit. -// -// Reset value: 0x0 -// 0x0 -> RX_UNDER interrupt is inactive -// 0x1 -> RX_UNDER interrupt is active -#define I2C_IC_INTR_STAT_R_RX_UNDER_RESET _u(0x0) -#define I2C_IC_INTR_STAT_R_RX_UNDER_BITS _u(0x00000001) -#define I2C_IC_INTR_STAT_R_RX_UNDER_MSB _u(0) -#define I2C_IC_INTR_STAT_R_RX_UNDER_LSB _u(0) -#define I2C_IC_INTR_STAT_R_RX_UNDER_ACCESS "RO" -#define I2C_IC_INTR_STAT_R_RX_UNDER_VALUE_INACTIVE _u(0x0) -#define I2C_IC_INTR_STAT_R_RX_UNDER_VALUE_ACTIVE _u(0x1) -// ============================================================================= -// Register : I2C_IC_INTR_MASK -// Description : I2C Interrupt Mask Register. -// -// These bits mask their corresponding interrupt status bits. This -// register is active low; a value of 0 masks the interrupt, -// whereas a value of 1 unmasks the interrupt. -#define I2C_IC_INTR_MASK_OFFSET _u(0x00000030) -#define I2C_IC_INTR_MASK_BITS _u(0x00001fff) -#define I2C_IC_INTR_MASK_RESET _u(0x000008ff) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_INTR_MASK_M_RESTART_DET -// Description : This bit masks the R_RESTART_DET interrupt in IC_INTR_STAT -// register. -// -// Reset value: 0x0 -// 0x0 -> RESTART_DET interrupt is masked -// 0x1 -> RESTART_DET interrupt is unmasked -#define I2C_IC_INTR_MASK_M_RESTART_DET_RESET _u(0x0) -#define I2C_IC_INTR_MASK_M_RESTART_DET_BITS _u(0x00001000) -#define I2C_IC_INTR_MASK_M_RESTART_DET_MSB _u(12) -#define I2C_IC_INTR_MASK_M_RESTART_DET_LSB _u(12) -#define I2C_IC_INTR_MASK_M_RESTART_DET_ACCESS "RW" -#define I2C_IC_INTR_MASK_M_RESTART_DET_VALUE_ENABLED _u(0x0) -#define I2C_IC_INTR_MASK_M_RESTART_DET_VALUE_DISABLED _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_INTR_MASK_M_GEN_CALL -// Description : This bit masks the R_GEN_CALL interrupt in IC_INTR_STAT -// register. -// -// Reset value: 0x1 -// 0x0 -> GEN_CALL interrupt is masked -// 0x1 -> GEN_CALL interrupt is unmasked -#define I2C_IC_INTR_MASK_M_GEN_CALL_RESET _u(0x1) -#define I2C_IC_INTR_MASK_M_GEN_CALL_BITS _u(0x00000800) -#define I2C_IC_INTR_MASK_M_GEN_CALL_MSB _u(11) -#define I2C_IC_INTR_MASK_M_GEN_CALL_LSB _u(11) -#define I2C_IC_INTR_MASK_M_GEN_CALL_ACCESS "RW" -#define I2C_IC_INTR_MASK_M_GEN_CALL_VALUE_ENABLED _u(0x0) -#define I2C_IC_INTR_MASK_M_GEN_CALL_VALUE_DISABLED _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_INTR_MASK_M_START_DET -// Description : This bit masks the R_START_DET interrupt in IC_INTR_STAT -// register. -// -// Reset value: 0x0 -// 0x0 -> START_DET interrupt is masked -// 0x1 -> START_DET interrupt is unmasked -#define I2C_IC_INTR_MASK_M_START_DET_RESET _u(0x0) -#define I2C_IC_INTR_MASK_M_START_DET_BITS _u(0x00000400) -#define I2C_IC_INTR_MASK_M_START_DET_MSB _u(10) -#define I2C_IC_INTR_MASK_M_START_DET_LSB _u(10) -#define I2C_IC_INTR_MASK_M_START_DET_ACCESS "RW" -#define I2C_IC_INTR_MASK_M_START_DET_VALUE_ENABLED _u(0x0) -#define I2C_IC_INTR_MASK_M_START_DET_VALUE_DISABLED _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_INTR_MASK_M_STOP_DET -// Description : This bit masks the R_STOP_DET interrupt in IC_INTR_STAT -// register. -// -// Reset value: 0x0 -// 0x0 -> STOP_DET interrupt is masked -// 0x1 -> STOP_DET interrupt is unmasked -#define I2C_IC_INTR_MASK_M_STOP_DET_RESET _u(0x0) -#define I2C_IC_INTR_MASK_M_STOP_DET_BITS _u(0x00000200) -#define I2C_IC_INTR_MASK_M_STOP_DET_MSB _u(9) -#define I2C_IC_INTR_MASK_M_STOP_DET_LSB _u(9) -#define I2C_IC_INTR_MASK_M_STOP_DET_ACCESS "RW" -#define I2C_IC_INTR_MASK_M_STOP_DET_VALUE_ENABLED _u(0x0) -#define I2C_IC_INTR_MASK_M_STOP_DET_VALUE_DISABLED _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_INTR_MASK_M_ACTIVITY -// Description : This bit masks the R_ACTIVITY interrupt in IC_INTR_STAT -// register. -// -// Reset value: 0x0 -// 0x0 -> ACTIVITY interrupt is masked -// 0x1 -> ACTIVITY interrupt is unmasked -#define I2C_IC_INTR_MASK_M_ACTIVITY_RESET _u(0x0) -#define I2C_IC_INTR_MASK_M_ACTIVITY_BITS _u(0x00000100) -#define I2C_IC_INTR_MASK_M_ACTIVITY_MSB _u(8) -#define I2C_IC_INTR_MASK_M_ACTIVITY_LSB _u(8) -#define I2C_IC_INTR_MASK_M_ACTIVITY_ACCESS "RW" -#define I2C_IC_INTR_MASK_M_ACTIVITY_VALUE_ENABLED _u(0x0) -#define I2C_IC_INTR_MASK_M_ACTIVITY_VALUE_DISABLED _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_INTR_MASK_M_RX_DONE -// Description : This bit masks the R_RX_DONE interrupt in IC_INTR_STAT -// register. -// -// Reset value: 0x1 -// 0x0 -> RX_DONE interrupt is masked -// 0x1 -> RX_DONE interrupt is unmasked -#define I2C_IC_INTR_MASK_M_RX_DONE_RESET _u(0x1) -#define I2C_IC_INTR_MASK_M_RX_DONE_BITS _u(0x00000080) -#define I2C_IC_INTR_MASK_M_RX_DONE_MSB _u(7) -#define I2C_IC_INTR_MASK_M_RX_DONE_LSB _u(7) -#define I2C_IC_INTR_MASK_M_RX_DONE_ACCESS "RW" -#define I2C_IC_INTR_MASK_M_RX_DONE_VALUE_ENABLED _u(0x0) -#define I2C_IC_INTR_MASK_M_RX_DONE_VALUE_DISABLED _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_INTR_MASK_M_TX_ABRT -// Description : This bit masks the R_TX_ABRT interrupt in IC_INTR_STAT -// register. -// -// Reset value: 0x1 -// 0x0 -> TX_ABORT interrupt is masked -// 0x1 -> TX_ABORT interrupt is unmasked -#define I2C_IC_INTR_MASK_M_TX_ABRT_RESET _u(0x1) -#define I2C_IC_INTR_MASK_M_TX_ABRT_BITS _u(0x00000040) -#define I2C_IC_INTR_MASK_M_TX_ABRT_MSB _u(6) -#define I2C_IC_INTR_MASK_M_TX_ABRT_LSB _u(6) -#define I2C_IC_INTR_MASK_M_TX_ABRT_ACCESS "RW" -#define I2C_IC_INTR_MASK_M_TX_ABRT_VALUE_ENABLED _u(0x0) -#define I2C_IC_INTR_MASK_M_TX_ABRT_VALUE_DISABLED _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_INTR_MASK_M_RD_REQ -// Description : This bit masks the R_RD_REQ interrupt in IC_INTR_STAT register. -// -// Reset value: 0x1 -// 0x0 -> RD_REQ interrupt is masked -// 0x1 -> RD_REQ interrupt is unmasked -#define I2C_IC_INTR_MASK_M_RD_REQ_RESET _u(0x1) -#define I2C_IC_INTR_MASK_M_RD_REQ_BITS _u(0x00000020) -#define I2C_IC_INTR_MASK_M_RD_REQ_MSB _u(5) -#define I2C_IC_INTR_MASK_M_RD_REQ_LSB _u(5) -#define I2C_IC_INTR_MASK_M_RD_REQ_ACCESS "RW" -#define I2C_IC_INTR_MASK_M_RD_REQ_VALUE_ENABLED _u(0x0) -#define I2C_IC_INTR_MASK_M_RD_REQ_VALUE_DISABLED _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_INTR_MASK_M_TX_EMPTY -// Description : This bit masks the R_TX_EMPTY interrupt in IC_INTR_STAT -// register. -// -// Reset value: 0x1 -// 0x0 -> TX_EMPTY interrupt is masked -// 0x1 -> TX_EMPTY interrupt is unmasked -#define I2C_IC_INTR_MASK_M_TX_EMPTY_RESET _u(0x1) -#define I2C_IC_INTR_MASK_M_TX_EMPTY_BITS _u(0x00000010) -#define I2C_IC_INTR_MASK_M_TX_EMPTY_MSB _u(4) -#define I2C_IC_INTR_MASK_M_TX_EMPTY_LSB _u(4) -#define I2C_IC_INTR_MASK_M_TX_EMPTY_ACCESS "RW" -#define I2C_IC_INTR_MASK_M_TX_EMPTY_VALUE_ENABLED _u(0x0) -#define I2C_IC_INTR_MASK_M_TX_EMPTY_VALUE_DISABLED _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_INTR_MASK_M_TX_OVER -// Description : This bit masks the R_TX_OVER interrupt in IC_INTR_STAT -// register. -// -// Reset value: 0x1 -// 0x0 -> TX_OVER interrupt is masked -// 0x1 -> TX_OVER interrupt is unmasked -#define I2C_IC_INTR_MASK_M_TX_OVER_RESET _u(0x1) -#define I2C_IC_INTR_MASK_M_TX_OVER_BITS _u(0x00000008) -#define I2C_IC_INTR_MASK_M_TX_OVER_MSB _u(3) -#define I2C_IC_INTR_MASK_M_TX_OVER_LSB _u(3) -#define I2C_IC_INTR_MASK_M_TX_OVER_ACCESS "RW" -#define I2C_IC_INTR_MASK_M_TX_OVER_VALUE_ENABLED _u(0x0) -#define I2C_IC_INTR_MASK_M_TX_OVER_VALUE_DISABLED _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_INTR_MASK_M_RX_FULL -// Description : This bit masks the R_RX_FULL interrupt in IC_INTR_STAT -// register. -// -// Reset value: 0x1 -// 0x0 -> RX_FULL interrupt is masked -// 0x1 -> RX_FULL interrupt is unmasked -#define I2C_IC_INTR_MASK_M_RX_FULL_RESET _u(0x1) -#define I2C_IC_INTR_MASK_M_RX_FULL_BITS _u(0x00000004) -#define I2C_IC_INTR_MASK_M_RX_FULL_MSB _u(2) -#define I2C_IC_INTR_MASK_M_RX_FULL_LSB _u(2) -#define I2C_IC_INTR_MASK_M_RX_FULL_ACCESS "RW" -#define I2C_IC_INTR_MASK_M_RX_FULL_VALUE_ENABLED _u(0x0) -#define I2C_IC_INTR_MASK_M_RX_FULL_VALUE_DISABLED _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_INTR_MASK_M_RX_OVER -// Description : This bit masks the R_RX_OVER interrupt in IC_INTR_STAT -// register. -// -// Reset value: 0x1 -// 0x0 -> RX_OVER interrupt is masked -// 0x1 -> RX_OVER interrupt is unmasked -#define I2C_IC_INTR_MASK_M_RX_OVER_RESET _u(0x1) -#define I2C_IC_INTR_MASK_M_RX_OVER_BITS _u(0x00000002) -#define I2C_IC_INTR_MASK_M_RX_OVER_MSB _u(1) -#define I2C_IC_INTR_MASK_M_RX_OVER_LSB _u(1) -#define I2C_IC_INTR_MASK_M_RX_OVER_ACCESS "RW" -#define I2C_IC_INTR_MASK_M_RX_OVER_VALUE_ENABLED _u(0x0) -#define I2C_IC_INTR_MASK_M_RX_OVER_VALUE_DISABLED _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_INTR_MASK_M_RX_UNDER -// Description : This bit masks the R_RX_UNDER interrupt in IC_INTR_STAT -// register. -// -// Reset value: 0x1 -// 0x0 -> RX_UNDER interrupt is masked -// 0x1 -> RX_UNDER interrupt is unmasked -#define I2C_IC_INTR_MASK_M_RX_UNDER_RESET _u(0x1) -#define I2C_IC_INTR_MASK_M_RX_UNDER_BITS _u(0x00000001) -#define I2C_IC_INTR_MASK_M_RX_UNDER_MSB _u(0) -#define I2C_IC_INTR_MASK_M_RX_UNDER_LSB _u(0) -#define I2C_IC_INTR_MASK_M_RX_UNDER_ACCESS "RW" -#define I2C_IC_INTR_MASK_M_RX_UNDER_VALUE_ENABLED _u(0x0) -#define I2C_IC_INTR_MASK_M_RX_UNDER_VALUE_DISABLED _u(0x1) -// ============================================================================= -// Register : I2C_IC_RAW_INTR_STAT -// Description : I2C Raw Interrupt Status Register -// -// Unlike the IC_INTR_STAT register, these bits are not masked so -// they always show the true status of the DW_apb_i2c. -#define I2C_IC_RAW_INTR_STAT_OFFSET _u(0x00000034) -#define I2C_IC_RAW_INTR_STAT_BITS _u(0x00001fff) -#define I2C_IC_RAW_INTR_STAT_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_RAW_INTR_STAT_RESTART_DET -// Description : Indicates whether a RESTART condition has occurred on the I2C -// interface when DW_apb_i2c is operating in Slave mode and the -// slave is being addressed. Enabled only when -// IC_SLV_RESTART_DET_EN=1. -// -// Note: However, in high-speed mode or during a START BYTE -// transfer, the RESTART comes before the address field as per the -// I2C protocol. In this case, the slave is not the addressed -// slave when the RESTART is issued, therefore DW_apb_i2c does not -// generate the RESTART_DET interrupt. -// -// Reset value: 0x0 -// 0x0 -> RESTART_DET interrupt is inactive -// 0x1 -> RESTART_DET interrupt is active -#define I2C_IC_RAW_INTR_STAT_RESTART_DET_RESET _u(0x0) -#define I2C_IC_RAW_INTR_STAT_RESTART_DET_BITS _u(0x00001000) -#define I2C_IC_RAW_INTR_STAT_RESTART_DET_MSB _u(12) -#define I2C_IC_RAW_INTR_STAT_RESTART_DET_LSB _u(12) -#define I2C_IC_RAW_INTR_STAT_RESTART_DET_ACCESS "RO" -#define I2C_IC_RAW_INTR_STAT_RESTART_DET_VALUE_INACTIVE _u(0x0) -#define I2C_IC_RAW_INTR_STAT_RESTART_DET_VALUE_ACTIVE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_RAW_INTR_STAT_GEN_CALL -// Description : Set only when a General Call address is received and it is -// acknowledged. It stays set until it is cleared either by -// disabling DW_apb_i2c or when the CPU reads bit 0 of the -// IC_CLR_GEN_CALL register. DW_apb_i2c stores the received data -// in the Rx buffer. -// -// Reset value: 0x0 -// 0x0 -> GEN_CALL interrupt is inactive -// 0x1 -> GEN_CALL interrupt is active -#define I2C_IC_RAW_INTR_STAT_GEN_CALL_RESET _u(0x0) -#define I2C_IC_RAW_INTR_STAT_GEN_CALL_BITS _u(0x00000800) -#define I2C_IC_RAW_INTR_STAT_GEN_CALL_MSB _u(11) -#define I2C_IC_RAW_INTR_STAT_GEN_CALL_LSB _u(11) -#define I2C_IC_RAW_INTR_STAT_GEN_CALL_ACCESS "RO" -#define I2C_IC_RAW_INTR_STAT_GEN_CALL_VALUE_INACTIVE _u(0x0) -#define I2C_IC_RAW_INTR_STAT_GEN_CALL_VALUE_ACTIVE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_RAW_INTR_STAT_START_DET -// Description : Indicates whether a START or RESTART condition has occurred on -// the I2C interface regardless of whether DW_apb_i2c is operating -// in slave or master mode. -// -// Reset value: 0x0 -// 0x0 -> START_DET interrupt is inactive -// 0x1 -> START_DET interrupt is active -#define I2C_IC_RAW_INTR_STAT_START_DET_RESET _u(0x0) -#define I2C_IC_RAW_INTR_STAT_START_DET_BITS _u(0x00000400) -#define I2C_IC_RAW_INTR_STAT_START_DET_MSB _u(10) -#define I2C_IC_RAW_INTR_STAT_START_DET_LSB _u(10) -#define I2C_IC_RAW_INTR_STAT_START_DET_ACCESS "RO" -#define I2C_IC_RAW_INTR_STAT_START_DET_VALUE_INACTIVE _u(0x0) -#define I2C_IC_RAW_INTR_STAT_START_DET_VALUE_ACTIVE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_RAW_INTR_STAT_STOP_DET -// Description : Indicates whether a STOP condition has occurred on the I2C -// interface regardless of whether DW_apb_i2c is operating in -// slave or master mode. -// -// In Slave Mode: - If IC_CON[7]=1'b1 (STOP_DET_IFADDRESSED), the -// STOP_DET interrupt will be issued only if slave is addressed. -// Note: During a general call address, this slave does not issue -// a STOP_DET interrupt if STOP_DET_IF_ADDRESSED=1'b1, even if the -// slave responds to the general call address by generating ACK. -// The STOP_DET interrupt is generated only when the transmitted -// address matches the slave address (SAR). - If IC_CON[7]=1'b0 -// (STOP_DET_IFADDRESSED), the STOP_DET interrupt is issued -// irrespective of whether it is being addressed. In Master Mode: -// - If IC_CON[10]=1'b1 (STOP_DET_IF_MASTER_ACTIVE),the STOP_DET -// interrupt will be issued only if Master is active. - If -// IC_CON[10]=1'b0 (STOP_DET_IFADDRESSED),the STOP_DET interrupt -// will be issued irrespective of whether master is active or not. -// Reset value: 0x0 -// 0x0 -> STOP_DET interrupt is inactive -// 0x1 -> STOP_DET interrupt is active -#define I2C_IC_RAW_INTR_STAT_STOP_DET_RESET _u(0x0) -#define I2C_IC_RAW_INTR_STAT_STOP_DET_BITS _u(0x00000200) -#define I2C_IC_RAW_INTR_STAT_STOP_DET_MSB _u(9) -#define I2C_IC_RAW_INTR_STAT_STOP_DET_LSB _u(9) -#define I2C_IC_RAW_INTR_STAT_STOP_DET_ACCESS "RO" -#define I2C_IC_RAW_INTR_STAT_STOP_DET_VALUE_INACTIVE _u(0x0) -#define I2C_IC_RAW_INTR_STAT_STOP_DET_VALUE_ACTIVE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_RAW_INTR_STAT_ACTIVITY -// Description : This bit captures DW_apb_i2c activity and stays set until it is -// cleared. There are four ways to clear it: - Disabling the -// DW_apb_i2c - Reading the IC_CLR_ACTIVITY register - Reading the -// IC_CLR_INTR register - System reset Once this bit is set, it -// stays set unless one of the four methods is used to clear it. -// Even if the DW_apb_i2c module is idle, this bit remains set -// until cleared, indicating that there was activity on the bus. -// -// Reset value: 0x0 -// 0x0 -> RAW_INTR_ACTIVITY interrupt is inactive -// 0x1 -> RAW_INTR_ACTIVITY interrupt is active -#define I2C_IC_RAW_INTR_STAT_ACTIVITY_RESET _u(0x0) -#define I2C_IC_RAW_INTR_STAT_ACTIVITY_BITS _u(0x00000100) -#define I2C_IC_RAW_INTR_STAT_ACTIVITY_MSB _u(8) -#define I2C_IC_RAW_INTR_STAT_ACTIVITY_LSB _u(8) -#define I2C_IC_RAW_INTR_STAT_ACTIVITY_ACCESS "RO" -#define I2C_IC_RAW_INTR_STAT_ACTIVITY_VALUE_INACTIVE _u(0x0) -#define I2C_IC_RAW_INTR_STAT_ACTIVITY_VALUE_ACTIVE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_RAW_INTR_STAT_RX_DONE -// Description : When the DW_apb_i2c is acting as a slave-transmitter, this bit -// is set to 1 if the master does not acknowledge a transmitted -// byte. This occurs on the last byte of the transmission, -// indicating that the transmission is done. -// -// Reset value: 0x0 -// 0x0 -> RX_DONE interrupt is inactive -// 0x1 -> RX_DONE interrupt is active -#define I2C_IC_RAW_INTR_STAT_RX_DONE_RESET _u(0x0) -#define I2C_IC_RAW_INTR_STAT_RX_DONE_BITS _u(0x00000080) -#define I2C_IC_RAW_INTR_STAT_RX_DONE_MSB _u(7) -#define I2C_IC_RAW_INTR_STAT_RX_DONE_LSB _u(7) -#define I2C_IC_RAW_INTR_STAT_RX_DONE_ACCESS "RO" -#define I2C_IC_RAW_INTR_STAT_RX_DONE_VALUE_INACTIVE _u(0x0) -#define I2C_IC_RAW_INTR_STAT_RX_DONE_VALUE_ACTIVE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_RAW_INTR_STAT_TX_ABRT -// Description : This bit indicates if DW_apb_i2c, as an I2C transmitter, is -// unable to complete the intended actions on the contents of the -// transmit FIFO. This situation can occur both as an I2C master -// or an I2C slave, and is referred to as a 'transmit abort'. When -// this bit is set to 1, the IC_TX_ABRT_SOURCE register indicates -// the reason why the transmit abort takes places. -// -// Note: The DW_apb_i2c flushes/resets/empties the TX_FIFO and -// RX_FIFO whenever there is a transmit abort caused by any of the -// events tracked by the IC_TX_ABRT_SOURCE register. The FIFOs -// remains in this flushed state until the register IC_CLR_TX_ABRT -// is read. Once this read is performed, the Tx FIFO is then ready -// to accept more data bytes from the APB interface. -// -// Reset value: 0x0 -// 0x0 -> TX_ABRT interrupt is inactive -// 0x1 -> TX_ABRT interrupt is active -#define I2C_IC_RAW_INTR_STAT_TX_ABRT_RESET _u(0x0) -#define I2C_IC_RAW_INTR_STAT_TX_ABRT_BITS _u(0x00000040) -#define I2C_IC_RAW_INTR_STAT_TX_ABRT_MSB _u(6) -#define I2C_IC_RAW_INTR_STAT_TX_ABRT_LSB _u(6) -#define I2C_IC_RAW_INTR_STAT_TX_ABRT_ACCESS "RO" -#define I2C_IC_RAW_INTR_STAT_TX_ABRT_VALUE_INACTIVE _u(0x0) -#define I2C_IC_RAW_INTR_STAT_TX_ABRT_VALUE_ACTIVE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_RAW_INTR_STAT_RD_REQ -// Description : This bit is set to 1 when DW_apb_i2c is acting as a slave and -// another I2C master is attempting to read data from DW_apb_i2c. -// The DW_apb_i2c holds the I2C bus in a wait state (SCL=0) until -// this interrupt is serviced, which means that the slave has been -// addressed by a remote master that is asking for data to be -// transferred. The processor must respond to this interrupt and -// then write the requested data to the IC_DATA_CMD register. This -// bit is set to 0 just after the processor reads the -// IC_CLR_RD_REQ register. -// -// Reset value: 0x0 -// 0x0 -> RD_REQ interrupt is inactive -// 0x1 -> RD_REQ interrupt is active -#define I2C_IC_RAW_INTR_STAT_RD_REQ_RESET _u(0x0) -#define I2C_IC_RAW_INTR_STAT_RD_REQ_BITS _u(0x00000020) -#define I2C_IC_RAW_INTR_STAT_RD_REQ_MSB _u(5) -#define I2C_IC_RAW_INTR_STAT_RD_REQ_LSB _u(5) -#define I2C_IC_RAW_INTR_STAT_RD_REQ_ACCESS "RO" -#define I2C_IC_RAW_INTR_STAT_RD_REQ_VALUE_INACTIVE _u(0x0) -#define I2C_IC_RAW_INTR_STAT_RD_REQ_VALUE_ACTIVE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_RAW_INTR_STAT_TX_EMPTY -// Description : The behavior of the TX_EMPTY interrupt status differs based on -// the TX_EMPTY_CTRL selection in the IC_CON register. - When -// TX_EMPTY_CTRL = 0: This bit is set to 1 when the transmit -// buffer is at or below the threshold value set in the IC_TX_TL -// register. - When TX_EMPTY_CTRL = 1: This bit is set to 1 when -// the transmit buffer is at or below the threshold value set in -// the IC_TX_TL register and the transmission of the address/data -// from the internal shift register for the most recently popped -// command is completed. It is automatically cleared by hardware -// when the buffer level goes above the threshold. When -// IC_ENABLE[0] is set to 0, the TX FIFO is flushed and held in -// reset. There the TX FIFO looks like it has no data within it, -// so this bit is set to 1, provided there is activity in the -// master or slave state machines. When there is no longer any -// activity, then with ic_en=0, this bit is set to 0. -// -// Reset value: 0x0. -// 0x0 -> TX_EMPTY interrupt is inactive -// 0x1 -> TX_EMPTY interrupt is active -#define I2C_IC_RAW_INTR_STAT_TX_EMPTY_RESET _u(0x0) -#define I2C_IC_RAW_INTR_STAT_TX_EMPTY_BITS _u(0x00000010) -#define I2C_IC_RAW_INTR_STAT_TX_EMPTY_MSB _u(4) -#define I2C_IC_RAW_INTR_STAT_TX_EMPTY_LSB _u(4) -#define I2C_IC_RAW_INTR_STAT_TX_EMPTY_ACCESS "RO" -#define I2C_IC_RAW_INTR_STAT_TX_EMPTY_VALUE_INACTIVE _u(0x0) -#define I2C_IC_RAW_INTR_STAT_TX_EMPTY_VALUE_ACTIVE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_RAW_INTR_STAT_TX_OVER -// Description : Set during transmit if the transmit buffer is filled to -// IC_TX_BUFFER_DEPTH and the processor attempts to issue another -// I2C command by writing to the IC_DATA_CMD register. When the -// module is disabled, this bit keeps its level until the master -// or slave state machines go into idle, and when ic_en goes to 0, -// this interrupt is cleared. -// -// Reset value: 0x0 -// 0x0 -> TX_OVER interrupt is inactive -// 0x1 -> TX_OVER interrupt is active -#define I2C_IC_RAW_INTR_STAT_TX_OVER_RESET _u(0x0) -#define I2C_IC_RAW_INTR_STAT_TX_OVER_BITS _u(0x00000008) -#define I2C_IC_RAW_INTR_STAT_TX_OVER_MSB _u(3) -#define I2C_IC_RAW_INTR_STAT_TX_OVER_LSB _u(3) -#define I2C_IC_RAW_INTR_STAT_TX_OVER_ACCESS "RO" -#define I2C_IC_RAW_INTR_STAT_TX_OVER_VALUE_INACTIVE _u(0x0) -#define I2C_IC_RAW_INTR_STAT_TX_OVER_VALUE_ACTIVE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_RAW_INTR_STAT_RX_FULL -// Description : Set when the receive buffer reaches or goes above the RX_TL -// threshold in the IC_RX_TL register. It is automatically cleared -// by hardware when buffer level goes below the threshold. If the -// module is disabled (IC_ENABLE[0]=0), the RX FIFO is flushed and -// held in reset; therefore the RX FIFO is not full. So this bit -// is cleared once the IC_ENABLE bit 0 is programmed with a 0, -// regardless of the activity that continues. -// -// Reset value: 0x0 -// 0x0 -> RX_FULL interrupt is inactive -// 0x1 -> RX_FULL interrupt is active -#define I2C_IC_RAW_INTR_STAT_RX_FULL_RESET _u(0x0) -#define I2C_IC_RAW_INTR_STAT_RX_FULL_BITS _u(0x00000004) -#define I2C_IC_RAW_INTR_STAT_RX_FULL_MSB _u(2) -#define I2C_IC_RAW_INTR_STAT_RX_FULL_LSB _u(2) -#define I2C_IC_RAW_INTR_STAT_RX_FULL_ACCESS "RO" -#define I2C_IC_RAW_INTR_STAT_RX_FULL_VALUE_INACTIVE _u(0x0) -#define I2C_IC_RAW_INTR_STAT_RX_FULL_VALUE_ACTIVE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_RAW_INTR_STAT_RX_OVER -// Description : Set if the receive buffer is completely filled to -// IC_RX_BUFFER_DEPTH and an additional byte is received from an -// external I2C device. The DW_apb_i2c acknowledges this, but any -// data bytes received after the FIFO is full are lost. If the -// module is disabled (IC_ENABLE[0]=0), this bit keeps its level -// until the master or slave state machines go into idle, and when -// ic_en goes to 0, this interrupt is cleared. -// -// Note: If bit 9 of the IC_CON register (RX_FIFO_FULL_HLD_CTRL) -// is programmed to HIGH, then the RX_OVER interrupt never occurs, -// because the Rx FIFO never overflows. -// -// Reset value: 0x0 -// 0x0 -> RX_OVER interrupt is inactive -// 0x1 -> RX_OVER interrupt is active -#define I2C_IC_RAW_INTR_STAT_RX_OVER_RESET _u(0x0) -#define I2C_IC_RAW_INTR_STAT_RX_OVER_BITS _u(0x00000002) -#define I2C_IC_RAW_INTR_STAT_RX_OVER_MSB _u(1) -#define I2C_IC_RAW_INTR_STAT_RX_OVER_LSB _u(1) -#define I2C_IC_RAW_INTR_STAT_RX_OVER_ACCESS "RO" -#define I2C_IC_RAW_INTR_STAT_RX_OVER_VALUE_INACTIVE _u(0x0) -#define I2C_IC_RAW_INTR_STAT_RX_OVER_VALUE_ACTIVE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_RAW_INTR_STAT_RX_UNDER -// Description : Set if the processor attempts to read the receive buffer when -// it is empty by reading from the IC_DATA_CMD register. If the -// module is disabled (IC_ENABLE[0]=0), this bit keeps its level -// until the master or slave state machines go into idle, and when -// ic_en goes to 0, this interrupt is cleared. -// -// Reset value: 0x0 -// 0x0 -> RX_UNDER interrupt is inactive -// 0x1 -> RX_UNDER interrupt is active -#define I2C_IC_RAW_INTR_STAT_RX_UNDER_RESET _u(0x0) -#define I2C_IC_RAW_INTR_STAT_RX_UNDER_BITS _u(0x00000001) -#define I2C_IC_RAW_INTR_STAT_RX_UNDER_MSB _u(0) -#define I2C_IC_RAW_INTR_STAT_RX_UNDER_LSB _u(0) -#define I2C_IC_RAW_INTR_STAT_RX_UNDER_ACCESS "RO" -#define I2C_IC_RAW_INTR_STAT_RX_UNDER_VALUE_INACTIVE _u(0x0) -#define I2C_IC_RAW_INTR_STAT_RX_UNDER_VALUE_ACTIVE _u(0x1) -// ============================================================================= -// Register : I2C_IC_RX_TL -// Description : I2C Receive FIFO Threshold Register -#define I2C_IC_RX_TL_OFFSET _u(0x00000038) -#define I2C_IC_RX_TL_BITS _u(0x000000ff) -#define I2C_IC_RX_TL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_RX_TL_RX_TL -// Description : Receive FIFO Threshold Level. -// -// Controls the level of entries (or above) that triggers the -// RX_FULL interrupt (bit 2 in IC_RAW_INTR_STAT register). The -// valid range is 0-255, with the additional restriction that -// hardware does not allow this value to be set to a value larger -// than the depth of the buffer. If an attempt is made to do that, -// the actual value set will be the maximum depth of the buffer. A -// value of 0 sets the threshold for 1 entry, and a value of 255 -// sets the threshold for 256 entries. -#define I2C_IC_RX_TL_RX_TL_RESET _u(0x00) -#define I2C_IC_RX_TL_RX_TL_BITS _u(0x000000ff) -#define I2C_IC_RX_TL_RX_TL_MSB _u(7) -#define I2C_IC_RX_TL_RX_TL_LSB _u(0) -#define I2C_IC_RX_TL_RX_TL_ACCESS "RW" -// ============================================================================= -// Register : I2C_IC_TX_TL -// Description : I2C Transmit FIFO Threshold Register -#define I2C_IC_TX_TL_OFFSET _u(0x0000003c) -#define I2C_IC_TX_TL_BITS _u(0x000000ff) -#define I2C_IC_TX_TL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_TX_TL_TX_TL -// Description : Transmit FIFO Threshold Level. -// -// Controls the level of entries (or below) that trigger the -// TX_EMPTY interrupt (bit 4 in IC_RAW_INTR_STAT register). The -// valid range is 0-255, with the additional restriction that it -// may not be set to value larger than the depth of the buffer. If -// an attempt is made to do that, the actual value set will be the -// maximum depth of the buffer. A value of 0 sets the threshold -// for 0 entries, and a value of 255 sets the threshold for 255 -// entries. -#define I2C_IC_TX_TL_TX_TL_RESET _u(0x00) -#define I2C_IC_TX_TL_TX_TL_BITS _u(0x000000ff) -#define I2C_IC_TX_TL_TX_TL_MSB _u(7) -#define I2C_IC_TX_TL_TX_TL_LSB _u(0) -#define I2C_IC_TX_TL_TX_TL_ACCESS "RW" -// ============================================================================= -// Register : I2C_IC_CLR_INTR -// Description : Clear Combined and Individual Interrupt Register -#define I2C_IC_CLR_INTR_OFFSET _u(0x00000040) -#define I2C_IC_CLR_INTR_BITS _u(0x00000001) -#define I2C_IC_CLR_INTR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_CLR_INTR_CLR_INTR -// Description : Read this register to clear the combined interrupt, all -// individual interrupts, and the IC_TX_ABRT_SOURCE register. This -// bit does not clear hardware clearable interrupts but software -// clearable interrupts. Refer to Bit 9 of the IC_TX_ABRT_SOURCE -// register for an exception to clearing IC_TX_ABRT_SOURCE. -// -// Reset value: 0x0 -#define I2C_IC_CLR_INTR_CLR_INTR_RESET _u(0x0) -#define I2C_IC_CLR_INTR_CLR_INTR_BITS _u(0x00000001) -#define I2C_IC_CLR_INTR_CLR_INTR_MSB _u(0) -#define I2C_IC_CLR_INTR_CLR_INTR_LSB _u(0) -#define I2C_IC_CLR_INTR_CLR_INTR_ACCESS "RO" -// ============================================================================= -// Register : I2C_IC_CLR_RX_UNDER -// Description : Clear RX_UNDER Interrupt Register -#define I2C_IC_CLR_RX_UNDER_OFFSET _u(0x00000044) -#define I2C_IC_CLR_RX_UNDER_BITS _u(0x00000001) -#define I2C_IC_CLR_RX_UNDER_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_CLR_RX_UNDER_CLR_RX_UNDER -// Description : Read this register to clear the RX_UNDER interrupt (bit 0) of -// the IC_RAW_INTR_STAT register. -// -// Reset value: 0x0 -#define I2C_IC_CLR_RX_UNDER_CLR_RX_UNDER_RESET _u(0x0) -#define I2C_IC_CLR_RX_UNDER_CLR_RX_UNDER_BITS _u(0x00000001) -#define I2C_IC_CLR_RX_UNDER_CLR_RX_UNDER_MSB _u(0) -#define I2C_IC_CLR_RX_UNDER_CLR_RX_UNDER_LSB _u(0) -#define I2C_IC_CLR_RX_UNDER_CLR_RX_UNDER_ACCESS "RO" -// ============================================================================= -// Register : I2C_IC_CLR_RX_OVER -// Description : Clear RX_OVER Interrupt Register -#define I2C_IC_CLR_RX_OVER_OFFSET _u(0x00000048) -#define I2C_IC_CLR_RX_OVER_BITS _u(0x00000001) -#define I2C_IC_CLR_RX_OVER_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_CLR_RX_OVER_CLR_RX_OVER -// Description : Read this register to clear the RX_OVER interrupt (bit 1) of -// the IC_RAW_INTR_STAT register. -// -// Reset value: 0x0 -#define I2C_IC_CLR_RX_OVER_CLR_RX_OVER_RESET _u(0x0) -#define I2C_IC_CLR_RX_OVER_CLR_RX_OVER_BITS _u(0x00000001) -#define I2C_IC_CLR_RX_OVER_CLR_RX_OVER_MSB _u(0) -#define I2C_IC_CLR_RX_OVER_CLR_RX_OVER_LSB _u(0) -#define I2C_IC_CLR_RX_OVER_CLR_RX_OVER_ACCESS "RO" -// ============================================================================= -// Register : I2C_IC_CLR_TX_OVER -// Description : Clear TX_OVER Interrupt Register -#define I2C_IC_CLR_TX_OVER_OFFSET _u(0x0000004c) -#define I2C_IC_CLR_TX_OVER_BITS _u(0x00000001) -#define I2C_IC_CLR_TX_OVER_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_CLR_TX_OVER_CLR_TX_OVER -// Description : Read this register to clear the TX_OVER interrupt (bit 3) of -// the IC_RAW_INTR_STAT register. -// -// Reset value: 0x0 -#define I2C_IC_CLR_TX_OVER_CLR_TX_OVER_RESET _u(0x0) -#define I2C_IC_CLR_TX_OVER_CLR_TX_OVER_BITS _u(0x00000001) -#define I2C_IC_CLR_TX_OVER_CLR_TX_OVER_MSB _u(0) -#define I2C_IC_CLR_TX_OVER_CLR_TX_OVER_LSB _u(0) -#define I2C_IC_CLR_TX_OVER_CLR_TX_OVER_ACCESS "RO" -// ============================================================================= -// Register : I2C_IC_CLR_RD_REQ -// Description : Clear RD_REQ Interrupt Register -#define I2C_IC_CLR_RD_REQ_OFFSET _u(0x00000050) -#define I2C_IC_CLR_RD_REQ_BITS _u(0x00000001) -#define I2C_IC_CLR_RD_REQ_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_CLR_RD_REQ_CLR_RD_REQ -// Description : Read this register to clear the RD_REQ interrupt (bit 5) of the -// IC_RAW_INTR_STAT register. -// -// Reset value: 0x0 -#define I2C_IC_CLR_RD_REQ_CLR_RD_REQ_RESET _u(0x0) -#define I2C_IC_CLR_RD_REQ_CLR_RD_REQ_BITS _u(0x00000001) -#define I2C_IC_CLR_RD_REQ_CLR_RD_REQ_MSB _u(0) -#define I2C_IC_CLR_RD_REQ_CLR_RD_REQ_LSB _u(0) -#define I2C_IC_CLR_RD_REQ_CLR_RD_REQ_ACCESS "RO" -// ============================================================================= -// Register : I2C_IC_CLR_TX_ABRT -// Description : Clear TX_ABRT Interrupt Register -#define I2C_IC_CLR_TX_ABRT_OFFSET _u(0x00000054) -#define I2C_IC_CLR_TX_ABRT_BITS _u(0x00000001) -#define I2C_IC_CLR_TX_ABRT_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_CLR_TX_ABRT_CLR_TX_ABRT -// Description : Read this register to clear the TX_ABRT interrupt (bit 6) of -// the IC_RAW_INTR_STAT register, and the IC_TX_ABRT_SOURCE -// register. This also releases the TX FIFO from the flushed/reset -// state, allowing more writes to the TX FIFO. Refer to Bit 9 of -// the IC_TX_ABRT_SOURCE register for an exception to clearing -// IC_TX_ABRT_SOURCE. -// -// Reset value: 0x0 -#define I2C_IC_CLR_TX_ABRT_CLR_TX_ABRT_RESET _u(0x0) -#define I2C_IC_CLR_TX_ABRT_CLR_TX_ABRT_BITS _u(0x00000001) -#define I2C_IC_CLR_TX_ABRT_CLR_TX_ABRT_MSB _u(0) -#define I2C_IC_CLR_TX_ABRT_CLR_TX_ABRT_LSB _u(0) -#define I2C_IC_CLR_TX_ABRT_CLR_TX_ABRT_ACCESS "RO" -// ============================================================================= -// Register : I2C_IC_CLR_RX_DONE -// Description : Clear RX_DONE Interrupt Register -#define I2C_IC_CLR_RX_DONE_OFFSET _u(0x00000058) -#define I2C_IC_CLR_RX_DONE_BITS _u(0x00000001) -#define I2C_IC_CLR_RX_DONE_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_CLR_RX_DONE_CLR_RX_DONE -// Description : Read this register to clear the RX_DONE interrupt (bit 7) of -// the IC_RAW_INTR_STAT register. -// -// Reset value: 0x0 -#define I2C_IC_CLR_RX_DONE_CLR_RX_DONE_RESET _u(0x0) -#define I2C_IC_CLR_RX_DONE_CLR_RX_DONE_BITS _u(0x00000001) -#define I2C_IC_CLR_RX_DONE_CLR_RX_DONE_MSB _u(0) -#define I2C_IC_CLR_RX_DONE_CLR_RX_DONE_LSB _u(0) -#define I2C_IC_CLR_RX_DONE_CLR_RX_DONE_ACCESS "RO" -// ============================================================================= -// Register : I2C_IC_CLR_ACTIVITY -// Description : Clear ACTIVITY Interrupt Register -#define I2C_IC_CLR_ACTIVITY_OFFSET _u(0x0000005c) -#define I2C_IC_CLR_ACTIVITY_BITS _u(0x00000001) -#define I2C_IC_CLR_ACTIVITY_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_CLR_ACTIVITY_CLR_ACTIVITY -// Description : Reading this register clears the ACTIVITY interrupt if the I2C -// is not active anymore. If the I2C module is still active on the -// bus, the ACTIVITY interrupt bit continues to be set. It is -// automatically cleared by hardware if the module is disabled and -// if there is no further activity on the bus. The value read from -// this register to get status of the ACTIVITY interrupt (bit 8) -// of the IC_RAW_INTR_STAT register. -// -// Reset value: 0x0 -#define I2C_IC_CLR_ACTIVITY_CLR_ACTIVITY_RESET _u(0x0) -#define I2C_IC_CLR_ACTIVITY_CLR_ACTIVITY_BITS _u(0x00000001) -#define I2C_IC_CLR_ACTIVITY_CLR_ACTIVITY_MSB _u(0) -#define I2C_IC_CLR_ACTIVITY_CLR_ACTIVITY_LSB _u(0) -#define I2C_IC_CLR_ACTIVITY_CLR_ACTIVITY_ACCESS "RO" -// ============================================================================= -// Register : I2C_IC_CLR_STOP_DET -// Description : Clear STOP_DET Interrupt Register -#define I2C_IC_CLR_STOP_DET_OFFSET _u(0x00000060) -#define I2C_IC_CLR_STOP_DET_BITS _u(0x00000001) -#define I2C_IC_CLR_STOP_DET_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_CLR_STOP_DET_CLR_STOP_DET -// Description : Read this register to clear the STOP_DET interrupt (bit 9) of -// the IC_RAW_INTR_STAT register. -// -// Reset value: 0x0 -#define I2C_IC_CLR_STOP_DET_CLR_STOP_DET_RESET _u(0x0) -#define I2C_IC_CLR_STOP_DET_CLR_STOP_DET_BITS _u(0x00000001) -#define I2C_IC_CLR_STOP_DET_CLR_STOP_DET_MSB _u(0) -#define I2C_IC_CLR_STOP_DET_CLR_STOP_DET_LSB _u(0) -#define I2C_IC_CLR_STOP_DET_CLR_STOP_DET_ACCESS "RO" -// ============================================================================= -// Register : I2C_IC_CLR_START_DET -// Description : Clear START_DET Interrupt Register -#define I2C_IC_CLR_START_DET_OFFSET _u(0x00000064) -#define I2C_IC_CLR_START_DET_BITS _u(0x00000001) -#define I2C_IC_CLR_START_DET_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_CLR_START_DET_CLR_START_DET -// Description : Read this register to clear the START_DET interrupt (bit 10) of -// the IC_RAW_INTR_STAT register. -// -// Reset value: 0x0 -#define I2C_IC_CLR_START_DET_CLR_START_DET_RESET _u(0x0) -#define I2C_IC_CLR_START_DET_CLR_START_DET_BITS _u(0x00000001) -#define I2C_IC_CLR_START_DET_CLR_START_DET_MSB _u(0) -#define I2C_IC_CLR_START_DET_CLR_START_DET_LSB _u(0) -#define I2C_IC_CLR_START_DET_CLR_START_DET_ACCESS "RO" -// ============================================================================= -// Register : I2C_IC_CLR_GEN_CALL -// Description : Clear GEN_CALL Interrupt Register -#define I2C_IC_CLR_GEN_CALL_OFFSET _u(0x00000068) -#define I2C_IC_CLR_GEN_CALL_BITS _u(0x00000001) -#define I2C_IC_CLR_GEN_CALL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_CLR_GEN_CALL_CLR_GEN_CALL -// Description : Read this register to clear the GEN_CALL interrupt (bit 11) of -// IC_RAW_INTR_STAT register. -// -// Reset value: 0x0 -#define I2C_IC_CLR_GEN_CALL_CLR_GEN_CALL_RESET _u(0x0) -#define I2C_IC_CLR_GEN_CALL_CLR_GEN_CALL_BITS _u(0x00000001) -#define I2C_IC_CLR_GEN_CALL_CLR_GEN_CALL_MSB _u(0) -#define I2C_IC_CLR_GEN_CALL_CLR_GEN_CALL_LSB _u(0) -#define I2C_IC_CLR_GEN_CALL_CLR_GEN_CALL_ACCESS "RO" -// ============================================================================= -// Register : I2C_IC_ENABLE -// Description : I2C Enable Register -#define I2C_IC_ENABLE_OFFSET _u(0x0000006c) -#define I2C_IC_ENABLE_BITS _u(0x00000007) -#define I2C_IC_ENABLE_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_ENABLE_TX_CMD_BLOCK -// Description : In Master mode: - 1'b1: Blocks the transmission of data on I2C -// bus even if Tx FIFO has data to transmit. - 1'b0: The -// transmission of data starts on I2C bus automatically, as soon -// as the first data is available in the Tx FIFO. Note: To block -// the execution of Master commands, set the TX_CMD_BLOCK bit only -// when Tx FIFO is empty (IC_STATUS[2]==1) and Master is in Idle -// state (IC_STATUS[5] == 0). Any further commands put in the Tx -// FIFO are not executed until TX_CMD_BLOCK bit is unset. Reset -// value: IC_TX_CMD_BLOCK_DEFAULT -// 0x0 -> Tx Command execution not blocked -// 0x1 -> Tx Command execution blocked -#define I2C_IC_ENABLE_TX_CMD_BLOCK_RESET _u(0x0) -#define I2C_IC_ENABLE_TX_CMD_BLOCK_BITS _u(0x00000004) -#define I2C_IC_ENABLE_TX_CMD_BLOCK_MSB _u(2) -#define I2C_IC_ENABLE_TX_CMD_BLOCK_LSB _u(2) -#define I2C_IC_ENABLE_TX_CMD_BLOCK_ACCESS "RW" -#define I2C_IC_ENABLE_TX_CMD_BLOCK_VALUE_NOT_BLOCKED _u(0x0) -#define I2C_IC_ENABLE_TX_CMD_BLOCK_VALUE_BLOCKED _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_ENABLE_ABORT -// Description : When set, the controller initiates the transfer abort. - 0: -// ABORT not initiated or ABORT done - 1: ABORT operation in -// progress The software can abort the I2C transfer in master mode -// by setting this bit. The software can set this bit only when -// ENABLE is already set; otherwise, the controller ignores any -// write to ABORT bit. The software cannot clear the ABORT bit -// once set. In response to an ABORT, the controller issues a STOP -// and flushes the Tx FIFO after completing the current transfer, -// then sets the TX_ABORT interrupt after the abort operation. The -// ABORT bit is cleared automatically after the abort operation. -// -// For a detailed description on how to abort I2C transfers, refer -// to 'Aborting I2C Transfers'. -// -// Reset value: 0x0 -// 0x0 -> ABORT operation not in progress -// 0x1 -> ABORT operation in progress -#define I2C_IC_ENABLE_ABORT_RESET _u(0x0) -#define I2C_IC_ENABLE_ABORT_BITS _u(0x00000002) -#define I2C_IC_ENABLE_ABORT_MSB _u(1) -#define I2C_IC_ENABLE_ABORT_LSB _u(1) -#define I2C_IC_ENABLE_ABORT_ACCESS "RW" -#define I2C_IC_ENABLE_ABORT_VALUE_DISABLE _u(0x0) -#define I2C_IC_ENABLE_ABORT_VALUE_ENABLED _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_ENABLE_ENABLE -// Description : Controls whether the DW_apb_i2c is enabled. - 0: Disables -// DW_apb_i2c (TX and RX FIFOs are held in an erased state) - 1: -// Enables DW_apb_i2c Software can disable DW_apb_i2c while it is -// active. However, it is important that care be taken to ensure -// that DW_apb_i2c is disabled properly. A recommended procedure -// is described in 'Disabling DW_apb_i2c'. -// -// When DW_apb_i2c is disabled, the following occurs: - The TX -// FIFO and RX FIFO get flushed. - Status bits in the IC_INTR_STAT -// register are still active until DW_apb_i2c goes into IDLE -// state. If the module is transmitting, it stops as well as -// deletes the contents of the transmit buffer after the current -// transfer is complete. If the module is receiving, the -// DW_apb_i2c stops the current transfer at the end of the current -// byte and does not acknowledge the transfer. -// -// In systems with asynchronous pclk and ic_clk when IC_CLK_TYPE -// parameter set to asynchronous (1), there is a two ic_clk delay -// when enabling or disabling the DW_apb_i2c. For a detailed -// description on how to disable DW_apb_i2c, refer to 'Disabling -// DW_apb_i2c' -// -// Reset value: 0x0 -// 0x0 -> I2C is disabled -// 0x1 -> I2C is enabled -#define I2C_IC_ENABLE_ENABLE_RESET _u(0x0) -#define I2C_IC_ENABLE_ENABLE_BITS _u(0x00000001) -#define I2C_IC_ENABLE_ENABLE_MSB _u(0) -#define I2C_IC_ENABLE_ENABLE_LSB _u(0) -#define I2C_IC_ENABLE_ENABLE_ACCESS "RW" -#define I2C_IC_ENABLE_ENABLE_VALUE_DISABLED _u(0x0) -#define I2C_IC_ENABLE_ENABLE_VALUE_ENABLED _u(0x1) -// ============================================================================= -// Register : I2C_IC_STATUS -// Description : I2C Status Register -// -// This is a read-only register used to indicate the current -// transfer status and FIFO status. The status register may be -// read at any time. None of the bits in this register request an -// interrupt. -// -// When the I2C is disabled by writing 0 in bit 0 of the IC_ENABLE -// register: - Bits 1 and 2 are set to 1 - Bits 3 and 10 are set -// to 0 When the master or slave state machines goes to idle and -// ic_en=0: - Bits 5 and 6 are set to 0 -#define I2C_IC_STATUS_OFFSET _u(0x00000070) -#define I2C_IC_STATUS_BITS _u(0x0000007f) -#define I2C_IC_STATUS_RESET _u(0x00000006) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_STATUS_SLV_ACTIVITY -// Description : Slave FSM Activity Status. When the Slave Finite State Machine -// (FSM) is not in the IDLE state, this bit is set. - 0: Slave FSM -// is in IDLE state so the Slave part of DW_apb_i2c is not Active -// - 1: Slave FSM is not in IDLE state so the Slave part of -// DW_apb_i2c is Active Reset value: 0x0 -// 0x0 -> Slave is idle -// 0x1 -> Slave not idle -#define I2C_IC_STATUS_SLV_ACTIVITY_RESET _u(0x0) -#define I2C_IC_STATUS_SLV_ACTIVITY_BITS _u(0x00000040) -#define I2C_IC_STATUS_SLV_ACTIVITY_MSB _u(6) -#define I2C_IC_STATUS_SLV_ACTIVITY_LSB _u(6) -#define I2C_IC_STATUS_SLV_ACTIVITY_ACCESS "RO" -#define I2C_IC_STATUS_SLV_ACTIVITY_VALUE_IDLE _u(0x0) -#define I2C_IC_STATUS_SLV_ACTIVITY_VALUE_ACTIVE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_STATUS_MST_ACTIVITY -// Description : Master FSM Activity Status. When the Master Finite State -// Machine (FSM) is not in the IDLE state, this bit is set. - 0: -// Master FSM is in IDLE state so the Master part of DW_apb_i2c is -// not Active - 1: Master FSM is not in IDLE state so the Master -// part of DW_apb_i2c is Active Note: IC_STATUS[0]-that is, -// ACTIVITY bit-is the OR of SLV_ACTIVITY and MST_ACTIVITY bits. -// -// Reset value: 0x0 -// 0x0 -> Master is idle -// 0x1 -> Master not idle -#define I2C_IC_STATUS_MST_ACTIVITY_RESET _u(0x0) -#define I2C_IC_STATUS_MST_ACTIVITY_BITS _u(0x00000020) -#define I2C_IC_STATUS_MST_ACTIVITY_MSB _u(5) -#define I2C_IC_STATUS_MST_ACTIVITY_LSB _u(5) -#define I2C_IC_STATUS_MST_ACTIVITY_ACCESS "RO" -#define I2C_IC_STATUS_MST_ACTIVITY_VALUE_IDLE _u(0x0) -#define I2C_IC_STATUS_MST_ACTIVITY_VALUE_ACTIVE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_STATUS_RFF -// Description : Receive FIFO Completely Full. When the receive FIFO is -// completely full, this bit is set. When the receive FIFO -// contains one or more empty location, this bit is cleared. - 0: -// Receive FIFO is not full - 1: Receive FIFO is full Reset value: -// 0x0 -// 0x0 -> Rx FIFO not full -// 0x1 -> Rx FIFO is full -#define I2C_IC_STATUS_RFF_RESET _u(0x0) -#define I2C_IC_STATUS_RFF_BITS _u(0x00000010) -#define I2C_IC_STATUS_RFF_MSB _u(4) -#define I2C_IC_STATUS_RFF_LSB _u(4) -#define I2C_IC_STATUS_RFF_ACCESS "RO" -#define I2C_IC_STATUS_RFF_VALUE_NOT_FULL _u(0x0) -#define I2C_IC_STATUS_RFF_VALUE_FULL _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_STATUS_RFNE -// Description : Receive FIFO Not Empty. This bit is set when the receive FIFO -// contains one or more entries; it is cleared when the receive -// FIFO is empty. - 0: Receive FIFO is empty - 1: Receive FIFO is -// not empty Reset value: 0x0 -// 0x0 -> Rx FIFO is empty -// 0x1 -> Rx FIFO not empty -#define I2C_IC_STATUS_RFNE_RESET _u(0x0) -#define I2C_IC_STATUS_RFNE_BITS _u(0x00000008) -#define I2C_IC_STATUS_RFNE_MSB _u(3) -#define I2C_IC_STATUS_RFNE_LSB _u(3) -#define I2C_IC_STATUS_RFNE_ACCESS "RO" -#define I2C_IC_STATUS_RFNE_VALUE_EMPTY _u(0x0) -#define I2C_IC_STATUS_RFNE_VALUE_NOT_EMPTY _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_STATUS_TFE -// Description : Transmit FIFO Completely Empty. When the transmit FIFO is -// completely empty, this bit is set. When it contains one or more -// valid entries, this bit is cleared. This bit field does not -// request an interrupt. - 0: Transmit FIFO is not empty - 1: -// Transmit FIFO is empty Reset value: 0x1 -// 0x0 -> Tx FIFO not empty -// 0x1 -> Tx FIFO is empty -#define I2C_IC_STATUS_TFE_RESET _u(0x1) -#define I2C_IC_STATUS_TFE_BITS _u(0x00000004) -#define I2C_IC_STATUS_TFE_MSB _u(2) -#define I2C_IC_STATUS_TFE_LSB _u(2) -#define I2C_IC_STATUS_TFE_ACCESS "RO" -#define I2C_IC_STATUS_TFE_VALUE_NON_EMPTY _u(0x0) -#define I2C_IC_STATUS_TFE_VALUE_EMPTY _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_STATUS_TFNF -// Description : Transmit FIFO Not Full. Set when the transmit FIFO contains one -// or more empty locations, and is cleared when the FIFO is full. -// - 0: Transmit FIFO is full - 1: Transmit FIFO is not full Reset -// value: 0x1 -// 0x0 -> Tx FIFO is full -// 0x1 -> Tx FIFO not full -#define I2C_IC_STATUS_TFNF_RESET _u(0x1) -#define I2C_IC_STATUS_TFNF_BITS _u(0x00000002) -#define I2C_IC_STATUS_TFNF_MSB _u(1) -#define I2C_IC_STATUS_TFNF_LSB _u(1) -#define I2C_IC_STATUS_TFNF_ACCESS "RO" -#define I2C_IC_STATUS_TFNF_VALUE_FULL _u(0x0) -#define I2C_IC_STATUS_TFNF_VALUE_NOT_FULL _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_STATUS_ACTIVITY -// Description : I2C Activity Status. Reset value: 0x0 -// 0x0 -> I2C is idle -// 0x1 -> I2C is active -#define I2C_IC_STATUS_ACTIVITY_RESET _u(0x0) -#define I2C_IC_STATUS_ACTIVITY_BITS _u(0x00000001) -#define I2C_IC_STATUS_ACTIVITY_MSB _u(0) -#define I2C_IC_STATUS_ACTIVITY_LSB _u(0) -#define I2C_IC_STATUS_ACTIVITY_ACCESS "RO" -#define I2C_IC_STATUS_ACTIVITY_VALUE_INACTIVE _u(0x0) -#define I2C_IC_STATUS_ACTIVITY_VALUE_ACTIVE _u(0x1) -// ============================================================================= -// Register : I2C_IC_TXFLR -// Description : I2C Transmit FIFO Level Register This register contains the -// number of valid data entries in the transmit FIFO buffer. It is -// cleared whenever: - The I2C is disabled - There is a transmit -// abort - that is, TX_ABRT bit is set in the IC_RAW_INTR_STAT -// register - The slave bulk transmit mode is aborted The register -// increments whenever data is placed into the transmit FIFO and -// decrements when data is taken from the transmit FIFO. -#define I2C_IC_TXFLR_OFFSET _u(0x00000074) -#define I2C_IC_TXFLR_BITS _u(0x0000001f) -#define I2C_IC_TXFLR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_TXFLR_TXFLR -// Description : Transmit FIFO Level. Contains the number of valid data entries -// in the transmit FIFO. -// -// Reset value: 0x0 -#define I2C_IC_TXFLR_TXFLR_RESET _u(0x00) -#define I2C_IC_TXFLR_TXFLR_BITS _u(0x0000001f) -#define I2C_IC_TXFLR_TXFLR_MSB _u(4) -#define I2C_IC_TXFLR_TXFLR_LSB _u(0) -#define I2C_IC_TXFLR_TXFLR_ACCESS "RO" -// ============================================================================= -// Register : I2C_IC_RXFLR -// Description : I2C Receive FIFO Level Register This register contains the -// number of valid data entries in the receive FIFO buffer. It is -// cleared whenever: - The I2C is disabled - Whenever there is a -// transmit abort caused by any of the events tracked in -// IC_TX_ABRT_SOURCE The register increments whenever data is -// placed into the receive FIFO and decrements when data is taken -// from the receive FIFO. -#define I2C_IC_RXFLR_OFFSET _u(0x00000078) -#define I2C_IC_RXFLR_BITS _u(0x0000001f) -#define I2C_IC_RXFLR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_RXFLR_RXFLR -// Description : Receive FIFO Level. Contains the number of valid data entries -// in the receive FIFO. -// -// Reset value: 0x0 -#define I2C_IC_RXFLR_RXFLR_RESET _u(0x00) -#define I2C_IC_RXFLR_RXFLR_BITS _u(0x0000001f) -#define I2C_IC_RXFLR_RXFLR_MSB _u(4) -#define I2C_IC_RXFLR_RXFLR_LSB _u(0) -#define I2C_IC_RXFLR_RXFLR_ACCESS "RO" -// ============================================================================= -// Register : I2C_IC_SDA_HOLD -// Description : I2C SDA Hold Time Length Register -// -// The bits [15:0] of this register are used to control the hold -// time of SDA during transmit in both slave and master mode -// (after SCL goes from HIGH to LOW). -// -// The bits [23:16] of this register are used to extend the SDA -// transition (if any) whenever SCL is HIGH in the receiver in -// either master or slave mode. -// -// Writes to this register succeed only when IC_ENABLE[0]=0. -// -// The values in this register are in units of ic_clk period. The -// value programmed in IC_SDA_TX_HOLD must be greater than the -// minimum hold time in each mode (one cycle in master mode, seven -// cycles in slave mode) for the value to be implemented. -// -// The programmed SDA hold time during transmit (IC_SDA_TX_HOLD) -// cannot exceed at any time the duration of the low part of scl. -// Therefore the programmed value cannot be larger than -// N_SCL_LOW-2, where N_SCL_LOW is the duration of the low part of -// the scl period measured in ic_clk cycles. -#define I2C_IC_SDA_HOLD_OFFSET _u(0x0000007c) -#define I2C_IC_SDA_HOLD_BITS _u(0x00ffffff) -#define I2C_IC_SDA_HOLD_RESET _u(0x00000001) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_SDA_HOLD_IC_SDA_RX_HOLD -// Description : Sets the required SDA hold time in units of ic_clk period, when -// DW_apb_i2c acts as a receiver. -// -// Reset value: IC_DEFAULT_SDA_HOLD[23:16]. -#define I2C_IC_SDA_HOLD_IC_SDA_RX_HOLD_RESET _u(0x00) -#define I2C_IC_SDA_HOLD_IC_SDA_RX_HOLD_BITS _u(0x00ff0000) -#define I2C_IC_SDA_HOLD_IC_SDA_RX_HOLD_MSB _u(23) -#define I2C_IC_SDA_HOLD_IC_SDA_RX_HOLD_LSB _u(16) -#define I2C_IC_SDA_HOLD_IC_SDA_RX_HOLD_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : I2C_IC_SDA_HOLD_IC_SDA_TX_HOLD -// Description : Sets the required SDA hold time in units of ic_clk period, when -// DW_apb_i2c acts as a transmitter. -// -// Reset value: IC_DEFAULT_SDA_HOLD[15:0]. -#define I2C_IC_SDA_HOLD_IC_SDA_TX_HOLD_RESET _u(0x0001) -#define I2C_IC_SDA_HOLD_IC_SDA_TX_HOLD_BITS _u(0x0000ffff) -#define I2C_IC_SDA_HOLD_IC_SDA_TX_HOLD_MSB _u(15) -#define I2C_IC_SDA_HOLD_IC_SDA_TX_HOLD_LSB _u(0) -#define I2C_IC_SDA_HOLD_IC_SDA_TX_HOLD_ACCESS "RW" -// ============================================================================= -// Register : I2C_IC_TX_ABRT_SOURCE -// Description : I2C Transmit Abort Source Register -// -// This register has 32 bits that indicate the source of the -// TX_ABRT bit. Except for Bit 9, this register is cleared -// whenever the IC_CLR_TX_ABRT register or the IC_CLR_INTR -// register is read. To clear Bit 9, the source of the -// ABRT_SBYTE_NORSTRT must be fixed first; RESTART must be enabled -// (IC_CON[5]=1), the SPECIAL bit must be cleared (IC_TAR[11]), or -// the GC_OR_START bit must be cleared (IC_TAR[10]). -// -// Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this -// bit can be cleared in the same manner as other bits in this -// register. If the source of the ABRT_SBYTE_NORSTRT is not fixed -// before attempting to clear this bit, Bit 9 clears for one cycle -// and is then re-asserted. -#define I2C_IC_TX_ABRT_SOURCE_OFFSET _u(0x00000080) -#define I2C_IC_TX_ABRT_SOURCE_BITS _u(0xff81ffff) -#define I2C_IC_TX_ABRT_SOURCE_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_TX_ABRT_SOURCE_TX_FLUSH_CNT -// Description : This field indicates the number of Tx FIFO Data Commands which -// are flushed due to TX_ABRT interrupt. It is cleared whenever -// I2C is disabled. -// -// Reset value: 0x0 -// -// Role of DW_apb_i2c: Master-Transmitter or Slave-Transmitter -#define I2C_IC_TX_ABRT_SOURCE_TX_FLUSH_CNT_RESET _u(0x000) -#define I2C_IC_TX_ABRT_SOURCE_TX_FLUSH_CNT_BITS _u(0xff800000) -#define I2C_IC_TX_ABRT_SOURCE_TX_FLUSH_CNT_MSB _u(31) -#define I2C_IC_TX_ABRT_SOURCE_TX_FLUSH_CNT_LSB _u(23) -#define I2C_IC_TX_ABRT_SOURCE_TX_FLUSH_CNT_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT -// Description : This is a master-mode-only bit. Master has detected the -// transfer abort (IC_ENABLE[1]) -// -// Reset value: 0x0 -// -// Role of DW_apb_i2c: Master-Transmitter -// 0x0 -> Transfer abort detected by master- scenario not present -// 0x1 -> Transfer abort detected by master -#define I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_RESET _u(0x0) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_BITS _u(0x00010000) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_MSB _u(16) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_LSB _u(16) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_ACCESS "RO" -#define I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_VALUE_ABRT_USER_ABRT_VOID _u(0x0) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_VALUE_ABRT_USER_ABRT_GENERATED _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX -// Description : 1: When the processor side responds to a slave mode request for -// data to be transmitted to a remote master and user writes a 1 -// in CMD (bit 8) of IC_DATA_CMD register. -// -// Reset value: 0x0 -// -// Role of DW_apb_i2c: Slave-Transmitter -// 0x0 -> Slave trying to transmit to remote master in read mode- scenario not present -// 0x1 -> Slave trying to transmit to remote master in read mode -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_RESET _u(0x0) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_BITS _u(0x00008000) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_MSB _u(15) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_LSB _u(15) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_ACCESS "RO" -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_VALUE_ABRT_SLVRD_INTX_VOID _u(0x0) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_VALUE_ABRT_SLVRD_INTX_GENERATED _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST -// Description : This field indicates that a Slave has lost the bus while -// transmitting data to a remote master. IC_TX_ABRT_SOURCE[12] is -// set at the same time. Note: Even though the slave never 'owns' -// the bus, something could go wrong on the bus. This is a fail -// safe check. For instance, during a data transmission at the -// low-to-high transition of SCL, if what is on the data bus is -// not what is supposed to be transmitted, then DW_apb_i2c no -// longer own the bus. -// -// Reset value: 0x0 -// -// Role of DW_apb_i2c: Slave-Transmitter -// 0x0 -> Slave lost arbitration to remote master- scenario not present -// 0x1 -> Slave lost arbitration to remote master -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_RESET _u(0x0) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_BITS _u(0x00004000) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_MSB _u(14) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_LSB _u(14) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_ACCESS "RO" -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_VALUE_ABRT_SLV_ARBLOST_VOID _u(0x0) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_VALUE_ABRT_SLV_ARBLOST_GENERATED _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO -// Description : This field specifies that the Slave has received a read command -// and some data exists in the TX FIFO, so the slave issues a -// TX_ABRT interrupt to flush old data in TX FIFO. -// -// Reset value: 0x0 -// -// Role of DW_apb_i2c: Slave-Transmitter -// 0x0 -> Slave flushes existing data in TX-FIFO upon getting read command- scenario not present -// 0x1 -> Slave flushes existing data in TX-FIFO upon getting read command -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_RESET _u(0x0) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_BITS _u(0x00002000) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_MSB _u(13) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_LSB _u(13) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_ACCESS "RO" -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_VALUE_ABRT_SLVFLUSH_TXFIFO_VOID _u(0x0) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_VALUE_ABRT_SLVFLUSH_TXFIFO_GENERATED _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_TX_ABRT_SOURCE_ARB_LOST -// Description : This field specifies that the Master has lost arbitration, or -// if IC_TX_ABRT_SOURCE[14] is also set, then the slave -// transmitter has lost arbitration. -// -// Reset value: 0x0 -// -// Role of DW_apb_i2c: Master-Transmitter or Slave-Transmitter -// 0x0 -> Master or Slave-Transmitter lost arbitration- scenario not present -// 0x1 -> Master or Slave-Transmitter lost arbitration -#define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_RESET _u(0x0) -#define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_BITS _u(0x00001000) -#define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_MSB _u(12) -#define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_LSB _u(12) -#define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_ACCESS "RO" -#define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_VALUE_ABRT_LOST_VOID _u(0x0) -#define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_VALUE_ABRT_LOST_GENERATED _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS -// Description : This field indicates that the User tries to initiate a Master -// operation with the Master mode disabled. -// -// Reset value: 0x0 -// -// Role of DW_apb_i2c: Master-Transmitter or Master-Receiver -// 0x0 -> User initiating master operation when MASTER disabled- scenario not present -// 0x1 -> User initiating master operation when MASTER disabled -#define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_RESET _u(0x0) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_BITS _u(0x00000800) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_MSB _u(11) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_LSB _u(11) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_ACCESS "RO" -#define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_VALUE_ABRT_MASTER_DIS_VOID _u(0x0) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_VALUE_ABRT_MASTER_DIS_GENERATED _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT -// Description : This field indicates that the restart is disabled -// (IC_RESTART_EN bit (IC_CON[5]) =0) and the master sends a read -// command in 10-bit addressing mode. -// -// Reset value: 0x0 -// -// Role of DW_apb_i2c: Master-Receiver -// 0x0 -> Master not trying to read in 10Bit addressing mode when RESTART disabled -// 0x1 -> Master trying to read in 10Bit addressing mode when RESTART disabled -#define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_RESET _u(0x0) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_BITS _u(0x00000400) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_MSB _u(10) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_LSB _u(10) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_ACCESS "RO" -#define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_VALUE_ABRT_10B_RD_VOID _u(0x0) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_VALUE_ABRT_10B_RD_GENERATED _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT -// Description : To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be -// fixed first; restart must be enabled (IC_CON[5]=1), the SPECIAL -// bit must be cleared (IC_TAR[11]), or the GC_OR_START bit must -// be cleared (IC_TAR[10]). Once the source of the -// ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in -// the same manner as other bits in this register. If the source -// of the ABRT_SBYTE_NORSTRT is not fixed before attempting to -// clear this bit, bit 9 clears for one cycle and then gets -// reasserted. When this field is set to 1, the restart is -// disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the user is -// trying to send a START Byte. -// -// Reset value: 0x0 -// -// Role of DW_apb_i2c: Master -// 0x0 -> User trying to send START byte when RESTART disabled- scenario not present -// 0x1 -> User trying to send START byte when RESTART disabled -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_RESET _u(0x0) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_BITS _u(0x00000200) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_MSB _u(9) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_LSB _u(9) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_ACCESS "RO" -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_VALUE_ABRT_SBYTE_NORSTRT_VOID _u(0x0) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_VALUE_ABRT_SBYTE_NORSTRT_GENERATED _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT -// Description : This field indicates that the restart is disabled -// (IC_RESTART_EN bit (IC_CON[5]) =0) and the user is trying to -// use the master to transfer data in High Speed mode. -// -// Reset value: 0x0 -// -// Role of DW_apb_i2c: Master-Transmitter or Master-Receiver -// 0x0 -> User trying to switch Master to HS mode when RESTART disabled- scenario not present -// 0x1 -> User trying to switch Master to HS mode when RESTART disabled -#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_RESET _u(0x0) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_BITS _u(0x00000100) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_MSB _u(8) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_LSB _u(8) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_ACCESS "RO" -#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_VALUE_ABRT_HS_NORSTRT_VOID _u(0x0) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_VALUE_ABRT_HS_NORSTRT_GENERATED _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET -// Description : This field indicates that the Master has sent a START Byte and -// the START Byte was acknowledged (wrong behavior). -// -// Reset value: 0x0 -// -// Role of DW_apb_i2c: Master -// 0x0 -> ACK detected for START byte- scenario not present -// 0x1 -> ACK detected for START byte -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_RESET _u(0x0) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_BITS _u(0x00000080) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_MSB _u(7) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_LSB _u(7) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_ACCESS "RO" -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_VALUE_ABRT_SBYTE_ACKDET_VOID _u(0x0) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_VALUE_ABRT_SBYTE_ACKDET_GENERATED _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET -// Description : This field indicates that the Master is in High Speed mode and -// the High Speed Master code was acknowledged (wrong behavior). -// -// Reset value: 0x0 -// -// Role of DW_apb_i2c: Master -// 0x0 -> HS Master code ACKed in HS Mode- scenario not present -// 0x1 -> HS Master code ACKed in HS Mode -#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_RESET _u(0x0) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_BITS _u(0x00000040) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_MSB _u(6) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_LSB _u(6) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_ACCESS "RO" -#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_VALUE_ABRT_HS_ACK_VOID _u(0x0) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_VALUE_ABRT_HS_ACK_GENERATED _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ -// Description : This field indicates that DW_apb_i2c in the master mode has -// sent a General Call but the user programmed the byte following -// the General Call to be a read from the bus (IC_DATA_CMD[9] is -// set to 1). -// -// Reset value: 0x0 -// -// Role of DW_apb_i2c: Master-Transmitter -// 0x0 -> GCALL is followed by read from bus-scenario not present -// 0x1 -> GCALL is followed by read from bus -#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_RESET _u(0x0) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_BITS _u(0x00000020) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_MSB _u(5) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_LSB _u(5) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_ACCESS "RO" -#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_VALUE_ABRT_GCALL_READ_VOID _u(0x0) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_VALUE_ABRT_GCALL_READ_GENERATED _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK -// Description : This field indicates that DW_apb_i2c in master mode has sent a -// General Call and no slave on the bus acknowledged the General -// Call. -// -// Reset value: 0x0 -// -// Role of DW_apb_i2c: Master-Transmitter -// 0x0 -> GCALL not ACKed by any slave-scenario not present -// 0x1 -> GCALL not ACKed by any slave -#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_RESET _u(0x0) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_BITS _u(0x00000010) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_MSB _u(4) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_LSB _u(4) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_ACCESS "RO" -#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_VALUE_ABRT_GCALL_NOACK_VOID _u(0x0) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_VALUE_ABRT_GCALL_NOACK_GENERATED _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK -// Description : This field indicates the master-mode only bit. When the master -// receives an acknowledgement for the address, but when it sends -// data byte(s) following the address, it did not receive an -// acknowledge from the remote slave(s). -// -// Reset value: 0x0 -// -// Role of DW_apb_i2c: Master-Transmitter -// 0x0 -> Transmitted data non-ACKed by addressed slave-scenario not present -// 0x1 -> Transmitted data not ACKed by addressed slave -#define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_RESET _u(0x0) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_BITS _u(0x00000008) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_MSB _u(3) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_LSB _u(3) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_ACCESS "RO" -#define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_VALUE_ABRT_TXDATA_NOACK_VOID _u(0x0) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_VALUE_ABRT_TXDATA_NOACK_GENERATED _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK -// Description : This field indicates that the Master is in 10-bit address mode -// and that the second address byte of the 10-bit address was not -// acknowledged by any slave. -// -// Reset value: 0x0 -// -// Role of DW_apb_i2c: Master-Transmitter or Master-Receiver -// 0x0 -> This abort is not generated -// 0x1 -> Byte 2 of 10Bit Address not ACKed by any slave -#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_RESET _u(0x0) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_BITS _u(0x00000004) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_MSB _u(2) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_LSB _u(2) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_ACCESS "RO" -#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_VALUE_INACTIVE _u(0x0) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_VALUE_ACTIVE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK -// Description : This field indicates that the Master is in 10-bit address mode -// and the first 10-bit address byte was not acknowledged by any -// slave. -// -// Reset value: 0x0 -// -// Role of DW_apb_i2c: Master-Transmitter or Master-Receiver -// 0x0 -> This abort is not generated -// 0x1 -> Byte 1 of 10Bit Address not ACKed by any slave -#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_RESET _u(0x0) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_BITS _u(0x00000002) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_MSB _u(1) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_LSB _u(1) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_ACCESS "RO" -#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_VALUE_INACTIVE _u(0x0) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_VALUE_ACTIVE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK -// Description : This field indicates that the Master is in 7-bit addressing -// mode and the address sent was not acknowledged by any slave. -// -// Reset value: 0x0 -// -// Role of DW_apb_i2c: Master-Transmitter or Master-Receiver -// 0x0 -> This abort is not generated -// 0x1 -> This abort is generated because of NOACK for 7-bit address -#define I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_RESET _u(0x0) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_BITS _u(0x00000001) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_MSB _u(0) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_LSB _u(0) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_ACCESS "RO" -#define I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_VALUE_INACTIVE _u(0x0) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_VALUE_ACTIVE _u(0x1) -// ============================================================================= -// Register : I2C_IC_SLV_DATA_NACK_ONLY -// Description : Generate Slave Data NACK Register -// -// The register is used to generate a NACK for the data part of a -// transfer when DW_apb_i2c is acting as a slave-receiver. This -// register only exists when the IC_SLV_DATA_NACK_ONLY parameter -// is set to 1. When this parameter disabled, this register does -// not exist and writing to the register's address has no effect. -// -// A write can occur on this register if both of the following -// conditions are met: - DW_apb_i2c is disabled (IC_ENABLE[0] = 0) -// - Slave part is inactive (IC_STATUS[6] = 0) Note: The -// IC_STATUS[6] is a register read-back location for the internal -// slv_activity signal; the user should poll this before writing -// the ic_slv_data_nack_only bit. -#define I2C_IC_SLV_DATA_NACK_ONLY_OFFSET _u(0x00000084) -#define I2C_IC_SLV_DATA_NACK_ONLY_BITS _u(0x00000001) -#define I2C_IC_SLV_DATA_NACK_ONLY_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_SLV_DATA_NACK_ONLY_NACK -// Description : Generate NACK. This NACK generation only occurs when DW_apb_i2c -// is a slave-receiver. If this register is set to a value of 1, -// it can only generate a NACK after a data byte is received; -// hence, the data transfer is aborted and the data received is -// not pushed to the receive buffer. -// -// When the register is set to a value of 0, it generates -// NACK/ACK, depending on normal criteria. - 1: generate NACK -// after data byte received - 0: generate NACK/ACK normally Reset -// value: 0x0 -// 0x0 -> Slave receiver generates NACK normally -// 0x1 -> Slave receiver generates NACK upon data reception only -#define I2C_IC_SLV_DATA_NACK_ONLY_NACK_RESET _u(0x0) -#define I2C_IC_SLV_DATA_NACK_ONLY_NACK_BITS _u(0x00000001) -#define I2C_IC_SLV_DATA_NACK_ONLY_NACK_MSB _u(0) -#define I2C_IC_SLV_DATA_NACK_ONLY_NACK_LSB _u(0) -#define I2C_IC_SLV_DATA_NACK_ONLY_NACK_ACCESS "RW" -#define I2C_IC_SLV_DATA_NACK_ONLY_NACK_VALUE_DISABLED _u(0x0) -#define I2C_IC_SLV_DATA_NACK_ONLY_NACK_VALUE_ENABLED _u(0x1) -// ============================================================================= -// Register : I2C_IC_DMA_CR -// Description : DMA Control Register -// -// The register is used to enable the DMA Controller interface -// operation. There is a separate bit for transmit and receive. -// This can be programmed regardless of the state of IC_ENABLE. -#define I2C_IC_DMA_CR_OFFSET _u(0x00000088) -#define I2C_IC_DMA_CR_BITS _u(0x00000003) -#define I2C_IC_DMA_CR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_DMA_CR_TDMAE -// Description : Transmit DMA Enable. This bit enables/disables the transmit -// FIFO DMA channel. Reset value: 0x0 -// 0x0 -> transmit FIFO DMA channel disabled -// 0x1 -> Transmit FIFO DMA channel enabled -#define I2C_IC_DMA_CR_TDMAE_RESET _u(0x0) -#define I2C_IC_DMA_CR_TDMAE_BITS _u(0x00000002) -#define I2C_IC_DMA_CR_TDMAE_MSB _u(1) -#define I2C_IC_DMA_CR_TDMAE_LSB _u(1) -#define I2C_IC_DMA_CR_TDMAE_ACCESS "RW" -#define I2C_IC_DMA_CR_TDMAE_VALUE_DISABLED _u(0x0) -#define I2C_IC_DMA_CR_TDMAE_VALUE_ENABLED _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_DMA_CR_RDMAE -// Description : Receive DMA Enable. This bit enables/disables the receive FIFO -// DMA channel. Reset value: 0x0 -// 0x0 -> Receive FIFO DMA channel disabled -// 0x1 -> Receive FIFO DMA channel enabled -#define I2C_IC_DMA_CR_RDMAE_RESET _u(0x0) -#define I2C_IC_DMA_CR_RDMAE_BITS _u(0x00000001) -#define I2C_IC_DMA_CR_RDMAE_MSB _u(0) -#define I2C_IC_DMA_CR_RDMAE_LSB _u(0) -#define I2C_IC_DMA_CR_RDMAE_ACCESS "RW" -#define I2C_IC_DMA_CR_RDMAE_VALUE_DISABLED _u(0x0) -#define I2C_IC_DMA_CR_RDMAE_VALUE_ENABLED _u(0x1) -// ============================================================================= -// Register : I2C_IC_DMA_TDLR -// Description : DMA Transmit Data Level Register -#define I2C_IC_DMA_TDLR_OFFSET _u(0x0000008c) -#define I2C_IC_DMA_TDLR_BITS _u(0x0000000f) -#define I2C_IC_DMA_TDLR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_DMA_TDLR_DMATDL -// Description : Transmit Data Level. This bit field controls the level at which -// a DMA request is made by the transmit logic. It is equal to the -// watermark level; that is, the dma_tx_req signal is generated -// when the number of valid data entries in the transmit FIFO is -// equal to or below this field value, and TDMAE = 1. -// -// Reset value: 0x0 -#define I2C_IC_DMA_TDLR_DMATDL_RESET _u(0x0) -#define I2C_IC_DMA_TDLR_DMATDL_BITS _u(0x0000000f) -#define I2C_IC_DMA_TDLR_DMATDL_MSB _u(3) -#define I2C_IC_DMA_TDLR_DMATDL_LSB _u(0) -#define I2C_IC_DMA_TDLR_DMATDL_ACCESS "RW" -// ============================================================================= -// Register : I2C_IC_DMA_RDLR -// Description : I2C Receive Data Level Register -#define I2C_IC_DMA_RDLR_OFFSET _u(0x00000090) -#define I2C_IC_DMA_RDLR_BITS _u(0x0000000f) -#define I2C_IC_DMA_RDLR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_DMA_RDLR_DMARDL -// Description : Receive Data Level. This bit field controls the level at which -// a DMA request is made by the receive logic. The watermark level -// = DMARDL+1; that is, dma_rx_req is generated when the number of -// valid data entries in the receive FIFO is equal to or more than -// this field value + 1, and RDMAE =1. For instance, when DMARDL -// is 0, then dma_rx_req is asserted when 1 or more data entries -// are present in the receive FIFO. -// -// Reset value: 0x0 -#define I2C_IC_DMA_RDLR_DMARDL_RESET _u(0x0) -#define I2C_IC_DMA_RDLR_DMARDL_BITS _u(0x0000000f) -#define I2C_IC_DMA_RDLR_DMARDL_MSB _u(3) -#define I2C_IC_DMA_RDLR_DMARDL_LSB _u(0) -#define I2C_IC_DMA_RDLR_DMARDL_ACCESS "RW" -// ============================================================================= -// Register : I2C_IC_SDA_SETUP -// Description : I2C SDA Setup Register -// -// This register controls the amount of time delay (in terms of -// number of ic_clk clock periods) introduced in the rising edge -// of SCL - relative to SDA changing - when DW_apb_i2c services a -// read request in a slave-transmitter operation. The relevant I2C -// requirement is tSU:DAT (note 4) as detailed in the I2C Bus -// Specification. This register must be programmed with a value -// equal to or greater than 2. -// -// Writes to this register succeed only when IC_ENABLE[0] = 0. -// -// Note: The length of setup time is calculated using -// [(IC_SDA_SETUP - 1) * (ic_clk_period)], so if the user requires -// 10 ic_clk periods of setup time, they should program a value of -// 11. The IC_SDA_SETUP register is only used by the DW_apb_i2c -// when operating as a slave transmitter. -#define I2C_IC_SDA_SETUP_OFFSET _u(0x00000094) -#define I2C_IC_SDA_SETUP_BITS _u(0x000000ff) -#define I2C_IC_SDA_SETUP_RESET _u(0x00000064) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_SDA_SETUP_SDA_SETUP -// Description : SDA Setup. It is recommended that if the required delay is -// 1000ns, then for an ic_clk frequency of 10 MHz, IC_SDA_SETUP -// should be programmed to a value of 11. IC_SDA_SETUP must be -// programmed with a minimum value of 2. -#define I2C_IC_SDA_SETUP_SDA_SETUP_RESET _u(0x64) -#define I2C_IC_SDA_SETUP_SDA_SETUP_BITS _u(0x000000ff) -#define I2C_IC_SDA_SETUP_SDA_SETUP_MSB _u(7) -#define I2C_IC_SDA_SETUP_SDA_SETUP_LSB _u(0) -#define I2C_IC_SDA_SETUP_SDA_SETUP_ACCESS "RW" -// ============================================================================= -// Register : I2C_IC_ACK_GENERAL_CALL -// Description : I2C ACK General Call Register -// -// The register controls whether DW_apb_i2c responds with a ACK or -// NACK when it receives an I2C General Call address. -// -// This register is applicable only when the DW_apb_i2c is in -// slave mode. -#define I2C_IC_ACK_GENERAL_CALL_OFFSET _u(0x00000098) -#define I2C_IC_ACK_GENERAL_CALL_BITS _u(0x00000001) -#define I2C_IC_ACK_GENERAL_CALL_RESET _u(0x00000001) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL -// Description : ACK General Call. When set to 1, DW_apb_i2c responds with a ACK -// (by asserting ic_data_oe) when it receives a General Call. -// Otherwise, DW_apb_i2c responds with a NACK (by negating -// ic_data_oe). -// 0x0 -> Generate NACK for a General Call -// 0x1 -> Generate ACK for a General Call -#define I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_RESET _u(0x1) -#define I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_BITS _u(0x00000001) -#define I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_MSB _u(0) -#define I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_LSB _u(0) -#define I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_ACCESS "RW" -#define I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_VALUE_DISABLED _u(0x0) -#define I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_VALUE_ENABLED _u(0x1) -// ============================================================================= -// Register : I2C_IC_ENABLE_STATUS -// Description : I2C Enable Status Register -// -// The register is used to report the DW_apb_i2c hardware status -// when the IC_ENABLE[0] register is set from 1 to 0; that is, -// when DW_apb_i2c is disabled. -// -// If IC_ENABLE[0] has been set to 1, bits 2:1 are forced to 0, -// and bit 0 is forced to 1. -// -// If IC_ENABLE[0] has been set to 0, bits 2:1 is only be valid as -// soon as bit 0 is read as '0'. -// -// Note: When IC_ENABLE[0] has been set to 0, a delay occurs for -// bit 0 to be read as 0 because disabling the DW_apb_i2c depends -// on I2C bus activities. -#define I2C_IC_ENABLE_STATUS_OFFSET _u(0x0000009c) -#define I2C_IC_ENABLE_STATUS_BITS _u(0x00000007) -#define I2C_IC_ENABLE_STATUS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST -// Description : Slave Received Data Lost. This bit indicates if a Slave- -// Receiver operation has been aborted with at least one data byte -// received from an I2C transfer due to the setting bit 0 of -// IC_ENABLE from 1 to 0. When read as 1, DW_apb_i2c is deemed to -// have been actively engaged in an aborted I2C transfer (with -// matching address) and the data phase of the I2C transfer has -// been entered, even though a data byte has been responded with a -// NACK. -// -// Note: If the remote I2C master terminates the transfer with a -// STOP condition before the DW_apb_i2c has a chance to NACK a -// transfer, and IC_ENABLE[0] has been set to 0, then this bit is -// also set to 1. -// -// When read as 0, DW_apb_i2c is deemed to have been disabled -// without being actively involved in the data phase of a Slave- -// Receiver transfer. -// -// Note: The CPU can safely read this bit when IC_EN (bit 0) is -// read as 0. -// -// Reset value: 0x0 -// 0x0 -> Slave RX Data is not lost -// 0x1 -> Slave RX Data is lost -#define I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_RESET _u(0x0) -#define I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_BITS _u(0x00000004) -#define I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_MSB _u(2) -#define I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_LSB _u(2) -#define I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_ACCESS "RO" -#define I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_VALUE_INACTIVE _u(0x0) -#define I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_VALUE_ACTIVE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY -// Description : Slave Disabled While Busy (Transmit, Receive). This bit -// indicates if a potential or active Slave operation has been -// aborted due to the setting bit 0 of the IC_ENABLE register from -// 1 to 0. This bit is set when the CPU writes a 0 to the -// IC_ENABLE register while: -// -// (a) DW_apb_i2c is receiving the address byte of the Slave- -// Transmitter operation from a remote master; -// -// OR, -// -// (b) address and data bytes of the Slave-Receiver operation from -// a remote master. -// -// When read as 1, DW_apb_i2c is deemed to have forced a NACK -// during any part of an I2C transfer, irrespective of whether the -// I2C address matches the slave address set in DW_apb_i2c (IC_SAR -// register) OR if the transfer is completed before IC_ENABLE is -// set to 0 but has not taken effect. -// -// Note: If the remote I2C master terminates the transfer with a -// STOP condition before the DW_apb_i2c has a chance to NACK a -// transfer, and IC_ENABLE[0] has been set to 0, then this bit -// will also be set to 1. -// -// When read as 0, DW_apb_i2c is deemed to have been disabled when -// there is master activity, or when the I2C bus is idle. -// -// Note: The CPU can safely read this bit when IC_EN (bit 0) is -// read as 0. -// -// Reset value: 0x0 -// 0x0 -> Slave is disabled when it is idle -// 0x1 -> Slave is disabled when it is active -#define I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_RESET _u(0x0) -#define I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_BITS _u(0x00000002) -#define I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_MSB _u(1) -#define I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_LSB _u(1) -#define I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_ACCESS "RO" -#define I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_VALUE_INACTIVE _u(0x0) -#define I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_VALUE_ACTIVE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_ENABLE_STATUS_IC_EN -// Description : ic_en Status. This bit always reflects the value driven on the -// output port ic_en. - When read as 1, DW_apb_i2c is deemed to be -// in an enabled state. - When read as 0, DW_apb_i2c is deemed -// completely inactive. Note: The CPU can safely read this bit -// anytime. When this bit is read as 0, the CPU can safely read -// SLV_RX_DATA_LOST (bit 2) and SLV_DISABLED_WHILE_BUSY (bit 1). -// -// Reset value: 0x0 -// 0x0 -> I2C disabled -// 0x1 -> I2C enabled -#define I2C_IC_ENABLE_STATUS_IC_EN_RESET _u(0x0) -#define I2C_IC_ENABLE_STATUS_IC_EN_BITS _u(0x00000001) -#define I2C_IC_ENABLE_STATUS_IC_EN_MSB _u(0) -#define I2C_IC_ENABLE_STATUS_IC_EN_LSB _u(0) -#define I2C_IC_ENABLE_STATUS_IC_EN_ACCESS "RO" -#define I2C_IC_ENABLE_STATUS_IC_EN_VALUE_DISABLED _u(0x0) -#define I2C_IC_ENABLE_STATUS_IC_EN_VALUE_ENABLED _u(0x1) -// ============================================================================= -// Register : I2C_IC_FS_SPKLEN -// Description : I2C SS, FS or FM+ spike suppression limit -// -// This register is used to store the duration, measured in ic_clk -// cycles, of the longest spike that is filtered out by the spike -// suppression logic when the component is operating in SS, FS or -// FM+ modes. The relevant I2C requirement is tSP (table 4) as -// detailed in the I2C Bus Specification. This register must be -// programmed with a minimum value of 1. -#define I2C_IC_FS_SPKLEN_OFFSET _u(0x000000a0) -#define I2C_IC_FS_SPKLEN_BITS _u(0x000000ff) -#define I2C_IC_FS_SPKLEN_RESET _u(0x00000007) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_FS_SPKLEN_IC_FS_SPKLEN -// Description : This register must be set before any I2C bus transaction can -// take place to ensure stable operation. This register sets the -// duration, measured in ic_clk cycles, of the longest spike in -// the SCL or SDA lines that will be filtered out by the spike -// suppression logic. This register can be written only when the -// I2C interface is disabled which corresponds to the IC_ENABLE[0] -// register being set to 0. Writes at other times have no effect. -// The minimum valid value is 1; hardware prevents values less -// than this being written, and if attempted results in 1 being -// set. or more information, refer to 'Spike Suppression'. -#define I2C_IC_FS_SPKLEN_IC_FS_SPKLEN_RESET _u(0x07) -#define I2C_IC_FS_SPKLEN_IC_FS_SPKLEN_BITS _u(0x000000ff) -#define I2C_IC_FS_SPKLEN_IC_FS_SPKLEN_MSB _u(7) -#define I2C_IC_FS_SPKLEN_IC_FS_SPKLEN_LSB _u(0) -#define I2C_IC_FS_SPKLEN_IC_FS_SPKLEN_ACCESS "RW" -// ============================================================================= -// Register : I2C_IC_CLR_RESTART_DET -// Description : Clear RESTART_DET Interrupt Register -#define I2C_IC_CLR_RESTART_DET_OFFSET _u(0x000000a8) -#define I2C_IC_CLR_RESTART_DET_BITS _u(0x00000001) -#define I2C_IC_CLR_RESTART_DET_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_CLR_RESTART_DET_CLR_RESTART_DET -// Description : Read this register to clear the RESTART_DET interrupt (bit 12) -// of IC_RAW_INTR_STAT register. -// -// Reset value: 0x0 -#define I2C_IC_CLR_RESTART_DET_CLR_RESTART_DET_RESET _u(0x0) -#define I2C_IC_CLR_RESTART_DET_CLR_RESTART_DET_BITS _u(0x00000001) -#define I2C_IC_CLR_RESTART_DET_CLR_RESTART_DET_MSB _u(0) -#define I2C_IC_CLR_RESTART_DET_CLR_RESTART_DET_LSB _u(0) -#define I2C_IC_CLR_RESTART_DET_CLR_RESTART_DET_ACCESS "RO" -// ============================================================================= -// Register : I2C_IC_COMP_PARAM_1 -// Description : Component Parameter Register 1 -// -// Note This register is not implemented and therefore reads as 0. -// If it was implemented it would be a constant read-only register -// that contains encoded information about the component's -// parameter settings. Fields shown below are the settings for -// those parameters -#define I2C_IC_COMP_PARAM_1_OFFSET _u(0x000000f4) -#define I2C_IC_COMP_PARAM_1_BITS _u(0x00ffffff) -#define I2C_IC_COMP_PARAM_1_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_COMP_PARAM_1_TX_BUFFER_DEPTH -// Description : TX Buffer Depth = 16 -#define I2C_IC_COMP_PARAM_1_TX_BUFFER_DEPTH_RESET _u(0x00) -#define I2C_IC_COMP_PARAM_1_TX_BUFFER_DEPTH_BITS _u(0x00ff0000) -#define I2C_IC_COMP_PARAM_1_TX_BUFFER_DEPTH_MSB _u(23) -#define I2C_IC_COMP_PARAM_1_TX_BUFFER_DEPTH_LSB _u(16) -#define I2C_IC_COMP_PARAM_1_TX_BUFFER_DEPTH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : I2C_IC_COMP_PARAM_1_RX_BUFFER_DEPTH -// Description : RX Buffer Depth = 16 -#define I2C_IC_COMP_PARAM_1_RX_BUFFER_DEPTH_RESET _u(0x00) -#define I2C_IC_COMP_PARAM_1_RX_BUFFER_DEPTH_BITS _u(0x0000ff00) -#define I2C_IC_COMP_PARAM_1_RX_BUFFER_DEPTH_MSB _u(15) -#define I2C_IC_COMP_PARAM_1_RX_BUFFER_DEPTH_LSB _u(8) -#define I2C_IC_COMP_PARAM_1_RX_BUFFER_DEPTH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : I2C_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS -// Description : Encoded parameters not visible -#define I2C_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS_RESET _u(0x0) -#define I2C_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS_BITS _u(0x00000080) -#define I2C_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS_MSB _u(7) -#define I2C_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS_LSB _u(7) -#define I2C_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : I2C_IC_COMP_PARAM_1_HAS_DMA -// Description : DMA handshaking signals are enabled -#define I2C_IC_COMP_PARAM_1_HAS_DMA_RESET _u(0x0) -#define I2C_IC_COMP_PARAM_1_HAS_DMA_BITS _u(0x00000040) -#define I2C_IC_COMP_PARAM_1_HAS_DMA_MSB _u(6) -#define I2C_IC_COMP_PARAM_1_HAS_DMA_LSB _u(6) -#define I2C_IC_COMP_PARAM_1_HAS_DMA_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : I2C_IC_COMP_PARAM_1_INTR_IO -// Description : COMBINED Interrupt outputs -#define I2C_IC_COMP_PARAM_1_INTR_IO_RESET _u(0x0) -#define I2C_IC_COMP_PARAM_1_INTR_IO_BITS _u(0x00000020) -#define I2C_IC_COMP_PARAM_1_INTR_IO_MSB _u(5) -#define I2C_IC_COMP_PARAM_1_INTR_IO_LSB _u(5) -#define I2C_IC_COMP_PARAM_1_INTR_IO_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : I2C_IC_COMP_PARAM_1_HC_COUNT_VALUES -// Description : Programmable count values for each mode. -#define I2C_IC_COMP_PARAM_1_HC_COUNT_VALUES_RESET _u(0x0) -#define I2C_IC_COMP_PARAM_1_HC_COUNT_VALUES_BITS _u(0x00000010) -#define I2C_IC_COMP_PARAM_1_HC_COUNT_VALUES_MSB _u(4) -#define I2C_IC_COMP_PARAM_1_HC_COUNT_VALUES_LSB _u(4) -#define I2C_IC_COMP_PARAM_1_HC_COUNT_VALUES_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE -// Description : MAX SPEED MODE = FAST MODE -#define I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE_RESET _u(0x0) -#define I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE_BITS _u(0x0000000c) -#define I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE_MSB _u(3) -#define I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE_LSB _u(2) -#define I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH -// Description : APB data bus width is 32 bits -#define I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH_RESET _u(0x0) -#define I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH_BITS _u(0x00000003) -#define I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH_MSB _u(1) -#define I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH_LSB _u(0) -#define I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH_ACCESS "RO" -// ============================================================================= -// Register : I2C_IC_COMP_VERSION -// Description : I2C Component Version Register -#define I2C_IC_COMP_VERSION_OFFSET _u(0x000000f8) -#define I2C_IC_COMP_VERSION_BITS _u(0xffffffff) -#define I2C_IC_COMP_VERSION_RESET _u(0x3230312a) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_COMP_VERSION_IC_COMP_VERSION -#define I2C_IC_COMP_VERSION_IC_COMP_VERSION_RESET _u(0x3230312a) -#define I2C_IC_COMP_VERSION_IC_COMP_VERSION_BITS _u(0xffffffff) -#define I2C_IC_COMP_VERSION_IC_COMP_VERSION_MSB _u(31) -#define I2C_IC_COMP_VERSION_IC_COMP_VERSION_LSB _u(0) -#define I2C_IC_COMP_VERSION_IC_COMP_VERSION_ACCESS "RO" -// ============================================================================= -// Register : I2C_IC_COMP_TYPE -// Description : I2C Component Type Register -#define I2C_IC_COMP_TYPE_OFFSET _u(0x000000fc) -#define I2C_IC_COMP_TYPE_BITS _u(0xffffffff) -#define I2C_IC_COMP_TYPE_RESET _u(0x44570140) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_COMP_TYPE_IC_COMP_TYPE -// Description : Designware Component Type number = 0x44_57_01_40. This assigned -// unique hex value is constant and is derived from the two ASCII -// letters 'DW' followed by a 16-bit unsigned number. -#define I2C_IC_COMP_TYPE_IC_COMP_TYPE_RESET _u(0x44570140) -#define I2C_IC_COMP_TYPE_IC_COMP_TYPE_BITS _u(0xffffffff) -#define I2C_IC_COMP_TYPE_IC_COMP_TYPE_MSB _u(31) -#define I2C_IC_COMP_TYPE_IC_COMP_TYPE_LSB _u(0) -#define I2C_IC_COMP_TYPE_IC_COMP_TYPE_ACCESS "RO" -// ============================================================================= -#endif // _HARDWARE_REGS_I2C_H - diff --git a/lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/intctrl.h b/lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/intctrl.h deleted file mode 100644 index 3190b413d0..0000000000 --- a/lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/intctrl.h +++ /dev/null @@ -1,106 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _INTCTRL_H -#define _INTCTRL_H - -/** - * \file rp2040/intctrl.h - */ - -#ifdef __ASSEMBLER__ -#define TIMER_IRQ_0 0 -#define TIMER_IRQ_1 1 -#define TIMER_IRQ_2 2 -#define TIMER_IRQ_3 3 -#define PWM_IRQ_WRAP 4 -#define USBCTRL_IRQ 5 -#define XIP_IRQ 6 -#define PIO0_IRQ_0 7 -#define PIO0_IRQ_1 8 -#define PIO1_IRQ_0 9 -#define PIO1_IRQ_1 10 -#define DMA_IRQ_0 11 -#define DMA_IRQ_1 12 -#define IO_IRQ_BANK0 13 -#define IO_IRQ_QSPI 14 -#define SIO_IRQ_PROC0 15 -#define SIO_IRQ_PROC1 16 -#define CLOCKS_IRQ 17 -#define SPI0_IRQ 18 -#define SPI1_IRQ 19 -#define UART0_IRQ 20 -#define UART1_IRQ 21 -#define ADC_IRQ_FIFO 22 -#define I2C0_IRQ 23 -#define I2C1_IRQ 24 -#define RTC_IRQ 25 -#else -/** - * \brief Interrupt numbers on RP2040 (used as typedef \ref irq_num_t) - * \ingroup hardware_irq - */ -typedef enum irq_num_rp2040 { - TIMER_IRQ_0 = 0, ///< Select TIMER's IRQ 0 output - TIMER_IRQ_1 = 1, ///< Select TIMER's IRQ 1 output - TIMER_IRQ_2 = 2, ///< Select TIMER's IRQ 2 output - TIMER_IRQ_3 = 3, ///< Select TIMER's IRQ 3 output - PWM_IRQ_WRAP = 4, ///< Select PWM's IRQ_WRAP output - USBCTRL_IRQ = 5, ///< Select USBCTRL's IRQ output - XIP_IRQ = 6, ///< Select XIP's IRQ output - PIO0_IRQ_0 = 7, ///< Select PIO0's IRQ 0 output - PIO0_IRQ_1 = 8, ///< Select PIO0's IRQ 1 output - PIO1_IRQ_0 = 9, ///< Select PIO1's IRQ 0 output - PIO1_IRQ_1 = 10, ///< Select PIO1's IRQ 1 output - DMA_IRQ_0 = 11, ///< Select DMA's IRQ 0 output - DMA_IRQ_1 = 12, ///< Select DMA's IRQ 1 output - IO_IRQ_BANK0 = 13, ///< Select IO_BANK0's IRQ output - IO_IRQ_QSPI = 14, ///< Select IO_QSPI's IRQ output - SIO_IRQ_PROC0 = 15, ///< Select SIO_PROC0's IRQ output - SIO_IRQ_PROC1 = 16, ///< Select SIO_PROC1's IRQ output - CLOCKS_IRQ = 17, ///< Select CLOCKS's IRQ output - SPI0_IRQ = 18, ///< Select SPI0's IRQ output - SPI1_IRQ = 19, ///< Select SPI1's IRQ output - UART0_IRQ = 20, ///< Select UART0's IRQ output - UART1_IRQ = 21, ///< Select UART1's IRQ output - ADC_IRQ_FIFO = 22, ///< Select ADC's IRQ_FIFO output - I2C0_IRQ = 23, ///< Select I2C0's IRQ output - I2C1_IRQ = 24, ///< Select I2C1's IRQ output - RTC_IRQ = 25, ///< Select RTC's IRQ output - IRQ_COUNT -} irq_num_t; -#endif - -#define isr_timer_0 isr_irq0 -#define isr_timer_1 isr_irq1 -#define isr_timer_2 isr_irq2 -#define isr_timer_3 isr_irq3 -#define isr_pwm_wrap isr_irq4 -#define isr_usbctrl isr_irq5 -#define isr_xip isr_irq6 -#define isr_pio0_0 isr_irq7 -#define isr_pio0_1 isr_irq8 -#define isr_pio1_0 isr_irq9 -#define isr_pio1_1 isr_irq10 -#define isr_dma_0 isr_irq11 -#define isr_dma_1 isr_irq12 -#define isr_io_bank0 isr_irq13 -#define isr_io_qspi isr_irq14 -#define isr_sio_proc0 isr_irq15 -#define isr_sio_proc1 isr_irq16 -#define isr_clocks isr_irq17 -#define isr_spi0 isr_irq18 -#define isr_spi1 isr_irq19 -#define isr_uart0 isr_irq20 -#define isr_uart1 isr_irq21 -#define isr_adc_fifo isr_irq22 -#define isr_i2c0 isr_irq23 -#define isr_i2c1 isr_irq24 -#define isr_rtc isr_irq25 - -#endif // _INTCTRL_H - diff --git a/lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/io_bank0.h b/lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/io_bank0.h deleted file mode 100644 index c0ebaf9f90..0000000000 --- a/lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/io_bank0.h +++ /dev/null @@ -1,13649 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -// ============================================================================= -// Register block : IO_BANK0 -// Version : 1 -// Bus type : apb -// ============================================================================= -#ifndef _HARDWARE_REGS_IO_BANK0_H -#define _HARDWARE_REGS_IO_BANK0_H -// ============================================================================= -// Register : IO_BANK0_GPIO0_STATUS -// Description : GPIO status -#define IO_BANK0_GPIO0_STATUS_OFFSET _u(0x00000000) -#define IO_BANK0_GPIO0_STATUS_BITS _u(0x050a3300) -#define IO_BANK0_GPIO0_STATUS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO0_STATUS_IRQTOPROC -// Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO0_STATUS_IRQTOPROC_RESET _u(0x0) -#define IO_BANK0_GPIO0_STATUS_IRQTOPROC_BITS _u(0x04000000) -#define IO_BANK0_GPIO0_STATUS_IRQTOPROC_MSB _u(26) -#define IO_BANK0_GPIO0_STATUS_IRQTOPROC_LSB _u(26) -#define IO_BANK0_GPIO0_STATUS_IRQTOPROC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO0_STATUS_IRQFROMPAD -// Description : interrupt from pad before override is applied -#define IO_BANK0_GPIO0_STATUS_IRQFROMPAD_RESET _u(0x0) -#define IO_BANK0_GPIO0_STATUS_IRQFROMPAD_BITS _u(0x01000000) -#define IO_BANK0_GPIO0_STATUS_IRQFROMPAD_MSB _u(24) -#define IO_BANK0_GPIO0_STATUS_IRQFROMPAD_LSB _u(24) -#define IO_BANK0_GPIO0_STATUS_IRQFROMPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO0_STATUS_INTOPERI -// Description : input signal to peripheral, after override is applied -#define IO_BANK0_GPIO0_STATUS_INTOPERI_RESET _u(0x0) -#define IO_BANK0_GPIO0_STATUS_INTOPERI_BITS _u(0x00080000) -#define IO_BANK0_GPIO0_STATUS_INTOPERI_MSB _u(19) -#define IO_BANK0_GPIO0_STATUS_INTOPERI_LSB _u(19) -#define IO_BANK0_GPIO0_STATUS_INTOPERI_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO0_STATUS_INFROMPAD -// Description : input signal from pad, before override is applied -#define IO_BANK0_GPIO0_STATUS_INFROMPAD_RESET _u(0x0) -#define IO_BANK0_GPIO0_STATUS_INFROMPAD_BITS _u(0x00020000) -#define IO_BANK0_GPIO0_STATUS_INFROMPAD_MSB _u(17) -#define IO_BANK0_GPIO0_STATUS_INFROMPAD_LSB _u(17) -#define IO_BANK0_GPIO0_STATUS_INFROMPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO0_STATUS_OETOPAD -// Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO0_STATUS_OETOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO0_STATUS_OETOPAD_BITS _u(0x00002000) -#define IO_BANK0_GPIO0_STATUS_OETOPAD_MSB _u(13) -#define IO_BANK0_GPIO0_STATUS_OETOPAD_LSB _u(13) -#define IO_BANK0_GPIO0_STATUS_OETOPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO0_STATUS_OEFROMPERI -// Description : output enable from selected peripheral, before register -// override is applied -#define IO_BANK0_GPIO0_STATUS_OEFROMPERI_RESET _u(0x0) -#define IO_BANK0_GPIO0_STATUS_OEFROMPERI_BITS _u(0x00001000) -#define IO_BANK0_GPIO0_STATUS_OEFROMPERI_MSB _u(12) -#define IO_BANK0_GPIO0_STATUS_OEFROMPERI_LSB _u(12) -#define IO_BANK0_GPIO0_STATUS_OEFROMPERI_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO0_STATUS_OUTTOPAD -// Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO0_STATUS_OUTTOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO0_STATUS_OUTTOPAD_BITS _u(0x00000200) -#define IO_BANK0_GPIO0_STATUS_OUTTOPAD_MSB _u(9) -#define IO_BANK0_GPIO0_STATUS_OUTTOPAD_LSB _u(9) -#define IO_BANK0_GPIO0_STATUS_OUTTOPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO0_STATUS_OUTFROMPERI -// Description : output signal from selected peripheral, before register -// override is applied -#define IO_BANK0_GPIO0_STATUS_OUTFROMPERI_RESET _u(0x0) -#define IO_BANK0_GPIO0_STATUS_OUTFROMPERI_BITS _u(0x00000100) -#define IO_BANK0_GPIO0_STATUS_OUTFROMPERI_MSB _u(8) -#define IO_BANK0_GPIO0_STATUS_OUTFROMPERI_LSB _u(8) -#define IO_BANK0_GPIO0_STATUS_OUTFROMPERI_ACCESS "RO" -// ============================================================================= -// Register : IO_BANK0_GPIO0_CTRL -// Description : GPIO control including function select and overrides. -#define IO_BANK0_GPIO0_CTRL_OFFSET _u(0x00000004) -#define IO_BANK0_GPIO0_CTRL_BITS _u(0x3003331f) -#define IO_BANK0_GPIO0_CTRL_RESET _u(0x0000001f) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO0_CTRL_IRQOVER -// 0x0 -> don't invert the interrupt -// 0x1 -> invert the interrupt -// 0x2 -> drive interrupt low -// 0x3 -> drive interrupt high -#define IO_BANK0_GPIO0_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO0_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO0_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO0_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO0_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO0_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO0_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO0_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO0_CTRL_IRQOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO0_CTRL_INOVER -// 0x0 -> don't invert the peri input -// 0x1 -> invert the peri input -// 0x2 -> drive peri input low -// 0x3 -> drive peri input high -#define IO_BANK0_GPIO0_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO0_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO0_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO0_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO0_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO0_CTRL_INOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO0_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO0_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO0_CTRL_INOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO0_CTRL_OEOVER -// 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel -// 0x2 -> disable output -// 0x3 -> enable output -#define IO_BANK0_GPIO0_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO0_CTRL_OEOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO0_CTRL_OEOVER_MSB _u(13) -#define IO_BANK0_GPIO0_CTRL_OEOVER_LSB _u(12) -#define IO_BANK0_GPIO0_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO0_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO0_CTRL_OEOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO0_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO0_CTRL_OEOVER_VALUE_ENABLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO0_CTRL_OUTOVER -// 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel -// 0x2 -> drive output low -// 0x3 -> drive output high -#define IO_BANK0_GPIO0_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO0_CTRL_OUTOVER_BITS _u(0x00000300) -#define IO_BANK0_GPIO0_CTRL_OUTOVER_MSB _u(9) -#define IO_BANK0_GPIO0_CTRL_OUTOVER_LSB _u(8) -#define IO_BANK0_GPIO0_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO0_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO0_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO0_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO0_CTRL_OUTOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO0_CTRL_FUNCSEL -// Description : 0-31 -> selects pin function according to the gpio table -// 31 == NULL -// 0x00 -> jtag_tck -// 0x01 -> spi0_rx -// 0x02 -> uart0_tx -// 0x03 -> i2c0_sda -// 0x04 -> pwm_a_0 -// 0x05 -> sio_0 -// 0x06 -> pio0_0 -// 0x07 -> pio1_0 -// 0x09 -> usb_muxing_overcurr_detect -// 0x1f -> null -#define IO_BANK0_GPIO0_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO0_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO0_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO0_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO0_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_JTAG_TCK _u(0x00) -#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_SPI0_RX _u(0x01) -#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_UART0_TX _u(0x02) -#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03) -#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_PWM_A_0 _u(0x04) -#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_SIO_0 _u(0x05) -#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_PIO0_0 _u(0x06) -#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_PIO1_0 _u(0x07) -#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x09) -#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) -// ============================================================================= -// Register : IO_BANK0_GPIO1_STATUS -// Description : GPIO status -#define IO_BANK0_GPIO1_STATUS_OFFSET _u(0x00000008) -#define IO_BANK0_GPIO1_STATUS_BITS _u(0x050a3300) -#define IO_BANK0_GPIO1_STATUS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO1_STATUS_IRQTOPROC -// Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO1_STATUS_IRQTOPROC_RESET _u(0x0) -#define IO_BANK0_GPIO1_STATUS_IRQTOPROC_BITS _u(0x04000000) -#define IO_BANK0_GPIO1_STATUS_IRQTOPROC_MSB _u(26) -#define IO_BANK0_GPIO1_STATUS_IRQTOPROC_LSB _u(26) -#define IO_BANK0_GPIO1_STATUS_IRQTOPROC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO1_STATUS_IRQFROMPAD -// Description : interrupt from pad before override is applied -#define IO_BANK0_GPIO1_STATUS_IRQFROMPAD_RESET _u(0x0) -#define IO_BANK0_GPIO1_STATUS_IRQFROMPAD_BITS _u(0x01000000) -#define IO_BANK0_GPIO1_STATUS_IRQFROMPAD_MSB _u(24) -#define IO_BANK0_GPIO1_STATUS_IRQFROMPAD_LSB _u(24) -#define IO_BANK0_GPIO1_STATUS_IRQFROMPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO1_STATUS_INTOPERI -// Description : input signal to peripheral, after override is applied -#define IO_BANK0_GPIO1_STATUS_INTOPERI_RESET _u(0x0) -#define IO_BANK0_GPIO1_STATUS_INTOPERI_BITS _u(0x00080000) -#define IO_BANK0_GPIO1_STATUS_INTOPERI_MSB _u(19) -#define IO_BANK0_GPIO1_STATUS_INTOPERI_LSB _u(19) -#define IO_BANK0_GPIO1_STATUS_INTOPERI_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO1_STATUS_INFROMPAD -// Description : input signal from pad, before override is applied -#define IO_BANK0_GPIO1_STATUS_INFROMPAD_RESET _u(0x0) -#define IO_BANK0_GPIO1_STATUS_INFROMPAD_BITS _u(0x00020000) -#define IO_BANK0_GPIO1_STATUS_INFROMPAD_MSB _u(17) -#define IO_BANK0_GPIO1_STATUS_INFROMPAD_LSB _u(17) -#define IO_BANK0_GPIO1_STATUS_INFROMPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO1_STATUS_OETOPAD -// Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO1_STATUS_OETOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO1_STATUS_OETOPAD_BITS _u(0x00002000) -#define IO_BANK0_GPIO1_STATUS_OETOPAD_MSB _u(13) -#define IO_BANK0_GPIO1_STATUS_OETOPAD_LSB _u(13) -#define IO_BANK0_GPIO1_STATUS_OETOPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO1_STATUS_OEFROMPERI -// Description : output enable from selected peripheral, before register -// override is applied -#define IO_BANK0_GPIO1_STATUS_OEFROMPERI_RESET _u(0x0) -#define IO_BANK0_GPIO1_STATUS_OEFROMPERI_BITS _u(0x00001000) -#define IO_BANK0_GPIO1_STATUS_OEFROMPERI_MSB _u(12) -#define IO_BANK0_GPIO1_STATUS_OEFROMPERI_LSB _u(12) -#define IO_BANK0_GPIO1_STATUS_OEFROMPERI_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO1_STATUS_OUTTOPAD -// Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO1_STATUS_OUTTOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO1_STATUS_OUTTOPAD_BITS _u(0x00000200) -#define IO_BANK0_GPIO1_STATUS_OUTTOPAD_MSB _u(9) -#define IO_BANK0_GPIO1_STATUS_OUTTOPAD_LSB _u(9) -#define IO_BANK0_GPIO1_STATUS_OUTTOPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO1_STATUS_OUTFROMPERI -// Description : output signal from selected peripheral, before register -// override is applied -#define IO_BANK0_GPIO1_STATUS_OUTFROMPERI_RESET _u(0x0) -#define IO_BANK0_GPIO1_STATUS_OUTFROMPERI_BITS _u(0x00000100) -#define IO_BANK0_GPIO1_STATUS_OUTFROMPERI_MSB _u(8) -#define IO_BANK0_GPIO1_STATUS_OUTFROMPERI_LSB _u(8) -#define IO_BANK0_GPIO1_STATUS_OUTFROMPERI_ACCESS "RO" -// ============================================================================= -// Register : IO_BANK0_GPIO1_CTRL -// Description : GPIO control including function select and overrides. -#define IO_BANK0_GPIO1_CTRL_OFFSET _u(0x0000000c) -#define IO_BANK0_GPIO1_CTRL_BITS _u(0x3003331f) -#define IO_BANK0_GPIO1_CTRL_RESET _u(0x0000001f) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO1_CTRL_IRQOVER -// 0x0 -> don't invert the interrupt -// 0x1 -> invert the interrupt -// 0x2 -> drive interrupt low -// 0x3 -> drive interrupt high -#define IO_BANK0_GPIO1_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO1_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO1_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO1_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO1_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO1_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO1_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO1_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO1_CTRL_IRQOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO1_CTRL_INOVER -// 0x0 -> don't invert the peri input -// 0x1 -> invert the peri input -// 0x2 -> drive peri input low -// 0x3 -> drive peri input high -#define IO_BANK0_GPIO1_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO1_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO1_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO1_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO1_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO1_CTRL_INOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO1_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO1_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO1_CTRL_INOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO1_CTRL_OEOVER -// 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel -// 0x2 -> disable output -// 0x3 -> enable output -#define IO_BANK0_GPIO1_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO1_CTRL_OEOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO1_CTRL_OEOVER_MSB _u(13) -#define IO_BANK0_GPIO1_CTRL_OEOVER_LSB _u(12) -#define IO_BANK0_GPIO1_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO1_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO1_CTRL_OEOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO1_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO1_CTRL_OEOVER_VALUE_ENABLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO1_CTRL_OUTOVER -// 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel -// 0x2 -> drive output low -// 0x3 -> drive output high -#define IO_BANK0_GPIO1_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO1_CTRL_OUTOVER_BITS _u(0x00000300) -#define IO_BANK0_GPIO1_CTRL_OUTOVER_MSB _u(9) -#define IO_BANK0_GPIO1_CTRL_OUTOVER_LSB _u(8) -#define IO_BANK0_GPIO1_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO1_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO1_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO1_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO1_CTRL_OUTOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO1_CTRL_FUNCSEL -// Description : 0-31 -> selects pin function according to the gpio table -// 31 == NULL -// 0x00 -> jtag_tms -// 0x01 -> spi0_ss_n -// 0x02 -> uart0_rx -// 0x03 -> i2c0_scl -// 0x04 -> pwm_b_0 -// 0x05 -> sio_1 -// 0x06 -> pio0_1 -// 0x07 -> pio1_1 -// 0x09 -> usb_muxing_vbus_detect -// 0x1f -> null -#define IO_BANK0_GPIO1_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO1_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO1_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO1_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO1_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_JTAG_TMS _u(0x00) -#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_SPI0_SS_N _u(0x01) -#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_UART0_RX _u(0x02) -#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03) -#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_PWM_B_0 _u(0x04) -#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_SIO_1 _u(0x05) -#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_PIO0_1 _u(0x06) -#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_PIO1_1 _u(0x07) -#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x09) -#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) -// ============================================================================= -// Register : IO_BANK0_GPIO2_STATUS -// Description : GPIO status -#define IO_BANK0_GPIO2_STATUS_OFFSET _u(0x00000010) -#define IO_BANK0_GPIO2_STATUS_BITS _u(0x050a3300) -#define IO_BANK0_GPIO2_STATUS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO2_STATUS_IRQTOPROC -// Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO2_STATUS_IRQTOPROC_RESET _u(0x0) -#define IO_BANK0_GPIO2_STATUS_IRQTOPROC_BITS _u(0x04000000) -#define IO_BANK0_GPIO2_STATUS_IRQTOPROC_MSB _u(26) -#define IO_BANK0_GPIO2_STATUS_IRQTOPROC_LSB _u(26) -#define IO_BANK0_GPIO2_STATUS_IRQTOPROC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO2_STATUS_IRQFROMPAD -// Description : interrupt from pad before override is applied -#define IO_BANK0_GPIO2_STATUS_IRQFROMPAD_RESET _u(0x0) -#define IO_BANK0_GPIO2_STATUS_IRQFROMPAD_BITS _u(0x01000000) -#define IO_BANK0_GPIO2_STATUS_IRQFROMPAD_MSB _u(24) -#define IO_BANK0_GPIO2_STATUS_IRQFROMPAD_LSB _u(24) -#define IO_BANK0_GPIO2_STATUS_IRQFROMPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO2_STATUS_INTOPERI -// Description : input signal to peripheral, after override is applied -#define IO_BANK0_GPIO2_STATUS_INTOPERI_RESET _u(0x0) -#define IO_BANK0_GPIO2_STATUS_INTOPERI_BITS _u(0x00080000) -#define IO_BANK0_GPIO2_STATUS_INTOPERI_MSB _u(19) -#define IO_BANK0_GPIO2_STATUS_INTOPERI_LSB _u(19) -#define IO_BANK0_GPIO2_STATUS_INTOPERI_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO2_STATUS_INFROMPAD -// Description : input signal from pad, before override is applied -#define IO_BANK0_GPIO2_STATUS_INFROMPAD_RESET _u(0x0) -#define IO_BANK0_GPIO2_STATUS_INFROMPAD_BITS _u(0x00020000) -#define IO_BANK0_GPIO2_STATUS_INFROMPAD_MSB _u(17) -#define IO_BANK0_GPIO2_STATUS_INFROMPAD_LSB _u(17) -#define IO_BANK0_GPIO2_STATUS_INFROMPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO2_STATUS_OETOPAD -// Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO2_STATUS_OETOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO2_STATUS_OETOPAD_BITS _u(0x00002000) -#define IO_BANK0_GPIO2_STATUS_OETOPAD_MSB _u(13) -#define IO_BANK0_GPIO2_STATUS_OETOPAD_LSB _u(13) -#define IO_BANK0_GPIO2_STATUS_OETOPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO2_STATUS_OEFROMPERI -// Description : output enable from selected peripheral, before register -// override is applied -#define IO_BANK0_GPIO2_STATUS_OEFROMPERI_RESET _u(0x0) -#define IO_BANK0_GPIO2_STATUS_OEFROMPERI_BITS _u(0x00001000) -#define IO_BANK0_GPIO2_STATUS_OEFROMPERI_MSB _u(12) -#define IO_BANK0_GPIO2_STATUS_OEFROMPERI_LSB _u(12) -#define IO_BANK0_GPIO2_STATUS_OEFROMPERI_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO2_STATUS_OUTTOPAD -// Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO2_STATUS_OUTTOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO2_STATUS_OUTTOPAD_BITS _u(0x00000200) -#define IO_BANK0_GPIO2_STATUS_OUTTOPAD_MSB _u(9) -#define IO_BANK0_GPIO2_STATUS_OUTTOPAD_LSB _u(9) -#define IO_BANK0_GPIO2_STATUS_OUTTOPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO2_STATUS_OUTFROMPERI -// Description : output signal from selected peripheral, before register -// override is applied -#define IO_BANK0_GPIO2_STATUS_OUTFROMPERI_RESET _u(0x0) -#define IO_BANK0_GPIO2_STATUS_OUTFROMPERI_BITS _u(0x00000100) -#define IO_BANK0_GPIO2_STATUS_OUTFROMPERI_MSB _u(8) -#define IO_BANK0_GPIO2_STATUS_OUTFROMPERI_LSB _u(8) -#define IO_BANK0_GPIO2_STATUS_OUTFROMPERI_ACCESS "RO" -// ============================================================================= -// Register : IO_BANK0_GPIO2_CTRL -// Description : GPIO control including function select and overrides. -#define IO_BANK0_GPIO2_CTRL_OFFSET _u(0x00000014) -#define IO_BANK0_GPIO2_CTRL_BITS _u(0x3003331f) -#define IO_BANK0_GPIO2_CTRL_RESET _u(0x0000001f) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO2_CTRL_IRQOVER -// 0x0 -> don't invert the interrupt -// 0x1 -> invert the interrupt -// 0x2 -> drive interrupt low -// 0x3 -> drive interrupt high -#define IO_BANK0_GPIO2_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO2_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO2_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO2_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO2_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO2_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO2_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO2_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO2_CTRL_IRQOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO2_CTRL_INOVER -// 0x0 -> don't invert the peri input -// 0x1 -> invert the peri input -// 0x2 -> drive peri input low -// 0x3 -> drive peri input high -#define IO_BANK0_GPIO2_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO2_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO2_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO2_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO2_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO2_CTRL_INOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO2_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO2_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO2_CTRL_INOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO2_CTRL_OEOVER -// 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel -// 0x2 -> disable output -// 0x3 -> enable output -#define IO_BANK0_GPIO2_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO2_CTRL_OEOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO2_CTRL_OEOVER_MSB _u(13) -#define IO_BANK0_GPIO2_CTRL_OEOVER_LSB _u(12) -#define IO_BANK0_GPIO2_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO2_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO2_CTRL_OEOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO2_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO2_CTRL_OEOVER_VALUE_ENABLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO2_CTRL_OUTOVER -// 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel -// 0x2 -> drive output low -// 0x3 -> drive output high -#define IO_BANK0_GPIO2_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO2_CTRL_OUTOVER_BITS _u(0x00000300) -#define IO_BANK0_GPIO2_CTRL_OUTOVER_MSB _u(9) -#define IO_BANK0_GPIO2_CTRL_OUTOVER_LSB _u(8) -#define IO_BANK0_GPIO2_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO2_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO2_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO2_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO2_CTRL_OUTOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO2_CTRL_FUNCSEL -// Description : 0-31 -> selects pin function according to the gpio table -// 31 == NULL -// 0x00 -> jtag_tdi -// 0x01 -> spi0_sclk -// 0x02 -> uart0_cts -// 0x03 -> i2c1_sda -// 0x04 -> pwm_a_1 -// 0x05 -> sio_2 -// 0x06 -> pio0_2 -// 0x07 -> pio1_2 -// 0x09 -> usb_muxing_vbus_en -// 0x1f -> null -#define IO_BANK0_GPIO2_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO2_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO2_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO2_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO2_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_JTAG_TDI _u(0x00) -#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_SPI0_SCLK _u(0x01) -#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_UART0_CTS _u(0x02) -#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03) -#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_PWM_A_1 _u(0x04) -#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_SIO_2 _u(0x05) -#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_PIO0_2 _u(0x06) -#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_PIO1_2 _u(0x07) -#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x09) -#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) -// ============================================================================= -// Register : IO_BANK0_GPIO3_STATUS -// Description : GPIO status -#define IO_BANK0_GPIO3_STATUS_OFFSET _u(0x00000018) -#define IO_BANK0_GPIO3_STATUS_BITS _u(0x050a3300) -#define IO_BANK0_GPIO3_STATUS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO3_STATUS_IRQTOPROC -// Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO3_STATUS_IRQTOPROC_RESET _u(0x0) -#define IO_BANK0_GPIO3_STATUS_IRQTOPROC_BITS _u(0x04000000) -#define IO_BANK0_GPIO3_STATUS_IRQTOPROC_MSB _u(26) -#define IO_BANK0_GPIO3_STATUS_IRQTOPROC_LSB _u(26) -#define IO_BANK0_GPIO3_STATUS_IRQTOPROC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO3_STATUS_IRQFROMPAD -// Description : interrupt from pad before override is applied -#define IO_BANK0_GPIO3_STATUS_IRQFROMPAD_RESET _u(0x0) -#define IO_BANK0_GPIO3_STATUS_IRQFROMPAD_BITS _u(0x01000000) -#define IO_BANK0_GPIO3_STATUS_IRQFROMPAD_MSB _u(24) -#define IO_BANK0_GPIO3_STATUS_IRQFROMPAD_LSB _u(24) -#define IO_BANK0_GPIO3_STATUS_IRQFROMPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO3_STATUS_INTOPERI -// Description : input signal to peripheral, after override is applied -#define IO_BANK0_GPIO3_STATUS_INTOPERI_RESET _u(0x0) -#define IO_BANK0_GPIO3_STATUS_INTOPERI_BITS _u(0x00080000) -#define IO_BANK0_GPIO3_STATUS_INTOPERI_MSB _u(19) -#define IO_BANK0_GPIO3_STATUS_INTOPERI_LSB _u(19) -#define IO_BANK0_GPIO3_STATUS_INTOPERI_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO3_STATUS_INFROMPAD -// Description : input signal from pad, before override is applied -#define IO_BANK0_GPIO3_STATUS_INFROMPAD_RESET _u(0x0) -#define IO_BANK0_GPIO3_STATUS_INFROMPAD_BITS _u(0x00020000) -#define IO_BANK0_GPIO3_STATUS_INFROMPAD_MSB _u(17) -#define IO_BANK0_GPIO3_STATUS_INFROMPAD_LSB _u(17) -#define IO_BANK0_GPIO3_STATUS_INFROMPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO3_STATUS_OETOPAD -// Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO3_STATUS_OETOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO3_STATUS_OETOPAD_BITS _u(0x00002000) -#define IO_BANK0_GPIO3_STATUS_OETOPAD_MSB _u(13) -#define IO_BANK0_GPIO3_STATUS_OETOPAD_LSB _u(13) -#define IO_BANK0_GPIO3_STATUS_OETOPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO3_STATUS_OEFROMPERI -// Description : output enable from selected peripheral, before register -// override is applied -#define IO_BANK0_GPIO3_STATUS_OEFROMPERI_RESET _u(0x0) -#define IO_BANK0_GPIO3_STATUS_OEFROMPERI_BITS _u(0x00001000) -#define IO_BANK0_GPIO3_STATUS_OEFROMPERI_MSB _u(12) -#define IO_BANK0_GPIO3_STATUS_OEFROMPERI_LSB _u(12) -#define IO_BANK0_GPIO3_STATUS_OEFROMPERI_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO3_STATUS_OUTTOPAD -// Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO3_STATUS_OUTTOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO3_STATUS_OUTTOPAD_BITS _u(0x00000200) -#define IO_BANK0_GPIO3_STATUS_OUTTOPAD_MSB _u(9) -#define IO_BANK0_GPIO3_STATUS_OUTTOPAD_LSB _u(9) -#define IO_BANK0_GPIO3_STATUS_OUTTOPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO3_STATUS_OUTFROMPERI -// Description : output signal from selected peripheral, before register -// override is applied -#define IO_BANK0_GPIO3_STATUS_OUTFROMPERI_RESET _u(0x0) -#define IO_BANK0_GPIO3_STATUS_OUTFROMPERI_BITS _u(0x00000100) -#define IO_BANK0_GPIO3_STATUS_OUTFROMPERI_MSB _u(8) -#define IO_BANK0_GPIO3_STATUS_OUTFROMPERI_LSB _u(8) -#define IO_BANK0_GPIO3_STATUS_OUTFROMPERI_ACCESS "RO" -// ============================================================================= -// Register : IO_BANK0_GPIO3_CTRL -// Description : GPIO control including function select and overrides. -#define IO_BANK0_GPIO3_CTRL_OFFSET _u(0x0000001c) -#define IO_BANK0_GPIO3_CTRL_BITS _u(0x3003331f) -#define IO_BANK0_GPIO3_CTRL_RESET _u(0x0000001f) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO3_CTRL_IRQOVER -// 0x0 -> don't invert the interrupt -// 0x1 -> invert the interrupt -// 0x2 -> drive interrupt low -// 0x3 -> drive interrupt high -#define IO_BANK0_GPIO3_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO3_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO3_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO3_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO3_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO3_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO3_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO3_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO3_CTRL_IRQOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO3_CTRL_INOVER -// 0x0 -> don't invert the peri input -// 0x1 -> invert the peri input -// 0x2 -> drive peri input low -// 0x3 -> drive peri input high -#define IO_BANK0_GPIO3_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO3_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO3_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO3_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO3_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO3_CTRL_INOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO3_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO3_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO3_CTRL_INOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO3_CTRL_OEOVER -// 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel -// 0x2 -> disable output -// 0x3 -> enable output -#define IO_BANK0_GPIO3_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO3_CTRL_OEOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO3_CTRL_OEOVER_MSB _u(13) -#define IO_BANK0_GPIO3_CTRL_OEOVER_LSB _u(12) -#define IO_BANK0_GPIO3_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO3_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO3_CTRL_OEOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO3_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO3_CTRL_OEOVER_VALUE_ENABLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO3_CTRL_OUTOVER -// 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel -// 0x2 -> drive output low -// 0x3 -> drive output high -#define IO_BANK0_GPIO3_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO3_CTRL_OUTOVER_BITS _u(0x00000300) -#define IO_BANK0_GPIO3_CTRL_OUTOVER_MSB _u(9) -#define IO_BANK0_GPIO3_CTRL_OUTOVER_LSB _u(8) -#define IO_BANK0_GPIO3_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO3_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO3_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO3_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO3_CTRL_OUTOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO3_CTRL_FUNCSEL -// Description : 0-31 -> selects pin function according to the gpio table -// 31 == NULL -// 0x00 -> jtag_tdo -// 0x01 -> spi0_tx -// 0x02 -> uart0_rts -// 0x03 -> i2c1_scl -// 0x04 -> pwm_b_1 -// 0x05 -> sio_3 -// 0x06 -> pio0_3 -// 0x07 -> pio1_3 -// 0x09 -> usb_muxing_overcurr_detect -// 0x1f -> null -#define IO_BANK0_GPIO3_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO3_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO3_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO3_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO3_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_JTAG_TDO _u(0x00) -#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_SPI0_TX _u(0x01) -#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_UART0_RTS _u(0x02) -#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03) -#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_PWM_B_1 _u(0x04) -#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_SIO_3 _u(0x05) -#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_PIO0_3 _u(0x06) -#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_PIO1_3 _u(0x07) -#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x09) -#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) -// ============================================================================= -// Register : IO_BANK0_GPIO4_STATUS -// Description : GPIO status -#define IO_BANK0_GPIO4_STATUS_OFFSET _u(0x00000020) -#define IO_BANK0_GPIO4_STATUS_BITS _u(0x050a3300) -#define IO_BANK0_GPIO4_STATUS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO4_STATUS_IRQTOPROC -// Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO4_STATUS_IRQTOPROC_RESET _u(0x0) -#define IO_BANK0_GPIO4_STATUS_IRQTOPROC_BITS _u(0x04000000) -#define IO_BANK0_GPIO4_STATUS_IRQTOPROC_MSB _u(26) -#define IO_BANK0_GPIO4_STATUS_IRQTOPROC_LSB _u(26) -#define IO_BANK0_GPIO4_STATUS_IRQTOPROC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO4_STATUS_IRQFROMPAD -// Description : interrupt from pad before override is applied -#define IO_BANK0_GPIO4_STATUS_IRQFROMPAD_RESET _u(0x0) -#define IO_BANK0_GPIO4_STATUS_IRQFROMPAD_BITS _u(0x01000000) -#define IO_BANK0_GPIO4_STATUS_IRQFROMPAD_MSB _u(24) -#define IO_BANK0_GPIO4_STATUS_IRQFROMPAD_LSB _u(24) -#define IO_BANK0_GPIO4_STATUS_IRQFROMPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO4_STATUS_INTOPERI -// Description : input signal to peripheral, after override is applied -#define IO_BANK0_GPIO4_STATUS_INTOPERI_RESET _u(0x0) -#define IO_BANK0_GPIO4_STATUS_INTOPERI_BITS _u(0x00080000) -#define IO_BANK0_GPIO4_STATUS_INTOPERI_MSB _u(19) -#define IO_BANK0_GPIO4_STATUS_INTOPERI_LSB _u(19) -#define IO_BANK0_GPIO4_STATUS_INTOPERI_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO4_STATUS_INFROMPAD -// Description : input signal from pad, before override is applied -#define IO_BANK0_GPIO4_STATUS_INFROMPAD_RESET _u(0x0) -#define IO_BANK0_GPIO4_STATUS_INFROMPAD_BITS _u(0x00020000) -#define IO_BANK0_GPIO4_STATUS_INFROMPAD_MSB _u(17) -#define IO_BANK0_GPIO4_STATUS_INFROMPAD_LSB _u(17) -#define IO_BANK0_GPIO4_STATUS_INFROMPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO4_STATUS_OETOPAD -// Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO4_STATUS_OETOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO4_STATUS_OETOPAD_BITS _u(0x00002000) -#define IO_BANK0_GPIO4_STATUS_OETOPAD_MSB _u(13) -#define IO_BANK0_GPIO4_STATUS_OETOPAD_LSB _u(13) -#define IO_BANK0_GPIO4_STATUS_OETOPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO4_STATUS_OEFROMPERI -// Description : output enable from selected peripheral, before register -// override is applied -#define IO_BANK0_GPIO4_STATUS_OEFROMPERI_RESET _u(0x0) -#define IO_BANK0_GPIO4_STATUS_OEFROMPERI_BITS _u(0x00001000) -#define IO_BANK0_GPIO4_STATUS_OEFROMPERI_MSB _u(12) -#define IO_BANK0_GPIO4_STATUS_OEFROMPERI_LSB _u(12) -#define IO_BANK0_GPIO4_STATUS_OEFROMPERI_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO4_STATUS_OUTTOPAD -// Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO4_STATUS_OUTTOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO4_STATUS_OUTTOPAD_BITS _u(0x00000200) -#define IO_BANK0_GPIO4_STATUS_OUTTOPAD_MSB _u(9) -#define IO_BANK0_GPIO4_STATUS_OUTTOPAD_LSB _u(9) -#define IO_BANK0_GPIO4_STATUS_OUTTOPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO4_STATUS_OUTFROMPERI -// Description : output signal from selected peripheral, before register -// override is applied -#define IO_BANK0_GPIO4_STATUS_OUTFROMPERI_RESET _u(0x0) -#define IO_BANK0_GPIO4_STATUS_OUTFROMPERI_BITS _u(0x00000100) -#define IO_BANK0_GPIO4_STATUS_OUTFROMPERI_MSB _u(8) -#define IO_BANK0_GPIO4_STATUS_OUTFROMPERI_LSB _u(8) -#define IO_BANK0_GPIO4_STATUS_OUTFROMPERI_ACCESS "RO" -// ============================================================================= -// Register : IO_BANK0_GPIO4_CTRL -// Description : GPIO control including function select and overrides. -#define IO_BANK0_GPIO4_CTRL_OFFSET _u(0x00000024) -#define IO_BANK0_GPIO4_CTRL_BITS _u(0x3003331f) -#define IO_BANK0_GPIO4_CTRL_RESET _u(0x0000001f) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO4_CTRL_IRQOVER -// 0x0 -> don't invert the interrupt -// 0x1 -> invert the interrupt -// 0x2 -> drive interrupt low -// 0x3 -> drive interrupt high -#define IO_BANK0_GPIO4_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO4_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO4_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO4_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO4_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO4_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO4_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO4_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO4_CTRL_IRQOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO4_CTRL_INOVER -// 0x0 -> don't invert the peri input -// 0x1 -> invert the peri input -// 0x2 -> drive peri input low -// 0x3 -> drive peri input high -#define IO_BANK0_GPIO4_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO4_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO4_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO4_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO4_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO4_CTRL_INOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO4_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO4_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO4_CTRL_INOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO4_CTRL_OEOVER -// 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel -// 0x2 -> disable output -// 0x3 -> enable output -#define IO_BANK0_GPIO4_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO4_CTRL_OEOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO4_CTRL_OEOVER_MSB _u(13) -#define IO_BANK0_GPIO4_CTRL_OEOVER_LSB _u(12) -#define IO_BANK0_GPIO4_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO4_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO4_CTRL_OEOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO4_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO4_CTRL_OEOVER_VALUE_ENABLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO4_CTRL_OUTOVER -// 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel -// 0x2 -> drive output low -// 0x3 -> drive output high -#define IO_BANK0_GPIO4_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO4_CTRL_OUTOVER_BITS _u(0x00000300) -#define IO_BANK0_GPIO4_CTRL_OUTOVER_MSB _u(9) -#define IO_BANK0_GPIO4_CTRL_OUTOVER_LSB _u(8) -#define IO_BANK0_GPIO4_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO4_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO4_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO4_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO4_CTRL_OUTOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO4_CTRL_FUNCSEL -// Description : 0-31 -> selects pin function according to the gpio table -// 31 == NULL -// 0x01 -> spi0_rx -// 0x02 -> uart1_tx -// 0x03 -> i2c0_sda -// 0x04 -> pwm_a_2 -// 0x05 -> sio_4 -// 0x06 -> pio0_4 -// 0x07 -> pio1_4 -// 0x09 -> usb_muxing_vbus_detect -// 0x1f -> null -#define IO_BANK0_GPIO4_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO4_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO4_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO4_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO4_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_SPI0_RX _u(0x01) -#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_UART1_TX _u(0x02) -#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03) -#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_PWM_A_2 _u(0x04) -#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_SIO_4 _u(0x05) -#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_PIO0_4 _u(0x06) -#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_PIO1_4 _u(0x07) -#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x09) -#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) -// ============================================================================= -// Register : IO_BANK0_GPIO5_STATUS -// Description : GPIO status -#define IO_BANK0_GPIO5_STATUS_OFFSET _u(0x00000028) -#define IO_BANK0_GPIO5_STATUS_BITS _u(0x050a3300) -#define IO_BANK0_GPIO5_STATUS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO5_STATUS_IRQTOPROC -// Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO5_STATUS_IRQTOPROC_RESET _u(0x0) -#define IO_BANK0_GPIO5_STATUS_IRQTOPROC_BITS _u(0x04000000) -#define IO_BANK0_GPIO5_STATUS_IRQTOPROC_MSB _u(26) -#define IO_BANK0_GPIO5_STATUS_IRQTOPROC_LSB _u(26) -#define IO_BANK0_GPIO5_STATUS_IRQTOPROC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO5_STATUS_IRQFROMPAD -// Description : interrupt from pad before override is applied -#define IO_BANK0_GPIO5_STATUS_IRQFROMPAD_RESET _u(0x0) -#define IO_BANK0_GPIO5_STATUS_IRQFROMPAD_BITS _u(0x01000000) -#define IO_BANK0_GPIO5_STATUS_IRQFROMPAD_MSB _u(24) -#define IO_BANK0_GPIO5_STATUS_IRQFROMPAD_LSB _u(24) -#define IO_BANK0_GPIO5_STATUS_IRQFROMPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO5_STATUS_INTOPERI -// Description : input signal to peripheral, after override is applied -#define IO_BANK0_GPIO5_STATUS_INTOPERI_RESET _u(0x0) -#define IO_BANK0_GPIO5_STATUS_INTOPERI_BITS _u(0x00080000) -#define IO_BANK0_GPIO5_STATUS_INTOPERI_MSB _u(19) -#define IO_BANK0_GPIO5_STATUS_INTOPERI_LSB _u(19) -#define IO_BANK0_GPIO5_STATUS_INTOPERI_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO5_STATUS_INFROMPAD -// Description : input signal from pad, before override is applied -#define IO_BANK0_GPIO5_STATUS_INFROMPAD_RESET _u(0x0) -#define IO_BANK0_GPIO5_STATUS_INFROMPAD_BITS _u(0x00020000) -#define IO_BANK0_GPIO5_STATUS_INFROMPAD_MSB _u(17) -#define IO_BANK0_GPIO5_STATUS_INFROMPAD_LSB _u(17) -#define IO_BANK0_GPIO5_STATUS_INFROMPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO5_STATUS_OETOPAD -// Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO5_STATUS_OETOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO5_STATUS_OETOPAD_BITS _u(0x00002000) -#define IO_BANK0_GPIO5_STATUS_OETOPAD_MSB _u(13) -#define IO_BANK0_GPIO5_STATUS_OETOPAD_LSB _u(13) -#define IO_BANK0_GPIO5_STATUS_OETOPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO5_STATUS_OEFROMPERI -// Description : output enable from selected peripheral, before register -// override is applied -#define IO_BANK0_GPIO5_STATUS_OEFROMPERI_RESET _u(0x0) -#define IO_BANK0_GPIO5_STATUS_OEFROMPERI_BITS _u(0x00001000) -#define IO_BANK0_GPIO5_STATUS_OEFROMPERI_MSB _u(12) -#define IO_BANK0_GPIO5_STATUS_OEFROMPERI_LSB _u(12) -#define IO_BANK0_GPIO5_STATUS_OEFROMPERI_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO5_STATUS_OUTTOPAD -// Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO5_STATUS_OUTTOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO5_STATUS_OUTTOPAD_BITS _u(0x00000200) -#define IO_BANK0_GPIO5_STATUS_OUTTOPAD_MSB _u(9) -#define IO_BANK0_GPIO5_STATUS_OUTTOPAD_LSB _u(9) -#define IO_BANK0_GPIO5_STATUS_OUTTOPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO5_STATUS_OUTFROMPERI -// Description : output signal from selected peripheral, before register -// override is applied -#define IO_BANK0_GPIO5_STATUS_OUTFROMPERI_RESET _u(0x0) -#define IO_BANK0_GPIO5_STATUS_OUTFROMPERI_BITS _u(0x00000100) -#define IO_BANK0_GPIO5_STATUS_OUTFROMPERI_MSB _u(8) -#define IO_BANK0_GPIO5_STATUS_OUTFROMPERI_LSB _u(8) -#define IO_BANK0_GPIO5_STATUS_OUTFROMPERI_ACCESS "RO" -// ============================================================================= -// Register : IO_BANK0_GPIO5_CTRL -// Description : GPIO control including function select and overrides. -#define IO_BANK0_GPIO5_CTRL_OFFSET _u(0x0000002c) -#define IO_BANK0_GPIO5_CTRL_BITS _u(0x3003331f) -#define IO_BANK0_GPIO5_CTRL_RESET _u(0x0000001f) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO5_CTRL_IRQOVER -// 0x0 -> don't invert the interrupt -// 0x1 -> invert the interrupt -// 0x2 -> drive interrupt low -// 0x3 -> drive interrupt high -#define IO_BANK0_GPIO5_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO5_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO5_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO5_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO5_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO5_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO5_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO5_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO5_CTRL_IRQOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO5_CTRL_INOVER -// 0x0 -> don't invert the peri input -// 0x1 -> invert the peri input -// 0x2 -> drive peri input low -// 0x3 -> drive peri input high -#define IO_BANK0_GPIO5_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO5_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO5_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO5_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO5_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO5_CTRL_INOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO5_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO5_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO5_CTRL_INOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO5_CTRL_OEOVER -// 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel -// 0x2 -> disable output -// 0x3 -> enable output -#define IO_BANK0_GPIO5_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO5_CTRL_OEOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO5_CTRL_OEOVER_MSB _u(13) -#define IO_BANK0_GPIO5_CTRL_OEOVER_LSB _u(12) -#define IO_BANK0_GPIO5_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO5_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO5_CTRL_OEOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO5_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO5_CTRL_OEOVER_VALUE_ENABLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO5_CTRL_OUTOVER -// 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel -// 0x2 -> drive output low -// 0x3 -> drive output high -#define IO_BANK0_GPIO5_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO5_CTRL_OUTOVER_BITS _u(0x00000300) -#define IO_BANK0_GPIO5_CTRL_OUTOVER_MSB _u(9) -#define IO_BANK0_GPIO5_CTRL_OUTOVER_LSB _u(8) -#define IO_BANK0_GPIO5_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO5_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO5_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO5_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO5_CTRL_OUTOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO5_CTRL_FUNCSEL -// Description : 0-31 -> selects pin function according to the gpio table -// 31 == NULL -// 0x01 -> spi0_ss_n -// 0x02 -> uart1_rx -// 0x03 -> i2c0_scl -// 0x04 -> pwm_b_2 -// 0x05 -> sio_5 -// 0x06 -> pio0_5 -// 0x07 -> pio1_5 -// 0x09 -> usb_muxing_vbus_en -// 0x1f -> null -#define IO_BANK0_GPIO5_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO5_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO5_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO5_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO5_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_SPI0_SS_N _u(0x01) -#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_UART1_RX _u(0x02) -#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03) -#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_PWM_B_2 _u(0x04) -#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_SIO_5 _u(0x05) -#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_PIO0_5 _u(0x06) -#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_PIO1_5 _u(0x07) -#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x09) -#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) -// ============================================================================= -// Register : IO_BANK0_GPIO6_STATUS -// Description : GPIO status -#define IO_BANK0_GPIO6_STATUS_OFFSET _u(0x00000030) -#define IO_BANK0_GPIO6_STATUS_BITS _u(0x050a3300) -#define IO_BANK0_GPIO6_STATUS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO6_STATUS_IRQTOPROC -// Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO6_STATUS_IRQTOPROC_RESET _u(0x0) -#define IO_BANK0_GPIO6_STATUS_IRQTOPROC_BITS _u(0x04000000) -#define IO_BANK0_GPIO6_STATUS_IRQTOPROC_MSB _u(26) -#define IO_BANK0_GPIO6_STATUS_IRQTOPROC_LSB _u(26) -#define IO_BANK0_GPIO6_STATUS_IRQTOPROC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO6_STATUS_IRQFROMPAD -// Description : interrupt from pad before override is applied -#define IO_BANK0_GPIO6_STATUS_IRQFROMPAD_RESET _u(0x0) -#define IO_BANK0_GPIO6_STATUS_IRQFROMPAD_BITS _u(0x01000000) -#define IO_BANK0_GPIO6_STATUS_IRQFROMPAD_MSB _u(24) -#define IO_BANK0_GPIO6_STATUS_IRQFROMPAD_LSB _u(24) -#define IO_BANK0_GPIO6_STATUS_IRQFROMPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO6_STATUS_INTOPERI -// Description : input signal to peripheral, after override is applied -#define IO_BANK0_GPIO6_STATUS_INTOPERI_RESET _u(0x0) -#define IO_BANK0_GPIO6_STATUS_INTOPERI_BITS _u(0x00080000) -#define IO_BANK0_GPIO6_STATUS_INTOPERI_MSB _u(19) -#define IO_BANK0_GPIO6_STATUS_INTOPERI_LSB _u(19) -#define IO_BANK0_GPIO6_STATUS_INTOPERI_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO6_STATUS_INFROMPAD -// Description : input signal from pad, before override is applied -#define IO_BANK0_GPIO6_STATUS_INFROMPAD_RESET _u(0x0) -#define IO_BANK0_GPIO6_STATUS_INFROMPAD_BITS _u(0x00020000) -#define IO_BANK0_GPIO6_STATUS_INFROMPAD_MSB _u(17) -#define IO_BANK0_GPIO6_STATUS_INFROMPAD_LSB _u(17) -#define IO_BANK0_GPIO6_STATUS_INFROMPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO6_STATUS_OETOPAD -// Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO6_STATUS_OETOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO6_STATUS_OETOPAD_BITS _u(0x00002000) -#define IO_BANK0_GPIO6_STATUS_OETOPAD_MSB _u(13) -#define IO_BANK0_GPIO6_STATUS_OETOPAD_LSB _u(13) -#define IO_BANK0_GPIO6_STATUS_OETOPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO6_STATUS_OEFROMPERI -// Description : output enable from selected peripheral, before register -// override is applied -#define IO_BANK0_GPIO6_STATUS_OEFROMPERI_RESET _u(0x0) -#define IO_BANK0_GPIO6_STATUS_OEFROMPERI_BITS _u(0x00001000) -#define IO_BANK0_GPIO6_STATUS_OEFROMPERI_MSB _u(12) -#define IO_BANK0_GPIO6_STATUS_OEFROMPERI_LSB _u(12) -#define IO_BANK0_GPIO6_STATUS_OEFROMPERI_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO6_STATUS_OUTTOPAD -// Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO6_STATUS_OUTTOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO6_STATUS_OUTTOPAD_BITS _u(0x00000200) -#define IO_BANK0_GPIO6_STATUS_OUTTOPAD_MSB _u(9) -#define IO_BANK0_GPIO6_STATUS_OUTTOPAD_LSB _u(9) -#define IO_BANK0_GPIO6_STATUS_OUTTOPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO6_STATUS_OUTFROMPERI -// Description : output signal from selected peripheral, before register -// override is applied -#define IO_BANK0_GPIO6_STATUS_OUTFROMPERI_RESET _u(0x0) -#define IO_BANK0_GPIO6_STATUS_OUTFROMPERI_BITS _u(0x00000100) -#define IO_BANK0_GPIO6_STATUS_OUTFROMPERI_MSB _u(8) -#define IO_BANK0_GPIO6_STATUS_OUTFROMPERI_LSB _u(8) -#define IO_BANK0_GPIO6_STATUS_OUTFROMPERI_ACCESS "RO" -// ============================================================================= -// Register : IO_BANK0_GPIO6_CTRL -// Description : GPIO control including function select and overrides. -#define IO_BANK0_GPIO6_CTRL_OFFSET _u(0x00000034) -#define IO_BANK0_GPIO6_CTRL_BITS _u(0x3003331f) -#define IO_BANK0_GPIO6_CTRL_RESET _u(0x0000001f) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO6_CTRL_IRQOVER -// 0x0 -> don't invert the interrupt -// 0x1 -> invert the interrupt -// 0x2 -> drive interrupt low -// 0x3 -> drive interrupt high -#define IO_BANK0_GPIO6_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO6_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO6_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO6_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO6_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO6_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO6_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO6_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO6_CTRL_IRQOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO6_CTRL_INOVER -// 0x0 -> don't invert the peri input -// 0x1 -> invert the peri input -// 0x2 -> drive peri input low -// 0x3 -> drive peri input high -#define IO_BANK0_GPIO6_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO6_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO6_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO6_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO6_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO6_CTRL_INOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO6_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO6_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO6_CTRL_INOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO6_CTRL_OEOVER -// 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel -// 0x2 -> disable output -// 0x3 -> enable output -#define IO_BANK0_GPIO6_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO6_CTRL_OEOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO6_CTRL_OEOVER_MSB _u(13) -#define IO_BANK0_GPIO6_CTRL_OEOVER_LSB _u(12) -#define IO_BANK0_GPIO6_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO6_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO6_CTRL_OEOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO6_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO6_CTRL_OEOVER_VALUE_ENABLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO6_CTRL_OUTOVER -// 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel -// 0x2 -> drive output low -// 0x3 -> drive output high -#define IO_BANK0_GPIO6_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO6_CTRL_OUTOVER_BITS _u(0x00000300) -#define IO_BANK0_GPIO6_CTRL_OUTOVER_MSB _u(9) -#define IO_BANK0_GPIO6_CTRL_OUTOVER_LSB _u(8) -#define IO_BANK0_GPIO6_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO6_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO6_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO6_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO6_CTRL_OUTOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO6_CTRL_FUNCSEL -// Description : 0-31 -> selects pin function according to the gpio table -// 31 == NULL -// 0x01 -> spi0_sclk -// 0x02 -> uart1_cts -// 0x03 -> i2c1_sda -// 0x04 -> pwm_a_3 -// 0x05 -> sio_6 -// 0x06 -> pio0_6 -// 0x07 -> pio1_6 -// 0x08 -> usb_muxing_extphy_softcon -// 0x09 -> usb_muxing_overcurr_detect -// 0x1f -> null -#define IO_BANK0_GPIO6_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO6_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO6_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO6_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO6_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_SPI0_SCLK _u(0x01) -#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_UART1_CTS _u(0x02) -#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03) -#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_PWM_A_3 _u(0x04) -#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_SIO_6 _u(0x05) -#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_PIO0_6 _u(0x06) -#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_PIO1_6 _u(0x07) -#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_SOFTCON _u(0x08) -#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x09) -#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) -// ============================================================================= -// Register : IO_BANK0_GPIO7_STATUS -// Description : GPIO status -#define IO_BANK0_GPIO7_STATUS_OFFSET _u(0x00000038) -#define IO_BANK0_GPIO7_STATUS_BITS _u(0x050a3300) -#define IO_BANK0_GPIO7_STATUS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO7_STATUS_IRQTOPROC -// Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO7_STATUS_IRQTOPROC_RESET _u(0x0) -#define IO_BANK0_GPIO7_STATUS_IRQTOPROC_BITS _u(0x04000000) -#define IO_BANK0_GPIO7_STATUS_IRQTOPROC_MSB _u(26) -#define IO_BANK0_GPIO7_STATUS_IRQTOPROC_LSB _u(26) -#define IO_BANK0_GPIO7_STATUS_IRQTOPROC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO7_STATUS_IRQFROMPAD -// Description : interrupt from pad before override is applied -#define IO_BANK0_GPIO7_STATUS_IRQFROMPAD_RESET _u(0x0) -#define IO_BANK0_GPIO7_STATUS_IRQFROMPAD_BITS _u(0x01000000) -#define IO_BANK0_GPIO7_STATUS_IRQFROMPAD_MSB _u(24) -#define IO_BANK0_GPIO7_STATUS_IRQFROMPAD_LSB _u(24) -#define IO_BANK0_GPIO7_STATUS_IRQFROMPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO7_STATUS_INTOPERI -// Description : input signal to peripheral, after override is applied -#define IO_BANK0_GPIO7_STATUS_INTOPERI_RESET _u(0x0) -#define IO_BANK0_GPIO7_STATUS_INTOPERI_BITS _u(0x00080000) -#define IO_BANK0_GPIO7_STATUS_INTOPERI_MSB _u(19) -#define IO_BANK0_GPIO7_STATUS_INTOPERI_LSB _u(19) -#define IO_BANK0_GPIO7_STATUS_INTOPERI_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO7_STATUS_INFROMPAD -// Description : input signal from pad, before override is applied -#define IO_BANK0_GPIO7_STATUS_INFROMPAD_RESET _u(0x0) -#define IO_BANK0_GPIO7_STATUS_INFROMPAD_BITS _u(0x00020000) -#define IO_BANK0_GPIO7_STATUS_INFROMPAD_MSB _u(17) -#define IO_BANK0_GPIO7_STATUS_INFROMPAD_LSB _u(17) -#define IO_BANK0_GPIO7_STATUS_INFROMPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO7_STATUS_OETOPAD -// Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO7_STATUS_OETOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO7_STATUS_OETOPAD_BITS _u(0x00002000) -#define IO_BANK0_GPIO7_STATUS_OETOPAD_MSB _u(13) -#define IO_BANK0_GPIO7_STATUS_OETOPAD_LSB _u(13) -#define IO_BANK0_GPIO7_STATUS_OETOPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO7_STATUS_OEFROMPERI -// Description : output enable from selected peripheral, before register -// override is applied -#define IO_BANK0_GPIO7_STATUS_OEFROMPERI_RESET _u(0x0) -#define IO_BANK0_GPIO7_STATUS_OEFROMPERI_BITS _u(0x00001000) -#define IO_BANK0_GPIO7_STATUS_OEFROMPERI_MSB _u(12) -#define IO_BANK0_GPIO7_STATUS_OEFROMPERI_LSB _u(12) -#define IO_BANK0_GPIO7_STATUS_OEFROMPERI_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO7_STATUS_OUTTOPAD -// Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO7_STATUS_OUTTOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO7_STATUS_OUTTOPAD_BITS _u(0x00000200) -#define IO_BANK0_GPIO7_STATUS_OUTTOPAD_MSB _u(9) -#define IO_BANK0_GPIO7_STATUS_OUTTOPAD_LSB _u(9) -#define IO_BANK0_GPIO7_STATUS_OUTTOPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO7_STATUS_OUTFROMPERI -// Description : output signal from selected peripheral, before register -// override is applied -#define IO_BANK0_GPIO7_STATUS_OUTFROMPERI_RESET _u(0x0) -#define IO_BANK0_GPIO7_STATUS_OUTFROMPERI_BITS _u(0x00000100) -#define IO_BANK0_GPIO7_STATUS_OUTFROMPERI_MSB _u(8) -#define IO_BANK0_GPIO7_STATUS_OUTFROMPERI_LSB _u(8) -#define IO_BANK0_GPIO7_STATUS_OUTFROMPERI_ACCESS "RO" -// ============================================================================= -// Register : IO_BANK0_GPIO7_CTRL -// Description : GPIO control including function select and overrides. -#define IO_BANK0_GPIO7_CTRL_OFFSET _u(0x0000003c) -#define IO_BANK0_GPIO7_CTRL_BITS _u(0x3003331f) -#define IO_BANK0_GPIO7_CTRL_RESET _u(0x0000001f) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO7_CTRL_IRQOVER -// 0x0 -> don't invert the interrupt -// 0x1 -> invert the interrupt -// 0x2 -> drive interrupt low -// 0x3 -> drive interrupt high -#define IO_BANK0_GPIO7_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO7_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO7_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO7_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO7_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO7_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO7_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO7_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO7_CTRL_IRQOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO7_CTRL_INOVER -// 0x0 -> don't invert the peri input -// 0x1 -> invert the peri input -// 0x2 -> drive peri input low -// 0x3 -> drive peri input high -#define IO_BANK0_GPIO7_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO7_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO7_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO7_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO7_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO7_CTRL_INOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO7_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO7_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO7_CTRL_INOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO7_CTRL_OEOVER -// 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel -// 0x2 -> disable output -// 0x3 -> enable output -#define IO_BANK0_GPIO7_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO7_CTRL_OEOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO7_CTRL_OEOVER_MSB _u(13) -#define IO_BANK0_GPIO7_CTRL_OEOVER_LSB _u(12) -#define IO_BANK0_GPIO7_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO7_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO7_CTRL_OEOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO7_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO7_CTRL_OEOVER_VALUE_ENABLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO7_CTRL_OUTOVER -// 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel -// 0x2 -> drive output low -// 0x3 -> drive output high -#define IO_BANK0_GPIO7_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO7_CTRL_OUTOVER_BITS _u(0x00000300) -#define IO_BANK0_GPIO7_CTRL_OUTOVER_MSB _u(9) -#define IO_BANK0_GPIO7_CTRL_OUTOVER_LSB _u(8) -#define IO_BANK0_GPIO7_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO7_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO7_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO7_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO7_CTRL_OUTOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO7_CTRL_FUNCSEL -// Description : 0-31 -> selects pin function according to the gpio table -// 31 == NULL -// 0x01 -> spi0_tx -// 0x02 -> uart1_rts -// 0x03 -> i2c1_scl -// 0x04 -> pwm_b_3 -// 0x05 -> sio_7 -// 0x06 -> pio0_7 -// 0x07 -> pio1_7 -// 0x08 -> usb_muxing_extphy_oe_n -// 0x09 -> usb_muxing_vbus_detect -// 0x1f -> null -#define IO_BANK0_GPIO7_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO7_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO7_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO7_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO7_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_SPI0_TX _u(0x01) -#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_UART1_RTS _u(0x02) -#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03) -#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_PWM_B_3 _u(0x04) -#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_SIO_7 _u(0x05) -#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_PIO0_7 _u(0x06) -#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_PIO1_7 _u(0x07) -#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_OE_N _u(0x08) -#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x09) -#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) -// ============================================================================= -// Register : IO_BANK0_GPIO8_STATUS -// Description : GPIO status -#define IO_BANK0_GPIO8_STATUS_OFFSET _u(0x00000040) -#define IO_BANK0_GPIO8_STATUS_BITS _u(0x050a3300) -#define IO_BANK0_GPIO8_STATUS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO8_STATUS_IRQTOPROC -// Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO8_STATUS_IRQTOPROC_RESET _u(0x0) -#define IO_BANK0_GPIO8_STATUS_IRQTOPROC_BITS _u(0x04000000) -#define IO_BANK0_GPIO8_STATUS_IRQTOPROC_MSB _u(26) -#define IO_BANK0_GPIO8_STATUS_IRQTOPROC_LSB _u(26) -#define IO_BANK0_GPIO8_STATUS_IRQTOPROC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO8_STATUS_IRQFROMPAD -// Description : interrupt from pad before override is applied -#define IO_BANK0_GPIO8_STATUS_IRQFROMPAD_RESET _u(0x0) -#define IO_BANK0_GPIO8_STATUS_IRQFROMPAD_BITS _u(0x01000000) -#define IO_BANK0_GPIO8_STATUS_IRQFROMPAD_MSB _u(24) -#define IO_BANK0_GPIO8_STATUS_IRQFROMPAD_LSB _u(24) -#define IO_BANK0_GPIO8_STATUS_IRQFROMPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO8_STATUS_INTOPERI -// Description : input signal to peripheral, after override is applied -#define IO_BANK0_GPIO8_STATUS_INTOPERI_RESET _u(0x0) -#define IO_BANK0_GPIO8_STATUS_INTOPERI_BITS _u(0x00080000) -#define IO_BANK0_GPIO8_STATUS_INTOPERI_MSB _u(19) -#define IO_BANK0_GPIO8_STATUS_INTOPERI_LSB _u(19) -#define IO_BANK0_GPIO8_STATUS_INTOPERI_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO8_STATUS_INFROMPAD -// Description : input signal from pad, before override is applied -#define IO_BANK0_GPIO8_STATUS_INFROMPAD_RESET _u(0x0) -#define IO_BANK0_GPIO8_STATUS_INFROMPAD_BITS _u(0x00020000) -#define IO_BANK0_GPIO8_STATUS_INFROMPAD_MSB _u(17) -#define IO_BANK0_GPIO8_STATUS_INFROMPAD_LSB _u(17) -#define IO_BANK0_GPIO8_STATUS_INFROMPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO8_STATUS_OETOPAD -// Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO8_STATUS_OETOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO8_STATUS_OETOPAD_BITS _u(0x00002000) -#define IO_BANK0_GPIO8_STATUS_OETOPAD_MSB _u(13) -#define IO_BANK0_GPIO8_STATUS_OETOPAD_LSB _u(13) -#define IO_BANK0_GPIO8_STATUS_OETOPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO8_STATUS_OEFROMPERI -// Description : output enable from selected peripheral, before register -// override is applied -#define IO_BANK0_GPIO8_STATUS_OEFROMPERI_RESET _u(0x0) -#define IO_BANK0_GPIO8_STATUS_OEFROMPERI_BITS _u(0x00001000) -#define IO_BANK0_GPIO8_STATUS_OEFROMPERI_MSB _u(12) -#define IO_BANK0_GPIO8_STATUS_OEFROMPERI_LSB _u(12) -#define IO_BANK0_GPIO8_STATUS_OEFROMPERI_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO8_STATUS_OUTTOPAD -// Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO8_STATUS_OUTTOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO8_STATUS_OUTTOPAD_BITS _u(0x00000200) -#define IO_BANK0_GPIO8_STATUS_OUTTOPAD_MSB _u(9) -#define IO_BANK0_GPIO8_STATUS_OUTTOPAD_LSB _u(9) -#define IO_BANK0_GPIO8_STATUS_OUTTOPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO8_STATUS_OUTFROMPERI -// Description : output signal from selected peripheral, before register -// override is applied -#define IO_BANK0_GPIO8_STATUS_OUTFROMPERI_RESET _u(0x0) -#define IO_BANK0_GPIO8_STATUS_OUTFROMPERI_BITS _u(0x00000100) -#define IO_BANK0_GPIO8_STATUS_OUTFROMPERI_MSB _u(8) -#define IO_BANK0_GPIO8_STATUS_OUTFROMPERI_LSB _u(8) -#define IO_BANK0_GPIO8_STATUS_OUTFROMPERI_ACCESS "RO" -// ============================================================================= -// Register : IO_BANK0_GPIO8_CTRL -// Description : GPIO control including function select and overrides. -#define IO_BANK0_GPIO8_CTRL_OFFSET _u(0x00000044) -#define IO_BANK0_GPIO8_CTRL_BITS _u(0x3003331f) -#define IO_BANK0_GPIO8_CTRL_RESET _u(0x0000001f) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO8_CTRL_IRQOVER -// 0x0 -> don't invert the interrupt -// 0x1 -> invert the interrupt -// 0x2 -> drive interrupt low -// 0x3 -> drive interrupt high -#define IO_BANK0_GPIO8_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO8_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO8_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO8_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO8_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO8_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO8_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO8_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO8_CTRL_IRQOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO8_CTRL_INOVER -// 0x0 -> don't invert the peri input -// 0x1 -> invert the peri input -// 0x2 -> drive peri input low -// 0x3 -> drive peri input high -#define IO_BANK0_GPIO8_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO8_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO8_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO8_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO8_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO8_CTRL_INOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO8_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO8_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO8_CTRL_INOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO8_CTRL_OEOVER -// 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel -// 0x2 -> disable output -// 0x3 -> enable output -#define IO_BANK0_GPIO8_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO8_CTRL_OEOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO8_CTRL_OEOVER_MSB _u(13) -#define IO_BANK0_GPIO8_CTRL_OEOVER_LSB _u(12) -#define IO_BANK0_GPIO8_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO8_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO8_CTRL_OEOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO8_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO8_CTRL_OEOVER_VALUE_ENABLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO8_CTRL_OUTOVER -// 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel -// 0x2 -> drive output low -// 0x3 -> drive output high -#define IO_BANK0_GPIO8_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO8_CTRL_OUTOVER_BITS _u(0x00000300) -#define IO_BANK0_GPIO8_CTRL_OUTOVER_MSB _u(9) -#define IO_BANK0_GPIO8_CTRL_OUTOVER_LSB _u(8) -#define IO_BANK0_GPIO8_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO8_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO8_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO8_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO8_CTRL_OUTOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO8_CTRL_FUNCSEL -// Description : 0-31 -> selects pin function according to the gpio table -// 31 == NULL -// 0x01 -> spi1_rx -// 0x02 -> uart1_tx -// 0x03 -> i2c0_sda -// 0x04 -> pwm_a_4 -// 0x05 -> sio_8 -// 0x06 -> pio0_8 -// 0x07 -> pio1_8 -// 0x08 -> usb_muxing_extphy_rcv -// 0x09 -> usb_muxing_vbus_en -// 0x1f -> null -#define IO_BANK0_GPIO8_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO8_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO8_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO8_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO8_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_SPI1_RX _u(0x01) -#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_UART1_TX _u(0x02) -#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03) -#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_PWM_A_4 _u(0x04) -#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_SIO_8 _u(0x05) -#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_PIO0_8 _u(0x06) -#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_PIO1_8 _u(0x07) -#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_RCV _u(0x08) -#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x09) -#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) -// ============================================================================= -// Register : IO_BANK0_GPIO9_STATUS -// Description : GPIO status -#define IO_BANK0_GPIO9_STATUS_OFFSET _u(0x00000048) -#define IO_BANK0_GPIO9_STATUS_BITS _u(0x050a3300) -#define IO_BANK0_GPIO9_STATUS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO9_STATUS_IRQTOPROC -// Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO9_STATUS_IRQTOPROC_RESET _u(0x0) -#define IO_BANK0_GPIO9_STATUS_IRQTOPROC_BITS _u(0x04000000) -#define IO_BANK0_GPIO9_STATUS_IRQTOPROC_MSB _u(26) -#define IO_BANK0_GPIO9_STATUS_IRQTOPROC_LSB _u(26) -#define IO_BANK0_GPIO9_STATUS_IRQTOPROC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO9_STATUS_IRQFROMPAD -// Description : interrupt from pad before override is applied -#define IO_BANK0_GPIO9_STATUS_IRQFROMPAD_RESET _u(0x0) -#define IO_BANK0_GPIO9_STATUS_IRQFROMPAD_BITS _u(0x01000000) -#define IO_BANK0_GPIO9_STATUS_IRQFROMPAD_MSB _u(24) -#define IO_BANK0_GPIO9_STATUS_IRQFROMPAD_LSB _u(24) -#define IO_BANK0_GPIO9_STATUS_IRQFROMPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO9_STATUS_INTOPERI -// Description : input signal to peripheral, after override is applied -#define IO_BANK0_GPIO9_STATUS_INTOPERI_RESET _u(0x0) -#define IO_BANK0_GPIO9_STATUS_INTOPERI_BITS _u(0x00080000) -#define IO_BANK0_GPIO9_STATUS_INTOPERI_MSB _u(19) -#define IO_BANK0_GPIO9_STATUS_INTOPERI_LSB _u(19) -#define IO_BANK0_GPIO9_STATUS_INTOPERI_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO9_STATUS_INFROMPAD -// Description : input signal from pad, before override is applied -#define IO_BANK0_GPIO9_STATUS_INFROMPAD_RESET _u(0x0) -#define IO_BANK0_GPIO9_STATUS_INFROMPAD_BITS _u(0x00020000) -#define IO_BANK0_GPIO9_STATUS_INFROMPAD_MSB _u(17) -#define IO_BANK0_GPIO9_STATUS_INFROMPAD_LSB _u(17) -#define IO_BANK0_GPIO9_STATUS_INFROMPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO9_STATUS_OETOPAD -// Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO9_STATUS_OETOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO9_STATUS_OETOPAD_BITS _u(0x00002000) -#define IO_BANK0_GPIO9_STATUS_OETOPAD_MSB _u(13) -#define IO_BANK0_GPIO9_STATUS_OETOPAD_LSB _u(13) -#define IO_BANK0_GPIO9_STATUS_OETOPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO9_STATUS_OEFROMPERI -// Description : output enable from selected peripheral, before register -// override is applied -#define IO_BANK0_GPIO9_STATUS_OEFROMPERI_RESET _u(0x0) -#define IO_BANK0_GPIO9_STATUS_OEFROMPERI_BITS _u(0x00001000) -#define IO_BANK0_GPIO9_STATUS_OEFROMPERI_MSB _u(12) -#define IO_BANK0_GPIO9_STATUS_OEFROMPERI_LSB _u(12) -#define IO_BANK0_GPIO9_STATUS_OEFROMPERI_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO9_STATUS_OUTTOPAD -// Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO9_STATUS_OUTTOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO9_STATUS_OUTTOPAD_BITS _u(0x00000200) -#define IO_BANK0_GPIO9_STATUS_OUTTOPAD_MSB _u(9) -#define IO_BANK0_GPIO9_STATUS_OUTTOPAD_LSB _u(9) -#define IO_BANK0_GPIO9_STATUS_OUTTOPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO9_STATUS_OUTFROMPERI -// Description : output signal from selected peripheral, before register -// override is applied -#define IO_BANK0_GPIO9_STATUS_OUTFROMPERI_RESET _u(0x0) -#define IO_BANK0_GPIO9_STATUS_OUTFROMPERI_BITS _u(0x00000100) -#define IO_BANK0_GPIO9_STATUS_OUTFROMPERI_MSB _u(8) -#define IO_BANK0_GPIO9_STATUS_OUTFROMPERI_LSB _u(8) -#define IO_BANK0_GPIO9_STATUS_OUTFROMPERI_ACCESS "RO" -// ============================================================================= -// Register : IO_BANK0_GPIO9_CTRL -// Description : GPIO control including function select and overrides. -#define IO_BANK0_GPIO9_CTRL_OFFSET _u(0x0000004c) -#define IO_BANK0_GPIO9_CTRL_BITS _u(0x3003331f) -#define IO_BANK0_GPIO9_CTRL_RESET _u(0x0000001f) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO9_CTRL_IRQOVER -// 0x0 -> don't invert the interrupt -// 0x1 -> invert the interrupt -// 0x2 -> drive interrupt low -// 0x3 -> drive interrupt high -#define IO_BANK0_GPIO9_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO9_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO9_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO9_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO9_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO9_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO9_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO9_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO9_CTRL_IRQOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO9_CTRL_INOVER -// 0x0 -> don't invert the peri input -// 0x1 -> invert the peri input -// 0x2 -> drive peri input low -// 0x3 -> drive peri input high -#define IO_BANK0_GPIO9_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO9_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO9_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO9_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO9_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO9_CTRL_INOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO9_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO9_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO9_CTRL_INOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO9_CTRL_OEOVER -// 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel -// 0x2 -> disable output -// 0x3 -> enable output -#define IO_BANK0_GPIO9_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO9_CTRL_OEOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO9_CTRL_OEOVER_MSB _u(13) -#define IO_BANK0_GPIO9_CTRL_OEOVER_LSB _u(12) -#define IO_BANK0_GPIO9_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO9_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO9_CTRL_OEOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO9_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO9_CTRL_OEOVER_VALUE_ENABLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO9_CTRL_OUTOVER -// 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel -// 0x2 -> drive output low -// 0x3 -> drive output high -#define IO_BANK0_GPIO9_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO9_CTRL_OUTOVER_BITS _u(0x00000300) -#define IO_BANK0_GPIO9_CTRL_OUTOVER_MSB _u(9) -#define IO_BANK0_GPIO9_CTRL_OUTOVER_LSB _u(8) -#define IO_BANK0_GPIO9_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO9_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO9_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO9_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO9_CTRL_OUTOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO9_CTRL_FUNCSEL -// Description : 0-31 -> selects pin function according to the gpio table -// 31 == NULL -// 0x01 -> spi1_ss_n -// 0x02 -> uart1_rx -// 0x03 -> i2c0_scl -// 0x04 -> pwm_b_4 -// 0x05 -> sio_9 -// 0x06 -> pio0_9 -// 0x07 -> pio1_9 -// 0x08 -> usb_muxing_extphy_vp -// 0x09 -> usb_muxing_overcurr_detect -// 0x1f -> null -#define IO_BANK0_GPIO9_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO9_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO9_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO9_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO9_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_SPI1_SS_N _u(0x01) -#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_UART1_RX _u(0x02) -#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03) -#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_PWM_B_4 _u(0x04) -#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_SIO_9 _u(0x05) -#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_PIO0_9 _u(0x06) -#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_PIO1_9 _u(0x07) -#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_VP _u(0x08) -#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x09) -#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) -// ============================================================================= -// Register : IO_BANK0_GPIO10_STATUS -// Description : GPIO status -#define IO_BANK0_GPIO10_STATUS_OFFSET _u(0x00000050) -#define IO_BANK0_GPIO10_STATUS_BITS _u(0x050a3300) -#define IO_BANK0_GPIO10_STATUS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO10_STATUS_IRQTOPROC -// Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO10_STATUS_IRQTOPROC_RESET _u(0x0) -#define IO_BANK0_GPIO10_STATUS_IRQTOPROC_BITS _u(0x04000000) -#define IO_BANK0_GPIO10_STATUS_IRQTOPROC_MSB _u(26) -#define IO_BANK0_GPIO10_STATUS_IRQTOPROC_LSB _u(26) -#define IO_BANK0_GPIO10_STATUS_IRQTOPROC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO10_STATUS_IRQFROMPAD -// Description : interrupt from pad before override is applied -#define IO_BANK0_GPIO10_STATUS_IRQFROMPAD_RESET _u(0x0) -#define IO_BANK0_GPIO10_STATUS_IRQFROMPAD_BITS _u(0x01000000) -#define IO_BANK0_GPIO10_STATUS_IRQFROMPAD_MSB _u(24) -#define IO_BANK0_GPIO10_STATUS_IRQFROMPAD_LSB _u(24) -#define IO_BANK0_GPIO10_STATUS_IRQFROMPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO10_STATUS_INTOPERI -// Description : input signal to peripheral, after override is applied -#define IO_BANK0_GPIO10_STATUS_INTOPERI_RESET _u(0x0) -#define IO_BANK0_GPIO10_STATUS_INTOPERI_BITS _u(0x00080000) -#define IO_BANK0_GPIO10_STATUS_INTOPERI_MSB _u(19) -#define IO_BANK0_GPIO10_STATUS_INTOPERI_LSB _u(19) -#define IO_BANK0_GPIO10_STATUS_INTOPERI_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO10_STATUS_INFROMPAD -// Description : input signal from pad, before override is applied -#define IO_BANK0_GPIO10_STATUS_INFROMPAD_RESET _u(0x0) -#define IO_BANK0_GPIO10_STATUS_INFROMPAD_BITS _u(0x00020000) -#define IO_BANK0_GPIO10_STATUS_INFROMPAD_MSB _u(17) -#define IO_BANK0_GPIO10_STATUS_INFROMPAD_LSB _u(17) -#define IO_BANK0_GPIO10_STATUS_INFROMPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO10_STATUS_OETOPAD -// Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO10_STATUS_OETOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO10_STATUS_OETOPAD_BITS _u(0x00002000) -#define IO_BANK0_GPIO10_STATUS_OETOPAD_MSB _u(13) -#define IO_BANK0_GPIO10_STATUS_OETOPAD_LSB _u(13) -#define IO_BANK0_GPIO10_STATUS_OETOPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO10_STATUS_OEFROMPERI -// Description : output enable from selected peripheral, before register -// override is applied -#define IO_BANK0_GPIO10_STATUS_OEFROMPERI_RESET _u(0x0) -#define IO_BANK0_GPIO10_STATUS_OEFROMPERI_BITS _u(0x00001000) -#define IO_BANK0_GPIO10_STATUS_OEFROMPERI_MSB _u(12) -#define IO_BANK0_GPIO10_STATUS_OEFROMPERI_LSB _u(12) -#define IO_BANK0_GPIO10_STATUS_OEFROMPERI_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO10_STATUS_OUTTOPAD -// Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO10_STATUS_OUTTOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO10_STATUS_OUTTOPAD_BITS _u(0x00000200) -#define IO_BANK0_GPIO10_STATUS_OUTTOPAD_MSB _u(9) -#define IO_BANK0_GPIO10_STATUS_OUTTOPAD_LSB _u(9) -#define IO_BANK0_GPIO10_STATUS_OUTTOPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO10_STATUS_OUTFROMPERI -// Description : output signal from selected peripheral, before register -// override is applied -#define IO_BANK0_GPIO10_STATUS_OUTFROMPERI_RESET _u(0x0) -#define IO_BANK0_GPIO10_STATUS_OUTFROMPERI_BITS _u(0x00000100) -#define IO_BANK0_GPIO10_STATUS_OUTFROMPERI_MSB _u(8) -#define IO_BANK0_GPIO10_STATUS_OUTFROMPERI_LSB _u(8) -#define IO_BANK0_GPIO10_STATUS_OUTFROMPERI_ACCESS "RO" -// ============================================================================= -// Register : IO_BANK0_GPIO10_CTRL -// Description : GPIO control including function select and overrides. -#define IO_BANK0_GPIO10_CTRL_OFFSET _u(0x00000054) -#define IO_BANK0_GPIO10_CTRL_BITS _u(0x3003331f) -#define IO_BANK0_GPIO10_CTRL_RESET _u(0x0000001f) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO10_CTRL_IRQOVER -// 0x0 -> don't invert the interrupt -// 0x1 -> invert the interrupt -// 0x2 -> drive interrupt low -// 0x3 -> drive interrupt high -#define IO_BANK0_GPIO10_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO10_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO10_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO10_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO10_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO10_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO10_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO10_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO10_CTRL_IRQOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO10_CTRL_INOVER -// 0x0 -> don't invert the peri input -// 0x1 -> invert the peri input -// 0x2 -> drive peri input low -// 0x3 -> drive peri input high -#define IO_BANK0_GPIO10_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO10_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO10_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO10_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO10_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO10_CTRL_INOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO10_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO10_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO10_CTRL_INOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO10_CTRL_OEOVER -// 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel -// 0x2 -> disable output -// 0x3 -> enable output -#define IO_BANK0_GPIO10_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO10_CTRL_OEOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO10_CTRL_OEOVER_MSB _u(13) -#define IO_BANK0_GPIO10_CTRL_OEOVER_LSB _u(12) -#define IO_BANK0_GPIO10_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO10_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO10_CTRL_OEOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO10_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO10_CTRL_OEOVER_VALUE_ENABLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO10_CTRL_OUTOVER -// 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel -// 0x2 -> drive output low -// 0x3 -> drive output high -#define IO_BANK0_GPIO10_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO10_CTRL_OUTOVER_BITS _u(0x00000300) -#define IO_BANK0_GPIO10_CTRL_OUTOVER_MSB _u(9) -#define IO_BANK0_GPIO10_CTRL_OUTOVER_LSB _u(8) -#define IO_BANK0_GPIO10_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO10_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO10_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO10_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO10_CTRL_OUTOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO10_CTRL_FUNCSEL -// Description : 0-31 -> selects pin function according to the gpio table -// 31 == NULL -// 0x01 -> spi1_sclk -// 0x02 -> uart1_cts -// 0x03 -> i2c1_sda -// 0x04 -> pwm_a_5 -// 0x05 -> sio_10 -// 0x06 -> pio0_10 -// 0x07 -> pio1_10 -// 0x08 -> usb_muxing_extphy_vm -// 0x09 -> usb_muxing_vbus_detect -// 0x1f -> null -#define IO_BANK0_GPIO10_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO10_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO10_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO10_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO10_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_SPI1_SCLK _u(0x01) -#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_UART1_CTS _u(0x02) -#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03) -#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_PWM_A_5 _u(0x04) -#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_SIO_10 _u(0x05) -#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_PIO0_10 _u(0x06) -#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_PIO1_10 _u(0x07) -#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_VM _u(0x08) -#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x09) -#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) -// ============================================================================= -// Register : IO_BANK0_GPIO11_STATUS -// Description : GPIO status -#define IO_BANK0_GPIO11_STATUS_OFFSET _u(0x00000058) -#define IO_BANK0_GPIO11_STATUS_BITS _u(0x050a3300) -#define IO_BANK0_GPIO11_STATUS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO11_STATUS_IRQTOPROC -// Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO11_STATUS_IRQTOPROC_RESET _u(0x0) -#define IO_BANK0_GPIO11_STATUS_IRQTOPROC_BITS _u(0x04000000) -#define IO_BANK0_GPIO11_STATUS_IRQTOPROC_MSB _u(26) -#define IO_BANK0_GPIO11_STATUS_IRQTOPROC_LSB _u(26) -#define IO_BANK0_GPIO11_STATUS_IRQTOPROC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO11_STATUS_IRQFROMPAD -// Description : interrupt from pad before override is applied -#define IO_BANK0_GPIO11_STATUS_IRQFROMPAD_RESET _u(0x0) -#define IO_BANK0_GPIO11_STATUS_IRQFROMPAD_BITS _u(0x01000000) -#define IO_BANK0_GPIO11_STATUS_IRQFROMPAD_MSB _u(24) -#define IO_BANK0_GPIO11_STATUS_IRQFROMPAD_LSB _u(24) -#define IO_BANK0_GPIO11_STATUS_IRQFROMPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO11_STATUS_INTOPERI -// Description : input signal to peripheral, after override is applied -#define IO_BANK0_GPIO11_STATUS_INTOPERI_RESET _u(0x0) -#define IO_BANK0_GPIO11_STATUS_INTOPERI_BITS _u(0x00080000) -#define IO_BANK0_GPIO11_STATUS_INTOPERI_MSB _u(19) -#define IO_BANK0_GPIO11_STATUS_INTOPERI_LSB _u(19) -#define IO_BANK0_GPIO11_STATUS_INTOPERI_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO11_STATUS_INFROMPAD -// Description : input signal from pad, before override is applied -#define IO_BANK0_GPIO11_STATUS_INFROMPAD_RESET _u(0x0) -#define IO_BANK0_GPIO11_STATUS_INFROMPAD_BITS _u(0x00020000) -#define IO_BANK0_GPIO11_STATUS_INFROMPAD_MSB _u(17) -#define IO_BANK0_GPIO11_STATUS_INFROMPAD_LSB _u(17) -#define IO_BANK0_GPIO11_STATUS_INFROMPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO11_STATUS_OETOPAD -// Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO11_STATUS_OETOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO11_STATUS_OETOPAD_BITS _u(0x00002000) -#define IO_BANK0_GPIO11_STATUS_OETOPAD_MSB _u(13) -#define IO_BANK0_GPIO11_STATUS_OETOPAD_LSB _u(13) -#define IO_BANK0_GPIO11_STATUS_OETOPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO11_STATUS_OEFROMPERI -// Description : output enable from selected peripheral, before register -// override is applied -#define IO_BANK0_GPIO11_STATUS_OEFROMPERI_RESET _u(0x0) -#define IO_BANK0_GPIO11_STATUS_OEFROMPERI_BITS _u(0x00001000) -#define IO_BANK0_GPIO11_STATUS_OEFROMPERI_MSB _u(12) -#define IO_BANK0_GPIO11_STATUS_OEFROMPERI_LSB _u(12) -#define IO_BANK0_GPIO11_STATUS_OEFROMPERI_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO11_STATUS_OUTTOPAD -// Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO11_STATUS_OUTTOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO11_STATUS_OUTTOPAD_BITS _u(0x00000200) -#define IO_BANK0_GPIO11_STATUS_OUTTOPAD_MSB _u(9) -#define IO_BANK0_GPIO11_STATUS_OUTTOPAD_LSB _u(9) -#define IO_BANK0_GPIO11_STATUS_OUTTOPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO11_STATUS_OUTFROMPERI -// Description : output signal from selected peripheral, before register -// override is applied -#define IO_BANK0_GPIO11_STATUS_OUTFROMPERI_RESET _u(0x0) -#define IO_BANK0_GPIO11_STATUS_OUTFROMPERI_BITS _u(0x00000100) -#define IO_BANK0_GPIO11_STATUS_OUTFROMPERI_MSB _u(8) -#define IO_BANK0_GPIO11_STATUS_OUTFROMPERI_LSB _u(8) -#define IO_BANK0_GPIO11_STATUS_OUTFROMPERI_ACCESS "RO" -// ============================================================================= -// Register : IO_BANK0_GPIO11_CTRL -// Description : GPIO control including function select and overrides. -#define IO_BANK0_GPIO11_CTRL_OFFSET _u(0x0000005c) -#define IO_BANK0_GPIO11_CTRL_BITS _u(0x3003331f) -#define IO_BANK0_GPIO11_CTRL_RESET _u(0x0000001f) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO11_CTRL_IRQOVER -// 0x0 -> don't invert the interrupt -// 0x1 -> invert the interrupt -// 0x2 -> drive interrupt low -// 0x3 -> drive interrupt high -#define IO_BANK0_GPIO11_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO11_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO11_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO11_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO11_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO11_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO11_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO11_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO11_CTRL_IRQOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO11_CTRL_INOVER -// 0x0 -> don't invert the peri input -// 0x1 -> invert the peri input -// 0x2 -> drive peri input low -// 0x3 -> drive peri input high -#define IO_BANK0_GPIO11_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO11_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO11_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO11_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO11_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO11_CTRL_INOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO11_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO11_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO11_CTRL_INOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO11_CTRL_OEOVER -// 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel -// 0x2 -> disable output -// 0x3 -> enable output -#define IO_BANK0_GPIO11_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO11_CTRL_OEOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO11_CTRL_OEOVER_MSB _u(13) -#define IO_BANK0_GPIO11_CTRL_OEOVER_LSB _u(12) -#define IO_BANK0_GPIO11_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO11_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO11_CTRL_OEOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO11_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO11_CTRL_OEOVER_VALUE_ENABLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO11_CTRL_OUTOVER -// 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel -// 0x2 -> drive output low -// 0x3 -> drive output high -#define IO_BANK0_GPIO11_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO11_CTRL_OUTOVER_BITS _u(0x00000300) -#define IO_BANK0_GPIO11_CTRL_OUTOVER_MSB _u(9) -#define IO_BANK0_GPIO11_CTRL_OUTOVER_LSB _u(8) -#define IO_BANK0_GPIO11_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO11_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO11_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO11_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO11_CTRL_OUTOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO11_CTRL_FUNCSEL -// Description : 0-31 -> selects pin function according to the gpio table -// 31 == NULL -// 0x01 -> spi1_tx -// 0x02 -> uart1_rts -// 0x03 -> i2c1_scl -// 0x04 -> pwm_b_5 -// 0x05 -> sio_11 -// 0x06 -> pio0_11 -// 0x07 -> pio1_11 -// 0x08 -> usb_muxing_extphy_suspnd -// 0x09 -> usb_muxing_vbus_en -// 0x1f -> null -#define IO_BANK0_GPIO11_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO11_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO11_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO11_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO11_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_SPI1_TX _u(0x01) -#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_UART1_RTS _u(0x02) -#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03) -#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_PWM_B_5 _u(0x04) -#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_SIO_11 _u(0x05) -#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_PIO0_11 _u(0x06) -#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_PIO1_11 _u(0x07) -#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_SUSPND _u(0x08) -#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x09) -#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) -// ============================================================================= -// Register : IO_BANK0_GPIO12_STATUS -// Description : GPIO status -#define IO_BANK0_GPIO12_STATUS_OFFSET _u(0x00000060) -#define IO_BANK0_GPIO12_STATUS_BITS _u(0x050a3300) -#define IO_BANK0_GPIO12_STATUS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO12_STATUS_IRQTOPROC -// Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO12_STATUS_IRQTOPROC_RESET _u(0x0) -#define IO_BANK0_GPIO12_STATUS_IRQTOPROC_BITS _u(0x04000000) -#define IO_BANK0_GPIO12_STATUS_IRQTOPROC_MSB _u(26) -#define IO_BANK0_GPIO12_STATUS_IRQTOPROC_LSB _u(26) -#define IO_BANK0_GPIO12_STATUS_IRQTOPROC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO12_STATUS_IRQFROMPAD -// Description : interrupt from pad before override is applied -#define IO_BANK0_GPIO12_STATUS_IRQFROMPAD_RESET _u(0x0) -#define IO_BANK0_GPIO12_STATUS_IRQFROMPAD_BITS _u(0x01000000) -#define IO_BANK0_GPIO12_STATUS_IRQFROMPAD_MSB _u(24) -#define IO_BANK0_GPIO12_STATUS_IRQFROMPAD_LSB _u(24) -#define IO_BANK0_GPIO12_STATUS_IRQFROMPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO12_STATUS_INTOPERI -// Description : input signal to peripheral, after override is applied -#define IO_BANK0_GPIO12_STATUS_INTOPERI_RESET _u(0x0) -#define IO_BANK0_GPIO12_STATUS_INTOPERI_BITS _u(0x00080000) -#define IO_BANK0_GPIO12_STATUS_INTOPERI_MSB _u(19) -#define IO_BANK0_GPIO12_STATUS_INTOPERI_LSB _u(19) -#define IO_BANK0_GPIO12_STATUS_INTOPERI_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO12_STATUS_INFROMPAD -// Description : input signal from pad, before override is applied -#define IO_BANK0_GPIO12_STATUS_INFROMPAD_RESET _u(0x0) -#define IO_BANK0_GPIO12_STATUS_INFROMPAD_BITS _u(0x00020000) -#define IO_BANK0_GPIO12_STATUS_INFROMPAD_MSB _u(17) -#define IO_BANK0_GPIO12_STATUS_INFROMPAD_LSB _u(17) -#define IO_BANK0_GPIO12_STATUS_INFROMPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO12_STATUS_OETOPAD -// Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO12_STATUS_OETOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO12_STATUS_OETOPAD_BITS _u(0x00002000) -#define IO_BANK0_GPIO12_STATUS_OETOPAD_MSB _u(13) -#define IO_BANK0_GPIO12_STATUS_OETOPAD_LSB _u(13) -#define IO_BANK0_GPIO12_STATUS_OETOPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO12_STATUS_OEFROMPERI -// Description : output enable from selected peripheral, before register -// override is applied -#define IO_BANK0_GPIO12_STATUS_OEFROMPERI_RESET _u(0x0) -#define IO_BANK0_GPIO12_STATUS_OEFROMPERI_BITS _u(0x00001000) -#define IO_BANK0_GPIO12_STATUS_OEFROMPERI_MSB _u(12) -#define IO_BANK0_GPIO12_STATUS_OEFROMPERI_LSB _u(12) -#define IO_BANK0_GPIO12_STATUS_OEFROMPERI_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO12_STATUS_OUTTOPAD -// Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO12_STATUS_OUTTOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO12_STATUS_OUTTOPAD_BITS _u(0x00000200) -#define IO_BANK0_GPIO12_STATUS_OUTTOPAD_MSB _u(9) -#define IO_BANK0_GPIO12_STATUS_OUTTOPAD_LSB _u(9) -#define IO_BANK0_GPIO12_STATUS_OUTTOPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO12_STATUS_OUTFROMPERI -// Description : output signal from selected peripheral, before register -// override is applied -#define IO_BANK0_GPIO12_STATUS_OUTFROMPERI_RESET _u(0x0) -#define IO_BANK0_GPIO12_STATUS_OUTFROMPERI_BITS _u(0x00000100) -#define IO_BANK0_GPIO12_STATUS_OUTFROMPERI_MSB _u(8) -#define IO_BANK0_GPIO12_STATUS_OUTFROMPERI_LSB _u(8) -#define IO_BANK0_GPIO12_STATUS_OUTFROMPERI_ACCESS "RO" -// ============================================================================= -// Register : IO_BANK0_GPIO12_CTRL -// Description : GPIO control including function select and overrides. -#define IO_BANK0_GPIO12_CTRL_OFFSET _u(0x00000064) -#define IO_BANK0_GPIO12_CTRL_BITS _u(0x3003331f) -#define IO_BANK0_GPIO12_CTRL_RESET _u(0x0000001f) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO12_CTRL_IRQOVER -// 0x0 -> don't invert the interrupt -// 0x1 -> invert the interrupt -// 0x2 -> drive interrupt low -// 0x3 -> drive interrupt high -#define IO_BANK0_GPIO12_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO12_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO12_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO12_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO12_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO12_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO12_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO12_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO12_CTRL_IRQOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO12_CTRL_INOVER -// 0x0 -> don't invert the peri input -// 0x1 -> invert the peri input -// 0x2 -> drive peri input low -// 0x3 -> drive peri input high -#define IO_BANK0_GPIO12_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO12_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO12_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO12_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO12_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO12_CTRL_INOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO12_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO12_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO12_CTRL_INOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO12_CTRL_OEOVER -// 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel -// 0x2 -> disable output -// 0x3 -> enable output -#define IO_BANK0_GPIO12_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO12_CTRL_OEOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO12_CTRL_OEOVER_MSB _u(13) -#define IO_BANK0_GPIO12_CTRL_OEOVER_LSB _u(12) -#define IO_BANK0_GPIO12_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO12_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO12_CTRL_OEOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO12_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO12_CTRL_OEOVER_VALUE_ENABLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO12_CTRL_OUTOVER -// 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel -// 0x2 -> drive output low -// 0x3 -> drive output high -#define IO_BANK0_GPIO12_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO12_CTRL_OUTOVER_BITS _u(0x00000300) -#define IO_BANK0_GPIO12_CTRL_OUTOVER_MSB _u(9) -#define IO_BANK0_GPIO12_CTRL_OUTOVER_LSB _u(8) -#define IO_BANK0_GPIO12_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO12_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO12_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO12_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO12_CTRL_OUTOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO12_CTRL_FUNCSEL -// Description : 0-31 -> selects pin function according to the gpio table -// 31 == NULL -// 0x01 -> spi1_rx -// 0x02 -> uart0_tx -// 0x03 -> i2c0_sda -// 0x04 -> pwm_a_6 -// 0x05 -> sio_12 -// 0x06 -> pio0_12 -// 0x07 -> pio1_12 -// 0x08 -> usb_muxing_extphy_speed -// 0x09 -> usb_muxing_overcurr_detect -// 0x1f -> null -#define IO_BANK0_GPIO12_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO12_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO12_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO12_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO12_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_SPI1_RX _u(0x01) -#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_UART0_TX _u(0x02) -#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03) -#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_PWM_A_6 _u(0x04) -#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_SIO_12 _u(0x05) -#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_PIO0_12 _u(0x06) -#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_PIO1_12 _u(0x07) -#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_SPEED _u(0x08) -#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x09) -#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) -// ============================================================================= -// Register : IO_BANK0_GPIO13_STATUS -// Description : GPIO status -#define IO_BANK0_GPIO13_STATUS_OFFSET _u(0x00000068) -#define IO_BANK0_GPIO13_STATUS_BITS _u(0x050a3300) -#define IO_BANK0_GPIO13_STATUS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO13_STATUS_IRQTOPROC -// Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO13_STATUS_IRQTOPROC_RESET _u(0x0) -#define IO_BANK0_GPIO13_STATUS_IRQTOPROC_BITS _u(0x04000000) -#define IO_BANK0_GPIO13_STATUS_IRQTOPROC_MSB _u(26) -#define IO_BANK0_GPIO13_STATUS_IRQTOPROC_LSB _u(26) -#define IO_BANK0_GPIO13_STATUS_IRQTOPROC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO13_STATUS_IRQFROMPAD -// Description : interrupt from pad before override is applied -#define IO_BANK0_GPIO13_STATUS_IRQFROMPAD_RESET _u(0x0) -#define IO_BANK0_GPIO13_STATUS_IRQFROMPAD_BITS _u(0x01000000) -#define IO_BANK0_GPIO13_STATUS_IRQFROMPAD_MSB _u(24) -#define IO_BANK0_GPIO13_STATUS_IRQFROMPAD_LSB _u(24) -#define IO_BANK0_GPIO13_STATUS_IRQFROMPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO13_STATUS_INTOPERI -// Description : input signal to peripheral, after override is applied -#define IO_BANK0_GPIO13_STATUS_INTOPERI_RESET _u(0x0) -#define IO_BANK0_GPIO13_STATUS_INTOPERI_BITS _u(0x00080000) -#define IO_BANK0_GPIO13_STATUS_INTOPERI_MSB _u(19) -#define IO_BANK0_GPIO13_STATUS_INTOPERI_LSB _u(19) -#define IO_BANK0_GPIO13_STATUS_INTOPERI_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO13_STATUS_INFROMPAD -// Description : input signal from pad, before override is applied -#define IO_BANK0_GPIO13_STATUS_INFROMPAD_RESET _u(0x0) -#define IO_BANK0_GPIO13_STATUS_INFROMPAD_BITS _u(0x00020000) -#define IO_BANK0_GPIO13_STATUS_INFROMPAD_MSB _u(17) -#define IO_BANK0_GPIO13_STATUS_INFROMPAD_LSB _u(17) -#define IO_BANK0_GPIO13_STATUS_INFROMPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO13_STATUS_OETOPAD -// Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO13_STATUS_OETOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO13_STATUS_OETOPAD_BITS _u(0x00002000) -#define IO_BANK0_GPIO13_STATUS_OETOPAD_MSB _u(13) -#define IO_BANK0_GPIO13_STATUS_OETOPAD_LSB _u(13) -#define IO_BANK0_GPIO13_STATUS_OETOPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO13_STATUS_OEFROMPERI -// Description : output enable from selected peripheral, before register -// override is applied -#define IO_BANK0_GPIO13_STATUS_OEFROMPERI_RESET _u(0x0) -#define IO_BANK0_GPIO13_STATUS_OEFROMPERI_BITS _u(0x00001000) -#define IO_BANK0_GPIO13_STATUS_OEFROMPERI_MSB _u(12) -#define IO_BANK0_GPIO13_STATUS_OEFROMPERI_LSB _u(12) -#define IO_BANK0_GPIO13_STATUS_OEFROMPERI_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO13_STATUS_OUTTOPAD -// Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO13_STATUS_OUTTOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO13_STATUS_OUTTOPAD_BITS _u(0x00000200) -#define IO_BANK0_GPIO13_STATUS_OUTTOPAD_MSB _u(9) -#define IO_BANK0_GPIO13_STATUS_OUTTOPAD_LSB _u(9) -#define IO_BANK0_GPIO13_STATUS_OUTTOPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO13_STATUS_OUTFROMPERI -// Description : output signal from selected peripheral, before register -// override is applied -#define IO_BANK0_GPIO13_STATUS_OUTFROMPERI_RESET _u(0x0) -#define IO_BANK0_GPIO13_STATUS_OUTFROMPERI_BITS _u(0x00000100) -#define IO_BANK0_GPIO13_STATUS_OUTFROMPERI_MSB _u(8) -#define IO_BANK0_GPIO13_STATUS_OUTFROMPERI_LSB _u(8) -#define IO_BANK0_GPIO13_STATUS_OUTFROMPERI_ACCESS "RO" -// ============================================================================= -// Register : IO_BANK0_GPIO13_CTRL -// Description : GPIO control including function select and overrides. -#define IO_BANK0_GPIO13_CTRL_OFFSET _u(0x0000006c) -#define IO_BANK0_GPIO13_CTRL_BITS _u(0x3003331f) -#define IO_BANK0_GPIO13_CTRL_RESET _u(0x0000001f) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO13_CTRL_IRQOVER -// 0x0 -> don't invert the interrupt -// 0x1 -> invert the interrupt -// 0x2 -> drive interrupt low -// 0x3 -> drive interrupt high -#define IO_BANK0_GPIO13_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO13_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO13_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO13_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO13_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO13_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO13_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO13_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO13_CTRL_IRQOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO13_CTRL_INOVER -// 0x0 -> don't invert the peri input -// 0x1 -> invert the peri input -// 0x2 -> drive peri input low -// 0x3 -> drive peri input high -#define IO_BANK0_GPIO13_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO13_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO13_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO13_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO13_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO13_CTRL_INOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO13_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO13_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO13_CTRL_INOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO13_CTRL_OEOVER -// 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel -// 0x2 -> disable output -// 0x3 -> enable output -#define IO_BANK0_GPIO13_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO13_CTRL_OEOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO13_CTRL_OEOVER_MSB _u(13) -#define IO_BANK0_GPIO13_CTRL_OEOVER_LSB _u(12) -#define IO_BANK0_GPIO13_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO13_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO13_CTRL_OEOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO13_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO13_CTRL_OEOVER_VALUE_ENABLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO13_CTRL_OUTOVER -// 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel -// 0x2 -> drive output low -// 0x3 -> drive output high -#define IO_BANK0_GPIO13_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO13_CTRL_OUTOVER_BITS _u(0x00000300) -#define IO_BANK0_GPIO13_CTRL_OUTOVER_MSB _u(9) -#define IO_BANK0_GPIO13_CTRL_OUTOVER_LSB _u(8) -#define IO_BANK0_GPIO13_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO13_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO13_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO13_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO13_CTRL_OUTOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO13_CTRL_FUNCSEL -// Description : 0-31 -> selects pin function according to the gpio table -// 31 == NULL -// 0x01 -> spi1_ss_n -// 0x02 -> uart0_rx -// 0x03 -> i2c0_scl -// 0x04 -> pwm_b_6 -// 0x05 -> sio_13 -// 0x06 -> pio0_13 -// 0x07 -> pio1_13 -// 0x08 -> usb_muxing_extphy_vpo -// 0x09 -> usb_muxing_vbus_detect -// 0x1f -> null -#define IO_BANK0_GPIO13_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO13_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO13_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO13_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO13_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_SPI1_SS_N _u(0x01) -#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_UART0_RX _u(0x02) -#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03) -#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_PWM_B_6 _u(0x04) -#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_SIO_13 _u(0x05) -#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_PIO0_13 _u(0x06) -#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_PIO1_13 _u(0x07) -#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_VPO _u(0x08) -#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x09) -#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) -// ============================================================================= -// Register : IO_BANK0_GPIO14_STATUS -// Description : GPIO status -#define IO_BANK0_GPIO14_STATUS_OFFSET _u(0x00000070) -#define IO_BANK0_GPIO14_STATUS_BITS _u(0x050a3300) -#define IO_BANK0_GPIO14_STATUS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO14_STATUS_IRQTOPROC -// Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO14_STATUS_IRQTOPROC_RESET _u(0x0) -#define IO_BANK0_GPIO14_STATUS_IRQTOPROC_BITS _u(0x04000000) -#define IO_BANK0_GPIO14_STATUS_IRQTOPROC_MSB _u(26) -#define IO_BANK0_GPIO14_STATUS_IRQTOPROC_LSB _u(26) -#define IO_BANK0_GPIO14_STATUS_IRQTOPROC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO14_STATUS_IRQFROMPAD -// Description : interrupt from pad before override is applied -#define IO_BANK0_GPIO14_STATUS_IRQFROMPAD_RESET _u(0x0) -#define IO_BANK0_GPIO14_STATUS_IRQFROMPAD_BITS _u(0x01000000) -#define IO_BANK0_GPIO14_STATUS_IRQFROMPAD_MSB _u(24) -#define IO_BANK0_GPIO14_STATUS_IRQFROMPAD_LSB _u(24) -#define IO_BANK0_GPIO14_STATUS_IRQFROMPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO14_STATUS_INTOPERI -// Description : input signal to peripheral, after override is applied -#define IO_BANK0_GPIO14_STATUS_INTOPERI_RESET _u(0x0) -#define IO_BANK0_GPIO14_STATUS_INTOPERI_BITS _u(0x00080000) -#define IO_BANK0_GPIO14_STATUS_INTOPERI_MSB _u(19) -#define IO_BANK0_GPIO14_STATUS_INTOPERI_LSB _u(19) -#define IO_BANK0_GPIO14_STATUS_INTOPERI_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO14_STATUS_INFROMPAD -// Description : input signal from pad, before override is applied -#define IO_BANK0_GPIO14_STATUS_INFROMPAD_RESET _u(0x0) -#define IO_BANK0_GPIO14_STATUS_INFROMPAD_BITS _u(0x00020000) -#define IO_BANK0_GPIO14_STATUS_INFROMPAD_MSB _u(17) -#define IO_BANK0_GPIO14_STATUS_INFROMPAD_LSB _u(17) -#define IO_BANK0_GPIO14_STATUS_INFROMPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO14_STATUS_OETOPAD -// Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO14_STATUS_OETOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO14_STATUS_OETOPAD_BITS _u(0x00002000) -#define IO_BANK0_GPIO14_STATUS_OETOPAD_MSB _u(13) -#define IO_BANK0_GPIO14_STATUS_OETOPAD_LSB _u(13) -#define IO_BANK0_GPIO14_STATUS_OETOPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO14_STATUS_OEFROMPERI -// Description : output enable from selected peripheral, before register -// override is applied -#define IO_BANK0_GPIO14_STATUS_OEFROMPERI_RESET _u(0x0) -#define IO_BANK0_GPIO14_STATUS_OEFROMPERI_BITS _u(0x00001000) -#define IO_BANK0_GPIO14_STATUS_OEFROMPERI_MSB _u(12) -#define IO_BANK0_GPIO14_STATUS_OEFROMPERI_LSB _u(12) -#define IO_BANK0_GPIO14_STATUS_OEFROMPERI_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO14_STATUS_OUTTOPAD -// Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO14_STATUS_OUTTOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO14_STATUS_OUTTOPAD_BITS _u(0x00000200) -#define IO_BANK0_GPIO14_STATUS_OUTTOPAD_MSB _u(9) -#define IO_BANK0_GPIO14_STATUS_OUTTOPAD_LSB _u(9) -#define IO_BANK0_GPIO14_STATUS_OUTTOPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO14_STATUS_OUTFROMPERI -// Description : output signal from selected peripheral, before register -// override is applied -#define IO_BANK0_GPIO14_STATUS_OUTFROMPERI_RESET _u(0x0) -#define IO_BANK0_GPIO14_STATUS_OUTFROMPERI_BITS _u(0x00000100) -#define IO_BANK0_GPIO14_STATUS_OUTFROMPERI_MSB _u(8) -#define IO_BANK0_GPIO14_STATUS_OUTFROMPERI_LSB _u(8) -#define IO_BANK0_GPIO14_STATUS_OUTFROMPERI_ACCESS "RO" -// ============================================================================= -// Register : IO_BANK0_GPIO14_CTRL -// Description : GPIO control including function select and overrides. -#define IO_BANK0_GPIO14_CTRL_OFFSET _u(0x00000074) -#define IO_BANK0_GPIO14_CTRL_BITS _u(0x3003331f) -#define IO_BANK0_GPIO14_CTRL_RESET _u(0x0000001f) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO14_CTRL_IRQOVER -// 0x0 -> don't invert the interrupt -// 0x1 -> invert the interrupt -// 0x2 -> drive interrupt low -// 0x3 -> drive interrupt high -#define IO_BANK0_GPIO14_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO14_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO14_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO14_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO14_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO14_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO14_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO14_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO14_CTRL_IRQOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO14_CTRL_INOVER -// 0x0 -> don't invert the peri input -// 0x1 -> invert the peri input -// 0x2 -> drive peri input low -// 0x3 -> drive peri input high -#define IO_BANK0_GPIO14_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO14_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO14_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO14_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO14_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO14_CTRL_INOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO14_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO14_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO14_CTRL_INOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO14_CTRL_OEOVER -// 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel -// 0x2 -> disable output -// 0x3 -> enable output -#define IO_BANK0_GPIO14_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO14_CTRL_OEOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO14_CTRL_OEOVER_MSB _u(13) -#define IO_BANK0_GPIO14_CTRL_OEOVER_LSB _u(12) -#define IO_BANK0_GPIO14_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO14_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO14_CTRL_OEOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO14_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO14_CTRL_OEOVER_VALUE_ENABLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO14_CTRL_OUTOVER -// 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel -// 0x2 -> drive output low -// 0x3 -> drive output high -#define IO_BANK0_GPIO14_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO14_CTRL_OUTOVER_BITS _u(0x00000300) -#define IO_BANK0_GPIO14_CTRL_OUTOVER_MSB _u(9) -#define IO_BANK0_GPIO14_CTRL_OUTOVER_LSB _u(8) -#define IO_BANK0_GPIO14_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO14_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO14_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO14_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO14_CTRL_OUTOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO14_CTRL_FUNCSEL -// Description : 0-31 -> selects pin function according to the gpio table -// 31 == NULL -// 0x01 -> spi1_sclk -// 0x02 -> uart0_cts -// 0x03 -> i2c1_sda -// 0x04 -> pwm_a_7 -// 0x05 -> sio_14 -// 0x06 -> pio0_14 -// 0x07 -> pio1_14 -// 0x08 -> usb_muxing_extphy_vmo -// 0x09 -> usb_muxing_vbus_en -// 0x1f -> null -#define IO_BANK0_GPIO14_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO14_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO14_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO14_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO14_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_SPI1_SCLK _u(0x01) -#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_UART0_CTS _u(0x02) -#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03) -#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_PWM_A_7 _u(0x04) -#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_SIO_14 _u(0x05) -#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_PIO0_14 _u(0x06) -#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_PIO1_14 _u(0x07) -#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_VMO _u(0x08) -#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x09) -#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) -// ============================================================================= -// Register : IO_BANK0_GPIO15_STATUS -// Description : GPIO status -#define IO_BANK0_GPIO15_STATUS_OFFSET _u(0x00000078) -#define IO_BANK0_GPIO15_STATUS_BITS _u(0x050a3300) -#define IO_BANK0_GPIO15_STATUS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO15_STATUS_IRQTOPROC -// Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO15_STATUS_IRQTOPROC_RESET _u(0x0) -#define IO_BANK0_GPIO15_STATUS_IRQTOPROC_BITS _u(0x04000000) -#define IO_BANK0_GPIO15_STATUS_IRQTOPROC_MSB _u(26) -#define IO_BANK0_GPIO15_STATUS_IRQTOPROC_LSB _u(26) -#define IO_BANK0_GPIO15_STATUS_IRQTOPROC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO15_STATUS_IRQFROMPAD -// Description : interrupt from pad before override is applied -#define IO_BANK0_GPIO15_STATUS_IRQFROMPAD_RESET _u(0x0) -#define IO_BANK0_GPIO15_STATUS_IRQFROMPAD_BITS _u(0x01000000) -#define IO_BANK0_GPIO15_STATUS_IRQFROMPAD_MSB _u(24) -#define IO_BANK0_GPIO15_STATUS_IRQFROMPAD_LSB _u(24) -#define IO_BANK0_GPIO15_STATUS_IRQFROMPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO15_STATUS_INTOPERI -// Description : input signal to peripheral, after override is applied -#define IO_BANK0_GPIO15_STATUS_INTOPERI_RESET _u(0x0) -#define IO_BANK0_GPIO15_STATUS_INTOPERI_BITS _u(0x00080000) -#define IO_BANK0_GPIO15_STATUS_INTOPERI_MSB _u(19) -#define IO_BANK0_GPIO15_STATUS_INTOPERI_LSB _u(19) -#define IO_BANK0_GPIO15_STATUS_INTOPERI_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO15_STATUS_INFROMPAD -// Description : input signal from pad, before override is applied -#define IO_BANK0_GPIO15_STATUS_INFROMPAD_RESET _u(0x0) -#define IO_BANK0_GPIO15_STATUS_INFROMPAD_BITS _u(0x00020000) -#define IO_BANK0_GPIO15_STATUS_INFROMPAD_MSB _u(17) -#define IO_BANK0_GPIO15_STATUS_INFROMPAD_LSB _u(17) -#define IO_BANK0_GPIO15_STATUS_INFROMPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO15_STATUS_OETOPAD -// Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO15_STATUS_OETOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO15_STATUS_OETOPAD_BITS _u(0x00002000) -#define IO_BANK0_GPIO15_STATUS_OETOPAD_MSB _u(13) -#define IO_BANK0_GPIO15_STATUS_OETOPAD_LSB _u(13) -#define IO_BANK0_GPIO15_STATUS_OETOPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO15_STATUS_OEFROMPERI -// Description : output enable from selected peripheral, before register -// override is applied -#define IO_BANK0_GPIO15_STATUS_OEFROMPERI_RESET _u(0x0) -#define IO_BANK0_GPIO15_STATUS_OEFROMPERI_BITS _u(0x00001000) -#define IO_BANK0_GPIO15_STATUS_OEFROMPERI_MSB _u(12) -#define IO_BANK0_GPIO15_STATUS_OEFROMPERI_LSB _u(12) -#define IO_BANK0_GPIO15_STATUS_OEFROMPERI_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO15_STATUS_OUTTOPAD -// Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO15_STATUS_OUTTOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO15_STATUS_OUTTOPAD_BITS _u(0x00000200) -#define IO_BANK0_GPIO15_STATUS_OUTTOPAD_MSB _u(9) -#define IO_BANK0_GPIO15_STATUS_OUTTOPAD_LSB _u(9) -#define IO_BANK0_GPIO15_STATUS_OUTTOPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO15_STATUS_OUTFROMPERI -// Description : output signal from selected peripheral, before register -// override is applied -#define IO_BANK0_GPIO15_STATUS_OUTFROMPERI_RESET _u(0x0) -#define IO_BANK0_GPIO15_STATUS_OUTFROMPERI_BITS _u(0x00000100) -#define IO_BANK0_GPIO15_STATUS_OUTFROMPERI_MSB _u(8) -#define IO_BANK0_GPIO15_STATUS_OUTFROMPERI_LSB _u(8) -#define IO_BANK0_GPIO15_STATUS_OUTFROMPERI_ACCESS "RO" -// ============================================================================= -// Register : IO_BANK0_GPIO15_CTRL -// Description : GPIO control including function select and overrides. -#define IO_BANK0_GPIO15_CTRL_OFFSET _u(0x0000007c) -#define IO_BANK0_GPIO15_CTRL_BITS _u(0x3003331f) -#define IO_BANK0_GPIO15_CTRL_RESET _u(0x0000001f) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO15_CTRL_IRQOVER -// 0x0 -> don't invert the interrupt -// 0x1 -> invert the interrupt -// 0x2 -> drive interrupt low -// 0x3 -> drive interrupt high -#define IO_BANK0_GPIO15_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO15_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO15_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO15_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO15_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO15_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO15_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO15_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO15_CTRL_IRQOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO15_CTRL_INOVER -// 0x0 -> don't invert the peri input -// 0x1 -> invert the peri input -// 0x2 -> drive peri input low -// 0x3 -> drive peri input high -#define IO_BANK0_GPIO15_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO15_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO15_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO15_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO15_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO15_CTRL_INOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO15_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO15_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO15_CTRL_INOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO15_CTRL_OEOVER -// 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel -// 0x2 -> disable output -// 0x3 -> enable output -#define IO_BANK0_GPIO15_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO15_CTRL_OEOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO15_CTRL_OEOVER_MSB _u(13) -#define IO_BANK0_GPIO15_CTRL_OEOVER_LSB _u(12) -#define IO_BANK0_GPIO15_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO15_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO15_CTRL_OEOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO15_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO15_CTRL_OEOVER_VALUE_ENABLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO15_CTRL_OUTOVER -// 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel -// 0x2 -> drive output low -// 0x3 -> drive output high -#define IO_BANK0_GPIO15_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO15_CTRL_OUTOVER_BITS _u(0x00000300) -#define IO_BANK0_GPIO15_CTRL_OUTOVER_MSB _u(9) -#define IO_BANK0_GPIO15_CTRL_OUTOVER_LSB _u(8) -#define IO_BANK0_GPIO15_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO15_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO15_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO15_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO15_CTRL_OUTOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO15_CTRL_FUNCSEL -// Description : 0-31 -> selects pin function according to the gpio table -// 31 == NULL -// 0x01 -> spi1_tx -// 0x02 -> uart0_rts -// 0x03 -> i2c1_scl -// 0x04 -> pwm_b_7 -// 0x05 -> sio_15 -// 0x06 -> pio0_15 -// 0x07 -> pio1_15 -// 0x08 -> usb_muxing_digital_dp -// 0x09 -> usb_muxing_overcurr_detect -// 0x1f -> null -#define IO_BANK0_GPIO15_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO15_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO15_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO15_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO15_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_SPI1_TX _u(0x01) -#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_UART0_RTS _u(0x02) -#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03) -#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_PWM_B_7 _u(0x04) -#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_SIO_15 _u(0x05) -#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_PIO0_15 _u(0x06) -#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_PIO1_15 _u(0x07) -#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_USB_MUXING_DIGITAL_DP _u(0x08) -#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x09) -#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) -// ============================================================================= -// Register : IO_BANK0_GPIO16_STATUS -// Description : GPIO status -#define IO_BANK0_GPIO16_STATUS_OFFSET _u(0x00000080) -#define IO_BANK0_GPIO16_STATUS_BITS _u(0x050a3300) -#define IO_BANK0_GPIO16_STATUS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO16_STATUS_IRQTOPROC -// Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO16_STATUS_IRQTOPROC_RESET _u(0x0) -#define IO_BANK0_GPIO16_STATUS_IRQTOPROC_BITS _u(0x04000000) -#define IO_BANK0_GPIO16_STATUS_IRQTOPROC_MSB _u(26) -#define IO_BANK0_GPIO16_STATUS_IRQTOPROC_LSB _u(26) -#define IO_BANK0_GPIO16_STATUS_IRQTOPROC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO16_STATUS_IRQFROMPAD -// Description : interrupt from pad before override is applied -#define IO_BANK0_GPIO16_STATUS_IRQFROMPAD_RESET _u(0x0) -#define IO_BANK0_GPIO16_STATUS_IRQFROMPAD_BITS _u(0x01000000) -#define IO_BANK0_GPIO16_STATUS_IRQFROMPAD_MSB _u(24) -#define IO_BANK0_GPIO16_STATUS_IRQFROMPAD_LSB _u(24) -#define IO_BANK0_GPIO16_STATUS_IRQFROMPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO16_STATUS_INTOPERI -// Description : input signal to peripheral, after override is applied -#define IO_BANK0_GPIO16_STATUS_INTOPERI_RESET _u(0x0) -#define IO_BANK0_GPIO16_STATUS_INTOPERI_BITS _u(0x00080000) -#define IO_BANK0_GPIO16_STATUS_INTOPERI_MSB _u(19) -#define IO_BANK0_GPIO16_STATUS_INTOPERI_LSB _u(19) -#define IO_BANK0_GPIO16_STATUS_INTOPERI_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO16_STATUS_INFROMPAD -// Description : input signal from pad, before override is applied -#define IO_BANK0_GPIO16_STATUS_INFROMPAD_RESET _u(0x0) -#define IO_BANK0_GPIO16_STATUS_INFROMPAD_BITS _u(0x00020000) -#define IO_BANK0_GPIO16_STATUS_INFROMPAD_MSB _u(17) -#define IO_BANK0_GPIO16_STATUS_INFROMPAD_LSB _u(17) -#define IO_BANK0_GPIO16_STATUS_INFROMPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO16_STATUS_OETOPAD -// Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO16_STATUS_OETOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO16_STATUS_OETOPAD_BITS _u(0x00002000) -#define IO_BANK0_GPIO16_STATUS_OETOPAD_MSB _u(13) -#define IO_BANK0_GPIO16_STATUS_OETOPAD_LSB _u(13) -#define IO_BANK0_GPIO16_STATUS_OETOPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO16_STATUS_OEFROMPERI -// Description : output enable from selected peripheral, before register -// override is applied -#define IO_BANK0_GPIO16_STATUS_OEFROMPERI_RESET _u(0x0) -#define IO_BANK0_GPIO16_STATUS_OEFROMPERI_BITS _u(0x00001000) -#define IO_BANK0_GPIO16_STATUS_OEFROMPERI_MSB _u(12) -#define IO_BANK0_GPIO16_STATUS_OEFROMPERI_LSB _u(12) -#define IO_BANK0_GPIO16_STATUS_OEFROMPERI_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO16_STATUS_OUTTOPAD -// Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO16_STATUS_OUTTOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO16_STATUS_OUTTOPAD_BITS _u(0x00000200) -#define IO_BANK0_GPIO16_STATUS_OUTTOPAD_MSB _u(9) -#define IO_BANK0_GPIO16_STATUS_OUTTOPAD_LSB _u(9) -#define IO_BANK0_GPIO16_STATUS_OUTTOPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO16_STATUS_OUTFROMPERI -// Description : output signal from selected peripheral, before register -// override is applied -#define IO_BANK0_GPIO16_STATUS_OUTFROMPERI_RESET _u(0x0) -#define IO_BANK0_GPIO16_STATUS_OUTFROMPERI_BITS _u(0x00000100) -#define IO_BANK0_GPIO16_STATUS_OUTFROMPERI_MSB _u(8) -#define IO_BANK0_GPIO16_STATUS_OUTFROMPERI_LSB _u(8) -#define IO_BANK0_GPIO16_STATUS_OUTFROMPERI_ACCESS "RO" -// ============================================================================= -// Register : IO_BANK0_GPIO16_CTRL -// Description : GPIO control including function select and overrides. -#define IO_BANK0_GPIO16_CTRL_OFFSET _u(0x00000084) -#define IO_BANK0_GPIO16_CTRL_BITS _u(0x3003331f) -#define IO_BANK0_GPIO16_CTRL_RESET _u(0x0000001f) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO16_CTRL_IRQOVER -// 0x0 -> don't invert the interrupt -// 0x1 -> invert the interrupt -// 0x2 -> drive interrupt low -// 0x3 -> drive interrupt high -#define IO_BANK0_GPIO16_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO16_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO16_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO16_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO16_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO16_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO16_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO16_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO16_CTRL_IRQOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO16_CTRL_INOVER -// 0x0 -> don't invert the peri input -// 0x1 -> invert the peri input -// 0x2 -> drive peri input low -// 0x3 -> drive peri input high -#define IO_BANK0_GPIO16_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO16_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO16_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO16_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO16_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO16_CTRL_INOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO16_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO16_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO16_CTRL_INOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO16_CTRL_OEOVER -// 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel -// 0x2 -> disable output -// 0x3 -> enable output -#define IO_BANK0_GPIO16_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO16_CTRL_OEOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO16_CTRL_OEOVER_MSB _u(13) -#define IO_BANK0_GPIO16_CTRL_OEOVER_LSB _u(12) -#define IO_BANK0_GPIO16_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO16_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO16_CTRL_OEOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO16_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO16_CTRL_OEOVER_VALUE_ENABLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO16_CTRL_OUTOVER -// 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel -// 0x2 -> drive output low -// 0x3 -> drive output high -#define IO_BANK0_GPIO16_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO16_CTRL_OUTOVER_BITS _u(0x00000300) -#define IO_BANK0_GPIO16_CTRL_OUTOVER_MSB _u(9) -#define IO_BANK0_GPIO16_CTRL_OUTOVER_LSB _u(8) -#define IO_BANK0_GPIO16_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO16_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO16_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO16_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO16_CTRL_OUTOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO16_CTRL_FUNCSEL -// Description : 0-31 -> selects pin function according to the gpio table -// 31 == NULL -// 0x01 -> spi0_rx -// 0x02 -> uart0_tx -// 0x03 -> i2c0_sda -// 0x04 -> pwm_a_0 -// 0x05 -> sio_16 -// 0x06 -> pio0_16 -// 0x07 -> pio1_16 -// 0x08 -> usb_muxing_digital_dm -// 0x09 -> usb_muxing_vbus_detect -// 0x1f -> null -#define IO_BANK0_GPIO16_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO16_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO16_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO16_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO16_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_SPI0_RX _u(0x01) -#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_UART0_TX _u(0x02) -#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03) -#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_PWM_A_0 _u(0x04) -#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_SIO_16 _u(0x05) -#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_PIO0_16 _u(0x06) -#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_PIO1_16 _u(0x07) -#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_USB_MUXING_DIGITAL_DM _u(0x08) -#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x09) -#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) -// ============================================================================= -// Register : IO_BANK0_GPIO17_STATUS -// Description : GPIO status -#define IO_BANK0_GPIO17_STATUS_OFFSET _u(0x00000088) -#define IO_BANK0_GPIO17_STATUS_BITS _u(0x050a3300) -#define IO_BANK0_GPIO17_STATUS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO17_STATUS_IRQTOPROC -// Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO17_STATUS_IRQTOPROC_RESET _u(0x0) -#define IO_BANK0_GPIO17_STATUS_IRQTOPROC_BITS _u(0x04000000) -#define IO_BANK0_GPIO17_STATUS_IRQTOPROC_MSB _u(26) -#define IO_BANK0_GPIO17_STATUS_IRQTOPROC_LSB _u(26) -#define IO_BANK0_GPIO17_STATUS_IRQTOPROC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO17_STATUS_IRQFROMPAD -// Description : interrupt from pad before override is applied -#define IO_BANK0_GPIO17_STATUS_IRQFROMPAD_RESET _u(0x0) -#define IO_BANK0_GPIO17_STATUS_IRQFROMPAD_BITS _u(0x01000000) -#define IO_BANK0_GPIO17_STATUS_IRQFROMPAD_MSB _u(24) -#define IO_BANK0_GPIO17_STATUS_IRQFROMPAD_LSB _u(24) -#define IO_BANK0_GPIO17_STATUS_IRQFROMPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO17_STATUS_INTOPERI -// Description : input signal to peripheral, after override is applied -#define IO_BANK0_GPIO17_STATUS_INTOPERI_RESET _u(0x0) -#define IO_BANK0_GPIO17_STATUS_INTOPERI_BITS _u(0x00080000) -#define IO_BANK0_GPIO17_STATUS_INTOPERI_MSB _u(19) -#define IO_BANK0_GPIO17_STATUS_INTOPERI_LSB _u(19) -#define IO_BANK0_GPIO17_STATUS_INTOPERI_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO17_STATUS_INFROMPAD -// Description : input signal from pad, before override is applied -#define IO_BANK0_GPIO17_STATUS_INFROMPAD_RESET _u(0x0) -#define IO_BANK0_GPIO17_STATUS_INFROMPAD_BITS _u(0x00020000) -#define IO_BANK0_GPIO17_STATUS_INFROMPAD_MSB _u(17) -#define IO_BANK0_GPIO17_STATUS_INFROMPAD_LSB _u(17) -#define IO_BANK0_GPIO17_STATUS_INFROMPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO17_STATUS_OETOPAD -// Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO17_STATUS_OETOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO17_STATUS_OETOPAD_BITS _u(0x00002000) -#define IO_BANK0_GPIO17_STATUS_OETOPAD_MSB _u(13) -#define IO_BANK0_GPIO17_STATUS_OETOPAD_LSB _u(13) -#define IO_BANK0_GPIO17_STATUS_OETOPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO17_STATUS_OEFROMPERI -// Description : output enable from selected peripheral, before register -// override is applied -#define IO_BANK0_GPIO17_STATUS_OEFROMPERI_RESET _u(0x0) -#define IO_BANK0_GPIO17_STATUS_OEFROMPERI_BITS _u(0x00001000) -#define IO_BANK0_GPIO17_STATUS_OEFROMPERI_MSB _u(12) -#define IO_BANK0_GPIO17_STATUS_OEFROMPERI_LSB _u(12) -#define IO_BANK0_GPIO17_STATUS_OEFROMPERI_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO17_STATUS_OUTTOPAD -// Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO17_STATUS_OUTTOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO17_STATUS_OUTTOPAD_BITS _u(0x00000200) -#define IO_BANK0_GPIO17_STATUS_OUTTOPAD_MSB _u(9) -#define IO_BANK0_GPIO17_STATUS_OUTTOPAD_LSB _u(9) -#define IO_BANK0_GPIO17_STATUS_OUTTOPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO17_STATUS_OUTFROMPERI -// Description : output signal from selected peripheral, before register -// override is applied -#define IO_BANK0_GPIO17_STATUS_OUTFROMPERI_RESET _u(0x0) -#define IO_BANK0_GPIO17_STATUS_OUTFROMPERI_BITS _u(0x00000100) -#define IO_BANK0_GPIO17_STATUS_OUTFROMPERI_MSB _u(8) -#define IO_BANK0_GPIO17_STATUS_OUTFROMPERI_LSB _u(8) -#define IO_BANK0_GPIO17_STATUS_OUTFROMPERI_ACCESS "RO" -// ============================================================================= -// Register : IO_BANK0_GPIO17_CTRL -// Description : GPIO control including function select and overrides. -#define IO_BANK0_GPIO17_CTRL_OFFSET _u(0x0000008c) -#define IO_BANK0_GPIO17_CTRL_BITS _u(0x3003331f) -#define IO_BANK0_GPIO17_CTRL_RESET _u(0x0000001f) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO17_CTRL_IRQOVER -// 0x0 -> don't invert the interrupt -// 0x1 -> invert the interrupt -// 0x2 -> drive interrupt low -// 0x3 -> drive interrupt high -#define IO_BANK0_GPIO17_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO17_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO17_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO17_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO17_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO17_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO17_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO17_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO17_CTRL_IRQOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO17_CTRL_INOVER -// 0x0 -> don't invert the peri input -// 0x1 -> invert the peri input -// 0x2 -> drive peri input low -// 0x3 -> drive peri input high -#define IO_BANK0_GPIO17_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO17_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO17_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO17_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO17_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO17_CTRL_INOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO17_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO17_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO17_CTRL_INOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO17_CTRL_OEOVER -// 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel -// 0x2 -> disable output -// 0x3 -> enable output -#define IO_BANK0_GPIO17_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO17_CTRL_OEOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO17_CTRL_OEOVER_MSB _u(13) -#define IO_BANK0_GPIO17_CTRL_OEOVER_LSB _u(12) -#define IO_BANK0_GPIO17_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO17_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO17_CTRL_OEOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO17_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO17_CTRL_OEOVER_VALUE_ENABLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO17_CTRL_OUTOVER -// 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel -// 0x2 -> drive output low -// 0x3 -> drive output high -#define IO_BANK0_GPIO17_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO17_CTRL_OUTOVER_BITS _u(0x00000300) -#define IO_BANK0_GPIO17_CTRL_OUTOVER_MSB _u(9) -#define IO_BANK0_GPIO17_CTRL_OUTOVER_LSB _u(8) -#define IO_BANK0_GPIO17_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO17_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO17_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO17_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO17_CTRL_OUTOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO17_CTRL_FUNCSEL -// Description : 0-31 -> selects pin function according to the gpio table -// 31 == NULL -// 0x01 -> spi0_ss_n -// 0x02 -> uart0_rx -// 0x03 -> i2c0_scl -// 0x04 -> pwm_b_0 -// 0x05 -> sio_17 -// 0x06 -> pio0_17 -// 0x07 -> pio1_17 -// 0x09 -> usb_muxing_vbus_en -// 0x1f -> null -#define IO_BANK0_GPIO17_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO17_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO17_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO17_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO17_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_SPI0_SS_N _u(0x01) -#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_UART0_RX _u(0x02) -#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03) -#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_PWM_B_0 _u(0x04) -#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_SIO_17 _u(0x05) -#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_PIO0_17 _u(0x06) -#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_PIO1_17 _u(0x07) -#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x09) -#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) -// ============================================================================= -// Register : IO_BANK0_GPIO18_STATUS -// Description : GPIO status -#define IO_BANK0_GPIO18_STATUS_OFFSET _u(0x00000090) -#define IO_BANK0_GPIO18_STATUS_BITS _u(0x050a3300) -#define IO_BANK0_GPIO18_STATUS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO18_STATUS_IRQTOPROC -// Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO18_STATUS_IRQTOPROC_RESET _u(0x0) -#define IO_BANK0_GPIO18_STATUS_IRQTOPROC_BITS _u(0x04000000) -#define IO_BANK0_GPIO18_STATUS_IRQTOPROC_MSB _u(26) -#define IO_BANK0_GPIO18_STATUS_IRQTOPROC_LSB _u(26) -#define IO_BANK0_GPIO18_STATUS_IRQTOPROC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO18_STATUS_IRQFROMPAD -// Description : interrupt from pad before override is applied -#define IO_BANK0_GPIO18_STATUS_IRQFROMPAD_RESET _u(0x0) -#define IO_BANK0_GPIO18_STATUS_IRQFROMPAD_BITS _u(0x01000000) -#define IO_BANK0_GPIO18_STATUS_IRQFROMPAD_MSB _u(24) -#define IO_BANK0_GPIO18_STATUS_IRQFROMPAD_LSB _u(24) -#define IO_BANK0_GPIO18_STATUS_IRQFROMPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO18_STATUS_INTOPERI -// Description : input signal to peripheral, after override is applied -#define IO_BANK0_GPIO18_STATUS_INTOPERI_RESET _u(0x0) -#define IO_BANK0_GPIO18_STATUS_INTOPERI_BITS _u(0x00080000) -#define IO_BANK0_GPIO18_STATUS_INTOPERI_MSB _u(19) -#define IO_BANK0_GPIO18_STATUS_INTOPERI_LSB _u(19) -#define IO_BANK0_GPIO18_STATUS_INTOPERI_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO18_STATUS_INFROMPAD -// Description : input signal from pad, before override is applied -#define IO_BANK0_GPIO18_STATUS_INFROMPAD_RESET _u(0x0) -#define IO_BANK0_GPIO18_STATUS_INFROMPAD_BITS _u(0x00020000) -#define IO_BANK0_GPIO18_STATUS_INFROMPAD_MSB _u(17) -#define IO_BANK0_GPIO18_STATUS_INFROMPAD_LSB _u(17) -#define IO_BANK0_GPIO18_STATUS_INFROMPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO18_STATUS_OETOPAD -// Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO18_STATUS_OETOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO18_STATUS_OETOPAD_BITS _u(0x00002000) -#define IO_BANK0_GPIO18_STATUS_OETOPAD_MSB _u(13) -#define IO_BANK0_GPIO18_STATUS_OETOPAD_LSB _u(13) -#define IO_BANK0_GPIO18_STATUS_OETOPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO18_STATUS_OEFROMPERI -// Description : output enable from selected peripheral, before register -// override is applied -#define IO_BANK0_GPIO18_STATUS_OEFROMPERI_RESET _u(0x0) -#define IO_BANK0_GPIO18_STATUS_OEFROMPERI_BITS _u(0x00001000) -#define IO_BANK0_GPIO18_STATUS_OEFROMPERI_MSB _u(12) -#define IO_BANK0_GPIO18_STATUS_OEFROMPERI_LSB _u(12) -#define IO_BANK0_GPIO18_STATUS_OEFROMPERI_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO18_STATUS_OUTTOPAD -// Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO18_STATUS_OUTTOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO18_STATUS_OUTTOPAD_BITS _u(0x00000200) -#define IO_BANK0_GPIO18_STATUS_OUTTOPAD_MSB _u(9) -#define IO_BANK0_GPIO18_STATUS_OUTTOPAD_LSB _u(9) -#define IO_BANK0_GPIO18_STATUS_OUTTOPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO18_STATUS_OUTFROMPERI -// Description : output signal from selected peripheral, before register -// override is applied -#define IO_BANK0_GPIO18_STATUS_OUTFROMPERI_RESET _u(0x0) -#define IO_BANK0_GPIO18_STATUS_OUTFROMPERI_BITS _u(0x00000100) -#define IO_BANK0_GPIO18_STATUS_OUTFROMPERI_MSB _u(8) -#define IO_BANK0_GPIO18_STATUS_OUTFROMPERI_LSB _u(8) -#define IO_BANK0_GPIO18_STATUS_OUTFROMPERI_ACCESS "RO" -// ============================================================================= -// Register : IO_BANK0_GPIO18_CTRL -// Description : GPIO control including function select and overrides. -#define IO_BANK0_GPIO18_CTRL_OFFSET _u(0x00000094) -#define IO_BANK0_GPIO18_CTRL_BITS _u(0x3003331f) -#define IO_BANK0_GPIO18_CTRL_RESET _u(0x0000001f) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO18_CTRL_IRQOVER -// 0x0 -> don't invert the interrupt -// 0x1 -> invert the interrupt -// 0x2 -> drive interrupt low -// 0x3 -> drive interrupt high -#define IO_BANK0_GPIO18_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO18_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO18_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO18_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO18_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO18_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO18_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO18_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO18_CTRL_IRQOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO18_CTRL_INOVER -// 0x0 -> don't invert the peri input -// 0x1 -> invert the peri input -// 0x2 -> drive peri input low -// 0x3 -> drive peri input high -#define IO_BANK0_GPIO18_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO18_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO18_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO18_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO18_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO18_CTRL_INOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO18_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO18_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO18_CTRL_INOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO18_CTRL_OEOVER -// 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel -// 0x2 -> disable output -// 0x3 -> enable output -#define IO_BANK0_GPIO18_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO18_CTRL_OEOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO18_CTRL_OEOVER_MSB _u(13) -#define IO_BANK0_GPIO18_CTRL_OEOVER_LSB _u(12) -#define IO_BANK0_GPIO18_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO18_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO18_CTRL_OEOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO18_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO18_CTRL_OEOVER_VALUE_ENABLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO18_CTRL_OUTOVER -// 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel -// 0x2 -> drive output low -// 0x3 -> drive output high -#define IO_BANK0_GPIO18_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO18_CTRL_OUTOVER_BITS _u(0x00000300) -#define IO_BANK0_GPIO18_CTRL_OUTOVER_MSB _u(9) -#define IO_BANK0_GPIO18_CTRL_OUTOVER_LSB _u(8) -#define IO_BANK0_GPIO18_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO18_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO18_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO18_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO18_CTRL_OUTOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO18_CTRL_FUNCSEL -// Description : 0-31 -> selects pin function according to the gpio table -// 31 == NULL -// 0x01 -> spi0_sclk -// 0x02 -> uart0_cts -// 0x03 -> i2c1_sda -// 0x04 -> pwm_a_1 -// 0x05 -> sio_18 -// 0x06 -> pio0_18 -// 0x07 -> pio1_18 -// 0x09 -> usb_muxing_overcurr_detect -// 0x1f -> null -#define IO_BANK0_GPIO18_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO18_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO18_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO18_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO18_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_SPI0_SCLK _u(0x01) -#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_UART0_CTS _u(0x02) -#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03) -#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_PWM_A_1 _u(0x04) -#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_SIO_18 _u(0x05) -#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_PIO0_18 _u(0x06) -#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_PIO1_18 _u(0x07) -#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x09) -#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) -// ============================================================================= -// Register : IO_BANK0_GPIO19_STATUS -// Description : GPIO status -#define IO_BANK0_GPIO19_STATUS_OFFSET _u(0x00000098) -#define IO_BANK0_GPIO19_STATUS_BITS _u(0x050a3300) -#define IO_BANK0_GPIO19_STATUS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO19_STATUS_IRQTOPROC -// Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO19_STATUS_IRQTOPROC_RESET _u(0x0) -#define IO_BANK0_GPIO19_STATUS_IRQTOPROC_BITS _u(0x04000000) -#define IO_BANK0_GPIO19_STATUS_IRQTOPROC_MSB _u(26) -#define IO_BANK0_GPIO19_STATUS_IRQTOPROC_LSB _u(26) -#define IO_BANK0_GPIO19_STATUS_IRQTOPROC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO19_STATUS_IRQFROMPAD -// Description : interrupt from pad before override is applied -#define IO_BANK0_GPIO19_STATUS_IRQFROMPAD_RESET _u(0x0) -#define IO_BANK0_GPIO19_STATUS_IRQFROMPAD_BITS _u(0x01000000) -#define IO_BANK0_GPIO19_STATUS_IRQFROMPAD_MSB _u(24) -#define IO_BANK0_GPIO19_STATUS_IRQFROMPAD_LSB _u(24) -#define IO_BANK0_GPIO19_STATUS_IRQFROMPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO19_STATUS_INTOPERI -// Description : input signal to peripheral, after override is applied -#define IO_BANK0_GPIO19_STATUS_INTOPERI_RESET _u(0x0) -#define IO_BANK0_GPIO19_STATUS_INTOPERI_BITS _u(0x00080000) -#define IO_BANK0_GPIO19_STATUS_INTOPERI_MSB _u(19) -#define IO_BANK0_GPIO19_STATUS_INTOPERI_LSB _u(19) -#define IO_BANK0_GPIO19_STATUS_INTOPERI_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO19_STATUS_INFROMPAD -// Description : input signal from pad, before override is applied -#define IO_BANK0_GPIO19_STATUS_INFROMPAD_RESET _u(0x0) -#define IO_BANK0_GPIO19_STATUS_INFROMPAD_BITS _u(0x00020000) -#define IO_BANK0_GPIO19_STATUS_INFROMPAD_MSB _u(17) -#define IO_BANK0_GPIO19_STATUS_INFROMPAD_LSB _u(17) -#define IO_BANK0_GPIO19_STATUS_INFROMPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO19_STATUS_OETOPAD -// Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO19_STATUS_OETOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO19_STATUS_OETOPAD_BITS _u(0x00002000) -#define IO_BANK0_GPIO19_STATUS_OETOPAD_MSB _u(13) -#define IO_BANK0_GPIO19_STATUS_OETOPAD_LSB _u(13) -#define IO_BANK0_GPIO19_STATUS_OETOPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO19_STATUS_OEFROMPERI -// Description : output enable from selected peripheral, before register -// override is applied -#define IO_BANK0_GPIO19_STATUS_OEFROMPERI_RESET _u(0x0) -#define IO_BANK0_GPIO19_STATUS_OEFROMPERI_BITS _u(0x00001000) -#define IO_BANK0_GPIO19_STATUS_OEFROMPERI_MSB _u(12) -#define IO_BANK0_GPIO19_STATUS_OEFROMPERI_LSB _u(12) -#define IO_BANK0_GPIO19_STATUS_OEFROMPERI_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO19_STATUS_OUTTOPAD -// Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO19_STATUS_OUTTOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO19_STATUS_OUTTOPAD_BITS _u(0x00000200) -#define IO_BANK0_GPIO19_STATUS_OUTTOPAD_MSB _u(9) -#define IO_BANK0_GPIO19_STATUS_OUTTOPAD_LSB _u(9) -#define IO_BANK0_GPIO19_STATUS_OUTTOPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO19_STATUS_OUTFROMPERI -// Description : output signal from selected peripheral, before register -// override is applied -#define IO_BANK0_GPIO19_STATUS_OUTFROMPERI_RESET _u(0x0) -#define IO_BANK0_GPIO19_STATUS_OUTFROMPERI_BITS _u(0x00000100) -#define IO_BANK0_GPIO19_STATUS_OUTFROMPERI_MSB _u(8) -#define IO_BANK0_GPIO19_STATUS_OUTFROMPERI_LSB _u(8) -#define IO_BANK0_GPIO19_STATUS_OUTFROMPERI_ACCESS "RO" -// ============================================================================= -// Register : IO_BANK0_GPIO19_CTRL -// Description : GPIO control including function select and overrides. -#define IO_BANK0_GPIO19_CTRL_OFFSET _u(0x0000009c) -#define IO_BANK0_GPIO19_CTRL_BITS _u(0x3003331f) -#define IO_BANK0_GPIO19_CTRL_RESET _u(0x0000001f) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO19_CTRL_IRQOVER -// 0x0 -> don't invert the interrupt -// 0x1 -> invert the interrupt -// 0x2 -> drive interrupt low -// 0x3 -> drive interrupt high -#define IO_BANK0_GPIO19_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO19_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO19_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO19_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO19_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO19_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO19_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO19_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO19_CTRL_IRQOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO19_CTRL_INOVER -// 0x0 -> don't invert the peri input -// 0x1 -> invert the peri input -// 0x2 -> drive peri input low -// 0x3 -> drive peri input high -#define IO_BANK0_GPIO19_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO19_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO19_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO19_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO19_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO19_CTRL_INOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO19_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO19_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO19_CTRL_INOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO19_CTRL_OEOVER -// 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel -// 0x2 -> disable output -// 0x3 -> enable output -#define IO_BANK0_GPIO19_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO19_CTRL_OEOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO19_CTRL_OEOVER_MSB _u(13) -#define IO_BANK0_GPIO19_CTRL_OEOVER_LSB _u(12) -#define IO_BANK0_GPIO19_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO19_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO19_CTRL_OEOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO19_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO19_CTRL_OEOVER_VALUE_ENABLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO19_CTRL_OUTOVER -// 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel -// 0x2 -> drive output low -// 0x3 -> drive output high -#define IO_BANK0_GPIO19_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO19_CTRL_OUTOVER_BITS _u(0x00000300) -#define IO_BANK0_GPIO19_CTRL_OUTOVER_MSB _u(9) -#define IO_BANK0_GPIO19_CTRL_OUTOVER_LSB _u(8) -#define IO_BANK0_GPIO19_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO19_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO19_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO19_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO19_CTRL_OUTOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO19_CTRL_FUNCSEL -// Description : 0-31 -> selects pin function according to the gpio table -// 31 == NULL -// 0x01 -> spi0_tx -// 0x02 -> uart0_rts -// 0x03 -> i2c1_scl -// 0x04 -> pwm_b_1 -// 0x05 -> sio_19 -// 0x06 -> pio0_19 -// 0x07 -> pio1_19 -// 0x09 -> usb_muxing_vbus_detect -// 0x1f -> null -#define IO_BANK0_GPIO19_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO19_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO19_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO19_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO19_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_SPI0_TX _u(0x01) -#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_UART0_RTS _u(0x02) -#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03) -#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_PWM_B_1 _u(0x04) -#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_SIO_19 _u(0x05) -#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_PIO0_19 _u(0x06) -#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_PIO1_19 _u(0x07) -#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x09) -#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) -// ============================================================================= -// Register : IO_BANK0_GPIO20_STATUS -// Description : GPIO status -#define IO_BANK0_GPIO20_STATUS_OFFSET _u(0x000000a0) -#define IO_BANK0_GPIO20_STATUS_BITS _u(0x050a3300) -#define IO_BANK0_GPIO20_STATUS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO20_STATUS_IRQTOPROC -// Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO20_STATUS_IRQTOPROC_RESET _u(0x0) -#define IO_BANK0_GPIO20_STATUS_IRQTOPROC_BITS _u(0x04000000) -#define IO_BANK0_GPIO20_STATUS_IRQTOPROC_MSB _u(26) -#define IO_BANK0_GPIO20_STATUS_IRQTOPROC_LSB _u(26) -#define IO_BANK0_GPIO20_STATUS_IRQTOPROC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO20_STATUS_IRQFROMPAD -// Description : interrupt from pad before override is applied -#define IO_BANK0_GPIO20_STATUS_IRQFROMPAD_RESET _u(0x0) -#define IO_BANK0_GPIO20_STATUS_IRQFROMPAD_BITS _u(0x01000000) -#define IO_BANK0_GPIO20_STATUS_IRQFROMPAD_MSB _u(24) -#define IO_BANK0_GPIO20_STATUS_IRQFROMPAD_LSB _u(24) -#define IO_BANK0_GPIO20_STATUS_IRQFROMPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO20_STATUS_INTOPERI -// Description : input signal to peripheral, after override is applied -#define IO_BANK0_GPIO20_STATUS_INTOPERI_RESET _u(0x0) -#define IO_BANK0_GPIO20_STATUS_INTOPERI_BITS _u(0x00080000) -#define IO_BANK0_GPIO20_STATUS_INTOPERI_MSB _u(19) -#define IO_BANK0_GPIO20_STATUS_INTOPERI_LSB _u(19) -#define IO_BANK0_GPIO20_STATUS_INTOPERI_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO20_STATUS_INFROMPAD -// Description : input signal from pad, before override is applied -#define IO_BANK0_GPIO20_STATUS_INFROMPAD_RESET _u(0x0) -#define IO_BANK0_GPIO20_STATUS_INFROMPAD_BITS _u(0x00020000) -#define IO_BANK0_GPIO20_STATUS_INFROMPAD_MSB _u(17) -#define IO_BANK0_GPIO20_STATUS_INFROMPAD_LSB _u(17) -#define IO_BANK0_GPIO20_STATUS_INFROMPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO20_STATUS_OETOPAD -// Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO20_STATUS_OETOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO20_STATUS_OETOPAD_BITS _u(0x00002000) -#define IO_BANK0_GPIO20_STATUS_OETOPAD_MSB _u(13) -#define IO_BANK0_GPIO20_STATUS_OETOPAD_LSB _u(13) -#define IO_BANK0_GPIO20_STATUS_OETOPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO20_STATUS_OEFROMPERI -// Description : output enable from selected peripheral, before register -// override is applied -#define IO_BANK0_GPIO20_STATUS_OEFROMPERI_RESET _u(0x0) -#define IO_BANK0_GPIO20_STATUS_OEFROMPERI_BITS _u(0x00001000) -#define IO_BANK0_GPIO20_STATUS_OEFROMPERI_MSB _u(12) -#define IO_BANK0_GPIO20_STATUS_OEFROMPERI_LSB _u(12) -#define IO_BANK0_GPIO20_STATUS_OEFROMPERI_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO20_STATUS_OUTTOPAD -// Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO20_STATUS_OUTTOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO20_STATUS_OUTTOPAD_BITS _u(0x00000200) -#define IO_BANK0_GPIO20_STATUS_OUTTOPAD_MSB _u(9) -#define IO_BANK0_GPIO20_STATUS_OUTTOPAD_LSB _u(9) -#define IO_BANK0_GPIO20_STATUS_OUTTOPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO20_STATUS_OUTFROMPERI -// Description : output signal from selected peripheral, before register -// override is applied -#define IO_BANK0_GPIO20_STATUS_OUTFROMPERI_RESET _u(0x0) -#define IO_BANK0_GPIO20_STATUS_OUTFROMPERI_BITS _u(0x00000100) -#define IO_BANK0_GPIO20_STATUS_OUTFROMPERI_MSB _u(8) -#define IO_BANK0_GPIO20_STATUS_OUTFROMPERI_LSB _u(8) -#define IO_BANK0_GPIO20_STATUS_OUTFROMPERI_ACCESS "RO" -// ============================================================================= -// Register : IO_BANK0_GPIO20_CTRL -// Description : GPIO control including function select and overrides. -#define IO_BANK0_GPIO20_CTRL_OFFSET _u(0x000000a4) -#define IO_BANK0_GPIO20_CTRL_BITS _u(0x3003331f) -#define IO_BANK0_GPIO20_CTRL_RESET _u(0x0000001f) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO20_CTRL_IRQOVER -// 0x0 -> don't invert the interrupt -// 0x1 -> invert the interrupt -// 0x2 -> drive interrupt low -// 0x3 -> drive interrupt high -#define IO_BANK0_GPIO20_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO20_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO20_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO20_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO20_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO20_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO20_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO20_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO20_CTRL_IRQOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO20_CTRL_INOVER -// 0x0 -> don't invert the peri input -// 0x1 -> invert the peri input -// 0x2 -> drive peri input low -// 0x3 -> drive peri input high -#define IO_BANK0_GPIO20_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO20_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO20_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO20_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO20_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO20_CTRL_INOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO20_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO20_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO20_CTRL_INOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO20_CTRL_OEOVER -// 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel -// 0x2 -> disable output -// 0x3 -> enable output -#define IO_BANK0_GPIO20_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO20_CTRL_OEOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO20_CTRL_OEOVER_MSB _u(13) -#define IO_BANK0_GPIO20_CTRL_OEOVER_LSB _u(12) -#define IO_BANK0_GPIO20_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO20_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO20_CTRL_OEOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO20_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO20_CTRL_OEOVER_VALUE_ENABLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO20_CTRL_OUTOVER -// 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel -// 0x2 -> drive output low -// 0x3 -> drive output high -#define IO_BANK0_GPIO20_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO20_CTRL_OUTOVER_BITS _u(0x00000300) -#define IO_BANK0_GPIO20_CTRL_OUTOVER_MSB _u(9) -#define IO_BANK0_GPIO20_CTRL_OUTOVER_LSB _u(8) -#define IO_BANK0_GPIO20_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO20_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO20_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO20_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO20_CTRL_OUTOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO20_CTRL_FUNCSEL -// Description : 0-31 -> selects pin function according to the gpio table -// 31 == NULL -// 0x01 -> spi0_rx -// 0x02 -> uart1_tx -// 0x03 -> i2c0_sda -// 0x04 -> pwm_a_2 -// 0x05 -> sio_20 -// 0x06 -> pio0_20 -// 0x07 -> pio1_20 -// 0x08 -> clocks_gpin_0 -// 0x09 -> usb_muxing_vbus_en -// 0x1f -> null -#define IO_BANK0_GPIO20_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO20_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO20_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO20_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO20_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_SPI0_RX _u(0x01) -#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_UART1_TX _u(0x02) -#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03) -#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_PWM_A_2 _u(0x04) -#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_SIO_20 _u(0x05) -#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_PIO0_20 _u(0x06) -#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_PIO1_20 _u(0x07) -#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_CLOCKS_GPIN_0 _u(0x08) -#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x09) -#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) -// ============================================================================= -// Register : IO_BANK0_GPIO21_STATUS -// Description : GPIO status -#define IO_BANK0_GPIO21_STATUS_OFFSET _u(0x000000a8) -#define IO_BANK0_GPIO21_STATUS_BITS _u(0x050a3300) -#define IO_BANK0_GPIO21_STATUS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO21_STATUS_IRQTOPROC -// Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO21_STATUS_IRQTOPROC_RESET _u(0x0) -#define IO_BANK0_GPIO21_STATUS_IRQTOPROC_BITS _u(0x04000000) -#define IO_BANK0_GPIO21_STATUS_IRQTOPROC_MSB _u(26) -#define IO_BANK0_GPIO21_STATUS_IRQTOPROC_LSB _u(26) -#define IO_BANK0_GPIO21_STATUS_IRQTOPROC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO21_STATUS_IRQFROMPAD -// Description : interrupt from pad before override is applied -#define IO_BANK0_GPIO21_STATUS_IRQFROMPAD_RESET _u(0x0) -#define IO_BANK0_GPIO21_STATUS_IRQFROMPAD_BITS _u(0x01000000) -#define IO_BANK0_GPIO21_STATUS_IRQFROMPAD_MSB _u(24) -#define IO_BANK0_GPIO21_STATUS_IRQFROMPAD_LSB _u(24) -#define IO_BANK0_GPIO21_STATUS_IRQFROMPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO21_STATUS_INTOPERI -// Description : input signal to peripheral, after override is applied -#define IO_BANK0_GPIO21_STATUS_INTOPERI_RESET _u(0x0) -#define IO_BANK0_GPIO21_STATUS_INTOPERI_BITS _u(0x00080000) -#define IO_BANK0_GPIO21_STATUS_INTOPERI_MSB _u(19) -#define IO_BANK0_GPIO21_STATUS_INTOPERI_LSB _u(19) -#define IO_BANK0_GPIO21_STATUS_INTOPERI_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO21_STATUS_INFROMPAD -// Description : input signal from pad, before override is applied -#define IO_BANK0_GPIO21_STATUS_INFROMPAD_RESET _u(0x0) -#define IO_BANK0_GPIO21_STATUS_INFROMPAD_BITS _u(0x00020000) -#define IO_BANK0_GPIO21_STATUS_INFROMPAD_MSB _u(17) -#define IO_BANK0_GPIO21_STATUS_INFROMPAD_LSB _u(17) -#define IO_BANK0_GPIO21_STATUS_INFROMPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO21_STATUS_OETOPAD -// Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO21_STATUS_OETOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO21_STATUS_OETOPAD_BITS _u(0x00002000) -#define IO_BANK0_GPIO21_STATUS_OETOPAD_MSB _u(13) -#define IO_BANK0_GPIO21_STATUS_OETOPAD_LSB _u(13) -#define IO_BANK0_GPIO21_STATUS_OETOPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO21_STATUS_OEFROMPERI -// Description : output enable from selected peripheral, before register -// override is applied -#define IO_BANK0_GPIO21_STATUS_OEFROMPERI_RESET _u(0x0) -#define IO_BANK0_GPIO21_STATUS_OEFROMPERI_BITS _u(0x00001000) -#define IO_BANK0_GPIO21_STATUS_OEFROMPERI_MSB _u(12) -#define IO_BANK0_GPIO21_STATUS_OEFROMPERI_LSB _u(12) -#define IO_BANK0_GPIO21_STATUS_OEFROMPERI_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO21_STATUS_OUTTOPAD -// Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO21_STATUS_OUTTOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO21_STATUS_OUTTOPAD_BITS _u(0x00000200) -#define IO_BANK0_GPIO21_STATUS_OUTTOPAD_MSB _u(9) -#define IO_BANK0_GPIO21_STATUS_OUTTOPAD_LSB _u(9) -#define IO_BANK0_GPIO21_STATUS_OUTTOPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO21_STATUS_OUTFROMPERI -// Description : output signal from selected peripheral, before register -// override is applied -#define IO_BANK0_GPIO21_STATUS_OUTFROMPERI_RESET _u(0x0) -#define IO_BANK0_GPIO21_STATUS_OUTFROMPERI_BITS _u(0x00000100) -#define IO_BANK0_GPIO21_STATUS_OUTFROMPERI_MSB _u(8) -#define IO_BANK0_GPIO21_STATUS_OUTFROMPERI_LSB _u(8) -#define IO_BANK0_GPIO21_STATUS_OUTFROMPERI_ACCESS "RO" -// ============================================================================= -// Register : IO_BANK0_GPIO21_CTRL -// Description : GPIO control including function select and overrides. -#define IO_BANK0_GPIO21_CTRL_OFFSET _u(0x000000ac) -#define IO_BANK0_GPIO21_CTRL_BITS _u(0x3003331f) -#define IO_BANK0_GPIO21_CTRL_RESET _u(0x0000001f) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO21_CTRL_IRQOVER -// 0x0 -> don't invert the interrupt -// 0x1 -> invert the interrupt -// 0x2 -> drive interrupt low -// 0x3 -> drive interrupt high -#define IO_BANK0_GPIO21_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO21_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO21_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO21_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO21_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO21_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO21_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO21_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO21_CTRL_IRQOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO21_CTRL_INOVER -// 0x0 -> don't invert the peri input -// 0x1 -> invert the peri input -// 0x2 -> drive peri input low -// 0x3 -> drive peri input high -#define IO_BANK0_GPIO21_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO21_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO21_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO21_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO21_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO21_CTRL_INOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO21_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO21_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO21_CTRL_INOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO21_CTRL_OEOVER -// 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel -// 0x2 -> disable output -// 0x3 -> enable output -#define IO_BANK0_GPIO21_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO21_CTRL_OEOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO21_CTRL_OEOVER_MSB _u(13) -#define IO_BANK0_GPIO21_CTRL_OEOVER_LSB _u(12) -#define IO_BANK0_GPIO21_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO21_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO21_CTRL_OEOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO21_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO21_CTRL_OEOVER_VALUE_ENABLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO21_CTRL_OUTOVER -// 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel -// 0x2 -> drive output low -// 0x3 -> drive output high -#define IO_BANK0_GPIO21_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO21_CTRL_OUTOVER_BITS _u(0x00000300) -#define IO_BANK0_GPIO21_CTRL_OUTOVER_MSB _u(9) -#define IO_BANK0_GPIO21_CTRL_OUTOVER_LSB _u(8) -#define IO_BANK0_GPIO21_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO21_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO21_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO21_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO21_CTRL_OUTOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO21_CTRL_FUNCSEL -// Description : 0-31 -> selects pin function according to the gpio table -// 31 == NULL -// 0x01 -> spi0_ss_n -// 0x02 -> uart1_rx -// 0x03 -> i2c0_scl -// 0x04 -> pwm_b_2 -// 0x05 -> sio_21 -// 0x06 -> pio0_21 -// 0x07 -> pio1_21 -// 0x08 -> clocks_gpout_0 -// 0x09 -> usb_muxing_overcurr_detect -// 0x1f -> null -#define IO_BANK0_GPIO21_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO21_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO21_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO21_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO21_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_SPI0_SS_N _u(0x01) -#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_UART1_RX _u(0x02) -#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03) -#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_PWM_B_2 _u(0x04) -#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_SIO_21 _u(0x05) -#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_PIO0_21 _u(0x06) -#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_PIO1_21 _u(0x07) -#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_CLOCKS_GPOUT_0 _u(0x08) -#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x09) -#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) -// ============================================================================= -// Register : IO_BANK0_GPIO22_STATUS -// Description : GPIO status -#define IO_BANK0_GPIO22_STATUS_OFFSET _u(0x000000b0) -#define IO_BANK0_GPIO22_STATUS_BITS _u(0x050a3300) -#define IO_BANK0_GPIO22_STATUS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO22_STATUS_IRQTOPROC -// Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO22_STATUS_IRQTOPROC_RESET _u(0x0) -#define IO_BANK0_GPIO22_STATUS_IRQTOPROC_BITS _u(0x04000000) -#define IO_BANK0_GPIO22_STATUS_IRQTOPROC_MSB _u(26) -#define IO_BANK0_GPIO22_STATUS_IRQTOPROC_LSB _u(26) -#define IO_BANK0_GPIO22_STATUS_IRQTOPROC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO22_STATUS_IRQFROMPAD -// Description : interrupt from pad before override is applied -#define IO_BANK0_GPIO22_STATUS_IRQFROMPAD_RESET _u(0x0) -#define IO_BANK0_GPIO22_STATUS_IRQFROMPAD_BITS _u(0x01000000) -#define IO_BANK0_GPIO22_STATUS_IRQFROMPAD_MSB _u(24) -#define IO_BANK0_GPIO22_STATUS_IRQFROMPAD_LSB _u(24) -#define IO_BANK0_GPIO22_STATUS_IRQFROMPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO22_STATUS_INTOPERI -// Description : input signal to peripheral, after override is applied -#define IO_BANK0_GPIO22_STATUS_INTOPERI_RESET _u(0x0) -#define IO_BANK0_GPIO22_STATUS_INTOPERI_BITS _u(0x00080000) -#define IO_BANK0_GPIO22_STATUS_INTOPERI_MSB _u(19) -#define IO_BANK0_GPIO22_STATUS_INTOPERI_LSB _u(19) -#define IO_BANK0_GPIO22_STATUS_INTOPERI_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO22_STATUS_INFROMPAD -// Description : input signal from pad, before override is applied -#define IO_BANK0_GPIO22_STATUS_INFROMPAD_RESET _u(0x0) -#define IO_BANK0_GPIO22_STATUS_INFROMPAD_BITS _u(0x00020000) -#define IO_BANK0_GPIO22_STATUS_INFROMPAD_MSB _u(17) -#define IO_BANK0_GPIO22_STATUS_INFROMPAD_LSB _u(17) -#define IO_BANK0_GPIO22_STATUS_INFROMPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO22_STATUS_OETOPAD -// Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO22_STATUS_OETOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO22_STATUS_OETOPAD_BITS _u(0x00002000) -#define IO_BANK0_GPIO22_STATUS_OETOPAD_MSB _u(13) -#define IO_BANK0_GPIO22_STATUS_OETOPAD_LSB _u(13) -#define IO_BANK0_GPIO22_STATUS_OETOPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO22_STATUS_OEFROMPERI -// Description : output enable from selected peripheral, before register -// override is applied -#define IO_BANK0_GPIO22_STATUS_OEFROMPERI_RESET _u(0x0) -#define IO_BANK0_GPIO22_STATUS_OEFROMPERI_BITS _u(0x00001000) -#define IO_BANK0_GPIO22_STATUS_OEFROMPERI_MSB _u(12) -#define IO_BANK0_GPIO22_STATUS_OEFROMPERI_LSB _u(12) -#define IO_BANK0_GPIO22_STATUS_OEFROMPERI_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO22_STATUS_OUTTOPAD -// Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO22_STATUS_OUTTOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO22_STATUS_OUTTOPAD_BITS _u(0x00000200) -#define IO_BANK0_GPIO22_STATUS_OUTTOPAD_MSB _u(9) -#define IO_BANK0_GPIO22_STATUS_OUTTOPAD_LSB _u(9) -#define IO_BANK0_GPIO22_STATUS_OUTTOPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO22_STATUS_OUTFROMPERI -// Description : output signal from selected peripheral, before register -// override is applied -#define IO_BANK0_GPIO22_STATUS_OUTFROMPERI_RESET _u(0x0) -#define IO_BANK0_GPIO22_STATUS_OUTFROMPERI_BITS _u(0x00000100) -#define IO_BANK0_GPIO22_STATUS_OUTFROMPERI_MSB _u(8) -#define IO_BANK0_GPIO22_STATUS_OUTFROMPERI_LSB _u(8) -#define IO_BANK0_GPIO22_STATUS_OUTFROMPERI_ACCESS "RO" -// ============================================================================= -// Register : IO_BANK0_GPIO22_CTRL -// Description : GPIO control including function select and overrides. -#define IO_BANK0_GPIO22_CTRL_OFFSET _u(0x000000b4) -#define IO_BANK0_GPIO22_CTRL_BITS _u(0x3003331f) -#define IO_BANK0_GPIO22_CTRL_RESET _u(0x0000001f) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO22_CTRL_IRQOVER -// 0x0 -> don't invert the interrupt -// 0x1 -> invert the interrupt -// 0x2 -> drive interrupt low -// 0x3 -> drive interrupt high -#define IO_BANK0_GPIO22_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO22_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO22_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO22_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO22_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO22_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO22_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO22_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO22_CTRL_IRQOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO22_CTRL_INOVER -// 0x0 -> don't invert the peri input -// 0x1 -> invert the peri input -// 0x2 -> drive peri input low -// 0x3 -> drive peri input high -#define IO_BANK0_GPIO22_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO22_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO22_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO22_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO22_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO22_CTRL_INOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO22_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO22_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO22_CTRL_INOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO22_CTRL_OEOVER -// 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel -// 0x2 -> disable output -// 0x3 -> enable output -#define IO_BANK0_GPIO22_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO22_CTRL_OEOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO22_CTRL_OEOVER_MSB _u(13) -#define IO_BANK0_GPIO22_CTRL_OEOVER_LSB _u(12) -#define IO_BANK0_GPIO22_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO22_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO22_CTRL_OEOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO22_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO22_CTRL_OEOVER_VALUE_ENABLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO22_CTRL_OUTOVER -// 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel -// 0x2 -> drive output low -// 0x3 -> drive output high -#define IO_BANK0_GPIO22_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO22_CTRL_OUTOVER_BITS _u(0x00000300) -#define IO_BANK0_GPIO22_CTRL_OUTOVER_MSB _u(9) -#define IO_BANK0_GPIO22_CTRL_OUTOVER_LSB _u(8) -#define IO_BANK0_GPIO22_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO22_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO22_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO22_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO22_CTRL_OUTOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO22_CTRL_FUNCSEL -// Description : 0-31 -> selects pin function according to the gpio table -// 31 == NULL -// 0x01 -> spi0_sclk -// 0x02 -> uart1_cts -// 0x03 -> i2c1_sda -// 0x04 -> pwm_a_3 -// 0x05 -> sio_22 -// 0x06 -> pio0_22 -// 0x07 -> pio1_22 -// 0x08 -> clocks_gpin_1 -// 0x09 -> usb_muxing_vbus_detect -// 0x1f -> null -#define IO_BANK0_GPIO22_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO22_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO22_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO22_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO22_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_SPI0_SCLK _u(0x01) -#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_UART1_CTS _u(0x02) -#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03) -#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_PWM_A_3 _u(0x04) -#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_SIO_22 _u(0x05) -#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_PIO0_22 _u(0x06) -#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_PIO1_22 _u(0x07) -#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_CLOCKS_GPIN_1 _u(0x08) -#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x09) -#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) -// ============================================================================= -// Register : IO_BANK0_GPIO23_STATUS -// Description : GPIO status -#define IO_BANK0_GPIO23_STATUS_OFFSET _u(0x000000b8) -#define IO_BANK0_GPIO23_STATUS_BITS _u(0x050a3300) -#define IO_BANK0_GPIO23_STATUS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO23_STATUS_IRQTOPROC -// Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO23_STATUS_IRQTOPROC_RESET _u(0x0) -#define IO_BANK0_GPIO23_STATUS_IRQTOPROC_BITS _u(0x04000000) -#define IO_BANK0_GPIO23_STATUS_IRQTOPROC_MSB _u(26) -#define IO_BANK0_GPIO23_STATUS_IRQTOPROC_LSB _u(26) -#define IO_BANK0_GPIO23_STATUS_IRQTOPROC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO23_STATUS_IRQFROMPAD -// Description : interrupt from pad before override is applied -#define IO_BANK0_GPIO23_STATUS_IRQFROMPAD_RESET _u(0x0) -#define IO_BANK0_GPIO23_STATUS_IRQFROMPAD_BITS _u(0x01000000) -#define IO_BANK0_GPIO23_STATUS_IRQFROMPAD_MSB _u(24) -#define IO_BANK0_GPIO23_STATUS_IRQFROMPAD_LSB _u(24) -#define IO_BANK0_GPIO23_STATUS_IRQFROMPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO23_STATUS_INTOPERI -// Description : input signal to peripheral, after override is applied -#define IO_BANK0_GPIO23_STATUS_INTOPERI_RESET _u(0x0) -#define IO_BANK0_GPIO23_STATUS_INTOPERI_BITS _u(0x00080000) -#define IO_BANK0_GPIO23_STATUS_INTOPERI_MSB _u(19) -#define IO_BANK0_GPIO23_STATUS_INTOPERI_LSB _u(19) -#define IO_BANK0_GPIO23_STATUS_INTOPERI_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO23_STATUS_INFROMPAD -// Description : input signal from pad, before override is applied -#define IO_BANK0_GPIO23_STATUS_INFROMPAD_RESET _u(0x0) -#define IO_BANK0_GPIO23_STATUS_INFROMPAD_BITS _u(0x00020000) -#define IO_BANK0_GPIO23_STATUS_INFROMPAD_MSB _u(17) -#define IO_BANK0_GPIO23_STATUS_INFROMPAD_LSB _u(17) -#define IO_BANK0_GPIO23_STATUS_INFROMPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO23_STATUS_OETOPAD -// Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO23_STATUS_OETOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO23_STATUS_OETOPAD_BITS _u(0x00002000) -#define IO_BANK0_GPIO23_STATUS_OETOPAD_MSB _u(13) -#define IO_BANK0_GPIO23_STATUS_OETOPAD_LSB _u(13) -#define IO_BANK0_GPIO23_STATUS_OETOPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO23_STATUS_OEFROMPERI -// Description : output enable from selected peripheral, before register -// override is applied -#define IO_BANK0_GPIO23_STATUS_OEFROMPERI_RESET _u(0x0) -#define IO_BANK0_GPIO23_STATUS_OEFROMPERI_BITS _u(0x00001000) -#define IO_BANK0_GPIO23_STATUS_OEFROMPERI_MSB _u(12) -#define IO_BANK0_GPIO23_STATUS_OEFROMPERI_LSB _u(12) -#define IO_BANK0_GPIO23_STATUS_OEFROMPERI_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO23_STATUS_OUTTOPAD -// Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO23_STATUS_OUTTOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO23_STATUS_OUTTOPAD_BITS _u(0x00000200) -#define IO_BANK0_GPIO23_STATUS_OUTTOPAD_MSB _u(9) -#define IO_BANK0_GPIO23_STATUS_OUTTOPAD_LSB _u(9) -#define IO_BANK0_GPIO23_STATUS_OUTTOPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO23_STATUS_OUTFROMPERI -// Description : output signal from selected peripheral, before register -// override is applied -#define IO_BANK0_GPIO23_STATUS_OUTFROMPERI_RESET _u(0x0) -#define IO_BANK0_GPIO23_STATUS_OUTFROMPERI_BITS _u(0x00000100) -#define IO_BANK0_GPIO23_STATUS_OUTFROMPERI_MSB _u(8) -#define IO_BANK0_GPIO23_STATUS_OUTFROMPERI_LSB _u(8) -#define IO_BANK0_GPIO23_STATUS_OUTFROMPERI_ACCESS "RO" -// ============================================================================= -// Register : IO_BANK0_GPIO23_CTRL -// Description : GPIO control including function select and overrides. -#define IO_BANK0_GPIO23_CTRL_OFFSET _u(0x000000bc) -#define IO_BANK0_GPIO23_CTRL_BITS _u(0x3003331f) -#define IO_BANK0_GPIO23_CTRL_RESET _u(0x0000001f) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO23_CTRL_IRQOVER -// 0x0 -> don't invert the interrupt -// 0x1 -> invert the interrupt -// 0x2 -> drive interrupt low -// 0x3 -> drive interrupt high -#define IO_BANK0_GPIO23_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO23_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO23_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO23_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO23_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO23_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO23_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO23_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO23_CTRL_IRQOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO23_CTRL_INOVER -// 0x0 -> don't invert the peri input -// 0x1 -> invert the peri input -// 0x2 -> drive peri input low -// 0x3 -> drive peri input high -#define IO_BANK0_GPIO23_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO23_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO23_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO23_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO23_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO23_CTRL_INOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO23_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO23_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO23_CTRL_INOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO23_CTRL_OEOVER -// 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel -// 0x2 -> disable output -// 0x3 -> enable output -#define IO_BANK0_GPIO23_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO23_CTRL_OEOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO23_CTRL_OEOVER_MSB _u(13) -#define IO_BANK0_GPIO23_CTRL_OEOVER_LSB _u(12) -#define IO_BANK0_GPIO23_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO23_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO23_CTRL_OEOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO23_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO23_CTRL_OEOVER_VALUE_ENABLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO23_CTRL_OUTOVER -// 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel -// 0x2 -> drive output low -// 0x3 -> drive output high -#define IO_BANK0_GPIO23_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO23_CTRL_OUTOVER_BITS _u(0x00000300) -#define IO_BANK0_GPIO23_CTRL_OUTOVER_MSB _u(9) -#define IO_BANK0_GPIO23_CTRL_OUTOVER_LSB _u(8) -#define IO_BANK0_GPIO23_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO23_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO23_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO23_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO23_CTRL_OUTOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO23_CTRL_FUNCSEL -// Description : 0-31 -> selects pin function according to the gpio table -// 31 == NULL -// 0x01 -> spi0_tx -// 0x02 -> uart1_rts -// 0x03 -> i2c1_scl -// 0x04 -> pwm_b_3 -// 0x05 -> sio_23 -// 0x06 -> pio0_23 -// 0x07 -> pio1_23 -// 0x08 -> clocks_gpout_1 -// 0x09 -> usb_muxing_vbus_en -// 0x1f -> null -#define IO_BANK0_GPIO23_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO23_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO23_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO23_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO23_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_SPI0_TX _u(0x01) -#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_UART1_RTS _u(0x02) -#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03) -#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_PWM_B_3 _u(0x04) -#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_SIO_23 _u(0x05) -#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_PIO0_23 _u(0x06) -#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_PIO1_23 _u(0x07) -#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_CLOCKS_GPOUT_1 _u(0x08) -#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x09) -#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) -// ============================================================================= -// Register : IO_BANK0_GPIO24_STATUS -// Description : GPIO status -#define IO_BANK0_GPIO24_STATUS_OFFSET _u(0x000000c0) -#define IO_BANK0_GPIO24_STATUS_BITS _u(0x050a3300) -#define IO_BANK0_GPIO24_STATUS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO24_STATUS_IRQTOPROC -// Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO24_STATUS_IRQTOPROC_RESET _u(0x0) -#define IO_BANK0_GPIO24_STATUS_IRQTOPROC_BITS _u(0x04000000) -#define IO_BANK0_GPIO24_STATUS_IRQTOPROC_MSB _u(26) -#define IO_BANK0_GPIO24_STATUS_IRQTOPROC_LSB _u(26) -#define IO_BANK0_GPIO24_STATUS_IRQTOPROC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO24_STATUS_IRQFROMPAD -// Description : interrupt from pad before override is applied -#define IO_BANK0_GPIO24_STATUS_IRQFROMPAD_RESET _u(0x0) -#define IO_BANK0_GPIO24_STATUS_IRQFROMPAD_BITS _u(0x01000000) -#define IO_BANK0_GPIO24_STATUS_IRQFROMPAD_MSB _u(24) -#define IO_BANK0_GPIO24_STATUS_IRQFROMPAD_LSB _u(24) -#define IO_BANK0_GPIO24_STATUS_IRQFROMPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO24_STATUS_INTOPERI -// Description : input signal to peripheral, after override is applied -#define IO_BANK0_GPIO24_STATUS_INTOPERI_RESET _u(0x0) -#define IO_BANK0_GPIO24_STATUS_INTOPERI_BITS _u(0x00080000) -#define IO_BANK0_GPIO24_STATUS_INTOPERI_MSB _u(19) -#define IO_BANK0_GPIO24_STATUS_INTOPERI_LSB _u(19) -#define IO_BANK0_GPIO24_STATUS_INTOPERI_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO24_STATUS_INFROMPAD -// Description : input signal from pad, before override is applied -#define IO_BANK0_GPIO24_STATUS_INFROMPAD_RESET _u(0x0) -#define IO_BANK0_GPIO24_STATUS_INFROMPAD_BITS _u(0x00020000) -#define IO_BANK0_GPIO24_STATUS_INFROMPAD_MSB _u(17) -#define IO_BANK0_GPIO24_STATUS_INFROMPAD_LSB _u(17) -#define IO_BANK0_GPIO24_STATUS_INFROMPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO24_STATUS_OETOPAD -// Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO24_STATUS_OETOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO24_STATUS_OETOPAD_BITS _u(0x00002000) -#define IO_BANK0_GPIO24_STATUS_OETOPAD_MSB _u(13) -#define IO_BANK0_GPIO24_STATUS_OETOPAD_LSB _u(13) -#define IO_BANK0_GPIO24_STATUS_OETOPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO24_STATUS_OEFROMPERI -// Description : output enable from selected peripheral, before register -// override is applied -#define IO_BANK0_GPIO24_STATUS_OEFROMPERI_RESET _u(0x0) -#define IO_BANK0_GPIO24_STATUS_OEFROMPERI_BITS _u(0x00001000) -#define IO_BANK0_GPIO24_STATUS_OEFROMPERI_MSB _u(12) -#define IO_BANK0_GPIO24_STATUS_OEFROMPERI_LSB _u(12) -#define IO_BANK0_GPIO24_STATUS_OEFROMPERI_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO24_STATUS_OUTTOPAD -// Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO24_STATUS_OUTTOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO24_STATUS_OUTTOPAD_BITS _u(0x00000200) -#define IO_BANK0_GPIO24_STATUS_OUTTOPAD_MSB _u(9) -#define IO_BANK0_GPIO24_STATUS_OUTTOPAD_LSB _u(9) -#define IO_BANK0_GPIO24_STATUS_OUTTOPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO24_STATUS_OUTFROMPERI -// Description : output signal from selected peripheral, before register -// override is applied -#define IO_BANK0_GPIO24_STATUS_OUTFROMPERI_RESET _u(0x0) -#define IO_BANK0_GPIO24_STATUS_OUTFROMPERI_BITS _u(0x00000100) -#define IO_BANK0_GPIO24_STATUS_OUTFROMPERI_MSB _u(8) -#define IO_BANK0_GPIO24_STATUS_OUTFROMPERI_LSB _u(8) -#define IO_BANK0_GPIO24_STATUS_OUTFROMPERI_ACCESS "RO" -// ============================================================================= -// Register : IO_BANK0_GPIO24_CTRL -// Description : GPIO control including function select and overrides. -#define IO_BANK0_GPIO24_CTRL_OFFSET _u(0x000000c4) -#define IO_BANK0_GPIO24_CTRL_BITS _u(0x3003331f) -#define IO_BANK0_GPIO24_CTRL_RESET _u(0x0000001f) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO24_CTRL_IRQOVER -// 0x0 -> don't invert the interrupt -// 0x1 -> invert the interrupt -// 0x2 -> drive interrupt low -// 0x3 -> drive interrupt high -#define IO_BANK0_GPIO24_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO24_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO24_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO24_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO24_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO24_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO24_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO24_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO24_CTRL_IRQOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO24_CTRL_INOVER -// 0x0 -> don't invert the peri input -// 0x1 -> invert the peri input -// 0x2 -> drive peri input low -// 0x3 -> drive peri input high -#define IO_BANK0_GPIO24_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO24_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO24_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO24_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO24_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO24_CTRL_INOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO24_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO24_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO24_CTRL_INOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO24_CTRL_OEOVER -// 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel -// 0x2 -> disable output -// 0x3 -> enable output -#define IO_BANK0_GPIO24_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO24_CTRL_OEOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO24_CTRL_OEOVER_MSB _u(13) -#define IO_BANK0_GPIO24_CTRL_OEOVER_LSB _u(12) -#define IO_BANK0_GPIO24_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO24_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO24_CTRL_OEOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO24_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO24_CTRL_OEOVER_VALUE_ENABLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO24_CTRL_OUTOVER -// 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel -// 0x2 -> drive output low -// 0x3 -> drive output high -#define IO_BANK0_GPIO24_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO24_CTRL_OUTOVER_BITS _u(0x00000300) -#define IO_BANK0_GPIO24_CTRL_OUTOVER_MSB _u(9) -#define IO_BANK0_GPIO24_CTRL_OUTOVER_LSB _u(8) -#define IO_BANK0_GPIO24_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO24_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO24_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO24_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO24_CTRL_OUTOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO24_CTRL_FUNCSEL -// Description : 0-31 -> selects pin function according to the gpio table -// 31 == NULL -// 0x01 -> spi1_rx -// 0x02 -> uart1_tx -// 0x03 -> i2c0_sda -// 0x04 -> pwm_a_4 -// 0x05 -> sio_24 -// 0x06 -> pio0_24 -// 0x07 -> pio1_24 -// 0x08 -> clocks_gpout_2 -// 0x09 -> usb_muxing_overcurr_detect -// 0x1f -> null -#define IO_BANK0_GPIO24_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO24_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO24_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO24_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO24_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_SPI1_RX _u(0x01) -#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_UART1_TX _u(0x02) -#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03) -#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_PWM_A_4 _u(0x04) -#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_SIO_24 _u(0x05) -#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_PIO0_24 _u(0x06) -#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_PIO1_24 _u(0x07) -#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_CLOCKS_GPOUT_2 _u(0x08) -#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x09) -#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) -// ============================================================================= -// Register : IO_BANK0_GPIO25_STATUS -// Description : GPIO status -#define IO_BANK0_GPIO25_STATUS_OFFSET _u(0x000000c8) -#define IO_BANK0_GPIO25_STATUS_BITS _u(0x050a3300) -#define IO_BANK0_GPIO25_STATUS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO25_STATUS_IRQTOPROC -// Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO25_STATUS_IRQTOPROC_RESET _u(0x0) -#define IO_BANK0_GPIO25_STATUS_IRQTOPROC_BITS _u(0x04000000) -#define IO_BANK0_GPIO25_STATUS_IRQTOPROC_MSB _u(26) -#define IO_BANK0_GPIO25_STATUS_IRQTOPROC_LSB _u(26) -#define IO_BANK0_GPIO25_STATUS_IRQTOPROC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO25_STATUS_IRQFROMPAD -// Description : interrupt from pad before override is applied -#define IO_BANK0_GPIO25_STATUS_IRQFROMPAD_RESET _u(0x0) -#define IO_BANK0_GPIO25_STATUS_IRQFROMPAD_BITS _u(0x01000000) -#define IO_BANK0_GPIO25_STATUS_IRQFROMPAD_MSB _u(24) -#define IO_BANK0_GPIO25_STATUS_IRQFROMPAD_LSB _u(24) -#define IO_BANK0_GPIO25_STATUS_IRQFROMPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO25_STATUS_INTOPERI -// Description : input signal to peripheral, after override is applied -#define IO_BANK0_GPIO25_STATUS_INTOPERI_RESET _u(0x0) -#define IO_BANK0_GPIO25_STATUS_INTOPERI_BITS _u(0x00080000) -#define IO_BANK0_GPIO25_STATUS_INTOPERI_MSB _u(19) -#define IO_BANK0_GPIO25_STATUS_INTOPERI_LSB _u(19) -#define IO_BANK0_GPIO25_STATUS_INTOPERI_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO25_STATUS_INFROMPAD -// Description : input signal from pad, before override is applied -#define IO_BANK0_GPIO25_STATUS_INFROMPAD_RESET _u(0x0) -#define IO_BANK0_GPIO25_STATUS_INFROMPAD_BITS _u(0x00020000) -#define IO_BANK0_GPIO25_STATUS_INFROMPAD_MSB _u(17) -#define IO_BANK0_GPIO25_STATUS_INFROMPAD_LSB _u(17) -#define IO_BANK0_GPIO25_STATUS_INFROMPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO25_STATUS_OETOPAD -// Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO25_STATUS_OETOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO25_STATUS_OETOPAD_BITS _u(0x00002000) -#define IO_BANK0_GPIO25_STATUS_OETOPAD_MSB _u(13) -#define IO_BANK0_GPIO25_STATUS_OETOPAD_LSB _u(13) -#define IO_BANK0_GPIO25_STATUS_OETOPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO25_STATUS_OEFROMPERI -// Description : output enable from selected peripheral, before register -// override is applied -#define IO_BANK0_GPIO25_STATUS_OEFROMPERI_RESET _u(0x0) -#define IO_BANK0_GPIO25_STATUS_OEFROMPERI_BITS _u(0x00001000) -#define IO_BANK0_GPIO25_STATUS_OEFROMPERI_MSB _u(12) -#define IO_BANK0_GPIO25_STATUS_OEFROMPERI_LSB _u(12) -#define IO_BANK0_GPIO25_STATUS_OEFROMPERI_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO25_STATUS_OUTTOPAD -// Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO25_STATUS_OUTTOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO25_STATUS_OUTTOPAD_BITS _u(0x00000200) -#define IO_BANK0_GPIO25_STATUS_OUTTOPAD_MSB _u(9) -#define IO_BANK0_GPIO25_STATUS_OUTTOPAD_LSB _u(9) -#define IO_BANK0_GPIO25_STATUS_OUTTOPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO25_STATUS_OUTFROMPERI -// Description : output signal from selected peripheral, before register -// override is applied -#define IO_BANK0_GPIO25_STATUS_OUTFROMPERI_RESET _u(0x0) -#define IO_BANK0_GPIO25_STATUS_OUTFROMPERI_BITS _u(0x00000100) -#define IO_BANK0_GPIO25_STATUS_OUTFROMPERI_MSB _u(8) -#define IO_BANK0_GPIO25_STATUS_OUTFROMPERI_LSB _u(8) -#define IO_BANK0_GPIO25_STATUS_OUTFROMPERI_ACCESS "RO" -// ============================================================================= -// Register : IO_BANK0_GPIO25_CTRL -// Description : GPIO control including function select and overrides. -#define IO_BANK0_GPIO25_CTRL_OFFSET _u(0x000000cc) -#define IO_BANK0_GPIO25_CTRL_BITS _u(0x3003331f) -#define IO_BANK0_GPIO25_CTRL_RESET _u(0x0000001f) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO25_CTRL_IRQOVER -// 0x0 -> don't invert the interrupt -// 0x1 -> invert the interrupt -// 0x2 -> drive interrupt low -// 0x3 -> drive interrupt high -#define IO_BANK0_GPIO25_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO25_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO25_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO25_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO25_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO25_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO25_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO25_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO25_CTRL_IRQOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO25_CTRL_INOVER -// 0x0 -> don't invert the peri input -// 0x1 -> invert the peri input -// 0x2 -> drive peri input low -// 0x3 -> drive peri input high -#define IO_BANK0_GPIO25_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO25_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO25_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO25_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO25_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO25_CTRL_INOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO25_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO25_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO25_CTRL_INOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO25_CTRL_OEOVER -// 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel -// 0x2 -> disable output -// 0x3 -> enable output -#define IO_BANK0_GPIO25_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO25_CTRL_OEOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO25_CTRL_OEOVER_MSB _u(13) -#define IO_BANK0_GPIO25_CTRL_OEOVER_LSB _u(12) -#define IO_BANK0_GPIO25_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO25_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO25_CTRL_OEOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO25_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO25_CTRL_OEOVER_VALUE_ENABLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO25_CTRL_OUTOVER -// 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel -// 0x2 -> drive output low -// 0x3 -> drive output high -#define IO_BANK0_GPIO25_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO25_CTRL_OUTOVER_BITS _u(0x00000300) -#define IO_BANK0_GPIO25_CTRL_OUTOVER_MSB _u(9) -#define IO_BANK0_GPIO25_CTRL_OUTOVER_LSB _u(8) -#define IO_BANK0_GPIO25_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO25_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO25_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO25_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO25_CTRL_OUTOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO25_CTRL_FUNCSEL -// Description : 0-31 -> selects pin function according to the gpio table -// 31 == NULL -// 0x01 -> spi1_ss_n -// 0x02 -> uart1_rx -// 0x03 -> i2c0_scl -// 0x04 -> pwm_b_4 -// 0x05 -> sio_25 -// 0x06 -> pio0_25 -// 0x07 -> pio1_25 -// 0x08 -> clocks_gpout_3 -// 0x09 -> usb_muxing_vbus_detect -// 0x1f -> null -#define IO_BANK0_GPIO25_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO25_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO25_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO25_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO25_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_SPI1_SS_N _u(0x01) -#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_UART1_RX _u(0x02) -#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03) -#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_PWM_B_4 _u(0x04) -#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_SIO_25 _u(0x05) -#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_PIO0_25 _u(0x06) -#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_PIO1_25 _u(0x07) -#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_CLOCKS_GPOUT_3 _u(0x08) -#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x09) -#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) -// ============================================================================= -// Register : IO_BANK0_GPIO26_STATUS -// Description : GPIO status -#define IO_BANK0_GPIO26_STATUS_OFFSET _u(0x000000d0) -#define IO_BANK0_GPIO26_STATUS_BITS _u(0x050a3300) -#define IO_BANK0_GPIO26_STATUS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO26_STATUS_IRQTOPROC -// Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO26_STATUS_IRQTOPROC_RESET _u(0x0) -#define IO_BANK0_GPIO26_STATUS_IRQTOPROC_BITS _u(0x04000000) -#define IO_BANK0_GPIO26_STATUS_IRQTOPROC_MSB _u(26) -#define IO_BANK0_GPIO26_STATUS_IRQTOPROC_LSB _u(26) -#define IO_BANK0_GPIO26_STATUS_IRQTOPROC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO26_STATUS_IRQFROMPAD -// Description : interrupt from pad before override is applied -#define IO_BANK0_GPIO26_STATUS_IRQFROMPAD_RESET _u(0x0) -#define IO_BANK0_GPIO26_STATUS_IRQFROMPAD_BITS _u(0x01000000) -#define IO_BANK0_GPIO26_STATUS_IRQFROMPAD_MSB _u(24) -#define IO_BANK0_GPIO26_STATUS_IRQFROMPAD_LSB _u(24) -#define IO_BANK0_GPIO26_STATUS_IRQFROMPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO26_STATUS_INTOPERI -// Description : input signal to peripheral, after override is applied -#define IO_BANK0_GPIO26_STATUS_INTOPERI_RESET _u(0x0) -#define IO_BANK0_GPIO26_STATUS_INTOPERI_BITS _u(0x00080000) -#define IO_BANK0_GPIO26_STATUS_INTOPERI_MSB _u(19) -#define IO_BANK0_GPIO26_STATUS_INTOPERI_LSB _u(19) -#define IO_BANK0_GPIO26_STATUS_INTOPERI_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO26_STATUS_INFROMPAD -// Description : input signal from pad, before override is applied -#define IO_BANK0_GPIO26_STATUS_INFROMPAD_RESET _u(0x0) -#define IO_BANK0_GPIO26_STATUS_INFROMPAD_BITS _u(0x00020000) -#define IO_BANK0_GPIO26_STATUS_INFROMPAD_MSB _u(17) -#define IO_BANK0_GPIO26_STATUS_INFROMPAD_LSB _u(17) -#define IO_BANK0_GPIO26_STATUS_INFROMPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO26_STATUS_OETOPAD -// Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO26_STATUS_OETOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO26_STATUS_OETOPAD_BITS _u(0x00002000) -#define IO_BANK0_GPIO26_STATUS_OETOPAD_MSB _u(13) -#define IO_BANK0_GPIO26_STATUS_OETOPAD_LSB _u(13) -#define IO_BANK0_GPIO26_STATUS_OETOPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO26_STATUS_OEFROMPERI -// Description : output enable from selected peripheral, before register -// override is applied -#define IO_BANK0_GPIO26_STATUS_OEFROMPERI_RESET _u(0x0) -#define IO_BANK0_GPIO26_STATUS_OEFROMPERI_BITS _u(0x00001000) -#define IO_BANK0_GPIO26_STATUS_OEFROMPERI_MSB _u(12) -#define IO_BANK0_GPIO26_STATUS_OEFROMPERI_LSB _u(12) -#define IO_BANK0_GPIO26_STATUS_OEFROMPERI_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO26_STATUS_OUTTOPAD -// Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO26_STATUS_OUTTOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO26_STATUS_OUTTOPAD_BITS _u(0x00000200) -#define IO_BANK0_GPIO26_STATUS_OUTTOPAD_MSB _u(9) -#define IO_BANK0_GPIO26_STATUS_OUTTOPAD_LSB _u(9) -#define IO_BANK0_GPIO26_STATUS_OUTTOPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO26_STATUS_OUTFROMPERI -// Description : output signal from selected peripheral, before register -// override is applied -#define IO_BANK0_GPIO26_STATUS_OUTFROMPERI_RESET _u(0x0) -#define IO_BANK0_GPIO26_STATUS_OUTFROMPERI_BITS _u(0x00000100) -#define IO_BANK0_GPIO26_STATUS_OUTFROMPERI_MSB _u(8) -#define IO_BANK0_GPIO26_STATUS_OUTFROMPERI_LSB _u(8) -#define IO_BANK0_GPIO26_STATUS_OUTFROMPERI_ACCESS "RO" -// ============================================================================= -// Register : IO_BANK0_GPIO26_CTRL -// Description : GPIO control including function select and overrides. -#define IO_BANK0_GPIO26_CTRL_OFFSET _u(0x000000d4) -#define IO_BANK0_GPIO26_CTRL_BITS _u(0x3003331f) -#define IO_BANK0_GPIO26_CTRL_RESET _u(0x0000001f) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO26_CTRL_IRQOVER -// 0x0 -> don't invert the interrupt -// 0x1 -> invert the interrupt -// 0x2 -> drive interrupt low -// 0x3 -> drive interrupt high -#define IO_BANK0_GPIO26_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO26_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO26_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO26_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO26_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO26_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO26_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO26_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO26_CTRL_IRQOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO26_CTRL_INOVER -// 0x0 -> don't invert the peri input -// 0x1 -> invert the peri input -// 0x2 -> drive peri input low -// 0x3 -> drive peri input high -#define IO_BANK0_GPIO26_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO26_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO26_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO26_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO26_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO26_CTRL_INOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO26_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO26_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO26_CTRL_INOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO26_CTRL_OEOVER -// 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel -// 0x2 -> disable output -// 0x3 -> enable output -#define IO_BANK0_GPIO26_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO26_CTRL_OEOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO26_CTRL_OEOVER_MSB _u(13) -#define IO_BANK0_GPIO26_CTRL_OEOVER_LSB _u(12) -#define IO_BANK0_GPIO26_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO26_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO26_CTRL_OEOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO26_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO26_CTRL_OEOVER_VALUE_ENABLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO26_CTRL_OUTOVER -// 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel -// 0x2 -> drive output low -// 0x3 -> drive output high -#define IO_BANK0_GPIO26_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO26_CTRL_OUTOVER_BITS _u(0x00000300) -#define IO_BANK0_GPIO26_CTRL_OUTOVER_MSB _u(9) -#define IO_BANK0_GPIO26_CTRL_OUTOVER_LSB _u(8) -#define IO_BANK0_GPIO26_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO26_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO26_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO26_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO26_CTRL_OUTOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO26_CTRL_FUNCSEL -// Description : 0-31 -> selects pin function according to the gpio table -// 31 == NULL -// 0x01 -> spi1_sclk -// 0x02 -> uart1_cts -// 0x03 -> i2c1_sda -// 0x04 -> pwm_a_5 -// 0x05 -> sio_26 -// 0x06 -> pio0_26 -// 0x07 -> pio1_26 -// 0x09 -> usb_muxing_vbus_en -// 0x1f -> null -#define IO_BANK0_GPIO26_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO26_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO26_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO26_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO26_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_SPI1_SCLK _u(0x01) -#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_UART1_CTS _u(0x02) -#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03) -#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_PWM_A_5 _u(0x04) -#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_SIO_26 _u(0x05) -#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_PIO0_26 _u(0x06) -#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_PIO1_26 _u(0x07) -#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x09) -#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) -// ============================================================================= -// Register : IO_BANK0_GPIO27_STATUS -// Description : GPIO status -#define IO_BANK0_GPIO27_STATUS_OFFSET _u(0x000000d8) -#define IO_BANK0_GPIO27_STATUS_BITS _u(0x050a3300) -#define IO_BANK0_GPIO27_STATUS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO27_STATUS_IRQTOPROC -// Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO27_STATUS_IRQTOPROC_RESET _u(0x0) -#define IO_BANK0_GPIO27_STATUS_IRQTOPROC_BITS _u(0x04000000) -#define IO_BANK0_GPIO27_STATUS_IRQTOPROC_MSB _u(26) -#define IO_BANK0_GPIO27_STATUS_IRQTOPROC_LSB _u(26) -#define IO_BANK0_GPIO27_STATUS_IRQTOPROC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO27_STATUS_IRQFROMPAD -// Description : interrupt from pad before override is applied -#define IO_BANK0_GPIO27_STATUS_IRQFROMPAD_RESET _u(0x0) -#define IO_BANK0_GPIO27_STATUS_IRQFROMPAD_BITS _u(0x01000000) -#define IO_BANK0_GPIO27_STATUS_IRQFROMPAD_MSB _u(24) -#define IO_BANK0_GPIO27_STATUS_IRQFROMPAD_LSB _u(24) -#define IO_BANK0_GPIO27_STATUS_IRQFROMPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO27_STATUS_INTOPERI -// Description : input signal to peripheral, after override is applied -#define IO_BANK0_GPIO27_STATUS_INTOPERI_RESET _u(0x0) -#define IO_BANK0_GPIO27_STATUS_INTOPERI_BITS _u(0x00080000) -#define IO_BANK0_GPIO27_STATUS_INTOPERI_MSB _u(19) -#define IO_BANK0_GPIO27_STATUS_INTOPERI_LSB _u(19) -#define IO_BANK0_GPIO27_STATUS_INTOPERI_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO27_STATUS_INFROMPAD -// Description : input signal from pad, before override is applied -#define IO_BANK0_GPIO27_STATUS_INFROMPAD_RESET _u(0x0) -#define IO_BANK0_GPIO27_STATUS_INFROMPAD_BITS _u(0x00020000) -#define IO_BANK0_GPIO27_STATUS_INFROMPAD_MSB _u(17) -#define IO_BANK0_GPIO27_STATUS_INFROMPAD_LSB _u(17) -#define IO_BANK0_GPIO27_STATUS_INFROMPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO27_STATUS_OETOPAD -// Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO27_STATUS_OETOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO27_STATUS_OETOPAD_BITS _u(0x00002000) -#define IO_BANK0_GPIO27_STATUS_OETOPAD_MSB _u(13) -#define IO_BANK0_GPIO27_STATUS_OETOPAD_LSB _u(13) -#define IO_BANK0_GPIO27_STATUS_OETOPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO27_STATUS_OEFROMPERI -// Description : output enable from selected peripheral, before register -// override is applied -#define IO_BANK0_GPIO27_STATUS_OEFROMPERI_RESET _u(0x0) -#define IO_BANK0_GPIO27_STATUS_OEFROMPERI_BITS _u(0x00001000) -#define IO_BANK0_GPIO27_STATUS_OEFROMPERI_MSB _u(12) -#define IO_BANK0_GPIO27_STATUS_OEFROMPERI_LSB _u(12) -#define IO_BANK0_GPIO27_STATUS_OEFROMPERI_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO27_STATUS_OUTTOPAD -// Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO27_STATUS_OUTTOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO27_STATUS_OUTTOPAD_BITS _u(0x00000200) -#define IO_BANK0_GPIO27_STATUS_OUTTOPAD_MSB _u(9) -#define IO_BANK0_GPIO27_STATUS_OUTTOPAD_LSB _u(9) -#define IO_BANK0_GPIO27_STATUS_OUTTOPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO27_STATUS_OUTFROMPERI -// Description : output signal from selected peripheral, before register -// override is applied -#define IO_BANK0_GPIO27_STATUS_OUTFROMPERI_RESET _u(0x0) -#define IO_BANK0_GPIO27_STATUS_OUTFROMPERI_BITS _u(0x00000100) -#define IO_BANK0_GPIO27_STATUS_OUTFROMPERI_MSB _u(8) -#define IO_BANK0_GPIO27_STATUS_OUTFROMPERI_LSB _u(8) -#define IO_BANK0_GPIO27_STATUS_OUTFROMPERI_ACCESS "RO" -// ============================================================================= -// Register : IO_BANK0_GPIO27_CTRL -// Description : GPIO control including function select and overrides. -#define IO_BANK0_GPIO27_CTRL_OFFSET _u(0x000000dc) -#define IO_BANK0_GPIO27_CTRL_BITS _u(0x3003331f) -#define IO_BANK0_GPIO27_CTRL_RESET _u(0x0000001f) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO27_CTRL_IRQOVER -// 0x0 -> don't invert the interrupt -// 0x1 -> invert the interrupt -// 0x2 -> drive interrupt low -// 0x3 -> drive interrupt high -#define IO_BANK0_GPIO27_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO27_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO27_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO27_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO27_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO27_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO27_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO27_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO27_CTRL_IRQOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO27_CTRL_INOVER -// 0x0 -> don't invert the peri input -// 0x1 -> invert the peri input -// 0x2 -> drive peri input low -// 0x3 -> drive peri input high -#define IO_BANK0_GPIO27_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO27_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO27_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO27_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO27_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO27_CTRL_INOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO27_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO27_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO27_CTRL_INOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO27_CTRL_OEOVER -// 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel -// 0x2 -> disable output -// 0x3 -> enable output -#define IO_BANK0_GPIO27_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO27_CTRL_OEOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO27_CTRL_OEOVER_MSB _u(13) -#define IO_BANK0_GPIO27_CTRL_OEOVER_LSB _u(12) -#define IO_BANK0_GPIO27_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO27_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO27_CTRL_OEOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO27_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO27_CTRL_OEOVER_VALUE_ENABLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO27_CTRL_OUTOVER -// 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel -// 0x2 -> drive output low -// 0x3 -> drive output high -#define IO_BANK0_GPIO27_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO27_CTRL_OUTOVER_BITS _u(0x00000300) -#define IO_BANK0_GPIO27_CTRL_OUTOVER_MSB _u(9) -#define IO_BANK0_GPIO27_CTRL_OUTOVER_LSB _u(8) -#define IO_BANK0_GPIO27_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO27_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO27_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO27_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO27_CTRL_OUTOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO27_CTRL_FUNCSEL -// Description : 0-31 -> selects pin function according to the gpio table -// 31 == NULL -// 0x01 -> spi1_tx -// 0x02 -> uart1_rts -// 0x03 -> i2c1_scl -// 0x04 -> pwm_b_5 -// 0x05 -> sio_27 -// 0x06 -> pio0_27 -// 0x07 -> pio1_27 -// 0x09 -> usb_muxing_overcurr_detect -// 0x1f -> null -#define IO_BANK0_GPIO27_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO27_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO27_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO27_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO27_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_SPI1_TX _u(0x01) -#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_UART1_RTS _u(0x02) -#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03) -#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_PWM_B_5 _u(0x04) -#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_SIO_27 _u(0x05) -#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_PIO0_27 _u(0x06) -#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_PIO1_27 _u(0x07) -#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x09) -#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) -// ============================================================================= -// Register : IO_BANK0_GPIO28_STATUS -// Description : GPIO status -#define IO_BANK0_GPIO28_STATUS_OFFSET _u(0x000000e0) -#define IO_BANK0_GPIO28_STATUS_BITS _u(0x050a3300) -#define IO_BANK0_GPIO28_STATUS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO28_STATUS_IRQTOPROC -// Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO28_STATUS_IRQTOPROC_RESET _u(0x0) -#define IO_BANK0_GPIO28_STATUS_IRQTOPROC_BITS _u(0x04000000) -#define IO_BANK0_GPIO28_STATUS_IRQTOPROC_MSB _u(26) -#define IO_BANK0_GPIO28_STATUS_IRQTOPROC_LSB _u(26) -#define IO_BANK0_GPIO28_STATUS_IRQTOPROC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO28_STATUS_IRQFROMPAD -// Description : interrupt from pad before override is applied -#define IO_BANK0_GPIO28_STATUS_IRQFROMPAD_RESET _u(0x0) -#define IO_BANK0_GPIO28_STATUS_IRQFROMPAD_BITS _u(0x01000000) -#define IO_BANK0_GPIO28_STATUS_IRQFROMPAD_MSB _u(24) -#define IO_BANK0_GPIO28_STATUS_IRQFROMPAD_LSB _u(24) -#define IO_BANK0_GPIO28_STATUS_IRQFROMPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO28_STATUS_INTOPERI -// Description : input signal to peripheral, after override is applied -#define IO_BANK0_GPIO28_STATUS_INTOPERI_RESET _u(0x0) -#define IO_BANK0_GPIO28_STATUS_INTOPERI_BITS _u(0x00080000) -#define IO_BANK0_GPIO28_STATUS_INTOPERI_MSB _u(19) -#define IO_BANK0_GPIO28_STATUS_INTOPERI_LSB _u(19) -#define IO_BANK0_GPIO28_STATUS_INTOPERI_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO28_STATUS_INFROMPAD -// Description : input signal from pad, before override is applied -#define IO_BANK0_GPIO28_STATUS_INFROMPAD_RESET _u(0x0) -#define IO_BANK0_GPIO28_STATUS_INFROMPAD_BITS _u(0x00020000) -#define IO_BANK0_GPIO28_STATUS_INFROMPAD_MSB _u(17) -#define IO_BANK0_GPIO28_STATUS_INFROMPAD_LSB _u(17) -#define IO_BANK0_GPIO28_STATUS_INFROMPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO28_STATUS_OETOPAD -// Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO28_STATUS_OETOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO28_STATUS_OETOPAD_BITS _u(0x00002000) -#define IO_BANK0_GPIO28_STATUS_OETOPAD_MSB _u(13) -#define IO_BANK0_GPIO28_STATUS_OETOPAD_LSB _u(13) -#define IO_BANK0_GPIO28_STATUS_OETOPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO28_STATUS_OEFROMPERI -// Description : output enable from selected peripheral, before register -// override is applied -#define IO_BANK0_GPIO28_STATUS_OEFROMPERI_RESET _u(0x0) -#define IO_BANK0_GPIO28_STATUS_OEFROMPERI_BITS _u(0x00001000) -#define IO_BANK0_GPIO28_STATUS_OEFROMPERI_MSB _u(12) -#define IO_BANK0_GPIO28_STATUS_OEFROMPERI_LSB _u(12) -#define IO_BANK0_GPIO28_STATUS_OEFROMPERI_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO28_STATUS_OUTTOPAD -// Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO28_STATUS_OUTTOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO28_STATUS_OUTTOPAD_BITS _u(0x00000200) -#define IO_BANK0_GPIO28_STATUS_OUTTOPAD_MSB _u(9) -#define IO_BANK0_GPIO28_STATUS_OUTTOPAD_LSB _u(9) -#define IO_BANK0_GPIO28_STATUS_OUTTOPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO28_STATUS_OUTFROMPERI -// Description : output signal from selected peripheral, before register -// override is applied -#define IO_BANK0_GPIO28_STATUS_OUTFROMPERI_RESET _u(0x0) -#define IO_BANK0_GPIO28_STATUS_OUTFROMPERI_BITS _u(0x00000100) -#define IO_BANK0_GPIO28_STATUS_OUTFROMPERI_MSB _u(8) -#define IO_BANK0_GPIO28_STATUS_OUTFROMPERI_LSB _u(8) -#define IO_BANK0_GPIO28_STATUS_OUTFROMPERI_ACCESS "RO" -// ============================================================================= -// Register : IO_BANK0_GPIO28_CTRL -// Description : GPIO control including function select and overrides. -#define IO_BANK0_GPIO28_CTRL_OFFSET _u(0x000000e4) -#define IO_BANK0_GPIO28_CTRL_BITS _u(0x3003331f) -#define IO_BANK0_GPIO28_CTRL_RESET _u(0x0000001f) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO28_CTRL_IRQOVER -// 0x0 -> don't invert the interrupt -// 0x1 -> invert the interrupt -// 0x2 -> drive interrupt low -// 0x3 -> drive interrupt high -#define IO_BANK0_GPIO28_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO28_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO28_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO28_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO28_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO28_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO28_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO28_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO28_CTRL_IRQOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO28_CTRL_INOVER -// 0x0 -> don't invert the peri input -// 0x1 -> invert the peri input -// 0x2 -> drive peri input low -// 0x3 -> drive peri input high -#define IO_BANK0_GPIO28_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO28_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO28_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO28_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO28_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO28_CTRL_INOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO28_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO28_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO28_CTRL_INOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO28_CTRL_OEOVER -// 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel -// 0x2 -> disable output -// 0x3 -> enable output -#define IO_BANK0_GPIO28_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO28_CTRL_OEOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO28_CTRL_OEOVER_MSB _u(13) -#define IO_BANK0_GPIO28_CTRL_OEOVER_LSB _u(12) -#define IO_BANK0_GPIO28_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO28_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO28_CTRL_OEOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO28_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO28_CTRL_OEOVER_VALUE_ENABLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO28_CTRL_OUTOVER -// 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel -// 0x2 -> drive output low -// 0x3 -> drive output high -#define IO_BANK0_GPIO28_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO28_CTRL_OUTOVER_BITS _u(0x00000300) -#define IO_BANK0_GPIO28_CTRL_OUTOVER_MSB _u(9) -#define IO_BANK0_GPIO28_CTRL_OUTOVER_LSB _u(8) -#define IO_BANK0_GPIO28_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO28_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO28_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO28_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO28_CTRL_OUTOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO28_CTRL_FUNCSEL -// Description : 0-31 -> selects pin function according to the gpio table -// 31 == NULL -// 0x01 -> spi1_rx -// 0x02 -> uart0_tx -// 0x03 -> i2c0_sda -// 0x04 -> pwm_a_6 -// 0x05 -> sio_28 -// 0x06 -> pio0_28 -// 0x07 -> pio1_28 -// 0x09 -> usb_muxing_vbus_detect -// 0x1f -> null -#define IO_BANK0_GPIO28_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO28_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO28_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO28_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO28_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_SPI1_RX _u(0x01) -#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_UART0_TX _u(0x02) -#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03) -#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_PWM_A_6 _u(0x04) -#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_SIO_28 _u(0x05) -#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_PIO0_28 _u(0x06) -#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_PIO1_28 _u(0x07) -#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x09) -#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) -// ============================================================================= -// Register : IO_BANK0_GPIO29_STATUS -// Description : GPIO status -#define IO_BANK0_GPIO29_STATUS_OFFSET _u(0x000000e8) -#define IO_BANK0_GPIO29_STATUS_BITS _u(0x050a3300) -#define IO_BANK0_GPIO29_STATUS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO29_STATUS_IRQTOPROC -// Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO29_STATUS_IRQTOPROC_RESET _u(0x0) -#define IO_BANK0_GPIO29_STATUS_IRQTOPROC_BITS _u(0x04000000) -#define IO_BANK0_GPIO29_STATUS_IRQTOPROC_MSB _u(26) -#define IO_BANK0_GPIO29_STATUS_IRQTOPROC_LSB _u(26) -#define IO_BANK0_GPIO29_STATUS_IRQTOPROC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO29_STATUS_IRQFROMPAD -// Description : interrupt from pad before override is applied -#define IO_BANK0_GPIO29_STATUS_IRQFROMPAD_RESET _u(0x0) -#define IO_BANK0_GPIO29_STATUS_IRQFROMPAD_BITS _u(0x01000000) -#define IO_BANK0_GPIO29_STATUS_IRQFROMPAD_MSB _u(24) -#define IO_BANK0_GPIO29_STATUS_IRQFROMPAD_LSB _u(24) -#define IO_BANK0_GPIO29_STATUS_IRQFROMPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO29_STATUS_INTOPERI -// Description : input signal to peripheral, after override is applied -#define IO_BANK0_GPIO29_STATUS_INTOPERI_RESET _u(0x0) -#define IO_BANK0_GPIO29_STATUS_INTOPERI_BITS _u(0x00080000) -#define IO_BANK0_GPIO29_STATUS_INTOPERI_MSB _u(19) -#define IO_BANK0_GPIO29_STATUS_INTOPERI_LSB _u(19) -#define IO_BANK0_GPIO29_STATUS_INTOPERI_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO29_STATUS_INFROMPAD -// Description : input signal from pad, before override is applied -#define IO_BANK0_GPIO29_STATUS_INFROMPAD_RESET _u(0x0) -#define IO_BANK0_GPIO29_STATUS_INFROMPAD_BITS _u(0x00020000) -#define IO_BANK0_GPIO29_STATUS_INFROMPAD_MSB _u(17) -#define IO_BANK0_GPIO29_STATUS_INFROMPAD_LSB _u(17) -#define IO_BANK0_GPIO29_STATUS_INFROMPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO29_STATUS_OETOPAD -// Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO29_STATUS_OETOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO29_STATUS_OETOPAD_BITS _u(0x00002000) -#define IO_BANK0_GPIO29_STATUS_OETOPAD_MSB _u(13) -#define IO_BANK0_GPIO29_STATUS_OETOPAD_LSB _u(13) -#define IO_BANK0_GPIO29_STATUS_OETOPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO29_STATUS_OEFROMPERI -// Description : output enable from selected peripheral, before register -// override is applied -#define IO_BANK0_GPIO29_STATUS_OEFROMPERI_RESET _u(0x0) -#define IO_BANK0_GPIO29_STATUS_OEFROMPERI_BITS _u(0x00001000) -#define IO_BANK0_GPIO29_STATUS_OEFROMPERI_MSB _u(12) -#define IO_BANK0_GPIO29_STATUS_OEFROMPERI_LSB _u(12) -#define IO_BANK0_GPIO29_STATUS_OEFROMPERI_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO29_STATUS_OUTTOPAD -// Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO29_STATUS_OUTTOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO29_STATUS_OUTTOPAD_BITS _u(0x00000200) -#define IO_BANK0_GPIO29_STATUS_OUTTOPAD_MSB _u(9) -#define IO_BANK0_GPIO29_STATUS_OUTTOPAD_LSB _u(9) -#define IO_BANK0_GPIO29_STATUS_OUTTOPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO29_STATUS_OUTFROMPERI -// Description : output signal from selected peripheral, before register -// override is applied -#define IO_BANK0_GPIO29_STATUS_OUTFROMPERI_RESET _u(0x0) -#define IO_BANK0_GPIO29_STATUS_OUTFROMPERI_BITS _u(0x00000100) -#define IO_BANK0_GPIO29_STATUS_OUTFROMPERI_MSB _u(8) -#define IO_BANK0_GPIO29_STATUS_OUTFROMPERI_LSB _u(8) -#define IO_BANK0_GPIO29_STATUS_OUTFROMPERI_ACCESS "RO" -// ============================================================================= -// Register : IO_BANK0_GPIO29_CTRL -// Description : GPIO control including function select and overrides. -#define IO_BANK0_GPIO29_CTRL_OFFSET _u(0x000000ec) -#define IO_BANK0_GPIO29_CTRL_BITS _u(0x3003331f) -#define IO_BANK0_GPIO29_CTRL_RESET _u(0x0000001f) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO29_CTRL_IRQOVER -// 0x0 -> don't invert the interrupt -// 0x1 -> invert the interrupt -// 0x2 -> drive interrupt low -// 0x3 -> drive interrupt high -#define IO_BANK0_GPIO29_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO29_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO29_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO29_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO29_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO29_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO29_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO29_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO29_CTRL_IRQOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO29_CTRL_INOVER -// 0x0 -> don't invert the peri input -// 0x1 -> invert the peri input -// 0x2 -> drive peri input low -// 0x3 -> drive peri input high -#define IO_BANK0_GPIO29_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO29_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO29_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO29_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO29_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO29_CTRL_INOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO29_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO29_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO29_CTRL_INOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO29_CTRL_OEOVER -// 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel -// 0x2 -> disable output -// 0x3 -> enable output -#define IO_BANK0_GPIO29_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO29_CTRL_OEOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO29_CTRL_OEOVER_MSB _u(13) -#define IO_BANK0_GPIO29_CTRL_OEOVER_LSB _u(12) -#define IO_BANK0_GPIO29_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO29_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO29_CTRL_OEOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO29_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO29_CTRL_OEOVER_VALUE_ENABLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO29_CTRL_OUTOVER -// 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel -// 0x2 -> drive output low -// 0x3 -> drive output high -#define IO_BANK0_GPIO29_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO29_CTRL_OUTOVER_BITS _u(0x00000300) -#define IO_BANK0_GPIO29_CTRL_OUTOVER_MSB _u(9) -#define IO_BANK0_GPIO29_CTRL_OUTOVER_LSB _u(8) -#define IO_BANK0_GPIO29_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO29_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO29_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO29_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO29_CTRL_OUTOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO29_CTRL_FUNCSEL -// Description : 0-31 -> selects pin function according to the gpio table -// 31 == NULL -// 0x01 -> spi1_ss_n -// 0x02 -> uart0_rx -// 0x03 -> i2c0_scl -// 0x04 -> pwm_b_6 -// 0x05 -> sio_29 -// 0x06 -> pio0_29 -// 0x07 -> pio1_29 -// 0x09 -> usb_muxing_vbus_en -// 0x1f -> null -#define IO_BANK0_GPIO29_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO29_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO29_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO29_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO29_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_SPI1_SS_N _u(0x01) -#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_UART0_RX _u(0x02) -#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03) -#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_PWM_B_6 _u(0x04) -#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_SIO_29 _u(0x05) -#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_PIO0_29 _u(0x06) -#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_PIO1_29 _u(0x07) -#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x09) -#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) -// ============================================================================= -// Register : IO_BANK0_INTR0 -// Description : Raw Interrupts -#define IO_BANK0_INTR0_OFFSET _u(0x000000f0) -#define IO_BANK0_INTR0_BITS _u(0xffffffff) -#define IO_BANK0_INTR0_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR0_GPIO7_EDGE_HIGH -#define IO_BANK0_INTR0_GPIO7_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR0_GPIO7_EDGE_HIGH_BITS _u(0x80000000) -#define IO_BANK0_INTR0_GPIO7_EDGE_HIGH_MSB _u(31) -#define IO_BANK0_INTR0_GPIO7_EDGE_HIGH_LSB _u(31) -#define IO_BANK0_INTR0_GPIO7_EDGE_HIGH_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR0_GPIO7_EDGE_LOW -#define IO_BANK0_INTR0_GPIO7_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_INTR0_GPIO7_EDGE_LOW_BITS _u(0x40000000) -#define IO_BANK0_INTR0_GPIO7_EDGE_LOW_MSB _u(30) -#define IO_BANK0_INTR0_GPIO7_EDGE_LOW_LSB _u(30) -#define IO_BANK0_INTR0_GPIO7_EDGE_LOW_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR0_GPIO7_LEVEL_HIGH -#define IO_BANK0_INTR0_GPIO7_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR0_GPIO7_LEVEL_HIGH_BITS _u(0x20000000) -#define IO_BANK0_INTR0_GPIO7_LEVEL_HIGH_MSB _u(29) -#define IO_BANK0_INTR0_GPIO7_LEVEL_HIGH_LSB _u(29) -#define IO_BANK0_INTR0_GPIO7_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR0_GPIO7_LEVEL_LOW -#define IO_BANK0_INTR0_GPIO7_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_INTR0_GPIO7_LEVEL_LOW_BITS _u(0x10000000) -#define IO_BANK0_INTR0_GPIO7_LEVEL_LOW_MSB _u(28) -#define IO_BANK0_INTR0_GPIO7_LEVEL_LOW_LSB _u(28) -#define IO_BANK0_INTR0_GPIO7_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR0_GPIO6_EDGE_HIGH -#define IO_BANK0_INTR0_GPIO6_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR0_GPIO6_EDGE_HIGH_BITS _u(0x08000000) -#define IO_BANK0_INTR0_GPIO6_EDGE_HIGH_MSB _u(27) -#define IO_BANK0_INTR0_GPIO6_EDGE_HIGH_LSB _u(27) -#define IO_BANK0_INTR0_GPIO6_EDGE_HIGH_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR0_GPIO6_EDGE_LOW -#define IO_BANK0_INTR0_GPIO6_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_INTR0_GPIO6_EDGE_LOW_BITS _u(0x04000000) -#define IO_BANK0_INTR0_GPIO6_EDGE_LOW_MSB _u(26) -#define IO_BANK0_INTR0_GPIO6_EDGE_LOW_LSB _u(26) -#define IO_BANK0_INTR0_GPIO6_EDGE_LOW_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR0_GPIO6_LEVEL_HIGH -#define IO_BANK0_INTR0_GPIO6_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR0_GPIO6_LEVEL_HIGH_BITS _u(0x02000000) -#define IO_BANK0_INTR0_GPIO6_LEVEL_HIGH_MSB _u(25) -#define IO_BANK0_INTR0_GPIO6_LEVEL_HIGH_LSB _u(25) -#define IO_BANK0_INTR0_GPIO6_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR0_GPIO6_LEVEL_LOW -#define IO_BANK0_INTR0_GPIO6_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_INTR0_GPIO6_LEVEL_LOW_BITS _u(0x01000000) -#define IO_BANK0_INTR0_GPIO6_LEVEL_LOW_MSB _u(24) -#define IO_BANK0_INTR0_GPIO6_LEVEL_LOW_LSB _u(24) -#define IO_BANK0_INTR0_GPIO6_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR0_GPIO5_EDGE_HIGH -#define IO_BANK0_INTR0_GPIO5_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR0_GPIO5_EDGE_HIGH_BITS _u(0x00800000) -#define IO_BANK0_INTR0_GPIO5_EDGE_HIGH_MSB _u(23) -#define IO_BANK0_INTR0_GPIO5_EDGE_HIGH_LSB _u(23) -#define IO_BANK0_INTR0_GPIO5_EDGE_HIGH_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR0_GPIO5_EDGE_LOW -#define IO_BANK0_INTR0_GPIO5_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_INTR0_GPIO5_EDGE_LOW_BITS _u(0x00400000) -#define IO_BANK0_INTR0_GPIO5_EDGE_LOW_MSB _u(22) -#define IO_BANK0_INTR0_GPIO5_EDGE_LOW_LSB _u(22) -#define IO_BANK0_INTR0_GPIO5_EDGE_LOW_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR0_GPIO5_LEVEL_HIGH -#define IO_BANK0_INTR0_GPIO5_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR0_GPIO5_LEVEL_HIGH_BITS _u(0x00200000) -#define IO_BANK0_INTR0_GPIO5_LEVEL_HIGH_MSB _u(21) -#define IO_BANK0_INTR0_GPIO5_LEVEL_HIGH_LSB _u(21) -#define IO_BANK0_INTR0_GPIO5_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR0_GPIO5_LEVEL_LOW -#define IO_BANK0_INTR0_GPIO5_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_INTR0_GPIO5_LEVEL_LOW_BITS _u(0x00100000) -#define IO_BANK0_INTR0_GPIO5_LEVEL_LOW_MSB _u(20) -#define IO_BANK0_INTR0_GPIO5_LEVEL_LOW_LSB _u(20) -#define IO_BANK0_INTR0_GPIO5_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR0_GPIO4_EDGE_HIGH -#define IO_BANK0_INTR0_GPIO4_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR0_GPIO4_EDGE_HIGH_BITS _u(0x00080000) -#define IO_BANK0_INTR0_GPIO4_EDGE_HIGH_MSB _u(19) -#define IO_BANK0_INTR0_GPIO4_EDGE_HIGH_LSB _u(19) -#define IO_BANK0_INTR0_GPIO4_EDGE_HIGH_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR0_GPIO4_EDGE_LOW -#define IO_BANK0_INTR0_GPIO4_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_INTR0_GPIO4_EDGE_LOW_BITS _u(0x00040000) -#define IO_BANK0_INTR0_GPIO4_EDGE_LOW_MSB _u(18) -#define IO_BANK0_INTR0_GPIO4_EDGE_LOW_LSB _u(18) -#define IO_BANK0_INTR0_GPIO4_EDGE_LOW_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR0_GPIO4_LEVEL_HIGH -#define IO_BANK0_INTR0_GPIO4_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR0_GPIO4_LEVEL_HIGH_BITS _u(0x00020000) -#define IO_BANK0_INTR0_GPIO4_LEVEL_HIGH_MSB _u(17) -#define IO_BANK0_INTR0_GPIO4_LEVEL_HIGH_LSB _u(17) -#define IO_BANK0_INTR0_GPIO4_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR0_GPIO4_LEVEL_LOW -#define IO_BANK0_INTR0_GPIO4_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_INTR0_GPIO4_LEVEL_LOW_BITS _u(0x00010000) -#define IO_BANK0_INTR0_GPIO4_LEVEL_LOW_MSB _u(16) -#define IO_BANK0_INTR0_GPIO4_LEVEL_LOW_LSB _u(16) -#define IO_BANK0_INTR0_GPIO4_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR0_GPIO3_EDGE_HIGH -#define IO_BANK0_INTR0_GPIO3_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR0_GPIO3_EDGE_HIGH_BITS _u(0x00008000) -#define IO_BANK0_INTR0_GPIO3_EDGE_HIGH_MSB _u(15) -#define IO_BANK0_INTR0_GPIO3_EDGE_HIGH_LSB _u(15) -#define IO_BANK0_INTR0_GPIO3_EDGE_HIGH_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR0_GPIO3_EDGE_LOW -#define IO_BANK0_INTR0_GPIO3_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_INTR0_GPIO3_EDGE_LOW_BITS _u(0x00004000) -#define IO_BANK0_INTR0_GPIO3_EDGE_LOW_MSB _u(14) -#define IO_BANK0_INTR0_GPIO3_EDGE_LOW_LSB _u(14) -#define IO_BANK0_INTR0_GPIO3_EDGE_LOW_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR0_GPIO3_LEVEL_HIGH -#define IO_BANK0_INTR0_GPIO3_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR0_GPIO3_LEVEL_HIGH_BITS _u(0x00002000) -#define IO_BANK0_INTR0_GPIO3_LEVEL_HIGH_MSB _u(13) -#define IO_BANK0_INTR0_GPIO3_LEVEL_HIGH_LSB _u(13) -#define IO_BANK0_INTR0_GPIO3_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR0_GPIO3_LEVEL_LOW -#define IO_BANK0_INTR0_GPIO3_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_INTR0_GPIO3_LEVEL_LOW_BITS _u(0x00001000) -#define IO_BANK0_INTR0_GPIO3_LEVEL_LOW_MSB _u(12) -#define IO_BANK0_INTR0_GPIO3_LEVEL_LOW_LSB _u(12) -#define IO_BANK0_INTR0_GPIO3_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR0_GPIO2_EDGE_HIGH -#define IO_BANK0_INTR0_GPIO2_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR0_GPIO2_EDGE_HIGH_BITS _u(0x00000800) -#define IO_BANK0_INTR0_GPIO2_EDGE_HIGH_MSB _u(11) -#define IO_BANK0_INTR0_GPIO2_EDGE_HIGH_LSB _u(11) -#define IO_BANK0_INTR0_GPIO2_EDGE_HIGH_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR0_GPIO2_EDGE_LOW -#define IO_BANK0_INTR0_GPIO2_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_INTR0_GPIO2_EDGE_LOW_BITS _u(0x00000400) -#define IO_BANK0_INTR0_GPIO2_EDGE_LOW_MSB _u(10) -#define IO_BANK0_INTR0_GPIO2_EDGE_LOW_LSB _u(10) -#define IO_BANK0_INTR0_GPIO2_EDGE_LOW_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR0_GPIO2_LEVEL_HIGH -#define IO_BANK0_INTR0_GPIO2_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR0_GPIO2_LEVEL_HIGH_BITS _u(0x00000200) -#define IO_BANK0_INTR0_GPIO2_LEVEL_HIGH_MSB _u(9) -#define IO_BANK0_INTR0_GPIO2_LEVEL_HIGH_LSB _u(9) -#define IO_BANK0_INTR0_GPIO2_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR0_GPIO2_LEVEL_LOW -#define IO_BANK0_INTR0_GPIO2_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_INTR0_GPIO2_LEVEL_LOW_BITS _u(0x00000100) -#define IO_BANK0_INTR0_GPIO2_LEVEL_LOW_MSB _u(8) -#define IO_BANK0_INTR0_GPIO2_LEVEL_LOW_LSB _u(8) -#define IO_BANK0_INTR0_GPIO2_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR0_GPIO1_EDGE_HIGH -#define IO_BANK0_INTR0_GPIO1_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR0_GPIO1_EDGE_HIGH_BITS _u(0x00000080) -#define IO_BANK0_INTR0_GPIO1_EDGE_HIGH_MSB _u(7) -#define IO_BANK0_INTR0_GPIO1_EDGE_HIGH_LSB _u(7) -#define IO_BANK0_INTR0_GPIO1_EDGE_HIGH_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR0_GPIO1_EDGE_LOW -#define IO_BANK0_INTR0_GPIO1_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_INTR0_GPIO1_EDGE_LOW_BITS _u(0x00000040) -#define IO_BANK0_INTR0_GPIO1_EDGE_LOW_MSB _u(6) -#define IO_BANK0_INTR0_GPIO1_EDGE_LOW_LSB _u(6) -#define IO_BANK0_INTR0_GPIO1_EDGE_LOW_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR0_GPIO1_LEVEL_HIGH -#define IO_BANK0_INTR0_GPIO1_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR0_GPIO1_LEVEL_HIGH_BITS _u(0x00000020) -#define IO_BANK0_INTR0_GPIO1_LEVEL_HIGH_MSB _u(5) -#define IO_BANK0_INTR0_GPIO1_LEVEL_HIGH_LSB _u(5) -#define IO_BANK0_INTR0_GPIO1_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR0_GPIO1_LEVEL_LOW -#define IO_BANK0_INTR0_GPIO1_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_INTR0_GPIO1_LEVEL_LOW_BITS _u(0x00000010) -#define IO_BANK0_INTR0_GPIO1_LEVEL_LOW_MSB _u(4) -#define IO_BANK0_INTR0_GPIO1_LEVEL_LOW_LSB _u(4) -#define IO_BANK0_INTR0_GPIO1_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR0_GPIO0_EDGE_HIGH -#define IO_BANK0_INTR0_GPIO0_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR0_GPIO0_EDGE_HIGH_BITS _u(0x00000008) -#define IO_BANK0_INTR0_GPIO0_EDGE_HIGH_MSB _u(3) -#define IO_BANK0_INTR0_GPIO0_EDGE_HIGH_LSB _u(3) -#define IO_BANK0_INTR0_GPIO0_EDGE_HIGH_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR0_GPIO0_EDGE_LOW -#define IO_BANK0_INTR0_GPIO0_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_INTR0_GPIO0_EDGE_LOW_BITS _u(0x00000004) -#define IO_BANK0_INTR0_GPIO0_EDGE_LOW_MSB _u(2) -#define IO_BANK0_INTR0_GPIO0_EDGE_LOW_LSB _u(2) -#define IO_BANK0_INTR0_GPIO0_EDGE_LOW_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR0_GPIO0_LEVEL_HIGH -#define IO_BANK0_INTR0_GPIO0_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR0_GPIO0_LEVEL_HIGH_BITS _u(0x00000002) -#define IO_BANK0_INTR0_GPIO0_LEVEL_HIGH_MSB _u(1) -#define IO_BANK0_INTR0_GPIO0_LEVEL_HIGH_LSB _u(1) -#define IO_BANK0_INTR0_GPIO0_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR0_GPIO0_LEVEL_LOW -#define IO_BANK0_INTR0_GPIO0_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_INTR0_GPIO0_LEVEL_LOW_BITS _u(0x00000001) -#define IO_BANK0_INTR0_GPIO0_LEVEL_LOW_MSB _u(0) -#define IO_BANK0_INTR0_GPIO0_LEVEL_LOW_LSB _u(0) -#define IO_BANK0_INTR0_GPIO0_LEVEL_LOW_ACCESS "RO" -// ============================================================================= -// Register : IO_BANK0_INTR1 -// Description : Raw Interrupts -#define IO_BANK0_INTR1_OFFSET _u(0x000000f4) -#define IO_BANK0_INTR1_BITS _u(0xffffffff) -#define IO_BANK0_INTR1_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR1_GPIO15_EDGE_HIGH -#define IO_BANK0_INTR1_GPIO15_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR1_GPIO15_EDGE_HIGH_BITS _u(0x80000000) -#define IO_BANK0_INTR1_GPIO15_EDGE_HIGH_MSB _u(31) -#define IO_BANK0_INTR1_GPIO15_EDGE_HIGH_LSB _u(31) -#define IO_BANK0_INTR1_GPIO15_EDGE_HIGH_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR1_GPIO15_EDGE_LOW -#define IO_BANK0_INTR1_GPIO15_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_INTR1_GPIO15_EDGE_LOW_BITS _u(0x40000000) -#define IO_BANK0_INTR1_GPIO15_EDGE_LOW_MSB _u(30) -#define IO_BANK0_INTR1_GPIO15_EDGE_LOW_LSB _u(30) -#define IO_BANK0_INTR1_GPIO15_EDGE_LOW_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR1_GPIO15_LEVEL_HIGH -#define IO_BANK0_INTR1_GPIO15_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR1_GPIO15_LEVEL_HIGH_BITS _u(0x20000000) -#define IO_BANK0_INTR1_GPIO15_LEVEL_HIGH_MSB _u(29) -#define IO_BANK0_INTR1_GPIO15_LEVEL_HIGH_LSB _u(29) -#define IO_BANK0_INTR1_GPIO15_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR1_GPIO15_LEVEL_LOW -#define IO_BANK0_INTR1_GPIO15_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_INTR1_GPIO15_LEVEL_LOW_BITS _u(0x10000000) -#define IO_BANK0_INTR1_GPIO15_LEVEL_LOW_MSB _u(28) -#define IO_BANK0_INTR1_GPIO15_LEVEL_LOW_LSB _u(28) -#define IO_BANK0_INTR1_GPIO15_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR1_GPIO14_EDGE_HIGH -#define IO_BANK0_INTR1_GPIO14_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR1_GPIO14_EDGE_HIGH_BITS _u(0x08000000) -#define IO_BANK0_INTR1_GPIO14_EDGE_HIGH_MSB _u(27) -#define IO_BANK0_INTR1_GPIO14_EDGE_HIGH_LSB _u(27) -#define IO_BANK0_INTR1_GPIO14_EDGE_HIGH_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR1_GPIO14_EDGE_LOW -#define IO_BANK0_INTR1_GPIO14_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_INTR1_GPIO14_EDGE_LOW_BITS _u(0x04000000) -#define IO_BANK0_INTR1_GPIO14_EDGE_LOW_MSB _u(26) -#define IO_BANK0_INTR1_GPIO14_EDGE_LOW_LSB _u(26) -#define IO_BANK0_INTR1_GPIO14_EDGE_LOW_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR1_GPIO14_LEVEL_HIGH -#define IO_BANK0_INTR1_GPIO14_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR1_GPIO14_LEVEL_HIGH_BITS _u(0x02000000) -#define IO_BANK0_INTR1_GPIO14_LEVEL_HIGH_MSB _u(25) -#define IO_BANK0_INTR1_GPIO14_LEVEL_HIGH_LSB _u(25) -#define IO_BANK0_INTR1_GPIO14_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR1_GPIO14_LEVEL_LOW -#define IO_BANK0_INTR1_GPIO14_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_INTR1_GPIO14_LEVEL_LOW_BITS _u(0x01000000) -#define IO_BANK0_INTR1_GPIO14_LEVEL_LOW_MSB _u(24) -#define IO_BANK0_INTR1_GPIO14_LEVEL_LOW_LSB _u(24) -#define IO_BANK0_INTR1_GPIO14_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR1_GPIO13_EDGE_HIGH -#define IO_BANK0_INTR1_GPIO13_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR1_GPIO13_EDGE_HIGH_BITS _u(0x00800000) -#define IO_BANK0_INTR1_GPIO13_EDGE_HIGH_MSB _u(23) -#define IO_BANK0_INTR1_GPIO13_EDGE_HIGH_LSB _u(23) -#define IO_BANK0_INTR1_GPIO13_EDGE_HIGH_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR1_GPIO13_EDGE_LOW -#define IO_BANK0_INTR1_GPIO13_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_INTR1_GPIO13_EDGE_LOW_BITS _u(0x00400000) -#define IO_BANK0_INTR1_GPIO13_EDGE_LOW_MSB _u(22) -#define IO_BANK0_INTR1_GPIO13_EDGE_LOW_LSB _u(22) -#define IO_BANK0_INTR1_GPIO13_EDGE_LOW_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR1_GPIO13_LEVEL_HIGH -#define IO_BANK0_INTR1_GPIO13_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR1_GPIO13_LEVEL_HIGH_BITS _u(0x00200000) -#define IO_BANK0_INTR1_GPIO13_LEVEL_HIGH_MSB _u(21) -#define IO_BANK0_INTR1_GPIO13_LEVEL_HIGH_LSB _u(21) -#define IO_BANK0_INTR1_GPIO13_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR1_GPIO13_LEVEL_LOW -#define IO_BANK0_INTR1_GPIO13_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_INTR1_GPIO13_LEVEL_LOW_BITS _u(0x00100000) -#define IO_BANK0_INTR1_GPIO13_LEVEL_LOW_MSB _u(20) -#define IO_BANK0_INTR1_GPIO13_LEVEL_LOW_LSB _u(20) -#define IO_BANK0_INTR1_GPIO13_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR1_GPIO12_EDGE_HIGH -#define IO_BANK0_INTR1_GPIO12_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR1_GPIO12_EDGE_HIGH_BITS _u(0x00080000) -#define IO_BANK0_INTR1_GPIO12_EDGE_HIGH_MSB _u(19) -#define IO_BANK0_INTR1_GPIO12_EDGE_HIGH_LSB _u(19) -#define IO_BANK0_INTR1_GPIO12_EDGE_HIGH_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR1_GPIO12_EDGE_LOW -#define IO_BANK0_INTR1_GPIO12_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_INTR1_GPIO12_EDGE_LOW_BITS _u(0x00040000) -#define IO_BANK0_INTR1_GPIO12_EDGE_LOW_MSB _u(18) -#define IO_BANK0_INTR1_GPIO12_EDGE_LOW_LSB _u(18) -#define IO_BANK0_INTR1_GPIO12_EDGE_LOW_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR1_GPIO12_LEVEL_HIGH -#define IO_BANK0_INTR1_GPIO12_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR1_GPIO12_LEVEL_HIGH_BITS _u(0x00020000) -#define IO_BANK0_INTR1_GPIO12_LEVEL_HIGH_MSB _u(17) -#define IO_BANK0_INTR1_GPIO12_LEVEL_HIGH_LSB _u(17) -#define IO_BANK0_INTR1_GPIO12_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR1_GPIO12_LEVEL_LOW -#define IO_BANK0_INTR1_GPIO12_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_INTR1_GPIO12_LEVEL_LOW_BITS _u(0x00010000) -#define IO_BANK0_INTR1_GPIO12_LEVEL_LOW_MSB _u(16) -#define IO_BANK0_INTR1_GPIO12_LEVEL_LOW_LSB _u(16) -#define IO_BANK0_INTR1_GPIO12_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR1_GPIO11_EDGE_HIGH -#define IO_BANK0_INTR1_GPIO11_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR1_GPIO11_EDGE_HIGH_BITS _u(0x00008000) -#define IO_BANK0_INTR1_GPIO11_EDGE_HIGH_MSB _u(15) -#define IO_BANK0_INTR1_GPIO11_EDGE_HIGH_LSB _u(15) -#define IO_BANK0_INTR1_GPIO11_EDGE_HIGH_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR1_GPIO11_EDGE_LOW -#define IO_BANK0_INTR1_GPIO11_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_INTR1_GPIO11_EDGE_LOW_BITS _u(0x00004000) -#define IO_BANK0_INTR1_GPIO11_EDGE_LOW_MSB _u(14) -#define IO_BANK0_INTR1_GPIO11_EDGE_LOW_LSB _u(14) -#define IO_BANK0_INTR1_GPIO11_EDGE_LOW_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR1_GPIO11_LEVEL_HIGH -#define IO_BANK0_INTR1_GPIO11_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR1_GPIO11_LEVEL_HIGH_BITS _u(0x00002000) -#define IO_BANK0_INTR1_GPIO11_LEVEL_HIGH_MSB _u(13) -#define IO_BANK0_INTR1_GPIO11_LEVEL_HIGH_LSB _u(13) -#define IO_BANK0_INTR1_GPIO11_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR1_GPIO11_LEVEL_LOW -#define IO_BANK0_INTR1_GPIO11_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_INTR1_GPIO11_LEVEL_LOW_BITS _u(0x00001000) -#define IO_BANK0_INTR1_GPIO11_LEVEL_LOW_MSB _u(12) -#define IO_BANK0_INTR1_GPIO11_LEVEL_LOW_LSB _u(12) -#define IO_BANK0_INTR1_GPIO11_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR1_GPIO10_EDGE_HIGH -#define IO_BANK0_INTR1_GPIO10_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR1_GPIO10_EDGE_HIGH_BITS _u(0x00000800) -#define IO_BANK0_INTR1_GPIO10_EDGE_HIGH_MSB _u(11) -#define IO_BANK0_INTR1_GPIO10_EDGE_HIGH_LSB _u(11) -#define IO_BANK0_INTR1_GPIO10_EDGE_HIGH_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR1_GPIO10_EDGE_LOW -#define IO_BANK0_INTR1_GPIO10_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_INTR1_GPIO10_EDGE_LOW_BITS _u(0x00000400) -#define IO_BANK0_INTR1_GPIO10_EDGE_LOW_MSB _u(10) -#define IO_BANK0_INTR1_GPIO10_EDGE_LOW_LSB _u(10) -#define IO_BANK0_INTR1_GPIO10_EDGE_LOW_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR1_GPIO10_LEVEL_HIGH -#define IO_BANK0_INTR1_GPIO10_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR1_GPIO10_LEVEL_HIGH_BITS _u(0x00000200) -#define IO_BANK0_INTR1_GPIO10_LEVEL_HIGH_MSB _u(9) -#define IO_BANK0_INTR1_GPIO10_LEVEL_HIGH_LSB _u(9) -#define IO_BANK0_INTR1_GPIO10_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR1_GPIO10_LEVEL_LOW -#define IO_BANK0_INTR1_GPIO10_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_INTR1_GPIO10_LEVEL_LOW_BITS _u(0x00000100) -#define IO_BANK0_INTR1_GPIO10_LEVEL_LOW_MSB _u(8) -#define IO_BANK0_INTR1_GPIO10_LEVEL_LOW_LSB _u(8) -#define IO_BANK0_INTR1_GPIO10_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR1_GPIO9_EDGE_HIGH -#define IO_BANK0_INTR1_GPIO9_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR1_GPIO9_EDGE_HIGH_BITS _u(0x00000080) -#define IO_BANK0_INTR1_GPIO9_EDGE_HIGH_MSB _u(7) -#define IO_BANK0_INTR1_GPIO9_EDGE_HIGH_LSB _u(7) -#define IO_BANK0_INTR1_GPIO9_EDGE_HIGH_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR1_GPIO9_EDGE_LOW -#define IO_BANK0_INTR1_GPIO9_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_INTR1_GPIO9_EDGE_LOW_BITS _u(0x00000040) -#define IO_BANK0_INTR1_GPIO9_EDGE_LOW_MSB _u(6) -#define IO_BANK0_INTR1_GPIO9_EDGE_LOW_LSB _u(6) -#define IO_BANK0_INTR1_GPIO9_EDGE_LOW_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR1_GPIO9_LEVEL_HIGH -#define IO_BANK0_INTR1_GPIO9_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR1_GPIO9_LEVEL_HIGH_BITS _u(0x00000020) -#define IO_BANK0_INTR1_GPIO9_LEVEL_HIGH_MSB _u(5) -#define IO_BANK0_INTR1_GPIO9_LEVEL_HIGH_LSB _u(5) -#define IO_BANK0_INTR1_GPIO9_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR1_GPIO9_LEVEL_LOW -#define IO_BANK0_INTR1_GPIO9_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_INTR1_GPIO9_LEVEL_LOW_BITS _u(0x00000010) -#define IO_BANK0_INTR1_GPIO9_LEVEL_LOW_MSB _u(4) -#define IO_BANK0_INTR1_GPIO9_LEVEL_LOW_LSB _u(4) -#define IO_BANK0_INTR1_GPIO9_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR1_GPIO8_EDGE_HIGH -#define IO_BANK0_INTR1_GPIO8_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR1_GPIO8_EDGE_HIGH_BITS _u(0x00000008) -#define IO_BANK0_INTR1_GPIO8_EDGE_HIGH_MSB _u(3) -#define IO_BANK0_INTR1_GPIO8_EDGE_HIGH_LSB _u(3) -#define IO_BANK0_INTR1_GPIO8_EDGE_HIGH_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR1_GPIO8_EDGE_LOW -#define IO_BANK0_INTR1_GPIO8_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_INTR1_GPIO8_EDGE_LOW_BITS _u(0x00000004) -#define IO_BANK0_INTR1_GPIO8_EDGE_LOW_MSB _u(2) -#define IO_BANK0_INTR1_GPIO8_EDGE_LOW_LSB _u(2) -#define IO_BANK0_INTR1_GPIO8_EDGE_LOW_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR1_GPIO8_LEVEL_HIGH -#define IO_BANK0_INTR1_GPIO8_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR1_GPIO8_LEVEL_HIGH_BITS _u(0x00000002) -#define IO_BANK0_INTR1_GPIO8_LEVEL_HIGH_MSB _u(1) -#define IO_BANK0_INTR1_GPIO8_LEVEL_HIGH_LSB _u(1) -#define IO_BANK0_INTR1_GPIO8_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR1_GPIO8_LEVEL_LOW -#define IO_BANK0_INTR1_GPIO8_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_INTR1_GPIO8_LEVEL_LOW_BITS _u(0x00000001) -#define IO_BANK0_INTR1_GPIO8_LEVEL_LOW_MSB _u(0) -#define IO_BANK0_INTR1_GPIO8_LEVEL_LOW_LSB _u(0) -#define IO_BANK0_INTR1_GPIO8_LEVEL_LOW_ACCESS "RO" -// ============================================================================= -// Register : IO_BANK0_INTR2 -// Description : Raw Interrupts -#define IO_BANK0_INTR2_OFFSET _u(0x000000f8) -#define IO_BANK0_INTR2_BITS _u(0xffffffff) -#define IO_BANK0_INTR2_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR2_GPIO23_EDGE_HIGH -#define IO_BANK0_INTR2_GPIO23_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR2_GPIO23_EDGE_HIGH_BITS _u(0x80000000) -#define IO_BANK0_INTR2_GPIO23_EDGE_HIGH_MSB _u(31) -#define IO_BANK0_INTR2_GPIO23_EDGE_HIGH_LSB _u(31) -#define IO_BANK0_INTR2_GPIO23_EDGE_HIGH_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR2_GPIO23_EDGE_LOW -#define IO_BANK0_INTR2_GPIO23_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_INTR2_GPIO23_EDGE_LOW_BITS _u(0x40000000) -#define IO_BANK0_INTR2_GPIO23_EDGE_LOW_MSB _u(30) -#define IO_BANK0_INTR2_GPIO23_EDGE_LOW_LSB _u(30) -#define IO_BANK0_INTR2_GPIO23_EDGE_LOW_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR2_GPIO23_LEVEL_HIGH -#define IO_BANK0_INTR2_GPIO23_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR2_GPIO23_LEVEL_HIGH_BITS _u(0x20000000) -#define IO_BANK0_INTR2_GPIO23_LEVEL_HIGH_MSB _u(29) -#define IO_BANK0_INTR2_GPIO23_LEVEL_HIGH_LSB _u(29) -#define IO_BANK0_INTR2_GPIO23_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR2_GPIO23_LEVEL_LOW -#define IO_BANK0_INTR2_GPIO23_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_INTR2_GPIO23_LEVEL_LOW_BITS _u(0x10000000) -#define IO_BANK0_INTR2_GPIO23_LEVEL_LOW_MSB _u(28) -#define IO_BANK0_INTR2_GPIO23_LEVEL_LOW_LSB _u(28) -#define IO_BANK0_INTR2_GPIO23_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR2_GPIO22_EDGE_HIGH -#define IO_BANK0_INTR2_GPIO22_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR2_GPIO22_EDGE_HIGH_BITS _u(0x08000000) -#define IO_BANK0_INTR2_GPIO22_EDGE_HIGH_MSB _u(27) -#define IO_BANK0_INTR2_GPIO22_EDGE_HIGH_LSB _u(27) -#define IO_BANK0_INTR2_GPIO22_EDGE_HIGH_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR2_GPIO22_EDGE_LOW -#define IO_BANK0_INTR2_GPIO22_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_INTR2_GPIO22_EDGE_LOW_BITS _u(0x04000000) -#define IO_BANK0_INTR2_GPIO22_EDGE_LOW_MSB _u(26) -#define IO_BANK0_INTR2_GPIO22_EDGE_LOW_LSB _u(26) -#define IO_BANK0_INTR2_GPIO22_EDGE_LOW_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR2_GPIO22_LEVEL_HIGH -#define IO_BANK0_INTR2_GPIO22_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR2_GPIO22_LEVEL_HIGH_BITS _u(0x02000000) -#define IO_BANK0_INTR2_GPIO22_LEVEL_HIGH_MSB _u(25) -#define IO_BANK0_INTR2_GPIO22_LEVEL_HIGH_LSB _u(25) -#define IO_BANK0_INTR2_GPIO22_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR2_GPIO22_LEVEL_LOW -#define IO_BANK0_INTR2_GPIO22_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_INTR2_GPIO22_LEVEL_LOW_BITS _u(0x01000000) -#define IO_BANK0_INTR2_GPIO22_LEVEL_LOW_MSB _u(24) -#define IO_BANK0_INTR2_GPIO22_LEVEL_LOW_LSB _u(24) -#define IO_BANK0_INTR2_GPIO22_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR2_GPIO21_EDGE_HIGH -#define IO_BANK0_INTR2_GPIO21_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR2_GPIO21_EDGE_HIGH_BITS _u(0x00800000) -#define IO_BANK0_INTR2_GPIO21_EDGE_HIGH_MSB _u(23) -#define IO_BANK0_INTR2_GPIO21_EDGE_HIGH_LSB _u(23) -#define IO_BANK0_INTR2_GPIO21_EDGE_HIGH_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR2_GPIO21_EDGE_LOW -#define IO_BANK0_INTR2_GPIO21_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_INTR2_GPIO21_EDGE_LOW_BITS _u(0x00400000) -#define IO_BANK0_INTR2_GPIO21_EDGE_LOW_MSB _u(22) -#define IO_BANK0_INTR2_GPIO21_EDGE_LOW_LSB _u(22) -#define IO_BANK0_INTR2_GPIO21_EDGE_LOW_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR2_GPIO21_LEVEL_HIGH -#define IO_BANK0_INTR2_GPIO21_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR2_GPIO21_LEVEL_HIGH_BITS _u(0x00200000) -#define IO_BANK0_INTR2_GPIO21_LEVEL_HIGH_MSB _u(21) -#define IO_BANK0_INTR2_GPIO21_LEVEL_HIGH_LSB _u(21) -#define IO_BANK0_INTR2_GPIO21_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR2_GPIO21_LEVEL_LOW -#define IO_BANK0_INTR2_GPIO21_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_INTR2_GPIO21_LEVEL_LOW_BITS _u(0x00100000) -#define IO_BANK0_INTR2_GPIO21_LEVEL_LOW_MSB _u(20) -#define IO_BANK0_INTR2_GPIO21_LEVEL_LOW_LSB _u(20) -#define IO_BANK0_INTR2_GPIO21_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR2_GPIO20_EDGE_HIGH -#define IO_BANK0_INTR2_GPIO20_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR2_GPIO20_EDGE_HIGH_BITS _u(0x00080000) -#define IO_BANK0_INTR2_GPIO20_EDGE_HIGH_MSB _u(19) -#define IO_BANK0_INTR2_GPIO20_EDGE_HIGH_LSB _u(19) -#define IO_BANK0_INTR2_GPIO20_EDGE_HIGH_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR2_GPIO20_EDGE_LOW -#define IO_BANK0_INTR2_GPIO20_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_INTR2_GPIO20_EDGE_LOW_BITS _u(0x00040000) -#define IO_BANK0_INTR2_GPIO20_EDGE_LOW_MSB _u(18) -#define IO_BANK0_INTR2_GPIO20_EDGE_LOW_LSB _u(18) -#define IO_BANK0_INTR2_GPIO20_EDGE_LOW_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR2_GPIO20_LEVEL_HIGH -#define IO_BANK0_INTR2_GPIO20_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR2_GPIO20_LEVEL_HIGH_BITS _u(0x00020000) -#define IO_BANK0_INTR2_GPIO20_LEVEL_HIGH_MSB _u(17) -#define IO_BANK0_INTR2_GPIO20_LEVEL_HIGH_LSB _u(17) -#define IO_BANK0_INTR2_GPIO20_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR2_GPIO20_LEVEL_LOW -#define IO_BANK0_INTR2_GPIO20_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_INTR2_GPIO20_LEVEL_LOW_BITS _u(0x00010000) -#define IO_BANK0_INTR2_GPIO20_LEVEL_LOW_MSB _u(16) -#define IO_BANK0_INTR2_GPIO20_LEVEL_LOW_LSB _u(16) -#define IO_BANK0_INTR2_GPIO20_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR2_GPIO19_EDGE_HIGH -#define IO_BANK0_INTR2_GPIO19_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR2_GPIO19_EDGE_HIGH_BITS _u(0x00008000) -#define IO_BANK0_INTR2_GPIO19_EDGE_HIGH_MSB _u(15) -#define IO_BANK0_INTR2_GPIO19_EDGE_HIGH_LSB _u(15) -#define IO_BANK0_INTR2_GPIO19_EDGE_HIGH_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR2_GPIO19_EDGE_LOW -#define IO_BANK0_INTR2_GPIO19_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_INTR2_GPIO19_EDGE_LOW_BITS _u(0x00004000) -#define IO_BANK0_INTR2_GPIO19_EDGE_LOW_MSB _u(14) -#define IO_BANK0_INTR2_GPIO19_EDGE_LOW_LSB _u(14) -#define IO_BANK0_INTR2_GPIO19_EDGE_LOW_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR2_GPIO19_LEVEL_HIGH -#define IO_BANK0_INTR2_GPIO19_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR2_GPIO19_LEVEL_HIGH_BITS _u(0x00002000) -#define IO_BANK0_INTR2_GPIO19_LEVEL_HIGH_MSB _u(13) -#define IO_BANK0_INTR2_GPIO19_LEVEL_HIGH_LSB _u(13) -#define IO_BANK0_INTR2_GPIO19_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR2_GPIO19_LEVEL_LOW -#define IO_BANK0_INTR2_GPIO19_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_INTR2_GPIO19_LEVEL_LOW_BITS _u(0x00001000) -#define IO_BANK0_INTR2_GPIO19_LEVEL_LOW_MSB _u(12) -#define IO_BANK0_INTR2_GPIO19_LEVEL_LOW_LSB _u(12) -#define IO_BANK0_INTR2_GPIO19_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR2_GPIO18_EDGE_HIGH -#define IO_BANK0_INTR2_GPIO18_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR2_GPIO18_EDGE_HIGH_BITS _u(0x00000800) -#define IO_BANK0_INTR2_GPIO18_EDGE_HIGH_MSB _u(11) -#define IO_BANK0_INTR2_GPIO18_EDGE_HIGH_LSB _u(11) -#define IO_BANK0_INTR2_GPIO18_EDGE_HIGH_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR2_GPIO18_EDGE_LOW -#define IO_BANK0_INTR2_GPIO18_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_INTR2_GPIO18_EDGE_LOW_BITS _u(0x00000400) -#define IO_BANK0_INTR2_GPIO18_EDGE_LOW_MSB _u(10) -#define IO_BANK0_INTR2_GPIO18_EDGE_LOW_LSB _u(10) -#define IO_BANK0_INTR2_GPIO18_EDGE_LOW_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR2_GPIO18_LEVEL_HIGH -#define IO_BANK0_INTR2_GPIO18_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR2_GPIO18_LEVEL_HIGH_BITS _u(0x00000200) -#define IO_BANK0_INTR2_GPIO18_LEVEL_HIGH_MSB _u(9) -#define IO_BANK0_INTR2_GPIO18_LEVEL_HIGH_LSB _u(9) -#define IO_BANK0_INTR2_GPIO18_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR2_GPIO18_LEVEL_LOW -#define IO_BANK0_INTR2_GPIO18_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_INTR2_GPIO18_LEVEL_LOW_BITS _u(0x00000100) -#define IO_BANK0_INTR2_GPIO18_LEVEL_LOW_MSB _u(8) -#define IO_BANK0_INTR2_GPIO18_LEVEL_LOW_LSB _u(8) -#define IO_BANK0_INTR2_GPIO18_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR2_GPIO17_EDGE_HIGH -#define IO_BANK0_INTR2_GPIO17_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR2_GPIO17_EDGE_HIGH_BITS _u(0x00000080) -#define IO_BANK0_INTR2_GPIO17_EDGE_HIGH_MSB _u(7) -#define IO_BANK0_INTR2_GPIO17_EDGE_HIGH_LSB _u(7) -#define IO_BANK0_INTR2_GPIO17_EDGE_HIGH_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR2_GPIO17_EDGE_LOW -#define IO_BANK0_INTR2_GPIO17_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_INTR2_GPIO17_EDGE_LOW_BITS _u(0x00000040) -#define IO_BANK0_INTR2_GPIO17_EDGE_LOW_MSB _u(6) -#define IO_BANK0_INTR2_GPIO17_EDGE_LOW_LSB _u(6) -#define IO_BANK0_INTR2_GPIO17_EDGE_LOW_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR2_GPIO17_LEVEL_HIGH -#define IO_BANK0_INTR2_GPIO17_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR2_GPIO17_LEVEL_HIGH_BITS _u(0x00000020) -#define IO_BANK0_INTR2_GPIO17_LEVEL_HIGH_MSB _u(5) -#define IO_BANK0_INTR2_GPIO17_LEVEL_HIGH_LSB _u(5) -#define IO_BANK0_INTR2_GPIO17_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR2_GPIO17_LEVEL_LOW -#define IO_BANK0_INTR2_GPIO17_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_INTR2_GPIO17_LEVEL_LOW_BITS _u(0x00000010) -#define IO_BANK0_INTR2_GPIO17_LEVEL_LOW_MSB _u(4) -#define IO_BANK0_INTR2_GPIO17_LEVEL_LOW_LSB _u(4) -#define IO_BANK0_INTR2_GPIO17_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR2_GPIO16_EDGE_HIGH -#define IO_BANK0_INTR2_GPIO16_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR2_GPIO16_EDGE_HIGH_BITS _u(0x00000008) -#define IO_BANK0_INTR2_GPIO16_EDGE_HIGH_MSB _u(3) -#define IO_BANK0_INTR2_GPIO16_EDGE_HIGH_LSB _u(3) -#define IO_BANK0_INTR2_GPIO16_EDGE_HIGH_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR2_GPIO16_EDGE_LOW -#define IO_BANK0_INTR2_GPIO16_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_INTR2_GPIO16_EDGE_LOW_BITS _u(0x00000004) -#define IO_BANK0_INTR2_GPIO16_EDGE_LOW_MSB _u(2) -#define IO_BANK0_INTR2_GPIO16_EDGE_LOW_LSB _u(2) -#define IO_BANK0_INTR2_GPIO16_EDGE_LOW_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR2_GPIO16_LEVEL_HIGH -#define IO_BANK0_INTR2_GPIO16_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR2_GPIO16_LEVEL_HIGH_BITS _u(0x00000002) -#define IO_BANK0_INTR2_GPIO16_LEVEL_HIGH_MSB _u(1) -#define IO_BANK0_INTR2_GPIO16_LEVEL_HIGH_LSB _u(1) -#define IO_BANK0_INTR2_GPIO16_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR2_GPIO16_LEVEL_LOW -#define IO_BANK0_INTR2_GPIO16_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_INTR2_GPIO16_LEVEL_LOW_BITS _u(0x00000001) -#define IO_BANK0_INTR2_GPIO16_LEVEL_LOW_MSB _u(0) -#define IO_BANK0_INTR2_GPIO16_LEVEL_LOW_LSB _u(0) -#define IO_BANK0_INTR2_GPIO16_LEVEL_LOW_ACCESS "RO" -// ============================================================================= -// Register : IO_BANK0_INTR3 -// Description : Raw Interrupts -#define IO_BANK0_INTR3_OFFSET _u(0x000000fc) -#define IO_BANK0_INTR3_BITS _u(0x00ffffff) -#define IO_BANK0_INTR3_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR3_GPIO29_EDGE_HIGH -#define IO_BANK0_INTR3_GPIO29_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR3_GPIO29_EDGE_HIGH_BITS _u(0x00800000) -#define IO_BANK0_INTR3_GPIO29_EDGE_HIGH_MSB _u(23) -#define IO_BANK0_INTR3_GPIO29_EDGE_HIGH_LSB _u(23) -#define IO_BANK0_INTR3_GPIO29_EDGE_HIGH_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR3_GPIO29_EDGE_LOW -#define IO_BANK0_INTR3_GPIO29_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_INTR3_GPIO29_EDGE_LOW_BITS _u(0x00400000) -#define IO_BANK0_INTR3_GPIO29_EDGE_LOW_MSB _u(22) -#define IO_BANK0_INTR3_GPIO29_EDGE_LOW_LSB _u(22) -#define IO_BANK0_INTR3_GPIO29_EDGE_LOW_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR3_GPIO29_LEVEL_HIGH -#define IO_BANK0_INTR3_GPIO29_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR3_GPIO29_LEVEL_HIGH_BITS _u(0x00200000) -#define IO_BANK0_INTR3_GPIO29_LEVEL_HIGH_MSB _u(21) -#define IO_BANK0_INTR3_GPIO29_LEVEL_HIGH_LSB _u(21) -#define IO_BANK0_INTR3_GPIO29_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR3_GPIO29_LEVEL_LOW -#define IO_BANK0_INTR3_GPIO29_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_INTR3_GPIO29_LEVEL_LOW_BITS _u(0x00100000) -#define IO_BANK0_INTR3_GPIO29_LEVEL_LOW_MSB _u(20) -#define IO_BANK0_INTR3_GPIO29_LEVEL_LOW_LSB _u(20) -#define IO_BANK0_INTR3_GPIO29_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR3_GPIO28_EDGE_HIGH -#define IO_BANK0_INTR3_GPIO28_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR3_GPIO28_EDGE_HIGH_BITS _u(0x00080000) -#define IO_BANK0_INTR3_GPIO28_EDGE_HIGH_MSB _u(19) -#define IO_BANK0_INTR3_GPIO28_EDGE_HIGH_LSB _u(19) -#define IO_BANK0_INTR3_GPIO28_EDGE_HIGH_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR3_GPIO28_EDGE_LOW -#define IO_BANK0_INTR3_GPIO28_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_INTR3_GPIO28_EDGE_LOW_BITS _u(0x00040000) -#define IO_BANK0_INTR3_GPIO28_EDGE_LOW_MSB _u(18) -#define IO_BANK0_INTR3_GPIO28_EDGE_LOW_LSB _u(18) -#define IO_BANK0_INTR3_GPIO28_EDGE_LOW_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR3_GPIO28_LEVEL_HIGH -#define IO_BANK0_INTR3_GPIO28_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR3_GPIO28_LEVEL_HIGH_BITS _u(0x00020000) -#define IO_BANK0_INTR3_GPIO28_LEVEL_HIGH_MSB _u(17) -#define IO_BANK0_INTR3_GPIO28_LEVEL_HIGH_LSB _u(17) -#define IO_BANK0_INTR3_GPIO28_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR3_GPIO28_LEVEL_LOW -#define IO_BANK0_INTR3_GPIO28_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_INTR3_GPIO28_LEVEL_LOW_BITS _u(0x00010000) -#define IO_BANK0_INTR3_GPIO28_LEVEL_LOW_MSB _u(16) -#define IO_BANK0_INTR3_GPIO28_LEVEL_LOW_LSB _u(16) -#define IO_BANK0_INTR3_GPIO28_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR3_GPIO27_EDGE_HIGH -#define IO_BANK0_INTR3_GPIO27_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR3_GPIO27_EDGE_HIGH_BITS _u(0x00008000) -#define IO_BANK0_INTR3_GPIO27_EDGE_HIGH_MSB _u(15) -#define IO_BANK0_INTR3_GPIO27_EDGE_HIGH_LSB _u(15) -#define IO_BANK0_INTR3_GPIO27_EDGE_HIGH_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR3_GPIO27_EDGE_LOW -#define IO_BANK0_INTR3_GPIO27_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_INTR3_GPIO27_EDGE_LOW_BITS _u(0x00004000) -#define IO_BANK0_INTR3_GPIO27_EDGE_LOW_MSB _u(14) -#define IO_BANK0_INTR3_GPIO27_EDGE_LOW_LSB _u(14) -#define IO_BANK0_INTR3_GPIO27_EDGE_LOW_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR3_GPIO27_LEVEL_HIGH -#define IO_BANK0_INTR3_GPIO27_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR3_GPIO27_LEVEL_HIGH_BITS _u(0x00002000) -#define IO_BANK0_INTR3_GPIO27_LEVEL_HIGH_MSB _u(13) -#define IO_BANK0_INTR3_GPIO27_LEVEL_HIGH_LSB _u(13) -#define IO_BANK0_INTR3_GPIO27_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR3_GPIO27_LEVEL_LOW -#define IO_BANK0_INTR3_GPIO27_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_INTR3_GPIO27_LEVEL_LOW_BITS _u(0x00001000) -#define IO_BANK0_INTR3_GPIO27_LEVEL_LOW_MSB _u(12) -#define IO_BANK0_INTR3_GPIO27_LEVEL_LOW_LSB _u(12) -#define IO_BANK0_INTR3_GPIO27_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR3_GPIO26_EDGE_HIGH -#define IO_BANK0_INTR3_GPIO26_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR3_GPIO26_EDGE_HIGH_BITS _u(0x00000800) -#define IO_BANK0_INTR3_GPIO26_EDGE_HIGH_MSB _u(11) -#define IO_BANK0_INTR3_GPIO26_EDGE_HIGH_LSB _u(11) -#define IO_BANK0_INTR3_GPIO26_EDGE_HIGH_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR3_GPIO26_EDGE_LOW -#define IO_BANK0_INTR3_GPIO26_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_INTR3_GPIO26_EDGE_LOW_BITS _u(0x00000400) -#define IO_BANK0_INTR3_GPIO26_EDGE_LOW_MSB _u(10) -#define IO_BANK0_INTR3_GPIO26_EDGE_LOW_LSB _u(10) -#define IO_BANK0_INTR3_GPIO26_EDGE_LOW_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR3_GPIO26_LEVEL_HIGH -#define IO_BANK0_INTR3_GPIO26_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR3_GPIO26_LEVEL_HIGH_BITS _u(0x00000200) -#define IO_BANK0_INTR3_GPIO26_LEVEL_HIGH_MSB _u(9) -#define IO_BANK0_INTR3_GPIO26_LEVEL_HIGH_LSB _u(9) -#define IO_BANK0_INTR3_GPIO26_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR3_GPIO26_LEVEL_LOW -#define IO_BANK0_INTR3_GPIO26_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_INTR3_GPIO26_LEVEL_LOW_BITS _u(0x00000100) -#define IO_BANK0_INTR3_GPIO26_LEVEL_LOW_MSB _u(8) -#define IO_BANK0_INTR3_GPIO26_LEVEL_LOW_LSB _u(8) -#define IO_BANK0_INTR3_GPIO26_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR3_GPIO25_EDGE_HIGH -#define IO_BANK0_INTR3_GPIO25_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR3_GPIO25_EDGE_HIGH_BITS _u(0x00000080) -#define IO_BANK0_INTR3_GPIO25_EDGE_HIGH_MSB _u(7) -#define IO_BANK0_INTR3_GPIO25_EDGE_HIGH_LSB _u(7) -#define IO_BANK0_INTR3_GPIO25_EDGE_HIGH_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR3_GPIO25_EDGE_LOW -#define IO_BANK0_INTR3_GPIO25_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_INTR3_GPIO25_EDGE_LOW_BITS _u(0x00000040) -#define IO_BANK0_INTR3_GPIO25_EDGE_LOW_MSB _u(6) -#define IO_BANK0_INTR3_GPIO25_EDGE_LOW_LSB _u(6) -#define IO_BANK0_INTR3_GPIO25_EDGE_LOW_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR3_GPIO25_LEVEL_HIGH -#define IO_BANK0_INTR3_GPIO25_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR3_GPIO25_LEVEL_HIGH_BITS _u(0x00000020) -#define IO_BANK0_INTR3_GPIO25_LEVEL_HIGH_MSB _u(5) -#define IO_BANK0_INTR3_GPIO25_LEVEL_HIGH_LSB _u(5) -#define IO_BANK0_INTR3_GPIO25_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR3_GPIO25_LEVEL_LOW -#define IO_BANK0_INTR3_GPIO25_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_INTR3_GPIO25_LEVEL_LOW_BITS _u(0x00000010) -#define IO_BANK0_INTR3_GPIO25_LEVEL_LOW_MSB _u(4) -#define IO_BANK0_INTR3_GPIO25_LEVEL_LOW_LSB _u(4) -#define IO_BANK0_INTR3_GPIO25_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR3_GPIO24_EDGE_HIGH -#define IO_BANK0_INTR3_GPIO24_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR3_GPIO24_EDGE_HIGH_BITS _u(0x00000008) -#define IO_BANK0_INTR3_GPIO24_EDGE_HIGH_MSB _u(3) -#define IO_BANK0_INTR3_GPIO24_EDGE_HIGH_LSB _u(3) -#define IO_BANK0_INTR3_GPIO24_EDGE_HIGH_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR3_GPIO24_EDGE_LOW -#define IO_BANK0_INTR3_GPIO24_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_INTR3_GPIO24_EDGE_LOW_BITS _u(0x00000004) -#define IO_BANK0_INTR3_GPIO24_EDGE_LOW_MSB _u(2) -#define IO_BANK0_INTR3_GPIO24_EDGE_LOW_LSB _u(2) -#define IO_BANK0_INTR3_GPIO24_EDGE_LOW_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR3_GPIO24_LEVEL_HIGH -#define IO_BANK0_INTR3_GPIO24_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR3_GPIO24_LEVEL_HIGH_BITS _u(0x00000002) -#define IO_BANK0_INTR3_GPIO24_LEVEL_HIGH_MSB _u(1) -#define IO_BANK0_INTR3_GPIO24_LEVEL_HIGH_LSB _u(1) -#define IO_BANK0_INTR3_GPIO24_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR3_GPIO24_LEVEL_LOW -#define IO_BANK0_INTR3_GPIO24_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_INTR3_GPIO24_LEVEL_LOW_BITS _u(0x00000001) -#define IO_BANK0_INTR3_GPIO24_LEVEL_LOW_MSB _u(0) -#define IO_BANK0_INTR3_GPIO24_LEVEL_LOW_LSB _u(0) -#define IO_BANK0_INTR3_GPIO24_LEVEL_LOW_ACCESS "RO" -// ============================================================================= -// Register : IO_BANK0_PROC0_INTE0 -// Description : Interrupt Enable for proc0 -#define IO_BANK0_PROC0_INTE0_OFFSET _u(0x00000100) -#define IO_BANK0_PROC0_INTE0_BITS _u(0xffffffff) -#define IO_BANK0_PROC0_INTE0_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE0_GPIO7_EDGE_HIGH -#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_HIGH_BITS _u(0x80000000) -#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_HIGH_MSB _u(31) -#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_HIGH_LSB _u(31) -#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE0_GPIO7_EDGE_LOW -#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_LOW_BITS _u(0x40000000) -#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_LOW_MSB _u(30) -#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_LOW_LSB _u(30) -#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_HIGH -#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_HIGH_BITS _u(0x20000000) -#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_HIGH_MSB _u(29) -#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_HIGH_LSB _u(29) -#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_LOW -#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_LOW_BITS _u(0x10000000) -#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_LOW_MSB _u(28) -#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_LOW_LSB _u(28) -#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE0_GPIO6_EDGE_HIGH -#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_HIGH_BITS _u(0x08000000) -#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_HIGH_MSB _u(27) -#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_HIGH_LSB _u(27) -#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE0_GPIO6_EDGE_LOW -#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_LOW_BITS _u(0x04000000) -#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_LOW_MSB _u(26) -#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_LOW_LSB _u(26) -#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_HIGH -#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_HIGH_BITS _u(0x02000000) -#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_HIGH_MSB _u(25) -#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_HIGH_LSB _u(25) -#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_LOW -#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_LOW_BITS _u(0x01000000) -#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_LOW_MSB _u(24) -#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_LOW_LSB _u(24) -#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE0_GPIO5_EDGE_HIGH -#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_HIGH_BITS _u(0x00800000) -#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_HIGH_MSB _u(23) -#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_HIGH_LSB _u(23) -#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE0_GPIO5_EDGE_LOW -#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_LOW_BITS _u(0x00400000) -#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_LOW_MSB _u(22) -#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_LOW_LSB _u(22) -#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_HIGH -#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_HIGH_BITS _u(0x00200000) -#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_HIGH_MSB _u(21) -#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_HIGH_LSB _u(21) -#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_LOW -#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_LOW_BITS _u(0x00100000) -#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_LOW_MSB _u(20) -#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_LOW_LSB _u(20) -#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE0_GPIO4_EDGE_HIGH -#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_HIGH_BITS _u(0x00080000) -#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_HIGH_MSB _u(19) -#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_HIGH_LSB _u(19) -#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE0_GPIO4_EDGE_LOW -#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_LOW_BITS _u(0x00040000) -#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_LOW_MSB _u(18) -#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_LOW_LSB _u(18) -#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_HIGH -#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_HIGH_BITS _u(0x00020000) -#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_HIGH_MSB _u(17) -#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_HIGH_LSB _u(17) -#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_LOW -#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_LOW_BITS _u(0x00010000) -#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_LOW_MSB _u(16) -#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_LOW_LSB _u(16) -#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE0_GPIO3_EDGE_HIGH -#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_HIGH_BITS _u(0x00008000) -#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_HIGH_MSB _u(15) -#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_HIGH_LSB _u(15) -#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE0_GPIO3_EDGE_LOW -#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_LOW_BITS _u(0x00004000) -#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_LOW_MSB _u(14) -#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_LOW_LSB _u(14) -#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_HIGH -#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_HIGH_BITS _u(0x00002000) -#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_HIGH_MSB _u(13) -#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_HIGH_LSB _u(13) -#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_LOW -#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_LOW_BITS _u(0x00001000) -#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_LOW_MSB _u(12) -#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_LOW_LSB _u(12) -#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE0_GPIO2_EDGE_HIGH -#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_HIGH_BITS _u(0x00000800) -#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_HIGH_MSB _u(11) -#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_HIGH_LSB _u(11) -#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE0_GPIO2_EDGE_LOW -#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_LOW_BITS _u(0x00000400) -#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_LOW_MSB _u(10) -#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_LOW_LSB _u(10) -#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_HIGH -#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_HIGH_BITS _u(0x00000200) -#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_HIGH_MSB _u(9) -#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_HIGH_LSB _u(9) -#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_LOW -#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_LOW_BITS _u(0x00000100) -#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_LOW_MSB _u(8) -#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_LOW_LSB _u(8) -#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE0_GPIO1_EDGE_HIGH -#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_HIGH_BITS _u(0x00000080) -#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_HIGH_MSB _u(7) -#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_HIGH_LSB _u(7) -#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE0_GPIO1_EDGE_LOW -#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_LOW_BITS _u(0x00000040) -#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_LOW_MSB _u(6) -#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_LOW_LSB _u(6) -#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_HIGH -#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_HIGH_BITS _u(0x00000020) -#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_HIGH_MSB _u(5) -#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_HIGH_LSB _u(5) -#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_LOW -#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_LOW_BITS _u(0x00000010) -#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_LOW_MSB _u(4) -#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_LOW_LSB _u(4) -#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE0_GPIO0_EDGE_HIGH -#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_HIGH_BITS _u(0x00000008) -#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_HIGH_MSB _u(3) -#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_HIGH_LSB _u(3) -#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE0_GPIO0_EDGE_LOW -#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_LOW_BITS _u(0x00000004) -#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_LOW_MSB _u(2) -#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_LOW_LSB _u(2) -#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_HIGH -#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_HIGH_BITS _u(0x00000002) -#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_HIGH_MSB _u(1) -#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_HIGH_LSB _u(1) -#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_LOW -#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_LOW_BITS _u(0x00000001) -#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_LOW_MSB _u(0) -#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_LOW_LSB _u(0) -#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_LOW_ACCESS "RW" -// ============================================================================= -// Register : IO_BANK0_PROC0_INTE1 -// Description : Interrupt Enable for proc0 -#define IO_BANK0_PROC0_INTE1_OFFSET _u(0x00000104) -#define IO_BANK0_PROC0_INTE1_BITS _u(0xffffffff) -#define IO_BANK0_PROC0_INTE1_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE1_GPIO15_EDGE_HIGH -#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_HIGH_BITS _u(0x80000000) -#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_HIGH_MSB _u(31) -#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_HIGH_LSB _u(31) -#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE1_GPIO15_EDGE_LOW -#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_LOW_BITS _u(0x40000000) -#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_LOW_MSB _u(30) -#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_LOW_LSB _u(30) -#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_HIGH -#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_HIGH_BITS _u(0x20000000) -#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_HIGH_MSB _u(29) -#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_HIGH_LSB _u(29) -#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_LOW -#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_LOW_BITS _u(0x10000000) -#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_LOW_MSB _u(28) -#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_LOW_LSB _u(28) -#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE1_GPIO14_EDGE_HIGH -#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_HIGH_BITS _u(0x08000000) -#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_HIGH_MSB _u(27) -#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_HIGH_LSB _u(27) -#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE1_GPIO14_EDGE_LOW -#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_LOW_BITS _u(0x04000000) -#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_LOW_MSB _u(26) -#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_LOW_LSB _u(26) -#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_HIGH -#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_HIGH_BITS _u(0x02000000) -#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_HIGH_MSB _u(25) -#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_HIGH_LSB _u(25) -#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_LOW -#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_LOW_BITS _u(0x01000000) -#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_LOW_MSB _u(24) -#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_LOW_LSB _u(24) -#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE1_GPIO13_EDGE_HIGH -#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_HIGH_BITS _u(0x00800000) -#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_HIGH_MSB _u(23) -#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_HIGH_LSB _u(23) -#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE1_GPIO13_EDGE_LOW -#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_LOW_BITS _u(0x00400000) -#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_LOW_MSB _u(22) -#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_LOW_LSB _u(22) -#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_HIGH -#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_HIGH_BITS _u(0x00200000) -#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_HIGH_MSB _u(21) -#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_HIGH_LSB _u(21) -#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_LOW -#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_LOW_BITS _u(0x00100000) -#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_LOW_MSB _u(20) -#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_LOW_LSB _u(20) -#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE1_GPIO12_EDGE_HIGH -#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_HIGH_BITS _u(0x00080000) -#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_HIGH_MSB _u(19) -#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_HIGH_LSB _u(19) -#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE1_GPIO12_EDGE_LOW -#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_LOW_BITS _u(0x00040000) -#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_LOW_MSB _u(18) -#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_LOW_LSB _u(18) -#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_HIGH -#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_HIGH_BITS _u(0x00020000) -#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_HIGH_MSB _u(17) -#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_HIGH_LSB _u(17) -#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_LOW -#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_LOW_BITS _u(0x00010000) -#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_LOW_MSB _u(16) -#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_LOW_LSB _u(16) -#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE1_GPIO11_EDGE_HIGH -#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_HIGH_BITS _u(0x00008000) -#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_HIGH_MSB _u(15) -#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_HIGH_LSB _u(15) -#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE1_GPIO11_EDGE_LOW -#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_LOW_BITS _u(0x00004000) -#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_LOW_MSB _u(14) -#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_LOW_LSB _u(14) -#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_HIGH -#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_HIGH_BITS _u(0x00002000) -#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_HIGH_MSB _u(13) -#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_HIGH_LSB _u(13) -#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_LOW -#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_LOW_BITS _u(0x00001000) -#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_LOW_MSB _u(12) -#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_LOW_LSB _u(12) -#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE1_GPIO10_EDGE_HIGH -#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_HIGH_BITS _u(0x00000800) -#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_HIGH_MSB _u(11) -#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_HIGH_LSB _u(11) -#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE1_GPIO10_EDGE_LOW -#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_LOW_BITS _u(0x00000400) -#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_LOW_MSB _u(10) -#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_LOW_LSB _u(10) -#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_HIGH -#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_HIGH_BITS _u(0x00000200) -#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_HIGH_MSB _u(9) -#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_HIGH_LSB _u(9) -#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_LOW -#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_LOW_BITS _u(0x00000100) -#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_LOW_MSB _u(8) -#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_LOW_LSB _u(8) -#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE1_GPIO9_EDGE_HIGH -#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_HIGH_BITS _u(0x00000080) -#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_HIGH_MSB _u(7) -#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_HIGH_LSB _u(7) -#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE1_GPIO9_EDGE_LOW -#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_LOW_BITS _u(0x00000040) -#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_LOW_MSB _u(6) -#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_LOW_LSB _u(6) -#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_HIGH -#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_HIGH_BITS _u(0x00000020) -#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_HIGH_MSB _u(5) -#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_HIGH_LSB _u(5) -#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_LOW -#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_LOW_BITS _u(0x00000010) -#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_LOW_MSB _u(4) -#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_LOW_LSB _u(4) -#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE1_GPIO8_EDGE_HIGH -#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_HIGH_BITS _u(0x00000008) -#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_HIGH_MSB _u(3) -#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_HIGH_LSB _u(3) -#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE1_GPIO8_EDGE_LOW -#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_LOW_BITS _u(0x00000004) -#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_LOW_MSB _u(2) -#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_LOW_LSB _u(2) -#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_HIGH -#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_HIGH_BITS _u(0x00000002) -#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_HIGH_MSB _u(1) -#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_HIGH_LSB _u(1) -#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_LOW -#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_LOW_BITS _u(0x00000001) -#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_LOW_MSB _u(0) -#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_LOW_LSB _u(0) -#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_LOW_ACCESS "RW" -// ============================================================================= -// Register : IO_BANK0_PROC0_INTE2 -// Description : Interrupt Enable for proc0 -#define IO_BANK0_PROC0_INTE2_OFFSET _u(0x00000108) -#define IO_BANK0_PROC0_INTE2_BITS _u(0xffffffff) -#define IO_BANK0_PROC0_INTE2_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE2_GPIO23_EDGE_HIGH -#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_HIGH_BITS _u(0x80000000) -#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_HIGH_MSB _u(31) -#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_HIGH_LSB _u(31) -#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE2_GPIO23_EDGE_LOW -#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_LOW_BITS _u(0x40000000) -#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_LOW_MSB _u(30) -#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_LOW_LSB _u(30) -#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_HIGH -#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_HIGH_BITS _u(0x20000000) -#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_HIGH_MSB _u(29) -#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_HIGH_LSB _u(29) -#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_LOW -#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_LOW_BITS _u(0x10000000) -#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_LOW_MSB _u(28) -#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_LOW_LSB _u(28) -#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE2_GPIO22_EDGE_HIGH -#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_HIGH_BITS _u(0x08000000) -#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_HIGH_MSB _u(27) -#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_HIGH_LSB _u(27) -#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE2_GPIO22_EDGE_LOW -#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_LOW_BITS _u(0x04000000) -#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_LOW_MSB _u(26) -#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_LOW_LSB _u(26) -#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_HIGH -#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_HIGH_BITS _u(0x02000000) -#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_HIGH_MSB _u(25) -#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_HIGH_LSB _u(25) -#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_LOW -#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_LOW_BITS _u(0x01000000) -#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_LOW_MSB _u(24) -#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_LOW_LSB _u(24) -#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE2_GPIO21_EDGE_HIGH -#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_HIGH_BITS _u(0x00800000) -#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_HIGH_MSB _u(23) -#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_HIGH_LSB _u(23) -#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE2_GPIO21_EDGE_LOW -#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_LOW_BITS _u(0x00400000) -#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_LOW_MSB _u(22) -#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_LOW_LSB _u(22) -#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_HIGH -#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_HIGH_BITS _u(0x00200000) -#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_HIGH_MSB _u(21) -#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_HIGH_LSB _u(21) -#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_LOW -#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_LOW_BITS _u(0x00100000) -#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_LOW_MSB _u(20) -#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_LOW_LSB _u(20) -#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE2_GPIO20_EDGE_HIGH -#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_HIGH_BITS _u(0x00080000) -#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_HIGH_MSB _u(19) -#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_HIGH_LSB _u(19) -#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE2_GPIO20_EDGE_LOW -#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_LOW_BITS _u(0x00040000) -#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_LOW_MSB _u(18) -#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_LOW_LSB _u(18) -#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_HIGH -#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_HIGH_BITS _u(0x00020000) -#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_HIGH_MSB _u(17) -#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_HIGH_LSB _u(17) -#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_LOW -#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_LOW_BITS _u(0x00010000) -#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_LOW_MSB _u(16) -#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_LOW_LSB _u(16) -#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE2_GPIO19_EDGE_HIGH -#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_HIGH_BITS _u(0x00008000) -#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_HIGH_MSB _u(15) -#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_HIGH_LSB _u(15) -#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE2_GPIO19_EDGE_LOW -#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_LOW_BITS _u(0x00004000) -#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_LOW_MSB _u(14) -#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_LOW_LSB _u(14) -#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_HIGH -#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_HIGH_BITS _u(0x00002000) -#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_HIGH_MSB _u(13) -#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_HIGH_LSB _u(13) -#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_LOW -#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_LOW_BITS _u(0x00001000) -#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_LOW_MSB _u(12) -#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_LOW_LSB _u(12) -#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE2_GPIO18_EDGE_HIGH -#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_HIGH_BITS _u(0x00000800) -#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_HIGH_MSB _u(11) -#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_HIGH_LSB _u(11) -#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE2_GPIO18_EDGE_LOW -#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_LOW_BITS _u(0x00000400) -#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_LOW_MSB _u(10) -#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_LOW_LSB _u(10) -#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_HIGH -#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_HIGH_BITS _u(0x00000200) -#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_HIGH_MSB _u(9) -#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_HIGH_LSB _u(9) -#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_LOW -#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_LOW_BITS _u(0x00000100) -#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_LOW_MSB _u(8) -#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_LOW_LSB _u(8) -#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE2_GPIO17_EDGE_HIGH -#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_HIGH_BITS _u(0x00000080) -#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_HIGH_MSB _u(7) -#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_HIGH_LSB _u(7) -#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE2_GPIO17_EDGE_LOW -#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_LOW_BITS _u(0x00000040) -#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_LOW_MSB _u(6) -#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_LOW_LSB _u(6) -#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_HIGH -#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_HIGH_BITS _u(0x00000020) -#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_HIGH_MSB _u(5) -#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_HIGH_LSB _u(5) -#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_LOW -#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_LOW_BITS _u(0x00000010) -#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_LOW_MSB _u(4) -#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_LOW_LSB _u(4) -#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE2_GPIO16_EDGE_HIGH -#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_HIGH_BITS _u(0x00000008) -#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_HIGH_MSB _u(3) -#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_HIGH_LSB _u(3) -#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE2_GPIO16_EDGE_LOW -#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_LOW_BITS _u(0x00000004) -#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_LOW_MSB _u(2) -#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_LOW_LSB _u(2) -#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_HIGH -#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_HIGH_BITS _u(0x00000002) -#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_HIGH_MSB _u(1) -#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_HIGH_LSB _u(1) -#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_LOW -#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_LOW_BITS _u(0x00000001) -#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_LOW_MSB _u(0) -#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_LOW_LSB _u(0) -#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_LOW_ACCESS "RW" -// ============================================================================= -// Register : IO_BANK0_PROC0_INTE3 -// Description : Interrupt Enable for proc0 -#define IO_BANK0_PROC0_INTE3_OFFSET _u(0x0000010c) -#define IO_BANK0_PROC0_INTE3_BITS _u(0x00ffffff) -#define IO_BANK0_PROC0_INTE3_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE3_GPIO29_EDGE_HIGH -#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_HIGH_BITS _u(0x00800000) -#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_HIGH_MSB _u(23) -#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_HIGH_LSB _u(23) -#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE3_GPIO29_EDGE_LOW -#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_LOW_BITS _u(0x00400000) -#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_LOW_MSB _u(22) -#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_LOW_LSB _u(22) -#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_HIGH -#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_HIGH_BITS _u(0x00200000) -#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_HIGH_MSB _u(21) -#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_HIGH_LSB _u(21) -#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_LOW -#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_LOW_BITS _u(0x00100000) -#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_LOW_MSB _u(20) -#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_LOW_LSB _u(20) -#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE3_GPIO28_EDGE_HIGH -#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_HIGH_BITS _u(0x00080000) -#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_HIGH_MSB _u(19) -#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_HIGH_LSB _u(19) -#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE3_GPIO28_EDGE_LOW -#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_LOW_BITS _u(0x00040000) -#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_LOW_MSB _u(18) -#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_LOW_LSB _u(18) -#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_HIGH -#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_HIGH_BITS _u(0x00020000) -#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_HIGH_MSB _u(17) -#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_HIGH_LSB _u(17) -#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_LOW -#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_LOW_BITS _u(0x00010000) -#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_LOW_MSB _u(16) -#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_LOW_LSB _u(16) -#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE3_GPIO27_EDGE_HIGH -#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_HIGH_BITS _u(0x00008000) -#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_HIGH_MSB _u(15) -#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_HIGH_LSB _u(15) -#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE3_GPIO27_EDGE_LOW -#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_LOW_BITS _u(0x00004000) -#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_LOW_MSB _u(14) -#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_LOW_LSB _u(14) -#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_HIGH -#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_HIGH_BITS _u(0x00002000) -#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_HIGH_MSB _u(13) -#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_HIGH_LSB _u(13) -#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_LOW -#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_LOW_BITS _u(0x00001000) -#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_LOW_MSB _u(12) -#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_LOW_LSB _u(12) -#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE3_GPIO26_EDGE_HIGH -#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_HIGH_BITS _u(0x00000800) -#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_HIGH_MSB _u(11) -#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_HIGH_LSB _u(11) -#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE3_GPIO26_EDGE_LOW -#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_LOW_BITS _u(0x00000400) -#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_LOW_MSB _u(10) -#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_LOW_LSB _u(10) -#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_HIGH -#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_HIGH_BITS _u(0x00000200) -#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_HIGH_MSB _u(9) -#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_HIGH_LSB _u(9) -#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_LOW -#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_LOW_BITS _u(0x00000100) -#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_LOW_MSB _u(8) -#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_LOW_LSB _u(8) -#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE3_GPIO25_EDGE_HIGH -#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_HIGH_BITS _u(0x00000080) -#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_HIGH_MSB _u(7) -#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_HIGH_LSB _u(7) -#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE3_GPIO25_EDGE_LOW -#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_LOW_BITS _u(0x00000040) -#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_LOW_MSB _u(6) -#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_LOW_LSB _u(6) -#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_HIGH -#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_HIGH_BITS _u(0x00000020) -#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_HIGH_MSB _u(5) -#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_HIGH_LSB _u(5) -#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_LOW -#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_LOW_BITS _u(0x00000010) -#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_LOW_MSB _u(4) -#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_LOW_LSB _u(4) -#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE3_GPIO24_EDGE_HIGH -#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_HIGH_BITS _u(0x00000008) -#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_HIGH_MSB _u(3) -#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_HIGH_LSB _u(3) -#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE3_GPIO24_EDGE_LOW -#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_LOW_BITS _u(0x00000004) -#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_LOW_MSB _u(2) -#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_LOW_LSB _u(2) -#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_HIGH -#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_HIGH_BITS _u(0x00000002) -#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_HIGH_MSB _u(1) -#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_HIGH_LSB _u(1) -#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_LOW -#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_LOW_BITS _u(0x00000001) -#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_LOW_MSB _u(0) -#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_LOW_LSB _u(0) -#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_LOW_ACCESS "RW" -// ============================================================================= -// Register : IO_BANK0_PROC0_INTF0 -// Description : Interrupt Force for proc0 -#define IO_BANK0_PROC0_INTF0_OFFSET _u(0x00000110) -#define IO_BANK0_PROC0_INTF0_BITS _u(0xffffffff) -#define IO_BANK0_PROC0_INTF0_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF0_GPIO7_EDGE_HIGH -#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_HIGH_BITS _u(0x80000000) -#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_HIGH_MSB _u(31) -#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_HIGH_LSB _u(31) -#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF0_GPIO7_EDGE_LOW -#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_LOW_BITS _u(0x40000000) -#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_LOW_MSB _u(30) -#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_LOW_LSB _u(30) -#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_HIGH -#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_HIGH_BITS _u(0x20000000) -#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_HIGH_MSB _u(29) -#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_HIGH_LSB _u(29) -#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_LOW -#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_LOW_BITS _u(0x10000000) -#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_LOW_MSB _u(28) -#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_LOW_LSB _u(28) -#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF0_GPIO6_EDGE_HIGH -#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_HIGH_BITS _u(0x08000000) -#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_HIGH_MSB _u(27) -#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_HIGH_LSB _u(27) -#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF0_GPIO6_EDGE_LOW -#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_LOW_BITS _u(0x04000000) -#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_LOW_MSB _u(26) -#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_LOW_LSB _u(26) -#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_HIGH -#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_HIGH_BITS _u(0x02000000) -#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_HIGH_MSB _u(25) -#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_HIGH_LSB _u(25) -#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_LOW -#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_LOW_BITS _u(0x01000000) -#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_LOW_MSB _u(24) -#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_LOW_LSB _u(24) -#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF0_GPIO5_EDGE_HIGH -#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_HIGH_BITS _u(0x00800000) -#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_HIGH_MSB _u(23) -#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_HIGH_LSB _u(23) -#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF0_GPIO5_EDGE_LOW -#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_LOW_BITS _u(0x00400000) -#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_LOW_MSB _u(22) -#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_LOW_LSB _u(22) -#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_HIGH -#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_HIGH_BITS _u(0x00200000) -#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_HIGH_MSB _u(21) -#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_HIGH_LSB _u(21) -#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_LOW -#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_LOW_BITS _u(0x00100000) -#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_LOW_MSB _u(20) -#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_LOW_LSB _u(20) -#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF0_GPIO4_EDGE_HIGH -#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_HIGH_BITS _u(0x00080000) -#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_HIGH_MSB _u(19) -#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_HIGH_LSB _u(19) -#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF0_GPIO4_EDGE_LOW -#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_LOW_BITS _u(0x00040000) -#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_LOW_MSB _u(18) -#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_LOW_LSB _u(18) -#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_HIGH -#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_HIGH_BITS _u(0x00020000) -#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_HIGH_MSB _u(17) -#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_HIGH_LSB _u(17) -#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_LOW -#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_LOW_BITS _u(0x00010000) -#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_LOW_MSB _u(16) -#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_LOW_LSB _u(16) -#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF0_GPIO3_EDGE_HIGH -#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_HIGH_BITS _u(0x00008000) -#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_HIGH_MSB _u(15) -#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_HIGH_LSB _u(15) -#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF0_GPIO3_EDGE_LOW -#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_LOW_BITS _u(0x00004000) -#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_LOW_MSB _u(14) -#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_LOW_LSB _u(14) -#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_HIGH -#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_HIGH_BITS _u(0x00002000) -#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_HIGH_MSB _u(13) -#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_HIGH_LSB _u(13) -#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_LOW -#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_LOW_BITS _u(0x00001000) -#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_LOW_MSB _u(12) -#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_LOW_LSB _u(12) -#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF0_GPIO2_EDGE_HIGH -#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_HIGH_BITS _u(0x00000800) -#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_HIGH_MSB _u(11) -#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_HIGH_LSB _u(11) -#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF0_GPIO2_EDGE_LOW -#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_LOW_BITS _u(0x00000400) -#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_LOW_MSB _u(10) -#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_LOW_LSB _u(10) -#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_HIGH -#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_HIGH_BITS _u(0x00000200) -#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_HIGH_MSB _u(9) -#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_HIGH_LSB _u(9) -#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_LOW -#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_LOW_BITS _u(0x00000100) -#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_LOW_MSB _u(8) -#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_LOW_LSB _u(8) -#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF0_GPIO1_EDGE_HIGH -#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_HIGH_BITS _u(0x00000080) -#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_HIGH_MSB _u(7) -#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_HIGH_LSB _u(7) -#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF0_GPIO1_EDGE_LOW -#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_LOW_BITS _u(0x00000040) -#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_LOW_MSB _u(6) -#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_LOW_LSB _u(6) -#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_HIGH -#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_HIGH_BITS _u(0x00000020) -#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_HIGH_MSB _u(5) -#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_HIGH_LSB _u(5) -#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_LOW -#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_LOW_BITS _u(0x00000010) -#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_LOW_MSB _u(4) -#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_LOW_LSB _u(4) -#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF0_GPIO0_EDGE_HIGH -#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_HIGH_BITS _u(0x00000008) -#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_HIGH_MSB _u(3) -#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_HIGH_LSB _u(3) -#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF0_GPIO0_EDGE_LOW -#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_LOW_BITS _u(0x00000004) -#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_LOW_MSB _u(2) -#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_LOW_LSB _u(2) -#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_HIGH -#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_HIGH_BITS _u(0x00000002) -#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_HIGH_MSB _u(1) -#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_HIGH_LSB _u(1) -#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_LOW -#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_LOW_BITS _u(0x00000001) -#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_LOW_MSB _u(0) -#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_LOW_LSB _u(0) -#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_LOW_ACCESS "RW" -// ============================================================================= -// Register : IO_BANK0_PROC0_INTF1 -// Description : Interrupt Force for proc0 -#define IO_BANK0_PROC0_INTF1_OFFSET _u(0x00000114) -#define IO_BANK0_PROC0_INTF1_BITS _u(0xffffffff) -#define IO_BANK0_PROC0_INTF1_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF1_GPIO15_EDGE_HIGH -#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_HIGH_BITS _u(0x80000000) -#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_HIGH_MSB _u(31) -#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_HIGH_LSB _u(31) -#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF1_GPIO15_EDGE_LOW -#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_LOW_BITS _u(0x40000000) -#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_LOW_MSB _u(30) -#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_LOW_LSB _u(30) -#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_HIGH -#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_HIGH_BITS _u(0x20000000) -#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_HIGH_MSB _u(29) -#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_HIGH_LSB _u(29) -#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_LOW -#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_LOW_BITS _u(0x10000000) -#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_LOW_MSB _u(28) -#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_LOW_LSB _u(28) -#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF1_GPIO14_EDGE_HIGH -#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_HIGH_BITS _u(0x08000000) -#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_HIGH_MSB _u(27) -#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_HIGH_LSB _u(27) -#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF1_GPIO14_EDGE_LOW -#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_LOW_BITS _u(0x04000000) -#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_LOW_MSB _u(26) -#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_LOW_LSB _u(26) -#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_HIGH -#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_HIGH_BITS _u(0x02000000) -#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_HIGH_MSB _u(25) -#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_HIGH_LSB _u(25) -#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_LOW -#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_LOW_BITS _u(0x01000000) -#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_LOW_MSB _u(24) -#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_LOW_LSB _u(24) -#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF1_GPIO13_EDGE_HIGH -#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_HIGH_BITS _u(0x00800000) -#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_HIGH_MSB _u(23) -#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_HIGH_LSB _u(23) -#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF1_GPIO13_EDGE_LOW -#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_LOW_BITS _u(0x00400000) -#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_LOW_MSB _u(22) -#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_LOW_LSB _u(22) -#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_HIGH -#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_HIGH_BITS _u(0x00200000) -#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_HIGH_MSB _u(21) -#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_HIGH_LSB _u(21) -#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_LOW -#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_LOW_BITS _u(0x00100000) -#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_LOW_MSB _u(20) -#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_LOW_LSB _u(20) -#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF1_GPIO12_EDGE_HIGH -#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_HIGH_BITS _u(0x00080000) -#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_HIGH_MSB _u(19) -#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_HIGH_LSB _u(19) -#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF1_GPIO12_EDGE_LOW -#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_LOW_BITS _u(0x00040000) -#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_LOW_MSB _u(18) -#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_LOW_LSB _u(18) -#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_HIGH -#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_HIGH_BITS _u(0x00020000) -#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_HIGH_MSB _u(17) -#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_HIGH_LSB _u(17) -#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_LOW -#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_LOW_BITS _u(0x00010000) -#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_LOW_MSB _u(16) -#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_LOW_LSB _u(16) -#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF1_GPIO11_EDGE_HIGH -#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_HIGH_BITS _u(0x00008000) -#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_HIGH_MSB _u(15) -#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_HIGH_LSB _u(15) -#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF1_GPIO11_EDGE_LOW -#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_LOW_BITS _u(0x00004000) -#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_LOW_MSB _u(14) -#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_LOW_LSB _u(14) -#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_HIGH -#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_HIGH_BITS _u(0x00002000) -#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_HIGH_MSB _u(13) -#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_HIGH_LSB _u(13) -#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_LOW -#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_LOW_BITS _u(0x00001000) -#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_LOW_MSB _u(12) -#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_LOW_LSB _u(12) -#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF1_GPIO10_EDGE_HIGH -#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_HIGH_BITS _u(0x00000800) -#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_HIGH_MSB _u(11) -#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_HIGH_LSB _u(11) -#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF1_GPIO10_EDGE_LOW -#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_LOW_BITS _u(0x00000400) -#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_LOW_MSB _u(10) -#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_LOW_LSB _u(10) -#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_HIGH -#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_HIGH_BITS _u(0x00000200) -#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_HIGH_MSB _u(9) -#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_HIGH_LSB _u(9) -#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_LOW -#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_LOW_BITS _u(0x00000100) -#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_LOW_MSB _u(8) -#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_LOW_LSB _u(8) -#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF1_GPIO9_EDGE_HIGH -#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_HIGH_BITS _u(0x00000080) -#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_HIGH_MSB _u(7) -#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_HIGH_LSB _u(7) -#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF1_GPIO9_EDGE_LOW -#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_LOW_BITS _u(0x00000040) -#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_LOW_MSB _u(6) -#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_LOW_LSB _u(6) -#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_HIGH -#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_HIGH_BITS _u(0x00000020) -#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_HIGH_MSB _u(5) -#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_HIGH_LSB _u(5) -#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_LOW -#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_LOW_BITS _u(0x00000010) -#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_LOW_MSB _u(4) -#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_LOW_LSB _u(4) -#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF1_GPIO8_EDGE_HIGH -#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_HIGH_BITS _u(0x00000008) -#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_HIGH_MSB _u(3) -#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_HIGH_LSB _u(3) -#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF1_GPIO8_EDGE_LOW -#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_LOW_BITS _u(0x00000004) -#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_LOW_MSB _u(2) -#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_LOW_LSB _u(2) -#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_HIGH -#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_HIGH_BITS _u(0x00000002) -#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_HIGH_MSB _u(1) -#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_HIGH_LSB _u(1) -#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_LOW -#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_LOW_BITS _u(0x00000001) -#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_LOW_MSB _u(0) -#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_LOW_LSB _u(0) -#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_LOW_ACCESS "RW" -// ============================================================================= -// Register : IO_BANK0_PROC0_INTF2 -// Description : Interrupt Force for proc0 -#define IO_BANK0_PROC0_INTF2_OFFSET _u(0x00000118) -#define IO_BANK0_PROC0_INTF2_BITS _u(0xffffffff) -#define IO_BANK0_PROC0_INTF2_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF2_GPIO23_EDGE_HIGH -#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_HIGH_BITS _u(0x80000000) -#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_HIGH_MSB _u(31) -#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_HIGH_LSB _u(31) -#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF2_GPIO23_EDGE_LOW -#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_LOW_BITS _u(0x40000000) -#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_LOW_MSB _u(30) -#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_LOW_LSB _u(30) -#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_HIGH -#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_HIGH_BITS _u(0x20000000) -#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_HIGH_MSB _u(29) -#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_HIGH_LSB _u(29) -#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_LOW -#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_LOW_BITS _u(0x10000000) -#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_LOW_MSB _u(28) -#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_LOW_LSB _u(28) -#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF2_GPIO22_EDGE_HIGH -#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_HIGH_BITS _u(0x08000000) -#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_HIGH_MSB _u(27) -#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_HIGH_LSB _u(27) -#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF2_GPIO22_EDGE_LOW -#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_LOW_BITS _u(0x04000000) -#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_LOW_MSB _u(26) -#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_LOW_LSB _u(26) -#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_HIGH -#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_HIGH_BITS _u(0x02000000) -#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_HIGH_MSB _u(25) -#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_HIGH_LSB _u(25) -#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_LOW -#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_LOW_BITS _u(0x01000000) -#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_LOW_MSB _u(24) -#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_LOW_LSB _u(24) -#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF2_GPIO21_EDGE_HIGH -#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_HIGH_BITS _u(0x00800000) -#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_HIGH_MSB _u(23) -#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_HIGH_LSB _u(23) -#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF2_GPIO21_EDGE_LOW -#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_LOW_BITS _u(0x00400000) -#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_LOW_MSB _u(22) -#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_LOW_LSB _u(22) -#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_HIGH -#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_HIGH_BITS _u(0x00200000) -#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_HIGH_MSB _u(21) -#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_HIGH_LSB _u(21) -#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_LOW -#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_LOW_BITS _u(0x00100000) -#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_LOW_MSB _u(20) -#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_LOW_LSB _u(20) -#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF2_GPIO20_EDGE_HIGH -#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_HIGH_BITS _u(0x00080000) -#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_HIGH_MSB _u(19) -#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_HIGH_LSB _u(19) -#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF2_GPIO20_EDGE_LOW -#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_LOW_BITS _u(0x00040000) -#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_LOW_MSB _u(18) -#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_LOW_LSB _u(18) -#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_HIGH -#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_HIGH_BITS _u(0x00020000) -#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_HIGH_MSB _u(17) -#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_HIGH_LSB _u(17) -#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_LOW -#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_LOW_BITS _u(0x00010000) -#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_LOW_MSB _u(16) -#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_LOW_LSB _u(16) -#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF2_GPIO19_EDGE_HIGH -#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_HIGH_BITS _u(0x00008000) -#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_HIGH_MSB _u(15) -#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_HIGH_LSB _u(15) -#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF2_GPIO19_EDGE_LOW -#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_LOW_BITS _u(0x00004000) -#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_LOW_MSB _u(14) -#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_LOW_LSB _u(14) -#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_HIGH -#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_HIGH_BITS _u(0x00002000) -#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_HIGH_MSB _u(13) -#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_HIGH_LSB _u(13) -#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_LOW -#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_LOW_BITS _u(0x00001000) -#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_LOW_MSB _u(12) -#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_LOW_LSB _u(12) -#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF2_GPIO18_EDGE_HIGH -#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_HIGH_BITS _u(0x00000800) -#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_HIGH_MSB _u(11) -#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_HIGH_LSB _u(11) -#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF2_GPIO18_EDGE_LOW -#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_LOW_BITS _u(0x00000400) -#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_LOW_MSB _u(10) -#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_LOW_LSB _u(10) -#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_HIGH -#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_HIGH_BITS _u(0x00000200) -#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_HIGH_MSB _u(9) -#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_HIGH_LSB _u(9) -#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_LOW -#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_LOW_BITS _u(0x00000100) -#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_LOW_MSB _u(8) -#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_LOW_LSB _u(8) -#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF2_GPIO17_EDGE_HIGH -#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_HIGH_BITS _u(0x00000080) -#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_HIGH_MSB _u(7) -#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_HIGH_LSB _u(7) -#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF2_GPIO17_EDGE_LOW -#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_LOW_BITS _u(0x00000040) -#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_LOW_MSB _u(6) -#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_LOW_LSB _u(6) -#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_HIGH -#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_HIGH_BITS _u(0x00000020) -#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_HIGH_MSB _u(5) -#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_HIGH_LSB _u(5) -#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_LOW -#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_LOW_BITS _u(0x00000010) -#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_LOW_MSB _u(4) -#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_LOW_LSB _u(4) -#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF2_GPIO16_EDGE_HIGH -#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_HIGH_BITS _u(0x00000008) -#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_HIGH_MSB _u(3) -#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_HIGH_LSB _u(3) -#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF2_GPIO16_EDGE_LOW -#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_LOW_BITS _u(0x00000004) -#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_LOW_MSB _u(2) -#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_LOW_LSB _u(2) -#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_HIGH -#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_HIGH_BITS _u(0x00000002) -#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_HIGH_MSB _u(1) -#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_HIGH_LSB _u(1) -#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_LOW -#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_LOW_BITS _u(0x00000001) -#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_LOW_MSB _u(0) -#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_LOW_LSB _u(0) -#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_LOW_ACCESS "RW" -// ============================================================================= -// Register : IO_BANK0_PROC0_INTF3 -// Description : Interrupt Force for proc0 -#define IO_BANK0_PROC0_INTF3_OFFSET _u(0x0000011c) -#define IO_BANK0_PROC0_INTF3_BITS _u(0x00ffffff) -#define IO_BANK0_PROC0_INTF3_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF3_GPIO29_EDGE_HIGH -#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_HIGH_BITS _u(0x00800000) -#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_HIGH_MSB _u(23) -#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_HIGH_LSB _u(23) -#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF3_GPIO29_EDGE_LOW -#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_LOW_BITS _u(0x00400000) -#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_LOW_MSB _u(22) -#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_LOW_LSB _u(22) -#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_HIGH -#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_HIGH_BITS _u(0x00200000) -#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_HIGH_MSB _u(21) -#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_HIGH_LSB _u(21) -#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_LOW -#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_LOW_BITS _u(0x00100000) -#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_LOW_MSB _u(20) -#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_LOW_LSB _u(20) -#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF3_GPIO28_EDGE_HIGH -#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_HIGH_BITS _u(0x00080000) -#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_HIGH_MSB _u(19) -#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_HIGH_LSB _u(19) -#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF3_GPIO28_EDGE_LOW -#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_LOW_BITS _u(0x00040000) -#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_LOW_MSB _u(18) -#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_LOW_LSB _u(18) -#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_HIGH -#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_HIGH_BITS _u(0x00020000) -#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_HIGH_MSB _u(17) -#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_HIGH_LSB _u(17) -#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_LOW -#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_LOW_BITS _u(0x00010000) -#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_LOW_MSB _u(16) -#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_LOW_LSB _u(16) -#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF3_GPIO27_EDGE_HIGH -#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_HIGH_BITS _u(0x00008000) -#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_HIGH_MSB _u(15) -#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_HIGH_LSB _u(15) -#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF3_GPIO27_EDGE_LOW -#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_LOW_BITS _u(0x00004000) -#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_LOW_MSB _u(14) -#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_LOW_LSB _u(14) -#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_HIGH -#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_HIGH_BITS _u(0x00002000) -#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_HIGH_MSB _u(13) -#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_HIGH_LSB _u(13) -#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_LOW -#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_LOW_BITS _u(0x00001000) -#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_LOW_MSB _u(12) -#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_LOW_LSB _u(12) -#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF3_GPIO26_EDGE_HIGH -#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_HIGH_BITS _u(0x00000800) -#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_HIGH_MSB _u(11) -#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_HIGH_LSB _u(11) -#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF3_GPIO26_EDGE_LOW -#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_LOW_BITS _u(0x00000400) -#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_LOW_MSB _u(10) -#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_LOW_LSB _u(10) -#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_HIGH -#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_HIGH_BITS _u(0x00000200) -#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_HIGH_MSB _u(9) -#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_HIGH_LSB _u(9) -#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_LOW -#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_LOW_BITS _u(0x00000100) -#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_LOW_MSB _u(8) -#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_LOW_LSB _u(8) -#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF3_GPIO25_EDGE_HIGH -#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_HIGH_BITS _u(0x00000080) -#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_HIGH_MSB _u(7) -#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_HIGH_LSB _u(7) -#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF3_GPIO25_EDGE_LOW -#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_LOW_BITS _u(0x00000040) -#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_LOW_MSB _u(6) -#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_LOW_LSB _u(6) -#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_HIGH -#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_HIGH_BITS _u(0x00000020) -#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_HIGH_MSB _u(5) -#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_HIGH_LSB _u(5) -#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_LOW -#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_LOW_BITS _u(0x00000010) -#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_LOW_MSB _u(4) -#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_LOW_LSB _u(4) -#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF3_GPIO24_EDGE_HIGH -#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_HIGH_BITS _u(0x00000008) -#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_HIGH_MSB _u(3) -#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_HIGH_LSB _u(3) -#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF3_GPIO24_EDGE_LOW -#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_LOW_BITS _u(0x00000004) -#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_LOW_MSB _u(2) -#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_LOW_LSB _u(2) -#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_HIGH -#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_HIGH_BITS _u(0x00000002) -#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_HIGH_MSB _u(1) -#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_HIGH_LSB _u(1) -#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_LOW -#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_LOW_BITS _u(0x00000001) -#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_LOW_MSB _u(0) -#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_LOW_LSB _u(0) -#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_LOW_ACCESS "RW" -// ============================================================================= -// Register : IO_BANK0_PROC0_INTS0 -// Description : Interrupt status after masking & forcing for proc0 -#define IO_BANK0_PROC0_INTS0_OFFSET _u(0x00000120) -#define IO_BANK0_PROC0_INTS0_BITS _u(0xffffffff) -#define IO_BANK0_PROC0_INTS0_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS0_GPIO7_EDGE_HIGH -#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_HIGH_BITS _u(0x80000000) -#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_HIGH_MSB _u(31) -#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_HIGH_LSB _u(31) -#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS0_GPIO7_EDGE_LOW -#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_LOW_BITS _u(0x40000000) -#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_LOW_MSB _u(30) -#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_LOW_LSB _u(30) -#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_HIGH -#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_HIGH_BITS _u(0x20000000) -#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_HIGH_MSB _u(29) -#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_HIGH_LSB _u(29) -#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_LOW -#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_LOW_BITS _u(0x10000000) -#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_LOW_MSB _u(28) -#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_LOW_LSB _u(28) -#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS0_GPIO6_EDGE_HIGH -#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_HIGH_BITS _u(0x08000000) -#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_HIGH_MSB _u(27) -#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_HIGH_LSB _u(27) -#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS0_GPIO6_EDGE_LOW -#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_LOW_BITS _u(0x04000000) -#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_LOW_MSB _u(26) -#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_LOW_LSB _u(26) -#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_HIGH -#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_HIGH_BITS _u(0x02000000) -#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_HIGH_MSB _u(25) -#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_HIGH_LSB _u(25) -#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_LOW -#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_LOW_BITS _u(0x01000000) -#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_LOW_MSB _u(24) -#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_LOW_LSB _u(24) -#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS0_GPIO5_EDGE_HIGH -#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_HIGH_BITS _u(0x00800000) -#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_HIGH_MSB _u(23) -#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_HIGH_LSB _u(23) -#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS0_GPIO5_EDGE_LOW -#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_LOW_BITS _u(0x00400000) -#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_LOW_MSB _u(22) -#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_LOW_LSB _u(22) -#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_HIGH -#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_HIGH_BITS _u(0x00200000) -#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_HIGH_MSB _u(21) -#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_HIGH_LSB _u(21) -#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_LOW -#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_LOW_BITS _u(0x00100000) -#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_LOW_MSB _u(20) -#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_LOW_LSB _u(20) -#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS0_GPIO4_EDGE_HIGH -#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_HIGH_BITS _u(0x00080000) -#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_HIGH_MSB _u(19) -#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_HIGH_LSB _u(19) -#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS0_GPIO4_EDGE_LOW -#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_LOW_BITS _u(0x00040000) -#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_LOW_MSB _u(18) -#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_LOW_LSB _u(18) -#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_HIGH -#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_HIGH_BITS _u(0x00020000) -#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_HIGH_MSB _u(17) -#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_HIGH_LSB _u(17) -#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_LOW -#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_LOW_BITS _u(0x00010000) -#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_LOW_MSB _u(16) -#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_LOW_LSB _u(16) -#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS0_GPIO3_EDGE_HIGH -#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_HIGH_BITS _u(0x00008000) -#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_HIGH_MSB _u(15) -#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_HIGH_LSB _u(15) -#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS0_GPIO3_EDGE_LOW -#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_LOW_BITS _u(0x00004000) -#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_LOW_MSB _u(14) -#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_LOW_LSB _u(14) -#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_HIGH -#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_HIGH_BITS _u(0x00002000) -#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_HIGH_MSB _u(13) -#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_HIGH_LSB _u(13) -#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_LOW -#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_LOW_BITS _u(0x00001000) -#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_LOW_MSB _u(12) -#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_LOW_LSB _u(12) -#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS0_GPIO2_EDGE_HIGH -#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_HIGH_BITS _u(0x00000800) -#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_HIGH_MSB _u(11) -#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_HIGH_LSB _u(11) -#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS0_GPIO2_EDGE_LOW -#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_LOW_BITS _u(0x00000400) -#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_LOW_MSB _u(10) -#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_LOW_LSB _u(10) -#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_HIGH -#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_HIGH_BITS _u(0x00000200) -#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_HIGH_MSB _u(9) -#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_HIGH_LSB _u(9) -#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_LOW -#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_LOW_BITS _u(0x00000100) -#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_LOW_MSB _u(8) -#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_LOW_LSB _u(8) -#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS0_GPIO1_EDGE_HIGH -#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_HIGH_BITS _u(0x00000080) -#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_HIGH_MSB _u(7) -#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_HIGH_LSB _u(7) -#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS0_GPIO1_EDGE_LOW -#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_LOW_BITS _u(0x00000040) -#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_LOW_MSB _u(6) -#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_LOW_LSB _u(6) -#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_HIGH -#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_HIGH_BITS _u(0x00000020) -#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_HIGH_MSB _u(5) -#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_HIGH_LSB _u(5) -#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_LOW -#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_LOW_BITS _u(0x00000010) -#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_LOW_MSB _u(4) -#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_LOW_LSB _u(4) -#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS0_GPIO0_EDGE_HIGH -#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_HIGH_BITS _u(0x00000008) -#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_HIGH_MSB _u(3) -#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_HIGH_LSB _u(3) -#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS0_GPIO0_EDGE_LOW -#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_LOW_BITS _u(0x00000004) -#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_LOW_MSB _u(2) -#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_LOW_LSB _u(2) -#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_HIGH -#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_HIGH_BITS _u(0x00000002) -#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_HIGH_MSB _u(1) -#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_HIGH_LSB _u(1) -#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_LOW -#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_LOW_BITS _u(0x00000001) -#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_LOW_MSB _u(0) -#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_LOW_LSB _u(0) -#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_LOW_ACCESS "RO" -// ============================================================================= -// Register : IO_BANK0_PROC0_INTS1 -// Description : Interrupt status after masking & forcing for proc0 -#define IO_BANK0_PROC0_INTS1_OFFSET _u(0x00000124) -#define IO_BANK0_PROC0_INTS1_BITS _u(0xffffffff) -#define IO_BANK0_PROC0_INTS1_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS1_GPIO15_EDGE_HIGH -#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_HIGH_BITS _u(0x80000000) -#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_HIGH_MSB _u(31) -#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_HIGH_LSB _u(31) -#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS1_GPIO15_EDGE_LOW -#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_LOW_BITS _u(0x40000000) -#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_LOW_MSB _u(30) -#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_LOW_LSB _u(30) -#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_HIGH -#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_HIGH_BITS _u(0x20000000) -#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_HIGH_MSB _u(29) -#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_HIGH_LSB _u(29) -#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_LOW -#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_LOW_BITS _u(0x10000000) -#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_LOW_MSB _u(28) -#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_LOW_LSB _u(28) -#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS1_GPIO14_EDGE_HIGH -#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_HIGH_BITS _u(0x08000000) -#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_HIGH_MSB _u(27) -#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_HIGH_LSB _u(27) -#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS1_GPIO14_EDGE_LOW -#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_LOW_BITS _u(0x04000000) -#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_LOW_MSB _u(26) -#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_LOW_LSB _u(26) -#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_HIGH -#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_HIGH_BITS _u(0x02000000) -#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_HIGH_MSB _u(25) -#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_HIGH_LSB _u(25) -#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_LOW -#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_LOW_BITS _u(0x01000000) -#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_LOW_MSB _u(24) -#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_LOW_LSB _u(24) -#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS1_GPIO13_EDGE_HIGH -#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_HIGH_BITS _u(0x00800000) -#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_HIGH_MSB _u(23) -#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_HIGH_LSB _u(23) -#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS1_GPIO13_EDGE_LOW -#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_LOW_BITS _u(0x00400000) -#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_LOW_MSB _u(22) -#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_LOW_LSB _u(22) -#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_HIGH -#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_HIGH_BITS _u(0x00200000) -#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_HIGH_MSB _u(21) -#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_HIGH_LSB _u(21) -#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_LOW -#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_LOW_BITS _u(0x00100000) -#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_LOW_MSB _u(20) -#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_LOW_LSB _u(20) -#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS1_GPIO12_EDGE_HIGH -#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_HIGH_BITS _u(0x00080000) -#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_HIGH_MSB _u(19) -#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_HIGH_LSB _u(19) -#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS1_GPIO12_EDGE_LOW -#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_LOW_BITS _u(0x00040000) -#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_LOW_MSB _u(18) -#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_LOW_LSB _u(18) -#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_HIGH -#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_HIGH_BITS _u(0x00020000) -#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_HIGH_MSB _u(17) -#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_HIGH_LSB _u(17) -#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_LOW -#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_LOW_BITS _u(0x00010000) -#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_LOW_MSB _u(16) -#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_LOW_LSB _u(16) -#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS1_GPIO11_EDGE_HIGH -#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_HIGH_BITS _u(0x00008000) -#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_HIGH_MSB _u(15) -#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_HIGH_LSB _u(15) -#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS1_GPIO11_EDGE_LOW -#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_LOW_BITS _u(0x00004000) -#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_LOW_MSB _u(14) -#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_LOW_LSB _u(14) -#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_HIGH -#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_HIGH_BITS _u(0x00002000) -#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_HIGH_MSB _u(13) -#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_HIGH_LSB _u(13) -#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_LOW -#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_LOW_BITS _u(0x00001000) -#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_LOW_MSB _u(12) -#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_LOW_LSB _u(12) -#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS1_GPIO10_EDGE_HIGH -#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_HIGH_BITS _u(0x00000800) -#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_HIGH_MSB _u(11) -#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_HIGH_LSB _u(11) -#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS1_GPIO10_EDGE_LOW -#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_LOW_BITS _u(0x00000400) -#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_LOW_MSB _u(10) -#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_LOW_LSB _u(10) -#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_HIGH -#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_HIGH_BITS _u(0x00000200) -#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_HIGH_MSB _u(9) -#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_HIGH_LSB _u(9) -#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_LOW -#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_LOW_BITS _u(0x00000100) -#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_LOW_MSB _u(8) -#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_LOW_LSB _u(8) -#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS1_GPIO9_EDGE_HIGH -#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_HIGH_BITS _u(0x00000080) -#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_HIGH_MSB _u(7) -#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_HIGH_LSB _u(7) -#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS1_GPIO9_EDGE_LOW -#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_LOW_BITS _u(0x00000040) -#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_LOW_MSB _u(6) -#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_LOW_LSB _u(6) -#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_HIGH -#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_HIGH_BITS _u(0x00000020) -#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_HIGH_MSB _u(5) -#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_HIGH_LSB _u(5) -#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_LOW -#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_LOW_BITS _u(0x00000010) -#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_LOW_MSB _u(4) -#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_LOW_LSB _u(4) -#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS1_GPIO8_EDGE_HIGH -#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_HIGH_BITS _u(0x00000008) -#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_HIGH_MSB _u(3) -#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_HIGH_LSB _u(3) -#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS1_GPIO8_EDGE_LOW -#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_LOW_BITS _u(0x00000004) -#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_LOW_MSB _u(2) -#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_LOW_LSB _u(2) -#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_HIGH -#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_HIGH_BITS _u(0x00000002) -#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_HIGH_MSB _u(1) -#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_HIGH_LSB _u(1) -#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_LOW -#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_LOW_BITS _u(0x00000001) -#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_LOW_MSB _u(0) -#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_LOW_LSB _u(0) -#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_LOW_ACCESS "RO" -// ============================================================================= -// Register : IO_BANK0_PROC0_INTS2 -// Description : Interrupt status after masking & forcing for proc0 -#define IO_BANK0_PROC0_INTS2_OFFSET _u(0x00000128) -#define IO_BANK0_PROC0_INTS2_BITS _u(0xffffffff) -#define IO_BANK0_PROC0_INTS2_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS2_GPIO23_EDGE_HIGH -#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_HIGH_BITS _u(0x80000000) -#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_HIGH_MSB _u(31) -#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_HIGH_LSB _u(31) -#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS2_GPIO23_EDGE_LOW -#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_LOW_BITS _u(0x40000000) -#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_LOW_MSB _u(30) -#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_LOW_LSB _u(30) -#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_HIGH -#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_HIGH_BITS _u(0x20000000) -#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_HIGH_MSB _u(29) -#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_HIGH_LSB _u(29) -#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_LOW -#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_LOW_BITS _u(0x10000000) -#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_LOW_MSB _u(28) -#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_LOW_LSB _u(28) -#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS2_GPIO22_EDGE_HIGH -#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_HIGH_BITS _u(0x08000000) -#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_HIGH_MSB _u(27) -#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_HIGH_LSB _u(27) -#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS2_GPIO22_EDGE_LOW -#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_LOW_BITS _u(0x04000000) -#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_LOW_MSB _u(26) -#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_LOW_LSB _u(26) -#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_HIGH -#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_HIGH_BITS _u(0x02000000) -#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_HIGH_MSB _u(25) -#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_HIGH_LSB _u(25) -#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_LOW -#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_LOW_BITS _u(0x01000000) -#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_LOW_MSB _u(24) -#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_LOW_LSB _u(24) -#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS2_GPIO21_EDGE_HIGH -#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_HIGH_BITS _u(0x00800000) -#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_HIGH_MSB _u(23) -#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_HIGH_LSB _u(23) -#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS2_GPIO21_EDGE_LOW -#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_LOW_BITS _u(0x00400000) -#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_LOW_MSB _u(22) -#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_LOW_LSB _u(22) -#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_HIGH -#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_HIGH_BITS _u(0x00200000) -#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_HIGH_MSB _u(21) -#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_HIGH_LSB _u(21) -#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_LOW -#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_LOW_BITS _u(0x00100000) -#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_LOW_MSB _u(20) -#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_LOW_LSB _u(20) -#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS2_GPIO20_EDGE_HIGH -#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_HIGH_BITS _u(0x00080000) -#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_HIGH_MSB _u(19) -#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_HIGH_LSB _u(19) -#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS2_GPIO20_EDGE_LOW -#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_LOW_BITS _u(0x00040000) -#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_LOW_MSB _u(18) -#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_LOW_LSB _u(18) -#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_HIGH -#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_HIGH_BITS _u(0x00020000) -#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_HIGH_MSB _u(17) -#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_HIGH_LSB _u(17) -#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_LOW -#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_LOW_BITS _u(0x00010000) -#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_LOW_MSB _u(16) -#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_LOW_LSB _u(16) -#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS2_GPIO19_EDGE_HIGH -#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_HIGH_BITS _u(0x00008000) -#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_HIGH_MSB _u(15) -#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_HIGH_LSB _u(15) -#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS2_GPIO19_EDGE_LOW -#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_LOW_BITS _u(0x00004000) -#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_LOW_MSB _u(14) -#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_LOW_LSB _u(14) -#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_HIGH -#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_HIGH_BITS _u(0x00002000) -#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_HIGH_MSB _u(13) -#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_HIGH_LSB _u(13) -#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_LOW -#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_LOW_BITS _u(0x00001000) -#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_LOW_MSB _u(12) -#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_LOW_LSB _u(12) -#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS2_GPIO18_EDGE_HIGH -#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_HIGH_BITS _u(0x00000800) -#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_HIGH_MSB _u(11) -#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_HIGH_LSB _u(11) -#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS2_GPIO18_EDGE_LOW -#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_LOW_BITS _u(0x00000400) -#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_LOW_MSB _u(10) -#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_LOW_LSB _u(10) -#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_HIGH -#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_HIGH_BITS _u(0x00000200) -#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_HIGH_MSB _u(9) -#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_HIGH_LSB _u(9) -#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_LOW -#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_LOW_BITS _u(0x00000100) -#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_LOW_MSB _u(8) -#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_LOW_LSB _u(8) -#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS2_GPIO17_EDGE_HIGH -#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_HIGH_BITS _u(0x00000080) -#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_HIGH_MSB _u(7) -#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_HIGH_LSB _u(7) -#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS2_GPIO17_EDGE_LOW -#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_LOW_BITS _u(0x00000040) -#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_LOW_MSB _u(6) -#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_LOW_LSB _u(6) -#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_HIGH -#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_HIGH_BITS _u(0x00000020) -#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_HIGH_MSB _u(5) -#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_HIGH_LSB _u(5) -#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_LOW -#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_LOW_BITS _u(0x00000010) -#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_LOW_MSB _u(4) -#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_LOW_LSB _u(4) -#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS2_GPIO16_EDGE_HIGH -#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_HIGH_BITS _u(0x00000008) -#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_HIGH_MSB _u(3) -#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_HIGH_LSB _u(3) -#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS2_GPIO16_EDGE_LOW -#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_LOW_BITS _u(0x00000004) -#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_LOW_MSB _u(2) -#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_LOW_LSB _u(2) -#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_HIGH -#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_HIGH_BITS _u(0x00000002) -#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_HIGH_MSB _u(1) -#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_HIGH_LSB _u(1) -#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_LOW -#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_LOW_BITS _u(0x00000001) -#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_LOW_MSB _u(0) -#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_LOW_LSB _u(0) -#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_LOW_ACCESS "RO" -// ============================================================================= -// Register : IO_BANK0_PROC0_INTS3 -// Description : Interrupt status after masking & forcing for proc0 -#define IO_BANK0_PROC0_INTS3_OFFSET _u(0x0000012c) -#define IO_BANK0_PROC0_INTS3_BITS _u(0x00ffffff) -#define IO_BANK0_PROC0_INTS3_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS3_GPIO29_EDGE_HIGH -#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_HIGH_BITS _u(0x00800000) -#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_HIGH_MSB _u(23) -#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_HIGH_LSB _u(23) -#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS3_GPIO29_EDGE_LOW -#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_LOW_BITS _u(0x00400000) -#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_LOW_MSB _u(22) -#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_LOW_LSB _u(22) -#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_HIGH -#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_HIGH_BITS _u(0x00200000) -#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_HIGH_MSB _u(21) -#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_HIGH_LSB _u(21) -#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_LOW -#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_LOW_BITS _u(0x00100000) -#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_LOW_MSB _u(20) -#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_LOW_LSB _u(20) -#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS3_GPIO28_EDGE_HIGH -#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_HIGH_BITS _u(0x00080000) -#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_HIGH_MSB _u(19) -#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_HIGH_LSB _u(19) -#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS3_GPIO28_EDGE_LOW -#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_LOW_BITS _u(0x00040000) -#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_LOW_MSB _u(18) -#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_LOW_LSB _u(18) -#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_HIGH -#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_HIGH_BITS _u(0x00020000) -#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_HIGH_MSB _u(17) -#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_HIGH_LSB _u(17) -#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_LOW -#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_LOW_BITS _u(0x00010000) -#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_LOW_MSB _u(16) -#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_LOW_LSB _u(16) -#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS3_GPIO27_EDGE_HIGH -#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_HIGH_BITS _u(0x00008000) -#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_HIGH_MSB _u(15) -#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_HIGH_LSB _u(15) -#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS3_GPIO27_EDGE_LOW -#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_LOW_BITS _u(0x00004000) -#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_LOW_MSB _u(14) -#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_LOW_LSB _u(14) -#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_HIGH -#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_HIGH_BITS _u(0x00002000) -#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_HIGH_MSB _u(13) -#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_HIGH_LSB _u(13) -#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_LOW -#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_LOW_BITS _u(0x00001000) -#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_LOW_MSB _u(12) -#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_LOW_LSB _u(12) -#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS3_GPIO26_EDGE_HIGH -#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_HIGH_BITS _u(0x00000800) -#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_HIGH_MSB _u(11) -#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_HIGH_LSB _u(11) -#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS3_GPIO26_EDGE_LOW -#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_LOW_BITS _u(0x00000400) -#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_LOW_MSB _u(10) -#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_LOW_LSB _u(10) -#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_HIGH -#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_HIGH_BITS _u(0x00000200) -#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_HIGH_MSB _u(9) -#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_HIGH_LSB _u(9) -#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_LOW -#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_LOW_BITS _u(0x00000100) -#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_LOW_MSB _u(8) -#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_LOW_LSB _u(8) -#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS3_GPIO25_EDGE_HIGH -#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_HIGH_BITS _u(0x00000080) -#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_HIGH_MSB _u(7) -#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_HIGH_LSB _u(7) -#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS3_GPIO25_EDGE_LOW -#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_LOW_BITS _u(0x00000040) -#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_LOW_MSB _u(6) -#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_LOW_LSB _u(6) -#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_HIGH -#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_HIGH_BITS _u(0x00000020) -#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_HIGH_MSB _u(5) -#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_HIGH_LSB _u(5) -#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_LOW -#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_LOW_BITS _u(0x00000010) -#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_LOW_MSB _u(4) -#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_LOW_LSB _u(4) -#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS3_GPIO24_EDGE_HIGH -#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_HIGH_BITS _u(0x00000008) -#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_HIGH_MSB _u(3) -#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_HIGH_LSB _u(3) -#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS3_GPIO24_EDGE_LOW -#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_LOW_BITS _u(0x00000004) -#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_LOW_MSB _u(2) -#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_LOW_LSB _u(2) -#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_HIGH -#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_HIGH_BITS _u(0x00000002) -#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_HIGH_MSB _u(1) -#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_HIGH_LSB _u(1) -#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_LOW -#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_LOW_BITS _u(0x00000001) -#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_LOW_MSB _u(0) -#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_LOW_LSB _u(0) -#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_LOW_ACCESS "RO" -// ============================================================================= -// Register : IO_BANK0_PROC1_INTE0 -// Description : Interrupt Enable for proc1 -#define IO_BANK0_PROC1_INTE0_OFFSET _u(0x00000130) -#define IO_BANK0_PROC1_INTE0_BITS _u(0xffffffff) -#define IO_BANK0_PROC1_INTE0_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE0_GPIO7_EDGE_HIGH -#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_HIGH_BITS _u(0x80000000) -#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_HIGH_MSB _u(31) -#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_HIGH_LSB _u(31) -#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE0_GPIO7_EDGE_LOW -#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_LOW_BITS _u(0x40000000) -#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_LOW_MSB _u(30) -#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_LOW_LSB _u(30) -#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_HIGH -#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_HIGH_BITS _u(0x20000000) -#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_HIGH_MSB _u(29) -#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_HIGH_LSB _u(29) -#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_LOW -#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_LOW_BITS _u(0x10000000) -#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_LOW_MSB _u(28) -#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_LOW_LSB _u(28) -#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE0_GPIO6_EDGE_HIGH -#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_HIGH_BITS _u(0x08000000) -#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_HIGH_MSB _u(27) -#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_HIGH_LSB _u(27) -#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE0_GPIO6_EDGE_LOW -#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_LOW_BITS _u(0x04000000) -#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_LOW_MSB _u(26) -#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_LOW_LSB _u(26) -#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_HIGH -#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_HIGH_BITS _u(0x02000000) -#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_HIGH_MSB _u(25) -#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_HIGH_LSB _u(25) -#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_LOW -#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_LOW_BITS _u(0x01000000) -#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_LOW_MSB _u(24) -#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_LOW_LSB _u(24) -#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE0_GPIO5_EDGE_HIGH -#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_HIGH_BITS _u(0x00800000) -#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_HIGH_MSB _u(23) -#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_HIGH_LSB _u(23) -#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE0_GPIO5_EDGE_LOW -#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_LOW_BITS _u(0x00400000) -#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_LOW_MSB _u(22) -#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_LOW_LSB _u(22) -#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_HIGH -#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_HIGH_BITS _u(0x00200000) -#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_HIGH_MSB _u(21) -#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_HIGH_LSB _u(21) -#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_LOW -#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_LOW_BITS _u(0x00100000) -#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_LOW_MSB _u(20) -#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_LOW_LSB _u(20) -#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE0_GPIO4_EDGE_HIGH -#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_HIGH_BITS _u(0x00080000) -#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_HIGH_MSB _u(19) -#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_HIGH_LSB _u(19) -#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE0_GPIO4_EDGE_LOW -#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_LOW_BITS _u(0x00040000) -#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_LOW_MSB _u(18) -#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_LOW_LSB _u(18) -#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_HIGH -#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_HIGH_BITS _u(0x00020000) -#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_HIGH_MSB _u(17) -#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_HIGH_LSB _u(17) -#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_LOW -#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_LOW_BITS _u(0x00010000) -#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_LOW_MSB _u(16) -#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_LOW_LSB _u(16) -#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE0_GPIO3_EDGE_HIGH -#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_HIGH_BITS _u(0x00008000) -#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_HIGH_MSB _u(15) -#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_HIGH_LSB _u(15) -#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE0_GPIO3_EDGE_LOW -#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_LOW_BITS _u(0x00004000) -#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_LOW_MSB _u(14) -#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_LOW_LSB _u(14) -#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_HIGH -#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_HIGH_BITS _u(0x00002000) -#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_HIGH_MSB _u(13) -#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_HIGH_LSB _u(13) -#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_LOW -#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_LOW_BITS _u(0x00001000) -#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_LOW_MSB _u(12) -#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_LOW_LSB _u(12) -#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE0_GPIO2_EDGE_HIGH -#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_HIGH_BITS _u(0x00000800) -#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_HIGH_MSB _u(11) -#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_HIGH_LSB _u(11) -#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE0_GPIO2_EDGE_LOW -#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_LOW_BITS _u(0x00000400) -#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_LOW_MSB _u(10) -#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_LOW_LSB _u(10) -#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_HIGH -#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_HIGH_BITS _u(0x00000200) -#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_HIGH_MSB _u(9) -#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_HIGH_LSB _u(9) -#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_LOW -#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_LOW_BITS _u(0x00000100) -#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_LOW_MSB _u(8) -#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_LOW_LSB _u(8) -#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE0_GPIO1_EDGE_HIGH -#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_HIGH_BITS _u(0x00000080) -#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_HIGH_MSB _u(7) -#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_HIGH_LSB _u(7) -#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE0_GPIO1_EDGE_LOW -#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_LOW_BITS _u(0x00000040) -#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_LOW_MSB _u(6) -#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_LOW_LSB _u(6) -#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_HIGH -#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_HIGH_BITS _u(0x00000020) -#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_HIGH_MSB _u(5) -#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_HIGH_LSB _u(5) -#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_LOW -#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_LOW_BITS _u(0x00000010) -#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_LOW_MSB _u(4) -#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_LOW_LSB _u(4) -#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE0_GPIO0_EDGE_HIGH -#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_HIGH_BITS _u(0x00000008) -#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_HIGH_MSB _u(3) -#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_HIGH_LSB _u(3) -#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE0_GPIO0_EDGE_LOW -#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_LOW_BITS _u(0x00000004) -#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_LOW_MSB _u(2) -#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_LOW_LSB _u(2) -#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_HIGH -#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_HIGH_BITS _u(0x00000002) -#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_HIGH_MSB _u(1) -#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_HIGH_LSB _u(1) -#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_LOW -#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_LOW_BITS _u(0x00000001) -#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_LOW_MSB _u(0) -#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_LOW_LSB _u(0) -#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_LOW_ACCESS "RW" -// ============================================================================= -// Register : IO_BANK0_PROC1_INTE1 -// Description : Interrupt Enable for proc1 -#define IO_BANK0_PROC1_INTE1_OFFSET _u(0x00000134) -#define IO_BANK0_PROC1_INTE1_BITS _u(0xffffffff) -#define IO_BANK0_PROC1_INTE1_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE1_GPIO15_EDGE_HIGH -#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_HIGH_BITS _u(0x80000000) -#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_HIGH_MSB _u(31) -#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_HIGH_LSB _u(31) -#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE1_GPIO15_EDGE_LOW -#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_LOW_BITS _u(0x40000000) -#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_LOW_MSB _u(30) -#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_LOW_LSB _u(30) -#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_HIGH -#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_HIGH_BITS _u(0x20000000) -#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_HIGH_MSB _u(29) -#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_HIGH_LSB _u(29) -#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_LOW -#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_LOW_BITS _u(0x10000000) -#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_LOW_MSB _u(28) -#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_LOW_LSB _u(28) -#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE1_GPIO14_EDGE_HIGH -#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_HIGH_BITS _u(0x08000000) -#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_HIGH_MSB _u(27) -#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_HIGH_LSB _u(27) -#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE1_GPIO14_EDGE_LOW -#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_LOW_BITS _u(0x04000000) -#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_LOW_MSB _u(26) -#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_LOW_LSB _u(26) -#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_HIGH -#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_HIGH_BITS _u(0x02000000) -#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_HIGH_MSB _u(25) -#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_HIGH_LSB _u(25) -#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_LOW -#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_LOW_BITS _u(0x01000000) -#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_LOW_MSB _u(24) -#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_LOW_LSB _u(24) -#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE1_GPIO13_EDGE_HIGH -#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_HIGH_BITS _u(0x00800000) -#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_HIGH_MSB _u(23) -#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_HIGH_LSB _u(23) -#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE1_GPIO13_EDGE_LOW -#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_LOW_BITS _u(0x00400000) -#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_LOW_MSB _u(22) -#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_LOW_LSB _u(22) -#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_HIGH -#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_HIGH_BITS _u(0x00200000) -#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_HIGH_MSB _u(21) -#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_HIGH_LSB _u(21) -#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_LOW -#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_LOW_BITS _u(0x00100000) -#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_LOW_MSB _u(20) -#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_LOW_LSB _u(20) -#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE1_GPIO12_EDGE_HIGH -#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_HIGH_BITS _u(0x00080000) -#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_HIGH_MSB _u(19) -#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_HIGH_LSB _u(19) -#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE1_GPIO12_EDGE_LOW -#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_LOW_BITS _u(0x00040000) -#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_LOW_MSB _u(18) -#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_LOW_LSB _u(18) -#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_HIGH -#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_HIGH_BITS _u(0x00020000) -#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_HIGH_MSB _u(17) -#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_HIGH_LSB _u(17) -#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_LOW -#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_LOW_BITS _u(0x00010000) -#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_LOW_MSB _u(16) -#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_LOW_LSB _u(16) -#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE1_GPIO11_EDGE_HIGH -#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_HIGH_BITS _u(0x00008000) -#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_HIGH_MSB _u(15) -#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_HIGH_LSB _u(15) -#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE1_GPIO11_EDGE_LOW -#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_LOW_BITS _u(0x00004000) -#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_LOW_MSB _u(14) -#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_LOW_LSB _u(14) -#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_HIGH -#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_HIGH_BITS _u(0x00002000) -#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_HIGH_MSB _u(13) -#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_HIGH_LSB _u(13) -#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_LOW -#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_LOW_BITS _u(0x00001000) -#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_LOW_MSB _u(12) -#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_LOW_LSB _u(12) -#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE1_GPIO10_EDGE_HIGH -#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_HIGH_BITS _u(0x00000800) -#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_HIGH_MSB _u(11) -#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_HIGH_LSB _u(11) -#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE1_GPIO10_EDGE_LOW -#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_LOW_BITS _u(0x00000400) -#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_LOW_MSB _u(10) -#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_LOW_LSB _u(10) -#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_HIGH -#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_HIGH_BITS _u(0x00000200) -#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_HIGH_MSB _u(9) -#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_HIGH_LSB _u(9) -#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_LOW -#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_LOW_BITS _u(0x00000100) -#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_LOW_MSB _u(8) -#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_LOW_LSB _u(8) -#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE1_GPIO9_EDGE_HIGH -#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_HIGH_BITS _u(0x00000080) -#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_HIGH_MSB _u(7) -#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_HIGH_LSB _u(7) -#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE1_GPIO9_EDGE_LOW -#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_LOW_BITS _u(0x00000040) -#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_LOW_MSB _u(6) -#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_LOW_LSB _u(6) -#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_HIGH -#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_HIGH_BITS _u(0x00000020) -#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_HIGH_MSB _u(5) -#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_HIGH_LSB _u(5) -#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_LOW -#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_LOW_BITS _u(0x00000010) -#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_LOW_MSB _u(4) -#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_LOW_LSB _u(4) -#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE1_GPIO8_EDGE_HIGH -#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_HIGH_BITS _u(0x00000008) -#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_HIGH_MSB _u(3) -#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_HIGH_LSB _u(3) -#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE1_GPIO8_EDGE_LOW -#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_LOW_BITS _u(0x00000004) -#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_LOW_MSB _u(2) -#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_LOW_LSB _u(2) -#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_HIGH -#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_HIGH_BITS _u(0x00000002) -#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_HIGH_MSB _u(1) -#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_HIGH_LSB _u(1) -#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_LOW -#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_LOW_BITS _u(0x00000001) -#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_LOW_MSB _u(0) -#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_LOW_LSB _u(0) -#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_LOW_ACCESS "RW" -// ============================================================================= -// Register : IO_BANK0_PROC1_INTE2 -// Description : Interrupt Enable for proc1 -#define IO_BANK0_PROC1_INTE2_OFFSET _u(0x00000138) -#define IO_BANK0_PROC1_INTE2_BITS _u(0xffffffff) -#define IO_BANK0_PROC1_INTE2_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE2_GPIO23_EDGE_HIGH -#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_HIGH_BITS _u(0x80000000) -#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_HIGH_MSB _u(31) -#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_HIGH_LSB _u(31) -#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE2_GPIO23_EDGE_LOW -#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_LOW_BITS _u(0x40000000) -#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_LOW_MSB _u(30) -#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_LOW_LSB _u(30) -#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_HIGH -#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_HIGH_BITS _u(0x20000000) -#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_HIGH_MSB _u(29) -#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_HIGH_LSB _u(29) -#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_LOW -#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_LOW_BITS _u(0x10000000) -#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_LOW_MSB _u(28) -#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_LOW_LSB _u(28) -#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE2_GPIO22_EDGE_HIGH -#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_HIGH_BITS _u(0x08000000) -#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_HIGH_MSB _u(27) -#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_HIGH_LSB _u(27) -#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE2_GPIO22_EDGE_LOW -#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_LOW_BITS _u(0x04000000) -#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_LOW_MSB _u(26) -#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_LOW_LSB _u(26) -#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_HIGH -#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_HIGH_BITS _u(0x02000000) -#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_HIGH_MSB _u(25) -#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_HIGH_LSB _u(25) -#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_LOW -#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_LOW_BITS _u(0x01000000) -#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_LOW_MSB _u(24) -#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_LOW_LSB _u(24) -#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE2_GPIO21_EDGE_HIGH -#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_HIGH_BITS _u(0x00800000) -#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_HIGH_MSB _u(23) -#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_HIGH_LSB _u(23) -#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE2_GPIO21_EDGE_LOW -#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_LOW_BITS _u(0x00400000) -#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_LOW_MSB _u(22) -#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_LOW_LSB _u(22) -#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_HIGH -#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_HIGH_BITS _u(0x00200000) -#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_HIGH_MSB _u(21) -#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_HIGH_LSB _u(21) -#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_LOW -#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_LOW_BITS _u(0x00100000) -#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_LOW_MSB _u(20) -#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_LOW_LSB _u(20) -#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE2_GPIO20_EDGE_HIGH -#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_HIGH_BITS _u(0x00080000) -#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_HIGH_MSB _u(19) -#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_HIGH_LSB _u(19) -#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE2_GPIO20_EDGE_LOW -#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_LOW_BITS _u(0x00040000) -#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_LOW_MSB _u(18) -#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_LOW_LSB _u(18) -#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_HIGH -#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_HIGH_BITS _u(0x00020000) -#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_HIGH_MSB _u(17) -#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_HIGH_LSB _u(17) -#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_LOW -#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_LOW_BITS _u(0x00010000) -#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_LOW_MSB _u(16) -#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_LOW_LSB _u(16) -#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE2_GPIO19_EDGE_HIGH -#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_HIGH_BITS _u(0x00008000) -#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_HIGH_MSB _u(15) -#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_HIGH_LSB _u(15) -#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE2_GPIO19_EDGE_LOW -#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_LOW_BITS _u(0x00004000) -#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_LOW_MSB _u(14) -#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_LOW_LSB _u(14) -#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_HIGH -#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_HIGH_BITS _u(0x00002000) -#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_HIGH_MSB _u(13) -#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_HIGH_LSB _u(13) -#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_LOW -#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_LOW_BITS _u(0x00001000) -#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_LOW_MSB _u(12) -#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_LOW_LSB _u(12) -#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE2_GPIO18_EDGE_HIGH -#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_HIGH_BITS _u(0x00000800) -#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_HIGH_MSB _u(11) -#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_HIGH_LSB _u(11) -#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE2_GPIO18_EDGE_LOW -#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_LOW_BITS _u(0x00000400) -#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_LOW_MSB _u(10) -#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_LOW_LSB _u(10) -#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_HIGH -#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_HIGH_BITS _u(0x00000200) -#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_HIGH_MSB _u(9) -#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_HIGH_LSB _u(9) -#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_LOW -#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_LOW_BITS _u(0x00000100) -#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_LOW_MSB _u(8) -#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_LOW_LSB _u(8) -#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE2_GPIO17_EDGE_HIGH -#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_HIGH_BITS _u(0x00000080) -#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_HIGH_MSB _u(7) -#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_HIGH_LSB _u(7) -#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE2_GPIO17_EDGE_LOW -#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_LOW_BITS _u(0x00000040) -#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_LOW_MSB _u(6) -#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_LOW_LSB _u(6) -#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_HIGH -#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_HIGH_BITS _u(0x00000020) -#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_HIGH_MSB _u(5) -#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_HIGH_LSB _u(5) -#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_LOW -#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_LOW_BITS _u(0x00000010) -#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_LOW_MSB _u(4) -#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_LOW_LSB _u(4) -#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE2_GPIO16_EDGE_HIGH -#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_HIGH_BITS _u(0x00000008) -#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_HIGH_MSB _u(3) -#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_HIGH_LSB _u(3) -#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE2_GPIO16_EDGE_LOW -#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_LOW_BITS _u(0x00000004) -#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_LOW_MSB _u(2) -#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_LOW_LSB _u(2) -#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_HIGH -#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_HIGH_BITS _u(0x00000002) -#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_HIGH_MSB _u(1) -#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_HIGH_LSB _u(1) -#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_LOW -#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_LOW_BITS _u(0x00000001) -#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_LOW_MSB _u(0) -#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_LOW_LSB _u(0) -#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_LOW_ACCESS "RW" -// ============================================================================= -// Register : IO_BANK0_PROC1_INTE3 -// Description : Interrupt Enable for proc1 -#define IO_BANK0_PROC1_INTE3_OFFSET _u(0x0000013c) -#define IO_BANK0_PROC1_INTE3_BITS _u(0x00ffffff) -#define IO_BANK0_PROC1_INTE3_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE3_GPIO29_EDGE_HIGH -#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_HIGH_BITS _u(0x00800000) -#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_HIGH_MSB _u(23) -#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_HIGH_LSB _u(23) -#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE3_GPIO29_EDGE_LOW -#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_LOW_BITS _u(0x00400000) -#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_LOW_MSB _u(22) -#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_LOW_LSB _u(22) -#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_HIGH -#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_HIGH_BITS _u(0x00200000) -#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_HIGH_MSB _u(21) -#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_HIGH_LSB _u(21) -#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_LOW -#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_LOW_BITS _u(0x00100000) -#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_LOW_MSB _u(20) -#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_LOW_LSB _u(20) -#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE3_GPIO28_EDGE_HIGH -#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_HIGH_BITS _u(0x00080000) -#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_HIGH_MSB _u(19) -#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_HIGH_LSB _u(19) -#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE3_GPIO28_EDGE_LOW -#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_LOW_BITS _u(0x00040000) -#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_LOW_MSB _u(18) -#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_LOW_LSB _u(18) -#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_HIGH -#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_HIGH_BITS _u(0x00020000) -#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_HIGH_MSB _u(17) -#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_HIGH_LSB _u(17) -#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_LOW -#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_LOW_BITS _u(0x00010000) -#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_LOW_MSB _u(16) -#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_LOW_LSB _u(16) -#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE3_GPIO27_EDGE_HIGH -#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_HIGH_BITS _u(0x00008000) -#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_HIGH_MSB _u(15) -#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_HIGH_LSB _u(15) -#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE3_GPIO27_EDGE_LOW -#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_LOW_BITS _u(0x00004000) -#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_LOW_MSB _u(14) -#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_LOW_LSB _u(14) -#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_HIGH -#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_HIGH_BITS _u(0x00002000) -#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_HIGH_MSB _u(13) -#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_HIGH_LSB _u(13) -#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_LOW -#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_LOW_BITS _u(0x00001000) -#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_LOW_MSB _u(12) -#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_LOW_LSB _u(12) -#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE3_GPIO26_EDGE_HIGH -#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_HIGH_BITS _u(0x00000800) -#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_HIGH_MSB _u(11) -#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_HIGH_LSB _u(11) -#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE3_GPIO26_EDGE_LOW -#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_LOW_BITS _u(0x00000400) -#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_LOW_MSB _u(10) -#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_LOW_LSB _u(10) -#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_HIGH -#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_HIGH_BITS _u(0x00000200) -#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_HIGH_MSB _u(9) -#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_HIGH_LSB _u(9) -#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_LOW -#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_LOW_BITS _u(0x00000100) -#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_LOW_MSB _u(8) -#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_LOW_LSB _u(8) -#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE3_GPIO25_EDGE_HIGH -#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_HIGH_BITS _u(0x00000080) -#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_HIGH_MSB _u(7) -#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_HIGH_LSB _u(7) -#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE3_GPIO25_EDGE_LOW -#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_LOW_BITS _u(0x00000040) -#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_LOW_MSB _u(6) -#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_LOW_LSB _u(6) -#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_HIGH -#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_HIGH_BITS _u(0x00000020) -#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_HIGH_MSB _u(5) -#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_HIGH_LSB _u(5) -#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_LOW -#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_LOW_BITS _u(0x00000010) -#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_LOW_MSB _u(4) -#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_LOW_LSB _u(4) -#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE3_GPIO24_EDGE_HIGH -#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_HIGH_BITS _u(0x00000008) -#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_HIGH_MSB _u(3) -#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_HIGH_LSB _u(3) -#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE3_GPIO24_EDGE_LOW -#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_LOW_BITS _u(0x00000004) -#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_LOW_MSB _u(2) -#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_LOW_LSB _u(2) -#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_HIGH -#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_HIGH_BITS _u(0x00000002) -#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_HIGH_MSB _u(1) -#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_HIGH_LSB _u(1) -#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_LOW -#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_LOW_BITS _u(0x00000001) -#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_LOW_MSB _u(0) -#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_LOW_LSB _u(0) -#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_LOW_ACCESS "RW" -// ============================================================================= -// Register : IO_BANK0_PROC1_INTF0 -// Description : Interrupt Force for proc1 -#define IO_BANK0_PROC1_INTF0_OFFSET _u(0x00000140) -#define IO_BANK0_PROC1_INTF0_BITS _u(0xffffffff) -#define IO_BANK0_PROC1_INTF0_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF0_GPIO7_EDGE_HIGH -#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_HIGH_BITS _u(0x80000000) -#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_HIGH_MSB _u(31) -#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_HIGH_LSB _u(31) -#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF0_GPIO7_EDGE_LOW -#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_LOW_BITS _u(0x40000000) -#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_LOW_MSB _u(30) -#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_LOW_LSB _u(30) -#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_HIGH -#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_HIGH_BITS _u(0x20000000) -#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_HIGH_MSB _u(29) -#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_HIGH_LSB _u(29) -#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_LOW -#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_LOW_BITS _u(0x10000000) -#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_LOW_MSB _u(28) -#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_LOW_LSB _u(28) -#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF0_GPIO6_EDGE_HIGH -#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_HIGH_BITS _u(0x08000000) -#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_HIGH_MSB _u(27) -#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_HIGH_LSB _u(27) -#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF0_GPIO6_EDGE_LOW -#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_LOW_BITS _u(0x04000000) -#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_LOW_MSB _u(26) -#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_LOW_LSB _u(26) -#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_HIGH -#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_HIGH_BITS _u(0x02000000) -#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_HIGH_MSB _u(25) -#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_HIGH_LSB _u(25) -#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_LOW -#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_LOW_BITS _u(0x01000000) -#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_LOW_MSB _u(24) -#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_LOW_LSB _u(24) -#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF0_GPIO5_EDGE_HIGH -#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_HIGH_BITS _u(0x00800000) -#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_HIGH_MSB _u(23) -#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_HIGH_LSB _u(23) -#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF0_GPIO5_EDGE_LOW -#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_LOW_BITS _u(0x00400000) -#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_LOW_MSB _u(22) -#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_LOW_LSB _u(22) -#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_HIGH -#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_HIGH_BITS _u(0x00200000) -#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_HIGH_MSB _u(21) -#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_HIGH_LSB _u(21) -#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_LOW -#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_LOW_BITS _u(0x00100000) -#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_LOW_MSB _u(20) -#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_LOW_LSB _u(20) -#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF0_GPIO4_EDGE_HIGH -#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_HIGH_BITS _u(0x00080000) -#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_HIGH_MSB _u(19) -#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_HIGH_LSB _u(19) -#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF0_GPIO4_EDGE_LOW -#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_LOW_BITS _u(0x00040000) -#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_LOW_MSB _u(18) -#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_LOW_LSB _u(18) -#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_HIGH -#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_HIGH_BITS _u(0x00020000) -#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_HIGH_MSB _u(17) -#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_HIGH_LSB _u(17) -#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_LOW -#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_LOW_BITS _u(0x00010000) -#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_LOW_MSB _u(16) -#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_LOW_LSB _u(16) -#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF0_GPIO3_EDGE_HIGH -#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_HIGH_BITS _u(0x00008000) -#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_HIGH_MSB _u(15) -#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_HIGH_LSB _u(15) -#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF0_GPIO3_EDGE_LOW -#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_LOW_BITS _u(0x00004000) -#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_LOW_MSB _u(14) -#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_LOW_LSB _u(14) -#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_HIGH -#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_HIGH_BITS _u(0x00002000) -#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_HIGH_MSB _u(13) -#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_HIGH_LSB _u(13) -#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_LOW -#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_LOW_BITS _u(0x00001000) -#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_LOW_MSB _u(12) -#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_LOW_LSB _u(12) -#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF0_GPIO2_EDGE_HIGH -#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_HIGH_BITS _u(0x00000800) -#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_HIGH_MSB _u(11) -#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_HIGH_LSB _u(11) -#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF0_GPIO2_EDGE_LOW -#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_LOW_BITS _u(0x00000400) -#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_LOW_MSB _u(10) -#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_LOW_LSB _u(10) -#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_HIGH -#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_HIGH_BITS _u(0x00000200) -#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_HIGH_MSB _u(9) -#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_HIGH_LSB _u(9) -#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_LOW -#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_LOW_BITS _u(0x00000100) -#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_LOW_MSB _u(8) -#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_LOW_LSB _u(8) -#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF0_GPIO1_EDGE_HIGH -#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_HIGH_BITS _u(0x00000080) -#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_HIGH_MSB _u(7) -#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_HIGH_LSB _u(7) -#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF0_GPIO1_EDGE_LOW -#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_LOW_BITS _u(0x00000040) -#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_LOW_MSB _u(6) -#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_LOW_LSB _u(6) -#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_HIGH -#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_HIGH_BITS _u(0x00000020) -#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_HIGH_MSB _u(5) -#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_HIGH_LSB _u(5) -#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_LOW -#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_LOW_BITS _u(0x00000010) -#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_LOW_MSB _u(4) -#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_LOW_LSB _u(4) -#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF0_GPIO0_EDGE_HIGH -#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_HIGH_BITS _u(0x00000008) -#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_HIGH_MSB _u(3) -#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_HIGH_LSB _u(3) -#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF0_GPIO0_EDGE_LOW -#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_LOW_BITS _u(0x00000004) -#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_LOW_MSB _u(2) -#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_LOW_LSB _u(2) -#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_HIGH -#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_HIGH_BITS _u(0x00000002) -#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_HIGH_MSB _u(1) -#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_HIGH_LSB _u(1) -#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_LOW -#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_LOW_BITS _u(0x00000001) -#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_LOW_MSB _u(0) -#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_LOW_LSB _u(0) -#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_LOW_ACCESS "RW" -// ============================================================================= -// Register : IO_BANK0_PROC1_INTF1 -// Description : Interrupt Force for proc1 -#define IO_BANK0_PROC1_INTF1_OFFSET _u(0x00000144) -#define IO_BANK0_PROC1_INTF1_BITS _u(0xffffffff) -#define IO_BANK0_PROC1_INTF1_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF1_GPIO15_EDGE_HIGH -#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_HIGH_BITS _u(0x80000000) -#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_HIGH_MSB _u(31) -#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_HIGH_LSB _u(31) -#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF1_GPIO15_EDGE_LOW -#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_LOW_BITS _u(0x40000000) -#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_LOW_MSB _u(30) -#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_LOW_LSB _u(30) -#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_HIGH -#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_HIGH_BITS _u(0x20000000) -#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_HIGH_MSB _u(29) -#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_HIGH_LSB _u(29) -#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_LOW -#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_LOW_BITS _u(0x10000000) -#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_LOW_MSB _u(28) -#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_LOW_LSB _u(28) -#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF1_GPIO14_EDGE_HIGH -#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_HIGH_BITS _u(0x08000000) -#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_HIGH_MSB _u(27) -#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_HIGH_LSB _u(27) -#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF1_GPIO14_EDGE_LOW -#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_LOW_BITS _u(0x04000000) -#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_LOW_MSB _u(26) -#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_LOW_LSB _u(26) -#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_HIGH -#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_HIGH_BITS _u(0x02000000) -#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_HIGH_MSB _u(25) -#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_HIGH_LSB _u(25) -#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_LOW -#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_LOW_BITS _u(0x01000000) -#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_LOW_MSB _u(24) -#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_LOW_LSB _u(24) -#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF1_GPIO13_EDGE_HIGH -#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_HIGH_BITS _u(0x00800000) -#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_HIGH_MSB _u(23) -#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_HIGH_LSB _u(23) -#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF1_GPIO13_EDGE_LOW -#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_LOW_BITS _u(0x00400000) -#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_LOW_MSB _u(22) -#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_LOW_LSB _u(22) -#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_HIGH -#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_HIGH_BITS _u(0x00200000) -#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_HIGH_MSB _u(21) -#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_HIGH_LSB _u(21) -#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_LOW -#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_LOW_BITS _u(0x00100000) -#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_LOW_MSB _u(20) -#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_LOW_LSB _u(20) -#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF1_GPIO12_EDGE_HIGH -#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_HIGH_BITS _u(0x00080000) -#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_HIGH_MSB _u(19) -#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_HIGH_LSB _u(19) -#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF1_GPIO12_EDGE_LOW -#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_LOW_BITS _u(0x00040000) -#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_LOW_MSB _u(18) -#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_LOW_LSB _u(18) -#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_HIGH -#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_HIGH_BITS _u(0x00020000) -#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_HIGH_MSB _u(17) -#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_HIGH_LSB _u(17) -#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_LOW -#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_LOW_BITS _u(0x00010000) -#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_LOW_MSB _u(16) -#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_LOW_LSB _u(16) -#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF1_GPIO11_EDGE_HIGH -#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_HIGH_BITS _u(0x00008000) -#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_HIGH_MSB _u(15) -#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_HIGH_LSB _u(15) -#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF1_GPIO11_EDGE_LOW -#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_LOW_BITS _u(0x00004000) -#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_LOW_MSB _u(14) -#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_LOW_LSB _u(14) -#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_HIGH -#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_HIGH_BITS _u(0x00002000) -#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_HIGH_MSB _u(13) -#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_HIGH_LSB _u(13) -#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_LOW -#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_LOW_BITS _u(0x00001000) -#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_LOW_MSB _u(12) -#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_LOW_LSB _u(12) -#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF1_GPIO10_EDGE_HIGH -#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_HIGH_BITS _u(0x00000800) -#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_HIGH_MSB _u(11) -#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_HIGH_LSB _u(11) -#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF1_GPIO10_EDGE_LOW -#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_LOW_BITS _u(0x00000400) -#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_LOW_MSB _u(10) -#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_LOW_LSB _u(10) -#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_HIGH -#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_HIGH_BITS _u(0x00000200) -#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_HIGH_MSB _u(9) -#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_HIGH_LSB _u(9) -#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_LOW -#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_LOW_BITS _u(0x00000100) -#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_LOW_MSB _u(8) -#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_LOW_LSB _u(8) -#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF1_GPIO9_EDGE_HIGH -#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_HIGH_BITS _u(0x00000080) -#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_HIGH_MSB _u(7) -#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_HIGH_LSB _u(7) -#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF1_GPIO9_EDGE_LOW -#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_LOW_BITS _u(0x00000040) -#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_LOW_MSB _u(6) -#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_LOW_LSB _u(6) -#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_HIGH -#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_HIGH_BITS _u(0x00000020) -#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_HIGH_MSB _u(5) -#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_HIGH_LSB _u(5) -#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_LOW -#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_LOW_BITS _u(0x00000010) -#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_LOW_MSB _u(4) -#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_LOW_LSB _u(4) -#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF1_GPIO8_EDGE_HIGH -#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_HIGH_BITS _u(0x00000008) -#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_HIGH_MSB _u(3) -#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_HIGH_LSB _u(3) -#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF1_GPIO8_EDGE_LOW -#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_LOW_BITS _u(0x00000004) -#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_LOW_MSB _u(2) -#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_LOW_LSB _u(2) -#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_HIGH -#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_HIGH_BITS _u(0x00000002) -#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_HIGH_MSB _u(1) -#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_HIGH_LSB _u(1) -#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_LOW -#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_LOW_BITS _u(0x00000001) -#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_LOW_MSB _u(0) -#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_LOW_LSB _u(0) -#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_LOW_ACCESS "RW" -// ============================================================================= -// Register : IO_BANK0_PROC1_INTF2 -// Description : Interrupt Force for proc1 -#define IO_BANK0_PROC1_INTF2_OFFSET _u(0x00000148) -#define IO_BANK0_PROC1_INTF2_BITS _u(0xffffffff) -#define IO_BANK0_PROC1_INTF2_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF2_GPIO23_EDGE_HIGH -#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_HIGH_BITS _u(0x80000000) -#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_HIGH_MSB _u(31) -#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_HIGH_LSB _u(31) -#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF2_GPIO23_EDGE_LOW -#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_LOW_BITS _u(0x40000000) -#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_LOW_MSB _u(30) -#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_LOW_LSB _u(30) -#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_HIGH -#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_HIGH_BITS _u(0x20000000) -#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_HIGH_MSB _u(29) -#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_HIGH_LSB _u(29) -#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_LOW -#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_LOW_BITS _u(0x10000000) -#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_LOW_MSB _u(28) -#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_LOW_LSB _u(28) -#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF2_GPIO22_EDGE_HIGH -#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_HIGH_BITS _u(0x08000000) -#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_HIGH_MSB _u(27) -#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_HIGH_LSB _u(27) -#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF2_GPIO22_EDGE_LOW -#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_LOW_BITS _u(0x04000000) -#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_LOW_MSB _u(26) -#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_LOW_LSB _u(26) -#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_HIGH -#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_HIGH_BITS _u(0x02000000) -#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_HIGH_MSB _u(25) -#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_HIGH_LSB _u(25) -#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_LOW -#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_LOW_BITS _u(0x01000000) -#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_LOW_MSB _u(24) -#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_LOW_LSB _u(24) -#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF2_GPIO21_EDGE_HIGH -#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_HIGH_BITS _u(0x00800000) -#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_HIGH_MSB _u(23) -#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_HIGH_LSB _u(23) -#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF2_GPIO21_EDGE_LOW -#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_LOW_BITS _u(0x00400000) -#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_LOW_MSB _u(22) -#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_LOW_LSB _u(22) -#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_HIGH -#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_HIGH_BITS _u(0x00200000) -#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_HIGH_MSB _u(21) -#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_HIGH_LSB _u(21) -#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_LOW -#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_LOW_BITS _u(0x00100000) -#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_LOW_MSB _u(20) -#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_LOW_LSB _u(20) -#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF2_GPIO20_EDGE_HIGH -#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_HIGH_BITS _u(0x00080000) -#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_HIGH_MSB _u(19) -#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_HIGH_LSB _u(19) -#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF2_GPIO20_EDGE_LOW -#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_LOW_BITS _u(0x00040000) -#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_LOW_MSB _u(18) -#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_LOW_LSB _u(18) -#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_HIGH -#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_HIGH_BITS _u(0x00020000) -#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_HIGH_MSB _u(17) -#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_HIGH_LSB _u(17) -#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_LOW -#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_LOW_BITS _u(0x00010000) -#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_LOW_MSB _u(16) -#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_LOW_LSB _u(16) -#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF2_GPIO19_EDGE_HIGH -#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_HIGH_BITS _u(0x00008000) -#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_HIGH_MSB _u(15) -#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_HIGH_LSB _u(15) -#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF2_GPIO19_EDGE_LOW -#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_LOW_BITS _u(0x00004000) -#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_LOW_MSB _u(14) -#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_LOW_LSB _u(14) -#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_HIGH -#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_HIGH_BITS _u(0x00002000) -#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_HIGH_MSB _u(13) -#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_HIGH_LSB _u(13) -#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_LOW -#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_LOW_BITS _u(0x00001000) -#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_LOW_MSB _u(12) -#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_LOW_LSB _u(12) -#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF2_GPIO18_EDGE_HIGH -#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_HIGH_BITS _u(0x00000800) -#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_HIGH_MSB _u(11) -#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_HIGH_LSB _u(11) -#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF2_GPIO18_EDGE_LOW -#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_LOW_BITS _u(0x00000400) -#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_LOW_MSB _u(10) -#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_LOW_LSB _u(10) -#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_HIGH -#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_HIGH_BITS _u(0x00000200) -#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_HIGH_MSB _u(9) -#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_HIGH_LSB _u(9) -#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_LOW -#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_LOW_BITS _u(0x00000100) -#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_LOW_MSB _u(8) -#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_LOW_LSB _u(8) -#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF2_GPIO17_EDGE_HIGH -#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_HIGH_BITS _u(0x00000080) -#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_HIGH_MSB _u(7) -#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_HIGH_LSB _u(7) -#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF2_GPIO17_EDGE_LOW -#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_LOW_BITS _u(0x00000040) -#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_LOW_MSB _u(6) -#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_LOW_LSB _u(6) -#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_HIGH -#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_HIGH_BITS _u(0x00000020) -#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_HIGH_MSB _u(5) -#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_HIGH_LSB _u(5) -#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_LOW -#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_LOW_BITS _u(0x00000010) -#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_LOW_MSB _u(4) -#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_LOW_LSB _u(4) -#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF2_GPIO16_EDGE_HIGH -#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_HIGH_BITS _u(0x00000008) -#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_HIGH_MSB _u(3) -#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_HIGH_LSB _u(3) -#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF2_GPIO16_EDGE_LOW -#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_LOW_BITS _u(0x00000004) -#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_LOW_MSB _u(2) -#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_LOW_LSB _u(2) -#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_HIGH -#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_HIGH_BITS _u(0x00000002) -#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_HIGH_MSB _u(1) -#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_HIGH_LSB _u(1) -#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_LOW -#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_LOW_BITS _u(0x00000001) -#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_LOW_MSB _u(0) -#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_LOW_LSB _u(0) -#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_LOW_ACCESS "RW" -// ============================================================================= -// Register : IO_BANK0_PROC1_INTF3 -// Description : Interrupt Force for proc1 -#define IO_BANK0_PROC1_INTF3_OFFSET _u(0x0000014c) -#define IO_BANK0_PROC1_INTF3_BITS _u(0x00ffffff) -#define IO_BANK0_PROC1_INTF3_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF3_GPIO29_EDGE_HIGH -#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_HIGH_BITS _u(0x00800000) -#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_HIGH_MSB _u(23) -#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_HIGH_LSB _u(23) -#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF3_GPIO29_EDGE_LOW -#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_LOW_BITS _u(0x00400000) -#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_LOW_MSB _u(22) -#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_LOW_LSB _u(22) -#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_HIGH -#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_HIGH_BITS _u(0x00200000) -#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_HIGH_MSB _u(21) -#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_HIGH_LSB _u(21) -#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_LOW -#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_LOW_BITS _u(0x00100000) -#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_LOW_MSB _u(20) -#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_LOW_LSB _u(20) -#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF3_GPIO28_EDGE_HIGH -#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_HIGH_BITS _u(0x00080000) -#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_HIGH_MSB _u(19) -#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_HIGH_LSB _u(19) -#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF3_GPIO28_EDGE_LOW -#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_LOW_BITS _u(0x00040000) -#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_LOW_MSB _u(18) -#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_LOW_LSB _u(18) -#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_HIGH -#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_HIGH_BITS _u(0x00020000) -#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_HIGH_MSB _u(17) -#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_HIGH_LSB _u(17) -#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_LOW -#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_LOW_BITS _u(0x00010000) -#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_LOW_MSB _u(16) -#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_LOW_LSB _u(16) -#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF3_GPIO27_EDGE_HIGH -#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_HIGH_BITS _u(0x00008000) -#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_HIGH_MSB _u(15) -#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_HIGH_LSB _u(15) -#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF3_GPIO27_EDGE_LOW -#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_LOW_BITS _u(0x00004000) -#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_LOW_MSB _u(14) -#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_LOW_LSB _u(14) -#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_HIGH -#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_HIGH_BITS _u(0x00002000) -#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_HIGH_MSB _u(13) -#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_HIGH_LSB _u(13) -#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_LOW -#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_LOW_BITS _u(0x00001000) -#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_LOW_MSB _u(12) -#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_LOW_LSB _u(12) -#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF3_GPIO26_EDGE_HIGH -#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_HIGH_BITS _u(0x00000800) -#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_HIGH_MSB _u(11) -#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_HIGH_LSB _u(11) -#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF3_GPIO26_EDGE_LOW -#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_LOW_BITS _u(0x00000400) -#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_LOW_MSB _u(10) -#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_LOW_LSB _u(10) -#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_HIGH -#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_HIGH_BITS _u(0x00000200) -#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_HIGH_MSB _u(9) -#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_HIGH_LSB _u(9) -#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_LOW -#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_LOW_BITS _u(0x00000100) -#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_LOW_MSB _u(8) -#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_LOW_LSB _u(8) -#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF3_GPIO25_EDGE_HIGH -#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_HIGH_BITS _u(0x00000080) -#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_HIGH_MSB _u(7) -#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_HIGH_LSB _u(7) -#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF3_GPIO25_EDGE_LOW -#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_LOW_BITS _u(0x00000040) -#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_LOW_MSB _u(6) -#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_LOW_LSB _u(6) -#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_HIGH -#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_HIGH_BITS _u(0x00000020) -#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_HIGH_MSB _u(5) -#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_HIGH_LSB _u(5) -#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_LOW -#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_LOW_BITS _u(0x00000010) -#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_LOW_MSB _u(4) -#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_LOW_LSB _u(4) -#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF3_GPIO24_EDGE_HIGH -#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_HIGH_BITS _u(0x00000008) -#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_HIGH_MSB _u(3) -#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_HIGH_LSB _u(3) -#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF3_GPIO24_EDGE_LOW -#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_LOW_BITS _u(0x00000004) -#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_LOW_MSB _u(2) -#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_LOW_LSB _u(2) -#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_HIGH -#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_HIGH_BITS _u(0x00000002) -#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_HIGH_MSB _u(1) -#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_HIGH_LSB _u(1) -#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_LOW -#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_LOW_BITS _u(0x00000001) -#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_LOW_MSB _u(0) -#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_LOW_LSB _u(0) -#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_LOW_ACCESS "RW" -// ============================================================================= -// Register : IO_BANK0_PROC1_INTS0 -// Description : Interrupt status after masking & forcing for proc1 -#define IO_BANK0_PROC1_INTS0_OFFSET _u(0x00000150) -#define IO_BANK0_PROC1_INTS0_BITS _u(0xffffffff) -#define IO_BANK0_PROC1_INTS0_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS0_GPIO7_EDGE_HIGH -#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_HIGH_BITS _u(0x80000000) -#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_HIGH_MSB _u(31) -#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_HIGH_LSB _u(31) -#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS0_GPIO7_EDGE_LOW -#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_LOW_BITS _u(0x40000000) -#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_LOW_MSB _u(30) -#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_LOW_LSB _u(30) -#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_HIGH -#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_HIGH_BITS _u(0x20000000) -#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_HIGH_MSB _u(29) -#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_HIGH_LSB _u(29) -#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_LOW -#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_LOW_BITS _u(0x10000000) -#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_LOW_MSB _u(28) -#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_LOW_LSB _u(28) -#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS0_GPIO6_EDGE_HIGH -#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_HIGH_BITS _u(0x08000000) -#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_HIGH_MSB _u(27) -#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_HIGH_LSB _u(27) -#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS0_GPIO6_EDGE_LOW -#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_LOW_BITS _u(0x04000000) -#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_LOW_MSB _u(26) -#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_LOW_LSB _u(26) -#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_HIGH -#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_HIGH_BITS _u(0x02000000) -#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_HIGH_MSB _u(25) -#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_HIGH_LSB _u(25) -#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_LOW -#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_LOW_BITS _u(0x01000000) -#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_LOW_MSB _u(24) -#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_LOW_LSB _u(24) -#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS0_GPIO5_EDGE_HIGH -#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_HIGH_BITS _u(0x00800000) -#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_HIGH_MSB _u(23) -#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_HIGH_LSB _u(23) -#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS0_GPIO5_EDGE_LOW -#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_LOW_BITS _u(0x00400000) -#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_LOW_MSB _u(22) -#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_LOW_LSB _u(22) -#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_HIGH -#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_HIGH_BITS _u(0x00200000) -#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_HIGH_MSB _u(21) -#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_HIGH_LSB _u(21) -#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_LOW -#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_LOW_BITS _u(0x00100000) -#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_LOW_MSB _u(20) -#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_LOW_LSB _u(20) -#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS0_GPIO4_EDGE_HIGH -#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_HIGH_BITS _u(0x00080000) -#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_HIGH_MSB _u(19) -#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_HIGH_LSB _u(19) -#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS0_GPIO4_EDGE_LOW -#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_LOW_BITS _u(0x00040000) -#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_LOW_MSB _u(18) -#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_LOW_LSB _u(18) -#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_HIGH -#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_HIGH_BITS _u(0x00020000) -#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_HIGH_MSB _u(17) -#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_HIGH_LSB _u(17) -#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_LOW -#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_LOW_BITS _u(0x00010000) -#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_LOW_MSB _u(16) -#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_LOW_LSB _u(16) -#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS0_GPIO3_EDGE_HIGH -#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_HIGH_BITS _u(0x00008000) -#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_HIGH_MSB _u(15) -#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_HIGH_LSB _u(15) -#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS0_GPIO3_EDGE_LOW -#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_LOW_BITS _u(0x00004000) -#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_LOW_MSB _u(14) -#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_LOW_LSB _u(14) -#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_HIGH -#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_HIGH_BITS _u(0x00002000) -#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_HIGH_MSB _u(13) -#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_HIGH_LSB _u(13) -#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_LOW -#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_LOW_BITS _u(0x00001000) -#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_LOW_MSB _u(12) -#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_LOW_LSB _u(12) -#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS0_GPIO2_EDGE_HIGH -#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_HIGH_BITS _u(0x00000800) -#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_HIGH_MSB _u(11) -#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_HIGH_LSB _u(11) -#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS0_GPIO2_EDGE_LOW -#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_LOW_BITS _u(0x00000400) -#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_LOW_MSB _u(10) -#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_LOW_LSB _u(10) -#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_HIGH -#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_HIGH_BITS _u(0x00000200) -#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_HIGH_MSB _u(9) -#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_HIGH_LSB _u(9) -#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_LOW -#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_LOW_BITS _u(0x00000100) -#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_LOW_MSB _u(8) -#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_LOW_LSB _u(8) -#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS0_GPIO1_EDGE_HIGH -#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_HIGH_BITS _u(0x00000080) -#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_HIGH_MSB _u(7) -#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_HIGH_LSB _u(7) -#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS0_GPIO1_EDGE_LOW -#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_LOW_BITS _u(0x00000040) -#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_LOW_MSB _u(6) -#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_LOW_LSB _u(6) -#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_HIGH -#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_HIGH_BITS _u(0x00000020) -#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_HIGH_MSB _u(5) -#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_HIGH_LSB _u(5) -#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_LOW -#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_LOW_BITS _u(0x00000010) -#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_LOW_MSB _u(4) -#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_LOW_LSB _u(4) -#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS0_GPIO0_EDGE_HIGH -#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_HIGH_BITS _u(0x00000008) -#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_HIGH_MSB _u(3) -#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_HIGH_LSB _u(3) -#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS0_GPIO0_EDGE_LOW -#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_LOW_BITS _u(0x00000004) -#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_LOW_MSB _u(2) -#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_LOW_LSB _u(2) -#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_HIGH -#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_HIGH_BITS _u(0x00000002) -#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_HIGH_MSB _u(1) -#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_HIGH_LSB _u(1) -#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_LOW -#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_LOW_BITS _u(0x00000001) -#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_LOW_MSB _u(0) -#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_LOW_LSB _u(0) -#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_LOW_ACCESS "RO" -// ============================================================================= -// Register : IO_BANK0_PROC1_INTS1 -// Description : Interrupt status after masking & forcing for proc1 -#define IO_BANK0_PROC1_INTS1_OFFSET _u(0x00000154) -#define IO_BANK0_PROC1_INTS1_BITS _u(0xffffffff) -#define IO_BANK0_PROC1_INTS1_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS1_GPIO15_EDGE_HIGH -#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_HIGH_BITS _u(0x80000000) -#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_HIGH_MSB _u(31) -#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_HIGH_LSB _u(31) -#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS1_GPIO15_EDGE_LOW -#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_LOW_BITS _u(0x40000000) -#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_LOW_MSB _u(30) -#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_LOW_LSB _u(30) -#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_HIGH -#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_HIGH_BITS _u(0x20000000) -#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_HIGH_MSB _u(29) -#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_HIGH_LSB _u(29) -#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_LOW -#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_LOW_BITS _u(0x10000000) -#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_LOW_MSB _u(28) -#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_LOW_LSB _u(28) -#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS1_GPIO14_EDGE_HIGH -#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_HIGH_BITS _u(0x08000000) -#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_HIGH_MSB _u(27) -#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_HIGH_LSB _u(27) -#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS1_GPIO14_EDGE_LOW -#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_LOW_BITS _u(0x04000000) -#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_LOW_MSB _u(26) -#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_LOW_LSB _u(26) -#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_HIGH -#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_HIGH_BITS _u(0x02000000) -#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_HIGH_MSB _u(25) -#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_HIGH_LSB _u(25) -#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_LOW -#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_LOW_BITS _u(0x01000000) -#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_LOW_MSB _u(24) -#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_LOW_LSB _u(24) -#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS1_GPIO13_EDGE_HIGH -#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_HIGH_BITS _u(0x00800000) -#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_HIGH_MSB _u(23) -#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_HIGH_LSB _u(23) -#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS1_GPIO13_EDGE_LOW -#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_LOW_BITS _u(0x00400000) -#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_LOW_MSB _u(22) -#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_LOW_LSB _u(22) -#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_HIGH -#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_HIGH_BITS _u(0x00200000) -#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_HIGH_MSB _u(21) -#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_HIGH_LSB _u(21) -#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_LOW -#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_LOW_BITS _u(0x00100000) -#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_LOW_MSB _u(20) -#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_LOW_LSB _u(20) -#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS1_GPIO12_EDGE_HIGH -#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_HIGH_BITS _u(0x00080000) -#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_HIGH_MSB _u(19) -#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_HIGH_LSB _u(19) -#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS1_GPIO12_EDGE_LOW -#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_LOW_BITS _u(0x00040000) -#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_LOW_MSB _u(18) -#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_LOW_LSB _u(18) -#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_HIGH -#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_HIGH_BITS _u(0x00020000) -#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_HIGH_MSB _u(17) -#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_HIGH_LSB _u(17) -#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_LOW -#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_LOW_BITS _u(0x00010000) -#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_LOW_MSB _u(16) -#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_LOW_LSB _u(16) -#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS1_GPIO11_EDGE_HIGH -#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_HIGH_BITS _u(0x00008000) -#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_HIGH_MSB _u(15) -#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_HIGH_LSB _u(15) -#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS1_GPIO11_EDGE_LOW -#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_LOW_BITS _u(0x00004000) -#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_LOW_MSB _u(14) -#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_LOW_LSB _u(14) -#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_HIGH -#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_HIGH_BITS _u(0x00002000) -#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_HIGH_MSB _u(13) -#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_HIGH_LSB _u(13) -#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_LOW -#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_LOW_BITS _u(0x00001000) -#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_LOW_MSB _u(12) -#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_LOW_LSB _u(12) -#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS1_GPIO10_EDGE_HIGH -#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_HIGH_BITS _u(0x00000800) -#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_HIGH_MSB _u(11) -#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_HIGH_LSB _u(11) -#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS1_GPIO10_EDGE_LOW -#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_LOW_BITS _u(0x00000400) -#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_LOW_MSB _u(10) -#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_LOW_LSB _u(10) -#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_HIGH -#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_HIGH_BITS _u(0x00000200) -#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_HIGH_MSB _u(9) -#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_HIGH_LSB _u(9) -#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_LOW -#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_LOW_BITS _u(0x00000100) -#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_LOW_MSB _u(8) -#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_LOW_LSB _u(8) -#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS1_GPIO9_EDGE_HIGH -#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_HIGH_BITS _u(0x00000080) -#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_HIGH_MSB _u(7) -#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_HIGH_LSB _u(7) -#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS1_GPIO9_EDGE_LOW -#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_LOW_BITS _u(0x00000040) -#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_LOW_MSB _u(6) -#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_LOW_LSB _u(6) -#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_HIGH -#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_HIGH_BITS _u(0x00000020) -#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_HIGH_MSB _u(5) -#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_HIGH_LSB _u(5) -#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_LOW -#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_LOW_BITS _u(0x00000010) -#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_LOW_MSB _u(4) -#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_LOW_LSB _u(4) -#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS1_GPIO8_EDGE_HIGH -#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_HIGH_BITS _u(0x00000008) -#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_HIGH_MSB _u(3) -#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_HIGH_LSB _u(3) -#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS1_GPIO8_EDGE_LOW -#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_LOW_BITS _u(0x00000004) -#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_LOW_MSB _u(2) -#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_LOW_LSB _u(2) -#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_HIGH -#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_HIGH_BITS _u(0x00000002) -#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_HIGH_MSB _u(1) -#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_HIGH_LSB _u(1) -#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_LOW -#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_LOW_BITS _u(0x00000001) -#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_LOW_MSB _u(0) -#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_LOW_LSB _u(0) -#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_LOW_ACCESS "RO" -// ============================================================================= -// Register : IO_BANK0_PROC1_INTS2 -// Description : Interrupt status after masking & forcing for proc1 -#define IO_BANK0_PROC1_INTS2_OFFSET _u(0x00000158) -#define IO_BANK0_PROC1_INTS2_BITS _u(0xffffffff) -#define IO_BANK0_PROC1_INTS2_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS2_GPIO23_EDGE_HIGH -#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_HIGH_BITS _u(0x80000000) -#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_HIGH_MSB _u(31) -#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_HIGH_LSB _u(31) -#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS2_GPIO23_EDGE_LOW -#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_LOW_BITS _u(0x40000000) -#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_LOW_MSB _u(30) -#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_LOW_LSB _u(30) -#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_HIGH -#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_HIGH_BITS _u(0x20000000) -#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_HIGH_MSB _u(29) -#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_HIGH_LSB _u(29) -#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_LOW -#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_LOW_BITS _u(0x10000000) -#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_LOW_MSB _u(28) -#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_LOW_LSB _u(28) -#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS2_GPIO22_EDGE_HIGH -#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_HIGH_BITS _u(0x08000000) -#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_HIGH_MSB _u(27) -#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_HIGH_LSB _u(27) -#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS2_GPIO22_EDGE_LOW -#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_LOW_BITS _u(0x04000000) -#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_LOW_MSB _u(26) -#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_LOW_LSB _u(26) -#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_HIGH -#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_HIGH_BITS _u(0x02000000) -#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_HIGH_MSB _u(25) -#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_HIGH_LSB _u(25) -#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_LOW -#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_LOW_BITS _u(0x01000000) -#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_LOW_MSB _u(24) -#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_LOW_LSB _u(24) -#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS2_GPIO21_EDGE_HIGH -#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_HIGH_BITS _u(0x00800000) -#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_HIGH_MSB _u(23) -#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_HIGH_LSB _u(23) -#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS2_GPIO21_EDGE_LOW -#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_LOW_BITS _u(0x00400000) -#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_LOW_MSB _u(22) -#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_LOW_LSB _u(22) -#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_HIGH -#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_HIGH_BITS _u(0x00200000) -#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_HIGH_MSB _u(21) -#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_HIGH_LSB _u(21) -#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_LOW -#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_LOW_BITS _u(0x00100000) -#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_LOW_MSB _u(20) -#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_LOW_LSB _u(20) -#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS2_GPIO20_EDGE_HIGH -#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_HIGH_BITS _u(0x00080000) -#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_HIGH_MSB _u(19) -#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_HIGH_LSB _u(19) -#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS2_GPIO20_EDGE_LOW -#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_LOW_BITS _u(0x00040000) -#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_LOW_MSB _u(18) -#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_LOW_LSB _u(18) -#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_HIGH -#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_HIGH_BITS _u(0x00020000) -#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_HIGH_MSB _u(17) -#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_HIGH_LSB _u(17) -#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_LOW -#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_LOW_BITS _u(0x00010000) -#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_LOW_MSB _u(16) -#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_LOW_LSB _u(16) -#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS2_GPIO19_EDGE_HIGH -#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_HIGH_BITS _u(0x00008000) -#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_HIGH_MSB _u(15) -#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_HIGH_LSB _u(15) -#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS2_GPIO19_EDGE_LOW -#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_LOW_BITS _u(0x00004000) -#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_LOW_MSB _u(14) -#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_LOW_LSB _u(14) -#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_HIGH -#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_HIGH_BITS _u(0x00002000) -#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_HIGH_MSB _u(13) -#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_HIGH_LSB _u(13) -#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_LOW -#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_LOW_BITS _u(0x00001000) -#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_LOW_MSB _u(12) -#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_LOW_LSB _u(12) -#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS2_GPIO18_EDGE_HIGH -#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_HIGH_BITS _u(0x00000800) -#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_HIGH_MSB _u(11) -#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_HIGH_LSB _u(11) -#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS2_GPIO18_EDGE_LOW -#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_LOW_BITS _u(0x00000400) -#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_LOW_MSB _u(10) -#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_LOW_LSB _u(10) -#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_HIGH -#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_HIGH_BITS _u(0x00000200) -#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_HIGH_MSB _u(9) -#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_HIGH_LSB _u(9) -#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_LOW -#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_LOW_BITS _u(0x00000100) -#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_LOW_MSB _u(8) -#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_LOW_LSB _u(8) -#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS2_GPIO17_EDGE_HIGH -#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_HIGH_BITS _u(0x00000080) -#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_HIGH_MSB _u(7) -#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_HIGH_LSB _u(7) -#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS2_GPIO17_EDGE_LOW -#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_LOW_BITS _u(0x00000040) -#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_LOW_MSB _u(6) -#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_LOW_LSB _u(6) -#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_HIGH -#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_HIGH_BITS _u(0x00000020) -#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_HIGH_MSB _u(5) -#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_HIGH_LSB _u(5) -#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_LOW -#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_LOW_BITS _u(0x00000010) -#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_LOW_MSB _u(4) -#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_LOW_LSB _u(4) -#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS2_GPIO16_EDGE_HIGH -#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_HIGH_BITS _u(0x00000008) -#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_HIGH_MSB _u(3) -#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_HIGH_LSB _u(3) -#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS2_GPIO16_EDGE_LOW -#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_LOW_BITS _u(0x00000004) -#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_LOW_MSB _u(2) -#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_LOW_LSB _u(2) -#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_HIGH -#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_HIGH_BITS _u(0x00000002) -#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_HIGH_MSB _u(1) -#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_HIGH_LSB _u(1) -#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_LOW -#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_LOW_BITS _u(0x00000001) -#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_LOW_MSB _u(0) -#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_LOW_LSB _u(0) -#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_LOW_ACCESS "RO" -// ============================================================================= -// Register : IO_BANK0_PROC1_INTS3 -// Description : Interrupt status after masking & forcing for proc1 -#define IO_BANK0_PROC1_INTS3_OFFSET _u(0x0000015c) -#define IO_BANK0_PROC1_INTS3_BITS _u(0x00ffffff) -#define IO_BANK0_PROC1_INTS3_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS3_GPIO29_EDGE_HIGH -#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_HIGH_BITS _u(0x00800000) -#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_HIGH_MSB _u(23) -#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_HIGH_LSB _u(23) -#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS3_GPIO29_EDGE_LOW -#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_LOW_BITS _u(0x00400000) -#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_LOW_MSB _u(22) -#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_LOW_LSB _u(22) -#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_HIGH -#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_HIGH_BITS _u(0x00200000) -#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_HIGH_MSB _u(21) -#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_HIGH_LSB _u(21) -#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_LOW -#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_LOW_BITS _u(0x00100000) -#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_LOW_MSB _u(20) -#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_LOW_LSB _u(20) -#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS3_GPIO28_EDGE_HIGH -#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_HIGH_BITS _u(0x00080000) -#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_HIGH_MSB _u(19) -#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_HIGH_LSB _u(19) -#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS3_GPIO28_EDGE_LOW -#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_LOW_BITS _u(0x00040000) -#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_LOW_MSB _u(18) -#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_LOW_LSB _u(18) -#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_HIGH -#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_HIGH_BITS _u(0x00020000) -#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_HIGH_MSB _u(17) -#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_HIGH_LSB _u(17) -#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_LOW -#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_LOW_BITS _u(0x00010000) -#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_LOW_MSB _u(16) -#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_LOW_LSB _u(16) -#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS3_GPIO27_EDGE_HIGH -#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_HIGH_BITS _u(0x00008000) -#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_HIGH_MSB _u(15) -#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_HIGH_LSB _u(15) -#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS3_GPIO27_EDGE_LOW -#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_LOW_BITS _u(0x00004000) -#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_LOW_MSB _u(14) -#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_LOW_LSB _u(14) -#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_HIGH -#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_HIGH_BITS _u(0x00002000) -#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_HIGH_MSB _u(13) -#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_HIGH_LSB _u(13) -#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_LOW -#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_LOW_BITS _u(0x00001000) -#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_LOW_MSB _u(12) -#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_LOW_LSB _u(12) -#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS3_GPIO26_EDGE_HIGH -#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_HIGH_BITS _u(0x00000800) -#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_HIGH_MSB _u(11) -#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_HIGH_LSB _u(11) -#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS3_GPIO26_EDGE_LOW -#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_LOW_BITS _u(0x00000400) -#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_LOW_MSB _u(10) -#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_LOW_LSB _u(10) -#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_HIGH -#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_HIGH_BITS _u(0x00000200) -#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_HIGH_MSB _u(9) -#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_HIGH_LSB _u(9) -#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_LOW -#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_LOW_BITS _u(0x00000100) -#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_LOW_MSB _u(8) -#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_LOW_LSB _u(8) -#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS3_GPIO25_EDGE_HIGH -#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_HIGH_BITS _u(0x00000080) -#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_HIGH_MSB _u(7) -#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_HIGH_LSB _u(7) -#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS3_GPIO25_EDGE_LOW -#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_LOW_BITS _u(0x00000040) -#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_LOW_MSB _u(6) -#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_LOW_LSB _u(6) -#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_HIGH -#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_HIGH_BITS _u(0x00000020) -#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_HIGH_MSB _u(5) -#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_HIGH_LSB _u(5) -#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_LOW -#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_LOW_BITS _u(0x00000010) -#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_LOW_MSB _u(4) -#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_LOW_LSB _u(4) -#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS3_GPIO24_EDGE_HIGH -#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_HIGH_BITS _u(0x00000008) -#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_HIGH_MSB _u(3) -#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_HIGH_LSB _u(3) -#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS3_GPIO24_EDGE_LOW -#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_LOW_BITS _u(0x00000004) -#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_LOW_MSB _u(2) -#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_LOW_LSB _u(2) -#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_HIGH -#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_HIGH_BITS _u(0x00000002) -#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_HIGH_MSB _u(1) -#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_HIGH_LSB _u(1) -#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_LOW -#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_LOW_BITS _u(0x00000001) -#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_LOW_MSB _u(0) -#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_LOW_LSB _u(0) -#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_LOW_ACCESS "RO" -// ============================================================================= -// Register : IO_BANK0_DORMANT_WAKE_INTE0 -// Description : Interrupt Enable for dormant_wake -#define IO_BANK0_DORMANT_WAKE_INTE0_OFFSET _u(0x00000160) -#define IO_BANK0_DORMANT_WAKE_INTE0_BITS _u(0xffffffff) -#define IO_BANK0_DORMANT_WAKE_INTE0_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_HIGH_BITS _u(0x80000000) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_HIGH_MSB _u(31) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_HIGH_LSB _u(31) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_LOW_BITS _u(0x40000000) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_LOW_MSB _u(30) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_LOW_LSB _u(30) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_HIGH_BITS _u(0x20000000) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_HIGH_MSB _u(29) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_HIGH_LSB _u(29) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_LOW_BITS _u(0x10000000) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_LOW_MSB _u(28) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_LOW_LSB _u(28) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_HIGH_BITS _u(0x08000000) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_HIGH_MSB _u(27) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_HIGH_LSB _u(27) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_LOW_BITS _u(0x04000000) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_LOW_MSB _u(26) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_LOW_LSB _u(26) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_HIGH_BITS _u(0x02000000) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_HIGH_MSB _u(25) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_HIGH_LSB _u(25) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_LOW_BITS _u(0x01000000) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_LOW_MSB _u(24) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_LOW_LSB _u(24) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_HIGH_BITS _u(0x00800000) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_HIGH_MSB _u(23) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_HIGH_LSB _u(23) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_LOW_BITS _u(0x00400000) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_LOW_MSB _u(22) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_LOW_LSB _u(22) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_HIGH_BITS _u(0x00200000) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_HIGH_MSB _u(21) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_HIGH_LSB _u(21) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_LOW_BITS _u(0x00100000) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_LOW_MSB _u(20) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_LOW_LSB _u(20) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_HIGH_BITS _u(0x00080000) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_HIGH_MSB _u(19) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_HIGH_LSB _u(19) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_LOW_BITS _u(0x00040000) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_LOW_MSB _u(18) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_LOW_LSB _u(18) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_HIGH_BITS _u(0x00020000) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_HIGH_MSB _u(17) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_HIGH_LSB _u(17) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_LOW_BITS _u(0x00010000) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_LOW_MSB _u(16) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_LOW_LSB _u(16) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_HIGH_BITS _u(0x00008000) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_HIGH_MSB _u(15) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_HIGH_LSB _u(15) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_LOW_BITS _u(0x00004000) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_LOW_MSB _u(14) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_LOW_LSB _u(14) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_HIGH_BITS _u(0x00002000) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_HIGH_MSB _u(13) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_HIGH_LSB _u(13) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_LOW_BITS _u(0x00001000) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_LOW_MSB _u(12) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_LOW_LSB _u(12) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_HIGH_BITS _u(0x00000800) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_HIGH_MSB _u(11) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_HIGH_LSB _u(11) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_LOW_BITS _u(0x00000400) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_LOW_MSB _u(10) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_LOW_LSB _u(10) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_HIGH_BITS _u(0x00000200) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_HIGH_MSB _u(9) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_HIGH_LSB _u(9) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_LOW_BITS _u(0x00000100) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_LOW_MSB _u(8) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_LOW_LSB _u(8) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_HIGH_BITS _u(0x00000080) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_HIGH_MSB _u(7) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_HIGH_LSB _u(7) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_LOW_BITS _u(0x00000040) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_LOW_MSB _u(6) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_LOW_LSB _u(6) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_HIGH_BITS _u(0x00000020) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_HIGH_MSB _u(5) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_HIGH_LSB _u(5) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_LOW_BITS _u(0x00000010) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_LOW_MSB _u(4) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_LOW_LSB _u(4) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_HIGH_BITS _u(0x00000008) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_HIGH_MSB _u(3) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_HIGH_LSB _u(3) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_LOW_BITS _u(0x00000004) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_LOW_MSB _u(2) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_LOW_LSB _u(2) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_HIGH_BITS _u(0x00000002) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_HIGH_MSB _u(1) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_HIGH_LSB _u(1) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_LOW_BITS _u(0x00000001) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_LOW_MSB _u(0) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_LOW_LSB _u(0) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_LOW_ACCESS "RW" -// ============================================================================= -// Register : IO_BANK0_DORMANT_WAKE_INTE1 -// Description : Interrupt Enable for dormant_wake -#define IO_BANK0_DORMANT_WAKE_INTE1_OFFSET _u(0x00000164) -#define IO_BANK0_DORMANT_WAKE_INTE1_BITS _u(0xffffffff) -#define IO_BANK0_DORMANT_WAKE_INTE1_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_HIGH_BITS _u(0x80000000) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_HIGH_MSB _u(31) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_HIGH_LSB _u(31) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_LOW_BITS _u(0x40000000) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_LOW_MSB _u(30) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_LOW_LSB _u(30) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_HIGH_BITS _u(0x20000000) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_HIGH_MSB _u(29) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_HIGH_LSB _u(29) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_LOW_BITS _u(0x10000000) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_LOW_MSB _u(28) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_LOW_LSB _u(28) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_HIGH_BITS _u(0x08000000) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_HIGH_MSB _u(27) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_HIGH_LSB _u(27) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_LOW_BITS _u(0x04000000) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_LOW_MSB _u(26) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_LOW_LSB _u(26) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_HIGH_BITS _u(0x02000000) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_HIGH_MSB _u(25) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_HIGH_LSB _u(25) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_LOW_BITS _u(0x01000000) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_LOW_MSB _u(24) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_LOW_LSB _u(24) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_HIGH_BITS _u(0x00800000) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_HIGH_MSB _u(23) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_HIGH_LSB _u(23) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_LOW_BITS _u(0x00400000) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_LOW_MSB _u(22) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_LOW_LSB _u(22) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_HIGH_BITS _u(0x00200000) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_HIGH_MSB _u(21) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_HIGH_LSB _u(21) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_LOW_BITS _u(0x00100000) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_LOW_MSB _u(20) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_LOW_LSB _u(20) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_HIGH_BITS _u(0x00080000) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_HIGH_MSB _u(19) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_HIGH_LSB _u(19) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_LOW_BITS _u(0x00040000) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_LOW_MSB _u(18) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_LOW_LSB _u(18) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_HIGH_BITS _u(0x00020000) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_HIGH_MSB _u(17) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_HIGH_LSB _u(17) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_LOW_BITS _u(0x00010000) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_LOW_MSB _u(16) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_LOW_LSB _u(16) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_HIGH_BITS _u(0x00008000) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_HIGH_MSB _u(15) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_HIGH_LSB _u(15) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_LOW_BITS _u(0x00004000) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_LOW_MSB _u(14) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_LOW_LSB _u(14) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_HIGH_BITS _u(0x00002000) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_HIGH_MSB _u(13) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_HIGH_LSB _u(13) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_LOW_BITS _u(0x00001000) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_LOW_MSB _u(12) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_LOW_LSB _u(12) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_HIGH_BITS _u(0x00000800) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_HIGH_MSB _u(11) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_HIGH_LSB _u(11) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_LOW_BITS _u(0x00000400) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_LOW_MSB _u(10) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_LOW_LSB _u(10) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_HIGH_BITS _u(0x00000200) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_HIGH_MSB _u(9) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_HIGH_LSB _u(9) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_LOW_BITS _u(0x00000100) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_LOW_MSB _u(8) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_LOW_LSB _u(8) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_HIGH_BITS _u(0x00000080) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_HIGH_MSB _u(7) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_HIGH_LSB _u(7) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_LOW_BITS _u(0x00000040) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_LOW_MSB _u(6) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_LOW_LSB _u(6) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_HIGH_BITS _u(0x00000020) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_HIGH_MSB _u(5) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_HIGH_LSB _u(5) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_LOW_BITS _u(0x00000010) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_LOW_MSB _u(4) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_LOW_LSB _u(4) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_HIGH_BITS _u(0x00000008) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_HIGH_MSB _u(3) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_HIGH_LSB _u(3) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_LOW_BITS _u(0x00000004) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_LOW_MSB _u(2) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_LOW_LSB _u(2) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_HIGH_BITS _u(0x00000002) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_HIGH_MSB _u(1) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_HIGH_LSB _u(1) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_LOW_BITS _u(0x00000001) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_LOW_MSB _u(0) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_LOW_LSB _u(0) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_LOW_ACCESS "RW" -// ============================================================================= -// Register : IO_BANK0_DORMANT_WAKE_INTE2 -// Description : Interrupt Enable for dormant_wake -#define IO_BANK0_DORMANT_WAKE_INTE2_OFFSET _u(0x00000168) -#define IO_BANK0_DORMANT_WAKE_INTE2_BITS _u(0xffffffff) -#define IO_BANK0_DORMANT_WAKE_INTE2_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_HIGH_BITS _u(0x80000000) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_HIGH_MSB _u(31) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_HIGH_LSB _u(31) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_LOW_BITS _u(0x40000000) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_LOW_MSB _u(30) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_LOW_LSB _u(30) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_HIGH_BITS _u(0x20000000) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_HIGH_MSB _u(29) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_HIGH_LSB _u(29) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_LOW_BITS _u(0x10000000) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_LOW_MSB _u(28) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_LOW_LSB _u(28) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_HIGH_BITS _u(0x08000000) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_HIGH_MSB _u(27) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_HIGH_LSB _u(27) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_LOW_BITS _u(0x04000000) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_LOW_MSB _u(26) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_LOW_LSB _u(26) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_HIGH_BITS _u(0x02000000) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_HIGH_MSB _u(25) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_HIGH_LSB _u(25) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_LOW_BITS _u(0x01000000) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_LOW_MSB _u(24) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_LOW_LSB _u(24) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_HIGH_BITS _u(0x00800000) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_HIGH_MSB _u(23) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_HIGH_LSB _u(23) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_LOW_BITS _u(0x00400000) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_LOW_MSB _u(22) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_LOW_LSB _u(22) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_HIGH_BITS _u(0x00200000) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_HIGH_MSB _u(21) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_HIGH_LSB _u(21) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_LOW_BITS _u(0x00100000) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_LOW_MSB _u(20) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_LOW_LSB _u(20) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_HIGH_BITS _u(0x00080000) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_HIGH_MSB _u(19) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_HIGH_LSB _u(19) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_LOW_BITS _u(0x00040000) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_LOW_MSB _u(18) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_LOW_LSB _u(18) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_HIGH_BITS _u(0x00020000) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_HIGH_MSB _u(17) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_HIGH_LSB _u(17) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_LOW_BITS _u(0x00010000) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_LOW_MSB _u(16) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_LOW_LSB _u(16) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_HIGH_BITS _u(0x00008000) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_HIGH_MSB _u(15) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_HIGH_LSB _u(15) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_LOW_BITS _u(0x00004000) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_LOW_MSB _u(14) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_LOW_LSB _u(14) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_HIGH_BITS _u(0x00002000) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_HIGH_MSB _u(13) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_HIGH_LSB _u(13) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_LOW_BITS _u(0x00001000) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_LOW_MSB _u(12) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_LOW_LSB _u(12) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_HIGH_BITS _u(0x00000800) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_HIGH_MSB _u(11) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_HIGH_LSB _u(11) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_LOW_BITS _u(0x00000400) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_LOW_MSB _u(10) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_LOW_LSB _u(10) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_HIGH_BITS _u(0x00000200) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_HIGH_MSB _u(9) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_HIGH_LSB _u(9) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_LOW_BITS _u(0x00000100) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_LOW_MSB _u(8) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_LOW_LSB _u(8) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_HIGH_BITS _u(0x00000080) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_HIGH_MSB _u(7) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_HIGH_LSB _u(7) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_LOW_BITS _u(0x00000040) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_LOW_MSB _u(6) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_LOW_LSB _u(6) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_HIGH_BITS _u(0x00000020) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_HIGH_MSB _u(5) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_HIGH_LSB _u(5) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_LOW_BITS _u(0x00000010) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_LOW_MSB _u(4) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_LOW_LSB _u(4) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_HIGH_BITS _u(0x00000008) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_HIGH_MSB _u(3) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_HIGH_LSB _u(3) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_LOW_BITS _u(0x00000004) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_LOW_MSB _u(2) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_LOW_LSB _u(2) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_HIGH_BITS _u(0x00000002) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_HIGH_MSB _u(1) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_HIGH_LSB _u(1) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_LOW_BITS _u(0x00000001) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_LOW_MSB _u(0) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_LOW_LSB _u(0) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_LOW_ACCESS "RW" -// ============================================================================= -// Register : IO_BANK0_DORMANT_WAKE_INTE3 -// Description : Interrupt Enable for dormant_wake -#define IO_BANK0_DORMANT_WAKE_INTE3_OFFSET _u(0x0000016c) -#define IO_BANK0_DORMANT_WAKE_INTE3_BITS _u(0x00ffffff) -#define IO_BANK0_DORMANT_WAKE_INTE3_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_HIGH_BITS _u(0x00800000) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_HIGH_MSB _u(23) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_HIGH_LSB _u(23) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_LOW_BITS _u(0x00400000) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_LOW_MSB _u(22) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_LOW_LSB _u(22) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_HIGH_BITS _u(0x00200000) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_HIGH_MSB _u(21) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_HIGH_LSB _u(21) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_LOW_BITS _u(0x00100000) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_LOW_MSB _u(20) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_LOW_LSB _u(20) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_HIGH_BITS _u(0x00080000) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_HIGH_MSB _u(19) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_HIGH_LSB _u(19) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_LOW_BITS _u(0x00040000) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_LOW_MSB _u(18) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_LOW_LSB _u(18) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_HIGH_BITS _u(0x00020000) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_HIGH_MSB _u(17) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_HIGH_LSB _u(17) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_LOW_BITS _u(0x00010000) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_LOW_MSB _u(16) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_LOW_LSB _u(16) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_HIGH_BITS _u(0x00008000) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_HIGH_MSB _u(15) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_HIGH_LSB _u(15) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_LOW_BITS _u(0x00004000) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_LOW_MSB _u(14) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_LOW_LSB _u(14) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_HIGH_BITS _u(0x00002000) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_HIGH_MSB _u(13) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_HIGH_LSB _u(13) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_LOW_BITS _u(0x00001000) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_LOW_MSB _u(12) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_LOW_LSB _u(12) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_HIGH_BITS _u(0x00000800) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_HIGH_MSB _u(11) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_HIGH_LSB _u(11) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_LOW_BITS _u(0x00000400) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_LOW_MSB _u(10) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_LOW_LSB _u(10) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_HIGH_BITS _u(0x00000200) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_HIGH_MSB _u(9) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_HIGH_LSB _u(9) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_LOW_BITS _u(0x00000100) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_LOW_MSB _u(8) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_LOW_LSB _u(8) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_HIGH_BITS _u(0x00000080) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_HIGH_MSB _u(7) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_HIGH_LSB _u(7) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_LOW_BITS _u(0x00000040) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_LOW_MSB _u(6) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_LOW_LSB _u(6) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_HIGH_BITS _u(0x00000020) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_HIGH_MSB _u(5) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_HIGH_LSB _u(5) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_LOW_BITS _u(0x00000010) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_LOW_MSB _u(4) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_LOW_LSB _u(4) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_HIGH_BITS _u(0x00000008) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_HIGH_MSB _u(3) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_HIGH_LSB _u(3) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_LOW_BITS _u(0x00000004) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_LOW_MSB _u(2) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_LOW_LSB _u(2) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_HIGH_BITS _u(0x00000002) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_HIGH_MSB _u(1) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_HIGH_LSB _u(1) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_LOW_BITS _u(0x00000001) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_LOW_MSB _u(0) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_LOW_LSB _u(0) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_LOW_ACCESS "RW" -// ============================================================================= -// Register : IO_BANK0_DORMANT_WAKE_INTF0 -// Description : Interrupt Force for dormant_wake -#define IO_BANK0_DORMANT_WAKE_INTF0_OFFSET _u(0x00000170) -#define IO_BANK0_DORMANT_WAKE_INTF0_BITS _u(0xffffffff) -#define IO_BANK0_DORMANT_WAKE_INTF0_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_HIGH_BITS _u(0x80000000) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_HIGH_MSB _u(31) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_HIGH_LSB _u(31) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_LOW_BITS _u(0x40000000) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_LOW_MSB _u(30) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_LOW_LSB _u(30) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_HIGH_BITS _u(0x20000000) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_HIGH_MSB _u(29) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_HIGH_LSB _u(29) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_LOW_BITS _u(0x10000000) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_LOW_MSB _u(28) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_LOW_LSB _u(28) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_HIGH_BITS _u(0x08000000) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_HIGH_MSB _u(27) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_HIGH_LSB _u(27) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_LOW_BITS _u(0x04000000) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_LOW_MSB _u(26) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_LOW_LSB _u(26) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_HIGH_BITS _u(0x02000000) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_HIGH_MSB _u(25) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_HIGH_LSB _u(25) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_LOW_BITS _u(0x01000000) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_LOW_MSB _u(24) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_LOW_LSB _u(24) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_HIGH_BITS _u(0x00800000) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_HIGH_MSB _u(23) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_HIGH_LSB _u(23) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_LOW_BITS _u(0x00400000) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_LOW_MSB _u(22) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_LOW_LSB _u(22) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_HIGH_BITS _u(0x00200000) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_HIGH_MSB _u(21) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_HIGH_LSB _u(21) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_LOW_BITS _u(0x00100000) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_LOW_MSB _u(20) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_LOW_LSB _u(20) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_HIGH_BITS _u(0x00080000) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_HIGH_MSB _u(19) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_HIGH_LSB _u(19) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_LOW_BITS _u(0x00040000) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_LOW_MSB _u(18) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_LOW_LSB _u(18) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_HIGH_BITS _u(0x00020000) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_HIGH_MSB _u(17) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_HIGH_LSB _u(17) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_LOW_BITS _u(0x00010000) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_LOW_MSB _u(16) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_LOW_LSB _u(16) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_HIGH_BITS _u(0x00008000) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_HIGH_MSB _u(15) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_HIGH_LSB _u(15) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_LOW_BITS _u(0x00004000) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_LOW_MSB _u(14) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_LOW_LSB _u(14) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_HIGH_BITS _u(0x00002000) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_HIGH_MSB _u(13) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_HIGH_LSB _u(13) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_LOW_BITS _u(0x00001000) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_LOW_MSB _u(12) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_LOW_LSB _u(12) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_HIGH_BITS _u(0x00000800) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_HIGH_MSB _u(11) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_HIGH_LSB _u(11) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_LOW_BITS _u(0x00000400) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_LOW_MSB _u(10) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_LOW_LSB _u(10) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_HIGH_BITS _u(0x00000200) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_HIGH_MSB _u(9) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_HIGH_LSB _u(9) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_LOW_BITS _u(0x00000100) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_LOW_MSB _u(8) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_LOW_LSB _u(8) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_HIGH_BITS _u(0x00000080) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_HIGH_MSB _u(7) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_HIGH_LSB _u(7) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_LOW_BITS _u(0x00000040) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_LOW_MSB _u(6) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_LOW_LSB _u(6) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_HIGH_BITS _u(0x00000020) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_HIGH_MSB _u(5) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_HIGH_LSB _u(5) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_LOW_BITS _u(0x00000010) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_LOW_MSB _u(4) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_LOW_LSB _u(4) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_HIGH_BITS _u(0x00000008) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_HIGH_MSB _u(3) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_HIGH_LSB _u(3) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_LOW_BITS _u(0x00000004) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_LOW_MSB _u(2) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_LOW_LSB _u(2) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_HIGH_BITS _u(0x00000002) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_HIGH_MSB _u(1) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_HIGH_LSB _u(1) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_LOW_BITS _u(0x00000001) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_LOW_MSB _u(0) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_LOW_LSB _u(0) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_LOW_ACCESS "RW" -// ============================================================================= -// Register : IO_BANK0_DORMANT_WAKE_INTF1 -// Description : Interrupt Force for dormant_wake -#define IO_BANK0_DORMANT_WAKE_INTF1_OFFSET _u(0x00000174) -#define IO_BANK0_DORMANT_WAKE_INTF1_BITS _u(0xffffffff) -#define IO_BANK0_DORMANT_WAKE_INTF1_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_HIGH_BITS _u(0x80000000) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_HIGH_MSB _u(31) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_HIGH_LSB _u(31) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_LOW_BITS _u(0x40000000) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_LOW_MSB _u(30) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_LOW_LSB _u(30) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_HIGH_BITS _u(0x20000000) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_HIGH_MSB _u(29) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_HIGH_LSB _u(29) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_LOW_BITS _u(0x10000000) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_LOW_MSB _u(28) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_LOW_LSB _u(28) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_HIGH_BITS _u(0x08000000) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_HIGH_MSB _u(27) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_HIGH_LSB _u(27) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_LOW_BITS _u(0x04000000) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_LOW_MSB _u(26) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_LOW_LSB _u(26) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_HIGH_BITS _u(0x02000000) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_HIGH_MSB _u(25) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_HIGH_LSB _u(25) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_LOW_BITS _u(0x01000000) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_LOW_MSB _u(24) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_LOW_LSB _u(24) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_HIGH_BITS _u(0x00800000) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_HIGH_MSB _u(23) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_HIGH_LSB _u(23) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_LOW_BITS _u(0x00400000) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_LOW_MSB _u(22) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_LOW_LSB _u(22) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_HIGH_BITS _u(0x00200000) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_HIGH_MSB _u(21) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_HIGH_LSB _u(21) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_LOW_BITS _u(0x00100000) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_LOW_MSB _u(20) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_LOW_LSB _u(20) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_HIGH_BITS _u(0x00080000) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_HIGH_MSB _u(19) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_HIGH_LSB _u(19) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_LOW_BITS _u(0x00040000) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_LOW_MSB _u(18) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_LOW_LSB _u(18) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_HIGH_BITS _u(0x00020000) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_HIGH_MSB _u(17) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_HIGH_LSB _u(17) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_LOW_BITS _u(0x00010000) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_LOW_MSB _u(16) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_LOW_LSB _u(16) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_HIGH_BITS _u(0x00008000) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_HIGH_MSB _u(15) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_HIGH_LSB _u(15) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_LOW_BITS _u(0x00004000) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_LOW_MSB _u(14) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_LOW_LSB _u(14) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_HIGH_BITS _u(0x00002000) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_HIGH_MSB _u(13) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_HIGH_LSB _u(13) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_LOW_BITS _u(0x00001000) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_LOW_MSB _u(12) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_LOW_LSB _u(12) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_HIGH_BITS _u(0x00000800) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_HIGH_MSB _u(11) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_HIGH_LSB _u(11) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_LOW_BITS _u(0x00000400) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_LOW_MSB _u(10) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_LOW_LSB _u(10) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_HIGH_BITS _u(0x00000200) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_HIGH_MSB _u(9) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_HIGH_LSB _u(9) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_LOW_BITS _u(0x00000100) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_LOW_MSB _u(8) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_LOW_LSB _u(8) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_HIGH_BITS _u(0x00000080) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_HIGH_MSB _u(7) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_HIGH_LSB _u(7) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_LOW_BITS _u(0x00000040) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_LOW_MSB _u(6) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_LOW_LSB _u(6) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_HIGH_BITS _u(0x00000020) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_HIGH_MSB _u(5) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_HIGH_LSB _u(5) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_LOW_BITS _u(0x00000010) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_LOW_MSB _u(4) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_LOW_LSB _u(4) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_HIGH_BITS _u(0x00000008) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_HIGH_MSB _u(3) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_HIGH_LSB _u(3) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_LOW_BITS _u(0x00000004) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_LOW_MSB _u(2) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_LOW_LSB _u(2) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_HIGH_BITS _u(0x00000002) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_HIGH_MSB _u(1) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_HIGH_LSB _u(1) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_LOW_BITS _u(0x00000001) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_LOW_MSB _u(0) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_LOW_LSB _u(0) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_LOW_ACCESS "RW" -// ============================================================================= -// Register : IO_BANK0_DORMANT_WAKE_INTF2 -// Description : Interrupt Force for dormant_wake -#define IO_BANK0_DORMANT_WAKE_INTF2_OFFSET _u(0x00000178) -#define IO_BANK0_DORMANT_WAKE_INTF2_BITS _u(0xffffffff) -#define IO_BANK0_DORMANT_WAKE_INTF2_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_HIGH_BITS _u(0x80000000) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_HIGH_MSB _u(31) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_HIGH_LSB _u(31) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_LOW_BITS _u(0x40000000) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_LOW_MSB _u(30) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_LOW_LSB _u(30) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_HIGH_BITS _u(0x20000000) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_HIGH_MSB _u(29) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_HIGH_LSB _u(29) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_LOW_BITS _u(0x10000000) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_LOW_MSB _u(28) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_LOW_LSB _u(28) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_HIGH_BITS _u(0x08000000) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_HIGH_MSB _u(27) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_HIGH_LSB _u(27) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_LOW_BITS _u(0x04000000) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_LOW_MSB _u(26) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_LOW_LSB _u(26) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_HIGH_BITS _u(0x02000000) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_HIGH_MSB _u(25) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_HIGH_LSB _u(25) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_LOW_BITS _u(0x01000000) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_LOW_MSB _u(24) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_LOW_LSB _u(24) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_HIGH_BITS _u(0x00800000) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_HIGH_MSB _u(23) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_HIGH_LSB _u(23) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_LOW_BITS _u(0x00400000) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_LOW_MSB _u(22) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_LOW_LSB _u(22) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_HIGH_BITS _u(0x00200000) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_HIGH_MSB _u(21) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_HIGH_LSB _u(21) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_LOW_BITS _u(0x00100000) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_LOW_MSB _u(20) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_LOW_LSB _u(20) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_HIGH_BITS _u(0x00080000) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_HIGH_MSB _u(19) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_HIGH_LSB _u(19) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_LOW_BITS _u(0x00040000) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_LOW_MSB _u(18) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_LOW_LSB _u(18) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_HIGH_BITS _u(0x00020000) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_HIGH_MSB _u(17) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_HIGH_LSB _u(17) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_LOW_BITS _u(0x00010000) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_LOW_MSB _u(16) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_LOW_LSB _u(16) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_HIGH_BITS _u(0x00008000) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_HIGH_MSB _u(15) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_HIGH_LSB _u(15) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_LOW_BITS _u(0x00004000) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_LOW_MSB _u(14) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_LOW_LSB _u(14) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_HIGH_BITS _u(0x00002000) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_HIGH_MSB _u(13) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_HIGH_LSB _u(13) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_LOW_BITS _u(0x00001000) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_LOW_MSB _u(12) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_LOW_LSB _u(12) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_HIGH_BITS _u(0x00000800) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_HIGH_MSB _u(11) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_HIGH_LSB _u(11) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_LOW_BITS _u(0x00000400) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_LOW_MSB _u(10) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_LOW_LSB _u(10) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_HIGH_BITS _u(0x00000200) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_HIGH_MSB _u(9) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_HIGH_LSB _u(9) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_LOW_BITS _u(0x00000100) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_LOW_MSB _u(8) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_LOW_LSB _u(8) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_HIGH_BITS _u(0x00000080) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_HIGH_MSB _u(7) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_HIGH_LSB _u(7) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_LOW_BITS _u(0x00000040) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_LOW_MSB _u(6) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_LOW_LSB _u(6) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_HIGH_BITS _u(0x00000020) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_HIGH_MSB _u(5) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_HIGH_LSB _u(5) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_LOW_BITS _u(0x00000010) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_LOW_MSB _u(4) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_LOW_LSB _u(4) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_HIGH_BITS _u(0x00000008) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_HIGH_MSB _u(3) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_HIGH_LSB _u(3) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_LOW_BITS _u(0x00000004) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_LOW_MSB _u(2) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_LOW_LSB _u(2) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_HIGH_BITS _u(0x00000002) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_HIGH_MSB _u(1) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_HIGH_LSB _u(1) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_LOW_BITS _u(0x00000001) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_LOW_MSB _u(0) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_LOW_LSB _u(0) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_LOW_ACCESS "RW" -// ============================================================================= -// Register : IO_BANK0_DORMANT_WAKE_INTF3 -// Description : Interrupt Force for dormant_wake -#define IO_BANK0_DORMANT_WAKE_INTF3_OFFSET _u(0x0000017c) -#define IO_BANK0_DORMANT_WAKE_INTF3_BITS _u(0x00ffffff) -#define IO_BANK0_DORMANT_WAKE_INTF3_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_HIGH_BITS _u(0x00800000) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_HIGH_MSB _u(23) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_HIGH_LSB _u(23) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_LOW_BITS _u(0x00400000) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_LOW_MSB _u(22) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_LOW_LSB _u(22) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_HIGH_BITS _u(0x00200000) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_HIGH_MSB _u(21) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_HIGH_LSB _u(21) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_LOW_BITS _u(0x00100000) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_LOW_MSB _u(20) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_LOW_LSB _u(20) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_HIGH_BITS _u(0x00080000) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_HIGH_MSB _u(19) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_HIGH_LSB _u(19) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_LOW_BITS _u(0x00040000) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_LOW_MSB _u(18) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_LOW_LSB _u(18) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_HIGH_BITS _u(0x00020000) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_HIGH_MSB _u(17) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_HIGH_LSB _u(17) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_LOW_BITS _u(0x00010000) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_LOW_MSB _u(16) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_LOW_LSB _u(16) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_HIGH_BITS _u(0x00008000) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_HIGH_MSB _u(15) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_HIGH_LSB _u(15) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_LOW_BITS _u(0x00004000) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_LOW_MSB _u(14) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_LOW_LSB _u(14) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_HIGH_BITS _u(0x00002000) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_HIGH_MSB _u(13) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_HIGH_LSB _u(13) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_LOW_BITS _u(0x00001000) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_LOW_MSB _u(12) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_LOW_LSB _u(12) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_HIGH_BITS _u(0x00000800) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_HIGH_MSB _u(11) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_HIGH_LSB _u(11) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_LOW_BITS _u(0x00000400) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_LOW_MSB _u(10) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_LOW_LSB _u(10) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_HIGH_BITS _u(0x00000200) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_HIGH_MSB _u(9) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_HIGH_LSB _u(9) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_LOW_BITS _u(0x00000100) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_LOW_MSB _u(8) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_LOW_LSB _u(8) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_HIGH_BITS _u(0x00000080) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_HIGH_MSB _u(7) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_HIGH_LSB _u(7) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_LOW_BITS _u(0x00000040) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_LOW_MSB _u(6) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_LOW_LSB _u(6) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_HIGH_BITS _u(0x00000020) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_HIGH_MSB _u(5) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_HIGH_LSB _u(5) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_LOW_BITS _u(0x00000010) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_LOW_MSB _u(4) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_LOW_LSB _u(4) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_HIGH_BITS _u(0x00000008) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_HIGH_MSB _u(3) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_HIGH_LSB _u(3) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_LOW_BITS _u(0x00000004) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_LOW_MSB _u(2) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_LOW_LSB _u(2) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_HIGH_BITS _u(0x00000002) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_HIGH_MSB _u(1) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_HIGH_LSB _u(1) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_LOW_BITS _u(0x00000001) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_LOW_MSB _u(0) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_LOW_LSB _u(0) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_LOW_ACCESS "RW" -// ============================================================================= -// Register : IO_BANK0_DORMANT_WAKE_INTS0 -// Description : Interrupt status after masking & forcing for dormant_wake -#define IO_BANK0_DORMANT_WAKE_INTS0_OFFSET _u(0x00000180) -#define IO_BANK0_DORMANT_WAKE_INTS0_BITS _u(0xffffffff) -#define IO_BANK0_DORMANT_WAKE_INTS0_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_HIGH_BITS _u(0x80000000) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_HIGH_MSB _u(31) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_HIGH_LSB _u(31) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_LOW_BITS _u(0x40000000) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_LOW_MSB _u(30) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_LOW_LSB _u(30) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_HIGH_BITS _u(0x20000000) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_HIGH_MSB _u(29) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_HIGH_LSB _u(29) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_LOW_BITS _u(0x10000000) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_LOW_MSB _u(28) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_LOW_LSB _u(28) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_HIGH_BITS _u(0x08000000) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_HIGH_MSB _u(27) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_HIGH_LSB _u(27) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_LOW_BITS _u(0x04000000) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_LOW_MSB _u(26) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_LOW_LSB _u(26) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_HIGH_BITS _u(0x02000000) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_HIGH_MSB _u(25) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_HIGH_LSB _u(25) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_LOW_BITS _u(0x01000000) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_LOW_MSB _u(24) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_LOW_LSB _u(24) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_HIGH_BITS _u(0x00800000) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_HIGH_MSB _u(23) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_HIGH_LSB _u(23) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_LOW_BITS _u(0x00400000) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_LOW_MSB _u(22) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_LOW_LSB _u(22) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_HIGH_BITS _u(0x00200000) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_HIGH_MSB _u(21) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_HIGH_LSB _u(21) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_LOW_BITS _u(0x00100000) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_LOW_MSB _u(20) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_LOW_LSB _u(20) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_HIGH_BITS _u(0x00080000) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_HIGH_MSB _u(19) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_HIGH_LSB _u(19) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_LOW_BITS _u(0x00040000) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_LOW_MSB _u(18) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_LOW_LSB _u(18) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_HIGH_BITS _u(0x00020000) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_HIGH_MSB _u(17) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_HIGH_LSB _u(17) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_LOW_BITS _u(0x00010000) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_LOW_MSB _u(16) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_LOW_LSB _u(16) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_HIGH_BITS _u(0x00008000) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_HIGH_MSB _u(15) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_HIGH_LSB _u(15) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_LOW_BITS _u(0x00004000) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_LOW_MSB _u(14) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_LOW_LSB _u(14) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_HIGH_BITS _u(0x00002000) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_HIGH_MSB _u(13) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_HIGH_LSB _u(13) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_LOW_BITS _u(0x00001000) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_LOW_MSB _u(12) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_LOW_LSB _u(12) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_HIGH_BITS _u(0x00000800) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_HIGH_MSB _u(11) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_HIGH_LSB _u(11) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_LOW_BITS _u(0x00000400) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_LOW_MSB _u(10) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_LOW_LSB _u(10) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_HIGH_BITS _u(0x00000200) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_HIGH_MSB _u(9) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_HIGH_LSB _u(9) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_LOW_BITS _u(0x00000100) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_LOW_MSB _u(8) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_LOW_LSB _u(8) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_HIGH_BITS _u(0x00000080) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_HIGH_MSB _u(7) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_HIGH_LSB _u(7) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_LOW_BITS _u(0x00000040) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_LOW_MSB _u(6) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_LOW_LSB _u(6) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_HIGH_BITS _u(0x00000020) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_HIGH_MSB _u(5) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_HIGH_LSB _u(5) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_LOW_BITS _u(0x00000010) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_LOW_MSB _u(4) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_LOW_LSB _u(4) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_HIGH_BITS _u(0x00000008) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_HIGH_MSB _u(3) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_HIGH_LSB _u(3) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_LOW_BITS _u(0x00000004) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_LOW_MSB _u(2) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_LOW_LSB _u(2) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_HIGH_BITS _u(0x00000002) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_HIGH_MSB _u(1) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_HIGH_LSB _u(1) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_LOW_BITS _u(0x00000001) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_LOW_MSB _u(0) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_LOW_LSB _u(0) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_LOW_ACCESS "RO" -// ============================================================================= -// Register : IO_BANK0_DORMANT_WAKE_INTS1 -// Description : Interrupt status after masking & forcing for dormant_wake -#define IO_BANK0_DORMANT_WAKE_INTS1_OFFSET _u(0x00000184) -#define IO_BANK0_DORMANT_WAKE_INTS1_BITS _u(0xffffffff) -#define IO_BANK0_DORMANT_WAKE_INTS1_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_HIGH_BITS _u(0x80000000) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_HIGH_MSB _u(31) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_HIGH_LSB _u(31) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_LOW_BITS _u(0x40000000) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_LOW_MSB _u(30) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_LOW_LSB _u(30) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_HIGH_BITS _u(0x20000000) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_HIGH_MSB _u(29) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_HIGH_LSB _u(29) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_LOW_BITS _u(0x10000000) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_LOW_MSB _u(28) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_LOW_LSB _u(28) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_HIGH_BITS _u(0x08000000) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_HIGH_MSB _u(27) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_HIGH_LSB _u(27) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_LOW_BITS _u(0x04000000) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_LOW_MSB _u(26) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_LOW_LSB _u(26) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_HIGH_BITS _u(0x02000000) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_HIGH_MSB _u(25) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_HIGH_LSB _u(25) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_LOW_BITS _u(0x01000000) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_LOW_MSB _u(24) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_LOW_LSB _u(24) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_HIGH_BITS _u(0x00800000) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_HIGH_MSB _u(23) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_HIGH_LSB _u(23) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_LOW_BITS _u(0x00400000) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_LOW_MSB _u(22) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_LOW_LSB _u(22) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_HIGH_BITS _u(0x00200000) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_HIGH_MSB _u(21) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_HIGH_LSB _u(21) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_LOW_BITS _u(0x00100000) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_LOW_MSB _u(20) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_LOW_LSB _u(20) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_HIGH_BITS _u(0x00080000) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_HIGH_MSB _u(19) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_HIGH_LSB _u(19) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_LOW_BITS _u(0x00040000) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_LOW_MSB _u(18) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_LOW_LSB _u(18) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_HIGH_BITS _u(0x00020000) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_HIGH_MSB _u(17) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_HIGH_LSB _u(17) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_LOW_BITS _u(0x00010000) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_LOW_MSB _u(16) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_LOW_LSB _u(16) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_HIGH_BITS _u(0x00008000) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_HIGH_MSB _u(15) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_HIGH_LSB _u(15) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_LOW_BITS _u(0x00004000) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_LOW_MSB _u(14) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_LOW_LSB _u(14) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_HIGH_BITS _u(0x00002000) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_HIGH_MSB _u(13) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_HIGH_LSB _u(13) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_LOW_BITS _u(0x00001000) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_LOW_MSB _u(12) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_LOW_LSB _u(12) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_HIGH_BITS _u(0x00000800) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_HIGH_MSB _u(11) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_HIGH_LSB _u(11) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_LOW_BITS _u(0x00000400) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_LOW_MSB _u(10) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_LOW_LSB _u(10) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_HIGH_BITS _u(0x00000200) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_HIGH_MSB _u(9) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_HIGH_LSB _u(9) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_LOW_BITS _u(0x00000100) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_LOW_MSB _u(8) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_LOW_LSB _u(8) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_HIGH_BITS _u(0x00000080) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_HIGH_MSB _u(7) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_HIGH_LSB _u(7) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_LOW_BITS _u(0x00000040) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_LOW_MSB _u(6) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_LOW_LSB _u(6) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_HIGH_BITS _u(0x00000020) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_HIGH_MSB _u(5) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_HIGH_LSB _u(5) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_LOW_BITS _u(0x00000010) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_LOW_MSB _u(4) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_LOW_LSB _u(4) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_HIGH_BITS _u(0x00000008) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_HIGH_MSB _u(3) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_HIGH_LSB _u(3) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_LOW_BITS _u(0x00000004) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_LOW_MSB _u(2) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_LOW_LSB _u(2) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_HIGH_BITS _u(0x00000002) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_HIGH_MSB _u(1) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_HIGH_LSB _u(1) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_LOW_BITS _u(0x00000001) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_LOW_MSB _u(0) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_LOW_LSB _u(0) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_LOW_ACCESS "RO" -// ============================================================================= -// Register : IO_BANK0_DORMANT_WAKE_INTS2 -// Description : Interrupt status after masking & forcing for dormant_wake -#define IO_BANK0_DORMANT_WAKE_INTS2_OFFSET _u(0x00000188) -#define IO_BANK0_DORMANT_WAKE_INTS2_BITS _u(0xffffffff) -#define IO_BANK0_DORMANT_WAKE_INTS2_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_HIGH_BITS _u(0x80000000) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_HIGH_MSB _u(31) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_HIGH_LSB _u(31) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_LOW_BITS _u(0x40000000) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_LOW_MSB _u(30) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_LOW_LSB _u(30) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_HIGH_BITS _u(0x20000000) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_HIGH_MSB _u(29) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_HIGH_LSB _u(29) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_LOW_BITS _u(0x10000000) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_LOW_MSB _u(28) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_LOW_LSB _u(28) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_HIGH_BITS _u(0x08000000) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_HIGH_MSB _u(27) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_HIGH_LSB _u(27) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_LOW_BITS _u(0x04000000) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_LOW_MSB _u(26) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_LOW_LSB _u(26) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_HIGH_BITS _u(0x02000000) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_HIGH_MSB _u(25) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_HIGH_LSB _u(25) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_LOW_BITS _u(0x01000000) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_LOW_MSB _u(24) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_LOW_LSB _u(24) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_HIGH_BITS _u(0x00800000) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_HIGH_MSB _u(23) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_HIGH_LSB _u(23) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_LOW_BITS _u(0x00400000) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_LOW_MSB _u(22) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_LOW_LSB _u(22) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_HIGH_BITS _u(0x00200000) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_HIGH_MSB _u(21) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_HIGH_LSB _u(21) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_LOW_BITS _u(0x00100000) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_LOW_MSB _u(20) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_LOW_LSB _u(20) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_HIGH_BITS _u(0x00080000) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_HIGH_MSB _u(19) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_HIGH_LSB _u(19) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_LOW_BITS _u(0x00040000) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_LOW_MSB _u(18) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_LOW_LSB _u(18) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_HIGH_BITS _u(0x00020000) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_HIGH_MSB _u(17) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_HIGH_LSB _u(17) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_LOW_BITS _u(0x00010000) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_LOW_MSB _u(16) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_LOW_LSB _u(16) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_HIGH_BITS _u(0x00008000) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_HIGH_MSB _u(15) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_HIGH_LSB _u(15) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_LOW_BITS _u(0x00004000) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_LOW_MSB _u(14) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_LOW_LSB _u(14) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_HIGH_BITS _u(0x00002000) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_HIGH_MSB _u(13) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_HIGH_LSB _u(13) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_LOW_BITS _u(0x00001000) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_LOW_MSB _u(12) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_LOW_LSB _u(12) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_HIGH_BITS _u(0x00000800) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_HIGH_MSB _u(11) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_HIGH_LSB _u(11) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_LOW_BITS _u(0x00000400) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_LOW_MSB _u(10) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_LOW_LSB _u(10) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_HIGH_BITS _u(0x00000200) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_HIGH_MSB _u(9) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_HIGH_LSB _u(9) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_LOW_BITS _u(0x00000100) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_LOW_MSB _u(8) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_LOW_LSB _u(8) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_HIGH_BITS _u(0x00000080) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_HIGH_MSB _u(7) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_HIGH_LSB _u(7) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_LOW_BITS _u(0x00000040) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_LOW_MSB _u(6) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_LOW_LSB _u(6) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_HIGH_BITS _u(0x00000020) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_HIGH_MSB _u(5) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_HIGH_LSB _u(5) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_LOW_BITS _u(0x00000010) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_LOW_MSB _u(4) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_LOW_LSB _u(4) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_HIGH_BITS _u(0x00000008) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_HIGH_MSB _u(3) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_HIGH_LSB _u(3) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_LOW_BITS _u(0x00000004) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_LOW_MSB _u(2) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_LOW_LSB _u(2) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_HIGH_BITS _u(0x00000002) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_HIGH_MSB _u(1) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_HIGH_LSB _u(1) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_LOW_BITS _u(0x00000001) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_LOW_MSB _u(0) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_LOW_LSB _u(0) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_LOW_ACCESS "RO" -// ============================================================================= -// Register : IO_BANK0_DORMANT_WAKE_INTS3 -// Description : Interrupt status after masking & forcing for dormant_wake -#define IO_BANK0_DORMANT_WAKE_INTS3_OFFSET _u(0x0000018c) -#define IO_BANK0_DORMANT_WAKE_INTS3_BITS _u(0x00ffffff) -#define IO_BANK0_DORMANT_WAKE_INTS3_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_HIGH_BITS _u(0x00800000) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_HIGH_MSB _u(23) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_HIGH_LSB _u(23) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_LOW_BITS _u(0x00400000) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_LOW_MSB _u(22) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_LOW_LSB _u(22) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_HIGH_BITS _u(0x00200000) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_HIGH_MSB _u(21) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_HIGH_LSB _u(21) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_LOW_BITS _u(0x00100000) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_LOW_MSB _u(20) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_LOW_LSB _u(20) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_HIGH_BITS _u(0x00080000) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_HIGH_MSB _u(19) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_HIGH_LSB _u(19) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_LOW_BITS _u(0x00040000) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_LOW_MSB _u(18) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_LOW_LSB _u(18) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_HIGH_BITS _u(0x00020000) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_HIGH_MSB _u(17) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_HIGH_LSB _u(17) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_LOW_BITS _u(0x00010000) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_LOW_MSB _u(16) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_LOW_LSB _u(16) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_HIGH_BITS _u(0x00008000) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_HIGH_MSB _u(15) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_HIGH_LSB _u(15) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_LOW_BITS _u(0x00004000) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_LOW_MSB _u(14) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_LOW_LSB _u(14) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_HIGH_BITS _u(0x00002000) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_HIGH_MSB _u(13) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_HIGH_LSB _u(13) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_LOW_BITS _u(0x00001000) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_LOW_MSB _u(12) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_LOW_LSB _u(12) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_HIGH_BITS _u(0x00000800) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_HIGH_MSB _u(11) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_HIGH_LSB _u(11) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_LOW_BITS _u(0x00000400) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_LOW_MSB _u(10) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_LOW_LSB _u(10) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_HIGH_BITS _u(0x00000200) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_HIGH_MSB _u(9) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_HIGH_LSB _u(9) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_LOW_BITS _u(0x00000100) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_LOW_MSB _u(8) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_LOW_LSB _u(8) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_HIGH_BITS _u(0x00000080) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_HIGH_MSB _u(7) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_HIGH_LSB _u(7) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_LOW_BITS _u(0x00000040) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_LOW_MSB _u(6) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_LOW_LSB _u(6) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_HIGH_BITS _u(0x00000020) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_HIGH_MSB _u(5) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_HIGH_LSB _u(5) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_LOW_BITS _u(0x00000010) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_LOW_MSB _u(4) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_LOW_LSB _u(4) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_HIGH_BITS _u(0x00000008) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_HIGH_MSB _u(3) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_HIGH_LSB _u(3) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_LOW_BITS _u(0x00000004) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_LOW_MSB _u(2) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_LOW_LSB _u(2) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_HIGH_BITS _u(0x00000002) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_HIGH_MSB _u(1) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_HIGH_LSB _u(1) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_LOW_BITS _u(0x00000001) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_LOW_MSB _u(0) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_LOW_LSB _u(0) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_LOW_ACCESS "RO" -// ============================================================================= -#endif // _HARDWARE_REGS_IO_BANK0_H - diff --git a/lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/io_qspi.h b/lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/io_qspi.h deleted file mode 100644 index 5ed0ddbad9..0000000000 --- a/lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/io_qspi.h +++ /dev/null @@ -1,2675 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -// ============================================================================= -// Register block : IO_QSPI -// Version : 1 -// Bus type : apb -// ============================================================================= -#ifndef _HARDWARE_REGS_IO_QSPI_H -#define _HARDWARE_REGS_IO_QSPI_H -// ============================================================================= -// Register : IO_QSPI_GPIO_QSPI_SCLK_STATUS -// Description : GPIO status -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OFFSET _u(0x00000000) -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_BITS _u(0x050a3300) -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQTOPROC -// Description : interrupt to processors, after override is applied -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQTOPROC_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQTOPROC_BITS _u(0x04000000) -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQTOPROC_MSB _u(26) -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQTOPROC_LSB _u(26) -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQTOPROC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQFROMPAD -// Description : interrupt from pad before override is applied -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQFROMPAD_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQFROMPAD_BITS _u(0x01000000) -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQFROMPAD_MSB _u(24) -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQFROMPAD_LSB _u(24) -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQFROMPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SCLK_STATUS_INTOPERI -// Description : input signal to peripheral, after override is applied -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INTOPERI_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INTOPERI_BITS _u(0x00080000) -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INTOPERI_MSB _u(19) -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INTOPERI_LSB _u(19) -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INTOPERI_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SCLK_STATUS_INFROMPAD -// Description : input signal from pad, before override is applied -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INFROMPAD_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INFROMPAD_BITS _u(0x00020000) -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INFROMPAD_MSB _u(17) -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INFROMPAD_LSB _u(17) -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INFROMPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SCLK_STATUS_OETOPAD -// Description : output enable to pad after register override is applied -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OETOPAD_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OETOPAD_BITS _u(0x00002000) -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OETOPAD_MSB _u(13) -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OETOPAD_LSB _u(13) -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OETOPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SCLK_STATUS_OEFROMPERI -// Description : output enable from selected peripheral, before register -// override is applied -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OEFROMPERI_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OEFROMPERI_BITS _u(0x00001000) -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OEFROMPERI_MSB _u(12) -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OEFROMPERI_LSB _u(12) -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OEFROMPERI_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTTOPAD -// Description : output signal to pad after register override is applied -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTTOPAD_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTTOPAD_BITS _u(0x00000200) -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTTOPAD_MSB _u(9) -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTTOPAD_LSB _u(9) -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTTOPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTFROMPERI -// Description : output signal from selected peripheral, before register -// override is applied -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTFROMPERI_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTFROMPERI_BITS _u(0x00000100) -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTFROMPERI_MSB _u(8) -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTFROMPERI_LSB _u(8) -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTFROMPERI_ACCESS "RO" -// ============================================================================= -// Register : IO_QSPI_GPIO_QSPI_SCLK_CTRL -// Description : GPIO control including function select and overrides. -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OFFSET _u(0x00000004) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_BITS _u(0x3003331f) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_RESET _u(0x0000001f) -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER -// 0x0 -> don't invert the interrupt -// 0x1 -> invert the interrupt -// 0x2 -> drive interrupt low -// 0x3 -> drive interrupt high -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_MSB _u(29) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_LSB _u(28) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER -// 0x0 -> don't invert the peri input -// 0x1 -> invert the peri input -// 0x2 -> drive peri input low -// 0x3 -> drive peri input high -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_BITS _u(0x00030000) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_MSB _u(17) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_LSB _u(16) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_VALUE_NORMAL _u(0x0) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER -// 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel -// 0x2 -> disable output -// 0x3 -> enable output -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_BITS _u(0x00003000) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_MSB _u(13) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_LSB _u(12) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_VALUE_INVERT _u(0x1) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_VALUE_ENABLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER -// 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel -// 0x2 -> drive output low -// 0x3 -> drive output high -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_BITS _u(0x00000300) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_MSB _u(9) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_LSB _u(8) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL -// Description : 0-31 -> selects pin function according to the gpio table -// 31 == NULL -// 0x00 -> xip_sclk -// 0x05 -> sio_30 -// 0x1f -> null -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_MSB _u(4) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_LSB _u(0) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_VALUE_XIP_SCLK _u(0x00) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_VALUE_SIO_30 _u(0x05) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) -// ============================================================================= -// Register : IO_QSPI_GPIO_QSPI_SS_STATUS -// Description : GPIO status -#define IO_QSPI_GPIO_QSPI_SS_STATUS_OFFSET _u(0x00000008) -#define IO_QSPI_GPIO_QSPI_SS_STATUS_BITS _u(0x050a3300) -#define IO_QSPI_GPIO_QSPI_SS_STATUS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SS_STATUS_IRQTOPROC -// Description : interrupt to processors, after override is applied -#define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQTOPROC_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQTOPROC_BITS _u(0x04000000) -#define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQTOPROC_MSB _u(26) -#define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQTOPROC_LSB _u(26) -#define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQTOPROC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SS_STATUS_IRQFROMPAD -// Description : interrupt from pad before override is applied -#define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQFROMPAD_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQFROMPAD_BITS _u(0x01000000) -#define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQFROMPAD_MSB _u(24) -#define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQFROMPAD_LSB _u(24) -#define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQFROMPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SS_STATUS_INTOPERI -// Description : input signal to peripheral, after override is applied -#define IO_QSPI_GPIO_QSPI_SS_STATUS_INTOPERI_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SS_STATUS_INTOPERI_BITS _u(0x00080000) -#define IO_QSPI_GPIO_QSPI_SS_STATUS_INTOPERI_MSB _u(19) -#define IO_QSPI_GPIO_QSPI_SS_STATUS_INTOPERI_LSB _u(19) -#define IO_QSPI_GPIO_QSPI_SS_STATUS_INTOPERI_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SS_STATUS_INFROMPAD -// Description : input signal from pad, before override is applied -#define IO_QSPI_GPIO_QSPI_SS_STATUS_INFROMPAD_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SS_STATUS_INFROMPAD_BITS _u(0x00020000) -#define IO_QSPI_GPIO_QSPI_SS_STATUS_INFROMPAD_MSB _u(17) -#define IO_QSPI_GPIO_QSPI_SS_STATUS_INFROMPAD_LSB _u(17) -#define IO_QSPI_GPIO_QSPI_SS_STATUS_INFROMPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SS_STATUS_OETOPAD -// Description : output enable to pad after register override is applied -#define IO_QSPI_GPIO_QSPI_SS_STATUS_OETOPAD_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SS_STATUS_OETOPAD_BITS _u(0x00002000) -#define IO_QSPI_GPIO_QSPI_SS_STATUS_OETOPAD_MSB _u(13) -#define IO_QSPI_GPIO_QSPI_SS_STATUS_OETOPAD_LSB _u(13) -#define IO_QSPI_GPIO_QSPI_SS_STATUS_OETOPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SS_STATUS_OEFROMPERI -// Description : output enable from selected peripheral, before register -// override is applied -#define IO_QSPI_GPIO_QSPI_SS_STATUS_OEFROMPERI_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SS_STATUS_OEFROMPERI_BITS _u(0x00001000) -#define IO_QSPI_GPIO_QSPI_SS_STATUS_OEFROMPERI_MSB _u(12) -#define IO_QSPI_GPIO_QSPI_SS_STATUS_OEFROMPERI_LSB _u(12) -#define IO_QSPI_GPIO_QSPI_SS_STATUS_OEFROMPERI_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SS_STATUS_OUTTOPAD -// Description : output signal to pad after register override is applied -#define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTTOPAD_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTTOPAD_BITS _u(0x00000200) -#define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTTOPAD_MSB _u(9) -#define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTTOPAD_LSB _u(9) -#define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTTOPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SS_STATUS_OUTFROMPERI -// Description : output signal from selected peripheral, before register -// override is applied -#define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTFROMPERI_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTFROMPERI_BITS _u(0x00000100) -#define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTFROMPERI_MSB _u(8) -#define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTFROMPERI_LSB _u(8) -#define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTFROMPERI_ACCESS "RO" -// ============================================================================= -// Register : IO_QSPI_GPIO_QSPI_SS_CTRL -// Description : GPIO control including function select and overrides. -#define IO_QSPI_GPIO_QSPI_SS_CTRL_OFFSET _u(0x0000000c) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_BITS _u(0x3003331f) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_RESET _u(0x0000001f) -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER -// 0x0 -> don't invert the interrupt -// 0x1 -> invert the interrupt -// 0x2 -> drive interrupt low -// 0x3 -> drive interrupt high -#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_MSB _u(29) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_LSB _u(28) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER -// 0x0 -> don't invert the peri input -// 0x1 -> invert the peri input -// 0x2 -> drive peri input low -// 0x3 -> drive peri input high -#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_BITS _u(0x00030000) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_MSB _u(17) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_LSB _u(16) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_VALUE_NORMAL _u(0x0) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER -// 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel -// 0x2 -> disable output -// 0x3 -> enable output -#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_BITS _u(0x00003000) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_MSB _u(13) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_LSB _u(12) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_VALUE_INVERT _u(0x1) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_VALUE_ENABLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER -// 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel -// 0x2 -> drive output low -// 0x3 -> drive output high -#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_BITS _u(0x00000300) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_MSB _u(9) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_LSB _u(8) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL -// Description : 0-31 -> selects pin function according to the gpio table -// 31 == NULL -// 0x00 -> xip_ss_n -// 0x05 -> sio_31 -// 0x1f -> null -#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_MSB _u(4) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_LSB _u(0) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_VALUE_XIP_SS_N _u(0x00) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_VALUE_SIO_31 _u(0x05) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) -// ============================================================================= -// Register : IO_QSPI_GPIO_QSPI_SD0_STATUS -// Description : GPIO status -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OFFSET _u(0x00000010) -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_BITS _u(0x050a3300) -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQTOPROC -// Description : interrupt to processors, after override is applied -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQTOPROC_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQTOPROC_BITS _u(0x04000000) -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQTOPROC_MSB _u(26) -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQTOPROC_LSB _u(26) -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQTOPROC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQFROMPAD -// Description : interrupt from pad before override is applied -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQFROMPAD_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQFROMPAD_BITS _u(0x01000000) -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQFROMPAD_MSB _u(24) -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQFROMPAD_LSB _u(24) -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQFROMPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SD0_STATUS_INTOPERI -// Description : input signal to peripheral, after override is applied -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_INTOPERI_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_INTOPERI_BITS _u(0x00080000) -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_INTOPERI_MSB _u(19) -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_INTOPERI_LSB _u(19) -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_INTOPERI_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SD0_STATUS_INFROMPAD -// Description : input signal from pad, before override is applied -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_INFROMPAD_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_INFROMPAD_BITS _u(0x00020000) -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_INFROMPAD_MSB _u(17) -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_INFROMPAD_LSB _u(17) -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_INFROMPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SD0_STATUS_OETOPAD -// Description : output enable to pad after register override is applied -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OETOPAD_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OETOPAD_BITS _u(0x00002000) -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OETOPAD_MSB _u(13) -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OETOPAD_LSB _u(13) -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OETOPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SD0_STATUS_OEFROMPERI -// Description : output enable from selected peripheral, before register -// override is applied -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OEFROMPERI_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OEFROMPERI_BITS _u(0x00001000) -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OEFROMPERI_MSB _u(12) -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OEFROMPERI_LSB _u(12) -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OEFROMPERI_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTTOPAD -// Description : output signal to pad after register override is applied -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTTOPAD_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTTOPAD_BITS _u(0x00000200) -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTTOPAD_MSB _u(9) -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTTOPAD_LSB _u(9) -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTTOPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTFROMPERI -// Description : output signal from selected peripheral, before register -// override is applied -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTFROMPERI_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTFROMPERI_BITS _u(0x00000100) -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTFROMPERI_MSB _u(8) -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTFROMPERI_LSB _u(8) -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTFROMPERI_ACCESS "RO" -// ============================================================================= -// Register : IO_QSPI_GPIO_QSPI_SD0_CTRL -// Description : GPIO control including function select and overrides. -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OFFSET _u(0x00000014) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_BITS _u(0x3003331f) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_RESET _u(0x0000001f) -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER -// 0x0 -> don't invert the interrupt -// 0x1 -> invert the interrupt -// 0x2 -> drive interrupt low -// 0x3 -> drive interrupt high -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_MSB _u(29) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_LSB _u(28) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER -// 0x0 -> don't invert the peri input -// 0x1 -> invert the peri input -// 0x2 -> drive peri input low -// 0x3 -> drive peri input high -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_BITS _u(0x00030000) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_MSB _u(17) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_LSB _u(16) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_VALUE_NORMAL _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER -// 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel -// 0x2 -> disable output -// 0x3 -> enable output -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_BITS _u(0x00003000) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_MSB _u(13) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_LSB _u(12) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_VALUE_INVERT _u(0x1) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_VALUE_ENABLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER -// 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel -// 0x2 -> drive output low -// 0x3 -> drive output high -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_BITS _u(0x00000300) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_MSB _u(9) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_LSB _u(8) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL -// Description : 0-31 -> selects pin function according to the gpio table -// 31 == NULL -// 0x00 -> xip_sd0 -// 0x05 -> sio_32 -// 0x1f -> null -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_MSB _u(4) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_LSB _u(0) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_VALUE_XIP_SD0 _u(0x00) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_VALUE_SIO_32 _u(0x05) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) -// ============================================================================= -// Register : IO_QSPI_GPIO_QSPI_SD1_STATUS -// Description : GPIO status -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OFFSET _u(0x00000018) -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_BITS _u(0x050a3300) -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQTOPROC -// Description : interrupt to processors, after override is applied -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQTOPROC_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQTOPROC_BITS _u(0x04000000) -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQTOPROC_MSB _u(26) -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQTOPROC_LSB _u(26) -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQTOPROC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQFROMPAD -// Description : interrupt from pad before override is applied -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQFROMPAD_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQFROMPAD_BITS _u(0x01000000) -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQFROMPAD_MSB _u(24) -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQFROMPAD_LSB _u(24) -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQFROMPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SD1_STATUS_INTOPERI -// Description : input signal to peripheral, after override is applied -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_INTOPERI_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_INTOPERI_BITS _u(0x00080000) -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_INTOPERI_MSB _u(19) -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_INTOPERI_LSB _u(19) -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_INTOPERI_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SD1_STATUS_INFROMPAD -// Description : input signal from pad, before override is applied -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_INFROMPAD_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_INFROMPAD_BITS _u(0x00020000) -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_INFROMPAD_MSB _u(17) -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_INFROMPAD_LSB _u(17) -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_INFROMPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SD1_STATUS_OETOPAD -// Description : output enable to pad after register override is applied -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OETOPAD_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OETOPAD_BITS _u(0x00002000) -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OETOPAD_MSB _u(13) -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OETOPAD_LSB _u(13) -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OETOPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SD1_STATUS_OEFROMPERI -// Description : output enable from selected peripheral, before register -// override is applied -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OEFROMPERI_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OEFROMPERI_BITS _u(0x00001000) -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OEFROMPERI_MSB _u(12) -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OEFROMPERI_LSB _u(12) -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OEFROMPERI_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTTOPAD -// Description : output signal to pad after register override is applied -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTTOPAD_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTTOPAD_BITS _u(0x00000200) -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTTOPAD_MSB _u(9) -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTTOPAD_LSB _u(9) -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTTOPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTFROMPERI -// Description : output signal from selected peripheral, before register -// override is applied -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTFROMPERI_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTFROMPERI_BITS _u(0x00000100) -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTFROMPERI_MSB _u(8) -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTFROMPERI_LSB _u(8) -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTFROMPERI_ACCESS "RO" -// ============================================================================= -// Register : IO_QSPI_GPIO_QSPI_SD1_CTRL -// Description : GPIO control including function select and overrides. -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OFFSET _u(0x0000001c) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_BITS _u(0x3003331f) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_RESET _u(0x0000001f) -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER -// 0x0 -> don't invert the interrupt -// 0x1 -> invert the interrupt -// 0x2 -> drive interrupt low -// 0x3 -> drive interrupt high -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_MSB _u(29) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_LSB _u(28) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER -// 0x0 -> don't invert the peri input -// 0x1 -> invert the peri input -// 0x2 -> drive peri input low -// 0x3 -> drive peri input high -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_BITS _u(0x00030000) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_MSB _u(17) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_LSB _u(16) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_VALUE_NORMAL _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER -// 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel -// 0x2 -> disable output -// 0x3 -> enable output -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_BITS _u(0x00003000) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_MSB _u(13) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_LSB _u(12) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_VALUE_INVERT _u(0x1) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_VALUE_ENABLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER -// 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel -// 0x2 -> drive output low -// 0x3 -> drive output high -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_BITS _u(0x00000300) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_MSB _u(9) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_LSB _u(8) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL -// Description : 0-31 -> selects pin function according to the gpio table -// 31 == NULL -// 0x00 -> xip_sd1 -// 0x05 -> sio_33 -// 0x1f -> null -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_MSB _u(4) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_LSB _u(0) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_VALUE_XIP_SD1 _u(0x00) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_VALUE_SIO_33 _u(0x05) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) -// ============================================================================= -// Register : IO_QSPI_GPIO_QSPI_SD2_STATUS -// Description : GPIO status -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OFFSET _u(0x00000020) -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_BITS _u(0x050a3300) -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQTOPROC -// Description : interrupt to processors, after override is applied -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQTOPROC_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQTOPROC_BITS _u(0x04000000) -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQTOPROC_MSB _u(26) -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQTOPROC_LSB _u(26) -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQTOPROC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQFROMPAD -// Description : interrupt from pad before override is applied -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQFROMPAD_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQFROMPAD_BITS _u(0x01000000) -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQFROMPAD_MSB _u(24) -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQFROMPAD_LSB _u(24) -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQFROMPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SD2_STATUS_INTOPERI -// Description : input signal to peripheral, after override is applied -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_INTOPERI_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_INTOPERI_BITS _u(0x00080000) -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_INTOPERI_MSB _u(19) -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_INTOPERI_LSB _u(19) -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_INTOPERI_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SD2_STATUS_INFROMPAD -// Description : input signal from pad, before override is applied -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_INFROMPAD_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_INFROMPAD_BITS _u(0x00020000) -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_INFROMPAD_MSB _u(17) -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_INFROMPAD_LSB _u(17) -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_INFROMPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SD2_STATUS_OETOPAD -// Description : output enable to pad after register override is applied -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OETOPAD_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OETOPAD_BITS _u(0x00002000) -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OETOPAD_MSB _u(13) -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OETOPAD_LSB _u(13) -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OETOPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SD2_STATUS_OEFROMPERI -// Description : output enable from selected peripheral, before register -// override is applied -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OEFROMPERI_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OEFROMPERI_BITS _u(0x00001000) -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OEFROMPERI_MSB _u(12) -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OEFROMPERI_LSB _u(12) -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OEFROMPERI_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTTOPAD -// Description : output signal to pad after register override is applied -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTTOPAD_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTTOPAD_BITS _u(0x00000200) -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTTOPAD_MSB _u(9) -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTTOPAD_LSB _u(9) -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTTOPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTFROMPERI -// Description : output signal from selected peripheral, before register -// override is applied -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTFROMPERI_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTFROMPERI_BITS _u(0x00000100) -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTFROMPERI_MSB _u(8) -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTFROMPERI_LSB _u(8) -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTFROMPERI_ACCESS "RO" -// ============================================================================= -// Register : IO_QSPI_GPIO_QSPI_SD2_CTRL -// Description : GPIO control including function select and overrides. -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OFFSET _u(0x00000024) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_BITS _u(0x3003331f) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_RESET _u(0x0000001f) -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER -// 0x0 -> don't invert the interrupt -// 0x1 -> invert the interrupt -// 0x2 -> drive interrupt low -// 0x3 -> drive interrupt high -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_MSB _u(29) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_LSB _u(28) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER -// 0x0 -> don't invert the peri input -// 0x1 -> invert the peri input -// 0x2 -> drive peri input low -// 0x3 -> drive peri input high -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_BITS _u(0x00030000) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_MSB _u(17) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_LSB _u(16) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_VALUE_NORMAL _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER -// 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel -// 0x2 -> disable output -// 0x3 -> enable output -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_BITS _u(0x00003000) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_MSB _u(13) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_LSB _u(12) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_VALUE_INVERT _u(0x1) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_VALUE_ENABLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER -// 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel -// 0x2 -> drive output low -// 0x3 -> drive output high -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_BITS _u(0x00000300) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_MSB _u(9) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_LSB _u(8) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL -// Description : 0-31 -> selects pin function according to the gpio table -// 31 == NULL -// 0x00 -> xip_sd2 -// 0x05 -> sio_34 -// 0x1f -> null -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_MSB _u(4) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_LSB _u(0) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_VALUE_XIP_SD2 _u(0x00) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_VALUE_SIO_34 _u(0x05) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) -// ============================================================================= -// Register : IO_QSPI_GPIO_QSPI_SD3_STATUS -// Description : GPIO status -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OFFSET _u(0x00000028) -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_BITS _u(0x050a3300) -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQTOPROC -// Description : interrupt to processors, after override is applied -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQTOPROC_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQTOPROC_BITS _u(0x04000000) -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQTOPROC_MSB _u(26) -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQTOPROC_LSB _u(26) -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQTOPROC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQFROMPAD -// Description : interrupt from pad before override is applied -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQFROMPAD_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQFROMPAD_BITS _u(0x01000000) -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQFROMPAD_MSB _u(24) -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQFROMPAD_LSB _u(24) -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQFROMPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SD3_STATUS_INTOPERI -// Description : input signal to peripheral, after override is applied -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_INTOPERI_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_INTOPERI_BITS _u(0x00080000) -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_INTOPERI_MSB _u(19) -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_INTOPERI_LSB _u(19) -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_INTOPERI_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SD3_STATUS_INFROMPAD -// Description : input signal from pad, before override is applied -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_INFROMPAD_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_INFROMPAD_BITS _u(0x00020000) -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_INFROMPAD_MSB _u(17) -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_INFROMPAD_LSB _u(17) -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_INFROMPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SD3_STATUS_OETOPAD -// Description : output enable to pad after register override is applied -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OETOPAD_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OETOPAD_BITS _u(0x00002000) -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OETOPAD_MSB _u(13) -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OETOPAD_LSB _u(13) -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OETOPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SD3_STATUS_OEFROMPERI -// Description : output enable from selected peripheral, before register -// override is applied -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OEFROMPERI_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OEFROMPERI_BITS _u(0x00001000) -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OEFROMPERI_MSB _u(12) -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OEFROMPERI_LSB _u(12) -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OEFROMPERI_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTTOPAD -// Description : output signal to pad after register override is applied -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTTOPAD_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTTOPAD_BITS _u(0x00000200) -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTTOPAD_MSB _u(9) -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTTOPAD_LSB _u(9) -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTTOPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTFROMPERI -// Description : output signal from selected peripheral, before register -// override is applied -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTFROMPERI_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTFROMPERI_BITS _u(0x00000100) -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTFROMPERI_MSB _u(8) -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTFROMPERI_LSB _u(8) -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTFROMPERI_ACCESS "RO" -// ============================================================================= -// Register : IO_QSPI_GPIO_QSPI_SD3_CTRL -// Description : GPIO control including function select and overrides. -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OFFSET _u(0x0000002c) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_BITS _u(0x3003331f) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_RESET _u(0x0000001f) -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER -// 0x0 -> don't invert the interrupt -// 0x1 -> invert the interrupt -// 0x2 -> drive interrupt low -// 0x3 -> drive interrupt high -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_MSB _u(29) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_LSB _u(28) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER -// 0x0 -> don't invert the peri input -// 0x1 -> invert the peri input -// 0x2 -> drive peri input low -// 0x3 -> drive peri input high -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_BITS _u(0x00030000) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_MSB _u(17) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_LSB _u(16) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_VALUE_NORMAL _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER -// 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel -// 0x2 -> disable output -// 0x3 -> enable output -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_BITS _u(0x00003000) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_MSB _u(13) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_LSB _u(12) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_VALUE_INVERT _u(0x1) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_VALUE_ENABLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER -// 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel -// 0x2 -> drive output low -// 0x3 -> drive output high -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_BITS _u(0x00000300) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_MSB _u(9) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_LSB _u(8) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL -// Description : 0-31 -> selects pin function according to the gpio table -// 31 == NULL -// 0x00 -> xip_sd3 -// 0x05 -> sio_35 -// 0x1f -> null -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_MSB _u(4) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_LSB _u(0) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_VALUE_XIP_SD3 _u(0x00) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_VALUE_SIO_35 _u(0x05) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) -// ============================================================================= -// Register : IO_QSPI_INTR -// Description : Raw Interrupts -#define IO_QSPI_INTR_OFFSET _u(0x00000030) -#define IO_QSPI_INTR_BITS _u(0x00ffffff) -#define IO_QSPI_INTR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_HIGH -#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_HIGH_BITS _u(0x00800000) -#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_HIGH_MSB _u(23) -#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_HIGH_LSB _u(23) -#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_LOW -#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_LOW_BITS _u(0x00400000) -#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_LOW_MSB _u(22) -#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_LOW_LSB _u(22) -#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_HIGH -#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_HIGH_BITS _u(0x00200000) -#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_HIGH_MSB _u(21) -#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_HIGH_LSB _u(21) -#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_LOW -#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_LOW_BITS _u(0x00100000) -#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_LOW_MSB _u(20) -#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_LOW_LSB _u(20) -#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_HIGH -#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_HIGH_BITS _u(0x00080000) -#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_HIGH_MSB _u(19) -#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_HIGH_LSB _u(19) -#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_LOW -#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_LOW_BITS _u(0x00040000) -#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_LOW_MSB _u(18) -#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_LOW_LSB _u(18) -#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_HIGH -#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_HIGH_BITS _u(0x00020000) -#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_HIGH_MSB _u(17) -#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_HIGH_LSB _u(17) -#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_LOW -#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_LOW_BITS _u(0x00010000) -#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_LOW_MSB _u(16) -#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_LOW_LSB _u(16) -#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_HIGH -#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_HIGH_BITS _u(0x00008000) -#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_HIGH_MSB _u(15) -#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_HIGH_LSB _u(15) -#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_LOW -#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_LOW_BITS _u(0x00004000) -#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_LOW_MSB _u(14) -#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_LOW_LSB _u(14) -#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_HIGH -#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_HIGH_BITS _u(0x00002000) -#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_HIGH_MSB _u(13) -#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_HIGH_LSB _u(13) -#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_LOW -#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_LOW_BITS _u(0x00001000) -#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_LOW_MSB _u(12) -#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_LOW_LSB _u(12) -#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_HIGH -#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_HIGH_BITS _u(0x00000800) -#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_HIGH_MSB _u(11) -#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_HIGH_LSB _u(11) -#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_LOW -#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_LOW_BITS _u(0x00000400) -#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_LOW_MSB _u(10) -#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_LOW_LSB _u(10) -#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_HIGH -#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_HIGH_BITS _u(0x00000200) -#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_HIGH_MSB _u(9) -#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_HIGH_LSB _u(9) -#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_LOW -#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_LOW_BITS _u(0x00000100) -#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_LOW_MSB _u(8) -#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_LOW_LSB _u(8) -#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_HIGH -#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_HIGH_BITS _u(0x00000080) -#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_HIGH_MSB _u(7) -#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_HIGH_LSB _u(7) -#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_LOW -#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_LOW_BITS _u(0x00000040) -#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_LOW_MSB _u(6) -#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_LOW_LSB _u(6) -#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_LOW_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_HIGH -#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_HIGH_BITS _u(0x00000020) -#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_HIGH_MSB _u(5) -#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_HIGH_LSB _u(5) -#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_LOW -#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_LOW_BITS _u(0x00000010) -#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_LOW_MSB _u(4) -#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_LOW_LSB _u(4) -#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_HIGH -#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_HIGH_BITS _u(0x00000008) -#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_HIGH_MSB _u(3) -#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_HIGH_LSB _u(3) -#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_LOW -#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_LOW_BITS _u(0x00000004) -#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_LOW_MSB _u(2) -#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_LOW_LSB _u(2) -#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_HIGH -#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS _u(0x00000002) -#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB _u(1) -#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB _u(1) -#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_LOW -#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_LOW_BITS _u(0x00000001) -#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_LOW_MSB _u(0) -#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_LOW_LSB _u(0) -#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RO" -// ============================================================================= -// Register : IO_QSPI_PROC0_INTE -// Description : Interrupt Enable for proc0 -#define IO_QSPI_PROC0_INTE_OFFSET _u(0x00000034) -#define IO_QSPI_PROC0_INTE_BITS _u(0x00ffffff) -#define IO_QSPI_PROC0_INTE_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_HIGH -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_HIGH_BITS _u(0x00800000) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_HIGH_MSB _u(23) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_HIGH_LSB _u(23) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_LOW -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_LOW_BITS _u(0x00400000) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_LOW_MSB _u(22) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_LOW_LSB _u(22) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_HIGH -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_BITS _u(0x00200000) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_MSB _u(21) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_LSB _u(21) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_LOW -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_LOW_BITS _u(0x00100000) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_LOW_MSB _u(20) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_LOW_LSB _u(20) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_HIGH -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_HIGH_BITS _u(0x00080000) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_HIGH_MSB _u(19) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_HIGH_LSB _u(19) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_LOW -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_LOW_BITS _u(0x00040000) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_LOW_MSB _u(18) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_LOW_LSB _u(18) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_HIGH -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_BITS _u(0x00020000) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_MSB _u(17) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_LSB _u(17) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_LOW -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_LOW_BITS _u(0x00010000) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_LOW_MSB _u(16) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_LOW_LSB _u(16) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_HIGH -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_HIGH_BITS _u(0x00008000) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_HIGH_MSB _u(15) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_HIGH_LSB _u(15) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_LOW -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_LOW_BITS _u(0x00004000) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_LOW_MSB _u(14) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_LOW_LSB _u(14) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_HIGH -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_BITS _u(0x00002000) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_MSB _u(13) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_LSB _u(13) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_LOW -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_LOW_BITS _u(0x00001000) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_LOW_MSB _u(12) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_LOW_LSB _u(12) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_HIGH -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_HIGH_BITS _u(0x00000800) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_HIGH_MSB _u(11) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_HIGH_LSB _u(11) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_LOW -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_LOW_BITS _u(0x00000400) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_LOW_MSB _u(10) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_LOW_LSB _u(10) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_HIGH -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_BITS _u(0x00000200) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_MSB _u(9) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_LSB _u(9) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_LOW -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_LOW_BITS _u(0x00000100) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_LOW_MSB _u(8) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_LOW_LSB _u(8) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_HIGH -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_HIGH_BITS _u(0x00000080) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_HIGH_MSB _u(7) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_HIGH_LSB _u(7) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_LOW -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_LOW_BITS _u(0x00000040) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_LOW_MSB _u(6) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_LOW_LSB _u(6) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_HIGH -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_HIGH_BITS _u(0x00000020) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_HIGH_MSB _u(5) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_HIGH_LSB _u(5) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_LOW -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_LOW_BITS _u(0x00000010) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_LOW_MSB _u(4) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_LOW_LSB _u(4) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_HIGH -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_BITS _u(0x00000008) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_MSB _u(3) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_LSB _u(3) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_LOW -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_LOW_BITS _u(0x00000004) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_LOW_MSB _u(2) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_LOW_LSB _u(2) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS _u(0x00000002) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB _u(1) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB _u(1) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_LOW -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_BITS _u(0x00000001) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_MSB _u(0) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_LSB _u(0) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RW" -// ============================================================================= -// Register : IO_QSPI_PROC0_INTF -// Description : Interrupt Force for proc0 -#define IO_QSPI_PROC0_INTF_OFFSET _u(0x00000038) -#define IO_QSPI_PROC0_INTF_BITS _u(0x00ffffff) -#define IO_QSPI_PROC0_INTF_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_HIGH -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_HIGH_BITS _u(0x00800000) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_HIGH_MSB _u(23) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_HIGH_LSB _u(23) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_LOW -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_LOW_BITS _u(0x00400000) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_LOW_MSB _u(22) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_LOW_LSB _u(22) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_HIGH -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_BITS _u(0x00200000) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_MSB _u(21) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_LSB _u(21) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_LOW -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_LOW_BITS _u(0x00100000) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_LOW_MSB _u(20) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_LOW_LSB _u(20) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_HIGH -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_HIGH_BITS _u(0x00080000) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_HIGH_MSB _u(19) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_HIGH_LSB _u(19) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_LOW -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_LOW_BITS _u(0x00040000) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_LOW_MSB _u(18) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_LOW_LSB _u(18) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_HIGH -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_BITS _u(0x00020000) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_MSB _u(17) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_LSB _u(17) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_LOW -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_LOW_BITS _u(0x00010000) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_LOW_MSB _u(16) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_LOW_LSB _u(16) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_HIGH -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_HIGH_BITS _u(0x00008000) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_HIGH_MSB _u(15) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_HIGH_LSB _u(15) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_LOW -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_LOW_BITS _u(0x00004000) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_LOW_MSB _u(14) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_LOW_LSB _u(14) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_HIGH -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_BITS _u(0x00002000) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_MSB _u(13) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_LSB _u(13) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_LOW -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_LOW_BITS _u(0x00001000) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_LOW_MSB _u(12) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_LOW_LSB _u(12) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_HIGH -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_HIGH_BITS _u(0x00000800) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_HIGH_MSB _u(11) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_HIGH_LSB _u(11) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_LOW -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_LOW_BITS _u(0x00000400) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_LOW_MSB _u(10) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_LOW_LSB _u(10) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_HIGH -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_BITS _u(0x00000200) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_MSB _u(9) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_LSB _u(9) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_LOW -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_LOW_BITS _u(0x00000100) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_LOW_MSB _u(8) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_LOW_LSB _u(8) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_HIGH -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_HIGH_BITS _u(0x00000080) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_HIGH_MSB _u(7) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_HIGH_LSB _u(7) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_LOW -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_LOW_BITS _u(0x00000040) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_LOW_MSB _u(6) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_LOW_LSB _u(6) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_HIGH -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_HIGH_BITS _u(0x00000020) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_HIGH_MSB _u(5) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_HIGH_LSB _u(5) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_LOW -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_LOW_BITS _u(0x00000010) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_LOW_MSB _u(4) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_LOW_LSB _u(4) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_HIGH -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_BITS _u(0x00000008) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_MSB _u(3) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_LSB _u(3) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_LOW -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_LOW_BITS _u(0x00000004) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_LOW_MSB _u(2) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_LOW_LSB _u(2) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS _u(0x00000002) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB _u(1) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB _u(1) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_LOW -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_BITS _u(0x00000001) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_MSB _u(0) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_LSB _u(0) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RW" -// ============================================================================= -// Register : IO_QSPI_PROC0_INTS -// Description : Interrupt status after masking & forcing for proc0 -#define IO_QSPI_PROC0_INTS_OFFSET _u(0x0000003c) -#define IO_QSPI_PROC0_INTS_BITS _u(0x00ffffff) -#define IO_QSPI_PROC0_INTS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_HIGH -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_HIGH_BITS _u(0x00800000) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_HIGH_MSB _u(23) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_HIGH_LSB _u(23) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_LOW -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_LOW_BITS _u(0x00400000) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_LOW_MSB _u(22) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_LOW_LSB _u(22) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_HIGH -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_BITS _u(0x00200000) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_MSB _u(21) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_LSB _u(21) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_LOW -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_LOW_BITS _u(0x00100000) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_LOW_MSB _u(20) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_LOW_LSB _u(20) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_HIGH -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_HIGH_BITS _u(0x00080000) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_HIGH_MSB _u(19) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_HIGH_LSB _u(19) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_LOW -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_LOW_BITS _u(0x00040000) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_LOW_MSB _u(18) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_LOW_LSB _u(18) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_HIGH -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_BITS _u(0x00020000) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_MSB _u(17) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_LSB _u(17) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_LOW -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_LOW_BITS _u(0x00010000) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_LOW_MSB _u(16) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_LOW_LSB _u(16) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_HIGH -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_HIGH_BITS _u(0x00008000) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_HIGH_MSB _u(15) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_HIGH_LSB _u(15) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_LOW -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_LOW_BITS _u(0x00004000) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_LOW_MSB _u(14) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_LOW_LSB _u(14) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_HIGH -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_BITS _u(0x00002000) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_MSB _u(13) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_LSB _u(13) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_LOW -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_LOW_BITS _u(0x00001000) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_LOW_MSB _u(12) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_LOW_LSB _u(12) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_HIGH -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_HIGH_BITS _u(0x00000800) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_HIGH_MSB _u(11) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_HIGH_LSB _u(11) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_LOW -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_LOW_BITS _u(0x00000400) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_LOW_MSB _u(10) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_LOW_LSB _u(10) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_HIGH -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_BITS _u(0x00000200) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_MSB _u(9) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_LSB _u(9) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_LOW -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_LOW_BITS _u(0x00000100) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_LOW_MSB _u(8) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_LOW_LSB _u(8) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_HIGH -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_HIGH_BITS _u(0x00000080) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_HIGH_MSB _u(7) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_HIGH_LSB _u(7) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_LOW -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_LOW_BITS _u(0x00000040) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_LOW_MSB _u(6) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_LOW_LSB _u(6) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_HIGH -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_HIGH_BITS _u(0x00000020) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_HIGH_MSB _u(5) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_HIGH_LSB _u(5) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_LOW -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_LOW_BITS _u(0x00000010) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_LOW_MSB _u(4) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_LOW_LSB _u(4) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_HIGH -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_BITS _u(0x00000008) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_MSB _u(3) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_LSB _u(3) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_LOW -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_LOW_BITS _u(0x00000004) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_LOW_MSB _u(2) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_LOW_LSB _u(2) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS _u(0x00000002) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB _u(1) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB _u(1) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_LOW -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_BITS _u(0x00000001) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_MSB _u(0) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_LSB _u(0) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RO" -// ============================================================================= -// Register : IO_QSPI_PROC1_INTE -// Description : Interrupt Enable for proc1 -#define IO_QSPI_PROC1_INTE_OFFSET _u(0x00000040) -#define IO_QSPI_PROC1_INTE_BITS _u(0x00ffffff) -#define IO_QSPI_PROC1_INTE_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_HIGH -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_HIGH_BITS _u(0x00800000) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_HIGH_MSB _u(23) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_HIGH_LSB _u(23) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_LOW -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_LOW_BITS _u(0x00400000) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_LOW_MSB _u(22) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_LOW_LSB _u(22) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_HIGH -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_BITS _u(0x00200000) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_MSB _u(21) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_LSB _u(21) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_LOW -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_LOW_BITS _u(0x00100000) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_LOW_MSB _u(20) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_LOW_LSB _u(20) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_HIGH -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_HIGH_BITS _u(0x00080000) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_HIGH_MSB _u(19) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_HIGH_LSB _u(19) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_LOW -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_LOW_BITS _u(0x00040000) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_LOW_MSB _u(18) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_LOW_LSB _u(18) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_HIGH -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_BITS _u(0x00020000) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_MSB _u(17) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_LSB _u(17) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_LOW -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_LOW_BITS _u(0x00010000) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_LOW_MSB _u(16) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_LOW_LSB _u(16) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_HIGH -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_HIGH_BITS _u(0x00008000) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_HIGH_MSB _u(15) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_HIGH_LSB _u(15) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_LOW -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_LOW_BITS _u(0x00004000) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_LOW_MSB _u(14) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_LOW_LSB _u(14) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_HIGH -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_BITS _u(0x00002000) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_MSB _u(13) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_LSB _u(13) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_LOW -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_LOW_BITS _u(0x00001000) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_LOW_MSB _u(12) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_LOW_LSB _u(12) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_HIGH -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_HIGH_BITS _u(0x00000800) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_HIGH_MSB _u(11) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_HIGH_LSB _u(11) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_LOW -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_LOW_BITS _u(0x00000400) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_LOW_MSB _u(10) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_LOW_LSB _u(10) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_HIGH -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_BITS _u(0x00000200) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_MSB _u(9) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_LSB _u(9) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_LOW -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_LOW_BITS _u(0x00000100) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_LOW_MSB _u(8) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_LOW_LSB _u(8) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_HIGH -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_HIGH_BITS _u(0x00000080) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_HIGH_MSB _u(7) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_HIGH_LSB _u(7) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_LOW -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_LOW_BITS _u(0x00000040) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_LOW_MSB _u(6) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_LOW_LSB _u(6) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_HIGH -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_HIGH_BITS _u(0x00000020) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_HIGH_MSB _u(5) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_HIGH_LSB _u(5) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_LOW -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_LOW_BITS _u(0x00000010) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_LOW_MSB _u(4) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_LOW_LSB _u(4) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_HIGH -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_BITS _u(0x00000008) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_MSB _u(3) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_LSB _u(3) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_LOW -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_LOW_BITS _u(0x00000004) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_LOW_MSB _u(2) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_LOW_LSB _u(2) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS _u(0x00000002) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB _u(1) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB _u(1) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_LOW -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_BITS _u(0x00000001) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_MSB _u(0) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_LSB _u(0) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RW" -// ============================================================================= -// Register : IO_QSPI_PROC1_INTF -// Description : Interrupt Force for proc1 -#define IO_QSPI_PROC1_INTF_OFFSET _u(0x00000044) -#define IO_QSPI_PROC1_INTF_BITS _u(0x00ffffff) -#define IO_QSPI_PROC1_INTF_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_HIGH -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_HIGH_BITS _u(0x00800000) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_HIGH_MSB _u(23) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_HIGH_LSB _u(23) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_LOW -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_LOW_BITS _u(0x00400000) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_LOW_MSB _u(22) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_LOW_LSB _u(22) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_HIGH -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_BITS _u(0x00200000) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_MSB _u(21) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_LSB _u(21) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_LOW -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_LOW_BITS _u(0x00100000) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_LOW_MSB _u(20) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_LOW_LSB _u(20) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_HIGH -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_HIGH_BITS _u(0x00080000) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_HIGH_MSB _u(19) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_HIGH_LSB _u(19) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_LOW -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_LOW_BITS _u(0x00040000) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_LOW_MSB _u(18) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_LOW_LSB _u(18) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_HIGH -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_BITS _u(0x00020000) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_MSB _u(17) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_LSB _u(17) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_LOW -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_LOW_BITS _u(0x00010000) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_LOW_MSB _u(16) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_LOW_LSB _u(16) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_HIGH -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_HIGH_BITS _u(0x00008000) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_HIGH_MSB _u(15) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_HIGH_LSB _u(15) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_LOW -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_LOW_BITS _u(0x00004000) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_LOW_MSB _u(14) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_LOW_LSB _u(14) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_HIGH -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_BITS _u(0x00002000) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_MSB _u(13) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_LSB _u(13) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_LOW -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_LOW_BITS _u(0x00001000) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_LOW_MSB _u(12) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_LOW_LSB _u(12) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_HIGH -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_HIGH_BITS _u(0x00000800) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_HIGH_MSB _u(11) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_HIGH_LSB _u(11) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_LOW -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_LOW_BITS _u(0x00000400) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_LOW_MSB _u(10) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_LOW_LSB _u(10) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_HIGH -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_BITS _u(0x00000200) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_MSB _u(9) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_LSB _u(9) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_LOW -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_LOW_BITS _u(0x00000100) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_LOW_MSB _u(8) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_LOW_LSB _u(8) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_HIGH -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_HIGH_BITS _u(0x00000080) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_HIGH_MSB _u(7) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_HIGH_LSB _u(7) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_LOW -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_LOW_BITS _u(0x00000040) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_LOW_MSB _u(6) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_LOW_LSB _u(6) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_HIGH -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_HIGH_BITS _u(0x00000020) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_HIGH_MSB _u(5) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_HIGH_LSB _u(5) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_LOW -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_LOW_BITS _u(0x00000010) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_LOW_MSB _u(4) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_LOW_LSB _u(4) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_HIGH -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_BITS _u(0x00000008) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_MSB _u(3) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_LSB _u(3) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_LOW -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_LOW_BITS _u(0x00000004) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_LOW_MSB _u(2) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_LOW_LSB _u(2) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS _u(0x00000002) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB _u(1) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB _u(1) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_LOW -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_BITS _u(0x00000001) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_MSB _u(0) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_LSB _u(0) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RW" -// ============================================================================= -// Register : IO_QSPI_PROC1_INTS -// Description : Interrupt status after masking & forcing for proc1 -#define IO_QSPI_PROC1_INTS_OFFSET _u(0x00000048) -#define IO_QSPI_PROC1_INTS_BITS _u(0x00ffffff) -#define IO_QSPI_PROC1_INTS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_HIGH -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_HIGH_BITS _u(0x00800000) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_HIGH_MSB _u(23) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_HIGH_LSB _u(23) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_LOW -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_LOW_BITS _u(0x00400000) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_LOW_MSB _u(22) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_LOW_LSB _u(22) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_HIGH -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_BITS _u(0x00200000) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_MSB _u(21) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_LSB _u(21) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_LOW -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_LOW_BITS _u(0x00100000) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_LOW_MSB _u(20) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_LOW_LSB _u(20) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_HIGH -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_HIGH_BITS _u(0x00080000) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_HIGH_MSB _u(19) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_HIGH_LSB _u(19) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_LOW -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_LOW_BITS _u(0x00040000) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_LOW_MSB _u(18) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_LOW_LSB _u(18) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_HIGH -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_BITS _u(0x00020000) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_MSB _u(17) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_LSB _u(17) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_LOW -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_LOW_BITS _u(0x00010000) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_LOW_MSB _u(16) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_LOW_LSB _u(16) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_HIGH -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_HIGH_BITS _u(0x00008000) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_HIGH_MSB _u(15) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_HIGH_LSB _u(15) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_LOW -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_LOW_BITS _u(0x00004000) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_LOW_MSB _u(14) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_LOW_LSB _u(14) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_HIGH -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_BITS _u(0x00002000) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_MSB _u(13) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_LSB _u(13) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_LOW -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_LOW_BITS _u(0x00001000) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_LOW_MSB _u(12) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_LOW_LSB _u(12) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_HIGH -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_HIGH_BITS _u(0x00000800) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_HIGH_MSB _u(11) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_HIGH_LSB _u(11) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_LOW -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_LOW_BITS _u(0x00000400) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_LOW_MSB _u(10) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_LOW_LSB _u(10) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_HIGH -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_BITS _u(0x00000200) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_MSB _u(9) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_LSB _u(9) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_LOW -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_LOW_BITS _u(0x00000100) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_LOW_MSB _u(8) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_LOW_LSB _u(8) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_HIGH -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_HIGH_BITS _u(0x00000080) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_HIGH_MSB _u(7) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_HIGH_LSB _u(7) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_LOW -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_LOW_BITS _u(0x00000040) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_LOW_MSB _u(6) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_LOW_LSB _u(6) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_HIGH -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_HIGH_BITS _u(0x00000020) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_HIGH_MSB _u(5) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_HIGH_LSB _u(5) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_LOW -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_LOW_BITS _u(0x00000010) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_LOW_MSB _u(4) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_LOW_LSB _u(4) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_HIGH -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_BITS _u(0x00000008) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_MSB _u(3) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_LSB _u(3) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_LOW -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_LOW_BITS _u(0x00000004) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_LOW_MSB _u(2) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_LOW_LSB _u(2) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS _u(0x00000002) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB _u(1) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB _u(1) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_LOW -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_BITS _u(0x00000001) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_MSB _u(0) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_LSB _u(0) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RO" -// ============================================================================= -// Register : IO_QSPI_DORMANT_WAKE_INTE -// Description : Interrupt Enable for dormant_wake -#define IO_QSPI_DORMANT_WAKE_INTE_OFFSET _u(0x0000004c) -#define IO_QSPI_DORMANT_WAKE_INTE_BITS _u(0x00ffffff) -#define IO_QSPI_DORMANT_WAKE_INTE_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_HIGH -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_HIGH_BITS _u(0x00800000) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_HIGH_MSB _u(23) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_HIGH_LSB _u(23) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_LOW -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_LOW_BITS _u(0x00400000) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_LOW_MSB _u(22) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_LOW_LSB _u(22) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_HIGH -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_BITS _u(0x00200000) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_MSB _u(21) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_LSB _u(21) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_LOW -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_LOW_BITS _u(0x00100000) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_LOW_MSB _u(20) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_LOW_LSB _u(20) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_HIGH -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_HIGH_BITS _u(0x00080000) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_HIGH_MSB _u(19) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_HIGH_LSB _u(19) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_LOW -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_LOW_BITS _u(0x00040000) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_LOW_MSB _u(18) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_LOW_LSB _u(18) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_HIGH -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_BITS _u(0x00020000) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_MSB _u(17) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_LSB _u(17) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_LOW -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_LOW_BITS _u(0x00010000) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_LOW_MSB _u(16) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_LOW_LSB _u(16) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_HIGH -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_HIGH_BITS _u(0x00008000) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_HIGH_MSB _u(15) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_HIGH_LSB _u(15) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_LOW -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_LOW_BITS _u(0x00004000) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_LOW_MSB _u(14) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_LOW_LSB _u(14) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_HIGH -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_BITS _u(0x00002000) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_MSB _u(13) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_LSB _u(13) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_LOW -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_LOW_BITS _u(0x00001000) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_LOW_MSB _u(12) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_LOW_LSB _u(12) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_HIGH -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_HIGH_BITS _u(0x00000800) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_HIGH_MSB _u(11) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_HIGH_LSB _u(11) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_LOW -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_LOW_BITS _u(0x00000400) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_LOW_MSB _u(10) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_LOW_LSB _u(10) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_HIGH -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_BITS _u(0x00000200) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_MSB _u(9) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_LSB _u(9) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_LOW -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_LOW_BITS _u(0x00000100) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_LOW_MSB _u(8) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_LOW_LSB _u(8) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_HIGH -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_HIGH_BITS _u(0x00000080) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_HIGH_MSB _u(7) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_HIGH_LSB _u(7) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_LOW -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_LOW_BITS _u(0x00000040) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_LOW_MSB _u(6) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_LOW_LSB _u(6) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_HIGH -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_HIGH_BITS _u(0x00000020) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_HIGH_MSB _u(5) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_HIGH_LSB _u(5) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_LOW -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_LOW_BITS _u(0x00000010) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_LOW_MSB _u(4) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_LOW_LSB _u(4) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_HIGH -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_BITS _u(0x00000008) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_MSB _u(3) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_LSB _u(3) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_LOW -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_LOW_BITS _u(0x00000004) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_LOW_MSB _u(2) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_LOW_LSB _u(2) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS _u(0x00000002) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB _u(1) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB _u(1) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_LOW -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_BITS _u(0x00000001) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_MSB _u(0) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_LSB _u(0) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RW" -// ============================================================================= -// Register : IO_QSPI_DORMANT_WAKE_INTF -// Description : Interrupt Force for dormant_wake -#define IO_QSPI_DORMANT_WAKE_INTF_OFFSET _u(0x00000050) -#define IO_QSPI_DORMANT_WAKE_INTF_BITS _u(0x00ffffff) -#define IO_QSPI_DORMANT_WAKE_INTF_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_HIGH -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_HIGH_BITS _u(0x00800000) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_HIGH_MSB _u(23) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_HIGH_LSB _u(23) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_LOW -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_LOW_BITS _u(0x00400000) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_LOW_MSB _u(22) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_LOW_LSB _u(22) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_HIGH -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_BITS _u(0x00200000) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_MSB _u(21) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_LSB _u(21) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_LOW -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_LOW_BITS _u(0x00100000) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_LOW_MSB _u(20) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_LOW_LSB _u(20) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_HIGH -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_HIGH_BITS _u(0x00080000) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_HIGH_MSB _u(19) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_HIGH_LSB _u(19) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_LOW -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_LOW_BITS _u(0x00040000) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_LOW_MSB _u(18) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_LOW_LSB _u(18) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_HIGH -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_BITS _u(0x00020000) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_MSB _u(17) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_LSB _u(17) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_LOW -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_LOW_BITS _u(0x00010000) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_LOW_MSB _u(16) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_LOW_LSB _u(16) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_HIGH -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_HIGH_BITS _u(0x00008000) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_HIGH_MSB _u(15) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_HIGH_LSB _u(15) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_LOW -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_LOW_BITS _u(0x00004000) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_LOW_MSB _u(14) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_LOW_LSB _u(14) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_HIGH -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_BITS _u(0x00002000) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_MSB _u(13) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_LSB _u(13) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_LOW -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_LOW_BITS _u(0x00001000) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_LOW_MSB _u(12) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_LOW_LSB _u(12) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_HIGH -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_HIGH_BITS _u(0x00000800) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_HIGH_MSB _u(11) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_HIGH_LSB _u(11) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_LOW -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_LOW_BITS _u(0x00000400) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_LOW_MSB _u(10) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_LOW_LSB _u(10) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_HIGH -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_BITS _u(0x00000200) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_MSB _u(9) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_LSB _u(9) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_LOW -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_LOW_BITS _u(0x00000100) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_LOW_MSB _u(8) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_LOW_LSB _u(8) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_HIGH -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_HIGH_BITS _u(0x00000080) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_HIGH_MSB _u(7) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_HIGH_LSB _u(7) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_LOW -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_LOW_BITS _u(0x00000040) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_LOW_MSB _u(6) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_LOW_LSB _u(6) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_HIGH -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_HIGH_BITS _u(0x00000020) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_HIGH_MSB _u(5) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_HIGH_LSB _u(5) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_LOW -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_LOW_BITS _u(0x00000010) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_LOW_MSB _u(4) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_LOW_LSB _u(4) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_HIGH -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_BITS _u(0x00000008) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_MSB _u(3) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_LSB _u(3) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_LOW -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_LOW_BITS _u(0x00000004) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_LOW_MSB _u(2) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_LOW_LSB _u(2) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS _u(0x00000002) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB _u(1) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB _u(1) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_LOW -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_BITS _u(0x00000001) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_MSB _u(0) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_LSB _u(0) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RW" -// ============================================================================= -// Register : IO_QSPI_DORMANT_WAKE_INTS -// Description : Interrupt status after masking & forcing for dormant_wake -#define IO_QSPI_DORMANT_WAKE_INTS_OFFSET _u(0x00000054) -#define IO_QSPI_DORMANT_WAKE_INTS_BITS _u(0x00ffffff) -#define IO_QSPI_DORMANT_WAKE_INTS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_HIGH -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_HIGH_BITS _u(0x00800000) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_HIGH_MSB _u(23) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_HIGH_LSB _u(23) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_LOW -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_LOW_BITS _u(0x00400000) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_LOW_MSB _u(22) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_LOW_LSB _u(22) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_HIGH -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_BITS _u(0x00200000) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_MSB _u(21) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_LSB _u(21) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_LOW -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_LOW_BITS _u(0x00100000) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_LOW_MSB _u(20) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_LOW_LSB _u(20) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_HIGH -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_HIGH_BITS _u(0x00080000) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_HIGH_MSB _u(19) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_HIGH_LSB _u(19) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_LOW -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_LOW_BITS _u(0x00040000) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_LOW_MSB _u(18) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_LOW_LSB _u(18) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_HIGH -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_BITS _u(0x00020000) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_MSB _u(17) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_LSB _u(17) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_LOW -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_LOW_BITS _u(0x00010000) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_LOW_MSB _u(16) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_LOW_LSB _u(16) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_HIGH -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_HIGH_BITS _u(0x00008000) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_HIGH_MSB _u(15) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_HIGH_LSB _u(15) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_LOW -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_LOW_BITS _u(0x00004000) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_LOW_MSB _u(14) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_LOW_LSB _u(14) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_HIGH -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_BITS _u(0x00002000) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_MSB _u(13) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_LSB _u(13) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_LOW -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_LOW_BITS _u(0x00001000) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_LOW_MSB _u(12) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_LOW_LSB _u(12) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_HIGH -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_HIGH_BITS _u(0x00000800) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_HIGH_MSB _u(11) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_HIGH_LSB _u(11) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_LOW -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_LOW_BITS _u(0x00000400) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_LOW_MSB _u(10) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_LOW_LSB _u(10) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_HIGH -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_BITS _u(0x00000200) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_MSB _u(9) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_LSB _u(9) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_LOW -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_LOW_BITS _u(0x00000100) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_LOW_MSB _u(8) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_LOW_LSB _u(8) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_HIGH -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_HIGH_BITS _u(0x00000080) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_HIGH_MSB _u(7) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_HIGH_LSB _u(7) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_LOW -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_LOW_BITS _u(0x00000040) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_LOW_MSB _u(6) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_LOW_LSB _u(6) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_HIGH -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_HIGH_BITS _u(0x00000020) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_HIGH_MSB _u(5) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_HIGH_LSB _u(5) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_LOW -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_LOW_BITS _u(0x00000010) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_LOW_MSB _u(4) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_LOW_LSB _u(4) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_HIGH -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_BITS _u(0x00000008) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_MSB _u(3) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_LSB _u(3) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_LOW -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_LOW_BITS _u(0x00000004) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_LOW_MSB _u(2) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_LOW_LSB _u(2) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS _u(0x00000002) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB _u(1) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB _u(1) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_LOW -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_BITS _u(0x00000001) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_MSB _u(0) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_LSB _u(0) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RO" -// ============================================================================= -#endif // _HARDWARE_REGS_IO_QSPI_H - diff --git a/lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/m0plus.h b/lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/m0plus.h deleted file mode 100644 index 028e5ad851..0000000000 --- a/lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/m0plus.h +++ /dev/null @@ -1,1151 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -// ============================================================================= -// Register block : M0PLUS -// Version : 1 -// Bus type : ahbl -// ============================================================================= -#ifndef _HARDWARE_REGS_M0PLUS_H -#define _HARDWARE_REGS_M0PLUS_H -// ============================================================================= -// Register : M0PLUS_SYST_CSR -// Description : Use the SysTick Control and Status Register to enable the -// SysTick features. -#define M0PLUS_SYST_CSR_OFFSET _u(0x0000e010) -#define M0PLUS_SYST_CSR_BITS _u(0x00010007) -#define M0PLUS_SYST_CSR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M0PLUS_SYST_CSR_COUNTFLAG -// Description : Returns 1 if timer counted to 0 since last time this was read. -// Clears on read by application or debugger. -#define M0PLUS_SYST_CSR_COUNTFLAG_RESET _u(0x0) -#define M0PLUS_SYST_CSR_COUNTFLAG_BITS _u(0x00010000) -#define M0PLUS_SYST_CSR_COUNTFLAG_MSB _u(16) -#define M0PLUS_SYST_CSR_COUNTFLAG_LSB _u(16) -#define M0PLUS_SYST_CSR_COUNTFLAG_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M0PLUS_SYST_CSR_CLKSOURCE -// Description : SysTick clock source. Always reads as one if SYST_CALIB reports -// NOREF. -// Selects the SysTick timer clock source: -// 0 = External reference clock. -// 1 = Processor clock. -#define M0PLUS_SYST_CSR_CLKSOURCE_RESET _u(0x0) -#define M0PLUS_SYST_CSR_CLKSOURCE_BITS _u(0x00000004) -#define M0PLUS_SYST_CSR_CLKSOURCE_MSB _u(2) -#define M0PLUS_SYST_CSR_CLKSOURCE_LSB _u(2) -#define M0PLUS_SYST_CSR_CLKSOURCE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M0PLUS_SYST_CSR_TICKINT -// Description : Enables SysTick exception request: -// 0 = Counting down to zero does not assert the SysTick exception -// request. -// 1 = Counting down to zero to asserts the SysTick exception -// request. -#define M0PLUS_SYST_CSR_TICKINT_RESET _u(0x0) -#define M0PLUS_SYST_CSR_TICKINT_BITS _u(0x00000002) -#define M0PLUS_SYST_CSR_TICKINT_MSB _u(1) -#define M0PLUS_SYST_CSR_TICKINT_LSB _u(1) -#define M0PLUS_SYST_CSR_TICKINT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M0PLUS_SYST_CSR_ENABLE -// Description : Enable SysTick counter: -// 0 = Counter disabled. -// 1 = Counter enabled. -#define M0PLUS_SYST_CSR_ENABLE_RESET _u(0x0) -#define M0PLUS_SYST_CSR_ENABLE_BITS _u(0x00000001) -#define M0PLUS_SYST_CSR_ENABLE_MSB _u(0) -#define M0PLUS_SYST_CSR_ENABLE_LSB _u(0) -#define M0PLUS_SYST_CSR_ENABLE_ACCESS "RW" -// ============================================================================= -// Register : M0PLUS_SYST_RVR -// Description : Use the SysTick Reload Value Register to specify the start -// value to load into the current value register when the counter -// reaches 0. It can be any value between 0 and 0x00FFFFFF. A -// start value of 0 is possible, but has no effect because the -// SysTick interrupt and COUNTFLAG are activated when counting -// from 1 to 0. The reset value of this register is UNKNOWN. -// To generate a multi-shot timer with a period of N processor -// clock cycles, use a RELOAD value of N-1. For example, if the -// SysTick interrupt is required every 100 clock pulses, set -// RELOAD to 99. -#define M0PLUS_SYST_RVR_OFFSET _u(0x0000e014) -#define M0PLUS_SYST_RVR_BITS _u(0x00ffffff) -#define M0PLUS_SYST_RVR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M0PLUS_SYST_RVR_RELOAD -// Description : Value to load into the SysTick Current Value Register when the -// counter reaches 0. -#define M0PLUS_SYST_RVR_RELOAD_RESET _u(0x000000) -#define M0PLUS_SYST_RVR_RELOAD_BITS _u(0x00ffffff) -#define M0PLUS_SYST_RVR_RELOAD_MSB _u(23) -#define M0PLUS_SYST_RVR_RELOAD_LSB _u(0) -#define M0PLUS_SYST_RVR_RELOAD_ACCESS "RW" -// ============================================================================= -// Register : M0PLUS_SYST_CVR -// Description : Use the SysTick Current Value Register to find the current -// value in the register. The reset value of this register is -// UNKNOWN. -#define M0PLUS_SYST_CVR_OFFSET _u(0x0000e018) -#define M0PLUS_SYST_CVR_BITS _u(0x00ffffff) -#define M0PLUS_SYST_CVR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M0PLUS_SYST_CVR_CURRENT -// Description : Reads return the current value of the SysTick counter. This -// register is write-clear. Writing to it with any value clears -// the register to 0. Clearing this register also clears the -// COUNTFLAG bit of the SysTick Control and Status Register. -#define M0PLUS_SYST_CVR_CURRENT_RESET _u(0x000000) -#define M0PLUS_SYST_CVR_CURRENT_BITS _u(0x00ffffff) -#define M0PLUS_SYST_CVR_CURRENT_MSB _u(23) -#define M0PLUS_SYST_CVR_CURRENT_LSB _u(0) -#define M0PLUS_SYST_CVR_CURRENT_ACCESS "RW" -// ============================================================================= -// Register : M0PLUS_SYST_CALIB -// Description : Use the SysTick Calibration Value Register to enable software -// to scale to any required speed using divide and multiply. -#define M0PLUS_SYST_CALIB_OFFSET _u(0x0000e01c) -#define M0PLUS_SYST_CALIB_BITS _u(0xc0ffffff) -#define M0PLUS_SYST_CALIB_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M0PLUS_SYST_CALIB_NOREF -// Description : If reads as 1, the Reference clock is not provided - the -// CLKSOURCE bit of the SysTick Control and Status register will -// be forced to 1 and cannot be cleared to 0. -#define M0PLUS_SYST_CALIB_NOREF_RESET _u(0x0) -#define M0PLUS_SYST_CALIB_NOREF_BITS _u(0x80000000) -#define M0PLUS_SYST_CALIB_NOREF_MSB _u(31) -#define M0PLUS_SYST_CALIB_NOREF_LSB _u(31) -#define M0PLUS_SYST_CALIB_NOREF_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M0PLUS_SYST_CALIB_SKEW -// Description : If reads as 1, the calibration value for 10ms is inexact (due -// to clock frequency). -#define M0PLUS_SYST_CALIB_SKEW_RESET _u(0x0) -#define M0PLUS_SYST_CALIB_SKEW_BITS _u(0x40000000) -#define M0PLUS_SYST_CALIB_SKEW_MSB _u(30) -#define M0PLUS_SYST_CALIB_SKEW_LSB _u(30) -#define M0PLUS_SYST_CALIB_SKEW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M0PLUS_SYST_CALIB_TENMS -// Description : An optional Reload value to be used for 10ms (100Hz) timing, -// subject to system clock skew errors. If the value reads as 0, -// the calibration value is not known. -#define M0PLUS_SYST_CALIB_TENMS_RESET _u(0x000000) -#define M0PLUS_SYST_CALIB_TENMS_BITS _u(0x00ffffff) -#define M0PLUS_SYST_CALIB_TENMS_MSB _u(23) -#define M0PLUS_SYST_CALIB_TENMS_LSB _u(0) -#define M0PLUS_SYST_CALIB_TENMS_ACCESS "RO" -// ============================================================================= -// Register : M0PLUS_NVIC_ISER -// Description : Use the Interrupt Set-Enable Register to enable interrupts and -// determine which interrupts are currently enabled. -// If a pending interrupt is enabled, the NVIC activates the -// interrupt based on its priority. If an interrupt is not -// enabled, asserting its interrupt signal changes the interrupt -// state to pending, but the NVIC never activates the interrupt, -// regardless of its priority. -#define M0PLUS_NVIC_ISER_OFFSET _u(0x0000e100) -#define M0PLUS_NVIC_ISER_BITS _u(0xffffffff) -#define M0PLUS_NVIC_ISER_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M0PLUS_NVIC_ISER_SETENA -// Description : Interrupt set-enable bits. -// Write: -// 0 = No effect. -// 1 = Enable interrupt. -// Read: -// 0 = Interrupt disabled. -// 1 = Interrupt enabled. -#define M0PLUS_NVIC_ISER_SETENA_RESET _u(0x00000000) -#define M0PLUS_NVIC_ISER_SETENA_BITS _u(0xffffffff) -#define M0PLUS_NVIC_ISER_SETENA_MSB _u(31) -#define M0PLUS_NVIC_ISER_SETENA_LSB _u(0) -#define M0PLUS_NVIC_ISER_SETENA_ACCESS "RW" -// ============================================================================= -// Register : M0PLUS_NVIC_ICER -// Description : Use the Interrupt Clear-Enable Registers to disable interrupts -// and determine which interrupts are currently enabled. -#define M0PLUS_NVIC_ICER_OFFSET _u(0x0000e180) -#define M0PLUS_NVIC_ICER_BITS _u(0xffffffff) -#define M0PLUS_NVIC_ICER_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M0PLUS_NVIC_ICER_CLRENA -// Description : Interrupt clear-enable bits. -// Write: -// 0 = No effect. -// 1 = Disable interrupt. -// Read: -// 0 = Interrupt disabled. -// 1 = Interrupt enabled. -#define M0PLUS_NVIC_ICER_CLRENA_RESET _u(0x00000000) -#define M0PLUS_NVIC_ICER_CLRENA_BITS _u(0xffffffff) -#define M0PLUS_NVIC_ICER_CLRENA_MSB _u(31) -#define M0PLUS_NVIC_ICER_CLRENA_LSB _u(0) -#define M0PLUS_NVIC_ICER_CLRENA_ACCESS "RW" -// ============================================================================= -// Register : M0PLUS_NVIC_ISPR -// Description : The NVIC_ISPR forces interrupts into the pending state, and -// shows which interrupts are pending. -#define M0PLUS_NVIC_ISPR_OFFSET _u(0x0000e200) -#define M0PLUS_NVIC_ISPR_BITS _u(0xffffffff) -#define M0PLUS_NVIC_ISPR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M0PLUS_NVIC_ISPR_SETPEND -// Description : Interrupt set-pending bits. -// Write: -// 0 = No effect. -// 1 = Changes interrupt state to pending. -// Read: -// 0 = Interrupt is not pending. -// 1 = Interrupt is pending. -// Note: Writing 1 to the NVIC_ISPR bit corresponding to: -// An interrupt that is pending has no effect. -// A disabled interrupt sets the state of that interrupt to -// pending. -#define M0PLUS_NVIC_ISPR_SETPEND_RESET _u(0x00000000) -#define M0PLUS_NVIC_ISPR_SETPEND_BITS _u(0xffffffff) -#define M0PLUS_NVIC_ISPR_SETPEND_MSB _u(31) -#define M0PLUS_NVIC_ISPR_SETPEND_LSB _u(0) -#define M0PLUS_NVIC_ISPR_SETPEND_ACCESS "RW" -// ============================================================================= -// Register : M0PLUS_NVIC_ICPR -// Description : Use the Interrupt Clear-Pending Register to clear pending -// interrupts and determine which interrupts are currently -// pending. -#define M0PLUS_NVIC_ICPR_OFFSET _u(0x0000e280) -#define M0PLUS_NVIC_ICPR_BITS _u(0xffffffff) -#define M0PLUS_NVIC_ICPR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M0PLUS_NVIC_ICPR_CLRPEND -// Description : Interrupt clear-pending bits. -// Write: -// 0 = No effect. -// 1 = Removes pending state and interrupt. -// Read: -// 0 = Interrupt is not pending. -// 1 = Interrupt is pending. -#define M0PLUS_NVIC_ICPR_CLRPEND_RESET _u(0x00000000) -#define M0PLUS_NVIC_ICPR_CLRPEND_BITS _u(0xffffffff) -#define M0PLUS_NVIC_ICPR_CLRPEND_MSB _u(31) -#define M0PLUS_NVIC_ICPR_CLRPEND_LSB _u(0) -#define M0PLUS_NVIC_ICPR_CLRPEND_ACCESS "RW" -// ============================================================================= -// Register : M0PLUS_NVIC_IPR0 -// Description : Use the Interrupt Priority Registers to assign a priority from -// 0 to 3 to each of the available interrupts. 0 is the highest -// priority, and 3 is the lowest. -// Note: Writing 1 to an NVIC_ICPR bit does not affect the active -// state of the corresponding interrupt. -// These registers are only word-accessible -#define M0PLUS_NVIC_IPR0_OFFSET _u(0x0000e400) -#define M0PLUS_NVIC_IPR0_BITS _u(0xc0c0c0c0) -#define M0PLUS_NVIC_IPR0_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M0PLUS_NVIC_IPR0_IP_3 -// Description : Priority of interrupt 3 -#define M0PLUS_NVIC_IPR0_IP_3_RESET _u(0x0) -#define M0PLUS_NVIC_IPR0_IP_3_BITS _u(0xc0000000) -#define M0PLUS_NVIC_IPR0_IP_3_MSB _u(31) -#define M0PLUS_NVIC_IPR0_IP_3_LSB _u(30) -#define M0PLUS_NVIC_IPR0_IP_3_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M0PLUS_NVIC_IPR0_IP_2 -// Description : Priority of interrupt 2 -#define M0PLUS_NVIC_IPR0_IP_2_RESET _u(0x0) -#define M0PLUS_NVIC_IPR0_IP_2_BITS _u(0x00c00000) -#define M0PLUS_NVIC_IPR0_IP_2_MSB _u(23) -#define M0PLUS_NVIC_IPR0_IP_2_LSB _u(22) -#define M0PLUS_NVIC_IPR0_IP_2_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M0PLUS_NVIC_IPR0_IP_1 -// Description : Priority of interrupt 1 -#define M0PLUS_NVIC_IPR0_IP_1_RESET _u(0x0) -#define M0PLUS_NVIC_IPR0_IP_1_BITS _u(0x0000c000) -#define M0PLUS_NVIC_IPR0_IP_1_MSB _u(15) -#define M0PLUS_NVIC_IPR0_IP_1_LSB _u(14) -#define M0PLUS_NVIC_IPR0_IP_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M0PLUS_NVIC_IPR0_IP_0 -// Description : Priority of interrupt 0 -#define M0PLUS_NVIC_IPR0_IP_0_RESET _u(0x0) -#define M0PLUS_NVIC_IPR0_IP_0_BITS _u(0x000000c0) -#define M0PLUS_NVIC_IPR0_IP_0_MSB _u(7) -#define M0PLUS_NVIC_IPR0_IP_0_LSB _u(6) -#define M0PLUS_NVIC_IPR0_IP_0_ACCESS "RW" -// ============================================================================= -// Register : M0PLUS_NVIC_IPR1 -// Description : Use the Interrupt Priority Registers to assign a priority from -// 0 to 3 to each of the available interrupts. 0 is the highest -// priority, and 3 is the lowest. -#define M0PLUS_NVIC_IPR1_OFFSET _u(0x0000e404) -#define M0PLUS_NVIC_IPR1_BITS _u(0xc0c0c0c0) -#define M0PLUS_NVIC_IPR1_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M0PLUS_NVIC_IPR1_IP_7 -// Description : Priority of interrupt 7 -#define M0PLUS_NVIC_IPR1_IP_7_RESET _u(0x0) -#define M0PLUS_NVIC_IPR1_IP_7_BITS _u(0xc0000000) -#define M0PLUS_NVIC_IPR1_IP_7_MSB _u(31) -#define M0PLUS_NVIC_IPR1_IP_7_LSB _u(30) -#define M0PLUS_NVIC_IPR1_IP_7_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M0PLUS_NVIC_IPR1_IP_6 -// Description : Priority of interrupt 6 -#define M0PLUS_NVIC_IPR1_IP_6_RESET _u(0x0) -#define M0PLUS_NVIC_IPR1_IP_6_BITS _u(0x00c00000) -#define M0PLUS_NVIC_IPR1_IP_6_MSB _u(23) -#define M0PLUS_NVIC_IPR1_IP_6_LSB _u(22) -#define M0PLUS_NVIC_IPR1_IP_6_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M0PLUS_NVIC_IPR1_IP_5 -// Description : Priority of interrupt 5 -#define M0PLUS_NVIC_IPR1_IP_5_RESET _u(0x0) -#define M0PLUS_NVIC_IPR1_IP_5_BITS _u(0x0000c000) -#define M0PLUS_NVIC_IPR1_IP_5_MSB _u(15) -#define M0PLUS_NVIC_IPR1_IP_5_LSB _u(14) -#define M0PLUS_NVIC_IPR1_IP_5_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M0PLUS_NVIC_IPR1_IP_4 -// Description : Priority of interrupt 4 -#define M0PLUS_NVIC_IPR1_IP_4_RESET _u(0x0) -#define M0PLUS_NVIC_IPR1_IP_4_BITS _u(0x000000c0) -#define M0PLUS_NVIC_IPR1_IP_4_MSB _u(7) -#define M0PLUS_NVIC_IPR1_IP_4_LSB _u(6) -#define M0PLUS_NVIC_IPR1_IP_4_ACCESS "RW" -// ============================================================================= -// Register : M0PLUS_NVIC_IPR2 -// Description : Use the Interrupt Priority Registers to assign a priority from -// 0 to 3 to each of the available interrupts. 0 is the highest -// priority, and 3 is the lowest. -#define M0PLUS_NVIC_IPR2_OFFSET _u(0x0000e408) -#define M0PLUS_NVIC_IPR2_BITS _u(0xc0c0c0c0) -#define M0PLUS_NVIC_IPR2_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M0PLUS_NVIC_IPR2_IP_11 -// Description : Priority of interrupt 11 -#define M0PLUS_NVIC_IPR2_IP_11_RESET _u(0x0) -#define M0PLUS_NVIC_IPR2_IP_11_BITS _u(0xc0000000) -#define M0PLUS_NVIC_IPR2_IP_11_MSB _u(31) -#define M0PLUS_NVIC_IPR2_IP_11_LSB _u(30) -#define M0PLUS_NVIC_IPR2_IP_11_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M0PLUS_NVIC_IPR2_IP_10 -// Description : Priority of interrupt 10 -#define M0PLUS_NVIC_IPR2_IP_10_RESET _u(0x0) -#define M0PLUS_NVIC_IPR2_IP_10_BITS _u(0x00c00000) -#define M0PLUS_NVIC_IPR2_IP_10_MSB _u(23) -#define M0PLUS_NVIC_IPR2_IP_10_LSB _u(22) -#define M0PLUS_NVIC_IPR2_IP_10_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M0PLUS_NVIC_IPR2_IP_9 -// Description : Priority of interrupt 9 -#define M0PLUS_NVIC_IPR2_IP_9_RESET _u(0x0) -#define M0PLUS_NVIC_IPR2_IP_9_BITS _u(0x0000c000) -#define M0PLUS_NVIC_IPR2_IP_9_MSB _u(15) -#define M0PLUS_NVIC_IPR2_IP_9_LSB _u(14) -#define M0PLUS_NVIC_IPR2_IP_9_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M0PLUS_NVIC_IPR2_IP_8 -// Description : Priority of interrupt 8 -#define M0PLUS_NVIC_IPR2_IP_8_RESET _u(0x0) -#define M0PLUS_NVIC_IPR2_IP_8_BITS _u(0x000000c0) -#define M0PLUS_NVIC_IPR2_IP_8_MSB _u(7) -#define M0PLUS_NVIC_IPR2_IP_8_LSB _u(6) -#define M0PLUS_NVIC_IPR2_IP_8_ACCESS "RW" -// ============================================================================= -// Register : M0PLUS_NVIC_IPR3 -// Description : Use the Interrupt Priority Registers to assign a priority from -// 0 to 3 to each of the available interrupts. 0 is the highest -// priority, and 3 is the lowest. -#define M0PLUS_NVIC_IPR3_OFFSET _u(0x0000e40c) -#define M0PLUS_NVIC_IPR3_BITS _u(0xc0c0c0c0) -#define M0PLUS_NVIC_IPR3_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M0PLUS_NVIC_IPR3_IP_15 -// Description : Priority of interrupt 15 -#define M0PLUS_NVIC_IPR3_IP_15_RESET _u(0x0) -#define M0PLUS_NVIC_IPR3_IP_15_BITS _u(0xc0000000) -#define M0PLUS_NVIC_IPR3_IP_15_MSB _u(31) -#define M0PLUS_NVIC_IPR3_IP_15_LSB _u(30) -#define M0PLUS_NVIC_IPR3_IP_15_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M0PLUS_NVIC_IPR3_IP_14 -// Description : Priority of interrupt 14 -#define M0PLUS_NVIC_IPR3_IP_14_RESET _u(0x0) -#define M0PLUS_NVIC_IPR3_IP_14_BITS _u(0x00c00000) -#define M0PLUS_NVIC_IPR3_IP_14_MSB _u(23) -#define M0PLUS_NVIC_IPR3_IP_14_LSB _u(22) -#define M0PLUS_NVIC_IPR3_IP_14_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M0PLUS_NVIC_IPR3_IP_13 -// Description : Priority of interrupt 13 -#define M0PLUS_NVIC_IPR3_IP_13_RESET _u(0x0) -#define M0PLUS_NVIC_IPR3_IP_13_BITS _u(0x0000c000) -#define M0PLUS_NVIC_IPR3_IP_13_MSB _u(15) -#define M0PLUS_NVIC_IPR3_IP_13_LSB _u(14) -#define M0PLUS_NVIC_IPR3_IP_13_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M0PLUS_NVIC_IPR3_IP_12 -// Description : Priority of interrupt 12 -#define M0PLUS_NVIC_IPR3_IP_12_RESET _u(0x0) -#define M0PLUS_NVIC_IPR3_IP_12_BITS _u(0x000000c0) -#define M0PLUS_NVIC_IPR3_IP_12_MSB _u(7) -#define M0PLUS_NVIC_IPR3_IP_12_LSB _u(6) -#define M0PLUS_NVIC_IPR3_IP_12_ACCESS "RW" -// ============================================================================= -// Register : M0PLUS_NVIC_IPR4 -// Description : Use the Interrupt Priority Registers to assign a priority from -// 0 to 3 to each of the available interrupts. 0 is the highest -// priority, and 3 is the lowest. -#define M0PLUS_NVIC_IPR4_OFFSET _u(0x0000e410) -#define M0PLUS_NVIC_IPR4_BITS _u(0xc0c0c0c0) -#define M0PLUS_NVIC_IPR4_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M0PLUS_NVIC_IPR4_IP_19 -// Description : Priority of interrupt 19 -#define M0PLUS_NVIC_IPR4_IP_19_RESET _u(0x0) -#define M0PLUS_NVIC_IPR4_IP_19_BITS _u(0xc0000000) -#define M0PLUS_NVIC_IPR4_IP_19_MSB _u(31) -#define M0PLUS_NVIC_IPR4_IP_19_LSB _u(30) -#define M0PLUS_NVIC_IPR4_IP_19_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M0PLUS_NVIC_IPR4_IP_18 -// Description : Priority of interrupt 18 -#define M0PLUS_NVIC_IPR4_IP_18_RESET _u(0x0) -#define M0PLUS_NVIC_IPR4_IP_18_BITS _u(0x00c00000) -#define M0PLUS_NVIC_IPR4_IP_18_MSB _u(23) -#define M0PLUS_NVIC_IPR4_IP_18_LSB _u(22) -#define M0PLUS_NVIC_IPR4_IP_18_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M0PLUS_NVIC_IPR4_IP_17 -// Description : Priority of interrupt 17 -#define M0PLUS_NVIC_IPR4_IP_17_RESET _u(0x0) -#define M0PLUS_NVIC_IPR4_IP_17_BITS _u(0x0000c000) -#define M0PLUS_NVIC_IPR4_IP_17_MSB _u(15) -#define M0PLUS_NVIC_IPR4_IP_17_LSB _u(14) -#define M0PLUS_NVIC_IPR4_IP_17_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M0PLUS_NVIC_IPR4_IP_16 -// Description : Priority of interrupt 16 -#define M0PLUS_NVIC_IPR4_IP_16_RESET _u(0x0) -#define M0PLUS_NVIC_IPR4_IP_16_BITS _u(0x000000c0) -#define M0PLUS_NVIC_IPR4_IP_16_MSB _u(7) -#define M0PLUS_NVIC_IPR4_IP_16_LSB _u(6) -#define M0PLUS_NVIC_IPR4_IP_16_ACCESS "RW" -// ============================================================================= -// Register : M0PLUS_NVIC_IPR5 -// Description : Use the Interrupt Priority Registers to assign a priority from -// 0 to 3 to each of the available interrupts. 0 is the highest -// priority, and 3 is the lowest. -#define M0PLUS_NVIC_IPR5_OFFSET _u(0x0000e414) -#define M0PLUS_NVIC_IPR5_BITS _u(0xc0c0c0c0) -#define M0PLUS_NVIC_IPR5_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M0PLUS_NVIC_IPR5_IP_23 -// Description : Priority of interrupt 23 -#define M0PLUS_NVIC_IPR5_IP_23_RESET _u(0x0) -#define M0PLUS_NVIC_IPR5_IP_23_BITS _u(0xc0000000) -#define M0PLUS_NVIC_IPR5_IP_23_MSB _u(31) -#define M0PLUS_NVIC_IPR5_IP_23_LSB _u(30) -#define M0PLUS_NVIC_IPR5_IP_23_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M0PLUS_NVIC_IPR5_IP_22 -// Description : Priority of interrupt 22 -#define M0PLUS_NVIC_IPR5_IP_22_RESET _u(0x0) -#define M0PLUS_NVIC_IPR5_IP_22_BITS _u(0x00c00000) -#define M0PLUS_NVIC_IPR5_IP_22_MSB _u(23) -#define M0PLUS_NVIC_IPR5_IP_22_LSB _u(22) -#define M0PLUS_NVIC_IPR5_IP_22_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M0PLUS_NVIC_IPR5_IP_21 -// Description : Priority of interrupt 21 -#define M0PLUS_NVIC_IPR5_IP_21_RESET _u(0x0) -#define M0PLUS_NVIC_IPR5_IP_21_BITS _u(0x0000c000) -#define M0PLUS_NVIC_IPR5_IP_21_MSB _u(15) -#define M0PLUS_NVIC_IPR5_IP_21_LSB _u(14) -#define M0PLUS_NVIC_IPR5_IP_21_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M0PLUS_NVIC_IPR5_IP_20 -// Description : Priority of interrupt 20 -#define M0PLUS_NVIC_IPR5_IP_20_RESET _u(0x0) -#define M0PLUS_NVIC_IPR5_IP_20_BITS _u(0x000000c0) -#define M0PLUS_NVIC_IPR5_IP_20_MSB _u(7) -#define M0PLUS_NVIC_IPR5_IP_20_LSB _u(6) -#define M0PLUS_NVIC_IPR5_IP_20_ACCESS "RW" -// ============================================================================= -// Register : M0PLUS_NVIC_IPR6 -// Description : Use the Interrupt Priority Registers to assign a priority from -// 0 to 3 to each of the available interrupts. 0 is the highest -// priority, and 3 is the lowest. -#define M0PLUS_NVIC_IPR6_OFFSET _u(0x0000e418) -#define M0PLUS_NVIC_IPR6_BITS _u(0xc0c0c0c0) -#define M0PLUS_NVIC_IPR6_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M0PLUS_NVIC_IPR6_IP_27 -// Description : Priority of interrupt 27 -#define M0PLUS_NVIC_IPR6_IP_27_RESET _u(0x0) -#define M0PLUS_NVIC_IPR6_IP_27_BITS _u(0xc0000000) -#define M0PLUS_NVIC_IPR6_IP_27_MSB _u(31) -#define M0PLUS_NVIC_IPR6_IP_27_LSB _u(30) -#define M0PLUS_NVIC_IPR6_IP_27_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M0PLUS_NVIC_IPR6_IP_26 -// Description : Priority of interrupt 26 -#define M0PLUS_NVIC_IPR6_IP_26_RESET _u(0x0) -#define M0PLUS_NVIC_IPR6_IP_26_BITS _u(0x00c00000) -#define M0PLUS_NVIC_IPR6_IP_26_MSB _u(23) -#define M0PLUS_NVIC_IPR6_IP_26_LSB _u(22) -#define M0PLUS_NVIC_IPR6_IP_26_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M0PLUS_NVIC_IPR6_IP_25 -// Description : Priority of interrupt 25 -#define M0PLUS_NVIC_IPR6_IP_25_RESET _u(0x0) -#define M0PLUS_NVIC_IPR6_IP_25_BITS _u(0x0000c000) -#define M0PLUS_NVIC_IPR6_IP_25_MSB _u(15) -#define M0PLUS_NVIC_IPR6_IP_25_LSB _u(14) -#define M0PLUS_NVIC_IPR6_IP_25_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M0PLUS_NVIC_IPR6_IP_24 -// Description : Priority of interrupt 24 -#define M0PLUS_NVIC_IPR6_IP_24_RESET _u(0x0) -#define M0PLUS_NVIC_IPR6_IP_24_BITS _u(0x000000c0) -#define M0PLUS_NVIC_IPR6_IP_24_MSB _u(7) -#define M0PLUS_NVIC_IPR6_IP_24_LSB _u(6) -#define M0PLUS_NVIC_IPR6_IP_24_ACCESS "RW" -// ============================================================================= -// Register : M0PLUS_NVIC_IPR7 -// Description : Use the Interrupt Priority Registers to assign a priority from -// 0 to 3 to each of the available interrupts. 0 is the highest -// priority, and 3 is the lowest. -#define M0PLUS_NVIC_IPR7_OFFSET _u(0x0000e41c) -#define M0PLUS_NVIC_IPR7_BITS _u(0xc0c0c0c0) -#define M0PLUS_NVIC_IPR7_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M0PLUS_NVIC_IPR7_IP_31 -// Description : Priority of interrupt 31 -#define M0PLUS_NVIC_IPR7_IP_31_RESET _u(0x0) -#define M0PLUS_NVIC_IPR7_IP_31_BITS _u(0xc0000000) -#define M0PLUS_NVIC_IPR7_IP_31_MSB _u(31) -#define M0PLUS_NVIC_IPR7_IP_31_LSB _u(30) -#define M0PLUS_NVIC_IPR7_IP_31_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M0PLUS_NVIC_IPR7_IP_30 -// Description : Priority of interrupt 30 -#define M0PLUS_NVIC_IPR7_IP_30_RESET _u(0x0) -#define M0PLUS_NVIC_IPR7_IP_30_BITS _u(0x00c00000) -#define M0PLUS_NVIC_IPR7_IP_30_MSB _u(23) -#define M0PLUS_NVIC_IPR7_IP_30_LSB _u(22) -#define M0PLUS_NVIC_IPR7_IP_30_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M0PLUS_NVIC_IPR7_IP_29 -// Description : Priority of interrupt 29 -#define M0PLUS_NVIC_IPR7_IP_29_RESET _u(0x0) -#define M0PLUS_NVIC_IPR7_IP_29_BITS _u(0x0000c000) -#define M0PLUS_NVIC_IPR7_IP_29_MSB _u(15) -#define M0PLUS_NVIC_IPR7_IP_29_LSB _u(14) -#define M0PLUS_NVIC_IPR7_IP_29_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M0PLUS_NVIC_IPR7_IP_28 -// Description : Priority of interrupt 28 -#define M0PLUS_NVIC_IPR7_IP_28_RESET _u(0x0) -#define M0PLUS_NVIC_IPR7_IP_28_BITS _u(0x000000c0) -#define M0PLUS_NVIC_IPR7_IP_28_MSB _u(7) -#define M0PLUS_NVIC_IPR7_IP_28_LSB _u(6) -#define M0PLUS_NVIC_IPR7_IP_28_ACCESS "RW" -// ============================================================================= -// Register : M0PLUS_CPUID -// Description : Read the CPU ID Base Register to determine: the ID number of -// the processor core, the version number of the processor core, -// the implementation details of the processor core. -#define M0PLUS_CPUID_OFFSET _u(0x0000ed00) -#define M0PLUS_CPUID_BITS _u(0xffffffff) -#define M0PLUS_CPUID_RESET _u(0x410cc601) -// ----------------------------------------------------------------------------- -// Field : M0PLUS_CPUID_IMPLEMENTER -// Description : Implementor code: 0x41 = ARM -#define M0PLUS_CPUID_IMPLEMENTER_RESET _u(0x41) -#define M0PLUS_CPUID_IMPLEMENTER_BITS _u(0xff000000) -#define M0PLUS_CPUID_IMPLEMENTER_MSB _u(31) -#define M0PLUS_CPUID_IMPLEMENTER_LSB _u(24) -#define M0PLUS_CPUID_IMPLEMENTER_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M0PLUS_CPUID_VARIANT -// Description : Major revision number n in the rnpm revision status: -// 0x0 = Revision 0. -#define M0PLUS_CPUID_VARIANT_RESET _u(0x0) -#define M0PLUS_CPUID_VARIANT_BITS _u(0x00f00000) -#define M0PLUS_CPUID_VARIANT_MSB _u(23) -#define M0PLUS_CPUID_VARIANT_LSB _u(20) -#define M0PLUS_CPUID_VARIANT_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M0PLUS_CPUID_ARCHITECTURE -// Description : Constant that defines the architecture of the processor: -// 0xC = ARMv6-M architecture. -#define M0PLUS_CPUID_ARCHITECTURE_RESET _u(0xc) -#define M0PLUS_CPUID_ARCHITECTURE_BITS _u(0x000f0000) -#define M0PLUS_CPUID_ARCHITECTURE_MSB _u(19) -#define M0PLUS_CPUID_ARCHITECTURE_LSB _u(16) -#define M0PLUS_CPUID_ARCHITECTURE_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M0PLUS_CPUID_PARTNO -// Description : Number of processor within family: 0xC60 = Cortex-M0+ -#define M0PLUS_CPUID_PARTNO_RESET _u(0xc60) -#define M0PLUS_CPUID_PARTNO_BITS _u(0x0000fff0) -#define M0PLUS_CPUID_PARTNO_MSB _u(15) -#define M0PLUS_CPUID_PARTNO_LSB _u(4) -#define M0PLUS_CPUID_PARTNO_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M0PLUS_CPUID_REVISION -// Description : Minor revision number m in the rnpm revision status: -// 0x1 = Patch 1. -#define M0PLUS_CPUID_REVISION_RESET _u(0x1) -#define M0PLUS_CPUID_REVISION_BITS _u(0x0000000f) -#define M0PLUS_CPUID_REVISION_MSB _u(3) -#define M0PLUS_CPUID_REVISION_LSB _u(0) -#define M0PLUS_CPUID_REVISION_ACCESS "RO" -// ============================================================================= -// Register : M0PLUS_ICSR -// Description : Use the Interrupt Control State Register to set a pending Non- -// Maskable Interrupt (NMI), set or clear a pending PendSV, set or -// clear a pending SysTick, check for pending exceptions, check -// the vector number of the highest priority pended exception, -// check the vector number of the active exception. -#define M0PLUS_ICSR_OFFSET _u(0x0000ed04) -#define M0PLUS_ICSR_BITS _u(0x9edff1ff) -#define M0PLUS_ICSR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M0PLUS_ICSR_NMIPENDSET -// Description : Setting this bit will activate an NMI. Since NMI is the highest -// priority exception, it will activate as soon as it is -// registered. -// NMI set-pending bit. -// Write: -// 0 = No effect. -// 1 = Changes NMI exception state to pending. -// Read: -// 0 = NMI exception is not pending. -// 1 = NMI exception is pending. -// Because NMI is the highest-priority exception, normally the -// processor enters the NMI -// exception handler as soon as it detects a write of 1 to this -// bit. Entering the handler then clears -// this bit to 0. This means a read of this bit by the NMI -// exception handler returns 1 only if the -// NMI signal is reasserted while the processor is executing that -// handler. -#define M0PLUS_ICSR_NMIPENDSET_RESET _u(0x0) -#define M0PLUS_ICSR_NMIPENDSET_BITS _u(0x80000000) -#define M0PLUS_ICSR_NMIPENDSET_MSB _u(31) -#define M0PLUS_ICSR_NMIPENDSET_LSB _u(31) -#define M0PLUS_ICSR_NMIPENDSET_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M0PLUS_ICSR_PENDSVSET -// Description : PendSV set-pending bit. -// Write: -// 0 = No effect. -// 1 = Changes PendSV exception state to pending. -// Read: -// 0 = PendSV exception is not pending. -// 1 = PendSV exception is pending. -// Writing 1 to this bit is the only way to set the PendSV -// exception state to pending. -#define M0PLUS_ICSR_PENDSVSET_RESET _u(0x0) -#define M0PLUS_ICSR_PENDSVSET_BITS _u(0x10000000) -#define M0PLUS_ICSR_PENDSVSET_MSB _u(28) -#define M0PLUS_ICSR_PENDSVSET_LSB _u(28) -#define M0PLUS_ICSR_PENDSVSET_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M0PLUS_ICSR_PENDSVCLR -// Description : PendSV clear-pending bit. -// Write: -// 0 = No effect. -// 1 = Removes the pending state from the PendSV exception. -#define M0PLUS_ICSR_PENDSVCLR_RESET _u(0x0) -#define M0PLUS_ICSR_PENDSVCLR_BITS _u(0x08000000) -#define M0PLUS_ICSR_PENDSVCLR_MSB _u(27) -#define M0PLUS_ICSR_PENDSVCLR_LSB _u(27) -#define M0PLUS_ICSR_PENDSVCLR_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M0PLUS_ICSR_PENDSTSET -// Description : SysTick exception set-pending bit. -// Write: -// 0 = No effect. -// 1 = Changes SysTick exception state to pending. -// Read: -// 0 = SysTick exception is not pending. -// 1 = SysTick exception is pending. -#define M0PLUS_ICSR_PENDSTSET_RESET _u(0x0) -#define M0PLUS_ICSR_PENDSTSET_BITS _u(0x04000000) -#define M0PLUS_ICSR_PENDSTSET_MSB _u(26) -#define M0PLUS_ICSR_PENDSTSET_LSB _u(26) -#define M0PLUS_ICSR_PENDSTSET_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M0PLUS_ICSR_PENDSTCLR -// Description : SysTick exception clear-pending bit. -// Write: -// 0 = No effect. -// 1 = Removes the pending state from the SysTick exception. -// This bit is WO. On a register read its value is Unknown. -#define M0PLUS_ICSR_PENDSTCLR_RESET _u(0x0) -#define M0PLUS_ICSR_PENDSTCLR_BITS _u(0x02000000) -#define M0PLUS_ICSR_PENDSTCLR_MSB _u(25) -#define M0PLUS_ICSR_PENDSTCLR_LSB _u(25) -#define M0PLUS_ICSR_PENDSTCLR_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M0PLUS_ICSR_ISRPREEMPT -// Description : The system can only access this bit when the core is halted. It -// indicates that a pending interrupt is to be taken in the next -// running cycle. If C_MASKINTS is clear in the Debug Halting -// Control and Status Register, the interrupt is serviced. -#define M0PLUS_ICSR_ISRPREEMPT_RESET _u(0x0) -#define M0PLUS_ICSR_ISRPREEMPT_BITS _u(0x00800000) -#define M0PLUS_ICSR_ISRPREEMPT_MSB _u(23) -#define M0PLUS_ICSR_ISRPREEMPT_LSB _u(23) -#define M0PLUS_ICSR_ISRPREEMPT_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M0PLUS_ICSR_ISRPENDING -// Description : External interrupt pending flag -#define M0PLUS_ICSR_ISRPENDING_RESET _u(0x0) -#define M0PLUS_ICSR_ISRPENDING_BITS _u(0x00400000) -#define M0PLUS_ICSR_ISRPENDING_MSB _u(22) -#define M0PLUS_ICSR_ISRPENDING_LSB _u(22) -#define M0PLUS_ICSR_ISRPENDING_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M0PLUS_ICSR_VECTPENDING -// Description : Indicates the exception number for the highest priority pending -// exception: 0 = no pending exceptions. Non zero = The pending -// state includes the effect of memory-mapped enable and mask -// registers. It does not include the PRIMASK special-purpose -// register qualifier. -#define M0PLUS_ICSR_VECTPENDING_RESET _u(0x000) -#define M0PLUS_ICSR_VECTPENDING_BITS _u(0x001ff000) -#define M0PLUS_ICSR_VECTPENDING_MSB _u(20) -#define M0PLUS_ICSR_VECTPENDING_LSB _u(12) -#define M0PLUS_ICSR_VECTPENDING_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M0PLUS_ICSR_VECTACTIVE -// Description : Active exception number field. Reset clears the VECTACTIVE -// field. -#define M0PLUS_ICSR_VECTACTIVE_RESET _u(0x000) -#define M0PLUS_ICSR_VECTACTIVE_BITS _u(0x000001ff) -#define M0PLUS_ICSR_VECTACTIVE_MSB _u(8) -#define M0PLUS_ICSR_VECTACTIVE_LSB _u(0) -#define M0PLUS_ICSR_VECTACTIVE_ACCESS "RO" -// ============================================================================= -// Register : M0PLUS_VTOR -// Description : The VTOR holds the vector table offset address. -#define M0PLUS_VTOR_OFFSET _u(0x0000ed08) -#define M0PLUS_VTOR_BITS _u(0xffffff00) -#define M0PLUS_VTOR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M0PLUS_VTOR_TBLOFF -// Description : Bits [31:8] of the indicate the vector table offset address. -#define M0PLUS_VTOR_TBLOFF_RESET _u(0x000000) -#define M0PLUS_VTOR_TBLOFF_BITS _u(0xffffff00) -#define M0PLUS_VTOR_TBLOFF_MSB _u(31) -#define M0PLUS_VTOR_TBLOFF_LSB _u(8) -#define M0PLUS_VTOR_TBLOFF_ACCESS "RW" -// ============================================================================= -// Register : M0PLUS_AIRCR -// Description : Use the Application Interrupt and Reset Control Register to: -// determine data endianness, clear all active state information -// from debug halt mode, request a system reset. -#define M0PLUS_AIRCR_OFFSET _u(0x0000ed0c) -#define M0PLUS_AIRCR_BITS _u(0xffff8006) -#define M0PLUS_AIRCR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M0PLUS_AIRCR_VECTKEY -// Description : Register key: -// Reads as Unknown -// On writes, write 0x05FA to VECTKEY, otherwise the write is -// ignored. -#define M0PLUS_AIRCR_VECTKEY_RESET _u(0x0000) -#define M0PLUS_AIRCR_VECTKEY_BITS _u(0xffff0000) -#define M0PLUS_AIRCR_VECTKEY_MSB _u(31) -#define M0PLUS_AIRCR_VECTKEY_LSB _u(16) -#define M0PLUS_AIRCR_VECTKEY_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M0PLUS_AIRCR_ENDIANESS -// Description : Data endianness implemented: -// 0 = Little-endian. -#define M0PLUS_AIRCR_ENDIANESS_RESET _u(0x0) -#define M0PLUS_AIRCR_ENDIANESS_BITS _u(0x00008000) -#define M0PLUS_AIRCR_ENDIANESS_MSB _u(15) -#define M0PLUS_AIRCR_ENDIANESS_LSB _u(15) -#define M0PLUS_AIRCR_ENDIANESS_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M0PLUS_AIRCR_SYSRESETREQ -// Description : Writing 1 to this bit causes the SYSRESETREQ signal to the -// outer system to be asserted to request a reset. The intention -// is to force a large system reset of all major components except -// for debug. The C_HALT bit in the DHCSR is cleared as a result -// of the system reset requested. The debugger does not lose -// contact with the device. -#define M0PLUS_AIRCR_SYSRESETREQ_RESET _u(0x0) -#define M0PLUS_AIRCR_SYSRESETREQ_BITS _u(0x00000004) -#define M0PLUS_AIRCR_SYSRESETREQ_MSB _u(2) -#define M0PLUS_AIRCR_SYSRESETREQ_LSB _u(2) -#define M0PLUS_AIRCR_SYSRESETREQ_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M0PLUS_AIRCR_VECTCLRACTIVE -// Description : Clears all active state information for fixed and configurable -// exceptions. This bit: is self-clearing, can only be set by the -// DAP when the core is halted. When set: clears all active -// exception status of the processor, forces a return to Thread -// mode, forces an IPSR of 0. A debugger must re-initialize the -// stack. -#define M0PLUS_AIRCR_VECTCLRACTIVE_RESET _u(0x0) -#define M0PLUS_AIRCR_VECTCLRACTIVE_BITS _u(0x00000002) -#define M0PLUS_AIRCR_VECTCLRACTIVE_MSB _u(1) -#define M0PLUS_AIRCR_VECTCLRACTIVE_LSB _u(1) -#define M0PLUS_AIRCR_VECTCLRACTIVE_ACCESS "RW" -// ============================================================================= -// Register : M0PLUS_SCR -// Description : System Control Register. Use the System Control Register for -// power-management functions: signal to the system when the -// processor can enter a low power state, control how the -// processor enters and exits low power states. -#define M0PLUS_SCR_OFFSET _u(0x0000ed10) -#define M0PLUS_SCR_BITS _u(0x00000016) -#define M0PLUS_SCR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M0PLUS_SCR_SEVONPEND -// Description : Send Event on Pending bit: -// 0 = Only enabled interrupts or events can wakeup the processor, -// disabled interrupts are excluded. -// 1 = Enabled events and all interrupts, including disabled -// interrupts, can wakeup the processor. -// When an event or interrupt becomes pending, the event signal -// wakes up the processor from WFE. If the -// processor is not waiting for an event, the event is registered -// and affects the next WFE. -// The processor also wakes up on execution of an SEV instruction -// or an external event. -#define M0PLUS_SCR_SEVONPEND_RESET _u(0x0) -#define M0PLUS_SCR_SEVONPEND_BITS _u(0x00000010) -#define M0PLUS_SCR_SEVONPEND_MSB _u(4) -#define M0PLUS_SCR_SEVONPEND_LSB _u(4) -#define M0PLUS_SCR_SEVONPEND_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M0PLUS_SCR_SLEEPDEEP -// Description : Controls whether the processor uses sleep or deep sleep as its -// low power mode: -// 0 = Sleep. -// 1 = Deep sleep. -#define M0PLUS_SCR_SLEEPDEEP_RESET _u(0x0) -#define M0PLUS_SCR_SLEEPDEEP_BITS _u(0x00000004) -#define M0PLUS_SCR_SLEEPDEEP_MSB _u(2) -#define M0PLUS_SCR_SLEEPDEEP_LSB _u(2) -#define M0PLUS_SCR_SLEEPDEEP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M0PLUS_SCR_SLEEPONEXIT -// Description : Indicates sleep-on-exit when returning from Handler mode to -// Thread mode: -// 0 = Do not sleep when returning to Thread mode. -// 1 = Enter sleep, or deep sleep, on return from an ISR to Thread -// mode. -// Setting this bit to 1 enables an interrupt driven application -// to avoid returning to an empty main application. -#define M0PLUS_SCR_SLEEPONEXIT_RESET _u(0x0) -#define M0PLUS_SCR_SLEEPONEXIT_BITS _u(0x00000002) -#define M0PLUS_SCR_SLEEPONEXIT_MSB _u(1) -#define M0PLUS_SCR_SLEEPONEXIT_LSB _u(1) -#define M0PLUS_SCR_SLEEPONEXIT_ACCESS "RW" -// ============================================================================= -// Register : M0PLUS_CCR -// Description : The Configuration and Control Register permanently enables -// stack alignment and causes unaligned accesses to result in a -// Hard Fault. -#define M0PLUS_CCR_OFFSET _u(0x0000ed14) -#define M0PLUS_CCR_BITS _u(0x00000208) -#define M0PLUS_CCR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M0PLUS_CCR_STKALIGN -// Description : Always reads as one, indicates 8-byte stack alignment on -// exception entry. On exception entry, the processor uses bit[9] -// of the stacked PSR to indicate the stack alignment. On return -// from the exception it uses this stacked bit to restore the -// correct stack alignment. -#define M0PLUS_CCR_STKALIGN_RESET _u(0x0) -#define M0PLUS_CCR_STKALIGN_BITS _u(0x00000200) -#define M0PLUS_CCR_STKALIGN_MSB _u(9) -#define M0PLUS_CCR_STKALIGN_LSB _u(9) -#define M0PLUS_CCR_STKALIGN_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M0PLUS_CCR_UNALIGN_TRP -// Description : Always reads as one, indicates that all unaligned accesses -// generate a HardFault. -#define M0PLUS_CCR_UNALIGN_TRP_RESET _u(0x0) -#define M0PLUS_CCR_UNALIGN_TRP_BITS _u(0x00000008) -#define M0PLUS_CCR_UNALIGN_TRP_MSB _u(3) -#define M0PLUS_CCR_UNALIGN_TRP_LSB _u(3) -#define M0PLUS_CCR_UNALIGN_TRP_ACCESS "RO" -// ============================================================================= -// Register : M0PLUS_SHPR2 -// Description : System handlers are a special class of exception handler that -// can have their priority set to any of the priority levels. Use -// the System Handler Priority Register 2 to set the priority of -// SVCall. -#define M0PLUS_SHPR2_OFFSET _u(0x0000ed1c) -#define M0PLUS_SHPR2_BITS _u(0xc0000000) -#define M0PLUS_SHPR2_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M0PLUS_SHPR2_PRI_11 -// Description : Priority of system handler 11, SVCall -#define M0PLUS_SHPR2_PRI_11_RESET _u(0x0) -#define M0PLUS_SHPR2_PRI_11_BITS _u(0xc0000000) -#define M0PLUS_SHPR2_PRI_11_MSB _u(31) -#define M0PLUS_SHPR2_PRI_11_LSB _u(30) -#define M0PLUS_SHPR2_PRI_11_ACCESS "RW" -// ============================================================================= -// Register : M0PLUS_SHPR3 -// Description : System handlers are a special class of exception handler that -// can have their priority set to any of the priority levels. Use -// the System Handler Priority Register 3 to set the priority of -// PendSV and SysTick. -#define M0PLUS_SHPR3_OFFSET _u(0x0000ed20) -#define M0PLUS_SHPR3_BITS _u(0xc0c00000) -#define M0PLUS_SHPR3_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M0PLUS_SHPR3_PRI_15 -// Description : Priority of system handler 15, SysTick -#define M0PLUS_SHPR3_PRI_15_RESET _u(0x0) -#define M0PLUS_SHPR3_PRI_15_BITS _u(0xc0000000) -#define M0PLUS_SHPR3_PRI_15_MSB _u(31) -#define M0PLUS_SHPR3_PRI_15_LSB _u(30) -#define M0PLUS_SHPR3_PRI_15_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M0PLUS_SHPR3_PRI_14 -// Description : Priority of system handler 14, PendSV -#define M0PLUS_SHPR3_PRI_14_RESET _u(0x0) -#define M0PLUS_SHPR3_PRI_14_BITS _u(0x00c00000) -#define M0PLUS_SHPR3_PRI_14_MSB _u(23) -#define M0PLUS_SHPR3_PRI_14_LSB _u(22) -#define M0PLUS_SHPR3_PRI_14_ACCESS "RW" -// ============================================================================= -// Register : M0PLUS_SHCSR -// Description : Use the System Handler Control and State Register to determine -// or clear the pending status of SVCall. -#define M0PLUS_SHCSR_OFFSET _u(0x0000ed24) -#define M0PLUS_SHCSR_BITS _u(0x00008000) -#define M0PLUS_SHCSR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M0PLUS_SHCSR_SVCALLPENDED -// Description : Reads as 1 if SVCall is Pending. Write 1 to set pending -// SVCall, write 0 to clear pending SVCall. -#define M0PLUS_SHCSR_SVCALLPENDED_RESET _u(0x0) -#define M0PLUS_SHCSR_SVCALLPENDED_BITS _u(0x00008000) -#define M0PLUS_SHCSR_SVCALLPENDED_MSB _u(15) -#define M0PLUS_SHCSR_SVCALLPENDED_LSB _u(15) -#define M0PLUS_SHCSR_SVCALLPENDED_ACCESS "RW" -// ============================================================================= -// Register : M0PLUS_MPU_TYPE -// Description : Read the MPU Type Register to determine if the processor -// implements an MPU, and how many regions the MPU supports. -#define M0PLUS_MPU_TYPE_OFFSET _u(0x0000ed90) -#define M0PLUS_MPU_TYPE_BITS _u(0x00ffff01) -#define M0PLUS_MPU_TYPE_RESET _u(0x00000800) -// ----------------------------------------------------------------------------- -// Field : M0PLUS_MPU_TYPE_IREGION -// Description : Instruction region. Reads as zero as ARMv6-M only supports a -// unified MPU. -#define M0PLUS_MPU_TYPE_IREGION_RESET _u(0x00) -#define M0PLUS_MPU_TYPE_IREGION_BITS _u(0x00ff0000) -#define M0PLUS_MPU_TYPE_IREGION_MSB _u(23) -#define M0PLUS_MPU_TYPE_IREGION_LSB _u(16) -#define M0PLUS_MPU_TYPE_IREGION_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M0PLUS_MPU_TYPE_DREGION -// Description : Number of regions supported by the MPU. -#define M0PLUS_MPU_TYPE_DREGION_RESET _u(0x08) -#define M0PLUS_MPU_TYPE_DREGION_BITS _u(0x0000ff00) -#define M0PLUS_MPU_TYPE_DREGION_MSB _u(15) -#define M0PLUS_MPU_TYPE_DREGION_LSB _u(8) -#define M0PLUS_MPU_TYPE_DREGION_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M0PLUS_MPU_TYPE_SEPARATE -// Description : Indicates support for separate instruction and data address -// maps. Reads as 0 as ARMv6-M only supports a unified MPU. -#define M0PLUS_MPU_TYPE_SEPARATE_RESET _u(0x0) -#define M0PLUS_MPU_TYPE_SEPARATE_BITS _u(0x00000001) -#define M0PLUS_MPU_TYPE_SEPARATE_MSB _u(0) -#define M0PLUS_MPU_TYPE_SEPARATE_LSB _u(0) -#define M0PLUS_MPU_TYPE_SEPARATE_ACCESS "RO" -// ============================================================================= -// Register : M0PLUS_MPU_CTRL -// Description : Use the MPU Control Register to enable and disable the MPU, and -// to control whether the default memory map is enabled as a -// background region for privileged accesses, and whether the MPU -// is enabled for HardFaults and NMIs. -#define M0PLUS_MPU_CTRL_OFFSET _u(0x0000ed94) -#define M0PLUS_MPU_CTRL_BITS _u(0x00000007) -#define M0PLUS_MPU_CTRL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M0PLUS_MPU_CTRL_PRIVDEFENA -// Description : Controls whether the default memory map is enabled as a -// background region for privileged accesses. This bit is ignored -// when ENABLE is clear. -// 0 = If the MPU is enabled, disables use of the default memory -// map. Any memory access to a location not -// covered by any enabled region causes a fault. -// 1 = If the MPU is enabled, enables use of the default memory -// map as a background region for privileged software accesses. -// When enabled, the background region acts as if it is region -// number -1. Any region that is defined and enabled has priority -// over this default map. -#define M0PLUS_MPU_CTRL_PRIVDEFENA_RESET _u(0x0) -#define M0PLUS_MPU_CTRL_PRIVDEFENA_BITS _u(0x00000004) -#define M0PLUS_MPU_CTRL_PRIVDEFENA_MSB _u(2) -#define M0PLUS_MPU_CTRL_PRIVDEFENA_LSB _u(2) -#define M0PLUS_MPU_CTRL_PRIVDEFENA_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M0PLUS_MPU_CTRL_HFNMIENA -// Description : Controls the use of the MPU for HardFaults and NMIs. Setting -// this bit when ENABLE is clear results in UNPREDICTABLE -// behaviour. -// When the MPU is enabled: -// 0 = MPU is disabled during HardFault and NMI handlers, -// regardless of the value of the ENABLE bit. -// 1 = the MPU is enabled during HardFault and NMI handlers. -#define M0PLUS_MPU_CTRL_HFNMIENA_RESET _u(0x0) -#define M0PLUS_MPU_CTRL_HFNMIENA_BITS _u(0x00000002) -#define M0PLUS_MPU_CTRL_HFNMIENA_MSB _u(1) -#define M0PLUS_MPU_CTRL_HFNMIENA_LSB _u(1) -#define M0PLUS_MPU_CTRL_HFNMIENA_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M0PLUS_MPU_CTRL_ENABLE -// Description : Enables the MPU. If the MPU is disabled, privileged and -// unprivileged accesses use the default memory map. -// 0 = MPU disabled. -// 1 = MPU enabled. -#define M0PLUS_MPU_CTRL_ENABLE_RESET _u(0x0) -#define M0PLUS_MPU_CTRL_ENABLE_BITS _u(0x00000001) -#define M0PLUS_MPU_CTRL_ENABLE_MSB _u(0) -#define M0PLUS_MPU_CTRL_ENABLE_LSB _u(0) -#define M0PLUS_MPU_CTRL_ENABLE_ACCESS "RW" -// ============================================================================= -// Register : M0PLUS_MPU_RNR -// Description : Use the MPU Region Number Register to select the region -// currently accessed by MPU_RBAR and MPU_RASR. -#define M0PLUS_MPU_RNR_OFFSET _u(0x0000ed98) -#define M0PLUS_MPU_RNR_BITS _u(0x0000000f) -#define M0PLUS_MPU_RNR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M0PLUS_MPU_RNR_REGION -// Description : Indicates the MPU region referenced by the MPU_RBAR and -// MPU_RASR registers. -// The MPU supports 8 memory regions, so the permitted values of -// this field are 0-7. -#define M0PLUS_MPU_RNR_REGION_RESET _u(0x0) -#define M0PLUS_MPU_RNR_REGION_BITS _u(0x0000000f) -#define M0PLUS_MPU_RNR_REGION_MSB _u(3) -#define M0PLUS_MPU_RNR_REGION_LSB _u(0) -#define M0PLUS_MPU_RNR_REGION_ACCESS "RW" -// ============================================================================= -// Register : M0PLUS_MPU_RBAR -// Description : Read the MPU Region Base Address Register to determine the base -// address of the region identified by MPU_RNR. Write to update -// the base address of said region or that of a specified region, -// with whose number MPU_RNR will also be updated. -#define M0PLUS_MPU_RBAR_OFFSET _u(0x0000ed9c) -#define M0PLUS_MPU_RBAR_BITS _u(0xffffff1f) -#define M0PLUS_MPU_RBAR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M0PLUS_MPU_RBAR_ADDR -// Description : Base address of the region. -#define M0PLUS_MPU_RBAR_ADDR_RESET _u(0x000000) -#define M0PLUS_MPU_RBAR_ADDR_BITS _u(0xffffff00) -#define M0PLUS_MPU_RBAR_ADDR_MSB _u(31) -#define M0PLUS_MPU_RBAR_ADDR_LSB _u(8) -#define M0PLUS_MPU_RBAR_ADDR_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M0PLUS_MPU_RBAR_VALID -// Description : On writes, indicates whether the write must update the base -// address of the region identified by the REGION field, updating -// the MPU_RNR to indicate this new region. -// Write: -// 0 = MPU_RNR not changed, and the processor: -// Updates the base address for the region specified in the -// MPU_RNR. -// Ignores the value of the REGION field. -// 1 = The processor: -// Updates the value of the MPU_RNR to the value of the REGION -// field. -// Updates the base address for the region specified in the REGION -// field. -// Always reads as zero. -#define M0PLUS_MPU_RBAR_VALID_RESET _u(0x0) -#define M0PLUS_MPU_RBAR_VALID_BITS _u(0x00000010) -#define M0PLUS_MPU_RBAR_VALID_MSB _u(4) -#define M0PLUS_MPU_RBAR_VALID_LSB _u(4) -#define M0PLUS_MPU_RBAR_VALID_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M0PLUS_MPU_RBAR_REGION -// Description : On writes, specifies the number of the region whose base -// address to update provided VALID is set written as 1. On reads, -// returns bits [3:0] of MPU_RNR. -#define M0PLUS_MPU_RBAR_REGION_RESET _u(0x0) -#define M0PLUS_MPU_RBAR_REGION_BITS _u(0x0000000f) -#define M0PLUS_MPU_RBAR_REGION_MSB _u(3) -#define M0PLUS_MPU_RBAR_REGION_LSB _u(0) -#define M0PLUS_MPU_RBAR_REGION_ACCESS "RW" -// ============================================================================= -// Register : M0PLUS_MPU_RASR -// Description : Use the MPU Region Attribute and Size Register to define the -// size, access behaviour and memory type of the region identified -// by MPU_RNR, and enable that region. -#define M0PLUS_MPU_RASR_OFFSET _u(0x0000eda0) -#define M0PLUS_MPU_RASR_BITS _u(0xffffff3f) -#define M0PLUS_MPU_RASR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M0PLUS_MPU_RASR_ATTRS -// Description : The MPU Region Attribute field. Use to define the region -// attribute control. -// 28 = XN: Instruction access disable bit: -// 0 = Instruction fetches enabled. -// 1 = Instruction fetches disabled. -// 26:24 = AP: Access permission field -// 18 = S: Shareable bit -// 17 = C: Cacheable bit -// 16 = B: Bufferable bit -#define M0PLUS_MPU_RASR_ATTRS_RESET _u(0x0000) -#define M0PLUS_MPU_RASR_ATTRS_BITS _u(0xffff0000) -#define M0PLUS_MPU_RASR_ATTRS_MSB _u(31) -#define M0PLUS_MPU_RASR_ATTRS_LSB _u(16) -#define M0PLUS_MPU_RASR_ATTRS_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M0PLUS_MPU_RASR_SRD -// Description : Subregion Disable. For regions of 256 bytes or larger, each bit -// of this field controls whether one of the eight equal -// subregions is enabled. -#define M0PLUS_MPU_RASR_SRD_RESET _u(0x00) -#define M0PLUS_MPU_RASR_SRD_BITS _u(0x0000ff00) -#define M0PLUS_MPU_RASR_SRD_MSB _u(15) -#define M0PLUS_MPU_RASR_SRD_LSB _u(8) -#define M0PLUS_MPU_RASR_SRD_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M0PLUS_MPU_RASR_SIZE -// Description : Indicates the region size. Region size in bytes = 2^(SIZE+1). -// The minimum permitted value is 7 (b00111) = 256Bytes -#define M0PLUS_MPU_RASR_SIZE_RESET _u(0x00) -#define M0PLUS_MPU_RASR_SIZE_BITS _u(0x0000003e) -#define M0PLUS_MPU_RASR_SIZE_MSB _u(5) -#define M0PLUS_MPU_RASR_SIZE_LSB _u(1) -#define M0PLUS_MPU_RASR_SIZE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M0PLUS_MPU_RASR_ENABLE -// Description : Enables the region. -#define M0PLUS_MPU_RASR_ENABLE_RESET _u(0x0) -#define M0PLUS_MPU_RASR_ENABLE_BITS _u(0x00000001) -#define M0PLUS_MPU_RASR_ENABLE_MSB _u(0) -#define M0PLUS_MPU_RASR_ENABLE_LSB _u(0) -#define M0PLUS_MPU_RASR_ENABLE_ACCESS "RW" -// ============================================================================= -#endif // _HARDWARE_REGS_M0PLUS_H - diff --git a/lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/pads_bank0.h b/lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/pads_bank0.h deleted file mode 100644 index 04c5e39712..0000000000 --- a/lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/pads_bank0.h +++ /dev/null @@ -1,2302 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -// ============================================================================= -// Register block : PADS_BANK0 -// Version : 1 -// Bus type : apb -// ============================================================================= -#ifndef _HARDWARE_REGS_PADS_BANK0_H -#define _HARDWARE_REGS_PADS_BANK0_H -// ============================================================================= -// Register : PADS_BANK0_VOLTAGE_SELECT -// Description : Voltage select. Per bank control -// 0x0 -> Set voltage to 3.3V (DVDD >= 2V5) -// 0x1 -> Set voltage to 1.8V (DVDD <= 1V8) -#define PADS_BANK0_VOLTAGE_SELECT_OFFSET _u(0x00000000) -#define PADS_BANK0_VOLTAGE_SELECT_BITS _u(0x00000001) -#define PADS_BANK0_VOLTAGE_SELECT_RESET _u(0x00000000) -#define PADS_BANK0_VOLTAGE_SELECT_MSB _u(0) -#define PADS_BANK0_VOLTAGE_SELECT_LSB _u(0) -#define PADS_BANK0_VOLTAGE_SELECT_ACCESS "RW" -#define PADS_BANK0_VOLTAGE_SELECT_VALUE_3V3 _u(0x0) -#define PADS_BANK0_VOLTAGE_SELECT_VALUE_1V8 _u(0x1) -// ============================================================================= -// Register : PADS_BANK0_GPIO0 -// Description : Pad control register -#define PADS_BANK0_GPIO0_OFFSET _u(0x00000004) -#define PADS_BANK0_GPIO0_BITS _u(0x000000ff) -#define PADS_BANK0_GPIO0_RESET _u(0x00000056) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO0_OD -// Description : Output disable. Has priority over output enable from -// peripherals -#define PADS_BANK0_GPIO0_OD_RESET _u(0x0) -#define PADS_BANK0_GPIO0_OD_BITS _u(0x00000080) -#define PADS_BANK0_GPIO0_OD_MSB _u(7) -#define PADS_BANK0_GPIO0_OD_LSB _u(7) -#define PADS_BANK0_GPIO0_OD_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO0_IE -// Description : Input enable -#define PADS_BANK0_GPIO0_IE_RESET _u(0x1) -#define PADS_BANK0_GPIO0_IE_BITS _u(0x00000040) -#define PADS_BANK0_GPIO0_IE_MSB _u(6) -#define PADS_BANK0_GPIO0_IE_LSB _u(6) -#define PADS_BANK0_GPIO0_IE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO0_DRIVE -// Description : Drive strength. -// 0x0 -> 2mA -// 0x1 -> 4mA -// 0x2 -> 8mA -// 0x3 -> 12mA -#define PADS_BANK0_GPIO0_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO0_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO0_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO0_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO0_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO0_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO0_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO0_DRIVE_VALUE_8MA _u(0x2) -#define PADS_BANK0_GPIO0_DRIVE_VALUE_12MA _u(0x3) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO0_PUE -// Description : Pull up enable -#define PADS_BANK0_GPIO0_PUE_RESET _u(0x0) -#define PADS_BANK0_GPIO0_PUE_BITS _u(0x00000008) -#define PADS_BANK0_GPIO0_PUE_MSB _u(3) -#define PADS_BANK0_GPIO0_PUE_LSB _u(3) -#define PADS_BANK0_GPIO0_PUE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO0_PDE -// Description : Pull down enable -#define PADS_BANK0_GPIO0_PDE_RESET _u(0x1) -#define PADS_BANK0_GPIO0_PDE_BITS _u(0x00000004) -#define PADS_BANK0_GPIO0_PDE_MSB _u(2) -#define PADS_BANK0_GPIO0_PDE_LSB _u(2) -#define PADS_BANK0_GPIO0_PDE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO0_SCHMITT -// Description : Enable schmitt trigger -#define PADS_BANK0_GPIO0_SCHMITT_RESET _u(0x1) -#define PADS_BANK0_GPIO0_SCHMITT_BITS _u(0x00000002) -#define PADS_BANK0_GPIO0_SCHMITT_MSB _u(1) -#define PADS_BANK0_GPIO0_SCHMITT_LSB _u(1) -#define PADS_BANK0_GPIO0_SCHMITT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO0_SLEWFAST -// Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO0_SLEWFAST_RESET _u(0x0) -#define PADS_BANK0_GPIO0_SLEWFAST_BITS _u(0x00000001) -#define PADS_BANK0_GPIO0_SLEWFAST_MSB _u(0) -#define PADS_BANK0_GPIO0_SLEWFAST_LSB _u(0) -#define PADS_BANK0_GPIO0_SLEWFAST_ACCESS "RW" -// ============================================================================= -// Register : PADS_BANK0_GPIO1 -// Description : Pad control register -#define PADS_BANK0_GPIO1_OFFSET _u(0x00000008) -#define PADS_BANK0_GPIO1_BITS _u(0x000000ff) -#define PADS_BANK0_GPIO1_RESET _u(0x00000056) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO1_OD -// Description : Output disable. Has priority over output enable from -// peripherals -#define PADS_BANK0_GPIO1_OD_RESET _u(0x0) -#define PADS_BANK0_GPIO1_OD_BITS _u(0x00000080) -#define PADS_BANK0_GPIO1_OD_MSB _u(7) -#define PADS_BANK0_GPIO1_OD_LSB _u(7) -#define PADS_BANK0_GPIO1_OD_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO1_IE -// Description : Input enable -#define PADS_BANK0_GPIO1_IE_RESET _u(0x1) -#define PADS_BANK0_GPIO1_IE_BITS _u(0x00000040) -#define PADS_BANK0_GPIO1_IE_MSB _u(6) -#define PADS_BANK0_GPIO1_IE_LSB _u(6) -#define PADS_BANK0_GPIO1_IE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO1_DRIVE -// Description : Drive strength. -// 0x0 -> 2mA -// 0x1 -> 4mA -// 0x2 -> 8mA -// 0x3 -> 12mA -#define PADS_BANK0_GPIO1_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO1_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO1_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO1_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO1_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO1_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO1_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO1_DRIVE_VALUE_8MA _u(0x2) -#define PADS_BANK0_GPIO1_DRIVE_VALUE_12MA _u(0x3) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO1_PUE -// Description : Pull up enable -#define PADS_BANK0_GPIO1_PUE_RESET _u(0x0) -#define PADS_BANK0_GPIO1_PUE_BITS _u(0x00000008) -#define PADS_BANK0_GPIO1_PUE_MSB _u(3) -#define PADS_BANK0_GPIO1_PUE_LSB _u(3) -#define PADS_BANK0_GPIO1_PUE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO1_PDE -// Description : Pull down enable -#define PADS_BANK0_GPIO1_PDE_RESET _u(0x1) -#define PADS_BANK0_GPIO1_PDE_BITS _u(0x00000004) -#define PADS_BANK0_GPIO1_PDE_MSB _u(2) -#define PADS_BANK0_GPIO1_PDE_LSB _u(2) -#define PADS_BANK0_GPIO1_PDE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO1_SCHMITT -// Description : Enable schmitt trigger -#define PADS_BANK0_GPIO1_SCHMITT_RESET _u(0x1) -#define PADS_BANK0_GPIO1_SCHMITT_BITS _u(0x00000002) -#define PADS_BANK0_GPIO1_SCHMITT_MSB _u(1) -#define PADS_BANK0_GPIO1_SCHMITT_LSB _u(1) -#define PADS_BANK0_GPIO1_SCHMITT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO1_SLEWFAST -// Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO1_SLEWFAST_RESET _u(0x0) -#define PADS_BANK0_GPIO1_SLEWFAST_BITS _u(0x00000001) -#define PADS_BANK0_GPIO1_SLEWFAST_MSB _u(0) -#define PADS_BANK0_GPIO1_SLEWFAST_LSB _u(0) -#define PADS_BANK0_GPIO1_SLEWFAST_ACCESS "RW" -// ============================================================================= -// Register : PADS_BANK0_GPIO2 -// Description : Pad control register -#define PADS_BANK0_GPIO2_OFFSET _u(0x0000000c) -#define PADS_BANK0_GPIO2_BITS _u(0x000000ff) -#define PADS_BANK0_GPIO2_RESET _u(0x00000056) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO2_OD -// Description : Output disable. Has priority over output enable from -// peripherals -#define PADS_BANK0_GPIO2_OD_RESET _u(0x0) -#define PADS_BANK0_GPIO2_OD_BITS _u(0x00000080) -#define PADS_BANK0_GPIO2_OD_MSB _u(7) -#define PADS_BANK0_GPIO2_OD_LSB _u(7) -#define PADS_BANK0_GPIO2_OD_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO2_IE -// Description : Input enable -#define PADS_BANK0_GPIO2_IE_RESET _u(0x1) -#define PADS_BANK0_GPIO2_IE_BITS _u(0x00000040) -#define PADS_BANK0_GPIO2_IE_MSB _u(6) -#define PADS_BANK0_GPIO2_IE_LSB _u(6) -#define PADS_BANK0_GPIO2_IE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO2_DRIVE -// Description : Drive strength. -// 0x0 -> 2mA -// 0x1 -> 4mA -// 0x2 -> 8mA -// 0x3 -> 12mA -#define PADS_BANK0_GPIO2_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO2_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO2_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO2_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO2_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO2_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO2_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO2_DRIVE_VALUE_8MA _u(0x2) -#define PADS_BANK0_GPIO2_DRIVE_VALUE_12MA _u(0x3) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO2_PUE -// Description : Pull up enable -#define PADS_BANK0_GPIO2_PUE_RESET _u(0x0) -#define PADS_BANK0_GPIO2_PUE_BITS _u(0x00000008) -#define PADS_BANK0_GPIO2_PUE_MSB _u(3) -#define PADS_BANK0_GPIO2_PUE_LSB _u(3) -#define PADS_BANK0_GPIO2_PUE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO2_PDE -// Description : Pull down enable -#define PADS_BANK0_GPIO2_PDE_RESET _u(0x1) -#define PADS_BANK0_GPIO2_PDE_BITS _u(0x00000004) -#define PADS_BANK0_GPIO2_PDE_MSB _u(2) -#define PADS_BANK0_GPIO2_PDE_LSB _u(2) -#define PADS_BANK0_GPIO2_PDE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO2_SCHMITT -// Description : Enable schmitt trigger -#define PADS_BANK0_GPIO2_SCHMITT_RESET _u(0x1) -#define PADS_BANK0_GPIO2_SCHMITT_BITS _u(0x00000002) -#define PADS_BANK0_GPIO2_SCHMITT_MSB _u(1) -#define PADS_BANK0_GPIO2_SCHMITT_LSB _u(1) -#define PADS_BANK0_GPIO2_SCHMITT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO2_SLEWFAST -// Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO2_SLEWFAST_RESET _u(0x0) -#define PADS_BANK0_GPIO2_SLEWFAST_BITS _u(0x00000001) -#define PADS_BANK0_GPIO2_SLEWFAST_MSB _u(0) -#define PADS_BANK0_GPIO2_SLEWFAST_LSB _u(0) -#define PADS_BANK0_GPIO2_SLEWFAST_ACCESS "RW" -// ============================================================================= -// Register : PADS_BANK0_GPIO3 -// Description : Pad control register -#define PADS_BANK0_GPIO3_OFFSET _u(0x00000010) -#define PADS_BANK0_GPIO3_BITS _u(0x000000ff) -#define PADS_BANK0_GPIO3_RESET _u(0x00000056) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO3_OD -// Description : Output disable. Has priority over output enable from -// peripherals -#define PADS_BANK0_GPIO3_OD_RESET _u(0x0) -#define PADS_BANK0_GPIO3_OD_BITS _u(0x00000080) -#define PADS_BANK0_GPIO3_OD_MSB _u(7) -#define PADS_BANK0_GPIO3_OD_LSB _u(7) -#define PADS_BANK0_GPIO3_OD_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO3_IE -// Description : Input enable -#define PADS_BANK0_GPIO3_IE_RESET _u(0x1) -#define PADS_BANK0_GPIO3_IE_BITS _u(0x00000040) -#define PADS_BANK0_GPIO3_IE_MSB _u(6) -#define PADS_BANK0_GPIO3_IE_LSB _u(6) -#define PADS_BANK0_GPIO3_IE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO3_DRIVE -// Description : Drive strength. -// 0x0 -> 2mA -// 0x1 -> 4mA -// 0x2 -> 8mA -// 0x3 -> 12mA -#define PADS_BANK0_GPIO3_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO3_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO3_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO3_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO3_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO3_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO3_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO3_DRIVE_VALUE_8MA _u(0x2) -#define PADS_BANK0_GPIO3_DRIVE_VALUE_12MA _u(0x3) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO3_PUE -// Description : Pull up enable -#define PADS_BANK0_GPIO3_PUE_RESET _u(0x0) -#define PADS_BANK0_GPIO3_PUE_BITS _u(0x00000008) -#define PADS_BANK0_GPIO3_PUE_MSB _u(3) -#define PADS_BANK0_GPIO3_PUE_LSB _u(3) -#define PADS_BANK0_GPIO3_PUE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO3_PDE -// Description : Pull down enable -#define PADS_BANK0_GPIO3_PDE_RESET _u(0x1) -#define PADS_BANK0_GPIO3_PDE_BITS _u(0x00000004) -#define PADS_BANK0_GPIO3_PDE_MSB _u(2) -#define PADS_BANK0_GPIO3_PDE_LSB _u(2) -#define PADS_BANK0_GPIO3_PDE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO3_SCHMITT -// Description : Enable schmitt trigger -#define PADS_BANK0_GPIO3_SCHMITT_RESET _u(0x1) -#define PADS_BANK0_GPIO3_SCHMITT_BITS _u(0x00000002) -#define PADS_BANK0_GPIO3_SCHMITT_MSB _u(1) -#define PADS_BANK0_GPIO3_SCHMITT_LSB _u(1) -#define PADS_BANK0_GPIO3_SCHMITT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO3_SLEWFAST -// Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO3_SLEWFAST_RESET _u(0x0) -#define PADS_BANK0_GPIO3_SLEWFAST_BITS _u(0x00000001) -#define PADS_BANK0_GPIO3_SLEWFAST_MSB _u(0) -#define PADS_BANK0_GPIO3_SLEWFAST_LSB _u(0) -#define PADS_BANK0_GPIO3_SLEWFAST_ACCESS "RW" -// ============================================================================= -// Register : PADS_BANK0_GPIO4 -// Description : Pad control register -#define PADS_BANK0_GPIO4_OFFSET _u(0x00000014) -#define PADS_BANK0_GPIO4_BITS _u(0x000000ff) -#define PADS_BANK0_GPIO4_RESET _u(0x00000056) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO4_OD -// Description : Output disable. Has priority over output enable from -// peripherals -#define PADS_BANK0_GPIO4_OD_RESET _u(0x0) -#define PADS_BANK0_GPIO4_OD_BITS _u(0x00000080) -#define PADS_BANK0_GPIO4_OD_MSB _u(7) -#define PADS_BANK0_GPIO4_OD_LSB _u(7) -#define PADS_BANK0_GPIO4_OD_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO4_IE -// Description : Input enable -#define PADS_BANK0_GPIO4_IE_RESET _u(0x1) -#define PADS_BANK0_GPIO4_IE_BITS _u(0x00000040) -#define PADS_BANK0_GPIO4_IE_MSB _u(6) -#define PADS_BANK0_GPIO4_IE_LSB _u(6) -#define PADS_BANK0_GPIO4_IE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO4_DRIVE -// Description : Drive strength. -// 0x0 -> 2mA -// 0x1 -> 4mA -// 0x2 -> 8mA -// 0x3 -> 12mA -#define PADS_BANK0_GPIO4_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO4_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO4_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO4_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO4_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO4_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO4_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO4_DRIVE_VALUE_8MA _u(0x2) -#define PADS_BANK0_GPIO4_DRIVE_VALUE_12MA _u(0x3) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO4_PUE -// Description : Pull up enable -#define PADS_BANK0_GPIO4_PUE_RESET _u(0x0) -#define PADS_BANK0_GPIO4_PUE_BITS _u(0x00000008) -#define PADS_BANK0_GPIO4_PUE_MSB _u(3) -#define PADS_BANK0_GPIO4_PUE_LSB _u(3) -#define PADS_BANK0_GPIO4_PUE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO4_PDE -// Description : Pull down enable -#define PADS_BANK0_GPIO4_PDE_RESET _u(0x1) -#define PADS_BANK0_GPIO4_PDE_BITS _u(0x00000004) -#define PADS_BANK0_GPIO4_PDE_MSB _u(2) -#define PADS_BANK0_GPIO4_PDE_LSB _u(2) -#define PADS_BANK0_GPIO4_PDE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO4_SCHMITT -// Description : Enable schmitt trigger -#define PADS_BANK0_GPIO4_SCHMITT_RESET _u(0x1) -#define PADS_BANK0_GPIO4_SCHMITT_BITS _u(0x00000002) -#define PADS_BANK0_GPIO4_SCHMITT_MSB _u(1) -#define PADS_BANK0_GPIO4_SCHMITT_LSB _u(1) -#define PADS_BANK0_GPIO4_SCHMITT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO4_SLEWFAST -// Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO4_SLEWFAST_RESET _u(0x0) -#define PADS_BANK0_GPIO4_SLEWFAST_BITS _u(0x00000001) -#define PADS_BANK0_GPIO4_SLEWFAST_MSB _u(0) -#define PADS_BANK0_GPIO4_SLEWFAST_LSB _u(0) -#define PADS_BANK0_GPIO4_SLEWFAST_ACCESS "RW" -// ============================================================================= -// Register : PADS_BANK0_GPIO5 -// Description : Pad control register -#define PADS_BANK0_GPIO5_OFFSET _u(0x00000018) -#define PADS_BANK0_GPIO5_BITS _u(0x000000ff) -#define PADS_BANK0_GPIO5_RESET _u(0x00000056) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO5_OD -// Description : Output disable. Has priority over output enable from -// peripherals -#define PADS_BANK0_GPIO5_OD_RESET _u(0x0) -#define PADS_BANK0_GPIO5_OD_BITS _u(0x00000080) -#define PADS_BANK0_GPIO5_OD_MSB _u(7) -#define PADS_BANK0_GPIO5_OD_LSB _u(7) -#define PADS_BANK0_GPIO5_OD_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO5_IE -// Description : Input enable -#define PADS_BANK0_GPIO5_IE_RESET _u(0x1) -#define PADS_BANK0_GPIO5_IE_BITS _u(0x00000040) -#define PADS_BANK0_GPIO5_IE_MSB _u(6) -#define PADS_BANK0_GPIO5_IE_LSB _u(6) -#define PADS_BANK0_GPIO5_IE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO5_DRIVE -// Description : Drive strength. -// 0x0 -> 2mA -// 0x1 -> 4mA -// 0x2 -> 8mA -// 0x3 -> 12mA -#define PADS_BANK0_GPIO5_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO5_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO5_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO5_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO5_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO5_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO5_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO5_DRIVE_VALUE_8MA _u(0x2) -#define PADS_BANK0_GPIO5_DRIVE_VALUE_12MA _u(0x3) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO5_PUE -// Description : Pull up enable -#define PADS_BANK0_GPIO5_PUE_RESET _u(0x0) -#define PADS_BANK0_GPIO5_PUE_BITS _u(0x00000008) -#define PADS_BANK0_GPIO5_PUE_MSB _u(3) -#define PADS_BANK0_GPIO5_PUE_LSB _u(3) -#define PADS_BANK0_GPIO5_PUE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO5_PDE -// Description : Pull down enable -#define PADS_BANK0_GPIO5_PDE_RESET _u(0x1) -#define PADS_BANK0_GPIO5_PDE_BITS _u(0x00000004) -#define PADS_BANK0_GPIO5_PDE_MSB _u(2) -#define PADS_BANK0_GPIO5_PDE_LSB _u(2) -#define PADS_BANK0_GPIO5_PDE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO5_SCHMITT -// Description : Enable schmitt trigger -#define PADS_BANK0_GPIO5_SCHMITT_RESET _u(0x1) -#define PADS_BANK0_GPIO5_SCHMITT_BITS _u(0x00000002) -#define PADS_BANK0_GPIO5_SCHMITT_MSB _u(1) -#define PADS_BANK0_GPIO5_SCHMITT_LSB _u(1) -#define PADS_BANK0_GPIO5_SCHMITT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO5_SLEWFAST -// Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO5_SLEWFAST_RESET _u(0x0) -#define PADS_BANK0_GPIO5_SLEWFAST_BITS _u(0x00000001) -#define PADS_BANK0_GPIO5_SLEWFAST_MSB _u(0) -#define PADS_BANK0_GPIO5_SLEWFAST_LSB _u(0) -#define PADS_BANK0_GPIO5_SLEWFAST_ACCESS "RW" -// ============================================================================= -// Register : PADS_BANK0_GPIO6 -// Description : Pad control register -#define PADS_BANK0_GPIO6_OFFSET _u(0x0000001c) -#define PADS_BANK0_GPIO6_BITS _u(0x000000ff) -#define PADS_BANK0_GPIO6_RESET _u(0x00000056) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO6_OD -// Description : Output disable. Has priority over output enable from -// peripherals -#define PADS_BANK0_GPIO6_OD_RESET _u(0x0) -#define PADS_BANK0_GPIO6_OD_BITS _u(0x00000080) -#define PADS_BANK0_GPIO6_OD_MSB _u(7) -#define PADS_BANK0_GPIO6_OD_LSB _u(7) -#define PADS_BANK0_GPIO6_OD_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO6_IE -// Description : Input enable -#define PADS_BANK0_GPIO6_IE_RESET _u(0x1) -#define PADS_BANK0_GPIO6_IE_BITS _u(0x00000040) -#define PADS_BANK0_GPIO6_IE_MSB _u(6) -#define PADS_BANK0_GPIO6_IE_LSB _u(6) -#define PADS_BANK0_GPIO6_IE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO6_DRIVE -// Description : Drive strength. -// 0x0 -> 2mA -// 0x1 -> 4mA -// 0x2 -> 8mA -// 0x3 -> 12mA -#define PADS_BANK0_GPIO6_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO6_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO6_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO6_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO6_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO6_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO6_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO6_DRIVE_VALUE_8MA _u(0x2) -#define PADS_BANK0_GPIO6_DRIVE_VALUE_12MA _u(0x3) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO6_PUE -// Description : Pull up enable -#define PADS_BANK0_GPIO6_PUE_RESET _u(0x0) -#define PADS_BANK0_GPIO6_PUE_BITS _u(0x00000008) -#define PADS_BANK0_GPIO6_PUE_MSB _u(3) -#define PADS_BANK0_GPIO6_PUE_LSB _u(3) -#define PADS_BANK0_GPIO6_PUE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO6_PDE -// Description : Pull down enable -#define PADS_BANK0_GPIO6_PDE_RESET _u(0x1) -#define PADS_BANK0_GPIO6_PDE_BITS _u(0x00000004) -#define PADS_BANK0_GPIO6_PDE_MSB _u(2) -#define PADS_BANK0_GPIO6_PDE_LSB _u(2) -#define PADS_BANK0_GPIO6_PDE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO6_SCHMITT -// Description : Enable schmitt trigger -#define PADS_BANK0_GPIO6_SCHMITT_RESET _u(0x1) -#define PADS_BANK0_GPIO6_SCHMITT_BITS _u(0x00000002) -#define PADS_BANK0_GPIO6_SCHMITT_MSB _u(1) -#define PADS_BANK0_GPIO6_SCHMITT_LSB _u(1) -#define PADS_BANK0_GPIO6_SCHMITT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO6_SLEWFAST -// Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO6_SLEWFAST_RESET _u(0x0) -#define PADS_BANK0_GPIO6_SLEWFAST_BITS _u(0x00000001) -#define PADS_BANK0_GPIO6_SLEWFAST_MSB _u(0) -#define PADS_BANK0_GPIO6_SLEWFAST_LSB _u(0) -#define PADS_BANK0_GPIO6_SLEWFAST_ACCESS "RW" -// ============================================================================= -// Register : PADS_BANK0_GPIO7 -// Description : Pad control register -#define PADS_BANK0_GPIO7_OFFSET _u(0x00000020) -#define PADS_BANK0_GPIO7_BITS _u(0x000000ff) -#define PADS_BANK0_GPIO7_RESET _u(0x00000056) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO7_OD -// Description : Output disable. Has priority over output enable from -// peripherals -#define PADS_BANK0_GPIO7_OD_RESET _u(0x0) -#define PADS_BANK0_GPIO7_OD_BITS _u(0x00000080) -#define PADS_BANK0_GPIO7_OD_MSB _u(7) -#define PADS_BANK0_GPIO7_OD_LSB _u(7) -#define PADS_BANK0_GPIO7_OD_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO7_IE -// Description : Input enable -#define PADS_BANK0_GPIO7_IE_RESET _u(0x1) -#define PADS_BANK0_GPIO7_IE_BITS _u(0x00000040) -#define PADS_BANK0_GPIO7_IE_MSB _u(6) -#define PADS_BANK0_GPIO7_IE_LSB _u(6) -#define PADS_BANK0_GPIO7_IE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO7_DRIVE -// Description : Drive strength. -// 0x0 -> 2mA -// 0x1 -> 4mA -// 0x2 -> 8mA -// 0x3 -> 12mA -#define PADS_BANK0_GPIO7_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO7_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO7_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO7_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO7_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO7_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO7_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO7_DRIVE_VALUE_8MA _u(0x2) -#define PADS_BANK0_GPIO7_DRIVE_VALUE_12MA _u(0x3) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO7_PUE -// Description : Pull up enable -#define PADS_BANK0_GPIO7_PUE_RESET _u(0x0) -#define PADS_BANK0_GPIO7_PUE_BITS _u(0x00000008) -#define PADS_BANK0_GPIO7_PUE_MSB _u(3) -#define PADS_BANK0_GPIO7_PUE_LSB _u(3) -#define PADS_BANK0_GPIO7_PUE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO7_PDE -// Description : Pull down enable -#define PADS_BANK0_GPIO7_PDE_RESET _u(0x1) -#define PADS_BANK0_GPIO7_PDE_BITS _u(0x00000004) -#define PADS_BANK0_GPIO7_PDE_MSB _u(2) -#define PADS_BANK0_GPIO7_PDE_LSB _u(2) -#define PADS_BANK0_GPIO7_PDE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO7_SCHMITT -// Description : Enable schmitt trigger -#define PADS_BANK0_GPIO7_SCHMITT_RESET _u(0x1) -#define PADS_BANK0_GPIO7_SCHMITT_BITS _u(0x00000002) -#define PADS_BANK0_GPIO7_SCHMITT_MSB _u(1) -#define PADS_BANK0_GPIO7_SCHMITT_LSB _u(1) -#define PADS_BANK0_GPIO7_SCHMITT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO7_SLEWFAST -// Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO7_SLEWFAST_RESET _u(0x0) -#define PADS_BANK0_GPIO7_SLEWFAST_BITS _u(0x00000001) -#define PADS_BANK0_GPIO7_SLEWFAST_MSB _u(0) -#define PADS_BANK0_GPIO7_SLEWFAST_LSB _u(0) -#define PADS_BANK0_GPIO7_SLEWFAST_ACCESS "RW" -// ============================================================================= -// Register : PADS_BANK0_GPIO8 -// Description : Pad control register -#define PADS_BANK0_GPIO8_OFFSET _u(0x00000024) -#define PADS_BANK0_GPIO8_BITS _u(0x000000ff) -#define PADS_BANK0_GPIO8_RESET _u(0x00000056) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO8_OD -// Description : Output disable. Has priority over output enable from -// peripherals -#define PADS_BANK0_GPIO8_OD_RESET _u(0x0) -#define PADS_BANK0_GPIO8_OD_BITS _u(0x00000080) -#define PADS_BANK0_GPIO8_OD_MSB _u(7) -#define PADS_BANK0_GPIO8_OD_LSB _u(7) -#define PADS_BANK0_GPIO8_OD_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO8_IE -// Description : Input enable -#define PADS_BANK0_GPIO8_IE_RESET _u(0x1) -#define PADS_BANK0_GPIO8_IE_BITS _u(0x00000040) -#define PADS_BANK0_GPIO8_IE_MSB _u(6) -#define PADS_BANK0_GPIO8_IE_LSB _u(6) -#define PADS_BANK0_GPIO8_IE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO8_DRIVE -// Description : Drive strength. -// 0x0 -> 2mA -// 0x1 -> 4mA -// 0x2 -> 8mA -// 0x3 -> 12mA -#define PADS_BANK0_GPIO8_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO8_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO8_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO8_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO8_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO8_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO8_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO8_DRIVE_VALUE_8MA _u(0x2) -#define PADS_BANK0_GPIO8_DRIVE_VALUE_12MA _u(0x3) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO8_PUE -// Description : Pull up enable -#define PADS_BANK0_GPIO8_PUE_RESET _u(0x0) -#define PADS_BANK0_GPIO8_PUE_BITS _u(0x00000008) -#define PADS_BANK0_GPIO8_PUE_MSB _u(3) -#define PADS_BANK0_GPIO8_PUE_LSB _u(3) -#define PADS_BANK0_GPIO8_PUE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO8_PDE -// Description : Pull down enable -#define PADS_BANK0_GPIO8_PDE_RESET _u(0x1) -#define PADS_BANK0_GPIO8_PDE_BITS _u(0x00000004) -#define PADS_BANK0_GPIO8_PDE_MSB _u(2) -#define PADS_BANK0_GPIO8_PDE_LSB _u(2) -#define PADS_BANK0_GPIO8_PDE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO8_SCHMITT -// Description : Enable schmitt trigger -#define PADS_BANK0_GPIO8_SCHMITT_RESET _u(0x1) -#define PADS_BANK0_GPIO8_SCHMITT_BITS _u(0x00000002) -#define PADS_BANK0_GPIO8_SCHMITT_MSB _u(1) -#define PADS_BANK0_GPIO8_SCHMITT_LSB _u(1) -#define PADS_BANK0_GPIO8_SCHMITT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO8_SLEWFAST -// Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO8_SLEWFAST_RESET _u(0x0) -#define PADS_BANK0_GPIO8_SLEWFAST_BITS _u(0x00000001) -#define PADS_BANK0_GPIO8_SLEWFAST_MSB _u(0) -#define PADS_BANK0_GPIO8_SLEWFAST_LSB _u(0) -#define PADS_BANK0_GPIO8_SLEWFAST_ACCESS "RW" -// ============================================================================= -// Register : PADS_BANK0_GPIO9 -// Description : Pad control register -#define PADS_BANK0_GPIO9_OFFSET _u(0x00000028) -#define PADS_BANK0_GPIO9_BITS _u(0x000000ff) -#define PADS_BANK0_GPIO9_RESET _u(0x00000056) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO9_OD -// Description : Output disable. Has priority over output enable from -// peripherals -#define PADS_BANK0_GPIO9_OD_RESET _u(0x0) -#define PADS_BANK0_GPIO9_OD_BITS _u(0x00000080) -#define PADS_BANK0_GPIO9_OD_MSB _u(7) -#define PADS_BANK0_GPIO9_OD_LSB _u(7) -#define PADS_BANK0_GPIO9_OD_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO9_IE -// Description : Input enable -#define PADS_BANK0_GPIO9_IE_RESET _u(0x1) -#define PADS_BANK0_GPIO9_IE_BITS _u(0x00000040) -#define PADS_BANK0_GPIO9_IE_MSB _u(6) -#define PADS_BANK0_GPIO9_IE_LSB _u(6) -#define PADS_BANK0_GPIO9_IE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO9_DRIVE -// Description : Drive strength. -// 0x0 -> 2mA -// 0x1 -> 4mA -// 0x2 -> 8mA -// 0x3 -> 12mA -#define PADS_BANK0_GPIO9_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO9_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO9_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO9_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO9_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO9_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO9_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO9_DRIVE_VALUE_8MA _u(0x2) -#define PADS_BANK0_GPIO9_DRIVE_VALUE_12MA _u(0x3) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO9_PUE -// Description : Pull up enable -#define PADS_BANK0_GPIO9_PUE_RESET _u(0x0) -#define PADS_BANK0_GPIO9_PUE_BITS _u(0x00000008) -#define PADS_BANK0_GPIO9_PUE_MSB _u(3) -#define PADS_BANK0_GPIO9_PUE_LSB _u(3) -#define PADS_BANK0_GPIO9_PUE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO9_PDE -// Description : Pull down enable -#define PADS_BANK0_GPIO9_PDE_RESET _u(0x1) -#define PADS_BANK0_GPIO9_PDE_BITS _u(0x00000004) -#define PADS_BANK0_GPIO9_PDE_MSB _u(2) -#define PADS_BANK0_GPIO9_PDE_LSB _u(2) -#define PADS_BANK0_GPIO9_PDE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO9_SCHMITT -// Description : Enable schmitt trigger -#define PADS_BANK0_GPIO9_SCHMITT_RESET _u(0x1) -#define PADS_BANK0_GPIO9_SCHMITT_BITS _u(0x00000002) -#define PADS_BANK0_GPIO9_SCHMITT_MSB _u(1) -#define PADS_BANK0_GPIO9_SCHMITT_LSB _u(1) -#define PADS_BANK0_GPIO9_SCHMITT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO9_SLEWFAST -// Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO9_SLEWFAST_RESET _u(0x0) -#define PADS_BANK0_GPIO9_SLEWFAST_BITS _u(0x00000001) -#define PADS_BANK0_GPIO9_SLEWFAST_MSB _u(0) -#define PADS_BANK0_GPIO9_SLEWFAST_LSB _u(0) -#define PADS_BANK0_GPIO9_SLEWFAST_ACCESS "RW" -// ============================================================================= -// Register : PADS_BANK0_GPIO10 -// Description : Pad control register -#define PADS_BANK0_GPIO10_OFFSET _u(0x0000002c) -#define PADS_BANK0_GPIO10_BITS _u(0x000000ff) -#define PADS_BANK0_GPIO10_RESET _u(0x00000056) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO10_OD -// Description : Output disable. Has priority over output enable from -// peripherals -#define PADS_BANK0_GPIO10_OD_RESET _u(0x0) -#define PADS_BANK0_GPIO10_OD_BITS _u(0x00000080) -#define PADS_BANK0_GPIO10_OD_MSB _u(7) -#define PADS_BANK0_GPIO10_OD_LSB _u(7) -#define PADS_BANK0_GPIO10_OD_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO10_IE -// Description : Input enable -#define PADS_BANK0_GPIO10_IE_RESET _u(0x1) -#define PADS_BANK0_GPIO10_IE_BITS _u(0x00000040) -#define PADS_BANK0_GPIO10_IE_MSB _u(6) -#define PADS_BANK0_GPIO10_IE_LSB _u(6) -#define PADS_BANK0_GPIO10_IE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO10_DRIVE -// Description : Drive strength. -// 0x0 -> 2mA -// 0x1 -> 4mA -// 0x2 -> 8mA -// 0x3 -> 12mA -#define PADS_BANK0_GPIO10_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO10_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO10_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO10_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO10_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO10_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO10_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO10_DRIVE_VALUE_8MA _u(0x2) -#define PADS_BANK0_GPIO10_DRIVE_VALUE_12MA _u(0x3) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO10_PUE -// Description : Pull up enable -#define PADS_BANK0_GPIO10_PUE_RESET _u(0x0) -#define PADS_BANK0_GPIO10_PUE_BITS _u(0x00000008) -#define PADS_BANK0_GPIO10_PUE_MSB _u(3) -#define PADS_BANK0_GPIO10_PUE_LSB _u(3) -#define PADS_BANK0_GPIO10_PUE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO10_PDE -// Description : Pull down enable -#define PADS_BANK0_GPIO10_PDE_RESET _u(0x1) -#define PADS_BANK0_GPIO10_PDE_BITS _u(0x00000004) -#define PADS_BANK0_GPIO10_PDE_MSB _u(2) -#define PADS_BANK0_GPIO10_PDE_LSB _u(2) -#define PADS_BANK0_GPIO10_PDE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO10_SCHMITT -// Description : Enable schmitt trigger -#define PADS_BANK0_GPIO10_SCHMITT_RESET _u(0x1) -#define PADS_BANK0_GPIO10_SCHMITT_BITS _u(0x00000002) -#define PADS_BANK0_GPIO10_SCHMITT_MSB _u(1) -#define PADS_BANK0_GPIO10_SCHMITT_LSB _u(1) -#define PADS_BANK0_GPIO10_SCHMITT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO10_SLEWFAST -// Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO10_SLEWFAST_RESET _u(0x0) -#define PADS_BANK0_GPIO10_SLEWFAST_BITS _u(0x00000001) -#define PADS_BANK0_GPIO10_SLEWFAST_MSB _u(0) -#define PADS_BANK0_GPIO10_SLEWFAST_LSB _u(0) -#define PADS_BANK0_GPIO10_SLEWFAST_ACCESS "RW" -// ============================================================================= -// Register : PADS_BANK0_GPIO11 -// Description : Pad control register -#define PADS_BANK0_GPIO11_OFFSET _u(0x00000030) -#define PADS_BANK0_GPIO11_BITS _u(0x000000ff) -#define PADS_BANK0_GPIO11_RESET _u(0x00000056) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO11_OD -// Description : Output disable. Has priority over output enable from -// peripherals -#define PADS_BANK0_GPIO11_OD_RESET _u(0x0) -#define PADS_BANK0_GPIO11_OD_BITS _u(0x00000080) -#define PADS_BANK0_GPIO11_OD_MSB _u(7) -#define PADS_BANK0_GPIO11_OD_LSB _u(7) -#define PADS_BANK0_GPIO11_OD_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO11_IE -// Description : Input enable -#define PADS_BANK0_GPIO11_IE_RESET _u(0x1) -#define PADS_BANK0_GPIO11_IE_BITS _u(0x00000040) -#define PADS_BANK0_GPIO11_IE_MSB _u(6) -#define PADS_BANK0_GPIO11_IE_LSB _u(6) -#define PADS_BANK0_GPIO11_IE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO11_DRIVE -// Description : Drive strength. -// 0x0 -> 2mA -// 0x1 -> 4mA -// 0x2 -> 8mA -// 0x3 -> 12mA -#define PADS_BANK0_GPIO11_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO11_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO11_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO11_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO11_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO11_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO11_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO11_DRIVE_VALUE_8MA _u(0x2) -#define PADS_BANK0_GPIO11_DRIVE_VALUE_12MA _u(0x3) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO11_PUE -// Description : Pull up enable -#define PADS_BANK0_GPIO11_PUE_RESET _u(0x0) -#define PADS_BANK0_GPIO11_PUE_BITS _u(0x00000008) -#define PADS_BANK0_GPIO11_PUE_MSB _u(3) -#define PADS_BANK0_GPIO11_PUE_LSB _u(3) -#define PADS_BANK0_GPIO11_PUE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO11_PDE -// Description : Pull down enable -#define PADS_BANK0_GPIO11_PDE_RESET _u(0x1) -#define PADS_BANK0_GPIO11_PDE_BITS _u(0x00000004) -#define PADS_BANK0_GPIO11_PDE_MSB _u(2) -#define PADS_BANK0_GPIO11_PDE_LSB _u(2) -#define PADS_BANK0_GPIO11_PDE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO11_SCHMITT -// Description : Enable schmitt trigger -#define PADS_BANK0_GPIO11_SCHMITT_RESET _u(0x1) -#define PADS_BANK0_GPIO11_SCHMITT_BITS _u(0x00000002) -#define PADS_BANK0_GPIO11_SCHMITT_MSB _u(1) -#define PADS_BANK0_GPIO11_SCHMITT_LSB _u(1) -#define PADS_BANK0_GPIO11_SCHMITT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO11_SLEWFAST -// Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO11_SLEWFAST_RESET _u(0x0) -#define PADS_BANK0_GPIO11_SLEWFAST_BITS _u(0x00000001) -#define PADS_BANK0_GPIO11_SLEWFAST_MSB _u(0) -#define PADS_BANK0_GPIO11_SLEWFAST_LSB _u(0) -#define PADS_BANK0_GPIO11_SLEWFAST_ACCESS "RW" -// ============================================================================= -// Register : PADS_BANK0_GPIO12 -// Description : Pad control register -#define PADS_BANK0_GPIO12_OFFSET _u(0x00000034) -#define PADS_BANK0_GPIO12_BITS _u(0x000000ff) -#define PADS_BANK0_GPIO12_RESET _u(0x00000056) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO12_OD -// Description : Output disable. Has priority over output enable from -// peripherals -#define PADS_BANK0_GPIO12_OD_RESET _u(0x0) -#define PADS_BANK0_GPIO12_OD_BITS _u(0x00000080) -#define PADS_BANK0_GPIO12_OD_MSB _u(7) -#define PADS_BANK0_GPIO12_OD_LSB _u(7) -#define PADS_BANK0_GPIO12_OD_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO12_IE -// Description : Input enable -#define PADS_BANK0_GPIO12_IE_RESET _u(0x1) -#define PADS_BANK0_GPIO12_IE_BITS _u(0x00000040) -#define PADS_BANK0_GPIO12_IE_MSB _u(6) -#define PADS_BANK0_GPIO12_IE_LSB _u(6) -#define PADS_BANK0_GPIO12_IE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO12_DRIVE -// Description : Drive strength. -// 0x0 -> 2mA -// 0x1 -> 4mA -// 0x2 -> 8mA -// 0x3 -> 12mA -#define PADS_BANK0_GPIO12_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO12_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO12_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO12_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO12_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO12_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO12_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO12_DRIVE_VALUE_8MA _u(0x2) -#define PADS_BANK0_GPIO12_DRIVE_VALUE_12MA _u(0x3) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO12_PUE -// Description : Pull up enable -#define PADS_BANK0_GPIO12_PUE_RESET _u(0x0) -#define PADS_BANK0_GPIO12_PUE_BITS _u(0x00000008) -#define PADS_BANK0_GPIO12_PUE_MSB _u(3) -#define PADS_BANK0_GPIO12_PUE_LSB _u(3) -#define PADS_BANK0_GPIO12_PUE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO12_PDE -// Description : Pull down enable -#define PADS_BANK0_GPIO12_PDE_RESET _u(0x1) -#define PADS_BANK0_GPIO12_PDE_BITS _u(0x00000004) -#define PADS_BANK0_GPIO12_PDE_MSB _u(2) -#define PADS_BANK0_GPIO12_PDE_LSB _u(2) -#define PADS_BANK0_GPIO12_PDE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO12_SCHMITT -// Description : Enable schmitt trigger -#define PADS_BANK0_GPIO12_SCHMITT_RESET _u(0x1) -#define PADS_BANK0_GPIO12_SCHMITT_BITS _u(0x00000002) -#define PADS_BANK0_GPIO12_SCHMITT_MSB _u(1) -#define PADS_BANK0_GPIO12_SCHMITT_LSB _u(1) -#define PADS_BANK0_GPIO12_SCHMITT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO12_SLEWFAST -// Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO12_SLEWFAST_RESET _u(0x0) -#define PADS_BANK0_GPIO12_SLEWFAST_BITS _u(0x00000001) -#define PADS_BANK0_GPIO12_SLEWFAST_MSB _u(0) -#define PADS_BANK0_GPIO12_SLEWFAST_LSB _u(0) -#define PADS_BANK0_GPIO12_SLEWFAST_ACCESS "RW" -// ============================================================================= -// Register : PADS_BANK0_GPIO13 -// Description : Pad control register -#define PADS_BANK0_GPIO13_OFFSET _u(0x00000038) -#define PADS_BANK0_GPIO13_BITS _u(0x000000ff) -#define PADS_BANK0_GPIO13_RESET _u(0x00000056) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO13_OD -// Description : Output disable. Has priority over output enable from -// peripherals -#define PADS_BANK0_GPIO13_OD_RESET _u(0x0) -#define PADS_BANK0_GPIO13_OD_BITS _u(0x00000080) -#define PADS_BANK0_GPIO13_OD_MSB _u(7) -#define PADS_BANK0_GPIO13_OD_LSB _u(7) -#define PADS_BANK0_GPIO13_OD_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO13_IE -// Description : Input enable -#define PADS_BANK0_GPIO13_IE_RESET _u(0x1) -#define PADS_BANK0_GPIO13_IE_BITS _u(0x00000040) -#define PADS_BANK0_GPIO13_IE_MSB _u(6) -#define PADS_BANK0_GPIO13_IE_LSB _u(6) -#define PADS_BANK0_GPIO13_IE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO13_DRIVE -// Description : Drive strength. -// 0x0 -> 2mA -// 0x1 -> 4mA -// 0x2 -> 8mA -// 0x3 -> 12mA -#define PADS_BANK0_GPIO13_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO13_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO13_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO13_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO13_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO13_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO13_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO13_DRIVE_VALUE_8MA _u(0x2) -#define PADS_BANK0_GPIO13_DRIVE_VALUE_12MA _u(0x3) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO13_PUE -// Description : Pull up enable -#define PADS_BANK0_GPIO13_PUE_RESET _u(0x0) -#define PADS_BANK0_GPIO13_PUE_BITS _u(0x00000008) -#define PADS_BANK0_GPIO13_PUE_MSB _u(3) -#define PADS_BANK0_GPIO13_PUE_LSB _u(3) -#define PADS_BANK0_GPIO13_PUE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO13_PDE -// Description : Pull down enable -#define PADS_BANK0_GPIO13_PDE_RESET _u(0x1) -#define PADS_BANK0_GPIO13_PDE_BITS _u(0x00000004) -#define PADS_BANK0_GPIO13_PDE_MSB _u(2) -#define PADS_BANK0_GPIO13_PDE_LSB _u(2) -#define PADS_BANK0_GPIO13_PDE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO13_SCHMITT -// Description : Enable schmitt trigger -#define PADS_BANK0_GPIO13_SCHMITT_RESET _u(0x1) -#define PADS_BANK0_GPIO13_SCHMITT_BITS _u(0x00000002) -#define PADS_BANK0_GPIO13_SCHMITT_MSB _u(1) -#define PADS_BANK0_GPIO13_SCHMITT_LSB _u(1) -#define PADS_BANK0_GPIO13_SCHMITT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO13_SLEWFAST -// Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO13_SLEWFAST_RESET _u(0x0) -#define PADS_BANK0_GPIO13_SLEWFAST_BITS _u(0x00000001) -#define PADS_BANK0_GPIO13_SLEWFAST_MSB _u(0) -#define PADS_BANK0_GPIO13_SLEWFAST_LSB _u(0) -#define PADS_BANK0_GPIO13_SLEWFAST_ACCESS "RW" -// ============================================================================= -// Register : PADS_BANK0_GPIO14 -// Description : Pad control register -#define PADS_BANK0_GPIO14_OFFSET _u(0x0000003c) -#define PADS_BANK0_GPIO14_BITS _u(0x000000ff) -#define PADS_BANK0_GPIO14_RESET _u(0x00000056) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO14_OD -// Description : Output disable. Has priority over output enable from -// peripherals -#define PADS_BANK0_GPIO14_OD_RESET _u(0x0) -#define PADS_BANK0_GPIO14_OD_BITS _u(0x00000080) -#define PADS_BANK0_GPIO14_OD_MSB _u(7) -#define PADS_BANK0_GPIO14_OD_LSB _u(7) -#define PADS_BANK0_GPIO14_OD_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO14_IE -// Description : Input enable -#define PADS_BANK0_GPIO14_IE_RESET _u(0x1) -#define PADS_BANK0_GPIO14_IE_BITS _u(0x00000040) -#define PADS_BANK0_GPIO14_IE_MSB _u(6) -#define PADS_BANK0_GPIO14_IE_LSB _u(6) -#define PADS_BANK0_GPIO14_IE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO14_DRIVE -// Description : Drive strength. -// 0x0 -> 2mA -// 0x1 -> 4mA -// 0x2 -> 8mA -// 0x3 -> 12mA -#define PADS_BANK0_GPIO14_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO14_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO14_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO14_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO14_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO14_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO14_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO14_DRIVE_VALUE_8MA _u(0x2) -#define PADS_BANK0_GPIO14_DRIVE_VALUE_12MA _u(0x3) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO14_PUE -// Description : Pull up enable -#define PADS_BANK0_GPIO14_PUE_RESET _u(0x0) -#define PADS_BANK0_GPIO14_PUE_BITS _u(0x00000008) -#define PADS_BANK0_GPIO14_PUE_MSB _u(3) -#define PADS_BANK0_GPIO14_PUE_LSB _u(3) -#define PADS_BANK0_GPIO14_PUE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO14_PDE -// Description : Pull down enable -#define PADS_BANK0_GPIO14_PDE_RESET _u(0x1) -#define PADS_BANK0_GPIO14_PDE_BITS _u(0x00000004) -#define PADS_BANK0_GPIO14_PDE_MSB _u(2) -#define PADS_BANK0_GPIO14_PDE_LSB _u(2) -#define PADS_BANK0_GPIO14_PDE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO14_SCHMITT -// Description : Enable schmitt trigger -#define PADS_BANK0_GPIO14_SCHMITT_RESET _u(0x1) -#define PADS_BANK0_GPIO14_SCHMITT_BITS _u(0x00000002) -#define PADS_BANK0_GPIO14_SCHMITT_MSB _u(1) -#define PADS_BANK0_GPIO14_SCHMITT_LSB _u(1) -#define PADS_BANK0_GPIO14_SCHMITT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO14_SLEWFAST -// Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO14_SLEWFAST_RESET _u(0x0) -#define PADS_BANK0_GPIO14_SLEWFAST_BITS _u(0x00000001) -#define PADS_BANK0_GPIO14_SLEWFAST_MSB _u(0) -#define PADS_BANK0_GPIO14_SLEWFAST_LSB _u(0) -#define PADS_BANK0_GPIO14_SLEWFAST_ACCESS "RW" -// ============================================================================= -// Register : PADS_BANK0_GPIO15 -// Description : Pad control register -#define PADS_BANK0_GPIO15_OFFSET _u(0x00000040) -#define PADS_BANK0_GPIO15_BITS _u(0x000000ff) -#define PADS_BANK0_GPIO15_RESET _u(0x00000056) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO15_OD -// Description : Output disable. Has priority over output enable from -// peripherals -#define PADS_BANK0_GPIO15_OD_RESET _u(0x0) -#define PADS_BANK0_GPIO15_OD_BITS _u(0x00000080) -#define PADS_BANK0_GPIO15_OD_MSB _u(7) -#define PADS_BANK0_GPIO15_OD_LSB _u(7) -#define PADS_BANK0_GPIO15_OD_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO15_IE -// Description : Input enable -#define PADS_BANK0_GPIO15_IE_RESET _u(0x1) -#define PADS_BANK0_GPIO15_IE_BITS _u(0x00000040) -#define PADS_BANK0_GPIO15_IE_MSB _u(6) -#define PADS_BANK0_GPIO15_IE_LSB _u(6) -#define PADS_BANK0_GPIO15_IE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO15_DRIVE -// Description : Drive strength. -// 0x0 -> 2mA -// 0x1 -> 4mA -// 0x2 -> 8mA -// 0x3 -> 12mA -#define PADS_BANK0_GPIO15_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO15_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO15_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO15_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO15_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO15_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO15_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO15_DRIVE_VALUE_8MA _u(0x2) -#define PADS_BANK0_GPIO15_DRIVE_VALUE_12MA _u(0x3) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO15_PUE -// Description : Pull up enable -#define PADS_BANK0_GPIO15_PUE_RESET _u(0x0) -#define PADS_BANK0_GPIO15_PUE_BITS _u(0x00000008) -#define PADS_BANK0_GPIO15_PUE_MSB _u(3) -#define PADS_BANK0_GPIO15_PUE_LSB _u(3) -#define PADS_BANK0_GPIO15_PUE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO15_PDE -// Description : Pull down enable -#define PADS_BANK0_GPIO15_PDE_RESET _u(0x1) -#define PADS_BANK0_GPIO15_PDE_BITS _u(0x00000004) -#define PADS_BANK0_GPIO15_PDE_MSB _u(2) -#define PADS_BANK0_GPIO15_PDE_LSB _u(2) -#define PADS_BANK0_GPIO15_PDE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO15_SCHMITT -// Description : Enable schmitt trigger -#define PADS_BANK0_GPIO15_SCHMITT_RESET _u(0x1) -#define PADS_BANK0_GPIO15_SCHMITT_BITS _u(0x00000002) -#define PADS_BANK0_GPIO15_SCHMITT_MSB _u(1) -#define PADS_BANK0_GPIO15_SCHMITT_LSB _u(1) -#define PADS_BANK0_GPIO15_SCHMITT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO15_SLEWFAST -// Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO15_SLEWFAST_RESET _u(0x0) -#define PADS_BANK0_GPIO15_SLEWFAST_BITS _u(0x00000001) -#define PADS_BANK0_GPIO15_SLEWFAST_MSB _u(0) -#define PADS_BANK0_GPIO15_SLEWFAST_LSB _u(0) -#define PADS_BANK0_GPIO15_SLEWFAST_ACCESS "RW" -// ============================================================================= -// Register : PADS_BANK0_GPIO16 -// Description : Pad control register -#define PADS_BANK0_GPIO16_OFFSET _u(0x00000044) -#define PADS_BANK0_GPIO16_BITS _u(0x000000ff) -#define PADS_BANK0_GPIO16_RESET _u(0x00000056) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO16_OD -// Description : Output disable. Has priority over output enable from -// peripherals -#define PADS_BANK0_GPIO16_OD_RESET _u(0x0) -#define PADS_BANK0_GPIO16_OD_BITS _u(0x00000080) -#define PADS_BANK0_GPIO16_OD_MSB _u(7) -#define PADS_BANK0_GPIO16_OD_LSB _u(7) -#define PADS_BANK0_GPIO16_OD_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO16_IE -// Description : Input enable -#define PADS_BANK0_GPIO16_IE_RESET _u(0x1) -#define PADS_BANK0_GPIO16_IE_BITS _u(0x00000040) -#define PADS_BANK0_GPIO16_IE_MSB _u(6) -#define PADS_BANK0_GPIO16_IE_LSB _u(6) -#define PADS_BANK0_GPIO16_IE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO16_DRIVE -// Description : Drive strength. -// 0x0 -> 2mA -// 0x1 -> 4mA -// 0x2 -> 8mA -// 0x3 -> 12mA -#define PADS_BANK0_GPIO16_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO16_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO16_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO16_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO16_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO16_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO16_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO16_DRIVE_VALUE_8MA _u(0x2) -#define PADS_BANK0_GPIO16_DRIVE_VALUE_12MA _u(0x3) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO16_PUE -// Description : Pull up enable -#define PADS_BANK0_GPIO16_PUE_RESET _u(0x0) -#define PADS_BANK0_GPIO16_PUE_BITS _u(0x00000008) -#define PADS_BANK0_GPIO16_PUE_MSB _u(3) -#define PADS_BANK0_GPIO16_PUE_LSB _u(3) -#define PADS_BANK0_GPIO16_PUE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO16_PDE -// Description : Pull down enable -#define PADS_BANK0_GPIO16_PDE_RESET _u(0x1) -#define PADS_BANK0_GPIO16_PDE_BITS _u(0x00000004) -#define PADS_BANK0_GPIO16_PDE_MSB _u(2) -#define PADS_BANK0_GPIO16_PDE_LSB _u(2) -#define PADS_BANK0_GPIO16_PDE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO16_SCHMITT -// Description : Enable schmitt trigger -#define PADS_BANK0_GPIO16_SCHMITT_RESET _u(0x1) -#define PADS_BANK0_GPIO16_SCHMITT_BITS _u(0x00000002) -#define PADS_BANK0_GPIO16_SCHMITT_MSB _u(1) -#define PADS_BANK0_GPIO16_SCHMITT_LSB _u(1) -#define PADS_BANK0_GPIO16_SCHMITT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO16_SLEWFAST -// Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO16_SLEWFAST_RESET _u(0x0) -#define PADS_BANK0_GPIO16_SLEWFAST_BITS _u(0x00000001) -#define PADS_BANK0_GPIO16_SLEWFAST_MSB _u(0) -#define PADS_BANK0_GPIO16_SLEWFAST_LSB _u(0) -#define PADS_BANK0_GPIO16_SLEWFAST_ACCESS "RW" -// ============================================================================= -// Register : PADS_BANK0_GPIO17 -// Description : Pad control register -#define PADS_BANK0_GPIO17_OFFSET _u(0x00000048) -#define PADS_BANK0_GPIO17_BITS _u(0x000000ff) -#define PADS_BANK0_GPIO17_RESET _u(0x00000056) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO17_OD -// Description : Output disable. Has priority over output enable from -// peripherals -#define PADS_BANK0_GPIO17_OD_RESET _u(0x0) -#define PADS_BANK0_GPIO17_OD_BITS _u(0x00000080) -#define PADS_BANK0_GPIO17_OD_MSB _u(7) -#define PADS_BANK0_GPIO17_OD_LSB _u(7) -#define PADS_BANK0_GPIO17_OD_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO17_IE -// Description : Input enable -#define PADS_BANK0_GPIO17_IE_RESET _u(0x1) -#define PADS_BANK0_GPIO17_IE_BITS _u(0x00000040) -#define PADS_BANK0_GPIO17_IE_MSB _u(6) -#define PADS_BANK0_GPIO17_IE_LSB _u(6) -#define PADS_BANK0_GPIO17_IE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO17_DRIVE -// Description : Drive strength. -// 0x0 -> 2mA -// 0x1 -> 4mA -// 0x2 -> 8mA -// 0x3 -> 12mA -#define PADS_BANK0_GPIO17_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO17_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO17_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO17_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO17_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO17_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO17_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO17_DRIVE_VALUE_8MA _u(0x2) -#define PADS_BANK0_GPIO17_DRIVE_VALUE_12MA _u(0x3) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO17_PUE -// Description : Pull up enable -#define PADS_BANK0_GPIO17_PUE_RESET _u(0x0) -#define PADS_BANK0_GPIO17_PUE_BITS _u(0x00000008) -#define PADS_BANK0_GPIO17_PUE_MSB _u(3) -#define PADS_BANK0_GPIO17_PUE_LSB _u(3) -#define PADS_BANK0_GPIO17_PUE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO17_PDE -// Description : Pull down enable -#define PADS_BANK0_GPIO17_PDE_RESET _u(0x1) -#define PADS_BANK0_GPIO17_PDE_BITS _u(0x00000004) -#define PADS_BANK0_GPIO17_PDE_MSB _u(2) -#define PADS_BANK0_GPIO17_PDE_LSB _u(2) -#define PADS_BANK0_GPIO17_PDE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO17_SCHMITT -// Description : Enable schmitt trigger -#define PADS_BANK0_GPIO17_SCHMITT_RESET _u(0x1) -#define PADS_BANK0_GPIO17_SCHMITT_BITS _u(0x00000002) -#define PADS_BANK0_GPIO17_SCHMITT_MSB _u(1) -#define PADS_BANK0_GPIO17_SCHMITT_LSB _u(1) -#define PADS_BANK0_GPIO17_SCHMITT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO17_SLEWFAST -// Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO17_SLEWFAST_RESET _u(0x0) -#define PADS_BANK0_GPIO17_SLEWFAST_BITS _u(0x00000001) -#define PADS_BANK0_GPIO17_SLEWFAST_MSB _u(0) -#define PADS_BANK0_GPIO17_SLEWFAST_LSB _u(0) -#define PADS_BANK0_GPIO17_SLEWFAST_ACCESS "RW" -// ============================================================================= -// Register : PADS_BANK0_GPIO18 -// Description : Pad control register -#define PADS_BANK0_GPIO18_OFFSET _u(0x0000004c) -#define PADS_BANK0_GPIO18_BITS _u(0x000000ff) -#define PADS_BANK0_GPIO18_RESET _u(0x00000056) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO18_OD -// Description : Output disable. Has priority over output enable from -// peripherals -#define PADS_BANK0_GPIO18_OD_RESET _u(0x0) -#define PADS_BANK0_GPIO18_OD_BITS _u(0x00000080) -#define PADS_BANK0_GPIO18_OD_MSB _u(7) -#define PADS_BANK0_GPIO18_OD_LSB _u(7) -#define PADS_BANK0_GPIO18_OD_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO18_IE -// Description : Input enable -#define PADS_BANK0_GPIO18_IE_RESET _u(0x1) -#define PADS_BANK0_GPIO18_IE_BITS _u(0x00000040) -#define PADS_BANK0_GPIO18_IE_MSB _u(6) -#define PADS_BANK0_GPIO18_IE_LSB _u(6) -#define PADS_BANK0_GPIO18_IE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO18_DRIVE -// Description : Drive strength. -// 0x0 -> 2mA -// 0x1 -> 4mA -// 0x2 -> 8mA -// 0x3 -> 12mA -#define PADS_BANK0_GPIO18_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO18_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO18_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO18_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO18_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO18_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO18_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO18_DRIVE_VALUE_8MA _u(0x2) -#define PADS_BANK0_GPIO18_DRIVE_VALUE_12MA _u(0x3) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO18_PUE -// Description : Pull up enable -#define PADS_BANK0_GPIO18_PUE_RESET _u(0x0) -#define PADS_BANK0_GPIO18_PUE_BITS _u(0x00000008) -#define PADS_BANK0_GPIO18_PUE_MSB _u(3) -#define PADS_BANK0_GPIO18_PUE_LSB _u(3) -#define PADS_BANK0_GPIO18_PUE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO18_PDE -// Description : Pull down enable -#define PADS_BANK0_GPIO18_PDE_RESET _u(0x1) -#define PADS_BANK0_GPIO18_PDE_BITS _u(0x00000004) -#define PADS_BANK0_GPIO18_PDE_MSB _u(2) -#define PADS_BANK0_GPIO18_PDE_LSB _u(2) -#define PADS_BANK0_GPIO18_PDE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO18_SCHMITT -// Description : Enable schmitt trigger -#define PADS_BANK0_GPIO18_SCHMITT_RESET _u(0x1) -#define PADS_BANK0_GPIO18_SCHMITT_BITS _u(0x00000002) -#define PADS_BANK0_GPIO18_SCHMITT_MSB _u(1) -#define PADS_BANK0_GPIO18_SCHMITT_LSB _u(1) -#define PADS_BANK0_GPIO18_SCHMITT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO18_SLEWFAST -// Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO18_SLEWFAST_RESET _u(0x0) -#define PADS_BANK0_GPIO18_SLEWFAST_BITS _u(0x00000001) -#define PADS_BANK0_GPIO18_SLEWFAST_MSB _u(0) -#define PADS_BANK0_GPIO18_SLEWFAST_LSB _u(0) -#define PADS_BANK0_GPIO18_SLEWFAST_ACCESS "RW" -// ============================================================================= -// Register : PADS_BANK0_GPIO19 -// Description : Pad control register -#define PADS_BANK0_GPIO19_OFFSET _u(0x00000050) -#define PADS_BANK0_GPIO19_BITS _u(0x000000ff) -#define PADS_BANK0_GPIO19_RESET _u(0x00000056) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO19_OD -// Description : Output disable. Has priority over output enable from -// peripherals -#define PADS_BANK0_GPIO19_OD_RESET _u(0x0) -#define PADS_BANK0_GPIO19_OD_BITS _u(0x00000080) -#define PADS_BANK0_GPIO19_OD_MSB _u(7) -#define PADS_BANK0_GPIO19_OD_LSB _u(7) -#define PADS_BANK0_GPIO19_OD_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO19_IE -// Description : Input enable -#define PADS_BANK0_GPIO19_IE_RESET _u(0x1) -#define PADS_BANK0_GPIO19_IE_BITS _u(0x00000040) -#define PADS_BANK0_GPIO19_IE_MSB _u(6) -#define PADS_BANK0_GPIO19_IE_LSB _u(6) -#define PADS_BANK0_GPIO19_IE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO19_DRIVE -// Description : Drive strength. -// 0x0 -> 2mA -// 0x1 -> 4mA -// 0x2 -> 8mA -// 0x3 -> 12mA -#define PADS_BANK0_GPIO19_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO19_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO19_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO19_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO19_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO19_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO19_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO19_DRIVE_VALUE_8MA _u(0x2) -#define PADS_BANK0_GPIO19_DRIVE_VALUE_12MA _u(0x3) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO19_PUE -// Description : Pull up enable -#define PADS_BANK0_GPIO19_PUE_RESET _u(0x0) -#define PADS_BANK0_GPIO19_PUE_BITS _u(0x00000008) -#define PADS_BANK0_GPIO19_PUE_MSB _u(3) -#define PADS_BANK0_GPIO19_PUE_LSB _u(3) -#define PADS_BANK0_GPIO19_PUE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO19_PDE -// Description : Pull down enable -#define PADS_BANK0_GPIO19_PDE_RESET _u(0x1) -#define PADS_BANK0_GPIO19_PDE_BITS _u(0x00000004) -#define PADS_BANK0_GPIO19_PDE_MSB _u(2) -#define PADS_BANK0_GPIO19_PDE_LSB _u(2) -#define PADS_BANK0_GPIO19_PDE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO19_SCHMITT -// Description : Enable schmitt trigger -#define PADS_BANK0_GPIO19_SCHMITT_RESET _u(0x1) -#define PADS_BANK0_GPIO19_SCHMITT_BITS _u(0x00000002) -#define PADS_BANK0_GPIO19_SCHMITT_MSB _u(1) -#define PADS_BANK0_GPIO19_SCHMITT_LSB _u(1) -#define PADS_BANK0_GPIO19_SCHMITT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO19_SLEWFAST -// Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO19_SLEWFAST_RESET _u(0x0) -#define PADS_BANK0_GPIO19_SLEWFAST_BITS _u(0x00000001) -#define PADS_BANK0_GPIO19_SLEWFAST_MSB _u(0) -#define PADS_BANK0_GPIO19_SLEWFAST_LSB _u(0) -#define PADS_BANK0_GPIO19_SLEWFAST_ACCESS "RW" -// ============================================================================= -// Register : PADS_BANK0_GPIO20 -// Description : Pad control register -#define PADS_BANK0_GPIO20_OFFSET _u(0x00000054) -#define PADS_BANK0_GPIO20_BITS _u(0x000000ff) -#define PADS_BANK0_GPIO20_RESET _u(0x00000056) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO20_OD -// Description : Output disable. Has priority over output enable from -// peripherals -#define PADS_BANK0_GPIO20_OD_RESET _u(0x0) -#define PADS_BANK0_GPIO20_OD_BITS _u(0x00000080) -#define PADS_BANK0_GPIO20_OD_MSB _u(7) -#define PADS_BANK0_GPIO20_OD_LSB _u(7) -#define PADS_BANK0_GPIO20_OD_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO20_IE -// Description : Input enable -#define PADS_BANK0_GPIO20_IE_RESET _u(0x1) -#define PADS_BANK0_GPIO20_IE_BITS _u(0x00000040) -#define PADS_BANK0_GPIO20_IE_MSB _u(6) -#define PADS_BANK0_GPIO20_IE_LSB _u(6) -#define PADS_BANK0_GPIO20_IE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO20_DRIVE -// Description : Drive strength. -// 0x0 -> 2mA -// 0x1 -> 4mA -// 0x2 -> 8mA -// 0x3 -> 12mA -#define PADS_BANK0_GPIO20_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO20_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO20_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO20_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO20_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO20_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO20_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO20_DRIVE_VALUE_8MA _u(0x2) -#define PADS_BANK0_GPIO20_DRIVE_VALUE_12MA _u(0x3) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO20_PUE -// Description : Pull up enable -#define PADS_BANK0_GPIO20_PUE_RESET _u(0x0) -#define PADS_BANK0_GPIO20_PUE_BITS _u(0x00000008) -#define PADS_BANK0_GPIO20_PUE_MSB _u(3) -#define PADS_BANK0_GPIO20_PUE_LSB _u(3) -#define PADS_BANK0_GPIO20_PUE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO20_PDE -// Description : Pull down enable -#define PADS_BANK0_GPIO20_PDE_RESET _u(0x1) -#define PADS_BANK0_GPIO20_PDE_BITS _u(0x00000004) -#define PADS_BANK0_GPIO20_PDE_MSB _u(2) -#define PADS_BANK0_GPIO20_PDE_LSB _u(2) -#define PADS_BANK0_GPIO20_PDE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO20_SCHMITT -// Description : Enable schmitt trigger -#define PADS_BANK0_GPIO20_SCHMITT_RESET _u(0x1) -#define PADS_BANK0_GPIO20_SCHMITT_BITS _u(0x00000002) -#define PADS_BANK0_GPIO20_SCHMITT_MSB _u(1) -#define PADS_BANK0_GPIO20_SCHMITT_LSB _u(1) -#define PADS_BANK0_GPIO20_SCHMITT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO20_SLEWFAST -// Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO20_SLEWFAST_RESET _u(0x0) -#define PADS_BANK0_GPIO20_SLEWFAST_BITS _u(0x00000001) -#define PADS_BANK0_GPIO20_SLEWFAST_MSB _u(0) -#define PADS_BANK0_GPIO20_SLEWFAST_LSB _u(0) -#define PADS_BANK0_GPIO20_SLEWFAST_ACCESS "RW" -// ============================================================================= -// Register : PADS_BANK0_GPIO21 -// Description : Pad control register -#define PADS_BANK0_GPIO21_OFFSET _u(0x00000058) -#define PADS_BANK0_GPIO21_BITS _u(0x000000ff) -#define PADS_BANK0_GPIO21_RESET _u(0x00000056) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO21_OD -// Description : Output disable. Has priority over output enable from -// peripherals -#define PADS_BANK0_GPIO21_OD_RESET _u(0x0) -#define PADS_BANK0_GPIO21_OD_BITS _u(0x00000080) -#define PADS_BANK0_GPIO21_OD_MSB _u(7) -#define PADS_BANK0_GPIO21_OD_LSB _u(7) -#define PADS_BANK0_GPIO21_OD_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO21_IE -// Description : Input enable -#define PADS_BANK0_GPIO21_IE_RESET _u(0x1) -#define PADS_BANK0_GPIO21_IE_BITS _u(0x00000040) -#define PADS_BANK0_GPIO21_IE_MSB _u(6) -#define PADS_BANK0_GPIO21_IE_LSB _u(6) -#define PADS_BANK0_GPIO21_IE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO21_DRIVE -// Description : Drive strength. -// 0x0 -> 2mA -// 0x1 -> 4mA -// 0x2 -> 8mA -// 0x3 -> 12mA -#define PADS_BANK0_GPIO21_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO21_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO21_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO21_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO21_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO21_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO21_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO21_DRIVE_VALUE_8MA _u(0x2) -#define PADS_BANK0_GPIO21_DRIVE_VALUE_12MA _u(0x3) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO21_PUE -// Description : Pull up enable -#define PADS_BANK0_GPIO21_PUE_RESET _u(0x0) -#define PADS_BANK0_GPIO21_PUE_BITS _u(0x00000008) -#define PADS_BANK0_GPIO21_PUE_MSB _u(3) -#define PADS_BANK0_GPIO21_PUE_LSB _u(3) -#define PADS_BANK0_GPIO21_PUE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO21_PDE -// Description : Pull down enable -#define PADS_BANK0_GPIO21_PDE_RESET _u(0x1) -#define PADS_BANK0_GPIO21_PDE_BITS _u(0x00000004) -#define PADS_BANK0_GPIO21_PDE_MSB _u(2) -#define PADS_BANK0_GPIO21_PDE_LSB _u(2) -#define PADS_BANK0_GPIO21_PDE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO21_SCHMITT -// Description : Enable schmitt trigger -#define PADS_BANK0_GPIO21_SCHMITT_RESET _u(0x1) -#define PADS_BANK0_GPIO21_SCHMITT_BITS _u(0x00000002) -#define PADS_BANK0_GPIO21_SCHMITT_MSB _u(1) -#define PADS_BANK0_GPIO21_SCHMITT_LSB _u(1) -#define PADS_BANK0_GPIO21_SCHMITT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO21_SLEWFAST -// Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO21_SLEWFAST_RESET _u(0x0) -#define PADS_BANK0_GPIO21_SLEWFAST_BITS _u(0x00000001) -#define PADS_BANK0_GPIO21_SLEWFAST_MSB _u(0) -#define PADS_BANK0_GPIO21_SLEWFAST_LSB _u(0) -#define PADS_BANK0_GPIO21_SLEWFAST_ACCESS "RW" -// ============================================================================= -// Register : PADS_BANK0_GPIO22 -// Description : Pad control register -#define PADS_BANK0_GPIO22_OFFSET _u(0x0000005c) -#define PADS_BANK0_GPIO22_BITS _u(0x000000ff) -#define PADS_BANK0_GPIO22_RESET _u(0x00000056) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO22_OD -// Description : Output disable. Has priority over output enable from -// peripherals -#define PADS_BANK0_GPIO22_OD_RESET _u(0x0) -#define PADS_BANK0_GPIO22_OD_BITS _u(0x00000080) -#define PADS_BANK0_GPIO22_OD_MSB _u(7) -#define PADS_BANK0_GPIO22_OD_LSB _u(7) -#define PADS_BANK0_GPIO22_OD_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO22_IE -// Description : Input enable -#define PADS_BANK0_GPIO22_IE_RESET _u(0x1) -#define PADS_BANK0_GPIO22_IE_BITS _u(0x00000040) -#define PADS_BANK0_GPIO22_IE_MSB _u(6) -#define PADS_BANK0_GPIO22_IE_LSB _u(6) -#define PADS_BANK0_GPIO22_IE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO22_DRIVE -// Description : Drive strength. -// 0x0 -> 2mA -// 0x1 -> 4mA -// 0x2 -> 8mA -// 0x3 -> 12mA -#define PADS_BANK0_GPIO22_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO22_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO22_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO22_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO22_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO22_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO22_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO22_DRIVE_VALUE_8MA _u(0x2) -#define PADS_BANK0_GPIO22_DRIVE_VALUE_12MA _u(0x3) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO22_PUE -// Description : Pull up enable -#define PADS_BANK0_GPIO22_PUE_RESET _u(0x0) -#define PADS_BANK0_GPIO22_PUE_BITS _u(0x00000008) -#define PADS_BANK0_GPIO22_PUE_MSB _u(3) -#define PADS_BANK0_GPIO22_PUE_LSB _u(3) -#define PADS_BANK0_GPIO22_PUE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO22_PDE -// Description : Pull down enable -#define PADS_BANK0_GPIO22_PDE_RESET _u(0x1) -#define PADS_BANK0_GPIO22_PDE_BITS _u(0x00000004) -#define PADS_BANK0_GPIO22_PDE_MSB _u(2) -#define PADS_BANK0_GPIO22_PDE_LSB _u(2) -#define PADS_BANK0_GPIO22_PDE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO22_SCHMITT -// Description : Enable schmitt trigger -#define PADS_BANK0_GPIO22_SCHMITT_RESET _u(0x1) -#define PADS_BANK0_GPIO22_SCHMITT_BITS _u(0x00000002) -#define PADS_BANK0_GPIO22_SCHMITT_MSB _u(1) -#define PADS_BANK0_GPIO22_SCHMITT_LSB _u(1) -#define PADS_BANK0_GPIO22_SCHMITT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO22_SLEWFAST -// Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO22_SLEWFAST_RESET _u(0x0) -#define PADS_BANK0_GPIO22_SLEWFAST_BITS _u(0x00000001) -#define PADS_BANK0_GPIO22_SLEWFAST_MSB _u(0) -#define PADS_BANK0_GPIO22_SLEWFAST_LSB _u(0) -#define PADS_BANK0_GPIO22_SLEWFAST_ACCESS "RW" -// ============================================================================= -// Register : PADS_BANK0_GPIO23 -// Description : Pad control register -#define PADS_BANK0_GPIO23_OFFSET _u(0x00000060) -#define PADS_BANK0_GPIO23_BITS _u(0x000000ff) -#define PADS_BANK0_GPIO23_RESET _u(0x00000056) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO23_OD -// Description : Output disable. Has priority over output enable from -// peripherals -#define PADS_BANK0_GPIO23_OD_RESET _u(0x0) -#define PADS_BANK0_GPIO23_OD_BITS _u(0x00000080) -#define PADS_BANK0_GPIO23_OD_MSB _u(7) -#define PADS_BANK0_GPIO23_OD_LSB _u(7) -#define PADS_BANK0_GPIO23_OD_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO23_IE -// Description : Input enable -#define PADS_BANK0_GPIO23_IE_RESET _u(0x1) -#define PADS_BANK0_GPIO23_IE_BITS _u(0x00000040) -#define PADS_BANK0_GPIO23_IE_MSB _u(6) -#define PADS_BANK0_GPIO23_IE_LSB _u(6) -#define PADS_BANK0_GPIO23_IE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO23_DRIVE -// Description : Drive strength. -// 0x0 -> 2mA -// 0x1 -> 4mA -// 0x2 -> 8mA -// 0x3 -> 12mA -#define PADS_BANK0_GPIO23_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO23_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO23_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO23_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO23_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO23_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO23_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO23_DRIVE_VALUE_8MA _u(0x2) -#define PADS_BANK0_GPIO23_DRIVE_VALUE_12MA _u(0x3) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO23_PUE -// Description : Pull up enable -#define PADS_BANK0_GPIO23_PUE_RESET _u(0x0) -#define PADS_BANK0_GPIO23_PUE_BITS _u(0x00000008) -#define PADS_BANK0_GPIO23_PUE_MSB _u(3) -#define PADS_BANK0_GPIO23_PUE_LSB _u(3) -#define PADS_BANK0_GPIO23_PUE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO23_PDE -// Description : Pull down enable -#define PADS_BANK0_GPIO23_PDE_RESET _u(0x1) -#define PADS_BANK0_GPIO23_PDE_BITS _u(0x00000004) -#define PADS_BANK0_GPIO23_PDE_MSB _u(2) -#define PADS_BANK0_GPIO23_PDE_LSB _u(2) -#define PADS_BANK0_GPIO23_PDE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO23_SCHMITT -// Description : Enable schmitt trigger -#define PADS_BANK0_GPIO23_SCHMITT_RESET _u(0x1) -#define PADS_BANK0_GPIO23_SCHMITT_BITS _u(0x00000002) -#define PADS_BANK0_GPIO23_SCHMITT_MSB _u(1) -#define PADS_BANK0_GPIO23_SCHMITT_LSB _u(1) -#define PADS_BANK0_GPIO23_SCHMITT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO23_SLEWFAST -// Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO23_SLEWFAST_RESET _u(0x0) -#define PADS_BANK0_GPIO23_SLEWFAST_BITS _u(0x00000001) -#define PADS_BANK0_GPIO23_SLEWFAST_MSB _u(0) -#define PADS_BANK0_GPIO23_SLEWFAST_LSB _u(0) -#define PADS_BANK0_GPIO23_SLEWFAST_ACCESS "RW" -// ============================================================================= -// Register : PADS_BANK0_GPIO24 -// Description : Pad control register -#define PADS_BANK0_GPIO24_OFFSET _u(0x00000064) -#define PADS_BANK0_GPIO24_BITS _u(0x000000ff) -#define PADS_BANK0_GPIO24_RESET _u(0x00000056) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO24_OD -// Description : Output disable. Has priority over output enable from -// peripherals -#define PADS_BANK0_GPIO24_OD_RESET _u(0x0) -#define PADS_BANK0_GPIO24_OD_BITS _u(0x00000080) -#define PADS_BANK0_GPIO24_OD_MSB _u(7) -#define PADS_BANK0_GPIO24_OD_LSB _u(7) -#define PADS_BANK0_GPIO24_OD_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO24_IE -// Description : Input enable -#define PADS_BANK0_GPIO24_IE_RESET _u(0x1) -#define PADS_BANK0_GPIO24_IE_BITS _u(0x00000040) -#define PADS_BANK0_GPIO24_IE_MSB _u(6) -#define PADS_BANK0_GPIO24_IE_LSB _u(6) -#define PADS_BANK0_GPIO24_IE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO24_DRIVE -// Description : Drive strength. -// 0x0 -> 2mA -// 0x1 -> 4mA -// 0x2 -> 8mA -// 0x3 -> 12mA -#define PADS_BANK0_GPIO24_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO24_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO24_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO24_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO24_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO24_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO24_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO24_DRIVE_VALUE_8MA _u(0x2) -#define PADS_BANK0_GPIO24_DRIVE_VALUE_12MA _u(0x3) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO24_PUE -// Description : Pull up enable -#define PADS_BANK0_GPIO24_PUE_RESET _u(0x0) -#define PADS_BANK0_GPIO24_PUE_BITS _u(0x00000008) -#define PADS_BANK0_GPIO24_PUE_MSB _u(3) -#define PADS_BANK0_GPIO24_PUE_LSB _u(3) -#define PADS_BANK0_GPIO24_PUE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO24_PDE -// Description : Pull down enable -#define PADS_BANK0_GPIO24_PDE_RESET _u(0x1) -#define PADS_BANK0_GPIO24_PDE_BITS _u(0x00000004) -#define PADS_BANK0_GPIO24_PDE_MSB _u(2) -#define PADS_BANK0_GPIO24_PDE_LSB _u(2) -#define PADS_BANK0_GPIO24_PDE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO24_SCHMITT -// Description : Enable schmitt trigger -#define PADS_BANK0_GPIO24_SCHMITT_RESET _u(0x1) -#define PADS_BANK0_GPIO24_SCHMITT_BITS _u(0x00000002) -#define PADS_BANK0_GPIO24_SCHMITT_MSB _u(1) -#define PADS_BANK0_GPIO24_SCHMITT_LSB _u(1) -#define PADS_BANK0_GPIO24_SCHMITT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO24_SLEWFAST -// Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO24_SLEWFAST_RESET _u(0x0) -#define PADS_BANK0_GPIO24_SLEWFAST_BITS _u(0x00000001) -#define PADS_BANK0_GPIO24_SLEWFAST_MSB _u(0) -#define PADS_BANK0_GPIO24_SLEWFAST_LSB _u(0) -#define PADS_BANK0_GPIO24_SLEWFAST_ACCESS "RW" -// ============================================================================= -// Register : PADS_BANK0_GPIO25 -// Description : Pad control register -#define PADS_BANK0_GPIO25_OFFSET _u(0x00000068) -#define PADS_BANK0_GPIO25_BITS _u(0x000000ff) -#define PADS_BANK0_GPIO25_RESET _u(0x00000056) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO25_OD -// Description : Output disable. Has priority over output enable from -// peripherals -#define PADS_BANK0_GPIO25_OD_RESET _u(0x0) -#define PADS_BANK0_GPIO25_OD_BITS _u(0x00000080) -#define PADS_BANK0_GPIO25_OD_MSB _u(7) -#define PADS_BANK0_GPIO25_OD_LSB _u(7) -#define PADS_BANK0_GPIO25_OD_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO25_IE -// Description : Input enable -#define PADS_BANK0_GPIO25_IE_RESET _u(0x1) -#define PADS_BANK0_GPIO25_IE_BITS _u(0x00000040) -#define PADS_BANK0_GPIO25_IE_MSB _u(6) -#define PADS_BANK0_GPIO25_IE_LSB _u(6) -#define PADS_BANK0_GPIO25_IE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO25_DRIVE -// Description : Drive strength. -// 0x0 -> 2mA -// 0x1 -> 4mA -// 0x2 -> 8mA -// 0x3 -> 12mA -#define PADS_BANK0_GPIO25_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO25_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO25_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO25_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO25_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO25_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO25_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO25_DRIVE_VALUE_8MA _u(0x2) -#define PADS_BANK0_GPIO25_DRIVE_VALUE_12MA _u(0x3) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO25_PUE -// Description : Pull up enable -#define PADS_BANK0_GPIO25_PUE_RESET _u(0x0) -#define PADS_BANK0_GPIO25_PUE_BITS _u(0x00000008) -#define PADS_BANK0_GPIO25_PUE_MSB _u(3) -#define PADS_BANK0_GPIO25_PUE_LSB _u(3) -#define PADS_BANK0_GPIO25_PUE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO25_PDE -// Description : Pull down enable -#define PADS_BANK0_GPIO25_PDE_RESET _u(0x1) -#define PADS_BANK0_GPIO25_PDE_BITS _u(0x00000004) -#define PADS_BANK0_GPIO25_PDE_MSB _u(2) -#define PADS_BANK0_GPIO25_PDE_LSB _u(2) -#define PADS_BANK0_GPIO25_PDE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO25_SCHMITT -// Description : Enable schmitt trigger -#define PADS_BANK0_GPIO25_SCHMITT_RESET _u(0x1) -#define PADS_BANK0_GPIO25_SCHMITT_BITS _u(0x00000002) -#define PADS_BANK0_GPIO25_SCHMITT_MSB _u(1) -#define PADS_BANK0_GPIO25_SCHMITT_LSB _u(1) -#define PADS_BANK0_GPIO25_SCHMITT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO25_SLEWFAST -// Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO25_SLEWFAST_RESET _u(0x0) -#define PADS_BANK0_GPIO25_SLEWFAST_BITS _u(0x00000001) -#define PADS_BANK0_GPIO25_SLEWFAST_MSB _u(0) -#define PADS_BANK0_GPIO25_SLEWFAST_LSB _u(0) -#define PADS_BANK0_GPIO25_SLEWFAST_ACCESS "RW" -// ============================================================================= -// Register : PADS_BANK0_GPIO26 -// Description : Pad control register -#define PADS_BANK0_GPIO26_OFFSET _u(0x0000006c) -#define PADS_BANK0_GPIO26_BITS _u(0x000000ff) -#define PADS_BANK0_GPIO26_RESET _u(0x00000056) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO26_OD -// Description : Output disable. Has priority over output enable from -// peripherals -#define PADS_BANK0_GPIO26_OD_RESET _u(0x0) -#define PADS_BANK0_GPIO26_OD_BITS _u(0x00000080) -#define PADS_BANK0_GPIO26_OD_MSB _u(7) -#define PADS_BANK0_GPIO26_OD_LSB _u(7) -#define PADS_BANK0_GPIO26_OD_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO26_IE -// Description : Input enable -#define PADS_BANK0_GPIO26_IE_RESET _u(0x1) -#define PADS_BANK0_GPIO26_IE_BITS _u(0x00000040) -#define PADS_BANK0_GPIO26_IE_MSB _u(6) -#define PADS_BANK0_GPIO26_IE_LSB _u(6) -#define PADS_BANK0_GPIO26_IE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO26_DRIVE -// Description : Drive strength. -// 0x0 -> 2mA -// 0x1 -> 4mA -// 0x2 -> 8mA -// 0x3 -> 12mA -#define PADS_BANK0_GPIO26_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO26_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO26_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO26_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO26_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO26_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO26_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO26_DRIVE_VALUE_8MA _u(0x2) -#define PADS_BANK0_GPIO26_DRIVE_VALUE_12MA _u(0x3) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO26_PUE -// Description : Pull up enable -#define PADS_BANK0_GPIO26_PUE_RESET _u(0x0) -#define PADS_BANK0_GPIO26_PUE_BITS _u(0x00000008) -#define PADS_BANK0_GPIO26_PUE_MSB _u(3) -#define PADS_BANK0_GPIO26_PUE_LSB _u(3) -#define PADS_BANK0_GPIO26_PUE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO26_PDE -// Description : Pull down enable -#define PADS_BANK0_GPIO26_PDE_RESET _u(0x1) -#define PADS_BANK0_GPIO26_PDE_BITS _u(0x00000004) -#define PADS_BANK0_GPIO26_PDE_MSB _u(2) -#define PADS_BANK0_GPIO26_PDE_LSB _u(2) -#define PADS_BANK0_GPIO26_PDE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO26_SCHMITT -// Description : Enable schmitt trigger -#define PADS_BANK0_GPIO26_SCHMITT_RESET _u(0x1) -#define PADS_BANK0_GPIO26_SCHMITT_BITS _u(0x00000002) -#define PADS_BANK0_GPIO26_SCHMITT_MSB _u(1) -#define PADS_BANK0_GPIO26_SCHMITT_LSB _u(1) -#define PADS_BANK0_GPIO26_SCHMITT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO26_SLEWFAST -// Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO26_SLEWFAST_RESET _u(0x0) -#define PADS_BANK0_GPIO26_SLEWFAST_BITS _u(0x00000001) -#define PADS_BANK0_GPIO26_SLEWFAST_MSB _u(0) -#define PADS_BANK0_GPIO26_SLEWFAST_LSB _u(0) -#define PADS_BANK0_GPIO26_SLEWFAST_ACCESS "RW" -// ============================================================================= -// Register : PADS_BANK0_GPIO27 -// Description : Pad control register -#define PADS_BANK0_GPIO27_OFFSET _u(0x00000070) -#define PADS_BANK0_GPIO27_BITS _u(0x000000ff) -#define PADS_BANK0_GPIO27_RESET _u(0x00000056) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO27_OD -// Description : Output disable. Has priority over output enable from -// peripherals -#define PADS_BANK0_GPIO27_OD_RESET _u(0x0) -#define PADS_BANK0_GPIO27_OD_BITS _u(0x00000080) -#define PADS_BANK0_GPIO27_OD_MSB _u(7) -#define PADS_BANK0_GPIO27_OD_LSB _u(7) -#define PADS_BANK0_GPIO27_OD_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO27_IE -// Description : Input enable -#define PADS_BANK0_GPIO27_IE_RESET _u(0x1) -#define PADS_BANK0_GPIO27_IE_BITS _u(0x00000040) -#define PADS_BANK0_GPIO27_IE_MSB _u(6) -#define PADS_BANK0_GPIO27_IE_LSB _u(6) -#define PADS_BANK0_GPIO27_IE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO27_DRIVE -// Description : Drive strength. -// 0x0 -> 2mA -// 0x1 -> 4mA -// 0x2 -> 8mA -// 0x3 -> 12mA -#define PADS_BANK0_GPIO27_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO27_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO27_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO27_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO27_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO27_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO27_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO27_DRIVE_VALUE_8MA _u(0x2) -#define PADS_BANK0_GPIO27_DRIVE_VALUE_12MA _u(0x3) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO27_PUE -// Description : Pull up enable -#define PADS_BANK0_GPIO27_PUE_RESET _u(0x0) -#define PADS_BANK0_GPIO27_PUE_BITS _u(0x00000008) -#define PADS_BANK0_GPIO27_PUE_MSB _u(3) -#define PADS_BANK0_GPIO27_PUE_LSB _u(3) -#define PADS_BANK0_GPIO27_PUE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO27_PDE -// Description : Pull down enable -#define PADS_BANK0_GPIO27_PDE_RESET _u(0x1) -#define PADS_BANK0_GPIO27_PDE_BITS _u(0x00000004) -#define PADS_BANK0_GPIO27_PDE_MSB _u(2) -#define PADS_BANK0_GPIO27_PDE_LSB _u(2) -#define PADS_BANK0_GPIO27_PDE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO27_SCHMITT -// Description : Enable schmitt trigger -#define PADS_BANK0_GPIO27_SCHMITT_RESET _u(0x1) -#define PADS_BANK0_GPIO27_SCHMITT_BITS _u(0x00000002) -#define PADS_BANK0_GPIO27_SCHMITT_MSB _u(1) -#define PADS_BANK0_GPIO27_SCHMITT_LSB _u(1) -#define PADS_BANK0_GPIO27_SCHMITT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO27_SLEWFAST -// Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO27_SLEWFAST_RESET _u(0x0) -#define PADS_BANK0_GPIO27_SLEWFAST_BITS _u(0x00000001) -#define PADS_BANK0_GPIO27_SLEWFAST_MSB _u(0) -#define PADS_BANK0_GPIO27_SLEWFAST_LSB _u(0) -#define PADS_BANK0_GPIO27_SLEWFAST_ACCESS "RW" -// ============================================================================= -// Register : PADS_BANK0_GPIO28 -// Description : Pad control register -#define PADS_BANK0_GPIO28_OFFSET _u(0x00000074) -#define PADS_BANK0_GPIO28_BITS _u(0x000000ff) -#define PADS_BANK0_GPIO28_RESET _u(0x00000056) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO28_OD -// Description : Output disable. Has priority over output enable from -// peripherals -#define PADS_BANK0_GPIO28_OD_RESET _u(0x0) -#define PADS_BANK0_GPIO28_OD_BITS _u(0x00000080) -#define PADS_BANK0_GPIO28_OD_MSB _u(7) -#define PADS_BANK0_GPIO28_OD_LSB _u(7) -#define PADS_BANK0_GPIO28_OD_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO28_IE -// Description : Input enable -#define PADS_BANK0_GPIO28_IE_RESET _u(0x1) -#define PADS_BANK0_GPIO28_IE_BITS _u(0x00000040) -#define PADS_BANK0_GPIO28_IE_MSB _u(6) -#define PADS_BANK0_GPIO28_IE_LSB _u(6) -#define PADS_BANK0_GPIO28_IE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO28_DRIVE -// Description : Drive strength. -// 0x0 -> 2mA -// 0x1 -> 4mA -// 0x2 -> 8mA -// 0x3 -> 12mA -#define PADS_BANK0_GPIO28_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO28_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO28_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO28_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO28_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO28_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO28_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO28_DRIVE_VALUE_8MA _u(0x2) -#define PADS_BANK0_GPIO28_DRIVE_VALUE_12MA _u(0x3) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO28_PUE -// Description : Pull up enable -#define PADS_BANK0_GPIO28_PUE_RESET _u(0x0) -#define PADS_BANK0_GPIO28_PUE_BITS _u(0x00000008) -#define PADS_BANK0_GPIO28_PUE_MSB _u(3) -#define PADS_BANK0_GPIO28_PUE_LSB _u(3) -#define PADS_BANK0_GPIO28_PUE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO28_PDE -// Description : Pull down enable -#define PADS_BANK0_GPIO28_PDE_RESET _u(0x1) -#define PADS_BANK0_GPIO28_PDE_BITS _u(0x00000004) -#define PADS_BANK0_GPIO28_PDE_MSB _u(2) -#define PADS_BANK0_GPIO28_PDE_LSB _u(2) -#define PADS_BANK0_GPIO28_PDE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO28_SCHMITT -// Description : Enable schmitt trigger -#define PADS_BANK0_GPIO28_SCHMITT_RESET _u(0x1) -#define PADS_BANK0_GPIO28_SCHMITT_BITS _u(0x00000002) -#define PADS_BANK0_GPIO28_SCHMITT_MSB _u(1) -#define PADS_BANK0_GPIO28_SCHMITT_LSB _u(1) -#define PADS_BANK0_GPIO28_SCHMITT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO28_SLEWFAST -// Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO28_SLEWFAST_RESET _u(0x0) -#define PADS_BANK0_GPIO28_SLEWFAST_BITS _u(0x00000001) -#define PADS_BANK0_GPIO28_SLEWFAST_MSB _u(0) -#define PADS_BANK0_GPIO28_SLEWFAST_LSB _u(0) -#define PADS_BANK0_GPIO28_SLEWFAST_ACCESS "RW" -// ============================================================================= -// Register : PADS_BANK0_GPIO29 -// Description : Pad control register -#define PADS_BANK0_GPIO29_OFFSET _u(0x00000078) -#define PADS_BANK0_GPIO29_BITS _u(0x000000ff) -#define PADS_BANK0_GPIO29_RESET _u(0x00000056) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO29_OD -// Description : Output disable. Has priority over output enable from -// peripherals -#define PADS_BANK0_GPIO29_OD_RESET _u(0x0) -#define PADS_BANK0_GPIO29_OD_BITS _u(0x00000080) -#define PADS_BANK0_GPIO29_OD_MSB _u(7) -#define PADS_BANK0_GPIO29_OD_LSB _u(7) -#define PADS_BANK0_GPIO29_OD_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO29_IE -// Description : Input enable -#define PADS_BANK0_GPIO29_IE_RESET _u(0x1) -#define PADS_BANK0_GPIO29_IE_BITS _u(0x00000040) -#define PADS_BANK0_GPIO29_IE_MSB _u(6) -#define PADS_BANK0_GPIO29_IE_LSB _u(6) -#define PADS_BANK0_GPIO29_IE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO29_DRIVE -// Description : Drive strength. -// 0x0 -> 2mA -// 0x1 -> 4mA -// 0x2 -> 8mA -// 0x3 -> 12mA -#define PADS_BANK0_GPIO29_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO29_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO29_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO29_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO29_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO29_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO29_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO29_DRIVE_VALUE_8MA _u(0x2) -#define PADS_BANK0_GPIO29_DRIVE_VALUE_12MA _u(0x3) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO29_PUE -// Description : Pull up enable -#define PADS_BANK0_GPIO29_PUE_RESET _u(0x0) -#define PADS_BANK0_GPIO29_PUE_BITS _u(0x00000008) -#define PADS_BANK0_GPIO29_PUE_MSB _u(3) -#define PADS_BANK0_GPIO29_PUE_LSB _u(3) -#define PADS_BANK0_GPIO29_PUE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO29_PDE -// Description : Pull down enable -#define PADS_BANK0_GPIO29_PDE_RESET _u(0x1) -#define PADS_BANK0_GPIO29_PDE_BITS _u(0x00000004) -#define PADS_BANK0_GPIO29_PDE_MSB _u(2) -#define PADS_BANK0_GPIO29_PDE_LSB _u(2) -#define PADS_BANK0_GPIO29_PDE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO29_SCHMITT -// Description : Enable schmitt trigger -#define PADS_BANK0_GPIO29_SCHMITT_RESET _u(0x1) -#define PADS_BANK0_GPIO29_SCHMITT_BITS _u(0x00000002) -#define PADS_BANK0_GPIO29_SCHMITT_MSB _u(1) -#define PADS_BANK0_GPIO29_SCHMITT_LSB _u(1) -#define PADS_BANK0_GPIO29_SCHMITT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO29_SLEWFAST -// Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO29_SLEWFAST_RESET _u(0x0) -#define PADS_BANK0_GPIO29_SLEWFAST_BITS _u(0x00000001) -#define PADS_BANK0_GPIO29_SLEWFAST_MSB _u(0) -#define PADS_BANK0_GPIO29_SLEWFAST_LSB _u(0) -#define PADS_BANK0_GPIO29_SLEWFAST_ACCESS "RW" -// ============================================================================= -// Register : PADS_BANK0_SWCLK -// Description : Pad control register -#define PADS_BANK0_SWCLK_OFFSET _u(0x0000007c) -#define PADS_BANK0_SWCLK_BITS _u(0x000000ff) -#define PADS_BANK0_SWCLK_RESET _u(0x000000da) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_SWCLK_OD -// Description : Output disable. Has priority over output enable from -// peripherals -#define PADS_BANK0_SWCLK_OD_RESET _u(0x1) -#define PADS_BANK0_SWCLK_OD_BITS _u(0x00000080) -#define PADS_BANK0_SWCLK_OD_MSB _u(7) -#define PADS_BANK0_SWCLK_OD_LSB _u(7) -#define PADS_BANK0_SWCLK_OD_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_SWCLK_IE -// Description : Input enable -#define PADS_BANK0_SWCLK_IE_RESET _u(0x1) -#define PADS_BANK0_SWCLK_IE_BITS _u(0x00000040) -#define PADS_BANK0_SWCLK_IE_MSB _u(6) -#define PADS_BANK0_SWCLK_IE_LSB _u(6) -#define PADS_BANK0_SWCLK_IE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_SWCLK_DRIVE -// Description : Drive strength. -// 0x0 -> 2mA -// 0x1 -> 4mA -// 0x2 -> 8mA -// 0x3 -> 12mA -#define PADS_BANK0_SWCLK_DRIVE_RESET _u(0x1) -#define PADS_BANK0_SWCLK_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_SWCLK_DRIVE_MSB _u(5) -#define PADS_BANK0_SWCLK_DRIVE_LSB _u(4) -#define PADS_BANK0_SWCLK_DRIVE_ACCESS "RW" -#define PADS_BANK0_SWCLK_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_SWCLK_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_SWCLK_DRIVE_VALUE_8MA _u(0x2) -#define PADS_BANK0_SWCLK_DRIVE_VALUE_12MA _u(0x3) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_SWCLK_PUE -// Description : Pull up enable -#define PADS_BANK0_SWCLK_PUE_RESET _u(0x1) -#define PADS_BANK0_SWCLK_PUE_BITS _u(0x00000008) -#define PADS_BANK0_SWCLK_PUE_MSB _u(3) -#define PADS_BANK0_SWCLK_PUE_LSB _u(3) -#define PADS_BANK0_SWCLK_PUE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_SWCLK_PDE -// Description : Pull down enable -#define PADS_BANK0_SWCLK_PDE_RESET _u(0x0) -#define PADS_BANK0_SWCLK_PDE_BITS _u(0x00000004) -#define PADS_BANK0_SWCLK_PDE_MSB _u(2) -#define PADS_BANK0_SWCLK_PDE_LSB _u(2) -#define PADS_BANK0_SWCLK_PDE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_SWCLK_SCHMITT -// Description : Enable schmitt trigger -#define PADS_BANK0_SWCLK_SCHMITT_RESET _u(0x1) -#define PADS_BANK0_SWCLK_SCHMITT_BITS _u(0x00000002) -#define PADS_BANK0_SWCLK_SCHMITT_MSB _u(1) -#define PADS_BANK0_SWCLK_SCHMITT_LSB _u(1) -#define PADS_BANK0_SWCLK_SCHMITT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_SWCLK_SLEWFAST -// Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_SWCLK_SLEWFAST_RESET _u(0x0) -#define PADS_BANK0_SWCLK_SLEWFAST_BITS _u(0x00000001) -#define PADS_BANK0_SWCLK_SLEWFAST_MSB _u(0) -#define PADS_BANK0_SWCLK_SLEWFAST_LSB _u(0) -#define PADS_BANK0_SWCLK_SLEWFAST_ACCESS "RW" -// ============================================================================= -// Register : PADS_BANK0_SWD -// Description : Pad control register -#define PADS_BANK0_SWD_OFFSET _u(0x00000080) -#define PADS_BANK0_SWD_BITS _u(0x000000ff) -#define PADS_BANK0_SWD_RESET _u(0x0000005a) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_SWD_OD -// Description : Output disable. Has priority over output enable from -// peripherals -#define PADS_BANK0_SWD_OD_RESET _u(0x0) -#define PADS_BANK0_SWD_OD_BITS _u(0x00000080) -#define PADS_BANK0_SWD_OD_MSB _u(7) -#define PADS_BANK0_SWD_OD_LSB _u(7) -#define PADS_BANK0_SWD_OD_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_SWD_IE -// Description : Input enable -#define PADS_BANK0_SWD_IE_RESET _u(0x1) -#define PADS_BANK0_SWD_IE_BITS _u(0x00000040) -#define PADS_BANK0_SWD_IE_MSB _u(6) -#define PADS_BANK0_SWD_IE_LSB _u(6) -#define PADS_BANK0_SWD_IE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_SWD_DRIVE -// Description : Drive strength. -// 0x0 -> 2mA -// 0x1 -> 4mA -// 0x2 -> 8mA -// 0x3 -> 12mA -#define PADS_BANK0_SWD_DRIVE_RESET _u(0x1) -#define PADS_BANK0_SWD_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_SWD_DRIVE_MSB _u(5) -#define PADS_BANK0_SWD_DRIVE_LSB _u(4) -#define PADS_BANK0_SWD_DRIVE_ACCESS "RW" -#define PADS_BANK0_SWD_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_SWD_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_SWD_DRIVE_VALUE_8MA _u(0x2) -#define PADS_BANK0_SWD_DRIVE_VALUE_12MA _u(0x3) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_SWD_PUE -// Description : Pull up enable -#define PADS_BANK0_SWD_PUE_RESET _u(0x1) -#define PADS_BANK0_SWD_PUE_BITS _u(0x00000008) -#define PADS_BANK0_SWD_PUE_MSB _u(3) -#define PADS_BANK0_SWD_PUE_LSB _u(3) -#define PADS_BANK0_SWD_PUE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_SWD_PDE -// Description : Pull down enable -#define PADS_BANK0_SWD_PDE_RESET _u(0x0) -#define PADS_BANK0_SWD_PDE_BITS _u(0x00000004) -#define PADS_BANK0_SWD_PDE_MSB _u(2) -#define PADS_BANK0_SWD_PDE_LSB _u(2) -#define PADS_BANK0_SWD_PDE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_SWD_SCHMITT -// Description : Enable schmitt trigger -#define PADS_BANK0_SWD_SCHMITT_RESET _u(0x1) -#define PADS_BANK0_SWD_SCHMITT_BITS _u(0x00000002) -#define PADS_BANK0_SWD_SCHMITT_MSB _u(1) -#define PADS_BANK0_SWD_SCHMITT_LSB _u(1) -#define PADS_BANK0_SWD_SCHMITT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_SWD_SLEWFAST -// Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_SWD_SLEWFAST_RESET _u(0x0) -#define PADS_BANK0_SWD_SLEWFAST_BITS _u(0x00000001) -#define PADS_BANK0_SWD_SLEWFAST_MSB _u(0) -#define PADS_BANK0_SWD_SLEWFAST_LSB _u(0) -#define PADS_BANK0_SWD_SLEWFAST_ACCESS "RW" -// ============================================================================= -#endif // _HARDWARE_REGS_PADS_BANK0_H - diff --git a/lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/pads_qspi.h b/lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/pads_qspi.h deleted file mode 100644 index 4cd27ea7c0..0000000000 --- a/lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/pads_qspi.h +++ /dev/null @@ -1,456 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -// ============================================================================= -// Register block : PADS_QSPI -// Version : 1 -// Bus type : apb -// ============================================================================= -#ifndef _HARDWARE_REGS_PADS_QSPI_H -#define _HARDWARE_REGS_PADS_QSPI_H -// ============================================================================= -// Register : PADS_QSPI_VOLTAGE_SELECT -// Description : Voltage select. Per bank control -// 0x0 -> Set voltage to 3.3V (DVDD >= 2V5) -// 0x1 -> Set voltage to 1.8V (DVDD <= 1V8) -#define PADS_QSPI_VOLTAGE_SELECT_OFFSET _u(0x00000000) -#define PADS_QSPI_VOLTAGE_SELECT_BITS _u(0x00000001) -#define PADS_QSPI_VOLTAGE_SELECT_RESET _u(0x00000000) -#define PADS_QSPI_VOLTAGE_SELECT_MSB _u(0) -#define PADS_QSPI_VOLTAGE_SELECT_LSB _u(0) -#define PADS_QSPI_VOLTAGE_SELECT_ACCESS "RW" -#define PADS_QSPI_VOLTAGE_SELECT_VALUE_3V3 _u(0x0) -#define PADS_QSPI_VOLTAGE_SELECT_VALUE_1V8 _u(0x1) -// ============================================================================= -// Register : PADS_QSPI_GPIO_QSPI_SCLK -// Description : Pad control register -#define PADS_QSPI_GPIO_QSPI_SCLK_OFFSET _u(0x00000004) -#define PADS_QSPI_GPIO_QSPI_SCLK_BITS _u(0x000000ff) -#define PADS_QSPI_GPIO_QSPI_SCLK_RESET _u(0x00000056) -// ----------------------------------------------------------------------------- -// Field : PADS_QSPI_GPIO_QSPI_SCLK_OD -// Description : Output disable. Has priority over output enable from -// peripherals -#define PADS_QSPI_GPIO_QSPI_SCLK_OD_RESET _u(0x0) -#define PADS_QSPI_GPIO_QSPI_SCLK_OD_BITS _u(0x00000080) -#define PADS_QSPI_GPIO_QSPI_SCLK_OD_MSB _u(7) -#define PADS_QSPI_GPIO_QSPI_SCLK_OD_LSB _u(7) -#define PADS_QSPI_GPIO_QSPI_SCLK_OD_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_QSPI_GPIO_QSPI_SCLK_IE -// Description : Input enable -#define PADS_QSPI_GPIO_QSPI_SCLK_IE_RESET _u(0x1) -#define PADS_QSPI_GPIO_QSPI_SCLK_IE_BITS _u(0x00000040) -#define PADS_QSPI_GPIO_QSPI_SCLK_IE_MSB _u(6) -#define PADS_QSPI_GPIO_QSPI_SCLK_IE_LSB _u(6) -#define PADS_QSPI_GPIO_QSPI_SCLK_IE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_QSPI_GPIO_QSPI_SCLK_DRIVE -// Description : Drive strength. -// 0x0 -> 2mA -// 0x1 -> 4mA -// 0x2 -> 8mA -// 0x3 -> 12mA -#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_RESET _u(0x1) -#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_BITS _u(0x00000030) -#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_MSB _u(5) -#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_LSB _u(4) -#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_ACCESS "RW" -#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_VALUE_2MA _u(0x0) -#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_VALUE_4MA _u(0x1) -#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_VALUE_8MA _u(0x2) -#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_VALUE_12MA _u(0x3) -// ----------------------------------------------------------------------------- -// Field : PADS_QSPI_GPIO_QSPI_SCLK_PUE -// Description : Pull up enable -#define PADS_QSPI_GPIO_QSPI_SCLK_PUE_RESET _u(0x0) -#define PADS_QSPI_GPIO_QSPI_SCLK_PUE_BITS _u(0x00000008) -#define PADS_QSPI_GPIO_QSPI_SCLK_PUE_MSB _u(3) -#define PADS_QSPI_GPIO_QSPI_SCLK_PUE_LSB _u(3) -#define PADS_QSPI_GPIO_QSPI_SCLK_PUE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_QSPI_GPIO_QSPI_SCLK_PDE -// Description : Pull down enable -#define PADS_QSPI_GPIO_QSPI_SCLK_PDE_RESET _u(0x1) -#define PADS_QSPI_GPIO_QSPI_SCLK_PDE_BITS _u(0x00000004) -#define PADS_QSPI_GPIO_QSPI_SCLK_PDE_MSB _u(2) -#define PADS_QSPI_GPIO_QSPI_SCLK_PDE_LSB _u(2) -#define PADS_QSPI_GPIO_QSPI_SCLK_PDE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT -// Description : Enable schmitt trigger -#define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_RESET _u(0x1) -#define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_BITS _u(0x00000002) -#define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_MSB _u(1) -#define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_LSB _u(1) -#define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST -// Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_RESET _u(0x0) -#define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_BITS _u(0x00000001) -#define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_MSB _u(0) -#define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_LSB _u(0) -#define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_ACCESS "RW" -// ============================================================================= -// Register : PADS_QSPI_GPIO_QSPI_SD0 -// Description : Pad control register -#define PADS_QSPI_GPIO_QSPI_SD0_OFFSET _u(0x00000008) -#define PADS_QSPI_GPIO_QSPI_SD0_BITS _u(0x000000ff) -#define PADS_QSPI_GPIO_QSPI_SD0_RESET _u(0x00000052) -// ----------------------------------------------------------------------------- -// Field : PADS_QSPI_GPIO_QSPI_SD0_OD -// Description : Output disable. Has priority over output enable from -// peripherals -#define PADS_QSPI_GPIO_QSPI_SD0_OD_RESET _u(0x0) -#define PADS_QSPI_GPIO_QSPI_SD0_OD_BITS _u(0x00000080) -#define PADS_QSPI_GPIO_QSPI_SD0_OD_MSB _u(7) -#define PADS_QSPI_GPIO_QSPI_SD0_OD_LSB _u(7) -#define PADS_QSPI_GPIO_QSPI_SD0_OD_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_QSPI_GPIO_QSPI_SD0_IE -// Description : Input enable -#define PADS_QSPI_GPIO_QSPI_SD0_IE_RESET _u(0x1) -#define PADS_QSPI_GPIO_QSPI_SD0_IE_BITS _u(0x00000040) -#define PADS_QSPI_GPIO_QSPI_SD0_IE_MSB _u(6) -#define PADS_QSPI_GPIO_QSPI_SD0_IE_LSB _u(6) -#define PADS_QSPI_GPIO_QSPI_SD0_IE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_QSPI_GPIO_QSPI_SD0_DRIVE -// Description : Drive strength. -// 0x0 -> 2mA -// 0x1 -> 4mA -// 0x2 -> 8mA -// 0x3 -> 12mA -#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_RESET _u(0x1) -#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_BITS _u(0x00000030) -#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_MSB _u(5) -#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_LSB _u(4) -#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_ACCESS "RW" -#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_VALUE_2MA _u(0x0) -#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_VALUE_4MA _u(0x1) -#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_VALUE_8MA _u(0x2) -#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_VALUE_12MA _u(0x3) -// ----------------------------------------------------------------------------- -// Field : PADS_QSPI_GPIO_QSPI_SD0_PUE -// Description : Pull up enable -#define PADS_QSPI_GPIO_QSPI_SD0_PUE_RESET _u(0x0) -#define PADS_QSPI_GPIO_QSPI_SD0_PUE_BITS _u(0x00000008) -#define PADS_QSPI_GPIO_QSPI_SD0_PUE_MSB _u(3) -#define PADS_QSPI_GPIO_QSPI_SD0_PUE_LSB _u(3) -#define PADS_QSPI_GPIO_QSPI_SD0_PUE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_QSPI_GPIO_QSPI_SD0_PDE -// Description : Pull down enable -#define PADS_QSPI_GPIO_QSPI_SD0_PDE_RESET _u(0x0) -#define PADS_QSPI_GPIO_QSPI_SD0_PDE_BITS _u(0x00000004) -#define PADS_QSPI_GPIO_QSPI_SD0_PDE_MSB _u(2) -#define PADS_QSPI_GPIO_QSPI_SD0_PDE_LSB _u(2) -#define PADS_QSPI_GPIO_QSPI_SD0_PDE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_QSPI_GPIO_QSPI_SD0_SCHMITT -// Description : Enable schmitt trigger -#define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_RESET _u(0x1) -#define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_BITS _u(0x00000002) -#define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_MSB _u(1) -#define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_LSB _u(1) -#define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST -// Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_RESET _u(0x0) -#define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_BITS _u(0x00000001) -#define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_MSB _u(0) -#define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_LSB _u(0) -#define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_ACCESS "RW" -// ============================================================================= -// Register : PADS_QSPI_GPIO_QSPI_SD1 -// Description : Pad control register -#define PADS_QSPI_GPIO_QSPI_SD1_OFFSET _u(0x0000000c) -#define PADS_QSPI_GPIO_QSPI_SD1_BITS _u(0x000000ff) -#define PADS_QSPI_GPIO_QSPI_SD1_RESET _u(0x00000052) -// ----------------------------------------------------------------------------- -// Field : PADS_QSPI_GPIO_QSPI_SD1_OD -// Description : Output disable. Has priority over output enable from -// peripherals -#define PADS_QSPI_GPIO_QSPI_SD1_OD_RESET _u(0x0) -#define PADS_QSPI_GPIO_QSPI_SD1_OD_BITS _u(0x00000080) -#define PADS_QSPI_GPIO_QSPI_SD1_OD_MSB _u(7) -#define PADS_QSPI_GPIO_QSPI_SD1_OD_LSB _u(7) -#define PADS_QSPI_GPIO_QSPI_SD1_OD_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_QSPI_GPIO_QSPI_SD1_IE -// Description : Input enable -#define PADS_QSPI_GPIO_QSPI_SD1_IE_RESET _u(0x1) -#define PADS_QSPI_GPIO_QSPI_SD1_IE_BITS _u(0x00000040) -#define PADS_QSPI_GPIO_QSPI_SD1_IE_MSB _u(6) -#define PADS_QSPI_GPIO_QSPI_SD1_IE_LSB _u(6) -#define PADS_QSPI_GPIO_QSPI_SD1_IE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_QSPI_GPIO_QSPI_SD1_DRIVE -// Description : Drive strength. -// 0x0 -> 2mA -// 0x1 -> 4mA -// 0x2 -> 8mA -// 0x3 -> 12mA -#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_RESET _u(0x1) -#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_BITS _u(0x00000030) -#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_MSB _u(5) -#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_LSB _u(4) -#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_ACCESS "RW" -#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_VALUE_2MA _u(0x0) -#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_VALUE_4MA _u(0x1) -#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_VALUE_8MA _u(0x2) -#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_VALUE_12MA _u(0x3) -// ----------------------------------------------------------------------------- -// Field : PADS_QSPI_GPIO_QSPI_SD1_PUE -// Description : Pull up enable -#define PADS_QSPI_GPIO_QSPI_SD1_PUE_RESET _u(0x0) -#define PADS_QSPI_GPIO_QSPI_SD1_PUE_BITS _u(0x00000008) -#define PADS_QSPI_GPIO_QSPI_SD1_PUE_MSB _u(3) -#define PADS_QSPI_GPIO_QSPI_SD1_PUE_LSB _u(3) -#define PADS_QSPI_GPIO_QSPI_SD1_PUE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_QSPI_GPIO_QSPI_SD1_PDE -// Description : Pull down enable -#define PADS_QSPI_GPIO_QSPI_SD1_PDE_RESET _u(0x0) -#define PADS_QSPI_GPIO_QSPI_SD1_PDE_BITS _u(0x00000004) -#define PADS_QSPI_GPIO_QSPI_SD1_PDE_MSB _u(2) -#define PADS_QSPI_GPIO_QSPI_SD1_PDE_LSB _u(2) -#define PADS_QSPI_GPIO_QSPI_SD1_PDE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_QSPI_GPIO_QSPI_SD1_SCHMITT -// Description : Enable schmitt trigger -#define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_RESET _u(0x1) -#define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_BITS _u(0x00000002) -#define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_MSB _u(1) -#define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_LSB _u(1) -#define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST -// Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_RESET _u(0x0) -#define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_BITS _u(0x00000001) -#define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_MSB _u(0) -#define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_LSB _u(0) -#define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_ACCESS "RW" -// ============================================================================= -// Register : PADS_QSPI_GPIO_QSPI_SD2 -// Description : Pad control register -#define PADS_QSPI_GPIO_QSPI_SD2_OFFSET _u(0x00000010) -#define PADS_QSPI_GPIO_QSPI_SD2_BITS _u(0x000000ff) -#define PADS_QSPI_GPIO_QSPI_SD2_RESET _u(0x00000052) -// ----------------------------------------------------------------------------- -// Field : PADS_QSPI_GPIO_QSPI_SD2_OD -// Description : Output disable. Has priority over output enable from -// peripherals -#define PADS_QSPI_GPIO_QSPI_SD2_OD_RESET _u(0x0) -#define PADS_QSPI_GPIO_QSPI_SD2_OD_BITS _u(0x00000080) -#define PADS_QSPI_GPIO_QSPI_SD2_OD_MSB _u(7) -#define PADS_QSPI_GPIO_QSPI_SD2_OD_LSB _u(7) -#define PADS_QSPI_GPIO_QSPI_SD2_OD_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_QSPI_GPIO_QSPI_SD2_IE -// Description : Input enable -#define PADS_QSPI_GPIO_QSPI_SD2_IE_RESET _u(0x1) -#define PADS_QSPI_GPIO_QSPI_SD2_IE_BITS _u(0x00000040) -#define PADS_QSPI_GPIO_QSPI_SD2_IE_MSB _u(6) -#define PADS_QSPI_GPIO_QSPI_SD2_IE_LSB _u(6) -#define PADS_QSPI_GPIO_QSPI_SD2_IE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_QSPI_GPIO_QSPI_SD2_DRIVE -// Description : Drive strength. -// 0x0 -> 2mA -// 0x1 -> 4mA -// 0x2 -> 8mA -// 0x3 -> 12mA -#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_RESET _u(0x1) -#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_BITS _u(0x00000030) -#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_MSB _u(5) -#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_LSB _u(4) -#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_ACCESS "RW" -#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_VALUE_2MA _u(0x0) -#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_VALUE_4MA _u(0x1) -#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_VALUE_8MA _u(0x2) -#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_VALUE_12MA _u(0x3) -// ----------------------------------------------------------------------------- -// Field : PADS_QSPI_GPIO_QSPI_SD2_PUE -// Description : Pull up enable -#define PADS_QSPI_GPIO_QSPI_SD2_PUE_RESET _u(0x0) -#define PADS_QSPI_GPIO_QSPI_SD2_PUE_BITS _u(0x00000008) -#define PADS_QSPI_GPIO_QSPI_SD2_PUE_MSB _u(3) -#define PADS_QSPI_GPIO_QSPI_SD2_PUE_LSB _u(3) -#define PADS_QSPI_GPIO_QSPI_SD2_PUE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_QSPI_GPIO_QSPI_SD2_PDE -// Description : Pull down enable -#define PADS_QSPI_GPIO_QSPI_SD2_PDE_RESET _u(0x0) -#define PADS_QSPI_GPIO_QSPI_SD2_PDE_BITS _u(0x00000004) -#define PADS_QSPI_GPIO_QSPI_SD2_PDE_MSB _u(2) -#define PADS_QSPI_GPIO_QSPI_SD2_PDE_LSB _u(2) -#define PADS_QSPI_GPIO_QSPI_SD2_PDE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_QSPI_GPIO_QSPI_SD2_SCHMITT -// Description : Enable schmitt trigger -#define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_RESET _u(0x1) -#define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_BITS _u(0x00000002) -#define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_MSB _u(1) -#define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_LSB _u(1) -#define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST -// Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_RESET _u(0x0) -#define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_BITS _u(0x00000001) -#define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_MSB _u(0) -#define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_LSB _u(0) -#define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_ACCESS "RW" -// ============================================================================= -// Register : PADS_QSPI_GPIO_QSPI_SD3 -// Description : Pad control register -#define PADS_QSPI_GPIO_QSPI_SD3_OFFSET _u(0x00000014) -#define PADS_QSPI_GPIO_QSPI_SD3_BITS _u(0x000000ff) -#define PADS_QSPI_GPIO_QSPI_SD3_RESET _u(0x00000052) -// ----------------------------------------------------------------------------- -// Field : PADS_QSPI_GPIO_QSPI_SD3_OD -// Description : Output disable. Has priority over output enable from -// peripherals -#define PADS_QSPI_GPIO_QSPI_SD3_OD_RESET _u(0x0) -#define PADS_QSPI_GPIO_QSPI_SD3_OD_BITS _u(0x00000080) -#define PADS_QSPI_GPIO_QSPI_SD3_OD_MSB _u(7) -#define PADS_QSPI_GPIO_QSPI_SD3_OD_LSB _u(7) -#define PADS_QSPI_GPIO_QSPI_SD3_OD_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_QSPI_GPIO_QSPI_SD3_IE -// Description : Input enable -#define PADS_QSPI_GPIO_QSPI_SD3_IE_RESET _u(0x1) -#define PADS_QSPI_GPIO_QSPI_SD3_IE_BITS _u(0x00000040) -#define PADS_QSPI_GPIO_QSPI_SD3_IE_MSB _u(6) -#define PADS_QSPI_GPIO_QSPI_SD3_IE_LSB _u(6) -#define PADS_QSPI_GPIO_QSPI_SD3_IE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_QSPI_GPIO_QSPI_SD3_DRIVE -// Description : Drive strength. -// 0x0 -> 2mA -// 0x1 -> 4mA -// 0x2 -> 8mA -// 0x3 -> 12mA -#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_RESET _u(0x1) -#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_BITS _u(0x00000030) -#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_MSB _u(5) -#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_LSB _u(4) -#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_ACCESS "RW" -#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_VALUE_2MA _u(0x0) -#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_VALUE_4MA _u(0x1) -#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_VALUE_8MA _u(0x2) -#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_VALUE_12MA _u(0x3) -// ----------------------------------------------------------------------------- -// Field : PADS_QSPI_GPIO_QSPI_SD3_PUE -// Description : Pull up enable -#define PADS_QSPI_GPIO_QSPI_SD3_PUE_RESET _u(0x0) -#define PADS_QSPI_GPIO_QSPI_SD3_PUE_BITS _u(0x00000008) -#define PADS_QSPI_GPIO_QSPI_SD3_PUE_MSB _u(3) -#define PADS_QSPI_GPIO_QSPI_SD3_PUE_LSB _u(3) -#define PADS_QSPI_GPIO_QSPI_SD3_PUE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_QSPI_GPIO_QSPI_SD3_PDE -// Description : Pull down enable -#define PADS_QSPI_GPIO_QSPI_SD3_PDE_RESET _u(0x0) -#define PADS_QSPI_GPIO_QSPI_SD3_PDE_BITS _u(0x00000004) -#define PADS_QSPI_GPIO_QSPI_SD3_PDE_MSB _u(2) -#define PADS_QSPI_GPIO_QSPI_SD3_PDE_LSB _u(2) -#define PADS_QSPI_GPIO_QSPI_SD3_PDE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_QSPI_GPIO_QSPI_SD3_SCHMITT -// Description : Enable schmitt trigger -#define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_RESET _u(0x1) -#define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_BITS _u(0x00000002) -#define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_MSB _u(1) -#define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_LSB _u(1) -#define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST -// Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_RESET _u(0x0) -#define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_BITS _u(0x00000001) -#define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_MSB _u(0) -#define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_LSB _u(0) -#define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_ACCESS "RW" -// ============================================================================= -// Register : PADS_QSPI_GPIO_QSPI_SS -// Description : Pad control register -#define PADS_QSPI_GPIO_QSPI_SS_OFFSET _u(0x00000018) -#define PADS_QSPI_GPIO_QSPI_SS_BITS _u(0x000000ff) -#define PADS_QSPI_GPIO_QSPI_SS_RESET _u(0x0000005a) -// ----------------------------------------------------------------------------- -// Field : PADS_QSPI_GPIO_QSPI_SS_OD -// Description : Output disable. Has priority over output enable from -// peripherals -#define PADS_QSPI_GPIO_QSPI_SS_OD_RESET _u(0x0) -#define PADS_QSPI_GPIO_QSPI_SS_OD_BITS _u(0x00000080) -#define PADS_QSPI_GPIO_QSPI_SS_OD_MSB _u(7) -#define PADS_QSPI_GPIO_QSPI_SS_OD_LSB _u(7) -#define PADS_QSPI_GPIO_QSPI_SS_OD_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_QSPI_GPIO_QSPI_SS_IE -// Description : Input enable -#define PADS_QSPI_GPIO_QSPI_SS_IE_RESET _u(0x1) -#define PADS_QSPI_GPIO_QSPI_SS_IE_BITS _u(0x00000040) -#define PADS_QSPI_GPIO_QSPI_SS_IE_MSB _u(6) -#define PADS_QSPI_GPIO_QSPI_SS_IE_LSB _u(6) -#define PADS_QSPI_GPIO_QSPI_SS_IE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_QSPI_GPIO_QSPI_SS_DRIVE -// Description : Drive strength. -// 0x0 -> 2mA -// 0x1 -> 4mA -// 0x2 -> 8mA -// 0x3 -> 12mA -#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_RESET _u(0x1) -#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_BITS _u(0x00000030) -#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_MSB _u(5) -#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_LSB _u(4) -#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_ACCESS "RW" -#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_VALUE_2MA _u(0x0) -#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_VALUE_4MA _u(0x1) -#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_VALUE_8MA _u(0x2) -#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_VALUE_12MA _u(0x3) -// ----------------------------------------------------------------------------- -// Field : PADS_QSPI_GPIO_QSPI_SS_PUE -// Description : Pull up enable -#define PADS_QSPI_GPIO_QSPI_SS_PUE_RESET _u(0x1) -#define PADS_QSPI_GPIO_QSPI_SS_PUE_BITS _u(0x00000008) -#define PADS_QSPI_GPIO_QSPI_SS_PUE_MSB _u(3) -#define PADS_QSPI_GPIO_QSPI_SS_PUE_LSB _u(3) -#define PADS_QSPI_GPIO_QSPI_SS_PUE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_QSPI_GPIO_QSPI_SS_PDE -// Description : Pull down enable -#define PADS_QSPI_GPIO_QSPI_SS_PDE_RESET _u(0x0) -#define PADS_QSPI_GPIO_QSPI_SS_PDE_BITS _u(0x00000004) -#define PADS_QSPI_GPIO_QSPI_SS_PDE_MSB _u(2) -#define PADS_QSPI_GPIO_QSPI_SS_PDE_LSB _u(2) -#define PADS_QSPI_GPIO_QSPI_SS_PDE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_QSPI_GPIO_QSPI_SS_SCHMITT -// Description : Enable schmitt trigger -#define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_RESET _u(0x1) -#define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_BITS _u(0x00000002) -#define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_MSB _u(1) -#define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_LSB _u(1) -#define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_QSPI_GPIO_QSPI_SS_SLEWFAST -// Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_RESET _u(0x0) -#define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_BITS _u(0x00000001) -#define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_MSB _u(0) -#define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_LSB _u(0) -#define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_ACCESS "RW" -// ============================================================================= -#endif // _HARDWARE_REGS_PADS_QSPI_H - diff --git a/lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/pio.h b/lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/pio.h deleted file mode 100644 index d10de90f2c..0000000000 --- a/lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/pio.h +++ /dev/null @@ -1,2678 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -// ============================================================================= -// Register block : PIO -// Version : 1 -// Bus type : ahbl -// Description : Programmable IO block -// ============================================================================= -#ifndef _HARDWARE_REGS_PIO_H -#define _HARDWARE_REGS_PIO_H -// ============================================================================= -// Register : PIO_CTRL -// Description : PIO control register -#define PIO_CTRL_OFFSET _u(0x00000000) -#define PIO_CTRL_BITS _u(0x00000fff) -#define PIO_CTRL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : PIO_CTRL_CLKDIV_RESTART -// Description : Restart a state machine's clock divider from an initial phase -// of 0. Clock dividers are free-running, so once started, their -// output (including fractional jitter) is completely determined -// by the integer/fractional divisor configured in SMx_CLKDIV. -// This means that, if multiple clock dividers with the same -// divisor are restarted simultaneously, by writing multiple 1 -// bits to this field, the execution clocks of those state -// machines will run in precise lockstep. -// -// Note that setting/clearing SM_ENABLE does not stop the clock -// divider from running, so once multiple state machines' clocks -// are synchronised, it is safe to disable/reenable a state -// machine, whilst keeping the clock dividers in sync. -// -// Note also that CLKDIV_RESTART can be written to whilst the -// state machine is running, and this is useful to resynchronise -// clock dividers after the divisors (SMx_CLKDIV) have been -// changed on-the-fly. -#define PIO_CTRL_CLKDIV_RESTART_RESET _u(0x0) -#define PIO_CTRL_CLKDIV_RESTART_BITS _u(0x00000f00) -#define PIO_CTRL_CLKDIV_RESTART_MSB _u(11) -#define PIO_CTRL_CLKDIV_RESTART_LSB _u(8) -#define PIO_CTRL_CLKDIV_RESTART_ACCESS "SC" -// ----------------------------------------------------------------------------- -// Field : PIO_CTRL_SM_RESTART -// Description : Write 1 to instantly clear internal SM state which may be -// otherwise difficult to access and will affect future execution. -// -// Specifically, the following are cleared: input and output shift -// counters; the contents of the input shift register; the delay -// counter; the waiting-on-IRQ state; any stalled instruction -// written to SMx_INSTR or run by OUT/MOV EXEC; any pin write left -// asserted due to OUT_STICKY. -// -// The program counter, the contents of the output shift register -// and the X/Y scratch registers are not affected. -#define PIO_CTRL_SM_RESTART_RESET _u(0x0) -#define PIO_CTRL_SM_RESTART_BITS _u(0x000000f0) -#define PIO_CTRL_SM_RESTART_MSB _u(7) -#define PIO_CTRL_SM_RESTART_LSB _u(4) -#define PIO_CTRL_SM_RESTART_ACCESS "SC" -// ----------------------------------------------------------------------------- -// Field : PIO_CTRL_SM_ENABLE -// Description : Enable/disable each of the four state machines by writing 1/0 -// to each of these four bits. When disabled, a state machine will -// cease executing instructions, except those written directly to -// SMx_INSTR by the system. Multiple bits can be set/cleared at -// once to run/halt multiple state machines simultaneously. -#define PIO_CTRL_SM_ENABLE_RESET _u(0x0) -#define PIO_CTRL_SM_ENABLE_BITS _u(0x0000000f) -#define PIO_CTRL_SM_ENABLE_MSB _u(3) -#define PIO_CTRL_SM_ENABLE_LSB _u(0) -#define PIO_CTRL_SM_ENABLE_ACCESS "RW" -// ============================================================================= -// Register : PIO_FSTAT -// Description : FIFO status register -#define PIO_FSTAT_OFFSET _u(0x00000004) -#define PIO_FSTAT_BITS _u(0x0f0f0f0f) -#define PIO_FSTAT_RESET _u(0x0f000f00) -// ----------------------------------------------------------------------------- -// Field : PIO_FSTAT_TXEMPTY -// Description : State machine TX FIFO is empty -#define PIO_FSTAT_TXEMPTY_RESET _u(0xf) -#define PIO_FSTAT_TXEMPTY_BITS _u(0x0f000000) -#define PIO_FSTAT_TXEMPTY_MSB _u(27) -#define PIO_FSTAT_TXEMPTY_LSB _u(24) -#define PIO_FSTAT_TXEMPTY_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PIO_FSTAT_TXFULL -// Description : State machine TX FIFO is full -#define PIO_FSTAT_TXFULL_RESET _u(0x0) -#define PIO_FSTAT_TXFULL_BITS _u(0x000f0000) -#define PIO_FSTAT_TXFULL_MSB _u(19) -#define PIO_FSTAT_TXFULL_LSB _u(16) -#define PIO_FSTAT_TXFULL_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PIO_FSTAT_RXEMPTY -// Description : State machine RX FIFO is empty -#define PIO_FSTAT_RXEMPTY_RESET _u(0xf) -#define PIO_FSTAT_RXEMPTY_BITS _u(0x00000f00) -#define PIO_FSTAT_RXEMPTY_MSB _u(11) -#define PIO_FSTAT_RXEMPTY_LSB _u(8) -#define PIO_FSTAT_RXEMPTY_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PIO_FSTAT_RXFULL -// Description : State machine RX FIFO is full -#define PIO_FSTAT_RXFULL_RESET _u(0x0) -#define PIO_FSTAT_RXFULL_BITS _u(0x0000000f) -#define PIO_FSTAT_RXFULL_MSB _u(3) -#define PIO_FSTAT_RXFULL_LSB _u(0) -#define PIO_FSTAT_RXFULL_ACCESS "RO" -// ============================================================================= -// Register : PIO_FDEBUG -// Description : FIFO debug register -#define PIO_FDEBUG_OFFSET _u(0x00000008) -#define PIO_FDEBUG_BITS _u(0x0f0f0f0f) -#define PIO_FDEBUG_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : PIO_FDEBUG_TXSTALL -// Description : State machine has stalled on empty TX FIFO during a blocking -// PULL, or an OUT with autopull enabled. Write 1 to clear. -#define PIO_FDEBUG_TXSTALL_RESET _u(0x0) -#define PIO_FDEBUG_TXSTALL_BITS _u(0x0f000000) -#define PIO_FDEBUG_TXSTALL_MSB _u(27) -#define PIO_FDEBUG_TXSTALL_LSB _u(24) -#define PIO_FDEBUG_TXSTALL_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : PIO_FDEBUG_TXOVER -// Description : TX FIFO overflow (i.e. write-on-full by the system) has -// occurred. Write 1 to clear. Note that write-on-full does not -// alter the state or contents of the FIFO in any way, but the -// data that the system attempted to write is dropped, so if this -// flag is set, your software has quite likely dropped some data -// on the floor. -#define PIO_FDEBUG_TXOVER_RESET _u(0x0) -#define PIO_FDEBUG_TXOVER_BITS _u(0x000f0000) -#define PIO_FDEBUG_TXOVER_MSB _u(19) -#define PIO_FDEBUG_TXOVER_LSB _u(16) -#define PIO_FDEBUG_TXOVER_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : PIO_FDEBUG_RXUNDER -// Description : RX FIFO underflow (i.e. read-on-empty by the system) has -// occurred. Write 1 to clear. Note that read-on-empty does not -// perturb the state of the FIFO in any way, but the data returned -// by reading from an empty FIFO is undefined, so this flag -// generally only becomes set due to some kind of software error. -#define PIO_FDEBUG_RXUNDER_RESET _u(0x0) -#define PIO_FDEBUG_RXUNDER_BITS _u(0x00000f00) -#define PIO_FDEBUG_RXUNDER_MSB _u(11) -#define PIO_FDEBUG_RXUNDER_LSB _u(8) -#define PIO_FDEBUG_RXUNDER_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : PIO_FDEBUG_RXSTALL -// Description : State machine has stalled on full RX FIFO during a blocking -// PUSH, or an IN with autopush enabled. This flag is also set -// when a nonblocking PUSH to a full FIFO took place, in which -// case the state machine has dropped data. Write 1 to clear. -#define PIO_FDEBUG_RXSTALL_RESET _u(0x0) -#define PIO_FDEBUG_RXSTALL_BITS _u(0x0000000f) -#define PIO_FDEBUG_RXSTALL_MSB _u(3) -#define PIO_FDEBUG_RXSTALL_LSB _u(0) -#define PIO_FDEBUG_RXSTALL_ACCESS "WC" -// ============================================================================= -// Register : PIO_FLEVEL -// Description : FIFO levels -#define PIO_FLEVEL_OFFSET _u(0x0000000c) -#define PIO_FLEVEL_BITS _u(0xffffffff) -#define PIO_FLEVEL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : PIO_FLEVEL_RX3 -#define PIO_FLEVEL_RX3_RESET _u(0x0) -#define PIO_FLEVEL_RX3_BITS _u(0xf0000000) -#define PIO_FLEVEL_RX3_MSB _u(31) -#define PIO_FLEVEL_RX3_LSB _u(28) -#define PIO_FLEVEL_RX3_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PIO_FLEVEL_TX3 -#define PIO_FLEVEL_TX3_RESET _u(0x0) -#define PIO_FLEVEL_TX3_BITS _u(0x0f000000) -#define PIO_FLEVEL_TX3_MSB _u(27) -#define PIO_FLEVEL_TX3_LSB _u(24) -#define PIO_FLEVEL_TX3_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PIO_FLEVEL_RX2 -#define PIO_FLEVEL_RX2_RESET _u(0x0) -#define PIO_FLEVEL_RX2_BITS _u(0x00f00000) -#define PIO_FLEVEL_RX2_MSB _u(23) -#define PIO_FLEVEL_RX2_LSB _u(20) -#define PIO_FLEVEL_RX2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PIO_FLEVEL_TX2 -#define PIO_FLEVEL_TX2_RESET _u(0x0) -#define PIO_FLEVEL_TX2_BITS _u(0x000f0000) -#define PIO_FLEVEL_TX2_MSB _u(19) -#define PIO_FLEVEL_TX2_LSB _u(16) -#define PIO_FLEVEL_TX2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PIO_FLEVEL_RX1 -#define PIO_FLEVEL_RX1_RESET _u(0x0) -#define PIO_FLEVEL_RX1_BITS _u(0x0000f000) -#define PIO_FLEVEL_RX1_MSB _u(15) -#define PIO_FLEVEL_RX1_LSB _u(12) -#define PIO_FLEVEL_RX1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PIO_FLEVEL_TX1 -#define PIO_FLEVEL_TX1_RESET _u(0x0) -#define PIO_FLEVEL_TX1_BITS _u(0x00000f00) -#define PIO_FLEVEL_TX1_MSB _u(11) -#define PIO_FLEVEL_TX1_LSB _u(8) -#define PIO_FLEVEL_TX1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PIO_FLEVEL_RX0 -#define PIO_FLEVEL_RX0_RESET _u(0x0) -#define PIO_FLEVEL_RX0_BITS _u(0x000000f0) -#define PIO_FLEVEL_RX0_MSB _u(7) -#define PIO_FLEVEL_RX0_LSB _u(4) -#define PIO_FLEVEL_RX0_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PIO_FLEVEL_TX0 -#define PIO_FLEVEL_TX0_RESET _u(0x0) -#define PIO_FLEVEL_TX0_BITS _u(0x0000000f) -#define PIO_FLEVEL_TX0_MSB _u(3) -#define PIO_FLEVEL_TX0_LSB _u(0) -#define PIO_FLEVEL_TX0_ACCESS "RO" -// ============================================================================= -// Register : PIO_TXF0 -// Description : Direct write access to the TX FIFO for this state machine. Each -// write pushes one word to the FIFO. Attempting to write to a -// full FIFO has no effect on the FIFO state or contents, and sets -// the sticky FDEBUG_TXOVER error flag for this FIFO. -#define PIO_TXF0_OFFSET _u(0x00000010) -#define PIO_TXF0_BITS _u(0xffffffff) -#define PIO_TXF0_RESET _u(0x00000000) -#define PIO_TXF0_MSB _u(31) -#define PIO_TXF0_LSB _u(0) -#define PIO_TXF0_ACCESS "WF" -// ============================================================================= -// Register : PIO_TXF1 -// Description : Direct write access to the TX FIFO for this state machine. Each -// write pushes one word to the FIFO. Attempting to write to a -// full FIFO has no effect on the FIFO state or contents, and sets -// the sticky FDEBUG_TXOVER error flag for this FIFO. -#define PIO_TXF1_OFFSET _u(0x00000014) -#define PIO_TXF1_BITS _u(0xffffffff) -#define PIO_TXF1_RESET _u(0x00000000) -#define PIO_TXF1_MSB _u(31) -#define PIO_TXF1_LSB _u(0) -#define PIO_TXF1_ACCESS "WF" -// ============================================================================= -// Register : PIO_TXF2 -// Description : Direct write access to the TX FIFO for this state machine. Each -// write pushes one word to the FIFO. Attempting to write to a -// full FIFO has no effect on the FIFO state or contents, and sets -// the sticky FDEBUG_TXOVER error flag for this FIFO. -#define PIO_TXF2_OFFSET _u(0x00000018) -#define PIO_TXF2_BITS _u(0xffffffff) -#define PIO_TXF2_RESET _u(0x00000000) -#define PIO_TXF2_MSB _u(31) -#define PIO_TXF2_LSB _u(0) -#define PIO_TXF2_ACCESS "WF" -// ============================================================================= -// Register : PIO_TXF3 -// Description : Direct write access to the TX FIFO for this state machine. Each -// write pushes one word to the FIFO. Attempting to write to a -// full FIFO has no effect on the FIFO state or contents, and sets -// the sticky FDEBUG_TXOVER error flag for this FIFO. -#define PIO_TXF3_OFFSET _u(0x0000001c) -#define PIO_TXF3_BITS _u(0xffffffff) -#define PIO_TXF3_RESET _u(0x00000000) -#define PIO_TXF3_MSB _u(31) -#define PIO_TXF3_LSB _u(0) -#define PIO_TXF3_ACCESS "WF" -// ============================================================================= -// Register : PIO_RXF0 -// Description : Direct read access to the RX FIFO for this state machine. Each -// read pops one word from the FIFO. Attempting to read from an -// empty FIFO has no effect on the FIFO state, and sets the sticky -// FDEBUG_RXUNDER error flag for this FIFO. The data returned to -// the system on a read from an empty FIFO is undefined. -#define PIO_RXF0_OFFSET _u(0x00000020) -#define PIO_RXF0_BITS _u(0xffffffff) -#define PIO_RXF0_RESET "-" -#define PIO_RXF0_MSB _u(31) -#define PIO_RXF0_LSB _u(0) -#define PIO_RXF0_ACCESS "RF" -// ============================================================================= -// Register : PIO_RXF1 -// Description : Direct read access to the RX FIFO for this state machine. Each -// read pops one word from the FIFO. Attempting to read from an -// empty FIFO has no effect on the FIFO state, and sets the sticky -// FDEBUG_RXUNDER error flag for this FIFO. The data returned to -// the system on a read from an empty FIFO is undefined. -#define PIO_RXF1_OFFSET _u(0x00000024) -#define PIO_RXF1_BITS _u(0xffffffff) -#define PIO_RXF1_RESET "-" -#define PIO_RXF1_MSB _u(31) -#define PIO_RXF1_LSB _u(0) -#define PIO_RXF1_ACCESS "RF" -// ============================================================================= -// Register : PIO_RXF2 -// Description : Direct read access to the RX FIFO for this state machine. Each -// read pops one word from the FIFO. Attempting to read from an -// empty FIFO has no effect on the FIFO state, and sets the sticky -// FDEBUG_RXUNDER error flag for this FIFO. The data returned to -// the system on a read from an empty FIFO is undefined. -#define PIO_RXF2_OFFSET _u(0x00000028) -#define PIO_RXF2_BITS _u(0xffffffff) -#define PIO_RXF2_RESET "-" -#define PIO_RXF2_MSB _u(31) -#define PIO_RXF2_LSB _u(0) -#define PIO_RXF2_ACCESS "RF" -// ============================================================================= -// Register : PIO_RXF3 -// Description : Direct read access to the RX FIFO for this state machine. Each -// read pops one word from the FIFO. Attempting to read from an -// empty FIFO has no effect on the FIFO state, and sets the sticky -// FDEBUG_RXUNDER error flag for this FIFO. The data returned to -// the system on a read from an empty FIFO is undefined. -#define PIO_RXF3_OFFSET _u(0x0000002c) -#define PIO_RXF3_BITS _u(0xffffffff) -#define PIO_RXF3_RESET "-" -#define PIO_RXF3_MSB _u(31) -#define PIO_RXF3_LSB _u(0) -#define PIO_RXF3_ACCESS "RF" -// ============================================================================= -// Register : PIO_IRQ -// Description : State machine IRQ flags register. Write 1 to clear. There are 8 -// state machine IRQ flags, which can be set, cleared, and waited -// on by the state machines. There's no fixed association between -// flags and state machines -- any state machine can use any flag. -// -// Any of the 8 flags can be used for timing synchronisation -// between state machines, using IRQ and WAIT instructions. The -// lower four of these flags are also routed out to system-level -// interrupt requests, alongside FIFO status interrupts -- see -// e.g. IRQ0_INTE. -#define PIO_IRQ_OFFSET _u(0x00000030) -#define PIO_IRQ_BITS _u(0x000000ff) -#define PIO_IRQ_RESET _u(0x00000000) -#define PIO_IRQ_MSB _u(7) -#define PIO_IRQ_LSB _u(0) -#define PIO_IRQ_ACCESS "WC" -// ============================================================================= -// Register : PIO_IRQ_FORCE -// Description : Writing a 1 to each of these bits will forcibly assert the -// corresponding IRQ. Note this is different to the INTF register: -// writing here affects PIO internal state. INTF just asserts the -// processor-facing IRQ signal for testing ISRs, and is not -// visible to the state machines. -#define PIO_IRQ_FORCE_OFFSET _u(0x00000034) -#define PIO_IRQ_FORCE_BITS _u(0x000000ff) -#define PIO_IRQ_FORCE_RESET _u(0x00000000) -#define PIO_IRQ_FORCE_MSB _u(7) -#define PIO_IRQ_FORCE_LSB _u(0) -#define PIO_IRQ_FORCE_ACCESS "WF" -// ============================================================================= -// Register : PIO_INPUT_SYNC_BYPASS -// Description : There is a 2-flipflop synchronizer on each GPIO input, which -// protects PIO logic from metastabilities. This increases input -// delay, and for fast synchronous IO (e.g. SPI) these -// synchronizers may need to be bypassed. Each bit in this -// register corresponds to one GPIO. -// 0 -> input is synchronized (default) -// 1 -> synchronizer is bypassed -// If in doubt, leave this register as all zeroes. -#define PIO_INPUT_SYNC_BYPASS_OFFSET _u(0x00000038) -#define PIO_INPUT_SYNC_BYPASS_BITS _u(0xffffffff) -#define PIO_INPUT_SYNC_BYPASS_RESET _u(0x00000000) -#define PIO_INPUT_SYNC_BYPASS_MSB _u(31) -#define PIO_INPUT_SYNC_BYPASS_LSB _u(0) -#define PIO_INPUT_SYNC_BYPASS_ACCESS "RW" -// ============================================================================= -// Register : PIO_DBG_PADOUT -// Description : Read to sample the pad output values PIO is currently driving -// to the GPIOs. On RP2040 there are 30 GPIOs, so the two most -// significant bits are hardwired to 0. -#define PIO_DBG_PADOUT_OFFSET _u(0x0000003c) -#define PIO_DBG_PADOUT_BITS _u(0xffffffff) -#define PIO_DBG_PADOUT_RESET _u(0x00000000) -#define PIO_DBG_PADOUT_MSB _u(31) -#define PIO_DBG_PADOUT_LSB _u(0) -#define PIO_DBG_PADOUT_ACCESS "RO" -// ============================================================================= -// Register : PIO_DBG_PADOE -// Description : Read to sample the pad output enables (direction) PIO is -// currently driving to the GPIOs. On RP2040 there are 30 GPIOs, -// so the two most significant bits are hardwired to 0. -#define PIO_DBG_PADOE_OFFSET _u(0x00000040) -#define PIO_DBG_PADOE_BITS _u(0xffffffff) -#define PIO_DBG_PADOE_RESET _u(0x00000000) -#define PIO_DBG_PADOE_MSB _u(31) -#define PIO_DBG_PADOE_LSB _u(0) -#define PIO_DBG_PADOE_ACCESS "RO" -// ============================================================================= -// Register : PIO_DBG_CFGINFO -// Description : The PIO hardware has some free parameters that may vary between -// chip products. -// These should be provided in the chip datasheet, but are also -// exposed here. -#define PIO_DBG_CFGINFO_OFFSET _u(0x00000044) -#define PIO_DBG_CFGINFO_BITS _u(0x003f0f3f) -#define PIO_DBG_CFGINFO_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : PIO_DBG_CFGINFO_IMEM_SIZE -// Description : The size of the instruction memory, measured in units of one -// instruction -#define PIO_DBG_CFGINFO_IMEM_SIZE_RESET "-" -#define PIO_DBG_CFGINFO_IMEM_SIZE_BITS _u(0x003f0000) -#define PIO_DBG_CFGINFO_IMEM_SIZE_MSB _u(21) -#define PIO_DBG_CFGINFO_IMEM_SIZE_LSB _u(16) -#define PIO_DBG_CFGINFO_IMEM_SIZE_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PIO_DBG_CFGINFO_SM_COUNT -// Description : The number of state machines this PIO instance is equipped -// with. -#define PIO_DBG_CFGINFO_SM_COUNT_RESET "-" -#define PIO_DBG_CFGINFO_SM_COUNT_BITS _u(0x00000f00) -#define PIO_DBG_CFGINFO_SM_COUNT_MSB _u(11) -#define PIO_DBG_CFGINFO_SM_COUNT_LSB _u(8) -#define PIO_DBG_CFGINFO_SM_COUNT_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PIO_DBG_CFGINFO_FIFO_DEPTH -// Description : The depth of the state machine TX/RX FIFOs, measured in words. -// Joining fifos via SHIFTCTRL_FJOIN gives one FIFO with double -// this depth. -#define PIO_DBG_CFGINFO_FIFO_DEPTH_RESET "-" -#define PIO_DBG_CFGINFO_FIFO_DEPTH_BITS _u(0x0000003f) -#define PIO_DBG_CFGINFO_FIFO_DEPTH_MSB _u(5) -#define PIO_DBG_CFGINFO_FIFO_DEPTH_LSB _u(0) -#define PIO_DBG_CFGINFO_FIFO_DEPTH_ACCESS "RO" -// ============================================================================= -// Register : PIO_INSTR_MEM0 -// Description : Write-only access to instruction memory location 0 -#define PIO_INSTR_MEM0_OFFSET _u(0x00000048) -#define PIO_INSTR_MEM0_BITS _u(0x0000ffff) -#define PIO_INSTR_MEM0_RESET _u(0x00000000) -#define PIO_INSTR_MEM0_MSB _u(15) -#define PIO_INSTR_MEM0_LSB _u(0) -#define PIO_INSTR_MEM0_ACCESS "WO" -// ============================================================================= -// Register : PIO_INSTR_MEM1 -// Description : Write-only access to instruction memory location 1 -#define PIO_INSTR_MEM1_OFFSET _u(0x0000004c) -#define PIO_INSTR_MEM1_BITS _u(0x0000ffff) -#define PIO_INSTR_MEM1_RESET _u(0x00000000) -#define PIO_INSTR_MEM1_MSB _u(15) -#define PIO_INSTR_MEM1_LSB _u(0) -#define PIO_INSTR_MEM1_ACCESS "WO" -// ============================================================================= -// Register : PIO_INSTR_MEM2 -// Description : Write-only access to instruction memory location 2 -#define PIO_INSTR_MEM2_OFFSET _u(0x00000050) -#define PIO_INSTR_MEM2_BITS _u(0x0000ffff) -#define PIO_INSTR_MEM2_RESET _u(0x00000000) -#define PIO_INSTR_MEM2_MSB _u(15) -#define PIO_INSTR_MEM2_LSB _u(0) -#define PIO_INSTR_MEM2_ACCESS "WO" -// ============================================================================= -// Register : PIO_INSTR_MEM3 -// Description : Write-only access to instruction memory location 3 -#define PIO_INSTR_MEM3_OFFSET _u(0x00000054) -#define PIO_INSTR_MEM3_BITS _u(0x0000ffff) -#define PIO_INSTR_MEM3_RESET _u(0x00000000) -#define PIO_INSTR_MEM3_MSB _u(15) -#define PIO_INSTR_MEM3_LSB _u(0) -#define PIO_INSTR_MEM3_ACCESS "WO" -// ============================================================================= -// Register : PIO_INSTR_MEM4 -// Description : Write-only access to instruction memory location 4 -#define PIO_INSTR_MEM4_OFFSET _u(0x00000058) -#define PIO_INSTR_MEM4_BITS _u(0x0000ffff) -#define PIO_INSTR_MEM4_RESET _u(0x00000000) -#define PIO_INSTR_MEM4_MSB _u(15) -#define PIO_INSTR_MEM4_LSB _u(0) -#define PIO_INSTR_MEM4_ACCESS "WO" -// ============================================================================= -// Register : PIO_INSTR_MEM5 -// Description : Write-only access to instruction memory location 5 -#define PIO_INSTR_MEM5_OFFSET _u(0x0000005c) -#define PIO_INSTR_MEM5_BITS _u(0x0000ffff) -#define PIO_INSTR_MEM5_RESET _u(0x00000000) -#define PIO_INSTR_MEM5_MSB _u(15) -#define PIO_INSTR_MEM5_LSB _u(0) -#define PIO_INSTR_MEM5_ACCESS "WO" -// ============================================================================= -// Register : PIO_INSTR_MEM6 -// Description : Write-only access to instruction memory location 6 -#define PIO_INSTR_MEM6_OFFSET _u(0x00000060) -#define PIO_INSTR_MEM6_BITS _u(0x0000ffff) -#define PIO_INSTR_MEM6_RESET _u(0x00000000) -#define PIO_INSTR_MEM6_MSB _u(15) -#define PIO_INSTR_MEM6_LSB _u(0) -#define PIO_INSTR_MEM6_ACCESS "WO" -// ============================================================================= -// Register : PIO_INSTR_MEM7 -// Description : Write-only access to instruction memory location 7 -#define PIO_INSTR_MEM7_OFFSET _u(0x00000064) -#define PIO_INSTR_MEM7_BITS _u(0x0000ffff) -#define PIO_INSTR_MEM7_RESET _u(0x00000000) -#define PIO_INSTR_MEM7_MSB _u(15) -#define PIO_INSTR_MEM7_LSB _u(0) -#define PIO_INSTR_MEM7_ACCESS "WO" -// ============================================================================= -// Register : PIO_INSTR_MEM8 -// Description : Write-only access to instruction memory location 8 -#define PIO_INSTR_MEM8_OFFSET _u(0x00000068) -#define PIO_INSTR_MEM8_BITS _u(0x0000ffff) -#define PIO_INSTR_MEM8_RESET _u(0x00000000) -#define PIO_INSTR_MEM8_MSB _u(15) -#define PIO_INSTR_MEM8_LSB _u(0) -#define PIO_INSTR_MEM8_ACCESS "WO" -// ============================================================================= -// Register : PIO_INSTR_MEM9 -// Description : Write-only access to instruction memory location 9 -#define PIO_INSTR_MEM9_OFFSET _u(0x0000006c) -#define PIO_INSTR_MEM9_BITS _u(0x0000ffff) -#define PIO_INSTR_MEM9_RESET _u(0x00000000) -#define PIO_INSTR_MEM9_MSB _u(15) -#define PIO_INSTR_MEM9_LSB _u(0) -#define PIO_INSTR_MEM9_ACCESS "WO" -// ============================================================================= -// Register : PIO_INSTR_MEM10 -// Description : Write-only access to instruction memory location 10 -#define PIO_INSTR_MEM10_OFFSET _u(0x00000070) -#define PIO_INSTR_MEM10_BITS _u(0x0000ffff) -#define PIO_INSTR_MEM10_RESET _u(0x00000000) -#define PIO_INSTR_MEM10_MSB _u(15) -#define PIO_INSTR_MEM10_LSB _u(0) -#define PIO_INSTR_MEM10_ACCESS "WO" -// ============================================================================= -// Register : PIO_INSTR_MEM11 -// Description : Write-only access to instruction memory location 11 -#define PIO_INSTR_MEM11_OFFSET _u(0x00000074) -#define PIO_INSTR_MEM11_BITS _u(0x0000ffff) -#define PIO_INSTR_MEM11_RESET _u(0x00000000) -#define PIO_INSTR_MEM11_MSB _u(15) -#define PIO_INSTR_MEM11_LSB _u(0) -#define PIO_INSTR_MEM11_ACCESS "WO" -// ============================================================================= -// Register : PIO_INSTR_MEM12 -// Description : Write-only access to instruction memory location 12 -#define PIO_INSTR_MEM12_OFFSET _u(0x00000078) -#define PIO_INSTR_MEM12_BITS _u(0x0000ffff) -#define PIO_INSTR_MEM12_RESET _u(0x00000000) -#define PIO_INSTR_MEM12_MSB _u(15) -#define PIO_INSTR_MEM12_LSB _u(0) -#define PIO_INSTR_MEM12_ACCESS "WO" -// ============================================================================= -// Register : PIO_INSTR_MEM13 -// Description : Write-only access to instruction memory location 13 -#define PIO_INSTR_MEM13_OFFSET _u(0x0000007c) -#define PIO_INSTR_MEM13_BITS _u(0x0000ffff) -#define PIO_INSTR_MEM13_RESET _u(0x00000000) -#define PIO_INSTR_MEM13_MSB _u(15) -#define PIO_INSTR_MEM13_LSB _u(0) -#define PIO_INSTR_MEM13_ACCESS "WO" -// ============================================================================= -// Register : PIO_INSTR_MEM14 -// Description : Write-only access to instruction memory location 14 -#define PIO_INSTR_MEM14_OFFSET _u(0x00000080) -#define PIO_INSTR_MEM14_BITS _u(0x0000ffff) -#define PIO_INSTR_MEM14_RESET _u(0x00000000) -#define PIO_INSTR_MEM14_MSB _u(15) -#define PIO_INSTR_MEM14_LSB _u(0) -#define PIO_INSTR_MEM14_ACCESS "WO" -// ============================================================================= -// Register : PIO_INSTR_MEM15 -// Description : Write-only access to instruction memory location 15 -#define PIO_INSTR_MEM15_OFFSET _u(0x00000084) -#define PIO_INSTR_MEM15_BITS _u(0x0000ffff) -#define PIO_INSTR_MEM15_RESET _u(0x00000000) -#define PIO_INSTR_MEM15_MSB _u(15) -#define PIO_INSTR_MEM15_LSB _u(0) -#define PIO_INSTR_MEM15_ACCESS "WO" -// ============================================================================= -// Register : PIO_INSTR_MEM16 -// Description : Write-only access to instruction memory location 16 -#define PIO_INSTR_MEM16_OFFSET _u(0x00000088) -#define PIO_INSTR_MEM16_BITS _u(0x0000ffff) -#define PIO_INSTR_MEM16_RESET _u(0x00000000) -#define PIO_INSTR_MEM16_MSB _u(15) -#define PIO_INSTR_MEM16_LSB _u(0) -#define PIO_INSTR_MEM16_ACCESS "WO" -// ============================================================================= -// Register : PIO_INSTR_MEM17 -// Description : Write-only access to instruction memory location 17 -#define PIO_INSTR_MEM17_OFFSET _u(0x0000008c) -#define PIO_INSTR_MEM17_BITS _u(0x0000ffff) -#define PIO_INSTR_MEM17_RESET _u(0x00000000) -#define PIO_INSTR_MEM17_MSB _u(15) -#define PIO_INSTR_MEM17_LSB _u(0) -#define PIO_INSTR_MEM17_ACCESS "WO" -// ============================================================================= -// Register : PIO_INSTR_MEM18 -// Description : Write-only access to instruction memory location 18 -#define PIO_INSTR_MEM18_OFFSET _u(0x00000090) -#define PIO_INSTR_MEM18_BITS _u(0x0000ffff) -#define PIO_INSTR_MEM18_RESET _u(0x00000000) -#define PIO_INSTR_MEM18_MSB _u(15) -#define PIO_INSTR_MEM18_LSB _u(0) -#define PIO_INSTR_MEM18_ACCESS "WO" -// ============================================================================= -// Register : PIO_INSTR_MEM19 -// Description : Write-only access to instruction memory location 19 -#define PIO_INSTR_MEM19_OFFSET _u(0x00000094) -#define PIO_INSTR_MEM19_BITS _u(0x0000ffff) -#define PIO_INSTR_MEM19_RESET _u(0x00000000) -#define PIO_INSTR_MEM19_MSB _u(15) -#define PIO_INSTR_MEM19_LSB _u(0) -#define PIO_INSTR_MEM19_ACCESS "WO" -// ============================================================================= -// Register : PIO_INSTR_MEM20 -// Description : Write-only access to instruction memory location 20 -#define PIO_INSTR_MEM20_OFFSET _u(0x00000098) -#define PIO_INSTR_MEM20_BITS _u(0x0000ffff) -#define PIO_INSTR_MEM20_RESET _u(0x00000000) -#define PIO_INSTR_MEM20_MSB _u(15) -#define PIO_INSTR_MEM20_LSB _u(0) -#define PIO_INSTR_MEM20_ACCESS "WO" -// ============================================================================= -// Register : PIO_INSTR_MEM21 -// Description : Write-only access to instruction memory location 21 -#define PIO_INSTR_MEM21_OFFSET _u(0x0000009c) -#define PIO_INSTR_MEM21_BITS _u(0x0000ffff) -#define PIO_INSTR_MEM21_RESET _u(0x00000000) -#define PIO_INSTR_MEM21_MSB _u(15) -#define PIO_INSTR_MEM21_LSB _u(0) -#define PIO_INSTR_MEM21_ACCESS "WO" -// ============================================================================= -// Register : PIO_INSTR_MEM22 -// Description : Write-only access to instruction memory location 22 -#define PIO_INSTR_MEM22_OFFSET _u(0x000000a0) -#define PIO_INSTR_MEM22_BITS _u(0x0000ffff) -#define PIO_INSTR_MEM22_RESET _u(0x00000000) -#define PIO_INSTR_MEM22_MSB _u(15) -#define PIO_INSTR_MEM22_LSB _u(0) -#define PIO_INSTR_MEM22_ACCESS "WO" -// ============================================================================= -// Register : PIO_INSTR_MEM23 -// Description : Write-only access to instruction memory location 23 -#define PIO_INSTR_MEM23_OFFSET _u(0x000000a4) -#define PIO_INSTR_MEM23_BITS _u(0x0000ffff) -#define PIO_INSTR_MEM23_RESET _u(0x00000000) -#define PIO_INSTR_MEM23_MSB _u(15) -#define PIO_INSTR_MEM23_LSB _u(0) -#define PIO_INSTR_MEM23_ACCESS "WO" -// ============================================================================= -// Register : PIO_INSTR_MEM24 -// Description : Write-only access to instruction memory location 24 -#define PIO_INSTR_MEM24_OFFSET _u(0x000000a8) -#define PIO_INSTR_MEM24_BITS _u(0x0000ffff) -#define PIO_INSTR_MEM24_RESET _u(0x00000000) -#define PIO_INSTR_MEM24_MSB _u(15) -#define PIO_INSTR_MEM24_LSB _u(0) -#define PIO_INSTR_MEM24_ACCESS "WO" -// ============================================================================= -// Register : PIO_INSTR_MEM25 -// Description : Write-only access to instruction memory location 25 -#define PIO_INSTR_MEM25_OFFSET _u(0x000000ac) -#define PIO_INSTR_MEM25_BITS _u(0x0000ffff) -#define PIO_INSTR_MEM25_RESET _u(0x00000000) -#define PIO_INSTR_MEM25_MSB _u(15) -#define PIO_INSTR_MEM25_LSB _u(0) -#define PIO_INSTR_MEM25_ACCESS "WO" -// ============================================================================= -// Register : PIO_INSTR_MEM26 -// Description : Write-only access to instruction memory location 26 -#define PIO_INSTR_MEM26_OFFSET _u(0x000000b0) -#define PIO_INSTR_MEM26_BITS _u(0x0000ffff) -#define PIO_INSTR_MEM26_RESET _u(0x00000000) -#define PIO_INSTR_MEM26_MSB _u(15) -#define PIO_INSTR_MEM26_LSB _u(0) -#define PIO_INSTR_MEM26_ACCESS "WO" -// ============================================================================= -// Register : PIO_INSTR_MEM27 -// Description : Write-only access to instruction memory location 27 -#define PIO_INSTR_MEM27_OFFSET _u(0x000000b4) -#define PIO_INSTR_MEM27_BITS _u(0x0000ffff) -#define PIO_INSTR_MEM27_RESET _u(0x00000000) -#define PIO_INSTR_MEM27_MSB _u(15) -#define PIO_INSTR_MEM27_LSB _u(0) -#define PIO_INSTR_MEM27_ACCESS "WO" -// ============================================================================= -// Register : PIO_INSTR_MEM28 -// Description : Write-only access to instruction memory location 28 -#define PIO_INSTR_MEM28_OFFSET _u(0x000000b8) -#define PIO_INSTR_MEM28_BITS _u(0x0000ffff) -#define PIO_INSTR_MEM28_RESET _u(0x00000000) -#define PIO_INSTR_MEM28_MSB _u(15) -#define PIO_INSTR_MEM28_LSB _u(0) -#define PIO_INSTR_MEM28_ACCESS "WO" -// ============================================================================= -// Register : PIO_INSTR_MEM29 -// Description : Write-only access to instruction memory location 29 -#define PIO_INSTR_MEM29_OFFSET _u(0x000000bc) -#define PIO_INSTR_MEM29_BITS _u(0x0000ffff) -#define PIO_INSTR_MEM29_RESET _u(0x00000000) -#define PIO_INSTR_MEM29_MSB _u(15) -#define PIO_INSTR_MEM29_LSB _u(0) -#define PIO_INSTR_MEM29_ACCESS "WO" -// ============================================================================= -// Register : PIO_INSTR_MEM30 -// Description : Write-only access to instruction memory location 30 -#define PIO_INSTR_MEM30_OFFSET _u(0x000000c0) -#define PIO_INSTR_MEM30_BITS _u(0x0000ffff) -#define PIO_INSTR_MEM30_RESET _u(0x00000000) -#define PIO_INSTR_MEM30_MSB _u(15) -#define PIO_INSTR_MEM30_LSB _u(0) -#define PIO_INSTR_MEM30_ACCESS "WO" -// ============================================================================= -// Register : PIO_INSTR_MEM31 -// Description : Write-only access to instruction memory location 31 -#define PIO_INSTR_MEM31_OFFSET _u(0x000000c4) -#define PIO_INSTR_MEM31_BITS _u(0x0000ffff) -#define PIO_INSTR_MEM31_RESET _u(0x00000000) -#define PIO_INSTR_MEM31_MSB _u(15) -#define PIO_INSTR_MEM31_LSB _u(0) -#define PIO_INSTR_MEM31_ACCESS "WO" -// ============================================================================= -// Register : PIO_SM0_CLKDIV -// Description : Clock divisor register for state machine 0 -// Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) -#define PIO_SM0_CLKDIV_OFFSET _u(0x000000c8) -#define PIO_SM0_CLKDIV_BITS _u(0xffffff00) -#define PIO_SM0_CLKDIV_RESET _u(0x00010000) -// ----------------------------------------------------------------------------- -// Field : PIO_SM0_CLKDIV_INT -// Description : Effective frequency is sysclk/(int + frac/256). -// Value of 0 is interpreted as 65536. If INT is 0, FRAC must also -// be 0. -#define PIO_SM0_CLKDIV_INT_RESET _u(0x0001) -#define PIO_SM0_CLKDIV_INT_BITS _u(0xffff0000) -#define PIO_SM0_CLKDIV_INT_MSB _u(31) -#define PIO_SM0_CLKDIV_INT_LSB _u(16) -#define PIO_SM0_CLKDIV_INT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM0_CLKDIV_FRAC -// Description : Fractional part of clock divisor -#define PIO_SM0_CLKDIV_FRAC_RESET _u(0x00) -#define PIO_SM0_CLKDIV_FRAC_BITS _u(0x0000ff00) -#define PIO_SM0_CLKDIV_FRAC_MSB _u(15) -#define PIO_SM0_CLKDIV_FRAC_LSB _u(8) -#define PIO_SM0_CLKDIV_FRAC_ACCESS "RW" -// ============================================================================= -// Register : PIO_SM0_EXECCTRL -// Description : Execution/behavioural settings for state machine 0 -#define PIO_SM0_EXECCTRL_OFFSET _u(0x000000cc) -#define PIO_SM0_EXECCTRL_BITS _u(0xffffff9f) -#define PIO_SM0_EXECCTRL_RESET _u(0x0001f000) -// ----------------------------------------------------------------------------- -// Field : PIO_SM0_EXECCTRL_EXEC_STALLED -// Description : If 1, an instruction written to SMx_INSTR is stalled, and -// latched by the state machine. Will clear to 0 once this -// instruction completes. -#define PIO_SM0_EXECCTRL_EXEC_STALLED_RESET _u(0x0) -#define PIO_SM0_EXECCTRL_EXEC_STALLED_BITS _u(0x80000000) -#define PIO_SM0_EXECCTRL_EXEC_STALLED_MSB _u(31) -#define PIO_SM0_EXECCTRL_EXEC_STALLED_LSB _u(31) -#define PIO_SM0_EXECCTRL_EXEC_STALLED_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PIO_SM0_EXECCTRL_SIDE_EN -// Description : If 1, the MSB of the Delay/Side-set instruction field is used -// as side-set enable, rather than a side-set data bit. This -// allows instructions to perform side-set optionally, rather than -// on every instruction, but the maximum possible side-set width -// is reduced from 5 to 4. Note that the value of -// PINCTRL_SIDESET_COUNT is inclusive of this enable bit. -#define PIO_SM0_EXECCTRL_SIDE_EN_RESET _u(0x0) -#define PIO_SM0_EXECCTRL_SIDE_EN_BITS _u(0x40000000) -#define PIO_SM0_EXECCTRL_SIDE_EN_MSB _u(30) -#define PIO_SM0_EXECCTRL_SIDE_EN_LSB _u(30) -#define PIO_SM0_EXECCTRL_SIDE_EN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM0_EXECCTRL_SIDE_PINDIR -// Description : If 1, side-set data is asserted to pin directions, instead of -// pin values -#define PIO_SM0_EXECCTRL_SIDE_PINDIR_RESET _u(0x0) -#define PIO_SM0_EXECCTRL_SIDE_PINDIR_BITS _u(0x20000000) -#define PIO_SM0_EXECCTRL_SIDE_PINDIR_MSB _u(29) -#define PIO_SM0_EXECCTRL_SIDE_PINDIR_LSB _u(29) -#define PIO_SM0_EXECCTRL_SIDE_PINDIR_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM0_EXECCTRL_JMP_PIN -// Description : The GPIO number to use as condition for JMP PIN. Unaffected by -// input mapping. -#define PIO_SM0_EXECCTRL_JMP_PIN_RESET _u(0x00) -#define PIO_SM0_EXECCTRL_JMP_PIN_BITS _u(0x1f000000) -#define PIO_SM0_EXECCTRL_JMP_PIN_MSB _u(28) -#define PIO_SM0_EXECCTRL_JMP_PIN_LSB _u(24) -#define PIO_SM0_EXECCTRL_JMP_PIN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM0_EXECCTRL_OUT_EN_SEL -// Description : Which data bit to use for inline OUT enable -#define PIO_SM0_EXECCTRL_OUT_EN_SEL_RESET _u(0x00) -#define PIO_SM0_EXECCTRL_OUT_EN_SEL_BITS _u(0x00f80000) -#define PIO_SM0_EXECCTRL_OUT_EN_SEL_MSB _u(23) -#define PIO_SM0_EXECCTRL_OUT_EN_SEL_LSB _u(19) -#define PIO_SM0_EXECCTRL_OUT_EN_SEL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM0_EXECCTRL_INLINE_OUT_EN -// Description : If 1, use a bit of OUT data as an auxiliary write enable -// When used in conjunction with OUT_STICKY, writes with an enable -// of 0 will -// deassert the latest pin write. This can create useful -// masking/override behaviour -// due to the priority ordering of state machine pin writes (SM0 < -// SM1 < ...) -#define PIO_SM0_EXECCTRL_INLINE_OUT_EN_RESET _u(0x0) -#define PIO_SM0_EXECCTRL_INLINE_OUT_EN_BITS _u(0x00040000) -#define PIO_SM0_EXECCTRL_INLINE_OUT_EN_MSB _u(18) -#define PIO_SM0_EXECCTRL_INLINE_OUT_EN_LSB _u(18) -#define PIO_SM0_EXECCTRL_INLINE_OUT_EN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM0_EXECCTRL_OUT_STICKY -// Description : Continuously assert the most recent OUT/SET to the pins -#define PIO_SM0_EXECCTRL_OUT_STICKY_RESET _u(0x0) -#define PIO_SM0_EXECCTRL_OUT_STICKY_BITS _u(0x00020000) -#define PIO_SM0_EXECCTRL_OUT_STICKY_MSB _u(17) -#define PIO_SM0_EXECCTRL_OUT_STICKY_LSB _u(17) -#define PIO_SM0_EXECCTRL_OUT_STICKY_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM0_EXECCTRL_WRAP_TOP -// Description : After reaching this address, execution is wrapped to -// wrap_bottom. -// If the instruction is a jump, and the jump condition is true, -// the jump takes priority. -#define PIO_SM0_EXECCTRL_WRAP_TOP_RESET _u(0x1f) -#define PIO_SM0_EXECCTRL_WRAP_TOP_BITS _u(0x0001f000) -#define PIO_SM0_EXECCTRL_WRAP_TOP_MSB _u(16) -#define PIO_SM0_EXECCTRL_WRAP_TOP_LSB _u(12) -#define PIO_SM0_EXECCTRL_WRAP_TOP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM0_EXECCTRL_WRAP_BOTTOM -// Description : After reaching wrap_top, execution is wrapped to this address. -#define PIO_SM0_EXECCTRL_WRAP_BOTTOM_RESET _u(0x00) -#define PIO_SM0_EXECCTRL_WRAP_BOTTOM_BITS _u(0x00000f80) -#define PIO_SM0_EXECCTRL_WRAP_BOTTOM_MSB _u(11) -#define PIO_SM0_EXECCTRL_WRAP_BOTTOM_LSB _u(7) -#define PIO_SM0_EXECCTRL_WRAP_BOTTOM_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM0_EXECCTRL_STATUS_SEL -// Description : Comparison used for the MOV x, STATUS instruction. -// 0x0 -> All-ones if TX FIFO level < N, otherwise all-zeroes -// 0x1 -> All-ones if RX FIFO level < N, otherwise all-zeroes -#define PIO_SM0_EXECCTRL_STATUS_SEL_RESET _u(0x0) -#define PIO_SM0_EXECCTRL_STATUS_SEL_BITS _u(0x00000010) -#define PIO_SM0_EXECCTRL_STATUS_SEL_MSB _u(4) -#define PIO_SM0_EXECCTRL_STATUS_SEL_LSB _u(4) -#define PIO_SM0_EXECCTRL_STATUS_SEL_ACCESS "RW" -#define PIO_SM0_EXECCTRL_STATUS_SEL_VALUE_TXLEVEL _u(0x0) -#define PIO_SM0_EXECCTRL_STATUS_SEL_VALUE_RXLEVEL _u(0x1) -// ----------------------------------------------------------------------------- -// Field : PIO_SM0_EXECCTRL_STATUS_N -// Description : Comparison level for the MOV x, STATUS instruction -#define PIO_SM0_EXECCTRL_STATUS_N_RESET _u(0x0) -#define PIO_SM0_EXECCTRL_STATUS_N_BITS _u(0x0000000f) -#define PIO_SM0_EXECCTRL_STATUS_N_MSB _u(3) -#define PIO_SM0_EXECCTRL_STATUS_N_LSB _u(0) -#define PIO_SM0_EXECCTRL_STATUS_N_ACCESS "RW" -// ============================================================================= -// Register : PIO_SM0_SHIFTCTRL -// Description : Control behaviour of the input/output shift registers for state -// machine 0 -#define PIO_SM0_SHIFTCTRL_OFFSET _u(0x000000d0) -#define PIO_SM0_SHIFTCTRL_BITS _u(0xffff0000) -#define PIO_SM0_SHIFTCTRL_RESET _u(0x000c0000) -// ----------------------------------------------------------------------------- -// Field : PIO_SM0_SHIFTCTRL_FJOIN_RX -// Description : When 1, RX FIFO steals the TX FIFO's storage, and becomes twice -// as deep. -// TX FIFO is disabled as a result (always reads as both full and -// empty). -// FIFOs are flushed when this bit is changed. -#define PIO_SM0_SHIFTCTRL_FJOIN_RX_RESET _u(0x0) -#define PIO_SM0_SHIFTCTRL_FJOIN_RX_BITS _u(0x80000000) -#define PIO_SM0_SHIFTCTRL_FJOIN_RX_MSB _u(31) -#define PIO_SM0_SHIFTCTRL_FJOIN_RX_LSB _u(31) -#define PIO_SM0_SHIFTCTRL_FJOIN_RX_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM0_SHIFTCTRL_FJOIN_TX -// Description : When 1, TX FIFO steals the RX FIFO's storage, and becomes twice -// as deep. -// RX FIFO is disabled as a result (always reads as both full and -// empty). -// FIFOs are flushed when this bit is changed. -#define PIO_SM0_SHIFTCTRL_FJOIN_TX_RESET _u(0x0) -#define PIO_SM0_SHIFTCTRL_FJOIN_TX_BITS _u(0x40000000) -#define PIO_SM0_SHIFTCTRL_FJOIN_TX_MSB _u(30) -#define PIO_SM0_SHIFTCTRL_FJOIN_TX_LSB _u(30) -#define PIO_SM0_SHIFTCTRL_FJOIN_TX_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM0_SHIFTCTRL_PULL_THRESH -// Description : Number of bits shifted out of OSR before autopull, or -// conditional pull (PULL IFEMPTY), will take place. -// Write 0 for value of 32. -#define PIO_SM0_SHIFTCTRL_PULL_THRESH_RESET _u(0x00) -#define PIO_SM0_SHIFTCTRL_PULL_THRESH_BITS _u(0x3e000000) -#define PIO_SM0_SHIFTCTRL_PULL_THRESH_MSB _u(29) -#define PIO_SM0_SHIFTCTRL_PULL_THRESH_LSB _u(25) -#define PIO_SM0_SHIFTCTRL_PULL_THRESH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM0_SHIFTCTRL_PUSH_THRESH -// Description : Number of bits shifted into ISR before autopush, or conditional -// push (PUSH IFFULL), will take place. -// Write 0 for value of 32. -#define PIO_SM0_SHIFTCTRL_PUSH_THRESH_RESET _u(0x00) -#define PIO_SM0_SHIFTCTRL_PUSH_THRESH_BITS _u(0x01f00000) -#define PIO_SM0_SHIFTCTRL_PUSH_THRESH_MSB _u(24) -#define PIO_SM0_SHIFTCTRL_PUSH_THRESH_LSB _u(20) -#define PIO_SM0_SHIFTCTRL_PUSH_THRESH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR -// Description : 1 = shift out of output shift register to right. 0 = to left. -#define PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR_RESET _u(0x1) -#define PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR_BITS _u(0x00080000) -#define PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR_MSB _u(19) -#define PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR_LSB _u(19) -#define PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM0_SHIFTCTRL_IN_SHIFTDIR -// Description : 1 = shift input shift register to right (data enters from -// left). 0 = to left. -#define PIO_SM0_SHIFTCTRL_IN_SHIFTDIR_RESET _u(0x1) -#define PIO_SM0_SHIFTCTRL_IN_SHIFTDIR_BITS _u(0x00040000) -#define PIO_SM0_SHIFTCTRL_IN_SHIFTDIR_MSB _u(18) -#define PIO_SM0_SHIFTCTRL_IN_SHIFTDIR_LSB _u(18) -#define PIO_SM0_SHIFTCTRL_IN_SHIFTDIR_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM0_SHIFTCTRL_AUTOPULL -// Description : Pull automatically when the output shift register is emptied, -// i.e. on or following an OUT instruction which causes the output -// shift counter to reach or exceed PULL_THRESH. -#define PIO_SM0_SHIFTCTRL_AUTOPULL_RESET _u(0x0) -#define PIO_SM0_SHIFTCTRL_AUTOPULL_BITS _u(0x00020000) -#define PIO_SM0_SHIFTCTRL_AUTOPULL_MSB _u(17) -#define PIO_SM0_SHIFTCTRL_AUTOPULL_LSB _u(17) -#define PIO_SM0_SHIFTCTRL_AUTOPULL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM0_SHIFTCTRL_AUTOPUSH -// Description : Push automatically when the input shift register is filled, -// i.e. on an IN instruction which causes the input shift counter -// to reach or exceed PUSH_THRESH. -#define PIO_SM0_SHIFTCTRL_AUTOPUSH_RESET _u(0x0) -#define PIO_SM0_SHIFTCTRL_AUTOPUSH_BITS _u(0x00010000) -#define PIO_SM0_SHIFTCTRL_AUTOPUSH_MSB _u(16) -#define PIO_SM0_SHIFTCTRL_AUTOPUSH_LSB _u(16) -#define PIO_SM0_SHIFTCTRL_AUTOPUSH_ACCESS "RW" -// ============================================================================= -// Register : PIO_SM0_ADDR -// Description : Current instruction address of state machine 0 -#define PIO_SM0_ADDR_OFFSET _u(0x000000d4) -#define PIO_SM0_ADDR_BITS _u(0x0000001f) -#define PIO_SM0_ADDR_RESET _u(0x00000000) -#define PIO_SM0_ADDR_MSB _u(4) -#define PIO_SM0_ADDR_LSB _u(0) -#define PIO_SM0_ADDR_ACCESS "RO" -// ============================================================================= -// Register : PIO_SM0_INSTR -// Description : Read to see the instruction currently addressed by state -// machine 0's program counter -// Write to execute an instruction immediately (including jumps) -// and then resume execution. -#define PIO_SM0_INSTR_OFFSET _u(0x000000d8) -#define PIO_SM0_INSTR_BITS _u(0x0000ffff) -#define PIO_SM0_INSTR_RESET "-" -#define PIO_SM0_INSTR_MSB _u(15) -#define PIO_SM0_INSTR_LSB _u(0) -#define PIO_SM0_INSTR_ACCESS "RW" -// ============================================================================= -// Register : PIO_SM0_PINCTRL -// Description : State machine pin control -#define PIO_SM0_PINCTRL_OFFSET _u(0x000000dc) -#define PIO_SM0_PINCTRL_BITS _u(0xffffffff) -#define PIO_SM0_PINCTRL_RESET _u(0x14000000) -// ----------------------------------------------------------------------------- -// Field : PIO_SM0_PINCTRL_SIDESET_COUNT -// Description : The number of MSBs of the Delay/Side-set instruction field -// which are used for side-set. Inclusive of the enable bit, if -// present. Minimum of 0 (all delay bits, no side-set) and maximum -// of 5 (all side-set, no delay). -#define PIO_SM0_PINCTRL_SIDESET_COUNT_RESET _u(0x0) -#define PIO_SM0_PINCTRL_SIDESET_COUNT_BITS _u(0xe0000000) -#define PIO_SM0_PINCTRL_SIDESET_COUNT_MSB _u(31) -#define PIO_SM0_PINCTRL_SIDESET_COUNT_LSB _u(29) -#define PIO_SM0_PINCTRL_SIDESET_COUNT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM0_PINCTRL_SET_COUNT -// Description : The number of pins asserted by a SET. In the range 0 to 5 -// inclusive. -#define PIO_SM0_PINCTRL_SET_COUNT_RESET _u(0x5) -#define PIO_SM0_PINCTRL_SET_COUNT_BITS _u(0x1c000000) -#define PIO_SM0_PINCTRL_SET_COUNT_MSB _u(28) -#define PIO_SM0_PINCTRL_SET_COUNT_LSB _u(26) -#define PIO_SM0_PINCTRL_SET_COUNT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM0_PINCTRL_OUT_COUNT -// Description : The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV -// PINS instruction. In the range 0 to 32 inclusive. -#define PIO_SM0_PINCTRL_OUT_COUNT_RESET _u(0x00) -#define PIO_SM0_PINCTRL_OUT_COUNT_BITS _u(0x03f00000) -#define PIO_SM0_PINCTRL_OUT_COUNT_MSB _u(25) -#define PIO_SM0_PINCTRL_OUT_COUNT_LSB _u(20) -#define PIO_SM0_PINCTRL_OUT_COUNT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM0_PINCTRL_IN_BASE -// Description : The pin which is mapped to the least-significant bit of a state -// machine's IN data bus. Higher-numbered pins are mapped to -// consecutively more-significant data bits, with a modulo of 32 -// applied to pin number. -#define PIO_SM0_PINCTRL_IN_BASE_RESET _u(0x00) -#define PIO_SM0_PINCTRL_IN_BASE_BITS _u(0x000f8000) -#define PIO_SM0_PINCTRL_IN_BASE_MSB _u(19) -#define PIO_SM0_PINCTRL_IN_BASE_LSB _u(15) -#define PIO_SM0_PINCTRL_IN_BASE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM0_PINCTRL_SIDESET_BASE -// Description : The lowest-numbered pin that will be affected by a side-set -// operation. The MSBs of an instruction's side-set/delay field -// (up to 5, determined by SIDESET_COUNT) are used for side-set -// data, with the remaining LSBs used for delay. The least- -// significant bit of the side-set portion is the bit written to -// this pin, with more-significant bits written to higher-numbered -// pins. -#define PIO_SM0_PINCTRL_SIDESET_BASE_RESET _u(0x00) -#define PIO_SM0_PINCTRL_SIDESET_BASE_BITS _u(0x00007c00) -#define PIO_SM0_PINCTRL_SIDESET_BASE_MSB _u(14) -#define PIO_SM0_PINCTRL_SIDESET_BASE_LSB _u(10) -#define PIO_SM0_PINCTRL_SIDESET_BASE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM0_PINCTRL_SET_BASE -// Description : The lowest-numbered pin that will be affected by a SET PINS or -// SET PINDIRS instruction. The data written to this pin is the -// least-significant bit of the SET data. -#define PIO_SM0_PINCTRL_SET_BASE_RESET _u(0x00) -#define PIO_SM0_PINCTRL_SET_BASE_BITS _u(0x000003e0) -#define PIO_SM0_PINCTRL_SET_BASE_MSB _u(9) -#define PIO_SM0_PINCTRL_SET_BASE_LSB _u(5) -#define PIO_SM0_PINCTRL_SET_BASE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM0_PINCTRL_OUT_BASE -// Description : The lowest-numbered pin that will be affected by an OUT PINS, -// OUT PINDIRS or MOV PINS instruction. The data written to this -// pin will always be the least-significant bit of the OUT or MOV -// data. -#define PIO_SM0_PINCTRL_OUT_BASE_RESET _u(0x00) -#define PIO_SM0_PINCTRL_OUT_BASE_BITS _u(0x0000001f) -#define PIO_SM0_PINCTRL_OUT_BASE_MSB _u(4) -#define PIO_SM0_PINCTRL_OUT_BASE_LSB _u(0) -#define PIO_SM0_PINCTRL_OUT_BASE_ACCESS "RW" -// ============================================================================= -// Register : PIO_SM1_CLKDIV -// Description : Clock divisor register for state machine 1 -// Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) -#define PIO_SM1_CLKDIV_OFFSET _u(0x000000e0) -#define PIO_SM1_CLKDIV_BITS _u(0xffffff00) -#define PIO_SM1_CLKDIV_RESET _u(0x00010000) -// ----------------------------------------------------------------------------- -// Field : PIO_SM1_CLKDIV_INT -// Description : Effective frequency is sysclk/(int + frac/256). -// Value of 0 is interpreted as 65536. If INT is 0, FRAC must also -// be 0. -#define PIO_SM1_CLKDIV_INT_RESET _u(0x0001) -#define PIO_SM1_CLKDIV_INT_BITS _u(0xffff0000) -#define PIO_SM1_CLKDIV_INT_MSB _u(31) -#define PIO_SM1_CLKDIV_INT_LSB _u(16) -#define PIO_SM1_CLKDIV_INT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM1_CLKDIV_FRAC -// Description : Fractional part of clock divisor -#define PIO_SM1_CLKDIV_FRAC_RESET _u(0x00) -#define PIO_SM1_CLKDIV_FRAC_BITS _u(0x0000ff00) -#define PIO_SM1_CLKDIV_FRAC_MSB _u(15) -#define PIO_SM1_CLKDIV_FRAC_LSB _u(8) -#define PIO_SM1_CLKDIV_FRAC_ACCESS "RW" -// ============================================================================= -// Register : PIO_SM1_EXECCTRL -// Description : Execution/behavioural settings for state machine 1 -#define PIO_SM1_EXECCTRL_OFFSET _u(0x000000e4) -#define PIO_SM1_EXECCTRL_BITS _u(0xffffff9f) -#define PIO_SM1_EXECCTRL_RESET _u(0x0001f000) -// ----------------------------------------------------------------------------- -// Field : PIO_SM1_EXECCTRL_EXEC_STALLED -// Description : If 1, an instruction written to SMx_INSTR is stalled, and -// latched by the state machine. Will clear to 0 once this -// instruction completes. -#define PIO_SM1_EXECCTRL_EXEC_STALLED_RESET _u(0x0) -#define PIO_SM1_EXECCTRL_EXEC_STALLED_BITS _u(0x80000000) -#define PIO_SM1_EXECCTRL_EXEC_STALLED_MSB _u(31) -#define PIO_SM1_EXECCTRL_EXEC_STALLED_LSB _u(31) -#define PIO_SM1_EXECCTRL_EXEC_STALLED_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PIO_SM1_EXECCTRL_SIDE_EN -// Description : If 1, the MSB of the Delay/Side-set instruction field is used -// as side-set enable, rather than a side-set data bit. This -// allows instructions to perform side-set optionally, rather than -// on every instruction, but the maximum possible side-set width -// is reduced from 5 to 4. Note that the value of -// PINCTRL_SIDESET_COUNT is inclusive of this enable bit. -#define PIO_SM1_EXECCTRL_SIDE_EN_RESET _u(0x0) -#define PIO_SM1_EXECCTRL_SIDE_EN_BITS _u(0x40000000) -#define PIO_SM1_EXECCTRL_SIDE_EN_MSB _u(30) -#define PIO_SM1_EXECCTRL_SIDE_EN_LSB _u(30) -#define PIO_SM1_EXECCTRL_SIDE_EN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM1_EXECCTRL_SIDE_PINDIR -// Description : If 1, side-set data is asserted to pin directions, instead of -// pin values -#define PIO_SM1_EXECCTRL_SIDE_PINDIR_RESET _u(0x0) -#define PIO_SM1_EXECCTRL_SIDE_PINDIR_BITS _u(0x20000000) -#define PIO_SM1_EXECCTRL_SIDE_PINDIR_MSB _u(29) -#define PIO_SM1_EXECCTRL_SIDE_PINDIR_LSB _u(29) -#define PIO_SM1_EXECCTRL_SIDE_PINDIR_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM1_EXECCTRL_JMP_PIN -// Description : The GPIO number to use as condition for JMP PIN. Unaffected by -// input mapping. -#define PIO_SM1_EXECCTRL_JMP_PIN_RESET _u(0x00) -#define PIO_SM1_EXECCTRL_JMP_PIN_BITS _u(0x1f000000) -#define PIO_SM1_EXECCTRL_JMP_PIN_MSB _u(28) -#define PIO_SM1_EXECCTRL_JMP_PIN_LSB _u(24) -#define PIO_SM1_EXECCTRL_JMP_PIN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM1_EXECCTRL_OUT_EN_SEL -// Description : Which data bit to use for inline OUT enable -#define PIO_SM1_EXECCTRL_OUT_EN_SEL_RESET _u(0x00) -#define PIO_SM1_EXECCTRL_OUT_EN_SEL_BITS _u(0x00f80000) -#define PIO_SM1_EXECCTRL_OUT_EN_SEL_MSB _u(23) -#define PIO_SM1_EXECCTRL_OUT_EN_SEL_LSB _u(19) -#define PIO_SM1_EXECCTRL_OUT_EN_SEL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM1_EXECCTRL_INLINE_OUT_EN -// Description : If 1, use a bit of OUT data as an auxiliary write enable -// When used in conjunction with OUT_STICKY, writes with an enable -// of 0 will -// deassert the latest pin write. This can create useful -// masking/override behaviour -// due to the priority ordering of state machine pin writes (SM0 < -// SM1 < ...) -#define PIO_SM1_EXECCTRL_INLINE_OUT_EN_RESET _u(0x0) -#define PIO_SM1_EXECCTRL_INLINE_OUT_EN_BITS _u(0x00040000) -#define PIO_SM1_EXECCTRL_INLINE_OUT_EN_MSB _u(18) -#define PIO_SM1_EXECCTRL_INLINE_OUT_EN_LSB _u(18) -#define PIO_SM1_EXECCTRL_INLINE_OUT_EN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM1_EXECCTRL_OUT_STICKY -// Description : Continuously assert the most recent OUT/SET to the pins -#define PIO_SM1_EXECCTRL_OUT_STICKY_RESET _u(0x0) -#define PIO_SM1_EXECCTRL_OUT_STICKY_BITS _u(0x00020000) -#define PIO_SM1_EXECCTRL_OUT_STICKY_MSB _u(17) -#define PIO_SM1_EXECCTRL_OUT_STICKY_LSB _u(17) -#define PIO_SM1_EXECCTRL_OUT_STICKY_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM1_EXECCTRL_WRAP_TOP -// Description : After reaching this address, execution is wrapped to -// wrap_bottom. -// If the instruction is a jump, and the jump condition is true, -// the jump takes priority. -#define PIO_SM1_EXECCTRL_WRAP_TOP_RESET _u(0x1f) -#define PIO_SM1_EXECCTRL_WRAP_TOP_BITS _u(0x0001f000) -#define PIO_SM1_EXECCTRL_WRAP_TOP_MSB _u(16) -#define PIO_SM1_EXECCTRL_WRAP_TOP_LSB _u(12) -#define PIO_SM1_EXECCTRL_WRAP_TOP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM1_EXECCTRL_WRAP_BOTTOM -// Description : After reaching wrap_top, execution is wrapped to this address. -#define PIO_SM1_EXECCTRL_WRAP_BOTTOM_RESET _u(0x00) -#define PIO_SM1_EXECCTRL_WRAP_BOTTOM_BITS _u(0x00000f80) -#define PIO_SM1_EXECCTRL_WRAP_BOTTOM_MSB _u(11) -#define PIO_SM1_EXECCTRL_WRAP_BOTTOM_LSB _u(7) -#define PIO_SM1_EXECCTRL_WRAP_BOTTOM_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM1_EXECCTRL_STATUS_SEL -// Description : Comparison used for the MOV x, STATUS instruction. -// 0x0 -> All-ones if TX FIFO level < N, otherwise all-zeroes -// 0x1 -> All-ones if RX FIFO level < N, otherwise all-zeroes -#define PIO_SM1_EXECCTRL_STATUS_SEL_RESET _u(0x0) -#define PIO_SM1_EXECCTRL_STATUS_SEL_BITS _u(0x00000010) -#define PIO_SM1_EXECCTRL_STATUS_SEL_MSB _u(4) -#define PIO_SM1_EXECCTRL_STATUS_SEL_LSB _u(4) -#define PIO_SM1_EXECCTRL_STATUS_SEL_ACCESS "RW" -#define PIO_SM1_EXECCTRL_STATUS_SEL_VALUE_TXLEVEL _u(0x0) -#define PIO_SM1_EXECCTRL_STATUS_SEL_VALUE_RXLEVEL _u(0x1) -// ----------------------------------------------------------------------------- -// Field : PIO_SM1_EXECCTRL_STATUS_N -// Description : Comparison level for the MOV x, STATUS instruction -#define PIO_SM1_EXECCTRL_STATUS_N_RESET _u(0x0) -#define PIO_SM1_EXECCTRL_STATUS_N_BITS _u(0x0000000f) -#define PIO_SM1_EXECCTRL_STATUS_N_MSB _u(3) -#define PIO_SM1_EXECCTRL_STATUS_N_LSB _u(0) -#define PIO_SM1_EXECCTRL_STATUS_N_ACCESS "RW" -// ============================================================================= -// Register : PIO_SM1_SHIFTCTRL -// Description : Control behaviour of the input/output shift registers for state -// machine 1 -#define PIO_SM1_SHIFTCTRL_OFFSET _u(0x000000e8) -#define PIO_SM1_SHIFTCTRL_BITS _u(0xffff0000) -#define PIO_SM1_SHIFTCTRL_RESET _u(0x000c0000) -// ----------------------------------------------------------------------------- -// Field : PIO_SM1_SHIFTCTRL_FJOIN_RX -// Description : When 1, RX FIFO steals the TX FIFO's storage, and becomes twice -// as deep. -// TX FIFO is disabled as a result (always reads as both full and -// empty). -// FIFOs are flushed when this bit is changed. -#define PIO_SM1_SHIFTCTRL_FJOIN_RX_RESET _u(0x0) -#define PIO_SM1_SHIFTCTRL_FJOIN_RX_BITS _u(0x80000000) -#define PIO_SM1_SHIFTCTRL_FJOIN_RX_MSB _u(31) -#define PIO_SM1_SHIFTCTRL_FJOIN_RX_LSB _u(31) -#define PIO_SM1_SHIFTCTRL_FJOIN_RX_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM1_SHIFTCTRL_FJOIN_TX -// Description : When 1, TX FIFO steals the RX FIFO's storage, and becomes twice -// as deep. -// RX FIFO is disabled as a result (always reads as both full and -// empty). -// FIFOs are flushed when this bit is changed. -#define PIO_SM1_SHIFTCTRL_FJOIN_TX_RESET _u(0x0) -#define PIO_SM1_SHIFTCTRL_FJOIN_TX_BITS _u(0x40000000) -#define PIO_SM1_SHIFTCTRL_FJOIN_TX_MSB _u(30) -#define PIO_SM1_SHIFTCTRL_FJOIN_TX_LSB _u(30) -#define PIO_SM1_SHIFTCTRL_FJOIN_TX_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM1_SHIFTCTRL_PULL_THRESH -// Description : Number of bits shifted out of OSR before autopull, or -// conditional pull (PULL IFEMPTY), will take place. -// Write 0 for value of 32. -#define PIO_SM1_SHIFTCTRL_PULL_THRESH_RESET _u(0x00) -#define PIO_SM1_SHIFTCTRL_PULL_THRESH_BITS _u(0x3e000000) -#define PIO_SM1_SHIFTCTRL_PULL_THRESH_MSB _u(29) -#define PIO_SM1_SHIFTCTRL_PULL_THRESH_LSB _u(25) -#define PIO_SM1_SHIFTCTRL_PULL_THRESH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM1_SHIFTCTRL_PUSH_THRESH -// Description : Number of bits shifted into ISR before autopush, or conditional -// push (PUSH IFFULL), will take place. -// Write 0 for value of 32. -#define PIO_SM1_SHIFTCTRL_PUSH_THRESH_RESET _u(0x00) -#define PIO_SM1_SHIFTCTRL_PUSH_THRESH_BITS _u(0x01f00000) -#define PIO_SM1_SHIFTCTRL_PUSH_THRESH_MSB _u(24) -#define PIO_SM1_SHIFTCTRL_PUSH_THRESH_LSB _u(20) -#define PIO_SM1_SHIFTCTRL_PUSH_THRESH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM1_SHIFTCTRL_OUT_SHIFTDIR -// Description : 1 = shift out of output shift register to right. 0 = to left. -#define PIO_SM1_SHIFTCTRL_OUT_SHIFTDIR_RESET _u(0x1) -#define PIO_SM1_SHIFTCTRL_OUT_SHIFTDIR_BITS _u(0x00080000) -#define PIO_SM1_SHIFTCTRL_OUT_SHIFTDIR_MSB _u(19) -#define PIO_SM1_SHIFTCTRL_OUT_SHIFTDIR_LSB _u(19) -#define PIO_SM1_SHIFTCTRL_OUT_SHIFTDIR_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM1_SHIFTCTRL_IN_SHIFTDIR -// Description : 1 = shift input shift register to right (data enters from -// left). 0 = to left. -#define PIO_SM1_SHIFTCTRL_IN_SHIFTDIR_RESET _u(0x1) -#define PIO_SM1_SHIFTCTRL_IN_SHIFTDIR_BITS _u(0x00040000) -#define PIO_SM1_SHIFTCTRL_IN_SHIFTDIR_MSB _u(18) -#define PIO_SM1_SHIFTCTRL_IN_SHIFTDIR_LSB _u(18) -#define PIO_SM1_SHIFTCTRL_IN_SHIFTDIR_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM1_SHIFTCTRL_AUTOPULL -// Description : Pull automatically when the output shift register is emptied, -// i.e. on or following an OUT instruction which causes the output -// shift counter to reach or exceed PULL_THRESH. -#define PIO_SM1_SHIFTCTRL_AUTOPULL_RESET _u(0x0) -#define PIO_SM1_SHIFTCTRL_AUTOPULL_BITS _u(0x00020000) -#define PIO_SM1_SHIFTCTRL_AUTOPULL_MSB _u(17) -#define PIO_SM1_SHIFTCTRL_AUTOPULL_LSB _u(17) -#define PIO_SM1_SHIFTCTRL_AUTOPULL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM1_SHIFTCTRL_AUTOPUSH -// Description : Push automatically when the input shift register is filled, -// i.e. on an IN instruction which causes the input shift counter -// to reach or exceed PUSH_THRESH. -#define PIO_SM1_SHIFTCTRL_AUTOPUSH_RESET _u(0x0) -#define PIO_SM1_SHIFTCTRL_AUTOPUSH_BITS _u(0x00010000) -#define PIO_SM1_SHIFTCTRL_AUTOPUSH_MSB _u(16) -#define PIO_SM1_SHIFTCTRL_AUTOPUSH_LSB _u(16) -#define PIO_SM1_SHIFTCTRL_AUTOPUSH_ACCESS "RW" -// ============================================================================= -// Register : PIO_SM1_ADDR -// Description : Current instruction address of state machine 1 -#define PIO_SM1_ADDR_OFFSET _u(0x000000ec) -#define PIO_SM1_ADDR_BITS _u(0x0000001f) -#define PIO_SM1_ADDR_RESET _u(0x00000000) -#define PIO_SM1_ADDR_MSB _u(4) -#define PIO_SM1_ADDR_LSB _u(0) -#define PIO_SM1_ADDR_ACCESS "RO" -// ============================================================================= -// Register : PIO_SM1_INSTR -// Description : Read to see the instruction currently addressed by state -// machine 1's program counter -// Write to execute an instruction immediately (including jumps) -// and then resume execution. -#define PIO_SM1_INSTR_OFFSET _u(0x000000f0) -#define PIO_SM1_INSTR_BITS _u(0x0000ffff) -#define PIO_SM1_INSTR_RESET "-" -#define PIO_SM1_INSTR_MSB _u(15) -#define PIO_SM1_INSTR_LSB _u(0) -#define PIO_SM1_INSTR_ACCESS "RW" -// ============================================================================= -// Register : PIO_SM1_PINCTRL -// Description : State machine pin control -#define PIO_SM1_PINCTRL_OFFSET _u(0x000000f4) -#define PIO_SM1_PINCTRL_BITS _u(0xffffffff) -#define PIO_SM1_PINCTRL_RESET _u(0x14000000) -// ----------------------------------------------------------------------------- -// Field : PIO_SM1_PINCTRL_SIDESET_COUNT -// Description : The number of MSBs of the Delay/Side-set instruction field -// which are used for side-set. Inclusive of the enable bit, if -// present. Minimum of 0 (all delay bits, no side-set) and maximum -// of 5 (all side-set, no delay). -#define PIO_SM1_PINCTRL_SIDESET_COUNT_RESET _u(0x0) -#define PIO_SM1_PINCTRL_SIDESET_COUNT_BITS _u(0xe0000000) -#define PIO_SM1_PINCTRL_SIDESET_COUNT_MSB _u(31) -#define PIO_SM1_PINCTRL_SIDESET_COUNT_LSB _u(29) -#define PIO_SM1_PINCTRL_SIDESET_COUNT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM1_PINCTRL_SET_COUNT -// Description : The number of pins asserted by a SET. In the range 0 to 5 -// inclusive. -#define PIO_SM1_PINCTRL_SET_COUNT_RESET _u(0x5) -#define PIO_SM1_PINCTRL_SET_COUNT_BITS _u(0x1c000000) -#define PIO_SM1_PINCTRL_SET_COUNT_MSB _u(28) -#define PIO_SM1_PINCTRL_SET_COUNT_LSB _u(26) -#define PIO_SM1_PINCTRL_SET_COUNT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM1_PINCTRL_OUT_COUNT -// Description : The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV -// PINS instruction. In the range 0 to 32 inclusive. -#define PIO_SM1_PINCTRL_OUT_COUNT_RESET _u(0x00) -#define PIO_SM1_PINCTRL_OUT_COUNT_BITS _u(0x03f00000) -#define PIO_SM1_PINCTRL_OUT_COUNT_MSB _u(25) -#define PIO_SM1_PINCTRL_OUT_COUNT_LSB _u(20) -#define PIO_SM1_PINCTRL_OUT_COUNT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM1_PINCTRL_IN_BASE -// Description : The pin which is mapped to the least-significant bit of a state -// machine's IN data bus. Higher-numbered pins are mapped to -// consecutively more-significant data bits, with a modulo of 32 -// applied to pin number. -#define PIO_SM1_PINCTRL_IN_BASE_RESET _u(0x00) -#define PIO_SM1_PINCTRL_IN_BASE_BITS _u(0x000f8000) -#define PIO_SM1_PINCTRL_IN_BASE_MSB _u(19) -#define PIO_SM1_PINCTRL_IN_BASE_LSB _u(15) -#define PIO_SM1_PINCTRL_IN_BASE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM1_PINCTRL_SIDESET_BASE -// Description : The lowest-numbered pin that will be affected by a side-set -// operation. The MSBs of an instruction's side-set/delay field -// (up to 5, determined by SIDESET_COUNT) are used for side-set -// data, with the remaining LSBs used for delay. The least- -// significant bit of the side-set portion is the bit written to -// this pin, with more-significant bits written to higher-numbered -// pins. -#define PIO_SM1_PINCTRL_SIDESET_BASE_RESET _u(0x00) -#define PIO_SM1_PINCTRL_SIDESET_BASE_BITS _u(0x00007c00) -#define PIO_SM1_PINCTRL_SIDESET_BASE_MSB _u(14) -#define PIO_SM1_PINCTRL_SIDESET_BASE_LSB _u(10) -#define PIO_SM1_PINCTRL_SIDESET_BASE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM1_PINCTRL_SET_BASE -// Description : The lowest-numbered pin that will be affected by a SET PINS or -// SET PINDIRS instruction. The data written to this pin is the -// least-significant bit of the SET data. -#define PIO_SM1_PINCTRL_SET_BASE_RESET _u(0x00) -#define PIO_SM1_PINCTRL_SET_BASE_BITS _u(0x000003e0) -#define PIO_SM1_PINCTRL_SET_BASE_MSB _u(9) -#define PIO_SM1_PINCTRL_SET_BASE_LSB _u(5) -#define PIO_SM1_PINCTRL_SET_BASE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM1_PINCTRL_OUT_BASE -// Description : The lowest-numbered pin that will be affected by an OUT PINS, -// OUT PINDIRS or MOV PINS instruction. The data written to this -// pin will always be the least-significant bit of the OUT or MOV -// data. -#define PIO_SM1_PINCTRL_OUT_BASE_RESET _u(0x00) -#define PIO_SM1_PINCTRL_OUT_BASE_BITS _u(0x0000001f) -#define PIO_SM1_PINCTRL_OUT_BASE_MSB _u(4) -#define PIO_SM1_PINCTRL_OUT_BASE_LSB _u(0) -#define PIO_SM1_PINCTRL_OUT_BASE_ACCESS "RW" -// ============================================================================= -// Register : PIO_SM2_CLKDIV -// Description : Clock divisor register for state machine 2 -// Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) -#define PIO_SM2_CLKDIV_OFFSET _u(0x000000f8) -#define PIO_SM2_CLKDIV_BITS _u(0xffffff00) -#define PIO_SM2_CLKDIV_RESET _u(0x00010000) -// ----------------------------------------------------------------------------- -// Field : PIO_SM2_CLKDIV_INT -// Description : Effective frequency is sysclk/(int + frac/256). -// Value of 0 is interpreted as 65536. If INT is 0, FRAC must also -// be 0. -#define PIO_SM2_CLKDIV_INT_RESET _u(0x0001) -#define PIO_SM2_CLKDIV_INT_BITS _u(0xffff0000) -#define PIO_SM2_CLKDIV_INT_MSB _u(31) -#define PIO_SM2_CLKDIV_INT_LSB _u(16) -#define PIO_SM2_CLKDIV_INT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM2_CLKDIV_FRAC -// Description : Fractional part of clock divisor -#define PIO_SM2_CLKDIV_FRAC_RESET _u(0x00) -#define PIO_SM2_CLKDIV_FRAC_BITS _u(0x0000ff00) -#define PIO_SM2_CLKDIV_FRAC_MSB _u(15) -#define PIO_SM2_CLKDIV_FRAC_LSB _u(8) -#define PIO_SM2_CLKDIV_FRAC_ACCESS "RW" -// ============================================================================= -// Register : PIO_SM2_EXECCTRL -// Description : Execution/behavioural settings for state machine 2 -#define PIO_SM2_EXECCTRL_OFFSET _u(0x000000fc) -#define PIO_SM2_EXECCTRL_BITS _u(0xffffff9f) -#define PIO_SM2_EXECCTRL_RESET _u(0x0001f000) -// ----------------------------------------------------------------------------- -// Field : PIO_SM2_EXECCTRL_EXEC_STALLED -// Description : If 1, an instruction written to SMx_INSTR is stalled, and -// latched by the state machine. Will clear to 0 once this -// instruction completes. -#define PIO_SM2_EXECCTRL_EXEC_STALLED_RESET _u(0x0) -#define PIO_SM2_EXECCTRL_EXEC_STALLED_BITS _u(0x80000000) -#define PIO_SM2_EXECCTRL_EXEC_STALLED_MSB _u(31) -#define PIO_SM2_EXECCTRL_EXEC_STALLED_LSB _u(31) -#define PIO_SM2_EXECCTRL_EXEC_STALLED_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PIO_SM2_EXECCTRL_SIDE_EN -// Description : If 1, the MSB of the Delay/Side-set instruction field is used -// as side-set enable, rather than a side-set data bit. This -// allows instructions to perform side-set optionally, rather than -// on every instruction, but the maximum possible side-set width -// is reduced from 5 to 4. Note that the value of -// PINCTRL_SIDESET_COUNT is inclusive of this enable bit. -#define PIO_SM2_EXECCTRL_SIDE_EN_RESET _u(0x0) -#define PIO_SM2_EXECCTRL_SIDE_EN_BITS _u(0x40000000) -#define PIO_SM2_EXECCTRL_SIDE_EN_MSB _u(30) -#define PIO_SM2_EXECCTRL_SIDE_EN_LSB _u(30) -#define PIO_SM2_EXECCTRL_SIDE_EN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM2_EXECCTRL_SIDE_PINDIR -// Description : If 1, side-set data is asserted to pin directions, instead of -// pin values -#define PIO_SM2_EXECCTRL_SIDE_PINDIR_RESET _u(0x0) -#define PIO_SM2_EXECCTRL_SIDE_PINDIR_BITS _u(0x20000000) -#define PIO_SM2_EXECCTRL_SIDE_PINDIR_MSB _u(29) -#define PIO_SM2_EXECCTRL_SIDE_PINDIR_LSB _u(29) -#define PIO_SM2_EXECCTRL_SIDE_PINDIR_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM2_EXECCTRL_JMP_PIN -// Description : The GPIO number to use as condition for JMP PIN. Unaffected by -// input mapping. -#define PIO_SM2_EXECCTRL_JMP_PIN_RESET _u(0x00) -#define PIO_SM2_EXECCTRL_JMP_PIN_BITS _u(0x1f000000) -#define PIO_SM2_EXECCTRL_JMP_PIN_MSB _u(28) -#define PIO_SM2_EXECCTRL_JMP_PIN_LSB _u(24) -#define PIO_SM2_EXECCTRL_JMP_PIN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM2_EXECCTRL_OUT_EN_SEL -// Description : Which data bit to use for inline OUT enable -#define PIO_SM2_EXECCTRL_OUT_EN_SEL_RESET _u(0x00) -#define PIO_SM2_EXECCTRL_OUT_EN_SEL_BITS _u(0x00f80000) -#define PIO_SM2_EXECCTRL_OUT_EN_SEL_MSB _u(23) -#define PIO_SM2_EXECCTRL_OUT_EN_SEL_LSB _u(19) -#define PIO_SM2_EXECCTRL_OUT_EN_SEL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM2_EXECCTRL_INLINE_OUT_EN -// Description : If 1, use a bit of OUT data as an auxiliary write enable -// When used in conjunction with OUT_STICKY, writes with an enable -// of 0 will -// deassert the latest pin write. This can create useful -// masking/override behaviour -// due to the priority ordering of state machine pin writes (SM0 < -// SM1 < ...) -#define PIO_SM2_EXECCTRL_INLINE_OUT_EN_RESET _u(0x0) -#define PIO_SM2_EXECCTRL_INLINE_OUT_EN_BITS _u(0x00040000) -#define PIO_SM2_EXECCTRL_INLINE_OUT_EN_MSB _u(18) -#define PIO_SM2_EXECCTRL_INLINE_OUT_EN_LSB _u(18) -#define PIO_SM2_EXECCTRL_INLINE_OUT_EN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM2_EXECCTRL_OUT_STICKY -// Description : Continuously assert the most recent OUT/SET to the pins -#define PIO_SM2_EXECCTRL_OUT_STICKY_RESET _u(0x0) -#define PIO_SM2_EXECCTRL_OUT_STICKY_BITS _u(0x00020000) -#define PIO_SM2_EXECCTRL_OUT_STICKY_MSB _u(17) -#define PIO_SM2_EXECCTRL_OUT_STICKY_LSB _u(17) -#define PIO_SM2_EXECCTRL_OUT_STICKY_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM2_EXECCTRL_WRAP_TOP -// Description : After reaching this address, execution is wrapped to -// wrap_bottom. -// If the instruction is a jump, and the jump condition is true, -// the jump takes priority. -#define PIO_SM2_EXECCTRL_WRAP_TOP_RESET _u(0x1f) -#define PIO_SM2_EXECCTRL_WRAP_TOP_BITS _u(0x0001f000) -#define PIO_SM2_EXECCTRL_WRAP_TOP_MSB _u(16) -#define PIO_SM2_EXECCTRL_WRAP_TOP_LSB _u(12) -#define PIO_SM2_EXECCTRL_WRAP_TOP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM2_EXECCTRL_WRAP_BOTTOM -// Description : After reaching wrap_top, execution is wrapped to this address. -#define PIO_SM2_EXECCTRL_WRAP_BOTTOM_RESET _u(0x00) -#define PIO_SM2_EXECCTRL_WRAP_BOTTOM_BITS _u(0x00000f80) -#define PIO_SM2_EXECCTRL_WRAP_BOTTOM_MSB _u(11) -#define PIO_SM2_EXECCTRL_WRAP_BOTTOM_LSB _u(7) -#define PIO_SM2_EXECCTRL_WRAP_BOTTOM_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM2_EXECCTRL_STATUS_SEL -// Description : Comparison used for the MOV x, STATUS instruction. -// 0x0 -> All-ones if TX FIFO level < N, otherwise all-zeroes -// 0x1 -> All-ones if RX FIFO level < N, otherwise all-zeroes -#define PIO_SM2_EXECCTRL_STATUS_SEL_RESET _u(0x0) -#define PIO_SM2_EXECCTRL_STATUS_SEL_BITS _u(0x00000010) -#define PIO_SM2_EXECCTRL_STATUS_SEL_MSB _u(4) -#define PIO_SM2_EXECCTRL_STATUS_SEL_LSB _u(4) -#define PIO_SM2_EXECCTRL_STATUS_SEL_ACCESS "RW" -#define PIO_SM2_EXECCTRL_STATUS_SEL_VALUE_TXLEVEL _u(0x0) -#define PIO_SM2_EXECCTRL_STATUS_SEL_VALUE_RXLEVEL _u(0x1) -// ----------------------------------------------------------------------------- -// Field : PIO_SM2_EXECCTRL_STATUS_N -// Description : Comparison level for the MOV x, STATUS instruction -#define PIO_SM2_EXECCTRL_STATUS_N_RESET _u(0x0) -#define PIO_SM2_EXECCTRL_STATUS_N_BITS _u(0x0000000f) -#define PIO_SM2_EXECCTRL_STATUS_N_MSB _u(3) -#define PIO_SM2_EXECCTRL_STATUS_N_LSB _u(0) -#define PIO_SM2_EXECCTRL_STATUS_N_ACCESS "RW" -// ============================================================================= -// Register : PIO_SM2_SHIFTCTRL -// Description : Control behaviour of the input/output shift registers for state -// machine 2 -#define PIO_SM2_SHIFTCTRL_OFFSET _u(0x00000100) -#define PIO_SM2_SHIFTCTRL_BITS _u(0xffff0000) -#define PIO_SM2_SHIFTCTRL_RESET _u(0x000c0000) -// ----------------------------------------------------------------------------- -// Field : PIO_SM2_SHIFTCTRL_FJOIN_RX -// Description : When 1, RX FIFO steals the TX FIFO's storage, and becomes twice -// as deep. -// TX FIFO is disabled as a result (always reads as both full and -// empty). -// FIFOs are flushed when this bit is changed. -#define PIO_SM2_SHIFTCTRL_FJOIN_RX_RESET _u(0x0) -#define PIO_SM2_SHIFTCTRL_FJOIN_RX_BITS _u(0x80000000) -#define PIO_SM2_SHIFTCTRL_FJOIN_RX_MSB _u(31) -#define PIO_SM2_SHIFTCTRL_FJOIN_RX_LSB _u(31) -#define PIO_SM2_SHIFTCTRL_FJOIN_RX_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM2_SHIFTCTRL_FJOIN_TX -// Description : When 1, TX FIFO steals the RX FIFO's storage, and becomes twice -// as deep. -// RX FIFO is disabled as a result (always reads as both full and -// empty). -// FIFOs are flushed when this bit is changed. -#define PIO_SM2_SHIFTCTRL_FJOIN_TX_RESET _u(0x0) -#define PIO_SM2_SHIFTCTRL_FJOIN_TX_BITS _u(0x40000000) -#define PIO_SM2_SHIFTCTRL_FJOIN_TX_MSB _u(30) -#define PIO_SM2_SHIFTCTRL_FJOIN_TX_LSB _u(30) -#define PIO_SM2_SHIFTCTRL_FJOIN_TX_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM2_SHIFTCTRL_PULL_THRESH -// Description : Number of bits shifted out of OSR before autopull, or -// conditional pull (PULL IFEMPTY), will take place. -// Write 0 for value of 32. -#define PIO_SM2_SHIFTCTRL_PULL_THRESH_RESET _u(0x00) -#define PIO_SM2_SHIFTCTRL_PULL_THRESH_BITS _u(0x3e000000) -#define PIO_SM2_SHIFTCTRL_PULL_THRESH_MSB _u(29) -#define PIO_SM2_SHIFTCTRL_PULL_THRESH_LSB _u(25) -#define PIO_SM2_SHIFTCTRL_PULL_THRESH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM2_SHIFTCTRL_PUSH_THRESH -// Description : Number of bits shifted into ISR before autopush, or conditional -// push (PUSH IFFULL), will take place. -// Write 0 for value of 32. -#define PIO_SM2_SHIFTCTRL_PUSH_THRESH_RESET _u(0x00) -#define PIO_SM2_SHIFTCTRL_PUSH_THRESH_BITS _u(0x01f00000) -#define PIO_SM2_SHIFTCTRL_PUSH_THRESH_MSB _u(24) -#define PIO_SM2_SHIFTCTRL_PUSH_THRESH_LSB _u(20) -#define PIO_SM2_SHIFTCTRL_PUSH_THRESH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM2_SHIFTCTRL_OUT_SHIFTDIR -// Description : 1 = shift out of output shift register to right. 0 = to left. -#define PIO_SM2_SHIFTCTRL_OUT_SHIFTDIR_RESET _u(0x1) -#define PIO_SM2_SHIFTCTRL_OUT_SHIFTDIR_BITS _u(0x00080000) -#define PIO_SM2_SHIFTCTRL_OUT_SHIFTDIR_MSB _u(19) -#define PIO_SM2_SHIFTCTRL_OUT_SHIFTDIR_LSB _u(19) -#define PIO_SM2_SHIFTCTRL_OUT_SHIFTDIR_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM2_SHIFTCTRL_IN_SHIFTDIR -// Description : 1 = shift input shift register to right (data enters from -// left). 0 = to left. -#define PIO_SM2_SHIFTCTRL_IN_SHIFTDIR_RESET _u(0x1) -#define PIO_SM2_SHIFTCTRL_IN_SHIFTDIR_BITS _u(0x00040000) -#define PIO_SM2_SHIFTCTRL_IN_SHIFTDIR_MSB _u(18) -#define PIO_SM2_SHIFTCTRL_IN_SHIFTDIR_LSB _u(18) -#define PIO_SM2_SHIFTCTRL_IN_SHIFTDIR_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM2_SHIFTCTRL_AUTOPULL -// Description : Pull automatically when the output shift register is emptied, -// i.e. on or following an OUT instruction which causes the output -// shift counter to reach or exceed PULL_THRESH. -#define PIO_SM2_SHIFTCTRL_AUTOPULL_RESET _u(0x0) -#define PIO_SM2_SHIFTCTRL_AUTOPULL_BITS _u(0x00020000) -#define PIO_SM2_SHIFTCTRL_AUTOPULL_MSB _u(17) -#define PIO_SM2_SHIFTCTRL_AUTOPULL_LSB _u(17) -#define PIO_SM2_SHIFTCTRL_AUTOPULL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM2_SHIFTCTRL_AUTOPUSH -// Description : Push automatically when the input shift register is filled, -// i.e. on an IN instruction which causes the input shift counter -// to reach or exceed PUSH_THRESH. -#define PIO_SM2_SHIFTCTRL_AUTOPUSH_RESET _u(0x0) -#define PIO_SM2_SHIFTCTRL_AUTOPUSH_BITS _u(0x00010000) -#define PIO_SM2_SHIFTCTRL_AUTOPUSH_MSB _u(16) -#define PIO_SM2_SHIFTCTRL_AUTOPUSH_LSB _u(16) -#define PIO_SM2_SHIFTCTRL_AUTOPUSH_ACCESS "RW" -// ============================================================================= -// Register : PIO_SM2_ADDR -// Description : Current instruction address of state machine 2 -#define PIO_SM2_ADDR_OFFSET _u(0x00000104) -#define PIO_SM2_ADDR_BITS _u(0x0000001f) -#define PIO_SM2_ADDR_RESET _u(0x00000000) -#define PIO_SM2_ADDR_MSB _u(4) -#define PIO_SM2_ADDR_LSB _u(0) -#define PIO_SM2_ADDR_ACCESS "RO" -// ============================================================================= -// Register : PIO_SM2_INSTR -// Description : Read to see the instruction currently addressed by state -// machine 2's program counter -// Write to execute an instruction immediately (including jumps) -// and then resume execution. -#define PIO_SM2_INSTR_OFFSET _u(0x00000108) -#define PIO_SM2_INSTR_BITS _u(0x0000ffff) -#define PIO_SM2_INSTR_RESET "-" -#define PIO_SM2_INSTR_MSB _u(15) -#define PIO_SM2_INSTR_LSB _u(0) -#define PIO_SM2_INSTR_ACCESS "RW" -// ============================================================================= -// Register : PIO_SM2_PINCTRL -// Description : State machine pin control -#define PIO_SM2_PINCTRL_OFFSET _u(0x0000010c) -#define PIO_SM2_PINCTRL_BITS _u(0xffffffff) -#define PIO_SM2_PINCTRL_RESET _u(0x14000000) -// ----------------------------------------------------------------------------- -// Field : PIO_SM2_PINCTRL_SIDESET_COUNT -// Description : The number of MSBs of the Delay/Side-set instruction field -// which are used for side-set. Inclusive of the enable bit, if -// present. Minimum of 0 (all delay bits, no side-set) and maximum -// of 5 (all side-set, no delay). -#define PIO_SM2_PINCTRL_SIDESET_COUNT_RESET _u(0x0) -#define PIO_SM2_PINCTRL_SIDESET_COUNT_BITS _u(0xe0000000) -#define PIO_SM2_PINCTRL_SIDESET_COUNT_MSB _u(31) -#define PIO_SM2_PINCTRL_SIDESET_COUNT_LSB _u(29) -#define PIO_SM2_PINCTRL_SIDESET_COUNT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM2_PINCTRL_SET_COUNT -// Description : The number of pins asserted by a SET. In the range 0 to 5 -// inclusive. -#define PIO_SM2_PINCTRL_SET_COUNT_RESET _u(0x5) -#define PIO_SM2_PINCTRL_SET_COUNT_BITS _u(0x1c000000) -#define PIO_SM2_PINCTRL_SET_COUNT_MSB _u(28) -#define PIO_SM2_PINCTRL_SET_COUNT_LSB _u(26) -#define PIO_SM2_PINCTRL_SET_COUNT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM2_PINCTRL_OUT_COUNT -// Description : The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV -// PINS instruction. In the range 0 to 32 inclusive. -#define PIO_SM2_PINCTRL_OUT_COUNT_RESET _u(0x00) -#define PIO_SM2_PINCTRL_OUT_COUNT_BITS _u(0x03f00000) -#define PIO_SM2_PINCTRL_OUT_COUNT_MSB _u(25) -#define PIO_SM2_PINCTRL_OUT_COUNT_LSB _u(20) -#define PIO_SM2_PINCTRL_OUT_COUNT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM2_PINCTRL_IN_BASE -// Description : The pin which is mapped to the least-significant bit of a state -// machine's IN data bus. Higher-numbered pins are mapped to -// consecutively more-significant data bits, with a modulo of 32 -// applied to pin number. -#define PIO_SM2_PINCTRL_IN_BASE_RESET _u(0x00) -#define PIO_SM2_PINCTRL_IN_BASE_BITS _u(0x000f8000) -#define PIO_SM2_PINCTRL_IN_BASE_MSB _u(19) -#define PIO_SM2_PINCTRL_IN_BASE_LSB _u(15) -#define PIO_SM2_PINCTRL_IN_BASE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM2_PINCTRL_SIDESET_BASE -// Description : The lowest-numbered pin that will be affected by a side-set -// operation. The MSBs of an instruction's side-set/delay field -// (up to 5, determined by SIDESET_COUNT) are used for side-set -// data, with the remaining LSBs used for delay. The least- -// significant bit of the side-set portion is the bit written to -// this pin, with more-significant bits written to higher-numbered -// pins. -#define PIO_SM2_PINCTRL_SIDESET_BASE_RESET _u(0x00) -#define PIO_SM2_PINCTRL_SIDESET_BASE_BITS _u(0x00007c00) -#define PIO_SM2_PINCTRL_SIDESET_BASE_MSB _u(14) -#define PIO_SM2_PINCTRL_SIDESET_BASE_LSB _u(10) -#define PIO_SM2_PINCTRL_SIDESET_BASE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM2_PINCTRL_SET_BASE -// Description : The lowest-numbered pin that will be affected by a SET PINS or -// SET PINDIRS instruction. The data written to this pin is the -// least-significant bit of the SET data. -#define PIO_SM2_PINCTRL_SET_BASE_RESET _u(0x00) -#define PIO_SM2_PINCTRL_SET_BASE_BITS _u(0x000003e0) -#define PIO_SM2_PINCTRL_SET_BASE_MSB _u(9) -#define PIO_SM2_PINCTRL_SET_BASE_LSB _u(5) -#define PIO_SM2_PINCTRL_SET_BASE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM2_PINCTRL_OUT_BASE -// Description : The lowest-numbered pin that will be affected by an OUT PINS, -// OUT PINDIRS or MOV PINS instruction. The data written to this -// pin will always be the least-significant bit of the OUT or MOV -// data. -#define PIO_SM2_PINCTRL_OUT_BASE_RESET _u(0x00) -#define PIO_SM2_PINCTRL_OUT_BASE_BITS _u(0x0000001f) -#define PIO_SM2_PINCTRL_OUT_BASE_MSB _u(4) -#define PIO_SM2_PINCTRL_OUT_BASE_LSB _u(0) -#define PIO_SM2_PINCTRL_OUT_BASE_ACCESS "RW" -// ============================================================================= -// Register : PIO_SM3_CLKDIV -// Description : Clock divisor register for state machine 3 -// Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) -#define PIO_SM3_CLKDIV_OFFSET _u(0x00000110) -#define PIO_SM3_CLKDIV_BITS _u(0xffffff00) -#define PIO_SM3_CLKDIV_RESET _u(0x00010000) -// ----------------------------------------------------------------------------- -// Field : PIO_SM3_CLKDIV_INT -// Description : Effective frequency is sysclk/(int + frac/256). -// Value of 0 is interpreted as 65536. If INT is 0, FRAC must also -// be 0. -#define PIO_SM3_CLKDIV_INT_RESET _u(0x0001) -#define PIO_SM3_CLKDIV_INT_BITS _u(0xffff0000) -#define PIO_SM3_CLKDIV_INT_MSB _u(31) -#define PIO_SM3_CLKDIV_INT_LSB _u(16) -#define PIO_SM3_CLKDIV_INT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM3_CLKDIV_FRAC -// Description : Fractional part of clock divisor -#define PIO_SM3_CLKDIV_FRAC_RESET _u(0x00) -#define PIO_SM3_CLKDIV_FRAC_BITS _u(0x0000ff00) -#define PIO_SM3_CLKDIV_FRAC_MSB _u(15) -#define PIO_SM3_CLKDIV_FRAC_LSB _u(8) -#define PIO_SM3_CLKDIV_FRAC_ACCESS "RW" -// ============================================================================= -// Register : PIO_SM3_EXECCTRL -// Description : Execution/behavioural settings for state machine 3 -#define PIO_SM3_EXECCTRL_OFFSET _u(0x00000114) -#define PIO_SM3_EXECCTRL_BITS _u(0xffffff9f) -#define PIO_SM3_EXECCTRL_RESET _u(0x0001f000) -// ----------------------------------------------------------------------------- -// Field : PIO_SM3_EXECCTRL_EXEC_STALLED -// Description : If 1, an instruction written to SMx_INSTR is stalled, and -// latched by the state machine. Will clear to 0 once this -// instruction completes. -#define PIO_SM3_EXECCTRL_EXEC_STALLED_RESET _u(0x0) -#define PIO_SM3_EXECCTRL_EXEC_STALLED_BITS _u(0x80000000) -#define PIO_SM3_EXECCTRL_EXEC_STALLED_MSB _u(31) -#define PIO_SM3_EXECCTRL_EXEC_STALLED_LSB _u(31) -#define PIO_SM3_EXECCTRL_EXEC_STALLED_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PIO_SM3_EXECCTRL_SIDE_EN -// Description : If 1, the MSB of the Delay/Side-set instruction field is used -// as side-set enable, rather than a side-set data bit. This -// allows instructions to perform side-set optionally, rather than -// on every instruction, but the maximum possible side-set width -// is reduced from 5 to 4. Note that the value of -// PINCTRL_SIDESET_COUNT is inclusive of this enable bit. -#define PIO_SM3_EXECCTRL_SIDE_EN_RESET _u(0x0) -#define PIO_SM3_EXECCTRL_SIDE_EN_BITS _u(0x40000000) -#define PIO_SM3_EXECCTRL_SIDE_EN_MSB _u(30) -#define PIO_SM3_EXECCTRL_SIDE_EN_LSB _u(30) -#define PIO_SM3_EXECCTRL_SIDE_EN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM3_EXECCTRL_SIDE_PINDIR -// Description : If 1, side-set data is asserted to pin directions, instead of -// pin values -#define PIO_SM3_EXECCTRL_SIDE_PINDIR_RESET _u(0x0) -#define PIO_SM3_EXECCTRL_SIDE_PINDIR_BITS _u(0x20000000) -#define PIO_SM3_EXECCTRL_SIDE_PINDIR_MSB _u(29) -#define PIO_SM3_EXECCTRL_SIDE_PINDIR_LSB _u(29) -#define PIO_SM3_EXECCTRL_SIDE_PINDIR_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM3_EXECCTRL_JMP_PIN -// Description : The GPIO number to use as condition for JMP PIN. Unaffected by -// input mapping. -#define PIO_SM3_EXECCTRL_JMP_PIN_RESET _u(0x00) -#define PIO_SM3_EXECCTRL_JMP_PIN_BITS _u(0x1f000000) -#define PIO_SM3_EXECCTRL_JMP_PIN_MSB _u(28) -#define PIO_SM3_EXECCTRL_JMP_PIN_LSB _u(24) -#define PIO_SM3_EXECCTRL_JMP_PIN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM3_EXECCTRL_OUT_EN_SEL -// Description : Which data bit to use for inline OUT enable -#define PIO_SM3_EXECCTRL_OUT_EN_SEL_RESET _u(0x00) -#define PIO_SM3_EXECCTRL_OUT_EN_SEL_BITS _u(0x00f80000) -#define PIO_SM3_EXECCTRL_OUT_EN_SEL_MSB _u(23) -#define PIO_SM3_EXECCTRL_OUT_EN_SEL_LSB _u(19) -#define PIO_SM3_EXECCTRL_OUT_EN_SEL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM3_EXECCTRL_INLINE_OUT_EN -// Description : If 1, use a bit of OUT data as an auxiliary write enable -// When used in conjunction with OUT_STICKY, writes with an enable -// of 0 will -// deassert the latest pin write. This can create useful -// masking/override behaviour -// due to the priority ordering of state machine pin writes (SM0 < -// SM1 < ...) -#define PIO_SM3_EXECCTRL_INLINE_OUT_EN_RESET _u(0x0) -#define PIO_SM3_EXECCTRL_INLINE_OUT_EN_BITS _u(0x00040000) -#define PIO_SM3_EXECCTRL_INLINE_OUT_EN_MSB _u(18) -#define PIO_SM3_EXECCTRL_INLINE_OUT_EN_LSB _u(18) -#define PIO_SM3_EXECCTRL_INLINE_OUT_EN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM3_EXECCTRL_OUT_STICKY -// Description : Continuously assert the most recent OUT/SET to the pins -#define PIO_SM3_EXECCTRL_OUT_STICKY_RESET _u(0x0) -#define PIO_SM3_EXECCTRL_OUT_STICKY_BITS _u(0x00020000) -#define PIO_SM3_EXECCTRL_OUT_STICKY_MSB _u(17) -#define PIO_SM3_EXECCTRL_OUT_STICKY_LSB _u(17) -#define PIO_SM3_EXECCTRL_OUT_STICKY_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM3_EXECCTRL_WRAP_TOP -// Description : After reaching this address, execution is wrapped to -// wrap_bottom. -// If the instruction is a jump, and the jump condition is true, -// the jump takes priority. -#define PIO_SM3_EXECCTRL_WRAP_TOP_RESET _u(0x1f) -#define PIO_SM3_EXECCTRL_WRAP_TOP_BITS _u(0x0001f000) -#define PIO_SM3_EXECCTRL_WRAP_TOP_MSB _u(16) -#define PIO_SM3_EXECCTRL_WRAP_TOP_LSB _u(12) -#define PIO_SM3_EXECCTRL_WRAP_TOP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM3_EXECCTRL_WRAP_BOTTOM -// Description : After reaching wrap_top, execution is wrapped to this address. -#define PIO_SM3_EXECCTRL_WRAP_BOTTOM_RESET _u(0x00) -#define PIO_SM3_EXECCTRL_WRAP_BOTTOM_BITS _u(0x00000f80) -#define PIO_SM3_EXECCTRL_WRAP_BOTTOM_MSB _u(11) -#define PIO_SM3_EXECCTRL_WRAP_BOTTOM_LSB _u(7) -#define PIO_SM3_EXECCTRL_WRAP_BOTTOM_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM3_EXECCTRL_STATUS_SEL -// Description : Comparison used for the MOV x, STATUS instruction. -// 0x0 -> All-ones if TX FIFO level < N, otherwise all-zeroes -// 0x1 -> All-ones if RX FIFO level < N, otherwise all-zeroes -#define PIO_SM3_EXECCTRL_STATUS_SEL_RESET _u(0x0) -#define PIO_SM3_EXECCTRL_STATUS_SEL_BITS _u(0x00000010) -#define PIO_SM3_EXECCTRL_STATUS_SEL_MSB _u(4) -#define PIO_SM3_EXECCTRL_STATUS_SEL_LSB _u(4) -#define PIO_SM3_EXECCTRL_STATUS_SEL_ACCESS "RW" -#define PIO_SM3_EXECCTRL_STATUS_SEL_VALUE_TXLEVEL _u(0x0) -#define PIO_SM3_EXECCTRL_STATUS_SEL_VALUE_RXLEVEL _u(0x1) -// ----------------------------------------------------------------------------- -// Field : PIO_SM3_EXECCTRL_STATUS_N -// Description : Comparison level for the MOV x, STATUS instruction -#define PIO_SM3_EXECCTRL_STATUS_N_RESET _u(0x0) -#define PIO_SM3_EXECCTRL_STATUS_N_BITS _u(0x0000000f) -#define PIO_SM3_EXECCTRL_STATUS_N_MSB _u(3) -#define PIO_SM3_EXECCTRL_STATUS_N_LSB _u(0) -#define PIO_SM3_EXECCTRL_STATUS_N_ACCESS "RW" -// ============================================================================= -// Register : PIO_SM3_SHIFTCTRL -// Description : Control behaviour of the input/output shift registers for state -// machine 3 -#define PIO_SM3_SHIFTCTRL_OFFSET _u(0x00000118) -#define PIO_SM3_SHIFTCTRL_BITS _u(0xffff0000) -#define PIO_SM3_SHIFTCTRL_RESET _u(0x000c0000) -// ----------------------------------------------------------------------------- -// Field : PIO_SM3_SHIFTCTRL_FJOIN_RX -// Description : When 1, RX FIFO steals the TX FIFO's storage, and becomes twice -// as deep. -// TX FIFO is disabled as a result (always reads as both full and -// empty). -// FIFOs are flushed when this bit is changed. -#define PIO_SM3_SHIFTCTRL_FJOIN_RX_RESET _u(0x0) -#define PIO_SM3_SHIFTCTRL_FJOIN_RX_BITS _u(0x80000000) -#define PIO_SM3_SHIFTCTRL_FJOIN_RX_MSB _u(31) -#define PIO_SM3_SHIFTCTRL_FJOIN_RX_LSB _u(31) -#define PIO_SM3_SHIFTCTRL_FJOIN_RX_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM3_SHIFTCTRL_FJOIN_TX -// Description : When 1, TX FIFO steals the RX FIFO's storage, and becomes twice -// as deep. -// RX FIFO is disabled as a result (always reads as both full and -// empty). -// FIFOs are flushed when this bit is changed. -#define PIO_SM3_SHIFTCTRL_FJOIN_TX_RESET _u(0x0) -#define PIO_SM3_SHIFTCTRL_FJOIN_TX_BITS _u(0x40000000) -#define PIO_SM3_SHIFTCTRL_FJOIN_TX_MSB _u(30) -#define PIO_SM3_SHIFTCTRL_FJOIN_TX_LSB _u(30) -#define PIO_SM3_SHIFTCTRL_FJOIN_TX_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM3_SHIFTCTRL_PULL_THRESH -// Description : Number of bits shifted out of OSR before autopull, or -// conditional pull (PULL IFEMPTY), will take place. -// Write 0 for value of 32. -#define PIO_SM3_SHIFTCTRL_PULL_THRESH_RESET _u(0x00) -#define PIO_SM3_SHIFTCTRL_PULL_THRESH_BITS _u(0x3e000000) -#define PIO_SM3_SHIFTCTRL_PULL_THRESH_MSB _u(29) -#define PIO_SM3_SHIFTCTRL_PULL_THRESH_LSB _u(25) -#define PIO_SM3_SHIFTCTRL_PULL_THRESH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM3_SHIFTCTRL_PUSH_THRESH -// Description : Number of bits shifted into ISR before autopush, or conditional -// push (PUSH IFFULL), will take place. -// Write 0 for value of 32. -#define PIO_SM3_SHIFTCTRL_PUSH_THRESH_RESET _u(0x00) -#define PIO_SM3_SHIFTCTRL_PUSH_THRESH_BITS _u(0x01f00000) -#define PIO_SM3_SHIFTCTRL_PUSH_THRESH_MSB _u(24) -#define PIO_SM3_SHIFTCTRL_PUSH_THRESH_LSB _u(20) -#define PIO_SM3_SHIFTCTRL_PUSH_THRESH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM3_SHIFTCTRL_OUT_SHIFTDIR -// Description : 1 = shift out of output shift register to right. 0 = to left. -#define PIO_SM3_SHIFTCTRL_OUT_SHIFTDIR_RESET _u(0x1) -#define PIO_SM3_SHIFTCTRL_OUT_SHIFTDIR_BITS _u(0x00080000) -#define PIO_SM3_SHIFTCTRL_OUT_SHIFTDIR_MSB _u(19) -#define PIO_SM3_SHIFTCTRL_OUT_SHIFTDIR_LSB _u(19) -#define PIO_SM3_SHIFTCTRL_OUT_SHIFTDIR_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM3_SHIFTCTRL_IN_SHIFTDIR -// Description : 1 = shift input shift register to right (data enters from -// left). 0 = to left. -#define PIO_SM3_SHIFTCTRL_IN_SHIFTDIR_RESET _u(0x1) -#define PIO_SM3_SHIFTCTRL_IN_SHIFTDIR_BITS _u(0x00040000) -#define PIO_SM3_SHIFTCTRL_IN_SHIFTDIR_MSB _u(18) -#define PIO_SM3_SHIFTCTRL_IN_SHIFTDIR_LSB _u(18) -#define PIO_SM3_SHIFTCTRL_IN_SHIFTDIR_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM3_SHIFTCTRL_AUTOPULL -// Description : Pull automatically when the output shift register is emptied, -// i.e. on or following an OUT instruction which causes the output -// shift counter to reach or exceed PULL_THRESH. -#define PIO_SM3_SHIFTCTRL_AUTOPULL_RESET _u(0x0) -#define PIO_SM3_SHIFTCTRL_AUTOPULL_BITS _u(0x00020000) -#define PIO_SM3_SHIFTCTRL_AUTOPULL_MSB _u(17) -#define PIO_SM3_SHIFTCTRL_AUTOPULL_LSB _u(17) -#define PIO_SM3_SHIFTCTRL_AUTOPULL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM3_SHIFTCTRL_AUTOPUSH -// Description : Push automatically when the input shift register is filled, -// i.e. on an IN instruction which causes the input shift counter -// to reach or exceed PUSH_THRESH. -#define PIO_SM3_SHIFTCTRL_AUTOPUSH_RESET _u(0x0) -#define PIO_SM3_SHIFTCTRL_AUTOPUSH_BITS _u(0x00010000) -#define PIO_SM3_SHIFTCTRL_AUTOPUSH_MSB _u(16) -#define PIO_SM3_SHIFTCTRL_AUTOPUSH_LSB _u(16) -#define PIO_SM3_SHIFTCTRL_AUTOPUSH_ACCESS "RW" -// ============================================================================= -// Register : PIO_SM3_ADDR -// Description : Current instruction address of state machine 3 -#define PIO_SM3_ADDR_OFFSET _u(0x0000011c) -#define PIO_SM3_ADDR_BITS _u(0x0000001f) -#define PIO_SM3_ADDR_RESET _u(0x00000000) -#define PIO_SM3_ADDR_MSB _u(4) -#define PIO_SM3_ADDR_LSB _u(0) -#define PIO_SM3_ADDR_ACCESS "RO" -// ============================================================================= -// Register : PIO_SM3_INSTR -// Description : Read to see the instruction currently addressed by state -// machine 3's program counter -// Write to execute an instruction immediately (including jumps) -// and then resume execution. -#define PIO_SM3_INSTR_OFFSET _u(0x00000120) -#define PIO_SM3_INSTR_BITS _u(0x0000ffff) -#define PIO_SM3_INSTR_RESET "-" -#define PIO_SM3_INSTR_MSB _u(15) -#define PIO_SM3_INSTR_LSB _u(0) -#define PIO_SM3_INSTR_ACCESS "RW" -// ============================================================================= -// Register : PIO_SM3_PINCTRL -// Description : State machine pin control -#define PIO_SM3_PINCTRL_OFFSET _u(0x00000124) -#define PIO_SM3_PINCTRL_BITS _u(0xffffffff) -#define PIO_SM3_PINCTRL_RESET _u(0x14000000) -// ----------------------------------------------------------------------------- -// Field : PIO_SM3_PINCTRL_SIDESET_COUNT -// Description : The number of MSBs of the Delay/Side-set instruction field -// which are used for side-set. Inclusive of the enable bit, if -// present. Minimum of 0 (all delay bits, no side-set) and maximum -// of 5 (all side-set, no delay). -#define PIO_SM3_PINCTRL_SIDESET_COUNT_RESET _u(0x0) -#define PIO_SM3_PINCTRL_SIDESET_COUNT_BITS _u(0xe0000000) -#define PIO_SM3_PINCTRL_SIDESET_COUNT_MSB _u(31) -#define PIO_SM3_PINCTRL_SIDESET_COUNT_LSB _u(29) -#define PIO_SM3_PINCTRL_SIDESET_COUNT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM3_PINCTRL_SET_COUNT -// Description : The number of pins asserted by a SET. In the range 0 to 5 -// inclusive. -#define PIO_SM3_PINCTRL_SET_COUNT_RESET _u(0x5) -#define PIO_SM3_PINCTRL_SET_COUNT_BITS _u(0x1c000000) -#define PIO_SM3_PINCTRL_SET_COUNT_MSB _u(28) -#define PIO_SM3_PINCTRL_SET_COUNT_LSB _u(26) -#define PIO_SM3_PINCTRL_SET_COUNT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM3_PINCTRL_OUT_COUNT -// Description : The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV -// PINS instruction. In the range 0 to 32 inclusive. -#define PIO_SM3_PINCTRL_OUT_COUNT_RESET _u(0x00) -#define PIO_SM3_PINCTRL_OUT_COUNT_BITS _u(0x03f00000) -#define PIO_SM3_PINCTRL_OUT_COUNT_MSB _u(25) -#define PIO_SM3_PINCTRL_OUT_COUNT_LSB _u(20) -#define PIO_SM3_PINCTRL_OUT_COUNT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM3_PINCTRL_IN_BASE -// Description : The pin which is mapped to the least-significant bit of a state -// machine's IN data bus. Higher-numbered pins are mapped to -// consecutively more-significant data bits, with a modulo of 32 -// applied to pin number. -#define PIO_SM3_PINCTRL_IN_BASE_RESET _u(0x00) -#define PIO_SM3_PINCTRL_IN_BASE_BITS _u(0x000f8000) -#define PIO_SM3_PINCTRL_IN_BASE_MSB _u(19) -#define PIO_SM3_PINCTRL_IN_BASE_LSB _u(15) -#define PIO_SM3_PINCTRL_IN_BASE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM3_PINCTRL_SIDESET_BASE -// Description : The lowest-numbered pin that will be affected by a side-set -// operation. The MSBs of an instruction's side-set/delay field -// (up to 5, determined by SIDESET_COUNT) are used for side-set -// data, with the remaining LSBs used for delay. The least- -// significant bit of the side-set portion is the bit written to -// this pin, with more-significant bits written to higher-numbered -// pins. -#define PIO_SM3_PINCTRL_SIDESET_BASE_RESET _u(0x00) -#define PIO_SM3_PINCTRL_SIDESET_BASE_BITS _u(0x00007c00) -#define PIO_SM3_PINCTRL_SIDESET_BASE_MSB _u(14) -#define PIO_SM3_PINCTRL_SIDESET_BASE_LSB _u(10) -#define PIO_SM3_PINCTRL_SIDESET_BASE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM3_PINCTRL_SET_BASE -// Description : The lowest-numbered pin that will be affected by a SET PINS or -// SET PINDIRS instruction. The data written to this pin is the -// least-significant bit of the SET data. -#define PIO_SM3_PINCTRL_SET_BASE_RESET _u(0x00) -#define PIO_SM3_PINCTRL_SET_BASE_BITS _u(0x000003e0) -#define PIO_SM3_PINCTRL_SET_BASE_MSB _u(9) -#define PIO_SM3_PINCTRL_SET_BASE_LSB _u(5) -#define PIO_SM3_PINCTRL_SET_BASE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM3_PINCTRL_OUT_BASE -// Description : The lowest-numbered pin that will be affected by an OUT PINS, -// OUT PINDIRS or MOV PINS instruction. The data written to this -// pin will always be the least-significant bit of the OUT or MOV -// data. -#define PIO_SM3_PINCTRL_OUT_BASE_RESET _u(0x00) -#define PIO_SM3_PINCTRL_OUT_BASE_BITS _u(0x0000001f) -#define PIO_SM3_PINCTRL_OUT_BASE_MSB _u(4) -#define PIO_SM3_PINCTRL_OUT_BASE_LSB _u(0) -#define PIO_SM3_PINCTRL_OUT_BASE_ACCESS "RW" -// ============================================================================= -// Register : PIO_INTR -// Description : Raw Interrupts -#define PIO_INTR_OFFSET _u(0x00000128) -#define PIO_INTR_BITS _u(0x00000fff) -#define PIO_INTR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : PIO_INTR_SM3 -#define PIO_INTR_SM3_RESET _u(0x0) -#define PIO_INTR_SM3_BITS _u(0x00000800) -#define PIO_INTR_SM3_MSB _u(11) -#define PIO_INTR_SM3_LSB _u(11) -#define PIO_INTR_SM3_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PIO_INTR_SM2 -#define PIO_INTR_SM2_RESET _u(0x0) -#define PIO_INTR_SM2_BITS _u(0x00000400) -#define PIO_INTR_SM2_MSB _u(10) -#define PIO_INTR_SM2_LSB _u(10) -#define PIO_INTR_SM2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PIO_INTR_SM1 -#define PIO_INTR_SM1_RESET _u(0x0) -#define PIO_INTR_SM1_BITS _u(0x00000200) -#define PIO_INTR_SM1_MSB _u(9) -#define PIO_INTR_SM1_LSB _u(9) -#define PIO_INTR_SM1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PIO_INTR_SM0 -#define PIO_INTR_SM0_RESET _u(0x0) -#define PIO_INTR_SM0_BITS _u(0x00000100) -#define PIO_INTR_SM0_MSB _u(8) -#define PIO_INTR_SM0_LSB _u(8) -#define PIO_INTR_SM0_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PIO_INTR_SM3_TXNFULL -#define PIO_INTR_SM3_TXNFULL_RESET _u(0x0) -#define PIO_INTR_SM3_TXNFULL_BITS _u(0x00000080) -#define PIO_INTR_SM3_TXNFULL_MSB _u(7) -#define PIO_INTR_SM3_TXNFULL_LSB _u(7) -#define PIO_INTR_SM3_TXNFULL_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PIO_INTR_SM2_TXNFULL -#define PIO_INTR_SM2_TXNFULL_RESET _u(0x0) -#define PIO_INTR_SM2_TXNFULL_BITS _u(0x00000040) -#define PIO_INTR_SM2_TXNFULL_MSB _u(6) -#define PIO_INTR_SM2_TXNFULL_LSB _u(6) -#define PIO_INTR_SM2_TXNFULL_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PIO_INTR_SM1_TXNFULL -#define PIO_INTR_SM1_TXNFULL_RESET _u(0x0) -#define PIO_INTR_SM1_TXNFULL_BITS _u(0x00000020) -#define PIO_INTR_SM1_TXNFULL_MSB _u(5) -#define PIO_INTR_SM1_TXNFULL_LSB _u(5) -#define PIO_INTR_SM1_TXNFULL_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PIO_INTR_SM0_TXNFULL -#define PIO_INTR_SM0_TXNFULL_RESET _u(0x0) -#define PIO_INTR_SM0_TXNFULL_BITS _u(0x00000010) -#define PIO_INTR_SM0_TXNFULL_MSB _u(4) -#define PIO_INTR_SM0_TXNFULL_LSB _u(4) -#define PIO_INTR_SM0_TXNFULL_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PIO_INTR_SM3_RXNEMPTY -#define PIO_INTR_SM3_RXNEMPTY_RESET _u(0x0) -#define PIO_INTR_SM3_RXNEMPTY_BITS _u(0x00000008) -#define PIO_INTR_SM3_RXNEMPTY_MSB _u(3) -#define PIO_INTR_SM3_RXNEMPTY_LSB _u(3) -#define PIO_INTR_SM3_RXNEMPTY_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PIO_INTR_SM2_RXNEMPTY -#define PIO_INTR_SM2_RXNEMPTY_RESET _u(0x0) -#define PIO_INTR_SM2_RXNEMPTY_BITS _u(0x00000004) -#define PIO_INTR_SM2_RXNEMPTY_MSB _u(2) -#define PIO_INTR_SM2_RXNEMPTY_LSB _u(2) -#define PIO_INTR_SM2_RXNEMPTY_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PIO_INTR_SM1_RXNEMPTY -#define PIO_INTR_SM1_RXNEMPTY_RESET _u(0x0) -#define PIO_INTR_SM1_RXNEMPTY_BITS _u(0x00000002) -#define PIO_INTR_SM1_RXNEMPTY_MSB _u(1) -#define PIO_INTR_SM1_RXNEMPTY_LSB _u(1) -#define PIO_INTR_SM1_RXNEMPTY_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PIO_INTR_SM0_RXNEMPTY -#define PIO_INTR_SM0_RXNEMPTY_RESET _u(0x0) -#define PIO_INTR_SM0_RXNEMPTY_BITS _u(0x00000001) -#define PIO_INTR_SM0_RXNEMPTY_MSB _u(0) -#define PIO_INTR_SM0_RXNEMPTY_LSB _u(0) -#define PIO_INTR_SM0_RXNEMPTY_ACCESS "RO" -// ============================================================================= -// Register : PIO_IRQ0_INTE -// Description : Interrupt Enable for irq0 -#define PIO_IRQ0_INTE_OFFSET _u(0x0000012c) -#define PIO_IRQ0_INTE_BITS _u(0x00000fff) -#define PIO_IRQ0_INTE_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ0_INTE_SM3 -#define PIO_IRQ0_INTE_SM3_RESET _u(0x0) -#define PIO_IRQ0_INTE_SM3_BITS _u(0x00000800) -#define PIO_IRQ0_INTE_SM3_MSB _u(11) -#define PIO_IRQ0_INTE_SM3_LSB _u(11) -#define PIO_IRQ0_INTE_SM3_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ0_INTE_SM2 -#define PIO_IRQ0_INTE_SM2_RESET _u(0x0) -#define PIO_IRQ0_INTE_SM2_BITS _u(0x00000400) -#define PIO_IRQ0_INTE_SM2_MSB _u(10) -#define PIO_IRQ0_INTE_SM2_LSB _u(10) -#define PIO_IRQ0_INTE_SM2_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ0_INTE_SM1 -#define PIO_IRQ0_INTE_SM1_RESET _u(0x0) -#define PIO_IRQ0_INTE_SM1_BITS _u(0x00000200) -#define PIO_IRQ0_INTE_SM1_MSB _u(9) -#define PIO_IRQ0_INTE_SM1_LSB _u(9) -#define PIO_IRQ0_INTE_SM1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ0_INTE_SM0 -#define PIO_IRQ0_INTE_SM0_RESET _u(0x0) -#define PIO_IRQ0_INTE_SM0_BITS _u(0x00000100) -#define PIO_IRQ0_INTE_SM0_MSB _u(8) -#define PIO_IRQ0_INTE_SM0_LSB _u(8) -#define PIO_IRQ0_INTE_SM0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ0_INTE_SM3_TXNFULL -#define PIO_IRQ0_INTE_SM3_TXNFULL_RESET _u(0x0) -#define PIO_IRQ0_INTE_SM3_TXNFULL_BITS _u(0x00000080) -#define PIO_IRQ0_INTE_SM3_TXNFULL_MSB _u(7) -#define PIO_IRQ0_INTE_SM3_TXNFULL_LSB _u(7) -#define PIO_IRQ0_INTE_SM3_TXNFULL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ0_INTE_SM2_TXNFULL -#define PIO_IRQ0_INTE_SM2_TXNFULL_RESET _u(0x0) -#define PIO_IRQ0_INTE_SM2_TXNFULL_BITS _u(0x00000040) -#define PIO_IRQ0_INTE_SM2_TXNFULL_MSB _u(6) -#define PIO_IRQ0_INTE_SM2_TXNFULL_LSB _u(6) -#define PIO_IRQ0_INTE_SM2_TXNFULL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ0_INTE_SM1_TXNFULL -#define PIO_IRQ0_INTE_SM1_TXNFULL_RESET _u(0x0) -#define PIO_IRQ0_INTE_SM1_TXNFULL_BITS _u(0x00000020) -#define PIO_IRQ0_INTE_SM1_TXNFULL_MSB _u(5) -#define PIO_IRQ0_INTE_SM1_TXNFULL_LSB _u(5) -#define PIO_IRQ0_INTE_SM1_TXNFULL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ0_INTE_SM0_TXNFULL -#define PIO_IRQ0_INTE_SM0_TXNFULL_RESET _u(0x0) -#define PIO_IRQ0_INTE_SM0_TXNFULL_BITS _u(0x00000010) -#define PIO_IRQ0_INTE_SM0_TXNFULL_MSB _u(4) -#define PIO_IRQ0_INTE_SM0_TXNFULL_LSB _u(4) -#define PIO_IRQ0_INTE_SM0_TXNFULL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ0_INTE_SM3_RXNEMPTY -#define PIO_IRQ0_INTE_SM3_RXNEMPTY_RESET _u(0x0) -#define PIO_IRQ0_INTE_SM3_RXNEMPTY_BITS _u(0x00000008) -#define PIO_IRQ0_INTE_SM3_RXNEMPTY_MSB _u(3) -#define PIO_IRQ0_INTE_SM3_RXNEMPTY_LSB _u(3) -#define PIO_IRQ0_INTE_SM3_RXNEMPTY_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ0_INTE_SM2_RXNEMPTY -#define PIO_IRQ0_INTE_SM2_RXNEMPTY_RESET _u(0x0) -#define PIO_IRQ0_INTE_SM2_RXNEMPTY_BITS _u(0x00000004) -#define PIO_IRQ0_INTE_SM2_RXNEMPTY_MSB _u(2) -#define PIO_IRQ0_INTE_SM2_RXNEMPTY_LSB _u(2) -#define PIO_IRQ0_INTE_SM2_RXNEMPTY_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ0_INTE_SM1_RXNEMPTY -#define PIO_IRQ0_INTE_SM1_RXNEMPTY_RESET _u(0x0) -#define PIO_IRQ0_INTE_SM1_RXNEMPTY_BITS _u(0x00000002) -#define PIO_IRQ0_INTE_SM1_RXNEMPTY_MSB _u(1) -#define PIO_IRQ0_INTE_SM1_RXNEMPTY_LSB _u(1) -#define PIO_IRQ0_INTE_SM1_RXNEMPTY_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ0_INTE_SM0_RXNEMPTY -#define PIO_IRQ0_INTE_SM0_RXNEMPTY_RESET _u(0x0) -#define PIO_IRQ0_INTE_SM0_RXNEMPTY_BITS _u(0x00000001) -#define PIO_IRQ0_INTE_SM0_RXNEMPTY_MSB _u(0) -#define PIO_IRQ0_INTE_SM0_RXNEMPTY_LSB _u(0) -#define PIO_IRQ0_INTE_SM0_RXNEMPTY_ACCESS "RW" -// ============================================================================= -// Register : PIO_IRQ0_INTF -// Description : Interrupt Force for irq0 -#define PIO_IRQ0_INTF_OFFSET _u(0x00000130) -#define PIO_IRQ0_INTF_BITS _u(0x00000fff) -#define PIO_IRQ0_INTF_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ0_INTF_SM3 -#define PIO_IRQ0_INTF_SM3_RESET _u(0x0) -#define PIO_IRQ0_INTF_SM3_BITS _u(0x00000800) -#define PIO_IRQ0_INTF_SM3_MSB _u(11) -#define PIO_IRQ0_INTF_SM3_LSB _u(11) -#define PIO_IRQ0_INTF_SM3_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ0_INTF_SM2 -#define PIO_IRQ0_INTF_SM2_RESET _u(0x0) -#define PIO_IRQ0_INTF_SM2_BITS _u(0x00000400) -#define PIO_IRQ0_INTF_SM2_MSB _u(10) -#define PIO_IRQ0_INTF_SM2_LSB _u(10) -#define PIO_IRQ0_INTF_SM2_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ0_INTF_SM1 -#define PIO_IRQ0_INTF_SM1_RESET _u(0x0) -#define PIO_IRQ0_INTF_SM1_BITS _u(0x00000200) -#define PIO_IRQ0_INTF_SM1_MSB _u(9) -#define PIO_IRQ0_INTF_SM1_LSB _u(9) -#define PIO_IRQ0_INTF_SM1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ0_INTF_SM0 -#define PIO_IRQ0_INTF_SM0_RESET _u(0x0) -#define PIO_IRQ0_INTF_SM0_BITS _u(0x00000100) -#define PIO_IRQ0_INTF_SM0_MSB _u(8) -#define PIO_IRQ0_INTF_SM0_LSB _u(8) -#define PIO_IRQ0_INTF_SM0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ0_INTF_SM3_TXNFULL -#define PIO_IRQ0_INTF_SM3_TXNFULL_RESET _u(0x0) -#define PIO_IRQ0_INTF_SM3_TXNFULL_BITS _u(0x00000080) -#define PIO_IRQ0_INTF_SM3_TXNFULL_MSB _u(7) -#define PIO_IRQ0_INTF_SM3_TXNFULL_LSB _u(7) -#define PIO_IRQ0_INTF_SM3_TXNFULL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ0_INTF_SM2_TXNFULL -#define PIO_IRQ0_INTF_SM2_TXNFULL_RESET _u(0x0) -#define PIO_IRQ0_INTF_SM2_TXNFULL_BITS _u(0x00000040) -#define PIO_IRQ0_INTF_SM2_TXNFULL_MSB _u(6) -#define PIO_IRQ0_INTF_SM2_TXNFULL_LSB _u(6) -#define PIO_IRQ0_INTF_SM2_TXNFULL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ0_INTF_SM1_TXNFULL -#define PIO_IRQ0_INTF_SM1_TXNFULL_RESET _u(0x0) -#define PIO_IRQ0_INTF_SM1_TXNFULL_BITS _u(0x00000020) -#define PIO_IRQ0_INTF_SM1_TXNFULL_MSB _u(5) -#define PIO_IRQ0_INTF_SM1_TXNFULL_LSB _u(5) -#define PIO_IRQ0_INTF_SM1_TXNFULL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ0_INTF_SM0_TXNFULL -#define PIO_IRQ0_INTF_SM0_TXNFULL_RESET _u(0x0) -#define PIO_IRQ0_INTF_SM0_TXNFULL_BITS _u(0x00000010) -#define PIO_IRQ0_INTF_SM0_TXNFULL_MSB _u(4) -#define PIO_IRQ0_INTF_SM0_TXNFULL_LSB _u(4) -#define PIO_IRQ0_INTF_SM0_TXNFULL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ0_INTF_SM3_RXNEMPTY -#define PIO_IRQ0_INTF_SM3_RXNEMPTY_RESET _u(0x0) -#define PIO_IRQ0_INTF_SM3_RXNEMPTY_BITS _u(0x00000008) -#define PIO_IRQ0_INTF_SM3_RXNEMPTY_MSB _u(3) -#define PIO_IRQ0_INTF_SM3_RXNEMPTY_LSB _u(3) -#define PIO_IRQ0_INTF_SM3_RXNEMPTY_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ0_INTF_SM2_RXNEMPTY -#define PIO_IRQ0_INTF_SM2_RXNEMPTY_RESET _u(0x0) -#define PIO_IRQ0_INTF_SM2_RXNEMPTY_BITS _u(0x00000004) -#define PIO_IRQ0_INTF_SM2_RXNEMPTY_MSB _u(2) -#define PIO_IRQ0_INTF_SM2_RXNEMPTY_LSB _u(2) -#define PIO_IRQ0_INTF_SM2_RXNEMPTY_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ0_INTF_SM1_RXNEMPTY -#define PIO_IRQ0_INTF_SM1_RXNEMPTY_RESET _u(0x0) -#define PIO_IRQ0_INTF_SM1_RXNEMPTY_BITS _u(0x00000002) -#define PIO_IRQ0_INTF_SM1_RXNEMPTY_MSB _u(1) -#define PIO_IRQ0_INTF_SM1_RXNEMPTY_LSB _u(1) -#define PIO_IRQ0_INTF_SM1_RXNEMPTY_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ0_INTF_SM0_RXNEMPTY -#define PIO_IRQ0_INTF_SM0_RXNEMPTY_RESET _u(0x0) -#define PIO_IRQ0_INTF_SM0_RXNEMPTY_BITS _u(0x00000001) -#define PIO_IRQ0_INTF_SM0_RXNEMPTY_MSB _u(0) -#define PIO_IRQ0_INTF_SM0_RXNEMPTY_LSB _u(0) -#define PIO_IRQ0_INTF_SM0_RXNEMPTY_ACCESS "RW" -// ============================================================================= -// Register : PIO_IRQ0_INTS -// Description : Interrupt status after masking & forcing for irq0 -#define PIO_IRQ0_INTS_OFFSET _u(0x00000134) -#define PIO_IRQ0_INTS_BITS _u(0x00000fff) -#define PIO_IRQ0_INTS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ0_INTS_SM3 -#define PIO_IRQ0_INTS_SM3_RESET _u(0x0) -#define PIO_IRQ0_INTS_SM3_BITS _u(0x00000800) -#define PIO_IRQ0_INTS_SM3_MSB _u(11) -#define PIO_IRQ0_INTS_SM3_LSB _u(11) -#define PIO_IRQ0_INTS_SM3_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ0_INTS_SM2 -#define PIO_IRQ0_INTS_SM2_RESET _u(0x0) -#define PIO_IRQ0_INTS_SM2_BITS _u(0x00000400) -#define PIO_IRQ0_INTS_SM2_MSB _u(10) -#define PIO_IRQ0_INTS_SM2_LSB _u(10) -#define PIO_IRQ0_INTS_SM2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ0_INTS_SM1 -#define PIO_IRQ0_INTS_SM1_RESET _u(0x0) -#define PIO_IRQ0_INTS_SM1_BITS _u(0x00000200) -#define PIO_IRQ0_INTS_SM1_MSB _u(9) -#define PIO_IRQ0_INTS_SM1_LSB _u(9) -#define PIO_IRQ0_INTS_SM1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ0_INTS_SM0 -#define PIO_IRQ0_INTS_SM0_RESET _u(0x0) -#define PIO_IRQ0_INTS_SM0_BITS _u(0x00000100) -#define PIO_IRQ0_INTS_SM0_MSB _u(8) -#define PIO_IRQ0_INTS_SM0_LSB _u(8) -#define PIO_IRQ0_INTS_SM0_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ0_INTS_SM3_TXNFULL -#define PIO_IRQ0_INTS_SM3_TXNFULL_RESET _u(0x0) -#define PIO_IRQ0_INTS_SM3_TXNFULL_BITS _u(0x00000080) -#define PIO_IRQ0_INTS_SM3_TXNFULL_MSB _u(7) -#define PIO_IRQ0_INTS_SM3_TXNFULL_LSB _u(7) -#define PIO_IRQ0_INTS_SM3_TXNFULL_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ0_INTS_SM2_TXNFULL -#define PIO_IRQ0_INTS_SM2_TXNFULL_RESET _u(0x0) -#define PIO_IRQ0_INTS_SM2_TXNFULL_BITS _u(0x00000040) -#define PIO_IRQ0_INTS_SM2_TXNFULL_MSB _u(6) -#define PIO_IRQ0_INTS_SM2_TXNFULL_LSB _u(6) -#define PIO_IRQ0_INTS_SM2_TXNFULL_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ0_INTS_SM1_TXNFULL -#define PIO_IRQ0_INTS_SM1_TXNFULL_RESET _u(0x0) -#define PIO_IRQ0_INTS_SM1_TXNFULL_BITS _u(0x00000020) -#define PIO_IRQ0_INTS_SM1_TXNFULL_MSB _u(5) -#define PIO_IRQ0_INTS_SM1_TXNFULL_LSB _u(5) -#define PIO_IRQ0_INTS_SM1_TXNFULL_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ0_INTS_SM0_TXNFULL -#define PIO_IRQ0_INTS_SM0_TXNFULL_RESET _u(0x0) -#define PIO_IRQ0_INTS_SM0_TXNFULL_BITS _u(0x00000010) -#define PIO_IRQ0_INTS_SM0_TXNFULL_MSB _u(4) -#define PIO_IRQ0_INTS_SM0_TXNFULL_LSB _u(4) -#define PIO_IRQ0_INTS_SM0_TXNFULL_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ0_INTS_SM3_RXNEMPTY -#define PIO_IRQ0_INTS_SM3_RXNEMPTY_RESET _u(0x0) -#define PIO_IRQ0_INTS_SM3_RXNEMPTY_BITS _u(0x00000008) -#define PIO_IRQ0_INTS_SM3_RXNEMPTY_MSB _u(3) -#define PIO_IRQ0_INTS_SM3_RXNEMPTY_LSB _u(3) -#define PIO_IRQ0_INTS_SM3_RXNEMPTY_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ0_INTS_SM2_RXNEMPTY -#define PIO_IRQ0_INTS_SM2_RXNEMPTY_RESET _u(0x0) -#define PIO_IRQ0_INTS_SM2_RXNEMPTY_BITS _u(0x00000004) -#define PIO_IRQ0_INTS_SM2_RXNEMPTY_MSB _u(2) -#define PIO_IRQ0_INTS_SM2_RXNEMPTY_LSB _u(2) -#define PIO_IRQ0_INTS_SM2_RXNEMPTY_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ0_INTS_SM1_RXNEMPTY -#define PIO_IRQ0_INTS_SM1_RXNEMPTY_RESET _u(0x0) -#define PIO_IRQ0_INTS_SM1_RXNEMPTY_BITS _u(0x00000002) -#define PIO_IRQ0_INTS_SM1_RXNEMPTY_MSB _u(1) -#define PIO_IRQ0_INTS_SM1_RXNEMPTY_LSB _u(1) -#define PIO_IRQ0_INTS_SM1_RXNEMPTY_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ0_INTS_SM0_RXNEMPTY -#define PIO_IRQ0_INTS_SM0_RXNEMPTY_RESET _u(0x0) -#define PIO_IRQ0_INTS_SM0_RXNEMPTY_BITS _u(0x00000001) -#define PIO_IRQ0_INTS_SM0_RXNEMPTY_MSB _u(0) -#define PIO_IRQ0_INTS_SM0_RXNEMPTY_LSB _u(0) -#define PIO_IRQ0_INTS_SM0_RXNEMPTY_ACCESS "RO" -// ============================================================================= -// Register : PIO_IRQ1_INTE -// Description : Interrupt Enable for irq1 -#define PIO_IRQ1_INTE_OFFSET _u(0x00000138) -#define PIO_IRQ1_INTE_BITS _u(0x00000fff) -#define PIO_IRQ1_INTE_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ1_INTE_SM3 -#define PIO_IRQ1_INTE_SM3_RESET _u(0x0) -#define PIO_IRQ1_INTE_SM3_BITS _u(0x00000800) -#define PIO_IRQ1_INTE_SM3_MSB _u(11) -#define PIO_IRQ1_INTE_SM3_LSB _u(11) -#define PIO_IRQ1_INTE_SM3_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ1_INTE_SM2 -#define PIO_IRQ1_INTE_SM2_RESET _u(0x0) -#define PIO_IRQ1_INTE_SM2_BITS _u(0x00000400) -#define PIO_IRQ1_INTE_SM2_MSB _u(10) -#define PIO_IRQ1_INTE_SM2_LSB _u(10) -#define PIO_IRQ1_INTE_SM2_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ1_INTE_SM1 -#define PIO_IRQ1_INTE_SM1_RESET _u(0x0) -#define PIO_IRQ1_INTE_SM1_BITS _u(0x00000200) -#define PIO_IRQ1_INTE_SM1_MSB _u(9) -#define PIO_IRQ1_INTE_SM1_LSB _u(9) -#define PIO_IRQ1_INTE_SM1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ1_INTE_SM0 -#define PIO_IRQ1_INTE_SM0_RESET _u(0x0) -#define PIO_IRQ1_INTE_SM0_BITS _u(0x00000100) -#define PIO_IRQ1_INTE_SM0_MSB _u(8) -#define PIO_IRQ1_INTE_SM0_LSB _u(8) -#define PIO_IRQ1_INTE_SM0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ1_INTE_SM3_TXNFULL -#define PIO_IRQ1_INTE_SM3_TXNFULL_RESET _u(0x0) -#define PIO_IRQ1_INTE_SM3_TXNFULL_BITS _u(0x00000080) -#define PIO_IRQ1_INTE_SM3_TXNFULL_MSB _u(7) -#define PIO_IRQ1_INTE_SM3_TXNFULL_LSB _u(7) -#define PIO_IRQ1_INTE_SM3_TXNFULL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ1_INTE_SM2_TXNFULL -#define PIO_IRQ1_INTE_SM2_TXNFULL_RESET _u(0x0) -#define PIO_IRQ1_INTE_SM2_TXNFULL_BITS _u(0x00000040) -#define PIO_IRQ1_INTE_SM2_TXNFULL_MSB _u(6) -#define PIO_IRQ1_INTE_SM2_TXNFULL_LSB _u(6) -#define PIO_IRQ1_INTE_SM2_TXNFULL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ1_INTE_SM1_TXNFULL -#define PIO_IRQ1_INTE_SM1_TXNFULL_RESET _u(0x0) -#define PIO_IRQ1_INTE_SM1_TXNFULL_BITS _u(0x00000020) -#define PIO_IRQ1_INTE_SM1_TXNFULL_MSB _u(5) -#define PIO_IRQ1_INTE_SM1_TXNFULL_LSB _u(5) -#define PIO_IRQ1_INTE_SM1_TXNFULL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ1_INTE_SM0_TXNFULL -#define PIO_IRQ1_INTE_SM0_TXNFULL_RESET _u(0x0) -#define PIO_IRQ1_INTE_SM0_TXNFULL_BITS _u(0x00000010) -#define PIO_IRQ1_INTE_SM0_TXNFULL_MSB _u(4) -#define PIO_IRQ1_INTE_SM0_TXNFULL_LSB _u(4) -#define PIO_IRQ1_INTE_SM0_TXNFULL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ1_INTE_SM3_RXNEMPTY -#define PIO_IRQ1_INTE_SM3_RXNEMPTY_RESET _u(0x0) -#define PIO_IRQ1_INTE_SM3_RXNEMPTY_BITS _u(0x00000008) -#define PIO_IRQ1_INTE_SM3_RXNEMPTY_MSB _u(3) -#define PIO_IRQ1_INTE_SM3_RXNEMPTY_LSB _u(3) -#define PIO_IRQ1_INTE_SM3_RXNEMPTY_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ1_INTE_SM2_RXNEMPTY -#define PIO_IRQ1_INTE_SM2_RXNEMPTY_RESET _u(0x0) -#define PIO_IRQ1_INTE_SM2_RXNEMPTY_BITS _u(0x00000004) -#define PIO_IRQ1_INTE_SM2_RXNEMPTY_MSB _u(2) -#define PIO_IRQ1_INTE_SM2_RXNEMPTY_LSB _u(2) -#define PIO_IRQ1_INTE_SM2_RXNEMPTY_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ1_INTE_SM1_RXNEMPTY -#define PIO_IRQ1_INTE_SM1_RXNEMPTY_RESET _u(0x0) -#define PIO_IRQ1_INTE_SM1_RXNEMPTY_BITS _u(0x00000002) -#define PIO_IRQ1_INTE_SM1_RXNEMPTY_MSB _u(1) -#define PIO_IRQ1_INTE_SM1_RXNEMPTY_LSB _u(1) -#define PIO_IRQ1_INTE_SM1_RXNEMPTY_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ1_INTE_SM0_RXNEMPTY -#define PIO_IRQ1_INTE_SM0_RXNEMPTY_RESET _u(0x0) -#define PIO_IRQ1_INTE_SM0_RXNEMPTY_BITS _u(0x00000001) -#define PIO_IRQ1_INTE_SM0_RXNEMPTY_MSB _u(0) -#define PIO_IRQ1_INTE_SM0_RXNEMPTY_LSB _u(0) -#define PIO_IRQ1_INTE_SM0_RXNEMPTY_ACCESS "RW" -// ============================================================================= -// Register : PIO_IRQ1_INTF -// Description : Interrupt Force for irq1 -#define PIO_IRQ1_INTF_OFFSET _u(0x0000013c) -#define PIO_IRQ1_INTF_BITS _u(0x00000fff) -#define PIO_IRQ1_INTF_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ1_INTF_SM3 -#define PIO_IRQ1_INTF_SM3_RESET _u(0x0) -#define PIO_IRQ1_INTF_SM3_BITS _u(0x00000800) -#define PIO_IRQ1_INTF_SM3_MSB _u(11) -#define PIO_IRQ1_INTF_SM3_LSB _u(11) -#define PIO_IRQ1_INTF_SM3_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ1_INTF_SM2 -#define PIO_IRQ1_INTF_SM2_RESET _u(0x0) -#define PIO_IRQ1_INTF_SM2_BITS _u(0x00000400) -#define PIO_IRQ1_INTF_SM2_MSB _u(10) -#define PIO_IRQ1_INTF_SM2_LSB _u(10) -#define PIO_IRQ1_INTF_SM2_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ1_INTF_SM1 -#define PIO_IRQ1_INTF_SM1_RESET _u(0x0) -#define PIO_IRQ1_INTF_SM1_BITS _u(0x00000200) -#define PIO_IRQ1_INTF_SM1_MSB _u(9) -#define PIO_IRQ1_INTF_SM1_LSB _u(9) -#define PIO_IRQ1_INTF_SM1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ1_INTF_SM0 -#define PIO_IRQ1_INTF_SM0_RESET _u(0x0) -#define PIO_IRQ1_INTF_SM0_BITS _u(0x00000100) -#define PIO_IRQ1_INTF_SM0_MSB _u(8) -#define PIO_IRQ1_INTF_SM0_LSB _u(8) -#define PIO_IRQ1_INTF_SM0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ1_INTF_SM3_TXNFULL -#define PIO_IRQ1_INTF_SM3_TXNFULL_RESET _u(0x0) -#define PIO_IRQ1_INTF_SM3_TXNFULL_BITS _u(0x00000080) -#define PIO_IRQ1_INTF_SM3_TXNFULL_MSB _u(7) -#define PIO_IRQ1_INTF_SM3_TXNFULL_LSB _u(7) -#define PIO_IRQ1_INTF_SM3_TXNFULL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ1_INTF_SM2_TXNFULL -#define PIO_IRQ1_INTF_SM2_TXNFULL_RESET _u(0x0) -#define PIO_IRQ1_INTF_SM2_TXNFULL_BITS _u(0x00000040) -#define PIO_IRQ1_INTF_SM2_TXNFULL_MSB _u(6) -#define PIO_IRQ1_INTF_SM2_TXNFULL_LSB _u(6) -#define PIO_IRQ1_INTF_SM2_TXNFULL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ1_INTF_SM1_TXNFULL -#define PIO_IRQ1_INTF_SM1_TXNFULL_RESET _u(0x0) -#define PIO_IRQ1_INTF_SM1_TXNFULL_BITS _u(0x00000020) -#define PIO_IRQ1_INTF_SM1_TXNFULL_MSB _u(5) -#define PIO_IRQ1_INTF_SM1_TXNFULL_LSB _u(5) -#define PIO_IRQ1_INTF_SM1_TXNFULL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ1_INTF_SM0_TXNFULL -#define PIO_IRQ1_INTF_SM0_TXNFULL_RESET _u(0x0) -#define PIO_IRQ1_INTF_SM0_TXNFULL_BITS _u(0x00000010) -#define PIO_IRQ1_INTF_SM0_TXNFULL_MSB _u(4) -#define PIO_IRQ1_INTF_SM0_TXNFULL_LSB _u(4) -#define PIO_IRQ1_INTF_SM0_TXNFULL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ1_INTF_SM3_RXNEMPTY -#define PIO_IRQ1_INTF_SM3_RXNEMPTY_RESET _u(0x0) -#define PIO_IRQ1_INTF_SM3_RXNEMPTY_BITS _u(0x00000008) -#define PIO_IRQ1_INTF_SM3_RXNEMPTY_MSB _u(3) -#define PIO_IRQ1_INTF_SM3_RXNEMPTY_LSB _u(3) -#define PIO_IRQ1_INTF_SM3_RXNEMPTY_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ1_INTF_SM2_RXNEMPTY -#define PIO_IRQ1_INTF_SM2_RXNEMPTY_RESET _u(0x0) -#define PIO_IRQ1_INTF_SM2_RXNEMPTY_BITS _u(0x00000004) -#define PIO_IRQ1_INTF_SM2_RXNEMPTY_MSB _u(2) -#define PIO_IRQ1_INTF_SM2_RXNEMPTY_LSB _u(2) -#define PIO_IRQ1_INTF_SM2_RXNEMPTY_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ1_INTF_SM1_RXNEMPTY -#define PIO_IRQ1_INTF_SM1_RXNEMPTY_RESET _u(0x0) -#define PIO_IRQ1_INTF_SM1_RXNEMPTY_BITS _u(0x00000002) -#define PIO_IRQ1_INTF_SM1_RXNEMPTY_MSB _u(1) -#define PIO_IRQ1_INTF_SM1_RXNEMPTY_LSB _u(1) -#define PIO_IRQ1_INTF_SM1_RXNEMPTY_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ1_INTF_SM0_RXNEMPTY -#define PIO_IRQ1_INTF_SM0_RXNEMPTY_RESET _u(0x0) -#define PIO_IRQ1_INTF_SM0_RXNEMPTY_BITS _u(0x00000001) -#define PIO_IRQ1_INTF_SM0_RXNEMPTY_MSB _u(0) -#define PIO_IRQ1_INTF_SM0_RXNEMPTY_LSB _u(0) -#define PIO_IRQ1_INTF_SM0_RXNEMPTY_ACCESS "RW" -// ============================================================================= -// Register : PIO_IRQ1_INTS -// Description : Interrupt status after masking & forcing for irq1 -#define PIO_IRQ1_INTS_OFFSET _u(0x00000140) -#define PIO_IRQ1_INTS_BITS _u(0x00000fff) -#define PIO_IRQ1_INTS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ1_INTS_SM3 -#define PIO_IRQ1_INTS_SM3_RESET _u(0x0) -#define PIO_IRQ1_INTS_SM3_BITS _u(0x00000800) -#define PIO_IRQ1_INTS_SM3_MSB _u(11) -#define PIO_IRQ1_INTS_SM3_LSB _u(11) -#define PIO_IRQ1_INTS_SM3_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ1_INTS_SM2 -#define PIO_IRQ1_INTS_SM2_RESET _u(0x0) -#define PIO_IRQ1_INTS_SM2_BITS _u(0x00000400) -#define PIO_IRQ1_INTS_SM2_MSB _u(10) -#define PIO_IRQ1_INTS_SM2_LSB _u(10) -#define PIO_IRQ1_INTS_SM2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ1_INTS_SM1 -#define PIO_IRQ1_INTS_SM1_RESET _u(0x0) -#define PIO_IRQ1_INTS_SM1_BITS _u(0x00000200) -#define PIO_IRQ1_INTS_SM1_MSB _u(9) -#define PIO_IRQ1_INTS_SM1_LSB _u(9) -#define PIO_IRQ1_INTS_SM1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ1_INTS_SM0 -#define PIO_IRQ1_INTS_SM0_RESET _u(0x0) -#define PIO_IRQ1_INTS_SM0_BITS _u(0x00000100) -#define PIO_IRQ1_INTS_SM0_MSB _u(8) -#define PIO_IRQ1_INTS_SM0_LSB _u(8) -#define PIO_IRQ1_INTS_SM0_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ1_INTS_SM3_TXNFULL -#define PIO_IRQ1_INTS_SM3_TXNFULL_RESET _u(0x0) -#define PIO_IRQ1_INTS_SM3_TXNFULL_BITS _u(0x00000080) -#define PIO_IRQ1_INTS_SM3_TXNFULL_MSB _u(7) -#define PIO_IRQ1_INTS_SM3_TXNFULL_LSB _u(7) -#define PIO_IRQ1_INTS_SM3_TXNFULL_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ1_INTS_SM2_TXNFULL -#define PIO_IRQ1_INTS_SM2_TXNFULL_RESET _u(0x0) -#define PIO_IRQ1_INTS_SM2_TXNFULL_BITS _u(0x00000040) -#define PIO_IRQ1_INTS_SM2_TXNFULL_MSB _u(6) -#define PIO_IRQ1_INTS_SM2_TXNFULL_LSB _u(6) -#define PIO_IRQ1_INTS_SM2_TXNFULL_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ1_INTS_SM1_TXNFULL -#define PIO_IRQ1_INTS_SM1_TXNFULL_RESET _u(0x0) -#define PIO_IRQ1_INTS_SM1_TXNFULL_BITS _u(0x00000020) -#define PIO_IRQ1_INTS_SM1_TXNFULL_MSB _u(5) -#define PIO_IRQ1_INTS_SM1_TXNFULL_LSB _u(5) -#define PIO_IRQ1_INTS_SM1_TXNFULL_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ1_INTS_SM0_TXNFULL -#define PIO_IRQ1_INTS_SM0_TXNFULL_RESET _u(0x0) -#define PIO_IRQ1_INTS_SM0_TXNFULL_BITS _u(0x00000010) -#define PIO_IRQ1_INTS_SM0_TXNFULL_MSB _u(4) -#define PIO_IRQ1_INTS_SM0_TXNFULL_LSB _u(4) -#define PIO_IRQ1_INTS_SM0_TXNFULL_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ1_INTS_SM3_RXNEMPTY -#define PIO_IRQ1_INTS_SM3_RXNEMPTY_RESET _u(0x0) -#define PIO_IRQ1_INTS_SM3_RXNEMPTY_BITS _u(0x00000008) -#define PIO_IRQ1_INTS_SM3_RXNEMPTY_MSB _u(3) -#define PIO_IRQ1_INTS_SM3_RXNEMPTY_LSB _u(3) -#define PIO_IRQ1_INTS_SM3_RXNEMPTY_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ1_INTS_SM2_RXNEMPTY -#define PIO_IRQ1_INTS_SM2_RXNEMPTY_RESET _u(0x0) -#define PIO_IRQ1_INTS_SM2_RXNEMPTY_BITS _u(0x00000004) -#define PIO_IRQ1_INTS_SM2_RXNEMPTY_MSB _u(2) -#define PIO_IRQ1_INTS_SM2_RXNEMPTY_LSB _u(2) -#define PIO_IRQ1_INTS_SM2_RXNEMPTY_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ1_INTS_SM1_RXNEMPTY -#define PIO_IRQ1_INTS_SM1_RXNEMPTY_RESET _u(0x0) -#define PIO_IRQ1_INTS_SM1_RXNEMPTY_BITS _u(0x00000002) -#define PIO_IRQ1_INTS_SM1_RXNEMPTY_MSB _u(1) -#define PIO_IRQ1_INTS_SM1_RXNEMPTY_LSB _u(1) -#define PIO_IRQ1_INTS_SM1_RXNEMPTY_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ1_INTS_SM0_RXNEMPTY -#define PIO_IRQ1_INTS_SM0_RXNEMPTY_RESET _u(0x0) -#define PIO_IRQ1_INTS_SM0_RXNEMPTY_BITS _u(0x00000001) -#define PIO_IRQ1_INTS_SM0_RXNEMPTY_MSB _u(0) -#define PIO_IRQ1_INTS_SM0_RXNEMPTY_LSB _u(0) -#define PIO_IRQ1_INTS_SM0_RXNEMPTY_ACCESS "RO" -// ============================================================================= -#endif // _HARDWARE_REGS_PIO_H - diff --git a/lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/pll.h b/lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/pll.h deleted file mode 100644 index 345982e859..0000000000 --- a/lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/pll.h +++ /dev/null @@ -1,137 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -// ============================================================================= -// Register block : PLL -// Version : 1 -// Bus type : apb -// ============================================================================= -#ifndef _HARDWARE_REGS_PLL_H -#define _HARDWARE_REGS_PLL_H -// ============================================================================= -// Register : PLL_CS -// Description : Control and Status -// GENERAL CONSTRAINTS: -// Reference clock frequency min=5MHz, max=800MHz -// Feedback divider min=16, max=320 -// VCO frequency min=750MHz, max=1600MHz -#define PLL_CS_OFFSET _u(0x00000000) -#define PLL_CS_BITS _u(0x8000013f) -#define PLL_CS_RESET _u(0x00000001) -// ----------------------------------------------------------------------------- -// Field : PLL_CS_LOCK -// Description : PLL is locked -#define PLL_CS_LOCK_RESET _u(0x0) -#define PLL_CS_LOCK_BITS _u(0x80000000) -#define PLL_CS_LOCK_MSB _u(31) -#define PLL_CS_LOCK_LSB _u(31) -#define PLL_CS_LOCK_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PLL_CS_BYPASS -// Description : Passes the reference clock to the output instead of the divided -// VCO. The VCO continues to run so the user can switch between -// the reference clock and the divided VCO but the output will -// glitch when doing so. -#define PLL_CS_BYPASS_RESET _u(0x0) -#define PLL_CS_BYPASS_BITS _u(0x00000100) -#define PLL_CS_BYPASS_MSB _u(8) -#define PLL_CS_BYPASS_LSB _u(8) -#define PLL_CS_BYPASS_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PLL_CS_REFDIV -// Description : Divides the PLL input reference clock. -// Behaviour is undefined for div=0. -// PLL output will be unpredictable during refdiv changes, wait -// for lock=1 before using it. -#define PLL_CS_REFDIV_RESET _u(0x01) -#define PLL_CS_REFDIV_BITS _u(0x0000003f) -#define PLL_CS_REFDIV_MSB _u(5) -#define PLL_CS_REFDIV_LSB _u(0) -#define PLL_CS_REFDIV_ACCESS "RW" -// ============================================================================= -// Register : PLL_PWR -// Description : Controls the PLL power modes. -#define PLL_PWR_OFFSET _u(0x00000004) -#define PLL_PWR_BITS _u(0x0000002d) -#define PLL_PWR_RESET _u(0x0000002d) -// ----------------------------------------------------------------------------- -// Field : PLL_PWR_VCOPD -// Description : PLL VCO powerdown -// To save power set high when PLL output not required or -// bypass=1. -#define PLL_PWR_VCOPD_RESET _u(0x1) -#define PLL_PWR_VCOPD_BITS _u(0x00000020) -#define PLL_PWR_VCOPD_MSB _u(5) -#define PLL_PWR_VCOPD_LSB _u(5) -#define PLL_PWR_VCOPD_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PLL_PWR_POSTDIVPD -// Description : PLL post divider powerdown -// To save power set high when PLL output not required or -// bypass=1. -#define PLL_PWR_POSTDIVPD_RESET _u(0x1) -#define PLL_PWR_POSTDIVPD_BITS _u(0x00000008) -#define PLL_PWR_POSTDIVPD_MSB _u(3) -#define PLL_PWR_POSTDIVPD_LSB _u(3) -#define PLL_PWR_POSTDIVPD_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PLL_PWR_DSMPD -// Description : PLL DSM powerdown -// Nothing is achieved by setting this low. -#define PLL_PWR_DSMPD_RESET _u(0x1) -#define PLL_PWR_DSMPD_BITS _u(0x00000004) -#define PLL_PWR_DSMPD_MSB _u(2) -#define PLL_PWR_DSMPD_LSB _u(2) -#define PLL_PWR_DSMPD_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PLL_PWR_PD -// Description : PLL powerdown -// To save power set high when PLL output not required. -#define PLL_PWR_PD_RESET _u(0x1) -#define PLL_PWR_PD_BITS _u(0x00000001) -#define PLL_PWR_PD_MSB _u(0) -#define PLL_PWR_PD_LSB _u(0) -#define PLL_PWR_PD_ACCESS "RW" -// ============================================================================= -// Register : PLL_FBDIV_INT -// Description : Feedback divisor -// (note: this PLL does not support fractional division) -// see ctrl reg description for constraints -#define PLL_FBDIV_INT_OFFSET _u(0x00000008) -#define PLL_FBDIV_INT_BITS _u(0x00000fff) -#define PLL_FBDIV_INT_RESET _u(0x00000000) -#define PLL_FBDIV_INT_MSB _u(11) -#define PLL_FBDIV_INT_LSB _u(0) -#define PLL_FBDIV_INT_ACCESS "RW" -// ============================================================================= -// Register : PLL_PRIM -// Description : Controls the PLL post dividers for the primary output -// (note: this PLL does not have a secondary output) -// the primary output is driven from VCO divided by -// postdiv1*postdiv2 -#define PLL_PRIM_OFFSET _u(0x0000000c) -#define PLL_PRIM_BITS _u(0x00077000) -#define PLL_PRIM_RESET _u(0x00077000) -// ----------------------------------------------------------------------------- -// Field : PLL_PRIM_POSTDIV1 -// Description : divide by 1-7 -#define PLL_PRIM_POSTDIV1_RESET _u(0x7) -#define PLL_PRIM_POSTDIV1_BITS _u(0x00070000) -#define PLL_PRIM_POSTDIV1_MSB _u(18) -#define PLL_PRIM_POSTDIV1_LSB _u(16) -#define PLL_PRIM_POSTDIV1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PLL_PRIM_POSTDIV2 -// Description : divide by 1-7 -#define PLL_PRIM_POSTDIV2_RESET _u(0x7) -#define PLL_PRIM_POSTDIV2_BITS _u(0x00007000) -#define PLL_PRIM_POSTDIV2_MSB _u(14) -#define PLL_PRIM_POSTDIV2_LSB _u(12) -#define PLL_PRIM_POSTDIV2_ACCESS "RW" -// ============================================================================= -#endif // _HARDWARE_REGS_PLL_H - diff --git a/lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/psm.h b/lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/psm.h deleted file mode 100644 index 3433f6dc4e..0000000000 --- a/lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/psm.h +++ /dev/null @@ -1,518 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -// ============================================================================= -// Register block : PSM -// Version : 1 -// Bus type : apb -// ============================================================================= -#ifndef _HARDWARE_REGS_PSM_H -#define _HARDWARE_REGS_PSM_H -// ============================================================================= -// Register : PSM_FRCE_ON -// Description : Force block out of reset (i.e. power it on) -#define PSM_FRCE_ON_OFFSET _u(0x00000000) -#define PSM_FRCE_ON_BITS _u(0x0001ffff) -#define PSM_FRCE_ON_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : PSM_FRCE_ON_PROC1 -#define PSM_FRCE_ON_PROC1_RESET _u(0x0) -#define PSM_FRCE_ON_PROC1_BITS _u(0x00010000) -#define PSM_FRCE_ON_PROC1_MSB _u(16) -#define PSM_FRCE_ON_PROC1_LSB _u(16) -#define PSM_FRCE_ON_PROC1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PSM_FRCE_ON_PROC0 -#define PSM_FRCE_ON_PROC0_RESET _u(0x0) -#define PSM_FRCE_ON_PROC0_BITS _u(0x00008000) -#define PSM_FRCE_ON_PROC0_MSB _u(15) -#define PSM_FRCE_ON_PROC0_LSB _u(15) -#define PSM_FRCE_ON_PROC0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PSM_FRCE_ON_SIO -#define PSM_FRCE_ON_SIO_RESET _u(0x0) -#define PSM_FRCE_ON_SIO_BITS _u(0x00004000) -#define PSM_FRCE_ON_SIO_MSB _u(14) -#define PSM_FRCE_ON_SIO_LSB _u(14) -#define PSM_FRCE_ON_SIO_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PSM_FRCE_ON_VREG_AND_CHIP_RESET -#define PSM_FRCE_ON_VREG_AND_CHIP_RESET_RESET _u(0x0) -#define PSM_FRCE_ON_VREG_AND_CHIP_RESET_BITS _u(0x00002000) -#define PSM_FRCE_ON_VREG_AND_CHIP_RESET_MSB _u(13) -#define PSM_FRCE_ON_VREG_AND_CHIP_RESET_LSB _u(13) -#define PSM_FRCE_ON_VREG_AND_CHIP_RESET_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PSM_FRCE_ON_XIP -#define PSM_FRCE_ON_XIP_RESET _u(0x0) -#define PSM_FRCE_ON_XIP_BITS _u(0x00001000) -#define PSM_FRCE_ON_XIP_MSB _u(12) -#define PSM_FRCE_ON_XIP_LSB _u(12) -#define PSM_FRCE_ON_XIP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PSM_FRCE_ON_SRAM5 -#define PSM_FRCE_ON_SRAM5_RESET _u(0x0) -#define PSM_FRCE_ON_SRAM5_BITS _u(0x00000800) -#define PSM_FRCE_ON_SRAM5_MSB _u(11) -#define PSM_FRCE_ON_SRAM5_LSB _u(11) -#define PSM_FRCE_ON_SRAM5_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PSM_FRCE_ON_SRAM4 -#define PSM_FRCE_ON_SRAM4_RESET _u(0x0) -#define PSM_FRCE_ON_SRAM4_BITS _u(0x00000400) -#define PSM_FRCE_ON_SRAM4_MSB _u(10) -#define PSM_FRCE_ON_SRAM4_LSB _u(10) -#define PSM_FRCE_ON_SRAM4_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PSM_FRCE_ON_SRAM3 -#define PSM_FRCE_ON_SRAM3_RESET _u(0x0) -#define PSM_FRCE_ON_SRAM3_BITS _u(0x00000200) -#define PSM_FRCE_ON_SRAM3_MSB _u(9) -#define PSM_FRCE_ON_SRAM3_LSB _u(9) -#define PSM_FRCE_ON_SRAM3_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PSM_FRCE_ON_SRAM2 -#define PSM_FRCE_ON_SRAM2_RESET _u(0x0) -#define PSM_FRCE_ON_SRAM2_BITS _u(0x00000100) -#define PSM_FRCE_ON_SRAM2_MSB _u(8) -#define PSM_FRCE_ON_SRAM2_LSB _u(8) -#define PSM_FRCE_ON_SRAM2_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PSM_FRCE_ON_SRAM1 -#define PSM_FRCE_ON_SRAM1_RESET _u(0x0) -#define PSM_FRCE_ON_SRAM1_BITS _u(0x00000080) -#define PSM_FRCE_ON_SRAM1_MSB _u(7) -#define PSM_FRCE_ON_SRAM1_LSB _u(7) -#define PSM_FRCE_ON_SRAM1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PSM_FRCE_ON_SRAM0 -#define PSM_FRCE_ON_SRAM0_RESET _u(0x0) -#define PSM_FRCE_ON_SRAM0_BITS _u(0x00000040) -#define PSM_FRCE_ON_SRAM0_MSB _u(6) -#define PSM_FRCE_ON_SRAM0_LSB _u(6) -#define PSM_FRCE_ON_SRAM0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PSM_FRCE_ON_ROM -#define PSM_FRCE_ON_ROM_RESET _u(0x0) -#define PSM_FRCE_ON_ROM_BITS _u(0x00000020) -#define PSM_FRCE_ON_ROM_MSB _u(5) -#define PSM_FRCE_ON_ROM_LSB _u(5) -#define PSM_FRCE_ON_ROM_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PSM_FRCE_ON_BUSFABRIC -#define PSM_FRCE_ON_BUSFABRIC_RESET _u(0x0) -#define PSM_FRCE_ON_BUSFABRIC_BITS _u(0x00000010) -#define PSM_FRCE_ON_BUSFABRIC_MSB _u(4) -#define PSM_FRCE_ON_BUSFABRIC_LSB _u(4) -#define PSM_FRCE_ON_BUSFABRIC_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PSM_FRCE_ON_RESETS -#define PSM_FRCE_ON_RESETS_RESET _u(0x0) -#define PSM_FRCE_ON_RESETS_BITS _u(0x00000008) -#define PSM_FRCE_ON_RESETS_MSB _u(3) -#define PSM_FRCE_ON_RESETS_LSB _u(3) -#define PSM_FRCE_ON_RESETS_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PSM_FRCE_ON_CLOCKS -#define PSM_FRCE_ON_CLOCKS_RESET _u(0x0) -#define PSM_FRCE_ON_CLOCKS_BITS _u(0x00000004) -#define PSM_FRCE_ON_CLOCKS_MSB _u(2) -#define PSM_FRCE_ON_CLOCKS_LSB _u(2) -#define PSM_FRCE_ON_CLOCKS_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PSM_FRCE_ON_XOSC -#define PSM_FRCE_ON_XOSC_RESET _u(0x0) -#define PSM_FRCE_ON_XOSC_BITS _u(0x00000002) -#define PSM_FRCE_ON_XOSC_MSB _u(1) -#define PSM_FRCE_ON_XOSC_LSB _u(1) -#define PSM_FRCE_ON_XOSC_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PSM_FRCE_ON_ROSC -#define PSM_FRCE_ON_ROSC_RESET _u(0x0) -#define PSM_FRCE_ON_ROSC_BITS _u(0x00000001) -#define PSM_FRCE_ON_ROSC_MSB _u(0) -#define PSM_FRCE_ON_ROSC_LSB _u(0) -#define PSM_FRCE_ON_ROSC_ACCESS "RW" -// ============================================================================= -// Register : PSM_FRCE_OFF -// Description : Force into reset (i.e. power it off) -#define PSM_FRCE_OFF_OFFSET _u(0x00000004) -#define PSM_FRCE_OFF_BITS _u(0x0001ffff) -#define PSM_FRCE_OFF_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : PSM_FRCE_OFF_PROC1 -#define PSM_FRCE_OFF_PROC1_RESET _u(0x0) -#define PSM_FRCE_OFF_PROC1_BITS _u(0x00010000) -#define PSM_FRCE_OFF_PROC1_MSB _u(16) -#define PSM_FRCE_OFF_PROC1_LSB _u(16) -#define PSM_FRCE_OFF_PROC1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PSM_FRCE_OFF_PROC0 -#define PSM_FRCE_OFF_PROC0_RESET _u(0x0) -#define PSM_FRCE_OFF_PROC0_BITS _u(0x00008000) -#define PSM_FRCE_OFF_PROC0_MSB _u(15) -#define PSM_FRCE_OFF_PROC0_LSB _u(15) -#define PSM_FRCE_OFF_PROC0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PSM_FRCE_OFF_SIO -#define PSM_FRCE_OFF_SIO_RESET _u(0x0) -#define PSM_FRCE_OFF_SIO_BITS _u(0x00004000) -#define PSM_FRCE_OFF_SIO_MSB _u(14) -#define PSM_FRCE_OFF_SIO_LSB _u(14) -#define PSM_FRCE_OFF_SIO_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PSM_FRCE_OFF_VREG_AND_CHIP_RESET -#define PSM_FRCE_OFF_VREG_AND_CHIP_RESET_RESET _u(0x0) -#define PSM_FRCE_OFF_VREG_AND_CHIP_RESET_BITS _u(0x00002000) -#define PSM_FRCE_OFF_VREG_AND_CHIP_RESET_MSB _u(13) -#define PSM_FRCE_OFF_VREG_AND_CHIP_RESET_LSB _u(13) -#define PSM_FRCE_OFF_VREG_AND_CHIP_RESET_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PSM_FRCE_OFF_XIP -#define PSM_FRCE_OFF_XIP_RESET _u(0x0) -#define PSM_FRCE_OFF_XIP_BITS _u(0x00001000) -#define PSM_FRCE_OFF_XIP_MSB _u(12) -#define PSM_FRCE_OFF_XIP_LSB _u(12) -#define PSM_FRCE_OFF_XIP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PSM_FRCE_OFF_SRAM5 -#define PSM_FRCE_OFF_SRAM5_RESET _u(0x0) -#define PSM_FRCE_OFF_SRAM5_BITS _u(0x00000800) -#define PSM_FRCE_OFF_SRAM5_MSB _u(11) -#define PSM_FRCE_OFF_SRAM5_LSB _u(11) -#define PSM_FRCE_OFF_SRAM5_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PSM_FRCE_OFF_SRAM4 -#define PSM_FRCE_OFF_SRAM4_RESET _u(0x0) -#define PSM_FRCE_OFF_SRAM4_BITS _u(0x00000400) -#define PSM_FRCE_OFF_SRAM4_MSB _u(10) -#define PSM_FRCE_OFF_SRAM4_LSB _u(10) -#define PSM_FRCE_OFF_SRAM4_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PSM_FRCE_OFF_SRAM3 -#define PSM_FRCE_OFF_SRAM3_RESET _u(0x0) -#define PSM_FRCE_OFF_SRAM3_BITS _u(0x00000200) -#define PSM_FRCE_OFF_SRAM3_MSB _u(9) -#define PSM_FRCE_OFF_SRAM3_LSB _u(9) -#define PSM_FRCE_OFF_SRAM3_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PSM_FRCE_OFF_SRAM2 -#define PSM_FRCE_OFF_SRAM2_RESET _u(0x0) -#define PSM_FRCE_OFF_SRAM2_BITS _u(0x00000100) -#define PSM_FRCE_OFF_SRAM2_MSB _u(8) -#define PSM_FRCE_OFF_SRAM2_LSB _u(8) -#define PSM_FRCE_OFF_SRAM2_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PSM_FRCE_OFF_SRAM1 -#define PSM_FRCE_OFF_SRAM1_RESET _u(0x0) -#define PSM_FRCE_OFF_SRAM1_BITS _u(0x00000080) -#define PSM_FRCE_OFF_SRAM1_MSB _u(7) -#define PSM_FRCE_OFF_SRAM1_LSB _u(7) -#define PSM_FRCE_OFF_SRAM1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PSM_FRCE_OFF_SRAM0 -#define PSM_FRCE_OFF_SRAM0_RESET _u(0x0) -#define PSM_FRCE_OFF_SRAM0_BITS _u(0x00000040) -#define PSM_FRCE_OFF_SRAM0_MSB _u(6) -#define PSM_FRCE_OFF_SRAM0_LSB _u(6) -#define PSM_FRCE_OFF_SRAM0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PSM_FRCE_OFF_ROM -#define PSM_FRCE_OFF_ROM_RESET _u(0x0) -#define PSM_FRCE_OFF_ROM_BITS _u(0x00000020) -#define PSM_FRCE_OFF_ROM_MSB _u(5) -#define PSM_FRCE_OFF_ROM_LSB _u(5) -#define PSM_FRCE_OFF_ROM_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PSM_FRCE_OFF_BUSFABRIC -#define PSM_FRCE_OFF_BUSFABRIC_RESET _u(0x0) -#define PSM_FRCE_OFF_BUSFABRIC_BITS _u(0x00000010) -#define PSM_FRCE_OFF_BUSFABRIC_MSB _u(4) -#define PSM_FRCE_OFF_BUSFABRIC_LSB _u(4) -#define PSM_FRCE_OFF_BUSFABRIC_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PSM_FRCE_OFF_RESETS -#define PSM_FRCE_OFF_RESETS_RESET _u(0x0) -#define PSM_FRCE_OFF_RESETS_BITS _u(0x00000008) -#define PSM_FRCE_OFF_RESETS_MSB _u(3) -#define PSM_FRCE_OFF_RESETS_LSB _u(3) -#define PSM_FRCE_OFF_RESETS_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PSM_FRCE_OFF_CLOCKS -#define PSM_FRCE_OFF_CLOCKS_RESET _u(0x0) -#define PSM_FRCE_OFF_CLOCKS_BITS _u(0x00000004) -#define PSM_FRCE_OFF_CLOCKS_MSB _u(2) -#define PSM_FRCE_OFF_CLOCKS_LSB _u(2) -#define PSM_FRCE_OFF_CLOCKS_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PSM_FRCE_OFF_XOSC -#define PSM_FRCE_OFF_XOSC_RESET _u(0x0) -#define PSM_FRCE_OFF_XOSC_BITS _u(0x00000002) -#define PSM_FRCE_OFF_XOSC_MSB _u(1) -#define PSM_FRCE_OFF_XOSC_LSB _u(1) -#define PSM_FRCE_OFF_XOSC_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PSM_FRCE_OFF_ROSC -#define PSM_FRCE_OFF_ROSC_RESET _u(0x0) -#define PSM_FRCE_OFF_ROSC_BITS _u(0x00000001) -#define PSM_FRCE_OFF_ROSC_MSB _u(0) -#define PSM_FRCE_OFF_ROSC_LSB _u(0) -#define PSM_FRCE_OFF_ROSC_ACCESS "RW" -// ============================================================================= -// Register : PSM_WDSEL -// Description : Set to 1 if this peripheral should be reset when the watchdog -// fires. -#define PSM_WDSEL_OFFSET _u(0x00000008) -#define PSM_WDSEL_BITS _u(0x0001ffff) -#define PSM_WDSEL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : PSM_WDSEL_PROC1 -#define PSM_WDSEL_PROC1_RESET _u(0x0) -#define PSM_WDSEL_PROC1_BITS _u(0x00010000) -#define PSM_WDSEL_PROC1_MSB _u(16) -#define PSM_WDSEL_PROC1_LSB _u(16) -#define PSM_WDSEL_PROC1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PSM_WDSEL_PROC0 -#define PSM_WDSEL_PROC0_RESET _u(0x0) -#define PSM_WDSEL_PROC0_BITS _u(0x00008000) -#define PSM_WDSEL_PROC0_MSB _u(15) -#define PSM_WDSEL_PROC0_LSB _u(15) -#define PSM_WDSEL_PROC0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PSM_WDSEL_SIO -#define PSM_WDSEL_SIO_RESET _u(0x0) -#define PSM_WDSEL_SIO_BITS _u(0x00004000) -#define PSM_WDSEL_SIO_MSB _u(14) -#define PSM_WDSEL_SIO_LSB _u(14) -#define PSM_WDSEL_SIO_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PSM_WDSEL_VREG_AND_CHIP_RESET -#define PSM_WDSEL_VREG_AND_CHIP_RESET_RESET _u(0x0) -#define PSM_WDSEL_VREG_AND_CHIP_RESET_BITS _u(0x00002000) -#define PSM_WDSEL_VREG_AND_CHIP_RESET_MSB _u(13) -#define PSM_WDSEL_VREG_AND_CHIP_RESET_LSB _u(13) -#define PSM_WDSEL_VREG_AND_CHIP_RESET_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PSM_WDSEL_XIP -#define PSM_WDSEL_XIP_RESET _u(0x0) -#define PSM_WDSEL_XIP_BITS _u(0x00001000) -#define PSM_WDSEL_XIP_MSB _u(12) -#define PSM_WDSEL_XIP_LSB _u(12) -#define PSM_WDSEL_XIP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PSM_WDSEL_SRAM5 -#define PSM_WDSEL_SRAM5_RESET _u(0x0) -#define PSM_WDSEL_SRAM5_BITS _u(0x00000800) -#define PSM_WDSEL_SRAM5_MSB _u(11) -#define PSM_WDSEL_SRAM5_LSB _u(11) -#define PSM_WDSEL_SRAM5_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PSM_WDSEL_SRAM4 -#define PSM_WDSEL_SRAM4_RESET _u(0x0) -#define PSM_WDSEL_SRAM4_BITS _u(0x00000400) -#define PSM_WDSEL_SRAM4_MSB _u(10) -#define PSM_WDSEL_SRAM4_LSB _u(10) -#define PSM_WDSEL_SRAM4_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PSM_WDSEL_SRAM3 -#define PSM_WDSEL_SRAM3_RESET _u(0x0) -#define PSM_WDSEL_SRAM3_BITS _u(0x00000200) -#define PSM_WDSEL_SRAM3_MSB _u(9) -#define PSM_WDSEL_SRAM3_LSB _u(9) -#define PSM_WDSEL_SRAM3_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PSM_WDSEL_SRAM2 -#define PSM_WDSEL_SRAM2_RESET _u(0x0) -#define PSM_WDSEL_SRAM2_BITS _u(0x00000100) -#define PSM_WDSEL_SRAM2_MSB _u(8) -#define PSM_WDSEL_SRAM2_LSB _u(8) -#define PSM_WDSEL_SRAM2_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PSM_WDSEL_SRAM1 -#define PSM_WDSEL_SRAM1_RESET _u(0x0) -#define PSM_WDSEL_SRAM1_BITS _u(0x00000080) -#define PSM_WDSEL_SRAM1_MSB _u(7) -#define PSM_WDSEL_SRAM1_LSB _u(7) -#define PSM_WDSEL_SRAM1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PSM_WDSEL_SRAM0 -#define PSM_WDSEL_SRAM0_RESET _u(0x0) -#define PSM_WDSEL_SRAM0_BITS _u(0x00000040) -#define PSM_WDSEL_SRAM0_MSB _u(6) -#define PSM_WDSEL_SRAM0_LSB _u(6) -#define PSM_WDSEL_SRAM0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PSM_WDSEL_ROM -#define PSM_WDSEL_ROM_RESET _u(0x0) -#define PSM_WDSEL_ROM_BITS _u(0x00000020) -#define PSM_WDSEL_ROM_MSB _u(5) -#define PSM_WDSEL_ROM_LSB _u(5) -#define PSM_WDSEL_ROM_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PSM_WDSEL_BUSFABRIC -#define PSM_WDSEL_BUSFABRIC_RESET _u(0x0) -#define PSM_WDSEL_BUSFABRIC_BITS _u(0x00000010) -#define PSM_WDSEL_BUSFABRIC_MSB _u(4) -#define PSM_WDSEL_BUSFABRIC_LSB _u(4) -#define PSM_WDSEL_BUSFABRIC_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PSM_WDSEL_RESETS -#define PSM_WDSEL_RESETS_RESET _u(0x0) -#define PSM_WDSEL_RESETS_BITS _u(0x00000008) -#define PSM_WDSEL_RESETS_MSB _u(3) -#define PSM_WDSEL_RESETS_LSB _u(3) -#define PSM_WDSEL_RESETS_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PSM_WDSEL_CLOCKS -#define PSM_WDSEL_CLOCKS_RESET _u(0x0) -#define PSM_WDSEL_CLOCKS_BITS _u(0x00000004) -#define PSM_WDSEL_CLOCKS_MSB _u(2) -#define PSM_WDSEL_CLOCKS_LSB _u(2) -#define PSM_WDSEL_CLOCKS_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PSM_WDSEL_XOSC -#define PSM_WDSEL_XOSC_RESET _u(0x0) -#define PSM_WDSEL_XOSC_BITS _u(0x00000002) -#define PSM_WDSEL_XOSC_MSB _u(1) -#define PSM_WDSEL_XOSC_LSB _u(1) -#define PSM_WDSEL_XOSC_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PSM_WDSEL_ROSC -#define PSM_WDSEL_ROSC_RESET _u(0x0) -#define PSM_WDSEL_ROSC_BITS _u(0x00000001) -#define PSM_WDSEL_ROSC_MSB _u(0) -#define PSM_WDSEL_ROSC_LSB _u(0) -#define PSM_WDSEL_ROSC_ACCESS "RW" -// ============================================================================= -// Register : PSM_DONE -// Description : Indicates the peripheral's registers are ready to access. -#define PSM_DONE_OFFSET _u(0x0000000c) -#define PSM_DONE_BITS _u(0x0001ffff) -#define PSM_DONE_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : PSM_DONE_PROC1 -#define PSM_DONE_PROC1_RESET _u(0x0) -#define PSM_DONE_PROC1_BITS _u(0x00010000) -#define PSM_DONE_PROC1_MSB _u(16) -#define PSM_DONE_PROC1_LSB _u(16) -#define PSM_DONE_PROC1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PSM_DONE_PROC0 -#define PSM_DONE_PROC0_RESET _u(0x0) -#define PSM_DONE_PROC0_BITS _u(0x00008000) -#define PSM_DONE_PROC0_MSB _u(15) -#define PSM_DONE_PROC0_LSB _u(15) -#define PSM_DONE_PROC0_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PSM_DONE_SIO -#define PSM_DONE_SIO_RESET _u(0x0) -#define PSM_DONE_SIO_BITS _u(0x00004000) -#define PSM_DONE_SIO_MSB _u(14) -#define PSM_DONE_SIO_LSB _u(14) -#define PSM_DONE_SIO_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PSM_DONE_VREG_AND_CHIP_RESET -#define PSM_DONE_VREG_AND_CHIP_RESET_RESET _u(0x0) -#define PSM_DONE_VREG_AND_CHIP_RESET_BITS _u(0x00002000) -#define PSM_DONE_VREG_AND_CHIP_RESET_MSB _u(13) -#define PSM_DONE_VREG_AND_CHIP_RESET_LSB _u(13) -#define PSM_DONE_VREG_AND_CHIP_RESET_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PSM_DONE_XIP -#define PSM_DONE_XIP_RESET _u(0x0) -#define PSM_DONE_XIP_BITS _u(0x00001000) -#define PSM_DONE_XIP_MSB _u(12) -#define PSM_DONE_XIP_LSB _u(12) -#define PSM_DONE_XIP_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PSM_DONE_SRAM5 -#define PSM_DONE_SRAM5_RESET _u(0x0) -#define PSM_DONE_SRAM5_BITS _u(0x00000800) -#define PSM_DONE_SRAM5_MSB _u(11) -#define PSM_DONE_SRAM5_LSB _u(11) -#define PSM_DONE_SRAM5_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PSM_DONE_SRAM4 -#define PSM_DONE_SRAM4_RESET _u(0x0) -#define PSM_DONE_SRAM4_BITS _u(0x00000400) -#define PSM_DONE_SRAM4_MSB _u(10) -#define PSM_DONE_SRAM4_LSB _u(10) -#define PSM_DONE_SRAM4_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PSM_DONE_SRAM3 -#define PSM_DONE_SRAM3_RESET _u(0x0) -#define PSM_DONE_SRAM3_BITS _u(0x00000200) -#define PSM_DONE_SRAM3_MSB _u(9) -#define PSM_DONE_SRAM3_LSB _u(9) -#define PSM_DONE_SRAM3_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PSM_DONE_SRAM2 -#define PSM_DONE_SRAM2_RESET _u(0x0) -#define PSM_DONE_SRAM2_BITS _u(0x00000100) -#define PSM_DONE_SRAM2_MSB _u(8) -#define PSM_DONE_SRAM2_LSB _u(8) -#define PSM_DONE_SRAM2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PSM_DONE_SRAM1 -#define PSM_DONE_SRAM1_RESET _u(0x0) -#define PSM_DONE_SRAM1_BITS _u(0x00000080) -#define PSM_DONE_SRAM1_MSB _u(7) -#define PSM_DONE_SRAM1_LSB _u(7) -#define PSM_DONE_SRAM1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PSM_DONE_SRAM0 -#define PSM_DONE_SRAM0_RESET _u(0x0) -#define PSM_DONE_SRAM0_BITS _u(0x00000040) -#define PSM_DONE_SRAM0_MSB _u(6) -#define PSM_DONE_SRAM0_LSB _u(6) -#define PSM_DONE_SRAM0_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PSM_DONE_ROM -#define PSM_DONE_ROM_RESET _u(0x0) -#define PSM_DONE_ROM_BITS _u(0x00000020) -#define PSM_DONE_ROM_MSB _u(5) -#define PSM_DONE_ROM_LSB _u(5) -#define PSM_DONE_ROM_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PSM_DONE_BUSFABRIC -#define PSM_DONE_BUSFABRIC_RESET _u(0x0) -#define PSM_DONE_BUSFABRIC_BITS _u(0x00000010) -#define PSM_DONE_BUSFABRIC_MSB _u(4) -#define PSM_DONE_BUSFABRIC_LSB _u(4) -#define PSM_DONE_BUSFABRIC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PSM_DONE_RESETS -#define PSM_DONE_RESETS_RESET _u(0x0) -#define PSM_DONE_RESETS_BITS _u(0x00000008) -#define PSM_DONE_RESETS_MSB _u(3) -#define PSM_DONE_RESETS_LSB _u(3) -#define PSM_DONE_RESETS_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PSM_DONE_CLOCKS -#define PSM_DONE_CLOCKS_RESET _u(0x0) -#define PSM_DONE_CLOCKS_BITS _u(0x00000004) -#define PSM_DONE_CLOCKS_MSB _u(2) -#define PSM_DONE_CLOCKS_LSB _u(2) -#define PSM_DONE_CLOCKS_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PSM_DONE_XOSC -#define PSM_DONE_XOSC_RESET _u(0x0) -#define PSM_DONE_XOSC_BITS _u(0x00000002) -#define PSM_DONE_XOSC_MSB _u(1) -#define PSM_DONE_XOSC_LSB _u(1) -#define PSM_DONE_XOSC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PSM_DONE_ROSC -#define PSM_DONE_ROSC_RESET _u(0x0) -#define PSM_DONE_ROSC_BITS _u(0x00000001) -#define PSM_DONE_ROSC_MSB _u(0) -#define PSM_DONE_ROSC_LSB _u(0) -#define PSM_DONE_ROSC_ACCESS "RO" -// ============================================================================= -#endif // _HARDWARE_REGS_PSM_H - diff --git a/lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/pwm.h b/lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/pwm.h deleted file mode 100644 index 29a24f8d07..0000000000 --- a/lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/pwm.h +++ /dev/null @@ -1,1420 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -// ============================================================================= -// Register block : PWM -// Version : 1 -// Bus type : apb -// Description : Simple PWM -// ============================================================================= -#ifndef _HARDWARE_REGS_PWM_H -#define _HARDWARE_REGS_PWM_H -// ============================================================================= -// Register : PWM_CH0_CSR -// Description : Control and status register -#define PWM_CH0_CSR_OFFSET _u(0x00000000) -#define PWM_CH0_CSR_BITS _u(0x000000ff) -#define PWM_CH0_CSR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : PWM_CH0_CSR_PH_ADV -// Description : Advance the phase of the counter by 1 count, while it is -// running. -// Self-clearing. Write a 1, and poll until low. Counter must be -// running -// at less than full speed (div_int + div_frac / 16 > 1) -#define PWM_CH0_CSR_PH_ADV_RESET _u(0x0) -#define PWM_CH0_CSR_PH_ADV_BITS _u(0x00000080) -#define PWM_CH0_CSR_PH_ADV_MSB _u(7) -#define PWM_CH0_CSR_PH_ADV_LSB _u(7) -#define PWM_CH0_CSR_PH_ADV_ACCESS "SC" -// ----------------------------------------------------------------------------- -// Field : PWM_CH0_CSR_PH_RET -// Description : Retard the phase of the counter by 1 count, while it is -// running. -// Self-clearing. Write a 1, and poll until low. Counter must be -// running. -#define PWM_CH0_CSR_PH_RET_RESET _u(0x0) -#define PWM_CH0_CSR_PH_RET_BITS _u(0x00000040) -#define PWM_CH0_CSR_PH_RET_MSB _u(6) -#define PWM_CH0_CSR_PH_RET_LSB _u(6) -#define PWM_CH0_CSR_PH_RET_ACCESS "SC" -// ----------------------------------------------------------------------------- -// Field : PWM_CH0_CSR_DIVMODE -// 0x0 -> Free-running counting at rate dictated by fractional divider -// 0x1 -> Fractional divider operation is gated by the PWM B pin. -// 0x2 -> Counter advances with each rising edge of the PWM B pin. -// 0x3 -> Counter advances with each falling edge of the PWM B pin. -#define PWM_CH0_CSR_DIVMODE_RESET _u(0x0) -#define PWM_CH0_CSR_DIVMODE_BITS _u(0x00000030) -#define PWM_CH0_CSR_DIVMODE_MSB _u(5) -#define PWM_CH0_CSR_DIVMODE_LSB _u(4) -#define PWM_CH0_CSR_DIVMODE_ACCESS "RW" -#define PWM_CH0_CSR_DIVMODE_VALUE_DIV _u(0x0) -#define PWM_CH0_CSR_DIVMODE_VALUE_LEVEL _u(0x1) -#define PWM_CH0_CSR_DIVMODE_VALUE_RISE _u(0x2) -#define PWM_CH0_CSR_DIVMODE_VALUE_FALL _u(0x3) -// ----------------------------------------------------------------------------- -// Field : PWM_CH0_CSR_B_INV -// Description : Invert output B -#define PWM_CH0_CSR_B_INV_RESET _u(0x0) -#define PWM_CH0_CSR_B_INV_BITS _u(0x00000008) -#define PWM_CH0_CSR_B_INV_MSB _u(3) -#define PWM_CH0_CSR_B_INV_LSB _u(3) -#define PWM_CH0_CSR_B_INV_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_CH0_CSR_A_INV -// Description : Invert output A -#define PWM_CH0_CSR_A_INV_RESET _u(0x0) -#define PWM_CH0_CSR_A_INV_BITS _u(0x00000004) -#define PWM_CH0_CSR_A_INV_MSB _u(2) -#define PWM_CH0_CSR_A_INV_LSB _u(2) -#define PWM_CH0_CSR_A_INV_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_CH0_CSR_PH_CORRECT -// Description : 1: Enable phase-correct modulation. 0: Trailing-edge -#define PWM_CH0_CSR_PH_CORRECT_RESET _u(0x0) -#define PWM_CH0_CSR_PH_CORRECT_BITS _u(0x00000002) -#define PWM_CH0_CSR_PH_CORRECT_MSB _u(1) -#define PWM_CH0_CSR_PH_CORRECT_LSB _u(1) -#define PWM_CH0_CSR_PH_CORRECT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_CH0_CSR_EN -// Description : Enable the PWM channel. -#define PWM_CH0_CSR_EN_RESET _u(0x0) -#define PWM_CH0_CSR_EN_BITS _u(0x00000001) -#define PWM_CH0_CSR_EN_MSB _u(0) -#define PWM_CH0_CSR_EN_LSB _u(0) -#define PWM_CH0_CSR_EN_ACCESS "RW" -// ============================================================================= -// Register : PWM_CH0_DIV -// Description : INT and FRAC form a fixed-point fractional number. -// Counting rate is system clock frequency divided by this number. -// Fractional division uses simple 1st-order sigma-delta. -#define PWM_CH0_DIV_OFFSET _u(0x00000004) -#define PWM_CH0_DIV_BITS _u(0x00000fff) -#define PWM_CH0_DIV_RESET _u(0x00000010) -// ----------------------------------------------------------------------------- -// Field : PWM_CH0_DIV_INT -#define PWM_CH0_DIV_INT_RESET _u(0x01) -#define PWM_CH0_DIV_INT_BITS _u(0x00000ff0) -#define PWM_CH0_DIV_INT_MSB _u(11) -#define PWM_CH0_DIV_INT_LSB _u(4) -#define PWM_CH0_DIV_INT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_CH0_DIV_FRAC -#define PWM_CH0_DIV_FRAC_RESET _u(0x0) -#define PWM_CH0_DIV_FRAC_BITS _u(0x0000000f) -#define PWM_CH0_DIV_FRAC_MSB _u(3) -#define PWM_CH0_DIV_FRAC_LSB _u(0) -#define PWM_CH0_DIV_FRAC_ACCESS "RW" -// ============================================================================= -// Register : PWM_CH0_CTR -// Description : Direct access to the PWM counter -#define PWM_CH0_CTR_OFFSET _u(0x00000008) -#define PWM_CH0_CTR_BITS _u(0x0000ffff) -#define PWM_CH0_CTR_RESET _u(0x00000000) -#define PWM_CH0_CTR_MSB _u(15) -#define PWM_CH0_CTR_LSB _u(0) -#define PWM_CH0_CTR_ACCESS "RW" -// ============================================================================= -// Register : PWM_CH0_CC -// Description : Counter compare values -#define PWM_CH0_CC_OFFSET _u(0x0000000c) -#define PWM_CH0_CC_BITS _u(0xffffffff) -#define PWM_CH0_CC_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : PWM_CH0_CC_B -#define PWM_CH0_CC_B_RESET _u(0x0000) -#define PWM_CH0_CC_B_BITS _u(0xffff0000) -#define PWM_CH0_CC_B_MSB _u(31) -#define PWM_CH0_CC_B_LSB _u(16) -#define PWM_CH0_CC_B_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_CH0_CC_A -#define PWM_CH0_CC_A_RESET _u(0x0000) -#define PWM_CH0_CC_A_BITS _u(0x0000ffff) -#define PWM_CH0_CC_A_MSB _u(15) -#define PWM_CH0_CC_A_LSB _u(0) -#define PWM_CH0_CC_A_ACCESS "RW" -// ============================================================================= -// Register : PWM_CH0_TOP -// Description : Counter wrap value -#define PWM_CH0_TOP_OFFSET _u(0x00000010) -#define PWM_CH0_TOP_BITS _u(0x0000ffff) -#define PWM_CH0_TOP_RESET _u(0x0000ffff) -#define PWM_CH0_TOP_MSB _u(15) -#define PWM_CH0_TOP_LSB _u(0) -#define PWM_CH0_TOP_ACCESS "RW" -// ============================================================================= -// Register : PWM_CH1_CSR -// Description : Control and status register -#define PWM_CH1_CSR_OFFSET _u(0x00000014) -#define PWM_CH1_CSR_BITS _u(0x000000ff) -#define PWM_CH1_CSR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : PWM_CH1_CSR_PH_ADV -// Description : Advance the phase of the counter by 1 count, while it is -// running. -// Self-clearing. Write a 1, and poll until low. Counter must be -// running -// at less than full speed (div_int + div_frac / 16 > 1) -#define PWM_CH1_CSR_PH_ADV_RESET _u(0x0) -#define PWM_CH1_CSR_PH_ADV_BITS _u(0x00000080) -#define PWM_CH1_CSR_PH_ADV_MSB _u(7) -#define PWM_CH1_CSR_PH_ADV_LSB _u(7) -#define PWM_CH1_CSR_PH_ADV_ACCESS "SC" -// ----------------------------------------------------------------------------- -// Field : PWM_CH1_CSR_PH_RET -// Description : Retard the phase of the counter by 1 count, while it is -// running. -// Self-clearing. Write a 1, and poll until low. Counter must be -// running. -#define PWM_CH1_CSR_PH_RET_RESET _u(0x0) -#define PWM_CH1_CSR_PH_RET_BITS _u(0x00000040) -#define PWM_CH1_CSR_PH_RET_MSB _u(6) -#define PWM_CH1_CSR_PH_RET_LSB _u(6) -#define PWM_CH1_CSR_PH_RET_ACCESS "SC" -// ----------------------------------------------------------------------------- -// Field : PWM_CH1_CSR_DIVMODE -// 0x0 -> Free-running counting at rate dictated by fractional divider -// 0x1 -> Fractional divider operation is gated by the PWM B pin. -// 0x2 -> Counter advances with each rising edge of the PWM B pin. -// 0x3 -> Counter advances with each falling edge of the PWM B pin. -#define PWM_CH1_CSR_DIVMODE_RESET _u(0x0) -#define PWM_CH1_CSR_DIVMODE_BITS _u(0x00000030) -#define PWM_CH1_CSR_DIVMODE_MSB _u(5) -#define PWM_CH1_CSR_DIVMODE_LSB _u(4) -#define PWM_CH1_CSR_DIVMODE_ACCESS "RW" -#define PWM_CH1_CSR_DIVMODE_VALUE_DIV _u(0x0) -#define PWM_CH1_CSR_DIVMODE_VALUE_LEVEL _u(0x1) -#define PWM_CH1_CSR_DIVMODE_VALUE_RISE _u(0x2) -#define PWM_CH1_CSR_DIVMODE_VALUE_FALL _u(0x3) -// ----------------------------------------------------------------------------- -// Field : PWM_CH1_CSR_B_INV -// Description : Invert output B -#define PWM_CH1_CSR_B_INV_RESET _u(0x0) -#define PWM_CH1_CSR_B_INV_BITS _u(0x00000008) -#define PWM_CH1_CSR_B_INV_MSB _u(3) -#define PWM_CH1_CSR_B_INV_LSB _u(3) -#define PWM_CH1_CSR_B_INV_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_CH1_CSR_A_INV -// Description : Invert output A -#define PWM_CH1_CSR_A_INV_RESET _u(0x0) -#define PWM_CH1_CSR_A_INV_BITS _u(0x00000004) -#define PWM_CH1_CSR_A_INV_MSB _u(2) -#define PWM_CH1_CSR_A_INV_LSB _u(2) -#define PWM_CH1_CSR_A_INV_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_CH1_CSR_PH_CORRECT -// Description : 1: Enable phase-correct modulation. 0: Trailing-edge -#define PWM_CH1_CSR_PH_CORRECT_RESET _u(0x0) -#define PWM_CH1_CSR_PH_CORRECT_BITS _u(0x00000002) -#define PWM_CH1_CSR_PH_CORRECT_MSB _u(1) -#define PWM_CH1_CSR_PH_CORRECT_LSB _u(1) -#define PWM_CH1_CSR_PH_CORRECT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_CH1_CSR_EN -// Description : Enable the PWM channel. -#define PWM_CH1_CSR_EN_RESET _u(0x0) -#define PWM_CH1_CSR_EN_BITS _u(0x00000001) -#define PWM_CH1_CSR_EN_MSB _u(0) -#define PWM_CH1_CSR_EN_LSB _u(0) -#define PWM_CH1_CSR_EN_ACCESS "RW" -// ============================================================================= -// Register : PWM_CH1_DIV -// Description : INT and FRAC form a fixed-point fractional number. -// Counting rate is system clock frequency divided by this number. -// Fractional division uses simple 1st-order sigma-delta. -#define PWM_CH1_DIV_OFFSET _u(0x00000018) -#define PWM_CH1_DIV_BITS _u(0x00000fff) -#define PWM_CH1_DIV_RESET _u(0x00000010) -// ----------------------------------------------------------------------------- -// Field : PWM_CH1_DIV_INT -#define PWM_CH1_DIV_INT_RESET _u(0x01) -#define PWM_CH1_DIV_INT_BITS _u(0x00000ff0) -#define PWM_CH1_DIV_INT_MSB _u(11) -#define PWM_CH1_DIV_INT_LSB _u(4) -#define PWM_CH1_DIV_INT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_CH1_DIV_FRAC -#define PWM_CH1_DIV_FRAC_RESET _u(0x0) -#define PWM_CH1_DIV_FRAC_BITS _u(0x0000000f) -#define PWM_CH1_DIV_FRAC_MSB _u(3) -#define PWM_CH1_DIV_FRAC_LSB _u(0) -#define PWM_CH1_DIV_FRAC_ACCESS "RW" -// ============================================================================= -// Register : PWM_CH1_CTR -// Description : Direct access to the PWM counter -#define PWM_CH1_CTR_OFFSET _u(0x0000001c) -#define PWM_CH1_CTR_BITS _u(0x0000ffff) -#define PWM_CH1_CTR_RESET _u(0x00000000) -#define PWM_CH1_CTR_MSB _u(15) -#define PWM_CH1_CTR_LSB _u(0) -#define PWM_CH1_CTR_ACCESS "RW" -// ============================================================================= -// Register : PWM_CH1_CC -// Description : Counter compare values -#define PWM_CH1_CC_OFFSET _u(0x00000020) -#define PWM_CH1_CC_BITS _u(0xffffffff) -#define PWM_CH1_CC_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : PWM_CH1_CC_B -#define PWM_CH1_CC_B_RESET _u(0x0000) -#define PWM_CH1_CC_B_BITS _u(0xffff0000) -#define PWM_CH1_CC_B_MSB _u(31) -#define PWM_CH1_CC_B_LSB _u(16) -#define PWM_CH1_CC_B_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_CH1_CC_A -#define PWM_CH1_CC_A_RESET _u(0x0000) -#define PWM_CH1_CC_A_BITS _u(0x0000ffff) -#define PWM_CH1_CC_A_MSB _u(15) -#define PWM_CH1_CC_A_LSB _u(0) -#define PWM_CH1_CC_A_ACCESS "RW" -// ============================================================================= -// Register : PWM_CH1_TOP -// Description : Counter wrap value -#define PWM_CH1_TOP_OFFSET _u(0x00000024) -#define PWM_CH1_TOP_BITS _u(0x0000ffff) -#define PWM_CH1_TOP_RESET _u(0x0000ffff) -#define PWM_CH1_TOP_MSB _u(15) -#define PWM_CH1_TOP_LSB _u(0) -#define PWM_CH1_TOP_ACCESS "RW" -// ============================================================================= -// Register : PWM_CH2_CSR -// Description : Control and status register -#define PWM_CH2_CSR_OFFSET _u(0x00000028) -#define PWM_CH2_CSR_BITS _u(0x000000ff) -#define PWM_CH2_CSR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : PWM_CH2_CSR_PH_ADV -// Description : Advance the phase of the counter by 1 count, while it is -// running. -// Self-clearing. Write a 1, and poll until low. Counter must be -// running -// at less than full speed (div_int + div_frac / 16 > 1) -#define PWM_CH2_CSR_PH_ADV_RESET _u(0x0) -#define PWM_CH2_CSR_PH_ADV_BITS _u(0x00000080) -#define PWM_CH2_CSR_PH_ADV_MSB _u(7) -#define PWM_CH2_CSR_PH_ADV_LSB _u(7) -#define PWM_CH2_CSR_PH_ADV_ACCESS "SC" -// ----------------------------------------------------------------------------- -// Field : PWM_CH2_CSR_PH_RET -// Description : Retard the phase of the counter by 1 count, while it is -// running. -// Self-clearing. Write a 1, and poll until low. Counter must be -// running. -#define PWM_CH2_CSR_PH_RET_RESET _u(0x0) -#define PWM_CH2_CSR_PH_RET_BITS _u(0x00000040) -#define PWM_CH2_CSR_PH_RET_MSB _u(6) -#define PWM_CH2_CSR_PH_RET_LSB _u(6) -#define PWM_CH2_CSR_PH_RET_ACCESS "SC" -// ----------------------------------------------------------------------------- -// Field : PWM_CH2_CSR_DIVMODE -// 0x0 -> Free-running counting at rate dictated by fractional divider -// 0x1 -> Fractional divider operation is gated by the PWM B pin. -// 0x2 -> Counter advances with each rising edge of the PWM B pin. -// 0x3 -> Counter advances with each falling edge of the PWM B pin. -#define PWM_CH2_CSR_DIVMODE_RESET _u(0x0) -#define PWM_CH2_CSR_DIVMODE_BITS _u(0x00000030) -#define PWM_CH2_CSR_DIVMODE_MSB _u(5) -#define PWM_CH2_CSR_DIVMODE_LSB _u(4) -#define PWM_CH2_CSR_DIVMODE_ACCESS "RW" -#define PWM_CH2_CSR_DIVMODE_VALUE_DIV _u(0x0) -#define PWM_CH2_CSR_DIVMODE_VALUE_LEVEL _u(0x1) -#define PWM_CH2_CSR_DIVMODE_VALUE_RISE _u(0x2) -#define PWM_CH2_CSR_DIVMODE_VALUE_FALL _u(0x3) -// ----------------------------------------------------------------------------- -// Field : PWM_CH2_CSR_B_INV -// Description : Invert output B -#define PWM_CH2_CSR_B_INV_RESET _u(0x0) -#define PWM_CH2_CSR_B_INV_BITS _u(0x00000008) -#define PWM_CH2_CSR_B_INV_MSB _u(3) -#define PWM_CH2_CSR_B_INV_LSB _u(3) -#define PWM_CH2_CSR_B_INV_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_CH2_CSR_A_INV -// Description : Invert output A -#define PWM_CH2_CSR_A_INV_RESET _u(0x0) -#define PWM_CH2_CSR_A_INV_BITS _u(0x00000004) -#define PWM_CH2_CSR_A_INV_MSB _u(2) -#define PWM_CH2_CSR_A_INV_LSB _u(2) -#define PWM_CH2_CSR_A_INV_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_CH2_CSR_PH_CORRECT -// Description : 1: Enable phase-correct modulation. 0: Trailing-edge -#define PWM_CH2_CSR_PH_CORRECT_RESET _u(0x0) -#define PWM_CH2_CSR_PH_CORRECT_BITS _u(0x00000002) -#define PWM_CH2_CSR_PH_CORRECT_MSB _u(1) -#define PWM_CH2_CSR_PH_CORRECT_LSB _u(1) -#define PWM_CH2_CSR_PH_CORRECT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_CH2_CSR_EN -// Description : Enable the PWM channel. -#define PWM_CH2_CSR_EN_RESET _u(0x0) -#define PWM_CH2_CSR_EN_BITS _u(0x00000001) -#define PWM_CH2_CSR_EN_MSB _u(0) -#define PWM_CH2_CSR_EN_LSB _u(0) -#define PWM_CH2_CSR_EN_ACCESS "RW" -// ============================================================================= -// Register : PWM_CH2_DIV -// Description : INT and FRAC form a fixed-point fractional number. -// Counting rate is system clock frequency divided by this number. -// Fractional division uses simple 1st-order sigma-delta. -#define PWM_CH2_DIV_OFFSET _u(0x0000002c) -#define PWM_CH2_DIV_BITS _u(0x00000fff) -#define PWM_CH2_DIV_RESET _u(0x00000010) -// ----------------------------------------------------------------------------- -// Field : PWM_CH2_DIV_INT -#define PWM_CH2_DIV_INT_RESET _u(0x01) -#define PWM_CH2_DIV_INT_BITS _u(0x00000ff0) -#define PWM_CH2_DIV_INT_MSB _u(11) -#define PWM_CH2_DIV_INT_LSB _u(4) -#define PWM_CH2_DIV_INT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_CH2_DIV_FRAC -#define PWM_CH2_DIV_FRAC_RESET _u(0x0) -#define PWM_CH2_DIV_FRAC_BITS _u(0x0000000f) -#define PWM_CH2_DIV_FRAC_MSB _u(3) -#define PWM_CH2_DIV_FRAC_LSB _u(0) -#define PWM_CH2_DIV_FRAC_ACCESS "RW" -// ============================================================================= -// Register : PWM_CH2_CTR -// Description : Direct access to the PWM counter -#define PWM_CH2_CTR_OFFSET _u(0x00000030) -#define PWM_CH2_CTR_BITS _u(0x0000ffff) -#define PWM_CH2_CTR_RESET _u(0x00000000) -#define PWM_CH2_CTR_MSB _u(15) -#define PWM_CH2_CTR_LSB _u(0) -#define PWM_CH2_CTR_ACCESS "RW" -// ============================================================================= -// Register : PWM_CH2_CC -// Description : Counter compare values -#define PWM_CH2_CC_OFFSET _u(0x00000034) -#define PWM_CH2_CC_BITS _u(0xffffffff) -#define PWM_CH2_CC_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : PWM_CH2_CC_B -#define PWM_CH2_CC_B_RESET _u(0x0000) -#define PWM_CH2_CC_B_BITS _u(0xffff0000) -#define PWM_CH2_CC_B_MSB _u(31) -#define PWM_CH2_CC_B_LSB _u(16) -#define PWM_CH2_CC_B_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_CH2_CC_A -#define PWM_CH2_CC_A_RESET _u(0x0000) -#define PWM_CH2_CC_A_BITS _u(0x0000ffff) -#define PWM_CH2_CC_A_MSB _u(15) -#define PWM_CH2_CC_A_LSB _u(0) -#define PWM_CH2_CC_A_ACCESS "RW" -// ============================================================================= -// Register : PWM_CH2_TOP -// Description : Counter wrap value -#define PWM_CH2_TOP_OFFSET _u(0x00000038) -#define PWM_CH2_TOP_BITS _u(0x0000ffff) -#define PWM_CH2_TOP_RESET _u(0x0000ffff) -#define PWM_CH2_TOP_MSB _u(15) -#define PWM_CH2_TOP_LSB _u(0) -#define PWM_CH2_TOP_ACCESS "RW" -// ============================================================================= -// Register : PWM_CH3_CSR -// Description : Control and status register -#define PWM_CH3_CSR_OFFSET _u(0x0000003c) -#define PWM_CH3_CSR_BITS _u(0x000000ff) -#define PWM_CH3_CSR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : PWM_CH3_CSR_PH_ADV -// Description : Advance the phase of the counter by 1 count, while it is -// running. -// Self-clearing. Write a 1, and poll until low. Counter must be -// running -// at less than full speed (div_int + div_frac / 16 > 1) -#define PWM_CH3_CSR_PH_ADV_RESET _u(0x0) -#define PWM_CH3_CSR_PH_ADV_BITS _u(0x00000080) -#define PWM_CH3_CSR_PH_ADV_MSB _u(7) -#define PWM_CH3_CSR_PH_ADV_LSB _u(7) -#define PWM_CH3_CSR_PH_ADV_ACCESS "SC" -// ----------------------------------------------------------------------------- -// Field : PWM_CH3_CSR_PH_RET -// Description : Retard the phase of the counter by 1 count, while it is -// running. -// Self-clearing. Write a 1, and poll until low. Counter must be -// running. -#define PWM_CH3_CSR_PH_RET_RESET _u(0x0) -#define PWM_CH3_CSR_PH_RET_BITS _u(0x00000040) -#define PWM_CH3_CSR_PH_RET_MSB _u(6) -#define PWM_CH3_CSR_PH_RET_LSB _u(6) -#define PWM_CH3_CSR_PH_RET_ACCESS "SC" -// ----------------------------------------------------------------------------- -// Field : PWM_CH3_CSR_DIVMODE -// 0x0 -> Free-running counting at rate dictated by fractional divider -// 0x1 -> Fractional divider operation is gated by the PWM B pin. -// 0x2 -> Counter advances with each rising edge of the PWM B pin. -// 0x3 -> Counter advances with each falling edge of the PWM B pin. -#define PWM_CH3_CSR_DIVMODE_RESET _u(0x0) -#define PWM_CH3_CSR_DIVMODE_BITS _u(0x00000030) -#define PWM_CH3_CSR_DIVMODE_MSB _u(5) -#define PWM_CH3_CSR_DIVMODE_LSB _u(4) -#define PWM_CH3_CSR_DIVMODE_ACCESS "RW" -#define PWM_CH3_CSR_DIVMODE_VALUE_DIV _u(0x0) -#define PWM_CH3_CSR_DIVMODE_VALUE_LEVEL _u(0x1) -#define PWM_CH3_CSR_DIVMODE_VALUE_RISE _u(0x2) -#define PWM_CH3_CSR_DIVMODE_VALUE_FALL _u(0x3) -// ----------------------------------------------------------------------------- -// Field : PWM_CH3_CSR_B_INV -// Description : Invert output B -#define PWM_CH3_CSR_B_INV_RESET _u(0x0) -#define PWM_CH3_CSR_B_INV_BITS _u(0x00000008) -#define PWM_CH3_CSR_B_INV_MSB _u(3) -#define PWM_CH3_CSR_B_INV_LSB _u(3) -#define PWM_CH3_CSR_B_INV_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_CH3_CSR_A_INV -// Description : Invert output A -#define PWM_CH3_CSR_A_INV_RESET _u(0x0) -#define PWM_CH3_CSR_A_INV_BITS _u(0x00000004) -#define PWM_CH3_CSR_A_INV_MSB _u(2) -#define PWM_CH3_CSR_A_INV_LSB _u(2) -#define PWM_CH3_CSR_A_INV_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_CH3_CSR_PH_CORRECT -// Description : 1: Enable phase-correct modulation. 0: Trailing-edge -#define PWM_CH3_CSR_PH_CORRECT_RESET _u(0x0) -#define PWM_CH3_CSR_PH_CORRECT_BITS _u(0x00000002) -#define PWM_CH3_CSR_PH_CORRECT_MSB _u(1) -#define PWM_CH3_CSR_PH_CORRECT_LSB _u(1) -#define PWM_CH3_CSR_PH_CORRECT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_CH3_CSR_EN -// Description : Enable the PWM channel. -#define PWM_CH3_CSR_EN_RESET _u(0x0) -#define PWM_CH3_CSR_EN_BITS _u(0x00000001) -#define PWM_CH3_CSR_EN_MSB _u(0) -#define PWM_CH3_CSR_EN_LSB _u(0) -#define PWM_CH3_CSR_EN_ACCESS "RW" -// ============================================================================= -// Register : PWM_CH3_DIV -// Description : INT and FRAC form a fixed-point fractional number. -// Counting rate is system clock frequency divided by this number. -// Fractional division uses simple 1st-order sigma-delta. -#define PWM_CH3_DIV_OFFSET _u(0x00000040) -#define PWM_CH3_DIV_BITS _u(0x00000fff) -#define PWM_CH3_DIV_RESET _u(0x00000010) -// ----------------------------------------------------------------------------- -// Field : PWM_CH3_DIV_INT -#define PWM_CH3_DIV_INT_RESET _u(0x01) -#define PWM_CH3_DIV_INT_BITS _u(0x00000ff0) -#define PWM_CH3_DIV_INT_MSB _u(11) -#define PWM_CH3_DIV_INT_LSB _u(4) -#define PWM_CH3_DIV_INT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_CH3_DIV_FRAC -#define PWM_CH3_DIV_FRAC_RESET _u(0x0) -#define PWM_CH3_DIV_FRAC_BITS _u(0x0000000f) -#define PWM_CH3_DIV_FRAC_MSB _u(3) -#define PWM_CH3_DIV_FRAC_LSB _u(0) -#define PWM_CH3_DIV_FRAC_ACCESS "RW" -// ============================================================================= -// Register : PWM_CH3_CTR -// Description : Direct access to the PWM counter -#define PWM_CH3_CTR_OFFSET _u(0x00000044) -#define PWM_CH3_CTR_BITS _u(0x0000ffff) -#define PWM_CH3_CTR_RESET _u(0x00000000) -#define PWM_CH3_CTR_MSB _u(15) -#define PWM_CH3_CTR_LSB _u(0) -#define PWM_CH3_CTR_ACCESS "RW" -// ============================================================================= -// Register : PWM_CH3_CC -// Description : Counter compare values -#define PWM_CH3_CC_OFFSET _u(0x00000048) -#define PWM_CH3_CC_BITS _u(0xffffffff) -#define PWM_CH3_CC_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : PWM_CH3_CC_B -#define PWM_CH3_CC_B_RESET _u(0x0000) -#define PWM_CH3_CC_B_BITS _u(0xffff0000) -#define PWM_CH3_CC_B_MSB _u(31) -#define PWM_CH3_CC_B_LSB _u(16) -#define PWM_CH3_CC_B_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_CH3_CC_A -#define PWM_CH3_CC_A_RESET _u(0x0000) -#define PWM_CH3_CC_A_BITS _u(0x0000ffff) -#define PWM_CH3_CC_A_MSB _u(15) -#define PWM_CH3_CC_A_LSB _u(0) -#define PWM_CH3_CC_A_ACCESS "RW" -// ============================================================================= -// Register : PWM_CH3_TOP -// Description : Counter wrap value -#define PWM_CH3_TOP_OFFSET _u(0x0000004c) -#define PWM_CH3_TOP_BITS _u(0x0000ffff) -#define PWM_CH3_TOP_RESET _u(0x0000ffff) -#define PWM_CH3_TOP_MSB _u(15) -#define PWM_CH3_TOP_LSB _u(0) -#define PWM_CH3_TOP_ACCESS "RW" -// ============================================================================= -// Register : PWM_CH4_CSR -// Description : Control and status register -#define PWM_CH4_CSR_OFFSET _u(0x00000050) -#define PWM_CH4_CSR_BITS _u(0x000000ff) -#define PWM_CH4_CSR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : PWM_CH4_CSR_PH_ADV -// Description : Advance the phase of the counter by 1 count, while it is -// running. -// Self-clearing. Write a 1, and poll until low. Counter must be -// running -// at less than full speed (div_int + div_frac / 16 > 1) -#define PWM_CH4_CSR_PH_ADV_RESET _u(0x0) -#define PWM_CH4_CSR_PH_ADV_BITS _u(0x00000080) -#define PWM_CH4_CSR_PH_ADV_MSB _u(7) -#define PWM_CH4_CSR_PH_ADV_LSB _u(7) -#define PWM_CH4_CSR_PH_ADV_ACCESS "SC" -// ----------------------------------------------------------------------------- -// Field : PWM_CH4_CSR_PH_RET -// Description : Retard the phase of the counter by 1 count, while it is -// running. -// Self-clearing. Write a 1, and poll until low. Counter must be -// running. -#define PWM_CH4_CSR_PH_RET_RESET _u(0x0) -#define PWM_CH4_CSR_PH_RET_BITS _u(0x00000040) -#define PWM_CH4_CSR_PH_RET_MSB _u(6) -#define PWM_CH4_CSR_PH_RET_LSB _u(6) -#define PWM_CH4_CSR_PH_RET_ACCESS "SC" -// ----------------------------------------------------------------------------- -// Field : PWM_CH4_CSR_DIVMODE -// 0x0 -> Free-running counting at rate dictated by fractional divider -// 0x1 -> Fractional divider operation is gated by the PWM B pin. -// 0x2 -> Counter advances with each rising edge of the PWM B pin. -// 0x3 -> Counter advances with each falling edge of the PWM B pin. -#define PWM_CH4_CSR_DIVMODE_RESET _u(0x0) -#define PWM_CH4_CSR_DIVMODE_BITS _u(0x00000030) -#define PWM_CH4_CSR_DIVMODE_MSB _u(5) -#define PWM_CH4_CSR_DIVMODE_LSB _u(4) -#define PWM_CH4_CSR_DIVMODE_ACCESS "RW" -#define PWM_CH4_CSR_DIVMODE_VALUE_DIV _u(0x0) -#define PWM_CH4_CSR_DIVMODE_VALUE_LEVEL _u(0x1) -#define PWM_CH4_CSR_DIVMODE_VALUE_RISE _u(0x2) -#define PWM_CH4_CSR_DIVMODE_VALUE_FALL _u(0x3) -// ----------------------------------------------------------------------------- -// Field : PWM_CH4_CSR_B_INV -// Description : Invert output B -#define PWM_CH4_CSR_B_INV_RESET _u(0x0) -#define PWM_CH4_CSR_B_INV_BITS _u(0x00000008) -#define PWM_CH4_CSR_B_INV_MSB _u(3) -#define PWM_CH4_CSR_B_INV_LSB _u(3) -#define PWM_CH4_CSR_B_INV_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_CH4_CSR_A_INV -// Description : Invert output A -#define PWM_CH4_CSR_A_INV_RESET _u(0x0) -#define PWM_CH4_CSR_A_INV_BITS _u(0x00000004) -#define PWM_CH4_CSR_A_INV_MSB _u(2) -#define PWM_CH4_CSR_A_INV_LSB _u(2) -#define PWM_CH4_CSR_A_INV_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_CH4_CSR_PH_CORRECT -// Description : 1: Enable phase-correct modulation. 0: Trailing-edge -#define PWM_CH4_CSR_PH_CORRECT_RESET _u(0x0) -#define PWM_CH4_CSR_PH_CORRECT_BITS _u(0x00000002) -#define PWM_CH4_CSR_PH_CORRECT_MSB _u(1) -#define PWM_CH4_CSR_PH_CORRECT_LSB _u(1) -#define PWM_CH4_CSR_PH_CORRECT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_CH4_CSR_EN -// Description : Enable the PWM channel. -#define PWM_CH4_CSR_EN_RESET _u(0x0) -#define PWM_CH4_CSR_EN_BITS _u(0x00000001) -#define PWM_CH4_CSR_EN_MSB _u(0) -#define PWM_CH4_CSR_EN_LSB _u(0) -#define PWM_CH4_CSR_EN_ACCESS "RW" -// ============================================================================= -// Register : PWM_CH4_DIV -// Description : INT and FRAC form a fixed-point fractional number. -// Counting rate is system clock frequency divided by this number. -// Fractional division uses simple 1st-order sigma-delta. -#define PWM_CH4_DIV_OFFSET _u(0x00000054) -#define PWM_CH4_DIV_BITS _u(0x00000fff) -#define PWM_CH4_DIV_RESET _u(0x00000010) -// ----------------------------------------------------------------------------- -// Field : PWM_CH4_DIV_INT -#define PWM_CH4_DIV_INT_RESET _u(0x01) -#define PWM_CH4_DIV_INT_BITS _u(0x00000ff0) -#define PWM_CH4_DIV_INT_MSB _u(11) -#define PWM_CH4_DIV_INT_LSB _u(4) -#define PWM_CH4_DIV_INT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_CH4_DIV_FRAC -#define PWM_CH4_DIV_FRAC_RESET _u(0x0) -#define PWM_CH4_DIV_FRAC_BITS _u(0x0000000f) -#define PWM_CH4_DIV_FRAC_MSB _u(3) -#define PWM_CH4_DIV_FRAC_LSB _u(0) -#define PWM_CH4_DIV_FRAC_ACCESS "RW" -// ============================================================================= -// Register : PWM_CH4_CTR -// Description : Direct access to the PWM counter -#define PWM_CH4_CTR_OFFSET _u(0x00000058) -#define PWM_CH4_CTR_BITS _u(0x0000ffff) -#define PWM_CH4_CTR_RESET _u(0x00000000) -#define PWM_CH4_CTR_MSB _u(15) -#define PWM_CH4_CTR_LSB _u(0) -#define PWM_CH4_CTR_ACCESS "RW" -// ============================================================================= -// Register : PWM_CH4_CC -// Description : Counter compare values -#define PWM_CH4_CC_OFFSET _u(0x0000005c) -#define PWM_CH4_CC_BITS _u(0xffffffff) -#define PWM_CH4_CC_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : PWM_CH4_CC_B -#define PWM_CH4_CC_B_RESET _u(0x0000) -#define PWM_CH4_CC_B_BITS _u(0xffff0000) -#define PWM_CH4_CC_B_MSB _u(31) -#define PWM_CH4_CC_B_LSB _u(16) -#define PWM_CH4_CC_B_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_CH4_CC_A -#define PWM_CH4_CC_A_RESET _u(0x0000) -#define PWM_CH4_CC_A_BITS _u(0x0000ffff) -#define PWM_CH4_CC_A_MSB _u(15) -#define PWM_CH4_CC_A_LSB _u(0) -#define PWM_CH4_CC_A_ACCESS "RW" -// ============================================================================= -// Register : PWM_CH4_TOP -// Description : Counter wrap value -#define PWM_CH4_TOP_OFFSET _u(0x00000060) -#define PWM_CH4_TOP_BITS _u(0x0000ffff) -#define PWM_CH4_TOP_RESET _u(0x0000ffff) -#define PWM_CH4_TOP_MSB _u(15) -#define PWM_CH4_TOP_LSB _u(0) -#define PWM_CH4_TOP_ACCESS "RW" -// ============================================================================= -// Register : PWM_CH5_CSR -// Description : Control and status register -#define PWM_CH5_CSR_OFFSET _u(0x00000064) -#define PWM_CH5_CSR_BITS _u(0x000000ff) -#define PWM_CH5_CSR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : PWM_CH5_CSR_PH_ADV -// Description : Advance the phase of the counter by 1 count, while it is -// running. -// Self-clearing. Write a 1, and poll until low. Counter must be -// running -// at less than full speed (div_int + div_frac / 16 > 1) -#define PWM_CH5_CSR_PH_ADV_RESET _u(0x0) -#define PWM_CH5_CSR_PH_ADV_BITS _u(0x00000080) -#define PWM_CH5_CSR_PH_ADV_MSB _u(7) -#define PWM_CH5_CSR_PH_ADV_LSB _u(7) -#define PWM_CH5_CSR_PH_ADV_ACCESS "SC" -// ----------------------------------------------------------------------------- -// Field : PWM_CH5_CSR_PH_RET -// Description : Retard the phase of the counter by 1 count, while it is -// running. -// Self-clearing. Write a 1, and poll until low. Counter must be -// running. -#define PWM_CH5_CSR_PH_RET_RESET _u(0x0) -#define PWM_CH5_CSR_PH_RET_BITS _u(0x00000040) -#define PWM_CH5_CSR_PH_RET_MSB _u(6) -#define PWM_CH5_CSR_PH_RET_LSB _u(6) -#define PWM_CH5_CSR_PH_RET_ACCESS "SC" -// ----------------------------------------------------------------------------- -// Field : PWM_CH5_CSR_DIVMODE -// 0x0 -> Free-running counting at rate dictated by fractional divider -// 0x1 -> Fractional divider operation is gated by the PWM B pin. -// 0x2 -> Counter advances with each rising edge of the PWM B pin. -// 0x3 -> Counter advances with each falling edge of the PWM B pin. -#define PWM_CH5_CSR_DIVMODE_RESET _u(0x0) -#define PWM_CH5_CSR_DIVMODE_BITS _u(0x00000030) -#define PWM_CH5_CSR_DIVMODE_MSB _u(5) -#define PWM_CH5_CSR_DIVMODE_LSB _u(4) -#define PWM_CH5_CSR_DIVMODE_ACCESS "RW" -#define PWM_CH5_CSR_DIVMODE_VALUE_DIV _u(0x0) -#define PWM_CH5_CSR_DIVMODE_VALUE_LEVEL _u(0x1) -#define PWM_CH5_CSR_DIVMODE_VALUE_RISE _u(0x2) -#define PWM_CH5_CSR_DIVMODE_VALUE_FALL _u(0x3) -// ----------------------------------------------------------------------------- -// Field : PWM_CH5_CSR_B_INV -// Description : Invert output B -#define PWM_CH5_CSR_B_INV_RESET _u(0x0) -#define PWM_CH5_CSR_B_INV_BITS _u(0x00000008) -#define PWM_CH5_CSR_B_INV_MSB _u(3) -#define PWM_CH5_CSR_B_INV_LSB _u(3) -#define PWM_CH5_CSR_B_INV_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_CH5_CSR_A_INV -// Description : Invert output A -#define PWM_CH5_CSR_A_INV_RESET _u(0x0) -#define PWM_CH5_CSR_A_INV_BITS _u(0x00000004) -#define PWM_CH5_CSR_A_INV_MSB _u(2) -#define PWM_CH5_CSR_A_INV_LSB _u(2) -#define PWM_CH5_CSR_A_INV_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_CH5_CSR_PH_CORRECT -// Description : 1: Enable phase-correct modulation. 0: Trailing-edge -#define PWM_CH5_CSR_PH_CORRECT_RESET _u(0x0) -#define PWM_CH5_CSR_PH_CORRECT_BITS _u(0x00000002) -#define PWM_CH5_CSR_PH_CORRECT_MSB _u(1) -#define PWM_CH5_CSR_PH_CORRECT_LSB _u(1) -#define PWM_CH5_CSR_PH_CORRECT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_CH5_CSR_EN -// Description : Enable the PWM channel. -#define PWM_CH5_CSR_EN_RESET _u(0x0) -#define PWM_CH5_CSR_EN_BITS _u(0x00000001) -#define PWM_CH5_CSR_EN_MSB _u(0) -#define PWM_CH5_CSR_EN_LSB _u(0) -#define PWM_CH5_CSR_EN_ACCESS "RW" -// ============================================================================= -// Register : PWM_CH5_DIV -// Description : INT and FRAC form a fixed-point fractional number. -// Counting rate is system clock frequency divided by this number. -// Fractional division uses simple 1st-order sigma-delta. -#define PWM_CH5_DIV_OFFSET _u(0x00000068) -#define PWM_CH5_DIV_BITS _u(0x00000fff) -#define PWM_CH5_DIV_RESET _u(0x00000010) -// ----------------------------------------------------------------------------- -// Field : PWM_CH5_DIV_INT -#define PWM_CH5_DIV_INT_RESET _u(0x01) -#define PWM_CH5_DIV_INT_BITS _u(0x00000ff0) -#define PWM_CH5_DIV_INT_MSB _u(11) -#define PWM_CH5_DIV_INT_LSB _u(4) -#define PWM_CH5_DIV_INT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_CH5_DIV_FRAC -#define PWM_CH5_DIV_FRAC_RESET _u(0x0) -#define PWM_CH5_DIV_FRAC_BITS _u(0x0000000f) -#define PWM_CH5_DIV_FRAC_MSB _u(3) -#define PWM_CH5_DIV_FRAC_LSB _u(0) -#define PWM_CH5_DIV_FRAC_ACCESS "RW" -// ============================================================================= -// Register : PWM_CH5_CTR -// Description : Direct access to the PWM counter -#define PWM_CH5_CTR_OFFSET _u(0x0000006c) -#define PWM_CH5_CTR_BITS _u(0x0000ffff) -#define PWM_CH5_CTR_RESET _u(0x00000000) -#define PWM_CH5_CTR_MSB _u(15) -#define PWM_CH5_CTR_LSB _u(0) -#define PWM_CH5_CTR_ACCESS "RW" -// ============================================================================= -// Register : PWM_CH5_CC -// Description : Counter compare values -#define PWM_CH5_CC_OFFSET _u(0x00000070) -#define PWM_CH5_CC_BITS _u(0xffffffff) -#define PWM_CH5_CC_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : PWM_CH5_CC_B -#define PWM_CH5_CC_B_RESET _u(0x0000) -#define PWM_CH5_CC_B_BITS _u(0xffff0000) -#define PWM_CH5_CC_B_MSB _u(31) -#define PWM_CH5_CC_B_LSB _u(16) -#define PWM_CH5_CC_B_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_CH5_CC_A -#define PWM_CH5_CC_A_RESET _u(0x0000) -#define PWM_CH5_CC_A_BITS _u(0x0000ffff) -#define PWM_CH5_CC_A_MSB _u(15) -#define PWM_CH5_CC_A_LSB _u(0) -#define PWM_CH5_CC_A_ACCESS "RW" -// ============================================================================= -// Register : PWM_CH5_TOP -// Description : Counter wrap value -#define PWM_CH5_TOP_OFFSET _u(0x00000074) -#define PWM_CH5_TOP_BITS _u(0x0000ffff) -#define PWM_CH5_TOP_RESET _u(0x0000ffff) -#define PWM_CH5_TOP_MSB _u(15) -#define PWM_CH5_TOP_LSB _u(0) -#define PWM_CH5_TOP_ACCESS "RW" -// ============================================================================= -// Register : PWM_CH6_CSR -// Description : Control and status register -#define PWM_CH6_CSR_OFFSET _u(0x00000078) -#define PWM_CH6_CSR_BITS _u(0x000000ff) -#define PWM_CH6_CSR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : PWM_CH6_CSR_PH_ADV -// Description : Advance the phase of the counter by 1 count, while it is -// running. -// Self-clearing. Write a 1, and poll until low. Counter must be -// running -// at less than full speed (div_int + div_frac / 16 > 1) -#define PWM_CH6_CSR_PH_ADV_RESET _u(0x0) -#define PWM_CH6_CSR_PH_ADV_BITS _u(0x00000080) -#define PWM_CH6_CSR_PH_ADV_MSB _u(7) -#define PWM_CH6_CSR_PH_ADV_LSB _u(7) -#define PWM_CH6_CSR_PH_ADV_ACCESS "SC" -// ----------------------------------------------------------------------------- -// Field : PWM_CH6_CSR_PH_RET -// Description : Retard the phase of the counter by 1 count, while it is -// running. -// Self-clearing. Write a 1, and poll until low. Counter must be -// running. -#define PWM_CH6_CSR_PH_RET_RESET _u(0x0) -#define PWM_CH6_CSR_PH_RET_BITS _u(0x00000040) -#define PWM_CH6_CSR_PH_RET_MSB _u(6) -#define PWM_CH6_CSR_PH_RET_LSB _u(6) -#define PWM_CH6_CSR_PH_RET_ACCESS "SC" -// ----------------------------------------------------------------------------- -// Field : PWM_CH6_CSR_DIVMODE -// 0x0 -> Free-running counting at rate dictated by fractional divider -// 0x1 -> Fractional divider operation is gated by the PWM B pin. -// 0x2 -> Counter advances with each rising edge of the PWM B pin. -// 0x3 -> Counter advances with each falling edge of the PWM B pin. -#define PWM_CH6_CSR_DIVMODE_RESET _u(0x0) -#define PWM_CH6_CSR_DIVMODE_BITS _u(0x00000030) -#define PWM_CH6_CSR_DIVMODE_MSB _u(5) -#define PWM_CH6_CSR_DIVMODE_LSB _u(4) -#define PWM_CH6_CSR_DIVMODE_ACCESS "RW" -#define PWM_CH6_CSR_DIVMODE_VALUE_DIV _u(0x0) -#define PWM_CH6_CSR_DIVMODE_VALUE_LEVEL _u(0x1) -#define PWM_CH6_CSR_DIVMODE_VALUE_RISE _u(0x2) -#define PWM_CH6_CSR_DIVMODE_VALUE_FALL _u(0x3) -// ----------------------------------------------------------------------------- -// Field : PWM_CH6_CSR_B_INV -// Description : Invert output B -#define PWM_CH6_CSR_B_INV_RESET _u(0x0) -#define PWM_CH6_CSR_B_INV_BITS _u(0x00000008) -#define PWM_CH6_CSR_B_INV_MSB _u(3) -#define PWM_CH6_CSR_B_INV_LSB _u(3) -#define PWM_CH6_CSR_B_INV_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_CH6_CSR_A_INV -// Description : Invert output A -#define PWM_CH6_CSR_A_INV_RESET _u(0x0) -#define PWM_CH6_CSR_A_INV_BITS _u(0x00000004) -#define PWM_CH6_CSR_A_INV_MSB _u(2) -#define PWM_CH6_CSR_A_INV_LSB _u(2) -#define PWM_CH6_CSR_A_INV_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_CH6_CSR_PH_CORRECT -// Description : 1: Enable phase-correct modulation. 0: Trailing-edge -#define PWM_CH6_CSR_PH_CORRECT_RESET _u(0x0) -#define PWM_CH6_CSR_PH_CORRECT_BITS _u(0x00000002) -#define PWM_CH6_CSR_PH_CORRECT_MSB _u(1) -#define PWM_CH6_CSR_PH_CORRECT_LSB _u(1) -#define PWM_CH6_CSR_PH_CORRECT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_CH6_CSR_EN -// Description : Enable the PWM channel. -#define PWM_CH6_CSR_EN_RESET _u(0x0) -#define PWM_CH6_CSR_EN_BITS _u(0x00000001) -#define PWM_CH6_CSR_EN_MSB _u(0) -#define PWM_CH6_CSR_EN_LSB _u(0) -#define PWM_CH6_CSR_EN_ACCESS "RW" -// ============================================================================= -// Register : PWM_CH6_DIV -// Description : INT and FRAC form a fixed-point fractional number. -// Counting rate is system clock frequency divided by this number. -// Fractional division uses simple 1st-order sigma-delta. -#define PWM_CH6_DIV_OFFSET _u(0x0000007c) -#define PWM_CH6_DIV_BITS _u(0x00000fff) -#define PWM_CH6_DIV_RESET _u(0x00000010) -// ----------------------------------------------------------------------------- -// Field : PWM_CH6_DIV_INT -#define PWM_CH6_DIV_INT_RESET _u(0x01) -#define PWM_CH6_DIV_INT_BITS _u(0x00000ff0) -#define PWM_CH6_DIV_INT_MSB _u(11) -#define PWM_CH6_DIV_INT_LSB _u(4) -#define PWM_CH6_DIV_INT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_CH6_DIV_FRAC -#define PWM_CH6_DIV_FRAC_RESET _u(0x0) -#define PWM_CH6_DIV_FRAC_BITS _u(0x0000000f) -#define PWM_CH6_DIV_FRAC_MSB _u(3) -#define PWM_CH6_DIV_FRAC_LSB _u(0) -#define PWM_CH6_DIV_FRAC_ACCESS "RW" -// ============================================================================= -// Register : PWM_CH6_CTR -// Description : Direct access to the PWM counter -#define PWM_CH6_CTR_OFFSET _u(0x00000080) -#define PWM_CH6_CTR_BITS _u(0x0000ffff) -#define PWM_CH6_CTR_RESET _u(0x00000000) -#define PWM_CH6_CTR_MSB _u(15) -#define PWM_CH6_CTR_LSB _u(0) -#define PWM_CH6_CTR_ACCESS "RW" -// ============================================================================= -// Register : PWM_CH6_CC -// Description : Counter compare values -#define PWM_CH6_CC_OFFSET _u(0x00000084) -#define PWM_CH6_CC_BITS _u(0xffffffff) -#define PWM_CH6_CC_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : PWM_CH6_CC_B -#define PWM_CH6_CC_B_RESET _u(0x0000) -#define PWM_CH6_CC_B_BITS _u(0xffff0000) -#define PWM_CH6_CC_B_MSB _u(31) -#define PWM_CH6_CC_B_LSB _u(16) -#define PWM_CH6_CC_B_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_CH6_CC_A -#define PWM_CH6_CC_A_RESET _u(0x0000) -#define PWM_CH6_CC_A_BITS _u(0x0000ffff) -#define PWM_CH6_CC_A_MSB _u(15) -#define PWM_CH6_CC_A_LSB _u(0) -#define PWM_CH6_CC_A_ACCESS "RW" -// ============================================================================= -// Register : PWM_CH6_TOP -// Description : Counter wrap value -#define PWM_CH6_TOP_OFFSET _u(0x00000088) -#define PWM_CH6_TOP_BITS _u(0x0000ffff) -#define PWM_CH6_TOP_RESET _u(0x0000ffff) -#define PWM_CH6_TOP_MSB _u(15) -#define PWM_CH6_TOP_LSB _u(0) -#define PWM_CH6_TOP_ACCESS "RW" -// ============================================================================= -// Register : PWM_CH7_CSR -// Description : Control and status register -#define PWM_CH7_CSR_OFFSET _u(0x0000008c) -#define PWM_CH7_CSR_BITS _u(0x000000ff) -#define PWM_CH7_CSR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : PWM_CH7_CSR_PH_ADV -// Description : Advance the phase of the counter by 1 count, while it is -// running. -// Self-clearing. Write a 1, and poll until low. Counter must be -// running -// at less than full speed (div_int + div_frac / 16 > 1) -#define PWM_CH7_CSR_PH_ADV_RESET _u(0x0) -#define PWM_CH7_CSR_PH_ADV_BITS _u(0x00000080) -#define PWM_CH7_CSR_PH_ADV_MSB _u(7) -#define PWM_CH7_CSR_PH_ADV_LSB _u(7) -#define PWM_CH7_CSR_PH_ADV_ACCESS "SC" -// ----------------------------------------------------------------------------- -// Field : PWM_CH7_CSR_PH_RET -// Description : Retard the phase of the counter by 1 count, while it is -// running. -// Self-clearing. Write a 1, and poll until low. Counter must be -// running. -#define PWM_CH7_CSR_PH_RET_RESET _u(0x0) -#define PWM_CH7_CSR_PH_RET_BITS _u(0x00000040) -#define PWM_CH7_CSR_PH_RET_MSB _u(6) -#define PWM_CH7_CSR_PH_RET_LSB _u(6) -#define PWM_CH7_CSR_PH_RET_ACCESS "SC" -// ----------------------------------------------------------------------------- -// Field : PWM_CH7_CSR_DIVMODE -// 0x0 -> Free-running counting at rate dictated by fractional divider -// 0x1 -> Fractional divider operation is gated by the PWM B pin. -// 0x2 -> Counter advances with each rising edge of the PWM B pin. -// 0x3 -> Counter advances with each falling edge of the PWM B pin. -#define PWM_CH7_CSR_DIVMODE_RESET _u(0x0) -#define PWM_CH7_CSR_DIVMODE_BITS _u(0x00000030) -#define PWM_CH7_CSR_DIVMODE_MSB _u(5) -#define PWM_CH7_CSR_DIVMODE_LSB _u(4) -#define PWM_CH7_CSR_DIVMODE_ACCESS "RW" -#define PWM_CH7_CSR_DIVMODE_VALUE_DIV _u(0x0) -#define PWM_CH7_CSR_DIVMODE_VALUE_LEVEL _u(0x1) -#define PWM_CH7_CSR_DIVMODE_VALUE_RISE _u(0x2) -#define PWM_CH7_CSR_DIVMODE_VALUE_FALL _u(0x3) -// ----------------------------------------------------------------------------- -// Field : PWM_CH7_CSR_B_INV -// Description : Invert output B -#define PWM_CH7_CSR_B_INV_RESET _u(0x0) -#define PWM_CH7_CSR_B_INV_BITS _u(0x00000008) -#define PWM_CH7_CSR_B_INV_MSB _u(3) -#define PWM_CH7_CSR_B_INV_LSB _u(3) -#define PWM_CH7_CSR_B_INV_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_CH7_CSR_A_INV -// Description : Invert output A -#define PWM_CH7_CSR_A_INV_RESET _u(0x0) -#define PWM_CH7_CSR_A_INV_BITS _u(0x00000004) -#define PWM_CH7_CSR_A_INV_MSB _u(2) -#define PWM_CH7_CSR_A_INV_LSB _u(2) -#define PWM_CH7_CSR_A_INV_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_CH7_CSR_PH_CORRECT -// Description : 1: Enable phase-correct modulation. 0: Trailing-edge -#define PWM_CH7_CSR_PH_CORRECT_RESET _u(0x0) -#define PWM_CH7_CSR_PH_CORRECT_BITS _u(0x00000002) -#define PWM_CH7_CSR_PH_CORRECT_MSB _u(1) -#define PWM_CH7_CSR_PH_CORRECT_LSB _u(1) -#define PWM_CH7_CSR_PH_CORRECT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_CH7_CSR_EN -// Description : Enable the PWM channel. -#define PWM_CH7_CSR_EN_RESET _u(0x0) -#define PWM_CH7_CSR_EN_BITS _u(0x00000001) -#define PWM_CH7_CSR_EN_MSB _u(0) -#define PWM_CH7_CSR_EN_LSB _u(0) -#define PWM_CH7_CSR_EN_ACCESS "RW" -// ============================================================================= -// Register : PWM_CH7_DIV -// Description : INT and FRAC form a fixed-point fractional number. -// Counting rate is system clock frequency divided by this number. -// Fractional division uses simple 1st-order sigma-delta. -#define PWM_CH7_DIV_OFFSET _u(0x00000090) -#define PWM_CH7_DIV_BITS _u(0x00000fff) -#define PWM_CH7_DIV_RESET _u(0x00000010) -// ----------------------------------------------------------------------------- -// Field : PWM_CH7_DIV_INT -#define PWM_CH7_DIV_INT_RESET _u(0x01) -#define PWM_CH7_DIV_INT_BITS _u(0x00000ff0) -#define PWM_CH7_DIV_INT_MSB _u(11) -#define PWM_CH7_DIV_INT_LSB _u(4) -#define PWM_CH7_DIV_INT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_CH7_DIV_FRAC -#define PWM_CH7_DIV_FRAC_RESET _u(0x0) -#define PWM_CH7_DIV_FRAC_BITS _u(0x0000000f) -#define PWM_CH7_DIV_FRAC_MSB _u(3) -#define PWM_CH7_DIV_FRAC_LSB _u(0) -#define PWM_CH7_DIV_FRAC_ACCESS "RW" -// ============================================================================= -// Register : PWM_CH7_CTR -// Description : Direct access to the PWM counter -#define PWM_CH7_CTR_OFFSET _u(0x00000094) -#define PWM_CH7_CTR_BITS _u(0x0000ffff) -#define PWM_CH7_CTR_RESET _u(0x00000000) -#define PWM_CH7_CTR_MSB _u(15) -#define PWM_CH7_CTR_LSB _u(0) -#define PWM_CH7_CTR_ACCESS "RW" -// ============================================================================= -// Register : PWM_CH7_CC -// Description : Counter compare values -#define PWM_CH7_CC_OFFSET _u(0x00000098) -#define PWM_CH7_CC_BITS _u(0xffffffff) -#define PWM_CH7_CC_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : PWM_CH7_CC_B -#define PWM_CH7_CC_B_RESET _u(0x0000) -#define PWM_CH7_CC_B_BITS _u(0xffff0000) -#define PWM_CH7_CC_B_MSB _u(31) -#define PWM_CH7_CC_B_LSB _u(16) -#define PWM_CH7_CC_B_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_CH7_CC_A -#define PWM_CH7_CC_A_RESET _u(0x0000) -#define PWM_CH7_CC_A_BITS _u(0x0000ffff) -#define PWM_CH7_CC_A_MSB _u(15) -#define PWM_CH7_CC_A_LSB _u(0) -#define PWM_CH7_CC_A_ACCESS "RW" -// ============================================================================= -// Register : PWM_CH7_TOP -// Description : Counter wrap value -#define PWM_CH7_TOP_OFFSET _u(0x0000009c) -#define PWM_CH7_TOP_BITS _u(0x0000ffff) -#define PWM_CH7_TOP_RESET _u(0x0000ffff) -#define PWM_CH7_TOP_MSB _u(15) -#define PWM_CH7_TOP_LSB _u(0) -#define PWM_CH7_TOP_ACCESS "RW" -// ============================================================================= -// Register : PWM_EN -// Description : This register aliases the CSR_EN bits for all channels. -// Writing to this register allows multiple channels to be enabled -// or disabled simultaneously, so they can run in perfect sync. -// For each channel, there is only one physical EN register bit, -// which can be accessed through here or CHx_CSR. -#define PWM_EN_OFFSET _u(0x000000a0) -#define PWM_EN_BITS _u(0x000000ff) -#define PWM_EN_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : PWM_EN_CH7 -#define PWM_EN_CH7_RESET _u(0x0) -#define PWM_EN_CH7_BITS _u(0x00000080) -#define PWM_EN_CH7_MSB _u(7) -#define PWM_EN_CH7_LSB _u(7) -#define PWM_EN_CH7_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_EN_CH6 -#define PWM_EN_CH6_RESET _u(0x0) -#define PWM_EN_CH6_BITS _u(0x00000040) -#define PWM_EN_CH6_MSB _u(6) -#define PWM_EN_CH6_LSB _u(6) -#define PWM_EN_CH6_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_EN_CH5 -#define PWM_EN_CH5_RESET _u(0x0) -#define PWM_EN_CH5_BITS _u(0x00000020) -#define PWM_EN_CH5_MSB _u(5) -#define PWM_EN_CH5_LSB _u(5) -#define PWM_EN_CH5_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_EN_CH4 -#define PWM_EN_CH4_RESET _u(0x0) -#define PWM_EN_CH4_BITS _u(0x00000010) -#define PWM_EN_CH4_MSB _u(4) -#define PWM_EN_CH4_LSB _u(4) -#define PWM_EN_CH4_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_EN_CH3 -#define PWM_EN_CH3_RESET _u(0x0) -#define PWM_EN_CH3_BITS _u(0x00000008) -#define PWM_EN_CH3_MSB _u(3) -#define PWM_EN_CH3_LSB _u(3) -#define PWM_EN_CH3_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_EN_CH2 -#define PWM_EN_CH2_RESET _u(0x0) -#define PWM_EN_CH2_BITS _u(0x00000004) -#define PWM_EN_CH2_MSB _u(2) -#define PWM_EN_CH2_LSB _u(2) -#define PWM_EN_CH2_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_EN_CH1 -#define PWM_EN_CH1_RESET _u(0x0) -#define PWM_EN_CH1_BITS _u(0x00000002) -#define PWM_EN_CH1_MSB _u(1) -#define PWM_EN_CH1_LSB _u(1) -#define PWM_EN_CH1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_EN_CH0 -#define PWM_EN_CH0_RESET _u(0x0) -#define PWM_EN_CH0_BITS _u(0x00000001) -#define PWM_EN_CH0_MSB _u(0) -#define PWM_EN_CH0_LSB _u(0) -#define PWM_EN_CH0_ACCESS "RW" -// ============================================================================= -// Register : PWM_INTR -// Description : Raw Interrupts -#define PWM_INTR_OFFSET _u(0x000000a4) -#define PWM_INTR_BITS _u(0x000000ff) -#define PWM_INTR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : PWM_INTR_CH7 -#define PWM_INTR_CH7_RESET _u(0x0) -#define PWM_INTR_CH7_BITS _u(0x00000080) -#define PWM_INTR_CH7_MSB _u(7) -#define PWM_INTR_CH7_LSB _u(7) -#define PWM_INTR_CH7_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : PWM_INTR_CH6 -#define PWM_INTR_CH6_RESET _u(0x0) -#define PWM_INTR_CH6_BITS _u(0x00000040) -#define PWM_INTR_CH6_MSB _u(6) -#define PWM_INTR_CH6_LSB _u(6) -#define PWM_INTR_CH6_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : PWM_INTR_CH5 -#define PWM_INTR_CH5_RESET _u(0x0) -#define PWM_INTR_CH5_BITS _u(0x00000020) -#define PWM_INTR_CH5_MSB _u(5) -#define PWM_INTR_CH5_LSB _u(5) -#define PWM_INTR_CH5_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : PWM_INTR_CH4 -#define PWM_INTR_CH4_RESET _u(0x0) -#define PWM_INTR_CH4_BITS _u(0x00000010) -#define PWM_INTR_CH4_MSB _u(4) -#define PWM_INTR_CH4_LSB _u(4) -#define PWM_INTR_CH4_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : PWM_INTR_CH3 -#define PWM_INTR_CH3_RESET _u(0x0) -#define PWM_INTR_CH3_BITS _u(0x00000008) -#define PWM_INTR_CH3_MSB _u(3) -#define PWM_INTR_CH3_LSB _u(3) -#define PWM_INTR_CH3_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : PWM_INTR_CH2 -#define PWM_INTR_CH2_RESET _u(0x0) -#define PWM_INTR_CH2_BITS _u(0x00000004) -#define PWM_INTR_CH2_MSB _u(2) -#define PWM_INTR_CH2_LSB _u(2) -#define PWM_INTR_CH2_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : PWM_INTR_CH1 -#define PWM_INTR_CH1_RESET _u(0x0) -#define PWM_INTR_CH1_BITS _u(0x00000002) -#define PWM_INTR_CH1_MSB _u(1) -#define PWM_INTR_CH1_LSB _u(1) -#define PWM_INTR_CH1_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : PWM_INTR_CH0 -#define PWM_INTR_CH0_RESET _u(0x0) -#define PWM_INTR_CH0_BITS _u(0x00000001) -#define PWM_INTR_CH0_MSB _u(0) -#define PWM_INTR_CH0_LSB _u(0) -#define PWM_INTR_CH0_ACCESS "WC" -// ============================================================================= -// Register : PWM_INTE -// Description : Interrupt Enable -#define PWM_INTE_OFFSET _u(0x000000a8) -#define PWM_INTE_BITS _u(0x000000ff) -#define PWM_INTE_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : PWM_INTE_CH7 -#define PWM_INTE_CH7_RESET _u(0x0) -#define PWM_INTE_CH7_BITS _u(0x00000080) -#define PWM_INTE_CH7_MSB _u(7) -#define PWM_INTE_CH7_LSB _u(7) -#define PWM_INTE_CH7_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_INTE_CH6 -#define PWM_INTE_CH6_RESET _u(0x0) -#define PWM_INTE_CH6_BITS _u(0x00000040) -#define PWM_INTE_CH6_MSB _u(6) -#define PWM_INTE_CH6_LSB _u(6) -#define PWM_INTE_CH6_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_INTE_CH5 -#define PWM_INTE_CH5_RESET _u(0x0) -#define PWM_INTE_CH5_BITS _u(0x00000020) -#define PWM_INTE_CH5_MSB _u(5) -#define PWM_INTE_CH5_LSB _u(5) -#define PWM_INTE_CH5_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_INTE_CH4 -#define PWM_INTE_CH4_RESET _u(0x0) -#define PWM_INTE_CH4_BITS _u(0x00000010) -#define PWM_INTE_CH4_MSB _u(4) -#define PWM_INTE_CH4_LSB _u(4) -#define PWM_INTE_CH4_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_INTE_CH3 -#define PWM_INTE_CH3_RESET _u(0x0) -#define PWM_INTE_CH3_BITS _u(0x00000008) -#define PWM_INTE_CH3_MSB _u(3) -#define PWM_INTE_CH3_LSB _u(3) -#define PWM_INTE_CH3_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_INTE_CH2 -#define PWM_INTE_CH2_RESET _u(0x0) -#define PWM_INTE_CH2_BITS _u(0x00000004) -#define PWM_INTE_CH2_MSB _u(2) -#define PWM_INTE_CH2_LSB _u(2) -#define PWM_INTE_CH2_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_INTE_CH1 -#define PWM_INTE_CH1_RESET _u(0x0) -#define PWM_INTE_CH1_BITS _u(0x00000002) -#define PWM_INTE_CH1_MSB _u(1) -#define PWM_INTE_CH1_LSB _u(1) -#define PWM_INTE_CH1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_INTE_CH0 -#define PWM_INTE_CH0_RESET _u(0x0) -#define PWM_INTE_CH0_BITS _u(0x00000001) -#define PWM_INTE_CH0_MSB _u(0) -#define PWM_INTE_CH0_LSB _u(0) -#define PWM_INTE_CH0_ACCESS "RW" -// ============================================================================= -// Register : PWM_INTF -// Description : Interrupt Force -#define PWM_INTF_OFFSET _u(0x000000ac) -#define PWM_INTF_BITS _u(0x000000ff) -#define PWM_INTF_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : PWM_INTF_CH7 -#define PWM_INTF_CH7_RESET _u(0x0) -#define PWM_INTF_CH7_BITS _u(0x00000080) -#define PWM_INTF_CH7_MSB _u(7) -#define PWM_INTF_CH7_LSB _u(7) -#define PWM_INTF_CH7_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_INTF_CH6 -#define PWM_INTF_CH6_RESET _u(0x0) -#define PWM_INTF_CH6_BITS _u(0x00000040) -#define PWM_INTF_CH6_MSB _u(6) -#define PWM_INTF_CH6_LSB _u(6) -#define PWM_INTF_CH6_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_INTF_CH5 -#define PWM_INTF_CH5_RESET _u(0x0) -#define PWM_INTF_CH5_BITS _u(0x00000020) -#define PWM_INTF_CH5_MSB _u(5) -#define PWM_INTF_CH5_LSB _u(5) -#define PWM_INTF_CH5_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_INTF_CH4 -#define PWM_INTF_CH4_RESET _u(0x0) -#define PWM_INTF_CH4_BITS _u(0x00000010) -#define PWM_INTF_CH4_MSB _u(4) -#define PWM_INTF_CH4_LSB _u(4) -#define PWM_INTF_CH4_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_INTF_CH3 -#define PWM_INTF_CH3_RESET _u(0x0) -#define PWM_INTF_CH3_BITS _u(0x00000008) -#define PWM_INTF_CH3_MSB _u(3) -#define PWM_INTF_CH3_LSB _u(3) -#define PWM_INTF_CH3_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_INTF_CH2 -#define PWM_INTF_CH2_RESET _u(0x0) -#define PWM_INTF_CH2_BITS _u(0x00000004) -#define PWM_INTF_CH2_MSB _u(2) -#define PWM_INTF_CH2_LSB _u(2) -#define PWM_INTF_CH2_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_INTF_CH1 -#define PWM_INTF_CH1_RESET _u(0x0) -#define PWM_INTF_CH1_BITS _u(0x00000002) -#define PWM_INTF_CH1_MSB _u(1) -#define PWM_INTF_CH1_LSB _u(1) -#define PWM_INTF_CH1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_INTF_CH0 -#define PWM_INTF_CH0_RESET _u(0x0) -#define PWM_INTF_CH0_BITS _u(0x00000001) -#define PWM_INTF_CH0_MSB _u(0) -#define PWM_INTF_CH0_LSB _u(0) -#define PWM_INTF_CH0_ACCESS "RW" -// ============================================================================= -// Register : PWM_INTS -// Description : Interrupt status after masking & forcing -#define PWM_INTS_OFFSET _u(0x000000b0) -#define PWM_INTS_BITS _u(0x000000ff) -#define PWM_INTS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : PWM_INTS_CH7 -#define PWM_INTS_CH7_RESET _u(0x0) -#define PWM_INTS_CH7_BITS _u(0x00000080) -#define PWM_INTS_CH7_MSB _u(7) -#define PWM_INTS_CH7_LSB _u(7) -#define PWM_INTS_CH7_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PWM_INTS_CH6 -#define PWM_INTS_CH6_RESET _u(0x0) -#define PWM_INTS_CH6_BITS _u(0x00000040) -#define PWM_INTS_CH6_MSB _u(6) -#define PWM_INTS_CH6_LSB _u(6) -#define PWM_INTS_CH6_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PWM_INTS_CH5 -#define PWM_INTS_CH5_RESET _u(0x0) -#define PWM_INTS_CH5_BITS _u(0x00000020) -#define PWM_INTS_CH5_MSB _u(5) -#define PWM_INTS_CH5_LSB _u(5) -#define PWM_INTS_CH5_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PWM_INTS_CH4 -#define PWM_INTS_CH4_RESET _u(0x0) -#define PWM_INTS_CH4_BITS _u(0x00000010) -#define PWM_INTS_CH4_MSB _u(4) -#define PWM_INTS_CH4_LSB _u(4) -#define PWM_INTS_CH4_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PWM_INTS_CH3 -#define PWM_INTS_CH3_RESET _u(0x0) -#define PWM_INTS_CH3_BITS _u(0x00000008) -#define PWM_INTS_CH3_MSB _u(3) -#define PWM_INTS_CH3_LSB _u(3) -#define PWM_INTS_CH3_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PWM_INTS_CH2 -#define PWM_INTS_CH2_RESET _u(0x0) -#define PWM_INTS_CH2_BITS _u(0x00000004) -#define PWM_INTS_CH2_MSB _u(2) -#define PWM_INTS_CH2_LSB _u(2) -#define PWM_INTS_CH2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PWM_INTS_CH1 -#define PWM_INTS_CH1_RESET _u(0x0) -#define PWM_INTS_CH1_BITS _u(0x00000002) -#define PWM_INTS_CH1_MSB _u(1) -#define PWM_INTS_CH1_LSB _u(1) -#define PWM_INTS_CH1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PWM_INTS_CH0 -#define PWM_INTS_CH0_RESET _u(0x0) -#define PWM_INTS_CH0_BITS _u(0x00000001) -#define PWM_INTS_CH0_MSB _u(0) -#define PWM_INTS_CH0_LSB _u(0) -#define PWM_INTS_CH0_ACCESS "RO" -// ============================================================================= -#endif // _HARDWARE_REGS_PWM_H - diff --git a/lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/resets.h b/lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/resets.h deleted file mode 100644 index 03a56e75d9..0000000000 --- a/lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/resets.h +++ /dev/null @@ -1,564 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -// ============================================================================= -// Register block : RESETS -// Version : 1 -// Bus type : apb -// ============================================================================= -#ifndef _HARDWARE_REGS_RESETS_H -#define _HARDWARE_REGS_RESETS_H -// ============================================================================= -// Register : RESETS_RESET -// Description : Reset control. If a bit is set it means the peripheral is in -// reset. 0 means the peripheral's reset is deasserted. -#define RESETS_RESET_OFFSET _u(0x00000000) -#define RESETS_RESET_BITS _u(0x01ffffff) -#define RESETS_RESET_RESET _u(0x01ffffff) -// ----------------------------------------------------------------------------- -// Field : RESETS_RESET_USBCTRL -#define RESETS_RESET_USBCTRL_RESET _u(0x1) -#define RESETS_RESET_USBCTRL_BITS _u(0x01000000) -#define RESETS_RESET_USBCTRL_MSB _u(24) -#define RESETS_RESET_USBCTRL_LSB _u(24) -#define RESETS_RESET_USBCTRL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RESETS_RESET_UART1 -#define RESETS_RESET_UART1_RESET _u(0x1) -#define RESETS_RESET_UART1_BITS _u(0x00800000) -#define RESETS_RESET_UART1_MSB _u(23) -#define RESETS_RESET_UART1_LSB _u(23) -#define RESETS_RESET_UART1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RESETS_RESET_UART0 -#define RESETS_RESET_UART0_RESET _u(0x1) -#define RESETS_RESET_UART0_BITS _u(0x00400000) -#define RESETS_RESET_UART0_MSB _u(22) -#define RESETS_RESET_UART0_LSB _u(22) -#define RESETS_RESET_UART0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RESETS_RESET_TIMER -#define RESETS_RESET_TIMER_RESET _u(0x1) -#define RESETS_RESET_TIMER_BITS _u(0x00200000) -#define RESETS_RESET_TIMER_MSB _u(21) -#define RESETS_RESET_TIMER_LSB _u(21) -#define RESETS_RESET_TIMER_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RESETS_RESET_TBMAN -#define RESETS_RESET_TBMAN_RESET _u(0x1) -#define RESETS_RESET_TBMAN_BITS _u(0x00100000) -#define RESETS_RESET_TBMAN_MSB _u(20) -#define RESETS_RESET_TBMAN_LSB _u(20) -#define RESETS_RESET_TBMAN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RESETS_RESET_SYSINFO -#define RESETS_RESET_SYSINFO_RESET _u(0x1) -#define RESETS_RESET_SYSINFO_BITS _u(0x00080000) -#define RESETS_RESET_SYSINFO_MSB _u(19) -#define RESETS_RESET_SYSINFO_LSB _u(19) -#define RESETS_RESET_SYSINFO_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RESETS_RESET_SYSCFG -#define RESETS_RESET_SYSCFG_RESET _u(0x1) -#define RESETS_RESET_SYSCFG_BITS _u(0x00040000) -#define RESETS_RESET_SYSCFG_MSB _u(18) -#define RESETS_RESET_SYSCFG_LSB _u(18) -#define RESETS_RESET_SYSCFG_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RESETS_RESET_SPI1 -#define RESETS_RESET_SPI1_RESET _u(0x1) -#define RESETS_RESET_SPI1_BITS _u(0x00020000) -#define RESETS_RESET_SPI1_MSB _u(17) -#define RESETS_RESET_SPI1_LSB _u(17) -#define RESETS_RESET_SPI1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RESETS_RESET_SPI0 -#define RESETS_RESET_SPI0_RESET _u(0x1) -#define RESETS_RESET_SPI0_BITS _u(0x00010000) -#define RESETS_RESET_SPI0_MSB _u(16) -#define RESETS_RESET_SPI0_LSB _u(16) -#define RESETS_RESET_SPI0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RESETS_RESET_RTC -#define RESETS_RESET_RTC_RESET _u(0x1) -#define RESETS_RESET_RTC_BITS _u(0x00008000) -#define RESETS_RESET_RTC_MSB _u(15) -#define RESETS_RESET_RTC_LSB _u(15) -#define RESETS_RESET_RTC_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RESETS_RESET_PWM -#define RESETS_RESET_PWM_RESET _u(0x1) -#define RESETS_RESET_PWM_BITS _u(0x00004000) -#define RESETS_RESET_PWM_MSB _u(14) -#define RESETS_RESET_PWM_LSB _u(14) -#define RESETS_RESET_PWM_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RESETS_RESET_PLL_USB -#define RESETS_RESET_PLL_USB_RESET _u(0x1) -#define RESETS_RESET_PLL_USB_BITS _u(0x00002000) -#define RESETS_RESET_PLL_USB_MSB _u(13) -#define RESETS_RESET_PLL_USB_LSB _u(13) -#define RESETS_RESET_PLL_USB_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RESETS_RESET_PLL_SYS -#define RESETS_RESET_PLL_SYS_RESET _u(0x1) -#define RESETS_RESET_PLL_SYS_BITS _u(0x00001000) -#define RESETS_RESET_PLL_SYS_MSB _u(12) -#define RESETS_RESET_PLL_SYS_LSB _u(12) -#define RESETS_RESET_PLL_SYS_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RESETS_RESET_PIO1 -#define RESETS_RESET_PIO1_RESET _u(0x1) -#define RESETS_RESET_PIO1_BITS _u(0x00000800) -#define RESETS_RESET_PIO1_MSB _u(11) -#define RESETS_RESET_PIO1_LSB _u(11) -#define RESETS_RESET_PIO1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RESETS_RESET_PIO0 -#define RESETS_RESET_PIO0_RESET _u(0x1) -#define RESETS_RESET_PIO0_BITS _u(0x00000400) -#define RESETS_RESET_PIO0_MSB _u(10) -#define RESETS_RESET_PIO0_LSB _u(10) -#define RESETS_RESET_PIO0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RESETS_RESET_PADS_QSPI -#define RESETS_RESET_PADS_QSPI_RESET _u(0x1) -#define RESETS_RESET_PADS_QSPI_BITS _u(0x00000200) -#define RESETS_RESET_PADS_QSPI_MSB _u(9) -#define RESETS_RESET_PADS_QSPI_LSB _u(9) -#define RESETS_RESET_PADS_QSPI_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RESETS_RESET_PADS_BANK0 -#define RESETS_RESET_PADS_BANK0_RESET _u(0x1) -#define RESETS_RESET_PADS_BANK0_BITS _u(0x00000100) -#define RESETS_RESET_PADS_BANK0_MSB _u(8) -#define RESETS_RESET_PADS_BANK0_LSB _u(8) -#define RESETS_RESET_PADS_BANK0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RESETS_RESET_JTAG -#define RESETS_RESET_JTAG_RESET _u(0x1) -#define RESETS_RESET_JTAG_BITS _u(0x00000080) -#define RESETS_RESET_JTAG_MSB _u(7) -#define RESETS_RESET_JTAG_LSB _u(7) -#define RESETS_RESET_JTAG_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RESETS_RESET_IO_QSPI -#define RESETS_RESET_IO_QSPI_RESET _u(0x1) -#define RESETS_RESET_IO_QSPI_BITS _u(0x00000040) -#define RESETS_RESET_IO_QSPI_MSB _u(6) -#define RESETS_RESET_IO_QSPI_LSB _u(6) -#define RESETS_RESET_IO_QSPI_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RESETS_RESET_IO_BANK0 -#define RESETS_RESET_IO_BANK0_RESET _u(0x1) -#define RESETS_RESET_IO_BANK0_BITS _u(0x00000020) -#define RESETS_RESET_IO_BANK0_MSB _u(5) -#define RESETS_RESET_IO_BANK0_LSB _u(5) -#define RESETS_RESET_IO_BANK0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RESETS_RESET_I2C1 -#define RESETS_RESET_I2C1_RESET _u(0x1) -#define RESETS_RESET_I2C1_BITS _u(0x00000010) -#define RESETS_RESET_I2C1_MSB _u(4) -#define RESETS_RESET_I2C1_LSB _u(4) -#define RESETS_RESET_I2C1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RESETS_RESET_I2C0 -#define RESETS_RESET_I2C0_RESET _u(0x1) -#define RESETS_RESET_I2C0_BITS _u(0x00000008) -#define RESETS_RESET_I2C0_MSB _u(3) -#define RESETS_RESET_I2C0_LSB _u(3) -#define RESETS_RESET_I2C0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RESETS_RESET_DMA -#define RESETS_RESET_DMA_RESET _u(0x1) -#define RESETS_RESET_DMA_BITS _u(0x00000004) -#define RESETS_RESET_DMA_MSB _u(2) -#define RESETS_RESET_DMA_LSB _u(2) -#define RESETS_RESET_DMA_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RESETS_RESET_BUSCTRL -#define RESETS_RESET_BUSCTRL_RESET _u(0x1) -#define RESETS_RESET_BUSCTRL_BITS _u(0x00000002) -#define RESETS_RESET_BUSCTRL_MSB _u(1) -#define RESETS_RESET_BUSCTRL_LSB _u(1) -#define RESETS_RESET_BUSCTRL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RESETS_RESET_ADC -#define RESETS_RESET_ADC_RESET _u(0x1) -#define RESETS_RESET_ADC_BITS _u(0x00000001) -#define RESETS_RESET_ADC_MSB _u(0) -#define RESETS_RESET_ADC_LSB _u(0) -#define RESETS_RESET_ADC_ACCESS "RW" -// ============================================================================= -// Register : RESETS_WDSEL -// Description : Watchdog select. If a bit is set then the watchdog will reset -// this peripheral when the watchdog fires. -#define RESETS_WDSEL_OFFSET _u(0x00000004) -#define RESETS_WDSEL_BITS _u(0x01ffffff) -#define RESETS_WDSEL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : RESETS_WDSEL_USBCTRL -#define RESETS_WDSEL_USBCTRL_RESET _u(0x0) -#define RESETS_WDSEL_USBCTRL_BITS _u(0x01000000) -#define RESETS_WDSEL_USBCTRL_MSB _u(24) -#define RESETS_WDSEL_USBCTRL_LSB _u(24) -#define RESETS_WDSEL_USBCTRL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RESETS_WDSEL_UART1 -#define RESETS_WDSEL_UART1_RESET _u(0x0) -#define RESETS_WDSEL_UART1_BITS _u(0x00800000) -#define RESETS_WDSEL_UART1_MSB _u(23) -#define RESETS_WDSEL_UART1_LSB _u(23) -#define RESETS_WDSEL_UART1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RESETS_WDSEL_UART0 -#define RESETS_WDSEL_UART0_RESET _u(0x0) -#define RESETS_WDSEL_UART0_BITS _u(0x00400000) -#define RESETS_WDSEL_UART0_MSB _u(22) -#define RESETS_WDSEL_UART0_LSB _u(22) -#define RESETS_WDSEL_UART0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RESETS_WDSEL_TIMER -#define RESETS_WDSEL_TIMER_RESET _u(0x0) -#define RESETS_WDSEL_TIMER_BITS _u(0x00200000) -#define RESETS_WDSEL_TIMER_MSB _u(21) -#define RESETS_WDSEL_TIMER_LSB _u(21) -#define RESETS_WDSEL_TIMER_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RESETS_WDSEL_TBMAN -#define RESETS_WDSEL_TBMAN_RESET _u(0x0) -#define RESETS_WDSEL_TBMAN_BITS _u(0x00100000) -#define RESETS_WDSEL_TBMAN_MSB _u(20) -#define RESETS_WDSEL_TBMAN_LSB _u(20) -#define RESETS_WDSEL_TBMAN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RESETS_WDSEL_SYSINFO -#define RESETS_WDSEL_SYSINFO_RESET _u(0x0) -#define RESETS_WDSEL_SYSINFO_BITS _u(0x00080000) -#define RESETS_WDSEL_SYSINFO_MSB _u(19) -#define RESETS_WDSEL_SYSINFO_LSB _u(19) -#define RESETS_WDSEL_SYSINFO_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RESETS_WDSEL_SYSCFG -#define RESETS_WDSEL_SYSCFG_RESET _u(0x0) -#define RESETS_WDSEL_SYSCFG_BITS _u(0x00040000) -#define RESETS_WDSEL_SYSCFG_MSB _u(18) -#define RESETS_WDSEL_SYSCFG_LSB _u(18) -#define RESETS_WDSEL_SYSCFG_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RESETS_WDSEL_SPI1 -#define RESETS_WDSEL_SPI1_RESET _u(0x0) -#define RESETS_WDSEL_SPI1_BITS _u(0x00020000) -#define RESETS_WDSEL_SPI1_MSB _u(17) -#define RESETS_WDSEL_SPI1_LSB _u(17) -#define RESETS_WDSEL_SPI1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RESETS_WDSEL_SPI0 -#define RESETS_WDSEL_SPI0_RESET _u(0x0) -#define RESETS_WDSEL_SPI0_BITS _u(0x00010000) -#define RESETS_WDSEL_SPI0_MSB _u(16) -#define RESETS_WDSEL_SPI0_LSB _u(16) -#define RESETS_WDSEL_SPI0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RESETS_WDSEL_RTC -#define RESETS_WDSEL_RTC_RESET _u(0x0) -#define RESETS_WDSEL_RTC_BITS _u(0x00008000) -#define RESETS_WDSEL_RTC_MSB _u(15) -#define RESETS_WDSEL_RTC_LSB _u(15) -#define RESETS_WDSEL_RTC_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RESETS_WDSEL_PWM -#define RESETS_WDSEL_PWM_RESET _u(0x0) -#define RESETS_WDSEL_PWM_BITS _u(0x00004000) -#define RESETS_WDSEL_PWM_MSB _u(14) -#define RESETS_WDSEL_PWM_LSB _u(14) -#define RESETS_WDSEL_PWM_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RESETS_WDSEL_PLL_USB -#define RESETS_WDSEL_PLL_USB_RESET _u(0x0) -#define RESETS_WDSEL_PLL_USB_BITS _u(0x00002000) -#define RESETS_WDSEL_PLL_USB_MSB _u(13) -#define RESETS_WDSEL_PLL_USB_LSB _u(13) -#define RESETS_WDSEL_PLL_USB_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RESETS_WDSEL_PLL_SYS -#define RESETS_WDSEL_PLL_SYS_RESET _u(0x0) -#define RESETS_WDSEL_PLL_SYS_BITS _u(0x00001000) -#define RESETS_WDSEL_PLL_SYS_MSB _u(12) -#define RESETS_WDSEL_PLL_SYS_LSB _u(12) -#define RESETS_WDSEL_PLL_SYS_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RESETS_WDSEL_PIO1 -#define RESETS_WDSEL_PIO1_RESET _u(0x0) -#define RESETS_WDSEL_PIO1_BITS _u(0x00000800) -#define RESETS_WDSEL_PIO1_MSB _u(11) -#define RESETS_WDSEL_PIO1_LSB _u(11) -#define RESETS_WDSEL_PIO1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RESETS_WDSEL_PIO0 -#define RESETS_WDSEL_PIO0_RESET _u(0x0) -#define RESETS_WDSEL_PIO0_BITS _u(0x00000400) -#define RESETS_WDSEL_PIO0_MSB _u(10) -#define RESETS_WDSEL_PIO0_LSB _u(10) -#define RESETS_WDSEL_PIO0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RESETS_WDSEL_PADS_QSPI -#define RESETS_WDSEL_PADS_QSPI_RESET _u(0x0) -#define RESETS_WDSEL_PADS_QSPI_BITS _u(0x00000200) -#define RESETS_WDSEL_PADS_QSPI_MSB _u(9) -#define RESETS_WDSEL_PADS_QSPI_LSB _u(9) -#define RESETS_WDSEL_PADS_QSPI_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RESETS_WDSEL_PADS_BANK0 -#define RESETS_WDSEL_PADS_BANK0_RESET _u(0x0) -#define RESETS_WDSEL_PADS_BANK0_BITS _u(0x00000100) -#define RESETS_WDSEL_PADS_BANK0_MSB _u(8) -#define RESETS_WDSEL_PADS_BANK0_LSB _u(8) -#define RESETS_WDSEL_PADS_BANK0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RESETS_WDSEL_JTAG -#define RESETS_WDSEL_JTAG_RESET _u(0x0) -#define RESETS_WDSEL_JTAG_BITS _u(0x00000080) -#define RESETS_WDSEL_JTAG_MSB _u(7) -#define RESETS_WDSEL_JTAG_LSB _u(7) -#define RESETS_WDSEL_JTAG_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RESETS_WDSEL_IO_QSPI -#define RESETS_WDSEL_IO_QSPI_RESET _u(0x0) -#define RESETS_WDSEL_IO_QSPI_BITS _u(0x00000040) -#define RESETS_WDSEL_IO_QSPI_MSB _u(6) -#define RESETS_WDSEL_IO_QSPI_LSB _u(6) -#define RESETS_WDSEL_IO_QSPI_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RESETS_WDSEL_IO_BANK0 -#define RESETS_WDSEL_IO_BANK0_RESET _u(0x0) -#define RESETS_WDSEL_IO_BANK0_BITS _u(0x00000020) -#define RESETS_WDSEL_IO_BANK0_MSB _u(5) -#define RESETS_WDSEL_IO_BANK0_LSB _u(5) -#define RESETS_WDSEL_IO_BANK0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RESETS_WDSEL_I2C1 -#define RESETS_WDSEL_I2C1_RESET _u(0x0) -#define RESETS_WDSEL_I2C1_BITS _u(0x00000010) -#define RESETS_WDSEL_I2C1_MSB _u(4) -#define RESETS_WDSEL_I2C1_LSB _u(4) -#define RESETS_WDSEL_I2C1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RESETS_WDSEL_I2C0 -#define RESETS_WDSEL_I2C0_RESET _u(0x0) -#define RESETS_WDSEL_I2C0_BITS _u(0x00000008) -#define RESETS_WDSEL_I2C0_MSB _u(3) -#define RESETS_WDSEL_I2C0_LSB _u(3) -#define RESETS_WDSEL_I2C0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RESETS_WDSEL_DMA -#define RESETS_WDSEL_DMA_RESET _u(0x0) -#define RESETS_WDSEL_DMA_BITS _u(0x00000004) -#define RESETS_WDSEL_DMA_MSB _u(2) -#define RESETS_WDSEL_DMA_LSB _u(2) -#define RESETS_WDSEL_DMA_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RESETS_WDSEL_BUSCTRL -#define RESETS_WDSEL_BUSCTRL_RESET _u(0x0) -#define RESETS_WDSEL_BUSCTRL_BITS _u(0x00000002) -#define RESETS_WDSEL_BUSCTRL_MSB _u(1) -#define RESETS_WDSEL_BUSCTRL_LSB _u(1) -#define RESETS_WDSEL_BUSCTRL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RESETS_WDSEL_ADC -#define RESETS_WDSEL_ADC_RESET _u(0x0) -#define RESETS_WDSEL_ADC_BITS _u(0x00000001) -#define RESETS_WDSEL_ADC_MSB _u(0) -#define RESETS_WDSEL_ADC_LSB _u(0) -#define RESETS_WDSEL_ADC_ACCESS "RW" -// ============================================================================= -// Register : RESETS_RESET_DONE -// Description : Reset done. If a bit is set then a reset done signal has been -// returned by the peripheral. This indicates that the -// peripheral's registers are ready to be accessed. -#define RESETS_RESET_DONE_OFFSET _u(0x00000008) -#define RESETS_RESET_DONE_BITS _u(0x01ffffff) -#define RESETS_RESET_DONE_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : RESETS_RESET_DONE_USBCTRL -#define RESETS_RESET_DONE_USBCTRL_RESET _u(0x0) -#define RESETS_RESET_DONE_USBCTRL_BITS _u(0x01000000) -#define RESETS_RESET_DONE_USBCTRL_MSB _u(24) -#define RESETS_RESET_DONE_USBCTRL_LSB _u(24) -#define RESETS_RESET_DONE_USBCTRL_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RESETS_RESET_DONE_UART1 -#define RESETS_RESET_DONE_UART1_RESET _u(0x0) -#define RESETS_RESET_DONE_UART1_BITS _u(0x00800000) -#define RESETS_RESET_DONE_UART1_MSB _u(23) -#define RESETS_RESET_DONE_UART1_LSB _u(23) -#define RESETS_RESET_DONE_UART1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RESETS_RESET_DONE_UART0 -#define RESETS_RESET_DONE_UART0_RESET _u(0x0) -#define RESETS_RESET_DONE_UART0_BITS _u(0x00400000) -#define RESETS_RESET_DONE_UART0_MSB _u(22) -#define RESETS_RESET_DONE_UART0_LSB _u(22) -#define RESETS_RESET_DONE_UART0_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RESETS_RESET_DONE_TIMER -#define RESETS_RESET_DONE_TIMER_RESET _u(0x0) -#define RESETS_RESET_DONE_TIMER_BITS _u(0x00200000) -#define RESETS_RESET_DONE_TIMER_MSB _u(21) -#define RESETS_RESET_DONE_TIMER_LSB _u(21) -#define RESETS_RESET_DONE_TIMER_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RESETS_RESET_DONE_TBMAN -#define RESETS_RESET_DONE_TBMAN_RESET _u(0x0) -#define RESETS_RESET_DONE_TBMAN_BITS _u(0x00100000) -#define RESETS_RESET_DONE_TBMAN_MSB _u(20) -#define RESETS_RESET_DONE_TBMAN_LSB _u(20) -#define RESETS_RESET_DONE_TBMAN_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RESETS_RESET_DONE_SYSINFO -#define RESETS_RESET_DONE_SYSINFO_RESET _u(0x0) -#define RESETS_RESET_DONE_SYSINFO_BITS _u(0x00080000) -#define RESETS_RESET_DONE_SYSINFO_MSB _u(19) -#define RESETS_RESET_DONE_SYSINFO_LSB _u(19) -#define RESETS_RESET_DONE_SYSINFO_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RESETS_RESET_DONE_SYSCFG -#define RESETS_RESET_DONE_SYSCFG_RESET _u(0x0) -#define RESETS_RESET_DONE_SYSCFG_BITS _u(0x00040000) -#define RESETS_RESET_DONE_SYSCFG_MSB _u(18) -#define RESETS_RESET_DONE_SYSCFG_LSB _u(18) -#define RESETS_RESET_DONE_SYSCFG_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RESETS_RESET_DONE_SPI1 -#define RESETS_RESET_DONE_SPI1_RESET _u(0x0) -#define RESETS_RESET_DONE_SPI1_BITS _u(0x00020000) -#define RESETS_RESET_DONE_SPI1_MSB _u(17) -#define RESETS_RESET_DONE_SPI1_LSB _u(17) -#define RESETS_RESET_DONE_SPI1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RESETS_RESET_DONE_SPI0 -#define RESETS_RESET_DONE_SPI0_RESET _u(0x0) -#define RESETS_RESET_DONE_SPI0_BITS _u(0x00010000) -#define RESETS_RESET_DONE_SPI0_MSB _u(16) -#define RESETS_RESET_DONE_SPI0_LSB _u(16) -#define RESETS_RESET_DONE_SPI0_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RESETS_RESET_DONE_RTC -#define RESETS_RESET_DONE_RTC_RESET _u(0x0) -#define RESETS_RESET_DONE_RTC_BITS _u(0x00008000) -#define RESETS_RESET_DONE_RTC_MSB _u(15) -#define RESETS_RESET_DONE_RTC_LSB _u(15) -#define RESETS_RESET_DONE_RTC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RESETS_RESET_DONE_PWM -#define RESETS_RESET_DONE_PWM_RESET _u(0x0) -#define RESETS_RESET_DONE_PWM_BITS _u(0x00004000) -#define RESETS_RESET_DONE_PWM_MSB _u(14) -#define RESETS_RESET_DONE_PWM_LSB _u(14) -#define RESETS_RESET_DONE_PWM_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RESETS_RESET_DONE_PLL_USB -#define RESETS_RESET_DONE_PLL_USB_RESET _u(0x0) -#define RESETS_RESET_DONE_PLL_USB_BITS _u(0x00002000) -#define RESETS_RESET_DONE_PLL_USB_MSB _u(13) -#define RESETS_RESET_DONE_PLL_USB_LSB _u(13) -#define RESETS_RESET_DONE_PLL_USB_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RESETS_RESET_DONE_PLL_SYS -#define RESETS_RESET_DONE_PLL_SYS_RESET _u(0x0) -#define RESETS_RESET_DONE_PLL_SYS_BITS _u(0x00001000) -#define RESETS_RESET_DONE_PLL_SYS_MSB _u(12) -#define RESETS_RESET_DONE_PLL_SYS_LSB _u(12) -#define RESETS_RESET_DONE_PLL_SYS_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RESETS_RESET_DONE_PIO1 -#define RESETS_RESET_DONE_PIO1_RESET _u(0x0) -#define RESETS_RESET_DONE_PIO1_BITS _u(0x00000800) -#define RESETS_RESET_DONE_PIO1_MSB _u(11) -#define RESETS_RESET_DONE_PIO1_LSB _u(11) -#define RESETS_RESET_DONE_PIO1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RESETS_RESET_DONE_PIO0 -#define RESETS_RESET_DONE_PIO0_RESET _u(0x0) -#define RESETS_RESET_DONE_PIO0_BITS _u(0x00000400) -#define RESETS_RESET_DONE_PIO0_MSB _u(10) -#define RESETS_RESET_DONE_PIO0_LSB _u(10) -#define RESETS_RESET_DONE_PIO0_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RESETS_RESET_DONE_PADS_QSPI -#define RESETS_RESET_DONE_PADS_QSPI_RESET _u(0x0) -#define RESETS_RESET_DONE_PADS_QSPI_BITS _u(0x00000200) -#define RESETS_RESET_DONE_PADS_QSPI_MSB _u(9) -#define RESETS_RESET_DONE_PADS_QSPI_LSB _u(9) -#define RESETS_RESET_DONE_PADS_QSPI_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RESETS_RESET_DONE_PADS_BANK0 -#define RESETS_RESET_DONE_PADS_BANK0_RESET _u(0x0) -#define RESETS_RESET_DONE_PADS_BANK0_BITS _u(0x00000100) -#define RESETS_RESET_DONE_PADS_BANK0_MSB _u(8) -#define RESETS_RESET_DONE_PADS_BANK0_LSB _u(8) -#define RESETS_RESET_DONE_PADS_BANK0_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RESETS_RESET_DONE_JTAG -#define RESETS_RESET_DONE_JTAG_RESET _u(0x0) -#define RESETS_RESET_DONE_JTAG_BITS _u(0x00000080) -#define RESETS_RESET_DONE_JTAG_MSB _u(7) -#define RESETS_RESET_DONE_JTAG_LSB _u(7) -#define RESETS_RESET_DONE_JTAG_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RESETS_RESET_DONE_IO_QSPI -#define RESETS_RESET_DONE_IO_QSPI_RESET _u(0x0) -#define RESETS_RESET_DONE_IO_QSPI_BITS _u(0x00000040) -#define RESETS_RESET_DONE_IO_QSPI_MSB _u(6) -#define RESETS_RESET_DONE_IO_QSPI_LSB _u(6) -#define RESETS_RESET_DONE_IO_QSPI_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RESETS_RESET_DONE_IO_BANK0 -#define RESETS_RESET_DONE_IO_BANK0_RESET _u(0x0) -#define RESETS_RESET_DONE_IO_BANK0_BITS _u(0x00000020) -#define RESETS_RESET_DONE_IO_BANK0_MSB _u(5) -#define RESETS_RESET_DONE_IO_BANK0_LSB _u(5) -#define RESETS_RESET_DONE_IO_BANK0_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RESETS_RESET_DONE_I2C1 -#define RESETS_RESET_DONE_I2C1_RESET _u(0x0) -#define RESETS_RESET_DONE_I2C1_BITS _u(0x00000010) -#define RESETS_RESET_DONE_I2C1_MSB _u(4) -#define RESETS_RESET_DONE_I2C1_LSB _u(4) -#define RESETS_RESET_DONE_I2C1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RESETS_RESET_DONE_I2C0 -#define RESETS_RESET_DONE_I2C0_RESET _u(0x0) -#define RESETS_RESET_DONE_I2C0_BITS _u(0x00000008) -#define RESETS_RESET_DONE_I2C0_MSB _u(3) -#define RESETS_RESET_DONE_I2C0_LSB _u(3) -#define RESETS_RESET_DONE_I2C0_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RESETS_RESET_DONE_DMA -#define RESETS_RESET_DONE_DMA_RESET _u(0x0) -#define RESETS_RESET_DONE_DMA_BITS _u(0x00000004) -#define RESETS_RESET_DONE_DMA_MSB _u(2) -#define RESETS_RESET_DONE_DMA_LSB _u(2) -#define RESETS_RESET_DONE_DMA_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RESETS_RESET_DONE_BUSCTRL -#define RESETS_RESET_DONE_BUSCTRL_RESET _u(0x0) -#define RESETS_RESET_DONE_BUSCTRL_BITS _u(0x00000002) -#define RESETS_RESET_DONE_BUSCTRL_MSB _u(1) -#define RESETS_RESET_DONE_BUSCTRL_LSB _u(1) -#define RESETS_RESET_DONE_BUSCTRL_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RESETS_RESET_DONE_ADC -#define RESETS_RESET_DONE_ADC_RESET _u(0x0) -#define RESETS_RESET_DONE_ADC_BITS _u(0x00000001) -#define RESETS_RESET_DONE_ADC_MSB _u(0) -#define RESETS_RESET_DONE_ADC_LSB _u(0) -#define RESETS_RESET_DONE_ADC_ACCESS "RO" -// ============================================================================= -#endif // _HARDWARE_REGS_RESETS_H - diff --git a/lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/rosc.h b/lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/rosc.h deleted file mode 100644 index bd4bb9d4a9..0000000000 --- a/lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/rosc.h +++ /dev/null @@ -1,314 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -// ============================================================================= -// Register block : ROSC -// Version : 1 -// Bus type : apb -// ============================================================================= -#ifndef _HARDWARE_REGS_ROSC_H -#define _HARDWARE_REGS_ROSC_H -// ============================================================================= -// Register : ROSC_CTRL -// Description : Ring Oscillator control -#define ROSC_CTRL_OFFSET _u(0x00000000) -#define ROSC_CTRL_BITS _u(0x00ffffff) -#define ROSC_CTRL_RESET _u(0x00000aa0) -// ----------------------------------------------------------------------------- -// Field : ROSC_CTRL_ENABLE -// Description : On power-up this field is initialised to ENABLE -// The system clock must be switched to another source before -// setting this field to DISABLE otherwise the chip will lock up -// The 12-bit code is intended to give some protection against -// accidental writes. An invalid setting will enable the -// oscillator. -// 0xd1e -> DISABLE -// 0xfab -> ENABLE -#define ROSC_CTRL_ENABLE_RESET "-" -#define ROSC_CTRL_ENABLE_BITS _u(0x00fff000) -#define ROSC_CTRL_ENABLE_MSB _u(23) -#define ROSC_CTRL_ENABLE_LSB _u(12) -#define ROSC_CTRL_ENABLE_ACCESS "RW" -#define ROSC_CTRL_ENABLE_VALUE_DISABLE _u(0xd1e) -#define ROSC_CTRL_ENABLE_VALUE_ENABLE _u(0xfab) -// ----------------------------------------------------------------------------- -// Field : ROSC_CTRL_FREQ_RANGE -// Description : Controls the number of delay stages in the ROSC ring -// LOW uses stages 0 to 7 -// MEDIUM uses stages 2 to 7 -// HIGH uses stages 4 to 7 -// TOOHIGH uses stages 6 to 7 and should not be used because its -// frequency exceeds design specifications -// The clock output will not glitch when changing the range up one -// step at a time -// The clock output will glitch when changing the range down -// Note: the values here are gray coded which is why HIGH comes -// before TOOHIGH -// 0xfa4 -> LOW -// 0xfa5 -> MEDIUM -// 0xfa7 -> HIGH -// 0xfa6 -> TOOHIGH -#define ROSC_CTRL_FREQ_RANGE_RESET _u(0xaa0) -#define ROSC_CTRL_FREQ_RANGE_BITS _u(0x00000fff) -#define ROSC_CTRL_FREQ_RANGE_MSB _u(11) -#define ROSC_CTRL_FREQ_RANGE_LSB _u(0) -#define ROSC_CTRL_FREQ_RANGE_ACCESS "RW" -#define ROSC_CTRL_FREQ_RANGE_VALUE_LOW _u(0xfa4) -#define ROSC_CTRL_FREQ_RANGE_VALUE_MEDIUM _u(0xfa5) -#define ROSC_CTRL_FREQ_RANGE_VALUE_HIGH _u(0xfa7) -#define ROSC_CTRL_FREQ_RANGE_VALUE_TOOHIGH _u(0xfa6) -// ============================================================================= -// Register : ROSC_FREQA -// Description : The FREQA & FREQB registers control the frequency by -// controlling the drive strength of each stage -// The drive strength has 4 levels determined by the number of -// bits set -// Increasing the number of bits set increases the drive strength -// and increases the oscillation frequency -// 0 bits set is the default drive strength -// 1 bit set doubles the drive strength -// 2 bits set triples drive strength -// 3 bits set quadruples drive strength -#define ROSC_FREQA_OFFSET _u(0x00000004) -#define ROSC_FREQA_BITS _u(0xffff7777) -#define ROSC_FREQA_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : ROSC_FREQA_PASSWD -// Description : Set to 0x9696 to apply the settings -// Any other value in this field will set all drive strengths to 0 -// 0x9696 -> PASS -#define ROSC_FREQA_PASSWD_RESET _u(0x0000) -#define ROSC_FREQA_PASSWD_BITS _u(0xffff0000) -#define ROSC_FREQA_PASSWD_MSB _u(31) -#define ROSC_FREQA_PASSWD_LSB _u(16) -#define ROSC_FREQA_PASSWD_ACCESS "RW" -#define ROSC_FREQA_PASSWD_VALUE_PASS _u(0x9696) -// ----------------------------------------------------------------------------- -// Field : ROSC_FREQA_DS3 -// Description : Stage 3 drive strength -#define ROSC_FREQA_DS3_RESET _u(0x0) -#define ROSC_FREQA_DS3_BITS _u(0x00007000) -#define ROSC_FREQA_DS3_MSB _u(14) -#define ROSC_FREQA_DS3_LSB _u(12) -#define ROSC_FREQA_DS3_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ROSC_FREQA_DS2 -// Description : Stage 2 drive strength -#define ROSC_FREQA_DS2_RESET _u(0x0) -#define ROSC_FREQA_DS2_BITS _u(0x00000700) -#define ROSC_FREQA_DS2_MSB _u(10) -#define ROSC_FREQA_DS2_LSB _u(8) -#define ROSC_FREQA_DS2_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ROSC_FREQA_DS1 -// Description : Stage 1 drive strength -#define ROSC_FREQA_DS1_RESET _u(0x0) -#define ROSC_FREQA_DS1_BITS _u(0x00000070) -#define ROSC_FREQA_DS1_MSB _u(6) -#define ROSC_FREQA_DS1_LSB _u(4) -#define ROSC_FREQA_DS1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ROSC_FREQA_DS0 -// Description : Stage 0 drive strength -#define ROSC_FREQA_DS0_RESET _u(0x0) -#define ROSC_FREQA_DS0_BITS _u(0x00000007) -#define ROSC_FREQA_DS0_MSB _u(2) -#define ROSC_FREQA_DS0_LSB _u(0) -#define ROSC_FREQA_DS0_ACCESS "RW" -// ============================================================================= -// Register : ROSC_FREQB -// Description : For a detailed description see freqa register -#define ROSC_FREQB_OFFSET _u(0x00000008) -#define ROSC_FREQB_BITS _u(0xffff7777) -#define ROSC_FREQB_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : ROSC_FREQB_PASSWD -// Description : Set to 0x9696 to apply the settings -// Any other value in this field will set all drive strengths to 0 -// 0x9696 -> PASS -#define ROSC_FREQB_PASSWD_RESET _u(0x0000) -#define ROSC_FREQB_PASSWD_BITS _u(0xffff0000) -#define ROSC_FREQB_PASSWD_MSB _u(31) -#define ROSC_FREQB_PASSWD_LSB _u(16) -#define ROSC_FREQB_PASSWD_ACCESS "RW" -#define ROSC_FREQB_PASSWD_VALUE_PASS _u(0x9696) -// ----------------------------------------------------------------------------- -// Field : ROSC_FREQB_DS7 -// Description : Stage 7 drive strength -#define ROSC_FREQB_DS7_RESET _u(0x0) -#define ROSC_FREQB_DS7_BITS _u(0x00007000) -#define ROSC_FREQB_DS7_MSB _u(14) -#define ROSC_FREQB_DS7_LSB _u(12) -#define ROSC_FREQB_DS7_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ROSC_FREQB_DS6 -// Description : Stage 6 drive strength -#define ROSC_FREQB_DS6_RESET _u(0x0) -#define ROSC_FREQB_DS6_BITS _u(0x00000700) -#define ROSC_FREQB_DS6_MSB _u(10) -#define ROSC_FREQB_DS6_LSB _u(8) -#define ROSC_FREQB_DS6_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ROSC_FREQB_DS5 -// Description : Stage 5 drive strength -#define ROSC_FREQB_DS5_RESET _u(0x0) -#define ROSC_FREQB_DS5_BITS _u(0x00000070) -#define ROSC_FREQB_DS5_MSB _u(6) -#define ROSC_FREQB_DS5_LSB _u(4) -#define ROSC_FREQB_DS5_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ROSC_FREQB_DS4 -// Description : Stage 4 drive strength -#define ROSC_FREQB_DS4_RESET _u(0x0) -#define ROSC_FREQB_DS4_BITS _u(0x00000007) -#define ROSC_FREQB_DS4_MSB _u(2) -#define ROSC_FREQB_DS4_LSB _u(0) -#define ROSC_FREQB_DS4_ACCESS "RW" -// ============================================================================= -// Register : ROSC_DORMANT -// Description : Ring Oscillator pause control -// This is used to save power by pausing the ROSC -// On power-up this field is initialised to WAKE -// An invalid write will also select WAKE -// Warning: setup the irq before selecting dormant mode -// 0x636f6d61 -> dormant -// 0x77616b65 -> WAKE -#define ROSC_DORMANT_OFFSET _u(0x0000000c) -#define ROSC_DORMANT_BITS _u(0xffffffff) -#define ROSC_DORMANT_RESET "-" -#define ROSC_DORMANT_MSB _u(31) -#define ROSC_DORMANT_LSB _u(0) -#define ROSC_DORMANT_ACCESS "RW" -#define ROSC_DORMANT_VALUE_DORMANT _u(0x636f6d61) -#define ROSC_DORMANT_VALUE_WAKE _u(0x77616b65) -// ============================================================================= -// Register : ROSC_DIV -// Description : Controls the output divider -// set to 0xaa0 + div where -// div = 0 divides by 32 -// div = 1-31 divides by div -// any other value sets div=31 -// this register resets to div=16 -// 0xaa0 -> PASS -#define ROSC_DIV_OFFSET _u(0x00000010) -#define ROSC_DIV_BITS _u(0x00000fff) -#define ROSC_DIV_RESET "-" -#define ROSC_DIV_MSB _u(11) -#define ROSC_DIV_LSB _u(0) -#define ROSC_DIV_ACCESS "RW" -#define ROSC_DIV_VALUE_PASS _u(0xaa0) -// ============================================================================= -// Register : ROSC_PHASE -// Description : Controls the phase shifted output -#define ROSC_PHASE_OFFSET _u(0x00000014) -#define ROSC_PHASE_BITS _u(0x00000fff) -#define ROSC_PHASE_RESET _u(0x00000008) -// ----------------------------------------------------------------------------- -// Field : ROSC_PHASE_PASSWD -// Description : set to 0xaa -// any other value enables the output with shift=0 -#define ROSC_PHASE_PASSWD_RESET _u(0x00) -#define ROSC_PHASE_PASSWD_BITS _u(0x00000ff0) -#define ROSC_PHASE_PASSWD_MSB _u(11) -#define ROSC_PHASE_PASSWD_LSB _u(4) -#define ROSC_PHASE_PASSWD_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ROSC_PHASE_ENABLE -// Description : enable the phase-shifted output -// this can be changed on-the-fly -#define ROSC_PHASE_ENABLE_RESET _u(0x1) -#define ROSC_PHASE_ENABLE_BITS _u(0x00000008) -#define ROSC_PHASE_ENABLE_MSB _u(3) -#define ROSC_PHASE_ENABLE_LSB _u(3) -#define ROSC_PHASE_ENABLE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ROSC_PHASE_FLIP -// Description : invert the phase-shifted output -// this is ignored when div=1 -#define ROSC_PHASE_FLIP_RESET _u(0x0) -#define ROSC_PHASE_FLIP_BITS _u(0x00000004) -#define ROSC_PHASE_FLIP_MSB _u(2) -#define ROSC_PHASE_FLIP_LSB _u(2) -#define ROSC_PHASE_FLIP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ROSC_PHASE_SHIFT -// Description : phase shift the phase-shifted output by SHIFT input clocks -// this can be changed on-the-fly -// must be set to 0 before setting div=1 -#define ROSC_PHASE_SHIFT_RESET _u(0x0) -#define ROSC_PHASE_SHIFT_BITS _u(0x00000003) -#define ROSC_PHASE_SHIFT_MSB _u(1) -#define ROSC_PHASE_SHIFT_LSB _u(0) -#define ROSC_PHASE_SHIFT_ACCESS "RW" -// ============================================================================= -// Register : ROSC_STATUS -// Description : Ring Oscillator Status -#define ROSC_STATUS_OFFSET _u(0x00000018) -#define ROSC_STATUS_BITS _u(0x81011000) -#define ROSC_STATUS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : ROSC_STATUS_STABLE -// Description : Oscillator is running and stable -#define ROSC_STATUS_STABLE_RESET _u(0x0) -#define ROSC_STATUS_STABLE_BITS _u(0x80000000) -#define ROSC_STATUS_STABLE_MSB _u(31) -#define ROSC_STATUS_STABLE_LSB _u(31) -#define ROSC_STATUS_STABLE_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : ROSC_STATUS_BADWRITE -// Description : An invalid value has been written to CTRL_ENABLE or -// CTRL_FREQ_RANGE or FREQA or FREQB or DIV or PHASE or DORMANT -#define ROSC_STATUS_BADWRITE_RESET _u(0x0) -#define ROSC_STATUS_BADWRITE_BITS _u(0x01000000) -#define ROSC_STATUS_BADWRITE_MSB _u(24) -#define ROSC_STATUS_BADWRITE_LSB _u(24) -#define ROSC_STATUS_BADWRITE_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : ROSC_STATUS_DIV_RUNNING -// Description : post-divider is running -// this resets to 0 but transitions to 1 during chip startup -#define ROSC_STATUS_DIV_RUNNING_RESET "-" -#define ROSC_STATUS_DIV_RUNNING_BITS _u(0x00010000) -#define ROSC_STATUS_DIV_RUNNING_MSB _u(16) -#define ROSC_STATUS_DIV_RUNNING_LSB _u(16) -#define ROSC_STATUS_DIV_RUNNING_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : ROSC_STATUS_ENABLED -// Description : Oscillator is enabled but not necessarily running and stable -// this resets to 0 but transitions to 1 during chip startup -#define ROSC_STATUS_ENABLED_RESET "-" -#define ROSC_STATUS_ENABLED_BITS _u(0x00001000) -#define ROSC_STATUS_ENABLED_MSB _u(12) -#define ROSC_STATUS_ENABLED_LSB _u(12) -#define ROSC_STATUS_ENABLED_ACCESS "RO" -// ============================================================================= -// Register : ROSC_RANDOMBIT -// Description : This just reads the state of the oscillator output so -// randomness is compromised if the ring oscillator is stopped or -// run at a harmonic of the bus frequency -#define ROSC_RANDOMBIT_OFFSET _u(0x0000001c) -#define ROSC_RANDOMBIT_BITS _u(0x00000001) -#define ROSC_RANDOMBIT_RESET _u(0x00000001) -#define ROSC_RANDOMBIT_MSB _u(0) -#define ROSC_RANDOMBIT_LSB _u(0) -#define ROSC_RANDOMBIT_ACCESS "RO" -// ============================================================================= -// Register : ROSC_COUNT -// Description : A down counter running at the ROSC frequency which counts to -// zero and stops. -// To start the counter write a non-zero value. -// Can be used for short software pauses when setting up time -// sensitive hardware. -#define ROSC_COUNT_OFFSET _u(0x00000020) -#define ROSC_COUNT_BITS _u(0x000000ff) -#define ROSC_COUNT_RESET _u(0x00000000) -#define ROSC_COUNT_MSB _u(7) -#define ROSC_COUNT_LSB _u(0) -#define ROSC_COUNT_ACCESS "RW" -// ============================================================================= -#endif // _HARDWARE_REGS_ROSC_H - diff --git a/lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/rtc.h b/lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/rtc.h deleted file mode 100644 index 86d519eb04..0000000000 --- a/lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/rtc.h +++ /dev/null @@ -1,396 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -// ============================================================================= -// Register block : RTC -// Version : 1 -// Bus type : apb -// Description : Register block to control RTC -// ============================================================================= -#ifndef _HARDWARE_REGS_RTC_H -#define _HARDWARE_REGS_RTC_H -// ============================================================================= -// Register : RTC_CLKDIV_M1 -// Description : Divider minus 1 for the 1 second counter. Safe to change the -// value when RTC is not enabled. -#define RTC_CLKDIV_M1_OFFSET _u(0x00000000) -#define RTC_CLKDIV_M1_BITS _u(0x0000ffff) -#define RTC_CLKDIV_M1_RESET _u(0x00000000) -#define RTC_CLKDIV_M1_MSB _u(15) -#define RTC_CLKDIV_M1_LSB _u(0) -#define RTC_CLKDIV_M1_ACCESS "RW" -// ============================================================================= -// Register : RTC_SETUP_0 -// Description : RTC setup register 0 -#define RTC_SETUP_0_OFFSET _u(0x00000004) -#define RTC_SETUP_0_BITS _u(0x00ffff1f) -#define RTC_SETUP_0_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : RTC_SETUP_0_YEAR -// Description : Year -#define RTC_SETUP_0_YEAR_RESET _u(0x000) -#define RTC_SETUP_0_YEAR_BITS _u(0x00fff000) -#define RTC_SETUP_0_YEAR_MSB _u(23) -#define RTC_SETUP_0_YEAR_LSB _u(12) -#define RTC_SETUP_0_YEAR_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RTC_SETUP_0_MONTH -// Description : Month (1..12) -#define RTC_SETUP_0_MONTH_RESET _u(0x0) -#define RTC_SETUP_0_MONTH_BITS _u(0x00000f00) -#define RTC_SETUP_0_MONTH_MSB _u(11) -#define RTC_SETUP_0_MONTH_LSB _u(8) -#define RTC_SETUP_0_MONTH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RTC_SETUP_0_DAY -// Description : Day of the month (1..31) -#define RTC_SETUP_0_DAY_RESET _u(0x00) -#define RTC_SETUP_0_DAY_BITS _u(0x0000001f) -#define RTC_SETUP_0_DAY_MSB _u(4) -#define RTC_SETUP_0_DAY_LSB _u(0) -#define RTC_SETUP_0_DAY_ACCESS "RW" -// ============================================================================= -// Register : RTC_SETUP_1 -// Description : RTC setup register 1 -#define RTC_SETUP_1_OFFSET _u(0x00000008) -#define RTC_SETUP_1_BITS _u(0x071f3f3f) -#define RTC_SETUP_1_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : RTC_SETUP_1_DOTW -// Description : Day of the week: 1-Monday...0-Sunday ISO 8601 mod 7 -#define RTC_SETUP_1_DOTW_RESET _u(0x0) -#define RTC_SETUP_1_DOTW_BITS _u(0x07000000) -#define RTC_SETUP_1_DOTW_MSB _u(26) -#define RTC_SETUP_1_DOTW_LSB _u(24) -#define RTC_SETUP_1_DOTW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RTC_SETUP_1_HOUR -// Description : Hours -#define RTC_SETUP_1_HOUR_RESET _u(0x00) -#define RTC_SETUP_1_HOUR_BITS _u(0x001f0000) -#define RTC_SETUP_1_HOUR_MSB _u(20) -#define RTC_SETUP_1_HOUR_LSB _u(16) -#define RTC_SETUP_1_HOUR_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RTC_SETUP_1_MIN -// Description : Minutes -#define RTC_SETUP_1_MIN_RESET _u(0x00) -#define RTC_SETUP_1_MIN_BITS _u(0x00003f00) -#define RTC_SETUP_1_MIN_MSB _u(13) -#define RTC_SETUP_1_MIN_LSB _u(8) -#define RTC_SETUP_1_MIN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RTC_SETUP_1_SEC -// Description : Seconds -#define RTC_SETUP_1_SEC_RESET _u(0x00) -#define RTC_SETUP_1_SEC_BITS _u(0x0000003f) -#define RTC_SETUP_1_SEC_MSB _u(5) -#define RTC_SETUP_1_SEC_LSB _u(0) -#define RTC_SETUP_1_SEC_ACCESS "RW" -// ============================================================================= -// Register : RTC_CTRL -// Description : RTC Control and status -#define RTC_CTRL_OFFSET _u(0x0000000c) -#define RTC_CTRL_BITS _u(0x00000113) -#define RTC_CTRL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : RTC_CTRL_FORCE_NOTLEAPYEAR -// Description : If set, leapyear is forced off. -// Useful for years divisible by 100 but not by 400 -#define RTC_CTRL_FORCE_NOTLEAPYEAR_RESET _u(0x0) -#define RTC_CTRL_FORCE_NOTLEAPYEAR_BITS _u(0x00000100) -#define RTC_CTRL_FORCE_NOTLEAPYEAR_MSB _u(8) -#define RTC_CTRL_FORCE_NOTLEAPYEAR_LSB _u(8) -#define RTC_CTRL_FORCE_NOTLEAPYEAR_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RTC_CTRL_LOAD -// Description : Load RTC -#define RTC_CTRL_LOAD_RESET _u(0x0) -#define RTC_CTRL_LOAD_BITS _u(0x00000010) -#define RTC_CTRL_LOAD_MSB _u(4) -#define RTC_CTRL_LOAD_LSB _u(4) -#define RTC_CTRL_LOAD_ACCESS "SC" -// ----------------------------------------------------------------------------- -// Field : RTC_CTRL_RTC_ACTIVE -// Description : RTC enabled (running) -#define RTC_CTRL_RTC_ACTIVE_RESET "-" -#define RTC_CTRL_RTC_ACTIVE_BITS _u(0x00000002) -#define RTC_CTRL_RTC_ACTIVE_MSB _u(1) -#define RTC_CTRL_RTC_ACTIVE_LSB _u(1) -#define RTC_CTRL_RTC_ACTIVE_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RTC_CTRL_RTC_ENABLE -// Description : Enable RTC -#define RTC_CTRL_RTC_ENABLE_RESET _u(0x0) -#define RTC_CTRL_RTC_ENABLE_BITS _u(0x00000001) -#define RTC_CTRL_RTC_ENABLE_MSB _u(0) -#define RTC_CTRL_RTC_ENABLE_LSB _u(0) -#define RTC_CTRL_RTC_ENABLE_ACCESS "RW" -// ============================================================================= -// Register : RTC_IRQ_SETUP_0 -// Description : Interrupt setup register 0 -#define RTC_IRQ_SETUP_0_OFFSET _u(0x00000010) -#define RTC_IRQ_SETUP_0_BITS _u(0x37ffff1f) -#define RTC_IRQ_SETUP_0_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : RTC_IRQ_SETUP_0_MATCH_ACTIVE -#define RTC_IRQ_SETUP_0_MATCH_ACTIVE_RESET "-" -#define RTC_IRQ_SETUP_0_MATCH_ACTIVE_BITS _u(0x20000000) -#define RTC_IRQ_SETUP_0_MATCH_ACTIVE_MSB _u(29) -#define RTC_IRQ_SETUP_0_MATCH_ACTIVE_LSB _u(29) -#define RTC_IRQ_SETUP_0_MATCH_ACTIVE_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RTC_IRQ_SETUP_0_MATCH_ENA -// Description : Global match enable. Don't change any other value while this -// one is enabled -#define RTC_IRQ_SETUP_0_MATCH_ENA_RESET _u(0x0) -#define RTC_IRQ_SETUP_0_MATCH_ENA_BITS _u(0x10000000) -#define RTC_IRQ_SETUP_0_MATCH_ENA_MSB _u(28) -#define RTC_IRQ_SETUP_0_MATCH_ENA_LSB _u(28) -#define RTC_IRQ_SETUP_0_MATCH_ENA_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RTC_IRQ_SETUP_0_YEAR_ENA -// Description : Enable year matching -#define RTC_IRQ_SETUP_0_YEAR_ENA_RESET _u(0x0) -#define RTC_IRQ_SETUP_0_YEAR_ENA_BITS _u(0x04000000) -#define RTC_IRQ_SETUP_0_YEAR_ENA_MSB _u(26) -#define RTC_IRQ_SETUP_0_YEAR_ENA_LSB _u(26) -#define RTC_IRQ_SETUP_0_YEAR_ENA_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RTC_IRQ_SETUP_0_MONTH_ENA -// Description : Enable month matching -#define RTC_IRQ_SETUP_0_MONTH_ENA_RESET _u(0x0) -#define RTC_IRQ_SETUP_0_MONTH_ENA_BITS _u(0x02000000) -#define RTC_IRQ_SETUP_0_MONTH_ENA_MSB _u(25) -#define RTC_IRQ_SETUP_0_MONTH_ENA_LSB _u(25) -#define RTC_IRQ_SETUP_0_MONTH_ENA_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RTC_IRQ_SETUP_0_DAY_ENA -// Description : Enable day matching -#define RTC_IRQ_SETUP_0_DAY_ENA_RESET _u(0x0) -#define RTC_IRQ_SETUP_0_DAY_ENA_BITS _u(0x01000000) -#define RTC_IRQ_SETUP_0_DAY_ENA_MSB _u(24) -#define RTC_IRQ_SETUP_0_DAY_ENA_LSB _u(24) -#define RTC_IRQ_SETUP_0_DAY_ENA_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RTC_IRQ_SETUP_0_YEAR -// Description : Year -#define RTC_IRQ_SETUP_0_YEAR_RESET _u(0x000) -#define RTC_IRQ_SETUP_0_YEAR_BITS _u(0x00fff000) -#define RTC_IRQ_SETUP_0_YEAR_MSB _u(23) -#define RTC_IRQ_SETUP_0_YEAR_LSB _u(12) -#define RTC_IRQ_SETUP_0_YEAR_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RTC_IRQ_SETUP_0_MONTH -// Description : Month (1..12) -#define RTC_IRQ_SETUP_0_MONTH_RESET _u(0x0) -#define RTC_IRQ_SETUP_0_MONTH_BITS _u(0x00000f00) -#define RTC_IRQ_SETUP_0_MONTH_MSB _u(11) -#define RTC_IRQ_SETUP_0_MONTH_LSB _u(8) -#define RTC_IRQ_SETUP_0_MONTH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RTC_IRQ_SETUP_0_DAY -// Description : Day of the month (1..31) -#define RTC_IRQ_SETUP_0_DAY_RESET _u(0x00) -#define RTC_IRQ_SETUP_0_DAY_BITS _u(0x0000001f) -#define RTC_IRQ_SETUP_0_DAY_MSB _u(4) -#define RTC_IRQ_SETUP_0_DAY_LSB _u(0) -#define RTC_IRQ_SETUP_0_DAY_ACCESS "RW" -// ============================================================================= -// Register : RTC_IRQ_SETUP_1 -// Description : Interrupt setup register 1 -#define RTC_IRQ_SETUP_1_OFFSET _u(0x00000014) -#define RTC_IRQ_SETUP_1_BITS _u(0xf71f3f3f) -#define RTC_IRQ_SETUP_1_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : RTC_IRQ_SETUP_1_DOTW_ENA -// Description : Enable day of the week matching -#define RTC_IRQ_SETUP_1_DOTW_ENA_RESET _u(0x0) -#define RTC_IRQ_SETUP_1_DOTW_ENA_BITS _u(0x80000000) -#define RTC_IRQ_SETUP_1_DOTW_ENA_MSB _u(31) -#define RTC_IRQ_SETUP_1_DOTW_ENA_LSB _u(31) -#define RTC_IRQ_SETUP_1_DOTW_ENA_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RTC_IRQ_SETUP_1_HOUR_ENA -// Description : Enable hour matching -#define RTC_IRQ_SETUP_1_HOUR_ENA_RESET _u(0x0) -#define RTC_IRQ_SETUP_1_HOUR_ENA_BITS _u(0x40000000) -#define RTC_IRQ_SETUP_1_HOUR_ENA_MSB _u(30) -#define RTC_IRQ_SETUP_1_HOUR_ENA_LSB _u(30) -#define RTC_IRQ_SETUP_1_HOUR_ENA_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RTC_IRQ_SETUP_1_MIN_ENA -// Description : Enable minute matching -#define RTC_IRQ_SETUP_1_MIN_ENA_RESET _u(0x0) -#define RTC_IRQ_SETUP_1_MIN_ENA_BITS _u(0x20000000) -#define RTC_IRQ_SETUP_1_MIN_ENA_MSB _u(29) -#define RTC_IRQ_SETUP_1_MIN_ENA_LSB _u(29) -#define RTC_IRQ_SETUP_1_MIN_ENA_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RTC_IRQ_SETUP_1_SEC_ENA -// Description : Enable second matching -#define RTC_IRQ_SETUP_1_SEC_ENA_RESET _u(0x0) -#define RTC_IRQ_SETUP_1_SEC_ENA_BITS _u(0x10000000) -#define RTC_IRQ_SETUP_1_SEC_ENA_MSB _u(28) -#define RTC_IRQ_SETUP_1_SEC_ENA_LSB _u(28) -#define RTC_IRQ_SETUP_1_SEC_ENA_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RTC_IRQ_SETUP_1_DOTW -// Description : Day of the week -#define RTC_IRQ_SETUP_1_DOTW_RESET _u(0x0) -#define RTC_IRQ_SETUP_1_DOTW_BITS _u(0x07000000) -#define RTC_IRQ_SETUP_1_DOTW_MSB _u(26) -#define RTC_IRQ_SETUP_1_DOTW_LSB _u(24) -#define RTC_IRQ_SETUP_1_DOTW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RTC_IRQ_SETUP_1_HOUR -// Description : Hours -#define RTC_IRQ_SETUP_1_HOUR_RESET _u(0x00) -#define RTC_IRQ_SETUP_1_HOUR_BITS _u(0x001f0000) -#define RTC_IRQ_SETUP_1_HOUR_MSB _u(20) -#define RTC_IRQ_SETUP_1_HOUR_LSB _u(16) -#define RTC_IRQ_SETUP_1_HOUR_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RTC_IRQ_SETUP_1_MIN -// Description : Minutes -#define RTC_IRQ_SETUP_1_MIN_RESET _u(0x00) -#define RTC_IRQ_SETUP_1_MIN_BITS _u(0x00003f00) -#define RTC_IRQ_SETUP_1_MIN_MSB _u(13) -#define RTC_IRQ_SETUP_1_MIN_LSB _u(8) -#define RTC_IRQ_SETUP_1_MIN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RTC_IRQ_SETUP_1_SEC -// Description : Seconds -#define RTC_IRQ_SETUP_1_SEC_RESET _u(0x00) -#define RTC_IRQ_SETUP_1_SEC_BITS _u(0x0000003f) -#define RTC_IRQ_SETUP_1_SEC_MSB _u(5) -#define RTC_IRQ_SETUP_1_SEC_LSB _u(0) -#define RTC_IRQ_SETUP_1_SEC_ACCESS "RW" -// ============================================================================= -// Register : RTC_RTC_1 -// Description : RTC register 1. -#define RTC_RTC_1_OFFSET _u(0x00000018) -#define RTC_RTC_1_BITS _u(0x00ffff1f) -#define RTC_RTC_1_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : RTC_RTC_1_YEAR -// Description : Year -#define RTC_RTC_1_YEAR_RESET "-" -#define RTC_RTC_1_YEAR_BITS _u(0x00fff000) -#define RTC_RTC_1_YEAR_MSB _u(23) -#define RTC_RTC_1_YEAR_LSB _u(12) -#define RTC_RTC_1_YEAR_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RTC_RTC_1_MONTH -// Description : Month (1..12) -#define RTC_RTC_1_MONTH_RESET "-" -#define RTC_RTC_1_MONTH_BITS _u(0x00000f00) -#define RTC_RTC_1_MONTH_MSB _u(11) -#define RTC_RTC_1_MONTH_LSB _u(8) -#define RTC_RTC_1_MONTH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RTC_RTC_1_DAY -// Description : Day of the month (1..31) -#define RTC_RTC_1_DAY_RESET "-" -#define RTC_RTC_1_DAY_BITS _u(0x0000001f) -#define RTC_RTC_1_DAY_MSB _u(4) -#define RTC_RTC_1_DAY_LSB _u(0) -#define RTC_RTC_1_DAY_ACCESS "RO" -// ============================================================================= -// Register : RTC_RTC_0 -// Description : RTC register 0 -// Read this before RTC 1! -#define RTC_RTC_0_OFFSET _u(0x0000001c) -#define RTC_RTC_0_BITS _u(0x071f3f3f) -#define RTC_RTC_0_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : RTC_RTC_0_DOTW -// Description : Day of the week -#define RTC_RTC_0_DOTW_RESET "-" -#define RTC_RTC_0_DOTW_BITS _u(0x07000000) -#define RTC_RTC_0_DOTW_MSB _u(26) -#define RTC_RTC_0_DOTW_LSB _u(24) -#define RTC_RTC_0_DOTW_ACCESS "RF" -// ----------------------------------------------------------------------------- -// Field : RTC_RTC_0_HOUR -// Description : Hours -#define RTC_RTC_0_HOUR_RESET "-" -#define RTC_RTC_0_HOUR_BITS _u(0x001f0000) -#define RTC_RTC_0_HOUR_MSB _u(20) -#define RTC_RTC_0_HOUR_LSB _u(16) -#define RTC_RTC_0_HOUR_ACCESS "RF" -// ----------------------------------------------------------------------------- -// Field : RTC_RTC_0_MIN -// Description : Minutes -#define RTC_RTC_0_MIN_RESET "-" -#define RTC_RTC_0_MIN_BITS _u(0x00003f00) -#define RTC_RTC_0_MIN_MSB _u(13) -#define RTC_RTC_0_MIN_LSB _u(8) -#define RTC_RTC_0_MIN_ACCESS "RF" -// ----------------------------------------------------------------------------- -// Field : RTC_RTC_0_SEC -// Description : Seconds -#define RTC_RTC_0_SEC_RESET "-" -#define RTC_RTC_0_SEC_BITS _u(0x0000003f) -#define RTC_RTC_0_SEC_MSB _u(5) -#define RTC_RTC_0_SEC_LSB _u(0) -#define RTC_RTC_0_SEC_ACCESS "RF" -// ============================================================================= -// Register : RTC_INTR -// Description : Raw Interrupts -#define RTC_INTR_OFFSET _u(0x00000020) -#define RTC_INTR_BITS _u(0x00000001) -#define RTC_INTR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : RTC_INTR_RTC -#define RTC_INTR_RTC_RESET _u(0x0) -#define RTC_INTR_RTC_BITS _u(0x00000001) -#define RTC_INTR_RTC_MSB _u(0) -#define RTC_INTR_RTC_LSB _u(0) -#define RTC_INTR_RTC_ACCESS "RO" -// ============================================================================= -// Register : RTC_INTE -// Description : Interrupt Enable -#define RTC_INTE_OFFSET _u(0x00000024) -#define RTC_INTE_BITS _u(0x00000001) -#define RTC_INTE_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : RTC_INTE_RTC -#define RTC_INTE_RTC_RESET _u(0x0) -#define RTC_INTE_RTC_BITS _u(0x00000001) -#define RTC_INTE_RTC_MSB _u(0) -#define RTC_INTE_RTC_LSB _u(0) -#define RTC_INTE_RTC_ACCESS "RW" -// ============================================================================= -// Register : RTC_INTF -// Description : Interrupt Force -#define RTC_INTF_OFFSET _u(0x00000028) -#define RTC_INTF_BITS _u(0x00000001) -#define RTC_INTF_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : RTC_INTF_RTC -#define RTC_INTF_RTC_RESET _u(0x0) -#define RTC_INTF_RTC_BITS _u(0x00000001) -#define RTC_INTF_RTC_MSB _u(0) -#define RTC_INTF_RTC_LSB _u(0) -#define RTC_INTF_RTC_ACCESS "RW" -// ============================================================================= -// Register : RTC_INTS -// Description : Interrupt status after masking & forcing -#define RTC_INTS_OFFSET _u(0x0000002c) -#define RTC_INTS_BITS _u(0x00000001) -#define RTC_INTS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : RTC_INTS_RTC -#define RTC_INTS_RTC_RESET _u(0x0) -#define RTC_INTS_RTC_BITS _u(0x00000001) -#define RTC_INTS_RTC_MSB _u(0) -#define RTC_INTS_RTC_LSB _u(0) -#define RTC_INTS_RTC_ACCESS "RO" -// ============================================================================= -#endif // _HARDWARE_REGS_RTC_H - diff --git a/lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/sio.h b/lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/sio.h deleted file mode 100644 index 2d720e9279..0000000000 --- a/lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/sio.h +++ /dev/null @@ -1,1659 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -// ============================================================================= -// Register block : SIO -// Version : 1 -// Bus type : apb -// Description : Single-cycle IO block -// Provides core-local and inter-core hardware for the two -// processors, with single-cycle access. -// ============================================================================= -#ifndef _HARDWARE_REGS_SIO_H -#define _HARDWARE_REGS_SIO_H -// ============================================================================= -// Register : SIO_CPUID -// Description : Processor core identifier -// Value is 0 when read from processor core 0, and 1 when read -// from processor core 1. -#define SIO_CPUID_OFFSET _u(0x00000000) -#define SIO_CPUID_BITS _u(0xffffffff) -#define SIO_CPUID_RESET "-" -#define SIO_CPUID_MSB _u(31) -#define SIO_CPUID_LSB _u(0) -#define SIO_CPUID_ACCESS "RO" -// ============================================================================= -// Register : SIO_GPIO_IN -// Description : Input value for GPIO pins -// Input value for GPIO0...29 -#define SIO_GPIO_IN_OFFSET _u(0x00000004) -#define SIO_GPIO_IN_BITS _u(0x3fffffff) -#define SIO_GPIO_IN_RESET _u(0x00000000) -#define SIO_GPIO_IN_MSB _u(29) -#define SIO_GPIO_IN_LSB _u(0) -#define SIO_GPIO_IN_ACCESS "RO" -// ============================================================================= -// Register : SIO_GPIO_HI_IN -// Description : Input value for QSPI pins -// Input value on QSPI IO in order 0..5: SCLK, SSn, SD0, SD1, SD2, -// SD3 -#define SIO_GPIO_HI_IN_OFFSET _u(0x00000008) -#define SIO_GPIO_HI_IN_BITS _u(0x0000003f) -#define SIO_GPIO_HI_IN_RESET _u(0x00000000) -#define SIO_GPIO_HI_IN_MSB _u(5) -#define SIO_GPIO_HI_IN_LSB _u(0) -#define SIO_GPIO_HI_IN_ACCESS "RO" -// ============================================================================= -// Register : SIO_GPIO_OUT -// Description : GPIO output value -// Set output level (1/0 -> high/low) for GPIO0...29. -// Reading back gives the last value written, NOT the input value -// from the pins. -// If core 0 and core 1 both write to GPIO_OUT simultaneously (or -// to a SET/CLR/XOR alias), -// the result is as though the write from core 0 took place first, -// and the write from core 1 was then applied to that intermediate -// result. -#define SIO_GPIO_OUT_OFFSET _u(0x00000010) -#define SIO_GPIO_OUT_BITS _u(0x3fffffff) -#define SIO_GPIO_OUT_RESET _u(0x00000000) -#define SIO_GPIO_OUT_MSB _u(29) -#define SIO_GPIO_OUT_LSB _u(0) -#define SIO_GPIO_OUT_ACCESS "RW" -// ============================================================================= -// Register : SIO_GPIO_OUT_SET -// Description : GPIO output value set -// Perform an atomic bit-set on GPIO_OUT, i.e. `GPIO_OUT |= wdata` -#define SIO_GPIO_OUT_SET_OFFSET _u(0x00000014) -#define SIO_GPIO_OUT_SET_BITS _u(0x3fffffff) -#define SIO_GPIO_OUT_SET_RESET _u(0x00000000) -#define SIO_GPIO_OUT_SET_MSB _u(29) -#define SIO_GPIO_OUT_SET_LSB _u(0) -#define SIO_GPIO_OUT_SET_ACCESS "WO" -// ============================================================================= -// Register : SIO_GPIO_OUT_CLR -// Description : GPIO output value clear -// Perform an atomic bit-clear on GPIO_OUT, i.e. `GPIO_OUT &= -// ~wdata` -#define SIO_GPIO_OUT_CLR_OFFSET _u(0x00000018) -#define SIO_GPIO_OUT_CLR_BITS _u(0x3fffffff) -#define SIO_GPIO_OUT_CLR_RESET _u(0x00000000) -#define SIO_GPIO_OUT_CLR_MSB _u(29) -#define SIO_GPIO_OUT_CLR_LSB _u(0) -#define SIO_GPIO_OUT_CLR_ACCESS "WO" -// ============================================================================= -// Register : SIO_GPIO_OUT_XOR -// Description : GPIO output value XOR -// Perform an atomic bitwise XOR on GPIO_OUT, i.e. `GPIO_OUT ^= -// wdata` -#define SIO_GPIO_OUT_XOR_OFFSET _u(0x0000001c) -#define SIO_GPIO_OUT_XOR_BITS _u(0x3fffffff) -#define SIO_GPIO_OUT_XOR_RESET _u(0x00000000) -#define SIO_GPIO_OUT_XOR_MSB _u(29) -#define SIO_GPIO_OUT_XOR_LSB _u(0) -#define SIO_GPIO_OUT_XOR_ACCESS "WO" -// ============================================================================= -// Register : SIO_GPIO_OE -// Description : GPIO output enable -// Set output enable (1/0 -> output/input) for GPIO0...29. -// Reading back gives the last value written. -// If core 0 and core 1 both write to GPIO_OE simultaneously (or -// to a SET/CLR/XOR alias), -// the result is as though the write from core 0 took place first, -// and the write from core 1 was then applied to that intermediate -// result. -#define SIO_GPIO_OE_OFFSET _u(0x00000020) -#define SIO_GPIO_OE_BITS _u(0x3fffffff) -#define SIO_GPIO_OE_RESET _u(0x00000000) -#define SIO_GPIO_OE_MSB _u(29) -#define SIO_GPIO_OE_LSB _u(0) -#define SIO_GPIO_OE_ACCESS "RW" -// ============================================================================= -// Register : SIO_GPIO_OE_SET -// Description : GPIO output enable set -// Perform an atomic bit-set on GPIO_OE, i.e. `GPIO_OE |= wdata` -#define SIO_GPIO_OE_SET_OFFSET _u(0x00000024) -#define SIO_GPIO_OE_SET_BITS _u(0x3fffffff) -#define SIO_GPIO_OE_SET_RESET _u(0x00000000) -#define SIO_GPIO_OE_SET_MSB _u(29) -#define SIO_GPIO_OE_SET_LSB _u(0) -#define SIO_GPIO_OE_SET_ACCESS "WO" -// ============================================================================= -// Register : SIO_GPIO_OE_CLR -// Description : GPIO output enable clear -// Perform an atomic bit-clear on GPIO_OE, i.e. `GPIO_OE &= -// ~wdata` -#define SIO_GPIO_OE_CLR_OFFSET _u(0x00000028) -#define SIO_GPIO_OE_CLR_BITS _u(0x3fffffff) -#define SIO_GPIO_OE_CLR_RESET _u(0x00000000) -#define SIO_GPIO_OE_CLR_MSB _u(29) -#define SIO_GPIO_OE_CLR_LSB _u(0) -#define SIO_GPIO_OE_CLR_ACCESS "WO" -// ============================================================================= -// Register : SIO_GPIO_OE_XOR -// Description : GPIO output enable XOR -// Perform an atomic bitwise XOR on GPIO_OE, i.e. `GPIO_OE ^= -// wdata` -#define SIO_GPIO_OE_XOR_OFFSET _u(0x0000002c) -#define SIO_GPIO_OE_XOR_BITS _u(0x3fffffff) -#define SIO_GPIO_OE_XOR_RESET _u(0x00000000) -#define SIO_GPIO_OE_XOR_MSB _u(29) -#define SIO_GPIO_OE_XOR_LSB _u(0) -#define SIO_GPIO_OE_XOR_ACCESS "WO" -// ============================================================================= -// Register : SIO_GPIO_HI_OUT -// Description : QSPI output value -// Set output level (1/0 -> high/low) for QSPI IO0...5. -// Reading back gives the last value written, NOT the input value -// from the pins. -// If core 0 and core 1 both write to GPIO_HI_OUT simultaneously -// (or to a SET/CLR/XOR alias), -// the result is as though the write from core 0 took place first, -// and the write from core 1 was then applied to that intermediate -// result. -#define SIO_GPIO_HI_OUT_OFFSET _u(0x00000030) -#define SIO_GPIO_HI_OUT_BITS _u(0x0000003f) -#define SIO_GPIO_HI_OUT_RESET _u(0x00000000) -#define SIO_GPIO_HI_OUT_MSB _u(5) -#define SIO_GPIO_HI_OUT_LSB _u(0) -#define SIO_GPIO_HI_OUT_ACCESS "RW" -// ============================================================================= -// Register : SIO_GPIO_HI_OUT_SET -// Description : QSPI output value set -// Perform an atomic bit-set on GPIO_HI_OUT, i.e. `GPIO_HI_OUT |= -// wdata` -#define SIO_GPIO_HI_OUT_SET_OFFSET _u(0x00000034) -#define SIO_GPIO_HI_OUT_SET_BITS _u(0x0000003f) -#define SIO_GPIO_HI_OUT_SET_RESET _u(0x00000000) -#define SIO_GPIO_HI_OUT_SET_MSB _u(5) -#define SIO_GPIO_HI_OUT_SET_LSB _u(0) -#define SIO_GPIO_HI_OUT_SET_ACCESS "WO" -// ============================================================================= -// Register : SIO_GPIO_HI_OUT_CLR -// Description : QSPI output value clear -// Perform an atomic bit-clear on GPIO_HI_OUT, i.e. `GPIO_HI_OUT -// &= ~wdata` -#define SIO_GPIO_HI_OUT_CLR_OFFSET _u(0x00000038) -#define SIO_GPIO_HI_OUT_CLR_BITS _u(0x0000003f) -#define SIO_GPIO_HI_OUT_CLR_RESET _u(0x00000000) -#define SIO_GPIO_HI_OUT_CLR_MSB _u(5) -#define SIO_GPIO_HI_OUT_CLR_LSB _u(0) -#define SIO_GPIO_HI_OUT_CLR_ACCESS "WO" -// ============================================================================= -// Register : SIO_GPIO_HI_OUT_XOR -// Description : QSPI output value XOR -// Perform an atomic bitwise XOR on GPIO_HI_OUT, i.e. `GPIO_HI_OUT -// ^= wdata` -#define SIO_GPIO_HI_OUT_XOR_OFFSET _u(0x0000003c) -#define SIO_GPIO_HI_OUT_XOR_BITS _u(0x0000003f) -#define SIO_GPIO_HI_OUT_XOR_RESET _u(0x00000000) -#define SIO_GPIO_HI_OUT_XOR_MSB _u(5) -#define SIO_GPIO_HI_OUT_XOR_LSB _u(0) -#define SIO_GPIO_HI_OUT_XOR_ACCESS "WO" -// ============================================================================= -// Register : SIO_GPIO_HI_OE -// Description : QSPI output enable -// Set output enable (1/0 -> output/input) for QSPI IO0...5. -// Reading back gives the last value written. -// If core 0 and core 1 both write to GPIO_HI_OE simultaneously -// (or to a SET/CLR/XOR alias), -// the result is as though the write from core 0 took place first, -// and the write from core 1 was then applied to that intermediate -// result. -#define SIO_GPIO_HI_OE_OFFSET _u(0x00000040) -#define SIO_GPIO_HI_OE_BITS _u(0x0000003f) -#define SIO_GPIO_HI_OE_RESET _u(0x00000000) -#define SIO_GPIO_HI_OE_MSB _u(5) -#define SIO_GPIO_HI_OE_LSB _u(0) -#define SIO_GPIO_HI_OE_ACCESS "RW" -// ============================================================================= -// Register : SIO_GPIO_HI_OE_SET -// Description : QSPI output enable set -// Perform an atomic bit-set on GPIO_HI_OE, i.e. `GPIO_HI_OE |= -// wdata` -#define SIO_GPIO_HI_OE_SET_OFFSET _u(0x00000044) -#define SIO_GPIO_HI_OE_SET_BITS _u(0x0000003f) -#define SIO_GPIO_HI_OE_SET_RESET _u(0x00000000) -#define SIO_GPIO_HI_OE_SET_MSB _u(5) -#define SIO_GPIO_HI_OE_SET_LSB _u(0) -#define SIO_GPIO_HI_OE_SET_ACCESS "WO" -// ============================================================================= -// Register : SIO_GPIO_HI_OE_CLR -// Description : QSPI output enable clear -// Perform an atomic bit-clear on GPIO_HI_OE, i.e. `GPIO_HI_OE &= -// ~wdata` -#define SIO_GPIO_HI_OE_CLR_OFFSET _u(0x00000048) -#define SIO_GPIO_HI_OE_CLR_BITS _u(0x0000003f) -#define SIO_GPIO_HI_OE_CLR_RESET _u(0x00000000) -#define SIO_GPIO_HI_OE_CLR_MSB _u(5) -#define SIO_GPIO_HI_OE_CLR_LSB _u(0) -#define SIO_GPIO_HI_OE_CLR_ACCESS "WO" -// ============================================================================= -// Register : SIO_GPIO_HI_OE_XOR -// Description : QSPI output enable XOR -// Perform an atomic bitwise XOR on GPIO_HI_OE, i.e. `GPIO_HI_OE -// ^= wdata` -#define SIO_GPIO_HI_OE_XOR_OFFSET _u(0x0000004c) -#define SIO_GPIO_HI_OE_XOR_BITS _u(0x0000003f) -#define SIO_GPIO_HI_OE_XOR_RESET _u(0x00000000) -#define SIO_GPIO_HI_OE_XOR_MSB _u(5) -#define SIO_GPIO_HI_OE_XOR_LSB _u(0) -#define SIO_GPIO_HI_OE_XOR_ACCESS "WO" -// ============================================================================= -// Register : SIO_FIFO_ST -// Description : Status register for inter-core FIFOs (mailboxes). -// There is one FIFO in the core 0 -> core 1 direction, and one -// core 1 -> core 0. Both are 32 bits wide and 8 words deep. -// Core 0 can see the read side of the 1->0 FIFO (RX), and the -// write side of 0->1 FIFO (TX). -// Core 1 can see the read side of the 0->1 FIFO (RX), and the -// write side of 1->0 FIFO (TX). -// The SIO IRQ for each core is the logical OR of the VLD, WOF and -// ROE fields of its FIFO_ST register. -#define SIO_FIFO_ST_OFFSET _u(0x00000050) -#define SIO_FIFO_ST_BITS _u(0x0000000f) -#define SIO_FIFO_ST_RESET _u(0x00000002) -// ----------------------------------------------------------------------------- -// Field : SIO_FIFO_ST_ROE -// Description : Sticky flag indicating the RX FIFO was read when empty. This -// read was ignored by the FIFO. -#define SIO_FIFO_ST_ROE_RESET _u(0x0) -#define SIO_FIFO_ST_ROE_BITS _u(0x00000008) -#define SIO_FIFO_ST_ROE_MSB _u(3) -#define SIO_FIFO_ST_ROE_LSB _u(3) -#define SIO_FIFO_ST_ROE_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : SIO_FIFO_ST_WOF -// Description : Sticky flag indicating the TX FIFO was written when full. This -// write was ignored by the FIFO. -#define SIO_FIFO_ST_WOF_RESET _u(0x0) -#define SIO_FIFO_ST_WOF_BITS _u(0x00000004) -#define SIO_FIFO_ST_WOF_MSB _u(2) -#define SIO_FIFO_ST_WOF_LSB _u(2) -#define SIO_FIFO_ST_WOF_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : SIO_FIFO_ST_RDY -// Description : Value is 1 if this core's TX FIFO is not full (i.e. if FIFO_WR -// is ready for more data) -#define SIO_FIFO_ST_RDY_RESET _u(0x1) -#define SIO_FIFO_ST_RDY_BITS _u(0x00000002) -#define SIO_FIFO_ST_RDY_MSB _u(1) -#define SIO_FIFO_ST_RDY_LSB _u(1) -#define SIO_FIFO_ST_RDY_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : SIO_FIFO_ST_VLD -// Description : Value is 1 if this core's RX FIFO is not empty (i.e. if FIFO_RD -// is valid) -#define SIO_FIFO_ST_VLD_RESET _u(0x0) -#define SIO_FIFO_ST_VLD_BITS _u(0x00000001) -#define SIO_FIFO_ST_VLD_MSB _u(0) -#define SIO_FIFO_ST_VLD_LSB _u(0) -#define SIO_FIFO_ST_VLD_ACCESS "RO" -// ============================================================================= -// Register : SIO_FIFO_WR -// Description : Write access to this core's TX FIFO -#define SIO_FIFO_WR_OFFSET _u(0x00000054) -#define SIO_FIFO_WR_BITS _u(0xffffffff) -#define SIO_FIFO_WR_RESET _u(0x00000000) -#define SIO_FIFO_WR_MSB _u(31) -#define SIO_FIFO_WR_LSB _u(0) -#define SIO_FIFO_WR_ACCESS "WF" -// ============================================================================= -// Register : SIO_FIFO_RD -// Description : Read access to this core's RX FIFO -#define SIO_FIFO_RD_OFFSET _u(0x00000058) -#define SIO_FIFO_RD_BITS _u(0xffffffff) -#define SIO_FIFO_RD_RESET "-" -#define SIO_FIFO_RD_MSB _u(31) -#define SIO_FIFO_RD_LSB _u(0) -#define SIO_FIFO_RD_ACCESS "RF" -// ============================================================================= -// Register : SIO_SPINLOCK_ST -// Description : Spinlock state -// A bitmap containing the state of all 32 spinlocks (1=locked). -// Mainly intended for debugging. -#define SIO_SPINLOCK_ST_OFFSET _u(0x0000005c) -#define SIO_SPINLOCK_ST_BITS _u(0xffffffff) -#define SIO_SPINLOCK_ST_RESET _u(0x00000000) -#define SIO_SPINLOCK_ST_MSB _u(31) -#define SIO_SPINLOCK_ST_LSB _u(0) -#define SIO_SPINLOCK_ST_ACCESS "RO" -// ============================================================================= -// Register : SIO_DIV_UDIVIDEND -// Description : Divider unsigned dividend -// Write to the DIVIDEND operand of the divider, i.e. the p in `p -// / q`. -// Any operand write starts a new calculation. The results appear -// in QUOTIENT, REMAINDER. -// UDIVIDEND/SDIVIDEND are aliases of the same internal register. -// The U alias starts an -// unsigned calculation, and the S alias starts a signed -// calculation. -#define SIO_DIV_UDIVIDEND_OFFSET _u(0x00000060) -#define SIO_DIV_UDIVIDEND_BITS _u(0xffffffff) -#define SIO_DIV_UDIVIDEND_RESET _u(0x00000000) -#define SIO_DIV_UDIVIDEND_MSB _u(31) -#define SIO_DIV_UDIVIDEND_LSB _u(0) -#define SIO_DIV_UDIVIDEND_ACCESS "RW" -// ============================================================================= -// Register : SIO_DIV_UDIVISOR -// Description : Divider unsigned divisor -// Write to the DIVISOR operand of the divider, i.e. the q in `p / -// q`. -// Any operand write starts a new calculation. The results appear -// in QUOTIENT, REMAINDER. -// UDIVISOR/SDIVISOR are aliases of the same internal register. -// The U alias starts an -// unsigned calculation, and the S alias starts a signed -// calculation. -#define SIO_DIV_UDIVISOR_OFFSET _u(0x00000064) -#define SIO_DIV_UDIVISOR_BITS _u(0xffffffff) -#define SIO_DIV_UDIVISOR_RESET _u(0x00000000) -#define SIO_DIV_UDIVISOR_MSB _u(31) -#define SIO_DIV_UDIVISOR_LSB _u(0) -#define SIO_DIV_UDIVISOR_ACCESS "RW" -// ============================================================================= -// Register : SIO_DIV_SDIVIDEND -// Description : Divider signed dividend -// The same as UDIVIDEND, but starts a signed calculation, rather -// than unsigned. -#define SIO_DIV_SDIVIDEND_OFFSET _u(0x00000068) -#define SIO_DIV_SDIVIDEND_BITS _u(0xffffffff) -#define SIO_DIV_SDIVIDEND_RESET _u(0x00000000) -#define SIO_DIV_SDIVIDEND_MSB _u(31) -#define SIO_DIV_SDIVIDEND_LSB _u(0) -#define SIO_DIV_SDIVIDEND_ACCESS "RW" -// ============================================================================= -// Register : SIO_DIV_SDIVISOR -// Description : Divider signed divisor -// The same as UDIVISOR, but starts a signed calculation, rather -// than unsigned. -#define SIO_DIV_SDIVISOR_OFFSET _u(0x0000006c) -#define SIO_DIV_SDIVISOR_BITS _u(0xffffffff) -#define SIO_DIV_SDIVISOR_RESET _u(0x00000000) -#define SIO_DIV_SDIVISOR_MSB _u(31) -#define SIO_DIV_SDIVISOR_LSB _u(0) -#define SIO_DIV_SDIVISOR_ACCESS "RW" -// ============================================================================= -// Register : SIO_DIV_QUOTIENT -// Description : Divider result quotient -// The result of `DIVIDEND / DIVISOR` (division). Contents -// undefined while CSR_READY is low. -// For signed calculations, QUOTIENT is negative when the signs of -// DIVIDEND and DIVISOR differ. -// This register can be written to directly, for context -// save/restore purposes. This halts any -// in-progress calculation and sets the CSR_READY and CSR_DIRTY -// flags. -// Reading from QUOTIENT clears the CSR_DIRTY flag, so should read -// results in the order -// REMAINDER, QUOTIENT if CSR_DIRTY is used. -#define SIO_DIV_QUOTIENT_OFFSET _u(0x00000070) -#define SIO_DIV_QUOTIENT_BITS _u(0xffffffff) -#define SIO_DIV_QUOTIENT_RESET _u(0x00000000) -#define SIO_DIV_QUOTIENT_MSB _u(31) -#define SIO_DIV_QUOTIENT_LSB _u(0) -#define SIO_DIV_QUOTIENT_ACCESS "RW" -// ============================================================================= -// Register : SIO_DIV_REMAINDER -// Description : Divider result remainder -// The result of `DIVIDEND % DIVISOR` (modulo). Contents undefined -// while CSR_READY is low. -// For signed calculations, REMAINDER is negative only when -// DIVIDEND is negative. -// This register can be written to directly, for context -// save/restore purposes. This halts any -// in-progress calculation and sets the CSR_READY and CSR_DIRTY -// flags. -#define SIO_DIV_REMAINDER_OFFSET _u(0x00000074) -#define SIO_DIV_REMAINDER_BITS _u(0xffffffff) -#define SIO_DIV_REMAINDER_RESET _u(0x00000000) -#define SIO_DIV_REMAINDER_MSB _u(31) -#define SIO_DIV_REMAINDER_LSB _u(0) -#define SIO_DIV_REMAINDER_ACCESS "RW" -// ============================================================================= -// Register : SIO_DIV_CSR -// Description : Control and status register for divider. -#define SIO_DIV_CSR_OFFSET _u(0x00000078) -#define SIO_DIV_CSR_BITS _u(0x00000003) -#define SIO_DIV_CSR_RESET _u(0x00000001) -// ----------------------------------------------------------------------------- -// Field : SIO_DIV_CSR_DIRTY -// Description : Changes to 1 when any register is written, and back to 0 when -// QUOTIENT is read. -// Software can use this flag to make save/restore more efficient -// (skip if not DIRTY). -// If the flag is used in this way, it's recommended to either -// read QUOTIENT only, -// or REMAINDER and then QUOTIENT, to prevent data loss on context -// switch. -#define SIO_DIV_CSR_DIRTY_RESET _u(0x0) -#define SIO_DIV_CSR_DIRTY_BITS _u(0x00000002) -#define SIO_DIV_CSR_DIRTY_MSB _u(1) -#define SIO_DIV_CSR_DIRTY_LSB _u(1) -#define SIO_DIV_CSR_DIRTY_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : SIO_DIV_CSR_READY -// Description : Reads as 0 when a calculation is in progress, 1 otherwise. -// Writing an operand (xDIVIDEND, xDIVISOR) will immediately start -// a new calculation, no -// matter if one is already in progress. -// Writing to a result register will immediately terminate any in- -// progress calculation -// and set the READY and DIRTY flags. -#define SIO_DIV_CSR_READY_RESET _u(0x1) -#define SIO_DIV_CSR_READY_BITS _u(0x00000001) -#define SIO_DIV_CSR_READY_MSB _u(0) -#define SIO_DIV_CSR_READY_LSB _u(0) -#define SIO_DIV_CSR_READY_ACCESS "RO" -// ============================================================================= -// Register : SIO_INTERP0_ACCUM0 -// Description : Read/write access to accumulator 0 -#define SIO_INTERP0_ACCUM0_OFFSET _u(0x00000080) -#define SIO_INTERP0_ACCUM0_BITS _u(0xffffffff) -#define SIO_INTERP0_ACCUM0_RESET _u(0x00000000) -#define SIO_INTERP0_ACCUM0_MSB _u(31) -#define SIO_INTERP0_ACCUM0_LSB _u(0) -#define SIO_INTERP0_ACCUM0_ACCESS "RW" -// ============================================================================= -// Register : SIO_INTERP0_ACCUM1 -// Description : Read/write access to accumulator 1 -#define SIO_INTERP0_ACCUM1_OFFSET _u(0x00000084) -#define SIO_INTERP0_ACCUM1_BITS _u(0xffffffff) -#define SIO_INTERP0_ACCUM1_RESET _u(0x00000000) -#define SIO_INTERP0_ACCUM1_MSB _u(31) -#define SIO_INTERP0_ACCUM1_LSB _u(0) -#define SIO_INTERP0_ACCUM1_ACCESS "RW" -// ============================================================================= -// Register : SIO_INTERP0_BASE0 -// Description : Read/write access to BASE0 register. -#define SIO_INTERP0_BASE0_OFFSET _u(0x00000088) -#define SIO_INTERP0_BASE0_BITS _u(0xffffffff) -#define SIO_INTERP0_BASE0_RESET _u(0x00000000) -#define SIO_INTERP0_BASE0_MSB _u(31) -#define SIO_INTERP0_BASE0_LSB _u(0) -#define SIO_INTERP0_BASE0_ACCESS "RW" -// ============================================================================= -// Register : SIO_INTERP0_BASE1 -// Description : Read/write access to BASE1 register. -#define SIO_INTERP0_BASE1_OFFSET _u(0x0000008c) -#define SIO_INTERP0_BASE1_BITS _u(0xffffffff) -#define SIO_INTERP0_BASE1_RESET _u(0x00000000) -#define SIO_INTERP0_BASE1_MSB _u(31) -#define SIO_INTERP0_BASE1_LSB _u(0) -#define SIO_INTERP0_BASE1_ACCESS "RW" -// ============================================================================= -// Register : SIO_INTERP0_BASE2 -// Description : Read/write access to BASE2 register. -#define SIO_INTERP0_BASE2_OFFSET _u(0x00000090) -#define SIO_INTERP0_BASE2_BITS _u(0xffffffff) -#define SIO_INTERP0_BASE2_RESET _u(0x00000000) -#define SIO_INTERP0_BASE2_MSB _u(31) -#define SIO_INTERP0_BASE2_LSB _u(0) -#define SIO_INTERP0_BASE2_ACCESS "RW" -// ============================================================================= -// Register : SIO_INTERP0_POP_LANE0 -// Description : Read LANE0 result, and simultaneously write lane results to -// both accumulators (POP). -#define SIO_INTERP0_POP_LANE0_OFFSET _u(0x00000094) -#define SIO_INTERP0_POP_LANE0_BITS _u(0xffffffff) -#define SIO_INTERP0_POP_LANE0_RESET _u(0x00000000) -#define SIO_INTERP0_POP_LANE0_MSB _u(31) -#define SIO_INTERP0_POP_LANE0_LSB _u(0) -#define SIO_INTERP0_POP_LANE0_ACCESS "RO" -// ============================================================================= -// Register : SIO_INTERP0_POP_LANE1 -// Description : Read LANE1 result, and simultaneously write lane results to -// both accumulators (POP). -#define SIO_INTERP0_POP_LANE1_OFFSET _u(0x00000098) -#define SIO_INTERP0_POP_LANE1_BITS _u(0xffffffff) -#define SIO_INTERP0_POP_LANE1_RESET _u(0x00000000) -#define SIO_INTERP0_POP_LANE1_MSB _u(31) -#define SIO_INTERP0_POP_LANE1_LSB _u(0) -#define SIO_INTERP0_POP_LANE1_ACCESS "RO" -// ============================================================================= -// Register : SIO_INTERP0_POP_FULL -// Description : Read FULL result, and simultaneously write lane results to both -// accumulators (POP). -#define SIO_INTERP0_POP_FULL_OFFSET _u(0x0000009c) -#define SIO_INTERP0_POP_FULL_BITS _u(0xffffffff) -#define SIO_INTERP0_POP_FULL_RESET _u(0x00000000) -#define SIO_INTERP0_POP_FULL_MSB _u(31) -#define SIO_INTERP0_POP_FULL_LSB _u(0) -#define SIO_INTERP0_POP_FULL_ACCESS "RO" -// ============================================================================= -// Register : SIO_INTERP0_PEEK_LANE0 -// Description : Read LANE0 result, without altering any internal state (PEEK). -#define SIO_INTERP0_PEEK_LANE0_OFFSET _u(0x000000a0) -#define SIO_INTERP0_PEEK_LANE0_BITS _u(0xffffffff) -#define SIO_INTERP0_PEEK_LANE0_RESET _u(0x00000000) -#define SIO_INTERP0_PEEK_LANE0_MSB _u(31) -#define SIO_INTERP0_PEEK_LANE0_LSB _u(0) -#define SIO_INTERP0_PEEK_LANE0_ACCESS "RO" -// ============================================================================= -// Register : SIO_INTERP0_PEEK_LANE1 -// Description : Read LANE1 result, without altering any internal state (PEEK). -#define SIO_INTERP0_PEEK_LANE1_OFFSET _u(0x000000a4) -#define SIO_INTERP0_PEEK_LANE1_BITS _u(0xffffffff) -#define SIO_INTERP0_PEEK_LANE1_RESET _u(0x00000000) -#define SIO_INTERP0_PEEK_LANE1_MSB _u(31) -#define SIO_INTERP0_PEEK_LANE1_LSB _u(0) -#define SIO_INTERP0_PEEK_LANE1_ACCESS "RO" -// ============================================================================= -// Register : SIO_INTERP0_PEEK_FULL -// Description : Read FULL result, without altering any internal state (PEEK). -#define SIO_INTERP0_PEEK_FULL_OFFSET _u(0x000000a8) -#define SIO_INTERP0_PEEK_FULL_BITS _u(0xffffffff) -#define SIO_INTERP0_PEEK_FULL_RESET _u(0x00000000) -#define SIO_INTERP0_PEEK_FULL_MSB _u(31) -#define SIO_INTERP0_PEEK_FULL_LSB _u(0) -#define SIO_INTERP0_PEEK_FULL_ACCESS "RO" -// ============================================================================= -// Register : SIO_INTERP0_CTRL_LANE0 -// Description : Control register for lane 0 -#define SIO_INTERP0_CTRL_LANE0_OFFSET _u(0x000000ac) -#define SIO_INTERP0_CTRL_LANE0_BITS _u(0x03bfffff) -#define SIO_INTERP0_CTRL_LANE0_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : SIO_INTERP0_CTRL_LANE0_OVERF -// Description : Set if either OVERF0 or OVERF1 is set. -#define SIO_INTERP0_CTRL_LANE0_OVERF_RESET _u(0x0) -#define SIO_INTERP0_CTRL_LANE0_OVERF_BITS _u(0x02000000) -#define SIO_INTERP0_CTRL_LANE0_OVERF_MSB _u(25) -#define SIO_INTERP0_CTRL_LANE0_OVERF_LSB _u(25) -#define SIO_INTERP0_CTRL_LANE0_OVERF_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : SIO_INTERP0_CTRL_LANE0_OVERF1 -// Description : Indicates if any masked-off MSBs in ACCUM1 are set. -#define SIO_INTERP0_CTRL_LANE0_OVERF1_RESET _u(0x0) -#define SIO_INTERP0_CTRL_LANE0_OVERF1_BITS _u(0x01000000) -#define SIO_INTERP0_CTRL_LANE0_OVERF1_MSB _u(24) -#define SIO_INTERP0_CTRL_LANE0_OVERF1_LSB _u(24) -#define SIO_INTERP0_CTRL_LANE0_OVERF1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : SIO_INTERP0_CTRL_LANE0_OVERF0 -// Description : Indicates if any masked-off MSBs in ACCUM0 are set. -#define SIO_INTERP0_CTRL_LANE0_OVERF0_RESET _u(0x0) -#define SIO_INTERP0_CTRL_LANE0_OVERF0_BITS _u(0x00800000) -#define SIO_INTERP0_CTRL_LANE0_OVERF0_MSB _u(23) -#define SIO_INTERP0_CTRL_LANE0_OVERF0_LSB _u(23) -#define SIO_INTERP0_CTRL_LANE0_OVERF0_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : SIO_INTERP0_CTRL_LANE0_BLEND -// Description : Only present on INTERP0 on each core. If BLEND mode is enabled: -// - LANE1 result is a linear interpolation between BASE0 and -// BASE1, controlled -// by the 8 LSBs of lane 1 shift and mask value (a fractional -// number between -// 0 and 255/256ths) -// - LANE0 result does not have BASE0 added (yields only the 8 -// LSBs of lane 1 shift+mask value) -// - FULL result does not have lane 1 shift+mask value added -// (BASE2 + lane 0 shift+mask) -// LANE1 SIGNED flag controls whether the interpolation is signed -// or unsigned. -#define SIO_INTERP0_CTRL_LANE0_BLEND_RESET _u(0x0) -#define SIO_INTERP0_CTRL_LANE0_BLEND_BITS _u(0x00200000) -#define SIO_INTERP0_CTRL_LANE0_BLEND_MSB _u(21) -#define SIO_INTERP0_CTRL_LANE0_BLEND_LSB _u(21) -#define SIO_INTERP0_CTRL_LANE0_BLEND_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SIO_INTERP0_CTRL_LANE0_FORCE_MSB -// Description : ORed into bits 29:28 of the lane result presented to the -// processor on the bus. -// No effect on the internal 32-bit datapath. Handy for using a -// lane to generate sequence -// of pointers into flash or SRAM. -#define SIO_INTERP0_CTRL_LANE0_FORCE_MSB_RESET _u(0x0) -#define SIO_INTERP0_CTRL_LANE0_FORCE_MSB_BITS _u(0x00180000) -#define SIO_INTERP0_CTRL_LANE0_FORCE_MSB_MSB _u(20) -#define SIO_INTERP0_CTRL_LANE0_FORCE_MSB_LSB _u(19) -#define SIO_INTERP0_CTRL_LANE0_FORCE_MSB_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SIO_INTERP0_CTRL_LANE0_ADD_RAW -// Description : If 1, mask + shift is bypassed for LANE0 result. This does not -// affect FULL result. -#define SIO_INTERP0_CTRL_LANE0_ADD_RAW_RESET _u(0x0) -#define SIO_INTERP0_CTRL_LANE0_ADD_RAW_BITS _u(0x00040000) -#define SIO_INTERP0_CTRL_LANE0_ADD_RAW_MSB _u(18) -#define SIO_INTERP0_CTRL_LANE0_ADD_RAW_LSB _u(18) -#define SIO_INTERP0_CTRL_LANE0_ADD_RAW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SIO_INTERP0_CTRL_LANE0_CROSS_RESULT -// Description : If 1, feed the opposite lane's result into this lane's -// accumulator on POP. -#define SIO_INTERP0_CTRL_LANE0_CROSS_RESULT_RESET _u(0x0) -#define SIO_INTERP0_CTRL_LANE0_CROSS_RESULT_BITS _u(0x00020000) -#define SIO_INTERP0_CTRL_LANE0_CROSS_RESULT_MSB _u(17) -#define SIO_INTERP0_CTRL_LANE0_CROSS_RESULT_LSB _u(17) -#define SIO_INTERP0_CTRL_LANE0_CROSS_RESULT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SIO_INTERP0_CTRL_LANE0_CROSS_INPUT -// Description : If 1, feed the opposite lane's accumulator into this lane's -// shift + mask hardware. -// Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is -// before the shift+mask bypass) -#define SIO_INTERP0_CTRL_LANE0_CROSS_INPUT_RESET _u(0x0) -#define SIO_INTERP0_CTRL_LANE0_CROSS_INPUT_BITS _u(0x00010000) -#define SIO_INTERP0_CTRL_LANE0_CROSS_INPUT_MSB _u(16) -#define SIO_INTERP0_CTRL_LANE0_CROSS_INPUT_LSB _u(16) -#define SIO_INTERP0_CTRL_LANE0_CROSS_INPUT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SIO_INTERP0_CTRL_LANE0_SIGNED -// Description : If SIGNED is set, the shifted and masked accumulator value is -// sign-extended to 32 bits -// before adding to BASE0, and LANE0 PEEK/POP appear extended to -// 32 bits when read by processor. -#define SIO_INTERP0_CTRL_LANE0_SIGNED_RESET _u(0x0) -#define SIO_INTERP0_CTRL_LANE0_SIGNED_BITS _u(0x00008000) -#define SIO_INTERP0_CTRL_LANE0_SIGNED_MSB _u(15) -#define SIO_INTERP0_CTRL_LANE0_SIGNED_LSB _u(15) -#define SIO_INTERP0_CTRL_LANE0_SIGNED_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SIO_INTERP0_CTRL_LANE0_MASK_MSB -// Description : The most-significant bit allowed to pass by the mask -// (inclusive) -// Setting MSB < LSB may cause chip to turn inside-out -#define SIO_INTERP0_CTRL_LANE0_MASK_MSB_RESET _u(0x00) -#define SIO_INTERP0_CTRL_LANE0_MASK_MSB_BITS _u(0x00007c00) -#define SIO_INTERP0_CTRL_LANE0_MASK_MSB_MSB _u(14) -#define SIO_INTERP0_CTRL_LANE0_MASK_MSB_LSB _u(10) -#define SIO_INTERP0_CTRL_LANE0_MASK_MSB_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SIO_INTERP0_CTRL_LANE0_MASK_LSB -// Description : The least-significant bit allowed to pass by the mask -// (inclusive) -#define SIO_INTERP0_CTRL_LANE0_MASK_LSB_RESET _u(0x00) -#define SIO_INTERP0_CTRL_LANE0_MASK_LSB_BITS _u(0x000003e0) -#define SIO_INTERP0_CTRL_LANE0_MASK_LSB_MSB _u(9) -#define SIO_INTERP0_CTRL_LANE0_MASK_LSB_LSB _u(5) -#define SIO_INTERP0_CTRL_LANE0_MASK_LSB_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SIO_INTERP0_CTRL_LANE0_SHIFT -// Description : Logical right-shift applied to accumulator before masking -#define SIO_INTERP0_CTRL_LANE0_SHIFT_RESET _u(0x00) -#define SIO_INTERP0_CTRL_LANE0_SHIFT_BITS _u(0x0000001f) -#define SIO_INTERP0_CTRL_LANE0_SHIFT_MSB _u(4) -#define SIO_INTERP0_CTRL_LANE0_SHIFT_LSB _u(0) -#define SIO_INTERP0_CTRL_LANE0_SHIFT_ACCESS "RW" -// ============================================================================= -// Register : SIO_INTERP0_CTRL_LANE1 -// Description : Control register for lane 1 -#define SIO_INTERP0_CTRL_LANE1_OFFSET _u(0x000000b0) -#define SIO_INTERP0_CTRL_LANE1_BITS _u(0x001fffff) -#define SIO_INTERP0_CTRL_LANE1_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : SIO_INTERP0_CTRL_LANE1_FORCE_MSB -// Description : ORed into bits 29:28 of the lane result presented to the -// processor on the bus. -// No effect on the internal 32-bit datapath. Handy for using a -// lane to generate sequence -// of pointers into flash or SRAM. -#define SIO_INTERP0_CTRL_LANE1_FORCE_MSB_RESET _u(0x0) -#define SIO_INTERP0_CTRL_LANE1_FORCE_MSB_BITS _u(0x00180000) -#define SIO_INTERP0_CTRL_LANE1_FORCE_MSB_MSB _u(20) -#define SIO_INTERP0_CTRL_LANE1_FORCE_MSB_LSB _u(19) -#define SIO_INTERP0_CTRL_LANE1_FORCE_MSB_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SIO_INTERP0_CTRL_LANE1_ADD_RAW -// Description : If 1, mask + shift is bypassed for LANE1 result. This does not -// affect FULL result. -#define SIO_INTERP0_CTRL_LANE1_ADD_RAW_RESET _u(0x0) -#define SIO_INTERP0_CTRL_LANE1_ADD_RAW_BITS _u(0x00040000) -#define SIO_INTERP0_CTRL_LANE1_ADD_RAW_MSB _u(18) -#define SIO_INTERP0_CTRL_LANE1_ADD_RAW_LSB _u(18) -#define SIO_INTERP0_CTRL_LANE1_ADD_RAW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SIO_INTERP0_CTRL_LANE1_CROSS_RESULT -// Description : If 1, feed the opposite lane's result into this lane's -// accumulator on POP. -#define SIO_INTERP0_CTRL_LANE1_CROSS_RESULT_RESET _u(0x0) -#define SIO_INTERP0_CTRL_LANE1_CROSS_RESULT_BITS _u(0x00020000) -#define SIO_INTERP0_CTRL_LANE1_CROSS_RESULT_MSB _u(17) -#define SIO_INTERP0_CTRL_LANE1_CROSS_RESULT_LSB _u(17) -#define SIO_INTERP0_CTRL_LANE1_CROSS_RESULT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SIO_INTERP0_CTRL_LANE1_CROSS_INPUT -// Description : If 1, feed the opposite lane's accumulator into this lane's -// shift + mask hardware. -// Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is -// before the shift+mask bypass) -#define SIO_INTERP0_CTRL_LANE1_CROSS_INPUT_RESET _u(0x0) -#define SIO_INTERP0_CTRL_LANE1_CROSS_INPUT_BITS _u(0x00010000) -#define SIO_INTERP0_CTRL_LANE1_CROSS_INPUT_MSB _u(16) -#define SIO_INTERP0_CTRL_LANE1_CROSS_INPUT_LSB _u(16) -#define SIO_INTERP0_CTRL_LANE1_CROSS_INPUT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SIO_INTERP0_CTRL_LANE1_SIGNED -// Description : If SIGNED is set, the shifted and masked accumulator value is -// sign-extended to 32 bits -// before adding to BASE1, and LANE1 PEEK/POP appear extended to -// 32 bits when read by processor. -#define SIO_INTERP0_CTRL_LANE1_SIGNED_RESET _u(0x0) -#define SIO_INTERP0_CTRL_LANE1_SIGNED_BITS _u(0x00008000) -#define SIO_INTERP0_CTRL_LANE1_SIGNED_MSB _u(15) -#define SIO_INTERP0_CTRL_LANE1_SIGNED_LSB _u(15) -#define SIO_INTERP0_CTRL_LANE1_SIGNED_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SIO_INTERP0_CTRL_LANE1_MASK_MSB -// Description : The most-significant bit allowed to pass by the mask -// (inclusive) -// Setting MSB < LSB may cause chip to turn inside-out -#define SIO_INTERP0_CTRL_LANE1_MASK_MSB_RESET _u(0x00) -#define SIO_INTERP0_CTRL_LANE1_MASK_MSB_BITS _u(0x00007c00) -#define SIO_INTERP0_CTRL_LANE1_MASK_MSB_MSB _u(14) -#define SIO_INTERP0_CTRL_LANE1_MASK_MSB_LSB _u(10) -#define SIO_INTERP0_CTRL_LANE1_MASK_MSB_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SIO_INTERP0_CTRL_LANE1_MASK_LSB -// Description : The least-significant bit allowed to pass by the mask -// (inclusive) -#define SIO_INTERP0_CTRL_LANE1_MASK_LSB_RESET _u(0x00) -#define SIO_INTERP0_CTRL_LANE1_MASK_LSB_BITS _u(0x000003e0) -#define SIO_INTERP0_CTRL_LANE1_MASK_LSB_MSB _u(9) -#define SIO_INTERP0_CTRL_LANE1_MASK_LSB_LSB _u(5) -#define SIO_INTERP0_CTRL_LANE1_MASK_LSB_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SIO_INTERP0_CTRL_LANE1_SHIFT -// Description : Logical right-shift applied to accumulator before masking -#define SIO_INTERP0_CTRL_LANE1_SHIFT_RESET _u(0x00) -#define SIO_INTERP0_CTRL_LANE1_SHIFT_BITS _u(0x0000001f) -#define SIO_INTERP0_CTRL_LANE1_SHIFT_MSB _u(4) -#define SIO_INTERP0_CTRL_LANE1_SHIFT_LSB _u(0) -#define SIO_INTERP0_CTRL_LANE1_SHIFT_ACCESS "RW" -// ============================================================================= -// Register : SIO_INTERP0_ACCUM0_ADD -// Description : Values written here are atomically added to ACCUM0 -// Reading yields lane 0's raw shift and mask value (BASE0 not -// added). -#define SIO_INTERP0_ACCUM0_ADD_OFFSET _u(0x000000b4) -#define SIO_INTERP0_ACCUM0_ADD_BITS _u(0x00ffffff) -#define SIO_INTERP0_ACCUM0_ADD_RESET _u(0x00000000) -#define SIO_INTERP0_ACCUM0_ADD_MSB _u(23) -#define SIO_INTERP0_ACCUM0_ADD_LSB _u(0) -#define SIO_INTERP0_ACCUM0_ADD_ACCESS "RW" -// ============================================================================= -// Register : SIO_INTERP0_ACCUM1_ADD -// Description : Values written here are atomically added to ACCUM1 -// Reading yields lane 1's raw shift and mask value (BASE1 not -// added). -#define SIO_INTERP0_ACCUM1_ADD_OFFSET _u(0x000000b8) -#define SIO_INTERP0_ACCUM1_ADD_BITS _u(0x00ffffff) -#define SIO_INTERP0_ACCUM1_ADD_RESET _u(0x00000000) -#define SIO_INTERP0_ACCUM1_ADD_MSB _u(23) -#define SIO_INTERP0_ACCUM1_ADD_LSB _u(0) -#define SIO_INTERP0_ACCUM1_ADD_ACCESS "RW" -// ============================================================================= -// Register : SIO_INTERP0_BASE_1AND0 -// Description : On write, the lower 16 bits go to BASE0, upper bits to BASE1 -// simultaneously. -// Each half is sign-extended to 32 bits if that lane's SIGNED -// flag is set. -#define SIO_INTERP0_BASE_1AND0_OFFSET _u(0x000000bc) -#define SIO_INTERP0_BASE_1AND0_BITS _u(0xffffffff) -#define SIO_INTERP0_BASE_1AND0_RESET _u(0x00000000) -#define SIO_INTERP0_BASE_1AND0_MSB _u(31) -#define SIO_INTERP0_BASE_1AND0_LSB _u(0) -#define SIO_INTERP0_BASE_1AND0_ACCESS "WO" -// ============================================================================= -// Register : SIO_INTERP1_ACCUM0 -// Description : Read/write access to accumulator 0 -#define SIO_INTERP1_ACCUM0_OFFSET _u(0x000000c0) -#define SIO_INTERP1_ACCUM0_BITS _u(0xffffffff) -#define SIO_INTERP1_ACCUM0_RESET _u(0x00000000) -#define SIO_INTERP1_ACCUM0_MSB _u(31) -#define SIO_INTERP1_ACCUM0_LSB _u(0) -#define SIO_INTERP1_ACCUM0_ACCESS "RW" -// ============================================================================= -// Register : SIO_INTERP1_ACCUM1 -// Description : Read/write access to accumulator 1 -#define SIO_INTERP1_ACCUM1_OFFSET _u(0x000000c4) -#define SIO_INTERP1_ACCUM1_BITS _u(0xffffffff) -#define SIO_INTERP1_ACCUM1_RESET _u(0x00000000) -#define SIO_INTERP1_ACCUM1_MSB _u(31) -#define SIO_INTERP1_ACCUM1_LSB _u(0) -#define SIO_INTERP1_ACCUM1_ACCESS "RW" -// ============================================================================= -// Register : SIO_INTERP1_BASE0 -// Description : Read/write access to BASE0 register. -#define SIO_INTERP1_BASE0_OFFSET _u(0x000000c8) -#define SIO_INTERP1_BASE0_BITS _u(0xffffffff) -#define SIO_INTERP1_BASE0_RESET _u(0x00000000) -#define SIO_INTERP1_BASE0_MSB _u(31) -#define SIO_INTERP1_BASE0_LSB _u(0) -#define SIO_INTERP1_BASE0_ACCESS "RW" -// ============================================================================= -// Register : SIO_INTERP1_BASE1 -// Description : Read/write access to BASE1 register. -#define SIO_INTERP1_BASE1_OFFSET _u(0x000000cc) -#define SIO_INTERP1_BASE1_BITS _u(0xffffffff) -#define SIO_INTERP1_BASE1_RESET _u(0x00000000) -#define SIO_INTERP1_BASE1_MSB _u(31) -#define SIO_INTERP1_BASE1_LSB _u(0) -#define SIO_INTERP1_BASE1_ACCESS "RW" -// ============================================================================= -// Register : SIO_INTERP1_BASE2 -// Description : Read/write access to BASE2 register. -#define SIO_INTERP1_BASE2_OFFSET _u(0x000000d0) -#define SIO_INTERP1_BASE2_BITS _u(0xffffffff) -#define SIO_INTERP1_BASE2_RESET _u(0x00000000) -#define SIO_INTERP1_BASE2_MSB _u(31) -#define SIO_INTERP1_BASE2_LSB _u(0) -#define SIO_INTERP1_BASE2_ACCESS "RW" -// ============================================================================= -// Register : SIO_INTERP1_POP_LANE0 -// Description : Read LANE0 result, and simultaneously write lane results to -// both accumulators (POP). -#define SIO_INTERP1_POP_LANE0_OFFSET _u(0x000000d4) -#define SIO_INTERP1_POP_LANE0_BITS _u(0xffffffff) -#define SIO_INTERP1_POP_LANE0_RESET _u(0x00000000) -#define SIO_INTERP1_POP_LANE0_MSB _u(31) -#define SIO_INTERP1_POP_LANE0_LSB _u(0) -#define SIO_INTERP1_POP_LANE0_ACCESS "RO" -// ============================================================================= -// Register : SIO_INTERP1_POP_LANE1 -// Description : Read LANE1 result, and simultaneously write lane results to -// both accumulators (POP). -#define SIO_INTERP1_POP_LANE1_OFFSET _u(0x000000d8) -#define SIO_INTERP1_POP_LANE1_BITS _u(0xffffffff) -#define SIO_INTERP1_POP_LANE1_RESET _u(0x00000000) -#define SIO_INTERP1_POP_LANE1_MSB _u(31) -#define SIO_INTERP1_POP_LANE1_LSB _u(0) -#define SIO_INTERP1_POP_LANE1_ACCESS "RO" -// ============================================================================= -// Register : SIO_INTERP1_POP_FULL -// Description : Read FULL result, and simultaneously write lane results to both -// accumulators (POP). -#define SIO_INTERP1_POP_FULL_OFFSET _u(0x000000dc) -#define SIO_INTERP1_POP_FULL_BITS _u(0xffffffff) -#define SIO_INTERP1_POP_FULL_RESET _u(0x00000000) -#define SIO_INTERP1_POP_FULL_MSB _u(31) -#define SIO_INTERP1_POP_FULL_LSB _u(0) -#define SIO_INTERP1_POP_FULL_ACCESS "RO" -// ============================================================================= -// Register : SIO_INTERP1_PEEK_LANE0 -// Description : Read LANE0 result, without altering any internal state (PEEK). -#define SIO_INTERP1_PEEK_LANE0_OFFSET _u(0x000000e0) -#define SIO_INTERP1_PEEK_LANE0_BITS _u(0xffffffff) -#define SIO_INTERP1_PEEK_LANE0_RESET _u(0x00000000) -#define SIO_INTERP1_PEEK_LANE0_MSB _u(31) -#define SIO_INTERP1_PEEK_LANE0_LSB _u(0) -#define SIO_INTERP1_PEEK_LANE0_ACCESS "RO" -// ============================================================================= -// Register : SIO_INTERP1_PEEK_LANE1 -// Description : Read LANE1 result, without altering any internal state (PEEK). -#define SIO_INTERP1_PEEK_LANE1_OFFSET _u(0x000000e4) -#define SIO_INTERP1_PEEK_LANE1_BITS _u(0xffffffff) -#define SIO_INTERP1_PEEK_LANE1_RESET _u(0x00000000) -#define SIO_INTERP1_PEEK_LANE1_MSB _u(31) -#define SIO_INTERP1_PEEK_LANE1_LSB _u(0) -#define SIO_INTERP1_PEEK_LANE1_ACCESS "RO" -// ============================================================================= -// Register : SIO_INTERP1_PEEK_FULL -// Description : Read FULL result, without altering any internal state (PEEK). -#define SIO_INTERP1_PEEK_FULL_OFFSET _u(0x000000e8) -#define SIO_INTERP1_PEEK_FULL_BITS _u(0xffffffff) -#define SIO_INTERP1_PEEK_FULL_RESET _u(0x00000000) -#define SIO_INTERP1_PEEK_FULL_MSB _u(31) -#define SIO_INTERP1_PEEK_FULL_LSB _u(0) -#define SIO_INTERP1_PEEK_FULL_ACCESS "RO" -// ============================================================================= -// Register : SIO_INTERP1_CTRL_LANE0 -// Description : Control register for lane 0 -#define SIO_INTERP1_CTRL_LANE0_OFFSET _u(0x000000ec) -#define SIO_INTERP1_CTRL_LANE0_BITS _u(0x03dfffff) -#define SIO_INTERP1_CTRL_LANE0_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : SIO_INTERP1_CTRL_LANE0_OVERF -// Description : Set if either OVERF0 or OVERF1 is set. -#define SIO_INTERP1_CTRL_LANE0_OVERF_RESET _u(0x0) -#define SIO_INTERP1_CTRL_LANE0_OVERF_BITS _u(0x02000000) -#define SIO_INTERP1_CTRL_LANE0_OVERF_MSB _u(25) -#define SIO_INTERP1_CTRL_LANE0_OVERF_LSB _u(25) -#define SIO_INTERP1_CTRL_LANE0_OVERF_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : SIO_INTERP1_CTRL_LANE0_OVERF1 -// Description : Indicates if any masked-off MSBs in ACCUM1 are set. -#define SIO_INTERP1_CTRL_LANE0_OVERF1_RESET _u(0x0) -#define SIO_INTERP1_CTRL_LANE0_OVERF1_BITS _u(0x01000000) -#define SIO_INTERP1_CTRL_LANE0_OVERF1_MSB _u(24) -#define SIO_INTERP1_CTRL_LANE0_OVERF1_LSB _u(24) -#define SIO_INTERP1_CTRL_LANE0_OVERF1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : SIO_INTERP1_CTRL_LANE0_OVERF0 -// Description : Indicates if any masked-off MSBs in ACCUM0 are set. -#define SIO_INTERP1_CTRL_LANE0_OVERF0_RESET _u(0x0) -#define SIO_INTERP1_CTRL_LANE0_OVERF0_BITS _u(0x00800000) -#define SIO_INTERP1_CTRL_LANE0_OVERF0_MSB _u(23) -#define SIO_INTERP1_CTRL_LANE0_OVERF0_LSB _u(23) -#define SIO_INTERP1_CTRL_LANE0_OVERF0_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : SIO_INTERP1_CTRL_LANE0_CLAMP -// Description : Only present on INTERP1 on each core. If CLAMP mode is enabled: -// - LANE0 result is shifted and masked ACCUM0, clamped by a lower -// bound of -// BASE0 and an upper bound of BASE1. -// - Signedness of these comparisons is determined by -// LANE0_CTRL_SIGNED -#define SIO_INTERP1_CTRL_LANE0_CLAMP_RESET _u(0x0) -#define SIO_INTERP1_CTRL_LANE0_CLAMP_BITS _u(0x00400000) -#define SIO_INTERP1_CTRL_LANE0_CLAMP_MSB _u(22) -#define SIO_INTERP1_CTRL_LANE0_CLAMP_LSB _u(22) -#define SIO_INTERP1_CTRL_LANE0_CLAMP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SIO_INTERP1_CTRL_LANE0_FORCE_MSB -// Description : ORed into bits 29:28 of the lane result presented to the -// processor on the bus. -// No effect on the internal 32-bit datapath. Handy for using a -// lane to generate sequence -// of pointers into flash or SRAM. -#define SIO_INTERP1_CTRL_LANE0_FORCE_MSB_RESET _u(0x0) -#define SIO_INTERP1_CTRL_LANE0_FORCE_MSB_BITS _u(0x00180000) -#define SIO_INTERP1_CTRL_LANE0_FORCE_MSB_MSB _u(20) -#define SIO_INTERP1_CTRL_LANE0_FORCE_MSB_LSB _u(19) -#define SIO_INTERP1_CTRL_LANE0_FORCE_MSB_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SIO_INTERP1_CTRL_LANE0_ADD_RAW -// Description : If 1, mask + shift is bypassed for LANE0 result. This does not -// affect FULL result. -#define SIO_INTERP1_CTRL_LANE0_ADD_RAW_RESET _u(0x0) -#define SIO_INTERP1_CTRL_LANE0_ADD_RAW_BITS _u(0x00040000) -#define SIO_INTERP1_CTRL_LANE0_ADD_RAW_MSB _u(18) -#define SIO_INTERP1_CTRL_LANE0_ADD_RAW_LSB _u(18) -#define SIO_INTERP1_CTRL_LANE0_ADD_RAW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SIO_INTERP1_CTRL_LANE0_CROSS_RESULT -// Description : If 1, feed the opposite lane's result into this lane's -// accumulator on POP. -#define SIO_INTERP1_CTRL_LANE0_CROSS_RESULT_RESET _u(0x0) -#define SIO_INTERP1_CTRL_LANE0_CROSS_RESULT_BITS _u(0x00020000) -#define SIO_INTERP1_CTRL_LANE0_CROSS_RESULT_MSB _u(17) -#define SIO_INTERP1_CTRL_LANE0_CROSS_RESULT_LSB _u(17) -#define SIO_INTERP1_CTRL_LANE0_CROSS_RESULT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SIO_INTERP1_CTRL_LANE0_CROSS_INPUT -// Description : If 1, feed the opposite lane's accumulator into this lane's -// shift + mask hardware. -// Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is -// before the shift+mask bypass) -#define SIO_INTERP1_CTRL_LANE0_CROSS_INPUT_RESET _u(0x0) -#define SIO_INTERP1_CTRL_LANE0_CROSS_INPUT_BITS _u(0x00010000) -#define SIO_INTERP1_CTRL_LANE0_CROSS_INPUT_MSB _u(16) -#define SIO_INTERP1_CTRL_LANE0_CROSS_INPUT_LSB _u(16) -#define SIO_INTERP1_CTRL_LANE0_CROSS_INPUT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SIO_INTERP1_CTRL_LANE0_SIGNED -// Description : If SIGNED is set, the shifted and masked accumulator value is -// sign-extended to 32 bits -// before adding to BASE0, and LANE0 PEEK/POP appear extended to -// 32 bits when read by processor. -#define SIO_INTERP1_CTRL_LANE0_SIGNED_RESET _u(0x0) -#define SIO_INTERP1_CTRL_LANE0_SIGNED_BITS _u(0x00008000) -#define SIO_INTERP1_CTRL_LANE0_SIGNED_MSB _u(15) -#define SIO_INTERP1_CTRL_LANE0_SIGNED_LSB _u(15) -#define SIO_INTERP1_CTRL_LANE0_SIGNED_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SIO_INTERP1_CTRL_LANE0_MASK_MSB -// Description : The most-significant bit allowed to pass by the mask -// (inclusive) -// Setting MSB < LSB may cause chip to turn inside-out -#define SIO_INTERP1_CTRL_LANE0_MASK_MSB_RESET _u(0x00) -#define SIO_INTERP1_CTRL_LANE0_MASK_MSB_BITS _u(0x00007c00) -#define SIO_INTERP1_CTRL_LANE0_MASK_MSB_MSB _u(14) -#define SIO_INTERP1_CTRL_LANE0_MASK_MSB_LSB _u(10) -#define SIO_INTERP1_CTRL_LANE0_MASK_MSB_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SIO_INTERP1_CTRL_LANE0_MASK_LSB -// Description : The least-significant bit allowed to pass by the mask -// (inclusive) -#define SIO_INTERP1_CTRL_LANE0_MASK_LSB_RESET _u(0x00) -#define SIO_INTERP1_CTRL_LANE0_MASK_LSB_BITS _u(0x000003e0) -#define SIO_INTERP1_CTRL_LANE0_MASK_LSB_MSB _u(9) -#define SIO_INTERP1_CTRL_LANE0_MASK_LSB_LSB _u(5) -#define SIO_INTERP1_CTRL_LANE0_MASK_LSB_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SIO_INTERP1_CTRL_LANE0_SHIFT -// Description : Logical right-shift applied to accumulator before masking -#define SIO_INTERP1_CTRL_LANE0_SHIFT_RESET _u(0x00) -#define SIO_INTERP1_CTRL_LANE0_SHIFT_BITS _u(0x0000001f) -#define SIO_INTERP1_CTRL_LANE0_SHIFT_MSB _u(4) -#define SIO_INTERP1_CTRL_LANE0_SHIFT_LSB _u(0) -#define SIO_INTERP1_CTRL_LANE0_SHIFT_ACCESS "RW" -// ============================================================================= -// Register : SIO_INTERP1_CTRL_LANE1 -// Description : Control register for lane 1 -#define SIO_INTERP1_CTRL_LANE1_OFFSET _u(0x000000f0) -#define SIO_INTERP1_CTRL_LANE1_BITS _u(0x001fffff) -#define SIO_INTERP1_CTRL_LANE1_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : SIO_INTERP1_CTRL_LANE1_FORCE_MSB -// Description : ORed into bits 29:28 of the lane result presented to the -// processor on the bus. -// No effect on the internal 32-bit datapath. Handy for using a -// lane to generate sequence -// of pointers into flash or SRAM. -#define SIO_INTERP1_CTRL_LANE1_FORCE_MSB_RESET _u(0x0) -#define SIO_INTERP1_CTRL_LANE1_FORCE_MSB_BITS _u(0x00180000) -#define SIO_INTERP1_CTRL_LANE1_FORCE_MSB_MSB _u(20) -#define SIO_INTERP1_CTRL_LANE1_FORCE_MSB_LSB _u(19) -#define SIO_INTERP1_CTRL_LANE1_FORCE_MSB_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SIO_INTERP1_CTRL_LANE1_ADD_RAW -// Description : If 1, mask + shift is bypassed for LANE1 result. This does not -// affect FULL result. -#define SIO_INTERP1_CTRL_LANE1_ADD_RAW_RESET _u(0x0) -#define SIO_INTERP1_CTRL_LANE1_ADD_RAW_BITS _u(0x00040000) -#define SIO_INTERP1_CTRL_LANE1_ADD_RAW_MSB _u(18) -#define SIO_INTERP1_CTRL_LANE1_ADD_RAW_LSB _u(18) -#define SIO_INTERP1_CTRL_LANE1_ADD_RAW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SIO_INTERP1_CTRL_LANE1_CROSS_RESULT -// Description : If 1, feed the opposite lane's result into this lane's -// accumulator on POP. -#define SIO_INTERP1_CTRL_LANE1_CROSS_RESULT_RESET _u(0x0) -#define SIO_INTERP1_CTRL_LANE1_CROSS_RESULT_BITS _u(0x00020000) -#define SIO_INTERP1_CTRL_LANE1_CROSS_RESULT_MSB _u(17) -#define SIO_INTERP1_CTRL_LANE1_CROSS_RESULT_LSB _u(17) -#define SIO_INTERP1_CTRL_LANE1_CROSS_RESULT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SIO_INTERP1_CTRL_LANE1_CROSS_INPUT -// Description : If 1, feed the opposite lane's accumulator into this lane's -// shift + mask hardware. -// Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is -// before the shift+mask bypass) -#define SIO_INTERP1_CTRL_LANE1_CROSS_INPUT_RESET _u(0x0) -#define SIO_INTERP1_CTRL_LANE1_CROSS_INPUT_BITS _u(0x00010000) -#define SIO_INTERP1_CTRL_LANE1_CROSS_INPUT_MSB _u(16) -#define SIO_INTERP1_CTRL_LANE1_CROSS_INPUT_LSB _u(16) -#define SIO_INTERP1_CTRL_LANE1_CROSS_INPUT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SIO_INTERP1_CTRL_LANE1_SIGNED -// Description : If SIGNED is set, the shifted and masked accumulator value is -// sign-extended to 32 bits -// before adding to BASE1, and LANE1 PEEK/POP appear extended to -// 32 bits when read by processor. -#define SIO_INTERP1_CTRL_LANE1_SIGNED_RESET _u(0x0) -#define SIO_INTERP1_CTRL_LANE1_SIGNED_BITS _u(0x00008000) -#define SIO_INTERP1_CTRL_LANE1_SIGNED_MSB _u(15) -#define SIO_INTERP1_CTRL_LANE1_SIGNED_LSB _u(15) -#define SIO_INTERP1_CTRL_LANE1_SIGNED_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SIO_INTERP1_CTRL_LANE1_MASK_MSB -// Description : The most-significant bit allowed to pass by the mask -// (inclusive) -// Setting MSB < LSB may cause chip to turn inside-out -#define SIO_INTERP1_CTRL_LANE1_MASK_MSB_RESET _u(0x00) -#define SIO_INTERP1_CTRL_LANE1_MASK_MSB_BITS _u(0x00007c00) -#define SIO_INTERP1_CTRL_LANE1_MASK_MSB_MSB _u(14) -#define SIO_INTERP1_CTRL_LANE1_MASK_MSB_LSB _u(10) -#define SIO_INTERP1_CTRL_LANE1_MASK_MSB_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SIO_INTERP1_CTRL_LANE1_MASK_LSB -// Description : The least-significant bit allowed to pass by the mask -// (inclusive) -#define SIO_INTERP1_CTRL_LANE1_MASK_LSB_RESET _u(0x00) -#define SIO_INTERP1_CTRL_LANE1_MASK_LSB_BITS _u(0x000003e0) -#define SIO_INTERP1_CTRL_LANE1_MASK_LSB_MSB _u(9) -#define SIO_INTERP1_CTRL_LANE1_MASK_LSB_LSB _u(5) -#define SIO_INTERP1_CTRL_LANE1_MASK_LSB_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SIO_INTERP1_CTRL_LANE1_SHIFT -// Description : Logical right-shift applied to accumulator before masking -#define SIO_INTERP1_CTRL_LANE1_SHIFT_RESET _u(0x00) -#define SIO_INTERP1_CTRL_LANE1_SHIFT_BITS _u(0x0000001f) -#define SIO_INTERP1_CTRL_LANE1_SHIFT_MSB _u(4) -#define SIO_INTERP1_CTRL_LANE1_SHIFT_LSB _u(0) -#define SIO_INTERP1_CTRL_LANE1_SHIFT_ACCESS "RW" -// ============================================================================= -// Register : SIO_INTERP1_ACCUM0_ADD -// Description : Values written here are atomically added to ACCUM0 -// Reading yields lane 0's raw shift and mask value (BASE0 not -// added). -#define SIO_INTERP1_ACCUM0_ADD_OFFSET _u(0x000000f4) -#define SIO_INTERP1_ACCUM0_ADD_BITS _u(0x00ffffff) -#define SIO_INTERP1_ACCUM0_ADD_RESET _u(0x00000000) -#define SIO_INTERP1_ACCUM0_ADD_MSB _u(23) -#define SIO_INTERP1_ACCUM0_ADD_LSB _u(0) -#define SIO_INTERP1_ACCUM0_ADD_ACCESS "RW" -// ============================================================================= -// Register : SIO_INTERP1_ACCUM1_ADD -// Description : Values written here are atomically added to ACCUM1 -// Reading yields lane 1's raw shift and mask value (BASE1 not -// added). -#define SIO_INTERP1_ACCUM1_ADD_OFFSET _u(0x000000f8) -#define SIO_INTERP1_ACCUM1_ADD_BITS _u(0x00ffffff) -#define SIO_INTERP1_ACCUM1_ADD_RESET _u(0x00000000) -#define SIO_INTERP1_ACCUM1_ADD_MSB _u(23) -#define SIO_INTERP1_ACCUM1_ADD_LSB _u(0) -#define SIO_INTERP1_ACCUM1_ADD_ACCESS "RW" -// ============================================================================= -// Register : SIO_INTERP1_BASE_1AND0 -// Description : On write, the lower 16 bits go to BASE0, upper bits to BASE1 -// simultaneously. -// Each half is sign-extended to 32 bits if that lane's SIGNED -// flag is set. -#define SIO_INTERP1_BASE_1AND0_OFFSET _u(0x000000fc) -#define SIO_INTERP1_BASE_1AND0_BITS _u(0xffffffff) -#define SIO_INTERP1_BASE_1AND0_RESET _u(0x00000000) -#define SIO_INTERP1_BASE_1AND0_MSB _u(31) -#define SIO_INTERP1_BASE_1AND0_LSB _u(0) -#define SIO_INTERP1_BASE_1AND0_ACCESS "WO" -// ============================================================================= -// Register : SIO_SPINLOCK0 -// Description : Reading from a spinlock address will: -// - Return 0 if lock is already locked -// - Otherwise return nonzero, and simultaneously claim the lock -// -// Writing (any value) releases the lock. -// If core 0 and core 1 attempt to claim the same lock -// simultaneously, core 0 wins. -// The value returned on success is 0x1 << lock number. -#define SIO_SPINLOCK0_OFFSET _u(0x00000100) -#define SIO_SPINLOCK0_BITS _u(0xffffffff) -#define SIO_SPINLOCK0_RESET _u(0x00000000) -#define SIO_SPINLOCK0_MSB _u(31) -#define SIO_SPINLOCK0_LSB _u(0) -#define SIO_SPINLOCK0_ACCESS "RW" -// ============================================================================= -// Register : SIO_SPINLOCK1 -// Description : Reading from a spinlock address will: -// - Return 0 if lock is already locked -// - Otherwise return nonzero, and simultaneously claim the lock -// -// Writing (any value) releases the lock. -// If core 0 and core 1 attempt to claim the same lock -// simultaneously, core 0 wins. -// The value returned on success is 0x1 << lock number. -#define SIO_SPINLOCK1_OFFSET _u(0x00000104) -#define SIO_SPINLOCK1_BITS _u(0xffffffff) -#define SIO_SPINLOCK1_RESET _u(0x00000000) -#define SIO_SPINLOCK1_MSB _u(31) -#define SIO_SPINLOCK1_LSB _u(0) -#define SIO_SPINLOCK1_ACCESS "RW" -// ============================================================================= -// Register : SIO_SPINLOCK2 -// Description : Reading from a spinlock address will: -// - Return 0 if lock is already locked -// - Otherwise return nonzero, and simultaneously claim the lock -// -// Writing (any value) releases the lock. -// If core 0 and core 1 attempt to claim the same lock -// simultaneously, core 0 wins. -// The value returned on success is 0x1 << lock number. -#define SIO_SPINLOCK2_OFFSET _u(0x00000108) -#define SIO_SPINLOCK2_BITS _u(0xffffffff) -#define SIO_SPINLOCK2_RESET _u(0x00000000) -#define SIO_SPINLOCK2_MSB _u(31) -#define SIO_SPINLOCK2_LSB _u(0) -#define SIO_SPINLOCK2_ACCESS "RW" -// ============================================================================= -// Register : SIO_SPINLOCK3 -// Description : Reading from a spinlock address will: -// - Return 0 if lock is already locked -// - Otherwise return nonzero, and simultaneously claim the lock -// -// Writing (any value) releases the lock. -// If core 0 and core 1 attempt to claim the same lock -// simultaneously, core 0 wins. -// The value returned on success is 0x1 << lock number. -#define SIO_SPINLOCK3_OFFSET _u(0x0000010c) -#define SIO_SPINLOCK3_BITS _u(0xffffffff) -#define SIO_SPINLOCK3_RESET _u(0x00000000) -#define SIO_SPINLOCK3_MSB _u(31) -#define SIO_SPINLOCK3_LSB _u(0) -#define SIO_SPINLOCK3_ACCESS "RW" -// ============================================================================= -// Register : SIO_SPINLOCK4 -// Description : Reading from a spinlock address will: -// - Return 0 if lock is already locked -// - Otherwise return nonzero, and simultaneously claim the lock -// -// Writing (any value) releases the lock. -// If core 0 and core 1 attempt to claim the same lock -// simultaneously, core 0 wins. -// The value returned on success is 0x1 << lock number. -#define SIO_SPINLOCK4_OFFSET _u(0x00000110) -#define SIO_SPINLOCK4_BITS _u(0xffffffff) -#define SIO_SPINLOCK4_RESET _u(0x00000000) -#define SIO_SPINLOCK4_MSB _u(31) -#define SIO_SPINLOCK4_LSB _u(0) -#define SIO_SPINLOCK4_ACCESS "RW" -// ============================================================================= -// Register : SIO_SPINLOCK5 -// Description : Reading from a spinlock address will: -// - Return 0 if lock is already locked -// - Otherwise return nonzero, and simultaneously claim the lock -// -// Writing (any value) releases the lock. -// If core 0 and core 1 attempt to claim the same lock -// simultaneously, core 0 wins. -// The value returned on success is 0x1 << lock number. -#define SIO_SPINLOCK5_OFFSET _u(0x00000114) -#define SIO_SPINLOCK5_BITS _u(0xffffffff) -#define SIO_SPINLOCK5_RESET _u(0x00000000) -#define SIO_SPINLOCK5_MSB _u(31) -#define SIO_SPINLOCK5_LSB _u(0) -#define SIO_SPINLOCK5_ACCESS "RW" -// ============================================================================= -// Register : SIO_SPINLOCK6 -// Description : Reading from a spinlock address will: -// - Return 0 if lock is already locked -// - Otherwise return nonzero, and simultaneously claim the lock -// -// Writing (any value) releases the lock. -// If core 0 and core 1 attempt to claim the same lock -// simultaneously, core 0 wins. -// The value returned on success is 0x1 << lock number. -#define SIO_SPINLOCK6_OFFSET _u(0x00000118) -#define SIO_SPINLOCK6_BITS _u(0xffffffff) -#define SIO_SPINLOCK6_RESET _u(0x00000000) -#define SIO_SPINLOCK6_MSB _u(31) -#define SIO_SPINLOCK6_LSB _u(0) -#define SIO_SPINLOCK6_ACCESS "RW" -// ============================================================================= -// Register : SIO_SPINLOCK7 -// Description : Reading from a spinlock address will: -// - Return 0 if lock is already locked -// - Otherwise return nonzero, and simultaneously claim the lock -// -// Writing (any value) releases the lock. -// If core 0 and core 1 attempt to claim the same lock -// simultaneously, core 0 wins. -// The value returned on success is 0x1 << lock number. -#define SIO_SPINLOCK7_OFFSET _u(0x0000011c) -#define SIO_SPINLOCK7_BITS _u(0xffffffff) -#define SIO_SPINLOCK7_RESET _u(0x00000000) -#define SIO_SPINLOCK7_MSB _u(31) -#define SIO_SPINLOCK7_LSB _u(0) -#define SIO_SPINLOCK7_ACCESS "RW" -// ============================================================================= -// Register : SIO_SPINLOCK8 -// Description : Reading from a spinlock address will: -// - Return 0 if lock is already locked -// - Otherwise return nonzero, and simultaneously claim the lock -// -// Writing (any value) releases the lock. -// If core 0 and core 1 attempt to claim the same lock -// simultaneously, core 0 wins. -// The value returned on success is 0x1 << lock number. -#define SIO_SPINLOCK8_OFFSET _u(0x00000120) -#define SIO_SPINLOCK8_BITS _u(0xffffffff) -#define SIO_SPINLOCK8_RESET _u(0x00000000) -#define SIO_SPINLOCK8_MSB _u(31) -#define SIO_SPINLOCK8_LSB _u(0) -#define SIO_SPINLOCK8_ACCESS "RW" -// ============================================================================= -// Register : SIO_SPINLOCK9 -// Description : Reading from a spinlock address will: -// - Return 0 if lock is already locked -// - Otherwise return nonzero, and simultaneously claim the lock -// -// Writing (any value) releases the lock. -// If core 0 and core 1 attempt to claim the same lock -// simultaneously, core 0 wins. -// The value returned on success is 0x1 << lock number. -#define SIO_SPINLOCK9_OFFSET _u(0x00000124) -#define SIO_SPINLOCK9_BITS _u(0xffffffff) -#define SIO_SPINLOCK9_RESET _u(0x00000000) -#define SIO_SPINLOCK9_MSB _u(31) -#define SIO_SPINLOCK9_LSB _u(0) -#define SIO_SPINLOCK9_ACCESS "RW" -// ============================================================================= -// Register : SIO_SPINLOCK10 -// Description : Reading from a spinlock address will: -// - Return 0 if lock is already locked -// - Otherwise return nonzero, and simultaneously claim the lock -// -// Writing (any value) releases the lock. -// If core 0 and core 1 attempt to claim the same lock -// simultaneously, core 0 wins. -// The value returned on success is 0x1 << lock number. -#define SIO_SPINLOCK10_OFFSET _u(0x00000128) -#define SIO_SPINLOCK10_BITS _u(0xffffffff) -#define SIO_SPINLOCK10_RESET _u(0x00000000) -#define SIO_SPINLOCK10_MSB _u(31) -#define SIO_SPINLOCK10_LSB _u(0) -#define SIO_SPINLOCK10_ACCESS "RW" -// ============================================================================= -// Register : SIO_SPINLOCK11 -// Description : Reading from a spinlock address will: -// - Return 0 if lock is already locked -// - Otherwise return nonzero, and simultaneously claim the lock -// -// Writing (any value) releases the lock. -// If core 0 and core 1 attempt to claim the same lock -// simultaneously, core 0 wins. -// The value returned on success is 0x1 << lock number. -#define SIO_SPINLOCK11_OFFSET _u(0x0000012c) -#define SIO_SPINLOCK11_BITS _u(0xffffffff) -#define SIO_SPINLOCK11_RESET _u(0x00000000) -#define SIO_SPINLOCK11_MSB _u(31) -#define SIO_SPINLOCK11_LSB _u(0) -#define SIO_SPINLOCK11_ACCESS "RW" -// ============================================================================= -// Register : SIO_SPINLOCK12 -// Description : Reading from a spinlock address will: -// - Return 0 if lock is already locked -// - Otherwise return nonzero, and simultaneously claim the lock -// -// Writing (any value) releases the lock. -// If core 0 and core 1 attempt to claim the same lock -// simultaneously, core 0 wins. -// The value returned on success is 0x1 << lock number. -#define SIO_SPINLOCK12_OFFSET _u(0x00000130) -#define SIO_SPINLOCK12_BITS _u(0xffffffff) -#define SIO_SPINLOCK12_RESET _u(0x00000000) -#define SIO_SPINLOCK12_MSB _u(31) -#define SIO_SPINLOCK12_LSB _u(0) -#define SIO_SPINLOCK12_ACCESS "RW" -// ============================================================================= -// Register : SIO_SPINLOCK13 -// Description : Reading from a spinlock address will: -// - Return 0 if lock is already locked -// - Otherwise return nonzero, and simultaneously claim the lock -// -// Writing (any value) releases the lock. -// If core 0 and core 1 attempt to claim the same lock -// simultaneously, core 0 wins. -// The value returned on success is 0x1 << lock number. -#define SIO_SPINLOCK13_OFFSET _u(0x00000134) -#define SIO_SPINLOCK13_BITS _u(0xffffffff) -#define SIO_SPINLOCK13_RESET _u(0x00000000) -#define SIO_SPINLOCK13_MSB _u(31) -#define SIO_SPINLOCK13_LSB _u(0) -#define SIO_SPINLOCK13_ACCESS "RW" -// ============================================================================= -// Register : SIO_SPINLOCK14 -// Description : Reading from a spinlock address will: -// - Return 0 if lock is already locked -// - Otherwise return nonzero, and simultaneously claim the lock -// -// Writing (any value) releases the lock. -// If core 0 and core 1 attempt to claim the same lock -// simultaneously, core 0 wins. -// The value returned on success is 0x1 << lock number. -#define SIO_SPINLOCK14_OFFSET _u(0x00000138) -#define SIO_SPINLOCK14_BITS _u(0xffffffff) -#define SIO_SPINLOCK14_RESET _u(0x00000000) -#define SIO_SPINLOCK14_MSB _u(31) -#define SIO_SPINLOCK14_LSB _u(0) -#define SIO_SPINLOCK14_ACCESS "RW" -// ============================================================================= -// Register : SIO_SPINLOCK15 -// Description : Reading from a spinlock address will: -// - Return 0 if lock is already locked -// - Otherwise return nonzero, and simultaneously claim the lock -// -// Writing (any value) releases the lock. -// If core 0 and core 1 attempt to claim the same lock -// simultaneously, core 0 wins. -// The value returned on success is 0x1 << lock number. -#define SIO_SPINLOCK15_OFFSET _u(0x0000013c) -#define SIO_SPINLOCK15_BITS _u(0xffffffff) -#define SIO_SPINLOCK15_RESET _u(0x00000000) -#define SIO_SPINLOCK15_MSB _u(31) -#define SIO_SPINLOCK15_LSB _u(0) -#define SIO_SPINLOCK15_ACCESS "RW" -// ============================================================================= -// Register : SIO_SPINLOCK16 -// Description : Reading from a spinlock address will: -// - Return 0 if lock is already locked -// - Otherwise return nonzero, and simultaneously claim the lock -// -// Writing (any value) releases the lock. -// If core 0 and core 1 attempt to claim the same lock -// simultaneously, core 0 wins. -// The value returned on success is 0x1 << lock number. -#define SIO_SPINLOCK16_OFFSET _u(0x00000140) -#define SIO_SPINLOCK16_BITS _u(0xffffffff) -#define SIO_SPINLOCK16_RESET _u(0x00000000) -#define SIO_SPINLOCK16_MSB _u(31) -#define SIO_SPINLOCK16_LSB _u(0) -#define SIO_SPINLOCK16_ACCESS "RW" -// ============================================================================= -// Register : SIO_SPINLOCK17 -// Description : Reading from a spinlock address will: -// - Return 0 if lock is already locked -// - Otherwise return nonzero, and simultaneously claim the lock -// -// Writing (any value) releases the lock. -// If core 0 and core 1 attempt to claim the same lock -// simultaneously, core 0 wins. -// The value returned on success is 0x1 << lock number. -#define SIO_SPINLOCK17_OFFSET _u(0x00000144) -#define SIO_SPINLOCK17_BITS _u(0xffffffff) -#define SIO_SPINLOCK17_RESET _u(0x00000000) -#define SIO_SPINLOCK17_MSB _u(31) -#define SIO_SPINLOCK17_LSB _u(0) -#define SIO_SPINLOCK17_ACCESS "RW" -// ============================================================================= -// Register : SIO_SPINLOCK18 -// Description : Reading from a spinlock address will: -// - Return 0 if lock is already locked -// - Otherwise return nonzero, and simultaneously claim the lock -// -// Writing (any value) releases the lock. -// If core 0 and core 1 attempt to claim the same lock -// simultaneously, core 0 wins. -// The value returned on success is 0x1 << lock number. -#define SIO_SPINLOCK18_OFFSET _u(0x00000148) -#define SIO_SPINLOCK18_BITS _u(0xffffffff) -#define SIO_SPINLOCK18_RESET _u(0x00000000) -#define SIO_SPINLOCK18_MSB _u(31) -#define SIO_SPINLOCK18_LSB _u(0) -#define SIO_SPINLOCK18_ACCESS "RW" -// ============================================================================= -// Register : SIO_SPINLOCK19 -// Description : Reading from a spinlock address will: -// - Return 0 if lock is already locked -// - Otherwise return nonzero, and simultaneously claim the lock -// -// Writing (any value) releases the lock. -// If core 0 and core 1 attempt to claim the same lock -// simultaneously, core 0 wins. -// The value returned on success is 0x1 << lock number. -#define SIO_SPINLOCK19_OFFSET _u(0x0000014c) -#define SIO_SPINLOCK19_BITS _u(0xffffffff) -#define SIO_SPINLOCK19_RESET _u(0x00000000) -#define SIO_SPINLOCK19_MSB _u(31) -#define SIO_SPINLOCK19_LSB _u(0) -#define SIO_SPINLOCK19_ACCESS "RW" -// ============================================================================= -// Register : SIO_SPINLOCK20 -// Description : Reading from a spinlock address will: -// - Return 0 if lock is already locked -// - Otherwise return nonzero, and simultaneously claim the lock -// -// Writing (any value) releases the lock. -// If core 0 and core 1 attempt to claim the same lock -// simultaneously, core 0 wins. -// The value returned on success is 0x1 << lock number. -#define SIO_SPINLOCK20_OFFSET _u(0x00000150) -#define SIO_SPINLOCK20_BITS _u(0xffffffff) -#define SIO_SPINLOCK20_RESET _u(0x00000000) -#define SIO_SPINLOCK20_MSB _u(31) -#define SIO_SPINLOCK20_LSB _u(0) -#define SIO_SPINLOCK20_ACCESS "RW" -// ============================================================================= -// Register : SIO_SPINLOCK21 -// Description : Reading from a spinlock address will: -// - Return 0 if lock is already locked -// - Otherwise return nonzero, and simultaneously claim the lock -// -// Writing (any value) releases the lock. -// If core 0 and core 1 attempt to claim the same lock -// simultaneously, core 0 wins. -// The value returned on success is 0x1 << lock number. -#define SIO_SPINLOCK21_OFFSET _u(0x00000154) -#define SIO_SPINLOCK21_BITS _u(0xffffffff) -#define SIO_SPINLOCK21_RESET _u(0x00000000) -#define SIO_SPINLOCK21_MSB _u(31) -#define SIO_SPINLOCK21_LSB _u(0) -#define SIO_SPINLOCK21_ACCESS "RW" -// ============================================================================= -// Register : SIO_SPINLOCK22 -// Description : Reading from a spinlock address will: -// - Return 0 if lock is already locked -// - Otherwise return nonzero, and simultaneously claim the lock -// -// Writing (any value) releases the lock. -// If core 0 and core 1 attempt to claim the same lock -// simultaneously, core 0 wins. -// The value returned on success is 0x1 << lock number. -#define SIO_SPINLOCK22_OFFSET _u(0x00000158) -#define SIO_SPINLOCK22_BITS _u(0xffffffff) -#define SIO_SPINLOCK22_RESET _u(0x00000000) -#define SIO_SPINLOCK22_MSB _u(31) -#define SIO_SPINLOCK22_LSB _u(0) -#define SIO_SPINLOCK22_ACCESS "RW" -// ============================================================================= -// Register : SIO_SPINLOCK23 -// Description : Reading from a spinlock address will: -// - Return 0 if lock is already locked -// - Otherwise return nonzero, and simultaneously claim the lock -// -// Writing (any value) releases the lock. -// If core 0 and core 1 attempt to claim the same lock -// simultaneously, core 0 wins. -// The value returned on success is 0x1 << lock number. -#define SIO_SPINLOCK23_OFFSET _u(0x0000015c) -#define SIO_SPINLOCK23_BITS _u(0xffffffff) -#define SIO_SPINLOCK23_RESET _u(0x00000000) -#define SIO_SPINLOCK23_MSB _u(31) -#define SIO_SPINLOCK23_LSB _u(0) -#define SIO_SPINLOCK23_ACCESS "RW" -// ============================================================================= -// Register : SIO_SPINLOCK24 -// Description : Reading from a spinlock address will: -// - Return 0 if lock is already locked -// - Otherwise return nonzero, and simultaneously claim the lock -// -// Writing (any value) releases the lock. -// If core 0 and core 1 attempt to claim the same lock -// simultaneously, core 0 wins. -// The value returned on success is 0x1 << lock number. -#define SIO_SPINLOCK24_OFFSET _u(0x00000160) -#define SIO_SPINLOCK24_BITS _u(0xffffffff) -#define SIO_SPINLOCK24_RESET _u(0x00000000) -#define SIO_SPINLOCK24_MSB _u(31) -#define SIO_SPINLOCK24_LSB _u(0) -#define SIO_SPINLOCK24_ACCESS "RW" -// ============================================================================= -// Register : SIO_SPINLOCK25 -// Description : Reading from a spinlock address will: -// - Return 0 if lock is already locked -// - Otherwise return nonzero, and simultaneously claim the lock -// -// Writing (any value) releases the lock. -// If core 0 and core 1 attempt to claim the same lock -// simultaneously, core 0 wins. -// The value returned on success is 0x1 << lock number. -#define SIO_SPINLOCK25_OFFSET _u(0x00000164) -#define SIO_SPINLOCK25_BITS _u(0xffffffff) -#define SIO_SPINLOCK25_RESET _u(0x00000000) -#define SIO_SPINLOCK25_MSB _u(31) -#define SIO_SPINLOCK25_LSB _u(0) -#define SIO_SPINLOCK25_ACCESS "RW" -// ============================================================================= -// Register : SIO_SPINLOCK26 -// Description : Reading from a spinlock address will: -// - Return 0 if lock is already locked -// - Otherwise return nonzero, and simultaneously claim the lock -// -// Writing (any value) releases the lock. -// If core 0 and core 1 attempt to claim the same lock -// simultaneously, core 0 wins. -// The value returned on success is 0x1 << lock number. -#define SIO_SPINLOCK26_OFFSET _u(0x00000168) -#define SIO_SPINLOCK26_BITS _u(0xffffffff) -#define SIO_SPINLOCK26_RESET _u(0x00000000) -#define SIO_SPINLOCK26_MSB _u(31) -#define SIO_SPINLOCK26_LSB _u(0) -#define SIO_SPINLOCK26_ACCESS "RW" -// ============================================================================= -// Register : SIO_SPINLOCK27 -// Description : Reading from a spinlock address will: -// - Return 0 if lock is already locked -// - Otherwise return nonzero, and simultaneously claim the lock -// -// Writing (any value) releases the lock. -// If core 0 and core 1 attempt to claim the same lock -// simultaneously, core 0 wins. -// The value returned on success is 0x1 << lock number. -#define SIO_SPINLOCK27_OFFSET _u(0x0000016c) -#define SIO_SPINLOCK27_BITS _u(0xffffffff) -#define SIO_SPINLOCK27_RESET _u(0x00000000) -#define SIO_SPINLOCK27_MSB _u(31) -#define SIO_SPINLOCK27_LSB _u(0) -#define SIO_SPINLOCK27_ACCESS "RW" -// ============================================================================= -// Register : SIO_SPINLOCK28 -// Description : Reading from a spinlock address will: -// - Return 0 if lock is already locked -// - Otherwise return nonzero, and simultaneously claim the lock -// -// Writing (any value) releases the lock. -// If core 0 and core 1 attempt to claim the same lock -// simultaneously, core 0 wins. -// The value returned on success is 0x1 << lock number. -#define SIO_SPINLOCK28_OFFSET _u(0x00000170) -#define SIO_SPINLOCK28_BITS _u(0xffffffff) -#define SIO_SPINLOCK28_RESET _u(0x00000000) -#define SIO_SPINLOCK28_MSB _u(31) -#define SIO_SPINLOCK28_LSB _u(0) -#define SIO_SPINLOCK28_ACCESS "RW" -// ============================================================================= -// Register : SIO_SPINLOCK29 -// Description : Reading from a spinlock address will: -// - Return 0 if lock is already locked -// - Otherwise return nonzero, and simultaneously claim the lock -// -// Writing (any value) releases the lock. -// If core 0 and core 1 attempt to claim the same lock -// simultaneously, core 0 wins. -// The value returned on success is 0x1 << lock number. -#define SIO_SPINLOCK29_OFFSET _u(0x00000174) -#define SIO_SPINLOCK29_BITS _u(0xffffffff) -#define SIO_SPINLOCK29_RESET _u(0x00000000) -#define SIO_SPINLOCK29_MSB _u(31) -#define SIO_SPINLOCK29_LSB _u(0) -#define SIO_SPINLOCK29_ACCESS "RW" -// ============================================================================= -// Register : SIO_SPINLOCK30 -// Description : Reading from a spinlock address will: -// - Return 0 if lock is already locked -// - Otherwise return nonzero, and simultaneously claim the lock -// -// Writing (any value) releases the lock. -// If core 0 and core 1 attempt to claim the same lock -// simultaneously, core 0 wins. -// The value returned on success is 0x1 << lock number. -#define SIO_SPINLOCK30_OFFSET _u(0x00000178) -#define SIO_SPINLOCK30_BITS _u(0xffffffff) -#define SIO_SPINLOCK30_RESET _u(0x00000000) -#define SIO_SPINLOCK30_MSB _u(31) -#define SIO_SPINLOCK30_LSB _u(0) -#define SIO_SPINLOCK30_ACCESS "RW" -// ============================================================================= -// Register : SIO_SPINLOCK31 -// Description : Reading from a spinlock address will: -// - Return 0 if lock is already locked -// - Otherwise return nonzero, and simultaneously claim the lock -// -// Writing (any value) releases the lock. -// If core 0 and core 1 attempt to claim the same lock -// simultaneously, core 0 wins. -// The value returned on success is 0x1 << lock number. -#define SIO_SPINLOCK31_OFFSET _u(0x0000017c) -#define SIO_SPINLOCK31_BITS _u(0xffffffff) -#define SIO_SPINLOCK31_RESET _u(0x00000000) -#define SIO_SPINLOCK31_MSB _u(31) -#define SIO_SPINLOCK31_LSB _u(0) -#define SIO_SPINLOCK31_ACCESS "RW" -// ============================================================================= -#endif // _HARDWARE_REGS_SIO_H - diff --git a/lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/spi.h b/lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/spi.h deleted file mode 100644 index d9d3b14df6..0000000000 --- a/lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/spi.h +++ /dev/null @@ -1,523 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -// ============================================================================= -// Register block : SPI -// Version : 1 -// Bus type : apb -// ============================================================================= -#ifndef _HARDWARE_REGS_SPI_H -#define _HARDWARE_REGS_SPI_H -// ============================================================================= -// Register : SPI_SSPCR0 -// Description : Control register 0, SSPCR0 on page 3-4 -#define SPI_SSPCR0_OFFSET _u(0x00000000) -#define SPI_SSPCR0_BITS _u(0x0000ffff) -#define SPI_SSPCR0_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : SPI_SSPCR0_SCR -// Description : Serial clock rate. The value SCR is used to generate the -// transmit and receive bit rate of the PrimeCell SSP. The bit -// rate is: F SSPCLK CPSDVSR x (1+SCR) where CPSDVSR is an even -// value from 2-254, programmed through the SSPCPSR register and -// SCR is a value from 0-255. -#define SPI_SSPCR0_SCR_RESET _u(0x00) -#define SPI_SSPCR0_SCR_BITS _u(0x0000ff00) -#define SPI_SSPCR0_SCR_MSB _u(15) -#define SPI_SSPCR0_SCR_LSB _u(8) -#define SPI_SSPCR0_SCR_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SPI_SSPCR0_SPH -// Description : SSPCLKOUT phase, applicable to Motorola SPI frame format only. -// See Motorola SPI frame format on page 2-10. -#define SPI_SSPCR0_SPH_RESET _u(0x0) -#define SPI_SSPCR0_SPH_BITS _u(0x00000080) -#define SPI_SSPCR0_SPH_MSB _u(7) -#define SPI_SSPCR0_SPH_LSB _u(7) -#define SPI_SSPCR0_SPH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SPI_SSPCR0_SPO -// Description : SSPCLKOUT polarity, applicable to Motorola SPI frame format -// only. See Motorola SPI frame format on page 2-10. -#define SPI_SSPCR0_SPO_RESET _u(0x0) -#define SPI_SSPCR0_SPO_BITS _u(0x00000040) -#define SPI_SSPCR0_SPO_MSB _u(6) -#define SPI_SSPCR0_SPO_LSB _u(6) -#define SPI_SSPCR0_SPO_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SPI_SSPCR0_FRF -// Description : Frame format: 00 Motorola SPI frame format. 01 TI synchronous -// serial frame format. 10 National Microwire frame format. 11 -// Reserved, undefined operation. -#define SPI_SSPCR0_FRF_RESET _u(0x0) -#define SPI_SSPCR0_FRF_BITS _u(0x00000030) -#define SPI_SSPCR0_FRF_MSB _u(5) -#define SPI_SSPCR0_FRF_LSB _u(4) -#define SPI_SSPCR0_FRF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SPI_SSPCR0_DSS -// Description : Data Size Select: 0000 Reserved, undefined operation. 0001 -// Reserved, undefined operation. 0010 Reserved, undefined -// operation. 0011 4-bit data. 0100 5-bit data. 0101 6-bit data. -// 0110 7-bit data. 0111 8-bit data. 1000 9-bit data. 1001 10-bit -// data. 1010 11-bit data. 1011 12-bit data. 1100 13-bit data. -// 1101 14-bit data. 1110 15-bit data. 1111 16-bit data. -#define SPI_SSPCR0_DSS_RESET _u(0x0) -#define SPI_SSPCR0_DSS_BITS _u(0x0000000f) -#define SPI_SSPCR0_DSS_MSB _u(3) -#define SPI_SSPCR0_DSS_LSB _u(0) -#define SPI_SSPCR0_DSS_ACCESS "RW" -// ============================================================================= -// Register : SPI_SSPCR1 -// Description : Control register 1, SSPCR1 on page 3-5 -#define SPI_SSPCR1_OFFSET _u(0x00000004) -#define SPI_SSPCR1_BITS _u(0x0000000f) -#define SPI_SSPCR1_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : SPI_SSPCR1_SOD -// Description : Slave-mode output disable. This bit is relevant only in the -// slave mode, MS=1. In multiple-slave systems, it is possible for -// an PrimeCell SSP master to broadcast a message to all slaves in -// the system while ensuring that only one slave drives data onto -// its serial output line. In such systems the RXD lines from -// multiple slaves could be tied together. To operate in such -// systems, the SOD bit can be set if the PrimeCell SSP slave is -// not supposed to drive the SSPTXD line: 0 SSP can drive the -// SSPTXD output in slave mode. 1 SSP must not drive the SSPTXD -// output in slave mode. -#define SPI_SSPCR1_SOD_RESET _u(0x0) -#define SPI_SSPCR1_SOD_BITS _u(0x00000008) -#define SPI_SSPCR1_SOD_MSB _u(3) -#define SPI_SSPCR1_SOD_LSB _u(3) -#define SPI_SSPCR1_SOD_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SPI_SSPCR1_MS -// Description : Master or slave mode select. This bit can be modified only when -// the PrimeCell SSP is disabled, SSE=0: 0 Device configured as -// master, default. 1 Device configured as slave. -#define SPI_SSPCR1_MS_RESET _u(0x0) -#define SPI_SSPCR1_MS_BITS _u(0x00000004) -#define SPI_SSPCR1_MS_MSB _u(2) -#define SPI_SSPCR1_MS_LSB _u(2) -#define SPI_SSPCR1_MS_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SPI_SSPCR1_SSE -// Description : Synchronous serial port enable: 0 SSP operation disabled. 1 SSP -// operation enabled. -#define SPI_SSPCR1_SSE_RESET _u(0x0) -#define SPI_SSPCR1_SSE_BITS _u(0x00000002) -#define SPI_SSPCR1_SSE_MSB _u(1) -#define SPI_SSPCR1_SSE_LSB _u(1) -#define SPI_SSPCR1_SSE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SPI_SSPCR1_LBM -// Description : Loop back mode: 0 Normal serial port operation enabled. 1 -// Output of transmit serial shifter is connected to input of -// receive serial shifter internally. -#define SPI_SSPCR1_LBM_RESET _u(0x0) -#define SPI_SSPCR1_LBM_BITS _u(0x00000001) -#define SPI_SSPCR1_LBM_MSB _u(0) -#define SPI_SSPCR1_LBM_LSB _u(0) -#define SPI_SSPCR1_LBM_ACCESS "RW" -// ============================================================================= -// Register : SPI_SSPDR -// Description : Data register, SSPDR on page 3-6 -#define SPI_SSPDR_OFFSET _u(0x00000008) -#define SPI_SSPDR_BITS _u(0x0000ffff) -#define SPI_SSPDR_RESET "-" -// ----------------------------------------------------------------------------- -// Field : SPI_SSPDR_DATA -// Description : Transmit/Receive FIFO: Read Receive FIFO. Write Transmit FIFO. -// You must right-justify data when the PrimeCell SSP is -// programmed for a data size that is less than 16 bits. Unused -// bits at the top are ignored by transmit logic. The receive -// logic automatically right-justifies. -#define SPI_SSPDR_DATA_RESET "-" -#define SPI_SSPDR_DATA_BITS _u(0x0000ffff) -#define SPI_SSPDR_DATA_MSB _u(15) -#define SPI_SSPDR_DATA_LSB _u(0) -#define SPI_SSPDR_DATA_ACCESS "RWF" -// ============================================================================= -// Register : SPI_SSPSR -// Description : Status register, SSPSR on page 3-7 -#define SPI_SSPSR_OFFSET _u(0x0000000c) -#define SPI_SSPSR_BITS _u(0x0000001f) -#define SPI_SSPSR_RESET _u(0x00000003) -// ----------------------------------------------------------------------------- -// Field : SPI_SSPSR_BSY -// Description : PrimeCell SSP busy flag, RO: 0 SSP is idle. 1 SSP is currently -// transmitting and/or receiving a frame or the transmit FIFO is -// not empty. -#define SPI_SSPSR_BSY_RESET _u(0x0) -#define SPI_SSPSR_BSY_BITS _u(0x00000010) -#define SPI_SSPSR_BSY_MSB _u(4) -#define SPI_SSPSR_BSY_LSB _u(4) -#define SPI_SSPSR_BSY_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : SPI_SSPSR_RFF -// Description : Receive FIFO full, RO: 0 Receive FIFO is not full. 1 Receive -// FIFO is full. -#define SPI_SSPSR_RFF_RESET _u(0x0) -#define SPI_SSPSR_RFF_BITS _u(0x00000008) -#define SPI_SSPSR_RFF_MSB _u(3) -#define SPI_SSPSR_RFF_LSB _u(3) -#define SPI_SSPSR_RFF_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : SPI_SSPSR_RNE -// Description : Receive FIFO not empty, RO: 0 Receive FIFO is empty. 1 Receive -// FIFO is not empty. -#define SPI_SSPSR_RNE_RESET _u(0x0) -#define SPI_SSPSR_RNE_BITS _u(0x00000004) -#define SPI_SSPSR_RNE_MSB _u(2) -#define SPI_SSPSR_RNE_LSB _u(2) -#define SPI_SSPSR_RNE_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : SPI_SSPSR_TNF -// Description : Transmit FIFO not full, RO: 0 Transmit FIFO is full. 1 Transmit -// FIFO is not full. -#define SPI_SSPSR_TNF_RESET _u(0x1) -#define SPI_SSPSR_TNF_BITS _u(0x00000002) -#define SPI_SSPSR_TNF_MSB _u(1) -#define SPI_SSPSR_TNF_LSB _u(1) -#define SPI_SSPSR_TNF_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : SPI_SSPSR_TFE -// Description : Transmit FIFO empty, RO: 0 Transmit FIFO is not empty. 1 -// Transmit FIFO is empty. -#define SPI_SSPSR_TFE_RESET _u(0x1) -#define SPI_SSPSR_TFE_BITS _u(0x00000001) -#define SPI_SSPSR_TFE_MSB _u(0) -#define SPI_SSPSR_TFE_LSB _u(0) -#define SPI_SSPSR_TFE_ACCESS "RO" -// ============================================================================= -// Register : SPI_SSPCPSR -// Description : Clock prescale register, SSPCPSR on page 3-8 -#define SPI_SSPCPSR_OFFSET _u(0x00000010) -#define SPI_SSPCPSR_BITS _u(0x000000ff) -#define SPI_SSPCPSR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : SPI_SSPCPSR_CPSDVSR -// Description : Clock prescale divisor. Must be an even number from 2-254, -// depending on the frequency of SSPCLK. The least significant bit -// always returns zero on reads. -#define SPI_SSPCPSR_CPSDVSR_RESET _u(0x00) -#define SPI_SSPCPSR_CPSDVSR_BITS _u(0x000000ff) -#define SPI_SSPCPSR_CPSDVSR_MSB _u(7) -#define SPI_SSPCPSR_CPSDVSR_LSB _u(0) -#define SPI_SSPCPSR_CPSDVSR_ACCESS "RW" -// ============================================================================= -// Register : SPI_SSPIMSC -// Description : Interrupt mask set or clear register, SSPIMSC on page 3-9 -#define SPI_SSPIMSC_OFFSET _u(0x00000014) -#define SPI_SSPIMSC_BITS _u(0x0000000f) -#define SPI_SSPIMSC_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : SPI_SSPIMSC_TXIM -// Description : Transmit FIFO interrupt mask: 0 Transmit FIFO half empty or -// less condition interrupt is masked. 1 Transmit FIFO half empty -// or less condition interrupt is not masked. -#define SPI_SSPIMSC_TXIM_RESET _u(0x0) -#define SPI_SSPIMSC_TXIM_BITS _u(0x00000008) -#define SPI_SSPIMSC_TXIM_MSB _u(3) -#define SPI_SSPIMSC_TXIM_LSB _u(3) -#define SPI_SSPIMSC_TXIM_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SPI_SSPIMSC_RXIM -// Description : Receive FIFO interrupt mask: 0 Receive FIFO half full or less -// condition interrupt is masked. 1 Receive FIFO half full or less -// condition interrupt is not masked. -#define SPI_SSPIMSC_RXIM_RESET _u(0x0) -#define SPI_SSPIMSC_RXIM_BITS _u(0x00000004) -#define SPI_SSPIMSC_RXIM_MSB _u(2) -#define SPI_SSPIMSC_RXIM_LSB _u(2) -#define SPI_SSPIMSC_RXIM_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SPI_SSPIMSC_RTIM -// Description : Receive timeout interrupt mask: 0 Receive FIFO not empty and no -// read prior to timeout period interrupt is masked. 1 Receive -// FIFO not empty and no read prior to timeout period interrupt is -// not masked. -#define SPI_SSPIMSC_RTIM_RESET _u(0x0) -#define SPI_SSPIMSC_RTIM_BITS _u(0x00000002) -#define SPI_SSPIMSC_RTIM_MSB _u(1) -#define SPI_SSPIMSC_RTIM_LSB _u(1) -#define SPI_SSPIMSC_RTIM_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SPI_SSPIMSC_RORIM -// Description : Receive overrun interrupt mask: 0 Receive FIFO written to while -// full condition interrupt is masked. 1 Receive FIFO written to -// while full condition interrupt is not masked. -#define SPI_SSPIMSC_RORIM_RESET _u(0x0) -#define SPI_SSPIMSC_RORIM_BITS _u(0x00000001) -#define SPI_SSPIMSC_RORIM_MSB _u(0) -#define SPI_SSPIMSC_RORIM_LSB _u(0) -#define SPI_SSPIMSC_RORIM_ACCESS "RW" -// ============================================================================= -// Register : SPI_SSPRIS -// Description : Raw interrupt status register, SSPRIS on page 3-10 -#define SPI_SSPRIS_OFFSET _u(0x00000018) -#define SPI_SSPRIS_BITS _u(0x0000000f) -#define SPI_SSPRIS_RESET _u(0x00000008) -// ----------------------------------------------------------------------------- -// Field : SPI_SSPRIS_TXRIS -// Description : Gives the raw interrupt state, prior to masking, of the -// SSPTXINTR interrupt -#define SPI_SSPRIS_TXRIS_RESET _u(0x1) -#define SPI_SSPRIS_TXRIS_BITS _u(0x00000008) -#define SPI_SSPRIS_TXRIS_MSB _u(3) -#define SPI_SSPRIS_TXRIS_LSB _u(3) -#define SPI_SSPRIS_TXRIS_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : SPI_SSPRIS_RXRIS -// Description : Gives the raw interrupt state, prior to masking, of the -// SSPRXINTR interrupt -#define SPI_SSPRIS_RXRIS_RESET _u(0x0) -#define SPI_SSPRIS_RXRIS_BITS _u(0x00000004) -#define SPI_SSPRIS_RXRIS_MSB _u(2) -#define SPI_SSPRIS_RXRIS_LSB _u(2) -#define SPI_SSPRIS_RXRIS_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : SPI_SSPRIS_RTRIS -// Description : Gives the raw interrupt state, prior to masking, of the -// SSPRTINTR interrupt -#define SPI_SSPRIS_RTRIS_RESET _u(0x0) -#define SPI_SSPRIS_RTRIS_BITS _u(0x00000002) -#define SPI_SSPRIS_RTRIS_MSB _u(1) -#define SPI_SSPRIS_RTRIS_LSB _u(1) -#define SPI_SSPRIS_RTRIS_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : SPI_SSPRIS_RORRIS -// Description : Gives the raw interrupt state, prior to masking, of the -// SSPRORINTR interrupt -#define SPI_SSPRIS_RORRIS_RESET _u(0x0) -#define SPI_SSPRIS_RORRIS_BITS _u(0x00000001) -#define SPI_SSPRIS_RORRIS_MSB _u(0) -#define SPI_SSPRIS_RORRIS_LSB _u(0) -#define SPI_SSPRIS_RORRIS_ACCESS "RO" -// ============================================================================= -// Register : SPI_SSPMIS -// Description : Masked interrupt status register, SSPMIS on page 3-11 -#define SPI_SSPMIS_OFFSET _u(0x0000001c) -#define SPI_SSPMIS_BITS _u(0x0000000f) -#define SPI_SSPMIS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : SPI_SSPMIS_TXMIS -// Description : Gives the transmit FIFO masked interrupt state, after masking, -// of the SSPTXINTR interrupt -#define SPI_SSPMIS_TXMIS_RESET _u(0x0) -#define SPI_SSPMIS_TXMIS_BITS _u(0x00000008) -#define SPI_SSPMIS_TXMIS_MSB _u(3) -#define SPI_SSPMIS_TXMIS_LSB _u(3) -#define SPI_SSPMIS_TXMIS_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : SPI_SSPMIS_RXMIS -// Description : Gives the receive FIFO masked interrupt state, after masking, -// of the SSPRXINTR interrupt -#define SPI_SSPMIS_RXMIS_RESET _u(0x0) -#define SPI_SSPMIS_RXMIS_BITS _u(0x00000004) -#define SPI_SSPMIS_RXMIS_MSB _u(2) -#define SPI_SSPMIS_RXMIS_LSB _u(2) -#define SPI_SSPMIS_RXMIS_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : SPI_SSPMIS_RTMIS -// Description : Gives the receive timeout masked interrupt state, after -// masking, of the SSPRTINTR interrupt -#define SPI_SSPMIS_RTMIS_RESET _u(0x0) -#define SPI_SSPMIS_RTMIS_BITS _u(0x00000002) -#define SPI_SSPMIS_RTMIS_MSB _u(1) -#define SPI_SSPMIS_RTMIS_LSB _u(1) -#define SPI_SSPMIS_RTMIS_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : SPI_SSPMIS_RORMIS -// Description : Gives the receive over run masked interrupt status, after -// masking, of the SSPRORINTR interrupt -#define SPI_SSPMIS_RORMIS_RESET _u(0x0) -#define SPI_SSPMIS_RORMIS_BITS _u(0x00000001) -#define SPI_SSPMIS_RORMIS_MSB _u(0) -#define SPI_SSPMIS_RORMIS_LSB _u(0) -#define SPI_SSPMIS_RORMIS_ACCESS "RO" -// ============================================================================= -// Register : SPI_SSPICR -// Description : Interrupt clear register, SSPICR on page 3-11 -#define SPI_SSPICR_OFFSET _u(0x00000020) -#define SPI_SSPICR_BITS _u(0x00000003) -#define SPI_SSPICR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : SPI_SSPICR_RTIC -// Description : Clears the SSPRTINTR interrupt -#define SPI_SSPICR_RTIC_RESET _u(0x0) -#define SPI_SSPICR_RTIC_BITS _u(0x00000002) -#define SPI_SSPICR_RTIC_MSB _u(1) -#define SPI_SSPICR_RTIC_LSB _u(1) -#define SPI_SSPICR_RTIC_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : SPI_SSPICR_RORIC -// Description : Clears the SSPRORINTR interrupt -#define SPI_SSPICR_RORIC_RESET _u(0x0) -#define SPI_SSPICR_RORIC_BITS _u(0x00000001) -#define SPI_SSPICR_RORIC_MSB _u(0) -#define SPI_SSPICR_RORIC_LSB _u(0) -#define SPI_SSPICR_RORIC_ACCESS "WC" -// ============================================================================= -// Register : SPI_SSPDMACR -// Description : DMA control register, SSPDMACR on page 3-12 -#define SPI_SSPDMACR_OFFSET _u(0x00000024) -#define SPI_SSPDMACR_BITS _u(0x00000003) -#define SPI_SSPDMACR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : SPI_SSPDMACR_TXDMAE -// Description : Transmit DMA Enable. If this bit is set to 1, DMA for the -// transmit FIFO is enabled. -#define SPI_SSPDMACR_TXDMAE_RESET _u(0x0) -#define SPI_SSPDMACR_TXDMAE_BITS _u(0x00000002) -#define SPI_SSPDMACR_TXDMAE_MSB _u(1) -#define SPI_SSPDMACR_TXDMAE_LSB _u(1) -#define SPI_SSPDMACR_TXDMAE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SPI_SSPDMACR_RXDMAE -// Description : Receive DMA Enable. If this bit is set to 1, DMA for the -// receive FIFO is enabled. -#define SPI_SSPDMACR_RXDMAE_RESET _u(0x0) -#define SPI_SSPDMACR_RXDMAE_BITS _u(0x00000001) -#define SPI_SSPDMACR_RXDMAE_MSB _u(0) -#define SPI_SSPDMACR_RXDMAE_LSB _u(0) -#define SPI_SSPDMACR_RXDMAE_ACCESS "RW" -// ============================================================================= -// Register : SPI_SSPPERIPHID0 -// Description : Peripheral identification registers, SSPPeriphID0-3 on page -// 3-13 -#define SPI_SSPPERIPHID0_OFFSET _u(0x00000fe0) -#define SPI_SSPPERIPHID0_BITS _u(0x000000ff) -#define SPI_SSPPERIPHID0_RESET _u(0x00000022) -// ----------------------------------------------------------------------------- -// Field : SPI_SSPPERIPHID0_PARTNUMBER0 -// Description : These bits read back as 0x22 -#define SPI_SSPPERIPHID0_PARTNUMBER0_RESET _u(0x22) -#define SPI_SSPPERIPHID0_PARTNUMBER0_BITS _u(0x000000ff) -#define SPI_SSPPERIPHID0_PARTNUMBER0_MSB _u(7) -#define SPI_SSPPERIPHID0_PARTNUMBER0_LSB _u(0) -#define SPI_SSPPERIPHID0_PARTNUMBER0_ACCESS "RO" -// ============================================================================= -// Register : SPI_SSPPERIPHID1 -// Description : Peripheral identification registers, SSPPeriphID0-3 on page -// 3-13 -#define SPI_SSPPERIPHID1_OFFSET _u(0x00000fe4) -#define SPI_SSPPERIPHID1_BITS _u(0x000000ff) -#define SPI_SSPPERIPHID1_RESET _u(0x00000010) -// ----------------------------------------------------------------------------- -// Field : SPI_SSPPERIPHID1_DESIGNER0 -// Description : These bits read back as 0x1 -#define SPI_SSPPERIPHID1_DESIGNER0_RESET _u(0x1) -#define SPI_SSPPERIPHID1_DESIGNER0_BITS _u(0x000000f0) -#define SPI_SSPPERIPHID1_DESIGNER0_MSB _u(7) -#define SPI_SSPPERIPHID1_DESIGNER0_LSB _u(4) -#define SPI_SSPPERIPHID1_DESIGNER0_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : SPI_SSPPERIPHID1_PARTNUMBER1 -// Description : These bits read back as 0x0 -#define SPI_SSPPERIPHID1_PARTNUMBER1_RESET _u(0x0) -#define SPI_SSPPERIPHID1_PARTNUMBER1_BITS _u(0x0000000f) -#define SPI_SSPPERIPHID1_PARTNUMBER1_MSB _u(3) -#define SPI_SSPPERIPHID1_PARTNUMBER1_LSB _u(0) -#define SPI_SSPPERIPHID1_PARTNUMBER1_ACCESS "RO" -// ============================================================================= -// Register : SPI_SSPPERIPHID2 -// Description : Peripheral identification registers, SSPPeriphID0-3 on page -// 3-13 -#define SPI_SSPPERIPHID2_OFFSET _u(0x00000fe8) -#define SPI_SSPPERIPHID2_BITS _u(0x000000ff) -#define SPI_SSPPERIPHID2_RESET _u(0x00000034) -// ----------------------------------------------------------------------------- -// Field : SPI_SSPPERIPHID2_REVISION -// Description : These bits return the peripheral revision -#define SPI_SSPPERIPHID2_REVISION_RESET _u(0x3) -#define SPI_SSPPERIPHID2_REVISION_BITS _u(0x000000f0) -#define SPI_SSPPERIPHID2_REVISION_MSB _u(7) -#define SPI_SSPPERIPHID2_REVISION_LSB _u(4) -#define SPI_SSPPERIPHID2_REVISION_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : SPI_SSPPERIPHID2_DESIGNER1 -// Description : These bits read back as 0x4 -#define SPI_SSPPERIPHID2_DESIGNER1_RESET _u(0x4) -#define SPI_SSPPERIPHID2_DESIGNER1_BITS _u(0x0000000f) -#define SPI_SSPPERIPHID2_DESIGNER1_MSB _u(3) -#define SPI_SSPPERIPHID2_DESIGNER1_LSB _u(0) -#define SPI_SSPPERIPHID2_DESIGNER1_ACCESS "RO" -// ============================================================================= -// Register : SPI_SSPPERIPHID3 -// Description : Peripheral identification registers, SSPPeriphID0-3 on page -// 3-13 -#define SPI_SSPPERIPHID3_OFFSET _u(0x00000fec) -#define SPI_SSPPERIPHID3_BITS _u(0x000000ff) -#define SPI_SSPPERIPHID3_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : SPI_SSPPERIPHID3_CONFIGURATION -// Description : These bits read back as 0x00 -#define SPI_SSPPERIPHID3_CONFIGURATION_RESET _u(0x00) -#define SPI_SSPPERIPHID3_CONFIGURATION_BITS _u(0x000000ff) -#define SPI_SSPPERIPHID3_CONFIGURATION_MSB _u(7) -#define SPI_SSPPERIPHID3_CONFIGURATION_LSB _u(0) -#define SPI_SSPPERIPHID3_CONFIGURATION_ACCESS "RO" -// ============================================================================= -// Register : SPI_SSPPCELLID0 -// Description : PrimeCell identification registers, SSPPCellID0-3 on page 3-16 -#define SPI_SSPPCELLID0_OFFSET _u(0x00000ff0) -#define SPI_SSPPCELLID0_BITS _u(0x000000ff) -#define SPI_SSPPCELLID0_RESET _u(0x0000000d) -// ----------------------------------------------------------------------------- -// Field : SPI_SSPPCELLID0_SSPPCELLID0 -// Description : These bits read back as 0x0D -#define SPI_SSPPCELLID0_SSPPCELLID0_RESET _u(0x0d) -#define SPI_SSPPCELLID0_SSPPCELLID0_BITS _u(0x000000ff) -#define SPI_SSPPCELLID0_SSPPCELLID0_MSB _u(7) -#define SPI_SSPPCELLID0_SSPPCELLID0_LSB _u(0) -#define SPI_SSPPCELLID0_SSPPCELLID0_ACCESS "RO" -// ============================================================================= -// Register : SPI_SSPPCELLID1 -// Description : PrimeCell identification registers, SSPPCellID0-3 on page 3-16 -#define SPI_SSPPCELLID1_OFFSET _u(0x00000ff4) -#define SPI_SSPPCELLID1_BITS _u(0x000000ff) -#define SPI_SSPPCELLID1_RESET _u(0x000000f0) -// ----------------------------------------------------------------------------- -// Field : SPI_SSPPCELLID1_SSPPCELLID1 -// Description : These bits read back as 0xF0 -#define SPI_SSPPCELLID1_SSPPCELLID1_RESET _u(0xf0) -#define SPI_SSPPCELLID1_SSPPCELLID1_BITS _u(0x000000ff) -#define SPI_SSPPCELLID1_SSPPCELLID1_MSB _u(7) -#define SPI_SSPPCELLID1_SSPPCELLID1_LSB _u(0) -#define SPI_SSPPCELLID1_SSPPCELLID1_ACCESS "RO" -// ============================================================================= -// Register : SPI_SSPPCELLID2 -// Description : PrimeCell identification registers, SSPPCellID0-3 on page 3-16 -#define SPI_SSPPCELLID2_OFFSET _u(0x00000ff8) -#define SPI_SSPPCELLID2_BITS _u(0x000000ff) -#define SPI_SSPPCELLID2_RESET _u(0x00000005) -// ----------------------------------------------------------------------------- -// Field : SPI_SSPPCELLID2_SSPPCELLID2 -// Description : These bits read back as 0x05 -#define SPI_SSPPCELLID2_SSPPCELLID2_RESET _u(0x05) -#define SPI_SSPPCELLID2_SSPPCELLID2_BITS _u(0x000000ff) -#define SPI_SSPPCELLID2_SSPPCELLID2_MSB _u(7) -#define SPI_SSPPCELLID2_SSPPCELLID2_LSB _u(0) -#define SPI_SSPPCELLID2_SSPPCELLID2_ACCESS "RO" -// ============================================================================= -// Register : SPI_SSPPCELLID3 -// Description : PrimeCell identification registers, SSPPCellID0-3 on page 3-16 -#define SPI_SSPPCELLID3_OFFSET _u(0x00000ffc) -#define SPI_SSPPCELLID3_BITS _u(0x000000ff) -#define SPI_SSPPCELLID3_RESET _u(0x000000b1) -// ----------------------------------------------------------------------------- -// Field : SPI_SSPPCELLID3_SSPPCELLID3 -// Description : These bits read back as 0xB1 -#define SPI_SSPPCELLID3_SSPPCELLID3_RESET _u(0xb1) -#define SPI_SSPPCELLID3_SSPPCELLID3_BITS _u(0x000000ff) -#define SPI_SSPPCELLID3_SSPPCELLID3_MSB _u(7) -#define SPI_SSPPCELLID3_SSPPCELLID3_LSB _u(0) -#define SPI_SSPPCELLID3_SSPPCELLID3_ACCESS "RO" -// ============================================================================= -#endif // _HARDWARE_REGS_SPI_H - diff --git a/lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/ssi.h b/lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/ssi.h deleted file mode 100644 index 7fe6aa6aac..0000000000 --- a/lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/ssi.h +++ /dev/null @@ -1,808 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -// ============================================================================= -// Register block : SSI -// Version : 1 -// Bus type : apb -// Description : DW_apb_ssi has the following features: -// * APB interface – Allows for easy integration into a -// DesignWare Synthesizable Components for AMBA 2 -// implementation. -// * APB3 and APB4 protocol support. -// * Scalable APB data bus width – Supports APB data bus widths -// of 8, 16, and 32 bits. -// * Serial-master or serial-slave operation – Enables serial -// communication with serial-master or serial-slave peripheral -// devices. -// * Programmable Dual/Quad/Octal SPI support in Master Mode. -// * Dual Data Rate (DDR) and Read Data Strobe (RDS) Support - -// Enables the DW_apb_ssi master to perform operations with the -// device in DDR and RDS modes when working in Dual/Quad/Octal -// mode of operation. -// * Data Mask Support - Enables the DW_apb_ssi to selectively -// update the bytes in the device. This feature is applicable -// only in enhanced SPI modes. -// * eXecute-In-Place (XIP) support - Enables the DW_apb_ssi -// master to behave as a memory mapped I/O and fetches the data -// from the device based on the APB read request. This feature -// is applicable only in enhanced SPI modes. -// * DMA Controller Interface – Enables the DW_apb_ssi to -// interface to a DMA controller over the bus using a -// handshaking interface for transfer requests. -// * Independent masking of interrupts – Master collision, -// transmit FIFO overflow, transmit FIFO empty, receive FIFO -// full, receive FIFO underflow, and receive FIFO overflow -// interrupts can all be masked independently. -// * Multi-master contention detection – Informs the processor -// of multiple serial-master accesses on the serial bus. -// * Bypass of meta-stability flip-flops for synchronous clocks -// – When the APB clock (pclk) and the DW_apb_ssi serial clock -// (ssi_clk) are synchronous, meta-stable flip-flops are not -// used when transferring control signals across these clock -// domains. -// * Programmable delay on the sample time of the received -// serial data bit (rxd); enables programmable control of -// routing delays resulting in higher serial data-bit rates. -// * Programmable features: -// - Serial interface operation – Choice of Motorola SPI, Texas -// Instruments Synchronous Serial Protocol or National -// Semiconductor Microwire. -// - Clock bit-rate – Dynamic control of the serial bit rate of -// the data transfer; used in only serial-master mode of -// operation. -// - Data Item size (4 to 32 bits) – Item size of each data -// transfer under the control of the programmer. -// * Configured features: -// - FIFO depth – 16 words deep. The FIFO width is fixed at 32 -// bits. -// - 1 slave select output. -// - Hardware slave-select – Dedicated hardware slave-select -// line. -// - Combined interrupt line - one combined interrupt line from -// the DW_apb_ssi to the interrupt controller. -// - Interrupt polarity – active high interrupt lines. -// - Serial clock polarity – low serial-clock polarity directly -// after reset. -// - Serial clock phase – capture on first edge of serial-clock -// directly after reset. -// ============================================================================= -#ifndef _HARDWARE_REGS_SSI_H -#define _HARDWARE_REGS_SSI_H -// ============================================================================= -// Register : SSI_CTRLR0 -// Description : Control register 0 -#define SSI_CTRLR0_OFFSET _u(0x00000000) -#define SSI_CTRLR0_BITS _u(0x017fffff) -#define SSI_CTRLR0_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : SSI_CTRLR0_SSTE -// Description : Slave select toggle enable -#define SSI_CTRLR0_SSTE_RESET _u(0x0) -#define SSI_CTRLR0_SSTE_BITS _u(0x01000000) -#define SSI_CTRLR0_SSTE_MSB _u(24) -#define SSI_CTRLR0_SSTE_LSB _u(24) -#define SSI_CTRLR0_SSTE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SSI_CTRLR0_SPI_FRF -// Description : SPI frame format -// 0x0 -> Standard 1-bit SPI frame format; 1 bit per SCK, full-duplex -// 0x1 -> Dual-SPI frame format; two bits per SCK, half-duplex -// 0x2 -> Quad-SPI frame format; four bits per SCK, half-duplex -#define SSI_CTRLR0_SPI_FRF_RESET _u(0x0) -#define SSI_CTRLR0_SPI_FRF_BITS _u(0x00600000) -#define SSI_CTRLR0_SPI_FRF_MSB _u(22) -#define SSI_CTRLR0_SPI_FRF_LSB _u(21) -#define SSI_CTRLR0_SPI_FRF_ACCESS "RW" -#define SSI_CTRLR0_SPI_FRF_VALUE_STD _u(0x0) -#define SSI_CTRLR0_SPI_FRF_VALUE_DUAL _u(0x1) -#define SSI_CTRLR0_SPI_FRF_VALUE_QUAD _u(0x2) -// ----------------------------------------------------------------------------- -// Field : SSI_CTRLR0_DFS_32 -// Description : Data frame size in 32b transfer mode -// Value of n -> n+1 clocks per frame. -#define SSI_CTRLR0_DFS_32_RESET _u(0x00) -#define SSI_CTRLR0_DFS_32_BITS _u(0x001f0000) -#define SSI_CTRLR0_DFS_32_MSB _u(20) -#define SSI_CTRLR0_DFS_32_LSB _u(16) -#define SSI_CTRLR0_DFS_32_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SSI_CTRLR0_CFS -// Description : Control frame size -// Value of n -> n+1 clocks per frame. -#define SSI_CTRLR0_CFS_RESET _u(0x0) -#define SSI_CTRLR0_CFS_BITS _u(0x0000f000) -#define SSI_CTRLR0_CFS_MSB _u(15) -#define SSI_CTRLR0_CFS_LSB _u(12) -#define SSI_CTRLR0_CFS_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SSI_CTRLR0_SRL -// Description : Shift register loop (test mode) -#define SSI_CTRLR0_SRL_RESET _u(0x0) -#define SSI_CTRLR0_SRL_BITS _u(0x00000800) -#define SSI_CTRLR0_SRL_MSB _u(11) -#define SSI_CTRLR0_SRL_LSB _u(11) -#define SSI_CTRLR0_SRL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SSI_CTRLR0_SLV_OE -// Description : Slave output enable -#define SSI_CTRLR0_SLV_OE_RESET _u(0x0) -#define SSI_CTRLR0_SLV_OE_BITS _u(0x00000400) -#define SSI_CTRLR0_SLV_OE_MSB _u(10) -#define SSI_CTRLR0_SLV_OE_LSB _u(10) -#define SSI_CTRLR0_SLV_OE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SSI_CTRLR0_TMOD -// Description : Transfer mode -// 0x0 -> Both transmit and receive -// 0x1 -> Transmit only (not for FRF == 0, standard SPI mode) -// 0x2 -> Receive only (not for FRF == 0, standard SPI mode) -// 0x3 -> EEPROM read mode (TX then RX; RX starts after control data TX'd) -#define SSI_CTRLR0_TMOD_RESET _u(0x0) -#define SSI_CTRLR0_TMOD_BITS _u(0x00000300) -#define SSI_CTRLR0_TMOD_MSB _u(9) -#define SSI_CTRLR0_TMOD_LSB _u(8) -#define SSI_CTRLR0_TMOD_ACCESS "RW" -#define SSI_CTRLR0_TMOD_VALUE_TX_AND_RX _u(0x0) -#define SSI_CTRLR0_TMOD_VALUE_TX_ONLY _u(0x1) -#define SSI_CTRLR0_TMOD_VALUE_RX_ONLY _u(0x2) -#define SSI_CTRLR0_TMOD_VALUE_EEPROM_READ _u(0x3) -// ----------------------------------------------------------------------------- -// Field : SSI_CTRLR0_SCPOL -// Description : Serial clock polarity -#define SSI_CTRLR0_SCPOL_RESET _u(0x0) -#define SSI_CTRLR0_SCPOL_BITS _u(0x00000080) -#define SSI_CTRLR0_SCPOL_MSB _u(7) -#define SSI_CTRLR0_SCPOL_LSB _u(7) -#define SSI_CTRLR0_SCPOL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SSI_CTRLR0_SCPH -// Description : Serial clock phase -#define SSI_CTRLR0_SCPH_RESET _u(0x0) -#define SSI_CTRLR0_SCPH_BITS _u(0x00000040) -#define SSI_CTRLR0_SCPH_MSB _u(6) -#define SSI_CTRLR0_SCPH_LSB _u(6) -#define SSI_CTRLR0_SCPH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SSI_CTRLR0_FRF -// Description : Frame format -#define SSI_CTRLR0_FRF_RESET _u(0x0) -#define SSI_CTRLR0_FRF_BITS _u(0x00000030) -#define SSI_CTRLR0_FRF_MSB _u(5) -#define SSI_CTRLR0_FRF_LSB _u(4) -#define SSI_CTRLR0_FRF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SSI_CTRLR0_DFS -// Description : Data frame size -#define SSI_CTRLR0_DFS_RESET _u(0x0) -#define SSI_CTRLR0_DFS_BITS _u(0x0000000f) -#define SSI_CTRLR0_DFS_MSB _u(3) -#define SSI_CTRLR0_DFS_LSB _u(0) -#define SSI_CTRLR0_DFS_ACCESS "RW" -// ============================================================================= -// Register : SSI_CTRLR1 -// Description : Master Control register 1 -#define SSI_CTRLR1_OFFSET _u(0x00000004) -#define SSI_CTRLR1_BITS _u(0x0000ffff) -#define SSI_CTRLR1_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : SSI_CTRLR1_NDF -// Description : Number of data frames -#define SSI_CTRLR1_NDF_RESET _u(0x0000) -#define SSI_CTRLR1_NDF_BITS _u(0x0000ffff) -#define SSI_CTRLR1_NDF_MSB _u(15) -#define SSI_CTRLR1_NDF_LSB _u(0) -#define SSI_CTRLR1_NDF_ACCESS "RW" -// ============================================================================= -// Register : SSI_SSIENR -// Description : SSI Enable -#define SSI_SSIENR_OFFSET _u(0x00000008) -#define SSI_SSIENR_BITS _u(0x00000001) -#define SSI_SSIENR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : SSI_SSIENR_SSI_EN -// Description : SSI enable -#define SSI_SSIENR_SSI_EN_RESET _u(0x0) -#define SSI_SSIENR_SSI_EN_BITS _u(0x00000001) -#define SSI_SSIENR_SSI_EN_MSB _u(0) -#define SSI_SSIENR_SSI_EN_LSB _u(0) -#define SSI_SSIENR_SSI_EN_ACCESS "RW" -// ============================================================================= -// Register : SSI_MWCR -// Description : Microwire Control -#define SSI_MWCR_OFFSET _u(0x0000000c) -#define SSI_MWCR_BITS _u(0x00000007) -#define SSI_MWCR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : SSI_MWCR_MHS -// Description : Microwire handshaking -#define SSI_MWCR_MHS_RESET _u(0x0) -#define SSI_MWCR_MHS_BITS _u(0x00000004) -#define SSI_MWCR_MHS_MSB _u(2) -#define SSI_MWCR_MHS_LSB _u(2) -#define SSI_MWCR_MHS_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SSI_MWCR_MDD -// Description : Microwire control -#define SSI_MWCR_MDD_RESET _u(0x0) -#define SSI_MWCR_MDD_BITS _u(0x00000002) -#define SSI_MWCR_MDD_MSB _u(1) -#define SSI_MWCR_MDD_LSB _u(1) -#define SSI_MWCR_MDD_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SSI_MWCR_MWMOD -// Description : Microwire transfer mode -#define SSI_MWCR_MWMOD_RESET _u(0x0) -#define SSI_MWCR_MWMOD_BITS _u(0x00000001) -#define SSI_MWCR_MWMOD_MSB _u(0) -#define SSI_MWCR_MWMOD_LSB _u(0) -#define SSI_MWCR_MWMOD_ACCESS "RW" -// ============================================================================= -// Register : SSI_SER -// Description : Slave enable -// For each bit: -// 0 -> slave not selected -// 1 -> slave selected -#define SSI_SER_OFFSET _u(0x00000010) -#define SSI_SER_BITS _u(0x00000001) -#define SSI_SER_RESET _u(0x00000000) -#define SSI_SER_MSB _u(0) -#define SSI_SER_LSB _u(0) -#define SSI_SER_ACCESS "RW" -// ============================================================================= -// Register : SSI_BAUDR -// Description : Baud rate -#define SSI_BAUDR_OFFSET _u(0x00000014) -#define SSI_BAUDR_BITS _u(0x0000ffff) -#define SSI_BAUDR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : SSI_BAUDR_SCKDV -// Description : SSI clock divider -#define SSI_BAUDR_SCKDV_RESET _u(0x0000) -#define SSI_BAUDR_SCKDV_BITS _u(0x0000ffff) -#define SSI_BAUDR_SCKDV_MSB _u(15) -#define SSI_BAUDR_SCKDV_LSB _u(0) -#define SSI_BAUDR_SCKDV_ACCESS "RW" -// ============================================================================= -// Register : SSI_TXFTLR -// Description : TX FIFO threshold level -#define SSI_TXFTLR_OFFSET _u(0x00000018) -#define SSI_TXFTLR_BITS _u(0x000000ff) -#define SSI_TXFTLR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : SSI_TXFTLR_TFT -// Description : Transmit FIFO threshold -#define SSI_TXFTLR_TFT_RESET _u(0x00) -#define SSI_TXFTLR_TFT_BITS _u(0x000000ff) -#define SSI_TXFTLR_TFT_MSB _u(7) -#define SSI_TXFTLR_TFT_LSB _u(0) -#define SSI_TXFTLR_TFT_ACCESS "RW" -// ============================================================================= -// Register : SSI_RXFTLR -// Description : RX FIFO threshold level -#define SSI_RXFTLR_OFFSET _u(0x0000001c) -#define SSI_RXFTLR_BITS _u(0x000000ff) -#define SSI_RXFTLR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : SSI_RXFTLR_RFT -// Description : Receive FIFO threshold -#define SSI_RXFTLR_RFT_RESET _u(0x00) -#define SSI_RXFTLR_RFT_BITS _u(0x000000ff) -#define SSI_RXFTLR_RFT_MSB _u(7) -#define SSI_RXFTLR_RFT_LSB _u(0) -#define SSI_RXFTLR_RFT_ACCESS "RW" -// ============================================================================= -// Register : SSI_TXFLR -// Description : TX FIFO level -#define SSI_TXFLR_OFFSET _u(0x00000020) -#define SSI_TXFLR_BITS _u(0x000000ff) -#define SSI_TXFLR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : SSI_TXFLR_TFTFL -// Description : Transmit FIFO level -#define SSI_TXFLR_TFTFL_RESET _u(0x00) -#define SSI_TXFLR_TFTFL_BITS _u(0x000000ff) -#define SSI_TXFLR_TFTFL_MSB _u(7) -#define SSI_TXFLR_TFTFL_LSB _u(0) -#define SSI_TXFLR_TFTFL_ACCESS "RO" -// ============================================================================= -// Register : SSI_RXFLR -// Description : RX FIFO level -#define SSI_RXFLR_OFFSET _u(0x00000024) -#define SSI_RXFLR_BITS _u(0x000000ff) -#define SSI_RXFLR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : SSI_RXFLR_RXTFL -// Description : Receive FIFO level -#define SSI_RXFLR_RXTFL_RESET _u(0x00) -#define SSI_RXFLR_RXTFL_BITS _u(0x000000ff) -#define SSI_RXFLR_RXTFL_MSB _u(7) -#define SSI_RXFLR_RXTFL_LSB _u(0) -#define SSI_RXFLR_RXTFL_ACCESS "RO" -// ============================================================================= -// Register : SSI_SR -// Description : Status register -#define SSI_SR_OFFSET _u(0x00000028) -#define SSI_SR_BITS _u(0x0000007f) -#define SSI_SR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : SSI_SR_DCOL -// Description : Data collision error -#define SSI_SR_DCOL_RESET _u(0x0) -#define SSI_SR_DCOL_BITS _u(0x00000040) -#define SSI_SR_DCOL_MSB _u(6) -#define SSI_SR_DCOL_LSB _u(6) -#define SSI_SR_DCOL_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : SSI_SR_TXE -// Description : Transmission error -#define SSI_SR_TXE_RESET _u(0x0) -#define SSI_SR_TXE_BITS _u(0x00000020) -#define SSI_SR_TXE_MSB _u(5) -#define SSI_SR_TXE_LSB _u(5) -#define SSI_SR_TXE_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : SSI_SR_RFF -// Description : Receive FIFO full -#define SSI_SR_RFF_RESET _u(0x0) -#define SSI_SR_RFF_BITS _u(0x00000010) -#define SSI_SR_RFF_MSB _u(4) -#define SSI_SR_RFF_LSB _u(4) -#define SSI_SR_RFF_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : SSI_SR_RFNE -// Description : Receive FIFO not empty -#define SSI_SR_RFNE_RESET _u(0x0) -#define SSI_SR_RFNE_BITS _u(0x00000008) -#define SSI_SR_RFNE_MSB _u(3) -#define SSI_SR_RFNE_LSB _u(3) -#define SSI_SR_RFNE_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : SSI_SR_TFE -// Description : Transmit FIFO empty -#define SSI_SR_TFE_RESET _u(0x0) -#define SSI_SR_TFE_BITS _u(0x00000004) -#define SSI_SR_TFE_MSB _u(2) -#define SSI_SR_TFE_LSB _u(2) -#define SSI_SR_TFE_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : SSI_SR_TFNF -// Description : Transmit FIFO not full -#define SSI_SR_TFNF_RESET _u(0x0) -#define SSI_SR_TFNF_BITS _u(0x00000002) -#define SSI_SR_TFNF_MSB _u(1) -#define SSI_SR_TFNF_LSB _u(1) -#define SSI_SR_TFNF_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : SSI_SR_BUSY -// Description : SSI busy flag -#define SSI_SR_BUSY_RESET _u(0x0) -#define SSI_SR_BUSY_BITS _u(0x00000001) -#define SSI_SR_BUSY_MSB _u(0) -#define SSI_SR_BUSY_LSB _u(0) -#define SSI_SR_BUSY_ACCESS "RO" -// ============================================================================= -// Register : SSI_IMR -// Description : Interrupt mask -#define SSI_IMR_OFFSET _u(0x0000002c) -#define SSI_IMR_BITS _u(0x0000003f) -#define SSI_IMR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : SSI_IMR_MSTIM -// Description : Multi-master contention interrupt mask -#define SSI_IMR_MSTIM_RESET _u(0x0) -#define SSI_IMR_MSTIM_BITS _u(0x00000020) -#define SSI_IMR_MSTIM_MSB _u(5) -#define SSI_IMR_MSTIM_LSB _u(5) -#define SSI_IMR_MSTIM_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SSI_IMR_RXFIM -// Description : Receive FIFO full interrupt mask -#define SSI_IMR_RXFIM_RESET _u(0x0) -#define SSI_IMR_RXFIM_BITS _u(0x00000010) -#define SSI_IMR_RXFIM_MSB _u(4) -#define SSI_IMR_RXFIM_LSB _u(4) -#define SSI_IMR_RXFIM_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SSI_IMR_RXOIM -// Description : Receive FIFO overflow interrupt mask -#define SSI_IMR_RXOIM_RESET _u(0x0) -#define SSI_IMR_RXOIM_BITS _u(0x00000008) -#define SSI_IMR_RXOIM_MSB _u(3) -#define SSI_IMR_RXOIM_LSB _u(3) -#define SSI_IMR_RXOIM_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SSI_IMR_RXUIM -// Description : Receive FIFO underflow interrupt mask -#define SSI_IMR_RXUIM_RESET _u(0x0) -#define SSI_IMR_RXUIM_BITS _u(0x00000004) -#define SSI_IMR_RXUIM_MSB _u(2) -#define SSI_IMR_RXUIM_LSB _u(2) -#define SSI_IMR_RXUIM_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SSI_IMR_TXOIM -// Description : Transmit FIFO overflow interrupt mask -#define SSI_IMR_TXOIM_RESET _u(0x0) -#define SSI_IMR_TXOIM_BITS _u(0x00000002) -#define SSI_IMR_TXOIM_MSB _u(1) -#define SSI_IMR_TXOIM_LSB _u(1) -#define SSI_IMR_TXOIM_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SSI_IMR_TXEIM -// Description : Transmit FIFO empty interrupt mask -#define SSI_IMR_TXEIM_RESET _u(0x0) -#define SSI_IMR_TXEIM_BITS _u(0x00000001) -#define SSI_IMR_TXEIM_MSB _u(0) -#define SSI_IMR_TXEIM_LSB _u(0) -#define SSI_IMR_TXEIM_ACCESS "RW" -// ============================================================================= -// Register : SSI_ISR -// Description : Interrupt status -#define SSI_ISR_OFFSET _u(0x00000030) -#define SSI_ISR_BITS _u(0x0000003f) -#define SSI_ISR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : SSI_ISR_MSTIS -// Description : Multi-master contention interrupt status -#define SSI_ISR_MSTIS_RESET _u(0x0) -#define SSI_ISR_MSTIS_BITS _u(0x00000020) -#define SSI_ISR_MSTIS_MSB _u(5) -#define SSI_ISR_MSTIS_LSB _u(5) -#define SSI_ISR_MSTIS_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : SSI_ISR_RXFIS -// Description : Receive FIFO full interrupt status -#define SSI_ISR_RXFIS_RESET _u(0x0) -#define SSI_ISR_RXFIS_BITS _u(0x00000010) -#define SSI_ISR_RXFIS_MSB _u(4) -#define SSI_ISR_RXFIS_LSB _u(4) -#define SSI_ISR_RXFIS_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : SSI_ISR_RXOIS -// Description : Receive FIFO overflow interrupt status -#define SSI_ISR_RXOIS_RESET _u(0x0) -#define SSI_ISR_RXOIS_BITS _u(0x00000008) -#define SSI_ISR_RXOIS_MSB _u(3) -#define SSI_ISR_RXOIS_LSB _u(3) -#define SSI_ISR_RXOIS_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : SSI_ISR_RXUIS -// Description : Receive FIFO underflow interrupt status -#define SSI_ISR_RXUIS_RESET _u(0x0) -#define SSI_ISR_RXUIS_BITS _u(0x00000004) -#define SSI_ISR_RXUIS_MSB _u(2) -#define SSI_ISR_RXUIS_LSB _u(2) -#define SSI_ISR_RXUIS_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : SSI_ISR_TXOIS -// Description : Transmit FIFO overflow interrupt status -#define SSI_ISR_TXOIS_RESET _u(0x0) -#define SSI_ISR_TXOIS_BITS _u(0x00000002) -#define SSI_ISR_TXOIS_MSB _u(1) -#define SSI_ISR_TXOIS_LSB _u(1) -#define SSI_ISR_TXOIS_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : SSI_ISR_TXEIS -// Description : Transmit FIFO empty interrupt status -#define SSI_ISR_TXEIS_RESET _u(0x0) -#define SSI_ISR_TXEIS_BITS _u(0x00000001) -#define SSI_ISR_TXEIS_MSB _u(0) -#define SSI_ISR_TXEIS_LSB _u(0) -#define SSI_ISR_TXEIS_ACCESS "RO" -// ============================================================================= -// Register : SSI_RISR -// Description : Raw interrupt status -#define SSI_RISR_OFFSET _u(0x00000034) -#define SSI_RISR_BITS _u(0x0000003f) -#define SSI_RISR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : SSI_RISR_MSTIR -// Description : Multi-master contention raw interrupt status -#define SSI_RISR_MSTIR_RESET _u(0x0) -#define SSI_RISR_MSTIR_BITS _u(0x00000020) -#define SSI_RISR_MSTIR_MSB _u(5) -#define SSI_RISR_MSTIR_LSB _u(5) -#define SSI_RISR_MSTIR_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : SSI_RISR_RXFIR -// Description : Receive FIFO full raw interrupt status -#define SSI_RISR_RXFIR_RESET _u(0x0) -#define SSI_RISR_RXFIR_BITS _u(0x00000010) -#define SSI_RISR_RXFIR_MSB _u(4) -#define SSI_RISR_RXFIR_LSB _u(4) -#define SSI_RISR_RXFIR_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : SSI_RISR_RXOIR -// Description : Receive FIFO overflow raw interrupt status -#define SSI_RISR_RXOIR_RESET _u(0x0) -#define SSI_RISR_RXOIR_BITS _u(0x00000008) -#define SSI_RISR_RXOIR_MSB _u(3) -#define SSI_RISR_RXOIR_LSB _u(3) -#define SSI_RISR_RXOIR_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : SSI_RISR_RXUIR -// Description : Receive FIFO underflow raw interrupt status -#define SSI_RISR_RXUIR_RESET _u(0x0) -#define SSI_RISR_RXUIR_BITS _u(0x00000004) -#define SSI_RISR_RXUIR_MSB _u(2) -#define SSI_RISR_RXUIR_LSB _u(2) -#define SSI_RISR_RXUIR_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : SSI_RISR_TXOIR -// Description : Transmit FIFO overflow raw interrupt status -#define SSI_RISR_TXOIR_RESET _u(0x0) -#define SSI_RISR_TXOIR_BITS _u(0x00000002) -#define SSI_RISR_TXOIR_MSB _u(1) -#define SSI_RISR_TXOIR_LSB _u(1) -#define SSI_RISR_TXOIR_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : SSI_RISR_TXEIR -// Description : Transmit FIFO empty raw interrupt status -#define SSI_RISR_TXEIR_RESET _u(0x0) -#define SSI_RISR_TXEIR_BITS _u(0x00000001) -#define SSI_RISR_TXEIR_MSB _u(0) -#define SSI_RISR_TXEIR_LSB _u(0) -#define SSI_RISR_TXEIR_ACCESS "RO" -// ============================================================================= -// Register : SSI_TXOICR -// Description : TX FIFO overflow interrupt clear -// Clear-on-read transmit FIFO overflow interrupt -#define SSI_TXOICR_OFFSET _u(0x00000038) -#define SSI_TXOICR_BITS _u(0x00000001) -#define SSI_TXOICR_RESET _u(0x00000000) -#define SSI_TXOICR_MSB _u(0) -#define SSI_TXOICR_LSB _u(0) -#define SSI_TXOICR_ACCESS "RO" -// ============================================================================= -// Register : SSI_RXOICR -// Description : RX FIFO overflow interrupt clear -// Clear-on-read receive FIFO overflow interrupt -#define SSI_RXOICR_OFFSET _u(0x0000003c) -#define SSI_RXOICR_BITS _u(0x00000001) -#define SSI_RXOICR_RESET _u(0x00000000) -#define SSI_RXOICR_MSB _u(0) -#define SSI_RXOICR_LSB _u(0) -#define SSI_RXOICR_ACCESS "RO" -// ============================================================================= -// Register : SSI_RXUICR -// Description : RX FIFO underflow interrupt clear -// Clear-on-read receive FIFO underflow interrupt -#define SSI_RXUICR_OFFSET _u(0x00000040) -#define SSI_RXUICR_BITS _u(0x00000001) -#define SSI_RXUICR_RESET _u(0x00000000) -#define SSI_RXUICR_MSB _u(0) -#define SSI_RXUICR_LSB _u(0) -#define SSI_RXUICR_ACCESS "RO" -// ============================================================================= -// Register : SSI_MSTICR -// Description : Multi-master interrupt clear -// Clear-on-read multi-master contention interrupt -#define SSI_MSTICR_OFFSET _u(0x00000044) -#define SSI_MSTICR_BITS _u(0x00000001) -#define SSI_MSTICR_RESET _u(0x00000000) -#define SSI_MSTICR_MSB _u(0) -#define SSI_MSTICR_LSB _u(0) -#define SSI_MSTICR_ACCESS "RO" -// ============================================================================= -// Register : SSI_ICR -// Description : Interrupt clear -// Clear-on-read all active interrupts -#define SSI_ICR_OFFSET _u(0x00000048) -#define SSI_ICR_BITS _u(0x00000001) -#define SSI_ICR_RESET _u(0x00000000) -#define SSI_ICR_MSB _u(0) -#define SSI_ICR_LSB _u(0) -#define SSI_ICR_ACCESS "RO" -// ============================================================================= -// Register : SSI_DMACR -// Description : DMA control -#define SSI_DMACR_OFFSET _u(0x0000004c) -#define SSI_DMACR_BITS _u(0x00000003) -#define SSI_DMACR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : SSI_DMACR_TDMAE -// Description : Transmit DMA enable -#define SSI_DMACR_TDMAE_RESET _u(0x0) -#define SSI_DMACR_TDMAE_BITS _u(0x00000002) -#define SSI_DMACR_TDMAE_MSB _u(1) -#define SSI_DMACR_TDMAE_LSB _u(1) -#define SSI_DMACR_TDMAE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SSI_DMACR_RDMAE -// Description : Receive DMA enable -#define SSI_DMACR_RDMAE_RESET _u(0x0) -#define SSI_DMACR_RDMAE_BITS _u(0x00000001) -#define SSI_DMACR_RDMAE_MSB _u(0) -#define SSI_DMACR_RDMAE_LSB _u(0) -#define SSI_DMACR_RDMAE_ACCESS "RW" -// ============================================================================= -// Register : SSI_DMATDLR -// Description : DMA TX data level -#define SSI_DMATDLR_OFFSET _u(0x00000050) -#define SSI_DMATDLR_BITS _u(0x000000ff) -#define SSI_DMATDLR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : SSI_DMATDLR_DMATDL -// Description : Transmit data watermark level -#define SSI_DMATDLR_DMATDL_RESET _u(0x00) -#define SSI_DMATDLR_DMATDL_BITS _u(0x000000ff) -#define SSI_DMATDLR_DMATDL_MSB _u(7) -#define SSI_DMATDLR_DMATDL_LSB _u(0) -#define SSI_DMATDLR_DMATDL_ACCESS "RW" -// ============================================================================= -// Register : SSI_DMARDLR -// Description : DMA RX data level -#define SSI_DMARDLR_OFFSET _u(0x00000054) -#define SSI_DMARDLR_BITS _u(0x000000ff) -#define SSI_DMARDLR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : SSI_DMARDLR_DMARDL -// Description : Receive data watermark level (DMARDLR+1) -#define SSI_DMARDLR_DMARDL_RESET _u(0x00) -#define SSI_DMARDLR_DMARDL_BITS _u(0x000000ff) -#define SSI_DMARDLR_DMARDL_MSB _u(7) -#define SSI_DMARDLR_DMARDL_LSB _u(0) -#define SSI_DMARDLR_DMARDL_ACCESS "RW" -// ============================================================================= -// Register : SSI_IDR -// Description : Identification register -#define SSI_IDR_OFFSET _u(0x00000058) -#define SSI_IDR_BITS _u(0xffffffff) -#define SSI_IDR_RESET _u(0x51535049) -// ----------------------------------------------------------------------------- -// Field : SSI_IDR_IDCODE -// Description : Peripheral dentification code -#define SSI_IDR_IDCODE_RESET _u(0x51535049) -#define SSI_IDR_IDCODE_BITS _u(0xffffffff) -#define SSI_IDR_IDCODE_MSB _u(31) -#define SSI_IDR_IDCODE_LSB _u(0) -#define SSI_IDR_IDCODE_ACCESS "RO" -// ============================================================================= -// Register : SSI_SSI_VERSION_ID -// Description : Version ID -#define SSI_SSI_VERSION_ID_OFFSET _u(0x0000005c) -#define SSI_SSI_VERSION_ID_BITS _u(0xffffffff) -#define SSI_SSI_VERSION_ID_RESET _u(0x3430312a) -// ----------------------------------------------------------------------------- -// Field : SSI_SSI_VERSION_ID_SSI_COMP_VERSION -// Description : SNPS component version (format X.YY) -#define SSI_SSI_VERSION_ID_SSI_COMP_VERSION_RESET _u(0x3430312a) -#define SSI_SSI_VERSION_ID_SSI_COMP_VERSION_BITS _u(0xffffffff) -#define SSI_SSI_VERSION_ID_SSI_COMP_VERSION_MSB _u(31) -#define SSI_SSI_VERSION_ID_SSI_COMP_VERSION_LSB _u(0) -#define SSI_SSI_VERSION_ID_SSI_COMP_VERSION_ACCESS "RO" -// ============================================================================= -// Register : SSI_DR0 -// Description : Data Register 0 (of 36) -#define SSI_DR0_OFFSET _u(0x00000060) -#define SSI_DR0_BITS _u(0xffffffff) -#define SSI_DR0_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : SSI_DR0_DR -// Description : First data register of 36 -#define SSI_DR0_DR_RESET _u(0x00000000) -#define SSI_DR0_DR_BITS _u(0xffffffff) -#define SSI_DR0_DR_MSB _u(31) -#define SSI_DR0_DR_LSB _u(0) -#define SSI_DR0_DR_ACCESS "RW" -// ============================================================================= -// Register : SSI_RX_SAMPLE_DLY -// Description : RX sample delay -#define SSI_RX_SAMPLE_DLY_OFFSET _u(0x000000f0) -#define SSI_RX_SAMPLE_DLY_BITS _u(0x000000ff) -#define SSI_RX_SAMPLE_DLY_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : SSI_RX_SAMPLE_DLY_RSD -// Description : RXD sample delay (in SCLK cycles) -#define SSI_RX_SAMPLE_DLY_RSD_RESET _u(0x00) -#define SSI_RX_SAMPLE_DLY_RSD_BITS _u(0x000000ff) -#define SSI_RX_SAMPLE_DLY_RSD_MSB _u(7) -#define SSI_RX_SAMPLE_DLY_RSD_LSB _u(0) -#define SSI_RX_SAMPLE_DLY_RSD_ACCESS "RW" -// ============================================================================= -// Register : SSI_SPI_CTRLR0 -// Description : SPI control -#define SSI_SPI_CTRLR0_OFFSET _u(0x000000f4) -#define SSI_SPI_CTRLR0_BITS _u(0xff07fb3f) -#define SSI_SPI_CTRLR0_RESET _u(0x03000000) -// ----------------------------------------------------------------------------- -// Field : SSI_SPI_CTRLR0_XIP_CMD -// Description : SPI Command to send in XIP mode (INST_L = 8-bit) or to append -// to Address (INST_L = 0-bit) -#define SSI_SPI_CTRLR0_XIP_CMD_RESET _u(0x03) -#define SSI_SPI_CTRLR0_XIP_CMD_BITS _u(0xff000000) -#define SSI_SPI_CTRLR0_XIP_CMD_MSB _u(31) -#define SSI_SPI_CTRLR0_XIP_CMD_LSB _u(24) -#define SSI_SPI_CTRLR0_XIP_CMD_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SSI_SPI_CTRLR0_SPI_RXDS_EN -// Description : Read data strobe enable -#define SSI_SPI_CTRLR0_SPI_RXDS_EN_RESET _u(0x0) -#define SSI_SPI_CTRLR0_SPI_RXDS_EN_BITS _u(0x00040000) -#define SSI_SPI_CTRLR0_SPI_RXDS_EN_MSB _u(18) -#define SSI_SPI_CTRLR0_SPI_RXDS_EN_LSB _u(18) -#define SSI_SPI_CTRLR0_SPI_RXDS_EN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SSI_SPI_CTRLR0_INST_DDR_EN -// Description : Instruction DDR transfer enable -#define SSI_SPI_CTRLR0_INST_DDR_EN_RESET _u(0x0) -#define SSI_SPI_CTRLR0_INST_DDR_EN_BITS _u(0x00020000) -#define SSI_SPI_CTRLR0_INST_DDR_EN_MSB _u(17) -#define SSI_SPI_CTRLR0_INST_DDR_EN_LSB _u(17) -#define SSI_SPI_CTRLR0_INST_DDR_EN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SSI_SPI_CTRLR0_SPI_DDR_EN -// Description : SPI DDR transfer enable -#define SSI_SPI_CTRLR0_SPI_DDR_EN_RESET _u(0x0) -#define SSI_SPI_CTRLR0_SPI_DDR_EN_BITS _u(0x00010000) -#define SSI_SPI_CTRLR0_SPI_DDR_EN_MSB _u(16) -#define SSI_SPI_CTRLR0_SPI_DDR_EN_LSB _u(16) -#define SSI_SPI_CTRLR0_SPI_DDR_EN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SSI_SPI_CTRLR0_WAIT_CYCLES -// Description : Wait cycles between control frame transmit and data reception -// (in SCLK cycles) -#define SSI_SPI_CTRLR0_WAIT_CYCLES_RESET _u(0x00) -#define SSI_SPI_CTRLR0_WAIT_CYCLES_BITS _u(0x0000f800) -#define SSI_SPI_CTRLR0_WAIT_CYCLES_MSB _u(15) -#define SSI_SPI_CTRLR0_WAIT_CYCLES_LSB _u(11) -#define SSI_SPI_CTRLR0_WAIT_CYCLES_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SSI_SPI_CTRLR0_INST_L -// Description : Instruction length (0/4/8/16b) -// 0x0 -> No instruction -// 0x1 -> 4-bit instruction -// 0x2 -> 8-bit instruction -// 0x3 -> 16-bit instruction -#define SSI_SPI_CTRLR0_INST_L_RESET _u(0x0) -#define SSI_SPI_CTRLR0_INST_L_BITS _u(0x00000300) -#define SSI_SPI_CTRLR0_INST_L_MSB _u(9) -#define SSI_SPI_CTRLR0_INST_L_LSB _u(8) -#define SSI_SPI_CTRLR0_INST_L_ACCESS "RW" -#define SSI_SPI_CTRLR0_INST_L_VALUE_NONE _u(0x0) -#define SSI_SPI_CTRLR0_INST_L_VALUE_4B _u(0x1) -#define SSI_SPI_CTRLR0_INST_L_VALUE_8B _u(0x2) -#define SSI_SPI_CTRLR0_INST_L_VALUE_16B _u(0x3) -// ----------------------------------------------------------------------------- -// Field : SSI_SPI_CTRLR0_ADDR_L -// Description : Address length (0b-60b in 4b increments) -#define SSI_SPI_CTRLR0_ADDR_L_RESET _u(0x0) -#define SSI_SPI_CTRLR0_ADDR_L_BITS _u(0x0000003c) -#define SSI_SPI_CTRLR0_ADDR_L_MSB _u(5) -#define SSI_SPI_CTRLR0_ADDR_L_LSB _u(2) -#define SSI_SPI_CTRLR0_ADDR_L_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SSI_SPI_CTRLR0_TRANS_TYPE -// Description : Address and instruction transfer format -// 0x0 -> Command and address both in standard SPI frame format -// 0x1 -> Command in standard SPI format, address in format specified by FRF -// 0x2 -> Command and address both in format specified by FRF (e.g. Dual-SPI) -#define SSI_SPI_CTRLR0_TRANS_TYPE_RESET _u(0x0) -#define SSI_SPI_CTRLR0_TRANS_TYPE_BITS _u(0x00000003) -#define SSI_SPI_CTRLR0_TRANS_TYPE_MSB _u(1) -#define SSI_SPI_CTRLR0_TRANS_TYPE_LSB _u(0) -#define SSI_SPI_CTRLR0_TRANS_TYPE_ACCESS "RW" -#define SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_1C1A _u(0x0) -#define SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_1C2A _u(0x1) -#define SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_2C2A _u(0x2) -// ============================================================================= -// Register : SSI_TXD_DRIVE_EDGE -// Description : TX drive edge -#define SSI_TXD_DRIVE_EDGE_OFFSET _u(0x000000f8) -#define SSI_TXD_DRIVE_EDGE_BITS _u(0x000000ff) -#define SSI_TXD_DRIVE_EDGE_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : SSI_TXD_DRIVE_EDGE_TDE -// Description : TXD drive edge -#define SSI_TXD_DRIVE_EDGE_TDE_RESET _u(0x00) -#define SSI_TXD_DRIVE_EDGE_TDE_BITS _u(0x000000ff) -#define SSI_TXD_DRIVE_EDGE_TDE_MSB _u(7) -#define SSI_TXD_DRIVE_EDGE_TDE_LSB _u(0) -#define SSI_TXD_DRIVE_EDGE_TDE_ACCESS "RW" -// ============================================================================= -#endif // _HARDWARE_REGS_SSI_H - diff --git a/lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/syscfg.h b/lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/syscfg.h deleted file mode 100644 index 96672bb499..0000000000 --- a/lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/syscfg.h +++ /dev/null @@ -1,252 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -// ============================================================================= -// Register block : SYSCFG -// Version : 1 -// Bus type : apb -// Description : Register block for various chip control signals -// ============================================================================= -#ifndef _HARDWARE_REGS_SYSCFG_H -#define _HARDWARE_REGS_SYSCFG_H -// ============================================================================= -// Register : SYSCFG_PROC0_NMI_MASK -// Description : Processor core 0 NMI source mask -// Set a bit high to enable NMI from that IRQ -#define SYSCFG_PROC0_NMI_MASK_OFFSET _u(0x00000000) -#define SYSCFG_PROC0_NMI_MASK_BITS _u(0xffffffff) -#define SYSCFG_PROC0_NMI_MASK_RESET _u(0x00000000) -#define SYSCFG_PROC0_NMI_MASK_MSB _u(31) -#define SYSCFG_PROC0_NMI_MASK_LSB _u(0) -#define SYSCFG_PROC0_NMI_MASK_ACCESS "RW" -// ============================================================================= -// Register : SYSCFG_PROC1_NMI_MASK -// Description : Processor core 1 NMI source mask -// Set a bit high to enable NMI from that IRQ -#define SYSCFG_PROC1_NMI_MASK_OFFSET _u(0x00000004) -#define SYSCFG_PROC1_NMI_MASK_BITS _u(0xffffffff) -#define SYSCFG_PROC1_NMI_MASK_RESET _u(0x00000000) -#define SYSCFG_PROC1_NMI_MASK_MSB _u(31) -#define SYSCFG_PROC1_NMI_MASK_LSB _u(0) -#define SYSCFG_PROC1_NMI_MASK_ACCESS "RW" -// ============================================================================= -// Register : SYSCFG_PROC_CONFIG -// Description : Configuration for processors -#define SYSCFG_PROC_CONFIG_OFFSET _u(0x00000008) -#define SYSCFG_PROC_CONFIG_BITS _u(0xff000003) -#define SYSCFG_PROC_CONFIG_RESET _u(0x10000000) -// ----------------------------------------------------------------------------- -// Field : SYSCFG_PROC_CONFIG_PROC1_DAP_INSTID -// Description : Configure proc1 DAP instance ID. -// Recommend that this is NOT changed until you require debug -// access in multi-chip environment -// WARNING: do not set to 15 as this is reserved for RescueDP -#define SYSCFG_PROC_CONFIG_PROC1_DAP_INSTID_RESET _u(0x1) -#define SYSCFG_PROC_CONFIG_PROC1_DAP_INSTID_BITS _u(0xf0000000) -#define SYSCFG_PROC_CONFIG_PROC1_DAP_INSTID_MSB _u(31) -#define SYSCFG_PROC_CONFIG_PROC1_DAP_INSTID_LSB _u(28) -#define SYSCFG_PROC_CONFIG_PROC1_DAP_INSTID_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SYSCFG_PROC_CONFIG_PROC0_DAP_INSTID -// Description : Configure proc0 DAP instance ID. -// Recommend that this is NOT changed until you require debug -// access in multi-chip environment -// WARNING: do not set to 15 as this is reserved for RescueDP -#define SYSCFG_PROC_CONFIG_PROC0_DAP_INSTID_RESET _u(0x0) -#define SYSCFG_PROC_CONFIG_PROC0_DAP_INSTID_BITS _u(0x0f000000) -#define SYSCFG_PROC_CONFIG_PROC0_DAP_INSTID_MSB _u(27) -#define SYSCFG_PROC_CONFIG_PROC0_DAP_INSTID_LSB _u(24) -#define SYSCFG_PROC_CONFIG_PROC0_DAP_INSTID_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SYSCFG_PROC_CONFIG_PROC1_HALTED -// Description : Indication that proc1 has halted -#define SYSCFG_PROC_CONFIG_PROC1_HALTED_RESET _u(0x0) -#define SYSCFG_PROC_CONFIG_PROC1_HALTED_BITS _u(0x00000002) -#define SYSCFG_PROC_CONFIG_PROC1_HALTED_MSB _u(1) -#define SYSCFG_PROC_CONFIG_PROC1_HALTED_LSB _u(1) -#define SYSCFG_PROC_CONFIG_PROC1_HALTED_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : SYSCFG_PROC_CONFIG_PROC0_HALTED -// Description : Indication that proc0 has halted -#define SYSCFG_PROC_CONFIG_PROC0_HALTED_RESET _u(0x0) -#define SYSCFG_PROC_CONFIG_PROC0_HALTED_BITS _u(0x00000001) -#define SYSCFG_PROC_CONFIG_PROC0_HALTED_MSB _u(0) -#define SYSCFG_PROC_CONFIG_PROC0_HALTED_LSB _u(0) -#define SYSCFG_PROC_CONFIG_PROC0_HALTED_ACCESS "RO" -// ============================================================================= -// Register : SYSCFG_PROC_IN_SYNC_BYPASS -// Description : For each bit, if 1, bypass the input synchronizer between that -// GPIO -// and the GPIO input register in the SIO. The input synchronizers -// should -// generally be unbypassed, to avoid injecting metastabilities -// into processors. -// If you're feeling brave, you can bypass to save two cycles of -// input -// latency. This register applies to GPIO 0...29. -#define SYSCFG_PROC_IN_SYNC_BYPASS_OFFSET _u(0x0000000c) -#define SYSCFG_PROC_IN_SYNC_BYPASS_BITS _u(0x3fffffff) -#define SYSCFG_PROC_IN_SYNC_BYPASS_RESET _u(0x00000000) -#define SYSCFG_PROC_IN_SYNC_BYPASS_MSB _u(29) -#define SYSCFG_PROC_IN_SYNC_BYPASS_LSB _u(0) -#define SYSCFG_PROC_IN_SYNC_BYPASS_ACCESS "RW" -// ============================================================================= -// Register : SYSCFG_PROC_IN_SYNC_BYPASS_HI -// Description : For each bit, if 1, bypass the input synchronizer between that -// GPIO -// and the GPIO input register in the SIO. The input synchronizers -// should -// generally be unbypassed, to avoid injecting metastabilities -// into processors. -// If you're feeling brave, you can bypass to save two cycles of -// input -// latency. This register applies to GPIO 30...35 (the QSPI IOs). -#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_OFFSET _u(0x00000010) -#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_BITS _u(0x0000003f) -#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_RESET _u(0x00000000) -#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_MSB _u(5) -#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_LSB _u(0) -#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_ACCESS "RW" -// ============================================================================= -// Register : SYSCFG_DBGFORCE -// Description : Directly control the SWD debug port of either processor -#define SYSCFG_DBGFORCE_OFFSET _u(0x00000014) -#define SYSCFG_DBGFORCE_BITS _u(0x000000ff) -#define SYSCFG_DBGFORCE_RESET _u(0x00000066) -// ----------------------------------------------------------------------------- -// Field : SYSCFG_DBGFORCE_PROC1_ATTACH -// Description : Attach processor 1 debug port to syscfg controls, and -// disconnect it from external SWD pads. -#define SYSCFG_DBGFORCE_PROC1_ATTACH_RESET _u(0x0) -#define SYSCFG_DBGFORCE_PROC1_ATTACH_BITS _u(0x00000080) -#define SYSCFG_DBGFORCE_PROC1_ATTACH_MSB _u(7) -#define SYSCFG_DBGFORCE_PROC1_ATTACH_LSB _u(7) -#define SYSCFG_DBGFORCE_PROC1_ATTACH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SYSCFG_DBGFORCE_PROC1_SWCLK -// Description : Directly drive processor 1 SWCLK, if PROC1_ATTACH is set -#define SYSCFG_DBGFORCE_PROC1_SWCLK_RESET _u(0x1) -#define SYSCFG_DBGFORCE_PROC1_SWCLK_BITS _u(0x00000040) -#define SYSCFG_DBGFORCE_PROC1_SWCLK_MSB _u(6) -#define SYSCFG_DBGFORCE_PROC1_SWCLK_LSB _u(6) -#define SYSCFG_DBGFORCE_PROC1_SWCLK_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SYSCFG_DBGFORCE_PROC1_SWDI -// Description : Directly drive processor 1 SWDIO input, if PROC1_ATTACH is set -#define SYSCFG_DBGFORCE_PROC1_SWDI_RESET _u(0x1) -#define SYSCFG_DBGFORCE_PROC1_SWDI_BITS _u(0x00000020) -#define SYSCFG_DBGFORCE_PROC1_SWDI_MSB _u(5) -#define SYSCFG_DBGFORCE_PROC1_SWDI_LSB _u(5) -#define SYSCFG_DBGFORCE_PROC1_SWDI_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SYSCFG_DBGFORCE_PROC1_SWDO -// Description : Observe the value of processor 1 SWDIO output. -#define SYSCFG_DBGFORCE_PROC1_SWDO_RESET "-" -#define SYSCFG_DBGFORCE_PROC1_SWDO_BITS _u(0x00000010) -#define SYSCFG_DBGFORCE_PROC1_SWDO_MSB _u(4) -#define SYSCFG_DBGFORCE_PROC1_SWDO_LSB _u(4) -#define SYSCFG_DBGFORCE_PROC1_SWDO_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : SYSCFG_DBGFORCE_PROC0_ATTACH -// Description : Attach processor 0 debug port to syscfg controls, and -// disconnect it from external SWD pads. -#define SYSCFG_DBGFORCE_PROC0_ATTACH_RESET _u(0x0) -#define SYSCFG_DBGFORCE_PROC0_ATTACH_BITS _u(0x00000008) -#define SYSCFG_DBGFORCE_PROC0_ATTACH_MSB _u(3) -#define SYSCFG_DBGFORCE_PROC0_ATTACH_LSB _u(3) -#define SYSCFG_DBGFORCE_PROC0_ATTACH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SYSCFG_DBGFORCE_PROC0_SWCLK -// Description : Directly drive processor 0 SWCLK, if PROC0_ATTACH is set -#define SYSCFG_DBGFORCE_PROC0_SWCLK_RESET _u(0x1) -#define SYSCFG_DBGFORCE_PROC0_SWCLK_BITS _u(0x00000004) -#define SYSCFG_DBGFORCE_PROC0_SWCLK_MSB _u(2) -#define SYSCFG_DBGFORCE_PROC0_SWCLK_LSB _u(2) -#define SYSCFG_DBGFORCE_PROC0_SWCLK_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SYSCFG_DBGFORCE_PROC0_SWDI -// Description : Directly drive processor 0 SWDIO input, if PROC0_ATTACH is set -#define SYSCFG_DBGFORCE_PROC0_SWDI_RESET _u(0x1) -#define SYSCFG_DBGFORCE_PROC0_SWDI_BITS _u(0x00000002) -#define SYSCFG_DBGFORCE_PROC0_SWDI_MSB _u(1) -#define SYSCFG_DBGFORCE_PROC0_SWDI_LSB _u(1) -#define SYSCFG_DBGFORCE_PROC0_SWDI_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SYSCFG_DBGFORCE_PROC0_SWDO -// Description : Observe the value of processor 0 SWDIO output. -#define SYSCFG_DBGFORCE_PROC0_SWDO_RESET "-" -#define SYSCFG_DBGFORCE_PROC0_SWDO_BITS _u(0x00000001) -#define SYSCFG_DBGFORCE_PROC0_SWDO_MSB _u(0) -#define SYSCFG_DBGFORCE_PROC0_SWDO_LSB _u(0) -#define SYSCFG_DBGFORCE_PROC0_SWDO_ACCESS "RO" -// ============================================================================= -// Register : SYSCFG_MEMPOWERDOWN -// Description : Control power downs to memories. Set high to power down -// memories. -// Use with extreme caution -#define SYSCFG_MEMPOWERDOWN_OFFSET _u(0x00000018) -#define SYSCFG_MEMPOWERDOWN_BITS _u(0x000000ff) -#define SYSCFG_MEMPOWERDOWN_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : SYSCFG_MEMPOWERDOWN_ROM -#define SYSCFG_MEMPOWERDOWN_ROM_RESET _u(0x0) -#define SYSCFG_MEMPOWERDOWN_ROM_BITS _u(0x00000080) -#define SYSCFG_MEMPOWERDOWN_ROM_MSB _u(7) -#define SYSCFG_MEMPOWERDOWN_ROM_LSB _u(7) -#define SYSCFG_MEMPOWERDOWN_ROM_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SYSCFG_MEMPOWERDOWN_USB -#define SYSCFG_MEMPOWERDOWN_USB_RESET _u(0x0) -#define SYSCFG_MEMPOWERDOWN_USB_BITS _u(0x00000040) -#define SYSCFG_MEMPOWERDOWN_USB_MSB _u(6) -#define SYSCFG_MEMPOWERDOWN_USB_LSB _u(6) -#define SYSCFG_MEMPOWERDOWN_USB_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SYSCFG_MEMPOWERDOWN_SRAM5 -#define SYSCFG_MEMPOWERDOWN_SRAM5_RESET _u(0x0) -#define SYSCFG_MEMPOWERDOWN_SRAM5_BITS _u(0x00000020) -#define SYSCFG_MEMPOWERDOWN_SRAM5_MSB _u(5) -#define SYSCFG_MEMPOWERDOWN_SRAM5_LSB _u(5) -#define SYSCFG_MEMPOWERDOWN_SRAM5_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SYSCFG_MEMPOWERDOWN_SRAM4 -#define SYSCFG_MEMPOWERDOWN_SRAM4_RESET _u(0x0) -#define SYSCFG_MEMPOWERDOWN_SRAM4_BITS _u(0x00000010) -#define SYSCFG_MEMPOWERDOWN_SRAM4_MSB _u(4) -#define SYSCFG_MEMPOWERDOWN_SRAM4_LSB _u(4) -#define SYSCFG_MEMPOWERDOWN_SRAM4_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SYSCFG_MEMPOWERDOWN_SRAM3 -#define SYSCFG_MEMPOWERDOWN_SRAM3_RESET _u(0x0) -#define SYSCFG_MEMPOWERDOWN_SRAM3_BITS _u(0x00000008) -#define SYSCFG_MEMPOWERDOWN_SRAM3_MSB _u(3) -#define SYSCFG_MEMPOWERDOWN_SRAM3_LSB _u(3) -#define SYSCFG_MEMPOWERDOWN_SRAM3_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SYSCFG_MEMPOWERDOWN_SRAM2 -#define SYSCFG_MEMPOWERDOWN_SRAM2_RESET _u(0x0) -#define SYSCFG_MEMPOWERDOWN_SRAM2_BITS _u(0x00000004) -#define SYSCFG_MEMPOWERDOWN_SRAM2_MSB _u(2) -#define SYSCFG_MEMPOWERDOWN_SRAM2_LSB _u(2) -#define SYSCFG_MEMPOWERDOWN_SRAM2_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SYSCFG_MEMPOWERDOWN_SRAM1 -#define SYSCFG_MEMPOWERDOWN_SRAM1_RESET _u(0x0) -#define SYSCFG_MEMPOWERDOWN_SRAM1_BITS _u(0x00000002) -#define SYSCFG_MEMPOWERDOWN_SRAM1_MSB _u(1) -#define SYSCFG_MEMPOWERDOWN_SRAM1_LSB _u(1) -#define SYSCFG_MEMPOWERDOWN_SRAM1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SYSCFG_MEMPOWERDOWN_SRAM0 -#define SYSCFG_MEMPOWERDOWN_SRAM0_RESET _u(0x0) -#define SYSCFG_MEMPOWERDOWN_SRAM0_BITS _u(0x00000001) -#define SYSCFG_MEMPOWERDOWN_SRAM0_MSB _u(0) -#define SYSCFG_MEMPOWERDOWN_SRAM0_LSB _u(0) -#define SYSCFG_MEMPOWERDOWN_SRAM0_ACCESS "RW" -// ============================================================================= -#endif // _HARDWARE_REGS_SYSCFG_H - diff --git a/lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/sysinfo.h b/lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/sysinfo.h deleted file mode 100644 index e0cf2efabc..0000000000 --- a/lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/sysinfo.h +++ /dev/null @@ -1,74 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -// ============================================================================= -// Register block : SYSINFO -// Version : 1 -// Bus type : apb -// ============================================================================= -#ifndef _HARDWARE_REGS_SYSINFO_H -#define _HARDWARE_REGS_SYSINFO_H -// ============================================================================= -// Register : SYSINFO_CHIP_ID -// Description : JEDEC JEP-106 compliant chip identifier. -#define SYSINFO_CHIP_ID_OFFSET _u(0x00000000) -#define SYSINFO_CHIP_ID_BITS _u(0xffffffff) -#define SYSINFO_CHIP_ID_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : SYSINFO_CHIP_ID_REVISION -#define SYSINFO_CHIP_ID_REVISION_RESET "-" -#define SYSINFO_CHIP_ID_REVISION_BITS _u(0xf0000000) -#define SYSINFO_CHIP_ID_REVISION_MSB _u(31) -#define SYSINFO_CHIP_ID_REVISION_LSB _u(28) -#define SYSINFO_CHIP_ID_REVISION_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : SYSINFO_CHIP_ID_PART -#define SYSINFO_CHIP_ID_PART_RESET "-" -#define SYSINFO_CHIP_ID_PART_BITS _u(0x0ffff000) -#define SYSINFO_CHIP_ID_PART_MSB _u(27) -#define SYSINFO_CHIP_ID_PART_LSB _u(12) -#define SYSINFO_CHIP_ID_PART_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : SYSINFO_CHIP_ID_MANUFACTURER -#define SYSINFO_CHIP_ID_MANUFACTURER_RESET "-" -#define SYSINFO_CHIP_ID_MANUFACTURER_BITS _u(0x00000fff) -#define SYSINFO_CHIP_ID_MANUFACTURER_MSB _u(11) -#define SYSINFO_CHIP_ID_MANUFACTURER_LSB _u(0) -#define SYSINFO_CHIP_ID_MANUFACTURER_ACCESS "RO" -// ============================================================================= -// Register : SYSINFO_PLATFORM -// Description : Platform register. Allows software to know what environment it -// is running in. -#define SYSINFO_PLATFORM_OFFSET _u(0x00000004) -#define SYSINFO_PLATFORM_BITS _u(0x00000003) -#define SYSINFO_PLATFORM_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : SYSINFO_PLATFORM_ASIC -#define SYSINFO_PLATFORM_ASIC_RESET _u(0x0) -#define SYSINFO_PLATFORM_ASIC_BITS _u(0x00000002) -#define SYSINFO_PLATFORM_ASIC_MSB _u(1) -#define SYSINFO_PLATFORM_ASIC_LSB _u(1) -#define SYSINFO_PLATFORM_ASIC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : SYSINFO_PLATFORM_FPGA -#define SYSINFO_PLATFORM_FPGA_RESET _u(0x0) -#define SYSINFO_PLATFORM_FPGA_BITS _u(0x00000001) -#define SYSINFO_PLATFORM_FPGA_MSB _u(0) -#define SYSINFO_PLATFORM_FPGA_LSB _u(0) -#define SYSINFO_PLATFORM_FPGA_ACCESS "RO" -// ============================================================================= -// Register : SYSINFO_GITREF_RP2040 -// Description : Git hash of the chip source. Used to identify chip version. -#define SYSINFO_GITREF_RP2040_OFFSET _u(0x00000010) -#define SYSINFO_GITREF_RP2040_BITS _u(0xffffffff) -#define SYSINFO_GITREF_RP2040_RESET "-" -#define SYSINFO_GITREF_RP2040_MSB _u(31) -#define SYSINFO_GITREF_RP2040_LSB _u(0) -#define SYSINFO_GITREF_RP2040_ACCESS "RO" -// ============================================================================= -#endif // _HARDWARE_REGS_SYSINFO_H - diff --git a/lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/tbman.h b/lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/tbman.h deleted file mode 100644 index 49b627c849..0000000000 --- a/lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/tbman.h +++ /dev/null @@ -1,41 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -// ============================================================================= -// Register block : TBMAN -// Version : 1 -// Bus type : apb -// Description : Testbench manager. Allows the programmer to know what -// platform their software is running on. -// ============================================================================= -#ifndef _HARDWARE_REGS_TBMAN_H -#define _HARDWARE_REGS_TBMAN_H -// ============================================================================= -// Register : TBMAN_PLATFORM -// Description : Indicates the type of platform in use -#define TBMAN_PLATFORM_OFFSET _u(0x00000000) -#define TBMAN_PLATFORM_BITS _u(0x00000003) -#define TBMAN_PLATFORM_RESET _u(0x00000005) -// ----------------------------------------------------------------------------- -// Field : TBMAN_PLATFORM_FPGA -// Description : Indicates the platform is an FPGA -#define TBMAN_PLATFORM_FPGA_RESET _u(0x0) -#define TBMAN_PLATFORM_FPGA_BITS _u(0x00000002) -#define TBMAN_PLATFORM_FPGA_MSB _u(1) -#define TBMAN_PLATFORM_FPGA_LSB _u(1) -#define TBMAN_PLATFORM_FPGA_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : TBMAN_PLATFORM_ASIC -// Description : Indicates the platform is an ASIC -#define TBMAN_PLATFORM_ASIC_RESET _u(0x1) -#define TBMAN_PLATFORM_ASIC_BITS _u(0x00000001) -#define TBMAN_PLATFORM_ASIC_MSB _u(0) -#define TBMAN_PLATFORM_ASIC_LSB _u(0) -#define TBMAN_PLATFORM_ASIC_ACCESS "RO" -// ============================================================================= -#endif // _HARDWARE_REGS_TBMAN_H - diff --git a/lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/timer.h b/lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/timer.h deleted file mode 100644 index 7cdcbb3041..0000000000 --- a/lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/timer.h +++ /dev/null @@ -1,319 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -// ============================================================================= -// Register block : TIMER -// Version : 1 -// Bus type : apb -// Description : Controls time and alarms -// time is a 64 bit value indicating the time in usec since -// power-on -// timeh is the top 32 bits of time & timel is the bottom 32 -// bits -// to change time write to timelw before timehw -// to read time read from timelr before timehr -// An alarm is set by setting alarm_enable and writing to the -// corresponding alarm register -// When an alarm is pending, the corresponding alarm_running -// signal will be high -// An alarm can be cancelled before it has finished by clearing -// the alarm_enable -// When an alarm fires, the corresponding alarm_irq is set and -// alarm_running is cleared -// To clear the interrupt write a 1 to the corresponding -// alarm_irq -// ============================================================================= -#ifndef _HARDWARE_REGS_TIMER_H -#define _HARDWARE_REGS_TIMER_H -// ============================================================================= -// Register : TIMER_TIMEHW -// Description : Write to bits 63:32 of time -// always write timelw before timehw -#define TIMER_TIMEHW_OFFSET _u(0x00000000) -#define TIMER_TIMEHW_BITS _u(0xffffffff) -#define TIMER_TIMEHW_RESET _u(0x00000000) -#define TIMER_TIMEHW_MSB _u(31) -#define TIMER_TIMEHW_LSB _u(0) -#define TIMER_TIMEHW_ACCESS "WF" -// ============================================================================= -// Register : TIMER_TIMELW -// Description : Write to bits 31:0 of time -// writes do not get copied to time until timehw is written -#define TIMER_TIMELW_OFFSET _u(0x00000004) -#define TIMER_TIMELW_BITS _u(0xffffffff) -#define TIMER_TIMELW_RESET _u(0x00000000) -#define TIMER_TIMELW_MSB _u(31) -#define TIMER_TIMELW_LSB _u(0) -#define TIMER_TIMELW_ACCESS "WF" -// ============================================================================= -// Register : TIMER_TIMEHR -// Description : Read from bits 63:32 of time -// always read timelr before timehr -#define TIMER_TIMEHR_OFFSET _u(0x00000008) -#define TIMER_TIMEHR_BITS _u(0xffffffff) -#define TIMER_TIMEHR_RESET _u(0x00000000) -#define TIMER_TIMEHR_MSB _u(31) -#define TIMER_TIMEHR_LSB _u(0) -#define TIMER_TIMEHR_ACCESS "RO" -// ============================================================================= -// Register : TIMER_TIMELR -// Description : Read from bits 31:0 of time -#define TIMER_TIMELR_OFFSET _u(0x0000000c) -#define TIMER_TIMELR_BITS _u(0xffffffff) -#define TIMER_TIMELR_RESET _u(0x00000000) -#define TIMER_TIMELR_MSB _u(31) -#define TIMER_TIMELR_LSB _u(0) -#define TIMER_TIMELR_ACCESS "RO" -// ============================================================================= -// Register : TIMER_ALARM0 -// Description : Arm alarm 0, and configure the time it will fire. -// Once armed, the alarm fires when TIMER_ALARM0 == TIMELR. -// The alarm will disarm itself once it fires, and can -// be disarmed early using the ARMED status register. -#define TIMER_ALARM0_OFFSET _u(0x00000010) -#define TIMER_ALARM0_BITS _u(0xffffffff) -#define TIMER_ALARM0_RESET _u(0x00000000) -#define TIMER_ALARM0_MSB _u(31) -#define TIMER_ALARM0_LSB _u(0) -#define TIMER_ALARM0_ACCESS "RW" -// ============================================================================= -// Register : TIMER_ALARM1 -// Description : Arm alarm 1, and configure the time it will fire. -// Once armed, the alarm fires when TIMER_ALARM1 == TIMELR. -// The alarm will disarm itself once it fires, and can -// be disarmed early using the ARMED status register. -#define TIMER_ALARM1_OFFSET _u(0x00000014) -#define TIMER_ALARM1_BITS _u(0xffffffff) -#define TIMER_ALARM1_RESET _u(0x00000000) -#define TIMER_ALARM1_MSB _u(31) -#define TIMER_ALARM1_LSB _u(0) -#define TIMER_ALARM1_ACCESS "RW" -// ============================================================================= -// Register : TIMER_ALARM2 -// Description : Arm alarm 2, and configure the time it will fire. -// Once armed, the alarm fires when TIMER_ALARM2 == TIMELR. -// The alarm will disarm itself once it fires, and can -// be disarmed early using the ARMED status register. -#define TIMER_ALARM2_OFFSET _u(0x00000018) -#define TIMER_ALARM2_BITS _u(0xffffffff) -#define TIMER_ALARM2_RESET _u(0x00000000) -#define TIMER_ALARM2_MSB _u(31) -#define TIMER_ALARM2_LSB _u(0) -#define TIMER_ALARM2_ACCESS "RW" -// ============================================================================= -// Register : TIMER_ALARM3 -// Description : Arm alarm 3, and configure the time it will fire. -// Once armed, the alarm fires when TIMER_ALARM3 == TIMELR. -// The alarm will disarm itself once it fires, and can -// be disarmed early using the ARMED status register. -#define TIMER_ALARM3_OFFSET _u(0x0000001c) -#define TIMER_ALARM3_BITS _u(0xffffffff) -#define TIMER_ALARM3_RESET _u(0x00000000) -#define TIMER_ALARM3_MSB _u(31) -#define TIMER_ALARM3_LSB _u(0) -#define TIMER_ALARM3_ACCESS "RW" -// ============================================================================= -// Register : TIMER_ARMED -// Description : Indicates the armed/disarmed status of each alarm. -// A write to the corresponding ALARMx register arms the alarm. -// Alarms automatically disarm upon firing, but writing ones here -// will disarm immediately without waiting to fire. -#define TIMER_ARMED_OFFSET _u(0x00000020) -#define TIMER_ARMED_BITS _u(0x0000000f) -#define TIMER_ARMED_RESET _u(0x00000000) -#define TIMER_ARMED_MSB _u(3) -#define TIMER_ARMED_LSB _u(0) -#define TIMER_ARMED_ACCESS "WC" -// ============================================================================= -// Register : TIMER_TIMERAWH -// Description : Raw read from bits 63:32 of time (no side effects) -#define TIMER_TIMERAWH_OFFSET _u(0x00000024) -#define TIMER_TIMERAWH_BITS _u(0xffffffff) -#define TIMER_TIMERAWH_RESET _u(0x00000000) -#define TIMER_TIMERAWH_MSB _u(31) -#define TIMER_TIMERAWH_LSB _u(0) -#define TIMER_TIMERAWH_ACCESS "RO" -// ============================================================================= -// Register : TIMER_TIMERAWL -// Description : Raw read from bits 31:0 of time (no side effects) -#define TIMER_TIMERAWL_OFFSET _u(0x00000028) -#define TIMER_TIMERAWL_BITS _u(0xffffffff) -#define TIMER_TIMERAWL_RESET _u(0x00000000) -#define TIMER_TIMERAWL_MSB _u(31) -#define TIMER_TIMERAWL_LSB _u(0) -#define TIMER_TIMERAWL_ACCESS "RO" -// ============================================================================= -// Register : TIMER_DBGPAUSE -// Description : Set bits high to enable pause when the corresponding debug -// ports are active -#define TIMER_DBGPAUSE_OFFSET _u(0x0000002c) -#define TIMER_DBGPAUSE_BITS _u(0x00000006) -#define TIMER_DBGPAUSE_RESET _u(0x00000007) -// ----------------------------------------------------------------------------- -// Field : TIMER_DBGPAUSE_DBG1 -// Description : Pause when processor 1 is in debug mode -#define TIMER_DBGPAUSE_DBG1_RESET _u(0x1) -#define TIMER_DBGPAUSE_DBG1_BITS _u(0x00000004) -#define TIMER_DBGPAUSE_DBG1_MSB _u(2) -#define TIMER_DBGPAUSE_DBG1_LSB _u(2) -#define TIMER_DBGPAUSE_DBG1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : TIMER_DBGPAUSE_DBG0 -// Description : Pause when processor 0 is in debug mode -#define TIMER_DBGPAUSE_DBG0_RESET _u(0x1) -#define TIMER_DBGPAUSE_DBG0_BITS _u(0x00000002) -#define TIMER_DBGPAUSE_DBG0_MSB _u(1) -#define TIMER_DBGPAUSE_DBG0_LSB _u(1) -#define TIMER_DBGPAUSE_DBG0_ACCESS "RW" -// ============================================================================= -// Register : TIMER_PAUSE -// Description : Set high to pause the timer -#define TIMER_PAUSE_OFFSET _u(0x00000030) -#define TIMER_PAUSE_BITS _u(0x00000001) -#define TIMER_PAUSE_RESET _u(0x00000000) -#define TIMER_PAUSE_MSB _u(0) -#define TIMER_PAUSE_LSB _u(0) -#define TIMER_PAUSE_ACCESS "RW" -// ============================================================================= -// Register : TIMER_INTR -// Description : Raw Interrupts -#define TIMER_INTR_OFFSET _u(0x00000034) -#define TIMER_INTR_BITS _u(0x0000000f) -#define TIMER_INTR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : TIMER_INTR_ALARM_3 -#define TIMER_INTR_ALARM_3_RESET _u(0x0) -#define TIMER_INTR_ALARM_3_BITS _u(0x00000008) -#define TIMER_INTR_ALARM_3_MSB _u(3) -#define TIMER_INTR_ALARM_3_LSB _u(3) -#define TIMER_INTR_ALARM_3_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : TIMER_INTR_ALARM_2 -#define TIMER_INTR_ALARM_2_RESET _u(0x0) -#define TIMER_INTR_ALARM_2_BITS _u(0x00000004) -#define TIMER_INTR_ALARM_2_MSB _u(2) -#define TIMER_INTR_ALARM_2_LSB _u(2) -#define TIMER_INTR_ALARM_2_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : TIMER_INTR_ALARM_1 -#define TIMER_INTR_ALARM_1_RESET _u(0x0) -#define TIMER_INTR_ALARM_1_BITS _u(0x00000002) -#define TIMER_INTR_ALARM_1_MSB _u(1) -#define TIMER_INTR_ALARM_1_LSB _u(1) -#define TIMER_INTR_ALARM_1_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : TIMER_INTR_ALARM_0 -#define TIMER_INTR_ALARM_0_RESET _u(0x0) -#define TIMER_INTR_ALARM_0_BITS _u(0x00000001) -#define TIMER_INTR_ALARM_0_MSB _u(0) -#define TIMER_INTR_ALARM_0_LSB _u(0) -#define TIMER_INTR_ALARM_0_ACCESS "WC" -// ============================================================================= -// Register : TIMER_INTE -// Description : Interrupt Enable -#define TIMER_INTE_OFFSET _u(0x00000038) -#define TIMER_INTE_BITS _u(0x0000000f) -#define TIMER_INTE_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : TIMER_INTE_ALARM_3 -#define TIMER_INTE_ALARM_3_RESET _u(0x0) -#define TIMER_INTE_ALARM_3_BITS _u(0x00000008) -#define TIMER_INTE_ALARM_3_MSB _u(3) -#define TIMER_INTE_ALARM_3_LSB _u(3) -#define TIMER_INTE_ALARM_3_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : TIMER_INTE_ALARM_2 -#define TIMER_INTE_ALARM_2_RESET _u(0x0) -#define TIMER_INTE_ALARM_2_BITS _u(0x00000004) -#define TIMER_INTE_ALARM_2_MSB _u(2) -#define TIMER_INTE_ALARM_2_LSB _u(2) -#define TIMER_INTE_ALARM_2_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : TIMER_INTE_ALARM_1 -#define TIMER_INTE_ALARM_1_RESET _u(0x0) -#define TIMER_INTE_ALARM_1_BITS _u(0x00000002) -#define TIMER_INTE_ALARM_1_MSB _u(1) -#define TIMER_INTE_ALARM_1_LSB _u(1) -#define TIMER_INTE_ALARM_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : TIMER_INTE_ALARM_0 -#define TIMER_INTE_ALARM_0_RESET _u(0x0) -#define TIMER_INTE_ALARM_0_BITS _u(0x00000001) -#define TIMER_INTE_ALARM_0_MSB _u(0) -#define TIMER_INTE_ALARM_0_LSB _u(0) -#define TIMER_INTE_ALARM_0_ACCESS "RW" -// ============================================================================= -// Register : TIMER_INTF -// Description : Interrupt Force -#define TIMER_INTF_OFFSET _u(0x0000003c) -#define TIMER_INTF_BITS _u(0x0000000f) -#define TIMER_INTF_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : TIMER_INTF_ALARM_3 -#define TIMER_INTF_ALARM_3_RESET _u(0x0) -#define TIMER_INTF_ALARM_3_BITS _u(0x00000008) -#define TIMER_INTF_ALARM_3_MSB _u(3) -#define TIMER_INTF_ALARM_3_LSB _u(3) -#define TIMER_INTF_ALARM_3_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : TIMER_INTF_ALARM_2 -#define TIMER_INTF_ALARM_2_RESET _u(0x0) -#define TIMER_INTF_ALARM_2_BITS _u(0x00000004) -#define TIMER_INTF_ALARM_2_MSB _u(2) -#define TIMER_INTF_ALARM_2_LSB _u(2) -#define TIMER_INTF_ALARM_2_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : TIMER_INTF_ALARM_1 -#define TIMER_INTF_ALARM_1_RESET _u(0x0) -#define TIMER_INTF_ALARM_1_BITS _u(0x00000002) -#define TIMER_INTF_ALARM_1_MSB _u(1) -#define TIMER_INTF_ALARM_1_LSB _u(1) -#define TIMER_INTF_ALARM_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : TIMER_INTF_ALARM_0 -#define TIMER_INTF_ALARM_0_RESET _u(0x0) -#define TIMER_INTF_ALARM_0_BITS _u(0x00000001) -#define TIMER_INTF_ALARM_0_MSB _u(0) -#define TIMER_INTF_ALARM_0_LSB _u(0) -#define TIMER_INTF_ALARM_0_ACCESS "RW" -// ============================================================================= -// Register : TIMER_INTS -// Description : Interrupt status after masking & forcing -#define TIMER_INTS_OFFSET _u(0x00000040) -#define TIMER_INTS_BITS _u(0x0000000f) -#define TIMER_INTS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : TIMER_INTS_ALARM_3 -#define TIMER_INTS_ALARM_3_RESET _u(0x0) -#define TIMER_INTS_ALARM_3_BITS _u(0x00000008) -#define TIMER_INTS_ALARM_3_MSB _u(3) -#define TIMER_INTS_ALARM_3_LSB _u(3) -#define TIMER_INTS_ALARM_3_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : TIMER_INTS_ALARM_2 -#define TIMER_INTS_ALARM_2_RESET _u(0x0) -#define TIMER_INTS_ALARM_2_BITS _u(0x00000004) -#define TIMER_INTS_ALARM_2_MSB _u(2) -#define TIMER_INTS_ALARM_2_LSB _u(2) -#define TIMER_INTS_ALARM_2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : TIMER_INTS_ALARM_1 -#define TIMER_INTS_ALARM_1_RESET _u(0x0) -#define TIMER_INTS_ALARM_1_BITS _u(0x00000002) -#define TIMER_INTS_ALARM_1_MSB _u(1) -#define TIMER_INTS_ALARM_1_LSB _u(1) -#define TIMER_INTS_ALARM_1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : TIMER_INTS_ALARM_0 -#define TIMER_INTS_ALARM_0_RESET _u(0x0) -#define TIMER_INTS_ALARM_0_BITS _u(0x00000001) -#define TIMER_INTS_ALARM_0_MSB _u(0) -#define TIMER_INTS_ALARM_0_LSB _u(0) -#define TIMER_INTS_ALARM_0_ACCESS "RO" -// ============================================================================= -#endif // _HARDWARE_REGS_TIMER_H - diff --git a/lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/uart.h b/lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/uart.h deleted file mode 100644 index 0f7f17ec0f..0000000000 --- a/lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/uart.h +++ /dev/null @@ -1,1150 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -// ============================================================================= -// Register block : UART -// Version : 1 -// Bus type : apb -// ============================================================================= -#ifndef _HARDWARE_REGS_UART_H -#define _HARDWARE_REGS_UART_H -// ============================================================================= -// Register : UART_UARTDR -// Description : Data Register, UARTDR -#define UART_UARTDR_OFFSET _u(0x00000000) -#define UART_UARTDR_BITS _u(0x00000fff) -#define UART_UARTDR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : UART_UARTDR_OE -// Description : Overrun error. This bit is set to 1 if data is received and the -// receive FIFO is already full. This is cleared to 0 once there -// is an empty space in the FIFO and a new character can be -// written to it. -#define UART_UARTDR_OE_RESET "-" -#define UART_UARTDR_OE_BITS _u(0x00000800) -#define UART_UARTDR_OE_MSB _u(11) -#define UART_UARTDR_OE_LSB _u(11) -#define UART_UARTDR_OE_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : UART_UARTDR_BE -// Description : Break error. This bit is set to 1 if a break condition was -// detected, indicating that the received data input was held LOW -// for longer than a full-word transmission time (defined as -// start, data, parity and stop bits). In FIFO mode, this error is -// associated with the character at the top of the FIFO. When a -// break occurs, only one 0 character is loaded into the FIFO. The -// next character is only enabled after the receive data input -// goes to a 1 (marking state), and the next valid start bit is -// received. -#define UART_UARTDR_BE_RESET "-" -#define UART_UARTDR_BE_BITS _u(0x00000400) -#define UART_UARTDR_BE_MSB _u(10) -#define UART_UARTDR_BE_LSB _u(10) -#define UART_UARTDR_BE_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : UART_UARTDR_PE -// Description : Parity error. When set to 1, it indicates that the parity of -// the received data character does not match the parity that the -// EPS and SPS bits in the Line Control Register, UARTLCR_H. In -// FIFO mode, this error is associated with the character at the -// top of the FIFO. -#define UART_UARTDR_PE_RESET "-" -#define UART_UARTDR_PE_BITS _u(0x00000200) -#define UART_UARTDR_PE_MSB _u(9) -#define UART_UARTDR_PE_LSB _u(9) -#define UART_UARTDR_PE_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : UART_UARTDR_FE -// Description : Framing error. When set to 1, it indicates that the received -// character did not have a valid stop bit (a valid stop bit is -// 1). In FIFO mode, this error is associated with the character -// at the top of the FIFO. -#define UART_UARTDR_FE_RESET "-" -#define UART_UARTDR_FE_BITS _u(0x00000100) -#define UART_UARTDR_FE_MSB _u(8) -#define UART_UARTDR_FE_LSB _u(8) -#define UART_UARTDR_FE_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : UART_UARTDR_DATA -// Description : Receive (read) data character. Transmit (write) data character. -#define UART_UARTDR_DATA_RESET "-" -#define UART_UARTDR_DATA_BITS _u(0x000000ff) -#define UART_UARTDR_DATA_MSB _u(7) -#define UART_UARTDR_DATA_LSB _u(0) -#define UART_UARTDR_DATA_ACCESS "RWF" -// ============================================================================= -// Register : UART_UARTRSR -// Description : Receive Status Register/Error Clear Register, UARTRSR/UARTECR -#define UART_UARTRSR_OFFSET _u(0x00000004) -#define UART_UARTRSR_BITS _u(0x0000000f) -#define UART_UARTRSR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : UART_UARTRSR_OE -// Description : Overrun error. This bit is set to 1 if data is received and the -// FIFO is already full. This bit is cleared to 0 by a write to -// UARTECR. The FIFO contents remain valid because no more data is -// written when the FIFO is full, only the contents of the shift -// register are overwritten. The CPU must now read the data, to -// empty the FIFO. -#define UART_UARTRSR_OE_RESET _u(0x0) -#define UART_UARTRSR_OE_BITS _u(0x00000008) -#define UART_UARTRSR_OE_MSB _u(3) -#define UART_UARTRSR_OE_LSB _u(3) -#define UART_UARTRSR_OE_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : UART_UARTRSR_BE -// Description : Break error. This bit is set to 1 if a break condition was -// detected, indicating that the received data input was held LOW -// for longer than a full-word transmission time (defined as -// start, data, parity, and stop bits). This bit is cleared to 0 -// after a write to UARTECR. In FIFO mode, this error is -// associated with the character at the top of the FIFO. When a -// break occurs, only one 0 character is loaded into the FIFO. The -// next character is only enabled after the receive data input -// goes to a 1 (marking state) and the next valid start bit is -// received. -#define UART_UARTRSR_BE_RESET _u(0x0) -#define UART_UARTRSR_BE_BITS _u(0x00000004) -#define UART_UARTRSR_BE_MSB _u(2) -#define UART_UARTRSR_BE_LSB _u(2) -#define UART_UARTRSR_BE_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : UART_UARTRSR_PE -// Description : Parity error. When set to 1, it indicates that the parity of -// the received data character does not match the parity that the -// EPS and SPS bits in the Line Control Register, UARTLCR_H. This -// bit is cleared to 0 by a write to UARTECR. In FIFO mode, this -// error is associated with the character at the top of the FIFO. -#define UART_UARTRSR_PE_RESET _u(0x0) -#define UART_UARTRSR_PE_BITS _u(0x00000002) -#define UART_UARTRSR_PE_MSB _u(1) -#define UART_UARTRSR_PE_LSB _u(1) -#define UART_UARTRSR_PE_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : UART_UARTRSR_FE -// Description : Framing error. When set to 1, it indicates that the received -// character did not have a valid stop bit (a valid stop bit is -// 1). This bit is cleared to 0 by a write to UARTECR. In FIFO -// mode, this error is associated with the character at the top of -// the FIFO. -#define UART_UARTRSR_FE_RESET _u(0x0) -#define UART_UARTRSR_FE_BITS _u(0x00000001) -#define UART_UARTRSR_FE_MSB _u(0) -#define UART_UARTRSR_FE_LSB _u(0) -#define UART_UARTRSR_FE_ACCESS "WC" -// ============================================================================= -// Register : UART_UARTFR -// Description : Flag Register, UARTFR -#define UART_UARTFR_OFFSET _u(0x00000018) -#define UART_UARTFR_BITS _u(0x000001ff) -#define UART_UARTFR_RESET _u(0x00000090) -// ----------------------------------------------------------------------------- -// Field : UART_UARTFR_RI -// Description : Ring indicator. This bit is the complement of the UART ring -// indicator, nUARTRI, modem status input. That is, the bit is 1 -// when nUARTRI is LOW. -#define UART_UARTFR_RI_RESET "-" -#define UART_UARTFR_RI_BITS _u(0x00000100) -#define UART_UARTFR_RI_MSB _u(8) -#define UART_UARTFR_RI_LSB _u(8) -#define UART_UARTFR_RI_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : UART_UARTFR_TXFE -// Description : Transmit FIFO empty. The meaning of this bit depends on the -// state of the FEN bit in the Line Control Register, UARTLCR_H. -// If the FIFO is disabled, this bit is set when the transmit -// holding register is empty. If the FIFO is enabled, the TXFE bit -// is set when the transmit FIFO is empty. This bit does not -// indicate if there is data in the transmit shift register. -#define UART_UARTFR_TXFE_RESET _u(0x1) -#define UART_UARTFR_TXFE_BITS _u(0x00000080) -#define UART_UARTFR_TXFE_MSB _u(7) -#define UART_UARTFR_TXFE_LSB _u(7) -#define UART_UARTFR_TXFE_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : UART_UARTFR_RXFF -// Description : Receive FIFO full. The meaning of this bit depends on the state -// of the FEN bit in the UARTLCR_H Register. If the FIFO is -// disabled, this bit is set when the receive holding register is -// full. If the FIFO is enabled, the RXFF bit is set when the -// receive FIFO is full. -#define UART_UARTFR_RXFF_RESET _u(0x0) -#define UART_UARTFR_RXFF_BITS _u(0x00000040) -#define UART_UARTFR_RXFF_MSB _u(6) -#define UART_UARTFR_RXFF_LSB _u(6) -#define UART_UARTFR_RXFF_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : UART_UARTFR_TXFF -// Description : Transmit FIFO full. The meaning of this bit depends on the -// state of the FEN bit in the UARTLCR_H Register. If the FIFO is -// disabled, this bit is set when the transmit holding register is -// full. If the FIFO is enabled, the TXFF bit is set when the -// transmit FIFO is full. -#define UART_UARTFR_TXFF_RESET _u(0x0) -#define UART_UARTFR_TXFF_BITS _u(0x00000020) -#define UART_UARTFR_TXFF_MSB _u(5) -#define UART_UARTFR_TXFF_LSB _u(5) -#define UART_UARTFR_TXFF_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : UART_UARTFR_RXFE -// Description : Receive FIFO empty. The meaning of this bit depends on the -// state of the FEN bit in the UARTLCR_H Register. If the FIFO is -// disabled, this bit is set when the receive holding register is -// empty. If the FIFO is enabled, the RXFE bit is set when the -// receive FIFO is empty. -#define UART_UARTFR_RXFE_RESET _u(0x1) -#define UART_UARTFR_RXFE_BITS _u(0x00000010) -#define UART_UARTFR_RXFE_MSB _u(4) -#define UART_UARTFR_RXFE_LSB _u(4) -#define UART_UARTFR_RXFE_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : UART_UARTFR_BUSY -// Description : UART busy. If this bit is set to 1, the UART is busy -// transmitting data. This bit remains set until the complete -// byte, including all the stop bits, has been sent from the shift -// register. This bit is set as soon as the transmit FIFO becomes -// non-empty, regardless of whether the UART is enabled or not. -#define UART_UARTFR_BUSY_RESET _u(0x0) -#define UART_UARTFR_BUSY_BITS _u(0x00000008) -#define UART_UARTFR_BUSY_MSB _u(3) -#define UART_UARTFR_BUSY_LSB _u(3) -#define UART_UARTFR_BUSY_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : UART_UARTFR_DCD -// Description : Data carrier detect. This bit is the complement of the UART -// data carrier detect, nUARTDCD, modem status input. That is, the -// bit is 1 when nUARTDCD is LOW. -#define UART_UARTFR_DCD_RESET "-" -#define UART_UARTFR_DCD_BITS _u(0x00000004) -#define UART_UARTFR_DCD_MSB _u(2) -#define UART_UARTFR_DCD_LSB _u(2) -#define UART_UARTFR_DCD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : UART_UARTFR_DSR -// Description : Data set ready. This bit is the complement of the UART data set -// ready, nUARTDSR, modem status input. That is, the bit is 1 when -// nUARTDSR is LOW. -#define UART_UARTFR_DSR_RESET "-" -#define UART_UARTFR_DSR_BITS _u(0x00000002) -#define UART_UARTFR_DSR_MSB _u(1) -#define UART_UARTFR_DSR_LSB _u(1) -#define UART_UARTFR_DSR_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : UART_UARTFR_CTS -// Description : Clear to send. This bit is the complement of the UART clear to -// send, nUARTCTS, modem status input. That is, the bit is 1 when -// nUARTCTS is LOW. -#define UART_UARTFR_CTS_RESET "-" -#define UART_UARTFR_CTS_BITS _u(0x00000001) -#define UART_UARTFR_CTS_MSB _u(0) -#define UART_UARTFR_CTS_LSB _u(0) -#define UART_UARTFR_CTS_ACCESS "RO" -// ============================================================================= -// Register : UART_UARTILPR -// Description : IrDA Low-Power Counter Register, UARTILPR -#define UART_UARTILPR_OFFSET _u(0x00000020) -#define UART_UARTILPR_BITS _u(0x000000ff) -#define UART_UARTILPR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : UART_UARTILPR_ILPDVSR -// Description : 8-bit low-power divisor value. These bits are cleared to 0 at -// reset. -#define UART_UARTILPR_ILPDVSR_RESET _u(0x00) -#define UART_UARTILPR_ILPDVSR_BITS _u(0x000000ff) -#define UART_UARTILPR_ILPDVSR_MSB _u(7) -#define UART_UARTILPR_ILPDVSR_LSB _u(0) -#define UART_UARTILPR_ILPDVSR_ACCESS "RW" -// ============================================================================= -// Register : UART_UARTIBRD -// Description : Integer Baud Rate Register, UARTIBRD -#define UART_UARTIBRD_OFFSET _u(0x00000024) -#define UART_UARTIBRD_BITS _u(0x0000ffff) -#define UART_UARTIBRD_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : UART_UARTIBRD_BAUD_DIVINT -// Description : The integer baud rate divisor. These bits are cleared to 0 on -// reset. -#define UART_UARTIBRD_BAUD_DIVINT_RESET _u(0x0000) -#define UART_UARTIBRD_BAUD_DIVINT_BITS _u(0x0000ffff) -#define UART_UARTIBRD_BAUD_DIVINT_MSB _u(15) -#define UART_UARTIBRD_BAUD_DIVINT_LSB _u(0) -#define UART_UARTIBRD_BAUD_DIVINT_ACCESS "RW" -// ============================================================================= -// Register : UART_UARTFBRD -// Description : Fractional Baud Rate Register, UARTFBRD -#define UART_UARTFBRD_OFFSET _u(0x00000028) -#define UART_UARTFBRD_BITS _u(0x0000003f) -#define UART_UARTFBRD_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : UART_UARTFBRD_BAUD_DIVFRAC -// Description : The fractional baud rate divisor. These bits are cleared to 0 -// on reset. -#define UART_UARTFBRD_BAUD_DIVFRAC_RESET _u(0x00) -#define UART_UARTFBRD_BAUD_DIVFRAC_BITS _u(0x0000003f) -#define UART_UARTFBRD_BAUD_DIVFRAC_MSB _u(5) -#define UART_UARTFBRD_BAUD_DIVFRAC_LSB _u(0) -#define UART_UARTFBRD_BAUD_DIVFRAC_ACCESS "RW" -// ============================================================================= -// Register : UART_UARTLCR_H -// Description : Line Control Register, UARTLCR_H -#define UART_UARTLCR_H_OFFSET _u(0x0000002c) -#define UART_UARTLCR_H_BITS _u(0x000000ff) -#define UART_UARTLCR_H_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : UART_UARTLCR_H_SPS -// Description : Stick parity select. 0 = stick parity is disabled 1 = either: * -// if the EPS bit is 0 then the parity bit is transmitted and -// checked as a 1 * if the EPS bit is 1 then the parity bit is -// transmitted and checked as a 0. This bit has no effect when the -// PEN bit disables parity checking and generation. -#define UART_UARTLCR_H_SPS_RESET _u(0x0) -#define UART_UARTLCR_H_SPS_BITS _u(0x00000080) -#define UART_UARTLCR_H_SPS_MSB _u(7) -#define UART_UARTLCR_H_SPS_LSB _u(7) -#define UART_UARTLCR_H_SPS_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : UART_UARTLCR_H_WLEN -// Description : Word length. These bits indicate the number of data bits -// transmitted or received in a frame as follows: b11 = 8 bits b10 -// = 7 bits b01 = 6 bits b00 = 5 bits. -#define UART_UARTLCR_H_WLEN_RESET _u(0x0) -#define UART_UARTLCR_H_WLEN_BITS _u(0x00000060) -#define UART_UARTLCR_H_WLEN_MSB _u(6) -#define UART_UARTLCR_H_WLEN_LSB _u(5) -#define UART_UARTLCR_H_WLEN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : UART_UARTLCR_H_FEN -// Description : Enable FIFOs: 0 = FIFOs are disabled (character mode) that is, -// the FIFOs become 1-byte-deep holding registers 1 = transmit and -// receive FIFO buffers are enabled (FIFO mode). -#define UART_UARTLCR_H_FEN_RESET _u(0x0) -#define UART_UARTLCR_H_FEN_BITS _u(0x00000010) -#define UART_UARTLCR_H_FEN_MSB _u(4) -#define UART_UARTLCR_H_FEN_LSB _u(4) -#define UART_UARTLCR_H_FEN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : UART_UARTLCR_H_STP2 -// Description : Two stop bits select. If this bit is set to 1, two stop bits -// are transmitted at the end of the frame. The receive logic does -// not check for two stop bits being received. -#define UART_UARTLCR_H_STP2_RESET _u(0x0) -#define UART_UARTLCR_H_STP2_BITS _u(0x00000008) -#define UART_UARTLCR_H_STP2_MSB _u(3) -#define UART_UARTLCR_H_STP2_LSB _u(3) -#define UART_UARTLCR_H_STP2_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : UART_UARTLCR_H_EPS -// Description : Even parity select. Controls the type of parity the UART uses -// during transmission and reception: 0 = odd parity. The UART -// generates or checks for an odd number of 1s in the data and -// parity bits. 1 = even parity. The UART generates or checks for -// an even number of 1s in the data and parity bits. This bit has -// no effect when the PEN bit disables parity checking and -// generation. -#define UART_UARTLCR_H_EPS_RESET _u(0x0) -#define UART_UARTLCR_H_EPS_BITS _u(0x00000004) -#define UART_UARTLCR_H_EPS_MSB _u(2) -#define UART_UARTLCR_H_EPS_LSB _u(2) -#define UART_UARTLCR_H_EPS_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : UART_UARTLCR_H_PEN -// Description : Parity enable: 0 = parity is disabled and no parity bit added -// to the data frame 1 = parity checking and generation is -// enabled. -#define UART_UARTLCR_H_PEN_RESET _u(0x0) -#define UART_UARTLCR_H_PEN_BITS _u(0x00000002) -#define UART_UARTLCR_H_PEN_MSB _u(1) -#define UART_UARTLCR_H_PEN_LSB _u(1) -#define UART_UARTLCR_H_PEN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : UART_UARTLCR_H_BRK -// Description : Send break. If this bit is set to 1, a low-level is continually -// output on the UARTTXD output, after completing transmission of -// the current character. For the proper execution of the break -// command, the software must set this bit for at least two -// complete frames. For normal use, this bit must be cleared to 0. -#define UART_UARTLCR_H_BRK_RESET _u(0x0) -#define UART_UARTLCR_H_BRK_BITS _u(0x00000001) -#define UART_UARTLCR_H_BRK_MSB _u(0) -#define UART_UARTLCR_H_BRK_LSB _u(0) -#define UART_UARTLCR_H_BRK_ACCESS "RW" -// ============================================================================= -// Register : UART_UARTCR -// Description : Control Register, UARTCR -#define UART_UARTCR_OFFSET _u(0x00000030) -#define UART_UARTCR_BITS _u(0x0000ff87) -#define UART_UARTCR_RESET _u(0x00000300) -// ----------------------------------------------------------------------------- -// Field : UART_UARTCR_CTSEN -// Description : CTS hardware flow control enable. If this bit is set to 1, CTS -// hardware flow control is enabled. Data is only transmitted when -// the nUARTCTS signal is asserted. -#define UART_UARTCR_CTSEN_RESET _u(0x0) -#define UART_UARTCR_CTSEN_BITS _u(0x00008000) -#define UART_UARTCR_CTSEN_MSB _u(15) -#define UART_UARTCR_CTSEN_LSB _u(15) -#define UART_UARTCR_CTSEN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : UART_UARTCR_RTSEN -// Description : RTS hardware flow control enable. If this bit is set to 1, RTS -// hardware flow control is enabled. Data is only requested when -// there is space in the receive FIFO for it to be received. -#define UART_UARTCR_RTSEN_RESET _u(0x0) -#define UART_UARTCR_RTSEN_BITS _u(0x00004000) -#define UART_UARTCR_RTSEN_MSB _u(14) -#define UART_UARTCR_RTSEN_LSB _u(14) -#define UART_UARTCR_RTSEN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : UART_UARTCR_OUT2 -// Description : This bit is the complement of the UART Out2 (nUARTOut2) modem -// status output. That is, when the bit is programmed to a 1, the -// output is 0. For DTE this can be used as Ring Indicator (RI). -#define UART_UARTCR_OUT2_RESET _u(0x0) -#define UART_UARTCR_OUT2_BITS _u(0x00002000) -#define UART_UARTCR_OUT2_MSB _u(13) -#define UART_UARTCR_OUT2_LSB _u(13) -#define UART_UARTCR_OUT2_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : UART_UARTCR_OUT1 -// Description : This bit is the complement of the UART Out1 (nUARTOut1) modem -// status output. That is, when the bit is programmed to a 1 the -// output is 0. For DTE this can be used as Data Carrier Detect -// (DCD). -#define UART_UARTCR_OUT1_RESET _u(0x0) -#define UART_UARTCR_OUT1_BITS _u(0x00001000) -#define UART_UARTCR_OUT1_MSB _u(12) -#define UART_UARTCR_OUT1_LSB _u(12) -#define UART_UARTCR_OUT1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : UART_UARTCR_RTS -// Description : Request to send. This bit is the complement of the UART request -// to send, nUARTRTS, modem status output. That is, when the bit -// is programmed to a 1 then nUARTRTS is LOW. -#define UART_UARTCR_RTS_RESET _u(0x0) -#define UART_UARTCR_RTS_BITS _u(0x00000800) -#define UART_UARTCR_RTS_MSB _u(11) -#define UART_UARTCR_RTS_LSB _u(11) -#define UART_UARTCR_RTS_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : UART_UARTCR_DTR -// Description : Data transmit ready. This bit is the complement of the UART -// data transmit ready, nUARTDTR, modem status output. That is, -// when the bit is programmed to a 1 then nUARTDTR is LOW. -#define UART_UARTCR_DTR_RESET _u(0x0) -#define UART_UARTCR_DTR_BITS _u(0x00000400) -#define UART_UARTCR_DTR_MSB _u(10) -#define UART_UARTCR_DTR_LSB _u(10) -#define UART_UARTCR_DTR_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : UART_UARTCR_RXE -// Description : Receive enable. If this bit is set to 1, the receive section of -// the UART is enabled. Data reception occurs for either UART -// signals or SIR signals depending on the setting of the SIREN -// bit. When the UART is disabled in the middle of reception, it -// completes the current character before stopping. -#define UART_UARTCR_RXE_RESET _u(0x1) -#define UART_UARTCR_RXE_BITS _u(0x00000200) -#define UART_UARTCR_RXE_MSB _u(9) -#define UART_UARTCR_RXE_LSB _u(9) -#define UART_UARTCR_RXE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : UART_UARTCR_TXE -// Description : Transmit enable. If this bit is set to 1, the transmit section -// of the UART is enabled. Data transmission occurs for either -// UART signals, or SIR signals depending on the setting of the -// SIREN bit. When the UART is disabled in the middle of -// transmission, it completes the current character before -// stopping. -#define UART_UARTCR_TXE_RESET _u(0x1) -#define UART_UARTCR_TXE_BITS _u(0x00000100) -#define UART_UARTCR_TXE_MSB _u(8) -#define UART_UARTCR_TXE_LSB _u(8) -#define UART_UARTCR_TXE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : UART_UARTCR_LBE -// Description : Loopback enable. If this bit is set to 1 and the SIREN bit is -// set to 1 and the SIRTEST bit in the Test Control Register, -// UARTTCR is set to 1, then the nSIROUT path is inverted, and fed -// through to the SIRIN path. The SIRTEST bit in the test register -// must be set to 1 to override the normal half-duplex SIR -// operation. This must be the requirement for accessing the test -// registers during normal operation, and SIRTEST must be cleared -// to 0 when loopback testing is finished. This feature reduces -// the amount of external coupling required during system test. If -// this bit is set to 1, and the SIRTEST bit is set to 0, the -// UARTTXD path is fed through to the UARTRXD path. In either SIR -// mode or UART mode, when this bit is set, the modem outputs are -// also fed through to the modem inputs. This bit is cleared to 0 -// on reset, to disable loopback. -#define UART_UARTCR_LBE_RESET _u(0x0) -#define UART_UARTCR_LBE_BITS _u(0x00000080) -#define UART_UARTCR_LBE_MSB _u(7) -#define UART_UARTCR_LBE_LSB _u(7) -#define UART_UARTCR_LBE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : UART_UARTCR_SIRLP -// Description : SIR low-power IrDA mode. This bit selects the IrDA encoding -// mode. If this bit is cleared to 0, low-level bits are -// transmitted as an active high pulse with a width of 3 / 16th of -// the bit period. If this bit is set to 1, low-level bits are -// transmitted with a pulse width that is 3 times the period of -// the IrLPBaud16 input signal, regardless of the selected bit -// rate. Setting this bit uses less power, but might reduce -// transmission distances. -#define UART_UARTCR_SIRLP_RESET _u(0x0) -#define UART_UARTCR_SIRLP_BITS _u(0x00000004) -#define UART_UARTCR_SIRLP_MSB _u(2) -#define UART_UARTCR_SIRLP_LSB _u(2) -#define UART_UARTCR_SIRLP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : UART_UARTCR_SIREN -// Description : SIR enable: 0 = IrDA SIR ENDEC is disabled. nSIROUT remains LOW -// (no light pulse generated), and signal transitions on SIRIN -// have no effect. 1 = IrDA SIR ENDEC is enabled. Data is -// transmitted and received on nSIROUT and SIRIN. UARTTXD remains -// HIGH, in the marking state. Signal transitions on UARTRXD or -// modem status inputs have no effect. This bit has no effect if -// the UARTEN bit disables the UART. -#define UART_UARTCR_SIREN_RESET _u(0x0) -#define UART_UARTCR_SIREN_BITS _u(0x00000002) -#define UART_UARTCR_SIREN_MSB _u(1) -#define UART_UARTCR_SIREN_LSB _u(1) -#define UART_UARTCR_SIREN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : UART_UARTCR_UARTEN -// Description : UART enable: 0 = UART is disabled. If the UART is disabled in -// the middle of transmission or reception, it completes the -// current character before stopping. 1 = the UART is enabled. -// Data transmission and reception occurs for either UART signals -// or SIR signals depending on the setting of the SIREN bit. -#define UART_UARTCR_UARTEN_RESET _u(0x0) -#define UART_UARTCR_UARTEN_BITS _u(0x00000001) -#define UART_UARTCR_UARTEN_MSB _u(0) -#define UART_UARTCR_UARTEN_LSB _u(0) -#define UART_UARTCR_UARTEN_ACCESS "RW" -// ============================================================================= -// Register : UART_UARTIFLS -// Description : Interrupt FIFO Level Select Register, UARTIFLS -#define UART_UARTIFLS_OFFSET _u(0x00000034) -#define UART_UARTIFLS_BITS _u(0x0000003f) -#define UART_UARTIFLS_RESET _u(0x00000012) -// ----------------------------------------------------------------------------- -// Field : UART_UARTIFLS_RXIFLSEL -// Description : Receive interrupt FIFO level select. The trigger points for the -// receive interrupt are as follows: b000 = Receive FIFO becomes -// >= 1 / 8 full b001 = Receive FIFO becomes >= 1 / 4 full b010 = -// Receive FIFO becomes >= 1 / 2 full b011 = Receive FIFO becomes -// >= 3 / 4 full b100 = Receive FIFO becomes >= 7 / 8 full -// b101-b111 = reserved. -#define UART_UARTIFLS_RXIFLSEL_RESET _u(0x2) -#define UART_UARTIFLS_RXIFLSEL_BITS _u(0x00000038) -#define UART_UARTIFLS_RXIFLSEL_MSB _u(5) -#define UART_UARTIFLS_RXIFLSEL_LSB _u(3) -#define UART_UARTIFLS_RXIFLSEL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : UART_UARTIFLS_TXIFLSEL -// Description : Transmit interrupt FIFO level select. The trigger points for -// the transmit interrupt are as follows: b000 = Transmit FIFO -// becomes <= 1 / 8 full b001 = Transmit FIFO becomes <= 1 / 4 -// full b010 = Transmit FIFO becomes <= 1 / 2 full b011 = Transmit -// FIFO becomes <= 3 / 4 full b100 = Transmit FIFO becomes <= 7 / -// 8 full b101-b111 = reserved. -#define UART_UARTIFLS_TXIFLSEL_RESET _u(0x2) -#define UART_UARTIFLS_TXIFLSEL_BITS _u(0x00000007) -#define UART_UARTIFLS_TXIFLSEL_MSB _u(2) -#define UART_UARTIFLS_TXIFLSEL_LSB _u(0) -#define UART_UARTIFLS_TXIFLSEL_ACCESS "RW" -// ============================================================================= -// Register : UART_UARTIMSC -// Description : Interrupt Mask Set/Clear Register, UARTIMSC -#define UART_UARTIMSC_OFFSET _u(0x00000038) -#define UART_UARTIMSC_BITS _u(0x000007ff) -#define UART_UARTIMSC_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : UART_UARTIMSC_OEIM -// Description : Overrun error interrupt mask. A read returns the current mask -// for the UARTOEINTR interrupt. On a write of 1, the mask of the -// UARTOEINTR interrupt is set. A write of 0 clears the mask. -#define UART_UARTIMSC_OEIM_RESET _u(0x0) -#define UART_UARTIMSC_OEIM_BITS _u(0x00000400) -#define UART_UARTIMSC_OEIM_MSB _u(10) -#define UART_UARTIMSC_OEIM_LSB _u(10) -#define UART_UARTIMSC_OEIM_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : UART_UARTIMSC_BEIM -// Description : Break error interrupt mask. A read returns the current mask for -// the UARTBEINTR interrupt. On a write of 1, the mask of the -// UARTBEINTR interrupt is set. A write of 0 clears the mask. -#define UART_UARTIMSC_BEIM_RESET _u(0x0) -#define UART_UARTIMSC_BEIM_BITS _u(0x00000200) -#define UART_UARTIMSC_BEIM_MSB _u(9) -#define UART_UARTIMSC_BEIM_LSB _u(9) -#define UART_UARTIMSC_BEIM_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : UART_UARTIMSC_PEIM -// Description : Parity error interrupt mask. A read returns the current mask -// for the UARTPEINTR interrupt. On a write of 1, the mask of the -// UARTPEINTR interrupt is set. A write of 0 clears the mask. -#define UART_UARTIMSC_PEIM_RESET _u(0x0) -#define UART_UARTIMSC_PEIM_BITS _u(0x00000100) -#define UART_UARTIMSC_PEIM_MSB _u(8) -#define UART_UARTIMSC_PEIM_LSB _u(8) -#define UART_UARTIMSC_PEIM_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : UART_UARTIMSC_FEIM -// Description : Framing error interrupt mask. A read returns the current mask -// for the UARTFEINTR interrupt. On a write of 1, the mask of the -// UARTFEINTR interrupt is set. A write of 0 clears the mask. -#define UART_UARTIMSC_FEIM_RESET _u(0x0) -#define UART_UARTIMSC_FEIM_BITS _u(0x00000080) -#define UART_UARTIMSC_FEIM_MSB _u(7) -#define UART_UARTIMSC_FEIM_LSB _u(7) -#define UART_UARTIMSC_FEIM_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : UART_UARTIMSC_RTIM -// Description : Receive timeout interrupt mask. A read returns the current mask -// for the UARTRTINTR interrupt. On a write of 1, the mask of the -// UARTRTINTR interrupt is set. A write of 0 clears the mask. -#define UART_UARTIMSC_RTIM_RESET _u(0x0) -#define UART_UARTIMSC_RTIM_BITS _u(0x00000040) -#define UART_UARTIMSC_RTIM_MSB _u(6) -#define UART_UARTIMSC_RTIM_LSB _u(6) -#define UART_UARTIMSC_RTIM_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : UART_UARTIMSC_TXIM -// Description : Transmit interrupt mask. A read returns the current mask for -// the UARTTXINTR interrupt. On a write of 1, the mask of the -// UARTTXINTR interrupt is set. A write of 0 clears the mask. -#define UART_UARTIMSC_TXIM_RESET _u(0x0) -#define UART_UARTIMSC_TXIM_BITS _u(0x00000020) -#define UART_UARTIMSC_TXIM_MSB _u(5) -#define UART_UARTIMSC_TXIM_LSB _u(5) -#define UART_UARTIMSC_TXIM_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : UART_UARTIMSC_RXIM -// Description : Receive interrupt mask. A read returns the current mask for the -// UARTRXINTR interrupt. On a write of 1, the mask of the -// UARTRXINTR interrupt is set. A write of 0 clears the mask. -#define UART_UARTIMSC_RXIM_RESET _u(0x0) -#define UART_UARTIMSC_RXIM_BITS _u(0x00000010) -#define UART_UARTIMSC_RXIM_MSB _u(4) -#define UART_UARTIMSC_RXIM_LSB _u(4) -#define UART_UARTIMSC_RXIM_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : UART_UARTIMSC_DSRMIM -// Description : nUARTDSR modem interrupt mask. A read returns the current mask -// for the UARTDSRINTR interrupt. On a write of 1, the mask of the -// UARTDSRINTR interrupt is set. A write of 0 clears the mask. -#define UART_UARTIMSC_DSRMIM_RESET _u(0x0) -#define UART_UARTIMSC_DSRMIM_BITS _u(0x00000008) -#define UART_UARTIMSC_DSRMIM_MSB _u(3) -#define UART_UARTIMSC_DSRMIM_LSB _u(3) -#define UART_UARTIMSC_DSRMIM_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : UART_UARTIMSC_DCDMIM -// Description : nUARTDCD modem interrupt mask. A read returns the current mask -// for the UARTDCDINTR interrupt. On a write of 1, the mask of the -// UARTDCDINTR interrupt is set. A write of 0 clears the mask. -#define UART_UARTIMSC_DCDMIM_RESET _u(0x0) -#define UART_UARTIMSC_DCDMIM_BITS _u(0x00000004) -#define UART_UARTIMSC_DCDMIM_MSB _u(2) -#define UART_UARTIMSC_DCDMIM_LSB _u(2) -#define UART_UARTIMSC_DCDMIM_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : UART_UARTIMSC_CTSMIM -// Description : nUARTCTS modem interrupt mask. A read returns the current mask -// for the UARTCTSINTR interrupt. On a write of 1, the mask of the -// UARTCTSINTR interrupt is set. A write of 0 clears the mask. -#define UART_UARTIMSC_CTSMIM_RESET _u(0x0) -#define UART_UARTIMSC_CTSMIM_BITS _u(0x00000002) -#define UART_UARTIMSC_CTSMIM_MSB _u(1) -#define UART_UARTIMSC_CTSMIM_LSB _u(1) -#define UART_UARTIMSC_CTSMIM_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : UART_UARTIMSC_RIMIM -// Description : nUARTRI modem interrupt mask. A read returns the current mask -// for the UARTRIINTR interrupt. On a write of 1, the mask of the -// UARTRIINTR interrupt is set. A write of 0 clears the mask. -#define UART_UARTIMSC_RIMIM_RESET _u(0x0) -#define UART_UARTIMSC_RIMIM_BITS _u(0x00000001) -#define UART_UARTIMSC_RIMIM_MSB _u(0) -#define UART_UARTIMSC_RIMIM_LSB _u(0) -#define UART_UARTIMSC_RIMIM_ACCESS "RW" -// ============================================================================= -// Register : UART_UARTRIS -// Description : Raw Interrupt Status Register, UARTRIS -#define UART_UARTRIS_OFFSET _u(0x0000003c) -#define UART_UARTRIS_BITS _u(0x000007ff) -#define UART_UARTRIS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : UART_UARTRIS_OERIS -// Description : Overrun error interrupt status. Returns the raw interrupt state -// of the UARTOEINTR interrupt. -#define UART_UARTRIS_OERIS_RESET _u(0x0) -#define UART_UARTRIS_OERIS_BITS _u(0x00000400) -#define UART_UARTRIS_OERIS_MSB _u(10) -#define UART_UARTRIS_OERIS_LSB _u(10) -#define UART_UARTRIS_OERIS_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : UART_UARTRIS_BERIS -// Description : Break error interrupt status. Returns the raw interrupt state -// of the UARTBEINTR interrupt. -#define UART_UARTRIS_BERIS_RESET _u(0x0) -#define UART_UARTRIS_BERIS_BITS _u(0x00000200) -#define UART_UARTRIS_BERIS_MSB _u(9) -#define UART_UARTRIS_BERIS_LSB _u(9) -#define UART_UARTRIS_BERIS_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : UART_UARTRIS_PERIS -// Description : Parity error interrupt status. Returns the raw interrupt state -// of the UARTPEINTR interrupt. -#define UART_UARTRIS_PERIS_RESET _u(0x0) -#define UART_UARTRIS_PERIS_BITS _u(0x00000100) -#define UART_UARTRIS_PERIS_MSB _u(8) -#define UART_UARTRIS_PERIS_LSB _u(8) -#define UART_UARTRIS_PERIS_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : UART_UARTRIS_FERIS -// Description : Framing error interrupt status. Returns the raw interrupt state -// of the UARTFEINTR interrupt. -#define UART_UARTRIS_FERIS_RESET _u(0x0) -#define UART_UARTRIS_FERIS_BITS _u(0x00000080) -#define UART_UARTRIS_FERIS_MSB _u(7) -#define UART_UARTRIS_FERIS_LSB _u(7) -#define UART_UARTRIS_FERIS_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : UART_UARTRIS_RTRIS -// Description : Receive timeout interrupt status. Returns the raw interrupt -// state of the UARTRTINTR interrupt. a -#define UART_UARTRIS_RTRIS_RESET _u(0x0) -#define UART_UARTRIS_RTRIS_BITS _u(0x00000040) -#define UART_UARTRIS_RTRIS_MSB _u(6) -#define UART_UARTRIS_RTRIS_LSB _u(6) -#define UART_UARTRIS_RTRIS_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : UART_UARTRIS_TXRIS -// Description : Transmit interrupt status. Returns the raw interrupt state of -// the UARTTXINTR interrupt. -#define UART_UARTRIS_TXRIS_RESET _u(0x0) -#define UART_UARTRIS_TXRIS_BITS _u(0x00000020) -#define UART_UARTRIS_TXRIS_MSB _u(5) -#define UART_UARTRIS_TXRIS_LSB _u(5) -#define UART_UARTRIS_TXRIS_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : UART_UARTRIS_RXRIS -// Description : Receive interrupt status. Returns the raw interrupt state of -// the UARTRXINTR interrupt. -#define UART_UARTRIS_RXRIS_RESET _u(0x0) -#define UART_UARTRIS_RXRIS_BITS _u(0x00000010) -#define UART_UARTRIS_RXRIS_MSB _u(4) -#define UART_UARTRIS_RXRIS_LSB _u(4) -#define UART_UARTRIS_RXRIS_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : UART_UARTRIS_DSRRMIS -// Description : nUARTDSR modem interrupt status. Returns the raw interrupt -// state of the UARTDSRINTR interrupt. -#define UART_UARTRIS_DSRRMIS_RESET "-" -#define UART_UARTRIS_DSRRMIS_BITS _u(0x00000008) -#define UART_UARTRIS_DSRRMIS_MSB _u(3) -#define UART_UARTRIS_DSRRMIS_LSB _u(3) -#define UART_UARTRIS_DSRRMIS_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : UART_UARTRIS_DCDRMIS -// Description : nUARTDCD modem interrupt status. Returns the raw interrupt -// state of the UARTDCDINTR interrupt. -#define UART_UARTRIS_DCDRMIS_RESET "-" -#define UART_UARTRIS_DCDRMIS_BITS _u(0x00000004) -#define UART_UARTRIS_DCDRMIS_MSB _u(2) -#define UART_UARTRIS_DCDRMIS_LSB _u(2) -#define UART_UARTRIS_DCDRMIS_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : UART_UARTRIS_CTSRMIS -// Description : nUARTCTS modem interrupt status. Returns the raw interrupt -// state of the UARTCTSINTR interrupt. -#define UART_UARTRIS_CTSRMIS_RESET "-" -#define UART_UARTRIS_CTSRMIS_BITS _u(0x00000002) -#define UART_UARTRIS_CTSRMIS_MSB _u(1) -#define UART_UARTRIS_CTSRMIS_LSB _u(1) -#define UART_UARTRIS_CTSRMIS_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : UART_UARTRIS_RIRMIS -// Description : nUARTRI modem interrupt status. Returns the raw interrupt state -// of the UARTRIINTR interrupt. -#define UART_UARTRIS_RIRMIS_RESET "-" -#define UART_UARTRIS_RIRMIS_BITS _u(0x00000001) -#define UART_UARTRIS_RIRMIS_MSB _u(0) -#define UART_UARTRIS_RIRMIS_LSB _u(0) -#define UART_UARTRIS_RIRMIS_ACCESS "RO" -// ============================================================================= -// Register : UART_UARTMIS -// Description : Masked Interrupt Status Register, UARTMIS -#define UART_UARTMIS_OFFSET _u(0x00000040) -#define UART_UARTMIS_BITS _u(0x000007ff) -#define UART_UARTMIS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : UART_UARTMIS_OEMIS -// Description : Overrun error masked interrupt status. Returns the masked -// interrupt state of the UARTOEINTR interrupt. -#define UART_UARTMIS_OEMIS_RESET _u(0x0) -#define UART_UARTMIS_OEMIS_BITS _u(0x00000400) -#define UART_UARTMIS_OEMIS_MSB _u(10) -#define UART_UARTMIS_OEMIS_LSB _u(10) -#define UART_UARTMIS_OEMIS_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : UART_UARTMIS_BEMIS -// Description : Break error masked interrupt status. Returns the masked -// interrupt state of the UARTBEINTR interrupt. -#define UART_UARTMIS_BEMIS_RESET _u(0x0) -#define UART_UARTMIS_BEMIS_BITS _u(0x00000200) -#define UART_UARTMIS_BEMIS_MSB _u(9) -#define UART_UARTMIS_BEMIS_LSB _u(9) -#define UART_UARTMIS_BEMIS_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : UART_UARTMIS_PEMIS -// Description : Parity error masked interrupt status. Returns the masked -// interrupt state of the UARTPEINTR interrupt. -#define UART_UARTMIS_PEMIS_RESET _u(0x0) -#define UART_UARTMIS_PEMIS_BITS _u(0x00000100) -#define UART_UARTMIS_PEMIS_MSB _u(8) -#define UART_UARTMIS_PEMIS_LSB _u(8) -#define UART_UARTMIS_PEMIS_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : UART_UARTMIS_FEMIS -// Description : Framing error masked interrupt status. Returns the masked -// interrupt state of the UARTFEINTR interrupt. -#define UART_UARTMIS_FEMIS_RESET _u(0x0) -#define UART_UARTMIS_FEMIS_BITS _u(0x00000080) -#define UART_UARTMIS_FEMIS_MSB _u(7) -#define UART_UARTMIS_FEMIS_LSB _u(7) -#define UART_UARTMIS_FEMIS_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : UART_UARTMIS_RTMIS -// Description : Receive timeout masked interrupt status. Returns the masked -// interrupt state of the UARTRTINTR interrupt. -#define UART_UARTMIS_RTMIS_RESET _u(0x0) -#define UART_UARTMIS_RTMIS_BITS _u(0x00000040) -#define UART_UARTMIS_RTMIS_MSB _u(6) -#define UART_UARTMIS_RTMIS_LSB _u(6) -#define UART_UARTMIS_RTMIS_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : UART_UARTMIS_TXMIS -// Description : Transmit masked interrupt status. Returns the masked interrupt -// state of the UARTTXINTR interrupt. -#define UART_UARTMIS_TXMIS_RESET _u(0x0) -#define UART_UARTMIS_TXMIS_BITS _u(0x00000020) -#define UART_UARTMIS_TXMIS_MSB _u(5) -#define UART_UARTMIS_TXMIS_LSB _u(5) -#define UART_UARTMIS_TXMIS_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : UART_UARTMIS_RXMIS -// Description : Receive masked interrupt status. Returns the masked interrupt -// state of the UARTRXINTR interrupt. -#define UART_UARTMIS_RXMIS_RESET _u(0x0) -#define UART_UARTMIS_RXMIS_BITS _u(0x00000010) -#define UART_UARTMIS_RXMIS_MSB _u(4) -#define UART_UARTMIS_RXMIS_LSB _u(4) -#define UART_UARTMIS_RXMIS_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : UART_UARTMIS_DSRMMIS -// Description : nUARTDSR modem masked interrupt status. Returns the masked -// interrupt state of the UARTDSRINTR interrupt. -#define UART_UARTMIS_DSRMMIS_RESET "-" -#define UART_UARTMIS_DSRMMIS_BITS _u(0x00000008) -#define UART_UARTMIS_DSRMMIS_MSB _u(3) -#define UART_UARTMIS_DSRMMIS_LSB _u(3) -#define UART_UARTMIS_DSRMMIS_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : UART_UARTMIS_DCDMMIS -// Description : nUARTDCD modem masked interrupt status. Returns the masked -// interrupt state of the UARTDCDINTR interrupt. -#define UART_UARTMIS_DCDMMIS_RESET "-" -#define UART_UARTMIS_DCDMMIS_BITS _u(0x00000004) -#define UART_UARTMIS_DCDMMIS_MSB _u(2) -#define UART_UARTMIS_DCDMMIS_LSB _u(2) -#define UART_UARTMIS_DCDMMIS_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : UART_UARTMIS_CTSMMIS -// Description : nUARTCTS modem masked interrupt status. Returns the masked -// interrupt state of the UARTCTSINTR interrupt. -#define UART_UARTMIS_CTSMMIS_RESET "-" -#define UART_UARTMIS_CTSMMIS_BITS _u(0x00000002) -#define UART_UARTMIS_CTSMMIS_MSB _u(1) -#define UART_UARTMIS_CTSMMIS_LSB _u(1) -#define UART_UARTMIS_CTSMMIS_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : UART_UARTMIS_RIMMIS -// Description : nUARTRI modem masked interrupt status. Returns the masked -// interrupt state of the UARTRIINTR interrupt. -#define UART_UARTMIS_RIMMIS_RESET "-" -#define UART_UARTMIS_RIMMIS_BITS _u(0x00000001) -#define UART_UARTMIS_RIMMIS_MSB _u(0) -#define UART_UARTMIS_RIMMIS_LSB _u(0) -#define UART_UARTMIS_RIMMIS_ACCESS "RO" -// ============================================================================= -// Register : UART_UARTICR -// Description : Interrupt Clear Register, UARTICR -#define UART_UARTICR_OFFSET _u(0x00000044) -#define UART_UARTICR_BITS _u(0x000007ff) -#define UART_UARTICR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : UART_UARTICR_OEIC -// Description : Overrun error interrupt clear. Clears the UARTOEINTR interrupt. -#define UART_UARTICR_OEIC_RESET "-" -#define UART_UARTICR_OEIC_BITS _u(0x00000400) -#define UART_UARTICR_OEIC_MSB _u(10) -#define UART_UARTICR_OEIC_LSB _u(10) -#define UART_UARTICR_OEIC_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : UART_UARTICR_BEIC -// Description : Break error interrupt clear. Clears the UARTBEINTR interrupt. -#define UART_UARTICR_BEIC_RESET "-" -#define UART_UARTICR_BEIC_BITS _u(0x00000200) -#define UART_UARTICR_BEIC_MSB _u(9) -#define UART_UARTICR_BEIC_LSB _u(9) -#define UART_UARTICR_BEIC_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : UART_UARTICR_PEIC -// Description : Parity error interrupt clear. Clears the UARTPEINTR interrupt. -#define UART_UARTICR_PEIC_RESET "-" -#define UART_UARTICR_PEIC_BITS _u(0x00000100) -#define UART_UARTICR_PEIC_MSB _u(8) -#define UART_UARTICR_PEIC_LSB _u(8) -#define UART_UARTICR_PEIC_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : UART_UARTICR_FEIC -// Description : Framing error interrupt clear. Clears the UARTFEINTR interrupt. -#define UART_UARTICR_FEIC_RESET "-" -#define UART_UARTICR_FEIC_BITS _u(0x00000080) -#define UART_UARTICR_FEIC_MSB _u(7) -#define UART_UARTICR_FEIC_LSB _u(7) -#define UART_UARTICR_FEIC_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : UART_UARTICR_RTIC -// Description : Receive timeout interrupt clear. Clears the UARTRTINTR -// interrupt. -#define UART_UARTICR_RTIC_RESET "-" -#define UART_UARTICR_RTIC_BITS _u(0x00000040) -#define UART_UARTICR_RTIC_MSB _u(6) -#define UART_UARTICR_RTIC_LSB _u(6) -#define UART_UARTICR_RTIC_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : UART_UARTICR_TXIC -// Description : Transmit interrupt clear. Clears the UARTTXINTR interrupt. -#define UART_UARTICR_TXIC_RESET "-" -#define UART_UARTICR_TXIC_BITS _u(0x00000020) -#define UART_UARTICR_TXIC_MSB _u(5) -#define UART_UARTICR_TXIC_LSB _u(5) -#define UART_UARTICR_TXIC_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : UART_UARTICR_RXIC -// Description : Receive interrupt clear. Clears the UARTRXINTR interrupt. -#define UART_UARTICR_RXIC_RESET "-" -#define UART_UARTICR_RXIC_BITS _u(0x00000010) -#define UART_UARTICR_RXIC_MSB _u(4) -#define UART_UARTICR_RXIC_LSB _u(4) -#define UART_UARTICR_RXIC_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : UART_UARTICR_DSRMIC -// Description : nUARTDSR modem interrupt clear. Clears the UARTDSRINTR -// interrupt. -#define UART_UARTICR_DSRMIC_RESET "-" -#define UART_UARTICR_DSRMIC_BITS _u(0x00000008) -#define UART_UARTICR_DSRMIC_MSB _u(3) -#define UART_UARTICR_DSRMIC_LSB _u(3) -#define UART_UARTICR_DSRMIC_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : UART_UARTICR_DCDMIC -// Description : nUARTDCD modem interrupt clear. Clears the UARTDCDINTR -// interrupt. -#define UART_UARTICR_DCDMIC_RESET "-" -#define UART_UARTICR_DCDMIC_BITS _u(0x00000004) -#define UART_UARTICR_DCDMIC_MSB _u(2) -#define UART_UARTICR_DCDMIC_LSB _u(2) -#define UART_UARTICR_DCDMIC_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : UART_UARTICR_CTSMIC -// Description : nUARTCTS modem interrupt clear. Clears the UARTCTSINTR -// interrupt. -#define UART_UARTICR_CTSMIC_RESET "-" -#define UART_UARTICR_CTSMIC_BITS _u(0x00000002) -#define UART_UARTICR_CTSMIC_MSB _u(1) -#define UART_UARTICR_CTSMIC_LSB _u(1) -#define UART_UARTICR_CTSMIC_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : UART_UARTICR_RIMIC -// Description : nUARTRI modem interrupt clear. Clears the UARTRIINTR interrupt. -#define UART_UARTICR_RIMIC_RESET "-" -#define UART_UARTICR_RIMIC_BITS _u(0x00000001) -#define UART_UARTICR_RIMIC_MSB _u(0) -#define UART_UARTICR_RIMIC_LSB _u(0) -#define UART_UARTICR_RIMIC_ACCESS "WC" -// ============================================================================= -// Register : UART_UARTDMACR -// Description : DMA Control Register, UARTDMACR -#define UART_UARTDMACR_OFFSET _u(0x00000048) -#define UART_UARTDMACR_BITS _u(0x00000007) -#define UART_UARTDMACR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : UART_UARTDMACR_DMAONERR -// Description : DMA on error. If this bit is set to 1, the DMA receive request -// outputs, UARTRXDMASREQ or UARTRXDMABREQ, are disabled when the -// UART error interrupt is asserted. -#define UART_UARTDMACR_DMAONERR_RESET _u(0x0) -#define UART_UARTDMACR_DMAONERR_BITS _u(0x00000004) -#define UART_UARTDMACR_DMAONERR_MSB _u(2) -#define UART_UARTDMACR_DMAONERR_LSB _u(2) -#define UART_UARTDMACR_DMAONERR_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : UART_UARTDMACR_TXDMAE -// Description : Transmit DMA enable. If this bit is set to 1, DMA for the -// transmit FIFO is enabled. -#define UART_UARTDMACR_TXDMAE_RESET _u(0x0) -#define UART_UARTDMACR_TXDMAE_BITS _u(0x00000002) -#define UART_UARTDMACR_TXDMAE_MSB _u(1) -#define UART_UARTDMACR_TXDMAE_LSB _u(1) -#define UART_UARTDMACR_TXDMAE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : UART_UARTDMACR_RXDMAE -// Description : Receive DMA enable. If this bit is set to 1, DMA for the -// receive FIFO is enabled. -#define UART_UARTDMACR_RXDMAE_RESET _u(0x0) -#define UART_UARTDMACR_RXDMAE_BITS _u(0x00000001) -#define UART_UARTDMACR_RXDMAE_MSB _u(0) -#define UART_UARTDMACR_RXDMAE_LSB _u(0) -#define UART_UARTDMACR_RXDMAE_ACCESS "RW" -// ============================================================================= -// Register : UART_UARTPERIPHID0 -// Description : UARTPeriphID0 Register -#define UART_UARTPERIPHID0_OFFSET _u(0x00000fe0) -#define UART_UARTPERIPHID0_BITS _u(0x000000ff) -#define UART_UARTPERIPHID0_RESET _u(0x00000011) -// ----------------------------------------------------------------------------- -// Field : UART_UARTPERIPHID0_PARTNUMBER0 -// Description : These bits read back as 0x11 -#define UART_UARTPERIPHID0_PARTNUMBER0_RESET _u(0x11) -#define UART_UARTPERIPHID0_PARTNUMBER0_BITS _u(0x000000ff) -#define UART_UARTPERIPHID0_PARTNUMBER0_MSB _u(7) -#define UART_UARTPERIPHID0_PARTNUMBER0_LSB _u(0) -#define UART_UARTPERIPHID0_PARTNUMBER0_ACCESS "RO" -// ============================================================================= -// Register : UART_UARTPERIPHID1 -// Description : UARTPeriphID1 Register -#define UART_UARTPERIPHID1_OFFSET _u(0x00000fe4) -#define UART_UARTPERIPHID1_BITS _u(0x000000ff) -#define UART_UARTPERIPHID1_RESET _u(0x00000010) -// ----------------------------------------------------------------------------- -// Field : UART_UARTPERIPHID1_DESIGNER0 -// Description : These bits read back as 0x1 -#define UART_UARTPERIPHID1_DESIGNER0_RESET _u(0x1) -#define UART_UARTPERIPHID1_DESIGNER0_BITS _u(0x000000f0) -#define UART_UARTPERIPHID1_DESIGNER0_MSB _u(7) -#define UART_UARTPERIPHID1_DESIGNER0_LSB _u(4) -#define UART_UARTPERIPHID1_DESIGNER0_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : UART_UARTPERIPHID1_PARTNUMBER1 -// Description : These bits read back as 0x0 -#define UART_UARTPERIPHID1_PARTNUMBER1_RESET _u(0x0) -#define UART_UARTPERIPHID1_PARTNUMBER1_BITS _u(0x0000000f) -#define UART_UARTPERIPHID1_PARTNUMBER1_MSB _u(3) -#define UART_UARTPERIPHID1_PARTNUMBER1_LSB _u(0) -#define UART_UARTPERIPHID1_PARTNUMBER1_ACCESS "RO" -// ============================================================================= -// Register : UART_UARTPERIPHID2 -// Description : UARTPeriphID2 Register -#define UART_UARTPERIPHID2_OFFSET _u(0x00000fe8) -#define UART_UARTPERIPHID2_BITS _u(0x000000ff) -#define UART_UARTPERIPHID2_RESET _u(0x00000034) -// ----------------------------------------------------------------------------- -// Field : UART_UARTPERIPHID2_REVISION -// Description : This field depends on the revision of the UART: r1p0 0x0 r1p1 -// 0x1 r1p3 0x2 r1p4 0x2 r1p5 0x3 -#define UART_UARTPERIPHID2_REVISION_RESET _u(0x3) -#define UART_UARTPERIPHID2_REVISION_BITS _u(0x000000f0) -#define UART_UARTPERIPHID2_REVISION_MSB _u(7) -#define UART_UARTPERIPHID2_REVISION_LSB _u(4) -#define UART_UARTPERIPHID2_REVISION_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : UART_UARTPERIPHID2_DESIGNER1 -// Description : These bits read back as 0x4 -#define UART_UARTPERIPHID2_DESIGNER1_RESET _u(0x4) -#define UART_UARTPERIPHID2_DESIGNER1_BITS _u(0x0000000f) -#define UART_UARTPERIPHID2_DESIGNER1_MSB _u(3) -#define UART_UARTPERIPHID2_DESIGNER1_LSB _u(0) -#define UART_UARTPERIPHID2_DESIGNER1_ACCESS "RO" -// ============================================================================= -// Register : UART_UARTPERIPHID3 -// Description : UARTPeriphID3 Register -#define UART_UARTPERIPHID3_OFFSET _u(0x00000fec) -#define UART_UARTPERIPHID3_BITS _u(0x000000ff) -#define UART_UARTPERIPHID3_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : UART_UARTPERIPHID3_CONFIGURATION -// Description : These bits read back as 0x00 -#define UART_UARTPERIPHID3_CONFIGURATION_RESET _u(0x00) -#define UART_UARTPERIPHID3_CONFIGURATION_BITS _u(0x000000ff) -#define UART_UARTPERIPHID3_CONFIGURATION_MSB _u(7) -#define UART_UARTPERIPHID3_CONFIGURATION_LSB _u(0) -#define UART_UARTPERIPHID3_CONFIGURATION_ACCESS "RO" -// ============================================================================= -// Register : UART_UARTPCELLID0 -// Description : UARTPCellID0 Register -#define UART_UARTPCELLID0_OFFSET _u(0x00000ff0) -#define UART_UARTPCELLID0_BITS _u(0x000000ff) -#define UART_UARTPCELLID0_RESET _u(0x0000000d) -// ----------------------------------------------------------------------------- -// Field : UART_UARTPCELLID0_UARTPCELLID0 -// Description : These bits read back as 0x0D -#define UART_UARTPCELLID0_UARTPCELLID0_RESET _u(0x0d) -#define UART_UARTPCELLID0_UARTPCELLID0_BITS _u(0x000000ff) -#define UART_UARTPCELLID0_UARTPCELLID0_MSB _u(7) -#define UART_UARTPCELLID0_UARTPCELLID0_LSB _u(0) -#define UART_UARTPCELLID0_UARTPCELLID0_ACCESS "RO" -// ============================================================================= -// Register : UART_UARTPCELLID1 -// Description : UARTPCellID1 Register -#define UART_UARTPCELLID1_OFFSET _u(0x00000ff4) -#define UART_UARTPCELLID1_BITS _u(0x000000ff) -#define UART_UARTPCELLID1_RESET _u(0x000000f0) -// ----------------------------------------------------------------------------- -// Field : UART_UARTPCELLID1_UARTPCELLID1 -// Description : These bits read back as 0xF0 -#define UART_UARTPCELLID1_UARTPCELLID1_RESET _u(0xf0) -#define UART_UARTPCELLID1_UARTPCELLID1_BITS _u(0x000000ff) -#define UART_UARTPCELLID1_UARTPCELLID1_MSB _u(7) -#define UART_UARTPCELLID1_UARTPCELLID1_LSB _u(0) -#define UART_UARTPCELLID1_UARTPCELLID1_ACCESS "RO" -// ============================================================================= -// Register : UART_UARTPCELLID2 -// Description : UARTPCellID2 Register -#define UART_UARTPCELLID2_OFFSET _u(0x00000ff8) -#define UART_UARTPCELLID2_BITS _u(0x000000ff) -#define UART_UARTPCELLID2_RESET _u(0x00000005) -// ----------------------------------------------------------------------------- -// Field : UART_UARTPCELLID2_UARTPCELLID2 -// Description : These bits read back as 0x05 -#define UART_UARTPCELLID2_UARTPCELLID2_RESET _u(0x05) -#define UART_UARTPCELLID2_UARTPCELLID2_BITS _u(0x000000ff) -#define UART_UARTPCELLID2_UARTPCELLID2_MSB _u(7) -#define UART_UARTPCELLID2_UARTPCELLID2_LSB _u(0) -#define UART_UARTPCELLID2_UARTPCELLID2_ACCESS "RO" -// ============================================================================= -// Register : UART_UARTPCELLID3 -// Description : UARTPCellID3 Register -#define UART_UARTPCELLID3_OFFSET _u(0x00000ffc) -#define UART_UARTPCELLID3_BITS _u(0x000000ff) -#define UART_UARTPCELLID3_RESET _u(0x000000b1) -// ----------------------------------------------------------------------------- -// Field : UART_UARTPCELLID3_UARTPCELLID3 -// Description : These bits read back as 0xB1 -#define UART_UARTPCELLID3_UARTPCELLID3_RESET _u(0xb1) -#define UART_UARTPCELLID3_UARTPCELLID3_BITS _u(0x000000ff) -#define UART_UARTPCELLID3_UARTPCELLID3_MSB _u(7) -#define UART_UARTPCELLID3_UARTPCELLID3_LSB _u(0) -#define UART_UARTPCELLID3_UARTPCELLID3_ACCESS "RO" -// ============================================================================= -#endif // _HARDWARE_REGS_UART_H - diff --git a/lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/usb.h b/lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/usb.h deleted file mode 100644 index 291f65ee74..0000000000 --- a/lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/usb.h +++ /dev/null @@ -1,3453 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -// ============================================================================= -// Register block : USB -// Version : 1 -// Bus type : ahbl -// Description : USB FS/LS controller device registers -// ============================================================================= -#ifndef _HARDWARE_REGS_USB_H -#define _HARDWARE_REGS_USB_H -// ============================================================================= -// Register : USB_ADDR_ENDP -// Description : Device address and endpoint control -#define USB_ADDR_ENDP_OFFSET _u(0x00000000) -#define USB_ADDR_ENDP_BITS _u(0x000f007f) -#define USB_ADDR_ENDP_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_ADDR_ENDP_ENDPOINT -// Description : Device endpoint to send data to. Only valid for HOST mode. -#define USB_ADDR_ENDP_ENDPOINT_RESET _u(0x0) -#define USB_ADDR_ENDP_ENDPOINT_BITS _u(0x000f0000) -#define USB_ADDR_ENDP_ENDPOINT_MSB _u(19) -#define USB_ADDR_ENDP_ENDPOINT_LSB _u(16) -#define USB_ADDR_ENDP_ENDPOINT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_ADDR_ENDP_ADDRESS -// Description : In device mode, the address that the device should respond to. -// Set in response to a SET_ADDR setup packet from the host. In -// host mode set to the address of the device to communicate with. -#define USB_ADDR_ENDP_ADDRESS_RESET _u(0x00) -#define USB_ADDR_ENDP_ADDRESS_BITS _u(0x0000007f) -#define USB_ADDR_ENDP_ADDRESS_MSB _u(6) -#define USB_ADDR_ENDP_ADDRESS_LSB _u(0) -#define USB_ADDR_ENDP_ADDRESS_ACCESS "RW" -// ============================================================================= -// Register : USB_ADDR_ENDP1 -// Description : Interrupt endpoint 1. Only valid for HOST mode. -#define USB_ADDR_ENDP1_OFFSET _u(0x00000004) -#define USB_ADDR_ENDP1_BITS _u(0x060f007f) -#define USB_ADDR_ENDP1_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_ADDR_ENDP1_INTEP_PREAMBLE -// Description : Interrupt EP requires preamble (is a low speed device on a full -// speed hub) -#define USB_ADDR_ENDP1_INTEP_PREAMBLE_RESET _u(0x0) -#define USB_ADDR_ENDP1_INTEP_PREAMBLE_BITS _u(0x04000000) -#define USB_ADDR_ENDP1_INTEP_PREAMBLE_MSB _u(26) -#define USB_ADDR_ENDP1_INTEP_PREAMBLE_LSB _u(26) -#define USB_ADDR_ENDP1_INTEP_PREAMBLE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_ADDR_ENDP1_INTEP_DIR -// Description : Direction of the interrupt endpoint. In=0, Out=1 -#define USB_ADDR_ENDP1_INTEP_DIR_RESET _u(0x0) -#define USB_ADDR_ENDP1_INTEP_DIR_BITS _u(0x02000000) -#define USB_ADDR_ENDP1_INTEP_DIR_MSB _u(25) -#define USB_ADDR_ENDP1_INTEP_DIR_LSB _u(25) -#define USB_ADDR_ENDP1_INTEP_DIR_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_ADDR_ENDP1_ENDPOINT -// Description : Endpoint number of the interrupt endpoint -#define USB_ADDR_ENDP1_ENDPOINT_RESET _u(0x0) -#define USB_ADDR_ENDP1_ENDPOINT_BITS _u(0x000f0000) -#define USB_ADDR_ENDP1_ENDPOINT_MSB _u(19) -#define USB_ADDR_ENDP1_ENDPOINT_LSB _u(16) -#define USB_ADDR_ENDP1_ENDPOINT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_ADDR_ENDP1_ADDRESS -// Description : Device address -#define USB_ADDR_ENDP1_ADDRESS_RESET _u(0x00) -#define USB_ADDR_ENDP1_ADDRESS_BITS _u(0x0000007f) -#define USB_ADDR_ENDP1_ADDRESS_MSB _u(6) -#define USB_ADDR_ENDP1_ADDRESS_LSB _u(0) -#define USB_ADDR_ENDP1_ADDRESS_ACCESS "RW" -// ============================================================================= -// Register : USB_ADDR_ENDP2 -// Description : Interrupt endpoint 2. Only valid for HOST mode. -#define USB_ADDR_ENDP2_OFFSET _u(0x00000008) -#define USB_ADDR_ENDP2_BITS _u(0x060f007f) -#define USB_ADDR_ENDP2_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_ADDR_ENDP2_INTEP_PREAMBLE -// Description : Interrupt EP requires preamble (is a low speed device on a full -// speed hub) -#define USB_ADDR_ENDP2_INTEP_PREAMBLE_RESET _u(0x0) -#define USB_ADDR_ENDP2_INTEP_PREAMBLE_BITS _u(0x04000000) -#define USB_ADDR_ENDP2_INTEP_PREAMBLE_MSB _u(26) -#define USB_ADDR_ENDP2_INTEP_PREAMBLE_LSB _u(26) -#define USB_ADDR_ENDP2_INTEP_PREAMBLE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_ADDR_ENDP2_INTEP_DIR -// Description : Direction of the interrupt endpoint. In=0, Out=1 -#define USB_ADDR_ENDP2_INTEP_DIR_RESET _u(0x0) -#define USB_ADDR_ENDP2_INTEP_DIR_BITS _u(0x02000000) -#define USB_ADDR_ENDP2_INTEP_DIR_MSB _u(25) -#define USB_ADDR_ENDP2_INTEP_DIR_LSB _u(25) -#define USB_ADDR_ENDP2_INTEP_DIR_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_ADDR_ENDP2_ENDPOINT -// Description : Endpoint number of the interrupt endpoint -#define USB_ADDR_ENDP2_ENDPOINT_RESET _u(0x0) -#define USB_ADDR_ENDP2_ENDPOINT_BITS _u(0x000f0000) -#define USB_ADDR_ENDP2_ENDPOINT_MSB _u(19) -#define USB_ADDR_ENDP2_ENDPOINT_LSB _u(16) -#define USB_ADDR_ENDP2_ENDPOINT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_ADDR_ENDP2_ADDRESS -// Description : Device address -#define USB_ADDR_ENDP2_ADDRESS_RESET _u(0x00) -#define USB_ADDR_ENDP2_ADDRESS_BITS _u(0x0000007f) -#define USB_ADDR_ENDP2_ADDRESS_MSB _u(6) -#define USB_ADDR_ENDP2_ADDRESS_LSB _u(0) -#define USB_ADDR_ENDP2_ADDRESS_ACCESS "RW" -// ============================================================================= -// Register : USB_ADDR_ENDP3 -// Description : Interrupt endpoint 3. Only valid for HOST mode. -#define USB_ADDR_ENDP3_OFFSET _u(0x0000000c) -#define USB_ADDR_ENDP3_BITS _u(0x060f007f) -#define USB_ADDR_ENDP3_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_ADDR_ENDP3_INTEP_PREAMBLE -// Description : Interrupt EP requires preamble (is a low speed device on a full -// speed hub) -#define USB_ADDR_ENDP3_INTEP_PREAMBLE_RESET _u(0x0) -#define USB_ADDR_ENDP3_INTEP_PREAMBLE_BITS _u(0x04000000) -#define USB_ADDR_ENDP3_INTEP_PREAMBLE_MSB _u(26) -#define USB_ADDR_ENDP3_INTEP_PREAMBLE_LSB _u(26) -#define USB_ADDR_ENDP3_INTEP_PREAMBLE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_ADDR_ENDP3_INTEP_DIR -// Description : Direction of the interrupt endpoint. In=0, Out=1 -#define USB_ADDR_ENDP3_INTEP_DIR_RESET _u(0x0) -#define USB_ADDR_ENDP3_INTEP_DIR_BITS _u(0x02000000) -#define USB_ADDR_ENDP3_INTEP_DIR_MSB _u(25) -#define USB_ADDR_ENDP3_INTEP_DIR_LSB _u(25) -#define USB_ADDR_ENDP3_INTEP_DIR_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_ADDR_ENDP3_ENDPOINT -// Description : Endpoint number of the interrupt endpoint -#define USB_ADDR_ENDP3_ENDPOINT_RESET _u(0x0) -#define USB_ADDR_ENDP3_ENDPOINT_BITS _u(0x000f0000) -#define USB_ADDR_ENDP3_ENDPOINT_MSB _u(19) -#define USB_ADDR_ENDP3_ENDPOINT_LSB _u(16) -#define USB_ADDR_ENDP3_ENDPOINT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_ADDR_ENDP3_ADDRESS -// Description : Device address -#define USB_ADDR_ENDP3_ADDRESS_RESET _u(0x00) -#define USB_ADDR_ENDP3_ADDRESS_BITS _u(0x0000007f) -#define USB_ADDR_ENDP3_ADDRESS_MSB _u(6) -#define USB_ADDR_ENDP3_ADDRESS_LSB _u(0) -#define USB_ADDR_ENDP3_ADDRESS_ACCESS "RW" -// ============================================================================= -// Register : USB_ADDR_ENDP4 -// Description : Interrupt endpoint 4. Only valid for HOST mode. -#define USB_ADDR_ENDP4_OFFSET _u(0x00000010) -#define USB_ADDR_ENDP4_BITS _u(0x060f007f) -#define USB_ADDR_ENDP4_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_ADDR_ENDP4_INTEP_PREAMBLE -// Description : Interrupt EP requires preamble (is a low speed device on a full -// speed hub) -#define USB_ADDR_ENDP4_INTEP_PREAMBLE_RESET _u(0x0) -#define USB_ADDR_ENDP4_INTEP_PREAMBLE_BITS _u(0x04000000) -#define USB_ADDR_ENDP4_INTEP_PREAMBLE_MSB _u(26) -#define USB_ADDR_ENDP4_INTEP_PREAMBLE_LSB _u(26) -#define USB_ADDR_ENDP4_INTEP_PREAMBLE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_ADDR_ENDP4_INTEP_DIR -// Description : Direction of the interrupt endpoint. In=0, Out=1 -#define USB_ADDR_ENDP4_INTEP_DIR_RESET _u(0x0) -#define USB_ADDR_ENDP4_INTEP_DIR_BITS _u(0x02000000) -#define USB_ADDR_ENDP4_INTEP_DIR_MSB _u(25) -#define USB_ADDR_ENDP4_INTEP_DIR_LSB _u(25) -#define USB_ADDR_ENDP4_INTEP_DIR_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_ADDR_ENDP4_ENDPOINT -// Description : Endpoint number of the interrupt endpoint -#define USB_ADDR_ENDP4_ENDPOINT_RESET _u(0x0) -#define USB_ADDR_ENDP4_ENDPOINT_BITS _u(0x000f0000) -#define USB_ADDR_ENDP4_ENDPOINT_MSB _u(19) -#define USB_ADDR_ENDP4_ENDPOINT_LSB _u(16) -#define USB_ADDR_ENDP4_ENDPOINT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_ADDR_ENDP4_ADDRESS -// Description : Device address -#define USB_ADDR_ENDP4_ADDRESS_RESET _u(0x00) -#define USB_ADDR_ENDP4_ADDRESS_BITS _u(0x0000007f) -#define USB_ADDR_ENDP4_ADDRESS_MSB _u(6) -#define USB_ADDR_ENDP4_ADDRESS_LSB _u(0) -#define USB_ADDR_ENDP4_ADDRESS_ACCESS "RW" -// ============================================================================= -// Register : USB_ADDR_ENDP5 -// Description : Interrupt endpoint 5. Only valid for HOST mode. -#define USB_ADDR_ENDP5_OFFSET _u(0x00000014) -#define USB_ADDR_ENDP5_BITS _u(0x060f007f) -#define USB_ADDR_ENDP5_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_ADDR_ENDP5_INTEP_PREAMBLE -// Description : Interrupt EP requires preamble (is a low speed device on a full -// speed hub) -#define USB_ADDR_ENDP5_INTEP_PREAMBLE_RESET _u(0x0) -#define USB_ADDR_ENDP5_INTEP_PREAMBLE_BITS _u(0x04000000) -#define USB_ADDR_ENDP5_INTEP_PREAMBLE_MSB _u(26) -#define USB_ADDR_ENDP5_INTEP_PREAMBLE_LSB _u(26) -#define USB_ADDR_ENDP5_INTEP_PREAMBLE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_ADDR_ENDP5_INTEP_DIR -// Description : Direction of the interrupt endpoint. In=0, Out=1 -#define USB_ADDR_ENDP5_INTEP_DIR_RESET _u(0x0) -#define USB_ADDR_ENDP5_INTEP_DIR_BITS _u(0x02000000) -#define USB_ADDR_ENDP5_INTEP_DIR_MSB _u(25) -#define USB_ADDR_ENDP5_INTEP_DIR_LSB _u(25) -#define USB_ADDR_ENDP5_INTEP_DIR_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_ADDR_ENDP5_ENDPOINT -// Description : Endpoint number of the interrupt endpoint -#define USB_ADDR_ENDP5_ENDPOINT_RESET _u(0x0) -#define USB_ADDR_ENDP5_ENDPOINT_BITS _u(0x000f0000) -#define USB_ADDR_ENDP5_ENDPOINT_MSB _u(19) -#define USB_ADDR_ENDP5_ENDPOINT_LSB _u(16) -#define USB_ADDR_ENDP5_ENDPOINT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_ADDR_ENDP5_ADDRESS -// Description : Device address -#define USB_ADDR_ENDP5_ADDRESS_RESET _u(0x00) -#define USB_ADDR_ENDP5_ADDRESS_BITS _u(0x0000007f) -#define USB_ADDR_ENDP5_ADDRESS_MSB _u(6) -#define USB_ADDR_ENDP5_ADDRESS_LSB _u(0) -#define USB_ADDR_ENDP5_ADDRESS_ACCESS "RW" -// ============================================================================= -// Register : USB_ADDR_ENDP6 -// Description : Interrupt endpoint 6. Only valid for HOST mode. -#define USB_ADDR_ENDP6_OFFSET _u(0x00000018) -#define USB_ADDR_ENDP6_BITS _u(0x060f007f) -#define USB_ADDR_ENDP6_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_ADDR_ENDP6_INTEP_PREAMBLE -// Description : Interrupt EP requires preamble (is a low speed device on a full -// speed hub) -#define USB_ADDR_ENDP6_INTEP_PREAMBLE_RESET _u(0x0) -#define USB_ADDR_ENDP6_INTEP_PREAMBLE_BITS _u(0x04000000) -#define USB_ADDR_ENDP6_INTEP_PREAMBLE_MSB _u(26) -#define USB_ADDR_ENDP6_INTEP_PREAMBLE_LSB _u(26) -#define USB_ADDR_ENDP6_INTEP_PREAMBLE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_ADDR_ENDP6_INTEP_DIR -// Description : Direction of the interrupt endpoint. In=0, Out=1 -#define USB_ADDR_ENDP6_INTEP_DIR_RESET _u(0x0) -#define USB_ADDR_ENDP6_INTEP_DIR_BITS _u(0x02000000) -#define USB_ADDR_ENDP6_INTEP_DIR_MSB _u(25) -#define USB_ADDR_ENDP6_INTEP_DIR_LSB _u(25) -#define USB_ADDR_ENDP6_INTEP_DIR_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_ADDR_ENDP6_ENDPOINT -// Description : Endpoint number of the interrupt endpoint -#define USB_ADDR_ENDP6_ENDPOINT_RESET _u(0x0) -#define USB_ADDR_ENDP6_ENDPOINT_BITS _u(0x000f0000) -#define USB_ADDR_ENDP6_ENDPOINT_MSB _u(19) -#define USB_ADDR_ENDP6_ENDPOINT_LSB _u(16) -#define USB_ADDR_ENDP6_ENDPOINT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_ADDR_ENDP6_ADDRESS -// Description : Device address -#define USB_ADDR_ENDP6_ADDRESS_RESET _u(0x00) -#define USB_ADDR_ENDP6_ADDRESS_BITS _u(0x0000007f) -#define USB_ADDR_ENDP6_ADDRESS_MSB _u(6) -#define USB_ADDR_ENDP6_ADDRESS_LSB _u(0) -#define USB_ADDR_ENDP6_ADDRESS_ACCESS "RW" -// ============================================================================= -// Register : USB_ADDR_ENDP7 -// Description : Interrupt endpoint 7. Only valid for HOST mode. -#define USB_ADDR_ENDP7_OFFSET _u(0x0000001c) -#define USB_ADDR_ENDP7_BITS _u(0x060f007f) -#define USB_ADDR_ENDP7_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_ADDR_ENDP7_INTEP_PREAMBLE -// Description : Interrupt EP requires preamble (is a low speed device on a full -// speed hub) -#define USB_ADDR_ENDP7_INTEP_PREAMBLE_RESET _u(0x0) -#define USB_ADDR_ENDP7_INTEP_PREAMBLE_BITS _u(0x04000000) -#define USB_ADDR_ENDP7_INTEP_PREAMBLE_MSB _u(26) -#define USB_ADDR_ENDP7_INTEP_PREAMBLE_LSB _u(26) -#define USB_ADDR_ENDP7_INTEP_PREAMBLE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_ADDR_ENDP7_INTEP_DIR -// Description : Direction of the interrupt endpoint. In=0, Out=1 -#define USB_ADDR_ENDP7_INTEP_DIR_RESET _u(0x0) -#define USB_ADDR_ENDP7_INTEP_DIR_BITS _u(0x02000000) -#define USB_ADDR_ENDP7_INTEP_DIR_MSB _u(25) -#define USB_ADDR_ENDP7_INTEP_DIR_LSB _u(25) -#define USB_ADDR_ENDP7_INTEP_DIR_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_ADDR_ENDP7_ENDPOINT -// Description : Endpoint number of the interrupt endpoint -#define USB_ADDR_ENDP7_ENDPOINT_RESET _u(0x0) -#define USB_ADDR_ENDP7_ENDPOINT_BITS _u(0x000f0000) -#define USB_ADDR_ENDP7_ENDPOINT_MSB _u(19) -#define USB_ADDR_ENDP7_ENDPOINT_LSB _u(16) -#define USB_ADDR_ENDP7_ENDPOINT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_ADDR_ENDP7_ADDRESS -// Description : Device address -#define USB_ADDR_ENDP7_ADDRESS_RESET _u(0x00) -#define USB_ADDR_ENDP7_ADDRESS_BITS _u(0x0000007f) -#define USB_ADDR_ENDP7_ADDRESS_MSB _u(6) -#define USB_ADDR_ENDP7_ADDRESS_LSB _u(0) -#define USB_ADDR_ENDP7_ADDRESS_ACCESS "RW" -// ============================================================================= -// Register : USB_ADDR_ENDP8 -// Description : Interrupt endpoint 8. Only valid for HOST mode. -#define USB_ADDR_ENDP8_OFFSET _u(0x00000020) -#define USB_ADDR_ENDP8_BITS _u(0x060f007f) -#define USB_ADDR_ENDP8_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_ADDR_ENDP8_INTEP_PREAMBLE -// Description : Interrupt EP requires preamble (is a low speed device on a full -// speed hub) -#define USB_ADDR_ENDP8_INTEP_PREAMBLE_RESET _u(0x0) -#define USB_ADDR_ENDP8_INTEP_PREAMBLE_BITS _u(0x04000000) -#define USB_ADDR_ENDP8_INTEP_PREAMBLE_MSB _u(26) -#define USB_ADDR_ENDP8_INTEP_PREAMBLE_LSB _u(26) -#define USB_ADDR_ENDP8_INTEP_PREAMBLE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_ADDR_ENDP8_INTEP_DIR -// Description : Direction of the interrupt endpoint. In=0, Out=1 -#define USB_ADDR_ENDP8_INTEP_DIR_RESET _u(0x0) -#define USB_ADDR_ENDP8_INTEP_DIR_BITS _u(0x02000000) -#define USB_ADDR_ENDP8_INTEP_DIR_MSB _u(25) -#define USB_ADDR_ENDP8_INTEP_DIR_LSB _u(25) -#define USB_ADDR_ENDP8_INTEP_DIR_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_ADDR_ENDP8_ENDPOINT -// Description : Endpoint number of the interrupt endpoint -#define USB_ADDR_ENDP8_ENDPOINT_RESET _u(0x0) -#define USB_ADDR_ENDP8_ENDPOINT_BITS _u(0x000f0000) -#define USB_ADDR_ENDP8_ENDPOINT_MSB _u(19) -#define USB_ADDR_ENDP8_ENDPOINT_LSB _u(16) -#define USB_ADDR_ENDP8_ENDPOINT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_ADDR_ENDP8_ADDRESS -// Description : Device address -#define USB_ADDR_ENDP8_ADDRESS_RESET _u(0x00) -#define USB_ADDR_ENDP8_ADDRESS_BITS _u(0x0000007f) -#define USB_ADDR_ENDP8_ADDRESS_MSB _u(6) -#define USB_ADDR_ENDP8_ADDRESS_LSB _u(0) -#define USB_ADDR_ENDP8_ADDRESS_ACCESS "RW" -// ============================================================================= -// Register : USB_ADDR_ENDP9 -// Description : Interrupt endpoint 9. Only valid for HOST mode. -#define USB_ADDR_ENDP9_OFFSET _u(0x00000024) -#define USB_ADDR_ENDP9_BITS _u(0x060f007f) -#define USB_ADDR_ENDP9_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_ADDR_ENDP9_INTEP_PREAMBLE -// Description : Interrupt EP requires preamble (is a low speed device on a full -// speed hub) -#define USB_ADDR_ENDP9_INTEP_PREAMBLE_RESET _u(0x0) -#define USB_ADDR_ENDP9_INTEP_PREAMBLE_BITS _u(0x04000000) -#define USB_ADDR_ENDP9_INTEP_PREAMBLE_MSB _u(26) -#define USB_ADDR_ENDP9_INTEP_PREAMBLE_LSB _u(26) -#define USB_ADDR_ENDP9_INTEP_PREAMBLE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_ADDR_ENDP9_INTEP_DIR -// Description : Direction of the interrupt endpoint. In=0, Out=1 -#define USB_ADDR_ENDP9_INTEP_DIR_RESET _u(0x0) -#define USB_ADDR_ENDP9_INTEP_DIR_BITS _u(0x02000000) -#define USB_ADDR_ENDP9_INTEP_DIR_MSB _u(25) -#define USB_ADDR_ENDP9_INTEP_DIR_LSB _u(25) -#define USB_ADDR_ENDP9_INTEP_DIR_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_ADDR_ENDP9_ENDPOINT -// Description : Endpoint number of the interrupt endpoint -#define USB_ADDR_ENDP9_ENDPOINT_RESET _u(0x0) -#define USB_ADDR_ENDP9_ENDPOINT_BITS _u(0x000f0000) -#define USB_ADDR_ENDP9_ENDPOINT_MSB _u(19) -#define USB_ADDR_ENDP9_ENDPOINT_LSB _u(16) -#define USB_ADDR_ENDP9_ENDPOINT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_ADDR_ENDP9_ADDRESS -// Description : Device address -#define USB_ADDR_ENDP9_ADDRESS_RESET _u(0x00) -#define USB_ADDR_ENDP9_ADDRESS_BITS _u(0x0000007f) -#define USB_ADDR_ENDP9_ADDRESS_MSB _u(6) -#define USB_ADDR_ENDP9_ADDRESS_LSB _u(0) -#define USB_ADDR_ENDP9_ADDRESS_ACCESS "RW" -// ============================================================================= -// Register : USB_ADDR_ENDP10 -// Description : Interrupt endpoint 10. Only valid for HOST mode. -#define USB_ADDR_ENDP10_OFFSET _u(0x00000028) -#define USB_ADDR_ENDP10_BITS _u(0x060f007f) -#define USB_ADDR_ENDP10_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_ADDR_ENDP10_INTEP_PREAMBLE -// Description : Interrupt EP requires preamble (is a low speed device on a full -// speed hub) -#define USB_ADDR_ENDP10_INTEP_PREAMBLE_RESET _u(0x0) -#define USB_ADDR_ENDP10_INTEP_PREAMBLE_BITS _u(0x04000000) -#define USB_ADDR_ENDP10_INTEP_PREAMBLE_MSB _u(26) -#define USB_ADDR_ENDP10_INTEP_PREAMBLE_LSB _u(26) -#define USB_ADDR_ENDP10_INTEP_PREAMBLE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_ADDR_ENDP10_INTEP_DIR -// Description : Direction of the interrupt endpoint. In=0, Out=1 -#define USB_ADDR_ENDP10_INTEP_DIR_RESET _u(0x0) -#define USB_ADDR_ENDP10_INTEP_DIR_BITS _u(0x02000000) -#define USB_ADDR_ENDP10_INTEP_DIR_MSB _u(25) -#define USB_ADDR_ENDP10_INTEP_DIR_LSB _u(25) -#define USB_ADDR_ENDP10_INTEP_DIR_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_ADDR_ENDP10_ENDPOINT -// Description : Endpoint number of the interrupt endpoint -#define USB_ADDR_ENDP10_ENDPOINT_RESET _u(0x0) -#define USB_ADDR_ENDP10_ENDPOINT_BITS _u(0x000f0000) -#define USB_ADDR_ENDP10_ENDPOINT_MSB _u(19) -#define USB_ADDR_ENDP10_ENDPOINT_LSB _u(16) -#define USB_ADDR_ENDP10_ENDPOINT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_ADDR_ENDP10_ADDRESS -// Description : Device address -#define USB_ADDR_ENDP10_ADDRESS_RESET _u(0x00) -#define USB_ADDR_ENDP10_ADDRESS_BITS _u(0x0000007f) -#define USB_ADDR_ENDP10_ADDRESS_MSB _u(6) -#define USB_ADDR_ENDP10_ADDRESS_LSB _u(0) -#define USB_ADDR_ENDP10_ADDRESS_ACCESS "RW" -// ============================================================================= -// Register : USB_ADDR_ENDP11 -// Description : Interrupt endpoint 11. Only valid for HOST mode. -#define USB_ADDR_ENDP11_OFFSET _u(0x0000002c) -#define USB_ADDR_ENDP11_BITS _u(0x060f007f) -#define USB_ADDR_ENDP11_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_ADDR_ENDP11_INTEP_PREAMBLE -// Description : Interrupt EP requires preamble (is a low speed device on a full -// speed hub) -#define USB_ADDR_ENDP11_INTEP_PREAMBLE_RESET _u(0x0) -#define USB_ADDR_ENDP11_INTEP_PREAMBLE_BITS _u(0x04000000) -#define USB_ADDR_ENDP11_INTEP_PREAMBLE_MSB _u(26) -#define USB_ADDR_ENDP11_INTEP_PREAMBLE_LSB _u(26) -#define USB_ADDR_ENDP11_INTEP_PREAMBLE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_ADDR_ENDP11_INTEP_DIR -// Description : Direction of the interrupt endpoint. In=0, Out=1 -#define USB_ADDR_ENDP11_INTEP_DIR_RESET _u(0x0) -#define USB_ADDR_ENDP11_INTEP_DIR_BITS _u(0x02000000) -#define USB_ADDR_ENDP11_INTEP_DIR_MSB _u(25) -#define USB_ADDR_ENDP11_INTEP_DIR_LSB _u(25) -#define USB_ADDR_ENDP11_INTEP_DIR_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_ADDR_ENDP11_ENDPOINT -// Description : Endpoint number of the interrupt endpoint -#define USB_ADDR_ENDP11_ENDPOINT_RESET _u(0x0) -#define USB_ADDR_ENDP11_ENDPOINT_BITS _u(0x000f0000) -#define USB_ADDR_ENDP11_ENDPOINT_MSB _u(19) -#define USB_ADDR_ENDP11_ENDPOINT_LSB _u(16) -#define USB_ADDR_ENDP11_ENDPOINT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_ADDR_ENDP11_ADDRESS -// Description : Device address -#define USB_ADDR_ENDP11_ADDRESS_RESET _u(0x00) -#define USB_ADDR_ENDP11_ADDRESS_BITS _u(0x0000007f) -#define USB_ADDR_ENDP11_ADDRESS_MSB _u(6) -#define USB_ADDR_ENDP11_ADDRESS_LSB _u(0) -#define USB_ADDR_ENDP11_ADDRESS_ACCESS "RW" -// ============================================================================= -// Register : USB_ADDR_ENDP12 -// Description : Interrupt endpoint 12. Only valid for HOST mode. -#define USB_ADDR_ENDP12_OFFSET _u(0x00000030) -#define USB_ADDR_ENDP12_BITS _u(0x060f007f) -#define USB_ADDR_ENDP12_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_ADDR_ENDP12_INTEP_PREAMBLE -// Description : Interrupt EP requires preamble (is a low speed device on a full -// speed hub) -#define USB_ADDR_ENDP12_INTEP_PREAMBLE_RESET _u(0x0) -#define USB_ADDR_ENDP12_INTEP_PREAMBLE_BITS _u(0x04000000) -#define USB_ADDR_ENDP12_INTEP_PREAMBLE_MSB _u(26) -#define USB_ADDR_ENDP12_INTEP_PREAMBLE_LSB _u(26) -#define USB_ADDR_ENDP12_INTEP_PREAMBLE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_ADDR_ENDP12_INTEP_DIR -// Description : Direction of the interrupt endpoint. In=0, Out=1 -#define USB_ADDR_ENDP12_INTEP_DIR_RESET _u(0x0) -#define USB_ADDR_ENDP12_INTEP_DIR_BITS _u(0x02000000) -#define USB_ADDR_ENDP12_INTEP_DIR_MSB _u(25) -#define USB_ADDR_ENDP12_INTEP_DIR_LSB _u(25) -#define USB_ADDR_ENDP12_INTEP_DIR_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_ADDR_ENDP12_ENDPOINT -// Description : Endpoint number of the interrupt endpoint -#define USB_ADDR_ENDP12_ENDPOINT_RESET _u(0x0) -#define USB_ADDR_ENDP12_ENDPOINT_BITS _u(0x000f0000) -#define USB_ADDR_ENDP12_ENDPOINT_MSB _u(19) -#define USB_ADDR_ENDP12_ENDPOINT_LSB _u(16) -#define USB_ADDR_ENDP12_ENDPOINT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_ADDR_ENDP12_ADDRESS -// Description : Device address -#define USB_ADDR_ENDP12_ADDRESS_RESET _u(0x00) -#define USB_ADDR_ENDP12_ADDRESS_BITS _u(0x0000007f) -#define USB_ADDR_ENDP12_ADDRESS_MSB _u(6) -#define USB_ADDR_ENDP12_ADDRESS_LSB _u(0) -#define USB_ADDR_ENDP12_ADDRESS_ACCESS "RW" -// ============================================================================= -// Register : USB_ADDR_ENDP13 -// Description : Interrupt endpoint 13. Only valid for HOST mode. -#define USB_ADDR_ENDP13_OFFSET _u(0x00000034) -#define USB_ADDR_ENDP13_BITS _u(0x060f007f) -#define USB_ADDR_ENDP13_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_ADDR_ENDP13_INTEP_PREAMBLE -// Description : Interrupt EP requires preamble (is a low speed device on a full -// speed hub) -#define USB_ADDR_ENDP13_INTEP_PREAMBLE_RESET _u(0x0) -#define USB_ADDR_ENDP13_INTEP_PREAMBLE_BITS _u(0x04000000) -#define USB_ADDR_ENDP13_INTEP_PREAMBLE_MSB _u(26) -#define USB_ADDR_ENDP13_INTEP_PREAMBLE_LSB _u(26) -#define USB_ADDR_ENDP13_INTEP_PREAMBLE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_ADDR_ENDP13_INTEP_DIR -// Description : Direction of the interrupt endpoint. In=0, Out=1 -#define USB_ADDR_ENDP13_INTEP_DIR_RESET _u(0x0) -#define USB_ADDR_ENDP13_INTEP_DIR_BITS _u(0x02000000) -#define USB_ADDR_ENDP13_INTEP_DIR_MSB _u(25) -#define USB_ADDR_ENDP13_INTEP_DIR_LSB _u(25) -#define USB_ADDR_ENDP13_INTEP_DIR_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_ADDR_ENDP13_ENDPOINT -// Description : Endpoint number of the interrupt endpoint -#define USB_ADDR_ENDP13_ENDPOINT_RESET _u(0x0) -#define USB_ADDR_ENDP13_ENDPOINT_BITS _u(0x000f0000) -#define USB_ADDR_ENDP13_ENDPOINT_MSB _u(19) -#define USB_ADDR_ENDP13_ENDPOINT_LSB _u(16) -#define USB_ADDR_ENDP13_ENDPOINT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_ADDR_ENDP13_ADDRESS -// Description : Device address -#define USB_ADDR_ENDP13_ADDRESS_RESET _u(0x00) -#define USB_ADDR_ENDP13_ADDRESS_BITS _u(0x0000007f) -#define USB_ADDR_ENDP13_ADDRESS_MSB _u(6) -#define USB_ADDR_ENDP13_ADDRESS_LSB _u(0) -#define USB_ADDR_ENDP13_ADDRESS_ACCESS "RW" -// ============================================================================= -// Register : USB_ADDR_ENDP14 -// Description : Interrupt endpoint 14. Only valid for HOST mode. -#define USB_ADDR_ENDP14_OFFSET _u(0x00000038) -#define USB_ADDR_ENDP14_BITS _u(0x060f007f) -#define USB_ADDR_ENDP14_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_ADDR_ENDP14_INTEP_PREAMBLE -// Description : Interrupt EP requires preamble (is a low speed device on a full -// speed hub) -#define USB_ADDR_ENDP14_INTEP_PREAMBLE_RESET _u(0x0) -#define USB_ADDR_ENDP14_INTEP_PREAMBLE_BITS _u(0x04000000) -#define USB_ADDR_ENDP14_INTEP_PREAMBLE_MSB _u(26) -#define USB_ADDR_ENDP14_INTEP_PREAMBLE_LSB _u(26) -#define USB_ADDR_ENDP14_INTEP_PREAMBLE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_ADDR_ENDP14_INTEP_DIR -// Description : Direction of the interrupt endpoint. In=0, Out=1 -#define USB_ADDR_ENDP14_INTEP_DIR_RESET _u(0x0) -#define USB_ADDR_ENDP14_INTEP_DIR_BITS _u(0x02000000) -#define USB_ADDR_ENDP14_INTEP_DIR_MSB _u(25) -#define USB_ADDR_ENDP14_INTEP_DIR_LSB _u(25) -#define USB_ADDR_ENDP14_INTEP_DIR_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_ADDR_ENDP14_ENDPOINT -// Description : Endpoint number of the interrupt endpoint -#define USB_ADDR_ENDP14_ENDPOINT_RESET _u(0x0) -#define USB_ADDR_ENDP14_ENDPOINT_BITS _u(0x000f0000) -#define USB_ADDR_ENDP14_ENDPOINT_MSB _u(19) -#define USB_ADDR_ENDP14_ENDPOINT_LSB _u(16) -#define USB_ADDR_ENDP14_ENDPOINT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_ADDR_ENDP14_ADDRESS -// Description : Device address -#define USB_ADDR_ENDP14_ADDRESS_RESET _u(0x00) -#define USB_ADDR_ENDP14_ADDRESS_BITS _u(0x0000007f) -#define USB_ADDR_ENDP14_ADDRESS_MSB _u(6) -#define USB_ADDR_ENDP14_ADDRESS_LSB _u(0) -#define USB_ADDR_ENDP14_ADDRESS_ACCESS "RW" -// ============================================================================= -// Register : USB_ADDR_ENDP15 -// Description : Interrupt endpoint 15. Only valid for HOST mode. -#define USB_ADDR_ENDP15_OFFSET _u(0x0000003c) -#define USB_ADDR_ENDP15_BITS _u(0x060f007f) -#define USB_ADDR_ENDP15_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_ADDR_ENDP15_INTEP_PREAMBLE -// Description : Interrupt EP requires preamble (is a low speed device on a full -// speed hub) -#define USB_ADDR_ENDP15_INTEP_PREAMBLE_RESET _u(0x0) -#define USB_ADDR_ENDP15_INTEP_PREAMBLE_BITS _u(0x04000000) -#define USB_ADDR_ENDP15_INTEP_PREAMBLE_MSB _u(26) -#define USB_ADDR_ENDP15_INTEP_PREAMBLE_LSB _u(26) -#define USB_ADDR_ENDP15_INTEP_PREAMBLE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_ADDR_ENDP15_INTEP_DIR -// Description : Direction of the interrupt endpoint. In=0, Out=1 -#define USB_ADDR_ENDP15_INTEP_DIR_RESET _u(0x0) -#define USB_ADDR_ENDP15_INTEP_DIR_BITS _u(0x02000000) -#define USB_ADDR_ENDP15_INTEP_DIR_MSB _u(25) -#define USB_ADDR_ENDP15_INTEP_DIR_LSB _u(25) -#define USB_ADDR_ENDP15_INTEP_DIR_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_ADDR_ENDP15_ENDPOINT -// Description : Endpoint number of the interrupt endpoint -#define USB_ADDR_ENDP15_ENDPOINT_RESET _u(0x0) -#define USB_ADDR_ENDP15_ENDPOINT_BITS _u(0x000f0000) -#define USB_ADDR_ENDP15_ENDPOINT_MSB _u(19) -#define USB_ADDR_ENDP15_ENDPOINT_LSB _u(16) -#define USB_ADDR_ENDP15_ENDPOINT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_ADDR_ENDP15_ADDRESS -// Description : Device address -#define USB_ADDR_ENDP15_ADDRESS_RESET _u(0x00) -#define USB_ADDR_ENDP15_ADDRESS_BITS _u(0x0000007f) -#define USB_ADDR_ENDP15_ADDRESS_MSB _u(6) -#define USB_ADDR_ENDP15_ADDRESS_LSB _u(0) -#define USB_ADDR_ENDP15_ADDRESS_ACCESS "RW" -// ============================================================================= -// Register : USB_MAIN_CTRL -// Description : Main control register -#define USB_MAIN_CTRL_OFFSET _u(0x00000040) -#define USB_MAIN_CTRL_BITS _u(0x80000003) -#define USB_MAIN_CTRL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_MAIN_CTRL_SIM_TIMING -// Description : Reduced timings for simulation -#define USB_MAIN_CTRL_SIM_TIMING_RESET _u(0x0) -#define USB_MAIN_CTRL_SIM_TIMING_BITS _u(0x80000000) -#define USB_MAIN_CTRL_SIM_TIMING_MSB _u(31) -#define USB_MAIN_CTRL_SIM_TIMING_LSB _u(31) -#define USB_MAIN_CTRL_SIM_TIMING_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_MAIN_CTRL_HOST_NDEVICE -// Description : Device mode = 0, Host mode = 1 -#define USB_MAIN_CTRL_HOST_NDEVICE_RESET _u(0x0) -#define USB_MAIN_CTRL_HOST_NDEVICE_BITS _u(0x00000002) -#define USB_MAIN_CTRL_HOST_NDEVICE_MSB _u(1) -#define USB_MAIN_CTRL_HOST_NDEVICE_LSB _u(1) -#define USB_MAIN_CTRL_HOST_NDEVICE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_MAIN_CTRL_CONTROLLER_EN -// Description : Enable controller -#define USB_MAIN_CTRL_CONTROLLER_EN_RESET _u(0x0) -#define USB_MAIN_CTRL_CONTROLLER_EN_BITS _u(0x00000001) -#define USB_MAIN_CTRL_CONTROLLER_EN_MSB _u(0) -#define USB_MAIN_CTRL_CONTROLLER_EN_LSB _u(0) -#define USB_MAIN_CTRL_CONTROLLER_EN_ACCESS "RW" -// ============================================================================= -// Register : USB_SOF_WR -// Description : Set the SOF (Start of Frame) frame number in the host -// controller. The SOF packet is sent every 1ms and the host will -// increment the frame number by 1 each time. -#define USB_SOF_WR_OFFSET _u(0x00000044) -#define USB_SOF_WR_BITS _u(0x000007ff) -#define USB_SOF_WR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_SOF_WR_COUNT -#define USB_SOF_WR_COUNT_RESET _u(0x000) -#define USB_SOF_WR_COUNT_BITS _u(0x000007ff) -#define USB_SOF_WR_COUNT_MSB _u(10) -#define USB_SOF_WR_COUNT_LSB _u(0) -#define USB_SOF_WR_COUNT_ACCESS "WF" -// ============================================================================= -// Register : USB_SOF_RD -// Description : Read the last SOF (Start of Frame) frame number seen. In device -// mode the last SOF received from the host. In host mode the last -// SOF sent by the host. -#define USB_SOF_RD_OFFSET _u(0x00000048) -#define USB_SOF_RD_BITS _u(0x000007ff) -#define USB_SOF_RD_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_SOF_RD_COUNT -#define USB_SOF_RD_COUNT_RESET _u(0x000) -#define USB_SOF_RD_COUNT_BITS _u(0x000007ff) -#define USB_SOF_RD_COUNT_MSB _u(10) -#define USB_SOF_RD_COUNT_LSB _u(0) -#define USB_SOF_RD_COUNT_ACCESS "RO" -// ============================================================================= -// Register : USB_SIE_CTRL -// Description : SIE control register -#define USB_SIE_CTRL_OFFSET _u(0x0000004c) -#define USB_SIE_CTRL_BITS _u(0xff07bf5f) -#define USB_SIE_CTRL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_SIE_CTRL_EP0_INT_STALL -// Description : Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a STALL -#define USB_SIE_CTRL_EP0_INT_STALL_RESET _u(0x0) -#define USB_SIE_CTRL_EP0_INT_STALL_BITS _u(0x80000000) -#define USB_SIE_CTRL_EP0_INT_STALL_MSB _u(31) -#define USB_SIE_CTRL_EP0_INT_STALL_LSB _u(31) -#define USB_SIE_CTRL_EP0_INT_STALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_SIE_CTRL_EP0_DOUBLE_BUF -// Description : Device: EP0 single buffered = 0, double buffered = 1 -#define USB_SIE_CTRL_EP0_DOUBLE_BUF_RESET _u(0x0) -#define USB_SIE_CTRL_EP0_DOUBLE_BUF_BITS _u(0x40000000) -#define USB_SIE_CTRL_EP0_DOUBLE_BUF_MSB _u(30) -#define USB_SIE_CTRL_EP0_DOUBLE_BUF_LSB _u(30) -#define USB_SIE_CTRL_EP0_DOUBLE_BUF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_SIE_CTRL_EP0_INT_1BUF -// Description : Device: Set bit in BUFF_STATUS for every buffer completed on -// EP0 -#define USB_SIE_CTRL_EP0_INT_1BUF_RESET _u(0x0) -#define USB_SIE_CTRL_EP0_INT_1BUF_BITS _u(0x20000000) -#define USB_SIE_CTRL_EP0_INT_1BUF_MSB _u(29) -#define USB_SIE_CTRL_EP0_INT_1BUF_LSB _u(29) -#define USB_SIE_CTRL_EP0_INT_1BUF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_SIE_CTRL_EP0_INT_2BUF -// Description : Device: Set bit in BUFF_STATUS for every 2 buffers completed on -// EP0 -#define USB_SIE_CTRL_EP0_INT_2BUF_RESET _u(0x0) -#define USB_SIE_CTRL_EP0_INT_2BUF_BITS _u(0x10000000) -#define USB_SIE_CTRL_EP0_INT_2BUF_MSB _u(28) -#define USB_SIE_CTRL_EP0_INT_2BUF_LSB _u(28) -#define USB_SIE_CTRL_EP0_INT_2BUF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_SIE_CTRL_EP0_INT_NAK -// Description : Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a NAK -#define USB_SIE_CTRL_EP0_INT_NAK_RESET _u(0x0) -#define USB_SIE_CTRL_EP0_INT_NAK_BITS _u(0x08000000) -#define USB_SIE_CTRL_EP0_INT_NAK_MSB _u(27) -#define USB_SIE_CTRL_EP0_INT_NAK_LSB _u(27) -#define USB_SIE_CTRL_EP0_INT_NAK_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_SIE_CTRL_DIRECT_EN -// Description : Direct bus drive enable -#define USB_SIE_CTRL_DIRECT_EN_RESET _u(0x0) -#define USB_SIE_CTRL_DIRECT_EN_BITS _u(0x04000000) -#define USB_SIE_CTRL_DIRECT_EN_MSB _u(26) -#define USB_SIE_CTRL_DIRECT_EN_LSB _u(26) -#define USB_SIE_CTRL_DIRECT_EN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_SIE_CTRL_DIRECT_DP -// Description : Direct control of DP -#define USB_SIE_CTRL_DIRECT_DP_RESET _u(0x0) -#define USB_SIE_CTRL_DIRECT_DP_BITS _u(0x02000000) -#define USB_SIE_CTRL_DIRECT_DP_MSB _u(25) -#define USB_SIE_CTRL_DIRECT_DP_LSB _u(25) -#define USB_SIE_CTRL_DIRECT_DP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_SIE_CTRL_DIRECT_DM -// Description : Direct control of DM -#define USB_SIE_CTRL_DIRECT_DM_RESET _u(0x0) -#define USB_SIE_CTRL_DIRECT_DM_BITS _u(0x01000000) -#define USB_SIE_CTRL_DIRECT_DM_MSB _u(24) -#define USB_SIE_CTRL_DIRECT_DM_LSB _u(24) -#define USB_SIE_CTRL_DIRECT_DM_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_SIE_CTRL_TRANSCEIVER_PD -// Description : Power down bus transceiver -#define USB_SIE_CTRL_TRANSCEIVER_PD_RESET _u(0x0) -#define USB_SIE_CTRL_TRANSCEIVER_PD_BITS _u(0x00040000) -#define USB_SIE_CTRL_TRANSCEIVER_PD_MSB _u(18) -#define USB_SIE_CTRL_TRANSCEIVER_PD_LSB _u(18) -#define USB_SIE_CTRL_TRANSCEIVER_PD_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_SIE_CTRL_RPU_OPT -// Description : Device: Pull-up strength (0=1K2, 1=2k3) -#define USB_SIE_CTRL_RPU_OPT_RESET _u(0x0) -#define USB_SIE_CTRL_RPU_OPT_BITS _u(0x00020000) -#define USB_SIE_CTRL_RPU_OPT_MSB _u(17) -#define USB_SIE_CTRL_RPU_OPT_LSB _u(17) -#define USB_SIE_CTRL_RPU_OPT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_SIE_CTRL_PULLUP_EN -// Description : Device: Enable pull up resistor -#define USB_SIE_CTRL_PULLUP_EN_RESET _u(0x0) -#define USB_SIE_CTRL_PULLUP_EN_BITS _u(0x00010000) -#define USB_SIE_CTRL_PULLUP_EN_MSB _u(16) -#define USB_SIE_CTRL_PULLUP_EN_LSB _u(16) -#define USB_SIE_CTRL_PULLUP_EN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_SIE_CTRL_PULLDOWN_EN -// Description : Host: Enable pull down resistors -#define USB_SIE_CTRL_PULLDOWN_EN_RESET _u(0x0) -#define USB_SIE_CTRL_PULLDOWN_EN_BITS _u(0x00008000) -#define USB_SIE_CTRL_PULLDOWN_EN_MSB _u(15) -#define USB_SIE_CTRL_PULLDOWN_EN_LSB _u(15) -#define USB_SIE_CTRL_PULLDOWN_EN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_SIE_CTRL_RESET_BUS -// Description : Host: Reset bus -#define USB_SIE_CTRL_RESET_BUS_RESET _u(0x0) -#define USB_SIE_CTRL_RESET_BUS_BITS _u(0x00002000) -#define USB_SIE_CTRL_RESET_BUS_MSB _u(13) -#define USB_SIE_CTRL_RESET_BUS_LSB _u(13) -#define USB_SIE_CTRL_RESET_BUS_ACCESS "SC" -// ----------------------------------------------------------------------------- -// Field : USB_SIE_CTRL_RESUME -// Description : Device: Remote wakeup. Device can initiate its own resume after -// suspend. -#define USB_SIE_CTRL_RESUME_RESET _u(0x0) -#define USB_SIE_CTRL_RESUME_BITS _u(0x00001000) -#define USB_SIE_CTRL_RESUME_MSB _u(12) -#define USB_SIE_CTRL_RESUME_LSB _u(12) -#define USB_SIE_CTRL_RESUME_ACCESS "SC" -// ----------------------------------------------------------------------------- -// Field : USB_SIE_CTRL_VBUS_EN -// Description : Host: Enable VBUS -#define USB_SIE_CTRL_VBUS_EN_RESET _u(0x0) -#define USB_SIE_CTRL_VBUS_EN_BITS _u(0x00000800) -#define USB_SIE_CTRL_VBUS_EN_MSB _u(11) -#define USB_SIE_CTRL_VBUS_EN_LSB _u(11) -#define USB_SIE_CTRL_VBUS_EN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_SIE_CTRL_KEEP_ALIVE_EN -// Description : Host: Enable keep alive packet (for low speed bus) -#define USB_SIE_CTRL_KEEP_ALIVE_EN_RESET _u(0x0) -#define USB_SIE_CTRL_KEEP_ALIVE_EN_BITS _u(0x00000400) -#define USB_SIE_CTRL_KEEP_ALIVE_EN_MSB _u(10) -#define USB_SIE_CTRL_KEEP_ALIVE_EN_LSB _u(10) -#define USB_SIE_CTRL_KEEP_ALIVE_EN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_SIE_CTRL_SOF_EN -// Description : Host: Enable SOF generation (for full speed bus) -#define USB_SIE_CTRL_SOF_EN_RESET _u(0x0) -#define USB_SIE_CTRL_SOF_EN_BITS _u(0x00000200) -#define USB_SIE_CTRL_SOF_EN_MSB _u(9) -#define USB_SIE_CTRL_SOF_EN_LSB _u(9) -#define USB_SIE_CTRL_SOF_EN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_SIE_CTRL_SOF_SYNC -// Description : Host: Delay packet(s) until after SOF -#define USB_SIE_CTRL_SOF_SYNC_RESET _u(0x0) -#define USB_SIE_CTRL_SOF_SYNC_BITS _u(0x00000100) -#define USB_SIE_CTRL_SOF_SYNC_MSB _u(8) -#define USB_SIE_CTRL_SOF_SYNC_LSB _u(8) -#define USB_SIE_CTRL_SOF_SYNC_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_SIE_CTRL_PREAMBLE_EN -// Description : Host: Preable enable for LS device on FS hub -#define USB_SIE_CTRL_PREAMBLE_EN_RESET _u(0x0) -#define USB_SIE_CTRL_PREAMBLE_EN_BITS _u(0x00000040) -#define USB_SIE_CTRL_PREAMBLE_EN_MSB _u(6) -#define USB_SIE_CTRL_PREAMBLE_EN_LSB _u(6) -#define USB_SIE_CTRL_PREAMBLE_EN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_SIE_CTRL_STOP_TRANS -// Description : Host: Stop transaction -#define USB_SIE_CTRL_STOP_TRANS_RESET _u(0x0) -#define USB_SIE_CTRL_STOP_TRANS_BITS _u(0x00000010) -#define USB_SIE_CTRL_STOP_TRANS_MSB _u(4) -#define USB_SIE_CTRL_STOP_TRANS_LSB _u(4) -#define USB_SIE_CTRL_STOP_TRANS_ACCESS "SC" -// ----------------------------------------------------------------------------- -// Field : USB_SIE_CTRL_RECEIVE_DATA -// Description : Host: Receive transaction (IN to host) -#define USB_SIE_CTRL_RECEIVE_DATA_RESET _u(0x0) -#define USB_SIE_CTRL_RECEIVE_DATA_BITS _u(0x00000008) -#define USB_SIE_CTRL_RECEIVE_DATA_MSB _u(3) -#define USB_SIE_CTRL_RECEIVE_DATA_LSB _u(3) -#define USB_SIE_CTRL_RECEIVE_DATA_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_SIE_CTRL_SEND_DATA -// Description : Host: Send transaction (OUT from host) -#define USB_SIE_CTRL_SEND_DATA_RESET _u(0x0) -#define USB_SIE_CTRL_SEND_DATA_BITS _u(0x00000004) -#define USB_SIE_CTRL_SEND_DATA_MSB _u(2) -#define USB_SIE_CTRL_SEND_DATA_LSB _u(2) -#define USB_SIE_CTRL_SEND_DATA_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_SIE_CTRL_SEND_SETUP -// Description : Host: Send Setup packet -#define USB_SIE_CTRL_SEND_SETUP_RESET _u(0x0) -#define USB_SIE_CTRL_SEND_SETUP_BITS _u(0x00000002) -#define USB_SIE_CTRL_SEND_SETUP_MSB _u(1) -#define USB_SIE_CTRL_SEND_SETUP_LSB _u(1) -#define USB_SIE_CTRL_SEND_SETUP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_SIE_CTRL_START_TRANS -// Description : Host: Start transaction -#define USB_SIE_CTRL_START_TRANS_RESET _u(0x0) -#define USB_SIE_CTRL_START_TRANS_BITS _u(0x00000001) -#define USB_SIE_CTRL_START_TRANS_MSB _u(0) -#define USB_SIE_CTRL_START_TRANS_LSB _u(0) -#define USB_SIE_CTRL_START_TRANS_ACCESS "SC" -// ============================================================================= -// Register : USB_SIE_STATUS -// Description : SIE status register -#define USB_SIE_STATUS_OFFSET _u(0x00000050) -#define USB_SIE_STATUS_BITS _u(0xff0f0f1d) -#define USB_SIE_STATUS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_SIE_STATUS_DATA_SEQ_ERROR -// Description : Data Sequence Error. -// -// The device can raise a sequence error in the following -// conditions: -// -// * A SETUP packet is received followed by a DATA1 packet (data -// phase should always be DATA0) * An OUT packet is received from -// the host but doesn't match the data pid in the buffer control -// register read from DPSRAM -// -// The host can raise a data sequence error in the following -// conditions: -// -// * An IN packet from the device has the wrong data PID -#define USB_SIE_STATUS_DATA_SEQ_ERROR_RESET _u(0x0) -#define USB_SIE_STATUS_DATA_SEQ_ERROR_BITS _u(0x80000000) -#define USB_SIE_STATUS_DATA_SEQ_ERROR_MSB _u(31) -#define USB_SIE_STATUS_DATA_SEQ_ERROR_LSB _u(31) -#define USB_SIE_STATUS_DATA_SEQ_ERROR_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_SIE_STATUS_ACK_REC -// Description : ACK received. Raised by both host and device. -#define USB_SIE_STATUS_ACK_REC_RESET _u(0x0) -#define USB_SIE_STATUS_ACK_REC_BITS _u(0x40000000) -#define USB_SIE_STATUS_ACK_REC_MSB _u(30) -#define USB_SIE_STATUS_ACK_REC_LSB _u(30) -#define USB_SIE_STATUS_ACK_REC_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_SIE_STATUS_STALL_REC -// Description : Host: STALL received -#define USB_SIE_STATUS_STALL_REC_RESET _u(0x0) -#define USB_SIE_STATUS_STALL_REC_BITS _u(0x20000000) -#define USB_SIE_STATUS_STALL_REC_MSB _u(29) -#define USB_SIE_STATUS_STALL_REC_LSB _u(29) -#define USB_SIE_STATUS_STALL_REC_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_SIE_STATUS_NAK_REC -// Description : Host: NAK received -#define USB_SIE_STATUS_NAK_REC_RESET _u(0x0) -#define USB_SIE_STATUS_NAK_REC_BITS _u(0x10000000) -#define USB_SIE_STATUS_NAK_REC_MSB _u(28) -#define USB_SIE_STATUS_NAK_REC_LSB _u(28) -#define USB_SIE_STATUS_NAK_REC_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_SIE_STATUS_RX_TIMEOUT -// Description : RX timeout is raised by both the host and device if an ACK is -// not received in the maximum time specified by the USB spec. -#define USB_SIE_STATUS_RX_TIMEOUT_RESET _u(0x0) -#define USB_SIE_STATUS_RX_TIMEOUT_BITS _u(0x08000000) -#define USB_SIE_STATUS_RX_TIMEOUT_MSB _u(27) -#define USB_SIE_STATUS_RX_TIMEOUT_LSB _u(27) -#define USB_SIE_STATUS_RX_TIMEOUT_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_SIE_STATUS_RX_OVERFLOW -// Description : RX overflow is raised by the Serial RX engine if the incoming -// data is too fast. -#define USB_SIE_STATUS_RX_OVERFLOW_RESET _u(0x0) -#define USB_SIE_STATUS_RX_OVERFLOW_BITS _u(0x04000000) -#define USB_SIE_STATUS_RX_OVERFLOW_MSB _u(26) -#define USB_SIE_STATUS_RX_OVERFLOW_LSB _u(26) -#define USB_SIE_STATUS_RX_OVERFLOW_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_SIE_STATUS_BIT_STUFF_ERROR -// Description : Bit Stuff Error. Raised by the Serial RX engine. -#define USB_SIE_STATUS_BIT_STUFF_ERROR_RESET _u(0x0) -#define USB_SIE_STATUS_BIT_STUFF_ERROR_BITS _u(0x02000000) -#define USB_SIE_STATUS_BIT_STUFF_ERROR_MSB _u(25) -#define USB_SIE_STATUS_BIT_STUFF_ERROR_LSB _u(25) -#define USB_SIE_STATUS_BIT_STUFF_ERROR_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_SIE_STATUS_CRC_ERROR -// Description : CRC Error. Raised by the Serial RX engine. -#define USB_SIE_STATUS_CRC_ERROR_RESET _u(0x0) -#define USB_SIE_STATUS_CRC_ERROR_BITS _u(0x01000000) -#define USB_SIE_STATUS_CRC_ERROR_MSB _u(24) -#define USB_SIE_STATUS_CRC_ERROR_LSB _u(24) -#define USB_SIE_STATUS_CRC_ERROR_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_SIE_STATUS_BUS_RESET -// Description : Device: bus reset received -#define USB_SIE_STATUS_BUS_RESET_RESET _u(0x0) -#define USB_SIE_STATUS_BUS_RESET_BITS _u(0x00080000) -#define USB_SIE_STATUS_BUS_RESET_MSB _u(19) -#define USB_SIE_STATUS_BUS_RESET_LSB _u(19) -#define USB_SIE_STATUS_BUS_RESET_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_SIE_STATUS_TRANS_COMPLETE -// Description : Transaction complete. -// -// Raised by device if: -// -// * An IN or OUT packet is sent with the `LAST_BUFF` bit set in -// the buffer control register -// -// Raised by host if: -// -// * A setup packet is sent when no data in or data out -// transaction follows * An IN packet is received and the -// `LAST_BUFF` bit is set in the buffer control register * An IN -// packet is received with zero length * An OUT packet is sent and -// the `LAST_BUFF` bit is set -#define USB_SIE_STATUS_TRANS_COMPLETE_RESET _u(0x0) -#define USB_SIE_STATUS_TRANS_COMPLETE_BITS _u(0x00040000) -#define USB_SIE_STATUS_TRANS_COMPLETE_MSB _u(18) -#define USB_SIE_STATUS_TRANS_COMPLETE_LSB _u(18) -#define USB_SIE_STATUS_TRANS_COMPLETE_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_SIE_STATUS_SETUP_REC -// Description : Device: Setup packet received -#define USB_SIE_STATUS_SETUP_REC_RESET _u(0x0) -#define USB_SIE_STATUS_SETUP_REC_BITS _u(0x00020000) -#define USB_SIE_STATUS_SETUP_REC_MSB _u(17) -#define USB_SIE_STATUS_SETUP_REC_LSB _u(17) -#define USB_SIE_STATUS_SETUP_REC_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_SIE_STATUS_CONNECTED -// Description : Device: connected -#define USB_SIE_STATUS_CONNECTED_RESET _u(0x0) -#define USB_SIE_STATUS_CONNECTED_BITS _u(0x00010000) -#define USB_SIE_STATUS_CONNECTED_MSB _u(16) -#define USB_SIE_STATUS_CONNECTED_LSB _u(16) -#define USB_SIE_STATUS_CONNECTED_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_SIE_STATUS_RESUME -// Description : Host: Device has initiated a remote resume. Device: host has -// initiated a resume. -#define USB_SIE_STATUS_RESUME_RESET _u(0x0) -#define USB_SIE_STATUS_RESUME_BITS _u(0x00000800) -#define USB_SIE_STATUS_RESUME_MSB _u(11) -#define USB_SIE_STATUS_RESUME_LSB _u(11) -#define USB_SIE_STATUS_RESUME_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_SIE_STATUS_VBUS_OVER_CURR -// Description : VBUS over current detected -#define USB_SIE_STATUS_VBUS_OVER_CURR_RESET _u(0x0) -#define USB_SIE_STATUS_VBUS_OVER_CURR_BITS _u(0x00000400) -#define USB_SIE_STATUS_VBUS_OVER_CURR_MSB _u(10) -#define USB_SIE_STATUS_VBUS_OVER_CURR_LSB _u(10) -#define USB_SIE_STATUS_VBUS_OVER_CURR_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_SIE_STATUS_SPEED -// Description : Host: device speed. Disconnected = 00, LS = 01, FS = 10 -#define USB_SIE_STATUS_SPEED_RESET _u(0x0) -#define USB_SIE_STATUS_SPEED_BITS _u(0x00000300) -#define USB_SIE_STATUS_SPEED_MSB _u(9) -#define USB_SIE_STATUS_SPEED_LSB _u(8) -#define USB_SIE_STATUS_SPEED_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_SIE_STATUS_SUSPENDED -// Description : Bus in suspended state. Valid for device and host. Host and -// device will go into suspend if neither Keep Alive / SOF frames -// are enabled. -#define USB_SIE_STATUS_SUSPENDED_RESET _u(0x0) -#define USB_SIE_STATUS_SUSPENDED_BITS _u(0x00000010) -#define USB_SIE_STATUS_SUSPENDED_MSB _u(4) -#define USB_SIE_STATUS_SUSPENDED_LSB _u(4) -#define USB_SIE_STATUS_SUSPENDED_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_SIE_STATUS_LINE_STATE -// Description : USB bus line state -#define USB_SIE_STATUS_LINE_STATE_RESET _u(0x0) -#define USB_SIE_STATUS_LINE_STATE_BITS _u(0x0000000c) -#define USB_SIE_STATUS_LINE_STATE_MSB _u(3) -#define USB_SIE_STATUS_LINE_STATE_LSB _u(2) -#define USB_SIE_STATUS_LINE_STATE_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_SIE_STATUS_VBUS_DETECTED -// Description : Device: VBUS Detected -#define USB_SIE_STATUS_VBUS_DETECTED_RESET _u(0x0) -#define USB_SIE_STATUS_VBUS_DETECTED_BITS _u(0x00000001) -#define USB_SIE_STATUS_VBUS_DETECTED_MSB _u(0) -#define USB_SIE_STATUS_VBUS_DETECTED_LSB _u(0) -#define USB_SIE_STATUS_VBUS_DETECTED_ACCESS "RO" -// ============================================================================= -// Register : USB_INT_EP_CTRL -// Description : interrupt endpoint control register -#define USB_INT_EP_CTRL_OFFSET _u(0x00000054) -#define USB_INT_EP_CTRL_BITS _u(0x0000fffe) -#define USB_INT_EP_CTRL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_INT_EP_CTRL_INT_EP_ACTIVE -// Description : Host: Enable interrupt endpoint 1 => 15 -#define USB_INT_EP_CTRL_INT_EP_ACTIVE_RESET _u(0x0000) -#define USB_INT_EP_CTRL_INT_EP_ACTIVE_BITS _u(0x0000fffe) -#define USB_INT_EP_CTRL_INT_EP_ACTIVE_MSB _u(15) -#define USB_INT_EP_CTRL_INT_EP_ACTIVE_LSB _u(1) -#define USB_INT_EP_CTRL_INT_EP_ACTIVE_ACCESS "RW" -// ============================================================================= -// Register : USB_BUFF_STATUS -// Description : Buffer status register. A bit set here indicates that a buffer -// has completed on the endpoint (if the buffer interrupt is -// enabled). It is possible for 2 buffers to be completed, so -// clearing the buffer status bit may instantly re set it on the -// next clock cycle. -#define USB_BUFF_STATUS_OFFSET _u(0x00000058) -#define USB_BUFF_STATUS_BITS _u(0xffffffff) -#define USB_BUFF_STATUS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_BUFF_STATUS_EP15_OUT -#define USB_BUFF_STATUS_EP15_OUT_RESET _u(0x0) -#define USB_BUFF_STATUS_EP15_OUT_BITS _u(0x80000000) -#define USB_BUFF_STATUS_EP15_OUT_MSB _u(31) -#define USB_BUFF_STATUS_EP15_OUT_LSB _u(31) -#define USB_BUFF_STATUS_EP15_OUT_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_BUFF_STATUS_EP15_IN -#define USB_BUFF_STATUS_EP15_IN_RESET _u(0x0) -#define USB_BUFF_STATUS_EP15_IN_BITS _u(0x40000000) -#define USB_BUFF_STATUS_EP15_IN_MSB _u(30) -#define USB_BUFF_STATUS_EP15_IN_LSB _u(30) -#define USB_BUFF_STATUS_EP15_IN_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_BUFF_STATUS_EP14_OUT -#define USB_BUFF_STATUS_EP14_OUT_RESET _u(0x0) -#define USB_BUFF_STATUS_EP14_OUT_BITS _u(0x20000000) -#define USB_BUFF_STATUS_EP14_OUT_MSB _u(29) -#define USB_BUFF_STATUS_EP14_OUT_LSB _u(29) -#define USB_BUFF_STATUS_EP14_OUT_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_BUFF_STATUS_EP14_IN -#define USB_BUFF_STATUS_EP14_IN_RESET _u(0x0) -#define USB_BUFF_STATUS_EP14_IN_BITS _u(0x10000000) -#define USB_BUFF_STATUS_EP14_IN_MSB _u(28) -#define USB_BUFF_STATUS_EP14_IN_LSB _u(28) -#define USB_BUFF_STATUS_EP14_IN_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_BUFF_STATUS_EP13_OUT -#define USB_BUFF_STATUS_EP13_OUT_RESET _u(0x0) -#define USB_BUFF_STATUS_EP13_OUT_BITS _u(0x08000000) -#define USB_BUFF_STATUS_EP13_OUT_MSB _u(27) -#define USB_BUFF_STATUS_EP13_OUT_LSB _u(27) -#define USB_BUFF_STATUS_EP13_OUT_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_BUFF_STATUS_EP13_IN -#define USB_BUFF_STATUS_EP13_IN_RESET _u(0x0) -#define USB_BUFF_STATUS_EP13_IN_BITS _u(0x04000000) -#define USB_BUFF_STATUS_EP13_IN_MSB _u(26) -#define USB_BUFF_STATUS_EP13_IN_LSB _u(26) -#define USB_BUFF_STATUS_EP13_IN_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_BUFF_STATUS_EP12_OUT -#define USB_BUFF_STATUS_EP12_OUT_RESET _u(0x0) -#define USB_BUFF_STATUS_EP12_OUT_BITS _u(0x02000000) -#define USB_BUFF_STATUS_EP12_OUT_MSB _u(25) -#define USB_BUFF_STATUS_EP12_OUT_LSB _u(25) -#define USB_BUFF_STATUS_EP12_OUT_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_BUFF_STATUS_EP12_IN -#define USB_BUFF_STATUS_EP12_IN_RESET _u(0x0) -#define USB_BUFF_STATUS_EP12_IN_BITS _u(0x01000000) -#define USB_BUFF_STATUS_EP12_IN_MSB _u(24) -#define USB_BUFF_STATUS_EP12_IN_LSB _u(24) -#define USB_BUFF_STATUS_EP12_IN_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_BUFF_STATUS_EP11_OUT -#define USB_BUFF_STATUS_EP11_OUT_RESET _u(0x0) -#define USB_BUFF_STATUS_EP11_OUT_BITS _u(0x00800000) -#define USB_BUFF_STATUS_EP11_OUT_MSB _u(23) -#define USB_BUFF_STATUS_EP11_OUT_LSB _u(23) -#define USB_BUFF_STATUS_EP11_OUT_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_BUFF_STATUS_EP11_IN -#define USB_BUFF_STATUS_EP11_IN_RESET _u(0x0) -#define USB_BUFF_STATUS_EP11_IN_BITS _u(0x00400000) -#define USB_BUFF_STATUS_EP11_IN_MSB _u(22) -#define USB_BUFF_STATUS_EP11_IN_LSB _u(22) -#define USB_BUFF_STATUS_EP11_IN_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_BUFF_STATUS_EP10_OUT -#define USB_BUFF_STATUS_EP10_OUT_RESET _u(0x0) -#define USB_BUFF_STATUS_EP10_OUT_BITS _u(0x00200000) -#define USB_BUFF_STATUS_EP10_OUT_MSB _u(21) -#define USB_BUFF_STATUS_EP10_OUT_LSB _u(21) -#define USB_BUFF_STATUS_EP10_OUT_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_BUFF_STATUS_EP10_IN -#define USB_BUFF_STATUS_EP10_IN_RESET _u(0x0) -#define USB_BUFF_STATUS_EP10_IN_BITS _u(0x00100000) -#define USB_BUFF_STATUS_EP10_IN_MSB _u(20) -#define USB_BUFF_STATUS_EP10_IN_LSB _u(20) -#define USB_BUFF_STATUS_EP10_IN_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_BUFF_STATUS_EP9_OUT -#define USB_BUFF_STATUS_EP9_OUT_RESET _u(0x0) -#define USB_BUFF_STATUS_EP9_OUT_BITS _u(0x00080000) -#define USB_BUFF_STATUS_EP9_OUT_MSB _u(19) -#define USB_BUFF_STATUS_EP9_OUT_LSB _u(19) -#define USB_BUFF_STATUS_EP9_OUT_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_BUFF_STATUS_EP9_IN -#define USB_BUFF_STATUS_EP9_IN_RESET _u(0x0) -#define USB_BUFF_STATUS_EP9_IN_BITS _u(0x00040000) -#define USB_BUFF_STATUS_EP9_IN_MSB _u(18) -#define USB_BUFF_STATUS_EP9_IN_LSB _u(18) -#define USB_BUFF_STATUS_EP9_IN_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_BUFF_STATUS_EP8_OUT -#define USB_BUFF_STATUS_EP8_OUT_RESET _u(0x0) -#define USB_BUFF_STATUS_EP8_OUT_BITS _u(0x00020000) -#define USB_BUFF_STATUS_EP8_OUT_MSB _u(17) -#define USB_BUFF_STATUS_EP8_OUT_LSB _u(17) -#define USB_BUFF_STATUS_EP8_OUT_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_BUFF_STATUS_EP8_IN -#define USB_BUFF_STATUS_EP8_IN_RESET _u(0x0) -#define USB_BUFF_STATUS_EP8_IN_BITS _u(0x00010000) -#define USB_BUFF_STATUS_EP8_IN_MSB _u(16) -#define USB_BUFF_STATUS_EP8_IN_LSB _u(16) -#define USB_BUFF_STATUS_EP8_IN_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_BUFF_STATUS_EP7_OUT -#define USB_BUFF_STATUS_EP7_OUT_RESET _u(0x0) -#define USB_BUFF_STATUS_EP7_OUT_BITS _u(0x00008000) -#define USB_BUFF_STATUS_EP7_OUT_MSB _u(15) -#define USB_BUFF_STATUS_EP7_OUT_LSB _u(15) -#define USB_BUFF_STATUS_EP7_OUT_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_BUFF_STATUS_EP7_IN -#define USB_BUFF_STATUS_EP7_IN_RESET _u(0x0) -#define USB_BUFF_STATUS_EP7_IN_BITS _u(0x00004000) -#define USB_BUFF_STATUS_EP7_IN_MSB _u(14) -#define USB_BUFF_STATUS_EP7_IN_LSB _u(14) -#define USB_BUFF_STATUS_EP7_IN_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_BUFF_STATUS_EP6_OUT -#define USB_BUFF_STATUS_EP6_OUT_RESET _u(0x0) -#define USB_BUFF_STATUS_EP6_OUT_BITS _u(0x00002000) -#define USB_BUFF_STATUS_EP6_OUT_MSB _u(13) -#define USB_BUFF_STATUS_EP6_OUT_LSB _u(13) -#define USB_BUFF_STATUS_EP6_OUT_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_BUFF_STATUS_EP6_IN -#define USB_BUFF_STATUS_EP6_IN_RESET _u(0x0) -#define USB_BUFF_STATUS_EP6_IN_BITS _u(0x00001000) -#define USB_BUFF_STATUS_EP6_IN_MSB _u(12) -#define USB_BUFF_STATUS_EP6_IN_LSB _u(12) -#define USB_BUFF_STATUS_EP6_IN_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_BUFF_STATUS_EP5_OUT -#define USB_BUFF_STATUS_EP5_OUT_RESET _u(0x0) -#define USB_BUFF_STATUS_EP5_OUT_BITS _u(0x00000800) -#define USB_BUFF_STATUS_EP5_OUT_MSB _u(11) -#define USB_BUFF_STATUS_EP5_OUT_LSB _u(11) -#define USB_BUFF_STATUS_EP5_OUT_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_BUFF_STATUS_EP5_IN -#define USB_BUFF_STATUS_EP5_IN_RESET _u(0x0) -#define USB_BUFF_STATUS_EP5_IN_BITS _u(0x00000400) -#define USB_BUFF_STATUS_EP5_IN_MSB _u(10) -#define USB_BUFF_STATUS_EP5_IN_LSB _u(10) -#define USB_BUFF_STATUS_EP5_IN_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_BUFF_STATUS_EP4_OUT -#define USB_BUFF_STATUS_EP4_OUT_RESET _u(0x0) -#define USB_BUFF_STATUS_EP4_OUT_BITS _u(0x00000200) -#define USB_BUFF_STATUS_EP4_OUT_MSB _u(9) -#define USB_BUFF_STATUS_EP4_OUT_LSB _u(9) -#define USB_BUFF_STATUS_EP4_OUT_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_BUFF_STATUS_EP4_IN -#define USB_BUFF_STATUS_EP4_IN_RESET _u(0x0) -#define USB_BUFF_STATUS_EP4_IN_BITS _u(0x00000100) -#define USB_BUFF_STATUS_EP4_IN_MSB _u(8) -#define USB_BUFF_STATUS_EP4_IN_LSB _u(8) -#define USB_BUFF_STATUS_EP4_IN_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_BUFF_STATUS_EP3_OUT -#define USB_BUFF_STATUS_EP3_OUT_RESET _u(0x0) -#define USB_BUFF_STATUS_EP3_OUT_BITS _u(0x00000080) -#define USB_BUFF_STATUS_EP3_OUT_MSB _u(7) -#define USB_BUFF_STATUS_EP3_OUT_LSB _u(7) -#define USB_BUFF_STATUS_EP3_OUT_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_BUFF_STATUS_EP3_IN -#define USB_BUFF_STATUS_EP3_IN_RESET _u(0x0) -#define USB_BUFF_STATUS_EP3_IN_BITS _u(0x00000040) -#define USB_BUFF_STATUS_EP3_IN_MSB _u(6) -#define USB_BUFF_STATUS_EP3_IN_LSB _u(6) -#define USB_BUFF_STATUS_EP3_IN_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_BUFF_STATUS_EP2_OUT -#define USB_BUFF_STATUS_EP2_OUT_RESET _u(0x0) -#define USB_BUFF_STATUS_EP2_OUT_BITS _u(0x00000020) -#define USB_BUFF_STATUS_EP2_OUT_MSB _u(5) -#define USB_BUFF_STATUS_EP2_OUT_LSB _u(5) -#define USB_BUFF_STATUS_EP2_OUT_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_BUFF_STATUS_EP2_IN -#define USB_BUFF_STATUS_EP2_IN_RESET _u(0x0) -#define USB_BUFF_STATUS_EP2_IN_BITS _u(0x00000010) -#define USB_BUFF_STATUS_EP2_IN_MSB _u(4) -#define USB_BUFF_STATUS_EP2_IN_LSB _u(4) -#define USB_BUFF_STATUS_EP2_IN_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_BUFF_STATUS_EP1_OUT -#define USB_BUFF_STATUS_EP1_OUT_RESET _u(0x0) -#define USB_BUFF_STATUS_EP1_OUT_BITS _u(0x00000008) -#define USB_BUFF_STATUS_EP1_OUT_MSB _u(3) -#define USB_BUFF_STATUS_EP1_OUT_LSB _u(3) -#define USB_BUFF_STATUS_EP1_OUT_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_BUFF_STATUS_EP1_IN -#define USB_BUFF_STATUS_EP1_IN_RESET _u(0x0) -#define USB_BUFF_STATUS_EP1_IN_BITS _u(0x00000004) -#define USB_BUFF_STATUS_EP1_IN_MSB _u(2) -#define USB_BUFF_STATUS_EP1_IN_LSB _u(2) -#define USB_BUFF_STATUS_EP1_IN_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_BUFF_STATUS_EP0_OUT -#define USB_BUFF_STATUS_EP0_OUT_RESET _u(0x0) -#define USB_BUFF_STATUS_EP0_OUT_BITS _u(0x00000002) -#define USB_BUFF_STATUS_EP0_OUT_MSB _u(1) -#define USB_BUFF_STATUS_EP0_OUT_LSB _u(1) -#define USB_BUFF_STATUS_EP0_OUT_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_BUFF_STATUS_EP0_IN -#define USB_BUFF_STATUS_EP0_IN_RESET _u(0x0) -#define USB_BUFF_STATUS_EP0_IN_BITS _u(0x00000001) -#define USB_BUFF_STATUS_EP0_IN_MSB _u(0) -#define USB_BUFF_STATUS_EP0_IN_LSB _u(0) -#define USB_BUFF_STATUS_EP0_IN_ACCESS "WC" -// ============================================================================= -// Register : USB_BUFF_CPU_SHOULD_HANDLE -// Description : Which of the double buffers should be handled. Only valid if -// using an interrupt per buffer (i.e. not per 2 buffers). Not -// valid for host interrupt endpoint polling because they are only -// single buffered. -#define USB_BUFF_CPU_SHOULD_HANDLE_OFFSET _u(0x0000005c) -#define USB_BUFF_CPU_SHOULD_HANDLE_BITS _u(0xffffffff) -#define USB_BUFF_CPU_SHOULD_HANDLE_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP15_OUT -#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_OUT_RESET _u(0x0) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_OUT_BITS _u(0x80000000) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_OUT_MSB _u(31) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_OUT_LSB _u(31) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_OUT_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP15_IN -#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_IN_RESET _u(0x0) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_IN_BITS _u(0x40000000) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_IN_MSB _u(30) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_IN_LSB _u(30) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_IN_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP14_OUT -#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_OUT_RESET _u(0x0) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_OUT_BITS _u(0x20000000) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_OUT_MSB _u(29) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_OUT_LSB _u(29) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_OUT_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP14_IN -#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_IN_RESET _u(0x0) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_IN_BITS _u(0x10000000) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_IN_MSB _u(28) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_IN_LSB _u(28) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_IN_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP13_OUT -#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_OUT_RESET _u(0x0) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_OUT_BITS _u(0x08000000) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_OUT_MSB _u(27) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_OUT_LSB _u(27) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_OUT_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP13_IN -#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_IN_RESET _u(0x0) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_IN_BITS _u(0x04000000) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_IN_MSB _u(26) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_IN_LSB _u(26) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_IN_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP12_OUT -#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_OUT_RESET _u(0x0) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_OUT_BITS _u(0x02000000) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_OUT_MSB _u(25) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_OUT_LSB _u(25) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_OUT_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP12_IN -#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_IN_RESET _u(0x0) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_IN_BITS _u(0x01000000) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_IN_MSB _u(24) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_IN_LSB _u(24) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_IN_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP11_OUT -#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_OUT_RESET _u(0x0) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_OUT_BITS _u(0x00800000) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_OUT_MSB _u(23) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_OUT_LSB _u(23) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_OUT_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP11_IN -#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_IN_RESET _u(0x0) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_IN_BITS _u(0x00400000) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_IN_MSB _u(22) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_IN_LSB _u(22) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_IN_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP10_OUT -#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_OUT_RESET _u(0x0) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_OUT_BITS _u(0x00200000) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_OUT_MSB _u(21) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_OUT_LSB _u(21) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_OUT_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP10_IN -#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_IN_RESET _u(0x0) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_IN_BITS _u(0x00100000) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_IN_MSB _u(20) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_IN_LSB _u(20) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_IN_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP9_OUT -#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_OUT_RESET _u(0x0) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_OUT_BITS _u(0x00080000) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_OUT_MSB _u(19) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_OUT_LSB _u(19) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_OUT_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP9_IN -#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_IN_RESET _u(0x0) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_IN_BITS _u(0x00040000) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_IN_MSB _u(18) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_IN_LSB _u(18) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_IN_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP8_OUT -#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_OUT_RESET _u(0x0) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_OUT_BITS _u(0x00020000) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_OUT_MSB _u(17) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_OUT_LSB _u(17) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_OUT_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP8_IN -#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_IN_RESET _u(0x0) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_IN_BITS _u(0x00010000) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_IN_MSB _u(16) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_IN_LSB _u(16) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_IN_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP7_OUT -#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_OUT_RESET _u(0x0) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_OUT_BITS _u(0x00008000) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_OUT_MSB _u(15) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_OUT_LSB _u(15) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_OUT_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP7_IN -#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_IN_RESET _u(0x0) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_IN_BITS _u(0x00004000) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_IN_MSB _u(14) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_IN_LSB _u(14) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_IN_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP6_OUT -#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_OUT_RESET _u(0x0) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_OUT_BITS _u(0x00002000) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_OUT_MSB _u(13) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_OUT_LSB _u(13) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_OUT_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP6_IN -#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_IN_RESET _u(0x0) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_IN_BITS _u(0x00001000) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_IN_MSB _u(12) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_IN_LSB _u(12) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_IN_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP5_OUT -#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_OUT_RESET _u(0x0) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_OUT_BITS _u(0x00000800) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_OUT_MSB _u(11) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_OUT_LSB _u(11) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_OUT_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP5_IN -#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_IN_RESET _u(0x0) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_IN_BITS _u(0x00000400) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_IN_MSB _u(10) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_IN_LSB _u(10) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_IN_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP4_OUT -#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_OUT_RESET _u(0x0) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_OUT_BITS _u(0x00000200) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_OUT_MSB _u(9) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_OUT_LSB _u(9) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_OUT_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP4_IN -#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_IN_RESET _u(0x0) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_IN_BITS _u(0x00000100) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_IN_MSB _u(8) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_IN_LSB _u(8) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_IN_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP3_OUT -#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_OUT_RESET _u(0x0) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_OUT_BITS _u(0x00000080) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_OUT_MSB _u(7) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_OUT_LSB _u(7) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_OUT_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP3_IN -#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_IN_RESET _u(0x0) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_IN_BITS _u(0x00000040) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_IN_MSB _u(6) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_IN_LSB _u(6) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_IN_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP2_OUT -#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_OUT_RESET _u(0x0) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_OUT_BITS _u(0x00000020) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_OUT_MSB _u(5) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_OUT_LSB _u(5) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_OUT_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP2_IN -#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_IN_RESET _u(0x0) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_IN_BITS _u(0x00000010) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_IN_MSB _u(4) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_IN_LSB _u(4) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_IN_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP1_OUT -#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_OUT_RESET _u(0x0) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_OUT_BITS _u(0x00000008) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_OUT_MSB _u(3) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_OUT_LSB _u(3) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_OUT_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP1_IN -#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_IN_RESET _u(0x0) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_IN_BITS _u(0x00000004) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_IN_MSB _u(2) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_IN_LSB _u(2) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_IN_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP0_OUT -#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_OUT_RESET _u(0x0) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_OUT_BITS _u(0x00000002) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_OUT_MSB _u(1) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_OUT_LSB _u(1) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_OUT_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP0_IN -#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_IN_RESET _u(0x0) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_IN_BITS _u(0x00000001) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_IN_MSB _u(0) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_IN_LSB _u(0) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_IN_ACCESS "RO" -// ============================================================================= -// Register : USB_EP_ABORT -// Description : Device only: Can be set to ignore the buffer control register -// for this endpoint in case you would like to revoke a buffer. A -// NAK will be sent for every access to the endpoint until this -// bit is cleared. A corresponding bit in `EP_ABORT_DONE` is set -// when it is safe to modify the buffer control register. -#define USB_EP_ABORT_OFFSET _u(0x00000060) -#define USB_EP_ABORT_BITS _u(0xffffffff) -#define USB_EP_ABORT_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_EP_ABORT_EP15_OUT -#define USB_EP_ABORT_EP15_OUT_RESET _u(0x0) -#define USB_EP_ABORT_EP15_OUT_BITS _u(0x80000000) -#define USB_EP_ABORT_EP15_OUT_MSB _u(31) -#define USB_EP_ABORT_EP15_OUT_LSB _u(31) -#define USB_EP_ABORT_EP15_OUT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_EP_ABORT_EP15_IN -#define USB_EP_ABORT_EP15_IN_RESET _u(0x0) -#define USB_EP_ABORT_EP15_IN_BITS _u(0x40000000) -#define USB_EP_ABORT_EP15_IN_MSB _u(30) -#define USB_EP_ABORT_EP15_IN_LSB _u(30) -#define USB_EP_ABORT_EP15_IN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_EP_ABORT_EP14_OUT -#define USB_EP_ABORT_EP14_OUT_RESET _u(0x0) -#define USB_EP_ABORT_EP14_OUT_BITS _u(0x20000000) -#define USB_EP_ABORT_EP14_OUT_MSB _u(29) -#define USB_EP_ABORT_EP14_OUT_LSB _u(29) -#define USB_EP_ABORT_EP14_OUT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_EP_ABORT_EP14_IN -#define USB_EP_ABORT_EP14_IN_RESET _u(0x0) -#define USB_EP_ABORT_EP14_IN_BITS _u(0x10000000) -#define USB_EP_ABORT_EP14_IN_MSB _u(28) -#define USB_EP_ABORT_EP14_IN_LSB _u(28) -#define USB_EP_ABORT_EP14_IN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_EP_ABORT_EP13_OUT -#define USB_EP_ABORT_EP13_OUT_RESET _u(0x0) -#define USB_EP_ABORT_EP13_OUT_BITS _u(0x08000000) -#define USB_EP_ABORT_EP13_OUT_MSB _u(27) -#define USB_EP_ABORT_EP13_OUT_LSB _u(27) -#define USB_EP_ABORT_EP13_OUT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_EP_ABORT_EP13_IN -#define USB_EP_ABORT_EP13_IN_RESET _u(0x0) -#define USB_EP_ABORT_EP13_IN_BITS _u(0x04000000) -#define USB_EP_ABORT_EP13_IN_MSB _u(26) -#define USB_EP_ABORT_EP13_IN_LSB _u(26) -#define USB_EP_ABORT_EP13_IN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_EP_ABORT_EP12_OUT -#define USB_EP_ABORT_EP12_OUT_RESET _u(0x0) -#define USB_EP_ABORT_EP12_OUT_BITS _u(0x02000000) -#define USB_EP_ABORT_EP12_OUT_MSB _u(25) -#define USB_EP_ABORT_EP12_OUT_LSB _u(25) -#define USB_EP_ABORT_EP12_OUT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_EP_ABORT_EP12_IN -#define USB_EP_ABORT_EP12_IN_RESET _u(0x0) -#define USB_EP_ABORT_EP12_IN_BITS _u(0x01000000) -#define USB_EP_ABORT_EP12_IN_MSB _u(24) -#define USB_EP_ABORT_EP12_IN_LSB _u(24) -#define USB_EP_ABORT_EP12_IN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_EP_ABORT_EP11_OUT -#define USB_EP_ABORT_EP11_OUT_RESET _u(0x0) -#define USB_EP_ABORT_EP11_OUT_BITS _u(0x00800000) -#define USB_EP_ABORT_EP11_OUT_MSB _u(23) -#define USB_EP_ABORT_EP11_OUT_LSB _u(23) -#define USB_EP_ABORT_EP11_OUT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_EP_ABORT_EP11_IN -#define USB_EP_ABORT_EP11_IN_RESET _u(0x0) -#define USB_EP_ABORT_EP11_IN_BITS _u(0x00400000) -#define USB_EP_ABORT_EP11_IN_MSB _u(22) -#define USB_EP_ABORT_EP11_IN_LSB _u(22) -#define USB_EP_ABORT_EP11_IN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_EP_ABORT_EP10_OUT -#define USB_EP_ABORT_EP10_OUT_RESET _u(0x0) -#define USB_EP_ABORT_EP10_OUT_BITS _u(0x00200000) -#define USB_EP_ABORT_EP10_OUT_MSB _u(21) -#define USB_EP_ABORT_EP10_OUT_LSB _u(21) -#define USB_EP_ABORT_EP10_OUT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_EP_ABORT_EP10_IN -#define USB_EP_ABORT_EP10_IN_RESET _u(0x0) -#define USB_EP_ABORT_EP10_IN_BITS _u(0x00100000) -#define USB_EP_ABORT_EP10_IN_MSB _u(20) -#define USB_EP_ABORT_EP10_IN_LSB _u(20) -#define USB_EP_ABORT_EP10_IN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_EP_ABORT_EP9_OUT -#define USB_EP_ABORT_EP9_OUT_RESET _u(0x0) -#define USB_EP_ABORT_EP9_OUT_BITS _u(0x00080000) -#define USB_EP_ABORT_EP9_OUT_MSB _u(19) -#define USB_EP_ABORT_EP9_OUT_LSB _u(19) -#define USB_EP_ABORT_EP9_OUT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_EP_ABORT_EP9_IN -#define USB_EP_ABORT_EP9_IN_RESET _u(0x0) -#define USB_EP_ABORT_EP9_IN_BITS _u(0x00040000) -#define USB_EP_ABORT_EP9_IN_MSB _u(18) -#define USB_EP_ABORT_EP9_IN_LSB _u(18) -#define USB_EP_ABORT_EP9_IN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_EP_ABORT_EP8_OUT -#define USB_EP_ABORT_EP8_OUT_RESET _u(0x0) -#define USB_EP_ABORT_EP8_OUT_BITS _u(0x00020000) -#define USB_EP_ABORT_EP8_OUT_MSB _u(17) -#define USB_EP_ABORT_EP8_OUT_LSB _u(17) -#define USB_EP_ABORT_EP8_OUT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_EP_ABORT_EP8_IN -#define USB_EP_ABORT_EP8_IN_RESET _u(0x0) -#define USB_EP_ABORT_EP8_IN_BITS _u(0x00010000) -#define USB_EP_ABORT_EP8_IN_MSB _u(16) -#define USB_EP_ABORT_EP8_IN_LSB _u(16) -#define USB_EP_ABORT_EP8_IN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_EP_ABORT_EP7_OUT -#define USB_EP_ABORT_EP7_OUT_RESET _u(0x0) -#define USB_EP_ABORT_EP7_OUT_BITS _u(0x00008000) -#define USB_EP_ABORT_EP7_OUT_MSB _u(15) -#define USB_EP_ABORT_EP7_OUT_LSB _u(15) -#define USB_EP_ABORT_EP7_OUT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_EP_ABORT_EP7_IN -#define USB_EP_ABORT_EP7_IN_RESET _u(0x0) -#define USB_EP_ABORT_EP7_IN_BITS _u(0x00004000) -#define USB_EP_ABORT_EP7_IN_MSB _u(14) -#define USB_EP_ABORT_EP7_IN_LSB _u(14) -#define USB_EP_ABORT_EP7_IN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_EP_ABORT_EP6_OUT -#define USB_EP_ABORT_EP6_OUT_RESET _u(0x0) -#define USB_EP_ABORT_EP6_OUT_BITS _u(0x00002000) -#define USB_EP_ABORT_EP6_OUT_MSB _u(13) -#define USB_EP_ABORT_EP6_OUT_LSB _u(13) -#define USB_EP_ABORT_EP6_OUT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_EP_ABORT_EP6_IN -#define USB_EP_ABORT_EP6_IN_RESET _u(0x0) -#define USB_EP_ABORT_EP6_IN_BITS _u(0x00001000) -#define USB_EP_ABORT_EP6_IN_MSB _u(12) -#define USB_EP_ABORT_EP6_IN_LSB _u(12) -#define USB_EP_ABORT_EP6_IN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_EP_ABORT_EP5_OUT -#define USB_EP_ABORT_EP5_OUT_RESET _u(0x0) -#define USB_EP_ABORT_EP5_OUT_BITS _u(0x00000800) -#define USB_EP_ABORT_EP5_OUT_MSB _u(11) -#define USB_EP_ABORT_EP5_OUT_LSB _u(11) -#define USB_EP_ABORT_EP5_OUT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_EP_ABORT_EP5_IN -#define USB_EP_ABORT_EP5_IN_RESET _u(0x0) -#define USB_EP_ABORT_EP5_IN_BITS _u(0x00000400) -#define USB_EP_ABORT_EP5_IN_MSB _u(10) -#define USB_EP_ABORT_EP5_IN_LSB _u(10) -#define USB_EP_ABORT_EP5_IN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_EP_ABORT_EP4_OUT -#define USB_EP_ABORT_EP4_OUT_RESET _u(0x0) -#define USB_EP_ABORT_EP4_OUT_BITS _u(0x00000200) -#define USB_EP_ABORT_EP4_OUT_MSB _u(9) -#define USB_EP_ABORT_EP4_OUT_LSB _u(9) -#define USB_EP_ABORT_EP4_OUT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_EP_ABORT_EP4_IN -#define USB_EP_ABORT_EP4_IN_RESET _u(0x0) -#define USB_EP_ABORT_EP4_IN_BITS _u(0x00000100) -#define USB_EP_ABORT_EP4_IN_MSB _u(8) -#define USB_EP_ABORT_EP4_IN_LSB _u(8) -#define USB_EP_ABORT_EP4_IN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_EP_ABORT_EP3_OUT -#define USB_EP_ABORT_EP3_OUT_RESET _u(0x0) -#define USB_EP_ABORT_EP3_OUT_BITS _u(0x00000080) -#define USB_EP_ABORT_EP3_OUT_MSB _u(7) -#define USB_EP_ABORT_EP3_OUT_LSB _u(7) -#define USB_EP_ABORT_EP3_OUT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_EP_ABORT_EP3_IN -#define USB_EP_ABORT_EP3_IN_RESET _u(0x0) -#define USB_EP_ABORT_EP3_IN_BITS _u(0x00000040) -#define USB_EP_ABORT_EP3_IN_MSB _u(6) -#define USB_EP_ABORT_EP3_IN_LSB _u(6) -#define USB_EP_ABORT_EP3_IN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_EP_ABORT_EP2_OUT -#define USB_EP_ABORT_EP2_OUT_RESET _u(0x0) -#define USB_EP_ABORT_EP2_OUT_BITS _u(0x00000020) -#define USB_EP_ABORT_EP2_OUT_MSB _u(5) -#define USB_EP_ABORT_EP2_OUT_LSB _u(5) -#define USB_EP_ABORT_EP2_OUT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_EP_ABORT_EP2_IN -#define USB_EP_ABORT_EP2_IN_RESET _u(0x0) -#define USB_EP_ABORT_EP2_IN_BITS _u(0x00000010) -#define USB_EP_ABORT_EP2_IN_MSB _u(4) -#define USB_EP_ABORT_EP2_IN_LSB _u(4) -#define USB_EP_ABORT_EP2_IN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_EP_ABORT_EP1_OUT -#define USB_EP_ABORT_EP1_OUT_RESET _u(0x0) -#define USB_EP_ABORT_EP1_OUT_BITS _u(0x00000008) -#define USB_EP_ABORT_EP1_OUT_MSB _u(3) -#define USB_EP_ABORT_EP1_OUT_LSB _u(3) -#define USB_EP_ABORT_EP1_OUT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_EP_ABORT_EP1_IN -#define USB_EP_ABORT_EP1_IN_RESET _u(0x0) -#define USB_EP_ABORT_EP1_IN_BITS _u(0x00000004) -#define USB_EP_ABORT_EP1_IN_MSB _u(2) -#define USB_EP_ABORT_EP1_IN_LSB _u(2) -#define USB_EP_ABORT_EP1_IN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_EP_ABORT_EP0_OUT -#define USB_EP_ABORT_EP0_OUT_RESET _u(0x0) -#define USB_EP_ABORT_EP0_OUT_BITS _u(0x00000002) -#define USB_EP_ABORT_EP0_OUT_MSB _u(1) -#define USB_EP_ABORT_EP0_OUT_LSB _u(1) -#define USB_EP_ABORT_EP0_OUT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_EP_ABORT_EP0_IN -#define USB_EP_ABORT_EP0_IN_RESET _u(0x0) -#define USB_EP_ABORT_EP0_IN_BITS _u(0x00000001) -#define USB_EP_ABORT_EP0_IN_MSB _u(0) -#define USB_EP_ABORT_EP0_IN_LSB _u(0) -#define USB_EP_ABORT_EP0_IN_ACCESS "RW" -// ============================================================================= -// Register : USB_EP_ABORT_DONE -// Description : Device only: Used in conjunction with `EP_ABORT`. Set once an -// endpoint is idle so the programmer knows it is safe to modify -// the buffer control register. -#define USB_EP_ABORT_DONE_OFFSET _u(0x00000064) -#define USB_EP_ABORT_DONE_BITS _u(0xffffffff) -#define USB_EP_ABORT_DONE_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_EP_ABORT_DONE_EP15_OUT -#define USB_EP_ABORT_DONE_EP15_OUT_RESET _u(0x0) -#define USB_EP_ABORT_DONE_EP15_OUT_BITS _u(0x80000000) -#define USB_EP_ABORT_DONE_EP15_OUT_MSB _u(31) -#define USB_EP_ABORT_DONE_EP15_OUT_LSB _u(31) -#define USB_EP_ABORT_DONE_EP15_OUT_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_ABORT_DONE_EP15_IN -#define USB_EP_ABORT_DONE_EP15_IN_RESET _u(0x0) -#define USB_EP_ABORT_DONE_EP15_IN_BITS _u(0x40000000) -#define USB_EP_ABORT_DONE_EP15_IN_MSB _u(30) -#define USB_EP_ABORT_DONE_EP15_IN_LSB _u(30) -#define USB_EP_ABORT_DONE_EP15_IN_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_ABORT_DONE_EP14_OUT -#define USB_EP_ABORT_DONE_EP14_OUT_RESET _u(0x0) -#define USB_EP_ABORT_DONE_EP14_OUT_BITS _u(0x20000000) -#define USB_EP_ABORT_DONE_EP14_OUT_MSB _u(29) -#define USB_EP_ABORT_DONE_EP14_OUT_LSB _u(29) -#define USB_EP_ABORT_DONE_EP14_OUT_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_ABORT_DONE_EP14_IN -#define USB_EP_ABORT_DONE_EP14_IN_RESET _u(0x0) -#define USB_EP_ABORT_DONE_EP14_IN_BITS _u(0x10000000) -#define USB_EP_ABORT_DONE_EP14_IN_MSB _u(28) -#define USB_EP_ABORT_DONE_EP14_IN_LSB _u(28) -#define USB_EP_ABORT_DONE_EP14_IN_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_ABORT_DONE_EP13_OUT -#define USB_EP_ABORT_DONE_EP13_OUT_RESET _u(0x0) -#define USB_EP_ABORT_DONE_EP13_OUT_BITS _u(0x08000000) -#define USB_EP_ABORT_DONE_EP13_OUT_MSB _u(27) -#define USB_EP_ABORT_DONE_EP13_OUT_LSB _u(27) -#define USB_EP_ABORT_DONE_EP13_OUT_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_ABORT_DONE_EP13_IN -#define USB_EP_ABORT_DONE_EP13_IN_RESET _u(0x0) -#define USB_EP_ABORT_DONE_EP13_IN_BITS _u(0x04000000) -#define USB_EP_ABORT_DONE_EP13_IN_MSB _u(26) -#define USB_EP_ABORT_DONE_EP13_IN_LSB _u(26) -#define USB_EP_ABORT_DONE_EP13_IN_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_ABORT_DONE_EP12_OUT -#define USB_EP_ABORT_DONE_EP12_OUT_RESET _u(0x0) -#define USB_EP_ABORT_DONE_EP12_OUT_BITS _u(0x02000000) -#define USB_EP_ABORT_DONE_EP12_OUT_MSB _u(25) -#define USB_EP_ABORT_DONE_EP12_OUT_LSB _u(25) -#define USB_EP_ABORT_DONE_EP12_OUT_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_ABORT_DONE_EP12_IN -#define USB_EP_ABORT_DONE_EP12_IN_RESET _u(0x0) -#define USB_EP_ABORT_DONE_EP12_IN_BITS _u(0x01000000) -#define USB_EP_ABORT_DONE_EP12_IN_MSB _u(24) -#define USB_EP_ABORT_DONE_EP12_IN_LSB _u(24) -#define USB_EP_ABORT_DONE_EP12_IN_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_ABORT_DONE_EP11_OUT -#define USB_EP_ABORT_DONE_EP11_OUT_RESET _u(0x0) -#define USB_EP_ABORT_DONE_EP11_OUT_BITS _u(0x00800000) -#define USB_EP_ABORT_DONE_EP11_OUT_MSB _u(23) -#define USB_EP_ABORT_DONE_EP11_OUT_LSB _u(23) -#define USB_EP_ABORT_DONE_EP11_OUT_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_ABORT_DONE_EP11_IN -#define USB_EP_ABORT_DONE_EP11_IN_RESET _u(0x0) -#define USB_EP_ABORT_DONE_EP11_IN_BITS _u(0x00400000) -#define USB_EP_ABORT_DONE_EP11_IN_MSB _u(22) -#define USB_EP_ABORT_DONE_EP11_IN_LSB _u(22) -#define USB_EP_ABORT_DONE_EP11_IN_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_ABORT_DONE_EP10_OUT -#define USB_EP_ABORT_DONE_EP10_OUT_RESET _u(0x0) -#define USB_EP_ABORT_DONE_EP10_OUT_BITS _u(0x00200000) -#define USB_EP_ABORT_DONE_EP10_OUT_MSB _u(21) -#define USB_EP_ABORT_DONE_EP10_OUT_LSB _u(21) -#define USB_EP_ABORT_DONE_EP10_OUT_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_ABORT_DONE_EP10_IN -#define USB_EP_ABORT_DONE_EP10_IN_RESET _u(0x0) -#define USB_EP_ABORT_DONE_EP10_IN_BITS _u(0x00100000) -#define USB_EP_ABORT_DONE_EP10_IN_MSB _u(20) -#define USB_EP_ABORT_DONE_EP10_IN_LSB _u(20) -#define USB_EP_ABORT_DONE_EP10_IN_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_ABORT_DONE_EP9_OUT -#define USB_EP_ABORT_DONE_EP9_OUT_RESET _u(0x0) -#define USB_EP_ABORT_DONE_EP9_OUT_BITS _u(0x00080000) -#define USB_EP_ABORT_DONE_EP9_OUT_MSB _u(19) -#define USB_EP_ABORT_DONE_EP9_OUT_LSB _u(19) -#define USB_EP_ABORT_DONE_EP9_OUT_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_ABORT_DONE_EP9_IN -#define USB_EP_ABORT_DONE_EP9_IN_RESET _u(0x0) -#define USB_EP_ABORT_DONE_EP9_IN_BITS _u(0x00040000) -#define USB_EP_ABORT_DONE_EP9_IN_MSB _u(18) -#define USB_EP_ABORT_DONE_EP9_IN_LSB _u(18) -#define USB_EP_ABORT_DONE_EP9_IN_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_ABORT_DONE_EP8_OUT -#define USB_EP_ABORT_DONE_EP8_OUT_RESET _u(0x0) -#define USB_EP_ABORT_DONE_EP8_OUT_BITS _u(0x00020000) -#define USB_EP_ABORT_DONE_EP8_OUT_MSB _u(17) -#define USB_EP_ABORT_DONE_EP8_OUT_LSB _u(17) -#define USB_EP_ABORT_DONE_EP8_OUT_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_ABORT_DONE_EP8_IN -#define USB_EP_ABORT_DONE_EP8_IN_RESET _u(0x0) -#define USB_EP_ABORT_DONE_EP8_IN_BITS _u(0x00010000) -#define USB_EP_ABORT_DONE_EP8_IN_MSB _u(16) -#define USB_EP_ABORT_DONE_EP8_IN_LSB _u(16) -#define USB_EP_ABORT_DONE_EP8_IN_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_ABORT_DONE_EP7_OUT -#define USB_EP_ABORT_DONE_EP7_OUT_RESET _u(0x0) -#define USB_EP_ABORT_DONE_EP7_OUT_BITS _u(0x00008000) -#define USB_EP_ABORT_DONE_EP7_OUT_MSB _u(15) -#define USB_EP_ABORT_DONE_EP7_OUT_LSB _u(15) -#define USB_EP_ABORT_DONE_EP7_OUT_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_ABORT_DONE_EP7_IN -#define USB_EP_ABORT_DONE_EP7_IN_RESET _u(0x0) -#define USB_EP_ABORT_DONE_EP7_IN_BITS _u(0x00004000) -#define USB_EP_ABORT_DONE_EP7_IN_MSB _u(14) -#define USB_EP_ABORT_DONE_EP7_IN_LSB _u(14) -#define USB_EP_ABORT_DONE_EP7_IN_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_ABORT_DONE_EP6_OUT -#define USB_EP_ABORT_DONE_EP6_OUT_RESET _u(0x0) -#define USB_EP_ABORT_DONE_EP6_OUT_BITS _u(0x00002000) -#define USB_EP_ABORT_DONE_EP6_OUT_MSB _u(13) -#define USB_EP_ABORT_DONE_EP6_OUT_LSB _u(13) -#define USB_EP_ABORT_DONE_EP6_OUT_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_ABORT_DONE_EP6_IN -#define USB_EP_ABORT_DONE_EP6_IN_RESET _u(0x0) -#define USB_EP_ABORT_DONE_EP6_IN_BITS _u(0x00001000) -#define USB_EP_ABORT_DONE_EP6_IN_MSB _u(12) -#define USB_EP_ABORT_DONE_EP6_IN_LSB _u(12) -#define USB_EP_ABORT_DONE_EP6_IN_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_ABORT_DONE_EP5_OUT -#define USB_EP_ABORT_DONE_EP5_OUT_RESET _u(0x0) -#define USB_EP_ABORT_DONE_EP5_OUT_BITS _u(0x00000800) -#define USB_EP_ABORT_DONE_EP5_OUT_MSB _u(11) -#define USB_EP_ABORT_DONE_EP5_OUT_LSB _u(11) -#define USB_EP_ABORT_DONE_EP5_OUT_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_ABORT_DONE_EP5_IN -#define USB_EP_ABORT_DONE_EP5_IN_RESET _u(0x0) -#define USB_EP_ABORT_DONE_EP5_IN_BITS _u(0x00000400) -#define USB_EP_ABORT_DONE_EP5_IN_MSB _u(10) -#define USB_EP_ABORT_DONE_EP5_IN_LSB _u(10) -#define USB_EP_ABORT_DONE_EP5_IN_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_ABORT_DONE_EP4_OUT -#define USB_EP_ABORT_DONE_EP4_OUT_RESET _u(0x0) -#define USB_EP_ABORT_DONE_EP4_OUT_BITS _u(0x00000200) -#define USB_EP_ABORT_DONE_EP4_OUT_MSB _u(9) -#define USB_EP_ABORT_DONE_EP4_OUT_LSB _u(9) -#define USB_EP_ABORT_DONE_EP4_OUT_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_ABORT_DONE_EP4_IN -#define USB_EP_ABORT_DONE_EP4_IN_RESET _u(0x0) -#define USB_EP_ABORT_DONE_EP4_IN_BITS _u(0x00000100) -#define USB_EP_ABORT_DONE_EP4_IN_MSB _u(8) -#define USB_EP_ABORT_DONE_EP4_IN_LSB _u(8) -#define USB_EP_ABORT_DONE_EP4_IN_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_ABORT_DONE_EP3_OUT -#define USB_EP_ABORT_DONE_EP3_OUT_RESET _u(0x0) -#define USB_EP_ABORT_DONE_EP3_OUT_BITS _u(0x00000080) -#define USB_EP_ABORT_DONE_EP3_OUT_MSB _u(7) -#define USB_EP_ABORT_DONE_EP3_OUT_LSB _u(7) -#define USB_EP_ABORT_DONE_EP3_OUT_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_ABORT_DONE_EP3_IN -#define USB_EP_ABORT_DONE_EP3_IN_RESET _u(0x0) -#define USB_EP_ABORT_DONE_EP3_IN_BITS _u(0x00000040) -#define USB_EP_ABORT_DONE_EP3_IN_MSB _u(6) -#define USB_EP_ABORT_DONE_EP3_IN_LSB _u(6) -#define USB_EP_ABORT_DONE_EP3_IN_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_ABORT_DONE_EP2_OUT -#define USB_EP_ABORT_DONE_EP2_OUT_RESET _u(0x0) -#define USB_EP_ABORT_DONE_EP2_OUT_BITS _u(0x00000020) -#define USB_EP_ABORT_DONE_EP2_OUT_MSB _u(5) -#define USB_EP_ABORT_DONE_EP2_OUT_LSB _u(5) -#define USB_EP_ABORT_DONE_EP2_OUT_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_ABORT_DONE_EP2_IN -#define USB_EP_ABORT_DONE_EP2_IN_RESET _u(0x0) -#define USB_EP_ABORT_DONE_EP2_IN_BITS _u(0x00000010) -#define USB_EP_ABORT_DONE_EP2_IN_MSB _u(4) -#define USB_EP_ABORT_DONE_EP2_IN_LSB _u(4) -#define USB_EP_ABORT_DONE_EP2_IN_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_ABORT_DONE_EP1_OUT -#define USB_EP_ABORT_DONE_EP1_OUT_RESET _u(0x0) -#define USB_EP_ABORT_DONE_EP1_OUT_BITS _u(0x00000008) -#define USB_EP_ABORT_DONE_EP1_OUT_MSB _u(3) -#define USB_EP_ABORT_DONE_EP1_OUT_LSB _u(3) -#define USB_EP_ABORT_DONE_EP1_OUT_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_ABORT_DONE_EP1_IN -#define USB_EP_ABORT_DONE_EP1_IN_RESET _u(0x0) -#define USB_EP_ABORT_DONE_EP1_IN_BITS _u(0x00000004) -#define USB_EP_ABORT_DONE_EP1_IN_MSB _u(2) -#define USB_EP_ABORT_DONE_EP1_IN_LSB _u(2) -#define USB_EP_ABORT_DONE_EP1_IN_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_ABORT_DONE_EP0_OUT -#define USB_EP_ABORT_DONE_EP0_OUT_RESET _u(0x0) -#define USB_EP_ABORT_DONE_EP0_OUT_BITS _u(0x00000002) -#define USB_EP_ABORT_DONE_EP0_OUT_MSB _u(1) -#define USB_EP_ABORT_DONE_EP0_OUT_LSB _u(1) -#define USB_EP_ABORT_DONE_EP0_OUT_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_ABORT_DONE_EP0_IN -#define USB_EP_ABORT_DONE_EP0_IN_RESET _u(0x0) -#define USB_EP_ABORT_DONE_EP0_IN_BITS _u(0x00000001) -#define USB_EP_ABORT_DONE_EP0_IN_MSB _u(0) -#define USB_EP_ABORT_DONE_EP0_IN_LSB _u(0) -#define USB_EP_ABORT_DONE_EP0_IN_ACCESS "WC" -// ============================================================================= -// Register : USB_EP_STALL_ARM -// Description : Device: this bit must be set in conjunction with the `STALL` -// bit in the buffer control register to send a STALL on EP0. The -// device controller clears these bits when a SETUP packet is -// received because the USB spec requires that a STALL condition -// is cleared when a SETUP packet is received. -#define USB_EP_STALL_ARM_OFFSET _u(0x00000068) -#define USB_EP_STALL_ARM_BITS _u(0x00000003) -#define USB_EP_STALL_ARM_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_EP_STALL_ARM_EP0_OUT -#define USB_EP_STALL_ARM_EP0_OUT_RESET _u(0x0) -#define USB_EP_STALL_ARM_EP0_OUT_BITS _u(0x00000002) -#define USB_EP_STALL_ARM_EP0_OUT_MSB _u(1) -#define USB_EP_STALL_ARM_EP0_OUT_LSB _u(1) -#define USB_EP_STALL_ARM_EP0_OUT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_EP_STALL_ARM_EP0_IN -#define USB_EP_STALL_ARM_EP0_IN_RESET _u(0x0) -#define USB_EP_STALL_ARM_EP0_IN_BITS _u(0x00000001) -#define USB_EP_STALL_ARM_EP0_IN_MSB _u(0) -#define USB_EP_STALL_ARM_EP0_IN_LSB _u(0) -#define USB_EP_STALL_ARM_EP0_IN_ACCESS "RW" -// ============================================================================= -// Register : USB_NAK_POLL -// Description : Used by the host controller. Sets the wait time in microseconds -// before trying again if the device replies with a NAK. -#define USB_NAK_POLL_OFFSET _u(0x0000006c) -#define USB_NAK_POLL_BITS _u(0x03ff03ff) -#define USB_NAK_POLL_RESET _u(0x00100010) -// ----------------------------------------------------------------------------- -// Field : USB_NAK_POLL_DELAY_FS -// Description : NAK polling interval for a full speed device -#define USB_NAK_POLL_DELAY_FS_RESET _u(0x010) -#define USB_NAK_POLL_DELAY_FS_BITS _u(0x03ff0000) -#define USB_NAK_POLL_DELAY_FS_MSB _u(25) -#define USB_NAK_POLL_DELAY_FS_LSB _u(16) -#define USB_NAK_POLL_DELAY_FS_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_NAK_POLL_DELAY_LS -// Description : NAK polling interval for a low speed device -#define USB_NAK_POLL_DELAY_LS_RESET _u(0x010) -#define USB_NAK_POLL_DELAY_LS_BITS _u(0x000003ff) -#define USB_NAK_POLL_DELAY_LS_MSB _u(9) -#define USB_NAK_POLL_DELAY_LS_LSB _u(0) -#define USB_NAK_POLL_DELAY_LS_ACCESS "RW" -// ============================================================================= -// Register : USB_EP_STATUS_STALL_NAK -// Description : Device: bits are set when the `IRQ_ON_NAK` or `IRQ_ON_STALL` -// bits are set. For EP0 this comes from `SIE_CTRL`. For all other -// endpoints it comes from the endpoint control register. -#define USB_EP_STATUS_STALL_NAK_OFFSET _u(0x00000070) -#define USB_EP_STATUS_STALL_NAK_BITS _u(0xffffffff) -#define USB_EP_STATUS_STALL_NAK_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_EP_STATUS_STALL_NAK_EP15_OUT -#define USB_EP_STATUS_STALL_NAK_EP15_OUT_RESET _u(0x0) -#define USB_EP_STATUS_STALL_NAK_EP15_OUT_BITS _u(0x80000000) -#define USB_EP_STATUS_STALL_NAK_EP15_OUT_MSB _u(31) -#define USB_EP_STATUS_STALL_NAK_EP15_OUT_LSB _u(31) -#define USB_EP_STATUS_STALL_NAK_EP15_OUT_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_STATUS_STALL_NAK_EP15_IN -#define USB_EP_STATUS_STALL_NAK_EP15_IN_RESET _u(0x0) -#define USB_EP_STATUS_STALL_NAK_EP15_IN_BITS _u(0x40000000) -#define USB_EP_STATUS_STALL_NAK_EP15_IN_MSB _u(30) -#define USB_EP_STATUS_STALL_NAK_EP15_IN_LSB _u(30) -#define USB_EP_STATUS_STALL_NAK_EP15_IN_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_STATUS_STALL_NAK_EP14_OUT -#define USB_EP_STATUS_STALL_NAK_EP14_OUT_RESET _u(0x0) -#define USB_EP_STATUS_STALL_NAK_EP14_OUT_BITS _u(0x20000000) -#define USB_EP_STATUS_STALL_NAK_EP14_OUT_MSB _u(29) -#define USB_EP_STATUS_STALL_NAK_EP14_OUT_LSB _u(29) -#define USB_EP_STATUS_STALL_NAK_EP14_OUT_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_STATUS_STALL_NAK_EP14_IN -#define USB_EP_STATUS_STALL_NAK_EP14_IN_RESET _u(0x0) -#define USB_EP_STATUS_STALL_NAK_EP14_IN_BITS _u(0x10000000) -#define USB_EP_STATUS_STALL_NAK_EP14_IN_MSB _u(28) -#define USB_EP_STATUS_STALL_NAK_EP14_IN_LSB _u(28) -#define USB_EP_STATUS_STALL_NAK_EP14_IN_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_STATUS_STALL_NAK_EP13_OUT -#define USB_EP_STATUS_STALL_NAK_EP13_OUT_RESET _u(0x0) -#define USB_EP_STATUS_STALL_NAK_EP13_OUT_BITS _u(0x08000000) -#define USB_EP_STATUS_STALL_NAK_EP13_OUT_MSB _u(27) -#define USB_EP_STATUS_STALL_NAK_EP13_OUT_LSB _u(27) -#define USB_EP_STATUS_STALL_NAK_EP13_OUT_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_STATUS_STALL_NAK_EP13_IN -#define USB_EP_STATUS_STALL_NAK_EP13_IN_RESET _u(0x0) -#define USB_EP_STATUS_STALL_NAK_EP13_IN_BITS _u(0x04000000) -#define USB_EP_STATUS_STALL_NAK_EP13_IN_MSB _u(26) -#define USB_EP_STATUS_STALL_NAK_EP13_IN_LSB _u(26) -#define USB_EP_STATUS_STALL_NAK_EP13_IN_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_STATUS_STALL_NAK_EP12_OUT -#define USB_EP_STATUS_STALL_NAK_EP12_OUT_RESET _u(0x0) -#define USB_EP_STATUS_STALL_NAK_EP12_OUT_BITS _u(0x02000000) -#define USB_EP_STATUS_STALL_NAK_EP12_OUT_MSB _u(25) -#define USB_EP_STATUS_STALL_NAK_EP12_OUT_LSB _u(25) -#define USB_EP_STATUS_STALL_NAK_EP12_OUT_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_STATUS_STALL_NAK_EP12_IN -#define USB_EP_STATUS_STALL_NAK_EP12_IN_RESET _u(0x0) -#define USB_EP_STATUS_STALL_NAK_EP12_IN_BITS _u(0x01000000) -#define USB_EP_STATUS_STALL_NAK_EP12_IN_MSB _u(24) -#define USB_EP_STATUS_STALL_NAK_EP12_IN_LSB _u(24) -#define USB_EP_STATUS_STALL_NAK_EP12_IN_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_STATUS_STALL_NAK_EP11_OUT -#define USB_EP_STATUS_STALL_NAK_EP11_OUT_RESET _u(0x0) -#define USB_EP_STATUS_STALL_NAK_EP11_OUT_BITS _u(0x00800000) -#define USB_EP_STATUS_STALL_NAK_EP11_OUT_MSB _u(23) -#define USB_EP_STATUS_STALL_NAK_EP11_OUT_LSB _u(23) -#define USB_EP_STATUS_STALL_NAK_EP11_OUT_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_STATUS_STALL_NAK_EP11_IN -#define USB_EP_STATUS_STALL_NAK_EP11_IN_RESET _u(0x0) -#define USB_EP_STATUS_STALL_NAK_EP11_IN_BITS _u(0x00400000) -#define USB_EP_STATUS_STALL_NAK_EP11_IN_MSB _u(22) -#define USB_EP_STATUS_STALL_NAK_EP11_IN_LSB _u(22) -#define USB_EP_STATUS_STALL_NAK_EP11_IN_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_STATUS_STALL_NAK_EP10_OUT -#define USB_EP_STATUS_STALL_NAK_EP10_OUT_RESET _u(0x0) -#define USB_EP_STATUS_STALL_NAK_EP10_OUT_BITS _u(0x00200000) -#define USB_EP_STATUS_STALL_NAK_EP10_OUT_MSB _u(21) -#define USB_EP_STATUS_STALL_NAK_EP10_OUT_LSB _u(21) -#define USB_EP_STATUS_STALL_NAK_EP10_OUT_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_STATUS_STALL_NAK_EP10_IN -#define USB_EP_STATUS_STALL_NAK_EP10_IN_RESET _u(0x0) -#define USB_EP_STATUS_STALL_NAK_EP10_IN_BITS _u(0x00100000) -#define USB_EP_STATUS_STALL_NAK_EP10_IN_MSB _u(20) -#define USB_EP_STATUS_STALL_NAK_EP10_IN_LSB _u(20) -#define USB_EP_STATUS_STALL_NAK_EP10_IN_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_STATUS_STALL_NAK_EP9_OUT -#define USB_EP_STATUS_STALL_NAK_EP9_OUT_RESET _u(0x0) -#define USB_EP_STATUS_STALL_NAK_EP9_OUT_BITS _u(0x00080000) -#define USB_EP_STATUS_STALL_NAK_EP9_OUT_MSB _u(19) -#define USB_EP_STATUS_STALL_NAK_EP9_OUT_LSB _u(19) -#define USB_EP_STATUS_STALL_NAK_EP9_OUT_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_STATUS_STALL_NAK_EP9_IN -#define USB_EP_STATUS_STALL_NAK_EP9_IN_RESET _u(0x0) -#define USB_EP_STATUS_STALL_NAK_EP9_IN_BITS _u(0x00040000) -#define USB_EP_STATUS_STALL_NAK_EP9_IN_MSB _u(18) -#define USB_EP_STATUS_STALL_NAK_EP9_IN_LSB _u(18) -#define USB_EP_STATUS_STALL_NAK_EP9_IN_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_STATUS_STALL_NAK_EP8_OUT -#define USB_EP_STATUS_STALL_NAK_EP8_OUT_RESET _u(0x0) -#define USB_EP_STATUS_STALL_NAK_EP8_OUT_BITS _u(0x00020000) -#define USB_EP_STATUS_STALL_NAK_EP8_OUT_MSB _u(17) -#define USB_EP_STATUS_STALL_NAK_EP8_OUT_LSB _u(17) -#define USB_EP_STATUS_STALL_NAK_EP8_OUT_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_STATUS_STALL_NAK_EP8_IN -#define USB_EP_STATUS_STALL_NAK_EP8_IN_RESET _u(0x0) -#define USB_EP_STATUS_STALL_NAK_EP8_IN_BITS _u(0x00010000) -#define USB_EP_STATUS_STALL_NAK_EP8_IN_MSB _u(16) -#define USB_EP_STATUS_STALL_NAK_EP8_IN_LSB _u(16) -#define USB_EP_STATUS_STALL_NAK_EP8_IN_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_STATUS_STALL_NAK_EP7_OUT -#define USB_EP_STATUS_STALL_NAK_EP7_OUT_RESET _u(0x0) -#define USB_EP_STATUS_STALL_NAK_EP7_OUT_BITS _u(0x00008000) -#define USB_EP_STATUS_STALL_NAK_EP7_OUT_MSB _u(15) -#define USB_EP_STATUS_STALL_NAK_EP7_OUT_LSB _u(15) -#define USB_EP_STATUS_STALL_NAK_EP7_OUT_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_STATUS_STALL_NAK_EP7_IN -#define USB_EP_STATUS_STALL_NAK_EP7_IN_RESET _u(0x0) -#define USB_EP_STATUS_STALL_NAK_EP7_IN_BITS _u(0x00004000) -#define USB_EP_STATUS_STALL_NAK_EP7_IN_MSB _u(14) -#define USB_EP_STATUS_STALL_NAK_EP7_IN_LSB _u(14) -#define USB_EP_STATUS_STALL_NAK_EP7_IN_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_STATUS_STALL_NAK_EP6_OUT -#define USB_EP_STATUS_STALL_NAK_EP6_OUT_RESET _u(0x0) -#define USB_EP_STATUS_STALL_NAK_EP6_OUT_BITS _u(0x00002000) -#define USB_EP_STATUS_STALL_NAK_EP6_OUT_MSB _u(13) -#define USB_EP_STATUS_STALL_NAK_EP6_OUT_LSB _u(13) -#define USB_EP_STATUS_STALL_NAK_EP6_OUT_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_STATUS_STALL_NAK_EP6_IN -#define USB_EP_STATUS_STALL_NAK_EP6_IN_RESET _u(0x0) -#define USB_EP_STATUS_STALL_NAK_EP6_IN_BITS _u(0x00001000) -#define USB_EP_STATUS_STALL_NAK_EP6_IN_MSB _u(12) -#define USB_EP_STATUS_STALL_NAK_EP6_IN_LSB _u(12) -#define USB_EP_STATUS_STALL_NAK_EP6_IN_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_STATUS_STALL_NAK_EP5_OUT -#define USB_EP_STATUS_STALL_NAK_EP5_OUT_RESET _u(0x0) -#define USB_EP_STATUS_STALL_NAK_EP5_OUT_BITS _u(0x00000800) -#define USB_EP_STATUS_STALL_NAK_EP5_OUT_MSB _u(11) -#define USB_EP_STATUS_STALL_NAK_EP5_OUT_LSB _u(11) -#define USB_EP_STATUS_STALL_NAK_EP5_OUT_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_STATUS_STALL_NAK_EP5_IN -#define USB_EP_STATUS_STALL_NAK_EP5_IN_RESET _u(0x0) -#define USB_EP_STATUS_STALL_NAK_EP5_IN_BITS _u(0x00000400) -#define USB_EP_STATUS_STALL_NAK_EP5_IN_MSB _u(10) -#define USB_EP_STATUS_STALL_NAK_EP5_IN_LSB _u(10) -#define USB_EP_STATUS_STALL_NAK_EP5_IN_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_STATUS_STALL_NAK_EP4_OUT -#define USB_EP_STATUS_STALL_NAK_EP4_OUT_RESET _u(0x0) -#define USB_EP_STATUS_STALL_NAK_EP4_OUT_BITS _u(0x00000200) -#define USB_EP_STATUS_STALL_NAK_EP4_OUT_MSB _u(9) -#define USB_EP_STATUS_STALL_NAK_EP4_OUT_LSB _u(9) -#define USB_EP_STATUS_STALL_NAK_EP4_OUT_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_STATUS_STALL_NAK_EP4_IN -#define USB_EP_STATUS_STALL_NAK_EP4_IN_RESET _u(0x0) -#define USB_EP_STATUS_STALL_NAK_EP4_IN_BITS _u(0x00000100) -#define USB_EP_STATUS_STALL_NAK_EP4_IN_MSB _u(8) -#define USB_EP_STATUS_STALL_NAK_EP4_IN_LSB _u(8) -#define USB_EP_STATUS_STALL_NAK_EP4_IN_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_STATUS_STALL_NAK_EP3_OUT -#define USB_EP_STATUS_STALL_NAK_EP3_OUT_RESET _u(0x0) -#define USB_EP_STATUS_STALL_NAK_EP3_OUT_BITS _u(0x00000080) -#define USB_EP_STATUS_STALL_NAK_EP3_OUT_MSB _u(7) -#define USB_EP_STATUS_STALL_NAK_EP3_OUT_LSB _u(7) -#define USB_EP_STATUS_STALL_NAK_EP3_OUT_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_STATUS_STALL_NAK_EP3_IN -#define USB_EP_STATUS_STALL_NAK_EP3_IN_RESET _u(0x0) -#define USB_EP_STATUS_STALL_NAK_EP3_IN_BITS _u(0x00000040) -#define USB_EP_STATUS_STALL_NAK_EP3_IN_MSB _u(6) -#define USB_EP_STATUS_STALL_NAK_EP3_IN_LSB _u(6) -#define USB_EP_STATUS_STALL_NAK_EP3_IN_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_STATUS_STALL_NAK_EP2_OUT -#define USB_EP_STATUS_STALL_NAK_EP2_OUT_RESET _u(0x0) -#define USB_EP_STATUS_STALL_NAK_EP2_OUT_BITS _u(0x00000020) -#define USB_EP_STATUS_STALL_NAK_EP2_OUT_MSB _u(5) -#define USB_EP_STATUS_STALL_NAK_EP2_OUT_LSB _u(5) -#define USB_EP_STATUS_STALL_NAK_EP2_OUT_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_STATUS_STALL_NAK_EP2_IN -#define USB_EP_STATUS_STALL_NAK_EP2_IN_RESET _u(0x0) -#define USB_EP_STATUS_STALL_NAK_EP2_IN_BITS _u(0x00000010) -#define USB_EP_STATUS_STALL_NAK_EP2_IN_MSB _u(4) -#define USB_EP_STATUS_STALL_NAK_EP2_IN_LSB _u(4) -#define USB_EP_STATUS_STALL_NAK_EP2_IN_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_STATUS_STALL_NAK_EP1_OUT -#define USB_EP_STATUS_STALL_NAK_EP1_OUT_RESET _u(0x0) -#define USB_EP_STATUS_STALL_NAK_EP1_OUT_BITS _u(0x00000008) -#define USB_EP_STATUS_STALL_NAK_EP1_OUT_MSB _u(3) -#define USB_EP_STATUS_STALL_NAK_EP1_OUT_LSB _u(3) -#define USB_EP_STATUS_STALL_NAK_EP1_OUT_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_STATUS_STALL_NAK_EP1_IN -#define USB_EP_STATUS_STALL_NAK_EP1_IN_RESET _u(0x0) -#define USB_EP_STATUS_STALL_NAK_EP1_IN_BITS _u(0x00000004) -#define USB_EP_STATUS_STALL_NAK_EP1_IN_MSB _u(2) -#define USB_EP_STATUS_STALL_NAK_EP1_IN_LSB _u(2) -#define USB_EP_STATUS_STALL_NAK_EP1_IN_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_STATUS_STALL_NAK_EP0_OUT -#define USB_EP_STATUS_STALL_NAK_EP0_OUT_RESET _u(0x0) -#define USB_EP_STATUS_STALL_NAK_EP0_OUT_BITS _u(0x00000002) -#define USB_EP_STATUS_STALL_NAK_EP0_OUT_MSB _u(1) -#define USB_EP_STATUS_STALL_NAK_EP0_OUT_LSB _u(1) -#define USB_EP_STATUS_STALL_NAK_EP0_OUT_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_STATUS_STALL_NAK_EP0_IN -#define USB_EP_STATUS_STALL_NAK_EP0_IN_RESET _u(0x0) -#define USB_EP_STATUS_STALL_NAK_EP0_IN_BITS _u(0x00000001) -#define USB_EP_STATUS_STALL_NAK_EP0_IN_MSB _u(0) -#define USB_EP_STATUS_STALL_NAK_EP0_IN_LSB _u(0) -#define USB_EP_STATUS_STALL_NAK_EP0_IN_ACCESS "WC" -// ============================================================================= -// Register : USB_USB_MUXING -// Description : Where to connect the USB controller. Should be to_phy by -// default. -#define USB_USB_MUXING_OFFSET _u(0x00000074) -#define USB_USB_MUXING_BITS _u(0x0000000f) -#define USB_USB_MUXING_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_USB_MUXING_SOFTCON -#define USB_USB_MUXING_SOFTCON_RESET _u(0x0) -#define USB_USB_MUXING_SOFTCON_BITS _u(0x00000008) -#define USB_USB_MUXING_SOFTCON_MSB _u(3) -#define USB_USB_MUXING_SOFTCON_LSB _u(3) -#define USB_USB_MUXING_SOFTCON_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_USB_MUXING_TO_DIGITAL_PAD -#define USB_USB_MUXING_TO_DIGITAL_PAD_RESET _u(0x0) -#define USB_USB_MUXING_TO_DIGITAL_PAD_BITS _u(0x00000004) -#define USB_USB_MUXING_TO_DIGITAL_PAD_MSB _u(2) -#define USB_USB_MUXING_TO_DIGITAL_PAD_LSB _u(2) -#define USB_USB_MUXING_TO_DIGITAL_PAD_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_USB_MUXING_TO_EXTPHY -#define USB_USB_MUXING_TO_EXTPHY_RESET _u(0x0) -#define USB_USB_MUXING_TO_EXTPHY_BITS _u(0x00000002) -#define USB_USB_MUXING_TO_EXTPHY_MSB _u(1) -#define USB_USB_MUXING_TO_EXTPHY_LSB _u(1) -#define USB_USB_MUXING_TO_EXTPHY_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_USB_MUXING_TO_PHY -#define USB_USB_MUXING_TO_PHY_RESET _u(0x0) -#define USB_USB_MUXING_TO_PHY_BITS _u(0x00000001) -#define USB_USB_MUXING_TO_PHY_MSB _u(0) -#define USB_USB_MUXING_TO_PHY_LSB _u(0) -#define USB_USB_MUXING_TO_PHY_ACCESS "RW" -// ============================================================================= -// Register : USB_USB_PWR -// Description : Overrides for the power signals in the event that the VBUS -// signals are not hooked up to GPIO. Set the value of the -// override and then the override enable so switch over to the -// override value. -#define USB_USB_PWR_OFFSET _u(0x00000078) -#define USB_USB_PWR_BITS _u(0x0000003f) -#define USB_USB_PWR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_USB_PWR_OVERCURR_DETECT_EN -#define USB_USB_PWR_OVERCURR_DETECT_EN_RESET _u(0x0) -#define USB_USB_PWR_OVERCURR_DETECT_EN_BITS _u(0x00000020) -#define USB_USB_PWR_OVERCURR_DETECT_EN_MSB _u(5) -#define USB_USB_PWR_OVERCURR_DETECT_EN_LSB _u(5) -#define USB_USB_PWR_OVERCURR_DETECT_EN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_USB_PWR_OVERCURR_DETECT -#define USB_USB_PWR_OVERCURR_DETECT_RESET _u(0x0) -#define USB_USB_PWR_OVERCURR_DETECT_BITS _u(0x00000010) -#define USB_USB_PWR_OVERCURR_DETECT_MSB _u(4) -#define USB_USB_PWR_OVERCURR_DETECT_LSB _u(4) -#define USB_USB_PWR_OVERCURR_DETECT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_USB_PWR_VBUS_DETECT_OVERRIDE_EN -#define USB_USB_PWR_VBUS_DETECT_OVERRIDE_EN_RESET _u(0x0) -#define USB_USB_PWR_VBUS_DETECT_OVERRIDE_EN_BITS _u(0x00000008) -#define USB_USB_PWR_VBUS_DETECT_OVERRIDE_EN_MSB _u(3) -#define USB_USB_PWR_VBUS_DETECT_OVERRIDE_EN_LSB _u(3) -#define USB_USB_PWR_VBUS_DETECT_OVERRIDE_EN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_USB_PWR_VBUS_DETECT -#define USB_USB_PWR_VBUS_DETECT_RESET _u(0x0) -#define USB_USB_PWR_VBUS_DETECT_BITS _u(0x00000004) -#define USB_USB_PWR_VBUS_DETECT_MSB _u(2) -#define USB_USB_PWR_VBUS_DETECT_LSB _u(2) -#define USB_USB_PWR_VBUS_DETECT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_USB_PWR_VBUS_EN_OVERRIDE_EN -#define USB_USB_PWR_VBUS_EN_OVERRIDE_EN_RESET _u(0x0) -#define USB_USB_PWR_VBUS_EN_OVERRIDE_EN_BITS _u(0x00000002) -#define USB_USB_PWR_VBUS_EN_OVERRIDE_EN_MSB _u(1) -#define USB_USB_PWR_VBUS_EN_OVERRIDE_EN_LSB _u(1) -#define USB_USB_PWR_VBUS_EN_OVERRIDE_EN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_USB_PWR_VBUS_EN -#define USB_USB_PWR_VBUS_EN_RESET _u(0x0) -#define USB_USB_PWR_VBUS_EN_BITS _u(0x00000001) -#define USB_USB_PWR_VBUS_EN_MSB _u(0) -#define USB_USB_PWR_VBUS_EN_LSB _u(0) -#define USB_USB_PWR_VBUS_EN_ACCESS "RW" -// ============================================================================= -// Register : USB_USBPHY_DIRECT -// Description : Note that most functions are driven directly from usb_fsls -// controller. This register allows more detailed control/status -// from the USB PHY. Useful for debug but not expected to be used -// in normal operation -// Use in conjunction with usbphy_direct_override register -#define USB_USBPHY_DIRECT_OFFSET _u(0x0000007c) -#define USB_USBPHY_DIRECT_BITS _u(0x007fff77) -#define USB_USBPHY_DIRECT_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_USBPHY_DIRECT_DM_OVV -// Description : Status bit from USB PHY -#define USB_USBPHY_DIRECT_DM_OVV_RESET _u(0x0) -#define USB_USBPHY_DIRECT_DM_OVV_BITS _u(0x00400000) -#define USB_USBPHY_DIRECT_DM_OVV_MSB _u(22) -#define USB_USBPHY_DIRECT_DM_OVV_LSB _u(22) -#define USB_USBPHY_DIRECT_DM_OVV_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_USBPHY_DIRECT_DP_OVV -// Description : Status bit from USB PHY -#define USB_USBPHY_DIRECT_DP_OVV_RESET _u(0x0) -#define USB_USBPHY_DIRECT_DP_OVV_BITS _u(0x00200000) -#define USB_USBPHY_DIRECT_DP_OVV_MSB _u(21) -#define USB_USBPHY_DIRECT_DP_OVV_LSB _u(21) -#define USB_USBPHY_DIRECT_DP_OVV_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_USBPHY_DIRECT_DM_OVCN -// Description : Status bit from USB PHY -#define USB_USBPHY_DIRECT_DM_OVCN_RESET _u(0x0) -#define USB_USBPHY_DIRECT_DM_OVCN_BITS _u(0x00100000) -#define USB_USBPHY_DIRECT_DM_OVCN_MSB _u(20) -#define USB_USBPHY_DIRECT_DM_OVCN_LSB _u(20) -#define USB_USBPHY_DIRECT_DM_OVCN_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_USBPHY_DIRECT_DP_OVCN -// Description : Status bit from USB PHY -#define USB_USBPHY_DIRECT_DP_OVCN_RESET _u(0x0) -#define USB_USBPHY_DIRECT_DP_OVCN_BITS _u(0x00080000) -#define USB_USBPHY_DIRECT_DP_OVCN_MSB _u(19) -#define USB_USBPHY_DIRECT_DP_OVCN_LSB _u(19) -#define USB_USBPHY_DIRECT_DP_OVCN_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_USBPHY_DIRECT_RX_DM -// Description : Status bit from USB PHY -// DPM pin state -#define USB_USBPHY_DIRECT_RX_DM_RESET _u(0x0) -#define USB_USBPHY_DIRECT_RX_DM_BITS _u(0x00040000) -#define USB_USBPHY_DIRECT_RX_DM_MSB _u(18) -#define USB_USBPHY_DIRECT_RX_DM_LSB _u(18) -#define USB_USBPHY_DIRECT_RX_DM_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_USBPHY_DIRECT_RX_DP -// Description : Status bit from USB PHY -// DPP pin state -#define USB_USBPHY_DIRECT_RX_DP_RESET _u(0x0) -#define USB_USBPHY_DIRECT_RX_DP_BITS _u(0x00020000) -#define USB_USBPHY_DIRECT_RX_DP_MSB _u(17) -#define USB_USBPHY_DIRECT_RX_DP_LSB _u(17) -#define USB_USBPHY_DIRECT_RX_DP_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_USBPHY_DIRECT_RX_DD -// Description : Status bit from USB PHY -// RX Diff data -#define USB_USBPHY_DIRECT_RX_DD_RESET _u(0x0) -#define USB_USBPHY_DIRECT_RX_DD_BITS _u(0x00010000) -#define USB_USBPHY_DIRECT_RX_DD_MSB _u(16) -#define USB_USBPHY_DIRECT_RX_DD_LSB _u(16) -#define USB_USBPHY_DIRECT_RX_DD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_USBPHY_DIRECT_TX_DIFFMODE -#define USB_USBPHY_DIRECT_TX_DIFFMODE_RESET _u(0x0) -#define USB_USBPHY_DIRECT_TX_DIFFMODE_BITS _u(0x00008000) -#define USB_USBPHY_DIRECT_TX_DIFFMODE_MSB _u(15) -#define USB_USBPHY_DIRECT_TX_DIFFMODE_LSB _u(15) -#define USB_USBPHY_DIRECT_TX_DIFFMODE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_USBPHY_DIRECT_TX_FSSLEW -#define USB_USBPHY_DIRECT_TX_FSSLEW_RESET _u(0x0) -#define USB_USBPHY_DIRECT_TX_FSSLEW_BITS _u(0x00004000) -#define USB_USBPHY_DIRECT_TX_FSSLEW_MSB _u(14) -#define USB_USBPHY_DIRECT_TX_FSSLEW_LSB _u(14) -#define USB_USBPHY_DIRECT_TX_FSSLEW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_USBPHY_DIRECT_TX_PD -#define USB_USBPHY_DIRECT_TX_PD_RESET _u(0x0) -#define USB_USBPHY_DIRECT_TX_PD_BITS _u(0x00002000) -#define USB_USBPHY_DIRECT_TX_PD_MSB _u(13) -#define USB_USBPHY_DIRECT_TX_PD_LSB _u(13) -#define USB_USBPHY_DIRECT_TX_PD_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_USBPHY_DIRECT_RX_PD -#define USB_USBPHY_DIRECT_RX_PD_RESET _u(0x0) -#define USB_USBPHY_DIRECT_RX_PD_BITS _u(0x00001000) -#define USB_USBPHY_DIRECT_RX_PD_MSB _u(12) -#define USB_USBPHY_DIRECT_RX_PD_LSB _u(12) -#define USB_USBPHY_DIRECT_RX_PD_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_USBPHY_DIRECT_TX_DM -// Description : Value to drive to USB PHY when override enable is set (which -// will override the default value or value driven from USB -// controller -// TX_SEMODE=0, Ignored -// TX_SEMODE=1, Drives DPM only. TX_DM_OE=1 to enable drive. -// DPM=TX_DM -#define USB_USBPHY_DIRECT_TX_DM_RESET _u(0x0) -#define USB_USBPHY_DIRECT_TX_DM_BITS _u(0x00000800) -#define USB_USBPHY_DIRECT_TX_DM_MSB _u(11) -#define USB_USBPHY_DIRECT_TX_DM_LSB _u(11) -#define USB_USBPHY_DIRECT_TX_DM_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_USBPHY_DIRECT_TX_DP -// Description : Value to drive to USB PHY when override enable is set (which -// will override the default value or value driven from USB -// controller -// TX_SEMODE=0, Drives DPP/DPM diff pair. TX_DP_OE=1 to enable -// drive. DPP=TX_DP, DPM=~TX_DP -// TX_SEMODE=1, Drives DPP only. TX_DP_OE=1 to enable drive. -// DPP=TX_DP -#define USB_USBPHY_DIRECT_TX_DP_RESET _u(0x0) -#define USB_USBPHY_DIRECT_TX_DP_BITS _u(0x00000400) -#define USB_USBPHY_DIRECT_TX_DP_MSB _u(10) -#define USB_USBPHY_DIRECT_TX_DP_LSB _u(10) -#define USB_USBPHY_DIRECT_TX_DP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_USBPHY_DIRECT_TX_DM_OE -// Description : Value to drive to USB PHY when override enable is set (which -// will override the default value or value driven from USB -// controller -// TX_SEMODE=0, Ignored. -// TX_SEMODE=1, OE for DPM only. 0 - DPM in Hi-Z state; 1 - DPM -// driving -#define USB_USBPHY_DIRECT_TX_DM_OE_RESET _u(0x0) -#define USB_USBPHY_DIRECT_TX_DM_OE_BITS _u(0x00000200) -#define USB_USBPHY_DIRECT_TX_DM_OE_MSB _u(9) -#define USB_USBPHY_DIRECT_TX_DM_OE_LSB _u(9) -#define USB_USBPHY_DIRECT_TX_DM_OE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_USBPHY_DIRECT_TX_DP_OE -// Description : Value to drive to USB PHY when override enable is set (which -// will override the default value or value driven from USB -// controller -// TX_SEMODE=0, OE for DPP/DPM diff pair. 0 - DPP/DPM in Hi-Z -// state; 1 - DPP/DPM driving -// TX_SEMODE=1, OE for DPP only. 0 - DPP in Hi-Z state; 1 - DPP -// driving -#define USB_USBPHY_DIRECT_TX_DP_OE_RESET _u(0x0) -#define USB_USBPHY_DIRECT_TX_DP_OE_BITS _u(0x00000100) -#define USB_USBPHY_DIRECT_TX_DP_OE_MSB _u(8) -#define USB_USBPHY_DIRECT_TX_DP_OE_LSB _u(8) -#define USB_USBPHY_DIRECT_TX_DP_OE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_USBPHY_DIRECT_DM_PULLDN_EN -// Description : Value to drive to USB PHY when override enable is set (which -// will override the default value or value driven from USB -// controller -// 1 - Enable Rpd on DPM -#define USB_USBPHY_DIRECT_DM_PULLDN_EN_RESET _u(0x0) -#define USB_USBPHY_DIRECT_DM_PULLDN_EN_BITS _u(0x00000040) -#define USB_USBPHY_DIRECT_DM_PULLDN_EN_MSB _u(6) -#define USB_USBPHY_DIRECT_DM_PULLDN_EN_LSB _u(6) -#define USB_USBPHY_DIRECT_DM_PULLDN_EN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_USBPHY_DIRECT_DM_PULLUP_EN -// Description : Value to drive to USB PHY when override enable is set (which -// will override the default value or value driven from USB -// controller -// 1 - Enable Rpu on DPM -#define USB_USBPHY_DIRECT_DM_PULLUP_EN_RESET _u(0x0) -#define USB_USBPHY_DIRECT_DM_PULLUP_EN_BITS _u(0x00000020) -#define USB_USBPHY_DIRECT_DM_PULLUP_EN_MSB _u(5) -#define USB_USBPHY_DIRECT_DM_PULLUP_EN_LSB _u(5) -#define USB_USBPHY_DIRECT_DM_PULLUP_EN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_USBPHY_DIRECT_DM_PULLUP_HISEL -// Description : when dm_pullup_en is set high, this enables second resistor. 0 -// - Pull = Rpu2; 1 - Pull = Rpu1 + Rpu2 -#define USB_USBPHY_DIRECT_DM_PULLUP_HISEL_RESET _u(0x0) -#define USB_USBPHY_DIRECT_DM_PULLUP_HISEL_BITS _u(0x00000010) -#define USB_USBPHY_DIRECT_DM_PULLUP_HISEL_MSB _u(4) -#define USB_USBPHY_DIRECT_DM_PULLUP_HISEL_LSB _u(4) -#define USB_USBPHY_DIRECT_DM_PULLUP_HISEL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_USBPHY_DIRECT_DP_PULLDN_EN -// Description : Value to drive to USB PHY when override enable is set (which -// will override the default value or value driven from USB -// controller -// 1 - Enable Rpd on DPP -#define USB_USBPHY_DIRECT_DP_PULLDN_EN_RESET _u(0x0) -#define USB_USBPHY_DIRECT_DP_PULLDN_EN_BITS _u(0x00000004) -#define USB_USBPHY_DIRECT_DP_PULLDN_EN_MSB _u(2) -#define USB_USBPHY_DIRECT_DP_PULLDN_EN_LSB _u(2) -#define USB_USBPHY_DIRECT_DP_PULLDN_EN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_USBPHY_DIRECT_DP_PULLUP_EN -// Description : Value to drive to USB PHY when override enable is set (which -// will override the default value or value driven from USB -// controller -#define USB_USBPHY_DIRECT_DP_PULLUP_EN_RESET _u(0x0) -#define USB_USBPHY_DIRECT_DP_PULLUP_EN_BITS _u(0x00000002) -#define USB_USBPHY_DIRECT_DP_PULLUP_EN_MSB _u(1) -#define USB_USBPHY_DIRECT_DP_PULLUP_EN_LSB _u(1) -#define USB_USBPHY_DIRECT_DP_PULLUP_EN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_USBPHY_DIRECT_DP_PULLUP_HISEL -// Description : when dp_pullup_en is set high, this enables second resistor. 0 -// - Pull = Rpu2; 1 - Pull = Rpu1 + Rpu2 -#define USB_USBPHY_DIRECT_DP_PULLUP_HISEL_RESET _u(0x0) -#define USB_USBPHY_DIRECT_DP_PULLUP_HISEL_BITS _u(0x00000001) -#define USB_USBPHY_DIRECT_DP_PULLUP_HISEL_MSB _u(0) -#define USB_USBPHY_DIRECT_DP_PULLUP_HISEL_LSB _u(0) -#define USB_USBPHY_DIRECT_DP_PULLUP_HISEL_ACCESS "RW" -// ============================================================================= -// Register : USB_USBPHY_DIRECT_OVERRIDE -#define USB_USBPHY_DIRECT_OVERRIDE_OFFSET _u(0x00000080) -#define USB_USBPHY_DIRECT_OVERRIDE_BITS _u(0x00009fff) -#define USB_USBPHY_DIRECT_OVERRIDE_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_USBPHY_DIRECT_OVERRIDE_TX_DIFFMODE_OVERRIDE_EN -#define USB_USBPHY_DIRECT_OVERRIDE_TX_DIFFMODE_OVERRIDE_EN_RESET _u(0x0) -#define USB_USBPHY_DIRECT_OVERRIDE_TX_DIFFMODE_OVERRIDE_EN_BITS _u(0x00008000) -#define USB_USBPHY_DIRECT_OVERRIDE_TX_DIFFMODE_OVERRIDE_EN_MSB _u(15) -#define USB_USBPHY_DIRECT_OVERRIDE_TX_DIFFMODE_OVERRIDE_EN_LSB _u(15) -#define USB_USBPHY_DIRECT_OVERRIDE_TX_DIFFMODE_OVERRIDE_EN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_OVERRIDE_EN -#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_OVERRIDE_EN_RESET _u(0x0) -#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_OVERRIDE_EN_BITS _u(0x00001000) -#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_OVERRIDE_EN_MSB _u(12) -#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_OVERRIDE_EN_LSB _u(12) -#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_OVERRIDE_EN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_USBPHY_DIRECT_OVERRIDE_TX_FSSLEW_OVERRIDE_EN -#define USB_USBPHY_DIRECT_OVERRIDE_TX_FSSLEW_OVERRIDE_EN_RESET _u(0x0) -#define USB_USBPHY_DIRECT_OVERRIDE_TX_FSSLEW_OVERRIDE_EN_BITS _u(0x00000800) -#define USB_USBPHY_DIRECT_OVERRIDE_TX_FSSLEW_OVERRIDE_EN_MSB _u(11) -#define USB_USBPHY_DIRECT_OVERRIDE_TX_FSSLEW_OVERRIDE_EN_LSB _u(11) -#define USB_USBPHY_DIRECT_OVERRIDE_TX_FSSLEW_OVERRIDE_EN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_USBPHY_DIRECT_OVERRIDE_TX_PD_OVERRIDE_EN -#define USB_USBPHY_DIRECT_OVERRIDE_TX_PD_OVERRIDE_EN_RESET _u(0x0) -#define USB_USBPHY_DIRECT_OVERRIDE_TX_PD_OVERRIDE_EN_BITS _u(0x00000400) -#define USB_USBPHY_DIRECT_OVERRIDE_TX_PD_OVERRIDE_EN_MSB _u(10) -#define USB_USBPHY_DIRECT_OVERRIDE_TX_PD_OVERRIDE_EN_LSB _u(10) -#define USB_USBPHY_DIRECT_OVERRIDE_TX_PD_OVERRIDE_EN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_USBPHY_DIRECT_OVERRIDE_RX_PD_OVERRIDE_EN -#define USB_USBPHY_DIRECT_OVERRIDE_RX_PD_OVERRIDE_EN_RESET _u(0x0) -#define USB_USBPHY_DIRECT_OVERRIDE_RX_PD_OVERRIDE_EN_BITS _u(0x00000200) -#define USB_USBPHY_DIRECT_OVERRIDE_RX_PD_OVERRIDE_EN_MSB _u(9) -#define USB_USBPHY_DIRECT_OVERRIDE_RX_PD_OVERRIDE_EN_LSB _u(9) -#define USB_USBPHY_DIRECT_OVERRIDE_RX_PD_OVERRIDE_EN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OVERRIDE_EN -// Description : Override default value or value driven from USB Controller to -// PHY -#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OVERRIDE_EN_RESET _u(0x0) -#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OVERRIDE_EN_BITS _u(0x00000100) -#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OVERRIDE_EN_MSB _u(8) -#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OVERRIDE_EN_LSB _u(8) -#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OVERRIDE_EN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OVERRIDE_EN -// Description : Override default value or value driven from USB Controller to -// PHY -#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OVERRIDE_EN_RESET _u(0x0) -#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OVERRIDE_EN_BITS _u(0x00000080) -#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OVERRIDE_EN_MSB _u(7) -#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OVERRIDE_EN_LSB _u(7) -#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OVERRIDE_EN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OE_OVERRIDE_EN -// Description : Override default value or value driven from USB Controller to -// PHY -#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OE_OVERRIDE_EN_RESET _u(0x0) -#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OE_OVERRIDE_EN_BITS _u(0x00000040) -#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OE_OVERRIDE_EN_MSB _u(6) -#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OE_OVERRIDE_EN_LSB _u(6) -#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OE_OVERRIDE_EN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OE_OVERRIDE_EN -// Description : Override default value or value driven from USB Controller to -// PHY -#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OE_OVERRIDE_EN_RESET _u(0x0) -#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OE_OVERRIDE_EN_BITS _u(0x00000020) -#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OE_OVERRIDE_EN_MSB _u(5) -#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OE_OVERRIDE_EN_LSB _u(5) -#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OE_OVERRIDE_EN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_USBPHY_DIRECT_OVERRIDE_DM_PULLDN_EN_OVERRIDE_EN -// Description : Override default value or value driven from USB Controller to -// PHY -#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLDN_EN_OVERRIDE_EN_RESET _u(0x0) -#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLDN_EN_OVERRIDE_EN_BITS _u(0x00000010) -#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLDN_EN_OVERRIDE_EN_MSB _u(4) -#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLDN_EN_OVERRIDE_EN_LSB _u(4) -#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLDN_EN_OVERRIDE_EN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_USBPHY_DIRECT_OVERRIDE_DP_PULLDN_EN_OVERRIDE_EN -// Description : Override default value or value driven from USB Controller to -// PHY -#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLDN_EN_OVERRIDE_EN_RESET _u(0x0) -#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLDN_EN_OVERRIDE_EN_BITS _u(0x00000008) -#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLDN_EN_OVERRIDE_EN_MSB _u(3) -#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLDN_EN_OVERRIDE_EN_LSB _u(3) -#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLDN_EN_OVERRIDE_EN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_EN_OVERRIDE_EN -// Description : Override default value or value driven from USB Controller to -// PHY -#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_EN_OVERRIDE_EN_RESET _u(0x0) -#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_EN_OVERRIDE_EN_BITS _u(0x00000004) -#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_EN_OVERRIDE_EN_MSB _u(2) -#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_EN_OVERRIDE_EN_LSB _u(2) -#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_EN_OVERRIDE_EN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_HISEL_OVERRIDE_EN -#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_HISEL_OVERRIDE_EN_RESET _u(0x0) -#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_HISEL_OVERRIDE_EN_BITS _u(0x00000002) -#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_HISEL_OVERRIDE_EN_MSB _u(1) -#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_HISEL_OVERRIDE_EN_LSB _u(1) -#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_HISEL_OVERRIDE_EN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_HISEL_OVERRIDE_EN -#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_HISEL_OVERRIDE_EN_RESET _u(0x0) -#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_HISEL_OVERRIDE_EN_BITS _u(0x00000001) -#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_HISEL_OVERRIDE_EN_MSB _u(0) -#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_HISEL_OVERRIDE_EN_LSB _u(0) -#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_HISEL_OVERRIDE_EN_ACCESS "RW" -// ============================================================================= -// Register : USB_USBPHY_TRIM -// Description : Note that most functions are driven directly from usb_fsls -// controller. This register allows more detailed control/status -// from the USB PHY. Useful for debug but not expected to be used -// in normal operation -#define USB_USBPHY_TRIM_OFFSET _u(0x00000084) -#define USB_USBPHY_TRIM_BITS _u(0x00001f1f) -#define USB_USBPHY_TRIM_RESET _u(0x00001f1f) -// ----------------------------------------------------------------------------- -// Field : USB_USBPHY_TRIM_DM_PULLDN_TRIM -// Description : Value to drive to USB PHY -// DM pulldown resistor trim control -// Experimental data suggests that the reset value will work, but -// this register allows adjustment if required -#define USB_USBPHY_TRIM_DM_PULLDN_TRIM_RESET _u(0x1f) -#define USB_USBPHY_TRIM_DM_PULLDN_TRIM_BITS _u(0x00001f00) -#define USB_USBPHY_TRIM_DM_PULLDN_TRIM_MSB _u(12) -#define USB_USBPHY_TRIM_DM_PULLDN_TRIM_LSB _u(8) -#define USB_USBPHY_TRIM_DM_PULLDN_TRIM_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_USBPHY_TRIM_DP_PULLDN_TRIM -// Description : Value to drive to USB PHY -// DP pulldown resistor trim control -// Experimental data suggests that the reset value will work, but -// this register allows adjustment if required -#define USB_USBPHY_TRIM_DP_PULLDN_TRIM_RESET _u(0x1f) -#define USB_USBPHY_TRIM_DP_PULLDN_TRIM_BITS _u(0x0000001f) -#define USB_USBPHY_TRIM_DP_PULLDN_TRIM_MSB _u(4) -#define USB_USBPHY_TRIM_DP_PULLDN_TRIM_LSB _u(0) -#define USB_USBPHY_TRIM_DP_PULLDN_TRIM_ACCESS "RW" -// ============================================================================= -// Register : USB_INTR -// Description : Raw Interrupts -#define USB_INTR_OFFSET _u(0x0000008c) -#define USB_INTR_BITS _u(0x000fffff) -#define USB_INTR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_INTR_EP_STALL_NAK -// Description : Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by -// clearing all bits in EP_STATUS_STALL_NAK. -#define USB_INTR_EP_STALL_NAK_RESET _u(0x0) -#define USB_INTR_EP_STALL_NAK_BITS _u(0x00080000) -#define USB_INTR_EP_STALL_NAK_MSB _u(19) -#define USB_INTR_EP_STALL_NAK_LSB _u(19) -#define USB_INTR_EP_STALL_NAK_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_INTR_ABORT_DONE -// Description : Raised when any bit in ABORT_DONE is set. Clear by clearing all -// bits in ABORT_DONE. -#define USB_INTR_ABORT_DONE_RESET _u(0x0) -#define USB_INTR_ABORT_DONE_BITS _u(0x00040000) -#define USB_INTR_ABORT_DONE_MSB _u(18) -#define USB_INTR_ABORT_DONE_LSB _u(18) -#define USB_INTR_ABORT_DONE_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_INTR_DEV_SOF -// Description : Set every time the device receives a SOF (Start of Frame) -// packet. Cleared by reading SOF_RD -#define USB_INTR_DEV_SOF_RESET _u(0x0) -#define USB_INTR_DEV_SOF_BITS _u(0x00020000) -#define USB_INTR_DEV_SOF_MSB _u(17) -#define USB_INTR_DEV_SOF_LSB _u(17) -#define USB_INTR_DEV_SOF_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_INTR_SETUP_REQ -// Description : Device. Source: SIE_STATUS.SETUP_REC -#define USB_INTR_SETUP_REQ_RESET _u(0x0) -#define USB_INTR_SETUP_REQ_BITS _u(0x00010000) -#define USB_INTR_SETUP_REQ_MSB _u(16) -#define USB_INTR_SETUP_REQ_LSB _u(16) -#define USB_INTR_SETUP_REQ_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_INTR_DEV_RESUME_FROM_HOST -// Description : Set when the device receives a resume from the host. Cleared by -// writing to SIE_STATUS.RESUME_REMOTE -#define USB_INTR_DEV_RESUME_FROM_HOST_RESET _u(0x0) -#define USB_INTR_DEV_RESUME_FROM_HOST_BITS _u(0x00008000) -#define USB_INTR_DEV_RESUME_FROM_HOST_MSB _u(15) -#define USB_INTR_DEV_RESUME_FROM_HOST_LSB _u(15) -#define USB_INTR_DEV_RESUME_FROM_HOST_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_INTR_DEV_SUSPEND -// Description : Set when the device suspend state changes. Cleared by writing -// to SIE_STATUS.SUSPENDED -#define USB_INTR_DEV_SUSPEND_RESET _u(0x0) -#define USB_INTR_DEV_SUSPEND_BITS _u(0x00004000) -#define USB_INTR_DEV_SUSPEND_MSB _u(14) -#define USB_INTR_DEV_SUSPEND_LSB _u(14) -#define USB_INTR_DEV_SUSPEND_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_INTR_DEV_CONN_DIS -// Description : Set when the device connection state changes. Cleared by -// writing to SIE_STATUS.CONNECTED -#define USB_INTR_DEV_CONN_DIS_RESET _u(0x0) -#define USB_INTR_DEV_CONN_DIS_BITS _u(0x00002000) -#define USB_INTR_DEV_CONN_DIS_MSB _u(13) -#define USB_INTR_DEV_CONN_DIS_LSB _u(13) -#define USB_INTR_DEV_CONN_DIS_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_INTR_BUS_RESET -// Description : Source: SIE_STATUS.BUS_RESET -#define USB_INTR_BUS_RESET_RESET _u(0x0) -#define USB_INTR_BUS_RESET_BITS _u(0x00001000) -#define USB_INTR_BUS_RESET_MSB _u(12) -#define USB_INTR_BUS_RESET_LSB _u(12) -#define USB_INTR_BUS_RESET_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_INTR_VBUS_DETECT -// Description : Source: SIE_STATUS.VBUS_DETECT -#define USB_INTR_VBUS_DETECT_RESET _u(0x0) -#define USB_INTR_VBUS_DETECT_BITS _u(0x00000800) -#define USB_INTR_VBUS_DETECT_MSB _u(11) -#define USB_INTR_VBUS_DETECT_LSB _u(11) -#define USB_INTR_VBUS_DETECT_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_INTR_STALL -// Description : Source: SIE_STATUS.STALL_REC -#define USB_INTR_STALL_RESET _u(0x0) -#define USB_INTR_STALL_BITS _u(0x00000400) -#define USB_INTR_STALL_MSB _u(10) -#define USB_INTR_STALL_LSB _u(10) -#define USB_INTR_STALL_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_INTR_ERROR_CRC -// Description : Source: SIE_STATUS.CRC_ERROR -#define USB_INTR_ERROR_CRC_RESET _u(0x0) -#define USB_INTR_ERROR_CRC_BITS _u(0x00000200) -#define USB_INTR_ERROR_CRC_MSB _u(9) -#define USB_INTR_ERROR_CRC_LSB _u(9) -#define USB_INTR_ERROR_CRC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_INTR_ERROR_BIT_STUFF -// Description : Source: SIE_STATUS.BIT_STUFF_ERROR -#define USB_INTR_ERROR_BIT_STUFF_RESET _u(0x0) -#define USB_INTR_ERROR_BIT_STUFF_BITS _u(0x00000100) -#define USB_INTR_ERROR_BIT_STUFF_MSB _u(8) -#define USB_INTR_ERROR_BIT_STUFF_LSB _u(8) -#define USB_INTR_ERROR_BIT_STUFF_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_INTR_ERROR_RX_OVERFLOW -// Description : Source: SIE_STATUS.RX_OVERFLOW -#define USB_INTR_ERROR_RX_OVERFLOW_RESET _u(0x0) -#define USB_INTR_ERROR_RX_OVERFLOW_BITS _u(0x00000080) -#define USB_INTR_ERROR_RX_OVERFLOW_MSB _u(7) -#define USB_INTR_ERROR_RX_OVERFLOW_LSB _u(7) -#define USB_INTR_ERROR_RX_OVERFLOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_INTR_ERROR_RX_TIMEOUT -// Description : Source: SIE_STATUS.RX_TIMEOUT -#define USB_INTR_ERROR_RX_TIMEOUT_RESET _u(0x0) -#define USB_INTR_ERROR_RX_TIMEOUT_BITS _u(0x00000040) -#define USB_INTR_ERROR_RX_TIMEOUT_MSB _u(6) -#define USB_INTR_ERROR_RX_TIMEOUT_LSB _u(6) -#define USB_INTR_ERROR_RX_TIMEOUT_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_INTR_ERROR_DATA_SEQ -// Description : Source: SIE_STATUS.DATA_SEQ_ERROR -#define USB_INTR_ERROR_DATA_SEQ_RESET _u(0x0) -#define USB_INTR_ERROR_DATA_SEQ_BITS _u(0x00000020) -#define USB_INTR_ERROR_DATA_SEQ_MSB _u(5) -#define USB_INTR_ERROR_DATA_SEQ_LSB _u(5) -#define USB_INTR_ERROR_DATA_SEQ_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_INTR_BUFF_STATUS -// Description : Raised when any bit in BUFF_STATUS is set. Clear by clearing -// all bits in BUFF_STATUS. -#define USB_INTR_BUFF_STATUS_RESET _u(0x0) -#define USB_INTR_BUFF_STATUS_BITS _u(0x00000010) -#define USB_INTR_BUFF_STATUS_MSB _u(4) -#define USB_INTR_BUFF_STATUS_LSB _u(4) -#define USB_INTR_BUFF_STATUS_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_INTR_TRANS_COMPLETE -// Description : Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by -// writing to this bit. -#define USB_INTR_TRANS_COMPLETE_RESET _u(0x0) -#define USB_INTR_TRANS_COMPLETE_BITS _u(0x00000008) -#define USB_INTR_TRANS_COMPLETE_MSB _u(3) -#define USB_INTR_TRANS_COMPLETE_LSB _u(3) -#define USB_INTR_TRANS_COMPLETE_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_INTR_HOST_SOF -// Description : Host: raised every time the host sends a SOF (Start of Frame). -// Cleared by reading SOF_RD -#define USB_INTR_HOST_SOF_RESET _u(0x0) -#define USB_INTR_HOST_SOF_BITS _u(0x00000004) -#define USB_INTR_HOST_SOF_MSB _u(2) -#define USB_INTR_HOST_SOF_LSB _u(2) -#define USB_INTR_HOST_SOF_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_INTR_HOST_RESUME -// Description : Host: raised when a device wakes up the host. Cleared by -// writing to SIE_STATUS.RESUME_REMOTE -#define USB_INTR_HOST_RESUME_RESET _u(0x0) -#define USB_INTR_HOST_RESUME_BITS _u(0x00000002) -#define USB_INTR_HOST_RESUME_MSB _u(1) -#define USB_INTR_HOST_RESUME_LSB _u(1) -#define USB_INTR_HOST_RESUME_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_INTR_HOST_CONN_DIS -// Description : Host: raised when a device is connected or disconnected (i.e. -// when SIE_STATUS.SPEED changes). Cleared by writing to -// SIE_STATUS.SPEED -#define USB_INTR_HOST_CONN_DIS_RESET _u(0x0) -#define USB_INTR_HOST_CONN_DIS_BITS _u(0x00000001) -#define USB_INTR_HOST_CONN_DIS_MSB _u(0) -#define USB_INTR_HOST_CONN_DIS_LSB _u(0) -#define USB_INTR_HOST_CONN_DIS_ACCESS "RO" -// ============================================================================= -// Register : USB_INTE -// Description : Interrupt Enable -#define USB_INTE_OFFSET _u(0x00000090) -#define USB_INTE_BITS _u(0x000fffff) -#define USB_INTE_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_INTE_EP_STALL_NAK -// Description : Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by -// clearing all bits in EP_STATUS_STALL_NAK. -#define USB_INTE_EP_STALL_NAK_RESET _u(0x0) -#define USB_INTE_EP_STALL_NAK_BITS _u(0x00080000) -#define USB_INTE_EP_STALL_NAK_MSB _u(19) -#define USB_INTE_EP_STALL_NAK_LSB _u(19) -#define USB_INTE_EP_STALL_NAK_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_INTE_ABORT_DONE -// Description : Raised when any bit in ABORT_DONE is set. Clear by clearing all -// bits in ABORT_DONE. -#define USB_INTE_ABORT_DONE_RESET _u(0x0) -#define USB_INTE_ABORT_DONE_BITS _u(0x00040000) -#define USB_INTE_ABORT_DONE_MSB _u(18) -#define USB_INTE_ABORT_DONE_LSB _u(18) -#define USB_INTE_ABORT_DONE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_INTE_DEV_SOF -// Description : Set every time the device receives a SOF (Start of Frame) -// packet. Cleared by reading SOF_RD -#define USB_INTE_DEV_SOF_RESET _u(0x0) -#define USB_INTE_DEV_SOF_BITS _u(0x00020000) -#define USB_INTE_DEV_SOF_MSB _u(17) -#define USB_INTE_DEV_SOF_LSB _u(17) -#define USB_INTE_DEV_SOF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_INTE_SETUP_REQ -// Description : Device. Source: SIE_STATUS.SETUP_REC -#define USB_INTE_SETUP_REQ_RESET _u(0x0) -#define USB_INTE_SETUP_REQ_BITS _u(0x00010000) -#define USB_INTE_SETUP_REQ_MSB _u(16) -#define USB_INTE_SETUP_REQ_LSB _u(16) -#define USB_INTE_SETUP_REQ_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_INTE_DEV_RESUME_FROM_HOST -// Description : Set when the device receives a resume from the host. Cleared by -// writing to SIE_STATUS.RESUME_REMOTE -#define USB_INTE_DEV_RESUME_FROM_HOST_RESET _u(0x0) -#define USB_INTE_DEV_RESUME_FROM_HOST_BITS _u(0x00008000) -#define USB_INTE_DEV_RESUME_FROM_HOST_MSB _u(15) -#define USB_INTE_DEV_RESUME_FROM_HOST_LSB _u(15) -#define USB_INTE_DEV_RESUME_FROM_HOST_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_INTE_DEV_SUSPEND -// Description : Set when the device suspend state changes. Cleared by writing -// to SIE_STATUS.SUSPENDED -#define USB_INTE_DEV_SUSPEND_RESET _u(0x0) -#define USB_INTE_DEV_SUSPEND_BITS _u(0x00004000) -#define USB_INTE_DEV_SUSPEND_MSB _u(14) -#define USB_INTE_DEV_SUSPEND_LSB _u(14) -#define USB_INTE_DEV_SUSPEND_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_INTE_DEV_CONN_DIS -// Description : Set when the device connection state changes. Cleared by -// writing to SIE_STATUS.CONNECTED -#define USB_INTE_DEV_CONN_DIS_RESET _u(0x0) -#define USB_INTE_DEV_CONN_DIS_BITS _u(0x00002000) -#define USB_INTE_DEV_CONN_DIS_MSB _u(13) -#define USB_INTE_DEV_CONN_DIS_LSB _u(13) -#define USB_INTE_DEV_CONN_DIS_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_INTE_BUS_RESET -// Description : Source: SIE_STATUS.BUS_RESET -#define USB_INTE_BUS_RESET_RESET _u(0x0) -#define USB_INTE_BUS_RESET_BITS _u(0x00001000) -#define USB_INTE_BUS_RESET_MSB _u(12) -#define USB_INTE_BUS_RESET_LSB _u(12) -#define USB_INTE_BUS_RESET_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_INTE_VBUS_DETECT -// Description : Source: SIE_STATUS.VBUS_DETECT -#define USB_INTE_VBUS_DETECT_RESET _u(0x0) -#define USB_INTE_VBUS_DETECT_BITS _u(0x00000800) -#define USB_INTE_VBUS_DETECT_MSB _u(11) -#define USB_INTE_VBUS_DETECT_LSB _u(11) -#define USB_INTE_VBUS_DETECT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_INTE_STALL -// Description : Source: SIE_STATUS.STALL_REC -#define USB_INTE_STALL_RESET _u(0x0) -#define USB_INTE_STALL_BITS _u(0x00000400) -#define USB_INTE_STALL_MSB _u(10) -#define USB_INTE_STALL_LSB _u(10) -#define USB_INTE_STALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_INTE_ERROR_CRC -// Description : Source: SIE_STATUS.CRC_ERROR -#define USB_INTE_ERROR_CRC_RESET _u(0x0) -#define USB_INTE_ERROR_CRC_BITS _u(0x00000200) -#define USB_INTE_ERROR_CRC_MSB _u(9) -#define USB_INTE_ERROR_CRC_LSB _u(9) -#define USB_INTE_ERROR_CRC_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_INTE_ERROR_BIT_STUFF -// Description : Source: SIE_STATUS.BIT_STUFF_ERROR -#define USB_INTE_ERROR_BIT_STUFF_RESET _u(0x0) -#define USB_INTE_ERROR_BIT_STUFF_BITS _u(0x00000100) -#define USB_INTE_ERROR_BIT_STUFF_MSB _u(8) -#define USB_INTE_ERROR_BIT_STUFF_LSB _u(8) -#define USB_INTE_ERROR_BIT_STUFF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_INTE_ERROR_RX_OVERFLOW -// Description : Source: SIE_STATUS.RX_OVERFLOW -#define USB_INTE_ERROR_RX_OVERFLOW_RESET _u(0x0) -#define USB_INTE_ERROR_RX_OVERFLOW_BITS _u(0x00000080) -#define USB_INTE_ERROR_RX_OVERFLOW_MSB _u(7) -#define USB_INTE_ERROR_RX_OVERFLOW_LSB _u(7) -#define USB_INTE_ERROR_RX_OVERFLOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_INTE_ERROR_RX_TIMEOUT -// Description : Source: SIE_STATUS.RX_TIMEOUT -#define USB_INTE_ERROR_RX_TIMEOUT_RESET _u(0x0) -#define USB_INTE_ERROR_RX_TIMEOUT_BITS _u(0x00000040) -#define USB_INTE_ERROR_RX_TIMEOUT_MSB _u(6) -#define USB_INTE_ERROR_RX_TIMEOUT_LSB _u(6) -#define USB_INTE_ERROR_RX_TIMEOUT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_INTE_ERROR_DATA_SEQ -// Description : Source: SIE_STATUS.DATA_SEQ_ERROR -#define USB_INTE_ERROR_DATA_SEQ_RESET _u(0x0) -#define USB_INTE_ERROR_DATA_SEQ_BITS _u(0x00000020) -#define USB_INTE_ERROR_DATA_SEQ_MSB _u(5) -#define USB_INTE_ERROR_DATA_SEQ_LSB _u(5) -#define USB_INTE_ERROR_DATA_SEQ_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_INTE_BUFF_STATUS -// Description : Raised when any bit in BUFF_STATUS is set. Clear by clearing -// all bits in BUFF_STATUS. -#define USB_INTE_BUFF_STATUS_RESET _u(0x0) -#define USB_INTE_BUFF_STATUS_BITS _u(0x00000010) -#define USB_INTE_BUFF_STATUS_MSB _u(4) -#define USB_INTE_BUFF_STATUS_LSB _u(4) -#define USB_INTE_BUFF_STATUS_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_INTE_TRANS_COMPLETE -// Description : Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by -// writing to this bit. -#define USB_INTE_TRANS_COMPLETE_RESET _u(0x0) -#define USB_INTE_TRANS_COMPLETE_BITS _u(0x00000008) -#define USB_INTE_TRANS_COMPLETE_MSB _u(3) -#define USB_INTE_TRANS_COMPLETE_LSB _u(3) -#define USB_INTE_TRANS_COMPLETE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_INTE_HOST_SOF -// Description : Host: raised every time the host sends a SOF (Start of Frame). -// Cleared by reading SOF_RD -#define USB_INTE_HOST_SOF_RESET _u(0x0) -#define USB_INTE_HOST_SOF_BITS _u(0x00000004) -#define USB_INTE_HOST_SOF_MSB _u(2) -#define USB_INTE_HOST_SOF_LSB _u(2) -#define USB_INTE_HOST_SOF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_INTE_HOST_RESUME -// Description : Host: raised when a device wakes up the host. Cleared by -// writing to SIE_STATUS.RESUME_REMOTE -#define USB_INTE_HOST_RESUME_RESET _u(0x0) -#define USB_INTE_HOST_RESUME_BITS _u(0x00000002) -#define USB_INTE_HOST_RESUME_MSB _u(1) -#define USB_INTE_HOST_RESUME_LSB _u(1) -#define USB_INTE_HOST_RESUME_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_INTE_HOST_CONN_DIS -// Description : Host: raised when a device is connected or disconnected (i.e. -// when SIE_STATUS.SPEED changes). Cleared by writing to -// SIE_STATUS.SPEED -#define USB_INTE_HOST_CONN_DIS_RESET _u(0x0) -#define USB_INTE_HOST_CONN_DIS_BITS _u(0x00000001) -#define USB_INTE_HOST_CONN_DIS_MSB _u(0) -#define USB_INTE_HOST_CONN_DIS_LSB _u(0) -#define USB_INTE_HOST_CONN_DIS_ACCESS "RW" -// ============================================================================= -// Register : USB_INTF -// Description : Interrupt Force -#define USB_INTF_OFFSET _u(0x00000094) -#define USB_INTF_BITS _u(0x000fffff) -#define USB_INTF_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_INTF_EP_STALL_NAK -// Description : Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by -// clearing all bits in EP_STATUS_STALL_NAK. -#define USB_INTF_EP_STALL_NAK_RESET _u(0x0) -#define USB_INTF_EP_STALL_NAK_BITS _u(0x00080000) -#define USB_INTF_EP_STALL_NAK_MSB _u(19) -#define USB_INTF_EP_STALL_NAK_LSB _u(19) -#define USB_INTF_EP_STALL_NAK_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_INTF_ABORT_DONE -// Description : Raised when any bit in ABORT_DONE is set. Clear by clearing all -// bits in ABORT_DONE. -#define USB_INTF_ABORT_DONE_RESET _u(0x0) -#define USB_INTF_ABORT_DONE_BITS _u(0x00040000) -#define USB_INTF_ABORT_DONE_MSB _u(18) -#define USB_INTF_ABORT_DONE_LSB _u(18) -#define USB_INTF_ABORT_DONE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_INTF_DEV_SOF -// Description : Set every time the device receives a SOF (Start of Frame) -// packet. Cleared by reading SOF_RD -#define USB_INTF_DEV_SOF_RESET _u(0x0) -#define USB_INTF_DEV_SOF_BITS _u(0x00020000) -#define USB_INTF_DEV_SOF_MSB _u(17) -#define USB_INTF_DEV_SOF_LSB _u(17) -#define USB_INTF_DEV_SOF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_INTF_SETUP_REQ -// Description : Device. Source: SIE_STATUS.SETUP_REC -#define USB_INTF_SETUP_REQ_RESET _u(0x0) -#define USB_INTF_SETUP_REQ_BITS _u(0x00010000) -#define USB_INTF_SETUP_REQ_MSB _u(16) -#define USB_INTF_SETUP_REQ_LSB _u(16) -#define USB_INTF_SETUP_REQ_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_INTF_DEV_RESUME_FROM_HOST -// Description : Set when the device receives a resume from the host. Cleared by -// writing to SIE_STATUS.RESUME_REMOTE -#define USB_INTF_DEV_RESUME_FROM_HOST_RESET _u(0x0) -#define USB_INTF_DEV_RESUME_FROM_HOST_BITS _u(0x00008000) -#define USB_INTF_DEV_RESUME_FROM_HOST_MSB _u(15) -#define USB_INTF_DEV_RESUME_FROM_HOST_LSB _u(15) -#define USB_INTF_DEV_RESUME_FROM_HOST_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_INTF_DEV_SUSPEND -// Description : Set when the device suspend state changes. Cleared by writing -// to SIE_STATUS.SUSPENDED -#define USB_INTF_DEV_SUSPEND_RESET _u(0x0) -#define USB_INTF_DEV_SUSPEND_BITS _u(0x00004000) -#define USB_INTF_DEV_SUSPEND_MSB _u(14) -#define USB_INTF_DEV_SUSPEND_LSB _u(14) -#define USB_INTF_DEV_SUSPEND_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_INTF_DEV_CONN_DIS -// Description : Set when the device connection state changes. Cleared by -// writing to SIE_STATUS.CONNECTED -#define USB_INTF_DEV_CONN_DIS_RESET _u(0x0) -#define USB_INTF_DEV_CONN_DIS_BITS _u(0x00002000) -#define USB_INTF_DEV_CONN_DIS_MSB _u(13) -#define USB_INTF_DEV_CONN_DIS_LSB _u(13) -#define USB_INTF_DEV_CONN_DIS_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_INTF_BUS_RESET -// Description : Source: SIE_STATUS.BUS_RESET -#define USB_INTF_BUS_RESET_RESET _u(0x0) -#define USB_INTF_BUS_RESET_BITS _u(0x00001000) -#define USB_INTF_BUS_RESET_MSB _u(12) -#define USB_INTF_BUS_RESET_LSB _u(12) -#define USB_INTF_BUS_RESET_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_INTF_VBUS_DETECT -// Description : Source: SIE_STATUS.VBUS_DETECT -#define USB_INTF_VBUS_DETECT_RESET _u(0x0) -#define USB_INTF_VBUS_DETECT_BITS _u(0x00000800) -#define USB_INTF_VBUS_DETECT_MSB _u(11) -#define USB_INTF_VBUS_DETECT_LSB _u(11) -#define USB_INTF_VBUS_DETECT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_INTF_STALL -// Description : Source: SIE_STATUS.STALL_REC -#define USB_INTF_STALL_RESET _u(0x0) -#define USB_INTF_STALL_BITS _u(0x00000400) -#define USB_INTF_STALL_MSB _u(10) -#define USB_INTF_STALL_LSB _u(10) -#define USB_INTF_STALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_INTF_ERROR_CRC -// Description : Source: SIE_STATUS.CRC_ERROR -#define USB_INTF_ERROR_CRC_RESET _u(0x0) -#define USB_INTF_ERROR_CRC_BITS _u(0x00000200) -#define USB_INTF_ERROR_CRC_MSB _u(9) -#define USB_INTF_ERROR_CRC_LSB _u(9) -#define USB_INTF_ERROR_CRC_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_INTF_ERROR_BIT_STUFF -// Description : Source: SIE_STATUS.BIT_STUFF_ERROR -#define USB_INTF_ERROR_BIT_STUFF_RESET _u(0x0) -#define USB_INTF_ERROR_BIT_STUFF_BITS _u(0x00000100) -#define USB_INTF_ERROR_BIT_STUFF_MSB _u(8) -#define USB_INTF_ERROR_BIT_STUFF_LSB _u(8) -#define USB_INTF_ERROR_BIT_STUFF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_INTF_ERROR_RX_OVERFLOW -// Description : Source: SIE_STATUS.RX_OVERFLOW -#define USB_INTF_ERROR_RX_OVERFLOW_RESET _u(0x0) -#define USB_INTF_ERROR_RX_OVERFLOW_BITS _u(0x00000080) -#define USB_INTF_ERROR_RX_OVERFLOW_MSB _u(7) -#define USB_INTF_ERROR_RX_OVERFLOW_LSB _u(7) -#define USB_INTF_ERROR_RX_OVERFLOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_INTF_ERROR_RX_TIMEOUT -// Description : Source: SIE_STATUS.RX_TIMEOUT -#define USB_INTF_ERROR_RX_TIMEOUT_RESET _u(0x0) -#define USB_INTF_ERROR_RX_TIMEOUT_BITS _u(0x00000040) -#define USB_INTF_ERROR_RX_TIMEOUT_MSB _u(6) -#define USB_INTF_ERROR_RX_TIMEOUT_LSB _u(6) -#define USB_INTF_ERROR_RX_TIMEOUT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_INTF_ERROR_DATA_SEQ -// Description : Source: SIE_STATUS.DATA_SEQ_ERROR -#define USB_INTF_ERROR_DATA_SEQ_RESET _u(0x0) -#define USB_INTF_ERROR_DATA_SEQ_BITS _u(0x00000020) -#define USB_INTF_ERROR_DATA_SEQ_MSB _u(5) -#define USB_INTF_ERROR_DATA_SEQ_LSB _u(5) -#define USB_INTF_ERROR_DATA_SEQ_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_INTF_BUFF_STATUS -// Description : Raised when any bit in BUFF_STATUS is set. Clear by clearing -// all bits in BUFF_STATUS. -#define USB_INTF_BUFF_STATUS_RESET _u(0x0) -#define USB_INTF_BUFF_STATUS_BITS _u(0x00000010) -#define USB_INTF_BUFF_STATUS_MSB _u(4) -#define USB_INTF_BUFF_STATUS_LSB _u(4) -#define USB_INTF_BUFF_STATUS_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_INTF_TRANS_COMPLETE -// Description : Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by -// writing to this bit. -#define USB_INTF_TRANS_COMPLETE_RESET _u(0x0) -#define USB_INTF_TRANS_COMPLETE_BITS _u(0x00000008) -#define USB_INTF_TRANS_COMPLETE_MSB _u(3) -#define USB_INTF_TRANS_COMPLETE_LSB _u(3) -#define USB_INTF_TRANS_COMPLETE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_INTF_HOST_SOF -// Description : Host: raised every time the host sends a SOF (Start of Frame). -// Cleared by reading SOF_RD -#define USB_INTF_HOST_SOF_RESET _u(0x0) -#define USB_INTF_HOST_SOF_BITS _u(0x00000004) -#define USB_INTF_HOST_SOF_MSB _u(2) -#define USB_INTF_HOST_SOF_LSB _u(2) -#define USB_INTF_HOST_SOF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_INTF_HOST_RESUME -// Description : Host: raised when a device wakes up the host. Cleared by -// writing to SIE_STATUS.RESUME_REMOTE -#define USB_INTF_HOST_RESUME_RESET _u(0x0) -#define USB_INTF_HOST_RESUME_BITS _u(0x00000002) -#define USB_INTF_HOST_RESUME_MSB _u(1) -#define USB_INTF_HOST_RESUME_LSB _u(1) -#define USB_INTF_HOST_RESUME_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_INTF_HOST_CONN_DIS -// Description : Host: raised when a device is connected or disconnected (i.e. -// when SIE_STATUS.SPEED changes). Cleared by writing to -// SIE_STATUS.SPEED -#define USB_INTF_HOST_CONN_DIS_RESET _u(0x0) -#define USB_INTF_HOST_CONN_DIS_BITS _u(0x00000001) -#define USB_INTF_HOST_CONN_DIS_MSB _u(0) -#define USB_INTF_HOST_CONN_DIS_LSB _u(0) -#define USB_INTF_HOST_CONN_DIS_ACCESS "RW" -// ============================================================================= -// Register : USB_INTS -// Description : Interrupt status after masking & forcing -#define USB_INTS_OFFSET _u(0x00000098) -#define USB_INTS_BITS _u(0x000fffff) -#define USB_INTS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_INTS_EP_STALL_NAK -// Description : Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by -// clearing all bits in EP_STATUS_STALL_NAK. -#define USB_INTS_EP_STALL_NAK_RESET _u(0x0) -#define USB_INTS_EP_STALL_NAK_BITS _u(0x00080000) -#define USB_INTS_EP_STALL_NAK_MSB _u(19) -#define USB_INTS_EP_STALL_NAK_LSB _u(19) -#define USB_INTS_EP_STALL_NAK_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_INTS_ABORT_DONE -// Description : Raised when any bit in ABORT_DONE is set. Clear by clearing all -// bits in ABORT_DONE. -#define USB_INTS_ABORT_DONE_RESET _u(0x0) -#define USB_INTS_ABORT_DONE_BITS _u(0x00040000) -#define USB_INTS_ABORT_DONE_MSB _u(18) -#define USB_INTS_ABORT_DONE_LSB _u(18) -#define USB_INTS_ABORT_DONE_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_INTS_DEV_SOF -// Description : Set every time the device receives a SOF (Start of Frame) -// packet. Cleared by reading SOF_RD -#define USB_INTS_DEV_SOF_RESET _u(0x0) -#define USB_INTS_DEV_SOF_BITS _u(0x00020000) -#define USB_INTS_DEV_SOF_MSB _u(17) -#define USB_INTS_DEV_SOF_LSB _u(17) -#define USB_INTS_DEV_SOF_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_INTS_SETUP_REQ -// Description : Device. Source: SIE_STATUS.SETUP_REC -#define USB_INTS_SETUP_REQ_RESET _u(0x0) -#define USB_INTS_SETUP_REQ_BITS _u(0x00010000) -#define USB_INTS_SETUP_REQ_MSB _u(16) -#define USB_INTS_SETUP_REQ_LSB _u(16) -#define USB_INTS_SETUP_REQ_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_INTS_DEV_RESUME_FROM_HOST -// Description : Set when the device receives a resume from the host. Cleared by -// writing to SIE_STATUS.RESUME_REMOTE -#define USB_INTS_DEV_RESUME_FROM_HOST_RESET _u(0x0) -#define USB_INTS_DEV_RESUME_FROM_HOST_BITS _u(0x00008000) -#define USB_INTS_DEV_RESUME_FROM_HOST_MSB _u(15) -#define USB_INTS_DEV_RESUME_FROM_HOST_LSB _u(15) -#define USB_INTS_DEV_RESUME_FROM_HOST_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_INTS_DEV_SUSPEND -// Description : Set when the device suspend state changes. Cleared by writing -// to SIE_STATUS.SUSPENDED -#define USB_INTS_DEV_SUSPEND_RESET _u(0x0) -#define USB_INTS_DEV_SUSPEND_BITS _u(0x00004000) -#define USB_INTS_DEV_SUSPEND_MSB _u(14) -#define USB_INTS_DEV_SUSPEND_LSB _u(14) -#define USB_INTS_DEV_SUSPEND_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_INTS_DEV_CONN_DIS -// Description : Set when the device connection state changes. Cleared by -// writing to SIE_STATUS.CONNECTED -#define USB_INTS_DEV_CONN_DIS_RESET _u(0x0) -#define USB_INTS_DEV_CONN_DIS_BITS _u(0x00002000) -#define USB_INTS_DEV_CONN_DIS_MSB _u(13) -#define USB_INTS_DEV_CONN_DIS_LSB _u(13) -#define USB_INTS_DEV_CONN_DIS_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_INTS_BUS_RESET -// Description : Source: SIE_STATUS.BUS_RESET -#define USB_INTS_BUS_RESET_RESET _u(0x0) -#define USB_INTS_BUS_RESET_BITS _u(0x00001000) -#define USB_INTS_BUS_RESET_MSB _u(12) -#define USB_INTS_BUS_RESET_LSB _u(12) -#define USB_INTS_BUS_RESET_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_INTS_VBUS_DETECT -// Description : Source: SIE_STATUS.VBUS_DETECT -#define USB_INTS_VBUS_DETECT_RESET _u(0x0) -#define USB_INTS_VBUS_DETECT_BITS _u(0x00000800) -#define USB_INTS_VBUS_DETECT_MSB _u(11) -#define USB_INTS_VBUS_DETECT_LSB _u(11) -#define USB_INTS_VBUS_DETECT_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_INTS_STALL -// Description : Source: SIE_STATUS.STALL_REC -#define USB_INTS_STALL_RESET _u(0x0) -#define USB_INTS_STALL_BITS _u(0x00000400) -#define USB_INTS_STALL_MSB _u(10) -#define USB_INTS_STALL_LSB _u(10) -#define USB_INTS_STALL_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_INTS_ERROR_CRC -// Description : Source: SIE_STATUS.CRC_ERROR -#define USB_INTS_ERROR_CRC_RESET _u(0x0) -#define USB_INTS_ERROR_CRC_BITS _u(0x00000200) -#define USB_INTS_ERROR_CRC_MSB _u(9) -#define USB_INTS_ERROR_CRC_LSB _u(9) -#define USB_INTS_ERROR_CRC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_INTS_ERROR_BIT_STUFF -// Description : Source: SIE_STATUS.BIT_STUFF_ERROR -#define USB_INTS_ERROR_BIT_STUFF_RESET _u(0x0) -#define USB_INTS_ERROR_BIT_STUFF_BITS _u(0x00000100) -#define USB_INTS_ERROR_BIT_STUFF_MSB _u(8) -#define USB_INTS_ERROR_BIT_STUFF_LSB _u(8) -#define USB_INTS_ERROR_BIT_STUFF_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_INTS_ERROR_RX_OVERFLOW -// Description : Source: SIE_STATUS.RX_OVERFLOW -#define USB_INTS_ERROR_RX_OVERFLOW_RESET _u(0x0) -#define USB_INTS_ERROR_RX_OVERFLOW_BITS _u(0x00000080) -#define USB_INTS_ERROR_RX_OVERFLOW_MSB _u(7) -#define USB_INTS_ERROR_RX_OVERFLOW_LSB _u(7) -#define USB_INTS_ERROR_RX_OVERFLOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_INTS_ERROR_RX_TIMEOUT -// Description : Source: SIE_STATUS.RX_TIMEOUT -#define USB_INTS_ERROR_RX_TIMEOUT_RESET _u(0x0) -#define USB_INTS_ERROR_RX_TIMEOUT_BITS _u(0x00000040) -#define USB_INTS_ERROR_RX_TIMEOUT_MSB _u(6) -#define USB_INTS_ERROR_RX_TIMEOUT_LSB _u(6) -#define USB_INTS_ERROR_RX_TIMEOUT_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_INTS_ERROR_DATA_SEQ -// Description : Source: SIE_STATUS.DATA_SEQ_ERROR -#define USB_INTS_ERROR_DATA_SEQ_RESET _u(0x0) -#define USB_INTS_ERROR_DATA_SEQ_BITS _u(0x00000020) -#define USB_INTS_ERROR_DATA_SEQ_MSB _u(5) -#define USB_INTS_ERROR_DATA_SEQ_LSB _u(5) -#define USB_INTS_ERROR_DATA_SEQ_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_INTS_BUFF_STATUS -// Description : Raised when any bit in BUFF_STATUS is set. Clear by clearing -// all bits in BUFF_STATUS. -#define USB_INTS_BUFF_STATUS_RESET _u(0x0) -#define USB_INTS_BUFF_STATUS_BITS _u(0x00000010) -#define USB_INTS_BUFF_STATUS_MSB _u(4) -#define USB_INTS_BUFF_STATUS_LSB _u(4) -#define USB_INTS_BUFF_STATUS_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_INTS_TRANS_COMPLETE -// Description : Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by -// writing to this bit. -#define USB_INTS_TRANS_COMPLETE_RESET _u(0x0) -#define USB_INTS_TRANS_COMPLETE_BITS _u(0x00000008) -#define USB_INTS_TRANS_COMPLETE_MSB _u(3) -#define USB_INTS_TRANS_COMPLETE_LSB _u(3) -#define USB_INTS_TRANS_COMPLETE_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_INTS_HOST_SOF -// Description : Host: raised every time the host sends a SOF (Start of Frame). -// Cleared by reading SOF_RD -#define USB_INTS_HOST_SOF_RESET _u(0x0) -#define USB_INTS_HOST_SOF_BITS _u(0x00000004) -#define USB_INTS_HOST_SOF_MSB _u(2) -#define USB_INTS_HOST_SOF_LSB _u(2) -#define USB_INTS_HOST_SOF_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_INTS_HOST_RESUME -// Description : Host: raised when a device wakes up the host. Cleared by -// writing to SIE_STATUS.RESUME_REMOTE -#define USB_INTS_HOST_RESUME_RESET _u(0x0) -#define USB_INTS_HOST_RESUME_BITS _u(0x00000002) -#define USB_INTS_HOST_RESUME_MSB _u(1) -#define USB_INTS_HOST_RESUME_LSB _u(1) -#define USB_INTS_HOST_RESUME_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_INTS_HOST_CONN_DIS -// Description : Host: raised when a device is connected or disconnected (i.e. -// when SIE_STATUS.SPEED changes). Cleared by writing to -// SIE_STATUS.SPEED -#define USB_INTS_HOST_CONN_DIS_RESET _u(0x0) -#define USB_INTS_HOST_CONN_DIS_BITS _u(0x00000001) -#define USB_INTS_HOST_CONN_DIS_MSB _u(0) -#define USB_INTS_HOST_CONN_DIS_LSB _u(0) -#define USB_INTS_HOST_CONN_DIS_ACCESS "RO" -// ============================================================================= -#endif // _HARDWARE_REGS_USB_H - diff --git a/lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/usb_device_dpram.h b/lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/usb_device_dpram.h deleted file mode 100644 index d3a5ad32e4..0000000000 --- a/lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/usb_device_dpram.h +++ /dev/null @@ -1,6753 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -// ============================================================================= -// Register block : USB_DEVICE_DPRAM -// Version : 1 -// Bus type : ahbl -// Description : DPRAM layout for USB device. -// ============================================================================= -#ifndef _HARDWARE_REGS_USB_DEVICE_DPRAM_H -#define _HARDWARE_REGS_USB_DEVICE_DPRAM_H -// ============================================================================= -// Register : USB_DEVICE_DPRAM_SETUP_PACKET_LOW -// Description : Bytes 0-3 of the SETUP packet from the host. -#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_OFFSET _u(0x00000000) -#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BITS _u(0xffffffff) -#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_SETUP_PACKET_LOW_WVALUE -#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_WVALUE_RESET _u(0x0000) -#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_WVALUE_BITS _u(0xffff0000) -#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_WVALUE_MSB _u(31) -#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_WVALUE_LSB _u(16) -#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_WVALUE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BREQUEST -#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BREQUEST_RESET _u(0x00) -#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BREQUEST_BITS _u(0x0000ff00) -#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BREQUEST_MSB _u(15) -#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BREQUEST_LSB _u(8) -#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BREQUEST_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BMREQUESTTYPE -#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BMREQUESTTYPE_RESET _u(0x00) -#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BMREQUESTTYPE_BITS _u(0x000000ff) -#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BMREQUESTTYPE_MSB _u(7) -#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BMREQUESTTYPE_LSB _u(0) -#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BMREQUESTTYPE_ACCESS "RW" -// ============================================================================= -// Register : USB_DEVICE_DPRAM_SETUP_PACKET_HIGH -// Description : Bytes 4-7 of the setup packet from the host. -#define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_OFFSET _u(0x00000004) -#define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_BITS _u(0xffffffff) -#define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_WLENGTH -#define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_WLENGTH_RESET _u(0x0000) -#define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_WLENGTH_BITS _u(0xffff0000) -#define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_WLENGTH_MSB _u(31) -#define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_WLENGTH_LSB _u(16) -#define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_WLENGTH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_WINDEX -#define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_WINDEX_RESET _u(0x0000) -#define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_WINDEX_BITS _u(0x0000ffff) -#define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_WINDEX_MSB _u(15) -#define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_WINDEX_LSB _u(0) -#define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_WINDEX_ACCESS "RW" -// ============================================================================= -// Register : USB_DEVICE_DPRAM_EP1_IN_CONTROL -#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_OFFSET _u(0x00000008) -#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_BITS _u(0xfc03ffff) -#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENABLE -// Description : Enable this endpoint. The device will not reply to any packets -// for this endpoint if this bit is not set. -#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENABLE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENABLE_BITS _u(0x80000000) -#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENABLE_MSB _u(31) -#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENABLE_LSB _u(31) -#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENABLE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP1_IN_CONTROL_DOUBLE_BUFFERED -// Description : This endpoint is double buffered. -#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) -#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_DOUBLE_BUFFERED_MSB _u(30) -#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_DOUBLE_BUFFERED_LSB _u(30) -#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_PER_BUFF -// Description : Trigger an interrupt each time a buffer is done. -#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) -#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) -#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) -#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF -// Description : Trigger an interrupt each time both buffers are done. Only -// valid in double buffered mode. -#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) -#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) -#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) -#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE -// 0x0 -> Control -// 0x1 -> Isochronous -// 0x2 -> Bulk -// 0x3 -> Interrupt -#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) -#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) -#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) -#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) -#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) -#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) -#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_ON_STALL -// Description : Trigger an interrupt if a STALL is sent. Intended for debug -// only. -#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) -#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) -#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) -#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_ON_NAK -// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. -#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) -#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) -#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) -#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP1_IN_CONTROL_BUFFER_ADDRESS -// Description : 64 byte aligned buffer address for this EP (bits 0-5 are -// ignored). Relative to the start of the DPRAM. -#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) -#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) -#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_BUFFER_ADDRESS_MSB _u(15) -#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_BUFFER_ADDRESS_LSB _u(0) -#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW" -// ============================================================================= -// Register : USB_DEVICE_DPRAM_EP1_OUT_CONTROL -#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_OFFSET _u(0x0000000c) -#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_BITS _u(0xfc03ffff) -#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENABLE -// Description : Enable this endpoint. The device will not reply to any packets -// for this endpoint if this bit is not set. -#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENABLE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENABLE_BITS _u(0x80000000) -#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENABLE_MSB _u(31) -#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENABLE_LSB _u(31) -#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENABLE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP1_OUT_CONTROL_DOUBLE_BUFFERED -// Description : This endpoint is double buffered. -#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) -#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_DOUBLE_BUFFERED_MSB _u(30) -#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_DOUBLE_BUFFERED_LSB _u(30) -#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_PER_BUFF -// Description : Trigger an interrupt each time a buffer is done. -#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) -#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) -#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) -#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF -// Description : Trigger an interrupt each time both buffers are done. Only -// valid in double buffered mode. -#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) -#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) -#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) -#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE -// 0x0 -> Control -// 0x1 -> Isochronous -// 0x2 -> Bulk -// 0x3 -> Interrupt -#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) -#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) -#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) -#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) -#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) -#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) -#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_ON_STALL -// Description : Trigger an interrupt if a STALL is sent. Intended for debug -// only. -#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) -#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) -#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) -#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_ON_NAK -// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. -#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) -#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) -#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) -#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP1_OUT_CONTROL_BUFFER_ADDRESS -// Description : 64 byte aligned buffer address for this EP (bits 0-5 are -// ignored). Relative to the start of the DPRAM. -#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) -#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) -#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_BUFFER_ADDRESS_MSB _u(15) -#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_BUFFER_ADDRESS_LSB _u(0) -#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW" -// ============================================================================= -// Register : USB_DEVICE_DPRAM_EP2_IN_CONTROL -#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_OFFSET _u(0x00000010) -#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_BITS _u(0xfc03ffff) -#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENABLE -// Description : Enable this endpoint. The device will not reply to any packets -// for this endpoint if this bit is not set. -#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENABLE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENABLE_BITS _u(0x80000000) -#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENABLE_MSB _u(31) -#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENABLE_LSB _u(31) -#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENABLE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP2_IN_CONTROL_DOUBLE_BUFFERED -// Description : This endpoint is double buffered. -#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) -#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_DOUBLE_BUFFERED_MSB _u(30) -#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_DOUBLE_BUFFERED_LSB _u(30) -#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_PER_BUFF -// Description : Trigger an interrupt each time a buffer is done. -#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) -#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) -#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) -#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF -// Description : Trigger an interrupt each time both buffers are done. Only -// valid in double buffered mode. -#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) -#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) -#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) -#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE -// 0x0 -> Control -// 0x1 -> Isochronous -// 0x2 -> Bulk -// 0x3 -> Interrupt -#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) -#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) -#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) -#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) -#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) -#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) -#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_ON_STALL -// Description : Trigger an interrupt if a STALL is sent. Intended for debug -// only. -#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) -#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) -#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) -#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_ON_NAK -// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. -#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) -#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) -#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) -#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP2_IN_CONTROL_BUFFER_ADDRESS -// Description : 64 byte aligned buffer address for this EP (bits 0-5 are -// ignored). Relative to the start of the DPRAM. -#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) -#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) -#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_BUFFER_ADDRESS_MSB _u(15) -#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_BUFFER_ADDRESS_LSB _u(0) -#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW" -// ============================================================================= -// Register : USB_DEVICE_DPRAM_EP2_OUT_CONTROL -#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_OFFSET _u(0x00000014) -#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_BITS _u(0xfc03ffff) -#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENABLE -// Description : Enable this endpoint. The device will not reply to any packets -// for this endpoint if this bit is not set. -#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENABLE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENABLE_BITS _u(0x80000000) -#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENABLE_MSB _u(31) -#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENABLE_LSB _u(31) -#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENABLE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP2_OUT_CONTROL_DOUBLE_BUFFERED -// Description : This endpoint is double buffered. -#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) -#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_DOUBLE_BUFFERED_MSB _u(30) -#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_DOUBLE_BUFFERED_LSB _u(30) -#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_PER_BUFF -// Description : Trigger an interrupt each time a buffer is done. -#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) -#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) -#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) -#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF -// Description : Trigger an interrupt each time both buffers are done. Only -// valid in double buffered mode. -#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) -#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) -#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) -#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE -// 0x0 -> Control -// 0x1 -> Isochronous -// 0x2 -> Bulk -// 0x3 -> Interrupt -#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) -#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) -#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) -#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) -#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) -#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) -#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_ON_STALL -// Description : Trigger an interrupt if a STALL is sent. Intended for debug -// only. -#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) -#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) -#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) -#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_ON_NAK -// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. -#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) -#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) -#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) -#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP2_OUT_CONTROL_BUFFER_ADDRESS -// Description : 64 byte aligned buffer address for this EP (bits 0-5 are -// ignored). Relative to the start of the DPRAM. -#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) -#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) -#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_BUFFER_ADDRESS_MSB _u(15) -#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_BUFFER_ADDRESS_LSB _u(0) -#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW" -// ============================================================================= -// Register : USB_DEVICE_DPRAM_EP3_IN_CONTROL -#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_OFFSET _u(0x00000018) -#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_BITS _u(0xfc03ffff) -#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENABLE -// Description : Enable this endpoint. The device will not reply to any packets -// for this endpoint if this bit is not set. -#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENABLE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENABLE_BITS _u(0x80000000) -#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENABLE_MSB _u(31) -#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENABLE_LSB _u(31) -#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENABLE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP3_IN_CONTROL_DOUBLE_BUFFERED -// Description : This endpoint is double buffered. -#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) -#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_DOUBLE_BUFFERED_MSB _u(30) -#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_DOUBLE_BUFFERED_LSB _u(30) -#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_PER_BUFF -// Description : Trigger an interrupt each time a buffer is done. -#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) -#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) -#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) -#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF -// Description : Trigger an interrupt each time both buffers are done. Only -// valid in double buffered mode. -#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) -#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) -#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) -#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE -// 0x0 -> Control -// 0x1 -> Isochronous -// 0x2 -> Bulk -// 0x3 -> Interrupt -#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) -#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) -#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) -#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) -#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) -#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) -#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_ON_STALL -// Description : Trigger an interrupt if a STALL is sent. Intended for debug -// only. -#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) -#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) -#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) -#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_ON_NAK -// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. -#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) -#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) -#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) -#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP3_IN_CONTROL_BUFFER_ADDRESS -// Description : 64 byte aligned buffer address for this EP (bits 0-5 are -// ignored). Relative to the start of the DPRAM. -#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) -#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) -#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_BUFFER_ADDRESS_MSB _u(15) -#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_BUFFER_ADDRESS_LSB _u(0) -#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW" -// ============================================================================= -// Register : USB_DEVICE_DPRAM_EP3_OUT_CONTROL -#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_OFFSET _u(0x0000001c) -#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_BITS _u(0xfc03ffff) -#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENABLE -// Description : Enable this endpoint. The device will not reply to any packets -// for this endpoint if this bit is not set. -#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENABLE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENABLE_BITS _u(0x80000000) -#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENABLE_MSB _u(31) -#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENABLE_LSB _u(31) -#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENABLE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP3_OUT_CONTROL_DOUBLE_BUFFERED -// Description : This endpoint is double buffered. -#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) -#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_DOUBLE_BUFFERED_MSB _u(30) -#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_DOUBLE_BUFFERED_LSB _u(30) -#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_PER_BUFF -// Description : Trigger an interrupt each time a buffer is done. -#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) -#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) -#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) -#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF -// Description : Trigger an interrupt each time both buffers are done. Only -// valid in double buffered mode. -#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) -#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) -#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) -#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE -// 0x0 -> Control -// 0x1 -> Isochronous -// 0x2 -> Bulk -// 0x3 -> Interrupt -#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) -#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) -#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) -#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) -#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) -#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) -#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_ON_STALL -// Description : Trigger an interrupt if a STALL is sent. Intended for debug -// only. -#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) -#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) -#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) -#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_ON_NAK -// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. -#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) -#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) -#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) -#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP3_OUT_CONTROL_BUFFER_ADDRESS -// Description : 64 byte aligned buffer address for this EP (bits 0-5 are -// ignored). Relative to the start of the DPRAM. -#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) -#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) -#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_BUFFER_ADDRESS_MSB _u(15) -#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_BUFFER_ADDRESS_LSB _u(0) -#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW" -// ============================================================================= -// Register : USB_DEVICE_DPRAM_EP4_IN_CONTROL -#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_OFFSET _u(0x00000020) -#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_BITS _u(0xfc03ffff) -#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENABLE -// Description : Enable this endpoint. The device will not reply to any packets -// for this endpoint if this bit is not set. -#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENABLE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENABLE_BITS _u(0x80000000) -#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENABLE_MSB _u(31) -#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENABLE_LSB _u(31) -#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENABLE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP4_IN_CONTROL_DOUBLE_BUFFERED -// Description : This endpoint is double buffered. -#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) -#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_DOUBLE_BUFFERED_MSB _u(30) -#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_DOUBLE_BUFFERED_LSB _u(30) -#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_PER_BUFF -// Description : Trigger an interrupt each time a buffer is done. -#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) -#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) -#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) -#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF -// Description : Trigger an interrupt each time both buffers are done. Only -// valid in double buffered mode. -#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) -#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) -#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) -#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE -// 0x0 -> Control -// 0x1 -> Isochronous -// 0x2 -> Bulk -// 0x3 -> Interrupt -#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) -#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) -#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) -#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) -#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) -#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) -#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_ON_STALL -// Description : Trigger an interrupt if a STALL is sent. Intended for debug -// only. -#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) -#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) -#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) -#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_ON_NAK -// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. -#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) -#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) -#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) -#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP4_IN_CONTROL_BUFFER_ADDRESS -// Description : 64 byte aligned buffer address for this EP (bits 0-5 are -// ignored). Relative to the start of the DPRAM. -#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) -#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) -#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_BUFFER_ADDRESS_MSB _u(15) -#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_BUFFER_ADDRESS_LSB _u(0) -#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW" -// ============================================================================= -// Register : USB_DEVICE_DPRAM_EP4_OUT_CONTROL -#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_OFFSET _u(0x00000024) -#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_BITS _u(0xfc03ffff) -#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENABLE -// Description : Enable this endpoint. The device will not reply to any packets -// for this endpoint if this bit is not set. -#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENABLE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENABLE_BITS _u(0x80000000) -#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENABLE_MSB _u(31) -#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENABLE_LSB _u(31) -#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENABLE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP4_OUT_CONTROL_DOUBLE_BUFFERED -// Description : This endpoint is double buffered. -#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) -#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_DOUBLE_BUFFERED_MSB _u(30) -#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_DOUBLE_BUFFERED_LSB _u(30) -#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_PER_BUFF -// Description : Trigger an interrupt each time a buffer is done. -#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) -#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) -#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) -#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF -// Description : Trigger an interrupt each time both buffers are done. Only -// valid in double buffered mode. -#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) -#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) -#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) -#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE -// 0x0 -> Control -// 0x1 -> Isochronous -// 0x2 -> Bulk -// 0x3 -> Interrupt -#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) -#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) -#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) -#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) -#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) -#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) -#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_ON_STALL -// Description : Trigger an interrupt if a STALL is sent. Intended for debug -// only. -#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) -#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) -#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) -#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_ON_NAK -// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. -#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) -#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) -#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) -#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP4_OUT_CONTROL_BUFFER_ADDRESS -// Description : 64 byte aligned buffer address for this EP (bits 0-5 are -// ignored). Relative to the start of the DPRAM. -#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) -#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) -#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_BUFFER_ADDRESS_MSB _u(15) -#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_BUFFER_ADDRESS_LSB _u(0) -#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW" -// ============================================================================= -// Register : USB_DEVICE_DPRAM_EP5_IN_CONTROL -#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_OFFSET _u(0x00000028) -#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_BITS _u(0xfc03ffff) -#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENABLE -// Description : Enable this endpoint. The device will not reply to any packets -// for this endpoint if this bit is not set. -#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENABLE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENABLE_BITS _u(0x80000000) -#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENABLE_MSB _u(31) -#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENABLE_LSB _u(31) -#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENABLE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP5_IN_CONTROL_DOUBLE_BUFFERED -// Description : This endpoint is double buffered. -#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) -#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_DOUBLE_BUFFERED_MSB _u(30) -#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_DOUBLE_BUFFERED_LSB _u(30) -#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_PER_BUFF -// Description : Trigger an interrupt each time a buffer is done. -#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) -#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) -#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) -#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF -// Description : Trigger an interrupt each time both buffers are done. Only -// valid in double buffered mode. -#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) -#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) -#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) -#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE -// 0x0 -> Control -// 0x1 -> Isochronous -// 0x2 -> Bulk -// 0x3 -> Interrupt -#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) -#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) -#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) -#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) -#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) -#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) -#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_ON_STALL -// Description : Trigger an interrupt if a STALL is sent. Intended for debug -// only. -#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) -#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) -#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) -#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_ON_NAK -// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. -#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) -#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) -#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) -#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP5_IN_CONTROL_BUFFER_ADDRESS -// Description : 64 byte aligned buffer address for this EP (bits 0-5 are -// ignored). Relative to the start of the DPRAM. -#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) -#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) -#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_BUFFER_ADDRESS_MSB _u(15) -#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_BUFFER_ADDRESS_LSB _u(0) -#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW" -// ============================================================================= -// Register : USB_DEVICE_DPRAM_EP5_OUT_CONTROL -#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_OFFSET _u(0x0000002c) -#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_BITS _u(0xfc03ffff) -#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENABLE -// Description : Enable this endpoint. The device will not reply to any packets -// for this endpoint if this bit is not set. -#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENABLE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENABLE_BITS _u(0x80000000) -#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENABLE_MSB _u(31) -#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENABLE_LSB _u(31) -#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENABLE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP5_OUT_CONTROL_DOUBLE_BUFFERED -// Description : This endpoint is double buffered. -#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) -#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_DOUBLE_BUFFERED_MSB _u(30) -#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_DOUBLE_BUFFERED_LSB _u(30) -#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_PER_BUFF -// Description : Trigger an interrupt each time a buffer is done. -#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) -#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) -#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) -#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF -// Description : Trigger an interrupt each time both buffers are done. Only -// valid in double buffered mode. -#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) -#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) -#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) -#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE -// 0x0 -> Control -// 0x1 -> Isochronous -// 0x2 -> Bulk -// 0x3 -> Interrupt -#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) -#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) -#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) -#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) -#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) -#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) -#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_ON_STALL -// Description : Trigger an interrupt if a STALL is sent. Intended for debug -// only. -#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) -#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) -#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) -#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_ON_NAK -// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. -#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) -#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) -#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) -#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP5_OUT_CONTROL_BUFFER_ADDRESS -// Description : 64 byte aligned buffer address for this EP (bits 0-5 are -// ignored). Relative to the start of the DPRAM. -#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) -#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) -#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_BUFFER_ADDRESS_MSB _u(15) -#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_BUFFER_ADDRESS_LSB _u(0) -#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW" -// ============================================================================= -// Register : USB_DEVICE_DPRAM_EP6_IN_CONTROL -#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_OFFSET _u(0x00000030) -#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_BITS _u(0xfc03ffff) -#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENABLE -// Description : Enable this endpoint. The device will not reply to any packets -// for this endpoint if this bit is not set. -#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENABLE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENABLE_BITS _u(0x80000000) -#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENABLE_MSB _u(31) -#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENABLE_LSB _u(31) -#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENABLE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP6_IN_CONTROL_DOUBLE_BUFFERED -// Description : This endpoint is double buffered. -#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) -#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_DOUBLE_BUFFERED_MSB _u(30) -#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_DOUBLE_BUFFERED_LSB _u(30) -#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_PER_BUFF -// Description : Trigger an interrupt each time a buffer is done. -#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) -#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) -#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) -#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF -// Description : Trigger an interrupt each time both buffers are done. Only -// valid in double buffered mode. -#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) -#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) -#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) -#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE -// 0x0 -> Control -// 0x1 -> Isochronous -// 0x2 -> Bulk -// 0x3 -> Interrupt -#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) -#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) -#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) -#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) -#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) -#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) -#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_ON_STALL -// Description : Trigger an interrupt if a STALL is sent. Intended for debug -// only. -#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) -#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) -#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) -#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_ON_NAK -// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. -#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) -#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) -#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) -#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP6_IN_CONTROL_BUFFER_ADDRESS -// Description : 64 byte aligned buffer address for this EP (bits 0-5 are -// ignored). Relative to the start of the DPRAM. -#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) -#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) -#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_BUFFER_ADDRESS_MSB _u(15) -#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_BUFFER_ADDRESS_LSB _u(0) -#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW" -// ============================================================================= -// Register : USB_DEVICE_DPRAM_EP6_OUT_CONTROL -#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_OFFSET _u(0x00000034) -#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_BITS _u(0xfc03ffff) -#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENABLE -// Description : Enable this endpoint. The device will not reply to any packets -// for this endpoint if this bit is not set. -#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENABLE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENABLE_BITS _u(0x80000000) -#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENABLE_MSB _u(31) -#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENABLE_LSB _u(31) -#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENABLE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP6_OUT_CONTROL_DOUBLE_BUFFERED -// Description : This endpoint is double buffered. -#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) -#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_DOUBLE_BUFFERED_MSB _u(30) -#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_DOUBLE_BUFFERED_LSB _u(30) -#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_PER_BUFF -// Description : Trigger an interrupt each time a buffer is done. -#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) -#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) -#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) -#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF -// Description : Trigger an interrupt each time both buffers are done. Only -// valid in double buffered mode. -#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) -#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) -#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) -#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE -// 0x0 -> Control -// 0x1 -> Isochronous -// 0x2 -> Bulk -// 0x3 -> Interrupt -#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) -#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) -#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) -#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) -#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) -#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) -#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_ON_STALL -// Description : Trigger an interrupt if a STALL is sent. Intended for debug -// only. -#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) -#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) -#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) -#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_ON_NAK -// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. -#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) -#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) -#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) -#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP6_OUT_CONTROL_BUFFER_ADDRESS -// Description : 64 byte aligned buffer address for this EP (bits 0-5 are -// ignored). Relative to the start of the DPRAM. -#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) -#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) -#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_BUFFER_ADDRESS_MSB _u(15) -#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_BUFFER_ADDRESS_LSB _u(0) -#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW" -// ============================================================================= -// Register : USB_DEVICE_DPRAM_EP7_IN_CONTROL -#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_OFFSET _u(0x00000038) -#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_BITS _u(0xfc03ffff) -#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENABLE -// Description : Enable this endpoint. The device will not reply to any packets -// for this endpoint if this bit is not set. -#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENABLE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENABLE_BITS _u(0x80000000) -#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENABLE_MSB _u(31) -#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENABLE_LSB _u(31) -#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENABLE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP7_IN_CONTROL_DOUBLE_BUFFERED -// Description : This endpoint is double buffered. -#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) -#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_DOUBLE_BUFFERED_MSB _u(30) -#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_DOUBLE_BUFFERED_LSB _u(30) -#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_PER_BUFF -// Description : Trigger an interrupt each time a buffer is done. -#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) -#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) -#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) -#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF -// Description : Trigger an interrupt each time both buffers are done. Only -// valid in double buffered mode. -#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) -#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) -#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) -#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE -// 0x0 -> Control -// 0x1 -> Isochronous -// 0x2 -> Bulk -// 0x3 -> Interrupt -#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) -#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) -#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) -#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) -#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) -#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) -#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_ON_STALL -// Description : Trigger an interrupt if a STALL is sent. Intended for debug -// only. -#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) -#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) -#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) -#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_ON_NAK -// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. -#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) -#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) -#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) -#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP7_IN_CONTROL_BUFFER_ADDRESS -// Description : 64 byte aligned buffer address for this EP (bits 0-5 are -// ignored). Relative to the start of the DPRAM. -#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) -#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) -#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_BUFFER_ADDRESS_MSB _u(15) -#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_BUFFER_ADDRESS_LSB _u(0) -#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW" -// ============================================================================= -// Register : USB_DEVICE_DPRAM_EP7_OUT_CONTROL -#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_OFFSET _u(0x0000003c) -#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_BITS _u(0xfc03ffff) -#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENABLE -// Description : Enable this endpoint. The device will not reply to any packets -// for this endpoint if this bit is not set. -#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENABLE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENABLE_BITS _u(0x80000000) -#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENABLE_MSB _u(31) -#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENABLE_LSB _u(31) -#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENABLE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP7_OUT_CONTROL_DOUBLE_BUFFERED -// Description : This endpoint is double buffered. -#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) -#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_DOUBLE_BUFFERED_MSB _u(30) -#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_DOUBLE_BUFFERED_LSB _u(30) -#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_PER_BUFF -// Description : Trigger an interrupt each time a buffer is done. -#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) -#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) -#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) -#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF -// Description : Trigger an interrupt each time both buffers are done. Only -// valid in double buffered mode. -#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) -#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) -#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) -#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE -// 0x0 -> Control -// 0x1 -> Isochronous -// 0x2 -> Bulk -// 0x3 -> Interrupt -#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) -#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) -#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) -#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) -#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) -#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) -#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_ON_STALL -// Description : Trigger an interrupt if a STALL is sent. Intended for debug -// only. -#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) -#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) -#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) -#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_ON_NAK -// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. -#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) -#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) -#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) -#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP7_OUT_CONTROL_BUFFER_ADDRESS -// Description : 64 byte aligned buffer address for this EP (bits 0-5 are -// ignored). Relative to the start of the DPRAM. -#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) -#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) -#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_BUFFER_ADDRESS_MSB _u(15) -#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_BUFFER_ADDRESS_LSB _u(0) -#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW" -// ============================================================================= -// Register : USB_DEVICE_DPRAM_EP8_IN_CONTROL -#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_OFFSET _u(0x00000040) -#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_BITS _u(0xfc03ffff) -#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENABLE -// Description : Enable this endpoint. The device will not reply to any packets -// for this endpoint if this bit is not set. -#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENABLE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENABLE_BITS _u(0x80000000) -#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENABLE_MSB _u(31) -#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENABLE_LSB _u(31) -#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENABLE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP8_IN_CONTROL_DOUBLE_BUFFERED -// Description : This endpoint is double buffered. -#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) -#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_DOUBLE_BUFFERED_MSB _u(30) -#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_DOUBLE_BUFFERED_LSB _u(30) -#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_PER_BUFF -// Description : Trigger an interrupt each time a buffer is done. -#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) -#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) -#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) -#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF -// Description : Trigger an interrupt each time both buffers are done. Only -// valid in double buffered mode. -#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) -#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) -#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) -#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE -// 0x0 -> Control -// 0x1 -> Isochronous -// 0x2 -> Bulk -// 0x3 -> Interrupt -#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) -#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) -#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) -#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) -#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) -#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) -#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_ON_STALL -// Description : Trigger an interrupt if a STALL is sent. Intended for debug -// only. -#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) -#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) -#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) -#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_ON_NAK -// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. -#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) -#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) -#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) -#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP8_IN_CONTROL_BUFFER_ADDRESS -// Description : 64 byte aligned buffer address for this EP (bits 0-5 are -// ignored). Relative to the start of the DPRAM. -#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) -#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) -#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_BUFFER_ADDRESS_MSB _u(15) -#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_BUFFER_ADDRESS_LSB _u(0) -#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW" -// ============================================================================= -// Register : USB_DEVICE_DPRAM_EP8_OUT_CONTROL -#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_OFFSET _u(0x00000044) -#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_BITS _u(0xfc03ffff) -#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENABLE -// Description : Enable this endpoint. The device will not reply to any packets -// for this endpoint if this bit is not set. -#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENABLE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENABLE_BITS _u(0x80000000) -#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENABLE_MSB _u(31) -#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENABLE_LSB _u(31) -#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENABLE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP8_OUT_CONTROL_DOUBLE_BUFFERED -// Description : This endpoint is double buffered. -#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) -#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_DOUBLE_BUFFERED_MSB _u(30) -#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_DOUBLE_BUFFERED_LSB _u(30) -#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_PER_BUFF -// Description : Trigger an interrupt each time a buffer is done. -#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) -#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) -#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) -#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF -// Description : Trigger an interrupt each time both buffers are done. Only -// valid in double buffered mode. -#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) -#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) -#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) -#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE -// 0x0 -> Control -// 0x1 -> Isochronous -// 0x2 -> Bulk -// 0x3 -> Interrupt -#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) -#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) -#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) -#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) -#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) -#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) -#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_ON_STALL -// Description : Trigger an interrupt if a STALL is sent. Intended for debug -// only. -#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) -#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) -#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) -#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_ON_NAK -// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. -#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) -#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) -#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) -#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP8_OUT_CONTROL_BUFFER_ADDRESS -// Description : 64 byte aligned buffer address for this EP (bits 0-5 are -// ignored). Relative to the start of the DPRAM. -#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) -#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) -#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_BUFFER_ADDRESS_MSB _u(15) -#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_BUFFER_ADDRESS_LSB _u(0) -#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW" -// ============================================================================= -// Register : USB_DEVICE_DPRAM_EP9_IN_CONTROL -#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_OFFSET _u(0x00000048) -#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_BITS _u(0xfc03ffff) -#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENABLE -// Description : Enable this endpoint. The device will not reply to any packets -// for this endpoint if this bit is not set. -#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENABLE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENABLE_BITS _u(0x80000000) -#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENABLE_MSB _u(31) -#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENABLE_LSB _u(31) -#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENABLE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP9_IN_CONTROL_DOUBLE_BUFFERED -// Description : This endpoint is double buffered. -#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) -#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_DOUBLE_BUFFERED_MSB _u(30) -#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_DOUBLE_BUFFERED_LSB _u(30) -#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_PER_BUFF -// Description : Trigger an interrupt each time a buffer is done. -#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) -#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) -#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) -#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF -// Description : Trigger an interrupt each time both buffers are done. Only -// valid in double buffered mode. -#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) -#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) -#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) -#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE -// 0x0 -> Control -// 0x1 -> Isochronous -// 0x2 -> Bulk -// 0x3 -> Interrupt -#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) -#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) -#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) -#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) -#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) -#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) -#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_ON_STALL -// Description : Trigger an interrupt if a STALL is sent. Intended for debug -// only. -#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) -#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) -#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) -#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_ON_NAK -// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. -#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) -#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) -#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) -#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP9_IN_CONTROL_BUFFER_ADDRESS -// Description : 64 byte aligned buffer address for this EP (bits 0-5 are -// ignored). Relative to the start of the DPRAM. -#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) -#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) -#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_BUFFER_ADDRESS_MSB _u(15) -#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_BUFFER_ADDRESS_LSB _u(0) -#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW" -// ============================================================================= -// Register : USB_DEVICE_DPRAM_EP9_OUT_CONTROL -#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_OFFSET _u(0x0000004c) -#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_BITS _u(0xfc03ffff) -#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENABLE -// Description : Enable this endpoint. The device will not reply to any packets -// for this endpoint if this bit is not set. -#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENABLE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENABLE_BITS _u(0x80000000) -#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENABLE_MSB _u(31) -#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENABLE_LSB _u(31) -#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENABLE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP9_OUT_CONTROL_DOUBLE_BUFFERED -// Description : This endpoint is double buffered. -#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) -#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_DOUBLE_BUFFERED_MSB _u(30) -#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_DOUBLE_BUFFERED_LSB _u(30) -#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_PER_BUFF -// Description : Trigger an interrupt each time a buffer is done. -#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) -#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) -#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) -#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF -// Description : Trigger an interrupt each time both buffers are done. Only -// valid in double buffered mode. -#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) -#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) -#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) -#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE -// 0x0 -> Control -// 0x1 -> Isochronous -// 0x2 -> Bulk -// 0x3 -> Interrupt -#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) -#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) -#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) -#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) -#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) -#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) -#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_ON_STALL -// Description : Trigger an interrupt if a STALL is sent. Intended for debug -// only. -#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) -#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) -#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) -#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_ON_NAK -// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. -#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) -#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) -#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) -#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP9_OUT_CONTROL_BUFFER_ADDRESS -// Description : 64 byte aligned buffer address for this EP (bits 0-5 are -// ignored). Relative to the start of the DPRAM. -#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) -#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) -#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_BUFFER_ADDRESS_MSB _u(15) -#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_BUFFER_ADDRESS_LSB _u(0) -#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW" -// ============================================================================= -// Register : USB_DEVICE_DPRAM_EP10_IN_CONTROL -#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_OFFSET _u(0x00000050) -#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_BITS _u(0xfc03ffff) -#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENABLE -// Description : Enable this endpoint. The device will not reply to any packets -// for this endpoint if this bit is not set. -#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENABLE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENABLE_BITS _u(0x80000000) -#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENABLE_MSB _u(31) -#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENABLE_LSB _u(31) -#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENABLE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP10_IN_CONTROL_DOUBLE_BUFFERED -// Description : This endpoint is double buffered. -#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) -#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_DOUBLE_BUFFERED_MSB _u(30) -#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_DOUBLE_BUFFERED_LSB _u(30) -#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_PER_BUFF -// Description : Trigger an interrupt each time a buffer is done. -#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) -#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) -#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) -#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF -// Description : Trigger an interrupt each time both buffers are done. Only -// valid in double buffered mode. -#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) -#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) -#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) -#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE -// 0x0 -> Control -// 0x1 -> Isochronous -// 0x2 -> Bulk -// 0x3 -> Interrupt -#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) -#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) -#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) -#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) -#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) -#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) -#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_ON_STALL -// Description : Trigger an interrupt if a STALL is sent. Intended for debug -// only. -#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) -#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) -#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) -#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_ON_NAK -// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. -#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) -#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) -#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) -#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP10_IN_CONTROL_BUFFER_ADDRESS -// Description : 64 byte aligned buffer address for this EP (bits 0-5 are -// ignored). Relative to the start of the DPRAM. -#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) -#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) -#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_BUFFER_ADDRESS_MSB _u(15) -#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_BUFFER_ADDRESS_LSB _u(0) -#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW" -// ============================================================================= -// Register : USB_DEVICE_DPRAM_EP10_OUT_CONTROL -#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_OFFSET _u(0x00000054) -#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_BITS _u(0xfc03ffff) -#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENABLE -// Description : Enable this endpoint. The device will not reply to any packets -// for this endpoint if this bit is not set. -#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENABLE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENABLE_BITS _u(0x80000000) -#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENABLE_MSB _u(31) -#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENABLE_LSB _u(31) -#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENABLE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP10_OUT_CONTROL_DOUBLE_BUFFERED -// Description : This endpoint is double buffered. -#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) -#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_DOUBLE_BUFFERED_MSB _u(30) -#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_DOUBLE_BUFFERED_LSB _u(30) -#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_PER_BUFF -// Description : Trigger an interrupt each time a buffer is done. -#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) -#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) -#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) -#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF -// Description : Trigger an interrupt each time both buffers are done. Only -// valid in double buffered mode. -#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) -#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) -#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) -#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE -// 0x0 -> Control -// 0x1 -> Isochronous -// 0x2 -> Bulk -// 0x3 -> Interrupt -#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) -#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) -#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) -#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) -#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) -#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) -#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_ON_STALL -// Description : Trigger an interrupt if a STALL is sent. Intended for debug -// only. -#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) -#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) -#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) -#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_ON_NAK -// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. -#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) -#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) -#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) -#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP10_OUT_CONTROL_BUFFER_ADDRESS -// Description : 64 byte aligned buffer address for this EP (bits 0-5 are -// ignored). Relative to the start of the DPRAM. -#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) -#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) -#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_BUFFER_ADDRESS_MSB _u(15) -#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_BUFFER_ADDRESS_LSB _u(0) -#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW" -// ============================================================================= -// Register : USB_DEVICE_DPRAM_EP11_IN_CONTROL -#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_OFFSET _u(0x00000058) -#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_BITS _u(0xfc03ffff) -#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENABLE -// Description : Enable this endpoint. The device will not reply to any packets -// for this endpoint if this bit is not set. -#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENABLE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENABLE_BITS _u(0x80000000) -#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENABLE_MSB _u(31) -#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENABLE_LSB _u(31) -#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENABLE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP11_IN_CONTROL_DOUBLE_BUFFERED -// Description : This endpoint is double buffered. -#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) -#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_DOUBLE_BUFFERED_MSB _u(30) -#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_DOUBLE_BUFFERED_LSB _u(30) -#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_PER_BUFF -// Description : Trigger an interrupt each time a buffer is done. -#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) -#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) -#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) -#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF -// Description : Trigger an interrupt each time both buffers are done. Only -// valid in double buffered mode. -#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) -#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) -#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) -#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE -// 0x0 -> Control -// 0x1 -> Isochronous -// 0x2 -> Bulk -// 0x3 -> Interrupt -#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) -#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) -#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) -#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) -#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) -#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) -#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_ON_STALL -// Description : Trigger an interrupt if a STALL is sent. Intended for debug -// only. -#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) -#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) -#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) -#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_ON_NAK -// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. -#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) -#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) -#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) -#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP11_IN_CONTROL_BUFFER_ADDRESS -// Description : 64 byte aligned buffer address for this EP (bits 0-5 are -// ignored). Relative to the start of the DPRAM. -#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) -#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) -#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_BUFFER_ADDRESS_MSB _u(15) -#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_BUFFER_ADDRESS_LSB _u(0) -#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW" -// ============================================================================= -// Register : USB_DEVICE_DPRAM_EP11_OUT_CONTROL -#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_OFFSET _u(0x0000005c) -#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_BITS _u(0xfc03ffff) -#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENABLE -// Description : Enable this endpoint. The device will not reply to any packets -// for this endpoint if this bit is not set. -#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENABLE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENABLE_BITS _u(0x80000000) -#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENABLE_MSB _u(31) -#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENABLE_LSB _u(31) -#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENABLE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP11_OUT_CONTROL_DOUBLE_BUFFERED -// Description : This endpoint is double buffered. -#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) -#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_DOUBLE_BUFFERED_MSB _u(30) -#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_DOUBLE_BUFFERED_LSB _u(30) -#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_PER_BUFF -// Description : Trigger an interrupt each time a buffer is done. -#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) -#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) -#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) -#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF -// Description : Trigger an interrupt each time both buffers are done. Only -// valid in double buffered mode. -#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) -#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) -#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) -#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE -// 0x0 -> Control -// 0x1 -> Isochronous -// 0x2 -> Bulk -// 0x3 -> Interrupt -#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) -#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) -#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) -#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) -#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) -#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) -#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_ON_STALL -// Description : Trigger an interrupt if a STALL is sent. Intended for debug -// only. -#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) -#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) -#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) -#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_ON_NAK -// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. -#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) -#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) -#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) -#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP11_OUT_CONTROL_BUFFER_ADDRESS -// Description : 64 byte aligned buffer address for this EP (bits 0-5 are -// ignored). Relative to the start of the DPRAM. -#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) -#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) -#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_BUFFER_ADDRESS_MSB _u(15) -#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_BUFFER_ADDRESS_LSB _u(0) -#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW" -// ============================================================================= -// Register : USB_DEVICE_DPRAM_EP12_IN_CONTROL -#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_OFFSET _u(0x00000060) -#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_BITS _u(0xfc03ffff) -#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENABLE -// Description : Enable this endpoint. The device will not reply to any packets -// for this endpoint if this bit is not set. -#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENABLE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENABLE_BITS _u(0x80000000) -#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENABLE_MSB _u(31) -#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENABLE_LSB _u(31) -#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENABLE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP12_IN_CONTROL_DOUBLE_BUFFERED -// Description : This endpoint is double buffered. -#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) -#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_DOUBLE_BUFFERED_MSB _u(30) -#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_DOUBLE_BUFFERED_LSB _u(30) -#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_PER_BUFF -// Description : Trigger an interrupt each time a buffer is done. -#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) -#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) -#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) -#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF -// Description : Trigger an interrupt each time both buffers are done. Only -// valid in double buffered mode. -#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) -#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) -#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) -#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE -// 0x0 -> Control -// 0x1 -> Isochronous -// 0x2 -> Bulk -// 0x3 -> Interrupt -#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) -#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) -#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) -#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) -#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) -#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) -#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_ON_STALL -// Description : Trigger an interrupt if a STALL is sent. Intended for debug -// only. -#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) -#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) -#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) -#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_ON_NAK -// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. -#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) -#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) -#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) -#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP12_IN_CONTROL_BUFFER_ADDRESS -// Description : 64 byte aligned buffer address for this EP (bits 0-5 are -// ignored). Relative to the start of the DPRAM. -#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) -#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) -#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_BUFFER_ADDRESS_MSB _u(15) -#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_BUFFER_ADDRESS_LSB _u(0) -#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW" -// ============================================================================= -// Register : USB_DEVICE_DPRAM_EP12_OUT_CONTROL -#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_OFFSET _u(0x00000064) -#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_BITS _u(0xfc03ffff) -#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENABLE -// Description : Enable this endpoint. The device will not reply to any packets -// for this endpoint if this bit is not set. -#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENABLE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENABLE_BITS _u(0x80000000) -#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENABLE_MSB _u(31) -#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENABLE_LSB _u(31) -#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENABLE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP12_OUT_CONTROL_DOUBLE_BUFFERED -// Description : This endpoint is double buffered. -#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) -#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_DOUBLE_BUFFERED_MSB _u(30) -#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_DOUBLE_BUFFERED_LSB _u(30) -#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_PER_BUFF -// Description : Trigger an interrupt each time a buffer is done. -#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) -#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) -#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) -#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF -// Description : Trigger an interrupt each time both buffers are done. Only -// valid in double buffered mode. -#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) -#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) -#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) -#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE -// 0x0 -> Control -// 0x1 -> Isochronous -// 0x2 -> Bulk -// 0x3 -> Interrupt -#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) -#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) -#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) -#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) -#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) -#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) -#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_ON_STALL -// Description : Trigger an interrupt if a STALL is sent. Intended for debug -// only. -#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) -#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) -#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) -#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_ON_NAK -// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. -#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) -#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) -#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) -#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP12_OUT_CONTROL_BUFFER_ADDRESS -// Description : 64 byte aligned buffer address for this EP (bits 0-5 are -// ignored). Relative to the start of the DPRAM. -#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) -#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) -#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_BUFFER_ADDRESS_MSB _u(15) -#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_BUFFER_ADDRESS_LSB _u(0) -#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW" -// ============================================================================= -// Register : USB_DEVICE_DPRAM_EP13_IN_CONTROL -#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_OFFSET _u(0x00000068) -#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_BITS _u(0xfc03ffff) -#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENABLE -// Description : Enable this endpoint. The device will not reply to any packets -// for this endpoint if this bit is not set. -#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENABLE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENABLE_BITS _u(0x80000000) -#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENABLE_MSB _u(31) -#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENABLE_LSB _u(31) -#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENABLE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP13_IN_CONTROL_DOUBLE_BUFFERED -// Description : This endpoint is double buffered. -#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) -#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_DOUBLE_BUFFERED_MSB _u(30) -#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_DOUBLE_BUFFERED_LSB _u(30) -#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_PER_BUFF -// Description : Trigger an interrupt each time a buffer is done. -#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) -#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) -#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) -#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF -// Description : Trigger an interrupt each time both buffers are done. Only -// valid in double buffered mode. -#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) -#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) -#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) -#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE -// 0x0 -> Control -// 0x1 -> Isochronous -// 0x2 -> Bulk -// 0x3 -> Interrupt -#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) -#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) -#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) -#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) -#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) -#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) -#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_ON_STALL -// Description : Trigger an interrupt if a STALL is sent. Intended for debug -// only. -#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) -#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) -#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) -#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_ON_NAK -// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. -#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) -#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) -#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) -#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP13_IN_CONTROL_BUFFER_ADDRESS -// Description : 64 byte aligned buffer address for this EP (bits 0-5 are -// ignored). Relative to the start of the DPRAM. -#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) -#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) -#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_BUFFER_ADDRESS_MSB _u(15) -#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_BUFFER_ADDRESS_LSB _u(0) -#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW" -// ============================================================================= -// Register : USB_DEVICE_DPRAM_EP13_OUT_CONTROL -#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_OFFSET _u(0x0000006c) -#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_BITS _u(0xfc03ffff) -#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENABLE -// Description : Enable this endpoint. The device will not reply to any packets -// for this endpoint if this bit is not set. -#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENABLE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENABLE_BITS _u(0x80000000) -#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENABLE_MSB _u(31) -#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENABLE_LSB _u(31) -#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENABLE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP13_OUT_CONTROL_DOUBLE_BUFFERED -// Description : This endpoint is double buffered. -#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) -#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_DOUBLE_BUFFERED_MSB _u(30) -#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_DOUBLE_BUFFERED_LSB _u(30) -#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_PER_BUFF -// Description : Trigger an interrupt each time a buffer is done. -#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) -#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) -#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) -#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF -// Description : Trigger an interrupt each time both buffers are done. Only -// valid in double buffered mode. -#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) -#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) -#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) -#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE -// 0x0 -> Control -// 0x1 -> Isochronous -// 0x2 -> Bulk -// 0x3 -> Interrupt -#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) -#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) -#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) -#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) -#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) -#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) -#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_ON_STALL -// Description : Trigger an interrupt if a STALL is sent. Intended for debug -// only. -#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) -#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) -#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) -#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_ON_NAK -// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. -#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) -#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) -#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) -#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP13_OUT_CONTROL_BUFFER_ADDRESS -// Description : 64 byte aligned buffer address for this EP (bits 0-5 are -// ignored). Relative to the start of the DPRAM. -#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) -#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) -#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_BUFFER_ADDRESS_MSB _u(15) -#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_BUFFER_ADDRESS_LSB _u(0) -#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW" -// ============================================================================= -// Register : USB_DEVICE_DPRAM_EP14_IN_CONTROL -#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_OFFSET _u(0x00000070) -#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_BITS _u(0xfc03ffff) -#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENABLE -// Description : Enable this endpoint. The device will not reply to any packets -// for this endpoint if this bit is not set. -#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENABLE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENABLE_BITS _u(0x80000000) -#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENABLE_MSB _u(31) -#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENABLE_LSB _u(31) -#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENABLE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP14_IN_CONTROL_DOUBLE_BUFFERED -// Description : This endpoint is double buffered. -#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) -#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_DOUBLE_BUFFERED_MSB _u(30) -#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_DOUBLE_BUFFERED_LSB _u(30) -#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_PER_BUFF -// Description : Trigger an interrupt each time a buffer is done. -#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) -#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) -#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) -#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF -// Description : Trigger an interrupt each time both buffers are done. Only -// valid in double buffered mode. -#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) -#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) -#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) -#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE -// 0x0 -> Control -// 0x1 -> Isochronous -// 0x2 -> Bulk -// 0x3 -> Interrupt -#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) -#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) -#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) -#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) -#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) -#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) -#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_ON_STALL -// Description : Trigger an interrupt if a STALL is sent. Intended for debug -// only. -#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) -#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) -#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) -#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_ON_NAK -// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. -#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) -#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) -#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) -#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP14_IN_CONTROL_BUFFER_ADDRESS -// Description : 64 byte aligned buffer address for this EP (bits 0-5 are -// ignored). Relative to the start of the DPRAM. -#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) -#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) -#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_BUFFER_ADDRESS_MSB _u(15) -#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_BUFFER_ADDRESS_LSB _u(0) -#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW" -// ============================================================================= -// Register : USB_DEVICE_DPRAM_EP14_OUT_CONTROL -#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_OFFSET _u(0x00000074) -#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_BITS _u(0xfc03ffff) -#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENABLE -// Description : Enable this endpoint. The device will not reply to any packets -// for this endpoint if this bit is not set. -#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENABLE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENABLE_BITS _u(0x80000000) -#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENABLE_MSB _u(31) -#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENABLE_LSB _u(31) -#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENABLE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP14_OUT_CONTROL_DOUBLE_BUFFERED -// Description : This endpoint is double buffered. -#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) -#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_DOUBLE_BUFFERED_MSB _u(30) -#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_DOUBLE_BUFFERED_LSB _u(30) -#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_PER_BUFF -// Description : Trigger an interrupt each time a buffer is done. -#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) -#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) -#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) -#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF -// Description : Trigger an interrupt each time both buffers are done. Only -// valid in double buffered mode. -#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) -#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) -#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) -#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE -// 0x0 -> Control -// 0x1 -> Isochronous -// 0x2 -> Bulk -// 0x3 -> Interrupt -#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) -#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) -#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) -#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) -#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) -#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) -#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_ON_STALL -// Description : Trigger an interrupt if a STALL is sent. Intended for debug -// only. -#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) -#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) -#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) -#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_ON_NAK -// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. -#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) -#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) -#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) -#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP14_OUT_CONTROL_BUFFER_ADDRESS -// Description : 64 byte aligned buffer address for this EP (bits 0-5 are -// ignored). Relative to the start of the DPRAM. -#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) -#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) -#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_BUFFER_ADDRESS_MSB _u(15) -#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_BUFFER_ADDRESS_LSB _u(0) -#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW" -// ============================================================================= -// Register : USB_DEVICE_DPRAM_EP15_IN_CONTROL -#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_OFFSET _u(0x00000078) -#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_BITS _u(0xfc03ffff) -#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENABLE -// Description : Enable this endpoint. The device will not reply to any packets -// for this endpoint if this bit is not set. -#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENABLE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENABLE_BITS _u(0x80000000) -#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENABLE_MSB _u(31) -#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENABLE_LSB _u(31) -#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENABLE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP15_IN_CONTROL_DOUBLE_BUFFERED -// Description : This endpoint is double buffered. -#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) -#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_DOUBLE_BUFFERED_MSB _u(30) -#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_DOUBLE_BUFFERED_LSB _u(30) -#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_PER_BUFF -// Description : Trigger an interrupt each time a buffer is done. -#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) -#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) -#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) -#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF -// Description : Trigger an interrupt each time both buffers are done. Only -// valid in double buffered mode. -#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) -#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) -#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) -#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE -// 0x0 -> Control -// 0x1 -> Isochronous -// 0x2 -> Bulk -// 0x3 -> Interrupt -#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) -#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) -#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) -#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) -#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) -#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) -#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_ON_STALL -// Description : Trigger an interrupt if a STALL is sent. Intended for debug -// only. -#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) -#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) -#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) -#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_ON_NAK -// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. -#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) -#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) -#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) -#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP15_IN_CONTROL_BUFFER_ADDRESS -// Description : 64 byte aligned buffer address for this EP (bits 0-5 are -// ignored). Relative to the start of the DPRAM. -#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) -#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) -#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_BUFFER_ADDRESS_MSB _u(15) -#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_BUFFER_ADDRESS_LSB _u(0) -#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW" -// ============================================================================= -// Register : USB_DEVICE_DPRAM_EP15_OUT_CONTROL -#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_OFFSET _u(0x0000007c) -#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_BITS _u(0xfc03ffff) -#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENABLE -// Description : Enable this endpoint. The device will not reply to any packets -// for this endpoint if this bit is not set. -#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENABLE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENABLE_BITS _u(0x80000000) -#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENABLE_MSB _u(31) -#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENABLE_LSB _u(31) -#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENABLE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP15_OUT_CONTROL_DOUBLE_BUFFERED -// Description : This endpoint is double buffered. -#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) -#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_DOUBLE_BUFFERED_MSB _u(30) -#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_DOUBLE_BUFFERED_LSB _u(30) -#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_PER_BUFF -// Description : Trigger an interrupt each time a buffer is done. -#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) -#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) -#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) -#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF -// Description : Trigger an interrupt each time both buffers are done. Only -// valid in double buffered mode. -#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) -#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) -#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) -#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE -// 0x0 -> Control -// 0x1 -> Isochronous -// 0x2 -> Bulk -// 0x3 -> Interrupt -#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) -#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) -#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) -#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) -#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) -#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) -#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_ON_STALL -// Description : Trigger an interrupt if a STALL is sent. Intended for debug -// only. -#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) -#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) -#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) -#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_ON_NAK -// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. -#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) -#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) -#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) -#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP15_OUT_CONTROL_BUFFER_ADDRESS -// Description : 64 byte aligned buffer address for this EP (bits 0-5 are -// ignored). Relative to the start of the DPRAM. -#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) -#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) -#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_BUFFER_ADDRESS_MSB _u(15) -#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_BUFFER_ADDRESS_LSB _u(0) -#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW" -// ============================================================================= -// Register : USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL -// Description : Buffer control for both buffers of an endpoint. Fields ending -// in a _1 are for buffer 1. -// Fields ending in a _0 are for buffer 0. Buffer 1 controls are -// only valid if the endpoint is in double buffered mode. -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_OFFSET _u(0x00000080) -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_BITS _u(0xffffffff) -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_FULL_1 -// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit -// is set to indicate the data is valid. For an OUT transfer (RX -// from the host) this bit should be left as a 0. The host will -// set it when it has filled the buffer with data. -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_FULL_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_FULL_1_MSB _u(31) -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_FULL_1_LSB _u(31) -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LAST_1 -// Description : Buffer 1 is the last buffer of the transfer. -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LAST_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LAST_1_MSB _u(30) -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LAST_1_LSB _u(30) -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_PID_1 -// Description : The data pid of buffer 1. -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_PID_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_PID_1_MSB _u(29) -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_PID_1_LSB _u(29) -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_PID_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET -// Description : The number of bytes buffer 1 is offset from buffer 0 in -// Isochronous mode. Only valid in double buffered mode for an -// Isochronous endpoint. -// For a non Isochronous endpoint the offset is always 64 bytes. -// 0x0 -> 128 -// 0x1 -> 256 -// 0x2 -> 512 -// 0x3 -> 1024 -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_AVAILABLE_1 -// Description : Buffer 1 is available. This bit is set to indicate the buffer -// can be used by the controller. The controller clears the -// available bit when writing the status back. -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_1 -// Description : The length of the data in buffer 1. -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_1_MSB _u(25) -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_1_LSB _u(16) -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_FULL_0 -// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit -// is set to indicate the data is valid. For an OUT transfer (RX -// from the host) this bit should be left as a 0. The host will -// set it when it has filled the buffer with data. -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_FULL_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_FULL_0_MSB _u(15) -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_FULL_0_LSB _u(15) -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LAST_0 -// Description : Buffer 0 is the last buffer of the transfer. -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LAST_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LAST_0_MSB _u(14) -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LAST_0_LSB _u(14) -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_PID_0 -// Description : The data pid of buffer 0. -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_PID_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_PID_0_MSB _u(13) -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_PID_0_LSB _u(13) -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_PID_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_RESET -// Description : Reset the buffer selector to buffer 0. -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_RESET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_RESET_BITS _u(0x00001000) -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_RESET_MSB _u(12) -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_RESET_LSB _u(12) -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_RESET_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_STALL -// Description : Reply with a stall (valid for both buffers). -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_STALL_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_STALL_BITS _u(0x00000800) -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_STALL_MSB _u(11) -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_STALL_LSB _u(11) -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_STALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_AVAILABLE_0 -// Description : Buffer 0 is available. This bit is set to indicate the buffer -// can be used by the controller. The controller clears the -// available bit when writing the status back. -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_0 -// Description : The length of the data in buffer 0. -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_0_MSB _u(9) -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_0_LSB _u(0) -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" -// ============================================================================= -// Register : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL -// Description : Buffer control for both buffers of an endpoint. Fields ending -// in a _1 are for buffer 1. -// Fields ending in a _0 are for buffer 0. Buffer 1 controls are -// only valid if the endpoint is in double buffered mode. -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_OFFSET _u(0x00000084) -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_BITS _u(0xffffffff) -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_FULL_1 -// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit -// is set to indicate the data is valid. For an OUT transfer (RX -// from the host) this bit should be left as a 0. The host will -// set it when it has filled the buffer with data. -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_FULL_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_FULL_1_MSB _u(31) -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_FULL_1_LSB _u(31) -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LAST_1 -// Description : Buffer 1 is the last buffer of the transfer. -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LAST_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LAST_1_MSB _u(30) -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LAST_1_LSB _u(30) -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_PID_1 -// Description : The data pid of buffer 1. -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_PID_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_PID_1_MSB _u(29) -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_PID_1_LSB _u(29) -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET -// Description : The number of bytes buffer 1 is offset from buffer 0 in -// Isochronous mode. Only valid in double buffered mode for an -// Isochronous endpoint. -// For a non Isochronous endpoint the offset is always 64 bytes. -// 0x0 -> 128 -// 0x1 -> 256 -// 0x2 -> 512 -// 0x3 -> 1024 -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_AVAILABLE_1 -// Description : Buffer 1 is available. This bit is set to indicate the buffer -// can be used by the controller. The controller clears the -// available bit when writing the status back. -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_1 -// Description : The length of the data in buffer 1. -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_1_MSB _u(25) -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_1_LSB _u(16) -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_FULL_0 -// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit -// is set to indicate the data is valid. For an OUT transfer (RX -// from the host) this bit should be left as a 0. The host will -// set it when it has filled the buffer with data. -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_FULL_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_FULL_0_MSB _u(15) -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_FULL_0_LSB _u(15) -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LAST_0 -// Description : Buffer 0 is the last buffer of the transfer. -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LAST_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LAST_0_MSB _u(14) -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LAST_0_LSB _u(14) -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_PID_0 -// Description : The data pid of buffer 0. -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_PID_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_PID_0_MSB _u(13) -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_PID_0_LSB _u(13) -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_RESET -// Description : Reset the buffer selector to buffer 0. -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_RESET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_RESET_BITS _u(0x00001000) -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_RESET_MSB _u(12) -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_RESET_LSB _u(12) -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_RESET_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_STALL -// Description : Reply with a stall (valid for both buffers). -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_STALL_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_STALL_BITS _u(0x00000800) -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_STALL_MSB _u(11) -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_STALL_LSB _u(11) -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_STALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_AVAILABLE_0 -// Description : Buffer 0 is available. This bit is set to indicate the buffer -// can be used by the controller. The controller clears the -// available bit when writing the status back. -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_0 -// Description : The length of the data in buffer 0. -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_0_MSB _u(9) -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_0_LSB _u(0) -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" -// ============================================================================= -// Register : USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL -// Description : Buffer control for both buffers of an endpoint. Fields ending -// in a _1 are for buffer 1. -// Fields ending in a _0 are for buffer 0. Buffer 1 controls are -// only valid if the endpoint is in double buffered mode. -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_OFFSET _u(0x00000088) -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_BITS _u(0xffffffff) -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_FULL_1 -// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit -// is set to indicate the data is valid. For an OUT transfer (RX -// from the host) this bit should be left as a 0. The host will -// set it when it has filled the buffer with data. -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_FULL_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_FULL_1_MSB _u(31) -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_FULL_1_LSB _u(31) -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LAST_1 -// Description : Buffer 1 is the last buffer of the transfer. -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LAST_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LAST_1_MSB _u(30) -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LAST_1_LSB _u(30) -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_PID_1 -// Description : The data pid of buffer 1. -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_PID_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_PID_1_MSB _u(29) -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_PID_1_LSB _u(29) -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_PID_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET -// Description : The number of bytes buffer 1 is offset from buffer 0 in -// Isochronous mode. Only valid in double buffered mode for an -// Isochronous endpoint. -// For a non Isochronous endpoint the offset is always 64 bytes. -// 0x0 -> 128 -// 0x1 -> 256 -// 0x2 -> 512 -// 0x3 -> 1024 -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_AVAILABLE_1 -// Description : Buffer 1 is available. This bit is set to indicate the buffer -// can be used by the controller. The controller clears the -// available bit when writing the status back. -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_1 -// Description : The length of the data in buffer 1. -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_1_MSB _u(25) -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_1_LSB _u(16) -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_FULL_0 -// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit -// is set to indicate the data is valid. For an OUT transfer (RX -// from the host) this bit should be left as a 0. The host will -// set it when it has filled the buffer with data. -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_FULL_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_FULL_0_MSB _u(15) -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_FULL_0_LSB _u(15) -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LAST_0 -// Description : Buffer 0 is the last buffer of the transfer. -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LAST_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LAST_0_MSB _u(14) -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LAST_0_LSB _u(14) -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_PID_0 -// Description : The data pid of buffer 0. -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_PID_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_PID_0_MSB _u(13) -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_PID_0_LSB _u(13) -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_PID_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_RESET -// Description : Reset the buffer selector to buffer 0. -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_RESET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_RESET_BITS _u(0x00001000) -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_RESET_MSB _u(12) -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_RESET_LSB _u(12) -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_RESET_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_STALL -// Description : Reply with a stall (valid for both buffers). -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_STALL_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_STALL_BITS _u(0x00000800) -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_STALL_MSB _u(11) -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_STALL_LSB _u(11) -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_STALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_AVAILABLE_0 -// Description : Buffer 0 is available. This bit is set to indicate the buffer -// can be used by the controller. The controller clears the -// available bit when writing the status back. -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_0 -// Description : The length of the data in buffer 0. -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_0_MSB _u(9) -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_0_LSB _u(0) -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" -// ============================================================================= -// Register : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL -// Description : Buffer control for both buffers of an endpoint. Fields ending -// in a _1 are for buffer 1. -// Fields ending in a _0 are for buffer 0. Buffer 1 controls are -// only valid if the endpoint is in double buffered mode. -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_OFFSET _u(0x0000008c) -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_BITS _u(0xffffffff) -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_FULL_1 -// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit -// is set to indicate the data is valid. For an OUT transfer (RX -// from the host) this bit should be left as a 0. The host will -// set it when it has filled the buffer with data. -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_FULL_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_FULL_1_MSB _u(31) -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_FULL_1_LSB _u(31) -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LAST_1 -// Description : Buffer 1 is the last buffer of the transfer. -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LAST_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LAST_1_MSB _u(30) -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LAST_1_LSB _u(30) -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_PID_1 -// Description : The data pid of buffer 1. -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_PID_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_PID_1_MSB _u(29) -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_PID_1_LSB _u(29) -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET -// Description : The number of bytes buffer 1 is offset from buffer 0 in -// Isochronous mode. Only valid in double buffered mode for an -// Isochronous endpoint. -// For a non Isochronous endpoint the offset is always 64 bytes. -// 0x0 -> 128 -// 0x1 -> 256 -// 0x2 -> 512 -// 0x3 -> 1024 -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_AVAILABLE_1 -// Description : Buffer 1 is available. This bit is set to indicate the buffer -// can be used by the controller. The controller clears the -// available bit when writing the status back. -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_1 -// Description : The length of the data in buffer 1. -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_1_MSB _u(25) -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_1_LSB _u(16) -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_FULL_0 -// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit -// is set to indicate the data is valid. For an OUT transfer (RX -// from the host) this bit should be left as a 0. The host will -// set it when it has filled the buffer with data. -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_FULL_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_FULL_0_MSB _u(15) -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_FULL_0_LSB _u(15) -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LAST_0 -// Description : Buffer 0 is the last buffer of the transfer. -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LAST_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LAST_0_MSB _u(14) -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LAST_0_LSB _u(14) -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_PID_0 -// Description : The data pid of buffer 0. -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_PID_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_PID_0_MSB _u(13) -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_PID_0_LSB _u(13) -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_RESET -// Description : Reset the buffer selector to buffer 0. -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_RESET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_RESET_BITS _u(0x00001000) -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_RESET_MSB _u(12) -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_RESET_LSB _u(12) -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_RESET_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_STALL -// Description : Reply with a stall (valid for both buffers). -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_STALL_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_STALL_BITS _u(0x00000800) -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_STALL_MSB _u(11) -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_STALL_LSB _u(11) -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_STALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_AVAILABLE_0 -// Description : Buffer 0 is available. This bit is set to indicate the buffer -// can be used by the controller. The controller clears the -// available bit when writing the status back. -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_0 -// Description : The length of the data in buffer 0. -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_0_MSB _u(9) -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_0_LSB _u(0) -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" -// ============================================================================= -// Register : USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL -// Description : Buffer control for both buffers of an endpoint. Fields ending -// in a _1 are for buffer 1. -// Fields ending in a _0 are for buffer 0. Buffer 1 controls are -// only valid if the endpoint is in double buffered mode. -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_OFFSET _u(0x00000090) -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_BITS _u(0xffffffff) -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_FULL_1 -// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit -// is set to indicate the data is valid. For an OUT transfer (RX -// from the host) this bit should be left as a 0. The host will -// set it when it has filled the buffer with data. -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_FULL_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_FULL_1_MSB _u(31) -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_FULL_1_LSB _u(31) -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LAST_1 -// Description : Buffer 1 is the last buffer of the transfer. -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LAST_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LAST_1_MSB _u(30) -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LAST_1_LSB _u(30) -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_PID_1 -// Description : The data pid of buffer 1. -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_PID_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_PID_1_MSB _u(29) -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_PID_1_LSB _u(29) -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_PID_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET -// Description : The number of bytes buffer 1 is offset from buffer 0 in -// Isochronous mode. Only valid in double buffered mode for an -// Isochronous endpoint. -// For a non Isochronous endpoint the offset is always 64 bytes. -// 0x0 -> 128 -// 0x1 -> 256 -// 0x2 -> 512 -// 0x3 -> 1024 -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_AVAILABLE_1 -// Description : Buffer 1 is available. This bit is set to indicate the buffer -// can be used by the controller. The controller clears the -// available bit when writing the status back. -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_1 -// Description : The length of the data in buffer 1. -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_1_MSB _u(25) -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_1_LSB _u(16) -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_FULL_0 -// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit -// is set to indicate the data is valid. For an OUT transfer (RX -// from the host) this bit should be left as a 0. The host will -// set it when it has filled the buffer with data. -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_FULL_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_FULL_0_MSB _u(15) -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_FULL_0_LSB _u(15) -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LAST_0 -// Description : Buffer 0 is the last buffer of the transfer. -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LAST_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LAST_0_MSB _u(14) -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LAST_0_LSB _u(14) -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_PID_0 -// Description : The data pid of buffer 0. -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_PID_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_PID_0_MSB _u(13) -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_PID_0_LSB _u(13) -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_PID_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_RESET -// Description : Reset the buffer selector to buffer 0. -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_RESET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_RESET_BITS _u(0x00001000) -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_RESET_MSB _u(12) -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_RESET_LSB _u(12) -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_RESET_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_STALL -// Description : Reply with a stall (valid for both buffers). -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_STALL_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_STALL_BITS _u(0x00000800) -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_STALL_MSB _u(11) -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_STALL_LSB _u(11) -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_STALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_AVAILABLE_0 -// Description : Buffer 0 is available. This bit is set to indicate the buffer -// can be used by the controller. The controller clears the -// available bit when writing the status back. -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_0 -// Description : The length of the data in buffer 0. -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_0_MSB _u(9) -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_0_LSB _u(0) -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" -// ============================================================================= -// Register : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL -// Description : Buffer control for both buffers of an endpoint. Fields ending -// in a _1 are for buffer 1. -// Fields ending in a _0 are for buffer 0. Buffer 1 controls are -// only valid if the endpoint is in double buffered mode. -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_OFFSET _u(0x00000094) -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_BITS _u(0xffffffff) -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_FULL_1 -// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit -// is set to indicate the data is valid. For an OUT transfer (RX -// from the host) this bit should be left as a 0. The host will -// set it when it has filled the buffer with data. -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_FULL_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_FULL_1_MSB _u(31) -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_FULL_1_LSB _u(31) -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LAST_1 -// Description : Buffer 1 is the last buffer of the transfer. -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LAST_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LAST_1_MSB _u(30) -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LAST_1_LSB _u(30) -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_PID_1 -// Description : The data pid of buffer 1. -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_PID_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_PID_1_MSB _u(29) -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_PID_1_LSB _u(29) -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET -// Description : The number of bytes buffer 1 is offset from buffer 0 in -// Isochronous mode. Only valid in double buffered mode for an -// Isochronous endpoint. -// For a non Isochronous endpoint the offset is always 64 bytes. -// 0x0 -> 128 -// 0x1 -> 256 -// 0x2 -> 512 -// 0x3 -> 1024 -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_AVAILABLE_1 -// Description : Buffer 1 is available. This bit is set to indicate the buffer -// can be used by the controller. The controller clears the -// available bit when writing the status back. -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_1 -// Description : The length of the data in buffer 1. -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_1_MSB _u(25) -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_1_LSB _u(16) -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_FULL_0 -// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit -// is set to indicate the data is valid. For an OUT transfer (RX -// from the host) this bit should be left as a 0. The host will -// set it when it has filled the buffer with data. -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_FULL_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_FULL_0_MSB _u(15) -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_FULL_0_LSB _u(15) -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LAST_0 -// Description : Buffer 0 is the last buffer of the transfer. -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LAST_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LAST_0_MSB _u(14) -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LAST_0_LSB _u(14) -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_PID_0 -// Description : The data pid of buffer 0. -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_PID_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_PID_0_MSB _u(13) -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_PID_0_LSB _u(13) -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_RESET -// Description : Reset the buffer selector to buffer 0. -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_RESET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_RESET_BITS _u(0x00001000) -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_RESET_MSB _u(12) -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_RESET_LSB _u(12) -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_RESET_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_STALL -// Description : Reply with a stall (valid for both buffers). -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_STALL_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_STALL_BITS _u(0x00000800) -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_STALL_MSB _u(11) -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_STALL_LSB _u(11) -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_STALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_AVAILABLE_0 -// Description : Buffer 0 is available. This bit is set to indicate the buffer -// can be used by the controller. The controller clears the -// available bit when writing the status back. -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_0 -// Description : The length of the data in buffer 0. -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_0_MSB _u(9) -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_0_LSB _u(0) -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" -// ============================================================================= -// Register : USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL -// Description : Buffer control for both buffers of an endpoint. Fields ending -// in a _1 are for buffer 1. -// Fields ending in a _0 are for buffer 0. Buffer 1 controls are -// only valid if the endpoint is in double buffered mode. -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_OFFSET _u(0x00000098) -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_BITS _u(0xffffffff) -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_FULL_1 -// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit -// is set to indicate the data is valid. For an OUT transfer (RX -// from the host) this bit should be left as a 0. The host will -// set it when it has filled the buffer with data. -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_FULL_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_FULL_1_MSB _u(31) -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_FULL_1_LSB _u(31) -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LAST_1 -// Description : Buffer 1 is the last buffer of the transfer. -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LAST_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LAST_1_MSB _u(30) -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LAST_1_LSB _u(30) -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_PID_1 -// Description : The data pid of buffer 1. -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_PID_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_PID_1_MSB _u(29) -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_PID_1_LSB _u(29) -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_PID_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET -// Description : The number of bytes buffer 1 is offset from buffer 0 in -// Isochronous mode. Only valid in double buffered mode for an -// Isochronous endpoint. -// For a non Isochronous endpoint the offset is always 64 bytes. -// 0x0 -> 128 -// 0x1 -> 256 -// 0x2 -> 512 -// 0x3 -> 1024 -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_AVAILABLE_1 -// Description : Buffer 1 is available. This bit is set to indicate the buffer -// can be used by the controller. The controller clears the -// available bit when writing the status back. -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_1 -// Description : The length of the data in buffer 1. -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_1_MSB _u(25) -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_1_LSB _u(16) -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_FULL_0 -// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit -// is set to indicate the data is valid. For an OUT transfer (RX -// from the host) this bit should be left as a 0. The host will -// set it when it has filled the buffer with data. -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_FULL_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_FULL_0_MSB _u(15) -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_FULL_0_LSB _u(15) -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LAST_0 -// Description : Buffer 0 is the last buffer of the transfer. -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LAST_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LAST_0_MSB _u(14) -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LAST_0_LSB _u(14) -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_PID_0 -// Description : The data pid of buffer 0. -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_PID_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_PID_0_MSB _u(13) -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_PID_0_LSB _u(13) -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_PID_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_RESET -// Description : Reset the buffer selector to buffer 0. -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_RESET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_RESET_BITS _u(0x00001000) -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_RESET_MSB _u(12) -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_RESET_LSB _u(12) -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_RESET_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_STALL -// Description : Reply with a stall (valid for both buffers). -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_STALL_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_STALL_BITS _u(0x00000800) -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_STALL_MSB _u(11) -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_STALL_LSB _u(11) -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_STALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_AVAILABLE_0 -// Description : Buffer 0 is available. This bit is set to indicate the buffer -// can be used by the controller. The controller clears the -// available bit when writing the status back. -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_0 -// Description : The length of the data in buffer 0. -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_0_MSB _u(9) -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_0_LSB _u(0) -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" -// ============================================================================= -// Register : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL -// Description : Buffer control for both buffers of an endpoint. Fields ending -// in a _1 are for buffer 1. -// Fields ending in a _0 are for buffer 0. Buffer 1 controls are -// only valid if the endpoint is in double buffered mode. -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_OFFSET _u(0x0000009c) -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_BITS _u(0xffffffff) -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_FULL_1 -// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit -// is set to indicate the data is valid. For an OUT transfer (RX -// from the host) this bit should be left as a 0. The host will -// set it when it has filled the buffer with data. -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_FULL_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_FULL_1_MSB _u(31) -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_FULL_1_LSB _u(31) -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LAST_1 -// Description : Buffer 1 is the last buffer of the transfer. -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LAST_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LAST_1_MSB _u(30) -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LAST_1_LSB _u(30) -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_PID_1 -// Description : The data pid of buffer 1. -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_PID_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_PID_1_MSB _u(29) -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_PID_1_LSB _u(29) -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET -// Description : The number of bytes buffer 1 is offset from buffer 0 in -// Isochronous mode. Only valid in double buffered mode for an -// Isochronous endpoint. -// For a non Isochronous endpoint the offset is always 64 bytes. -// 0x0 -> 128 -// 0x1 -> 256 -// 0x2 -> 512 -// 0x3 -> 1024 -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_AVAILABLE_1 -// Description : Buffer 1 is available. This bit is set to indicate the buffer -// can be used by the controller. The controller clears the -// available bit when writing the status back. -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_1 -// Description : The length of the data in buffer 1. -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_1_MSB _u(25) -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_1_LSB _u(16) -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_FULL_0 -// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit -// is set to indicate the data is valid. For an OUT transfer (RX -// from the host) this bit should be left as a 0. The host will -// set it when it has filled the buffer with data. -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_FULL_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_FULL_0_MSB _u(15) -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_FULL_0_LSB _u(15) -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LAST_0 -// Description : Buffer 0 is the last buffer of the transfer. -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LAST_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LAST_0_MSB _u(14) -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LAST_0_LSB _u(14) -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_PID_0 -// Description : The data pid of buffer 0. -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_PID_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_PID_0_MSB _u(13) -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_PID_0_LSB _u(13) -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_RESET -// Description : Reset the buffer selector to buffer 0. -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_RESET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_RESET_BITS _u(0x00001000) -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_RESET_MSB _u(12) -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_RESET_LSB _u(12) -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_RESET_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_STALL -// Description : Reply with a stall (valid for both buffers). -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_STALL_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_STALL_BITS _u(0x00000800) -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_STALL_MSB _u(11) -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_STALL_LSB _u(11) -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_STALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_AVAILABLE_0 -// Description : Buffer 0 is available. This bit is set to indicate the buffer -// can be used by the controller. The controller clears the -// available bit when writing the status back. -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_0 -// Description : The length of the data in buffer 0. -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_0_MSB _u(9) -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_0_LSB _u(0) -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" -// ============================================================================= -// Register : USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL -// Description : Buffer control for both buffers of an endpoint. Fields ending -// in a _1 are for buffer 1. -// Fields ending in a _0 are for buffer 0. Buffer 1 controls are -// only valid if the endpoint is in double buffered mode. -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_OFFSET _u(0x000000a0) -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_BITS _u(0xffffffff) -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_FULL_1 -// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit -// is set to indicate the data is valid. For an OUT transfer (RX -// from the host) this bit should be left as a 0. The host will -// set it when it has filled the buffer with data. -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_FULL_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_FULL_1_MSB _u(31) -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_FULL_1_LSB _u(31) -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LAST_1 -// Description : Buffer 1 is the last buffer of the transfer. -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LAST_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LAST_1_MSB _u(30) -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LAST_1_LSB _u(30) -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_PID_1 -// Description : The data pid of buffer 1. -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_PID_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_PID_1_MSB _u(29) -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_PID_1_LSB _u(29) -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_PID_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET -// Description : The number of bytes buffer 1 is offset from buffer 0 in -// Isochronous mode. Only valid in double buffered mode for an -// Isochronous endpoint. -// For a non Isochronous endpoint the offset is always 64 bytes. -// 0x0 -> 128 -// 0x1 -> 256 -// 0x2 -> 512 -// 0x3 -> 1024 -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_AVAILABLE_1 -// Description : Buffer 1 is available. This bit is set to indicate the buffer -// can be used by the controller. The controller clears the -// available bit when writing the status back. -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_1 -// Description : The length of the data in buffer 1. -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_1_MSB _u(25) -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_1_LSB _u(16) -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_FULL_0 -// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit -// is set to indicate the data is valid. For an OUT transfer (RX -// from the host) this bit should be left as a 0. The host will -// set it when it has filled the buffer with data. -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_FULL_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_FULL_0_MSB _u(15) -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_FULL_0_LSB _u(15) -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LAST_0 -// Description : Buffer 0 is the last buffer of the transfer. -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LAST_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LAST_0_MSB _u(14) -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LAST_0_LSB _u(14) -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_PID_0 -// Description : The data pid of buffer 0. -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_PID_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_PID_0_MSB _u(13) -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_PID_0_LSB _u(13) -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_PID_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_RESET -// Description : Reset the buffer selector to buffer 0. -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_RESET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_RESET_BITS _u(0x00001000) -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_RESET_MSB _u(12) -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_RESET_LSB _u(12) -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_RESET_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_STALL -// Description : Reply with a stall (valid for both buffers). -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_STALL_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_STALL_BITS _u(0x00000800) -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_STALL_MSB _u(11) -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_STALL_LSB _u(11) -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_STALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_AVAILABLE_0 -// Description : Buffer 0 is available. This bit is set to indicate the buffer -// can be used by the controller. The controller clears the -// available bit when writing the status back. -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_0 -// Description : The length of the data in buffer 0. -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_0_MSB _u(9) -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_0_LSB _u(0) -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" -// ============================================================================= -// Register : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL -// Description : Buffer control for both buffers of an endpoint. Fields ending -// in a _1 are for buffer 1. -// Fields ending in a _0 are for buffer 0. Buffer 1 controls are -// only valid if the endpoint is in double buffered mode. -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_OFFSET _u(0x000000a4) -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_BITS _u(0xffffffff) -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_FULL_1 -// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit -// is set to indicate the data is valid. For an OUT transfer (RX -// from the host) this bit should be left as a 0. The host will -// set it when it has filled the buffer with data. -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_FULL_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_FULL_1_MSB _u(31) -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_FULL_1_LSB _u(31) -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LAST_1 -// Description : Buffer 1 is the last buffer of the transfer. -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LAST_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LAST_1_MSB _u(30) -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LAST_1_LSB _u(30) -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_PID_1 -// Description : The data pid of buffer 1. -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_PID_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_PID_1_MSB _u(29) -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_PID_1_LSB _u(29) -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET -// Description : The number of bytes buffer 1 is offset from buffer 0 in -// Isochronous mode. Only valid in double buffered mode for an -// Isochronous endpoint. -// For a non Isochronous endpoint the offset is always 64 bytes. -// 0x0 -> 128 -// 0x1 -> 256 -// 0x2 -> 512 -// 0x3 -> 1024 -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_AVAILABLE_1 -// Description : Buffer 1 is available. This bit is set to indicate the buffer -// can be used by the controller. The controller clears the -// available bit when writing the status back. -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_1 -// Description : The length of the data in buffer 1. -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_1_MSB _u(25) -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_1_LSB _u(16) -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_FULL_0 -// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit -// is set to indicate the data is valid. For an OUT transfer (RX -// from the host) this bit should be left as a 0. The host will -// set it when it has filled the buffer with data. -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_FULL_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_FULL_0_MSB _u(15) -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_FULL_0_LSB _u(15) -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LAST_0 -// Description : Buffer 0 is the last buffer of the transfer. -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LAST_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LAST_0_MSB _u(14) -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LAST_0_LSB _u(14) -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_PID_0 -// Description : The data pid of buffer 0. -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_PID_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_PID_0_MSB _u(13) -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_PID_0_LSB _u(13) -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_RESET -// Description : Reset the buffer selector to buffer 0. -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_RESET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_RESET_BITS _u(0x00001000) -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_RESET_MSB _u(12) -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_RESET_LSB _u(12) -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_RESET_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_STALL -// Description : Reply with a stall (valid for both buffers). -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_STALL_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_STALL_BITS _u(0x00000800) -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_STALL_MSB _u(11) -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_STALL_LSB _u(11) -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_STALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_AVAILABLE_0 -// Description : Buffer 0 is available. This bit is set to indicate the buffer -// can be used by the controller. The controller clears the -// available bit when writing the status back. -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_0 -// Description : The length of the data in buffer 0. -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_0_MSB _u(9) -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_0_LSB _u(0) -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" -// ============================================================================= -// Register : USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL -// Description : Buffer control for both buffers of an endpoint. Fields ending -// in a _1 are for buffer 1. -// Fields ending in a _0 are for buffer 0. Buffer 1 controls are -// only valid if the endpoint is in double buffered mode. -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_OFFSET _u(0x000000a8) -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_BITS _u(0xffffffff) -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_FULL_1 -// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit -// is set to indicate the data is valid. For an OUT transfer (RX -// from the host) this bit should be left as a 0. The host will -// set it when it has filled the buffer with data. -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_FULL_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_FULL_1_MSB _u(31) -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_FULL_1_LSB _u(31) -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LAST_1 -// Description : Buffer 1 is the last buffer of the transfer. -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LAST_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LAST_1_MSB _u(30) -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LAST_1_LSB _u(30) -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_PID_1 -// Description : The data pid of buffer 1. -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_PID_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_PID_1_MSB _u(29) -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_PID_1_LSB _u(29) -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_PID_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET -// Description : The number of bytes buffer 1 is offset from buffer 0 in -// Isochronous mode. Only valid in double buffered mode for an -// Isochronous endpoint. -// For a non Isochronous endpoint the offset is always 64 bytes. -// 0x0 -> 128 -// 0x1 -> 256 -// 0x2 -> 512 -// 0x3 -> 1024 -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_AVAILABLE_1 -// Description : Buffer 1 is available. This bit is set to indicate the buffer -// can be used by the controller. The controller clears the -// available bit when writing the status back. -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_1 -// Description : The length of the data in buffer 1. -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_1_MSB _u(25) -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_1_LSB _u(16) -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_FULL_0 -// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit -// is set to indicate the data is valid. For an OUT transfer (RX -// from the host) this bit should be left as a 0. The host will -// set it when it has filled the buffer with data. -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_FULL_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_FULL_0_MSB _u(15) -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_FULL_0_LSB _u(15) -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LAST_0 -// Description : Buffer 0 is the last buffer of the transfer. -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LAST_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LAST_0_MSB _u(14) -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LAST_0_LSB _u(14) -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_PID_0 -// Description : The data pid of buffer 0. -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_PID_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_PID_0_MSB _u(13) -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_PID_0_LSB _u(13) -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_PID_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_RESET -// Description : Reset the buffer selector to buffer 0. -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_RESET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_RESET_BITS _u(0x00001000) -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_RESET_MSB _u(12) -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_RESET_LSB _u(12) -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_RESET_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_STALL -// Description : Reply with a stall (valid for both buffers). -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_STALL_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_STALL_BITS _u(0x00000800) -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_STALL_MSB _u(11) -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_STALL_LSB _u(11) -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_STALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_AVAILABLE_0 -// Description : Buffer 0 is available. This bit is set to indicate the buffer -// can be used by the controller. The controller clears the -// available bit when writing the status back. -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_0 -// Description : The length of the data in buffer 0. -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_0_MSB _u(9) -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_0_LSB _u(0) -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" -// ============================================================================= -// Register : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL -// Description : Buffer control for both buffers of an endpoint. Fields ending -// in a _1 are for buffer 1. -// Fields ending in a _0 are for buffer 0. Buffer 1 controls are -// only valid if the endpoint is in double buffered mode. -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_OFFSET _u(0x000000ac) -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_BITS _u(0xffffffff) -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_FULL_1 -// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit -// is set to indicate the data is valid. For an OUT transfer (RX -// from the host) this bit should be left as a 0. The host will -// set it when it has filled the buffer with data. -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_FULL_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_FULL_1_MSB _u(31) -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_FULL_1_LSB _u(31) -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LAST_1 -// Description : Buffer 1 is the last buffer of the transfer. -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LAST_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LAST_1_MSB _u(30) -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LAST_1_LSB _u(30) -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_PID_1 -// Description : The data pid of buffer 1. -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_PID_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_PID_1_MSB _u(29) -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_PID_1_LSB _u(29) -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET -// Description : The number of bytes buffer 1 is offset from buffer 0 in -// Isochronous mode. Only valid in double buffered mode for an -// Isochronous endpoint. -// For a non Isochronous endpoint the offset is always 64 bytes. -// 0x0 -> 128 -// 0x1 -> 256 -// 0x2 -> 512 -// 0x3 -> 1024 -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_AVAILABLE_1 -// Description : Buffer 1 is available. This bit is set to indicate the buffer -// can be used by the controller. The controller clears the -// available bit when writing the status back. -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_1 -// Description : The length of the data in buffer 1. -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_1_MSB _u(25) -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_1_LSB _u(16) -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_FULL_0 -// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit -// is set to indicate the data is valid. For an OUT transfer (RX -// from the host) this bit should be left as a 0. The host will -// set it when it has filled the buffer with data. -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_FULL_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_FULL_0_MSB _u(15) -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_FULL_0_LSB _u(15) -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LAST_0 -// Description : Buffer 0 is the last buffer of the transfer. -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LAST_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LAST_0_MSB _u(14) -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LAST_0_LSB _u(14) -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_PID_0 -// Description : The data pid of buffer 0. -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_PID_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_PID_0_MSB _u(13) -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_PID_0_LSB _u(13) -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_RESET -// Description : Reset the buffer selector to buffer 0. -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_RESET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_RESET_BITS _u(0x00001000) -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_RESET_MSB _u(12) -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_RESET_LSB _u(12) -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_RESET_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_STALL -// Description : Reply with a stall (valid for both buffers). -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_STALL_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_STALL_BITS _u(0x00000800) -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_STALL_MSB _u(11) -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_STALL_LSB _u(11) -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_STALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_AVAILABLE_0 -// Description : Buffer 0 is available. This bit is set to indicate the buffer -// can be used by the controller. The controller clears the -// available bit when writing the status back. -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_0 -// Description : The length of the data in buffer 0. -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_0_MSB _u(9) -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_0_LSB _u(0) -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" -// ============================================================================= -// Register : USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL -// Description : Buffer control for both buffers of an endpoint. Fields ending -// in a _1 are for buffer 1. -// Fields ending in a _0 are for buffer 0. Buffer 1 controls are -// only valid if the endpoint is in double buffered mode. -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_OFFSET _u(0x000000b0) -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_BITS _u(0xffffffff) -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_FULL_1 -// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit -// is set to indicate the data is valid. For an OUT transfer (RX -// from the host) this bit should be left as a 0. The host will -// set it when it has filled the buffer with data. -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_FULL_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_FULL_1_MSB _u(31) -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_FULL_1_LSB _u(31) -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LAST_1 -// Description : Buffer 1 is the last buffer of the transfer. -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LAST_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LAST_1_MSB _u(30) -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LAST_1_LSB _u(30) -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_PID_1 -// Description : The data pid of buffer 1. -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_PID_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_PID_1_MSB _u(29) -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_PID_1_LSB _u(29) -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_PID_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET -// Description : The number of bytes buffer 1 is offset from buffer 0 in -// Isochronous mode. Only valid in double buffered mode for an -// Isochronous endpoint. -// For a non Isochronous endpoint the offset is always 64 bytes. -// 0x0 -> 128 -// 0x1 -> 256 -// 0x2 -> 512 -// 0x3 -> 1024 -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_AVAILABLE_1 -// Description : Buffer 1 is available. This bit is set to indicate the buffer -// can be used by the controller. The controller clears the -// available bit when writing the status back. -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_1 -// Description : The length of the data in buffer 1. -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_1_MSB _u(25) -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_1_LSB _u(16) -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_FULL_0 -// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit -// is set to indicate the data is valid. For an OUT transfer (RX -// from the host) this bit should be left as a 0. The host will -// set it when it has filled the buffer with data. -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_FULL_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_FULL_0_MSB _u(15) -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_FULL_0_LSB _u(15) -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LAST_0 -// Description : Buffer 0 is the last buffer of the transfer. -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LAST_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LAST_0_MSB _u(14) -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LAST_0_LSB _u(14) -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_PID_0 -// Description : The data pid of buffer 0. -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_PID_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_PID_0_MSB _u(13) -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_PID_0_LSB _u(13) -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_PID_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_RESET -// Description : Reset the buffer selector to buffer 0. -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_RESET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_RESET_BITS _u(0x00001000) -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_RESET_MSB _u(12) -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_RESET_LSB _u(12) -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_RESET_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_STALL -// Description : Reply with a stall (valid for both buffers). -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_STALL_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_STALL_BITS _u(0x00000800) -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_STALL_MSB _u(11) -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_STALL_LSB _u(11) -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_STALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_AVAILABLE_0 -// Description : Buffer 0 is available. This bit is set to indicate the buffer -// can be used by the controller. The controller clears the -// available bit when writing the status back. -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_0 -// Description : The length of the data in buffer 0. -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_0_MSB _u(9) -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_0_LSB _u(0) -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" -// ============================================================================= -// Register : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL -// Description : Buffer control for both buffers of an endpoint. Fields ending -// in a _1 are for buffer 1. -// Fields ending in a _0 are for buffer 0. Buffer 1 controls are -// only valid if the endpoint is in double buffered mode. -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_OFFSET _u(0x000000b4) -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_BITS _u(0xffffffff) -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_FULL_1 -// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit -// is set to indicate the data is valid. For an OUT transfer (RX -// from the host) this bit should be left as a 0. The host will -// set it when it has filled the buffer with data. -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_FULL_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_FULL_1_MSB _u(31) -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_FULL_1_LSB _u(31) -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LAST_1 -// Description : Buffer 1 is the last buffer of the transfer. -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LAST_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LAST_1_MSB _u(30) -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LAST_1_LSB _u(30) -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_PID_1 -// Description : The data pid of buffer 1. -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_PID_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_PID_1_MSB _u(29) -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_PID_1_LSB _u(29) -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET -// Description : The number of bytes buffer 1 is offset from buffer 0 in -// Isochronous mode. Only valid in double buffered mode for an -// Isochronous endpoint. -// For a non Isochronous endpoint the offset is always 64 bytes. -// 0x0 -> 128 -// 0x1 -> 256 -// 0x2 -> 512 -// 0x3 -> 1024 -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_AVAILABLE_1 -// Description : Buffer 1 is available. This bit is set to indicate the buffer -// can be used by the controller. The controller clears the -// available bit when writing the status back. -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_1 -// Description : The length of the data in buffer 1. -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_1_MSB _u(25) -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_1_LSB _u(16) -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_FULL_0 -// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit -// is set to indicate the data is valid. For an OUT transfer (RX -// from the host) this bit should be left as a 0. The host will -// set it when it has filled the buffer with data. -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_FULL_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_FULL_0_MSB _u(15) -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_FULL_0_LSB _u(15) -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LAST_0 -// Description : Buffer 0 is the last buffer of the transfer. -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LAST_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LAST_0_MSB _u(14) -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LAST_0_LSB _u(14) -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_PID_0 -// Description : The data pid of buffer 0. -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_PID_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_PID_0_MSB _u(13) -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_PID_0_LSB _u(13) -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_RESET -// Description : Reset the buffer selector to buffer 0. -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_RESET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_RESET_BITS _u(0x00001000) -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_RESET_MSB _u(12) -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_RESET_LSB _u(12) -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_RESET_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_STALL -// Description : Reply with a stall (valid for both buffers). -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_STALL_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_STALL_BITS _u(0x00000800) -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_STALL_MSB _u(11) -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_STALL_LSB _u(11) -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_STALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_AVAILABLE_0 -// Description : Buffer 0 is available. This bit is set to indicate the buffer -// can be used by the controller. The controller clears the -// available bit when writing the status back. -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_0 -// Description : The length of the data in buffer 0. -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_0_MSB _u(9) -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_0_LSB _u(0) -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" -// ============================================================================= -// Register : USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL -// Description : Buffer control for both buffers of an endpoint. Fields ending -// in a _1 are for buffer 1. -// Fields ending in a _0 are for buffer 0. Buffer 1 controls are -// only valid if the endpoint is in double buffered mode. -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_OFFSET _u(0x000000b8) -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_BITS _u(0xffffffff) -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_FULL_1 -// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit -// is set to indicate the data is valid. For an OUT transfer (RX -// from the host) this bit should be left as a 0. The host will -// set it when it has filled the buffer with data. -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_FULL_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_FULL_1_MSB _u(31) -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_FULL_1_LSB _u(31) -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LAST_1 -// Description : Buffer 1 is the last buffer of the transfer. -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LAST_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LAST_1_MSB _u(30) -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LAST_1_LSB _u(30) -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_PID_1 -// Description : The data pid of buffer 1. -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_PID_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_PID_1_MSB _u(29) -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_PID_1_LSB _u(29) -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_PID_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET -// Description : The number of bytes buffer 1 is offset from buffer 0 in -// Isochronous mode. Only valid in double buffered mode for an -// Isochronous endpoint. -// For a non Isochronous endpoint the offset is always 64 bytes. -// 0x0 -> 128 -// 0x1 -> 256 -// 0x2 -> 512 -// 0x3 -> 1024 -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_AVAILABLE_1 -// Description : Buffer 1 is available. This bit is set to indicate the buffer -// can be used by the controller. The controller clears the -// available bit when writing the status back. -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_1 -// Description : The length of the data in buffer 1. -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_1_MSB _u(25) -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_1_LSB _u(16) -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_FULL_0 -// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit -// is set to indicate the data is valid. For an OUT transfer (RX -// from the host) this bit should be left as a 0. The host will -// set it when it has filled the buffer with data. -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_FULL_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_FULL_0_MSB _u(15) -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_FULL_0_LSB _u(15) -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LAST_0 -// Description : Buffer 0 is the last buffer of the transfer. -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LAST_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LAST_0_MSB _u(14) -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LAST_0_LSB _u(14) -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_PID_0 -// Description : The data pid of buffer 0. -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_PID_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_PID_0_MSB _u(13) -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_PID_0_LSB _u(13) -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_PID_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_RESET -// Description : Reset the buffer selector to buffer 0. -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_RESET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_RESET_BITS _u(0x00001000) -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_RESET_MSB _u(12) -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_RESET_LSB _u(12) -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_RESET_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_STALL -// Description : Reply with a stall (valid for both buffers). -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_STALL_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_STALL_BITS _u(0x00000800) -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_STALL_MSB _u(11) -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_STALL_LSB _u(11) -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_STALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_AVAILABLE_0 -// Description : Buffer 0 is available. This bit is set to indicate the buffer -// can be used by the controller. The controller clears the -// available bit when writing the status back. -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_0 -// Description : The length of the data in buffer 0. -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_0_MSB _u(9) -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_0_LSB _u(0) -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" -// ============================================================================= -// Register : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL -// Description : Buffer control for both buffers of an endpoint. Fields ending -// in a _1 are for buffer 1. -// Fields ending in a _0 are for buffer 0. Buffer 1 controls are -// only valid if the endpoint is in double buffered mode. -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_OFFSET _u(0x000000bc) -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_BITS _u(0xffffffff) -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_FULL_1 -// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit -// is set to indicate the data is valid. For an OUT transfer (RX -// from the host) this bit should be left as a 0. The host will -// set it when it has filled the buffer with data. -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_FULL_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_FULL_1_MSB _u(31) -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_FULL_1_LSB _u(31) -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LAST_1 -// Description : Buffer 1 is the last buffer of the transfer. -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LAST_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LAST_1_MSB _u(30) -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LAST_1_LSB _u(30) -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_PID_1 -// Description : The data pid of buffer 1. -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_PID_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_PID_1_MSB _u(29) -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_PID_1_LSB _u(29) -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET -// Description : The number of bytes buffer 1 is offset from buffer 0 in -// Isochronous mode. Only valid in double buffered mode for an -// Isochronous endpoint. -// For a non Isochronous endpoint the offset is always 64 bytes. -// 0x0 -> 128 -// 0x1 -> 256 -// 0x2 -> 512 -// 0x3 -> 1024 -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_AVAILABLE_1 -// Description : Buffer 1 is available. This bit is set to indicate the buffer -// can be used by the controller. The controller clears the -// available bit when writing the status back. -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_1 -// Description : The length of the data in buffer 1. -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_1_MSB _u(25) -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_1_LSB _u(16) -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_FULL_0 -// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit -// is set to indicate the data is valid. For an OUT transfer (RX -// from the host) this bit should be left as a 0. The host will -// set it when it has filled the buffer with data. -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_FULL_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_FULL_0_MSB _u(15) -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_FULL_0_LSB _u(15) -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LAST_0 -// Description : Buffer 0 is the last buffer of the transfer. -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LAST_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LAST_0_MSB _u(14) -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LAST_0_LSB _u(14) -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_PID_0 -// Description : The data pid of buffer 0. -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_PID_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_PID_0_MSB _u(13) -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_PID_0_LSB _u(13) -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_RESET -// Description : Reset the buffer selector to buffer 0. -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_RESET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_RESET_BITS _u(0x00001000) -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_RESET_MSB _u(12) -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_RESET_LSB _u(12) -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_RESET_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_STALL -// Description : Reply with a stall (valid for both buffers). -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_STALL_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_STALL_BITS _u(0x00000800) -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_STALL_MSB _u(11) -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_STALL_LSB _u(11) -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_STALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_AVAILABLE_0 -// Description : Buffer 0 is available. This bit is set to indicate the buffer -// can be used by the controller. The controller clears the -// available bit when writing the status back. -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_0 -// Description : The length of the data in buffer 0. -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_0_MSB _u(9) -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_0_LSB _u(0) -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" -// ============================================================================= -// Register : USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL -// Description : Buffer control for both buffers of an endpoint. Fields ending -// in a _1 are for buffer 1. -// Fields ending in a _0 are for buffer 0. Buffer 1 controls are -// only valid if the endpoint is in double buffered mode. -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_OFFSET _u(0x000000c0) -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_BITS _u(0xffffffff) -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_FULL_1 -// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit -// is set to indicate the data is valid. For an OUT transfer (RX -// from the host) this bit should be left as a 0. The host will -// set it when it has filled the buffer with data. -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_FULL_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_FULL_1_MSB _u(31) -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_FULL_1_LSB _u(31) -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LAST_1 -// Description : Buffer 1 is the last buffer of the transfer. -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LAST_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LAST_1_MSB _u(30) -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LAST_1_LSB _u(30) -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_PID_1 -// Description : The data pid of buffer 1. -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_PID_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_PID_1_MSB _u(29) -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_PID_1_LSB _u(29) -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_PID_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET -// Description : The number of bytes buffer 1 is offset from buffer 0 in -// Isochronous mode. Only valid in double buffered mode for an -// Isochronous endpoint. -// For a non Isochronous endpoint the offset is always 64 bytes. -// 0x0 -> 128 -// 0x1 -> 256 -// 0x2 -> 512 -// 0x3 -> 1024 -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_AVAILABLE_1 -// Description : Buffer 1 is available. This bit is set to indicate the buffer -// can be used by the controller. The controller clears the -// available bit when writing the status back. -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_1 -// Description : The length of the data in buffer 1. -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_1_MSB _u(25) -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_1_LSB _u(16) -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_FULL_0 -// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit -// is set to indicate the data is valid. For an OUT transfer (RX -// from the host) this bit should be left as a 0. The host will -// set it when it has filled the buffer with data. -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_FULL_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_FULL_0_MSB _u(15) -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_FULL_0_LSB _u(15) -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LAST_0 -// Description : Buffer 0 is the last buffer of the transfer. -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LAST_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LAST_0_MSB _u(14) -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LAST_0_LSB _u(14) -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_PID_0 -// Description : The data pid of buffer 0. -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_PID_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_PID_0_MSB _u(13) -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_PID_0_LSB _u(13) -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_PID_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_RESET -// Description : Reset the buffer selector to buffer 0. -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_RESET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_RESET_BITS _u(0x00001000) -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_RESET_MSB _u(12) -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_RESET_LSB _u(12) -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_RESET_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_STALL -// Description : Reply with a stall (valid for both buffers). -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_STALL_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_STALL_BITS _u(0x00000800) -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_STALL_MSB _u(11) -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_STALL_LSB _u(11) -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_STALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_AVAILABLE_0 -// Description : Buffer 0 is available. This bit is set to indicate the buffer -// can be used by the controller. The controller clears the -// available bit when writing the status back. -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_0 -// Description : The length of the data in buffer 0. -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_0_MSB _u(9) -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_0_LSB _u(0) -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" -// ============================================================================= -// Register : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL -// Description : Buffer control for both buffers of an endpoint. Fields ending -// in a _1 are for buffer 1. -// Fields ending in a _0 are for buffer 0. Buffer 1 controls are -// only valid if the endpoint is in double buffered mode. -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_OFFSET _u(0x000000c4) -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_BITS _u(0xffffffff) -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_FULL_1 -// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit -// is set to indicate the data is valid. For an OUT transfer (RX -// from the host) this bit should be left as a 0. The host will -// set it when it has filled the buffer with data. -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_FULL_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_FULL_1_MSB _u(31) -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_FULL_1_LSB _u(31) -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LAST_1 -// Description : Buffer 1 is the last buffer of the transfer. -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LAST_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LAST_1_MSB _u(30) -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LAST_1_LSB _u(30) -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_PID_1 -// Description : The data pid of buffer 1. -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_PID_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_PID_1_MSB _u(29) -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_PID_1_LSB _u(29) -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET -// Description : The number of bytes buffer 1 is offset from buffer 0 in -// Isochronous mode. Only valid in double buffered mode for an -// Isochronous endpoint. -// For a non Isochronous endpoint the offset is always 64 bytes. -// 0x0 -> 128 -// 0x1 -> 256 -// 0x2 -> 512 -// 0x3 -> 1024 -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_AVAILABLE_1 -// Description : Buffer 1 is available. This bit is set to indicate the buffer -// can be used by the controller. The controller clears the -// available bit when writing the status back. -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_1 -// Description : The length of the data in buffer 1. -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_1_MSB _u(25) -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_1_LSB _u(16) -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_FULL_0 -// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit -// is set to indicate the data is valid. For an OUT transfer (RX -// from the host) this bit should be left as a 0. The host will -// set it when it has filled the buffer with data. -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_FULL_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_FULL_0_MSB _u(15) -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_FULL_0_LSB _u(15) -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LAST_0 -// Description : Buffer 0 is the last buffer of the transfer. -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LAST_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LAST_0_MSB _u(14) -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LAST_0_LSB _u(14) -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_PID_0 -// Description : The data pid of buffer 0. -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_PID_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_PID_0_MSB _u(13) -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_PID_0_LSB _u(13) -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_RESET -// Description : Reset the buffer selector to buffer 0. -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_RESET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_RESET_BITS _u(0x00001000) -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_RESET_MSB _u(12) -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_RESET_LSB _u(12) -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_RESET_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_STALL -// Description : Reply with a stall (valid for both buffers). -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_STALL_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_STALL_BITS _u(0x00000800) -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_STALL_MSB _u(11) -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_STALL_LSB _u(11) -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_STALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_AVAILABLE_0 -// Description : Buffer 0 is available. This bit is set to indicate the buffer -// can be used by the controller. The controller clears the -// available bit when writing the status back. -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_0 -// Description : The length of the data in buffer 0. -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_0_MSB _u(9) -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_0_LSB _u(0) -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" -// ============================================================================= -// Register : USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL -// Description : Buffer control for both buffers of an endpoint. Fields ending -// in a _1 are for buffer 1. -// Fields ending in a _0 are for buffer 0. Buffer 1 controls are -// only valid if the endpoint is in double buffered mode. -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_OFFSET _u(0x000000c8) -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_BITS _u(0xffffffff) -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_FULL_1 -// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit -// is set to indicate the data is valid. For an OUT transfer (RX -// from the host) this bit should be left as a 0. The host will -// set it when it has filled the buffer with data. -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_FULL_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_FULL_1_MSB _u(31) -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_FULL_1_LSB _u(31) -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LAST_1 -// Description : Buffer 1 is the last buffer of the transfer. -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LAST_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LAST_1_MSB _u(30) -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LAST_1_LSB _u(30) -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_PID_1 -// Description : The data pid of buffer 1. -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_PID_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_PID_1_MSB _u(29) -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_PID_1_LSB _u(29) -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_PID_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET -// Description : The number of bytes buffer 1 is offset from buffer 0 in -// Isochronous mode. Only valid in double buffered mode for an -// Isochronous endpoint. -// For a non Isochronous endpoint the offset is always 64 bytes. -// 0x0 -> 128 -// 0x1 -> 256 -// 0x2 -> 512 -// 0x3 -> 1024 -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_AVAILABLE_1 -// Description : Buffer 1 is available. This bit is set to indicate the buffer -// can be used by the controller. The controller clears the -// available bit when writing the status back. -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_1 -// Description : The length of the data in buffer 1. -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_1_MSB _u(25) -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_1_LSB _u(16) -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_FULL_0 -// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit -// is set to indicate the data is valid. For an OUT transfer (RX -// from the host) this bit should be left as a 0. The host will -// set it when it has filled the buffer with data. -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_FULL_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_FULL_0_MSB _u(15) -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_FULL_0_LSB _u(15) -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LAST_0 -// Description : Buffer 0 is the last buffer of the transfer. -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LAST_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LAST_0_MSB _u(14) -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LAST_0_LSB _u(14) -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_PID_0 -// Description : The data pid of buffer 0. -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_PID_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_PID_0_MSB _u(13) -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_PID_0_LSB _u(13) -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_PID_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_RESET -// Description : Reset the buffer selector to buffer 0. -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_RESET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_RESET_BITS _u(0x00001000) -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_RESET_MSB _u(12) -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_RESET_LSB _u(12) -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_RESET_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_STALL -// Description : Reply with a stall (valid for both buffers). -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_STALL_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_STALL_BITS _u(0x00000800) -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_STALL_MSB _u(11) -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_STALL_LSB _u(11) -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_STALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_AVAILABLE_0 -// Description : Buffer 0 is available. This bit is set to indicate the buffer -// can be used by the controller. The controller clears the -// available bit when writing the status back. -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_0 -// Description : The length of the data in buffer 0. -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_0_MSB _u(9) -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_0_LSB _u(0) -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" -// ============================================================================= -// Register : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL -// Description : Buffer control for both buffers of an endpoint. Fields ending -// in a _1 are for buffer 1. -// Fields ending in a _0 are for buffer 0. Buffer 1 controls are -// only valid if the endpoint is in double buffered mode. -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_OFFSET _u(0x000000cc) -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_BITS _u(0xffffffff) -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_FULL_1 -// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit -// is set to indicate the data is valid. For an OUT transfer (RX -// from the host) this bit should be left as a 0. The host will -// set it when it has filled the buffer with data. -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_FULL_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_FULL_1_MSB _u(31) -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_FULL_1_LSB _u(31) -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LAST_1 -// Description : Buffer 1 is the last buffer of the transfer. -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LAST_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LAST_1_MSB _u(30) -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LAST_1_LSB _u(30) -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_PID_1 -// Description : The data pid of buffer 1. -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_PID_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_PID_1_MSB _u(29) -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_PID_1_LSB _u(29) -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET -// Description : The number of bytes buffer 1 is offset from buffer 0 in -// Isochronous mode. Only valid in double buffered mode for an -// Isochronous endpoint. -// For a non Isochronous endpoint the offset is always 64 bytes. -// 0x0 -> 128 -// 0x1 -> 256 -// 0x2 -> 512 -// 0x3 -> 1024 -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_AVAILABLE_1 -// Description : Buffer 1 is available. This bit is set to indicate the buffer -// can be used by the controller. The controller clears the -// available bit when writing the status back. -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_1 -// Description : The length of the data in buffer 1. -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_1_MSB _u(25) -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_1_LSB _u(16) -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_FULL_0 -// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit -// is set to indicate the data is valid. For an OUT transfer (RX -// from the host) this bit should be left as a 0. The host will -// set it when it has filled the buffer with data. -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_FULL_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_FULL_0_MSB _u(15) -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_FULL_0_LSB _u(15) -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LAST_0 -// Description : Buffer 0 is the last buffer of the transfer. -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LAST_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LAST_0_MSB _u(14) -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LAST_0_LSB _u(14) -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_PID_0 -// Description : The data pid of buffer 0. -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_PID_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_PID_0_MSB _u(13) -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_PID_0_LSB _u(13) -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_RESET -// Description : Reset the buffer selector to buffer 0. -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_RESET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_RESET_BITS _u(0x00001000) -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_RESET_MSB _u(12) -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_RESET_LSB _u(12) -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_RESET_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_STALL -// Description : Reply with a stall (valid for both buffers). -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_STALL_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_STALL_BITS _u(0x00000800) -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_STALL_MSB _u(11) -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_STALL_LSB _u(11) -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_STALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_AVAILABLE_0 -// Description : Buffer 0 is available. This bit is set to indicate the buffer -// can be used by the controller. The controller clears the -// available bit when writing the status back. -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_0 -// Description : The length of the data in buffer 0. -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_0_MSB _u(9) -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_0_LSB _u(0) -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" -// ============================================================================= -// Register : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL -// Description : Buffer control for both buffers of an endpoint. Fields ending -// in a _1 are for buffer 1. -// Fields ending in a _0 are for buffer 0. Buffer 1 controls are -// only valid if the endpoint is in double buffered mode. -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_OFFSET _u(0x000000d0) -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_BITS _u(0xffffffff) -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_FULL_1 -// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit -// is set to indicate the data is valid. For an OUT transfer (RX -// from the host) this bit should be left as a 0. The host will -// set it when it has filled the buffer with data. -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_FULL_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_FULL_1_MSB _u(31) -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_FULL_1_LSB _u(31) -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LAST_1 -// Description : Buffer 1 is the last buffer of the transfer. -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LAST_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LAST_1_MSB _u(30) -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LAST_1_LSB _u(30) -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_PID_1 -// Description : The data pid of buffer 1. -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_PID_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_PID_1_MSB _u(29) -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_PID_1_LSB _u(29) -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_PID_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET -// Description : The number of bytes buffer 1 is offset from buffer 0 in -// Isochronous mode. Only valid in double buffered mode for an -// Isochronous endpoint. -// For a non Isochronous endpoint the offset is always 64 bytes. -// 0x0 -> 128 -// 0x1 -> 256 -// 0x2 -> 512 -// 0x3 -> 1024 -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_AVAILABLE_1 -// Description : Buffer 1 is available. This bit is set to indicate the buffer -// can be used by the controller. The controller clears the -// available bit when writing the status back. -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_1 -// Description : The length of the data in buffer 1. -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_1_MSB _u(25) -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_1_LSB _u(16) -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_FULL_0 -// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit -// is set to indicate the data is valid. For an OUT transfer (RX -// from the host) this bit should be left as a 0. The host will -// set it when it has filled the buffer with data. -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_FULL_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_FULL_0_MSB _u(15) -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_FULL_0_LSB _u(15) -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LAST_0 -// Description : Buffer 0 is the last buffer of the transfer. -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LAST_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LAST_0_MSB _u(14) -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LAST_0_LSB _u(14) -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_PID_0 -// Description : The data pid of buffer 0. -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_PID_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_PID_0_MSB _u(13) -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_PID_0_LSB _u(13) -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_PID_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_RESET -// Description : Reset the buffer selector to buffer 0. -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_RESET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_RESET_BITS _u(0x00001000) -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_RESET_MSB _u(12) -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_RESET_LSB _u(12) -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_RESET_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_STALL -// Description : Reply with a stall (valid for both buffers). -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_STALL_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_STALL_BITS _u(0x00000800) -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_STALL_MSB _u(11) -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_STALL_LSB _u(11) -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_STALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_AVAILABLE_0 -// Description : Buffer 0 is available. This bit is set to indicate the buffer -// can be used by the controller. The controller clears the -// available bit when writing the status back. -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_0 -// Description : The length of the data in buffer 0. -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_0_MSB _u(9) -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_0_LSB _u(0) -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" -// ============================================================================= -// Register : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL -// Description : Buffer control for both buffers of an endpoint. Fields ending -// in a _1 are for buffer 1. -// Fields ending in a _0 are for buffer 0. Buffer 1 controls are -// only valid if the endpoint is in double buffered mode. -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_OFFSET _u(0x000000d4) -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_BITS _u(0xffffffff) -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_FULL_1 -// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit -// is set to indicate the data is valid. For an OUT transfer (RX -// from the host) this bit should be left as a 0. The host will -// set it when it has filled the buffer with data. -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_FULL_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_FULL_1_MSB _u(31) -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_FULL_1_LSB _u(31) -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LAST_1 -// Description : Buffer 1 is the last buffer of the transfer. -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LAST_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LAST_1_MSB _u(30) -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LAST_1_LSB _u(30) -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_PID_1 -// Description : The data pid of buffer 1. -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_PID_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_PID_1_MSB _u(29) -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_PID_1_LSB _u(29) -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET -// Description : The number of bytes buffer 1 is offset from buffer 0 in -// Isochronous mode. Only valid in double buffered mode for an -// Isochronous endpoint. -// For a non Isochronous endpoint the offset is always 64 bytes. -// 0x0 -> 128 -// 0x1 -> 256 -// 0x2 -> 512 -// 0x3 -> 1024 -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_AVAILABLE_1 -// Description : Buffer 1 is available. This bit is set to indicate the buffer -// can be used by the controller. The controller clears the -// available bit when writing the status back. -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_1 -// Description : The length of the data in buffer 1. -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_1_MSB _u(25) -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_1_LSB _u(16) -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_FULL_0 -// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit -// is set to indicate the data is valid. For an OUT transfer (RX -// from the host) this bit should be left as a 0. The host will -// set it when it has filled the buffer with data. -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_FULL_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_FULL_0_MSB _u(15) -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_FULL_0_LSB _u(15) -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LAST_0 -// Description : Buffer 0 is the last buffer of the transfer. -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LAST_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LAST_0_MSB _u(14) -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LAST_0_LSB _u(14) -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_PID_0 -// Description : The data pid of buffer 0. -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_PID_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_PID_0_MSB _u(13) -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_PID_0_LSB _u(13) -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_RESET -// Description : Reset the buffer selector to buffer 0. -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_RESET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_RESET_BITS _u(0x00001000) -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_RESET_MSB _u(12) -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_RESET_LSB _u(12) -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_RESET_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_STALL -// Description : Reply with a stall (valid for both buffers). -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_STALL_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_STALL_BITS _u(0x00000800) -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_STALL_MSB _u(11) -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_STALL_LSB _u(11) -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_STALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_AVAILABLE_0 -// Description : Buffer 0 is available. This bit is set to indicate the buffer -// can be used by the controller. The controller clears the -// available bit when writing the status back. -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_0 -// Description : The length of the data in buffer 0. -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_0_MSB _u(9) -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_0_LSB _u(0) -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" -// ============================================================================= -// Register : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL -// Description : Buffer control for both buffers of an endpoint. Fields ending -// in a _1 are for buffer 1. -// Fields ending in a _0 are for buffer 0. Buffer 1 controls are -// only valid if the endpoint is in double buffered mode. -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_OFFSET _u(0x000000d8) -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_BITS _u(0xffffffff) -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_FULL_1 -// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit -// is set to indicate the data is valid. For an OUT transfer (RX -// from the host) this bit should be left as a 0. The host will -// set it when it has filled the buffer with data. -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_FULL_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_FULL_1_MSB _u(31) -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_FULL_1_LSB _u(31) -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LAST_1 -// Description : Buffer 1 is the last buffer of the transfer. -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LAST_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LAST_1_MSB _u(30) -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LAST_1_LSB _u(30) -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_PID_1 -// Description : The data pid of buffer 1. -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_PID_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_PID_1_MSB _u(29) -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_PID_1_LSB _u(29) -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_PID_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET -// Description : The number of bytes buffer 1 is offset from buffer 0 in -// Isochronous mode. Only valid in double buffered mode for an -// Isochronous endpoint. -// For a non Isochronous endpoint the offset is always 64 bytes. -// 0x0 -> 128 -// 0x1 -> 256 -// 0x2 -> 512 -// 0x3 -> 1024 -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_AVAILABLE_1 -// Description : Buffer 1 is available. This bit is set to indicate the buffer -// can be used by the controller. The controller clears the -// available bit when writing the status back. -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_1 -// Description : The length of the data in buffer 1. -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_1_MSB _u(25) -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_1_LSB _u(16) -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_FULL_0 -// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit -// is set to indicate the data is valid. For an OUT transfer (RX -// from the host) this bit should be left as a 0. The host will -// set it when it has filled the buffer with data. -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_FULL_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_FULL_0_MSB _u(15) -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_FULL_0_LSB _u(15) -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LAST_0 -// Description : Buffer 0 is the last buffer of the transfer. -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LAST_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LAST_0_MSB _u(14) -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LAST_0_LSB _u(14) -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_PID_0 -// Description : The data pid of buffer 0. -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_PID_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_PID_0_MSB _u(13) -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_PID_0_LSB _u(13) -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_PID_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_RESET -// Description : Reset the buffer selector to buffer 0. -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_RESET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_RESET_BITS _u(0x00001000) -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_RESET_MSB _u(12) -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_RESET_LSB _u(12) -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_RESET_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_STALL -// Description : Reply with a stall (valid for both buffers). -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_STALL_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_STALL_BITS _u(0x00000800) -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_STALL_MSB _u(11) -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_STALL_LSB _u(11) -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_STALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_AVAILABLE_0 -// Description : Buffer 0 is available. This bit is set to indicate the buffer -// can be used by the controller. The controller clears the -// available bit when writing the status back. -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_0 -// Description : The length of the data in buffer 0. -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_0_MSB _u(9) -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_0_LSB _u(0) -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" -// ============================================================================= -// Register : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL -// Description : Buffer control for both buffers of an endpoint. Fields ending -// in a _1 are for buffer 1. -// Fields ending in a _0 are for buffer 0. Buffer 1 controls are -// only valid if the endpoint is in double buffered mode. -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_OFFSET _u(0x000000dc) -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_BITS _u(0xffffffff) -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_FULL_1 -// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit -// is set to indicate the data is valid. For an OUT transfer (RX -// from the host) this bit should be left as a 0. The host will -// set it when it has filled the buffer with data. -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_FULL_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_FULL_1_MSB _u(31) -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_FULL_1_LSB _u(31) -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LAST_1 -// Description : Buffer 1 is the last buffer of the transfer. -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LAST_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LAST_1_MSB _u(30) -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LAST_1_LSB _u(30) -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_PID_1 -// Description : The data pid of buffer 1. -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_PID_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_PID_1_MSB _u(29) -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_PID_1_LSB _u(29) -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET -// Description : The number of bytes buffer 1 is offset from buffer 0 in -// Isochronous mode. Only valid in double buffered mode for an -// Isochronous endpoint. -// For a non Isochronous endpoint the offset is always 64 bytes. -// 0x0 -> 128 -// 0x1 -> 256 -// 0x2 -> 512 -// 0x3 -> 1024 -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_AVAILABLE_1 -// Description : Buffer 1 is available. This bit is set to indicate the buffer -// can be used by the controller. The controller clears the -// available bit when writing the status back. -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_1 -// Description : The length of the data in buffer 1. -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_1_MSB _u(25) -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_1_LSB _u(16) -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_FULL_0 -// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit -// is set to indicate the data is valid. For an OUT transfer (RX -// from the host) this bit should be left as a 0. The host will -// set it when it has filled the buffer with data. -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_FULL_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_FULL_0_MSB _u(15) -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_FULL_0_LSB _u(15) -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LAST_0 -// Description : Buffer 0 is the last buffer of the transfer. -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LAST_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LAST_0_MSB _u(14) -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LAST_0_LSB _u(14) -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_PID_0 -// Description : The data pid of buffer 0. -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_PID_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_PID_0_MSB _u(13) -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_PID_0_LSB _u(13) -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_RESET -// Description : Reset the buffer selector to buffer 0. -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_RESET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_RESET_BITS _u(0x00001000) -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_RESET_MSB _u(12) -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_RESET_LSB _u(12) -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_RESET_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_STALL -// Description : Reply with a stall (valid for both buffers). -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_STALL_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_STALL_BITS _u(0x00000800) -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_STALL_MSB _u(11) -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_STALL_LSB _u(11) -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_STALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_AVAILABLE_0 -// Description : Buffer 0 is available. This bit is set to indicate the buffer -// can be used by the controller. The controller clears the -// available bit when writing the status back. -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_0 -// Description : The length of the data in buffer 0. -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_0_MSB _u(9) -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_0_LSB _u(0) -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" -// ============================================================================= -// Register : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL -// Description : Buffer control for both buffers of an endpoint. Fields ending -// in a _1 are for buffer 1. -// Fields ending in a _0 are for buffer 0. Buffer 1 controls are -// only valid if the endpoint is in double buffered mode. -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_OFFSET _u(0x000000e0) -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_BITS _u(0xffffffff) -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_FULL_1 -// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit -// is set to indicate the data is valid. For an OUT transfer (RX -// from the host) this bit should be left as a 0. The host will -// set it when it has filled the buffer with data. -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_FULL_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_FULL_1_MSB _u(31) -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_FULL_1_LSB _u(31) -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LAST_1 -// Description : Buffer 1 is the last buffer of the transfer. -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LAST_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LAST_1_MSB _u(30) -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LAST_1_LSB _u(30) -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_PID_1 -// Description : The data pid of buffer 1. -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_PID_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_PID_1_MSB _u(29) -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_PID_1_LSB _u(29) -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_PID_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET -// Description : The number of bytes buffer 1 is offset from buffer 0 in -// Isochronous mode. Only valid in double buffered mode for an -// Isochronous endpoint. -// For a non Isochronous endpoint the offset is always 64 bytes. -// 0x0 -> 128 -// 0x1 -> 256 -// 0x2 -> 512 -// 0x3 -> 1024 -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_AVAILABLE_1 -// Description : Buffer 1 is available. This bit is set to indicate the buffer -// can be used by the controller. The controller clears the -// available bit when writing the status back. -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_1 -// Description : The length of the data in buffer 1. -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_1_MSB _u(25) -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_1_LSB _u(16) -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_FULL_0 -// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit -// is set to indicate the data is valid. For an OUT transfer (RX -// from the host) this bit should be left as a 0. The host will -// set it when it has filled the buffer with data. -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_FULL_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_FULL_0_MSB _u(15) -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_FULL_0_LSB _u(15) -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LAST_0 -// Description : Buffer 0 is the last buffer of the transfer. -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LAST_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LAST_0_MSB _u(14) -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LAST_0_LSB _u(14) -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_PID_0 -// Description : The data pid of buffer 0. -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_PID_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_PID_0_MSB _u(13) -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_PID_0_LSB _u(13) -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_PID_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_RESET -// Description : Reset the buffer selector to buffer 0. -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_RESET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_RESET_BITS _u(0x00001000) -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_RESET_MSB _u(12) -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_RESET_LSB _u(12) -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_RESET_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_STALL -// Description : Reply with a stall (valid for both buffers). -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_STALL_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_STALL_BITS _u(0x00000800) -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_STALL_MSB _u(11) -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_STALL_LSB _u(11) -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_STALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_AVAILABLE_0 -// Description : Buffer 0 is available. This bit is set to indicate the buffer -// can be used by the controller. The controller clears the -// available bit when writing the status back. -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_0 -// Description : The length of the data in buffer 0. -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_0_MSB _u(9) -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_0_LSB _u(0) -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" -// ============================================================================= -// Register : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL -// Description : Buffer control for both buffers of an endpoint. Fields ending -// in a _1 are for buffer 1. -// Fields ending in a _0 are for buffer 0. Buffer 1 controls are -// only valid if the endpoint is in double buffered mode. -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_OFFSET _u(0x000000e4) -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_BITS _u(0xffffffff) -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_FULL_1 -// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit -// is set to indicate the data is valid. For an OUT transfer (RX -// from the host) this bit should be left as a 0. The host will -// set it when it has filled the buffer with data. -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_FULL_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_FULL_1_MSB _u(31) -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_FULL_1_LSB _u(31) -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LAST_1 -// Description : Buffer 1 is the last buffer of the transfer. -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LAST_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LAST_1_MSB _u(30) -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LAST_1_LSB _u(30) -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_PID_1 -// Description : The data pid of buffer 1. -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_PID_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_PID_1_MSB _u(29) -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_PID_1_LSB _u(29) -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET -// Description : The number of bytes buffer 1 is offset from buffer 0 in -// Isochronous mode. Only valid in double buffered mode for an -// Isochronous endpoint. -// For a non Isochronous endpoint the offset is always 64 bytes. -// 0x0 -> 128 -// 0x1 -> 256 -// 0x2 -> 512 -// 0x3 -> 1024 -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_AVAILABLE_1 -// Description : Buffer 1 is available. This bit is set to indicate the buffer -// can be used by the controller. The controller clears the -// available bit when writing the status back. -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_1 -// Description : The length of the data in buffer 1. -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_1_MSB _u(25) -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_1_LSB _u(16) -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_FULL_0 -// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit -// is set to indicate the data is valid. For an OUT transfer (RX -// from the host) this bit should be left as a 0. The host will -// set it when it has filled the buffer with data. -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_FULL_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_FULL_0_MSB _u(15) -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_FULL_0_LSB _u(15) -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LAST_0 -// Description : Buffer 0 is the last buffer of the transfer. -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LAST_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LAST_0_MSB _u(14) -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LAST_0_LSB _u(14) -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_PID_0 -// Description : The data pid of buffer 0. -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_PID_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_PID_0_MSB _u(13) -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_PID_0_LSB _u(13) -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_RESET -// Description : Reset the buffer selector to buffer 0. -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_RESET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_RESET_BITS _u(0x00001000) -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_RESET_MSB _u(12) -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_RESET_LSB _u(12) -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_RESET_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_STALL -// Description : Reply with a stall (valid for both buffers). -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_STALL_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_STALL_BITS _u(0x00000800) -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_STALL_MSB _u(11) -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_STALL_LSB _u(11) -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_STALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_AVAILABLE_0 -// Description : Buffer 0 is available. This bit is set to indicate the buffer -// can be used by the controller. The controller clears the -// available bit when writing the status back. -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_0 -// Description : The length of the data in buffer 0. -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_0_MSB _u(9) -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_0_LSB _u(0) -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" -// ============================================================================= -// Register : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL -// Description : Buffer control for both buffers of an endpoint. Fields ending -// in a _1 are for buffer 1. -// Fields ending in a _0 are for buffer 0. Buffer 1 controls are -// only valid if the endpoint is in double buffered mode. -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_OFFSET _u(0x000000e8) -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_BITS _u(0xffffffff) -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_FULL_1 -// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit -// is set to indicate the data is valid. For an OUT transfer (RX -// from the host) this bit should be left as a 0. The host will -// set it when it has filled the buffer with data. -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_FULL_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_FULL_1_MSB _u(31) -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_FULL_1_LSB _u(31) -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LAST_1 -// Description : Buffer 1 is the last buffer of the transfer. -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LAST_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LAST_1_MSB _u(30) -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LAST_1_LSB _u(30) -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_PID_1 -// Description : The data pid of buffer 1. -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_PID_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_PID_1_MSB _u(29) -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_PID_1_LSB _u(29) -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_PID_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET -// Description : The number of bytes buffer 1 is offset from buffer 0 in -// Isochronous mode. Only valid in double buffered mode for an -// Isochronous endpoint. -// For a non Isochronous endpoint the offset is always 64 bytes. -// 0x0 -> 128 -// 0x1 -> 256 -// 0x2 -> 512 -// 0x3 -> 1024 -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_AVAILABLE_1 -// Description : Buffer 1 is available. This bit is set to indicate the buffer -// can be used by the controller. The controller clears the -// available bit when writing the status back. -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_1 -// Description : The length of the data in buffer 1. -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_1_MSB _u(25) -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_1_LSB _u(16) -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_FULL_0 -// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit -// is set to indicate the data is valid. For an OUT transfer (RX -// from the host) this bit should be left as a 0. The host will -// set it when it has filled the buffer with data. -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_FULL_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_FULL_0_MSB _u(15) -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_FULL_0_LSB _u(15) -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LAST_0 -// Description : Buffer 0 is the last buffer of the transfer. -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LAST_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LAST_0_MSB _u(14) -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LAST_0_LSB _u(14) -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_PID_0 -// Description : The data pid of buffer 0. -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_PID_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_PID_0_MSB _u(13) -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_PID_0_LSB _u(13) -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_PID_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_RESET -// Description : Reset the buffer selector to buffer 0. -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_RESET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_RESET_BITS _u(0x00001000) -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_RESET_MSB _u(12) -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_RESET_LSB _u(12) -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_RESET_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_STALL -// Description : Reply with a stall (valid for both buffers). -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_STALL_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_STALL_BITS _u(0x00000800) -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_STALL_MSB _u(11) -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_STALL_LSB _u(11) -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_STALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_AVAILABLE_0 -// Description : Buffer 0 is available. This bit is set to indicate the buffer -// can be used by the controller. The controller clears the -// available bit when writing the status back. -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_0 -// Description : The length of the data in buffer 0. -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_0_MSB _u(9) -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_0_LSB _u(0) -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" -// ============================================================================= -// Register : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL -// Description : Buffer control for both buffers of an endpoint. Fields ending -// in a _1 are for buffer 1. -// Fields ending in a _0 are for buffer 0. Buffer 1 controls are -// only valid if the endpoint is in double buffered mode. -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_OFFSET _u(0x000000ec) -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_BITS _u(0xffffffff) -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_FULL_1 -// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit -// is set to indicate the data is valid. For an OUT transfer (RX -// from the host) this bit should be left as a 0. The host will -// set it when it has filled the buffer with data. -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_FULL_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_FULL_1_MSB _u(31) -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_FULL_1_LSB _u(31) -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LAST_1 -// Description : Buffer 1 is the last buffer of the transfer. -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LAST_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LAST_1_MSB _u(30) -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LAST_1_LSB _u(30) -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_PID_1 -// Description : The data pid of buffer 1. -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_PID_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_PID_1_MSB _u(29) -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_PID_1_LSB _u(29) -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET -// Description : The number of bytes buffer 1 is offset from buffer 0 in -// Isochronous mode. Only valid in double buffered mode for an -// Isochronous endpoint. -// For a non Isochronous endpoint the offset is always 64 bytes. -// 0x0 -> 128 -// 0x1 -> 256 -// 0x2 -> 512 -// 0x3 -> 1024 -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_AVAILABLE_1 -// Description : Buffer 1 is available. This bit is set to indicate the buffer -// can be used by the controller. The controller clears the -// available bit when writing the status back. -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_1 -// Description : The length of the data in buffer 1. -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_1_MSB _u(25) -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_1_LSB _u(16) -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_FULL_0 -// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit -// is set to indicate the data is valid. For an OUT transfer (RX -// from the host) this bit should be left as a 0. The host will -// set it when it has filled the buffer with data. -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_FULL_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_FULL_0_MSB _u(15) -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_FULL_0_LSB _u(15) -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LAST_0 -// Description : Buffer 0 is the last buffer of the transfer. -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LAST_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LAST_0_MSB _u(14) -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LAST_0_LSB _u(14) -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_PID_0 -// Description : The data pid of buffer 0. -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_PID_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_PID_0_MSB _u(13) -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_PID_0_LSB _u(13) -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_RESET -// Description : Reset the buffer selector to buffer 0. -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_RESET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_RESET_BITS _u(0x00001000) -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_RESET_MSB _u(12) -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_RESET_LSB _u(12) -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_RESET_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_STALL -// Description : Reply with a stall (valid for both buffers). -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_STALL_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_STALL_BITS _u(0x00000800) -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_STALL_MSB _u(11) -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_STALL_LSB _u(11) -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_STALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_AVAILABLE_0 -// Description : Buffer 0 is available. This bit is set to indicate the buffer -// can be used by the controller. The controller clears the -// available bit when writing the status back. -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_0 -// Description : The length of the data in buffer 0. -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_0_MSB _u(9) -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_0_LSB _u(0) -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" -// ============================================================================= -// Register : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL -// Description : Buffer control for both buffers of an endpoint. Fields ending -// in a _1 are for buffer 1. -// Fields ending in a _0 are for buffer 0. Buffer 1 controls are -// only valid if the endpoint is in double buffered mode. -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_OFFSET _u(0x000000f0) -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_BITS _u(0xffffffff) -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_FULL_1 -// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit -// is set to indicate the data is valid. For an OUT transfer (RX -// from the host) this bit should be left as a 0. The host will -// set it when it has filled the buffer with data. -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_FULL_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_FULL_1_MSB _u(31) -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_FULL_1_LSB _u(31) -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LAST_1 -// Description : Buffer 1 is the last buffer of the transfer. -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LAST_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LAST_1_MSB _u(30) -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LAST_1_LSB _u(30) -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_PID_1 -// Description : The data pid of buffer 1. -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_PID_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_PID_1_MSB _u(29) -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_PID_1_LSB _u(29) -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_PID_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET -// Description : The number of bytes buffer 1 is offset from buffer 0 in -// Isochronous mode. Only valid in double buffered mode for an -// Isochronous endpoint. -// For a non Isochronous endpoint the offset is always 64 bytes. -// 0x0 -> 128 -// 0x1 -> 256 -// 0x2 -> 512 -// 0x3 -> 1024 -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_AVAILABLE_1 -// Description : Buffer 1 is available. This bit is set to indicate the buffer -// can be used by the controller. The controller clears the -// available bit when writing the status back. -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_1 -// Description : The length of the data in buffer 1. -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_1_MSB _u(25) -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_1_LSB _u(16) -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_FULL_0 -// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit -// is set to indicate the data is valid. For an OUT transfer (RX -// from the host) this bit should be left as a 0. The host will -// set it when it has filled the buffer with data. -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_FULL_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_FULL_0_MSB _u(15) -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_FULL_0_LSB _u(15) -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LAST_0 -// Description : Buffer 0 is the last buffer of the transfer. -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LAST_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LAST_0_MSB _u(14) -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LAST_0_LSB _u(14) -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_PID_0 -// Description : The data pid of buffer 0. -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_PID_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_PID_0_MSB _u(13) -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_PID_0_LSB _u(13) -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_PID_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_RESET -// Description : Reset the buffer selector to buffer 0. -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_RESET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_RESET_BITS _u(0x00001000) -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_RESET_MSB _u(12) -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_RESET_LSB _u(12) -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_RESET_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_STALL -// Description : Reply with a stall (valid for both buffers). -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_STALL_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_STALL_BITS _u(0x00000800) -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_STALL_MSB _u(11) -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_STALL_LSB _u(11) -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_STALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_AVAILABLE_0 -// Description : Buffer 0 is available. This bit is set to indicate the buffer -// can be used by the controller. The controller clears the -// available bit when writing the status back. -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_0 -// Description : The length of the data in buffer 0. -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_0_MSB _u(9) -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_0_LSB _u(0) -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" -// ============================================================================= -// Register : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL -// Description : Buffer control for both buffers of an endpoint. Fields ending -// in a _1 are for buffer 1. -// Fields ending in a _0 are for buffer 0. Buffer 1 controls are -// only valid if the endpoint is in double buffered mode. -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_OFFSET _u(0x000000f4) -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_BITS _u(0xffffffff) -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_FULL_1 -// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit -// is set to indicate the data is valid. For an OUT transfer (RX -// from the host) this bit should be left as a 0. The host will -// set it when it has filled the buffer with data. -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_FULL_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_FULL_1_MSB _u(31) -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_FULL_1_LSB _u(31) -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LAST_1 -// Description : Buffer 1 is the last buffer of the transfer. -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LAST_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LAST_1_MSB _u(30) -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LAST_1_LSB _u(30) -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_PID_1 -// Description : The data pid of buffer 1. -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_PID_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_PID_1_MSB _u(29) -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_PID_1_LSB _u(29) -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET -// Description : The number of bytes buffer 1 is offset from buffer 0 in -// Isochronous mode. Only valid in double buffered mode for an -// Isochronous endpoint. -// For a non Isochronous endpoint the offset is always 64 bytes. -// 0x0 -> 128 -// 0x1 -> 256 -// 0x2 -> 512 -// 0x3 -> 1024 -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_AVAILABLE_1 -// Description : Buffer 1 is available. This bit is set to indicate the buffer -// can be used by the controller. The controller clears the -// available bit when writing the status back. -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_1 -// Description : The length of the data in buffer 1. -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_1_MSB _u(25) -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_1_LSB _u(16) -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_FULL_0 -// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit -// is set to indicate the data is valid. For an OUT transfer (RX -// from the host) this bit should be left as a 0. The host will -// set it when it has filled the buffer with data. -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_FULL_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_FULL_0_MSB _u(15) -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_FULL_0_LSB _u(15) -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LAST_0 -// Description : Buffer 0 is the last buffer of the transfer. -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LAST_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LAST_0_MSB _u(14) -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LAST_0_LSB _u(14) -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_PID_0 -// Description : The data pid of buffer 0. -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_PID_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_PID_0_MSB _u(13) -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_PID_0_LSB _u(13) -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_RESET -// Description : Reset the buffer selector to buffer 0. -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_RESET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_RESET_BITS _u(0x00001000) -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_RESET_MSB _u(12) -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_RESET_LSB _u(12) -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_RESET_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_STALL -// Description : Reply with a stall (valid for both buffers). -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_STALL_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_STALL_BITS _u(0x00000800) -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_STALL_MSB _u(11) -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_STALL_LSB _u(11) -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_STALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_AVAILABLE_0 -// Description : Buffer 0 is available. This bit is set to indicate the buffer -// can be used by the controller. The controller clears the -// available bit when writing the status back. -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_0 -// Description : The length of the data in buffer 0. -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_0_MSB _u(9) -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_0_LSB _u(0) -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" -// ============================================================================= -// Register : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL -// Description : Buffer control for both buffers of an endpoint. Fields ending -// in a _1 are for buffer 1. -// Fields ending in a _0 are for buffer 0. Buffer 1 controls are -// only valid if the endpoint is in double buffered mode. -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_OFFSET _u(0x000000f8) -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_BITS _u(0xffffffff) -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_FULL_1 -// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit -// is set to indicate the data is valid. For an OUT transfer (RX -// from the host) this bit should be left as a 0. The host will -// set it when it has filled the buffer with data. -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_FULL_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_FULL_1_MSB _u(31) -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_FULL_1_LSB _u(31) -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LAST_1 -// Description : Buffer 1 is the last buffer of the transfer. -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LAST_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LAST_1_MSB _u(30) -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LAST_1_LSB _u(30) -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_PID_1 -// Description : The data pid of buffer 1. -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_PID_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_PID_1_MSB _u(29) -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_PID_1_LSB _u(29) -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_PID_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET -// Description : The number of bytes buffer 1 is offset from buffer 0 in -// Isochronous mode. Only valid in double buffered mode for an -// Isochronous endpoint. -// For a non Isochronous endpoint the offset is always 64 bytes. -// 0x0 -> 128 -// 0x1 -> 256 -// 0x2 -> 512 -// 0x3 -> 1024 -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_AVAILABLE_1 -// Description : Buffer 1 is available. This bit is set to indicate the buffer -// can be used by the controller. The controller clears the -// available bit when writing the status back. -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_1 -// Description : The length of the data in buffer 1. -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_1_MSB _u(25) -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_1_LSB _u(16) -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_FULL_0 -// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit -// is set to indicate the data is valid. For an OUT transfer (RX -// from the host) this bit should be left as a 0. The host will -// set it when it has filled the buffer with data. -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_FULL_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_FULL_0_MSB _u(15) -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_FULL_0_LSB _u(15) -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LAST_0 -// Description : Buffer 0 is the last buffer of the transfer. -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LAST_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LAST_0_MSB _u(14) -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LAST_0_LSB _u(14) -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_PID_0 -// Description : The data pid of buffer 0. -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_PID_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_PID_0_MSB _u(13) -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_PID_0_LSB _u(13) -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_PID_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_RESET -// Description : Reset the buffer selector to buffer 0. -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_RESET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_RESET_BITS _u(0x00001000) -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_RESET_MSB _u(12) -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_RESET_LSB _u(12) -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_RESET_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_STALL -// Description : Reply with a stall (valid for both buffers). -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_STALL_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_STALL_BITS _u(0x00000800) -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_STALL_MSB _u(11) -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_STALL_LSB _u(11) -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_STALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_AVAILABLE_0 -// Description : Buffer 0 is available. This bit is set to indicate the buffer -// can be used by the controller. The controller clears the -// available bit when writing the status back. -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_0 -// Description : The length of the data in buffer 0. -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_0_MSB _u(9) -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_0_LSB _u(0) -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" -// ============================================================================= -// Register : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL -// Description : Buffer control for both buffers of an endpoint. Fields ending -// in a _1 are for buffer 1. -// Fields ending in a _0 are for buffer 0. Buffer 1 controls are -// only valid if the endpoint is in double buffered mode. -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_OFFSET _u(0x000000fc) -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_BITS _u(0xffffffff) -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_FULL_1 -// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit -// is set to indicate the data is valid. For an OUT transfer (RX -// from the host) this bit should be left as a 0. The host will -// set it when it has filled the buffer with data. -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_FULL_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_FULL_1_MSB _u(31) -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_FULL_1_LSB _u(31) -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LAST_1 -// Description : Buffer 1 is the last buffer of the transfer. -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LAST_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LAST_1_MSB _u(30) -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LAST_1_LSB _u(30) -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_PID_1 -// Description : The data pid of buffer 1. -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_PID_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_PID_1_MSB _u(29) -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_PID_1_LSB _u(29) -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET -// Description : The number of bytes buffer 1 is offset from buffer 0 in -// Isochronous mode. Only valid in double buffered mode for an -// Isochronous endpoint. -// For a non Isochronous endpoint the offset is always 64 bytes. -// 0x0 -> 128 -// 0x1 -> 256 -// 0x2 -> 512 -// 0x3 -> 1024 -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_AVAILABLE_1 -// Description : Buffer 1 is available. This bit is set to indicate the buffer -// can be used by the controller. The controller clears the -// available bit when writing the status back. -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_1 -// Description : The length of the data in buffer 1. -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_1_MSB _u(25) -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_1_LSB _u(16) -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_FULL_0 -// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit -// is set to indicate the data is valid. For an OUT transfer (RX -// from the host) this bit should be left as a 0. The host will -// set it when it has filled the buffer with data. -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_FULL_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_FULL_0_MSB _u(15) -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_FULL_0_LSB _u(15) -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LAST_0 -// Description : Buffer 0 is the last buffer of the transfer. -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LAST_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LAST_0_MSB _u(14) -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LAST_0_LSB _u(14) -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_PID_0 -// Description : The data pid of buffer 0. -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_PID_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_PID_0_MSB _u(13) -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_PID_0_LSB _u(13) -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_RESET -// Description : Reset the buffer selector to buffer 0. -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_RESET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_RESET_BITS _u(0x00001000) -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_RESET_MSB _u(12) -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_RESET_LSB _u(12) -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_RESET_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_STALL -// Description : Reply with a stall (valid for both buffers). -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_STALL_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_STALL_BITS _u(0x00000800) -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_STALL_MSB _u(11) -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_STALL_LSB _u(11) -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_STALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_AVAILABLE_0 -// Description : Buffer 0 is available. This bit is set to indicate the buffer -// can be used by the controller. The controller clears the -// available bit when writing the status back. -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_0 -// Description : The length of the data in buffer 0. -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_0_MSB _u(9) -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_0_LSB _u(0) -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" -// ============================================================================= -#endif // _HARDWARE_REGS_USB_DEVICE_DPRAM_H - diff --git a/lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/vreg_and_chip_reset.h b/lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/vreg_and_chip_reset.h deleted file mode 100644 index da61c01f1a..0000000000 --- a/lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/vreg_and_chip_reset.h +++ /dev/null @@ -1,154 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -// ============================================================================= -// Register block : VREG_AND_CHIP_RESET -// Version : 1 -// Bus type : apb -// Description : control and status for on-chip voltage regulator and chip -// level reset subsystem -// ============================================================================= -#ifndef _HARDWARE_REGS_VREG_AND_CHIP_RESET_H -#define _HARDWARE_REGS_VREG_AND_CHIP_RESET_H -// ============================================================================= -// Register : VREG_AND_CHIP_RESET_VREG -// Description : Voltage regulator control and status -#define VREG_AND_CHIP_RESET_VREG_OFFSET _u(0x00000000) -#define VREG_AND_CHIP_RESET_VREG_BITS _u(0x000010f3) -#define VREG_AND_CHIP_RESET_VREG_RESET _u(0x000000b1) -// ----------------------------------------------------------------------------- -// Field : VREG_AND_CHIP_RESET_VREG_ROK -// Description : regulation status -// 0=not in regulation, 1=in regulation -#define VREG_AND_CHIP_RESET_VREG_ROK_RESET _u(0x0) -#define VREG_AND_CHIP_RESET_VREG_ROK_BITS _u(0x00001000) -#define VREG_AND_CHIP_RESET_VREG_ROK_MSB _u(12) -#define VREG_AND_CHIP_RESET_VREG_ROK_LSB _u(12) -#define VREG_AND_CHIP_RESET_VREG_ROK_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : VREG_AND_CHIP_RESET_VREG_VSEL -// Description : output voltage select -// 0000 to 0101 - 0.80V -// 0110 - 0.85V -// 0111 - 0.90V -// 1000 - 0.95V -// 1001 - 1.00V -// 1010 - 1.05V -// 1011 - 1.10V (default) -// 1100 - 1.15V -// 1101 - 1.20V -// 1110 - 1.25V -// 1111 - 1.30V -#define VREG_AND_CHIP_RESET_VREG_VSEL_RESET _u(0xb) -#define VREG_AND_CHIP_RESET_VREG_VSEL_BITS _u(0x000000f0) -#define VREG_AND_CHIP_RESET_VREG_VSEL_MSB _u(7) -#define VREG_AND_CHIP_RESET_VREG_VSEL_LSB _u(4) -#define VREG_AND_CHIP_RESET_VREG_VSEL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : VREG_AND_CHIP_RESET_VREG_HIZ -// Description : high impedance mode select -// 0=not in high impedance mode, 1=in high impedance mode -#define VREG_AND_CHIP_RESET_VREG_HIZ_RESET _u(0x0) -#define VREG_AND_CHIP_RESET_VREG_HIZ_BITS _u(0x00000002) -#define VREG_AND_CHIP_RESET_VREG_HIZ_MSB _u(1) -#define VREG_AND_CHIP_RESET_VREG_HIZ_LSB _u(1) -#define VREG_AND_CHIP_RESET_VREG_HIZ_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : VREG_AND_CHIP_RESET_VREG_EN -// Description : enable -// 0=not enabled, 1=enabled -#define VREG_AND_CHIP_RESET_VREG_EN_RESET _u(0x1) -#define VREG_AND_CHIP_RESET_VREG_EN_BITS _u(0x00000001) -#define VREG_AND_CHIP_RESET_VREG_EN_MSB _u(0) -#define VREG_AND_CHIP_RESET_VREG_EN_LSB _u(0) -#define VREG_AND_CHIP_RESET_VREG_EN_ACCESS "RW" -// ============================================================================= -// Register : VREG_AND_CHIP_RESET_BOD -// Description : brown-out detection control -#define VREG_AND_CHIP_RESET_BOD_OFFSET _u(0x00000004) -#define VREG_AND_CHIP_RESET_BOD_BITS _u(0x000000f1) -#define VREG_AND_CHIP_RESET_BOD_RESET _u(0x00000091) -// ----------------------------------------------------------------------------- -// Field : VREG_AND_CHIP_RESET_BOD_VSEL -// Description : threshold select -// 0000 - 0.473V -// 0001 - 0.516V -// 0010 - 0.559V -// 0011 - 0.602V -// 0100 - 0.645V -// 0101 - 0.688V -// 0110 - 0.731V -// 0111 - 0.774V -// 1000 - 0.817V -// 1001 - 0.860V (default) -// 1010 - 0.903V -// 1011 - 0.946V -// 1100 - 0.989V -// 1101 - 1.032V -// 1110 - 1.075V -// 1111 - 1.118V -#define VREG_AND_CHIP_RESET_BOD_VSEL_RESET _u(0x9) -#define VREG_AND_CHIP_RESET_BOD_VSEL_BITS _u(0x000000f0) -#define VREG_AND_CHIP_RESET_BOD_VSEL_MSB _u(7) -#define VREG_AND_CHIP_RESET_BOD_VSEL_LSB _u(4) -#define VREG_AND_CHIP_RESET_BOD_VSEL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : VREG_AND_CHIP_RESET_BOD_EN -// Description : enable -// 0=not enabled, 1=enabled -#define VREG_AND_CHIP_RESET_BOD_EN_RESET _u(0x1) -#define VREG_AND_CHIP_RESET_BOD_EN_BITS _u(0x00000001) -#define VREG_AND_CHIP_RESET_BOD_EN_MSB _u(0) -#define VREG_AND_CHIP_RESET_BOD_EN_LSB _u(0) -#define VREG_AND_CHIP_RESET_BOD_EN_ACCESS "RW" -// ============================================================================= -// Register : VREG_AND_CHIP_RESET_CHIP_RESET -// Description : Chip reset control and status -#define VREG_AND_CHIP_RESET_CHIP_RESET_OFFSET _u(0x00000008) -#define VREG_AND_CHIP_RESET_CHIP_RESET_BITS _u(0x01110100) -#define VREG_AND_CHIP_RESET_CHIP_RESET_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : VREG_AND_CHIP_RESET_CHIP_RESET_PSM_RESTART_FLAG -// Description : This is set by psm_restart from the debugger. -// Its purpose is to branch bootcode to a safe mode when the -// debugger has issued a psm_restart in order to recover from a -// boot lock-up. -// In the safe mode the debugger can repair the boot code, clear -// this flag then reboot the processor. -#define VREG_AND_CHIP_RESET_CHIP_RESET_PSM_RESTART_FLAG_RESET _u(0x0) -#define VREG_AND_CHIP_RESET_CHIP_RESET_PSM_RESTART_FLAG_BITS _u(0x01000000) -#define VREG_AND_CHIP_RESET_CHIP_RESET_PSM_RESTART_FLAG_MSB _u(24) -#define VREG_AND_CHIP_RESET_CHIP_RESET_PSM_RESTART_FLAG_LSB _u(24) -#define VREG_AND_CHIP_RESET_CHIP_RESET_PSM_RESTART_FLAG_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : VREG_AND_CHIP_RESET_CHIP_RESET_HAD_PSM_RESTART -// Description : Last reset was from the debug port -#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_PSM_RESTART_RESET _u(0x0) -#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_PSM_RESTART_BITS _u(0x00100000) -#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_PSM_RESTART_MSB _u(20) -#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_PSM_RESTART_LSB _u(20) -#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_PSM_RESTART_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : VREG_AND_CHIP_RESET_CHIP_RESET_HAD_RUN -// Description : Last reset was from the RUN pin -#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_RUN_RESET _u(0x0) -#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_RUN_BITS _u(0x00010000) -#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_RUN_MSB _u(16) -#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_RUN_LSB _u(16) -#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_RUN_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : VREG_AND_CHIP_RESET_CHIP_RESET_HAD_POR -// Description : Last reset was from the power-on reset or brown-out detection -// blocks -#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_POR_RESET _u(0x0) -#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_POR_BITS _u(0x00000100) -#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_POR_MSB _u(8) -#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_POR_LSB _u(8) -#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_POR_ACCESS "RO" -// ============================================================================= -#endif // _HARDWARE_REGS_VREG_AND_CHIP_RESET_H - diff --git a/lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/watchdog.h b/lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/watchdog.h deleted file mode 100644 index 9c941aede4..0000000000 --- a/lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/watchdog.h +++ /dev/null @@ -1,226 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -// ============================================================================= -// Register block : WATCHDOG -// Version : 1 -// Bus type : apb -// ============================================================================= -#ifndef _HARDWARE_REGS_WATCHDOG_H -#define _HARDWARE_REGS_WATCHDOG_H -// ============================================================================= -// Register : WATCHDOG_CTRL -// Description : Watchdog control -// The rst_wdsel register determines which subsystems are reset -// when the watchdog is triggered. -// The watchdog can be triggered in software. -#define WATCHDOG_CTRL_OFFSET _u(0x00000000) -#define WATCHDOG_CTRL_BITS _u(0xc7ffffff) -#define WATCHDOG_CTRL_RESET _u(0x07000000) -// ----------------------------------------------------------------------------- -// Field : WATCHDOG_CTRL_TRIGGER -// Description : Trigger a watchdog reset -#define WATCHDOG_CTRL_TRIGGER_RESET _u(0x0) -#define WATCHDOG_CTRL_TRIGGER_BITS _u(0x80000000) -#define WATCHDOG_CTRL_TRIGGER_MSB _u(31) -#define WATCHDOG_CTRL_TRIGGER_LSB _u(31) -#define WATCHDOG_CTRL_TRIGGER_ACCESS "SC" -// ----------------------------------------------------------------------------- -// Field : WATCHDOG_CTRL_ENABLE -// Description : When not enabled the watchdog timer is paused -#define WATCHDOG_CTRL_ENABLE_RESET _u(0x0) -#define WATCHDOG_CTRL_ENABLE_BITS _u(0x40000000) -#define WATCHDOG_CTRL_ENABLE_MSB _u(30) -#define WATCHDOG_CTRL_ENABLE_LSB _u(30) -#define WATCHDOG_CTRL_ENABLE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : WATCHDOG_CTRL_PAUSE_DBG1 -// Description : Pause the watchdog timer when processor 1 is in debug mode -#define WATCHDOG_CTRL_PAUSE_DBG1_RESET _u(0x1) -#define WATCHDOG_CTRL_PAUSE_DBG1_BITS _u(0x04000000) -#define WATCHDOG_CTRL_PAUSE_DBG1_MSB _u(26) -#define WATCHDOG_CTRL_PAUSE_DBG1_LSB _u(26) -#define WATCHDOG_CTRL_PAUSE_DBG1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : WATCHDOG_CTRL_PAUSE_DBG0 -// Description : Pause the watchdog timer when processor 0 is in debug mode -#define WATCHDOG_CTRL_PAUSE_DBG0_RESET _u(0x1) -#define WATCHDOG_CTRL_PAUSE_DBG0_BITS _u(0x02000000) -#define WATCHDOG_CTRL_PAUSE_DBG0_MSB _u(25) -#define WATCHDOG_CTRL_PAUSE_DBG0_LSB _u(25) -#define WATCHDOG_CTRL_PAUSE_DBG0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : WATCHDOG_CTRL_PAUSE_JTAG -// Description : Pause the watchdog timer when JTAG is accessing the bus fabric -#define WATCHDOG_CTRL_PAUSE_JTAG_RESET _u(0x1) -#define WATCHDOG_CTRL_PAUSE_JTAG_BITS _u(0x01000000) -#define WATCHDOG_CTRL_PAUSE_JTAG_MSB _u(24) -#define WATCHDOG_CTRL_PAUSE_JTAG_LSB _u(24) -#define WATCHDOG_CTRL_PAUSE_JTAG_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : WATCHDOG_CTRL_TIME -// Description : Indicates the number of ticks / 2 (see errata RP2040-E1) before -// a watchdog reset will be triggered -#define WATCHDOG_CTRL_TIME_RESET _u(0x000000) -#define WATCHDOG_CTRL_TIME_BITS _u(0x00ffffff) -#define WATCHDOG_CTRL_TIME_MSB _u(23) -#define WATCHDOG_CTRL_TIME_LSB _u(0) -#define WATCHDOG_CTRL_TIME_ACCESS "RO" -// ============================================================================= -// Register : WATCHDOG_LOAD -// Description : Load the watchdog timer. The maximum setting is 0xffffff which -// corresponds to 0xffffff / 2 ticks before triggering a watchdog -// reset (see errata RP2040-E1). -#define WATCHDOG_LOAD_OFFSET _u(0x00000004) -#define WATCHDOG_LOAD_BITS _u(0x00ffffff) -#define WATCHDOG_LOAD_RESET _u(0x00000000) -#define WATCHDOG_LOAD_MSB _u(23) -#define WATCHDOG_LOAD_LSB _u(0) -#define WATCHDOG_LOAD_ACCESS "WF" -// ============================================================================= -// Register : WATCHDOG_REASON -// Description : Logs the reason for the last reset. Both bits are zero for the -// case of a hardware reset. -#define WATCHDOG_REASON_OFFSET _u(0x00000008) -#define WATCHDOG_REASON_BITS _u(0x00000003) -#define WATCHDOG_REASON_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : WATCHDOG_REASON_FORCE -#define WATCHDOG_REASON_FORCE_RESET _u(0x0) -#define WATCHDOG_REASON_FORCE_BITS _u(0x00000002) -#define WATCHDOG_REASON_FORCE_MSB _u(1) -#define WATCHDOG_REASON_FORCE_LSB _u(1) -#define WATCHDOG_REASON_FORCE_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : WATCHDOG_REASON_TIMER -#define WATCHDOG_REASON_TIMER_RESET _u(0x0) -#define WATCHDOG_REASON_TIMER_BITS _u(0x00000001) -#define WATCHDOG_REASON_TIMER_MSB _u(0) -#define WATCHDOG_REASON_TIMER_LSB _u(0) -#define WATCHDOG_REASON_TIMER_ACCESS "RO" -// ============================================================================= -// Register : WATCHDOG_SCRATCH0 -// Description : Scratch register. Information persists through soft reset of -// the chip. -#define WATCHDOG_SCRATCH0_OFFSET _u(0x0000000c) -#define WATCHDOG_SCRATCH0_BITS _u(0xffffffff) -#define WATCHDOG_SCRATCH0_RESET _u(0x00000000) -#define WATCHDOG_SCRATCH0_MSB _u(31) -#define WATCHDOG_SCRATCH0_LSB _u(0) -#define WATCHDOG_SCRATCH0_ACCESS "RW" -// ============================================================================= -// Register : WATCHDOG_SCRATCH1 -// Description : Scratch register. Information persists through soft reset of -// the chip. -#define WATCHDOG_SCRATCH1_OFFSET _u(0x00000010) -#define WATCHDOG_SCRATCH1_BITS _u(0xffffffff) -#define WATCHDOG_SCRATCH1_RESET _u(0x00000000) -#define WATCHDOG_SCRATCH1_MSB _u(31) -#define WATCHDOG_SCRATCH1_LSB _u(0) -#define WATCHDOG_SCRATCH1_ACCESS "RW" -// ============================================================================= -// Register : WATCHDOG_SCRATCH2 -// Description : Scratch register. Information persists through soft reset of -// the chip. -#define WATCHDOG_SCRATCH2_OFFSET _u(0x00000014) -#define WATCHDOG_SCRATCH2_BITS _u(0xffffffff) -#define WATCHDOG_SCRATCH2_RESET _u(0x00000000) -#define WATCHDOG_SCRATCH2_MSB _u(31) -#define WATCHDOG_SCRATCH2_LSB _u(0) -#define WATCHDOG_SCRATCH2_ACCESS "RW" -// ============================================================================= -// Register : WATCHDOG_SCRATCH3 -// Description : Scratch register. Information persists through soft reset of -// the chip. -#define WATCHDOG_SCRATCH3_OFFSET _u(0x00000018) -#define WATCHDOG_SCRATCH3_BITS _u(0xffffffff) -#define WATCHDOG_SCRATCH3_RESET _u(0x00000000) -#define WATCHDOG_SCRATCH3_MSB _u(31) -#define WATCHDOG_SCRATCH3_LSB _u(0) -#define WATCHDOG_SCRATCH3_ACCESS "RW" -// ============================================================================= -// Register : WATCHDOG_SCRATCH4 -// Description : Scratch register. Information persists through soft reset of -// the chip. -#define WATCHDOG_SCRATCH4_OFFSET _u(0x0000001c) -#define WATCHDOG_SCRATCH4_BITS _u(0xffffffff) -#define WATCHDOG_SCRATCH4_RESET _u(0x00000000) -#define WATCHDOG_SCRATCH4_MSB _u(31) -#define WATCHDOG_SCRATCH4_LSB _u(0) -#define WATCHDOG_SCRATCH4_ACCESS "RW" -// ============================================================================= -// Register : WATCHDOG_SCRATCH5 -// Description : Scratch register. Information persists through soft reset of -// the chip. -#define WATCHDOG_SCRATCH5_OFFSET _u(0x00000020) -#define WATCHDOG_SCRATCH5_BITS _u(0xffffffff) -#define WATCHDOG_SCRATCH5_RESET _u(0x00000000) -#define WATCHDOG_SCRATCH5_MSB _u(31) -#define WATCHDOG_SCRATCH5_LSB _u(0) -#define WATCHDOG_SCRATCH5_ACCESS "RW" -// ============================================================================= -// Register : WATCHDOG_SCRATCH6 -// Description : Scratch register. Information persists through soft reset of -// the chip. -#define WATCHDOG_SCRATCH6_OFFSET _u(0x00000024) -#define WATCHDOG_SCRATCH6_BITS _u(0xffffffff) -#define WATCHDOG_SCRATCH6_RESET _u(0x00000000) -#define WATCHDOG_SCRATCH6_MSB _u(31) -#define WATCHDOG_SCRATCH6_LSB _u(0) -#define WATCHDOG_SCRATCH6_ACCESS "RW" -// ============================================================================= -// Register : WATCHDOG_SCRATCH7 -// Description : Scratch register. Information persists through soft reset of -// the chip. -#define WATCHDOG_SCRATCH7_OFFSET _u(0x00000028) -#define WATCHDOG_SCRATCH7_BITS _u(0xffffffff) -#define WATCHDOG_SCRATCH7_RESET _u(0x00000000) -#define WATCHDOG_SCRATCH7_MSB _u(31) -#define WATCHDOG_SCRATCH7_LSB _u(0) -#define WATCHDOG_SCRATCH7_ACCESS "RW" -// ============================================================================= -// Register : WATCHDOG_TICK -// Description : Controls the tick generator -#define WATCHDOG_TICK_OFFSET _u(0x0000002c) -#define WATCHDOG_TICK_BITS _u(0x000fffff) -#define WATCHDOG_TICK_RESET _u(0x00000200) -// ----------------------------------------------------------------------------- -// Field : WATCHDOG_TICK_COUNT -// Description : Count down timer: the remaining number clk_tick cycles before -// the next tick is generated. -#define WATCHDOG_TICK_COUNT_RESET "-" -#define WATCHDOG_TICK_COUNT_BITS _u(0x000ff800) -#define WATCHDOG_TICK_COUNT_MSB _u(19) -#define WATCHDOG_TICK_COUNT_LSB _u(11) -#define WATCHDOG_TICK_COUNT_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : WATCHDOG_TICK_RUNNING -// Description : Is the tick generator running? -#define WATCHDOG_TICK_RUNNING_RESET "-" -#define WATCHDOG_TICK_RUNNING_BITS _u(0x00000400) -#define WATCHDOG_TICK_RUNNING_MSB _u(10) -#define WATCHDOG_TICK_RUNNING_LSB _u(10) -#define WATCHDOG_TICK_RUNNING_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : WATCHDOG_TICK_ENABLE -// Description : start / stop tick generation -#define WATCHDOG_TICK_ENABLE_RESET _u(0x1) -#define WATCHDOG_TICK_ENABLE_BITS _u(0x00000200) -#define WATCHDOG_TICK_ENABLE_MSB _u(9) -#define WATCHDOG_TICK_ENABLE_LSB _u(9) -#define WATCHDOG_TICK_ENABLE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : WATCHDOG_TICK_CYCLES -// Description : Total number of clk_tick cycles before the next tick. -#define WATCHDOG_TICK_CYCLES_RESET _u(0x000) -#define WATCHDOG_TICK_CYCLES_BITS _u(0x000001ff) -#define WATCHDOG_TICK_CYCLES_MSB _u(8) -#define WATCHDOG_TICK_CYCLES_LSB _u(0) -#define WATCHDOG_TICK_CYCLES_ACCESS "RW" -// ============================================================================= -#endif // _HARDWARE_REGS_WATCHDOG_H - diff --git a/lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/xip.h b/lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/xip.h deleted file mode 100644 index e163f36d54..0000000000 --- a/lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/xip.h +++ /dev/null @@ -1,190 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -// ============================================================================= -// Register block : XIP -// Version : 1 -// Bus type : ahb -// Description : QSPI flash execute-in-place block -// ============================================================================= -#ifndef _HARDWARE_REGS_XIP_H -#define _HARDWARE_REGS_XIP_H -// ============================================================================= -// Register : XIP_CTRL -// Description : Cache control -#define XIP_CTRL_OFFSET _u(0x00000000) -#define XIP_CTRL_BITS _u(0x0000000b) -#define XIP_CTRL_RESET _u(0x00000003) -// ----------------------------------------------------------------------------- -// Field : XIP_CTRL_POWER_DOWN -// Description : When 1, the cache memories are powered down. They retain state, -// but can not be accessed. This reduces static power dissipation. -// Writing 1 to this bit forces CTRL_EN to 0, i.e. the cache -// cannot -// be enabled when powered down. -// Cache-as-SRAM accesses will produce a bus error response when -// the cache is powered down. -#define XIP_CTRL_POWER_DOWN_RESET _u(0x0) -#define XIP_CTRL_POWER_DOWN_BITS _u(0x00000008) -#define XIP_CTRL_POWER_DOWN_MSB _u(3) -#define XIP_CTRL_POWER_DOWN_LSB _u(3) -#define XIP_CTRL_POWER_DOWN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : XIP_CTRL_ERR_BADWRITE -// Description : When 1, writes to any alias other than 0x0 (caching, -// allocating) -// will produce a bus fault. When 0, these writes are silently -// ignored. -// In either case, writes to the 0x0 alias will deallocate on tag -// match, -// as usual. -#define XIP_CTRL_ERR_BADWRITE_RESET _u(0x1) -#define XIP_CTRL_ERR_BADWRITE_BITS _u(0x00000002) -#define XIP_CTRL_ERR_BADWRITE_MSB _u(1) -#define XIP_CTRL_ERR_BADWRITE_LSB _u(1) -#define XIP_CTRL_ERR_BADWRITE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : XIP_CTRL_EN -// Description : When 1, enable the cache. When the cache is disabled, all XIP -// accesses -// will go straight to the flash, without querying the cache. When -// enabled, -// cacheable XIP accesses will query the cache, and the flash will -// not be accessed if the tag matches and the valid bit is set. -// -// If the cache is enabled, cache-as-SRAM accesses have no effect -// on the -// cache data RAM, and will produce a bus error response. -#define XIP_CTRL_EN_RESET _u(0x1) -#define XIP_CTRL_EN_BITS _u(0x00000001) -#define XIP_CTRL_EN_MSB _u(0) -#define XIP_CTRL_EN_LSB _u(0) -#define XIP_CTRL_EN_ACCESS "RW" -// ============================================================================= -// Register : XIP_FLUSH -// Description : Cache Flush control -// Write 1 to flush the cache. This clears the tag memory, but -// the data memory retains its contents. (This means cache-as-SRAM -// contents is not affected by flush or reset.) -// Reading will hold the bus (stall the processor) until the flush -// completes. Alternatively STAT can be polled until completion. -#define XIP_FLUSH_OFFSET _u(0x00000004) -#define XIP_FLUSH_BITS _u(0x00000001) -#define XIP_FLUSH_RESET _u(0x00000000) -#define XIP_FLUSH_MSB _u(0) -#define XIP_FLUSH_LSB _u(0) -#define XIP_FLUSH_ACCESS "SC" -// ============================================================================= -// Register : XIP_STAT -// Description : Cache Status -#define XIP_STAT_OFFSET _u(0x00000008) -#define XIP_STAT_BITS _u(0x00000007) -#define XIP_STAT_RESET _u(0x00000002) -// ----------------------------------------------------------------------------- -// Field : XIP_STAT_FIFO_FULL -// Description : When 1, indicates the XIP streaming FIFO is completely full. -// The streaming FIFO is 2 entries deep, so the full and empty -// flag allow its level to be ascertained. -#define XIP_STAT_FIFO_FULL_RESET _u(0x0) -#define XIP_STAT_FIFO_FULL_BITS _u(0x00000004) -#define XIP_STAT_FIFO_FULL_MSB _u(2) -#define XIP_STAT_FIFO_FULL_LSB _u(2) -#define XIP_STAT_FIFO_FULL_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : XIP_STAT_FIFO_EMPTY -// Description : When 1, indicates the XIP streaming FIFO is completely empty. -#define XIP_STAT_FIFO_EMPTY_RESET _u(0x1) -#define XIP_STAT_FIFO_EMPTY_BITS _u(0x00000002) -#define XIP_STAT_FIFO_EMPTY_MSB _u(1) -#define XIP_STAT_FIFO_EMPTY_LSB _u(1) -#define XIP_STAT_FIFO_EMPTY_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : XIP_STAT_FLUSH_READY -// Description : Reads as 0 while a cache flush is in progress, and 1 otherwise. -// The cache is flushed whenever the XIP block is reset, and also -// when requested via the FLUSH register. -#define XIP_STAT_FLUSH_READY_RESET _u(0x0) -#define XIP_STAT_FLUSH_READY_BITS _u(0x00000001) -#define XIP_STAT_FLUSH_READY_MSB _u(0) -#define XIP_STAT_FLUSH_READY_LSB _u(0) -#define XIP_STAT_FLUSH_READY_ACCESS "RO" -// ============================================================================= -// Register : XIP_CTR_HIT -// Description : Cache Hit counter -// A 32 bit saturating counter that increments upon each cache -// hit, -// i.e. when an XIP access is serviced directly from cached data. -// Write any value to clear. -#define XIP_CTR_HIT_OFFSET _u(0x0000000c) -#define XIP_CTR_HIT_BITS _u(0xffffffff) -#define XIP_CTR_HIT_RESET _u(0x00000000) -#define XIP_CTR_HIT_MSB _u(31) -#define XIP_CTR_HIT_LSB _u(0) -#define XIP_CTR_HIT_ACCESS "WC" -// ============================================================================= -// Register : XIP_CTR_ACC -// Description : Cache Access counter -// A 32 bit saturating counter that increments upon each XIP -// access, -// whether the cache is hit or not. This includes noncacheable -// accesses. -// Write any value to clear. -#define XIP_CTR_ACC_OFFSET _u(0x00000010) -#define XIP_CTR_ACC_BITS _u(0xffffffff) -#define XIP_CTR_ACC_RESET _u(0x00000000) -#define XIP_CTR_ACC_MSB _u(31) -#define XIP_CTR_ACC_LSB _u(0) -#define XIP_CTR_ACC_ACCESS "WC" -// ============================================================================= -// Register : XIP_STREAM_ADDR -// Description : FIFO stream address -// The address of the next word to be streamed from flash to the -// streaming FIFO. -// Increments automatically after each flash access. -// Write the initial access address here before starting a -// streaming read. -#define XIP_STREAM_ADDR_OFFSET _u(0x00000014) -#define XIP_STREAM_ADDR_BITS _u(0xfffffffc) -#define XIP_STREAM_ADDR_RESET _u(0x00000000) -#define XIP_STREAM_ADDR_MSB _u(31) -#define XIP_STREAM_ADDR_LSB _u(2) -#define XIP_STREAM_ADDR_ACCESS "RW" -// ============================================================================= -// Register : XIP_STREAM_CTR -// Description : FIFO stream control -// Write a nonzero value to start a streaming read. This will then -// progress in the background, using flash idle cycles to transfer -// a linear data block from flash to the streaming FIFO. -// Decrements automatically (1 at a time) as the stream -// progresses, and halts on reaching 0. -// Write 0 to halt an in-progress stream, and discard any in- -// flight -// read, so that a new stream can immediately be started (after -// draining the FIFO and reinitialising STREAM_ADDR) -#define XIP_STREAM_CTR_OFFSET _u(0x00000018) -#define XIP_STREAM_CTR_BITS _u(0x003fffff) -#define XIP_STREAM_CTR_RESET _u(0x00000000) -#define XIP_STREAM_CTR_MSB _u(21) -#define XIP_STREAM_CTR_LSB _u(0) -#define XIP_STREAM_CTR_ACCESS "RW" -// ============================================================================= -// Register : XIP_STREAM_FIFO -// Description : FIFO stream data -// Streamed data is buffered here, for retrieval by the system -// DMA. -// This FIFO can also be accessed via the XIP_AUX slave, to avoid -// exposing -// the DMA to bus stalls caused by other XIP traffic. -#define XIP_STREAM_FIFO_OFFSET _u(0x0000001c) -#define XIP_STREAM_FIFO_BITS _u(0xffffffff) -#define XIP_STREAM_FIFO_RESET _u(0x00000000) -#define XIP_STREAM_FIFO_MSB _u(31) -#define XIP_STREAM_FIFO_LSB _u(0) -#define XIP_STREAM_FIFO_ACCESS "RF" -// ============================================================================= -#endif // _HARDWARE_REGS_XIP_H - diff --git a/lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/xosc.h b/lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/xosc.h deleted file mode 100644 index 8076a99d4a..0000000000 --- a/lib/main/pico-sdk/rp2040/hardware_regs/include/hardware/regs/xosc.h +++ /dev/null @@ -1,165 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -// ============================================================================= -// Register block : XOSC -// Version : 1 -// Bus type : apb -// Description : Controls the crystal oscillator -// ============================================================================= -#ifndef _HARDWARE_REGS_XOSC_H -#define _HARDWARE_REGS_XOSC_H -// ============================================================================= -// Register : XOSC_CTRL -// Description : Crystal Oscillator Control -#define XOSC_CTRL_OFFSET _u(0x00000000) -#define XOSC_CTRL_BITS _u(0x00ffffff) -#define XOSC_CTRL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : XOSC_CTRL_ENABLE -// Description : On power-up this field is initialised to DISABLE and the chip -// runs from the ROSC. -// If the chip has subsequently been programmed to run from the -// XOSC then DISABLE may lock-up the chip. If this is a concern -// then run the clk_ref from the ROSC and enable the clk_sys RESUS -// feature. -// The 12-bit code is intended to give some protection against -// accidental writes. An invalid setting will enable the -// oscillator. -// 0xd1e -> DISABLE -// 0xfab -> ENABLE -#define XOSC_CTRL_ENABLE_RESET "-" -#define XOSC_CTRL_ENABLE_BITS _u(0x00fff000) -#define XOSC_CTRL_ENABLE_MSB _u(23) -#define XOSC_CTRL_ENABLE_LSB _u(12) -#define XOSC_CTRL_ENABLE_ACCESS "RW" -#define XOSC_CTRL_ENABLE_VALUE_DISABLE _u(0xd1e) -#define XOSC_CTRL_ENABLE_VALUE_ENABLE _u(0xfab) -// ----------------------------------------------------------------------------- -// Field : XOSC_CTRL_FREQ_RANGE -// Description : Frequency range. An invalid setting will retain the previous -// value. The actual value being used can be read from -// STATUS_FREQ_RANGE. This resets to 0xAA0 and cannot be changed. -// 0xaa0 -> 1_15MHZ -// 0xaa1 -> RESERVED_1 -// 0xaa2 -> RESERVED_2 -// 0xaa3 -> RESERVED_3 -#define XOSC_CTRL_FREQ_RANGE_RESET "-" -#define XOSC_CTRL_FREQ_RANGE_BITS _u(0x00000fff) -#define XOSC_CTRL_FREQ_RANGE_MSB _u(11) -#define XOSC_CTRL_FREQ_RANGE_LSB _u(0) -#define XOSC_CTRL_FREQ_RANGE_ACCESS "RW" -#define XOSC_CTRL_FREQ_RANGE_VALUE_1_15MHZ _u(0xaa0) -#define XOSC_CTRL_FREQ_RANGE_VALUE_RESERVED_1 _u(0xaa1) -#define XOSC_CTRL_FREQ_RANGE_VALUE_RESERVED_2 _u(0xaa2) -#define XOSC_CTRL_FREQ_RANGE_VALUE_RESERVED_3 _u(0xaa3) -// ============================================================================= -// Register : XOSC_STATUS -// Description : Crystal Oscillator Status -#define XOSC_STATUS_OFFSET _u(0x00000004) -#define XOSC_STATUS_BITS _u(0x81001003) -#define XOSC_STATUS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : XOSC_STATUS_STABLE -// Description : Oscillator is running and stable -#define XOSC_STATUS_STABLE_RESET _u(0x0) -#define XOSC_STATUS_STABLE_BITS _u(0x80000000) -#define XOSC_STATUS_STABLE_MSB _u(31) -#define XOSC_STATUS_STABLE_LSB _u(31) -#define XOSC_STATUS_STABLE_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : XOSC_STATUS_BADWRITE -// Description : An invalid value has been written to CTRL_ENABLE or -// CTRL_FREQ_RANGE or DORMANT -#define XOSC_STATUS_BADWRITE_RESET _u(0x0) -#define XOSC_STATUS_BADWRITE_BITS _u(0x01000000) -#define XOSC_STATUS_BADWRITE_MSB _u(24) -#define XOSC_STATUS_BADWRITE_LSB _u(24) -#define XOSC_STATUS_BADWRITE_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : XOSC_STATUS_ENABLED -// Description : Oscillator is enabled but not necessarily running and stable, -// resets to 0 -#define XOSC_STATUS_ENABLED_RESET "-" -#define XOSC_STATUS_ENABLED_BITS _u(0x00001000) -#define XOSC_STATUS_ENABLED_MSB _u(12) -#define XOSC_STATUS_ENABLED_LSB _u(12) -#define XOSC_STATUS_ENABLED_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : XOSC_STATUS_FREQ_RANGE -// Description : The current frequency range setting, always reads 0 -// 0x0 -> 1_15MHZ -// 0x1 -> RESERVED_1 -// 0x2 -> RESERVED_2 -// 0x3 -> RESERVED_3 -#define XOSC_STATUS_FREQ_RANGE_RESET "-" -#define XOSC_STATUS_FREQ_RANGE_BITS _u(0x00000003) -#define XOSC_STATUS_FREQ_RANGE_MSB _u(1) -#define XOSC_STATUS_FREQ_RANGE_LSB _u(0) -#define XOSC_STATUS_FREQ_RANGE_ACCESS "RO" -#define XOSC_STATUS_FREQ_RANGE_VALUE_1_15MHZ _u(0x0) -#define XOSC_STATUS_FREQ_RANGE_VALUE_RESERVED_1 _u(0x1) -#define XOSC_STATUS_FREQ_RANGE_VALUE_RESERVED_2 _u(0x2) -#define XOSC_STATUS_FREQ_RANGE_VALUE_RESERVED_3 _u(0x3) -// ============================================================================= -// Register : XOSC_DORMANT -// Description : Crystal Oscillator pause control -// This is used to save power by pausing the XOSC -// On power-up this field is initialised to WAKE -// An invalid write will also select WAKE -// Warning: stop the PLLs before selecting dormant mode -// Warning: setup the irq before selecting dormant mode -// 0x636f6d61 -> dormant -// 0x77616b65 -> WAKE -#define XOSC_DORMANT_OFFSET _u(0x00000008) -#define XOSC_DORMANT_BITS _u(0xffffffff) -#define XOSC_DORMANT_RESET "-" -#define XOSC_DORMANT_MSB _u(31) -#define XOSC_DORMANT_LSB _u(0) -#define XOSC_DORMANT_ACCESS "RW" -#define XOSC_DORMANT_VALUE_DORMANT _u(0x636f6d61) -#define XOSC_DORMANT_VALUE_WAKE _u(0x77616b65) -// ============================================================================= -// Register : XOSC_STARTUP -// Description : Controls the startup delay -#define XOSC_STARTUP_OFFSET _u(0x0000000c) -#define XOSC_STARTUP_BITS _u(0x00103fff) -#define XOSC_STARTUP_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : XOSC_STARTUP_X4 -// Description : Multiplies the startup_delay by 4. This is of little value to -// the user given that the delay can be programmed directly. -#define XOSC_STARTUP_X4_RESET "-" -#define XOSC_STARTUP_X4_BITS _u(0x00100000) -#define XOSC_STARTUP_X4_MSB _u(20) -#define XOSC_STARTUP_X4_LSB _u(20) -#define XOSC_STARTUP_X4_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : XOSC_STARTUP_DELAY -// Description : in multiples of 256*xtal_period. The reset value of 0xc4 -// corresponds to approx 50 000 cycles. -#define XOSC_STARTUP_DELAY_RESET "-" -#define XOSC_STARTUP_DELAY_BITS _u(0x00003fff) -#define XOSC_STARTUP_DELAY_MSB _u(13) -#define XOSC_STARTUP_DELAY_LSB _u(0) -#define XOSC_STARTUP_DELAY_ACCESS "RW" -// ============================================================================= -// Register : XOSC_COUNT -// Description : A down counter running at the xosc frequency which counts to -// zero and stops. -// To start the counter write a non-zero value. -// Can be used for short software pauses when setting up time -// sensitive hardware. -#define XOSC_COUNT_OFFSET _u(0x0000001c) -#define XOSC_COUNT_BITS _u(0x000000ff) -#define XOSC_COUNT_RESET _u(0x00000000) -#define XOSC_COUNT_MSB _u(7) -#define XOSC_COUNT_LSB _u(0) -#define XOSC_COUNT_ACCESS "RW" -// ============================================================================= -#endif // _HARDWARE_REGS_XOSC_H - diff --git a/lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/adc.h b/lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/adc.h deleted file mode 100644 index a1b6f34c5c..0000000000 --- a/lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/adc.h +++ /dev/null @@ -1,96 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _HARDWARE_STRUCTS_ADC_H -#define _HARDWARE_STRUCTS_ADC_H - -/** - * \file rp2040/adc.h - */ - -#include "hardware/address_mapped.h" -#include "hardware/regs/adc.h" - -// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_adc -// -// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) -// _REG_(x) will link to the corresponding register in hardware/regs/adc.h. -// -// Bit-field descriptions are of the form: -// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION - -typedef struct { - _REG_(ADC_CS_OFFSET) // ADC_CS - // ADC Control and Status - // 0x001f0000 [20:16] RROBIN (0x00) Round-robin sampling - // 0x00007000 [14:12] AINSEL (0x0) Select analog mux input - // 0x00000400 [10] ERR_STICKY (0) Some past ADC conversion encountered an error - // 0x00000200 [9] ERR (0) The most recent ADC conversion encountered an error;... - // 0x00000100 [8] READY (0) 1 if the ADC is ready to start a new conversion - // 0x00000008 [3] START_MANY (0) Continuously perform conversions whilst this bit is 1 - // 0x00000004 [2] START_ONCE (0) Start a single conversion - // 0x00000002 [1] TS_EN (0) Power on temperature sensor - // 0x00000001 [0] EN (0) Power on ADC and enable its clock - io_rw_32 cs; - - _REG_(ADC_RESULT_OFFSET) // ADC_RESULT - // Result of most recent ADC conversion - // 0x00000fff [11:0] RESULT (0x000) - io_ro_32 result; - - _REG_(ADC_FCS_OFFSET) // ADC_FCS - // FIFO control and status - // 0x0f000000 [27:24] THRESH (0x0) DREQ/IRQ asserted when level >= threshold - // 0x000f0000 [19:16] LEVEL (0x0) The number of conversion results currently waiting in the FIFO - // 0x00000800 [11] OVER (0) 1 if the FIFO has been overflowed - // 0x00000400 [10] UNDER (0) 1 if the FIFO has been underflowed - // 0x00000200 [9] FULL (0) - // 0x00000100 [8] EMPTY (0) - // 0x00000008 [3] DREQ_EN (0) If 1: assert DMA requests when FIFO contains data - // 0x00000004 [2] ERR (0) If 1: conversion error bit appears in the FIFO alongside... - // 0x00000002 [1] SHIFT (0) If 1: FIFO results are right-shifted to be one byte in size - // 0x00000001 [0] EN (0) If 1: write result to the FIFO after each conversion - io_rw_32 fcs; - - _REG_(ADC_FIFO_OFFSET) // ADC_FIFO - // Conversion result FIFO - // 0x00008000 [15] ERR (-) 1 if this particular sample experienced a conversion error - // 0x00000fff [11:0] VAL (-) - io_ro_32 fifo; - - _REG_(ADC_DIV_OFFSET) // ADC_DIV - // Clock divider - // 0x00ffff00 [23:8] INT (0x0000) Integer part of clock divisor - // 0x000000ff [7:0] FRAC (0x00) Fractional part of clock divisor - io_rw_32 div; - - _REG_(ADC_INTR_OFFSET) // ADC_INTR - // Raw Interrupts - // 0x00000001 [0] FIFO (0) Triggered when the sample FIFO reaches a certain level - io_ro_32 intr; - - _REG_(ADC_INTE_OFFSET) // ADC_INTE - // Interrupt Enable - // 0x00000001 [0] FIFO (0) Triggered when the sample FIFO reaches a certain level - io_rw_32 inte; - - _REG_(ADC_INTF_OFFSET) // ADC_INTF - // Interrupt Force - // 0x00000001 [0] FIFO (0) Triggered when the sample FIFO reaches a certain level - io_rw_32 intf; - - _REG_(ADC_INTS_OFFSET) // ADC_INTS - // Interrupt status after masking & forcing - // 0x00000001 [0] FIFO (0) Triggered when the sample FIFO reaches a certain level - io_ro_32 ints; -} adc_hw_t; - -#define adc_hw ((adc_hw_t *)ADC_BASE) -static_assert(sizeof (adc_hw_t) == 0x0024, ""); - -#endif // _HARDWARE_STRUCTS_ADC_H - diff --git a/lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/bus_ctrl.h b/lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/bus_ctrl.h deleted file mode 100644 index b94a40459c..0000000000 --- a/lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/bus_ctrl.h +++ /dev/null @@ -1,9 +0,0 @@ -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -// Support old header for compatibility (and if included, support old variable name) -#include "hardware/structs/busctrl.h" -#define bus_ctrl_hw busctrl_hw \ No newline at end of file diff --git a/lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/busctrl.h b/lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/busctrl.h deleted file mode 100644 index 65893227dd..0000000000 --- a/lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/busctrl.h +++ /dev/null @@ -1,85 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _HARDWARE_STRUCTS_BUSCTRL_H -#define _HARDWARE_STRUCTS_BUSCTRL_H - -/** - * \file rp2040/busctrl.h - */ - -#include "hardware/address_mapped.h" -#include "hardware/regs/busctrl.h" - -// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_busctrl -// -// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) -// _REG_(x) will link to the corresponding register in hardware/regs/busctrl.h. -// -// Bit-field descriptions are of the form: -// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION - -/** \brief Bus fabric performance counters on RP2040 (used as typedef \ref bus_ctrl_perf_counter_t) - * \ingroup hardware_busctrl - */ -typedef enum bus_ctrl_perf_counter_rp2040 { - arbiter_rom_perf_event_access = 19, - arbiter_rom_perf_event_access_contested = 18, - arbiter_xip_main_perf_event_access = 17, - arbiter_xip_main_perf_event_access_contested = 16, - arbiter_sram0_perf_event_access = 15, - arbiter_sram0_perf_event_access_contested = 14, - arbiter_sram1_perf_event_access = 13, - arbiter_sram1_perf_event_access_contested = 12, - arbiter_sram2_perf_event_access = 11, - arbiter_sram2_perf_event_access_contested = 10, - arbiter_sram3_perf_event_access = 9, - arbiter_sram3_perf_event_access_contested = 8, - arbiter_sram4_perf_event_access = 7, - arbiter_sram4_perf_event_access_contested = 6, - arbiter_sram5_perf_event_access = 5, - arbiter_sram5_perf_event_access_contested = 4, - arbiter_fastperi_perf_event_access = 3, - arbiter_fastperi_perf_event_access_contested = 2, - arbiter_apb_perf_event_access = 1, - arbiter_apb_perf_event_access_contested = 0 -} bus_ctrl_perf_counter_t; - -typedef struct { - _REG_(BUSCTRL_PERFCTR0_OFFSET) // BUSCTRL_PERFCTR0 - // Bus fabric performance counter 0 - // 0x00ffffff [23:0] PERFCTR0 (0x000000) Busfabric saturating performance counter 0 + - io_rw_32 value; - - _REG_(BUSCTRL_PERFSEL0_OFFSET) // BUSCTRL_PERFSEL0 - // Bus fabric performance event select for PERFCTR0 - // 0x0000001f [4:0] PERFSEL0 (0x1f) Select an event for PERFCTR0 - io_rw_32 sel; -} bus_ctrl_perf_hw_t; - -typedef struct { - _REG_(BUSCTRL_BUS_PRIORITY_OFFSET) // BUSCTRL_BUS_PRIORITY - // Set the priority of each master for bus arbitration - // 0x00001000 [12] DMA_W (0) 0 - low priority, 1 - high priority - // 0x00000100 [8] DMA_R (0) 0 - low priority, 1 - high priority - // 0x00000010 [4] PROC1 (0) 0 - low priority, 1 - high priority - // 0x00000001 [0] PROC0 (0) 0 - low priority, 1 - high priority - io_rw_32 priority; - - _REG_(BUSCTRL_BUS_PRIORITY_ACK_OFFSET) // BUSCTRL_BUS_PRIORITY_ACK - // Bus priority acknowledge - // 0x00000001 [0] BUS_PRIORITY_ACK (0) Goes to 1 once all arbiters have registered the new... - io_ro_32 priority_ack; - - bus_ctrl_perf_hw_t counter[4]; -} busctrl_hw_t; - -#define busctrl_hw ((busctrl_hw_t *)BUSCTRL_BASE) -static_assert(sizeof (busctrl_hw_t) == 0x0028, ""); - -#endif // _HARDWARE_STRUCTS_BUSCTRL_H - diff --git a/lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/clocks.h b/lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/clocks.h deleted file mode 100644 index bdca7ee08d..0000000000 --- a/lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/clocks.h +++ /dev/null @@ -1,504 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _HARDWARE_STRUCTS_CLOCKS_H -#define _HARDWARE_STRUCTS_CLOCKS_H - -/** - * \file rp2040/clocks.h - */ - -#include "hardware/address_mapped.h" -#include "hardware/regs/clocks.h" - -// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_clocks -// -// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) -// _REG_(x) will link to the corresponding register in hardware/regs/clocks.h. -// -// Bit-field descriptions are of the form: -// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION - -/** \brief Clock numbers on RP2040 (used as typedef \ref clock_num_t) - * \ingroup hardware_clocks - */ -/// \tag::clkenum[] -typedef enum clock_num_rp2040 { - clk_gpout0 = 0, ///< Select CLK_GPOUT0 as clock source - clk_gpout1 = 1, ///< Select CLK_GPOUT1 as clock source - clk_gpout2 = 2, ///< Select CLK_GPOUT2 as clock source - clk_gpout3 = 3, ///< Select CLK_GPOUT3 as clock source - clk_ref = 4, ///< Select CLK_REF as clock source - clk_sys = 5, ///< Select CLK_SYS as clock source - clk_peri = 6, ///< Select CLK_PERI as clock source - clk_usb = 7, ///< Select CLK_USB as clock source - clk_adc = 8, ///< Select CLK_ADC as clock source - clk_rtc = 9, ///< Select CLK_RTC as clock source - CLK_COUNT -} clock_num_t; -/// \end::clkenum[] - -/** \brief Clock destination numbers on RP2040 (used as typedef \ref clock_dest_num_t) - * \ingroup hardware_clocks - */ -typedef enum clock_dest_num_rp2040 { - CLK_DEST_SYS_CLOCKS = 0, ///< Select SYS_CLOCKS as clock destination - CLK_DEST_ADC_ADC = 1, ///< Select ADC_ADC as clock destination - CLK_DEST_SYS_ADC = 2, ///< Select SYS_ADC as clock destination - CLK_DEST_SYS_BUSCTRL = 3, ///< Select SYS_BUSCTRL as clock destination - CLK_DEST_SYS_BUSFABRIC = 4, ///< Select SYS_BUSFABRIC as clock destination - CLK_DEST_SYS_DMA = 5, ///< Select SYS_DMA as clock destination - CLK_DEST_SYS_I2C0 = 6, ///< Select SYS_I2C0 as clock destination - CLK_DEST_SYS_I2C1 = 7, ///< Select SYS_I2C1 as clock destination - CLK_DEST_SYS_IO = 8, ///< Select SYS_IO as clock destination - CLK_DEST_SYS_JTAG = 9, ///< Select SYS_JTAG as clock destination - CLK_DEST_SYS_VREG_AND_CHIP_RESET = 10, ///< Select SYS_VREG_AND_CHIP_RESET as clock destination - CLK_DEST_SYS_PADS = 11, ///< Select SYS_PADS as clock destination - CLK_DEST_SYS_PIO0 = 12, ///< Select SYS_PIO0 as clock destination - CLK_DEST_SYS_PIO1 = 13, ///< Select SYS_PIO1 as clock destination - CLK_DEST_SYS_PLL_SYS = 14, ///< Select SYS_PLL_SYS as clock destination - CLK_DEST_SYS_PLL_USB = 15, ///< Select SYS_PLL_USB as clock destination - CLK_DEST_SYS_PSM = 16, ///< Select SYS_PSM as clock destination - CLK_DEST_SYS_PWM = 17, ///< Select SYS_PWM as clock destination - CLK_DEST_SYS_RESETS = 18, ///< Select SYS_RESETS as clock destination - CLK_DEST_SYS_ROM = 19, ///< Select SYS_ROM as clock destination - CLK_DEST_SYS_ROSC = 20, ///< Select SYS_ROSC as clock destination - CLK_DEST_RTC_RTC = 21, ///< Select RTC_RTC as clock destination - CLK_DEST_SYS_RTC = 22, ///< Select SYS_RTC as clock destination - CLK_DEST_SYS_SIO = 23, ///< Select SYS_SIO as clock destination - CLK_DEST_PERI_SPI0 = 24, ///< Select PERI_SPI0 as clock destination - CLK_DEST_SYS_SPI0 = 25, ///< Select SYS_SPI0 as clock destination - CLK_DEST_PERI_SPI1 = 26, ///< Select PERI_SPI1 as clock destination - CLK_DEST_SYS_SPI1 = 27, ///< Select SYS_SPI1 as clock destination - CLK_DEST_SYS_SRAM0 = 28, ///< Select SYS_SRAM0 as clock destination - CLK_DEST_SYS_SRAM1 = 29, ///< Select SYS_SRAM1 as clock destination - CLK_DEST_SYS_SRAM2 = 30, ///< Select SYS_SRAM2 as clock destination - CLK_DEST_SYS_SRAM3 = 31, ///< Select SYS_SRAM3 as clock destination - CLK_DEST_SYS_SRAM4 = 32, ///< Select SYS_SRAM4 as clock destination - CLK_DEST_SYS_SRAM5 = 33, ///< Select SYS_SRAM5 as clock destination - CLK_DEST_SYS_SYSCFG = 34, ///< Select SYS_SYSCFG as clock destination - CLK_DEST_SYS_SYSINFO = 35, ///< Select SYS_SYSINFO as clock destination - CLK_DEST_SYS_TBMAN = 36, ///< Select SYS_TBMAN as clock destination - CLK_DEST_SYS_TIMER = 37, ///< Select SYS_TIMER as clock destination - CLK_DEST_PERI_UART0 = 38, ///< Select PERI_UART0 as clock destination - CLK_DEST_SYS_UART0 = 39, ///< Select SYS_UART0 as clock destination - CLK_DEST_PERI_UART1 = 40, ///< Select PERI_UART1 as clock destination - CLK_DEST_SYS_UART1 = 41, ///< Select SYS_UART1 as clock destination - CLK_DEST_SYS_USBCTRL = 42, ///< Select SYS_USBCTRL as clock destination - CLK_DEST_USB_USBCTRL = 43, ///< Select USB_USBCTRL as clock destination - CLK_DEST_SYS_WATCHDOG = 44, ///< Select SYS_WATCHDOG as clock destination - CLK_DEST_SYS_XIP = 45, ///< Select SYS_XIP as clock destination - CLK_DEST_SYS_XOSC = 46, ///< Select SYS_XOSC as clock destination - NUM_CLOCK_DESTINATIONS -} clock_dest_num_t; - -/// \tag::clock_hw[] -typedef struct { - _REG_(CLOCKS_CLK_GPOUT0_CTRL_OFFSET) // CLOCKS_CLK_GPOUT0_CTRL - // Clock control, can be changed on-the-fly (except for auxsrc) - // 0x00100000 [20] NUDGE (0) An edge on this signal shifts the phase of the output by... - // 0x00030000 [17:16] PHASE (0x0) This delays the enable signal by up to 3 cycles of the... - // 0x00001000 [12] DC50 (0) Enables duty cycle correction for odd divisors - // 0x00000800 [11] ENABLE (0) Starts and stops the clock generator cleanly - // 0x00000400 [10] KILL (0) Asynchronously kills the clock generator - // 0x000001e0 [8:5] AUXSRC (0x0) Selects the auxiliary clock source, will glitch when switching - io_rw_32 ctrl; - - _REG_(CLOCKS_CLK_GPOUT0_DIV_OFFSET) // CLOCKS_CLK_GPOUT0_DIV - // Clock divisor, can be changed on-the-fly - // 0xffffff00 [31:8] INT (0x000001) Integer component of the divisor, 0 -> divide by 2^16 - // 0x000000ff [7:0] FRAC (0x00) Fractional component of the divisor - io_rw_32 div; - - _REG_(CLOCKS_CLK_GPOUT0_SELECTED_OFFSET) // CLOCKS_CLK_GPOUT0_SELECTED - // Indicates which SRC is currently selected by the glitchless mux (one-hot) - // 0xffffffff [31:0] CLK_GPOUT0_SELECTED (0x00000001) This slice does not have a glitchless mux (only the... - io_ro_32 selected; -} clock_hw_t; -/// \end::clock_hw[] - -typedef struct { - _REG_(CLOCKS_CLK_SYS_RESUS_CTRL_OFFSET) // CLOCKS_CLK_SYS_RESUS_CTRL - // 0x00010000 [16] CLEAR (0) For clearing the resus after the fault that triggered it... - // 0x00001000 [12] FRCE (0) Force a resus, for test purposes only - // 0x00000100 [8] ENABLE (0) Enable resus - // 0x000000ff [7:0] TIMEOUT (0xff) This is expressed as a number of clk_ref cycles + - io_rw_32 ctrl; - - _REG_(CLOCKS_CLK_SYS_RESUS_STATUS_OFFSET) // CLOCKS_CLK_SYS_RESUS_STATUS - // 0x00000001 [0] RESUSSED (0) Clock has been resuscitated, correct the error then send... - io_ro_32 status; -} clock_resus_hw_t; - -typedef struct { - _REG_(CLOCKS_FC0_REF_KHZ_OFFSET) // CLOCKS_FC0_REF_KHZ - // Reference clock frequency in kHz - // 0x000fffff [19:0] FC0_REF_KHZ (0x00000) - io_rw_32 ref_khz; - - _REG_(CLOCKS_FC0_MIN_KHZ_OFFSET) // CLOCKS_FC0_MIN_KHZ - // Minimum pass frequency in kHz - // 0x01ffffff [24:0] FC0_MIN_KHZ (0x0000000) - io_rw_32 min_khz; - - _REG_(CLOCKS_FC0_MAX_KHZ_OFFSET) // CLOCKS_FC0_MAX_KHZ - // Maximum pass frequency in kHz - // 0x01ffffff [24:0] FC0_MAX_KHZ (0x1ffffff) - io_rw_32 max_khz; - - _REG_(CLOCKS_FC0_DELAY_OFFSET) // CLOCKS_FC0_DELAY - // Delays the start of frequency counting to allow the mux to settle + - // 0x00000007 [2:0] FC0_DELAY (0x1) - io_rw_32 delay; - - _REG_(CLOCKS_FC0_INTERVAL_OFFSET) // CLOCKS_FC0_INTERVAL - // The test interval is 0 - // 0x0000000f [3:0] FC0_INTERVAL (0x8) - io_rw_32 interval; - - _REG_(CLOCKS_FC0_SRC_OFFSET) // CLOCKS_FC0_SRC - // Clock sent to frequency counter, set to 0 when not required + - // 0x000000ff [7:0] FC0_SRC (0x00) - io_rw_32 src; - - _REG_(CLOCKS_FC0_STATUS_OFFSET) // CLOCKS_FC0_STATUS - // Frequency counter status - // 0x10000000 [28] DIED (0) Test clock stopped during test - // 0x01000000 [24] FAST (0) Test clock faster than expected, only valid when status_done=1 - // 0x00100000 [20] SLOW (0) Test clock slower than expected, only valid when status_done=1 - // 0x00010000 [16] FAIL (0) Test failed - // 0x00001000 [12] WAITING (0) Waiting for test clock to start - // 0x00000100 [8] RUNNING (0) Test running - // 0x00000010 [4] DONE (0) Test complete - // 0x00000001 [0] PASS (0) Test passed - io_ro_32 status; - - _REG_(CLOCKS_FC0_RESULT_OFFSET) // CLOCKS_FC0_RESULT - // Result of frequency measurement, only valid when status_done=1 - // 0x3fffffe0 [29:5] KHZ (0x0000000) - // 0x0000001f [4:0] FRAC (0x00) - io_ro_32 result; -} fc_hw_t; - -typedef struct { - clock_hw_t clk[10]; - - clock_resus_hw_t resus; - - fc_hw_t fc0; - - union { - struct { - _REG_(CLOCKS_WAKE_EN0_OFFSET) // CLOCKS_WAKE_EN0 - // enable clock in wake mode - // 0x80000000 [31] CLK_SYS_SRAM3 (1) - // 0x40000000 [30] CLK_SYS_SRAM2 (1) - // 0x20000000 [29] CLK_SYS_SRAM1 (1) - // 0x10000000 [28] CLK_SYS_SRAM0 (1) - // 0x08000000 [27] CLK_SYS_SPI1 (1) - // 0x04000000 [26] CLK_PERI_SPI1 (1) - // 0x02000000 [25] CLK_SYS_SPI0 (1) - // 0x01000000 [24] CLK_PERI_SPI0 (1) - // 0x00800000 [23] CLK_SYS_SIOB (1) - // 0x00400000 [22] CLK_SYS_RTC (1) - // 0x00200000 [21] CLK_RTC_RTC (1) - // 0x00100000 [20] CLK_SYS_ROSC (1) - // 0x00080000 [19] CLK_SYS_ROM (1) - // 0x00040000 [18] CLK_SYS_RESETS (1) - // 0x00020000 [17] CLK_SYS_PWM (1) - // 0x00010000 [16] CLK_SYS_POWER (1) - // 0x00008000 [15] CLK_SYS_PLL_USB (1) - // 0x00004000 [14] CLK_SYS_PLL_SYS (1) - // 0x00002000 [13] CLK_SYS_PIO1 (1) - // 0x00001000 [12] CLK_SYS_PIO0 (1) - // 0x00000800 [11] CLK_SYS_PADS (1) - // 0x00000400 [10] CLK_SYS_LDO_POR (1) - // 0x00000200 [9] CLK_SYS_JTAG (1) - // 0x00000100 [8] CLK_SYS_IO (1) - // 0x00000080 [7] CLK_SYS_I2C1 (1) - // 0x00000040 [6] CLK_SYS_I2C0 (1) - // 0x00000020 [5] CLK_SYS_DMA (1) - // 0x00000010 [4] CLK_SYS_BUSFABRIC (1) - // 0x00000008 [3] CLK_SYS_BUSCTRL (1) - // 0x00000004 [2] CLK_SYS_ADC0 (1) - // 0x00000002 [1] CLK_ADC_ADC0 (1) - // 0x00000001 [0] CLK_SYS_CLOCKS_BANK_DEFAULT (1) - io_rw_32 wake_en0; - - _REG_(CLOCKS_WAKE_EN1_OFFSET) // CLOCKS_WAKE_EN1 - // enable clock in wake mode - // 0x00004000 [14] CLK_SYS_XOSC (1) - // 0x00002000 [13] CLK_SYS_XIP (1) - // 0x00001000 [12] CLK_SYS_WATCHDOG (1) - // 0x00000800 [11] CLK_USB_USBCTRL (1) - // 0x00000400 [10] CLK_SYS_USBCTRL (1) - // 0x00000200 [9] CLK_SYS_UART1 (1) - // 0x00000100 [8] CLK_PERI_UART1 (1) - // 0x00000080 [7] CLK_SYS_UART0 (1) - // 0x00000040 [6] CLK_PERI_UART0 (1) - // 0x00000020 [5] CLK_SYS_TIMER (1) - // 0x00000010 [4] CLK_SYS_TBMAN (1) - // 0x00000008 [3] CLK_SYS_SYSINFO (1) - // 0x00000004 [2] CLK_SYS_SYSCFG (1) - // 0x00000002 [1] CLK_SYS_SRAM5 (1) - // 0x00000001 [0] CLK_SYS_SRAM4 (1) - io_rw_32 wake_en1; - }; - // (Description copied from array index 0 register CLOCKS_WAKE_EN0 applies similarly to other array indexes) - _REG_(CLOCKS_WAKE_EN0_OFFSET) // CLOCKS_WAKE_EN0 - // enable clock in wake mode - // 0x80000000 [31] CLK_SYS_SRAM3 (1) - // 0x40000000 [30] CLK_SYS_SRAM2 (1) - // 0x20000000 [29] CLK_SYS_SRAM1 (1) - // 0x10000000 [28] CLK_SYS_SRAM0 (1) - // 0x08000000 [27] CLK_SYS_SPI1 (1) - // 0x04000000 [26] CLK_PERI_SPI1 (1) - // 0x02000000 [25] CLK_SYS_SPI0 (1) - // 0x01000000 [24] CLK_PERI_SPI0 (1) - // 0x00800000 [23] CLK_SYS_SIO (1) - // 0x00400000 [22] CLK_SYS_RTC (1) - // 0x00200000 [21] CLK_RTC_RTC (1) - // 0x00100000 [20] CLK_SYS_ROSC (1) - // 0x00080000 [19] CLK_SYS_ROM (1) - // 0x00040000 [18] CLK_SYS_RESETS (1) - // 0x00020000 [17] CLK_SYS_PWM (1) - // 0x00010000 [16] CLK_SYS_PSM (1) - // 0x00008000 [15] CLK_SYS_PLL_USB (1) - // 0x00004000 [14] CLK_SYS_PLL_SYS (1) - // 0x00002000 [13] CLK_SYS_PIO1 (1) - // 0x00001000 [12] CLK_SYS_PIO0 (1) - // 0x00000800 [11] CLK_SYS_PADS (1) - // 0x00000400 [10] CLK_SYS_VREG_AND_CHIP_RESET (1) - // 0x00000200 [9] CLK_SYS_JTAG (1) - // 0x00000100 [8] CLK_SYS_IO (1) - // 0x00000080 [7] CLK_SYS_I2C1 (1) - // 0x00000040 [6] CLK_SYS_I2C0 (1) - // 0x00000020 [5] CLK_SYS_DMA (1) - // 0x00000010 [4] CLK_SYS_BUSFABRIC (1) - // 0x00000008 [3] CLK_SYS_BUSCTRL (1) - // 0x00000004 [2] CLK_SYS_ADC (1) - // 0x00000002 [1] CLK_ADC_ADC (1) - // 0x00000001 [0] CLK_SYS_CLOCKS (1) - io_rw_32 wake_en[2]; - }; - - union { - struct { - _REG_(CLOCKS_SLEEP_EN0_OFFSET) // CLOCKS_SLEEP_EN0 - // enable clock in sleep mode - // 0x80000000 [31] CLK_SYS_SRAM3 (1) - // 0x40000000 [30] CLK_SYS_SRAM2 (1) - // 0x20000000 [29] CLK_SYS_SRAM1 (1) - // 0x10000000 [28] CLK_SYS_SRAM0 (1) - // 0x08000000 [27] CLK_SYS_SPI1 (1) - // 0x04000000 [26] CLK_PERI_SPI1 (1) - // 0x02000000 [25] CLK_SYS_SPI0 (1) - // 0x01000000 [24] CLK_PERI_SPI0 (1) - // 0x00800000 [23] CLK_SYS_SIOB (1) - // 0x00400000 [22] CLK_SYS_RTC (1) - // 0x00200000 [21] CLK_RTC_RTC (1) - // 0x00100000 [20] CLK_SYS_ROSC (1) - // 0x00080000 [19] CLK_SYS_ROM (1) - // 0x00040000 [18] CLK_SYS_RESETS (1) - // 0x00020000 [17] CLK_SYS_PWM (1) - // 0x00010000 [16] CLK_SYS_POWER (1) - // 0x00008000 [15] CLK_SYS_PLL_USB (1) - // 0x00004000 [14] CLK_SYS_PLL_SYS (1) - // 0x00002000 [13] CLK_SYS_PIO1 (1) - // 0x00001000 [12] CLK_SYS_PIO0 (1) - // 0x00000800 [11] CLK_SYS_PADS (1) - // 0x00000400 [10] CLK_SYS_LDO_POR (1) - // 0x00000200 [9] CLK_SYS_JTAG (1) - // 0x00000100 [8] CLK_SYS_IO (1) - // 0x00000080 [7] CLK_SYS_I2C1 (1) - // 0x00000040 [6] CLK_SYS_I2C0 (1) - // 0x00000020 [5] CLK_SYS_DMA (1) - // 0x00000010 [4] CLK_SYS_BUSFABRIC (1) - // 0x00000008 [3] CLK_SYS_BUSCTRL (1) - // 0x00000004 [2] CLK_SYS_ADC0 (1) - // 0x00000002 [1] CLK_ADC_ADC0 (1) - // 0x00000001 [0] CLK_SYS_CLOCKS_BANK_DEFAULT (1) - io_rw_32 sleep_en0; - - _REG_(CLOCKS_SLEEP_EN1_OFFSET) // CLOCKS_SLEEP_EN1 - // enable clock in sleep mode - // 0x00004000 [14] CLK_SYS_XOSC (1) - // 0x00002000 [13] CLK_SYS_XIP (1) - // 0x00001000 [12] CLK_SYS_WATCHDOG (1) - // 0x00000800 [11] CLK_USB_USBCTRL (1) - // 0x00000400 [10] CLK_SYS_USBCTRL (1) - // 0x00000200 [9] CLK_SYS_UART1 (1) - // 0x00000100 [8] CLK_PERI_UART1 (1) - // 0x00000080 [7] CLK_SYS_UART0 (1) - // 0x00000040 [6] CLK_PERI_UART0 (1) - // 0x00000020 [5] CLK_SYS_TIMER (1) - // 0x00000010 [4] CLK_SYS_TBMAN (1) - // 0x00000008 [3] CLK_SYS_SYSINFO (1) - // 0x00000004 [2] CLK_SYS_SYSCFG (1) - // 0x00000002 [1] CLK_SYS_SRAM5 (1) - // 0x00000001 [0] CLK_SYS_SRAM4 (1) - io_rw_32 sleep_en1; - }; - // (Description copied from array index 0 register CLOCKS_SLEEP_EN0 applies similarly to other array indexes) - _REG_(CLOCKS_SLEEP_EN0_OFFSET) // CLOCKS_SLEEP_EN0 - // enable clock in sleep mode - // 0x80000000 [31] CLK_SYS_SRAM3 (1) - // 0x40000000 [30] CLK_SYS_SRAM2 (1) - // 0x20000000 [29] CLK_SYS_SRAM1 (1) - // 0x10000000 [28] CLK_SYS_SRAM0 (1) - // 0x08000000 [27] CLK_SYS_SPI1 (1) - // 0x04000000 [26] CLK_PERI_SPI1 (1) - // 0x02000000 [25] CLK_SYS_SPI0 (1) - // 0x01000000 [24] CLK_PERI_SPI0 (1) - // 0x00800000 [23] CLK_SYS_SIO (1) - // 0x00400000 [22] CLK_SYS_RTC (1) - // 0x00200000 [21] CLK_RTC_RTC (1) - // 0x00100000 [20] CLK_SYS_ROSC (1) - // 0x00080000 [19] CLK_SYS_ROM (1) - // 0x00040000 [18] CLK_SYS_RESETS (1) - // 0x00020000 [17] CLK_SYS_PWM (1) - // 0x00010000 [16] CLK_SYS_PSM (1) - // 0x00008000 [15] CLK_SYS_PLL_USB (1) - // 0x00004000 [14] CLK_SYS_PLL_SYS (1) - // 0x00002000 [13] CLK_SYS_PIO1 (1) - // 0x00001000 [12] CLK_SYS_PIO0 (1) - // 0x00000800 [11] CLK_SYS_PADS (1) - // 0x00000400 [10] CLK_SYS_VREG_AND_CHIP_RESET (1) - // 0x00000200 [9] CLK_SYS_JTAG (1) - // 0x00000100 [8] CLK_SYS_IO (1) - // 0x00000080 [7] CLK_SYS_I2C1 (1) - // 0x00000040 [6] CLK_SYS_I2C0 (1) - // 0x00000020 [5] CLK_SYS_DMA (1) - // 0x00000010 [4] CLK_SYS_BUSFABRIC (1) - // 0x00000008 [3] CLK_SYS_BUSCTRL (1) - // 0x00000004 [2] CLK_SYS_ADC (1) - // 0x00000002 [1] CLK_ADC_ADC (1) - // 0x00000001 [0] CLK_SYS_CLOCKS (1) - io_rw_32 sleep_en[2]; - }; - - union { - struct { - _REG_(CLOCKS_ENABLED0_OFFSET) // CLOCKS_ENABLED0 - // indicates the state of the clock enable - // 0x80000000 [31] CLK_SYS_SRAM3 (0) - // 0x40000000 [30] CLK_SYS_SRAM2 (0) - // 0x20000000 [29] CLK_SYS_SRAM1 (0) - // 0x10000000 [28] CLK_SYS_SRAM0 (0) - // 0x08000000 [27] CLK_SYS_SPI1 (0) - // 0x04000000 [26] CLK_PERI_SPI1 (0) - // 0x02000000 [25] CLK_SYS_SPI0 (0) - // 0x01000000 [24] CLK_PERI_SPI0 (0) - // 0x00800000 [23] CLK_SYS_SIOB (0) - // 0x00400000 [22] CLK_SYS_RTC (0) - // 0x00200000 [21] CLK_RTC_RTC (0) - // 0x00100000 [20] CLK_SYS_ROSC (0) - // 0x00080000 [19] CLK_SYS_ROM (0) - // 0x00040000 [18] CLK_SYS_RESETS (0) - // 0x00020000 [17] CLK_SYS_PWM (0) - // 0x00010000 [16] CLK_SYS_POWER (0) - // 0x00008000 [15] CLK_SYS_PLL_USB (0) - // 0x00004000 [14] CLK_SYS_PLL_SYS (0) - // 0x00002000 [13] CLK_SYS_PIO1 (0) - // 0x00001000 [12] CLK_SYS_PIO0 (0) - // 0x00000800 [11] CLK_SYS_PADS (0) - // 0x00000400 [10] CLK_SYS_LDO_POR (0) - // 0x00000200 [9] CLK_SYS_JTAG (0) - // 0x00000100 [8] CLK_SYS_IO (0) - // 0x00000080 [7] CLK_SYS_I2C1 (0) - // 0x00000040 [6] CLK_SYS_I2C0 (0) - // 0x00000020 [5] CLK_SYS_DMA (0) - // 0x00000010 [4] CLK_SYS_BUSFABRIC (0) - // 0x00000008 [3] CLK_SYS_BUSCTRL (0) - // 0x00000004 [2] CLK_SYS_ADC0 (0) - // 0x00000002 [1] CLK_ADC_ADC0 (0) - // 0x00000001 [0] CLK_SYS_CLOCKS_BANK_DEFAULT (0) - io_ro_32 enabled0; - - _REG_(CLOCKS_ENABLED1_OFFSET) // CLOCKS_ENABLED1 - // indicates the state of the clock enable - // 0x00004000 [14] CLK_SYS_XOSC (0) - // 0x00002000 [13] CLK_SYS_XIP (0) - // 0x00001000 [12] CLK_SYS_WATCHDOG (0) - // 0x00000800 [11] CLK_USB_USBCTRL (0) - // 0x00000400 [10] CLK_SYS_USBCTRL (0) - // 0x00000200 [9] CLK_SYS_UART1 (0) - // 0x00000100 [8] CLK_PERI_UART1 (0) - // 0x00000080 [7] CLK_SYS_UART0 (0) - // 0x00000040 [6] CLK_PERI_UART0 (0) - // 0x00000020 [5] CLK_SYS_TIMER (0) - // 0x00000010 [4] CLK_SYS_TBMAN (0) - // 0x00000008 [3] CLK_SYS_SYSINFO (0) - // 0x00000004 [2] CLK_SYS_SYSCFG (0) - // 0x00000002 [1] CLK_SYS_SRAM5 (0) - // 0x00000001 [0] CLK_SYS_SRAM4 (0) - io_ro_32 enabled1; - }; - // (Description copied from array index 0 register CLOCKS_ENABLED0 applies similarly to other array indexes) - _REG_(CLOCKS_ENABLED0_OFFSET) // CLOCKS_ENABLED0 - // indicates the state of the clock enable - // 0x80000000 [31] CLK_SYS_SRAM3 (0) - // 0x40000000 [30] CLK_SYS_SRAM2 (0) - // 0x20000000 [29] CLK_SYS_SRAM1 (0) - // 0x10000000 [28] CLK_SYS_SRAM0 (0) - // 0x08000000 [27] CLK_SYS_SPI1 (0) - // 0x04000000 [26] CLK_PERI_SPI1 (0) - // 0x02000000 [25] CLK_SYS_SPI0 (0) - // 0x01000000 [24] CLK_PERI_SPI0 (0) - // 0x00800000 [23] CLK_SYS_SIO (0) - // 0x00400000 [22] CLK_SYS_RTC (0) - // 0x00200000 [21] CLK_RTC_RTC (0) - // 0x00100000 [20] CLK_SYS_ROSC (0) - // 0x00080000 [19] CLK_SYS_ROM (0) - // 0x00040000 [18] CLK_SYS_RESETS (0) - // 0x00020000 [17] CLK_SYS_PWM (0) - // 0x00010000 [16] CLK_SYS_PSM (0) - // 0x00008000 [15] CLK_SYS_PLL_USB (0) - // 0x00004000 [14] CLK_SYS_PLL_SYS (0) - // 0x00002000 [13] CLK_SYS_PIO1 (0) - // 0x00001000 [12] CLK_SYS_PIO0 (0) - // 0x00000800 [11] CLK_SYS_PADS (0) - // 0x00000400 [10] CLK_SYS_VREG_AND_CHIP_RESET (0) - // 0x00000200 [9] CLK_SYS_JTAG (0) - // 0x00000100 [8] CLK_SYS_IO (0) - // 0x00000080 [7] CLK_SYS_I2C1 (0) - // 0x00000040 [6] CLK_SYS_I2C0 (0) - // 0x00000020 [5] CLK_SYS_DMA (0) - // 0x00000010 [4] CLK_SYS_BUSFABRIC (0) - // 0x00000008 [3] CLK_SYS_BUSCTRL (0) - // 0x00000004 [2] CLK_SYS_ADC (0) - // 0x00000002 [1] CLK_ADC_ADC (0) - // 0x00000001 [0] CLK_SYS_CLOCKS (0) - io_ro_32 enabled[2]; - }; - - _REG_(CLOCKS_INTR_OFFSET) // CLOCKS_INTR - // Raw Interrupts - // 0x00000001 [0] CLK_SYS_RESUS (0) - io_ro_32 intr; - - _REG_(CLOCKS_INTE_OFFSET) // CLOCKS_INTE - // Interrupt Enable - // 0x00000001 [0] CLK_SYS_RESUS (0) - io_rw_32 inte; - - _REG_(CLOCKS_INTF_OFFSET) // CLOCKS_INTF - // Interrupt Force - // 0x00000001 [0] CLK_SYS_RESUS (0) - io_rw_32 intf; - - _REG_(CLOCKS_INTS_OFFSET) // CLOCKS_INTS - // Interrupt status after masking & forcing - // 0x00000001 [0] CLK_SYS_RESUS (0) - io_ro_32 ints; -} clocks_hw_t; - -#define clocks_hw ((clocks_hw_t *)CLOCKS_BASE) -static_assert(sizeof (clocks_hw_t) == 0x00c8, ""); - -#endif // _HARDWARE_STRUCTS_CLOCKS_H - diff --git a/lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/dma.h b/lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/dma.h deleted file mode 100644 index bc83060f7b..0000000000 --- a/lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/dma.h +++ /dev/null @@ -1,239 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _HARDWARE_STRUCTS_DMA_H -#define _HARDWARE_STRUCTS_DMA_H - -/** - * \file rp2040/dma.h - */ - -#include "hardware/address_mapped.h" -#include "hardware/regs/dma.h" -#include "hardware/structs/dma_debug.h" - -// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_dma -// -// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) -// _REG_(x) will link to the corresponding register in hardware/regs/dma.h. -// -// Bit-field descriptions are of the form: -// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION - -typedef struct { - _REG_(DMA_CH0_READ_ADDR_OFFSET) // DMA_CH0_READ_ADDR - // DMA Channel 0 Read Address pointer - // 0xffffffff [31:0] CH0_READ_ADDR (0x00000000) This register updates automatically each time a read completes - io_rw_32 read_addr; - - _REG_(DMA_CH0_WRITE_ADDR_OFFSET) // DMA_CH0_WRITE_ADDR - // DMA Channel 0 Write Address pointer - // 0xffffffff [31:0] CH0_WRITE_ADDR (0x00000000) This register updates automatically each time a write completes - io_rw_32 write_addr; - - _REG_(DMA_CH0_TRANS_COUNT_OFFSET) // DMA_CH0_TRANS_COUNT - // DMA Channel 0 Transfer Count - // 0xffffffff [31:0] CH0_TRANS_COUNT (0x00000000) Program the number of bus transfers a channel will... - io_rw_32 transfer_count; - - _REG_(DMA_CH0_CTRL_TRIG_OFFSET) // DMA_CH0_CTRL_TRIG - // DMA Channel 0 Control and Status - // 0x80000000 [31] AHB_ERROR (0) Logical OR of the READ_ERROR and WRITE_ERROR flags - // 0x40000000 [30] READ_ERROR (0) If 1, the channel received a read bus error - // 0x20000000 [29] WRITE_ERROR (0) If 1, the channel received a write bus error - // 0x01000000 [24] BUSY (0) This flag goes high when the channel starts a new... - // 0x00800000 [23] SNIFF_EN (0) If 1, this channel's data transfers are visible to the... - // 0x00400000 [22] BSWAP (0) Apply byte-swap transformation to DMA data - // 0x00200000 [21] IRQ_QUIET (0) In QUIET mode, the channel does not generate IRQs at the... - // 0x001f8000 [20:15] TREQ_SEL (0x00) Select a Transfer Request signal - // 0x00007800 [14:11] CHAIN_TO (0x0) When this channel completes, it will trigger the channel... - // 0x00000400 [10] RING_SEL (0) Select whether RING_SIZE applies to read or write addresses - // 0x000003c0 [9:6] RING_SIZE (0x0) Size of address wrap region - // 0x00000020 [5] INCR_WRITE (0) If 1, the write address increments with each transfer - // 0x00000010 [4] INCR_READ (0) If 1, the read address increments with each transfer - // 0x0000000c [3:2] DATA_SIZE (0x0) Set the size of each bus transfer (byte/halfword/word) - // 0x00000002 [1] HIGH_PRIORITY (0) HIGH_PRIORITY gives a channel preferential treatment in... - // 0x00000001 [0] EN (0) DMA Channel Enable - io_rw_32 ctrl_trig; - - _REG_(DMA_CH0_AL1_CTRL_OFFSET) // DMA_CH0_AL1_CTRL - // Alias for channel 0 CTRL register - // 0xffffffff [31:0] CH0_AL1_CTRL (-) - io_rw_32 al1_ctrl; - - _REG_(DMA_CH0_AL1_READ_ADDR_OFFSET) // DMA_CH0_AL1_READ_ADDR - // Alias for channel 0 READ_ADDR register - // 0xffffffff [31:0] CH0_AL1_READ_ADDR (-) - io_rw_32 al1_read_addr; - - _REG_(DMA_CH0_AL1_WRITE_ADDR_OFFSET) // DMA_CH0_AL1_WRITE_ADDR - // Alias for channel 0 WRITE_ADDR register - // 0xffffffff [31:0] CH0_AL1_WRITE_ADDR (-) - io_rw_32 al1_write_addr; - - _REG_(DMA_CH0_AL1_TRANS_COUNT_TRIG_OFFSET) // DMA_CH0_AL1_TRANS_COUNT_TRIG - // Alias for channel 0 TRANS_COUNT register + - // 0xffffffff [31:0] CH0_AL1_TRANS_COUNT_TRIG (-) - io_rw_32 al1_transfer_count_trig; - - _REG_(DMA_CH0_AL2_CTRL_OFFSET) // DMA_CH0_AL2_CTRL - // Alias for channel 0 CTRL register - // 0xffffffff [31:0] CH0_AL2_CTRL (-) - io_rw_32 al2_ctrl; - - _REG_(DMA_CH0_AL2_TRANS_COUNT_OFFSET) // DMA_CH0_AL2_TRANS_COUNT - // Alias for channel 0 TRANS_COUNT register - // 0xffffffff [31:0] CH0_AL2_TRANS_COUNT (-) - io_rw_32 al2_transfer_count; - - _REG_(DMA_CH0_AL2_READ_ADDR_OFFSET) // DMA_CH0_AL2_READ_ADDR - // Alias for channel 0 READ_ADDR register - // 0xffffffff [31:0] CH0_AL2_READ_ADDR (-) - io_rw_32 al2_read_addr; - - _REG_(DMA_CH0_AL2_WRITE_ADDR_TRIG_OFFSET) // DMA_CH0_AL2_WRITE_ADDR_TRIG - // Alias for channel 0 WRITE_ADDR register + - // 0xffffffff [31:0] CH0_AL2_WRITE_ADDR_TRIG (-) - io_rw_32 al2_write_addr_trig; - - _REG_(DMA_CH0_AL3_CTRL_OFFSET) // DMA_CH0_AL3_CTRL - // Alias for channel 0 CTRL register - // 0xffffffff [31:0] CH0_AL3_CTRL (-) - io_rw_32 al3_ctrl; - - _REG_(DMA_CH0_AL3_WRITE_ADDR_OFFSET) // DMA_CH0_AL3_WRITE_ADDR - // Alias for channel 0 WRITE_ADDR register - // 0xffffffff [31:0] CH0_AL3_WRITE_ADDR (-) - io_rw_32 al3_write_addr; - - _REG_(DMA_CH0_AL3_TRANS_COUNT_OFFSET) // DMA_CH0_AL3_TRANS_COUNT - // Alias for channel 0 TRANS_COUNT register - // 0xffffffff [31:0] CH0_AL3_TRANS_COUNT (-) - io_rw_32 al3_transfer_count; - - _REG_(DMA_CH0_AL3_READ_ADDR_TRIG_OFFSET) // DMA_CH0_AL3_READ_ADDR_TRIG - // Alias for channel 0 READ_ADDR register + - // 0xffffffff [31:0] CH0_AL3_READ_ADDR_TRIG (-) - io_rw_32 al3_read_addr_trig; -} dma_channel_hw_t; - -typedef struct { - _REG_(DMA_INTR_OFFSET) // DMA_INTR - // Interrupt Status (raw) - // 0x0000ffff [15:0] INTR (0x0000) Raw interrupt status for DMA Channels 0 - io_rw_32 intr; - - _REG_(DMA_INTE0_OFFSET) // DMA_INTE0 - // Interrupt Enables for IRQ 0 - // 0x0000ffff [15:0] INTE0 (0x0000) Set bit n to pass interrupts from channel n to DMA IRQ 0 - io_rw_32 inte; - - _REG_(DMA_INTF0_OFFSET) // DMA_INTF0 - // Force Interrupts - // 0x0000ffff [15:0] INTF0 (0x0000) Write 1s to force the corresponding bits in INTE0 - io_rw_32 intf; - - _REG_(DMA_INTS0_OFFSET) // DMA_INTS0 - // Interrupt Status for IRQ 0 - // 0x0000ffff [15:0] INTS0 (0x0000) Indicates active channel interrupt requests which are... - io_rw_32 ints; -} dma_irq_ctrl_hw_t; - -typedef struct { - dma_channel_hw_t ch[12]; - - uint32_t _pad0[64]; - - union { - struct { - _REG_(DMA_INTR_OFFSET) // DMA_INTR - // Interrupt Status (raw) - // 0x0000ffff [15:0] INTR (0x0000) Raw interrupt status for DMA Channels 0 - io_rw_32 intr; - - _REG_(DMA_INTE0_OFFSET) // DMA_INTE0 - // Interrupt Enables for IRQ 0 - // 0x0000ffff [15:0] INTE0 (0x0000) Set bit n to pass interrupts from channel n to DMA IRQ 0 - io_rw_32 inte0; - - _REG_(DMA_INTF0_OFFSET) // DMA_INTF0 - // Force Interrupts - // 0x0000ffff [15:0] INTF0 (0x0000) Write 1s to force the corresponding bits in INTE0 - io_rw_32 intf0; - - _REG_(DMA_INTS0_OFFSET) // DMA_INTS0 - // Interrupt Status for IRQ 0 - // 0x0000ffff [15:0] INTS0 (0x0000) Indicates active channel interrupt requests which are... - io_rw_32 ints0; - - uint32_t __pad0; - - _REG_(DMA_INTE1_OFFSET) // DMA_INTE1 - // Interrupt Enables for IRQ 1 - // 0x0000ffff [15:0] INTE1 (0x0000) Set bit n to pass interrupts from channel n to DMA IRQ 1 - io_rw_32 inte1; - - _REG_(DMA_INTF1_OFFSET) // DMA_INTF1 - // Force Interrupts for IRQ 1 - // 0x0000ffff [15:0] INTF1 (0x0000) Write 1s to force the corresponding bits in INTF1 - io_rw_32 intf1; - - _REG_(DMA_INTS1_OFFSET) // DMA_INTS1 - // Interrupt Status (masked) for IRQ 1 - // 0x0000ffff [15:0] INTS1 (0x0000) Indicates active channel interrupt requests which are... - io_rw_32 ints1; - }; - dma_irq_ctrl_hw_t irq_ctrl[2]; - }; - - // (Description copied from array index 0 register DMA_TIMER0 applies similarly to other array indexes) - _REG_(DMA_TIMER0_OFFSET) // DMA_TIMER0 - // Pacing (X/Y) Fractional Timer + - // 0xffff0000 [31:16] X (0x0000) Pacing Timer Dividend - // 0x0000ffff [15:0] Y (0x0000) Pacing Timer Divisor - io_rw_32 timer[4]; - - _REG_(DMA_MULTI_CHAN_TRIGGER_OFFSET) // DMA_MULTI_CHAN_TRIGGER - // Trigger one or more channels simultaneously - // 0x0000ffff [15:0] MULTI_CHAN_TRIGGER (0x0000) Each bit in this register corresponds to a DMA channel - io_wo_32 multi_channel_trigger; - - _REG_(DMA_SNIFF_CTRL_OFFSET) // DMA_SNIFF_CTRL - // Sniffer Control - // 0x00000800 [11] OUT_INV (0) If set, the result appears inverted (bitwise complement)... - // 0x00000400 [10] OUT_REV (0) If set, the result appears bit-reversed when read - // 0x00000200 [9] BSWAP (0) Locally perform a byte reverse on the sniffed data,... - // 0x000001e0 [8:5] CALC (0x0) - // 0x0000001e [4:1] DMACH (0x0) DMA channel for Sniffer to observe - // 0x00000001 [0] EN (0) Enable sniffer - io_rw_32 sniff_ctrl; - - _REG_(DMA_SNIFF_DATA_OFFSET) // DMA_SNIFF_DATA - // Data accumulator for sniff hardware - // 0xffffffff [31:0] SNIFF_DATA (0x00000000) Write an initial seed value here before starting a DMA... - io_rw_32 sniff_data; - - uint32_t _pad1; - - _REG_(DMA_FIFO_LEVELS_OFFSET) // DMA_FIFO_LEVELS - // Debug RAF, WAF, TDF levels - // 0x00ff0000 [23:16] RAF_LVL (0x00) Current Read-Address-FIFO fill level - // 0x0000ff00 [15:8] WAF_LVL (0x00) Current Write-Address-FIFO fill level - // 0x000000ff [7:0] TDF_LVL (0x00) Current Transfer-Data-FIFO fill level - io_ro_32 fifo_levels; - - _REG_(DMA_CHAN_ABORT_OFFSET) // DMA_CHAN_ABORT - // Abort an in-progress transfer sequence on one or more channels - // 0x0000ffff [15:0] CHAN_ABORT (0x0000) Each bit corresponds to a channel - io_wo_32 abort; -} dma_hw_t; - -#define dma_hw ((dma_hw_t *)DMA_BASE) -static_assert(sizeof (dma_hw_t) == 0x0448, ""); - -#endif // _HARDWARE_STRUCTS_DMA_H - diff --git a/lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/dma_debug.h b/lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/dma_debug.h deleted file mode 100644 index 239b8cae86..0000000000 --- a/lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/dma_debug.h +++ /dev/null @@ -1,47 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _HARDWARE_STRUCTS_DMA_DEBUG_H -#define _HARDWARE_STRUCTS_DMA_DEBUG_H - -/** - * \file rp2040/dma_debug.h - */ - -#include "hardware/address_mapped.h" -#include "hardware/regs/dma.h" - -// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_dma -// -// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) -// _REG_(x) will link to the corresponding register in hardware/regs/dma.h. -// -// Bit-field descriptions are of the form: -// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION - -typedef struct { - _REG_(DMA_CH0_DBG_CTDREQ_OFFSET) // DMA_CH0_DBG_CTDREQ - // Read: get channel DREQ counter (i - // 0x0000003f [5:0] CH0_DBG_CTDREQ (0x00) - io_rw_32 dbg_ctdreq; - - _REG_(DMA_CH0_DBG_TCR_OFFSET) // DMA_CH0_DBG_TCR - // Read to get channel TRANS_COUNT reload value, i - // 0xffffffff [31:0] CH0_DBG_TCR (0x00000000) - io_ro_32 dbg_tcr; - - uint32_t _pad0[14]; -} dma_debug_channel_hw_t; - -typedef struct { - dma_debug_channel_hw_t ch[12]; -} dma_debug_hw_t; - -#define dma_debug_hw ((dma_debug_hw_t *)(DMA_BASE + DMA_CH0_DBG_CTDREQ_OFFSET)) - -#endif // _HARDWARE_STRUCTS_DMA_DEBUG_H - diff --git a/lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/i2c.h b/lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/i2c.h deleted file mode 100644 index 2ff0997995..0000000000 --- a/lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/i2c.h +++ /dev/null @@ -1,338 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _HARDWARE_STRUCTS_I2C_H -#define _HARDWARE_STRUCTS_I2C_H - -/** - * \file rp2040/i2c.h - */ - -#include "hardware/address_mapped.h" -#include "hardware/regs/i2c.h" - -// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_i2c -// -// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) -// _REG_(x) will link to the corresponding register in hardware/regs/i2c.h. -// -// Bit-field descriptions are of the form: -// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION - -typedef struct { - _REG_(I2C_IC_CON_OFFSET) // I2C_IC_CON - // I2C Control Register - // 0x00000400 [10] STOP_DET_IF_MASTER_ACTIVE (0) Master issues the STOP_DET interrupt irrespective of... - // 0x00000200 [9] RX_FIFO_FULL_HLD_CTRL (0) This bit controls whether DW_apb_i2c should hold the bus... - // 0x00000100 [8] TX_EMPTY_CTRL (0) This bit controls the generation of the TX_EMPTY... - // 0x00000080 [7] STOP_DET_IFADDRESSED (0) In slave mode: - 1'b1: issues the STOP_DET interrupt... - // 0x00000040 [6] IC_SLAVE_DISABLE (1) This bit controls whether I2C has its slave disabled,... - // 0x00000020 [5] IC_RESTART_EN (1) Determines whether RESTART conditions may be sent when... - // 0x00000010 [4] IC_10BITADDR_MASTER (0) Controls whether the DW_apb_i2c starts its transfers in... - // 0x00000008 [3] IC_10BITADDR_SLAVE (0) When acting as a slave, this bit controls whether the... - // 0x00000006 [2:1] SPEED (0x2) These bits control at which speed the DW_apb_i2c... - // 0x00000001 [0] MASTER_MODE (1) This bit controls whether the DW_apb_i2c master is enabled - io_rw_32 con; - - _REG_(I2C_IC_TAR_OFFSET) // I2C_IC_TAR - // I2C Target Address Register - // 0x00000800 [11] SPECIAL (0) This bit indicates whether software performs a Device-ID... - // 0x00000400 [10] GC_OR_START (0) If bit 11 (SPECIAL) is set to 1 and bit 13(Device-ID) is... - // 0x000003ff [9:0] IC_TAR (0x055) This is the target address for any master transaction - io_rw_32 tar; - - _REG_(I2C_IC_SAR_OFFSET) // I2C_IC_SAR - // I2C Slave Address Register - // 0x000003ff [9:0] IC_SAR (0x055) The IC_SAR holds the slave address when the I2C is... - io_rw_32 sar; - - uint32_t _pad0; - - _REG_(I2C_IC_DATA_CMD_OFFSET) // I2C_IC_DATA_CMD - // I2C Rx/Tx Data Buffer and Command Register - // 0x00000800 [11] FIRST_DATA_BYTE (0) Indicates the first data byte received after the address... - // 0x00000400 [10] RESTART (0) This bit controls whether a RESTART is issued before the... - // 0x00000200 [9] STOP (0) This bit controls whether a STOP is issued after the... - // 0x00000100 [8] CMD (0) This bit controls whether a read or a write is performed - // 0x000000ff [7:0] DAT (0x00) This register contains the data to be transmitted or... - io_rw_32 data_cmd; - - _REG_(I2C_IC_SS_SCL_HCNT_OFFSET) // I2C_IC_SS_SCL_HCNT - // Standard Speed I2C Clock SCL High Count Register - // 0x0000ffff [15:0] IC_SS_SCL_HCNT (0x0028) This register must be set before any I2C bus transaction... - io_rw_32 ss_scl_hcnt; - - _REG_(I2C_IC_SS_SCL_LCNT_OFFSET) // I2C_IC_SS_SCL_LCNT - // Standard Speed I2C Clock SCL Low Count Register - // 0x0000ffff [15:0] IC_SS_SCL_LCNT (0x002f) This register must be set before any I2C bus transaction... - io_rw_32 ss_scl_lcnt; - - _REG_(I2C_IC_FS_SCL_HCNT_OFFSET) // I2C_IC_FS_SCL_HCNT - // Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register - // 0x0000ffff [15:0] IC_FS_SCL_HCNT (0x0006) This register must be set before any I2C bus transaction... - io_rw_32 fs_scl_hcnt; - - _REG_(I2C_IC_FS_SCL_LCNT_OFFSET) // I2C_IC_FS_SCL_LCNT - // Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register - // 0x0000ffff [15:0] IC_FS_SCL_LCNT (0x000d) This register must be set before any I2C bus transaction... - io_rw_32 fs_scl_lcnt; - - uint32_t _pad1[2]; - - _REG_(I2C_IC_INTR_STAT_OFFSET) // I2C_IC_INTR_STAT - // I2C Interrupt Status Register - // 0x00001000 [12] R_RESTART_DET (0) See IC_RAW_INTR_STAT for a detailed description of... - // 0x00000800 [11] R_GEN_CALL (0) See IC_RAW_INTR_STAT for a detailed description of R_GEN_CALL bit - // 0x00000400 [10] R_START_DET (0) See IC_RAW_INTR_STAT for a detailed description of... - // 0x00000200 [9] R_STOP_DET (0) See IC_RAW_INTR_STAT for a detailed description of R_STOP_DET bit - // 0x00000100 [8] R_ACTIVITY (0) See IC_RAW_INTR_STAT for a detailed description of R_ACTIVITY bit - // 0x00000080 [7] R_RX_DONE (0) See IC_RAW_INTR_STAT for a detailed description of R_RX_DONE bit - // 0x00000040 [6] R_TX_ABRT (0) See IC_RAW_INTR_STAT for a detailed description of R_TX_ABRT bit - // 0x00000020 [5] R_RD_REQ (0) See IC_RAW_INTR_STAT for a detailed description of R_RD_REQ bit - // 0x00000010 [4] R_TX_EMPTY (0) See IC_RAW_INTR_STAT for a detailed description of R_TX_EMPTY bit - // 0x00000008 [3] R_TX_OVER (0) See IC_RAW_INTR_STAT for a detailed description of R_TX_OVER bit - // 0x00000004 [2] R_RX_FULL (0) See IC_RAW_INTR_STAT for a detailed description of R_RX_FULL bit - // 0x00000002 [1] R_RX_OVER (0) See IC_RAW_INTR_STAT for a detailed description of R_RX_OVER bit - // 0x00000001 [0] R_RX_UNDER (0) See IC_RAW_INTR_STAT for a detailed description of R_RX_UNDER bit - io_ro_32 intr_stat; - - _REG_(I2C_IC_INTR_MASK_OFFSET) // I2C_IC_INTR_MASK - // I2C Interrupt Mask Register - // 0x00001000 [12] M_RESTART_DET (0) This bit masks the R_RESTART_DET interrupt in... - // 0x00000800 [11] M_GEN_CALL (1) This bit masks the R_GEN_CALL interrupt in IC_INTR_STAT register - // 0x00000400 [10] M_START_DET (0) This bit masks the R_START_DET interrupt in IC_INTR_STAT register - // 0x00000200 [9] M_STOP_DET (0) This bit masks the R_STOP_DET interrupt in IC_INTR_STAT register - // 0x00000100 [8] M_ACTIVITY (0) This bit masks the R_ACTIVITY interrupt in IC_INTR_STAT register - // 0x00000080 [7] M_RX_DONE (1) This bit masks the R_RX_DONE interrupt in IC_INTR_STAT register - // 0x00000040 [6] M_TX_ABRT (1) This bit masks the R_TX_ABRT interrupt in IC_INTR_STAT register - // 0x00000020 [5] M_RD_REQ (1) This bit masks the R_RD_REQ interrupt in IC_INTR_STAT register - // 0x00000010 [4] M_TX_EMPTY (1) This bit masks the R_TX_EMPTY interrupt in IC_INTR_STAT register - // 0x00000008 [3] M_TX_OVER (1) This bit masks the R_TX_OVER interrupt in IC_INTR_STAT register - // 0x00000004 [2] M_RX_FULL (1) This bit masks the R_RX_FULL interrupt in IC_INTR_STAT register - // 0x00000002 [1] M_RX_OVER (1) This bit masks the R_RX_OVER interrupt in IC_INTR_STAT register - // 0x00000001 [0] M_RX_UNDER (1) This bit masks the R_RX_UNDER interrupt in IC_INTR_STAT register - io_rw_32 intr_mask; - - _REG_(I2C_IC_RAW_INTR_STAT_OFFSET) // I2C_IC_RAW_INTR_STAT - // I2C Raw Interrupt Status Register - // 0x00001000 [12] RESTART_DET (0) Indicates whether a RESTART condition has occurred on... - // 0x00000800 [11] GEN_CALL (0) Set only when a General Call address is received and it... - // 0x00000400 [10] START_DET (0) Indicates whether a START or RESTART condition has... - // 0x00000200 [9] STOP_DET (0) Indicates whether a STOP condition has occurred on the... - // 0x00000100 [8] ACTIVITY (0) This bit captures DW_apb_i2c activity and stays set... - // 0x00000080 [7] RX_DONE (0) When the DW_apb_i2c is acting as a slave-transmitter,... - // 0x00000040 [6] TX_ABRT (0) This bit indicates if DW_apb_i2c, as an I2C transmitter,... - // 0x00000020 [5] RD_REQ (0) This bit is set to 1 when DW_apb_i2c is acting as a... - // 0x00000010 [4] TX_EMPTY (0) The behavior of the TX_EMPTY interrupt status differs... - // 0x00000008 [3] TX_OVER (0) Set during transmit if the transmit buffer is filled to... - // 0x00000004 [2] RX_FULL (0) Set when the receive buffer reaches or goes above the... - // 0x00000002 [1] RX_OVER (0) Set if the receive buffer is completely filled to... - // 0x00000001 [0] RX_UNDER (0) Set if the processor attempts to read the receive buffer... - io_ro_32 raw_intr_stat; - - _REG_(I2C_IC_RX_TL_OFFSET) // I2C_IC_RX_TL - // I2C Receive FIFO Threshold Register - // 0x000000ff [7:0] RX_TL (0x00) Receive FIFO Threshold Level - io_rw_32 rx_tl; - - _REG_(I2C_IC_TX_TL_OFFSET) // I2C_IC_TX_TL - // I2C Transmit FIFO Threshold Register - // 0x000000ff [7:0] TX_TL (0x00) Transmit FIFO Threshold Level - io_rw_32 tx_tl; - - _REG_(I2C_IC_CLR_INTR_OFFSET) // I2C_IC_CLR_INTR - // Clear Combined and Individual Interrupt Register - // 0x00000001 [0] CLR_INTR (0) Read this register to clear the combined interrupt, all... - io_ro_32 clr_intr; - - _REG_(I2C_IC_CLR_RX_UNDER_OFFSET) // I2C_IC_CLR_RX_UNDER - // Clear RX_UNDER Interrupt Register - // 0x00000001 [0] CLR_RX_UNDER (0) Read this register to clear the RX_UNDER interrupt (bit... - io_ro_32 clr_rx_under; - - _REG_(I2C_IC_CLR_RX_OVER_OFFSET) // I2C_IC_CLR_RX_OVER - // Clear RX_OVER Interrupt Register - // 0x00000001 [0] CLR_RX_OVER (0) Read this register to clear the RX_OVER interrupt (bit... - io_ro_32 clr_rx_over; - - _REG_(I2C_IC_CLR_TX_OVER_OFFSET) // I2C_IC_CLR_TX_OVER - // Clear TX_OVER Interrupt Register - // 0x00000001 [0] CLR_TX_OVER (0) Read this register to clear the TX_OVER interrupt (bit... - io_ro_32 clr_tx_over; - - _REG_(I2C_IC_CLR_RD_REQ_OFFSET) // I2C_IC_CLR_RD_REQ - // Clear RD_REQ Interrupt Register - // 0x00000001 [0] CLR_RD_REQ (0) Read this register to clear the RD_REQ interrupt (bit 5)... - io_ro_32 clr_rd_req; - - _REG_(I2C_IC_CLR_TX_ABRT_OFFSET) // I2C_IC_CLR_TX_ABRT - // Clear TX_ABRT Interrupt Register - // 0x00000001 [0] CLR_TX_ABRT (0) Read this register to clear the TX_ABRT interrupt (bit... - io_ro_32 clr_tx_abrt; - - _REG_(I2C_IC_CLR_RX_DONE_OFFSET) // I2C_IC_CLR_RX_DONE - // Clear RX_DONE Interrupt Register - // 0x00000001 [0] CLR_RX_DONE (0) Read this register to clear the RX_DONE interrupt (bit... - io_ro_32 clr_rx_done; - - _REG_(I2C_IC_CLR_ACTIVITY_OFFSET) // I2C_IC_CLR_ACTIVITY - // Clear ACTIVITY Interrupt Register - // 0x00000001 [0] CLR_ACTIVITY (0) Reading this register clears the ACTIVITY interrupt if... - io_ro_32 clr_activity; - - _REG_(I2C_IC_CLR_STOP_DET_OFFSET) // I2C_IC_CLR_STOP_DET - // Clear STOP_DET Interrupt Register - // 0x00000001 [0] CLR_STOP_DET (0) Read this register to clear the STOP_DET interrupt (bit... - io_ro_32 clr_stop_det; - - _REG_(I2C_IC_CLR_START_DET_OFFSET) // I2C_IC_CLR_START_DET - // Clear START_DET Interrupt Register - // 0x00000001 [0] CLR_START_DET (0) Read this register to clear the START_DET interrupt (bit... - io_ro_32 clr_start_det; - - _REG_(I2C_IC_CLR_GEN_CALL_OFFSET) // I2C_IC_CLR_GEN_CALL - // Clear GEN_CALL Interrupt Register - // 0x00000001 [0] CLR_GEN_CALL (0) Read this register to clear the GEN_CALL interrupt (bit... - io_ro_32 clr_gen_call; - - _REG_(I2C_IC_ENABLE_OFFSET) // I2C_IC_ENABLE - // I2C ENABLE Register - // 0x00000004 [2] TX_CMD_BLOCK (0) In Master mode: - 1'b1: Blocks the transmission of data... - // 0x00000002 [1] ABORT (0) When set, the controller initiates the transfer abort - // 0x00000001 [0] ENABLE (0) Controls whether the DW_apb_i2c is enabled - io_rw_32 enable; - - _REG_(I2C_IC_STATUS_OFFSET) // I2C_IC_STATUS - // I2C STATUS Register - // 0x00000040 [6] SLV_ACTIVITY (0) Slave FSM Activity Status - // 0x00000020 [5] MST_ACTIVITY (0) Master FSM Activity Status - // 0x00000010 [4] RFF (0) Receive FIFO Completely Full - // 0x00000008 [3] RFNE (0) Receive FIFO Not Empty - // 0x00000004 [2] TFE (1) Transmit FIFO Completely Empty - // 0x00000002 [1] TFNF (1) Transmit FIFO Not Full - // 0x00000001 [0] ACTIVITY (0) I2C Activity Status - io_ro_32 status; - - _REG_(I2C_IC_TXFLR_OFFSET) // I2C_IC_TXFLR - // I2C Transmit FIFO Level Register - // 0x0000001f [4:0] TXFLR (0x00) Transmit FIFO Level - io_ro_32 txflr; - - _REG_(I2C_IC_RXFLR_OFFSET) // I2C_IC_RXFLR - // I2C Receive FIFO Level Register - // 0x0000001f [4:0] RXFLR (0x00) Receive FIFO Level - io_ro_32 rxflr; - - _REG_(I2C_IC_SDA_HOLD_OFFSET) // I2C_IC_SDA_HOLD - // I2C SDA Hold Time Length Register - // 0x00ff0000 [23:16] IC_SDA_RX_HOLD (0x00) Sets the required SDA hold time in units of ic_clk... - // 0x0000ffff [15:0] IC_SDA_TX_HOLD (0x0001) Sets the required SDA hold time in units of ic_clk... - io_rw_32 sda_hold; - - _REG_(I2C_IC_TX_ABRT_SOURCE_OFFSET) // I2C_IC_TX_ABRT_SOURCE - // I2C Transmit Abort Source Register - // 0xff800000 [31:23] TX_FLUSH_CNT (0x000) This field indicates the number of Tx FIFO Data Commands... - // 0x00010000 [16] ABRT_USER_ABRT (0) This is a master-mode-only bit - // 0x00008000 [15] ABRT_SLVRD_INTX (0) 1: When the processor side responds to a slave mode... - // 0x00004000 [14] ABRT_SLV_ARBLOST (0) This field indicates that a Slave has lost the bus while... - // 0x00002000 [13] ABRT_SLVFLUSH_TXFIFO (0) This field specifies that the Slave has received a read... - // 0x00001000 [12] ARB_LOST (0) This field specifies that the Master has lost... - // 0x00000800 [11] ABRT_MASTER_DIS (0) This field indicates that the User tries to initiate a... - // 0x00000400 [10] ABRT_10B_RD_NORSTRT (0) This field indicates that the restart is disabled... - // 0x00000200 [9] ABRT_SBYTE_NORSTRT (0) To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT... - // 0x00000100 [8] ABRT_HS_NORSTRT (0) This field indicates that the restart is disabled... - // 0x00000080 [7] ABRT_SBYTE_ACKDET (0) This field indicates that the Master has sent a START... - // 0x00000040 [6] ABRT_HS_ACKDET (0) This field indicates that the Master is in High Speed... - // 0x00000020 [5] ABRT_GCALL_READ (0) This field indicates that DW_apb_i2c in the master mode... - // 0x00000010 [4] ABRT_GCALL_NOACK (0) This field indicates that DW_apb_i2c in master mode has... - // 0x00000008 [3] ABRT_TXDATA_NOACK (0) This field indicates the master-mode only bit - // 0x00000004 [2] ABRT_10ADDR2_NOACK (0) This field indicates that the Master is in 10-bit... - // 0x00000002 [1] ABRT_10ADDR1_NOACK (0) This field indicates that the Master is in 10-bit... - // 0x00000001 [0] ABRT_7B_ADDR_NOACK (0) This field indicates that the Master is in 7-bit... - io_ro_32 tx_abrt_source; - - _REG_(I2C_IC_SLV_DATA_NACK_ONLY_OFFSET) // I2C_IC_SLV_DATA_NACK_ONLY - // Generate Slave Data NACK Register - // 0x00000001 [0] NACK (0) Generate NACK - io_rw_32 slv_data_nack_only; - - _REG_(I2C_IC_DMA_CR_OFFSET) // I2C_IC_DMA_CR - // DMA Control Register - // 0x00000002 [1] TDMAE (0) Transmit DMA Enable - // 0x00000001 [0] RDMAE (0) Receive DMA Enable - io_rw_32 dma_cr; - - _REG_(I2C_IC_DMA_TDLR_OFFSET) // I2C_IC_DMA_TDLR - // DMA Transmit Data Level Register - // 0x0000000f [3:0] DMATDL (0x0) Transmit Data Level - io_rw_32 dma_tdlr; - - _REG_(I2C_IC_DMA_RDLR_OFFSET) // I2C_IC_DMA_RDLR - // DMA Transmit Data Level Register - // 0x0000000f [3:0] DMARDL (0x0) Receive Data Level - io_rw_32 dma_rdlr; - - _REG_(I2C_IC_SDA_SETUP_OFFSET) // I2C_IC_SDA_SETUP - // I2C SDA Setup Register - // 0x000000ff [7:0] SDA_SETUP (0x64) SDA Setup - io_rw_32 sda_setup; - - _REG_(I2C_IC_ACK_GENERAL_CALL_OFFSET) // I2C_IC_ACK_GENERAL_CALL - // I2C ACK General Call Register - // 0x00000001 [0] ACK_GEN_CALL (1) ACK General Call - io_rw_32 ack_general_call; - - _REG_(I2C_IC_ENABLE_STATUS_OFFSET) // I2C_IC_ENABLE_STATUS - // I2C Enable Status Register - // 0x00000004 [2] SLV_RX_DATA_LOST (0) Slave Received Data Lost - // 0x00000002 [1] SLV_DISABLED_WHILE_BUSY (0) Slave Disabled While Busy (Transmit, Receive) - // 0x00000001 [0] IC_EN (0) ic_en Status - io_ro_32 enable_status; - - _REG_(I2C_IC_FS_SPKLEN_OFFSET) // I2C_IC_FS_SPKLEN - // I2C SS, FS or FM+ spike suppression limit - // 0x000000ff [7:0] IC_FS_SPKLEN (0x07) This register must be set before any I2C bus transaction... - io_rw_32 fs_spklen; - - uint32_t _pad2; - - _REG_(I2C_IC_CLR_RESTART_DET_OFFSET) // I2C_IC_CLR_RESTART_DET - // Clear RESTART_DET Interrupt Register - // 0x00000001 [0] CLR_RESTART_DET (0) Read this register to clear the RESTART_DET interrupt... - io_ro_32 clr_restart_det; - - uint32_t _pad3[18]; - - _REG_(I2C_IC_COMP_PARAM_1_OFFSET) // I2C_IC_COMP_PARAM_1 - // Component Parameter Register 1 - // 0x00ff0000 [23:16] TX_BUFFER_DEPTH (0x00) TX Buffer Depth = 16 - // 0x0000ff00 [15:8] RX_BUFFER_DEPTH (0x00) RX Buffer Depth = 16 - // 0x00000080 [7] ADD_ENCODED_PARAMS (0) Encoded parameters not visible - // 0x00000040 [6] HAS_DMA (0) DMA handshaking signals are enabled - // 0x00000020 [5] INTR_IO (0) COMBINED Interrupt outputs - // 0x00000010 [4] HC_COUNT_VALUES (0) Programmable count values for each mode - // 0x0000000c [3:2] MAX_SPEED_MODE (0x0) MAX SPEED MODE = FAST MODE - // 0x00000003 [1:0] APB_DATA_WIDTH (0x0) APB data bus width is 32 bits - io_ro_32 comp_param_1; - - _REG_(I2C_IC_COMP_VERSION_OFFSET) // I2C_IC_COMP_VERSION - // I2C Component Version Register - // 0xffffffff [31:0] IC_COMP_VERSION (0x3230312a) - io_ro_32 comp_version; - - _REG_(I2C_IC_COMP_TYPE_OFFSET) // I2C_IC_COMP_TYPE - // I2C Component Type Register - // 0xffffffff [31:0] IC_COMP_TYPE (0x44570140) Designware Component Type number = 0x44_57_01_40 - io_ro_32 comp_type; -} i2c_hw_t; - -#define i2c0_hw ((i2c_hw_t *)I2C0_BASE) -#define i2c1_hw ((i2c_hw_t *)I2C1_BASE) -static_assert(sizeof (i2c_hw_t) == 0x0100, ""); - -#endif // _HARDWARE_STRUCTS_I2C_H - diff --git a/lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/interp.h b/lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/interp.h deleted file mode 100644 index abc06843a3..0000000000 --- a/lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/interp.h +++ /dev/null @@ -1,86 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _HARDWARE_STRUCTS_INTERP_H -#define _HARDWARE_STRUCTS_INTERP_H - -/** - * \file rp2040/interp.h - */ - -#include "hardware/address_mapped.h" -#include "hardware/regs/sio.h" - -// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_sio -// -// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) -// _REG_(x) will link to the corresponding register in hardware/regs/sio.h. -// -// Bit-field descriptions are of the form: -// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION - -typedef struct { - // (Description copied from array index 0 register SIO_INTERP0_ACCUM0 applies similarly to other array indexes) - _REG_(SIO_INTERP0_ACCUM0_OFFSET) // SIO_INTERP0_ACCUM0 - // Read/write access to accumulator 0 - // 0xffffffff [31:0] INTERP0_ACCUM0 (0x00000000) - io_rw_32 accum[2]; - - // (Description copied from array index 0 register SIO_INTERP0_BASE0 applies similarly to other array indexes) - _REG_(SIO_INTERP0_BASE0_OFFSET) // SIO_INTERP0_BASE0 - // Read/write access to BASE0 register - // 0xffffffff [31:0] INTERP0_BASE0 (0x00000000) - io_rw_32 base[3]; - - // (Description copied from array index 0 register SIO_INTERP0_POP_LANE0 applies similarly to other array indexes) - _REG_(SIO_INTERP0_POP_LANE0_OFFSET) // SIO_INTERP0_POP_LANE0 - // Read LANE0 result, and simultaneously write lane results to both accumulators (POP) - // 0xffffffff [31:0] INTERP0_POP_LANE0 (0x00000000) - io_ro_32 pop[3]; - - // (Description copied from array index 0 register SIO_INTERP0_PEEK_LANE0 applies similarly to other array indexes) - _REG_(SIO_INTERP0_PEEK_LANE0_OFFSET) // SIO_INTERP0_PEEK_LANE0 - // Read LANE0 result, without altering any internal state (PEEK) - // 0xffffffff [31:0] INTERP0_PEEK_LANE0 (0x00000000) - io_ro_32 peek[3]; - - // (Description copied from array index 0 register SIO_INTERP0_CTRL_LANE0 applies similarly to other array indexes) - _REG_(SIO_INTERP0_CTRL_LANE0_OFFSET) // SIO_INTERP0_CTRL_LANE0 - // Control register for lane 0 - // 0x02000000 [25] OVERF (0) Set if either OVERF0 or OVERF1 is set - // 0x01000000 [24] OVERF1 (0) Indicates if any masked-off MSBs in ACCUM1 are set - // 0x00800000 [23] OVERF0 (0) Indicates if any masked-off MSBs in ACCUM0 are set - // 0x00200000 [21] BLEND (0) Only present on INTERP0 on each core - // 0x00180000 [20:19] FORCE_MSB (0x0) ORed into bits 29:28 of the lane result presented to the... - // 0x00040000 [18] ADD_RAW (0) If 1, mask + shift is bypassed for LANE0 result - // 0x00020000 [17] CROSS_RESULT (0) If 1, feed the opposite lane's result into this lane's... - // 0x00010000 [16] CROSS_INPUT (0) If 1, feed the opposite lane's accumulator into this... - // 0x00008000 [15] SIGNED (0) If SIGNED is set, the shifted and masked accumulator... - // 0x00007c00 [14:10] MASK_MSB (0x00) The most-significant bit allowed to pass by the mask... - // 0x000003e0 [9:5] MASK_LSB (0x00) The least-significant bit allowed to pass by the mask (inclusive) - // 0x0000001f [4:0] SHIFT (0x00) Logical right-shift applied to accumulator before masking - io_rw_32 ctrl[2]; - - // (Description copied from array index 0 register SIO_INTERP0_ACCUM0_ADD applies similarly to other array indexes) - _REG_(SIO_INTERP0_ACCUM0_ADD_OFFSET) // SIO_INTERP0_ACCUM0_ADD - // Values written here are atomically added to ACCUM0 - // 0x00ffffff [23:0] INTERP0_ACCUM0_ADD (0x000000) - io_rw_32 add_raw[2]; - - _REG_(SIO_INTERP0_BASE_1AND0_OFFSET) // SIO_INTERP0_BASE_1AND0 - // On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously. - // 0xffffffff [31:0] INTERP0_BASE_1AND0 (0x00000000) - io_wo_32 base01; -} interp_hw_t; - -#define interp_hw_array ((interp_hw_t *)(SIO_BASE + SIO_INTERP0_ACCUM0_OFFSET)) -static_assert(sizeof (interp_hw_t) == 0x0040, ""); -#define interp0_hw (&interp_hw_array[0]) -#define interp1_hw (&interp_hw_array[1]) - -#endif // _HARDWARE_STRUCTS_INTERP_H - diff --git a/lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/io_bank0.h b/lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/io_bank0.h deleted file mode 100644 index 6c09bb0431..0000000000 --- a/lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/io_bank0.h +++ /dev/null @@ -1,236 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _HARDWARE_STRUCTS_IO_BANK0_H -#define _HARDWARE_STRUCTS_IO_BANK0_H - -/** - * \file rp2040/io_bank0.h - */ - -#include "hardware/address_mapped.h" -#include "hardware/regs/io_bank0.h" - -// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_io_bank0 -// -// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) -// _REG_(x) will link to the corresponding register in hardware/regs/io_bank0.h. -// -// Bit-field descriptions are of the form: -// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION - -/** - * \brief GPIO pin function selectors on RP2040 (used as typedef \ref gpio_function_t) - * \ingroup hardware_gpio - */ -typedef enum gpio_function_rp2040 { - GPIO_FUNC_XIP = 0, ///< Select XIP as GPIO pin function - GPIO_FUNC_SPI = 1, ///< Select SPI as GPIO pin function - GPIO_FUNC_UART = 2, ///< Select UART as GPIO pin function - GPIO_FUNC_I2C = 3, ///< Select I2C as GPIO pin function - GPIO_FUNC_PWM = 4, ///< Select PWM as GPIO pin function - GPIO_FUNC_SIO = 5, ///< Select SIO as GPIO pin function - GPIO_FUNC_PIO0 = 6, ///< Select PIO0 as GPIO pin function - GPIO_FUNC_PIO1 = 7, ///< Select PIO1 as GPIO pin function - GPIO_FUNC_GPCK = 8, ///< Select GPCK as GPIO pin function - GPIO_FUNC_USB = 9, ///< Select USB as GPIO pin function - GPIO_FUNC_NULL = 0x1f, ///< Select NULL as GPIO pin function -} gpio_function_t; - -typedef struct { - _REG_(IO_BANK0_GPIO0_STATUS_OFFSET) // IO_BANK0_GPIO0_STATUS - // GPIO status - // 0x04000000 [26] IRQTOPROC (0) interrupt to processors, after override is applied - // 0x01000000 [24] IRQFROMPAD (0) interrupt from pad before override is applied - // 0x00080000 [19] INTOPERI (0) input signal to peripheral, after override is applied - // 0x00020000 [17] INFROMPAD (0) input signal from pad, before override is applied - // 0x00002000 [13] OETOPAD (0) output enable to pad after register override is applied - // 0x00001000 [12] OEFROMPERI (0) output enable from selected peripheral, before register... - // 0x00000200 [9] OUTTOPAD (0) output signal to pad after register override is applied - // 0x00000100 [8] OUTFROMPERI (0) output signal from selected peripheral, before register... - io_ro_32 status; - - _REG_(IO_BANK0_GPIO0_CTRL_OFFSET) // IO_BANK0_GPIO0_CTRL - // GPIO control including function select and overrides - // 0x30000000 [29:28] IRQOVER (0x0) - // 0x00030000 [17:16] INOVER (0x0) - // 0x00003000 [13:12] OEOVER (0x0) - // 0x00000300 [9:8] OUTOVER (0x0) - // 0x0000001f [4:0] FUNCSEL (0x1f) 0-31 -> selects pin function according to the gpio table + - io_rw_32 ctrl; -} io_bank0_status_ctrl_hw_t; - -typedef struct { - // (Description copied from array index 0 register IO_BANK0_PROC0_INTE0 applies similarly to other array indexes) - _REG_(IO_BANK0_PROC0_INTE0_OFFSET) // IO_BANK0_PROC0_INTE0 - // Interrupt Enable for proc0 - // 0x80000000 [31] GPIO7_EDGE_HIGH (0) - // 0x40000000 [30] GPIO7_EDGE_LOW (0) - // 0x20000000 [29] GPIO7_LEVEL_HIGH (0) - // 0x10000000 [28] GPIO7_LEVEL_LOW (0) - // 0x08000000 [27] GPIO6_EDGE_HIGH (0) - // 0x04000000 [26] GPIO6_EDGE_LOW (0) - // 0x02000000 [25] GPIO6_LEVEL_HIGH (0) - // 0x01000000 [24] GPIO6_LEVEL_LOW (0) - // 0x00800000 [23] GPIO5_EDGE_HIGH (0) - // 0x00400000 [22] GPIO5_EDGE_LOW (0) - // 0x00200000 [21] GPIO5_LEVEL_HIGH (0) - // 0x00100000 [20] GPIO5_LEVEL_LOW (0) - // 0x00080000 [19] GPIO4_EDGE_HIGH (0) - // 0x00040000 [18] GPIO4_EDGE_LOW (0) - // 0x00020000 [17] GPIO4_LEVEL_HIGH (0) - // 0x00010000 [16] GPIO4_LEVEL_LOW (0) - // 0x00008000 [15] GPIO3_EDGE_HIGH (0) - // 0x00004000 [14] GPIO3_EDGE_LOW (0) - // 0x00002000 [13] GPIO3_LEVEL_HIGH (0) - // 0x00001000 [12] GPIO3_LEVEL_LOW (0) - // 0x00000800 [11] GPIO2_EDGE_HIGH (0) - // 0x00000400 [10] GPIO2_EDGE_LOW (0) - // 0x00000200 [9] GPIO2_LEVEL_HIGH (0) - // 0x00000100 [8] GPIO2_LEVEL_LOW (0) - // 0x00000080 [7] GPIO1_EDGE_HIGH (0) - // 0x00000040 [6] GPIO1_EDGE_LOW (0) - // 0x00000020 [5] GPIO1_LEVEL_HIGH (0) - // 0x00000010 [4] GPIO1_LEVEL_LOW (0) - // 0x00000008 [3] GPIO0_EDGE_HIGH (0) - // 0x00000004 [2] GPIO0_EDGE_LOW (0) - // 0x00000002 [1] GPIO0_LEVEL_HIGH (0) - // 0x00000001 [0] GPIO0_LEVEL_LOW (0) - io_rw_32 inte[4]; - - // (Description copied from array index 0 register IO_BANK0_PROC0_INTF0 applies similarly to other array indexes) - _REG_(IO_BANK0_PROC0_INTF0_OFFSET) // IO_BANK0_PROC0_INTF0 - // Interrupt Force for proc0 - // 0x80000000 [31] GPIO7_EDGE_HIGH (0) - // 0x40000000 [30] GPIO7_EDGE_LOW (0) - // 0x20000000 [29] GPIO7_LEVEL_HIGH (0) - // 0x10000000 [28] GPIO7_LEVEL_LOW (0) - // 0x08000000 [27] GPIO6_EDGE_HIGH (0) - // 0x04000000 [26] GPIO6_EDGE_LOW (0) - // 0x02000000 [25] GPIO6_LEVEL_HIGH (0) - // 0x01000000 [24] GPIO6_LEVEL_LOW (0) - // 0x00800000 [23] GPIO5_EDGE_HIGH (0) - // 0x00400000 [22] GPIO5_EDGE_LOW (0) - // 0x00200000 [21] GPIO5_LEVEL_HIGH (0) - // 0x00100000 [20] GPIO5_LEVEL_LOW (0) - // 0x00080000 [19] GPIO4_EDGE_HIGH (0) - // 0x00040000 [18] GPIO4_EDGE_LOW (0) - // 0x00020000 [17] GPIO4_LEVEL_HIGH (0) - // 0x00010000 [16] GPIO4_LEVEL_LOW (0) - // 0x00008000 [15] GPIO3_EDGE_HIGH (0) - // 0x00004000 [14] GPIO3_EDGE_LOW (0) - // 0x00002000 [13] GPIO3_LEVEL_HIGH (0) - // 0x00001000 [12] GPIO3_LEVEL_LOW (0) - // 0x00000800 [11] GPIO2_EDGE_HIGH (0) - // 0x00000400 [10] GPIO2_EDGE_LOW (0) - // 0x00000200 [9] GPIO2_LEVEL_HIGH (0) - // 0x00000100 [8] GPIO2_LEVEL_LOW (0) - // 0x00000080 [7] GPIO1_EDGE_HIGH (0) - // 0x00000040 [6] GPIO1_EDGE_LOW (0) - // 0x00000020 [5] GPIO1_LEVEL_HIGH (0) - // 0x00000010 [4] GPIO1_LEVEL_LOW (0) - // 0x00000008 [3] GPIO0_EDGE_HIGH (0) - // 0x00000004 [2] GPIO0_EDGE_LOW (0) - // 0x00000002 [1] GPIO0_LEVEL_HIGH (0) - // 0x00000001 [0] GPIO0_LEVEL_LOW (0) - io_rw_32 intf[4]; - - // (Description copied from array index 0 register IO_BANK0_PROC0_INTS0 applies similarly to other array indexes) - _REG_(IO_BANK0_PROC0_INTS0_OFFSET) // IO_BANK0_PROC0_INTS0 - // Interrupt status after masking & forcing for proc0 - // 0x80000000 [31] GPIO7_EDGE_HIGH (0) - // 0x40000000 [30] GPIO7_EDGE_LOW (0) - // 0x20000000 [29] GPIO7_LEVEL_HIGH (0) - // 0x10000000 [28] GPIO7_LEVEL_LOW (0) - // 0x08000000 [27] GPIO6_EDGE_HIGH (0) - // 0x04000000 [26] GPIO6_EDGE_LOW (0) - // 0x02000000 [25] GPIO6_LEVEL_HIGH (0) - // 0x01000000 [24] GPIO6_LEVEL_LOW (0) - // 0x00800000 [23] GPIO5_EDGE_HIGH (0) - // 0x00400000 [22] GPIO5_EDGE_LOW (0) - // 0x00200000 [21] GPIO5_LEVEL_HIGH (0) - // 0x00100000 [20] GPIO5_LEVEL_LOW (0) - // 0x00080000 [19] GPIO4_EDGE_HIGH (0) - // 0x00040000 [18] GPIO4_EDGE_LOW (0) - // 0x00020000 [17] GPIO4_LEVEL_HIGH (0) - // 0x00010000 [16] GPIO4_LEVEL_LOW (0) - // 0x00008000 [15] GPIO3_EDGE_HIGH (0) - // 0x00004000 [14] GPIO3_EDGE_LOW (0) - // 0x00002000 [13] GPIO3_LEVEL_HIGH (0) - // 0x00001000 [12] GPIO3_LEVEL_LOW (0) - // 0x00000800 [11] GPIO2_EDGE_HIGH (0) - // 0x00000400 [10] GPIO2_EDGE_LOW (0) - // 0x00000200 [9] GPIO2_LEVEL_HIGH (0) - // 0x00000100 [8] GPIO2_LEVEL_LOW (0) - // 0x00000080 [7] GPIO1_EDGE_HIGH (0) - // 0x00000040 [6] GPIO1_EDGE_LOW (0) - // 0x00000020 [5] GPIO1_LEVEL_HIGH (0) - // 0x00000010 [4] GPIO1_LEVEL_LOW (0) - // 0x00000008 [3] GPIO0_EDGE_HIGH (0) - // 0x00000004 [2] GPIO0_EDGE_LOW (0) - // 0x00000002 [1] GPIO0_LEVEL_HIGH (0) - // 0x00000001 [0] GPIO0_LEVEL_LOW (0) - io_ro_32 ints[4]; -} io_bank0_irq_ctrl_hw_t; - -/// \tag::io_bank0_hw[] -typedef struct { - io_bank0_status_ctrl_hw_t io[30]; - - // (Description copied from array index 0 register IO_BANK0_INTR0 applies similarly to other array indexes) - _REG_(IO_BANK0_INTR0_OFFSET) // IO_BANK0_INTR0 - // Raw Interrupts - // 0x80000000 [31] GPIO7_EDGE_HIGH (0) - // 0x40000000 [30] GPIO7_EDGE_LOW (0) - // 0x20000000 [29] GPIO7_LEVEL_HIGH (0) - // 0x10000000 [28] GPIO7_LEVEL_LOW (0) - // 0x08000000 [27] GPIO6_EDGE_HIGH (0) - // 0x04000000 [26] GPIO6_EDGE_LOW (0) - // 0x02000000 [25] GPIO6_LEVEL_HIGH (0) - // 0x01000000 [24] GPIO6_LEVEL_LOW (0) - // 0x00800000 [23] GPIO5_EDGE_HIGH (0) - // 0x00400000 [22] GPIO5_EDGE_LOW (0) - // 0x00200000 [21] GPIO5_LEVEL_HIGH (0) - // 0x00100000 [20] GPIO5_LEVEL_LOW (0) - // 0x00080000 [19] GPIO4_EDGE_HIGH (0) - // 0x00040000 [18] GPIO4_EDGE_LOW (0) - // 0x00020000 [17] GPIO4_LEVEL_HIGH (0) - // 0x00010000 [16] GPIO4_LEVEL_LOW (0) - // 0x00008000 [15] GPIO3_EDGE_HIGH (0) - // 0x00004000 [14] GPIO3_EDGE_LOW (0) - // 0x00002000 [13] GPIO3_LEVEL_HIGH (0) - // 0x00001000 [12] GPIO3_LEVEL_LOW (0) - // 0x00000800 [11] GPIO2_EDGE_HIGH (0) - // 0x00000400 [10] GPIO2_EDGE_LOW (0) - // 0x00000200 [9] GPIO2_LEVEL_HIGH (0) - // 0x00000100 [8] GPIO2_LEVEL_LOW (0) - // 0x00000080 [7] GPIO1_EDGE_HIGH (0) - // 0x00000040 [6] GPIO1_EDGE_LOW (0) - // 0x00000020 [5] GPIO1_LEVEL_HIGH (0) - // 0x00000010 [4] GPIO1_LEVEL_LOW (0) - // 0x00000008 [3] GPIO0_EDGE_HIGH (0) - // 0x00000004 [2] GPIO0_EDGE_LOW (0) - // 0x00000002 [1] GPIO0_LEVEL_HIGH (0) - // 0x00000001 [0] GPIO0_LEVEL_LOW (0) - io_rw_32 intr[4]; - - union { - struct { - io_bank0_irq_ctrl_hw_t proc0_irq_ctrl; - io_bank0_irq_ctrl_hw_t proc1_irq_ctrl; - io_bank0_irq_ctrl_hw_t dormant_wake_irq_ctrl; - }; - io_bank0_irq_ctrl_hw_t irq_ctrl[3]; - }; -} io_bank0_hw_t; -/// \end::io_bank0_hw[] - -#define io_bank0_hw ((io_bank0_hw_t *)IO_BANK0_BASE) -static_assert(sizeof (io_bank0_hw_t) == 0x0190, ""); - -#endif // _HARDWARE_STRUCTS_IO_BANK0_H - diff --git a/lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/io_qspi.h b/lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/io_qspi.h deleted file mode 100644 index 4dca02f5cb..0000000000 --- a/lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/io_qspi.h +++ /dev/null @@ -1,189 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _HARDWARE_STRUCTS_IO_QSPI_H -#define _HARDWARE_STRUCTS_IO_QSPI_H - -/** - * \file rp2040/io_qspi.h - */ - -#include "hardware/address_mapped.h" -#include "hardware/regs/io_qspi.h" - -// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_io_qspi -// -// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) -// _REG_(x) will link to the corresponding register in hardware/regs/io_qspi.h. -// -// Bit-field descriptions are of the form: -// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION - -/** - * \brief QSPI pin function selectors on RP2040 (used as typedef \ref gpio_function1_t) - */ -typedef enum gpio_function1_rp2040 { - GPIO_FUNC1_XIP = 0, ///< Select XIP as QSPI pin function - GPIO_FUNC1_SIO = 5, ///< Select SIO as QSPI pin function - GPIO_FUNC1_NULL = 0x1f, ///< Select NULL as QSPI pin function -} gpio_function1_t; - -typedef struct { - _REG_(IO_QSPI_GPIO_QSPI_SCLK_STATUS_OFFSET) // IO_QSPI_GPIO_QSPI_SCLK_STATUS - // GPIO status - // 0x04000000 [26] IRQTOPROC (0) interrupt to processors, after override is applied - // 0x01000000 [24] IRQFROMPAD (0) interrupt from pad before override is applied - // 0x00080000 [19] INTOPERI (0) input signal to peripheral, after override is applied - // 0x00020000 [17] INFROMPAD (0) input signal from pad, before override is applied - // 0x00002000 [13] OETOPAD (0) output enable to pad after register override is applied - // 0x00001000 [12] OEFROMPERI (0) output enable from selected peripheral, before register... - // 0x00000200 [9] OUTTOPAD (0) output signal to pad after register override is applied - // 0x00000100 [8] OUTFROMPERI (0) output signal from selected peripheral, before register... - io_ro_32 status; - - _REG_(IO_QSPI_GPIO_QSPI_SCLK_CTRL_OFFSET) // IO_QSPI_GPIO_QSPI_SCLK_CTRL - // GPIO control including function select and overrides - // 0x30000000 [29:28] IRQOVER (0x0) - // 0x00030000 [17:16] INOVER (0x0) - // 0x00003000 [13:12] OEOVER (0x0) - // 0x00000300 [9:8] OUTOVER (0x0) - // 0x0000001f [4:0] FUNCSEL (0x1f) 0-31 -> selects pin function according to the gpio table + - io_rw_32 ctrl; -} io_qspi_status_ctrl_hw_t; - -typedef struct { - _REG_(IO_QSPI_PROC0_INTE_OFFSET) // IO_QSPI_PROC0_INTE - // Interrupt Enable for proc0 - // 0x00800000 [23] GPIO_QSPI_SD3_EDGE_HIGH (0) - // 0x00400000 [22] GPIO_QSPI_SD3_EDGE_LOW (0) - // 0x00200000 [21] GPIO_QSPI_SD3_LEVEL_HIGH (0) - // 0x00100000 [20] GPIO_QSPI_SD3_LEVEL_LOW (0) - // 0x00080000 [19] GPIO_QSPI_SD2_EDGE_HIGH (0) - // 0x00040000 [18] GPIO_QSPI_SD2_EDGE_LOW (0) - // 0x00020000 [17] GPIO_QSPI_SD2_LEVEL_HIGH (0) - // 0x00010000 [16] GPIO_QSPI_SD2_LEVEL_LOW (0) - // 0x00008000 [15] GPIO_QSPI_SD1_EDGE_HIGH (0) - // 0x00004000 [14] GPIO_QSPI_SD1_EDGE_LOW (0) - // 0x00002000 [13] GPIO_QSPI_SD1_LEVEL_HIGH (0) - // 0x00001000 [12] GPIO_QSPI_SD1_LEVEL_LOW (0) - // 0x00000800 [11] GPIO_QSPI_SD0_EDGE_HIGH (0) - // 0x00000400 [10] GPIO_QSPI_SD0_EDGE_LOW (0) - // 0x00000200 [9] GPIO_QSPI_SD0_LEVEL_HIGH (0) - // 0x00000100 [8] GPIO_QSPI_SD0_LEVEL_LOW (0) - // 0x00000080 [7] GPIO_QSPI_SS_EDGE_HIGH (0) - // 0x00000040 [6] GPIO_QSPI_SS_EDGE_LOW (0) - // 0x00000020 [5] GPIO_QSPI_SS_LEVEL_HIGH (0) - // 0x00000010 [4] GPIO_QSPI_SS_LEVEL_LOW (0) - // 0x00000008 [3] GPIO_QSPI_SCLK_EDGE_HIGH (0) - // 0x00000004 [2] GPIO_QSPI_SCLK_EDGE_LOW (0) - // 0x00000002 [1] GPIO_QSPI_SCLK_LEVEL_HIGH (0) - // 0x00000001 [0] GPIO_QSPI_SCLK_LEVEL_LOW (0) - io_rw_32 inte; - - _REG_(IO_QSPI_PROC0_INTF_OFFSET) // IO_QSPI_PROC0_INTF - // Interrupt Force for proc0 - // 0x00800000 [23] GPIO_QSPI_SD3_EDGE_HIGH (0) - // 0x00400000 [22] GPIO_QSPI_SD3_EDGE_LOW (0) - // 0x00200000 [21] GPIO_QSPI_SD3_LEVEL_HIGH (0) - // 0x00100000 [20] GPIO_QSPI_SD3_LEVEL_LOW (0) - // 0x00080000 [19] GPIO_QSPI_SD2_EDGE_HIGH (0) - // 0x00040000 [18] GPIO_QSPI_SD2_EDGE_LOW (0) - // 0x00020000 [17] GPIO_QSPI_SD2_LEVEL_HIGH (0) - // 0x00010000 [16] GPIO_QSPI_SD2_LEVEL_LOW (0) - // 0x00008000 [15] GPIO_QSPI_SD1_EDGE_HIGH (0) - // 0x00004000 [14] GPIO_QSPI_SD1_EDGE_LOW (0) - // 0x00002000 [13] GPIO_QSPI_SD1_LEVEL_HIGH (0) - // 0x00001000 [12] GPIO_QSPI_SD1_LEVEL_LOW (0) - // 0x00000800 [11] GPIO_QSPI_SD0_EDGE_HIGH (0) - // 0x00000400 [10] GPIO_QSPI_SD0_EDGE_LOW (0) - // 0x00000200 [9] GPIO_QSPI_SD0_LEVEL_HIGH (0) - // 0x00000100 [8] GPIO_QSPI_SD0_LEVEL_LOW (0) - // 0x00000080 [7] GPIO_QSPI_SS_EDGE_HIGH (0) - // 0x00000040 [6] GPIO_QSPI_SS_EDGE_LOW (0) - // 0x00000020 [5] GPIO_QSPI_SS_LEVEL_HIGH (0) - // 0x00000010 [4] GPIO_QSPI_SS_LEVEL_LOW (0) - // 0x00000008 [3] GPIO_QSPI_SCLK_EDGE_HIGH (0) - // 0x00000004 [2] GPIO_QSPI_SCLK_EDGE_LOW (0) - // 0x00000002 [1] GPIO_QSPI_SCLK_LEVEL_HIGH (0) - // 0x00000001 [0] GPIO_QSPI_SCLK_LEVEL_LOW (0) - io_rw_32 intf; - - _REG_(IO_QSPI_PROC0_INTS_OFFSET) // IO_QSPI_PROC0_INTS - // Interrupt status after masking & forcing for proc0 - // 0x00800000 [23] GPIO_QSPI_SD3_EDGE_HIGH (0) - // 0x00400000 [22] GPIO_QSPI_SD3_EDGE_LOW (0) - // 0x00200000 [21] GPIO_QSPI_SD3_LEVEL_HIGH (0) - // 0x00100000 [20] GPIO_QSPI_SD3_LEVEL_LOW (0) - // 0x00080000 [19] GPIO_QSPI_SD2_EDGE_HIGH (0) - // 0x00040000 [18] GPIO_QSPI_SD2_EDGE_LOW (0) - // 0x00020000 [17] GPIO_QSPI_SD2_LEVEL_HIGH (0) - // 0x00010000 [16] GPIO_QSPI_SD2_LEVEL_LOW (0) - // 0x00008000 [15] GPIO_QSPI_SD1_EDGE_HIGH (0) - // 0x00004000 [14] GPIO_QSPI_SD1_EDGE_LOW (0) - // 0x00002000 [13] GPIO_QSPI_SD1_LEVEL_HIGH (0) - // 0x00001000 [12] GPIO_QSPI_SD1_LEVEL_LOW (0) - // 0x00000800 [11] GPIO_QSPI_SD0_EDGE_HIGH (0) - // 0x00000400 [10] GPIO_QSPI_SD0_EDGE_LOW (0) - // 0x00000200 [9] GPIO_QSPI_SD0_LEVEL_HIGH (0) - // 0x00000100 [8] GPIO_QSPI_SD0_LEVEL_LOW (0) - // 0x00000080 [7] GPIO_QSPI_SS_EDGE_HIGH (0) - // 0x00000040 [6] GPIO_QSPI_SS_EDGE_LOW (0) - // 0x00000020 [5] GPIO_QSPI_SS_LEVEL_HIGH (0) - // 0x00000010 [4] GPIO_QSPI_SS_LEVEL_LOW (0) - // 0x00000008 [3] GPIO_QSPI_SCLK_EDGE_HIGH (0) - // 0x00000004 [2] GPIO_QSPI_SCLK_EDGE_LOW (0) - // 0x00000002 [1] GPIO_QSPI_SCLK_LEVEL_HIGH (0) - // 0x00000001 [0] GPIO_QSPI_SCLK_LEVEL_LOW (0) - io_ro_32 ints; -} io_qspi_irq_ctrl_hw_t; - -typedef struct { - io_qspi_status_ctrl_hw_t io[6]; - - _REG_(IO_QSPI_INTR_OFFSET) // IO_QSPI_INTR - // Raw Interrupts - // 0x00800000 [23] GPIO_QSPI_SD3_EDGE_HIGH (0) - // 0x00400000 [22] GPIO_QSPI_SD3_EDGE_LOW (0) - // 0x00200000 [21] GPIO_QSPI_SD3_LEVEL_HIGH (0) - // 0x00100000 [20] GPIO_QSPI_SD3_LEVEL_LOW (0) - // 0x00080000 [19] GPIO_QSPI_SD2_EDGE_HIGH (0) - // 0x00040000 [18] GPIO_QSPI_SD2_EDGE_LOW (0) - // 0x00020000 [17] GPIO_QSPI_SD2_LEVEL_HIGH (0) - // 0x00010000 [16] GPIO_QSPI_SD2_LEVEL_LOW (0) - // 0x00008000 [15] GPIO_QSPI_SD1_EDGE_HIGH (0) - // 0x00004000 [14] GPIO_QSPI_SD1_EDGE_LOW (0) - // 0x00002000 [13] GPIO_QSPI_SD1_LEVEL_HIGH (0) - // 0x00001000 [12] GPIO_QSPI_SD1_LEVEL_LOW (0) - // 0x00000800 [11] GPIO_QSPI_SD0_EDGE_HIGH (0) - // 0x00000400 [10] GPIO_QSPI_SD0_EDGE_LOW (0) - // 0x00000200 [9] GPIO_QSPI_SD0_LEVEL_HIGH (0) - // 0x00000100 [8] GPIO_QSPI_SD0_LEVEL_LOW (0) - // 0x00000080 [7] GPIO_QSPI_SS_EDGE_HIGH (0) - // 0x00000040 [6] GPIO_QSPI_SS_EDGE_LOW (0) - // 0x00000020 [5] GPIO_QSPI_SS_LEVEL_HIGH (0) - // 0x00000010 [4] GPIO_QSPI_SS_LEVEL_LOW (0) - // 0x00000008 [3] GPIO_QSPI_SCLK_EDGE_HIGH (0) - // 0x00000004 [2] GPIO_QSPI_SCLK_EDGE_LOW (0) - // 0x00000002 [1] GPIO_QSPI_SCLK_LEVEL_HIGH (0) - // 0x00000001 [0] GPIO_QSPI_SCLK_LEVEL_LOW (0) - io_rw_32 intr; - - union { - struct { - io_qspi_irq_ctrl_hw_t proc0_irq_ctrl; - io_qspi_irq_ctrl_hw_t proc1_irq_ctrl; - io_qspi_irq_ctrl_hw_t dormant_wake_irq_ctrl; - }; - io_qspi_irq_ctrl_hw_t irq_ctrl[3]; - }; -} io_qspi_hw_t; - -#define io_qspi_hw ((io_qspi_hw_t *)IO_QSPI_BASE) -static_assert(sizeof (io_qspi_hw_t) == 0x0058, ""); - -#endif // _HARDWARE_STRUCTS_IO_QSPI_H - diff --git a/lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/iobank0.h b/lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/iobank0.h deleted file mode 100644 index 2dc31e38d4..0000000000 --- a/lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/iobank0.h +++ /dev/null @@ -1,9 +0,0 @@ -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -// Support old header for compatibility (and if included, support old variable name) -#include "hardware/structs/io_bank0.h" -#define iobank0_hw io_bank0_hw \ No newline at end of file diff --git a/lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/ioqspi.h b/lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/ioqspi.h deleted file mode 100644 index 20cc74c79b..0000000000 --- a/lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/ioqspi.h +++ /dev/null @@ -1,9 +0,0 @@ -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -// Support old header for compatibility (and if included, support old variable name) -#include "hardware/structs/io_qspi.h" -#define ioqspi_hw io_qspi_hw \ No newline at end of file diff --git a/lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/m0plus.h b/lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/m0plus.h deleted file mode 100644 index 6d30edec00..0000000000 --- a/lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/m0plus.h +++ /dev/null @@ -1,197 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _HARDWARE_STRUCTS_M0PLUS_H -#define _HARDWARE_STRUCTS_M0PLUS_H - -/** - * \file rp2040/m0plus.h - */ - -#include "hardware/address_mapped.h" -#include "hardware/regs/m0plus.h" - -// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_m0plus -// -// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) -// _REG_(x) will link to the corresponding register in hardware/regs/m0plus.h. -// -// Bit-field descriptions are of the form: -// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION - -typedef struct { - uint32_t _pad0[14340]; - - _REG_(M0PLUS_SYST_CSR_OFFSET) // M0PLUS_SYST_CSR - // SysTick Control and Status Register - // 0x00010000 [16] COUNTFLAG (0) Returns 1 if timer counted to 0 since last time this was read - // 0x00000004 [2] CLKSOURCE (0) SysTick clock source - // 0x00000002 [1] TICKINT (0) Enables SysTick exception request: + - // 0x00000001 [0] ENABLE (0) Enable SysTick counter: + - io_rw_32 syst_csr; - - _REG_(M0PLUS_SYST_RVR_OFFSET) // M0PLUS_SYST_RVR - // SysTick Reload Value Register - // 0x00ffffff [23:0] RELOAD (0x000000) Value to load into the SysTick Current Value Register... - io_rw_32 syst_rvr; - - _REG_(M0PLUS_SYST_CVR_OFFSET) // M0PLUS_SYST_CVR - // SysTick Current Value Register - // 0x00ffffff [23:0] CURRENT (0x000000) Reads return the current value of the SysTick counter - io_rw_32 syst_cvr; - - _REG_(M0PLUS_SYST_CALIB_OFFSET) // M0PLUS_SYST_CALIB - // SysTick Calibration Value Register - // 0x80000000 [31] NOREF (0) If reads as 1, the Reference clock is not provided - the... - // 0x40000000 [30] SKEW (0) If reads as 1, the calibration value for 10ms is inexact... - // 0x00ffffff [23:0] TENMS (0x000000) An optional Reload value to be used for 10ms (100Hz)... - io_ro_32 syst_calib; - - uint32_t _pad1[56]; - - _REG_(M0PLUS_NVIC_ISER_OFFSET) // M0PLUS_NVIC_ISER - // Interrupt Set-Enable Register - // 0xffffffff [31:0] SETENA (0x00000000) Interrupt set-enable bits - io_rw_32 nvic_iser; - - uint32_t _pad2[31]; - - _REG_(M0PLUS_NVIC_ICER_OFFSET) // M0PLUS_NVIC_ICER - // Interrupt Clear-Enable Register - // 0xffffffff [31:0] CLRENA (0x00000000) Interrupt clear-enable bits - io_rw_32 nvic_icer; - - uint32_t _pad3[31]; - - _REG_(M0PLUS_NVIC_ISPR_OFFSET) // M0PLUS_NVIC_ISPR - // Interrupt Set-Pending Register - // 0xffffffff [31:0] SETPEND (0x00000000) Interrupt set-pending bits - io_rw_32 nvic_ispr; - - uint32_t _pad4[31]; - - _REG_(M0PLUS_NVIC_ICPR_OFFSET) // M0PLUS_NVIC_ICPR - // Interrupt Clear-Pending Register - // 0xffffffff [31:0] CLRPEND (0x00000000) Interrupt clear-pending bits - io_rw_32 nvic_icpr; - - uint32_t _pad5[95]; - - // (Description copied from array index 0 register M0PLUS_NVIC_IPR0 applies similarly to other array indexes) - _REG_(M0PLUS_NVIC_IPR0_OFFSET) // M0PLUS_NVIC_IPR0 - // Interrupt Priority Register 0 - // 0xc0000000 [31:30] IP_3 (0x0) Priority of interrupt 3 - // 0x00c00000 [23:22] IP_2 (0x0) Priority of interrupt 2 - // 0x0000c000 [15:14] IP_1 (0x0) Priority of interrupt 1 - // 0x000000c0 [7:6] IP_0 (0x0) Priority of interrupt 0 - io_rw_32 nvic_ipr[8]; - - uint32_t _pad6[568]; - - _REG_(M0PLUS_CPUID_OFFSET) // M0PLUS_CPUID - // CPUID Base Register - // 0xff000000 [31:24] IMPLEMENTER (0x41) Implementor code: 0x41 = ARM - // 0x00f00000 [23:20] VARIANT (0x0) Major revision number n in the rnpm revision status: + - // 0x000f0000 [19:16] ARCHITECTURE (0xc) Constant that defines the architecture of the processor: + - // 0x0000fff0 [15:4] PARTNO (0xc60) Number of processor within family: 0xC60 = Cortex-M0+ - // 0x0000000f [3:0] REVISION (0x1) Minor revision number m in the rnpm revision status: + - io_ro_32 cpuid; - - _REG_(M0PLUS_ICSR_OFFSET) // M0PLUS_ICSR - // Interrupt Control and State Register - // 0x80000000 [31] NMIPENDSET (0) Setting this bit will activate an NMI - // 0x10000000 [28] PENDSVSET (0) PendSV set-pending bit - // 0x08000000 [27] PENDSVCLR (0) PendSV clear-pending bit - // 0x04000000 [26] PENDSTSET (0) SysTick exception set-pending bit - // 0x02000000 [25] PENDSTCLR (0) SysTick exception clear-pending bit - // 0x00800000 [23] ISRPREEMPT (0) The system can only access this bit when the core is halted - // 0x00400000 [22] ISRPENDING (0) External interrupt pending flag - // 0x001ff000 [20:12] VECTPENDING (0x000) Indicates the exception number for the highest priority... - // 0x000001ff [8:0] VECTACTIVE (0x000) Active exception number field - io_rw_32 icsr; - - _REG_(M0PLUS_VTOR_OFFSET) // M0PLUS_VTOR - // Vector Table Offset Register - // 0xffffff00 [31:8] TBLOFF (0x000000) Bits [31:8] of the indicate the vector table offset address - io_rw_32 vtor; - - _REG_(M0PLUS_AIRCR_OFFSET) // M0PLUS_AIRCR - // Application Interrupt and Reset Control Register - // 0xffff0000 [31:16] VECTKEY (0x0000) Register key: + - // 0x00008000 [15] ENDIANESS (0) Data endianness implemented: + - // 0x00000004 [2] SYSRESETREQ (0) Writing 1 to this bit causes the SYSRESETREQ signal to... - // 0x00000002 [1] VECTCLRACTIVE (0) Clears all active state information for fixed and... - io_rw_32 aircr; - - _REG_(M0PLUS_SCR_OFFSET) // M0PLUS_SCR - // System Control Register - // 0x00000010 [4] SEVONPEND (0) Send Event on Pending bit: + - // 0x00000004 [2] SLEEPDEEP (0) Controls whether the processor uses sleep or deep sleep... - // 0x00000002 [1] SLEEPONEXIT (0) Indicates sleep-on-exit when returning from Handler mode... - io_rw_32 scr; - - _REG_(M0PLUS_CCR_OFFSET) // M0PLUS_CCR - // Configuration and Control Register - // 0x00000200 [9] STKALIGN (0) Always reads as one, indicates 8-byte stack alignment on... - // 0x00000008 [3] UNALIGN_TRP (0) Always reads as one, indicates that all unaligned... - io_ro_32 ccr; - - uint32_t _pad7; - - // (Description copied from array index 0 register M0PLUS_SHPR2 applies similarly to other array indexes) - _REG_(M0PLUS_SHPR2_OFFSET) // M0PLUS_SHPR2 - // System Handler Priority Register 2 - // 0xc0000000 [31:30] PRI_11 (0x0) Priority of system handler 11, SVCall - io_rw_32 shpr[2]; - - _REG_(M0PLUS_SHCSR_OFFSET) // M0PLUS_SHCSR - // System Handler Control and State Register - // 0x00008000 [15] SVCALLPENDED (0) Reads as 1 if SVCall is Pending - io_rw_32 shcsr; - - uint32_t _pad8[26]; - - _REG_(M0PLUS_MPU_TYPE_OFFSET) // M0PLUS_MPU_TYPE - // MPU Type Register - // 0x00ff0000 [23:16] IREGION (0x00) Instruction region - // 0x0000ff00 [15:8] DREGION (0x08) Number of regions supported by the MPU - // 0x00000001 [0] SEPARATE (0) Indicates support for separate instruction and data address maps - io_ro_32 mpu_type; - - _REG_(M0PLUS_MPU_CTRL_OFFSET) // M0PLUS_MPU_CTRL - // MPU Control Register - // 0x00000004 [2] PRIVDEFENA (0) Controls whether the default memory map is enabled as a... - // 0x00000002 [1] HFNMIENA (0) Controls the use of the MPU for HardFaults and NMIs - // 0x00000001 [0] ENABLE (0) Enables the MPU - io_rw_32 mpu_ctrl; - - _REG_(M0PLUS_MPU_RNR_OFFSET) // M0PLUS_MPU_RNR - // MPU Region Number Register - // 0x0000000f [3:0] REGION (0x0) Indicates the MPU region referenced by the MPU_RBAR and... - io_rw_32 mpu_rnr; - - _REG_(M0PLUS_MPU_RBAR_OFFSET) // M0PLUS_MPU_RBAR - // MPU Region Base Address Register - // 0xffffff00 [31:8] ADDR (0x000000) Base address of the region - // 0x00000010 [4] VALID (0) On writes, indicates whether the write must update the... - // 0x0000000f [3:0] REGION (0x0) On writes, specifies the number of the region whose base... - io_rw_32 mpu_rbar; - - _REG_(M0PLUS_MPU_RASR_OFFSET) // M0PLUS_MPU_RASR - // MPU Region Attribute and Size Register - // 0xffff0000 [31:16] ATTRS (0x0000) The MPU Region Attribute field - // 0x0000ff00 [15:8] SRD (0x00) Subregion Disable - // 0x0000003e [5:1] SIZE (0x00) Indicates the region size - // 0x00000001 [0] ENABLE (0) Enables the region - io_rw_32 mpu_rasr; -} m0plus_hw_t; - -#define ppb_hw ((m0plus_hw_t *)PPB_BASE) -static_assert(sizeof (m0plus_hw_t) == 0xeda4, ""); - -#endif // _HARDWARE_STRUCTS_M0PLUS_H - diff --git a/lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/mpu.h b/lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/mpu.h deleted file mode 100644 index 766f4d5895..0000000000 --- a/lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/mpu.h +++ /dev/null @@ -1,66 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _HARDWARE_STRUCTS_MPU_H -#define _HARDWARE_STRUCTS_MPU_H - -/** - * \file rp2040/mpu.h - */ - -#include "hardware/address_mapped.h" -#include "hardware/regs/m0plus.h" - -// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_m0plus -// -// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) -// _REG_(x) will link to the corresponding register in hardware/regs/m0plus.h. -// -// Bit-field descriptions are of the form: -// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION - -typedef struct { - _REG_(M0PLUS_MPU_TYPE_OFFSET) // M0PLUS_MPU_TYPE - // MPU Type Register - // 0x00ff0000 [23:16] IREGION (0x00) Instruction region - // 0x0000ff00 [15:8] DREGION (0x08) Number of regions supported by the MPU - // 0x00000001 [0] SEPARATE (0) Indicates support for separate instruction and data address maps - io_ro_32 type; - - _REG_(M0PLUS_MPU_CTRL_OFFSET) // M0PLUS_MPU_CTRL - // MPU Control Register - // 0x00000004 [2] PRIVDEFENA (0) Controls whether the default memory map is enabled as a... - // 0x00000002 [1] HFNMIENA (0) Controls the use of the MPU for HardFaults and NMIs - // 0x00000001 [0] ENABLE (0) Enables the MPU - io_rw_32 ctrl; - - _REG_(M0PLUS_MPU_RNR_OFFSET) // M0PLUS_MPU_RNR - // MPU Region Number Register - // 0x0000000f [3:0] REGION (0x0) Indicates the MPU region referenced by the MPU_RBAR and... - io_rw_32 rnr; - - _REG_(M0PLUS_MPU_RBAR_OFFSET) // M0PLUS_MPU_RBAR - // MPU Region Base Address Register - // 0xffffff00 [31:8] ADDR (0x000000) Base address of the region - // 0x00000010 [4] VALID (0) On writes, indicates whether the write must update the... - // 0x0000000f [3:0] REGION (0x0) On writes, specifies the number of the region whose base... - io_rw_32 rbar; - - _REG_(M0PLUS_MPU_RASR_OFFSET) // M0PLUS_MPU_RASR - // MPU Region Attribute and Size Register - // 0xffff0000 [31:16] ATTRS (0x0000) The MPU Region Attribute field - // 0x0000ff00 [15:8] SRD (0x00) Subregion Disable - // 0x0000003e [5:1] SIZE (0x00) Indicates the region size - // 0x00000001 [0] ENABLE (0) Enables the region - io_rw_32 rasr; -} mpu_hw_t; - -#define mpu_hw ((mpu_hw_t *)(PPB_BASE + M0PLUS_MPU_TYPE_OFFSET)) -static_assert(sizeof (mpu_hw_t) == 0x0014, ""); - -#endif // _HARDWARE_STRUCTS_MPU_H - diff --git a/lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/nvic.h b/lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/nvic.h deleted file mode 100644 index d09ebd19e8..0000000000 --- a/lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/nvic.h +++ /dev/null @@ -1,69 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _HARDWARE_STRUCTS_NVIC_H -#define _HARDWARE_STRUCTS_NVIC_H - -/** - * \file rp2040/nvic.h - */ - -#include "hardware/address_mapped.h" -#include "hardware/regs/m0plus.h" - -// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_m0plus -// -// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) -// _REG_(x) will link to the corresponding register in hardware/regs/m0plus.h. -// -// Bit-field descriptions are of the form: -// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION - -typedef struct { - _REG_(M0PLUS_NVIC_ISER_OFFSET) // M0PLUS_NVIC_ISER - // Interrupt Set-Enable Register - // 0xffffffff [31:0] SETENA (0x00000000) Interrupt set-enable bits - io_rw_32 iser; - - uint32_t _pad0[31]; - - _REG_(M0PLUS_NVIC_ICER_OFFSET) // M0PLUS_NVIC_ICER - // Interrupt Clear-Enable Register - // 0xffffffff [31:0] CLRENA (0x00000000) Interrupt clear-enable bits - io_rw_32 icer; - - uint32_t _pad1[31]; - - _REG_(M0PLUS_NVIC_ISPR_OFFSET) // M0PLUS_NVIC_ISPR - // Interrupt Set-Pending Register - // 0xffffffff [31:0] SETPEND (0x00000000) Interrupt set-pending bits - io_rw_32 ispr; - - uint32_t _pad2[31]; - - _REG_(M0PLUS_NVIC_ICPR_OFFSET) // M0PLUS_NVIC_ICPR - // Interrupt Clear-Pending Register - // 0xffffffff [31:0] CLRPEND (0x00000000) Interrupt clear-pending bits - io_rw_32 icpr; - - uint32_t _pad3[95]; - - // (Description copied from array index 0 register M0PLUS_NVIC_IPR0 applies similarly to other array indexes) - _REG_(M0PLUS_NVIC_IPR0_OFFSET) // M0PLUS_NVIC_IPR0 - // Interrupt Priority Register 0 - // 0xc0000000 [31:30] IP_3 (0x0) Priority of interrupt 3 - // 0x00c00000 [23:22] IP_2 (0x0) Priority of interrupt 2 - // 0x0000c000 [15:14] IP_1 (0x0) Priority of interrupt 1 - // 0x000000c0 [7:6] IP_0 (0x0) Priority of interrupt 0 - io_rw_32 ipr[8]; -} nvic_hw_t; - -#define nvic_hw ((nvic_hw_t *)(PPB_BASE + M0PLUS_NVIC_ISER_OFFSET)) -static_assert(sizeof (nvic_hw_t) == 0x0320, ""); - -#endif // _HARDWARE_STRUCTS_NVIC_H - diff --git a/lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/pads_bank0.h b/lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/pads_bank0.h deleted file mode 100644 index f00c70afcb..0000000000 --- a/lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/pads_bank0.h +++ /dev/null @@ -1,49 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _HARDWARE_STRUCTS_PADS_BANK0_H -#define _HARDWARE_STRUCTS_PADS_BANK0_H - -/** - * \file rp2040/pads_bank0.h - */ - -#include "hardware/address_mapped.h" -#include "hardware/regs/pads_bank0.h" - -// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_pads_bank0 -// -// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) -// _REG_(x) will link to the corresponding register in hardware/regs/pads_bank0.h. -// -// Bit-field descriptions are of the form: -// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION - -typedef struct { - _REG_(PADS_BANK0_VOLTAGE_SELECT_OFFSET) // PADS_BANK0_VOLTAGE_SELECT - // Voltage select - // 0x00000001 [0] VOLTAGE_SELECT (0) - io_rw_32 voltage_select; - - // (Description copied from array index 0 register PADS_BANK0_GPIO0 applies similarly to other array indexes) - _REG_(PADS_BANK0_GPIO0_OFFSET) // PADS_BANK0_GPIO0 - // Pad control register - // 0x00000080 [7] OD (0) Output disable - // 0x00000040 [6] IE (1) Input enable - // 0x00000030 [5:4] DRIVE (0x1) Drive strength - // 0x00000008 [3] PUE (0) Pull up enable - // 0x00000004 [2] PDE (1) Pull down enable - // 0x00000002 [1] SCHMITT (1) Enable schmitt trigger - // 0x00000001 [0] SLEWFAST (0) Slew rate control - io_rw_32 io[30]; -} pads_bank0_hw_t; - -#define pads_bank0_hw ((pads_bank0_hw_t *)PADS_BANK0_BASE) -static_assert(sizeof (pads_bank0_hw_t) == 0x007c, ""); - -#endif // _HARDWARE_STRUCTS_PADS_BANK0_H - diff --git a/lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/pads_qspi.h b/lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/pads_qspi.h deleted file mode 100644 index 66b6c1a1bb..0000000000 --- a/lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/pads_qspi.h +++ /dev/null @@ -1,49 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _HARDWARE_STRUCTS_PADS_QSPI_H -#define _HARDWARE_STRUCTS_PADS_QSPI_H - -/** - * \file rp2040/pads_qspi.h - */ - -#include "hardware/address_mapped.h" -#include "hardware/regs/pads_qspi.h" - -// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_pads_qspi -// -// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) -// _REG_(x) will link to the corresponding register in hardware/regs/pads_qspi.h. -// -// Bit-field descriptions are of the form: -// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION - -typedef struct { - _REG_(PADS_QSPI_VOLTAGE_SELECT_OFFSET) // PADS_QSPI_VOLTAGE_SELECT - // Voltage select - // 0x00000001 [0] VOLTAGE_SELECT (0) - io_rw_32 voltage_select; - - // (Description copied from array index 0 register PADS_QSPI_GPIO_QSPI_SCLK applies similarly to other array indexes) - _REG_(PADS_QSPI_GPIO_QSPI_SCLK_OFFSET) // PADS_QSPI_GPIO_QSPI_SCLK - // Pad control register - // 0x00000080 [7] OD (0) Output disable - // 0x00000040 [6] IE (1) Input enable - // 0x00000030 [5:4] DRIVE (0x1) Drive strength - // 0x00000008 [3] PUE (0) Pull up enable - // 0x00000004 [2] PDE (1) Pull down enable - // 0x00000002 [1] SCHMITT (1) Enable schmitt trigger - // 0x00000001 [0] SLEWFAST (0) Slew rate control - io_rw_32 io[6]; -} pads_qspi_hw_t; - -#define pads_qspi_hw ((pads_qspi_hw_t *)PADS_QSPI_BASE) -static_assert(sizeof (pads_qspi_hw_t) == 0x001c, ""); - -#endif // _HARDWARE_STRUCTS_PADS_QSPI_H - diff --git a/lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/padsbank0.h b/lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/padsbank0.h deleted file mode 100644 index cb14e792b7..0000000000 --- a/lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/padsbank0.h +++ /dev/null @@ -1,9 +0,0 @@ -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -// Support old header for compatibility (and if included, support old variable name) -#include "hardware/structs/pads_bank0.h" -#define padsbank0_hw pads_bank0_hw \ No newline at end of file diff --git a/lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/pio.h b/lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/pio.h deleted file mode 100644 index bceb14a71a..0000000000 --- a/lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/pio.h +++ /dev/null @@ -1,343 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _HARDWARE_STRUCTS_PIO_H -#define _HARDWARE_STRUCTS_PIO_H - -/** - * \file rp2040/pio.h - */ - -#include "hardware/address_mapped.h" -#include "hardware/regs/pio.h" - -// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_pio -// -// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) -// _REG_(x) will link to the corresponding register in hardware/regs/pio.h. -// -// Bit-field descriptions are of the form: -// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION - -typedef struct { - _REG_(PIO_SM0_CLKDIV_OFFSET) // PIO_SM0_CLKDIV - // Clock divisor register for state machine 0 + - // 0xffff0000 [31:16] INT (0x0001) Effective frequency is sysclk/(int + frac/256) - // 0x0000ff00 [15:8] FRAC (0x00) Fractional part of clock divisor - io_rw_32 clkdiv; - - _REG_(PIO_SM0_EXECCTRL_OFFSET) // PIO_SM0_EXECCTRL - // Execution/behavioural settings for state machine 0 - // 0x80000000 [31] EXEC_STALLED (0) If 1, an instruction written to SMx_INSTR is stalled,... - // 0x40000000 [30] SIDE_EN (0) If 1, the MSB of the Delay/Side-set instruction field is... - // 0x20000000 [29] SIDE_PINDIR (0) If 1, side-set data is asserted to pin directions,... - // 0x1f000000 [28:24] JMP_PIN (0x00) The GPIO number to use as condition for JMP PIN - // 0x00f80000 [23:19] OUT_EN_SEL (0x00) Which data bit to use for inline OUT enable - // 0x00040000 [18] INLINE_OUT_EN (0) If 1, use a bit of OUT data as an auxiliary write enable + - // 0x00020000 [17] OUT_STICKY (0) Continuously assert the most recent OUT/SET to the pins - // 0x0001f000 [16:12] WRAP_TOP (0x1f) After reaching this address, execution is wrapped to wrap_bottom - // 0x00000f80 [11:7] WRAP_BOTTOM (0x00) After reaching wrap_top, execution is wrapped to this address - // 0x00000010 [4] STATUS_SEL (0) Comparison used for the MOV x, STATUS instruction - // 0x0000000f [3:0] STATUS_N (0x0) Comparison level for the MOV x, STATUS instruction - io_rw_32 execctrl; - - _REG_(PIO_SM0_SHIFTCTRL_OFFSET) // PIO_SM0_SHIFTCTRL - // Control behaviour of the input/output shift registers for state machine 0 - // 0x80000000 [31] FJOIN_RX (0) When 1, RX FIFO steals the TX FIFO's storage, and... - // 0x40000000 [30] FJOIN_TX (0) When 1, TX FIFO steals the RX FIFO's storage, and... - // 0x3e000000 [29:25] PULL_THRESH (0x00) Number of bits shifted out of OSR before autopull, or... - // 0x01f00000 [24:20] PUSH_THRESH (0x00) Number of bits shifted into ISR before autopush, or... - // 0x00080000 [19] OUT_SHIFTDIR (1) 1 = shift out of output shift register to right - // 0x00040000 [18] IN_SHIFTDIR (1) 1 = shift input shift register to right (data enters from left) - // 0x00020000 [17] AUTOPULL (0) Pull automatically when the output shift register is emptied, i - // 0x00010000 [16] AUTOPUSH (0) Push automatically when the input shift register is filled, i - io_rw_32 shiftctrl; - - _REG_(PIO_SM0_ADDR_OFFSET) // PIO_SM0_ADDR - // Current instruction address of state machine 0 - // 0x0000001f [4:0] SM0_ADDR (0x00) - io_ro_32 addr; - - _REG_(PIO_SM0_INSTR_OFFSET) // PIO_SM0_INSTR - // Read to see the instruction currently addressed by state machine 0's program counter + - // 0x0000ffff [15:0] SM0_INSTR (-) - io_rw_32 instr; - - _REG_(PIO_SM0_PINCTRL_OFFSET) // PIO_SM0_PINCTRL - // State machine pin control - // 0xe0000000 [31:29] SIDESET_COUNT (0x0) The number of MSBs of the Delay/Side-set instruction... - // 0x1c000000 [28:26] SET_COUNT (0x5) The number of pins asserted by a SET - // 0x03f00000 [25:20] OUT_COUNT (0x00) The number of pins asserted by an OUT PINS, OUT PINDIRS... - // 0x000f8000 [19:15] IN_BASE (0x00) The pin which is mapped to the least-significant bit of... - // 0x00007c00 [14:10] SIDESET_BASE (0x00) The lowest-numbered pin that will be affected by a... - // 0x000003e0 [9:5] SET_BASE (0x00) The lowest-numbered pin that will be affected by a SET... - // 0x0000001f [4:0] OUT_BASE (0x00) The lowest-numbered pin that will be affected by an OUT... - io_rw_32 pinctrl; -} pio_sm_hw_t; - -typedef struct { - _REG_(PIO_IRQ0_INTE_OFFSET) // PIO_IRQ0_INTE - // Interrupt Enable for irq0 - // 0x00000800 [11] SM3 (0) - // 0x00000400 [10] SM2 (0) - // 0x00000200 [9] SM1 (0) - // 0x00000100 [8] SM0 (0) - // 0x00000080 [7] SM3_TXNFULL (0) - // 0x00000040 [6] SM2_TXNFULL (0) - // 0x00000020 [5] SM1_TXNFULL (0) - // 0x00000010 [4] SM0_TXNFULL (0) - // 0x00000008 [3] SM3_RXNEMPTY (0) - // 0x00000004 [2] SM2_RXNEMPTY (0) - // 0x00000002 [1] SM1_RXNEMPTY (0) - // 0x00000001 [0] SM0_RXNEMPTY (0) - io_rw_32 inte; - - _REG_(PIO_IRQ0_INTF_OFFSET) // PIO_IRQ0_INTF - // Interrupt Force for irq0 - // 0x00000800 [11] SM3 (0) - // 0x00000400 [10] SM2 (0) - // 0x00000200 [9] SM1 (0) - // 0x00000100 [8] SM0 (0) - // 0x00000080 [7] SM3_TXNFULL (0) - // 0x00000040 [6] SM2_TXNFULL (0) - // 0x00000020 [5] SM1_TXNFULL (0) - // 0x00000010 [4] SM0_TXNFULL (0) - // 0x00000008 [3] SM3_RXNEMPTY (0) - // 0x00000004 [2] SM2_RXNEMPTY (0) - // 0x00000002 [1] SM1_RXNEMPTY (0) - // 0x00000001 [0] SM0_RXNEMPTY (0) - io_rw_32 intf; - - _REG_(PIO_IRQ0_INTS_OFFSET) // PIO_IRQ0_INTS - // Interrupt status after masking & forcing for irq0 - // 0x00000800 [11] SM3 (0) - // 0x00000400 [10] SM2 (0) - // 0x00000200 [9] SM1 (0) - // 0x00000100 [8] SM0 (0) - // 0x00000080 [7] SM3_TXNFULL (0) - // 0x00000040 [6] SM2_TXNFULL (0) - // 0x00000020 [5] SM1_TXNFULL (0) - // 0x00000010 [4] SM0_TXNFULL (0) - // 0x00000008 [3] SM3_RXNEMPTY (0) - // 0x00000004 [2] SM2_RXNEMPTY (0) - // 0x00000002 [1] SM1_RXNEMPTY (0) - // 0x00000001 [0] SM0_RXNEMPTY (0) - io_ro_32 ints; -} pio_irq_ctrl_hw_t; - -typedef struct { - _REG_(PIO_CTRL_OFFSET) // PIO_CTRL - // PIO control register - // 0x00000f00 [11:8] CLKDIV_RESTART (0x0) Restart a state machine's clock divider from an initial... - // 0x000000f0 [7:4] SM_RESTART (0x0) Write 1 to instantly clear internal SM state which may... - // 0x0000000f [3:0] SM_ENABLE (0x0) Enable/disable each of the four state machines by... - io_rw_32 ctrl; - - _REG_(PIO_FSTAT_OFFSET) // PIO_FSTAT - // FIFO status register - // 0x0f000000 [27:24] TXEMPTY (0xf) State machine TX FIFO is empty - // 0x000f0000 [19:16] TXFULL (0x0) State machine TX FIFO is full - // 0x00000f00 [11:8] RXEMPTY (0xf) State machine RX FIFO is empty - // 0x0000000f [3:0] RXFULL (0x0) State machine RX FIFO is full - io_ro_32 fstat; - - _REG_(PIO_FDEBUG_OFFSET) // PIO_FDEBUG - // FIFO debug register - // 0x0f000000 [27:24] TXSTALL (0x0) State machine has stalled on empty TX FIFO during a... - // 0x000f0000 [19:16] TXOVER (0x0) TX FIFO overflow (i - // 0x00000f00 [11:8] RXUNDER (0x0) RX FIFO underflow (i - // 0x0000000f [3:0] RXSTALL (0x0) State machine has stalled on full RX FIFO during a... - io_rw_32 fdebug; - - _REG_(PIO_FLEVEL_OFFSET) // PIO_FLEVEL - // FIFO levels - // 0xf0000000 [31:28] RX3 (0x0) - // 0x0f000000 [27:24] TX3 (0x0) - // 0x00f00000 [23:20] RX2 (0x0) - // 0x000f0000 [19:16] TX2 (0x0) - // 0x0000f000 [15:12] RX1 (0x0) - // 0x00000f00 [11:8] TX1 (0x0) - // 0x000000f0 [7:4] RX0 (0x0) - // 0x0000000f [3:0] TX0 (0x0) - io_ro_32 flevel; - - // (Description copied from array index 0 register PIO_TXF0 applies similarly to other array indexes) - _REG_(PIO_TXF0_OFFSET) // PIO_TXF0 - // Direct write access to the TX FIFO for this state machine - // 0xffffffff [31:0] TXF0 (0x00000000) - io_wo_32 txf[4]; - - // (Description copied from array index 0 register PIO_RXF0 applies similarly to other array indexes) - _REG_(PIO_RXF0_OFFSET) // PIO_RXF0 - // Direct read access to the RX FIFO for this state machine - // 0xffffffff [31:0] RXF0 (-) - io_ro_32 rxf[4]; - - _REG_(PIO_IRQ_OFFSET) // PIO_IRQ - // State machine IRQ flags register - // 0x000000ff [7:0] IRQ (0x00) - io_rw_32 irq; - - _REG_(PIO_IRQ_FORCE_OFFSET) // PIO_IRQ_FORCE - // Writing a 1 to each of these bits will forcibly assert the corresponding IRQ - // 0x000000ff [7:0] IRQ_FORCE (0x00) - io_wo_32 irq_force; - - _REG_(PIO_INPUT_SYNC_BYPASS_OFFSET) // PIO_INPUT_SYNC_BYPASS - // There is a 2-flipflop synchronizer on each GPIO input, which protects PIO logic from metastabilities - // 0xffffffff [31:0] INPUT_SYNC_BYPASS (0x00000000) - io_rw_32 input_sync_bypass; - - _REG_(PIO_DBG_PADOUT_OFFSET) // PIO_DBG_PADOUT - // Read to sample the pad output values PIO is currently driving to the GPIOs - // 0xffffffff [31:0] DBG_PADOUT (0x00000000) - io_ro_32 dbg_padout; - - _REG_(PIO_DBG_PADOE_OFFSET) // PIO_DBG_PADOE - // Read to sample the pad output enables (direction) PIO is currently driving to the GPIOs - // 0xffffffff [31:0] DBG_PADOE (0x00000000) - io_ro_32 dbg_padoe; - - _REG_(PIO_DBG_CFGINFO_OFFSET) // PIO_DBG_CFGINFO - // The PIO hardware has some free parameters that may vary between chip products - // 0x003f0000 [21:16] IMEM_SIZE (-) The size of the instruction memory, measured in units of... - // 0x00000f00 [11:8] SM_COUNT (-) The number of state machines this PIO instance is equipped with - // 0x0000003f [5:0] FIFO_DEPTH (-) The depth of the state machine TX/RX FIFOs, measured in words - io_ro_32 dbg_cfginfo; - - // (Description copied from array index 0 register PIO_INSTR_MEM0 applies similarly to other array indexes) - _REG_(PIO_INSTR_MEM0_OFFSET) // PIO_INSTR_MEM0 - // Write-only access to instruction memory location 0 - // 0x0000ffff [15:0] INSTR_MEM0 (0x0000) - io_wo_32 instr_mem[32]; - - pio_sm_hw_t sm[4]; - - _REG_(PIO_INTR_OFFSET) // PIO_INTR - // Raw Interrupts - // 0x00000800 [11] SM3 (0) - // 0x00000400 [10] SM2 (0) - // 0x00000200 [9] SM1 (0) - // 0x00000100 [8] SM0 (0) - // 0x00000080 [7] SM3_TXNFULL (0) - // 0x00000040 [6] SM2_TXNFULL (0) - // 0x00000020 [5] SM1_TXNFULL (0) - // 0x00000010 [4] SM0_TXNFULL (0) - // 0x00000008 [3] SM3_RXNEMPTY (0) - // 0x00000004 [2] SM2_RXNEMPTY (0) - // 0x00000002 [1] SM1_RXNEMPTY (0) - // 0x00000001 [0] SM0_RXNEMPTY (0) - io_ro_32 intr; - - union { - struct { - _REG_(PIO_IRQ0_INTE_OFFSET) // PIO_IRQ0_INTE - // Interrupt Enable for irq0 - // 0x00000800 [11] SM3 (0) - // 0x00000400 [10] SM2 (0) - // 0x00000200 [9] SM1 (0) - // 0x00000100 [8] SM0 (0) - // 0x00000080 [7] SM3_TXNFULL (0) - // 0x00000040 [6] SM2_TXNFULL (0) - // 0x00000020 [5] SM1_TXNFULL (0) - // 0x00000010 [4] SM0_TXNFULL (0) - // 0x00000008 [3] SM3_RXNEMPTY (0) - // 0x00000004 [2] SM2_RXNEMPTY (0) - // 0x00000002 [1] SM1_RXNEMPTY (0) - // 0x00000001 [0] SM0_RXNEMPTY (0) - io_rw_32 inte0; - - _REG_(PIO_IRQ0_INTF_OFFSET) // PIO_IRQ0_INTF - // Interrupt Force for irq0 - // 0x00000800 [11] SM3 (0) - // 0x00000400 [10] SM2 (0) - // 0x00000200 [9] SM1 (0) - // 0x00000100 [8] SM0 (0) - // 0x00000080 [7] SM3_TXNFULL (0) - // 0x00000040 [6] SM2_TXNFULL (0) - // 0x00000020 [5] SM1_TXNFULL (0) - // 0x00000010 [4] SM0_TXNFULL (0) - // 0x00000008 [3] SM3_RXNEMPTY (0) - // 0x00000004 [2] SM2_RXNEMPTY (0) - // 0x00000002 [1] SM1_RXNEMPTY (0) - // 0x00000001 [0] SM0_RXNEMPTY (0) - io_rw_32 intf0; - - _REG_(PIO_IRQ0_INTS_OFFSET) // PIO_IRQ0_INTS - // Interrupt status after masking & forcing for irq0 - // 0x00000800 [11] SM3 (0) - // 0x00000400 [10] SM2 (0) - // 0x00000200 [9] SM1 (0) - // 0x00000100 [8] SM0 (0) - // 0x00000080 [7] SM3_TXNFULL (0) - // 0x00000040 [6] SM2_TXNFULL (0) - // 0x00000020 [5] SM1_TXNFULL (0) - // 0x00000010 [4] SM0_TXNFULL (0) - // 0x00000008 [3] SM3_RXNEMPTY (0) - // 0x00000004 [2] SM2_RXNEMPTY (0) - // 0x00000002 [1] SM1_RXNEMPTY (0) - // 0x00000001 [0] SM0_RXNEMPTY (0) - io_ro_32 ints0; - - _REG_(PIO_IRQ1_INTE_OFFSET) // PIO_IRQ1_INTE - // Interrupt Enable for irq1 - // 0x00000800 [11] SM3 (0) - // 0x00000400 [10] SM2 (0) - // 0x00000200 [9] SM1 (0) - // 0x00000100 [8] SM0 (0) - // 0x00000080 [7] SM3_TXNFULL (0) - // 0x00000040 [6] SM2_TXNFULL (0) - // 0x00000020 [5] SM1_TXNFULL (0) - // 0x00000010 [4] SM0_TXNFULL (0) - // 0x00000008 [3] SM3_RXNEMPTY (0) - // 0x00000004 [2] SM2_RXNEMPTY (0) - // 0x00000002 [1] SM1_RXNEMPTY (0) - // 0x00000001 [0] SM0_RXNEMPTY (0) - io_rw_32 inte1; - - _REG_(PIO_IRQ1_INTF_OFFSET) // PIO_IRQ1_INTF - // Interrupt Force for irq1 - // 0x00000800 [11] SM3 (0) - // 0x00000400 [10] SM2 (0) - // 0x00000200 [9] SM1 (0) - // 0x00000100 [8] SM0 (0) - // 0x00000080 [7] SM3_TXNFULL (0) - // 0x00000040 [6] SM2_TXNFULL (0) - // 0x00000020 [5] SM1_TXNFULL (0) - // 0x00000010 [4] SM0_TXNFULL (0) - // 0x00000008 [3] SM3_RXNEMPTY (0) - // 0x00000004 [2] SM2_RXNEMPTY (0) - // 0x00000002 [1] SM1_RXNEMPTY (0) - // 0x00000001 [0] SM0_RXNEMPTY (0) - io_rw_32 intf1; - - _REG_(PIO_IRQ1_INTS_OFFSET) // PIO_IRQ1_INTS - // Interrupt status after masking & forcing for irq1 - // 0x00000800 [11] SM3 (0) - // 0x00000400 [10] SM2 (0) - // 0x00000200 [9] SM1 (0) - // 0x00000100 [8] SM0 (0) - // 0x00000080 [7] SM3_TXNFULL (0) - // 0x00000040 [6] SM2_TXNFULL (0) - // 0x00000020 [5] SM1_TXNFULL (0) - // 0x00000010 [4] SM0_TXNFULL (0) - // 0x00000008 [3] SM3_RXNEMPTY (0) - // 0x00000004 [2] SM2_RXNEMPTY (0) - // 0x00000002 [1] SM1_RXNEMPTY (0) - // 0x00000001 [0] SM0_RXNEMPTY (0) - io_ro_32 ints1; - }; - pio_irq_ctrl_hw_t irq_ctrl[2]; - }; -} pio_hw_t; - -#define pio0_hw ((pio_hw_t *)PIO0_BASE) -#define pio1_hw ((pio_hw_t *)PIO1_BASE) -static_assert(sizeof (pio_hw_t) == 0x0144, ""); - -#endif // _HARDWARE_STRUCTS_PIO_H - diff --git a/lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/pll.h b/lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/pll.h deleted file mode 100644 index 7d3ccc82b5..0000000000 --- a/lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/pll.h +++ /dev/null @@ -1,61 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _HARDWARE_STRUCTS_PLL_H -#define _HARDWARE_STRUCTS_PLL_H - -/** - * \file rp2040/pll.h - */ - -#include "hardware/address_mapped.h" -#include "hardware/regs/pll.h" - -// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_pll -// -// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) -// _REG_(x) will link to the corresponding register in hardware/regs/pll.h. -// -// Bit-field descriptions are of the form: -// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION - -/// \tag::pll_hw[] -typedef struct { - _REG_(PLL_CS_OFFSET) // PLL_CS - // Control and Status - // 0x80000000 [31] LOCK (0) PLL is locked - // 0x00000100 [8] BYPASS (0) Passes the reference clock to the output instead of the... - // 0x0000003f [5:0] REFDIV (0x01) Divides the PLL input reference clock - io_rw_32 cs; - - _REG_(PLL_PWR_OFFSET) // PLL_PWR - // Controls the PLL power modes - // 0x00000020 [5] VCOPD (1) PLL VCO powerdown + - // 0x00000008 [3] POSTDIVPD (1) PLL post divider powerdown + - // 0x00000004 [2] DSMPD (1) PLL DSM powerdown + - // 0x00000001 [0] PD (1) PLL powerdown + - io_rw_32 pwr; - - _REG_(PLL_FBDIV_INT_OFFSET) // PLL_FBDIV_INT - // Feedback divisor - // 0x00000fff [11:0] FBDIV_INT (0x000) see ctrl reg description for constraints - io_rw_32 fbdiv_int; - - _REG_(PLL_PRIM_OFFSET) // PLL_PRIM - // Controls the PLL post dividers for the primary output - // 0x00070000 [18:16] POSTDIV1 (0x7) divide by 1-7 - // 0x00007000 [14:12] POSTDIV2 (0x7) divide by 1-7 - io_rw_32 prim; -} pll_hw_t; -/// \end::pll_hw[] - -#define pll_sys_hw ((pll_hw_t *)PLL_SYS_BASE) -#define pll_usb_hw ((pll_hw_t *)PLL_USB_BASE) -static_assert(sizeof (pll_hw_t) == 0x0010, ""); - -#endif // _HARDWARE_STRUCTS_PLL_H - diff --git a/lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/psm.h b/lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/psm.h deleted file mode 100644 index 74ccaf32ad..0000000000 --- a/lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/psm.h +++ /dev/null @@ -1,116 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _HARDWARE_STRUCTS_PSM_H -#define _HARDWARE_STRUCTS_PSM_H - -/** - * \file rp2040/psm.h - */ - -#include "hardware/address_mapped.h" -#include "hardware/regs/psm.h" - -// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_psm -// -// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) -// _REG_(x) will link to the corresponding register in hardware/regs/psm.h. -// -// Bit-field descriptions are of the form: -// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION - -typedef struct { - _REG_(PSM_FRCE_ON_OFFSET) // PSM_FRCE_ON - // Force block out of reset (i - // 0x00010000 [16] PROC1 (0) - // 0x00008000 [15] PROC0 (0) - // 0x00004000 [14] SIO (0) - // 0x00002000 [13] VREG_AND_CHIP_RESET (0) - // 0x00001000 [12] XIP (0) - // 0x00000800 [11] SRAM5 (0) - // 0x00000400 [10] SRAM4 (0) - // 0x00000200 [9] SRAM3 (0) - // 0x00000100 [8] SRAM2 (0) - // 0x00000080 [7] SRAM1 (0) - // 0x00000040 [6] SRAM0 (0) - // 0x00000020 [5] ROM (0) - // 0x00000010 [4] BUSFABRIC (0) - // 0x00000008 [3] RESETS (0) - // 0x00000004 [2] CLOCKS (0) - // 0x00000002 [1] XOSC (0) - // 0x00000001 [0] ROSC (0) - io_rw_32 frce_on; - - _REG_(PSM_FRCE_OFF_OFFSET) // PSM_FRCE_OFF - // Force into reset (i - // 0x00010000 [16] PROC1 (0) - // 0x00008000 [15] PROC0 (0) - // 0x00004000 [14] SIO (0) - // 0x00002000 [13] VREG_AND_CHIP_RESET (0) - // 0x00001000 [12] XIP (0) - // 0x00000800 [11] SRAM5 (0) - // 0x00000400 [10] SRAM4 (0) - // 0x00000200 [9] SRAM3 (0) - // 0x00000100 [8] SRAM2 (0) - // 0x00000080 [7] SRAM1 (0) - // 0x00000040 [6] SRAM0 (0) - // 0x00000020 [5] ROM (0) - // 0x00000010 [4] BUSFABRIC (0) - // 0x00000008 [3] RESETS (0) - // 0x00000004 [2] CLOCKS (0) - // 0x00000002 [1] XOSC (0) - // 0x00000001 [0] ROSC (0) - io_rw_32 frce_off; - - _REG_(PSM_WDSEL_OFFSET) // PSM_WDSEL - // Set to 1 if this peripheral should be reset when the watchdog fires - // 0x00010000 [16] PROC1 (0) - // 0x00008000 [15] PROC0 (0) - // 0x00004000 [14] SIO (0) - // 0x00002000 [13] VREG_AND_CHIP_RESET (0) - // 0x00001000 [12] XIP (0) - // 0x00000800 [11] SRAM5 (0) - // 0x00000400 [10] SRAM4 (0) - // 0x00000200 [9] SRAM3 (0) - // 0x00000100 [8] SRAM2 (0) - // 0x00000080 [7] SRAM1 (0) - // 0x00000040 [6] SRAM0 (0) - // 0x00000020 [5] ROM (0) - // 0x00000010 [4] BUSFABRIC (0) - // 0x00000008 [3] RESETS (0) - // 0x00000004 [2] CLOCKS (0) - // 0x00000002 [1] XOSC (0) - // 0x00000001 [0] ROSC (0) - io_rw_32 wdsel; - - _REG_(PSM_DONE_OFFSET) // PSM_DONE - // Indicates the peripheral's registers are ready to access - // 0x00010000 [16] PROC1 (0) - // 0x00008000 [15] PROC0 (0) - // 0x00004000 [14] SIO (0) - // 0x00002000 [13] VREG_AND_CHIP_RESET (0) - // 0x00001000 [12] XIP (0) - // 0x00000800 [11] SRAM5 (0) - // 0x00000400 [10] SRAM4 (0) - // 0x00000200 [9] SRAM3 (0) - // 0x00000100 [8] SRAM2 (0) - // 0x00000080 [7] SRAM1 (0) - // 0x00000040 [6] SRAM0 (0) - // 0x00000020 [5] ROM (0) - // 0x00000010 [4] BUSFABRIC (0) - // 0x00000008 [3] RESETS (0) - // 0x00000004 [2] CLOCKS (0) - // 0x00000002 [1] XOSC (0) - // 0x00000001 [0] ROSC (0) - io_ro_32 done; -} psm_hw_t; - -#define psm_hw ((psm_hw_t *)PSM_BASE) -static_assert(sizeof (psm_hw_t) == 0x0010, ""); - -#endif // _HARDWARE_STRUCTS_PSM_H - diff --git a/lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/pwm.h b/lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/pwm.h deleted file mode 100644 index 3eedee4d9f..0000000000 --- a/lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/pwm.h +++ /dev/null @@ -1,172 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _HARDWARE_STRUCTS_PWM_H -#define _HARDWARE_STRUCTS_PWM_H - -/** - * \file rp2040/pwm.h - */ - -#include "hardware/address_mapped.h" -#include "hardware/regs/pwm.h" - -// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_pwm -// -// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) -// _REG_(x) will link to the corresponding register in hardware/regs/pwm.h. -// -// Bit-field descriptions are of the form: -// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION - -typedef struct { - _REG_(PWM_CH0_CSR_OFFSET) // PWM_CH0_CSR - // Control and status register - // 0x00000080 [7] PH_ADV (0) Advance the phase of the counter by 1 count, while it is running - // 0x00000040 [6] PH_RET (0) Retard the phase of the counter by 1 count, while it is running - // 0x00000030 [5:4] DIVMODE (0x0) - // 0x00000008 [3] B_INV (0) Invert output B - // 0x00000004 [2] A_INV (0) Invert output A - // 0x00000002 [1] PH_CORRECT (0) 1: Enable phase-correct modulation - // 0x00000001 [0] EN (0) Enable the PWM channel - io_rw_32 csr; - - _REG_(PWM_CH0_DIV_OFFSET) // PWM_CH0_DIV - // INT and FRAC form a fixed-point fractional number - // 0x00000ff0 [11:4] INT (0x01) - // 0x0000000f [3:0] FRAC (0x0) - io_rw_32 div; - - _REG_(PWM_CH0_CTR_OFFSET) // PWM_CH0_CTR - // Direct access to the PWM counter - // 0x0000ffff [15:0] CH0_CTR (0x0000) - io_rw_32 ctr; - - _REG_(PWM_CH0_CC_OFFSET) // PWM_CH0_CC - // Counter compare values - // 0xffff0000 [31:16] B (0x0000) - // 0x0000ffff [15:0] A (0x0000) - io_rw_32 cc; - - _REG_(PWM_CH0_TOP_OFFSET) // PWM_CH0_TOP - // Counter wrap value - // 0x0000ffff [15:0] CH0_TOP (0xffff) - io_rw_32 top; -} pwm_slice_hw_t; - -typedef struct { - _REG_(PWM_INTE_OFFSET) // PWM_INTE - // Interrupt Enable - // 0x00000080 [7] CH7 (0) - // 0x00000040 [6] CH6 (0) - // 0x00000020 [5] CH5 (0) - // 0x00000010 [4] CH4 (0) - // 0x00000008 [3] CH3 (0) - // 0x00000004 [2] CH2 (0) - // 0x00000002 [1] CH1 (0) - // 0x00000001 [0] CH0 (0) - io_rw_32 inte; - - _REG_(PWM_INTF_OFFSET) // PWM_INTF - // Interrupt Force - // 0x00000080 [7] CH7 (0) - // 0x00000040 [6] CH6 (0) - // 0x00000020 [5] CH5 (0) - // 0x00000010 [4] CH4 (0) - // 0x00000008 [3] CH3 (0) - // 0x00000004 [2] CH2 (0) - // 0x00000002 [1] CH1 (0) - // 0x00000001 [0] CH0 (0) - io_rw_32 intf; - - _REG_(PWM_INTS_OFFSET) // PWM_INTS - // Interrupt status after masking & forcing - // 0x00000080 [7] CH7 (0) - // 0x00000040 [6] CH6 (0) - // 0x00000020 [5] CH5 (0) - // 0x00000010 [4] CH4 (0) - // 0x00000008 [3] CH3 (0) - // 0x00000004 [2] CH2 (0) - // 0x00000002 [1] CH1 (0) - // 0x00000001 [0] CH0 (0) - io_ro_32 ints; -} pwm_irq_ctrl_hw_t; - -typedef struct { - pwm_slice_hw_t slice[8]; - - _REG_(PWM_EN_OFFSET) // PWM_EN - // This register aliases the CSR_EN bits for all channels - // 0x00000080 [7] CH7 (0) - // 0x00000040 [6] CH6 (0) - // 0x00000020 [5] CH5 (0) - // 0x00000010 [4] CH4 (0) - // 0x00000008 [3] CH3 (0) - // 0x00000004 [2] CH2 (0) - // 0x00000002 [1] CH1 (0) - // 0x00000001 [0] CH0 (0) - io_rw_32 en; - - _REG_(PWM_INTR_OFFSET) // PWM_INTR - // Raw Interrupts - // 0x00000080 [7] CH7 (0) - // 0x00000040 [6] CH6 (0) - // 0x00000020 [5] CH5 (0) - // 0x00000010 [4] CH4 (0) - // 0x00000008 [3] CH3 (0) - // 0x00000004 [2] CH2 (0) - // 0x00000002 [1] CH1 (0) - // 0x00000001 [0] CH0 (0) - io_rw_32 intr; - - union { - struct { - _REG_(PWM_INTE_OFFSET) // PWM_INTE - // Interrupt Enable - // 0x00000080 [7] CH7 (0) - // 0x00000040 [6] CH6 (0) - // 0x00000020 [5] CH5 (0) - // 0x00000010 [4] CH4 (0) - // 0x00000008 [3] CH3 (0) - // 0x00000004 [2] CH2 (0) - // 0x00000002 [1] CH1 (0) - // 0x00000001 [0] CH0 (0) - io_rw_32 inte; - - _REG_(PWM_INTF_OFFSET) // PWM_INTF - // Interrupt Force - // 0x00000080 [7] CH7 (0) - // 0x00000040 [6] CH6 (0) - // 0x00000020 [5] CH5 (0) - // 0x00000010 [4] CH4 (0) - // 0x00000008 [3] CH3 (0) - // 0x00000004 [2] CH2 (0) - // 0x00000002 [1] CH1 (0) - // 0x00000001 [0] CH0 (0) - io_rw_32 intf; - - _REG_(PWM_INTS_OFFSET) // PWM_INTS - // Interrupt status after masking & forcing - // 0x00000080 [7] CH7 (0) - // 0x00000040 [6] CH6 (0) - // 0x00000020 [5] CH5 (0) - // 0x00000010 [4] CH4 (0) - // 0x00000008 [3] CH3 (0) - // 0x00000004 [2] CH2 (0) - // 0x00000002 [1] CH1 (0) - // 0x00000001 [0] CH0 (0) - io_rw_32 ints; - }; - pwm_irq_ctrl_hw_t irq_ctrl[1]; - }; -} pwm_hw_t; - -#define pwm_hw ((pwm_hw_t *)PWM_BASE) -static_assert(sizeof (pwm_hw_t) == 0x00b4, ""); - -#endif // _HARDWARE_STRUCTS_PWM_H - diff --git a/lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/resets.h b/lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/resets.h deleted file mode 100644 index ca3a62970b..0000000000 --- a/lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/resets.h +++ /dev/null @@ -1,153 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _HARDWARE_STRUCTS_RESETS_H -#define _HARDWARE_STRUCTS_RESETS_H - -/** - * \file rp2040/resets.h - */ - -#include "hardware/address_mapped.h" -#include "hardware/regs/resets.h" - -// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_resets -// -// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) -// _REG_(x) will link to the corresponding register in hardware/regs/resets.h. -// -// Bit-field descriptions are of the form: -// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION - -/** \brief Resettable component numbers on RP2040 (used as typedef \ref reset_num_t) - * \ingroup hardware_resets - */ -typedef enum reset_num_rp2040 { - RESET_ADC = 0, ///< Select ADC to be reset - RESET_BUSCTRL = 1, ///< Select BUSCTRL to be reset - RESET_DMA = 2, ///< Select DMA to be reset - RESET_I2C0 = 3, ///< Select I2C0 to be reset - RESET_I2C1 = 4, ///< Select I2C1 to be reset - RESET_IO_BANK0 = 5, ///< Select IO_BANK0 to be reset - RESET_IO_QSPI = 6, ///< Select IO_QSPI to be reset - RESET_JTAG = 7, ///< Select JTAG to be reset - RESET_PADS_BANK0 = 8, ///< Select PADS_BANK0 to be reset - RESET_PADS_QSPI = 9, ///< Select PADS_QSPI to be reset - RESET_PIO0 = 10, ///< Select PIO0 to be reset - RESET_PIO1 = 11, ///< Select PIO1 to be reset - RESET_PLL_SYS = 12, ///< Select PLL_SYS to be reset - RESET_PLL_USB = 13, ///< Select PLL_USB to be reset - RESET_PWM = 14, ///< Select PWM to be reset - RESET_RTC = 15, ///< Select RTC to be reset - RESET_SPI0 = 16, ///< Select SPI0 to be reset - RESET_SPI1 = 17, ///< Select SPI1 to be reset - RESET_SYSCFG = 18, ///< Select SYSCFG to be reset - RESET_SYSINFO = 19, ///< Select SYSINFO to be reset - RESET_TBMAN = 20, ///< Select TBMAN to be reset - RESET_TIMER = 21, ///< Select TIMER to be reset - RESET_UART0 = 22, ///< Select UART0 to be reset - RESET_UART1 = 23, ///< Select UART1 to be reset - RESET_USBCTRL = 24, ///< Select USBCTRL to be reset - RESET_COUNT -} reset_num_t; - -/// \tag::resets_hw[] -typedef struct { - _REG_(RESETS_RESET_OFFSET) // RESETS_RESET - // Reset control. - // 0x01000000 [24] USBCTRL (1) - // 0x00800000 [23] UART1 (1) - // 0x00400000 [22] UART0 (1) - // 0x00200000 [21] TIMER (1) - // 0x00100000 [20] TBMAN (1) - // 0x00080000 [19] SYSINFO (1) - // 0x00040000 [18] SYSCFG (1) - // 0x00020000 [17] SPI1 (1) - // 0x00010000 [16] SPI0 (1) - // 0x00008000 [15] RTC (1) - // 0x00004000 [14] PWM (1) - // 0x00002000 [13] PLL_USB (1) - // 0x00001000 [12] PLL_SYS (1) - // 0x00000800 [11] PIO1 (1) - // 0x00000400 [10] PIO0 (1) - // 0x00000200 [9] PADS_QSPI (1) - // 0x00000100 [8] PADS_BANK0 (1) - // 0x00000080 [7] JTAG (1) - // 0x00000040 [6] IO_QSPI (1) - // 0x00000020 [5] IO_BANK0 (1) - // 0x00000010 [4] I2C1 (1) - // 0x00000008 [3] I2C0 (1) - // 0x00000004 [2] DMA (1) - // 0x00000002 [1] BUSCTRL (1) - // 0x00000001 [0] ADC (1) - io_rw_32 reset; - - _REG_(RESETS_WDSEL_OFFSET) // RESETS_WDSEL - // Watchdog select. - // 0x01000000 [24] USBCTRL (0) - // 0x00800000 [23] UART1 (0) - // 0x00400000 [22] UART0 (0) - // 0x00200000 [21] TIMER (0) - // 0x00100000 [20] TBMAN (0) - // 0x00080000 [19] SYSINFO (0) - // 0x00040000 [18] SYSCFG (0) - // 0x00020000 [17] SPI1 (0) - // 0x00010000 [16] SPI0 (0) - // 0x00008000 [15] RTC (0) - // 0x00004000 [14] PWM (0) - // 0x00002000 [13] PLL_USB (0) - // 0x00001000 [12] PLL_SYS (0) - // 0x00000800 [11] PIO1 (0) - // 0x00000400 [10] PIO0 (0) - // 0x00000200 [9] PADS_QSPI (0) - // 0x00000100 [8] PADS_BANK0 (0) - // 0x00000080 [7] JTAG (0) - // 0x00000040 [6] IO_QSPI (0) - // 0x00000020 [5] IO_BANK0 (0) - // 0x00000010 [4] I2C1 (0) - // 0x00000008 [3] I2C0 (0) - // 0x00000004 [2] DMA (0) - // 0x00000002 [1] BUSCTRL (0) - // 0x00000001 [0] ADC (0) - io_rw_32 wdsel; - - _REG_(RESETS_RESET_DONE_OFFSET) // RESETS_RESET_DONE - // Reset done. - // 0x01000000 [24] USBCTRL (0) - // 0x00800000 [23] UART1 (0) - // 0x00400000 [22] UART0 (0) - // 0x00200000 [21] TIMER (0) - // 0x00100000 [20] TBMAN (0) - // 0x00080000 [19] SYSINFO (0) - // 0x00040000 [18] SYSCFG (0) - // 0x00020000 [17] SPI1 (0) - // 0x00010000 [16] SPI0 (0) - // 0x00008000 [15] RTC (0) - // 0x00004000 [14] PWM (0) - // 0x00002000 [13] PLL_USB (0) - // 0x00001000 [12] PLL_SYS (0) - // 0x00000800 [11] PIO1 (0) - // 0x00000400 [10] PIO0 (0) - // 0x00000200 [9] PADS_QSPI (0) - // 0x00000100 [8] PADS_BANK0 (0) - // 0x00000080 [7] JTAG (0) - // 0x00000040 [6] IO_QSPI (0) - // 0x00000020 [5] IO_BANK0 (0) - // 0x00000010 [4] I2C1 (0) - // 0x00000008 [3] I2C0 (0) - // 0x00000004 [2] DMA (0) - // 0x00000002 [1] BUSCTRL (0) - // 0x00000001 [0] ADC (0) - io_ro_32 reset_done; -} resets_hw_t; -/// \end::resets_hw[] - -#define resets_hw ((resets_hw_t *)RESETS_BASE) -static_assert(sizeof (resets_hw_t) == 0x000c, ""); - -#endif // _HARDWARE_STRUCTS_RESETS_H - diff --git a/lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/rosc.h b/lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/rosc.h deleted file mode 100644 index 2bc82007b0..0000000000 --- a/lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/rosc.h +++ /dev/null @@ -1,92 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _HARDWARE_STRUCTS_ROSC_H -#define _HARDWARE_STRUCTS_ROSC_H - -/** - * \file rp2040/rosc.h - */ - -#include "hardware/address_mapped.h" -#include "hardware/regs/rosc.h" - -// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_rosc -// -// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) -// _REG_(x) will link to the corresponding register in hardware/regs/rosc.h. -// -// Bit-field descriptions are of the form: -// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION - -typedef struct { - _REG_(ROSC_CTRL_OFFSET) // ROSC_CTRL - // Ring Oscillator control - // 0x00fff000 [23:12] ENABLE (-) On power-up this field is initialised to ENABLE + - // 0x00000fff [11:0] FREQ_RANGE (0xaa0) Controls the number of delay stages in the ROSC ring + - io_rw_32 ctrl; - - _REG_(ROSC_FREQA_OFFSET) // ROSC_FREQA - // Ring Oscillator frequency control A - // 0xffff0000 [31:16] PASSWD (0x0000) Set to 0x9696 to apply the settings + - // 0x00007000 [14:12] DS3 (0x0) Stage 3 drive strength - // 0x00000700 [10:8] DS2 (0x0) Stage 2 drive strength - // 0x00000070 [6:4] DS1 (0x0) Stage 1 drive strength - // 0x00000007 [2:0] DS0 (0x0) Stage 0 drive strength - io_rw_32 freqa; - - _REG_(ROSC_FREQB_OFFSET) // ROSC_FREQB - // Ring Oscillator frequency control B - // 0xffff0000 [31:16] PASSWD (0x0000) Set to 0x9696 to apply the settings + - // 0x00007000 [14:12] DS7 (0x0) Stage 7 drive strength - // 0x00000700 [10:8] DS6 (0x0) Stage 6 drive strength - // 0x00000070 [6:4] DS5 (0x0) Stage 5 drive strength - // 0x00000007 [2:0] DS4 (0x0) Stage 4 drive strength - io_rw_32 freqb; - - _REG_(ROSC_DORMANT_OFFSET) // ROSC_DORMANT - // Ring Oscillator pause control - // 0xffffffff [31:0] DORMANT (-) This is used to save power by pausing the ROSC + - io_rw_32 dormant; - - _REG_(ROSC_DIV_OFFSET) // ROSC_DIV - // Controls the output divider - // 0x00000fff [11:0] DIV (-) set to 0xaa0 + div where + - io_rw_32 div; - - _REG_(ROSC_PHASE_OFFSET) // ROSC_PHASE - // Controls the phase shifted output - // 0x00000ff0 [11:4] PASSWD (0x00) set to 0xaa + - // 0x00000008 [3] ENABLE (1) enable the phase-shifted output + - // 0x00000004 [2] FLIP (0) invert the phase-shifted output + - // 0x00000003 [1:0] SHIFT (0x0) phase shift the phase-shifted output by SHIFT input clocks + - io_rw_32 phase; - - _REG_(ROSC_STATUS_OFFSET) // ROSC_STATUS - // Ring Oscillator Status - // 0x80000000 [31] STABLE (0) Oscillator is running and stable - // 0x01000000 [24] BADWRITE (0) An invalid value has been written to CTRL_ENABLE or... - // 0x00010000 [16] DIV_RUNNING (-) post-divider is running + - // 0x00001000 [12] ENABLED (-) Oscillator is enabled but not necessarily running and stable + - io_rw_32 status; - - _REG_(ROSC_RANDOMBIT_OFFSET) // ROSC_RANDOMBIT - // Returns a 1 bit random value - // 0x00000001 [0] RANDOMBIT (1) - io_ro_32 randombit; - - _REG_(ROSC_COUNT_OFFSET) // ROSC_COUNT - // A down counter running at the ROSC frequency which counts to zero and stops. - // 0x000000ff [7:0] COUNT (0x00) - io_rw_32 count; -} rosc_hw_t; - -#define rosc_hw ((rosc_hw_t *)ROSC_BASE) -static_assert(sizeof (rosc_hw_t) == 0x0024, ""); - -#endif // _HARDWARE_STRUCTS_ROSC_H - diff --git a/lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/rtc.h b/lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/rtc.h deleted file mode 100644 index 6f35b682a1..0000000000 --- a/lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/rtc.h +++ /dev/null @@ -1,119 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _HARDWARE_STRUCTS_RTC_H -#define _HARDWARE_STRUCTS_RTC_H - -/** - * \file rp2040/rtc.h - */ - -#include "hardware/address_mapped.h" -#include "hardware/regs/rtc.h" - -// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_rtc -// -// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) -// _REG_(x) will link to the corresponding register in hardware/regs/rtc.h. -// -// Bit-field descriptions are of the form: -// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION - -typedef struct { - _REG_(RTC_CLKDIV_M1_OFFSET) // RTC_CLKDIV_M1 - // Divider minus 1 for the 1 second counter - // 0x0000ffff [15:0] CLKDIV_M1 (0x0000) - io_rw_32 clkdiv_m1; - - _REG_(RTC_SETUP_0_OFFSET) // RTC_SETUP_0 - // RTC setup register 0 - // 0x00fff000 [23:12] YEAR (0x000) Year - // 0x00000f00 [11:8] MONTH (0x0) Month (1 - // 0x0000001f [4:0] DAY (0x00) Day of the month (1 - io_rw_32 setup_0; - - _REG_(RTC_SETUP_1_OFFSET) // RTC_SETUP_1 - // RTC setup register 1 - // 0x07000000 [26:24] DOTW (0x0) Day of the week: 1-Monday - // 0x001f0000 [20:16] HOUR (0x00) Hours - // 0x00003f00 [13:8] MIN (0x00) Minutes - // 0x0000003f [5:0] SEC (0x00) Seconds - io_rw_32 setup_1; - - _REG_(RTC_CTRL_OFFSET) // RTC_CTRL - // RTC Control and status - // 0x00000100 [8] FORCE_NOTLEAPYEAR (0) If set, leapyear is forced off - // 0x00000010 [4] LOAD (0) Load RTC - // 0x00000002 [1] RTC_ACTIVE (-) RTC enabled (running) - // 0x00000001 [0] RTC_ENABLE (0) Enable RTC - io_rw_32 ctrl; - - _REG_(RTC_IRQ_SETUP_0_OFFSET) // RTC_IRQ_SETUP_0 - // Interrupt setup register 0 - // 0x20000000 [29] MATCH_ACTIVE (-) - // 0x10000000 [28] MATCH_ENA (0) Global match enable - // 0x04000000 [26] YEAR_ENA (0) Enable year matching - // 0x02000000 [25] MONTH_ENA (0) Enable month matching - // 0x01000000 [24] DAY_ENA (0) Enable day matching - // 0x00fff000 [23:12] YEAR (0x000) Year - // 0x00000f00 [11:8] MONTH (0x0) Month (1 - // 0x0000001f [4:0] DAY (0x00) Day of the month (1 - io_rw_32 irq_setup_0; - - _REG_(RTC_IRQ_SETUP_1_OFFSET) // RTC_IRQ_SETUP_1 - // Interrupt setup register 1 - // 0x80000000 [31] DOTW_ENA (0) Enable day of the week matching - // 0x40000000 [30] HOUR_ENA (0) Enable hour matching - // 0x20000000 [29] MIN_ENA (0) Enable minute matching - // 0x10000000 [28] SEC_ENA (0) Enable second matching - // 0x07000000 [26:24] DOTW (0x0) Day of the week - // 0x001f0000 [20:16] HOUR (0x00) Hours - // 0x00003f00 [13:8] MIN (0x00) Minutes - // 0x0000003f [5:0] SEC (0x00) Seconds - io_rw_32 irq_setup_1; - - _REG_(RTC_RTC_1_OFFSET) // RTC_RTC_1 - // RTC register 1 - // 0x00fff000 [23:12] YEAR (-) Year - // 0x00000f00 [11:8] MONTH (-) Month (1 - // 0x0000001f [4:0] DAY (-) Day of the month (1 - io_ro_32 rtc_1; - - _REG_(RTC_RTC_0_OFFSET) // RTC_RTC_0 - // RTC register 0 + - // 0x07000000 [26:24] DOTW (-) Day of the week - // 0x001f0000 [20:16] HOUR (-) Hours - // 0x00003f00 [13:8] MIN (-) Minutes - // 0x0000003f [5:0] SEC (-) Seconds - io_ro_32 rtc_0; - - _REG_(RTC_INTR_OFFSET) // RTC_INTR - // Raw Interrupts - // 0x00000001 [0] RTC (0) - io_ro_32 intr; - - _REG_(RTC_INTE_OFFSET) // RTC_INTE - // Interrupt Enable - // 0x00000001 [0] RTC (0) - io_rw_32 inte; - - _REG_(RTC_INTF_OFFSET) // RTC_INTF - // Interrupt Force - // 0x00000001 [0] RTC (0) - io_rw_32 intf; - - _REG_(RTC_INTS_OFFSET) // RTC_INTS - // Interrupt status after masking & forcing - // 0x00000001 [0] RTC (0) - io_ro_32 ints; -} rtc_hw_t; - -#define rtc_hw ((rtc_hw_t *)RTC_BASE) -static_assert(sizeof (rtc_hw_t) == 0x0030, ""); - -#endif // _HARDWARE_STRUCTS_RTC_H - diff --git a/lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/scb.h b/lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/scb.h deleted file mode 100644 index d4af748008..0000000000 --- a/lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/scb.h +++ /dev/null @@ -1,74 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _HARDWARE_STRUCTS_SCB_H -#define _HARDWARE_STRUCTS_SCB_H - -/** - * \file rp2040/scb.h - */ - -#include "hardware/address_mapped.h" -#include "hardware/regs/m0plus.h" - -// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_m0plus -// -// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) -// _REG_(x) will link to the corresponding register in hardware/regs/m0plus.h. -// -// Bit-field descriptions are of the form: -// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION - -typedef struct { - _REG_(M0PLUS_CPUID_OFFSET) // M0PLUS_CPUID - // CPUID Base Register - // 0xff000000 [31:24] IMPLEMENTER (0x41) Implementor code: 0x41 = ARM - // 0x00f00000 [23:20] VARIANT (0x0) Major revision number n in the rnpm revision status: + - // 0x000f0000 [19:16] ARCHITECTURE (0xc) Constant that defines the architecture of the processor: + - // 0x0000fff0 [15:4] PARTNO (0xc60) Number of processor within family: 0xC60 = Cortex-M0+ - // 0x0000000f [3:0] REVISION (0x1) Minor revision number m in the rnpm revision status: + - io_ro_32 cpuid; - - _REG_(M0PLUS_ICSR_OFFSET) // M0PLUS_ICSR - // Interrupt Control and State Register - // 0x80000000 [31] NMIPENDSET (0) Setting this bit will activate an NMI - // 0x10000000 [28] PENDSVSET (0) PendSV set-pending bit - // 0x08000000 [27] PENDSVCLR (0) PendSV clear-pending bit - // 0x04000000 [26] PENDSTSET (0) SysTick exception set-pending bit - // 0x02000000 [25] PENDSTCLR (0) SysTick exception clear-pending bit - // 0x00800000 [23] ISRPREEMPT (0) The system can only access this bit when the core is halted - // 0x00400000 [22] ISRPENDING (0) External interrupt pending flag - // 0x001ff000 [20:12] VECTPENDING (0x000) Indicates the exception number for the highest priority... - // 0x000001ff [8:0] VECTACTIVE (0x000) Active exception number field - io_rw_32 icsr; - - _REG_(M0PLUS_VTOR_OFFSET) // M0PLUS_VTOR - // Vector Table Offset Register - // 0xffffff00 [31:8] TBLOFF (0x000000) Bits [31:8] of the indicate the vector table offset address - io_rw_32 vtor; - - _REG_(M0PLUS_AIRCR_OFFSET) // M0PLUS_AIRCR - // Application Interrupt and Reset Control Register - // 0xffff0000 [31:16] VECTKEY (0x0000) Register key: + - // 0x00008000 [15] ENDIANESS (0) Data endianness implemented: + - // 0x00000004 [2] SYSRESETREQ (0) Writing 1 to this bit causes the SYSRESETREQ signal to... - // 0x00000002 [1] VECTCLRACTIVE (0) Clears all active state information for fixed and... - io_rw_32 aircr; - - _REG_(M0PLUS_SCR_OFFSET) // M0PLUS_SCR - // System Control Register - // 0x00000010 [4] SEVONPEND (0) Send Event on Pending bit: + - // 0x00000004 [2] SLEEPDEEP (0) Controls whether the processor uses sleep or deep sleep... - // 0x00000002 [1] SLEEPONEXIT (0) Indicates sleep-on-exit when returning from Handler mode... - io_rw_32 scr; -} armv6m_scb_hw_t; - -#define scb_hw ((armv6m_scb_hw_t *)(PPB_BASE + M0PLUS_CPUID_OFFSET)) -static_assert(sizeof (armv6m_scb_hw_t) == 0x0014, ""); - -#endif // _HARDWARE_STRUCTS_SCB_H - diff --git a/lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/sio.h b/lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/sio.h deleted file mode 100644 index 412a7d868d..0000000000 --- a/lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/sio.h +++ /dev/null @@ -1,200 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _HARDWARE_STRUCTS_SIO_H -#define _HARDWARE_STRUCTS_SIO_H - -/** - * \file rp2040/sio.h - */ - -#include "hardware/address_mapped.h" -#include "hardware/regs/sio.h" -#include "hardware/structs/interp.h" - -// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_sio -// -// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) -// _REG_(x) will link to the corresponding register in hardware/regs/sio.h. -// -// Bit-field descriptions are of the form: -// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION - - -typedef struct { - _REG_(SIO_CPUID_OFFSET) // SIO_CPUID - // Processor core identifier - // 0xffffffff [31:0] CPUID (-) Value is 0 when read from processor core 0, and 1 when... - io_ro_32 cpuid; - - _REG_(SIO_GPIO_IN_OFFSET) // SIO_GPIO_IN - // Input value for GPIO pins - // 0x3fffffff [29:0] GPIO_IN (0x00000000) Input value for GPIO0 - io_ro_32 gpio_in; - - _REG_(SIO_GPIO_HI_IN_OFFSET) // SIO_GPIO_HI_IN - // Input value for QSPI pins - // 0x0000003f [5:0] GPIO_HI_IN (0x00) Input value on QSPI IO in order 0 - io_ro_32 gpio_hi_in; - - uint32_t _pad0; - - _REG_(SIO_GPIO_OUT_OFFSET) // SIO_GPIO_OUT - // GPIO output value - // 0x3fffffff [29:0] GPIO_OUT (0x00000000) Set output level (1/0 -> high/low) for GPIO0 - io_rw_32 gpio_out; - - _REG_(SIO_GPIO_OUT_SET_OFFSET) // SIO_GPIO_OUT_SET - // GPIO output value set - // 0x3fffffff [29:0] GPIO_OUT_SET (0x00000000) Perform an atomic bit-set on GPIO_OUT, i - io_wo_32 gpio_set; - - _REG_(SIO_GPIO_OUT_CLR_OFFSET) // SIO_GPIO_OUT_CLR - // GPIO output value clear - // 0x3fffffff [29:0] GPIO_OUT_CLR (0x00000000) Perform an atomic bit-clear on GPIO_OUT, i - io_wo_32 gpio_clr; - - _REG_(SIO_GPIO_OUT_XOR_OFFSET) // SIO_GPIO_OUT_XOR - // GPIO output value XOR - // 0x3fffffff [29:0] GPIO_OUT_XOR (0x00000000) Perform an atomic bitwise XOR on GPIO_OUT, i - io_wo_32 gpio_togl; - - _REG_(SIO_GPIO_OE_OFFSET) // SIO_GPIO_OE - // GPIO output enable - // 0x3fffffff [29:0] GPIO_OE (0x00000000) Set output enable (1/0 -> output/input) for GPIO0 - io_rw_32 gpio_oe; - - _REG_(SIO_GPIO_OE_SET_OFFSET) // SIO_GPIO_OE_SET - // GPIO output enable set - // 0x3fffffff [29:0] GPIO_OE_SET (0x00000000) Perform an atomic bit-set on GPIO_OE, i - io_wo_32 gpio_oe_set; - - _REG_(SIO_GPIO_OE_CLR_OFFSET) // SIO_GPIO_OE_CLR - // GPIO output enable clear - // 0x3fffffff [29:0] GPIO_OE_CLR (0x00000000) Perform an atomic bit-clear on GPIO_OE, i - io_wo_32 gpio_oe_clr; - - _REG_(SIO_GPIO_OE_XOR_OFFSET) // SIO_GPIO_OE_XOR - // GPIO output enable XOR - // 0x3fffffff [29:0] GPIO_OE_XOR (0x00000000) Perform an atomic bitwise XOR on GPIO_OE, i - io_wo_32 gpio_oe_togl; - - _REG_(SIO_GPIO_HI_OUT_OFFSET) // SIO_GPIO_HI_OUT - // QSPI output value - // 0x0000003f [5:0] GPIO_HI_OUT (0x00) Set output level (1/0 -> high/low) for QSPI IO0 - io_rw_32 gpio_hi_out; - - _REG_(SIO_GPIO_HI_OUT_SET_OFFSET) // SIO_GPIO_HI_OUT_SET - // QSPI output value set - // 0x0000003f [5:0] GPIO_HI_OUT_SET (0x00) Perform an atomic bit-set on GPIO_HI_OUT, i - io_wo_32 gpio_hi_set; - - _REG_(SIO_GPIO_HI_OUT_CLR_OFFSET) // SIO_GPIO_HI_OUT_CLR - // QSPI output value clear - // 0x0000003f [5:0] GPIO_HI_OUT_CLR (0x00) Perform an atomic bit-clear on GPIO_HI_OUT, i - io_wo_32 gpio_hi_clr; - - _REG_(SIO_GPIO_HI_OUT_XOR_OFFSET) // SIO_GPIO_HI_OUT_XOR - // QSPI output value XOR - // 0x0000003f [5:0] GPIO_HI_OUT_XOR (0x00) Perform an atomic bitwise XOR on GPIO_HI_OUT, i - io_wo_32 gpio_hi_togl; - - _REG_(SIO_GPIO_HI_OE_OFFSET) // SIO_GPIO_HI_OE - // QSPI output enable - // 0x0000003f [5:0] GPIO_HI_OE (0x00) Set output enable (1/0 -> output/input) for QSPI IO0 - io_rw_32 gpio_hi_oe; - - _REG_(SIO_GPIO_HI_OE_SET_OFFSET) // SIO_GPIO_HI_OE_SET - // QSPI output enable set - // 0x0000003f [5:0] GPIO_HI_OE_SET (0x00) Perform an atomic bit-set on GPIO_HI_OE, i - io_wo_32 gpio_hi_oe_set; - - _REG_(SIO_GPIO_HI_OE_CLR_OFFSET) // SIO_GPIO_HI_OE_CLR - // QSPI output enable clear - // 0x0000003f [5:0] GPIO_HI_OE_CLR (0x00) Perform an atomic bit-clear on GPIO_HI_OE, i - io_wo_32 gpio_hi_oe_clr; - - _REG_(SIO_GPIO_HI_OE_XOR_OFFSET) // SIO_GPIO_HI_OE_XOR - // QSPI output enable XOR - // 0x0000003f [5:0] GPIO_HI_OE_XOR (0x00) Perform an atomic bitwise XOR on GPIO_HI_OE, i - io_wo_32 gpio_hi_oe_togl; - - _REG_(SIO_FIFO_ST_OFFSET) // SIO_FIFO_ST - // Status register for inter-core FIFOs (mailboxes). - // 0x00000008 [3] ROE (0) Sticky flag indicating the RX FIFO was read when empty - // 0x00000004 [2] WOF (0) Sticky flag indicating the TX FIFO was written when full - // 0x00000002 [1] RDY (1) Value is 1 if this core's TX FIFO is not full (i - // 0x00000001 [0] VLD (0) Value is 1 if this core's RX FIFO is not empty (i - io_rw_32 fifo_st; - - _REG_(SIO_FIFO_WR_OFFSET) // SIO_FIFO_WR - // Write access to this core's TX FIFO - // 0xffffffff [31:0] FIFO_WR (0x00000000) - io_wo_32 fifo_wr; - - _REG_(SIO_FIFO_RD_OFFSET) // SIO_FIFO_RD - // Read access to this core's RX FIFO - // 0xffffffff [31:0] FIFO_RD (-) - io_ro_32 fifo_rd; - - _REG_(SIO_SPINLOCK_ST_OFFSET) // SIO_SPINLOCK_ST - // Spinlock state - // 0xffffffff [31:0] SPINLOCK_ST (0x00000000) - io_ro_32 spinlock_st; - - _REG_(SIO_DIV_UDIVIDEND_OFFSET) // SIO_DIV_UDIVIDEND - // Divider unsigned dividend - // 0xffffffff [31:0] DIV_UDIVIDEND (0x00000000) - io_rw_32 div_udividend; - - _REG_(SIO_DIV_UDIVISOR_OFFSET) // SIO_DIV_UDIVISOR - // Divider unsigned divisor - // 0xffffffff [31:0] DIV_UDIVISOR (0x00000000) - io_rw_32 div_udivisor; - - _REG_(SIO_DIV_SDIVIDEND_OFFSET) // SIO_DIV_SDIVIDEND - // Divider signed dividend - // 0xffffffff [31:0] DIV_SDIVIDEND (0x00000000) - io_rw_32 div_sdividend; - - _REG_(SIO_DIV_SDIVISOR_OFFSET) // SIO_DIV_SDIVISOR - // Divider signed divisor - // 0xffffffff [31:0] DIV_SDIVISOR (0x00000000) - io_rw_32 div_sdivisor; - - _REG_(SIO_DIV_QUOTIENT_OFFSET) // SIO_DIV_QUOTIENT - // Divider result quotient - // 0xffffffff [31:0] DIV_QUOTIENT (0x00000000) - io_rw_32 div_quotient; - - _REG_(SIO_DIV_REMAINDER_OFFSET) // SIO_DIV_REMAINDER - // Divider result remainder - // 0xffffffff [31:0] DIV_REMAINDER (0x00000000) - io_rw_32 div_remainder; - - _REG_(SIO_DIV_CSR_OFFSET) // SIO_DIV_CSR - // Control and status register for divider - // 0x00000002 [1] DIRTY (0) Changes to 1 when any register is written, and back to 0... - // 0x00000001 [0] READY (1) Reads as 0 when a calculation is in progress, 1 otherwise - io_ro_32 div_csr; - - uint32_t _pad1; - - interp_hw_t interp[2]; - - // (Description copied from array index 0 register SIO_SPINLOCK0 applies similarly to other array indexes) - _REG_(SIO_SPINLOCK0_OFFSET) // SIO_SPINLOCK0 - // Spinlock register 0 - // 0xffffffff [31:0] SPINLOCK0 (0x00000000) - io_rw_32 spinlock[32]; -} sio_hw_t; - -#define sio_hw ((sio_hw_t *)SIO_BASE) -static_assert(sizeof (sio_hw_t) == 0x0180, ""); - -#endif // _HARDWARE_STRUCTS_SIO_H - diff --git a/lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/spi.h b/lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/spi.h deleted file mode 100644 index 7d1956e91f..0000000000 --- a/lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/spi.h +++ /dev/null @@ -1,105 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _HARDWARE_STRUCTS_SPI_H -#define _HARDWARE_STRUCTS_SPI_H - -/** - * \file rp2040/spi.h - */ - -#include "hardware/address_mapped.h" -#include "hardware/regs/spi.h" - -// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_spi -// -// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) -// _REG_(x) will link to the corresponding register in hardware/regs/spi.h. -// -// Bit-field descriptions are of the form: -// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION - -typedef struct { - _REG_(SPI_SSPCR0_OFFSET) // SPI_SSPCR0 - // Control register 0, SSPCR0 on page 3-4 - // 0x0000ff00 [15:8] SCR (0x00) Serial clock rate - // 0x00000080 [7] SPH (0) SSPCLKOUT phase, applicable to Motorola SPI frame format only - // 0x00000040 [6] SPO (0) SSPCLKOUT polarity, applicable to Motorola SPI frame format only - // 0x00000030 [5:4] FRF (0x0) Frame format: 00 Motorola SPI frame format - // 0x0000000f [3:0] DSS (0x0) Data Size Select: 0000 Reserved, undefined operation - io_rw_32 cr0; - - _REG_(SPI_SSPCR1_OFFSET) // SPI_SSPCR1 - // Control register 1, SSPCR1 on page 3-5 - // 0x00000008 [3] SOD (0) Slave-mode output disable - // 0x00000004 [2] MS (0) Master or slave mode select - // 0x00000002 [1] SSE (0) Synchronous serial port enable: 0 SSP operation disabled - // 0x00000001 [0] LBM (0) Loop back mode: 0 Normal serial port operation enabled - io_rw_32 cr1; - - _REG_(SPI_SSPDR_OFFSET) // SPI_SSPDR - // Data register, SSPDR on page 3-6 - // 0x0000ffff [15:0] DATA (-) Transmit/Receive FIFO: Read Receive FIFO - io_rw_32 dr; - - _REG_(SPI_SSPSR_OFFSET) // SPI_SSPSR - // Status register, SSPSR on page 3-7 - // 0x00000010 [4] BSY (0) PrimeCell SSP busy flag, RO: 0 SSP is idle - // 0x00000008 [3] RFF (0) Receive FIFO full, RO: 0 Receive FIFO is not full - // 0x00000004 [2] RNE (0) Receive FIFO not empty, RO: 0 Receive FIFO is empty - // 0x00000002 [1] TNF (1) Transmit FIFO not full, RO: 0 Transmit FIFO is full - // 0x00000001 [0] TFE (1) Transmit FIFO empty, RO: 0 Transmit FIFO is not empty - io_ro_32 sr; - - _REG_(SPI_SSPCPSR_OFFSET) // SPI_SSPCPSR - // Clock prescale register, SSPCPSR on page 3-8 - // 0x000000ff [7:0] CPSDVSR (0x00) Clock prescale divisor - io_rw_32 cpsr; - - _REG_(SPI_SSPIMSC_OFFSET) // SPI_SSPIMSC - // Interrupt mask set or clear register, SSPIMSC on page 3-9 - // 0x00000008 [3] TXIM (0) Transmit FIFO interrupt mask: 0 Transmit FIFO half empty... - // 0x00000004 [2] RXIM (0) Receive FIFO interrupt mask: 0 Receive FIFO half full or... - // 0x00000002 [1] RTIM (0) Receive timeout interrupt mask: 0 Receive FIFO not empty... - // 0x00000001 [0] RORIM (0) Receive overrun interrupt mask: 0 Receive FIFO written... - io_rw_32 imsc; - - _REG_(SPI_SSPRIS_OFFSET) // SPI_SSPRIS - // Raw interrupt status register, SSPRIS on page 3-10 - // 0x00000008 [3] TXRIS (1) Gives the raw interrupt state, prior to masking, of the... - // 0x00000004 [2] RXRIS (0) Gives the raw interrupt state, prior to masking, of the... - // 0x00000002 [1] RTRIS (0) Gives the raw interrupt state, prior to masking, of the... - // 0x00000001 [0] RORRIS (0) Gives the raw interrupt state, prior to masking, of the... - io_ro_32 ris; - - _REG_(SPI_SSPMIS_OFFSET) // SPI_SSPMIS - // Masked interrupt status register, SSPMIS on page 3-11 - // 0x00000008 [3] TXMIS (0) Gives the transmit FIFO masked interrupt state, after... - // 0x00000004 [2] RXMIS (0) Gives the receive FIFO masked interrupt state, after... - // 0x00000002 [1] RTMIS (0) Gives the receive timeout masked interrupt state, after... - // 0x00000001 [0] RORMIS (0) Gives the receive over run masked interrupt status,... - io_ro_32 mis; - - _REG_(SPI_SSPICR_OFFSET) // SPI_SSPICR - // Interrupt clear register, SSPICR on page 3-11 - // 0x00000002 [1] RTIC (0) Clears the SSPRTINTR interrupt - // 0x00000001 [0] RORIC (0) Clears the SSPRORINTR interrupt - io_rw_32 icr; - - _REG_(SPI_SSPDMACR_OFFSET) // SPI_SSPDMACR - // DMA control register, SSPDMACR on page 3-12 - // 0x00000002 [1] TXDMAE (0) Transmit DMA Enable - // 0x00000001 [0] RXDMAE (0) Receive DMA Enable - io_rw_32 dmacr; -} spi_hw_t; - -#define spi0_hw ((spi_hw_t *)SPI0_BASE) -#define spi1_hw ((spi_hw_t *)SPI1_BASE) -static_assert(sizeof (spi_hw_t) == 0x0028, ""); - -#endif // _HARDWARE_STRUCTS_SPI_H - diff --git a/lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/ssi.h b/lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/ssi.h deleted file mode 100644 index 9d5fdace6e..0000000000 --- a/lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/ssi.h +++ /dev/null @@ -1,215 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _HARDWARE_STRUCTS_SSI_H -#define _HARDWARE_STRUCTS_SSI_H - -/** - * \file rp2040/ssi.h - */ - -#include "hardware/address_mapped.h" -#include "hardware/regs/ssi.h" - -// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_ssi -// -// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) -// _REG_(x) will link to the corresponding register in hardware/regs/ssi.h. -// -// Bit-field descriptions are of the form: -// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION - -typedef struct { - _REG_(SSI_CTRLR0_OFFSET) // SSI_CTRLR0 - // Control register 0 - // 0x01000000 [24] SSTE (0) Slave select toggle enable - // 0x00600000 [22:21] SPI_FRF (0x0) SPI frame format - // 0x001f0000 [20:16] DFS_32 (0x00) Data frame size in 32b transfer mode + - // 0x0000f000 [15:12] CFS (0x0) Control frame size + - // 0x00000800 [11] SRL (0) Shift register loop (test mode) - // 0x00000400 [10] SLV_OE (0) Slave output enable - // 0x00000300 [9:8] TMOD (0x0) Transfer mode - // 0x00000080 [7] SCPOL (0) Serial clock polarity - // 0x00000040 [6] SCPH (0) Serial clock phase - // 0x00000030 [5:4] FRF (0x0) Frame format - // 0x0000000f [3:0] DFS (0x0) Data frame size - io_rw_32 ctrlr0; - - _REG_(SSI_CTRLR1_OFFSET) // SSI_CTRLR1 - // Master Control register 1 - // 0x0000ffff [15:0] NDF (0x0000) Number of data frames - io_rw_32 ctrlr1; - - _REG_(SSI_SSIENR_OFFSET) // SSI_SSIENR - // SSI Enable - // 0x00000001 [0] SSI_EN (0) SSI enable - io_rw_32 ssienr; - - _REG_(SSI_MWCR_OFFSET) // SSI_MWCR - // Microwire Control - // 0x00000004 [2] MHS (0) Microwire handshaking - // 0x00000002 [1] MDD (0) Microwire control - // 0x00000001 [0] MWMOD (0) Microwire transfer mode - io_rw_32 mwcr; - - _REG_(SSI_SER_OFFSET) // SSI_SER - // Slave enable - // 0x00000001 [0] SER (0) For each bit: + - io_rw_32 ser; - - _REG_(SSI_BAUDR_OFFSET) // SSI_BAUDR - // Baud rate - // 0x0000ffff [15:0] SCKDV (0x0000) SSI clock divider - io_rw_32 baudr; - - _REG_(SSI_TXFTLR_OFFSET) // SSI_TXFTLR - // TX FIFO threshold level - // 0x000000ff [7:0] TFT (0x00) Transmit FIFO threshold - io_rw_32 txftlr; - - _REG_(SSI_RXFTLR_OFFSET) // SSI_RXFTLR - // RX FIFO threshold level - // 0x000000ff [7:0] RFT (0x00) Receive FIFO threshold - io_rw_32 rxftlr; - - _REG_(SSI_TXFLR_OFFSET) // SSI_TXFLR - // TX FIFO level - // 0x000000ff [7:0] TFTFL (0x00) Transmit FIFO level - io_ro_32 txflr; - - _REG_(SSI_RXFLR_OFFSET) // SSI_RXFLR - // RX FIFO level - // 0x000000ff [7:0] RXTFL (0x00) Receive FIFO level - io_ro_32 rxflr; - - _REG_(SSI_SR_OFFSET) // SSI_SR - // Status register - // 0x00000040 [6] DCOL (0) Data collision error - // 0x00000020 [5] TXE (0) Transmission error - // 0x00000010 [4] RFF (0) Receive FIFO full - // 0x00000008 [3] RFNE (0) Receive FIFO not empty - // 0x00000004 [2] TFE (0) Transmit FIFO empty - // 0x00000002 [1] TFNF (0) Transmit FIFO not full - // 0x00000001 [0] BUSY (0) SSI busy flag - io_ro_32 sr; - - _REG_(SSI_IMR_OFFSET) // SSI_IMR - // Interrupt mask - // 0x00000020 [5] MSTIM (0) Multi-master contention interrupt mask - // 0x00000010 [4] RXFIM (0) Receive FIFO full interrupt mask - // 0x00000008 [3] RXOIM (0) Receive FIFO overflow interrupt mask - // 0x00000004 [2] RXUIM (0) Receive FIFO underflow interrupt mask - // 0x00000002 [1] TXOIM (0) Transmit FIFO overflow interrupt mask - // 0x00000001 [0] TXEIM (0) Transmit FIFO empty interrupt mask - io_rw_32 imr; - - _REG_(SSI_ISR_OFFSET) // SSI_ISR - // Interrupt status - // 0x00000020 [5] MSTIS (0) Multi-master contention interrupt status - // 0x00000010 [4] RXFIS (0) Receive FIFO full interrupt status - // 0x00000008 [3] RXOIS (0) Receive FIFO overflow interrupt status - // 0x00000004 [2] RXUIS (0) Receive FIFO underflow interrupt status - // 0x00000002 [1] TXOIS (0) Transmit FIFO overflow interrupt status - // 0x00000001 [0] TXEIS (0) Transmit FIFO empty interrupt status - io_ro_32 isr; - - _REG_(SSI_RISR_OFFSET) // SSI_RISR - // Raw interrupt status - // 0x00000020 [5] MSTIR (0) Multi-master contention raw interrupt status - // 0x00000010 [4] RXFIR (0) Receive FIFO full raw interrupt status - // 0x00000008 [3] RXOIR (0) Receive FIFO overflow raw interrupt status - // 0x00000004 [2] RXUIR (0) Receive FIFO underflow raw interrupt status - // 0x00000002 [1] TXOIR (0) Transmit FIFO overflow raw interrupt status - // 0x00000001 [0] TXEIR (0) Transmit FIFO empty raw interrupt status - io_ro_32 risr; - - _REG_(SSI_TXOICR_OFFSET) // SSI_TXOICR - // TX FIFO overflow interrupt clear - // 0x00000001 [0] TXOICR (0) Clear-on-read transmit FIFO overflow interrupt - io_ro_32 txoicr; - - _REG_(SSI_RXOICR_OFFSET) // SSI_RXOICR - // RX FIFO overflow interrupt clear - // 0x00000001 [0] RXOICR (0) Clear-on-read receive FIFO overflow interrupt - io_ro_32 rxoicr; - - _REG_(SSI_RXUICR_OFFSET) // SSI_RXUICR - // RX FIFO underflow interrupt clear - // 0x00000001 [0] RXUICR (0) Clear-on-read receive FIFO underflow interrupt - io_ro_32 rxuicr; - - _REG_(SSI_MSTICR_OFFSET) // SSI_MSTICR - // Multi-master interrupt clear - // 0x00000001 [0] MSTICR (0) Clear-on-read multi-master contention interrupt - io_ro_32 msticr; - - _REG_(SSI_ICR_OFFSET) // SSI_ICR - // Interrupt clear - // 0x00000001 [0] ICR (0) Clear-on-read all active interrupts - io_ro_32 icr; - - _REG_(SSI_DMACR_OFFSET) // SSI_DMACR - // DMA control - // 0x00000002 [1] TDMAE (0) Transmit DMA enable - // 0x00000001 [0] RDMAE (0) Receive DMA enable - io_rw_32 dmacr; - - _REG_(SSI_DMATDLR_OFFSET) // SSI_DMATDLR - // DMA TX data level - // 0x000000ff [7:0] DMATDL (0x00) Transmit data watermark level - io_rw_32 dmatdlr; - - _REG_(SSI_DMARDLR_OFFSET) // SSI_DMARDLR - // DMA RX data level - // 0x000000ff [7:0] DMARDL (0x00) Receive data watermark level (DMARDLR+1) - io_rw_32 dmardlr; - - _REG_(SSI_IDR_OFFSET) // SSI_IDR - // Identification register - // 0xffffffff [31:0] IDCODE (0x51535049) Peripheral dentification code - io_ro_32 idr; - - _REG_(SSI_SSI_VERSION_ID_OFFSET) // SSI_SSI_VERSION_ID - // Version ID - // 0xffffffff [31:0] SSI_COMP_VERSION (0x3430312a) SNPS component version (format X - io_ro_32 ssi_version_id; - - _REG_(SSI_DR0_OFFSET) // SSI_DR0 - // Data Register 0 (of 36) - // 0xffffffff [31:0] DR (0x00000000) First data register of 36 - io_rw_32 dr0; - - uint32_t _pad0[35]; - - _REG_(SSI_RX_SAMPLE_DLY_OFFSET) // SSI_RX_SAMPLE_DLY - // RX sample delay - // 0x000000ff [7:0] RSD (0x00) RXD sample delay (in SCLK cycles) - io_rw_32 rx_sample_dly; - - _REG_(SSI_SPI_CTRLR0_OFFSET) // SSI_SPI_CTRLR0 - // SPI control - // 0xff000000 [31:24] XIP_CMD (0x03) SPI Command to send in XIP mode (INST_L = 8-bit) or to... - // 0x00040000 [18] SPI_RXDS_EN (0) Read data strobe enable - // 0x00020000 [17] INST_DDR_EN (0) Instruction DDR transfer enable - // 0x00010000 [16] SPI_DDR_EN (0) SPI DDR transfer enable - // 0x0000f800 [15:11] WAIT_CYCLES (0x00) Wait cycles between control frame transmit and data... - // 0x00000300 [9:8] INST_L (0x0) Instruction length (0/4/8/16b) - // 0x0000003c [5:2] ADDR_L (0x0) Address length (0b-60b in 4b increments) - // 0x00000003 [1:0] TRANS_TYPE (0x0) Address and instruction transfer format - io_rw_32 spi_ctrlr0; - - _REG_(SSI_TXD_DRIVE_EDGE_OFFSET) // SSI_TXD_DRIVE_EDGE - // TX drive edge - // 0x000000ff [7:0] TDE (0x00) TXD drive edge - io_rw_32 txd_drive_edge; -} ssi_hw_t; - -#define ssi_hw ((ssi_hw_t *)XIP_SSI_BASE) -static_assert(sizeof (ssi_hw_t) == 0x00fc, ""); - -#endif // _HARDWARE_STRUCTS_SSI_H - diff --git a/lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/syscfg.h b/lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/syscfg.h deleted file mode 100644 index 1d63dc75f3..0000000000 --- a/lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/syscfg.h +++ /dev/null @@ -1,84 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _HARDWARE_STRUCTS_SYSCFG_H -#define _HARDWARE_STRUCTS_SYSCFG_H - -/** - * \file rp2040/syscfg.h - */ - -#include "hardware/address_mapped.h" -#include "hardware/regs/syscfg.h" - -// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_syscfg -// -// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) -// _REG_(x) will link to the corresponding register in hardware/regs/syscfg.h. -// -// Bit-field descriptions are of the form: -// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION - -typedef struct { - _REG_(SYSCFG_PROC0_NMI_MASK_OFFSET) // SYSCFG_PROC0_NMI_MASK - // Processor core 0 NMI source mask - // 0xffffffff [31:0] PROC0_NMI_MASK (0x00000000) Set a bit high to enable NMI from that IRQ - io_rw_32 proc0_nmi_mask; - - _REG_(SYSCFG_PROC1_NMI_MASK_OFFSET) // SYSCFG_PROC1_NMI_MASK - // Processor core 1 NMI source mask - // 0xffffffff [31:0] PROC1_NMI_MASK (0x00000000) Set a bit high to enable NMI from that IRQ - io_rw_32 proc1_nmi_mask; - - _REG_(SYSCFG_PROC_CONFIG_OFFSET) // SYSCFG_PROC_CONFIG - // Configuration for processors - // 0xf0000000 [31:28] PROC1_DAP_INSTID (0x1) Configure proc1 DAP instance ID - // 0x0f000000 [27:24] PROC0_DAP_INSTID (0x0) Configure proc0 DAP instance ID - // 0x00000002 [1] PROC1_HALTED (0) Indication that proc1 has halted - // 0x00000001 [0] PROC0_HALTED (0) Indication that proc0 has halted - io_rw_32 proc_config; - - _REG_(SYSCFG_PROC_IN_SYNC_BYPASS_OFFSET) // SYSCFG_PROC_IN_SYNC_BYPASS - // For each bit, if 1, bypass the input synchronizer between that GPIO + - // 0x3fffffff [29:0] PROC_IN_SYNC_BYPASS (0x00000000) - io_rw_32 proc_in_sync_bypass; - - _REG_(SYSCFG_PROC_IN_SYNC_BYPASS_HI_OFFSET) // SYSCFG_PROC_IN_SYNC_BYPASS_HI - // For each bit, if 1, bypass the input synchronizer between that GPIO + - // 0x0000003f [5:0] PROC_IN_SYNC_BYPASS_HI (0x00) - io_rw_32 proc_in_sync_bypass_hi; - - _REG_(SYSCFG_DBGFORCE_OFFSET) // SYSCFG_DBGFORCE - // Directly control the SWD debug port of either processor - // 0x00000080 [7] PROC1_ATTACH (0) Attach processor 1 debug port to syscfg controls, and... - // 0x00000040 [6] PROC1_SWCLK (1) Directly drive processor 1 SWCLK, if PROC1_ATTACH is set - // 0x00000020 [5] PROC1_SWDI (1) Directly drive processor 1 SWDIO input, if PROC1_ATTACH is set - // 0x00000010 [4] PROC1_SWDO (-) Observe the value of processor 1 SWDIO output - // 0x00000008 [3] PROC0_ATTACH (0) Attach processor 0 debug port to syscfg controls, and... - // 0x00000004 [2] PROC0_SWCLK (1) Directly drive processor 0 SWCLK, if PROC0_ATTACH is set - // 0x00000002 [1] PROC0_SWDI (1) Directly drive processor 0 SWDIO input, if PROC0_ATTACH is set - // 0x00000001 [0] PROC0_SWDO (-) Observe the value of processor 0 SWDIO output - io_rw_32 dbgforce; - - _REG_(SYSCFG_MEMPOWERDOWN_OFFSET) // SYSCFG_MEMPOWERDOWN - // Control power downs to memories - // 0x00000080 [7] ROM (0) - // 0x00000040 [6] USB (0) - // 0x00000020 [5] SRAM5 (0) - // 0x00000010 [4] SRAM4 (0) - // 0x00000008 [3] SRAM3 (0) - // 0x00000004 [2] SRAM2 (0) - // 0x00000002 [1] SRAM1 (0) - // 0x00000001 [0] SRAM0 (0) - io_rw_32 mempowerdown; -} syscfg_hw_t; - -#define syscfg_hw ((syscfg_hw_t *)SYSCFG_BASE) -static_assert(sizeof (syscfg_hw_t) == 0x001c, ""); - -#endif // _HARDWARE_STRUCTS_SYSCFG_H - diff --git a/lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/sysinfo.h b/lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/sysinfo.h deleted file mode 100644 index 6c0502f6e7..0000000000 --- a/lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/sysinfo.h +++ /dev/null @@ -1,52 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _HARDWARE_STRUCTS_SYSINFO_H -#define _HARDWARE_STRUCTS_SYSINFO_H - -/** - * \file rp2040/sysinfo.h - */ - -#include "hardware/address_mapped.h" -#include "hardware/regs/sysinfo.h" - -// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_sysinfo -// -// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) -// _REG_(x) will link to the corresponding register in hardware/regs/sysinfo.h. -// -// Bit-field descriptions are of the form: -// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION - -typedef struct { - _REG_(SYSINFO_CHIP_ID_OFFSET) // SYSINFO_CHIP_ID - // JEDEC JEP-106 compliant chip identifier - // 0xf0000000 [31:28] REVISION (-) - // 0x0ffff000 [27:12] PART (-) - // 0x00000fff [11:0] MANUFACTURER (-) - io_ro_32 chip_id; - - _REG_(SYSINFO_PLATFORM_OFFSET) // SYSINFO_PLATFORM - // Platform register - // 0x00000002 [1] ASIC (0) - // 0x00000001 [0] FPGA (0) - io_ro_32 platform; - - uint32_t _pad0[2]; - - _REG_(SYSINFO_GITREF_RP2040_OFFSET) // SYSINFO_GITREF_RP2040 - // Git hash of the chip source - // 0xffffffff [31:0] GITREF_RP2040 (-) - io_ro_32 gitref_rp2040; -} sysinfo_hw_t; - -#define sysinfo_hw ((sysinfo_hw_t *)SYSINFO_BASE) -static_assert(sizeof (sysinfo_hw_t) == 0x0014, ""); - -#endif // _HARDWARE_STRUCTS_SYSINFO_H - diff --git a/lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/systick.h b/lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/systick.h deleted file mode 100644 index ee878719b1..0000000000 --- a/lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/systick.h +++ /dev/null @@ -1,57 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _HARDWARE_STRUCTS_SYSTICK_H -#define _HARDWARE_STRUCTS_SYSTICK_H - -/** - * \file rp2040/systick.h - */ - -#include "hardware/address_mapped.h" -#include "hardware/regs/m0plus.h" - -// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_m0plus -// -// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) -// _REG_(x) will link to the corresponding register in hardware/regs/m0plus.h. -// -// Bit-field descriptions are of the form: -// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION - -typedef struct { - _REG_(M0PLUS_SYST_CSR_OFFSET) // M0PLUS_SYST_CSR - // SysTick Control and Status Register - // 0x00010000 [16] COUNTFLAG (0) Returns 1 if timer counted to 0 since last time this was read - // 0x00000004 [2] CLKSOURCE (0) SysTick clock source - // 0x00000002 [1] TICKINT (0) Enables SysTick exception request: + - // 0x00000001 [0] ENABLE (0) Enable SysTick counter: + - io_rw_32 csr; - - _REG_(M0PLUS_SYST_RVR_OFFSET) // M0PLUS_SYST_RVR - // SysTick Reload Value Register - // 0x00ffffff [23:0] RELOAD (0x000000) Value to load into the SysTick Current Value Register... - io_rw_32 rvr; - - _REG_(M0PLUS_SYST_CVR_OFFSET) // M0PLUS_SYST_CVR - // SysTick Current Value Register - // 0x00ffffff [23:0] CURRENT (0x000000) Reads return the current value of the SysTick counter - io_rw_32 cvr; - - _REG_(M0PLUS_SYST_CALIB_OFFSET) // M0PLUS_SYST_CALIB - // SysTick Calibration Value Register - // 0x80000000 [31] NOREF (0) If reads as 1, the Reference clock is not provided - the... - // 0x40000000 [30] SKEW (0) If reads as 1, the calibration value for 10ms is inexact... - // 0x00ffffff [23:0] TENMS (0x000000) An optional Reload value to be used for 10ms (100Hz)... - io_ro_32 calib; -} systick_hw_t; - -#define systick_hw ((systick_hw_t *)(PPB_BASE + M0PLUS_SYST_CSR_OFFSET)) -static_assert(sizeof (systick_hw_t) == 0x0010, ""); - -#endif // _HARDWARE_STRUCTS_SYSTICK_H - diff --git a/lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/tbman.h b/lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/tbman.h deleted file mode 100644 index 78a5f3b22b..0000000000 --- a/lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/tbman.h +++ /dev/null @@ -1,38 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _HARDWARE_STRUCTS_TBMAN_H -#define _HARDWARE_STRUCTS_TBMAN_H - -/** - * \file rp2040/tbman.h - */ - -#include "hardware/address_mapped.h" -#include "hardware/regs/tbman.h" - -// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_tbman -// -// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) -// _REG_(x) will link to the corresponding register in hardware/regs/tbman.h. -// -// Bit-field descriptions are of the form: -// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION - -typedef struct { - _REG_(TBMAN_PLATFORM_OFFSET) // TBMAN_PLATFORM - // Indicates the type of platform in use - // 0x00000002 [1] FPGA (0) Indicates the platform is an FPGA - // 0x00000001 [0] ASIC (1) Indicates the platform is an ASIC - io_ro_32 platform; -} tbman_hw_t; - -#define tbman_hw ((tbman_hw_t *)TBMAN_BASE) -static_assert(sizeof (tbman_hw_t) == 0x0004, ""); - -#endif // _HARDWARE_STRUCTS_TBMAN_H - diff --git a/lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/timer.h b/lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/timer.h deleted file mode 100644 index 1b059ad56c..0000000000 --- a/lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/timer.h +++ /dev/null @@ -1,116 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _HARDWARE_STRUCTS_TIMER_H -#define _HARDWARE_STRUCTS_TIMER_H - -/** - * \file rp2040/timer.h - */ - -#include "hardware/address_mapped.h" -#include "hardware/regs/timer.h" - -// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_timer -// -// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) -// _REG_(x) will link to the corresponding register in hardware/regs/timer.h. -// -// Bit-field descriptions are of the form: -// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION - -typedef struct { - _REG_(TIMER_TIMEHW_OFFSET) // TIMER_TIMEHW - // Write to bits 63:32 of time + - // 0xffffffff [31:0] TIMEHW (0x00000000) - io_wo_32 timehw; - - _REG_(TIMER_TIMELW_OFFSET) // TIMER_TIMELW - // Write to bits 31:0 of time + - // 0xffffffff [31:0] TIMELW (0x00000000) - io_wo_32 timelw; - - _REG_(TIMER_TIMEHR_OFFSET) // TIMER_TIMEHR - // Read from bits 63:32 of time + - // 0xffffffff [31:0] TIMEHR (0x00000000) - io_ro_32 timehr; - - _REG_(TIMER_TIMELR_OFFSET) // TIMER_TIMELR - // Read from bits 31:0 of time - // 0xffffffff [31:0] TIMELR (0x00000000) - io_ro_32 timelr; - - // (Description copied from array index 0 register TIMER_ALARM0 applies similarly to other array indexes) - _REG_(TIMER_ALARM0_OFFSET) // TIMER_ALARM0 - // Arm alarm 0, and configure the time it will fire - // 0xffffffff [31:0] ALARM0 (0x00000000) - io_rw_32 alarm[4]; - - _REG_(TIMER_ARMED_OFFSET) // TIMER_ARMED - // Indicates the armed/disarmed status of each alarm - // 0x0000000f [3:0] ARMED (0x0) - io_rw_32 armed; - - _REG_(TIMER_TIMERAWH_OFFSET) // TIMER_TIMERAWH - // Raw read from bits 63:32 of time (no side effects) - // 0xffffffff [31:0] TIMERAWH (0x00000000) - io_ro_32 timerawh; - - _REG_(TIMER_TIMERAWL_OFFSET) // TIMER_TIMERAWL - // Raw read from bits 31:0 of time (no side effects) - // 0xffffffff [31:0] TIMERAWL (0x00000000) - io_ro_32 timerawl; - - _REG_(TIMER_DBGPAUSE_OFFSET) // TIMER_DBGPAUSE - // Set bits high to enable pause when the corresponding debug ports are active - // 0x00000004 [2] DBG1 (1) Pause when processor 1 is in debug mode - // 0x00000002 [1] DBG0 (1) Pause when processor 0 is in debug mode - io_rw_32 dbgpause; - - _REG_(TIMER_PAUSE_OFFSET) // TIMER_PAUSE - // Set high to pause the timer - // 0x00000001 [0] PAUSE (0) - io_rw_32 pause; - - _REG_(TIMER_INTR_OFFSET) // TIMER_INTR - // Raw Interrupts - // 0x00000008 [3] ALARM_3 (0) - // 0x00000004 [2] ALARM_2 (0) - // 0x00000002 [1] ALARM_1 (0) - // 0x00000001 [0] ALARM_0 (0) - io_rw_32 intr; - - _REG_(TIMER_INTE_OFFSET) // TIMER_INTE - // Interrupt Enable - // 0x00000008 [3] ALARM_3 (0) - // 0x00000004 [2] ALARM_2 (0) - // 0x00000002 [1] ALARM_1 (0) - // 0x00000001 [0] ALARM_0 (0) - io_rw_32 inte; - - _REG_(TIMER_INTF_OFFSET) // TIMER_INTF - // Interrupt Force - // 0x00000008 [3] ALARM_3 (0) - // 0x00000004 [2] ALARM_2 (0) - // 0x00000002 [1] ALARM_1 (0) - // 0x00000001 [0] ALARM_0 (0) - io_rw_32 intf; - - _REG_(TIMER_INTS_OFFSET) // TIMER_INTS - // Interrupt status after masking & forcing - // 0x00000008 [3] ALARM_3 (0) - // 0x00000004 [2] ALARM_2 (0) - // 0x00000002 [1] ALARM_1 (0) - // 0x00000001 [0] ALARM_0 (0) - io_ro_32 ints; -} timer_hw_t; - -#define timer_hw ((timer_hw_t *)TIMER_BASE) -static_assert(sizeof (timer_hw_t) == 0x0044, ""); - -#endif // _HARDWARE_STRUCTS_TIMER_H - diff --git a/lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/uart.h b/lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/uart.h deleted file mode 100644 index db0b4be40e..0000000000 --- a/lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/uart.h +++ /dev/null @@ -1,182 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _HARDWARE_STRUCTS_UART_H -#define _HARDWARE_STRUCTS_UART_H - -/** - * \file rp2040/uart.h - */ - -#include "hardware/address_mapped.h" -#include "hardware/regs/uart.h" - -// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_uart -// -// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) -// _REG_(x) will link to the corresponding register in hardware/regs/uart.h. -// -// Bit-field descriptions are of the form: -// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION - -typedef struct { - _REG_(UART_UARTDR_OFFSET) // UART_UARTDR - // Data Register, UARTDR - // 0x00000800 [11] OE (-) Overrun error - // 0x00000400 [10] BE (-) Break error - // 0x00000200 [9] PE (-) Parity error - // 0x00000100 [8] FE (-) Framing error - // 0x000000ff [7:0] DATA (-) Receive (read) data character - io_rw_32 dr; - - _REG_(UART_UARTRSR_OFFSET) // UART_UARTRSR - // Receive Status Register/Error Clear Register, UARTRSR/UARTECR - // 0x00000008 [3] OE (0) Overrun error - // 0x00000004 [2] BE (0) Break error - // 0x00000002 [1] PE (0) Parity error - // 0x00000001 [0] FE (0) Framing error - io_rw_32 rsr; - - uint32_t _pad0[4]; - - _REG_(UART_UARTFR_OFFSET) // UART_UARTFR - // Flag Register, UARTFR - // 0x00000100 [8] RI (-) Ring indicator - // 0x00000080 [7] TXFE (1) Transmit FIFO empty - // 0x00000040 [6] RXFF (0) Receive FIFO full - // 0x00000020 [5] TXFF (0) Transmit FIFO full - // 0x00000010 [4] RXFE (1) Receive FIFO empty - // 0x00000008 [3] BUSY (0) UART busy - // 0x00000004 [2] DCD (-) Data carrier detect - // 0x00000002 [1] DSR (-) Data set ready - // 0x00000001 [0] CTS (-) Clear to send - io_ro_32 fr; - - uint32_t _pad1; - - _REG_(UART_UARTILPR_OFFSET) // UART_UARTILPR - // IrDA Low-Power Counter Register, UARTILPR - // 0x000000ff [7:0] ILPDVSR (0x00) 8-bit low-power divisor value - io_rw_32 ilpr; - - _REG_(UART_UARTIBRD_OFFSET) // UART_UARTIBRD - // Integer Baud Rate Register, UARTIBRD - // 0x0000ffff [15:0] BAUD_DIVINT (0x0000) The integer baud rate divisor - io_rw_32 ibrd; - - _REG_(UART_UARTFBRD_OFFSET) // UART_UARTFBRD - // Fractional Baud Rate Register, UARTFBRD - // 0x0000003f [5:0] BAUD_DIVFRAC (0x00) The fractional baud rate divisor - io_rw_32 fbrd; - - _REG_(UART_UARTLCR_H_OFFSET) // UART_UARTLCR_H - // Line Control Register, UARTLCR_H - // 0x00000080 [7] SPS (0) Stick parity select - // 0x00000060 [6:5] WLEN (0x0) Word length - // 0x00000010 [4] FEN (0) Enable FIFOs: 0 = FIFOs are disabled (character mode)... - // 0x00000008 [3] STP2 (0) Two stop bits select - // 0x00000004 [2] EPS (0) Even parity select - // 0x00000002 [1] PEN (0) Parity enable: 0 = parity is disabled and no parity bit... - // 0x00000001 [0] BRK (0) Send break - io_rw_32 lcr_h; - - _REG_(UART_UARTCR_OFFSET) // UART_UARTCR - // Control Register, UARTCR - // 0x00008000 [15] CTSEN (0) CTS hardware flow control enable - // 0x00004000 [14] RTSEN (0) RTS hardware flow control enable - // 0x00002000 [13] OUT2 (0) This bit is the complement of the UART Out2 (nUARTOut2)... - // 0x00001000 [12] OUT1 (0) This bit is the complement of the UART Out1 (nUARTOut1)... - // 0x00000800 [11] RTS (0) Request to send - // 0x00000400 [10] DTR (0) Data transmit ready - // 0x00000200 [9] RXE (1) Receive enable - // 0x00000100 [8] TXE (1) Transmit enable - // 0x00000080 [7] LBE (0) Loopback enable - // 0x00000004 [2] SIRLP (0) SIR low-power IrDA mode - // 0x00000002 [1] SIREN (0) SIR enable: 0 = IrDA SIR ENDEC is disabled - // 0x00000001 [0] UARTEN (0) UART enable: 0 = UART is disabled - io_rw_32 cr; - - _REG_(UART_UARTIFLS_OFFSET) // UART_UARTIFLS - // Interrupt FIFO Level Select Register, UARTIFLS - // 0x00000038 [5:3] RXIFLSEL (0x2) Receive interrupt FIFO level select - // 0x00000007 [2:0] TXIFLSEL (0x2) Transmit interrupt FIFO level select - io_rw_32 ifls; - - _REG_(UART_UARTIMSC_OFFSET) // UART_UARTIMSC - // Interrupt Mask Set/Clear Register, UARTIMSC - // 0x00000400 [10] OEIM (0) Overrun error interrupt mask - // 0x00000200 [9] BEIM (0) Break error interrupt mask - // 0x00000100 [8] PEIM (0) Parity error interrupt mask - // 0x00000080 [7] FEIM (0) Framing error interrupt mask - // 0x00000040 [6] RTIM (0) Receive timeout interrupt mask - // 0x00000020 [5] TXIM (0) Transmit interrupt mask - // 0x00000010 [4] RXIM (0) Receive interrupt mask - // 0x00000008 [3] DSRMIM (0) nUARTDSR modem interrupt mask - // 0x00000004 [2] DCDMIM (0) nUARTDCD modem interrupt mask - // 0x00000002 [1] CTSMIM (0) nUARTCTS modem interrupt mask - // 0x00000001 [0] RIMIM (0) nUARTRI modem interrupt mask - io_rw_32 imsc; - - _REG_(UART_UARTRIS_OFFSET) // UART_UARTRIS - // Raw Interrupt Status Register, UARTRIS - // 0x00000400 [10] OERIS (0) Overrun error interrupt status - // 0x00000200 [9] BERIS (0) Break error interrupt status - // 0x00000100 [8] PERIS (0) Parity error interrupt status - // 0x00000080 [7] FERIS (0) Framing error interrupt status - // 0x00000040 [6] RTRIS (0) Receive timeout interrupt status - // 0x00000020 [5] TXRIS (0) Transmit interrupt status - // 0x00000010 [4] RXRIS (0) Receive interrupt status - // 0x00000008 [3] DSRRMIS (-) nUARTDSR modem interrupt status - // 0x00000004 [2] DCDRMIS (-) nUARTDCD modem interrupt status - // 0x00000002 [1] CTSRMIS (-) nUARTCTS modem interrupt status - // 0x00000001 [0] RIRMIS (-) nUARTRI modem interrupt status - io_ro_32 ris; - - _REG_(UART_UARTMIS_OFFSET) // UART_UARTMIS - // Masked Interrupt Status Register, UARTMIS - // 0x00000400 [10] OEMIS (0) Overrun error masked interrupt status - // 0x00000200 [9] BEMIS (0) Break error masked interrupt status - // 0x00000100 [8] PEMIS (0) Parity error masked interrupt status - // 0x00000080 [7] FEMIS (0) Framing error masked interrupt status - // 0x00000040 [6] RTMIS (0) Receive timeout masked interrupt status - // 0x00000020 [5] TXMIS (0) Transmit masked interrupt status - // 0x00000010 [4] RXMIS (0) Receive masked interrupt status - // 0x00000008 [3] DSRMMIS (-) nUARTDSR modem masked interrupt status - // 0x00000004 [2] DCDMMIS (-) nUARTDCD modem masked interrupt status - // 0x00000002 [1] CTSMMIS (-) nUARTCTS modem masked interrupt status - // 0x00000001 [0] RIMMIS (-) nUARTRI modem masked interrupt status - io_ro_32 mis; - - _REG_(UART_UARTICR_OFFSET) // UART_UARTICR - // Interrupt Clear Register, UARTICR - // 0x00000400 [10] OEIC (-) Overrun error interrupt clear - // 0x00000200 [9] BEIC (-) Break error interrupt clear - // 0x00000100 [8] PEIC (-) Parity error interrupt clear - // 0x00000080 [7] FEIC (-) Framing error interrupt clear - // 0x00000040 [6] RTIC (-) Receive timeout interrupt clear - // 0x00000020 [5] TXIC (-) Transmit interrupt clear - // 0x00000010 [4] RXIC (-) Receive interrupt clear - // 0x00000008 [3] DSRMIC (-) nUARTDSR modem interrupt clear - // 0x00000004 [2] DCDMIC (-) nUARTDCD modem interrupt clear - // 0x00000002 [1] CTSMIC (-) nUARTCTS modem interrupt clear - // 0x00000001 [0] RIMIC (-) nUARTRI modem interrupt clear - io_rw_32 icr; - - _REG_(UART_UARTDMACR_OFFSET) // UART_UARTDMACR - // DMA Control Register, UARTDMACR - // 0x00000004 [2] DMAONERR (0) DMA on error - // 0x00000002 [1] TXDMAE (0) Transmit DMA enable - // 0x00000001 [0] RXDMAE (0) Receive DMA enable - io_rw_32 dmacr; -} uart_hw_t; - -#define uart0_hw ((uart_hw_t *)UART0_BASE) -#define uart1_hw ((uart_hw_t *)UART1_BASE) -static_assert(sizeof (uart_hw_t) == 0x004c, ""); - -#endif // _HARDWARE_STRUCTS_UART_H - diff --git a/lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/usb.h b/lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/usb.h deleted file mode 100644 index 399845f172..0000000000 --- a/lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/usb.h +++ /dev/null @@ -1,476 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _HARDWARE_STRUCTS_USB_H -#define _HARDWARE_STRUCTS_USB_H - -/** - * \file rp2040/usb.h - */ - -#include "hardware/address_mapped.h" -#include "hardware/regs/usb.h" -#include "hardware/structs/usb_dpram.h" - -// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_usb -// -// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) -// _REG_(x) will link to the corresponding register in hardware/regs/usb.h. -// -// Bit-field descriptions are of the form: -// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION - -typedef struct { - _REG_(USB_ADDR_ENDP_OFFSET) // USB_ADDR_ENDP - // Device address and endpoint control - // 0x000f0000 [19:16] ENDPOINT (0x0) Device endpoint to send data to - // 0x0000007f [6:0] ADDRESS (0x00) In device mode, the address that the device should respond to - io_rw_32 dev_addr_ctrl; - - // (Description copied from array index 0 register USB_ADDR_ENDP1 applies similarly to other array indexes) - _REG_(USB_ADDR_ENDP1_OFFSET) // USB_ADDR_ENDP1 - // Interrupt endpoint 1 - // 0x04000000 [26] INTEP_PREAMBLE (0) Interrupt EP requires preamble (is a low speed device on... - // 0x02000000 [25] INTEP_DIR (0) Direction of the interrupt endpoint - // 0x000f0000 [19:16] ENDPOINT (0x0) Endpoint number of the interrupt endpoint - // 0x0000007f [6:0] ADDRESS (0x00) Device address - io_rw_32 int_ep_addr_ctrl[15]; - - _REG_(USB_MAIN_CTRL_OFFSET) // USB_MAIN_CTRL - // Main control register - // 0x80000000 [31] SIM_TIMING (0) Reduced timings for simulation - // 0x00000002 [1] HOST_NDEVICE (0) Device mode = 0, Host mode = 1 - // 0x00000001 [0] CONTROLLER_EN (0) Enable controller - io_rw_32 main_ctrl; - - _REG_(USB_SOF_WR_OFFSET) // USB_SOF_WR - // Set the SOF (Start of Frame) frame number in the host controller - // 0x000007ff [10:0] COUNT (0x000) - io_wo_32 sof_wr; - - _REG_(USB_SOF_RD_OFFSET) // USB_SOF_RD - // Read the last SOF (Start of Frame) frame number seen - // 0x000007ff [10:0] COUNT (0x000) - io_ro_32 sof_rd; - - _REG_(USB_SIE_CTRL_OFFSET) // USB_SIE_CTRL - // SIE control register - // 0x80000000 [31] EP0_INT_STALL (0) Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a STALL - // 0x40000000 [30] EP0_DOUBLE_BUF (0) Device: EP0 single buffered = 0, double buffered = 1 - // 0x20000000 [29] EP0_INT_1BUF (0) Device: Set bit in BUFF_STATUS for every buffer completed on EP0 - // 0x10000000 [28] EP0_INT_2BUF (0) Device: Set bit in BUFF_STATUS for every 2 buffers... - // 0x08000000 [27] EP0_INT_NAK (0) Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a NAK - // 0x04000000 [26] DIRECT_EN (0) Direct bus drive enable - // 0x02000000 [25] DIRECT_DP (0) Direct control of DP - // 0x01000000 [24] DIRECT_DM (0) Direct control of DM - // 0x00040000 [18] TRANSCEIVER_PD (0) Power down bus transceiver - // 0x00020000 [17] RPU_OPT (0) Device: Pull-up strength (0=1K2, 1=2k3) - // 0x00010000 [16] PULLUP_EN (0) Device: Enable pull up resistor - // 0x00008000 [15] PULLDOWN_EN (0) Host: Enable pull down resistors - // 0x00002000 [13] RESET_BUS (0) Host: Reset bus - // 0x00001000 [12] RESUME (0) Device: Remote wakeup - // 0x00000800 [11] VBUS_EN (0) Host: Enable VBUS - // 0x00000400 [10] KEEP_ALIVE_EN (0) Host: Enable keep alive packet (for low speed bus) - // 0x00000200 [9] SOF_EN (0) Host: Enable SOF generation (for full speed bus) - // 0x00000100 [8] SOF_SYNC (0) Host: Delay packet(s) until after SOF - // 0x00000040 [6] PREAMBLE_EN (0) Host: Preable enable for LS device on FS hub - // 0x00000010 [4] STOP_TRANS (0) Host: Stop transaction - // 0x00000008 [3] RECEIVE_DATA (0) Host: Receive transaction (IN to host) - // 0x00000004 [2] SEND_DATA (0) Host: Send transaction (OUT from host) - // 0x00000002 [1] SEND_SETUP (0) Host: Send Setup packet - // 0x00000001 [0] START_TRANS (0) Host: Start transaction - io_rw_32 sie_ctrl; - - _REG_(USB_SIE_STATUS_OFFSET) // USB_SIE_STATUS - // SIE status register - // 0x80000000 [31] DATA_SEQ_ERROR (0) Data Sequence Error - // 0x40000000 [30] ACK_REC (0) ACK received - // 0x20000000 [29] STALL_REC (0) Host: STALL received - // 0x10000000 [28] NAK_REC (0) Host: NAK received - // 0x08000000 [27] RX_TIMEOUT (0) RX timeout is raised by both the host and device if an... - // 0x04000000 [26] RX_OVERFLOW (0) RX overflow is raised by the Serial RX engine if the... - // 0x02000000 [25] BIT_STUFF_ERROR (0) Bit Stuff Error - // 0x01000000 [24] CRC_ERROR (0) CRC Error - // 0x00080000 [19] BUS_RESET (0) Device: bus reset received - // 0x00040000 [18] TRANS_COMPLETE (0) Transaction complete - // 0x00020000 [17] SETUP_REC (0) Device: Setup packet received - // 0x00010000 [16] CONNECTED (0) Device: connected - // 0x00000800 [11] RESUME (0) Host: Device has initiated a remote resume - // 0x00000400 [10] VBUS_OVER_CURR (0) VBUS over current detected - // 0x00000300 [9:8] SPEED (0x0) Host: device speed - // 0x00000010 [4] SUSPENDED (0) Bus in suspended state - // 0x0000000c [3:2] LINE_STATE (0x0) USB bus line state - // 0x00000001 [0] VBUS_DETECTED (0) Device: VBUS Detected - io_rw_32 sie_status; - - _REG_(USB_INT_EP_CTRL_OFFSET) // USB_INT_EP_CTRL - // interrupt endpoint control register - // 0x0000fffe [15:1] INT_EP_ACTIVE (0x0000) Host: Enable interrupt endpoint 1 => 15 - io_rw_32 int_ep_ctrl; - - _REG_(USB_BUFF_STATUS_OFFSET) // USB_BUFF_STATUS - // Buffer status register - // 0x80000000 [31] EP15_OUT (0) - // 0x40000000 [30] EP15_IN (0) - // 0x20000000 [29] EP14_OUT (0) - // 0x10000000 [28] EP14_IN (0) - // 0x08000000 [27] EP13_OUT (0) - // 0x04000000 [26] EP13_IN (0) - // 0x02000000 [25] EP12_OUT (0) - // 0x01000000 [24] EP12_IN (0) - // 0x00800000 [23] EP11_OUT (0) - // 0x00400000 [22] EP11_IN (0) - // 0x00200000 [21] EP10_OUT (0) - // 0x00100000 [20] EP10_IN (0) - // 0x00080000 [19] EP9_OUT (0) - // 0x00040000 [18] EP9_IN (0) - // 0x00020000 [17] EP8_OUT (0) - // 0x00010000 [16] EP8_IN (0) - // 0x00008000 [15] EP7_OUT (0) - // 0x00004000 [14] EP7_IN (0) - // 0x00002000 [13] EP6_OUT (0) - // 0x00001000 [12] EP6_IN (0) - // 0x00000800 [11] EP5_OUT (0) - // 0x00000400 [10] EP5_IN (0) - // 0x00000200 [9] EP4_OUT (0) - // 0x00000100 [8] EP4_IN (0) - // 0x00000080 [7] EP3_OUT (0) - // 0x00000040 [6] EP3_IN (0) - // 0x00000020 [5] EP2_OUT (0) - // 0x00000010 [4] EP2_IN (0) - // 0x00000008 [3] EP1_OUT (0) - // 0x00000004 [2] EP1_IN (0) - // 0x00000002 [1] EP0_OUT (0) - // 0x00000001 [0] EP0_IN (0) - io_rw_32 buf_status; - - _REG_(USB_BUFF_CPU_SHOULD_HANDLE_OFFSET) // USB_BUFF_CPU_SHOULD_HANDLE - // Which of the double buffers should be handled - // 0x80000000 [31] EP15_OUT (0) - // 0x40000000 [30] EP15_IN (0) - // 0x20000000 [29] EP14_OUT (0) - // 0x10000000 [28] EP14_IN (0) - // 0x08000000 [27] EP13_OUT (0) - // 0x04000000 [26] EP13_IN (0) - // 0x02000000 [25] EP12_OUT (0) - // 0x01000000 [24] EP12_IN (0) - // 0x00800000 [23] EP11_OUT (0) - // 0x00400000 [22] EP11_IN (0) - // 0x00200000 [21] EP10_OUT (0) - // 0x00100000 [20] EP10_IN (0) - // 0x00080000 [19] EP9_OUT (0) - // 0x00040000 [18] EP9_IN (0) - // 0x00020000 [17] EP8_OUT (0) - // 0x00010000 [16] EP8_IN (0) - // 0x00008000 [15] EP7_OUT (0) - // 0x00004000 [14] EP7_IN (0) - // 0x00002000 [13] EP6_OUT (0) - // 0x00001000 [12] EP6_IN (0) - // 0x00000800 [11] EP5_OUT (0) - // 0x00000400 [10] EP5_IN (0) - // 0x00000200 [9] EP4_OUT (0) - // 0x00000100 [8] EP4_IN (0) - // 0x00000080 [7] EP3_OUT (0) - // 0x00000040 [6] EP3_IN (0) - // 0x00000020 [5] EP2_OUT (0) - // 0x00000010 [4] EP2_IN (0) - // 0x00000008 [3] EP1_OUT (0) - // 0x00000004 [2] EP1_IN (0) - // 0x00000002 [1] EP0_OUT (0) - // 0x00000001 [0] EP0_IN (0) - io_ro_32 buf_cpu_should_handle; - - _REG_(USB_EP_ABORT_OFFSET) // USB_EP_ABORT - // Device only: Can be set to ignore the buffer control register for this endpoint in case you... - // 0x80000000 [31] EP15_OUT (0) - // 0x40000000 [30] EP15_IN (0) - // 0x20000000 [29] EP14_OUT (0) - // 0x10000000 [28] EP14_IN (0) - // 0x08000000 [27] EP13_OUT (0) - // 0x04000000 [26] EP13_IN (0) - // 0x02000000 [25] EP12_OUT (0) - // 0x01000000 [24] EP12_IN (0) - // 0x00800000 [23] EP11_OUT (0) - // 0x00400000 [22] EP11_IN (0) - // 0x00200000 [21] EP10_OUT (0) - // 0x00100000 [20] EP10_IN (0) - // 0x00080000 [19] EP9_OUT (0) - // 0x00040000 [18] EP9_IN (0) - // 0x00020000 [17] EP8_OUT (0) - // 0x00010000 [16] EP8_IN (0) - // 0x00008000 [15] EP7_OUT (0) - // 0x00004000 [14] EP7_IN (0) - // 0x00002000 [13] EP6_OUT (0) - // 0x00001000 [12] EP6_IN (0) - // 0x00000800 [11] EP5_OUT (0) - // 0x00000400 [10] EP5_IN (0) - // 0x00000200 [9] EP4_OUT (0) - // 0x00000100 [8] EP4_IN (0) - // 0x00000080 [7] EP3_OUT (0) - // 0x00000040 [6] EP3_IN (0) - // 0x00000020 [5] EP2_OUT (0) - // 0x00000010 [4] EP2_IN (0) - // 0x00000008 [3] EP1_OUT (0) - // 0x00000004 [2] EP1_IN (0) - // 0x00000002 [1] EP0_OUT (0) - // 0x00000001 [0] EP0_IN (0) - io_rw_32 abort; - - _REG_(USB_EP_ABORT_DONE_OFFSET) // USB_EP_ABORT_DONE - // Device only: Used in conjunction with `EP_ABORT` - // 0x80000000 [31] EP15_OUT (0) - // 0x40000000 [30] EP15_IN (0) - // 0x20000000 [29] EP14_OUT (0) - // 0x10000000 [28] EP14_IN (0) - // 0x08000000 [27] EP13_OUT (0) - // 0x04000000 [26] EP13_IN (0) - // 0x02000000 [25] EP12_OUT (0) - // 0x01000000 [24] EP12_IN (0) - // 0x00800000 [23] EP11_OUT (0) - // 0x00400000 [22] EP11_IN (0) - // 0x00200000 [21] EP10_OUT (0) - // 0x00100000 [20] EP10_IN (0) - // 0x00080000 [19] EP9_OUT (0) - // 0x00040000 [18] EP9_IN (0) - // 0x00020000 [17] EP8_OUT (0) - // 0x00010000 [16] EP8_IN (0) - // 0x00008000 [15] EP7_OUT (0) - // 0x00004000 [14] EP7_IN (0) - // 0x00002000 [13] EP6_OUT (0) - // 0x00001000 [12] EP6_IN (0) - // 0x00000800 [11] EP5_OUT (0) - // 0x00000400 [10] EP5_IN (0) - // 0x00000200 [9] EP4_OUT (0) - // 0x00000100 [8] EP4_IN (0) - // 0x00000080 [7] EP3_OUT (0) - // 0x00000040 [6] EP3_IN (0) - // 0x00000020 [5] EP2_OUT (0) - // 0x00000010 [4] EP2_IN (0) - // 0x00000008 [3] EP1_OUT (0) - // 0x00000004 [2] EP1_IN (0) - // 0x00000002 [1] EP0_OUT (0) - // 0x00000001 [0] EP0_IN (0) - io_rw_32 abort_done; - - _REG_(USB_EP_STALL_ARM_OFFSET) // USB_EP_STALL_ARM - // Device: this bit must be set in conjunction with the `STALL` bit in the buffer control register... - // 0x00000002 [1] EP0_OUT (0) - // 0x00000001 [0] EP0_IN (0) - io_rw_32 ep_stall_arm; - - _REG_(USB_NAK_POLL_OFFSET) // USB_NAK_POLL - // Used by the host controller - // 0x03ff0000 [25:16] DELAY_FS (0x010) NAK polling interval for a full speed device - // 0x000003ff [9:0] DELAY_LS (0x010) NAK polling interval for a low speed device - io_rw_32 nak_poll; - - _REG_(USB_EP_STATUS_STALL_NAK_OFFSET) // USB_EP_STATUS_STALL_NAK - // Device: bits are set when the `IRQ_ON_NAK` or `IRQ_ON_STALL` bits are set - // 0x80000000 [31] EP15_OUT (0) - // 0x40000000 [30] EP15_IN (0) - // 0x20000000 [29] EP14_OUT (0) - // 0x10000000 [28] EP14_IN (0) - // 0x08000000 [27] EP13_OUT (0) - // 0x04000000 [26] EP13_IN (0) - // 0x02000000 [25] EP12_OUT (0) - // 0x01000000 [24] EP12_IN (0) - // 0x00800000 [23] EP11_OUT (0) - // 0x00400000 [22] EP11_IN (0) - // 0x00200000 [21] EP10_OUT (0) - // 0x00100000 [20] EP10_IN (0) - // 0x00080000 [19] EP9_OUT (0) - // 0x00040000 [18] EP9_IN (0) - // 0x00020000 [17] EP8_OUT (0) - // 0x00010000 [16] EP8_IN (0) - // 0x00008000 [15] EP7_OUT (0) - // 0x00004000 [14] EP7_IN (0) - // 0x00002000 [13] EP6_OUT (0) - // 0x00001000 [12] EP6_IN (0) - // 0x00000800 [11] EP5_OUT (0) - // 0x00000400 [10] EP5_IN (0) - // 0x00000200 [9] EP4_OUT (0) - // 0x00000100 [8] EP4_IN (0) - // 0x00000080 [7] EP3_OUT (0) - // 0x00000040 [6] EP3_IN (0) - // 0x00000020 [5] EP2_OUT (0) - // 0x00000010 [4] EP2_IN (0) - // 0x00000008 [3] EP1_OUT (0) - // 0x00000004 [2] EP1_IN (0) - // 0x00000002 [1] EP0_OUT (0) - // 0x00000001 [0] EP0_IN (0) - io_rw_32 ep_nak_stall_status; - - _REG_(USB_USB_MUXING_OFFSET) // USB_USB_MUXING - // Where to connect the USB controller - // 0x00000008 [3] SOFTCON (0) - // 0x00000004 [2] TO_DIGITAL_PAD (0) - // 0x00000002 [1] TO_EXTPHY (0) - // 0x00000001 [0] TO_PHY (0) - io_rw_32 muxing; - - _REG_(USB_USB_PWR_OFFSET) // USB_USB_PWR - // Overrides for the power signals in the event that the VBUS signals are not hooked up to GPIO - // 0x00000020 [5] OVERCURR_DETECT_EN (0) - // 0x00000010 [4] OVERCURR_DETECT (0) - // 0x00000008 [3] VBUS_DETECT_OVERRIDE_EN (0) - // 0x00000004 [2] VBUS_DETECT (0) - // 0x00000002 [1] VBUS_EN_OVERRIDE_EN (0) - // 0x00000001 [0] VBUS_EN (0) - io_rw_32 pwr; - - _REG_(USB_USBPHY_DIRECT_OFFSET) // USB_USBPHY_DIRECT - // Note that most functions are driven directly from usb_fsls controller - // 0x00400000 [22] DM_OVV (0) Status bit from USB PHY - // 0x00200000 [21] DP_OVV (0) Status bit from USB PHY - // 0x00100000 [20] DM_OVCN (0) Status bit from USB PHY - // 0x00080000 [19] DP_OVCN (0) Status bit from USB PHY - // 0x00040000 [18] RX_DM (0) Status bit from USB PHY + - // 0x00020000 [17] RX_DP (0) Status bit from USB PHY + - // 0x00010000 [16] RX_DD (0) Status bit from USB PHY + - // 0x00008000 [15] TX_DIFFMODE (0) - // 0x00004000 [14] TX_FSSLEW (0) - // 0x00002000 [13] TX_PD (0) - // 0x00001000 [12] RX_PD (0) - // 0x00000800 [11] TX_DM (0) Value to drive to USB PHY when override enable is set... - // 0x00000400 [10] TX_DP (0) Value to drive to USB PHY when override enable is set... - // 0x00000200 [9] TX_DM_OE (0) Value to drive to USB PHY when override enable is set... - // 0x00000100 [8] TX_DP_OE (0) Value to drive to USB PHY when override enable is set... - // 0x00000040 [6] DM_PULLDN_EN (0) Value to drive to USB PHY when override enable is set... - // 0x00000020 [5] DM_PULLUP_EN (0) Value to drive to USB PHY when override enable is set... - // 0x00000010 [4] DM_PULLUP_HISEL (0) when dm_pullup_en is set high, this enables second resistor - // 0x00000004 [2] DP_PULLDN_EN (0) Value to drive to USB PHY when override enable is set... - // 0x00000002 [1] DP_PULLUP_EN (0) Value to drive to USB PHY when override enable is set... - // 0x00000001 [0] DP_PULLUP_HISEL (0) when dp_pullup_en is set high, this enables second resistor - io_rw_32 phy_direct; - - _REG_(USB_USBPHY_DIRECT_OVERRIDE_OFFSET) // USB_USBPHY_DIRECT_OVERRIDE - // 0x00008000 [15] TX_DIFFMODE_OVERRIDE_EN (0) - // 0x00001000 [12] DM_PULLUP_OVERRIDE_EN (0) - // 0x00000800 [11] TX_FSSLEW_OVERRIDE_EN (0) - // 0x00000400 [10] TX_PD_OVERRIDE_EN (0) - // 0x00000200 [9] RX_PD_OVERRIDE_EN (0) - // 0x00000100 [8] TX_DM_OVERRIDE_EN (0) Override default value or value driven from USB Controller to PHY - // 0x00000080 [7] TX_DP_OVERRIDE_EN (0) Override default value or value driven from USB Controller to PHY - // 0x00000040 [6] TX_DM_OE_OVERRIDE_EN (0) Override default value or value driven from USB Controller to PHY - // 0x00000020 [5] TX_DP_OE_OVERRIDE_EN (0) Override default value or value driven from USB Controller to PHY - // 0x00000010 [4] DM_PULLDN_EN_OVERRIDE_EN (0) Override default value or value driven from USB Controller to PHY - // 0x00000008 [3] DP_PULLDN_EN_OVERRIDE_EN (0) Override default value or value driven from USB Controller to PHY - // 0x00000004 [2] DP_PULLUP_EN_OVERRIDE_EN (0) Override default value or value driven from USB Controller to PHY - // 0x00000002 [1] DM_PULLUP_HISEL_OVERRIDE_EN (0) - // 0x00000001 [0] DP_PULLUP_HISEL_OVERRIDE_EN (0) - io_rw_32 phy_direct_override; - - _REG_(USB_USBPHY_TRIM_OFFSET) // USB_USBPHY_TRIM - // Note that most functions are driven directly from usb_fsls controller - // 0x00001f00 [12:8] DM_PULLDN_TRIM (0x1f) Value to drive to USB PHY + - // 0x0000001f [4:0] DP_PULLDN_TRIM (0x1f) Value to drive to USB PHY + - io_rw_32 phy_trim; - - uint32_t _pad0; - - _REG_(USB_INTR_OFFSET) // USB_INTR - // Raw Interrupts - // 0x00080000 [19] EP_STALL_NAK (0) Raised when any bit in EP_STATUS_STALL_NAK is set - // 0x00040000 [18] ABORT_DONE (0) Raised when any bit in ABORT_DONE is set - // 0x00020000 [17] DEV_SOF (0) Set every time the device receives a SOF (Start of Frame) packet - // 0x00010000 [16] SETUP_REQ (0) Device - // 0x00008000 [15] DEV_RESUME_FROM_HOST (0) Set when the device receives a resume from the host - // 0x00004000 [14] DEV_SUSPEND (0) Set when the device suspend state changes - // 0x00002000 [13] DEV_CONN_DIS (0) Set when the device connection state changes - // 0x00001000 [12] BUS_RESET (0) Source: SIE_STATUS - // 0x00000800 [11] VBUS_DETECT (0) Source: SIE_STATUS - // 0x00000400 [10] STALL (0) Source: SIE_STATUS - // 0x00000200 [9] ERROR_CRC (0) Source: SIE_STATUS - // 0x00000100 [8] ERROR_BIT_STUFF (0) Source: SIE_STATUS - // 0x00000080 [7] ERROR_RX_OVERFLOW (0) Source: SIE_STATUS - // 0x00000040 [6] ERROR_RX_TIMEOUT (0) Source: SIE_STATUS - // 0x00000020 [5] ERROR_DATA_SEQ (0) Source: SIE_STATUS - // 0x00000010 [4] BUFF_STATUS (0) Raised when any bit in BUFF_STATUS is set - // 0x00000008 [3] TRANS_COMPLETE (0) Raised every time SIE_STATUS - // 0x00000004 [2] HOST_SOF (0) Host: raised every time the host sends a SOF (Start of Frame) - // 0x00000002 [1] HOST_RESUME (0) Host: raised when a device wakes up the host - // 0x00000001 [0] HOST_CONN_DIS (0) Host: raised when a device is connected or disconnected (i - io_ro_32 intr; - - _REG_(USB_INTE_OFFSET) // USB_INTE - // Interrupt Enable - // 0x00080000 [19] EP_STALL_NAK (0) Raised when any bit in EP_STATUS_STALL_NAK is set - // 0x00040000 [18] ABORT_DONE (0) Raised when any bit in ABORT_DONE is set - // 0x00020000 [17] DEV_SOF (0) Set every time the device receives a SOF (Start of Frame) packet - // 0x00010000 [16] SETUP_REQ (0) Device - // 0x00008000 [15] DEV_RESUME_FROM_HOST (0) Set when the device receives a resume from the host - // 0x00004000 [14] DEV_SUSPEND (0) Set when the device suspend state changes - // 0x00002000 [13] DEV_CONN_DIS (0) Set when the device connection state changes - // 0x00001000 [12] BUS_RESET (0) Source: SIE_STATUS - // 0x00000800 [11] VBUS_DETECT (0) Source: SIE_STATUS - // 0x00000400 [10] STALL (0) Source: SIE_STATUS - // 0x00000200 [9] ERROR_CRC (0) Source: SIE_STATUS - // 0x00000100 [8] ERROR_BIT_STUFF (0) Source: SIE_STATUS - // 0x00000080 [7] ERROR_RX_OVERFLOW (0) Source: SIE_STATUS - // 0x00000040 [6] ERROR_RX_TIMEOUT (0) Source: SIE_STATUS - // 0x00000020 [5] ERROR_DATA_SEQ (0) Source: SIE_STATUS - // 0x00000010 [4] BUFF_STATUS (0) Raised when any bit in BUFF_STATUS is set - // 0x00000008 [3] TRANS_COMPLETE (0) Raised every time SIE_STATUS - // 0x00000004 [2] HOST_SOF (0) Host: raised every time the host sends a SOF (Start of Frame) - // 0x00000002 [1] HOST_RESUME (0) Host: raised when a device wakes up the host - // 0x00000001 [0] HOST_CONN_DIS (0) Host: raised when a device is connected or disconnected (i - io_rw_32 inte; - - _REG_(USB_INTF_OFFSET) // USB_INTF - // Interrupt Force - // 0x00080000 [19] EP_STALL_NAK (0) Raised when any bit in EP_STATUS_STALL_NAK is set - // 0x00040000 [18] ABORT_DONE (0) Raised when any bit in ABORT_DONE is set - // 0x00020000 [17] DEV_SOF (0) Set every time the device receives a SOF (Start of Frame) packet - // 0x00010000 [16] SETUP_REQ (0) Device - // 0x00008000 [15] DEV_RESUME_FROM_HOST (0) Set when the device receives a resume from the host - // 0x00004000 [14] DEV_SUSPEND (0) Set when the device suspend state changes - // 0x00002000 [13] DEV_CONN_DIS (0) Set when the device connection state changes - // 0x00001000 [12] BUS_RESET (0) Source: SIE_STATUS - // 0x00000800 [11] VBUS_DETECT (0) Source: SIE_STATUS - // 0x00000400 [10] STALL (0) Source: SIE_STATUS - // 0x00000200 [9] ERROR_CRC (0) Source: SIE_STATUS - // 0x00000100 [8] ERROR_BIT_STUFF (0) Source: SIE_STATUS - // 0x00000080 [7] ERROR_RX_OVERFLOW (0) Source: SIE_STATUS - // 0x00000040 [6] ERROR_RX_TIMEOUT (0) Source: SIE_STATUS - // 0x00000020 [5] ERROR_DATA_SEQ (0) Source: SIE_STATUS - // 0x00000010 [4] BUFF_STATUS (0) Raised when any bit in BUFF_STATUS is set - // 0x00000008 [3] TRANS_COMPLETE (0) Raised every time SIE_STATUS - // 0x00000004 [2] HOST_SOF (0) Host: raised every time the host sends a SOF (Start of Frame) - // 0x00000002 [1] HOST_RESUME (0) Host: raised when a device wakes up the host - // 0x00000001 [0] HOST_CONN_DIS (0) Host: raised when a device is connected or disconnected (i - io_rw_32 intf; - - _REG_(USB_INTS_OFFSET) // USB_INTS - // Interrupt status after masking & forcing - // 0x00080000 [19] EP_STALL_NAK (0) Raised when any bit in EP_STATUS_STALL_NAK is set - // 0x00040000 [18] ABORT_DONE (0) Raised when any bit in ABORT_DONE is set - // 0x00020000 [17] DEV_SOF (0) Set every time the device receives a SOF (Start of Frame) packet - // 0x00010000 [16] SETUP_REQ (0) Device - // 0x00008000 [15] DEV_RESUME_FROM_HOST (0) Set when the device receives a resume from the host - // 0x00004000 [14] DEV_SUSPEND (0) Set when the device suspend state changes - // 0x00002000 [13] DEV_CONN_DIS (0) Set when the device connection state changes - // 0x00001000 [12] BUS_RESET (0) Source: SIE_STATUS - // 0x00000800 [11] VBUS_DETECT (0) Source: SIE_STATUS - // 0x00000400 [10] STALL (0) Source: SIE_STATUS - // 0x00000200 [9] ERROR_CRC (0) Source: SIE_STATUS - // 0x00000100 [8] ERROR_BIT_STUFF (0) Source: SIE_STATUS - // 0x00000080 [7] ERROR_RX_OVERFLOW (0) Source: SIE_STATUS - // 0x00000040 [6] ERROR_RX_TIMEOUT (0) Source: SIE_STATUS - // 0x00000020 [5] ERROR_DATA_SEQ (0) Source: SIE_STATUS - // 0x00000010 [4] BUFF_STATUS (0) Raised when any bit in BUFF_STATUS is set - // 0x00000008 [3] TRANS_COMPLETE (0) Raised every time SIE_STATUS - // 0x00000004 [2] HOST_SOF (0) Host: raised every time the host sends a SOF (Start of Frame) - // 0x00000002 [1] HOST_RESUME (0) Host: raised when a device wakes up the host - // 0x00000001 [0] HOST_CONN_DIS (0) Host: raised when a device is connected or disconnected (i - io_ro_32 ints; -} usb_hw_t; - -#define usb_hw ((usb_hw_t *)USBCTRL_REGS_BASE) -static_assert(sizeof (usb_hw_t) == 0x009c, ""); - -#endif // _HARDWARE_STRUCTS_USB_H - diff --git a/lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/usb_dpram.h b/lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/usb_dpram.h deleted file mode 100644 index aaa4ec58b8..0000000000 --- a/lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/usb_dpram.h +++ /dev/null @@ -1,128 +0,0 @@ -/** - * Copyright (c) 2024 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _HARDWARE_STRUCTS_USB_DPRAM_H -#define _HARDWARE_STRUCTS_USB_DPRAM_H - -#include "hardware/address_mapped.h" -#include "hardware/regs/usb.h" - -// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_usb -// -// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) -// _REG_(x) will link to the corresponding register in hardware/regs/usb.h. -// -// Bit-field descriptions are of the form: -// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION - - -// 0-15 -#define USB_NUM_ENDPOINTS 16 - -// allow user to restrict number of endpoints available to save RAN -#ifndef USB_MAX_ENDPOINTS -#define USB_MAX_ENDPOINTS USB_NUM_ENDPOINTS -#endif - -// 1-15 -#define USB_HOST_INTERRUPT_ENDPOINTS (USB_NUM_ENDPOINTS - 1) - -// Endpoint buffer control bits -#define USB_BUF_CTRL_FULL 0x00008000u -#define USB_BUF_CTRL_LAST 0x00004000u -#define USB_BUF_CTRL_DATA0_PID 0x00000000u -#define USB_BUF_CTRL_DATA1_PID 0x00002000u -#define USB_BUF_CTRL_SEL 0x00001000u -#define USB_BUF_CTRL_STALL 0x00000800u -#define USB_BUF_CTRL_AVAIL 0x00000400u -#define USB_BUF_CTRL_LEN_MASK 0x000003FFu -#define USB_BUF_CTRL_LEN_LSB 0 - -// ep_inout_ctrl bits -#define EP_CTRL_ENABLE_BITS (1u << 31u) -#define EP_CTRL_DOUBLE_BUFFERED_BITS (1u << 30) -#define EP_CTRL_INTERRUPT_PER_BUFFER (1u << 29) -#define EP_CTRL_INTERRUPT_PER_DOUBLE_BUFFER (1u << 28) -#define EP_CTRL_INTERRUPT_ON_NAK (1u << 16) -#define EP_CTRL_INTERRUPT_ON_STALL (1u << 17) -#define EP_CTRL_BUFFER_TYPE_LSB 26u -#define EP_CTRL_HOST_INTERRUPT_INTERVAL_LSB 16u - -#define USB_DPRAM_SIZE 4096u - -// PICO_CONFIG: USB_DPRAM_MAX, Set amount of USB RAM used by USB system, min=0, max=4096, default=4096, group=hardware_usb -// Allow user to claim some of the USB RAM for themselves -#ifndef USB_DPRAM_MAX -#define USB_DPRAM_MAX USB_DPRAM_SIZE -#endif - -// Define maximum packet sizes -#define USB_MAX_ISO_PACKET_SIZE 1023 -#define USB_MAX_PACKET_SIZE 64 - -typedef struct { - // 4K of DPSRAM at beginning. Note this supports 8, 16, and 32 bit accesses - volatile uint8_t setup_packet[8]; // First 8 bytes are always for setup packets - - // Starts at ep1 - struct usb_device_dpram_ep_ctrl { - io_rw_32 in; - io_rw_32 out; - } ep_ctrl[USB_NUM_ENDPOINTS - 1]; - - // Starts at ep0 - struct usb_device_dpram_ep_buf_ctrl { - io_rw_32 in; - io_rw_32 out; - } ep_buf_ctrl[USB_NUM_ENDPOINTS]; - - // EP0 buffers are fixed. Assumes single buffered mode for EP0 - uint8_t ep0_buf_a[0x40]; - uint8_t ep0_buf_b[0x40]; - - // Rest of DPRAM can be carved up as needed - uint8_t epx_data[USB_DPRAM_MAX - 0x180]; -} usb_device_dpram_t; - -static_assert(sizeof(usb_device_dpram_t) == USB_DPRAM_MAX, ""); -static_assert(offsetof(usb_device_dpram_t, epx_data) == 0x180, ""); - -typedef struct { - // 4K of DPSRAM at beginning. Note this supports 8, 16, and 32 bit accesses - volatile uint8_t setup_packet[8]; // First 8 bytes are always for setup packets - - // Interrupt endpoint control 1 -> 15 - struct usb_host_dpram_ep_ctrl { - io_rw_32 ctrl; - io_rw_32 spare; - } int_ep_ctrl[USB_HOST_INTERRUPT_ENDPOINTS]; - - io_rw_32 epx_buf_ctrl; - io_rw_32 _spare0; - - // Interrupt endpoint buffer control - struct usb_host_dpram_ep_buf_ctrl { - io_rw_32 ctrl; - io_rw_32 spare; - } int_ep_buffer_ctrl[USB_HOST_INTERRUPT_ENDPOINTS]; - - io_rw_32 epx_ctrl; - - uint8_t _spare1[124]; - - // Should start at 0x180 - uint8_t epx_data[USB_DPRAM_MAX - 0x180]; -} usb_host_dpram_t; - -static_assert(sizeof(usb_host_dpram_t) == USB_DPRAM_MAX, ""); -static_assert(offsetof(usb_host_dpram_t, epx_data) == 0x180, ""); - -#define usb_dpram ((usb_device_dpram_t *)USBCTRL_DPRAM_BASE) -#define usbh_dpram ((usb_host_dpram_t *)USBCTRL_DPRAM_BASE) - -static_assert( USB_HOST_INTERRUPT_ENDPOINTS == 15, ""); - -#endif // _HARDWARE_STRUCTS_USB_DPRAM_H \ No newline at end of file diff --git a/lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/vreg_and_chip_reset.h b/lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/vreg_and_chip_reset.h deleted file mode 100644 index 0f16a0a046..0000000000 --- a/lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/vreg_and_chip_reset.h +++ /dev/null @@ -1,54 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _HARDWARE_STRUCTS_VREG_AND_CHIP_RESET_H -#define _HARDWARE_STRUCTS_VREG_AND_CHIP_RESET_H - -/** - * \file rp2040/vreg_and_chip_reset.h - */ - -#include "hardware/address_mapped.h" -#include "hardware/regs/vreg_and_chip_reset.h" - -// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_vreg_and_chip_reset -// -// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) -// _REG_(x) will link to the corresponding register in hardware/regs/vreg_and_chip_reset.h. -// -// Bit-field descriptions are of the form: -// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION - -typedef struct { - _REG_(VREG_AND_CHIP_RESET_VREG_OFFSET) // VREG_AND_CHIP_RESET_VREG - // Voltage regulator control and status - // 0x00001000 [12] ROK (0) regulation status + - // 0x000000f0 [7:4] VSEL (0xb) output voltage select + - // 0x00000002 [1] HIZ (0) high impedance mode select + - // 0x00000001 [0] EN (1) enable + - io_rw_32 vreg; - - _REG_(VREG_AND_CHIP_RESET_BOD_OFFSET) // VREG_AND_CHIP_RESET_BOD - // brown-out detection control - // 0x000000f0 [7:4] VSEL (0x9) threshold select + - // 0x00000001 [0] EN (1) enable + - io_rw_32 bod; - - _REG_(VREG_AND_CHIP_RESET_CHIP_RESET_OFFSET) // VREG_AND_CHIP_RESET_CHIP_RESET - // Chip reset control and status - // 0x01000000 [24] PSM_RESTART_FLAG (0) This is set by psm_restart from the debugger - // 0x00100000 [20] HAD_PSM_RESTART (0) Last reset was from the debug port - // 0x00010000 [16] HAD_RUN (0) Last reset was from the RUN pin - // 0x00000100 [8] HAD_POR (0) Last reset was from the power-on reset or brown-out... - io_rw_32 chip_reset; -} vreg_and_chip_reset_hw_t; - -#define vreg_and_chip_reset_hw ((vreg_and_chip_reset_hw_t *)VREG_AND_CHIP_RESET_BASE) -static_assert(sizeof (vreg_and_chip_reset_hw_t) == 0x000c, ""); - -#endif // _HARDWARE_STRUCTS_VREG_AND_CHIP_RESET_H - diff --git a/lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/watchdog.h b/lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/watchdog.h deleted file mode 100644 index 7667aa499d..0000000000 --- a/lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/watchdog.h +++ /dev/null @@ -1,67 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _HARDWARE_STRUCTS_WATCHDOG_H -#define _HARDWARE_STRUCTS_WATCHDOG_H - -/** - * \file rp2040/watchdog.h - */ - -#include "hardware/address_mapped.h" -#include "hardware/regs/watchdog.h" - -// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_watchdog -// -// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) -// _REG_(x) will link to the corresponding register in hardware/regs/watchdog.h. -// -// Bit-field descriptions are of the form: -// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION - -typedef struct { - _REG_(WATCHDOG_CTRL_OFFSET) // WATCHDOG_CTRL - // Watchdog control - // 0x80000000 [31] TRIGGER (0) Trigger a watchdog reset - // 0x40000000 [30] ENABLE (0) When not enabled the watchdog timer is paused - // 0x04000000 [26] PAUSE_DBG1 (1) Pause the watchdog timer when processor 1 is in debug mode - // 0x02000000 [25] PAUSE_DBG0 (1) Pause the watchdog timer when processor 0 is in debug mode - // 0x01000000 [24] PAUSE_JTAG (1) Pause the watchdog timer when JTAG is accessing the bus fabric - // 0x00ffffff [23:0] TIME (0x000000) Indicates the number of ticks / 2 (see errata RP2040-E1)... - io_rw_32 ctrl; - - _REG_(WATCHDOG_LOAD_OFFSET) // WATCHDOG_LOAD - // Load the watchdog timer. - // 0x00ffffff [23:0] LOAD (0x000000) - io_wo_32 load; - - _REG_(WATCHDOG_REASON_OFFSET) // WATCHDOG_REASON - // Logs the reason for the last reset. - // 0x00000002 [1] FORCE (0) - // 0x00000001 [0] TIMER (0) - io_ro_32 reason; - - // (Description copied from array index 0 register WATCHDOG_SCRATCH0 applies similarly to other array indexes) - _REG_(WATCHDOG_SCRATCH0_OFFSET) // WATCHDOG_SCRATCH0 - // Scratch register - // 0xffffffff [31:0] SCRATCH0 (0x00000000) - io_rw_32 scratch[8]; - - _REG_(WATCHDOG_TICK_OFFSET) // WATCHDOG_TICK - // Controls the tick generator - // 0x000ff800 [19:11] COUNT (-) Count down timer: the remaining number clk_tick cycles... - // 0x00000400 [10] RUNNING (-) Is the tick generator running? - // 0x00000200 [9] ENABLE (1) start / stop tick generation - // 0x000001ff [8:0] CYCLES (0x000) Total number of clk_tick cycles before the next tick - io_rw_32 tick; -} watchdog_hw_t; - -#define watchdog_hw ((watchdog_hw_t *)WATCHDOG_BASE) -static_assert(sizeof (watchdog_hw_t) == 0x0030, ""); - -#endif // _HARDWARE_STRUCTS_WATCHDOG_H - diff --git a/lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/xip.h b/lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/xip.h deleted file mode 100644 index 332e8ccf10..0000000000 --- a/lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/xip.h +++ /dev/null @@ -1,76 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _HARDWARE_STRUCTS_XIP_H -#define _HARDWARE_STRUCTS_XIP_H - -/** - * \file rp2040/xip.h - */ - -#include "hardware/address_mapped.h" -#include "hardware/regs/xip.h" - -// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_xip -// -// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) -// _REG_(x) will link to the corresponding register in hardware/regs/xip.h. -// -// Bit-field descriptions are of the form: -// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION - -typedef struct { - _REG_(XIP_CTRL_OFFSET) // XIP_CTRL - // Cache control - // 0x00000008 [3] POWER_DOWN (0) When 1, the cache memories are powered down - // 0x00000002 [1] ERR_BADWRITE (1) When 1, writes to any alias other than 0x0 (caching,... - // 0x00000001 [0] EN (1) When 1, enable the cache - io_rw_32 ctrl; - - _REG_(XIP_FLUSH_OFFSET) // XIP_FLUSH - // Cache Flush control - // 0x00000001 [0] FLUSH (0) Write 1 to flush the cache - io_wo_32 flush; - - _REG_(XIP_STAT_OFFSET) // XIP_STAT - // Cache Status - // 0x00000004 [2] FIFO_FULL (0) When 1, indicates the XIP streaming FIFO is completely full - // 0x00000002 [1] FIFO_EMPTY (1) When 1, indicates the XIP streaming FIFO is completely empty - // 0x00000001 [0] FLUSH_READY (0) Reads as 0 while a cache flush is in progress, and 1 otherwise - io_ro_32 stat; - - _REG_(XIP_CTR_HIT_OFFSET) // XIP_CTR_HIT - // Cache Hit counter - // 0xffffffff [31:0] CTR_HIT (0x00000000) A 32 bit saturating counter that increments upon each... - io_rw_32 ctr_hit; - - _REG_(XIP_CTR_ACC_OFFSET) // XIP_CTR_ACC - // Cache Access counter - // 0xffffffff [31:0] CTR_ACC (0x00000000) A 32 bit saturating counter that increments upon each... - io_rw_32 ctr_acc; - - _REG_(XIP_STREAM_ADDR_OFFSET) // XIP_STREAM_ADDR - // FIFO stream address - // 0xfffffffc [31:2] STREAM_ADDR (0x00000000) The address of the next word to be streamed from flash... - io_rw_32 stream_addr; - - _REG_(XIP_STREAM_CTR_OFFSET) // XIP_STREAM_CTR - // FIFO stream control - // 0x003fffff [21:0] STREAM_CTR (0x000000) Write a nonzero value to start a streaming read - io_rw_32 stream_ctr; - - _REG_(XIP_STREAM_FIFO_OFFSET) // XIP_STREAM_FIFO - // FIFO stream data - // 0xffffffff [31:0] STREAM_FIFO (0x00000000) Streamed data is buffered here, for retrieval by the system DMA - io_ro_32 stream_fifo; -} xip_ctrl_hw_t; - -#define xip_ctrl_hw ((xip_ctrl_hw_t *)XIP_CTRL_BASE) -static_assert(sizeof (xip_ctrl_hw_t) == 0x0020, ""); - -#endif // _HARDWARE_STRUCTS_XIP_H - diff --git a/lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/xip_ctrl.h b/lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/xip_ctrl.h deleted file mode 100644 index c31569b60f..0000000000 --- a/lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/xip_ctrl.h +++ /dev/null @@ -1,11 +0,0 @@ -/** - * Copyright (c) 2024 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -// Support old header for compatibility (and if included, support old variable name) -#include "hardware/structs/xip.h" -#define XIP_STAT_FIFO_FULL XIP_STAT_FIFO_FULL_BITS -#define XIP_STAT_FIFO_EMPTY XIP_STAT_FIFO_EMPTY_BITS -#define XIP_STAT_FLUSH_RDY XIP_STAT_FLUSH_READY_BITS diff --git a/lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/xosc.h b/lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/xosc.h deleted file mode 100644 index ee5a234f6b..0000000000 --- a/lib/main/pico-sdk/rp2040/hardware_structs/include/hardware/structs/xosc.h +++ /dev/null @@ -1,66 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _HARDWARE_STRUCTS_XOSC_H -#define _HARDWARE_STRUCTS_XOSC_H - -/** - * \file rp2040/xosc.h - */ - -#include "hardware/address_mapped.h" -#include "hardware/regs/xosc.h" - -// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_xosc -// -// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) -// _REG_(x) will link to the corresponding register in hardware/regs/xosc.h. -// -// Bit-field descriptions are of the form: -// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION - -/// \tag::xosc_hw[] -typedef struct { - _REG_(XOSC_CTRL_OFFSET) // XOSC_CTRL - // Crystal Oscillator Control - // 0x00fff000 [23:12] ENABLE (-) On power-up this field is initialised to DISABLE and the... - // 0x00000fff [11:0] FREQ_RANGE (-) Frequency range - io_rw_32 ctrl; - - _REG_(XOSC_STATUS_OFFSET) // XOSC_STATUS - // Crystal Oscillator Status - // 0x80000000 [31] STABLE (0) Oscillator is running and stable - // 0x01000000 [24] BADWRITE (0) An invalid value has been written to CTRL_ENABLE or... - // 0x00001000 [12] ENABLED (-) Oscillator is enabled but not necessarily running and... - // 0x00000003 [1:0] FREQ_RANGE (-) The current frequency range setting, always reads 0 - io_rw_32 status; - - _REG_(XOSC_DORMANT_OFFSET) // XOSC_DORMANT - // Crystal Oscillator pause control - // 0xffffffff [31:0] DORMANT (-) This is used to save power by pausing the XOSC + - io_rw_32 dormant; - - _REG_(XOSC_STARTUP_OFFSET) // XOSC_STARTUP - // Controls the startup delay - // 0x00100000 [20] X4 (-) Multiplies the startup_delay by 4 - // 0x00003fff [13:0] DELAY (-) in multiples of 256*xtal_period - io_rw_32 startup; - - uint32_t _pad0[3]; - - _REG_(XOSC_COUNT_OFFSET) // XOSC_COUNT - // A down counter running at the XOSC frequency which counts to zero and stops. - // 0x000000ff [7:0] COUNT (0x00) - io_rw_32 count; -} xosc_hw_t; -/// \end::xosc_hw[] - -#define xosc_hw ((xosc_hw_t *)XOSC_BASE) -static_assert(sizeof (xosc_hw_t) == 0x0020, ""); - -#endif // _HARDWARE_STRUCTS_XOSC_H - diff --git a/lib/main/pico-sdk/rp2040/pico_platform/include/pico/asm_helper.S b/lib/main/pico-sdk/rp2040/pico_platform/include/pico/asm_helper.S deleted file mode 100644 index aff1fc9ae8..0000000000 --- a/lib/main/pico-sdk/rp2040/pico_platform/include/pico/asm_helper.S +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "pico.h" - -# note we don't do this by default in this file for backwards comaptibility with user code -# that may include this file, but not use unified syntax. Note that this macro does equivalent -# setup to the pico_default_asm macro for inline assembly in C code. -.macro pico_default_asm_setup -.syntax unified -.cpu cortex-m0plus -.thumb -.endm - -// do not put align in here as it is used mid function sometimes -.macro regular_func x -.global \x -.type \x,%function -.thumb_func -\x: -.endm - -.macro weak_func x -.weak \x -.type \x,%function -.thumb_func -\x: -.endm - -.macro regular_func_with_section x -.section .text.\x -regular_func \x -.endm - -// do not put align in here as it is used mid function sometimes -.macro wrapper_func x -regular_func WRAPPER_FUNC_NAME(\x) -.endm - -.macro weak_wrapper_func x -weak_func WRAPPER_FUNC_NAME(\x) -.endm - -# backwards compatibility -.macro __pre_init func, priority_string -.section .preinit_array.\priority_string -.p2align 2 -.word \func -.endm diff --git a/lib/main/pico-sdk/rp2040/pico_platform/include/pico/platform.h b/lib/main/pico-sdk/rp2040/pico_platform/include/pico/platform.h deleted file mode 100644 index c1f9ad330f..0000000000 --- a/lib/main/pico-sdk/rp2040/pico_platform/include/pico/platform.h +++ /dev/null @@ -1,210 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -/** \file platform.h - * \defgroup pico_platform pico_platform - * - * \brief Macros and definitions (and functions when included by non assembly code) for the RP2 family device / architecture - * to provide a common abstraction over low level compiler / platform specifics - * - * This header may be included by assembly code - */ - -#ifndef _PICO_PLATFORM_H -#define _PICO_PLATFORM_H - -#ifndef _PICO_H -#error pico/platform.h should not be included directly; include pico.h instead -#endif - -#include "pico/platform/compiler.h" -#include "pico/platform/sections.h" -#include "pico/platform/panic.h" -#include "hardware/regs/addressmap.h" -#include "hardware/regs/sio.h" - -// PICO_CONFIG: PICO_STACK_SIZE, Minimum amount of stack space reserved in the linker script for each core. See also PICO_CORE1_STACK_SIZE, min=0x100, default=0x800, advanced=true, group=pico_platform -#ifndef PICO_STACK_SIZE -#define PICO_STACK_SIZE _u(0x800) -#endif - -// PICO_CONFIG: PICO_HEAP_SIZE, Minimum amount of heap space reserved by the linker script, min=0x100, default=0x800, advanced=true, group=pico_platform -#ifndef PICO_HEAP_SIZE -#define PICO_HEAP_SIZE _u(0x800) -#endif - -// PICO_CONFIG: PICO_NO_RAM_VECTOR_TABLE, Enable/disable the RAM vector table, type=bool, default=0, advanced=true, group=pico_platform -#ifndef PICO_NO_RAM_VECTOR_TABLE -#define PICO_NO_RAM_VECTOR_TABLE 0 -#endif - -// PICO_CONFIG: PICO_RP2040_B0_SUPPORTED, Whether to include any specific software support for RP2040 B0 revision, type=bool, default=1, advanced=true, group=pico_platform -#ifndef PICO_RP2040_B0_SUPPORTED -#define PICO_RP2040_B0_SUPPORTED 1 -#endif - -// PICO_CONFIG: PICO_FLOAT_SUPPORT_ROM_V1, Include float support code for RP2040 B0 when that chip revision is supported , type=bool, default=1, advanced=true, group=pico_platform -#ifndef PICO_FLOAT_SUPPORT_ROM_V1 -#define PICO_FLOAT_SUPPORT_ROM_V1 1 -#endif - -// PICO_CONFIG: PICO_DOUBLE_SUPPORT_ROM_V1, Include double support code for RP2040 B0 when that chip revision is supported , type=bool, default=1, advanced=true, group=pico_platform -#ifndef PICO_DOUBLE_SUPPORT_ROM_V1 -#define PICO_DOUBLE_SUPPORT_ROM_V1 1 -#endif - -// PICO_CONFIG: PICO_RP2040_B1_SUPPORTED, Whether to include any specific software support for RP2040 B1 revision, type=bool, default=1, advanced=true, group=pico_platform -#ifndef PICO_RP2040_B1_SUPPORTED -#define PICO_RP2040_B1_SUPPORTED 1 -#endif - -// PICO_CONFIG: PICO_RP2040_B2_SUPPORTED, Whether to include any specific software support for RP2040 B2 revision, type=bool, default=1, advanced=true, group=pico_platform -#ifndef PICO_RP2040_B2_SUPPORTED -#define PICO_RP2040_B2_SUPPORTED 1 -#endif - -#ifndef PICO_RAM_VECTOR_TABLE_SIZE -#define PICO_RAM_VECTOR_TABLE_SIZE (VTABLE_FIRST_IRQ + NUM_IRQS) -#endif - -#ifndef __ASSEMBLER__ - -/*! \brief No-op function for the body of tight loops - * \ingroup pico_platform - * - * No-op function intended to be called by any tight hardware polling loop. Using this ubiquitously - * makes it much easier to find tight loops, but also in the future \#ifdef-ed support for lockup - * debugging might be added - */ -static __force_inline void tight_loop_contents(void) {} - -/*! \brief Helper method to busy-wait for at least the given number of cycles - * \ingroup pico_platform - * - * This method is useful for introducing very short delays. - * - * This method busy-waits in a tight loop for the given number of system clock cycles. The total wait time is only accurate to within 2 cycles, - * and this method uses a loop counter rather than a hardware timer, so the method will always take longer than expected if an - * interrupt is handled on the calling core during the busy-wait; you can of course disable interrupts to prevent this. - * - * You can use \ref clock_get_hz(clk_sys) to determine the number of clock cycles per second if you want to convert an actual - * time duration to a number of cycles. - * - * \param minimum_cycles the minimum number of system clock cycles to delay for - */ -static inline void busy_wait_at_least_cycles(uint32_t minimum_cycles) { - pico_default_asm_volatile( - "1: subs %0, #3\n" - "bcs 1b\n" - : "+l" (minimum_cycles) : : "cc", "memory" - ); -} - -// PICO_CONFIG: PICO_NO_FPGA_CHECK, Remove the FPGA platform check for small code size reduction, type=bool, default=1, advanced=true, group=pico_runtime -#ifndef PICO_NO_FPGA_CHECK -#define PICO_NO_FPGA_CHECK 1 -#endif - -#if PICO_NO_FPGA_CHECK -static inline bool running_on_fpga(void) {return false;} -#else -bool running_on_fpga(void); -#endif - -/*! \brief Execute a breakpoint instruction - * \ingroup pico_platform - */ -static __force_inline void __breakpoint(void) { - pico_default_asm_volatile ("bkpt #0" : : : "memory"); -} - -/*! \brief Get the current core number - * \ingroup pico_platform - * - * \return The core number the call was made from - */ -__force_inline static uint get_core_num(void) { - return (*(uint32_t *) (SIO_BASE + SIO_CPUID_OFFSET)); -} - -/*! \brief Get the current exception level on this core - * \ingroup pico_platform - * - * On Cortex-M this is the exception number defined in the architecture - * reference, which is equal to VTABLE_FIRST_IRQ + irq num if inside an - * interrupt handler. (VTABLE_FIRST_IRQ is defined in platform_defs.h). - * - * On Hazard3, this function returns VTABLE_FIRST_IRQ + irq num if inside of - * an external IRQ handler (or a fault from such a handler), and 0 otherwise, - * generally aligning with the Cortex-M values. - * - * \return the exception number if the CPU is handling an exception, or 0 otherwise - */ -static __force_inline uint __get_current_exception(void) { - uint exception; - pico_default_asm_volatile ( "mrs %0, ipsr" : "=l" (exception)); - return exception; -} - -#define host_safe_hw_ptr(x) ((uintptr_t)(x)) -#define native_safe_hw_ptr(x) host_safe_hw_ptr(x) - -/*! \brief Returns the RP2040 chip revision number - * \ingroup pico_platform - * @return the RP2040 chip revision number (1 for B0/B1, 2 for B2) - */ -uint8_t rp2040_chip_version(void); - -/*! \brief Returns the RP2040 rom version number - * \ingroup pico_platform - * @return the RP2040 rom version number (1 for RP2040-B0, 2 for RP2040-B1, 3 for RP2040-B2) - */ -static inline uint8_t rp2040_rom_version(void) { - GCC_Pragma("GCC diagnostic push") - GCC_Pragma("GCC diagnostic ignored \"-Warray-bounds\"") - return *(uint8_t*)0x13; - GCC_Pragma("GCC diagnostic pop") -} - -/*! \brief Multiply two integers using an assembly `MUL` instruction - * \ingroup pico_platform - * - * This multiplies a by b using multiply instruction using the ARM mul instruction regardless of values (the compiler - * might otherwise choose to perform shifts/adds), i.e. this is a 1 cycle operation. - * - * \param a the first operand - * \param b the second operand - * \return a * b - */ -__force_inline static int32_t __mul_instruction(int32_t a, int32_t b) { -#ifdef __riscv -__asm ("mul %0, %0, %1" : "+l" (a) : "l" (b) : ); -#else -pico_default_asm ("muls %0, %1" : "+l" (a) : "l" (b) : "cc"); -#endif -return a; -} - -/*! \brief multiply two integer values using the fastest method possible - * \ingroup pico_platform - * - * Efficiently multiplies value a by possibly constant value b. - * - * If b is known to be constant and not zero or a power of 2, then a mul instruction is used rather than gcc's default - * which is often a slow combination of shifts and adds. If b is a power of 2 then a single shift is of course preferable - * and will be used - * - * \param a the first operand - * \param b the second operand - * \return a * b - */ -#define __fast_mul(a, b) __builtin_choose_expr(__builtin_constant_p(b) && !__builtin_constant_p(a), \ - (__builtin_popcount(b) >= 2 ? __mul_instruction(a,b) : (a)*(b)), \ - (a)*(b)) - -#endif // __ASSEMBLER__ - -#endif diff --git a/lib/main/pico-sdk/rp2040/pico_platform/include/pico/platform/cpu_regs.h b/lib/main/pico-sdk/rp2040/pico_platform/include/pico/platform/cpu_regs.h deleted file mode 100644 index 21ff95af34..0000000000 --- a/lib/main/pico-sdk/rp2040/pico_platform/include/pico/platform/cpu_regs.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -/** \file platform.h - * \defgroup pico_platform pico_platform - * - * \brief Macros and definitions for accessing the CPU registers - * - * This header may be included by assembly code - */ - -#ifndef _PICO_PLATFORM_CPU_REGS_H -#define _PICO_PLATFORM_CPU_REGS_H - -#include "hardware/regs/m0plus.h" -#define ARM_CPU_PREFIXED(x) M0PLUS_ ## x - -#ifndef __ASSEMBLER__ -#include "hardware/structs/m0plus.h" -#define arm_cpu_hw m0plus_hw -#include "hardware/structs/nvic.h" -#include "hardware/structs/scb.h" -#endif - -#endif \ No newline at end of file diff --git a/lib/main/pico-sdk/rp2040/pico_platform/platform.c b/lib/main/pico-sdk/rp2040/pico_platform/platform.c deleted file mode 100644 index 9b00165350..0000000000 --- a/lib/main/pico-sdk/rp2040/pico_platform/platform.c +++ /dev/null @@ -1,39 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "pico.h" -#include "hardware/address_mapped.h" -#include "hardware/regs/tbman.h" -#include "hardware/regs/sysinfo.h" - -// Note we leave the FPGA check in by default so that we can run bug repro -// binaries coming in from the wild on the FPGA platform. It takes up around -// 48 bytes if you include all the calls, so you can pass PICO_NO_FPGA_CHECK=1 -// to remove it. The FPGA check is used to skip initialisation of hardware -// (mainly clock generators and oscillators) that aren't present on FPGA. - -#if !PICO_NO_FPGA_CHECK -// Inline stub provided in header if this code is unused (so folding can be -// done in each TU instead of relying on LTO) -bool running_on_fpga(void) { - return (*(io_ro_32 *)TBMAN_BASE) & TBMAN_PLATFORM_FPGA_BITS; -} -#endif - -#define MANUFACTURER_RPI 0x927 -#define PART_RP2 0x2 - -uint8_t rp2040_chip_version(void) { - // First register of sysinfo is chip id - uint32_t chip_id = *((io_ro_32*)(SYSINFO_BASE + SYSINFO_CHIP_ID_OFFSET)); - uint32_t __unused manufacturer = chip_id & SYSINFO_CHIP_ID_MANUFACTURER_BITS; - uint32_t __unused part = (chip_id & SYSINFO_CHIP_ID_PART_BITS) >> SYSINFO_CHIP_ID_PART_LSB; - assert(manufacturer == MANUFACTURER_RPI); - assert(part == PART_RP2); - // Version 1 == B0/B1 - uint version = (chip_id & SYSINFO_CHIP_ID_REVISION_BITS) >> SYSINFO_CHIP_ID_REVISION_LSB; - return (uint8_t)version; -} \ No newline at end of file diff --git a/lib/main/pico-sdk/rp2040/rp2040_interface_pins.json b/lib/main/pico-sdk/rp2040/rp2040_interface_pins.json deleted file mode 100644 index 91cabd83e3..0000000000 --- a/lib/main/pico-sdk/rp2040/rp2040_interface_pins.json +++ /dev/null @@ -1,95 +0,0 @@ -{ - "interfaces": { - "UART": { - "instances": { - "0": { - "TX": [0, 12, 16, 28], - "RX": [1, 13, 17, 29], - "CTS": [2, 14, 18], - "RTS": [3, 15, 19] - }, - "1": { - "TX": [4, 8, 20, 24], - "RX": [5, 9, 21, 25], - "CTS": [6, 10, 22, 26], - "RTS": [7, 11, 23, 27] - } - }, - "expected_functions": { - "one_of": ["TX", "RX"] - } - }, - "I2C": { - "instances": { - "0": { - "SDA": [0, 4, 8, 12, 16, 20, 24, 28], - "SCL": [1, 5, 9, 13, 17, 21, 25, 29] - }, - "1": { - "SDA": [2, 6, 10, 14, 18, 22, 26], - "SCL": [3, 7, 11, 15, 19, 23, 27] - } - }, - "expected_functions": { - "required": ["SDA", "SCL"] - } - }, - "SPI": { - "instances": { - "0": { - "RX": [0, 4, 16, 20], - "CSN": [1, 5, 17, 21], - "SCK": [2, 6, 18, 22], - "TX": [3, 7, 19, 23] - }, - "1": { - "RX": [8, 12, 24, 28], - "CSN": [9, 13, 25, 29], - "SCK": [10, 14, 26], - "TX": [11, 15, 27] - } - }, - "expected_functions": { - "required": ["SCK"], - "one_of": ["RX", "TX"] - } - }, - "PWM": { - "instances": { - "0": { - "A": [0, 16], - "B": [1, 17] - }, - "1": { - "A": [2, 18], - "B": [3, 19] - }, - "2": { - "A": [4, 20], - "B": [5, 21] - }, - "3": { - "A": [6, 22], - "B": [7, 23] - }, - "4": { - "A": [8, 24], - "B": [9, 25] - }, - "5": { - "A": [10, 26], - "B": [11, 27] - }, - "6": { - "A": [12, 28], - "B": [13, 29] - }, - "7": { - "A": [14], - "B": [15] - } - } - } - }, - "pins": [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29] -} diff --git a/lib/main/pico-sdk/rp2350/README.md b/lib/main/pico-sdk/rp2350/README.md deleted file mode 100644 index 7a710171d2..0000000000 --- a/lib/main/pico-sdk/rp2350/README.md +++ /dev/null @@ -1,6 +0,0 @@ -This directory contains files specific to the RP2350 hardware. It is only used when building for RP2350 platforms, i.e. -`PICO_PLATFORM=rp2350-arm-s` or `PICO_PLATFORM=rp235-riscv` - -`hardware_regs` contains low level hardware register #defines autogenerated from the RP2350 chip definition itself. - -`hardware_structs` contains C structures for accessing memory mapped registers diff --git a/lib/main/pico-sdk/rp2350/boot_stage2/asminclude/boot2_helpers/exit_from_boot2.S b/lib/main/pico-sdk/rp2350/boot_stage2/asminclude/boot2_helpers/exit_from_boot2.S deleted file mode 100644 index cadcd01328..0000000000 --- a/lib/main/pico-sdk/rp2350/boot_stage2/asminclude/boot2_helpers/exit_from_boot2.S +++ /dev/null @@ -1,20 +0,0 @@ -/* - * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _BOOT2_HELPER_EXIT_FROM_BOOT2 -#define _BOOT2_HELPER_EXIT_FROM_BOOT2 - -// Always return through saved ra/lr. On RP2350, boot2 is not responsible for entering -// the flash image. It's just a relocatable function that sets up QMI and flash -// for the best possible XIP. - -#ifdef __riscv - jr t0 -#else - pop {pc} -#endif - -#endif diff --git a/lib/main/pico-sdk/rp2350/boot_stage2/asminclude/boot2_helpers/read_flash_sreg.S b/lib/main/pico-sdk/rp2350/boot_stage2/asminclude/boot2_helpers/read_flash_sreg.S deleted file mode 100644 index 8a69038679..0000000000 --- a/lib/main/pico-sdk/rp2350/boot_stage2/asminclude/boot2_helpers/read_flash_sreg.S +++ /dev/null @@ -1,49 +0,0 @@ -/* - * Copyright (c) 2022 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _BOOT2_HELPER_READ_FLASH_SREG -#define _BOOT2_HELPER_READ_FLASH_SREG - -#include "boot2_helpers/wait_qmi_ready.S" - -// Pass status read cmd into r0/a0. -// Returns status value in r0/a0. - -.global read_flash_sreg -.type read_flash_sreg,%function -#ifdef __riscv -read_flash_sreg: - // wait_qmi_ready does not clobber t1, so use this rather than stack. - mv t1, ra - sw a0, QMI_DIRECT_TX_OFFSET(a3) - // Dummy byte: - sw a0, QMI_DIRECT_TX_OFFSET(a3) - - jal wait_qmi_ready - // Discard first byte, return second - lw a0, QMI_DIRECT_RX_OFFSET(a3) - lw a0, QMI_DIRECT_RX_OFFSET(a3) - jr t1 - -#else - -.thumb_func -read_flash_sreg: - push {lr} - str r0, [r3, #QMI_DIRECT_TX_OFFSET] - // Dummy byte: - str r0, [r3, #QMI_DIRECT_TX_OFFSET] - - bl wait_qmi_ready - // Discard first byte, return second - ldr r0, [r3, #QMI_DIRECT_RX_OFFSET] - ldr r0, [r3, #QMI_DIRECT_RX_OFFSET] - - pop {pc} - -#endif - -#endif diff --git a/lib/main/pico-sdk/rp2350/boot_stage2/asminclude/boot2_helpers/wait_qmi_ready.S b/lib/main/pico-sdk/rp2350/boot_stage2/asminclude/boot2_helpers/wait_qmi_ready.S deleted file mode 100644 index cf191807fd..0000000000 --- a/lib/main/pico-sdk/rp2350/boot_stage2/asminclude/boot2_helpers/wait_qmi_ready.S +++ /dev/null @@ -1,34 +0,0 @@ -/* - * Copyright (c) 2022 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _BOOT2_HELPER_WAIT_SSI_READY -#define _BOOT2_HELPER_WAIT_SSI_READY - -// Wait for QMI direct mode to go idle. Clobbers r0/a0 (Arm/RISC-V) - -#ifdef __riscv - -wait_qmi_ready: -1: - lw a0, QMI_DIRECT_CSR_OFFSET(a3) - andi a0, a0, QMI_DIRECT_CSR_BUSY_BITS - bnez a0, 1b - - ret - -#else - -wait_qmi_ready: -1: - ldr r0, [r3, #QMI_DIRECT_CSR_OFFSET] - lsrs r0, r0, #QMI_DIRECT_CSR_BUSY_LSB + 1 - bcs 1b - - bx lr - -#endif - -#endif diff --git a/lib/main/pico-sdk/rp2350/boot_stage2/boot2_at25sf128a.S b/lib/main/pico-sdk/rp2350/boot_stage2/boot2_at25sf128a.S deleted file mode 100644 index 8682badea8..0000000000 --- a/lib/main/pico-sdk/rp2350/boot_stage2/boot2_at25sf128a.S +++ /dev/null @@ -1,278 +0,0 @@ -// ---------------------------------------------------------------------------- -// Second stage boot code -// Copyright (c) 2019-2021 Raspberry Pi (Trading) Ltd. -// SPDX-License-Identifier: BSD-3-Clause -// -// Device: Adesto AT25SF128A -// Based on W25Q080 code: main difference is the QE bit is being set -// via command 0x31 -// -// Description: Configures AT25SF128A to run in Quad I/O continuous read XIP mode -// -// Details: * Check status register 2 to determine if QSPI mode is enabled, -// and perform an SR2 programming cycle if necessary. -// * Use SSI to perform a dummy 0xEB read command, with the mode -// continuation bits set, so that the flash will not require -// 0xEB instruction prefix on subsequent reads. -// * Configure SSI to write address, mode bits, but no instruction. -// SSI + flash are now jointly in a state where continuous reads -// can take place. -// * Jump to exit pointer passed in via lr. Bootrom passes null, -// in which case this code uses a default 256 byte flash offset -// -// Building: * This code must be position-independent, and use stack only -// * The code will be padded to a size of 256 bytes, including a -// 4-byte checksum. Therefore code size cannot exceed 252 bytes. -// ---------------------------------------------------------------------------- - -#include "pico/asm_helper.S" -#include "hardware/regs/addressmap.h" -#include "hardware/regs/ssi.h" -#include "hardware/regs/pads_qspi.h" - -// todo port to QMI - -// ---------------------------------------------------------------------------- -// Config section -// ---------------------------------------------------------------------------- -// It should be possible to support most flash devices by modifying this section - -// The serial flash interface will run at clk_sys/PICO_FLASH_SPI_CLKDIV. -// This must be a positive, even integer. -// The bootrom is very conservative with SPI frequency, but here we should be -// as aggressive as possible. - -#ifndef PICO_FLASH_SPI_CLKDIV -#define PICO_FLASH_SPI_CLKDIV 4 -#endif -#if PICO_FLASH_SPI_CLKDIV & 1 -#error PICO_FLASH_SPI_CLKDIV must be even -#endif - -// Define interface width: single/dual/quad IO -#define FRAME_FORMAT SSI_CTRLR0_SPI_FRF_VALUE_QUAD - -// For W25Q080 this is the "Read data fast quad IO" instruction: -#define CMD_READ 0xeb - -// "Mode bits" are 8 special bits sent immediately after -// the address bits in a "Read Data Fast Quad I/O" command sequence. -// On W25Q080, the four LSBs are don't care, and if MSBs == 0xa, the -// next read does not require the 0xeb instruction prefix. -#define MODE_CONTINUOUS_READ 0x20 - -// The number of address + mode bits, divided by 4 (always 4, not function of -// interface width). -#define ADDR_L 8 - -// How many clocks of Hi-Z following the mode bits. For W25Q080, 4 dummy cycles -// are required. -#define WAIT_CYCLES 4 - -// If defined, we will read status reg, compare to SREG_DATA, and overwrite -// with our value if the SR doesn't match. -// We do a two-byte write to SR1 (01h cmd) rather than a one-byte write to -// SR2 (31h cmd) as the latter command isn't supported by WX25Q080. -// This isn't great because it will remove block protections. -// A better solution is to use a volatile SR write if your device supports it. -#define PROGRAM_STATUS_REG - -#define CMD_WRITE_ENABLE 0x06 -#define CMD_READ_STATUS 0x05 -#define CMD_READ_STATUS2 0x35 -#define CMD_WRITE_STATUS 0x01 -#define CMD_WRITE_STATUS2 0x31 -#define SREG_DATA 0x02 // Enable quad-SPI mode - -// ---------------------------------------------------------------------------- -// Start of 2nd Stage Boot Code -// ---------------------------------------------------------------------------- - -pico_default_asm_setup - -.section .text - -// On RP2350 boot stage2 is always called as a regular function, and should return normally -regular_func _stage2_boot - push {lr} - - // Set pad configuration: - // - SCLK 8mA drive, no slew limiting - // - SDx disable input Schmitt to reduce delay - - ldr r3, =PADS_QSPI_BASE - movs r0, #(2 << PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_LSB | PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_BITS) - str r0, [r3, #PADS_QSPI_GPIO_QSPI_SCLK_OFFSET] - ldr r0, [r3, #PADS_QSPI_GPIO_QSPI_SD0_OFFSET] - movs r1, #PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_BITS - bics r0, r1 - str r0, [r3, #PADS_QSPI_GPIO_QSPI_SD0_OFFSET] - str r0, [r3, #PADS_QSPI_GPIO_QSPI_SD1_OFFSET] - str r0, [r3, #PADS_QSPI_GPIO_QSPI_SD2_OFFSET] - str r0, [r3, #PADS_QSPI_GPIO_QSPI_SD3_OFFSET] - - ldr r3, =XIP_SSI_BASE - - // Disable SSI to allow further config - movs r1, #0 - str r1, [r3, #SSI_SSIENR_OFFSET] - - // Set baud rate - movs r1, #PICO_FLASH_SPI_CLKDIV - str r1, [r3, #SSI_BAUDR_OFFSET] - - // Set 1-cycle sample delay. If PICO_FLASH_SPI_CLKDIV == 2 then this means, - // if the flash launches data on SCLK posedge, we capture it at the time that - // the next SCLK posedge is launched. This is shortly before that posedge - // arrives at the flash, so data hold time should be ok. For - // PICO_FLASH_SPI_CLKDIV > 2 this pretty much has no effect. - - movs r1, #1 - movs r2, #SSI_RX_SAMPLE_DLY_OFFSET // == 0xf0 so need 8 bits of offset significance - str r1, [r3, r2] - - -// On QSPI parts we usually need a 01h SR-write command to enable QSPI mode -// (i.e. turn WPn and HOLDn into IO2/IO3) -#ifdef PROGRAM_STATUS_REG -program_sregs: -#define CTRL0_SPI_TXRX \ - (7 << SSI_CTRLR0_DFS_32_LSB) | /* 8 bits per data frame */ \ - (SSI_CTRLR0_TMOD_VALUE_TX_AND_RX << SSI_CTRLR0_TMOD_LSB) - - ldr r1, =(CTRL0_SPI_TXRX) - str r1, [r3, #SSI_CTRLR0_OFFSET] - - // Enable SSI and select slave 0 - movs r1, #1 - str r1, [r3, #SSI_SSIENR_OFFSET] - - // Check whether SR needs updating - movs r0, #CMD_READ_STATUS2 - bl read_flash_sreg - movs r2, #SREG_DATA - cmp r0, r2 - beq skip_sreg_programming - - // Send write enable command - movs r1, #CMD_WRITE_ENABLE - str r1, [r3, #SSI_DR0_OFFSET] - - // Poll for completion and discard RX - bl wait_ssi_ready - ldr r1, [r3, #SSI_DR0_OFFSET] - - // Send status write command followed by data bytes - movs r1, #CMD_WRITE_STATUS2 - str r1, [r3, #SSI_DR0_OFFSET] - str r2, [r3, #SSI_DR0_OFFSET] - - bl wait_ssi_ready - ldr r1, [r3, #SSI_DR0_OFFSET] - ldr r1, [r3, #SSI_DR0_OFFSET] - ldr r1, [r3, #SSI_DR0_OFFSET] - - // Poll status register for write completion -1: - movs r0, #CMD_READ_STATUS - bl read_flash_sreg - movs r1, #1 - tst r0, r1 - bne 1b - -skip_sreg_programming: - - // Disable SSI again so that it can be reconfigured - movs r1, #0 - str r1, [r3, #SSI_SSIENR_OFFSET] -#endif - -// Currently the flash expects an 8 bit serial command prefix on every -// transfer, which is a waste of cycles. Perform a dummy Fast Read Quad I/O -// command, with mode bits set such that the flash will not expect a serial -// command prefix on *subsequent* transfers. We don't care about the results -// of the read, the important part is the mode bits. - -dummy_read: -#define CTRLR0_ENTER_XIP \ - (FRAME_FORMAT /* Quad I/O mode */ \ - << SSI_CTRLR0_SPI_FRF_LSB) | \ - (31 << SSI_CTRLR0_DFS_32_LSB) | /* 32 data bits */ \ - (SSI_CTRLR0_TMOD_VALUE_EEPROM_READ /* Send INST/ADDR, Receive Data */ \ - << SSI_CTRLR0_TMOD_LSB) - - ldr r1, =(CTRLR0_ENTER_XIP) - str r1, [r3, #SSI_CTRLR0_OFFSET] - - movs r1, #0x0 // NDF=0 (single 32b read) - str r1, [r3, #SSI_CTRLR1_OFFSET] - -#define SPI_CTRLR0_ENTER_XIP \ - (ADDR_L << SSI_SPI_CTRLR0_ADDR_L_LSB) | /* Address + mode bits */ \ - (WAIT_CYCLES << SSI_SPI_CTRLR0_WAIT_CYCLES_LSB) | /* Hi-Z dummy clocks following address + mode */ \ - (SSI_SPI_CTRLR0_INST_L_VALUE_8B \ - << SSI_SPI_CTRLR0_INST_L_LSB) | /* 8-bit instruction */ \ - (SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_1C2A /* Send Command in serial mode then address in Quad I/O mode */ \ - << SSI_SPI_CTRLR0_TRANS_TYPE_LSB) - - ldr r1, =(SPI_CTRLR0_ENTER_XIP) - ldr r0, =(XIP_SSI_BASE + SSI_SPI_CTRLR0_OFFSET) // SPI_CTRL0 Register - str r1, [r0] - - movs r1, #1 // Re-enable SSI - str r1, [r3, #SSI_SSIENR_OFFSET] - - movs r1, #CMD_READ - str r1, [r3, #SSI_DR0_OFFSET] // Push SPI command into TX FIFO - movs r1, #MODE_CONTINUOUS_READ // 32-bit: 24 address bits (we don't care, so 0) and M[7:4]=1010 - str r1, [r3, #SSI_DR0_OFFSET] // Push Address into TX FIFO - this will trigger the transaction - - // Poll for completion - bl wait_ssi_ready - -// The flash is in a state where we can blast addresses in parallel, and get -// parallel data back. Now configure the SSI to translate XIP bus accesses -// into QSPI transfers of this form. - - movs r1, #0 - str r1, [r3, #SSI_SSIENR_OFFSET] // Disable SSI (and clear FIFO) to allow further config - -// Note that the INST_L field is used to select what XIP data gets pushed into -// the TX FIFO: -// INST_L_0_BITS {ADDR[23:0],XIP_CMD[7:0]} Load "mode bits" into XIP_CMD -// Anything else {XIP_CMD[7:0],ADDR[23:0]} Load SPI command into XIP_CMD -configure_ssi: -#define SPI_CTRLR0_XIP \ - (MODE_CONTINUOUS_READ /* Mode bits to keep flash in continuous read mode */ \ - << SSI_SPI_CTRLR0_XIP_CMD_LSB) | \ - (ADDR_L << SSI_SPI_CTRLR0_ADDR_L_LSB) | /* Total number of address + mode bits */ \ - (WAIT_CYCLES << SSI_SPI_CTRLR0_WAIT_CYCLES_LSB) | /* Hi-Z dummy clocks following address + mode */ \ - (SSI_SPI_CTRLR0_INST_L_VALUE_NONE /* Do not send a command, instead send XIP_CMD as mode bits after address */ \ - << SSI_SPI_CTRLR0_INST_L_LSB) | \ - (SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_2C2A /* Send Address in Quad I/O mode (and Command but that is zero bits long) */ \ - << SSI_SPI_CTRLR0_TRANS_TYPE_LSB) - - ldr r1, =(SPI_CTRLR0_XIP) - ldr r0, =(XIP_SSI_BASE + SSI_SPI_CTRLR0_OFFSET) - str r1, [r0] - - movs r1, #1 - str r1, [r3, #SSI_SSIENR_OFFSET] // Re-enable SSI - -// Bus accesses to the XIP window will now be transparently serviced by the -// external flash on cache miss. We are ready to run code from flash. - -// Pull in standard exit routine -#include "boot2_helpers/exit_from_boot2.S" - -// Common functions -#include "boot2_helpers/wait_ssi_ready.S" -#ifdef PROGRAM_STATUS_REG -#include "boot2_helpers/read_flash_sreg.S" -#endif - -.global literals -literals: -.ltorg - -.end diff --git a/lib/main/pico-sdk/rp2350/boot_stage2/boot2_generic_03h.S b/lib/main/pico-sdk/rp2350/boot_stage2/boot2_generic_03h.S deleted file mode 100644 index 4e14a4c7be..0000000000 --- a/lib/main/pico-sdk/rp2350/boot_stage2/boot2_generic_03h.S +++ /dev/null @@ -1,121 +0,0 @@ -// ---------------------------------------------------------------------------- -// Second stage boot code -// Copyright (c) 2019-2021 Raspberry Pi (Trading) Ltd. -// SPDX-License-Identifier: BSD-3-Clause -// -// Device: Anything which responds to 03h serial read command -// -// Details: * Configure SSI to translate each APB read into a 03h command -// * 8 command clocks, 24 address clocks and 32 data clocks -// * This enables you to boot from almost anything: you can pretty -// much solder a potato to your PCB, or a piece of cheese -// * The tradeoff is performance around 3x worse than QSPI XIP -// -// Building: * This code must be position-independent, and use stack only -// * The code will be padded to a size of 256 bytes, including a -// 4-byte checksum. Therefore code size cannot exceed 252 bytes. -// ---------------------------------------------------------------------------- - -#include "pico/asm_helper.S" -#include "hardware/regs/addressmap.h" -#include "hardware/regs/qmi.h" - -// ---------------------------------------------------------------------------- -// Config section -// ---------------------------------------------------------------------------- -// It should be possible to support most flash devices by modifying this section - -// The serial flash interface will run at clk_sys/PICO_FLASH_SPI_CLKDIV. -// This must be a positive integer. -// The bootrom is very conservative with SPI frequency, but here we should be -// as aggressive as possible. - -#ifndef PICO_FLASH_SPI_CLKDIV -#define PICO_FLASH_SPI_CLKDIV 4 -#endif -#if (PICO_FLASH_SPI_CLKDIV << QMI_M0_TIMING_CLKDIV_LSB) & ~QMI_M0_TIMING_CLKDIV_BITS -#error "CLKDIV greater than maximum" -#endif - -// RX sampling delay is measured in units of one half clock cycle. - -#ifndef PICO_FLASH_SPI_RXDELAY -#define PICO_FLASH_SPI_RXDELAY 1 -#endif -#if (PICO_FLASH_SPI_RXDELAY << QMI_M0_TIMING_RXDELAY_LSB) & ~QMI_M0_TIMING_RXDELAY_BITS -#error "RX delay greater than maximum" -#endif - -#define CMD_READ 0x03 - -// ---------------------------------------------------------------------------- -// Register initialisation values -- same in Arm/RISC-V code. -// ---------------------------------------------------------------------------- - -// The QMI is automatically configured for 03h XIP straight out of reset, -// but this code can't assume it's still in that state. Set up memory -// window 0 for 03h serial reads. - -// Setup timing parameters: short sequential-access cooldown, configured -// CLKDIV and RXDELAY, and no constraints on CS max assertion, CS min -// deassertion, or page boundary burst breaks. - -#define INIT_M0_TIMING (\ - 1 << QMI_M0_TIMING_COOLDOWN_LSB |\ - PICO_FLASH_SPI_RXDELAY << QMI_M0_TIMING_RXDELAY_LSB |\ - PICO_FLASH_SPI_CLKDIV << QMI_M0_TIMING_CLKDIV_LSB |\ -0) - -// Set command constants -#define INIT_M0_RCMD (\ - CMD_READ << QMI_M0_RCMD_PREFIX_LSB |\ -0) - -// Set read format to all-serial with a command prefix -#define INIT_M0_RFMT (\ - QMI_M0_RFMT_PREFIX_WIDTH_VALUE_S << QMI_M0_RFMT_PREFIX_WIDTH_LSB |\ - QMI_M0_RFMT_ADDR_WIDTH_VALUE_S << QMI_M0_RFMT_ADDR_WIDTH_LSB |\ - QMI_M0_RFMT_SUFFIX_WIDTH_VALUE_S << QMI_M0_RFMT_SUFFIX_WIDTH_LSB |\ - QMI_M0_RFMT_DUMMY_WIDTH_VALUE_S << QMI_M0_RFMT_DUMMY_WIDTH_LSB |\ - QMI_M0_RFMT_DATA_WIDTH_VALUE_S << QMI_M0_RFMT_DATA_WIDTH_LSB |\ - QMI_M0_RFMT_PREFIX_LEN_VALUE_8 << QMI_M0_RFMT_PREFIX_LEN_LSB |\ -0) - -// ---------------------------------------------------------------------------- -// Start of 2nd Stage Boot Code -// ---------------------------------------------------------------------------- - -pico_default_asm_setup - -.section .text - -// On RP2350 boot stage2 is always called as a regular function, and should return normally -regular_func _stage2_boot -#ifdef __riscv - mv t0, ra - li a3, XIP_QMI_BASE - li a0, INIT_M0_TIMING - sw a0, QMI_M0_TIMING_OFFSET(a3) - li a0, INIT_M0_RCMD - sw a0, QMI_M0_RCMD_OFFSET(a3) - li a0, INIT_M0_RFMT - sw a0, QMI_M0_RFMT_OFFSET(a3) -#else - push {lr} - ldr r3, =XIP_QMI_BASE - ldr r0, =INIT_M0_TIMING - str r0, [r3, #QMI_M0_TIMING_OFFSET] - ldr r0, =INIT_M0_RCMD - str r0, [r3, #QMI_M0_RCMD_OFFSET] - ldr r0, =INIT_M0_RFMT - str r0, [r3, #QMI_M0_RFMT_OFFSET] -#endif - -// Pull in standard exit routine -#include "boot2_helpers/exit_from_boot2.S" - -#ifndef __riscv -.global literals -literals: -.ltorg -#endif diff --git a/lib/main/pico-sdk/rp2350/boot_stage2/boot2_is25lp080.S b/lib/main/pico-sdk/rp2350/boot_stage2/boot2_is25lp080.S deleted file mode 100644 index e5cc2d4f41..0000000000 --- a/lib/main/pico-sdk/rp2350/boot_stage2/boot2_is25lp080.S +++ /dev/null @@ -1,260 +0,0 @@ -// ---------------------------------------------------------------------------- -// Copyright (c) 2019-2021 Raspberry Pi (Trading) Ltd. -// SPDX-License-Identifier: BSD-3-Clause -// -// Device: ISSI IS25LP080D -// Based on W25Q080 code: main difference is the QE bit being in -// SR1 instead of SR2. -// -// Description: Configures IS25LP080D to run in Quad I/O continuous read XIP mode -// -// Details: * Check status register to determine if QSPI mode is enabled, -// and perform an SR programming cycle if necessary. -// * Use SSI to perform a dummy 0xEB read command, with the mode -// continuation bits set, so that the flash will not require -// 0xEB instruction prefix on subsequent reads. -// * Configure SSI to write address, mode bits, but no instruction. -// SSI + flash are now jointly in a state where continuous reads -// can take place. -// * Set VTOR = 0x10000100 (user vector table immediately after -// this boot2 image). -// * Read stack pointer (MSP) and reset vector from the flash -// vector table; set SP and jump, as though the processor had -// booted directly from flash. -// -// Building: * This code must be linked to run at 0x20027f00 -// * The code will be padded to a size of 256 bytes, including a -// 4-byte checksum. Therefore code size cannot exceed 252 bytes. -// ---------------------------------------------------------------------------- - -#include "pico/asm_helper.S" -#include "hardware/regs/addressmap.h" -#include "hardware/regs/ssi.h" - -// todo port to QMI - -// ---------------------------------------------------------------------------- -// Config section -// ---------------------------------------------------------------------------- -// It should be possible to support most flash devices by modifying this section - -// The serial flash interface will run at clk_sys/PICO_FLASH_SPI_CLKDIV. -// This must be a positive, even integer. -// The bootrom is very conservative with SPI frequency, but here we should be -// as aggressive as possible. -#ifndef PICO_FLASH_SPI_CLKDIV -#define PICO_FLASH_SPI_CLKDIV 4 -#endif - - -// Define interface width: single/dual/quad IO -#define FRAME_FORMAT SSI_CTRLR0_SPI_FRF_VALUE_QUAD - -// For W25Q080 this is the "Read data fast quad IO" instruction: -#define CMD_READ 0xeb - -// "Mode bits" are 8 special bits sent immediately after -// the address bits in a "Read Data Fast Quad I/O" command sequence. -// On W25Q080, the four LSBs are don't care, and if MSBs == 0xa, the -// next read does not require the 0xeb instruction prefix. -#define MODE_CONTINUOUS_READ 0xa0 - -// The number of address + mode bits, divided by 4 (always 4, not function of -// interface width). -#define ADDR_L 8 - -// How many clocks of Hi-Z following the mode bits. For W25Q080, 4 dummy cycles -// are required. -#define WAIT_CYCLES 4 - -// If defined, we will read status reg, compare to SREG_DATA, and overwrite -// with our value if the SR doesn't match. -// This isn't great because it will remove block protections. -// A better solution is to use a volatile SR write if your device supports it. -#define PROGRAM_STATUS_REG - -#define CMD_WRITE_ENABLE 0x06 -#define CMD_READ_STATUS 0x05 -#define CMD_WRITE_STATUS 0x01 -#define SREG_DATA 0x40 // Enable quad-SPI mode - -// ---------------------------------------------------------------------------- -// Start of 2nd Stage Boot Code -// ---------------------------------------------------------------------------- - -pico_default_asm_setup - -.section text -// On RP2350 boot stage2 is always called as a regular function, and should return normally -regular_func _stage2_boot - push {lr} - - ldr r3, =XIP_SSI_BASE // Use as base address where possible - - // Disable SSI to allow further config - movs r1, #0 - str r1, [r3, #SSI_SSIENR_OFFSET] - - // Set baud rate - movs r1, #PICO_FLASH_SPI_CLKDIV - str r1, [r3, #SSI_BAUDR_OFFSET] - -// On QSPI parts we usually need a 01h SR-write command to enable QSPI mode -// (i.e. turn WPn and HOLDn into IO2/IO3) -#ifdef PROGRAM_STATUS_REG -program_sregs: -#define CTRL0_SPI_TXRX \ - (7 << SSI_CTRLR0_DFS_32_LSB) | /* 8 bits per data frame */ \ - (SSI_CTRLR0_TMOD_VALUE_TX_AND_RX << SSI_CTRLR0_TMOD_LSB) - - ldr r1, =(CTRL0_SPI_TXRX) - str r1, [r3, #SSI_CTRLR0_OFFSET] - - // Enable SSI and select slave 0 - movs r1, #1 - str r1, [r3, #SSI_SSIENR_OFFSET] - - // Check whether SR needs updating - ldr r0, =CMD_READ_STATUS - bl read_flash_sreg - ldr r2, =SREG_DATA - cmp r0, r2 - beq skip_sreg_programming - - // Send write enable command - movs r1, #CMD_WRITE_ENABLE - str r1, [r3, #SSI_DR0_OFFSET] - - // Poll for completion and discard RX - bl wait_ssi_ready - ldr r1, [r3, #SSI_DR0_OFFSET] - - // Send status write command followed by data bytes - movs r1, #CMD_WRITE_STATUS - str r1, [r3, #SSI_DR0_OFFSET] - movs r0, #0 - str r2, [r3, #SSI_DR0_OFFSET] - - bl wait_ssi_ready - ldr r1, [r3, #SSI_DR0_OFFSET] - ldr r1, [r3, #SSI_DR0_OFFSET] - - // Poll status register for write completion -1: - ldr r0, =CMD_READ_STATUS - bl read_flash_sreg - movs r1, #1 - tst r0, r1 - bne 1b - -skip_sreg_programming: - - // Send a 0xA3 high-performance-mode instruction -// ldr r1, =0xa3 -// str r1, [r3, #SSI_DR0_OFFSET] -// bl wait_ssi_ready - - // Disable SSI again so that it can be reconfigured - movs r1, #0 - str r1, [r3, #SSI_SSIENR_OFFSET] -#endif - - -// First we need to send the initial command to get us in to Fast Read Quad I/O -// mode. As this transaction requires a command, we can't send it in XIP mode. -// To enter Continuous Read mode as well we need to append 4'b0010 to the address -// bits and then add a further 4 don't care bits. We will construct this by -// specifying a 28-bit address, with the least significant bits being 4'b0010. -// This is just a dummy transaction so we'll perform a read from address zero -// and then discard what comes back. All we really care about is that at the -// end of the transaction, the flash device is in Continuous Read mode -// and from then on will only expect to receive addresses. -dummy_read: -#define CTRLR0_ENTER_XIP \ - (FRAME_FORMAT /* Quad I/O mode */ \ - << SSI_CTRLR0_SPI_FRF_LSB) | \ - (31 << SSI_CTRLR0_DFS_32_LSB) | /* 32 data bits */ \ - (SSI_CTRLR0_TMOD_VALUE_EEPROM_READ /* Send INST/ADDR, Receive Data */ \ - << SSI_CTRLR0_TMOD_LSB) - - ldr r1, =(CTRLR0_ENTER_XIP) - str r1, [r3, #SSI_CTRLR0_OFFSET] - - movs r1, #0x0 // NDF=0 (single 32b read) - str r1, [r3, #SSI_CTRLR1_OFFSET] - -#define SPI_CTRLR0_ENTER_XIP \ - (ADDR_L << SSI_SPI_CTRLR0_ADDR_L_LSB) | /* Address + mode bits */ \ - (WAIT_CYCLES << SSI_SPI_CTRLR0_WAIT_CYCLES_LSB) | /* Hi-Z dummy clocks following address + mode */ \ - (SSI_SPI_CTRLR0_INST_L_VALUE_8B \ - << SSI_SPI_CTRLR0_INST_L_LSB) | /* 8-bit instruction */ \ - (SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_1C2A /* Send Command in serial mode then address in Quad I/O mode */ \ - << SSI_SPI_CTRLR0_TRANS_TYPE_LSB) - - ldr r1, =(SPI_CTRLR0_ENTER_XIP) - ldr r0, =(XIP_SSI_BASE + SSI_SPI_CTRLR0_OFFSET) // SPI_CTRL0 Register - str r1, [r0] - - movs r1, #1 // Re-enable SSI - str r1, [r3, #SSI_SSIENR_OFFSET] - - movs r1, #CMD_READ - str r1, [r3, #SSI_DR0_OFFSET] // Push SPI command into TX FIFO - movs r1, #MODE_CONTINUOUS_READ // 32-bit: 24 address bits (we don't care, so 0) and M[7:4]=1010 - str r1, [r3, #SSI_DR0_OFFSET] // Push Address into TX FIFO - this will trigger the transaction - - // Poll for completion - bl wait_ssi_ready - -// At this point CN# will be deasserted and the SPI clock will not be running. -// The Winbond WX25X10CL device will be in continuous read, dual I/O mode and -// only expecting address bits after the next CN# assertion. So long as we -// send 4'b0010 (and 4 more dummy HiZ bits) after every subsequent 24b address -// then the Winbond device will remain in continuous read mode. This is the -// ideal mode for Execute-In-Place. -// (If we want to exit continuous read mode then we will need to switch back -// to APM mode and generate a 28-bit address phase with the extra nibble set -// to 4'b0000). - - movs r1, #0 - str r1, [r3, #SSI_SSIENR_OFFSET] // Disable SSI (and clear FIFO) to allow further config - -// Note that the INST_L field is used to select what XIP data gets pushed into -// the TX FIFO: -// INST_L_0_BITS {ADDR[23:0],XIP_CMD[7:0]} Load "mode bits" into XIP_CMD -// Anything else {XIP_CMD[7:0],ADDR[23:0]} Load SPI command into XIP_CMD -configure_ssi: -#define SPI_CTRLR0_XIP \ - (MODE_CONTINUOUS_READ /* Mode bits to keep flash in continuous read mode */ \ - << SSI_SPI_CTRLR0_XIP_CMD_LSB) | \ - (ADDR_L << SSI_SPI_CTRLR0_ADDR_L_LSB) | /* Total number of address + mode bits */ \ - (WAIT_CYCLES << SSI_SPI_CTRLR0_WAIT_CYCLES_LSB) | /* Hi-Z dummy clocks following address + mode */ \ - (SSI_SPI_CTRLR0_INST_L_VALUE_NONE /* Do not send a command, instead send XIP_CMD as mode bits after address */ \ - << SSI_SPI_CTRLR0_INST_L_LSB) | \ - (SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_2C2A /* Send Address in Quad I/O mode (and Command but that is zero bits long) */ \ - << SSI_SPI_CTRLR0_TRANS_TYPE_LSB) - - ldr r1, =(SPI_CTRLR0_XIP) - ldr r0, =(XIP_SSI_BASE + SSI_SPI_CTRLR0_OFFSET) - str r1, [r0] - - movs r1, #1 - str r1, [r3, #SSI_SSIENR_OFFSET] // Re-enable SSI - -// We are now in XIP mode, with all transactions using Dual I/O and only -// needing to send 24-bit addresses (plus mode bits) for each read transaction. - -// Pull in standard exit routine -#include "boot2_helpers/exit_from_boot2.S" - -// Common functions -#include "boot2_helpers/wait_ssi_ready.S" -#ifdef PROGRAM_STATUS_REG -#include "boot2_helpers/read_flash_sreg.S" -#endif - -.global literals -literals: -.ltorg - -.end diff --git a/lib/main/pico-sdk/rp2350/boot_stage2/boot2_usb_blinky.S b/lib/main/pico-sdk/rp2350/boot_stage2/boot2_usb_blinky.S deleted file mode 100644 index 4d280e087c..0000000000 --- a/lib/main/pico-sdk/rp2350/boot_stage2/boot2_usb_blinky.S +++ /dev/null @@ -1,51 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "pico/asm_helper.S" - -// Stub second stage which calls into USB bootcode, with parameters. -// USB boot takes two parameters: -// - A GPIO mask for activity LED -- if mask is 0, don't touch GPIOs at all -// - A mask of interfaces to disable. Bit 0 disables MSC, bit 1 disables PICOBoot -// The bootrom passes 0 for both of these parameters, but user code (or this -// second stage) can pass anything. - -#define USB_BOOT_MSD_AND_PICOBOOT 0x0 -#define USB_BOOT_MSD_ONLY 0x2 -#define USB_BOOT_PICOBOOT_ONLY 0x1 - -// Config -#define ACTIVITY_LED 0 -#define BOOT_MODE USB_BOOT_MSD_AND_PICOBOOT - -pico_default_asm_setup - -.section .text - -// On RP2350 boot stage2 is always called as a regular function, and should return normally -regular_func _stage2_boot - movs r7, #0x14 // Pointer to _well_known pointer table in ROM - ldrh r0, [r7, #0] // Offset 0 is 16 bit pointer to function table - ldrh r7, [r7, #4] // Offset 4 is 16 bit pointer to table lookup routine - ldr r1, =('U' | ('B' << 8)) // Symbol for USB Boot - blx r7 - cmp r0, #0 - beq dead - - mov r7, r0 - ldr r0, =(1u << ACTIVITY_LED) // Mask of which GPIO (or GPIOs) to use - movs r1, #BOOT_MODE - blx r7 - -dead: - wfi - b dead - -.global literals -literals: -.ltorg - -.end diff --git a/lib/main/pico-sdk/rp2350/boot_stage2/boot2_w25q080.S b/lib/main/pico-sdk/rp2350/boot_stage2/boot2_w25q080.S deleted file mode 100644 index 9d37e5f5aa..0000000000 --- a/lib/main/pico-sdk/rp2350/boot_stage2/boot2_w25q080.S +++ /dev/null @@ -1,343 +0,0 @@ -// ---------------------------------------------------------------------------- -// Second stage boot code -// Copyright (c) 2019-2022 Raspberry Pi (Trading) Ltd. -// SPDX-License-Identifier: BSD-3-Clause -// -// Device: Winbond W25Q080 -// Also supports W25Q16JV (which has some different SR instructions) -// Also supports AT25SF081 -// Also supports S25FL132K0 -// -// Description: Configures W25Q080 to run in Quad I/O continuous read XIP mode -// -// Details: * Check status register 2 to determine if QSPI mode is enabled, -// and perform an SR2 programming cycle if necessary. -// * Use SSI to perform a dummy 0xEB read command, with the mode -// continuation bits set, so that the flash will not require -// 0xEB instruction prefix on subsequent reads. -// * Configure SSI to write address, mode bits, but no instruction. -// SSI + flash are now jointly in a state where continuous reads -// can take place. -// * Jump to exit pointer passed in via lr. Bootrom passes null, -// in which case this code uses a default 256 byte flash offset -// -// Building: * This code must be position-independent, and use stack only -// * The code will be padded to a size of 256 bytes, including a -// 4-byte checksum. Therefore code size cannot exceed 252 bytes. -// ---------------------------------------------------------------------------- - -#include "pico/asm_helper.S" -#include "hardware/regs/addressmap.h" -#include "hardware/regs/pads_qspi.h" -#include "hardware/regs/qmi.h" - -// ---------------------------------------------------------------------------- -// Config section -// ---------------------------------------------------------------------------- -// It should be possible to support most flash devices by modifying this section - -// The serial flash interface will run at clk_sys/PICO_FLASH_SPI_CLKDIV. -// This must be a positive integer. -// The bootrom is very conservative with SPI frequency, but here we should be -// as aggressive as possible. - -#ifndef PICO_FLASH_SPI_CLKDIV -#define PICO_FLASH_SPI_CLKDIV 2 -#endif -#if (PICO_FLASH_SPI_CLKDIV << QMI_M0_TIMING_CLKDIV_LSB) & ~QMI_M0_TIMING_CLKDIV_BITS -#error "CLKDIV greater than maximum" -#endif - -// RX sampling delay is measured in units of one half clock cycle. - -#ifndef PICO_FLASH_SPI_RXDELAY -#define PICO_FLASH_SPI_RXDELAY 2 -#endif -#if (PICO_FLASH_SPI_RXDELAY << QMI_M0_TIMING_RXDELAY_LSB) & ~QMI_M0_TIMING_RXDELAY_BITS -#error "RX delay greater than maximum" -#endif - -// Define interface width: single/dual/quad IO -#define FRAME_FORMAT SSI_CTRLR0_SPI_FRF_VALUE_QUAD - -// For W25Q080 this is the "Read data fast quad IO" instruction: -#define CMD_READ 0xeb - -// "Mode bits" are 8 special bits sent immediately after -// the address bits in a "Read Data Fast Quad I/O" command sequence. -// On W25Q080, the four LSBs are don't care, and if MSBs == 0xa, the -// next read does not require the 0xeb instruction prefix. -#define MODE_CONTINUOUS_READ 0xa0 - -// How many clocks of Hi-Z following the mode bits. For W25Q080, 4 dummy cycles -// are required. -#define WAIT_CYCLES 4 - -// If defined, we will read status reg, compare to SREG_DATA, and overwrite -// with our value if the SR doesn't match. -// We do a two-byte write to SR1 (01h cmd) rather than a one-byte write to -// SR2 (31h cmd) as the latter command isn't supported by WX25Q080. -// This isn't great because it will remove block protections. -// A better solution is to use a volatile SR write if your device supports it. -#define PROGRAM_STATUS_REG - -#define CMD_WRITE_ENABLE 0x06 -#define CMD_READ_STATUS 0x05 -#define CMD_READ_STATUS2 0x35 -#define CMD_WRITE_STATUS 0x01 -#define SREG_DATA 0x02 // Enable quad-SPI mode - -// ---------------------------------------------------------------------------- -// Register initialisation values -- same in Arm/RISC-V code. -// ---------------------------------------------------------------------------- - -// SCLK: 8mA drive, no slew limiting, input buffer disabled -#define INIT_PAD_SCLK (\ - 2 << PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_LSB | \ - PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_BITS | \ -0) - -// Need to use direct serial mode to send SR commands. Choose a -// conservative direct-mode divisor (5 MHz at 150 MHz clk_sys) -// since the XIP-mode divisor may be unsafe without an RX delay. -#define INIT_DIRECT_CSR (\ - 30 << QMI_DIRECT_CSR_CLKDIV_LSB | \ - QMI_DIRECT_CSR_EN_BITS | \ - QMI_DIRECT_CSR_AUTO_CS0N_BITS | \ -0) - -// Setup timing parameters: short sequential-access cooldown, configured -// CLKDIV and RXDELAY, and no constraints on CS max assertion, CS min -// deassertion, or page boundary burst breaks. -#define INIT_M0_TIMING (\ - 1 << QMI_M0_TIMING_COOLDOWN_LSB |\ - PICO_FLASH_SPI_RXDELAY << QMI_M0_TIMING_RXDELAY_LSB |\ - PICO_FLASH_SPI_CLKDIV << QMI_M0_TIMING_CLKDIV_LSB |\ -0) - -// Set command constants (e.g. EBh + A0h) -#define INIT_M0_RCMD (\ - CMD_READ << QMI_M0_RCMD_PREFIX_LSB |\ - MODE_CONTINUOUS_READ << QMI_M0_RCMD_SUFFIX_LSB |\ -0) - -// Set read format (serial command prefix, everything else quad) -// Initial dummy transfer has a serial EBh prefix, and has XIP mode bits -// set after the address. Subsequent transfers don't need the prefix, as long -// as the mode bits are set correctly. -#define INIT_M0_RFMT (\ - QMI_M0_RFMT_PREFIX_WIDTH_VALUE_S << QMI_M0_RFMT_PREFIX_WIDTH_LSB |\ - QMI_M0_RFMT_ADDR_WIDTH_VALUE_Q << QMI_M0_RFMT_ADDR_WIDTH_LSB |\ - QMI_M0_RFMT_SUFFIX_WIDTH_VALUE_Q << QMI_M0_RFMT_SUFFIX_WIDTH_LSB |\ - QMI_M0_RFMT_DUMMY_WIDTH_VALUE_Q << QMI_M0_RFMT_DUMMY_WIDTH_LSB |\ - QMI_M0_RFMT_DATA_WIDTH_VALUE_Q << QMI_M0_RFMT_DATA_WIDTH_LSB |\ - QMI_M0_RFMT_PREFIX_LEN_VALUE_8 << QMI_M0_RFMT_PREFIX_LEN_LSB |\ - QMI_M0_RFMT_SUFFIX_LEN_VALUE_8 << QMI_M0_RFMT_SUFFIX_LEN_LSB |\ - WAIT_CYCLES << QMI_M0_RFMT_DUMMY_LEN_LSB |\ -0) - -// ---------------------------------------------------------------------------- -// Start of 2nd Stage Boot Code -// ---------------------------------------------------------------------------- - -pico_default_asm_setup -.section .text - -// ---------------------------------------------------------------------------- -// RISC-V implementation - -#ifdef __riscv - -// On RP2350 boot stage2 is always called as a regular function, and should return normally -regular_func _stage2_boot - mv t0, ra -_pad_config: - li a3, PADS_QSPI_BASE - li a0, INIT_PAD_SCLK - sw a0, PADS_QSPI_GPIO_QSPI_SCLK_OFFSET(a3) - // SDx: disable input Schmitt to reduce delay - li a3, PADS_QSPI_BASE + REG_ALIAS_CLR_BITS - li a0, PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_BITS - sw a0, PADS_QSPI_GPIO_QSPI_SD0_OFFSET(a3) - sw a0, PADS_QSPI_GPIO_QSPI_SD1_OFFSET(a3) - sw a0, PADS_QSPI_GPIO_QSPI_SD2_OFFSET(a3) - sw a0, PADS_QSPI_GPIO_QSPI_SD3_OFFSET(a3) - - li a3, XIP_QMI_BASE - -// On QSPI parts we usually need a 01h SR-write command to enable QSPI mode -// (i.e. turn WPn and HOLDn into IO2/IO3) -#ifdef PROGRAM_STATUS_REG -program_sregs: - li a1, INIT_DIRECT_CSR - sw a1, QMI_DIRECT_CSR_OFFSET(a3) - // Wait for cooldown on last XIP transfer to expire, by polling BUSY -1: - lw a1, QMI_DIRECT_CSR_OFFSET(a3) - andi a1, a1, QMI_DIRECT_CSR_BUSY_BITS - bnez a1, 1b - - // Check whether SR needs updating - li a0, CMD_READ_STATUS2 - jal read_flash_sreg - addi a0, a0, -SREG_DATA - beqz a0, _skip_sreg_programming - - // Send write enable command, discard RX - li a0, CMD_WRITE_ENABLE - sw a0, QMI_DIRECT_TX_OFFSET(a3) - jal wait_qmi_ready - lw a0, QMI_DIRECT_RX_OFFSET(a3) - - // Send status write command followed by data bytes - li a0, CMD_WRITE_STATUS - sw a0, QMI_DIRECT_TX_OFFSET(a3) - sw zero, QMI_DIRECT_TX_OFFSET(a3) - li a0, SREG_DATA - sw a0, QMI_DIRECT_TX_OFFSET(a3) - jal wait_qmi_ready - lw a0, QMI_DIRECT_RX_OFFSET(a3) - lw a0, QMI_DIRECT_RX_OFFSET(a3) - lw a0, QMI_DIRECT_RX_OFFSET(a3) - - // Poll status register for write completion -1: - li a0, CMD_READ_STATUS - jal read_flash_sreg - andi a0, a0, 0x1 - bnez a0, 1b - -_skip_sreg_programming: - // Disable direct mode - andi a1, a1, ~QMI_DIRECT_CSR_EN_BITS - sw a1, QMI_DIRECT_CSR_OFFSET(a3) -#endif - -_qmi_config: - li a0, INIT_M0_TIMING - sw a0, QMI_M0_TIMING_OFFSET(a3) - li a0, INIT_M0_RCMD - sw a0, QMI_M0_RCMD_OFFSET(a3) - li a0, INIT_M0_RFMT - sw a0, QMI_M0_RFMT_OFFSET(a3) - - // Dummy transfer - li a1, XIP_NOCACHE_NOALLOC_BASE - lw a1, (a1) - - // Set prefix length to 0, as flash no longer expects to see commands - bclri a0, a0, QMI_M0_RFMT_PREFIX_LEN_LSB - sw a0, QMI_M0_RFMT_OFFSET(a3) - -// ---------------------------------------------------------------------------- -// Arm implementation - -#else - -// On RP2350 boot stage2 is always called as a regular function, and should return normally -regular_func _stage2_boot - push {lr} -_pad_config: - ldr r3, =PADS_QSPI_BASE - movs r0, INIT_PAD_SCLK - str r0, [r3, #PADS_QSPI_GPIO_QSPI_SCLK_OFFSET] - // SDx: disable input Schmitt to reduce delay - adds r3, #REG_ALIAS_CLR_BITS - movs r0, #PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_BITS - str r0, [r3, #PADS_QSPI_GPIO_QSPI_SD0_OFFSET] - str r0, [r3, #PADS_QSPI_GPIO_QSPI_SD1_OFFSET] - str r0, [r3, #PADS_QSPI_GPIO_QSPI_SD2_OFFSET] - str r0, [r3, #PADS_QSPI_GPIO_QSPI_SD3_OFFSET] - - adds r3, (XIP_QMI_BASE - (PADS_QSPI_BASE + REG_ALIAS_CLR_BITS)) - -// On QSPI parts we usually need a 01h SR-write command to enable QSPI mode -// (i.e. turn WPn and HOLDn into IO2/IO3) -#ifdef PROGRAM_STATUS_REG -program_sregs: - - // Need to use direct serial mode to send SR commands. Choose a - // conservative direct-mode divisor (5 MHz at 150 MHz clk_sys) - // since the XIP-mode divisor may be unsafe without an RX delay. - ldr r1, =INIT_DIRECT_CSR - str r1, [r3, #QMI_DIRECT_CSR_OFFSET] - // Need to poll for the cooldown on the last XIP transfer to expire - // (via direct-mode BUSY flag) before it is safe to perform the first - // direct-mode operation -1: - ldr r0, [r3, #QMI_DIRECT_CSR_OFFSET] - tst r0, #QMI_DIRECT_CSR_BUSY_BITS - bne 1b - - // Check whether SR needs updating - movs r0, #CMD_READ_STATUS2 - bl read_flash_sreg - cmp r0, #SREG_DATA - beq _skip_sreg_programming - - // Send write enable command, discard RX - movs r0, #CMD_WRITE_ENABLE - str r0, [r3, #QMI_DIRECT_TX_OFFSET] - bl wait_qmi_ready - ldr r0, [r3, #QMI_DIRECT_RX_OFFSET] - - // Send status write command followed by data bytes - movs r0, #CMD_WRITE_STATUS - str r0, [r3, #QMI_DIRECT_TX_OFFSET] - movs r0, #0 - str r0, [r3, #QMI_DIRECT_TX_OFFSET] - movs r0, #SREG_DATA - str r0, [r3, #QMI_DIRECT_TX_OFFSET] - bl wait_qmi_ready - ldr r0, [r3, #QMI_DIRECT_RX_OFFSET] - ldr r0, [r3, #QMI_DIRECT_RX_OFFSET] - ldr r0, [r3, #QMI_DIRECT_RX_OFFSET] - - // Poll status register for write completion -1: - movs r0, #CMD_READ_STATUS - bl read_flash_sreg - lsrs r0, #1 - bcs 1b - -_skip_sreg_programming: - // Disable direct mode - bics r1, #QMI_DIRECT_CSR_EN_BITS - str r1, [r3, #QMI_DIRECT_CSR_OFFSET] - -#endif - -_qmi_config: - ldr r0, =INIT_M0_TIMING - str r0, [r3, #QMI_M0_TIMING_OFFSET] - ldr r0, =INIT_M0_RCMD - str r0, [r3, #QMI_M0_RCMD_OFFSET] - ldr r0, =INIT_M0_RFMT - str r0, [r3, #QMI_M0_RFMT_OFFSET] - - // Dummy transfer - mov r1, #XIP_NOCACHE_NOALLOC_BASE - ldrb r1, [r1] - - // Set prefix length to 0, as flash no longer expects to see commands - bic r0, #QMI_M0_RFMT_PREFIX_LEN_BITS - str r0, [r3, #QMI_M0_RFMT_OFFSET] - -#endif - -// ---------------------------------------------------------------------------- - -// Pull in standard exit routine -#include "boot2_helpers/exit_from_boot2.S" - -// Common functions -#include "boot2_helpers/wait_qmi_ready.S" -#ifdef PROGRAM_STATUS_REG -#include "boot2_helpers/read_flash_sreg.S" -#endif - -#ifndef __riscv -.global literals -literals: -.ltorg -#endif diff --git a/lib/main/pico-sdk/rp2350/boot_stage2/boot2_w25x10cl.S b/lib/main/pico-sdk/rp2350/boot_stage2/boot2_w25x10cl.S deleted file mode 100644 index 6cdf1ec262..0000000000 --- a/lib/main/pico-sdk/rp2350/boot_stage2/boot2_w25x10cl.S +++ /dev/null @@ -1,193 +0,0 @@ -// ---------------------------------------------------------------------------- -// Second stage boot code -// Copyright (c) 2019-2021 Raspberry Pi (Trading) Ltd. -// SPDX-License-Identifier: BSD-3-Clause -// -// Device: Winbond W25X10CL -// -// Description: Configures W25X10CL to run in Dual I/O continuous read XIP mode -// -// Details: * Disable SSI -// * Configure SSI to generate 8b command + 28b address + 2 wait, -// with address and data using dual SPI mode -// * Enable SSI -// * Generate dummy read with command = 0xBB, top 24b of address -// of 0x000000 followed by M[7:0]=0010zzzz (with the HiZ being -// generated by 2 wait cycles). This leaves the W25X10CL in -// continuous read mode -// * Disable SSI -// * Configure SSI to generate 0b command + 28b address + 2 wait, -// with the extra 4 bits of address LSB being 0x2 to keep the -// W25X10CL in continuous read mode forever -// * Enable SSI -// * Set VTOR = 0x10000100 -// * Read MSP reset vector from 0x10000100 and write to MSP (this -// will also enable XIP mode in the SSI wrapper) -// * Read PC reset vector from 0x10000104 and jump to it -// -// Building: * This code must be linked to run at 0x20000000 -// * The code will be padded to a size of 256 bytes, including a -// 4-byte checksum. Therefore code size cannot exceed 252 bytes. -// ---------------------------------------------------------------------------- - -#include "pico/asm_helper.S" -#include "hardware/regs/addressmap.h" -#include "hardware/regs/ssi.h" - -// The serial flash interface will run at clk_sys/PICO_FLASH_SPI_CLKDIV. -// This must be an even number. -#ifndef PICO_FLASH_SPI_CLKDIV -#define PICO_FLASH_SPI_CLKDIV 4 -#endif - -pico_default_asm_setup - -// todo port to QMI - -// ---------------------------------------------------------------------------- -// The "System Control Block" is a set of internal Cortex-M0+ control registers -// that are memory mapped and accessed like any other H/W register. They have -// fixed addresses in the address map of every Cortex-M0+ system. -// ---------------------------------------------------------------------------- - -.equ SCB_VTOR, 0xE000ED08 // RW Vector Table Offset Register - -// ---------------------------------------------------------------------------- -// Winbond W25X10CL Supported Commands -// Taken from "w25x10cl_reg_021714.pdf" -// ---------------------------------------------------------------------------- - -.equ W25X10CL_CMD_READ_DATA_FAST_DUAL_IO, 0xbb - -// ---------------------------------------------------------------------------- -// Winbond W25X10CL "Mode bits" are 8 special bits sent immediately after -// the address bits in a "Read Data Fast Dual I/O" command sequence. -// Of M[7:4], they say M[7:6] are reserved (set to zero), and bits M[3:0] -// are don't care (we HiZ). Only M[5:4] are used, and they must be set -// to M[5:4] = 2'b10 to enable continuous read mode. -// ---------------------------------------------------------------------------- - -.equ W25X10CL_MODE_CONTINUOUS_READ, 0x20 - -// ---------------------------------------------------------------------------- -// Start of 2nd Stage Boot Code -// ---------------------------------------------------------------------------- - -.org 0 - -.section .text - -// On RP2350 boot stage2 is always called as a regular function, and should return normally -regular_func _stage2_boot - push {lr} - ldr r3, =XIP_SSI_BASE // Use as base address where possible - -// We are primarily interested in setting up Flash for DSPI XIP w/ continuous read - - movs r1, #0 - str r1, [r3, #SSI_SSIENR_OFFSET] // Disable SSI to allow further config - -// The Boot ROM sets a very conservative SPI clock frequency to be sure it can -// read the initial 256 bytes from any device. Here we can be more aggressive. - - movs r1, #PICO_FLASH_SPI_CLKDIV - str r1, [r3, #SSI_BAUDR_OFFSET] // Set SSI Clock - -// First we need to send the initial command to get us in to Fast Read Dual I/O -// mode. As this transaction requires a command, we can't send it in XIP mode. -// To enter Continuous Read mode as well we need to append 4'b0010 to the address -// bits and then add a further 4 don't care bits. We will construct this by -// specifying a 28-bit address, with the least significant bits being 4'b0010. -// This is just a dummy transaction so we'll perform a read from address zero -// and then discard what comes back. All we really care about is that at the -// end of the transaction, the Winbond W25X10CL device is in Continuous Read mode -// and from then on will only expect to receive addresses. - -#define CTRLR0_ENTER_XIP \ - (SSI_CTRLR0_SPI_FRF_VALUE_DUAL /* Dual I/O mode */ \ - << SSI_CTRLR0_SPI_FRF_LSB) | \ - (31 << SSI_CTRLR0_DFS_32_LSB) | /* 32 data bits */ \ - (SSI_CTRLR0_TMOD_VALUE_EEPROM_READ /* Send INST/ADDR, Receive Data */ \ - << SSI_CTRLR0_TMOD_LSB) - - ldr r1, =(CTRLR0_ENTER_XIP) - str r1, [r3, #SSI_CTRLR0_OFFSET] - - movs r1, #0x0 // NDF=0 (single 32b read) - str r1, [r3, #SSI_CTRLR1_OFFSET] - -#define SPI_CTRLR0_ENTER_XIP \ - (7 << SSI_SPI_CTRLR0_ADDR_L_LSB) | /* Send 28 bits (24 address + 4 mode) */ \ - (2 << SSI_SPI_CTRLR0_WAIT_CYCLES_LSB) | /* Hi-Z the other 4 mode bits (2 cycles @ dual I/O = 4 bits) */ \ - (SSI_SPI_CTRLR0_INST_L_VALUE_8B \ - << SSI_SPI_CTRLR0_INST_L_LSB) | /* 8-bit instruction */ \ - (SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_1C2A /* Send Command in serial mode then address in Dual I/O mode */ \ - << SSI_SPI_CTRLR0_TRANS_TYPE_LSB) - - ldr r1, =(SPI_CTRLR0_ENTER_XIP) - ldr r0, =(XIP_SSI_BASE + SSI_SPI_CTRLR0_OFFSET) // SPI_CTRL0 Register - str r1, [r0] - - movs r1, #1 // Re-enable SSI - str r1, [r3, #SSI_SSIENR_OFFSET] - - movs r1, #W25X10CL_CMD_READ_DATA_FAST_DUAL_IO // 8b command = 0xBB - str r1, [r3, #SSI_DR0_OFFSET] // Push SPI command into TX FIFO - movs r1, #0x0000002 // 28-bit Address for dummy read = 0x000000 + 0x2 Mode bits to set M[5:4]=10 - str r1, [r3, #SSI_DR0_OFFSET] // Push Address into TX FIFO - this will trigger the transaction - -// Now we wait for the read transaction to complete by monitoring the SSI -// status register and checking for the "RX FIFO Not Empty" flag to assert. - - movs r1, #SSI_SR_RFNE_BITS -00: - ldr r0, [r3, #SSI_SR_OFFSET] // Read status register - tst r0, r1 // RFNE status flag set? - beq 00b // If not then wait - -// At this point CN# will be deasserted and the SPI clock will not be running. -// The Winbond WX25X10CL device will be in continuous read, dual I/O mode and -// only expecting address bits after the next CN# assertion. So long as we -// send 4'b0010 (and 4 more dummy HiZ bits) after every subsequent 24b address -// then the Winbond device will remain in continuous read mode. This is the -// ideal mode for Execute-In-Place. -// (If we want to exit continuous read mode then we will need to switch back -// to APM mode and generate a 28-bit address phase with the extra nibble set -// to 4'b0000). - - movs r1, #0 - str r1, [r3, #SSI_SSIENR_OFFSET] // Disable SSI (and clear FIFO) to allow further config - -// Note that the INST_L field is used to select what XIP data gets pushed into -// the TX FIFO: -// INST_L_0_BITS {ADDR[23:0],XIP_CMD[7:0]} Load "mode bits" into XIP_CMD -// Anything else {XIP_CMD[7:0],ADDR[23:0]} Load SPI command into XIP_CMD - -#define SPI_CTRLR0_XIP \ - (W25X10CL_MODE_CONTINUOUS_READ /* Mode bits to keep Winbond in continuous read mode */ \ - << SSI_SPI_CTRLR0_XIP_CMD_LSB) | \ - (7 << SSI_SPI_CTRLR0_ADDR_L_LSB) | /* Send 28 bits (24 address + 4 mode) */ \ - (2 << SSI_SPI_CTRLR0_WAIT_CYCLES_LSB) | /* Hi-Z the other 4 mode bits (2 cycles @ dual I/O = 4 bits) */ \ - (SSI_SPI_CTRLR0_INST_L_VALUE_NONE /* Do not send a command, instead send XIP_CMD as mode bits after address */ \ - << SSI_SPI_CTRLR0_INST_L_LSB) | \ - (SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_2C2A /* Send Address in Dual I/O mode (and Command but that is zero bits long) */ \ - << SSI_SPI_CTRLR0_TRANS_TYPE_LSB) - - ldr r1, =(SPI_CTRLR0_XIP) - ldr r0, =(XIP_SSI_BASE + SSI_SPI_CTRLR0_OFFSET) - str r1, [r0] - - movs r1, #1 - str r1, [r3, #SSI_SSIENR_OFFSET] // Re-enable SSI - -// We are now in XIP mode, with all transactions using Dual I/O and only -// needing to send 24-bit addresses (plus mode bits) for each read transaction. - -// Pull in standard exit routine -#include "boot2_helpers/exit_from_boot2.S" - -.global literals -literals: -.ltorg - -.end diff --git a/lib/main/pico-sdk/rp2350/boot_stage2/boot_stage2.ld b/lib/main/pico-sdk/rp2350/boot_stage2/boot_stage2.ld deleted file mode 100644 index 0162414a85..0000000000 --- a/lib/main/pico-sdk/rp2350/boot_stage2/boot_stage2.ld +++ /dev/null @@ -1,13 +0,0 @@ -MEMORY { - /* We are loaded to the top 256 bytes of SRAM, which is above the bootrom - stack. Note 4 bytes occupied by checksum. */ - SRAM(rx) : ORIGIN = 0x20081f00, LENGTH = 252 -} - -SECTIONS { - . = ORIGIN(SRAM); - .text : { - *(.entry) - *(.text) - } >SRAM -} diff --git a/lib/main/pico-sdk/rp2350/boot_stage2/compile_time_choice.S b/lib/main/pico-sdk/rp2350/boot_stage2/compile_time_choice.S deleted file mode 100644 index 5aa2b96cd6..0000000000 --- a/lib/main/pico-sdk/rp2350/boot_stage2/compile_time_choice.S +++ /dev/null @@ -1,19 +0,0 @@ -// ---------------------------------------------------------------------------- -// Second stage boot code -// Copyright (c) 2019-2021 Raspberry Pi (Trading) Ltd. -// SPDX-License-Identifier: BSD-3-Clause -// ---------------------------------------------------------------------------- -// -// This implementation uses the PICO_BOOT_STAGE2_CHOOSE_ preprocessor defines to pick -// amongst a menu of known boot stage 2 implementations, allowing the board -// configuration header to be able to specify the boot stage 2 - -#include "boot_stage2/config.h" - -#ifdef PICO_BUILD_BOOT_STAGE2_NAME - // boot stage 2 is configured by cmake, so use the name specified there - #error PICO_BUILD_BOOT_STAGE2_NAME should not be defined for compile_time_choice builds -#else - // boot stage 2 is selected by board config header, and PICO_BOOT_STAGE2_ASM is set in boot_stage2/config.h - #include PICO_BOOT_STAGE2_ASM -#endif diff --git a/lib/main/pico-sdk/rp2350/boot_stage2/doc.h b/lib/main/pico-sdk/rp2350/boot_stage2/doc.h deleted file mode 100644 index 483dd682ff..0000000000 --- a/lib/main/pico-sdk/rp2350/boot_stage2/doc.h +++ /dev/null @@ -1,4 +0,0 @@ -/** - * \defgroup boot_stage2 boot_stage2 - * \brief Second stage boot loaders responsible for setting up external flash - */ diff --git a/lib/main/pico-sdk/rp2350/boot_stage2/include/boot_stage2/config.h b/lib/main/pico-sdk/rp2350/boot_stage2/include/boot_stage2/config.h deleted file mode 100644 index 61f9b9b53c..0000000000 --- a/lib/main/pico-sdk/rp2350/boot_stage2/include/boot_stage2/config.h +++ /dev/null @@ -1,97 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _BOOT_STAGE2_CONFIG_H_ -#define _BOOT_STAGE2_CONFIG_H_ - -// NOTE THIS HEADER IS INCLUDED FROM ASSEMBLY - -#include "pico/config.h" - -// PICO_CONFIG: PICO_BUILD_BOOT_STAGE2_NAME, Name of the boot stage 2 if selected in the build system, group=boot_stage2 -#ifdef PICO_BUILD_BOOT_STAGE2_NAME - #define _BOOT_STAGE2_SELECTED -#else - // check that multiple boot stage 2 options haven't been set... - -// PICO_CONFIG: PICO_BOOT_STAGE2_CHOOSE_IS25LP080, Select boot2_is25lp080 as the boot stage 2 when no boot stage 2 selection is made by the CMake build, type=bool, default=0, group=boot_stage2 -#ifndef PICO_BOOT_STAGE2_CHOOSE_IS25LP080 - #define PICO_BOOT_STAGE2_CHOOSE_IS25LP080 0 -#elif PICO_BOOT_STAGE2_CHOOSE_IS25LP080 - #ifdef _BOOT_STAGE2_SELECTED - #error multiple boot stage 2 options chosen - #endif - #define _BOOT_STAGE2_SELECTED -#endif -// PICO_CONFIG: PICO_BOOT_STAGE2_CHOOSE_W25Q080, Select boot2_w25q080 as the boot stage 2 when no boot stage 2 selection is made by the CMake build, type=bool, default=0, group=boot_stage2 -#ifndef PICO_BOOT_STAGE2_CHOOSE_W25Q080 - #define PICO_BOOT_STAGE2_CHOOSE_W25Q080 0 -#elif PICO_BOOT_STAGE2_CHOOSE_W25Q080 - #ifdef _BOOT_STAGE2_SELECTED - #error multiple boot stage 2 options chosen - #endif - #define _BOOT_STAGE2_SELECTED -#endif -// PICO_CONFIG: PICO_BOOT_STAGE2_CHOOSE_W25X10CL, Select boot2_w25x10cl as the boot stage 2 when no boot stage 2 selection is made by the CMake build, type=bool, default=0, group=boot_stage2 -#ifndef PICO_BOOT_STAGE2_CHOOSE_W25X10CL - #define PICO_BOOT_STAGE2_CHOOSE_W25X10CL 0 -#elif PICO_BOOT_STAGE2_CHOOSE_W25X10CL - #ifdef _BOOT_STAGE2_SELECTED - #error multiple boot stage 2 options chosen - #endif - #define _BOOT_STAGE2_SELECTED -#endif -// PICO_CONFIG: PICO_BOOT_STAGE2_CHOOSE_AT25SF128A, Select boot2_at25sf128a as the boot stage 2 when no boot stage 2 selection is made by the CMake build, type=bool, default=0, group=boot_stage2 -#ifndef PICO_BOOT_STAGE2_CHOOSE_AT25SF128A - #define PICO_BOOT_STAGE2_CHOOSE_AT25SF128A 0 -#elif PICO_BOOT_STAGE2_CHOOSE_AT25SF128A - #ifdef _BOOT_STAGE2_SELECTED - #error multiple boot stage 2 options chosen - #endif - #define _BOOT_STAGE2_SELECTED -#endif - -// PICO_CONFIG: PICO_BOOT_STAGE2_CHOOSE_GENERIC_03H, Select boot2_generic_03h as the boot stage 2 when no boot stage 2 selection is made by the CMake build, type=bool, default=1, group=boot_stage2 -#if defined(PICO_BOOT_STAGE2_CHOOSE_GENERIC_03H) && PICO_BOOT_STAGE2_CHOOSE_GENERIC_03H - #ifdef _BOOT_STAGE2_SELECTED - #error multiple boot stage 2 options chosen - #endif - #define _BOOT_STAGE2_SELECTED -#endif - -#endif // PICO_BUILD_BOOT_STAGE2_NAME - -#ifdef PICO_BUILD_BOOT_STAGE2_NAME - // boot stage 2 is configured by cmake, so use the name specified there - #define PICO_BOOT_STAGE2_NAME PICO_BUILD_BOOT_STAGE2_NAME -#else - // boot stage 2 is selected by board config header, so we have to do some work - #if PICO_BOOT_STAGE2_CHOOSE_IS25LP080 - #error "IS25LP080 boot2 is broken (FIXME)" - #define _BOOT_STAGE2 boot2_is25lp080 - #elif PICO_BOOT_STAGE2_CHOOSE_W25Q080 - #define _BOOT_STAGE2 boot2_w25q080 - #elif PICO_BOOT_STAGE2_CHOOSE_W25X10CL - #error "W25X10CL boot2 is broken (FIXME)" - #define _BOOT_STAGE2 boot2_w25x10cl - #elif PICO_BOOT_STAGE2_CHOOSE_AT25SF128A - #error "AT25SF128A boot2 is broken (FIXME)" - #define _BOOT_STAGE2 boot2_at25sf128a - #elif !defined(PICO_BOOT_STAGE2_CHOOSE_GENERIC_03H) || PICO_BOOT_STAGE2_CHOOSE_GENERIC_03H - #undef PICO_BOOT_STAGE2_CHOOSE_GENERIC_03H - #define PICO_BOOT_STAGE2_CHOOSE_GENERIC_03H 1 - #define _BOOT_STAGE2 boot2_generic_03h - #else - #error no boot stage 2 is defined by PICO_BOOT_STAGE2_CHOOSE_ macro - #endif - // we can't include cdefs in assembly, so define our own, but avoid conflict with real ones for c inclusion - #define _PICO__STRING(x) #x - #define _PICO__XSTRING(x) _PICO__STRING(x) - #define _PICO__CONCAT1(x, y) x ## y - #define PICO_BOOT_STAGE2_NAME _PICO__XSTRING(_BOOT_STAGE2) - #define PICO_BOOT_STAGE2_ASM _PICO__XSTRING(_PICO__CONCAT1(_BOOT_STAGE2,.S)) -#endif -#endif diff --git a/lib/main/pico-sdk/rp2350/boot_stage2/pad_checksum b/lib/main/pico-sdk/rp2350/boot_stage2/pad_checksum deleted file mode 100644 index 2cbe1ade2e..0000000000 --- a/lib/main/pico-sdk/rp2350/boot_stage2/pad_checksum +++ /dev/null @@ -1,56 +0,0 @@ -#!/usr/bin/env python3 - -import argparse -import sys - - -def any_int(x): - try: - return int(x, 0) - except: - raise argparse.ArgumentTypeError("expected an integer, not '{!r}'".format(x)) - - -def bitrev(x, width): - return int("{:0{w}b}".format(x, w=width)[::-1], 2) - - -parser = argparse.ArgumentParser() -parser.add_argument("ifile", help="Input file (binary)") -parser.add_argument("ofile", help="Output file (assembly)") -parser.add_argument("-p", "--pad", help="Padded size (bytes), including 4-byte checksum, default 256", - type=any_int, default=256) -parser.add_argument("-s", "--seed", help="Checksum seed value, default 0", - type=any_int, default=0) -parser.add_argument("-a", "--arch", default="arm", choices=["arm", "riscv"]) -args = parser.parse_args() - -try: - idata = open(args.ifile, "rb").read() -except: - sys.exit("Could not open input file '{}'".format(args.ifile)) - -if len(idata) > args.pad: - sys.exit("Input file size ({} bytes) too large for final size ({} bytes)".format(len(idata), args.pad)) - -odata = idata + bytes(args.pad - len(idata)) - -# No CRC, as "boot2" is entered by crt0 rather than the bootrom. The bootrom -# can optionally perform a SHA-256 hash check of the entire image, and will -# always at least check for a metadata block which is a valid IMAGE_DEF, so -# the boot2 CRC is redundant. - -# try: -with open(args.ofile, "w") as ofile: - ofile.write("// Padded and checksummed version of: {}\n\n".format(args.ifile)) - if args.arch == "arm": - ofile.write(".cpu cortex-m0plus\n") - ofile.write(".thumb\n\n") - ofile.write(".section .boot2, \"ax\"\n\n") - ofile.write(".global __boot2_entry_point\n") - ofile.write("__boot2_entry_point:\n") - for offs in range(0, len(odata), 16): - chunk = odata[offs:min(offs + 16, len(odata))] - ofile.write(".byte {}\n".format(", ".join("0x{:02x}".format(b) for b in chunk))) -# except: - # sys.exit("Could not open output file '{}'".format(args.ofile)) diff --git a/lib/main/pico-sdk/rp2350/hardware_regs/RP2350.svd b/lib/main/pico-sdk/rp2350/hardware_regs/RP2350.svd deleted file mode 100644 index aa2c36213f..0000000000 --- a/lib/main/pico-sdk/rp2350/hardware_regs/RP2350.svd +++ /dev/null @@ -1,105849 +0,0 @@ - - - - Raspberry Pi - RP2350 - RP - 0.1 - - Dual Cortex-M33 or Hazard3 processors at 150MHz - 520kB on-chip SRAM, in 10 independent banks - Extended low-power sleep states with optional SRAM retention: as low as 10uA DVDD - 8kB of one-time-programmable storage (OTP) - Up to 16MB of external QSPI flash/PSRAM via dedicated QSPI bus - Additional 16MB flash/PSRAM accessible via optional second chip-select - On-chip switched-mode power supply to generate core voltage - Low-quiescent-current LDO mode can be enabled for sleep states - 2x on-chip PLLs for internal or external clock generation - GPIOs are 5V-tolerant (powered), and 3.3V-failsafe (unpowered) - Security features: - Optional boot signing, enforced by on-chip mask ROM, with key fingerprint in OTP - Protected OTP storage for optional boot decryption key - Global bus filtering based on Arm or RISC-V security/privilege levels - Peripherals, GPIOs and DMA channels individually assignable to security domains - Hardware mitigations for fault injection attacks - Hardware SHA-256 accelerator - Peripherals: - 2x UARTs - 2x SPI controllers - 2x I2C controllers - 24x PWM channels - USB 1.1 controller and PHY, with host and device support - 12x PIO state machines - 1x HSTX peripheral - - 32 - 32 - 0xffffffff - 0x00000000 - read-write - - Copyright (c) 2024 Raspberry Pi Ltd. - - SPDX-License-Identifier: BSD-3-Clause - - - CM33 - r1p0 - little - true - true - 8 - 4 - 1 - 1 - false - 52 - - 8 - - - RESETS - 0x40020000 - - 0 - 12 - registers - - - - RESET - 0x00000000 - 0x1fffffff - - - USBCTRL - [28:28] - read-write - - - UART1 - [27:27] - read-write - - - UART0 - [26:26] - read-write - - - TRNG - [25:25] - read-write - - - TIMER1 - [24:24] - read-write - - - TIMER0 - [23:23] - read-write - - - TBMAN - [22:22] - read-write - - - SYSINFO - [21:21] - read-write - - - SYSCFG - [20:20] - read-write - - - SPI1 - [19:19] - read-write - - - SPI0 - [18:18] - read-write - - - SHA256 - [17:17] - read-write - - - PWM - [16:16] - read-write - - - PLL_USB - [15:15] - read-write - - - PLL_SYS - [14:14] - read-write - - - PIO2 - [13:13] - read-write - - - PIO1 - [12:12] - read-write - - - PIO0 - [11:11] - read-write - - - PADS_QSPI - [10:10] - read-write - - - PADS_BANK0 - [9:9] - read-write - - - JTAG - [8:8] - read-write - - - IO_QSPI - [7:7] - read-write - - - IO_BANK0 - [6:6] - read-write - - - I2C1 - [5:5] - read-write - - - I2C0 - [4:4] - read-write - - - HSTX - [3:3] - read-write - - - DMA - [2:2] - read-write - - - BUSCTRL - [1:1] - read-write - - - ADC - [0:0] - read-write - - - - - WDSEL - 0x00000004 - 0x00000000 - - - USBCTRL - [28:28] - read-write - - - UART1 - [27:27] - read-write - - - UART0 - [26:26] - read-write - - - TRNG - [25:25] - read-write - - - TIMER1 - [24:24] - read-write - - - TIMER0 - [23:23] - read-write - - - TBMAN - [22:22] - read-write - - - SYSINFO - [21:21] - read-write - - - SYSCFG - [20:20] - read-write - - - SPI1 - [19:19] - read-write - - - SPI0 - [18:18] - read-write - - - SHA256 - [17:17] - read-write - - - PWM - [16:16] - read-write - - - PLL_USB - [15:15] - read-write - - - PLL_SYS - [14:14] - read-write - - - PIO2 - [13:13] - read-write - - - PIO1 - [12:12] - read-write - - - PIO0 - [11:11] - read-write - - - PADS_QSPI - [10:10] - read-write - - - PADS_BANK0 - [9:9] - read-write - - - JTAG - [8:8] - read-write - - - IO_QSPI - [7:7] - read-write - - - IO_BANK0 - [6:6] - read-write - - - I2C1 - [5:5] - read-write - - - I2C0 - [4:4] - read-write - - - HSTX - [3:3] - read-write - - - DMA - [2:2] - read-write - - - BUSCTRL - [1:1] - read-write - - - ADC - [0:0] - read-write - - - - - RESET_DONE - 0x00000008 - 0x00000000 - - - USBCTRL - [28:28] - read-only - - - UART1 - [27:27] - read-only - - - UART0 - [26:26] - read-only - - - TRNG - [25:25] - read-only - - - TIMER1 - [24:24] - read-only - - - TIMER0 - [23:23] - read-only - - - TBMAN - [22:22] - read-only - - - SYSINFO - [21:21] - read-only - - - SYSCFG - [20:20] - read-only - - - SPI1 - [19:19] - read-only - - - SPI0 - [18:18] - read-only - - - SHA256 - [17:17] - read-only - - - PWM - [16:16] - read-only - - - PLL_USB - [15:15] - read-only - - - PLL_SYS - [14:14] - read-only - - - PIO2 - [13:13] - read-only - - - PIO1 - [12:12] - read-only - - - PIO0 - [11:11] - read-only - - - PADS_QSPI - [10:10] - read-only - - - PADS_BANK0 - [9:9] - read-only - - - JTAG - [8:8] - read-only - - - IO_QSPI - [7:7] - read-only - - - IO_BANK0 - [6:6] - read-only - - - I2C1 - [5:5] - read-only - - - I2C0 - [4:4] - read-only - - - HSTX - [3:3] - read-only - - - DMA - [2:2] - read-only - - - BUSCTRL - [1:1] - read-only - - - ADC - [0:0] - read-only - - - - - - - PSM - 0x40018000 - - 0 - 16 - registers - - - - FRCE_ON - 0x00000000 - Force block out of reset (i.e. power it on) - 0x00000000 - - - PROC1 - [24:24] - read-write - - - PROC0 - [23:23] - read-write - - - ACCESSCTRL - [22:22] - read-write - - - SIO - [21:21] - read-write - - - XIP - [20:20] - read-write - - - SRAM9 - [19:19] - read-write - - - SRAM8 - [18:18] - read-write - - - SRAM7 - [17:17] - read-write - - - SRAM6 - [16:16] - read-write - - - SRAM5 - [15:15] - read-write - - - SRAM4 - [14:14] - read-write - - - SRAM3 - [13:13] - read-write - - - SRAM2 - [12:12] - read-write - - - SRAM1 - [11:11] - read-write - - - SRAM0 - [10:10] - read-write - - - BOOTRAM - [9:9] - read-write - - - ROM - [8:8] - read-write - - - BUSFABRIC - [7:7] - read-write - - - PSM_READY - [6:6] - read-write - - - CLOCKS - [5:5] - read-write - - - RESETS - [4:4] - read-write - - - XOSC - [3:3] - read-write - - - ROSC - [2:2] - read-write - - - OTP - [1:1] - read-write - - - PROC_COLD - [0:0] - read-write - - - - - FRCE_OFF - 0x00000004 - Force into reset (i.e. power it off) - 0x00000000 - - - PROC1 - [24:24] - read-write - - - PROC0 - [23:23] - read-write - - - ACCESSCTRL - [22:22] - read-write - - - SIO - [21:21] - read-write - - - XIP - [20:20] - read-write - - - SRAM9 - [19:19] - read-write - - - SRAM8 - [18:18] - read-write - - - SRAM7 - [17:17] - read-write - - - SRAM6 - [16:16] - read-write - - - SRAM5 - [15:15] - read-write - - - SRAM4 - [14:14] - read-write - - - SRAM3 - [13:13] - read-write - - - SRAM2 - [12:12] - read-write - - - SRAM1 - [11:11] - read-write - - - SRAM0 - [10:10] - read-write - - - BOOTRAM - [9:9] - read-write - - - ROM - [8:8] - read-write - - - BUSFABRIC - [7:7] - read-write - - - PSM_READY - [6:6] - read-write - - - CLOCKS - [5:5] - read-write - - - RESETS - [4:4] - read-write - - - XOSC - [3:3] - read-write - - - ROSC - [2:2] - read-write - - - OTP - [1:1] - read-write - - - PROC_COLD - [0:0] - read-write - - - - - WDSEL - 0x00000008 - Set to 1 if the watchdog should reset this - 0x00000000 - - - PROC1 - [24:24] - read-write - - - PROC0 - [23:23] - read-write - - - ACCESSCTRL - [22:22] - read-write - - - SIO - [21:21] - read-write - - - XIP - [20:20] - read-write - - - SRAM9 - [19:19] - read-write - - - SRAM8 - [18:18] - read-write - - - SRAM7 - [17:17] - read-write - - - SRAM6 - [16:16] - read-write - - - SRAM5 - [15:15] - read-write - - - SRAM4 - [14:14] - read-write - - - SRAM3 - [13:13] - read-write - - - SRAM2 - [12:12] - read-write - - - SRAM1 - [11:11] - read-write - - - SRAM0 - [10:10] - read-write - - - BOOTRAM - [9:9] - read-write - - - ROM - [8:8] - read-write - - - BUSFABRIC - [7:7] - read-write - - - PSM_READY - [6:6] - read-write - - - CLOCKS - [5:5] - read-write - - - RESETS - [4:4] - read-write - - - XOSC - [3:3] - read-write - - - ROSC - [2:2] - read-write - - - OTP - [1:1] - read-write - - - PROC_COLD - [0:0] - read-write - - - - - DONE - 0x0000000c - Is the subsystem ready? - 0x00000000 - - - PROC1 - [24:24] - read-only - - - PROC0 - [23:23] - read-only - - - ACCESSCTRL - [22:22] - read-only - - - SIO - [21:21] - read-only - - - XIP - [20:20] - read-only - - - SRAM9 - [19:19] - read-only - - - SRAM8 - [18:18] - read-only - - - SRAM7 - [17:17] - read-only - - - SRAM6 - [16:16] - read-only - - - SRAM5 - [15:15] - read-only - - - SRAM4 - [14:14] - read-only - - - SRAM3 - [13:13] - read-only - - - SRAM2 - [12:12] - read-only - - - SRAM1 - [11:11] - read-only - - - SRAM0 - [10:10] - read-only - - - BOOTRAM - [9:9] - read-only - - - ROM - [8:8] - read-only - - - BUSFABRIC - [7:7] - read-only - - - PSM_READY - [6:6] - read-only - - - CLOCKS - [5:5] - read-only - - - RESETS - [4:4] - read-only - - - XOSC - [3:3] - read-only - - - ROSC - [2:2] - read-only - - - OTP - [1:1] - read-only - - - PROC_COLD - [0:0] - read-only - - - - - - - CLOCKS - 0x40010000 - - 0 - 212 - registers - - - CLOCKS_IRQ - 30 - - - - CLK_GPOUT0_CTRL - 0x00000000 - Clock control, can be changed on-the-fly (except for auxsrc) - 0x00000000 - - - ENABLED - clock generator is enabled - [28:28] - read-only - - - NUDGE - An edge on this signal shifts the phase of the output by 1 cycle of the input clock - This can be done at any time - [20:20] - read-write - - - PHASE - This delays the enable signal by up to 3 cycles of the input clock - This must be set before the clock is enabled to have any effect - [17:16] - read-write - - - DC50 - Enables duty cycle correction for odd divisors, can be changed on-the-fly - [12:12] - read-write - - - ENABLE - Starts and stops the clock generator cleanly - [11:11] - read-write - - - KILL - Asynchronously kills the clock generator, enable must be set low before deasserting kill - [10:10] - read-write - - - AUXSRC - Selects the auxiliary clock source, will glitch when switching - [8:5] - read-write - - - clksrc_pll_sys - 0 - - - clksrc_gpin0 - 1 - - - clksrc_gpin1 - 2 - - - clksrc_pll_usb - 3 - - - clksrc_pll_usb_primary_ref_opcg - 4 - - - rosc_clksrc - 5 - - - xosc_clksrc - 6 - - - lposc_clksrc - 7 - - - clk_sys - 8 - - - clk_usb - 9 - - - clk_adc - 10 - - - clk_ref - 11 - - - clk_peri - 12 - - - clk_hstx - 13 - - - otp_clk2fc - 14 - - - - - - - CLK_GPOUT0_DIV - 0x00000004 - 0x00010000 - - - INT - Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly - [31:16] - read-write - - - FRAC - Fractional component of the divisor, can be changed on-the-fly - [15:0] - read-write - - - - - CLK_GPOUT0_SELECTED - 0x00000008 - Indicates which src is currently selected (one-hot) - 0x00000001 - - - CLK_GPOUT0_SELECTED - This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. - [0:0] - read-only - - - - - CLK_GPOUT1_CTRL - 0x0000000c - Clock control, can be changed on-the-fly (except for auxsrc) - 0x00000000 - - - ENABLED - clock generator is enabled - [28:28] - read-only - - - NUDGE - An edge on this signal shifts the phase of the output by 1 cycle of the input clock - This can be done at any time - [20:20] - read-write - - - PHASE - This delays the enable signal by up to 3 cycles of the input clock - This must be set before the clock is enabled to have any effect - [17:16] - read-write - - - DC50 - Enables duty cycle correction for odd divisors, can be changed on-the-fly - [12:12] - read-write - - - ENABLE - Starts and stops the clock generator cleanly - [11:11] - read-write - - - KILL - Asynchronously kills the clock generator, enable must be set low before deasserting kill - [10:10] - read-write - - - AUXSRC - Selects the auxiliary clock source, will glitch when switching - [8:5] - read-write - - - clksrc_pll_sys - 0 - - - clksrc_gpin0 - 1 - - - clksrc_gpin1 - 2 - - - clksrc_pll_usb - 3 - - - clksrc_pll_usb_primary_ref_opcg - 4 - - - rosc_clksrc - 5 - - - xosc_clksrc - 6 - - - lposc_clksrc - 7 - - - clk_sys - 8 - - - clk_usb - 9 - - - clk_adc - 10 - - - clk_ref - 11 - - - clk_peri - 12 - - - clk_hstx - 13 - - - otp_clk2fc - 14 - - - - - - - CLK_GPOUT1_DIV - 0x00000010 - 0x00010000 - - - INT - Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly - [31:16] - read-write - - - FRAC - Fractional component of the divisor, can be changed on-the-fly - [15:0] - read-write - - - - - CLK_GPOUT1_SELECTED - 0x00000014 - Indicates which src is currently selected (one-hot) - 0x00000001 - - - CLK_GPOUT1_SELECTED - This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. - [0:0] - read-only - - - - - CLK_GPOUT2_CTRL - 0x00000018 - Clock control, can be changed on-the-fly (except for auxsrc) - 0x00000000 - - - ENABLED - clock generator is enabled - [28:28] - read-only - - - NUDGE - An edge on this signal shifts the phase of the output by 1 cycle of the input clock - This can be done at any time - [20:20] - read-write - - - PHASE - This delays the enable signal by up to 3 cycles of the input clock - This must be set before the clock is enabled to have any effect - [17:16] - read-write - - - DC50 - Enables duty cycle correction for odd divisors, can be changed on-the-fly - [12:12] - read-write - - - ENABLE - Starts and stops the clock generator cleanly - [11:11] - read-write - - - KILL - Asynchronously kills the clock generator, enable must be set low before deasserting kill - [10:10] - read-write - - - AUXSRC - Selects the auxiliary clock source, will glitch when switching - [8:5] - read-write - - - clksrc_pll_sys - 0 - - - clksrc_gpin0 - 1 - - - clksrc_gpin1 - 2 - - - clksrc_pll_usb - 3 - - - clksrc_pll_usb_primary_ref_opcg - 4 - - - rosc_clksrc_ph - 5 - - - xosc_clksrc - 6 - - - lposc_clksrc - 7 - - - clk_sys - 8 - - - clk_usb - 9 - - - clk_adc - 10 - - - clk_ref - 11 - - - clk_peri - 12 - - - clk_hstx - 13 - - - otp_clk2fc - 14 - - - - - - - CLK_GPOUT2_DIV - 0x0000001c - 0x00010000 - - - INT - Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly - [31:16] - read-write - - - FRAC - Fractional component of the divisor, can be changed on-the-fly - [15:0] - read-write - - - - - CLK_GPOUT2_SELECTED - 0x00000020 - Indicates which src is currently selected (one-hot) - 0x00000001 - - - CLK_GPOUT2_SELECTED - This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. - [0:0] - read-only - - - - - CLK_GPOUT3_CTRL - 0x00000024 - Clock control, can be changed on-the-fly (except for auxsrc) - 0x00000000 - - - ENABLED - clock generator is enabled - [28:28] - read-only - - - NUDGE - An edge on this signal shifts the phase of the output by 1 cycle of the input clock - This can be done at any time - [20:20] - read-write - - - PHASE - This delays the enable signal by up to 3 cycles of the input clock - This must be set before the clock is enabled to have any effect - [17:16] - read-write - - - DC50 - Enables duty cycle correction for odd divisors, can be changed on-the-fly - [12:12] - read-write - - - ENABLE - Starts and stops the clock generator cleanly - [11:11] - read-write - - - KILL - Asynchronously kills the clock generator, enable must be set low before deasserting kill - [10:10] - read-write - - - AUXSRC - Selects the auxiliary clock source, will glitch when switching - [8:5] - read-write - - - clksrc_pll_sys - 0 - - - clksrc_gpin0 - 1 - - - clksrc_gpin1 - 2 - - - clksrc_pll_usb - 3 - - - clksrc_pll_usb_primary_ref_opcg - 4 - - - rosc_clksrc_ph - 5 - - - xosc_clksrc - 6 - - - lposc_clksrc - 7 - - - clk_sys - 8 - - - clk_usb - 9 - - - clk_adc - 10 - - - clk_ref - 11 - - - clk_peri - 12 - - - clk_hstx - 13 - - - otp_clk2fc - 14 - - - - - - - CLK_GPOUT3_DIV - 0x00000028 - 0x00010000 - - - INT - Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly - [31:16] - read-write - - - FRAC - Fractional component of the divisor, can be changed on-the-fly - [15:0] - read-write - - - - - CLK_GPOUT3_SELECTED - 0x0000002c - Indicates which src is currently selected (one-hot) - 0x00000001 - - - CLK_GPOUT3_SELECTED - This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. - [0:0] - read-only - - - - - CLK_REF_CTRL - 0x00000030 - Clock control, can be changed on-the-fly (except for auxsrc) - 0x00000000 - - - AUXSRC - Selects the auxiliary clock source, will glitch when switching - [6:5] - read-write - - - clksrc_pll_usb - 0 - - - clksrc_gpin0 - 1 - - - clksrc_gpin1 - 2 - - - clksrc_pll_usb_primary_ref_opcg - 3 - - - - - SRC - Selects the clock source glitchlessly, can be changed on-the-fly - [1:0] - read-write - - - rosc_clksrc_ph - 0 - - - clksrc_clk_ref_aux - 1 - - - xosc_clksrc - 2 - - - lposc_clksrc - 3 - - - - - - - CLK_REF_DIV - 0x00000034 - 0x00010000 - - - INT - Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly - [23:16] - read-write - - - - - CLK_REF_SELECTED - 0x00000038 - Indicates which src is currently selected (one-hot) - 0x00000001 - - - CLK_REF_SELECTED - The glitchless multiplexer does not switch instantaneously (to avoid glitches), so software should poll this register to wait for the switch to complete. This register contains one decoded bit for each of the clock sources enumerated in the CTRL SRC field. At most one of these bits will be set at any time, indicating that clock is currently present at the output of the glitchless mux. Whilst switching is in progress, this register may briefly show all-0s. - [3:0] - read-only - - - - - CLK_SYS_CTRL - 0x0000003c - Clock control, can be changed on-the-fly (except for auxsrc) - 0x00000000 - - - AUXSRC - Selects the auxiliary clock source, will glitch when switching - [7:5] - read-write - - - clksrc_pll_sys - 0 - - - clksrc_pll_usb - 1 - - - rosc_clksrc - 2 - - - xosc_clksrc - 3 - - - clksrc_gpin0 - 4 - - - clksrc_gpin1 - 5 - - - - - SRC - Selects the clock source glitchlessly, can be changed on-the-fly - [0:0] - read-write - - - clk_ref - 0 - - - clksrc_clk_sys_aux - 1 - - - - - - - CLK_SYS_DIV - 0x00000040 - 0x00010000 - - - INT - Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly - [31:16] - read-write - - - FRAC - Fractional component of the divisor, can be changed on-the-fly - [15:0] - read-write - - - - - CLK_SYS_SELECTED - 0x00000044 - Indicates which src is currently selected (one-hot) - 0x00000001 - - - CLK_SYS_SELECTED - The glitchless multiplexer does not switch instantaneously (to avoid glitches), so software should poll this register to wait for the switch to complete. This register contains one decoded bit for each of the clock sources enumerated in the CTRL SRC field. At most one of these bits will be set at any time, indicating that clock is currently present at the output of the glitchless mux. Whilst switching is in progress, this register may briefly show all-0s. - [1:0] - read-only - - - - - CLK_PERI_CTRL - 0x00000048 - Clock control, can be changed on-the-fly (except for auxsrc) - 0x00000000 - - - ENABLED - clock generator is enabled - [28:28] - read-only - - - ENABLE - Starts and stops the clock generator cleanly - [11:11] - read-write - - - KILL - Asynchronously kills the clock generator, enable must be set low before deasserting kill - [10:10] - read-write - - - AUXSRC - Selects the auxiliary clock source, will glitch when switching - [7:5] - read-write - - - clk_sys - 0 - - - clksrc_pll_sys - 1 - - - clksrc_pll_usb - 2 - - - rosc_clksrc_ph - 3 - - - xosc_clksrc - 4 - - - clksrc_gpin0 - 5 - - - clksrc_gpin1 - 6 - - - - - - - CLK_PERI_DIV - 0x0000004c - 0x00010000 - - - INT - Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly - [17:16] - read-write - - - - - CLK_PERI_SELECTED - 0x00000050 - Indicates which src is currently selected (one-hot) - 0x00000001 - - - CLK_PERI_SELECTED - This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. - [0:0] - read-only - - - - - CLK_HSTX_CTRL - 0x00000054 - Clock control, can be changed on-the-fly (except for auxsrc) - 0x00000000 - - - ENABLED - clock generator is enabled - [28:28] - read-only - - - NUDGE - An edge on this signal shifts the phase of the output by 1 cycle of the input clock - This can be done at any time - [20:20] - read-write - - - PHASE - This delays the enable signal by up to 3 cycles of the input clock - This must be set before the clock is enabled to have any effect - [17:16] - read-write - - - ENABLE - Starts and stops the clock generator cleanly - [11:11] - read-write - - - KILL - Asynchronously kills the clock generator, enable must be set low before deasserting kill - [10:10] - read-write - - - AUXSRC - Selects the auxiliary clock source, will glitch when switching - [7:5] - read-write - - - clk_sys - 0 - - - clksrc_pll_sys - 1 - - - clksrc_pll_usb - 2 - - - clksrc_gpin0 - 3 - - - clksrc_gpin1 - 4 - - - - - - - CLK_HSTX_DIV - 0x00000058 - 0x00010000 - - - INT - Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly - [17:16] - read-write - - - - - CLK_HSTX_SELECTED - 0x0000005c - Indicates which src is currently selected (one-hot) - 0x00000001 - - - CLK_HSTX_SELECTED - This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. - [0:0] - read-only - - - - - CLK_USB_CTRL - 0x00000060 - Clock control, can be changed on-the-fly (except for auxsrc) - 0x00000000 - - - ENABLED - clock generator is enabled - [28:28] - read-only - - - NUDGE - An edge on this signal shifts the phase of the output by 1 cycle of the input clock - This can be done at any time - [20:20] - read-write - - - PHASE - This delays the enable signal by up to 3 cycles of the input clock - This must be set before the clock is enabled to have any effect - [17:16] - read-write - - - ENABLE - Starts and stops the clock generator cleanly - [11:11] - read-write - - - KILL - Asynchronously kills the clock generator, enable must be set low before deasserting kill - [10:10] - read-write - - - AUXSRC - Selects the auxiliary clock source, will glitch when switching - [7:5] - read-write - - - clksrc_pll_usb - 0 - - - clksrc_pll_sys - 1 - - - rosc_clksrc_ph - 2 - - - xosc_clksrc - 3 - - - clksrc_gpin0 - 4 - - - clksrc_gpin1 - 5 - - - - - - - CLK_USB_DIV - 0x00000064 - 0x00010000 - - - INT - Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly - [19:16] - read-write - - - - - CLK_USB_SELECTED - 0x00000068 - Indicates which src is currently selected (one-hot) - 0x00000001 - - - CLK_USB_SELECTED - This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. - [0:0] - read-only - - - - - CLK_ADC_CTRL - 0x0000006c - Clock control, can be changed on-the-fly (except for auxsrc) - 0x00000000 - - - ENABLED - clock generator is enabled - [28:28] - read-only - - - NUDGE - An edge on this signal shifts the phase of the output by 1 cycle of the input clock - This can be done at any time - [20:20] - read-write - - - PHASE - This delays the enable signal by up to 3 cycles of the input clock - This must be set before the clock is enabled to have any effect - [17:16] - read-write - - - ENABLE - Starts and stops the clock generator cleanly - [11:11] - read-write - - - KILL - Asynchronously kills the clock generator, enable must be set low before deasserting kill - [10:10] - read-write - - - AUXSRC - Selects the auxiliary clock source, will glitch when switching - [7:5] - read-write - - - clksrc_pll_usb - 0 - - - clksrc_pll_sys - 1 - - - rosc_clksrc_ph - 2 - - - xosc_clksrc - 3 - - - clksrc_gpin0 - 4 - - - clksrc_gpin1 - 5 - - - - - - - CLK_ADC_DIV - 0x00000070 - 0x00010000 - - - INT - Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly - [19:16] - read-write - - - - - CLK_ADC_SELECTED - 0x00000074 - Indicates which src is currently selected (one-hot) - 0x00000001 - - - CLK_ADC_SELECTED - This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. - [0:0] - read-only - - - - - DFTCLK_XOSC_CTRL - 0x00000078 - 0x00000000 - - - SRC - [1:0] - read-write - - - NULL - 0 - - - clksrc_pll_usb_primary - 1 - - - clksrc_gpin0 - 2 - - - - - - - DFTCLK_ROSC_CTRL - 0x0000007c - 0x00000000 - - - SRC - [1:0] - read-write - - - NULL - 0 - - - clksrc_pll_sys_primary_rosc - 1 - - - clksrc_gpin1 - 2 - - - - - - - DFTCLK_LPOSC_CTRL - 0x00000080 - 0x00000000 - - - SRC - [1:0] - read-write - - - NULL - 0 - - - clksrc_pll_usb_primary_lposc - 1 - - - clksrc_gpin1 - 2 - - - - - - - CLK_SYS_RESUS_CTRL - 0x00000084 - 0x000000ff - - - CLEAR - For clearing the resus after the fault that triggered it has been corrected - [16:16] - read-write - - - FRCE - Force a resus, for test purposes only - [12:12] - read-write - - - ENABLE - Enable resus - [8:8] - read-write - - - TIMEOUT - This is expressed as a number of clk_ref cycles - and must be >= 2x clk_ref_freq/min_clk_tst_freq - [7:0] - read-write - - - - - CLK_SYS_RESUS_STATUS - 0x00000088 - 0x00000000 - - - RESUSSED - Clock has been resuscitated, correct the error then send ctrl_clear=1 - [0:0] - read-only - - - - - FC0_REF_KHZ - 0x0000008c - Reference clock frequency in kHz - 0x00000000 - - - FC0_REF_KHZ - [19:0] - read-write - - - - - FC0_MIN_KHZ - 0x00000090 - Minimum pass frequency in kHz. This is optional. Set to 0 if you are not using the pass/fail flags - 0x00000000 - - - FC0_MIN_KHZ - [24:0] - read-write - - - - - FC0_MAX_KHZ - 0x00000094 - Maximum pass frequency in kHz. This is optional. Set to 0x1ffffff if you are not using the pass/fail flags - 0x01ffffff - - - FC0_MAX_KHZ - [24:0] - read-write - - - - - FC0_DELAY - 0x00000098 - Delays the start of frequency counting to allow the mux to settle - Delay is measured in multiples of the reference clock period - 0x00000001 - - - FC0_DELAY - [2:0] - read-write - - - - - FC0_INTERVAL - 0x0000009c - The test interval is 0.98us * 2**interval, but let's call it 1us * 2**interval - The default gives a test interval of 250us - 0x00000008 - - - FC0_INTERVAL - [3:0] - read-write - - - - - FC0_SRC - 0x000000a0 - Clock sent to frequency counter, set to 0 when not required - Writing to this register initiates the frequency count - 0x00000000 - - - FC0_SRC - [7:0] - read-write - - - NULL - 0 - - - pll_sys_clksrc_primary - 1 - - - pll_usb_clksrc_primary - 2 - - - rosc_clksrc - 3 - - - rosc_clksrc_ph - 4 - - - xosc_clksrc - 5 - - - clksrc_gpin0 - 6 - - - clksrc_gpin1 - 7 - - - clk_ref - 8 - - - clk_sys - 9 - - - clk_peri - 10 - - - clk_usb - 11 - - - clk_adc - 12 - - - clk_hstx - 13 - - - lposc_clksrc - 14 - - - otp_clk2fc - 15 - - - pll_usb_clksrc_primary_dft - 16 - - - - - - - FC0_STATUS - 0x000000a4 - Frequency counter status - 0x00000000 - - - DIED - Test clock stopped during test - [28:28] - read-only - - - FAST - Test clock faster than expected, only valid when status_done=1 - [24:24] - read-only - - - SLOW - Test clock slower than expected, only valid when status_done=1 - [20:20] - read-only - - - FAIL - Test failed - [16:16] - read-only - - - WAITING - Waiting for test clock to start - [12:12] - read-only - - - RUNNING - Test running - [8:8] - read-only - - - DONE - Test complete - [4:4] - read-only - - - PASS - Test passed - [0:0] - read-only - - - - - FC0_RESULT - 0x000000a8 - Result of frequency measurement, only valid when status_done=1 - 0x00000000 - - - KHZ - [29:5] - read-only - - - FRAC - [4:0] - read-only - - - - - WAKE_EN0 - 0x000000ac - enable clock in wake mode - 0xffffffff - - - CLK_SYS_SIO - [31:31] - read-write - - - CLK_SYS_SHA256 - [30:30] - read-write - - - CLK_SYS_PSM - [29:29] - read-write - - - CLK_SYS_ROSC - [28:28] - read-write - - - CLK_SYS_ROM - [27:27] - read-write - - - CLK_SYS_RESETS - [26:26] - read-write - - - CLK_SYS_PWM - [25:25] - read-write - - - CLK_SYS_POWMAN - [24:24] - read-write - - - CLK_REF_POWMAN - [23:23] - read-write - - - CLK_SYS_PLL_USB - [22:22] - read-write - - - CLK_SYS_PLL_SYS - [21:21] - read-write - - - CLK_SYS_PIO2 - [20:20] - read-write - - - CLK_SYS_PIO1 - [19:19] - read-write - - - CLK_SYS_PIO0 - [18:18] - read-write - - - CLK_SYS_PADS - [17:17] - read-write - - - CLK_SYS_OTP - [16:16] - read-write - - - CLK_REF_OTP - [15:15] - read-write - - - CLK_SYS_JTAG - [14:14] - read-write - - - CLK_SYS_IO - [13:13] - read-write - - - CLK_SYS_I2C1 - [12:12] - read-write - - - CLK_SYS_I2C0 - [11:11] - read-write - - - CLK_SYS_HSTX - [10:10] - read-write - - - CLK_HSTX - [9:9] - read-write - - - CLK_SYS_GLITCH_DETECTOR - [8:8] - read-write - - - CLK_SYS_DMA - [7:7] - read-write - - - CLK_SYS_BUSFABRIC - [6:6] - read-write - - - CLK_SYS_BUSCTRL - [5:5] - read-write - - - CLK_SYS_BOOTRAM - [4:4] - read-write - - - CLK_SYS_ADC - [3:3] - read-write - - - CLK_ADC - [2:2] - read-write - - - CLK_SYS_ACCESSCTRL - [1:1] - read-write - - - CLK_SYS_CLOCKS - [0:0] - read-write - - - - - WAKE_EN1 - 0x000000b0 - enable clock in wake mode - 0x7fffffff - - - CLK_SYS_XOSC - [30:30] - read-write - - - CLK_SYS_XIP - [29:29] - read-write - - - CLK_SYS_WATCHDOG - [28:28] - read-write - - - CLK_USB - [27:27] - read-write - - - CLK_SYS_USBCTRL - [26:26] - read-write - - - CLK_SYS_UART1 - [25:25] - read-write - - - CLK_PERI_UART1 - [24:24] - read-write - - - CLK_SYS_UART0 - [23:23] - read-write - - - CLK_PERI_UART0 - [22:22] - read-write - - - CLK_SYS_TRNG - [21:21] - read-write - - - CLK_SYS_TIMER1 - [20:20] - read-write - - - CLK_SYS_TIMER0 - [19:19] - read-write - - - CLK_SYS_TICKS - [18:18] - read-write - - - CLK_REF_TICKS - [17:17] - read-write - - - CLK_SYS_TBMAN - [16:16] - read-write - - - CLK_SYS_SYSINFO - [15:15] - read-write - - - CLK_SYS_SYSCFG - [14:14] - read-write - - - CLK_SYS_SRAM9 - [13:13] - read-write - - - CLK_SYS_SRAM8 - [12:12] - read-write - - - CLK_SYS_SRAM7 - [11:11] - read-write - - - CLK_SYS_SRAM6 - [10:10] - read-write - - - CLK_SYS_SRAM5 - [9:9] - read-write - - - CLK_SYS_SRAM4 - [8:8] - read-write - - - CLK_SYS_SRAM3 - [7:7] - read-write - - - CLK_SYS_SRAM2 - [6:6] - read-write - - - CLK_SYS_SRAM1 - [5:5] - read-write - - - CLK_SYS_SRAM0 - [4:4] - read-write - - - CLK_SYS_SPI1 - [3:3] - read-write - - - CLK_PERI_SPI1 - [2:2] - read-write - - - CLK_SYS_SPI0 - [1:1] - read-write - - - CLK_PERI_SPI0 - [0:0] - read-write - - - - - SLEEP_EN0 - 0x000000b4 - enable clock in sleep mode - 0xffffffff - - - CLK_SYS_SIO - [31:31] - read-write - - - CLK_SYS_SHA256 - [30:30] - read-write - - - CLK_SYS_PSM - [29:29] - read-write - - - CLK_SYS_ROSC - [28:28] - read-write - - - CLK_SYS_ROM - [27:27] - read-write - - - CLK_SYS_RESETS - [26:26] - read-write - - - CLK_SYS_PWM - [25:25] - read-write - - - CLK_SYS_POWMAN - [24:24] - read-write - - - CLK_REF_POWMAN - [23:23] - read-write - - - CLK_SYS_PLL_USB - [22:22] - read-write - - - CLK_SYS_PLL_SYS - [21:21] - read-write - - - CLK_SYS_PIO2 - [20:20] - read-write - - - CLK_SYS_PIO1 - [19:19] - read-write - - - CLK_SYS_PIO0 - [18:18] - read-write - - - CLK_SYS_PADS - [17:17] - read-write - - - CLK_SYS_OTP - [16:16] - read-write - - - CLK_REF_OTP - [15:15] - read-write - - - CLK_SYS_JTAG - [14:14] - read-write - - - CLK_SYS_IO - [13:13] - read-write - - - CLK_SYS_I2C1 - [12:12] - read-write - - - CLK_SYS_I2C0 - [11:11] - read-write - - - CLK_SYS_HSTX - [10:10] - read-write - - - CLK_HSTX - [9:9] - read-write - - - CLK_SYS_GLITCH_DETECTOR - [8:8] - read-write - - - CLK_SYS_DMA - [7:7] - read-write - - - CLK_SYS_BUSFABRIC - [6:6] - read-write - - - CLK_SYS_BUSCTRL - [5:5] - read-write - - - CLK_SYS_BOOTRAM - [4:4] - read-write - - - CLK_SYS_ADC - [3:3] - read-write - - - CLK_ADC - [2:2] - read-write - - - CLK_SYS_ACCESSCTRL - [1:1] - read-write - - - CLK_SYS_CLOCKS - [0:0] - read-write - - - - - SLEEP_EN1 - 0x000000b8 - enable clock in sleep mode - 0x7fffffff - - - CLK_SYS_XOSC - [30:30] - read-write - - - CLK_SYS_XIP - [29:29] - read-write - - - CLK_SYS_WATCHDOG - [28:28] - read-write - - - CLK_USB - [27:27] - read-write - - - CLK_SYS_USBCTRL - [26:26] - read-write - - - CLK_SYS_UART1 - [25:25] - read-write - - - CLK_PERI_UART1 - [24:24] - read-write - - - CLK_SYS_UART0 - [23:23] - read-write - - - CLK_PERI_UART0 - [22:22] - read-write - - - CLK_SYS_TRNG - [21:21] - read-write - - - CLK_SYS_TIMER1 - [20:20] - read-write - - - CLK_SYS_TIMER0 - [19:19] - read-write - - - CLK_SYS_TICKS - [18:18] - read-write - - - CLK_REF_TICKS - [17:17] - read-write - - - CLK_SYS_TBMAN - [16:16] - read-write - - - CLK_SYS_SYSINFO - [15:15] - read-write - - - CLK_SYS_SYSCFG - [14:14] - read-write - - - CLK_SYS_SRAM9 - [13:13] - read-write - - - CLK_SYS_SRAM8 - [12:12] - read-write - - - CLK_SYS_SRAM7 - [11:11] - read-write - - - CLK_SYS_SRAM6 - [10:10] - read-write - - - CLK_SYS_SRAM5 - [9:9] - read-write - - - CLK_SYS_SRAM4 - [8:8] - read-write - - - CLK_SYS_SRAM3 - [7:7] - read-write - - - CLK_SYS_SRAM2 - [6:6] - read-write - - - CLK_SYS_SRAM1 - [5:5] - read-write - - - CLK_SYS_SRAM0 - [4:4] - read-write - - - CLK_SYS_SPI1 - [3:3] - read-write - - - CLK_PERI_SPI1 - [2:2] - read-write - - - CLK_SYS_SPI0 - [1:1] - read-write - - - CLK_PERI_SPI0 - [0:0] - read-write - - - - - ENABLED0 - 0x000000bc - indicates the state of the clock enable - 0x00000000 - - - CLK_SYS_SIO - [31:31] - read-only - - - CLK_SYS_SHA256 - [30:30] - read-only - - - CLK_SYS_PSM - [29:29] - read-only - - - CLK_SYS_ROSC - [28:28] - read-only - - - CLK_SYS_ROM - [27:27] - read-only - - - CLK_SYS_RESETS - [26:26] - read-only - - - CLK_SYS_PWM - [25:25] - read-only - - - CLK_SYS_POWMAN - [24:24] - read-only - - - CLK_REF_POWMAN - [23:23] - read-only - - - CLK_SYS_PLL_USB - [22:22] - read-only - - - CLK_SYS_PLL_SYS - [21:21] - read-only - - - CLK_SYS_PIO2 - [20:20] - read-only - - - CLK_SYS_PIO1 - [19:19] - read-only - - - CLK_SYS_PIO0 - [18:18] - read-only - - - CLK_SYS_PADS - [17:17] - read-only - - - CLK_SYS_OTP - [16:16] - read-only - - - CLK_REF_OTP - [15:15] - read-only - - - CLK_SYS_JTAG - [14:14] - read-only - - - CLK_SYS_IO - [13:13] - read-only - - - CLK_SYS_I2C1 - [12:12] - read-only - - - CLK_SYS_I2C0 - [11:11] - read-only - - - CLK_SYS_HSTX - [10:10] - read-only - - - CLK_HSTX - [9:9] - read-only - - - CLK_SYS_GLITCH_DETECTOR - [8:8] - read-only - - - CLK_SYS_DMA - [7:7] - read-only - - - CLK_SYS_BUSFABRIC - [6:6] - read-only - - - CLK_SYS_BUSCTRL - [5:5] - read-only - - - CLK_SYS_BOOTRAM - [4:4] - read-only - - - CLK_SYS_ADC - [3:3] - read-only - - - CLK_ADC - [2:2] - read-only - - - CLK_SYS_ACCESSCTRL - [1:1] - read-only - - - CLK_SYS_CLOCKS - [0:0] - read-only - - - - - ENABLED1 - 0x000000c0 - indicates the state of the clock enable - 0x00000000 - - - CLK_SYS_XOSC - [30:30] - read-only - - - CLK_SYS_XIP - [29:29] - read-only - - - CLK_SYS_WATCHDOG - [28:28] - read-only - - - CLK_USB - [27:27] - read-only - - - CLK_SYS_USBCTRL - [26:26] - read-only - - - CLK_SYS_UART1 - [25:25] - read-only - - - CLK_PERI_UART1 - [24:24] - read-only - - - CLK_SYS_UART0 - [23:23] - read-only - - - CLK_PERI_UART0 - [22:22] - read-only - - - CLK_SYS_TRNG - [21:21] - read-only - - - CLK_SYS_TIMER1 - [20:20] - read-only - - - CLK_SYS_TIMER0 - [19:19] - read-only - - - CLK_SYS_TICKS - [18:18] - read-only - - - CLK_REF_TICKS - [17:17] - read-only - - - CLK_SYS_TBMAN - [16:16] - read-only - - - CLK_SYS_SYSINFO - [15:15] - read-only - - - CLK_SYS_SYSCFG - [14:14] - read-only - - - CLK_SYS_SRAM9 - [13:13] - read-only - - - CLK_SYS_SRAM8 - [12:12] - read-only - - - CLK_SYS_SRAM7 - [11:11] - read-only - - - CLK_SYS_SRAM6 - [10:10] - read-only - - - CLK_SYS_SRAM5 - [9:9] - read-only - - - CLK_SYS_SRAM4 - [8:8] - read-only - - - CLK_SYS_SRAM3 - [7:7] - read-only - - - CLK_SYS_SRAM2 - [6:6] - read-only - - - CLK_SYS_SRAM1 - [5:5] - read-only - - - CLK_SYS_SRAM0 - [4:4] - read-only - - - CLK_SYS_SPI1 - [3:3] - read-only - - - CLK_PERI_SPI1 - [2:2] - read-only - - - CLK_SYS_SPI0 - [1:1] - read-only - - - CLK_PERI_SPI0 - [0:0] - read-only - - - - - INTR - 0x000000c4 - Raw Interrupts - 0x00000000 - - - CLK_SYS_RESUS - [0:0] - read-only - - - - - INTE - 0x000000c8 - Interrupt Enable - 0x00000000 - - - CLK_SYS_RESUS - [0:0] - read-write - - - - - INTF - 0x000000cc - Interrupt Force - 0x00000000 - - - CLK_SYS_RESUS - [0:0] - read-write - - - - - INTS - 0x000000d0 - Interrupt status after masking & forcing - 0x00000000 - - - CLK_SYS_RESUS - [0:0] - read-only - - - - - - - TICKS - 0x40108000 - - 0 - 72 - registers - - - - PROC0_CTRL - 0x00000000 - Controls the tick generator - 0x00000000 - - - RUNNING - Is the tick generator running? - [1:1] - read-only - - - ENABLE - start / stop tick generation - [0:0] - read-write - - - - - PROC0_CYCLES - 0x00000004 - 0x00000000 - - - PROC0_CYCLES - Total number of clk_tick cycles before the next tick. - [8:0] - read-write - - - - - PROC0_COUNT - 0x00000008 - 0x00000000 - - - PROC0_COUNT - Count down timer: the remaining number clk_tick cycles before the next tick is generated. - [8:0] - read-only - - - - - PROC1_CTRL - 0x0000000c - Controls the tick generator - 0x00000000 - - - RUNNING - Is the tick generator running? - [1:1] - read-only - - - ENABLE - start / stop tick generation - [0:0] - read-write - - - - - PROC1_CYCLES - 0x00000010 - 0x00000000 - - - PROC1_CYCLES - Total number of clk_tick cycles before the next tick. - [8:0] - read-write - - - - - PROC1_COUNT - 0x00000014 - 0x00000000 - - - PROC1_COUNT - Count down timer: the remaining number clk_tick cycles before the next tick is generated. - [8:0] - read-only - - - - - TIMER0_CTRL - 0x00000018 - Controls the tick generator - 0x00000000 - - - RUNNING - Is the tick generator running? - [1:1] - read-only - - - ENABLE - start / stop tick generation - [0:0] - read-write - - - - - TIMER0_CYCLES - 0x0000001c - 0x00000000 - - - TIMER0_CYCLES - Total number of clk_tick cycles before the next tick. - [8:0] - read-write - - - - - TIMER0_COUNT - 0x00000020 - 0x00000000 - - - TIMER0_COUNT - Count down timer: the remaining number clk_tick cycles before the next tick is generated. - [8:0] - read-only - - - - - TIMER1_CTRL - 0x00000024 - Controls the tick generator - 0x00000000 - - - RUNNING - Is the tick generator running? - [1:1] - read-only - - - ENABLE - start / stop tick generation - [0:0] - read-write - - - - - TIMER1_CYCLES - 0x00000028 - 0x00000000 - - - TIMER1_CYCLES - Total number of clk_tick cycles before the next tick. - [8:0] - read-write - - - - - TIMER1_COUNT - 0x0000002c - 0x00000000 - - - TIMER1_COUNT - Count down timer: the remaining number clk_tick cycles before the next tick is generated. - [8:0] - read-only - - - - - WATCHDOG_CTRL - 0x00000030 - Controls the tick generator - 0x00000000 - - - RUNNING - Is the tick generator running? - [1:1] - read-only - - - ENABLE - start / stop tick generation - [0:0] - read-write - - - - - WATCHDOG_CYCLES - 0x00000034 - 0x00000000 - - - WATCHDOG_CYCLES - Total number of clk_tick cycles before the next tick. - [8:0] - read-write - - - - - WATCHDOG_COUNT - 0x00000038 - 0x00000000 - - - WATCHDOG_COUNT - Count down timer: the remaining number clk_tick cycles before the next tick is generated. - [8:0] - read-only - - - - - RISCV_CTRL - 0x0000003c - Controls the tick generator - 0x00000000 - - - RUNNING - Is the tick generator running? - [1:1] - read-only - - - ENABLE - start / stop tick generation - [0:0] - read-write - - - - - RISCV_CYCLES - 0x00000040 - 0x00000000 - - - RISCV_CYCLES - Total number of clk_tick cycles before the next tick. - [8:0] - read-write - - - - - RISCV_COUNT - 0x00000044 - 0x00000000 - - - RISCV_COUNT - Count down timer: the remaining number clk_tick cycles before the next tick is generated. - [8:0] - read-only - - - - - - - PADS_BANK0 - 0x40038000 - - 0 - 204 - registers - - - - VOLTAGE_SELECT - 0x00000000 - Voltage select. Per bank control - 0x00000000 - - - VOLTAGE_SELECT - [0:0] - read-write - - - 3v3 - 0 - Set voltage to 3.3V (DVDD >= 2V5) - - - 1v8 - 1 - Set voltage to 1.8V (DVDD <= 1V8) - - - - - - - GPIO0 - 0x00000004 - 0x00000116 - - - ISO - Pad isolation control. Remove this once the pad is configured by software. - [8:8] - read-write - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - GPIO1 - 0x00000008 - 0x00000116 - - - ISO - Pad isolation control. Remove this once the pad is configured by software. - [8:8] - read-write - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - GPIO2 - 0x0000000c - 0x00000116 - - - ISO - Pad isolation control. Remove this once the pad is configured by software. - [8:8] - read-write - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - GPIO3 - 0x00000010 - 0x00000116 - - - ISO - Pad isolation control. Remove this once the pad is configured by software. - [8:8] - read-write - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - GPIO4 - 0x00000014 - 0x00000116 - - - ISO - Pad isolation control. Remove this once the pad is configured by software. - [8:8] - read-write - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - GPIO5 - 0x00000018 - 0x00000116 - - - ISO - Pad isolation control. Remove this once the pad is configured by software. - [8:8] - read-write - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - GPIO6 - 0x0000001c - 0x00000116 - - - ISO - Pad isolation control. Remove this once the pad is configured by software. - [8:8] - read-write - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - GPIO7 - 0x00000020 - 0x00000116 - - - ISO - Pad isolation control. Remove this once the pad is configured by software. - [8:8] - read-write - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - GPIO8 - 0x00000024 - 0x00000116 - - - ISO - Pad isolation control. Remove this once the pad is configured by software. - [8:8] - read-write - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - GPIO9 - 0x00000028 - 0x00000116 - - - ISO - Pad isolation control. Remove this once the pad is configured by software. - [8:8] - read-write - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - GPIO10 - 0x0000002c - 0x00000116 - - - ISO - Pad isolation control. Remove this once the pad is configured by software. - [8:8] - read-write - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - GPIO11 - 0x00000030 - 0x00000116 - - - ISO - Pad isolation control. Remove this once the pad is configured by software. - [8:8] - read-write - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - GPIO12 - 0x00000034 - 0x00000116 - - - ISO - Pad isolation control. Remove this once the pad is configured by software. - [8:8] - read-write - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - GPIO13 - 0x00000038 - 0x00000116 - - - ISO - Pad isolation control. Remove this once the pad is configured by software. - [8:8] - read-write - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - GPIO14 - 0x0000003c - 0x00000116 - - - ISO - Pad isolation control. Remove this once the pad is configured by software. - [8:8] - read-write - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - GPIO15 - 0x00000040 - 0x00000116 - - - ISO - Pad isolation control. Remove this once the pad is configured by software. - [8:8] - read-write - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - GPIO16 - 0x00000044 - 0x00000116 - - - ISO - Pad isolation control. Remove this once the pad is configured by software. - [8:8] - read-write - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - GPIO17 - 0x00000048 - 0x00000116 - - - ISO - Pad isolation control. Remove this once the pad is configured by software. - [8:8] - read-write - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - GPIO18 - 0x0000004c - 0x00000116 - - - ISO - Pad isolation control. Remove this once the pad is configured by software. - [8:8] - read-write - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - GPIO19 - 0x00000050 - 0x00000116 - - - ISO - Pad isolation control. Remove this once the pad is configured by software. - [8:8] - read-write - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - GPIO20 - 0x00000054 - 0x00000116 - - - ISO - Pad isolation control. Remove this once the pad is configured by software. - [8:8] - read-write - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - GPIO21 - 0x00000058 - 0x00000116 - - - ISO - Pad isolation control. Remove this once the pad is configured by software. - [8:8] - read-write - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - GPIO22 - 0x0000005c - 0x00000116 - - - ISO - Pad isolation control. Remove this once the pad is configured by software. - [8:8] - read-write - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - GPIO23 - 0x00000060 - 0x00000116 - - - ISO - Pad isolation control. Remove this once the pad is configured by software. - [8:8] - read-write - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - GPIO24 - 0x00000064 - 0x00000116 - - - ISO - Pad isolation control. Remove this once the pad is configured by software. - [8:8] - read-write - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - GPIO25 - 0x00000068 - 0x00000116 - - - ISO - Pad isolation control. Remove this once the pad is configured by software. - [8:8] - read-write - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - GPIO26 - 0x0000006c - 0x00000116 - - - ISO - Pad isolation control. Remove this once the pad is configured by software. - [8:8] - read-write - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - GPIO27 - 0x00000070 - 0x00000116 - - - ISO - Pad isolation control. Remove this once the pad is configured by software. - [8:8] - read-write - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - GPIO28 - 0x00000074 - 0x00000116 - - - ISO - Pad isolation control. Remove this once the pad is configured by software. - [8:8] - read-write - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - GPIO29 - 0x00000078 - 0x00000116 - - - ISO - Pad isolation control. Remove this once the pad is configured by software. - [8:8] - read-write - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - GPIO30 - 0x0000007c - 0x00000116 - - - ISO - Pad isolation control. Remove this once the pad is configured by software. - [8:8] - read-write - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - GPIO31 - 0x00000080 - 0x00000116 - - - ISO - Pad isolation control. Remove this once the pad is configured by software. - [8:8] - read-write - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - GPIO32 - 0x00000084 - 0x00000116 - - - ISO - Pad isolation control. Remove this once the pad is configured by software. - [8:8] - read-write - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - GPIO33 - 0x00000088 - 0x00000116 - - - ISO - Pad isolation control. Remove this once the pad is configured by software. - [8:8] - read-write - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - GPIO34 - 0x0000008c - 0x00000116 - - - ISO - Pad isolation control. Remove this once the pad is configured by software. - [8:8] - read-write - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - GPIO35 - 0x00000090 - 0x00000116 - - - ISO - Pad isolation control. Remove this once the pad is configured by software. - [8:8] - read-write - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - GPIO36 - 0x00000094 - 0x00000116 - - - ISO - Pad isolation control. Remove this once the pad is configured by software. - [8:8] - read-write - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - GPIO37 - 0x00000098 - 0x00000116 - - - ISO - Pad isolation control. Remove this once the pad is configured by software. - [8:8] - read-write - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - GPIO38 - 0x0000009c - 0x00000116 - - - ISO - Pad isolation control. Remove this once the pad is configured by software. - [8:8] - read-write - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - GPIO39 - 0x000000a0 - 0x00000116 - - - ISO - Pad isolation control. Remove this once the pad is configured by software. - [8:8] - read-write - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - GPIO40 - 0x000000a4 - 0x00000116 - - - ISO - Pad isolation control. Remove this once the pad is configured by software. - [8:8] - read-write - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - GPIO41 - 0x000000a8 - 0x00000116 - - - ISO - Pad isolation control. Remove this once the pad is configured by software. - [8:8] - read-write - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - GPIO42 - 0x000000ac - 0x00000116 - - - ISO - Pad isolation control. Remove this once the pad is configured by software. - [8:8] - read-write - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - GPIO43 - 0x000000b0 - 0x00000116 - - - ISO - Pad isolation control. Remove this once the pad is configured by software. - [8:8] - read-write - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - GPIO44 - 0x000000b4 - 0x00000116 - - - ISO - Pad isolation control. Remove this once the pad is configured by software. - [8:8] - read-write - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - GPIO45 - 0x000000b8 - 0x00000116 - - - ISO - Pad isolation control. Remove this once the pad is configured by software. - [8:8] - read-write - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - GPIO46 - 0x000000bc - 0x00000116 - - - ISO - Pad isolation control. Remove this once the pad is configured by software. - [8:8] - read-write - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - GPIO47 - 0x000000c0 - 0x00000116 - - - ISO - Pad isolation control. Remove this once the pad is configured by software. - [8:8] - read-write - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - SWCLK - 0x000000c4 - 0x0000005a - - - ISO - Pad isolation control. Remove this once the pad is configured by software. - [8:8] - read-write - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - SWD - 0x000000c8 - 0x0000005a - - - ISO - Pad isolation control. Remove this once the pad is configured by software. - [8:8] - read-write - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - - - PADS_QSPI - 0x40040000 - - 0 - 28 - registers - - - - VOLTAGE_SELECT - 0x00000000 - Voltage select. Per bank control - 0x00000000 - - - VOLTAGE_SELECT - [0:0] - read-write - - - 3v3 - 0 - Set voltage to 3.3V (DVDD >= 2V5) - - - 1v8 - 1 - Set voltage to 1.8V (DVDD <= 1V8) - - - - - - - GPIO_QSPI_SCLK - 0x00000004 - 0x00000156 - - - ISO - Pad isolation control. Remove this once the pad is configured by software. - [8:8] - read-write - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - GPIO_QSPI_SD0 - 0x00000008 - 0x00000156 - - - ISO - Pad isolation control. Remove this once the pad is configured by software. - [8:8] - read-write - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - GPIO_QSPI_SD1 - 0x0000000c - 0x00000156 - - - ISO - Pad isolation control. Remove this once the pad is configured by software. - [8:8] - read-write - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - GPIO_QSPI_SD2 - 0x00000010 - 0x0000015a - - - ISO - Pad isolation control. Remove this once the pad is configured by software. - [8:8] - read-write - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - GPIO_QSPI_SD3 - 0x00000014 - 0x0000015a - - - ISO - Pad isolation control. Remove this once the pad is configured by software. - [8:8] - read-write - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - GPIO_QSPI_SS - 0x00000018 - 0x0000015a - - - ISO - Pad isolation control. Remove this once the pad is configured by software. - [8:8] - read-write - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - - - IO_QSPI - 0x40030000 - - 0 - 576 - registers - - - IO_IRQ_QSPI - 23 - - - IO_IRQ_QSPI_NS - 24 - - - - USBPHY_DP_STATUS - 0x00000000 - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - INFROMPAD - input signal from pad, before filtering and override are applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - - - USBPHY_DP_CTRL - 0x00000004 - 0x0000001f - - - IRQOVER - [29:28] - read-write - - - NORMAL - 0 - don't invert the interrupt - - - INVERT - 1 - invert the interrupt - - - LOW - 2 - drive interrupt low - - - HIGH - 3 - drive interrupt high - - - - - INOVER - [17:16] - read-write - - - NORMAL - 0 - don't invert the peri input - - - INVERT - 1 - invert the peri input - - - LOW - 2 - drive peri input low - - - HIGH - 3 - drive peri input high - - - - - OEOVER - [15:14] - read-write - - - NORMAL - 0 - drive output enable from peripheral signal selected by funcsel - - - INVERT - 1 - drive output enable from inverse of peripheral signal selected by funcsel - - - DISABLE - 2 - disable output - - - ENABLE - 3 - enable output - - - - - OUTOVER - [13:12] - read-write - - - NORMAL - 0 - drive output from peripheral signal selected by funcsel - - - INVERT - 1 - drive output from inverse of peripheral signal selected by funcsel - - - LOW - 2 - drive output low - - - HIGH - 3 - drive output high - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table - 31 == NULL - [4:0] - read-write - - - uart1_tx - 2 - - - i2c0_sda - 3 - - - siob_proc_56 - 5 - - - null - 31 - - - - - - - USBPHY_DM_STATUS - 0x00000008 - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - INFROMPAD - input signal from pad, before filtering and override are applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - - - USBPHY_DM_CTRL - 0x0000000c - 0x0000001f - - - IRQOVER - [29:28] - read-write - - - NORMAL - 0 - don't invert the interrupt - - - INVERT - 1 - invert the interrupt - - - LOW - 2 - drive interrupt low - - - HIGH - 3 - drive interrupt high - - - - - INOVER - [17:16] - read-write - - - NORMAL - 0 - don't invert the peri input - - - INVERT - 1 - invert the peri input - - - LOW - 2 - drive peri input low - - - HIGH - 3 - drive peri input high - - - - - OEOVER - [15:14] - read-write - - - NORMAL - 0 - drive output enable from peripheral signal selected by funcsel - - - INVERT - 1 - drive output enable from inverse of peripheral signal selected by funcsel - - - DISABLE - 2 - disable output - - - ENABLE - 3 - enable output - - - - - OUTOVER - [13:12] - read-write - - - NORMAL - 0 - drive output from peripheral signal selected by funcsel - - - INVERT - 1 - drive output from inverse of peripheral signal selected by funcsel - - - LOW - 2 - drive output low - - - HIGH - 3 - drive output high - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table - 31 == NULL - [4:0] - read-write - - - uart1_rx - 2 - - - i2c0_scl - 3 - - - siob_proc_57 - 5 - - - null - 31 - - - - - - - GPIO_QSPI_SCLK_STATUS - 0x00000010 - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - INFROMPAD - input signal from pad, before filtering and override are applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - - - GPIO_QSPI_SCLK_CTRL - 0x00000014 - 0x0000001f - - - IRQOVER - [29:28] - read-write - - - NORMAL - 0 - don't invert the interrupt - - - INVERT - 1 - invert the interrupt - - - LOW - 2 - drive interrupt low - - - HIGH - 3 - drive interrupt high - - - - - INOVER - [17:16] - read-write - - - NORMAL - 0 - don't invert the peri input - - - INVERT - 1 - invert the peri input - - - LOW - 2 - drive peri input low - - - HIGH - 3 - drive peri input high - - - - - OEOVER - [15:14] - read-write - - - NORMAL - 0 - drive output enable from peripheral signal selected by funcsel - - - INVERT - 1 - drive output enable from inverse of peripheral signal selected by funcsel - - - DISABLE - 2 - disable output - - - ENABLE - 3 - enable output - - - - - OUTOVER - [13:12] - read-write - - - NORMAL - 0 - drive output from peripheral signal selected by funcsel - - - INVERT - 1 - drive output from inverse of peripheral signal selected by funcsel - - - LOW - 2 - drive output low - - - HIGH - 3 - drive output high - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table - 31 == NULL - [4:0] - read-write - - - xip_sclk - 0 - - - uart1_cts - 2 - - - i2c1_sda - 3 - - - siob_proc_58 - 5 - - - uart1_tx - 11 - - - null - 31 - - - - - - - GPIO_QSPI_SS_STATUS - 0x00000018 - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - INFROMPAD - input signal from pad, before filtering and override are applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - - - GPIO_QSPI_SS_CTRL - 0x0000001c - 0x0000001f - - - IRQOVER - [29:28] - read-write - - - NORMAL - 0 - don't invert the interrupt - - - INVERT - 1 - invert the interrupt - - - LOW - 2 - drive interrupt low - - - HIGH - 3 - drive interrupt high - - - - - INOVER - [17:16] - read-write - - - NORMAL - 0 - don't invert the peri input - - - INVERT - 1 - invert the peri input - - - LOW - 2 - drive peri input low - - - HIGH - 3 - drive peri input high - - - - - OEOVER - [15:14] - read-write - - - NORMAL - 0 - drive output enable from peripheral signal selected by funcsel - - - INVERT - 1 - drive output enable from inverse of peripheral signal selected by funcsel - - - DISABLE - 2 - disable output - - - ENABLE - 3 - enable output - - - - - OUTOVER - [13:12] - read-write - - - NORMAL - 0 - drive output from peripheral signal selected by funcsel - - - INVERT - 1 - drive output from inverse of peripheral signal selected by funcsel - - - LOW - 2 - drive output low - - - HIGH - 3 - drive output high - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table - 31 == NULL - [4:0] - read-write - - - xip_ss_n_0 - 0 - - - uart1_rts - 2 - - - i2c1_scl - 3 - - - siob_proc_59 - 5 - - - uart1_rx - 11 - - - null - 31 - - - - - - - GPIO_QSPI_SD0_STATUS - 0x00000020 - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - INFROMPAD - input signal from pad, before filtering and override are applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - - - GPIO_QSPI_SD0_CTRL - 0x00000024 - 0x0000001f - - - IRQOVER - [29:28] - read-write - - - NORMAL - 0 - don't invert the interrupt - - - INVERT - 1 - invert the interrupt - - - LOW - 2 - drive interrupt low - - - HIGH - 3 - drive interrupt high - - - - - INOVER - [17:16] - read-write - - - NORMAL - 0 - don't invert the peri input - - - INVERT - 1 - invert the peri input - - - LOW - 2 - drive peri input low - - - HIGH - 3 - drive peri input high - - - - - OEOVER - [15:14] - read-write - - - NORMAL - 0 - drive output enable from peripheral signal selected by funcsel - - - INVERT - 1 - drive output enable from inverse of peripheral signal selected by funcsel - - - DISABLE - 2 - disable output - - - ENABLE - 3 - enable output - - - - - OUTOVER - [13:12] - read-write - - - NORMAL - 0 - drive output from peripheral signal selected by funcsel - - - INVERT - 1 - drive output from inverse of peripheral signal selected by funcsel - - - LOW - 2 - drive output low - - - HIGH - 3 - drive output high - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table - 31 == NULL - [4:0] - read-write - - - xip_sd0 - 0 - - - uart0_tx - 2 - - - i2c0_sda - 3 - - - siob_proc_60 - 5 - - - null - 31 - - - - - - - GPIO_QSPI_SD1_STATUS - 0x00000028 - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - INFROMPAD - input signal from pad, before filtering and override are applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - - - GPIO_QSPI_SD1_CTRL - 0x0000002c - 0x0000001f - - - IRQOVER - [29:28] - read-write - - - NORMAL - 0 - don't invert the interrupt - - - INVERT - 1 - invert the interrupt - - - LOW - 2 - drive interrupt low - - - HIGH - 3 - drive interrupt high - - - - - INOVER - [17:16] - read-write - - - NORMAL - 0 - don't invert the peri input - - - INVERT - 1 - invert the peri input - - - LOW - 2 - drive peri input low - - - HIGH - 3 - drive peri input high - - - - - OEOVER - [15:14] - read-write - - - NORMAL - 0 - drive output enable from peripheral signal selected by funcsel - - - INVERT - 1 - drive output enable from inverse of peripheral signal selected by funcsel - - - DISABLE - 2 - disable output - - - ENABLE - 3 - enable output - - - - - OUTOVER - [13:12] - read-write - - - NORMAL - 0 - drive output from peripheral signal selected by funcsel - - - INVERT - 1 - drive output from inverse of peripheral signal selected by funcsel - - - LOW - 2 - drive output low - - - HIGH - 3 - drive output high - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table - 31 == NULL - [4:0] - read-write - - - xip_sd1 - 0 - - - uart0_rx - 2 - - - i2c0_scl - 3 - - - siob_proc_61 - 5 - - - null - 31 - - - - - - - GPIO_QSPI_SD2_STATUS - 0x00000030 - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - INFROMPAD - input signal from pad, before filtering and override are applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - - - GPIO_QSPI_SD2_CTRL - 0x00000034 - 0x0000001f - - - IRQOVER - [29:28] - read-write - - - NORMAL - 0 - don't invert the interrupt - - - INVERT - 1 - invert the interrupt - - - LOW - 2 - drive interrupt low - - - HIGH - 3 - drive interrupt high - - - - - INOVER - [17:16] - read-write - - - NORMAL - 0 - don't invert the peri input - - - INVERT - 1 - invert the peri input - - - LOW - 2 - drive peri input low - - - HIGH - 3 - drive peri input high - - - - - OEOVER - [15:14] - read-write - - - NORMAL - 0 - drive output enable from peripheral signal selected by funcsel - - - INVERT - 1 - drive output enable from inverse of peripheral signal selected by funcsel - - - DISABLE - 2 - disable output - - - ENABLE - 3 - enable output - - - - - OUTOVER - [13:12] - read-write - - - NORMAL - 0 - drive output from peripheral signal selected by funcsel - - - INVERT - 1 - drive output from inverse of peripheral signal selected by funcsel - - - LOW - 2 - drive output low - - - HIGH - 3 - drive output high - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table - 31 == NULL - [4:0] - read-write - - - xip_sd2 - 0 - - - uart0_cts - 2 - - - i2c1_sda - 3 - - - siob_proc_62 - 5 - - - uart0_tx - 11 - - - null - 31 - - - - - - - GPIO_QSPI_SD3_STATUS - 0x00000038 - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - INFROMPAD - input signal from pad, before filtering and override are applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - - - GPIO_QSPI_SD3_CTRL - 0x0000003c - 0x0000001f - - - IRQOVER - [29:28] - read-write - - - NORMAL - 0 - don't invert the interrupt - - - INVERT - 1 - invert the interrupt - - - LOW - 2 - drive interrupt low - - - HIGH - 3 - drive interrupt high - - - - - INOVER - [17:16] - read-write - - - NORMAL - 0 - don't invert the peri input - - - INVERT - 1 - invert the peri input - - - LOW - 2 - drive peri input low - - - HIGH - 3 - drive peri input high - - - - - OEOVER - [15:14] - read-write - - - NORMAL - 0 - drive output enable from peripheral signal selected by funcsel - - - INVERT - 1 - drive output enable from inverse of peripheral signal selected by funcsel - - - DISABLE - 2 - disable output - - - ENABLE - 3 - enable output - - - - - OUTOVER - [13:12] - read-write - - - NORMAL - 0 - drive output from peripheral signal selected by funcsel - - - INVERT - 1 - drive output from inverse of peripheral signal selected by funcsel - - - LOW - 2 - drive output low - - - HIGH - 3 - drive output high - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table - 31 == NULL - [4:0] - read-write - - - xip_sd3 - 0 - - - uart0_rts - 2 - - - i2c1_scl - 3 - - - siob_proc_63 - 5 - - - uart0_rx - 11 - - - null - 31 - - - - - - - IRQSUMMARY_PROC0_SECURE - 0x00000200 - 0x00000000 - - - GPIO_QSPI_SD3 - [7:7] - read-only - - - GPIO_QSPI_SD2 - [6:6] - read-only - - - GPIO_QSPI_SD1 - [5:5] - read-only - - - GPIO_QSPI_SD0 - [4:4] - read-only - - - GPIO_QSPI_SS - [3:3] - read-only - - - GPIO_QSPI_SCLK - [2:2] - read-only - - - USBPHY_DM - [1:1] - read-only - - - USBPHY_DP - [0:0] - read-only - - - - - IRQSUMMARY_PROC0_NONSECURE - 0x00000204 - 0x00000000 - - - GPIO_QSPI_SD3 - [7:7] - read-only - - - GPIO_QSPI_SD2 - [6:6] - read-only - - - GPIO_QSPI_SD1 - [5:5] - read-only - - - GPIO_QSPI_SD0 - [4:4] - read-only - - - GPIO_QSPI_SS - [3:3] - read-only - - - GPIO_QSPI_SCLK - [2:2] - read-only - - - USBPHY_DM - [1:1] - read-only - - - USBPHY_DP - [0:0] - read-only - - - - - IRQSUMMARY_PROC1_SECURE - 0x00000208 - 0x00000000 - - - GPIO_QSPI_SD3 - [7:7] - read-only - - - GPIO_QSPI_SD2 - [6:6] - read-only - - - GPIO_QSPI_SD1 - [5:5] - read-only - - - GPIO_QSPI_SD0 - [4:4] - read-only - - - GPIO_QSPI_SS - [3:3] - read-only - - - GPIO_QSPI_SCLK - [2:2] - read-only - - - USBPHY_DM - [1:1] - read-only - - - USBPHY_DP - [0:0] - read-only - - - - - IRQSUMMARY_PROC1_NONSECURE - 0x0000020c - 0x00000000 - - - GPIO_QSPI_SD3 - [7:7] - read-only - - - GPIO_QSPI_SD2 - [6:6] - read-only - - - GPIO_QSPI_SD1 - [5:5] - read-only - - - GPIO_QSPI_SD0 - [4:4] - read-only - - - GPIO_QSPI_SS - [3:3] - read-only - - - GPIO_QSPI_SCLK - [2:2] - read-only - - - USBPHY_DM - [1:1] - read-only - - - USBPHY_DP - [0:0] - read-only - - - - - IRQSUMMARY_DORMANT_WAKE_SECURE - 0x00000210 - 0x00000000 - - - GPIO_QSPI_SD3 - [7:7] - read-only - - - GPIO_QSPI_SD2 - [6:6] - read-only - - - GPIO_QSPI_SD1 - [5:5] - read-only - - - GPIO_QSPI_SD0 - [4:4] - read-only - - - GPIO_QSPI_SS - [3:3] - read-only - - - GPIO_QSPI_SCLK - [2:2] - read-only - - - USBPHY_DM - [1:1] - read-only - - - USBPHY_DP - [0:0] - read-only - - - - - IRQSUMMARY_DORMANT_WAKE_NONSECURE - 0x00000214 - 0x00000000 - - - GPIO_QSPI_SD3 - [7:7] - read-only - - - GPIO_QSPI_SD2 - [6:6] - read-only - - - GPIO_QSPI_SD1 - [5:5] - read-only - - - GPIO_QSPI_SD0 - [4:4] - read-only - - - GPIO_QSPI_SS - [3:3] - read-only - - - GPIO_QSPI_SCLK - [2:2] - read-only - - - USBPHY_DM - [1:1] - read-only - - - USBPHY_DP - [0:0] - read-only - - - - - INTR - 0x00000218 - Raw Interrupts - 0x00000000 - - - GPIO_QSPI_SD3_EDGE_HIGH - [31:31] - read-write - oneToClear - - - GPIO_QSPI_SD3_EDGE_LOW - [30:30] - read-write - oneToClear - - - GPIO_QSPI_SD3_LEVEL_HIGH - [29:29] - read-only - - - GPIO_QSPI_SD3_LEVEL_LOW - [28:28] - read-only - - - GPIO_QSPI_SD2_EDGE_HIGH - [27:27] - read-write - oneToClear - - - GPIO_QSPI_SD2_EDGE_LOW - [26:26] - read-write - oneToClear - - - GPIO_QSPI_SD2_LEVEL_HIGH - [25:25] - read-only - - - GPIO_QSPI_SD2_LEVEL_LOW - [24:24] - read-only - - - GPIO_QSPI_SD1_EDGE_HIGH - [23:23] - read-write - oneToClear - - - GPIO_QSPI_SD1_EDGE_LOW - [22:22] - read-write - oneToClear - - - GPIO_QSPI_SD1_LEVEL_HIGH - [21:21] - read-only - - - GPIO_QSPI_SD1_LEVEL_LOW - [20:20] - read-only - - - GPIO_QSPI_SD0_EDGE_HIGH - [19:19] - read-write - oneToClear - - - GPIO_QSPI_SD0_EDGE_LOW - [18:18] - read-write - oneToClear - - - GPIO_QSPI_SD0_LEVEL_HIGH - [17:17] - read-only - - - GPIO_QSPI_SD0_LEVEL_LOW - [16:16] - read-only - - - GPIO_QSPI_SS_EDGE_HIGH - [15:15] - read-write - oneToClear - - - GPIO_QSPI_SS_EDGE_LOW - [14:14] - read-write - oneToClear - - - GPIO_QSPI_SS_LEVEL_HIGH - [13:13] - read-only - - - GPIO_QSPI_SS_LEVEL_LOW - [12:12] - read-only - - - GPIO_QSPI_SCLK_EDGE_HIGH - [11:11] - read-write - oneToClear - - - GPIO_QSPI_SCLK_EDGE_LOW - [10:10] - read-write - oneToClear - - - GPIO_QSPI_SCLK_LEVEL_HIGH - [9:9] - read-only - - - GPIO_QSPI_SCLK_LEVEL_LOW - [8:8] - read-only - - - USBPHY_DM_EDGE_HIGH - [7:7] - read-write - oneToClear - - - USBPHY_DM_EDGE_LOW - [6:6] - read-write - oneToClear - - - USBPHY_DM_LEVEL_HIGH - [5:5] - read-only - - - USBPHY_DM_LEVEL_LOW - [4:4] - read-only - - - USBPHY_DP_EDGE_HIGH - [3:3] - read-write - oneToClear - - - USBPHY_DP_EDGE_LOW - [2:2] - read-write - oneToClear - - - USBPHY_DP_LEVEL_HIGH - [1:1] - read-only - - - USBPHY_DP_LEVEL_LOW - [0:0] - read-only - - - - - PROC0_INTE - 0x0000021c - Interrupt Enable for proc0 - 0x00000000 - - - GPIO_QSPI_SD3_EDGE_HIGH - [31:31] - read-write - - - GPIO_QSPI_SD3_EDGE_LOW - [30:30] - read-write - - - GPIO_QSPI_SD3_LEVEL_HIGH - [29:29] - read-write - - - GPIO_QSPI_SD3_LEVEL_LOW - [28:28] - read-write - - - GPIO_QSPI_SD2_EDGE_HIGH - [27:27] - read-write - - - GPIO_QSPI_SD2_EDGE_LOW - [26:26] - read-write - - - GPIO_QSPI_SD2_LEVEL_HIGH - [25:25] - read-write - - - GPIO_QSPI_SD2_LEVEL_LOW - [24:24] - read-write - - - GPIO_QSPI_SD1_EDGE_HIGH - [23:23] - read-write - - - GPIO_QSPI_SD1_EDGE_LOW - [22:22] - read-write - - - GPIO_QSPI_SD1_LEVEL_HIGH - [21:21] - read-write - - - GPIO_QSPI_SD1_LEVEL_LOW - [20:20] - read-write - - - GPIO_QSPI_SD0_EDGE_HIGH - [19:19] - read-write - - - GPIO_QSPI_SD0_EDGE_LOW - [18:18] - read-write - - - GPIO_QSPI_SD0_LEVEL_HIGH - [17:17] - read-write - - - GPIO_QSPI_SD0_LEVEL_LOW - [16:16] - read-write - - - GPIO_QSPI_SS_EDGE_HIGH - [15:15] - read-write - - - GPIO_QSPI_SS_EDGE_LOW - [14:14] - read-write - - - GPIO_QSPI_SS_LEVEL_HIGH - [13:13] - read-write - - - GPIO_QSPI_SS_LEVEL_LOW - [12:12] - read-write - - - GPIO_QSPI_SCLK_EDGE_HIGH - [11:11] - read-write - - - GPIO_QSPI_SCLK_EDGE_LOW - [10:10] - read-write - - - GPIO_QSPI_SCLK_LEVEL_HIGH - [9:9] - read-write - - - GPIO_QSPI_SCLK_LEVEL_LOW - [8:8] - read-write - - - USBPHY_DM_EDGE_HIGH - [7:7] - read-write - - - USBPHY_DM_EDGE_LOW - [6:6] - read-write - - - USBPHY_DM_LEVEL_HIGH - [5:5] - read-write - - - USBPHY_DM_LEVEL_LOW - [4:4] - read-write - - - USBPHY_DP_EDGE_HIGH - [3:3] - read-write - - - USBPHY_DP_EDGE_LOW - [2:2] - read-write - - - USBPHY_DP_LEVEL_HIGH - [1:1] - read-write - - - USBPHY_DP_LEVEL_LOW - [0:0] - read-write - - - - - PROC0_INTF - 0x00000220 - Interrupt Force for proc0 - 0x00000000 - - - GPIO_QSPI_SD3_EDGE_HIGH - [31:31] - read-write - - - GPIO_QSPI_SD3_EDGE_LOW - [30:30] - read-write - - - GPIO_QSPI_SD3_LEVEL_HIGH - [29:29] - read-write - - - GPIO_QSPI_SD3_LEVEL_LOW - [28:28] - read-write - - - GPIO_QSPI_SD2_EDGE_HIGH - [27:27] - read-write - - - GPIO_QSPI_SD2_EDGE_LOW - [26:26] - read-write - - - GPIO_QSPI_SD2_LEVEL_HIGH - [25:25] - read-write - - - GPIO_QSPI_SD2_LEVEL_LOW - [24:24] - read-write - - - GPIO_QSPI_SD1_EDGE_HIGH - [23:23] - read-write - - - GPIO_QSPI_SD1_EDGE_LOW - [22:22] - read-write - - - GPIO_QSPI_SD1_LEVEL_HIGH - [21:21] - read-write - - - GPIO_QSPI_SD1_LEVEL_LOW - [20:20] - read-write - - - GPIO_QSPI_SD0_EDGE_HIGH - [19:19] - read-write - - - GPIO_QSPI_SD0_EDGE_LOW - [18:18] - read-write - - - GPIO_QSPI_SD0_LEVEL_HIGH - [17:17] - read-write - - - GPIO_QSPI_SD0_LEVEL_LOW - [16:16] - read-write - - - GPIO_QSPI_SS_EDGE_HIGH - [15:15] - read-write - - - GPIO_QSPI_SS_EDGE_LOW - [14:14] - read-write - - - GPIO_QSPI_SS_LEVEL_HIGH - [13:13] - read-write - - - GPIO_QSPI_SS_LEVEL_LOW - [12:12] - read-write - - - GPIO_QSPI_SCLK_EDGE_HIGH - [11:11] - read-write - - - GPIO_QSPI_SCLK_EDGE_LOW - [10:10] - read-write - - - GPIO_QSPI_SCLK_LEVEL_HIGH - [9:9] - read-write - - - GPIO_QSPI_SCLK_LEVEL_LOW - [8:8] - read-write - - - USBPHY_DM_EDGE_HIGH - [7:7] - read-write - - - USBPHY_DM_EDGE_LOW - [6:6] - read-write - - - USBPHY_DM_LEVEL_HIGH - [5:5] - read-write - - - USBPHY_DM_LEVEL_LOW - [4:4] - read-write - - - USBPHY_DP_EDGE_HIGH - [3:3] - read-write - - - USBPHY_DP_EDGE_LOW - [2:2] - read-write - - - USBPHY_DP_LEVEL_HIGH - [1:1] - read-write - - - USBPHY_DP_LEVEL_LOW - [0:0] - read-write - - - - - PROC0_INTS - 0x00000224 - Interrupt status after masking & forcing for proc0 - 0x00000000 - - - GPIO_QSPI_SD3_EDGE_HIGH - [31:31] - read-only - - - GPIO_QSPI_SD3_EDGE_LOW - [30:30] - read-only - - - GPIO_QSPI_SD3_LEVEL_HIGH - [29:29] - read-only - - - GPIO_QSPI_SD3_LEVEL_LOW - [28:28] - read-only - - - GPIO_QSPI_SD2_EDGE_HIGH - [27:27] - read-only - - - GPIO_QSPI_SD2_EDGE_LOW - [26:26] - read-only - - - GPIO_QSPI_SD2_LEVEL_HIGH - [25:25] - read-only - - - GPIO_QSPI_SD2_LEVEL_LOW - [24:24] - read-only - - - GPIO_QSPI_SD1_EDGE_HIGH - [23:23] - read-only - - - GPIO_QSPI_SD1_EDGE_LOW - [22:22] - read-only - - - GPIO_QSPI_SD1_LEVEL_HIGH - [21:21] - read-only - - - GPIO_QSPI_SD1_LEVEL_LOW - [20:20] - read-only - - - GPIO_QSPI_SD0_EDGE_HIGH - [19:19] - read-only - - - GPIO_QSPI_SD0_EDGE_LOW - [18:18] - read-only - - - GPIO_QSPI_SD0_LEVEL_HIGH - [17:17] - read-only - - - GPIO_QSPI_SD0_LEVEL_LOW - [16:16] - read-only - - - GPIO_QSPI_SS_EDGE_HIGH - [15:15] - read-only - - - GPIO_QSPI_SS_EDGE_LOW - [14:14] - read-only - - - GPIO_QSPI_SS_LEVEL_HIGH - [13:13] - read-only - - - GPIO_QSPI_SS_LEVEL_LOW - [12:12] - read-only - - - GPIO_QSPI_SCLK_EDGE_HIGH - [11:11] - read-only - - - GPIO_QSPI_SCLK_EDGE_LOW - [10:10] - read-only - - - GPIO_QSPI_SCLK_LEVEL_HIGH - [9:9] - read-only - - - GPIO_QSPI_SCLK_LEVEL_LOW - [8:8] - read-only - - - USBPHY_DM_EDGE_HIGH - [7:7] - read-only - - - USBPHY_DM_EDGE_LOW - [6:6] - read-only - - - USBPHY_DM_LEVEL_HIGH - [5:5] - read-only - - - USBPHY_DM_LEVEL_LOW - [4:4] - read-only - - - USBPHY_DP_EDGE_HIGH - [3:3] - read-only - - - USBPHY_DP_EDGE_LOW - [2:2] - read-only - - - USBPHY_DP_LEVEL_HIGH - [1:1] - read-only - - - USBPHY_DP_LEVEL_LOW - [0:0] - read-only - - - - - PROC1_INTE - 0x00000228 - Interrupt Enable for proc1 - 0x00000000 - - - GPIO_QSPI_SD3_EDGE_HIGH - [31:31] - read-write - - - GPIO_QSPI_SD3_EDGE_LOW - [30:30] - read-write - - - GPIO_QSPI_SD3_LEVEL_HIGH - [29:29] - read-write - - - GPIO_QSPI_SD3_LEVEL_LOW - [28:28] - read-write - - - GPIO_QSPI_SD2_EDGE_HIGH - [27:27] - read-write - - - GPIO_QSPI_SD2_EDGE_LOW - [26:26] - read-write - - - GPIO_QSPI_SD2_LEVEL_HIGH - [25:25] - read-write - - - GPIO_QSPI_SD2_LEVEL_LOW - [24:24] - read-write - - - GPIO_QSPI_SD1_EDGE_HIGH - [23:23] - read-write - - - GPIO_QSPI_SD1_EDGE_LOW - [22:22] - read-write - - - GPIO_QSPI_SD1_LEVEL_HIGH - [21:21] - read-write - - - GPIO_QSPI_SD1_LEVEL_LOW - [20:20] - read-write - - - GPIO_QSPI_SD0_EDGE_HIGH - [19:19] - read-write - - - GPIO_QSPI_SD0_EDGE_LOW - [18:18] - read-write - - - GPIO_QSPI_SD0_LEVEL_HIGH - [17:17] - read-write - - - GPIO_QSPI_SD0_LEVEL_LOW - [16:16] - read-write - - - GPIO_QSPI_SS_EDGE_HIGH - [15:15] - read-write - - - GPIO_QSPI_SS_EDGE_LOW - [14:14] - read-write - - - GPIO_QSPI_SS_LEVEL_HIGH - [13:13] - read-write - - - GPIO_QSPI_SS_LEVEL_LOW - [12:12] - read-write - - - GPIO_QSPI_SCLK_EDGE_HIGH - [11:11] - read-write - - - GPIO_QSPI_SCLK_EDGE_LOW - [10:10] - read-write - - - GPIO_QSPI_SCLK_LEVEL_HIGH - [9:9] - read-write - - - GPIO_QSPI_SCLK_LEVEL_LOW - [8:8] - read-write - - - USBPHY_DM_EDGE_HIGH - [7:7] - read-write - - - USBPHY_DM_EDGE_LOW - [6:6] - read-write - - - USBPHY_DM_LEVEL_HIGH - [5:5] - read-write - - - USBPHY_DM_LEVEL_LOW - [4:4] - read-write - - - USBPHY_DP_EDGE_HIGH - [3:3] - read-write - - - USBPHY_DP_EDGE_LOW - [2:2] - read-write - - - USBPHY_DP_LEVEL_HIGH - [1:1] - read-write - - - USBPHY_DP_LEVEL_LOW - [0:0] - read-write - - - - - PROC1_INTF - 0x0000022c - Interrupt Force for proc1 - 0x00000000 - - - GPIO_QSPI_SD3_EDGE_HIGH - [31:31] - read-write - - - GPIO_QSPI_SD3_EDGE_LOW - [30:30] - read-write - - - GPIO_QSPI_SD3_LEVEL_HIGH - [29:29] - read-write - - - GPIO_QSPI_SD3_LEVEL_LOW - [28:28] - read-write - - - GPIO_QSPI_SD2_EDGE_HIGH - [27:27] - read-write - - - GPIO_QSPI_SD2_EDGE_LOW - [26:26] - read-write - - - GPIO_QSPI_SD2_LEVEL_HIGH - [25:25] - read-write - - - GPIO_QSPI_SD2_LEVEL_LOW - [24:24] - read-write - - - GPIO_QSPI_SD1_EDGE_HIGH - [23:23] - read-write - - - GPIO_QSPI_SD1_EDGE_LOW - [22:22] - read-write - - - GPIO_QSPI_SD1_LEVEL_HIGH - [21:21] - read-write - - - GPIO_QSPI_SD1_LEVEL_LOW - [20:20] - read-write - - - GPIO_QSPI_SD0_EDGE_HIGH - [19:19] - read-write - - - GPIO_QSPI_SD0_EDGE_LOW - [18:18] - read-write - - - GPIO_QSPI_SD0_LEVEL_HIGH - [17:17] - read-write - - - GPIO_QSPI_SD0_LEVEL_LOW - [16:16] - read-write - - - GPIO_QSPI_SS_EDGE_HIGH - [15:15] - read-write - - - GPIO_QSPI_SS_EDGE_LOW - [14:14] - read-write - - - GPIO_QSPI_SS_LEVEL_HIGH - [13:13] - read-write - - - GPIO_QSPI_SS_LEVEL_LOW - [12:12] - read-write - - - GPIO_QSPI_SCLK_EDGE_HIGH - [11:11] - read-write - - - GPIO_QSPI_SCLK_EDGE_LOW - [10:10] - read-write - - - GPIO_QSPI_SCLK_LEVEL_HIGH - [9:9] - read-write - - - GPIO_QSPI_SCLK_LEVEL_LOW - [8:8] - read-write - - - USBPHY_DM_EDGE_HIGH - [7:7] - read-write - - - USBPHY_DM_EDGE_LOW - [6:6] - read-write - - - USBPHY_DM_LEVEL_HIGH - [5:5] - read-write - - - USBPHY_DM_LEVEL_LOW - [4:4] - read-write - - - USBPHY_DP_EDGE_HIGH - [3:3] - read-write - - - USBPHY_DP_EDGE_LOW - [2:2] - read-write - - - USBPHY_DP_LEVEL_HIGH - [1:1] - read-write - - - USBPHY_DP_LEVEL_LOW - [0:0] - read-write - - - - - PROC1_INTS - 0x00000230 - Interrupt status after masking & forcing for proc1 - 0x00000000 - - - GPIO_QSPI_SD3_EDGE_HIGH - [31:31] - read-only - - - GPIO_QSPI_SD3_EDGE_LOW - [30:30] - read-only - - - GPIO_QSPI_SD3_LEVEL_HIGH - [29:29] - read-only - - - GPIO_QSPI_SD3_LEVEL_LOW - [28:28] - read-only - - - GPIO_QSPI_SD2_EDGE_HIGH - [27:27] - read-only - - - GPIO_QSPI_SD2_EDGE_LOW - [26:26] - read-only - - - GPIO_QSPI_SD2_LEVEL_HIGH - [25:25] - read-only - - - GPIO_QSPI_SD2_LEVEL_LOW - [24:24] - read-only - - - GPIO_QSPI_SD1_EDGE_HIGH - [23:23] - read-only - - - GPIO_QSPI_SD1_EDGE_LOW - [22:22] - read-only - - - GPIO_QSPI_SD1_LEVEL_HIGH - [21:21] - read-only - - - GPIO_QSPI_SD1_LEVEL_LOW - [20:20] - read-only - - - GPIO_QSPI_SD0_EDGE_HIGH - [19:19] - read-only - - - GPIO_QSPI_SD0_EDGE_LOW - [18:18] - read-only - - - GPIO_QSPI_SD0_LEVEL_HIGH - [17:17] - read-only - - - GPIO_QSPI_SD0_LEVEL_LOW - [16:16] - read-only - - - GPIO_QSPI_SS_EDGE_HIGH - [15:15] - read-only - - - GPIO_QSPI_SS_EDGE_LOW - [14:14] - read-only - - - GPIO_QSPI_SS_LEVEL_HIGH - [13:13] - read-only - - - GPIO_QSPI_SS_LEVEL_LOW - [12:12] - read-only - - - GPIO_QSPI_SCLK_EDGE_HIGH - [11:11] - read-only - - - GPIO_QSPI_SCLK_EDGE_LOW - [10:10] - read-only - - - GPIO_QSPI_SCLK_LEVEL_HIGH - [9:9] - read-only - - - GPIO_QSPI_SCLK_LEVEL_LOW - [8:8] - read-only - - - USBPHY_DM_EDGE_HIGH - [7:7] - read-only - - - USBPHY_DM_EDGE_LOW - [6:6] - read-only - - - USBPHY_DM_LEVEL_HIGH - [5:5] - read-only - - - USBPHY_DM_LEVEL_LOW - [4:4] - read-only - - - USBPHY_DP_EDGE_HIGH - [3:3] - read-only - - - USBPHY_DP_EDGE_LOW - [2:2] - read-only - - - USBPHY_DP_LEVEL_HIGH - [1:1] - read-only - - - USBPHY_DP_LEVEL_LOW - [0:0] - read-only - - - - - DORMANT_WAKE_INTE - 0x00000234 - Interrupt Enable for dormant_wake - 0x00000000 - - - GPIO_QSPI_SD3_EDGE_HIGH - [31:31] - read-write - - - GPIO_QSPI_SD3_EDGE_LOW - [30:30] - read-write - - - GPIO_QSPI_SD3_LEVEL_HIGH - [29:29] - read-write - - - GPIO_QSPI_SD3_LEVEL_LOW - [28:28] - read-write - - - GPIO_QSPI_SD2_EDGE_HIGH - [27:27] - read-write - - - GPIO_QSPI_SD2_EDGE_LOW - [26:26] - read-write - - - GPIO_QSPI_SD2_LEVEL_HIGH - [25:25] - read-write - - - GPIO_QSPI_SD2_LEVEL_LOW - [24:24] - read-write - - - GPIO_QSPI_SD1_EDGE_HIGH - [23:23] - read-write - - - GPIO_QSPI_SD1_EDGE_LOW - [22:22] - read-write - - - GPIO_QSPI_SD1_LEVEL_HIGH - [21:21] - read-write - - - GPIO_QSPI_SD1_LEVEL_LOW - [20:20] - read-write - - - GPIO_QSPI_SD0_EDGE_HIGH - [19:19] - read-write - - - GPIO_QSPI_SD0_EDGE_LOW - [18:18] - read-write - - - GPIO_QSPI_SD0_LEVEL_HIGH - [17:17] - read-write - - - GPIO_QSPI_SD0_LEVEL_LOW - [16:16] - read-write - - - GPIO_QSPI_SS_EDGE_HIGH - [15:15] - read-write - - - GPIO_QSPI_SS_EDGE_LOW - [14:14] - read-write - - - GPIO_QSPI_SS_LEVEL_HIGH - [13:13] - read-write - - - GPIO_QSPI_SS_LEVEL_LOW - [12:12] - read-write - - - GPIO_QSPI_SCLK_EDGE_HIGH - [11:11] - read-write - - - GPIO_QSPI_SCLK_EDGE_LOW - [10:10] - read-write - - - GPIO_QSPI_SCLK_LEVEL_HIGH - [9:9] - read-write - - - GPIO_QSPI_SCLK_LEVEL_LOW - [8:8] - read-write - - - USBPHY_DM_EDGE_HIGH - [7:7] - read-write - - - USBPHY_DM_EDGE_LOW - [6:6] - read-write - - - USBPHY_DM_LEVEL_HIGH - [5:5] - read-write - - - USBPHY_DM_LEVEL_LOW - [4:4] - read-write - - - USBPHY_DP_EDGE_HIGH - [3:3] - read-write - - - USBPHY_DP_EDGE_LOW - [2:2] - read-write - - - USBPHY_DP_LEVEL_HIGH - [1:1] - read-write - - - USBPHY_DP_LEVEL_LOW - [0:0] - read-write - - - - - DORMANT_WAKE_INTF - 0x00000238 - Interrupt Force for dormant_wake - 0x00000000 - - - GPIO_QSPI_SD3_EDGE_HIGH - [31:31] - read-write - - - GPIO_QSPI_SD3_EDGE_LOW - [30:30] - read-write - - - GPIO_QSPI_SD3_LEVEL_HIGH - [29:29] - read-write - - - GPIO_QSPI_SD3_LEVEL_LOW - [28:28] - read-write - - - GPIO_QSPI_SD2_EDGE_HIGH - [27:27] - read-write - - - GPIO_QSPI_SD2_EDGE_LOW - [26:26] - read-write - - - GPIO_QSPI_SD2_LEVEL_HIGH - [25:25] - read-write - - - GPIO_QSPI_SD2_LEVEL_LOW - [24:24] - read-write - - - GPIO_QSPI_SD1_EDGE_HIGH - [23:23] - read-write - - - GPIO_QSPI_SD1_EDGE_LOW - [22:22] - read-write - - - GPIO_QSPI_SD1_LEVEL_HIGH - [21:21] - read-write - - - GPIO_QSPI_SD1_LEVEL_LOW - [20:20] - read-write - - - GPIO_QSPI_SD0_EDGE_HIGH - [19:19] - read-write - - - GPIO_QSPI_SD0_EDGE_LOW - [18:18] - read-write - - - GPIO_QSPI_SD0_LEVEL_HIGH - [17:17] - read-write - - - GPIO_QSPI_SD0_LEVEL_LOW - [16:16] - read-write - - - GPIO_QSPI_SS_EDGE_HIGH - [15:15] - read-write - - - GPIO_QSPI_SS_EDGE_LOW - [14:14] - read-write - - - GPIO_QSPI_SS_LEVEL_HIGH - [13:13] - read-write - - - GPIO_QSPI_SS_LEVEL_LOW - [12:12] - read-write - - - GPIO_QSPI_SCLK_EDGE_HIGH - [11:11] - read-write - - - GPIO_QSPI_SCLK_EDGE_LOW - [10:10] - read-write - - - GPIO_QSPI_SCLK_LEVEL_HIGH - [9:9] - read-write - - - GPIO_QSPI_SCLK_LEVEL_LOW - [8:8] - read-write - - - USBPHY_DM_EDGE_HIGH - [7:7] - read-write - - - USBPHY_DM_EDGE_LOW - [6:6] - read-write - - - USBPHY_DM_LEVEL_HIGH - [5:5] - read-write - - - USBPHY_DM_LEVEL_LOW - [4:4] - read-write - - - USBPHY_DP_EDGE_HIGH - [3:3] - read-write - - - USBPHY_DP_EDGE_LOW - [2:2] - read-write - - - USBPHY_DP_LEVEL_HIGH - [1:1] - read-write - - - USBPHY_DP_LEVEL_LOW - [0:0] - read-write - - - - - DORMANT_WAKE_INTS - 0x0000023c - Interrupt status after masking & forcing for dormant_wake - 0x00000000 - - - GPIO_QSPI_SD3_EDGE_HIGH - [31:31] - read-only - - - GPIO_QSPI_SD3_EDGE_LOW - [30:30] - read-only - - - GPIO_QSPI_SD3_LEVEL_HIGH - [29:29] - read-only - - - GPIO_QSPI_SD3_LEVEL_LOW - [28:28] - read-only - - - GPIO_QSPI_SD2_EDGE_HIGH - [27:27] - read-only - - - GPIO_QSPI_SD2_EDGE_LOW - [26:26] - read-only - - - GPIO_QSPI_SD2_LEVEL_HIGH - [25:25] - read-only - - - GPIO_QSPI_SD2_LEVEL_LOW - [24:24] - read-only - - - GPIO_QSPI_SD1_EDGE_HIGH - [23:23] - read-only - - - GPIO_QSPI_SD1_EDGE_LOW - [22:22] - read-only - - - GPIO_QSPI_SD1_LEVEL_HIGH - [21:21] - read-only - - - GPIO_QSPI_SD1_LEVEL_LOW - [20:20] - read-only - - - GPIO_QSPI_SD0_EDGE_HIGH - [19:19] - read-only - - - GPIO_QSPI_SD0_EDGE_LOW - [18:18] - read-only - - - GPIO_QSPI_SD0_LEVEL_HIGH - [17:17] - read-only - - - GPIO_QSPI_SD0_LEVEL_LOW - [16:16] - read-only - - - GPIO_QSPI_SS_EDGE_HIGH - [15:15] - read-only - - - GPIO_QSPI_SS_EDGE_LOW - [14:14] - read-only - - - GPIO_QSPI_SS_LEVEL_HIGH - [13:13] - read-only - - - GPIO_QSPI_SS_LEVEL_LOW - [12:12] - read-only - - - GPIO_QSPI_SCLK_EDGE_HIGH - [11:11] - read-only - - - GPIO_QSPI_SCLK_EDGE_LOW - [10:10] - read-only - - - GPIO_QSPI_SCLK_LEVEL_HIGH - [9:9] - read-only - - - GPIO_QSPI_SCLK_LEVEL_LOW - [8:8] - read-only - - - USBPHY_DM_EDGE_HIGH - [7:7] - read-only - - - USBPHY_DM_EDGE_LOW - [6:6] - read-only - - - USBPHY_DM_LEVEL_HIGH - [5:5] - read-only - - - USBPHY_DM_LEVEL_LOW - [4:4] - read-only - - - USBPHY_DP_EDGE_HIGH - [3:3] - read-only - - - USBPHY_DP_EDGE_LOW - [2:2] - read-only - - - USBPHY_DP_LEVEL_HIGH - [1:1] - read-only - - - USBPHY_DP_LEVEL_LOW - [0:0] - read-only - - - - - - - IO_BANK0 - 0x40028000 - - 0 - 800 - registers - - - IO_IRQ_BANK0 - 21 - - - IO_IRQ_BANK0_NS - 22 - - - - GPIO0_STATUS - 0x00000000 - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - INFROMPAD - input signal from pad, before filtering and override are applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - - - GPIO0_CTRL - 0x00000004 - 0x0000001f - - - IRQOVER - [29:28] - read-write - - - NORMAL - 0 - don't invert the interrupt - - - INVERT - 1 - invert the interrupt - - - LOW - 2 - drive interrupt low - - - HIGH - 3 - drive interrupt high - - - - - INOVER - [17:16] - read-write - - - NORMAL - 0 - don't invert the peri input - - - INVERT - 1 - invert the peri input - - - LOW - 2 - drive peri input low - - - HIGH - 3 - drive peri input high - - - - - OEOVER - [15:14] - read-write - - - NORMAL - 0 - drive output enable from peripheral signal selected by funcsel - - - INVERT - 1 - drive output enable from inverse of peripheral signal selected by funcsel - - - DISABLE - 2 - disable output - - - ENABLE - 3 - enable output - - - - - OUTOVER - [13:12] - read-write - - - NORMAL - 0 - drive output from peripheral signal selected by funcsel - - - INVERT - 1 - drive output from inverse of peripheral signal selected by funcsel - - - LOW - 2 - drive output low - - - HIGH - 3 - drive output high - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table - 31 == NULL - [4:0] - read-write - - - jtag_tck - 0 - - - spi0_rx - 1 - - - uart0_tx - 2 - - - i2c0_sda - 3 - - - pwm_a_0 - 4 - - - siob_proc_0 - 5 - - - pio0_0 - 6 - - - pio1_0 - 7 - - - pio2_0 - 8 - - - xip_ss_n_1 - 9 - - - usb_muxing_overcurr_detect - 10 - - - null - 31 - - - - - - - GPIO1_STATUS - 0x00000008 - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - INFROMPAD - input signal from pad, before filtering and override are applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - - - GPIO1_CTRL - 0x0000000c - 0x0000001f - - - IRQOVER - [29:28] - read-write - - - NORMAL - 0 - don't invert the interrupt - - - INVERT - 1 - invert the interrupt - - - LOW - 2 - drive interrupt low - - - HIGH - 3 - drive interrupt high - - - - - INOVER - [17:16] - read-write - - - NORMAL - 0 - don't invert the peri input - - - INVERT - 1 - invert the peri input - - - LOW - 2 - drive peri input low - - - HIGH - 3 - drive peri input high - - - - - OEOVER - [15:14] - read-write - - - NORMAL - 0 - drive output enable from peripheral signal selected by funcsel - - - INVERT - 1 - drive output enable from inverse of peripheral signal selected by funcsel - - - DISABLE - 2 - disable output - - - ENABLE - 3 - enable output - - - - - OUTOVER - [13:12] - read-write - - - NORMAL - 0 - drive output from peripheral signal selected by funcsel - - - INVERT - 1 - drive output from inverse of peripheral signal selected by funcsel - - - LOW - 2 - drive output low - - - HIGH - 3 - drive output high - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table - 31 == NULL - [4:0] - read-write - - - jtag_tms - 0 - - - spi0_ss_n - 1 - - - uart0_rx - 2 - - - i2c0_scl - 3 - - - pwm_b_0 - 4 - - - siob_proc_1 - 5 - - - pio0_1 - 6 - - - pio1_1 - 7 - - - pio2_1 - 8 - - - coresight_traceclk - 9 - - - usb_muxing_vbus_detect - 10 - - - null - 31 - - - - - - - GPIO2_STATUS - 0x00000010 - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - INFROMPAD - input signal from pad, before filtering and override are applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - - - GPIO2_CTRL - 0x00000014 - 0x0000001f - - - IRQOVER - [29:28] - read-write - - - NORMAL - 0 - don't invert the interrupt - - - INVERT - 1 - invert the interrupt - - - LOW - 2 - drive interrupt low - - - HIGH - 3 - drive interrupt high - - - - - INOVER - [17:16] - read-write - - - NORMAL - 0 - don't invert the peri input - - - INVERT - 1 - invert the peri input - - - LOW - 2 - drive peri input low - - - HIGH - 3 - drive peri input high - - - - - OEOVER - [15:14] - read-write - - - NORMAL - 0 - drive output enable from peripheral signal selected by funcsel - - - INVERT - 1 - drive output enable from inverse of peripheral signal selected by funcsel - - - DISABLE - 2 - disable output - - - ENABLE - 3 - enable output - - - - - OUTOVER - [13:12] - read-write - - - NORMAL - 0 - drive output from peripheral signal selected by funcsel - - - INVERT - 1 - drive output from inverse of peripheral signal selected by funcsel - - - LOW - 2 - drive output low - - - HIGH - 3 - drive output high - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table - 31 == NULL - [4:0] - read-write - - - jtag_tdi - 0 - - - spi0_sclk - 1 - - - uart0_cts - 2 - - - i2c1_sda - 3 - - - pwm_a_1 - 4 - - - siob_proc_2 - 5 - - - pio0_2 - 6 - - - pio1_2 - 7 - - - pio2_2 - 8 - - - coresight_tracedata_0 - 9 - - - usb_muxing_vbus_en - 10 - - - uart0_tx - 11 - - - null - 31 - - - - - - - GPIO3_STATUS - 0x00000018 - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - INFROMPAD - input signal from pad, before filtering and override are applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - - - GPIO3_CTRL - 0x0000001c - 0x0000001f - - - IRQOVER - [29:28] - read-write - - - NORMAL - 0 - don't invert the interrupt - - - INVERT - 1 - invert the interrupt - - - LOW - 2 - drive interrupt low - - - HIGH - 3 - drive interrupt high - - - - - INOVER - [17:16] - read-write - - - NORMAL - 0 - don't invert the peri input - - - INVERT - 1 - invert the peri input - - - LOW - 2 - drive peri input low - - - HIGH - 3 - drive peri input high - - - - - OEOVER - [15:14] - read-write - - - NORMAL - 0 - drive output enable from peripheral signal selected by funcsel - - - INVERT - 1 - drive output enable from inverse of peripheral signal selected by funcsel - - - DISABLE - 2 - disable output - - - ENABLE - 3 - enable output - - - - - OUTOVER - [13:12] - read-write - - - NORMAL - 0 - drive output from peripheral signal selected by funcsel - - - INVERT - 1 - drive output from inverse of peripheral signal selected by funcsel - - - LOW - 2 - drive output low - - - HIGH - 3 - drive output high - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table - 31 == NULL - [4:0] - read-write - - - jtag_tdo - 0 - - - spi0_tx - 1 - - - uart0_rts - 2 - - - i2c1_scl - 3 - - - pwm_b_1 - 4 - - - siob_proc_3 - 5 - - - pio0_3 - 6 - - - pio1_3 - 7 - - - pio2_3 - 8 - - - coresight_tracedata_1 - 9 - - - usb_muxing_overcurr_detect - 10 - - - uart0_rx - 11 - - - null - 31 - - - - - - - GPIO4_STATUS - 0x00000020 - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - INFROMPAD - input signal from pad, before filtering and override are applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - - - GPIO4_CTRL - 0x00000024 - 0x0000001f - - - IRQOVER - [29:28] - read-write - - - NORMAL - 0 - don't invert the interrupt - - - INVERT - 1 - invert the interrupt - - - LOW - 2 - drive interrupt low - - - HIGH - 3 - drive interrupt high - - - - - INOVER - [17:16] - read-write - - - NORMAL - 0 - don't invert the peri input - - - INVERT - 1 - invert the peri input - - - LOW - 2 - drive peri input low - - - HIGH - 3 - drive peri input high - - - - - OEOVER - [15:14] - read-write - - - NORMAL - 0 - drive output enable from peripheral signal selected by funcsel - - - INVERT - 1 - drive output enable from inverse of peripheral signal selected by funcsel - - - DISABLE - 2 - disable output - - - ENABLE - 3 - enable output - - - - - OUTOVER - [13:12] - read-write - - - NORMAL - 0 - drive output from peripheral signal selected by funcsel - - - INVERT - 1 - drive output from inverse of peripheral signal selected by funcsel - - - LOW - 2 - drive output low - - - HIGH - 3 - drive output high - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table - 31 == NULL - [4:0] - read-write - - - spi0_rx - 1 - - - uart1_tx - 2 - - - i2c0_sda - 3 - - - pwm_a_2 - 4 - - - siob_proc_4 - 5 - - - pio0_4 - 6 - - - pio1_4 - 7 - - - pio2_4 - 8 - - - coresight_tracedata_2 - 9 - - - usb_muxing_vbus_detect - 10 - - - null - 31 - - - - - - - GPIO5_STATUS - 0x00000028 - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - INFROMPAD - input signal from pad, before filtering and override are applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - - - GPIO5_CTRL - 0x0000002c - 0x0000001f - - - IRQOVER - [29:28] - read-write - - - NORMAL - 0 - don't invert the interrupt - - - INVERT - 1 - invert the interrupt - - - LOW - 2 - drive interrupt low - - - HIGH - 3 - drive interrupt high - - - - - INOVER - [17:16] - read-write - - - NORMAL - 0 - don't invert the peri input - - - INVERT - 1 - invert the peri input - - - LOW - 2 - drive peri input low - - - HIGH - 3 - drive peri input high - - - - - OEOVER - [15:14] - read-write - - - NORMAL - 0 - drive output enable from peripheral signal selected by funcsel - - - INVERT - 1 - drive output enable from inverse of peripheral signal selected by funcsel - - - DISABLE - 2 - disable output - - - ENABLE - 3 - enable output - - - - - OUTOVER - [13:12] - read-write - - - NORMAL - 0 - drive output from peripheral signal selected by funcsel - - - INVERT - 1 - drive output from inverse of peripheral signal selected by funcsel - - - LOW - 2 - drive output low - - - HIGH - 3 - drive output high - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table - 31 == NULL - [4:0] - read-write - - - spi0_ss_n - 1 - - - uart1_rx - 2 - - - i2c0_scl - 3 - - - pwm_b_2 - 4 - - - siob_proc_5 - 5 - - - pio0_5 - 6 - - - pio1_5 - 7 - - - pio2_5 - 8 - - - coresight_tracedata_3 - 9 - - - usb_muxing_vbus_en - 10 - - - null - 31 - - - - - - - GPIO6_STATUS - 0x00000030 - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - INFROMPAD - input signal from pad, before filtering and override are applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - - - GPIO6_CTRL - 0x00000034 - 0x0000001f - - - IRQOVER - [29:28] - read-write - - - NORMAL - 0 - don't invert the interrupt - - - INVERT - 1 - invert the interrupt - - - LOW - 2 - drive interrupt low - - - HIGH - 3 - drive interrupt high - - - - - INOVER - [17:16] - read-write - - - NORMAL - 0 - don't invert the peri input - - - INVERT - 1 - invert the peri input - - - LOW - 2 - drive peri input low - - - HIGH - 3 - drive peri input high - - - - - OEOVER - [15:14] - read-write - - - NORMAL - 0 - drive output enable from peripheral signal selected by funcsel - - - INVERT - 1 - drive output enable from inverse of peripheral signal selected by funcsel - - - DISABLE - 2 - disable output - - - ENABLE - 3 - enable output - - - - - OUTOVER - [13:12] - read-write - - - NORMAL - 0 - drive output from peripheral signal selected by funcsel - - - INVERT - 1 - drive output from inverse of peripheral signal selected by funcsel - - - LOW - 2 - drive output low - - - HIGH - 3 - drive output high - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table - 31 == NULL - [4:0] - read-write - - - spi0_sclk - 1 - - - uart1_cts - 2 - - - i2c1_sda - 3 - - - pwm_a_3 - 4 - - - siob_proc_6 - 5 - - - pio0_6 - 6 - - - pio1_6 - 7 - - - pio2_6 - 8 - - - usb_muxing_overcurr_detect - 10 - - - uart1_tx - 11 - - - null - 31 - - - - - - - GPIO7_STATUS - 0x00000038 - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - INFROMPAD - input signal from pad, before filtering and override are applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - - - GPIO7_CTRL - 0x0000003c - 0x0000001f - - - IRQOVER - [29:28] - read-write - - - NORMAL - 0 - don't invert the interrupt - - - INVERT - 1 - invert the interrupt - - - LOW - 2 - drive interrupt low - - - HIGH - 3 - drive interrupt high - - - - - INOVER - [17:16] - read-write - - - NORMAL - 0 - don't invert the peri input - - - INVERT - 1 - invert the peri input - - - LOW - 2 - drive peri input low - - - HIGH - 3 - drive peri input high - - - - - OEOVER - [15:14] - read-write - - - NORMAL - 0 - drive output enable from peripheral signal selected by funcsel - - - INVERT - 1 - drive output enable from inverse of peripheral signal selected by funcsel - - - DISABLE - 2 - disable output - - - ENABLE - 3 - enable output - - - - - OUTOVER - [13:12] - read-write - - - NORMAL - 0 - drive output from peripheral signal selected by funcsel - - - INVERT - 1 - drive output from inverse of peripheral signal selected by funcsel - - - LOW - 2 - drive output low - - - HIGH - 3 - drive output high - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table - 31 == NULL - [4:0] - read-write - - - spi0_tx - 1 - - - uart1_rts - 2 - - - i2c1_scl - 3 - - - pwm_b_3 - 4 - - - siob_proc_7 - 5 - - - pio0_7 - 6 - - - pio1_7 - 7 - - - pio2_7 - 8 - - - usb_muxing_vbus_detect - 10 - - - uart1_rx - 11 - - - null - 31 - - - - - - - GPIO8_STATUS - 0x00000040 - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - INFROMPAD - input signal from pad, before filtering and override are applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - - - GPIO8_CTRL - 0x00000044 - 0x0000001f - - - IRQOVER - [29:28] - read-write - - - NORMAL - 0 - don't invert the interrupt - - - INVERT - 1 - invert the interrupt - - - LOW - 2 - drive interrupt low - - - HIGH - 3 - drive interrupt high - - - - - INOVER - [17:16] - read-write - - - NORMAL - 0 - don't invert the peri input - - - INVERT - 1 - invert the peri input - - - LOW - 2 - drive peri input low - - - HIGH - 3 - drive peri input high - - - - - OEOVER - [15:14] - read-write - - - NORMAL - 0 - drive output enable from peripheral signal selected by funcsel - - - INVERT - 1 - drive output enable from inverse of peripheral signal selected by funcsel - - - DISABLE - 2 - disable output - - - ENABLE - 3 - enable output - - - - - OUTOVER - [13:12] - read-write - - - NORMAL - 0 - drive output from peripheral signal selected by funcsel - - - INVERT - 1 - drive output from inverse of peripheral signal selected by funcsel - - - LOW - 2 - drive output low - - - HIGH - 3 - drive output high - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table - 31 == NULL - [4:0] - read-write - - - spi1_rx - 1 - - - uart1_tx - 2 - - - i2c0_sda - 3 - - - pwm_a_4 - 4 - - - siob_proc_8 - 5 - - - pio0_8 - 6 - - - pio1_8 - 7 - - - pio2_8 - 8 - - - xip_ss_n_1 - 9 - - - usb_muxing_vbus_en - 10 - - - null - 31 - - - - - - - GPIO9_STATUS - 0x00000048 - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - INFROMPAD - input signal from pad, before filtering and override are applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - - - GPIO9_CTRL - 0x0000004c - 0x0000001f - - - IRQOVER - [29:28] - read-write - - - NORMAL - 0 - don't invert the interrupt - - - INVERT - 1 - invert the interrupt - - - LOW - 2 - drive interrupt low - - - HIGH - 3 - drive interrupt high - - - - - INOVER - [17:16] - read-write - - - NORMAL - 0 - don't invert the peri input - - - INVERT - 1 - invert the peri input - - - LOW - 2 - drive peri input low - - - HIGH - 3 - drive peri input high - - - - - OEOVER - [15:14] - read-write - - - NORMAL - 0 - drive output enable from peripheral signal selected by funcsel - - - INVERT - 1 - drive output enable from inverse of peripheral signal selected by funcsel - - - DISABLE - 2 - disable output - - - ENABLE - 3 - enable output - - - - - OUTOVER - [13:12] - read-write - - - NORMAL - 0 - drive output from peripheral signal selected by funcsel - - - INVERT - 1 - drive output from inverse of peripheral signal selected by funcsel - - - LOW - 2 - drive output low - - - HIGH - 3 - drive output high - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table - 31 == NULL - [4:0] - read-write - - - spi1_ss_n - 1 - - - uart1_rx - 2 - - - i2c0_scl - 3 - - - pwm_b_4 - 4 - - - siob_proc_9 - 5 - - - pio0_9 - 6 - - - pio1_9 - 7 - - - pio2_9 - 8 - - - usb_muxing_overcurr_detect - 10 - - - null - 31 - - - - - - - GPIO10_STATUS - 0x00000050 - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - INFROMPAD - input signal from pad, before filtering and override are applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - - - GPIO10_CTRL - 0x00000054 - 0x0000001f - - - IRQOVER - [29:28] - read-write - - - NORMAL - 0 - don't invert the interrupt - - - INVERT - 1 - invert the interrupt - - - LOW - 2 - drive interrupt low - - - HIGH - 3 - drive interrupt high - - - - - INOVER - [17:16] - read-write - - - NORMAL - 0 - don't invert the peri input - - - INVERT - 1 - invert the peri input - - - LOW - 2 - drive peri input low - - - HIGH - 3 - drive peri input high - - - - - OEOVER - [15:14] - read-write - - - NORMAL - 0 - drive output enable from peripheral signal selected by funcsel - - - INVERT - 1 - drive output enable from inverse of peripheral signal selected by funcsel - - - DISABLE - 2 - disable output - - - ENABLE - 3 - enable output - - - - - OUTOVER - [13:12] - read-write - - - NORMAL - 0 - drive output from peripheral signal selected by funcsel - - - INVERT - 1 - drive output from inverse of peripheral signal selected by funcsel - - - LOW - 2 - drive output low - - - HIGH - 3 - drive output high - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table - 31 == NULL - [4:0] - read-write - - - spi1_sclk - 1 - - - uart1_cts - 2 - - - i2c1_sda - 3 - - - pwm_a_5 - 4 - - - siob_proc_10 - 5 - - - pio0_10 - 6 - - - pio1_10 - 7 - - - pio2_10 - 8 - - - usb_muxing_vbus_detect - 10 - - - uart1_tx - 11 - - - null - 31 - - - - - - - GPIO11_STATUS - 0x00000058 - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - INFROMPAD - input signal from pad, before filtering and override are applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - - - GPIO11_CTRL - 0x0000005c - 0x0000001f - - - IRQOVER - [29:28] - read-write - - - NORMAL - 0 - don't invert the interrupt - - - INVERT - 1 - invert the interrupt - - - LOW - 2 - drive interrupt low - - - HIGH - 3 - drive interrupt high - - - - - INOVER - [17:16] - read-write - - - NORMAL - 0 - don't invert the peri input - - - INVERT - 1 - invert the peri input - - - LOW - 2 - drive peri input low - - - HIGH - 3 - drive peri input high - - - - - OEOVER - [15:14] - read-write - - - NORMAL - 0 - drive output enable from peripheral signal selected by funcsel - - - INVERT - 1 - drive output enable from inverse of peripheral signal selected by funcsel - - - DISABLE - 2 - disable output - - - ENABLE - 3 - enable output - - - - - OUTOVER - [13:12] - read-write - - - NORMAL - 0 - drive output from peripheral signal selected by funcsel - - - INVERT - 1 - drive output from inverse of peripheral signal selected by funcsel - - - LOW - 2 - drive output low - - - HIGH - 3 - drive output high - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table - 31 == NULL - [4:0] - read-write - - - spi1_tx - 1 - - - uart1_rts - 2 - - - i2c1_scl - 3 - - - pwm_b_5 - 4 - - - siob_proc_11 - 5 - - - pio0_11 - 6 - - - pio1_11 - 7 - - - pio2_11 - 8 - - - usb_muxing_vbus_en - 10 - - - uart1_rx - 11 - - - null - 31 - - - - - - - GPIO12_STATUS - 0x00000060 - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - INFROMPAD - input signal from pad, before filtering and override are applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - - - GPIO12_CTRL - 0x00000064 - 0x0000001f - - - IRQOVER - [29:28] - read-write - - - NORMAL - 0 - don't invert the interrupt - - - INVERT - 1 - invert the interrupt - - - LOW - 2 - drive interrupt low - - - HIGH - 3 - drive interrupt high - - - - - INOVER - [17:16] - read-write - - - NORMAL - 0 - don't invert the peri input - - - INVERT - 1 - invert the peri input - - - LOW - 2 - drive peri input low - - - HIGH - 3 - drive peri input high - - - - - OEOVER - [15:14] - read-write - - - NORMAL - 0 - drive output enable from peripheral signal selected by funcsel - - - INVERT - 1 - drive output enable from inverse of peripheral signal selected by funcsel - - - DISABLE - 2 - disable output - - - ENABLE - 3 - enable output - - - - - OUTOVER - [13:12] - read-write - - - NORMAL - 0 - drive output from peripheral signal selected by funcsel - - - INVERT - 1 - drive output from inverse of peripheral signal selected by funcsel - - - LOW - 2 - drive output low - - - HIGH - 3 - drive output high - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table - 31 == NULL - [4:0] - read-write - - - hstx_0 - 0 - - - spi1_rx - 1 - - - uart0_tx - 2 - - - i2c0_sda - 3 - - - pwm_a_6 - 4 - - - siob_proc_12 - 5 - - - pio0_12 - 6 - - - pio1_12 - 7 - - - pio2_12 - 8 - - - clocks_gpin_0 - 9 - - - usb_muxing_overcurr_detect - 10 - - - null - 31 - - - - - - - GPIO13_STATUS - 0x00000068 - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - INFROMPAD - input signal from pad, before filtering and override are applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - - - GPIO13_CTRL - 0x0000006c - 0x0000001f - - - IRQOVER - [29:28] - read-write - - - NORMAL - 0 - don't invert the interrupt - - - INVERT - 1 - invert the interrupt - - - LOW - 2 - drive interrupt low - - - HIGH - 3 - drive interrupt high - - - - - INOVER - [17:16] - read-write - - - NORMAL - 0 - don't invert the peri input - - - INVERT - 1 - invert the peri input - - - LOW - 2 - drive peri input low - - - HIGH - 3 - drive peri input high - - - - - OEOVER - [15:14] - read-write - - - NORMAL - 0 - drive output enable from peripheral signal selected by funcsel - - - INVERT - 1 - drive output enable from inverse of peripheral signal selected by funcsel - - - DISABLE - 2 - disable output - - - ENABLE - 3 - enable output - - - - - OUTOVER - [13:12] - read-write - - - NORMAL - 0 - drive output from peripheral signal selected by funcsel - - - INVERT - 1 - drive output from inverse of peripheral signal selected by funcsel - - - LOW - 2 - drive output low - - - HIGH - 3 - drive output high - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table - 31 == NULL - [4:0] - read-write - - - hstx_1 - 0 - - - spi1_ss_n - 1 - - - uart0_rx - 2 - - - i2c0_scl - 3 - - - pwm_b_6 - 4 - - - siob_proc_13 - 5 - - - pio0_13 - 6 - - - pio1_13 - 7 - - - pio2_13 - 8 - - - clocks_gpout_0 - 9 - - - usb_muxing_vbus_detect - 10 - - - null - 31 - - - - - - - GPIO14_STATUS - 0x00000070 - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - INFROMPAD - input signal from pad, before filtering and override are applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - - - GPIO14_CTRL - 0x00000074 - 0x0000001f - - - IRQOVER - [29:28] - read-write - - - NORMAL - 0 - don't invert the interrupt - - - INVERT - 1 - invert the interrupt - - - LOW - 2 - drive interrupt low - - - HIGH - 3 - drive interrupt high - - - - - INOVER - [17:16] - read-write - - - NORMAL - 0 - don't invert the peri input - - - INVERT - 1 - invert the peri input - - - LOW - 2 - drive peri input low - - - HIGH - 3 - drive peri input high - - - - - OEOVER - [15:14] - read-write - - - NORMAL - 0 - drive output enable from peripheral signal selected by funcsel - - - INVERT - 1 - drive output enable from inverse of peripheral signal selected by funcsel - - - DISABLE - 2 - disable output - - - ENABLE - 3 - enable output - - - - - OUTOVER - [13:12] - read-write - - - NORMAL - 0 - drive output from peripheral signal selected by funcsel - - - INVERT - 1 - drive output from inverse of peripheral signal selected by funcsel - - - LOW - 2 - drive output low - - - HIGH - 3 - drive output high - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table - 31 == NULL - [4:0] - read-write - - - hstx_2 - 0 - - - spi1_sclk - 1 - - - uart0_cts - 2 - - - i2c1_sda - 3 - - - pwm_a_7 - 4 - - - siob_proc_14 - 5 - - - pio0_14 - 6 - - - pio1_14 - 7 - - - pio2_14 - 8 - - - clocks_gpin_1 - 9 - - - usb_muxing_vbus_en - 10 - - - uart0_tx - 11 - - - null - 31 - - - - - - - GPIO15_STATUS - 0x00000078 - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - INFROMPAD - input signal from pad, before filtering and override are applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - - - GPIO15_CTRL - 0x0000007c - 0x0000001f - - - IRQOVER - [29:28] - read-write - - - NORMAL - 0 - don't invert the interrupt - - - INVERT - 1 - invert the interrupt - - - LOW - 2 - drive interrupt low - - - HIGH - 3 - drive interrupt high - - - - - INOVER - [17:16] - read-write - - - NORMAL - 0 - don't invert the peri input - - - INVERT - 1 - invert the peri input - - - LOW - 2 - drive peri input low - - - HIGH - 3 - drive peri input high - - - - - OEOVER - [15:14] - read-write - - - NORMAL - 0 - drive output enable from peripheral signal selected by funcsel - - - INVERT - 1 - drive output enable from inverse of peripheral signal selected by funcsel - - - DISABLE - 2 - disable output - - - ENABLE - 3 - enable output - - - - - OUTOVER - [13:12] - read-write - - - NORMAL - 0 - drive output from peripheral signal selected by funcsel - - - INVERT - 1 - drive output from inverse of peripheral signal selected by funcsel - - - LOW - 2 - drive output low - - - HIGH - 3 - drive output high - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table - 31 == NULL - [4:0] - read-write - - - hstx_3 - 0 - - - spi1_tx - 1 - - - uart0_rts - 2 - - - i2c1_scl - 3 - - - pwm_b_7 - 4 - - - siob_proc_15 - 5 - - - pio0_15 - 6 - - - pio1_15 - 7 - - - pio2_15 - 8 - - - clocks_gpout_1 - 9 - - - usb_muxing_overcurr_detect - 10 - - - uart0_rx - 11 - - - null - 31 - - - - - - - GPIO16_STATUS - 0x00000080 - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - INFROMPAD - input signal from pad, before filtering and override are applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - - - GPIO16_CTRL - 0x00000084 - 0x0000001f - - - IRQOVER - [29:28] - read-write - - - NORMAL - 0 - don't invert the interrupt - - - INVERT - 1 - invert the interrupt - - - LOW - 2 - drive interrupt low - - - HIGH - 3 - drive interrupt high - - - - - INOVER - [17:16] - read-write - - - NORMAL - 0 - don't invert the peri input - - - INVERT - 1 - invert the peri input - - - LOW - 2 - drive peri input low - - - HIGH - 3 - drive peri input high - - - - - OEOVER - [15:14] - read-write - - - NORMAL - 0 - drive output enable from peripheral signal selected by funcsel - - - INVERT - 1 - drive output enable from inverse of peripheral signal selected by funcsel - - - DISABLE - 2 - disable output - - - ENABLE - 3 - enable output - - - - - OUTOVER - [13:12] - read-write - - - NORMAL - 0 - drive output from peripheral signal selected by funcsel - - - INVERT - 1 - drive output from inverse of peripheral signal selected by funcsel - - - LOW - 2 - drive output low - - - HIGH - 3 - drive output high - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table - 31 == NULL - [4:0] - read-write - - - hstx_4 - 0 - - - spi0_rx - 1 - - - uart0_tx - 2 - - - i2c0_sda - 3 - - - pwm_a_0 - 4 - - - siob_proc_16 - 5 - - - pio0_16 - 6 - - - pio1_16 - 7 - - - pio2_16 - 8 - - - usb_muxing_vbus_detect - 10 - - - null - 31 - - - - - - - GPIO17_STATUS - 0x00000088 - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - INFROMPAD - input signal from pad, before filtering and override are applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - - - GPIO17_CTRL - 0x0000008c - 0x0000001f - - - IRQOVER - [29:28] - read-write - - - NORMAL - 0 - don't invert the interrupt - - - INVERT - 1 - invert the interrupt - - - LOW - 2 - drive interrupt low - - - HIGH - 3 - drive interrupt high - - - - - INOVER - [17:16] - read-write - - - NORMAL - 0 - don't invert the peri input - - - INVERT - 1 - invert the peri input - - - LOW - 2 - drive peri input low - - - HIGH - 3 - drive peri input high - - - - - OEOVER - [15:14] - read-write - - - NORMAL - 0 - drive output enable from peripheral signal selected by funcsel - - - INVERT - 1 - drive output enable from inverse of peripheral signal selected by funcsel - - - DISABLE - 2 - disable output - - - ENABLE - 3 - enable output - - - - - OUTOVER - [13:12] - read-write - - - NORMAL - 0 - drive output from peripheral signal selected by funcsel - - - INVERT - 1 - drive output from inverse of peripheral signal selected by funcsel - - - LOW - 2 - drive output low - - - HIGH - 3 - drive output high - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table - 31 == NULL - [4:0] - read-write - - - hstx_5 - 0 - - - spi0_ss_n - 1 - - - uart0_rx - 2 - - - i2c0_scl - 3 - - - pwm_b_0 - 4 - - - siob_proc_17 - 5 - - - pio0_17 - 6 - - - pio1_17 - 7 - - - pio2_17 - 8 - - - usb_muxing_vbus_en - 10 - - - null - 31 - - - - - - - GPIO18_STATUS - 0x00000090 - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - INFROMPAD - input signal from pad, before filtering and override are applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - - - GPIO18_CTRL - 0x00000094 - 0x0000001f - - - IRQOVER - [29:28] - read-write - - - NORMAL - 0 - don't invert the interrupt - - - INVERT - 1 - invert the interrupt - - - LOW - 2 - drive interrupt low - - - HIGH - 3 - drive interrupt high - - - - - INOVER - [17:16] - read-write - - - NORMAL - 0 - don't invert the peri input - - - INVERT - 1 - invert the peri input - - - LOW - 2 - drive peri input low - - - HIGH - 3 - drive peri input high - - - - - OEOVER - [15:14] - read-write - - - NORMAL - 0 - drive output enable from peripheral signal selected by funcsel - - - INVERT - 1 - drive output enable from inverse of peripheral signal selected by funcsel - - - DISABLE - 2 - disable output - - - ENABLE - 3 - enable output - - - - - OUTOVER - [13:12] - read-write - - - NORMAL - 0 - drive output from peripheral signal selected by funcsel - - - INVERT - 1 - drive output from inverse of peripheral signal selected by funcsel - - - LOW - 2 - drive output low - - - HIGH - 3 - drive output high - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table - 31 == NULL - [4:0] - read-write - - - hstx_6 - 0 - - - spi0_sclk - 1 - - - uart0_cts - 2 - - - i2c1_sda - 3 - - - pwm_a_1 - 4 - - - siob_proc_18 - 5 - - - pio0_18 - 6 - - - pio1_18 - 7 - - - pio2_18 - 8 - - - usb_muxing_overcurr_detect - 10 - - - uart0_tx - 11 - - - null - 31 - - - - - - - GPIO19_STATUS - 0x00000098 - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - INFROMPAD - input signal from pad, before filtering and override are applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - - - GPIO19_CTRL - 0x0000009c - 0x0000001f - - - IRQOVER - [29:28] - read-write - - - NORMAL - 0 - don't invert the interrupt - - - INVERT - 1 - invert the interrupt - - - LOW - 2 - drive interrupt low - - - HIGH - 3 - drive interrupt high - - - - - INOVER - [17:16] - read-write - - - NORMAL - 0 - don't invert the peri input - - - INVERT - 1 - invert the peri input - - - LOW - 2 - drive peri input low - - - HIGH - 3 - drive peri input high - - - - - OEOVER - [15:14] - read-write - - - NORMAL - 0 - drive output enable from peripheral signal selected by funcsel - - - INVERT - 1 - drive output enable from inverse of peripheral signal selected by funcsel - - - DISABLE - 2 - disable output - - - ENABLE - 3 - enable output - - - - - OUTOVER - [13:12] - read-write - - - NORMAL - 0 - drive output from peripheral signal selected by funcsel - - - INVERT - 1 - drive output from inverse of peripheral signal selected by funcsel - - - LOW - 2 - drive output low - - - HIGH - 3 - drive output high - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table - 31 == NULL - [4:0] - read-write - - - hstx_7 - 0 - - - spi0_tx - 1 - - - uart0_rts - 2 - - - i2c1_scl - 3 - - - pwm_b_1 - 4 - - - siob_proc_19 - 5 - - - pio0_19 - 6 - - - pio1_19 - 7 - - - pio2_19 - 8 - - - xip_ss_n_1 - 9 - - - usb_muxing_vbus_detect - 10 - - - uart0_rx - 11 - - - null - 31 - - - - - - - GPIO20_STATUS - 0x000000a0 - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - INFROMPAD - input signal from pad, before filtering and override are applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - - - GPIO20_CTRL - 0x000000a4 - 0x0000001f - - - IRQOVER - [29:28] - read-write - - - NORMAL - 0 - don't invert the interrupt - - - INVERT - 1 - invert the interrupt - - - LOW - 2 - drive interrupt low - - - HIGH - 3 - drive interrupt high - - - - - INOVER - [17:16] - read-write - - - NORMAL - 0 - don't invert the peri input - - - INVERT - 1 - invert the peri input - - - LOW - 2 - drive peri input low - - - HIGH - 3 - drive peri input high - - - - - OEOVER - [15:14] - read-write - - - NORMAL - 0 - drive output enable from peripheral signal selected by funcsel - - - INVERT - 1 - drive output enable from inverse of peripheral signal selected by funcsel - - - DISABLE - 2 - disable output - - - ENABLE - 3 - enable output - - - - - OUTOVER - [13:12] - read-write - - - NORMAL - 0 - drive output from peripheral signal selected by funcsel - - - INVERT - 1 - drive output from inverse of peripheral signal selected by funcsel - - - LOW - 2 - drive output low - - - HIGH - 3 - drive output high - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table - 31 == NULL - [4:0] - read-write - - - spi0_rx - 1 - - - uart1_tx - 2 - - - i2c0_sda - 3 - - - pwm_a_2 - 4 - - - siob_proc_20 - 5 - - - pio0_20 - 6 - - - pio1_20 - 7 - - - pio2_20 - 8 - - - clocks_gpin_0 - 9 - - - usb_muxing_vbus_en - 10 - - - null - 31 - - - - - - - GPIO21_STATUS - 0x000000a8 - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - INFROMPAD - input signal from pad, before filtering and override are applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - - - GPIO21_CTRL - 0x000000ac - 0x0000001f - - - IRQOVER - [29:28] - read-write - - - NORMAL - 0 - don't invert the interrupt - - - INVERT - 1 - invert the interrupt - - - LOW - 2 - drive interrupt low - - - HIGH - 3 - drive interrupt high - - - - - INOVER - [17:16] - read-write - - - NORMAL - 0 - don't invert the peri input - - - INVERT - 1 - invert the peri input - - - LOW - 2 - drive peri input low - - - HIGH - 3 - drive peri input high - - - - - OEOVER - [15:14] - read-write - - - NORMAL - 0 - drive output enable from peripheral signal selected by funcsel - - - INVERT - 1 - drive output enable from inverse of peripheral signal selected by funcsel - - - DISABLE - 2 - disable output - - - ENABLE - 3 - enable output - - - - - OUTOVER - [13:12] - read-write - - - NORMAL - 0 - drive output from peripheral signal selected by funcsel - - - INVERT - 1 - drive output from inverse of peripheral signal selected by funcsel - - - LOW - 2 - drive output low - - - HIGH - 3 - drive output high - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table - 31 == NULL - [4:0] - read-write - - - spi0_ss_n - 1 - - - uart1_rx - 2 - - - i2c0_scl - 3 - - - pwm_b_2 - 4 - - - siob_proc_21 - 5 - - - pio0_21 - 6 - - - pio1_21 - 7 - - - pio2_21 - 8 - - - clocks_gpout_0 - 9 - - - usb_muxing_overcurr_detect - 10 - - - null - 31 - - - - - - - GPIO22_STATUS - 0x000000b0 - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - INFROMPAD - input signal from pad, before filtering and override are applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - - - GPIO22_CTRL - 0x000000b4 - 0x0000001f - - - IRQOVER - [29:28] - read-write - - - NORMAL - 0 - don't invert the interrupt - - - INVERT - 1 - invert the interrupt - - - LOW - 2 - drive interrupt low - - - HIGH - 3 - drive interrupt high - - - - - INOVER - [17:16] - read-write - - - NORMAL - 0 - don't invert the peri input - - - INVERT - 1 - invert the peri input - - - LOW - 2 - drive peri input low - - - HIGH - 3 - drive peri input high - - - - - OEOVER - [15:14] - read-write - - - NORMAL - 0 - drive output enable from peripheral signal selected by funcsel - - - INVERT - 1 - drive output enable from inverse of peripheral signal selected by funcsel - - - DISABLE - 2 - disable output - - - ENABLE - 3 - enable output - - - - - OUTOVER - [13:12] - read-write - - - NORMAL - 0 - drive output from peripheral signal selected by funcsel - - - INVERT - 1 - drive output from inverse of peripheral signal selected by funcsel - - - LOW - 2 - drive output low - - - HIGH - 3 - drive output high - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table - 31 == NULL - [4:0] - read-write - - - spi0_sclk - 1 - - - uart1_cts - 2 - - - i2c1_sda - 3 - - - pwm_a_3 - 4 - - - siob_proc_22 - 5 - - - pio0_22 - 6 - - - pio1_22 - 7 - - - pio2_22 - 8 - - - clocks_gpin_1 - 9 - - - usb_muxing_vbus_detect - 10 - - - uart1_tx - 11 - - - null - 31 - - - - - - - GPIO23_STATUS - 0x000000b8 - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - INFROMPAD - input signal from pad, before filtering and override are applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - - - GPIO23_CTRL - 0x000000bc - 0x0000001f - - - IRQOVER - [29:28] - read-write - - - NORMAL - 0 - don't invert the interrupt - - - INVERT - 1 - invert the interrupt - - - LOW - 2 - drive interrupt low - - - HIGH - 3 - drive interrupt high - - - - - INOVER - [17:16] - read-write - - - NORMAL - 0 - don't invert the peri input - - - INVERT - 1 - invert the peri input - - - LOW - 2 - drive peri input low - - - HIGH - 3 - drive peri input high - - - - - OEOVER - [15:14] - read-write - - - NORMAL - 0 - drive output enable from peripheral signal selected by funcsel - - - INVERT - 1 - drive output enable from inverse of peripheral signal selected by funcsel - - - DISABLE - 2 - disable output - - - ENABLE - 3 - enable output - - - - - OUTOVER - [13:12] - read-write - - - NORMAL - 0 - drive output from peripheral signal selected by funcsel - - - INVERT - 1 - drive output from inverse of peripheral signal selected by funcsel - - - LOW - 2 - drive output low - - - HIGH - 3 - drive output high - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table - 31 == NULL - [4:0] - read-write - - - spi0_tx - 1 - - - uart1_rts - 2 - - - i2c1_scl - 3 - - - pwm_b_3 - 4 - - - siob_proc_23 - 5 - - - pio0_23 - 6 - - - pio1_23 - 7 - - - pio2_23 - 8 - - - clocks_gpout_1 - 9 - - - usb_muxing_vbus_en - 10 - - - uart1_rx - 11 - - - null - 31 - - - - - - - GPIO24_STATUS - 0x000000c0 - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - INFROMPAD - input signal from pad, before filtering and override are applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - - - GPIO24_CTRL - 0x000000c4 - 0x0000001f - - - IRQOVER - [29:28] - read-write - - - NORMAL - 0 - don't invert the interrupt - - - INVERT - 1 - invert the interrupt - - - LOW - 2 - drive interrupt low - - - HIGH - 3 - drive interrupt high - - - - - INOVER - [17:16] - read-write - - - NORMAL - 0 - don't invert the peri input - - - INVERT - 1 - invert the peri input - - - LOW - 2 - drive peri input low - - - HIGH - 3 - drive peri input high - - - - - OEOVER - [15:14] - read-write - - - NORMAL - 0 - drive output enable from peripheral signal selected by funcsel - - - INVERT - 1 - drive output enable from inverse of peripheral signal selected by funcsel - - - DISABLE - 2 - disable output - - - ENABLE - 3 - enable output - - - - - OUTOVER - [13:12] - read-write - - - NORMAL - 0 - drive output from peripheral signal selected by funcsel - - - INVERT - 1 - drive output from inverse of peripheral signal selected by funcsel - - - LOW - 2 - drive output low - - - HIGH - 3 - drive output high - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table - 31 == NULL - [4:0] - read-write - - - spi1_rx - 1 - - - uart1_tx - 2 - - - i2c0_sda - 3 - - - pwm_a_4 - 4 - - - siob_proc_24 - 5 - - - pio0_24 - 6 - - - pio1_24 - 7 - - - pio2_24 - 8 - - - clocks_gpout_2 - 9 - - - usb_muxing_overcurr_detect - 10 - - - null - 31 - - - - - - - GPIO25_STATUS - 0x000000c8 - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - INFROMPAD - input signal from pad, before filtering and override are applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - - - GPIO25_CTRL - 0x000000cc - 0x0000001f - - - IRQOVER - [29:28] - read-write - - - NORMAL - 0 - don't invert the interrupt - - - INVERT - 1 - invert the interrupt - - - LOW - 2 - drive interrupt low - - - HIGH - 3 - drive interrupt high - - - - - INOVER - [17:16] - read-write - - - NORMAL - 0 - don't invert the peri input - - - INVERT - 1 - invert the peri input - - - LOW - 2 - drive peri input low - - - HIGH - 3 - drive peri input high - - - - - OEOVER - [15:14] - read-write - - - NORMAL - 0 - drive output enable from peripheral signal selected by funcsel - - - INVERT - 1 - drive output enable from inverse of peripheral signal selected by funcsel - - - DISABLE - 2 - disable output - - - ENABLE - 3 - enable output - - - - - OUTOVER - [13:12] - read-write - - - NORMAL - 0 - drive output from peripheral signal selected by funcsel - - - INVERT - 1 - drive output from inverse of peripheral signal selected by funcsel - - - LOW - 2 - drive output low - - - HIGH - 3 - drive output high - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table - 31 == NULL - [4:0] - read-write - - - spi1_ss_n - 1 - - - uart1_rx - 2 - - - i2c0_scl - 3 - - - pwm_b_4 - 4 - - - siob_proc_25 - 5 - - - pio0_25 - 6 - - - pio1_25 - 7 - - - pio2_25 - 8 - - - clocks_gpout_3 - 9 - - - usb_muxing_vbus_detect - 10 - - - null - 31 - - - - - - - GPIO26_STATUS - 0x000000d0 - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - INFROMPAD - input signal from pad, before filtering and override are applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - - - GPIO26_CTRL - 0x000000d4 - 0x0000001f - - - IRQOVER - [29:28] - read-write - - - NORMAL - 0 - don't invert the interrupt - - - INVERT - 1 - invert the interrupt - - - LOW - 2 - drive interrupt low - - - HIGH - 3 - drive interrupt high - - - - - INOVER - [17:16] - read-write - - - NORMAL - 0 - don't invert the peri input - - - INVERT - 1 - invert the peri input - - - LOW - 2 - drive peri input low - - - HIGH - 3 - drive peri input high - - - - - OEOVER - [15:14] - read-write - - - NORMAL - 0 - drive output enable from peripheral signal selected by funcsel - - - INVERT - 1 - drive output enable from inverse of peripheral signal selected by funcsel - - - DISABLE - 2 - disable output - - - ENABLE - 3 - enable output - - - - - OUTOVER - [13:12] - read-write - - - NORMAL - 0 - drive output from peripheral signal selected by funcsel - - - INVERT - 1 - drive output from inverse of peripheral signal selected by funcsel - - - LOW - 2 - drive output low - - - HIGH - 3 - drive output high - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table - 31 == NULL - [4:0] - read-write - - - spi1_sclk - 1 - - - uart1_cts - 2 - - - i2c1_sda - 3 - - - pwm_a_5 - 4 - - - siob_proc_26 - 5 - - - pio0_26 - 6 - - - pio1_26 - 7 - - - pio2_26 - 8 - - - usb_muxing_vbus_en - 10 - - - uart1_tx - 11 - - - null - 31 - - - - - - - GPIO27_STATUS - 0x000000d8 - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - INFROMPAD - input signal from pad, before filtering and override are applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - - - GPIO27_CTRL - 0x000000dc - 0x0000001f - - - IRQOVER - [29:28] - read-write - - - NORMAL - 0 - don't invert the interrupt - - - INVERT - 1 - invert the interrupt - - - LOW - 2 - drive interrupt low - - - HIGH - 3 - drive interrupt high - - - - - INOVER - [17:16] - read-write - - - NORMAL - 0 - don't invert the peri input - - - INVERT - 1 - invert the peri input - - - LOW - 2 - drive peri input low - - - HIGH - 3 - drive peri input high - - - - - OEOVER - [15:14] - read-write - - - NORMAL - 0 - drive output enable from peripheral signal selected by funcsel - - - INVERT - 1 - drive output enable from inverse of peripheral signal selected by funcsel - - - DISABLE - 2 - disable output - - - ENABLE - 3 - enable output - - - - - OUTOVER - [13:12] - read-write - - - NORMAL - 0 - drive output from peripheral signal selected by funcsel - - - INVERT - 1 - drive output from inverse of peripheral signal selected by funcsel - - - LOW - 2 - drive output low - - - HIGH - 3 - drive output high - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table - 31 == NULL - [4:0] - read-write - - - spi1_tx - 1 - - - uart1_rts - 2 - - - i2c1_scl - 3 - - - pwm_b_5 - 4 - - - siob_proc_27 - 5 - - - pio0_27 - 6 - - - pio1_27 - 7 - - - pio2_27 - 8 - - - usb_muxing_overcurr_detect - 10 - - - uart1_rx - 11 - - - null - 31 - - - - - - - GPIO28_STATUS - 0x000000e0 - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - INFROMPAD - input signal from pad, before filtering and override are applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - - - GPIO28_CTRL - 0x000000e4 - 0x0000001f - - - IRQOVER - [29:28] - read-write - - - NORMAL - 0 - don't invert the interrupt - - - INVERT - 1 - invert the interrupt - - - LOW - 2 - drive interrupt low - - - HIGH - 3 - drive interrupt high - - - - - INOVER - [17:16] - read-write - - - NORMAL - 0 - don't invert the peri input - - - INVERT - 1 - invert the peri input - - - LOW - 2 - drive peri input low - - - HIGH - 3 - drive peri input high - - - - - OEOVER - [15:14] - read-write - - - NORMAL - 0 - drive output enable from peripheral signal selected by funcsel - - - INVERT - 1 - drive output enable from inverse of peripheral signal selected by funcsel - - - DISABLE - 2 - disable output - - - ENABLE - 3 - enable output - - - - - OUTOVER - [13:12] - read-write - - - NORMAL - 0 - drive output from peripheral signal selected by funcsel - - - INVERT - 1 - drive output from inverse of peripheral signal selected by funcsel - - - LOW - 2 - drive output low - - - HIGH - 3 - drive output high - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table - 31 == NULL - [4:0] - read-write - - - spi1_rx - 1 - - - uart0_tx - 2 - - - i2c0_sda - 3 - - - pwm_a_6 - 4 - - - siob_proc_28 - 5 - - - pio0_28 - 6 - - - pio1_28 - 7 - - - pio2_28 - 8 - - - usb_muxing_vbus_detect - 10 - - - null - 31 - - - - - - - GPIO29_STATUS - 0x000000e8 - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - INFROMPAD - input signal from pad, before filtering and override are applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - - - GPIO29_CTRL - 0x000000ec - 0x0000001f - - - IRQOVER - [29:28] - read-write - - - NORMAL - 0 - don't invert the interrupt - - - INVERT - 1 - invert the interrupt - - - LOW - 2 - drive interrupt low - - - HIGH - 3 - drive interrupt high - - - - - INOVER - [17:16] - read-write - - - NORMAL - 0 - don't invert the peri input - - - INVERT - 1 - invert the peri input - - - LOW - 2 - drive peri input low - - - HIGH - 3 - drive peri input high - - - - - OEOVER - [15:14] - read-write - - - NORMAL - 0 - drive output enable from peripheral signal selected by funcsel - - - INVERT - 1 - drive output enable from inverse of peripheral signal selected by funcsel - - - DISABLE - 2 - disable output - - - ENABLE - 3 - enable output - - - - - OUTOVER - [13:12] - read-write - - - NORMAL - 0 - drive output from peripheral signal selected by funcsel - - - INVERT - 1 - drive output from inverse of peripheral signal selected by funcsel - - - LOW - 2 - drive output low - - - HIGH - 3 - drive output high - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table - 31 == NULL - [4:0] - read-write - - - spi1_ss_n - 1 - - - uart0_rx - 2 - - - i2c0_scl - 3 - - - pwm_b_6 - 4 - - - siob_proc_29 - 5 - - - pio0_29 - 6 - - - pio1_29 - 7 - - - pio2_29 - 8 - - - usb_muxing_vbus_en - 10 - - - null - 31 - - - - - - - GPIO30_STATUS - 0x000000f0 - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - INFROMPAD - input signal from pad, before filtering and override are applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - - - GPIO30_CTRL - 0x000000f4 - 0x0000001f - - - IRQOVER - [29:28] - read-write - - - NORMAL - 0 - don't invert the interrupt - - - INVERT - 1 - invert the interrupt - - - LOW - 2 - drive interrupt low - - - HIGH - 3 - drive interrupt high - - - - - INOVER - [17:16] - read-write - - - NORMAL - 0 - don't invert the peri input - - - INVERT - 1 - invert the peri input - - - LOW - 2 - drive peri input low - - - HIGH - 3 - drive peri input high - - - - - OEOVER - [15:14] - read-write - - - NORMAL - 0 - drive output enable from peripheral signal selected by funcsel - - - INVERT - 1 - drive output enable from inverse of peripheral signal selected by funcsel - - - DISABLE - 2 - disable output - - - ENABLE - 3 - enable output - - - - - OUTOVER - [13:12] - read-write - - - NORMAL - 0 - drive output from peripheral signal selected by funcsel - - - INVERT - 1 - drive output from inverse of peripheral signal selected by funcsel - - - LOW - 2 - drive output low - - - HIGH - 3 - drive output high - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table - 31 == NULL - [4:0] - read-write - - - spi1_sclk - 1 - - - uart0_cts - 2 - - - i2c1_sda - 3 - - - pwm_a_7 - 4 - - - siob_proc_30 - 5 - - - pio0_30 - 6 - - - pio1_30 - 7 - - - pio2_30 - 8 - - - usb_muxing_overcurr_detect - 10 - - - uart0_tx - 11 - - - null - 31 - - - - - - - GPIO31_STATUS - 0x000000f8 - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - INFROMPAD - input signal from pad, before filtering and override are applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - - - GPIO31_CTRL - 0x000000fc - 0x0000001f - - - IRQOVER - [29:28] - read-write - - - NORMAL - 0 - don't invert the interrupt - - - INVERT - 1 - invert the interrupt - - - LOW - 2 - drive interrupt low - - - HIGH - 3 - drive interrupt high - - - - - INOVER - [17:16] - read-write - - - NORMAL - 0 - don't invert the peri input - - - INVERT - 1 - invert the peri input - - - LOW - 2 - drive peri input low - - - HIGH - 3 - drive peri input high - - - - - OEOVER - [15:14] - read-write - - - NORMAL - 0 - drive output enable from peripheral signal selected by funcsel - - - INVERT - 1 - drive output enable from inverse of peripheral signal selected by funcsel - - - DISABLE - 2 - disable output - - - ENABLE - 3 - enable output - - - - - OUTOVER - [13:12] - read-write - - - NORMAL - 0 - drive output from peripheral signal selected by funcsel - - - INVERT - 1 - drive output from inverse of peripheral signal selected by funcsel - - - LOW - 2 - drive output low - - - HIGH - 3 - drive output high - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table - 31 == NULL - [4:0] - read-write - - - spi1_tx - 1 - - - uart0_rts - 2 - - - i2c1_scl - 3 - - - pwm_b_7 - 4 - - - siob_proc_31 - 5 - - - pio0_31 - 6 - - - pio1_31 - 7 - - - pio2_31 - 8 - - - usb_muxing_vbus_detect - 10 - - - uart0_rx - 11 - - - null - 31 - - - - - - - GPIO32_STATUS - 0x00000100 - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - INFROMPAD - input signal from pad, before filtering and override are applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - - - GPIO32_CTRL - 0x00000104 - 0x0000001f - - - IRQOVER - [29:28] - read-write - - - NORMAL - 0 - don't invert the interrupt - - - INVERT - 1 - invert the interrupt - - - LOW - 2 - drive interrupt low - - - HIGH - 3 - drive interrupt high - - - - - INOVER - [17:16] - read-write - - - NORMAL - 0 - don't invert the peri input - - - INVERT - 1 - invert the peri input - - - LOW - 2 - drive peri input low - - - HIGH - 3 - drive peri input high - - - - - OEOVER - [15:14] - read-write - - - NORMAL - 0 - drive output enable from peripheral signal selected by funcsel - - - INVERT - 1 - drive output enable from inverse of peripheral signal selected by funcsel - - - DISABLE - 2 - disable output - - - ENABLE - 3 - enable output - - - - - OUTOVER - [13:12] - read-write - - - NORMAL - 0 - drive output from peripheral signal selected by funcsel - - - INVERT - 1 - drive output from inverse of peripheral signal selected by funcsel - - - LOW - 2 - drive output low - - - HIGH - 3 - drive output high - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table - 31 == NULL - [4:0] - read-write - - - spi0_rx - 1 - - - uart0_tx - 2 - - - i2c0_sda - 3 - - - pwm_a_8 - 4 - - - siob_proc_32 - 5 - - - pio0_32 - 6 - - - pio1_32 - 7 - - - pio2_32 - 8 - - - usb_muxing_vbus_en - 10 - - - null - 31 - - - - - - - GPIO33_STATUS - 0x00000108 - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - INFROMPAD - input signal from pad, before filtering and override are applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - - - GPIO33_CTRL - 0x0000010c - 0x0000001f - - - IRQOVER - [29:28] - read-write - - - NORMAL - 0 - don't invert the interrupt - - - INVERT - 1 - invert the interrupt - - - LOW - 2 - drive interrupt low - - - HIGH - 3 - drive interrupt high - - - - - INOVER - [17:16] - read-write - - - NORMAL - 0 - don't invert the peri input - - - INVERT - 1 - invert the peri input - - - LOW - 2 - drive peri input low - - - HIGH - 3 - drive peri input high - - - - - OEOVER - [15:14] - read-write - - - NORMAL - 0 - drive output enable from peripheral signal selected by funcsel - - - INVERT - 1 - drive output enable from inverse of peripheral signal selected by funcsel - - - DISABLE - 2 - disable output - - - ENABLE - 3 - enable output - - - - - OUTOVER - [13:12] - read-write - - - NORMAL - 0 - drive output from peripheral signal selected by funcsel - - - INVERT - 1 - drive output from inverse of peripheral signal selected by funcsel - - - LOW - 2 - drive output low - - - HIGH - 3 - drive output high - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table - 31 == NULL - [4:0] - read-write - - - spi0_ss_n - 1 - - - uart0_rx - 2 - - - i2c0_scl - 3 - - - pwm_b_8 - 4 - - - siob_proc_33 - 5 - - - pio0_33 - 6 - - - pio1_33 - 7 - - - pio2_33 - 8 - - - usb_muxing_overcurr_detect - 10 - - - null - 31 - - - - - - - GPIO34_STATUS - 0x00000110 - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - INFROMPAD - input signal from pad, before filtering and override are applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - - - GPIO34_CTRL - 0x00000114 - 0x0000001f - - - IRQOVER - [29:28] - read-write - - - NORMAL - 0 - don't invert the interrupt - - - INVERT - 1 - invert the interrupt - - - LOW - 2 - drive interrupt low - - - HIGH - 3 - drive interrupt high - - - - - INOVER - [17:16] - read-write - - - NORMAL - 0 - don't invert the peri input - - - INVERT - 1 - invert the peri input - - - LOW - 2 - drive peri input low - - - HIGH - 3 - drive peri input high - - - - - OEOVER - [15:14] - read-write - - - NORMAL - 0 - drive output enable from peripheral signal selected by funcsel - - - INVERT - 1 - drive output enable from inverse of peripheral signal selected by funcsel - - - DISABLE - 2 - disable output - - - ENABLE - 3 - enable output - - - - - OUTOVER - [13:12] - read-write - - - NORMAL - 0 - drive output from peripheral signal selected by funcsel - - - INVERT - 1 - drive output from inverse of peripheral signal selected by funcsel - - - LOW - 2 - drive output low - - - HIGH - 3 - drive output high - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table - 31 == NULL - [4:0] - read-write - - - spi0_sclk - 1 - - - uart0_cts - 2 - - - i2c1_sda - 3 - - - pwm_a_9 - 4 - - - siob_proc_34 - 5 - - - pio0_34 - 6 - - - pio1_34 - 7 - - - pio2_34 - 8 - - - usb_muxing_vbus_detect - 10 - - - uart0_tx - 11 - - - null - 31 - - - - - - - GPIO35_STATUS - 0x00000118 - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - INFROMPAD - input signal from pad, before filtering and override are applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - - - GPIO35_CTRL - 0x0000011c - 0x0000001f - - - IRQOVER - [29:28] - read-write - - - NORMAL - 0 - don't invert the interrupt - - - INVERT - 1 - invert the interrupt - - - LOW - 2 - drive interrupt low - - - HIGH - 3 - drive interrupt high - - - - - INOVER - [17:16] - read-write - - - NORMAL - 0 - don't invert the peri input - - - INVERT - 1 - invert the peri input - - - LOW - 2 - drive peri input low - - - HIGH - 3 - drive peri input high - - - - - OEOVER - [15:14] - read-write - - - NORMAL - 0 - drive output enable from peripheral signal selected by funcsel - - - INVERT - 1 - drive output enable from inverse of peripheral signal selected by funcsel - - - DISABLE - 2 - disable output - - - ENABLE - 3 - enable output - - - - - OUTOVER - [13:12] - read-write - - - NORMAL - 0 - drive output from peripheral signal selected by funcsel - - - INVERT - 1 - drive output from inverse of peripheral signal selected by funcsel - - - LOW - 2 - drive output low - - - HIGH - 3 - drive output high - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table - 31 == NULL - [4:0] - read-write - - - spi0_tx - 1 - - - uart0_rts - 2 - - - i2c1_scl - 3 - - - pwm_b_9 - 4 - - - siob_proc_35 - 5 - - - pio0_35 - 6 - - - pio1_35 - 7 - - - pio2_35 - 8 - - - usb_muxing_vbus_en - 10 - - - uart0_rx - 11 - - - null - 31 - - - - - - - GPIO36_STATUS - 0x00000120 - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - INFROMPAD - input signal from pad, before filtering and override are applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - - - GPIO36_CTRL - 0x00000124 - 0x0000001f - - - IRQOVER - [29:28] - read-write - - - NORMAL - 0 - don't invert the interrupt - - - INVERT - 1 - invert the interrupt - - - LOW - 2 - drive interrupt low - - - HIGH - 3 - drive interrupt high - - - - - INOVER - [17:16] - read-write - - - NORMAL - 0 - don't invert the peri input - - - INVERT - 1 - invert the peri input - - - LOW - 2 - drive peri input low - - - HIGH - 3 - drive peri input high - - - - - OEOVER - [15:14] - read-write - - - NORMAL - 0 - drive output enable from peripheral signal selected by funcsel - - - INVERT - 1 - drive output enable from inverse of peripheral signal selected by funcsel - - - DISABLE - 2 - disable output - - - ENABLE - 3 - enable output - - - - - OUTOVER - [13:12] - read-write - - - NORMAL - 0 - drive output from peripheral signal selected by funcsel - - - INVERT - 1 - drive output from inverse of peripheral signal selected by funcsel - - - LOW - 2 - drive output low - - - HIGH - 3 - drive output high - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table - 31 == NULL - [4:0] - read-write - - - spi0_rx - 1 - - - uart1_tx - 2 - - - i2c0_sda - 3 - - - pwm_a_10 - 4 - - - siob_proc_36 - 5 - - - pio0_36 - 6 - - - pio1_36 - 7 - - - pio2_36 - 8 - - - usb_muxing_overcurr_detect - 10 - - - null - 31 - - - - - - - GPIO37_STATUS - 0x00000128 - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - INFROMPAD - input signal from pad, before filtering and override are applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - - - GPIO37_CTRL - 0x0000012c - 0x0000001f - - - IRQOVER - [29:28] - read-write - - - NORMAL - 0 - don't invert the interrupt - - - INVERT - 1 - invert the interrupt - - - LOW - 2 - drive interrupt low - - - HIGH - 3 - drive interrupt high - - - - - INOVER - [17:16] - read-write - - - NORMAL - 0 - don't invert the peri input - - - INVERT - 1 - invert the peri input - - - LOW - 2 - drive peri input low - - - HIGH - 3 - drive peri input high - - - - - OEOVER - [15:14] - read-write - - - NORMAL - 0 - drive output enable from peripheral signal selected by funcsel - - - INVERT - 1 - drive output enable from inverse of peripheral signal selected by funcsel - - - DISABLE - 2 - disable output - - - ENABLE - 3 - enable output - - - - - OUTOVER - [13:12] - read-write - - - NORMAL - 0 - drive output from peripheral signal selected by funcsel - - - INVERT - 1 - drive output from inverse of peripheral signal selected by funcsel - - - LOW - 2 - drive output low - - - HIGH - 3 - drive output high - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table - 31 == NULL - [4:0] - read-write - - - spi0_ss_n - 1 - - - uart1_rx - 2 - - - i2c0_scl - 3 - - - pwm_b_10 - 4 - - - siob_proc_37 - 5 - - - pio0_37 - 6 - - - pio1_37 - 7 - - - pio2_37 - 8 - - - usb_muxing_vbus_detect - 10 - - - null - 31 - - - - - - - GPIO38_STATUS - 0x00000130 - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - INFROMPAD - input signal from pad, before filtering and override are applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - - - GPIO38_CTRL - 0x00000134 - 0x0000001f - - - IRQOVER - [29:28] - read-write - - - NORMAL - 0 - don't invert the interrupt - - - INVERT - 1 - invert the interrupt - - - LOW - 2 - drive interrupt low - - - HIGH - 3 - drive interrupt high - - - - - INOVER - [17:16] - read-write - - - NORMAL - 0 - don't invert the peri input - - - INVERT - 1 - invert the peri input - - - LOW - 2 - drive peri input low - - - HIGH - 3 - drive peri input high - - - - - OEOVER - [15:14] - read-write - - - NORMAL - 0 - drive output enable from peripheral signal selected by funcsel - - - INVERT - 1 - drive output enable from inverse of peripheral signal selected by funcsel - - - DISABLE - 2 - disable output - - - ENABLE - 3 - enable output - - - - - OUTOVER - [13:12] - read-write - - - NORMAL - 0 - drive output from peripheral signal selected by funcsel - - - INVERT - 1 - drive output from inverse of peripheral signal selected by funcsel - - - LOW - 2 - drive output low - - - HIGH - 3 - drive output high - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table - 31 == NULL - [4:0] - read-write - - - spi0_sclk - 1 - - - uart1_cts - 2 - - - i2c1_sda - 3 - - - pwm_a_11 - 4 - - - siob_proc_38 - 5 - - - pio0_38 - 6 - - - pio1_38 - 7 - - - pio2_38 - 8 - - - usb_muxing_vbus_en - 10 - - - uart1_tx - 11 - - - null - 31 - - - - - - - GPIO39_STATUS - 0x00000138 - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - INFROMPAD - input signal from pad, before filtering and override are applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - - - GPIO39_CTRL - 0x0000013c - 0x0000001f - - - IRQOVER - [29:28] - read-write - - - NORMAL - 0 - don't invert the interrupt - - - INVERT - 1 - invert the interrupt - - - LOW - 2 - drive interrupt low - - - HIGH - 3 - drive interrupt high - - - - - INOVER - [17:16] - read-write - - - NORMAL - 0 - don't invert the peri input - - - INVERT - 1 - invert the peri input - - - LOW - 2 - drive peri input low - - - HIGH - 3 - drive peri input high - - - - - OEOVER - [15:14] - read-write - - - NORMAL - 0 - drive output enable from peripheral signal selected by funcsel - - - INVERT - 1 - drive output enable from inverse of peripheral signal selected by funcsel - - - DISABLE - 2 - disable output - - - ENABLE - 3 - enable output - - - - - OUTOVER - [13:12] - read-write - - - NORMAL - 0 - drive output from peripheral signal selected by funcsel - - - INVERT - 1 - drive output from inverse of peripheral signal selected by funcsel - - - LOW - 2 - drive output low - - - HIGH - 3 - drive output high - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table - 31 == NULL - [4:0] - read-write - - - spi0_tx - 1 - - - uart1_rts - 2 - - - i2c1_scl - 3 - - - pwm_b_11 - 4 - - - siob_proc_39 - 5 - - - pio0_39 - 6 - - - pio1_39 - 7 - - - pio2_39 - 8 - - - usb_muxing_overcurr_detect - 10 - - - uart1_rx - 11 - - - null - 31 - - - - - - - GPIO40_STATUS - 0x00000140 - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - INFROMPAD - input signal from pad, before filtering and override are applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - - - GPIO40_CTRL - 0x00000144 - 0x0000001f - - - IRQOVER - [29:28] - read-write - - - NORMAL - 0 - don't invert the interrupt - - - INVERT - 1 - invert the interrupt - - - LOW - 2 - drive interrupt low - - - HIGH - 3 - drive interrupt high - - - - - INOVER - [17:16] - read-write - - - NORMAL - 0 - don't invert the peri input - - - INVERT - 1 - invert the peri input - - - LOW - 2 - drive peri input low - - - HIGH - 3 - drive peri input high - - - - - OEOVER - [15:14] - read-write - - - NORMAL - 0 - drive output enable from peripheral signal selected by funcsel - - - INVERT - 1 - drive output enable from inverse of peripheral signal selected by funcsel - - - DISABLE - 2 - disable output - - - ENABLE - 3 - enable output - - - - - OUTOVER - [13:12] - read-write - - - NORMAL - 0 - drive output from peripheral signal selected by funcsel - - - INVERT - 1 - drive output from inverse of peripheral signal selected by funcsel - - - LOW - 2 - drive output low - - - HIGH - 3 - drive output high - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table - 31 == NULL - [4:0] - read-write - - - spi1_rx - 1 - - - uart1_tx - 2 - - - i2c0_sda - 3 - - - pwm_a_8 - 4 - - - siob_proc_40 - 5 - - - pio0_40 - 6 - - - pio1_40 - 7 - - - pio2_40 - 8 - - - usb_muxing_vbus_detect - 10 - - - null - 31 - - - - - - - GPIO41_STATUS - 0x00000148 - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - INFROMPAD - input signal from pad, before filtering and override are applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - - - GPIO41_CTRL - 0x0000014c - 0x0000001f - - - IRQOVER - [29:28] - read-write - - - NORMAL - 0 - don't invert the interrupt - - - INVERT - 1 - invert the interrupt - - - LOW - 2 - drive interrupt low - - - HIGH - 3 - drive interrupt high - - - - - INOVER - [17:16] - read-write - - - NORMAL - 0 - don't invert the peri input - - - INVERT - 1 - invert the peri input - - - LOW - 2 - drive peri input low - - - HIGH - 3 - drive peri input high - - - - - OEOVER - [15:14] - read-write - - - NORMAL - 0 - drive output enable from peripheral signal selected by funcsel - - - INVERT - 1 - drive output enable from inverse of peripheral signal selected by funcsel - - - DISABLE - 2 - disable output - - - ENABLE - 3 - enable output - - - - - OUTOVER - [13:12] - read-write - - - NORMAL - 0 - drive output from peripheral signal selected by funcsel - - - INVERT - 1 - drive output from inverse of peripheral signal selected by funcsel - - - LOW - 2 - drive output low - - - HIGH - 3 - drive output high - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table - 31 == NULL - [4:0] - read-write - - - spi1_ss_n - 1 - - - uart1_rx - 2 - - - i2c0_scl - 3 - - - pwm_b_8 - 4 - - - siob_proc_41 - 5 - - - pio0_41 - 6 - - - pio1_41 - 7 - - - pio2_41 - 8 - - - usb_muxing_vbus_en - 10 - - - null - 31 - - - - - - - GPIO42_STATUS - 0x00000150 - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - INFROMPAD - input signal from pad, before filtering and override are applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - - - GPIO42_CTRL - 0x00000154 - 0x0000001f - - - IRQOVER - [29:28] - read-write - - - NORMAL - 0 - don't invert the interrupt - - - INVERT - 1 - invert the interrupt - - - LOW - 2 - drive interrupt low - - - HIGH - 3 - drive interrupt high - - - - - INOVER - [17:16] - read-write - - - NORMAL - 0 - don't invert the peri input - - - INVERT - 1 - invert the peri input - - - LOW - 2 - drive peri input low - - - HIGH - 3 - drive peri input high - - - - - OEOVER - [15:14] - read-write - - - NORMAL - 0 - drive output enable from peripheral signal selected by funcsel - - - INVERT - 1 - drive output enable from inverse of peripheral signal selected by funcsel - - - DISABLE - 2 - disable output - - - ENABLE - 3 - enable output - - - - - OUTOVER - [13:12] - read-write - - - NORMAL - 0 - drive output from peripheral signal selected by funcsel - - - INVERT - 1 - drive output from inverse of peripheral signal selected by funcsel - - - LOW - 2 - drive output low - - - HIGH - 3 - drive output high - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table - 31 == NULL - [4:0] - read-write - - - spi1_sclk - 1 - - - uart1_cts - 2 - - - i2c1_sda - 3 - - - pwm_a_9 - 4 - - - siob_proc_42 - 5 - - - pio0_42 - 6 - - - pio1_42 - 7 - - - pio2_42 - 8 - - - usb_muxing_overcurr_detect - 10 - - - uart1_tx - 11 - - - null - 31 - - - - - - - GPIO43_STATUS - 0x00000158 - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - INFROMPAD - input signal from pad, before filtering and override are applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - - - GPIO43_CTRL - 0x0000015c - 0x0000001f - - - IRQOVER - [29:28] - read-write - - - NORMAL - 0 - don't invert the interrupt - - - INVERT - 1 - invert the interrupt - - - LOW - 2 - drive interrupt low - - - HIGH - 3 - drive interrupt high - - - - - INOVER - [17:16] - read-write - - - NORMAL - 0 - don't invert the peri input - - - INVERT - 1 - invert the peri input - - - LOW - 2 - drive peri input low - - - HIGH - 3 - drive peri input high - - - - - OEOVER - [15:14] - read-write - - - NORMAL - 0 - drive output enable from peripheral signal selected by funcsel - - - INVERT - 1 - drive output enable from inverse of peripheral signal selected by funcsel - - - DISABLE - 2 - disable output - - - ENABLE - 3 - enable output - - - - - OUTOVER - [13:12] - read-write - - - NORMAL - 0 - drive output from peripheral signal selected by funcsel - - - INVERT - 1 - drive output from inverse of peripheral signal selected by funcsel - - - LOW - 2 - drive output low - - - HIGH - 3 - drive output high - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table - 31 == NULL - [4:0] - read-write - - - spi1_tx - 1 - - - uart1_rts - 2 - - - i2c1_scl - 3 - - - pwm_b_9 - 4 - - - siob_proc_43 - 5 - - - pio0_43 - 6 - - - pio1_43 - 7 - - - pio2_43 - 8 - - - usb_muxing_vbus_detect - 10 - - - uart1_rx - 11 - - - null - 31 - - - - - - - GPIO44_STATUS - 0x00000160 - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - INFROMPAD - input signal from pad, before filtering and override are applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - - - GPIO44_CTRL - 0x00000164 - 0x0000001f - - - IRQOVER - [29:28] - read-write - - - NORMAL - 0 - don't invert the interrupt - - - INVERT - 1 - invert the interrupt - - - LOW - 2 - drive interrupt low - - - HIGH - 3 - drive interrupt high - - - - - INOVER - [17:16] - read-write - - - NORMAL - 0 - don't invert the peri input - - - INVERT - 1 - invert the peri input - - - LOW - 2 - drive peri input low - - - HIGH - 3 - drive peri input high - - - - - OEOVER - [15:14] - read-write - - - NORMAL - 0 - drive output enable from peripheral signal selected by funcsel - - - INVERT - 1 - drive output enable from inverse of peripheral signal selected by funcsel - - - DISABLE - 2 - disable output - - - ENABLE - 3 - enable output - - - - - OUTOVER - [13:12] - read-write - - - NORMAL - 0 - drive output from peripheral signal selected by funcsel - - - INVERT - 1 - drive output from inverse of peripheral signal selected by funcsel - - - LOW - 2 - drive output low - - - HIGH - 3 - drive output high - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table - 31 == NULL - [4:0] - read-write - - - spi1_rx - 1 - - - uart0_tx - 2 - - - i2c0_sda - 3 - - - pwm_a_10 - 4 - - - siob_proc_44 - 5 - - - pio0_44 - 6 - - - pio1_44 - 7 - - - pio2_44 - 8 - - - usb_muxing_vbus_en - 10 - - - null - 31 - - - - - - - GPIO45_STATUS - 0x00000168 - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - INFROMPAD - input signal from pad, before filtering and override are applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - - - GPIO45_CTRL - 0x0000016c - 0x0000001f - - - IRQOVER - [29:28] - read-write - - - NORMAL - 0 - don't invert the interrupt - - - INVERT - 1 - invert the interrupt - - - LOW - 2 - drive interrupt low - - - HIGH - 3 - drive interrupt high - - - - - INOVER - [17:16] - read-write - - - NORMAL - 0 - don't invert the peri input - - - INVERT - 1 - invert the peri input - - - LOW - 2 - drive peri input low - - - HIGH - 3 - drive peri input high - - - - - OEOVER - [15:14] - read-write - - - NORMAL - 0 - drive output enable from peripheral signal selected by funcsel - - - INVERT - 1 - drive output enable from inverse of peripheral signal selected by funcsel - - - DISABLE - 2 - disable output - - - ENABLE - 3 - enable output - - - - - OUTOVER - [13:12] - read-write - - - NORMAL - 0 - drive output from peripheral signal selected by funcsel - - - INVERT - 1 - drive output from inverse of peripheral signal selected by funcsel - - - LOW - 2 - drive output low - - - HIGH - 3 - drive output high - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table - 31 == NULL - [4:0] - read-write - - - spi1_ss_n - 1 - - - uart0_rx - 2 - - - i2c0_scl - 3 - - - pwm_b_10 - 4 - - - siob_proc_45 - 5 - - - pio0_45 - 6 - - - pio1_45 - 7 - - - pio2_45 - 8 - - - usb_muxing_overcurr_detect - 10 - - - null - 31 - - - - - - - GPIO46_STATUS - 0x00000170 - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - INFROMPAD - input signal from pad, before filtering and override are applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - - - GPIO46_CTRL - 0x00000174 - 0x0000001f - - - IRQOVER - [29:28] - read-write - - - NORMAL - 0 - don't invert the interrupt - - - INVERT - 1 - invert the interrupt - - - LOW - 2 - drive interrupt low - - - HIGH - 3 - drive interrupt high - - - - - INOVER - [17:16] - read-write - - - NORMAL - 0 - don't invert the peri input - - - INVERT - 1 - invert the peri input - - - LOW - 2 - drive peri input low - - - HIGH - 3 - drive peri input high - - - - - OEOVER - [15:14] - read-write - - - NORMAL - 0 - drive output enable from peripheral signal selected by funcsel - - - INVERT - 1 - drive output enable from inverse of peripheral signal selected by funcsel - - - DISABLE - 2 - disable output - - - ENABLE - 3 - enable output - - - - - OUTOVER - [13:12] - read-write - - - NORMAL - 0 - drive output from peripheral signal selected by funcsel - - - INVERT - 1 - drive output from inverse of peripheral signal selected by funcsel - - - LOW - 2 - drive output low - - - HIGH - 3 - drive output high - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table - 31 == NULL - [4:0] - read-write - - - spi1_sclk - 1 - - - uart0_cts - 2 - - - i2c1_sda - 3 - - - pwm_a_11 - 4 - - - siob_proc_46 - 5 - - - pio0_46 - 6 - - - pio1_46 - 7 - - - pio2_46 - 8 - - - usb_muxing_vbus_detect - 10 - - - uart0_tx - 11 - - - null - 31 - - - - - - - GPIO47_STATUS - 0x00000178 - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - INFROMPAD - input signal from pad, before filtering and override are applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - - - GPIO47_CTRL - 0x0000017c - 0x0000001f - - - IRQOVER - [29:28] - read-write - - - NORMAL - 0 - don't invert the interrupt - - - INVERT - 1 - invert the interrupt - - - LOW - 2 - drive interrupt low - - - HIGH - 3 - drive interrupt high - - - - - INOVER - [17:16] - read-write - - - NORMAL - 0 - don't invert the peri input - - - INVERT - 1 - invert the peri input - - - LOW - 2 - drive peri input low - - - HIGH - 3 - drive peri input high - - - - - OEOVER - [15:14] - read-write - - - NORMAL - 0 - drive output enable from peripheral signal selected by funcsel - - - INVERT - 1 - drive output enable from inverse of peripheral signal selected by funcsel - - - DISABLE - 2 - disable output - - - ENABLE - 3 - enable output - - - - - OUTOVER - [13:12] - read-write - - - NORMAL - 0 - drive output from peripheral signal selected by funcsel - - - INVERT - 1 - drive output from inverse of peripheral signal selected by funcsel - - - LOW - 2 - drive output low - - - HIGH - 3 - drive output high - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table - 31 == NULL - [4:0] - read-write - - - spi1_tx - 1 - - - uart0_rts - 2 - - - i2c1_scl - 3 - - - pwm_b_11 - 4 - - - siob_proc_47 - 5 - - - pio0_47 - 6 - - - pio1_47 - 7 - - - pio2_47 - 8 - - - xip_ss_n_1 - 9 - - - usb_muxing_vbus_en - 10 - - - uart0_rx - 11 - - - null - 31 - - - - - - - IRQSUMMARY_PROC0_SECURE0 - 0x00000200 - 0x00000000 - - - GPIO31 - [31:31] - read-only - - - GPIO30 - [30:30] - read-only - - - GPIO29 - [29:29] - read-only - - - GPIO28 - [28:28] - read-only - - - GPIO27 - [27:27] - read-only - - - GPIO26 - [26:26] - read-only - - - GPIO25 - [25:25] - read-only - - - GPIO24 - [24:24] - read-only - - - GPIO23 - [23:23] - read-only - - - GPIO22 - [22:22] - read-only - - - GPIO21 - [21:21] - read-only - - - GPIO20 - [20:20] - read-only - - - GPIO19 - [19:19] - read-only - - - GPIO18 - [18:18] - read-only - - - GPIO17 - [17:17] - read-only - - - GPIO16 - [16:16] - read-only - - - GPIO15 - [15:15] - read-only - - - GPIO14 - [14:14] - read-only - - - GPIO13 - [13:13] - read-only - - - GPIO12 - [12:12] - read-only - - - GPIO11 - [11:11] - read-only - - - GPIO10 - [10:10] - read-only - - - GPIO9 - [9:9] - read-only - - - GPIO8 - [8:8] - read-only - - - GPIO7 - [7:7] - read-only - - - GPIO6 - [6:6] - read-only - - - GPIO5 - [5:5] - read-only - - - GPIO4 - [4:4] - read-only - - - GPIO3 - [3:3] - read-only - - - GPIO2 - [2:2] - read-only - - - GPIO1 - [1:1] - read-only - - - GPIO0 - [0:0] - read-only - - - - - IRQSUMMARY_PROC0_SECURE1 - 0x00000204 - 0x00000000 - - - GPIO47 - [15:15] - read-only - - - GPIO46 - [14:14] - read-only - - - GPIO45 - [13:13] - read-only - - - GPIO44 - [12:12] - read-only - - - GPIO43 - [11:11] - read-only - - - GPIO42 - [10:10] - read-only - - - GPIO41 - [9:9] - read-only - - - GPIO40 - [8:8] - read-only - - - GPIO39 - [7:7] - read-only - - - GPIO38 - [6:6] - read-only - - - GPIO37 - [5:5] - read-only - - - GPIO36 - [4:4] - read-only - - - GPIO35 - [3:3] - read-only - - - GPIO34 - [2:2] - read-only - - - GPIO33 - [1:1] - read-only - - - GPIO32 - [0:0] - read-only - - - - - IRQSUMMARY_PROC0_NONSECURE0 - 0x00000208 - 0x00000000 - - - GPIO31 - [31:31] - read-only - - - GPIO30 - [30:30] - read-only - - - GPIO29 - [29:29] - read-only - - - GPIO28 - [28:28] - read-only - - - GPIO27 - [27:27] - read-only - - - GPIO26 - [26:26] - read-only - - - GPIO25 - [25:25] - read-only - - - GPIO24 - [24:24] - read-only - - - GPIO23 - [23:23] - read-only - - - GPIO22 - [22:22] - read-only - - - GPIO21 - [21:21] - read-only - - - GPIO20 - [20:20] - read-only - - - GPIO19 - [19:19] - read-only - - - GPIO18 - [18:18] - read-only - - - GPIO17 - [17:17] - read-only - - - GPIO16 - [16:16] - read-only - - - GPIO15 - [15:15] - read-only - - - GPIO14 - [14:14] - read-only - - - GPIO13 - [13:13] - read-only - - - GPIO12 - [12:12] - read-only - - - GPIO11 - [11:11] - read-only - - - GPIO10 - [10:10] - read-only - - - GPIO9 - [9:9] - read-only - - - GPIO8 - [8:8] - read-only - - - GPIO7 - [7:7] - read-only - - - GPIO6 - [6:6] - read-only - - - GPIO5 - [5:5] - read-only - - - GPIO4 - [4:4] - read-only - - - GPIO3 - [3:3] - read-only - - - GPIO2 - [2:2] - read-only - - - GPIO1 - [1:1] - read-only - - - GPIO0 - [0:0] - read-only - - - - - IRQSUMMARY_PROC0_NONSECURE1 - 0x0000020c - 0x00000000 - - - GPIO47 - [15:15] - read-only - - - GPIO46 - [14:14] - read-only - - - GPIO45 - [13:13] - read-only - - - GPIO44 - [12:12] - read-only - - - GPIO43 - [11:11] - read-only - - - GPIO42 - [10:10] - read-only - - - GPIO41 - [9:9] - read-only - - - GPIO40 - [8:8] - read-only - - - GPIO39 - [7:7] - read-only - - - GPIO38 - [6:6] - read-only - - - GPIO37 - [5:5] - read-only - - - GPIO36 - [4:4] - read-only - - - GPIO35 - [3:3] - read-only - - - GPIO34 - [2:2] - read-only - - - GPIO33 - [1:1] - read-only - - - GPIO32 - [0:0] - read-only - - - - - IRQSUMMARY_PROC1_SECURE0 - 0x00000210 - 0x00000000 - - - GPIO31 - [31:31] - read-only - - - GPIO30 - [30:30] - read-only - - - GPIO29 - [29:29] - read-only - - - GPIO28 - [28:28] - read-only - - - GPIO27 - [27:27] - read-only - - - GPIO26 - [26:26] - read-only - - - GPIO25 - [25:25] - read-only - - - GPIO24 - [24:24] - read-only - - - GPIO23 - [23:23] - read-only - - - GPIO22 - [22:22] - read-only - - - GPIO21 - [21:21] - read-only - - - GPIO20 - [20:20] - read-only - - - GPIO19 - [19:19] - read-only - - - GPIO18 - [18:18] - read-only - - - GPIO17 - [17:17] - read-only - - - GPIO16 - [16:16] - read-only - - - GPIO15 - [15:15] - read-only - - - GPIO14 - [14:14] - read-only - - - GPIO13 - [13:13] - read-only - - - GPIO12 - [12:12] - read-only - - - GPIO11 - [11:11] - read-only - - - GPIO10 - [10:10] - read-only - - - GPIO9 - [9:9] - read-only - - - GPIO8 - [8:8] - read-only - - - GPIO7 - [7:7] - read-only - - - GPIO6 - [6:6] - read-only - - - GPIO5 - [5:5] - read-only - - - GPIO4 - [4:4] - read-only - - - GPIO3 - [3:3] - read-only - - - GPIO2 - [2:2] - read-only - - - GPIO1 - [1:1] - read-only - - - GPIO0 - [0:0] - read-only - - - - - IRQSUMMARY_PROC1_SECURE1 - 0x00000214 - 0x00000000 - - - GPIO47 - [15:15] - read-only - - - GPIO46 - [14:14] - read-only - - - GPIO45 - [13:13] - read-only - - - GPIO44 - [12:12] - read-only - - - GPIO43 - [11:11] - read-only - - - GPIO42 - [10:10] - read-only - - - GPIO41 - [9:9] - read-only - - - GPIO40 - [8:8] - read-only - - - GPIO39 - [7:7] - read-only - - - GPIO38 - [6:6] - read-only - - - GPIO37 - [5:5] - read-only - - - GPIO36 - [4:4] - read-only - - - GPIO35 - [3:3] - read-only - - - GPIO34 - [2:2] - read-only - - - GPIO33 - [1:1] - read-only - - - GPIO32 - [0:0] - read-only - - - - - IRQSUMMARY_PROC1_NONSECURE0 - 0x00000218 - 0x00000000 - - - GPIO31 - [31:31] - read-only - - - GPIO30 - [30:30] - read-only - - - GPIO29 - [29:29] - read-only - - - GPIO28 - [28:28] - read-only - - - GPIO27 - [27:27] - read-only - - - GPIO26 - [26:26] - read-only - - - GPIO25 - [25:25] - read-only - - - GPIO24 - [24:24] - read-only - - - GPIO23 - [23:23] - read-only - - - GPIO22 - [22:22] - read-only - - - GPIO21 - [21:21] - read-only - - - GPIO20 - [20:20] - read-only - - - GPIO19 - [19:19] - read-only - - - GPIO18 - [18:18] - read-only - - - GPIO17 - [17:17] - read-only - - - GPIO16 - [16:16] - read-only - - - GPIO15 - [15:15] - read-only - - - GPIO14 - [14:14] - read-only - - - GPIO13 - [13:13] - read-only - - - GPIO12 - [12:12] - read-only - - - GPIO11 - [11:11] - read-only - - - GPIO10 - [10:10] - read-only - - - GPIO9 - [9:9] - read-only - - - GPIO8 - [8:8] - read-only - - - GPIO7 - [7:7] - read-only - - - GPIO6 - [6:6] - read-only - - - GPIO5 - [5:5] - read-only - - - GPIO4 - [4:4] - read-only - - - GPIO3 - [3:3] - read-only - - - GPIO2 - [2:2] - read-only - - - GPIO1 - [1:1] - read-only - - - GPIO0 - [0:0] - read-only - - - - - IRQSUMMARY_PROC1_NONSECURE1 - 0x0000021c - 0x00000000 - - - GPIO47 - [15:15] - read-only - - - GPIO46 - [14:14] - read-only - - - GPIO45 - [13:13] - read-only - - - GPIO44 - [12:12] - read-only - - - GPIO43 - [11:11] - read-only - - - GPIO42 - [10:10] - read-only - - - GPIO41 - [9:9] - read-only - - - GPIO40 - [8:8] - read-only - - - GPIO39 - [7:7] - read-only - - - GPIO38 - [6:6] - read-only - - - GPIO37 - [5:5] - read-only - - - GPIO36 - [4:4] - read-only - - - GPIO35 - [3:3] - read-only - - - GPIO34 - [2:2] - read-only - - - GPIO33 - [1:1] - read-only - - - GPIO32 - [0:0] - read-only - - - - - IRQSUMMARY_DORMANT_WAKE_SECURE0 - 0x00000220 - 0x00000000 - - - GPIO31 - [31:31] - read-only - - - GPIO30 - [30:30] - read-only - - - GPIO29 - [29:29] - read-only - - - GPIO28 - [28:28] - read-only - - - GPIO27 - [27:27] - read-only - - - GPIO26 - [26:26] - read-only - - - GPIO25 - [25:25] - read-only - - - GPIO24 - [24:24] - read-only - - - GPIO23 - [23:23] - read-only - - - GPIO22 - [22:22] - read-only - - - GPIO21 - [21:21] - read-only - - - GPIO20 - [20:20] - read-only - - - GPIO19 - [19:19] - read-only - - - GPIO18 - [18:18] - read-only - - - GPIO17 - [17:17] - read-only - - - GPIO16 - [16:16] - read-only - - - GPIO15 - [15:15] - read-only - - - GPIO14 - [14:14] - read-only - - - GPIO13 - [13:13] - read-only - - - GPIO12 - [12:12] - read-only - - - GPIO11 - [11:11] - read-only - - - GPIO10 - [10:10] - read-only - - - GPIO9 - [9:9] - read-only - - - GPIO8 - [8:8] - read-only - - - GPIO7 - [7:7] - read-only - - - GPIO6 - [6:6] - read-only - - - GPIO5 - [5:5] - read-only - - - GPIO4 - [4:4] - read-only - - - GPIO3 - [3:3] - read-only - - - GPIO2 - [2:2] - read-only - - - GPIO1 - [1:1] - read-only - - - GPIO0 - [0:0] - read-only - - - - - IRQSUMMARY_DORMANT_WAKE_SECURE1 - 0x00000224 - 0x00000000 - - - GPIO47 - [15:15] - read-only - - - GPIO46 - [14:14] - read-only - - - GPIO45 - [13:13] - read-only - - - GPIO44 - [12:12] - read-only - - - GPIO43 - [11:11] - read-only - - - GPIO42 - [10:10] - read-only - - - GPIO41 - [9:9] - read-only - - - GPIO40 - [8:8] - read-only - - - GPIO39 - [7:7] - read-only - - - GPIO38 - [6:6] - read-only - - - GPIO37 - [5:5] - read-only - - - GPIO36 - [4:4] - read-only - - - GPIO35 - [3:3] - read-only - - - GPIO34 - [2:2] - read-only - - - GPIO33 - [1:1] - read-only - - - GPIO32 - [0:0] - read-only - - - - - IRQSUMMARY_DORMANT_WAKE_NONSECURE0 - 0x00000228 - 0x00000000 - - - GPIO31 - [31:31] - read-only - - - GPIO30 - [30:30] - read-only - - - GPIO29 - [29:29] - read-only - - - GPIO28 - [28:28] - read-only - - - GPIO27 - [27:27] - read-only - - - GPIO26 - [26:26] - read-only - - - GPIO25 - [25:25] - read-only - - - GPIO24 - [24:24] - read-only - - - GPIO23 - [23:23] - read-only - - - GPIO22 - [22:22] - read-only - - - GPIO21 - [21:21] - read-only - - - GPIO20 - [20:20] - read-only - - - GPIO19 - [19:19] - read-only - - - GPIO18 - [18:18] - read-only - - - GPIO17 - [17:17] - read-only - - - GPIO16 - [16:16] - read-only - - - GPIO15 - [15:15] - read-only - - - GPIO14 - [14:14] - read-only - - - GPIO13 - [13:13] - read-only - - - GPIO12 - [12:12] - read-only - - - GPIO11 - [11:11] - read-only - - - GPIO10 - [10:10] - read-only - - - GPIO9 - [9:9] - read-only - - - GPIO8 - [8:8] - read-only - - - GPIO7 - [7:7] - read-only - - - GPIO6 - [6:6] - read-only - - - GPIO5 - [5:5] - read-only - - - GPIO4 - [4:4] - read-only - - - GPIO3 - [3:3] - read-only - - - GPIO2 - [2:2] - read-only - - - GPIO1 - [1:1] - read-only - - - GPIO0 - [0:0] - read-only - - - - - IRQSUMMARY_DORMANT_WAKE_NONSECURE1 - 0x0000022c - 0x00000000 - - - GPIO47 - [15:15] - read-only - - - GPIO46 - [14:14] - read-only - - - GPIO45 - [13:13] - read-only - - - GPIO44 - [12:12] - read-only - - - GPIO43 - [11:11] - read-only - - - GPIO42 - [10:10] - read-only - - - GPIO41 - [9:9] - read-only - - - GPIO40 - [8:8] - read-only - - - GPIO39 - [7:7] - read-only - - - GPIO38 - [6:6] - read-only - - - GPIO37 - [5:5] - read-only - - - GPIO36 - [4:4] - read-only - - - GPIO35 - [3:3] - read-only - - - GPIO34 - [2:2] - read-only - - - GPIO33 - [1:1] - read-only - - - GPIO32 - [0:0] - read-only - - - - - INTR0 - 0x00000230 - Raw Interrupts - 0x00000000 - - - GPIO7_EDGE_HIGH - [31:31] - read-write - oneToClear - - - GPIO7_EDGE_LOW - [30:30] - read-write - oneToClear - - - GPIO7_LEVEL_HIGH - [29:29] - read-only - - - GPIO7_LEVEL_LOW - [28:28] - read-only - - - GPIO6_EDGE_HIGH - [27:27] - read-write - oneToClear - - - GPIO6_EDGE_LOW - [26:26] - read-write - oneToClear - - - GPIO6_LEVEL_HIGH - [25:25] - read-only - - - GPIO6_LEVEL_LOW - [24:24] - read-only - - - GPIO5_EDGE_HIGH - [23:23] - read-write - oneToClear - - - GPIO5_EDGE_LOW - [22:22] - read-write - oneToClear - - - GPIO5_LEVEL_HIGH - [21:21] - read-only - - - GPIO5_LEVEL_LOW - [20:20] - read-only - - - GPIO4_EDGE_HIGH - [19:19] - read-write - oneToClear - - - GPIO4_EDGE_LOW - [18:18] - read-write - oneToClear - - - GPIO4_LEVEL_HIGH - [17:17] - read-only - - - GPIO4_LEVEL_LOW - [16:16] - read-only - - - GPIO3_EDGE_HIGH - [15:15] - read-write - oneToClear - - - GPIO3_EDGE_LOW - [14:14] - read-write - oneToClear - - - GPIO3_LEVEL_HIGH - [13:13] - read-only - - - GPIO3_LEVEL_LOW - [12:12] - read-only - - - GPIO2_EDGE_HIGH - [11:11] - read-write - oneToClear - - - GPIO2_EDGE_LOW - [10:10] - read-write - oneToClear - - - GPIO2_LEVEL_HIGH - [9:9] - read-only - - - GPIO2_LEVEL_LOW - [8:8] - read-only - - - GPIO1_EDGE_HIGH - [7:7] - read-write - oneToClear - - - GPIO1_EDGE_LOW - [6:6] - read-write - oneToClear - - - GPIO1_LEVEL_HIGH - [5:5] - read-only - - - GPIO1_LEVEL_LOW - [4:4] - read-only - - - GPIO0_EDGE_HIGH - [3:3] - read-write - oneToClear - - - GPIO0_EDGE_LOW - [2:2] - read-write - oneToClear - - - GPIO0_LEVEL_HIGH - [1:1] - read-only - - - GPIO0_LEVEL_LOW - [0:0] - read-only - - - - - INTR1 - 0x00000234 - Raw Interrupts - 0x00000000 - - - GPIO15_EDGE_HIGH - [31:31] - read-write - oneToClear - - - GPIO15_EDGE_LOW - [30:30] - read-write - oneToClear - - - GPIO15_LEVEL_HIGH - [29:29] - read-only - - - GPIO15_LEVEL_LOW - [28:28] - read-only - - - GPIO14_EDGE_HIGH - [27:27] - read-write - oneToClear - - - GPIO14_EDGE_LOW - [26:26] - read-write - oneToClear - - - GPIO14_LEVEL_HIGH - [25:25] - read-only - - - GPIO14_LEVEL_LOW - [24:24] - read-only - - - GPIO13_EDGE_HIGH - [23:23] - read-write - oneToClear - - - GPIO13_EDGE_LOW - [22:22] - read-write - oneToClear - - - GPIO13_LEVEL_HIGH - [21:21] - read-only - - - GPIO13_LEVEL_LOW - [20:20] - read-only - - - GPIO12_EDGE_HIGH - [19:19] - read-write - oneToClear - - - GPIO12_EDGE_LOW - [18:18] - read-write - oneToClear - - - GPIO12_LEVEL_HIGH - [17:17] - read-only - - - GPIO12_LEVEL_LOW - [16:16] - read-only - - - GPIO11_EDGE_HIGH - [15:15] - read-write - oneToClear - - - GPIO11_EDGE_LOW - [14:14] - read-write - oneToClear - - - GPIO11_LEVEL_HIGH - [13:13] - read-only - - - GPIO11_LEVEL_LOW - [12:12] - read-only - - - GPIO10_EDGE_HIGH - [11:11] - read-write - oneToClear - - - GPIO10_EDGE_LOW - [10:10] - read-write - oneToClear - - - GPIO10_LEVEL_HIGH - [9:9] - read-only - - - GPIO10_LEVEL_LOW - [8:8] - read-only - - - GPIO9_EDGE_HIGH - [7:7] - read-write - oneToClear - - - GPIO9_EDGE_LOW - [6:6] - read-write - oneToClear - - - GPIO9_LEVEL_HIGH - [5:5] - read-only - - - GPIO9_LEVEL_LOW - [4:4] - read-only - - - GPIO8_EDGE_HIGH - [3:3] - read-write - oneToClear - - - GPIO8_EDGE_LOW - [2:2] - read-write - oneToClear - - - GPIO8_LEVEL_HIGH - [1:1] - read-only - - - GPIO8_LEVEL_LOW - [0:0] - read-only - - - - - INTR2 - 0x00000238 - Raw Interrupts - 0x00000000 - - - GPIO23_EDGE_HIGH - [31:31] - read-write - oneToClear - - - GPIO23_EDGE_LOW - [30:30] - read-write - oneToClear - - - GPIO23_LEVEL_HIGH - [29:29] - read-only - - - GPIO23_LEVEL_LOW - [28:28] - read-only - - - GPIO22_EDGE_HIGH - [27:27] - read-write - oneToClear - - - GPIO22_EDGE_LOW - [26:26] - read-write - oneToClear - - - GPIO22_LEVEL_HIGH - [25:25] - read-only - - - GPIO22_LEVEL_LOW - [24:24] - read-only - - - GPIO21_EDGE_HIGH - [23:23] - read-write - oneToClear - - - GPIO21_EDGE_LOW - [22:22] - read-write - oneToClear - - - GPIO21_LEVEL_HIGH - [21:21] - read-only - - - GPIO21_LEVEL_LOW - [20:20] - read-only - - - GPIO20_EDGE_HIGH - [19:19] - read-write - oneToClear - - - GPIO20_EDGE_LOW - [18:18] - read-write - oneToClear - - - GPIO20_LEVEL_HIGH - [17:17] - read-only - - - GPIO20_LEVEL_LOW - [16:16] - read-only - - - GPIO19_EDGE_HIGH - [15:15] - read-write - oneToClear - - - GPIO19_EDGE_LOW - [14:14] - read-write - oneToClear - - - GPIO19_LEVEL_HIGH - [13:13] - read-only - - - GPIO19_LEVEL_LOW - [12:12] - read-only - - - GPIO18_EDGE_HIGH - [11:11] - read-write - oneToClear - - - GPIO18_EDGE_LOW - [10:10] - read-write - oneToClear - - - GPIO18_LEVEL_HIGH - [9:9] - read-only - - - GPIO18_LEVEL_LOW - [8:8] - read-only - - - GPIO17_EDGE_HIGH - [7:7] - read-write - oneToClear - - - GPIO17_EDGE_LOW - [6:6] - read-write - oneToClear - - - GPIO17_LEVEL_HIGH - [5:5] - read-only - - - GPIO17_LEVEL_LOW - [4:4] - read-only - - - GPIO16_EDGE_HIGH - [3:3] - read-write - oneToClear - - - GPIO16_EDGE_LOW - [2:2] - read-write - oneToClear - - - GPIO16_LEVEL_HIGH - [1:1] - read-only - - - GPIO16_LEVEL_LOW - [0:0] - read-only - - - - - INTR3 - 0x0000023c - Raw Interrupts - 0x00000000 - - - GPIO31_EDGE_HIGH - [31:31] - read-write - oneToClear - - - GPIO31_EDGE_LOW - [30:30] - read-write - oneToClear - - - GPIO31_LEVEL_HIGH - [29:29] - read-only - - - GPIO31_LEVEL_LOW - [28:28] - read-only - - - GPIO30_EDGE_HIGH - [27:27] - read-write - oneToClear - - - GPIO30_EDGE_LOW - [26:26] - read-write - oneToClear - - - GPIO30_LEVEL_HIGH - [25:25] - read-only - - - GPIO30_LEVEL_LOW - [24:24] - read-only - - - GPIO29_EDGE_HIGH - [23:23] - read-write - oneToClear - - - GPIO29_EDGE_LOW - [22:22] - read-write - oneToClear - - - GPIO29_LEVEL_HIGH - [21:21] - read-only - - - GPIO29_LEVEL_LOW - [20:20] - read-only - - - GPIO28_EDGE_HIGH - [19:19] - read-write - oneToClear - - - GPIO28_EDGE_LOW - [18:18] - read-write - oneToClear - - - GPIO28_LEVEL_HIGH - [17:17] - read-only - - - GPIO28_LEVEL_LOW - [16:16] - read-only - - - GPIO27_EDGE_HIGH - [15:15] - read-write - oneToClear - - - GPIO27_EDGE_LOW - [14:14] - read-write - oneToClear - - - GPIO27_LEVEL_HIGH - [13:13] - read-only - - - GPIO27_LEVEL_LOW - [12:12] - read-only - - - GPIO26_EDGE_HIGH - [11:11] - read-write - oneToClear - - - GPIO26_EDGE_LOW - [10:10] - read-write - oneToClear - - - GPIO26_LEVEL_HIGH - [9:9] - read-only - - - GPIO26_LEVEL_LOW - [8:8] - read-only - - - GPIO25_EDGE_HIGH - [7:7] - read-write - oneToClear - - - GPIO25_EDGE_LOW - [6:6] - read-write - oneToClear - - - GPIO25_LEVEL_HIGH - [5:5] - read-only - - - GPIO25_LEVEL_LOW - [4:4] - read-only - - - GPIO24_EDGE_HIGH - [3:3] - read-write - oneToClear - - - GPIO24_EDGE_LOW - [2:2] - read-write - oneToClear - - - GPIO24_LEVEL_HIGH - [1:1] - read-only - - - GPIO24_LEVEL_LOW - [0:0] - read-only - - - - - INTR4 - 0x00000240 - Raw Interrupts - 0x00000000 - - - GPIO39_EDGE_HIGH - [31:31] - read-write - oneToClear - - - GPIO39_EDGE_LOW - [30:30] - read-write - oneToClear - - - GPIO39_LEVEL_HIGH - [29:29] - read-only - - - GPIO39_LEVEL_LOW - [28:28] - read-only - - - GPIO38_EDGE_HIGH - [27:27] - read-write - oneToClear - - - GPIO38_EDGE_LOW - [26:26] - read-write - oneToClear - - - GPIO38_LEVEL_HIGH - [25:25] - read-only - - - GPIO38_LEVEL_LOW - [24:24] - read-only - - - GPIO37_EDGE_HIGH - [23:23] - read-write - oneToClear - - - GPIO37_EDGE_LOW - [22:22] - read-write - oneToClear - - - GPIO37_LEVEL_HIGH - [21:21] - read-only - - - GPIO37_LEVEL_LOW - [20:20] - read-only - - - GPIO36_EDGE_HIGH - [19:19] - read-write - oneToClear - - - GPIO36_EDGE_LOW - [18:18] - read-write - oneToClear - - - GPIO36_LEVEL_HIGH - [17:17] - read-only - - - GPIO36_LEVEL_LOW - [16:16] - read-only - - - GPIO35_EDGE_HIGH - [15:15] - read-write - oneToClear - - - GPIO35_EDGE_LOW - [14:14] - read-write - oneToClear - - - GPIO35_LEVEL_HIGH - [13:13] - read-only - - - GPIO35_LEVEL_LOW - [12:12] - read-only - - - GPIO34_EDGE_HIGH - [11:11] - read-write - oneToClear - - - GPIO34_EDGE_LOW - [10:10] - read-write - oneToClear - - - GPIO34_LEVEL_HIGH - [9:9] - read-only - - - GPIO34_LEVEL_LOW - [8:8] - read-only - - - GPIO33_EDGE_HIGH - [7:7] - read-write - oneToClear - - - GPIO33_EDGE_LOW - [6:6] - read-write - oneToClear - - - GPIO33_LEVEL_HIGH - [5:5] - read-only - - - GPIO33_LEVEL_LOW - [4:4] - read-only - - - GPIO32_EDGE_HIGH - [3:3] - read-write - oneToClear - - - GPIO32_EDGE_LOW - [2:2] - read-write - oneToClear - - - GPIO32_LEVEL_HIGH - [1:1] - read-only - - - GPIO32_LEVEL_LOW - [0:0] - read-only - - - - - INTR5 - 0x00000244 - Raw Interrupts - 0x00000000 - - - GPIO47_EDGE_HIGH - [31:31] - read-write - oneToClear - - - GPIO47_EDGE_LOW - [30:30] - read-write - oneToClear - - - GPIO47_LEVEL_HIGH - [29:29] - read-only - - - GPIO47_LEVEL_LOW - [28:28] - read-only - - - GPIO46_EDGE_HIGH - [27:27] - read-write - oneToClear - - - GPIO46_EDGE_LOW - [26:26] - read-write - oneToClear - - - GPIO46_LEVEL_HIGH - [25:25] - read-only - - - GPIO46_LEVEL_LOW - [24:24] - read-only - - - GPIO45_EDGE_HIGH - [23:23] - read-write - oneToClear - - - GPIO45_EDGE_LOW - [22:22] - read-write - oneToClear - - - GPIO45_LEVEL_HIGH - [21:21] - read-only - - - GPIO45_LEVEL_LOW - [20:20] - read-only - - - GPIO44_EDGE_HIGH - [19:19] - read-write - oneToClear - - - GPIO44_EDGE_LOW - [18:18] - read-write - oneToClear - - - GPIO44_LEVEL_HIGH - [17:17] - read-only - - - GPIO44_LEVEL_LOW - [16:16] - read-only - - - GPIO43_EDGE_HIGH - [15:15] - read-write - oneToClear - - - GPIO43_EDGE_LOW - [14:14] - read-write - oneToClear - - - GPIO43_LEVEL_HIGH - [13:13] - read-only - - - GPIO43_LEVEL_LOW - [12:12] - read-only - - - GPIO42_EDGE_HIGH - [11:11] - read-write - oneToClear - - - GPIO42_EDGE_LOW - [10:10] - read-write - oneToClear - - - GPIO42_LEVEL_HIGH - [9:9] - read-only - - - GPIO42_LEVEL_LOW - [8:8] - read-only - - - GPIO41_EDGE_HIGH - [7:7] - read-write - oneToClear - - - GPIO41_EDGE_LOW - [6:6] - read-write - oneToClear - - - GPIO41_LEVEL_HIGH - [5:5] - read-only - - - GPIO41_LEVEL_LOW - [4:4] - read-only - - - GPIO40_EDGE_HIGH - [3:3] - read-write - oneToClear - - - GPIO40_EDGE_LOW - [2:2] - read-write - oneToClear - - - GPIO40_LEVEL_HIGH - [1:1] - read-only - - - GPIO40_LEVEL_LOW - [0:0] - read-only - - - - - PROC0_INTE0 - 0x00000248 - Interrupt Enable for proc0 - 0x00000000 - - - GPIO7_EDGE_HIGH - [31:31] - read-write - - - GPIO7_EDGE_LOW - [30:30] - read-write - - - GPIO7_LEVEL_HIGH - [29:29] - read-write - - - GPIO7_LEVEL_LOW - [28:28] - read-write - - - GPIO6_EDGE_HIGH - [27:27] - read-write - - - GPIO6_EDGE_LOW - [26:26] - read-write - - - GPIO6_LEVEL_HIGH - [25:25] - read-write - - - GPIO6_LEVEL_LOW - [24:24] - read-write - - - GPIO5_EDGE_HIGH - [23:23] - read-write - - - GPIO5_EDGE_LOW - [22:22] - read-write - - - GPIO5_LEVEL_HIGH - [21:21] - read-write - - - GPIO5_LEVEL_LOW - [20:20] - read-write - - - GPIO4_EDGE_HIGH - [19:19] - read-write - - - GPIO4_EDGE_LOW - [18:18] - read-write - - - GPIO4_LEVEL_HIGH - [17:17] - read-write - - - GPIO4_LEVEL_LOW - [16:16] - read-write - - - GPIO3_EDGE_HIGH - [15:15] - read-write - - - GPIO3_EDGE_LOW - [14:14] - read-write - - - GPIO3_LEVEL_HIGH - [13:13] - read-write - - - GPIO3_LEVEL_LOW - [12:12] - read-write - - - GPIO2_EDGE_HIGH - [11:11] - read-write - - - GPIO2_EDGE_LOW - [10:10] - read-write - - - GPIO2_LEVEL_HIGH - [9:9] - read-write - - - GPIO2_LEVEL_LOW - [8:8] - read-write - - - GPIO1_EDGE_HIGH - [7:7] - read-write - - - GPIO1_EDGE_LOW - [6:6] - read-write - - - GPIO1_LEVEL_HIGH - [5:5] - read-write - - - GPIO1_LEVEL_LOW - [4:4] - read-write - - - GPIO0_EDGE_HIGH - [3:3] - read-write - - - GPIO0_EDGE_LOW - [2:2] - read-write - - - GPIO0_LEVEL_HIGH - [1:1] - read-write - - - GPIO0_LEVEL_LOW - [0:0] - read-write - - - - - PROC0_INTE1 - 0x0000024c - Interrupt Enable for proc0 - 0x00000000 - - - GPIO15_EDGE_HIGH - [31:31] - read-write - - - GPIO15_EDGE_LOW - [30:30] - read-write - - - GPIO15_LEVEL_HIGH - [29:29] - read-write - - - GPIO15_LEVEL_LOW - [28:28] - read-write - - - GPIO14_EDGE_HIGH - [27:27] - read-write - - - GPIO14_EDGE_LOW - [26:26] - read-write - - - GPIO14_LEVEL_HIGH - [25:25] - read-write - - - GPIO14_LEVEL_LOW - [24:24] - read-write - - - GPIO13_EDGE_HIGH - [23:23] - read-write - - - GPIO13_EDGE_LOW - [22:22] - read-write - - - GPIO13_LEVEL_HIGH - [21:21] - read-write - - - GPIO13_LEVEL_LOW - [20:20] - read-write - - - GPIO12_EDGE_HIGH - [19:19] - read-write - - - GPIO12_EDGE_LOW - [18:18] - read-write - - - GPIO12_LEVEL_HIGH - [17:17] - read-write - - - GPIO12_LEVEL_LOW - [16:16] - read-write - - - GPIO11_EDGE_HIGH - [15:15] - read-write - - - GPIO11_EDGE_LOW - [14:14] - read-write - - - GPIO11_LEVEL_HIGH - [13:13] - read-write - - - GPIO11_LEVEL_LOW - [12:12] - read-write - - - GPIO10_EDGE_HIGH - [11:11] - read-write - - - GPIO10_EDGE_LOW - [10:10] - read-write - - - GPIO10_LEVEL_HIGH - [9:9] - read-write - - - GPIO10_LEVEL_LOW - [8:8] - read-write - - - GPIO9_EDGE_HIGH - [7:7] - read-write - - - GPIO9_EDGE_LOW - [6:6] - read-write - - - GPIO9_LEVEL_HIGH - [5:5] - read-write - - - GPIO9_LEVEL_LOW - [4:4] - read-write - - - GPIO8_EDGE_HIGH - [3:3] - read-write - - - GPIO8_EDGE_LOW - [2:2] - read-write - - - GPIO8_LEVEL_HIGH - [1:1] - read-write - - - GPIO8_LEVEL_LOW - [0:0] - read-write - - - - - PROC0_INTE2 - 0x00000250 - Interrupt Enable for proc0 - 0x00000000 - - - GPIO23_EDGE_HIGH - [31:31] - read-write - - - GPIO23_EDGE_LOW - [30:30] - read-write - - - GPIO23_LEVEL_HIGH - [29:29] - read-write - - - GPIO23_LEVEL_LOW - [28:28] - read-write - - - GPIO22_EDGE_HIGH - [27:27] - read-write - - - GPIO22_EDGE_LOW - [26:26] - read-write - - - GPIO22_LEVEL_HIGH - [25:25] - read-write - - - GPIO22_LEVEL_LOW - [24:24] - read-write - - - GPIO21_EDGE_HIGH - [23:23] - read-write - - - GPIO21_EDGE_LOW - [22:22] - read-write - - - GPIO21_LEVEL_HIGH - [21:21] - read-write - - - GPIO21_LEVEL_LOW - [20:20] - read-write - - - GPIO20_EDGE_HIGH - [19:19] - read-write - - - GPIO20_EDGE_LOW - [18:18] - read-write - - - GPIO20_LEVEL_HIGH - [17:17] - read-write - - - GPIO20_LEVEL_LOW - [16:16] - read-write - - - GPIO19_EDGE_HIGH - [15:15] - read-write - - - GPIO19_EDGE_LOW - [14:14] - read-write - - - GPIO19_LEVEL_HIGH - [13:13] - read-write - - - GPIO19_LEVEL_LOW - [12:12] - read-write - - - GPIO18_EDGE_HIGH - [11:11] - read-write - - - GPIO18_EDGE_LOW - [10:10] - read-write - - - GPIO18_LEVEL_HIGH - [9:9] - read-write - - - GPIO18_LEVEL_LOW - [8:8] - read-write - - - GPIO17_EDGE_HIGH - [7:7] - read-write - - - GPIO17_EDGE_LOW - [6:6] - read-write - - - GPIO17_LEVEL_HIGH - [5:5] - read-write - - - GPIO17_LEVEL_LOW - [4:4] - read-write - - - GPIO16_EDGE_HIGH - [3:3] - read-write - - - GPIO16_EDGE_LOW - [2:2] - read-write - - - GPIO16_LEVEL_HIGH - [1:1] - read-write - - - GPIO16_LEVEL_LOW - [0:0] - read-write - - - - - PROC0_INTE3 - 0x00000254 - Interrupt Enable for proc0 - 0x00000000 - - - GPIO31_EDGE_HIGH - [31:31] - read-write - - - GPIO31_EDGE_LOW - [30:30] - read-write - - - GPIO31_LEVEL_HIGH - [29:29] - read-write - - - GPIO31_LEVEL_LOW - [28:28] - read-write - - - GPIO30_EDGE_HIGH - [27:27] - read-write - - - GPIO30_EDGE_LOW - [26:26] - read-write - - - GPIO30_LEVEL_HIGH - [25:25] - read-write - - - GPIO30_LEVEL_LOW - [24:24] - read-write - - - GPIO29_EDGE_HIGH - [23:23] - read-write - - - GPIO29_EDGE_LOW - [22:22] - read-write - - - GPIO29_LEVEL_HIGH - [21:21] - read-write - - - GPIO29_LEVEL_LOW - [20:20] - read-write - - - GPIO28_EDGE_HIGH - [19:19] - read-write - - - GPIO28_EDGE_LOW - [18:18] - read-write - - - GPIO28_LEVEL_HIGH - [17:17] - read-write - - - GPIO28_LEVEL_LOW - [16:16] - read-write - - - GPIO27_EDGE_HIGH - [15:15] - read-write - - - GPIO27_EDGE_LOW - [14:14] - read-write - - - GPIO27_LEVEL_HIGH - [13:13] - read-write - - - GPIO27_LEVEL_LOW - [12:12] - read-write - - - GPIO26_EDGE_HIGH - [11:11] - read-write - - - GPIO26_EDGE_LOW - [10:10] - read-write - - - GPIO26_LEVEL_HIGH - [9:9] - read-write - - - GPIO26_LEVEL_LOW - [8:8] - read-write - - - GPIO25_EDGE_HIGH - [7:7] - read-write - - - GPIO25_EDGE_LOW - [6:6] - read-write - - - GPIO25_LEVEL_HIGH - [5:5] - read-write - - - GPIO25_LEVEL_LOW - [4:4] - read-write - - - GPIO24_EDGE_HIGH - [3:3] - read-write - - - GPIO24_EDGE_LOW - [2:2] - read-write - - - GPIO24_LEVEL_HIGH - [1:1] - read-write - - - GPIO24_LEVEL_LOW - [0:0] - read-write - - - - - PROC0_INTE4 - 0x00000258 - Interrupt Enable for proc0 - 0x00000000 - - - GPIO39_EDGE_HIGH - [31:31] - read-write - - - GPIO39_EDGE_LOW - [30:30] - read-write - - - GPIO39_LEVEL_HIGH - [29:29] - read-write - - - GPIO39_LEVEL_LOW - [28:28] - read-write - - - GPIO38_EDGE_HIGH - [27:27] - read-write - - - GPIO38_EDGE_LOW - [26:26] - read-write - - - GPIO38_LEVEL_HIGH - [25:25] - read-write - - - GPIO38_LEVEL_LOW - [24:24] - read-write - - - GPIO37_EDGE_HIGH - [23:23] - read-write - - - GPIO37_EDGE_LOW - [22:22] - read-write - - - GPIO37_LEVEL_HIGH - [21:21] - read-write - - - GPIO37_LEVEL_LOW - [20:20] - read-write - - - GPIO36_EDGE_HIGH - [19:19] - read-write - - - GPIO36_EDGE_LOW - [18:18] - read-write - - - GPIO36_LEVEL_HIGH - [17:17] - read-write - - - GPIO36_LEVEL_LOW - [16:16] - read-write - - - GPIO35_EDGE_HIGH - [15:15] - read-write - - - GPIO35_EDGE_LOW - [14:14] - read-write - - - GPIO35_LEVEL_HIGH - [13:13] - read-write - - - GPIO35_LEVEL_LOW - [12:12] - read-write - - - GPIO34_EDGE_HIGH - [11:11] - read-write - - - GPIO34_EDGE_LOW - [10:10] - read-write - - - GPIO34_LEVEL_HIGH - [9:9] - read-write - - - GPIO34_LEVEL_LOW - [8:8] - read-write - - - GPIO33_EDGE_HIGH - [7:7] - read-write - - - GPIO33_EDGE_LOW - [6:6] - read-write - - - GPIO33_LEVEL_HIGH - [5:5] - read-write - - - GPIO33_LEVEL_LOW - [4:4] - read-write - - - GPIO32_EDGE_HIGH - [3:3] - read-write - - - GPIO32_EDGE_LOW - [2:2] - read-write - - - GPIO32_LEVEL_HIGH - [1:1] - read-write - - - GPIO32_LEVEL_LOW - [0:0] - read-write - - - - - PROC0_INTE5 - 0x0000025c - Interrupt Enable for proc0 - 0x00000000 - - - GPIO47_EDGE_HIGH - [31:31] - read-write - - - GPIO47_EDGE_LOW - [30:30] - read-write - - - GPIO47_LEVEL_HIGH - [29:29] - read-write - - - GPIO47_LEVEL_LOW - [28:28] - read-write - - - GPIO46_EDGE_HIGH - [27:27] - read-write - - - GPIO46_EDGE_LOW - [26:26] - read-write - - - GPIO46_LEVEL_HIGH - [25:25] - read-write - - - GPIO46_LEVEL_LOW - [24:24] - read-write - - - GPIO45_EDGE_HIGH - [23:23] - read-write - - - GPIO45_EDGE_LOW - [22:22] - read-write - - - GPIO45_LEVEL_HIGH - [21:21] - read-write - - - GPIO45_LEVEL_LOW - [20:20] - read-write - - - GPIO44_EDGE_HIGH - [19:19] - read-write - - - GPIO44_EDGE_LOW - [18:18] - read-write - - - GPIO44_LEVEL_HIGH - [17:17] - read-write - - - GPIO44_LEVEL_LOW - [16:16] - read-write - - - GPIO43_EDGE_HIGH - [15:15] - read-write - - - GPIO43_EDGE_LOW - [14:14] - read-write - - - GPIO43_LEVEL_HIGH - [13:13] - read-write - - - GPIO43_LEVEL_LOW - [12:12] - read-write - - - GPIO42_EDGE_HIGH - [11:11] - read-write - - - GPIO42_EDGE_LOW - [10:10] - read-write - - - GPIO42_LEVEL_HIGH - [9:9] - read-write - - - GPIO42_LEVEL_LOW - [8:8] - read-write - - - GPIO41_EDGE_HIGH - [7:7] - read-write - - - GPIO41_EDGE_LOW - [6:6] - read-write - - - GPIO41_LEVEL_HIGH - [5:5] - read-write - - - GPIO41_LEVEL_LOW - [4:4] - read-write - - - GPIO40_EDGE_HIGH - [3:3] - read-write - - - GPIO40_EDGE_LOW - [2:2] - read-write - - - GPIO40_LEVEL_HIGH - [1:1] - read-write - - - GPIO40_LEVEL_LOW - [0:0] - read-write - - - - - PROC0_INTF0 - 0x00000260 - Interrupt Force for proc0 - 0x00000000 - - - GPIO7_EDGE_HIGH - [31:31] - read-write - - - GPIO7_EDGE_LOW - [30:30] - read-write - - - GPIO7_LEVEL_HIGH - [29:29] - read-write - - - GPIO7_LEVEL_LOW - [28:28] - read-write - - - GPIO6_EDGE_HIGH - [27:27] - read-write - - - GPIO6_EDGE_LOW - [26:26] - read-write - - - GPIO6_LEVEL_HIGH - [25:25] - read-write - - - GPIO6_LEVEL_LOW - [24:24] - read-write - - - GPIO5_EDGE_HIGH - [23:23] - read-write - - - GPIO5_EDGE_LOW - [22:22] - read-write - - - GPIO5_LEVEL_HIGH - [21:21] - read-write - - - GPIO5_LEVEL_LOW - [20:20] - read-write - - - GPIO4_EDGE_HIGH - [19:19] - read-write - - - GPIO4_EDGE_LOW - [18:18] - read-write - - - GPIO4_LEVEL_HIGH - [17:17] - read-write - - - GPIO4_LEVEL_LOW - [16:16] - read-write - - - GPIO3_EDGE_HIGH - [15:15] - read-write - - - GPIO3_EDGE_LOW - [14:14] - read-write - - - GPIO3_LEVEL_HIGH - [13:13] - read-write - - - GPIO3_LEVEL_LOW - [12:12] - read-write - - - GPIO2_EDGE_HIGH - [11:11] - read-write - - - GPIO2_EDGE_LOW - [10:10] - read-write - - - GPIO2_LEVEL_HIGH - [9:9] - read-write - - - GPIO2_LEVEL_LOW - [8:8] - read-write - - - GPIO1_EDGE_HIGH - [7:7] - read-write - - - GPIO1_EDGE_LOW - [6:6] - read-write - - - GPIO1_LEVEL_HIGH - [5:5] - read-write - - - GPIO1_LEVEL_LOW - [4:4] - read-write - - - GPIO0_EDGE_HIGH - [3:3] - read-write - - - GPIO0_EDGE_LOW - [2:2] - read-write - - - GPIO0_LEVEL_HIGH - [1:1] - read-write - - - GPIO0_LEVEL_LOW - [0:0] - read-write - - - - - PROC0_INTF1 - 0x00000264 - Interrupt Force for proc0 - 0x00000000 - - - GPIO15_EDGE_HIGH - [31:31] - read-write - - - GPIO15_EDGE_LOW - [30:30] - read-write - - - GPIO15_LEVEL_HIGH - [29:29] - read-write - - - GPIO15_LEVEL_LOW - [28:28] - read-write - - - GPIO14_EDGE_HIGH - [27:27] - read-write - - - GPIO14_EDGE_LOW - [26:26] - read-write - - - GPIO14_LEVEL_HIGH - [25:25] - read-write - - - GPIO14_LEVEL_LOW - [24:24] - read-write - - - GPIO13_EDGE_HIGH - [23:23] - read-write - - - GPIO13_EDGE_LOW - [22:22] - read-write - - - GPIO13_LEVEL_HIGH - [21:21] - read-write - - - GPIO13_LEVEL_LOW - [20:20] - read-write - - - GPIO12_EDGE_HIGH - [19:19] - read-write - - - GPIO12_EDGE_LOW - [18:18] - read-write - - - GPIO12_LEVEL_HIGH - [17:17] - read-write - - - GPIO12_LEVEL_LOW - [16:16] - read-write - - - GPIO11_EDGE_HIGH - [15:15] - read-write - - - GPIO11_EDGE_LOW - [14:14] - read-write - - - GPIO11_LEVEL_HIGH - [13:13] - read-write - - - GPIO11_LEVEL_LOW - [12:12] - read-write - - - GPIO10_EDGE_HIGH - [11:11] - read-write - - - GPIO10_EDGE_LOW - [10:10] - read-write - - - GPIO10_LEVEL_HIGH - [9:9] - read-write - - - GPIO10_LEVEL_LOW - [8:8] - read-write - - - GPIO9_EDGE_HIGH - [7:7] - read-write - - - GPIO9_EDGE_LOW - [6:6] - read-write - - - GPIO9_LEVEL_HIGH - [5:5] - read-write - - - GPIO9_LEVEL_LOW - [4:4] - read-write - - - GPIO8_EDGE_HIGH - [3:3] - read-write - - - GPIO8_EDGE_LOW - [2:2] - read-write - - - GPIO8_LEVEL_HIGH - [1:1] - read-write - - - GPIO8_LEVEL_LOW - [0:0] - read-write - - - - - PROC0_INTF2 - 0x00000268 - Interrupt Force for proc0 - 0x00000000 - - - GPIO23_EDGE_HIGH - [31:31] - read-write - - - GPIO23_EDGE_LOW - [30:30] - read-write - - - GPIO23_LEVEL_HIGH - [29:29] - read-write - - - GPIO23_LEVEL_LOW - [28:28] - read-write - - - GPIO22_EDGE_HIGH - [27:27] - read-write - - - GPIO22_EDGE_LOW - [26:26] - read-write - - - GPIO22_LEVEL_HIGH - [25:25] - read-write - - - GPIO22_LEVEL_LOW - [24:24] - read-write - - - GPIO21_EDGE_HIGH - [23:23] - read-write - - - GPIO21_EDGE_LOW - [22:22] - read-write - - - GPIO21_LEVEL_HIGH - [21:21] - read-write - - - GPIO21_LEVEL_LOW - [20:20] - read-write - - - GPIO20_EDGE_HIGH - [19:19] - read-write - - - GPIO20_EDGE_LOW - [18:18] - read-write - - - GPIO20_LEVEL_HIGH - [17:17] - read-write - - - GPIO20_LEVEL_LOW - [16:16] - read-write - - - GPIO19_EDGE_HIGH - [15:15] - read-write - - - GPIO19_EDGE_LOW - [14:14] - read-write - - - GPIO19_LEVEL_HIGH - [13:13] - read-write - - - GPIO19_LEVEL_LOW - [12:12] - read-write - - - GPIO18_EDGE_HIGH - [11:11] - read-write - - - GPIO18_EDGE_LOW - [10:10] - read-write - - - GPIO18_LEVEL_HIGH - [9:9] - read-write - - - GPIO18_LEVEL_LOW - [8:8] - read-write - - - GPIO17_EDGE_HIGH - [7:7] - read-write - - - GPIO17_EDGE_LOW - [6:6] - read-write - - - GPIO17_LEVEL_HIGH - [5:5] - read-write - - - GPIO17_LEVEL_LOW - [4:4] - read-write - - - GPIO16_EDGE_HIGH - [3:3] - read-write - - - GPIO16_EDGE_LOW - [2:2] - read-write - - - GPIO16_LEVEL_HIGH - [1:1] - read-write - - - GPIO16_LEVEL_LOW - [0:0] - read-write - - - - - PROC0_INTF3 - 0x0000026c - Interrupt Force for proc0 - 0x00000000 - - - GPIO31_EDGE_HIGH - [31:31] - read-write - - - GPIO31_EDGE_LOW - [30:30] - read-write - - - GPIO31_LEVEL_HIGH - [29:29] - read-write - - - GPIO31_LEVEL_LOW - [28:28] - read-write - - - GPIO30_EDGE_HIGH - [27:27] - read-write - - - GPIO30_EDGE_LOW - [26:26] - read-write - - - GPIO30_LEVEL_HIGH - [25:25] - read-write - - - GPIO30_LEVEL_LOW - [24:24] - read-write - - - GPIO29_EDGE_HIGH - [23:23] - read-write - - - GPIO29_EDGE_LOW - [22:22] - read-write - - - GPIO29_LEVEL_HIGH - [21:21] - read-write - - - GPIO29_LEVEL_LOW - [20:20] - read-write - - - GPIO28_EDGE_HIGH - [19:19] - read-write - - - GPIO28_EDGE_LOW - [18:18] - read-write - - - GPIO28_LEVEL_HIGH - [17:17] - read-write - - - GPIO28_LEVEL_LOW - [16:16] - read-write - - - GPIO27_EDGE_HIGH - [15:15] - read-write - - - GPIO27_EDGE_LOW - [14:14] - read-write - - - GPIO27_LEVEL_HIGH - [13:13] - read-write - - - GPIO27_LEVEL_LOW - [12:12] - read-write - - - GPIO26_EDGE_HIGH - [11:11] - read-write - - - GPIO26_EDGE_LOW - [10:10] - read-write - - - GPIO26_LEVEL_HIGH - [9:9] - read-write - - - GPIO26_LEVEL_LOW - [8:8] - read-write - - - GPIO25_EDGE_HIGH - [7:7] - read-write - - - GPIO25_EDGE_LOW - [6:6] - read-write - - - GPIO25_LEVEL_HIGH - [5:5] - read-write - - - GPIO25_LEVEL_LOW - [4:4] - read-write - - - GPIO24_EDGE_HIGH - [3:3] - read-write - - - GPIO24_EDGE_LOW - [2:2] - read-write - - - GPIO24_LEVEL_HIGH - [1:1] - read-write - - - GPIO24_LEVEL_LOW - [0:0] - read-write - - - - - PROC0_INTF4 - 0x00000270 - Interrupt Force for proc0 - 0x00000000 - - - GPIO39_EDGE_HIGH - [31:31] - read-write - - - GPIO39_EDGE_LOW - [30:30] - read-write - - - GPIO39_LEVEL_HIGH - [29:29] - read-write - - - GPIO39_LEVEL_LOW - [28:28] - read-write - - - GPIO38_EDGE_HIGH - [27:27] - read-write - - - GPIO38_EDGE_LOW - [26:26] - read-write - - - GPIO38_LEVEL_HIGH - [25:25] - read-write - - - GPIO38_LEVEL_LOW - [24:24] - read-write - - - GPIO37_EDGE_HIGH - [23:23] - read-write - - - GPIO37_EDGE_LOW - [22:22] - read-write - - - GPIO37_LEVEL_HIGH - [21:21] - read-write - - - GPIO37_LEVEL_LOW - [20:20] - read-write - - - GPIO36_EDGE_HIGH - [19:19] - read-write - - - GPIO36_EDGE_LOW - [18:18] - read-write - - - GPIO36_LEVEL_HIGH - [17:17] - read-write - - - GPIO36_LEVEL_LOW - [16:16] - read-write - - - GPIO35_EDGE_HIGH - [15:15] - read-write - - - GPIO35_EDGE_LOW - [14:14] - read-write - - - GPIO35_LEVEL_HIGH - [13:13] - read-write - - - GPIO35_LEVEL_LOW - [12:12] - read-write - - - GPIO34_EDGE_HIGH - [11:11] - read-write - - - GPIO34_EDGE_LOW - [10:10] - read-write - - - GPIO34_LEVEL_HIGH - [9:9] - read-write - - - GPIO34_LEVEL_LOW - [8:8] - read-write - - - GPIO33_EDGE_HIGH - [7:7] - read-write - - - GPIO33_EDGE_LOW - [6:6] - read-write - - - GPIO33_LEVEL_HIGH - [5:5] - read-write - - - GPIO33_LEVEL_LOW - [4:4] - read-write - - - GPIO32_EDGE_HIGH - [3:3] - read-write - - - GPIO32_EDGE_LOW - [2:2] - read-write - - - GPIO32_LEVEL_HIGH - [1:1] - read-write - - - GPIO32_LEVEL_LOW - [0:0] - read-write - - - - - PROC0_INTF5 - 0x00000274 - Interrupt Force for proc0 - 0x00000000 - - - GPIO47_EDGE_HIGH - [31:31] - read-write - - - GPIO47_EDGE_LOW - [30:30] - read-write - - - GPIO47_LEVEL_HIGH - [29:29] - read-write - - - GPIO47_LEVEL_LOW - [28:28] - read-write - - - GPIO46_EDGE_HIGH - [27:27] - read-write - - - GPIO46_EDGE_LOW - [26:26] - read-write - - - GPIO46_LEVEL_HIGH - [25:25] - read-write - - - GPIO46_LEVEL_LOW - [24:24] - read-write - - - GPIO45_EDGE_HIGH - [23:23] - read-write - - - GPIO45_EDGE_LOW - [22:22] - read-write - - - GPIO45_LEVEL_HIGH - [21:21] - read-write - - - GPIO45_LEVEL_LOW - [20:20] - read-write - - - GPIO44_EDGE_HIGH - [19:19] - read-write - - - GPIO44_EDGE_LOW - [18:18] - read-write - - - GPIO44_LEVEL_HIGH - [17:17] - read-write - - - GPIO44_LEVEL_LOW - [16:16] - read-write - - - GPIO43_EDGE_HIGH - [15:15] - read-write - - - GPIO43_EDGE_LOW - [14:14] - read-write - - - GPIO43_LEVEL_HIGH - [13:13] - read-write - - - GPIO43_LEVEL_LOW - [12:12] - read-write - - - GPIO42_EDGE_HIGH - [11:11] - read-write - - - GPIO42_EDGE_LOW - [10:10] - read-write - - - GPIO42_LEVEL_HIGH - [9:9] - read-write - - - GPIO42_LEVEL_LOW - [8:8] - read-write - - - GPIO41_EDGE_HIGH - [7:7] - read-write - - - GPIO41_EDGE_LOW - [6:6] - read-write - - - GPIO41_LEVEL_HIGH - [5:5] - read-write - - - GPIO41_LEVEL_LOW - [4:4] - read-write - - - GPIO40_EDGE_HIGH - [3:3] - read-write - - - GPIO40_EDGE_LOW - [2:2] - read-write - - - GPIO40_LEVEL_HIGH - [1:1] - read-write - - - GPIO40_LEVEL_LOW - [0:0] - read-write - - - - - PROC0_INTS0 - 0x00000278 - Interrupt status after masking & forcing for proc0 - 0x00000000 - - - GPIO7_EDGE_HIGH - [31:31] - read-only - - - GPIO7_EDGE_LOW - [30:30] - read-only - - - GPIO7_LEVEL_HIGH - [29:29] - read-only - - - GPIO7_LEVEL_LOW - [28:28] - read-only - - - GPIO6_EDGE_HIGH - [27:27] - read-only - - - GPIO6_EDGE_LOW - [26:26] - read-only - - - GPIO6_LEVEL_HIGH - [25:25] - read-only - - - GPIO6_LEVEL_LOW - [24:24] - read-only - - - GPIO5_EDGE_HIGH - [23:23] - read-only - - - GPIO5_EDGE_LOW - [22:22] - read-only - - - GPIO5_LEVEL_HIGH - [21:21] - read-only - - - GPIO5_LEVEL_LOW - [20:20] - read-only - - - GPIO4_EDGE_HIGH - [19:19] - read-only - - - GPIO4_EDGE_LOW - [18:18] - read-only - - - GPIO4_LEVEL_HIGH - [17:17] - read-only - - - GPIO4_LEVEL_LOW - [16:16] - read-only - - - GPIO3_EDGE_HIGH - [15:15] - read-only - - - GPIO3_EDGE_LOW - [14:14] - read-only - - - GPIO3_LEVEL_HIGH - [13:13] - read-only - - - GPIO3_LEVEL_LOW - [12:12] - read-only - - - GPIO2_EDGE_HIGH - [11:11] - read-only - - - GPIO2_EDGE_LOW - [10:10] - read-only - - - GPIO2_LEVEL_HIGH - [9:9] - read-only - - - GPIO2_LEVEL_LOW - [8:8] - read-only - - - GPIO1_EDGE_HIGH - [7:7] - read-only - - - GPIO1_EDGE_LOW - [6:6] - read-only - - - GPIO1_LEVEL_HIGH - [5:5] - read-only - - - GPIO1_LEVEL_LOW - [4:4] - read-only - - - GPIO0_EDGE_HIGH - [3:3] - read-only - - - GPIO0_EDGE_LOW - [2:2] - read-only - - - GPIO0_LEVEL_HIGH - [1:1] - read-only - - - GPIO0_LEVEL_LOW - [0:0] - read-only - - - - - PROC0_INTS1 - 0x0000027c - Interrupt status after masking & forcing for proc0 - 0x00000000 - - - GPIO15_EDGE_HIGH - [31:31] - read-only - - - GPIO15_EDGE_LOW - [30:30] - read-only - - - GPIO15_LEVEL_HIGH - [29:29] - read-only - - - GPIO15_LEVEL_LOW - [28:28] - read-only - - - GPIO14_EDGE_HIGH - [27:27] - read-only - - - GPIO14_EDGE_LOW - [26:26] - read-only - - - GPIO14_LEVEL_HIGH - [25:25] - read-only - - - GPIO14_LEVEL_LOW - [24:24] - read-only - - - GPIO13_EDGE_HIGH - [23:23] - read-only - - - GPIO13_EDGE_LOW - [22:22] - read-only - - - GPIO13_LEVEL_HIGH - [21:21] - read-only - - - GPIO13_LEVEL_LOW - [20:20] - read-only - - - GPIO12_EDGE_HIGH - [19:19] - read-only - - - GPIO12_EDGE_LOW - [18:18] - read-only - - - GPIO12_LEVEL_HIGH - [17:17] - read-only - - - GPIO12_LEVEL_LOW - [16:16] - read-only - - - GPIO11_EDGE_HIGH - [15:15] - read-only - - - GPIO11_EDGE_LOW - [14:14] - read-only - - - GPIO11_LEVEL_HIGH - [13:13] - read-only - - - GPIO11_LEVEL_LOW - [12:12] - read-only - - - GPIO10_EDGE_HIGH - [11:11] - read-only - - - GPIO10_EDGE_LOW - [10:10] - read-only - - - GPIO10_LEVEL_HIGH - [9:9] - read-only - - - GPIO10_LEVEL_LOW - [8:8] - read-only - - - GPIO9_EDGE_HIGH - [7:7] - read-only - - - GPIO9_EDGE_LOW - [6:6] - read-only - - - GPIO9_LEVEL_HIGH - [5:5] - read-only - - - GPIO9_LEVEL_LOW - [4:4] - read-only - - - GPIO8_EDGE_HIGH - [3:3] - read-only - - - GPIO8_EDGE_LOW - [2:2] - read-only - - - GPIO8_LEVEL_HIGH - [1:1] - read-only - - - GPIO8_LEVEL_LOW - [0:0] - read-only - - - - - PROC0_INTS2 - 0x00000280 - Interrupt status after masking & forcing for proc0 - 0x00000000 - - - GPIO23_EDGE_HIGH - [31:31] - read-only - - - GPIO23_EDGE_LOW - [30:30] - read-only - - - GPIO23_LEVEL_HIGH - [29:29] - read-only - - - GPIO23_LEVEL_LOW - [28:28] - read-only - - - GPIO22_EDGE_HIGH - [27:27] - read-only - - - GPIO22_EDGE_LOW - [26:26] - read-only - - - GPIO22_LEVEL_HIGH - [25:25] - read-only - - - GPIO22_LEVEL_LOW - [24:24] - read-only - - - GPIO21_EDGE_HIGH - [23:23] - read-only - - - GPIO21_EDGE_LOW - [22:22] - read-only - - - GPIO21_LEVEL_HIGH - [21:21] - read-only - - - GPIO21_LEVEL_LOW - [20:20] - read-only - - - GPIO20_EDGE_HIGH - [19:19] - read-only - - - GPIO20_EDGE_LOW - [18:18] - read-only - - - GPIO20_LEVEL_HIGH - [17:17] - read-only - - - GPIO20_LEVEL_LOW - [16:16] - read-only - - - GPIO19_EDGE_HIGH - [15:15] - read-only - - - GPIO19_EDGE_LOW - [14:14] - read-only - - - GPIO19_LEVEL_HIGH - [13:13] - read-only - - - GPIO19_LEVEL_LOW - [12:12] - read-only - - - GPIO18_EDGE_HIGH - [11:11] - read-only - - - GPIO18_EDGE_LOW - [10:10] - read-only - - - GPIO18_LEVEL_HIGH - [9:9] - read-only - - - GPIO18_LEVEL_LOW - [8:8] - read-only - - - GPIO17_EDGE_HIGH - [7:7] - read-only - - - GPIO17_EDGE_LOW - [6:6] - read-only - - - GPIO17_LEVEL_HIGH - [5:5] - read-only - - - GPIO17_LEVEL_LOW - [4:4] - read-only - - - GPIO16_EDGE_HIGH - [3:3] - read-only - - - GPIO16_EDGE_LOW - [2:2] - read-only - - - GPIO16_LEVEL_HIGH - [1:1] - read-only - - - GPIO16_LEVEL_LOW - [0:0] - read-only - - - - - PROC0_INTS3 - 0x00000284 - Interrupt status after masking & forcing for proc0 - 0x00000000 - - - GPIO31_EDGE_HIGH - [31:31] - read-only - - - GPIO31_EDGE_LOW - [30:30] - read-only - - - GPIO31_LEVEL_HIGH - [29:29] - read-only - - - GPIO31_LEVEL_LOW - [28:28] - read-only - - - GPIO30_EDGE_HIGH - [27:27] - read-only - - - GPIO30_EDGE_LOW - [26:26] - read-only - - - GPIO30_LEVEL_HIGH - [25:25] - read-only - - - GPIO30_LEVEL_LOW - [24:24] - read-only - - - GPIO29_EDGE_HIGH - [23:23] - read-only - - - GPIO29_EDGE_LOW - [22:22] - read-only - - - GPIO29_LEVEL_HIGH - [21:21] - read-only - - - GPIO29_LEVEL_LOW - [20:20] - read-only - - - GPIO28_EDGE_HIGH - [19:19] - read-only - - - GPIO28_EDGE_LOW - [18:18] - read-only - - - GPIO28_LEVEL_HIGH - [17:17] - read-only - - - GPIO28_LEVEL_LOW - [16:16] - read-only - - - GPIO27_EDGE_HIGH - [15:15] - read-only - - - GPIO27_EDGE_LOW - [14:14] - read-only - - - GPIO27_LEVEL_HIGH - [13:13] - read-only - - - GPIO27_LEVEL_LOW - [12:12] - read-only - - - GPIO26_EDGE_HIGH - [11:11] - read-only - - - GPIO26_EDGE_LOW - [10:10] - read-only - - - GPIO26_LEVEL_HIGH - [9:9] - read-only - - - GPIO26_LEVEL_LOW - [8:8] - read-only - - - GPIO25_EDGE_HIGH - [7:7] - read-only - - - GPIO25_EDGE_LOW - [6:6] - read-only - - - GPIO25_LEVEL_HIGH - [5:5] - read-only - - - GPIO25_LEVEL_LOW - [4:4] - read-only - - - GPIO24_EDGE_HIGH - [3:3] - read-only - - - GPIO24_EDGE_LOW - [2:2] - read-only - - - GPIO24_LEVEL_HIGH - [1:1] - read-only - - - GPIO24_LEVEL_LOW - [0:0] - read-only - - - - - PROC0_INTS4 - 0x00000288 - Interrupt status after masking & forcing for proc0 - 0x00000000 - - - GPIO39_EDGE_HIGH - [31:31] - read-only - - - GPIO39_EDGE_LOW - [30:30] - read-only - - - GPIO39_LEVEL_HIGH - [29:29] - read-only - - - GPIO39_LEVEL_LOW - [28:28] - read-only - - - GPIO38_EDGE_HIGH - [27:27] - read-only - - - GPIO38_EDGE_LOW - [26:26] - read-only - - - GPIO38_LEVEL_HIGH - [25:25] - read-only - - - GPIO38_LEVEL_LOW - [24:24] - read-only - - - GPIO37_EDGE_HIGH - [23:23] - read-only - - - GPIO37_EDGE_LOW - [22:22] - read-only - - - GPIO37_LEVEL_HIGH - [21:21] - read-only - - - GPIO37_LEVEL_LOW - [20:20] - read-only - - - GPIO36_EDGE_HIGH - [19:19] - read-only - - - GPIO36_EDGE_LOW - [18:18] - read-only - - - GPIO36_LEVEL_HIGH - [17:17] - read-only - - - GPIO36_LEVEL_LOW - [16:16] - read-only - - - GPIO35_EDGE_HIGH - [15:15] - read-only - - - GPIO35_EDGE_LOW - [14:14] - read-only - - - GPIO35_LEVEL_HIGH - [13:13] - read-only - - - GPIO35_LEVEL_LOW - [12:12] - read-only - - - GPIO34_EDGE_HIGH - [11:11] - read-only - - - GPIO34_EDGE_LOW - [10:10] - read-only - - - GPIO34_LEVEL_HIGH - [9:9] - read-only - - - GPIO34_LEVEL_LOW - [8:8] - read-only - - - GPIO33_EDGE_HIGH - [7:7] - read-only - - - GPIO33_EDGE_LOW - [6:6] - read-only - - - GPIO33_LEVEL_HIGH - [5:5] - read-only - - - GPIO33_LEVEL_LOW - [4:4] - read-only - - - GPIO32_EDGE_HIGH - [3:3] - read-only - - - GPIO32_EDGE_LOW - [2:2] - read-only - - - GPIO32_LEVEL_HIGH - [1:1] - read-only - - - GPIO32_LEVEL_LOW - [0:0] - read-only - - - - - PROC0_INTS5 - 0x0000028c - Interrupt status after masking & forcing for proc0 - 0x00000000 - - - GPIO47_EDGE_HIGH - [31:31] - read-only - - - GPIO47_EDGE_LOW - [30:30] - read-only - - - GPIO47_LEVEL_HIGH - [29:29] - read-only - - - GPIO47_LEVEL_LOW - [28:28] - read-only - - - GPIO46_EDGE_HIGH - [27:27] - read-only - - - GPIO46_EDGE_LOW - [26:26] - read-only - - - GPIO46_LEVEL_HIGH - [25:25] - read-only - - - GPIO46_LEVEL_LOW - [24:24] - read-only - - - GPIO45_EDGE_HIGH - [23:23] - read-only - - - GPIO45_EDGE_LOW - [22:22] - read-only - - - GPIO45_LEVEL_HIGH - [21:21] - read-only - - - GPIO45_LEVEL_LOW - [20:20] - read-only - - - GPIO44_EDGE_HIGH - [19:19] - read-only - - - GPIO44_EDGE_LOW - [18:18] - read-only - - - GPIO44_LEVEL_HIGH - [17:17] - read-only - - - GPIO44_LEVEL_LOW - [16:16] - read-only - - - GPIO43_EDGE_HIGH - [15:15] - read-only - - - GPIO43_EDGE_LOW - [14:14] - read-only - - - GPIO43_LEVEL_HIGH - [13:13] - read-only - - - GPIO43_LEVEL_LOW - [12:12] - read-only - - - GPIO42_EDGE_HIGH - [11:11] - read-only - - - GPIO42_EDGE_LOW - [10:10] - read-only - - - GPIO42_LEVEL_HIGH - [9:9] - read-only - - - GPIO42_LEVEL_LOW - [8:8] - read-only - - - GPIO41_EDGE_HIGH - [7:7] - read-only - - - GPIO41_EDGE_LOW - [6:6] - read-only - - - GPIO41_LEVEL_HIGH - [5:5] - read-only - - - GPIO41_LEVEL_LOW - [4:4] - read-only - - - GPIO40_EDGE_HIGH - [3:3] - read-only - - - GPIO40_EDGE_LOW - [2:2] - read-only - - - GPIO40_LEVEL_HIGH - [1:1] - read-only - - - GPIO40_LEVEL_LOW - [0:0] - read-only - - - - - PROC1_INTE0 - 0x00000290 - Interrupt Enable for proc1 - 0x00000000 - - - GPIO7_EDGE_HIGH - [31:31] - read-write - - - GPIO7_EDGE_LOW - [30:30] - read-write - - - GPIO7_LEVEL_HIGH - [29:29] - read-write - - - GPIO7_LEVEL_LOW - [28:28] - read-write - - - GPIO6_EDGE_HIGH - [27:27] - read-write - - - GPIO6_EDGE_LOW - [26:26] - read-write - - - GPIO6_LEVEL_HIGH - [25:25] - read-write - - - GPIO6_LEVEL_LOW - [24:24] - read-write - - - GPIO5_EDGE_HIGH - [23:23] - read-write - - - GPIO5_EDGE_LOW - [22:22] - read-write - - - GPIO5_LEVEL_HIGH - [21:21] - read-write - - - GPIO5_LEVEL_LOW - [20:20] - read-write - - - GPIO4_EDGE_HIGH - [19:19] - read-write - - - GPIO4_EDGE_LOW - [18:18] - read-write - - - GPIO4_LEVEL_HIGH - [17:17] - read-write - - - GPIO4_LEVEL_LOW - [16:16] - read-write - - - GPIO3_EDGE_HIGH - [15:15] - read-write - - - GPIO3_EDGE_LOW - [14:14] - read-write - - - GPIO3_LEVEL_HIGH - [13:13] - read-write - - - GPIO3_LEVEL_LOW - [12:12] - read-write - - - GPIO2_EDGE_HIGH - [11:11] - read-write - - - GPIO2_EDGE_LOW - [10:10] - read-write - - - GPIO2_LEVEL_HIGH - [9:9] - read-write - - - GPIO2_LEVEL_LOW - [8:8] - read-write - - - GPIO1_EDGE_HIGH - [7:7] - read-write - - - GPIO1_EDGE_LOW - [6:6] - read-write - - - GPIO1_LEVEL_HIGH - [5:5] - read-write - - - GPIO1_LEVEL_LOW - [4:4] - read-write - - - GPIO0_EDGE_HIGH - [3:3] - read-write - - - GPIO0_EDGE_LOW - [2:2] - read-write - - - GPIO0_LEVEL_HIGH - [1:1] - read-write - - - GPIO0_LEVEL_LOW - [0:0] - read-write - - - - - PROC1_INTE1 - 0x00000294 - Interrupt Enable for proc1 - 0x00000000 - - - GPIO15_EDGE_HIGH - [31:31] - read-write - - - GPIO15_EDGE_LOW - [30:30] - read-write - - - GPIO15_LEVEL_HIGH - [29:29] - read-write - - - GPIO15_LEVEL_LOW - [28:28] - read-write - - - GPIO14_EDGE_HIGH - [27:27] - read-write - - - GPIO14_EDGE_LOW - [26:26] - read-write - - - GPIO14_LEVEL_HIGH - [25:25] - read-write - - - GPIO14_LEVEL_LOW - [24:24] - read-write - - - GPIO13_EDGE_HIGH - [23:23] - read-write - - - GPIO13_EDGE_LOW - [22:22] - read-write - - - GPIO13_LEVEL_HIGH - [21:21] - read-write - - - GPIO13_LEVEL_LOW - [20:20] - read-write - - - GPIO12_EDGE_HIGH - [19:19] - read-write - - - GPIO12_EDGE_LOW - [18:18] - read-write - - - GPIO12_LEVEL_HIGH - [17:17] - read-write - - - GPIO12_LEVEL_LOW - [16:16] - read-write - - - GPIO11_EDGE_HIGH - [15:15] - read-write - - - GPIO11_EDGE_LOW - [14:14] - read-write - - - GPIO11_LEVEL_HIGH - [13:13] - read-write - - - GPIO11_LEVEL_LOW - [12:12] - read-write - - - GPIO10_EDGE_HIGH - [11:11] - read-write - - - GPIO10_EDGE_LOW - [10:10] - read-write - - - GPIO10_LEVEL_HIGH - [9:9] - read-write - - - GPIO10_LEVEL_LOW - [8:8] - read-write - - - GPIO9_EDGE_HIGH - [7:7] - read-write - - - GPIO9_EDGE_LOW - [6:6] - read-write - - - GPIO9_LEVEL_HIGH - [5:5] - read-write - - - GPIO9_LEVEL_LOW - [4:4] - read-write - - - GPIO8_EDGE_HIGH - [3:3] - read-write - - - GPIO8_EDGE_LOW - [2:2] - read-write - - - GPIO8_LEVEL_HIGH - [1:1] - read-write - - - GPIO8_LEVEL_LOW - [0:0] - read-write - - - - - PROC1_INTE2 - 0x00000298 - Interrupt Enable for proc1 - 0x00000000 - - - GPIO23_EDGE_HIGH - [31:31] - read-write - - - GPIO23_EDGE_LOW - [30:30] - read-write - - - GPIO23_LEVEL_HIGH - [29:29] - read-write - - - GPIO23_LEVEL_LOW - [28:28] - read-write - - - GPIO22_EDGE_HIGH - [27:27] - read-write - - - GPIO22_EDGE_LOW - [26:26] - read-write - - - GPIO22_LEVEL_HIGH - [25:25] - read-write - - - GPIO22_LEVEL_LOW - [24:24] - read-write - - - GPIO21_EDGE_HIGH - [23:23] - read-write - - - GPIO21_EDGE_LOW - [22:22] - read-write - - - GPIO21_LEVEL_HIGH - [21:21] - read-write - - - GPIO21_LEVEL_LOW - [20:20] - read-write - - - GPIO20_EDGE_HIGH - [19:19] - read-write - - - GPIO20_EDGE_LOW - [18:18] - read-write - - - GPIO20_LEVEL_HIGH - [17:17] - read-write - - - GPIO20_LEVEL_LOW - [16:16] - read-write - - - GPIO19_EDGE_HIGH - [15:15] - read-write - - - GPIO19_EDGE_LOW - [14:14] - read-write - - - GPIO19_LEVEL_HIGH - [13:13] - read-write - - - GPIO19_LEVEL_LOW - [12:12] - read-write - - - GPIO18_EDGE_HIGH - [11:11] - read-write - - - GPIO18_EDGE_LOW - [10:10] - read-write - - - GPIO18_LEVEL_HIGH - [9:9] - read-write - - - GPIO18_LEVEL_LOW - [8:8] - read-write - - - GPIO17_EDGE_HIGH - [7:7] - read-write - - - GPIO17_EDGE_LOW - [6:6] - read-write - - - GPIO17_LEVEL_HIGH - [5:5] - read-write - - - GPIO17_LEVEL_LOW - [4:4] - read-write - - - GPIO16_EDGE_HIGH - [3:3] - read-write - - - GPIO16_EDGE_LOW - [2:2] - read-write - - - GPIO16_LEVEL_HIGH - [1:1] - read-write - - - GPIO16_LEVEL_LOW - [0:0] - read-write - - - - - PROC1_INTE3 - 0x0000029c - Interrupt Enable for proc1 - 0x00000000 - - - GPIO31_EDGE_HIGH - [31:31] - read-write - - - GPIO31_EDGE_LOW - [30:30] - read-write - - - GPIO31_LEVEL_HIGH - [29:29] - read-write - - - GPIO31_LEVEL_LOW - [28:28] - read-write - - - GPIO30_EDGE_HIGH - [27:27] - read-write - - - GPIO30_EDGE_LOW - [26:26] - read-write - - - GPIO30_LEVEL_HIGH - [25:25] - read-write - - - GPIO30_LEVEL_LOW - [24:24] - read-write - - - GPIO29_EDGE_HIGH - [23:23] - read-write - - - GPIO29_EDGE_LOW - [22:22] - read-write - - - GPIO29_LEVEL_HIGH - [21:21] - read-write - - - GPIO29_LEVEL_LOW - [20:20] - read-write - - - GPIO28_EDGE_HIGH - [19:19] - read-write - - - GPIO28_EDGE_LOW - [18:18] - read-write - - - GPIO28_LEVEL_HIGH - [17:17] - read-write - - - GPIO28_LEVEL_LOW - [16:16] - read-write - - - GPIO27_EDGE_HIGH - [15:15] - read-write - - - GPIO27_EDGE_LOW - [14:14] - read-write - - - GPIO27_LEVEL_HIGH - [13:13] - read-write - - - GPIO27_LEVEL_LOW - [12:12] - read-write - - - GPIO26_EDGE_HIGH - [11:11] - read-write - - - GPIO26_EDGE_LOW - [10:10] - read-write - - - GPIO26_LEVEL_HIGH - [9:9] - read-write - - - GPIO26_LEVEL_LOW - [8:8] - read-write - - - GPIO25_EDGE_HIGH - [7:7] - read-write - - - GPIO25_EDGE_LOW - [6:6] - read-write - - - GPIO25_LEVEL_HIGH - [5:5] - read-write - - - GPIO25_LEVEL_LOW - [4:4] - read-write - - - GPIO24_EDGE_HIGH - [3:3] - read-write - - - GPIO24_EDGE_LOW - [2:2] - read-write - - - GPIO24_LEVEL_HIGH - [1:1] - read-write - - - GPIO24_LEVEL_LOW - [0:0] - read-write - - - - - PROC1_INTE4 - 0x000002a0 - Interrupt Enable for proc1 - 0x00000000 - - - GPIO39_EDGE_HIGH - [31:31] - read-write - - - GPIO39_EDGE_LOW - [30:30] - read-write - - - GPIO39_LEVEL_HIGH - [29:29] - read-write - - - GPIO39_LEVEL_LOW - [28:28] - read-write - - - GPIO38_EDGE_HIGH - [27:27] - read-write - - - GPIO38_EDGE_LOW - [26:26] - read-write - - - GPIO38_LEVEL_HIGH - [25:25] - read-write - - - GPIO38_LEVEL_LOW - [24:24] - read-write - - - GPIO37_EDGE_HIGH - [23:23] - read-write - - - GPIO37_EDGE_LOW - [22:22] - read-write - - - GPIO37_LEVEL_HIGH - [21:21] - read-write - - - GPIO37_LEVEL_LOW - [20:20] - read-write - - - GPIO36_EDGE_HIGH - [19:19] - read-write - - - GPIO36_EDGE_LOW - [18:18] - read-write - - - GPIO36_LEVEL_HIGH - [17:17] - read-write - - - GPIO36_LEVEL_LOW - [16:16] - read-write - - - GPIO35_EDGE_HIGH - [15:15] - read-write - - - GPIO35_EDGE_LOW - [14:14] - read-write - - - GPIO35_LEVEL_HIGH - [13:13] - read-write - - - GPIO35_LEVEL_LOW - [12:12] - read-write - - - GPIO34_EDGE_HIGH - [11:11] - read-write - - - GPIO34_EDGE_LOW - [10:10] - read-write - - - GPIO34_LEVEL_HIGH - [9:9] - read-write - - - GPIO34_LEVEL_LOW - [8:8] - read-write - - - GPIO33_EDGE_HIGH - [7:7] - read-write - - - GPIO33_EDGE_LOW - [6:6] - read-write - - - GPIO33_LEVEL_HIGH - [5:5] - read-write - - - GPIO33_LEVEL_LOW - [4:4] - read-write - - - GPIO32_EDGE_HIGH - [3:3] - read-write - - - GPIO32_EDGE_LOW - [2:2] - read-write - - - GPIO32_LEVEL_HIGH - [1:1] - read-write - - - GPIO32_LEVEL_LOW - [0:0] - read-write - - - - - PROC1_INTE5 - 0x000002a4 - Interrupt Enable for proc1 - 0x00000000 - - - GPIO47_EDGE_HIGH - [31:31] - read-write - - - GPIO47_EDGE_LOW - [30:30] - read-write - - - GPIO47_LEVEL_HIGH - [29:29] - read-write - - - GPIO47_LEVEL_LOW - [28:28] - read-write - - - GPIO46_EDGE_HIGH - [27:27] - read-write - - - GPIO46_EDGE_LOW - [26:26] - read-write - - - GPIO46_LEVEL_HIGH - [25:25] - read-write - - - GPIO46_LEVEL_LOW - [24:24] - read-write - - - GPIO45_EDGE_HIGH - [23:23] - read-write - - - GPIO45_EDGE_LOW - [22:22] - read-write - - - GPIO45_LEVEL_HIGH - [21:21] - read-write - - - GPIO45_LEVEL_LOW - [20:20] - read-write - - - GPIO44_EDGE_HIGH - [19:19] - read-write - - - GPIO44_EDGE_LOW - [18:18] - read-write - - - GPIO44_LEVEL_HIGH - [17:17] - read-write - - - GPIO44_LEVEL_LOW - [16:16] - read-write - - - GPIO43_EDGE_HIGH - [15:15] - read-write - - - GPIO43_EDGE_LOW - [14:14] - read-write - - - GPIO43_LEVEL_HIGH - [13:13] - read-write - - - GPIO43_LEVEL_LOW - [12:12] - read-write - - - GPIO42_EDGE_HIGH - [11:11] - read-write - - - GPIO42_EDGE_LOW - [10:10] - read-write - - - GPIO42_LEVEL_HIGH - [9:9] - read-write - - - GPIO42_LEVEL_LOW - [8:8] - read-write - - - GPIO41_EDGE_HIGH - [7:7] - read-write - - - GPIO41_EDGE_LOW - [6:6] - read-write - - - GPIO41_LEVEL_HIGH - [5:5] - read-write - - - GPIO41_LEVEL_LOW - [4:4] - read-write - - - GPIO40_EDGE_HIGH - [3:3] - read-write - - - GPIO40_EDGE_LOW - [2:2] - read-write - - - GPIO40_LEVEL_HIGH - [1:1] - read-write - - - GPIO40_LEVEL_LOW - [0:0] - read-write - - - - - PROC1_INTF0 - 0x000002a8 - Interrupt Force for proc1 - 0x00000000 - - - GPIO7_EDGE_HIGH - [31:31] - read-write - - - GPIO7_EDGE_LOW - [30:30] - read-write - - - GPIO7_LEVEL_HIGH - [29:29] - read-write - - - GPIO7_LEVEL_LOW - [28:28] - read-write - - - GPIO6_EDGE_HIGH - [27:27] - read-write - - - GPIO6_EDGE_LOW - [26:26] - read-write - - - GPIO6_LEVEL_HIGH - [25:25] - read-write - - - GPIO6_LEVEL_LOW - [24:24] - read-write - - - GPIO5_EDGE_HIGH - [23:23] - read-write - - - GPIO5_EDGE_LOW - [22:22] - read-write - - - GPIO5_LEVEL_HIGH - [21:21] - read-write - - - GPIO5_LEVEL_LOW - [20:20] - read-write - - - GPIO4_EDGE_HIGH - [19:19] - read-write - - - GPIO4_EDGE_LOW - [18:18] - read-write - - - GPIO4_LEVEL_HIGH - [17:17] - read-write - - - GPIO4_LEVEL_LOW - [16:16] - read-write - - - GPIO3_EDGE_HIGH - [15:15] - read-write - - - GPIO3_EDGE_LOW - [14:14] - read-write - - - GPIO3_LEVEL_HIGH - [13:13] - read-write - - - GPIO3_LEVEL_LOW - [12:12] - read-write - - - GPIO2_EDGE_HIGH - [11:11] - read-write - - - GPIO2_EDGE_LOW - [10:10] - read-write - - - GPIO2_LEVEL_HIGH - [9:9] - read-write - - - GPIO2_LEVEL_LOW - [8:8] - read-write - - - GPIO1_EDGE_HIGH - [7:7] - read-write - - - GPIO1_EDGE_LOW - [6:6] - read-write - - - GPIO1_LEVEL_HIGH - [5:5] - read-write - - - GPIO1_LEVEL_LOW - [4:4] - read-write - - - GPIO0_EDGE_HIGH - [3:3] - read-write - - - GPIO0_EDGE_LOW - [2:2] - read-write - - - GPIO0_LEVEL_HIGH - [1:1] - read-write - - - GPIO0_LEVEL_LOW - [0:0] - read-write - - - - - PROC1_INTF1 - 0x000002ac - Interrupt Force for proc1 - 0x00000000 - - - GPIO15_EDGE_HIGH - [31:31] - read-write - - - GPIO15_EDGE_LOW - [30:30] - read-write - - - GPIO15_LEVEL_HIGH - [29:29] - read-write - - - GPIO15_LEVEL_LOW - [28:28] - read-write - - - GPIO14_EDGE_HIGH - [27:27] - read-write - - - GPIO14_EDGE_LOW - [26:26] - read-write - - - GPIO14_LEVEL_HIGH - [25:25] - read-write - - - GPIO14_LEVEL_LOW - [24:24] - read-write - - - GPIO13_EDGE_HIGH - [23:23] - read-write - - - GPIO13_EDGE_LOW - [22:22] - read-write - - - GPIO13_LEVEL_HIGH - [21:21] - read-write - - - GPIO13_LEVEL_LOW - [20:20] - read-write - - - GPIO12_EDGE_HIGH - [19:19] - read-write - - - GPIO12_EDGE_LOW - [18:18] - read-write - - - GPIO12_LEVEL_HIGH - [17:17] - read-write - - - GPIO12_LEVEL_LOW - [16:16] - read-write - - - GPIO11_EDGE_HIGH - [15:15] - read-write - - - GPIO11_EDGE_LOW - [14:14] - read-write - - - GPIO11_LEVEL_HIGH - [13:13] - read-write - - - GPIO11_LEVEL_LOW - [12:12] - read-write - - - GPIO10_EDGE_HIGH - [11:11] - read-write - - - GPIO10_EDGE_LOW - [10:10] - read-write - - - GPIO10_LEVEL_HIGH - [9:9] - read-write - - - GPIO10_LEVEL_LOW - [8:8] - read-write - - - GPIO9_EDGE_HIGH - [7:7] - read-write - - - GPIO9_EDGE_LOW - [6:6] - read-write - - - GPIO9_LEVEL_HIGH - [5:5] - read-write - - - GPIO9_LEVEL_LOW - [4:4] - read-write - - - GPIO8_EDGE_HIGH - [3:3] - read-write - - - GPIO8_EDGE_LOW - [2:2] - read-write - - - GPIO8_LEVEL_HIGH - [1:1] - read-write - - - GPIO8_LEVEL_LOW - [0:0] - read-write - - - - - PROC1_INTF2 - 0x000002b0 - Interrupt Force for proc1 - 0x00000000 - - - GPIO23_EDGE_HIGH - [31:31] - read-write - - - GPIO23_EDGE_LOW - [30:30] - read-write - - - GPIO23_LEVEL_HIGH - [29:29] - read-write - - - GPIO23_LEVEL_LOW - [28:28] - read-write - - - GPIO22_EDGE_HIGH - [27:27] - read-write - - - GPIO22_EDGE_LOW - [26:26] - read-write - - - GPIO22_LEVEL_HIGH - [25:25] - read-write - - - GPIO22_LEVEL_LOW - [24:24] - read-write - - - GPIO21_EDGE_HIGH - [23:23] - read-write - - - GPIO21_EDGE_LOW - [22:22] - read-write - - - GPIO21_LEVEL_HIGH - [21:21] - read-write - - - GPIO21_LEVEL_LOW - [20:20] - read-write - - - GPIO20_EDGE_HIGH - [19:19] - read-write - - - GPIO20_EDGE_LOW - [18:18] - read-write - - - GPIO20_LEVEL_HIGH - [17:17] - read-write - - - GPIO20_LEVEL_LOW - [16:16] - read-write - - - GPIO19_EDGE_HIGH - [15:15] - read-write - - - GPIO19_EDGE_LOW - [14:14] - read-write - - - GPIO19_LEVEL_HIGH - [13:13] - read-write - - - GPIO19_LEVEL_LOW - [12:12] - read-write - - - GPIO18_EDGE_HIGH - [11:11] - read-write - - - GPIO18_EDGE_LOW - [10:10] - read-write - - - GPIO18_LEVEL_HIGH - [9:9] - read-write - - - GPIO18_LEVEL_LOW - [8:8] - read-write - - - GPIO17_EDGE_HIGH - [7:7] - read-write - - - GPIO17_EDGE_LOW - [6:6] - read-write - - - GPIO17_LEVEL_HIGH - [5:5] - read-write - - - GPIO17_LEVEL_LOW - [4:4] - read-write - - - GPIO16_EDGE_HIGH - [3:3] - read-write - - - GPIO16_EDGE_LOW - [2:2] - read-write - - - GPIO16_LEVEL_HIGH - [1:1] - read-write - - - GPIO16_LEVEL_LOW - [0:0] - read-write - - - - - PROC1_INTF3 - 0x000002b4 - Interrupt Force for proc1 - 0x00000000 - - - GPIO31_EDGE_HIGH - [31:31] - read-write - - - GPIO31_EDGE_LOW - [30:30] - read-write - - - GPIO31_LEVEL_HIGH - [29:29] - read-write - - - GPIO31_LEVEL_LOW - [28:28] - read-write - - - GPIO30_EDGE_HIGH - [27:27] - read-write - - - GPIO30_EDGE_LOW - [26:26] - read-write - - - GPIO30_LEVEL_HIGH - [25:25] - read-write - - - GPIO30_LEVEL_LOW - [24:24] - read-write - - - GPIO29_EDGE_HIGH - [23:23] - read-write - - - GPIO29_EDGE_LOW - [22:22] - read-write - - - GPIO29_LEVEL_HIGH - [21:21] - read-write - - - GPIO29_LEVEL_LOW - [20:20] - read-write - - - GPIO28_EDGE_HIGH - [19:19] - read-write - - - GPIO28_EDGE_LOW - [18:18] - read-write - - - GPIO28_LEVEL_HIGH - [17:17] - read-write - - - GPIO28_LEVEL_LOW - [16:16] - read-write - - - GPIO27_EDGE_HIGH - [15:15] - read-write - - - GPIO27_EDGE_LOW - [14:14] - read-write - - - GPIO27_LEVEL_HIGH - [13:13] - read-write - - - GPIO27_LEVEL_LOW - [12:12] - read-write - - - GPIO26_EDGE_HIGH - [11:11] - read-write - - - GPIO26_EDGE_LOW - [10:10] - read-write - - - GPIO26_LEVEL_HIGH - [9:9] - read-write - - - GPIO26_LEVEL_LOW - [8:8] - read-write - - - GPIO25_EDGE_HIGH - [7:7] - read-write - - - GPIO25_EDGE_LOW - [6:6] - read-write - - - GPIO25_LEVEL_HIGH - [5:5] - read-write - - - GPIO25_LEVEL_LOW - [4:4] - read-write - - - GPIO24_EDGE_HIGH - [3:3] - read-write - - - GPIO24_EDGE_LOW - [2:2] - read-write - - - GPIO24_LEVEL_HIGH - [1:1] - read-write - - - GPIO24_LEVEL_LOW - [0:0] - read-write - - - - - PROC1_INTF4 - 0x000002b8 - Interrupt Force for proc1 - 0x00000000 - - - GPIO39_EDGE_HIGH - [31:31] - read-write - - - GPIO39_EDGE_LOW - [30:30] - read-write - - - GPIO39_LEVEL_HIGH - [29:29] - read-write - - - GPIO39_LEVEL_LOW - [28:28] - read-write - - - GPIO38_EDGE_HIGH - [27:27] - read-write - - - GPIO38_EDGE_LOW - [26:26] - read-write - - - GPIO38_LEVEL_HIGH - [25:25] - read-write - - - GPIO38_LEVEL_LOW - [24:24] - read-write - - - GPIO37_EDGE_HIGH - [23:23] - read-write - - - GPIO37_EDGE_LOW - [22:22] - read-write - - - GPIO37_LEVEL_HIGH - [21:21] - read-write - - - GPIO37_LEVEL_LOW - [20:20] - read-write - - - GPIO36_EDGE_HIGH - [19:19] - read-write - - - GPIO36_EDGE_LOW - [18:18] - read-write - - - GPIO36_LEVEL_HIGH - [17:17] - read-write - - - GPIO36_LEVEL_LOW - [16:16] - read-write - - - GPIO35_EDGE_HIGH - [15:15] - read-write - - - GPIO35_EDGE_LOW - [14:14] - read-write - - - GPIO35_LEVEL_HIGH - [13:13] - read-write - - - GPIO35_LEVEL_LOW - [12:12] - read-write - - - GPIO34_EDGE_HIGH - [11:11] - read-write - - - GPIO34_EDGE_LOW - [10:10] - read-write - - - GPIO34_LEVEL_HIGH - [9:9] - read-write - - - GPIO34_LEVEL_LOW - [8:8] - read-write - - - GPIO33_EDGE_HIGH - [7:7] - read-write - - - GPIO33_EDGE_LOW - [6:6] - read-write - - - GPIO33_LEVEL_HIGH - [5:5] - read-write - - - GPIO33_LEVEL_LOW - [4:4] - read-write - - - GPIO32_EDGE_HIGH - [3:3] - read-write - - - GPIO32_EDGE_LOW - [2:2] - read-write - - - GPIO32_LEVEL_HIGH - [1:1] - read-write - - - GPIO32_LEVEL_LOW - [0:0] - read-write - - - - - PROC1_INTF5 - 0x000002bc - Interrupt Force for proc1 - 0x00000000 - - - GPIO47_EDGE_HIGH - [31:31] - read-write - - - GPIO47_EDGE_LOW - [30:30] - read-write - - - GPIO47_LEVEL_HIGH - [29:29] - read-write - - - GPIO47_LEVEL_LOW - [28:28] - read-write - - - GPIO46_EDGE_HIGH - [27:27] - read-write - - - GPIO46_EDGE_LOW - [26:26] - read-write - - - GPIO46_LEVEL_HIGH - [25:25] - read-write - - - GPIO46_LEVEL_LOW - [24:24] - read-write - - - GPIO45_EDGE_HIGH - [23:23] - read-write - - - GPIO45_EDGE_LOW - [22:22] - read-write - - - GPIO45_LEVEL_HIGH - [21:21] - read-write - - - GPIO45_LEVEL_LOW - [20:20] - read-write - - - GPIO44_EDGE_HIGH - [19:19] - read-write - - - GPIO44_EDGE_LOW - [18:18] - read-write - - - GPIO44_LEVEL_HIGH - [17:17] - read-write - - - GPIO44_LEVEL_LOW - [16:16] - read-write - - - GPIO43_EDGE_HIGH - [15:15] - read-write - - - GPIO43_EDGE_LOW - [14:14] - read-write - - - GPIO43_LEVEL_HIGH - [13:13] - read-write - - - GPIO43_LEVEL_LOW - [12:12] - read-write - - - GPIO42_EDGE_HIGH - [11:11] - read-write - - - GPIO42_EDGE_LOW - [10:10] - read-write - - - GPIO42_LEVEL_HIGH - [9:9] - read-write - - - GPIO42_LEVEL_LOW - [8:8] - read-write - - - GPIO41_EDGE_HIGH - [7:7] - read-write - - - GPIO41_EDGE_LOW - [6:6] - read-write - - - GPIO41_LEVEL_HIGH - [5:5] - read-write - - - GPIO41_LEVEL_LOW - [4:4] - read-write - - - GPIO40_EDGE_HIGH - [3:3] - read-write - - - GPIO40_EDGE_LOW - [2:2] - read-write - - - GPIO40_LEVEL_HIGH - [1:1] - read-write - - - GPIO40_LEVEL_LOW - [0:0] - read-write - - - - - PROC1_INTS0 - 0x000002c0 - Interrupt status after masking & forcing for proc1 - 0x00000000 - - - GPIO7_EDGE_HIGH - [31:31] - read-only - - - GPIO7_EDGE_LOW - [30:30] - read-only - - - GPIO7_LEVEL_HIGH - [29:29] - read-only - - - GPIO7_LEVEL_LOW - [28:28] - read-only - - - GPIO6_EDGE_HIGH - [27:27] - read-only - - - GPIO6_EDGE_LOW - [26:26] - read-only - - - GPIO6_LEVEL_HIGH - [25:25] - read-only - - - GPIO6_LEVEL_LOW - [24:24] - read-only - - - GPIO5_EDGE_HIGH - [23:23] - read-only - - - GPIO5_EDGE_LOW - [22:22] - read-only - - - GPIO5_LEVEL_HIGH - [21:21] - read-only - - - GPIO5_LEVEL_LOW - [20:20] - read-only - - - GPIO4_EDGE_HIGH - [19:19] - read-only - - - GPIO4_EDGE_LOW - [18:18] - read-only - - - GPIO4_LEVEL_HIGH - [17:17] - read-only - - - GPIO4_LEVEL_LOW - [16:16] - read-only - - - GPIO3_EDGE_HIGH - [15:15] - read-only - - - GPIO3_EDGE_LOW - [14:14] - read-only - - - GPIO3_LEVEL_HIGH - [13:13] - read-only - - - GPIO3_LEVEL_LOW - [12:12] - read-only - - - GPIO2_EDGE_HIGH - [11:11] - read-only - - - GPIO2_EDGE_LOW - [10:10] - read-only - - - GPIO2_LEVEL_HIGH - [9:9] - read-only - - - GPIO2_LEVEL_LOW - [8:8] - read-only - - - GPIO1_EDGE_HIGH - [7:7] - read-only - - - GPIO1_EDGE_LOW - [6:6] - read-only - - - GPIO1_LEVEL_HIGH - [5:5] - read-only - - - GPIO1_LEVEL_LOW - [4:4] - read-only - - - GPIO0_EDGE_HIGH - [3:3] - read-only - - - GPIO0_EDGE_LOW - [2:2] - read-only - - - GPIO0_LEVEL_HIGH - [1:1] - read-only - - - GPIO0_LEVEL_LOW - [0:0] - read-only - - - - - PROC1_INTS1 - 0x000002c4 - Interrupt status after masking & forcing for proc1 - 0x00000000 - - - GPIO15_EDGE_HIGH - [31:31] - read-only - - - GPIO15_EDGE_LOW - [30:30] - read-only - - - GPIO15_LEVEL_HIGH - [29:29] - read-only - - - GPIO15_LEVEL_LOW - [28:28] - read-only - - - GPIO14_EDGE_HIGH - [27:27] - read-only - - - GPIO14_EDGE_LOW - [26:26] - read-only - - - GPIO14_LEVEL_HIGH - [25:25] - read-only - - - GPIO14_LEVEL_LOW - [24:24] - read-only - - - GPIO13_EDGE_HIGH - [23:23] - read-only - - - GPIO13_EDGE_LOW - [22:22] - read-only - - - GPIO13_LEVEL_HIGH - [21:21] - read-only - - - GPIO13_LEVEL_LOW - [20:20] - read-only - - - GPIO12_EDGE_HIGH - [19:19] - read-only - - - GPIO12_EDGE_LOW - [18:18] - read-only - - - GPIO12_LEVEL_HIGH - [17:17] - read-only - - - GPIO12_LEVEL_LOW - [16:16] - read-only - - - GPIO11_EDGE_HIGH - [15:15] - read-only - - - GPIO11_EDGE_LOW - [14:14] - read-only - - - GPIO11_LEVEL_HIGH - [13:13] - read-only - - - GPIO11_LEVEL_LOW - [12:12] - read-only - - - GPIO10_EDGE_HIGH - [11:11] - read-only - - - GPIO10_EDGE_LOW - [10:10] - read-only - - - GPIO10_LEVEL_HIGH - [9:9] - read-only - - - GPIO10_LEVEL_LOW - [8:8] - read-only - - - GPIO9_EDGE_HIGH - [7:7] - read-only - - - GPIO9_EDGE_LOW - [6:6] - read-only - - - GPIO9_LEVEL_HIGH - [5:5] - read-only - - - GPIO9_LEVEL_LOW - [4:4] - read-only - - - GPIO8_EDGE_HIGH - [3:3] - read-only - - - GPIO8_EDGE_LOW - [2:2] - read-only - - - GPIO8_LEVEL_HIGH - [1:1] - read-only - - - GPIO8_LEVEL_LOW - [0:0] - read-only - - - - - PROC1_INTS2 - 0x000002c8 - Interrupt status after masking & forcing for proc1 - 0x00000000 - - - GPIO23_EDGE_HIGH - [31:31] - read-only - - - GPIO23_EDGE_LOW - [30:30] - read-only - - - GPIO23_LEVEL_HIGH - [29:29] - read-only - - - GPIO23_LEVEL_LOW - [28:28] - read-only - - - GPIO22_EDGE_HIGH - [27:27] - read-only - - - GPIO22_EDGE_LOW - [26:26] - read-only - - - GPIO22_LEVEL_HIGH - [25:25] - read-only - - - GPIO22_LEVEL_LOW - [24:24] - read-only - - - GPIO21_EDGE_HIGH - [23:23] - read-only - - - GPIO21_EDGE_LOW - [22:22] - read-only - - - GPIO21_LEVEL_HIGH - [21:21] - read-only - - - GPIO21_LEVEL_LOW - [20:20] - read-only - - - GPIO20_EDGE_HIGH - [19:19] - read-only - - - GPIO20_EDGE_LOW - [18:18] - read-only - - - GPIO20_LEVEL_HIGH - [17:17] - read-only - - - GPIO20_LEVEL_LOW - [16:16] - read-only - - - GPIO19_EDGE_HIGH - [15:15] - read-only - - - GPIO19_EDGE_LOW - [14:14] - read-only - - - GPIO19_LEVEL_HIGH - [13:13] - read-only - - - GPIO19_LEVEL_LOW - [12:12] - read-only - - - GPIO18_EDGE_HIGH - [11:11] - read-only - - - GPIO18_EDGE_LOW - [10:10] - read-only - - - GPIO18_LEVEL_HIGH - [9:9] - read-only - - - GPIO18_LEVEL_LOW - [8:8] - read-only - - - GPIO17_EDGE_HIGH - [7:7] - read-only - - - GPIO17_EDGE_LOW - [6:6] - read-only - - - GPIO17_LEVEL_HIGH - [5:5] - read-only - - - GPIO17_LEVEL_LOW - [4:4] - read-only - - - GPIO16_EDGE_HIGH - [3:3] - read-only - - - GPIO16_EDGE_LOW - [2:2] - read-only - - - GPIO16_LEVEL_HIGH - [1:1] - read-only - - - GPIO16_LEVEL_LOW - [0:0] - read-only - - - - - PROC1_INTS3 - 0x000002cc - Interrupt status after masking & forcing for proc1 - 0x00000000 - - - GPIO31_EDGE_HIGH - [31:31] - read-only - - - GPIO31_EDGE_LOW - [30:30] - read-only - - - GPIO31_LEVEL_HIGH - [29:29] - read-only - - - GPIO31_LEVEL_LOW - [28:28] - read-only - - - GPIO30_EDGE_HIGH - [27:27] - read-only - - - GPIO30_EDGE_LOW - [26:26] - read-only - - - GPIO30_LEVEL_HIGH - [25:25] - read-only - - - GPIO30_LEVEL_LOW - [24:24] - read-only - - - GPIO29_EDGE_HIGH - [23:23] - read-only - - - GPIO29_EDGE_LOW - [22:22] - read-only - - - GPIO29_LEVEL_HIGH - [21:21] - read-only - - - GPIO29_LEVEL_LOW - [20:20] - read-only - - - GPIO28_EDGE_HIGH - [19:19] - read-only - - - GPIO28_EDGE_LOW - [18:18] - read-only - - - GPIO28_LEVEL_HIGH - [17:17] - read-only - - - GPIO28_LEVEL_LOW - [16:16] - read-only - - - GPIO27_EDGE_HIGH - [15:15] - read-only - - - GPIO27_EDGE_LOW - [14:14] - read-only - - - GPIO27_LEVEL_HIGH - [13:13] - read-only - - - GPIO27_LEVEL_LOW - [12:12] - read-only - - - GPIO26_EDGE_HIGH - [11:11] - read-only - - - GPIO26_EDGE_LOW - [10:10] - read-only - - - GPIO26_LEVEL_HIGH - [9:9] - read-only - - - GPIO26_LEVEL_LOW - [8:8] - read-only - - - GPIO25_EDGE_HIGH - [7:7] - read-only - - - GPIO25_EDGE_LOW - [6:6] - read-only - - - GPIO25_LEVEL_HIGH - [5:5] - read-only - - - GPIO25_LEVEL_LOW - [4:4] - read-only - - - GPIO24_EDGE_HIGH - [3:3] - read-only - - - GPIO24_EDGE_LOW - [2:2] - read-only - - - GPIO24_LEVEL_HIGH - [1:1] - read-only - - - GPIO24_LEVEL_LOW - [0:0] - read-only - - - - - PROC1_INTS4 - 0x000002d0 - Interrupt status after masking & forcing for proc1 - 0x00000000 - - - GPIO39_EDGE_HIGH - [31:31] - read-only - - - GPIO39_EDGE_LOW - [30:30] - read-only - - - GPIO39_LEVEL_HIGH - [29:29] - read-only - - - GPIO39_LEVEL_LOW - [28:28] - read-only - - - GPIO38_EDGE_HIGH - [27:27] - read-only - - - GPIO38_EDGE_LOW - [26:26] - read-only - - - GPIO38_LEVEL_HIGH - [25:25] - read-only - - - GPIO38_LEVEL_LOW - [24:24] - read-only - - - GPIO37_EDGE_HIGH - [23:23] - read-only - - - GPIO37_EDGE_LOW - [22:22] - read-only - - - GPIO37_LEVEL_HIGH - [21:21] - read-only - - - GPIO37_LEVEL_LOW - [20:20] - read-only - - - GPIO36_EDGE_HIGH - [19:19] - read-only - - - GPIO36_EDGE_LOW - [18:18] - read-only - - - GPIO36_LEVEL_HIGH - [17:17] - read-only - - - GPIO36_LEVEL_LOW - [16:16] - read-only - - - GPIO35_EDGE_HIGH - [15:15] - read-only - - - GPIO35_EDGE_LOW - [14:14] - read-only - - - GPIO35_LEVEL_HIGH - [13:13] - read-only - - - GPIO35_LEVEL_LOW - [12:12] - read-only - - - GPIO34_EDGE_HIGH - [11:11] - read-only - - - GPIO34_EDGE_LOW - [10:10] - read-only - - - GPIO34_LEVEL_HIGH - [9:9] - read-only - - - GPIO34_LEVEL_LOW - [8:8] - read-only - - - GPIO33_EDGE_HIGH - [7:7] - read-only - - - GPIO33_EDGE_LOW - [6:6] - read-only - - - GPIO33_LEVEL_HIGH - [5:5] - read-only - - - GPIO33_LEVEL_LOW - [4:4] - read-only - - - GPIO32_EDGE_HIGH - [3:3] - read-only - - - GPIO32_EDGE_LOW - [2:2] - read-only - - - GPIO32_LEVEL_HIGH - [1:1] - read-only - - - GPIO32_LEVEL_LOW - [0:0] - read-only - - - - - PROC1_INTS5 - 0x000002d4 - Interrupt status after masking & forcing for proc1 - 0x00000000 - - - GPIO47_EDGE_HIGH - [31:31] - read-only - - - GPIO47_EDGE_LOW - [30:30] - read-only - - - GPIO47_LEVEL_HIGH - [29:29] - read-only - - - GPIO47_LEVEL_LOW - [28:28] - read-only - - - GPIO46_EDGE_HIGH - [27:27] - read-only - - - GPIO46_EDGE_LOW - [26:26] - read-only - - - GPIO46_LEVEL_HIGH - [25:25] - read-only - - - GPIO46_LEVEL_LOW - [24:24] - read-only - - - GPIO45_EDGE_HIGH - [23:23] - read-only - - - GPIO45_EDGE_LOW - [22:22] - read-only - - - GPIO45_LEVEL_HIGH - [21:21] - read-only - - - GPIO45_LEVEL_LOW - [20:20] - read-only - - - GPIO44_EDGE_HIGH - [19:19] - read-only - - - GPIO44_EDGE_LOW - [18:18] - read-only - - - GPIO44_LEVEL_HIGH - [17:17] - read-only - - - GPIO44_LEVEL_LOW - [16:16] - read-only - - - GPIO43_EDGE_HIGH - [15:15] - read-only - - - GPIO43_EDGE_LOW - [14:14] - read-only - - - GPIO43_LEVEL_HIGH - [13:13] - read-only - - - GPIO43_LEVEL_LOW - [12:12] - read-only - - - GPIO42_EDGE_HIGH - [11:11] - read-only - - - GPIO42_EDGE_LOW - [10:10] - read-only - - - GPIO42_LEVEL_HIGH - [9:9] - read-only - - - GPIO42_LEVEL_LOW - [8:8] - read-only - - - GPIO41_EDGE_HIGH - [7:7] - read-only - - - GPIO41_EDGE_LOW - [6:6] - read-only - - - GPIO41_LEVEL_HIGH - [5:5] - read-only - - - GPIO41_LEVEL_LOW - [4:4] - read-only - - - GPIO40_EDGE_HIGH - [3:3] - read-only - - - GPIO40_EDGE_LOW - [2:2] - read-only - - - GPIO40_LEVEL_HIGH - [1:1] - read-only - - - GPIO40_LEVEL_LOW - [0:0] - read-only - - - - - DORMANT_WAKE_INTE0 - 0x000002d8 - Interrupt Enable for dormant_wake - 0x00000000 - - - GPIO7_EDGE_HIGH - [31:31] - read-write - - - GPIO7_EDGE_LOW - [30:30] - read-write - - - GPIO7_LEVEL_HIGH - [29:29] - read-write - - - GPIO7_LEVEL_LOW - [28:28] - read-write - - - GPIO6_EDGE_HIGH - [27:27] - read-write - - - GPIO6_EDGE_LOW - [26:26] - read-write - - - GPIO6_LEVEL_HIGH - [25:25] - read-write - - - GPIO6_LEVEL_LOW - [24:24] - read-write - - - GPIO5_EDGE_HIGH - [23:23] - read-write - - - GPIO5_EDGE_LOW - [22:22] - read-write - - - GPIO5_LEVEL_HIGH - [21:21] - read-write - - - GPIO5_LEVEL_LOW - [20:20] - read-write - - - GPIO4_EDGE_HIGH - [19:19] - read-write - - - GPIO4_EDGE_LOW - [18:18] - read-write - - - GPIO4_LEVEL_HIGH - [17:17] - read-write - - - GPIO4_LEVEL_LOW - [16:16] - read-write - - - GPIO3_EDGE_HIGH - [15:15] - read-write - - - GPIO3_EDGE_LOW - [14:14] - read-write - - - GPIO3_LEVEL_HIGH - [13:13] - read-write - - - GPIO3_LEVEL_LOW - [12:12] - read-write - - - GPIO2_EDGE_HIGH - [11:11] - read-write - - - GPIO2_EDGE_LOW - [10:10] - read-write - - - GPIO2_LEVEL_HIGH - [9:9] - read-write - - - GPIO2_LEVEL_LOW - [8:8] - read-write - - - GPIO1_EDGE_HIGH - [7:7] - read-write - - - GPIO1_EDGE_LOW - [6:6] - read-write - - - GPIO1_LEVEL_HIGH - [5:5] - read-write - - - GPIO1_LEVEL_LOW - [4:4] - read-write - - - GPIO0_EDGE_HIGH - [3:3] - read-write - - - GPIO0_EDGE_LOW - [2:2] - read-write - - - GPIO0_LEVEL_HIGH - [1:1] - read-write - - - GPIO0_LEVEL_LOW - [0:0] - read-write - - - - - DORMANT_WAKE_INTE1 - 0x000002dc - Interrupt Enable for dormant_wake - 0x00000000 - - - GPIO15_EDGE_HIGH - [31:31] - read-write - - - GPIO15_EDGE_LOW - [30:30] - read-write - - - GPIO15_LEVEL_HIGH - [29:29] - read-write - - - GPIO15_LEVEL_LOW - [28:28] - read-write - - - GPIO14_EDGE_HIGH - [27:27] - read-write - - - GPIO14_EDGE_LOW - [26:26] - read-write - - - GPIO14_LEVEL_HIGH - [25:25] - read-write - - - GPIO14_LEVEL_LOW - [24:24] - read-write - - - GPIO13_EDGE_HIGH - [23:23] - read-write - - - GPIO13_EDGE_LOW - [22:22] - read-write - - - GPIO13_LEVEL_HIGH - [21:21] - read-write - - - GPIO13_LEVEL_LOW - [20:20] - read-write - - - GPIO12_EDGE_HIGH - [19:19] - read-write - - - GPIO12_EDGE_LOW - [18:18] - read-write - - - GPIO12_LEVEL_HIGH - [17:17] - read-write - - - GPIO12_LEVEL_LOW - [16:16] - read-write - - - GPIO11_EDGE_HIGH - [15:15] - read-write - - - GPIO11_EDGE_LOW - [14:14] - read-write - - - GPIO11_LEVEL_HIGH - [13:13] - read-write - - - GPIO11_LEVEL_LOW - [12:12] - read-write - - - GPIO10_EDGE_HIGH - [11:11] - read-write - - - GPIO10_EDGE_LOW - [10:10] - read-write - - - GPIO10_LEVEL_HIGH - [9:9] - read-write - - - GPIO10_LEVEL_LOW - [8:8] - read-write - - - GPIO9_EDGE_HIGH - [7:7] - read-write - - - GPIO9_EDGE_LOW - [6:6] - read-write - - - GPIO9_LEVEL_HIGH - [5:5] - read-write - - - GPIO9_LEVEL_LOW - [4:4] - read-write - - - GPIO8_EDGE_HIGH - [3:3] - read-write - - - GPIO8_EDGE_LOW - [2:2] - read-write - - - GPIO8_LEVEL_HIGH - [1:1] - read-write - - - GPIO8_LEVEL_LOW - [0:0] - read-write - - - - - DORMANT_WAKE_INTE2 - 0x000002e0 - Interrupt Enable for dormant_wake - 0x00000000 - - - GPIO23_EDGE_HIGH - [31:31] - read-write - - - GPIO23_EDGE_LOW - [30:30] - read-write - - - GPIO23_LEVEL_HIGH - [29:29] - read-write - - - GPIO23_LEVEL_LOW - [28:28] - read-write - - - GPIO22_EDGE_HIGH - [27:27] - read-write - - - GPIO22_EDGE_LOW - [26:26] - read-write - - - GPIO22_LEVEL_HIGH - [25:25] - read-write - - - GPIO22_LEVEL_LOW - [24:24] - read-write - - - GPIO21_EDGE_HIGH - [23:23] - read-write - - - GPIO21_EDGE_LOW - [22:22] - read-write - - - GPIO21_LEVEL_HIGH - [21:21] - read-write - - - GPIO21_LEVEL_LOW - [20:20] - read-write - - - GPIO20_EDGE_HIGH - [19:19] - read-write - - - GPIO20_EDGE_LOW - [18:18] - read-write - - - GPIO20_LEVEL_HIGH - [17:17] - read-write - - - GPIO20_LEVEL_LOW - [16:16] - read-write - - - GPIO19_EDGE_HIGH - [15:15] - read-write - - - GPIO19_EDGE_LOW - [14:14] - read-write - - - GPIO19_LEVEL_HIGH - [13:13] - read-write - - - GPIO19_LEVEL_LOW - [12:12] - read-write - - - GPIO18_EDGE_HIGH - [11:11] - read-write - - - GPIO18_EDGE_LOW - [10:10] - read-write - - - GPIO18_LEVEL_HIGH - [9:9] - read-write - - - GPIO18_LEVEL_LOW - [8:8] - read-write - - - GPIO17_EDGE_HIGH - [7:7] - read-write - - - GPIO17_EDGE_LOW - [6:6] - read-write - - - GPIO17_LEVEL_HIGH - [5:5] - read-write - - - GPIO17_LEVEL_LOW - [4:4] - read-write - - - GPIO16_EDGE_HIGH - [3:3] - read-write - - - GPIO16_EDGE_LOW - [2:2] - read-write - - - GPIO16_LEVEL_HIGH - [1:1] - read-write - - - GPIO16_LEVEL_LOW - [0:0] - read-write - - - - - DORMANT_WAKE_INTE3 - 0x000002e4 - Interrupt Enable for dormant_wake - 0x00000000 - - - GPIO31_EDGE_HIGH - [31:31] - read-write - - - GPIO31_EDGE_LOW - [30:30] - read-write - - - GPIO31_LEVEL_HIGH - [29:29] - read-write - - - GPIO31_LEVEL_LOW - [28:28] - read-write - - - GPIO30_EDGE_HIGH - [27:27] - read-write - - - GPIO30_EDGE_LOW - [26:26] - read-write - - - GPIO30_LEVEL_HIGH - [25:25] - read-write - - - GPIO30_LEVEL_LOW - [24:24] - read-write - - - GPIO29_EDGE_HIGH - [23:23] - read-write - - - GPIO29_EDGE_LOW - [22:22] - read-write - - - GPIO29_LEVEL_HIGH - [21:21] - read-write - - - GPIO29_LEVEL_LOW - [20:20] - read-write - - - GPIO28_EDGE_HIGH - [19:19] - read-write - - - GPIO28_EDGE_LOW - [18:18] - read-write - - - GPIO28_LEVEL_HIGH - [17:17] - read-write - - - GPIO28_LEVEL_LOW - [16:16] - read-write - - - GPIO27_EDGE_HIGH - [15:15] - read-write - - - GPIO27_EDGE_LOW - [14:14] - read-write - - - GPIO27_LEVEL_HIGH - [13:13] - read-write - - - GPIO27_LEVEL_LOW - [12:12] - read-write - - - GPIO26_EDGE_HIGH - [11:11] - read-write - - - GPIO26_EDGE_LOW - [10:10] - read-write - - - GPIO26_LEVEL_HIGH - [9:9] - read-write - - - GPIO26_LEVEL_LOW - [8:8] - read-write - - - GPIO25_EDGE_HIGH - [7:7] - read-write - - - GPIO25_EDGE_LOW - [6:6] - read-write - - - GPIO25_LEVEL_HIGH - [5:5] - read-write - - - GPIO25_LEVEL_LOW - [4:4] - read-write - - - GPIO24_EDGE_HIGH - [3:3] - read-write - - - GPIO24_EDGE_LOW - [2:2] - read-write - - - GPIO24_LEVEL_HIGH - [1:1] - read-write - - - GPIO24_LEVEL_LOW - [0:0] - read-write - - - - - DORMANT_WAKE_INTE4 - 0x000002e8 - Interrupt Enable for dormant_wake - 0x00000000 - - - GPIO39_EDGE_HIGH - [31:31] - read-write - - - GPIO39_EDGE_LOW - [30:30] - read-write - - - GPIO39_LEVEL_HIGH - [29:29] - read-write - - - GPIO39_LEVEL_LOW - [28:28] - read-write - - - GPIO38_EDGE_HIGH - [27:27] - read-write - - - GPIO38_EDGE_LOW - [26:26] - read-write - - - GPIO38_LEVEL_HIGH - [25:25] - read-write - - - GPIO38_LEVEL_LOW - [24:24] - read-write - - - GPIO37_EDGE_HIGH - [23:23] - read-write - - - GPIO37_EDGE_LOW - [22:22] - read-write - - - GPIO37_LEVEL_HIGH - [21:21] - read-write - - - GPIO37_LEVEL_LOW - [20:20] - read-write - - - GPIO36_EDGE_HIGH - [19:19] - read-write - - - GPIO36_EDGE_LOW - [18:18] - read-write - - - GPIO36_LEVEL_HIGH - [17:17] - read-write - - - GPIO36_LEVEL_LOW - [16:16] - read-write - - - GPIO35_EDGE_HIGH - [15:15] - read-write - - - GPIO35_EDGE_LOW - [14:14] - read-write - - - GPIO35_LEVEL_HIGH - [13:13] - read-write - - - GPIO35_LEVEL_LOW - [12:12] - read-write - - - GPIO34_EDGE_HIGH - [11:11] - read-write - - - GPIO34_EDGE_LOW - [10:10] - read-write - - - GPIO34_LEVEL_HIGH - [9:9] - read-write - - - GPIO34_LEVEL_LOW - [8:8] - read-write - - - GPIO33_EDGE_HIGH - [7:7] - read-write - - - GPIO33_EDGE_LOW - [6:6] - read-write - - - GPIO33_LEVEL_HIGH - [5:5] - read-write - - - GPIO33_LEVEL_LOW - [4:4] - read-write - - - GPIO32_EDGE_HIGH - [3:3] - read-write - - - GPIO32_EDGE_LOW - [2:2] - read-write - - - GPIO32_LEVEL_HIGH - [1:1] - read-write - - - GPIO32_LEVEL_LOW - [0:0] - read-write - - - - - DORMANT_WAKE_INTE5 - 0x000002ec - Interrupt Enable for dormant_wake - 0x00000000 - - - GPIO47_EDGE_HIGH - [31:31] - read-write - - - GPIO47_EDGE_LOW - [30:30] - read-write - - - GPIO47_LEVEL_HIGH - [29:29] - read-write - - - GPIO47_LEVEL_LOW - [28:28] - read-write - - - GPIO46_EDGE_HIGH - [27:27] - read-write - - - GPIO46_EDGE_LOW - [26:26] - read-write - - - GPIO46_LEVEL_HIGH - [25:25] - read-write - - - GPIO46_LEVEL_LOW - [24:24] - read-write - - - GPIO45_EDGE_HIGH - [23:23] - read-write - - - GPIO45_EDGE_LOW - [22:22] - read-write - - - GPIO45_LEVEL_HIGH - [21:21] - read-write - - - GPIO45_LEVEL_LOW - [20:20] - read-write - - - GPIO44_EDGE_HIGH - [19:19] - read-write - - - GPIO44_EDGE_LOW - [18:18] - read-write - - - GPIO44_LEVEL_HIGH - [17:17] - read-write - - - GPIO44_LEVEL_LOW - [16:16] - read-write - - - GPIO43_EDGE_HIGH - [15:15] - read-write - - - GPIO43_EDGE_LOW - [14:14] - read-write - - - GPIO43_LEVEL_HIGH - [13:13] - read-write - - - GPIO43_LEVEL_LOW - [12:12] - read-write - - - GPIO42_EDGE_HIGH - [11:11] - read-write - - - GPIO42_EDGE_LOW - [10:10] - read-write - - - GPIO42_LEVEL_HIGH - [9:9] - read-write - - - GPIO42_LEVEL_LOW - [8:8] - read-write - - - GPIO41_EDGE_HIGH - [7:7] - read-write - - - GPIO41_EDGE_LOW - [6:6] - read-write - - - GPIO41_LEVEL_HIGH - [5:5] - read-write - - - GPIO41_LEVEL_LOW - [4:4] - read-write - - - GPIO40_EDGE_HIGH - [3:3] - read-write - - - GPIO40_EDGE_LOW - [2:2] - read-write - - - GPIO40_LEVEL_HIGH - [1:1] - read-write - - - GPIO40_LEVEL_LOW - [0:0] - read-write - - - - - DORMANT_WAKE_INTF0 - 0x000002f0 - Interrupt Force for dormant_wake - 0x00000000 - - - GPIO7_EDGE_HIGH - [31:31] - read-write - - - GPIO7_EDGE_LOW - [30:30] - read-write - - - GPIO7_LEVEL_HIGH - [29:29] - read-write - - - GPIO7_LEVEL_LOW - [28:28] - read-write - - - GPIO6_EDGE_HIGH - [27:27] - read-write - - - GPIO6_EDGE_LOW - [26:26] - read-write - - - GPIO6_LEVEL_HIGH - [25:25] - read-write - - - GPIO6_LEVEL_LOW - [24:24] - read-write - - - GPIO5_EDGE_HIGH - [23:23] - read-write - - - GPIO5_EDGE_LOW - [22:22] - read-write - - - GPIO5_LEVEL_HIGH - [21:21] - read-write - - - GPIO5_LEVEL_LOW - [20:20] - read-write - - - GPIO4_EDGE_HIGH - [19:19] - read-write - - - GPIO4_EDGE_LOW - [18:18] - read-write - - - GPIO4_LEVEL_HIGH - [17:17] - read-write - - - GPIO4_LEVEL_LOW - [16:16] - read-write - - - GPIO3_EDGE_HIGH - [15:15] - read-write - - - GPIO3_EDGE_LOW - [14:14] - read-write - - - GPIO3_LEVEL_HIGH - [13:13] - read-write - - - GPIO3_LEVEL_LOW - [12:12] - read-write - - - GPIO2_EDGE_HIGH - [11:11] - read-write - - - GPIO2_EDGE_LOW - [10:10] - read-write - - - GPIO2_LEVEL_HIGH - [9:9] - read-write - - - GPIO2_LEVEL_LOW - [8:8] - read-write - - - GPIO1_EDGE_HIGH - [7:7] - read-write - - - GPIO1_EDGE_LOW - [6:6] - read-write - - - GPIO1_LEVEL_HIGH - [5:5] - read-write - - - GPIO1_LEVEL_LOW - [4:4] - read-write - - - GPIO0_EDGE_HIGH - [3:3] - read-write - - - GPIO0_EDGE_LOW - [2:2] - read-write - - - GPIO0_LEVEL_HIGH - [1:1] - read-write - - - GPIO0_LEVEL_LOW - [0:0] - read-write - - - - - DORMANT_WAKE_INTF1 - 0x000002f4 - Interrupt Force for dormant_wake - 0x00000000 - - - GPIO15_EDGE_HIGH - [31:31] - read-write - - - GPIO15_EDGE_LOW - [30:30] - read-write - - - GPIO15_LEVEL_HIGH - [29:29] - read-write - - - GPIO15_LEVEL_LOW - [28:28] - read-write - - - GPIO14_EDGE_HIGH - [27:27] - read-write - - - GPIO14_EDGE_LOW - [26:26] - read-write - - - GPIO14_LEVEL_HIGH - [25:25] - read-write - - - GPIO14_LEVEL_LOW - [24:24] - read-write - - - GPIO13_EDGE_HIGH - [23:23] - read-write - - - GPIO13_EDGE_LOW - [22:22] - read-write - - - GPIO13_LEVEL_HIGH - [21:21] - read-write - - - GPIO13_LEVEL_LOW - [20:20] - read-write - - - GPIO12_EDGE_HIGH - [19:19] - read-write - - - GPIO12_EDGE_LOW - [18:18] - read-write - - - GPIO12_LEVEL_HIGH - [17:17] - read-write - - - GPIO12_LEVEL_LOW - [16:16] - read-write - - - GPIO11_EDGE_HIGH - [15:15] - read-write - - - GPIO11_EDGE_LOW - [14:14] - read-write - - - GPIO11_LEVEL_HIGH - [13:13] - read-write - - - GPIO11_LEVEL_LOW - [12:12] - read-write - - - GPIO10_EDGE_HIGH - [11:11] - read-write - - - GPIO10_EDGE_LOW - [10:10] - read-write - - - GPIO10_LEVEL_HIGH - [9:9] - read-write - - - GPIO10_LEVEL_LOW - [8:8] - read-write - - - GPIO9_EDGE_HIGH - [7:7] - read-write - - - GPIO9_EDGE_LOW - [6:6] - read-write - - - GPIO9_LEVEL_HIGH - [5:5] - read-write - - - GPIO9_LEVEL_LOW - [4:4] - read-write - - - GPIO8_EDGE_HIGH - [3:3] - read-write - - - GPIO8_EDGE_LOW - [2:2] - read-write - - - GPIO8_LEVEL_HIGH - [1:1] - read-write - - - GPIO8_LEVEL_LOW - [0:0] - read-write - - - - - DORMANT_WAKE_INTF2 - 0x000002f8 - Interrupt Force for dormant_wake - 0x00000000 - - - GPIO23_EDGE_HIGH - [31:31] - read-write - - - GPIO23_EDGE_LOW - [30:30] - read-write - - - GPIO23_LEVEL_HIGH - [29:29] - read-write - - - GPIO23_LEVEL_LOW - [28:28] - read-write - - - GPIO22_EDGE_HIGH - [27:27] - read-write - - - GPIO22_EDGE_LOW - [26:26] - read-write - - - GPIO22_LEVEL_HIGH - [25:25] - read-write - - - GPIO22_LEVEL_LOW - [24:24] - read-write - - - GPIO21_EDGE_HIGH - [23:23] - read-write - - - GPIO21_EDGE_LOW - [22:22] - read-write - - - GPIO21_LEVEL_HIGH - [21:21] - read-write - - - GPIO21_LEVEL_LOW - [20:20] - read-write - - - GPIO20_EDGE_HIGH - [19:19] - read-write - - - GPIO20_EDGE_LOW - [18:18] - read-write - - - GPIO20_LEVEL_HIGH - [17:17] - read-write - - - GPIO20_LEVEL_LOW - [16:16] - read-write - - - GPIO19_EDGE_HIGH - [15:15] - read-write - - - GPIO19_EDGE_LOW - [14:14] - read-write - - - GPIO19_LEVEL_HIGH - [13:13] - read-write - - - GPIO19_LEVEL_LOW - [12:12] - read-write - - - GPIO18_EDGE_HIGH - [11:11] - read-write - - - GPIO18_EDGE_LOW - [10:10] - read-write - - - GPIO18_LEVEL_HIGH - [9:9] - read-write - - - GPIO18_LEVEL_LOW - [8:8] - read-write - - - GPIO17_EDGE_HIGH - [7:7] - read-write - - - GPIO17_EDGE_LOW - [6:6] - read-write - - - GPIO17_LEVEL_HIGH - [5:5] - read-write - - - GPIO17_LEVEL_LOW - [4:4] - read-write - - - GPIO16_EDGE_HIGH - [3:3] - read-write - - - GPIO16_EDGE_LOW - [2:2] - read-write - - - GPIO16_LEVEL_HIGH - [1:1] - read-write - - - GPIO16_LEVEL_LOW - [0:0] - read-write - - - - - DORMANT_WAKE_INTF3 - 0x000002fc - Interrupt Force for dormant_wake - 0x00000000 - - - GPIO31_EDGE_HIGH - [31:31] - read-write - - - GPIO31_EDGE_LOW - [30:30] - read-write - - - GPIO31_LEVEL_HIGH - [29:29] - read-write - - - GPIO31_LEVEL_LOW - [28:28] - read-write - - - GPIO30_EDGE_HIGH - [27:27] - read-write - - - GPIO30_EDGE_LOW - [26:26] - read-write - - - GPIO30_LEVEL_HIGH - [25:25] - read-write - - - GPIO30_LEVEL_LOW - [24:24] - read-write - - - GPIO29_EDGE_HIGH - [23:23] - read-write - - - GPIO29_EDGE_LOW - [22:22] - read-write - - - GPIO29_LEVEL_HIGH - [21:21] - read-write - - - GPIO29_LEVEL_LOW - [20:20] - read-write - - - GPIO28_EDGE_HIGH - [19:19] - read-write - - - GPIO28_EDGE_LOW - [18:18] - read-write - - - GPIO28_LEVEL_HIGH - [17:17] - read-write - - - GPIO28_LEVEL_LOW - [16:16] - read-write - - - GPIO27_EDGE_HIGH - [15:15] - read-write - - - GPIO27_EDGE_LOW - [14:14] - read-write - - - GPIO27_LEVEL_HIGH - [13:13] - read-write - - - GPIO27_LEVEL_LOW - [12:12] - read-write - - - GPIO26_EDGE_HIGH - [11:11] - read-write - - - GPIO26_EDGE_LOW - [10:10] - read-write - - - GPIO26_LEVEL_HIGH - [9:9] - read-write - - - GPIO26_LEVEL_LOW - [8:8] - read-write - - - GPIO25_EDGE_HIGH - [7:7] - read-write - - - GPIO25_EDGE_LOW - [6:6] - read-write - - - GPIO25_LEVEL_HIGH - [5:5] - read-write - - - GPIO25_LEVEL_LOW - [4:4] - read-write - - - GPIO24_EDGE_HIGH - [3:3] - read-write - - - GPIO24_EDGE_LOW - [2:2] - read-write - - - GPIO24_LEVEL_HIGH - [1:1] - read-write - - - GPIO24_LEVEL_LOW - [0:0] - read-write - - - - - DORMANT_WAKE_INTF4 - 0x00000300 - Interrupt Force for dormant_wake - 0x00000000 - - - GPIO39_EDGE_HIGH - [31:31] - read-write - - - GPIO39_EDGE_LOW - [30:30] - read-write - - - GPIO39_LEVEL_HIGH - [29:29] - read-write - - - GPIO39_LEVEL_LOW - [28:28] - read-write - - - GPIO38_EDGE_HIGH - [27:27] - read-write - - - GPIO38_EDGE_LOW - [26:26] - read-write - - - GPIO38_LEVEL_HIGH - [25:25] - read-write - - - GPIO38_LEVEL_LOW - [24:24] - read-write - - - GPIO37_EDGE_HIGH - [23:23] - read-write - - - GPIO37_EDGE_LOW - [22:22] - read-write - - - GPIO37_LEVEL_HIGH - [21:21] - read-write - - - GPIO37_LEVEL_LOW - [20:20] - read-write - - - GPIO36_EDGE_HIGH - [19:19] - read-write - - - GPIO36_EDGE_LOW - [18:18] - read-write - - - GPIO36_LEVEL_HIGH - [17:17] - read-write - - - GPIO36_LEVEL_LOW - [16:16] - read-write - - - GPIO35_EDGE_HIGH - [15:15] - read-write - - - GPIO35_EDGE_LOW - [14:14] - read-write - - - GPIO35_LEVEL_HIGH - [13:13] - read-write - - - GPIO35_LEVEL_LOW - [12:12] - read-write - - - GPIO34_EDGE_HIGH - [11:11] - read-write - - - GPIO34_EDGE_LOW - [10:10] - read-write - - - GPIO34_LEVEL_HIGH - [9:9] - read-write - - - GPIO34_LEVEL_LOW - [8:8] - read-write - - - GPIO33_EDGE_HIGH - [7:7] - read-write - - - GPIO33_EDGE_LOW - [6:6] - read-write - - - GPIO33_LEVEL_HIGH - [5:5] - read-write - - - GPIO33_LEVEL_LOW - [4:4] - read-write - - - GPIO32_EDGE_HIGH - [3:3] - read-write - - - GPIO32_EDGE_LOW - [2:2] - read-write - - - GPIO32_LEVEL_HIGH - [1:1] - read-write - - - GPIO32_LEVEL_LOW - [0:0] - read-write - - - - - DORMANT_WAKE_INTF5 - 0x00000304 - Interrupt Force for dormant_wake - 0x00000000 - - - GPIO47_EDGE_HIGH - [31:31] - read-write - - - GPIO47_EDGE_LOW - [30:30] - read-write - - - GPIO47_LEVEL_HIGH - [29:29] - read-write - - - GPIO47_LEVEL_LOW - [28:28] - read-write - - - GPIO46_EDGE_HIGH - [27:27] - read-write - - - GPIO46_EDGE_LOW - [26:26] - read-write - - - GPIO46_LEVEL_HIGH - [25:25] - read-write - - - GPIO46_LEVEL_LOW - [24:24] - read-write - - - GPIO45_EDGE_HIGH - [23:23] - read-write - - - GPIO45_EDGE_LOW - [22:22] - read-write - - - GPIO45_LEVEL_HIGH - [21:21] - read-write - - - GPIO45_LEVEL_LOW - [20:20] - read-write - - - GPIO44_EDGE_HIGH - [19:19] - read-write - - - GPIO44_EDGE_LOW - [18:18] - read-write - - - GPIO44_LEVEL_HIGH - [17:17] - read-write - - - GPIO44_LEVEL_LOW - [16:16] - read-write - - - GPIO43_EDGE_HIGH - [15:15] - read-write - - - GPIO43_EDGE_LOW - [14:14] - read-write - - - GPIO43_LEVEL_HIGH - [13:13] - read-write - - - GPIO43_LEVEL_LOW - [12:12] - read-write - - - GPIO42_EDGE_HIGH - [11:11] - read-write - - - GPIO42_EDGE_LOW - [10:10] - read-write - - - GPIO42_LEVEL_HIGH - [9:9] - read-write - - - GPIO42_LEVEL_LOW - [8:8] - read-write - - - GPIO41_EDGE_HIGH - [7:7] - read-write - - - GPIO41_EDGE_LOW - [6:6] - read-write - - - GPIO41_LEVEL_HIGH - [5:5] - read-write - - - GPIO41_LEVEL_LOW - [4:4] - read-write - - - GPIO40_EDGE_HIGH - [3:3] - read-write - - - GPIO40_EDGE_LOW - [2:2] - read-write - - - GPIO40_LEVEL_HIGH - [1:1] - read-write - - - GPIO40_LEVEL_LOW - [0:0] - read-write - - - - - DORMANT_WAKE_INTS0 - 0x00000308 - Interrupt status after masking & forcing for dormant_wake - 0x00000000 - - - GPIO7_EDGE_HIGH - [31:31] - read-only - - - GPIO7_EDGE_LOW - [30:30] - read-only - - - GPIO7_LEVEL_HIGH - [29:29] - read-only - - - GPIO7_LEVEL_LOW - [28:28] - read-only - - - GPIO6_EDGE_HIGH - [27:27] - read-only - - - GPIO6_EDGE_LOW - [26:26] - read-only - - - GPIO6_LEVEL_HIGH - [25:25] - read-only - - - GPIO6_LEVEL_LOW - [24:24] - read-only - - - GPIO5_EDGE_HIGH - [23:23] - read-only - - - GPIO5_EDGE_LOW - [22:22] - read-only - - - GPIO5_LEVEL_HIGH - [21:21] - read-only - - - GPIO5_LEVEL_LOW - [20:20] - read-only - - - GPIO4_EDGE_HIGH - [19:19] - read-only - - - GPIO4_EDGE_LOW - [18:18] - read-only - - - GPIO4_LEVEL_HIGH - [17:17] - read-only - - - GPIO4_LEVEL_LOW - [16:16] - read-only - - - GPIO3_EDGE_HIGH - [15:15] - read-only - - - GPIO3_EDGE_LOW - [14:14] - read-only - - - GPIO3_LEVEL_HIGH - [13:13] - read-only - - - GPIO3_LEVEL_LOW - [12:12] - read-only - - - GPIO2_EDGE_HIGH - [11:11] - read-only - - - GPIO2_EDGE_LOW - [10:10] - read-only - - - GPIO2_LEVEL_HIGH - [9:9] - read-only - - - GPIO2_LEVEL_LOW - [8:8] - read-only - - - GPIO1_EDGE_HIGH - [7:7] - read-only - - - GPIO1_EDGE_LOW - [6:6] - read-only - - - GPIO1_LEVEL_HIGH - [5:5] - read-only - - - GPIO1_LEVEL_LOW - [4:4] - read-only - - - GPIO0_EDGE_HIGH - [3:3] - read-only - - - GPIO0_EDGE_LOW - [2:2] - read-only - - - GPIO0_LEVEL_HIGH - [1:1] - read-only - - - GPIO0_LEVEL_LOW - [0:0] - read-only - - - - - DORMANT_WAKE_INTS1 - 0x0000030c - Interrupt status after masking & forcing for dormant_wake - 0x00000000 - - - GPIO15_EDGE_HIGH - [31:31] - read-only - - - GPIO15_EDGE_LOW - [30:30] - read-only - - - GPIO15_LEVEL_HIGH - [29:29] - read-only - - - GPIO15_LEVEL_LOW - [28:28] - read-only - - - GPIO14_EDGE_HIGH - [27:27] - read-only - - - GPIO14_EDGE_LOW - [26:26] - read-only - - - GPIO14_LEVEL_HIGH - [25:25] - read-only - - - GPIO14_LEVEL_LOW - [24:24] - read-only - - - GPIO13_EDGE_HIGH - [23:23] - read-only - - - GPIO13_EDGE_LOW - [22:22] - read-only - - - GPIO13_LEVEL_HIGH - [21:21] - read-only - - - GPIO13_LEVEL_LOW - [20:20] - read-only - - - GPIO12_EDGE_HIGH - [19:19] - read-only - - - GPIO12_EDGE_LOW - [18:18] - read-only - - - GPIO12_LEVEL_HIGH - [17:17] - read-only - - - GPIO12_LEVEL_LOW - [16:16] - read-only - - - GPIO11_EDGE_HIGH - [15:15] - read-only - - - GPIO11_EDGE_LOW - [14:14] - read-only - - - GPIO11_LEVEL_HIGH - [13:13] - read-only - - - GPIO11_LEVEL_LOW - [12:12] - read-only - - - GPIO10_EDGE_HIGH - [11:11] - read-only - - - GPIO10_EDGE_LOW - [10:10] - read-only - - - GPIO10_LEVEL_HIGH - [9:9] - read-only - - - GPIO10_LEVEL_LOW - [8:8] - read-only - - - GPIO9_EDGE_HIGH - [7:7] - read-only - - - GPIO9_EDGE_LOW - [6:6] - read-only - - - GPIO9_LEVEL_HIGH - [5:5] - read-only - - - GPIO9_LEVEL_LOW - [4:4] - read-only - - - GPIO8_EDGE_HIGH - [3:3] - read-only - - - GPIO8_EDGE_LOW - [2:2] - read-only - - - GPIO8_LEVEL_HIGH - [1:1] - read-only - - - GPIO8_LEVEL_LOW - [0:0] - read-only - - - - - DORMANT_WAKE_INTS2 - 0x00000310 - Interrupt status after masking & forcing for dormant_wake - 0x00000000 - - - GPIO23_EDGE_HIGH - [31:31] - read-only - - - GPIO23_EDGE_LOW - [30:30] - read-only - - - GPIO23_LEVEL_HIGH - [29:29] - read-only - - - GPIO23_LEVEL_LOW - [28:28] - read-only - - - GPIO22_EDGE_HIGH - [27:27] - read-only - - - GPIO22_EDGE_LOW - [26:26] - read-only - - - GPIO22_LEVEL_HIGH - [25:25] - read-only - - - GPIO22_LEVEL_LOW - [24:24] - read-only - - - GPIO21_EDGE_HIGH - [23:23] - read-only - - - GPIO21_EDGE_LOW - [22:22] - read-only - - - GPIO21_LEVEL_HIGH - [21:21] - read-only - - - GPIO21_LEVEL_LOW - [20:20] - read-only - - - GPIO20_EDGE_HIGH - [19:19] - read-only - - - GPIO20_EDGE_LOW - [18:18] - read-only - - - GPIO20_LEVEL_HIGH - [17:17] - read-only - - - GPIO20_LEVEL_LOW - [16:16] - read-only - - - GPIO19_EDGE_HIGH - [15:15] - read-only - - - GPIO19_EDGE_LOW - [14:14] - read-only - - - GPIO19_LEVEL_HIGH - [13:13] - read-only - - - GPIO19_LEVEL_LOW - [12:12] - read-only - - - GPIO18_EDGE_HIGH - [11:11] - read-only - - - GPIO18_EDGE_LOW - [10:10] - read-only - - - GPIO18_LEVEL_HIGH - [9:9] - read-only - - - GPIO18_LEVEL_LOW - [8:8] - read-only - - - GPIO17_EDGE_HIGH - [7:7] - read-only - - - GPIO17_EDGE_LOW - [6:6] - read-only - - - GPIO17_LEVEL_HIGH - [5:5] - read-only - - - GPIO17_LEVEL_LOW - [4:4] - read-only - - - GPIO16_EDGE_HIGH - [3:3] - read-only - - - GPIO16_EDGE_LOW - [2:2] - read-only - - - GPIO16_LEVEL_HIGH - [1:1] - read-only - - - GPIO16_LEVEL_LOW - [0:0] - read-only - - - - - DORMANT_WAKE_INTS3 - 0x00000314 - Interrupt status after masking & forcing for dormant_wake - 0x00000000 - - - GPIO31_EDGE_HIGH - [31:31] - read-only - - - GPIO31_EDGE_LOW - [30:30] - read-only - - - GPIO31_LEVEL_HIGH - [29:29] - read-only - - - GPIO31_LEVEL_LOW - [28:28] - read-only - - - GPIO30_EDGE_HIGH - [27:27] - read-only - - - GPIO30_EDGE_LOW - [26:26] - read-only - - - GPIO30_LEVEL_HIGH - [25:25] - read-only - - - GPIO30_LEVEL_LOW - [24:24] - read-only - - - GPIO29_EDGE_HIGH - [23:23] - read-only - - - GPIO29_EDGE_LOW - [22:22] - read-only - - - GPIO29_LEVEL_HIGH - [21:21] - read-only - - - GPIO29_LEVEL_LOW - [20:20] - read-only - - - GPIO28_EDGE_HIGH - [19:19] - read-only - - - GPIO28_EDGE_LOW - [18:18] - read-only - - - GPIO28_LEVEL_HIGH - [17:17] - read-only - - - GPIO28_LEVEL_LOW - [16:16] - read-only - - - GPIO27_EDGE_HIGH - [15:15] - read-only - - - GPIO27_EDGE_LOW - [14:14] - read-only - - - GPIO27_LEVEL_HIGH - [13:13] - read-only - - - GPIO27_LEVEL_LOW - [12:12] - read-only - - - GPIO26_EDGE_HIGH - [11:11] - read-only - - - GPIO26_EDGE_LOW - [10:10] - read-only - - - GPIO26_LEVEL_HIGH - [9:9] - read-only - - - GPIO26_LEVEL_LOW - [8:8] - read-only - - - GPIO25_EDGE_HIGH - [7:7] - read-only - - - GPIO25_EDGE_LOW - [6:6] - read-only - - - GPIO25_LEVEL_HIGH - [5:5] - read-only - - - GPIO25_LEVEL_LOW - [4:4] - read-only - - - GPIO24_EDGE_HIGH - [3:3] - read-only - - - GPIO24_EDGE_LOW - [2:2] - read-only - - - GPIO24_LEVEL_HIGH - [1:1] - read-only - - - GPIO24_LEVEL_LOW - [0:0] - read-only - - - - - DORMANT_WAKE_INTS4 - 0x00000318 - Interrupt status after masking & forcing for dormant_wake - 0x00000000 - - - GPIO39_EDGE_HIGH - [31:31] - read-only - - - GPIO39_EDGE_LOW - [30:30] - read-only - - - GPIO39_LEVEL_HIGH - [29:29] - read-only - - - GPIO39_LEVEL_LOW - [28:28] - read-only - - - GPIO38_EDGE_HIGH - [27:27] - read-only - - - GPIO38_EDGE_LOW - [26:26] - read-only - - - GPIO38_LEVEL_HIGH - [25:25] - read-only - - - GPIO38_LEVEL_LOW - [24:24] - read-only - - - GPIO37_EDGE_HIGH - [23:23] - read-only - - - GPIO37_EDGE_LOW - [22:22] - read-only - - - GPIO37_LEVEL_HIGH - [21:21] - read-only - - - GPIO37_LEVEL_LOW - [20:20] - read-only - - - GPIO36_EDGE_HIGH - [19:19] - read-only - - - GPIO36_EDGE_LOW - [18:18] - read-only - - - GPIO36_LEVEL_HIGH - [17:17] - read-only - - - GPIO36_LEVEL_LOW - [16:16] - read-only - - - GPIO35_EDGE_HIGH - [15:15] - read-only - - - GPIO35_EDGE_LOW - [14:14] - read-only - - - GPIO35_LEVEL_HIGH - [13:13] - read-only - - - GPIO35_LEVEL_LOW - [12:12] - read-only - - - GPIO34_EDGE_HIGH - [11:11] - read-only - - - GPIO34_EDGE_LOW - [10:10] - read-only - - - GPIO34_LEVEL_HIGH - [9:9] - read-only - - - GPIO34_LEVEL_LOW - [8:8] - read-only - - - GPIO33_EDGE_HIGH - [7:7] - read-only - - - GPIO33_EDGE_LOW - [6:6] - read-only - - - GPIO33_LEVEL_HIGH - [5:5] - read-only - - - GPIO33_LEVEL_LOW - [4:4] - read-only - - - GPIO32_EDGE_HIGH - [3:3] - read-only - - - GPIO32_EDGE_LOW - [2:2] - read-only - - - GPIO32_LEVEL_HIGH - [1:1] - read-only - - - GPIO32_LEVEL_LOW - [0:0] - read-only - - - - - DORMANT_WAKE_INTS5 - 0x0000031c - Interrupt status after masking & forcing for dormant_wake - 0x00000000 - - - GPIO47_EDGE_HIGH - [31:31] - read-only - - - GPIO47_EDGE_LOW - [30:30] - read-only - - - GPIO47_LEVEL_HIGH - [29:29] - read-only - - - GPIO47_LEVEL_LOW - [28:28] - read-only - - - GPIO46_EDGE_HIGH - [27:27] - read-only - - - GPIO46_EDGE_LOW - [26:26] - read-only - - - GPIO46_LEVEL_HIGH - [25:25] - read-only - - - GPIO46_LEVEL_LOW - [24:24] - read-only - - - GPIO45_EDGE_HIGH - [23:23] - read-only - - - GPIO45_EDGE_LOW - [22:22] - read-only - - - GPIO45_LEVEL_HIGH - [21:21] - read-only - - - GPIO45_LEVEL_LOW - [20:20] - read-only - - - GPIO44_EDGE_HIGH - [19:19] - read-only - - - GPIO44_EDGE_LOW - [18:18] - read-only - - - GPIO44_LEVEL_HIGH - [17:17] - read-only - - - GPIO44_LEVEL_LOW - [16:16] - read-only - - - GPIO43_EDGE_HIGH - [15:15] - read-only - - - GPIO43_EDGE_LOW - [14:14] - read-only - - - GPIO43_LEVEL_HIGH - [13:13] - read-only - - - GPIO43_LEVEL_LOW - [12:12] - read-only - - - GPIO42_EDGE_HIGH - [11:11] - read-only - - - GPIO42_EDGE_LOW - [10:10] - read-only - - - GPIO42_LEVEL_HIGH - [9:9] - read-only - - - GPIO42_LEVEL_LOW - [8:8] - read-only - - - GPIO41_EDGE_HIGH - [7:7] - read-only - - - GPIO41_EDGE_LOW - [6:6] - read-only - - - GPIO41_LEVEL_HIGH - [5:5] - read-only - - - GPIO41_LEVEL_LOW - [4:4] - read-only - - - GPIO40_EDGE_HIGH - [3:3] - read-only - - - GPIO40_EDGE_LOW - [2:2] - read-only - - - GPIO40_LEVEL_HIGH - [1:1] - read-only - - - GPIO40_LEVEL_LOW - [0:0] - read-only - - - - - - - SYSINFO - 0x40000000 - - 0 - 24 - registers - - - - CHIP_ID - 0x00000000 - JEDEC JEP-106 compliant chip identifier. - 0x00000001 - - - REVISION - [31:28] - read-only - - - PART - [27:12] - read-only - - - MANUFACTURER - [11:1] - read-only - - - STOP_BIT - [0:0] - read-only - - - - - PACKAGE_SEL - 0x00000004 - 0x00000000 - - - PACKAGE_SEL - [0:0] - read-only - - - - - PLATFORM - 0x00000008 - Platform register. Allows software to know what environment it is running in during pre-production development. Post-production, the PLATFORM is always ASIC, non-SIM. - 0x00000000 - - - GATESIM - [4:4] - read-only - - - BATCHSIM - [3:3] - read-only - - - HDLSIM - [2:2] - read-only - - - ASIC - [1:1] - read-only - - - FPGA - [0:0] - read-only - - - - - GITREF_RP2350 - 0x00000014 - Git hash of the chip source. Used to identify chip version. - 0x00000000 - - - GITREF_RP2350 - [31:0] - read-only - - - - - - - SHA256 - SHA-256 hash function implementation - 0x400f8000 - - 0 - 40 - registers - - - - CSR - 0x00000000 - Control and status register - 0x00001206 - - - BSWAP - Enable byte swapping of 32-bit values at the point they are committed to the SHA message scheduler. - - This block's bus interface assembles byte/halfword data into message words in little-endian order, so that DMAing the same buffer with different transfer sizes always gives the same result on a little-endian system like RP2350. - - However, when marshalling bytes into blocks, SHA expects that the first byte is the *most significant* in each message word. To resolve this, once the bus interface has accumulated 32 bits of data (either a word write, two halfword writes in little-endian order, or four byte writes in little-endian order) the final value can be byte-swapped before passing to the actual SHA core. - - This feature is enabled by default because using the SHA core to checksum byte buffers is expected to be more common than having preformatted SHA message words lying around. - [12:12] - read-write - - - DMA_SIZE - Configure DREQ logic for the correct DMA data size. Must be configured before the DMA channel is triggered. - - The SHA-256 core's DREQ logic requests one entire block of data at once, since there is no FIFO, and data goes straight into the core's message schedule and digest hardware. Therefore, when transferring data with DMA, CSR_DMA_SIZE must be configured in advance so that the correct number of transfers can be requested per block. - [9:8] - read-write - - - 8bit - 0 - - - 16bit - 1 - - - 32bit - 2 - - - - - ERR_WDATA_NOT_RDY - Set when a write occurs whilst the SHA-256 core is not ready for data (WDATA_RDY is low). Write one to clear. - [4:4] - read-write - oneToClear - - - SUM_VLD - If 1, the SHA-256 checksum presented in registers SUM0 through SUM7 is currently valid. - - Goes low when WDATA is first written, then returns high once 16 words have been written and the digest of the current 512-bit block has subsequently completed. - [2:2] - read-only - - - WDATA_RDY - If 1, the SHA-256 core is ready to accept more data through the WDATA register. - - After writing 16 words, this flag will go low for 57 cycles whilst the core completes its digest. - [1:1] - read-only - - - START - Write 1 to prepare the SHA-256 core for a new checksum. - - The SUMx registers are initialised to the proper values (fractional bits of square roots of first 8 primes) and internal counters are cleared. This immediately forces WDATA_RDY and SUM_VLD high. - - START must be written before initiating a DMA transfer to the SHA-256 core, because the core will always request 16 transfers at a time (1 512-bit block). Additionally, the DMA channel should be configured for a multiple of 16 32-bit transfers. - [0:0] - write-only - - - - - WDATA - 0x00000004 - Write data register - 0x00000000 - - - WDATA - After pulsing START and writing 16 words of data to this register, WDATA_RDY will go low and the SHA-256 core will complete the digest of the current 512-bit block. - - Software is responsible for ensuring the data is correctly padded and terminated to a whole number of 512-bit blocks. - - After this, WDATA_RDY will return high, and more data can be written (if any). - - This register supports word, halfword and byte writes, so that DMA from non-word-aligned buffers can be supported. The total amount of data per block remains the same (16 words, 32 halfwords or 64 bytes) and byte/halfword transfers must not be mixed within a block. - [31:0] - write-only - - - - - SUM0 - 0x00000008 - 256-bit checksum result. Contents are undefined when CSR_SUM_VLD is 0. - 0x00000000 - - - SUM0 - [31:0] - read-only - - - - - SUM1 - 0x0000000c - 256-bit checksum result. Contents are undefined when CSR_SUM_VLD is 0. - 0x00000000 - - - SUM1 - [31:0] - read-only - - - - - SUM2 - 0x00000010 - 256-bit checksum result. Contents are undefined when CSR_SUM_VLD is 0. - 0x00000000 - - - SUM2 - [31:0] - read-only - - - - - SUM3 - 0x00000014 - 256-bit checksum result. Contents are undefined when CSR_SUM_VLD is 0. - 0x00000000 - - - SUM3 - [31:0] - read-only - - - - - SUM4 - 0x00000018 - 256-bit checksum result. Contents are undefined when CSR_SUM_VLD is 0. - 0x00000000 - - - SUM4 - [31:0] - read-only - - - - - SUM5 - 0x0000001c - 256-bit checksum result. Contents are undefined when CSR_SUM_VLD is 0. - 0x00000000 - - - SUM5 - [31:0] - read-only - - - - - SUM6 - 0x00000020 - 256-bit checksum result. Contents are undefined when CSR_SUM_VLD is 0. - 0x00000000 - - - SUM6 - [31:0] - read-only - - - - - SUM7 - 0x00000024 - 256-bit checksum result. Contents are undefined when CSR_SUM_VLD is 0. - 0x00000000 - - - SUM7 - [31:0] - read-only - - - - - - - HSTX_FIFO - FIFO status and write access for HSTX - 0x50600000 - - 0 - 8 - registers - - - - STAT - 0x00000000 - FIFO status - 0x00000000 - - - WOF - FIFO was written when full. Write 1 to clear. - [10:10] - read-write - oneToClear - - - EMPTY - [9:9] - read-only - - - FULL - [8:8] - read-only - - - LEVEL - [7:0] - read-only - - - - - FIFO - 0x00000004 - Write access to FIFO - 0x00000000 - - - FIFO - [31:0] - write-only - - - - - - - HSTX_CTRL - Control interface to HSTX. For FIFO write access and status, see the HSTX_FIFO register block. - 0x400c0000 - - 0 - 44 - registers - - - - CSR - 0x00000000 - 0x10050600 - - - CLKDIV - Clock period of the generated clock, measured in HSTX clock cycles. Can be odd or even. The generated clock advances only on cycles where the shift register shifts. - - For example, a clkdiv of 5 would generate a complete output clock period for every 5 HSTX clocks (or every 10 half-clocks). - - A CLKDIV value of 0 is mapped to a period of 16 HSTX clock cycles. - [31:28] - read-write - - - CLKPHASE - Set the initial phase of the generated clock. - - A CLKPHASE of 0 means the clock is initially low, and the first rising edge occurs after one half period of the generated clock (i.e. CLKDIV/2 cycles of clk_hstx). Incrementing CLKPHASE by 1 will advance the initial clock phase by one half clk_hstx period. For example, if CLKDIV=2 and CLKPHASE=1: - - * The clock will be initially low - - * The first rising edge will be 0.5 clk_hstx cycles after asserting first data - - * The first falling edge will be 1.5 clk_hstx cycles after asserting first data - - This configuration would be suitable for serialising at a bit rate of clk_hstx with a centre-aligned DDR clock. - - When the HSTX is halted by clearing CSR_EN, the clock generator will return to its initial phase as configured by the CLKPHASE field. - - Note CLKPHASE must be strictly less than double the value of CLKDIV (one full period), else its operation is undefined. - [27:24] - read-write - - - N_SHIFTS - Number of times to shift the shift register before refilling it from the FIFO. (A count of how many times it has been shifted, *not* the total shift distance.) - - A register value of 0 means shift 32 times. - [20:16] - read-write - - - SHIFT - How many bits to right-rotate the shift register by each cycle. - - The use of a rotate rather than a shift allows left shifts to be emulated, by subtracting the left-shift amount from 32. It also allows data to be repeated, when the product of SHIFT and N_SHIFTS is greater than 32. - [12:8] - read-write - - - COUPLED_SEL - Select which PIO to use for coupled mode operation. - [6:5] - read-write - - - COUPLED_MODE - Enable the PIO-to-HSTX 1:1 connection. The HSTX must be clocked *directly* from the system clock (not just from some other clock source of the same frequency) for this synchronous interface to function correctly. - - When COUPLED_MODE is set, BITx_SEL_P and SEL_N indices 24 through 31 will select bits from the 8-bit PIO-to-HSTX path, rather than shifter bits. Indices of 0 through 23 will still index the shift register as normal. - - The PIO outputs connected to the PIO-to-HSTX bus are those same outputs that would appear on the HSTX-capable pins if those pins' FUNCSELs were set to PIO instead of HSTX. - - For example, if HSTX is on GPIOs 12 through 19, then PIO outputs 12 through 19 are connected to the HSTX when coupled mode is engaged. - [4:4] - read-write - - - EXPAND_EN - Enable the command expander. When 0, raw FIFO data is passed directly to the output shift register. When 1, the command expander can perform simple operations such as run length decoding on data between the FIFO and the shift register. - - Do not change CXPD_EN whilst EN is set. It's safe to set CXPD_EN simultaneously with setting EN. - [1:1] - read-write - - - EN - When EN is 1, the HSTX will shift out data as it appears in the FIFO. As long as there is data, the HSTX shift register will shift once per clock cycle, and the frequency of popping from the FIFO is determined by the ratio of SHIFT and SHIFT_THRESH. - - When EN is 0, the FIFO is not popped. The shift counter and clock generator are also reset to their initial state for as long as EN is low. Note the initial phase of the clock generator can be configured by the CLKPHASE field. - - Once the HSTX is enabled again, and data is pushed to the FIFO, the generated clock's first rising edge will be one half-period after the first data is launched. - [0:0] - read-write - - - - - BIT0 - 0x00000004 - Data control register for output bit 0 - 0x00000000 - - - CLK - Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock. - [17:17] - read-write - - - INV - Invert this data output (logical NOT) - [16:16] - read-write - - - SEL_N - Shift register data bit select for the second half of the HSTX clock cycle - [12:8] - read-write - - - SEL_P - Shift register data bit select for the first half of the HSTX clock cycle - [4:0] - read-write - - - - - BIT1 - 0x00000008 - Data control register for output bit 1 - 0x00000000 - - - CLK - Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock. - [17:17] - read-write - - - INV - Invert this data output (logical NOT) - [16:16] - read-write - - - SEL_N - Shift register data bit select for the second half of the HSTX clock cycle - [12:8] - read-write - - - SEL_P - Shift register data bit select for the first half of the HSTX clock cycle - [4:0] - read-write - - - - - BIT2 - 0x0000000c - Data control register for output bit 2 - 0x00000000 - - - CLK - Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock. - [17:17] - read-write - - - INV - Invert this data output (logical NOT) - [16:16] - read-write - - - SEL_N - Shift register data bit select for the second half of the HSTX clock cycle - [12:8] - read-write - - - SEL_P - Shift register data bit select for the first half of the HSTX clock cycle - [4:0] - read-write - - - - - BIT3 - 0x00000010 - Data control register for output bit 3 - 0x00000000 - - - CLK - Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock. - [17:17] - read-write - - - INV - Invert this data output (logical NOT) - [16:16] - read-write - - - SEL_N - Shift register data bit select for the second half of the HSTX clock cycle - [12:8] - read-write - - - SEL_P - Shift register data bit select for the first half of the HSTX clock cycle - [4:0] - read-write - - - - - BIT4 - 0x00000014 - Data control register for output bit 4 - 0x00000000 - - - CLK - Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock. - [17:17] - read-write - - - INV - Invert this data output (logical NOT) - [16:16] - read-write - - - SEL_N - Shift register data bit select for the second half of the HSTX clock cycle - [12:8] - read-write - - - SEL_P - Shift register data bit select for the first half of the HSTX clock cycle - [4:0] - read-write - - - - - BIT5 - 0x00000018 - Data control register for output bit 5 - 0x00000000 - - - CLK - Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock. - [17:17] - read-write - - - INV - Invert this data output (logical NOT) - [16:16] - read-write - - - SEL_N - Shift register data bit select for the second half of the HSTX clock cycle - [12:8] - read-write - - - SEL_P - Shift register data bit select for the first half of the HSTX clock cycle - [4:0] - read-write - - - - - BIT6 - 0x0000001c - Data control register for output bit 6 - 0x00000000 - - - CLK - Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock. - [17:17] - read-write - - - INV - Invert this data output (logical NOT) - [16:16] - read-write - - - SEL_N - Shift register data bit select for the second half of the HSTX clock cycle - [12:8] - read-write - - - SEL_P - Shift register data bit select for the first half of the HSTX clock cycle - [4:0] - read-write - - - - - BIT7 - 0x00000020 - Data control register for output bit 7 - 0x00000000 - - - CLK - Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock. - [17:17] - read-write - - - INV - Invert this data output (logical NOT) - [16:16] - read-write - - - SEL_N - Shift register data bit select for the second half of the HSTX clock cycle - [12:8] - read-write - - - SEL_P - Shift register data bit select for the first half of the HSTX clock cycle - [4:0] - read-write - - - - - EXPAND_SHIFT - 0x00000024 - Configure the optional shifter inside the command expander - 0x01000100 - - - ENC_N_SHIFTS - Number of times to consume from the shift register before refilling it from the FIFO, when the current command is an encoded data command (e.g. TMDS). A register value of 0 means shift 32 times. - [28:24] - read-write - - - ENC_SHIFT - How many bits to right-rotate the shift register by each time data is pushed to the output shifter, when the current command is an encoded data command (e.g. TMDS). - [20:16] - read-write - - - RAW_N_SHIFTS - Number of times to consume from the shift register before refilling it from the FIFO, when the current command is a raw data command. A register value of 0 means shift 32 times. - [12:8] - read-write - - - RAW_SHIFT - How many bits to right-rotate the shift register by each time data is pushed to the output shifter, when the current command is a raw data command. - [4:0] - read-write - - - - - EXPAND_TMDS - 0x00000028 - Configure the optional TMDS encoder inside the command expander - 0x00000000 - - - L2_NBITS - Number of valid data bits for the lane 2 TMDS encoder, starting from bit 7 of the rotated data. Field values of 0 -> 7 encode counts of 1 -> 8 bits. - [23:21] - read-write - - - L2_ROT - Right-rotate applied to the current shifter data before the lane 2 TMDS encoder. - [20:16] - read-write - - - L1_NBITS - Number of valid data bits for the lane 1 TMDS encoder, starting from bit 7 of the rotated data. Field values of 0 -> 7 encode counts of 1 -> 8 bits. - [15:13] - read-write - - - L1_ROT - Right-rotate applied to the current shifter data before the lane 1 TMDS encoder. - [12:8] - read-write - - - L0_NBITS - Number of valid data bits for the lane 0 TMDS encoder, starting from bit 7 of the rotated data. Field values of 0 -> 7 encode counts of 1 -> 8 bits. - [7:5] - read-write - - - L0_ROT - Right-rotate applied to the current shifter data before the lane 0 TMDS encoder. - [4:0] - read-write - - - - - - - EPPB - Cortex-M33 EPPB vendor register block for RP2350 - 0xe0080000 - - 0 - 12 - registers - - - - NMI_MASK0 - 0x00000000 - NMI mask for IRQs 0 through 31. This register is core-local, and is reset by a processor warm reset. - 0x00000000 - - - NMI_MASK0 - [31:0] - read-write - - - - - NMI_MASK1 - 0x00000004 - NMI mask for IRQs 0 though 51. This register is core-local, and is reset by a processor warm reset. - 0x00000000 - - - NMI_MASK1 - [19:0] - read-write - - - - - SLEEPCTRL - 0x00000008 - Nonstandard sleep control register - 0x00000002 - - - WICENACK - Status signal from the processor's interrupt controller. Changes to WICENREQ are eventually reflected in WICENACK. - [2:2] - read-only - - - WICENREQ - Request that the next processor deep sleep is a WIC sleep. After setting this bit, before sleeping, poll WICENACK to ensure the processor interrupt controller has acknowledged the change. - [1:1] - read-write - - - LIGHT_SLEEP - By default, any processor sleep will deassert the system-level clock request. Reenabling the clocks incurs 5 cycles of additional latency on wakeup. - - Setting LIGHT_SLEEP to 1 keeps the clock request asserted during a normal sleep (Arm SCR.SLEEPDEEP = 0), for faster wakeup. Processor deep sleep (Arm SCR.SLEEPDEEP = 1) is not affected, and will always deassert the system-level clock request. - [0:0] - read-write - - - - - - - PPB - TEAL registers accessible through the debug interface - 0xe0000000 - - 0 - 274432 - registers - - - - ITM_STIM0 - 0x00000000 - Provides the interface for generating Instrumentation packets - 0x00000000 - - - STIMULUS - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. - [31:0] - read-write - - - - - ITM_STIM1 - 0x00000004 - Provides the interface for generating Instrumentation packets - 0x00000000 - - - STIMULUS - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. - [31:0] - read-write - - - - - ITM_STIM2 - 0x00000008 - Provides the interface for generating Instrumentation packets - 0x00000000 - - - STIMULUS - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. - [31:0] - read-write - - - - - ITM_STIM3 - 0x0000000c - Provides the interface for generating Instrumentation packets - 0x00000000 - - - STIMULUS - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. - [31:0] - read-write - - - - - ITM_STIM4 - 0x00000010 - Provides the interface for generating Instrumentation packets - 0x00000000 - - - STIMULUS - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. - [31:0] - read-write - - - - - ITM_STIM5 - 0x00000014 - Provides the interface for generating Instrumentation packets - 0x00000000 - - - STIMULUS - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. - [31:0] - read-write - - - - - ITM_STIM6 - 0x00000018 - Provides the interface for generating Instrumentation packets - 0x00000000 - - - STIMULUS - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. - [31:0] - read-write - - - - - ITM_STIM7 - 0x0000001c - Provides the interface for generating Instrumentation packets - 0x00000000 - - - STIMULUS - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. - [31:0] - read-write - - - - - ITM_STIM8 - 0x00000020 - Provides the interface for generating Instrumentation packets - 0x00000000 - - - STIMULUS - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. - [31:0] - read-write - - - - - ITM_STIM9 - 0x00000024 - Provides the interface for generating Instrumentation packets - 0x00000000 - - - STIMULUS - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. - [31:0] - read-write - - - - - ITM_STIM10 - 0x00000028 - Provides the interface for generating Instrumentation packets - 0x00000000 - - - STIMULUS - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. - [31:0] - read-write - - - - - ITM_STIM11 - 0x0000002c - Provides the interface for generating Instrumentation packets - 0x00000000 - - - STIMULUS - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. - [31:0] - read-write - - - - - ITM_STIM12 - 0x00000030 - Provides the interface for generating Instrumentation packets - 0x00000000 - - - STIMULUS - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. - [31:0] - read-write - - - - - ITM_STIM13 - 0x00000034 - Provides the interface for generating Instrumentation packets - 0x00000000 - - - STIMULUS - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. - [31:0] - read-write - - - - - ITM_STIM14 - 0x00000038 - Provides the interface for generating Instrumentation packets - 0x00000000 - - - STIMULUS - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. - [31:0] - read-write - - - - - ITM_STIM15 - 0x0000003c - Provides the interface for generating Instrumentation packets - 0x00000000 - - - STIMULUS - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. - [31:0] - read-write - - - - - ITM_STIM16 - 0x00000040 - Provides the interface for generating Instrumentation packets - 0x00000000 - - - STIMULUS - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. - [31:0] - read-write - - - - - ITM_STIM17 - 0x00000044 - Provides the interface for generating Instrumentation packets - 0x00000000 - - - STIMULUS - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. - [31:0] - read-write - - - - - ITM_STIM18 - 0x00000048 - Provides the interface for generating Instrumentation packets - 0x00000000 - - - STIMULUS - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. - [31:0] - read-write - - - - - ITM_STIM19 - 0x0000004c - Provides the interface for generating Instrumentation packets - 0x00000000 - - - STIMULUS - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. - [31:0] - read-write - - - - - ITM_STIM20 - 0x00000050 - Provides the interface for generating Instrumentation packets - 0x00000000 - - - STIMULUS - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. - [31:0] - read-write - - - - - ITM_STIM21 - 0x00000054 - Provides the interface for generating Instrumentation packets - 0x00000000 - - - STIMULUS - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. - [31:0] - read-write - - - - - ITM_STIM22 - 0x00000058 - Provides the interface for generating Instrumentation packets - 0x00000000 - - - STIMULUS - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. - [31:0] - read-write - - - - - ITM_STIM23 - 0x0000005c - Provides the interface for generating Instrumentation packets - 0x00000000 - - - STIMULUS - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. - [31:0] - read-write - - - - - ITM_STIM24 - 0x00000060 - Provides the interface for generating Instrumentation packets - 0x00000000 - - - STIMULUS - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. - [31:0] - read-write - - - - - ITM_STIM25 - 0x00000064 - Provides the interface for generating Instrumentation packets - 0x00000000 - - - STIMULUS - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. - [31:0] - read-write - - - - - ITM_STIM26 - 0x00000068 - Provides the interface for generating Instrumentation packets - 0x00000000 - - - STIMULUS - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. - [31:0] - read-write - - - - - ITM_STIM27 - 0x0000006c - Provides the interface for generating Instrumentation packets - 0x00000000 - - - STIMULUS - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. - [31:0] - read-write - - - - - ITM_STIM28 - 0x00000070 - Provides the interface for generating Instrumentation packets - 0x00000000 - - - STIMULUS - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. - [31:0] - read-write - - - - - ITM_STIM29 - 0x00000074 - Provides the interface for generating Instrumentation packets - 0x00000000 - - - STIMULUS - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. - [31:0] - read-write - - - - - ITM_STIM30 - 0x00000078 - Provides the interface for generating Instrumentation packets - 0x00000000 - - - STIMULUS - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. - [31:0] - read-write - - - - - ITM_STIM31 - 0x0000007c - Provides the interface for generating Instrumentation packets - 0x00000000 - - - STIMULUS - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. - [31:0] - read-write - - - - - ITM_TER0 - 0x00000e00 - Provide an individual enable bit for each ITM_STIM register - 0x00000000 - - - STIMENA - For STIMENA[m] in ITM_TER*n, controls whether ITM_STIM(32*n + m) is enabled - [31:0] - read-write - - - - - ITM_TPR - 0x00000e40 - Controls which stimulus ports can be accessed by unprivileged code - 0x00000000 - - - PRIVMASK - Bit mask to enable tracing on ITM stimulus ports - [3:0] - read-write - - - - - ITM_TCR - 0x00000e80 - Configures and controls transfers through the ITM interface - 0x00000000 - - - BUSY - Indicates whether the ITM is currently processing events - [23:23] - read-only - - - TRACEBUSID - Identifier for multi-source trace stream formatting. If multi-source trace is in use, the debugger must write a unique non-zero trace ID value to this field - [22:16] - read-write - - - GTSFREQ - Defines how often the ITM generates a global timestamp, based on the global timestamp clock frequency, or disables generation of global timestamps - [11:10] - read-write - - - TSPRESCALE - Local timestamp prescaler, used with the trace packet reference clock - [9:8] - read-write - - - STALLENA - Stall the PE to guarantee delivery of Data Trace packets. - [5:5] - read-write - - - SWOENA - Enables asynchronous clocking of the timestamp counter - [4:4] - read-write - - - TXENA - Enables forwarding of hardware event packet from the DWT unit to the ITM for output to the TPIU - [3:3] - read-write - - - SYNCENA - Enables Synchronization packet transmission for a synchronous TPIU - [2:2] - read-write - - - TSENA - Enables Local timestamp generation - [1:1] - read-write - - - ITMENA - Enables the ITM - [0:0] - read-write - - - - - INT_ATREADY - 0x00000ef0 - Integration Mode: Read ATB Ready - 0x00000000 - - - AFVALID - A read of this bit returns the value of AFVALID - [1:1] - read-only - - - ATREADY - A read of this bit returns the value of ATREADY - [0:0] - read-only - - - - - INT_ATVALID - 0x00000ef8 - Integration Mode: Write ATB Valid - 0x00000000 - - - AFREADY - A write to this bit gives the value of AFREADY - [1:1] - read-write - - - ATREADY - A write to this bit gives the value of ATVALID - [0:0] - read-write - - - - - ITM_ITCTRL - 0x00000f00 - Integration Mode Control Register - 0x00000000 - - - IME - Integration mode enable bit - The possible values are: 0 - The trace unit is not in integration mode. 1 - The trace unit is in integration mode. This mode enables: A debug agent to perform topology detection. SoC test software to perform integration testing. - [0:0] - read-write - - - - - ITM_DEVARCH - 0x00000fbc - Provides CoreSight discovery information for the ITM - 0x47701a01 - - - ARCHITECT - Defines the architect of the component. Bits [31:28] are the JEP106 continuation code (JEP106 bank ID, minus 1) and bits [27:21] are the JEP106 ID code. - [31:21] - read-only - - - PRESENT - Defines that the DEVARCH register is present - [20:20] - read-only - - - REVISION - Defines the architecture revision of the component - [19:16] - read-only - - - ARCHVER - Defines the architecture version of the component - [15:12] - read-only - - - ARCHPART - Defines the architecture of the component - [11:0] - read-only - - - - - ITM_DEVTYPE - 0x00000fcc - Provides CoreSight discovery information for the ITM - 0x00000043 - - - SUB - Component sub-type - [7:4] - read-only - - - MAJOR - Component major type - [3:0] - read-only - - - - - ITM_PIDR4 - 0x00000fd0 - Provides CoreSight discovery information for the ITM - 0x00000004 - - - SIZE - See CoreSight Architecture Specification - [7:4] - read-only - - - DES_2 - See CoreSight Architecture Specification - [3:0] - read-only - - - - - ITM_PIDR5 - 0x00000fd4 - Provides CoreSight discovery information for the ITM - 0x00000000 - - - ITM_PIDR5 - [31:0] - read-write - - - - - ITM_PIDR6 - 0x00000fd8 - Provides CoreSight discovery information for the ITM - 0x00000000 - - - ITM_PIDR6 - [31:0] - read-write - - - - - ITM_PIDR7 - 0x00000fdc - Provides CoreSight discovery information for the ITM - 0x00000000 - - - ITM_PIDR7 - [31:0] - read-write - - - - - ITM_PIDR0 - 0x00000fe0 - Provides CoreSight discovery information for the ITM - 0x00000021 - - - PART_0 - See CoreSight Architecture Specification - [7:0] - read-only - - - - - ITM_PIDR1 - 0x00000fe4 - Provides CoreSight discovery information for the ITM - 0x000000bd - - - DES_0 - See CoreSight Architecture Specification - [7:4] - read-only - - - PART_1 - See CoreSight Architecture Specification - [3:0] - read-only - - - - - ITM_PIDR2 - 0x00000fe8 - Provides CoreSight discovery information for the ITM - 0x0000000b - - - REVISION - See CoreSight Architecture Specification - [7:4] - read-only - - - JEDEC - See CoreSight Architecture Specification - [3:3] - read-only - - - DES_1 - See CoreSight Architecture Specification - [2:0] - read-only - - - - - ITM_PIDR3 - 0x00000fec - Provides CoreSight discovery information for the ITM - 0x00000000 - - - REVAND - See CoreSight Architecture Specification - [7:4] - read-only - - - CMOD - See CoreSight Architecture Specification - [3:0] - read-only - - - - - ITM_CIDR0 - 0x00000ff0 - Provides CoreSight discovery information for the ITM - 0x0000000d - - - PRMBL_0 - See CoreSight Architecture Specification - [7:0] - read-only - - - - - ITM_CIDR1 - 0x00000ff4 - Provides CoreSight discovery information for the ITM - 0x00000090 - - - CLASS - See CoreSight Architecture Specification - [7:4] - read-only - - - PRMBL_1 - See CoreSight Architecture Specification - [3:0] - read-only - - - - - ITM_CIDR2 - 0x00000ff8 - Provides CoreSight discovery information for the ITM - 0x00000005 - - - PRMBL_2 - See CoreSight Architecture Specification - [7:0] - read-only - - - - - ITM_CIDR3 - 0x00000ffc - Provides CoreSight discovery information for the ITM - 0x000000b1 - - - PRMBL_3 - See CoreSight Architecture Specification - [7:0] - read-only - - - - - DWT_CTRL - 0x00001000 - Provides configuration and status information for the DWT unit, and used to control features of the unit - 0x73741824 - - - NUMCOMP - Number of DWT comparators implemented - [31:28] - read-only - - - NOTRCPKT - Indicates whether the implementation does not support trace - [27:27] - read-only - - - NOEXTTRIG - Reserved, RAZ - [26:26] - read-only - - - NOCYCCNT - Indicates whether the implementation does not include a cycle counter - [25:25] - read-only - - - NOPRFCNT - Indicates whether the implementation does not include the profiling counters - [24:24] - read-only - - - CYCDISS - Controls whether the cycle counter is disabled in Secure state - [23:23] - read-write - - - CYCEVTENA - Enables Event Counter packet generation on POSTCNT underflow - [22:22] - read-write - - - FOLDEVTENA - Enables DWT_FOLDCNT counter - [21:21] - read-write - - - LSUEVTENA - Enables DWT_LSUCNT counter - [20:20] - read-write - - - SLEEPEVTENA - Enable DWT_SLEEPCNT counter - [19:19] - read-write - - - EXCEVTENA - Enables DWT_EXCCNT counter - [18:18] - read-write - - - CPIEVTENA - Enables DWT_CPICNT counter - [17:17] - read-write - - - EXTTRCENA - Enables generation of Exception Trace packets - [16:16] - read-write - - - PCSAMPLENA - Enables use of POSTCNT counter as a timer for Periodic PC Sample packet generation - [12:12] - read-write - - - SYNCTAP - Selects the position of the synchronization packet counter tap on the CYCCNT counter. This determines the Synchronization packet rate - [11:10] - read-write - - - CYCTAP - Selects the position of the POSTCNT tap on the CYCCNT counter - [9:9] - read-write - - - POSTINIT - Initial value for the POSTCNT counter - [8:5] - read-write - - - POSTPRESET - Reload value for the POSTCNT counter - [4:1] - read-write - - - CYCCNTENA - Enables CYCCNT - [0:0] - read-write - - - - - DWT_CYCCNT - 0x00001004 - Shows or sets the value of the processor cycle counter, CYCCNT - 0x00000000 - - - CYCCNT - Increments one on each processor clock cycle when DWT_CTRL.CYCCNTENA == 1 and DEMCR.TRCENA == 1. On overflow, CYCCNT wraps to zero - [31:0] - read-write - - - - - DWT_EXCCNT - 0x0000100c - Counts the total cycles spent in exception processing - 0x00000000 - - - EXCCNT - Counts one on each cycle when all of the following are true: - DWT_CTRL.EXCEVTENA == 1 and DEMCR.TRCENA == 1. - No instruction is executed, see DWT_CPICNT. - An exception-entry or exception-exit related operation is in progress. - Either SecureNoninvasiveDebugAllowed() == TRUE, or NS-Req for the operation is set to Non-secure and NoninvasiveDebugAllowed() == TRUE. - [7:0] - read-write - - - - - DWT_LSUCNT - 0x00001014 - Increments on the additional cycles required to execute all load or store instructions - 0x00000000 - - - LSUCNT - Counts one on each cycle when all of the following are true: - DWT_CTRL.LSUEVTENA == 1 and DEMCR.TRCENA == 1. - No instruction is executed, see DWT_CPICNT. - No exception-entry or exception-exit operation is in progress, see DWT_EXCCNT. - A load-store operation is in progress. - Either SecureNoninvasiveDebugAllowed() == TRUE, or NS-Req for the operation is set to Non-secure and NoninvasiveDebugAllowed() == TRUE. - [7:0] - read-write - - - - - DWT_FOLDCNT - 0x00001018 - Increments on the additional cycles required to execute all load or store instructions - 0x00000000 - - - FOLDCNT - Counts on each cycle when all of the following are true: - DWT_CTRL.FOLDEVTENA == 1 and DEMCR.TRCENA == 1. - At least two instructions are executed, see DWT_CPICNT. - Either SecureNoninvasiveDebugAllowed() == TRUE, or the PE is in Non-secure state and NoninvasiveDebugAllowed() == TRUE. The counter is incremented by the number of instructions executed, minus one - [7:0] - read-write - - - - - DWT_COMP0 - 0x00001020 - Provides a reference value for use by watchpoint comparator 0 - 0x00000000 - - - DWT_COMP0 - [31:0] - read-write - - - - - DWT_FUNCTION0 - 0x00001028 - Controls the operation of watchpoint comparator 0 - 0x58000000 - - - ID - Identifies the capabilities for MATCH for comparator *n - [31:27] - read-only - - - MATCHED - Set to 1 when the comparator matches - [24:24] - read-only - - - DATAVSIZE - Defines the size of the object being watched for by Data Value and Data Address comparators - [11:10] - read-write - - - ACTION - Defines the action on a match. This field is ignored and the comparator generates no actions if it is disabled by MATCH - [5:4] - read-write - - - MATCH - Controls the type of match generated by this comparator - [3:0] - read-write - - - - - DWT_COMP1 - 0x00001030 - Provides a reference value for use by watchpoint comparator 1 - 0x00000000 - - - DWT_COMP1 - [31:0] - read-write - - - - - DWT_FUNCTION1 - 0x00001038 - Controls the operation of watchpoint comparator 1 - 0x89000828 - - - ID - Identifies the capabilities for MATCH for comparator *n - [31:27] - read-only - - - MATCHED - Set to 1 when the comparator matches - [24:24] - read-only - - - DATAVSIZE - Defines the size of the object being watched for by Data Value and Data Address comparators - [11:10] - read-write - - - ACTION - Defines the action on a match. This field is ignored and the comparator generates no actions if it is disabled by MATCH - [5:4] - read-write - - - MATCH - Controls the type of match generated by this comparator - [3:0] - read-write - - - - - DWT_COMP2 - 0x00001040 - Provides a reference value for use by watchpoint comparator 2 - 0x00000000 - - - DWT_COMP2 - [31:0] - read-write - - - - - DWT_FUNCTION2 - 0x00001048 - Controls the operation of watchpoint comparator 2 - 0x50000000 - - - ID - Identifies the capabilities for MATCH for comparator *n - [31:27] - read-only - - - MATCHED - Set to 1 when the comparator matches - [24:24] - read-only - - - DATAVSIZE - Defines the size of the object being watched for by Data Value and Data Address comparators - [11:10] - read-write - - - ACTION - Defines the action on a match. This field is ignored and the comparator generates no actions if it is disabled by MATCH - [5:4] - read-write - - - MATCH - Controls the type of match generated by this comparator - [3:0] - read-write - - - - - DWT_COMP3 - 0x00001050 - Provides a reference value for use by watchpoint comparator 3 - 0x00000000 - - - DWT_COMP3 - [31:0] - read-write - - - - - DWT_FUNCTION3 - 0x00001058 - Controls the operation of watchpoint comparator 3 - 0x20000800 - - - ID - Identifies the capabilities for MATCH for comparator *n - [31:27] - read-only - - - MATCHED - Set to 1 when the comparator matches - [24:24] - read-only - - - DATAVSIZE - Defines the size of the object being watched for by Data Value and Data Address comparators - [11:10] - read-write - - - ACTION - Defines the action on a match. This field is ignored and the comparator generates no actions if it is disabled by MATCH - [5:4] - read-write - - - MATCH - Controls the type of match generated by this comparator - [3:0] - read-write - - - - - DWT_DEVARCH - 0x00001fbc - Provides CoreSight discovery information for the DWT - 0x47701a02 - - - ARCHITECT - Defines the architect of the component. Bits [31:28] are the JEP106 continuation code (JEP106 bank ID, minus 1) and bits [27:21] are the JEP106 ID code. - [31:21] - read-only - - - PRESENT - Defines that the DEVARCH register is present - [20:20] - read-only - - - REVISION - Defines the architecture revision of the component - [19:16] - read-only - - - ARCHVER - Defines the architecture version of the component - [15:12] - read-only - - - ARCHPART - Defines the architecture of the component - [11:0] - read-only - - - - - DWT_DEVTYPE - 0x00001fcc - Provides CoreSight discovery information for the DWT - 0x00000000 - - - SUB - Component sub-type - [7:4] - read-only - - - MAJOR - Component major type - [3:0] - read-only - - - - - DWT_PIDR4 - 0x00001fd0 - Provides CoreSight discovery information for the DWT - 0x00000004 - - - SIZE - See CoreSight Architecture Specification - [7:4] - read-only - - - DES_2 - See CoreSight Architecture Specification - [3:0] - read-only - - - - - DWT_PIDR5 - 0x00001fd4 - Provides CoreSight discovery information for the DWT - 0x00000000 - - - DWT_PIDR5 - [31:0] - read-write - - - - - DWT_PIDR6 - 0x00001fd8 - Provides CoreSight discovery information for the DWT - 0x00000000 - - - DWT_PIDR6 - [31:0] - read-write - - - - - DWT_PIDR7 - 0x00001fdc - Provides CoreSight discovery information for the DWT - 0x00000000 - - - DWT_PIDR7 - [31:0] - read-write - - - - - DWT_PIDR0 - 0x00001fe0 - Provides CoreSight discovery information for the DWT - 0x00000021 - - - PART_0 - See CoreSight Architecture Specification - [7:0] - read-only - - - - - DWT_PIDR1 - 0x00001fe4 - Provides CoreSight discovery information for the DWT - 0x000000bd - - - DES_0 - See CoreSight Architecture Specification - [7:4] - read-only - - - PART_1 - See CoreSight Architecture Specification - [3:0] - read-only - - - - - DWT_PIDR2 - 0x00001fe8 - Provides CoreSight discovery information for the DWT - 0x0000000b - - - REVISION - See CoreSight Architecture Specification - [7:4] - read-only - - - JEDEC - See CoreSight Architecture Specification - [3:3] - read-only - - - DES_1 - See CoreSight Architecture Specification - [2:0] - read-only - - - - - DWT_PIDR3 - 0x00001fec - Provides CoreSight discovery information for the DWT - 0x00000000 - - - REVAND - See CoreSight Architecture Specification - [7:4] - read-only - - - CMOD - See CoreSight Architecture Specification - [3:0] - read-only - - - - - DWT_CIDR0 - 0x00001ff0 - Provides CoreSight discovery information for the DWT - 0x0000000d - - - PRMBL_0 - See CoreSight Architecture Specification - [7:0] - read-only - - - - - DWT_CIDR1 - 0x00001ff4 - Provides CoreSight discovery information for the DWT - 0x00000090 - - - CLASS - See CoreSight Architecture Specification - [7:4] - read-only - - - PRMBL_1 - See CoreSight Architecture Specification - [3:0] - read-only - - - - - DWT_CIDR2 - 0x00001ff8 - Provides CoreSight discovery information for the DWT - 0x00000005 - - - PRMBL_2 - See CoreSight Architecture Specification - [7:0] - read-only - - - - - DWT_CIDR3 - 0x00001ffc - Provides CoreSight discovery information for the DWT - 0x000000b1 - - - PRMBL_3 - See CoreSight Architecture Specification - [7:0] - read-only - - - - - FP_CTRL - 0x00002000 - Provides FPB implementation information, and the global enable for the FPB unit - 0x60005580 - - - REV - Flash Patch and Breakpoint Unit architecture revision - [31:28] - read-only - - - NUM_CODE_14_12_ - Indicates the number of implemented instruction address comparators. Zero indicates no Instruction Address comparators are implemented. The Instruction Address comparators are numbered from 0 to NUM_CODE - 1 - [14:12] - read-only - - - NUM_LIT - Indicates the number of implemented literal address comparators. The Literal Address comparators are numbered from NUM_CODE to NUM_CODE + NUM_LIT - 1 - [11:8] - read-only - - - NUM_CODE_7_4_ - Indicates the number of implemented instruction address comparators. Zero indicates no Instruction Address comparators are implemented. The Instruction Address comparators are numbered from 0 to NUM_CODE - 1 - [7:4] - read-only - - - KEY - Writes to the FP_CTRL are ignored unless KEY is concurrently written to one - [1:1] - read-write - - - ENABLE - Enables the FPB - [0:0] - read-write - - - - - FP_REMAP - 0x00002004 - Indicates whether the implementation supports Flash Patch remap and, if it does, holds the target address for remap - 0x00000000 - - - RMPSPT - Indicates whether the FPB unit supports the Flash Patch remap function - [29:29] - read-only - - - REMAP - Holds the bits[28:5] of the Flash Patch remap address - [28:5] - read-only - - - - - FP_COMP0 - 0x00002008 - Holds an address for comparison. The effect of the match depends on the configuration of the FPB and whether the comparator is an instruction address comparator or a literal address comparator - 0x00000000 - - - BE - Selects between flashpatch and breakpoint functionality - [0:0] - read-write - - - - - FP_COMP1 - 0x0000200c - Holds an address for comparison. The effect of the match depends on the configuration of the FPB and whether the comparator is an instruction address comparator or a literal address comparator - 0x00000000 - - - BE - Selects between flashpatch and breakpoint functionality - [0:0] - read-write - - - - - FP_COMP2 - 0x00002010 - Holds an address for comparison. The effect of the match depends on the configuration of the FPB and whether the comparator is an instruction address comparator or a literal address comparator - 0x00000000 - - - BE - Selects between flashpatch and breakpoint functionality - [0:0] - read-write - - - - - FP_COMP3 - 0x00002014 - Holds an address for comparison. The effect of the match depends on the configuration of the FPB and whether the comparator is an instruction address comparator or a literal address comparator - 0x00000000 - - - BE - Selects between flashpatch and breakpoint functionality - [0:0] - read-write - - - - - FP_COMP4 - 0x00002018 - Holds an address for comparison. The effect of the match depends on the configuration of the FPB and whether the comparator is an instruction address comparator or a literal address comparator - 0x00000000 - - - BE - Selects between flashpatch and breakpoint functionality - [0:0] - read-write - - - - - FP_COMP5 - 0x0000201c - Holds an address for comparison. The effect of the match depends on the configuration of the FPB and whether the comparator is an instruction address comparator or a literal address comparator - 0x00000000 - - - BE - Selects between flashpatch and breakpoint functionality - [0:0] - read-write - - - - - FP_COMP6 - 0x00002020 - Holds an address for comparison. The effect of the match depends on the configuration of the FPB and whether the comparator is an instruction address comparator or a literal address comparator - 0x00000000 - - - BE - Selects between flashpatch and breakpoint functionality - [0:0] - read-write - - - - - FP_COMP7 - 0x00002024 - Holds an address for comparison. The effect of the match depends on the configuration of the FPB and whether the comparator is an instruction address comparator or a literal address comparator - 0x00000000 - - - BE - Selects between flashpatch and breakpoint functionality - [0:0] - read-write - - - - - FP_DEVARCH - 0x00002fbc - Provides CoreSight discovery information for the FPB - 0x47701a03 - - - ARCHITECT - Defines the architect of the component. Bits [31:28] are the JEP106 continuation code (JEP106 bank ID, minus 1) and bits [27:21] are the JEP106 ID code. - [31:21] - read-only - - - PRESENT - Defines that the DEVARCH register is present - [20:20] - read-only - - - REVISION - Defines the architecture revision of the component - [19:16] - read-only - - - ARCHVER - Defines the architecture version of the component - [15:12] - read-only - - - ARCHPART - Defines the architecture of the component - [11:0] - read-only - - - - - FP_DEVTYPE - 0x00002fcc - Provides CoreSight discovery information for the FPB - 0x00000000 - - - SUB - Component sub-type - [7:4] - read-only - - - MAJOR - Component major type - [3:0] - read-only - - - - - FP_PIDR4 - 0x00002fd0 - Provides CoreSight discovery information for the FP - 0x00000004 - - - SIZE - See CoreSight Architecture Specification - [7:4] - read-only - - - DES_2 - See CoreSight Architecture Specification - [3:0] - read-only - - - - - FP_PIDR5 - 0x00002fd4 - Provides CoreSight discovery information for the FP - 0x00000000 - - - FP_PIDR5 - [31:0] - read-write - - - - - FP_PIDR6 - 0x00002fd8 - Provides CoreSight discovery information for the FP - 0x00000000 - - - FP_PIDR6 - [31:0] - read-write - - - - - FP_PIDR7 - 0x00002fdc - Provides CoreSight discovery information for the FP - 0x00000000 - - - FP_PIDR7 - [31:0] - read-write - - - - - FP_PIDR0 - 0x00002fe0 - Provides CoreSight discovery information for the FP - 0x00000021 - - - PART_0 - See CoreSight Architecture Specification - [7:0] - read-only - - - - - FP_PIDR1 - 0x00002fe4 - Provides CoreSight discovery information for the FP - 0x000000bd - - - DES_0 - See CoreSight Architecture Specification - [7:4] - read-only - - - PART_1 - See CoreSight Architecture Specification - [3:0] - read-only - - - - - FP_PIDR2 - 0x00002fe8 - Provides CoreSight discovery information for the FP - 0x0000000b - - - REVISION - See CoreSight Architecture Specification - [7:4] - read-only - - - JEDEC - See CoreSight Architecture Specification - [3:3] - read-only - - - DES_1 - See CoreSight Architecture Specification - [2:0] - read-only - - - - - FP_PIDR3 - 0x00002fec - Provides CoreSight discovery information for the FP - 0x00000000 - - - REVAND - See CoreSight Architecture Specification - [7:4] - read-only - - - CMOD - See CoreSight Architecture Specification - [3:0] - read-only - - - - - FP_CIDR0 - 0x00002ff0 - Provides CoreSight discovery information for the FP - 0x0000000d - - - PRMBL_0 - See CoreSight Architecture Specification - [7:0] - read-only - - - - - FP_CIDR1 - 0x00002ff4 - Provides CoreSight discovery information for the FP - 0x00000090 - - - CLASS - See CoreSight Architecture Specification - [7:4] - read-only - - - PRMBL_1 - See CoreSight Architecture Specification - [3:0] - read-only - - - - - FP_CIDR2 - 0x00002ff8 - Provides CoreSight discovery information for the FP - 0x00000005 - - - PRMBL_2 - See CoreSight Architecture Specification - [7:0] - read-only - - - - - FP_CIDR3 - 0x00002ffc - Provides CoreSight discovery information for the FP - 0x000000b1 - - - PRMBL_3 - See CoreSight Architecture Specification - [7:0] - read-only - - - - - ICTR - 0x0000e004 - Provides information about the interrupt controller - 0x00000001 - - - INTLINESNUM - Indicates the number of the highest implemented register in each of the NVIC control register sets, or in the case of NVIC_IPR*n, 4×INTLINESNUM - [3:0] - read-only - - - - - ACTLR - 0x0000e008 - Provides IMPLEMENTATION DEFINED configuration and control options - 0x00000000 - - - EXTEXCLALL - External Exclusives Allowed with no MPU - [29:29] - read-write - - - DISITMATBFLUSH - Disable ATB Flush - [12:12] - read-write - - - FPEXCODIS - Disable FPU exception outputs - [10:10] - read-write - - - DISOOFP - Disable out-of-order FP instruction completion - [9:9] - read-write - - - DISFOLD - Disable dual-issue. - [2:2] - read-write - - - DISMCYCINT - Disable dual-issue. - [0:0] - read-write - - - - - SYST_CSR - 0x0000e010 - Use the SysTick Control and Status Register to enable the SysTick features. - 0x00000000 - - - COUNTFLAG - Returns 1 if timer counted to 0 since last time this was read. Clears on read by application or debugger. - [16:16] - read-only - - - CLKSOURCE - SysTick clock source. Always reads as one if SYST_CALIB reports NOREF. - Selects the SysTick timer clock source: - 0 = External reference clock. - 1 = Processor clock. - [2:2] - read-write - - - TICKINT - Enables SysTick exception request: - 0 = Counting down to zero does not assert the SysTick exception request. - 1 = Counting down to zero to asserts the SysTick exception request. - [1:1] - read-write - - - ENABLE - Enable SysTick counter: - 0 = Counter disabled. - 1 = Counter enabled. - [0:0] - read-write - - - - - SYST_RVR - 0x0000e014 - Use the SysTick Reload Value Register to specify the start value to load into the current value register when the counter reaches 0. It can be any value between 0 and 0x00FFFFFF. A start value of 0 is possible, but has no effect because the SysTick interrupt and COUNTFLAG are activated when counting from 1 to 0. The reset value of this register is UNKNOWN. - To generate a multi-shot timer with a period of N processor clock cycles, use a RELOAD value of N-1. For example, if the SysTick interrupt is required every 100 clock pulses, set RELOAD to 99. - 0x00000000 - - - RELOAD - Value to load into the SysTick Current Value Register when the counter reaches 0. - [23:0] - read-write - - - - - SYST_CVR - 0x0000e018 - Use the SysTick Current Value Register to find the current value in the register. The reset value of this register is UNKNOWN. - 0x00000000 - - - CURRENT - Reads return the current value of the SysTick counter. This register is write-clear. Writing to it with any value clears the register to 0. Clearing this register also clears the COUNTFLAG bit of the SysTick Control and Status Register. - [23:0] - read-write - - - - - SYST_CALIB - 0x0000e01c - Use the SysTick Calibration Value Register to enable software to scale to any required speed using divide and multiply. - 0x00000000 - - - NOREF - If reads as 1, the Reference clock is not provided - the CLKSOURCE bit of the SysTick Control and Status register will be forced to 1 and cannot be cleared to 0. - [31:31] - read-only - - - SKEW - If reads as 1, the calibration value for 10ms is inexact (due to clock frequency). - [30:30] - read-only - - - TENMS - An optional Reload value to be used for 10ms (100Hz) timing, subject to system clock skew errors. If the value reads as 0, the calibration value is not known. - [23:0] - read-only - - - - - NVIC_ISER0 - 0x0000e100 - Enables or reads the enabled state of each group of 32 interrupts - 0x00000000 - - - SETENA - For SETENA[m] in NVIC_ISER*n, indicates whether interrupt 32*n + m is enabled - [31:0] - read-write - - - - - NVIC_ISER1 - 0x0000e104 - Enables or reads the enabled state of each group of 32 interrupts - 0x00000000 - - - SETENA - For SETENA[m] in NVIC_ISER*n, indicates whether interrupt 32*n + m is enabled - [31:0] - read-write - - - - - NVIC_ICER0 - 0x0000e180 - Clears or reads the enabled state of each group of 32 interrupts - 0x00000000 - - - CLRENA - For CLRENA[m] in NVIC_ICER*n, indicates whether interrupt 32*n + m is enabled - [31:0] - read-write - - - - - NVIC_ICER1 - 0x0000e184 - Clears or reads the enabled state of each group of 32 interrupts - 0x00000000 - - - CLRENA - For CLRENA[m] in NVIC_ICER*n, indicates whether interrupt 32*n + m is enabled - [31:0] - read-write - - - - - NVIC_ISPR0 - 0x0000e200 - Enables or reads the pending state of each group of 32 interrupts - 0x00000000 - - - SETPEND - For SETPEND[m] in NVIC_ISPR*n, indicates whether interrupt 32*n + m is pending - [31:0] - read-write - - - - - NVIC_ISPR1 - 0x0000e204 - Enables or reads the pending state of each group of 32 interrupts - 0x00000000 - - - SETPEND - For SETPEND[m] in NVIC_ISPR*n, indicates whether interrupt 32*n + m is pending - [31:0] - read-write - - - - - NVIC_ICPR0 - 0x0000e280 - Clears or reads the pending state of each group of 32 interrupts - 0x00000000 - - - CLRPEND - For CLRPEND[m] in NVIC_ICPR*n, indicates whether interrupt 32*n + m is pending - [31:0] - read-write - - - - - NVIC_ICPR1 - 0x0000e284 - Clears or reads the pending state of each group of 32 interrupts - 0x00000000 - - - CLRPEND - For CLRPEND[m] in NVIC_ICPR*n, indicates whether interrupt 32*n + m is pending - [31:0] - read-write - - - - - NVIC_IABR0 - 0x0000e300 - For each group of 32 interrupts, shows the active state of each interrupt - 0x00000000 - - - ACTIVE - For ACTIVE[m] in NVIC_IABR*n, indicates the active state for interrupt 32*n+m - [31:0] - read-write - - - - - NVIC_IABR1 - 0x0000e304 - For each group of 32 interrupts, shows the active state of each interrupt - 0x00000000 - - - ACTIVE - For ACTIVE[m] in NVIC_IABR*n, indicates the active state for interrupt 32*n+m - [31:0] - read-write - - - - - NVIC_ITNS0 - 0x0000e380 - For each group of 32 interrupts, determines whether each interrupt targets Non-secure or Secure state - 0x00000000 - - - ITNS - For ITNS[m] in NVIC_ITNS*n, `IAAMO the target Security state for interrupt 32*n+m - [31:0] - read-write - - - - - NVIC_ITNS1 - 0x0000e384 - For each group of 32 interrupts, determines whether each interrupt targets Non-secure or Secure state - 0x00000000 - - - ITNS - For ITNS[m] in NVIC_ITNS*n, `IAAMO the target Security state for interrupt 32*n+m - [31:0] - read-write - - - - - NVIC_IPR0 - 0x0000e400 - Sets or reads interrupt priorities - 0x00000000 - - - PRI_N3 - For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt - [31:28] - read-write - - - PRI_N2 - For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt - [23:20] - read-write - - - PRI_N1 - For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt - [15:12] - read-write - - - PRI_N0 - For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt - [7:4] - read-write - - - - - NVIC_IPR1 - 0x0000e404 - Sets or reads interrupt priorities - 0x00000000 - - - PRI_N3 - For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt - [31:28] - read-write - - - PRI_N2 - For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt - [23:20] - read-write - - - PRI_N1 - For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt - [15:12] - read-write - - - PRI_N0 - For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt - [7:4] - read-write - - - - - NVIC_IPR2 - 0x0000e408 - Sets or reads interrupt priorities - 0x00000000 - - - PRI_N3 - For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt - [31:28] - read-write - - - PRI_N2 - For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt - [23:20] - read-write - - - PRI_N1 - For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt - [15:12] - read-write - - - PRI_N0 - For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt - [7:4] - read-write - - - - - NVIC_IPR3 - 0x0000e40c - Sets or reads interrupt priorities - 0x00000000 - - - PRI_N3 - For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt - [31:28] - read-write - - - PRI_N2 - For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt - [23:20] - read-write - - - PRI_N1 - For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt - [15:12] - read-write - - - PRI_N0 - For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt - [7:4] - read-write - - - - - NVIC_IPR4 - 0x0000e410 - Sets or reads interrupt priorities - 0x00000000 - - - PRI_N3 - For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt - [31:28] - read-write - - - PRI_N2 - For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt - [23:20] - read-write - - - PRI_N1 - For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt - [15:12] - read-write - - - PRI_N0 - For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt - [7:4] - read-write - - - - - NVIC_IPR5 - 0x0000e414 - Sets or reads interrupt priorities - 0x00000000 - - - PRI_N3 - For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt - [31:28] - read-write - - - PRI_N2 - For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt - [23:20] - read-write - - - PRI_N1 - For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt - [15:12] - read-write - - - PRI_N0 - For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt - [7:4] - read-write - - - - - NVIC_IPR6 - 0x0000e418 - Sets or reads interrupt priorities - 0x00000000 - - - PRI_N3 - For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt - [31:28] - read-write - - - PRI_N2 - For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt - [23:20] - read-write - - - PRI_N1 - For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt - [15:12] - read-write - - - PRI_N0 - For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt - [7:4] - read-write - - - - - NVIC_IPR7 - 0x0000e41c - Sets or reads interrupt priorities - 0x00000000 - - - PRI_N3 - For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt - [31:28] - read-write - - - PRI_N2 - For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt - [23:20] - read-write - - - PRI_N1 - For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt - [15:12] - read-write - - - PRI_N0 - For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt - [7:4] - read-write - - - - - NVIC_IPR8 - 0x0000e420 - Sets or reads interrupt priorities - 0x00000000 - - - PRI_N3 - For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt - [31:28] - read-write - - - PRI_N2 - For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt - [23:20] - read-write - - - PRI_N1 - For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt - [15:12] - read-write - - - PRI_N0 - For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt - [7:4] - read-write - - - - - NVIC_IPR9 - 0x0000e424 - Sets or reads interrupt priorities - 0x00000000 - - - PRI_N3 - For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt - [31:28] - read-write - - - PRI_N2 - For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt - [23:20] - read-write - - - PRI_N1 - For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt - [15:12] - read-write - - - PRI_N0 - For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt - [7:4] - read-write - - - - - NVIC_IPR10 - 0x0000e428 - Sets or reads interrupt priorities - 0x00000000 - - - PRI_N3 - For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt - [31:28] - read-write - - - PRI_N2 - For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt - [23:20] - read-write - - - PRI_N1 - For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt - [15:12] - read-write - - - PRI_N0 - For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt - [7:4] - read-write - - - - - NVIC_IPR11 - 0x0000e42c - Sets or reads interrupt priorities - 0x00000000 - - - PRI_N3 - For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt - [31:28] - read-write - - - PRI_N2 - For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt - [23:20] - read-write - - - PRI_N1 - For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt - [15:12] - read-write - - - PRI_N0 - For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt - [7:4] - read-write - - - - - NVIC_IPR12 - 0x0000e430 - Sets or reads interrupt priorities - 0x00000000 - - - PRI_N3 - For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt - [31:28] - read-write - - - PRI_N2 - For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt - [23:20] - read-write - - - PRI_N1 - For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt - [15:12] - read-write - - - PRI_N0 - For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt - [7:4] - read-write - - - - - NVIC_IPR13 - 0x0000e434 - Sets or reads interrupt priorities - 0x00000000 - - - PRI_N3 - For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt - [31:28] - read-write - - - PRI_N2 - For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt - [23:20] - read-write - - - PRI_N1 - For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt - [15:12] - read-write - - - PRI_N0 - For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt - [7:4] - read-write - - - - - NVIC_IPR14 - 0x0000e438 - Sets or reads interrupt priorities - 0x00000000 - - - PRI_N3 - For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt - [31:28] - read-write - - - PRI_N2 - For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt - [23:20] - read-write - - - PRI_N1 - For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt - [15:12] - read-write - - - PRI_N0 - For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt - [7:4] - read-write - - - - - NVIC_IPR15 - 0x0000e43c - Sets or reads interrupt priorities - 0x00000000 - - - PRI_N3 - For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt - [31:28] - read-write - - - PRI_N2 - For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt - [23:20] - read-write - - - PRI_N1 - For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt - [15:12] - read-write - - - PRI_N0 - For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt - [7:4] - read-write - - - - - CPUID - 0x0000ed00 - Provides identification information for the PE, including an implementer code for the device and a device ID number - 0x411fd210 - - - IMPLEMENTER - This field must hold an implementer code that has been assigned by ARM - [31:24] - read-only - - - VARIANT - IMPLEMENTATION DEFINED variant number. Typically, this field is used to distinguish between different product variants, or major revisions of a product - [23:20] - read-only - - - ARCHITECTURE - Defines the Architecture implemented by the PE - [19:16] - read-only - - - PARTNO - IMPLEMENTATION DEFINED primary part number for the device - [15:4] - read-only - - - REVISION - IMPLEMENTATION DEFINED revision number for the device - [3:0] - read-only - - - - - ICSR - 0x0000ed04 - Controls and provides status information for NMI, PendSV, SysTick and interrupts - 0x00000000 - - - PENDNMISET - Indicates whether the NMI exception is pending - [31:31] - read-only - - - PENDNMICLR - Allows the NMI exception pend state to be cleared - [30:30] - read-write - - - PENDSVSET - Indicates whether the PendSV `FTSSS exception is pending - [28:28] - read-only - - - PENDSVCLR - Allows the PendSV exception pend state to be cleared `FTSSS - [27:27] - read-write - - - PENDSTSET - Indicates whether the SysTick `FTSSS exception is pending - [26:26] - read-only - - - PENDSTCLR - Allows the SysTick exception pend state to be cleared `FTSSS - [25:25] - read-write - - - STTNS - Controls whether in a single SysTick implementation, the SysTick is Secure or Non-secure - [24:24] - read-write - - - ISRPREEMPT - Indicates whether a pending exception will be serviced on exit from debug halt state - [23:23] - read-only - - - ISRPENDING - Indicates whether an external interrupt, generated by the NVIC, is pending - [22:22] - read-only - - - VECTPENDING - The exception number of the highest priority pending and enabled interrupt - [20:12] - read-only - - - RETTOBASE - In Handler mode, indicates whether there is more than one active exception - [11:11] - read-only - - - VECTACTIVE - The exception number of the current executing exception - [8:0] - read-only - - - - - VTOR - 0x0000ed08 - The VTOR indicates the offset of the vector table base address from memory address 0x00000000. - 0x00000000 - - - TBLOFF - Vector table base offset field. It contains bits[31:7] of the offset of the table base from the bottom of the memory map. - [31:7] - read-write - - - - - AIRCR - 0x0000ed0c - Use the Application Interrupt and Reset Control Register to: determine data endianness, clear all active state information from debug halt mode, request a system reset. - 0x00000000 - - - VECTKEY - Register key: - Reads as Unknown - On writes, write 0x05FA to VECTKEY, otherwise the write is ignored. - [31:16] - read-write - - - ENDIANESS - Data endianness implemented: - 0 = Little-endian. - [15:15] - read-only - - - PRIS - Prioritize Secure exceptions. The value of this bit defines whether Secure exception priority boosting is enabled. - 0 Priority ranges of Secure and Non-secure exceptions are identical. - 1 Non-secure exceptions are de-prioritized. - [14:14] - read-write - - - BFHFNMINS - BusFault, HardFault, and NMI Non-secure enable. - 0 BusFault, HardFault, and NMI are Secure. - 1 BusFault and NMI are Non-secure and exceptions can target Non-secure HardFault. - [13:13] - read-write - - - PRIGROUP - Interrupt priority grouping field. This field determines the split of group priority from subpriority. - See https://developer.arm.com/documentation/100235/0004/the-cortex-m33-peripherals/system-control-block/application-interrupt-and-reset-control-register?lang=en - [10:8] - read-write - - - SYSRESETREQS - System reset request, Secure state only. - 0 SYSRESETREQ functionality is available to both Security states. - 1 SYSRESETREQ functionality is only available to Secure state. - [3:3] - read-write - - - SYSRESETREQ - Writing 1 to this bit causes the SYSRESETREQ signal to the outer system to be asserted to request a reset. The intention is to force a large system reset of all major components except for debug. The C_HALT bit in the DHCSR is cleared as a result of the system reset requested. The debugger does not lose contact with the device. - [2:2] - read-write - - - VECTCLRACTIVE - Clears all active state information for fixed and configurable exceptions. This bit: is self-clearing, can only be set by the DAP when the core is halted. When set: clears all active exception status of the processor, forces a return to Thread mode, forces an IPSR of 0. A debugger must re-initialize the stack. - [1:1] - read-write - - - - - SCR - 0x0000ed10 - System Control Register. Use the System Control Register for power-management functions: signal to the system when the processor can enter a low power state, control how the processor enters and exits low power states. - 0x00000000 - - - SEVONPEND - Send Event on Pending bit: - 0 = Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded. - 1 = Enabled events and all interrupts, including disabled interrupts, can wakeup the processor. - When an event or interrupt becomes pending, the event signal wakes up the processor from WFE. If the - processor is not waiting for an event, the event is registered and affects the next WFE. - The processor also wakes up on execution of an SEV instruction or an external event. - [4:4] - read-write - - - SLEEPDEEPS - 0 SLEEPDEEP is available to both security states - 1 SLEEPDEEP is only available to Secure state - [3:3] - read-write - - - SLEEPDEEP - Controls whether the processor uses sleep or deep sleep as its low power mode: - 0 = Sleep. - 1 = Deep sleep. - [2:2] - read-write - - - SLEEPONEXIT - Indicates sleep-on-exit when returning from Handler mode to Thread mode: - 0 = Do not sleep when returning to Thread mode. - 1 = Enter sleep, or deep sleep, on return from an ISR to Thread mode. - Setting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application. - [1:1] - read-write - - - - - CCR - 0x0000ed14 - Sets or returns configuration and control data - 0x00000201 - - - BP - Enables program flow prediction `FTSSS - [18:18] - read-only - - - IC - This is a global enable bit for instruction caches in the selected Security state - [17:17] - read-only - - - DC - Enables data caching of all data accesses to Normal memory `FTSSS - [16:16] - read-only - - - STKOFHFNMIGN - Controls the effect of a stack limit violation while executing at a requested priority less than 0 - [10:10] - read-write - - - RES1 - Reserved, RES1 - [9:9] - read-only - - - BFHFNMIGN - Determines the effect of precise BusFaults on handlers running at a requested priority less than 0 - [8:8] - read-write - - - DIV_0_TRP - Controls the generation of a DIVBYZERO UsageFault when attempting to perform integer division by zero - [4:4] - read-write - - - UNALIGN_TRP - Controls the trapping of unaligned word or halfword accesses - [3:3] - read-write - - - USERSETMPEND - Determines whether unprivileged accesses are permitted to pend interrupts via the STIR - [1:1] - read-write - - - RES1_1 - Reserved, RES1 - [0:0] - read-only - - - - - SHPR1 - 0x0000ed18 - Sets or returns priority for system handlers 4 - 7 - 0x00000000 - - - PRI_7_3 - Priority of system handler 7, SecureFault - [31:29] - read-write - - - PRI_6_3 - Priority of system handler 6, SecureFault - [23:21] - read-write - - - PRI_5_3 - Priority of system handler 5, SecureFault - [15:13] - read-write - - - PRI_4_3 - Priority of system handler 4, SecureFault - [7:5] - read-write - - - - - SHPR2 - 0x0000ed1c - Sets or returns priority for system handlers 8 - 11 - 0x00000000 - - - PRI_11_3 - Priority of system handler 11, SecureFault - [31:29] - read-write - - - PRI_10 - Reserved, RES0 - [23:16] - read-only - - - PRI_9 - Reserved, RES0 - [15:8] - read-only - - - PRI_8 - Reserved, RES0 - [7:0] - read-only - - - - - SHPR3 - 0x0000ed20 - Sets or returns priority for system handlers 12 - 15 - 0x00000000 - - - PRI_15_3 - Priority of system handler 15, SecureFault - [31:29] - read-write - - - PRI_14_3 - Priority of system handler 14, SecureFault - [23:21] - read-write - - - PRI_13 - Reserved, RES0 - [15:8] - read-only - - - PRI_12_3 - Priority of system handler 12, SecureFault - [7:5] - read-write - - - - - SHCSR - 0x0000ed24 - Provides access to the active and pending status of system exceptions - 0x00000000 - - - HARDFAULTPENDED - `IAAMO the pending state of the HardFault exception `CTTSSS - [21:21] - read-write - - - SECUREFAULTPENDED - `IAAMO the pending state of the SecureFault exception - [20:20] - read-write - - - SECUREFAULTENA - `DW the SecureFault exception is enabled - [19:19] - read-write - - - USGFAULTENA - `DW the UsageFault exception is enabled `FTSSS - [18:18] - read-write - - - BUSFAULTENA - `DW the BusFault exception is enabled - [17:17] - read-write - - - MEMFAULTENA - `DW the MemManage exception is enabled `FTSSS - [16:16] - read-write - - - SVCALLPENDED - `IAAMO the pending state of the SVCall exception `FTSSS - [15:15] - read-write - - - BUSFAULTPENDED - `IAAMO the pending state of the BusFault exception - [14:14] - read-write - - - MEMFAULTPENDED - `IAAMO the pending state of the MemManage exception `FTSSS - [13:13] - read-write - - - USGFAULTPENDED - The UsageFault exception is banked between Security states, `IAAMO the pending state of the UsageFault exception `FTSSS - [12:12] - read-write - - - SYSTICKACT - `IAAMO the active state of the SysTick exception `FTSSS - [11:11] - read-write - - - PENDSVACT - `IAAMO the active state of the PendSV exception `FTSSS - [10:10] - read-write - - - MONITORACT - `IAAMO the active state of the DebugMonitor exception - [8:8] - read-write - - - SVCALLACT - `IAAMO the active state of the SVCall exception `FTSSS - [7:7] - read-write - - - NMIACT - `IAAMO the active state of the NMI exception - [5:5] - read-write - - - SECUREFAULTACT - `IAAMO the active state of the SecureFault exception - [4:4] - read-write - - - USGFAULTACT - `IAAMO the active state of the UsageFault exception `FTSSS - [3:3] - read-write - - - HARDFAULTACT - Indicates and allows limited modification of the active state of the HardFault exception `FTSSS - [2:2] - read-write - - - BUSFAULTACT - `IAAMO the active state of the BusFault exception - [1:1] - read-write - - - MEMFAULTACT - `IAAMO the active state of the MemManage exception `FTSSS - [0:0] - read-write - - - - - CFSR - 0x0000ed28 - Contains the three Configurable Fault Status Registers. - - 31:16 UFSR: Provides information on UsageFault exceptions - - 15:8 BFSR: Provides information on BusFault exceptions - - 7:0 MMFSR: Provides information on MemManage exceptions - 0x00000000 - - - UFSR_DIVBYZERO - Sticky flag indicating whether an integer division by zero error has occurred - [25:25] - read-write - - - UFSR_UNALIGNED - Sticky flag indicating whether an unaligned access error has occurred - [24:24] - read-write - - - UFSR_STKOF - Sticky flag indicating whether a stack overflow error has occurred - [20:20] - read-write - - - UFSR_NOCP - Sticky flag indicating whether a coprocessor disabled or not present error has occurred - [19:19] - read-write - - - UFSR_INVPC - Sticky flag indicating whether an integrity check error has occurred - [18:18] - read-write - - - UFSR_INVSTATE - Sticky flag indicating whether an EPSR.T or EPSR.IT validity error has occurred - [17:17] - read-write - - - UFSR_UNDEFINSTR - Sticky flag indicating whether an undefined instruction error has occurred - [16:16] - read-write - - - BFSR_BFARVALID - Indicates validity of the contents of the BFAR register - [15:15] - read-write - - - BFSR_LSPERR - Records whether a BusFault occurred during FP lazy state preservation - [13:13] - read-write - - - BFSR_STKERR - Records whether a derived BusFault occurred during exception entry stacking - [12:12] - read-write - - - BFSR_UNSTKERR - Records whether a derived BusFault occurred during exception return unstacking - [11:11] - read-write - - - BFSR_IMPRECISERR - Records whether an imprecise data access error has occurred - [10:10] - read-write - - - BFSR_PRECISERR - Records whether a precise data access error has occurred - [9:9] - read-write - - - BFSR_IBUSERR - Records whether a BusFault on an instruction prefetch has occurred - [8:8] - read-write - - - MMFSR - Provides information on MemManage exceptions - [7:0] - read-write - - - - - HFSR - 0x0000ed2c - Shows the cause of any HardFaults - 0x00000000 - - - DEBUGEVT - Indicates when a Debug event has occurred - [31:31] - read-write - - - FORCED - Indicates that a fault with configurable priority has been escalated to a HardFault exception, because it could not be made active, because of priority, or because it was disabled - [30:30] - read-write - - - VECTTBL - Indicates when a fault has occurred because of a vector table read error on exception processing - [1:1] - read-write - - - - - DFSR - 0x0000ed30 - Shows which debug event occurred - 0x00000000 - - - EXTERNAL - Sticky flag indicating whether an External debug request debug event has occurred - [4:4] - read-write - - - VCATCH - Sticky flag indicating whether a Vector catch debug event has occurred - [3:3] - read-write - - - DWTTRAP - Sticky flag indicating whether a Watchpoint debug event has occurred - [2:2] - read-write - - - BKPT - Sticky flag indicating whether a Breakpoint debug event has occurred - [1:1] - read-write - - - HALTED - Sticky flag indicating that a Halt request debug event or Step debug event has occurred - [0:0] - read-write - - - - - MMFAR - 0x0000ed34 - Shows the address of the memory location that caused an MPU fault - 0x00000000 - - - ADDRESS - This register is updated with the address of a location that produced a MemManage fault. The MMFSR shows the cause of the fault, and whether this field is valid. This field is valid only when MMFSR.MMARVALID is set, otherwise it is UNKNOWN - [31:0] - read-write - - - - - BFAR - 0x0000ed38 - Shows the address associated with a precise data access BusFault - 0x00000000 - - - ADDRESS - This register is updated with the address of a location that produced a BusFault. The BFSR shows the reason for the fault. This field is valid only when BFSR.BFARVALID is set, otherwise it is UNKNOWN - [31:0] - read-write - - - - - ID_PFR0 - 0x0000ed40 - Gives top-level information about the instruction set supported by the PE - 0x00000030 - - - STATE1 - T32 instruction set support - [7:4] - read-only - - - STATE0 - A32 instruction set support - [3:0] - read-only - - - - - ID_PFR1 - 0x0000ed44 - Gives information about the programmers' model and Extensions support - 0x00000520 - - - MPROGMOD - Identifies support for the M-Profile programmers' model support - [11:8] - read-only - - - SECURITY - Identifies whether the Security Extension is implemented - [7:4] - read-only - - - - - ID_DFR0 - 0x0000ed48 - Provides top level information about the debug system - 0x00200000 - - - MPROFDBG - Indicates the supported M-profile debug architecture - [23:20] - read-only - - - - - ID_AFR0 - 0x0000ed4c - Provides information about the IMPLEMENTATION DEFINED features of the PE - 0x00000000 - - - IMPDEF3 - IMPLEMENTATION DEFINED meaning - [15:12] - read-only - - - IMPDEF2 - IMPLEMENTATION DEFINED meaning - [11:8] - read-only - - - IMPDEF1 - IMPLEMENTATION DEFINED meaning - [7:4] - read-only - - - IMPDEF0 - IMPLEMENTATION DEFINED meaning - [3:0] - read-only - - - - - ID_MMFR0 - 0x0000ed50 - Provides information about the implemented memory model and memory management support - 0x00101f40 - - - AUXREG - Indicates support for Auxiliary Control Registers - [23:20] - read-only - - - TCM - Indicates support for tightly coupled memories (TCMs) - [19:16] - read-only - - - SHARELVL - Indicates the number of shareability levels implemented - [15:12] - read-only - - - OUTERSHR - Indicates the outermost shareability domain implemented - [11:8] - read-only - - - PMSA - Indicates support for the protected memory system architecture (PMSA) - [7:4] - read-only - - - - - ID_MMFR1 - 0x0000ed54 - Provides information about the implemented memory model and memory management support - 0x00000000 - - - ID_MMFR1 - [31:0] - read-write - - - - - ID_MMFR2 - 0x0000ed58 - Provides information about the implemented memory model and memory management support - 0x01000000 - - - WFISTALL - Indicates the support for Wait For Interrupt (WFI) stalling - [27:24] - read-only - - - - - ID_MMFR3 - 0x0000ed5c - Provides information about the implemented memory model and memory management support - 0x00000000 - - - BPMAINT - Indicates the supported branch predictor maintenance - [11:8] - read-only - - - CMAINTSW - Indicates the supported cache maintenance operations by set/way - [7:4] - read-only - - - CMAINTVA - Indicates the supported cache maintenance operations by address - [3:0] - read-only - - - - - ID_ISAR0 - 0x0000ed60 - Provides information about the instruction set implemented by the PE - 0x08092300 - - - DIVIDE - Indicates the supported Divide instructions - [27:24] - read-only - - - DEBUG - Indicates the implemented Debug instructions - [23:20] - read-only - - - COPROC - Indicates the supported Coprocessor instructions - [19:16] - read-only - - - CMPBRANCH - Indicates the supported combined Compare and Branch instructions - [15:12] - read-only - - - BITFIELD - Indicates the supported bit field instructions - [11:8] - read-only - - - BITCOUNT - Indicates the supported bit count instructions - [7:4] - read-only - - - - - ID_ISAR1 - 0x0000ed64 - Provides information about the instruction set implemented by the PE - 0x05725000 - - - INTERWORK - Indicates the implemented Interworking instructions - [27:24] - read-only - - - IMMEDIATE - Indicates the implemented for data-processing instructions with long immediates - [23:20] - read-only - - - IFTHEN - Indicates the implemented If-Then instructions - [19:16] - read-only - - - EXTEND - Indicates the implemented Extend instructions - [15:12] - read-only - - - - - ID_ISAR2 - 0x0000ed68 - Provides information about the instruction set implemented by the PE - 0x30173426 - - - REVERSAL - Indicates the implemented Reversal instructions - [31:28] - read-only - - - MULTU - Indicates the implemented advanced unsigned Multiply instructions - [23:20] - read-only - - - MULTS - Indicates the implemented advanced signed Multiply instructions - [19:16] - read-only - - - MULT - Indicates the implemented additional Multiply instructions - [15:12] - read-only - - - MULTIACCESSINT - Indicates the support for interruptible multi-access instructions - [11:8] - read-only - - - MEMHINT - Indicates the implemented Memory Hint instructions - [7:4] - read-only - - - LOADSTORE - Indicates the implemented additional load/store instructions - [3:0] - read-only - - - - - ID_ISAR3 - 0x0000ed6c - Provides information about the instruction set implemented by the PE - 0x07895729 - - - TRUENOP - Indicates the implemented true NOP instructions - [27:24] - read-only - - - T32COPY - Indicates the support for T32 non flag-setting MOV instructions - [23:20] - read-only - - - TABBRANCH - Indicates the implemented Table Branch instructions - [19:16] - read-only - - - SYNCHPRIM - Used in conjunction with ID_ISAR4.SynchPrim_frac to indicate the implemented Synchronization Primitive instructions - [15:12] - read-only - - - SVC - Indicates the implemented SVC instructions - [11:8] - read-only - - - SIMD - Indicates the implemented SIMD instructions - [7:4] - read-only - - - SATURATE - Indicates the implemented saturating instructions - [3:0] - read-only - - - - - ID_ISAR4 - 0x0000ed70 - Provides information about the instruction set implemented by the PE - 0x01310132 - - - PSR_M - Indicates the implemented M profile instructions to modify the PSRs - [27:24] - read-only - - - SYNCPRIM_FRAC - Used in conjunction with ID_ISAR3.SynchPrim to indicate the implemented Synchronization Primitive instructions - [23:20] - read-only - - - BARRIER - Indicates the implemented Barrier instructions - [19:16] - read-only - - - WRITEBACK - Indicates the support for writeback addressing modes - [11:8] - read-only - - - WITHSHIFTS - Indicates the support for writeback addressing modes - [7:4] - read-only - - - UNPRIV - Indicates the implemented unprivileged instructions - [3:0] - read-only - - - - - ID_ISAR5 - 0x0000ed74 - Provides information about the instruction set implemented by the PE - 0x00000000 - - - ID_ISAR5 - [31:0] - read-write - - - - - CTR - 0x0000ed7c - Provides information about the architecture of the caches. CTR is RES0 if CLIDR is zero. - 0x8000c000 - - - RES1 - Reserved, RES1 - [31:31] - read-only - - - CWG - Log2 of the number of words of the maximum size of memory that can be overwritten as a result of the eviction of a cache entry that has had a memory location in it modified - [27:24] - read-only - - - ERG - Log2 of the number of words of the maximum size of the reservation granule that has been implemented for the Load-Exclusive and Store-Exclusive instructions - [23:20] - read-only - - - DMINLINE - Log2 of the number of words in the smallest cache line of all the data caches and unified caches that are controlled by the PE - [19:16] - read-only - - - RES1_1 - Reserved, RES1 - [15:14] - read-only - - - IMINLINE - Log2 of the number of words in the smallest cache line of all the instruction caches that are controlled by the PE - [3:0] - read-only - - - - - CPACR - 0x0000ed88 - Specifies the access privileges for coprocessors and the FP Extension - 0x00000000 - - - CP11 - The value in this field is ignored. If the implementation does not include the FP Extension, this field is RAZ/WI. If the value of this bit is not programmed to the same value as the CP10 field, then the value is UNKNOWN - [23:22] - read-write - - - CP10 - Defines the access rights for the floating-point functionality - [21:20] - read-write - - - CP7 - Controls access privileges for coprocessor 7 - [15:14] - read-write - - - CP6 - Controls access privileges for coprocessor 6 - [13:12] - read-write - - - CP5 - Controls access privileges for coprocessor 5 - [11:10] - read-write - - - CP4 - Controls access privileges for coprocessor 4 - [9:8] - read-write - - - CP3 - Controls access privileges for coprocessor 3 - [7:6] - read-write - - - CP2 - Controls access privileges for coprocessor 2 - [5:4] - read-write - - - CP1 - Controls access privileges for coprocessor 1 - [3:2] - read-write - - - CP0 - Controls access privileges for coprocessor 0 - [1:0] - read-write - - - - - NSACR - 0x0000ed8c - Defines the Non-secure access permissions for both the FP Extension and coprocessors CP0 to CP7 - 0x00000000 - - - CP11 - Enables Non-secure access to the Floating-point Extension - [11:11] - read-write - - - CP10 - Enables Non-secure access to the Floating-point Extension - [10:10] - read-write - - - CP7 - Enables Non-secure access to coprocessor CP7 - [7:7] - read-write - - - CP6 - Enables Non-secure access to coprocessor CP6 - [6:6] - read-write - - - CP5 - Enables Non-secure access to coprocessor CP5 - [5:5] - read-write - - - CP4 - Enables Non-secure access to coprocessor CP4 - [4:4] - read-write - - - CP3 - Enables Non-secure access to coprocessor CP3 - [3:3] - read-write - - - CP2 - Enables Non-secure access to coprocessor CP2 - [2:2] - read-write - - - CP1 - Enables Non-secure access to coprocessor CP1 - [1:1] - read-write - - - CP0 - Enables Non-secure access to coprocessor CP0 - [0:0] - read-write - - - - - MPU_TYPE - 0x0000ed90 - The MPU Type Register indicates how many regions the MPU `FTSSS supports - 0x00000800 - - - DREGION - Number of regions supported by the MPU - [15:8] - read-only - - - SEPARATE - Indicates support for separate instructions and data address regions - [0:0] - read-only - - - - - MPU_CTRL - 0x0000ed94 - Enables the MPU and, when the MPU is enabled, controls whether the default memory map is enabled as a background region for privileged accesses, and whether the MPU is enabled for HardFaults, NMIs, and exception handlers when FAULTMASK is set to 1 - 0x00000000 - - - PRIVDEFENA - Controls whether the default memory map is enabled for privileged software - [2:2] - read-write - - - HFNMIENA - Controls whether handlers executing with priority less than 0 access memory with the MPU enabled or disabled. This applies to HardFaults, NMIs, and exception handlers when FAULTMASK is set to 1 - [1:1] - read-write - - - ENABLE - Enables the MPU - [0:0] - read-write - - - - - MPU_RNR - 0x0000ed98 - Selects the region currently accessed by MPU_RBAR and MPU_RLAR - 0x00000000 - - - REGION - Indicates the memory region accessed by MPU_RBAR and MPU_RLAR - [2:0] - read-write - - - - - MPU_RBAR - 0x0000ed9c - Provides indirect read and write access to the base address of the currently selected MPU region `FTSSS - 0x00000000 - - - BASE - Contains bits [31:5] of the lower inclusive limit of the selected MPU memory region. This value is zero extended to provide the base address to be checked against - [31:5] - read-write - - - SH - Defines the Shareability domain of this region for Normal memory - [4:3] - read-write - - - AP - Defines the access permissions for this region - [2:1] - read-write - - - XN - Defines whether code can be executed from this region - [0:0] - read-write - - - - - MPU_RLAR - 0x0000eda0 - Provides indirect read and write access to the limit address of the currently selected MPU region `FTSSS - 0x00000000 - - - LIMIT - Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region. This value is postfixed with 0x1F to provide the limit address to be checked against - [31:5] - read-write - - - ATTRINDX - Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields - [3:1] - read-write - - - EN - Region enable - [0:0] - read-write - - - - - MPU_RBAR_A1 - 0x0000eda4 - Provides indirect read and write access to the base address of the MPU region selected by MPU_RNR[7:2]:(1[1:0]) `FTSSS - 0x00000000 - - - BASE - Contains bits [31:5] of the lower inclusive limit of the selected MPU memory region. This value is zero extended to provide the base address to be checked against - [31:5] - read-write - - - SH - Defines the Shareability domain of this region for Normal memory - [4:3] - read-write - - - AP - Defines the access permissions for this region - [2:1] - read-write - - - XN - Defines whether code can be executed from this region - [0:0] - read-write - - - - - MPU_RLAR_A1 - 0x0000eda8 - Provides indirect read and write access to the limit address of the currently selected MPU region selected by MPU_RNR[7:2]:(1[1:0]) `FTSSS - 0x00000000 - - - LIMIT - Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region. This value is postfixed with 0x1F to provide the limit address to be checked against - [31:5] - read-write - - - ATTRINDX - Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields - [3:1] - read-write - - - EN - Region enable - [0:0] - read-write - - - - - MPU_RBAR_A2 - 0x0000edac - Provides indirect read and write access to the base address of the MPU region selected by MPU_RNR[7:2]:(2[1:0]) `FTSSS - 0x00000000 - - - BASE - Contains bits [31:5] of the lower inclusive limit of the selected MPU memory region. This value is zero extended to provide the base address to be checked against - [31:5] - read-write - - - SH - Defines the Shareability domain of this region for Normal memory - [4:3] - read-write - - - AP - Defines the access permissions for this region - [2:1] - read-write - - - XN - Defines whether code can be executed from this region - [0:0] - read-write - - - - - MPU_RLAR_A2 - 0x0000edb0 - Provides indirect read and write access to the limit address of the currently selected MPU region selected by MPU_RNR[7:2]:(2[1:0]) `FTSSS - 0x00000000 - - - LIMIT - Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region. This value is postfixed with 0x1F to provide the limit address to be checked against - [31:5] - read-write - - - ATTRINDX - Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields - [3:1] - read-write - - - EN - Region enable - [0:0] - read-write - - - - - MPU_RBAR_A3 - 0x0000edb4 - Provides indirect read and write access to the base address of the MPU region selected by MPU_RNR[7:2]:(3[1:0]) `FTSSS - 0x00000000 - - - BASE - Contains bits [31:5] of the lower inclusive limit of the selected MPU memory region. This value is zero extended to provide the base address to be checked against - [31:5] - read-write - - - SH - Defines the Shareability domain of this region for Normal memory - [4:3] - read-write - - - AP - Defines the access permissions for this region - [2:1] - read-write - - - XN - Defines whether code can be executed from this region - [0:0] - read-write - - - - - MPU_RLAR_A3 - 0x0000edb8 - Provides indirect read and write access to the limit address of the currently selected MPU region selected by MPU_RNR[7:2]:(3[1:0]) `FTSSS - 0x00000000 - - - LIMIT - Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region. This value is postfixed with 0x1F to provide the limit address to be checked against - [31:5] - read-write - - - ATTRINDX - Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields - [3:1] - read-write - - - EN - Region enable - [0:0] - read-write - - - - - MPU_MAIR0 - 0x0000edc0 - Along with MPU_MAIR1, provides the memory attribute encodings corresponding to the AttrIndex values - 0x00000000 - - - ATTR3 - Memory attribute encoding for MPU regions with an AttrIndex of 3 - [31:24] - read-write - - - ATTR2 - Memory attribute encoding for MPU regions with an AttrIndex of 2 - [23:16] - read-write - - - ATTR1 - Memory attribute encoding for MPU regions with an AttrIndex of 1 - [15:8] - read-write - - - ATTR0 - Memory attribute encoding for MPU regions with an AttrIndex of 0 - [7:0] - read-write - - - - - MPU_MAIR1 - 0x0000edc4 - Along with MPU_MAIR0, provides the memory attribute encodings corresponding to the AttrIndex values - 0x00000000 - - - ATTR7 - Memory attribute encoding for MPU regions with an AttrIndex of 7 - [31:24] - read-write - - - ATTR6 - Memory attribute encoding for MPU regions with an AttrIndex of 6 - [23:16] - read-write - - - ATTR5 - Memory attribute encoding for MPU regions with an AttrIndex of 5 - [15:8] - read-write - - - ATTR4 - Memory attribute encoding for MPU regions with an AttrIndex of 4 - [7:0] - read-write - - - - - SAU_CTRL - 0x0000edd0 - Allows enabling of the Security Attribution Unit - 0x00000000 - - - ALLNS - When SAU_CTRL.ENABLE is 0 this bit controls if the memory is marked as Non-secure or Secure - [1:1] - read-write - - - ENABLE - Enables the SAU - [0:0] - read-write - - - - - SAU_TYPE - 0x0000edd4 - Indicates the number of regions implemented by the Security Attribution Unit - 0x00000008 - - - SREGION - The number of implemented SAU regions - [7:0] - read-only - - - - - SAU_RNR - 0x0000edd8 - Selects the region currently accessed by SAU_RBAR and SAU_RLAR - 0x00000000 - - - REGION - Indicates the SAU region accessed by SAU_RBAR and SAU_RLAR - [7:0] - read-write - - - - - SAU_RBAR - 0x0000eddc - Provides indirect read and write access to the base address of the currently selected SAU region - 0x00000000 - - - BADDR - Holds bits [31:5] of the base address for the selected SAU region - [31:5] - read-write - - - - - SAU_RLAR - 0x0000ede0 - Provides indirect read and write access to the limit address of the currently selected SAU region - 0x00000000 - - - LADDR - Holds bits [31:5] of the limit address for the selected SAU region - [31:5] - read-write - - - NSC - Controls whether Non-secure state is permitted to execute an SG instruction from this region - [1:1] - read-write - - - ENABLE - SAU region enable - [0:0] - read-write - - - - - SFSR - 0x0000ede4 - Provides information about any security related faults - 0x00000000 - - - LSERR - Sticky flag indicating that an error occurred during lazy state activation or deactivation - [7:7] - read-write - - - SFARVALID - This bit is set when the SFAR register contains a valid value. As with similar fields, such as BFSR.BFARVALID and MMFSR.MMARVALID, this bit can be cleared by other exceptions, such as BusFault - [6:6] - read-write - - - LSPERR - Stick flag indicating that an SAU or IDAU violation occurred during the lazy preservation of floating-point state - [5:5] - read-write - - - INVTRAN - Sticky flag indicating that an exception was raised due to a branch that was not flagged as being domain crossing causing a transition from Secure to Non-secure memory - [4:4] - read-write - - - AUVIOL - Sticky flag indicating that an attempt was made to access parts of the address space that are marked as Secure with NS-Req for the transaction set to Non-secure. This bit is not set if the violation occurred during lazy state preservation. See LSPERR - [3:3] - read-write - - - INVER - This can be caused by EXC_RETURN.DCRS being set to 0 when returning from an exception in the Non-secure state, or by EXC_RETURN.ES being set to 1 when returning from an exception in the Non-secure state - [2:2] - read-write - - - INVIS - This bit is set if the integrity signature in an exception stack frame is found to be invalid during the unstacking operation - [1:1] - read-write - - - INVEP - This bit is set if a function call from the Non-secure state or exception targets a non-SG instruction in the Secure state. This bit is also set if the target address is a SG instruction, but there is no matching SAU/IDAU region with the NSC flag set - [0:0] - read-write - - - - - SFAR - 0x0000ede8 - Shows the address of the memory location that caused a Security violation - 0x00000000 - - - ADDRESS - The address of an access that caused a attribution unit violation. This field is only valid when SFSR.SFARVALID is set. This allows the actual flip flops associated with this register to be shared with other fault address registers. If an implementation chooses to share the storage in this way, care must be taken to not leak Secure address information to the Non-secure state. One way of achieving this is to share the SFAR register with the MMFAR_S register, which is not accessible to the Non-secure state - [31:0] - read-write - - - - - DHCSR - 0x0000edf0 - Controls halting debug - 0x00000000 - - - S_RESTART_ST - Indicates the PE has processed a request to clear DHCSR.C_HALT to 0. That is, either a write to DHCSR that clears DHCSR.C_HALT from 1 to 0, or an External Restart Request - [26:26] - read-only - - - S_RESET_ST - Indicates whether the PE has been reset since the last read of the DHCSR - [25:25] - read-only - - - S_RETIRE_ST - Set to 1 every time the PE retires one of more instructions - [24:24] - read-only - - - S_SDE - Indicates whether Secure invasive debug is allowed - [20:20] - read-only - - - S_LOCKUP - Indicates whether the PE is in Lockup state - [19:19] - read-only - - - S_SLEEP - Indicates whether the PE is sleeping - [18:18] - read-only - - - S_HALT - Indicates whether the PE is in Debug state - [17:17] - read-only - - - S_REGRDY - Handshake flag to transfers through the DCRDR - [16:16] - read-only - - - C_SNAPSTALL - Allow imprecise entry to Debug state - [5:5] - read-write - - - C_MASKINTS - When debug is enabled, the debugger can write to this bit to mask PendSV, SysTick and external configurable interrupts - [3:3] - read-write - - - C_STEP - Enable single instruction step - [2:2] - read-write - - - C_HALT - PE enter Debug state halt request - [1:1] - read-write - - - C_DEBUGEN - Enable Halting debug - [0:0] - read-write - - - - - DCRSR - 0x0000edf4 - With the DCRDR, provides debug access to the general-purpose registers, special-purpose registers, and the FP extension registers. A write to the DCRSR specifies the register to transfer, whether the transfer is a read or write, and starts the transfer - 0x00000000 - - - REGWNR - Specifies the access type for the transfer - [16:16] - read-write - - - REGSEL - Specifies the general-purpose register, special-purpose register, or FP register to transfer - [6:0] - read-write - - - - - DCRDR - 0x0000edf8 - With the DCRSR, provides debug access to the general-purpose registers, special-purpose registers, and the FP Extension registers. If the Main Extension is implemented, it can also be used for message passing between an external debugger and a debug agent running on the PE - 0x00000000 - - - DBGTMP - Provides debug access for reading and writing the general-purpose registers, special-purpose registers, and Floating-point Extension registers - [31:0] - read-write - - - - - DEMCR - 0x0000edfc - Manages vector catch behavior and DebugMonitor handling when debugging - 0x00000000 - - - TRCENA - Global enable for all DWT and ITM features - [24:24] - read-write - - - SDME - Indicates whether the DebugMonitor targets the Secure or the Non-secure state and whether debug events are allowed in Secure state - [20:20] - read-only - - - MON_REQ - DebugMonitor semaphore bit - [19:19] - read-write - - - MON_STEP - Enable DebugMonitor stepping - [18:18] - read-write - - - MON_PEND - Sets or clears the pending state of the DebugMonitor exception - [17:17] - read-write - - - MON_EN - Enable the DebugMonitor exception - [16:16] - read-write - - - VC_SFERR - SecureFault exception halting debug vector catch enable - [11:11] - read-write - - - VC_HARDERR - HardFault exception halting debug vector catch enable - [10:10] - read-write - - - VC_INTERR - Enable halting debug vector catch for faults during exception entry and return - [9:9] - read-write - - - VC_BUSERR - BusFault exception halting debug vector catch enable - [8:8] - read-write - - - VC_STATERR - Enable halting debug trap on a UsageFault exception caused by a state information error, for example an Undefined Instruction exception - [7:7] - read-write - - - VC_CHKERR - Enable halting debug trap on a UsageFault exception caused by a checking error, for example an alignment check error - [6:6] - read-write - - - VC_NOCPERR - Enable halting debug trap on a UsageFault caused by an access to a coprocessor - [5:5] - read-write - - - VC_MMERR - Enable halting debug trap on a MemManage exception - [4:4] - read-write - - - VC_CORERESET - Enable Reset Vector Catch. This causes a warm reset to halt a running system - [0:0] - read-write - - - - - DSCSR - 0x0000ee08 - Provides control and status information for Secure debug - 0x00000000 - - - CDSKEY - Writes to the CDS bit are ignored unless CDSKEY is concurrently written to zero - [17:17] - read-write - - - CDS - This field indicates the current Security state of the processor - [16:16] - read-write - - - SBRSEL - If SBRSELEN is 1 this bit selects whether the Non-secure or the Secure version of the memory-mapped Banked registers are accessible to the debugger - [1:1] - read-write - - - SBRSELEN - Controls whether the SBRSEL field or the current Security state of the processor selects which version of the memory-mapped Banked registers are accessed to the debugger - [0:0] - read-write - - - - - STIR - 0x0000ef00 - Provides a mechanism for software to generate an interrupt - 0x00000000 - - - INTID - Indicates the interrupt to be pended. The value written is (ExceptionNumber - 16) - [8:0] - read-write - - - - - FPCCR - 0x0000ef34 - Holds control data for the Floating-point extension - 0x20000472 - - - ASPEN - When this bit is set to 1, execution of a floating-point instruction sets the CONTROL.FPCA bit to 1 - [31:31] - read-write - - - LSPEN - Enables lazy context save of floating-point state - [30:30] - read-write - - - LSPENS - This bit controls whether the LSPEN bit is writeable from the Non-secure state - [29:29] - read-write - - - CLRONRET - Clear floating-point caller saved registers on exception return - [28:28] - read-write - - - CLRONRETS - This bit controls whether the CLRONRET bit is writeable from the Non-secure state - [27:27] - read-write - - - TS - Treat floating-point registers as Secure enable - [26:26] - read-write - - - UFRDY - Indicates whether the software executing when the PE allocated the floating-point stack frame was able to set the UsageFault exception to pending - [10:10] - read-write - - - SPLIMVIOL - This bit is banked between the Security states and indicates whether the floating-point context violates the stack pointer limit that was active when lazy state preservation was activated. SPLIMVIOL modifies the lazy floating-point state preservation behavior - [9:9] - read-write - - - MONRDY - Indicates whether the software executing when the PE allocated the floating-point stack frame was able to set the DebugMonitor exception to pending - [8:8] - read-write - - - SFRDY - Indicates whether the software executing when the PE allocated the floating-point stack frame was able to set the SecureFault exception to pending. This bit is only present in the Secure version of the register, and behaves as RAZ/WI when accessed from the Non-secure state - [7:7] - read-write - - - BFRDY - Indicates whether the software executing when the PE allocated the floating-point stack frame was able to set the BusFault exception to pending - [6:6] - read-write - - - MMRDY - Indicates whether the software executing when the PE allocated the floating-point stack frame was able to set the MemManage exception to pending - [5:5] - read-write - - - HFRDY - Indicates whether the software executing when the PE allocated the floating-point stack frame was able to set the HardFault exception to pending - [4:4] - read-write - - - THREAD - Indicates the PE mode when it allocated the floating-point stack frame - [3:3] - read-write - - - S - Security status of the floating-point context. This bit is only present in the Secure version of the register, and behaves as RAZ/WI when accessed from the Non-secure state. This bit is updated whenever lazy state preservation is activated, or when a floating-point instruction is executed - [2:2] - read-write - - - USER - Indicates the privilege level of the software executing when the PE allocated the floating-point stack frame - [1:1] - read-write - - - LSPACT - Indicates whether lazy preservation of the floating-point state is active - [0:0] - read-write - - - - - FPCAR - 0x0000ef38 - Holds the location of the unpopulated floating-point register space allocated on an exception stack frame - 0x00000000 - - - ADDRESS - The location of the unpopulated floating-point register space allocated on an exception stack frame - [31:3] - read-write - - - - - FPDSCR - 0x0000ef3c - Holds the default values for the floating-point status control data that the PE assigns to the FPSCR when it creates a new floating-point context - 0x00000000 - - - AHP - Default value for FPSCR.AHP - [26:26] - read-write - - - DN - Default value for FPSCR.DN - [25:25] - read-write - - - FZ - Default value for FPSCR.FZ - [24:24] - read-write - - - RMODE - Default value for FPSCR.RMode - [23:22] - read-write - - - - - MVFR0 - 0x0000ef40 - Describes the features provided by the Floating-point Extension - 0x60540601 - - - FPROUND - Indicates the rounding modes supported by the FP Extension - [31:28] - read-only - - - FPSQRT - Indicates the support for FP square root operations - [23:20] - read-only - - - FPDIVIDE - Indicates the support for FP divide operations - [19:16] - read-only - - - FPDP - Indicates support for FP double-precision operations - [11:8] - read-only - - - FPSP - Indicates support for FP single-precision operations - [7:4] - read-only - - - SIMDREG - Indicates size of FP register file - [3:0] - read-only - - - - - MVFR1 - 0x0000ef44 - Describes the features provided by the Floating-point Extension - 0x85000089 - - - FMAC - Indicates whether the FP Extension implements the fused multiply accumulate instructions - [31:28] - read-only - - - FPHP - Indicates whether the FP Extension implements half-precision FP conversion instructions - [27:24] - read-only - - - FPDNAN - Indicates whether the FP hardware implementation supports NaN propagation - [7:4] - read-only - - - FPFTZ - Indicates whether subnormals are always flushed-to-zero - [3:0] - read-only - - - - - MVFR2 - 0x0000ef48 - Describes the features provided by the Floating-point Extension - 0x00000060 - - - FPMISC - Indicates support for miscellaneous FP features - [7:4] - read-only - - - - - DDEVARCH - 0x0000efbc - Provides CoreSight discovery information for the SCS - 0x47702a04 - - - ARCHITECT - Defines the architect of the component. Bits [31:28] are the JEP106 continuation code (JEP106 bank ID, minus 1) and bits [27:21] are the JEP106 ID code. - [31:21] - read-only - - - PRESENT - Defines that the DEVARCH register is present - [20:20] - read-only - - - REVISION - Defines the architecture revision of the component - [19:16] - read-only - - - ARCHVER - Defines the architecture version of the component - [15:12] - read-only - - - ARCHPART - Defines the architecture of the component - [11:0] - read-only - - - - - DDEVTYPE - 0x0000efcc - Provides CoreSight discovery information for the SCS - 0x00000000 - - - SUB - Component sub-type - [7:4] - read-only - - - MAJOR - CoreSight major type - [3:0] - read-only - - - - - DPIDR4 - 0x0000efd0 - Provides CoreSight discovery information for the SCS - 0x00000004 - - - SIZE - See CoreSight Architecture Specification - [7:4] - read-only - - - DES_2 - See CoreSight Architecture Specification - [3:0] - read-only - - - - - DPIDR5 - 0x0000efd4 - Provides CoreSight discovery information for the SCS - 0x00000000 - - - DPIDR5 - [31:0] - read-write - - - - - DPIDR6 - 0x0000efd8 - Provides CoreSight discovery information for the SCS - 0x00000000 - - - DPIDR6 - [31:0] - read-write - - - - - DPIDR7 - 0x0000efdc - Provides CoreSight discovery information for the SCS - 0x00000000 - - - DPIDR7 - [31:0] - read-write - - - - - DPIDR0 - 0x0000efe0 - Provides CoreSight discovery information for the SCS - 0x00000021 - - - PART_0 - See CoreSight Architecture Specification - [7:0] - read-only - - - - - DPIDR1 - 0x0000efe4 - Provides CoreSight discovery information for the SCS - 0x000000bd - - - DES_0 - See CoreSight Architecture Specification - [7:4] - read-only - - - PART_1 - See CoreSight Architecture Specification - [3:0] - read-only - - - - - DPIDR2 - 0x0000efe8 - Provides CoreSight discovery information for the SCS - 0x0000000b - - - REVISION - See CoreSight Architecture Specification - [7:4] - read-only - - - JEDEC - See CoreSight Architecture Specification - [3:3] - read-only - - - DES_1 - See CoreSight Architecture Specification - [2:0] - read-only - - - - - DPIDR3 - 0x0000efec - Provides CoreSight discovery information for the SCS - 0x00000000 - - - REVAND - See CoreSight Architecture Specification - [7:4] - read-only - - - CMOD - See CoreSight Architecture Specification - [3:0] - read-only - - - - - DCIDR0 - 0x0000eff0 - Provides CoreSight discovery information for the SCS - 0x0000000d - - - PRMBL_0 - See CoreSight Architecture Specification - [7:0] - read-only - - - - - DCIDR1 - 0x0000eff4 - Provides CoreSight discovery information for the SCS - 0x00000090 - - - CLASS - See CoreSight Architecture Specification - [7:4] - read-only - - - PRMBL_1 - See CoreSight Architecture Specification - [3:0] - read-only - - - - - DCIDR2 - 0x0000eff8 - Provides CoreSight discovery information for the SCS - 0x00000005 - - - PRMBL_2 - See CoreSight Architecture Specification - [7:0] - read-only - - - - - DCIDR3 - 0x0000effc - Provides CoreSight discovery information for the SCS - 0x000000b1 - - - PRMBL_3 - See CoreSight Architecture Specification - [7:0] - read-only - - - - - TRCPRGCTLR - 0x00041004 - Programming Control Register - 0x00000000 - - - EN - Trace Unit Enable - [0:0] - read-write - - - - - TRCSTATR - 0x0004100c - The TRCSTATR indicates the ETM-Teal status - 0x00000000 - - - PMSTABLE - Indicates whether the ETM-Teal registers are stable and can be read - [1:1] - read-only - - - IDLE - Indicates that the trace unit is inactive - [0:0] - read-only - - - - - TRCCONFIGR - 0x00041010 - The TRCCONFIGR sets the basic tracing options for the trace unit - 0x00000000 - - - RS - Return stack enable - [12:12] - read-write - - - TS - Global timestamp tracing - [11:11] - read-write - - - COND - Conditional instruction tracing - [10:5] - read-write - - - CCI - Cycle counting in instruction trace - [4:4] - read-write - - - BB - Branch broadcast mode - [3:3] - read-write - - - - - TRCEVENTCTL0R - 0x00041020 - The TRCEVENTCTL0R controls the tracing of events in the trace stream. The events also drive the ETM-Teal external outputs. - 0x00000000 - - - TYPE1 - Selects the resource type for event 1 - [15:15] - read-write - - - SEL1 - Selects the resource number, based on the value of TYPE1: When TYPE1 is 0, selects a single selected resource from 0-15 defined by SEL1[2:0]. When TYPE1 is 1, selects a Boolean combined resource pair from 0-7 defined by SEL1[2:0] - [10:8] - read-write - - - TYPE0 - Selects the resource type for event 0 - [7:7] - read-write - - - SEL0 - Selects the resource number, based on the value of TYPE0: When TYPE1 is 0, selects a single selected resource from 0-15 defined by SEL0[2:0]. When TYPE1 is 1, selects a Boolean combined resource pair from 0-7 defined by SEL0[2:0] - [2:0] - read-write - - - - - TRCEVENTCTL1R - 0x00041024 - The TRCEVENTCTL1R controls how the events selected by TRCEVENTCTL0R behave - 0x00000000 - - - LPOVERRIDE - Low power state behavior override - [12:12] - read-write - - - ATB - ATB enabled - [11:11] - read-write - - - INSTEN1 - One bit per event, to enable generation of an event element in the instruction trace stream when the selected event occurs - [1:1] - read-write - - - INSTEN0 - One bit per event, to enable generation of an event element in the instruction trace stream when the selected event occurs - [0:0] - read-write - - - - - TRCSTALLCTLR - 0x0004102c - The TRCSTALLCTLR enables ETM-Teal to stall the processor if the ETM-Teal FIFO goes over the programmed level to minimize risk of overflow - 0x00000000 - - - INSTPRIORITY - Reserved, RES0 - [10:10] - read-only - - - ISTALL - Stall processor based on instruction trace buffer space - [8:8] - read-write - - - LEVEL - Threshold at which stalling becomes active. This provides four levels. This level can be varied to optimize the level of invasion caused by stalling, balanced against the risk of a FIFO overflow - [3:2] - read-write - - - - - TRCTSCTLR - 0x00041030 - The TRCTSCTLR controls the insertion of global timestamps into the trace stream. A timestamp is always inserted into the instruction trace stream - 0x00000000 - - - TYPE0 - Selects the resource type for event 0 - [7:7] - read-write - - - SEL0 - Selects the resource number, based on the value of TYPE0: When TYPE1 is 0, selects a single selected resource from 0-15 defined by SEL0[2:0]. When TYPE1 is 1, selects a Boolean combined resource pair from 0-7 defined by SEL0[2:0] - [1:0] - read-write - - - - - TRCSYNCPR - 0x00041034 - The TRCSYNCPR specifies the period of trace synchronization of the trace streams. TRCSYNCPR defines a number of bytes of trace between requests for trace synchronization. This value is always a power of two - 0x0000000a - - - PERIOD - Defines the number of bytes of trace between trace synchronization requests as a total of the number of bytes generated by the instruction stream. The number of bytes is 2N where N is the value of this field: - A value of zero disables these periodic trace synchronization requests, but does not disable other trace synchronization requests. - The minimum value that can be programmed, other than zero, is 8, providing a minimum trace synchronization period of 256 bytes. - The maximum value is 20, providing a maximum trace synchronization period of 2^20 bytes - [4:0] - read-only - - - - - TRCCCCTLR - 0x00041038 - The TRCCCCTLR sets the threshold value for instruction trace cycle counting. The threshold represents the minimum interval between cycle count trace packets - 0x00000000 - - - THRESHOLD - Instruction trace cycle count threshold - [11:0] - read-write - - - - - TRCVICTLR - 0x00041080 - The TRCVICTLR controls instruction trace filtering - 0x00000000 - - - EXLEVEL_S3 - In Secure state, each bit controls whether instruction tracing is enabled for the corresponding exception level - [19:19] - read-write - - - EXLEVEL_S0 - In Secure state, each bit controls whether instruction tracing is enabled for the corresponding exception level - [16:16] - read-write - - - TRCERR - Selects whether a system error exception must always be traced - [11:11] - read-write - - - TRCRESET - Selects whether a reset exception must always be traced - [10:10] - read-write - - - SSSTATUS - Indicates the current status of the start/stop logic - [9:9] - read-write - - - TYPE0 - Selects the resource type for event 0 - [7:7] - read-write - - - SEL0 - Selects the resource number, based on the value of TYPE0: When TYPE1 is 0, selects a single selected resource from 0-15 defined by SEL0[2:0]. When TYPE1 is 1, selects a Boolean combined resource pair from 0-7 defined by SEL0[2:0] - [1:0] - read-write - - - - - TRCCNTRLDVR0 - 0x00041140 - The TRCCNTRLDVR defines the reload value for the reduced function counter - 0x00000000 - - - VALUE - Defines the reload value for the counter. This value is loaded into the counter each time the reload event occurs - [15:0] - read-write - - - - - TRCIDR8 - 0x00041180 - TRCIDR8 - 0x00000000 - - - MAXSPEC - reads as `ImpDef - [31:0] - read-only - - - - - TRCIDR9 - 0x00041184 - TRCIDR9 - 0x00000000 - - - NUMP0KEY - reads as `ImpDef - [31:0] - read-only - - - - - TRCIDR10 - 0x00041188 - TRCIDR10 - 0x00000000 - - - NUMP1KEY - reads as `ImpDef - [31:0] - read-only - - - - - TRCIDR11 - 0x0004118c - TRCIDR11 - 0x00000000 - - - NUMP1SPC - reads as `ImpDef - [31:0] - read-only - - - - - TRCIDR12 - 0x00041190 - TRCIDR12 - 0x00000001 - - - NUMCONDKEY - reads as `ImpDef - [31:0] - read-only - - - - - TRCIDR13 - 0x00041194 - TRCIDR13 - 0x00000000 - - - NUMCONDSPC - reads as `ImpDef - [31:0] - read-only - - - - - TRCIMSPEC - 0x000411c0 - The TRCIMSPEC shows the presence of any IMPLEMENTATION SPECIFIC features, and enables any features that are provided - 0x00000000 - - - SUPPORT - Reserved, RES0 - [3:0] - read-only - - - - - TRCIDR0 - 0x000411e0 - TRCIDR0 - 0x280006e1 - - - COMMOPT - reads as `ImpDef - [29:29] - read-only - - - TSSIZE - reads as `ImpDef - [28:24] - read-only - - - TRCEXDATA - reads as `ImpDef - [17:17] - read-only - - - QSUPP - reads as `ImpDef - [16:15] - read-only - - - QFILT - reads as `ImpDef - [14:14] - read-only - - - CONDTYPE - reads as `ImpDef - [13:12] - read-only - - - NUMEVENT - reads as `ImpDef - [11:10] - read-only - - - RETSTACK - reads as `ImpDef - [9:9] - read-only - - - TRCCCI - reads as `ImpDef - [7:7] - read-only - - - TRCCOND - reads as `ImpDef - [6:6] - read-only - - - TRCBB - reads as `ImpDef - [5:5] - read-only - - - TRCDATA - reads as `ImpDef - [4:3] - read-only - - - INSTP0 - reads as `ImpDef - [2:1] - read-only - - - RES1 - Reserved, RES1 - [0:0] - read-only - - - - - TRCIDR1 - 0x000411e4 - TRCIDR1 - 0x4100f421 - - - DESIGNER - reads as `ImpDef - [31:24] - read-only - - - RES1 - Reserved, RES1 - [15:12] - read-only - - - TRCARCHMAJ - reads as 0b0100 - [11:8] - read-only - - - TRCARCHMIN - reads as 0b0000 - [7:4] - read-only - - - REVISION - reads as `ImpDef - [3:0] - read-only - - - - - TRCIDR2 - 0x000411e8 - TRCIDR2 - 0x00000004 - - - CCSIZE - reads as `ImpDef - [28:25] - read-only - - - DVSIZE - reads as `ImpDef - [24:20] - read-only - - - DASIZE - reads as `ImpDef - [19:15] - read-only - - - VMIDSIZE - reads as `ImpDef - [14:10] - read-only - - - CIDSIZE - reads as `ImpDef - [9:5] - read-only - - - IASIZE - reads as `ImpDef - [4:0] - read-only - - - - - TRCIDR3 - 0x000411ec - TRCIDR3 - 0x0f090004 - - - NOOVERFLOW - reads as `ImpDef - [31:31] - read-only - - - NUMPROC - reads as `ImpDef - [30:28] - read-only - - - SYSSTALL - reads as `ImpDef - [27:27] - read-only - - - STALLCTL - reads as `ImpDef - [26:26] - read-only - - - SYNCPR - reads as `ImpDef - [25:25] - read-only - - - TRCERR - reads as `ImpDef - [24:24] - read-only - - - EXLEVEL_NS - reads as `ImpDef - [23:20] - read-only - - - EXLEVEL_S - reads as `ImpDef - [19:16] - read-only - - - CCITMIN - reads as `ImpDef - [11:0] - read-only - - - - - TRCIDR4 - 0x000411f0 - TRCIDR4 - 0x00114000 - - - NUMVMIDC - reads as `ImpDef - [31:28] - read-only - - - NUMCIDC - reads as `ImpDef - [27:24] - read-only - - - NUMSSCC - reads as `ImpDef - [23:20] - read-only - - - NUMRSPAIR - reads as `ImpDef - [19:16] - read-only - - - NUMPC - reads as `ImpDef - [15:12] - read-only - - - SUPPDAC - reads as `ImpDef - [8:8] - read-only - - - NUMDVC - reads as `ImpDef - [7:4] - read-only - - - NUMACPAIRS - reads as `ImpDef - [3:0] - read-only - - - - - TRCIDR5 - 0x000411f4 - TRCIDR5 - 0x90c70004 - - - REDFUNCNTR - reads as `ImpDef - [31:31] - read-only - - - NUMCNTR - reads as `ImpDef - [30:28] - read-only - - - NUMSEQSTATE - reads as `ImpDef - [27:25] - read-only - - - LPOVERRIDE - reads as `ImpDef - [23:23] - read-only - - - ATBTRIG - reads as `ImpDef - [22:22] - read-only - - - TRACEIDSIZE - reads as 0x07 - [21:16] - read-only - - - NUMEXTINSEL - reads as `ImpDef - [11:9] - read-only - - - NUMEXTIN - reads as `ImpDef - [8:0] - read-only - - - - - TRCIDR6 - 0x000411f8 - TRCIDR6 - 0x00000000 - - - TRCIDR6 - [31:0] - read-write - - - - - TRCIDR7 - 0x000411fc - TRCIDR7 - 0x00000000 - - - TRCIDR7 - [31:0] - read-write - - - - - TRCRSCTLR2 - 0x00041208 - The TRCRSCTLR controls the trace resources - 0x00000000 - - - PAIRINV - Inverts the result of a combined pair of resources. This bit is only implemented on the lower register for a pair of resource selectors - [21:21] - read-write - - - INV - Inverts the selected resources - [20:20] - read-write - - - GROUP - Selects a group of resource - [18:16] - read-write - - - SELECT - Selects one or more resources from the wanted group. One bit is provided per resource from the group - [7:0] - read-write - - - - - TRCRSCTLR3 - 0x0004120c - The TRCRSCTLR controls the trace resources - 0x00000000 - - - PAIRINV - Inverts the result of a combined pair of resources. This bit is only implemented on the lower register for a pair of resource selectors - [21:21] - read-write - - - INV - Inverts the selected resources - [20:20] - read-write - - - GROUP - Selects a group of resource - [18:16] - read-write - - - SELECT - Selects one or more resources from the wanted group. One bit is provided per resource from the group - [7:0] - read-write - - - - - TRCSSCSR - 0x000412a0 - Controls the corresponding single-shot comparator resource - 0x00000000 - - - STATUS - Single-shot status bit. Indicates if any of the comparators, that TRCSSCCRn.SAC or TRCSSCCRn.ARC selects, have matched - [31:31] - read-write - - - PC - Reserved, RES1 - [3:3] - read-only - - - DV - Reserved, RES0 - [2:2] - read-only - - - DA - Reserved, RES0 - [1:1] - read-only - - - INST - Reserved, RES0 - [0:0] - read-only - - - - - TRCSSPCICR - 0x000412c0 - Selects the PE comparator inputs for Single-shot control - 0x00000000 - - - PC - Selects one or more PE comparator inputs for Single-shot control. TRCIDR4.NUMPC defines the size of the PC field. 1 bit is provided for each implemented PE comparator input. For example, if bit[1] == 1 this selects PE comparator input 1 for Single-shot control - [3:0] - read-write - - - - - TRCPDCR - 0x00041310 - Requests the system to provide power to the trace unit - 0x00000000 - - - PU - Powerup request bit: - [3:3] - read-write - - - - - TRCPDSR - 0x00041314 - Returns the following information about the trace unit: - OS Lock status. - Core power domain status. - Power interruption status - 0x00000003 - - - OSLK - OS Lock status bit: - [5:5] - read-only - - - STICKYPD - Sticky powerdown status bit. Indicates whether the trace register state is valid: - [1:1] - read-only - - - POWER - Power status bit: - [0:0] - read-only - - - - - TRCITATBIDR - 0x00041ee4 - Trace Integration ATB Identification Register - 0x00000000 - - - ID - Trace ID - [6:0] - read-write - - - - - TRCITIATBINR - 0x00041ef4 - Trace Integration Instruction ATB In Register - 0x00000000 - - - AFVALIDM - Integration Mode instruction AFVALIDM in - [1:1] - read-write - - - ATREADYM - Integration Mode instruction ATREADYM in - [0:0] - read-write - - - - - TRCITIATBOUTR - 0x00041efc - Trace Integration Instruction ATB Out Register - 0x00000000 - - - AFREADY - Integration Mode instruction AFREADY out - [1:1] - read-write - - - ATVALID - Integration Mode instruction ATVALID out - [0:0] - read-write - - - - - TRCCLAIMSET - 0x00041fa0 - Claim Tag Set Register - 0x0000000f - - - SET3 - When a write to one of these bits occurs, with the value: - [3:3] - read-write - - - SET2 - When a write to one of these bits occurs, with the value: - [2:2] - read-write - - - SET1 - When a write to one of these bits occurs, with the value: - [1:1] - read-write - - - SET0 - When a write to one of these bits occurs, with the value: - [0:0] - read-write - - - - - TRCCLAIMCLR - 0x00041fa4 - Claim Tag Clear Register - 0x00000000 - - - CLR3 - When a write to one of these bits occurs, with the value: - [3:3] - read-write - - - CLR2 - When a write to one of these bits occurs, with the value: - [2:2] - read-write - - - CLR1 - When a write to one of these bits occurs, with the value: - [1:1] - read-write - - - CLR0 - When a write to one of these bits occurs, with the value: - [0:0] - read-write - - - - - TRCAUTHSTATUS - 0x00041fb8 - Returns the level of tracing that the trace unit can support - 0x00000000 - - - SNID - Indicates whether the system enables the trace unit to support Secure non-invasive debug: - [7:6] - read-only - - - SID - Indicates whether the trace unit supports Secure invasive debug: - [5:4] - read-only - - - NSNID - Indicates whether the system enables the trace unit to support Non-secure non-invasive debug: - [3:2] - read-only - - - NSID - Indicates whether the trace unit supports Non-secure invasive debug: - [1:0] - read-only - - - - - TRCDEVARCH - 0x00041fbc - TRCDEVARCH - 0x47724a13 - - - ARCHITECT - reads as 0b01000111011 - [31:21] - read-only - - - PRESENT - reads as 0b1 - [20:20] - read-only - - - REVISION - reads as 0b0000 - [19:16] - read-only - - - ARCHID - reads as 0b0100101000010011 - [15:0] - read-only - - - - - TRCDEVID - 0x00041fc8 - TRCDEVID - 0x00000000 - - - TRCDEVID - [31:0] - read-write - - - - - TRCDEVTYPE - 0x00041fcc - TRCDEVTYPE - 0x00000013 - - - SUB - reads as 0b0001 - [7:4] - read-only - - - MAJOR - reads as 0b0011 - [3:0] - read-only - - - - - TRCPIDR4 - 0x00041fd0 - TRCPIDR4 - 0x00000004 - - - SIZE - reads as `ImpDef - [7:4] - read-only - - - DES_2 - reads as `ImpDef - [3:0] - read-only - - - - - TRCPIDR5 - 0x00041fd4 - TRCPIDR5 - 0x00000000 - - - TRCPIDR5 - [31:0] - read-write - - - - - TRCPIDR6 - 0x00041fd8 - TRCPIDR6 - 0x00000000 - - - TRCPIDR6 - [31:0] - read-write - - - - - TRCPIDR7 - 0x00041fdc - TRCPIDR7 - 0x00000000 - - - TRCPIDR7 - [31:0] - read-write - - - - - TRCPIDR0 - 0x00041fe0 - TRCPIDR0 - 0x00000021 - - - PART_0 - reads as `ImpDef - [7:0] - read-only - - - - - TRCPIDR1 - 0x00041fe4 - TRCPIDR1 - 0x000000bd - - - DES_0 - reads as `ImpDef - [7:4] - read-only - - - PART_0 - reads as `ImpDef - [3:0] - read-only - - - - - TRCPIDR2 - 0x00041fe8 - TRCPIDR2 - 0x0000002b - - - REVISION - reads as `ImpDef - [7:4] - read-only - - - JEDEC - reads as 0b1 - [3:3] - read-only - - - DES_0 - reads as `ImpDef - [2:0] - read-only - - - - - TRCPIDR3 - 0x00041fec - TRCPIDR3 - 0x00000000 - - - REVAND - reads as `ImpDef - [7:4] - read-only - - - CMOD - reads as `ImpDef - [3:0] - read-only - - - - - TRCCIDR0 - 0x00041ff0 - TRCCIDR0 - 0x0000000d - - - PRMBL_0 - reads as 0b00001101 - [7:0] - read-only - - - - - TRCCIDR1 - 0x00041ff4 - TRCCIDR1 - 0x00000090 - - - CLASS - reads as 0b1001 - [7:4] - read-only - - - PRMBL_1 - reads as 0b0000 - [3:0] - read-only - - - - - TRCCIDR2 - 0x00041ff8 - TRCCIDR2 - 0x00000005 - - - PRMBL_2 - reads as 0b00000101 - [7:0] - read-only - - - - - TRCCIDR3 - 0x00041ffc - TRCCIDR3 - 0x000000b1 - - - PRMBL_3 - reads as 0b10110001 - [7:0] - read-only - - - - - CTICONTROL - 0x00042000 - CTI Control Register - 0x00000000 - - - GLBEN - Enables or disables the CTI - [0:0] - read-write - - - - - CTIINTACK - 0x00042010 - CTI Interrupt Acknowledge Register - 0x00000000 - - - INTACK - Acknowledges the corresponding ctitrigout output. There is one bit of the register for each ctitrigout output. When a 1 is written to a bit in this register, the corresponding ctitrigout is acknowledged, causing it to be cleared. - [7:0] - read-write - - - - - CTIAPPSET - 0x00042014 - CTI Application Trigger Set Register - 0x00000000 - - - APPSET - Setting a bit HIGH generates a channel event for the selected channel. There is one bit of the register for each channel - [3:0] - read-write - - - - - CTIAPPCLEAR - 0x00042018 - CTI Application Trigger Clear Register - 0x00000000 - - - APPCLEAR - Sets the corresponding bits in the CTIAPPSET to 0. There is one bit of the register for each channel. - [3:0] - read-write - - - - - CTIAPPPULSE - 0x0004201c - CTI Application Pulse Register - 0x00000000 - - - APPULSE - Setting a bit HIGH generates a channel event pulse for the selected channel. There is one bit of the register for each channel. - [3:0] - read-write - - - - - CTIINEN0 - 0x00042020 - CTI Trigger to Channel Enable Registers - 0x00000000 - - - TRIGINEN - Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels - [3:0] - read-write - - - - - CTIINEN1 - 0x00042024 - CTI Trigger to Channel Enable Registers - 0x00000000 - - - TRIGINEN - Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels - [3:0] - read-write - - - - - CTIINEN2 - 0x00042028 - CTI Trigger to Channel Enable Registers - 0x00000000 - - - TRIGINEN - Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels - [3:0] - read-write - - - - - CTIINEN3 - 0x0004202c - CTI Trigger to Channel Enable Registers - 0x00000000 - - - TRIGINEN - Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels - [3:0] - read-write - - - - - CTIINEN4 - 0x00042030 - CTI Trigger to Channel Enable Registers - 0x00000000 - - - TRIGINEN - Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels - [3:0] - read-write - - - - - CTIINEN5 - 0x00042034 - CTI Trigger to Channel Enable Registers - 0x00000000 - - - TRIGINEN - Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels - [3:0] - read-write - - - - - CTIINEN6 - 0x00042038 - CTI Trigger to Channel Enable Registers - 0x00000000 - - - TRIGINEN - Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels - [3:0] - read-write - - - - - CTIINEN7 - 0x0004203c - CTI Trigger to Channel Enable Registers - 0x00000000 - - - TRIGINEN - Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels - [3:0] - read-write - - - - - CTIOUTEN0 - 0x000420a0 - CTI Trigger to Channel Enable Registers - 0x00000000 - - - TRIGOUTEN - Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels. - [3:0] - read-write - - - - - CTIOUTEN1 - 0x000420a4 - CTI Trigger to Channel Enable Registers - 0x00000000 - - - TRIGOUTEN - Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels. - [3:0] - read-write - - - - - CTIOUTEN2 - 0x000420a8 - CTI Trigger to Channel Enable Registers - 0x00000000 - - - TRIGOUTEN - Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels. - [3:0] - read-write - - - - - CTIOUTEN3 - 0x000420ac - CTI Trigger to Channel Enable Registers - 0x00000000 - - - TRIGOUTEN - Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels. - [3:0] - read-write - - - - - CTIOUTEN4 - 0x000420b0 - CTI Trigger to Channel Enable Registers - 0x00000000 - - - TRIGOUTEN - Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels. - [3:0] - read-write - - - - - CTIOUTEN5 - 0x000420b4 - CTI Trigger to Channel Enable Registers - 0x00000000 - - - TRIGOUTEN - Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels. - [3:0] - read-write - - - - - CTIOUTEN6 - 0x000420b8 - CTI Trigger to Channel Enable Registers - 0x00000000 - - - TRIGOUTEN - Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels. - [3:0] - read-write - - - - - CTIOUTEN7 - 0x000420bc - CTI Trigger to Channel Enable Registers - 0x00000000 - - - TRIGOUTEN - Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels. - [3:0] - read-write - - - - - CTITRIGINSTATUS - 0x00042130 - CTI Trigger to Channel Enable Registers - 0x00000000 - - - TRIGINSTATUS - Shows the status of the ctitrigin inputs. There is one bit of the field for each trigger input.Because the register provides a view of the raw ctitrigin inputs, the reset value is UNKNOWN. - [7:0] - read-only - - - - - CTITRIGOUTSTATUS - 0x00042134 - CTI Trigger In Status Register - 0x00000000 - - - TRIGOUTSTATUS - Shows the status of the ctitrigout outputs. There is one bit of the field for each trigger output. - [7:0] - read-only - - - - - CTICHINSTATUS - 0x00042138 - CTI Channel In Status Register - 0x00000000 - - - CTICHOUTSTATUS - Shows the status of the ctichout outputs. There is one bit of the field for each channel output - [3:0] - read-only - - - - - CTIGATE - 0x00042140 - Enable CTI Channel Gate register - 0x0000000f - - - CTIGATEEN3 - Enable ctichout3. Set to 0 to disable channel propagation. - [3:3] - read-write - - - CTIGATEEN2 - Enable ctichout2. Set to 0 to disable channel propagation. - [2:2] - read-write - - - CTIGATEEN1 - Enable ctichout1. Set to 0 to disable channel propagation. - [1:1] - read-write - - - CTIGATEEN0 - Enable ctichout0. Set to 0 to disable channel propagation. - [0:0] - read-write - - - - - ASICCTL - 0x00042144 - External Multiplexer Control register - 0x00000000 - - - ASICCTL - [31:0] - read-write - - - - - ITCHOUT - 0x00042ee4 - Integration Test Channel Output register - 0x00000000 - - - CTCHOUT - Sets the value of the ctichout outputs - [3:0] - read-write - - - - - ITTRIGOUT - 0x00042ee8 - Integration Test Trigger Output register - 0x00000000 - - - CTTRIGOUT - Sets the value of the ctitrigout outputs - [7:0] - read-write - - - - - ITCHIN - 0x00042ef4 - Integration Test Channel Input register - 0x00000000 - - - CTCHIN - Reads the value of the ctichin inputs. - [3:0] - read-only - - - - - ITCTRL - 0x00042f00 - Integration Mode Control register - 0x00000000 - - - IME - Integration Mode Enable - [0:0] - read-write - - - - - DEVARCH - 0x00042fbc - Device Architecture register - 0x47701a14 - - - ARCHITECT - Indicates the component architect - [31:21] - read-only - - - PRESENT - Indicates whether the DEVARCH register is present - [20:20] - read-only - - - REVISION - Indicates the architecture revision - [19:16] - read-only - - - ARCHID - Indicates the component - [15:0] - read-only - - - - - DEVID - 0x00042fc8 - Device Configuration register - 0x00040800 - - - NUMCH - Number of ECT channels available - [19:16] - read-only - - - NUMTRIG - Number of ECT triggers available. - [15:8] - read-only - - - EXTMUXNUM - Indicates the number of multiplexers available on Trigger Inputs and Trigger Outputs that are using asicctl. The default value of 0b00000 indicates that no multiplexing is present. This value of this bit depends on the Verilog define EXTMUXNUM that you must change accordingly. - [4:0] - read-only - - - - - DEVTYPE - 0x00042fcc - Device Type Identifier register - 0x00000014 - - - SUB - Sub-classification of the type of the debug component as specified in the ARM Architecture Specification within the major classification as specified in the MAJOR field. - [7:4] - read-only - - - MAJOR - Major classification of the type of the debug component as specified in the ARM Architecture Specification for this debug and trace component. - [3:0] - read-only - - - - - PIDR4 - 0x00042fd0 - CoreSight Peripheral ID4 - 0x00000004 - - - SIZE - Always 0b0000. Indicates that the device only occupies 4KB of memory - [7:4] - read-only - - - DES_2 - Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component. - [3:0] - read-only - - - - - PIDR5 - 0x00042fd4 - CoreSight Peripheral ID5 - 0x00000000 - - - PIDR5 - [31:0] - read-write - - - - - PIDR6 - 0x00042fd8 - CoreSight Peripheral ID6 - 0x00000000 - - - PIDR6 - [31:0] - read-write - - - - - PIDR7 - 0x00042fdc - CoreSight Peripheral ID7 - 0x00000000 - - - PIDR7 - [31:0] - read-write - - - - - PIDR0 - 0x00042fe0 - CoreSight Peripheral ID0 - 0x00000021 - - - PART_0 - Bits[7:0] of the 12-bit part number of the component. The designer of the component assigns this part number. - [7:0] - read-only - - - - - PIDR1 - 0x00042fe4 - CoreSight Peripheral ID1 - 0x000000bd - - - DES_0 - Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component. - [7:4] - read-only - - - PART_1 - Bits[11:8] of the 12-bit part number of the component. The designer of the component assigns this part number. - [3:0] - read-only - - - - - PIDR2 - 0x00042fe8 - CoreSight Peripheral ID2 - 0x0000000b - - - REVISION - This device is at r1p0 - [7:4] - read-only - - - JEDEC - Always 1. Indicates that the JEDEC-assigned designer ID is used. - [3:3] - read-only - - - DES_1 - Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component. - [2:0] - read-only - - - - - PIDR3 - 0x00042fec - CoreSight Peripheral ID3 - 0x00000000 - - - REVAND - Indicates minor errata fixes specific to the revision of the component being used, for example metal fixes after implementation. In most cases, this field is 0b0000. ARM recommends that the component designers ensure that a metal fix can change this field if required, for example, by driving it from registers that reset to 0b0000. - [7:4] - read-only - - - CMOD - Customer Modified. Indicates whether the customer has modified the behavior of the component. In most cases, this field is 0b0000. Customers change this value when they make authorized modifications to this component. - [3:0] - read-only - - - - - CIDR0 - 0x00042ff0 - CoreSight Component ID0 - 0x0000000d - - - PRMBL_0 - Preamble[0]. Contains bits[7:0] of the component identification code - [7:0] - read-only - - - - - CIDR1 - 0x00042ff4 - CoreSight Component ID1 - 0x00000090 - - - CLASS - Class of the component, for example, whether the component is a ROM table or a generic CoreSight component. Contains bits[15:12] of the component identification code. - [7:4] - read-only - - - PRMBL_1 - Preamble[1]. Contains bits[11:8] of the component identification code. - [3:0] - read-only - - - - - CIDR2 - 0x00042ff8 - CoreSight Component ID2 - 0x00000005 - - - PRMBL_2 - Preamble[2]. Contains bits[23:16] of the component identification code. - [7:0] - read-only - - - - - CIDR3 - 0x00042ffc - CoreSight Component ID3 - 0x000000b1 - - - PRMBL_3 - Preamble[3]. Contains bits[31:24] of the component identification code. - [7:0] - read-only - - - - - - - PPB_NS - 0xe0020000 - - - QMI - QSPI Memory Interface. - - Provides a memory-mapped interface to up to two SPI/DSPI/QSPI flash or PSRAM devices. Also provides a serial interface for programming and configuration of the external device. - 0x400d0000 - - 0 - 84 - registers - - - - DIRECT_CSR - 0x00000000 - Control and status for direct serial mode - - Direct serial mode allows the processor to send and receive raw serial frames, for programming, configuration and control of the external memory devices. Only SPI mode 0 (CPOL=0 CPHA=0) is supported. - 0x01800000 - - - RXDELAY - Delay the read data sample timing, in units of one half of a system clock cycle. (Not necessarily half of an SCK cycle.) - [31:30] - read-write - - - CLKDIV - Clock divisor for direct serial mode. Divisors of 1..255 are encoded directly, and the maximum divisor of 256 is encoded by a value of CLKDIV=0. - - The clock divisor can be changed on-the-fly by software, without halting or otherwise coordinating with the serial interface. The serial interface will sample the latest clock divisor each time it begins the transmission of a new byte. - [29:22] - read-write - - - RXLEVEL - Current level of DIRECT_RX FIFO - [20:18] - read-only - - - RXFULL - When 1, the DIRECT_RX FIFO is currently full. The serial interface will be stalled until data is popped; the interface will not begin a new serial frame when the DIRECT_TX FIFO is empty or the DIRECT_RX FIFO is full. - [17:17] - read-only - - - RXEMPTY - When 1, the DIRECT_RX FIFO is currently empty. If the processor attempts to read more data, the FIFO state is not affected, but the value returned to the processor is undefined. - [16:16] - read-only - - - TXLEVEL - Current level of DIRECT_TX FIFO - [14:12] - read-only - - - TXEMPTY - When 1, the DIRECT_TX FIFO is currently empty. Unless the processor pushes more data, transmission will stop and BUSY will go low once the current 8-bit serial frame completes. - [11:11] - read-only - - - TXFULL - When 1, the DIRECT_TX FIFO is currently full. If the processor tries to write more data, that data will be ignored. - [10:10] - read-only - - - AUTO_CS1N - When 1, automatically assert the CS1n chip select line whenever the BUSY flag is set. - [7:7] - read-write - - - AUTO_CS0N - When 1, automatically assert the CS0n chip select line whenever the BUSY flag is set. - [6:6] - read-write - - - ASSERT_CS1N - When 1, assert (i.e. drive low) the CS1n chip select line. - - Note that this applies even when DIRECT_CSR_EN is 0. - [3:3] - read-write - - - ASSERT_CS0N - When 1, assert (i.e. drive low) the CS0n chip select line. - - Note that this applies even when DIRECT_CSR_EN is 0. - [2:2] - read-write - - - BUSY - Direct mode busy flag. If 1, data is currently being shifted in/out (or would be if the interface were not stalled on the RX FIFO), and the chip select must not yet be deasserted. - - The busy flag will also be set to 1 if a memory-mapped transfer is still in progress when direct mode is enabled. Direct mode blocks new memory-mapped transfers, but can't halt a transfer that is already in progress. If there is a chance that memory-mapped transfers may be in progress, the busy flag should be polled for 0 before asserting the chip select. - - (In practice you will usually discover this timing condition through other means, because any subsequent memory-mapped transfers when direct mode is enabled will return bus errors, which are difficult to ignore.) - [1:1] - read-only - - - EN - Enable direct mode. - - In direct mode, software controls the chip select lines, and can perform direct SPI transfers by pushing data to the DIRECT_TX FIFO, and popping the same amount of data from the DIRECT_RX FIFO. - - Memory-mapped accesses will generate bus errors when direct serial mode is enabled. - [0:0] - read-write - - - - - DIRECT_TX - 0x00000004 - Transmit FIFO for direct mode - 0x00000000 - - - NOPUSH - Inhibit the RX FIFO push that would correspond to this TX FIFO entry. - - Useful to avoid garbage appearing in the RX FIFO when pushing the command at the beginning of a SPI transfer. - [20:20] - write-only - - - OE - Output enable (active-high). For single width (SPI), this field is ignored, and SD0 is always set to output, with SD1 always set to input. - - For dual and quad width (DSPI/QSPI), this sets whether the relevant SDx pads are set to output whilst transferring this FIFO record. In this case the command/address should have OE set, and the data transfer should have OE set or clear depending on the direction of the transfer. - [19:19] - write-only - - - DWIDTH - Data width. If 0, hardware will transmit the 8 LSBs of the DIRECT_TX DATA field, and return an 8-bit value in the 8 LSBs of DIRECT_RX. If 1, the full 16-bit width is used. 8-bit and 16-bit transfers can be mixed freely. - [18:18] - write-only - - - IWIDTH - Configure whether this FIFO record is transferred with single/dual/quad interface width (0/1/2). Different widths can be mixed freely. - [17:16] - write-only - - - S - 0 - Single width - - - D - 1 - Dual width - - - Q - 2 - Quad width - - - - - DATA - Data pushed here will be clocked out falling edges of SCK (or before the very first rising edge of SCK, if this is the first pulse). For each byte clocked out, the interface will simultaneously sample one byte, on rising edges of SCK, and push this to the DIRECT_RX FIFO. - - For 16-bit data, the least-significant byte is transmitted first. - [15:0] - write-only - - - - - DIRECT_RX - 0x00000008 - Receive FIFO for direct mode - 0x00000000 - - - DIRECT_RX - With each byte clocked out on the serial interface, one byte will simultaneously be clocked in, and will appear in this FIFO. The serial interface will stall when this FIFO is full, to avoid dropping data. - - When 16-bit data is pushed into the TX FIFO, the corresponding RX FIFO push will also contain 16 bits of data. The least-significant byte is the first one received. - [15:0] - read-only - modify - - - - - M0_TIMING - 0x0000000c - Timing configuration register for memory address window 0. - 0x40000004 - - - COOLDOWN - Chip select cooldown period. When a memory transfer finishes, the chip select remains asserted for 64 x COOLDOWN system clock cycles, plus half an SCK clock period (rounded up for odd SCK divisors). After this cooldown expires, the chip select is always deasserted to save power. - - If the next memory access arrives within the cooldown period, the QMI may be able to append more SCK cycles to the currently ongoing SPI transfer, rather than starting a new transfer. This reduces access latency and increases bus throughput. - - Specifically, the next access must be in the same direction (read/write), access the same memory window (chip select 0/1), and follow sequentially the address of the last transfer. If any of these are false, the new access will first deassert the chip select, then begin a new transfer. - - If COOLDOWN is 0, the address alignment configured by PAGEBREAK has been reached, or the total chip select assertion limit MAX_SELECT has been reached, the cooldown period is skipped, and the chip select will always be deasserted one half SCK period after the transfer finishes. - [31:30] - read-write - - - PAGEBREAK - When page break is enabled, chip select will automatically deassert when crossing certain power-of-2-aligned address boundaries. The next access will always begin a new read/write SPI burst, even if the address of the next access follows in sequence with the last access before the page boundary. - - Some flash and PSRAM devices forbid crossing page boundaries with a single read/write transfer, or restrict the operating frequency for transfers that do cross page a boundary. This option allows the QMI to safely support those devices. - - This field has no effect when COOLDOWN is disabled. - [29:28] - read-write - - - NONE - 0 - No page boundary is enforced - - - 256 - 1 - Break bursts crossing a 256-byte page boundary - - - 1024 - 2 - Break bursts crossing a 1024-byte quad-page boundary - - - 4096 - 3 - Break bursts crossing a 4096-byte sector boundary - - - - - SELECT_SETUP - Add up to one additional system clock cycle of setup between chip select assertion and the first rising edge of SCK. - - The default setup time is one half SCK period, which is usually sufficient except for very high SCK frequencies with some flash devices. - [25:25] - read-write - - - SELECT_HOLD - Add up to three additional system clock cycles of active hold between the last falling edge of SCK and the deassertion of this window's chip select. - - The default hold time is one system clock cycle. Note that flash datasheets usually give chip select active hold time from the last *rising* edge of SCK, and so even zero hold from the last falling edge would be safe. - - Note that this is a minimum hold time guaranteed by the QMI: the actual chip select active hold may be slightly longer for read transfers with low clock divisors and/or high sample delays. Specifically, if the point two cycles after the last RX data sample is later than the last SCK falling edge, then the hold time is measured from *this* point. - - Note also that, in case the final SCK pulse is masked to save energy (true for non-DTR reads when COOLDOWN is disabled or PAGE_BREAK is reached), all of QMI's timing logic behaves as though the clock pulse were still present. The SELECT_HOLD time is applied from the point where the last SCK falling edge would be if the clock pulse were not masked. - [24:23] - read-write - - - MAX_SELECT - Enforce a maximum assertion duration for this window's chip select, in units of 64 system clock cycles. If 0, the QMI is permitted to keep the chip select asserted indefinitely when servicing sequential memory accesses (see COOLDOWN). - - This feature is required to meet timing constraints of PSRAM devices, which specify a maximum chip select assertion so they can perform DRAM refresh cycles. See also MIN_DESELECT, which can enforce a minimum deselect time. - - If a memory access is in progress at the time MAX_SELECT is reached, the QMI will wait for the access to complete before deasserting the chip select. This additional time must be accounted for to calculate a safe MAX_SELECT value. In the worst case, this may be a fully-formed serial transfer, including command prefix and address, with a data payload as large as one cache line. - [22:17] - read-write - - - MIN_DESELECT - After this window's chip select is deasserted, it remains deasserted for half an SCK cycle (rounded up to an integer number of system clock cycles), plus MIN_DESELECT additional system clock cycles, before the QMI reasserts either chip select pin. - - Nonzero values may be required for PSRAM devices which enforce a longer minimum CS deselect time, so that they can perform internal DRAM refresh cycles whilst deselected. - [16:12] - read-write - - - RXDELAY - Delay the read data sample timing, in units of one half of a system clock cycle. (Not necessarily half of an SCK cycle.) An RXDELAY of 0 means the sample is captured at the SDI input registers simultaneously with the rising edge of SCK launched from the SCK output register. - - At higher SCK frequencies, RXDELAY may need to be increased to account for the round trip delay of the pads, and the clock-to-Q delay of the QSPI memory device. - [10:8] - read-write - - - CLKDIV - Clock divisor. Odd and even divisors are supported. Defines the SCK clock period in units of 1 system clock cycle. Divisors 1..255 are encoded directly, and a divisor of 256 is encoded with a value of CLKDIV=0. - - The clock divisor can be changed on-the-fly, even when the QMI is currently accessing memory in this address window. All other parameters must only be changed when the QMI is idle. - - If software is increasing CLKDIV in anticipation of an increase in the system clock frequency, a dummy access to either memory window (and appropriate processor barriers/fences) must be inserted after the Mx_TIMING write to ensure the SCK divisor change is in effect _before_ the system clock is changed. - [7:0] - read-write - - - - - M0_RFMT - 0x00000010 - Read transfer format configuration for memory address window 0. - - Configure the bus width of each transfer phase individually, and configure the length or presence of the command prefix, command suffix and dummy/turnaround transfer phases. Only 24-bit addresses are supported. - - The reset value of the M0_RFMT register is configured to support a basic 03h serial read transfer with no additional configuration. - 0x00001000 - - - DTR - Enable double transfer rate (DTR) for read commands: address, suffix and read data phases are active on both edges of SCK. SDO data is launched centre-aligned on each SCK edge, and SDI data is captured on the SCK edge that follows its launch. - - DTR is implemented by halving the clock rate; SCK has a period of 2 x CLK_DIV throughout the transfer. The prefix and dummy phases are still single transfer rate. - - If the suffix is quad-width, it must be 0 or 8 bits in length, to ensure an even number of SCK edges. - [28:28] - read-write - - - DUMMY_LEN - Length of dummy phase between command suffix and data phase, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single) - [18:16] - read-write - - - NONE - 0 - No dummy phase - - - 4 - 1 - 4 dummy bits - - - 8 - 2 - 8 dummy bits - - - 12 - 3 - 12 dummy bits - - - 16 - 4 - 16 dummy bits - - - 20 - 5 - 20 dummy bits - - - 24 - 6 - 24 dummy bits - - - 28 - 7 - 28 dummy bits - - - - - SUFFIX_LEN - Length of post-address command suffix, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single) - - Only values of 0 and 8 bits are supported. - [15:14] - read-write - - - NONE - 0 - No suffix - - - 8 - 2 - 8-bit suffix - - - - - PREFIX_LEN - Length of command prefix, in units of 8 bits. (i.e. 2 cycles for quad width, 4 for dual, 8 for single) - [12:12] - read-write - - - NONE - 0 - No prefix - - - 8 - 1 - 8-bit prefix - - - - - DATA_WIDTH - The width used for the data transfer - [9:8] - read-write - - - S - 0 - Single width - - - D - 1 - Dual width - - - Q - 2 - Quad width - - - - - DUMMY_WIDTH - The width used for the dummy phase, if any. - - If width is single, SD0/MOSI is held asserted low during the dummy phase, and SD1...SD3 are tristated. If width is dual/quad, all IOs are tristated during the dummy phase. - [7:6] - read-write - - - S - 0 - Single width - - - D - 1 - Dual width - - - Q - 2 - Quad width - - - - - SUFFIX_WIDTH - The width used for the post-address command suffix, if any - [5:4] - read-write - - - S - 0 - Single width - - - D - 1 - Dual width - - - Q - 2 - Quad width - - - - - ADDR_WIDTH - The transfer width used for the address. The address phase always transfers 24 bits in total. - [3:2] - read-write - - - S - 0 - Single width - - - D - 1 - Dual width - - - Q - 2 - Quad width - - - - - PREFIX_WIDTH - The transfer width used for the command prefix, if any - [1:0] - read-write - - - S - 0 - Single width - - - D - 1 - Dual width - - - Q - 2 - Quad width - - - - - - - M0_RCMD - 0x00000014 - Command constants used for reads from memory address window 0. - - The reset value of the M0_RCMD register is configured to support a basic 03h serial read transfer with no additional configuration. - 0x0000a003 - - - SUFFIX - The command suffix bits following the address, if Mx_RFMT_SUFFIX_LEN is nonzero. - [15:8] - read-write - - - PREFIX - The command prefix bits to prepend on each new transfer, if Mx_RFMT_PREFIX_LEN is nonzero. - [7:0] - read-write - - - - - M0_WFMT - 0x00000018 - Write transfer format configuration for memory address window 0. - - Configure the bus width of each transfer phase individually, and configure the length or presence of the command prefix, command suffix and dummy/turnaround transfer phases. Only 24-bit addresses are supported. - - The reset value of the M0_WFMT register is configured to support a basic 02h serial write transfer. However, writes to this window must first be enabled via the XIP_CTRL_WRITABLE_M0 bit, as XIP memory is read-only by default. - 0x00001000 - - - DTR - Enable double transfer rate (DTR) for write commands: address, suffix and write data phases are active on both edges of SCK. SDO data is launched centre-aligned on each SCK edge, and SDI data is captured on the SCK edge that follows its launch. - - DTR is implemented by halving the clock rate; SCK has a period of 2 x CLK_DIV throughout the transfer. The prefix and dummy phases are still single transfer rate. - - If the suffix is quad-width, it must be 0 or 8 bits in length, to ensure an even number of SCK edges. - [28:28] - read-write - - - DUMMY_LEN - Length of dummy phase between command suffix and data phase, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single) - [18:16] - read-write - - - NONE - 0 - No dummy phase - - - 4 - 1 - 4 dummy bits - - - 8 - 2 - 8 dummy bits - - - 12 - 3 - 12 dummy bits - - - 16 - 4 - 16 dummy bits - - - 20 - 5 - 20 dummy bits - - - 24 - 6 - 24 dummy bits - - - 28 - 7 - 28 dummy bits - - - - - SUFFIX_LEN - Length of post-address command suffix, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single) - - Only values of 0 and 8 bits are supported. - [15:14] - read-write - - - NONE - 0 - No suffix - - - 8 - 2 - 8-bit suffix - - - - - PREFIX_LEN - Length of command prefix, in units of 8 bits. (i.e. 2 cycles for quad width, 4 for dual, 8 for single) - [12:12] - read-write - - - NONE - 0 - No prefix - - - 8 - 1 - 8-bit prefix - - - - - DATA_WIDTH - The width used for the data transfer - [9:8] - read-write - - - S - 0 - Single width - - - D - 1 - Dual width - - - Q - 2 - Quad width - - - - - DUMMY_WIDTH - The width used for the dummy phase, if any. - - If width is single, SD0/MOSI is held asserted low during the dummy phase, and SD1...SD3 are tristated. If width is dual/quad, all IOs are tristated during the dummy phase. - [7:6] - read-write - - - S - 0 - Single width - - - D - 1 - Dual width - - - Q - 2 - Quad width - - - - - SUFFIX_WIDTH - The width used for the post-address command suffix, if any - [5:4] - read-write - - - S - 0 - Single width - - - D - 1 - Dual width - - - Q - 2 - Quad width - - - - - ADDR_WIDTH - The transfer width used for the address. The address phase always transfers 24 bits in total. - [3:2] - read-write - - - S - 0 - Single width - - - D - 1 - Dual width - - - Q - 2 - Quad width - - - - - PREFIX_WIDTH - The transfer width used for the command prefix, if any - [1:0] - read-write - - - S - 0 - Single width - - - D - 1 - Dual width - - - Q - 2 - Quad width - - - - - - - M0_WCMD - 0x0000001c - Command constants used for writes to memory address window 0. - - The reset value of the M0_WCMD register is configured to support a basic 02h serial write transfer with no additional configuration. - 0x0000a002 - - - SUFFIX - The command suffix bits following the address, if Mx_WFMT_SUFFIX_LEN is nonzero. - [15:8] - read-write - - - PREFIX - The command prefix bits to prepend on each new transfer, if Mx_WFMT_PREFIX_LEN is nonzero. - [7:0] - read-write - - - - - M1_TIMING - 0x00000020 - Timing configuration register for memory address window 1. - 0x40000004 - - - COOLDOWN - Chip select cooldown period. When a memory transfer finishes, the chip select remains asserted for 64 x COOLDOWN system clock cycles, plus half an SCK clock period (rounded up for odd SCK divisors). After this cooldown expires, the chip select is always deasserted to save power. - - If the next memory access arrives within the cooldown period, the QMI may be able to append more SCK cycles to the currently ongoing SPI transfer, rather than starting a new transfer. This reduces access latency and increases bus throughput. - - Specifically, the next access must be in the same direction (read/write), access the same memory window (chip select 0/1), and follow sequentially the address of the last transfer. If any of these are false, the new access will first deassert the chip select, then begin a new transfer. - - If COOLDOWN is 0, the address alignment configured by PAGEBREAK has been reached, or the total chip select assertion limit MAX_SELECT has been reached, the cooldown period is skipped, and the chip select will always be deasserted one half SCK period after the transfer finishes. - [31:30] - read-write - - - PAGEBREAK - When page break is enabled, chip select will automatically deassert when crossing certain power-of-2-aligned address boundaries. The next access will always begin a new read/write SPI burst, even if the address of the next access follows in sequence with the last access before the page boundary. - - Some flash and PSRAM devices forbid crossing page boundaries with a single read/write transfer, or restrict the operating frequency for transfers that do cross page a boundary. This option allows the QMI to safely support those devices. - - This field has no effect when COOLDOWN is disabled. - [29:28] - read-write - - - NONE - 0 - No page boundary is enforced - - - 256 - 1 - Break bursts crossing a 256-byte page boundary - - - 1024 - 2 - Break bursts crossing a 1024-byte quad-page boundary - - - 4096 - 3 - Break bursts crossing a 4096-byte sector boundary - - - - - SELECT_SETUP - Add up to one additional system clock cycle of setup between chip select assertion and the first rising edge of SCK. - - The default setup time is one half SCK period, which is usually sufficient except for very high SCK frequencies with some flash devices. - [25:25] - read-write - - - SELECT_HOLD - Add up to three additional system clock cycles of active hold between the last falling edge of SCK and the deassertion of this window's chip select. - - The default hold time is one system clock cycle. Note that flash datasheets usually give chip select active hold time from the last *rising* edge of SCK, and so even zero hold from the last falling edge would be safe. - - Note that this is a minimum hold time guaranteed by the QMI: the actual chip select active hold may be slightly longer for read transfers with low clock divisors and/or high sample delays. Specifically, if the point two cycles after the last RX data sample is later than the last SCK falling edge, then the hold time is measured from *this* point. - - Note also that, in case the final SCK pulse is masked to save energy (true for non-DTR reads when COOLDOWN is disabled or PAGE_BREAK is reached), all of QMI's timing logic behaves as though the clock pulse were still present. The SELECT_HOLD time is applied from the point where the last SCK falling edge would be if the clock pulse were not masked. - [24:23] - read-write - - - MAX_SELECT - Enforce a maximum assertion duration for this window's chip select, in units of 64 system clock cycles. If 0, the QMI is permitted to keep the chip select asserted indefinitely when servicing sequential memory accesses (see COOLDOWN). - - This feature is required to meet timing constraints of PSRAM devices, which specify a maximum chip select assertion so they can perform DRAM refresh cycles. See also MIN_DESELECT, which can enforce a minimum deselect time. - - If a memory access is in progress at the time MAX_SELECT is reached, the QMI will wait for the access to complete before deasserting the chip select. This additional time must be accounted for to calculate a safe MAX_SELECT value. In the worst case, this may be a fully-formed serial transfer, including command prefix and address, with a data payload as large as one cache line. - [22:17] - read-write - - - MIN_DESELECT - After this window's chip select is deasserted, it remains deasserted for half an SCK cycle (rounded up to an integer number of system clock cycles), plus MIN_DESELECT additional system clock cycles, before the QMI reasserts either chip select pin. - - Nonzero values may be required for PSRAM devices which enforce a longer minimum CS deselect time, so that they can perform internal DRAM refresh cycles whilst deselected. - [16:12] - read-write - - - RXDELAY - Delay the read data sample timing, in units of one half of a system clock cycle. (Not necessarily half of an SCK cycle.) An RXDELAY of 0 means the sample is captured at the SDI input registers simultaneously with the rising edge of SCK launched from the SCK output register. - - At higher SCK frequencies, RXDELAY may need to be increased to account for the round trip delay of the pads, and the clock-to-Q delay of the QSPI memory device. - [10:8] - read-write - - - CLKDIV - Clock divisor. Odd and even divisors are supported. Defines the SCK clock period in units of 1 system clock cycle. Divisors 1..255 are encoded directly, and a divisor of 256 is encoded with a value of CLKDIV=0. - - The clock divisor can be changed on-the-fly, even when the QMI is currently accessing memory in this address window. All other parameters must only be changed when the QMI is idle. - - If software is increasing CLKDIV in anticipation of an increase in the system clock frequency, a dummy access to either memory window (and appropriate processor barriers/fences) must be inserted after the Mx_TIMING write to ensure the SCK divisor change is in effect _before_ the system clock is changed. - [7:0] - read-write - - - - - M1_RFMT - 0x00000024 - Read transfer format configuration for memory address window 1. - - Configure the bus width of each transfer phase individually, and configure the length or presence of the command prefix, command suffix and dummy/turnaround transfer phases. Only 24-bit addresses are supported. - - The reset value of the M1_RFMT register is configured to support a basic 03h serial read transfer with no additional configuration. - 0x00001000 - - - DTR - Enable double transfer rate (DTR) for read commands: address, suffix and read data phases are active on both edges of SCK. SDO data is launched centre-aligned on each SCK edge, and SDI data is captured on the SCK edge that follows its launch. - - DTR is implemented by halving the clock rate; SCK has a period of 2 x CLK_DIV throughout the transfer. The prefix and dummy phases are still single transfer rate. - - If the suffix is quad-width, it must be 0 or 8 bits in length, to ensure an even number of SCK edges. - [28:28] - read-write - - - DUMMY_LEN - Length of dummy phase between command suffix and data phase, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single) - [18:16] - read-write - - - NONE - 0 - No dummy phase - - - 4 - 1 - 4 dummy bits - - - 8 - 2 - 8 dummy bits - - - 12 - 3 - 12 dummy bits - - - 16 - 4 - 16 dummy bits - - - 20 - 5 - 20 dummy bits - - - 24 - 6 - 24 dummy bits - - - 28 - 7 - 28 dummy bits - - - - - SUFFIX_LEN - Length of post-address command suffix, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single) - - Only values of 0 and 8 bits are supported. - [15:14] - read-write - - - NONE - 0 - No suffix - - - 8 - 2 - 8-bit suffix - - - - - PREFIX_LEN - Length of command prefix, in units of 8 bits. (i.e. 2 cycles for quad width, 4 for dual, 8 for single) - [12:12] - read-write - - - NONE - 0 - No prefix - - - 8 - 1 - 8-bit prefix - - - - - DATA_WIDTH - The width used for the data transfer - [9:8] - read-write - - - S - 0 - Single width - - - D - 1 - Dual width - - - Q - 2 - Quad width - - - - - DUMMY_WIDTH - The width used for the dummy phase, if any. - - If width is single, SD0/MOSI is held asserted low during the dummy phase, and SD1...SD3 are tristated. If width is dual/quad, all IOs are tristated during the dummy phase. - [7:6] - read-write - - - S - 0 - Single width - - - D - 1 - Dual width - - - Q - 2 - Quad width - - - - - SUFFIX_WIDTH - The width used for the post-address command suffix, if any - [5:4] - read-write - - - S - 0 - Single width - - - D - 1 - Dual width - - - Q - 2 - Quad width - - - - - ADDR_WIDTH - The transfer width used for the address. The address phase always transfers 24 bits in total. - [3:2] - read-write - - - S - 0 - Single width - - - D - 1 - Dual width - - - Q - 2 - Quad width - - - - - PREFIX_WIDTH - The transfer width used for the command prefix, if any - [1:0] - read-write - - - S - 0 - Single width - - - D - 1 - Dual width - - - Q - 2 - Quad width - - - - - - - M1_RCMD - 0x00000028 - Command constants used for reads from memory address window 1. - - The reset value of the M1_RCMD register is configured to support a basic 03h serial read transfer with no additional configuration. - 0x0000a003 - - - SUFFIX - The command suffix bits following the address, if Mx_RFMT_SUFFIX_LEN is nonzero. - [15:8] - read-write - - - PREFIX - The command prefix bits to prepend on each new transfer, if Mx_RFMT_PREFIX_LEN is nonzero. - [7:0] - read-write - - - - - M1_WFMT - 0x0000002c - Write transfer format configuration for memory address window 1. - - Configure the bus width of each transfer phase individually, and configure the length or presence of the command prefix, command suffix and dummy/turnaround transfer phases. Only 24-bit addresses are supported. - - The reset value of the M1_WFMT register is configured to support a basic 02h serial write transfer. However, writes to this window must first be enabled via the XIP_CTRL_WRITABLE_M1 bit, as XIP memory is read-only by default. - 0x00001000 - - - DTR - Enable double transfer rate (DTR) for write commands: address, suffix and write data phases are active on both edges of SCK. SDO data is launched centre-aligned on each SCK edge, and SDI data is captured on the SCK edge that follows its launch. - - DTR is implemented by halving the clock rate; SCK has a period of 2 x CLK_DIV throughout the transfer. The prefix and dummy phases are still single transfer rate. - - If the suffix is quad-width, it must be 0 or 8 bits in length, to ensure an even number of SCK edges. - [28:28] - read-write - - - DUMMY_LEN - Length of dummy phase between command suffix and data phase, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single) - [18:16] - read-write - - - NONE - 0 - No dummy phase - - - 4 - 1 - 4 dummy bits - - - 8 - 2 - 8 dummy bits - - - 12 - 3 - 12 dummy bits - - - 16 - 4 - 16 dummy bits - - - 20 - 5 - 20 dummy bits - - - 24 - 6 - 24 dummy bits - - - 28 - 7 - 28 dummy bits - - - - - SUFFIX_LEN - Length of post-address command suffix, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single) - - Only values of 0 and 8 bits are supported. - [15:14] - read-write - - - NONE - 0 - No suffix - - - 8 - 2 - 8-bit suffix - - - - - PREFIX_LEN - Length of command prefix, in units of 8 bits. (i.e. 2 cycles for quad width, 4 for dual, 8 for single) - [12:12] - read-write - - - NONE - 0 - No prefix - - - 8 - 1 - 8-bit prefix - - - - - DATA_WIDTH - The width used for the data transfer - [9:8] - read-write - - - S - 0 - Single width - - - D - 1 - Dual width - - - Q - 2 - Quad width - - - - - DUMMY_WIDTH - The width used for the dummy phase, if any. - - If width is single, SD0/MOSI is held asserted low during the dummy phase, and SD1...SD3 are tristated. If width is dual/quad, all IOs are tristated during the dummy phase. - [7:6] - read-write - - - S - 0 - Single width - - - D - 1 - Dual width - - - Q - 2 - Quad width - - - - - SUFFIX_WIDTH - The width used for the post-address command suffix, if any - [5:4] - read-write - - - S - 0 - Single width - - - D - 1 - Dual width - - - Q - 2 - Quad width - - - - - ADDR_WIDTH - The transfer width used for the address. The address phase always transfers 24 bits in total. - [3:2] - read-write - - - S - 0 - Single width - - - D - 1 - Dual width - - - Q - 2 - Quad width - - - - - PREFIX_WIDTH - The transfer width used for the command prefix, if any - [1:0] - read-write - - - S - 0 - Single width - - - D - 1 - Dual width - - - Q - 2 - Quad width - - - - - - - M1_WCMD - 0x00000030 - Command constants used for writes to memory address window 1. - - The reset value of the M1_WCMD register is configured to support a basic 02h serial write transfer with no additional configuration. - 0x0000a002 - - - SUFFIX - The command suffix bits following the address, if Mx_WFMT_SUFFIX_LEN is nonzero. - [15:8] - read-write - - - PREFIX - The command prefix bits to prepend on each new transfer, if Mx_WFMT_PREFIX_LEN is nonzero. - [7:0] - read-write - - - - - ATRANS0 - 0x00000034 - Configure address translation for XIP virtual addresses 0x000000 through 0x3fffff (a 4 MiB window starting at +0 MiB). - - Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code. - - At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required. - - Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation. - 0x04000000 - - - SIZE - Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). - - Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access. - [26:16] - read-write - - - BASE - Physical address base for this virtual address range, in units of 4 kiB (one flash sector). - - Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary. - [11:0] - read-write - - - - - ATRANS1 - 0x00000038 - Configure address translation for XIP virtual addresses 0x400000 through 0x7fffff (a 4 MiB window starting at +4 MiB). - - Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code. - - At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required. - - Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation. - 0x04000400 - - - SIZE - Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). - - Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access. - [26:16] - read-write - - - BASE - Physical address base for this virtual address range, in units of 4 kiB (one flash sector). - - Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary. - [11:0] - read-write - - - - - ATRANS2 - 0x0000003c - Configure address translation for XIP virtual addresses 0x800000 through 0xbfffff (a 4 MiB window starting at +8 MiB). - - Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code. - - At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required. - - Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation. - 0x04000800 - - - SIZE - Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). - - Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access. - [26:16] - read-write - - - BASE - Physical address base for this virtual address range, in units of 4 kiB (one flash sector). - - Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary. - [11:0] - read-write - - - - - ATRANS3 - 0x00000040 - Configure address translation for XIP virtual addresses 0xc00000 through 0xffffff (a 4 MiB window starting at +12 MiB). - - Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code. - - At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required. - - Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation. - 0x04000c00 - - - SIZE - Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). - - Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access. - [26:16] - read-write - - - BASE - Physical address base for this virtual address range, in units of 4 kiB (one flash sector). - - Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary. - [11:0] - read-write - - - - - ATRANS4 - 0x00000044 - Configure address translation for XIP virtual addresses 0x1000000 through 0x13fffff (a 4 MiB window starting at +16 MiB). - - Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code. - - At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required. - - Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation. - 0x04000000 - - - SIZE - Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). - - Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access. - [26:16] - read-write - - - BASE - Physical address base for this virtual address range, in units of 4 kiB (one flash sector). - - Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary. - [11:0] - read-write - - - - - ATRANS5 - 0x00000048 - Configure address translation for XIP virtual addresses 0x1400000 through 0x17fffff (a 4 MiB window starting at +20 MiB). - - Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code. - - At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required. - - Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation. - 0x04000400 - - - SIZE - Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). - - Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access. - [26:16] - read-write - - - BASE - Physical address base for this virtual address range, in units of 4 kiB (one flash sector). - - Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary. - [11:0] - read-write - - - - - ATRANS6 - 0x0000004c - Configure address translation for XIP virtual addresses 0x1800000 through 0x1bfffff (a 4 MiB window starting at +24 MiB). - - Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code. - - At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required. - - Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation. - 0x04000800 - - - SIZE - Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). - - Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access. - [26:16] - read-write - - - BASE - Physical address base for this virtual address range, in units of 4 kiB (one flash sector). - - Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary. - [11:0] - read-write - - - - - ATRANS7 - 0x00000050 - Configure address translation for XIP virtual addresses 0x1c00000 through 0x1ffffff (a 4 MiB window starting at +28 MiB). - - Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code. - - At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required. - - Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation. - 0x04000c00 - - - SIZE - Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). - - Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access. - [26:16] - read-write - - - BASE - Physical address base for this virtual address range, in units of 4 kiB (one flash sector). - - Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary. - [11:0] - read-write - - - - - - - XIP_CTRL - QSPI flash execute-in-place block - 0x400c8000 - - 0 - 32 - registers - - - - CTRL - 0x00000000 - Cache control register. Read-only from a Non-secure context. - 0x00000083 - - - WRITABLE_M1 - If 1, enable writes to XIP memory window 1 (addresses 0x11000000 through 0x11ffffff, and their uncached mirrors). If 0, this region is read-only. - - XIP memory is *read-only by default*. This bit must be set to enable writes if a RAM device is attached on QSPI chip select 1. - - The default read-only behaviour avoids two issues with writing to a read-only QSPI device (e.g. flash). First, a write will initially appear to succeed due to caching, but the data will eventually be lost when the written line is evicted, causing unpredictable behaviour. - - Second, when a written line is evicted, it will cause a write command to be issued to the flash, which can break the flash out of its continuous read mode. After this point, flash reads will return garbage. This is a security concern, as it allows Non-secure software to break Secure flash reads if it has permission to write to any flash address. - - Note the read-only behaviour is implemented by downgrading writes to reads, so writes will still cause allocation of an address, but have no other effect. - [11:11] - read-write - - - WRITABLE_M0 - If 1, enable writes to XIP memory window 0 (addresses 0x10000000 through 0x10ffffff, and their uncached mirrors). If 0, this region is read-only. - - XIP memory is *read-only by default*. This bit must be set to enable writes if a RAM device is attached on QSPI chip select 0. - - The default read-only behaviour avoids two issues with writing to a read-only QSPI device (e.g. flash). First, a write will initially appear to succeed due to caching, but the data will eventually be lost when the written line is evicted, causing unpredictable behaviour. - - Second, when a written line is evicted, it will cause a write command to be issued to the flash, which can break the flash out of its continuous read mode. After this point, flash reads will return garbage. This is a security concern, as it allows Non-secure software to break Secure flash reads if it has permission to write to any flash address. - - Note the read-only behaviour is implemented by downgrading writes to reads, so writes will still cause allocation of an address, but have no other effect. - [10:10] - read-write - - - SPLIT_WAYS - When 1, route all cached+Secure accesses to way 0 of the cache, and route all cached+Non-secure accesses to way 1 of the cache. - - This partitions the cache into two half-sized direct-mapped regions, such that Non-secure code can not observe cache line state changes caused by Secure execution. - - A full cache flush is required when changing the value of SPLIT_WAYS. The flush should be performed whilst SPLIT_WAYS is 0, so that both cache ways are accessible for invalidation. - [9:9] - read-write - - - MAINT_NONSEC - When 0, Non-secure accesses to the cache maintenance address window (addr[27] == 1, addr[26] == 0) will generate a bus error. When 1, Non-secure accesses can perform cache maintenance operations by writing to the cache maintenance address window. - - Cache maintenance operations may be used to corrupt Secure data by invalidating cache lines inappropriately, or map Secure content into a Non-secure region by pinning cache lines. Therefore this bit should generally be set to 0, unless Secure code is not using the cache. - - Care should also be taken to clear the cache data memory and tag memory before granting maintenance operations to Non-secure code. - [8:8] - read-write - - - NO_UNTRANSLATED_NONSEC - When 1, Non-secure accesses to the uncached, untranslated window (addr[27:26] == 3) will generate a bus error. - [7:7] - read-write - - - NO_UNTRANSLATED_SEC - When 1, Secure accesses to the uncached, untranslated window (addr[27:26] == 3) will generate a bus error. - [6:6] - read-write - - - NO_UNCACHED_NONSEC - When 1, Non-secure accesses to the uncached window (addr[27:26] == 1) will generate a bus error. This may reduce the number of SAU/MPU/PMP regions required to protect flash contents. - - Note this does not disable access to the uncached, untranslated window -- see NO_UNTRANSLATED_SEC. - [5:5] - read-write - - - NO_UNCACHED_SEC - When 1, Secure accesses to the uncached window (addr[27:26] == 1) will generate a bus error. This may reduce the number of SAU/MPU/PMP regions required to protect flash contents. - - Note this does not disable access to the uncached, untranslated window -- see NO_UNTRANSLATED_SEC. - [4:4] - read-write - - - POWER_DOWN - When 1, the cache memories are powered down. They retain state, but can not be accessed. This reduces static power dissipation. Writing 1 to this bit forces CTRL_EN_SECURE and CTRL_EN_NONSECURE to 0, i.e. the cache cannot be enabled when powered down. - [3:3] - read-write - - - EN_NONSECURE - When 1, enable the cache for Non-secure accesses. When enabled, Non-secure XIP accesses to the cached (addr[26] == 0) window will query the cache, and QSPI accesses are performed only if the requested data is not present. When disabled, Secure access ignore the cache contents, and always access the QSPI interface. - - Accesses to the uncached (addr[26] == 1) window will never query the cache, irrespective of this bit. - [1:1] - read-write - - - EN_SECURE - When 1, enable the cache for Secure accesses. When enabled, Secure XIP accesses to the cached (addr[26] == 0) window will query the cache, and QSPI accesses are performed only if the requested data is not present. When disabled, Secure access ignore the cache contents, and always access the QSPI interface. - - Accesses to the uncached (addr[26] == 1) window will never query the cache, irrespective of this bit. - - There is no cache-as-SRAM address window. Cache lines are allocated for SRAM-like use by individually pinning them, and keeping the cache enabled. - [0:0] - read-write - - - - - STAT - 0x00000008 - 0x00000002 - - - FIFO_FULL - When 1, indicates the XIP streaming FIFO is completely full. - The streaming FIFO is 2 entries deep, so the full and empty - flag allow its level to be ascertained. - [2:2] - read-only - - - FIFO_EMPTY - When 1, indicates the XIP streaming FIFO is completely empty. - [1:1] - read-only - - - - - CTR_HIT - 0x0000000c - Cache Hit counter - 0x00000000 - - - CTR_HIT - A 32 bit saturating counter that increments upon each cache hit, - i.e. when an XIP access is serviced directly from cached data. - Write any value to clear. - [31:0] - read-write - oneToClear - - - - - CTR_ACC - 0x00000010 - Cache Access counter - 0x00000000 - - - CTR_ACC - A 32 bit saturating counter that increments upon each XIP access, - whether the cache is hit or not. This includes noncacheable accesses. - Write any value to clear. - [31:0] - read-write - oneToClear - - - - - STREAM_ADDR - 0x00000014 - FIFO stream address - 0x00000000 - - - STREAM_ADDR - The address of the next word to be streamed from flash to the streaming FIFO. - Increments automatically after each flash access. - Write the initial access address here before starting a streaming read. - [31:2] - read-write - - - - - STREAM_CTR - 0x00000018 - FIFO stream control - 0x00000000 - - - STREAM_CTR - Write a nonzero value to start a streaming read. This will then - progress in the background, using flash idle cycles to transfer - a linear data block from flash to the streaming FIFO. - Decrements automatically (1 at a time) as the stream - progresses, and halts on reaching 0. - Write 0 to halt an in-progress stream, and discard any in-flight - read, so that a new stream can immediately be started (after - draining the FIFO and reinitialising STREAM_ADDR) - [21:0] - read-write - - - - - STREAM_FIFO - 0x0000001c - FIFO stream data - 0x00000000 - - - STREAM_FIFO - Streamed data is buffered here, for retrieval by the system DMA. - This FIFO can also be accessed via the XIP_AUX slave, to avoid exposing - the DMA to bus stalls caused by other XIP traffic. - [31:0] - read-only - modify - - - - - - - XIP_AUX - Auxiliary DMA access to XIP FIFOs, via fast AHB bus access - 0x50500000 - - 0 - 12 - registers - - - - STREAM - 0x00000000 - Read the XIP stream FIFO (fast bus access to XIP_CTRL_STREAM_FIFO) - 0x00000000 - - - STREAM - [31:0] - read-only - modify - - - - - QMI_DIRECT_TX - 0x00000004 - Write to the QMI direct-mode TX FIFO (fast bus access to QMI_DIRECT_TX) - 0x00000000 - - - NOPUSH - Inhibit the RX FIFO push that would correspond to this TX FIFO entry. - - Useful to avoid garbage appearing in the RX FIFO when pushing the command at the beginning of a SPI transfer. - [20:20] - write-only - - - OE - Output enable (active-high). For single width (SPI), this field is ignored, and SD0 is always set to output, with SD1 always set to input. - - For dual and quad width (DSPI/QSPI), this sets whether the relevant SDx pads are set to output whilst transferring this FIFO record. In this case the command/address should have OE set, and the data transfer should have OE set or clear depending on the direction of the transfer. - [19:19] - write-only - - - DWIDTH - Data width. If 0, hardware will transmit the 8 LSBs of the DIRECT_TX DATA field, and return an 8-bit value in the 8 LSBs of DIRECT_RX. If 1, the full 16-bit width is used. 8-bit and 16-bit transfers can be mixed freely. - [18:18] - write-only - - - IWIDTH - Configure whether this FIFO record is transferred with single/dual/quad interface width (0/1/2). Different widths can be mixed freely. - [17:16] - write-only - - - S - 0 - Single width - - - D - 1 - Dual width - - - Q - 2 - Quad width - - - - - DATA - Data pushed here will be clocked out falling edges of SCK (or before the very first rising edge of SCK, if this is the first pulse). For each byte clocked out, the interface will simultaneously sample one byte, on rising edges of SCK, and push this to the DIRECT_RX FIFO. - - For 16-bit data, the least-significant byte is transmitted first. - [15:0] - write-only - - - - - QMI_DIRECT_RX - 0x00000008 - Read from the QMI direct-mode RX FIFO (fast bus access to QMI_DIRECT_RX) - 0x00000000 - - - QMI_DIRECT_RX - With each byte clocked out on the serial interface, one byte will simultaneously be clocked in, and will appear in this FIFO. The serial interface will stall when this FIFO is full, to avoid dropping data. - - When 16-bit data is pushed into the TX FIFO, the corresponding RX FIFO push will also contain 16 bits of data. The least-significant byte is the first one received. - [15:0] - read-only - modify - - - - - - - SYSCFG - Register block for various chip control signals - 0x40008000 - - 0 - 24 - registers - - - - PROC_CONFIG - 0x00000000 - Configuration for processors - 0x00000000 - - - PROC1_HALTED - Indication that proc1 has halted - [1:1] - read-only - - - PROC0_HALTED - Indication that proc0 has halted - [0:0] - read-only - - - - - PROC_IN_SYNC_BYPASS - 0x00000004 - For each bit, if 1, bypass the input synchronizer between that GPIO - and the GPIO input register in the SIO. The input synchronizers should - generally be unbypassed, to avoid injecting metastabilities into processors. - If you're feeling brave, you can bypass to save two cycles of input - latency. This register applies to GPIO 0...31. - 0x00000000 - - - GPIO - [31:0] - read-write - - - - - PROC_IN_SYNC_BYPASS_HI - 0x00000008 - For each bit, if 1, bypass the input synchronizer between that GPIO - and the GPIO input register in the SIO. The input synchronizers should - generally be unbypassed, to avoid injecting metastabilities into processors. - If you're feeling brave, you can bypass to save two cycles of input - latency. This register applies to GPIO 32...47. USB GPIO 56..57 QSPI GPIO 58..63 - 0x00000000 - - - QSPI_SD - [31:28] - read-write - - - QSPI_CSN - [27:27] - read-write - - - QSPI_SCK - [26:26] - read-write - - - USB_DM - [25:25] - read-write - - - USB_DP - [24:24] - read-write - - - GPIO - [15:0] - read-write - - - - - DBGFORCE - 0x0000000c - Directly control the chip SWD debug port - 0x00000006 - - - ATTACH - Attach chip debug port to syscfg controls, and disconnect it from external SWD pads. - [3:3] - read-write - - - SWCLK - Directly drive SWCLK, if ATTACH is set - [2:2] - read-write - - - SWDI - Directly drive SWDIO input, if ATTACH is set - [1:1] - read-write - - - SWDO - Observe the value of SWDIO output. - [0:0] - read-only - - - - - MEMPOWERDOWN - 0x00000010 - Control PD pins to memories. - Set high to put memories to a low power state. In this state the memories will retain contents but not be accessible - Use with caution - 0x00000000 - - - BOOTRAM - [12:12] - read-write - - - ROM - [11:11] - read-write - - - USB - [10:10] - read-write - - - SRAM9 - [9:9] - read-write - - - SRAM8 - [8:8] - read-write - - - SRAM7 - [7:7] - read-write - - - SRAM6 - [6:6] - read-write - - - SRAM5 - [5:5] - read-write - - - SRAM4 - [4:4] - read-write - - - SRAM3 - [3:3] - read-write - - - SRAM2 - [2:2] - read-write - - - SRAM1 - [1:1] - read-write - - - SRAM0 - [0:0] - read-write - - - - - AUXCTRL - 0x00000014 - Auxiliary system control register - 0x00000000 - - - AUXCTRL - * Bits 7:2: Reserved - - * Bit 1: When clear, the LPOSC output is XORed into the TRNG ROSC output as an additional, uncorrelated entropy source. When set, this behaviour is disabled. - - * Bit 0: Force POWMAN clock to switch to LPOSC, by asserting its WDRESET input. This must be set before initiating a watchdog reset of the RSM from a stage that includes CLOCKS, if POWMAN is running from clk_ref at the point that the watchdog reset takes place. Otherwise, the short pulse generated on clk_ref by the reset of the CLOCKS block may affect POWMAN register state. - [7:0] - read-write - - - - - - - XOSC - Controls the crystal oscillator - 0x40048000 - - 0 - 20 - registers - - - - CTRL - 0x00000000 - Crystal Oscillator Control - 0x00000000 - - - ENABLE - On power-up this field is initialised to DISABLE and the chip runs from the ROSC. - If the chip has subsequently been programmed to run from the XOSC then setting this field to DISABLE may lock-up the chip. If this is a concern then run the clk_ref from the ROSC and enable the clk_sys RESUS feature. - The 12-bit code is intended to give some protection against accidental writes. An invalid setting will retain the previous value. The actual value being used can be read from STATUS_ENABLED - [23:12] - read-write - - - DISABLE - 3358 - - - ENABLE - 4011 - - - - - FREQ_RANGE - The 12-bit code is intended to give some protection against accidental writes. An invalid setting will retain the previous value. The actual value being used can be read from STATUS_FREQ_RANGE - [11:0] - read-write - - - 1_15MHZ - 2720 - - - 10_30MHZ - 2721 - - - 25_60MHZ - 2722 - - - 40_100MHZ - 2723 - - - - - - - STATUS - 0x00000004 - Crystal Oscillator Status - 0x00000000 - - - STABLE - Oscillator is running and stable - [31:31] - read-only - - - BADWRITE - An invalid value has been written to CTRL_ENABLE or CTRL_FREQ_RANGE or DORMANT - [24:24] - read-write - oneToClear - - - ENABLED - Oscillator is enabled but not necessarily running and stable, resets to 0 - [12:12] - read-only - - - FREQ_RANGE - The current frequency range setting - [1:0] - read-only - - - 1_15MHZ - 0 - - - 10_30MHZ - 1 - - - 25_60MHZ - 2 - - - 40_100MHZ - 3 - - - - - - - DORMANT - 0x00000008 - Crystal Oscillator pause control - 0x00000000 - - - DORMANT - This is used to save power by pausing the XOSC - On power-up this field is initialised to WAKE - An invalid write will also select WAKE - Warning: stop the PLLs before selecting dormant mode - Warning: setup the irq before selecting dormant mode - [31:0] - read-write - - - dormant - 1668246881 - - - WAKE - 2002873189 - - - - - - - STARTUP - 0x0000000c - Controls the startup delay - 0x00000000 - - - X4 - Multiplies the startup_delay by 4, just in case. The reset value is controlled by a mask-programmable tiecell and is provided in case we are booting from XOSC and the default startup delay is insufficient. The reset value is 0x0. - [20:20] - read-write - - - DELAY - in multiples of 256*xtal_period. The reset value of 0xc4 corresponds to approx 50 000 cycles. - [13:0] - read-write - - - - - COUNT - 0x00000010 - A down counter running at the xosc frequency which counts to zero and stops. - Can be used for short software pauses when setting up time sensitive hardware. - To start the counter, write a non-zero value. Reads will return 1 while the count is running and 0 when it has finished. - Minimum count value is 4. Count values <4 will be treated as count value =4. - Note that synchronisation to the register clock domain costs 2 register clock cycles and the counter cannot compensate for that. - 0x00000000 - - - COUNT - [15:0] - read-write - - - - - - - PLL_SYS - 0x40050000 - - 0 - 32 - registers - - - PLL_SYS_IRQ - 42 - - - - CS - 0x00000000 - Control and Status - GENERAL CONSTRAINTS: - Reference clock frequency min=5MHz, max=800MHz - Feedback divider min=16, max=320 - VCO frequency min=750MHz, max=1600MHz - 0x00000001 - - - LOCK - PLL is locked - [31:31] - read-only - - - LOCK_N - PLL is not locked - Ideally this is cleared when PLL lock is seen and this should never normally be set - [30:30] - read-write - oneToClear - - - BYPASS - Passes the reference clock to the output instead of the divided VCO. The VCO continues to run so the user can switch between the reference clock and the divided VCO but the output will glitch when doing so. - [8:8] - read-write - - - REFDIV - Divides the PLL input reference clock. - Behaviour is undefined for div=0. - PLL output will be unpredictable during refdiv changes, wait for lock=1 before using it. - [5:0] - read-write - - - - - PWR - 0x00000004 - Controls the PLL power modes. - 0x0000002d - - - VCOPD - PLL VCO powerdown - To save power set high when PLL output not required or bypass=1. - [5:5] - read-write - - - POSTDIVPD - PLL post divider powerdown - To save power set high when PLL output not required or bypass=1. - [3:3] - read-write - - - DSMPD - PLL DSM powerdown - Nothing is achieved by setting this low. - [2:2] - read-write - - - PD - PLL powerdown - To save power set high when PLL output not required. - [0:0] - read-write - - - - - FBDIV_INT - 0x00000008 - Feedback divisor - (note: this PLL does not support fractional division) - 0x00000000 - - - FBDIV_INT - see ctrl reg description for constraints - [11:0] - read-write - - - - - PRIM - 0x0000000c - Controls the PLL post dividers for the primary output - (note: this PLL does not have a secondary output) - the primary output is driven from VCO divided by postdiv1*postdiv2 - 0x00077000 - - - POSTDIV1 - divide by 1-7 - [18:16] - read-write - - - POSTDIV2 - divide by 1-7 - [14:12] - read-write - - - - - INTR - 0x00000010 - Raw Interrupts - 0x00000000 - - - LOCK_N_STICKY - [0:0] - read-write - oneToClear - - - - - INTE - 0x00000014 - Interrupt Enable - 0x00000000 - - - LOCK_N_STICKY - [0:0] - read-write - - - - - INTF - 0x00000018 - Interrupt Force - 0x00000000 - - - LOCK_N_STICKY - [0:0] - read-write - - - - - INTS - 0x0000001c - Interrupt status after masking & forcing - 0x00000000 - - - LOCK_N_STICKY - [0:0] - read-only - - - - - - - PLL_USB - 0x40058000 - - PLL_USB_IRQ - 43 - - - - ACCESSCTRL - Hardware access control registers - 0x40060000 - - 0 - 236 - registers - - - - LOCK - 0x00000000 - Once a LOCK bit is written to 1, ACCESSCTRL silently ignores writes from that master. LOCK is writable only by a Secure, Privileged processor or debugger. - - LOCK bits are only writable when their value is zero. Once set, they can never be cleared, except by a full reset of ACCESSCTRL - - Setting the LOCK bit does not affect whether an access raises a bus error. Unprivileged writes, or writes from the DMA, will continue to raise bus errors. All other accesses will continue not to. - 0x00000004 - - - DEBUG - [3:3] - read-write - - - DMA - [2:2] - read-only - - - CORE1 - [1:1] - read-write - - - CORE0 - [0:0] - read-write - - - - - FORCE_CORE_NS - 0x00000004 - Force core 1's bus accesses to always be Non-secure, no matter the core's internal state. - - Useful for schemes where one core is designated as the Non-secure core, since some peripherals may filter individual registers internally based on security state but not on master ID. - 0x00000000 - - - CORE1 - [1:1] - read-write - - - - - CFGRESET - 0x00000008 - Write 1 to reset all ACCESSCTRL configuration, except for the LOCK and FORCE_CORE_NS registers. - - This bit is used in the RP2350 bootrom to quickly restore ACCESSCTRL to a known state during the boot path. - - Note that, like all registers in ACCESSCTRL, this register is not writable when the writer's corresponding LOCK bit is set, therefore a master which has been locked out of ACCESSCTRL can not use the CFGRESET register to disturb its contents. - 0x00000000 - - - CFGRESET - [0:0] - write-only - - - - - GPIO_NSMASK0 - 0x0000000c - Control whether GPIO0...31 are accessible to Non-secure code. Writable only by a Secure, Privileged processor or debugger. - - 0 -> Secure access only - - 1 -> Secure + Non-secure access - 0x00000000 - - - GPIO_NSMASK0 - [31:0] - read-write - - - - - GPIO_NSMASK1 - 0x00000010 - Control whether GPIO32..47 are accessible to Non-secure code, and whether QSPI and USB bitbang are accessible through the Non-secure SIO. Writable only by a Secure, Privileged processor or debugger. - 0x00000000 - - - QSPI_SD - [31:28] - read-write - - - QSPI_CSN - [27:27] - read-write - - - QSPI_SCK - [26:26] - read-write - - - USB_DM - [25:25] - read-write - - - USB_DP - [24:24] - read-write - - - GPIO - [15:0] - read-write - - - - - ROM - 0x00000014 - Control whether debugger, DMA, core 0 and core 1 can access ROM, and at what security/privilege levels they can do so. - - Defaults to fully open access. - - This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. - 0x000000ff - - - DBG - If 1, ROM can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [7:7] - read-write - - - DMA - If 1, ROM can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [6:6] - read-write - - - CORE1 - If 1, ROM can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [5:5] - read-write - - - CORE0 - If 1, ROM can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [4:4] - read-write - - - SP - If 1, ROM can be accessed from a Secure, Privileged context. - [3:3] - read-write - - - SU - If 1, and SP is also set, ROM can be accessed from a Secure, Unprivileged context. - [2:2] - read-write - - - NSP - If 1, ROM can be accessed from a Non-secure, Privileged context. - [1:1] - read-write - - - NSU - If 1, and NSP is also set, ROM can be accessed from a Non-secure, Unprivileged context. - - This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. - [0:0] - read-write - - - - - XIP_MAIN - 0x00000018 - Control whether debugger, DMA, core 0 and core 1 can access XIP_MAIN, and at what security/privilege levels they can do so. - - Defaults to fully open access. - - This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. - 0x000000ff - - - DBG - If 1, XIP_MAIN can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [7:7] - read-write - - - DMA - If 1, XIP_MAIN can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [6:6] - read-write - - - CORE1 - If 1, XIP_MAIN can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [5:5] - read-write - - - CORE0 - If 1, XIP_MAIN can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [4:4] - read-write - - - SP - If 1, XIP_MAIN can be accessed from a Secure, Privileged context. - [3:3] - read-write - - - SU - If 1, and SP is also set, XIP_MAIN can be accessed from a Secure, Unprivileged context. - [2:2] - read-write - - - NSP - If 1, XIP_MAIN can be accessed from a Non-secure, Privileged context. - [1:1] - read-write - - - NSU - If 1, and NSP is also set, XIP_MAIN can be accessed from a Non-secure, Unprivileged context. - - This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. - [0:0] - read-write - - - - - SRAM0 - 0x0000001c - Control whether debugger, DMA, core 0 and core 1 can access SRAM0, and at what security/privilege levels they can do so. - - Defaults to fully open access. - - This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. - 0x000000ff - - - DBG - If 1, SRAM0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [7:7] - read-write - - - DMA - If 1, SRAM0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [6:6] - read-write - - - CORE1 - If 1, SRAM0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [5:5] - read-write - - - CORE0 - If 1, SRAM0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [4:4] - read-write - - - SP - If 1, SRAM0 can be accessed from a Secure, Privileged context. - [3:3] - read-write - - - SU - If 1, and SP is also set, SRAM0 can be accessed from a Secure, Unprivileged context. - [2:2] - read-write - - - NSP - If 1, SRAM0 can be accessed from a Non-secure, Privileged context. - [1:1] - read-write - - - NSU - If 1, and NSP is also set, SRAM0 can be accessed from a Non-secure, Unprivileged context. - - This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. - [0:0] - read-write - - - - - SRAM1 - 0x00000020 - Control whether debugger, DMA, core 0 and core 1 can access SRAM1, and at what security/privilege levels they can do so. - - Defaults to fully open access. - - This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. - 0x000000ff - - - DBG - If 1, SRAM1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [7:7] - read-write - - - DMA - If 1, SRAM1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [6:6] - read-write - - - CORE1 - If 1, SRAM1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [5:5] - read-write - - - CORE0 - If 1, SRAM1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [4:4] - read-write - - - SP - If 1, SRAM1 can be accessed from a Secure, Privileged context. - [3:3] - read-write - - - SU - If 1, and SP is also set, SRAM1 can be accessed from a Secure, Unprivileged context. - [2:2] - read-write - - - NSP - If 1, SRAM1 can be accessed from a Non-secure, Privileged context. - [1:1] - read-write - - - NSU - If 1, and NSP is also set, SRAM1 can be accessed from a Non-secure, Unprivileged context. - - This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. - [0:0] - read-write - - - - - SRAM2 - 0x00000024 - Control whether debugger, DMA, core 0 and core 1 can access SRAM2, and at what security/privilege levels they can do so. - - Defaults to fully open access. - - This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. - 0x000000ff - - - DBG - If 1, SRAM2 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [7:7] - read-write - - - DMA - If 1, SRAM2 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [6:6] - read-write - - - CORE1 - If 1, SRAM2 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [5:5] - read-write - - - CORE0 - If 1, SRAM2 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [4:4] - read-write - - - SP - If 1, SRAM2 can be accessed from a Secure, Privileged context. - [3:3] - read-write - - - SU - If 1, and SP is also set, SRAM2 can be accessed from a Secure, Unprivileged context. - [2:2] - read-write - - - NSP - If 1, SRAM2 can be accessed from a Non-secure, Privileged context. - [1:1] - read-write - - - NSU - If 1, and NSP is also set, SRAM2 can be accessed from a Non-secure, Unprivileged context. - - This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. - [0:0] - read-write - - - - - SRAM3 - 0x00000028 - Control whether debugger, DMA, core 0 and core 1 can access SRAM3, and at what security/privilege levels they can do so. - - Defaults to fully open access. - - This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. - 0x000000ff - - - DBG - If 1, SRAM3 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [7:7] - read-write - - - DMA - If 1, SRAM3 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [6:6] - read-write - - - CORE1 - If 1, SRAM3 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [5:5] - read-write - - - CORE0 - If 1, SRAM3 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [4:4] - read-write - - - SP - If 1, SRAM3 can be accessed from a Secure, Privileged context. - [3:3] - read-write - - - SU - If 1, and SP is also set, SRAM3 can be accessed from a Secure, Unprivileged context. - [2:2] - read-write - - - NSP - If 1, SRAM3 can be accessed from a Non-secure, Privileged context. - [1:1] - read-write - - - NSU - If 1, and NSP is also set, SRAM3 can be accessed from a Non-secure, Unprivileged context. - - This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. - [0:0] - read-write - - - - - SRAM4 - 0x0000002c - Control whether debugger, DMA, core 0 and core 1 can access SRAM4, and at what security/privilege levels they can do so. - - Defaults to fully open access. - - This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. - 0x000000ff - - - DBG - If 1, SRAM4 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [7:7] - read-write - - - DMA - If 1, SRAM4 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [6:6] - read-write - - - CORE1 - If 1, SRAM4 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [5:5] - read-write - - - CORE0 - If 1, SRAM4 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [4:4] - read-write - - - SP - If 1, SRAM4 can be accessed from a Secure, Privileged context. - [3:3] - read-write - - - SU - If 1, and SP is also set, SRAM4 can be accessed from a Secure, Unprivileged context. - [2:2] - read-write - - - NSP - If 1, SRAM4 can be accessed from a Non-secure, Privileged context. - [1:1] - read-write - - - NSU - If 1, and NSP is also set, SRAM4 can be accessed from a Non-secure, Unprivileged context. - - This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. - [0:0] - read-write - - - - - SRAM5 - 0x00000030 - Control whether debugger, DMA, core 0 and core 1 can access SRAM5, and at what security/privilege levels they can do so. - - Defaults to fully open access. - - This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. - 0x000000ff - - - DBG - If 1, SRAM5 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [7:7] - read-write - - - DMA - If 1, SRAM5 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [6:6] - read-write - - - CORE1 - If 1, SRAM5 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [5:5] - read-write - - - CORE0 - If 1, SRAM5 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [4:4] - read-write - - - SP - If 1, SRAM5 can be accessed from a Secure, Privileged context. - [3:3] - read-write - - - SU - If 1, and SP is also set, SRAM5 can be accessed from a Secure, Unprivileged context. - [2:2] - read-write - - - NSP - If 1, SRAM5 can be accessed from a Non-secure, Privileged context. - [1:1] - read-write - - - NSU - If 1, and NSP is also set, SRAM5 can be accessed from a Non-secure, Unprivileged context. - - This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. - [0:0] - read-write - - - - - SRAM6 - 0x00000034 - Control whether debugger, DMA, core 0 and core 1 can access SRAM6, and at what security/privilege levels they can do so. - - Defaults to fully open access. - - This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. - 0x000000ff - - - DBG - If 1, SRAM6 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [7:7] - read-write - - - DMA - If 1, SRAM6 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [6:6] - read-write - - - CORE1 - If 1, SRAM6 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [5:5] - read-write - - - CORE0 - If 1, SRAM6 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [4:4] - read-write - - - SP - If 1, SRAM6 can be accessed from a Secure, Privileged context. - [3:3] - read-write - - - SU - If 1, and SP is also set, SRAM6 can be accessed from a Secure, Unprivileged context. - [2:2] - read-write - - - NSP - If 1, SRAM6 can be accessed from a Non-secure, Privileged context. - [1:1] - read-write - - - NSU - If 1, and NSP is also set, SRAM6 can be accessed from a Non-secure, Unprivileged context. - - This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. - [0:0] - read-write - - - - - SRAM7 - 0x00000038 - Control whether debugger, DMA, core 0 and core 1 can access SRAM7, and at what security/privilege levels they can do so. - - Defaults to fully open access. - - This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. - 0x000000ff - - - DBG - If 1, SRAM7 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [7:7] - read-write - - - DMA - If 1, SRAM7 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [6:6] - read-write - - - CORE1 - If 1, SRAM7 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [5:5] - read-write - - - CORE0 - If 1, SRAM7 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [4:4] - read-write - - - SP - If 1, SRAM7 can be accessed from a Secure, Privileged context. - [3:3] - read-write - - - SU - If 1, and SP is also set, SRAM7 can be accessed from a Secure, Unprivileged context. - [2:2] - read-write - - - NSP - If 1, SRAM7 can be accessed from a Non-secure, Privileged context. - [1:1] - read-write - - - NSU - If 1, and NSP is also set, SRAM7 can be accessed from a Non-secure, Unprivileged context. - - This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. - [0:0] - read-write - - - - - SRAM8 - 0x0000003c - Control whether debugger, DMA, core 0 and core 1 can access SRAM8, and at what security/privilege levels they can do so. - - Defaults to fully open access. - - This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. - 0x000000ff - - - DBG - If 1, SRAM8 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [7:7] - read-write - - - DMA - If 1, SRAM8 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [6:6] - read-write - - - CORE1 - If 1, SRAM8 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [5:5] - read-write - - - CORE0 - If 1, SRAM8 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [4:4] - read-write - - - SP - If 1, SRAM8 can be accessed from a Secure, Privileged context. - [3:3] - read-write - - - SU - If 1, and SP is also set, SRAM8 can be accessed from a Secure, Unprivileged context. - [2:2] - read-write - - - NSP - If 1, SRAM8 can be accessed from a Non-secure, Privileged context. - [1:1] - read-write - - - NSU - If 1, and NSP is also set, SRAM8 can be accessed from a Non-secure, Unprivileged context. - - This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. - [0:0] - read-write - - - - - SRAM9 - 0x00000040 - Control whether debugger, DMA, core 0 and core 1 can access SRAM9, and at what security/privilege levels they can do so. - - Defaults to fully open access. - - This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. - 0x000000ff - - - DBG - If 1, SRAM9 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [7:7] - read-write - - - DMA - If 1, SRAM9 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [6:6] - read-write - - - CORE1 - If 1, SRAM9 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [5:5] - read-write - - - CORE0 - If 1, SRAM9 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [4:4] - read-write - - - SP - If 1, SRAM9 can be accessed from a Secure, Privileged context. - [3:3] - read-write - - - SU - If 1, and SP is also set, SRAM9 can be accessed from a Secure, Unprivileged context. - [2:2] - read-write - - - NSP - If 1, SRAM9 can be accessed from a Non-secure, Privileged context. - [1:1] - read-write - - - NSU - If 1, and NSP is also set, SRAM9 can be accessed from a Non-secure, Unprivileged context. - - This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. - [0:0] - read-write - - - - - DMA - 0x00000044 - Control whether debugger, DMA, core 0 and core 1 can access DMA, and at what security/privilege levels they can do so. - - Defaults to Secure access from any master. - - This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. - 0x000000fc - - - DBG - If 1, DMA can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [7:7] - read-write - - - DMA - If 1, DMA can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [6:6] - read-write - - - CORE1 - If 1, DMA can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [5:5] - read-write - - - CORE0 - If 1, DMA can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [4:4] - read-write - - - SP - If 1, DMA can be accessed from a Secure, Privileged context. - [3:3] - read-write - - - SU - If 1, and SP is also set, DMA can be accessed from a Secure, Unprivileged context. - [2:2] - read-write - - - NSP - If 1, DMA can be accessed from a Non-secure, Privileged context. - [1:1] - read-write - - - NSU - If 1, and NSP is also set, DMA can be accessed from a Non-secure, Unprivileged context. - - This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. - [0:0] - read-write - - - - - USBCTRL - 0x00000048 - Control whether debugger, DMA, core 0 and core 1 can access USBCTRL, and at what security/privilege levels they can do so. - - Defaults to Secure access from any master. - - This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. - 0x000000fc - - - DBG - If 1, USBCTRL can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [7:7] - read-write - - - DMA - If 1, USBCTRL can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [6:6] - read-write - - - CORE1 - If 1, USBCTRL can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [5:5] - read-write - - - CORE0 - If 1, USBCTRL can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [4:4] - read-write - - - SP - If 1, USBCTRL can be accessed from a Secure, Privileged context. - [3:3] - read-write - - - SU - If 1, and SP is also set, USBCTRL can be accessed from a Secure, Unprivileged context. - [2:2] - read-write - - - NSP - If 1, USBCTRL can be accessed from a Non-secure, Privileged context. - [1:1] - read-write - - - NSU - If 1, and NSP is also set, USBCTRL can be accessed from a Non-secure, Unprivileged context. - - This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. - [0:0] - read-write - - - - - PIO0 - 0x0000004c - Control whether debugger, DMA, core 0 and core 1 can access PIO0, and at what security/privilege levels they can do so. - - Defaults to Secure access from any master. - - This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. - 0x000000fc - - - DBG - If 1, PIO0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [7:7] - read-write - - - DMA - If 1, PIO0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [6:6] - read-write - - - CORE1 - If 1, PIO0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [5:5] - read-write - - - CORE0 - If 1, PIO0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [4:4] - read-write - - - SP - If 1, PIO0 can be accessed from a Secure, Privileged context. - [3:3] - read-write - - - SU - If 1, and SP is also set, PIO0 can be accessed from a Secure, Unprivileged context. - [2:2] - read-write - - - NSP - If 1, PIO0 can be accessed from a Non-secure, Privileged context. - [1:1] - read-write - - - NSU - If 1, and NSP is also set, PIO0 can be accessed from a Non-secure, Unprivileged context. - - This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. - [0:0] - read-write - - - - - PIO1 - 0x00000050 - Control whether debugger, DMA, core 0 and core 1 can access PIO1, and at what security/privilege levels they can do so. - - Defaults to Secure access from any master. - - This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. - 0x000000fc - - - DBG - If 1, PIO1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [7:7] - read-write - - - DMA - If 1, PIO1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [6:6] - read-write - - - CORE1 - If 1, PIO1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [5:5] - read-write - - - CORE0 - If 1, PIO1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [4:4] - read-write - - - SP - If 1, PIO1 can be accessed from a Secure, Privileged context. - [3:3] - read-write - - - SU - If 1, and SP is also set, PIO1 can be accessed from a Secure, Unprivileged context. - [2:2] - read-write - - - NSP - If 1, PIO1 can be accessed from a Non-secure, Privileged context. - [1:1] - read-write - - - NSU - If 1, and NSP is also set, PIO1 can be accessed from a Non-secure, Unprivileged context. - - This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. - [0:0] - read-write - - - - - PIO2 - 0x00000054 - Control whether debugger, DMA, core 0 and core 1 can access PIO2, and at what security/privilege levels they can do so. - - Defaults to Secure access from any master. - - This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. - 0x000000fc - - - DBG - If 1, PIO2 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [7:7] - read-write - - - DMA - If 1, PIO2 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [6:6] - read-write - - - CORE1 - If 1, PIO2 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [5:5] - read-write - - - CORE0 - If 1, PIO2 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [4:4] - read-write - - - SP - If 1, PIO2 can be accessed from a Secure, Privileged context. - [3:3] - read-write - - - SU - If 1, and SP is also set, PIO2 can be accessed from a Secure, Unprivileged context. - [2:2] - read-write - - - NSP - If 1, PIO2 can be accessed from a Non-secure, Privileged context. - [1:1] - read-write - - - NSU - If 1, and NSP is also set, PIO2 can be accessed from a Non-secure, Unprivileged context. - - This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. - [0:0] - read-write - - - - - CORESIGHT_TRACE - 0x00000058 - Control whether debugger, DMA, core 0 and core 1 can access CORESIGHT_TRACE, and at what security/privilege levels they can do so. - - Defaults to Secure, Privileged processor or debug access only. - - This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. - 0x000000b8 - - - DBG - If 1, CORESIGHT_TRACE can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [7:7] - read-write - - - DMA - If 1, CORESIGHT_TRACE can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [6:6] - read-write - - - CORE1 - If 1, CORESIGHT_TRACE can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [5:5] - read-write - - - CORE0 - If 1, CORESIGHT_TRACE can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [4:4] - read-write - - - SP - If 1, CORESIGHT_TRACE can be accessed from a Secure, Privileged context. - [3:3] - read-write - - - SU - If 1, and SP is also set, CORESIGHT_TRACE can be accessed from a Secure, Unprivileged context. - [2:2] - read-write - - - NSP - If 1, CORESIGHT_TRACE can be accessed from a Non-secure, Privileged context. - [1:1] - read-write - - - NSU - If 1, and NSP is also set, CORESIGHT_TRACE can be accessed from a Non-secure, Unprivileged context. - - This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. - [0:0] - read-write - - - - - CORESIGHT_PERIPH - 0x0000005c - Control whether debugger, DMA, core 0 and core 1 can access CORESIGHT_PERIPH, and at what security/privilege levels they can do so. - - Defaults to Secure, Privileged processor or debug access only. - - This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. - 0x000000b8 - - - DBG - If 1, CORESIGHT_PERIPH can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [7:7] - read-write - - - DMA - If 1, CORESIGHT_PERIPH can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [6:6] - read-write - - - CORE1 - If 1, CORESIGHT_PERIPH can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [5:5] - read-write - - - CORE0 - If 1, CORESIGHT_PERIPH can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [4:4] - read-write - - - SP - If 1, CORESIGHT_PERIPH can be accessed from a Secure, Privileged context. - [3:3] - read-write - - - SU - If 1, and SP is also set, CORESIGHT_PERIPH can be accessed from a Secure, Unprivileged context. - [2:2] - read-write - - - NSP - If 1, CORESIGHT_PERIPH can be accessed from a Non-secure, Privileged context. - [1:1] - read-write - - - NSU - If 1, and NSP is also set, CORESIGHT_PERIPH can be accessed from a Non-secure, Unprivileged context. - - This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. - [0:0] - read-write - - - - - SYSINFO - 0x00000060 - Control whether debugger, DMA, core 0 and core 1 can access SYSINFO, and at what security/privilege levels they can do so. - - Defaults to fully open access. - - This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. - 0x000000ff - - - DBG - If 1, SYSINFO can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [7:7] - read-write - - - DMA - If 1, SYSINFO can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [6:6] - read-write - - - CORE1 - If 1, SYSINFO can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [5:5] - read-write - - - CORE0 - If 1, SYSINFO can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [4:4] - read-write - - - SP - If 1, SYSINFO can be accessed from a Secure, Privileged context. - [3:3] - read-write - - - SU - If 1, and SP is also set, SYSINFO can be accessed from a Secure, Unprivileged context. - [2:2] - read-write - - - NSP - If 1, SYSINFO can be accessed from a Non-secure, Privileged context. - [1:1] - read-write - - - NSU - If 1, and NSP is also set, SYSINFO can be accessed from a Non-secure, Unprivileged context. - - This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. - [0:0] - read-write - - - - - RESETS - 0x00000064 - Control whether debugger, DMA, core 0 and core 1 can access RESETS, and at what security/privilege levels they can do so. - - Defaults to Secure access from any master. - - This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. - 0x000000fc - - - DBG - If 1, RESETS can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [7:7] - read-write - - - DMA - If 1, RESETS can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [6:6] - read-write - - - CORE1 - If 1, RESETS can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [5:5] - read-write - - - CORE0 - If 1, RESETS can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [4:4] - read-write - - - SP - If 1, RESETS can be accessed from a Secure, Privileged context. - [3:3] - read-write - - - SU - If 1, and SP is also set, RESETS can be accessed from a Secure, Unprivileged context. - [2:2] - read-write - - - NSP - If 1, RESETS can be accessed from a Non-secure, Privileged context. - [1:1] - read-write - - - NSU - If 1, and NSP is also set, RESETS can be accessed from a Non-secure, Unprivileged context. - - This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. - [0:0] - read-write - - - - - IO_BANK0 - 0x00000068 - Control whether debugger, DMA, core 0 and core 1 can access IO_BANK0, and at what security/privilege levels they can do so. - - Defaults to Secure access from any master. - - This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. - 0x000000fc - - - DBG - If 1, IO_BANK0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [7:7] - read-write - - - DMA - If 1, IO_BANK0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [6:6] - read-write - - - CORE1 - If 1, IO_BANK0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [5:5] - read-write - - - CORE0 - If 1, IO_BANK0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [4:4] - read-write - - - SP - If 1, IO_BANK0 can be accessed from a Secure, Privileged context. - [3:3] - read-write - - - SU - If 1, and SP is also set, IO_BANK0 can be accessed from a Secure, Unprivileged context. - [2:2] - read-write - - - NSP - If 1, IO_BANK0 can be accessed from a Non-secure, Privileged context. - [1:1] - read-write - - - NSU - If 1, and NSP is also set, IO_BANK0 can be accessed from a Non-secure, Unprivileged context. - - This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. - [0:0] - read-write - - - - - IO_BANK1 - 0x0000006c - Control whether debugger, DMA, core 0 and core 1 can access IO_BANK1, and at what security/privilege levels they can do so. - - Defaults to Secure access from any master. - - This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. - 0x000000fc - - - DBG - If 1, IO_BANK1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [7:7] - read-write - - - DMA - If 1, IO_BANK1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [6:6] - read-write - - - CORE1 - If 1, IO_BANK1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [5:5] - read-write - - - CORE0 - If 1, IO_BANK1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [4:4] - read-write - - - SP - If 1, IO_BANK1 can be accessed from a Secure, Privileged context. - [3:3] - read-write - - - SU - If 1, and SP is also set, IO_BANK1 can be accessed from a Secure, Unprivileged context. - [2:2] - read-write - - - NSP - If 1, IO_BANK1 can be accessed from a Non-secure, Privileged context. - [1:1] - read-write - - - NSU - If 1, and NSP is also set, IO_BANK1 can be accessed from a Non-secure, Unprivileged context. - - This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. - [0:0] - read-write - - - - - PADS_BANK0 - 0x00000070 - Control whether debugger, DMA, core 0 and core 1 can access PADS_BANK0, and at what security/privilege levels they can do so. - - Defaults to Secure access from any master. - - This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. - 0x000000fc - - - DBG - If 1, PADS_BANK0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [7:7] - read-write - - - DMA - If 1, PADS_BANK0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [6:6] - read-write - - - CORE1 - If 1, PADS_BANK0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [5:5] - read-write - - - CORE0 - If 1, PADS_BANK0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [4:4] - read-write - - - SP - If 1, PADS_BANK0 can be accessed from a Secure, Privileged context. - [3:3] - read-write - - - SU - If 1, and SP is also set, PADS_BANK0 can be accessed from a Secure, Unprivileged context. - [2:2] - read-write - - - NSP - If 1, PADS_BANK0 can be accessed from a Non-secure, Privileged context. - [1:1] - read-write - - - NSU - If 1, and NSP is also set, PADS_BANK0 can be accessed from a Non-secure, Unprivileged context. - - This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. - [0:0] - read-write - - - - - PADS_QSPI - 0x00000074 - Control whether debugger, DMA, core 0 and core 1 can access PADS_QSPI, and at what security/privilege levels they can do so. - - Defaults to Secure access from any master. - - This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. - 0x000000fc - - - DBG - If 1, PADS_QSPI can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [7:7] - read-write - - - DMA - If 1, PADS_QSPI can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [6:6] - read-write - - - CORE1 - If 1, PADS_QSPI can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [5:5] - read-write - - - CORE0 - If 1, PADS_QSPI can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [4:4] - read-write - - - SP - If 1, PADS_QSPI can be accessed from a Secure, Privileged context. - [3:3] - read-write - - - SU - If 1, and SP is also set, PADS_QSPI can be accessed from a Secure, Unprivileged context. - [2:2] - read-write - - - NSP - If 1, PADS_QSPI can be accessed from a Non-secure, Privileged context. - [1:1] - read-write - - - NSU - If 1, and NSP is also set, PADS_QSPI can be accessed from a Non-secure, Unprivileged context. - - This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. - [0:0] - read-write - - - - - BUSCTRL - 0x00000078 - Control whether debugger, DMA, core 0 and core 1 can access BUSCTRL, and at what security/privilege levels they can do so. - - Defaults to Secure access from any master. - - This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. - 0x000000fc - - - DBG - If 1, BUSCTRL can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [7:7] - read-write - - - DMA - If 1, BUSCTRL can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [6:6] - read-write - - - CORE1 - If 1, BUSCTRL can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [5:5] - read-write - - - CORE0 - If 1, BUSCTRL can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [4:4] - read-write - - - SP - If 1, BUSCTRL can be accessed from a Secure, Privileged context. - [3:3] - read-write - - - SU - If 1, and SP is also set, BUSCTRL can be accessed from a Secure, Unprivileged context. - [2:2] - read-write - - - NSP - If 1, BUSCTRL can be accessed from a Non-secure, Privileged context. - [1:1] - read-write - - - NSU - If 1, and NSP is also set, BUSCTRL can be accessed from a Non-secure, Unprivileged context. - - This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. - [0:0] - read-write - - - - - ADC0 - 0x0000007c - Control whether debugger, DMA, core 0 and core 1 can access ADC0, and at what security/privilege levels they can do so. - - Defaults to Secure access from any master. - - This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. - 0x000000fc - - - DBG - If 1, ADC0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [7:7] - read-write - - - DMA - If 1, ADC0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [6:6] - read-write - - - CORE1 - If 1, ADC0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [5:5] - read-write - - - CORE0 - If 1, ADC0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [4:4] - read-write - - - SP - If 1, ADC0 can be accessed from a Secure, Privileged context. - [3:3] - read-write - - - SU - If 1, and SP is also set, ADC0 can be accessed from a Secure, Unprivileged context. - [2:2] - read-write - - - NSP - If 1, ADC0 can be accessed from a Non-secure, Privileged context. - [1:1] - read-write - - - NSU - If 1, and NSP is also set, ADC0 can be accessed from a Non-secure, Unprivileged context. - - This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. - [0:0] - read-write - - - - - HSTX - 0x00000080 - Control whether debugger, DMA, core 0 and core 1 can access HSTX, and at what security/privilege levels they can do so. - - Defaults to Secure access from any master. - - This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. - 0x000000fc - - - DBG - If 1, HSTX can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [7:7] - read-write - - - DMA - If 1, HSTX can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [6:6] - read-write - - - CORE1 - If 1, HSTX can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [5:5] - read-write - - - CORE0 - If 1, HSTX can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [4:4] - read-write - - - SP - If 1, HSTX can be accessed from a Secure, Privileged context. - [3:3] - read-write - - - SU - If 1, and SP is also set, HSTX can be accessed from a Secure, Unprivileged context. - [2:2] - read-write - - - NSP - If 1, HSTX can be accessed from a Non-secure, Privileged context. - [1:1] - read-write - - - NSU - If 1, and NSP is also set, HSTX can be accessed from a Non-secure, Unprivileged context. - - This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. - [0:0] - read-write - - - - - I2C0 - 0x00000084 - Control whether debugger, DMA, core 0 and core 1 can access I2C0, and at what security/privilege levels they can do so. - - Defaults to Secure access from any master. - - This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. - 0x000000fc - - - DBG - If 1, I2C0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [7:7] - read-write - - - DMA - If 1, I2C0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [6:6] - read-write - - - CORE1 - If 1, I2C0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [5:5] - read-write - - - CORE0 - If 1, I2C0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [4:4] - read-write - - - SP - If 1, I2C0 can be accessed from a Secure, Privileged context. - [3:3] - read-write - - - SU - If 1, and SP is also set, I2C0 can be accessed from a Secure, Unprivileged context. - [2:2] - read-write - - - NSP - If 1, I2C0 can be accessed from a Non-secure, Privileged context. - [1:1] - read-write - - - NSU - If 1, and NSP is also set, I2C0 can be accessed from a Non-secure, Unprivileged context. - - This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. - [0:0] - read-write - - - - - I2C1 - 0x00000088 - Control whether debugger, DMA, core 0 and core 1 can access I2C1, and at what security/privilege levels they can do so. - - Defaults to Secure access from any master. - - This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. - 0x000000fc - - - DBG - If 1, I2C1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [7:7] - read-write - - - DMA - If 1, I2C1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [6:6] - read-write - - - CORE1 - If 1, I2C1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [5:5] - read-write - - - CORE0 - If 1, I2C1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [4:4] - read-write - - - SP - If 1, I2C1 can be accessed from a Secure, Privileged context. - [3:3] - read-write - - - SU - If 1, and SP is also set, I2C1 can be accessed from a Secure, Unprivileged context. - [2:2] - read-write - - - NSP - If 1, I2C1 can be accessed from a Non-secure, Privileged context. - [1:1] - read-write - - - NSU - If 1, and NSP is also set, I2C1 can be accessed from a Non-secure, Unprivileged context. - - This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. - [0:0] - read-write - - - - - PWM - 0x0000008c - Control whether debugger, DMA, core 0 and core 1 can access PWM, and at what security/privilege levels they can do so. - - Defaults to Secure access from any master. - - This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. - 0x000000fc - - - DBG - If 1, PWM can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [7:7] - read-write - - - DMA - If 1, PWM can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [6:6] - read-write - - - CORE1 - If 1, PWM can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [5:5] - read-write - - - CORE0 - If 1, PWM can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [4:4] - read-write - - - SP - If 1, PWM can be accessed from a Secure, Privileged context. - [3:3] - read-write - - - SU - If 1, and SP is also set, PWM can be accessed from a Secure, Unprivileged context. - [2:2] - read-write - - - NSP - If 1, PWM can be accessed from a Non-secure, Privileged context. - [1:1] - read-write - - - NSU - If 1, and NSP is also set, PWM can be accessed from a Non-secure, Unprivileged context. - - This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. - [0:0] - read-write - - - - - SPI0 - 0x00000090 - Control whether debugger, DMA, core 0 and core 1 can access SPI0, and at what security/privilege levels they can do so. - - Defaults to Secure access from any master. - - This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. - 0x000000fc - - - DBG - If 1, SPI0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [7:7] - read-write - - - DMA - If 1, SPI0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [6:6] - read-write - - - CORE1 - If 1, SPI0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [5:5] - read-write - - - CORE0 - If 1, SPI0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [4:4] - read-write - - - SP - If 1, SPI0 can be accessed from a Secure, Privileged context. - [3:3] - read-write - - - SU - If 1, and SP is also set, SPI0 can be accessed from a Secure, Unprivileged context. - [2:2] - read-write - - - NSP - If 1, SPI0 can be accessed from a Non-secure, Privileged context. - [1:1] - read-write - - - NSU - If 1, and NSP is also set, SPI0 can be accessed from a Non-secure, Unprivileged context. - - This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. - [0:0] - read-write - - - - - SPI1 - 0x00000094 - Control whether debugger, DMA, core 0 and core 1 can access SPI1, and at what security/privilege levels they can do so. - - Defaults to Secure access from any master. - - This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. - 0x000000fc - - - DBG - If 1, SPI1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [7:7] - read-write - - - DMA - If 1, SPI1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [6:6] - read-write - - - CORE1 - If 1, SPI1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [5:5] - read-write - - - CORE0 - If 1, SPI1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [4:4] - read-write - - - SP - If 1, SPI1 can be accessed from a Secure, Privileged context. - [3:3] - read-write - - - SU - If 1, and SP is also set, SPI1 can be accessed from a Secure, Unprivileged context. - [2:2] - read-write - - - NSP - If 1, SPI1 can be accessed from a Non-secure, Privileged context. - [1:1] - read-write - - - NSU - If 1, and NSP is also set, SPI1 can be accessed from a Non-secure, Unprivileged context. - - This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. - [0:0] - read-write - - - - - TIMER0 - 0x00000098 - Control whether debugger, DMA, core 0 and core 1 can access TIMER0, and at what security/privilege levels they can do so. - - Defaults to Secure access from any master. - - This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. - 0x000000fc - - - DBG - If 1, TIMER0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [7:7] - read-write - - - DMA - If 1, TIMER0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [6:6] - read-write - - - CORE1 - If 1, TIMER0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [5:5] - read-write - - - CORE0 - If 1, TIMER0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [4:4] - read-write - - - SP - If 1, TIMER0 can be accessed from a Secure, Privileged context. - [3:3] - read-write - - - SU - If 1, and SP is also set, TIMER0 can be accessed from a Secure, Unprivileged context. - [2:2] - read-write - - - NSP - If 1, TIMER0 can be accessed from a Non-secure, Privileged context. - [1:1] - read-write - - - NSU - If 1, and NSP is also set, TIMER0 can be accessed from a Non-secure, Unprivileged context. - - This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. - [0:0] - read-write - - - - - TIMER1 - 0x0000009c - Control whether debugger, DMA, core 0 and core 1 can access TIMER1, and at what security/privilege levels they can do so. - - Defaults to Secure access from any master. - - This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. - 0x000000fc - - - DBG - If 1, TIMER1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [7:7] - read-write - - - DMA - If 1, TIMER1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [6:6] - read-write - - - CORE1 - If 1, TIMER1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [5:5] - read-write - - - CORE0 - If 1, TIMER1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [4:4] - read-write - - - SP - If 1, TIMER1 can be accessed from a Secure, Privileged context. - [3:3] - read-write - - - SU - If 1, and SP is also set, TIMER1 can be accessed from a Secure, Unprivileged context. - [2:2] - read-write - - - NSP - If 1, TIMER1 can be accessed from a Non-secure, Privileged context. - [1:1] - read-write - - - NSU - If 1, and NSP is also set, TIMER1 can be accessed from a Non-secure, Unprivileged context. - - This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. - [0:0] - read-write - - - - - UART0 - 0x000000a0 - Control whether debugger, DMA, core 0 and core 1 can access UART0, and at what security/privilege levels they can do so. - - Defaults to Secure access from any master. - - This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. - 0x000000fc - - - DBG - If 1, UART0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [7:7] - read-write - - - DMA - If 1, UART0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [6:6] - read-write - - - CORE1 - If 1, UART0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [5:5] - read-write - - - CORE0 - If 1, UART0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [4:4] - read-write - - - SP - If 1, UART0 can be accessed from a Secure, Privileged context. - [3:3] - read-write - - - SU - If 1, and SP is also set, UART0 can be accessed from a Secure, Unprivileged context. - [2:2] - read-write - - - NSP - If 1, UART0 can be accessed from a Non-secure, Privileged context. - [1:1] - read-write - - - NSU - If 1, and NSP is also set, UART0 can be accessed from a Non-secure, Unprivileged context. - - This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. - [0:0] - read-write - - - - - UART1 - 0x000000a4 - Control whether debugger, DMA, core 0 and core 1 can access UART1, and at what security/privilege levels they can do so. - - Defaults to Secure access from any master. - - This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. - 0x000000fc - - - DBG - If 1, UART1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [7:7] - read-write - - - DMA - If 1, UART1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [6:6] - read-write - - - CORE1 - If 1, UART1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [5:5] - read-write - - - CORE0 - If 1, UART1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [4:4] - read-write - - - SP - If 1, UART1 can be accessed from a Secure, Privileged context. - [3:3] - read-write - - - SU - If 1, and SP is also set, UART1 can be accessed from a Secure, Unprivileged context. - [2:2] - read-write - - - NSP - If 1, UART1 can be accessed from a Non-secure, Privileged context. - [1:1] - read-write - - - NSU - If 1, and NSP is also set, UART1 can be accessed from a Non-secure, Unprivileged context. - - This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. - [0:0] - read-write - - - - - OTP - 0x000000a8 - Control whether debugger, DMA, core 0 and core 1 can access OTP, and at what security/privilege levels they can do so. - - Defaults to Secure access from any master. - - This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. - 0x000000fc - - - DBG - If 1, OTP can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [7:7] - read-write - - - DMA - If 1, OTP can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [6:6] - read-write - - - CORE1 - If 1, OTP can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [5:5] - read-write - - - CORE0 - If 1, OTP can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [4:4] - read-write - - - SP - If 1, OTP can be accessed from a Secure, Privileged context. - [3:3] - read-write - - - SU - If 1, and SP is also set, OTP can be accessed from a Secure, Unprivileged context. - [2:2] - read-write - - - NSP - If 1, OTP can be accessed from a Non-secure, Privileged context. - [1:1] - read-write - - - NSU - If 1, and NSP is also set, OTP can be accessed from a Non-secure, Unprivileged context. - - This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. - [0:0] - read-write - - - - - TBMAN - 0x000000ac - Control whether debugger, DMA, core 0 and core 1 can access TBMAN, and at what security/privilege levels they can do so. - - Defaults to Secure access from any master. - - This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. - 0x000000fc - - - DBG - If 1, TBMAN can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [7:7] - read-write - - - DMA - If 1, TBMAN can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [6:6] - read-write - - - CORE1 - If 1, TBMAN can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [5:5] - read-write - - - CORE0 - If 1, TBMAN can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [4:4] - read-write - - - SP - If 1, TBMAN can be accessed from a Secure, Privileged context. - [3:3] - read-write - - - SU - If 1, and SP is also set, TBMAN can be accessed from a Secure, Unprivileged context. - [2:2] - read-write - - - NSP - If 1, TBMAN can be accessed from a Non-secure, Privileged context. - [1:1] - read-write - - - NSU - If 1, and NSP is also set, TBMAN can be accessed from a Non-secure, Unprivileged context. - - This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. - [0:0] - read-write - - - - - POWMAN - 0x000000b0 - Control whether debugger, DMA, core 0 and core 1 can access POWMAN, and at what security/privilege levels they can do so. - - Defaults to Secure, Privileged processor or debug access only. - - This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. - 0x000000b8 - - - DBG - If 1, POWMAN can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [7:7] - read-write - - - DMA - If 1, POWMAN can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [6:6] - read-write - - - CORE1 - If 1, POWMAN can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [5:5] - read-write - - - CORE0 - If 1, POWMAN can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [4:4] - read-write - - - SP - If 1, POWMAN can be accessed from a Secure, Privileged context. - [3:3] - read-write - - - SU - If 1, and SP is also set, POWMAN can be accessed from a Secure, Unprivileged context. - [2:2] - read-write - - - NSP - If 1, POWMAN can be accessed from a Non-secure, Privileged context. - [1:1] - read-write - - - NSU - If 1, and NSP is also set, POWMAN can be accessed from a Non-secure, Unprivileged context. - - This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. - [0:0] - read-write - - - - - TRNG - 0x000000b4 - Control whether debugger, DMA, core 0 and core 1 can access TRNG, and at what security/privilege levels they can do so. - - Defaults to Secure, Privileged processor or debug access only. - - This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. - 0x000000b8 - - - DBG - If 1, TRNG can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [7:7] - read-write - - - DMA - If 1, TRNG can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [6:6] - read-write - - - CORE1 - If 1, TRNG can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [5:5] - read-write - - - CORE0 - If 1, TRNG can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [4:4] - read-write - - - SP - If 1, TRNG can be accessed from a Secure, Privileged context. - [3:3] - read-write - - - SU - If 1, and SP is also set, TRNG can be accessed from a Secure, Unprivileged context. - [2:2] - read-write - - - NSP - If 1, TRNG can be accessed from a Non-secure, Privileged context. - [1:1] - read-write - - - NSU - If 1, and NSP is also set, TRNG can be accessed from a Non-secure, Unprivileged context. - - This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. - [0:0] - read-write - - - - - SHA256 - 0x000000b8 - Control whether debugger, DMA, core 0 and core 1 can access SHA256, and at what security/privilege levels they can do so. - - Defaults to Secure, Privileged access only. - - This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. - 0x000000f8 - - - DBG - If 1, SHA256 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [7:7] - read-write - - - DMA - If 1, SHA256 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [6:6] - read-write - - - CORE1 - If 1, SHA256 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [5:5] - read-write - - - CORE0 - If 1, SHA256 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [4:4] - read-write - - - SP - If 1, SHA256 can be accessed from a Secure, Privileged context. - [3:3] - read-write - - - SU - If 1, and SP is also set, SHA256 can be accessed from a Secure, Unprivileged context. - [2:2] - read-write - - - NSP - If 1, SHA256 can be accessed from a Non-secure, Privileged context. - [1:1] - read-write - - - NSU - If 1, and NSP is also set, SHA256 can be accessed from a Non-secure, Unprivileged context. - - This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. - [0:0] - read-write - - - - - SYSCFG - 0x000000bc - Control whether debugger, DMA, core 0 and core 1 can access SYSCFG, and at what security/privilege levels they can do so. - - Defaults to Secure, Privileged processor or debug access only. - - This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. - 0x000000b8 - - - DBG - If 1, SYSCFG can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [7:7] - read-write - - - DMA - If 1, SYSCFG can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [6:6] - read-write - - - CORE1 - If 1, SYSCFG can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [5:5] - read-write - - - CORE0 - If 1, SYSCFG can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [4:4] - read-write - - - SP - If 1, SYSCFG can be accessed from a Secure, Privileged context. - [3:3] - read-write - - - SU - If 1, and SP is also set, SYSCFG can be accessed from a Secure, Unprivileged context. - [2:2] - read-write - - - NSP - If 1, SYSCFG can be accessed from a Non-secure, Privileged context. - [1:1] - read-write - - - NSU - If 1, and NSP is also set, SYSCFG can be accessed from a Non-secure, Unprivileged context. - - This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. - [0:0] - read-write - - - - - CLOCKS - 0x000000c0 - Control whether debugger, DMA, core 0 and core 1 can access CLOCKS, and at what security/privilege levels they can do so. - - Defaults to Secure, Privileged processor or debug access only. - - This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. - 0x000000b8 - - - DBG - If 1, CLOCKS can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [7:7] - read-write - - - DMA - If 1, CLOCKS can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [6:6] - read-write - - - CORE1 - If 1, CLOCKS can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [5:5] - read-write - - - CORE0 - If 1, CLOCKS can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [4:4] - read-write - - - SP - If 1, CLOCKS can be accessed from a Secure, Privileged context. - [3:3] - read-write - - - SU - If 1, and SP is also set, CLOCKS can be accessed from a Secure, Unprivileged context. - [2:2] - read-write - - - NSP - If 1, CLOCKS can be accessed from a Non-secure, Privileged context. - [1:1] - read-write - - - NSU - If 1, and NSP is also set, CLOCKS can be accessed from a Non-secure, Unprivileged context. - - This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. - [0:0] - read-write - - - - - XOSC - 0x000000c4 - Control whether debugger, DMA, core 0 and core 1 can access XOSC, and at what security/privilege levels they can do so. - - Defaults to Secure, Privileged processor or debug access only. - - This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. - 0x000000b8 - - - DBG - If 1, XOSC can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [7:7] - read-write - - - DMA - If 1, XOSC can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [6:6] - read-write - - - CORE1 - If 1, XOSC can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [5:5] - read-write - - - CORE0 - If 1, XOSC can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [4:4] - read-write - - - SP - If 1, XOSC can be accessed from a Secure, Privileged context. - [3:3] - read-write - - - SU - If 1, and SP is also set, XOSC can be accessed from a Secure, Unprivileged context. - [2:2] - read-write - - - NSP - If 1, XOSC can be accessed from a Non-secure, Privileged context. - [1:1] - read-write - - - NSU - If 1, and NSP is also set, XOSC can be accessed from a Non-secure, Unprivileged context. - - This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. - [0:0] - read-write - - - - - ROSC - 0x000000c8 - Control whether debugger, DMA, core 0 and core 1 can access ROSC, and at what security/privilege levels they can do so. - - Defaults to Secure, Privileged processor or debug access only. - - This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. - 0x000000b8 - - - DBG - If 1, ROSC can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [7:7] - read-write - - - DMA - If 1, ROSC can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [6:6] - read-write - - - CORE1 - If 1, ROSC can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [5:5] - read-write - - - CORE0 - If 1, ROSC can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [4:4] - read-write - - - SP - If 1, ROSC can be accessed from a Secure, Privileged context. - [3:3] - read-write - - - SU - If 1, and SP is also set, ROSC can be accessed from a Secure, Unprivileged context. - [2:2] - read-write - - - NSP - If 1, ROSC can be accessed from a Non-secure, Privileged context. - [1:1] - read-write - - - NSU - If 1, and NSP is also set, ROSC can be accessed from a Non-secure, Unprivileged context. - - This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. - [0:0] - read-write - - - - - PLL_SYS - 0x000000cc - Control whether debugger, DMA, core 0 and core 1 can access PLL_SYS, and at what security/privilege levels they can do so. - - Defaults to Secure, Privileged processor or debug access only. - - This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. - 0x000000b8 - - - DBG - If 1, PLL_SYS can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [7:7] - read-write - - - DMA - If 1, PLL_SYS can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [6:6] - read-write - - - CORE1 - If 1, PLL_SYS can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [5:5] - read-write - - - CORE0 - If 1, PLL_SYS can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [4:4] - read-write - - - SP - If 1, PLL_SYS can be accessed from a Secure, Privileged context. - [3:3] - read-write - - - SU - If 1, and SP is also set, PLL_SYS can be accessed from a Secure, Unprivileged context. - [2:2] - read-write - - - NSP - If 1, PLL_SYS can be accessed from a Non-secure, Privileged context. - [1:1] - read-write - - - NSU - If 1, and NSP is also set, PLL_SYS can be accessed from a Non-secure, Unprivileged context. - - This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. - [0:0] - read-write - - - - - PLL_USB - 0x000000d0 - Control whether debugger, DMA, core 0 and core 1 can access PLL_USB, and at what security/privilege levels they can do so. - - Defaults to Secure, Privileged processor or debug access only. - - This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. - 0x000000b8 - - - DBG - If 1, PLL_USB can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [7:7] - read-write - - - DMA - If 1, PLL_USB can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [6:6] - read-write - - - CORE1 - If 1, PLL_USB can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [5:5] - read-write - - - CORE0 - If 1, PLL_USB can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [4:4] - read-write - - - SP - If 1, PLL_USB can be accessed from a Secure, Privileged context. - [3:3] - read-write - - - SU - If 1, and SP is also set, PLL_USB can be accessed from a Secure, Unprivileged context. - [2:2] - read-write - - - NSP - If 1, PLL_USB can be accessed from a Non-secure, Privileged context. - [1:1] - read-write - - - NSU - If 1, and NSP is also set, PLL_USB can be accessed from a Non-secure, Unprivileged context. - - This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. - [0:0] - read-write - - - - - TICKS - 0x000000d4 - Control whether debugger, DMA, core 0 and core 1 can access TICKS, and at what security/privilege levels they can do so. - - Defaults to Secure, Privileged processor or debug access only. - - This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. - 0x000000b8 - - - DBG - If 1, TICKS can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [7:7] - read-write - - - DMA - If 1, TICKS can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [6:6] - read-write - - - CORE1 - If 1, TICKS can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [5:5] - read-write - - - CORE0 - If 1, TICKS can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [4:4] - read-write - - - SP - If 1, TICKS can be accessed from a Secure, Privileged context. - [3:3] - read-write - - - SU - If 1, and SP is also set, TICKS can be accessed from a Secure, Unprivileged context. - [2:2] - read-write - - - NSP - If 1, TICKS can be accessed from a Non-secure, Privileged context. - [1:1] - read-write - - - NSU - If 1, and NSP is also set, TICKS can be accessed from a Non-secure, Unprivileged context. - - This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. - [0:0] - read-write - - - - - WATCHDOG - 0x000000d8 - Control whether debugger, DMA, core 0 and core 1 can access WATCHDOG, and at what security/privilege levels they can do so. - - Defaults to Secure, Privileged processor or debug access only. - - This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. - 0x000000b8 - - - DBG - If 1, WATCHDOG can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [7:7] - read-write - - - DMA - If 1, WATCHDOG can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [6:6] - read-write - - - CORE1 - If 1, WATCHDOG can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [5:5] - read-write - - - CORE0 - If 1, WATCHDOG can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [4:4] - read-write - - - SP - If 1, WATCHDOG can be accessed from a Secure, Privileged context. - [3:3] - read-write - - - SU - If 1, and SP is also set, WATCHDOG can be accessed from a Secure, Unprivileged context. - [2:2] - read-write - - - NSP - If 1, WATCHDOG can be accessed from a Non-secure, Privileged context. - [1:1] - read-write - - - NSU - If 1, and NSP is also set, WATCHDOG can be accessed from a Non-secure, Unprivileged context. - - This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. - [0:0] - read-write - - - - - RSM - 0x000000dc - Control whether debugger, DMA, core 0 and core 1 can access RSM, and at what security/privilege levels they can do so. - - Defaults to Secure, Privileged processor or debug access only. - - This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. - 0x000000b8 - - - DBG - If 1, RSM can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [7:7] - read-write - - - DMA - If 1, RSM can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [6:6] - read-write - - - CORE1 - If 1, RSM can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [5:5] - read-write - - - CORE0 - If 1, RSM can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [4:4] - read-write - - - SP - If 1, RSM can be accessed from a Secure, Privileged context. - [3:3] - read-write - - - SU - If 1, and SP is also set, RSM can be accessed from a Secure, Unprivileged context. - [2:2] - read-write - - - NSP - If 1, RSM can be accessed from a Non-secure, Privileged context. - [1:1] - read-write - - - NSU - If 1, and NSP is also set, RSM can be accessed from a Non-secure, Unprivileged context. - - This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. - [0:0] - read-write - - - - - XIP_CTRL - 0x000000e0 - Control whether debugger, DMA, core 0 and core 1 can access XIP_CTRL, and at what security/privilege levels they can do so. - - Defaults to Secure, Privileged processor or debug access only. - - This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. - 0x000000b8 - - - DBG - If 1, XIP_CTRL can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [7:7] - read-write - - - DMA - If 1, XIP_CTRL can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [6:6] - read-write - - - CORE1 - If 1, XIP_CTRL can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [5:5] - read-write - - - CORE0 - If 1, XIP_CTRL can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [4:4] - read-write - - - SP - If 1, XIP_CTRL can be accessed from a Secure, Privileged context. - [3:3] - read-write - - - SU - If 1, and SP is also set, XIP_CTRL can be accessed from a Secure, Unprivileged context. - [2:2] - read-write - - - NSP - If 1, XIP_CTRL can be accessed from a Non-secure, Privileged context. - [1:1] - read-write - - - NSU - If 1, and NSP is also set, XIP_CTRL can be accessed from a Non-secure, Unprivileged context. - - This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. - [0:0] - read-write - - - - - XIP_QMI - 0x000000e4 - Control whether debugger, DMA, core 0 and core 1 can access XIP_QMI, and at what security/privilege levels they can do so. - - Defaults to Secure, Privileged processor or debug access only. - - This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. - 0x000000b8 - - - DBG - If 1, XIP_QMI can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [7:7] - read-write - - - DMA - If 1, XIP_QMI can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [6:6] - read-write - - - CORE1 - If 1, XIP_QMI can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [5:5] - read-write - - - CORE0 - If 1, XIP_QMI can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [4:4] - read-write - - - SP - If 1, XIP_QMI can be accessed from a Secure, Privileged context. - [3:3] - read-write - - - SU - If 1, and SP is also set, XIP_QMI can be accessed from a Secure, Unprivileged context. - [2:2] - read-write - - - NSP - If 1, XIP_QMI can be accessed from a Non-secure, Privileged context. - [1:1] - read-write - - - NSU - If 1, and NSP is also set, XIP_QMI can be accessed from a Non-secure, Unprivileged context. - - This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. - [0:0] - read-write - - - - - XIP_AUX - 0x000000e8 - Control whether debugger, DMA, core 0 and core 1 can access XIP_AUX, and at what security/privilege levels they can do so. - - Defaults to Secure, Privileged access only. - - This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. - 0x000000f8 - - - DBG - If 1, XIP_AUX can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [7:7] - read-write - - - DMA - If 1, XIP_AUX can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [6:6] - read-write - - - CORE1 - If 1, XIP_AUX can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [5:5] - read-write - - - CORE0 - If 1, XIP_AUX can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. - [4:4] - read-write - - - SP - If 1, XIP_AUX can be accessed from a Secure, Privileged context. - [3:3] - read-write - - - SU - If 1, and SP is also set, XIP_AUX can be accessed from a Secure, Unprivileged context. - [2:2] - read-write - - - NSP - If 1, XIP_AUX can be accessed from a Non-secure, Privileged context. - [1:1] - read-write - - - NSU - If 1, and NSP is also set, XIP_AUX can be accessed from a Non-secure, Unprivileged context. - - This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. - [0:0] - read-write - - - - - - - UART0 - 0x40070000 - - 0 - 4096 - registers - - - UART0_IRQ - 33 - - - - UARTDR - 0x00000000 - Data Register, UARTDR - 0x00000000 - - - OE - Overrun error. This bit is set to 1 if data is received and the receive FIFO is already full. This is cleared to 0 once there is an empty space in the FIFO and a new character can be written to it. - [11:11] - read-only - - - BE - Break error. This bit is set to 1 if a break condition was detected, indicating that the received data input was held LOW for longer than a full-word transmission time (defined as start, data, parity and stop bits). In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state), and the next valid start bit is received. - [10:10] - read-only - - - PE - Parity error. When set to 1, it indicates that the parity of the received data character does not match the parity that the EPS and SPS bits in the Line Control Register, UARTLCR_H. In FIFO mode, this error is associated with the character at the top of the FIFO. - [9:9] - read-only - - - FE - Framing error. When set to 1, it indicates that the received character did not have a valid stop bit (a valid stop bit is 1). In FIFO mode, this error is associated with the character at the top of the FIFO. - [8:8] - read-only - - - DATA - Receive (read) data character. Transmit (write) data character. - [7:0] - read-write - modify - - - - - UARTRSR - 0x00000004 - Receive Status Register/Error Clear Register, UARTRSR/UARTECR - 0x00000000 - - - OE - Overrun error. This bit is set to 1 if data is received and the FIFO is already full. This bit is cleared to 0 by a write to UARTECR. The FIFO contents remain valid because no more data is written when the FIFO is full, only the contents of the shift register are overwritten. The CPU must now read the data, to empty the FIFO. - [3:3] - read-write - oneToClear - - - BE - Break error. This bit is set to 1 if a break condition was detected, indicating that the received data input was held LOW for longer than a full-word transmission time (defined as start, data, parity, and stop bits). This bit is cleared to 0 after a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state) and the next valid start bit is received. - [2:2] - read-write - oneToClear - - - PE - Parity error. When set to 1, it indicates that the parity of the received data character does not match the parity that the EPS and SPS bits in the Line Control Register, UARTLCR_H. This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO. - [1:1] - read-write - oneToClear - - - FE - Framing error. When set to 1, it indicates that the received character did not have a valid stop bit (a valid stop bit is 1). This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO. - [0:0] - read-write - oneToClear - - - - - UARTFR - 0x00000018 - Flag Register, UARTFR - 0x00000090 - - - RI - Ring indicator. This bit is the complement of the UART ring indicator, nUARTRI, modem status input. That is, the bit is 1 when nUARTRI is LOW. - [8:8] - read-only - - - TXFE - Transmit FIFO empty. The meaning of this bit depends on the state of the FEN bit in the Line Control Register, UARTLCR_H. If the FIFO is disabled, this bit is set when the transmit holding register is empty. If the FIFO is enabled, the TXFE bit is set when the transmit FIFO is empty. This bit does not indicate if there is data in the transmit shift register. - [7:7] - read-only - - - RXFF - Receive FIFO full. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the receive holding register is full. If the FIFO is enabled, the RXFF bit is set when the receive FIFO is full. - [6:6] - read-only - - - TXFF - Transmit FIFO full. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the transmit holding register is full. If the FIFO is enabled, the TXFF bit is set when the transmit FIFO is full. - [5:5] - read-only - - - RXFE - Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the receive holding register is empty. If the FIFO is enabled, the RXFE bit is set when the receive FIFO is empty. - [4:4] - read-only - - - BUSY - UART busy. If this bit is set to 1, the UART is busy transmitting data. This bit remains set until the complete byte, including all the stop bits, has been sent from the shift register. This bit is set as soon as the transmit FIFO becomes non-empty, regardless of whether the UART is enabled or not. - [3:3] - read-only - - - DCD - Data carrier detect. This bit is the complement of the UART data carrier detect, nUARTDCD, modem status input. That is, the bit is 1 when nUARTDCD is LOW. - [2:2] - read-only - - - DSR - Data set ready. This bit is the complement of the UART data set ready, nUARTDSR, modem status input. That is, the bit is 1 when nUARTDSR is LOW. - [1:1] - read-only - - - CTS - Clear to send. This bit is the complement of the UART clear to send, nUARTCTS, modem status input. That is, the bit is 1 when nUARTCTS is LOW. - [0:0] - read-only - - - - - UARTILPR - 0x00000020 - IrDA Low-Power Counter Register, UARTILPR - 0x00000000 - - - ILPDVSR - 8-bit low-power divisor value. These bits are cleared to 0 at reset. - [7:0] - read-write - - - - - UARTIBRD - 0x00000024 - Integer Baud Rate Register, UARTIBRD - 0x00000000 - - - BAUD_DIVINT - The integer baud rate divisor. These bits are cleared to 0 on reset. - [15:0] - read-write - - - - - UARTFBRD - 0x00000028 - Fractional Baud Rate Register, UARTFBRD - 0x00000000 - - - BAUD_DIVFRAC - The fractional baud rate divisor. These bits are cleared to 0 on reset. - [5:0] - read-write - - - - - UARTLCR_H - 0x0000002c - Line Control Register, UARTLCR_H - 0x00000000 - - - SPS - Stick parity select. 0 = stick parity is disabled 1 = either: * if the EPS bit is 0 then the parity bit is transmitted and checked as a 1 * if the EPS bit is 1 then the parity bit is transmitted and checked as a 0. This bit has no effect when the PEN bit disables parity checking and generation. - [7:7] - read-write - - - WLEN - Word length. These bits indicate the number of data bits transmitted or received in a frame as follows: b11 = 8 bits b10 = 7 bits b01 = 6 bits b00 = 5 bits. - [6:5] - read-write - - - FEN - Enable FIFOs: 0 = FIFOs are disabled (character mode) that is, the FIFOs become 1-byte-deep holding registers 1 = transmit and receive FIFO buffers are enabled (FIFO mode). - [4:4] - read-write - - - STP2 - Two stop bits select. If this bit is set to 1, two stop bits are transmitted at the end of the frame. The receive logic does not check for two stop bits being received. - [3:3] - read-write - - - EPS - Even parity select. Controls the type of parity the UART uses during transmission and reception: 0 = odd parity. The UART generates or checks for an odd number of 1s in the data and parity bits. 1 = even parity. The UART generates or checks for an even number of 1s in the data and parity bits. This bit has no effect when the PEN bit disables parity checking and generation. - [2:2] - read-write - - - PEN - Parity enable: 0 = parity is disabled and no parity bit added to the data frame 1 = parity checking and generation is enabled. - [1:1] - read-write - - - BRK - Send break. If this bit is set to 1, a low-level is continually output on the UARTTXD output, after completing transmission of the current character. For the proper execution of the break command, the software must set this bit for at least two complete frames. For normal use, this bit must be cleared to 0. - [0:0] - read-write - - - - - UARTCR - 0x00000030 - Control Register, UARTCR - 0x00000300 - - - CTSEN - CTS hardware flow control enable. If this bit is set to 1, CTS hardware flow control is enabled. Data is only transmitted when the nUARTCTS signal is asserted. - [15:15] - read-write - - - RTSEN - RTS hardware flow control enable. If this bit is set to 1, RTS hardware flow control is enabled. Data is only requested when there is space in the receive FIFO for it to be received. - [14:14] - read-write - - - OUT2 - This bit is the complement of the UART Out2 (nUARTOut2) modem status output. That is, when the bit is programmed to a 1, the output is 0. For DTE this can be used as Ring Indicator (RI). - [13:13] - read-write - - - OUT1 - This bit is the complement of the UART Out1 (nUARTOut1) modem status output. That is, when the bit is programmed to a 1 the output is 0. For DTE this can be used as Data Carrier Detect (DCD). - [12:12] - read-write - - - RTS - Request to send. This bit is the complement of the UART request to send, nUARTRTS, modem status output. That is, when the bit is programmed to a 1 then nUARTRTS is LOW. - [11:11] - read-write - - - DTR - Data transmit ready. This bit is the complement of the UART data transmit ready, nUARTDTR, modem status output. That is, when the bit is programmed to a 1 then nUARTDTR is LOW. - [10:10] - read-write - - - RXE - Receive enable. If this bit is set to 1, the receive section of the UART is enabled. Data reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of reception, it completes the current character before stopping. - [9:9] - read-write - - - TXE - Transmit enable. If this bit is set to 1, the transmit section of the UART is enabled. Data transmission occurs for either UART signals, or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of transmission, it completes the current character before stopping. - [8:8] - read-write - - - LBE - Loopback enable. If this bit is set to 1 and the SIREN bit is set to 1 and the SIRTEST bit in the Test Control Register, UARTTCR is set to 1, then the nSIROUT path is inverted, and fed through to the SIRIN path. The SIRTEST bit in the test register must be set to 1 to override the normal half-duplex SIR operation. This must be the requirement for accessing the test registers during normal operation, and SIRTEST must be cleared to 0 when loopback testing is finished. This feature reduces the amount of external coupling required during system test. If this bit is set to 1, and the SIRTEST bit is set to 0, the UARTTXD path is fed through to the UARTRXD path. In either SIR mode or UART mode, when this bit is set, the modem outputs are also fed through to the modem inputs. This bit is cleared to 0 on reset, to disable loopback. - [7:7] - read-write - - - SIRLP - SIR low-power IrDA mode. This bit selects the IrDA encoding mode. If this bit is cleared to 0, low-level bits are transmitted as an active high pulse with a width of 3 / 16th of the bit period. If this bit is set to 1, low-level bits are transmitted with a pulse width that is 3 times the period of the IrLPBaud16 input signal, regardless of the selected bit rate. Setting this bit uses less power, but might reduce transmission distances. - [2:2] - read-write - - - SIREN - SIR enable: 0 = IrDA SIR ENDEC is disabled. nSIROUT remains LOW (no light pulse generated), and signal transitions on SIRIN have no effect. 1 = IrDA SIR ENDEC is enabled. Data is transmitted and received on nSIROUT and SIRIN. UARTTXD remains HIGH, in the marking state. Signal transitions on UARTRXD or modem status inputs have no effect. This bit has no effect if the UARTEN bit disables the UART. - [1:1] - read-write - - - UARTEN - UART enable: 0 = UART is disabled. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. 1 = the UART is enabled. Data transmission and reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit. - [0:0] - read-write - - - - - UARTIFLS - 0x00000034 - Interrupt FIFO Level Select Register, UARTIFLS - 0x00000012 - - - RXIFLSEL - Receive interrupt FIFO level select. The trigger points for the receive interrupt are as follows: b000 = Receive FIFO becomes >= 1 / 8 full b001 = Receive FIFO becomes >= 1 / 4 full b010 = Receive FIFO becomes >= 1 / 2 full b011 = Receive FIFO becomes >= 3 / 4 full b100 = Receive FIFO becomes >= 7 / 8 full b101-b111 = reserved. - [5:3] - read-write - - - TXIFLSEL - Transmit interrupt FIFO level select. The trigger points for the transmit interrupt are as follows: b000 = Transmit FIFO becomes <= 1 / 8 full b001 = Transmit FIFO becomes <= 1 / 4 full b010 = Transmit FIFO becomes <= 1 / 2 full b011 = Transmit FIFO becomes <= 3 / 4 full b100 = Transmit FIFO becomes <= 7 / 8 full b101-b111 = reserved. - [2:0] - read-write - - - - - UARTIMSC - 0x00000038 - Interrupt Mask Set/Clear Register, UARTIMSC - 0x00000000 - - - OEIM - Overrun error interrupt mask. A read returns the current mask for the UARTOEINTR interrupt. On a write of 1, the mask of the UARTOEINTR interrupt is set. A write of 0 clears the mask. - [10:10] - read-write - - - BEIM - Break error interrupt mask. A read returns the current mask for the UARTBEINTR interrupt. On a write of 1, the mask of the UARTBEINTR interrupt is set. A write of 0 clears the mask. - [9:9] - read-write - - - PEIM - Parity error interrupt mask. A read returns the current mask for the UARTPEINTR interrupt. On a write of 1, the mask of the UARTPEINTR interrupt is set. A write of 0 clears the mask. - [8:8] - read-write - - - FEIM - Framing error interrupt mask. A read returns the current mask for the UARTFEINTR interrupt. On a write of 1, the mask of the UARTFEINTR interrupt is set. A write of 0 clears the mask. - [7:7] - read-write - - - RTIM - Receive timeout interrupt mask. A read returns the current mask for the UARTRTINTR interrupt. On a write of 1, the mask of the UARTRTINTR interrupt is set. A write of 0 clears the mask. - [6:6] - read-write - - - TXIM - Transmit interrupt mask. A read returns the current mask for the UARTTXINTR interrupt. On a write of 1, the mask of the UARTTXINTR interrupt is set. A write of 0 clears the mask. - [5:5] - read-write - - - RXIM - Receive interrupt mask. A read returns the current mask for the UARTRXINTR interrupt. On a write of 1, the mask of the UARTRXINTR interrupt is set. A write of 0 clears the mask. - [4:4] - read-write - - - DSRMIM - nUARTDSR modem interrupt mask. A read returns the current mask for the UARTDSRINTR interrupt. On a write of 1, the mask of the UARTDSRINTR interrupt is set. A write of 0 clears the mask. - [3:3] - read-write - - - DCDMIM - nUARTDCD modem interrupt mask. A read returns the current mask for the UARTDCDINTR interrupt. On a write of 1, the mask of the UARTDCDINTR interrupt is set. A write of 0 clears the mask. - [2:2] - read-write - - - CTSMIM - nUARTCTS modem interrupt mask. A read returns the current mask for the UARTCTSINTR interrupt. On a write of 1, the mask of the UARTCTSINTR interrupt is set. A write of 0 clears the mask. - [1:1] - read-write - - - RIMIM - nUARTRI modem interrupt mask. A read returns the current mask for the UARTRIINTR interrupt. On a write of 1, the mask of the UARTRIINTR interrupt is set. A write of 0 clears the mask. - [0:0] - read-write - - - - - UARTRIS - 0x0000003c - Raw Interrupt Status Register, UARTRIS - 0x00000000 - - - OERIS - Overrun error interrupt status. Returns the raw interrupt state of the UARTOEINTR interrupt. - [10:10] - read-only - - - BERIS - Break error interrupt status. Returns the raw interrupt state of the UARTBEINTR interrupt. - [9:9] - read-only - - - PERIS - Parity error interrupt status. Returns the raw interrupt state of the UARTPEINTR interrupt. - [8:8] - read-only - - - FERIS - Framing error interrupt status. Returns the raw interrupt state of the UARTFEINTR interrupt. - [7:7] - read-only - - - RTRIS - Receive timeout interrupt status. Returns the raw interrupt state of the UARTRTINTR interrupt. a - [6:6] - read-only - - - TXRIS - Transmit interrupt status. Returns the raw interrupt state of the UARTTXINTR interrupt. - [5:5] - read-only - - - RXRIS - Receive interrupt status. Returns the raw interrupt state of the UARTRXINTR interrupt. - [4:4] - read-only - - - DSRRMIS - nUARTDSR modem interrupt status. Returns the raw interrupt state of the UARTDSRINTR interrupt. - [3:3] - read-only - - - DCDRMIS - nUARTDCD modem interrupt status. Returns the raw interrupt state of the UARTDCDINTR interrupt. - [2:2] - read-only - - - CTSRMIS - nUARTCTS modem interrupt status. Returns the raw interrupt state of the UARTCTSINTR interrupt. - [1:1] - read-only - - - RIRMIS - nUARTRI modem interrupt status. Returns the raw interrupt state of the UARTRIINTR interrupt. - [0:0] - read-only - - - - - UARTMIS - 0x00000040 - Masked Interrupt Status Register, UARTMIS - 0x00000000 - - - OEMIS - Overrun error masked interrupt status. Returns the masked interrupt state of the UARTOEINTR interrupt. - [10:10] - read-only - - - BEMIS - Break error masked interrupt status. Returns the masked interrupt state of the UARTBEINTR interrupt. - [9:9] - read-only - - - PEMIS - Parity error masked interrupt status. Returns the masked interrupt state of the UARTPEINTR interrupt. - [8:8] - read-only - - - FEMIS - Framing error masked interrupt status. Returns the masked interrupt state of the UARTFEINTR interrupt. - [7:7] - read-only - - - RTMIS - Receive timeout masked interrupt status. Returns the masked interrupt state of the UARTRTINTR interrupt. - [6:6] - read-only - - - TXMIS - Transmit masked interrupt status. Returns the masked interrupt state of the UARTTXINTR interrupt. - [5:5] - read-only - - - RXMIS - Receive masked interrupt status. Returns the masked interrupt state of the UARTRXINTR interrupt. - [4:4] - read-only - - - DSRMMIS - nUARTDSR modem masked interrupt status. Returns the masked interrupt state of the UARTDSRINTR interrupt. - [3:3] - read-only - - - DCDMMIS - nUARTDCD modem masked interrupt status. Returns the masked interrupt state of the UARTDCDINTR interrupt. - [2:2] - read-only - - - CTSMMIS - nUARTCTS modem masked interrupt status. Returns the masked interrupt state of the UARTCTSINTR interrupt. - [1:1] - read-only - - - RIMMIS - nUARTRI modem masked interrupt status. Returns the masked interrupt state of the UARTRIINTR interrupt. - [0:0] - read-only - - - - - UARTICR - 0x00000044 - Interrupt Clear Register, UARTICR - 0x00000000 - - - OEIC - Overrun error interrupt clear. Clears the UARTOEINTR interrupt. - [10:10] - read-write - oneToClear - - - BEIC - Break error interrupt clear. Clears the UARTBEINTR interrupt. - [9:9] - read-write - oneToClear - - - PEIC - Parity error interrupt clear. Clears the UARTPEINTR interrupt. - [8:8] - read-write - oneToClear - - - FEIC - Framing error interrupt clear. Clears the UARTFEINTR interrupt. - [7:7] - read-write - oneToClear - - - RTIC - Receive timeout interrupt clear. Clears the UARTRTINTR interrupt. - [6:6] - read-write - oneToClear - - - TXIC - Transmit interrupt clear. Clears the UARTTXINTR interrupt. - [5:5] - read-write - oneToClear - - - RXIC - Receive interrupt clear. Clears the UARTRXINTR interrupt. - [4:4] - read-write - oneToClear - - - DSRMIC - nUARTDSR modem interrupt clear. Clears the UARTDSRINTR interrupt. - [3:3] - read-write - oneToClear - - - DCDMIC - nUARTDCD modem interrupt clear. Clears the UARTDCDINTR interrupt. - [2:2] - read-write - oneToClear - - - CTSMIC - nUARTCTS modem interrupt clear. Clears the UARTCTSINTR interrupt. - [1:1] - read-write - oneToClear - - - RIMIC - nUARTRI modem interrupt clear. Clears the UARTRIINTR interrupt. - [0:0] - read-write - oneToClear - - - - - UARTDMACR - 0x00000048 - DMA Control Register, UARTDMACR - 0x00000000 - - - DMAONERR - DMA on error. If this bit is set to 1, the DMA receive request outputs, UARTRXDMASREQ or UARTRXDMABREQ, are disabled when the UART error interrupt is asserted. - [2:2] - read-write - - - TXDMAE - Transmit DMA enable. If this bit is set to 1, DMA for the transmit FIFO is enabled. - [1:1] - read-write - - - RXDMAE - Receive DMA enable. If this bit is set to 1, DMA for the receive FIFO is enabled. - [0:0] - read-write - - - - - UARTPERIPHID0 - 0x00000fe0 - UARTPeriphID0 Register - 0x00000011 - - - PARTNUMBER0 - These bits read back as 0x11 - [7:0] - read-only - - - - - UARTPERIPHID1 - 0x00000fe4 - UARTPeriphID1 Register - 0x00000010 - - - DESIGNER0 - These bits read back as 0x1 - [7:4] - read-only - - - PARTNUMBER1 - These bits read back as 0x0 - [3:0] - read-only - - - - - UARTPERIPHID2 - 0x00000fe8 - UARTPeriphID2 Register - 0x00000034 - - - REVISION - This field depends on the revision of the UART: r1p0 0x0 r1p1 0x1 r1p3 0x2 r1p4 0x2 r1p5 0x3 - [7:4] - read-only - - - DESIGNER1 - These bits read back as 0x4 - [3:0] - read-only - - - - - UARTPERIPHID3 - 0x00000fec - UARTPeriphID3 Register - 0x00000000 - - - CONFIGURATION - These bits read back as 0x00 - [7:0] - read-only - - - - - UARTPCELLID0 - 0x00000ff0 - UARTPCellID0 Register - 0x0000000d - - - UARTPCELLID0 - These bits read back as 0x0D - [7:0] - read-only - - - - - UARTPCELLID1 - 0x00000ff4 - UARTPCellID1 Register - 0x000000f0 - - - UARTPCELLID1 - These bits read back as 0xF0 - [7:0] - read-only - - - - - UARTPCELLID2 - 0x00000ff8 - UARTPCellID2 Register - 0x00000005 - - - UARTPCELLID2 - These bits read back as 0x05 - [7:0] - read-only - - - - - UARTPCELLID3 - 0x00000ffc - UARTPCellID3 Register - 0x000000b1 - - - UARTPCELLID3 - These bits read back as 0xB1 - [7:0] - read-only - - - - - - - UART1 - 0x40078000 - - UART1_IRQ - 34 - - - - ROSC - 0x400e8000 - - 0 - 40 - registers - - - - CTRL - 0x00000000 - Ring Oscillator control - 0x00000aa0 - - - ENABLE - On power-up this field is initialised to ENABLE - The system clock must be switched to another source before setting this field to DISABLE otherwise the chip will lock up - The 12-bit code is intended to give some protection against accidental writes. An invalid setting will enable the oscillator. - [23:12] - read-write - - - DISABLE - 3358 - - - ENABLE - 4011 - - - - - FREQ_RANGE - Controls the number of delay stages in the ROSC ring - LOW uses stages 0 to 7 - MEDIUM uses stages 2 to 7 - HIGH uses stages 4 to 7 - TOOHIGH uses stages 6 to 7 and should not be used because its frequency exceeds design specifications - The clock output will not glitch when changing the range up one step at a time - The clock output will glitch when changing the range down - Note: the values here are gray coded which is why HIGH comes before TOOHIGH - [11:0] - read-write - - - LOW - 4004 - - - MEDIUM - 4005 - - - HIGH - 4007 - - - TOOHIGH - 4006 - - - - - - - FREQA - 0x00000004 - The FREQA & FREQB registers control the frequency by controlling the drive strength of each stage - The drive strength has 4 levels determined by the number of bits set - Increasing the number of bits set increases the drive strength and increases the oscillation frequency - 0 bits set is the default drive strength - 1 bit set doubles the drive strength - 2 bits set triples drive strength - 3 bits set quadruples drive strength - For frequency randomisation set both DS0_RANDOM=1 & DS1_RANDOM=1 - 0x00000000 - - - PASSWD - Set to 0x9696 to apply the settings - Any other value in this field will set all drive strengths to 0 - [31:16] - read-write - - - PASS - 38550 - - - - - DS3 - Stage 3 drive strength - [14:12] - read-write - - - DS2 - Stage 2 drive strength - [10:8] - read-write - - - DS1_RANDOM - Randomises the stage 1 drive strength - [7:7] - read-write - - - DS1 - Stage 1 drive strength - [6:4] - read-write - - - DS0_RANDOM - Randomises the stage 0 drive strength - [3:3] - read-write - - - DS0 - Stage 0 drive strength - [2:0] - read-write - - - - - FREQB - 0x00000008 - For a detailed description see freqa register - 0x00000000 - - - PASSWD - Set to 0x9696 to apply the settings - Any other value in this field will set all drive strengths to 0 - [31:16] - read-write - - - PASS - 38550 - - - - - DS7 - Stage 7 drive strength - [14:12] - read-write - - - DS6 - Stage 6 drive strength - [10:8] - read-write - - - DS5 - Stage 5 drive strength - [6:4] - read-write - - - DS4 - Stage 4 drive strength - [2:0] - read-write - - - - - RANDOM - 0x0000000c - Loads a value to the LFSR randomiser - 0x3f04b16d - - - SEED - [31:0] - read-write - - - - - DORMANT - 0x00000010 - Ring Oscillator pause control - 0x00000000 - - - DORMANT - This is used to save power by pausing the ROSC - On power-up this field is initialised to WAKE - An invalid write will also select WAKE - Warning: setup the irq before selecting dormant mode - [31:0] - read-write - - - dormant - 1668246881 - - - WAKE - 2002873189 - - - - - - - DIV - 0x00000014 - Controls the output divider - 0x00000000 - - - DIV - set to 0xaa00 + div where - div = 0 divides by 128 - div = 1-127 divides by div - any other value sets div=128 - this register resets to div=32 - [15:0] - read-write - - - PASS - 43520 - - - - - - - PHASE - 0x00000018 - Controls the phase shifted output - 0x00000008 - - - PASSWD - set to 0xaa - any other value enables the output with shift=0 - [11:4] - read-write - - - ENABLE - enable the phase-shifted output - this can be changed on-the-fly - [3:3] - read-write - - - FLIP - invert the phase-shifted output - this is ignored when div=1 - [2:2] - read-write - - - SHIFT - phase shift the phase-shifted output by SHIFT input clocks - this can be changed on-the-fly - must be set to 0 before setting div=1 - [1:0] - read-write - - - - - STATUS - 0x0000001c - Ring Oscillator Status - 0x00000000 - - - STABLE - Oscillator is running and stable - [31:31] - read-only - - - BADWRITE - An invalid value has been written to CTRL_ENABLE or CTRL_FREQ_RANGE or FREQA or FREQB or DIV or PHASE or DORMANT - [24:24] - read-write - oneToClear - - - DIV_RUNNING - post-divider is running - this resets to 0 but transitions to 1 during chip startup - [16:16] - read-only - - - ENABLED - Oscillator is enabled but not necessarily running and stable - this resets to 0 but transitions to 1 during chip startup - [12:12] - read-only - - - - - RANDOMBIT - 0x00000020 - This just reads the state of the oscillator output so randomness is compromised if the ring oscillator is stopped or run at a harmonic of the bus frequency - 0x00000001 - - - RANDOMBIT - [0:0] - read-only - - - - - COUNT - 0x00000024 - A down counter running at the ROSC frequency which counts to zero and stops. - To start the counter write a non-zero value. - Can be used for short software pauses when setting up time sensitive hardware. - 0x00000000 - - - COUNT - [15:0] - read-write - - - - - - - POWMAN - Controls vreg, bor, lposc, chip resets & xosc startup, powman and provides scratch register for general use and for bootcode use - 0x40100000 - - 0 - 240 - registers - - - POWMAN_IRQ_POW - 44 - - - POWMAN_IRQ_TIMER - 45 - - - - BADPASSWD - 0x00000000 - Indicates a bad password has been used - 0x00000000 - - - BADPASSWD - [0:0] - read-write - oneToClear - - - - - VREG_CTRL - 0x00000004 - Voltage Regulator Control - 0x00008050 - - - RST_N - returns the regulator to its startup settings - 0 - reset - 1 - not reset (default) - [15:15] - read-write - - - UNLOCK - unlocks the VREG control interface after power up - 0 - Locked (default) - 1 - Unlocked - It cannot be relocked when it is unlocked. - [13:13] - read-write - - - ISOLATE - isolates the VREG control interface - 0 - not isolated (default) - 1 - isolated - [12:12] - read-write - - - DISABLE_VOLTAGE_LIMIT - 0=not disabled, 1=enabled - [8:8] - read-write - - - HT_TH - high temperature protection threshold - regulator power transistors are disabled when junction temperature exceeds threshold - 000 - 100C - 001 - 105C - 010 - 110C - 011 - 115C - 100 - 120C - 101 - 125C - 110 - 135C - 111 - 150C - [6:4] - read-write - - - - - VREG_STS - 0x00000008 - Voltage Regulator Status - 0x00000000 - - - VOUT_OK - output regulation status - 0=not in regulation, 1=in regulation - [4:4] - read-only - - - STARTUP - startup status - 0=startup complete, 1=starting up - [0:0] - read-only - - - - - VREG - 0x0000000c - Voltage Regulator Settings - 0x000000b0 - - - UPDATE_IN_PROGRESS - regulator state is being updated - writes to the vreg register will be ignored when this field is set - [15:15] - read-only - - - VSEL - output voltage select - the regulator output voltage is limited to 1.3V unless the voltage limit - is disabled using the disable_voltage_limit field in the vreg_ctrl register - 00000 - 0.55V - 00001 - 0.60V - 00010 - 0.65V - 00011 - 0.70V - 00100 - 0.75V - 00101 - 0.80V - 00110 - 0.85V - 00111 - 0.90V - 01000 - 0.95V - 01001 - 1.00V - 01010 - 1.05V - 01011 - 1.10V (default) - 01100 - 1.15V - 01101 - 1.20V - 01110 - 1.25V - 01111 - 1.30V - 10000 - 1.35V - 10001 - 1.40V - 10010 - 1.50V - 10011 - 1.60V - 10100 - 1.65V - 10101 - 1.70V - 10110 - 1.80V - 10111 - 1.90V - 11000 - 2.00V - 11001 - 2.35V - 11010 - 2.50V - 11011 - 2.65V - 11100 - 2.80V - 11101 - 3.00V - 11110 - 3.15V - 11111 - 3.30V - [8:4] - read-write - - - HIZ - high impedance mode select - 0=not in high impedance mode, 1=in high impedance mode - [1:1] - read-write - - - - - VREG_LP_ENTRY - 0x00000010 - Voltage Regulator Low Power Entry Settings - 0x000000b4 - - - VSEL - output voltage select - the regulator output voltage is limited to 1.3V unless the voltage limit - is disabled using the disable_voltage_limit field in the vreg_ctrl register - 00000 - 0.55V - 00001 - 0.60V - 00010 - 0.65V - 00011 - 0.70V - 00100 - 0.75V - 00101 - 0.80V - 00110 - 0.85V - 00111 - 0.90V - 01000 - 0.95V - 01001 - 1.00V - 01010 - 1.05V - 01011 - 1.10V (default) - 01100 - 1.15V - 01101 - 1.20V - 01110 - 1.25V - 01111 - 1.30V - 10000 - 1.35V - 10001 - 1.40V - 10010 - 1.50V - 10011 - 1.60V - 10100 - 1.65V - 10101 - 1.70V - 10110 - 1.80V - 10111 - 1.90V - 11000 - 2.00V - 11001 - 2.35V - 11010 - 2.50V - 11011 - 2.65V - 11100 - 2.80V - 11101 - 3.00V - 11110 - 3.15V - 11111 - 3.30V - [8:4] - read-write - - - MODE - selects either normal (switching) mode or low power (linear) mode - low power mode can only be selected for output voltages up to 1.3V - 0 = normal mode (switching) - 1 = low power mode (linear) - [2:2] - read-write - - - HIZ - high impedance mode select - 0=not in high impedance mode, 1=in high impedance mode - [1:1] - read-write - - - - - VREG_LP_EXIT - 0x00000014 - Voltage Regulator Low Power Exit Settings - 0x000000b0 - - - VSEL - output voltage select - the regulator output voltage is limited to 1.3V unless the voltage limit - is disabled using the disable_voltage_limit field in the vreg_ctrl register - 00000 - 0.55V - 00001 - 0.60V - 00010 - 0.65V - 00011 - 0.70V - 00100 - 0.75V - 00101 - 0.80V - 00110 - 0.85V - 00111 - 0.90V - 01000 - 0.95V - 01001 - 1.00V - 01010 - 1.05V - 01011 - 1.10V (default) - 01100 - 1.15V - 01101 - 1.20V - 01110 - 1.25V - 01111 - 1.30V - 10000 - 1.35V - 10001 - 1.40V - 10010 - 1.50V - 10011 - 1.60V - 10100 - 1.65V - 10101 - 1.70V - 10110 - 1.80V - 10111 - 1.90V - 11000 - 2.00V - 11001 - 2.35V - 11010 - 2.50V - 11011 - 2.65V - 11100 - 2.80V - 11101 - 3.00V - 11110 - 3.15V - 11111 - 3.30V - [8:4] - read-write - - - MODE - selects either normal (switching) mode or low power (linear) mode - low power mode can only be selected for output voltages up to 1.3V - 0 = normal mode (switching) - 1 = low power mode (linear) - [2:2] - read-write - - - HIZ - high impedance mode select - 0=not in high impedance mode, 1=in high impedance mode - [1:1] - read-write - - - - - BOD_CTRL - 0x00000018 - Brown-out Detection Control - 0x00000000 - - - ISOLATE - isolates the brown-out detection control interface - 0 - not isolated (default) - 1 - isolated - [12:12] - read-write - - - - - BOD - 0x0000001c - Brown-out Detection Settings - 0x000000b1 - - - VSEL - threshold select - 00000 - 0.473V - 00001 - 0.516V - 00010 - 0.559V - 00011 - 0.602V - 00100 - 0.645VS - 00101 - 0.688V - 00110 - 0.731V - 00111 - 0.774V - 01000 - 0.817V - 01001 - 0.860V (default) - 01010 - 0.903V - 01011 - 0.946V - 01100 - 0.989V - 01101 - 1.032V - 01110 - 1.075V - 01111 - 1.118V - 10000 - 1.161 - 10001 - 1.204V - [8:4] - read-write - - - EN - enable brown-out detection - 0=not enabled, 1=enabled - [0:0] - read-write - - - - - BOD_LP_ENTRY - 0x00000020 - Brown-out Detection Low Power Entry Settings - 0x000000b0 - - - VSEL - threshold select - 00000 - 0.473V - 00001 - 0.516V - 00010 - 0.559V - 00011 - 0.602V - 00100 - 0.645VS - 00101 - 0.688V - 00110 - 0.731V - 00111 - 0.774V - 01000 - 0.817V - 01001 - 0.860V (default) - 01010 - 0.903V - 01011 - 0.946V - 01100 - 0.989V - 01101 - 1.032V - 01110 - 1.075V - 01111 - 1.118V - 10000 - 1.161 - 10001 - 1.204V - [8:4] - read-write - - - EN - enable brown-out detection - 0=not enabled, 1=enabled - [0:0] - read-write - - - - - BOD_LP_EXIT - 0x00000024 - Brown-out Detection Low Power Exit Settings - 0x000000b1 - - - VSEL - threshold select - 00000 - 0.473V - 00001 - 0.516V - 00010 - 0.559V - 00011 - 0.602V - 00100 - 0.645VS - 00101 - 0.688V - 00110 - 0.731V - 00111 - 0.774V - 01000 - 0.817V - 01001 - 0.860V (default) - 01010 - 0.903V - 01011 - 0.946V - 01100 - 0.989V - 01101 - 1.032V - 01110 - 1.075V - 01111 - 1.118V - 10000 - 1.161 - 10001 - 1.204V - [8:4] - read-write - - - EN - enable brown-out detection - 0=not enabled, 1=enabled - [0:0] - read-write - - - - - LPOSC - 0x00000028 - Low power oscillator control register. - 0x00000203 - - - TRIM - Frequency trim - the trim step is typically 1% of the reset frequency, but can be up to 3% - [9:4] - read-write - - - MODE - This feature has been removed - [1:0] - read-write - - - - - CHIP_RESET - 0x0000002c - Chip reset control and status - 0x00000000 - - - HAD_WATCHDOG_RESET_RSM - Last reset was a watchdog timeout which was configured to reset the power-on state machine - This resets: - double_tap flag no - DP no - RPAP no - rescue_flag no - timer no - powman no - swcore no - psm yes - and does not change the power state - [28:28] - read-only - - - HAD_HZD_SYS_RESET_REQ - Last reset was a system reset from the hazard debugger - This resets: - double_tap flag no - DP no - RPAP no - rescue_flag no - timer no - powman no - swcore no - psm yes - and does not change the power state - [27:27] - read-only - - - HAD_GLITCH_DETECT - Last reset was due to a power supply glitch - This resets: - double_tap flag no - DP no - RPAP no - rescue_flag no - timer no - powman no - swcore no - psm yes - and does not change the power state - [26:26] - read-only - - - HAD_SWCORE_PD - Last reset was a switched core powerdown - This resets: - double_tap flag no - DP no - RPAP no - rescue_flag no - timer no - powman no - swcore yes - psm yes - then starts the power sequencer - [25:25] - read-only - - - HAD_WATCHDOG_RESET_SWCORE - Last reset was a watchdog timeout which was configured to reset the switched-core - This resets: - double_tap flag no - DP no - RPAP no - rescue_flag no - timer no - powman no - swcore yes - psm yes - then starts the power sequencer - [24:24] - read-only - - - HAD_WATCHDOG_RESET_POWMAN - Last reset was a watchdog timeout which was configured to reset the power manager - This resets: - double_tap flag no - DP no - RPAP no - rescue_flag no - timer yes - powman yes - swcore yes - psm yes - then starts the power sequencer - [23:23] - read-only - - - HAD_WATCHDOG_RESET_POWMAN_ASYNC - Last reset was a watchdog timeout which was configured to reset the power manager asynchronously - This resets: - double_tap flag no - DP no - RPAP no - rescue_flag no - timer yes - powman yes - swcore yes - psm yes - then starts the power sequencer - [22:22] - read-only - - - HAD_RESCUE - Last reset was a rescue reset from the debugger - This resets: - double_tap flag no - DP no - RPAP no - rescue_flag no, it sets this flag - timer yes - powman yes - swcore yes - psm yes - then starts the power sequencer - [21:21] - read-only - - - HAD_DP_RESET_REQ - Last reset was an reset request from the arm debugger - This resets: - double_tap flag no - DP no - RPAP no - rescue_flag yes - timer yes - powman yes - swcore yes - psm yes - then starts the power sequencer - [19:19] - read-only - - - HAD_RUN_LOW - Last reset was from the RUN pin - This resets: - double_tap flag no - DP yes - RPAP yes - rescue_flag yes - timer yes - powman yes - swcore yes - psm yes - then starts the power sequencer - [18:18] - read-only - - - HAD_BOR - Last reset was from the brown-out detection block - This resets: - double_tap flag yes - DP yes - RPAP yes - rescue_flag yes - timer yes - powman yes - swcore yes - psm yes - then starts the power sequencer - [17:17] - read-only - - - HAD_POR - Last reset was from the power-on reset - This resets: - double_tap flag yes - DP yes - RPAP yes - rescue_flag yes - timer yes - powman yes - swcore yes - psm yes - then starts the power sequencer - [16:16] - read-only - - - RESCUE_FLAG - This is set by a rescue reset from the RP-AP. - Its purpose is to halt before the bootrom before booting from flash in order to recover from a boot lock-up. - The debugger can then attach once the bootrom has been halted and flash some working code that does not lock up. - [4:4] - read-write - oneToClear - - - DOUBLE_TAP - This flag is set by double-tapping RUN. It tells bootcode to go into the bootloader. - [0:0] - read-write - - - - - WDSEL - 0x00000030 - Allows a watchdog reset to reset the internal state of powman in addition to the power-on state machine (PSM). - Note that powman ignores watchdog resets that do not select at least the CLOCKS stage or earlier stages in the PSM. If using these bits, it's recommended to set PSM_WDSEL to all-ones in addition to the desired bits in this register. Failing to select CLOCKS or earlier will result in the POWMAN_WDSEL register having no effect. - 0x00000000 - - - RESET_RSM - If set to 1, a watchdog reset will run the full power-on state machine (PSM) sequence - From a user perspective it is the same as setting RSM_WDSEL_PROC_COLD - From a hardware debug perspective it has the same effect as a reset from a glitch detector - [12:12] - read-write - - - RESET_SWCORE - If set to 1, a watchdog reset will reset the switched core power domain and run the full power-on state machine (PSM) sequence - From a user perspective it is the same as setting RSM_WDSEL_PROC_COLD - From a hardware debug perspective it has the same effect as a power-on reset for the switched core power domain - [8:8] - read-write - - - RESET_POWMAN - If set to 1, a watchdog reset will restore powman defaults, reset the timer, reset the switched core power domain - and run the full power-on state machine (PSM) sequence - This relies on clk_ref running. Use reset_powman_async if that may not be true - [4:4] - read-write - - - RESET_POWMAN_ASYNC - If set to 1, a watchdog reset will restore powman defaults, reset the timer, - reset the switched core domain and run the full power-on state machine (PSM) sequence - This does not rely on clk_ref running - [0:0] - read-write - - - - - SEQ_CFG - 0x00000034 - For configuration of the power sequencer - Writes are ignored while POWMAN_STATE_CHANGING=1 - 0x001011f0 - - - USING_FAST_POWCK - 0 indicates the POWMAN clock is running from the low power oscillator (32kHz) - 1 indicates the POWMAN clock is running from the reference clock (2-50MHz) - [20:20] - read-only - - - USING_BOD_LP - Indicates the brown-out detector (BOD) mode - 0 = BOD high power mode which is the default - 1 = BOD low power mode - [17:17] - read-only - - - USING_VREG_LP - Indicates the voltage regulator (VREG) mode - 0 = VREG high power mode which is the default - 1 = VREG low power mode - [16:16] - read-only - - - USE_FAST_POWCK - selects the reference clock (clk_ref) as the source of the POWMAN clock when switched-core is powered. The POWMAN clock always switches to the slow clock (lposc) when switched-core is powered down because the fast clock stops running. - 0 always run the POWMAN clock from the slow clock (lposc) - 1 run the POWMAN clock from the fast clock when available - This setting takes effect when a power up sequence is next run - [12:12] - read-write - - - RUN_LPOSC_IN_LP - Set to 0 to stop the low power osc when the switched-core is powered down, which is unwise if using it to clock the timer - This setting takes effect when the swcore is next powered down - [8:8] - read-write - - - USE_BOD_HP - Set to 0 to prevent automatic switching to bod high power mode when switched-core is powered up - This setting takes effect when the swcore is next powered up - [7:7] - read-write - - - USE_BOD_LP - Set to 0 to prevent automatic switching to bod low power mode when switched-core is powered down - This setting takes effect when the swcore is next powered down - [6:6] - read-write - - - USE_VREG_HP - Set to 0 to prevent automatic switching to vreg high power mode when switched-core is powered up - This setting takes effect when the swcore is next powered up - [5:5] - read-write - - - USE_VREG_LP - Set to 0 to prevent automatic switching to vreg low power mode when switched-core is powered down - This setting takes effect when the swcore is next powered down - [4:4] - read-write - - - HW_PWRUP_SRAM0 - Specifies the power state of SRAM0 when powering up swcore from a low power state (P1.xxx) to a high power state (P0.0xx). - 0=power-up - 1=no change - [1:1] - read-write - - - HW_PWRUP_SRAM1 - Specifies the power state of SRAM1 when powering up swcore from a low power state (P1.xxx) to a high power state (P0.0xx). - 0=power-up - 1=no change - [0:0] - read-write - - - - - STATE - 0x00000038 - This register controls the power state of the 4 power domains. - The current power state is indicated in POWMAN_STATE_CURRENT which is read-only. - To change the state, write to POWMAN_STATE_REQ. - The coding of POWMAN_STATE_CURRENT & POWMAN_STATE_REQ corresponds to the power states - defined in the datasheet: - bit 3 = SWCORE - bit 2 = XIP cache - bit 1 = SRAM0 - bit 0 = SRAM1 - 0 = powered up - 1 = powered down - When POWMAN_STATE_REQ is written, the POWMAN_STATE_WAITING flag is set while the Power Manager determines what is required. If an invalid transition is requested the Power Manager will still register the request in POWMAN_STATE_REQ but will also set the POWMAN_BAD_REQ flag. It will then implement the power-up requests and ignore the power down requests. To do nothing would risk entering an unrecoverable lock-up state. Invalid requests are: any combination of power up and power down requests any request that results in swcore boing powered and xip unpowered If the request is to power down the switched-core domain then POWMAN_STATE_WAITING stays active until the processors halt. During this time the POWMAN_STATE_REQ field can be re-written to change or cancel the request. When the power state transition begins the POWMAN_STATE_WAITING_flag is cleared, the POWMAN_STATE_CHANGING flag is set and POWMAN register writes are ignored until the transition completes. - 0x0000000f - - - CHANGING - [13:13] - read-only - - - WAITING - [12:12] - read-only - - - BAD_HW_REQ - Bad hardware initiated state request. Went back to state 0 (i.e. everything powered up) - [11:11] - read-only - - - BAD_SW_REQ - Bad software initiated state request. No action taken. - [10:10] - read-only - - - PWRUP_WHILE_WAITING - Request ignored because of a pending pwrup request. See current_pwrup_req. Note this blocks powering up AND powering down. - [9:9] - read-write - oneToClear - - - REQ_IGNORED - [8:8] - read-write - oneToClear - - - REQ - [7:4] - read-write - - - CURRENT - [3:0] - read-only - - - - - POW_FASTDIV - 0x0000003c - 0x00000040 - - - POW_FASTDIV - divides the POWMAN clock to provide a tick for the delay module and state machines - when clk_pow is running from the slow clock it is not divided - when clk_pow is running from the fast clock it is divided by tick_div - [10:0] - read-write - - - - - POW_DELAY - 0x00000040 - power state machine delays - 0x00002011 - - - SRAM_STEP - timing between the sram0 and sram1 power state machine steps - measured in units of the powman tick period (>=1us), 0 gives a delay of 1 unit - [15:8] - read-write - - - XIP_STEP - timing between the xip power state machine steps - measured in units of the lposc period, 0 gives a delay of 1 unit - [7:4] - read-write - - - SWCORE_STEP - timing between the swcore power state machine steps - measured in units of the lposc period, 0 gives a delay of 1 unit - [3:0] - read-write - - - - - EXT_CTRL0 - 0x00000044 - Configures a gpio as a power mode aware control output - 0x0000003f - - - LP_EXIT_STATE - output level when exiting the low power state - [14:14] - read-write - - - LP_ENTRY_STATE - output level when entering the low power state - [13:13] - read-write - - - INIT_STATE - [12:12] - read-write - - - INIT - [8:8] - read-write - - - GPIO_SELECT - selects from gpio 0->30 - set to 31 to disable this feature - [5:0] - read-write - - - - - EXT_CTRL1 - 0x00000048 - Configures a gpio as a power mode aware control output - 0x0000003f - - - LP_EXIT_STATE - output level when exiting the low power state - [14:14] - read-write - - - LP_ENTRY_STATE - output level when entering the low power state - [13:13] - read-write - - - INIT_STATE - [12:12] - read-write - - - INIT - [8:8] - read-write - - - GPIO_SELECT - selects from gpio 0->30 - set to 31 to disable this feature - [5:0] - read-write - - - - - EXT_TIME_REF - 0x0000004c - Select a GPIO to use as a time reference, the source can be used to drive the low power clock at 32kHz, or to provide a 1ms tick to the timer, or provide a 1Hz tick to the timer. The tick selection is controlled by the POWMAN_TIMER register. - 0x00000000 - - - DRIVE_LPCK - Use the selected GPIO to drive the 32kHz low power clock, in place of LPOSC. This field must only be written when POWMAN_TIMER_RUN=0 - [4:4] - read-write - - - SOURCE_SEL - 0 -> gpio12 - 1 -> gpio20 - 2 -> gpio14 - 3 -> gpio22 - [1:0] - read-write - - - - - LPOSC_FREQ_KHZ_INT - 0x00000050 - Informs the AON Timer of the integer component of the clock frequency when running off the LPOSC. - 0x00000020 - - - LPOSC_FREQ_KHZ_INT - Integer component of the LPOSC or GPIO clock source frequency in kHz. Default = 32 This field must only be written when POWMAN_TIMER_RUN=0 or POWMAN_TIMER_USING_XOSC=1 - [5:0] - read-write - - - - - LPOSC_FREQ_KHZ_FRAC - 0x00000054 - Informs the AON Timer of the fractional component of the clock frequency when running off the LPOSC. - 0x0000c49c - - - LPOSC_FREQ_KHZ_FRAC - Fractional component of the LPOSC or GPIO clock source frequency in kHz. Default = 0.768 This field must only be written when POWMAN_TIMER_RUN=0 or POWMAN_TIMER_USING_XOSC=1 - [15:0] - read-write - - - - - XOSC_FREQ_KHZ_INT - 0x00000058 - Informs the AON Timer of the integer component of the clock frequency when running off the XOSC. - 0x00002ee0 - - - XOSC_FREQ_KHZ_INT - Integer component of the XOSC frequency in kHz. Default = 12000 Must be >1 This field must only be written when POWMAN_TIMER_RUN=0 or POWMAN_TIMER_USING_XOSC=0 - [15:0] - read-write - - - - - XOSC_FREQ_KHZ_FRAC - 0x0000005c - Informs the AON Timer of the fractional component of the clock frequency when running off the XOSC. - 0x00000000 - - - XOSC_FREQ_KHZ_FRAC - Fractional component of the XOSC frequency in kHz. This field must only be written when POWMAN_TIMER_RUN=0 or POWMAN_TIMER_USING_XOSC=0 - [15:0] - read-write - - - - - SET_TIME_63TO48 - 0x00000060 - 0x00000000 - - - SET_TIME_63TO48 - For setting the time, do not use for reading the time, use POWMAN_READ_TIME_UPPER and POWMAN_READ_TIME_LOWER. This field must only be written when POWMAN_TIMER_RUN=0 - [15:0] - read-write - - - - - SET_TIME_47TO32 - 0x00000064 - 0x00000000 - - - SET_TIME_47TO32 - For setting the time, do not use for reading the time, use POWMAN_READ_TIME_UPPER and POWMAN_READ_TIME_LOWER. This field must only be written when POWMAN_TIMER_RUN=0 - [15:0] - read-write - - - - - SET_TIME_31TO16 - 0x00000068 - 0x00000000 - - - SET_TIME_31TO16 - For setting the time, do not use for reading the time, use POWMAN_READ_TIME_UPPER and POWMAN_READ_TIME_LOWER. This field must only be written when POWMAN_TIMER_RUN=0 - [15:0] - read-write - - - - - SET_TIME_15TO0 - 0x0000006c - 0x00000000 - - - SET_TIME_15TO0 - For setting the time, do not use for reading the time, use POWMAN_READ_TIME_UPPER and POWMAN_READ_TIME_LOWER. This field must only be written when POWMAN_TIMER_RUN=0 - [15:0] - read-write - - - - - READ_TIME_UPPER - 0x00000070 - 0x00000000 - - - READ_TIME_UPPER - For reading bits 63:32 of the timer. When reading all 64 bits it is possible for the LOWER count to rollover during the read. It is recommended to read UPPER, then LOWER, then re-read UPPER and, if it has changed, re-read LOWER. - [31:0] - read-only - - - - - READ_TIME_LOWER - 0x00000074 - 0x00000000 - - - READ_TIME_LOWER - For reading bits 31:0 of the timer. - [31:0] - read-only - - - - - ALARM_TIME_63TO48 - 0x00000078 - 0x00000000 - - - ALARM_TIME_63TO48 - This field must only be written when POWMAN_ALARM_ENAB=0 - [15:0] - read-write - - - - - ALARM_TIME_47TO32 - 0x0000007c - 0x00000000 - - - ALARM_TIME_47TO32 - This field must only be written when POWMAN_ALARM_ENAB=0 - [15:0] - read-write - - - - - ALARM_TIME_31TO16 - 0x00000080 - 0x00000000 - - - ALARM_TIME_31TO16 - This field must only be written when POWMAN_ALARM_ENAB=0 - [15:0] - read-write - - - - - ALARM_TIME_15TO0 - 0x00000084 - 0x00000000 - - - ALARM_TIME_15TO0 - This field must only be written when POWMAN_ALARM_ENAB=0 - [15:0] - read-write - - - - - TIMER - 0x00000088 - 0x00000000 - - - USING_GPIO_1HZ - Timer is synchronised to a 1hz gpio source - [19:19] - read-only - - - USING_GPIO_1KHZ - Timer is running from a 1khz gpio source - [18:18] - read-only - - - USING_LPOSC - Timer is running from lposc - [17:17] - read-only - - - USING_XOSC - Timer is running from xosc - [16:16] - read-only - - - USE_GPIO_1HZ - Selects the gpio source as the reference for the sec counter. The msec counter will continue to use the lposc or xosc reference. - [13:13] - read-write - - - USE_GPIO_1KHZ - switch to gpio as the source of the 1kHz timer tick - [10:10] - write-only - - - USE_XOSC - switch to xosc as the source of the 1kHz timer tick - [9:9] - write-only - - - USE_LPOSC - Switch to lposc as the source of the 1kHz timer tick - [8:8] - write-only - - - ALARM - Alarm has fired. Write to 1 to clear the alarm. - [6:6] - read-write - oneToClear - - - PWRUP_ON_ALARM - Alarm wakes the chip from low power mode - [5:5] - read-write - - - ALARM_ENAB - Enables the alarm. The alarm must be disabled while writing the alarm time. - [4:4] - read-write - - - CLEAR - Clears the timer, does not disable the timer and does not affect the alarm. This control can be written at any time. - [2:2] - write-only - - - RUN - Timer enable. Setting this bit causes the timer to begin counting up from its current value. Clearing this bit stops the timer from counting. - - Before enabling the timer, set the POWMAN_LPOSC_FREQ* and POWMAN_XOSC_FREQ* registers to configure the count rate, and initialise the current time by writing to SET_TIME_63TO48 through SET_TIME_15TO0. You must not write to the SET_TIME_x registers when the timer is running. - - Once configured, start the timer by setting POWMAN_TIMER_RUN=1. This will start the timer running from the LPOSC. When the XOSC is available switch the reference clock to XOSC then select it as the timer clock by setting POWMAN_TIMER_USE_XOSC=1 - [1:1] - read-write - - - NONSEC_WRITE - Control whether Non-secure software can write to the timer registers. All other registers are hardwired to be inaccessible to Non-secure. - [0:0] - read-write - - - - - PWRUP0 - 0x0000008c - 4 GPIO powerup events can be configured to wake the chip up from a low power state. - The pwrups are level/edge sensitive and can be set to trigger on a high/rising or low/falling event - The number of gpios available depends on the package option. An invalid selection will be ignored - source = 0 selects gpio0 - . - . - source = 47 selects gpio47 - source = 48 selects qspi_ss - source = 49 selects qspi_sd0 - source = 50 selects qspi_sd1 - source = 51 selects qspi_sd2 - source = 52 selects qspi_sd3 - source = 53 selects qspi_sclk - level = 0 triggers the pwrup when the source is low - level = 1 triggers the pwrup when the source is high - 0x0000003f - - - RAW_STATUS - Value of selected gpio pin (only if enable == 1) - [10:10] - read-only - - - STATUS - Status of gpio wakeup. Write to 1 to clear a latched edge detect. - [9:9] - read-write - oneToClear - - - MODE - Edge or level detect. Edge will detect a 0 to 1 transition (or 1 to 0 transition). Level will detect a 1 or 0. Both types of event get latched into the current_pwrup_req register. - [8:8] - read-write - - - level - 0 - - - edge - 1 - - - - - DIRECTION - [7:7] - read-write - - - low_falling - 0 - - - high_rising - 1 - - - - - ENABLE - Set to 1 to enable the wakeup source. Set to 0 to disable the wakeup source and clear a pending wakeup event. - If using edge detect a latched edge needs to be cleared by writing 1 to the status register also. - [6:6] - read-write - - - SOURCE - [5:0] - read-write - - - - - PWRUP1 - 0x00000090 - 4 GPIO powerup events can be configured to wake the chip up from a low power state. - The pwrups are level/edge sensitive and can be set to trigger on a high/rising or low/falling event - The number of gpios available depends on the package option. An invalid selection will be ignored - source = 0 selects gpio0 - . - . - source = 47 selects gpio47 - source = 48 selects qspi_ss - source = 49 selects qspi_sd0 - source = 50 selects qspi_sd1 - source = 51 selects qspi_sd2 - source = 52 selects qspi_sd3 - source = 53 selects qspi_sclk - level = 0 triggers the pwrup when the source is low - level = 1 triggers the pwrup when the source is high - 0x0000003f - - - RAW_STATUS - Value of selected gpio pin (only if enable == 1) - [10:10] - read-only - - - STATUS - Status of gpio wakeup. Write to 1 to clear a latched edge detect. - [9:9] - read-write - oneToClear - - - MODE - Edge or level detect. Edge will detect a 0 to 1 transition (or 1 to 0 transition). Level will detect a 1 or 0. Both types of event get latched into the current_pwrup_req register. - [8:8] - read-write - - - level - 0 - - - edge - 1 - - - - - DIRECTION - [7:7] - read-write - - - low_falling - 0 - - - high_rising - 1 - - - - - ENABLE - Set to 1 to enable the wakeup source. Set to 0 to disable the wakeup source and clear a pending wakeup event. - If using edge detect a latched edge needs to be cleared by writing 1 to the status register also. - [6:6] - read-write - - - SOURCE - [5:0] - read-write - - - - - PWRUP2 - 0x00000094 - 4 GPIO powerup events can be configured to wake the chip up from a low power state. - The pwrups are level/edge sensitive and can be set to trigger on a high/rising or low/falling event - The number of gpios available depends on the package option. An invalid selection will be ignored - source = 0 selects gpio0 - . - . - source = 47 selects gpio47 - source = 48 selects qspi_ss - source = 49 selects qspi_sd0 - source = 50 selects qspi_sd1 - source = 51 selects qspi_sd2 - source = 52 selects qspi_sd3 - source = 53 selects qspi_sclk - level = 0 triggers the pwrup when the source is low - level = 1 triggers the pwrup when the source is high - 0x0000003f - - - RAW_STATUS - Value of selected gpio pin (only if enable == 1) - [10:10] - read-only - - - STATUS - Status of gpio wakeup. Write to 1 to clear a latched edge detect. - [9:9] - read-write - oneToClear - - - MODE - Edge or level detect. Edge will detect a 0 to 1 transition (or 1 to 0 transition). Level will detect a 1 or 0. Both types of event get latched into the current_pwrup_req register. - [8:8] - read-write - - - level - 0 - - - edge - 1 - - - - - DIRECTION - [7:7] - read-write - - - low_falling - 0 - - - high_rising - 1 - - - - - ENABLE - Set to 1 to enable the wakeup source. Set to 0 to disable the wakeup source and clear a pending wakeup event. - If using edge detect a latched edge needs to be cleared by writing 1 to the status register also. - [6:6] - read-write - - - SOURCE - [5:0] - read-write - - - - - PWRUP3 - 0x00000098 - 4 GPIO powerup events can be configured to wake the chip up from a low power state. - The pwrups are level/edge sensitive and can be set to trigger on a high/rising or low/falling event - The number of gpios available depends on the package option. An invalid selection will be ignored - source = 0 selects gpio0 - . - . - source = 47 selects gpio47 - source = 48 selects qspi_ss - source = 49 selects qspi_sd0 - source = 50 selects qspi_sd1 - source = 51 selects qspi_sd2 - source = 52 selects qspi_sd3 - source = 53 selects qspi_sclk - level = 0 triggers the pwrup when the source is low - level = 1 triggers the pwrup when the source is high - 0x0000003f - - - RAW_STATUS - Value of selected gpio pin (only if enable == 1) - [10:10] - read-only - - - STATUS - Status of gpio wakeup. Write to 1 to clear a latched edge detect. - [9:9] - read-write - oneToClear - - - MODE - Edge or level detect. Edge will detect a 0 to 1 transition (or 1 to 0 transition). Level will detect a 1 or 0. Both types of event get latched into the current_pwrup_req register. - [8:8] - read-write - - - level - 0 - - - edge - 1 - - - - - DIRECTION - [7:7] - read-write - - - low_falling - 0 - - - high_rising - 1 - - - - - ENABLE - Set to 1 to enable the wakeup source. Set to 0 to disable the wakeup source and clear a pending wakeup event. - If using edge detect a latched edge needs to be cleared by writing 1 to the status register also. - [6:6] - read-write - - - SOURCE - [5:0] - read-write - - - - - CURRENT_PWRUP_REQ - 0x0000009c - Indicates current powerup request state - pwrup events can be cleared by removing the enable from the pwrup register. The alarm pwrup req can be cleared by clearing timer.alarm_enab - 0 = chip reset, for the source of the last reset see POWMAN_CHIP_RESET - 1 = pwrup0 - 2 = pwrup1 - 3 = pwrup2 - 4 = pwrup3 - 5 = coresight_pwrup - 6 = alarm_pwrup - 0x00000000 - - - CURRENT_PWRUP_REQ - [6:0] - read-only - - - - - LAST_SWCORE_PWRUP - 0x000000a0 - Indicates which pwrup source triggered the last switched-core power up - 0 = chip reset, for the source of the last reset see POWMAN_CHIP_RESET - 1 = pwrup0 - 2 = pwrup1 - 3 = pwrup2 - 4 = pwrup3 - 5 = coresight_pwrup - 6 = alarm_pwrup - 0x00000000 - - - LAST_SWCORE_PWRUP - [6:0] - read-only - - - - - DBG_PWRCFG - 0x000000a4 - 0x00000000 - - - IGNORE - Ignore pwrup req from debugger. If pwrup req is asserted then this will prevent power down and set powerdown blocked. Set ignore to stop paying attention to pwrup_req - [0:0] - read-write - - - - - BOOTDIS - 0x000000a8 - Tell the bootrom to ignore the BOOT0..3 registers following the next RSM reset (e.g. the next core power down/up). - - If an early boot stage has soft-locked some OTP pages in order to protect their contents from later stages, there is a risk that Secure code running at a later stage can unlock the pages by powering the core up and down. - - This register can be used to ensure that the bootloader runs as normal on the next power up, preventing Secure code at a later stage from accessing OTP in its unlocked state. - - Should be used in conjunction with the OTP BOOTDIS register. - 0x00000000 - - - NEXT - This flag always ORs writes into its current contents. It can be set but not cleared by software. - - The BOOTDIS_NEXT bit is OR'd into the BOOTDIS_NOW bit when the core is powered down. Simultaneously, the BOOTDIS_NEXT bit is cleared. Setting this bit means that the BOOT0..3 registers will be ignored following the next reset of the RSM by powman. - - This flag should be set by an early boot stage that has soft-locked OTP pages, to prevent later stages from unlocking it by power cycling. - [1:1] - read-write - - - NOW - When powman resets the RSM, the current value of BOOTDIS_NEXT is OR'd into BOOTDIS_NOW, and BOOTDIS_NEXT is cleared. - - The bootrom checks this flag before reading the BOOT0..3 registers. If it is set, the bootrom clears it, and ignores the BOOT registers. This prevents Secure software from diverting the boot path before a bootloader has had the chance to soft lock OTP pages containing sensitive data. - [0:0] - read-write - oneToClear - - - - - DBGCONFIG - 0x000000ac - 0x00000000 - - - DP_INSTID - Configure DP instance ID for SWD multidrop selection. - Recommend that this is NOT changed until you require debug access in multi-chip environment - [3:0] - read-write - - - - - SCRATCH0 - 0x000000b0 - Scratch register. Information persists in low power mode - 0x00000000 - - - SCRATCH0 - [31:0] - read-write - - - - - SCRATCH1 - 0x000000b4 - Scratch register. Information persists in low power mode - 0x00000000 - - - SCRATCH1 - [31:0] - read-write - - - - - SCRATCH2 - 0x000000b8 - Scratch register. Information persists in low power mode - 0x00000000 - - - SCRATCH2 - [31:0] - read-write - - - - - SCRATCH3 - 0x000000bc - Scratch register. Information persists in low power mode - 0x00000000 - - - SCRATCH3 - [31:0] - read-write - - - - - SCRATCH4 - 0x000000c0 - Scratch register. Information persists in low power mode - 0x00000000 - - - SCRATCH4 - [31:0] - read-write - - - - - SCRATCH5 - 0x000000c4 - Scratch register. Information persists in low power mode - 0x00000000 - - - SCRATCH5 - [31:0] - read-write - - - - - SCRATCH6 - 0x000000c8 - Scratch register. Information persists in low power mode - 0x00000000 - - - SCRATCH6 - [31:0] - read-write - - - - - SCRATCH7 - 0x000000cc - Scratch register. Information persists in low power mode - 0x00000000 - - - SCRATCH7 - [31:0] - read-write - - - - - BOOT0 - 0x000000d0 - Scratch register. Information persists in low power mode - 0x00000000 - - - BOOT0 - [31:0] - read-write - - - - - BOOT1 - 0x000000d4 - Scratch register. Information persists in low power mode - 0x00000000 - - - BOOT1 - [31:0] - read-write - - - - - BOOT2 - 0x000000d8 - Scratch register. Information persists in low power mode - 0x00000000 - - - BOOT2 - [31:0] - read-write - - - - - BOOT3 - 0x000000dc - Scratch register. Information persists in low power mode - 0x00000000 - - - BOOT3 - [31:0] - read-write - - - - - INTR - 0x000000e0 - Raw Interrupts - 0x00000000 - - - PWRUP_WHILE_WAITING - Source is state.pwrup_while_waiting - [3:3] - read-only - - - STATE_REQ_IGNORED - Source is state.req_ignored - [2:2] - read-only - - - TIMER - [1:1] - read-only - - - VREG_OUTPUT_LOW - [0:0] - read-write - oneToClear - - - - - INTE - 0x000000e4 - Interrupt Enable - 0x00000000 - - - PWRUP_WHILE_WAITING - Source is state.pwrup_while_waiting - [3:3] - read-write - - - STATE_REQ_IGNORED - Source is state.req_ignored - [2:2] - read-write - - - TIMER - [1:1] - read-write - - - VREG_OUTPUT_LOW - [0:0] - read-write - - - - - INTF - 0x000000e8 - Interrupt Force - 0x00000000 - - - PWRUP_WHILE_WAITING - Source is state.pwrup_while_waiting - [3:3] - read-write - - - STATE_REQ_IGNORED - Source is state.req_ignored - [2:2] - read-write - - - TIMER - [1:1] - read-write - - - VREG_OUTPUT_LOW - [0:0] - read-write - - - - - INTS - 0x000000ec - Interrupt status after masking & forcing - 0x00000000 - - - PWRUP_WHILE_WAITING - Source is state.pwrup_while_waiting - [3:3] - read-only - - - STATE_REQ_IGNORED - Source is state.req_ignored - [2:2] - read-only - - - TIMER - [1:1] - read-only - - - VREG_OUTPUT_LOW - [0:0] - read-only - - - - - - - WATCHDOG - 0x400d8000 - - 0 - 44 - registers - - - - CTRL - 0x00000000 - Watchdog control - The rst_wdsel register determines which subsystems are reset when the watchdog is triggered. - The watchdog can be triggered in software. - 0x07000000 - - - TRIGGER - Trigger a watchdog reset - [31:31] - write-only - - - ENABLE - When not enabled the watchdog timer is paused - [30:30] - read-write - - - PAUSE_DBG1 - Pause the watchdog timer when processor 1 is in debug mode - [26:26] - read-write - - - PAUSE_DBG0 - Pause the watchdog timer when processor 0 is in debug mode - [25:25] - read-write - - - PAUSE_JTAG - Pause the watchdog timer when JTAG is accessing the bus fabric - [24:24] - read-write - - - TIME - Indicates the time in usec before a watchdog reset will be triggered - [23:0] - read-only - - - - - LOAD - 0x00000004 - Load the watchdog timer. The maximum setting is 0xffffff which corresponds to approximately 16 seconds. - 0x00000000 - - - LOAD - [23:0] - write-only - - - - - REASON - 0x00000008 - Logs the reason for the last reset. Both bits are zero for the case of a hardware reset. - - Additionally, as of RP2350, a debugger warm reset of either core (SYSRESETREQ or hartreset) will also clear the watchdog reason register, so that software loaded under the debugger following a watchdog timeout will not continue to see the timeout condition. - 0x00000000 - - - FORCE - [1:1] - read-only - - - TIMER - [0:0] - read-only - - - - - SCRATCH0 - 0x0000000c - Scratch register. Information persists through soft reset of the chip. - 0x00000000 - - - SCRATCH0 - [31:0] - read-write - - - - - SCRATCH1 - 0x00000010 - Scratch register. Information persists through soft reset of the chip. - 0x00000000 - - - SCRATCH1 - [31:0] - read-write - - - - - SCRATCH2 - 0x00000014 - Scratch register. Information persists through soft reset of the chip. - 0x00000000 - - - SCRATCH2 - [31:0] - read-write - - - - - SCRATCH3 - 0x00000018 - Scratch register. Information persists through soft reset of the chip. - 0x00000000 - - - SCRATCH3 - [31:0] - read-write - - - - - SCRATCH4 - 0x0000001c - Scratch register. Information persists through soft reset of the chip. - 0x00000000 - - - SCRATCH4 - [31:0] - read-write - - - - - SCRATCH5 - 0x00000020 - Scratch register. Information persists through soft reset of the chip. - 0x00000000 - - - SCRATCH5 - [31:0] - read-write - - - - - SCRATCH6 - 0x00000024 - Scratch register. Information persists through soft reset of the chip. - 0x00000000 - - - SCRATCH6 - [31:0] - read-write - - - - - SCRATCH7 - 0x00000028 - Scratch register. Information persists through soft reset of the chip. - 0x00000000 - - - SCRATCH7 - [31:0] - read-write - - - - - - - DMA - DMA with separate read and write masters - 0x50000000 - - 0 - 3016 - registers - - - DMA_IRQ_0 - 10 - - - DMA_IRQ_1 - 11 - - - DMA_IRQ_2 - 12 - - - DMA_IRQ_3 - 13 - - - - CH0_READ_ADDR - 0x00000000 - DMA Channel 0 Read Address pointer - 0x00000000 - - - CH0_READ_ADDR - This register updates automatically each time a read completes. The current value is the next address to be read by this channel. - [31:0] - read-write - - - - - CH0_WRITE_ADDR - 0x00000004 - DMA Channel 0 Write Address pointer - 0x00000000 - - - CH0_WRITE_ADDR - This register updates automatically each time a write completes. The current value is the next address to be written by this channel. - [31:0] - read-write - - - - - CH0_TRANS_COUNT - 0x00000008 - DMA Channel 0 Transfer Count - 0x00000000 - - - MODE - When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. - - When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. - - When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. - - All other values are reserved. - [31:28] - read-write - - - NORMAL - 0 - - - TRIGGER_SELF - 1 - - - ENDLESS - 15 - - - - - COUNT - 28-bit transfer count (256 million transfers maximum). - - Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). - - When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. - - Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. - - The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. - [27:0] - read-write - - - - - CH0_CTRL_TRIG - 0x0000000c - DMA Channel 0 Control and Status - 0x00000000 - - - AHB_ERROR - Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. - [31:31] - read-only - - - READ_ERROR - If 1, the channel received a read bus error. Write one to clear. - READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) - [30:30] - read-write - oneToClear - - - WRITE_ERROR - If 1, the channel received a write bus error. Write one to clear. - WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) - [29:29] - read-write - oneToClear - - - BUSY - This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. - - To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. - [26:26] - read-only - - - SNIFF_EN - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. - - This allows checksum to be enabled or disabled on a per-control- block basis. - [25:25] - read-write - - - BSWAP - Apply byte-swap transformation to DMA data. - For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. - [24:24] - read-write - - - IRQ_QUIET - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. - - This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. - [23:23] - read-write - - - TREQ_SEL - Select a Transfer Request signal. - The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). - 0x0 to 0x3a -> select DREQ n as TREQ - [22:17] - read-write - - - PIO0_TX0 - 0 - Select PIO0's TX FIFO 0 as TREQ - - - PIO0_TX1 - 1 - Select PIO0's TX FIFO 1 as TREQ - - - PIO0_TX2 - 2 - Select PIO0's TX FIFO 2 as TREQ - - - PIO0_TX3 - 3 - Select PIO0's TX FIFO 3 as TREQ - - - PIO0_RX0 - 4 - Select PIO0's RX FIFO 0 as TREQ - - - PIO0_RX1 - 5 - Select PIO0's RX FIFO 1 as TREQ - - - PIO0_RX2 - 6 - Select PIO0's RX FIFO 2 as TREQ - - - PIO0_RX3 - 7 - Select PIO0's RX FIFO 3 as TREQ - - - PIO1_TX0 - 8 - Select PIO1's TX FIFO 0 as TREQ - - - PIO1_TX1 - 9 - Select PIO1's TX FIFO 1 as TREQ - - - PIO1_TX2 - 10 - Select PIO1's TX FIFO 2 as TREQ - - - PIO1_TX3 - 11 - Select PIO1's TX FIFO 3 as TREQ - - - PIO1_RX0 - 12 - Select PIO1's RX FIFO 0 as TREQ - - - PIO1_RX1 - 13 - Select PIO1's RX FIFO 1 as TREQ - - - PIO1_RX2 - 14 - Select PIO1's RX FIFO 2 as TREQ - - - PIO1_RX3 - 15 - Select PIO1's RX FIFO 3 as TREQ - - - PIO2_TX0 - 16 - Select PIO2's TX FIFO 0 as TREQ - - - PIO2_TX1 - 17 - Select PIO2's TX FIFO 1 as TREQ - - - PIO2_TX2 - 18 - Select PIO2's TX FIFO 2 as TREQ - - - PIO2_TX3 - 19 - Select PIO2's TX FIFO 3 as TREQ - - - PIO2_RX0 - 20 - Select PIO2's RX FIFO 0 as TREQ - - - PIO2_RX1 - 21 - Select PIO2's RX FIFO 1 as TREQ - - - PIO2_RX2 - 22 - Select PIO2's RX FIFO 2 as TREQ - - - PIO2_RX3 - 23 - Select PIO2's RX FIFO 3 as TREQ - - - SPI0_TX - 24 - Select SPI0's TX FIFO as TREQ - - - SPI0_RX - 25 - Select SPI0's RX FIFO as TREQ - - - SPI1_TX - 26 - Select SPI1's TX FIFO as TREQ - - - SPI1_RX - 27 - Select SPI1's RX FIFO as TREQ - - - UART0_TX - 28 - Select UART0's TX FIFO as TREQ - - - UART0_RX - 29 - Select UART0's RX FIFO as TREQ - - - UART1_TX - 30 - Select UART1's TX FIFO as TREQ - - - UART1_RX - 31 - Select UART1's RX FIFO as TREQ - - - PWM_WRAP0 - 32 - Select PWM Counter 0's Wrap Value as TREQ - - - PWM_WRAP1 - 33 - Select PWM Counter 1's Wrap Value as TREQ - - - PWM_WRAP2 - 34 - Select PWM Counter 2's Wrap Value as TREQ - - - PWM_WRAP3 - 35 - Select PWM Counter 3's Wrap Value as TREQ - - - PWM_WRAP4 - 36 - Select PWM Counter 4's Wrap Value as TREQ - - - PWM_WRAP5 - 37 - Select PWM Counter 5's Wrap Value as TREQ - - - PWM_WRAP6 - 38 - Select PWM Counter 6's Wrap Value as TREQ - - - PWM_WRAP7 - 39 - Select PWM Counter 7's Wrap Value as TREQ - - - PWM_WRAP8 - 40 - Select PWM Counter 8's Wrap Value as TREQ - - - PWM_WRAP9 - 41 - Select PWM Counter 9's Wrap Value as TREQ - - - PWM_WRAP10 - 42 - Select PWM Counter 0's Wrap Value as TREQ - - - PWM_WRAP11 - 43 - Select PWM Counter 1's Wrap Value as TREQ - - - I2C0_TX - 44 - Select I2C0's TX FIFO as TREQ - - - I2C0_RX - 45 - Select I2C0's RX FIFO as TREQ - - - I2C1_TX - 46 - Select I2C1's TX FIFO as TREQ - - - I2C1_RX - 47 - Select I2C1's RX FIFO as TREQ - - - ADC - 48 - Select the ADC as TREQ - - - XIP_STREAM - 49 - Select the XIP Streaming FIFO as TREQ - - - XIP_QMITX - 50 - Select XIP_QMITX as TREQ - - - XIP_QMIRX - 51 - Select XIP_QMIRX as TREQ - - - HSTX - 52 - Select HSTX as TREQ - - - CORESIGHT - 53 - Select CORESIGHT as TREQ - - - SHA256 - 54 - Select SHA256 as TREQ - - - TIMER0 - 59 - Select Timer 0 as TREQ - - - TIMER1 - 60 - Select Timer 1 as TREQ - - - TIMER2 - 61 - Select Timer 2 as TREQ (Optional) - - - TIMER3 - 62 - Select Timer 3 as TREQ (Optional) - - - PERMANENT - 63 - Permanent request, for unpaced transfers. - - - - - CHAIN_TO - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. - - Note this field resets to 0, so channels 1 and above will chain to channel 0 by default. Set this field to avoid this behaviour. - [16:13] - read-write - - - RING_SEL - Select whether RING_SIZE applies to read or write addresses. - If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. - [12:12] - read-write - - - RING_SIZE - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. - - Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. - [11:8] - read-write - - - RING_NONE - 0 - - - - - INCR_WRITE_REV - If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer. - - If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. - [7:7] - read-write - - - INCR_WRITE - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. - - Generally this should be disabled for memory-to-peripheral transfers. - [6:6] - read-write - - - INCR_READ_REV - If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer. - - If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. - [5:5] - read-write - - - INCR_READ - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. - - Generally this should be disabled for peripheral-to-memory transfers. - [4:4] - read-write - - - DATA_SIZE - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. - [3:2] - read-write - - - SIZE_BYTE - 0 - - - SIZE_HALFWORD - 1 - - - SIZE_WORD - 2 - - - - - HIGH_PRIORITY - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. - - This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. - [1:1] - read-write - - - EN - DMA Channel Enable. - When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) - [0:0] - read-write - - - - - CH0_AL1_CTRL - 0x00000010 - Alias for channel 0 CTRL register - 0x00000000 - - - CH0_AL1_CTRL - [31:0] - read-write - - - - - CH0_AL1_READ_ADDR - 0x00000014 - Alias for channel 0 READ_ADDR register - 0x00000000 - - - CH0_AL1_READ_ADDR - [31:0] - read-write - - - - - CH0_AL1_WRITE_ADDR - 0x00000018 - Alias for channel 0 WRITE_ADDR register - 0x00000000 - - - CH0_AL1_WRITE_ADDR - [31:0] - read-write - - - - - CH0_AL1_TRANS_COUNT_TRIG - 0x0000001c - Alias for channel 0 TRANS_COUNT register - This is a trigger register (0xc). Writing a nonzero value will - reload the channel counter and start the channel. - 0x00000000 - - - CH0_AL1_TRANS_COUNT_TRIG - [31:0] - read-write - - - - - CH0_AL2_CTRL - 0x00000020 - Alias for channel 0 CTRL register - 0x00000000 - - - CH0_AL2_CTRL - [31:0] - read-write - - - - - CH0_AL2_TRANS_COUNT - 0x00000024 - Alias for channel 0 TRANS_COUNT register - 0x00000000 - - - CH0_AL2_TRANS_COUNT - [31:0] - read-write - - - - - CH0_AL2_READ_ADDR - 0x00000028 - Alias for channel 0 READ_ADDR register - 0x00000000 - - - CH0_AL2_READ_ADDR - [31:0] - read-write - - - - - CH0_AL2_WRITE_ADDR_TRIG - 0x0000002c - Alias for channel 0 WRITE_ADDR register - This is a trigger register (0xc). Writing a nonzero value will - reload the channel counter and start the channel. - 0x00000000 - - - CH0_AL2_WRITE_ADDR_TRIG - [31:0] - read-write - - - - - CH0_AL3_CTRL - 0x00000030 - Alias for channel 0 CTRL register - 0x00000000 - - - CH0_AL3_CTRL - [31:0] - read-write - - - - - CH0_AL3_WRITE_ADDR - 0x00000034 - Alias for channel 0 WRITE_ADDR register - 0x00000000 - - - CH0_AL3_WRITE_ADDR - [31:0] - read-write - - - - - CH0_AL3_TRANS_COUNT - 0x00000038 - Alias for channel 0 TRANS_COUNT register - 0x00000000 - - - CH0_AL3_TRANS_COUNT - [31:0] - read-write - - - - - CH0_AL3_READ_ADDR_TRIG - 0x0000003c - Alias for channel 0 READ_ADDR register - This is a trigger register (0xc). Writing a nonzero value will - reload the channel counter and start the channel. - 0x00000000 - - - CH0_AL3_READ_ADDR_TRIG - [31:0] - read-write - - - - - CH1_READ_ADDR - 0x00000040 - DMA Channel 1 Read Address pointer - 0x00000000 - - - CH1_READ_ADDR - This register updates automatically each time a read completes. The current value is the next address to be read by this channel. - [31:0] - read-write - - - - - CH1_WRITE_ADDR - 0x00000044 - DMA Channel 1 Write Address pointer - 0x00000000 - - - CH1_WRITE_ADDR - This register updates automatically each time a write completes. The current value is the next address to be written by this channel. - [31:0] - read-write - - - - - CH1_TRANS_COUNT - 0x00000048 - DMA Channel 1 Transfer Count - 0x00000000 - - - MODE - When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. - - When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. - - When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. - - All other values are reserved. - [31:28] - read-write - - - NORMAL - 0 - - - TRIGGER_SELF - 1 - - - ENDLESS - 15 - - - - - COUNT - 28-bit transfer count (256 million transfers maximum). - - Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). - - When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. - - Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. - - The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. - [27:0] - read-write - - - - - CH1_CTRL_TRIG - 0x0000004c - DMA Channel 1 Control and Status - 0x00000000 - - - AHB_ERROR - Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. - [31:31] - read-only - - - READ_ERROR - If 1, the channel received a read bus error. Write one to clear. - READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) - [30:30] - read-write - oneToClear - - - WRITE_ERROR - If 1, the channel received a write bus error. Write one to clear. - WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) - [29:29] - read-write - oneToClear - - - BUSY - This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. - - To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. - [26:26] - read-only - - - SNIFF_EN - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. - - This allows checksum to be enabled or disabled on a per-control- block basis. - [25:25] - read-write - - - BSWAP - Apply byte-swap transformation to DMA data. - For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. - [24:24] - read-write - - - IRQ_QUIET - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. - - This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. - [23:23] - read-write - - - TREQ_SEL - Select a Transfer Request signal. - The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). - 0x0 to 0x3a -> select DREQ n as TREQ - [22:17] - read-write - - - PIO0_TX0 - 0 - Select PIO0's TX FIFO 0 as TREQ - - - PIO0_TX1 - 1 - Select PIO0's TX FIFO 1 as TREQ - - - PIO0_TX2 - 2 - Select PIO0's TX FIFO 2 as TREQ - - - PIO0_TX3 - 3 - Select PIO0's TX FIFO 3 as TREQ - - - PIO0_RX0 - 4 - Select PIO0's RX FIFO 0 as TREQ - - - PIO0_RX1 - 5 - Select PIO0's RX FIFO 1 as TREQ - - - PIO0_RX2 - 6 - Select PIO0's RX FIFO 2 as TREQ - - - PIO0_RX3 - 7 - Select PIO0's RX FIFO 3 as TREQ - - - PIO1_TX0 - 8 - Select PIO1's TX FIFO 0 as TREQ - - - PIO1_TX1 - 9 - Select PIO1's TX FIFO 1 as TREQ - - - PIO1_TX2 - 10 - Select PIO1's TX FIFO 2 as TREQ - - - PIO1_TX3 - 11 - Select PIO1's TX FIFO 3 as TREQ - - - PIO1_RX0 - 12 - Select PIO1's RX FIFO 0 as TREQ - - - PIO1_RX1 - 13 - Select PIO1's RX FIFO 1 as TREQ - - - PIO1_RX2 - 14 - Select PIO1's RX FIFO 2 as TREQ - - - PIO1_RX3 - 15 - Select PIO1's RX FIFO 3 as TREQ - - - PIO2_TX0 - 16 - Select PIO2's TX FIFO 0 as TREQ - - - PIO2_TX1 - 17 - Select PIO2's TX FIFO 1 as TREQ - - - PIO2_TX2 - 18 - Select PIO2's TX FIFO 2 as TREQ - - - PIO2_TX3 - 19 - Select PIO2's TX FIFO 3 as TREQ - - - PIO2_RX0 - 20 - Select PIO2's RX FIFO 0 as TREQ - - - PIO2_RX1 - 21 - Select PIO2's RX FIFO 1 as TREQ - - - PIO2_RX2 - 22 - Select PIO2's RX FIFO 2 as TREQ - - - PIO2_RX3 - 23 - Select PIO2's RX FIFO 3 as TREQ - - - SPI0_TX - 24 - Select SPI0's TX FIFO as TREQ - - - SPI0_RX - 25 - Select SPI0's RX FIFO as TREQ - - - SPI1_TX - 26 - Select SPI1's TX FIFO as TREQ - - - SPI1_RX - 27 - Select SPI1's RX FIFO as TREQ - - - UART0_TX - 28 - Select UART0's TX FIFO as TREQ - - - UART0_RX - 29 - Select UART0's RX FIFO as TREQ - - - UART1_TX - 30 - Select UART1's TX FIFO as TREQ - - - UART1_RX - 31 - Select UART1's RX FIFO as TREQ - - - PWM_WRAP0 - 32 - Select PWM Counter 0's Wrap Value as TREQ - - - PWM_WRAP1 - 33 - Select PWM Counter 1's Wrap Value as TREQ - - - PWM_WRAP2 - 34 - Select PWM Counter 2's Wrap Value as TREQ - - - PWM_WRAP3 - 35 - Select PWM Counter 3's Wrap Value as TREQ - - - PWM_WRAP4 - 36 - Select PWM Counter 4's Wrap Value as TREQ - - - PWM_WRAP5 - 37 - Select PWM Counter 5's Wrap Value as TREQ - - - PWM_WRAP6 - 38 - Select PWM Counter 6's Wrap Value as TREQ - - - PWM_WRAP7 - 39 - Select PWM Counter 7's Wrap Value as TREQ - - - PWM_WRAP8 - 40 - Select PWM Counter 8's Wrap Value as TREQ - - - PWM_WRAP9 - 41 - Select PWM Counter 9's Wrap Value as TREQ - - - PWM_WRAP10 - 42 - Select PWM Counter 0's Wrap Value as TREQ - - - PWM_WRAP11 - 43 - Select PWM Counter 1's Wrap Value as TREQ - - - I2C0_TX - 44 - Select I2C0's TX FIFO as TREQ - - - I2C0_RX - 45 - Select I2C0's RX FIFO as TREQ - - - I2C1_TX - 46 - Select I2C1's TX FIFO as TREQ - - - I2C1_RX - 47 - Select I2C1's RX FIFO as TREQ - - - ADC - 48 - Select the ADC as TREQ - - - XIP_STREAM - 49 - Select the XIP Streaming FIFO as TREQ - - - XIP_QMITX - 50 - Select XIP_QMITX as TREQ - - - XIP_QMIRX - 51 - Select XIP_QMIRX as TREQ - - - HSTX - 52 - Select HSTX as TREQ - - - CORESIGHT - 53 - Select CORESIGHT as TREQ - - - SHA256 - 54 - Select SHA256 as TREQ - - - TIMER0 - 59 - Select Timer 0 as TREQ - - - TIMER1 - 60 - Select Timer 1 as TREQ - - - TIMER2 - 61 - Select Timer 2 as TREQ (Optional) - - - TIMER3 - 62 - Select Timer 3 as TREQ (Optional) - - - PERMANENT - 63 - Permanent request, for unpaced transfers. - - - - - CHAIN_TO - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. - - Note this field resets to 0, so channels 1 and above will chain to channel 0 by default. Set this field to avoid this behaviour. - [16:13] - read-write - - - RING_SEL - Select whether RING_SIZE applies to read or write addresses. - If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. - [12:12] - read-write - - - RING_SIZE - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. - - Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. - [11:8] - read-write - - - RING_NONE - 0 - - - - - INCR_WRITE_REV - If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer. - - If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. - [7:7] - read-write - - - INCR_WRITE - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. - - Generally this should be disabled for memory-to-peripheral transfers. - [6:6] - read-write - - - INCR_READ_REV - If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer. - - If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. - [5:5] - read-write - - - INCR_READ - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. - - Generally this should be disabled for peripheral-to-memory transfers. - [4:4] - read-write - - - DATA_SIZE - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. - [3:2] - read-write - - - SIZE_BYTE - 0 - - - SIZE_HALFWORD - 1 - - - SIZE_WORD - 2 - - - - - HIGH_PRIORITY - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. - - This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. - [1:1] - read-write - - - EN - DMA Channel Enable. - When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) - [0:0] - read-write - - - - - CH1_AL1_CTRL - 0x00000050 - Alias for channel 1 CTRL register - 0x00000000 - - - CH1_AL1_CTRL - [31:0] - read-write - - - - - CH1_AL1_READ_ADDR - 0x00000054 - Alias for channel 1 READ_ADDR register - 0x00000000 - - - CH1_AL1_READ_ADDR - [31:0] - read-write - - - - - CH1_AL1_WRITE_ADDR - 0x00000058 - Alias for channel 1 WRITE_ADDR register - 0x00000000 - - - CH1_AL1_WRITE_ADDR - [31:0] - read-write - - - - - CH1_AL1_TRANS_COUNT_TRIG - 0x0000005c - Alias for channel 1 TRANS_COUNT register - This is a trigger register (0xc). Writing a nonzero value will - reload the channel counter and start the channel. - 0x00000000 - - - CH1_AL1_TRANS_COUNT_TRIG - [31:0] - read-write - - - - - CH1_AL2_CTRL - 0x00000060 - Alias for channel 1 CTRL register - 0x00000000 - - - CH1_AL2_CTRL - [31:0] - read-write - - - - - CH1_AL2_TRANS_COUNT - 0x00000064 - Alias for channel 1 TRANS_COUNT register - 0x00000000 - - - CH1_AL2_TRANS_COUNT - [31:0] - read-write - - - - - CH1_AL2_READ_ADDR - 0x00000068 - Alias for channel 1 READ_ADDR register - 0x00000000 - - - CH1_AL2_READ_ADDR - [31:0] - read-write - - - - - CH1_AL2_WRITE_ADDR_TRIG - 0x0000006c - Alias for channel 1 WRITE_ADDR register - This is a trigger register (0xc). Writing a nonzero value will - reload the channel counter and start the channel. - 0x00000000 - - - CH1_AL2_WRITE_ADDR_TRIG - [31:0] - read-write - - - - - CH1_AL3_CTRL - 0x00000070 - Alias for channel 1 CTRL register - 0x00000000 - - - CH1_AL3_CTRL - [31:0] - read-write - - - - - CH1_AL3_WRITE_ADDR - 0x00000074 - Alias for channel 1 WRITE_ADDR register - 0x00000000 - - - CH1_AL3_WRITE_ADDR - [31:0] - read-write - - - - - CH1_AL3_TRANS_COUNT - 0x00000078 - Alias for channel 1 TRANS_COUNT register - 0x00000000 - - - CH1_AL3_TRANS_COUNT - [31:0] - read-write - - - - - CH1_AL3_READ_ADDR_TRIG - 0x0000007c - Alias for channel 1 READ_ADDR register - This is a trigger register (0xc). Writing a nonzero value will - reload the channel counter and start the channel. - 0x00000000 - - - CH1_AL3_READ_ADDR_TRIG - [31:0] - read-write - - - - - CH2_READ_ADDR - 0x00000080 - DMA Channel 2 Read Address pointer - 0x00000000 - - - CH2_READ_ADDR - This register updates automatically each time a read completes. The current value is the next address to be read by this channel. - [31:0] - read-write - - - - - CH2_WRITE_ADDR - 0x00000084 - DMA Channel 2 Write Address pointer - 0x00000000 - - - CH2_WRITE_ADDR - This register updates automatically each time a write completes. The current value is the next address to be written by this channel. - [31:0] - read-write - - - - - CH2_TRANS_COUNT - 0x00000088 - DMA Channel 2 Transfer Count - 0x00000000 - - - MODE - When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. - - When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. - - When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. - - All other values are reserved. - [31:28] - read-write - - - NORMAL - 0 - - - TRIGGER_SELF - 1 - - - ENDLESS - 15 - - - - - COUNT - 28-bit transfer count (256 million transfers maximum). - - Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). - - When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. - - Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. - - The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. - [27:0] - read-write - - - - - CH2_CTRL_TRIG - 0x0000008c - DMA Channel 2 Control and Status - 0x00000000 - - - AHB_ERROR - Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. - [31:31] - read-only - - - READ_ERROR - If 1, the channel received a read bus error. Write one to clear. - READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) - [30:30] - read-write - oneToClear - - - WRITE_ERROR - If 1, the channel received a write bus error. Write one to clear. - WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) - [29:29] - read-write - oneToClear - - - BUSY - This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. - - To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. - [26:26] - read-only - - - SNIFF_EN - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. - - This allows checksum to be enabled or disabled on a per-control- block basis. - [25:25] - read-write - - - BSWAP - Apply byte-swap transformation to DMA data. - For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. - [24:24] - read-write - - - IRQ_QUIET - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. - - This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. - [23:23] - read-write - - - TREQ_SEL - Select a Transfer Request signal. - The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). - 0x0 to 0x3a -> select DREQ n as TREQ - [22:17] - read-write - - - PIO0_TX0 - 0 - Select PIO0's TX FIFO 0 as TREQ - - - PIO0_TX1 - 1 - Select PIO0's TX FIFO 1 as TREQ - - - PIO0_TX2 - 2 - Select PIO0's TX FIFO 2 as TREQ - - - PIO0_TX3 - 3 - Select PIO0's TX FIFO 3 as TREQ - - - PIO0_RX0 - 4 - Select PIO0's RX FIFO 0 as TREQ - - - PIO0_RX1 - 5 - Select PIO0's RX FIFO 1 as TREQ - - - PIO0_RX2 - 6 - Select PIO0's RX FIFO 2 as TREQ - - - PIO0_RX3 - 7 - Select PIO0's RX FIFO 3 as TREQ - - - PIO1_TX0 - 8 - Select PIO1's TX FIFO 0 as TREQ - - - PIO1_TX1 - 9 - Select PIO1's TX FIFO 1 as TREQ - - - PIO1_TX2 - 10 - Select PIO1's TX FIFO 2 as TREQ - - - PIO1_TX3 - 11 - Select PIO1's TX FIFO 3 as TREQ - - - PIO1_RX0 - 12 - Select PIO1's RX FIFO 0 as TREQ - - - PIO1_RX1 - 13 - Select PIO1's RX FIFO 1 as TREQ - - - PIO1_RX2 - 14 - Select PIO1's RX FIFO 2 as TREQ - - - PIO1_RX3 - 15 - Select PIO1's RX FIFO 3 as TREQ - - - PIO2_TX0 - 16 - Select PIO2's TX FIFO 0 as TREQ - - - PIO2_TX1 - 17 - Select PIO2's TX FIFO 1 as TREQ - - - PIO2_TX2 - 18 - Select PIO2's TX FIFO 2 as TREQ - - - PIO2_TX3 - 19 - Select PIO2's TX FIFO 3 as TREQ - - - PIO2_RX0 - 20 - Select PIO2's RX FIFO 0 as TREQ - - - PIO2_RX1 - 21 - Select PIO2's RX FIFO 1 as TREQ - - - PIO2_RX2 - 22 - Select PIO2's RX FIFO 2 as TREQ - - - PIO2_RX3 - 23 - Select PIO2's RX FIFO 3 as TREQ - - - SPI0_TX - 24 - Select SPI0's TX FIFO as TREQ - - - SPI0_RX - 25 - Select SPI0's RX FIFO as TREQ - - - SPI1_TX - 26 - Select SPI1's TX FIFO as TREQ - - - SPI1_RX - 27 - Select SPI1's RX FIFO as TREQ - - - UART0_TX - 28 - Select UART0's TX FIFO as TREQ - - - UART0_RX - 29 - Select UART0's RX FIFO as TREQ - - - UART1_TX - 30 - Select UART1's TX FIFO as TREQ - - - UART1_RX - 31 - Select UART1's RX FIFO as TREQ - - - PWM_WRAP0 - 32 - Select PWM Counter 0's Wrap Value as TREQ - - - PWM_WRAP1 - 33 - Select PWM Counter 1's Wrap Value as TREQ - - - PWM_WRAP2 - 34 - Select PWM Counter 2's Wrap Value as TREQ - - - PWM_WRAP3 - 35 - Select PWM Counter 3's Wrap Value as TREQ - - - PWM_WRAP4 - 36 - Select PWM Counter 4's Wrap Value as TREQ - - - PWM_WRAP5 - 37 - Select PWM Counter 5's Wrap Value as TREQ - - - PWM_WRAP6 - 38 - Select PWM Counter 6's Wrap Value as TREQ - - - PWM_WRAP7 - 39 - Select PWM Counter 7's Wrap Value as TREQ - - - PWM_WRAP8 - 40 - Select PWM Counter 8's Wrap Value as TREQ - - - PWM_WRAP9 - 41 - Select PWM Counter 9's Wrap Value as TREQ - - - PWM_WRAP10 - 42 - Select PWM Counter 0's Wrap Value as TREQ - - - PWM_WRAP11 - 43 - Select PWM Counter 1's Wrap Value as TREQ - - - I2C0_TX - 44 - Select I2C0's TX FIFO as TREQ - - - I2C0_RX - 45 - Select I2C0's RX FIFO as TREQ - - - I2C1_TX - 46 - Select I2C1's TX FIFO as TREQ - - - I2C1_RX - 47 - Select I2C1's RX FIFO as TREQ - - - ADC - 48 - Select the ADC as TREQ - - - XIP_STREAM - 49 - Select the XIP Streaming FIFO as TREQ - - - XIP_QMITX - 50 - Select XIP_QMITX as TREQ - - - XIP_QMIRX - 51 - Select XIP_QMIRX as TREQ - - - HSTX - 52 - Select HSTX as TREQ - - - CORESIGHT - 53 - Select CORESIGHT as TREQ - - - SHA256 - 54 - Select SHA256 as TREQ - - - TIMER0 - 59 - Select Timer 0 as TREQ - - - TIMER1 - 60 - Select Timer 1 as TREQ - - - TIMER2 - 61 - Select Timer 2 as TREQ (Optional) - - - TIMER3 - 62 - Select Timer 3 as TREQ (Optional) - - - PERMANENT - 63 - Permanent request, for unpaced transfers. - - - - - CHAIN_TO - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. - - Note this field resets to 0, so channels 1 and above will chain to channel 0 by default. Set this field to avoid this behaviour. - [16:13] - read-write - - - RING_SEL - Select whether RING_SIZE applies to read or write addresses. - If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. - [12:12] - read-write - - - RING_SIZE - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. - - Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. - [11:8] - read-write - - - RING_NONE - 0 - - - - - INCR_WRITE_REV - If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer. - - If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. - [7:7] - read-write - - - INCR_WRITE - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. - - Generally this should be disabled for memory-to-peripheral transfers. - [6:6] - read-write - - - INCR_READ_REV - If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer. - - If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. - [5:5] - read-write - - - INCR_READ - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. - - Generally this should be disabled for peripheral-to-memory transfers. - [4:4] - read-write - - - DATA_SIZE - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. - [3:2] - read-write - - - SIZE_BYTE - 0 - - - SIZE_HALFWORD - 1 - - - SIZE_WORD - 2 - - - - - HIGH_PRIORITY - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. - - This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. - [1:1] - read-write - - - EN - DMA Channel Enable. - When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) - [0:0] - read-write - - - - - CH2_AL1_CTRL - 0x00000090 - Alias for channel 2 CTRL register - 0x00000000 - - - CH2_AL1_CTRL - [31:0] - read-write - - - - - CH2_AL1_READ_ADDR - 0x00000094 - Alias for channel 2 READ_ADDR register - 0x00000000 - - - CH2_AL1_READ_ADDR - [31:0] - read-write - - - - - CH2_AL1_WRITE_ADDR - 0x00000098 - Alias for channel 2 WRITE_ADDR register - 0x00000000 - - - CH2_AL1_WRITE_ADDR - [31:0] - read-write - - - - - CH2_AL1_TRANS_COUNT_TRIG - 0x0000009c - Alias for channel 2 TRANS_COUNT register - This is a trigger register (0xc). Writing a nonzero value will - reload the channel counter and start the channel. - 0x00000000 - - - CH2_AL1_TRANS_COUNT_TRIG - [31:0] - read-write - - - - - CH2_AL2_CTRL - 0x000000a0 - Alias for channel 2 CTRL register - 0x00000000 - - - CH2_AL2_CTRL - [31:0] - read-write - - - - - CH2_AL2_TRANS_COUNT - 0x000000a4 - Alias for channel 2 TRANS_COUNT register - 0x00000000 - - - CH2_AL2_TRANS_COUNT - [31:0] - read-write - - - - - CH2_AL2_READ_ADDR - 0x000000a8 - Alias for channel 2 READ_ADDR register - 0x00000000 - - - CH2_AL2_READ_ADDR - [31:0] - read-write - - - - - CH2_AL2_WRITE_ADDR_TRIG - 0x000000ac - Alias for channel 2 WRITE_ADDR register - This is a trigger register (0xc). Writing a nonzero value will - reload the channel counter and start the channel. - 0x00000000 - - - CH2_AL2_WRITE_ADDR_TRIG - [31:0] - read-write - - - - - CH2_AL3_CTRL - 0x000000b0 - Alias for channel 2 CTRL register - 0x00000000 - - - CH2_AL3_CTRL - [31:0] - read-write - - - - - CH2_AL3_WRITE_ADDR - 0x000000b4 - Alias for channel 2 WRITE_ADDR register - 0x00000000 - - - CH2_AL3_WRITE_ADDR - [31:0] - read-write - - - - - CH2_AL3_TRANS_COUNT - 0x000000b8 - Alias for channel 2 TRANS_COUNT register - 0x00000000 - - - CH2_AL3_TRANS_COUNT - [31:0] - read-write - - - - - CH2_AL3_READ_ADDR_TRIG - 0x000000bc - Alias for channel 2 READ_ADDR register - This is a trigger register (0xc). Writing a nonzero value will - reload the channel counter and start the channel. - 0x00000000 - - - CH2_AL3_READ_ADDR_TRIG - [31:0] - read-write - - - - - CH3_READ_ADDR - 0x000000c0 - DMA Channel 3 Read Address pointer - 0x00000000 - - - CH3_READ_ADDR - This register updates automatically each time a read completes. The current value is the next address to be read by this channel. - [31:0] - read-write - - - - - CH3_WRITE_ADDR - 0x000000c4 - DMA Channel 3 Write Address pointer - 0x00000000 - - - CH3_WRITE_ADDR - This register updates automatically each time a write completes. The current value is the next address to be written by this channel. - [31:0] - read-write - - - - - CH3_TRANS_COUNT - 0x000000c8 - DMA Channel 3 Transfer Count - 0x00000000 - - - MODE - When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. - - When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. - - When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. - - All other values are reserved. - [31:28] - read-write - - - NORMAL - 0 - - - TRIGGER_SELF - 1 - - - ENDLESS - 15 - - - - - COUNT - 28-bit transfer count (256 million transfers maximum). - - Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). - - When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. - - Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. - - The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. - [27:0] - read-write - - - - - CH3_CTRL_TRIG - 0x000000cc - DMA Channel 3 Control and Status - 0x00000000 - - - AHB_ERROR - Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. - [31:31] - read-only - - - READ_ERROR - If 1, the channel received a read bus error. Write one to clear. - READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) - [30:30] - read-write - oneToClear - - - WRITE_ERROR - If 1, the channel received a write bus error. Write one to clear. - WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) - [29:29] - read-write - oneToClear - - - BUSY - This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. - - To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. - [26:26] - read-only - - - SNIFF_EN - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. - - This allows checksum to be enabled or disabled on a per-control- block basis. - [25:25] - read-write - - - BSWAP - Apply byte-swap transformation to DMA data. - For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. - [24:24] - read-write - - - IRQ_QUIET - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. - - This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. - [23:23] - read-write - - - TREQ_SEL - Select a Transfer Request signal. - The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). - 0x0 to 0x3a -> select DREQ n as TREQ - [22:17] - read-write - - - PIO0_TX0 - 0 - Select PIO0's TX FIFO 0 as TREQ - - - PIO0_TX1 - 1 - Select PIO0's TX FIFO 1 as TREQ - - - PIO0_TX2 - 2 - Select PIO0's TX FIFO 2 as TREQ - - - PIO0_TX3 - 3 - Select PIO0's TX FIFO 3 as TREQ - - - PIO0_RX0 - 4 - Select PIO0's RX FIFO 0 as TREQ - - - PIO0_RX1 - 5 - Select PIO0's RX FIFO 1 as TREQ - - - PIO0_RX2 - 6 - Select PIO0's RX FIFO 2 as TREQ - - - PIO0_RX3 - 7 - Select PIO0's RX FIFO 3 as TREQ - - - PIO1_TX0 - 8 - Select PIO1's TX FIFO 0 as TREQ - - - PIO1_TX1 - 9 - Select PIO1's TX FIFO 1 as TREQ - - - PIO1_TX2 - 10 - Select PIO1's TX FIFO 2 as TREQ - - - PIO1_TX3 - 11 - Select PIO1's TX FIFO 3 as TREQ - - - PIO1_RX0 - 12 - Select PIO1's RX FIFO 0 as TREQ - - - PIO1_RX1 - 13 - Select PIO1's RX FIFO 1 as TREQ - - - PIO1_RX2 - 14 - Select PIO1's RX FIFO 2 as TREQ - - - PIO1_RX3 - 15 - Select PIO1's RX FIFO 3 as TREQ - - - PIO2_TX0 - 16 - Select PIO2's TX FIFO 0 as TREQ - - - PIO2_TX1 - 17 - Select PIO2's TX FIFO 1 as TREQ - - - PIO2_TX2 - 18 - Select PIO2's TX FIFO 2 as TREQ - - - PIO2_TX3 - 19 - Select PIO2's TX FIFO 3 as TREQ - - - PIO2_RX0 - 20 - Select PIO2's RX FIFO 0 as TREQ - - - PIO2_RX1 - 21 - Select PIO2's RX FIFO 1 as TREQ - - - PIO2_RX2 - 22 - Select PIO2's RX FIFO 2 as TREQ - - - PIO2_RX3 - 23 - Select PIO2's RX FIFO 3 as TREQ - - - SPI0_TX - 24 - Select SPI0's TX FIFO as TREQ - - - SPI0_RX - 25 - Select SPI0's RX FIFO as TREQ - - - SPI1_TX - 26 - Select SPI1's TX FIFO as TREQ - - - SPI1_RX - 27 - Select SPI1's RX FIFO as TREQ - - - UART0_TX - 28 - Select UART0's TX FIFO as TREQ - - - UART0_RX - 29 - Select UART0's RX FIFO as TREQ - - - UART1_TX - 30 - Select UART1's TX FIFO as TREQ - - - UART1_RX - 31 - Select UART1's RX FIFO as TREQ - - - PWM_WRAP0 - 32 - Select PWM Counter 0's Wrap Value as TREQ - - - PWM_WRAP1 - 33 - Select PWM Counter 1's Wrap Value as TREQ - - - PWM_WRAP2 - 34 - Select PWM Counter 2's Wrap Value as TREQ - - - PWM_WRAP3 - 35 - Select PWM Counter 3's Wrap Value as TREQ - - - PWM_WRAP4 - 36 - Select PWM Counter 4's Wrap Value as TREQ - - - PWM_WRAP5 - 37 - Select PWM Counter 5's Wrap Value as TREQ - - - PWM_WRAP6 - 38 - Select PWM Counter 6's Wrap Value as TREQ - - - PWM_WRAP7 - 39 - Select PWM Counter 7's Wrap Value as TREQ - - - PWM_WRAP8 - 40 - Select PWM Counter 8's Wrap Value as TREQ - - - PWM_WRAP9 - 41 - Select PWM Counter 9's Wrap Value as TREQ - - - PWM_WRAP10 - 42 - Select PWM Counter 0's Wrap Value as TREQ - - - PWM_WRAP11 - 43 - Select PWM Counter 1's Wrap Value as TREQ - - - I2C0_TX - 44 - Select I2C0's TX FIFO as TREQ - - - I2C0_RX - 45 - Select I2C0's RX FIFO as TREQ - - - I2C1_TX - 46 - Select I2C1's TX FIFO as TREQ - - - I2C1_RX - 47 - Select I2C1's RX FIFO as TREQ - - - ADC - 48 - Select the ADC as TREQ - - - XIP_STREAM - 49 - Select the XIP Streaming FIFO as TREQ - - - XIP_QMITX - 50 - Select XIP_QMITX as TREQ - - - XIP_QMIRX - 51 - Select XIP_QMIRX as TREQ - - - HSTX - 52 - Select HSTX as TREQ - - - CORESIGHT - 53 - Select CORESIGHT as TREQ - - - SHA256 - 54 - Select SHA256 as TREQ - - - TIMER0 - 59 - Select Timer 0 as TREQ - - - TIMER1 - 60 - Select Timer 1 as TREQ - - - TIMER2 - 61 - Select Timer 2 as TREQ (Optional) - - - TIMER3 - 62 - Select Timer 3 as TREQ (Optional) - - - PERMANENT - 63 - Permanent request, for unpaced transfers. - - - - - CHAIN_TO - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. - - Note this field resets to 0, so channels 1 and above will chain to channel 0 by default. Set this field to avoid this behaviour. - [16:13] - read-write - - - RING_SEL - Select whether RING_SIZE applies to read or write addresses. - If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. - [12:12] - read-write - - - RING_SIZE - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. - - Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. - [11:8] - read-write - - - RING_NONE - 0 - - - - - INCR_WRITE_REV - If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer. - - If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. - [7:7] - read-write - - - INCR_WRITE - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. - - Generally this should be disabled for memory-to-peripheral transfers. - [6:6] - read-write - - - INCR_READ_REV - If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer. - - If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. - [5:5] - read-write - - - INCR_READ - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. - - Generally this should be disabled for peripheral-to-memory transfers. - [4:4] - read-write - - - DATA_SIZE - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. - [3:2] - read-write - - - SIZE_BYTE - 0 - - - SIZE_HALFWORD - 1 - - - SIZE_WORD - 2 - - - - - HIGH_PRIORITY - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. - - This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. - [1:1] - read-write - - - EN - DMA Channel Enable. - When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) - [0:0] - read-write - - - - - CH3_AL1_CTRL - 0x000000d0 - Alias for channel 3 CTRL register - 0x00000000 - - - CH3_AL1_CTRL - [31:0] - read-write - - - - - CH3_AL1_READ_ADDR - 0x000000d4 - Alias for channel 3 READ_ADDR register - 0x00000000 - - - CH3_AL1_READ_ADDR - [31:0] - read-write - - - - - CH3_AL1_WRITE_ADDR - 0x000000d8 - Alias for channel 3 WRITE_ADDR register - 0x00000000 - - - CH3_AL1_WRITE_ADDR - [31:0] - read-write - - - - - CH3_AL1_TRANS_COUNT_TRIG - 0x000000dc - Alias for channel 3 TRANS_COUNT register - This is a trigger register (0xc). Writing a nonzero value will - reload the channel counter and start the channel. - 0x00000000 - - - CH3_AL1_TRANS_COUNT_TRIG - [31:0] - read-write - - - - - CH3_AL2_CTRL - 0x000000e0 - Alias for channel 3 CTRL register - 0x00000000 - - - CH3_AL2_CTRL - [31:0] - read-write - - - - - CH3_AL2_TRANS_COUNT - 0x000000e4 - Alias for channel 3 TRANS_COUNT register - 0x00000000 - - - CH3_AL2_TRANS_COUNT - [31:0] - read-write - - - - - CH3_AL2_READ_ADDR - 0x000000e8 - Alias for channel 3 READ_ADDR register - 0x00000000 - - - CH3_AL2_READ_ADDR - [31:0] - read-write - - - - - CH3_AL2_WRITE_ADDR_TRIG - 0x000000ec - Alias for channel 3 WRITE_ADDR register - This is a trigger register (0xc). Writing a nonzero value will - reload the channel counter and start the channel. - 0x00000000 - - - CH3_AL2_WRITE_ADDR_TRIG - [31:0] - read-write - - - - - CH3_AL3_CTRL - 0x000000f0 - Alias for channel 3 CTRL register - 0x00000000 - - - CH3_AL3_CTRL - [31:0] - read-write - - - - - CH3_AL3_WRITE_ADDR - 0x000000f4 - Alias for channel 3 WRITE_ADDR register - 0x00000000 - - - CH3_AL3_WRITE_ADDR - [31:0] - read-write - - - - - CH3_AL3_TRANS_COUNT - 0x000000f8 - Alias for channel 3 TRANS_COUNT register - 0x00000000 - - - CH3_AL3_TRANS_COUNT - [31:0] - read-write - - - - - CH3_AL3_READ_ADDR_TRIG - 0x000000fc - Alias for channel 3 READ_ADDR register - This is a trigger register (0xc). Writing a nonzero value will - reload the channel counter and start the channel. - 0x00000000 - - - CH3_AL3_READ_ADDR_TRIG - [31:0] - read-write - - - - - CH4_READ_ADDR - 0x00000100 - DMA Channel 4 Read Address pointer - 0x00000000 - - - CH4_READ_ADDR - This register updates automatically each time a read completes. The current value is the next address to be read by this channel. - [31:0] - read-write - - - - - CH4_WRITE_ADDR - 0x00000104 - DMA Channel 4 Write Address pointer - 0x00000000 - - - CH4_WRITE_ADDR - This register updates automatically each time a write completes. The current value is the next address to be written by this channel. - [31:0] - read-write - - - - - CH4_TRANS_COUNT - 0x00000108 - DMA Channel 4 Transfer Count - 0x00000000 - - - MODE - When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. - - When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. - - When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. - - All other values are reserved. - [31:28] - read-write - - - NORMAL - 0 - - - TRIGGER_SELF - 1 - - - ENDLESS - 15 - - - - - COUNT - 28-bit transfer count (256 million transfers maximum). - - Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). - - When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. - - Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. - - The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. - [27:0] - read-write - - - - - CH4_CTRL_TRIG - 0x0000010c - DMA Channel 4 Control and Status - 0x00000000 - - - AHB_ERROR - Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. - [31:31] - read-only - - - READ_ERROR - If 1, the channel received a read bus error. Write one to clear. - READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) - [30:30] - read-write - oneToClear - - - WRITE_ERROR - If 1, the channel received a write bus error. Write one to clear. - WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) - [29:29] - read-write - oneToClear - - - BUSY - This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. - - To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. - [26:26] - read-only - - - SNIFF_EN - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. - - This allows checksum to be enabled or disabled on a per-control- block basis. - [25:25] - read-write - - - BSWAP - Apply byte-swap transformation to DMA data. - For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. - [24:24] - read-write - - - IRQ_QUIET - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. - - This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. - [23:23] - read-write - - - TREQ_SEL - Select a Transfer Request signal. - The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). - 0x0 to 0x3a -> select DREQ n as TREQ - [22:17] - read-write - - - PIO0_TX0 - 0 - Select PIO0's TX FIFO 0 as TREQ - - - PIO0_TX1 - 1 - Select PIO0's TX FIFO 1 as TREQ - - - PIO0_TX2 - 2 - Select PIO0's TX FIFO 2 as TREQ - - - PIO0_TX3 - 3 - Select PIO0's TX FIFO 3 as TREQ - - - PIO0_RX0 - 4 - Select PIO0's RX FIFO 0 as TREQ - - - PIO0_RX1 - 5 - Select PIO0's RX FIFO 1 as TREQ - - - PIO0_RX2 - 6 - Select PIO0's RX FIFO 2 as TREQ - - - PIO0_RX3 - 7 - Select PIO0's RX FIFO 3 as TREQ - - - PIO1_TX0 - 8 - Select PIO1's TX FIFO 0 as TREQ - - - PIO1_TX1 - 9 - Select PIO1's TX FIFO 1 as TREQ - - - PIO1_TX2 - 10 - Select PIO1's TX FIFO 2 as TREQ - - - PIO1_TX3 - 11 - Select PIO1's TX FIFO 3 as TREQ - - - PIO1_RX0 - 12 - Select PIO1's RX FIFO 0 as TREQ - - - PIO1_RX1 - 13 - Select PIO1's RX FIFO 1 as TREQ - - - PIO1_RX2 - 14 - Select PIO1's RX FIFO 2 as TREQ - - - PIO1_RX3 - 15 - Select PIO1's RX FIFO 3 as TREQ - - - PIO2_TX0 - 16 - Select PIO2's TX FIFO 0 as TREQ - - - PIO2_TX1 - 17 - Select PIO2's TX FIFO 1 as TREQ - - - PIO2_TX2 - 18 - Select PIO2's TX FIFO 2 as TREQ - - - PIO2_TX3 - 19 - Select PIO2's TX FIFO 3 as TREQ - - - PIO2_RX0 - 20 - Select PIO2's RX FIFO 0 as TREQ - - - PIO2_RX1 - 21 - Select PIO2's RX FIFO 1 as TREQ - - - PIO2_RX2 - 22 - Select PIO2's RX FIFO 2 as TREQ - - - PIO2_RX3 - 23 - Select PIO2's RX FIFO 3 as TREQ - - - SPI0_TX - 24 - Select SPI0's TX FIFO as TREQ - - - SPI0_RX - 25 - Select SPI0's RX FIFO as TREQ - - - SPI1_TX - 26 - Select SPI1's TX FIFO as TREQ - - - SPI1_RX - 27 - Select SPI1's RX FIFO as TREQ - - - UART0_TX - 28 - Select UART0's TX FIFO as TREQ - - - UART0_RX - 29 - Select UART0's RX FIFO as TREQ - - - UART1_TX - 30 - Select UART1's TX FIFO as TREQ - - - UART1_RX - 31 - Select UART1's RX FIFO as TREQ - - - PWM_WRAP0 - 32 - Select PWM Counter 0's Wrap Value as TREQ - - - PWM_WRAP1 - 33 - Select PWM Counter 1's Wrap Value as TREQ - - - PWM_WRAP2 - 34 - Select PWM Counter 2's Wrap Value as TREQ - - - PWM_WRAP3 - 35 - Select PWM Counter 3's Wrap Value as TREQ - - - PWM_WRAP4 - 36 - Select PWM Counter 4's Wrap Value as TREQ - - - PWM_WRAP5 - 37 - Select PWM Counter 5's Wrap Value as TREQ - - - PWM_WRAP6 - 38 - Select PWM Counter 6's Wrap Value as TREQ - - - PWM_WRAP7 - 39 - Select PWM Counter 7's Wrap Value as TREQ - - - PWM_WRAP8 - 40 - Select PWM Counter 8's Wrap Value as TREQ - - - PWM_WRAP9 - 41 - Select PWM Counter 9's Wrap Value as TREQ - - - PWM_WRAP10 - 42 - Select PWM Counter 0's Wrap Value as TREQ - - - PWM_WRAP11 - 43 - Select PWM Counter 1's Wrap Value as TREQ - - - I2C0_TX - 44 - Select I2C0's TX FIFO as TREQ - - - I2C0_RX - 45 - Select I2C0's RX FIFO as TREQ - - - I2C1_TX - 46 - Select I2C1's TX FIFO as TREQ - - - I2C1_RX - 47 - Select I2C1's RX FIFO as TREQ - - - ADC - 48 - Select the ADC as TREQ - - - XIP_STREAM - 49 - Select the XIP Streaming FIFO as TREQ - - - XIP_QMITX - 50 - Select XIP_QMITX as TREQ - - - XIP_QMIRX - 51 - Select XIP_QMIRX as TREQ - - - HSTX - 52 - Select HSTX as TREQ - - - CORESIGHT - 53 - Select CORESIGHT as TREQ - - - SHA256 - 54 - Select SHA256 as TREQ - - - TIMER0 - 59 - Select Timer 0 as TREQ - - - TIMER1 - 60 - Select Timer 1 as TREQ - - - TIMER2 - 61 - Select Timer 2 as TREQ (Optional) - - - TIMER3 - 62 - Select Timer 3 as TREQ (Optional) - - - PERMANENT - 63 - Permanent request, for unpaced transfers. - - - - - CHAIN_TO - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. - - Note this field resets to 0, so channels 1 and above will chain to channel 0 by default. Set this field to avoid this behaviour. - [16:13] - read-write - - - RING_SEL - Select whether RING_SIZE applies to read or write addresses. - If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. - [12:12] - read-write - - - RING_SIZE - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. - - Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. - [11:8] - read-write - - - RING_NONE - 0 - - - - - INCR_WRITE_REV - If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer. - - If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. - [7:7] - read-write - - - INCR_WRITE - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. - - Generally this should be disabled for memory-to-peripheral transfers. - [6:6] - read-write - - - INCR_READ_REV - If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer. - - If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. - [5:5] - read-write - - - INCR_READ - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. - - Generally this should be disabled for peripheral-to-memory transfers. - [4:4] - read-write - - - DATA_SIZE - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. - [3:2] - read-write - - - SIZE_BYTE - 0 - - - SIZE_HALFWORD - 1 - - - SIZE_WORD - 2 - - - - - HIGH_PRIORITY - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. - - This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. - [1:1] - read-write - - - EN - DMA Channel Enable. - When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) - [0:0] - read-write - - - - - CH4_AL1_CTRL - 0x00000110 - Alias for channel 4 CTRL register - 0x00000000 - - - CH4_AL1_CTRL - [31:0] - read-write - - - - - CH4_AL1_READ_ADDR - 0x00000114 - Alias for channel 4 READ_ADDR register - 0x00000000 - - - CH4_AL1_READ_ADDR - [31:0] - read-write - - - - - CH4_AL1_WRITE_ADDR - 0x00000118 - Alias for channel 4 WRITE_ADDR register - 0x00000000 - - - CH4_AL1_WRITE_ADDR - [31:0] - read-write - - - - - CH4_AL1_TRANS_COUNT_TRIG - 0x0000011c - Alias for channel 4 TRANS_COUNT register - This is a trigger register (0xc). Writing a nonzero value will - reload the channel counter and start the channel. - 0x00000000 - - - CH4_AL1_TRANS_COUNT_TRIG - [31:0] - read-write - - - - - CH4_AL2_CTRL - 0x00000120 - Alias for channel 4 CTRL register - 0x00000000 - - - CH4_AL2_CTRL - [31:0] - read-write - - - - - CH4_AL2_TRANS_COUNT - 0x00000124 - Alias for channel 4 TRANS_COUNT register - 0x00000000 - - - CH4_AL2_TRANS_COUNT - [31:0] - read-write - - - - - CH4_AL2_READ_ADDR - 0x00000128 - Alias for channel 4 READ_ADDR register - 0x00000000 - - - CH4_AL2_READ_ADDR - [31:0] - read-write - - - - - CH4_AL2_WRITE_ADDR_TRIG - 0x0000012c - Alias for channel 4 WRITE_ADDR register - This is a trigger register (0xc). Writing a nonzero value will - reload the channel counter and start the channel. - 0x00000000 - - - CH4_AL2_WRITE_ADDR_TRIG - [31:0] - read-write - - - - - CH4_AL3_CTRL - 0x00000130 - Alias for channel 4 CTRL register - 0x00000000 - - - CH4_AL3_CTRL - [31:0] - read-write - - - - - CH4_AL3_WRITE_ADDR - 0x00000134 - Alias for channel 4 WRITE_ADDR register - 0x00000000 - - - CH4_AL3_WRITE_ADDR - [31:0] - read-write - - - - - CH4_AL3_TRANS_COUNT - 0x00000138 - Alias for channel 4 TRANS_COUNT register - 0x00000000 - - - CH4_AL3_TRANS_COUNT - [31:0] - read-write - - - - - CH4_AL3_READ_ADDR_TRIG - 0x0000013c - Alias for channel 4 READ_ADDR register - This is a trigger register (0xc). Writing a nonzero value will - reload the channel counter and start the channel. - 0x00000000 - - - CH4_AL3_READ_ADDR_TRIG - [31:0] - read-write - - - - - CH5_READ_ADDR - 0x00000140 - DMA Channel 5 Read Address pointer - 0x00000000 - - - CH5_READ_ADDR - This register updates automatically each time a read completes. The current value is the next address to be read by this channel. - [31:0] - read-write - - - - - CH5_WRITE_ADDR - 0x00000144 - DMA Channel 5 Write Address pointer - 0x00000000 - - - CH5_WRITE_ADDR - This register updates automatically each time a write completes. The current value is the next address to be written by this channel. - [31:0] - read-write - - - - - CH5_TRANS_COUNT - 0x00000148 - DMA Channel 5 Transfer Count - 0x00000000 - - - MODE - When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. - - When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. - - When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. - - All other values are reserved. - [31:28] - read-write - - - NORMAL - 0 - - - TRIGGER_SELF - 1 - - - ENDLESS - 15 - - - - - COUNT - 28-bit transfer count (256 million transfers maximum). - - Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). - - When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. - - Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. - - The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. - [27:0] - read-write - - - - - CH5_CTRL_TRIG - 0x0000014c - DMA Channel 5 Control and Status - 0x00000000 - - - AHB_ERROR - Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. - [31:31] - read-only - - - READ_ERROR - If 1, the channel received a read bus error. Write one to clear. - READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) - [30:30] - read-write - oneToClear - - - WRITE_ERROR - If 1, the channel received a write bus error. Write one to clear. - WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) - [29:29] - read-write - oneToClear - - - BUSY - This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. - - To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. - [26:26] - read-only - - - SNIFF_EN - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. - - This allows checksum to be enabled or disabled on a per-control- block basis. - [25:25] - read-write - - - BSWAP - Apply byte-swap transformation to DMA data. - For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. - [24:24] - read-write - - - IRQ_QUIET - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. - - This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. - [23:23] - read-write - - - TREQ_SEL - Select a Transfer Request signal. - The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). - 0x0 to 0x3a -> select DREQ n as TREQ - [22:17] - read-write - - - PIO0_TX0 - 0 - Select PIO0's TX FIFO 0 as TREQ - - - PIO0_TX1 - 1 - Select PIO0's TX FIFO 1 as TREQ - - - PIO0_TX2 - 2 - Select PIO0's TX FIFO 2 as TREQ - - - PIO0_TX3 - 3 - Select PIO0's TX FIFO 3 as TREQ - - - PIO0_RX0 - 4 - Select PIO0's RX FIFO 0 as TREQ - - - PIO0_RX1 - 5 - Select PIO0's RX FIFO 1 as TREQ - - - PIO0_RX2 - 6 - Select PIO0's RX FIFO 2 as TREQ - - - PIO0_RX3 - 7 - Select PIO0's RX FIFO 3 as TREQ - - - PIO1_TX0 - 8 - Select PIO1's TX FIFO 0 as TREQ - - - PIO1_TX1 - 9 - Select PIO1's TX FIFO 1 as TREQ - - - PIO1_TX2 - 10 - Select PIO1's TX FIFO 2 as TREQ - - - PIO1_TX3 - 11 - Select PIO1's TX FIFO 3 as TREQ - - - PIO1_RX0 - 12 - Select PIO1's RX FIFO 0 as TREQ - - - PIO1_RX1 - 13 - Select PIO1's RX FIFO 1 as TREQ - - - PIO1_RX2 - 14 - Select PIO1's RX FIFO 2 as TREQ - - - PIO1_RX3 - 15 - Select PIO1's RX FIFO 3 as TREQ - - - PIO2_TX0 - 16 - Select PIO2's TX FIFO 0 as TREQ - - - PIO2_TX1 - 17 - Select PIO2's TX FIFO 1 as TREQ - - - PIO2_TX2 - 18 - Select PIO2's TX FIFO 2 as TREQ - - - PIO2_TX3 - 19 - Select PIO2's TX FIFO 3 as TREQ - - - PIO2_RX0 - 20 - Select PIO2's RX FIFO 0 as TREQ - - - PIO2_RX1 - 21 - Select PIO2's RX FIFO 1 as TREQ - - - PIO2_RX2 - 22 - Select PIO2's RX FIFO 2 as TREQ - - - PIO2_RX3 - 23 - Select PIO2's RX FIFO 3 as TREQ - - - SPI0_TX - 24 - Select SPI0's TX FIFO as TREQ - - - SPI0_RX - 25 - Select SPI0's RX FIFO as TREQ - - - SPI1_TX - 26 - Select SPI1's TX FIFO as TREQ - - - SPI1_RX - 27 - Select SPI1's RX FIFO as TREQ - - - UART0_TX - 28 - Select UART0's TX FIFO as TREQ - - - UART0_RX - 29 - Select UART0's RX FIFO as TREQ - - - UART1_TX - 30 - Select UART1's TX FIFO as TREQ - - - UART1_RX - 31 - Select UART1's RX FIFO as TREQ - - - PWM_WRAP0 - 32 - Select PWM Counter 0's Wrap Value as TREQ - - - PWM_WRAP1 - 33 - Select PWM Counter 1's Wrap Value as TREQ - - - PWM_WRAP2 - 34 - Select PWM Counter 2's Wrap Value as TREQ - - - PWM_WRAP3 - 35 - Select PWM Counter 3's Wrap Value as TREQ - - - PWM_WRAP4 - 36 - Select PWM Counter 4's Wrap Value as TREQ - - - PWM_WRAP5 - 37 - Select PWM Counter 5's Wrap Value as TREQ - - - PWM_WRAP6 - 38 - Select PWM Counter 6's Wrap Value as TREQ - - - PWM_WRAP7 - 39 - Select PWM Counter 7's Wrap Value as TREQ - - - PWM_WRAP8 - 40 - Select PWM Counter 8's Wrap Value as TREQ - - - PWM_WRAP9 - 41 - Select PWM Counter 9's Wrap Value as TREQ - - - PWM_WRAP10 - 42 - Select PWM Counter 0's Wrap Value as TREQ - - - PWM_WRAP11 - 43 - Select PWM Counter 1's Wrap Value as TREQ - - - I2C0_TX - 44 - Select I2C0's TX FIFO as TREQ - - - I2C0_RX - 45 - Select I2C0's RX FIFO as TREQ - - - I2C1_TX - 46 - Select I2C1's TX FIFO as TREQ - - - I2C1_RX - 47 - Select I2C1's RX FIFO as TREQ - - - ADC - 48 - Select the ADC as TREQ - - - XIP_STREAM - 49 - Select the XIP Streaming FIFO as TREQ - - - XIP_QMITX - 50 - Select XIP_QMITX as TREQ - - - XIP_QMIRX - 51 - Select XIP_QMIRX as TREQ - - - HSTX - 52 - Select HSTX as TREQ - - - CORESIGHT - 53 - Select CORESIGHT as TREQ - - - SHA256 - 54 - Select SHA256 as TREQ - - - TIMER0 - 59 - Select Timer 0 as TREQ - - - TIMER1 - 60 - Select Timer 1 as TREQ - - - TIMER2 - 61 - Select Timer 2 as TREQ (Optional) - - - TIMER3 - 62 - Select Timer 3 as TREQ (Optional) - - - PERMANENT - 63 - Permanent request, for unpaced transfers. - - - - - CHAIN_TO - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. - - Note this field resets to 0, so channels 1 and above will chain to channel 0 by default. Set this field to avoid this behaviour. - [16:13] - read-write - - - RING_SEL - Select whether RING_SIZE applies to read or write addresses. - If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. - [12:12] - read-write - - - RING_SIZE - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. - - Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. - [11:8] - read-write - - - RING_NONE - 0 - - - - - INCR_WRITE_REV - If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer. - - If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. - [7:7] - read-write - - - INCR_WRITE - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. - - Generally this should be disabled for memory-to-peripheral transfers. - [6:6] - read-write - - - INCR_READ_REV - If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer. - - If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. - [5:5] - read-write - - - INCR_READ - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. - - Generally this should be disabled for peripheral-to-memory transfers. - [4:4] - read-write - - - DATA_SIZE - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. - [3:2] - read-write - - - SIZE_BYTE - 0 - - - SIZE_HALFWORD - 1 - - - SIZE_WORD - 2 - - - - - HIGH_PRIORITY - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. - - This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. - [1:1] - read-write - - - EN - DMA Channel Enable. - When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) - [0:0] - read-write - - - - - CH5_AL1_CTRL - 0x00000150 - Alias for channel 5 CTRL register - 0x00000000 - - - CH5_AL1_CTRL - [31:0] - read-write - - - - - CH5_AL1_READ_ADDR - 0x00000154 - Alias for channel 5 READ_ADDR register - 0x00000000 - - - CH5_AL1_READ_ADDR - [31:0] - read-write - - - - - CH5_AL1_WRITE_ADDR - 0x00000158 - Alias for channel 5 WRITE_ADDR register - 0x00000000 - - - CH5_AL1_WRITE_ADDR - [31:0] - read-write - - - - - CH5_AL1_TRANS_COUNT_TRIG - 0x0000015c - Alias for channel 5 TRANS_COUNT register - This is a trigger register (0xc). Writing a nonzero value will - reload the channel counter and start the channel. - 0x00000000 - - - CH5_AL1_TRANS_COUNT_TRIG - [31:0] - read-write - - - - - CH5_AL2_CTRL - 0x00000160 - Alias for channel 5 CTRL register - 0x00000000 - - - CH5_AL2_CTRL - [31:0] - read-write - - - - - CH5_AL2_TRANS_COUNT - 0x00000164 - Alias for channel 5 TRANS_COUNT register - 0x00000000 - - - CH5_AL2_TRANS_COUNT - [31:0] - read-write - - - - - CH5_AL2_READ_ADDR - 0x00000168 - Alias for channel 5 READ_ADDR register - 0x00000000 - - - CH5_AL2_READ_ADDR - [31:0] - read-write - - - - - CH5_AL2_WRITE_ADDR_TRIG - 0x0000016c - Alias for channel 5 WRITE_ADDR register - This is a trigger register (0xc). Writing a nonzero value will - reload the channel counter and start the channel. - 0x00000000 - - - CH5_AL2_WRITE_ADDR_TRIG - [31:0] - read-write - - - - - CH5_AL3_CTRL - 0x00000170 - Alias for channel 5 CTRL register - 0x00000000 - - - CH5_AL3_CTRL - [31:0] - read-write - - - - - CH5_AL3_WRITE_ADDR - 0x00000174 - Alias for channel 5 WRITE_ADDR register - 0x00000000 - - - CH5_AL3_WRITE_ADDR - [31:0] - read-write - - - - - CH5_AL3_TRANS_COUNT - 0x00000178 - Alias for channel 5 TRANS_COUNT register - 0x00000000 - - - CH5_AL3_TRANS_COUNT - [31:0] - read-write - - - - - CH5_AL3_READ_ADDR_TRIG - 0x0000017c - Alias for channel 5 READ_ADDR register - This is a trigger register (0xc). Writing a nonzero value will - reload the channel counter and start the channel. - 0x00000000 - - - CH5_AL3_READ_ADDR_TRIG - [31:0] - read-write - - - - - CH6_READ_ADDR - 0x00000180 - DMA Channel 6 Read Address pointer - 0x00000000 - - - CH6_READ_ADDR - This register updates automatically each time a read completes. The current value is the next address to be read by this channel. - [31:0] - read-write - - - - - CH6_WRITE_ADDR - 0x00000184 - DMA Channel 6 Write Address pointer - 0x00000000 - - - CH6_WRITE_ADDR - This register updates automatically each time a write completes. The current value is the next address to be written by this channel. - [31:0] - read-write - - - - - CH6_TRANS_COUNT - 0x00000188 - DMA Channel 6 Transfer Count - 0x00000000 - - - MODE - When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. - - When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. - - When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. - - All other values are reserved. - [31:28] - read-write - - - NORMAL - 0 - - - TRIGGER_SELF - 1 - - - ENDLESS - 15 - - - - - COUNT - 28-bit transfer count (256 million transfers maximum). - - Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). - - When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. - - Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. - - The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. - [27:0] - read-write - - - - - CH6_CTRL_TRIG - 0x0000018c - DMA Channel 6 Control and Status - 0x00000000 - - - AHB_ERROR - Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. - [31:31] - read-only - - - READ_ERROR - If 1, the channel received a read bus error. Write one to clear. - READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) - [30:30] - read-write - oneToClear - - - WRITE_ERROR - If 1, the channel received a write bus error. Write one to clear. - WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) - [29:29] - read-write - oneToClear - - - BUSY - This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. - - To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. - [26:26] - read-only - - - SNIFF_EN - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. - - This allows checksum to be enabled or disabled on a per-control- block basis. - [25:25] - read-write - - - BSWAP - Apply byte-swap transformation to DMA data. - For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. - [24:24] - read-write - - - IRQ_QUIET - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. - - This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. - [23:23] - read-write - - - TREQ_SEL - Select a Transfer Request signal. - The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). - 0x0 to 0x3a -> select DREQ n as TREQ - [22:17] - read-write - - - PIO0_TX0 - 0 - Select PIO0's TX FIFO 0 as TREQ - - - PIO0_TX1 - 1 - Select PIO0's TX FIFO 1 as TREQ - - - PIO0_TX2 - 2 - Select PIO0's TX FIFO 2 as TREQ - - - PIO0_TX3 - 3 - Select PIO0's TX FIFO 3 as TREQ - - - PIO0_RX0 - 4 - Select PIO0's RX FIFO 0 as TREQ - - - PIO0_RX1 - 5 - Select PIO0's RX FIFO 1 as TREQ - - - PIO0_RX2 - 6 - Select PIO0's RX FIFO 2 as TREQ - - - PIO0_RX3 - 7 - Select PIO0's RX FIFO 3 as TREQ - - - PIO1_TX0 - 8 - Select PIO1's TX FIFO 0 as TREQ - - - PIO1_TX1 - 9 - Select PIO1's TX FIFO 1 as TREQ - - - PIO1_TX2 - 10 - Select PIO1's TX FIFO 2 as TREQ - - - PIO1_TX3 - 11 - Select PIO1's TX FIFO 3 as TREQ - - - PIO1_RX0 - 12 - Select PIO1's RX FIFO 0 as TREQ - - - PIO1_RX1 - 13 - Select PIO1's RX FIFO 1 as TREQ - - - PIO1_RX2 - 14 - Select PIO1's RX FIFO 2 as TREQ - - - PIO1_RX3 - 15 - Select PIO1's RX FIFO 3 as TREQ - - - PIO2_TX0 - 16 - Select PIO2's TX FIFO 0 as TREQ - - - PIO2_TX1 - 17 - Select PIO2's TX FIFO 1 as TREQ - - - PIO2_TX2 - 18 - Select PIO2's TX FIFO 2 as TREQ - - - PIO2_TX3 - 19 - Select PIO2's TX FIFO 3 as TREQ - - - PIO2_RX0 - 20 - Select PIO2's RX FIFO 0 as TREQ - - - PIO2_RX1 - 21 - Select PIO2's RX FIFO 1 as TREQ - - - PIO2_RX2 - 22 - Select PIO2's RX FIFO 2 as TREQ - - - PIO2_RX3 - 23 - Select PIO2's RX FIFO 3 as TREQ - - - SPI0_TX - 24 - Select SPI0's TX FIFO as TREQ - - - SPI0_RX - 25 - Select SPI0's RX FIFO as TREQ - - - SPI1_TX - 26 - Select SPI1's TX FIFO as TREQ - - - SPI1_RX - 27 - Select SPI1's RX FIFO as TREQ - - - UART0_TX - 28 - Select UART0's TX FIFO as TREQ - - - UART0_RX - 29 - Select UART0's RX FIFO as TREQ - - - UART1_TX - 30 - Select UART1's TX FIFO as TREQ - - - UART1_RX - 31 - Select UART1's RX FIFO as TREQ - - - PWM_WRAP0 - 32 - Select PWM Counter 0's Wrap Value as TREQ - - - PWM_WRAP1 - 33 - Select PWM Counter 1's Wrap Value as TREQ - - - PWM_WRAP2 - 34 - Select PWM Counter 2's Wrap Value as TREQ - - - PWM_WRAP3 - 35 - Select PWM Counter 3's Wrap Value as TREQ - - - PWM_WRAP4 - 36 - Select PWM Counter 4's Wrap Value as TREQ - - - PWM_WRAP5 - 37 - Select PWM Counter 5's Wrap Value as TREQ - - - PWM_WRAP6 - 38 - Select PWM Counter 6's Wrap Value as TREQ - - - PWM_WRAP7 - 39 - Select PWM Counter 7's Wrap Value as TREQ - - - PWM_WRAP8 - 40 - Select PWM Counter 8's Wrap Value as TREQ - - - PWM_WRAP9 - 41 - Select PWM Counter 9's Wrap Value as TREQ - - - PWM_WRAP10 - 42 - Select PWM Counter 0's Wrap Value as TREQ - - - PWM_WRAP11 - 43 - Select PWM Counter 1's Wrap Value as TREQ - - - I2C0_TX - 44 - Select I2C0's TX FIFO as TREQ - - - I2C0_RX - 45 - Select I2C0's RX FIFO as TREQ - - - I2C1_TX - 46 - Select I2C1's TX FIFO as TREQ - - - I2C1_RX - 47 - Select I2C1's RX FIFO as TREQ - - - ADC - 48 - Select the ADC as TREQ - - - XIP_STREAM - 49 - Select the XIP Streaming FIFO as TREQ - - - XIP_QMITX - 50 - Select XIP_QMITX as TREQ - - - XIP_QMIRX - 51 - Select XIP_QMIRX as TREQ - - - HSTX - 52 - Select HSTX as TREQ - - - CORESIGHT - 53 - Select CORESIGHT as TREQ - - - SHA256 - 54 - Select SHA256 as TREQ - - - TIMER0 - 59 - Select Timer 0 as TREQ - - - TIMER1 - 60 - Select Timer 1 as TREQ - - - TIMER2 - 61 - Select Timer 2 as TREQ (Optional) - - - TIMER3 - 62 - Select Timer 3 as TREQ (Optional) - - - PERMANENT - 63 - Permanent request, for unpaced transfers. - - - - - CHAIN_TO - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. - - Note this field resets to 0, so channels 1 and above will chain to channel 0 by default. Set this field to avoid this behaviour. - [16:13] - read-write - - - RING_SEL - Select whether RING_SIZE applies to read or write addresses. - If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. - [12:12] - read-write - - - RING_SIZE - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. - - Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. - [11:8] - read-write - - - RING_NONE - 0 - - - - - INCR_WRITE_REV - If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer. - - If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. - [7:7] - read-write - - - INCR_WRITE - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. - - Generally this should be disabled for memory-to-peripheral transfers. - [6:6] - read-write - - - INCR_READ_REV - If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer. - - If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. - [5:5] - read-write - - - INCR_READ - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. - - Generally this should be disabled for peripheral-to-memory transfers. - [4:4] - read-write - - - DATA_SIZE - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. - [3:2] - read-write - - - SIZE_BYTE - 0 - - - SIZE_HALFWORD - 1 - - - SIZE_WORD - 2 - - - - - HIGH_PRIORITY - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. - - This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. - [1:1] - read-write - - - EN - DMA Channel Enable. - When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) - [0:0] - read-write - - - - - CH6_AL1_CTRL - 0x00000190 - Alias for channel 6 CTRL register - 0x00000000 - - - CH6_AL1_CTRL - [31:0] - read-write - - - - - CH6_AL1_READ_ADDR - 0x00000194 - Alias for channel 6 READ_ADDR register - 0x00000000 - - - CH6_AL1_READ_ADDR - [31:0] - read-write - - - - - CH6_AL1_WRITE_ADDR - 0x00000198 - Alias for channel 6 WRITE_ADDR register - 0x00000000 - - - CH6_AL1_WRITE_ADDR - [31:0] - read-write - - - - - CH6_AL1_TRANS_COUNT_TRIG - 0x0000019c - Alias for channel 6 TRANS_COUNT register - This is a trigger register (0xc). Writing a nonzero value will - reload the channel counter and start the channel. - 0x00000000 - - - CH6_AL1_TRANS_COUNT_TRIG - [31:0] - read-write - - - - - CH6_AL2_CTRL - 0x000001a0 - Alias for channel 6 CTRL register - 0x00000000 - - - CH6_AL2_CTRL - [31:0] - read-write - - - - - CH6_AL2_TRANS_COUNT - 0x000001a4 - Alias for channel 6 TRANS_COUNT register - 0x00000000 - - - CH6_AL2_TRANS_COUNT - [31:0] - read-write - - - - - CH6_AL2_READ_ADDR - 0x000001a8 - Alias for channel 6 READ_ADDR register - 0x00000000 - - - CH6_AL2_READ_ADDR - [31:0] - read-write - - - - - CH6_AL2_WRITE_ADDR_TRIG - 0x000001ac - Alias for channel 6 WRITE_ADDR register - This is a trigger register (0xc). Writing a nonzero value will - reload the channel counter and start the channel. - 0x00000000 - - - CH6_AL2_WRITE_ADDR_TRIG - [31:0] - read-write - - - - - CH6_AL3_CTRL - 0x000001b0 - Alias for channel 6 CTRL register - 0x00000000 - - - CH6_AL3_CTRL - [31:0] - read-write - - - - - CH6_AL3_WRITE_ADDR - 0x000001b4 - Alias for channel 6 WRITE_ADDR register - 0x00000000 - - - CH6_AL3_WRITE_ADDR - [31:0] - read-write - - - - - CH6_AL3_TRANS_COUNT - 0x000001b8 - Alias for channel 6 TRANS_COUNT register - 0x00000000 - - - CH6_AL3_TRANS_COUNT - [31:0] - read-write - - - - - CH6_AL3_READ_ADDR_TRIG - 0x000001bc - Alias for channel 6 READ_ADDR register - This is a trigger register (0xc). Writing a nonzero value will - reload the channel counter and start the channel. - 0x00000000 - - - CH6_AL3_READ_ADDR_TRIG - [31:0] - read-write - - - - - CH7_READ_ADDR - 0x000001c0 - DMA Channel 7 Read Address pointer - 0x00000000 - - - CH7_READ_ADDR - This register updates automatically each time a read completes. The current value is the next address to be read by this channel. - [31:0] - read-write - - - - - CH7_WRITE_ADDR - 0x000001c4 - DMA Channel 7 Write Address pointer - 0x00000000 - - - CH7_WRITE_ADDR - This register updates automatically each time a write completes. The current value is the next address to be written by this channel. - [31:0] - read-write - - - - - CH7_TRANS_COUNT - 0x000001c8 - DMA Channel 7 Transfer Count - 0x00000000 - - - MODE - When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. - - When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. - - When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. - - All other values are reserved. - [31:28] - read-write - - - NORMAL - 0 - - - TRIGGER_SELF - 1 - - - ENDLESS - 15 - - - - - COUNT - 28-bit transfer count (256 million transfers maximum). - - Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). - - When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. - - Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. - - The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. - [27:0] - read-write - - - - - CH7_CTRL_TRIG - 0x000001cc - DMA Channel 7 Control and Status - 0x00000000 - - - AHB_ERROR - Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. - [31:31] - read-only - - - READ_ERROR - If 1, the channel received a read bus error. Write one to clear. - READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) - [30:30] - read-write - oneToClear - - - WRITE_ERROR - If 1, the channel received a write bus error. Write one to clear. - WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) - [29:29] - read-write - oneToClear - - - BUSY - This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. - - To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. - [26:26] - read-only - - - SNIFF_EN - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. - - This allows checksum to be enabled or disabled on a per-control- block basis. - [25:25] - read-write - - - BSWAP - Apply byte-swap transformation to DMA data. - For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. - [24:24] - read-write - - - IRQ_QUIET - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. - - This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. - [23:23] - read-write - - - TREQ_SEL - Select a Transfer Request signal. - The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). - 0x0 to 0x3a -> select DREQ n as TREQ - [22:17] - read-write - - - PIO0_TX0 - 0 - Select PIO0's TX FIFO 0 as TREQ - - - PIO0_TX1 - 1 - Select PIO0's TX FIFO 1 as TREQ - - - PIO0_TX2 - 2 - Select PIO0's TX FIFO 2 as TREQ - - - PIO0_TX3 - 3 - Select PIO0's TX FIFO 3 as TREQ - - - PIO0_RX0 - 4 - Select PIO0's RX FIFO 0 as TREQ - - - PIO0_RX1 - 5 - Select PIO0's RX FIFO 1 as TREQ - - - PIO0_RX2 - 6 - Select PIO0's RX FIFO 2 as TREQ - - - PIO0_RX3 - 7 - Select PIO0's RX FIFO 3 as TREQ - - - PIO1_TX0 - 8 - Select PIO1's TX FIFO 0 as TREQ - - - PIO1_TX1 - 9 - Select PIO1's TX FIFO 1 as TREQ - - - PIO1_TX2 - 10 - Select PIO1's TX FIFO 2 as TREQ - - - PIO1_TX3 - 11 - Select PIO1's TX FIFO 3 as TREQ - - - PIO1_RX0 - 12 - Select PIO1's RX FIFO 0 as TREQ - - - PIO1_RX1 - 13 - Select PIO1's RX FIFO 1 as TREQ - - - PIO1_RX2 - 14 - Select PIO1's RX FIFO 2 as TREQ - - - PIO1_RX3 - 15 - Select PIO1's RX FIFO 3 as TREQ - - - PIO2_TX0 - 16 - Select PIO2's TX FIFO 0 as TREQ - - - PIO2_TX1 - 17 - Select PIO2's TX FIFO 1 as TREQ - - - PIO2_TX2 - 18 - Select PIO2's TX FIFO 2 as TREQ - - - PIO2_TX3 - 19 - Select PIO2's TX FIFO 3 as TREQ - - - PIO2_RX0 - 20 - Select PIO2's RX FIFO 0 as TREQ - - - PIO2_RX1 - 21 - Select PIO2's RX FIFO 1 as TREQ - - - PIO2_RX2 - 22 - Select PIO2's RX FIFO 2 as TREQ - - - PIO2_RX3 - 23 - Select PIO2's RX FIFO 3 as TREQ - - - SPI0_TX - 24 - Select SPI0's TX FIFO as TREQ - - - SPI0_RX - 25 - Select SPI0's RX FIFO as TREQ - - - SPI1_TX - 26 - Select SPI1's TX FIFO as TREQ - - - SPI1_RX - 27 - Select SPI1's RX FIFO as TREQ - - - UART0_TX - 28 - Select UART0's TX FIFO as TREQ - - - UART0_RX - 29 - Select UART0's RX FIFO as TREQ - - - UART1_TX - 30 - Select UART1's TX FIFO as TREQ - - - UART1_RX - 31 - Select UART1's RX FIFO as TREQ - - - PWM_WRAP0 - 32 - Select PWM Counter 0's Wrap Value as TREQ - - - PWM_WRAP1 - 33 - Select PWM Counter 1's Wrap Value as TREQ - - - PWM_WRAP2 - 34 - Select PWM Counter 2's Wrap Value as TREQ - - - PWM_WRAP3 - 35 - Select PWM Counter 3's Wrap Value as TREQ - - - PWM_WRAP4 - 36 - Select PWM Counter 4's Wrap Value as TREQ - - - PWM_WRAP5 - 37 - Select PWM Counter 5's Wrap Value as TREQ - - - PWM_WRAP6 - 38 - Select PWM Counter 6's Wrap Value as TREQ - - - PWM_WRAP7 - 39 - Select PWM Counter 7's Wrap Value as TREQ - - - PWM_WRAP8 - 40 - Select PWM Counter 8's Wrap Value as TREQ - - - PWM_WRAP9 - 41 - Select PWM Counter 9's Wrap Value as TREQ - - - PWM_WRAP10 - 42 - Select PWM Counter 0's Wrap Value as TREQ - - - PWM_WRAP11 - 43 - Select PWM Counter 1's Wrap Value as TREQ - - - I2C0_TX - 44 - Select I2C0's TX FIFO as TREQ - - - I2C0_RX - 45 - Select I2C0's RX FIFO as TREQ - - - I2C1_TX - 46 - Select I2C1's TX FIFO as TREQ - - - I2C1_RX - 47 - Select I2C1's RX FIFO as TREQ - - - ADC - 48 - Select the ADC as TREQ - - - XIP_STREAM - 49 - Select the XIP Streaming FIFO as TREQ - - - XIP_QMITX - 50 - Select XIP_QMITX as TREQ - - - XIP_QMIRX - 51 - Select XIP_QMIRX as TREQ - - - HSTX - 52 - Select HSTX as TREQ - - - CORESIGHT - 53 - Select CORESIGHT as TREQ - - - SHA256 - 54 - Select SHA256 as TREQ - - - TIMER0 - 59 - Select Timer 0 as TREQ - - - TIMER1 - 60 - Select Timer 1 as TREQ - - - TIMER2 - 61 - Select Timer 2 as TREQ (Optional) - - - TIMER3 - 62 - Select Timer 3 as TREQ (Optional) - - - PERMANENT - 63 - Permanent request, for unpaced transfers. - - - - - CHAIN_TO - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. - - Note this field resets to 0, so channels 1 and above will chain to channel 0 by default. Set this field to avoid this behaviour. - [16:13] - read-write - - - RING_SEL - Select whether RING_SIZE applies to read or write addresses. - If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. - [12:12] - read-write - - - RING_SIZE - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. - - Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. - [11:8] - read-write - - - RING_NONE - 0 - - - - - INCR_WRITE_REV - If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer. - - If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. - [7:7] - read-write - - - INCR_WRITE - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. - - Generally this should be disabled for memory-to-peripheral transfers. - [6:6] - read-write - - - INCR_READ_REV - If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer. - - If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. - [5:5] - read-write - - - INCR_READ - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. - - Generally this should be disabled for peripheral-to-memory transfers. - [4:4] - read-write - - - DATA_SIZE - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. - [3:2] - read-write - - - SIZE_BYTE - 0 - - - SIZE_HALFWORD - 1 - - - SIZE_WORD - 2 - - - - - HIGH_PRIORITY - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. - - This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. - [1:1] - read-write - - - EN - DMA Channel Enable. - When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) - [0:0] - read-write - - - - - CH7_AL1_CTRL - 0x000001d0 - Alias for channel 7 CTRL register - 0x00000000 - - - CH7_AL1_CTRL - [31:0] - read-write - - - - - CH7_AL1_READ_ADDR - 0x000001d4 - Alias for channel 7 READ_ADDR register - 0x00000000 - - - CH7_AL1_READ_ADDR - [31:0] - read-write - - - - - CH7_AL1_WRITE_ADDR - 0x000001d8 - Alias for channel 7 WRITE_ADDR register - 0x00000000 - - - CH7_AL1_WRITE_ADDR - [31:0] - read-write - - - - - CH7_AL1_TRANS_COUNT_TRIG - 0x000001dc - Alias for channel 7 TRANS_COUNT register - This is a trigger register (0xc). Writing a nonzero value will - reload the channel counter and start the channel. - 0x00000000 - - - CH7_AL1_TRANS_COUNT_TRIG - [31:0] - read-write - - - - - CH7_AL2_CTRL - 0x000001e0 - Alias for channel 7 CTRL register - 0x00000000 - - - CH7_AL2_CTRL - [31:0] - read-write - - - - - CH7_AL2_TRANS_COUNT - 0x000001e4 - Alias for channel 7 TRANS_COUNT register - 0x00000000 - - - CH7_AL2_TRANS_COUNT - [31:0] - read-write - - - - - CH7_AL2_READ_ADDR - 0x000001e8 - Alias for channel 7 READ_ADDR register - 0x00000000 - - - CH7_AL2_READ_ADDR - [31:0] - read-write - - - - - CH7_AL2_WRITE_ADDR_TRIG - 0x000001ec - Alias for channel 7 WRITE_ADDR register - This is a trigger register (0xc). Writing a nonzero value will - reload the channel counter and start the channel. - 0x00000000 - - - CH7_AL2_WRITE_ADDR_TRIG - [31:0] - read-write - - - - - CH7_AL3_CTRL - 0x000001f0 - Alias for channel 7 CTRL register - 0x00000000 - - - CH7_AL3_CTRL - [31:0] - read-write - - - - - CH7_AL3_WRITE_ADDR - 0x000001f4 - Alias for channel 7 WRITE_ADDR register - 0x00000000 - - - CH7_AL3_WRITE_ADDR - [31:0] - read-write - - - - - CH7_AL3_TRANS_COUNT - 0x000001f8 - Alias for channel 7 TRANS_COUNT register - 0x00000000 - - - CH7_AL3_TRANS_COUNT - [31:0] - read-write - - - - - CH7_AL3_READ_ADDR_TRIG - 0x000001fc - Alias for channel 7 READ_ADDR register - This is a trigger register (0xc). Writing a nonzero value will - reload the channel counter and start the channel. - 0x00000000 - - - CH7_AL3_READ_ADDR_TRIG - [31:0] - read-write - - - - - CH8_READ_ADDR - 0x00000200 - DMA Channel 8 Read Address pointer - 0x00000000 - - - CH8_READ_ADDR - This register updates automatically each time a read completes. The current value is the next address to be read by this channel. - [31:0] - read-write - - - - - CH8_WRITE_ADDR - 0x00000204 - DMA Channel 8 Write Address pointer - 0x00000000 - - - CH8_WRITE_ADDR - This register updates automatically each time a write completes. The current value is the next address to be written by this channel. - [31:0] - read-write - - - - - CH8_TRANS_COUNT - 0x00000208 - DMA Channel 8 Transfer Count - 0x00000000 - - - MODE - When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. - - When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. - - When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. - - All other values are reserved. - [31:28] - read-write - - - NORMAL - 0 - - - TRIGGER_SELF - 1 - - - ENDLESS - 15 - - - - - COUNT - 28-bit transfer count (256 million transfers maximum). - - Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). - - When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. - - Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. - - The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. - [27:0] - read-write - - - - - CH8_CTRL_TRIG - 0x0000020c - DMA Channel 8 Control and Status - 0x00000000 - - - AHB_ERROR - Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. - [31:31] - read-only - - - READ_ERROR - If 1, the channel received a read bus error. Write one to clear. - READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) - [30:30] - read-write - oneToClear - - - WRITE_ERROR - If 1, the channel received a write bus error. Write one to clear. - WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) - [29:29] - read-write - oneToClear - - - BUSY - This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. - - To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. - [26:26] - read-only - - - SNIFF_EN - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. - - This allows checksum to be enabled or disabled on a per-control- block basis. - [25:25] - read-write - - - BSWAP - Apply byte-swap transformation to DMA data. - For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. - [24:24] - read-write - - - IRQ_QUIET - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. - - This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. - [23:23] - read-write - - - TREQ_SEL - Select a Transfer Request signal. - The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). - 0x0 to 0x3a -> select DREQ n as TREQ - [22:17] - read-write - - - PIO0_TX0 - 0 - Select PIO0's TX FIFO 0 as TREQ - - - PIO0_TX1 - 1 - Select PIO0's TX FIFO 1 as TREQ - - - PIO0_TX2 - 2 - Select PIO0's TX FIFO 2 as TREQ - - - PIO0_TX3 - 3 - Select PIO0's TX FIFO 3 as TREQ - - - PIO0_RX0 - 4 - Select PIO0's RX FIFO 0 as TREQ - - - PIO0_RX1 - 5 - Select PIO0's RX FIFO 1 as TREQ - - - PIO0_RX2 - 6 - Select PIO0's RX FIFO 2 as TREQ - - - PIO0_RX3 - 7 - Select PIO0's RX FIFO 3 as TREQ - - - PIO1_TX0 - 8 - Select PIO1's TX FIFO 0 as TREQ - - - PIO1_TX1 - 9 - Select PIO1's TX FIFO 1 as TREQ - - - PIO1_TX2 - 10 - Select PIO1's TX FIFO 2 as TREQ - - - PIO1_TX3 - 11 - Select PIO1's TX FIFO 3 as TREQ - - - PIO1_RX0 - 12 - Select PIO1's RX FIFO 0 as TREQ - - - PIO1_RX1 - 13 - Select PIO1's RX FIFO 1 as TREQ - - - PIO1_RX2 - 14 - Select PIO1's RX FIFO 2 as TREQ - - - PIO1_RX3 - 15 - Select PIO1's RX FIFO 3 as TREQ - - - PIO2_TX0 - 16 - Select PIO2's TX FIFO 0 as TREQ - - - PIO2_TX1 - 17 - Select PIO2's TX FIFO 1 as TREQ - - - PIO2_TX2 - 18 - Select PIO2's TX FIFO 2 as TREQ - - - PIO2_TX3 - 19 - Select PIO2's TX FIFO 3 as TREQ - - - PIO2_RX0 - 20 - Select PIO2's RX FIFO 0 as TREQ - - - PIO2_RX1 - 21 - Select PIO2's RX FIFO 1 as TREQ - - - PIO2_RX2 - 22 - Select PIO2's RX FIFO 2 as TREQ - - - PIO2_RX3 - 23 - Select PIO2's RX FIFO 3 as TREQ - - - SPI0_TX - 24 - Select SPI0's TX FIFO as TREQ - - - SPI0_RX - 25 - Select SPI0's RX FIFO as TREQ - - - SPI1_TX - 26 - Select SPI1's TX FIFO as TREQ - - - SPI1_RX - 27 - Select SPI1's RX FIFO as TREQ - - - UART0_TX - 28 - Select UART0's TX FIFO as TREQ - - - UART0_RX - 29 - Select UART0's RX FIFO as TREQ - - - UART1_TX - 30 - Select UART1's TX FIFO as TREQ - - - UART1_RX - 31 - Select UART1's RX FIFO as TREQ - - - PWM_WRAP0 - 32 - Select PWM Counter 0's Wrap Value as TREQ - - - PWM_WRAP1 - 33 - Select PWM Counter 1's Wrap Value as TREQ - - - PWM_WRAP2 - 34 - Select PWM Counter 2's Wrap Value as TREQ - - - PWM_WRAP3 - 35 - Select PWM Counter 3's Wrap Value as TREQ - - - PWM_WRAP4 - 36 - Select PWM Counter 4's Wrap Value as TREQ - - - PWM_WRAP5 - 37 - Select PWM Counter 5's Wrap Value as TREQ - - - PWM_WRAP6 - 38 - Select PWM Counter 6's Wrap Value as TREQ - - - PWM_WRAP7 - 39 - Select PWM Counter 7's Wrap Value as TREQ - - - PWM_WRAP8 - 40 - Select PWM Counter 8's Wrap Value as TREQ - - - PWM_WRAP9 - 41 - Select PWM Counter 9's Wrap Value as TREQ - - - PWM_WRAP10 - 42 - Select PWM Counter 0's Wrap Value as TREQ - - - PWM_WRAP11 - 43 - Select PWM Counter 1's Wrap Value as TREQ - - - I2C0_TX - 44 - Select I2C0's TX FIFO as TREQ - - - I2C0_RX - 45 - Select I2C0's RX FIFO as TREQ - - - I2C1_TX - 46 - Select I2C1's TX FIFO as TREQ - - - I2C1_RX - 47 - Select I2C1's RX FIFO as TREQ - - - ADC - 48 - Select the ADC as TREQ - - - XIP_STREAM - 49 - Select the XIP Streaming FIFO as TREQ - - - XIP_QMITX - 50 - Select XIP_QMITX as TREQ - - - XIP_QMIRX - 51 - Select XIP_QMIRX as TREQ - - - HSTX - 52 - Select HSTX as TREQ - - - CORESIGHT - 53 - Select CORESIGHT as TREQ - - - SHA256 - 54 - Select SHA256 as TREQ - - - TIMER0 - 59 - Select Timer 0 as TREQ - - - TIMER1 - 60 - Select Timer 1 as TREQ - - - TIMER2 - 61 - Select Timer 2 as TREQ (Optional) - - - TIMER3 - 62 - Select Timer 3 as TREQ (Optional) - - - PERMANENT - 63 - Permanent request, for unpaced transfers. - - - - - CHAIN_TO - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. - - Note this field resets to 0, so channels 1 and above will chain to channel 0 by default. Set this field to avoid this behaviour. - [16:13] - read-write - - - RING_SEL - Select whether RING_SIZE applies to read or write addresses. - If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. - [12:12] - read-write - - - RING_SIZE - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. - - Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. - [11:8] - read-write - - - RING_NONE - 0 - - - - - INCR_WRITE_REV - If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer. - - If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. - [7:7] - read-write - - - INCR_WRITE - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. - - Generally this should be disabled for memory-to-peripheral transfers. - [6:6] - read-write - - - INCR_READ_REV - If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer. - - If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. - [5:5] - read-write - - - INCR_READ - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. - - Generally this should be disabled for peripheral-to-memory transfers. - [4:4] - read-write - - - DATA_SIZE - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. - [3:2] - read-write - - - SIZE_BYTE - 0 - - - SIZE_HALFWORD - 1 - - - SIZE_WORD - 2 - - - - - HIGH_PRIORITY - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. - - This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. - [1:1] - read-write - - - EN - DMA Channel Enable. - When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) - [0:0] - read-write - - - - - CH8_AL1_CTRL - 0x00000210 - Alias for channel 8 CTRL register - 0x00000000 - - - CH8_AL1_CTRL - [31:0] - read-write - - - - - CH8_AL1_READ_ADDR - 0x00000214 - Alias for channel 8 READ_ADDR register - 0x00000000 - - - CH8_AL1_READ_ADDR - [31:0] - read-write - - - - - CH8_AL1_WRITE_ADDR - 0x00000218 - Alias for channel 8 WRITE_ADDR register - 0x00000000 - - - CH8_AL1_WRITE_ADDR - [31:0] - read-write - - - - - CH8_AL1_TRANS_COUNT_TRIG - 0x0000021c - Alias for channel 8 TRANS_COUNT register - This is a trigger register (0xc). Writing a nonzero value will - reload the channel counter and start the channel. - 0x00000000 - - - CH8_AL1_TRANS_COUNT_TRIG - [31:0] - read-write - - - - - CH8_AL2_CTRL - 0x00000220 - Alias for channel 8 CTRL register - 0x00000000 - - - CH8_AL2_CTRL - [31:0] - read-write - - - - - CH8_AL2_TRANS_COUNT - 0x00000224 - Alias for channel 8 TRANS_COUNT register - 0x00000000 - - - CH8_AL2_TRANS_COUNT - [31:0] - read-write - - - - - CH8_AL2_READ_ADDR - 0x00000228 - Alias for channel 8 READ_ADDR register - 0x00000000 - - - CH8_AL2_READ_ADDR - [31:0] - read-write - - - - - CH8_AL2_WRITE_ADDR_TRIG - 0x0000022c - Alias for channel 8 WRITE_ADDR register - This is a trigger register (0xc). Writing a nonzero value will - reload the channel counter and start the channel. - 0x00000000 - - - CH8_AL2_WRITE_ADDR_TRIG - [31:0] - read-write - - - - - CH8_AL3_CTRL - 0x00000230 - Alias for channel 8 CTRL register - 0x00000000 - - - CH8_AL3_CTRL - [31:0] - read-write - - - - - CH8_AL3_WRITE_ADDR - 0x00000234 - Alias for channel 8 WRITE_ADDR register - 0x00000000 - - - CH8_AL3_WRITE_ADDR - [31:0] - read-write - - - - - CH8_AL3_TRANS_COUNT - 0x00000238 - Alias for channel 8 TRANS_COUNT register - 0x00000000 - - - CH8_AL3_TRANS_COUNT - [31:0] - read-write - - - - - CH8_AL3_READ_ADDR_TRIG - 0x0000023c - Alias for channel 8 READ_ADDR register - This is a trigger register (0xc). Writing a nonzero value will - reload the channel counter and start the channel. - 0x00000000 - - - CH8_AL3_READ_ADDR_TRIG - [31:0] - read-write - - - - - CH9_READ_ADDR - 0x00000240 - DMA Channel 9 Read Address pointer - 0x00000000 - - - CH9_READ_ADDR - This register updates automatically each time a read completes. The current value is the next address to be read by this channel. - [31:0] - read-write - - - - - CH9_WRITE_ADDR - 0x00000244 - DMA Channel 9 Write Address pointer - 0x00000000 - - - CH9_WRITE_ADDR - This register updates automatically each time a write completes. The current value is the next address to be written by this channel. - [31:0] - read-write - - - - - CH9_TRANS_COUNT - 0x00000248 - DMA Channel 9 Transfer Count - 0x00000000 - - - MODE - When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. - - When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. - - When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. - - All other values are reserved. - [31:28] - read-write - - - NORMAL - 0 - - - TRIGGER_SELF - 1 - - - ENDLESS - 15 - - - - - COUNT - 28-bit transfer count (256 million transfers maximum). - - Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). - - When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. - - Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. - - The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. - [27:0] - read-write - - - - - CH9_CTRL_TRIG - 0x0000024c - DMA Channel 9 Control and Status - 0x00000000 - - - AHB_ERROR - Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. - [31:31] - read-only - - - READ_ERROR - If 1, the channel received a read bus error. Write one to clear. - READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) - [30:30] - read-write - oneToClear - - - WRITE_ERROR - If 1, the channel received a write bus error. Write one to clear. - WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) - [29:29] - read-write - oneToClear - - - BUSY - This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. - - To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. - [26:26] - read-only - - - SNIFF_EN - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. - - This allows checksum to be enabled or disabled on a per-control- block basis. - [25:25] - read-write - - - BSWAP - Apply byte-swap transformation to DMA data. - For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. - [24:24] - read-write - - - IRQ_QUIET - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. - - This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. - [23:23] - read-write - - - TREQ_SEL - Select a Transfer Request signal. - The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). - 0x0 to 0x3a -> select DREQ n as TREQ - [22:17] - read-write - - - PIO0_TX0 - 0 - Select PIO0's TX FIFO 0 as TREQ - - - PIO0_TX1 - 1 - Select PIO0's TX FIFO 1 as TREQ - - - PIO0_TX2 - 2 - Select PIO0's TX FIFO 2 as TREQ - - - PIO0_TX3 - 3 - Select PIO0's TX FIFO 3 as TREQ - - - PIO0_RX0 - 4 - Select PIO0's RX FIFO 0 as TREQ - - - PIO0_RX1 - 5 - Select PIO0's RX FIFO 1 as TREQ - - - PIO0_RX2 - 6 - Select PIO0's RX FIFO 2 as TREQ - - - PIO0_RX3 - 7 - Select PIO0's RX FIFO 3 as TREQ - - - PIO1_TX0 - 8 - Select PIO1's TX FIFO 0 as TREQ - - - PIO1_TX1 - 9 - Select PIO1's TX FIFO 1 as TREQ - - - PIO1_TX2 - 10 - Select PIO1's TX FIFO 2 as TREQ - - - PIO1_TX3 - 11 - Select PIO1's TX FIFO 3 as TREQ - - - PIO1_RX0 - 12 - Select PIO1's RX FIFO 0 as TREQ - - - PIO1_RX1 - 13 - Select PIO1's RX FIFO 1 as TREQ - - - PIO1_RX2 - 14 - Select PIO1's RX FIFO 2 as TREQ - - - PIO1_RX3 - 15 - Select PIO1's RX FIFO 3 as TREQ - - - PIO2_TX0 - 16 - Select PIO2's TX FIFO 0 as TREQ - - - PIO2_TX1 - 17 - Select PIO2's TX FIFO 1 as TREQ - - - PIO2_TX2 - 18 - Select PIO2's TX FIFO 2 as TREQ - - - PIO2_TX3 - 19 - Select PIO2's TX FIFO 3 as TREQ - - - PIO2_RX0 - 20 - Select PIO2's RX FIFO 0 as TREQ - - - PIO2_RX1 - 21 - Select PIO2's RX FIFO 1 as TREQ - - - PIO2_RX2 - 22 - Select PIO2's RX FIFO 2 as TREQ - - - PIO2_RX3 - 23 - Select PIO2's RX FIFO 3 as TREQ - - - SPI0_TX - 24 - Select SPI0's TX FIFO as TREQ - - - SPI0_RX - 25 - Select SPI0's RX FIFO as TREQ - - - SPI1_TX - 26 - Select SPI1's TX FIFO as TREQ - - - SPI1_RX - 27 - Select SPI1's RX FIFO as TREQ - - - UART0_TX - 28 - Select UART0's TX FIFO as TREQ - - - UART0_RX - 29 - Select UART0's RX FIFO as TREQ - - - UART1_TX - 30 - Select UART1's TX FIFO as TREQ - - - UART1_RX - 31 - Select UART1's RX FIFO as TREQ - - - PWM_WRAP0 - 32 - Select PWM Counter 0's Wrap Value as TREQ - - - PWM_WRAP1 - 33 - Select PWM Counter 1's Wrap Value as TREQ - - - PWM_WRAP2 - 34 - Select PWM Counter 2's Wrap Value as TREQ - - - PWM_WRAP3 - 35 - Select PWM Counter 3's Wrap Value as TREQ - - - PWM_WRAP4 - 36 - Select PWM Counter 4's Wrap Value as TREQ - - - PWM_WRAP5 - 37 - Select PWM Counter 5's Wrap Value as TREQ - - - PWM_WRAP6 - 38 - Select PWM Counter 6's Wrap Value as TREQ - - - PWM_WRAP7 - 39 - Select PWM Counter 7's Wrap Value as TREQ - - - PWM_WRAP8 - 40 - Select PWM Counter 8's Wrap Value as TREQ - - - PWM_WRAP9 - 41 - Select PWM Counter 9's Wrap Value as TREQ - - - PWM_WRAP10 - 42 - Select PWM Counter 0's Wrap Value as TREQ - - - PWM_WRAP11 - 43 - Select PWM Counter 1's Wrap Value as TREQ - - - I2C0_TX - 44 - Select I2C0's TX FIFO as TREQ - - - I2C0_RX - 45 - Select I2C0's RX FIFO as TREQ - - - I2C1_TX - 46 - Select I2C1's TX FIFO as TREQ - - - I2C1_RX - 47 - Select I2C1's RX FIFO as TREQ - - - ADC - 48 - Select the ADC as TREQ - - - XIP_STREAM - 49 - Select the XIP Streaming FIFO as TREQ - - - XIP_QMITX - 50 - Select XIP_QMITX as TREQ - - - XIP_QMIRX - 51 - Select XIP_QMIRX as TREQ - - - HSTX - 52 - Select HSTX as TREQ - - - CORESIGHT - 53 - Select CORESIGHT as TREQ - - - SHA256 - 54 - Select SHA256 as TREQ - - - TIMER0 - 59 - Select Timer 0 as TREQ - - - TIMER1 - 60 - Select Timer 1 as TREQ - - - TIMER2 - 61 - Select Timer 2 as TREQ (Optional) - - - TIMER3 - 62 - Select Timer 3 as TREQ (Optional) - - - PERMANENT - 63 - Permanent request, for unpaced transfers. - - - - - CHAIN_TO - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. - - Note this field resets to 0, so channels 1 and above will chain to channel 0 by default. Set this field to avoid this behaviour. - [16:13] - read-write - - - RING_SEL - Select whether RING_SIZE applies to read or write addresses. - If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. - [12:12] - read-write - - - RING_SIZE - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. - - Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. - [11:8] - read-write - - - RING_NONE - 0 - - - - - INCR_WRITE_REV - If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer. - - If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. - [7:7] - read-write - - - INCR_WRITE - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. - - Generally this should be disabled for memory-to-peripheral transfers. - [6:6] - read-write - - - INCR_READ_REV - If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer. - - If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. - [5:5] - read-write - - - INCR_READ - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. - - Generally this should be disabled for peripheral-to-memory transfers. - [4:4] - read-write - - - DATA_SIZE - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. - [3:2] - read-write - - - SIZE_BYTE - 0 - - - SIZE_HALFWORD - 1 - - - SIZE_WORD - 2 - - - - - HIGH_PRIORITY - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. - - This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. - [1:1] - read-write - - - EN - DMA Channel Enable. - When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) - [0:0] - read-write - - - - - CH9_AL1_CTRL - 0x00000250 - Alias for channel 9 CTRL register - 0x00000000 - - - CH9_AL1_CTRL - [31:0] - read-write - - - - - CH9_AL1_READ_ADDR - 0x00000254 - Alias for channel 9 READ_ADDR register - 0x00000000 - - - CH9_AL1_READ_ADDR - [31:0] - read-write - - - - - CH9_AL1_WRITE_ADDR - 0x00000258 - Alias for channel 9 WRITE_ADDR register - 0x00000000 - - - CH9_AL1_WRITE_ADDR - [31:0] - read-write - - - - - CH9_AL1_TRANS_COUNT_TRIG - 0x0000025c - Alias for channel 9 TRANS_COUNT register - This is a trigger register (0xc). Writing a nonzero value will - reload the channel counter and start the channel. - 0x00000000 - - - CH9_AL1_TRANS_COUNT_TRIG - [31:0] - read-write - - - - - CH9_AL2_CTRL - 0x00000260 - Alias for channel 9 CTRL register - 0x00000000 - - - CH9_AL2_CTRL - [31:0] - read-write - - - - - CH9_AL2_TRANS_COUNT - 0x00000264 - Alias for channel 9 TRANS_COUNT register - 0x00000000 - - - CH9_AL2_TRANS_COUNT - [31:0] - read-write - - - - - CH9_AL2_READ_ADDR - 0x00000268 - Alias for channel 9 READ_ADDR register - 0x00000000 - - - CH9_AL2_READ_ADDR - [31:0] - read-write - - - - - CH9_AL2_WRITE_ADDR_TRIG - 0x0000026c - Alias for channel 9 WRITE_ADDR register - This is a trigger register (0xc). Writing a nonzero value will - reload the channel counter and start the channel. - 0x00000000 - - - CH9_AL2_WRITE_ADDR_TRIG - [31:0] - read-write - - - - - CH9_AL3_CTRL - 0x00000270 - Alias for channel 9 CTRL register - 0x00000000 - - - CH9_AL3_CTRL - [31:0] - read-write - - - - - CH9_AL3_WRITE_ADDR - 0x00000274 - Alias for channel 9 WRITE_ADDR register - 0x00000000 - - - CH9_AL3_WRITE_ADDR - [31:0] - read-write - - - - - CH9_AL3_TRANS_COUNT - 0x00000278 - Alias for channel 9 TRANS_COUNT register - 0x00000000 - - - CH9_AL3_TRANS_COUNT - [31:0] - read-write - - - - - CH9_AL3_READ_ADDR_TRIG - 0x0000027c - Alias for channel 9 READ_ADDR register - This is a trigger register (0xc). Writing a nonzero value will - reload the channel counter and start the channel. - 0x00000000 - - - CH9_AL3_READ_ADDR_TRIG - [31:0] - read-write - - - - - CH10_READ_ADDR - 0x00000280 - DMA Channel 10 Read Address pointer - 0x00000000 - - - CH10_READ_ADDR - This register updates automatically each time a read completes. The current value is the next address to be read by this channel. - [31:0] - read-write - - - - - CH10_WRITE_ADDR - 0x00000284 - DMA Channel 10 Write Address pointer - 0x00000000 - - - CH10_WRITE_ADDR - This register updates automatically each time a write completes. The current value is the next address to be written by this channel. - [31:0] - read-write - - - - - CH10_TRANS_COUNT - 0x00000288 - DMA Channel 10 Transfer Count - 0x00000000 - - - MODE - When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. - - When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. - - When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. - - All other values are reserved. - [31:28] - read-write - - - NORMAL - 0 - - - TRIGGER_SELF - 1 - - - ENDLESS - 15 - - - - - COUNT - 28-bit transfer count (256 million transfers maximum). - - Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). - - When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. - - Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. - - The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. - [27:0] - read-write - - - - - CH10_CTRL_TRIG - 0x0000028c - DMA Channel 10 Control and Status - 0x00000000 - - - AHB_ERROR - Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. - [31:31] - read-only - - - READ_ERROR - If 1, the channel received a read bus error. Write one to clear. - READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) - [30:30] - read-write - oneToClear - - - WRITE_ERROR - If 1, the channel received a write bus error. Write one to clear. - WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) - [29:29] - read-write - oneToClear - - - BUSY - This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. - - To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. - [26:26] - read-only - - - SNIFF_EN - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. - - This allows checksum to be enabled or disabled on a per-control- block basis. - [25:25] - read-write - - - BSWAP - Apply byte-swap transformation to DMA data. - For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. - [24:24] - read-write - - - IRQ_QUIET - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. - - This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. - [23:23] - read-write - - - TREQ_SEL - Select a Transfer Request signal. - The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). - 0x0 to 0x3a -> select DREQ n as TREQ - [22:17] - read-write - - - PIO0_TX0 - 0 - Select PIO0's TX FIFO 0 as TREQ - - - PIO0_TX1 - 1 - Select PIO0's TX FIFO 1 as TREQ - - - PIO0_TX2 - 2 - Select PIO0's TX FIFO 2 as TREQ - - - PIO0_TX3 - 3 - Select PIO0's TX FIFO 3 as TREQ - - - PIO0_RX0 - 4 - Select PIO0's RX FIFO 0 as TREQ - - - PIO0_RX1 - 5 - Select PIO0's RX FIFO 1 as TREQ - - - PIO0_RX2 - 6 - Select PIO0's RX FIFO 2 as TREQ - - - PIO0_RX3 - 7 - Select PIO0's RX FIFO 3 as TREQ - - - PIO1_TX0 - 8 - Select PIO1's TX FIFO 0 as TREQ - - - PIO1_TX1 - 9 - Select PIO1's TX FIFO 1 as TREQ - - - PIO1_TX2 - 10 - Select PIO1's TX FIFO 2 as TREQ - - - PIO1_TX3 - 11 - Select PIO1's TX FIFO 3 as TREQ - - - PIO1_RX0 - 12 - Select PIO1's RX FIFO 0 as TREQ - - - PIO1_RX1 - 13 - Select PIO1's RX FIFO 1 as TREQ - - - PIO1_RX2 - 14 - Select PIO1's RX FIFO 2 as TREQ - - - PIO1_RX3 - 15 - Select PIO1's RX FIFO 3 as TREQ - - - PIO2_TX0 - 16 - Select PIO2's TX FIFO 0 as TREQ - - - PIO2_TX1 - 17 - Select PIO2's TX FIFO 1 as TREQ - - - PIO2_TX2 - 18 - Select PIO2's TX FIFO 2 as TREQ - - - PIO2_TX3 - 19 - Select PIO2's TX FIFO 3 as TREQ - - - PIO2_RX0 - 20 - Select PIO2's RX FIFO 0 as TREQ - - - PIO2_RX1 - 21 - Select PIO2's RX FIFO 1 as TREQ - - - PIO2_RX2 - 22 - Select PIO2's RX FIFO 2 as TREQ - - - PIO2_RX3 - 23 - Select PIO2's RX FIFO 3 as TREQ - - - SPI0_TX - 24 - Select SPI0's TX FIFO as TREQ - - - SPI0_RX - 25 - Select SPI0's RX FIFO as TREQ - - - SPI1_TX - 26 - Select SPI1's TX FIFO as TREQ - - - SPI1_RX - 27 - Select SPI1's RX FIFO as TREQ - - - UART0_TX - 28 - Select UART0's TX FIFO as TREQ - - - UART0_RX - 29 - Select UART0's RX FIFO as TREQ - - - UART1_TX - 30 - Select UART1's TX FIFO as TREQ - - - UART1_RX - 31 - Select UART1's RX FIFO as TREQ - - - PWM_WRAP0 - 32 - Select PWM Counter 0's Wrap Value as TREQ - - - PWM_WRAP1 - 33 - Select PWM Counter 1's Wrap Value as TREQ - - - PWM_WRAP2 - 34 - Select PWM Counter 2's Wrap Value as TREQ - - - PWM_WRAP3 - 35 - Select PWM Counter 3's Wrap Value as TREQ - - - PWM_WRAP4 - 36 - Select PWM Counter 4's Wrap Value as TREQ - - - PWM_WRAP5 - 37 - Select PWM Counter 5's Wrap Value as TREQ - - - PWM_WRAP6 - 38 - Select PWM Counter 6's Wrap Value as TREQ - - - PWM_WRAP7 - 39 - Select PWM Counter 7's Wrap Value as TREQ - - - PWM_WRAP8 - 40 - Select PWM Counter 8's Wrap Value as TREQ - - - PWM_WRAP9 - 41 - Select PWM Counter 9's Wrap Value as TREQ - - - PWM_WRAP10 - 42 - Select PWM Counter 0's Wrap Value as TREQ - - - PWM_WRAP11 - 43 - Select PWM Counter 1's Wrap Value as TREQ - - - I2C0_TX - 44 - Select I2C0's TX FIFO as TREQ - - - I2C0_RX - 45 - Select I2C0's RX FIFO as TREQ - - - I2C1_TX - 46 - Select I2C1's TX FIFO as TREQ - - - I2C1_RX - 47 - Select I2C1's RX FIFO as TREQ - - - ADC - 48 - Select the ADC as TREQ - - - XIP_STREAM - 49 - Select the XIP Streaming FIFO as TREQ - - - XIP_QMITX - 50 - Select XIP_QMITX as TREQ - - - XIP_QMIRX - 51 - Select XIP_QMIRX as TREQ - - - HSTX - 52 - Select HSTX as TREQ - - - CORESIGHT - 53 - Select CORESIGHT as TREQ - - - SHA256 - 54 - Select SHA256 as TREQ - - - TIMER0 - 59 - Select Timer 0 as TREQ - - - TIMER1 - 60 - Select Timer 1 as TREQ - - - TIMER2 - 61 - Select Timer 2 as TREQ (Optional) - - - TIMER3 - 62 - Select Timer 3 as TREQ (Optional) - - - PERMANENT - 63 - Permanent request, for unpaced transfers. - - - - - CHAIN_TO - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. - - Note this field resets to 0, so channels 1 and above will chain to channel 0 by default. Set this field to avoid this behaviour. - [16:13] - read-write - - - RING_SEL - Select whether RING_SIZE applies to read or write addresses. - If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. - [12:12] - read-write - - - RING_SIZE - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. - - Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. - [11:8] - read-write - - - RING_NONE - 0 - - - - - INCR_WRITE_REV - If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer. - - If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. - [7:7] - read-write - - - INCR_WRITE - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. - - Generally this should be disabled for memory-to-peripheral transfers. - [6:6] - read-write - - - INCR_READ_REV - If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer. - - If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. - [5:5] - read-write - - - INCR_READ - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. - - Generally this should be disabled for peripheral-to-memory transfers. - [4:4] - read-write - - - DATA_SIZE - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. - [3:2] - read-write - - - SIZE_BYTE - 0 - - - SIZE_HALFWORD - 1 - - - SIZE_WORD - 2 - - - - - HIGH_PRIORITY - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. - - This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. - [1:1] - read-write - - - EN - DMA Channel Enable. - When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) - [0:0] - read-write - - - - - CH10_AL1_CTRL - 0x00000290 - Alias for channel 10 CTRL register - 0x00000000 - - - CH10_AL1_CTRL - [31:0] - read-write - - - - - CH10_AL1_READ_ADDR - 0x00000294 - Alias for channel 10 READ_ADDR register - 0x00000000 - - - CH10_AL1_READ_ADDR - [31:0] - read-write - - - - - CH10_AL1_WRITE_ADDR - 0x00000298 - Alias for channel 10 WRITE_ADDR register - 0x00000000 - - - CH10_AL1_WRITE_ADDR - [31:0] - read-write - - - - - CH10_AL1_TRANS_COUNT_TRIG - 0x0000029c - Alias for channel 10 TRANS_COUNT register - This is a trigger register (0xc). Writing a nonzero value will - reload the channel counter and start the channel. - 0x00000000 - - - CH10_AL1_TRANS_COUNT_TRIG - [31:0] - read-write - - - - - CH10_AL2_CTRL - 0x000002a0 - Alias for channel 10 CTRL register - 0x00000000 - - - CH10_AL2_CTRL - [31:0] - read-write - - - - - CH10_AL2_TRANS_COUNT - 0x000002a4 - Alias for channel 10 TRANS_COUNT register - 0x00000000 - - - CH10_AL2_TRANS_COUNT - [31:0] - read-write - - - - - CH10_AL2_READ_ADDR - 0x000002a8 - Alias for channel 10 READ_ADDR register - 0x00000000 - - - CH10_AL2_READ_ADDR - [31:0] - read-write - - - - - CH10_AL2_WRITE_ADDR_TRIG - 0x000002ac - Alias for channel 10 WRITE_ADDR register - This is a trigger register (0xc). Writing a nonzero value will - reload the channel counter and start the channel. - 0x00000000 - - - CH10_AL2_WRITE_ADDR_TRIG - [31:0] - read-write - - - - - CH10_AL3_CTRL - 0x000002b0 - Alias for channel 10 CTRL register - 0x00000000 - - - CH10_AL3_CTRL - [31:0] - read-write - - - - - CH10_AL3_WRITE_ADDR - 0x000002b4 - Alias for channel 10 WRITE_ADDR register - 0x00000000 - - - CH10_AL3_WRITE_ADDR - [31:0] - read-write - - - - - CH10_AL3_TRANS_COUNT - 0x000002b8 - Alias for channel 10 TRANS_COUNT register - 0x00000000 - - - CH10_AL3_TRANS_COUNT - [31:0] - read-write - - - - - CH10_AL3_READ_ADDR_TRIG - 0x000002bc - Alias for channel 10 READ_ADDR register - This is a trigger register (0xc). Writing a nonzero value will - reload the channel counter and start the channel. - 0x00000000 - - - CH10_AL3_READ_ADDR_TRIG - [31:0] - read-write - - - - - CH11_READ_ADDR - 0x000002c0 - DMA Channel 11 Read Address pointer - 0x00000000 - - - CH11_READ_ADDR - This register updates automatically each time a read completes. The current value is the next address to be read by this channel. - [31:0] - read-write - - - - - CH11_WRITE_ADDR - 0x000002c4 - DMA Channel 11 Write Address pointer - 0x00000000 - - - CH11_WRITE_ADDR - This register updates automatically each time a write completes. The current value is the next address to be written by this channel. - [31:0] - read-write - - - - - CH11_TRANS_COUNT - 0x000002c8 - DMA Channel 11 Transfer Count - 0x00000000 - - - MODE - When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. - - When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. - - When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. - - All other values are reserved. - [31:28] - read-write - - - NORMAL - 0 - - - TRIGGER_SELF - 1 - - - ENDLESS - 15 - - - - - COUNT - 28-bit transfer count (256 million transfers maximum). - - Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). - - When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. - - Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. - - The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. - [27:0] - read-write - - - - - CH11_CTRL_TRIG - 0x000002cc - DMA Channel 11 Control and Status - 0x00000000 - - - AHB_ERROR - Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. - [31:31] - read-only - - - READ_ERROR - If 1, the channel received a read bus error. Write one to clear. - READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) - [30:30] - read-write - oneToClear - - - WRITE_ERROR - If 1, the channel received a write bus error. Write one to clear. - WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) - [29:29] - read-write - oneToClear - - - BUSY - This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. - - To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. - [26:26] - read-only - - - SNIFF_EN - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. - - This allows checksum to be enabled or disabled on a per-control- block basis. - [25:25] - read-write - - - BSWAP - Apply byte-swap transformation to DMA data. - For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. - [24:24] - read-write - - - IRQ_QUIET - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. - - This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. - [23:23] - read-write - - - TREQ_SEL - Select a Transfer Request signal. - The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). - 0x0 to 0x3a -> select DREQ n as TREQ - [22:17] - read-write - - - PIO0_TX0 - 0 - Select PIO0's TX FIFO 0 as TREQ - - - PIO0_TX1 - 1 - Select PIO0's TX FIFO 1 as TREQ - - - PIO0_TX2 - 2 - Select PIO0's TX FIFO 2 as TREQ - - - PIO0_TX3 - 3 - Select PIO0's TX FIFO 3 as TREQ - - - PIO0_RX0 - 4 - Select PIO0's RX FIFO 0 as TREQ - - - PIO0_RX1 - 5 - Select PIO0's RX FIFO 1 as TREQ - - - PIO0_RX2 - 6 - Select PIO0's RX FIFO 2 as TREQ - - - PIO0_RX3 - 7 - Select PIO0's RX FIFO 3 as TREQ - - - PIO1_TX0 - 8 - Select PIO1's TX FIFO 0 as TREQ - - - PIO1_TX1 - 9 - Select PIO1's TX FIFO 1 as TREQ - - - PIO1_TX2 - 10 - Select PIO1's TX FIFO 2 as TREQ - - - PIO1_TX3 - 11 - Select PIO1's TX FIFO 3 as TREQ - - - PIO1_RX0 - 12 - Select PIO1's RX FIFO 0 as TREQ - - - PIO1_RX1 - 13 - Select PIO1's RX FIFO 1 as TREQ - - - PIO1_RX2 - 14 - Select PIO1's RX FIFO 2 as TREQ - - - PIO1_RX3 - 15 - Select PIO1's RX FIFO 3 as TREQ - - - PIO2_TX0 - 16 - Select PIO2's TX FIFO 0 as TREQ - - - PIO2_TX1 - 17 - Select PIO2's TX FIFO 1 as TREQ - - - PIO2_TX2 - 18 - Select PIO2's TX FIFO 2 as TREQ - - - PIO2_TX3 - 19 - Select PIO2's TX FIFO 3 as TREQ - - - PIO2_RX0 - 20 - Select PIO2's RX FIFO 0 as TREQ - - - PIO2_RX1 - 21 - Select PIO2's RX FIFO 1 as TREQ - - - PIO2_RX2 - 22 - Select PIO2's RX FIFO 2 as TREQ - - - PIO2_RX3 - 23 - Select PIO2's RX FIFO 3 as TREQ - - - SPI0_TX - 24 - Select SPI0's TX FIFO as TREQ - - - SPI0_RX - 25 - Select SPI0's RX FIFO as TREQ - - - SPI1_TX - 26 - Select SPI1's TX FIFO as TREQ - - - SPI1_RX - 27 - Select SPI1's RX FIFO as TREQ - - - UART0_TX - 28 - Select UART0's TX FIFO as TREQ - - - UART0_RX - 29 - Select UART0's RX FIFO as TREQ - - - UART1_TX - 30 - Select UART1's TX FIFO as TREQ - - - UART1_RX - 31 - Select UART1's RX FIFO as TREQ - - - PWM_WRAP0 - 32 - Select PWM Counter 0's Wrap Value as TREQ - - - PWM_WRAP1 - 33 - Select PWM Counter 1's Wrap Value as TREQ - - - PWM_WRAP2 - 34 - Select PWM Counter 2's Wrap Value as TREQ - - - PWM_WRAP3 - 35 - Select PWM Counter 3's Wrap Value as TREQ - - - PWM_WRAP4 - 36 - Select PWM Counter 4's Wrap Value as TREQ - - - PWM_WRAP5 - 37 - Select PWM Counter 5's Wrap Value as TREQ - - - PWM_WRAP6 - 38 - Select PWM Counter 6's Wrap Value as TREQ - - - PWM_WRAP7 - 39 - Select PWM Counter 7's Wrap Value as TREQ - - - PWM_WRAP8 - 40 - Select PWM Counter 8's Wrap Value as TREQ - - - PWM_WRAP9 - 41 - Select PWM Counter 9's Wrap Value as TREQ - - - PWM_WRAP10 - 42 - Select PWM Counter 0's Wrap Value as TREQ - - - PWM_WRAP11 - 43 - Select PWM Counter 1's Wrap Value as TREQ - - - I2C0_TX - 44 - Select I2C0's TX FIFO as TREQ - - - I2C0_RX - 45 - Select I2C0's RX FIFO as TREQ - - - I2C1_TX - 46 - Select I2C1's TX FIFO as TREQ - - - I2C1_RX - 47 - Select I2C1's RX FIFO as TREQ - - - ADC - 48 - Select the ADC as TREQ - - - XIP_STREAM - 49 - Select the XIP Streaming FIFO as TREQ - - - XIP_QMITX - 50 - Select XIP_QMITX as TREQ - - - XIP_QMIRX - 51 - Select XIP_QMIRX as TREQ - - - HSTX - 52 - Select HSTX as TREQ - - - CORESIGHT - 53 - Select CORESIGHT as TREQ - - - SHA256 - 54 - Select SHA256 as TREQ - - - TIMER0 - 59 - Select Timer 0 as TREQ - - - TIMER1 - 60 - Select Timer 1 as TREQ - - - TIMER2 - 61 - Select Timer 2 as TREQ (Optional) - - - TIMER3 - 62 - Select Timer 3 as TREQ (Optional) - - - PERMANENT - 63 - Permanent request, for unpaced transfers. - - - - - CHAIN_TO - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. - - Note this field resets to 0, so channels 1 and above will chain to channel 0 by default. Set this field to avoid this behaviour. - [16:13] - read-write - - - RING_SEL - Select whether RING_SIZE applies to read or write addresses. - If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. - [12:12] - read-write - - - RING_SIZE - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. - - Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. - [11:8] - read-write - - - RING_NONE - 0 - - - - - INCR_WRITE_REV - If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer. - - If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. - [7:7] - read-write - - - INCR_WRITE - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. - - Generally this should be disabled for memory-to-peripheral transfers. - [6:6] - read-write - - - INCR_READ_REV - If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer. - - If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. - [5:5] - read-write - - - INCR_READ - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. - - Generally this should be disabled for peripheral-to-memory transfers. - [4:4] - read-write - - - DATA_SIZE - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. - [3:2] - read-write - - - SIZE_BYTE - 0 - - - SIZE_HALFWORD - 1 - - - SIZE_WORD - 2 - - - - - HIGH_PRIORITY - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. - - This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. - [1:1] - read-write - - - EN - DMA Channel Enable. - When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) - [0:0] - read-write - - - - - CH11_AL1_CTRL - 0x000002d0 - Alias for channel 11 CTRL register - 0x00000000 - - - CH11_AL1_CTRL - [31:0] - read-write - - - - - CH11_AL1_READ_ADDR - 0x000002d4 - Alias for channel 11 READ_ADDR register - 0x00000000 - - - CH11_AL1_READ_ADDR - [31:0] - read-write - - - - - CH11_AL1_WRITE_ADDR - 0x000002d8 - Alias for channel 11 WRITE_ADDR register - 0x00000000 - - - CH11_AL1_WRITE_ADDR - [31:0] - read-write - - - - - CH11_AL1_TRANS_COUNT_TRIG - 0x000002dc - Alias for channel 11 TRANS_COUNT register - This is a trigger register (0xc). Writing a nonzero value will - reload the channel counter and start the channel. - 0x00000000 - - - CH11_AL1_TRANS_COUNT_TRIG - [31:0] - read-write - - - - - CH11_AL2_CTRL - 0x000002e0 - Alias for channel 11 CTRL register - 0x00000000 - - - CH11_AL2_CTRL - [31:0] - read-write - - - - - CH11_AL2_TRANS_COUNT - 0x000002e4 - Alias for channel 11 TRANS_COUNT register - 0x00000000 - - - CH11_AL2_TRANS_COUNT - [31:0] - read-write - - - - - CH11_AL2_READ_ADDR - 0x000002e8 - Alias for channel 11 READ_ADDR register - 0x00000000 - - - CH11_AL2_READ_ADDR - [31:0] - read-write - - - - - CH11_AL2_WRITE_ADDR_TRIG - 0x000002ec - Alias for channel 11 WRITE_ADDR register - This is a trigger register (0xc). Writing a nonzero value will - reload the channel counter and start the channel. - 0x00000000 - - - CH11_AL2_WRITE_ADDR_TRIG - [31:0] - read-write - - - - - CH11_AL3_CTRL - 0x000002f0 - Alias for channel 11 CTRL register - 0x00000000 - - - CH11_AL3_CTRL - [31:0] - read-write - - - - - CH11_AL3_WRITE_ADDR - 0x000002f4 - Alias for channel 11 WRITE_ADDR register - 0x00000000 - - - CH11_AL3_WRITE_ADDR - [31:0] - read-write - - - - - CH11_AL3_TRANS_COUNT - 0x000002f8 - Alias for channel 11 TRANS_COUNT register - 0x00000000 - - - CH11_AL3_TRANS_COUNT - [31:0] - read-write - - - - - CH11_AL3_READ_ADDR_TRIG - 0x000002fc - Alias for channel 11 READ_ADDR register - This is a trigger register (0xc). Writing a nonzero value will - reload the channel counter and start the channel. - 0x00000000 - - - CH11_AL3_READ_ADDR_TRIG - [31:0] - read-write - - - - - CH12_READ_ADDR - 0x00000300 - DMA Channel 12 Read Address pointer - 0x00000000 - - - CH12_READ_ADDR - This register updates automatically each time a read completes. The current value is the next address to be read by this channel. - [31:0] - read-write - - - - - CH12_WRITE_ADDR - 0x00000304 - DMA Channel 12 Write Address pointer - 0x00000000 - - - CH12_WRITE_ADDR - This register updates automatically each time a write completes. The current value is the next address to be written by this channel. - [31:0] - read-write - - - - - CH12_TRANS_COUNT - 0x00000308 - DMA Channel 12 Transfer Count - 0x00000000 - - - MODE - When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. - - When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. - - When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. - - All other values are reserved. - [31:28] - read-write - - - NORMAL - 0 - - - TRIGGER_SELF - 1 - - - ENDLESS - 15 - - - - - COUNT - 28-bit transfer count (256 million transfers maximum). - - Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). - - When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. - - Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. - - The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. - [27:0] - read-write - - - - - CH12_CTRL_TRIG - 0x0000030c - DMA Channel 12 Control and Status - 0x00000000 - - - AHB_ERROR - Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. - [31:31] - read-only - - - READ_ERROR - If 1, the channel received a read bus error. Write one to clear. - READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) - [30:30] - read-write - oneToClear - - - WRITE_ERROR - If 1, the channel received a write bus error. Write one to clear. - WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) - [29:29] - read-write - oneToClear - - - BUSY - This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. - - To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. - [26:26] - read-only - - - SNIFF_EN - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. - - This allows checksum to be enabled or disabled on a per-control- block basis. - [25:25] - read-write - - - BSWAP - Apply byte-swap transformation to DMA data. - For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. - [24:24] - read-write - - - IRQ_QUIET - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. - - This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. - [23:23] - read-write - - - TREQ_SEL - Select a Transfer Request signal. - The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). - 0x0 to 0x3a -> select DREQ n as TREQ - [22:17] - read-write - - - PIO0_TX0 - 0 - Select PIO0's TX FIFO 0 as TREQ - - - PIO0_TX1 - 1 - Select PIO0's TX FIFO 1 as TREQ - - - PIO0_TX2 - 2 - Select PIO0's TX FIFO 2 as TREQ - - - PIO0_TX3 - 3 - Select PIO0's TX FIFO 3 as TREQ - - - PIO0_RX0 - 4 - Select PIO0's RX FIFO 0 as TREQ - - - PIO0_RX1 - 5 - Select PIO0's RX FIFO 1 as TREQ - - - PIO0_RX2 - 6 - Select PIO0's RX FIFO 2 as TREQ - - - PIO0_RX3 - 7 - Select PIO0's RX FIFO 3 as TREQ - - - PIO1_TX0 - 8 - Select PIO1's TX FIFO 0 as TREQ - - - PIO1_TX1 - 9 - Select PIO1's TX FIFO 1 as TREQ - - - PIO1_TX2 - 10 - Select PIO1's TX FIFO 2 as TREQ - - - PIO1_TX3 - 11 - Select PIO1's TX FIFO 3 as TREQ - - - PIO1_RX0 - 12 - Select PIO1's RX FIFO 0 as TREQ - - - PIO1_RX1 - 13 - Select PIO1's RX FIFO 1 as TREQ - - - PIO1_RX2 - 14 - Select PIO1's RX FIFO 2 as TREQ - - - PIO1_RX3 - 15 - Select PIO1's RX FIFO 3 as TREQ - - - PIO2_TX0 - 16 - Select PIO2's TX FIFO 0 as TREQ - - - PIO2_TX1 - 17 - Select PIO2's TX FIFO 1 as TREQ - - - PIO2_TX2 - 18 - Select PIO2's TX FIFO 2 as TREQ - - - PIO2_TX3 - 19 - Select PIO2's TX FIFO 3 as TREQ - - - PIO2_RX0 - 20 - Select PIO2's RX FIFO 0 as TREQ - - - PIO2_RX1 - 21 - Select PIO2's RX FIFO 1 as TREQ - - - PIO2_RX2 - 22 - Select PIO2's RX FIFO 2 as TREQ - - - PIO2_RX3 - 23 - Select PIO2's RX FIFO 3 as TREQ - - - SPI0_TX - 24 - Select SPI0's TX FIFO as TREQ - - - SPI0_RX - 25 - Select SPI0's RX FIFO as TREQ - - - SPI1_TX - 26 - Select SPI1's TX FIFO as TREQ - - - SPI1_RX - 27 - Select SPI1's RX FIFO as TREQ - - - UART0_TX - 28 - Select UART0's TX FIFO as TREQ - - - UART0_RX - 29 - Select UART0's RX FIFO as TREQ - - - UART1_TX - 30 - Select UART1's TX FIFO as TREQ - - - UART1_RX - 31 - Select UART1's RX FIFO as TREQ - - - PWM_WRAP0 - 32 - Select PWM Counter 0's Wrap Value as TREQ - - - PWM_WRAP1 - 33 - Select PWM Counter 1's Wrap Value as TREQ - - - PWM_WRAP2 - 34 - Select PWM Counter 2's Wrap Value as TREQ - - - PWM_WRAP3 - 35 - Select PWM Counter 3's Wrap Value as TREQ - - - PWM_WRAP4 - 36 - Select PWM Counter 4's Wrap Value as TREQ - - - PWM_WRAP5 - 37 - Select PWM Counter 5's Wrap Value as TREQ - - - PWM_WRAP6 - 38 - Select PWM Counter 6's Wrap Value as TREQ - - - PWM_WRAP7 - 39 - Select PWM Counter 7's Wrap Value as TREQ - - - PWM_WRAP8 - 40 - Select PWM Counter 8's Wrap Value as TREQ - - - PWM_WRAP9 - 41 - Select PWM Counter 9's Wrap Value as TREQ - - - PWM_WRAP10 - 42 - Select PWM Counter 0's Wrap Value as TREQ - - - PWM_WRAP11 - 43 - Select PWM Counter 1's Wrap Value as TREQ - - - I2C0_TX - 44 - Select I2C0's TX FIFO as TREQ - - - I2C0_RX - 45 - Select I2C0's RX FIFO as TREQ - - - I2C1_TX - 46 - Select I2C1's TX FIFO as TREQ - - - I2C1_RX - 47 - Select I2C1's RX FIFO as TREQ - - - ADC - 48 - Select the ADC as TREQ - - - XIP_STREAM - 49 - Select the XIP Streaming FIFO as TREQ - - - XIP_QMITX - 50 - Select XIP_QMITX as TREQ - - - XIP_QMIRX - 51 - Select XIP_QMIRX as TREQ - - - HSTX - 52 - Select HSTX as TREQ - - - CORESIGHT - 53 - Select CORESIGHT as TREQ - - - SHA256 - 54 - Select SHA256 as TREQ - - - TIMER0 - 59 - Select Timer 0 as TREQ - - - TIMER1 - 60 - Select Timer 1 as TREQ - - - TIMER2 - 61 - Select Timer 2 as TREQ (Optional) - - - TIMER3 - 62 - Select Timer 3 as TREQ (Optional) - - - PERMANENT - 63 - Permanent request, for unpaced transfers. - - - - - CHAIN_TO - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. - - Note this field resets to 0, so channels 1 and above will chain to channel 0 by default. Set this field to avoid this behaviour. - [16:13] - read-write - - - RING_SEL - Select whether RING_SIZE applies to read or write addresses. - If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. - [12:12] - read-write - - - RING_SIZE - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. - - Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. - [11:8] - read-write - - - RING_NONE - 0 - - - - - INCR_WRITE_REV - If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer. - - If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. - [7:7] - read-write - - - INCR_WRITE - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. - - Generally this should be disabled for memory-to-peripheral transfers. - [6:6] - read-write - - - INCR_READ_REV - If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer. - - If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. - [5:5] - read-write - - - INCR_READ - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. - - Generally this should be disabled for peripheral-to-memory transfers. - [4:4] - read-write - - - DATA_SIZE - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. - [3:2] - read-write - - - SIZE_BYTE - 0 - - - SIZE_HALFWORD - 1 - - - SIZE_WORD - 2 - - - - - HIGH_PRIORITY - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. - - This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. - [1:1] - read-write - - - EN - DMA Channel Enable. - When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) - [0:0] - read-write - - - - - CH12_AL1_CTRL - 0x00000310 - Alias for channel 12 CTRL register - 0x00000000 - - - CH12_AL1_CTRL - [31:0] - read-write - - - - - CH12_AL1_READ_ADDR - 0x00000314 - Alias for channel 12 READ_ADDR register - 0x00000000 - - - CH12_AL1_READ_ADDR - [31:0] - read-write - - - - - CH12_AL1_WRITE_ADDR - 0x00000318 - Alias for channel 12 WRITE_ADDR register - 0x00000000 - - - CH12_AL1_WRITE_ADDR - [31:0] - read-write - - - - - CH12_AL1_TRANS_COUNT_TRIG - 0x0000031c - Alias for channel 12 TRANS_COUNT register - This is a trigger register (0xc). Writing a nonzero value will - reload the channel counter and start the channel. - 0x00000000 - - - CH12_AL1_TRANS_COUNT_TRIG - [31:0] - read-write - - - - - CH12_AL2_CTRL - 0x00000320 - Alias for channel 12 CTRL register - 0x00000000 - - - CH12_AL2_CTRL - [31:0] - read-write - - - - - CH12_AL2_TRANS_COUNT - 0x00000324 - Alias for channel 12 TRANS_COUNT register - 0x00000000 - - - CH12_AL2_TRANS_COUNT - [31:0] - read-write - - - - - CH12_AL2_READ_ADDR - 0x00000328 - Alias for channel 12 READ_ADDR register - 0x00000000 - - - CH12_AL2_READ_ADDR - [31:0] - read-write - - - - - CH12_AL2_WRITE_ADDR_TRIG - 0x0000032c - Alias for channel 12 WRITE_ADDR register - This is a trigger register (0xc). Writing a nonzero value will - reload the channel counter and start the channel. - 0x00000000 - - - CH12_AL2_WRITE_ADDR_TRIG - [31:0] - read-write - - - - - CH12_AL3_CTRL - 0x00000330 - Alias for channel 12 CTRL register - 0x00000000 - - - CH12_AL3_CTRL - [31:0] - read-write - - - - - CH12_AL3_WRITE_ADDR - 0x00000334 - Alias for channel 12 WRITE_ADDR register - 0x00000000 - - - CH12_AL3_WRITE_ADDR - [31:0] - read-write - - - - - CH12_AL3_TRANS_COUNT - 0x00000338 - Alias for channel 12 TRANS_COUNT register - 0x00000000 - - - CH12_AL3_TRANS_COUNT - [31:0] - read-write - - - - - CH12_AL3_READ_ADDR_TRIG - 0x0000033c - Alias for channel 12 READ_ADDR register - This is a trigger register (0xc). Writing a nonzero value will - reload the channel counter and start the channel. - 0x00000000 - - - CH12_AL3_READ_ADDR_TRIG - [31:0] - read-write - - - - - CH13_READ_ADDR - 0x00000340 - DMA Channel 13 Read Address pointer - 0x00000000 - - - CH13_READ_ADDR - This register updates automatically each time a read completes. The current value is the next address to be read by this channel. - [31:0] - read-write - - - - - CH13_WRITE_ADDR - 0x00000344 - DMA Channel 13 Write Address pointer - 0x00000000 - - - CH13_WRITE_ADDR - This register updates automatically each time a write completes. The current value is the next address to be written by this channel. - [31:0] - read-write - - - - - CH13_TRANS_COUNT - 0x00000348 - DMA Channel 13 Transfer Count - 0x00000000 - - - MODE - When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. - - When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. - - When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. - - All other values are reserved. - [31:28] - read-write - - - NORMAL - 0 - - - TRIGGER_SELF - 1 - - - ENDLESS - 15 - - - - - COUNT - 28-bit transfer count (256 million transfers maximum). - - Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). - - When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. - - Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. - - The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. - [27:0] - read-write - - - - - CH13_CTRL_TRIG - 0x0000034c - DMA Channel 13 Control and Status - 0x00000000 - - - AHB_ERROR - Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. - [31:31] - read-only - - - READ_ERROR - If 1, the channel received a read bus error. Write one to clear. - READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) - [30:30] - read-write - oneToClear - - - WRITE_ERROR - If 1, the channel received a write bus error. Write one to clear. - WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) - [29:29] - read-write - oneToClear - - - BUSY - This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. - - To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. - [26:26] - read-only - - - SNIFF_EN - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. - - This allows checksum to be enabled or disabled on a per-control- block basis. - [25:25] - read-write - - - BSWAP - Apply byte-swap transformation to DMA data. - For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. - [24:24] - read-write - - - IRQ_QUIET - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. - - This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. - [23:23] - read-write - - - TREQ_SEL - Select a Transfer Request signal. - The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). - 0x0 to 0x3a -> select DREQ n as TREQ - [22:17] - read-write - - - PIO0_TX0 - 0 - Select PIO0's TX FIFO 0 as TREQ - - - PIO0_TX1 - 1 - Select PIO0's TX FIFO 1 as TREQ - - - PIO0_TX2 - 2 - Select PIO0's TX FIFO 2 as TREQ - - - PIO0_TX3 - 3 - Select PIO0's TX FIFO 3 as TREQ - - - PIO0_RX0 - 4 - Select PIO0's RX FIFO 0 as TREQ - - - PIO0_RX1 - 5 - Select PIO0's RX FIFO 1 as TREQ - - - PIO0_RX2 - 6 - Select PIO0's RX FIFO 2 as TREQ - - - PIO0_RX3 - 7 - Select PIO0's RX FIFO 3 as TREQ - - - PIO1_TX0 - 8 - Select PIO1's TX FIFO 0 as TREQ - - - PIO1_TX1 - 9 - Select PIO1's TX FIFO 1 as TREQ - - - PIO1_TX2 - 10 - Select PIO1's TX FIFO 2 as TREQ - - - PIO1_TX3 - 11 - Select PIO1's TX FIFO 3 as TREQ - - - PIO1_RX0 - 12 - Select PIO1's RX FIFO 0 as TREQ - - - PIO1_RX1 - 13 - Select PIO1's RX FIFO 1 as TREQ - - - PIO1_RX2 - 14 - Select PIO1's RX FIFO 2 as TREQ - - - PIO1_RX3 - 15 - Select PIO1's RX FIFO 3 as TREQ - - - PIO2_TX0 - 16 - Select PIO2's TX FIFO 0 as TREQ - - - PIO2_TX1 - 17 - Select PIO2's TX FIFO 1 as TREQ - - - PIO2_TX2 - 18 - Select PIO2's TX FIFO 2 as TREQ - - - PIO2_TX3 - 19 - Select PIO2's TX FIFO 3 as TREQ - - - PIO2_RX0 - 20 - Select PIO2's RX FIFO 0 as TREQ - - - PIO2_RX1 - 21 - Select PIO2's RX FIFO 1 as TREQ - - - PIO2_RX2 - 22 - Select PIO2's RX FIFO 2 as TREQ - - - PIO2_RX3 - 23 - Select PIO2's RX FIFO 3 as TREQ - - - SPI0_TX - 24 - Select SPI0's TX FIFO as TREQ - - - SPI0_RX - 25 - Select SPI0's RX FIFO as TREQ - - - SPI1_TX - 26 - Select SPI1's TX FIFO as TREQ - - - SPI1_RX - 27 - Select SPI1's RX FIFO as TREQ - - - UART0_TX - 28 - Select UART0's TX FIFO as TREQ - - - UART0_RX - 29 - Select UART0's RX FIFO as TREQ - - - UART1_TX - 30 - Select UART1's TX FIFO as TREQ - - - UART1_RX - 31 - Select UART1's RX FIFO as TREQ - - - PWM_WRAP0 - 32 - Select PWM Counter 0's Wrap Value as TREQ - - - PWM_WRAP1 - 33 - Select PWM Counter 1's Wrap Value as TREQ - - - PWM_WRAP2 - 34 - Select PWM Counter 2's Wrap Value as TREQ - - - PWM_WRAP3 - 35 - Select PWM Counter 3's Wrap Value as TREQ - - - PWM_WRAP4 - 36 - Select PWM Counter 4's Wrap Value as TREQ - - - PWM_WRAP5 - 37 - Select PWM Counter 5's Wrap Value as TREQ - - - PWM_WRAP6 - 38 - Select PWM Counter 6's Wrap Value as TREQ - - - PWM_WRAP7 - 39 - Select PWM Counter 7's Wrap Value as TREQ - - - PWM_WRAP8 - 40 - Select PWM Counter 8's Wrap Value as TREQ - - - PWM_WRAP9 - 41 - Select PWM Counter 9's Wrap Value as TREQ - - - PWM_WRAP10 - 42 - Select PWM Counter 0's Wrap Value as TREQ - - - PWM_WRAP11 - 43 - Select PWM Counter 1's Wrap Value as TREQ - - - I2C0_TX - 44 - Select I2C0's TX FIFO as TREQ - - - I2C0_RX - 45 - Select I2C0's RX FIFO as TREQ - - - I2C1_TX - 46 - Select I2C1's TX FIFO as TREQ - - - I2C1_RX - 47 - Select I2C1's RX FIFO as TREQ - - - ADC - 48 - Select the ADC as TREQ - - - XIP_STREAM - 49 - Select the XIP Streaming FIFO as TREQ - - - XIP_QMITX - 50 - Select XIP_QMITX as TREQ - - - XIP_QMIRX - 51 - Select XIP_QMIRX as TREQ - - - HSTX - 52 - Select HSTX as TREQ - - - CORESIGHT - 53 - Select CORESIGHT as TREQ - - - SHA256 - 54 - Select SHA256 as TREQ - - - TIMER0 - 59 - Select Timer 0 as TREQ - - - TIMER1 - 60 - Select Timer 1 as TREQ - - - TIMER2 - 61 - Select Timer 2 as TREQ (Optional) - - - TIMER3 - 62 - Select Timer 3 as TREQ (Optional) - - - PERMANENT - 63 - Permanent request, for unpaced transfers. - - - - - CHAIN_TO - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. - - Note this field resets to 0, so channels 1 and above will chain to channel 0 by default. Set this field to avoid this behaviour. - [16:13] - read-write - - - RING_SEL - Select whether RING_SIZE applies to read or write addresses. - If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. - [12:12] - read-write - - - RING_SIZE - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. - - Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. - [11:8] - read-write - - - RING_NONE - 0 - - - - - INCR_WRITE_REV - If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer. - - If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. - [7:7] - read-write - - - INCR_WRITE - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. - - Generally this should be disabled for memory-to-peripheral transfers. - [6:6] - read-write - - - INCR_READ_REV - If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer. - - If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. - [5:5] - read-write - - - INCR_READ - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. - - Generally this should be disabled for peripheral-to-memory transfers. - [4:4] - read-write - - - DATA_SIZE - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. - [3:2] - read-write - - - SIZE_BYTE - 0 - - - SIZE_HALFWORD - 1 - - - SIZE_WORD - 2 - - - - - HIGH_PRIORITY - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. - - This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. - [1:1] - read-write - - - EN - DMA Channel Enable. - When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) - [0:0] - read-write - - - - - CH13_AL1_CTRL - 0x00000350 - Alias for channel 13 CTRL register - 0x00000000 - - - CH13_AL1_CTRL - [31:0] - read-write - - - - - CH13_AL1_READ_ADDR - 0x00000354 - Alias for channel 13 READ_ADDR register - 0x00000000 - - - CH13_AL1_READ_ADDR - [31:0] - read-write - - - - - CH13_AL1_WRITE_ADDR - 0x00000358 - Alias for channel 13 WRITE_ADDR register - 0x00000000 - - - CH13_AL1_WRITE_ADDR - [31:0] - read-write - - - - - CH13_AL1_TRANS_COUNT_TRIG - 0x0000035c - Alias for channel 13 TRANS_COUNT register - This is a trigger register (0xc). Writing a nonzero value will - reload the channel counter and start the channel. - 0x00000000 - - - CH13_AL1_TRANS_COUNT_TRIG - [31:0] - read-write - - - - - CH13_AL2_CTRL - 0x00000360 - Alias for channel 13 CTRL register - 0x00000000 - - - CH13_AL2_CTRL - [31:0] - read-write - - - - - CH13_AL2_TRANS_COUNT - 0x00000364 - Alias for channel 13 TRANS_COUNT register - 0x00000000 - - - CH13_AL2_TRANS_COUNT - [31:0] - read-write - - - - - CH13_AL2_READ_ADDR - 0x00000368 - Alias for channel 13 READ_ADDR register - 0x00000000 - - - CH13_AL2_READ_ADDR - [31:0] - read-write - - - - - CH13_AL2_WRITE_ADDR_TRIG - 0x0000036c - Alias for channel 13 WRITE_ADDR register - This is a trigger register (0xc). Writing a nonzero value will - reload the channel counter and start the channel. - 0x00000000 - - - CH13_AL2_WRITE_ADDR_TRIG - [31:0] - read-write - - - - - CH13_AL3_CTRL - 0x00000370 - Alias for channel 13 CTRL register - 0x00000000 - - - CH13_AL3_CTRL - [31:0] - read-write - - - - - CH13_AL3_WRITE_ADDR - 0x00000374 - Alias for channel 13 WRITE_ADDR register - 0x00000000 - - - CH13_AL3_WRITE_ADDR - [31:0] - read-write - - - - - CH13_AL3_TRANS_COUNT - 0x00000378 - Alias for channel 13 TRANS_COUNT register - 0x00000000 - - - CH13_AL3_TRANS_COUNT - [31:0] - read-write - - - - - CH13_AL3_READ_ADDR_TRIG - 0x0000037c - Alias for channel 13 READ_ADDR register - This is a trigger register (0xc). Writing a nonzero value will - reload the channel counter and start the channel. - 0x00000000 - - - CH13_AL3_READ_ADDR_TRIG - [31:0] - read-write - - - - - CH14_READ_ADDR - 0x00000380 - DMA Channel 14 Read Address pointer - 0x00000000 - - - CH14_READ_ADDR - This register updates automatically each time a read completes. The current value is the next address to be read by this channel. - [31:0] - read-write - - - - - CH14_WRITE_ADDR - 0x00000384 - DMA Channel 14 Write Address pointer - 0x00000000 - - - CH14_WRITE_ADDR - This register updates automatically each time a write completes. The current value is the next address to be written by this channel. - [31:0] - read-write - - - - - CH14_TRANS_COUNT - 0x00000388 - DMA Channel 14 Transfer Count - 0x00000000 - - - MODE - When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. - - When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. - - When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. - - All other values are reserved. - [31:28] - read-write - - - NORMAL - 0 - - - TRIGGER_SELF - 1 - - - ENDLESS - 15 - - - - - COUNT - 28-bit transfer count (256 million transfers maximum). - - Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). - - When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. - - Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. - - The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. - [27:0] - read-write - - - - - CH14_CTRL_TRIG - 0x0000038c - DMA Channel 14 Control and Status - 0x00000000 - - - AHB_ERROR - Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. - [31:31] - read-only - - - READ_ERROR - If 1, the channel received a read bus error. Write one to clear. - READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) - [30:30] - read-write - oneToClear - - - WRITE_ERROR - If 1, the channel received a write bus error. Write one to clear. - WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) - [29:29] - read-write - oneToClear - - - BUSY - This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. - - To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. - [26:26] - read-only - - - SNIFF_EN - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. - - This allows checksum to be enabled or disabled on a per-control- block basis. - [25:25] - read-write - - - BSWAP - Apply byte-swap transformation to DMA data. - For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. - [24:24] - read-write - - - IRQ_QUIET - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. - - This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. - [23:23] - read-write - - - TREQ_SEL - Select a Transfer Request signal. - The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). - 0x0 to 0x3a -> select DREQ n as TREQ - [22:17] - read-write - - - PIO0_TX0 - 0 - Select PIO0's TX FIFO 0 as TREQ - - - PIO0_TX1 - 1 - Select PIO0's TX FIFO 1 as TREQ - - - PIO0_TX2 - 2 - Select PIO0's TX FIFO 2 as TREQ - - - PIO0_TX3 - 3 - Select PIO0's TX FIFO 3 as TREQ - - - PIO0_RX0 - 4 - Select PIO0's RX FIFO 0 as TREQ - - - PIO0_RX1 - 5 - Select PIO0's RX FIFO 1 as TREQ - - - PIO0_RX2 - 6 - Select PIO0's RX FIFO 2 as TREQ - - - PIO0_RX3 - 7 - Select PIO0's RX FIFO 3 as TREQ - - - PIO1_TX0 - 8 - Select PIO1's TX FIFO 0 as TREQ - - - PIO1_TX1 - 9 - Select PIO1's TX FIFO 1 as TREQ - - - PIO1_TX2 - 10 - Select PIO1's TX FIFO 2 as TREQ - - - PIO1_TX3 - 11 - Select PIO1's TX FIFO 3 as TREQ - - - PIO1_RX0 - 12 - Select PIO1's RX FIFO 0 as TREQ - - - PIO1_RX1 - 13 - Select PIO1's RX FIFO 1 as TREQ - - - PIO1_RX2 - 14 - Select PIO1's RX FIFO 2 as TREQ - - - PIO1_RX3 - 15 - Select PIO1's RX FIFO 3 as TREQ - - - PIO2_TX0 - 16 - Select PIO2's TX FIFO 0 as TREQ - - - PIO2_TX1 - 17 - Select PIO2's TX FIFO 1 as TREQ - - - PIO2_TX2 - 18 - Select PIO2's TX FIFO 2 as TREQ - - - PIO2_TX3 - 19 - Select PIO2's TX FIFO 3 as TREQ - - - PIO2_RX0 - 20 - Select PIO2's RX FIFO 0 as TREQ - - - PIO2_RX1 - 21 - Select PIO2's RX FIFO 1 as TREQ - - - PIO2_RX2 - 22 - Select PIO2's RX FIFO 2 as TREQ - - - PIO2_RX3 - 23 - Select PIO2's RX FIFO 3 as TREQ - - - SPI0_TX - 24 - Select SPI0's TX FIFO as TREQ - - - SPI0_RX - 25 - Select SPI0's RX FIFO as TREQ - - - SPI1_TX - 26 - Select SPI1's TX FIFO as TREQ - - - SPI1_RX - 27 - Select SPI1's RX FIFO as TREQ - - - UART0_TX - 28 - Select UART0's TX FIFO as TREQ - - - UART0_RX - 29 - Select UART0's RX FIFO as TREQ - - - UART1_TX - 30 - Select UART1's TX FIFO as TREQ - - - UART1_RX - 31 - Select UART1's RX FIFO as TREQ - - - PWM_WRAP0 - 32 - Select PWM Counter 0's Wrap Value as TREQ - - - PWM_WRAP1 - 33 - Select PWM Counter 1's Wrap Value as TREQ - - - PWM_WRAP2 - 34 - Select PWM Counter 2's Wrap Value as TREQ - - - PWM_WRAP3 - 35 - Select PWM Counter 3's Wrap Value as TREQ - - - PWM_WRAP4 - 36 - Select PWM Counter 4's Wrap Value as TREQ - - - PWM_WRAP5 - 37 - Select PWM Counter 5's Wrap Value as TREQ - - - PWM_WRAP6 - 38 - Select PWM Counter 6's Wrap Value as TREQ - - - PWM_WRAP7 - 39 - Select PWM Counter 7's Wrap Value as TREQ - - - PWM_WRAP8 - 40 - Select PWM Counter 8's Wrap Value as TREQ - - - PWM_WRAP9 - 41 - Select PWM Counter 9's Wrap Value as TREQ - - - PWM_WRAP10 - 42 - Select PWM Counter 0's Wrap Value as TREQ - - - PWM_WRAP11 - 43 - Select PWM Counter 1's Wrap Value as TREQ - - - I2C0_TX - 44 - Select I2C0's TX FIFO as TREQ - - - I2C0_RX - 45 - Select I2C0's RX FIFO as TREQ - - - I2C1_TX - 46 - Select I2C1's TX FIFO as TREQ - - - I2C1_RX - 47 - Select I2C1's RX FIFO as TREQ - - - ADC - 48 - Select the ADC as TREQ - - - XIP_STREAM - 49 - Select the XIP Streaming FIFO as TREQ - - - XIP_QMITX - 50 - Select XIP_QMITX as TREQ - - - XIP_QMIRX - 51 - Select XIP_QMIRX as TREQ - - - HSTX - 52 - Select HSTX as TREQ - - - CORESIGHT - 53 - Select CORESIGHT as TREQ - - - SHA256 - 54 - Select SHA256 as TREQ - - - TIMER0 - 59 - Select Timer 0 as TREQ - - - TIMER1 - 60 - Select Timer 1 as TREQ - - - TIMER2 - 61 - Select Timer 2 as TREQ (Optional) - - - TIMER3 - 62 - Select Timer 3 as TREQ (Optional) - - - PERMANENT - 63 - Permanent request, for unpaced transfers. - - - - - CHAIN_TO - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. - - Note this field resets to 0, so channels 1 and above will chain to channel 0 by default. Set this field to avoid this behaviour. - [16:13] - read-write - - - RING_SEL - Select whether RING_SIZE applies to read or write addresses. - If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. - [12:12] - read-write - - - RING_SIZE - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. - - Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. - [11:8] - read-write - - - RING_NONE - 0 - - - - - INCR_WRITE_REV - If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer. - - If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. - [7:7] - read-write - - - INCR_WRITE - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. - - Generally this should be disabled for memory-to-peripheral transfers. - [6:6] - read-write - - - INCR_READ_REV - If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer. - - If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. - [5:5] - read-write - - - INCR_READ - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. - - Generally this should be disabled for peripheral-to-memory transfers. - [4:4] - read-write - - - DATA_SIZE - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. - [3:2] - read-write - - - SIZE_BYTE - 0 - - - SIZE_HALFWORD - 1 - - - SIZE_WORD - 2 - - - - - HIGH_PRIORITY - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. - - This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. - [1:1] - read-write - - - EN - DMA Channel Enable. - When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) - [0:0] - read-write - - - - - CH14_AL1_CTRL - 0x00000390 - Alias for channel 14 CTRL register - 0x00000000 - - - CH14_AL1_CTRL - [31:0] - read-write - - - - - CH14_AL1_READ_ADDR - 0x00000394 - Alias for channel 14 READ_ADDR register - 0x00000000 - - - CH14_AL1_READ_ADDR - [31:0] - read-write - - - - - CH14_AL1_WRITE_ADDR - 0x00000398 - Alias for channel 14 WRITE_ADDR register - 0x00000000 - - - CH14_AL1_WRITE_ADDR - [31:0] - read-write - - - - - CH14_AL1_TRANS_COUNT_TRIG - 0x0000039c - Alias for channel 14 TRANS_COUNT register - This is a trigger register (0xc). Writing a nonzero value will - reload the channel counter and start the channel. - 0x00000000 - - - CH14_AL1_TRANS_COUNT_TRIG - [31:0] - read-write - - - - - CH14_AL2_CTRL - 0x000003a0 - Alias for channel 14 CTRL register - 0x00000000 - - - CH14_AL2_CTRL - [31:0] - read-write - - - - - CH14_AL2_TRANS_COUNT - 0x000003a4 - Alias for channel 14 TRANS_COUNT register - 0x00000000 - - - CH14_AL2_TRANS_COUNT - [31:0] - read-write - - - - - CH14_AL2_READ_ADDR - 0x000003a8 - Alias for channel 14 READ_ADDR register - 0x00000000 - - - CH14_AL2_READ_ADDR - [31:0] - read-write - - - - - CH14_AL2_WRITE_ADDR_TRIG - 0x000003ac - Alias for channel 14 WRITE_ADDR register - This is a trigger register (0xc). Writing a nonzero value will - reload the channel counter and start the channel. - 0x00000000 - - - CH14_AL2_WRITE_ADDR_TRIG - [31:0] - read-write - - - - - CH14_AL3_CTRL - 0x000003b0 - Alias for channel 14 CTRL register - 0x00000000 - - - CH14_AL3_CTRL - [31:0] - read-write - - - - - CH14_AL3_WRITE_ADDR - 0x000003b4 - Alias for channel 14 WRITE_ADDR register - 0x00000000 - - - CH14_AL3_WRITE_ADDR - [31:0] - read-write - - - - - CH14_AL3_TRANS_COUNT - 0x000003b8 - Alias for channel 14 TRANS_COUNT register - 0x00000000 - - - CH14_AL3_TRANS_COUNT - [31:0] - read-write - - - - - CH14_AL3_READ_ADDR_TRIG - 0x000003bc - Alias for channel 14 READ_ADDR register - This is a trigger register (0xc). Writing a nonzero value will - reload the channel counter and start the channel. - 0x00000000 - - - CH14_AL3_READ_ADDR_TRIG - [31:0] - read-write - - - - - CH15_READ_ADDR - 0x000003c0 - DMA Channel 15 Read Address pointer - 0x00000000 - - - CH15_READ_ADDR - This register updates automatically each time a read completes. The current value is the next address to be read by this channel. - [31:0] - read-write - - - - - CH15_WRITE_ADDR - 0x000003c4 - DMA Channel 15 Write Address pointer - 0x00000000 - - - CH15_WRITE_ADDR - This register updates automatically each time a write completes. The current value is the next address to be written by this channel. - [31:0] - read-write - - - - - CH15_TRANS_COUNT - 0x000003c8 - DMA Channel 15 Transfer Count - 0x00000000 - - - MODE - When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. - - When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. - - When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. - - All other values are reserved. - [31:28] - read-write - - - NORMAL - 0 - - - TRIGGER_SELF - 1 - - - ENDLESS - 15 - - - - - COUNT - 28-bit transfer count (256 million transfers maximum). - - Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). - - When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. - - Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. - - The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. - [27:0] - read-write - - - - - CH15_CTRL_TRIG - 0x000003cc - DMA Channel 15 Control and Status - 0x00000000 - - - AHB_ERROR - Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. - [31:31] - read-only - - - READ_ERROR - If 1, the channel received a read bus error. Write one to clear. - READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) - [30:30] - read-write - oneToClear - - - WRITE_ERROR - If 1, the channel received a write bus error. Write one to clear. - WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) - [29:29] - read-write - oneToClear - - - BUSY - This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. - - To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. - [26:26] - read-only - - - SNIFF_EN - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. - - This allows checksum to be enabled or disabled on a per-control- block basis. - [25:25] - read-write - - - BSWAP - Apply byte-swap transformation to DMA data. - For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. - [24:24] - read-write - - - IRQ_QUIET - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. - - This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. - [23:23] - read-write - - - TREQ_SEL - Select a Transfer Request signal. - The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). - 0x0 to 0x3a -> select DREQ n as TREQ - [22:17] - read-write - - - PIO0_TX0 - 0 - Select PIO0's TX FIFO 0 as TREQ - - - PIO0_TX1 - 1 - Select PIO0's TX FIFO 1 as TREQ - - - PIO0_TX2 - 2 - Select PIO0's TX FIFO 2 as TREQ - - - PIO0_TX3 - 3 - Select PIO0's TX FIFO 3 as TREQ - - - PIO0_RX0 - 4 - Select PIO0's RX FIFO 0 as TREQ - - - PIO0_RX1 - 5 - Select PIO0's RX FIFO 1 as TREQ - - - PIO0_RX2 - 6 - Select PIO0's RX FIFO 2 as TREQ - - - PIO0_RX3 - 7 - Select PIO0's RX FIFO 3 as TREQ - - - PIO1_TX0 - 8 - Select PIO1's TX FIFO 0 as TREQ - - - PIO1_TX1 - 9 - Select PIO1's TX FIFO 1 as TREQ - - - PIO1_TX2 - 10 - Select PIO1's TX FIFO 2 as TREQ - - - PIO1_TX3 - 11 - Select PIO1's TX FIFO 3 as TREQ - - - PIO1_RX0 - 12 - Select PIO1's RX FIFO 0 as TREQ - - - PIO1_RX1 - 13 - Select PIO1's RX FIFO 1 as TREQ - - - PIO1_RX2 - 14 - Select PIO1's RX FIFO 2 as TREQ - - - PIO1_RX3 - 15 - Select PIO1's RX FIFO 3 as TREQ - - - PIO2_TX0 - 16 - Select PIO2's TX FIFO 0 as TREQ - - - PIO2_TX1 - 17 - Select PIO2's TX FIFO 1 as TREQ - - - PIO2_TX2 - 18 - Select PIO2's TX FIFO 2 as TREQ - - - PIO2_TX3 - 19 - Select PIO2's TX FIFO 3 as TREQ - - - PIO2_RX0 - 20 - Select PIO2's RX FIFO 0 as TREQ - - - PIO2_RX1 - 21 - Select PIO2's RX FIFO 1 as TREQ - - - PIO2_RX2 - 22 - Select PIO2's RX FIFO 2 as TREQ - - - PIO2_RX3 - 23 - Select PIO2's RX FIFO 3 as TREQ - - - SPI0_TX - 24 - Select SPI0's TX FIFO as TREQ - - - SPI0_RX - 25 - Select SPI0's RX FIFO as TREQ - - - SPI1_TX - 26 - Select SPI1's TX FIFO as TREQ - - - SPI1_RX - 27 - Select SPI1's RX FIFO as TREQ - - - UART0_TX - 28 - Select UART0's TX FIFO as TREQ - - - UART0_RX - 29 - Select UART0's RX FIFO as TREQ - - - UART1_TX - 30 - Select UART1's TX FIFO as TREQ - - - UART1_RX - 31 - Select UART1's RX FIFO as TREQ - - - PWM_WRAP0 - 32 - Select PWM Counter 0's Wrap Value as TREQ - - - PWM_WRAP1 - 33 - Select PWM Counter 1's Wrap Value as TREQ - - - PWM_WRAP2 - 34 - Select PWM Counter 2's Wrap Value as TREQ - - - PWM_WRAP3 - 35 - Select PWM Counter 3's Wrap Value as TREQ - - - PWM_WRAP4 - 36 - Select PWM Counter 4's Wrap Value as TREQ - - - PWM_WRAP5 - 37 - Select PWM Counter 5's Wrap Value as TREQ - - - PWM_WRAP6 - 38 - Select PWM Counter 6's Wrap Value as TREQ - - - PWM_WRAP7 - 39 - Select PWM Counter 7's Wrap Value as TREQ - - - PWM_WRAP8 - 40 - Select PWM Counter 8's Wrap Value as TREQ - - - PWM_WRAP9 - 41 - Select PWM Counter 9's Wrap Value as TREQ - - - PWM_WRAP10 - 42 - Select PWM Counter 0's Wrap Value as TREQ - - - PWM_WRAP11 - 43 - Select PWM Counter 1's Wrap Value as TREQ - - - I2C0_TX - 44 - Select I2C0's TX FIFO as TREQ - - - I2C0_RX - 45 - Select I2C0's RX FIFO as TREQ - - - I2C1_TX - 46 - Select I2C1's TX FIFO as TREQ - - - I2C1_RX - 47 - Select I2C1's RX FIFO as TREQ - - - ADC - 48 - Select the ADC as TREQ - - - XIP_STREAM - 49 - Select the XIP Streaming FIFO as TREQ - - - XIP_QMITX - 50 - Select XIP_QMITX as TREQ - - - XIP_QMIRX - 51 - Select XIP_QMIRX as TREQ - - - HSTX - 52 - Select HSTX as TREQ - - - CORESIGHT - 53 - Select CORESIGHT as TREQ - - - SHA256 - 54 - Select SHA256 as TREQ - - - TIMER0 - 59 - Select Timer 0 as TREQ - - - TIMER1 - 60 - Select Timer 1 as TREQ - - - TIMER2 - 61 - Select Timer 2 as TREQ (Optional) - - - TIMER3 - 62 - Select Timer 3 as TREQ (Optional) - - - PERMANENT - 63 - Permanent request, for unpaced transfers. - - - - - CHAIN_TO - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. - - Note this field resets to 0, so channels 1 and above will chain to channel 0 by default. Set this field to avoid this behaviour. - [16:13] - read-write - - - RING_SEL - Select whether RING_SIZE applies to read or write addresses. - If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. - [12:12] - read-write - - - RING_SIZE - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. - - Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. - [11:8] - read-write - - - RING_NONE - 0 - - - - - INCR_WRITE_REV - If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer. - - If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. - [7:7] - read-write - - - INCR_WRITE - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. - - Generally this should be disabled for memory-to-peripheral transfers. - [6:6] - read-write - - - INCR_READ_REV - If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer. - - If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. - [5:5] - read-write - - - INCR_READ - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. - - Generally this should be disabled for peripheral-to-memory transfers. - [4:4] - read-write - - - DATA_SIZE - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. - [3:2] - read-write - - - SIZE_BYTE - 0 - - - SIZE_HALFWORD - 1 - - - SIZE_WORD - 2 - - - - - HIGH_PRIORITY - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. - - This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. - [1:1] - read-write - - - EN - DMA Channel Enable. - When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) - [0:0] - read-write - - - - - CH15_AL1_CTRL - 0x000003d0 - Alias for channel 15 CTRL register - 0x00000000 - - - CH15_AL1_CTRL - [31:0] - read-write - - - - - CH15_AL1_READ_ADDR - 0x000003d4 - Alias for channel 15 READ_ADDR register - 0x00000000 - - - CH15_AL1_READ_ADDR - [31:0] - read-write - - - - - CH15_AL1_WRITE_ADDR - 0x000003d8 - Alias for channel 15 WRITE_ADDR register - 0x00000000 - - - CH15_AL1_WRITE_ADDR - [31:0] - read-write - - - - - CH15_AL1_TRANS_COUNT_TRIG - 0x000003dc - Alias for channel 15 TRANS_COUNT register - This is a trigger register (0xc). Writing a nonzero value will - reload the channel counter and start the channel. - 0x00000000 - - - CH15_AL1_TRANS_COUNT_TRIG - [31:0] - read-write - - - - - CH15_AL2_CTRL - 0x000003e0 - Alias for channel 15 CTRL register - 0x00000000 - - - CH15_AL2_CTRL - [31:0] - read-write - - - - - CH15_AL2_TRANS_COUNT - 0x000003e4 - Alias for channel 15 TRANS_COUNT register - 0x00000000 - - - CH15_AL2_TRANS_COUNT - [31:0] - read-write - - - - - CH15_AL2_READ_ADDR - 0x000003e8 - Alias for channel 15 READ_ADDR register - 0x00000000 - - - CH15_AL2_READ_ADDR - [31:0] - read-write - - - - - CH15_AL2_WRITE_ADDR_TRIG - 0x000003ec - Alias for channel 15 WRITE_ADDR register - This is a trigger register (0xc). Writing a nonzero value will - reload the channel counter and start the channel. - 0x00000000 - - - CH15_AL2_WRITE_ADDR_TRIG - [31:0] - read-write - - - - - CH15_AL3_CTRL - 0x000003f0 - Alias for channel 15 CTRL register - 0x00000000 - - - CH15_AL3_CTRL - [31:0] - read-write - - - - - CH15_AL3_WRITE_ADDR - 0x000003f4 - Alias for channel 15 WRITE_ADDR register - 0x00000000 - - - CH15_AL3_WRITE_ADDR - [31:0] - read-write - - - - - CH15_AL3_TRANS_COUNT - 0x000003f8 - Alias for channel 15 TRANS_COUNT register - 0x00000000 - - - CH15_AL3_TRANS_COUNT - [31:0] - read-write - - - - - CH15_AL3_READ_ADDR_TRIG - 0x000003fc - Alias for channel 15 READ_ADDR register - This is a trigger register (0xc). Writing a nonzero value will - reload the channel counter and start the channel. - 0x00000000 - - - CH15_AL3_READ_ADDR_TRIG - [31:0] - read-write - - - - - INTR - 0x00000400 - Interrupt Status (raw) - 0x00000000 - - - INTR - Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR or INTS0/1/2/3. - - Channel interrupts can be routed to either of four system-level IRQs based on INTE0, INTE1, INTE2 and INTE3. - - The multiple system-level interrupts might be used to allow NVIC IRQ preemption for more time-critical channels, to spread IRQ load across different cores, or to target IRQs to different security domains. - - It is also valid to ignore the multiple IRQs, and just use INTE0/INTS0/IRQ 0. - - If this register is accessed at a security/privilege level less than that of a given channel (as defined by that channel's SECCFG_CHx register), then that channel's interrupt status will read as 0, ignore writes. - [15:0] - read-write - oneToClear - - - - - INTE0 - 0x00000404 - Interrupt Enables for IRQ 0 - 0x00000000 - - - INTE0 - Set bit n to pass interrupts from channel n to DMA IRQ 0. - - Note this bit has no effect if the channel security/privilege level, defined by SECCFG_CHx, is greater than the IRQ security/privilege defined by SECCFG_IRQ0. - [15:0] - read-write - - - - - INTF0 - 0x00000408 - Force Interrupts - 0x00000000 - - - INTF0 - Write 1s to force the corresponding bits in INTS0. The interrupt remains asserted until INTF0 is cleared. - [15:0] - read-write - - - - - INTS0 - 0x0000040c - Interrupt Status for IRQ 0 - 0x00000000 - - - INTS0 - Indicates active channel interrupt requests which are currently causing IRQ 0 to be asserted. - Channel interrupts can be cleared by writing a bit mask here. - - Channels with a security/privilege (SECCFG_CHx) greater SECCFG_IRQ0) read as 0 in this register, and ignore writes. - [15:0] - read-write - oneToClear - - - - - INTR1 - 0x00000410 - Interrupt Status (raw) - 0x00000000 - - - INTR1 - Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR or INTS0/1/2/3. - - Channel interrupts can be routed to either of four system-level IRQs based on INTE0, INTE1, INTE2 and INTE3. - - The multiple system-level interrupts might be used to allow NVIC IRQ preemption for more time-critical channels, to spread IRQ load across different cores, or to target IRQs to different security domains. - - It is also valid to ignore the multiple IRQs, and just use INTE0/INTS0/IRQ 0. - - If this register is accessed at a security/privilege level less than that of a given channel (as defined by that channel's SECCFG_CHx register), then that channel's interrupt status will read as 0, ignore writes. - [15:0] - read-write - oneToClear - - - - - INTE1 - 0x00000414 - Interrupt Enables for IRQ 1 - 0x00000000 - - - INTE1 - Set bit n to pass interrupts from channel n to DMA IRQ 1. - - Note this bit has no effect if the channel security/privilege level, defined by SECCFG_CHx, is greater than the IRQ security/privilege defined by SECCFG_IRQ1. - [15:0] - read-write - - - - - INTF1 - 0x00000418 - Force Interrupts - 0x00000000 - - - INTF1 - Write 1s to force the corresponding bits in INTS1. The interrupt remains asserted until INTF1 is cleared. - [15:0] - read-write - - - - - INTS1 - 0x0000041c - Interrupt Status for IRQ 1 - 0x00000000 - - - INTS1 - Indicates active channel interrupt requests which are currently causing IRQ 1 to be asserted. - Channel interrupts can be cleared by writing a bit mask here. - - Channels with a security/privilege (SECCFG_CHx) greater SECCFG_IRQ1) read as 0 in this register, and ignore writes. - [15:0] - read-write - oneToClear - - - - - INTR2 - 0x00000420 - Interrupt Status (raw) - 0x00000000 - - - INTR2 - Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR or INTS0/1/2/3. - - Channel interrupts can be routed to either of four system-level IRQs based on INTE0, INTE1, INTE2 and INTE3. - - The multiple system-level interrupts might be used to allow NVIC IRQ preemption for more time-critical channels, to spread IRQ load across different cores, or to target IRQs to different security domains. - - It is also valid to ignore the multiple IRQs, and just use INTE0/INTS0/IRQ 0. - - If this register is accessed at a security/privilege level less than that of a given channel (as defined by that channel's SECCFG_CHx register), then that channel's interrupt status will read as 0, ignore writes. - [15:0] - read-write - oneToClear - - - - - INTE2 - 0x00000424 - Interrupt Enables for IRQ 2 - 0x00000000 - - - INTE2 - Set bit n to pass interrupts from channel n to DMA IRQ 2. - - Note this bit has no effect if the channel security/privilege level, defined by SECCFG_CHx, is greater than the IRQ security/privilege defined by SECCFG_IRQ2. - [15:0] - read-write - - - - - INTF2 - 0x00000428 - Force Interrupts - 0x00000000 - - - INTF2 - Write 1s to force the corresponding bits in INTS2. The interrupt remains asserted until INTF2 is cleared. - [15:0] - read-write - - - - - INTS2 - 0x0000042c - Interrupt Status for IRQ 2 - 0x00000000 - - - INTS2 - Indicates active channel interrupt requests which are currently causing IRQ 2 to be asserted. - Channel interrupts can be cleared by writing a bit mask here. - - Channels with a security/privilege (SECCFG_CHx) greater SECCFG_IRQ2) read as 0 in this register, and ignore writes. - [15:0] - read-write - oneToClear - - - - - INTR3 - 0x00000430 - Interrupt Status (raw) - 0x00000000 - - - INTR3 - Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR or INTS0/1/2/3. - - Channel interrupts can be routed to either of four system-level IRQs based on INTE0, INTE1, INTE2 and INTE3. - - The multiple system-level interrupts might be used to allow NVIC IRQ preemption for more time-critical channels, to spread IRQ load across different cores, or to target IRQs to different security domains. - - It is also valid to ignore the multiple IRQs, and just use INTE0/INTS0/IRQ 0. - - If this register is accessed at a security/privilege level less than that of a given channel (as defined by that channel's SECCFG_CHx register), then that channel's interrupt status will read as 0, ignore writes. - [15:0] - read-write - oneToClear - - - - - INTE3 - 0x00000434 - Interrupt Enables for IRQ 3 - 0x00000000 - - - INTE3 - Set bit n to pass interrupts from channel n to DMA IRQ 3. - - Note this bit has no effect if the channel security/privilege level, defined by SECCFG_CHx, is greater than the IRQ security/privilege defined by SECCFG_IRQ3. - [15:0] - read-write - - - - - INTF3 - 0x00000438 - Force Interrupts - 0x00000000 - - - INTF3 - Write 1s to force the corresponding bits in INTS3. The interrupt remains asserted until INTF3 is cleared. - [15:0] - read-write - - - - - INTS3 - 0x0000043c - Interrupt Status for IRQ 3 - 0x00000000 - - - INTS3 - Indicates active channel interrupt requests which are currently causing IRQ 3 to be asserted. - Channel interrupts can be cleared by writing a bit mask here. - - Channels with a security/privilege (SECCFG_CHx) greater SECCFG_IRQ3) read as 0 in this register, and ignore writes. - [15:0] - read-write - oneToClear - - - - - TIMER0 - 0x00000440 - Pacing (X/Y) fractional timer - The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. - 0x00000000 - - - X - Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer. - [31:16] - read-write - - - Y - Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer. - [15:0] - read-write - - - - - TIMER1 - 0x00000444 - Pacing (X/Y) fractional timer - The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. - 0x00000000 - - - X - Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer. - [31:16] - read-write - - - Y - Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer. - [15:0] - read-write - - - - - TIMER2 - 0x00000448 - Pacing (X/Y) fractional timer - The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. - 0x00000000 - - - X - Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer. - [31:16] - read-write - - - Y - Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer. - [15:0] - read-write - - - - - TIMER3 - 0x0000044c - Pacing (X/Y) fractional timer - The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. - 0x00000000 - - - X - Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer. - [31:16] - read-write - - - Y - Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer. - [15:0] - read-write - - - - - MULTI_CHAN_TRIGGER - 0x00000450 - Trigger one or more channels simultaneously - 0x00000000 - - - MULTI_CHAN_TRIGGER - Each bit in this register corresponds to a DMA channel. Writing a 1 to the relevant bit is the same as writing to that channel's trigger register; the channel will start if it is currently enabled and not already busy. - [15:0] - write-only - - - - - SNIFF_CTRL - 0x00000454 - Sniffer Control - 0x00000000 - - - OUT_INV - If set, the result appears inverted (bitwise complement) when read. This does not affect the way the checksum is calculated; the result is transformed on-the-fly between the result register and the bus. - [11:11] - read-write - - - OUT_REV - If set, the result appears bit-reversed when read. This does not affect the way the checksum is calculated; the result is transformed on-the-fly between the result register and the bus. - [10:10] - read-write - - - BSWAP - Locally perform a byte reverse on the sniffed data, before feeding into checksum. - - Note that the sniff hardware is downstream of the DMA channel byteswap performed in the read master: if channel CTRL_BSWAP and SNIFF_CTRL_BSWAP are both enabled, their effects cancel from the sniffer's point of view. - [9:9] - read-write - - - CALC - [8:5] - read-write - - - CRC32 - 0 - Calculate a CRC-32 (IEEE802.3 polynomial) - - - CRC32R - 1 - Calculate a CRC-32 (IEEE802.3 polynomial) with bit reversed data - - - CRC16 - 2 - Calculate a CRC-16-CCITT - - - CRC16R - 3 - Calculate a CRC-16-CCITT with bit reversed data - - - EVEN - 14 - XOR reduction over all data. == 1 if the total 1 population count is odd. - - - SUM - 15 - Calculate a simple 32-bit checksum (addition with a 32 bit accumulator) - - - - - DMACH - DMA channel for Sniffer to observe - [4:1] - read-write - - - EN - Enable sniffer - [0:0] - read-write - - - - - SNIFF_DATA - 0x00000458 - Data accumulator for sniff hardware - 0x00000000 - - - SNIFF_DATA - Write an initial seed value here before starting a DMA transfer on the channel indicated by SNIFF_CTRL_DMACH. The hardware will update this register each time it observes a read from the indicated channel. Once the channel completes, the final result can be read from this register. - [31:0] - read-write - - - - - FIFO_LEVELS - 0x00000460 - Debug RAF, WAF, TDF levels - 0x00000000 - - - RAF_LVL - Current Read-Address-FIFO fill level - [23:16] - read-only - - - WAF_LVL - Current Write-Address-FIFO fill level - [15:8] - read-only - - - TDF_LVL - Current Transfer-Data-FIFO fill level - [7:0] - read-only - - - - - CHAN_ABORT - 0x00000464 - Abort an in-progress transfer sequence on one or more channels - 0x00000000 - - - CHAN_ABORT - Each bit corresponds to a channel. Writing a 1 aborts whatever transfer sequence is in progress on that channel. The bit will remain high until any in-flight transfers have been flushed through the address and data FIFOs. - - After writing, this register must be polled until it returns all-zero. Until this point, it is unsafe to restart the channel. - [15:0] - write-only - - - - - N_CHANNELS - 0x00000468 - The number of channels this DMA instance is equipped with. This DMA supports up to 16 hardware channels, but can be configured with as few as one, to minimise silicon area. - 0x00000000 - - - N_CHANNELS - [4:0] - read-only - - - - - SECCFG_CH0 - 0x00000480 - Security configuration for channel 0. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. - - If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. - - This register automatically locks down (becomes read-only) once software starts to configure the channel. - - This register is world-readable, but is writable only from a Secure, Privileged context. - 0x00000003 - - - LOCK - LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. - - Once its LOCK bit is set, this register becomes read-only. - - A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit. - [2:2] - read-write - - - S - Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. - - If 1, this channel is controllable only from a Secure context. - [1:1] - read-write - - - P - Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. - - If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. - [0:0] - read-write - - - - - SECCFG_CH1 - 0x00000484 - Security configuration for channel 1. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. - - If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. - - This register automatically locks down (becomes read-only) once software starts to configure the channel. - - This register is world-readable, but is writable only from a Secure, Privileged context. - 0x00000003 - - - LOCK - LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. - - Once its LOCK bit is set, this register becomes read-only. - - A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit. - [2:2] - read-write - - - S - Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. - - If 1, this channel is controllable only from a Secure context. - [1:1] - read-write - - - P - Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. - - If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. - [0:0] - read-write - - - - - SECCFG_CH2 - 0x00000488 - Security configuration for channel 2. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. - - If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. - - This register automatically locks down (becomes read-only) once software starts to configure the channel. - - This register is world-readable, but is writable only from a Secure, Privileged context. - 0x00000003 - - - LOCK - LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. - - Once its LOCK bit is set, this register becomes read-only. - - A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit. - [2:2] - read-write - - - S - Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. - - If 1, this channel is controllable only from a Secure context. - [1:1] - read-write - - - P - Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. - - If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. - [0:0] - read-write - - - - - SECCFG_CH3 - 0x0000048c - Security configuration for channel 3. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. - - If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. - - This register automatically locks down (becomes read-only) once software starts to configure the channel. - - This register is world-readable, but is writable only from a Secure, Privileged context. - 0x00000003 - - - LOCK - LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. - - Once its LOCK bit is set, this register becomes read-only. - - A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit. - [2:2] - read-write - - - S - Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. - - If 1, this channel is controllable only from a Secure context. - [1:1] - read-write - - - P - Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. - - If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. - [0:0] - read-write - - - - - SECCFG_CH4 - 0x00000490 - Security configuration for channel 4. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. - - If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. - - This register automatically locks down (becomes read-only) once software starts to configure the channel. - - This register is world-readable, but is writable only from a Secure, Privileged context. - 0x00000003 - - - LOCK - LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. - - Once its LOCK bit is set, this register becomes read-only. - - A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit. - [2:2] - read-write - - - S - Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. - - If 1, this channel is controllable only from a Secure context. - [1:1] - read-write - - - P - Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. - - If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. - [0:0] - read-write - - - - - SECCFG_CH5 - 0x00000494 - Security configuration for channel 5. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. - - If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. - - This register automatically locks down (becomes read-only) once software starts to configure the channel. - - This register is world-readable, but is writable only from a Secure, Privileged context. - 0x00000003 - - - LOCK - LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. - - Once its LOCK bit is set, this register becomes read-only. - - A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit. - [2:2] - read-write - - - S - Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. - - If 1, this channel is controllable only from a Secure context. - [1:1] - read-write - - - P - Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. - - If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. - [0:0] - read-write - - - - - SECCFG_CH6 - 0x00000498 - Security configuration for channel 6. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. - - If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. - - This register automatically locks down (becomes read-only) once software starts to configure the channel. - - This register is world-readable, but is writable only from a Secure, Privileged context. - 0x00000003 - - - LOCK - LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. - - Once its LOCK bit is set, this register becomes read-only. - - A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit. - [2:2] - read-write - - - S - Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. - - If 1, this channel is controllable only from a Secure context. - [1:1] - read-write - - - P - Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. - - If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. - [0:0] - read-write - - - - - SECCFG_CH7 - 0x0000049c - Security configuration for channel 7. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. - - If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. - - This register automatically locks down (becomes read-only) once software starts to configure the channel. - - This register is world-readable, but is writable only from a Secure, Privileged context. - 0x00000003 - - - LOCK - LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. - - Once its LOCK bit is set, this register becomes read-only. - - A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit. - [2:2] - read-write - - - S - Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. - - If 1, this channel is controllable only from a Secure context. - [1:1] - read-write - - - P - Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. - - If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. - [0:0] - read-write - - - - - SECCFG_CH8 - 0x000004a0 - Security configuration for channel 8. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. - - If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. - - This register automatically locks down (becomes read-only) once software starts to configure the channel. - - This register is world-readable, but is writable only from a Secure, Privileged context. - 0x00000003 - - - LOCK - LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. - - Once its LOCK bit is set, this register becomes read-only. - - A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit. - [2:2] - read-write - - - S - Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. - - If 1, this channel is controllable only from a Secure context. - [1:1] - read-write - - - P - Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. - - If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. - [0:0] - read-write - - - - - SECCFG_CH9 - 0x000004a4 - Security configuration for channel 9. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. - - If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. - - This register automatically locks down (becomes read-only) once software starts to configure the channel. - - This register is world-readable, but is writable only from a Secure, Privileged context. - 0x00000003 - - - LOCK - LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. - - Once its LOCK bit is set, this register becomes read-only. - - A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit. - [2:2] - read-write - - - S - Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. - - If 1, this channel is controllable only from a Secure context. - [1:1] - read-write - - - P - Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. - - If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. - [0:0] - read-write - - - - - SECCFG_CH10 - 0x000004a8 - Security configuration for channel 10. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. - - If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. - - This register automatically locks down (becomes read-only) once software starts to configure the channel. - - This register is world-readable, but is writable only from a Secure, Privileged context. - 0x00000003 - - - LOCK - LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. - - Once its LOCK bit is set, this register becomes read-only. - - A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit. - [2:2] - read-write - - - S - Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. - - If 1, this channel is controllable only from a Secure context. - [1:1] - read-write - - - P - Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. - - If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. - [0:0] - read-write - - - - - SECCFG_CH11 - 0x000004ac - Security configuration for channel 11. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. - - If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. - - This register automatically locks down (becomes read-only) once software starts to configure the channel. - - This register is world-readable, but is writable only from a Secure, Privileged context. - 0x00000003 - - - LOCK - LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. - - Once its LOCK bit is set, this register becomes read-only. - - A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit. - [2:2] - read-write - - - S - Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. - - If 1, this channel is controllable only from a Secure context. - [1:1] - read-write - - - P - Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. - - If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. - [0:0] - read-write - - - - - SECCFG_CH12 - 0x000004b0 - Security configuration for channel 12. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. - - If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. - - This register automatically locks down (becomes read-only) once software starts to configure the channel. - - This register is world-readable, but is writable only from a Secure, Privileged context. - 0x00000003 - - - LOCK - LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. - - Once its LOCK bit is set, this register becomes read-only. - - A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit. - [2:2] - read-write - - - S - Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. - - If 1, this channel is controllable only from a Secure context. - [1:1] - read-write - - - P - Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. - - If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. - [0:0] - read-write - - - - - SECCFG_CH13 - 0x000004b4 - Security configuration for channel 13. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. - - If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. - - This register automatically locks down (becomes read-only) once software starts to configure the channel. - - This register is world-readable, but is writable only from a Secure, Privileged context. - 0x00000003 - - - LOCK - LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. - - Once its LOCK bit is set, this register becomes read-only. - - A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit. - [2:2] - read-write - - - S - Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. - - If 1, this channel is controllable only from a Secure context. - [1:1] - read-write - - - P - Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. - - If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. - [0:0] - read-write - - - - - SECCFG_CH14 - 0x000004b8 - Security configuration for channel 14. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. - - If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. - - This register automatically locks down (becomes read-only) once software starts to configure the channel. - - This register is world-readable, but is writable only from a Secure, Privileged context. - 0x00000003 - - - LOCK - LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. - - Once its LOCK bit is set, this register becomes read-only. - - A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit. - [2:2] - read-write - - - S - Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. - - If 1, this channel is controllable only from a Secure context. - [1:1] - read-write - - - P - Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. - - If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. - [0:0] - read-write - - - - - SECCFG_CH15 - 0x000004bc - Security configuration for channel 15. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. - - If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. - - This register automatically locks down (becomes read-only) once software starts to configure the channel. - - This register is world-readable, but is writable only from a Secure, Privileged context. - 0x00000003 - - - LOCK - LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. - - Once its LOCK bit is set, this register becomes read-only. - - A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit. - [2:2] - read-write - - - S - Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. - - If 1, this channel is controllable only from a Secure context. - [1:1] - read-write - - - P - Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. - - If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. - [0:0] - read-write - - - - - SECCFG_IRQ0 - 0x000004c0 - Security configuration for IRQ 0. Control whether the IRQ permits configuration by Non-secure/Unprivileged contexts, and whether it can observe Secure/Privileged channel interrupt flags. - 0x00000003 - - - S - Secure IRQ. If 1, this IRQ's control registers can only be accessed from a Secure context. - - If 0, this IRQ's control registers can be accessed from a Non-secure context, but Secure channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Secure channels. - [1:1] - read-write - - - P - Privileged IRQ. If 1, this IRQ's control registers can only be accessed from a Privileged context. - - If 0, this IRQ's control registers can be accessed from an Unprivileged context, but Privileged channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Privileged channels. - [0:0] - read-write - - - - - SECCFG_IRQ1 - 0x000004c4 - Security configuration for IRQ 1. Control whether the IRQ permits configuration by Non-secure/Unprivileged contexts, and whether it can observe Secure/Privileged channel interrupt flags. - 0x00000003 - - - S - Secure IRQ. If 1, this IRQ's control registers can only be accessed from a Secure context. - - If 0, this IRQ's control registers can be accessed from a Non-secure context, but Secure channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Secure channels. - [1:1] - read-write - - - P - Privileged IRQ. If 1, this IRQ's control registers can only be accessed from a Privileged context. - - If 0, this IRQ's control registers can be accessed from an Unprivileged context, but Privileged channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Privileged channels. - [0:0] - read-write - - - - - SECCFG_IRQ2 - 0x000004c8 - Security configuration for IRQ 2. Control whether the IRQ permits configuration by Non-secure/Unprivileged contexts, and whether it can observe Secure/Privileged channel interrupt flags. - 0x00000003 - - - S - Secure IRQ. If 1, this IRQ's control registers can only be accessed from a Secure context. - - If 0, this IRQ's control registers can be accessed from a Non-secure context, but Secure channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Secure channels. - [1:1] - read-write - - - P - Privileged IRQ. If 1, this IRQ's control registers can only be accessed from a Privileged context. - - If 0, this IRQ's control registers can be accessed from an Unprivileged context, but Privileged channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Privileged channels. - [0:0] - read-write - - - - - SECCFG_IRQ3 - 0x000004cc - Security configuration for IRQ 3. Control whether the IRQ permits configuration by Non-secure/Unprivileged contexts, and whether it can observe Secure/Privileged channel interrupt flags. - 0x00000003 - - - S - Secure IRQ. If 1, this IRQ's control registers can only be accessed from a Secure context. - - If 0, this IRQ's control registers can be accessed from a Non-secure context, but Secure channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Secure channels. - [1:1] - read-write - - - P - Privileged IRQ. If 1, this IRQ's control registers can only be accessed from a Privileged context. - - If 0, this IRQ's control registers can be accessed from an Unprivileged context, but Privileged channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Privileged channels. - [0:0] - read-write - - - - - SECCFG_MISC - 0x000004d0 - Miscellaneous security configuration - 0x000003ff - - - TIMER3_S - If 1, the TIMER3 register is only accessible from a Secure context, and timer DREQ 3 is only visible to Secure channels. - [9:9] - read-write - - - TIMER3_P - If 1, the TIMER3 register is only accessible from a Privileged (or more Secure) context, and timer DREQ 3 is only visible to Privileged (or more Secure) channels. - [8:8] - read-write - - - TIMER2_S - If 1, the TIMER2 register is only accessible from a Secure context, and timer DREQ 2 is only visible to Secure channels. - [7:7] - read-write - - - TIMER2_P - If 1, the TIMER2 register is only accessible from a Privileged (or more Secure) context, and timer DREQ 2 is only visible to Privileged (or more Secure) channels. - [6:6] - read-write - - - TIMER1_S - If 1, the TIMER1 register is only accessible from a Secure context, and timer DREQ 1 is only visible to Secure channels. - [5:5] - read-write - - - TIMER1_P - If 1, the TIMER1 register is only accessible from a Privileged (or more Secure) context, and timer DREQ 1 is only visible to Privileged (or more Secure) channels. - [4:4] - read-write - - - TIMER0_S - If 1, the TIMER0 register is only accessible from a Secure context, and timer DREQ 0 is only visible to Secure channels. - [3:3] - read-write - - - TIMER0_P - If 1, the TIMER0 register is only accessible from a Privileged (or more Secure) context, and timer DREQ 0 is only visible to Privileged (or more Secure) channels. - [2:2] - read-write - - - SNIFF_S - If 1, the sniffer can see data transfers from Secure channels, and can itself only be accessed from a Secure context. - - If 0, the sniffer can be accessed from either a Secure or Non-secure context, but can not see data transfers of Secure channels. - [1:1] - read-write - - - SNIFF_P - If 1, the sniffer can see data transfers from Privileged channels, and can itself only be accessed from a privileged context, or from a Secure context when SNIFF_S is 0. - - If 0, the sniffer can be accessed from either a Privileged or Unprivileged context (with sufficient security level) but can not see transfers from Privileged channels. - [0:0] - read-write - - - - - MPU_CTRL - 0x00000500 - Control register for DMA MPU. Accessible only from a Privileged context. - 0x00000000 - - - NS_HIDE_ADDR - By default, when a region's S bit is clear, Non-secure-Privileged reads can see the region's base address and limit address. Set this bit to make the addresses appear as 0 to Non-secure reads, even when the region is Non-secure, to avoid leaking information about the processor SAU map. - [3:3] - read-write - - - S - Determine whether an address not covered by an active MPU region is Secure (1) or Non-secure (0) - [2:2] - read-write - - - P - Determine whether an address not covered by an active MPU region is Privileged (1) or Unprivileged (0) - [1:1] - read-write - - - - - MPU_BAR0 - 0x00000504 - Base address register for MPU region 0. Writable only from a Secure, Privileged context. - 0x00000000 - - - ADDR - This MPU region matches addresses where addr[31:5] (the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. - - Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context. - [31:5] - read-write - - - - - MPU_LAR0 - 0x00000508 - Limit address register for MPU region 0. Writable only from a Secure, Privileged context, with the exception of the P bit. - 0x00000000 - - - ADDR - Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context. - [31:5] - read-write - - - S - Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled. - [2:2] - read-write - - - P - Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context. - [1:1] - read-write - - - EN - Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P. - [0:0] - read-write - - - - - MPU_BAR1 - 0x0000050c - Base address register for MPU region 1. Writable only from a Secure, Privileged context. - 0x00000000 - - - ADDR - This MPU region matches addresses where addr[31:5] (the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. - - Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context. - [31:5] - read-write - - - - - MPU_LAR1 - 0x00000510 - Limit address register for MPU region 1. Writable only from a Secure, Privileged context, with the exception of the P bit. - 0x00000000 - - - ADDR - Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context. - [31:5] - read-write - - - S - Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled. - [2:2] - read-write - - - P - Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context. - [1:1] - read-write - - - EN - Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P. - [0:0] - read-write - - - - - MPU_BAR2 - 0x00000514 - Base address register for MPU region 2. Writable only from a Secure, Privileged context. - 0x00000000 - - - ADDR - This MPU region matches addresses where addr[31:5] (the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. - - Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context. - [31:5] - read-write - - - - - MPU_LAR2 - 0x00000518 - Limit address register for MPU region 2. Writable only from a Secure, Privileged context, with the exception of the P bit. - 0x00000000 - - - ADDR - Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context. - [31:5] - read-write - - - S - Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled. - [2:2] - read-write - - - P - Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context. - [1:1] - read-write - - - EN - Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P. - [0:0] - read-write - - - - - MPU_BAR3 - 0x0000051c - Base address register for MPU region 3. Writable only from a Secure, Privileged context. - 0x00000000 - - - ADDR - This MPU region matches addresses where addr[31:5] (the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. - - Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context. - [31:5] - read-write - - - - - MPU_LAR3 - 0x00000520 - Limit address register for MPU region 3. Writable only from a Secure, Privileged context, with the exception of the P bit. - 0x00000000 - - - ADDR - Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context. - [31:5] - read-write - - - S - Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled. - [2:2] - read-write - - - P - Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context. - [1:1] - read-write - - - EN - Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P. - [0:0] - read-write - - - - - MPU_BAR4 - 0x00000524 - Base address register for MPU region 4. Writable only from a Secure, Privileged context. - 0x00000000 - - - ADDR - This MPU region matches addresses where addr[31:5] (the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. - - Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context. - [31:5] - read-write - - - - - MPU_LAR4 - 0x00000528 - Limit address register for MPU region 4. Writable only from a Secure, Privileged context, with the exception of the P bit. - 0x00000000 - - - ADDR - Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context. - [31:5] - read-write - - - S - Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled. - [2:2] - read-write - - - P - Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context. - [1:1] - read-write - - - EN - Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P. - [0:0] - read-write - - - - - MPU_BAR5 - 0x0000052c - Base address register for MPU region 5. Writable only from a Secure, Privileged context. - 0x00000000 - - - ADDR - This MPU region matches addresses where addr[31:5] (the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. - - Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context. - [31:5] - read-write - - - - - MPU_LAR5 - 0x00000530 - Limit address register for MPU region 5. Writable only from a Secure, Privileged context, with the exception of the P bit. - 0x00000000 - - - ADDR - Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context. - [31:5] - read-write - - - S - Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled. - [2:2] - read-write - - - P - Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context. - [1:1] - read-write - - - EN - Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P. - [0:0] - read-write - - - - - MPU_BAR6 - 0x00000534 - Base address register for MPU region 6. Writable only from a Secure, Privileged context. - 0x00000000 - - - ADDR - This MPU region matches addresses where addr[31:5] (the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. - - Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context. - [31:5] - read-write - - - - - MPU_LAR6 - 0x00000538 - Limit address register for MPU region 6. Writable only from a Secure, Privileged context, with the exception of the P bit. - 0x00000000 - - - ADDR - Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context. - [31:5] - read-write - - - S - Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled. - [2:2] - read-write - - - P - Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context. - [1:1] - read-write - - - EN - Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P. - [0:0] - read-write - - - - - MPU_BAR7 - 0x0000053c - Base address register for MPU region 7. Writable only from a Secure, Privileged context. - 0x00000000 - - - ADDR - This MPU region matches addresses where addr[31:5] (the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. - - Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context. - [31:5] - read-write - - - - - MPU_LAR7 - 0x00000540 - Limit address register for MPU region 7. Writable only from a Secure, Privileged context, with the exception of the P bit. - 0x00000000 - - - ADDR - Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context. - [31:5] - read-write - - - S - Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled. - [2:2] - read-write - - - P - Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context. - [1:1] - read-write - - - EN - Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P. - [0:0] - read-write - - - - - CH0_DBG_CTDREQ - 0x00000800 - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. - 0x00000000 - - - CH0_DBG_CTDREQ - [5:0] - read-write - oneToClear - - - - - CH0_DBG_TCR - 0x00000804 - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer - 0x00000000 - - - CH0_DBG_TCR - [31:0] - read-only - - - - - CH1_DBG_CTDREQ - 0x00000840 - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. - 0x00000000 - - - CH1_DBG_CTDREQ - [5:0] - read-write - oneToClear - - - - - CH1_DBG_TCR - 0x00000844 - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer - 0x00000000 - - - CH1_DBG_TCR - [31:0] - read-only - - - - - CH2_DBG_CTDREQ - 0x00000880 - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. - 0x00000000 - - - CH2_DBG_CTDREQ - [5:0] - read-write - oneToClear - - - - - CH2_DBG_TCR - 0x00000884 - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer - 0x00000000 - - - CH2_DBG_TCR - [31:0] - read-only - - - - - CH3_DBG_CTDREQ - 0x000008c0 - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. - 0x00000000 - - - CH3_DBG_CTDREQ - [5:0] - read-write - oneToClear - - - - - CH3_DBG_TCR - 0x000008c4 - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer - 0x00000000 - - - CH3_DBG_TCR - [31:0] - read-only - - - - - CH4_DBG_CTDREQ - 0x00000900 - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. - 0x00000000 - - - CH4_DBG_CTDREQ - [5:0] - read-write - oneToClear - - - - - CH4_DBG_TCR - 0x00000904 - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer - 0x00000000 - - - CH4_DBG_TCR - [31:0] - read-only - - - - - CH5_DBG_CTDREQ - 0x00000940 - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. - 0x00000000 - - - CH5_DBG_CTDREQ - [5:0] - read-write - oneToClear - - - - - CH5_DBG_TCR - 0x00000944 - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer - 0x00000000 - - - CH5_DBG_TCR - [31:0] - read-only - - - - - CH6_DBG_CTDREQ - 0x00000980 - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. - 0x00000000 - - - CH6_DBG_CTDREQ - [5:0] - read-write - oneToClear - - - - - CH6_DBG_TCR - 0x00000984 - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer - 0x00000000 - - - CH6_DBG_TCR - [31:0] - read-only - - - - - CH7_DBG_CTDREQ - 0x000009c0 - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. - 0x00000000 - - - CH7_DBG_CTDREQ - [5:0] - read-write - oneToClear - - - - - CH7_DBG_TCR - 0x000009c4 - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer - 0x00000000 - - - CH7_DBG_TCR - [31:0] - read-only - - - - - CH8_DBG_CTDREQ - 0x00000a00 - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. - 0x00000000 - - - CH8_DBG_CTDREQ - [5:0] - read-write - oneToClear - - - - - CH8_DBG_TCR - 0x00000a04 - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer - 0x00000000 - - - CH8_DBG_TCR - [31:0] - read-only - - - - - CH9_DBG_CTDREQ - 0x00000a40 - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. - 0x00000000 - - - CH9_DBG_CTDREQ - [5:0] - read-write - oneToClear - - - - - CH9_DBG_TCR - 0x00000a44 - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer - 0x00000000 - - - CH9_DBG_TCR - [31:0] - read-only - - - - - CH10_DBG_CTDREQ - 0x00000a80 - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. - 0x00000000 - - - CH10_DBG_CTDREQ - [5:0] - read-write - oneToClear - - - - - CH10_DBG_TCR - 0x00000a84 - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer - 0x00000000 - - - CH10_DBG_TCR - [31:0] - read-only - - - - - CH11_DBG_CTDREQ - 0x00000ac0 - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. - 0x00000000 - - - CH11_DBG_CTDREQ - [5:0] - read-write - oneToClear - - - - - CH11_DBG_TCR - 0x00000ac4 - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer - 0x00000000 - - - CH11_DBG_TCR - [31:0] - read-only - - - - - CH12_DBG_CTDREQ - 0x00000b00 - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. - 0x00000000 - - - CH12_DBG_CTDREQ - [5:0] - read-write - oneToClear - - - - - CH12_DBG_TCR - 0x00000b04 - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer - 0x00000000 - - - CH12_DBG_TCR - [31:0] - read-only - - - - - CH13_DBG_CTDREQ - 0x00000b40 - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. - 0x00000000 - - - CH13_DBG_CTDREQ - [5:0] - read-write - oneToClear - - - - - CH13_DBG_TCR - 0x00000b44 - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer - 0x00000000 - - - CH13_DBG_TCR - [31:0] - read-only - - - - - CH14_DBG_CTDREQ - 0x00000b80 - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. - 0x00000000 - - - CH14_DBG_CTDREQ - [5:0] - read-write - oneToClear - - - - - CH14_DBG_TCR - 0x00000b84 - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer - 0x00000000 - - - CH14_DBG_TCR - [31:0] - read-only - - - - - CH15_DBG_CTDREQ - 0x00000bc0 - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. - 0x00000000 - - - CH15_DBG_CTDREQ - [5:0] - read-write - oneToClear - - - - - CH15_DBG_TCR - 0x00000bc4 - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer - 0x00000000 - - - CH15_DBG_TCR - [31:0] - read-only - - - - - - - TIMER0 - Controls time and alarms - - time is a 64 bit value indicating the time since power-on - - timeh is the top 32 bits of time & timel is the bottom 32 bits to change time write to timelw before timehw to read time read from timelr before timehr - - An alarm is set by setting alarm_enable and writing to the corresponding alarm register When an alarm is pending, the corresponding alarm_running signal will be high An alarm can be cancelled before it has finished by clearing the alarm_enable When an alarm fires, the corresponding alarm_irq is set and alarm_running is cleared To clear the interrupt write a 1 to the corresponding alarm_irq The timer can be locked to prevent writing - 0x400b0000 - - 0 - 76 - registers - - - TIMER0_IRQ_0 - 0 - - - TIMER0_IRQ_1 - 1 - - - TIMER0_IRQ_2 - 2 - - - TIMER0_IRQ_3 - 3 - - - - TIMEHW - 0x00000000 - Write to bits 63:32 of time always write timelw before timehw - 0x00000000 - - - TIMEHW - [31:0] - write-only - - - - - TIMELW - 0x00000004 - Write to bits 31:0 of time writes do not get copied to time until timehw is written - 0x00000000 - - - TIMELW - [31:0] - write-only - - - - - TIMEHR - 0x00000008 - Read from bits 63:32 of time always read timelr before timehr - 0x00000000 - - - TIMEHR - [31:0] - read-only - - - - - TIMELR - 0x0000000c - Read from bits 31:0 of time - 0x00000000 - - - TIMELR - [31:0] - read-only - modify - - - - - ALARM0 - 0x00000010 - Arm alarm 0, and configure the time it will fire. Once armed, the alarm fires when TIMER_ALARM0 == TIMELR. The alarm will disarm itself once it fires, and can be disarmed early using the ARMED status register. - 0x00000000 - - - ALARM0 - [31:0] - read-write - - - - - ALARM1 - 0x00000014 - Arm alarm 1, and configure the time it will fire. Once armed, the alarm fires when TIMER_ALARM1 == TIMELR. The alarm will disarm itself once it fires, and can be disarmed early using the ARMED status register. - 0x00000000 - - - ALARM1 - [31:0] - read-write - - - - - ALARM2 - 0x00000018 - Arm alarm 2, and configure the time it will fire. Once armed, the alarm fires when TIMER_ALARM2 == TIMELR. The alarm will disarm itself once it fires, and can be disarmed early using the ARMED status register. - 0x00000000 - - - ALARM2 - [31:0] - read-write - - - - - ALARM3 - 0x0000001c - Arm alarm 3, and configure the time it will fire. Once armed, the alarm fires when TIMER_ALARM3 == TIMELR. The alarm will disarm itself once it fires, and can be disarmed early using the ARMED status register. - 0x00000000 - - - ALARM3 - [31:0] - read-write - - - - - ARMED - 0x00000020 - Indicates the armed/disarmed status of each alarm. A write to the corresponding ALARMx register arms the alarm. Alarms automatically disarm upon firing, but writing ones here will disarm immediately without waiting to fire. - 0x00000000 - - - ARMED - [3:0] - read-write - oneToClear - - - - - TIMERAWH - 0x00000024 - Raw read from bits 63:32 of time (no side effects) - 0x00000000 - - - TIMERAWH - [31:0] - read-only - - - - - TIMERAWL - 0x00000028 - Raw read from bits 31:0 of time (no side effects) - 0x00000000 - - - TIMERAWL - [31:0] - read-only - - - - - DBGPAUSE - 0x0000002c - Set bits high to enable pause when the corresponding debug ports are active - 0x00000007 - - - DBG1 - Pause when processor 1 is in debug mode - [2:2] - read-write - - - DBG0 - Pause when processor 0 is in debug mode - [1:1] - read-write - - - - - PAUSE - 0x00000030 - Set high to pause the timer - 0x00000000 - - - PAUSE - [0:0] - read-write - - - - - LOCKED - 0x00000034 - Set locked bit to disable write access to timer Once set, cannot be cleared (without a reset) - 0x00000000 - - - LOCKED - [0:0] - read-write - - - - - SOURCE - 0x00000038 - Selects the source for the timer. Defaults to the normal tick configured in the ticks block (typically configured to 1 microsecond). Writing to 1 will ignore the tick and count clk_sys cycles instead. - 0x00000000 - - - CLK_SYS - [0:0] - read-write - - - TICK - 0 - - - CLK_SYS - 1 - - - - - - - INTR - 0x0000003c - Raw Interrupts - 0x00000000 - - - ALARM_3 - [3:3] - read-write - oneToClear - - - ALARM_2 - [2:2] - read-write - oneToClear - - - ALARM_1 - [1:1] - read-write - oneToClear - - - ALARM_0 - [0:0] - read-write - oneToClear - - - - - INTE - 0x00000040 - Interrupt Enable - 0x00000000 - - - ALARM_3 - [3:3] - read-write - - - ALARM_2 - [2:2] - read-write - - - ALARM_1 - [1:1] - read-write - - - ALARM_0 - [0:0] - read-write - - - - - INTF - 0x00000044 - Interrupt Force - 0x00000000 - - - ALARM_3 - [3:3] - read-write - - - ALARM_2 - [2:2] - read-write - - - ALARM_1 - [1:1] - read-write - - - ALARM_0 - [0:0] - read-write - - - - - INTS - 0x00000048 - Interrupt status after masking & forcing - 0x00000000 - - - ALARM_3 - [3:3] - read-only - - - ALARM_2 - [2:2] - read-only - - - ALARM_1 - [1:1] - read-only - - - ALARM_0 - [0:0] - read-only - - - - - - - TIMER1 - 0x400b8000 - - TIMER1_IRQ_0 - 4 - - - TIMER1_IRQ_1 - 5 - - - TIMER1_IRQ_2 - 6 - - - TIMER1_IRQ_3 - 7 - - - - PWM - Simple PWM - 0x400a8000 - - 0 - 272 - registers - - - PWM_IRQ_WRAP_0 - 8 - - - PWM_IRQ_WRAP_1 - 9 - - - - CH0_CSR - 0x00000000 - Control and status register - 0x00000000 - - - PH_ADV - Advance the phase of the counter by 1 count, while it is running. - Self-clearing. Write a 1, and poll until low. Counter must be running - at less than full speed (div_int + div_frac / 16 > 1) - [7:7] - write-only - - - PH_RET - Retard the phase of the counter by 1 count, while it is running. - Self-clearing. Write a 1, and poll until low. Counter must be running. - [6:6] - write-only - - - DIVMODE - [5:4] - read-write - - - div - 0 - Free-running counting at rate dictated by fractional divider - - - level - 1 - Fractional divider operation is gated by the PWM B pin. - - - rise - 2 - Counter advances with each rising edge of the PWM B pin. - - - fall - 3 - Counter advances with each falling edge of the PWM B pin. - - - - - B_INV - Invert output B - [3:3] - read-write - - - A_INV - Invert output A - [2:2] - read-write - - - PH_CORRECT - 1: Enable phase-correct modulation. 0: Trailing-edge - [1:1] - read-write - - - EN - Enable the PWM channel. - [0:0] - read-write - - - - - CH0_DIV - 0x00000004 - INT and FRAC form a fixed-point fractional number. - Counting rate is system clock frequency divided by this number. - Fractional division uses simple 1st-order sigma-delta. - 0x00000010 - - - INT - [11:4] - read-write - - - FRAC - [3:0] - read-write - - - - - CH0_CTR - 0x00000008 - Direct access to the PWM counter - 0x00000000 - - - CH0_CTR - [15:0] - read-write - - - - - CH0_CC - 0x0000000c - Counter compare values - 0x00000000 - - - B - [31:16] - read-write - - - A - [15:0] - read-write - - - - - CH0_TOP - 0x00000010 - Counter wrap value - 0x0000ffff - - - CH0_TOP - [15:0] - read-write - - - - - CH1_CSR - 0x00000014 - Control and status register - 0x00000000 - - - PH_ADV - Advance the phase of the counter by 1 count, while it is running. - Self-clearing. Write a 1, and poll until low. Counter must be running - at less than full speed (div_int + div_frac / 16 > 1) - [7:7] - write-only - - - PH_RET - Retard the phase of the counter by 1 count, while it is running. - Self-clearing. Write a 1, and poll until low. Counter must be running. - [6:6] - write-only - - - DIVMODE - [5:4] - read-write - - - div - 0 - Free-running counting at rate dictated by fractional divider - - - level - 1 - Fractional divider operation is gated by the PWM B pin. - - - rise - 2 - Counter advances with each rising edge of the PWM B pin. - - - fall - 3 - Counter advances with each falling edge of the PWM B pin. - - - - - B_INV - Invert output B - [3:3] - read-write - - - A_INV - Invert output A - [2:2] - read-write - - - PH_CORRECT - 1: Enable phase-correct modulation. 0: Trailing-edge - [1:1] - read-write - - - EN - Enable the PWM channel. - [0:0] - read-write - - - - - CH1_DIV - 0x00000018 - INT and FRAC form a fixed-point fractional number. - Counting rate is system clock frequency divided by this number. - Fractional division uses simple 1st-order sigma-delta. - 0x00000010 - - - INT - [11:4] - read-write - - - FRAC - [3:0] - read-write - - - - - CH1_CTR - 0x0000001c - Direct access to the PWM counter - 0x00000000 - - - CH1_CTR - [15:0] - read-write - - - - - CH1_CC - 0x00000020 - Counter compare values - 0x00000000 - - - B - [31:16] - read-write - - - A - [15:0] - read-write - - - - - CH1_TOP - 0x00000024 - Counter wrap value - 0x0000ffff - - - CH1_TOP - [15:0] - read-write - - - - - CH2_CSR - 0x00000028 - Control and status register - 0x00000000 - - - PH_ADV - Advance the phase of the counter by 1 count, while it is running. - Self-clearing. Write a 1, and poll until low. Counter must be running - at less than full speed (div_int + div_frac / 16 > 1) - [7:7] - write-only - - - PH_RET - Retard the phase of the counter by 1 count, while it is running. - Self-clearing. Write a 1, and poll until low. Counter must be running. - [6:6] - write-only - - - DIVMODE - [5:4] - read-write - - - div - 0 - Free-running counting at rate dictated by fractional divider - - - level - 1 - Fractional divider operation is gated by the PWM B pin. - - - rise - 2 - Counter advances with each rising edge of the PWM B pin. - - - fall - 3 - Counter advances with each falling edge of the PWM B pin. - - - - - B_INV - Invert output B - [3:3] - read-write - - - A_INV - Invert output A - [2:2] - read-write - - - PH_CORRECT - 1: Enable phase-correct modulation. 0: Trailing-edge - [1:1] - read-write - - - EN - Enable the PWM channel. - [0:0] - read-write - - - - - CH2_DIV - 0x0000002c - INT and FRAC form a fixed-point fractional number. - Counting rate is system clock frequency divided by this number. - Fractional division uses simple 1st-order sigma-delta. - 0x00000010 - - - INT - [11:4] - read-write - - - FRAC - [3:0] - read-write - - - - - CH2_CTR - 0x00000030 - Direct access to the PWM counter - 0x00000000 - - - CH2_CTR - [15:0] - read-write - - - - - CH2_CC - 0x00000034 - Counter compare values - 0x00000000 - - - B - [31:16] - read-write - - - A - [15:0] - read-write - - - - - CH2_TOP - 0x00000038 - Counter wrap value - 0x0000ffff - - - CH2_TOP - [15:0] - read-write - - - - - CH3_CSR - 0x0000003c - Control and status register - 0x00000000 - - - PH_ADV - Advance the phase of the counter by 1 count, while it is running. - Self-clearing. Write a 1, and poll until low. Counter must be running - at less than full speed (div_int + div_frac / 16 > 1) - [7:7] - write-only - - - PH_RET - Retard the phase of the counter by 1 count, while it is running. - Self-clearing. Write a 1, and poll until low. Counter must be running. - [6:6] - write-only - - - DIVMODE - [5:4] - read-write - - - div - 0 - Free-running counting at rate dictated by fractional divider - - - level - 1 - Fractional divider operation is gated by the PWM B pin. - - - rise - 2 - Counter advances with each rising edge of the PWM B pin. - - - fall - 3 - Counter advances with each falling edge of the PWM B pin. - - - - - B_INV - Invert output B - [3:3] - read-write - - - A_INV - Invert output A - [2:2] - read-write - - - PH_CORRECT - 1: Enable phase-correct modulation. 0: Trailing-edge - [1:1] - read-write - - - EN - Enable the PWM channel. - [0:0] - read-write - - - - - CH3_DIV - 0x00000040 - INT and FRAC form a fixed-point fractional number. - Counting rate is system clock frequency divided by this number. - Fractional division uses simple 1st-order sigma-delta. - 0x00000010 - - - INT - [11:4] - read-write - - - FRAC - [3:0] - read-write - - - - - CH3_CTR - 0x00000044 - Direct access to the PWM counter - 0x00000000 - - - CH3_CTR - [15:0] - read-write - - - - - CH3_CC - 0x00000048 - Counter compare values - 0x00000000 - - - B - [31:16] - read-write - - - A - [15:0] - read-write - - - - - CH3_TOP - 0x0000004c - Counter wrap value - 0x0000ffff - - - CH3_TOP - [15:0] - read-write - - - - - CH4_CSR - 0x00000050 - Control and status register - 0x00000000 - - - PH_ADV - Advance the phase of the counter by 1 count, while it is running. - Self-clearing. Write a 1, and poll until low. Counter must be running - at less than full speed (div_int + div_frac / 16 > 1) - [7:7] - write-only - - - PH_RET - Retard the phase of the counter by 1 count, while it is running. - Self-clearing. Write a 1, and poll until low. Counter must be running. - [6:6] - write-only - - - DIVMODE - [5:4] - read-write - - - div - 0 - Free-running counting at rate dictated by fractional divider - - - level - 1 - Fractional divider operation is gated by the PWM B pin. - - - rise - 2 - Counter advances with each rising edge of the PWM B pin. - - - fall - 3 - Counter advances with each falling edge of the PWM B pin. - - - - - B_INV - Invert output B - [3:3] - read-write - - - A_INV - Invert output A - [2:2] - read-write - - - PH_CORRECT - 1: Enable phase-correct modulation. 0: Trailing-edge - [1:1] - read-write - - - EN - Enable the PWM channel. - [0:0] - read-write - - - - - CH4_DIV - 0x00000054 - INT and FRAC form a fixed-point fractional number. - Counting rate is system clock frequency divided by this number. - Fractional division uses simple 1st-order sigma-delta. - 0x00000010 - - - INT - [11:4] - read-write - - - FRAC - [3:0] - read-write - - - - - CH4_CTR - 0x00000058 - Direct access to the PWM counter - 0x00000000 - - - CH4_CTR - [15:0] - read-write - - - - - CH4_CC - 0x0000005c - Counter compare values - 0x00000000 - - - B - [31:16] - read-write - - - A - [15:0] - read-write - - - - - CH4_TOP - 0x00000060 - Counter wrap value - 0x0000ffff - - - CH4_TOP - [15:0] - read-write - - - - - CH5_CSR - 0x00000064 - Control and status register - 0x00000000 - - - PH_ADV - Advance the phase of the counter by 1 count, while it is running. - Self-clearing. Write a 1, and poll until low. Counter must be running - at less than full speed (div_int + div_frac / 16 > 1) - [7:7] - write-only - - - PH_RET - Retard the phase of the counter by 1 count, while it is running. - Self-clearing. Write a 1, and poll until low. Counter must be running. - [6:6] - write-only - - - DIVMODE - [5:4] - read-write - - - div - 0 - Free-running counting at rate dictated by fractional divider - - - level - 1 - Fractional divider operation is gated by the PWM B pin. - - - rise - 2 - Counter advances with each rising edge of the PWM B pin. - - - fall - 3 - Counter advances with each falling edge of the PWM B pin. - - - - - B_INV - Invert output B - [3:3] - read-write - - - A_INV - Invert output A - [2:2] - read-write - - - PH_CORRECT - 1: Enable phase-correct modulation. 0: Trailing-edge - [1:1] - read-write - - - EN - Enable the PWM channel. - [0:0] - read-write - - - - - CH5_DIV - 0x00000068 - INT and FRAC form a fixed-point fractional number. - Counting rate is system clock frequency divided by this number. - Fractional division uses simple 1st-order sigma-delta. - 0x00000010 - - - INT - [11:4] - read-write - - - FRAC - [3:0] - read-write - - - - - CH5_CTR - 0x0000006c - Direct access to the PWM counter - 0x00000000 - - - CH5_CTR - [15:0] - read-write - - - - - CH5_CC - 0x00000070 - Counter compare values - 0x00000000 - - - B - [31:16] - read-write - - - A - [15:0] - read-write - - - - - CH5_TOP - 0x00000074 - Counter wrap value - 0x0000ffff - - - CH5_TOP - [15:0] - read-write - - - - - CH6_CSR - 0x00000078 - Control and status register - 0x00000000 - - - PH_ADV - Advance the phase of the counter by 1 count, while it is running. - Self-clearing. Write a 1, and poll until low. Counter must be running - at less than full speed (div_int + div_frac / 16 > 1) - [7:7] - write-only - - - PH_RET - Retard the phase of the counter by 1 count, while it is running. - Self-clearing. Write a 1, and poll until low. Counter must be running. - [6:6] - write-only - - - DIVMODE - [5:4] - read-write - - - div - 0 - Free-running counting at rate dictated by fractional divider - - - level - 1 - Fractional divider operation is gated by the PWM B pin. - - - rise - 2 - Counter advances with each rising edge of the PWM B pin. - - - fall - 3 - Counter advances with each falling edge of the PWM B pin. - - - - - B_INV - Invert output B - [3:3] - read-write - - - A_INV - Invert output A - [2:2] - read-write - - - PH_CORRECT - 1: Enable phase-correct modulation. 0: Trailing-edge - [1:1] - read-write - - - EN - Enable the PWM channel. - [0:0] - read-write - - - - - CH6_DIV - 0x0000007c - INT and FRAC form a fixed-point fractional number. - Counting rate is system clock frequency divided by this number. - Fractional division uses simple 1st-order sigma-delta. - 0x00000010 - - - INT - [11:4] - read-write - - - FRAC - [3:0] - read-write - - - - - CH6_CTR - 0x00000080 - Direct access to the PWM counter - 0x00000000 - - - CH6_CTR - [15:0] - read-write - - - - - CH6_CC - 0x00000084 - Counter compare values - 0x00000000 - - - B - [31:16] - read-write - - - A - [15:0] - read-write - - - - - CH6_TOP - 0x00000088 - Counter wrap value - 0x0000ffff - - - CH6_TOP - [15:0] - read-write - - - - - CH7_CSR - 0x0000008c - Control and status register - 0x00000000 - - - PH_ADV - Advance the phase of the counter by 1 count, while it is running. - Self-clearing. Write a 1, and poll until low. Counter must be running - at less than full speed (div_int + div_frac / 16 > 1) - [7:7] - write-only - - - PH_RET - Retard the phase of the counter by 1 count, while it is running. - Self-clearing. Write a 1, and poll until low. Counter must be running. - [6:6] - write-only - - - DIVMODE - [5:4] - read-write - - - div - 0 - Free-running counting at rate dictated by fractional divider - - - level - 1 - Fractional divider operation is gated by the PWM B pin. - - - rise - 2 - Counter advances with each rising edge of the PWM B pin. - - - fall - 3 - Counter advances with each falling edge of the PWM B pin. - - - - - B_INV - Invert output B - [3:3] - read-write - - - A_INV - Invert output A - [2:2] - read-write - - - PH_CORRECT - 1: Enable phase-correct modulation. 0: Trailing-edge - [1:1] - read-write - - - EN - Enable the PWM channel. - [0:0] - read-write - - - - - CH7_DIV - 0x00000090 - INT and FRAC form a fixed-point fractional number. - Counting rate is system clock frequency divided by this number. - Fractional division uses simple 1st-order sigma-delta. - 0x00000010 - - - INT - [11:4] - read-write - - - FRAC - [3:0] - read-write - - - - - CH7_CTR - 0x00000094 - Direct access to the PWM counter - 0x00000000 - - - CH7_CTR - [15:0] - read-write - - - - - CH7_CC - 0x00000098 - Counter compare values - 0x00000000 - - - B - [31:16] - read-write - - - A - [15:0] - read-write - - - - - CH7_TOP - 0x0000009c - Counter wrap value - 0x0000ffff - - - CH7_TOP - [15:0] - read-write - - - - - CH8_CSR - 0x000000a0 - Control and status register - 0x00000000 - - - PH_ADV - Advance the phase of the counter by 1 count, while it is running. - Self-clearing. Write a 1, and poll until low. Counter must be running - at less than full speed (div_int + div_frac / 16 > 1) - [7:7] - write-only - - - PH_RET - Retard the phase of the counter by 1 count, while it is running. - Self-clearing. Write a 1, and poll until low. Counter must be running. - [6:6] - write-only - - - DIVMODE - [5:4] - read-write - - - div - 0 - Free-running counting at rate dictated by fractional divider - - - level - 1 - Fractional divider operation is gated by the PWM B pin. - - - rise - 2 - Counter advances with each rising edge of the PWM B pin. - - - fall - 3 - Counter advances with each falling edge of the PWM B pin. - - - - - B_INV - Invert output B - [3:3] - read-write - - - A_INV - Invert output A - [2:2] - read-write - - - PH_CORRECT - 1: Enable phase-correct modulation. 0: Trailing-edge - [1:1] - read-write - - - EN - Enable the PWM channel. - [0:0] - read-write - - - - - CH8_DIV - 0x000000a4 - INT and FRAC form a fixed-point fractional number. - Counting rate is system clock frequency divided by this number. - Fractional division uses simple 1st-order sigma-delta. - 0x00000010 - - - INT - [11:4] - read-write - - - FRAC - [3:0] - read-write - - - - - CH8_CTR - 0x000000a8 - Direct access to the PWM counter - 0x00000000 - - - CH8_CTR - [15:0] - read-write - - - - - CH8_CC - 0x000000ac - Counter compare values - 0x00000000 - - - B - [31:16] - read-write - - - A - [15:0] - read-write - - - - - CH8_TOP - 0x000000b0 - Counter wrap value - 0x0000ffff - - - CH8_TOP - [15:0] - read-write - - - - - CH9_CSR - 0x000000b4 - Control and status register - 0x00000000 - - - PH_ADV - Advance the phase of the counter by 1 count, while it is running. - Self-clearing. Write a 1, and poll until low. Counter must be running - at less than full speed (div_int + div_frac / 16 > 1) - [7:7] - write-only - - - PH_RET - Retard the phase of the counter by 1 count, while it is running. - Self-clearing. Write a 1, and poll until low. Counter must be running. - [6:6] - write-only - - - DIVMODE - [5:4] - read-write - - - div - 0 - Free-running counting at rate dictated by fractional divider - - - level - 1 - Fractional divider operation is gated by the PWM B pin. - - - rise - 2 - Counter advances with each rising edge of the PWM B pin. - - - fall - 3 - Counter advances with each falling edge of the PWM B pin. - - - - - B_INV - Invert output B - [3:3] - read-write - - - A_INV - Invert output A - [2:2] - read-write - - - PH_CORRECT - 1: Enable phase-correct modulation. 0: Trailing-edge - [1:1] - read-write - - - EN - Enable the PWM channel. - [0:0] - read-write - - - - - CH9_DIV - 0x000000b8 - INT and FRAC form a fixed-point fractional number. - Counting rate is system clock frequency divided by this number. - Fractional division uses simple 1st-order sigma-delta. - 0x00000010 - - - INT - [11:4] - read-write - - - FRAC - [3:0] - read-write - - - - - CH9_CTR - 0x000000bc - Direct access to the PWM counter - 0x00000000 - - - CH9_CTR - [15:0] - read-write - - - - - CH9_CC - 0x000000c0 - Counter compare values - 0x00000000 - - - B - [31:16] - read-write - - - A - [15:0] - read-write - - - - - CH9_TOP - 0x000000c4 - Counter wrap value - 0x0000ffff - - - CH9_TOP - [15:0] - read-write - - - - - CH10_CSR - 0x000000c8 - Control and status register - 0x00000000 - - - PH_ADV - Advance the phase of the counter by 1 count, while it is running. - Self-clearing. Write a 1, and poll until low. Counter must be running - at less than full speed (div_int + div_frac / 16 > 1) - [7:7] - write-only - - - PH_RET - Retard the phase of the counter by 1 count, while it is running. - Self-clearing. Write a 1, and poll until low. Counter must be running. - [6:6] - write-only - - - DIVMODE - [5:4] - read-write - - - div - 0 - Free-running counting at rate dictated by fractional divider - - - level - 1 - Fractional divider operation is gated by the PWM B pin. - - - rise - 2 - Counter advances with each rising edge of the PWM B pin. - - - fall - 3 - Counter advances with each falling edge of the PWM B pin. - - - - - B_INV - Invert output B - [3:3] - read-write - - - A_INV - Invert output A - [2:2] - read-write - - - PH_CORRECT - 1: Enable phase-correct modulation. 0: Trailing-edge - [1:1] - read-write - - - EN - Enable the PWM channel. - [0:0] - read-write - - - - - CH10_DIV - 0x000000cc - INT and FRAC form a fixed-point fractional number. - Counting rate is system clock frequency divided by this number. - Fractional division uses simple 1st-order sigma-delta. - 0x00000010 - - - INT - [11:4] - read-write - - - FRAC - [3:0] - read-write - - - - - CH10_CTR - 0x000000d0 - Direct access to the PWM counter - 0x00000000 - - - CH10_CTR - [15:0] - read-write - - - - - CH10_CC - 0x000000d4 - Counter compare values - 0x00000000 - - - B - [31:16] - read-write - - - A - [15:0] - read-write - - - - - CH10_TOP - 0x000000d8 - Counter wrap value - 0x0000ffff - - - CH10_TOP - [15:0] - read-write - - - - - CH11_CSR - 0x000000dc - Control and status register - 0x00000000 - - - PH_ADV - Advance the phase of the counter by 1 count, while it is running. - Self-clearing. Write a 1, and poll until low. Counter must be running - at less than full speed (div_int + div_frac / 16 > 1) - [7:7] - write-only - - - PH_RET - Retard the phase of the counter by 1 count, while it is running. - Self-clearing. Write a 1, and poll until low. Counter must be running. - [6:6] - write-only - - - DIVMODE - [5:4] - read-write - - - div - 0 - Free-running counting at rate dictated by fractional divider - - - level - 1 - Fractional divider operation is gated by the PWM B pin. - - - rise - 2 - Counter advances with each rising edge of the PWM B pin. - - - fall - 3 - Counter advances with each falling edge of the PWM B pin. - - - - - B_INV - Invert output B - [3:3] - read-write - - - A_INV - Invert output A - [2:2] - read-write - - - PH_CORRECT - 1: Enable phase-correct modulation. 0: Trailing-edge - [1:1] - read-write - - - EN - Enable the PWM channel. - [0:0] - read-write - - - - - CH11_DIV - 0x000000e0 - INT and FRAC form a fixed-point fractional number. - Counting rate is system clock frequency divided by this number. - Fractional division uses simple 1st-order sigma-delta. - 0x00000010 - - - INT - [11:4] - read-write - - - FRAC - [3:0] - read-write - - - - - CH11_CTR - 0x000000e4 - Direct access to the PWM counter - 0x00000000 - - - CH11_CTR - [15:0] - read-write - - - - - CH11_CC - 0x000000e8 - Counter compare values - 0x00000000 - - - B - [31:16] - read-write - - - A - [15:0] - read-write - - - - - CH11_TOP - 0x000000ec - Counter wrap value - 0x0000ffff - - - CH11_TOP - [15:0] - read-write - - - - - EN - 0x000000f0 - This register aliases the CSR_EN bits for all channels. - Writing to this register allows multiple channels to be enabled - or disabled simultaneously, so they can run in perfect sync. - For each channel, there is only one physical EN register bit, - which can be accessed through here or CHx_CSR. - 0x00000000 - - - CH11 - [11:11] - read-write - - - CH10 - [10:10] - read-write - - - CH9 - [9:9] - read-write - - - CH8 - [8:8] - read-write - - - CH7 - [7:7] - read-write - - - CH6 - [6:6] - read-write - - - CH5 - [5:5] - read-write - - - CH4 - [4:4] - read-write - - - CH3 - [3:3] - read-write - - - CH2 - [2:2] - read-write - - - CH1 - [1:1] - read-write - - - CH0 - [0:0] - read-write - - - - - INTR - 0x000000f4 - Raw Interrupts - 0x00000000 - - - CH11 - [11:11] - read-write - oneToClear - - - CH10 - [10:10] - read-write - oneToClear - - - CH9 - [9:9] - read-write - oneToClear - - - CH8 - [8:8] - read-write - oneToClear - - - CH7 - [7:7] - read-write - oneToClear - - - CH6 - [6:6] - read-write - oneToClear - - - CH5 - [5:5] - read-write - oneToClear - - - CH4 - [4:4] - read-write - oneToClear - - - CH3 - [3:3] - read-write - oneToClear - - - CH2 - [2:2] - read-write - oneToClear - - - CH1 - [1:1] - read-write - oneToClear - - - CH0 - [0:0] - read-write - oneToClear - - - - - IRQ0_INTE - 0x000000f8 - Interrupt Enable for irq0 - 0x00000000 - - - CH11 - [11:11] - read-write - - - CH10 - [10:10] - read-write - - - CH9 - [9:9] - read-write - - - CH8 - [8:8] - read-write - - - CH7 - [7:7] - read-write - - - CH6 - [6:6] - read-write - - - CH5 - [5:5] - read-write - - - CH4 - [4:4] - read-write - - - CH3 - [3:3] - read-write - - - CH2 - [2:2] - read-write - - - CH1 - [1:1] - read-write - - - CH0 - [0:0] - read-write - - - - - IRQ0_INTF - 0x000000fc - Interrupt Force for irq0 - 0x00000000 - - - CH11 - [11:11] - read-write - - - CH10 - [10:10] - read-write - - - CH9 - [9:9] - read-write - - - CH8 - [8:8] - read-write - - - CH7 - [7:7] - read-write - - - CH6 - [6:6] - read-write - - - CH5 - [5:5] - read-write - - - CH4 - [4:4] - read-write - - - CH3 - [3:3] - read-write - - - CH2 - [2:2] - read-write - - - CH1 - [1:1] - read-write - - - CH0 - [0:0] - read-write - - - - - IRQ0_INTS - 0x00000100 - Interrupt status after masking & forcing for irq0 - 0x00000000 - - - CH11 - [11:11] - read-only - - - CH10 - [10:10] - read-only - - - CH9 - [9:9] - read-only - - - CH8 - [8:8] - read-only - - - CH7 - [7:7] - read-only - - - CH6 - [6:6] - read-only - - - CH5 - [5:5] - read-only - - - CH4 - [4:4] - read-only - - - CH3 - [3:3] - read-only - - - CH2 - [2:2] - read-only - - - CH1 - [1:1] - read-only - - - CH0 - [0:0] - read-only - - - - - IRQ1_INTE - 0x00000104 - Interrupt Enable for irq1 - 0x00000000 - - - CH11 - [11:11] - read-write - - - CH10 - [10:10] - read-write - - - CH9 - [9:9] - read-write - - - CH8 - [8:8] - read-write - - - CH7 - [7:7] - read-write - - - CH6 - [6:6] - read-write - - - CH5 - [5:5] - read-write - - - CH4 - [4:4] - read-write - - - CH3 - [3:3] - read-write - - - CH2 - [2:2] - read-write - - - CH1 - [1:1] - read-write - - - CH0 - [0:0] - read-write - - - - - IRQ1_INTF - 0x00000108 - Interrupt Force for irq1 - 0x00000000 - - - CH11 - [11:11] - read-write - - - CH10 - [10:10] - read-write - - - CH9 - [9:9] - read-write - - - CH8 - [8:8] - read-write - - - CH7 - [7:7] - read-write - - - CH6 - [6:6] - read-write - - - CH5 - [5:5] - read-write - - - CH4 - [4:4] - read-write - - - CH3 - [3:3] - read-write - - - CH2 - [2:2] - read-write - - - CH1 - [1:1] - read-write - - - CH0 - [0:0] - read-write - - - - - IRQ1_INTS - 0x0000010c - Interrupt status after masking & forcing for irq1 - 0x00000000 - - - CH11 - [11:11] - read-only - - - CH10 - [10:10] - read-only - - - CH9 - [9:9] - read-only - - - CH8 - [8:8] - read-only - - - CH7 - [7:7] - read-only - - - CH6 - [6:6] - read-only - - - CH5 - [5:5] - read-only - - - CH4 - [4:4] - read-only - - - CH3 - [3:3] - read-only - - - CH2 - [2:2] - read-only - - - CH1 - [1:1] - read-only - - - CH0 - [0:0] - read-only - - - - - - - ADC - Control and data interface to SAR ADC - 0x400a0000 - - 0 - 36 - registers - - - ADC_IRQ_FIFO - 35 - - - - CS - 0x00000000 - ADC Control and Status - 0x00000000 - - - RROBIN - Round-robin sampling. 1 bit per channel. Set all bits to 0 to disable. - Otherwise, the ADC will cycle through each enabled channel in a round-robin fashion. - The first channel to be sampled will be the one currently indicated by AINSEL. - AINSEL will be updated after each conversion with the newly-selected channel. - [24:16] - read-write - - - AINSEL - Select analog mux input. Updated automatically in round-robin mode. - This is corrected for the package option so only ADC channels which are bonded are available, and in the correct order - [15:12] - read-write - - - ERR_STICKY - Some past ADC conversion encountered an error. Write 1 to clear. - [10:10] - read-write - oneToClear - - - ERR - The most recent ADC conversion encountered an error; result is undefined or noisy. - [9:9] - read-only - - - READY - 1 if the ADC is ready to start a new conversion. Implies any previous conversion has completed. - 0 whilst conversion in progress. - [8:8] - read-only - - - START_MANY - Continuously perform conversions whilst this bit is 1. A new conversion will start immediately after the previous finishes. - [3:3] - read-write - - - START_ONCE - Start a single conversion. Self-clearing. Ignored if start_many is asserted. - [2:2] - write-only - - - TS_EN - Power on temperature sensor. 1 - enabled. 0 - disabled. - [1:1] - read-write - - - EN - Power on ADC and enable its clock. - 1 - enabled. 0 - disabled. - [0:0] - read-write - - - - - RESULT - 0x00000004 - Result of most recent ADC conversion - 0x00000000 - - - RESULT - [11:0] - read-only - - - - - FCS - 0x00000008 - FIFO control and status - 0x00000000 - - - THRESH - DREQ/IRQ asserted when level >= threshold - [27:24] - read-write - - - LEVEL - The number of conversion results currently waiting in the FIFO - [19:16] - read-only - - - OVER - 1 if the FIFO has been overflowed. Write 1 to clear. - [11:11] - read-write - oneToClear - - - UNDER - 1 if the FIFO has been underflowed. Write 1 to clear. - [10:10] - read-write - oneToClear - - - FULL - [9:9] - read-only - - - EMPTY - [8:8] - read-only - - - DREQ_EN - If 1: assert DMA requests when FIFO contains data - [3:3] - read-write - - - ERR - If 1: conversion error bit appears in the FIFO alongside the result - [2:2] - read-write - - - SHIFT - If 1: FIFO results are right-shifted to be one byte in size. Enables DMA to byte buffers. - [1:1] - read-write - - - EN - If 1: write result to the FIFO after each conversion. - [0:0] - read-write - - - - - FIFO - 0x0000000c - Conversion result FIFO - 0x00000000 - - - ERR - 1 if this particular sample experienced a conversion error. Remains in the same location if the sample is shifted. - [15:15] - read-only - modify - - - VAL - [11:0] - read-only - modify - - - - - DIV - 0x00000010 - Clock divider. If non-zero, CS_START_MANY will start conversions - at regular intervals rather than back-to-back. - The divider is reset when either of these fields are written. - Total period is 1 + INT + FRAC / 256 - 0x00000000 - - - INT - Integer part of clock divisor. - [23:8] - read-write - - - FRAC - Fractional part of clock divisor. First-order delta-sigma. - [7:0] - read-write - - - - - INTR - 0x00000014 - Raw Interrupts - 0x00000000 - - - FIFO - Triggered when the sample FIFO reaches a certain level. - This level can be programmed via the FCS_THRESH field. - [0:0] - read-only - - - - - INTE - 0x00000018 - Interrupt Enable - 0x00000000 - - - FIFO - Triggered when the sample FIFO reaches a certain level. - This level can be programmed via the FCS_THRESH field. - [0:0] - read-write - - - - - INTF - 0x0000001c - Interrupt Force - 0x00000000 - - - FIFO - Triggered when the sample FIFO reaches a certain level. - This level can be programmed via the FCS_THRESH field. - [0:0] - read-write - - - - - INTS - 0x00000020 - Interrupt status after masking & forcing - 0x00000000 - - - FIFO - Triggered when the sample FIFO reaches a certain level. - This level can be programmed via the FCS_THRESH field. - [0:0] - read-only - - - - - - - I2C0 - DW_apb_i2c address block - - List of configuration constants for the Synopsys I2C hardware (you may see references to these in I2C register header; these are *fixed* values, set at hardware design time): - - IC_ULTRA_FAST_MODE ................ 0x0 - IC_UFM_TBUF_CNT_DEFAULT ........... 0x8 - IC_UFM_SCL_LOW_COUNT .............. 0x0008 - IC_UFM_SCL_HIGH_COUNT ............. 0x0006 - IC_TX_TL .......................... 0x0 - IC_TX_CMD_BLOCK ................... 0x1 - IC_HAS_DMA ........................ 0x1 - IC_HAS_ASYNC_FIFO ................. 0x0 - IC_SMBUS_ARP ...................... 0x0 - IC_FIRST_DATA_BYTE_STATUS ......... 0x1 - IC_INTR_IO ........................ 0x1 - IC_MASTER_MODE .................... 0x1 - IC_DEFAULT_ACK_GENERAL_CALL ....... 0x1 - IC_INTR_POL ....................... 0x1 - IC_OPTIONAL_SAR ................... 0x0 - IC_DEFAULT_TAR_SLAVE_ADDR ......... 0x055 - IC_DEFAULT_SLAVE_ADDR ............. 0x055 - IC_DEFAULT_HS_SPKLEN .............. 0x1 - IC_FS_SCL_HIGH_COUNT .............. 0x0006 - IC_HS_SCL_LOW_COUNT ............... 0x0008 - IC_DEVICE_ID_VALUE ................ 0x0 - IC_10BITADDR_MASTER ............... 0x0 - IC_CLK_FREQ_OPTIMIZATION .......... 0x0 - IC_DEFAULT_FS_SPKLEN .............. 0x7 - IC_ADD_ENCODED_PARAMS ............. 0x0 - IC_DEFAULT_SDA_HOLD ............... 0x000001 - IC_DEFAULT_SDA_SETUP .............. 0x64 - IC_AVOID_RX_FIFO_FLUSH_ON_TX_ABRT . 0x0 - IC_CLOCK_PERIOD ................... 100 - IC_EMPTYFIFO_HOLD_MASTER_EN ....... 1 - IC_RESTART_EN ..................... 0x1 - IC_TX_CMD_BLOCK_DEFAULT ........... 0x0 - IC_BUS_CLEAR_FEATURE .............. 0x0 - IC_CAP_LOADING .................... 100 - IC_FS_SCL_LOW_COUNT ............... 0x000d - APB_DATA_WIDTH .................... 32 - IC_SDA_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff - IC_SLV_DATA_NACK_ONLY ............. 0x1 - IC_10BITADDR_SLAVE ................ 0x0 - IC_CLK_TYPE ....................... 0x0 - IC_SMBUS_UDID_MSB ................. 0x0 - IC_SMBUS_SUSPEND_ALERT ............ 0x0 - IC_HS_SCL_HIGH_COUNT .............. 0x0006 - IC_SLV_RESTART_DET_EN ............. 0x1 - IC_SMBUS .......................... 0x0 - IC_OPTIONAL_SAR_DEFAULT ........... 0x0 - IC_PERSISTANT_SLV_ADDR_DEFAULT .... 0x0 - IC_USE_COUNTS ..................... 0x0 - IC_RX_BUFFER_DEPTH ................ 16 - IC_SCL_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff - IC_RX_FULL_HLD_BUS_EN ............. 0x1 - IC_SLAVE_DISABLE .................. 0x1 - IC_RX_TL .......................... 0x0 - IC_DEVICE_ID ...................... 0x0 - IC_HC_COUNT_VALUES ................ 0x0 - I2C_DYNAMIC_TAR_UPDATE ............ 0 - IC_SMBUS_CLK_LOW_MEXT_DEFAULT ..... 0xffffffff - IC_SMBUS_CLK_LOW_SEXT_DEFAULT ..... 0xffffffff - IC_HS_MASTER_CODE ................. 0x1 - IC_SMBUS_RST_IDLE_CNT_DEFAULT ..... 0xffff - IC_SMBUS_UDID_LSB_DEFAULT ......... 0xffffffff - IC_SS_SCL_HIGH_COUNT .............. 0x0028 - IC_SS_SCL_LOW_COUNT ............... 0x002f - IC_MAX_SPEED_MODE ................. 0x2 - IC_STAT_FOR_CLK_STRETCH ........... 0x0 - IC_STOP_DET_IF_MASTER_ACTIVE ...... 0x0 - IC_DEFAULT_UFM_SPKLEN ............. 0x1 - IC_TX_BUFFER_DEPTH ................ 16 - 0x40090000 - - 0 - 256 - registers - - - I2C0_IRQ - 36 - - - - IC_CON - 0x00000000 - I2C Control Register. This register can be written only when the DW_apb_i2c is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect. - - Read/Write Access: - bit 10 is read only. - bit 11 is read only - bit 16 is read only - bit 17 is read only - bits 18 and 19 are read only. - 0x00000065 - - - STOP_DET_IF_MASTER_ACTIVE - Master issues the STOP_DET interrupt irrespective of whether master is active or not - [10:10] - read-only - - - RX_FIFO_FULL_HLD_CTRL - This bit controls whether DW_apb_i2c should hold the bus when the Rx FIFO is physically full to its RX_BUFFER_DEPTH, as described in the IC_RX_FULL_HLD_BUS_EN parameter. - - Reset value: 0x0. - [9:9] - read-write - - - DISABLED - 0 - Overflow when RX_FIFO is full - - - ENABLED - 1 - Hold bus when RX_FIFO is full - - - - - TX_EMPTY_CTRL - This bit controls the generation of the TX_EMPTY interrupt, as described in the IC_RAW_INTR_STAT register. - - Reset value: 0x0. - [8:8] - read-write - - - DISABLED - 0 - Default behaviour of TX_EMPTY interrupt - - - ENABLED - 1 - Controlled generation of TX_EMPTY interrupt - - - - - STOP_DET_IFADDRESSED - In slave mode: - 1'b1: issues the STOP_DET interrupt only when it is addressed. - 1'b0: issues the STOP_DET irrespective of whether it's addressed or not. Reset value: 0x0 - - NOTE: During a general call address, this slave does not issue the STOP_DET interrupt if STOP_DET_IF_ADDRESSED = 1'b1, even if the slave responds to the general call address by generating ACK. The STOP_DET interrupt is generated only when the transmitted address matches the slave address (SAR). - [7:7] - read-write - - - DISABLED - 0 - slave issues STOP_DET intr always - - - ENABLED - 1 - slave issues STOP_DET intr only if addressed - - - - - IC_SLAVE_DISABLE - This bit controls whether I2C has its slave disabled, which means once the presetn signal is applied, then this bit is set and the slave is disabled. - - If this bit is set (slave is disabled), DW_apb_i2c functions only as a master and does not perform any action that requires a slave. - - NOTE: Software should ensure that if this bit is written with 0, then bit 0 should also be written with a 0. - [6:6] - read-write - - - SLAVE_ENABLED - 0 - Slave mode is enabled - - - SLAVE_DISABLED - 1 - Slave mode is disabled - - - - - IC_RESTART_EN - Determines whether RESTART conditions may be sent when acting as a master. Some older slaves do not support handling RESTART conditions; however, RESTART conditions are used in several DW_apb_i2c operations. When RESTART is disabled, the master is prohibited from performing the following functions: - Sending a START BYTE - Performing any high-speed mode operation - High-speed mode operation - Performing direction changes in combined format mode - Performing a read operation with a 10-bit address By replacing RESTART condition followed by a STOP and a subsequent START condition, split operations are broken down into multiple DW_apb_i2c transfers. If the above operations are performed, it will result in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register. - - Reset value: ENABLED - [5:5] - read-write - - - DISABLED - 0 - Master restart disabled - - - ENABLED - 1 - Master restart enabled - - - - - IC_10BITADDR_MASTER - Controls whether the DW_apb_i2c starts its transfers in 7- or 10-bit addressing mode when acting as a master. - 0: 7-bit addressing - 1: 10-bit addressing - [4:4] - read-write - - - ADDR_7BITS - 0 - Master 7Bit addressing mode - - - ADDR_10BITS - 1 - Master 10Bit addressing mode - - - - - IC_10BITADDR_SLAVE - When acting as a slave, this bit controls whether the DW_apb_i2c responds to 7- or 10-bit addresses. - 0: 7-bit addressing. The DW_apb_i2c ignores transactions that involve 10-bit addressing; for 7-bit addressing, only the lower 7 bits of the IC_SAR register are compared. - 1: 10-bit addressing. The DW_apb_i2c responds to only 10-bit addressing transfers that match the full 10 bits of the IC_SAR register. - [3:3] - read-write - - - ADDR_7BITS - 0 - Slave 7Bit addressing - - - ADDR_10BITS - 1 - Slave 10Bit addressing - - - - - SPEED - These bits control at which speed the DW_apb_i2c operates; its setting is relevant only if one is operating the DW_apb_i2c in master mode. Hardware protects against illegal values being programmed by software. These bits must be programmed appropriately for slave mode also, as it is used to capture correct value of spike filter as per the speed mode. - - This register should be programmed only with a value in the range of 1 to IC_MAX_SPEED_MODE; otherwise, hardware updates this register with the value of IC_MAX_SPEED_MODE. - - 1: standard mode (100 kbit/s) - - 2: fast mode (<=400 kbit/s) or fast mode plus (<=1000Kbit/s) - - 3: high speed mode (3.4 Mbit/s) - - Note: This field is not applicable when IC_ULTRA_FAST_MODE=1 - [2:1] - read-write - - - STANDARD - 1 - Standard Speed mode of operation - - - FAST - 2 - Fast or Fast Plus mode of operation - - - HIGH - 3 - High Speed mode of operation - - - - - MASTER_MODE - This bit controls whether the DW_apb_i2c master is enabled. - - NOTE: Software should ensure that if this bit is written with '1' then bit 6 should also be written with a '1'. - [0:0] - read-write - - - DISABLED - 0 - Master mode is disabled - - - ENABLED - 1 - Master mode is enabled - - - - - - - IC_TAR - 0x00000004 - I2C Target Address Register - - This register is 12 bits wide, and bits 31:12 are reserved. This register can be written to only when IC_ENABLE[0] is set to 0. - - Note: If the software or application is aware that the DW_apb_i2c is not using the TAR address for the pending commands in the Tx FIFO, then it is possible to update the TAR address even while the Tx FIFO has entries (IC_STATUS[2]= 0). - It is not necessary to perform any write to this register if DW_apb_i2c is enabled as an I2C slave only. - 0x00000055 - - - SPECIAL - This bit indicates whether software performs a Device-ID or General Call or START BYTE command. - 0: ignore bit 10 GC_OR_START and use IC_TAR normally - 1: perform special I2C command as specified in Device_ID or GC_OR_START bit Reset value: 0x0 - [11:11] - read-write - - - DISABLED - 0 - Disables programming of GENERAL_CALL or START_BYTE transmission - - - ENABLED - 1 - Enables programming of GENERAL_CALL or START_BYTE transmission - - - - - GC_OR_START - If bit 11 (SPECIAL) is set to 1 and bit 13(Device-ID) is set to 0, then this bit indicates whether a General Call or START byte command is to be performed by the DW_apb_i2c. - 0: General Call Address - after issuing a General Call, only writes may be performed. Attempting to issue a read command results in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register. The DW_apb_i2c remains in General Call mode until the SPECIAL bit value (bit 11) is cleared. - 1: START BYTE Reset value: 0x0 - [10:10] - read-write - - - GENERAL_CALL - 0 - GENERAL_CALL byte transmission - - - START_BYTE - 1 - START byte transmission - - - - - IC_TAR - This is the target address for any master transaction. When transmitting a General Call, these bits are ignored. To generate a START BYTE, the CPU needs to write only once into these bits. - - If the IC_TAR and IC_SAR are the same, loopback exists but the FIFOs are shared between master and slave, so full loopback is not feasible. Only one direction loopback mode is supported (simplex), not duplex. A master cannot transmit to itself; it can transmit to only a slave. - [9:0] - read-write - - - - - IC_SAR - 0x00000008 - I2C Slave Address Register - 0x00000055 - - - IC_SAR - The IC_SAR holds the slave address when the I2C is operating as a slave. For 7-bit addressing, only IC_SAR[6:0] is used. - - This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect. - - Note: The default values cannot be any of the reserved address locations: that is, 0x00 to 0x07, or 0x78 to 0x7f. The correct operation of the device is not guaranteed if you program the IC_SAR or IC_TAR to a reserved value. Refer to <<table_I2C_firstbyte_bit_defs>> for a complete list of these reserved values. - [9:0] - read-write - - - - - IC_DATA_CMD - 0x00000010 - I2C Rx/Tx Data Buffer and Command Register; this is the register the CPU writes to when filling the TX FIFO and the CPU reads from when retrieving bytes from RX FIFO. - - The size of the register changes as follows: - - Write: - 11 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=1 - 9 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=0 Read: - 12 bits when IC_FIRST_DATA_BYTE_STATUS = 1 - 8 bits when IC_FIRST_DATA_BYTE_STATUS = 0 Note: In order for the DW_apb_i2c to continue acknowledging reads, a read command should be written for every byte that is to be received; otherwise the DW_apb_i2c will stop acknowledging. - 0x00000000 - - - FIRST_DATA_BYTE - Indicates the first data byte received after the address phase for receive transfer in Master receiver or Slave receiver mode. - - Reset value : 0x0 - - NOTE: In case of APB_DATA_WIDTH=8, - - 1. The user has to perform two APB Reads to IC_DATA_CMD in order to get status on 11 bit. - - 2. In order to read the 11 bit, the user has to perform the first data byte read [7:0] (offset 0x10) and then perform the second read [15:8] (offset 0x11) in order to know the status of 11 bit (whether the data received in previous read is a first data byte or not). - - 3. The 11th bit is an optional read field, user can ignore 2nd byte read [15:8] (offset 0x11) if not interested in FIRST_DATA_BYTE status. - [11:11] - read-only - - - INACTIVE - 0 - Sequential data byte received - - - ACTIVE - 1 - Non sequential data byte received - - - - - RESTART - This bit controls whether a RESTART is issued before the byte is sent or received. - - 1 - If IC_RESTART_EN is 1, a RESTART is issued before the data is sent/received (according to the value of CMD), regardless of whether or not the transfer direction is changing from the previous command; if IC_RESTART_EN is 0, a STOP followed by a START is issued instead. - - 0 - If IC_RESTART_EN is 1, a RESTART is issued only if the transfer direction is changing from the previous command; if IC_RESTART_EN is 0, a STOP followed by a START is issued instead. - - Reset value: 0x0 - [10:10] - write-only - - - DISABLE - 0 - Don't Issue RESTART before this command - - - ENABLE - 1 - Issue RESTART before this command - - - - - STOP - This bit controls whether a STOP is issued after the byte is sent or received. - - - 1 - STOP is issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master immediately tries to start a new transfer by issuing a START and arbitrating for the bus. - 0 - STOP is not issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master continues the current transfer by sending/receiving data bytes according to the value of the CMD bit. If the Tx FIFO is empty, the master holds the SCL line low and stalls the bus until a new command is available in the Tx FIFO. Reset value: 0x0 - [9:9] - write-only - - - DISABLE - 0 - Don't Issue STOP after this command - - - ENABLE - 1 - Issue STOP after this command - - - - - CMD - This bit controls whether a read or a write is performed. This bit does not control the direction when the DW_apb_i2con acts as a slave. It controls only the direction when it acts as a master. - - When a command is entered in the TX FIFO, this bit distinguishes the write and read commands. In slave-receiver mode, this bit is a 'don't care' because writes to this register are not required. In slave-transmitter mode, a '0' indicates that the data in IC_DATA_CMD is to be transmitted. - - When programming this bit, you should remember the following: attempting to perform a read operation after a General Call command has been sent results in a TX_ABRT interrupt (bit 6 of the IC_RAW_INTR_STAT register), unless bit 11 (SPECIAL) in the IC_TAR register has been cleared. If a '1' is written to this bit after receiving a RD_REQ interrupt, then a TX_ABRT interrupt occurs. - - Reset value: 0x0 - [8:8] - write-only - - - WRITE - 0 - Master Write Command - - - READ - 1 - Master Read Command - - - - - DAT - This register contains the data to be transmitted or received on the I2C bus. If you are writing to this register and want to perform a read, bits 7:0 (DAT) are ignored by the DW_apb_i2c. However, when you read this register, these bits return the value of data received on the DW_apb_i2c interface. - - Reset value: 0x0 - [7:0] - read-write - - - - - IC_SS_SCL_HCNT - 0x00000014 - Standard Speed I2C Clock SCL High Count Register - 0x00000028 - - - IC_SS_SCL_HCNT - This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for standard speed. For more information, refer to 'IC_CLK Frequency Configuration'. - - This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect. - - The minimum valid value is 6; hardware prevents values less than this being written, and if attempted results in 6 being set. For designs with APB_DATA_WIDTH = 8, the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed. - - NOTE: This register must not be programmed to a value higher than 65525, because DW_apb_i2c uses a 16-bit counter to flag an I2C bus idle condition when this counter reaches a value of IC_SS_SCL_HCNT + 10. - [15:0] - read-write - - - - - IC_SS_SCL_LCNT - 0x00000018 - Standard Speed I2C Clock SCL Low Count Register - 0x0000002f - - - IC_SS_SCL_LCNT - This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for standard speed. For more information, refer to 'IC_CLK Frequency Configuration' - - This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect. - - The minimum valid value is 8; hardware prevents values less than this being written, and if attempted, results in 8 being set. For designs with APB_DATA_WIDTH = 8, the order of programming is important to ensure the correct operation of DW_apb_i2c. The lower byte must be programmed first, and then the upper byte is programmed. - [15:0] - read-write - - - - - IC_FS_SCL_HCNT - 0x0000001c - Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register - 0x00000006 - - - IC_FS_SCL_HCNT - This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for fast mode or fast mode plus. It is used in high-speed mode to send the Master Code and START BYTE or General CALL. For more information, refer to 'IC_CLK Frequency Configuration'. - - This register goes away and becomes read-only returning 0s if IC_MAX_SPEED_MODE = standard. This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect. - - The minimum valid value is 6; hardware prevents values less than this being written, and if attempted results in 6 being set. For designs with APB_DATA_WIDTH == 8 the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed. - [15:0] - read-write - - - - - IC_FS_SCL_LCNT - 0x00000020 - Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register - 0x0000000d - - - IC_FS_SCL_LCNT - This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for fast speed. It is used in high-speed mode to send the Master Code and START BYTE or General CALL. For more information, refer to 'IC_CLK Frequency Configuration'. - - This register goes away and becomes read-only returning 0s if IC_MAX_SPEED_MODE = standard. - - This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect. - - The minimum valid value is 8; hardware prevents values less than this being written, and if attempted results in 8 being set. For designs with APB_DATA_WIDTH = 8 the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed. If the value is less than 8 then the count value gets changed to 8. - [15:0] - read-write - - - - - IC_INTR_STAT - 0x0000002c - I2C Interrupt Status Register - - Each bit in this register has a corresponding mask bit in the IC_INTR_MASK register. These bits are cleared by reading the matching interrupt clear register. The unmasked raw versions of these bits are available in the IC_RAW_INTR_STAT register. - 0x00000000 - - - R_RESTART_DET - See IC_RAW_INTR_STAT for a detailed description of R_RESTART_DET bit. - - Reset value: 0x0 - [12:12] - read-only - - - INACTIVE - 0 - R_RESTART_DET interrupt is inactive - - - ACTIVE - 1 - R_RESTART_DET interrupt is active - - - - - R_GEN_CALL - See IC_RAW_INTR_STAT for a detailed description of R_GEN_CALL bit. - - Reset value: 0x0 - [11:11] - read-only - - - INACTIVE - 0 - R_GEN_CALL interrupt is inactive - - - ACTIVE - 1 - R_GEN_CALL interrupt is active - - - - - R_START_DET - See IC_RAW_INTR_STAT for a detailed description of R_START_DET bit. - - Reset value: 0x0 - [10:10] - read-only - - - INACTIVE - 0 - R_START_DET interrupt is inactive - - - ACTIVE - 1 - R_START_DET interrupt is active - - - - - R_STOP_DET - See IC_RAW_INTR_STAT for a detailed description of R_STOP_DET bit. - - Reset value: 0x0 - [9:9] - read-only - - - INACTIVE - 0 - R_STOP_DET interrupt is inactive - - - ACTIVE - 1 - R_STOP_DET interrupt is active - - - - - R_ACTIVITY - See IC_RAW_INTR_STAT for a detailed description of R_ACTIVITY bit. - - Reset value: 0x0 - [8:8] - read-only - - - INACTIVE - 0 - R_ACTIVITY interrupt is inactive - - - ACTIVE - 1 - R_ACTIVITY interrupt is active - - - - - R_RX_DONE - See IC_RAW_INTR_STAT for a detailed description of R_RX_DONE bit. - - Reset value: 0x0 - [7:7] - read-only - - - INACTIVE - 0 - R_RX_DONE interrupt is inactive - - - ACTIVE - 1 - R_RX_DONE interrupt is active - - - - - R_TX_ABRT - See IC_RAW_INTR_STAT for a detailed description of R_TX_ABRT bit. - - Reset value: 0x0 - [6:6] - read-only - - - INACTIVE - 0 - R_TX_ABRT interrupt is inactive - - - ACTIVE - 1 - R_TX_ABRT interrupt is active - - - - - R_RD_REQ - See IC_RAW_INTR_STAT for a detailed description of R_RD_REQ bit. - - Reset value: 0x0 - [5:5] - read-only - - - INACTIVE - 0 - R_RD_REQ interrupt is inactive - - - ACTIVE - 1 - R_RD_REQ interrupt is active - - - - - R_TX_EMPTY - See IC_RAW_INTR_STAT for a detailed description of R_TX_EMPTY bit. - - Reset value: 0x0 - [4:4] - read-only - - - INACTIVE - 0 - R_TX_EMPTY interrupt is inactive - - - ACTIVE - 1 - R_TX_EMPTY interrupt is active - - - - - R_TX_OVER - See IC_RAW_INTR_STAT for a detailed description of R_TX_OVER bit. - - Reset value: 0x0 - [3:3] - read-only - - - INACTIVE - 0 - R_TX_OVER interrupt is inactive - - - ACTIVE - 1 - R_TX_OVER interrupt is active - - - - - R_RX_FULL - See IC_RAW_INTR_STAT for a detailed description of R_RX_FULL bit. - - Reset value: 0x0 - [2:2] - read-only - - - INACTIVE - 0 - R_RX_FULL interrupt is inactive - - - ACTIVE - 1 - R_RX_FULL interrupt is active - - - - - R_RX_OVER - See IC_RAW_INTR_STAT for a detailed description of R_RX_OVER bit. - - Reset value: 0x0 - [1:1] - read-only - - - INACTIVE - 0 - R_RX_OVER interrupt is inactive - - - ACTIVE - 1 - R_RX_OVER interrupt is active - - - - - R_RX_UNDER - See IC_RAW_INTR_STAT for a detailed description of R_RX_UNDER bit. - - Reset value: 0x0 - [0:0] - read-only - - - INACTIVE - 0 - RX_UNDER interrupt is inactive - - - ACTIVE - 1 - RX_UNDER interrupt is active - - - - - - - IC_INTR_MASK - 0x00000030 - I2C Interrupt Mask Register. - - These bits mask their corresponding interrupt status bits. This register is active low; a value of 0 masks the interrupt, whereas a value of 1 unmasks the interrupt. - 0x000008ff - - - M_RESTART_DET - This bit masks the R_RESTART_DET interrupt in IC_INTR_STAT register. - - Reset value: 0x0 - [12:12] - read-write - - - ENABLED - 0 - RESTART_DET interrupt is masked - - - DISABLED - 1 - RESTART_DET interrupt is unmasked - - - - - M_GEN_CALL - This bit masks the R_GEN_CALL interrupt in IC_INTR_STAT register. - - Reset value: 0x1 - [11:11] - read-write - - - ENABLED - 0 - GEN_CALL interrupt is masked - - - DISABLED - 1 - GEN_CALL interrupt is unmasked - - - - - M_START_DET - This bit masks the R_START_DET interrupt in IC_INTR_STAT register. - - Reset value: 0x0 - [10:10] - read-write - - - ENABLED - 0 - START_DET interrupt is masked - - - DISABLED - 1 - START_DET interrupt is unmasked - - - - - M_STOP_DET - This bit masks the R_STOP_DET interrupt in IC_INTR_STAT register. - - Reset value: 0x0 - [9:9] - read-write - - - ENABLED - 0 - STOP_DET interrupt is masked - - - DISABLED - 1 - STOP_DET interrupt is unmasked - - - - - M_ACTIVITY - This bit masks the R_ACTIVITY interrupt in IC_INTR_STAT register. - - Reset value: 0x0 - [8:8] - read-write - - - ENABLED - 0 - ACTIVITY interrupt is masked - - - DISABLED - 1 - ACTIVITY interrupt is unmasked - - - - - M_RX_DONE - This bit masks the R_RX_DONE interrupt in IC_INTR_STAT register. - - Reset value: 0x1 - [7:7] - read-write - - - ENABLED - 0 - RX_DONE interrupt is masked - - - DISABLED - 1 - RX_DONE interrupt is unmasked - - - - - M_TX_ABRT - This bit masks the R_TX_ABRT interrupt in IC_INTR_STAT register. - - Reset value: 0x1 - [6:6] - read-write - - - ENABLED - 0 - TX_ABORT interrupt is masked - - - DISABLED - 1 - TX_ABORT interrupt is unmasked - - - - - M_RD_REQ - This bit masks the R_RD_REQ interrupt in IC_INTR_STAT register. - - Reset value: 0x1 - [5:5] - read-write - - - ENABLED - 0 - RD_REQ interrupt is masked - - - DISABLED - 1 - RD_REQ interrupt is unmasked - - - - - M_TX_EMPTY - This bit masks the R_TX_EMPTY interrupt in IC_INTR_STAT register. - - Reset value: 0x1 - [4:4] - read-write - - - ENABLED - 0 - TX_EMPTY interrupt is masked - - - DISABLED - 1 - TX_EMPTY interrupt is unmasked - - - - - M_TX_OVER - This bit masks the R_TX_OVER interrupt in IC_INTR_STAT register. - - Reset value: 0x1 - [3:3] - read-write - - - ENABLED - 0 - TX_OVER interrupt is masked - - - DISABLED - 1 - TX_OVER interrupt is unmasked - - - - - M_RX_FULL - This bit masks the R_RX_FULL interrupt in IC_INTR_STAT register. - - Reset value: 0x1 - [2:2] - read-write - - - ENABLED - 0 - RX_FULL interrupt is masked - - - DISABLED - 1 - RX_FULL interrupt is unmasked - - - - - M_RX_OVER - This bit masks the R_RX_OVER interrupt in IC_INTR_STAT register. - - Reset value: 0x1 - [1:1] - read-write - - - ENABLED - 0 - RX_OVER interrupt is masked - - - DISABLED - 1 - RX_OVER interrupt is unmasked - - - - - M_RX_UNDER - This bit masks the R_RX_UNDER interrupt in IC_INTR_STAT register. - - Reset value: 0x1 - [0:0] - read-write - - - ENABLED - 0 - RX_UNDER interrupt is masked - - - DISABLED - 1 - RX_UNDER interrupt is unmasked - - - - - - - IC_RAW_INTR_STAT - 0x00000034 - I2C Raw Interrupt Status Register - - Unlike the IC_INTR_STAT register, these bits are not masked so they always show the true status of the DW_apb_i2c. - 0x00000000 - - - RESTART_DET - Indicates whether a RESTART condition has occurred on the I2C interface when DW_apb_i2c is operating in Slave mode and the slave is being addressed. Enabled only when IC_SLV_RESTART_DET_EN=1. - - Note: However, in high-speed mode or during a START BYTE transfer, the RESTART comes before the address field as per the I2C protocol. In this case, the slave is not the addressed slave when the RESTART is issued, therefore DW_apb_i2c does not generate the RESTART_DET interrupt. - - Reset value: 0x0 - [12:12] - read-only - - - INACTIVE - 0 - RESTART_DET interrupt is inactive - - - ACTIVE - 1 - RESTART_DET interrupt is active - - - - - GEN_CALL - Set only when a General Call address is received and it is acknowledged. It stays set until it is cleared either by disabling DW_apb_i2c or when the CPU reads bit 0 of the IC_CLR_GEN_CALL register. DW_apb_i2c stores the received data in the Rx buffer. - - Reset value: 0x0 - [11:11] - read-only - - - INACTIVE - 0 - GEN_CALL interrupt is inactive - - - ACTIVE - 1 - GEN_CALL interrupt is active - - - - - START_DET - Indicates whether a START or RESTART condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode. - - Reset value: 0x0 - [10:10] - read-only - - - INACTIVE - 0 - START_DET interrupt is inactive - - - ACTIVE - 1 - START_DET interrupt is active - - - - - STOP_DET - Indicates whether a STOP condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode. - - In Slave Mode: - If IC_CON[7]=1'b1 (STOP_DET_IFADDRESSED), the STOP_DET interrupt will be issued only if slave is addressed. Note: During a general call address, this slave does not issue a STOP_DET interrupt if STOP_DET_IF_ADDRESSED=1'b1, even if the slave responds to the general call address by generating ACK. The STOP_DET interrupt is generated only when the transmitted address matches the slave address (SAR). - If IC_CON[7]=1'b0 (STOP_DET_IFADDRESSED), the STOP_DET interrupt is issued irrespective of whether it is being addressed. In Master Mode: - If IC_CON[10]=1'b1 (STOP_DET_IF_MASTER_ACTIVE),the STOP_DET interrupt will be issued only if Master is active. - If IC_CON[10]=1'b0 (STOP_DET_IFADDRESSED),the STOP_DET interrupt will be issued irrespective of whether master is active or not. Reset value: 0x0 - [9:9] - read-only - - - INACTIVE - 0 - STOP_DET interrupt is inactive - - - ACTIVE - 1 - STOP_DET interrupt is active - - - - - ACTIVITY - This bit captures DW_apb_i2c activity and stays set until it is cleared. There are four ways to clear it: - Disabling the DW_apb_i2c - Reading the IC_CLR_ACTIVITY register - Reading the IC_CLR_INTR register - System reset Once this bit is set, it stays set unless one of the four methods is used to clear it. Even if the DW_apb_i2c module is idle, this bit remains set until cleared, indicating that there was activity on the bus. - - Reset value: 0x0 - [8:8] - read-only - - - INACTIVE - 0 - RAW_INTR_ACTIVITY interrupt is inactive - - - ACTIVE - 1 - RAW_INTR_ACTIVITY interrupt is active - - - - - RX_DONE - When the DW_apb_i2c is acting as a slave-transmitter, this bit is set to 1 if the master does not acknowledge a transmitted byte. This occurs on the last byte of the transmission, indicating that the transmission is done. - - Reset value: 0x0 - [7:7] - read-only - - - INACTIVE - 0 - RX_DONE interrupt is inactive - - - ACTIVE - 1 - RX_DONE interrupt is active - - - - - TX_ABRT - This bit indicates if DW_apb_i2c, as an I2C transmitter, is unable to complete the intended actions on the contents of the transmit FIFO. This situation can occur both as an I2C master or an I2C slave, and is referred to as a 'transmit abort'. When this bit is set to 1, the IC_TX_ABRT_SOURCE register indicates the reason why the transmit abort takes places. - - Note: The DW_apb_i2c flushes/resets/empties the TX_FIFO and RX_FIFO whenever there is a transmit abort caused by any of the events tracked by the IC_TX_ABRT_SOURCE register. The FIFOs remains in this flushed state until the register IC_CLR_TX_ABRT is read. Once this read is performed, the Tx FIFO is then ready to accept more data bytes from the APB interface. - - Reset value: 0x0 - [6:6] - read-only - - - INACTIVE - 0 - TX_ABRT interrupt is inactive - - - ACTIVE - 1 - TX_ABRT interrupt is active - - - - - RD_REQ - This bit is set to 1 when DW_apb_i2c is acting as a slave and another I2C master is attempting to read data from DW_apb_i2c. The DW_apb_i2c holds the I2C bus in a wait state (SCL=0) until this interrupt is serviced, which means that the slave has been addressed by a remote master that is asking for data to be transferred. The processor must respond to this interrupt and then write the requested data to the IC_DATA_CMD register. This bit is set to 0 just after the processor reads the IC_CLR_RD_REQ register. - - Reset value: 0x0 - [5:5] - read-only - - - INACTIVE - 0 - RD_REQ interrupt is inactive - - - ACTIVE - 1 - RD_REQ interrupt is active - - - - - TX_EMPTY - The behavior of the TX_EMPTY interrupt status differs based on the TX_EMPTY_CTRL selection in the IC_CON register. - When TX_EMPTY_CTRL = 0: This bit is set to 1 when the transmit buffer is at or below the threshold value set in the IC_TX_TL register. - When TX_EMPTY_CTRL = 1: This bit is set to 1 when the transmit buffer is at or below the threshold value set in the IC_TX_TL register and the transmission of the address/data from the internal shift register for the most recently popped command is completed. It is automatically cleared by hardware when the buffer level goes above the threshold. When IC_ENABLE[0] is set to 0, the TX FIFO is flushed and held in reset. There the TX FIFO looks like it has no data within it, so this bit is set to 1, provided there is activity in the master or slave state machines. When there is no longer any activity, then with ic_en=0, this bit is set to 0. - - Reset value: 0x0. - [4:4] - read-only - - - INACTIVE - 0 - TX_EMPTY interrupt is inactive - - - ACTIVE - 1 - TX_EMPTY interrupt is active - - - - - TX_OVER - Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH and the processor attempts to issue another I2C command by writing to the IC_DATA_CMD register. When the module is disabled, this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared. - - Reset value: 0x0 - [3:3] - read-only - - - INACTIVE - 0 - TX_OVER interrupt is inactive - - - ACTIVE - 1 - TX_OVER interrupt is active - - - - - RX_FULL - Set when the receive buffer reaches or goes above the RX_TL threshold in the IC_RX_TL register. It is automatically cleared by hardware when buffer level goes below the threshold. If the module is disabled (IC_ENABLE[0]=0), the RX FIFO is flushed and held in reset; therefore the RX FIFO is not full. So this bit is cleared once the IC_ENABLE bit 0 is programmed with a 0, regardless of the activity that continues. - - Reset value: 0x0 - [2:2] - read-only - - - INACTIVE - 0 - RX_FULL interrupt is inactive - - - ACTIVE - 1 - RX_FULL interrupt is active - - - - - RX_OVER - Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and an additional byte is received from an external I2C device. The DW_apb_i2c acknowledges this, but any data bytes received after the FIFO is full are lost. If the module is disabled (IC_ENABLE[0]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared. - - Note: If bit 9 of the IC_CON register (RX_FIFO_FULL_HLD_CTRL) is programmed to HIGH, then the RX_OVER interrupt never occurs, because the Rx FIFO never overflows. - - Reset value: 0x0 - [1:1] - read-only - - - INACTIVE - 0 - RX_OVER interrupt is inactive - - - ACTIVE - 1 - RX_OVER interrupt is active - - - - - RX_UNDER - Set if the processor attempts to read the receive buffer when it is empty by reading from the IC_DATA_CMD register. If the module is disabled (IC_ENABLE[0]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared. - - Reset value: 0x0 - [0:0] - read-only - - - INACTIVE - 0 - RX_UNDER interrupt is inactive - - - ACTIVE - 1 - RX_UNDER interrupt is active - - - - - - - IC_RX_TL - 0x00000038 - I2C Receive FIFO Threshold Register - 0x00000000 - - - RX_TL - Receive FIFO Threshold Level. - - Controls the level of entries (or above) that triggers the RX_FULL interrupt (bit 2 in IC_RAW_INTR_STAT register). The valid range is 0-255, with the additional restriction that hardware does not allow this value to be set to a value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 1 entry, and a value of 255 sets the threshold for 256 entries. - [7:0] - read-write - - - - - IC_TX_TL - 0x0000003c - I2C Transmit FIFO Threshold Register - 0x00000000 - - - TX_TL - Transmit FIFO Threshold Level. - - Controls the level of entries (or below) that trigger the TX_EMPTY interrupt (bit 4 in IC_RAW_INTR_STAT register). The valid range is 0-255, with the additional restriction that it may not be set to value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 0 entries, and a value of 255 sets the threshold for 255 entries. - [7:0] - read-write - - - - - IC_CLR_INTR - 0x00000040 - Clear Combined and Individual Interrupt Register - 0x00000000 - - - CLR_INTR - Read this register to clear the combined interrupt, all individual interrupts, and the IC_TX_ABRT_SOURCE register. This bit does not clear hardware clearable interrupts but software clearable interrupts. Refer to Bit 9 of the IC_TX_ABRT_SOURCE register for an exception to clearing IC_TX_ABRT_SOURCE. - - Reset value: 0x0 - [0:0] - read-only - - - - - IC_CLR_RX_UNDER - 0x00000044 - Clear RX_UNDER Interrupt Register - 0x00000000 - - - CLR_RX_UNDER - Read this register to clear the RX_UNDER interrupt (bit 0) of the IC_RAW_INTR_STAT register. - - Reset value: 0x0 - [0:0] - read-only - - - - - IC_CLR_RX_OVER - 0x00000048 - Clear RX_OVER Interrupt Register - 0x00000000 - - - CLR_RX_OVER - Read this register to clear the RX_OVER interrupt (bit 1) of the IC_RAW_INTR_STAT register. - - Reset value: 0x0 - [0:0] - read-only - - - - - IC_CLR_TX_OVER - 0x0000004c - Clear TX_OVER Interrupt Register - 0x00000000 - - - CLR_TX_OVER - Read this register to clear the TX_OVER interrupt (bit 3) of the IC_RAW_INTR_STAT register. - - Reset value: 0x0 - [0:0] - read-only - - - - - IC_CLR_RD_REQ - 0x00000050 - Clear RD_REQ Interrupt Register - 0x00000000 - - - CLR_RD_REQ - Read this register to clear the RD_REQ interrupt (bit 5) of the IC_RAW_INTR_STAT register. - - Reset value: 0x0 - [0:0] - read-only - - - - - IC_CLR_TX_ABRT - 0x00000054 - Clear TX_ABRT Interrupt Register - 0x00000000 - - - CLR_TX_ABRT - Read this register to clear the TX_ABRT interrupt (bit 6) of the IC_RAW_INTR_STAT register, and the IC_TX_ABRT_SOURCE register. This also releases the TX FIFO from the flushed/reset state, allowing more writes to the TX FIFO. Refer to Bit 9 of the IC_TX_ABRT_SOURCE register for an exception to clearing IC_TX_ABRT_SOURCE. - - Reset value: 0x0 - [0:0] - read-only - - - - - IC_CLR_RX_DONE - 0x00000058 - Clear RX_DONE Interrupt Register - 0x00000000 - - - CLR_RX_DONE - Read this register to clear the RX_DONE interrupt (bit 7) of the IC_RAW_INTR_STAT register. - - Reset value: 0x0 - [0:0] - read-only - - - - - IC_CLR_ACTIVITY - 0x0000005c - Clear ACTIVITY Interrupt Register - 0x00000000 - - - CLR_ACTIVITY - Reading this register clears the ACTIVITY interrupt if the I2C is not active anymore. If the I2C module is still active on the bus, the ACTIVITY interrupt bit continues to be set. It is automatically cleared by hardware if the module is disabled and if there is no further activity on the bus. The value read from this register to get status of the ACTIVITY interrupt (bit 8) of the IC_RAW_INTR_STAT register. - - Reset value: 0x0 - [0:0] - read-only - - - - - IC_CLR_STOP_DET - 0x00000060 - Clear STOP_DET Interrupt Register - 0x00000000 - - - CLR_STOP_DET - Read this register to clear the STOP_DET interrupt (bit 9) of the IC_RAW_INTR_STAT register. - - Reset value: 0x0 - [0:0] - read-only - - - - - IC_CLR_START_DET - 0x00000064 - Clear START_DET Interrupt Register - 0x00000000 - - - CLR_START_DET - Read this register to clear the START_DET interrupt (bit 10) of the IC_RAW_INTR_STAT register. - - Reset value: 0x0 - [0:0] - read-only - - - - - IC_CLR_GEN_CALL - 0x00000068 - Clear GEN_CALL Interrupt Register - 0x00000000 - - - CLR_GEN_CALL - Read this register to clear the GEN_CALL interrupt (bit 11) of IC_RAW_INTR_STAT register. - - Reset value: 0x0 - [0:0] - read-only - - - - - IC_ENABLE - 0x0000006c - I2C Enable Register - 0x00000000 - - - TX_CMD_BLOCK - In Master mode: - 1'b1: Blocks the transmission of data on I2C bus even if Tx FIFO has data to transmit. - 1'b0: The transmission of data starts on I2C bus automatically, as soon as the first data is available in the Tx FIFO. Note: To block the execution of Master commands, set the TX_CMD_BLOCK bit only when Tx FIFO is empty (IC_STATUS[2]==1) and Master is in Idle state (IC_STATUS[5] == 0). Any further commands put in the Tx FIFO are not executed until TX_CMD_BLOCK bit is unset. Reset value: IC_TX_CMD_BLOCK_DEFAULT - [2:2] - read-write - - - NOT_BLOCKED - 0 - Tx Command execution not blocked - - - BLOCKED - 1 - Tx Command execution blocked - - - - - ABORT - When set, the controller initiates the transfer abort. - 0: ABORT not initiated or ABORT done - 1: ABORT operation in progress The software can abort the I2C transfer in master mode by setting this bit. The software can set this bit only when ENABLE is already set; otherwise, the controller ignores any write to ABORT bit. The software cannot clear the ABORT bit once set. In response to an ABORT, the controller issues a STOP and flushes the Tx FIFO after completing the current transfer, then sets the TX_ABORT interrupt after the abort operation. The ABORT bit is cleared automatically after the abort operation. - - For a detailed description on how to abort I2C transfers, refer to 'Aborting I2C Transfers'. - - Reset value: 0x0 - [1:1] - read-write - - - DISABLE - 0 - ABORT operation not in progress - - - ENABLED - 1 - ABORT operation in progress - - - - - ENABLE - Controls whether the DW_apb_i2c is enabled. - 0: Disables DW_apb_i2c (TX and RX FIFOs are held in an erased state) - 1: Enables DW_apb_i2c Software can disable DW_apb_i2c while it is active. However, it is important that care be taken to ensure that DW_apb_i2c is disabled properly. A recommended procedure is described in 'Disabling DW_apb_i2c'. - - When DW_apb_i2c is disabled, the following occurs: - The TX FIFO and RX FIFO get flushed. - Status bits in the IC_INTR_STAT register are still active until DW_apb_i2c goes into IDLE state. If the module is transmitting, it stops as well as deletes the contents of the transmit buffer after the current transfer is complete. If the module is receiving, the DW_apb_i2c stops the current transfer at the end of the current byte and does not acknowledge the transfer. - - In systems with asynchronous pclk and ic_clk when IC_CLK_TYPE parameter set to asynchronous (1), there is a two ic_clk delay when enabling or disabling the DW_apb_i2c. For a detailed description on how to disable DW_apb_i2c, refer to 'Disabling DW_apb_i2c' - - Reset value: 0x0 - [0:0] - read-write - - - DISABLED - 0 - I2C is disabled - - - ENABLED - 1 - I2C is enabled - - - - - - - IC_STATUS - 0x00000070 - I2C Status Register - - This is a read-only register used to indicate the current transfer status and FIFO status. The status register may be read at any time. None of the bits in this register request an interrupt. - - When the I2C is disabled by writing 0 in bit 0 of the IC_ENABLE register: - Bits 1 and 2 are set to 1 - Bits 3 and 10 are set to 0 When the master or slave state machines goes to idle and ic_en=0: - Bits 5 and 6 are set to 0 - 0x00000006 - - - SLV_ACTIVITY - Slave FSM Activity Status. When the Slave Finite State Machine (FSM) is not in the IDLE state, this bit is set. - 0: Slave FSM is in IDLE state so the Slave part of DW_apb_i2c is not Active - 1: Slave FSM is not in IDLE state so the Slave part of DW_apb_i2c is Active Reset value: 0x0 - [6:6] - read-only - - - IDLE - 0 - Slave is idle - - - ACTIVE - 1 - Slave not idle - - - - - MST_ACTIVITY - Master FSM Activity Status. When the Master Finite State Machine (FSM) is not in the IDLE state, this bit is set. - 0: Master FSM is in IDLE state so the Master part of DW_apb_i2c is not Active - 1: Master FSM is not in IDLE state so the Master part of DW_apb_i2c is Active Note: IC_STATUS[0]-that is, ACTIVITY bit-is the OR of SLV_ACTIVITY and MST_ACTIVITY bits. - - Reset value: 0x0 - [5:5] - read-only - - - IDLE - 0 - Master is idle - - - ACTIVE - 1 - Master not idle - - - - - RFF - Receive FIFO Completely Full. When the receive FIFO is completely full, this bit is set. When the receive FIFO contains one or more empty location, this bit is cleared. - 0: Receive FIFO is not full - 1: Receive FIFO is full Reset value: 0x0 - [4:4] - read-only - - - NOT_FULL - 0 - Rx FIFO not full - - - FULL - 1 - Rx FIFO is full - - - - - RFNE - Receive FIFO Not Empty. This bit is set when the receive FIFO contains one or more entries; it is cleared when the receive FIFO is empty. - 0: Receive FIFO is empty - 1: Receive FIFO is not empty Reset value: 0x0 - [3:3] - read-only - - - EMPTY - 0 - Rx FIFO is empty - - - NOT_EMPTY - 1 - Rx FIFO not empty - - - - - TFE - Transmit FIFO Completely Empty. When the transmit FIFO is completely empty, this bit is set. When it contains one or more valid entries, this bit is cleared. This bit field does not request an interrupt. - 0: Transmit FIFO is not empty - 1: Transmit FIFO is empty Reset value: 0x1 - [2:2] - read-only - - - NON_EMPTY - 0 - Tx FIFO not empty - - - EMPTY - 1 - Tx FIFO is empty - - - - - TFNF - Transmit FIFO Not Full. Set when the transmit FIFO contains one or more empty locations, and is cleared when the FIFO is full. - 0: Transmit FIFO is full - 1: Transmit FIFO is not full Reset value: 0x1 - [1:1] - read-only - - - FULL - 0 - Tx FIFO is full - - - NOT_FULL - 1 - Tx FIFO not full - - - - - ACTIVITY - I2C Activity Status. Reset value: 0x0 - [0:0] - read-only - - - INACTIVE - 0 - I2C is idle - - - ACTIVE - 1 - I2C is active - - - - - - - IC_TXFLR - 0x00000074 - I2C Transmit FIFO Level Register This register contains the number of valid data entries in the transmit FIFO buffer. It is cleared whenever: - The I2C is disabled - There is a transmit abort - that is, TX_ABRT bit is set in the IC_RAW_INTR_STAT register - The slave bulk transmit mode is aborted The register increments whenever data is placed into the transmit FIFO and decrements when data is taken from the transmit FIFO. - 0x00000000 - - - TXFLR - Transmit FIFO Level. Contains the number of valid data entries in the transmit FIFO. - - Reset value: 0x0 - [4:0] - read-only - - - - - IC_RXFLR - 0x00000078 - I2C Receive FIFO Level Register This register contains the number of valid data entries in the receive FIFO buffer. It is cleared whenever: - The I2C is disabled - Whenever there is a transmit abort caused by any of the events tracked in IC_TX_ABRT_SOURCE The register increments whenever data is placed into the receive FIFO and decrements when data is taken from the receive FIFO. - 0x00000000 - - - RXFLR - Receive FIFO Level. Contains the number of valid data entries in the receive FIFO. - - Reset value: 0x0 - [4:0] - read-only - - - - - IC_SDA_HOLD - 0x0000007c - I2C SDA Hold Time Length Register - - The bits [15:0] of this register are used to control the hold time of SDA during transmit in both slave and master mode (after SCL goes from HIGH to LOW). - - The bits [23:16] of this register are used to extend the SDA transition (if any) whenever SCL is HIGH in the receiver in either master or slave mode. - - Writes to this register succeed only when IC_ENABLE[0]=0. - - The values in this register are in units of ic_clk period. The value programmed in IC_SDA_TX_HOLD must be greater than the minimum hold time in each mode (one cycle in master mode, seven cycles in slave mode) for the value to be implemented. - - The programmed SDA hold time during transmit (IC_SDA_TX_HOLD) cannot exceed at any time the duration of the low part of scl. Therefore the programmed value cannot be larger than N_SCL_LOW-2, where N_SCL_LOW is the duration of the low part of the scl period measured in ic_clk cycles. - 0x00000001 - - - IC_SDA_RX_HOLD - Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c acts as a receiver. - - Reset value: IC_DEFAULT_SDA_HOLD[23:16]. - [23:16] - read-write - - - IC_SDA_TX_HOLD - Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c acts as a transmitter. - - Reset value: IC_DEFAULT_SDA_HOLD[15:0]. - [15:0] - read-write - - - - - IC_TX_ABRT_SOURCE - 0x00000080 - I2C Transmit Abort Source Register - - This register has 32 bits that indicate the source of the TX_ABRT bit. Except for Bit 9, this register is cleared whenever the IC_CLR_TX_ABRT register or the IC_CLR_INTR register is read. To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed first; RESTART must be enabled (IC_CON[5]=1), the SPECIAL bit must be cleared (IC_TAR[11]), or the GC_OR_START bit must be cleared (IC_TAR[10]). - - Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in the same manner as other bits in this register. If the source of the ABRT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, Bit 9 clears for one cycle and is then re-asserted. - 0x00000000 - - - TX_FLUSH_CNT - This field indicates the number of Tx FIFO Data Commands which are flushed due to TX_ABRT interrupt. It is cleared whenever I2C is disabled. - - Reset value: 0x0 - - Role of DW_apb_i2c: Master-Transmitter or Slave-Transmitter - [31:23] - read-only - - - ABRT_USER_ABRT - This is a master-mode-only bit. Master has detected the transfer abort (IC_ENABLE[1]) - - Reset value: 0x0 - - Role of DW_apb_i2c: Master-Transmitter - [16:16] - read-only - - - ABRT_USER_ABRT_VOID - 0 - Transfer abort detected by master- scenario not present - - - ABRT_USER_ABRT_GENERATED - 1 - Transfer abort detected by master - - - - - ABRT_SLVRD_INTX - 1: When the processor side responds to a slave mode request for data to be transmitted to a remote master and user writes a 1 in CMD (bit 8) of IC_DATA_CMD register. - - Reset value: 0x0 - - Role of DW_apb_i2c: Slave-Transmitter - [15:15] - read-only - - - ABRT_SLVRD_INTX_VOID - 0 - Slave trying to transmit to remote master in read mode- scenario not present - - - ABRT_SLVRD_INTX_GENERATED - 1 - Slave trying to transmit to remote master in read mode - - - - - ABRT_SLV_ARBLOST - This field indicates that a Slave has lost the bus while transmitting data to a remote master. IC_TX_ABRT_SOURCE[12] is set at the same time. Note: Even though the slave never 'owns' the bus, something could go wrong on the bus. This is a fail safe check. For instance, during a data transmission at the low-to-high transition of SCL, if what is on the data bus is not what is supposed to be transmitted, then DW_apb_i2c no longer own the bus. - - Reset value: 0x0 - - Role of DW_apb_i2c: Slave-Transmitter - [14:14] - read-only - - - ABRT_SLV_ARBLOST_VOID - 0 - Slave lost arbitration to remote master- scenario not present - - - ABRT_SLV_ARBLOST_GENERATED - 1 - Slave lost arbitration to remote master - - - - - ABRT_SLVFLUSH_TXFIFO - This field specifies that the Slave has received a read command and some data exists in the TX FIFO, so the slave issues a TX_ABRT interrupt to flush old data in TX FIFO. - - Reset value: 0x0 - - Role of DW_apb_i2c: Slave-Transmitter - [13:13] - read-only - - - ABRT_SLVFLUSH_TXFIFO_VOID - 0 - Slave flushes existing data in TX-FIFO upon getting read command- scenario not present - - - ABRT_SLVFLUSH_TXFIFO_GENERATED - 1 - Slave flushes existing data in TX-FIFO upon getting read command - - - - - ARB_LOST - This field specifies that the Master has lost arbitration, or if IC_TX_ABRT_SOURCE[14] is also set, then the slave transmitter has lost arbitration. - - Reset value: 0x0 - - Role of DW_apb_i2c: Master-Transmitter or Slave-Transmitter - [12:12] - read-only - - - ABRT_LOST_VOID - 0 - Master or Slave-Transmitter lost arbitration- scenario not present - - - ABRT_LOST_GENERATED - 1 - Master or Slave-Transmitter lost arbitration - - - - - ABRT_MASTER_DIS - This field indicates that the User tries to initiate a Master operation with the Master mode disabled. - - Reset value: 0x0 - - Role of DW_apb_i2c: Master-Transmitter or Master-Receiver - [11:11] - read-only - - - ABRT_MASTER_DIS_VOID - 0 - User initiating master operation when MASTER disabled- scenario not present - - - ABRT_MASTER_DIS_GENERATED - 1 - User initiating master operation when MASTER disabled - - - - - ABRT_10B_RD_NORSTRT - This field indicates that the restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the master sends a read command in 10-bit addressing mode. - - Reset value: 0x0 - - Role of DW_apb_i2c: Master-Receiver - [10:10] - read-only - - - ABRT_10B_RD_VOID - 0 - Master not trying to read in 10Bit addressing mode when RESTART disabled - - - ABRT_10B_RD_GENERATED - 1 - Master trying to read in 10Bit addressing mode when RESTART disabled - - - - - ABRT_SBYTE_NORSTRT - To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed first; restart must be enabled (IC_CON[5]=1), the SPECIAL bit must be cleared (IC_TAR[11]), or the GC_OR_START bit must be cleared (IC_TAR[10]). Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in the same manner as other bits in this register. If the source of the ABRT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, bit 9 clears for one cycle and then gets reasserted. When this field is set to 1, the restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the user is trying to send a START Byte. - - Reset value: 0x0 - - Role of DW_apb_i2c: Master - [9:9] - read-only - - - ABRT_SBYTE_NORSTRT_VOID - 0 - User trying to send START byte when RESTART disabled- scenario not present - - - ABRT_SBYTE_NORSTRT_GENERATED - 1 - User trying to send START byte when RESTART disabled - - - - - ABRT_HS_NORSTRT - This field indicates that the restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the user is trying to use the master to transfer data in High Speed mode. - - Reset value: 0x0 - - Role of DW_apb_i2c: Master-Transmitter or Master-Receiver - [8:8] - read-only - - - ABRT_HS_NORSTRT_VOID - 0 - User trying to switch Master to HS mode when RESTART disabled- scenario not present - - - ABRT_HS_NORSTRT_GENERATED - 1 - User trying to switch Master to HS mode when RESTART disabled - - - - - ABRT_SBYTE_ACKDET - This field indicates that the Master has sent a START Byte and the START Byte was acknowledged (wrong behavior). - - Reset value: 0x0 - - Role of DW_apb_i2c: Master - [7:7] - read-only - - - ABRT_SBYTE_ACKDET_VOID - 0 - ACK detected for START byte- scenario not present - - - ABRT_SBYTE_ACKDET_GENERATED - 1 - ACK detected for START byte - - - - - ABRT_HS_ACKDET - This field indicates that the Master is in High Speed mode and the High Speed Master code was acknowledged (wrong behavior). - - Reset value: 0x0 - - Role of DW_apb_i2c: Master - [6:6] - read-only - - - ABRT_HS_ACK_VOID - 0 - HS Master code ACKed in HS Mode- scenario not present - - - ABRT_HS_ACK_GENERATED - 1 - HS Master code ACKed in HS Mode - - - - - ABRT_GCALL_READ - This field indicates that DW_apb_i2c in the master mode has sent a General Call but the user programmed the byte following the General Call to be a read from the bus (IC_DATA_CMD[9] is set to 1). - - Reset value: 0x0 - - Role of DW_apb_i2c: Master-Transmitter - [5:5] - read-only - - - ABRT_GCALL_READ_VOID - 0 - GCALL is followed by read from bus-scenario not present - - - ABRT_GCALL_READ_GENERATED - 1 - GCALL is followed by read from bus - - - - - ABRT_GCALL_NOACK - This field indicates that DW_apb_i2c in master mode has sent a General Call and no slave on the bus acknowledged the General Call. - - Reset value: 0x0 - - Role of DW_apb_i2c: Master-Transmitter - [4:4] - read-only - - - ABRT_GCALL_NOACK_VOID - 0 - GCALL not ACKed by any slave-scenario not present - - - ABRT_GCALL_NOACK_GENERATED - 1 - GCALL not ACKed by any slave - - - - - ABRT_TXDATA_NOACK - This field indicates the master-mode only bit. When the master receives an acknowledgement for the address, but when it sends data byte(s) following the address, it did not receive an acknowledge from the remote slave(s). - - Reset value: 0x0 - - Role of DW_apb_i2c: Master-Transmitter - [3:3] - read-only - - - ABRT_TXDATA_NOACK_VOID - 0 - Transmitted data non-ACKed by addressed slave-scenario not present - - - ABRT_TXDATA_NOACK_GENERATED - 1 - Transmitted data not ACKed by addressed slave - - - - - ABRT_10ADDR2_NOACK - This field indicates that the Master is in 10-bit address mode and that the second address byte of the 10-bit address was not acknowledged by any slave. - - Reset value: 0x0 - - Role of DW_apb_i2c: Master-Transmitter or Master-Receiver - [2:2] - read-only - - - INACTIVE - 0 - This abort is not generated - - - ACTIVE - 1 - Byte 2 of 10Bit Address not ACKed by any slave - - - - - ABRT_10ADDR1_NOACK - This field indicates that the Master is in 10-bit address mode and the first 10-bit address byte was not acknowledged by any slave. - - Reset value: 0x0 - - Role of DW_apb_i2c: Master-Transmitter or Master-Receiver - [1:1] - read-only - - - INACTIVE - 0 - This abort is not generated - - - ACTIVE - 1 - Byte 1 of 10Bit Address not ACKed by any slave - - - - - ABRT_7B_ADDR_NOACK - This field indicates that the Master is in 7-bit addressing mode and the address sent was not acknowledged by any slave. - - Reset value: 0x0 - - Role of DW_apb_i2c: Master-Transmitter or Master-Receiver - [0:0] - read-only - - - INACTIVE - 0 - This abort is not generated - - - ACTIVE - 1 - This abort is generated because of NOACK for 7-bit address - - - - - - - IC_SLV_DATA_NACK_ONLY - 0x00000084 - Generate Slave Data NACK Register - - The register is used to generate a NACK for the data part of a transfer when DW_apb_i2c is acting as a slave-receiver. This register only exists when the IC_SLV_DATA_NACK_ONLY parameter is set to 1. When this parameter disabled, this register does not exist and writing to the register's address has no effect. - - A write can occur on this register if both of the following conditions are met: - DW_apb_i2c is disabled (IC_ENABLE[0] = 0) - Slave part is inactive (IC_STATUS[6] = 0) Note: The IC_STATUS[6] is a register read-back location for the internal slv_activity signal; the user should poll this before writing the ic_slv_data_nack_only bit. - 0x00000000 - - - NACK - Generate NACK. This NACK generation only occurs when DW_apb_i2c is a slave-receiver. If this register is set to a value of 1, it can only generate a NACK after a data byte is received; hence, the data transfer is aborted and the data received is not pushed to the receive buffer. - - When the register is set to a value of 0, it generates NACK/ACK, depending on normal criteria. - 1: generate NACK after data byte received - 0: generate NACK/ACK normally Reset value: 0x0 - [0:0] - read-write - - - DISABLED - 0 - Slave receiver generates NACK normally - - - ENABLED - 1 - Slave receiver generates NACK upon data reception only - - - - - - - IC_DMA_CR - 0x00000088 - DMA Control Register - - The register is used to enable the DMA Controller interface operation. There is a separate bit for transmit and receive. This can be programmed regardless of the state of IC_ENABLE. - 0x00000000 - - - TDMAE - Transmit DMA Enable. This bit enables/disables the transmit FIFO DMA channel. Reset value: 0x0 - [1:1] - read-write - - - DISABLED - 0 - transmit FIFO DMA channel disabled - - - ENABLED - 1 - Transmit FIFO DMA channel enabled - - - - - RDMAE - Receive DMA Enable. This bit enables/disables the receive FIFO DMA channel. Reset value: 0x0 - [0:0] - read-write - - - DISABLED - 0 - Receive FIFO DMA channel disabled - - - ENABLED - 1 - Receive FIFO DMA channel enabled - - - - - - - IC_DMA_TDLR - 0x0000008c - DMA Transmit Data Level Register - 0x00000000 - - - DMATDL - Transmit Data Level. This bit field controls the level at which a DMA request is made by the transmit logic. It is equal to the watermark level; that is, the dma_tx_req signal is generated when the number of valid data entries in the transmit FIFO is equal to or below this field value, and TDMAE = 1. - - Reset value: 0x0 - [3:0] - read-write - - - - - IC_DMA_RDLR - 0x00000090 - I2C Receive Data Level Register - 0x00000000 - - - DMARDL - Receive Data Level. This bit field controls the level at which a DMA request is made by the receive logic. The watermark level = DMARDL+1; that is, dma_rx_req is generated when the number of valid data entries in the receive FIFO is equal to or more than this field value + 1, and RDMAE =1. For instance, when DMARDL is 0, then dma_rx_req is asserted when 1 or more data entries are present in the receive FIFO. - - Reset value: 0x0 - [3:0] - read-write - - - - - IC_SDA_SETUP - 0x00000094 - I2C SDA Setup Register - - This register controls the amount of time delay (in terms of number of ic_clk clock periods) introduced in the rising edge of SCL - relative to SDA changing - when DW_apb_i2c services a read request in a slave-transmitter operation. The relevant I2C requirement is tSU:DAT (note 4) as detailed in the I2C Bus Specification. This register must be programmed with a value equal to or greater than 2. - - Writes to this register succeed only when IC_ENABLE[0] = 0. - - Note: The length of setup time is calculated using [(IC_SDA_SETUP - 1) * (ic_clk_period)], so if the user requires 10 ic_clk periods of setup time, they should program a value of 11. The IC_SDA_SETUP register is only used by the DW_apb_i2c when operating as a slave transmitter. - 0x00000064 - - - SDA_SETUP - SDA Setup. It is recommended that if the required delay is 1000ns, then for an ic_clk frequency of 10 MHz, IC_SDA_SETUP should be programmed to a value of 11. IC_SDA_SETUP must be programmed with a minimum value of 2. - [7:0] - read-write - - - - - IC_ACK_GENERAL_CALL - 0x00000098 - I2C ACK General Call Register - - The register controls whether DW_apb_i2c responds with a ACK or NACK when it receives an I2C General Call address. - - This register is applicable only when the DW_apb_i2c is in slave mode. - 0x00000001 - - - ACK_GEN_CALL - ACK General Call. When set to 1, DW_apb_i2c responds with a ACK (by asserting ic_data_oe) when it receives a General Call. Otherwise, DW_apb_i2c responds with a NACK (by negating ic_data_oe). - [0:0] - read-write - - - DISABLED - 0 - Generate NACK for a General Call - - - ENABLED - 1 - Generate ACK for a General Call - - - - - - - IC_ENABLE_STATUS - 0x0000009c - I2C Enable Status Register - - The register is used to report the DW_apb_i2c hardware status when the IC_ENABLE[0] register is set from 1 to 0; that is, when DW_apb_i2c is disabled. - - If IC_ENABLE[0] has been set to 1, bits 2:1 are forced to 0, and bit 0 is forced to 1. - - If IC_ENABLE[0] has been set to 0, bits 2:1 is only be valid as soon as bit 0 is read as '0'. - - Note: When IC_ENABLE[0] has been set to 0, a delay occurs for bit 0 to be read as 0 because disabling the DW_apb_i2c depends on I2C bus activities. - 0x00000000 - - - SLV_RX_DATA_LOST - Slave Received Data Lost. This bit indicates if a Slave-Receiver operation has been aborted with at least one data byte received from an I2C transfer due to the setting bit 0 of IC_ENABLE from 1 to 0. When read as 1, DW_apb_i2c is deemed to have been actively engaged in an aborted I2C transfer (with matching address) and the data phase of the I2C transfer has been entered, even though a data byte has been responded with a NACK. - - Note: If the remote I2C master terminates the transfer with a STOP condition before the DW_apb_i2c has a chance to NACK a transfer, and IC_ENABLE[0] has been set to 0, then this bit is also set to 1. - - When read as 0, DW_apb_i2c is deemed to have been disabled without being actively involved in the data phase of a Slave-Receiver transfer. - - Note: The CPU can safely read this bit when IC_EN (bit 0) is read as 0. - - Reset value: 0x0 - [2:2] - read-only - - - INACTIVE - 0 - Slave RX Data is not lost - - - ACTIVE - 1 - Slave RX Data is lost - - - - - SLV_DISABLED_WHILE_BUSY - Slave Disabled While Busy (Transmit, Receive). This bit indicates if a potential or active Slave operation has been aborted due to the setting bit 0 of the IC_ENABLE register from 1 to 0. This bit is set when the CPU writes a 0 to the IC_ENABLE register while: - - (a) DW_apb_i2c is receiving the address byte of the Slave-Transmitter operation from a remote master; - - OR, - - (b) address and data bytes of the Slave-Receiver operation from a remote master. - - When read as 1, DW_apb_i2c is deemed to have forced a NACK during any part of an I2C transfer, irrespective of whether the I2C address matches the slave address set in DW_apb_i2c (IC_SAR register) OR if the transfer is completed before IC_ENABLE is set to 0 but has not taken effect. - - Note: If the remote I2C master terminates the transfer with a STOP condition before the DW_apb_i2c has a chance to NACK a transfer, and IC_ENABLE[0] has been set to 0, then this bit will also be set to 1. - - When read as 0, DW_apb_i2c is deemed to have been disabled when there is master activity, or when the I2C bus is idle. - - Note: The CPU can safely read this bit when IC_EN (bit 0) is read as 0. - - Reset value: 0x0 - [1:1] - read-only - - - INACTIVE - 0 - Slave is disabled when it is idle - - - ACTIVE - 1 - Slave is disabled when it is active - - - - - IC_EN - ic_en Status. This bit always reflects the value driven on the output port ic_en. - When read as 1, DW_apb_i2c is deemed to be in an enabled state. - When read as 0, DW_apb_i2c is deemed completely inactive. Note: The CPU can safely read this bit anytime. When this bit is read as 0, the CPU can safely read SLV_RX_DATA_LOST (bit 2) and SLV_DISABLED_WHILE_BUSY (bit 1). - - Reset value: 0x0 - [0:0] - read-only - - - DISABLED - 0 - I2C disabled - - - ENABLED - 1 - I2C enabled - - - - - - - IC_FS_SPKLEN - 0x000000a0 - I2C SS, FS or FM+ spike suppression limit - - This register is used to store the duration, measured in ic_clk cycles, of the longest spike that is filtered out by the spike suppression logic when the component is operating in SS, FS or FM+ modes. The relevant I2C requirement is tSP (table 4) as detailed in the I2C Bus Specification. This register must be programmed with a minimum value of 1. - 0x00000007 - - - IC_FS_SPKLEN - This register must be set before any I2C bus transaction can take place to ensure stable operation. This register sets the duration, measured in ic_clk cycles, of the longest spike in the SCL or SDA lines that will be filtered out by the spike suppression logic. This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect. The minimum valid value is 1; hardware prevents values less than this being written, and if attempted results in 1 being set. or more information, refer to 'Spike Suppression'. - [7:0] - read-write - - - - - IC_CLR_RESTART_DET - 0x000000a8 - Clear RESTART_DET Interrupt Register - 0x00000000 - - - CLR_RESTART_DET - Read this register to clear the RESTART_DET interrupt (bit 12) of IC_RAW_INTR_STAT register. - - Reset value: 0x0 - [0:0] - read-only - - - - - IC_COMP_PARAM_1 - 0x000000f4 - Component Parameter Register 1 - - Note This register is not implemented and therefore reads as 0. If it was implemented it would be a constant read-only register that contains encoded information about the component's parameter settings. Fields shown below are the settings for those parameters - 0x00000000 - - - TX_BUFFER_DEPTH - TX Buffer Depth = 16 - [23:16] - read-only - - - RX_BUFFER_DEPTH - RX Buffer Depth = 16 - [15:8] - read-only - - - ADD_ENCODED_PARAMS - Encoded parameters not visible - [7:7] - read-only - - - HAS_DMA - DMA handshaking signals are enabled - [6:6] - read-only - - - INTR_IO - COMBINED Interrupt outputs - [5:5] - read-only - - - HC_COUNT_VALUES - Programmable count values for each mode. - [4:4] - read-only - - - MAX_SPEED_MODE - MAX SPEED MODE = FAST MODE - [3:2] - read-only - - - APB_DATA_WIDTH - APB data bus width is 32 bits - [1:0] - read-only - - - - - IC_COMP_VERSION - 0x000000f8 - I2C Component Version Register - 0x3230312a - - - IC_COMP_VERSION - [31:0] - read-only - - - - - IC_COMP_TYPE - 0x000000fc - I2C Component Type Register - 0x44570140 - - - IC_COMP_TYPE - Designware Component Type number = 0x44_57_01_40. This assigned unique hex value is constant and is derived from the two ASCII letters 'DW' followed by a 16-bit unsigned number. - [31:0] - read-only - - - - - - - I2C1 - 0x40098000 - - I2C1_IRQ - 37 - - - - SPI0 - 0x40080000 - - 0 - 4096 - registers - - - SPI0_IRQ - 31 - - - - SSPCR0 - 0x00000000 - Control register 0, SSPCR0 on page 3-4 - 0x00000000 - - - SCR - Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: F SSPCLK CPSDVSR x (1+SCR) where CPSDVSR is an even value from 2-254, programmed through the SSPCPSR register and SCR is a value from 0-255. - [15:8] - read-write - - - SPH - SSPCLKOUT phase, applicable to Motorola SPI frame format only. See Motorola SPI frame format on page 2-10. - [7:7] - read-write - - - SPO - SSPCLKOUT polarity, applicable to Motorola SPI frame format only. See Motorola SPI frame format on page 2-10. - [6:6] - read-write - - - FRF - Frame format: 00 Motorola SPI frame format. 01 TI synchronous serial frame format. 10 National Microwire frame format. 11 Reserved, undefined operation. - [5:4] - read-write - - - DSS - Data Size Select: 0000 Reserved, undefined operation. 0001 Reserved, undefined operation. 0010 Reserved, undefined operation. 0011 4-bit data. 0100 5-bit data. 0101 6-bit data. 0110 7-bit data. 0111 8-bit data. 1000 9-bit data. 1001 10-bit data. 1010 11-bit data. 1011 12-bit data. 1100 13-bit data. 1101 14-bit data. 1110 15-bit data. 1111 16-bit data. - [3:0] - read-write - - - - - SSPCR1 - 0x00000004 - Control register 1, SSPCR1 on page 3-5 - 0x00000000 - - - SOD - Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line: 0 SSP can drive the SSPTXD output in slave mode. 1 SSP must not drive the SSPTXD output in slave mode. - [3:3] - read-write - - - MS - Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0: 0 Device configured as master, default. 1 Device configured as slave. - [2:2] - read-write - - - SSE - Synchronous serial port enable: 0 SSP operation disabled. 1 SSP operation enabled. - [1:1] - read-write - - - LBM - Loop back mode: 0 Normal serial port operation enabled. 1 Output of transmit serial shifter is connected to input of receive serial shifter internally. - [0:0] - read-write - - - - - SSPDR - 0x00000008 - Data register, SSPDR on page 3-6 - 0x00000000 - - - DATA - Transmit/Receive FIFO: Read Receive FIFO. Write Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies. - [15:0] - read-write - modify - - - - - SSPSR - 0x0000000c - Status register, SSPSR on page 3-7 - 0x00000003 - - - BSY - PrimeCell SSP busy flag, RO: 0 SSP is idle. 1 SSP is currently transmitting and/or receiving a frame or the transmit FIFO is not empty. - [4:4] - read-only - - - RFF - Receive FIFO full, RO: 0 Receive FIFO is not full. 1 Receive FIFO is full. - [3:3] - read-only - - - RNE - Receive FIFO not empty, RO: 0 Receive FIFO is empty. 1 Receive FIFO is not empty. - [2:2] - read-only - - - TNF - Transmit FIFO not full, RO: 0 Transmit FIFO is full. 1 Transmit FIFO is not full. - [1:1] - read-only - - - TFE - Transmit FIFO empty, RO: 0 Transmit FIFO is not empty. 1 Transmit FIFO is empty. - [0:0] - read-only - - - - - SSPCPSR - 0x00000010 - Clock prescale register, SSPCPSR on page 3-8 - 0x00000000 - - - CPSDVSR - Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads. - [7:0] - read-write - - - - - SSPIMSC - 0x00000014 - Interrupt mask set or clear register, SSPIMSC on page 3-9 - 0x00000000 - - - TXIM - Transmit FIFO interrupt mask: 0 Transmit FIFO half empty or less condition interrupt is masked. 1 Transmit FIFO half empty or less condition interrupt is not masked. - [3:3] - read-write - - - RXIM - Receive FIFO interrupt mask: 0 Receive FIFO half full or less condition interrupt is masked. 1 Receive FIFO half full or less condition interrupt is not masked. - [2:2] - read-write - - - RTIM - Receive timeout interrupt mask: 0 Receive FIFO not empty and no read prior to timeout period interrupt is masked. 1 Receive FIFO not empty and no read prior to timeout period interrupt is not masked. - [1:1] - read-write - - - RORIM - Receive overrun interrupt mask: 0 Receive FIFO written to while full condition interrupt is masked. 1 Receive FIFO written to while full condition interrupt is not masked. - [0:0] - read-write - - - - - SSPRIS - 0x00000018 - Raw interrupt status register, SSPRIS on page 3-10 - 0x00000008 - - - TXRIS - Gives the raw interrupt state, prior to masking, of the SSPTXINTR interrupt - [3:3] - read-only - - - RXRIS - Gives the raw interrupt state, prior to masking, of the SSPRXINTR interrupt - [2:2] - read-only - - - RTRIS - Gives the raw interrupt state, prior to masking, of the SSPRTINTR interrupt - [1:1] - read-only - - - RORRIS - Gives the raw interrupt state, prior to masking, of the SSPRORINTR interrupt - [0:0] - read-only - - - - - SSPMIS - 0x0000001c - Masked interrupt status register, SSPMIS on page 3-11 - 0x00000000 - - - TXMIS - Gives the transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt - [3:3] - read-only - - - RXMIS - Gives the receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt - [2:2] - read-only - - - RTMIS - Gives the receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt - [1:1] - read-only - - - RORMIS - Gives the receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt - [0:0] - read-only - - - - - SSPICR - 0x00000020 - Interrupt clear register, SSPICR on page 3-11 - 0x00000000 - - - RTIC - Clears the SSPRTINTR interrupt - [1:1] - read-write - oneToClear - - - RORIC - Clears the SSPRORINTR interrupt - [0:0] - read-write - oneToClear - - - - - SSPDMACR - 0x00000024 - DMA control register, SSPDMACR on page 3-12 - 0x00000000 - - - TXDMAE - Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled. - [1:1] - read-write - - - RXDMAE - Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled. - [0:0] - read-write - - - - - SSPPERIPHID0 - 0x00000fe0 - Peripheral identification registers, SSPPeriphID0-3 on page 3-13 - 0x00000022 - - - PARTNUMBER0 - These bits read back as 0x22 - [7:0] - read-only - - - - - SSPPERIPHID1 - 0x00000fe4 - Peripheral identification registers, SSPPeriphID0-3 on page 3-13 - 0x00000010 - - - DESIGNER0 - These bits read back as 0x1 - [7:4] - read-only - - - PARTNUMBER1 - These bits read back as 0x0 - [3:0] - read-only - - - - - SSPPERIPHID2 - 0x00000fe8 - Peripheral identification registers, SSPPeriphID0-3 on page 3-13 - 0x00000034 - - - REVISION - These bits return the peripheral revision - [7:4] - read-only - - - DESIGNER1 - These bits read back as 0x4 - [3:0] - read-only - - - - - SSPPERIPHID3 - 0x00000fec - Peripheral identification registers, SSPPeriphID0-3 on page 3-13 - 0x00000000 - - - CONFIGURATION - These bits read back as 0x00 - [7:0] - read-only - - - - - SSPPCELLID0 - 0x00000ff0 - PrimeCell identification registers, SSPPCellID0-3 on page 3-16 - 0x0000000d - - - SSPPCELLID0 - These bits read back as 0x0D - [7:0] - read-only - - - - - SSPPCELLID1 - 0x00000ff4 - PrimeCell identification registers, SSPPCellID0-3 on page 3-16 - 0x000000f0 - - - SSPPCELLID1 - These bits read back as 0xF0 - [7:0] - read-only - - - - - SSPPCELLID2 - 0x00000ff8 - PrimeCell identification registers, SSPPCellID0-3 on page 3-16 - 0x00000005 - - - SSPPCELLID2 - These bits read back as 0x05 - [7:0] - read-only - - - - - SSPPCELLID3 - 0x00000ffc - PrimeCell identification registers, SSPPCellID0-3 on page 3-16 - 0x000000b1 - - - SSPPCELLID3 - These bits read back as 0xB1 - [7:0] - read-only - - - - - - - SPI1 - 0x40088000 - - SPI1_IRQ - 32 - - - - PIO0 - Programmable IO block - 0x50200000 - - 0 - 392 - registers - - - PIO0_IRQ_0 - 15 - - - PIO0_IRQ_1 - 16 - - - - CTRL - 0x00000000 - PIO control register - 0x00000000 - - - NEXTPREV_CLKDIV_RESTART - Write 1 to restart the clock dividers of state machines in neighbouring PIO blocks, as specified by NEXT_PIO_MASK and PREV_PIO_MASK in the same write. - - This is equivalent to writing 1 to the corresponding CLKDIV_RESTART bits in those PIOs' CTRL registers. - [26:26] - write-only - - - NEXTPREV_SM_DISABLE - Write 1 to disable state machines in neighbouring PIO blocks, as specified by NEXT_PIO_MASK and PREV_PIO_MASK in the same write. - - This is equivalent to clearing the corresponding SM_ENABLE bits in those PIOs' CTRL registers. - [25:25] - write-only - - - NEXTPREV_SM_ENABLE - Write 1 to enable state machines in neighbouring PIO blocks, as specified by NEXT_PIO_MASK and PREV_PIO_MASK in the same write. - - This is equivalent to setting the corresponding SM_ENABLE bits in those PIOs' CTRL registers. - - If both OTHERS_SM_ENABLE and OTHERS_SM_DISABLE are set, the disable takes precedence. - [24:24] - write-only - - - NEXT_PIO_MASK - A mask of state machines in the neighbouring higher-numbered PIO block in the system (or PIO block 0 if this is the highest-numbered PIO block) to which to apply the operations specified by NEXTPREV_CLKDIV_RESTART, NEXTPREV_SM_ENABLE, and NEXTPREV_SM_DISABLE in the same write. - - This allows state machines in a neighbouring PIO block to be started/stopped/clock-synced exactly simultaneously with a write to this PIO block's CTRL register. - - Note that in a system with two PIOs, NEXT_PIO_MASK and PREV_PIO_MASK actually indicate the same PIO block. In this case the effects are applied cumulatively (as though the masks were OR'd together). - - Neighbouring PIO blocks are disconnected (status signals tied to 0 and control signals ignored) if one block is accessible to NonSecure code, and one is not. - [23:20] - write-only - - - PREV_PIO_MASK - A mask of state machines in the neighbouring lower-numbered PIO block in the system (or the highest-numbered PIO block if this is PIO block 0) to which to apply the operations specified by OP_CLKDIV_RESTART, OP_ENABLE, OP_DISABLE in the same write. - - This allows state machines in a neighbouring PIO block to be started/stopped/clock-synced exactly simultaneously with a write to this PIO block's CTRL register. - - Neighbouring PIO blocks are disconnected (status signals tied to 0 and control signals ignored) if one block is accessible to NonSecure code, and one is not. - [19:16] - write-only - - - CLKDIV_RESTART - Restart a state machine's clock divider from an initial phase of 0. Clock dividers are free-running, so once started, their output (including fractional jitter) is completely determined by the integer/fractional divisor configured in SMx_CLKDIV. This means that, if multiple clock dividers with the same divisor are restarted simultaneously, by writing multiple 1 bits to this field, the execution clocks of those state machines will run in precise lockstep. - - Note that setting/clearing SM_ENABLE does not stop the clock divider from running, so once multiple state machines' clocks are synchronised, it is safe to disable/reenable a state machine, whilst keeping the clock dividers in sync. - - Note also that CLKDIV_RESTART can be written to whilst the state machine is running, and this is useful to resynchronise clock dividers after the divisors (SMx_CLKDIV) have been changed on-the-fly. - [11:8] - write-only - - - SM_RESTART - Write 1 to instantly clear internal SM state which may be otherwise difficult to access and will affect future execution. - - Specifically, the following are cleared: input and output shift counters; the contents of the input shift register; the delay counter; the waiting-on-IRQ state; any stalled instruction written to SMx_INSTR or run by OUT/MOV EXEC; any pin write left asserted due to OUT_STICKY. - - The contents of the output shift register and the X/Y scratch registers are not affected. - [7:4] - write-only - - - SM_ENABLE - Enable/disable each of the four state machines by writing 1/0 to each of these four bits. When disabled, a state machine will cease executing instructions, except those written directly to SMx_INSTR by the system. Multiple bits can be set/cleared at once to run/halt multiple state machines simultaneously. - [3:0] - read-write - - - - - FSTAT - 0x00000004 - FIFO status register - 0x0f000f00 - - - TXEMPTY - State machine TX FIFO is empty - [27:24] - read-only - - - TXFULL - State machine TX FIFO is full - [19:16] - read-only - - - RXEMPTY - State machine RX FIFO is empty - [11:8] - read-only - - - RXFULL - State machine RX FIFO is full - [3:0] - read-only - - - - - FDEBUG - 0x00000008 - FIFO debug register - 0x00000000 - - - TXSTALL - State machine has stalled on empty TX FIFO during a blocking PULL, or an OUT with autopull enabled. Write 1 to clear. - [27:24] - read-write - oneToClear - - - TXOVER - TX FIFO overflow (i.e. write-on-full by the system) has occurred. Write 1 to clear. Note that write-on-full does not alter the state or contents of the FIFO in any way, but the data that the system attempted to write is dropped, so if this flag is set, your software has quite likely dropped some data on the floor. - [19:16] - read-write - oneToClear - - - RXUNDER - RX FIFO underflow (i.e. read-on-empty by the system) has occurred. Write 1 to clear. Note that read-on-empty does not perturb the state of the FIFO in any way, but the data returned by reading from an empty FIFO is undefined, so this flag generally only becomes set due to some kind of software error. - [11:8] - read-write - oneToClear - - - RXSTALL - State machine has stalled on full RX FIFO during a blocking PUSH, or an IN with autopush enabled. This flag is also set when a nonblocking PUSH to a full FIFO took place, in which case the state machine has dropped data. Write 1 to clear. - [3:0] - read-write - oneToClear - - - - - FLEVEL - 0x0000000c - FIFO levels - 0x00000000 - - - RX3 - [31:28] - read-only - - - TX3 - [27:24] - read-only - - - RX2 - [23:20] - read-only - - - TX2 - [19:16] - read-only - - - RX1 - [15:12] - read-only - - - TX1 - [11:8] - read-only - - - RX0 - [7:4] - read-only - - - TX0 - [3:0] - read-only - - - - - TXF0 - 0x00000010 - Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO. - 0x00000000 - - - TXF0 - [31:0] - write-only - - - - - TXF1 - 0x00000014 - Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO. - 0x00000000 - - - TXF1 - [31:0] - write-only - - - - - TXF2 - 0x00000018 - Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO. - 0x00000000 - - - TXF2 - [31:0] - write-only - - - - - TXF3 - 0x0000001c - Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO. - 0x00000000 - - - TXF3 - [31:0] - write-only - - - - - RXF0 - 0x00000020 - Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined. - 0x00000000 - - - RXF0 - [31:0] - read-only - modify - - - - - RXF1 - 0x00000024 - Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined. - 0x00000000 - - - RXF1 - [31:0] - read-only - modify - - - - - RXF2 - 0x00000028 - Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined. - 0x00000000 - - - RXF2 - [31:0] - read-only - modify - - - - - RXF3 - 0x0000002c - Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined. - 0x00000000 - - - RXF3 - [31:0] - read-only - modify - - - - - IRQ - 0x00000030 - State machine IRQ flags register. Write 1 to clear. There are eight state machine IRQ flags, which can be set, cleared, and waited on by the state machines. There's no fixed association between flags and state machines -- any state machine can use any flag. - - Any of the eight flags can be used for timing synchronisation between state machines, using IRQ and WAIT instructions. Any combination of the eight flags can also routed out to either of the two system-level interrupt requests, alongside FIFO status interrupts -- see e.g. IRQ0_INTE. - 0x00000000 - - - IRQ - [7:0] - read-write - oneToClear - - - - - IRQ_FORCE - 0x00000034 - Writing a 1 to each of these bits will forcibly assert the corresponding IRQ. Note this is different to the INTF register: writing here affects PIO internal state. INTF just asserts the processor-facing IRQ signal for testing ISRs, and is not visible to the state machines. - 0x00000000 - - - IRQ_FORCE - [7:0] - write-only - - - - - INPUT_SYNC_BYPASS - 0x00000038 - There is a 2-flipflop synchronizer on each GPIO input, which protects PIO logic from metastabilities. This increases input delay, and for fast synchronous IO (e.g. SPI) these synchronizers may need to be bypassed. Each bit in this register corresponds to one GPIO. - 0 -> input is synchronized (default) - 1 -> synchronizer is bypassed - If in doubt, leave this register as all zeroes. - 0x00000000 - - - INPUT_SYNC_BYPASS - [31:0] - read-write - - - - - DBG_PADOUT - 0x0000003c - Read to sample the pad output values PIO is currently driving to the GPIOs. On RP2040 there are 30 GPIOs, so the two most significant bits are hardwired to 0. - 0x00000000 - - - DBG_PADOUT - [31:0] - read-only - - - - - DBG_PADOE - 0x00000040 - Read to sample the pad output enables (direction) PIO is currently driving to the GPIOs. On RP2040 there are 30 GPIOs, so the two most significant bits are hardwired to 0. - 0x00000000 - - - DBG_PADOE - [31:0] - read-only - - - - - DBG_CFGINFO - 0x00000044 - The PIO hardware has some free parameters that may vary between chip products. - These should be provided in the chip datasheet, but are also exposed here. - 0x10000000 - - - VERSION - Version of the core PIO hardware. - [31:28] - read-only - - - v0 - 0 - Version 0 (RP2040) - - - v1 - 1 - Version 1 (RP2350) - - - - - IMEM_SIZE - The size of the instruction memory, measured in units of one instruction - [21:16] - read-only - - - SM_COUNT - The number of state machines this PIO instance is equipped with. - [11:8] - read-only - - - FIFO_DEPTH - The depth of the state machine TX/RX FIFOs, measured in words. - Joining fifos via SHIFTCTRL_FJOIN gives one FIFO with double - this depth. - [5:0] - read-only - - - - - INSTR_MEM0 - 0x00000048 - Write-only access to instruction memory location 0 - 0x00000000 - - - INSTR_MEM0 - [15:0] - write-only - - - - - INSTR_MEM1 - 0x0000004c - Write-only access to instruction memory location 1 - 0x00000000 - - - INSTR_MEM1 - [15:0] - write-only - - - - - INSTR_MEM2 - 0x00000050 - Write-only access to instruction memory location 2 - 0x00000000 - - - INSTR_MEM2 - [15:0] - write-only - - - - - INSTR_MEM3 - 0x00000054 - Write-only access to instruction memory location 3 - 0x00000000 - - - INSTR_MEM3 - [15:0] - write-only - - - - - INSTR_MEM4 - 0x00000058 - Write-only access to instruction memory location 4 - 0x00000000 - - - INSTR_MEM4 - [15:0] - write-only - - - - - INSTR_MEM5 - 0x0000005c - Write-only access to instruction memory location 5 - 0x00000000 - - - INSTR_MEM5 - [15:0] - write-only - - - - - INSTR_MEM6 - 0x00000060 - Write-only access to instruction memory location 6 - 0x00000000 - - - INSTR_MEM6 - [15:0] - write-only - - - - - INSTR_MEM7 - 0x00000064 - Write-only access to instruction memory location 7 - 0x00000000 - - - INSTR_MEM7 - [15:0] - write-only - - - - - INSTR_MEM8 - 0x00000068 - Write-only access to instruction memory location 8 - 0x00000000 - - - INSTR_MEM8 - [15:0] - write-only - - - - - INSTR_MEM9 - 0x0000006c - Write-only access to instruction memory location 9 - 0x00000000 - - - INSTR_MEM9 - [15:0] - write-only - - - - - INSTR_MEM10 - 0x00000070 - Write-only access to instruction memory location 10 - 0x00000000 - - - INSTR_MEM10 - [15:0] - write-only - - - - - INSTR_MEM11 - 0x00000074 - Write-only access to instruction memory location 11 - 0x00000000 - - - INSTR_MEM11 - [15:0] - write-only - - - - - INSTR_MEM12 - 0x00000078 - Write-only access to instruction memory location 12 - 0x00000000 - - - INSTR_MEM12 - [15:0] - write-only - - - - - INSTR_MEM13 - 0x0000007c - Write-only access to instruction memory location 13 - 0x00000000 - - - INSTR_MEM13 - [15:0] - write-only - - - - - INSTR_MEM14 - 0x00000080 - Write-only access to instruction memory location 14 - 0x00000000 - - - INSTR_MEM14 - [15:0] - write-only - - - - - INSTR_MEM15 - 0x00000084 - Write-only access to instruction memory location 15 - 0x00000000 - - - INSTR_MEM15 - [15:0] - write-only - - - - - INSTR_MEM16 - 0x00000088 - Write-only access to instruction memory location 16 - 0x00000000 - - - INSTR_MEM16 - [15:0] - write-only - - - - - INSTR_MEM17 - 0x0000008c - Write-only access to instruction memory location 17 - 0x00000000 - - - INSTR_MEM17 - [15:0] - write-only - - - - - INSTR_MEM18 - 0x00000090 - Write-only access to instruction memory location 18 - 0x00000000 - - - INSTR_MEM18 - [15:0] - write-only - - - - - INSTR_MEM19 - 0x00000094 - Write-only access to instruction memory location 19 - 0x00000000 - - - INSTR_MEM19 - [15:0] - write-only - - - - - INSTR_MEM20 - 0x00000098 - Write-only access to instruction memory location 20 - 0x00000000 - - - INSTR_MEM20 - [15:0] - write-only - - - - - INSTR_MEM21 - 0x0000009c - Write-only access to instruction memory location 21 - 0x00000000 - - - INSTR_MEM21 - [15:0] - write-only - - - - - INSTR_MEM22 - 0x000000a0 - Write-only access to instruction memory location 22 - 0x00000000 - - - INSTR_MEM22 - [15:0] - write-only - - - - - INSTR_MEM23 - 0x000000a4 - Write-only access to instruction memory location 23 - 0x00000000 - - - INSTR_MEM23 - [15:0] - write-only - - - - - INSTR_MEM24 - 0x000000a8 - Write-only access to instruction memory location 24 - 0x00000000 - - - INSTR_MEM24 - [15:0] - write-only - - - - - INSTR_MEM25 - 0x000000ac - Write-only access to instruction memory location 25 - 0x00000000 - - - INSTR_MEM25 - [15:0] - write-only - - - - - INSTR_MEM26 - 0x000000b0 - Write-only access to instruction memory location 26 - 0x00000000 - - - INSTR_MEM26 - [15:0] - write-only - - - - - INSTR_MEM27 - 0x000000b4 - Write-only access to instruction memory location 27 - 0x00000000 - - - INSTR_MEM27 - [15:0] - write-only - - - - - INSTR_MEM28 - 0x000000b8 - Write-only access to instruction memory location 28 - 0x00000000 - - - INSTR_MEM28 - [15:0] - write-only - - - - - INSTR_MEM29 - 0x000000bc - Write-only access to instruction memory location 29 - 0x00000000 - - - INSTR_MEM29 - [15:0] - write-only - - - - - INSTR_MEM30 - 0x000000c0 - Write-only access to instruction memory location 30 - 0x00000000 - - - INSTR_MEM30 - [15:0] - write-only - - - - - INSTR_MEM31 - 0x000000c4 - Write-only access to instruction memory location 31 - 0x00000000 - - - INSTR_MEM31 - [15:0] - write-only - - - - - SM0_CLKDIV - 0x000000c8 - Clock divisor register for state machine 0 - Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) - 0x00010000 - - - INT - Effective frequency is sysclk/(int + frac/256). - Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0. - [31:16] - read-write - - - FRAC - Fractional part of clock divisor - [15:8] - read-write - - - - - SM0_EXECCTRL - 0x000000cc - Execution/behavioural settings for state machine 0 - 0x0001f000 - - - EXEC_STALLED - If 1, an instruction written to SMx_INSTR is stalled, and latched by the state machine. Will clear to 0 once this instruction completes. - [31:31] - read-only - - - SIDE_EN - If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit. - [30:30] - read-write - - - SIDE_PINDIR - If 1, side-set data is asserted to pin directions, instead of pin values - [29:29] - read-write - - - JMP_PIN - The GPIO number to use as condition for JMP PIN. Unaffected by input mapping. - [28:24] - read-write - - - OUT_EN_SEL - Which data bit to use for inline OUT enable - [23:19] - read-write - - - INLINE_OUT_EN - If 1, use a bit of OUT data as an auxiliary write enable - When used in conjunction with OUT_STICKY, writes with an enable of 0 will - deassert the latest pin write. This can create useful masking/override behaviour - due to the priority ordering of state machine pin writes (SM0 < SM1 < ...) - [18:18] - read-write - - - OUT_STICKY - Continuously assert the most recent OUT/SET to the pins - [17:17] - read-write - - - WRAP_TOP - After reaching this address, execution is wrapped to wrap_bottom. - If the instruction is a jump, and the jump condition is true, the jump takes priority. - [16:12] - read-write - - - WRAP_BOTTOM - After reaching wrap_top, execution is wrapped to this address. - [11:7] - read-write - - - STATUS_SEL - Comparison used for the MOV x, STATUS instruction. - [6:5] - read-write - - - TXLEVEL - 0 - All-ones if TX FIFO level < N, otherwise all-zeroes - - - RXLEVEL - 1 - All-ones if RX FIFO level < N, otherwise all-zeroes - - - IRQ - 2 - All-ones if the indexed IRQ flag is raised, otherwise all-zeroes - - - - - STATUS_N - Comparison level or IRQ index for the MOV x, STATUS instruction. - - If STATUS_SEL is TXLEVEL or RXLEVEL, then values of STATUS_N greater than the current FIFO depth are reserved, and have undefined behaviour. - [4:0] - read-write - - - IRQ - 0 - Index 0-7 of an IRQ flag in this PIO block - - - IRQ_PREVPIO - 8 - Index 0-7 of an IRQ flag in the next lower-numbered PIO block - - - IRQ_NEXTPIO - 16 - Index 0-7 of an IRQ flag in the next higher-numbered PIO block - - - - - - - SM0_SHIFTCTRL - 0x000000d0 - Control behaviour of the input/output shift registers for state machine 0 - 0x000c0000 - - - FJOIN_RX - When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep. - TX FIFO is disabled as a result (always reads as both full and empty). - FIFOs are flushed when this bit is changed. - [31:31] - read-write - - - FJOIN_TX - When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep. - RX FIFO is disabled as a result (always reads as both full and empty). - FIFOs are flushed when this bit is changed. - [30:30] - read-write - - - PULL_THRESH - Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place. - Write 0 for value of 32. - [29:25] - read-write - - - PUSH_THRESH - Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place. - Write 0 for value of 32. - [24:20] - read-write - - - OUT_SHIFTDIR - 1 = shift out of output shift register to right. 0 = to left. - [19:19] - read-write - - - IN_SHIFTDIR - 1 = shift input shift register to right (data enters from left). 0 = to left. - [18:18] - read-write - - - AUTOPULL - Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH. - [17:17] - read-write - - - AUTOPUSH - Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH. - [16:16] - read-write - - - FJOIN_RX_PUT - If 1, disable this state machine's RX FIFO, make its storage available for random write access by the state machine (using the `put` instruction) and, unless FJOIN_RX_GET is also set, random read access by the processor (through the RXFx_PUTGETy registers). - - If FJOIN_RX_PUT and FJOIN_RX_GET are both set, then the RX FIFO's registers can be randomly read/written by the state machine, but are completely inaccessible to the processor. - - Setting this bit will clear the FJOIN_TX and FJOIN_RX bits. - [15:15] - read-write - - - FJOIN_RX_GET - If 1, disable this state machine's RX FIFO, make its storage available for random read access by the state machine (using the `get` instruction) and, unless FJOIN_RX_PUT is also set, random write access by the processor (through the RXFx_PUTGETy registers). - - If FJOIN_RX_PUT and FJOIN_RX_GET are both set, then the RX FIFO's registers can be randomly read/written by the state machine, but are completely inaccessible to the processor. - - Setting this bit will clear the FJOIN_TX and FJOIN_RX bits. - [14:14] - read-write - - - IN_COUNT - Set the number of pins which are not masked to 0 when read by an IN PINS, WAIT PIN or MOV x, PINS instruction. - - For example, an IN_COUNT of 5 means that the 5 LSBs of the IN pin group are visible (bits 4:0), but the remaining 27 MSBs are masked to 0. A count of 32 is encoded with a field value of 0, so the default behaviour is to not perform any masking. - - Note this masking is applied in addition to the masking usually performed by the IN instruction. This is mainly useful for the MOV x, PINS instruction, which otherwise has no way of masking pins. - [4:0] - read-write - - - - - SM0_ADDR - 0x000000d4 - Current instruction address of state machine 0 - 0x00000000 - - - SM0_ADDR - [4:0] - read-only - - - - - SM0_INSTR - 0x000000d8 - Read to see the instruction currently addressed by state machine 0's program counter - Write to execute an instruction immediately (including jumps) and then resume execution. - 0x00000000 - - - SM0_INSTR - [15:0] - read-write - - - - - SM0_PINCTRL - 0x000000dc - State machine pin control - 0x14000000 - - - SIDESET_COUNT - The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no delay). - [31:29] - read-write - - - SET_COUNT - The number of pins asserted by a SET. In the range 0 to 5 inclusive. - [28:26] - read-write - - - OUT_COUNT - The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive. - [25:20] - read-write - - - IN_BASE - The pin which is mapped to the least-significant bit of a state machine's IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits, with a modulo of 32 applied to pin number. - [19:15] - read-write - - - SIDESET_BASE - The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction's side-set/delay field (up to 5, determined by SIDESET_COUNT) are used for side-set data, with the remaining LSBs used for delay. The least-significant bit of the side-set portion is the bit written to this pin, with more-significant bits written to higher-numbered pins. - [14:10] - read-write - - - SET_BASE - The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data. - [9:5] - read-write - - - OUT_BASE - The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data. - [4:0] - read-write - - - - - SM1_CLKDIV - 0x000000e0 - Clock divisor register for state machine 1 - Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) - 0x00010000 - - - INT - Effective frequency is sysclk/(int + frac/256). - Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0. - [31:16] - read-write - - - FRAC - Fractional part of clock divisor - [15:8] - read-write - - - - - SM1_EXECCTRL - 0x000000e4 - Execution/behavioural settings for state machine 1 - 0x0001f000 - - - EXEC_STALLED - If 1, an instruction written to SMx_INSTR is stalled, and latched by the state machine. Will clear to 0 once this instruction completes. - [31:31] - read-only - - - SIDE_EN - If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit. - [30:30] - read-write - - - SIDE_PINDIR - If 1, side-set data is asserted to pin directions, instead of pin values - [29:29] - read-write - - - JMP_PIN - The GPIO number to use as condition for JMP PIN. Unaffected by input mapping. - [28:24] - read-write - - - OUT_EN_SEL - Which data bit to use for inline OUT enable - [23:19] - read-write - - - INLINE_OUT_EN - If 1, use a bit of OUT data as an auxiliary write enable - When used in conjunction with OUT_STICKY, writes with an enable of 0 will - deassert the latest pin write. This can create useful masking/override behaviour - due to the priority ordering of state machine pin writes (SM0 < SM1 < ...) - [18:18] - read-write - - - OUT_STICKY - Continuously assert the most recent OUT/SET to the pins - [17:17] - read-write - - - WRAP_TOP - After reaching this address, execution is wrapped to wrap_bottom. - If the instruction is a jump, and the jump condition is true, the jump takes priority. - [16:12] - read-write - - - WRAP_BOTTOM - After reaching wrap_top, execution is wrapped to this address. - [11:7] - read-write - - - STATUS_SEL - Comparison used for the MOV x, STATUS instruction. - [6:5] - read-write - - - TXLEVEL - 0 - All-ones if TX FIFO level < N, otherwise all-zeroes - - - RXLEVEL - 1 - All-ones if RX FIFO level < N, otherwise all-zeroes - - - IRQ - 2 - All-ones if the indexed IRQ flag is raised, otherwise all-zeroes - - - - - STATUS_N - Comparison level or IRQ index for the MOV x, STATUS instruction. - - If STATUS_SEL is TXLEVEL or RXLEVEL, then values of STATUS_N greater than the current FIFO depth are reserved, and have undefined behaviour. - [4:0] - read-write - - - IRQ - 0 - Index 0-7 of an IRQ flag in this PIO block - - - IRQ_PREVPIO - 8 - Index 0-7 of an IRQ flag in the next lower-numbered PIO block - - - IRQ_NEXTPIO - 16 - Index 0-7 of an IRQ flag in the next higher-numbered PIO block - - - - - - - SM1_SHIFTCTRL - 0x000000e8 - Control behaviour of the input/output shift registers for state machine 1 - 0x000c0000 - - - FJOIN_RX - When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep. - TX FIFO is disabled as a result (always reads as both full and empty). - FIFOs are flushed when this bit is changed. - [31:31] - read-write - - - FJOIN_TX - When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep. - RX FIFO is disabled as a result (always reads as both full and empty). - FIFOs are flushed when this bit is changed. - [30:30] - read-write - - - PULL_THRESH - Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place. - Write 0 for value of 32. - [29:25] - read-write - - - PUSH_THRESH - Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place. - Write 0 for value of 32. - [24:20] - read-write - - - OUT_SHIFTDIR - 1 = shift out of output shift register to right. 0 = to left. - [19:19] - read-write - - - IN_SHIFTDIR - 1 = shift input shift register to right (data enters from left). 0 = to left. - [18:18] - read-write - - - AUTOPULL - Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH. - [17:17] - read-write - - - AUTOPUSH - Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH. - [16:16] - read-write - - - FJOIN_RX_PUT - If 1, disable this state machine's RX FIFO, make its storage available for random write access by the state machine (using the `put` instruction) and, unless FJOIN_RX_GET is also set, random read access by the processor (through the RXFx_PUTGETy registers). - - If FJOIN_RX_PUT and FJOIN_RX_GET are both set, then the RX FIFO's registers can be randomly read/written by the state machine, but are completely inaccessible to the processor. - - Setting this bit will clear the FJOIN_TX and FJOIN_RX bits. - [15:15] - read-write - - - FJOIN_RX_GET - If 1, disable this state machine's RX FIFO, make its storage available for random read access by the state machine (using the `get` instruction) and, unless FJOIN_RX_PUT is also set, random write access by the processor (through the RXFx_PUTGETy registers). - - If FJOIN_RX_PUT and FJOIN_RX_GET are both set, then the RX FIFO's registers can be randomly read/written by the state machine, but are completely inaccessible to the processor. - - Setting this bit will clear the FJOIN_TX and FJOIN_RX bits. - [14:14] - read-write - - - IN_COUNT - Set the number of pins which are not masked to 0 when read by an IN PINS, WAIT PIN or MOV x, PINS instruction. - - For example, an IN_COUNT of 5 means that the 5 LSBs of the IN pin group are visible (bits 4:0), but the remaining 27 MSBs are masked to 0. A count of 32 is encoded with a field value of 0, so the default behaviour is to not perform any masking. - - Note this masking is applied in addition to the masking usually performed by the IN instruction. This is mainly useful for the MOV x, PINS instruction, which otherwise has no way of masking pins. - [4:0] - read-write - - - - - SM1_ADDR - 0x000000ec - Current instruction address of state machine 1 - 0x00000000 - - - SM1_ADDR - [4:0] - read-only - - - - - SM1_INSTR - 0x000000f0 - Read to see the instruction currently addressed by state machine 1's program counter - Write to execute an instruction immediately (including jumps) and then resume execution. - 0x00000000 - - - SM1_INSTR - [15:0] - read-write - - - - - SM1_PINCTRL - 0x000000f4 - State machine pin control - 0x14000000 - - - SIDESET_COUNT - The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no delay). - [31:29] - read-write - - - SET_COUNT - The number of pins asserted by a SET. In the range 0 to 5 inclusive. - [28:26] - read-write - - - OUT_COUNT - The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive. - [25:20] - read-write - - - IN_BASE - The pin which is mapped to the least-significant bit of a state machine's IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits, with a modulo of 32 applied to pin number. - [19:15] - read-write - - - SIDESET_BASE - The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction's side-set/delay field (up to 5, determined by SIDESET_COUNT) are used for side-set data, with the remaining LSBs used for delay. The least-significant bit of the side-set portion is the bit written to this pin, with more-significant bits written to higher-numbered pins. - [14:10] - read-write - - - SET_BASE - The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data. - [9:5] - read-write - - - OUT_BASE - The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data. - [4:0] - read-write - - - - - SM2_CLKDIV - 0x000000f8 - Clock divisor register for state machine 2 - Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) - 0x00010000 - - - INT - Effective frequency is sysclk/(int + frac/256). - Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0. - [31:16] - read-write - - - FRAC - Fractional part of clock divisor - [15:8] - read-write - - - - - SM2_EXECCTRL - 0x000000fc - Execution/behavioural settings for state machine 2 - 0x0001f000 - - - EXEC_STALLED - If 1, an instruction written to SMx_INSTR is stalled, and latched by the state machine. Will clear to 0 once this instruction completes. - [31:31] - read-only - - - SIDE_EN - If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit. - [30:30] - read-write - - - SIDE_PINDIR - If 1, side-set data is asserted to pin directions, instead of pin values - [29:29] - read-write - - - JMP_PIN - The GPIO number to use as condition for JMP PIN. Unaffected by input mapping. - [28:24] - read-write - - - OUT_EN_SEL - Which data bit to use for inline OUT enable - [23:19] - read-write - - - INLINE_OUT_EN - If 1, use a bit of OUT data as an auxiliary write enable - When used in conjunction with OUT_STICKY, writes with an enable of 0 will - deassert the latest pin write. This can create useful masking/override behaviour - due to the priority ordering of state machine pin writes (SM0 < SM1 < ...) - [18:18] - read-write - - - OUT_STICKY - Continuously assert the most recent OUT/SET to the pins - [17:17] - read-write - - - WRAP_TOP - After reaching this address, execution is wrapped to wrap_bottom. - If the instruction is a jump, and the jump condition is true, the jump takes priority. - [16:12] - read-write - - - WRAP_BOTTOM - After reaching wrap_top, execution is wrapped to this address. - [11:7] - read-write - - - STATUS_SEL - Comparison used for the MOV x, STATUS instruction. - [6:5] - read-write - - - TXLEVEL - 0 - All-ones if TX FIFO level < N, otherwise all-zeroes - - - RXLEVEL - 1 - All-ones if RX FIFO level < N, otherwise all-zeroes - - - IRQ - 2 - All-ones if the indexed IRQ flag is raised, otherwise all-zeroes - - - - - STATUS_N - Comparison level or IRQ index for the MOV x, STATUS instruction. - - If STATUS_SEL is TXLEVEL or RXLEVEL, then values of STATUS_N greater than the current FIFO depth are reserved, and have undefined behaviour. - [4:0] - read-write - - - IRQ - 0 - Index 0-7 of an IRQ flag in this PIO block - - - IRQ_PREVPIO - 8 - Index 0-7 of an IRQ flag in the next lower-numbered PIO block - - - IRQ_NEXTPIO - 16 - Index 0-7 of an IRQ flag in the next higher-numbered PIO block - - - - - - - SM2_SHIFTCTRL - 0x00000100 - Control behaviour of the input/output shift registers for state machine 2 - 0x000c0000 - - - FJOIN_RX - When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep. - TX FIFO is disabled as a result (always reads as both full and empty). - FIFOs are flushed when this bit is changed. - [31:31] - read-write - - - FJOIN_TX - When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep. - RX FIFO is disabled as a result (always reads as both full and empty). - FIFOs are flushed when this bit is changed. - [30:30] - read-write - - - PULL_THRESH - Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place. - Write 0 for value of 32. - [29:25] - read-write - - - PUSH_THRESH - Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place. - Write 0 for value of 32. - [24:20] - read-write - - - OUT_SHIFTDIR - 1 = shift out of output shift register to right. 0 = to left. - [19:19] - read-write - - - IN_SHIFTDIR - 1 = shift input shift register to right (data enters from left). 0 = to left. - [18:18] - read-write - - - AUTOPULL - Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH. - [17:17] - read-write - - - AUTOPUSH - Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH. - [16:16] - read-write - - - FJOIN_RX_PUT - If 1, disable this state machine's RX FIFO, make its storage available for random write access by the state machine (using the `put` instruction) and, unless FJOIN_RX_GET is also set, random read access by the processor (through the RXFx_PUTGETy registers). - - If FJOIN_RX_PUT and FJOIN_RX_GET are both set, then the RX FIFO's registers can be randomly read/written by the state machine, but are completely inaccessible to the processor. - - Setting this bit will clear the FJOIN_TX and FJOIN_RX bits. - [15:15] - read-write - - - FJOIN_RX_GET - If 1, disable this state machine's RX FIFO, make its storage available for random read access by the state machine (using the `get` instruction) and, unless FJOIN_RX_PUT is also set, random write access by the processor (through the RXFx_PUTGETy registers). - - If FJOIN_RX_PUT and FJOIN_RX_GET are both set, then the RX FIFO's registers can be randomly read/written by the state machine, but are completely inaccessible to the processor. - - Setting this bit will clear the FJOIN_TX and FJOIN_RX bits. - [14:14] - read-write - - - IN_COUNT - Set the number of pins which are not masked to 0 when read by an IN PINS, WAIT PIN or MOV x, PINS instruction. - - For example, an IN_COUNT of 5 means that the 5 LSBs of the IN pin group are visible (bits 4:0), but the remaining 27 MSBs are masked to 0. A count of 32 is encoded with a field value of 0, so the default behaviour is to not perform any masking. - - Note this masking is applied in addition to the masking usually performed by the IN instruction. This is mainly useful for the MOV x, PINS instruction, which otherwise has no way of masking pins. - [4:0] - read-write - - - - - SM2_ADDR - 0x00000104 - Current instruction address of state machine 2 - 0x00000000 - - - SM2_ADDR - [4:0] - read-only - - - - - SM2_INSTR - 0x00000108 - Read to see the instruction currently addressed by state machine 2's program counter - Write to execute an instruction immediately (including jumps) and then resume execution. - 0x00000000 - - - SM2_INSTR - [15:0] - read-write - - - - - SM2_PINCTRL - 0x0000010c - State machine pin control - 0x14000000 - - - SIDESET_COUNT - The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no delay). - [31:29] - read-write - - - SET_COUNT - The number of pins asserted by a SET. In the range 0 to 5 inclusive. - [28:26] - read-write - - - OUT_COUNT - The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive. - [25:20] - read-write - - - IN_BASE - The pin which is mapped to the least-significant bit of a state machine's IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits, with a modulo of 32 applied to pin number. - [19:15] - read-write - - - SIDESET_BASE - The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction's side-set/delay field (up to 5, determined by SIDESET_COUNT) are used for side-set data, with the remaining LSBs used for delay. The least-significant bit of the side-set portion is the bit written to this pin, with more-significant bits written to higher-numbered pins. - [14:10] - read-write - - - SET_BASE - The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data. - [9:5] - read-write - - - OUT_BASE - The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data. - [4:0] - read-write - - - - - SM3_CLKDIV - 0x00000110 - Clock divisor register for state machine 3 - Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) - 0x00010000 - - - INT - Effective frequency is sysclk/(int + frac/256). - Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0. - [31:16] - read-write - - - FRAC - Fractional part of clock divisor - [15:8] - read-write - - - - - SM3_EXECCTRL - 0x00000114 - Execution/behavioural settings for state machine 3 - 0x0001f000 - - - EXEC_STALLED - If 1, an instruction written to SMx_INSTR is stalled, and latched by the state machine. Will clear to 0 once this instruction completes. - [31:31] - read-only - - - SIDE_EN - If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit. - [30:30] - read-write - - - SIDE_PINDIR - If 1, side-set data is asserted to pin directions, instead of pin values - [29:29] - read-write - - - JMP_PIN - The GPIO number to use as condition for JMP PIN. Unaffected by input mapping. - [28:24] - read-write - - - OUT_EN_SEL - Which data bit to use for inline OUT enable - [23:19] - read-write - - - INLINE_OUT_EN - If 1, use a bit of OUT data as an auxiliary write enable - When used in conjunction with OUT_STICKY, writes with an enable of 0 will - deassert the latest pin write. This can create useful masking/override behaviour - due to the priority ordering of state machine pin writes (SM0 < SM1 < ...) - [18:18] - read-write - - - OUT_STICKY - Continuously assert the most recent OUT/SET to the pins - [17:17] - read-write - - - WRAP_TOP - After reaching this address, execution is wrapped to wrap_bottom. - If the instruction is a jump, and the jump condition is true, the jump takes priority. - [16:12] - read-write - - - WRAP_BOTTOM - After reaching wrap_top, execution is wrapped to this address. - [11:7] - read-write - - - STATUS_SEL - Comparison used for the MOV x, STATUS instruction. - [6:5] - read-write - - - TXLEVEL - 0 - All-ones if TX FIFO level < N, otherwise all-zeroes - - - RXLEVEL - 1 - All-ones if RX FIFO level < N, otherwise all-zeroes - - - IRQ - 2 - All-ones if the indexed IRQ flag is raised, otherwise all-zeroes - - - - - STATUS_N - Comparison level or IRQ index for the MOV x, STATUS instruction. - - If STATUS_SEL is TXLEVEL or RXLEVEL, then values of STATUS_N greater than the current FIFO depth are reserved, and have undefined behaviour. - [4:0] - read-write - - - IRQ - 0 - Index 0-7 of an IRQ flag in this PIO block - - - IRQ_PREVPIO - 8 - Index 0-7 of an IRQ flag in the next lower-numbered PIO block - - - IRQ_NEXTPIO - 16 - Index 0-7 of an IRQ flag in the next higher-numbered PIO block - - - - - - - SM3_SHIFTCTRL - 0x00000118 - Control behaviour of the input/output shift registers for state machine 3 - 0x000c0000 - - - FJOIN_RX - When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep. - TX FIFO is disabled as a result (always reads as both full and empty). - FIFOs are flushed when this bit is changed. - [31:31] - read-write - - - FJOIN_TX - When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep. - RX FIFO is disabled as a result (always reads as both full and empty). - FIFOs are flushed when this bit is changed. - [30:30] - read-write - - - PULL_THRESH - Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place. - Write 0 for value of 32. - [29:25] - read-write - - - PUSH_THRESH - Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place. - Write 0 for value of 32. - [24:20] - read-write - - - OUT_SHIFTDIR - 1 = shift out of output shift register to right. 0 = to left. - [19:19] - read-write - - - IN_SHIFTDIR - 1 = shift input shift register to right (data enters from left). 0 = to left. - [18:18] - read-write - - - AUTOPULL - Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH. - [17:17] - read-write - - - AUTOPUSH - Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH. - [16:16] - read-write - - - FJOIN_RX_PUT - If 1, disable this state machine's RX FIFO, make its storage available for random write access by the state machine (using the `put` instruction) and, unless FJOIN_RX_GET is also set, random read access by the processor (through the RXFx_PUTGETy registers). - - If FJOIN_RX_PUT and FJOIN_RX_GET are both set, then the RX FIFO's registers can be randomly read/written by the state machine, but are completely inaccessible to the processor. - - Setting this bit will clear the FJOIN_TX and FJOIN_RX bits. - [15:15] - read-write - - - FJOIN_RX_GET - If 1, disable this state machine's RX FIFO, make its storage available for random read access by the state machine (using the `get` instruction) and, unless FJOIN_RX_PUT is also set, random write access by the processor (through the RXFx_PUTGETy registers). - - If FJOIN_RX_PUT and FJOIN_RX_GET are both set, then the RX FIFO's registers can be randomly read/written by the state machine, but are completely inaccessible to the processor. - - Setting this bit will clear the FJOIN_TX and FJOIN_RX bits. - [14:14] - read-write - - - IN_COUNT - Set the number of pins which are not masked to 0 when read by an IN PINS, WAIT PIN or MOV x, PINS instruction. - - For example, an IN_COUNT of 5 means that the 5 LSBs of the IN pin group are visible (bits 4:0), but the remaining 27 MSBs are masked to 0. A count of 32 is encoded with a field value of 0, so the default behaviour is to not perform any masking. - - Note this masking is applied in addition to the masking usually performed by the IN instruction. This is mainly useful for the MOV x, PINS instruction, which otherwise has no way of masking pins. - [4:0] - read-write - - - - - SM3_ADDR - 0x0000011c - Current instruction address of state machine 3 - 0x00000000 - - - SM3_ADDR - [4:0] - read-only - - - - - SM3_INSTR - 0x00000120 - Read to see the instruction currently addressed by state machine 3's program counter - Write to execute an instruction immediately (including jumps) and then resume execution. - 0x00000000 - - - SM3_INSTR - [15:0] - read-write - - - - - SM3_PINCTRL - 0x00000124 - State machine pin control - 0x14000000 - - - SIDESET_COUNT - The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no delay). - [31:29] - read-write - - - SET_COUNT - The number of pins asserted by a SET. In the range 0 to 5 inclusive. - [28:26] - read-write - - - OUT_COUNT - The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive. - [25:20] - read-write - - - IN_BASE - The pin which is mapped to the least-significant bit of a state machine's IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits, with a modulo of 32 applied to pin number. - [19:15] - read-write - - - SIDESET_BASE - The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction's side-set/delay field (up to 5, determined by SIDESET_COUNT) are used for side-set data, with the remaining LSBs used for delay. The least-significant bit of the side-set portion is the bit written to this pin, with more-significant bits written to higher-numbered pins. - [14:10] - read-write - - - SET_BASE - The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data. - [9:5] - read-write - - - OUT_BASE - The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data. - [4:0] - read-write - - - - - RXF0_PUTGET0 - 0x00000128 - Direct read/write access to entry 0 of SM0's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. - 0x00000000 - - - RXF0_PUTGET0 - [31:0] - read-write - - - - - RXF0_PUTGET1 - 0x0000012c - Direct read/write access to entry 1 of SM0's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. - 0x00000000 - - - RXF0_PUTGET1 - [31:0] - read-write - - - - - RXF0_PUTGET2 - 0x00000130 - Direct read/write access to entry 2 of SM0's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. - 0x00000000 - - - RXF0_PUTGET2 - [31:0] - read-write - - - - - RXF0_PUTGET3 - 0x00000134 - Direct read/write access to entry 3 of SM0's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. - 0x00000000 - - - RXF0_PUTGET3 - [31:0] - read-write - - - - - RXF1_PUTGET0 - 0x00000138 - Direct read/write access to entry 0 of SM1's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. - 0x00000000 - - - RXF1_PUTGET0 - [31:0] - read-write - - - - - RXF1_PUTGET1 - 0x0000013c - Direct read/write access to entry 1 of SM1's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. - 0x00000000 - - - RXF1_PUTGET1 - [31:0] - read-write - - - - - RXF1_PUTGET2 - 0x00000140 - Direct read/write access to entry 2 of SM1's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. - 0x00000000 - - - RXF1_PUTGET2 - [31:0] - read-write - - - - - RXF1_PUTGET3 - 0x00000144 - Direct read/write access to entry 3 of SM1's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. - 0x00000000 - - - RXF1_PUTGET3 - [31:0] - read-write - - - - - RXF2_PUTGET0 - 0x00000148 - Direct read/write access to entry 0 of SM2's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. - 0x00000000 - - - RXF2_PUTGET0 - [31:0] - read-write - - - - - RXF2_PUTGET1 - 0x0000014c - Direct read/write access to entry 1 of SM2's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. - 0x00000000 - - - RXF2_PUTGET1 - [31:0] - read-write - - - - - RXF2_PUTGET2 - 0x00000150 - Direct read/write access to entry 2 of SM2's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. - 0x00000000 - - - RXF2_PUTGET2 - [31:0] - read-write - - - - - RXF2_PUTGET3 - 0x00000154 - Direct read/write access to entry 3 of SM2's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. - 0x00000000 - - - RXF2_PUTGET3 - [31:0] - read-write - - - - - RXF3_PUTGET0 - 0x00000158 - Direct read/write access to entry 0 of SM3's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. - 0x00000000 - - - RXF3_PUTGET0 - [31:0] - read-write - - - - - RXF3_PUTGET1 - 0x0000015c - Direct read/write access to entry 1 of SM3's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. - 0x00000000 - - - RXF3_PUTGET1 - [31:0] - read-write - - - - - RXF3_PUTGET2 - 0x00000160 - Direct read/write access to entry 2 of SM3's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. - 0x00000000 - - - RXF3_PUTGET2 - [31:0] - read-write - - - - - RXF3_PUTGET3 - 0x00000164 - Direct read/write access to entry 3 of SM3's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. - 0x00000000 - - - RXF3_PUTGET3 - [31:0] - read-write - - - - - GPIOBASE - 0x00000168 - Relocate GPIO 0 (from PIO's point of view) in the system GPIO numbering, to access more than 32 GPIOs from PIO. - - Only the values 0 and 16 are supported (only bit 4 is writable). - 0x00000000 - - - GPIOBASE - [4:4] - read-write - - - - - INTR - 0x0000016c - Raw Interrupts - 0x00000000 - - - SM7 - [15:15] - read-only - - - SM6 - [14:14] - read-only - - - SM5 - [13:13] - read-only - - - SM4 - [12:12] - read-only - - - SM3 - [11:11] - read-only - - - SM2 - [10:10] - read-only - - - SM1 - [9:9] - read-only - - - SM0 - [8:8] - read-only - - - SM3_TXNFULL - [7:7] - read-only - - - SM2_TXNFULL - [6:6] - read-only - - - SM1_TXNFULL - [5:5] - read-only - - - SM0_TXNFULL - [4:4] - read-only - - - SM3_RXNEMPTY - [3:3] - read-only - - - SM2_RXNEMPTY - [2:2] - read-only - - - SM1_RXNEMPTY - [1:1] - read-only - - - SM0_RXNEMPTY - [0:0] - read-only - - - - - IRQ0_INTE - 0x00000170 - Interrupt Enable for irq0 - 0x00000000 - - - SM7 - [15:15] - read-write - - - SM6 - [14:14] - read-write - - - SM5 - [13:13] - read-write - - - SM4 - [12:12] - read-write - - - SM3 - [11:11] - read-write - - - SM2 - [10:10] - read-write - - - SM1 - [9:9] - read-write - - - SM0 - [8:8] - read-write - - - SM3_TXNFULL - [7:7] - read-write - - - SM2_TXNFULL - [6:6] - read-write - - - SM1_TXNFULL - [5:5] - read-write - - - SM0_TXNFULL - [4:4] - read-write - - - SM3_RXNEMPTY - [3:3] - read-write - - - SM2_RXNEMPTY - [2:2] - read-write - - - SM1_RXNEMPTY - [1:1] - read-write - - - SM0_RXNEMPTY - [0:0] - read-write - - - - - IRQ0_INTF - 0x00000174 - Interrupt Force for irq0 - 0x00000000 - - - SM7 - [15:15] - read-write - - - SM6 - [14:14] - read-write - - - SM5 - [13:13] - read-write - - - SM4 - [12:12] - read-write - - - SM3 - [11:11] - read-write - - - SM2 - [10:10] - read-write - - - SM1 - [9:9] - read-write - - - SM0 - [8:8] - read-write - - - SM3_TXNFULL - [7:7] - read-write - - - SM2_TXNFULL - [6:6] - read-write - - - SM1_TXNFULL - [5:5] - read-write - - - SM0_TXNFULL - [4:4] - read-write - - - SM3_RXNEMPTY - [3:3] - read-write - - - SM2_RXNEMPTY - [2:2] - read-write - - - SM1_RXNEMPTY - [1:1] - read-write - - - SM0_RXNEMPTY - [0:0] - read-write - - - - - IRQ0_INTS - 0x00000178 - Interrupt status after masking & forcing for irq0 - 0x00000000 - - - SM7 - [15:15] - read-only - - - SM6 - [14:14] - read-only - - - SM5 - [13:13] - read-only - - - SM4 - [12:12] - read-only - - - SM3 - [11:11] - read-only - - - SM2 - [10:10] - read-only - - - SM1 - [9:9] - read-only - - - SM0 - [8:8] - read-only - - - SM3_TXNFULL - [7:7] - read-only - - - SM2_TXNFULL - [6:6] - read-only - - - SM1_TXNFULL - [5:5] - read-only - - - SM0_TXNFULL - [4:4] - read-only - - - SM3_RXNEMPTY - [3:3] - read-only - - - SM2_RXNEMPTY - [2:2] - read-only - - - SM1_RXNEMPTY - [1:1] - read-only - - - SM0_RXNEMPTY - [0:0] - read-only - - - - - IRQ1_INTE - 0x0000017c - Interrupt Enable for irq1 - 0x00000000 - - - SM7 - [15:15] - read-write - - - SM6 - [14:14] - read-write - - - SM5 - [13:13] - read-write - - - SM4 - [12:12] - read-write - - - SM3 - [11:11] - read-write - - - SM2 - [10:10] - read-write - - - SM1 - [9:9] - read-write - - - SM0 - [8:8] - read-write - - - SM3_TXNFULL - [7:7] - read-write - - - SM2_TXNFULL - [6:6] - read-write - - - SM1_TXNFULL - [5:5] - read-write - - - SM0_TXNFULL - [4:4] - read-write - - - SM3_RXNEMPTY - [3:3] - read-write - - - SM2_RXNEMPTY - [2:2] - read-write - - - SM1_RXNEMPTY - [1:1] - read-write - - - SM0_RXNEMPTY - [0:0] - read-write - - - - - IRQ1_INTF - 0x00000180 - Interrupt Force for irq1 - 0x00000000 - - - SM7 - [15:15] - read-write - - - SM6 - [14:14] - read-write - - - SM5 - [13:13] - read-write - - - SM4 - [12:12] - read-write - - - SM3 - [11:11] - read-write - - - SM2 - [10:10] - read-write - - - SM1 - [9:9] - read-write - - - SM0 - [8:8] - read-write - - - SM3_TXNFULL - [7:7] - read-write - - - SM2_TXNFULL - [6:6] - read-write - - - SM1_TXNFULL - [5:5] - read-write - - - SM0_TXNFULL - [4:4] - read-write - - - SM3_RXNEMPTY - [3:3] - read-write - - - SM2_RXNEMPTY - [2:2] - read-write - - - SM1_RXNEMPTY - [1:1] - read-write - - - SM0_RXNEMPTY - [0:0] - read-write - - - - - IRQ1_INTS - 0x00000184 - Interrupt status after masking & forcing for irq1 - 0x00000000 - - - SM7 - [15:15] - read-only - - - SM6 - [14:14] - read-only - - - SM5 - [13:13] - read-only - - - SM4 - [12:12] - read-only - - - SM3 - [11:11] - read-only - - - SM2 - [10:10] - read-only - - - SM1 - [9:9] - read-only - - - SM0 - [8:8] - read-only - - - SM3_TXNFULL - [7:7] - read-only - - - SM2_TXNFULL - [6:6] - read-only - - - SM1_TXNFULL - [5:5] - read-only - - - SM0_TXNFULL - [4:4] - read-only - - - SM3_RXNEMPTY - [3:3] - read-only - - - SM2_RXNEMPTY - [2:2] - read-only - - - SM1_RXNEMPTY - [1:1] - read-only - - - SM0_RXNEMPTY - [0:0] - read-only - - - - - - - PIO1 - 0x50300000 - - PIO1_IRQ_0 - 17 - - - PIO1_IRQ_1 - 18 - - - - PIO2 - 0x50400000 - - PIO2_IRQ_0 - 19 - - - PIO2_IRQ_1 - 20 - - - - BUSCTRL - Register block for busfabric control signals and performance counters - 0x40068000 - - 0 - 44 - registers - - - - BUS_PRIORITY - 0x00000000 - Set the priority of each master for bus arbitration. - 0x00000000 - - - DMA_W - 0 - low priority, 1 - high priority - [12:12] - read-write - - - DMA_R - 0 - low priority, 1 - high priority - [8:8] - read-write - - - PROC1 - 0 - low priority, 1 - high priority - [4:4] - read-write - - - PROC0 - 0 - low priority, 1 - high priority - [0:0] - read-write - - - - - BUS_PRIORITY_ACK - 0x00000004 - Bus priority acknowledge - 0x00000000 - - - BUS_PRIORITY_ACK - Goes to 1 once all arbiters have registered the new global priority levels. - Arbiters update their local priority when servicing a new nonsequential access. - In normal circumstances this will happen almost immediately. - [0:0] - read-only - - - - - PERFCTR_EN - 0x00000008 - Enable the performance counters. If 0, the performance counters do not increment. This can be used to precisely start/stop event sampling around the profiled section of code. - - The performance counters are initially disabled, to save energy. - 0x00000000 - - - PERFCTR_EN - [0:0] - read-write - - - - - PERFCTR0 - 0x0000000c - Bus fabric performance counter 0 - 0x00000000 - - - PERFCTR0 - Busfabric saturating performance counter 0 - Count some event signal from the busfabric arbiters, if PERFCTR_EN is set. - Write any value to clear. Select an event to count using PERFSEL0 - [23:0] - read-write - oneToClear - - - - - PERFSEL0 - 0x00000010 - Bus fabric performance event select for PERFCTR0 - 0x0000001f - - - PERFSEL0 - Select an event for PERFCTR0. For each downstream port of the main crossbar, four events are available: ACCESS, an access took place; ACCESS_CONTESTED, an access took place that previously stalled due to contention from other masters; STALL_DOWNSTREAM, count cycles where any master stalled due to a stall on the downstream bus; STALL_UPSTREAM, count cycles where any master stalled for any reason, including contention from other masters. - [6:0] - read-write - - - siob_proc1_stall_upstream - 0 - - - siob_proc1_stall_downstream - 1 - - - siob_proc1_access_contested - 2 - - - siob_proc1_access - 3 - - - siob_proc0_stall_upstream - 4 - - - siob_proc0_stall_downstream - 5 - - - siob_proc0_access_contested - 6 - - - siob_proc0_access - 7 - - - apb_stall_upstream - 8 - - - apb_stall_downstream - 9 - - - apb_access_contested - 10 - - - apb_access - 11 - - - fastperi_stall_upstream - 12 - - - fastperi_stall_downstream - 13 - - - fastperi_access_contested - 14 - - - fastperi_access - 15 - - - sram9_stall_upstream - 16 - - - sram9_stall_downstream - 17 - - - sram9_access_contested - 18 - - - sram9_access - 19 - - - sram8_stall_upstream - 20 - - - sram8_stall_downstream - 21 - - - sram8_access_contested - 22 - - - sram8_access - 23 - - - sram7_stall_upstream - 24 - - - sram7_stall_downstream - 25 - - - sram7_access_contested - 26 - - - sram7_access - 27 - - - sram6_stall_upstream - 28 - - - sram6_stall_downstream - 29 - - - sram6_access_contested - 30 - - - sram6_access - 31 - - - sram5_stall_upstream - 32 - - - sram5_stall_downstream - 33 - - - sram5_access_contested - 34 - - - sram5_access - 35 - - - sram4_stall_upstream - 36 - - - sram4_stall_downstream - 37 - - - sram4_access_contested - 38 - - - sram4_access - 39 - - - sram3_stall_upstream - 40 - - - sram3_stall_downstream - 41 - - - sram3_access_contested - 42 - - - sram3_access - 43 - - - sram2_stall_upstream - 44 - - - sram2_stall_downstream - 45 - - - sram2_access_contested - 46 - - - sram2_access - 47 - - - sram1_stall_upstream - 48 - - - sram1_stall_downstream - 49 - - - sram1_access_contested - 50 - - - sram1_access - 51 - - - sram0_stall_upstream - 52 - - - sram0_stall_downstream - 53 - - - sram0_access_contested - 54 - - - sram0_access - 55 - - - xip_main1_stall_upstream - 56 - - - xip_main1_stall_downstream - 57 - - - xip_main1_access_contested - 58 - - - xip_main1_access - 59 - - - xip_main0_stall_upstream - 60 - - - xip_main0_stall_downstream - 61 - - - xip_main0_access_contested - 62 - - - xip_main0_access - 63 - - - rom_stall_upstream - 64 - - - rom_stall_downstream - 65 - - - rom_access_contested - 66 - - - rom_access - 67 - - - - - - - PERFCTR1 - 0x00000014 - Bus fabric performance counter 1 - 0x00000000 - - - PERFCTR1 - Busfabric saturating performance counter 1 - Count some event signal from the busfabric arbiters, if PERFCTR_EN is set. - Write any value to clear. Select an event to count using PERFSEL1 - [23:0] - read-write - oneToClear - - - - - PERFSEL1 - 0x00000018 - Bus fabric performance event select for PERFCTR1 - 0x0000001f - - - PERFSEL1 - Select an event for PERFCTR1. For each downstream port of the main crossbar, four events are available: ACCESS, an access took place; ACCESS_CONTESTED, an access took place that previously stalled due to contention from other masters; STALL_DOWNSTREAM, count cycles where any master stalled due to a stall on the downstream bus; STALL_UPSTREAM, count cycles where any master stalled for any reason, including contention from other masters. - [6:0] - read-write - - - siob_proc1_stall_upstream - 0 - - - siob_proc1_stall_downstream - 1 - - - siob_proc1_access_contested - 2 - - - siob_proc1_access - 3 - - - siob_proc0_stall_upstream - 4 - - - siob_proc0_stall_downstream - 5 - - - siob_proc0_access_contested - 6 - - - siob_proc0_access - 7 - - - apb_stall_upstream - 8 - - - apb_stall_downstream - 9 - - - apb_access_contested - 10 - - - apb_access - 11 - - - fastperi_stall_upstream - 12 - - - fastperi_stall_downstream - 13 - - - fastperi_access_contested - 14 - - - fastperi_access - 15 - - - sram9_stall_upstream - 16 - - - sram9_stall_downstream - 17 - - - sram9_access_contested - 18 - - - sram9_access - 19 - - - sram8_stall_upstream - 20 - - - sram8_stall_downstream - 21 - - - sram8_access_contested - 22 - - - sram8_access - 23 - - - sram7_stall_upstream - 24 - - - sram7_stall_downstream - 25 - - - sram7_access_contested - 26 - - - sram7_access - 27 - - - sram6_stall_upstream - 28 - - - sram6_stall_downstream - 29 - - - sram6_access_contested - 30 - - - sram6_access - 31 - - - sram5_stall_upstream - 32 - - - sram5_stall_downstream - 33 - - - sram5_access_contested - 34 - - - sram5_access - 35 - - - sram4_stall_upstream - 36 - - - sram4_stall_downstream - 37 - - - sram4_access_contested - 38 - - - sram4_access - 39 - - - sram3_stall_upstream - 40 - - - sram3_stall_downstream - 41 - - - sram3_access_contested - 42 - - - sram3_access - 43 - - - sram2_stall_upstream - 44 - - - sram2_stall_downstream - 45 - - - sram2_access_contested - 46 - - - sram2_access - 47 - - - sram1_stall_upstream - 48 - - - sram1_stall_downstream - 49 - - - sram1_access_contested - 50 - - - sram1_access - 51 - - - sram0_stall_upstream - 52 - - - sram0_stall_downstream - 53 - - - sram0_access_contested - 54 - - - sram0_access - 55 - - - xip_main1_stall_upstream - 56 - - - xip_main1_stall_downstream - 57 - - - xip_main1_access_contested - 58 - - - xip_main1_access - 59 - - - xip_main0_stall_upstream - 60 - - - xip_main0_stall_downstream - 61 - - - xip_main0_access_contested - 62 - - - xip_main0_access - 63 - - - rom_stall_upstream - 64 - - - rom_stall_downstream - 65 - - - rom_access_contested - 66 - - - rom_access - 67 - - - - - - - PERFCTR2 - 0x0000001c - Bus fabric performance counter 2 - 0x00000000 - - - PERFCTR2 - Busfabric saturating performance counter 2 - Count some event signal from the busfabric arbiters, if PERFCTR_EN is set. - Write any value to clear. Select an event to count using PERFSEL2 - [23:0] - read-write - oneToClear - - - - - PERFSEL2 - 0x00000020 - Bus fabric performance event select for PERFCTR2 - 0x0000001f - - - PERFSEL2 - Select an event for PERFCTR2. For each downstream port of the main crossbar, four events are available: ACCESS, an access took place; ACCESS_CONTESTED, an access took place that previously stalled due to contention from other masters; STALL_DOWNSTREAM, count cycles where any master stalled due to a stall on the downstream bus; STALL_UPSTREAM, count cycles where any master stalled for any reason, including contention from other masters. - [6:0] - read-write - - - siob_proc1_stall_upstream - 0 - - - siob_proc1_stall_downstream - 1 - - - siob_proc1_access_contested - 2 - - - siob_proc1_access - 3 - - - siob_proc0_stall_upstream - 4 - - - siob_proc0_stall_downstream - 5 - - - siob_proc0_access_contested - 6 - - - siob_proc0_access - 7 - - - apb_stall_upstream - 8 - - - apb_stall_downstream - 9 - - - apb_access_contested - 10 - - - apb_access - 11 - - - fastperi_stall_upstream - 12 - - - fastperi_stall_downstream - 13 - - - fastperi_access_contested - 14 - - - fastperi_access - 15 - - - sram9_stall_upstream - 16 - - - sram9_stall_downstream - 17 - - - sram9_access_contested - 18 - - - sram9_access - 19 - - - sram8_stall_upstream - 20 - - - sram8_stall_downstream - 21 - - - sram8_access_contested - 22 - - - sram8_access - 23 - - - sram7_stall_upstream - 24 - - - sram7_stall_downstream - 25 - - - sram7_access_contested - 26 - - - sram7_access - 27 - - - sram6_stall_upstream - 28 - - - sram6_stall_downstream - 29 - - - sram6_access_contested - 30 - - - sram6_access - 31 - - - sram5_stall_upstream - 32 - - - sram5_stall_downstream - 33 - - - sram5_access_contested - 34 - - - sram5_access - 35 - - - sram4_stall_upstream - 36 - - - sram4_stall_downstream - 37 - - - sram4_access_contested - 38 - - - sram4_access - 39 - - - sram3_stall_upstream - 40 - - - sram3_stall_downstream - 41 - - - sram3_access_contested - 42 - - - sram3_access - 43 - - - sram2_stall_upstream - 44 - - - sram2_stall_downstream - 45 - - - sram2_access_contested - 46 - - - sram2_access - 47 - - - sram1_stall_upstream - 48 - - - sram1_stall_downstream - 49 - - - sram1_access_contested - 50 - - - sram1_access - 51 - - - sram0_stall_upstream - 52 - - - sram0_stall_downstream - 53 - - - sram0_access_contested - 54 - - - sram0_access - 55 - - - xip_main1_stall_upstream - 56 - - - xip_main1_stall_downstream - 57 - - - xip_main1_access_contested - 58 - - - xip_main1_access - 59 - - - xip_main0_stall_upstream - 60 - - - xip_main0_stall_downstream - 61 - - - xip_main0_access_contested - 62 - - - xip_main0_access - 63 - - - rom_stall_upstream - 64 - - - rom_stall_downstream - 65 - - - rom_access_contested - 66 - - - rom_access - 67 - - - - - - - PERFCTR3 - 0x00000024 - Bus fabric performance counter 3 - 0x00000000 - - - PERFCTR3 - Busfabric saturating performance counter 3 - Count some event signal from the busfabric arbiters, if PERFCTR_EN is set. - Write any value to clear. Select an event to count using PERFSEL3 - [23:0] - read-write - oneToClear - - - - - PERFSEL3 - 0x00000028 - Bus fabric performance event select for PERFCTR3 - 0x0000001f - - - PERFSEL3 - Select an event for PERFCTR3. For each downstream port of the main crossbar, four events are available: ACCESS, an access took place; ACCESS_CONTESTED, an access took place that previously stalled due to contention from other masters; STALL_DOWNSTREAM, count cycles where any master stalled due to a stall on the downstream bus; STALL_UPSTREAM, count cycles where any master stalled for any reason, including contention from other masters. - [6:0] - read-write - - - siob_proc1_stall_upstream - 0 - - - siob_proc1_stall_downstream - 1 - - - siob_proc1_access_contested - 2 - - - siob_proc1_access - 3 - - - siob_proc0_stall_upstream - 4 - - - siob_proc0_stall_downstream - 5 - - - siob_proc0_access_contested - 6 - - - siob_proc0_access - 7 - - - apb_stall_upstream - 8 - - - apb_stall_downstream - 9 - - - apb_access_contested - 10 - - - apb_access - 11 - - - fastperi_stall_upstream - 12 - - - fastperi_stall_downstream - 13 - - - fastperi_access_contested - 14 - - - fastperi_access - 15 - - - sram9_stall_upstream - 16 - - - sram9_stall_downstream - 17 - - - sram9_access_contested - 18 - - - sram9_access - 19 - - - sram8_stall_upstream - 20 - - - sram8_stall_downstream - 21 - - - sram8_access_contested - 22 - - - sram8_access - 23 - - - sram7_stall_upstream - 24 - - - sram7_stall_downstream - 25 - - - sram7_access_contested - 26 - - - sram7_access - 27 - - - sram6_stall_upstream - 28 - - - sram6_stall_downstream - 29 - - - sram6_access_contested - 30 - - - sram6_access - 31 - - - sram5_stall_upstream - 32 - - - sram5_stall_downstream - 33 - - - sram5_access_contested - 34 - - - sram5_access - 35 - - - sram4_stall_upstream - 36 - - - sram4_stall_downstream - 37 - - - sram4_access_contested - 38 - - - sram4_access - 39 - - - sram3_stall_upstream - 40 - - - sram3_stall_downstream - 41 - - - sram3_access_contested - 42 - - - sram3_access - 43 - - - sram2_stall_upstream - 44 - - - sram2_stall_downstream - 45 - - - sram2_access_contested - 46 - - - sram2_access - 47 - - - sram1_stall_upstream - 48 - - - sram1_stall_downstream - 49 - - - sram1_access_contested - 50 - - - sram1_access - 51 - - - sram0_stall_upstream - 52 - - - sram0_stall_downstream - 53 - - - sram0_access_contested - 54 - - - sram0_access - 55 - - - xip_main1_stall_upstream - 56 - - - xip_main1_stall_downstream - 57 - - - xip_main1_access_contested - 58 - - - xip_main1_access - 59 - - - xip_main0_stall_upstream - 60 - - - xip_main0_stall_downstream - 61 - - - xip_main0_access_contested - 62 - - - xip_main0_access - 63 - - - rom_stall_upstream - 64 - - - rom_stall_downstream - 65 - - - rom_access_contested - 66 - - - rom_access - 67 - - - - - - - - - SIO - Single-cycle IO block - Provides core-local and inter-core hardware for the two processors, with single-cycle access. - 0xd0000000 - - 0 - 488 - registers - - - SIO_IRQ_FIFO - 25 - - - SIO_IRQ_BELL - 26 - - - SIO_IRQ_FIFO_NS - 27 - - - SIO_IRQ_BELL_NS - 28 - - - SIO_IRQ_MTIMECMP - 29 - - - - CPUID - 0x00000000 - Processor core identifier - 0x00000000 - - - CPUID - Value is 0 when read from processor core 0, and 1 when read from processor core 1. - [31:0] - read-only - - - - - GPIO_IN - 0x00000004 - Input value for GPIO0...31. - - In the Non-secure SIO, Secure-only GPIOs (as per ACCESSCTRL) appear as zero. - 0x00000000 - - - GPIO_IN - [31:0] - read-only - - - - - GPIO_HI_IN - 0x00000008 - Input value on GPIO32...47, QSPI IOs and USB pins - - In the Non-secure SIO, Secure-only GPIOs (as per ACCESSCTRL) appear as zero. - 0x00000000 - - - QSPI_SD - Input value on QSPI SD0 (MOSI), SD1 (MISO), SD2 and SD3 pins - [31:28] - read-only - - - QSPI_CSN - Input value on QSPI CSn pin - [27:27] - read-only - - - QSPI_SCK - Input value on QSPI SCK pin - [26:26] - read-only - - - USB_DM - Input value on USB D- pin - [25:25] - read-only - - - USB_DP - Input value on USB D+ pin - [24:24] - read-only - - - GPIO - Input value on GPIO32...47 - [15:0] - read-only - - - - - GPIO_OUT - 0x00000010 - GPIO0...31 output value - 0x00000000 - - - GPIO_OUT - Set output level (1/0 -> high/low) for GPIO0...31. Reading back gives the last value written, NOT the input value from the pins. - - If core 0 and core 1 both write to GPIO_OUT simultaneously (or to a SET/CLR/XOR alias), the result is as though the write from core 0 took place first, and the write from core 1 was then applied to that intermediate result. - - In the Non-secure SIO, Secure-only GPIOs (as per ACCESSCTRL) ignore writes, and their output status reads back as zero. This is also true for SET/CLR/XOR aliases of this register. - [31:0] - read-write - - - - - GPIO_HI_OUT - 0x00000014 - Output value for GPIO32...47, QSPI IOs and USB pins. - - Write to set output level (1/0 -> high/low). Reading back gives the last value written, NOT the input value from the pins. If core 0 and core 1 both write to GPIO_HI_OUT simultaneously (or to a SET/CLR/XOR alias), the result is as though the write from core 0 took place first, and the write from core 1 was then applied to that intermediate result. - - In the Non-secure SIO, Secure-only GPIOs (as per ACCESSCTRL) ignore writes, and their output status reads back as zero. This is also true for SET/CLR/XOR aliases of this register. - 0x00000000 - - - QSPI_SD - Output value for QSPI SD0 (MOSI), SD1 (MISO), SD2 and SD3 pins - [31:28] - read-write - - - QSPI_CSN - Output value for QSPI CSn pin - [27:27] - read-write - - - QSPI_SCK - Output value for QSPI SCK pin - [26:26] - read-write - - - USB_DM - Output value for USB D- pin - [25:25] - read-write - - - USB_DP - Output value for USB D+ pin - [24:24] - read-write - - - GPIO - Output value for GPIO32...47 - [15:0] - read-write - - - - - GPIO_OUT_SET - 0x00000018 - GPIO0...31 output value set - 0x00000000 - - - GPIO_OUT_SET - Perform an atomic bit-set on GPIO_OUT, i.e. `GPIO_OUT |= wdata` - [31:0] - write-only - - - - - GPIO_HI_OUT_SET - 0x0000001c - Output value set for GPIO32..47, QSPI IOs and USB pins. - Perform an atomic bit-set on GPIO_HI_OUT, i.e. `GPIO_HI_OUT |= wdata` - 0x00000000 - - - QSPI_SD - [31:28] - write-only - - - QSPI_CSN - [27:27] - write-only - - - QSPI_SCK - [26:26] - write-only - - - USB_DM - [25:25] - write-only - - - USB_DP - [24:24] - write-only - - - GPIO - [15:0] - write-only - - - - - GPIO_OUT_CLR - 0x00000020 - GPIO0...31 output value clear - 0x00000000 - - - GPIO_OUT_CLR - Perform an atomic bit-clear on GPIO_OUT, i.e. `GPIO_OUT &= ~wdata` - [31:0] - write-only - - - - - GPIO_HI_OUT_CLR - 0x00000024 - Output value clear for GPIO32..47, QSPI IOs and USB pins. - Perform an atomic bit-clear on GPIO_HI_OUT, i.e. `GPIO_HI_OUT &= ~wdata` - 0x00000000 - - - QSPI_SD - [31:28] - write-only - - - QSPI_CSN - [27:27] - write-only - - - QSPI_SCK - [26:26] - write-only - - - USB_DM - [25:25] - write-only - - - USB_DP - [24:24] - write-only - - - GPIO - [15:0] - write-only - - - - - GPIO_OUT_XOR - 0x00000028 - GPIO0...31 output value XOR - 0x00000000 - - - GPIO_OUT_XOR - Perform an atomic bitwise XOR on GPIO_OUT, i.e. `GPIO_OUT ^= wdata` - [31:0] - write-only - - - - - GPIO_HI_OUT_XOR - 0x0000002c - Output value XOR for GPIO32..47, QSPI IOs and USB pins. - Perform an atomic bitwise XOR on GPIO_HI_OUT, i.e. `GPIO_HI_OUT ^= wdata` - 0x00000000 - - - QSPI_SD - [31:28] - write-only - - - QSPI_CSN - [27:27] - write-only - - - QSPI_SCK - [26:26] - write-only - - - USB_DM - [25:25] - write-only - - - USB_DP - [24:24] - write-only - - - GPIO - [15:0] - write-only - - - - - GPIO_OE - 0x00000030 - GPIO0...31 output enable - 0x00000000 - - - GPIO_OE - Set output enable (1/0 -> output/input) for GPIO0...31. Reading back gives the last value written. - - If core 0 and core 1 both write to GPIO_OE simultaneously (or to a SET/CLR/XOR alias), the result is as though the write from core 0 took place first, and the write from core 1 was then applied to that intermediate result. - - In the Non-secure SIO, Secure-only GPIOs (as per ACCESSCTRL) ignore writes, and their output status reads back as zero. This is also true for SET/CLR/XOR aliases of this register. - [31:0] - read-write - - - - - GPIO_HI_OE - 0x00000034 - Output enable value for GPIO32...47, QSPI IOs and USB pins. - - Write output enable (1/0 -> output/input). Reading back gives the last value written. If core 0 and core 1 both write to GPIO_HI_OE simultaneously (or to a SET/CLR/XOR alias), the result is as though the write from core 0 took place first, and the write from core 1 was then applied to that intermediate result. - - In the Non-secure SIO, Secure-only GPIOs (as per ACCESSCTRL) ignore writes, and their output status reads back as zero. This is also true for SET/CLR/XOR aliases of this register. - 0x00000000 - - - QSPI_SD - Output enable value for QSPI SD0 (MOSI), SD1 (MISO), SD2 and SD3 pins - [31:28] - read-write - - - QSPI_CSN - Output enable value for QSPI CSn pin - [27:27] - read-write - - - QSPI_SCK - Output enable value for QSPI SCK pin - [26:26] - read-write - - - USB_DM - Output enable value for USB D- pin - [25:25] - read-write - - - USB_DP - Output enable value for USB D+ pin - [24:24] - read-write - - - GPIO - Output enable value for GPIO32...47 - [15:0] - read-write - - - - - GPIO_OE_SET - 0x00000038 - GPIO0...31 output enable set - 0x00000000 - - - GPIO_OE_SET - Perform an atomic bit-set on GPIO_OE, i.e. `GPIO_OE |= wdata` - [31:0] - write-only - - - - - GPIO_HI_OE_SET - 0x0000003c - Output enable set for GPIO32...47, QSPI IOs and USB pins. - Perform an atomic bit-set on GPIO_HI_OE, i.e. `GPIO_HI_OE |= wdata` - 0x00000000 - - - QSPI_SD - [31:28] - write-only - - - QSPI_CSN - [27:27] - write-only - - - QSPI_SCK - [26:26] - write-only - - - USB_DM - [25:25] - write-only - - - USB_DP - [24:24] - write-only - - - GPIO - [15:0] - write-only - - - - - GPIO_OE_CLR - 0x00000040 - GPIO0...31 output enable clear - 0x00000000 - - - GPIO_OE_CLR - Perform an atomic bit-clear on GPIO_OE, i.e. `GPIO_OE &= ~wdata` - [31:0] - write-only - - - - - GPIO_HI_OE_CLR - 0x00000044 - Output enable clear for GPIO32...47, QSPI IOs and USB pins. - Perform an atomic bit-clear on GPIO_HI_OE, i.e. `GPIO_HI_OE &= ~wdata` - 0x00000000 - - - QSPI_SD - [31:28] - write-only - - - QSPI_CSN - [27:27] - write-only - - - QSPI_SCK - [26:26] - write-only - - - USB_DM - [25:25] - write-only - - - USB_DP - [24:24] - write-only - - - GPIO - [15:0] - write-only - - - - - GPIO_OE_XOR - 0x00000048 - GPIO0...31 output enable XOR - 0x00000000 - - - GPIO_OE_XOR - Perform an atomic bitwise XOR on GPIO_OE, i.e. `GPIO_OE ^= wdata` - [31:0] - write-only - - - - - GPIO_HI_OE_XOR - 0x0000004c - Output enable XOR for GPIO32...47, QSPI IOs and USB pins. - Perform an atomic bitwise XOR on GPIO_HI_OE, i.e. `GPIO_HI_OE ^= wdata` - 0x00000000 - - - QSPI_SD - [31:28] - write-only - - - QSPI_CSN - [27:27] - write-only - - - QSPI_SCK - [26:26] - write-only - - - USB_DM - [25:25] - write-only - - - USB_DP - [24:24] - write-only - - - GPIO - [15:0] - write-only - - - - - FIFO_ST - 0x00000050 - Status register for inter-core FIFOs (mailboxes). - There is one FIFO in the core 0 -> core 1 direction, and one core 1 -> core 0. Both are 32 bits wide and 8 words deep. - Core 0 can see the read side of the 1->0 FIFO (RX), and the write side of 0->1 FIFO (TX). - Core 1 can see the read side of the 0->1 FIFO (RX), and the write side of 1->0 FIFO (TX). - The SIO IRQ for each core is the logical OR of the VLD, WOF and ROE fields of its FIFO_ST register. - 0x00000002 - - - ROE - Sticky flag indicating the RX FIFO was read when empty. This read was ignored by the FIFO. - [3:3] - read-write - oneToClear - - - WOF - Sticky flag indicating the TX FIFO was written when full. This write was ignored by the FIFO. - [2:2] - read-write - oneToClear - - - RDY - Value is 1 if this core's TX FIFO is not full (i.e. if FIFO_WR is ready for more data) - [1:1] - read-only - - - VLD - Value is 1 if this core's RX FIFO is not empty (i.e. if FIFO_RD is valid) - [0:0] - read-only - - - - - FIFO_WR - 0x00000054 - Write access to this core's TX FIFO - 0x00000000 - - - FIFO_WR - [31:0] - write-only - - - - - FIFO_RD - 0x00000058 - Read access to this core's RX FIFO - 0x00000000 - - - FIFO_RD - [31:0] - read-only - modify - - - - - SPINLOCK_ST - 0x0000005c - Spinlock state - A bitmap containing the state of all 32 spinlocks (1=locked). - Mainly intended for debugging. - 0x00000000 - - - SPINLOCK_ST - [31:0] - read-only - - - - - INTERP0_ACCUM0 - 0x00000080 - Read/write access to accumulator 0 - 0x00000000 - - - INTERP0_ACCUM0 - [31:0] - read-write - - - - - INTERP0_ACCUM1 - 0x00000084 - Read/write access to accumulator 1 - 0x00000000 - - - INTERP0_ACCUM1 - [31:0] - read-write - - - - - INTERP0_BASE0 - 0x00000088 - Read/write access to BASE0 register. - 0x00000000 - - - INTERP0_BASE0 - [31:0] - read-write - - - - - INTERP0_BASE1 - 0x0000008c - Read/write access to BASE1 register. - 0x00000000 - - - INTERP0_BASE1 - [31:0] - read-write - - - - - INTERP0_BASE2 - 0x00000090 - Read/write access to BASE2 register. - 0x00000000 - - - INTERP0_BASE2 - [31:0] - read-write - - - - - INTERP0_POP_LANE0 - 0x00000094 - Read LANE0 result, and simultaneously write lane results to both accumulators (POP). - 0x00000000 - - - INTERP0_POP_LANE0 - [31:0] - read-only - - - - - INTERP0_POP_LANE1 - 0x00000098 - Read LANE1 result, and simultaneously write lane results to both accumulators (POP). - 0x00000000 - - - INTERP0_POP_LANE1 - [31:0] - read-only - - - - - INTERP0_POP_FULL - 0x0000009c - Read FULL result, and simultaneously write lane results to both accumulators (POP). - 0x00000000 - - - INTERP0_POP_FULL - [31:0] - read-only - - - - - INTERP0_PEEK_LANE0 - 0x000000a0 - Read LANE0 result, without altering any internal state (PEEK). - 0x00000000 - - - INTERP0_PEEK_LANE0 - [31:0] - read-only - - - - - INTERP0_PEEK_LANE1 - 0x000000a4 - Read LANE1 result, without altering any internal state (PEEK). - 0x00000000 - - - INTERP0_PEEK_LANE1 - [31:0] - read-only - - - - - INTERP0_PEEK_FULL - 0x000000a8 - Read FULL result, without altering any internal state (PEEK). - 0x00000000 - - - INTERP0_PEEK_FULL - [31:0] - read-only - - - - - INTERP0_CTRL_LANE0 - 0x000000ac - Control register for lane 0 - 0x00000000 - - - OVERF - Set if either OVERF0 or OVERF1 is set. - [25:25] - read-only - - - OVERF1 - Indicates if any masked-off MSBs in ACCUM1 are set. - [24:24] - read-only - - - OVERF0 - Indicates if any masked-off MSBs in ACCUM0 are set. - [23:23] - read-only - - - BLEND - Only present on INTERP0 on each core. If BLEND mode is enabled: - - LANE1 result is a linear interpolation between BASE0 and BASE1, controlled - by the 8 LSBs of lane 1 shift and mask value (a fractional number between - 0 and 255/256ths) - - LANE0 result does not have BASE0 added (yields only the 8 LSBs of lane 1 shift+mask value) - - FULL result does not have lane 1 shift+mask value added (BASE2 + lane 0 shift+mask) - LANE1 SIGNED flag controls whether the interpolation is signed or unsigned. - [21:21] - read-write - - - FORCE_MSB - ORed into bits 29:28 of the lane result presented to the processor on the bus. - No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence - of pointers into flash or SRAM. - [20:19] - read-write - - - ADD_RAW - If 1, mask + shift is bypassed for LANE0 result. This does not affect FULL result. - [18:18] - read-write - - - CROSS_RESULT - If 1, feed the opposite lane's result into this lane's accumulator on POP. - [17:17] - read-write - - - CROSS_INPUT - If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. - Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass) - [16:16] - read-write - - - SIGNED - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits - before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor. - [15:15] - read-write - - - MASK_MSB - The most-significant bit allowed to pass by the mask (inclusive) - Setting MSB < LSB may cause chip to turn inside-out - [14:10] - read-write - - - MASK_LSB - The least-significant bit allowed to pass by the mask (inclusive) - [9:5] - read-write - - - SHIFT - Right-rotate applied to accumulator before masking. By appropriately configuring the masks, left and right shifts can be synthesised. - [4:0] - read-write - - - - - INTERP0_CTRL_LANE1 - 0x000000b0 - Control register for lane 1 - 0x00000000 - - - FORCE_MSB - ORed into bits 29:28 of the lane result presented to the processor on the bus. - No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence - of pointers into flash or SRAM. - [20:19] - read-write - - - ADD_RAW - If 1, mask + shift is bypassed for LANE1 result. This does not affect FULL result. - [18:18] - read-write - - - CROSS_RESULT - If 1, feed the opposite lane's result into this lane's accumulator on POP. - [17:17] - read-write - - - CROSS_INPUT - If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. - Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass) - [16:16] - read-write - - - SIGNED - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits - before adding to BASE1, and LANE1 PEEK/POP appear extended to 32 bits when read by processor. - [15:15] - read-write - - - MASK_MSB - The most-significant bit allowed to pass by the mask (inclusive) - Setting MSB < LSB may cause chip to turn inside-out - [14:10] - read-write - - - MASK_LSB - The least-significant bit allowed to pass by the mask (inclusive) - [9:5] - read-write - - - SHIFT - Right-rotate applied to accumulator before masking. By appropriately configuring the masks, left and right shifts can be synthesised. - [4:0] - read-write - - - - - INTERP0_ACCUM0_ADD - 0x000000b4 - Values written here are atomically added to ACCUM0 - Reading yields lane 0's raw shift and mask value (BASE0 not added). - 0x00000000 - - - INTERP0_ACCUM0_ADD - [23:0] - read-write - - - - - INTERP0_ACCUM1_ADD - 0x000000b8 - Values written here are atomically added to ACCUM1 - Reading yields lane 1's raw shift and mask value (BASE1 not added). - 0x00000000 - - - INTERP0_ACCUM1_ADD - [23:0] - read-write - - - - - INTERP0_BASE_1AND0 - 0x000000bc - On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously. - Each half is sign-extended to 32 bits if that lane's SIGNED flag is set. - 0x00000000 - - - INTERP0_BASE_1AND0 - [31:0] - write-only - - - - - INTERP1_ACCUM0 - 0x000000c0 - Read/write access to accumulator 0 - 0x00000000 - - - INTERP1_ACCUM0 - [31:0] - read-write - - - - - INTERP1_ACCUM1 - 0x000000c4 - Read/write access to accumulator 1 - 0x00000000 - - - INTERP1_ACCUM1 - [31:0] - read-write - - - - - INTERP1_BASE0 - 0x000000c8 - Read/write access to BASE0 register. - 0x00000000 - - - INTERP1_BASE0 - [31:0] - read-write - - - - - INTERP1_BASE1 - 0x000000cc - Read/write access to BASE1 register. - 0x00000000 - - - INTERP1_BASE1 - [31:0] - read-write - - - - - INTERP1_BASE2 - 0x000000d0 - Read/write access to BASE2 register. - 0x00000000 - - - INTERP1_BASE2 - [31:0] - read-write - - - - - INTERP1_POP_LANE0 - 0x000000d4 - Read LANE0 result, and simultaneously write lane results to both accumulators (POP). - 0x00000000 - - - INTERP1_POP_LANE0 - [31:0] - read-only - - - - - INTERP1_POP_LANE1 - 0x000000d8 - Read LANE1 result, and simultaneously write lane results to both accumulators (POP). - 0x00000000 - - - INTERP1_POP_LANE1 - [31:0] - read-only - - - - - INTERP1_POP_FULL - 0x000000dc - Read FULL result, and simultaneously write lane results to both accumulators (POP). - 0x00000000 - - - INTERP1_POP_FULL - [31:0] - read-only - - - - - INTERP1_PEEK_LANE0 - 0x000000e0 - Read LANE0 result, without altering any internal state (PEEK). - 0x00000000 - - - INTERP1_PEEK_LANE0 - [31:0] - read-only - - - - - INTERP1_PEEK_LANE1 - 0x000000e4 - Read LANE1 result, without altering any internal state (PEEK). - 0x00000000 - - - INTERP1_PEEK_LANE1 - [31:0] - read-only - - - - - INTERP1_PEEK_FULL - 0x000000e8 - Read FULL result, without altering any internal state (PEEK). - 0x00000000 - - - INTERP1_PEEK_FULL - [31:0] - read-only - - - - - INTERP1_CTRL_LANE0 - 0x000000ec - Control register for lane 0 - 0x00000000 - - - OVERF - Set if either OVERF0 or OVERF1 is set. - [25:25] - read-only - - - OVERF1 - Indicates if any masked-off MSBs in ACCUM1 are set. - [24:24] - read-only - - - OVERF0 - Indicates if any masked-off MSBs in ACCUM0 are set. - [23:23] - read-only - - - CLAMP - Only present on INTERP1 on each core. If CLAMP mode is enabled: - - LANE0 result is shifted and masked ACCUM0, clamped by a lower bound of - BASE0 and an upper bound of BASE1. - - Signedness of these comparisons is determined by LANE0_CTRL_SIGNED - [22:22] - read-write - - - FORCE_MSB - ORed into bits 29:28 of the lane result presented to the processor on the bus. - No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence - of pointers into flash or SRAM. - [20:19] - read-write - - - ADD_RAW - If 1, mask + shift is bypassed for LANE0 result. This does not affect FULL result. - [18:18] - read-write - - - CROSS_RESULT - If 1, feed the opposite lane's result into this lane's accumulator on POP. - [17:17] - read-write - - - CROSS_INPUT - If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. - Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass) - [16:16] - read-write - - - SIGNED - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits - before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor. - [15:15] - read-write - - - MASK_MSB - The most-significant bit allowed to pass by the mask (inclusive) - Setting MSB < LSB may cause chip to turn inside-out - [14:10] - read-write - - - MASK_LSB - The least-significant bit allowed to pass by the mask (inclusive) - [9:5] - read-write - - - SHIFT - Right-rotate applied to accumulator before masking. By appropriately configuring the masks, left and right shifts can be synthesised. - [4:0] - read-write - - - - - INTERP1_CTRL_LANE1 - 0x000000f0 - Control register for lane 1 - 0x00000000 - - - FORCE_MSB - ORed into bits 29:28 of the lane result presented to the processor on the bus. - No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence - of pointers into flash or SRAM. - [20:19] - read-write - - - ADD_RAW - If 1, mask + shift is bypassed for LANE1 result. This does not affect FULL result. - [18:18] - read-write - - - CROSS_RESULT - If 1, feed the opposite lane's result into this lane's accumulator on POP. - [17:17] - read-write - - - CROSS_INPUT - If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. - Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass) - [16:16] - read-write - - - SIGNED - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits - before adding to BASE1, and LANE1 PEEK/POP appear extended to 32 bits when read by processor. - [15:15] - read-write - - - MASK_MSB - The most-significant bit allowed to pass by the mask (inclusive) - Setting MSB < LSB may cause chip to turn inside-out - [14:10] - read-write - - - MASK_LSB - The least-significant bit allowed to pass by the mask (inclusive) - [9:5] - read-write - - - SHIFT - Right-rotate applied to accumulator before masking. By appropriately configuring the masks, left and right shifts can be synthesised. - [4:0] - read-write - - - - - INTERP1_ACCUM0_ADD - 0x000000f4 - Values written here are atomically added to ACCUM0 - Reading yields lane 0's raw shift and mask value (BASE0 not added). - 0x00000000 - - - INTERP1_ACCUM0_ADD - [23:0] - read-write - - - - - INTERP1_ACCUM1_ADD - 0x000000f8 - Values written here are atomically added to ACCUM1 - Reading yields lane 1's raw shift and mask value (BASE1 not added). - 0x00000000 - - - INTERP1_ACCUM1_ADD - [23:0] - read-write - - - - - INTERP1_BASE_1AND0 - 0x000000fc - On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously. - Each half is sign-extended to 32 bits if that lane's SIGNED flag is set. - 0x00000000 - - - INTERP1_BASE_1AND0 - [31:0] - write-only - - - - - SPINLOCK0 - 0x00000100 - Reading from a spinlock address will: - - Return 0 if lock is already locked - - Otherwise return nonzero, and simultaneously claim the lock - - Writing (any value) releases the lock. - If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. - The value returned on success is 0x1 << lock number. - 0x00000000 - - - SPINLOCK0 - [31:0] - read-write - modify - - - - - SPINLOCK1 - 0x00000104 - Reading from a spinlock address will: - - Return 0 if lock is already locked - - Otherwise return nonzero, and simultaneously claim the lock - - Writing (any value) releases the lock. - If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. - The value returned on success is 0x1 << lock number. - 0x00000000 - - - SPINLOCK1 - [31:0] - read-write - modify - - - - - SPINLOCK2 - 0x00000108 - Reading from a spinlock address will: - - Return 0 if lock is already locked - - Otherwise return nonzero, and simultaneously claim the lock - - Writing (any value) releases the lock. - If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. - The value returned on success is 0x1 << lock number. - 0x00000000 - - - SPINLOCK2 - [31:0] - read-write - modify - - - - - SPINLOCK3 - 0x0000010c - Reading from a spinlock address will: - - Return 0 if lock is already locked - - Otherwise return nonzero, and simultaneously claim the lock - - Writing (any value) releases the lock. - If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. - The value returned on success is 0x1 << lock number. - 0x00000000 - - - SPINLOCK3 - [31:0] - read-write - modify - - - - - SPINLOCK4 - 0x00000110 - Reading from a spinlock address will: - - Return 0 if lock is already locked - - Otherwise return nonzero, and simultaneously claim the lock - - Writing (any value) releases the lock. - If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. - The value returned on success is 0x1 << lock number. - 0x00000000 - - - SPINLOCK4 - [31:0] - read-write - modify - - - - - SPINLOCK5 - 0x00000114 - Reading from a spinlock address will: - - Return 0 if lock is already locked - - Otherwise return nonzero, and simultaneously claim the lock - - Writing (any value) releases the lock. - If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. - The value returned on success is 0x1 << lock number. - 0x00000000 - - - SPINLOCK5 - [31:0] - read-write - modify - - - - - SPINLOCK6 - 0x00000118 - Reading from a spinlock address will: - - Return 0 if lock is already locked - - Otherwise return nonzero, and simultaneously claim the lock - - Writing (any value) releases the lock. - If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. - The value returned on success is 0x1 << lock number. - 0x00000000 - - - SPINLOCK6 - [31:0] - read-write - modify - - - - - SPINLOCK7 - 0x0000011c - Reading from a spinlock address will: - - Return 0 if lock is already locked - - Otherwise return nonzero, and simultaneously claim the lock - - Writing (any value) releases the lock. - If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. - The value returned on success is 0x1 << lock number. - 0x00000000 - - - SPINLOCK7 - [31:0] - read-write - modify - - - - - SPINLOCK8 - 0x00000120 - Reading from a spinlock address will: - - Return 0 if lock is already locked - - Otherwise return nonzero, and simultaneously claim the lock - - Writing (any value) releases the lock. - If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. - The value returned on success is 0x1 << lock number. - 0x00000000 - - - SPINLOCK8 - [31:0] - read-write - modify - - - - - SPINLOCK9 - 0x00000124 - Reading from a spinlock address will: - - Return 0 if lock is already locked - - Otherwise return nonzero, and simultaneously claim the lock - - Writing (any value) releases the lock. - If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. - The value returned on success is 0x1 << lock number. - 0x00000000 - - - SPINLOCK9 - [31:0] - read-write - modify - - - - - SPINLOCK10 - 0x00000128 - Reading from a spinlock address will: - - Return 0 if lock is already locked - - Otherwise return nonzero, and simultaneously claim the lock - - Writing (any value) releases the lock. - If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. - The value returned on success is 0x1 << lock number. - 0x00000000 - - - SPINLOCK10 - [31:0] - read-write - modify - - - - - SPINLOCK11 - 0x0000012c - Reading from a spinlock address will: - - Return 0 if lock is already locked - - Otherwise return nonzero, and simultaneously claim the lock - - Writing (any value) releases the lock. - If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. - The value returned on success is 0x1 << lock number. - 0x00000000 - - - SPINLOCK11 - [31:0] - read-write - modify - - - - - SPINLOCK12 - 0x00000130 - Reading from a spinlock address will: - - Return 0 if lock is already locked - - Otherwise return nonzero, and simultaneously claim the lock - - Writing (any value) releases the lock. - If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. - The value returned on success is 0x1 << lock number. - 0x00000000 - - - SPINLOCK12 - [31:0] - read-write - modify - - - - - SPINLOCK13 - 0x00000134 - Reading from a spinlock address will: - - Return 0 if lock is already locked - - Otherwise return nonzero, and simultaneously claim the lock - - Writing (any value) releases the lock. - If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. - The value returned on success is 0x1 << lock number. - 0x00000000 - - - SPINLOCK13 - [31:0] - read-write - modify - - - - - SPINLOCK14 - 0x00000138 - Reading from a spinlock address will: - - Return 0 if lock is already locked - - Otherwise return nonzero, and simultaneously claim the lock - - Writing (any value) releases the lock. - If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. - The value returned on success is 0x1 << lock number. - 0x00000000 - - - SPINLOCK14 - [31:0] - read-write - modify - - - - - SPINLOCK15 - 0x0000013c - Reading from a spinlock address will: - - Return 0 if lock is already locked - - Otherwise return nonzero, and simultaneously claim the lock - - Writing (any value) releases the lock. - If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. - The value returned on success is 0x1 << lock number. - 0x00000000 - - - SPINLOCK15 - [31:0] - read-write - modify - - - - - SPINLOCK16 - 0x00000140 - Reading from a spinlock address will: - - Return 0 if lock is already locked - - Otherwise return nonzero, and simultaneously claim the lock - - Writing (any value) releases the lock. - If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. - The value returned on success is 0x1 << lock number. - 0x00000000 - - - SPINLOCK16 - [31:0] - read-write - modify - - - - - SPINLOCK17 - 0x00000144 - Reading from a spinlock address will: - - Return 0 if lock is already locked - - Otherwise return nonzero, and simultaneously claim the lock - - Writing (any value) releases the lock. - If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. - The value returned on success is 0x1 << lock number. - 0x00000000 - - - SPINLOCK17 - [31:0] - read-write - modify - - - - - SPINLOCK18 - 0x00000148 - Reading from a spinlock address will: - - Return 0 if lock is already locked - - Otherwise return nonzero, and simultaneously claim the lock - - Writing (any value) releases the lock. - If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. - The value returned on success is 0x1 << lock number. - 0x00000000 - - - SPINLOCK18 - [31:0] - read-write - modify - - - - - SPINLOCK19 - 0x0000014c - Reading from a spinlock address will: - - Return 0 if lock is already locked - - Otherwise return nonzero, and simultaneously claim the lock - - Writing (any value) releases the lock. - If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. - The value returned on success is 0x1 << lock number. - 0x00000000 - - - SPINLOCK19 - [31:0] - read-write - modify - - - - - SPINLOCK20 - 0x00000150 - Reading from a spinlock address will: - - Return 0 if lock is already locked - - Otherwise return nonzero, and simultaneously claim the lock - - Writing (any value) releases the lock. - If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. - The value returned on success is 0x1 << lock number. - 0x00000000 - - - SPINLOCK20 - [31:0] - read-write - modify - - - - - SPINLOCK21 - 0x00000154 - Reading from a spinlock address will: - - Return 0 if lock is already locked - - Otherwise return nonzero, and simultaneously claim the lock - - Writing (any value) releases the lock. - If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. - The value returned on success is 0x1 << lock number. - 0x00000000 - - - SPINLOCK21 - [31:0] - read-write - modify - - - - - SPINLOCK22 - 0x00000158 - Reading from a spinlock address will: - - Return 0 if lock is already locked - - Otherwise return nonzero, and simultaneously claim the lock - - Writing (any value) releases the lock. - If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. - The value returned on success is 0x1 << lock number. - 0x00000000 - - - SPINLOCK22 - [31:0] - read-write - modify - - - - - SPINLOCK23 - 0x0000015c - Reading from a spinlock address will: - - Return 0 if lock is already locked - - Otherwise return nonzero, and simultaneously claim the lock - - Writing (any value) releases the lock. - If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. - The value returned on success is 0x1 << lock number. - 0x00000000 - - - SPINLOCK23 - [31:0] - read-write - modify - - - - - SPINLOCK24 - 0x00000160 - Reading from a spinlock address will: - - Return 0 if lock is already locked - - Otherwise return nonzero, and simultaneously claim the lock - - Writing (any value) releases the lock. - If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. - The value returned on success is 0x1 << lock number. - 0x00000000 - - - SPINLOCK24 - [31:0] - read-write - modify - - - - - SPINLOCK25 - 0x00000164 - Reading from a spinlock address will: - - Return 0 if lock is already locked - - Otherwise return nonzero, and simultaneously claim the lock - - Writing (any value) releases the lock. - If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. - The value returned on success is 0x1 << lock number. - 0x00000000 - - - SPINLOCK25 - [31:0] - read-write - modify - - - - - SPINLOCK26 - 0x00000168 - Reading from a spinlock address will: - - Return 0 if lock is already locked - - Otherwise return nonzero, and simultaneously claim the lock - - Writing (any value) releases the lock. - If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. - The value returned on success is 0x1 << lock number. - 0x00000000 - - - SPINLOCK26 - [31:0] - read-write - modify - - - - - SPINLOCK27 - 0x0000016c - Reading from a spinlock address will: - - Return 0 if lock is already locked - - Otherwise return nonzero, and simultaneously claim the lock - - Writing (any value) releases the lock. - If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. - The value returned on success is 0x1 << lock number. - 0x00000000 - - - SPINLOCK27 - [31:0] - read-write - modify - - - - - SPINLOCK28 - 0x00000170 - Reading from a spinlock address will: - - Return 0 if lock is already locked - - Otherwise return nonzero, and simultaneously claim the lock - - Writing (any value) releases the lock. - If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. - The value returned on success is 0x1 << lock number. - 0x00000000 - - - SPINLOCK28 - [31:0] - read-write - modify - - - - - SPINLOCK29 - 0x00000174 - Reading from a spinlock address will: - - Return 0 if lock is already locked - - Otherwise return nonzero, and simultaneously claim the lock - - Writing (any value) releases the lock. - If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. - The value returned on success is 0x1 << lock number. - 0x00000000 - - - SPINLOCK29 - [31:0] - read-write - modify - - - - - SPINLOCK30 - 0x00000178 - Reading from a spinlock address will: - - Return 0 if lock is already locked - - Otherwise return nonzero, and simultaneously claim the lock - - Writing (any value) releases the lock. - If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. - The value returned on success is 0x1 << lock number. - 0x00000000 - - - SPINLOCK30 - [31:0] - read-write - modify - - - - - SPINLOCK31 - 0x0000017c - Reading from a spinlock address will: - - Return 0 if lock is already locked - - Otherwise return nonzero, and simultaneously claim the lock - - Writing (any value) releases the lock. - If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. - The value returned on success is 0x1 << lock number. - 0x00000000 - - - SPINLOCK31 - [31:0] - read-write - modify - - - - - DOORBELL_OUT_SET - 0x00000180 - Trigger a doorbell interrupt on the opposite core. - - Write 1 to a bit to set the corresponding bit in DOORBELL_IN on the opposite core. This raises the opposite core's doorbell interrupt. - - Read to get the status of the doorbells currently asserted on the opposite core. This is equivalent to that core reading its own DOORBELL_IN status. - 0x00000000 - - - DOORBELL_OUT_SET - [7:0] - read-write - - - - - DOORBELL_OUT_CLR - 0x00000184 - Clear doorbells which have been posted to the opposite core. This register is intended for debugging and initialisation purposes. - - Writing 1 to a bit in DOORBELL_OUT_CLR clears the corresponding bit in DOORBELL_IN on the opposite core. Clearing all bits will cause that core's doorbell interrupt to deassert. Since the usual order of events is for software to send events using DOORBELL_OUT_SET, and acknowledge incoming events by writing to DOORBELL_IN_CLR, this register should be used with caution to avoid race conditions. - - Reading returns the status of the doorbells currently asserted on the other core, i.e. is equivalent to that core reading its own DOORBELL_IN status. - 0x00000000 - - - DOORBELL_OUT_CLR - [7:0] - read-write - oneToClear - - - - - DOORBELL_IN_SET - 0x00000188 - Write 1s to trigger doorbell interrupts on this core. Read to get status of doorbells currently asserted on this core. - 0x00000000 - - - DOORBELL_IN_SET - [7:0] - read-write - - - - - DOORBELL_IN_CLR - 0x0000018c - Check and acknowledge doorbells posted to this core. This core's doorbell interrupt is asserted when any bit in this register is 1. - - Write 1 to each bit to clear that bit. The doorbell interrupt deasserts once all bits are cleared. Read to get status of doorbells currently asserted on this core. - 0x00000000 - - - DOORBELL_IN_CLR - [7:0] - read-write - oneToClear - - - - - PERI_NONSEC - 0x00000190 - Detach certain core-local peripherals from Secure SIO, and attach them to Non-secure SIO, so that Non-secure software can use them. Attempting to access one of these peripherals from the Secure SIO when it is attached to the Non-secure SIO, or vice versa, will generate a bus error. - - This register is per-core, and is only present on the Secure SIO. - - Most SIO hardware is duplicated across the Secure and Non-secure SIO, so is not listed in this register. - 0x00000000 - - - TMDS - IF 1, detach TMDS encoder (of this core) from the Secure SIO, and attach to the Non-secure SIO. - [5:5] - read-write - - - INTERP1 - If 1, detach interpolator 1 (of this core) from the Secure SIO, and attach to the Non-secure SIO. - [1:1] - read-write - - - INTERP0 - If 1, detach interpolator 0 (of this core) from the Secure SIO, and attach to the Non-secure SIO. - [0:0] - read-write - - - - - RISCV_SOFTIRQ - 0x000001a0 - Control the assertion of the standard software interrupt (MIP.MSIP) on the RISC-V cores. - - Unlike the RISC-V timer, this interrupt is not routed to a normal system-level interrupt line, so can not be used by the Arm cores. - - It is safe for both cores to write to this register on the same cycle. The set/clear effect is accumulated across both cores, and then applied. If a flag is both set and cleared on the same cycle, only the set takes effect. - 0x00000000 - - - CORE1_CLR - Write 1 to atomically clear the core 1 software interrupt flag. Read to get the status of this flag. - [9:9] - read-write - - - CORE0_CLR - Write 1 to atomically clear the core 0 software interrupt flag. Read to get the status of this flag. - [8:8] - read-write - - - CORE1_SET - Write 1 to atomically set the core 1 software interrupt flag. Read to get the status of this flag. - [1:1] - read-write - - - CORE0_SET - Write 1 to atomically set the core 0 software interrupt flag. Read to get the status of this flag. - [0:0] - read-write - - - - - MTIME_CTRL - 0x000001a4 - Control register for the RISC-V 64-bit Machine-mode timer. This timer is only present in the Secure SIO, so is only accessible to an Arm core in Secure mode or a RISC-V core in Machine mode. - - Note whilst this timer follows the RISC-V privileged specification, it is equally usable by the Arm cores. The interrupts are routed to normal system-level interrupt lines as well as to the MIP.MTIP inputs on the RISC-V cores. - 0x0000000d - - - DBGPAUSE_CORE1 - If 1, the timer pauses when core 1 is in the debug halt state. - [3:3] - read-write - - - DBGPAUSE_CORE0 - If 1, the timer pauses when core 0 is in the debug halt state. - [2:2] - read-write - - - FULLSPEED - If 1, increment the timer every cycle (i.e. run directly from the system clock), rather than incrementing on the system-level timer tick input. - [1:1] - read-write - - - EN - Timer enable bit. When 0, the timer will not increment automatically. - [0:0] - read-write - - - - - MTIME - 0x000001b0 - Read/write access to the high half of RISC-V Machine-mode timer. This register is shared between both cores. If both cores write on the same cycle, core 1 takes precedence. - 0x00000000 - - - MTIME - [31:0] - read-write - - - - - MTIMEH - 0x000001b4 - Read/write access to the high half of RISC-V Machine-mode timer. This register is shared between both cores. If both cores write on the same cycle, core 1 takes precedence. - 0x00000000 - - - MTIMEH - [31:0] - read-write - - - - - MTIMECMP - 0x000001b8 - Low half of RISC-V Machine-mode timer comparator. This register is core-local, i.e., each core gets a copy of this register, with the comparison result routed to its own interrupt line. - - The timer interrupt is asserted whenever MTIME is greater than or equal to MTIMECMP. This comparison is unsigned, and performed on the full 64-bit values. - 0xffffffff - - - MTIMECMP - [31:0] - read-write - - - - - MTIMECMPH - 0x000001bc - High half of RISC-V Machine-mode timer comparator. This register is core-local. - - The timer interrupt is asserted whenever MTIME is greater than or equal to MTIMECMP. This comparison is unsigned, and performed on the full 64-bit values. - 0xffffffff - - - MTIMECMPH - [31:0] - read-write - - - - - TMDS_CTRL - 0x000001c0 - Control register for TMDS encoder. - 0x00000000 - - - CLEAR_BALANCE - Clear the running DC balance state of the TMDS encoders. This bit should be written once at the beginning of each scanline. - [28:28] - write-only - - - PIX2_NOSHIFT - When encoding two pixels's worth of symbols in one cycle (a read of a PEEK/POP_DOUBLE register), the second encoder sees a shifted version of the colour data register. - - This control disables that shift, so that both encoder layers see the same pixel data. This is used for pixel doubling. - [27:27] - read-write - - - PIX_SHIFT - Shift applied to the colour data register with each read of a POP alias register. - - Reading from the POP_SINGLE register, or reading from the POP_DOUBLE register with PIX2_NOSHIFT set (for pixel doubling), shifts by the indicated amount. - - Reading from a POP_DOUBLE register when PIX2_NOSHIFT is clear will shift by double the indicated amount. (Shift by 32 means no shift.) - [26:24] - read-write - - - 0 - 0 - Do not shift the colour data register. - - - 1 - 1 - Shift the colour data register by 1 bit - - - 2 - 2 - Shift the colour data register by 2 bits - - - 4 - 3 - Shift the colour data register by 4 bits - - - 8 - 4 - Shift the colour data register by 8 bits - - - 16 - 5 - Shift the colour data register by 16 bits - - - - - INTERLEAVE - Enable lane interleaving for reads of PEEK_SINGLE/POP_SINGLE. - - When interleaving is disabled, each of the 3 symbols appears as a contiguous 10-bit field, with lane 0 being the least-significant and starting at bit 0 of the register. - - When interleaving is enabled, the symbols are packed into 5 chunks of 3 lanes times 2 bits (30 bits total). Each chunk contains two bits of a TMDS symbol per lane, with lane 0 being the least significant. - [23:23] - read-write - - - L2_NBITS - Number of valid colour MSBs for lane 2 (1-8 bits, encoded as 0 through 7). Remaining LSBs are masked to 0 after the rotate. - [20:18] - read-write - - - L1_NBITS - Number of valid colour MSBs for lane 1 (1-8 bits, encoded as 0 through 7). Remaining LSBs are masked to 0 after the rotate. - [17:15] - read-write - - - L0_NBITS - Number of valid colour MSBs for lane 0 (1-8 bits, encoded as 0 through 7). Remaining LSBs are masked to 0 after the rotate. - [14:12] - read-write - - - L2_ROT - Right-rotate the 16 LSBs of the colour accumulator by 0-15 bits, in order to get the MSB of the lane 2 (red) colour data aligned with the MSB of the 8-bit encoder input. - - For example, for RGB565 (red most significant), red is bits 15:11, so should be right-rotated by 8 bits to align with bits 7:3 of the encoder input. - [11:8] - read-write - - - L1_ROT - Right-rotate the 16 LSBs of the colour accumulator by 0-15 bits, in order to get the MSB of the lane 1 (green) colour data aligned with the MSB of the 8-bit encoder input. - - For example, for RGB565, green is bits 10:5, so should be right-rotated by 3 bits to align with bits 7:2 of the encoder input. - [7:4] - read-write - - - L0_ROT - Right-rotate the 16 LSBs of the colour accumulator by 0-15 bits, in order to get the MSB of the lane 0 (blue) colour data aligned with the MSB of the 8-bit encoder input. - - For example, for RGB565 (red most significant), blue is bits 4:0, so should be right-rotated by 13 to align with bits 7:3 of the encoder input. - [3:0] - read-write - - - - - TMDS_WDATA - 0x000001c4 - Write-only access to the TMDS colour data register. - 0x00000000 - - - TMDS_WDATA - [31:0] - write-only - - - - - TMDS_PEEK_SINGLE - 0x000001c8 - Get the encoding of one pixel's worth of colour data, packed into a 32-bit value (3x10-bit symbols). - - The PEEK alias does not shift the colour register when read, but still advances the running DC balance state of each encoder. This is useful for pixel doubling. - 0x00000000 - - - TMDS_PEEK_SINGLE - [31:0] - read-only - modify - - - - - TMDS_POP_SINGLE - 0x000001cc - Get the encoding of one pixel's worth of colour data, packed into a 32-bit value. The packing is 5 chunks of 3 lanes times 2 bits (30 bits total). Each chunk contains two bits of a TMDS symbol per lane. This format is intended for shifting out with the HSTX peripheral on RP2350. - - The POP alias shifts the colour register when read, as well as advancing the running DC balance state of each encoder. - 0x00000000 - - - TMDS_POP_SINGLE - [31:0] - read-only - modify - - - - - TMDS_PEEK_DOUBLE_L0 - 0x000001d0 - Get lane 0 of the encoding of two pixels' worth of colour data. Two 10-bit TMDS symbols are packed at the bottom of a 32-bit word. - - The PEEK alias does not shift the colour register when read, but still advances the lane 0 DC balance state. This is useful if all 3 lanes' worth of encode are to be read at once, rather than processing the entire scanline for one lane before moving to the next lane. - 0x00000000 - - - TMDS_PEEK_DOUBLE_L0 - [31:0] - read-only - modify - - - - - TMDS_POP_DOUBLE_L0 - 0x000001d4 - Get lane 0 of the encoding of two pixels' worth of colour data. Two 10-bit TMDS symbols are packed at the bottom of a 32-bit word. - - The POP alias shifts the colour register when read, according to the values of PIX_SHIFT and PIX2_NOSHIFT. - 0x00000000 - - - TMDS_POP_DOUBLE_L0 - [31:0] - read-only - modify - - - - - TMDS_PEEK_DOUBLE_L1 - 0x000001d8 - Get lane 1 of the encoding of two pixels' worth of colour data. Two 10-bit TMDS symbols are packed at the bottom of a 32-bit word. - - The PEEK alias does not shift the colour register when read, but still advances the lane 1 DC balance state. This is useful if all 3 lanes' worth of encode are to be read at once, rather than processing the entire scanline for one lane before moving to the next lane. - 0x00000000 - - - TMDS_PEEK_DOUBLE_L1 - [31:0] - read-only - modify - - - - - TMDS_POP_DOUBLE_L1 - 0x000001dc - Get lane 1 of the encoding of two pixels' worth of colour data. Two 10-bit TMDS symbols are packed at the bottom of a 32-bit word. - - The POP alias shifts the colour register when read, according to the values of PIX_SHIFT and PIX2_NOSHIFT. - 0x00000000 - - - TMDS_POP_DOUBLE_L1 - [31:0] - read-only - modify - - - - - TMDS_PEEK_DOUBLE_L2 - 0x000001e0 - Get lane 2 of the encoding of two pixels' worth of colour data. Two 10-bit TMDS symbols are packed at the bottom of a 32-bit word. - - The PEEK alias does not shift the colour register when read, but still advances the lane 2 DC balance state. This is useful if all 3 lanes' worth of encode are to be read at once, rather than processing the entire scanline for one lane before moving to the next lane. - 0x00000000 - - - TMDS_PEEK_DOUBLE_L2 - [31:0] - read-only - modify - - - - - TMDS_POP_DOUBLE_L2 - 0x000001e4 - Get lane 2 of the encoding of two pixels' worth of colour data. Two 10-bit TMDS symbols are packed at the bottom of a 32-bit word. - - The POP alias shifts the colour register when read, according to the values of PIX_SHIFT and PIX2_NOSHIFT. - 0x00000000 - - - TMDS_POP_DOUBLE_L2 - [31:0] - read-only - modify - - - - - - - SIO_NS - 0xd0020000 - - - BOOTRAM - Additional registers mapped adjacent to the bootram, for use by the bootrom. - 0x400e0000 - - 0 - 2092 - registers - - - - WRITE_ONCE0 - 0x00000800 - This registers always ORs writes into its current contents. Once a bit is set, it can only be cleared by a reset. - 0x00000000 - - - WRITE_ONCE0 - [31:0] - read-write - - - - - WRITE_ONCE1 - 0x00000804 - This registers always ORs writes into its current contents. Once a bit is set, it can only be cleared by a reset. - 0x00000000 - - - WRITE_ONCE1 - [31:0] - read-write - - - - - BOOTLOCK_STAT - 0x00000808 - Bootlock status register. 1=unclaimed, 0=claimed. These locks function identically to the SIO spinlocks, but are reserved for bootrom use. - 0x000000ff - - - BOOTLOCK_STAT - [7:0] - read-write - - - - - BOOTLOCK0 - 0x0000080c - Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero. - 0x00000000 - - - BOOTLOCK0 - [31:0] - read-write - - - - - BOOTLOCK1 - 0x00000810 - Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero. - 0x00000000 - - - BOOTLOCK1 - [31:0] - read-write - - - - - BOOTLOCK2 - 0x00000814 - Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero. - 0x00000000 - - - BOOTLOCK2 - [31:0] - read-write - - - - - BOOTLOCK3 - 0x00000818 - Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero. - 0x00000000 - - - BOOTLOCK3 - [31:0] - read-write - - - - - BOOTLOCK4 - 0x0000081c - Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero. - 0x00000000 - - - BOOTLOCK4 - [31:0] - read-write - - - - - BOOTLOCK5 - 0x00000820 - Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero. - 0x00000000 - - - BOOTLOCK5 - [31:0] - read-write - - - - - BOOTLOCK6 - 0x00000824 - Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero. - 0x00000000 - - - BOOTLOCK6 - [31:0] - read-write - - - - - BOOTLOCK7 - 0x00000828 - Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero. - 0x00000000 - - - BOOTLOCK7 - [31:0] - read-write - - - - - - - CORESIGHT_TRACE - Coresight block - RP specific registers - 0x50700000 - - 0 - 8 - registers - - - - CTRL_STATUS - 0x00000000 - Control and status register - 0x00000001 - - - TRACE_CAPTURE_FIFO_OVERFLOW - This status flag is set high when trace data has been dropped due to the FIFO being full at the point trace data was sampled. Write 1 to acknowledge and clear the bit. - [1:1] - read-write - - - TRACE_CAPTURE_FIFO_FLUSH - Set to 1 to continuously hold the trace FIFO in a flushed state and prevent overflow. - - Before clearing this flag, configure and start a DMA channel with the correct DREQ for the TRACE_CAPTURE_FIFO register. - - Clear this flag to begin sampling trace data, and set once again once the trace capture buffer is full. You must configure the TPIU in order to generate trace packets to be captured, as well as components like the ETM further upstream to generate the event stream propagated to the TPIU. - [0:0] - read-write - - - - - TRACE_CAPTURE_FIFO - 0x00000004 - FIFO for trace data captured from the TPIU - 0x00000000 - - - RDATA - Read from an 8 x 32-bit FIFO containing trace data captured from the TPIU. - - Hardware pushes to the FIFO on rising edges of clk_sys, when either of the following is true: - - * TPIU TRACECTL output is low (normal trace data) - - * TPIU TRACETCL output is high, and TPIU TRACEDATA0 and TRACEDATA1 are both low (trigger packet) - - These conditions are in accordance with Arm Coresight Architecture Spec v3.0 section D3.3.3: Decoding requirements for Trace Capture Devices - - The data captured into the FIFO is the full 32-bit TRACEDATA bus output by the TPIU. Note that the TPIU is a DDR output at half of clk_sys, therefore this interface can capture the full 32-bit TPIU DDR output bandwidth as it samples once per active edge of the TPIU output clock. - [31:0] - read-only - modify - - - - - - - USB - USB FS/LS controller device registers - 0x50110000 - - 0 - 280 - registers - - - USBCTRL_IRQ - 14 - - - - ADDR_ENDP - 0x00000000 - Device address and endpoint control - 0x00000000 - - - ENDPOINT - Device endpoint to send data to. Only valid for HOST mode. - [19:16] - read-write - - - ADDRESS - In device mode, the address that the device should respond to. Set in response to a SET_ADDR setup packet from the host. In host mode set to the address of the device to communicate with. - [6:0] - read-write - - - - - ADDR_ENDP1 - 0x00000004 - Interrupt endpoint 1. Only valid for HOST mode. - 0x00000000 - - - INTEP_PREAMBLE - Interrupt EP requires preamble (is a low speed device on a full speed hub) - [26:26] - read-write - - - INTEP_DIR - Direction of the interrupt endpoint. In=0, Out=1 - [25:25] - read-write - - - ENDPOINT - Endpoint number of the interrupt endpoint - [19:16] - read-write - - - ADDRESS - Device address - [6:0] - read-write - - - - - ADDR_ENDP2 - 0x00000008 - Interrupt endpoint 2. Only valid for HOST mode. - 0x00000000 - - - INTEP_PREAMBLE - Interrupt EP requires preamble (is a low speed device on a full speed hub) - [26:26] - read-write - - - INTEP_DIR - Direction of the interrupt endpoint. In=0, Out=1 - [25:25] - read-write - - - ENDPOINT - Endpoint number of the interrupt endpoint - [19:16] - read-write - - - ADDRESS - Device address - [6:0] - read-write - - - - - ADDR_ENDP3 - 0x0000000c - Interrupt endpoint 3. Only valid for HOST mode. - 0x00000000 - - - INTEP_PREAMBLE - Interrupt EP requires preamble (is a low speed device on a full speed hub) - [26:26] - read-write - - - INTEP_DIR - Direction of the interrupt endpoint. In=0, Out=1 - [25:25] - read-write - - - ENDPOINT - Endpoint number of the interrupt endpoint - [19:16] - read-write - - - ADDRESS - Device address - [6:0] - read-write - - - - - ADDR_ENDP4 - 0x00000010 - Interrupt endpoint 4. Only valid for HOST mode. - 0x00000000 - - - INTEP_PREAMBLE - Interrupt EP requires preamble (is a low speed device on a full speed hub) - [26:26] - read-write - - - INTEP_DIR - Direction of the interrupt endpoint. In=0, Out=1 - [25:25] - read-write - - - ENDPOINT - Endpoint number of the interrupt endpoint - [19:16] - read-write - - - ADDRESS - Device address - [6:0] - read-write - - - - - ADDR_ENDP5 - 0x00000014 - Interrupt endpoint 5. Only valid for HOST mode. - 0x00000000 - - - INTEP_PREAMBLE - Interrupt EP requires preamble (is a low speed device on a full speed hub) - [26:26] - read-write - - - INTEP_DIR - Direction of the interrupt endpoint. In=0, Out=1 - [25:25] - read-write - - - ENDPOINT - Endpoint number of the interrupt endpoint - [19:16] - read-write - - - ADDRESS - Device address - [6:0] - read-write - - - - - ADDR_ENDP6 - 0x00000018 - Interrupt endpoint 6. Only valid for HOST mode. - 0x00000000 - - - INTEP_PREAMBLE - Interrupt EP requires preamble (is a low speed device on a full speed hub) - [26:26] - read-write - - - INTEP_DIR - Direction of the interrupt endpoint. In=0, Out=1 - [25:25] - read-write - - - ENDPOINT - Endpoint number of the interrupt endpoint - [19:16] - read-write - - - ADDRESS - Device address - [6:0] - read-write - - - - - ADDR_ENDP7 - 0x0000001c - Interrupt endpoint 7. Only valid for HOST mode. - 0x00000000 - - - INTEP_PREAMBLE - Interrupt EP requires preamble (is a low speed device on a full speed hub) - [26:26] - read-write - - - INTEP_DIR - Direction of the interrupt endpoint. In=0, Out=1 - [25:25] - read-write - - - ENDPOINT - Endpoint number of the interrupt endpoint - [19:16] - read-write - - - ADDRESS - Device address - [6:0] - read-write - - - - - ADDR_ENDP8 - 0x00000020 - Interrupt endpoint 8. Only valid for HOST mode. - 0x00000000 - - - INTEP_PREAMBLE - Interrupt EP requires preamble (is a low speed device on a full speed hub) - [26:26] - read-write - - - INTEP_DIR - Direction of the interrupt endpoint. In=0, Out=1 - [25:25] - read-write - - - ENDPOINT - Endpoint number of the interrupt endpoint - [19:16] - read-write - - - ADDRESS - Device address - [6:0] - read-write - - - - - ADDR_ENDP9 - 0x00000024 - Interrupt endpoint 9. Only valid for HOST mode. - 0x00000000 - - - INTEP_PREAMBLE - Interrupt EP requires preamble (is a low speed device on a full speed hub) - [26:26] - read-write - - - INTEP_DIR - Direction of the interrupt endpoint. In=0, Out=1 - [25:25] - read-write - - - ENDPOINT - Endpoint number of the interrupt endpoint - [19:16] - read-write - - - ADDRESS - Device address - [6:0] - read-write - - - - - ADDR_ENDP10 - 0x00000028 - Interrupt endpoint 10. Only valid for HOST mode. - 0x00000000 - - - INTEP_PREAMBLE - Interrupt EP requires preamble (is a low speed device on a full speed hub) - [26:26] - read-write - - - INTEP_DIR - Direction of the interrupt endpoint. In=0, Out=1 - [25:25] - read-write - - - ENDPOINT - Endpoint number of the interrupt endpoint - [19:16] - read-write - - - ADDRESS - Device address - [6:0] - read-write - - - - - ADDR_ENDP11 - 0x0000002c - Interrupt endpoint 11. Only valid for HOST mode. - 0x00000000 - - - INTEP_PREAMBLE - Interrupt EP requires preamble (is a low speed device on a full speed hub) - [26:26] - read-write - - - INTEP_DIR - Direction of the interrupt endpoint. In=0, Out=1 - [25:25] - read-write - - - ENDPOINT - Endpoint number of the interrupt endpoint - [19:16] - read-write - - - ADDRESS - Device address - [6:0] - read-write - - - - - ADDR_ENDP12 - 0x00000030 - Interrupt endpoint 12. Only valid for HOST mode. - 0x00000000 - - - INTEP_PREAMBLE - Interrupt EP requires preamble (is a low speed device on a full speed hub) - [26:26] - read-write - - - INTEP_DIR - Direction of the interrupt endpoint. In=0, Out=1 - [25:25] - read-write - - - ENDPOINT - Endpoint number of the interrupt endpoint - [19:16] - read-write - - - ADDRESS - Device address - [6:0] - read-write - - - - - ADDR_ENDP13 - 0x00000034 - Interrupt endpoint 13. Only valid for HOST mode. - 0x00000000 - - - INTEP_PREAMBLE - Interrupt EP requires preamble (is a low speed device on a full speed hub) - [26:26] - read-write - - - INTEP_DIR - Direction of the interrupt endpoint. In=0, Out=1 - [25:25] - read-write - - - ENDPOINT - Endpoint number of the interrupt endpoint - [19:16] - read-write - - - ADDRESS - Device address - [6:0] - read-write - - - - - ADDR_ENDP14 - 0x00000038 - Interrupt endpoint 14. Only valid for HOST mode. - 0x00000000 - - - INTEP_PREAMBLE - Interrupt EP requires preamble (is a low speed device on a full speed hub) - [26:26] - read-write - - - INTEP_DIR - Direction of the interrupt endpoint. In=0, Out=1 - [25:25] - read-write - - - ENDPOINT - Endpoint number of the interrupt endpoint - [19:16] - read-write - - - ADDRESS - Device address - [6:0] - read-write - - - - - ADDR_ENDP15 - 0x0000003c - Interrupt endpoint 15. Only valid for HOST mode. - 0x00000000 - - - INTEP_PREAMBLE - Interrupt EP requires preamble (is a low speed device on a full speed hub) - [26:26] - read-write - - - INTEP_DIR - Direction of the interrupt endpoint. In=0, Out=1 - [25:25] - read-write - - - ENDPOINT - Endpoint number of the interrupt endpoint - [19:16] - read-write - - - ADDRESS - Device address - [6:0] - read-write - - - - - MAIN_CTRL - 0x00000040 - Main control register - 0x00000004 - - - SIM_TIMING - Reduced timings for simulation - [31:31] - read-write - - - PHY_ISO - Isolates USB phy after controller power-up - Remove isolation once software has configured the controller - Not isolated = 0, Isolated = 1 - [2:2] - read-write - - - HOST_NDEVICE - Device mode = 0, Host mode = 1 - [1:1] - read-write - - - CONTROLLER_EN - Enable controller - [0:0] - read-write - - - - - SOF_WR - 0x00000044 - Set the SOF (Start of Frame) frame number in the host controller. The SOF packet is sent every 1ms and the host will increment the frame number by 1 each time. - 0x00000000 - - - COUNT - [10:0] - write-only - - - - - SOF_RD - 0x00000048 - Read the last SOF (Start of Frame) frame number seen. In device mode the last SOF received from the host. In host mode the last SOF sent by the host. - 0x00000000 - - - COUNT - [10:0] - read-only - - - - - SIE_CTRL - 0x0000004c - SIE control register - 0x00008000 - - - EP0_INT_STALL - Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a STALL - [31:31] - read-write - - - EP0_DOUBLE_BUF - Device: EP0 single buffered = 0, double buffered = 1 - [30:30] - read-write - - - EP0_INT_1BUF - Device: Set bit in BUFF_STATUS for every buffer completed on EP0 - [29:29] - read-write - - - EP0_INT_2BUF - Device: Set bit in BUFF_STATUS for every 2 buffers completed on EP0 - [28:28] - read-write - - - EP0_INT_NAK - Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a NAK - [27:27] - read-write - - - DIRECT_EN - Direct bus drive enable - [26:26] - read-write - - - DIRECT_DP - Direct control of DP - [25:25] - read-write - - - DIRECT_DM - Direct control of DM - [24:24] - read-write - - - EP0_STOP_ON_SHORT_PACKET - Device: Stop EP0 on a short packet. - [19:19] - read-write - - - TRANSCEIVER_PD - Power down bus transceiver - [18:18] - read-write - - - RPU_OPT - Device: Pull-up strength (0=1K2, 1=2k3) - [17:17] - read-write - - - PULLUP_EN - Device: Enable pull up resistor - [16:16] - read-write - - - PULLDOWN_EN - Host: Enable pull down resistors - [15:15] - read-write - - - RESET_BUS - Host: Reset bus - [13:13] - write-only - - - RESUME - Device: Remote wakeup. Device can initiate its own resume after suspend. - [12:12] - write-only - - - VBUS_EN - Host: Enable VBUS - [11:11] - read-write - - - KEEP_ALIVE_EN - Host: Enable keep alive packet (for low speed bus) - [10:10] - read-write - - - SOF_EN - Host: Enable SOF generation (for full speed bus) - [9:9] - read-write - - - SOF_SYNC - Host: Delay packet(s) until after SOF - [8:8] - read-write - - - PREAMBLE_EN - Host: Preable enable for LS device on FS hub - [6:6] - read-write - - - STOP_TRANS - Host: Stop transaction - [4:4] - write-only - - - RECEIVE_DATA - Host: Receive transaction (IN to host) - [3:3] - read-write - - - SEND_DATA - Host: Send transaction (OUT from host) - [2:2] - read-write - - - SEND_SETUP - Host: Send Setup packet - [1:1] - read-write - - - START_TRANS - Host: Start transaction - [0:0] - write-only - - - - - SIE_STATUS - 0x00000050 - SIE status register - 0x00000000 - - - DATA_SEQ_ERROR - Data Sequence Error. - - The device can raise a sequence error in the following conditions: - - * A SETUP packet is received followed by a DATA1 packet (data phase should always be DATA0) * An OUT packet is received from the host but doesn't match the data pid in the buffer control register read from DPSRAM - - The host can raise a data sequence error in the following conditions: - - * An IN packet from the device has the wrong data PID - [31:31] - read-write - oneToClear - - - ACK_REC - ACK received. Raised by both host and device. - [30:30] - read-write - oneToClear - - - STALL_REC - Host: STALL received - [29:29] - read-write - oneToClear - - - NAK_REC - Host: NAK received - [28:28] - read-write - oneToClear - - - RX_TIMEOUT - RX timeout is raised by both the host and device if an ACK is not received in the maximum time specified by the USB spec. - [27:27] - read-write - oneToClear - - - RX_OVERFLOW - RX overflow is raised by the Serial RX engine if the incoming data is too fast. - [26:26] - read-write - oneToClear - - - BIT_STUFF_ERROR - Bit Stuff Error. Raised by the Serial RX engine. - [25:25] - read-write - oneToClear - - - CRC_ERROR - CRC Error. Raised by the Serial RX engine. - [24:24] - read-write - oneToClear - - - ENDPOINT_ERROR - An endpoint has encountered an error. Read the ep_rx_error and ep_tx_error registers to find out which endpoint had an error. - [23:23] - read-write - oneToClear - - - BUS_RESET - Device: bus reset received - [19:19] - read-write - oneToClear - - - TRANS_COMPLETE - Transaction complete. - - Raised by device if: - - * An IN or OUT packet is sent with the `LAST_BUFF` bit set in the buffer control register - - Raised by host if: - - * A setup packet is sent when no data in or data out transaction follows * An IN packet is received and the `LAST_BUFF` bit is set in the buffer control register * An IN packet is received with zero length * An OUT packet is sent and the `LAST_BUFF` bit is set - [18:18] - read-write - oneToClear - - - SETUP_REC - Device: Setup packet received - [17:17] - read-write - oneToClear - - - CONNECTED - Device: connected - [16:16] - read-only - - - RX_SHORT_PACKET - Device or Host has received a short packet. This is when the data received is less than configured in the buffer control register. Device: If using double buffered mode on device the buffer select will not be toggled after writing status back to the buffer control register. This is to prevent any further transactions on that endpoint until the user has reset the buffer control registers. Host: the current transfer will be stopped early. - [12:12] - read-write - oneToClear - - - RESUME - Host: Device has initiated a remote resume. Device: host has initiated a resume. - [11:11] - read-write - oneToClear - - - VBUS_OVER_CURR - VBUS over current detected - [10:10] - read-only - - - SPEED - Host: device speed. Disconnected = 00, LS = 01, FS = 10 - [9:8] - read-only - - - SUSPENDED - Bus in suspended state. Valid for device. Device will go into suspend if neither Keep Alive / SOF frames are enabled. - [4:4] - read-write - oneToClear - - - LINE_STATE - USB bus line state - [3:2] - read-only - - - VBUS_DETECTED - Device: VBUS Detected - [0:0] - read-only - - - - - INT_EP_CTRL - 0x00000054 - interrupt endpoint control register - 0x00000000 - - - INT_EP_ACTIVE - Host: Enable interrupt endpoint 1 -> 15 - [15:1] - read-write - - - - - BUFF_STATUS - 0x00000058 - Buffer status register. A bit set here indicates that a buffer has completed on the endpoint (if the buffer interrupt is enabled). It is possible for 2 buffers to be completed, so clearing the buffer status bit may instantly re set it on the next clock cycle. - 0x00000000 - - - EP15_OUT - [31:31] - read-write - oneToClear - - - EP15_IN - [30:30] - read-write - oneToClear - - - EP14_OUT - [29:29] - read-write - oneToClear - - - EP14_IN - [28:28] - read-write - oneToClear - - - EP13_OUT - [27:27] - read-write - oneToClear - - - EP13_IN - [26:26] - read-write - oneToClear - - - EP12_OUT - [25:25] - read-write - oneToClear - - - EP12_IN - [24:24] - read-write - oneToClear - - - EP11_OUT - [23:23] - read-write - oneToClear - - - EP11_IN - [22:22] - read-write - oneToClear - - - EP10_OUT - [21:21] - read-write - oneToClear - - - EP10_IN - [20:20] - read-write - oneToClear - - - EP9_OUT - [19:19] - read-write - oneToClear - - - EP9_IN - [18:18] - read-write - oneToClear - - - EP8_OUT - [17:17] - read-write - oneToClear - - - EP8_IN - [16:16] - read-write - oneToClear - - - EP7_OUT - [15:15] - read-write - oneToClear - - - EP7_IN - [14:14] - read-write - oneToClear - - - EP6_OUT - [13:13] - read-write - oneToClear - - - EP6_IN - [12:12] - read-write - oneToClear - - - EP5_OUT - [11:11] - read-write - oneToClear - - - EP5_IN - [10:10] - read-write - oneToClear - - - EP4_OUT - [9:9] - read-write - oneToClear - - - EP4_IN - [8:8] - read-write - oneToClear - - - EP3_OUT - [7:7] - read-write - oneToClear - - - EP3_IN - [6:6] - read-write - oneToClear - - - EP2_OUT - [5:5] - read-write - oneToClear - - - EP2_IN - [4:4] - read-write - oneToClear - - - EP1_OUT - [3:3] - read-write - oneToClear - - - EP1_IN - [2:2] - read-write - oneToClear - - - EP0_OUT - [1:1] - read-write - oneToClear - - - EP0_IN - [0:0] - read-write - oneToClear - - - - - BUFF_CPU_SHOULD_HANDLE - 0x0000005c - Which of the double buffers should be handled. Only valid if using an interrupt per buffer (i.e. not per 2 buffers). Not valid for host interrupt endpoint polling because they are only single buffered. - 0x00000000 - - - EP15_OUT - [31:31] - read-only - - - EP15_IN - [30:30] - read-only - - - EP14_OUT - [29:29] - read-only - - - EP14_IN - [28:28] - read-only - - - EP13_OUT - [27:27] - read-only - - - EP13_IN - [26:26] - read-only - - - EP12_OUT - [25:25] - read-only - - - EP12_IN - [24:24] - read-only - - - EP11_OUT - [23:23] - read-only - - - EP11_IN - [22:22] - read-only - - - EP10_OUT - [21:21] - read-only - - - EP10_IN - [20:20] - read-only - - - EP9_OUT - [19:19] - read-only - - - EP9_IN - [18:18] - read-only - - - EP8_OUT - [17:17] - read-only - - - EP8_IN - [16:16] - read-only - - - EP7_OUT - [15:15] - read-only - - - EP7_IN - [14:14] - read-only - - - EP6_OUT - [13:13] - read-only - - - EP6_IN - [12:12] - read-only - - - EP5_OUT - [11:11] - read-only - - - EP5_IN - [10:10] - read-only - - - EP4_OUT - [9:9] - read-only - - - EP4_IN - [8:8] - read-only - - - EP3_OUT - [7:7] - read-only - - - EP3_IN - [6:6] - read-only - - - EP2_OUT - [5:5] - read-only - - - EP2_IN - [4:4] - read-only - - - EP1_OUT - [3:3] - read-only - - - EP1_IN - [2:2] - read-only - - - EP0_OUT - [1:1] - read-only - - - EP0_IN - [0:0] - read-only - - - - - EP_ABORT - 0x00000060 - Device only: Can be set to ignore the buffer control register for this endpoint in case you would like to revoke a buffer. A NAK will be sent for every access to the endpoint until this bit is cleared. A corresponding bit in `EP_ABORT_DONE` is set when it is safe to modify the buffer control register. - 0x00000000 - - - EP15_OUT - [31:31] - read-write - - - EP15_IN - [30:30] - read-write - - - EP14_OUT - [29:29] - read-write - - - EP14_IN - [28:28] - read-write - - - EP13_OUT - [27:27] - read-write - - - EP13_IN - [26:26] - read-write - - - EP12_OUT - [25:25] - read-write - - - EP12_IN - [24:24] - read-write - - - EP11_OUT - [23:23] - read-write - - - EP11_IN - [22:22] - read-write - - - EP10_OUT - [21:21] - read-write - - - EP10_IN - [20:20] - read-write - - - EP9_OUT - [19:19] - read-write - - - EP9_IN - [18:18] - read-write - - - EP8_OUT - [17:17] - read-write - - - EP8_IN - [16:16] - read-write - - - EP7_OUT - [15:15] - read-write - - - EP7_IN - [14:14] - read-write - - - EP6_OUT - [13:13] - read-write - - - EP6_IN - [12:12] - read-write - - - EP5_OUT - [11:11] - read-write - - - EP5_IN - [10:10] - read-write - - - EP4_OUT - [9:9] - read-write - - - EP4_IN - [8:8] - read-write - - - EP3_OUT - [7:7] - read-write - - - EP3_IN - [6:6] - read-write - - - EP2_OUT - [5:5] - read-write - - - EP2_IN - [4:4] - read-write - - - EP1_OUT - [3:3] - read-write - - - EP1_IN - [2:2] - read-write - - - EP0_OUT - [1:1] - read-write - - - EP0_IN - [0:0] - read-write - - - - - EP_ABORT_DONE - 0x00000064 - Device only: Used in conjunction with `EP_ABORT`. Set once an endpoint is idle so the programmer knows it is safe to modify the buffer control register. - 0x00000000 - - - EP15_OUT - [31:31] - read-write - oneToClear - - - EP15_IN - [30:30] - read-write - oneToClear - - - EP14_OUT - [29:29] - read-write - oneToClear - - - EP14_IN - [28:28] - read-write - oneToClear - - - EP13_OUT - [27:27] - read-write - oneToClear - - - EP13_IN - [26:26] - read-write - oneToClear - - - EP12_OUT - [25:25] - read-write - oneToClear - - - EP12_IN - [24:24] - read-write - oneToClear - - - EP11_OUT - [23:23] - read-write - oneToClear - - - EP11_IN - [22:22] - read-write - oneToClear - - - EP10_OUT - [21:21] - read-write - oneToClear - - - EP10_IN - [20:20] - read-write - oneToClear - - - EP9_OUT - [19:19] - read-write - oneToClear - - - EP9_IN - [18:18] - read-write - oneToClear - - - EP8_OUT - [17:17] - read-write - oneToClear - - - EP8_IN - [16:16] - read-write - oneToClear - - - EP7_OUT - [15:15] - read-write - oneToClear - - - EP7_IN - [14:14] - read-write - oneToClear - - - EP6_OUT - [13:13] - read-write - oneToClear - - - EP6_IN - [12:12] - read-write - oneToClear - - - EP5_OUT - [11:11] - read-write - oneToClear - - - EP5_IN - [10:10] - read-write - oneToClear - - - EP4_OUT - [9:9] - read-write - oneToClear - - - EP4_IN - [8:8] - read-write - oneToClear - - - EP3_OUT - [7:7] - read-write - oneToClear - - - EP3_IN - [6:6] - read-write - oneToClear - - - EP2_OUT - [5:5] - read-write - oneToClear - - - EP2_IN - [4:4] - read-write - oneToClear - - - EP1_OUT - [3:3] - read-write - oneToClear - - - EP1_IN - [2:2] - read-write - oneToClear - - - EP0_OUT - [1:1] - read-write - oneToClear - - - EP0_IN - [0:0] - read-write - oneToClear - - - - - EP_STALL_ARM - 0x00000068 - Device: this bit must be set in conjunction with the `STALL` bit in the buffer control register to send a STALL on EP0. The device controller clears these bits when a SETUP packet is received because the USB spec requires that a STALL condition is cleared when a SETUP packet is received. - 0x00000000 - - - EP0_OUT - [1:1] - read-write - - - EP0_IN - [0:0] - read-write - - - - - NAK_POLL - 0x0000006c - Used by the host controller. Sets the wait time in microseconds before trying again if the device replies with a NAK. - 0x00100010 - - - RETRY_COUNT_HI - Bits 9:6 of nak_retry count - [31:28] - read-only - - - EPX_STOPPED_ON_NAK - EPX polling has stopped because a nak was received - [27:27] - read-write - oneToClear - - - STOP_EPX_ON_NAK - Stop polling epx when a nak is received - [26:26] - read-write - - - DELAY_FS - NAK polling interval for a full speed device - [25:16] - read-write - - - RETRY_COUNT_LO - Bits 5:0 of nak_retry_count - [15:10] - read-only - - - DELAY_LS - NAK polling interval for a low speed device - [9:0] - read-write - - - - - EP_STATUS_STALL_NAK - 0x00000070 - Device: bits are set when the `IRQ_ON_NAK` or `IRQ_ON_STALL` bits are set. For EP0 this comes from `SIE_CTRL`. For all other endpoints it comes from the endpoint control register. - 0x00000000 - - - EP15_OUT - [31:31] - read-write - oneToClear - - - EP15_IN - [30:30] - read-write - oneToClear - - - EP14_OUT - [29:29] - read-write - oneToClear - - - EP14_IN - [28:28] - read-write - oneToClear - - - EP13_OUT - [27:27] - read-write - oneToClear - - - EP13_IN - [26:26] - read-write - oneToClear - - - EP12_OUT - [25:25] - read-write - oneToClear - - - EP12_IN - [24:24] - read-write - oneToClear - - - EP11_OUT - [23:23] - read-write - oneToClear - - - EP11_IN - [22:22] - read-write - oneToClear - - - EP10_OUT - [21:21] - read-write - oneToClear - - - EP10_IN - [20:20] - read-write - oneToClear - - - EP9_OUT - [19:19] - read-write - oneToClear - - - EP9_IN - [18:18] - read-write - oneToClear - - - EP8_OUT - [17:17] - read-write - oneToClear - - - EP8_IN - [16:16] - read-write - oneToClear - - - EP7_OUT - [15:15] - read-write - oneToClear - - - EP7_IN - [14:14] - read-write - oneToClear - - - EP6_OUT - [13:13] - read-write - oneToClear - - - EP6_IN - [12:12] - read-write - oneToClear - - - EP5_OUT - [11:11] - read-write - oneToClear - - - EP5_IN - [10:10] - read-write - oneToClear - - - EP4_OUT - [9:9] - read-write - oneToClear - - - EP4_IN - [8:8] - read-write - oneToClear - - - EP3_OUT - [7:7] - read-write - oneToClear - - - EP3_IN - [6:6] - read-write - oneToClear - - - EP2_OUT - [5:5] - read-write - oneToClear - - - EP2_IN - [4:4] - read-write - oneToClear - - - EP1_OUT - [3:3] - read-write - oneToClear - - - EP1_IN - [2:2] - read-write - oneToClear - - - EP0_OUT - [1:1] - read-write - oneToClear - - - EP0_IN - [0:0] - read-write - oneToClear - - - - - USB_MUXING - 0x00000074 - Where to connect the USB controller. Should be to_phy by default. - 0x00000001 - - - SWAP_DPDM - Swap the USB PHY DP and DM pins and all related controls and flip receive differential data. Can be used to switch USB DP/DP on the PCB. - This is done at a low level so overrides all other controls. - [31:31] - read-write - - - USBPHY_AS_GPIO - Use the usb DP and DM pins as GPIO pins instead of connecting them to the USB controller. - [4:4] - read-write - - - SOFTCON - [3:3] - read-write - - - TO_DIGITAL_PAD - [2:2] - read-write - - - TO_EXTPHY - [1:1] - read-write - - - TO_PHY - [0:0] - read-write - - - - - USB_PWR - 0x00000078 - Overrides for the power signals in the event that the VBUS signals are not hooked up to GPIO. Set the value of the override and then the override enable to switch over to the override value. - 0x00000000 - - - OVERCURR_DETECT_EN - [5:5] - read-write - - - OVERCURR_DETECT - [4:4] - read-write - - - VBUS_DETECT_OVERRIDE_EN - [3:3] - read-write - - - VBUS_DETECT - [2:2] - read-write - - - VBUS_EN_OVERRIDE_EN - [1:1] - read-write - - - VBUS_EN - [0:0] - read-write - - - - - USBPHY_DIRECT - 0x0000007c - This register allows for direct control of the USB phy. Use in conjunction with usbphy_direct_override register to enable each override bit. - 0x00000000 - - - RX_DM_OVERRIDE - Override rx_dm value into controller - [25:25] - read-write - - - RX_DP_OVERRIDE - Override rx_dp value into controller - [24:24] - read-write - - - RX_DD_OVERRIDE - Override rx_dd value into controller - [23:23] - read-write - - - DM_OVV - DM over voltage - [22:22] - read-only - - - DP_OVV - DP over voltage - [21:21] - read-only - - - DM_OVCN - DM overcurrent - [20:20] - read-only - - - DP_OVCN - DP overcurrent - [19:19] - read-only - - - RX_DM - DPM pin state - [18:18] - read-only - - - RX_DP - DPP pin state - [17:17] - read-only - - - RX_DD - Differential RX - [16:16] - read-only - - - TX_DIFFMODE - TX_DIFFMODE=0: Single ended mode - TX_DIFFMODE=1: Differential drive mode (TX_DM, TX_DM_OE ignored) - [15:15] - read-write - - - TX_FSSLEW - TX_FSSLEW=0: Low speed slew rate - TX_FSSLEW=1: Full speed slew rate - [14:14] - read-write - - - TX_PD - TX power down override (if override enable is set). 1 = powered down. - [13:13] - read-write - - - RX_PD - RX power down override (if override enable is set). 1 = powered down. - [12:12] - read-write - - - TX_DM - Output data. TX_DIFFMODE=1, Ignored - TX_DIFFMODE=0, Drives DPM only. TX_DM_OE=1 to enable drive. DPM=TX_DM - [11:11] - read-write - - - TX_DP - Output data. If TX_DIFFMODE=1, Drives DPP/DPM diff pair. TX_DP_OE=1 to enable drive. DPP=TX_DP, DPM=~TX_DP - If TX_DIFFMODE=0, Drives DPP only. TX_DP_OE=1 to enable drive. DPP=TX_DP - [10:10] - read-write - - - TX_DM_OE - Output enable. If TX_DIFFMODE=1, Ignored. - If TX_DIFFMODE=0, OE for DPM only. 0 - DPM in Hi-Z state; 1 - DPM driving - [9:9] - read-write - - - TX_DP_OE - Output enable. If TX_DIFFMODE=1, OE for DPP/DPM diff pair. 0 - DPP/DPM in Hi-Z state; 1 - DPP/DPM driving - If TX_DIFFMODE=0, OE for DPP only. 0 - DPP in Hi-Z state; 1 - DPP driving - [8:8] - read-write - - - DM_PULLDN_EN - DM pull down enable - [6:6] - read-write - - - DM_PULLUP_EN - DM pull up enable - [5:5] - read-write - - - DM_PULLUP_HISEL - Enable the second DM pull up resistor. 0 - Pull = Rpu2; 1 - Pull = Rpu1 + Rpu2 - [4:4] - read-write - - - DP_PULLDN_EN - DP pull down enable - [2:2] - read-write - - - DP_PULLUP_EN - DP pull up enable - [1:1] - read-write - - - DP_PULLUP_HISEL - Enable the second DP pull up resistor. 0 - Pull = Rpu2; 1 - Pull = Rpu1 + Rpu2 - [0:0] - read-write - - - - - USBPHY_DIRECT_OVERRIDE - 0x00000080 - Override enable for each control in usbphy_direct - 0x00000000 - - - RX_DM_OVERRIDE_EN - [18:18] - read-write - - - RX_DP_OVERRIDE_EN - [17:17] - read-write - - - RX_DD_OVERRIDE_EN - [16:16] - read-write - - - TX_DIFFMODE_OVERRIDE_EN - [15:15] - read-write - - - DM_PULLUP_OVERRIDE_EN - [12:12] - read-write - - - TX_FSSLEW_OVERRIDE_EN - [11:11] - read-write - - - TX_PD_OVERRIDE_EN - [10:10] - read-write - - - RX_PD_OVERRIDE_EN - [9:9] - read-write - - - TX_DM_OVERRIDE_EN - [8:8] - read-write - - - TX_DP_OVERRIDE_EN - [7:7] - read-write - - - TX_DM_OE_OVERRIDE_EN - [6:6] - read-write - - - TX_DP_OE_OVERRIDE_EN - [5:5] - read-write - - - DM_PULLDN_EN_OVERRIDE_EN - [4:4] - read-write - - - DP_PULLDN_EN_OVERRIDE_EN - [3:3] - read-write - - - DP_PULLUP_EN_OVERRIDE_EN - [2:2] - read-write - - - DM_PULLUP_HISEL_OVERRIDE_EN - [1:1] - read-write - - - DP_PULLUP_HISEL_OVERRIDE_EN - [0:0] - read-write - - - - - USBPHY_TRIM - 0x00000084 - Used to adjust trim values of USB phy pull down resistors. - 0x00001f1f - - - DM_PULLDN_TRIM - Value to drive to USB PHY - DM pulldown resistor trim control - Experimental data suggests that the reset value will work, but this register allows adjustment if required - [12:8] - read-write - - - DP_PULLDN_TRIM - Value to drive to USB PHY - DP pulldown resistor trim control - Experimental data suggests that the reset value will work, but this register allows adjustment if required - [4:0] - read-write - - - - - LINESTATE_TUNING - 0x00000088 - Used for debug only. - 0x000000f8 - - - SPARE_FIX - [11:8] - read-write - - - DEV_LS_WAKE_FIX - Device - exit suspend on any non-idle signalling, not qualified with a 1ms timer - [7:7] - read-write - - - DEV_RX_ERR_QUIESCE - Device - suppress repeated errors until the device FSM is next in the process of decoding an inbound packet. - [6:6] - read-write - - - SIE_RX_CHATTER_SE0_FIX - RX - when recovering from line chatter or bitstuff errors, treat SE0 as the end of chatter as well as - 8 consecutive idle bits. - [5:5] - read-write - - - SIE_RX_BITSTUFF_FIX - RX - when a bitstuff error is signalled by rx_dasm, unconditionally terminate RX decode to - avoid a hang during certain packet phases. - [4:4] - read-write - - - DEV_BUFF_CONTROL_DOUBLE_READ_FIX - Device - the controller FSM performs two reads of the buffer status memory address to - avoid sampling metastable data. An enabled buffer is only used if both reads match. - [3:3] - read-write - - - MULTI_HUB_FIX - Host - increase inter-packet and turnaround timeouts to accommodate worst-case hub delays. - [2:2] - read-write - - - LINESTATE_DELAY - Device/Host - add an extra 1-bit debounce of linestate sampling. - [1:1] - read-write - - - RCV_DELAY - Device - register the received data to account for hub bit dribble before EOP. Only affects certain hubs. - [0:0] - read-write - - - - - INTR - 0x0000008c - Raw Interrupts - 0x00000000 - - - EPX_STOPPED_ON_NAK - Source: NAK_POLL.EPX_STOPPED_ON_NAK - [23:23] - read-only - - - DEV_SM_WATCHDOG_FIRED - Source: DEV_SM_WATCHDOG.FIRED - [22:22] - read-only - - - ENDPOINT_ERROR - Source: SIE_STATUS.ENDPOINT_ERROR - [21:21] - read-only - - - RX_SHORT_PACKET - Source: SIE_STATUS.RX_SHORT_PACKET - [20:20] - read-only - - - EP_STALL_NAK - Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK. - [19:19] - read-only - - - ABORT_DONE - Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE. - [18:18] - read-only - - - DEV_SOF - Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD - [17:17] - read-only - - - SETUP_REQ - Device. Source: SIE_STATUS.SETUP_REC - [16:16] - read-only - - - DEV_RESUME_FROM_HOST - Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME - [15:15] - read-only - - - DEV_SUSPEND - Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED - [14:14] - read-only - - - DEV_CONN_DIS - Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED - [13:13] - read-only - - - BUS_RESET - Source: SIE_STATUS.BUS_RESET - [12:12] - read-only - - - VBUS_DETECT - Source: SIE_STATUS.VBUS_DETECTED - [11:11] - read-only - - - STALL - Source: SIE_STATUS.STALL_REC - [10:10] - read-only - - - ERROR_CRC - Source: SIE_STATUS.CRC_ERROR - [9:9] - read-only - - - ERROR_BIT_STUFF - Source: SIE_STATUS.BIT_STUFF_ERROR - [8:8] - read-only - - - ERROR_RX_OVERFLOW - Source: SIE_STATUS.RX_OVERFLOW - [7:7] - read-only - - - ERROR_RX_TIMEOUT - Source: SIE_STATUS.RX_TIMEOUT - [6:6] - read-only - - - ERROR_DATA_SEQ - Source: SIE_STATUS.DATA_SEQ_ERROR - [5:5] - read-only - - - BUFF_STATUS - Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS. - [4:4] - read-only - - - TRANS_COMPLETE - Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit. - [3:3] - read-only - - - HOST_SOF - Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD - [2:2] - read-only - - - HOST_RESUME - Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME - [1:1] - read-only - - - HOST_CONN_DIS - Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED - [0:0] - read-only - - - - - INTE - 0x00000090 - Interrupt Enable - 0x00000000 - - - EPX_STOPPED_ON_NAK - Source: NAK_POLL.EPX_STOPPED_ON_NAK - [23:23] - read-write - - - DEV_SM_WATCHDOG_FIRED - Source: DEV_SM_WATCHDOG.FIRED - [22:22] - read-write - - - ENDPOINT_ERROR - Source: SIE_STATUS.ENDPOINT_ERROR - [21:21] - read-write - - - RX_SHORT_PACKET - Source: SIE_STATUS.RX_SHORT_PACKET - [20:20] - read-write - - - EP_STALL_NAK - Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK. - [19:19] - read-write - - - ABORT_DONE - Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE. - [18:18] - read-write - - - DEV_SOF - Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD - [17:17] - read-write - - - SETUP_REQ - Device. Source: SIE_STATUS.SETUP_REC - [16:16] - read-write - - - DEV_RESUME_FROM_HOST - Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME - [15:15] - read-write - - - DEV_SUSPEND - Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED - [14:14] - read-write - - - DEV_CONN_DIS - Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED - [13:13] - read-write - - - BUS_RESET - Source: SIE_STATUS.BUS_RESET - [12:12] - read-write - - - VBUS_DETECT - Source: SIE_STATUS.VBUS_DETECTED - [11:11] - read-write - - - STALL - Source: SIE_STATUS.STALL_REC - [10:10] - read-write - - - ERROR_CRC - Source: SIE_STATUS.CRC_ERROR - [9:9] - read-write - - - ERROR_BIT_STUFF - Source: SIE_STATUS.BIT_STUFF_ERROR - [8:8] - read-write - - - ERROR_RX_OVERFLOW - Source: SIE_STATUS.RX_OVERFLOW - [7:7] - read-write - - - ERROR_RX_TIMEOUT - Source: SIE_STATUS.RX_TIMEOUT - [6:6] - read-write - - - ERROR_DATA_SEQ - Source: SIE_STATUS.DATA_SEQ_ERROR - [5:5] - read-write - - - BUFF_STATUS - Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS. - [4:4] - read-write - - - TRANS_COMPLETE - Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit. - [3:3] - read-write - - - HOST_SOF - Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD - [2:2] - read-write - - - HOST_RESUME - Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME - [1:1] - read-write - - - HOST_CONN_DIS - Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED - [0:0] - read-write - - - - - INTF - 0x00000094 - Interrupt Force - 0x00000000 - - - EPX_STOPPED_ON_NAK - Source: NAK_POLL.EPX_STOPPED_ON_NAK - [23:23] - read-write - - - DEV_SM_WATCHDOG_FIRED - Source: DEV_SM_WATCHDOG.FIRED - [22:22] - read-write - - - ENDPOINT_ERROR - Source: SIE_STATUS.ENDPOINT_ERROR - [21:21] - read-write - - - RX_SHORT_PACKET - Source: SIE_STATUS.RX_SHORT_PACKET - [20:20] - read-write - - - EP_STALL_NAK - Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK. - [19:19] - read-write - - - ABORT_DONE - Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE. - [18:18] - read-write - - - DEV_SOF - Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD - [17:17] - read-write - - - SETUP_REQ - Device. Source: SIE_STATUS.SETUP_REC - [16:16] - read-write - - - DEV_RESUME_FROM_HOST - Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME - [15:15] - read-write - - - DEV_SUSPEND - Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED - [14:14] - read-write - - - DEV_CONN_DIS - Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED - [13:13] - read-write - - - BUS_RESET - Source: SIE_STATUS.BUS_RESET - [12:12] - read-write - - - VBUS_DETECT - Source: SIE_STATUS.VBUS_DETECTED - [11:11] - read-write - - - STALL - Source: SIE_STATUS.STALL_REC - [10:10] - read-write - - - ERROR_CRC - Source: SIE_STATUS.CRC_ERROR - [9:9] - read-write - - - ERROR_BIT_STUFF - Source: SIE_STATUS.BIT_STUFF_ERROR - [8:8] - read-write - - - ERROR_RX_OVERFLOW - Source: SIE_STATUS.RX_OVERFLOW - [7:7] - read-write - - - ERROR_RX_TIMEOUT - Source: SIE_STATUS.RX_TIMEOUT - [6:6] - read-write - - - ERROR_DATA_SEQ - Source: SIE_STATUS.DATA_SEQ_ERROR - [5:5] - read-write - - - BUFF_STATUS - Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS. - [4:4] - read-write - - - TRANS_COMPLETE - Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit. - [3:3] - read-write - - - HOST_SOF - Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD - [2:2] - read-write - - - HOST_RESUME - Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME - [1:1] - read-write - - - HOST_CONN_DIS - Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED - [0:0] - read-write - - - - - INTS - 0x00000098 - Interrupt status after masking & forcing - 0x00000000 - - - EPX_STOPPED_ON_NAK - Source: NAK_POLL.EPX_STOPPED_ON_NAK - [23:23] - read-only - - - DEV_SM_WATCHDOG_FIRED - Source: DEV_SM_WATCHDOG.FIRED - [22:22] - read-only - - - ENDPOINT_ERROR - Source: SIE_STATUS.ENDPOINT_ERROR - [21:21] - read-only - - - RX_SHORT_PACKET - Source: SIE_STATUS.RX_SHORT_PACKET - [20:20] - read-only - - - EP_STALL_NAK - Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK. - [19:19] - read-only - - - ABORT_DONE - Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE. - [18:18] - read-only - - - DEV_SOF - Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD - [17:17] - read-only - - - SETUP_REQ - Device. Source: SIE_STATUS.SETUP_REC - [16:16] - read-only - - - DEV_RESUME_FROM_HOST - Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME - [15:15] - read-only - - - DEV_SUSPEND - Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED - [14:14] - read-only - - - DEV_CONN_DIS - Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED - [13:13] - read-only - - - BUS_RESET - Source: SIE_STATUS.BUS_RESET - [12:12] - read-only - - - VBUS_DETECT - Source: SIE_STATUS.VBUS_DETECTED - [11:11] - read-only - - - STALL - Source: SIE_STATUS.STALL_REC - [10:10] - read-only - - - ERROR_CRC - Source: SIE_STATUS.CRC_ERROR - [9:9] - read-only - - - ERROR_BIT_STUFF - Source: SIE_STATUS.BIT_STUFF_ERROR - [8:8] - read-only - - - ERROR_RX_OVERFLOW - Source: SIE_STATUS.RX_OVERFLOW - [7:7] - read-only - - - ERROR_RX_TIMEOUT - Source: SIE_STATUS.RX_TIMEOUT - [6:6] - read-only - - - ERROR_DATA_SEQ - Source: SIE_STATUS.DATA_SEQ_ERROR - [5:5] - read-only - - - BUFF_STATUS - Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS. - [4:4] - read-only - - - TRANS_COMPLETE - Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit. - [3:3] - read-only - - - HOST_SOF - Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD - [2:2] - read-only - - - HOST_RESUME - Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME - [1:1] - read-only - - - HOST_CONN_DIS - Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED - [0:0] - read-only - - - - - SOF_TIMESTAMP_RAW - 0x00000100 - Device only. Raw value of free-running PHY clock counter @48MHz. Used to calculate time between SOF events. - 0x00000000 - - - SOF_TIMESTAMP_RAW - [20:0] - read-only - - - - - SOF_TIMESTAMP_LAST - 0x00000104 - Device only. Value of free-running PHY clock counter @48MHz when last SOF event occurred. - 0x00000000 - - - SOF_TIMESTAMP_LAST - [20:0] - read-only - - - - - SM_STATE - 0x00000108 - 0x00000000 - - - RX_DASM - [11:8] - read-only - - - BC_STATE - [7:5] - read-only - - - STATE - [4:0] - read-only - - - - - EP_TX_ERROR - 0x0000010c - TX error count for each endpoint. Write to each field to reset the counter to 0. - 0x00000000 - - - EP15 - [31:30] - read-write - oneToClear - - - EP14 - [29:28] - read-write - oneToClear - - - EP13 - [27:26] - read-write - oneToClear - - - EP12 - [25:24] - read-write - oneToClear - - - EP11 - [23:22] - read-write - oneToClear - - - EP10 - [21:20] - read-write - oneToClear - - - EP9 - [19:18] - read-write - oneToClear - - - EP8 - [17:16] - read-write - oneToClear - - - EP7 - [15:14] - read-write - oneToClear - - - EP6 - [13:12] - read-write - oneToClear - - - EP5 - [11:10] - read-write - oneToClear - - - EP4 - [9:8] - read-write - oneToClear - - - EP3 - [7:6] - read-write - oneToClear - - - EP2 - [5:4] - read-write - oneToClear - - - EP1 - [3:2] - read-write - oneToClear - - - EP0 - [1:0] - read-write - oneToClear - - - - - EP_RX_ERROR - 0x00000110 - RX error count for each endpoint. Write to each field to reset the counter to 0. - 0x00000000 - - - EP15_SEQ - [31:31] - read-write - oneToClear - - - EP15_TRANSACTION - [30:30] - read-write - oneToClear - - - EP14_SEQ - [29:29] - read-write - oneToClear - - - EP14_TRANSACTION - [28:28] - read-write - oneToClear - - - EP13_SEQ - [27:27] - read-write - oneToClear - - - EP13_TRANSACTION - [26:26] - read-write - oneToClear - - - EP12_SEQ - [25:25] - read-write - oneToClear - - - EP12_TRANSACTION - [24:24] - read-write - oneToClear - - - EP11_SEQ - [23:23] - read-write - oneToClear - - - EP11_TRANSACTION - [22:22] - read-write - oneToClear - - - EP10_SEQ - [21:21] - read-write - oneToClear - - - EP10_TRANSACTION - [20:20] - read-write - oneToClear - - - EP9_SEQ - [19:19] - read-write - oneToClear - - - EP9_TRANSACTION - [18:18] - read-write - oneToClear - - - EP8_SEQ - [17:17] - read-write - oneToClear - - - EP8_TRANSACTION - [16:16] - read-write - oneToClear - - - EP7_SEQ - [15:15] - read-write - oneToClear - - - EP7_TRANSACTION - [14:14] - read-write - oneToClear - - - EP6_SEQ - [13:13] - read-write - oneToClear - - - EP6_TRANSACTION - [12:12] - read-write - oneToClear - - - EP5_SEQ - [11:11] - read-write - oneToClear - - - EP5_TRANSACTION - [10:10] - read-write - oneToClear - - - EP4_SEQ - [9:9] - read-write - oneToClear - - - EP4_TRANSACTION - [8:8] - read-write - oneToClear - - - EP3_SEQ - [7:7] - read-write - oneToClear - - - EP3_TRANSACTION - [6:6] - read-write - oneToClear - - - EP2_SEQ - [5:5] - read-write - oneToClear - - - EP2_TRANSACTION - [4:4] - read-write - oneToClear - - - EP1_SEQ - [3:3] - read-write - oneToClear - - - EP1_TRANSACTION - [2:2] - read-write - oneToClear - - - EP0_SEQ - [1:1] - read-write - oneToClear - - - EP0_TRANSACTION - [0:0] - read-write - oneToClear - - - - - DEV_SM_WATCHDOG - 0x00000114 - Watchdog that forces the device state machine to idle and raises an interrupt if the device stays in a state that isn't idle for the configured limit. The counter is reset on every state transition. - Set limit while enable is low and then set the enable. - 0x00000000 - - - FIRED - [20:20] - read-write - oneToClear - - - RESET - Set to 1 to forcibly reset the device state machine on watchdog expiry - [19:19] - read-write - - - ENABLE - [18:18] - read-write - - - LIMIT - [17:0] - read-write - - - - - - - TRNG - ARM TrustZone RNG register block - 0x400f0000 - - 0 - 492 - registers - - - TRNG_IRQ - 39 - - - - RNG_IMR - 0x00000100 - Interrupt masking. - 0x0000000f - - - RESERVED - RESERVED - [31:4] - read-only - - - VN_ERR_INT_MASK - 1'b1-mask interrupt, no interrupt will be generated. See RNG_ISR for an explanation on this interrupt. - [3:3] - read-write - - - CRNGT_ERR_INT_MASK - 1'b1-mask interrupt, no interrupt will be generated. See RNG_ISR for an explanation on this interrupt. - [2:2] - read-write - - - AUTOCORR_ERR_INT_MASK - 1'b1-mask interrupt, no interrupt will be generated. See RNG_ISR for an explanation on this interrupt. - [1:1] - read-write - - - EHR_VALID_INT_MASK - 1'b1-mask interrupt, no interrupt will be generated. See RNG_ISR for an explanation on this interrupt. - [0:0] - read-write - - - - - RNG_ISR - 0x00000104 - RNG status register. If corresponding RNG_IMR bit is unmasked, an interrupt will be generated. - 0x00000000 - - - RESERVED - RESERVED - [31:4] - read-only - - - VN_ERR - 1'b1 indicates Von Neuman error. Error in von Neuman occurs if 32 consecutive collected bits are identical, ZERO or ONE. - [3:3] - read-only - - - CRNGT_ERR - 1'b1 indicates CRNGT in the RNG test failed. Failure occurs when two consecutive blocks of 16 collected bits are equal. - [2:2] - read-only - - - AUTOCORR_ERR - 1'b1 indicates Autocorrelation test failed four times in a row. When set, RNG cease from functioning until next reset. - [1:1] - read-only - - - EHR_VALID - 1'b1 indicates that 192 bits have been collected in the RNG, and are ready to be read. - [0:0] - read-only - - - - - RNG_ICR - 0x00000108 - Interrupt/status bit clear Register. - 0x00000000 - - - RESERVED - RESERVED - [31:4] - read-only - - - VN_ERR - Write 1'b1 - clear corresponding bit in RNG_ISR. - [3:3] - read-write - - - CRNGT_ERR - Write 1'b1 - clear corresponding bit in RNG_ISR. - [2:2] - read-write - - - AUTOCORR_ERR - Cannot be cleared by SW! Only RNG reset clears this bit. - [1:1] - read-write - - - EHR_VALID - Write 1'b1 - clear corresponding bit in RNG_ISR. - [0:0] - read-write - - - - - TRNG_CONFIG - 0x0000010c - Selecting the inverter-chain length. - 0x00000000 - - - RESERVED - RESERVED - [31:2] - read-only - - - RND_SRC_SEL - Selects the number of inverters (out of four possible selections) in the ring oscillator (the entropy source). - [1:0] - read-write - - - - - TRNG_VALID - 0x00000110 - 192 bit collection indication. - 0x00000000 - - - RESERVED - RESERVED - [31:1] - read-only - - - EHR_VALID - 1'b1 indicates that collection of bits in the RNG is completed, and data can be read from EHR_DATA register. - [0:0] - read-only - - - - - EHR_DATA0 - 0x00000114 - RNG collected bits. - 0x00000000 - - - EHR_DATA0 - Bits [31:0] of Entropy Holding Register (EHR) - RNG output register - [31:0] - read-only - - - - - EHR_DATA1 - 0x00000118 - RNG collected bits. - 0x00000000 - - - EHR_DATA1 - Bits [63:32] of Entropy Holding Register (EHR) - RNG output register - [31:0] - read-only - - - - - EHR_DATA2 - 0x0000011c - RNG collected bits. - 0x00000000 - - - EHR_DATA2 - Bits [95:64] of Entropy Holding Register (EHR) - RNG output register - [31:0] - read-only - - - - - EHR_DATA3 - 0x00000120 - RNG collected bits. - 0x00000000 - - - EHR_DATA3 - Bits [127:96] of Entropy Holding Register (EHR) - RNG output register - [31:0] - read-only - - - - - EHR_DATA4 - 0x00000124 - RNG collected bits. - 0x00000000 - - - EHR_DATA4 - Bits [159:128] of Entropy Holding Register (EHR) - RNG output register - [31:0] - read-only - - - - - EHR_DATA5 - 0x00000128 - RNG collected bits. - 0x00000000 - - - EHR_DATA5 - Bits [191:160] of Entropy Holding Register (EHR) - RNG output register - [31:0] - read-only - - - - - RND_SOURCE_ENABLE - 0x0000012c - Enable signal for the random source. - 0x00000000 - - - RESERVED - RESERVED - [31:1] - read-only - - - RND_SRC_EN - * 1'b1 - entropy source is enabled. *1'b0 - entropy source is disabled - [0:0] - read-write - - - - - SAMPLE_CNT1 - 0x00000130 - Counts clocks between sampling of random bit. - 0x0000ffff - - - SAMPLE_CNTR1 - Sets the number of rng_clk cycles between two consecutive ring oscillator samples. Note! If the Von-Neuman is bypassed, the minimum value for sample counter must not be less then decimal seventeen - [31:0] - read-write - - - - - AUTOCORR_STATISTIC - 0x00000134 - Statistic about Autocorrelation test activations. - 0x00000000 - - - RESERVED - RESERVED - [31:22] - read-only - - - AUTOCORR_FAILS - Count each time an autocorrelation test fails. Any write to the register reset the counter. Stop collecting statistic if one of the counters reached the limit. - [21:14] - read-write - - - AUTOCORR_TRYS - Count each time an autocorrelation test starts. Any write to the register reset the counter. Stop collecting statistic if one of the counters reached the limit. - [13:0] - read-write - - - - - TRNG_DEBUG_CONTROL - 0x00000138 - Debug register. - 0x00000000 - - - AUTO_CORRELATE_BYPASS - When set, the autocorrelation test in the TRNG module is bypassed. - [3:3] - read-write - - - TRNG_CRNGT_BYPASS - When set, the CRNGT test in the RNG is bypassed. - [2:2] - read-write - - - VNC_BYPASS - When set, the Von-Neuman balancer is bypassed (including the 32 consecutive bits test). - [1:1] - read-write - - - RESERVED - N/A - [0:0] - read-only - - - - - TRNG_SW_RESET - 0x00000140 - Generate internal SW reset within the RNG block. - 0x00000000 - - - RESERVED - RESERVED - [31:1] - read-only - - - TRNG_SW_RESET - Writing 1'b1 to this register causes an internal RNG reset. - [0:0] - read-write - - - - - RNG_DEBUG_EN_INPUT - 0x000001b4 - Enable the RNG debug mode - 0x00000000 - - - RESERVED - RESERVED - [31:1] - read-only - - - RNG_DEBUG_EN - * 1'b1 - debug mode is enabled. *1'b0 - debug mode is disabled - [0:0] - read-write - - - - - TRNG_BUSY - 0x000001b8 - RNG Busy indication. - 0x00000000 - - - RESERVED - RESERVED - [31:1] - read-only - - - TRNG_BUSY - Reflects rng_busy status. - [0:0] - read-only - - - - - RST_BITS_COUNTER - 0x000001bc - Reset the counter of collected bits in the RNG. - 0x00000000 - - - RESERVED - RESERVED - [31:1] - read-only - - - RST_BITS_COUNTER - Writing any value to this address will reset the bits counter and RNG valid registers. RND_SORCE_ENABLE register must be unset in order for the reset to take place. - [0:0] - read-write - - - - - RNG_VERSION - 0x000001c0 - Displays the version settings of the TRNG. - 0x00000000 - - - RESERVED - RESERVED - [31:8] - read-only - - - RNG_USE_5_SBOXES - * 1'b1 - 5 SBOX AES. *1'b0 - 20 SBOX AES - [7:7] - read-only - - - RESEEDING_EXISTS - * 1'b1 - Exists. *1'b0 - Does not exist - [6:6] - read-only - - - KAT_EXISTS - * 1'b1 - Exists. *1'b0 - Does not exist - [5:5] - read-only - - - PRNG_EXISTS - * 1'b1 - Exists. *1'b0 - Does not exist - [4:4] - read-only - - - TRNG_TESTS_BYPASS_EN - * 1'b1 - Exists. *1'b0 - Does not exist - [3:3] - read-only - - - AUTOCORR_EXISTS - * 1'b1 - Exists. *1'b0 - Does not exist - [2:2] - read-only - - - CRNGT_EXISTS - * 1'b1 - Exists. *1'b0 - Does not exist - [1:1] - read-only - - - EHR_WIDTH_192 - * 1'b1 - 192-bit EHR. *1'b0 - 128-bit EHR - [0:0] - read-only - - - - - RNG_BIST_CNTR_0 - 0x000001e0 - Collected BIST results. - 0x00000000 - - - RESERVED - RESERVED - [31:22] - read-only - - - ROSC_CNTR_VAL - Reflects the results of RNG BIST counter. - [21:0] - read-only - - - - - RNG_BIST_CNTR_1 - 0x000001e4 - Collected BIST results. - 0x00000000 - - - RESERVED - RESERVED - [31:22] - read-only - - - ROSC_CNTR_VAL - Reflects the results of RNG BIST counter. - [21:0] - read-only - - - - - RNG_BIST_CNTR_2 - 0x000001e8 - Collected BIST results. - 0x00000000 - - - RESERVED - RESERVED - [31:22] - read-only - - - ROSC_CNTR_VAL - Reflects the results of RNG BIST counter. - [21:0] - read-only - - - - - - - GLITCH_DETECTOR - Glitch detector controls - 0x40158000 - - 0 - 24 - registers - - - - ARM - 0x00000000 - Forcibly arm the glitch detectors, if they are not already armed by OTP. When armed, any individual detector trigger will cause a restart of the switched core power domain's power-on reset state machine. - - Glitch detector triggers are recorded accumulatively in TRIG_STATUS. If the system is reset by a glitch detector trigger, this is recorded in POWMAN_CHIP_RESET. - - This register is Secure read/write only. - 0x00005bad - - - ARM - [15:0] - read-write - - - no - 23469 - Do not force the glitch detectors to be armed - - - yes - 0 - Force the glitch detectors to be armed. (Any value other than ARM_NO counts as YES) - - - - - - - DISARM - 0x00000004 - 0x00000000 - - - DISARM - Forcibly disarm the glitch detectors, if they are armed by OTP. Ignored if ARM is YES. - - This register is Secure read/write only. - [15:0] - read-write - - - no - 0 - Do not disarm the glitch detectors. (Any value other than DISARM_YES counts as NO) - - - yes - 56495 - Disarm the glitch detectors - - - - - - - SENSITIVITY - 0x00000008 - Adjust the sensitivity of glitch detectors to values other than their OTP-provided defaults. - - This register is Secure read/write only. - 0x00000000 - - - DEFAULT - [31:24] - read-write - - - yes - 0 - Use the default sensitivity configured in OTP for all detectors. (Any value other than DEFAULT_NO counts as YES) - - - no - 222 - Do not use the default sensitivity configured in OTP. Instead use the value from this register. - - - - - DET3_INV - Must be the inverse of DET3, else the default value is used. - [15:14] - read-write - - - DET2_INV - Must be the inverse of DET2, else the default value is used. - [13:12] - read-write - - - DET1_INV - Must be the inverse of DET1, else the default value is used. - [11:10] - read-write - - - DET0_INV - Must be the inverse of DET0, else the default value is used. - [9:8] - read-write - - - DET3 - Set sensitivity for detector 3. Higher values are more sensitive. - [7:6] - read-write - - - DET2 - Set sensitivity for detector 2. Higher values are more sensitive. - [5:4] - read-write - - - DET1 - Set sensitivity for detector 1. Higher values are more sensitive. - [3:2] - read-write - - - DET0 - Set sensitivity for detector 0. Higher values are more sensitive. - [1:0] - read-write - - - - - LOCK - 0x0000000c - 0x00000000 - - - LOCK - Write any nonzero value to disable writes to ARM, DISARM, SENSITIVITY and LOCK. This register is Secure read/write only. - [7:0] - read-write - - - - - TRIG_STATUS - 0x00000010 - Set when a detector output triggers. Write-1-clear. - - (May immediately return high if the detector remains in a failed state. Detectors can only be cleared by a full reset of the switched core power domain.) - - This register is Secure read/write only. - 0x00000000 - - - DET3 - [3:3] - read-write - oneToClear - - - DET2 - [2:2] - read-write - oneToClear - - - DET1 - [1:1] - read-write - oneToClear - - - DET0 - [0:0] - read-write - oneToClear - - - - - TRIG_FORCE - 0x00000014 - Simulate the firing of one or more detectors. Writing ones to this register will set the matching bits in STATUS_TRIG. - - If the glitch detectors are currently armed, writing ones will also immediately reset the switched core power domain, and set the reset reason latches in POWMAN_CHIP_RESET to indicate a glitch detector resets. - - This register is Secure read/write only. - 0x00000000 - - - TRIG_FORCE - [3:0] - write-only - - - - - - - OTP - SNPS OTP control IF (SBPI and RPi wrapper control) - 0x40120000 - - 0 - 372 - registers - - - OTP_IRQ - 38 - - - - SW_LOCK0 - 0x00000000 - Software lock register for page 0. - - Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. - 0x00000000 - - - NSEC - Non-secure lock status. Writes are OR'd with the current value. - [3:2] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - SEC - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. - [1:0] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - - - SW_LOCK1 - 0x00000004 - Software lock register for page 1. - - Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. - 0x00000000 - - - NSEC - Non-secure lock status. Writes are OR'd with the current value. - [3:2] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - SEC - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. - [1:0] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - - - SW_LOCK2 - 0x00000008 - Software lock register for page 2. - - Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. - 0x00000000 - - - NSEC - Non-secure lock status. Writes are OR'd with the current value. - [3:2] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - SEC - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. - [1:0] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - - - SW_LOCK3 - 0x0000000c - Software lock register for page 3. - - Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. - 0x00000000 - - - NSEC - Non-secure lock status. Writes are OR'd with the current value. - [3:2] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - SEC - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. - [1:0] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - - - SW_LOCK4 - 0x00000010 - Software lock register for page 4. - - Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. - 0x00000000 - - - NSEC - Non-secure lock status. Writes are OR'd with the current value. - [3:2] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - SEC - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. - [1:0] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - - - SW_LOCK5 - 0x00000014 - Software lock register for page 5. - - Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. - 0x00000000 - - - NSEC - Non-secure lock status. Writes are OR'd with the current value. - [3:2] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - SEC - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. - [1:0] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - - - SW_LOCK6 - 0x00000018 - Software lock register for page 6. - - Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. - 0x00000000 - - - NSEC - Non-secure lock status. Writes are OR'd with the current value. - [3:2] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - SEC - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. - [1:0] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - - - SW_LOCK7 - 0x0000001c - Software lock register for page 7. - - Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. - 0x00000000 - - - NSEC - Non-secure lock status. Writes are OR'd with the current value. - [3:2] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - SEC - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. - [1:0] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - - - SW_LOCK8 - 0x00000020 - Software lock register for page 8. - - Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. - 0x00000000 - - - NSEC - Non-secure lock status. Writes are OR'd with the current value. - [3:2] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - SEC - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. - [1:0] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - - - SW_LOCK9 - 0x00000024 - Software lock register for page 9. - - Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. - 0x00000000 - - - NSEC - Non-secure lock status. Writes are OR'd with the current value. - [3:2] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - SEC - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. - [1:0] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - - - SW_LOCK10 - 0x00000028 - Software lock register for page 10. - - Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. - 0x00000000 - - - NSEC - Non-secure lock status. Writes are OR'd with the current value. - [3:2] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - SEC - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. - [1:0] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - - - SW_LOCK11 - 0x0000002c - Software lock register for page 11. - - Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. - 0x00000000 - - - NSEC - Non-secure lock status. Writes are OR'd with the current value. - [3:2] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - SEC - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. - [1:0] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - - - SW_LOCK12 - 0x00000030 - Software lock register for page 12. - - Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. - 0x00000000 - - - NSEC - Non-secure lock status. Writes are OR'd with the current value. - [3:2] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - SEC - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. - [1:0] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - - - SW_LOCK13 - 0x00000034 - Software lock register for page 13. - - Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. - 0x00000000 - - - NSEC - Non-secure lock status. Writes are OR'd with the current value. - [3:2] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - SEC - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. - [1:0] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - - - SW_LOCK14 - 0x00000038 - Software lock register for page 14. - - Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. - 0x00000000 - - - NSEC - Non-secure lock status. Writes are OR'd with the current value. - [3:2] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - SEC - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. - [1:0] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - - - SW_LOCK15 - 0x0000003c - Software lock register for page 15. - - Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. - 0x00000000 - - - NSEC - Non-secure lock status. Writes are OR'd with the current value. - [3:2] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - SEC - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. - [1:0] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - - - SW_LOCK16 - 0x00000040 - Software lock register for page 16. - - Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. - 0x00000000 - - - NSEC - Non-secure lock status. Writes are OR'd with the current value. - [3:2] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - SEC - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. - [1:0] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - - - SW_LOCK17 - 0x00000044 - Software lock register for page 17. - - Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. - 0x00000000 - - - NSEC - Non-secure lock status. Writes are OR'd with the current value. - [3:2] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - SEC - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. - [1:0] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - - - SW_LOCK18 - 0x00000048 - Software lock register for page 18. - - Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. - 0x00000000 - - - NSEC - Non-secure lock status. Writes are OR'd with the current value. - [3:2] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - SEC - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. - [1:0] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - - - SW_LOCK19 - 0x0000004c - Software lock register for page 19. - - Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. - 0x00000000 - - - NSEC - Non-secure lock status. Writes are OR'd with the current value. - [3:2] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - SEC - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. - [1:0] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - - - SW_LOCK20 - 0x00000050 - Software lock register for page 20. - - Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. - 0x00000000 - - - NSEC - Non-secure lock status. Writes are OR'd with the current value. - [3:2] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - SEC - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. - [1:0] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - - - SW_LOCK21 - 0x00000054 - Software lock register for page 21. - - Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. - 0x00000000 - - - NSEC - Non-secure lock status. Writes are OR'd with the current value. - [3:2] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - SEC - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. - [1:0] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - - - SW_LOCK22 - 0x00000058 - Software lock register for page 22. - - Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. - 0x00000000 - - - NSEC - Non-secure lock status. Writes are OR'd with the current value. - [3:2] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - SEC - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. - [1:0] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - - - SW_LOCK23 - 0x0000005c - Software lock register for page 23. - - Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. - 0x00000000 - - - NSEC - Non-secure lock status. Writes are OR'd with the current value. - [3:2] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - SEC - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. - [1:0] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - - - SW_LOCK24 - 0x00000060 - Software lock register for page 24. - - Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. - 0x00000000 - - - NSEC - Non-secure lock status. Writes are OR'd with the current value. - [3:2] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - SEC - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. - [1:0] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - - - SW_LOCK25 - 0x00000064 - Software lock register for page 25. - - Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. - 0x00000000 - - - NSEC - Non-secure lock status. Writes are OR'd with the current value. - [3:2] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - SEC - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. - [1:0] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - - - SW_LOCK26 - 0x00000068 - Software lock register for page 26. - - Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. - 0x00000000 - - - NSEC - Non-secure lock status. Writes are OR'd with the current value. - [3:2] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - SEC - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. - [1:0] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - - - SW_LOCK27 - 0x0000006c - Software lock register for page 27. - - Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. - 0x00000000 - - - NSEC - Non-secure lock status. Writes are OR'd with the current value. - [3:2] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - SEC - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. - [1:0] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - - - SW_LOCK28 - 0x00000070 - Software lock register for page 28. - - Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. - 0x00000000 - - - NSEC - Non-secure lock status. Writes are OR'd with the current value. - [3:2] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - SEC - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. - [1:0] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - - - SW_LOCK29 - 0x00000074 - Software lock register for page 29. - - Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. - 0x00000000 - - - NSEC - Non-secure lock status. Writes are OR'd with the current value. - [3:2] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - SEC - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. - [1:0] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - - - SW_LOCK30 - 0x00000078 - Software lock register for page 30. - - Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. - 0x00000000 - - - NSEC - Non-secure lock status. Writes are OR'd with the current value. - [3:2] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - SEC - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. - [1:0] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - - - SW_LOCK31 - 0x0000007c - Software lock register for page 31. - - Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. - 0x00000000 - - - NSEC - Non-secure lock status. Writes are OR'd with the current value. - [3:2] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - SEC - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. - [1:0] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - - - SW_LOCK32 - 0x00000080 - Software lock register for page 32. - - Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. - 0x00000000 - - - NSEC - Non-secure lock status. Writes are OR'd with the current value. - [3:2] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - SEC - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. - [1:0] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - - - SW_LOCK33 - 0x00000084 - Software lock register for page 33. - - Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. - 0x00000000 - - - NSEC - Non-secure lock status. Writes are OR'd with the current value. - [3:2] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - SEC - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. - [1:0] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - - - SW_LOCK34 - 0x00000088 - Software lock register for page 34. - - Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. - 0x00000000 - - - NSEC - Non-secure lock status. Writes are OR'd with the current value. - [3:2] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - SEC - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. - [1:0] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - - - SW_LOCK35 - 0x0000008c - Software lock register for page 35. - - Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. - 0x00000000 - - - NSEC - Non-secure lock status. Writes are OR'd with the current value. - [3:2] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - SEC - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. - [1:0] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - - - SW_LOCK36 - 0x00000090 - Software lock register for page 36. - - Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. - 0x00000000 - - - NSEC - Non-secure lock status. Writes are OR'd with the current value. - [3:2] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - SEC - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. - [1:0] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - - - SW_LOCK37 - 0x00000094 - Software lock register for page 37. - - Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. - 0x00000000 - - - NSEC - Non-secure lock status. Writes are OR'd with the current value. - [3:2] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - SEC - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. - [1:0] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - - - SW_LOCK38 - 0x00000098 - Software lock register for page 38. - - Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. - 0x00000000 - - - NSEC - Non-secure lock status. Writes are OR'd with the current value. - [3:2] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - SEC - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. - [1:0] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - - - SW_LOCK39 - 0x0000009c - Software lock register for page 39. - - Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. - 0x00000000 - - - NSEC - Non-secure lock status. Writes are OR'd with the current value. - [3:2] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - SEC - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. - [1:0] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - - - SW_LOCK40 - 0x000000a0 - Software lock register for page 40. - - Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. - 0x00000000 - - - NSEC - Non-secure lock status. Writes are OR'd with the current value. - [3:2] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - SEC - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. - [1:0] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - - - SW_LOCK41 - 0x000000a4 - Software lock register for page 41. - - Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. - 0x00000000 - - - NSEC - Non-secure lock status. Writes are OR'd with the current value. - [3:2] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - SEC - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. - [1:0] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - - - SW_LOCK42 - 0x000000a8 - Software lock register for page 42. - - Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. - 0x00000000 - - - NSEC - Non-secure lock status. Writes are OR'd with the current value. - [3:2] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - SEC - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. - [1:0] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - - - SW_LOCK43 - 0x000000ac - Software lock register for page 43. - - Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. - 0x00000000 - - - NSEC - Non-secure lock status. Writes are OR'd with the current value. - [3:2] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - SEC - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. - [1:0] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - - - SW_LOCK44 - 0x000000b0 - Software lock register for page 44. - - Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. - 0x00000000 - - - NSEC - Non-secure lock status. Writes are OR'd with the current value. - [3:2] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - SEC - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. - [1:0] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - - - SW_LOCK45 - 0x000000b4 - Software lock register for page 45. - - Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. - 0x00000000 - - - NSEC - Non-secure lock status. Writes are OR'd with the current value. - [3:2] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - SEC - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. - [1:0] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - - - SW_LOCK46 - 0x000000b8 - Software lock register for page 46. - - Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. - 0x00000000 - - - NSEC - Non-secure lock status. Writes are OR'd with the current value. - [3:2] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - SEC - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. - [1:0] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - - - SW_LOCK47 - 0x000000bc - Software lock register for page 47. - - Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. - 0x00000000 - - - NSEC - Non-secure lock status. Writes are OR'd with the current value. - [3:2] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - SEC - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. - [1:0] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - - - SW_LOCK48 - 0x000000c0 - Software lock register for page 48. - - Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. - 0x00000000 - - - NSEC - Non-secure lock status. Writes are OR'd with the current value. - [3:2] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - SEC - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. - [1:0] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - - - SW_LOCK49 - 0x000000c4 - Software lock register for page 49. - - Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. - 0x00000000 - - - NSEC - Non-secure lock status. Writes are OR'd with the current value. - [3:2] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - SEC - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. - [1:0] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - - - SW_LOCK50 - 0x000000c8 - Software lock register for page 50. - - Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. - 0x00000000 - - - NSEC - Non-secure lock status. Writes are OR'd with the current value. - [3:2] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - SEC - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. - [1:0] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - - - SW_LOCK51 - 0x000000cc - Software lock register for page 51. - - Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. - 0x00000000 - - - NSEC - Non-secure lock status. Writes are OR'd with the current value. - [3:2] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - SEC - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. - [1:0] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - - - SW_LOCK52 - 0x000000d0 - Software lock register for page 52. - - Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. - 0x00000000 - - - NSEC - Non-secure lock status. Writes are OR'd with the current value. - [3:2] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - SEC - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. - [1:0] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - - - SW_LOCK53 - 0x000000d4 - Software lock register for page 53. - - Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. - 0x00000000 - - - NSEC - Non-secure lock status. Writes are OR'd with the current value. - [3:2] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - SEC - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. - [1:0] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - - - SW_LOCK54 - 0x000000d8 - Software lock register for page 54. - - Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. - 0x00000000 - - - NSEC - Non-secure lock status. Writes are OR'd with the current value. - [3:2] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - SEC - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. - [1:0] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - - - SW_LOCK55 - 0x000000dc - Software lock register for page 55. - - Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. - 0x00000000 - - - NSEC - Non-secure lock status. Writes are OR'd with the current value. - [3:2] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - SEC - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. - [1:0] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - - - SW_LOCK56 - 0x000000e0 - Software lock register for page 56. - - Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. - 0x00000000 - - - NSEC - Non-secure lock status. Writes are OR'd with the current value. - [3:2] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - SEC - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. - [1:0] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - - - SW_LOCK57 - 0x000000e4 - Software lock register for page 57. - - Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. - 0x00000000 - - - NSEC - Non-secure lock status. Writes are OR'd with the current value. - [3:2] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - SEC - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. - [1:0] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - - - SW_LOCK58 - 0x000000e8 - Software lock register for page 58. - - Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. - 0x00000000 - - - NSEC - Non-secure lock status. Writes are OR'd with the current value. - [3:2] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - SEC - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. - [1:0] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - - - SW_LOCK59 - 0x000000ec - Software lock register for page 59. - - Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. - 0x00000000 - - - NSEC - Non-secure lock status. Writes are OR'd with the current value. - [3:2] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - SEC - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. - [1:0] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - - - SW_LOCK60 - 0x000000f0 - Software lock register for page 60. - - Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. - 0x00000000 - - - NSEC - Non-secure lock status. Writes are OR'd with the current value. - [3:2] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - SEC - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. - [1:0] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - - - SW_LOCK61 - 0x000000f4 - Software lock register for page 61. - - Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. - 0x00000000 - - - NSEC - Non-secure lock status. Writes are OR'd with the current value. - [3:2] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - SEC - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. - [1:0] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - - - SW_LOCK62 - 0x000000f8 - Software lock register for page 62. - - Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. - 0x00000000 - - - NSEC - Non-secure lock status. Writes are OR'd with the current value. - [3:2] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - SEC - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. - [1:0] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - - - SW_LOCK63 - 0x000000fc - Software lock register for page 63. - - Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. - 0x00000000 - - - NSEC - Non-secure lock status. Writes are OR'd with the current value. - [3:2] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - SEC - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. - [1:0] - read-write - - - read_write - 0 - - - read_only - 1 - - - inaccessible - 3 - - - - - - - SBPI_INSTR - 0x00000100 - Dispatch instructions to the SBPI interface, used for programming the OTP fuses. - 0x00000000 - - - EXEC - Execute instruction - [30:30] - write-only - - - IS_WR - Payload type is write - [29:29] - read-write - - - HAS_PAYLOAD - Instruction has payload (data to be written or to be read) - [28:28] - read-write - - - PAYLOAD_SIZE_M1 - Instruction payload size in bytes minus 1 - [27:24] - read-write - - - TARGET - Instruction target, it can be PMC (0x3a) or DAP (0x02) - [23:16] - read-write - - - CMD - [15:8] - read-write - - - SHORT_WDATA - wdata to be used only when payload_size_m1=0 - [7:0] - read-write - - - - - SBPI_WDATA_0 - 0x00000104 - SBPI write payload bytes 3..0 - 0x00000000 - - - SBPI_WDATA_0 - [31:0] - read-write - - - - - SBPI_WDATA_1 - 0x00000108 - SBPI write payload bytes 7..4 - 0x00000000 - - - SBPI_WDATA_1 - [31:0] - read-write - - - - - SBPI_WDATA_2 - 0x0000010c - SBPI write payload bytes 11..8 - 0x00000000 - - - SBPI_WDATA_2 - [31:0] - read-write - - - - - SBPI_WDATA_3 - 0x00000110 - SBPI write payload bytes 15..12 - 0x00000000 - - - SBPI_WDATA_3 - [31:0] - read-write - - - - - SBPI_RDATA_0 - 0x00000114 - Read payload bytes 3..0. Once read, the data in the register will automatically clear to 0. - 0x00000000 - - - SBPI_RDATA_0 - [31:0] - read-only - modify - - - - - SBPI_RDATA_1 - 0x00000118 - Read payload bytes 7..4. Once read, the data in the register will automatically clear to 0. - 0x00000000 - - - SBPI_RDATA_1 - [31:0] - read-only - modify - - - - - SBPI_RDATA_2 - 0x0000011c - Read payload bytes 11..8. Once read, the data in the register will automatically clear to 0. - 0x00000000 - - - SBPI_RDATA_2 - [31:0] - read-only - modify - - - - - SBPI_RDATA_3 - 0x00000120 - Read payload bytes 15..12. Once read, the data in the register will automatically clear to 0. - 0x00000000 - - - SBPI_RDATA_3 - [31:0] - read-only - modify - - - - - SBPI_STATUS - 0x00000124 - 0x00000000 - - - MISO - SBPI MISO (master in - slave out): response from SBPI - [23:16] - read-only - - - FLAG - SBPI flag - [12:12] - read-only - - - INSTR_MISS - Last instruction missed (dropped), as the previous has not finished running - [8:8] - read-write - oneToClear - - - INSTR_DONE - Last instruction done - [4:4] - read-write - oneToClear - - - RDATA_VLD - Read command has returned data - [0:0] - read-write - oneToClear - - - - - USR - 0x00000128 - Controls for APB data read interface (USER interface) - 0x00000001 - - - PD - Power-down; 1 disables current reference. Must be 0 to read data from the OTP. - [4:4] - read-write - - - DCTRL - 1 enables USER interface; 0 disables USER interface (enables SBPI). - - This bit must be cleared before performing any SBPI access, such as when programming the OTP. The APB data read interface (USER interface) will be inaccessible during this time, and will return a bus error if any read is attempted. - [0:0] - read-write - - - - - DBG - 0x0000012c - Debug for OTP power-on state machine - 0x00000000 - - - CUSTOMER_RMA_FLAG - The chip is in RMA mode - [12:12] - read-only - - - PSM_STATE - Monitor the PSM FSM's state - [7:4] - read-only - - - ROSC_UP - Ring oscillator is up and running - [3:3] - read-only - - - ROSC_UP_SEEN - Ring oscillator was seen up and running - [2:2] - read-write - oneToClear - - - BOOT_DONE - PSM boot done status flag - [1:1] - read-only - - - PSM_DONE - PSM done status flag - [0:0] - read-only - - - - - BIST - 0x00000134 - During BIST, count address locations that have at least one leaky bit - 0x0fff0000 - - - CNT_FAIL - Flag if the count of address locations with at least one leaky bit exceeds cnt_max - [30:30] - read-only - - - CNT_CLR - Clear counter before use - [29:29] - write-only - - - CNT_ENA - Enable the counter before the BIST function is initiated - [28:28] - read-write - - - CNT_MAX - The cnt_fail flag will be set if the number of leaky locations exceeds this number - [27:16] - read-write - - - CNT - Number of locations that have at least one leaky bit. Note: This count is true only if the BIST was initiated without the fix option. - [12:0] - read-only - - - - - CRT_KEY_W0 - 0x00000138 - Word 0 (bits 31..0) of the key. Write only, read returns 0x0 - 0x00000000 - - - CRT_KEY_W0 - [31:0] - write-only - - - - - CRT_KEY_W1 - 0x0000013c - Word 1 (bits 63..32) of the key. Write only, read returns 0x0 - 0x00000000 - - - CRT_KEY_W1 - [31:0] - write-only - - - - - CRT_KEY_W2 - 0x00000140 - Word 2 (bits 95..64) of the key. Write only, read returns 0x0 - 0x00000000 - - - CRT_KEY_W2 - [31:0] - write-only - - - - - CRT_KEY_W3 - 0x00000144 - Word 3 (bits 127..96) of the key. Write only, read returns 0x0 - 0x00000000 - - - CRT_KEY_W3 - [31:0] - write-only - - - - - CRITICAL - 0x00000148 - Quickly check values of critical flags read during boot up - 0x00000000 - - - RISCV_DISABLE - [17:17] - read-only - - - ARM_DISABLE - [16:16] - read-only - - - GLITCH_DETECTOR_SENS - [6:5] - read-only - - - GLITCH_DETECTOR_ENABLE - [4:4] - read-only - - - DEFAULT_ARCHSEL - [3:3] - read-only - - - DEBUG_DISABLE - [2:2] - read-only - - - SECURE_DEBUG_DISABLE - [1:1] - read-only - - - SECURE_BOOT_ENABLE - [0:0] - read-only - - - - - KEY_VALID - 0x0000014c - Which keys were valid (enrolled) at boot time - 0x00000000 - - - KEY_VALID - [7:0] - read-only - - - - - DEBUGEN - 0x00000150 - Enable a debug feature that has been disabled. Debug features are disabled if one of the relevant critical boot flags is set in OTP (DEBUG_DISABLE or SECURE_DEBUG_DISABLE), OR if a debug key is marked valid in OTP, and the matching key value has not been supplied over SWD. - - Specifically: - - - The DEBUG_DISABLE flag disables all debug features. This can be fully overridden by setting all bits of this register. - - - The SECURE_DEBUG_DISABLE flag disables secure processor debug. This can be fully overridden by setting the PROC0_SECURE and PROC1_SECURE bits of this register. - - - If a single debug key has been registered, and no matching key value has been supplied over SWD, then all debug features are disabled. This can be fully overridden by setting all bits of this register. - - - If both debug keys have been registered, and the Non-secure key's value (key 6) has been supplied over SWD, secure processor debug is disabled. This can be fully overridden by setting the PROC0_SECURE and PROC1_SECURE bits of this register. - - - If both debug keys have been registered, and the Secure key's value (key 5) has been supplied over SWD, then no debug features are disabled by the key mechanism. However, note that in this case debug features may still be disabled by the critical boot flags. - 0x00000000 - - - MISC - Enable other debug components. Specifically, the CTI, and the APB-AP used to access the RISC-V Debug Module. - - These components are disabled by default if either of the debug disable critical flags is set, or if at least one debug key has been enrolled and the least secure of these enrolled key values has not been provided over SWD. - [8:8] - read-write - - - PROC1_SECURE - Permit core 1's Mem-AP to generate Secure accesses, assuming it is enabled at all. Also enable secure debug of core 1 (SPIDEN and SPNIDEN). - - Secure debug of core 1 is disabled by default if the secure debug disable critical flag is set, or if at least one debug key has been enrolled and the most secure of these enrolled key values not yet provided over SWD. - [3:3] - read-write - - - PROC1 - Enable core 1's Mem-AP if it is currently disabled. - - The Mem-AP is disabled by default if either of the debug disable critical flags is set, or if at least one debug key has been enrolled and the least secure of these enrolled key values has not been provided over SWD. - [2:2] - read-write - - - PROC0_SECURE - Permit core 0's Mem-AP to generate Secure accesses, assuming it is enabled at all. Also enable secure debug of core 0 (SPIDEN and SPNIDEN). - - Secure debug of core 0 is disabled by default if the secure debug disable critical flag is set, or if at least one debug key has been enrolled and the most secure of these enrolled key values not yet provided over SWD. - - Note also that core Mem-APs are unconditionally disabled when a core is switched to RISC-V mode (by setting the ARCHSEL bit and performing a warm reset of the core). - [1:1] - read-write - - - PROC0 - Enable core 0's Mem-AP if it is currently disabled. - - The Mem-AP is disabled by default if either of the debug disable critical flags is set, or if at least one debug key has been enrolled and the least secure of these enrolled key values has not been provided over SWD. - - Note also that core Mem-APs are unconditionally disabled when a core is switched to RISC-V mode (by setting the ARCHSEL bit and performing a warm reset of the core). - [0:0] - read-write - - - - - DEBUGEN_LOCK - 0x00000154 - Write 1s to lock corresponding bits in DEBUGEN. This register is reset by the processor cold reset. - 0x00000000 - - - MISC - Write 1 to lock the MISC bit of DEBUGEN. Can't be cleared once set. - [8:8] - read-write - - - PROC1_SECURE - Write 1 to lock the PROC1_SECURE bit of DEBUGEN. Can't be cleared once set. - [3:3] - read-write - - - PROC1 - Write 1 to lock the PROC1 bit of DEBUGEN. Can't be cleared once set. - [2:2] - read-write - - - PROC0_SECURE - Write 1 to lock the PROC0_SECURE bit of DEBUGEN. Can't be cleared once set. - [1:1] - read-write - - - PROC0 - Write 1 to lock the PROC0 bit of DEBUGEN. Can't be cleared once set. - [0:0] - read-write - - - - - ARCHSEL - 0x00000158 - Architecture select (Arm/RISC-V). The default and allowable values of this register are constrained by the critical boot flags. - - This register is reset by the earliest reset in the switched core power domain (before a processor cold reset). - - Cores sample their architecture select signal on a warm reset. The source of the warm reset could be the system power-up state machine, the watchdog timer, Arm SYSRESETREQ or from RISC-V hartresetreq. - - Note that when an Arm core is deselected, its cold reset domain is also held in reset, since in particular the SYSRESETREQ bit becomes inaccessible once the core is deselected. Note also the RISC-V cores do not have a cold reset domain, since their corresponding controls are located in the Debug Module. - 0x00000000 - - - CORE1 - Select architecture for core 1. - [1:1] - read-write - - - arm - 0 - Switch core 1 to Arm (Cortex-M33) - - - riscv - 1 - Switch core 1 to RISC-V (Hazard3) - - - - - CORE0 - Select architecture for core 0. - [0:0] - read-write - - - arm - 0 - Switch core 0 to Arm (Cortex-M33) - - - riscv - 1 - Switch core 0 to RISC-V (Hazard3) - - - - - - - ARCHSEL_STATUS - 0x0000015c - Get the current architecture select state of each core. Cores sample the current value of the ARCHSEL register when their warm reset is released, at which point the corresponding bit in this register will also update. - 0x00000000 - - - CORE1 - Current architecture for core 0. Updated on processor warm reset. - [1:1] - read-only - - - arm - 0 - Core 1 is currently Arm (Cortex-M33) - - - riscv - 1 - Core 1 is currently RISC-V (Hazard3) - - - - - CORE0 - Current architecture for core 0. Updated on processor warm reset. - [0:0] - read-only - - - arm - 0 - Core 0 is currently Arm (Cortex-M33) - - - riscv - 1 - Core 0 is currently RISC-V (Hazard3) - - - - - - - BOOTDIS - 0x00000160 - Tell the bootrom to ignore scratch register boot vectors (both power manager and watchdog) on the next power up. - - If an early boot stage has soft-locked some OTP pages in order to protect their contents from later stages, there is a risk that Secure code running at a later stage can unlock the pages by performing a watchdog reset that resets the OTP. - - This register can be used to ensure that the bootloader runs as normal on the next power up, preventing Secure code at a later stage from accessing OTP in its unlocked state. - - Should be used in conjunction with the power manager BOOTDIS register. - 0x00000000 - - - NEXT - This flag always ORs writes into its current contents. It can be set but not cleared by software. - - The BOOTDIS_NEXT bit is OR'd into the BOOTDIS_NOW bit when the core is powered down. Simultaneously, the BOOTDIS_NEXT bit is cleared. Setting this bit means that the boot scratch registers will be ignored following the next core power down. - - This flag should be set by an early boot stage that has soft-locked OTP pages, to prevent later stages from unlocking it via watchdog reset. - [1:1] - read-write - - - NOW - When the core is powered down, the current value of BOOTDIS_NEXT is OR'd into BOOTDIS_NOW, and BOOTDIS_NEXT is cleared. - - The bootrom checks this flag before reading the boot scratch registers. If it is set, the bootrom clears it, and ignores the BOOT registers. This prevents Secure software from diverting the boot path before a bootloader has had the chance to soft lock OTP pages containing sensitive data. - [0:0] - read-write - oneToClear - - - - - INTR - 0x00000164 - Raw Interrupts - 0x00000000 - - - APB_RD_NSEC_FAIL - [4:4] - read-write - oneToClear - - - APB_RD_SEC_FAIL - [3:3] - read-write - oneToClear - - - APB_DCTRL_FAIL - [2:2] - read-write - oneToClear - - - SBPI_WR_FAIL - [1:1] - read-write - oneToClear - - - SBPI_FLAG_N - [0:0] - read-only - - - - - INTE - 0x00000168 - Interrupt Enable - 0x00000000 - - - APB_RD_NSEC_FAIL - [4:4] - read-write - - - APB_RD_SEC_FAIL - [3:3] - read-write - - - APB_DCTRL_FAIL - [2:2] - read-write - - - SBPI_WR_FAIL - [1:1] - read-write - - - SBPI_FLAG_N - [0:0] - read-write - - - - - INTF - 0x0000016c - Interrupt Force - 0x00000000 - - - APB_RD_NSEC_FAIL - [4:4] - read-write - - - APB_RD_SEC_FAIL - [3:3] - read-write - - - APB_DCTRL_FAIL - [2:2] - read-write - - - SBPI_WR_FAIL - [1:1] - read-write - - - SBPI_FLAG_N - [0:0] - read-write - - - - - INTS - 0x00000170 - Interrupt status after masking & forcing - 0x00000000 - - - APB_RD_NSEC_FAIL - [4:4] - read-only - - - APB_RD_SEC_FAIL - [3:3] - read-only - - - APB_DCTRL_FAIL - [2:2] - read-only - - - SBPI_WR_FAIL - [1:1] - read-only - - - SBPI_FLAG_N - [0:0] - read-only - - - - - - - OTP_DATA - Predefined OTP data layout for RP2350 - 0x40130000 - - 0 - 7920 - registers - - - - CHIPID0 - 0x0000 - Bits 15:0 of public device ID. (ECC) - - The CHIPID0..3 rows contain a 64-bit random identifier for this chip, which can be read from the USB bootloader PICOBOOT interface or from the get_sys_info ROM API. - - The number of random bits makes the occurrence of twins exceedingly unlikely: for example, a fleet of a hundred million devices has a 99.97% probability of no twinned IDs. This is estimated to be lower than the occurrence of process errors in the assignment of sequential random IDs, and for practical purposes CHIPID may be treated as unique. - 16 - 0x0000 - - - CHIPID0 - [15:0] - read-only - - - - - CHIPID1 - 0x0002 - Bits 31:16 of public device ID (ECC) - 16 - 0x0000 - - - CHIPID1 - [15:0] - read-only - - - - - CHIPID2 - 0x0004 - Bits 47:32 of public device ID (ECC) - 16 - 0x0000 - - - CHIPID2 - [15:0] - read-only - - - - - CHIPID3 - 0x0006 - Bits 63:48 of public device ID (ECC) - 16 - 0x0000 - - - CHIPID3 - [15:0] - read-only - - - - - RANDID0 - 0x0008 - Bits 15:0 of private per-device random number (ECC) - - The RANDID0..7 rows form a 128-bit random number generated during device test. - - This ID is not exposed through the USB PICOBOOT GET_INFO command or the ROM `get_sys_info()` API. However note that the USB PICOBOOT OTP access point can read the entirety of page 0, so this value is not meaningfully private unless the USB PICOBOOT interface is disabled via the DISABLE_BOOTSEL_USB_PICOBOOT_IFC flag in BOOT_FLAGS0. - 16 - 0x0000 - - - RANDID0 - [15:0] - read-only - - - - - RANDID1 - 0x000a - Bits 31:16 of private per-device random number (ECC) - 16 - 0x0000 - - - RANDID1 - [15:0] - read-only - - - - - RANDID2 - 0x000c - Bits 47:32 of private per-device random number (ECC) - 16 - 0x0000 - - - RANDID2 - [15:0] - read-only - - - - - RANDID3 - 0x000e - Bits 63:48 of private per-device random number (ECC) - 16 - 0x0000 - - - RANDID3 - [15:0] - read-only - - - - - RANDID4 - 0x0010 - Bits 79:64 of private per-device random number (ECC) - 16 - 0x0000 - - - RANDID4 - [15:0] - read-only - - - - - RANDID5 - 0x0012 - Bits 95:80 of private per-device random number (ECC) - 16 - 0x0000 - - - RANDID5 - [15:0] - read-only - - - - - RANDID6 - 0x0014 - Bits 111:96 of private per-device random number (ECC) - 16 - 0x0000 - - - RANDID6 - [15:0] - read-only - - - - - RANDID7 - 0x0016 - Bits 127:112 of private per-device random number (ECC) - 16 - 0x0000 - - - RANDID7 - [15:0] - read-only - - - - - ROSC_CALIB - 0x0020 - Ring oscillator frequency in kHz, measured during manufacturing (ECC) - - This is measured at 1.1 V, at room temperature, with the ROSC configuration registers in their reset state. - 16 - 0x0000 - - - ROSC_CALIB - [15:0] - read-only - - - - - LPOSC_CALIB - 0x0022 - Low-power oscillator frequency in Hz, measured during manufacturing (ECC) - - This is measured at 1.1V, at room temperature, with the LPOSC trim register in its reset state. - 16 - 0x0000 - - - LPOSC_CALIB - [15:0] - read-only - - - - - NUM_GPIOS - 0x0030 - The number of main user GPIOs (bank 0). Should read 48 in the QFN80 package, and 30 in the QFN60 package. (ECC) - 16 - 0x0000 - - - NUM_GPIOS - [7:0] - read-only - - - - - INFO_CRC0 - 0x006c - Lower 16 bits of CRC32 of OTP addresses 0x00 through 0x6b (polynomial 0x4c11db7, input reflected, output reflected, seed all-ones, final XOR all-ones) (ECC) - 16 - 0x0000 - - - INFO_CRC0 - [15:0] - read-only - - - - - INFO_CRC1 - 0x006e - Upper 16 bits of CRC32 of OTP addresses 0x00 through 0x6b (ECC) - 16 - 0x0000 - - - INFO_CRC1 - [15:0] - read-only - - - - - FLASH_DEVINFO - 0x00a8 - Stores information about external flash device(s). (ECC) - - Assumed to be valid if BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is set. - 16 - 0x0000 - - - CS1_SIZE - The size of the flash/PSRAM device on chip select 1 (addressable at 0x11000000 through 0x11ffffff). - - A value of zero is decoded as a size of zero (no device). Nonzero values are decoded as 4kiB << CS1_SIZE. For example, four megabytes is encoded with a CS1_SIZE value of 10, and 16 megabytes is encoded with a CS1_SIZE value of 12. - - When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, a default of zero is used. - [15:12] - read-only - - - NONE - 0 - - - 8K - 1 - - - 16K - 2 - - - 32K - 3 - - - 64k - 4 - - - 128K - 5 - - - 256K - 6 - - - 512K - 7 - - - 1M - 8 - - - 2M - 9 - - - 4M - 10 - - - 8M - 11 - - - 16M - 12 - - - - - CS0_SIZE - The size of the flash/PSRAM device on chip select 0 (addressable at 0x10000000 through 0x10ffffff). - - A value of zero is decoded as a size of zero (no device). Nonzero values are decoded as 4kiB << CS0_SIZE. For example, four megabytes is encoded with a CS0_SIZE value of 10, and 16 megabytes is encoded with a CS0_SIZE value of 12. - - When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, a default of 12 (16 MiB) is used. - [11:8] - read-only - - - NONE - 0 - - - 8K - 1 - - - 16K - 2 - - - 32K - 3 - - - 64k - 4 - - - 128K - 5 - - - 256K - 6 - - - 512K - 7 - - - 1M - 8 - - - 2M - 9 - - - 4M - 10 - - - 8M - 11 - - - 16M - 12 - - - - - D8H_ERASE_SUPPORTED - If true, all attached devices are assumed to support (or ignore, in the case of PSRAM) a block erase command with a command prefix of D8h, an erase size of 64 kiB, and a 24-bit address. Almost all 25-series flash devices support this command. - - If set, the bootrom will use the D8h erase command where it is able, to accelerate bulk erase operations. This makes flash programming faster. - - When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, this field defaults to false. - [7:7] - read-only - - - CS1_GPIO - Indicate a GPIO number to be used for the secondary flash chip select (CS1), which selects the external QSPI device mapped at system addresses 0x11000000 through 0x11ffffff. There is no such configuration for CS0, as the primary chip select has a dedicated pin. - - On RP2350 the permissible GPIO numbers are 0, 8, 19 and 47. - - Ignored if CS1_size is zero. If CS1_SIZE is nonzero, the bootrom will automatically configure this GPIO as a second chip select upon entering the flash boot path, or entering any other path that may use the QSPI flash interface, such as BOOTSEL mode (nsboot). - [5:0] - read-only - - - - - FLASH_PARTITION_SLOT_SIZE - 0x00aa - Gap between partition table slot 0 and slot 1 at the start of flash (the default size is 4096 bytes) (ECC) Enabled by the OVERRIDE_FLASH_PARTITION_SLOT_SIZE bit in BOOT_FLAGS, the size is 4096 * (value + 1) - 16 - 0x0000 - - - FLASH_PARTITION_SLOT_SIZE - [15:0] - read-only - - - - - BOOTSEL_LED_CFG - 0x00ac - Pin configuration for LED status, used by USB bootloader. (ECC) - Must be valid if BOOT_FLAGS0_ENABLE_BOOTSEL_LED is set. - 16 - 0x0000 - - - ACTIVELOW - LED is active-low. (Default: active-high.) - [8:8] - read-only - - - PIN - GPIO index to use for bootloader activity LED. - [5:0] - read-only - - - - - BOOTSEL_PLL_CFG - 0x00ae - Optional PLL configuration for BOOTSEL mode. (ECC) - - This should be configured to produce an exact 48 MHz based on the crystal oscillator frequency. User mode software may also use this value to calculate the expected crystal frequency based on an assumed 48 MHz PLL output. - - If no configuration is given, the crystal is assumed to be 12 MHz. - - The PLL frequency can be calculated as: - - PLL out = (XOSC frequency / (REFDIV+1)) x FBDIV / (POSTDIV1 x POSTDIV2) - - Conversely the crystal frequency can be calculated as: - - XOSC frequency = 48 MHz x (REFDIV+1) x (POSTDIV1 x POSTDIV2) / FBDIV - - (Note the +1 on REFDIV is because the value stored in this OTP location is the actual divisor value minus one.) - - Used if and only if ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG is set in BOOT_FLAGS0. That bit should be set only after this row and BOOTSEL_XOSC_CFG are both correctly programmed. - 16 - 0x0000 - - - REFDIV - PLL reference divisor, minus one. - - Programming a value of 0 means a reference divisor of 1. Programming a value of 1 means a reference divisor of 2 (for exceptionally fast XIN inputs) - [15:15] - read-only - - - POSTDIV2 - PLL post-divide 2 divisor, in the range 1..7 inclusive. - [14:12] - read-only - - - POSTDIV1 - PLL post-divide 1 divisor, in the range 1..7 inclusive. - [11:9] - read-only - - - FBDIV - PLL feedback divisor, in the range 16..320 inclusive. - [8:0] - read-only - - - - - BOOTSEL_XOSC_CFG - 0x00b0 - Non-default crystal oscillator configuration for the USB bootloader. (ECC) - - These values may also be used by user code configuring the crystal oscillator. - - Used if and only if ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG is set in BOOT_FLAGS0. That bit should be set only after this row and BOOTSEL_PLL_CFG are both correctly programmed. - 16 - 0x0000 - - - RANGE - Value of the XOSC_CTRL_FREQ_RANGE register. - [15:14] - read-only - - - 1_15MHZ - 0 - - - 10_30MHZ - 1 - - - 25_60MHZ - 2 - - - 40_100MHZ - 3 - - - - - STARTUP - Value of the XOSC_STARTUP register - [13:0] - read-only - - - - - USB_WHITE_LABEL_ADDR - 0x00b8 - Row index of the USB_WHITE_LABEL structure within OTP (ECC) - - The table has 16 rows, each of which are also ECC and marked valid by the corresponding valid bit in USB_BOOT_FLAGS (ECC). - - The entries are either _VALUEs where the 16 bit value is used as is, or _STRDEFs which acts as a pointers to a string value. - - The value stored in a _STRDEF is two separate bytes: The low seven bits of the first (LSB) byte indicates the number of characters in the string, and the top bit of the first (LSB) byte if set to indicate that each character in the string is two bytes (Unicode) versus one byte if unset. The second (MSB) byte represents the location of the string data, and is encoded as the number of rows from this USB_WHITE_LABEL_ADDR; i.e. the row of the start of the string is USB_WHITE_LABEL_ADDR value + msb_byte. - - In each case, the corresponding valid bit enables replacing the default value for the corresponding item provided by the boot rom. - - Note that Unicode _STRDEFs are only supported for USB_DEVICE_PRODUCT_STRDEF, USB_DEVICE_SERIAL_NUMBER_STRDEF and USB_DEVICE_MANUFACTURER_STRDEF. Unicode values will be ignored if specified for other fields, and non-unicode values for these three items will be converted to Unicode characters by setting the upper 8 bits to zero. - - Note that if the USB_WHITE_LABEL structure or the corresponding strings are not readable by BOOTSEL mode based on OTP permissions, or if alignment requirements are not met, then the corresponding default values are used. - - The index values indicate where each field is located (row USB_WHITE_LABEL_ADDR value + index): - 16 - 0x0000 - - - USB_WHITE_LABEL_ADDR - [15:0] - read-only - - - INDEX_USB_DEVICE_VID_VALUE - 0 - - - INDEX_USB_DEVICE_PID_VALUE - 1 - - - INDEX_USB_DEVICE_BCD_DEVICE_VALUE - 2 - - - INDEX_USB_DEVICE_LANG_ID_VALUE - 3 - - - INDEX_USB_DEVICE_MANUFACTURER_STRDEF - 4 - - - INDEX_USB_DEVICE_PRODUCT_STRDEF - 5 - - - INDEX_USB_DEVICE_SERIAL_NUMBER_STRDEF - 6 - - - INDEX_USB_CONFIG_ATTRIBUTES_MAX_POWER_VALUES - 7 - - - INDEX_VOLUME_LABEL_STRDEF - 8 - - - INDEX_SCSI_INQUIRY_VENDOR_STRDEF - 9 - - - INDEX_SCSI_INQUIRY_PRODUCT_STRDEF - 10 - - - INDEX_SCSI_INQUIRY_VERSION_STRDEF - 11 - - - INDEX_INDEX_HTM_REDIRECT_URL_STRDEF - 12 - - - INDEX_INDEX_HTM_REDIRECT_NAME_STRDEF - 13 - - - INDEX_INFO_UF2_TXT_MODEL_STRDEF - 14 - - - INDEX_INFO_UF2_TXT_BOARD_ID_STRDEF - 15 - - - - - - - OTPBOOT_SRC - 0x00bc - OTP start row for the OTP boot image. (ECC) - - If OTP boot is enabled, the bootrom will load from this location into SRAM and then directly enter the loaded image. Note that the image must be signed if SECURE_BOOT_ENABLE is set. The image itself is assumed to be ECC-protected. - - This must be an even number. Equivalently, the OTP boot image must start at a word-aligned location in the ECC read data address window. - 16 - 0x0000 - - - OTPBOOT_SRC - [15:0] - read-only - - - - - OTPBOOT_LEN - 0x00be - Length in rows of the OTP boot image. (ECC) - - OTPBOOT_LEN must be even. The total image size must be a multiple of 4 bytes (32 bits). - 16 - 0x0000 - - - OTPBOOT_LEN - [15:0] - read-only - - - - - OTPBOOT_DST0 - 0x00c0 - Bits 15:0 of the OTP boot image load destination (and entry point). (ECC) - - This must be a location in main SRAM (main SRAM is addresses 0x20000000 through 0x20082000) and must be word-aligned. - 16 - 0x0000 - - - OTPBOOT_DST0 - [15:0] - read-only - - - - - OTPBOOT_DST1 - 0x00c2 - Bits 31:16 of the OTP boot image load destination (and entry point). (ECC) - - This must be a location in main SRAM (main SRAM is addresses 0x20000000 through 0x20082000) and must be word-aligned. - 16 - 0x0000 - - - OTPBOOT_DST1 - [15:0] - read-only - - - - - BOOTKEY0_0 - 0x0100 - Bits 15:0 of SHA-256 hash of boot key 0 (ECC) - 16 - 0x0000 - - - BOOTKEY0_0 - [15:0] - read-only - - - - - BOOTKEY0_1 - 0x0102 - Bits 31:16 of SHA-256 hash of boot key 0 (ECC) - 16 - 0x0000 - - - BOOTKEY0_1 - [15:0] - read-only - - - - - BOOTKEY0_2 - 0x0104 - Bits 47:32 of SHA-256 hash of boot key 0 (ECC) - 16 - 0x0000 - - - BOOTKEY0_2 - [15:0] - read-only - - - - - BOOTKEY0_3 - 0x0106 - Bits 63:48 of SHA-256 hash of boot key 0 (ECC) - 16 - 0x0000 - - - BOOTKEY0_3 - [15:0] - read-only - - - - - BOOTKEY0_4 - 0x0108 - Bits 79:64 of SHA-256 hash of boot key 0 (ECC) - 16 - 0x0000 - - - BOOTKEY0_4 - [15:0] - read-only - - - - - BOOTKEY0_5 - 0x010a - Bits 95:80 of SHA-256 hash of boot key 0 (ECC) - 16 - 0x0000 - - - BOOTKEY0_5 - [15:0] - read-only - - - - - BOOTKEY0_6 - 0x010c - Bits 111:96 of SHA-256 hash of boot key 0 (ECC) - 16 - 0x0000 - - - BOOTKEY0_6 - [15:0] - read-only - - - - - BOOTKEY0_7 - 0x010e - Bits 127:112 of SHA-256 hash of boot key 0 (ECC) - 16 - 0x0000 - - - BOOTKEY0_7 - [15:0] - read-only - - - - - BOOTKEY0_8 - 0x0110 - Bits 143:128 of SHA-256 hash of boot key 0 (ECC) - 16 - 0x0000 - - - BOOTKEY0_8 - [15:0] - read-only - - - - - BOOTKEY0_9 - 0x0112 - Bits 159:144 of SHA-256 hash of boot key 0 (ECC) - 16 - 0x0000 - - - BOOTKEY0_9 - [15:0] - read-only - - - - - BOOTKEY0_10 - 0x0114 - Bits 175:160 of SHA-256 hash of boot key 0 (ECC) - 16 - 0x0000 - - - BOOTKEY0_10 - [15:0] - read-only - - - - - BOOTKEY0_11 - 0x0116 - Bits 191:176 of SHA-256 hash of boot key 0 (ECC) - 16 - 0x0000 - - - BOOTKEY0_11 - [15:0] - read-only - - - - - BOOTKEY0_12 - 0x0118 - Bits 207:192 of SHA-256 hash of boot key 0 (ECC) - 16 - 0x0000 - - - BOOTKEY0_12 - [15:0] - read-only - - - - - BOOTKEY0_13 - 0x011a - Bits 223:208 of SHA-256 hash of boot key 0 (ECC) - 16 - 0x0000 - - - BOOTKEY0_13 - [15:0] - read-only - - - - - BOOTKEY0_14 - 0x011c - Bits 239:224 of SHA-256 hash of boot key 0 (ECC) - 16 - 0x0000 - - - BOOTKEY0_14 - [15:0] - read-only - - - - - BOOTKEY0_15 - 0x011e - Bits 255:240 of SHA-256 hash of boot key 0 (ECC) - 16 - 0x0000 - - - BOOTKEY0_15 - [15:0] - read-only - - - - - BOOTKEY1_0 - 0x0120 - Bits 15:0 of SHA-256 hash of boot key 1 (ECC) - 16 - 0x0000 - - - BOOTKEY1_0 - [15:0] - read-only - - - - - BOOTKEY1_1 - 0x0122 - Bits 31:16 of SHA-256 hash of boot key 1 (ECC) - 16 - 0x0000 - - - BOOTKEY1_1 - [15:0] - read-only - - - - - BOOTKEY1_2 - 0x0124 - Bits 47:32 of SHA-256 hash of boot key 1 (ECC) - 16 - 0x0000 - - - BOOTKEY1_2 - [15:0] - read-only - - - - - BOOTKEY1_3 - 0x0126 - Bits 63:48 of SHA-256 hash of boot key 1 (ECC) - 16 - 0x0000 - - - BOOTKEY1_3 - [15:0] - read-only - - - - - BOOTKEY1_4 - 0x0128 - Bits 79:64 of SHA-256 hash of boot key 1 (ECC) - 16 - 0x0000 - - - BOOTKEY1_4 - [15:0] - read-only - - - - - BOOTKEY1_5 - 0x012a - Bits 95:80 of SHA-256 hash of boot key 1 (ECC) - 16 - 0x0000 - - - BOOTKEY1_5 - [15:0] - read-only - - - - - BOOTKEY1_6 - 0x012c - Bits 111:96 of SHA-256 hash of boot key 1 (ECC) - 16 - 0x0000 - - - BOOTKEY1_6 - [15:0] - read-only - - - - - BOOTKEY1_7 - 0x012e - Bits 127:112 of SHA-256 hash of boot key 1 (ECC) - 16 - 0x0000 - - - BOOTKEY1_7 - [15:0] - read-only - - - - - BOOTKEY1_8 - 0x0130 - Bits 143:128 of SHA-256 hash of boot key 1 (ECC) - 16 - 0x0000 - - - BOOTKEY1_8 - [15:0] - read-only - - - - - BOOTKEY1_9 - 0x0132 - Bits 159:144 of SHA-256 hash of boot key 1 (ECC) - 16 - 0x0000 - - - BOOTKEY1_9 - [15:0] - read-only - - - - - BOOTKEY1_10 - 0x0134 - Bits 175:160 of SHA-256 hash of boot key 1 (ECC) - 16 - 0x0000 - - - BOOTKEY1_10 - [15:0] - read-only - - - - - BOOTKEY1_11 - 0x0136 - Bits 191:176 of SHA-256 hash of boot key 1 (ECC) - 16 - 0x0000 - - - BOOTKEY1_11 - [15:0] - read-only - - - - - BOOTKEY1_12 - 0x0138 - Bits 207:192 of SHA-256 hash of boot key 1 (ECC) - 16 - 0x0000 - - - BOOTKEY1_12 - [15:0] - read-only - - - - - BOOTKEY1_13 - 0x013a - Bits 223:208 of SHA-256 hash of boot key 1 (ECC) - 16 - 0x0000 - - - BOOTKEY1_13 - [15:0] - read-only - - - - - BOOTKEY1_14 - 0x013c - Bits 239:224 of SHA-256 hash of boot key 1 (ECC) - 16 - 0x0000 - - - BOOTKEY1_14 - [15:0] - read-only - - - - - BOOTKEY1_15 - 0x013e - Bits 255:240 of SHA-256 hash of boot key 1 (ECC) - 16 - 0x0000 - - - BOOTKEY1_15 - [15:0] - read-only - - - - - BOOTKEY2_0 - 0x0140 - Bits 15:0 of SHA-256 hash of boot key 2 (ECC) - 16 - 0x0000 - - - BOOTKEY2_0 - [15:0] - read-only - - - - - BOOTKEY2_1 - 0x0142 - Bits 31:16 of SHA-256 hash of boot key 2 (ECC) - 16 - 0x0000 - - - BOOTKEY2_1 - [15:0] - read-only - - - - - BOOTKEY2_2 - 0x0144 - Bits 47:32 of SHA-256 hash of boot key 2 (ECC) - 16 - 0x0000 - - - BOOTKEY2_2 - [15:0] - read-only - - - - - BOOTKEY2_3 - 0x0146 - Bits 63:48 of SHA-256 hash of boot key 2 (ECC) - 16 - 0x0000 - - - BOOTKEY2_3 - [15:0] - read-only - - - - - BOOTKEY2_4 - 0x0148 - Bits 79:64 of SHA-256 hash of boot key 2 (ECC) - 16 - 0x0000 - - - BOOTKEY2_4 - [15:0] - read-only - - - - - BOOTKEY2_5 - 0x014a - Bits 95:80 of SHA-256 hash of boot key 2 (ECC) - 16 - 0x0000 - - - BOOTKEY2_5 - [15:0] - read-only - - - - - BOOTKEY2_6 - 0x014c - Bits 111:96 of SHA-256 hash of boot key 2 (ECC) - 16 - 0x0000 - - - BOOTKEY2_6 - [15:0] - read-only - - - - - BOOTKEY2_7 - 0x014e - Bits 127:112 of SHA-256 hash of boot key 2 (ECC) - 16 - 0x0000 - - - BOOTKEY2_7 - [15:0] - read-only - - - - - BOOTKEY2_8 - 0x0150 - Bits 143:128 of SHA-256 hash of boot key 2 (ECC) - 16 - 0x0000 - - - BOOTKEY2_8 - [15:0] - read-only - - - - - BOOTKEY2_9 - 0x0152 - Bits 159:144 of SHA-256 hash of boot key 2 (ECC) - 16 - 0x0000 - - - BOOTKEY2_9 - [15:0] - read-only - - - - - BOOTKEY2_10 - 0x0154 - Bits 175:160 of SHA-256 hash of boot key 2 (ECC) - 16 - 0x0000 - - - BOOTKEY2_10 - [15:0] - read-only - - - - - BOOTKEY2_11 - 0x0156 - Bits 191:176 of SHA-256 hash of boot key 2 (ECC) - 16 - 0x0000 - - - BOOTKEY2_11 - [15:0] - read-only - - - - - BOOTKEY2_12 - 0x0158 - Bits 207:192 of SHA-256 hash of boot key 2 (ECC) - 16 - 0x0000 - - - BOOTKEY2_12 - [15:0] - read-only - - - - - BOOTKEY2_13 - 0x015a - Bits 223:208 of SHA-256 hash of boot key 2 (ECC) - 16 - 0x0000 - - - BOOTKEY2_13 - [15:0] - read-only - - - - - BOOTKEY2_14 - 0x015c - Bits 239:224 of SHA-256 hash of boot key 2 (ECC) - 16 - 0x0000 - - - BOOTKEY2_14 - [15:0] - read-only - - - - - BOOTKEY2_15 - 0x015e - Bits 255:240 of SHA-256 hash of boot key 2 (ECC) - 16 - 0x0000 - - - BOOTKEY2_15 - [15:0] - read-only - - - - - BOOTKEY3_0 - 0x0160 - Bits 15:0 of SHA-256 hash of boot key 3 (ECC) - 16 - 0x0000 - - - BOOTKEY3_0 - [15:0] - read-only - - - - - BOOTKEY3_1 - 0x0162 - Bits 31:16 of SHA-256 hash of boot key 3 (ECC) - 16 - 0x0000 - - - BOOTKEY3_1 - [15:0] - read-only - - - - - BOOTKEY3_2 - 0x0164 - Bits 47:32 of SHA-256 hash of boot key 3 (ECC) - 16 - 0x0000 - - - BOOTKEY3_2 - [15:0] - read-only - - - - - BOOTKEY3_3 - 0x0166 - Bits 63:48 of SHA-256 hash of boot key 3 (ECC) - 16 - 0x0000 - - - BOOTKEY3_3 - [15:0] - read-only - - - - - BOOTKEY3_4 - 0x0168 - Bits 79:64 of SHA-256 hash of boot key 3 (ECC) - 16 - 0x0000 - - - BOOTKEY3_4 - [15:0] - read-only - - - - - BOOTKEY3_5 - 0x016a - Bits 95:80 of SHA-256 hash of boot key 3 (ECC) - 16 - 0x0000 - - - BOOTKEY3_5 - [15:0] - read-only - - - - - BOOTKEY3_6 - 0x016c - Bits 111:96 of SHA-256 hash of boot key 3 (ECC) - 16 - 0x0000 - - - BOOTKEY3_6 - [15:0] - read-only - - - - - BOOTKEY3_7 - 0x016e - Bits 127:112 of SHA-256 hash of boot key 3 (ECC) - 16 - 0x0000 - - - BOOTKEY3_7 - [15:0] - read-only - - - - - BOOTKEY3_8 - 0x0170 - Bits 143:128 of SHA-256 hash of boot key 3 (ECC) - 16 - 0x0000 - - - BOOTKEY3_8 - [15:0] - read-only - - - - - BOOTKEY3_9 - 0x0172 - Bits 159:144 of SHA-256 hash of boot key 3 (ECC) - 16 - 0x0000 - - - BOOTKEY3_9 - [15:0] - read-only - - - - - BOOTKEY3_10 - 0x0174 - Bits 175:160 of SHA-256 hash of boot key 3 (ECC) - 16 - 0x0000 - - - BOOTKEY3_10 - [15:0] - read-only - - - - - BOOTKEY3_11 - 0x0176 - Bits 191:176 of SHA-256 hash of boot key 3 (ECC) - 16 - 0x0000 - - - BOOTKEY3_11 - [15:0] - read-only - - - - - BOOTKEY3_12 - 0x0178 - Bits 207:192 of SHA-256 hash of boot key 3 (ECC) - 16 - 0x0000 - - - BOOTKEY3_12 - [15:0] - read-only - - - - - BOOTKEY3_13 - 0x017a - Bits 223:208 of SHA-256 hash of boot key 3 (ECC) - 16 - 0x0000 - - - BOOTKEY3_13 - [15:0] - read-only - - - - - BOOTKEY3_14 - 0x017c - Bits 239:224 of SHA-256 hash of boot key 3 (ECC) - 16 - 0x0000 - - - BOOTKEY3_14 - [15:0] - read-only - - - - - BOOTKEY3_15 - 0x017e - Bits 255:240 of SHA-256 hash of boot key 3 (ECC) - 16 - 0x0000 - - - BOOTKEY3_15 - [15:0] - read-only - - - - - KEY1_0 - 0x1e90 - Bits 15:0 of OTP access key 1 (ECC) - 16 - 0x0000 - - - KEY1_0 - [15:0] - read-only - - - - - KEY1_1 - 0x1e92 - Bits 31:16 of OTP access key 1 (ECC) - 16 - 0x0000 - - - KEY1_1 - [15:0] - read-only - - - - - KEY1_2 - 0x1e94 - Bits 47:32 of OTP access key 1 (ECC) - 16 - 0x0000 - - - KEY1_2 - [15:0] - read-only - - - - - KEY1_3 - 0x1e96 - Bits 63:48 of OTP access key 1 (ECC) - 16 - 0x0000 - - - KEY1_3 - [15:0] - read-only - - - - - KEY1_4 - 0x1e98 - Bits 79:64 of OTP access key 1 (ECC) - 16 - 0x0000 - - - KEY1_4 - [15:0] - read-only - - - - - KEY1_5 - 0x1e9a - Bits 95:80 of OTP access key 1 (ECC) - 16 - 0x0000 - - - KEY1_5 - [15:0] - read-only - - - - - KEY1_6 - 0x1e9c - Bits 111:96 of OTP access key 1 (ECC) - 16 - 0x0000 - - - KEY1_6 - [15:0] - read-only - - - - - KEY1_7 - 0x1e9e - Bits 127:112 of OTP access key 1 (ECC) - 16 - 0x0000 - - - KEY1_7 - [15:0] - read-only - - - - - KEY2_0 - 0x1ea0 - Bits 15:0 of OTP access key 2 (ECC) - 16 - 0x0000 - - - KEY2_0 - [15:0] - read-only - - - - - KEY2_1 - 0x1ea2 - Bits 31:16 of OTP access key 2 (ECC) - 16 - 0x0000 - - - KEY2_1 - [15:0] - read-only - - - - - KEY2_2 - 0x1ea4 - Bits 47:32 of OTP access key 2 (ECC) - 16 - 0x0000 - - - KEY2_2 - [15:0] - read-only - - - - - KEY2_3 - 0x1ea6 - Bits 63:48 of OTP access key 2 (ECC) - 16 - 0x0000 - - - KEY2_3 - [15:0] - read-only - - - - - KEY2_4 - 0x1ea8 - Bits 79:64 of OTP access key 2 (ECC) - 16 - 0x0000 - - - KEY2_4 - [15:0] - read-only - - - - - KEY2_5 - 0x1eaa - Bits 95:80 of OTP access key 2 (ECC) - 16 - 0x0000 - - - KEY2_5 - [15:0] - read-only - - - - - KEY2_6 - 0x1eac - Bits 111:96 of OTP access key 2 (ECC) - 16 - 0x0000 - - - KEY2_6 - [15:0] - read-only - - - - - KEY2_7 - 0x1eae - Bits 127:112 of OTP access key 2 (ECC) - 16 - 0x0000 - - - KEY2_7 - [15:0] - read-only - - - - - KEY3_0 - 0x1eb0 - Bits 15:0 of OTP access key 3 (ECC) - 16 - 0x0000 - - - KEY3_0 - [15:0] - read-only - - - - - KEY3_1 - 0x1eb2 - Bits 31:16 of OTP access key 3 (ECC) - 16 - 0x0000 - - - KEY3_1 - [15:0] - read-only - - - - - KEY3_2 - 0x1eb4 - Bits 47:32 of OTP access key 3 (ECC) - 16 - 0x0000 - - - KEY3_2 - [15:0] - read-only - - - - - KEY3_3 - 0x1eb6 - Bits 63:48 of OTP access key 3 (ECC) - 16 - 0x0000 - - - KEY3_3 - [15:0] - read-only - - - - - KEY3_4 - 0x1eb8 - Bits 79:64 of OTP access key 3 (ECC) - 16 - 0x0000 - - - KEY3_4 - [15:0] - read-only - - - - - KEY3_5 - 0x1eba - Bits 95:80 of OTP access key 3 (ECC) - 16 - 0x0000 - - - KEY3_5 - [15:0] - read-only - - - - - KEY3_6 - 0x1ebc - Bits 111:96 of OTP access key 3 (ECC) - 16 - 0x0000 - - - KEY3_6 - [15:0] - read-only - - - - - KEY3_7 - 0x1ebe - Bits 127:112 of OTP access key 3 (ECC) - 16 - 0x0000 - - - KEY3_7 - [15:0] - read-only - - - - - KEY4_0 - 0x1ec0 - Bits 15:0 of OTP access key 4 (ECC) - 16 - 0x0000 - - - KEY4_0 - [15:0] - read-only - - - - - KEY4_1 - 0x1ec2 - Bits 31:16 of OTP access key 4 (ECC) - 16 - 0x0000 - - - KEY4_1 - [15:0] - read-only - - - - - KEY4_2 - 0x1ec4 - Bits 47:32 of OTP access key 4 (ECC) - 16 - 0x0000 - - - KEY4_2 - [15:0] - read-only - - - - - KEY4_3 - 0x1ec6 - Bits 63:48 of OTP access key 4 (ECC) - 16 - 0x0000 - - - KEY4_3 - [15:0] - read-only - - - - - KEY4_4 - 0x1ec8 - Bits 79:64 of OTP access key 4 (ECC) - 16 - 0x0000 - - - KEY4_4 - [15:0] - read-only - - - - - KEY4_5 - 0x1eca - Bits 95:80 of OTP access key 4 (ECC) - 16 - 0x0000 - - - KEY4_5 - [15:0] - read-only - - - - - KEY4_6 - 0x1ecc - Bits 111:96 of OTP access key 4 (ECC) - 16 - 0x0000 - - - KEY4_6 - [15:0] - read-only - - - - - KEY4_7 - 0x1ece - Bits 127:112 of OTP access key 4 (ECC) - 16 - 0x0000 - - - KEY4_7 - [15:0] - read-only - - - - - KEY5_0 - 0x1ed0 - Bits 15:0 of OTP access key 5 (ECC) - 16 - 0x0000 - - - KEY5_0 - [15:0] - read-only - - - - - KEY5_1 - 0x1ed2 - Bits 31:16 of OTP access key 5 (ECC) - 16 - 0x0000 - - - KEY5_1 - [15:0] - read-only - - - - - KEY5_2 - 0x1ed4 - Bits 47:32 of OTP access key 5 (ECC) - 16 - 0x0000 - - - KEY5_2 - [15:0] - read-only - - - - - KEY5_3 - 0x1ed6 - Bits 63:48 of OTP access key 5 (ECC) - 16 - 0x0000 - - - KEY5_3 - [15:0] - read-only - - - - - KEY5_4 - 0x1ed8 - Bits 79:64 of OTP access key 5 (ECC) - 16 - 0x0000 - - - KEY5_4 - [15:0] - read-only - - - - - KEY5_5 - 0x1eda - Bits 95:80 of OTP access key 5 (ECC) - 16 - 0x0000 - - - KEY5_5 - [15:0] - read-only - - - - - KEY5_6 - 0x1edc - Bits 111:96 of OTP access key 5 (ECC) - 16 - 0x0000 - - - KEY5_6 - [15:0] - read-only - - - - - KEY5_7 - 0x1ede - Bits 127:112 of OTP access key 5 (ECC) - 16 - 0x0000 - - - KEY5_7 - [15:0] - read-only - - - - - KEY6_0 - 0x1ee0 - Bits 15:0 of OTP access key 6 (ECC) - 16 - 0x0000 - - - KEY6_0 - [15:0] - read-only - - - - - KEY6_1 - 0x1ee2 - Bits 31:16 of OTP access key 6 (ECC) - 16 - 0x0000 - - - KEY6_1 - [15:0] - read-only - - - - - KEY6_2 - 0x1ee4 - Bits 47:32 of OTP access key 6 (ECC) - 16 - 0x0000 - - - KEY6_2 - [15:0] - read-only - - - - - KEY6_3 - 0x1ee6 - Bits 63:48 of OTP access key 6 (ECC) - 16 - 0x0000 - - - KEY6_3 - [15:0] - read-only - - - - - KEY6_4 - 0x1ee8 - Bits 79:64 of OTP access key 6 (ECC) - 16 - 0x0000 - - - KEY6_4 - [15:0] - read-only - - - - - KEY6_5 - 0x1eea - Bits 95:80 of OTP access key 6 (ECC) - 16 - 0x0000 - - - KEY6_5 - [15:0] - read-only - - - - - KEY6_6 - 0x1eec - Bits 111:96 of OTP access key 6 (ECC) - 16 - 0x0000 - - - KEY6_6 - [15:0] - read-only - - - - - KEY6_7 - 0x1eee - Bits 127:112 of OTP access key 6 (ECC) - 16 - 0x0000 - - - KEY6_7 - [15:0] - read-only - - - - - - - OTP_DATA_RAW - Predefined OTP data layout for RP2350 - 0x40134000 - - 0 - 16384 - registers - - - - CHIPID0 - 0x00000000 - Bits 15:0 of public device ID. (ECC) - - The CHIPID0..3 rows contain a 64-bit random identifier for this chip, which can be read from the USB bootloader PICOBOOT interface or from the get_sys_info ROM API. - - The number of random bits makes the occurrence of twins exceedingly unlikely: for example, a fleet of a hundred million devices has a 99.97% probability of no twinned IDs. This is estimated to be lower than the occurrence of process errors in the assignment of sequential random IDs, and for practical purposes CHIPID may be treated as unique. - 0x00000000 - - - CHIPID0 - [15:0] - read-only - - - - - CHIPID1 - 0x00000004 - Bits 31:16 of public device ID (ECC) - 0x00000000 - - - CHIPID1 - [15:0] - read-only - - - - - CHIPID2 - 0x00000008 - Bits 47:32 of public device ID (ECC) - 0x00000000 - - - CHIPID2 - [15:0] - read-only - - - - - CHIPID3 - 0x0000000c - Bits 63:48 of public device ID (ECC) - 0x00000000 - - - CHIPID3 - [15:0] - read-only - - - - - RANDID0 - 0x00000010 - Bits 15:0 of private per-device random number (ECC) - - The RANDID0..7 rows form a 128-bit random number generated during device test. - - This ID is not exposed through the USB PICOBOOT GET_INFO command or the ROM `get_sys_info()` API. However note that the USB PICOBOOT OTP access point can read the entirety of page 0, so this value is not meaningfully private unless the USB PICOBOOT interface is disabled via the DISABLE_BOOTSEL_USB_PICOBOOT_IFC flag in BOOT_FLAGS0. - 0x00000000 - - - RANDID0 - [15:0] - read-only - - - - - RANDID1 - 0x00000014 - Bits 31:16 of private per-device random number (ECC) - 0x00000000 - - - RANDID1 - [15:0] - read-only - - - - - RANDID2 - 0x00000018 - Bits 47:32 of private per-device random number (ECC) - 0x00000000 - - - RANDID2 - [15:0] - read-only - - - - - RANDID3 - 0x0000001c - Bits 63:48 of private per-device random number (ECC) - 0x00000000 - - - RANDID3 - [15:0] - read-only - - - - - RANDID4 - 0x00000020 - Bits 79:64 of private per-device random number (ECC) - 0x00000000 - - - RANDID4 - [15:0] - read-only - - - - - RANDID5 - 0x00000024 - Bits 95:80 of private per-device random number (ECC) - 0x00000000 - - - RANDID5 - [15:0] - read-only - - - - - RANDID6 - 0x00000028 - Bits 111:96 of private per-device random number (ECC) - 0x00000000 - - - RANDID6 - [15:0] - read-only - - - - - RANDID7 - 0x0000002c - Bits 127:112 of private per-device random number (ECC) - 0x00000000 - - - RANDID7 - [15:0] - read-only - - - - - ROSC_CALIB - 0x00000040 - Ring oscillator frequency in kHz, measured during manufacturing (ECC) - - This is measured at 1.1 V, at room temperature, with the ROSC configuration registers in their reset state. - 0x00000000 - - - ROSC_CALIB - [15:0] - read-only - - - - - LPOSC_CALIB - 0x00000044 - Low-power oscillator frequency in Hz, measured during manufacturing (ECC) - - This is measured at 1.1V, at room temperature, with the LPOSC trim register in its reset state. - 0x00000000 - - - LPOSC_CALIB - [15:0] - read-only - - - - - NUM_GPIOS - 0x00000060 - The number of main user GPIOs (bank 0). Should read 48 in the QFN80 package, and 30 in the QFN60 package. (ECC) - 0x00000000 - - - NUM_GPIOS - [7:0] - read-only - - - - - INFO_CRC0 - 0x000000d8 - Lower 16 bits of CRC32 of OTP addresses 0x00 through 0x6b (polynomial 0x4c11db7, input reflected, output reflected, seed all-ones, final XOR all-ones) (ECC) - 0x00000000 - - - INFO_CRC0 - [15:0] - read-only - - - - - INFO_CRC1 - 0x000000dc - Upper 16 bits of CRC32 of OTP addresses 0x00 through 0x6b (ECC) - 0x00000000 - - - INFO_CRC1 - [15:0] - read-only - - - - - CRIT0 - 0x000000e0 - Page 0 critical boot flags (RBIT-8) - 0x00000000 - - - RISCV_DISABLE - Permanently disable RISC-V processors (Hazard3) - [1:1] - read-only - - - ARM_DISABLE - Permanently disable ARM processors (Cortex-M33) - [0:0] - read-only - - - - - CRIT0_R1 - 0x000000e4 - Redundant copy of CRIT0 - 0x00000000 - - - CRIT0_R1 - [23:0] - read-only - - - - - CRIT0_R2 - 0x000000e8 - Redundant copy of CRIT0 - 0x00000000 - - - CRIT0_R2 - [23:0] - read-only - - - - - CRIT0_R3 - 0x000000ec - Redundant copy of CRIT0 - 0x00000000 - - - CRIT0_R3 - [23:0] - read-only - - - - - CRIT0_R4 - 0x000000f0 - Redundant copy of CRIT0 - 0x00000000 - - - CRIT0_R4 - [23:0] - read-only - - - - - CRIT0_R5 - 0x000000f4 - Redundant copy of CRIT0 - 0x00000000 - - - CRIT0_R5 - [23:0] - read-only - - - - - CRIT0_R6 - 0x000000f8 - Redundant copy of CRIT0 - 0x00000000 - - - CRIT0_R6 - [23:0] - read-only - - - - - CRIT0_R7 - 0x000000fc - Redundant copy of CRIT0 - 0x00000000 - - - CRIT0_R7 - [23:0] - read-only - - - - - CRIT1 - 0x00000100 - Page 1 critical boot flags (RBIT-8) - 0x00000000 - - - GLITCH_DETECTOR_SENS - Increase the sensitivity of the glitch detectors from their default. - [6:5] - read-only - - - GLITCH_DETECTOR_ENABLE - Arm the glitch detectors to reset the system if an abnormal clock/power event is observed. - [4:4] - read-only - - - BOOT_ARCH - Set the default boot architecture, 0=ARM 1=RISC-V. Ignored if ARM_DISABLE, RISCV_DISABLE or SECURE_BOOT_ENABLE is set. - [3:3] - read-only - - - DEBUG_DISABLE - Disable all debug access - [2:2] - read-only - - - SECURE_DEBUG_DISABLE - Disable Secure debug access - [1:1] - read-only - - - SECURE_BOOT_ENABLE - Enable boot signature enforcement, and permanently disable the RISC-V cores. - [0:0] - read-only - - - - - CRIT1_R1 - 0x00000104 - Redundant copy of CRIT1 - 0x00000000 - - - CRIT1_R1 - [23:0] - read-only - - - - - CRIT1_R2 - 0x00000108 - Redundant copy of CRIT1 - 0x00000000 - - - CRIT1_R2 - [23:0] - read-only - - - - - CRIT1_R3 - 0x0000010c - Redundant copy of CRIT1 - 0x00000000 - - - CRIT1_R3 - [23:0] - read-only - - - - - CRIT1_R4 - 0x00000110 - Redundant copy of CRIT1 - 0x00000000 - - - CRIT1_R4 - [23:0] - read-only - - - - - CRIT1_R5 - 0x00000114 - Redundant copy of CRIT1 - 0x00000000 - - - CRIT1_R5 - [23:0] - read-only - - - - - CRIT1_R6 - 0x00000118 - Redundant copy of CRIT1 - 0x00000000 - - - CRIT1_R6 - [23:0] - read-only - - - - - CRIT1_R7 - 0x0000011c - Redundant copy of CRIT1 - 0x00000000 - - - CRIT1_R7 - [23:0] - read-only - - - - - BOOT_FLAGS0 - 0x00000120 - Disable/Enable boot paths/features in the RP2350 mask ROM. Disables always supersede enables. Enables are provided where there are other configurations in OTP that must be valid. (RBIT-3) - 0x00000000 - - - DISABLE_SRAM_WINDOW_BOOT - [21:21] - read-only - - - DISABLE_XIP_ACCESS_ON_SRAM_ENTRY - Disable all access to XIP after entering an SRAM binary. - - Note that this will cause bootrom APIs that access XIP to fail, including APIs that interact with the partition table. - [20:20] - read-only - - - DISABLE_BOOTSEL_UART_BOOT - [19:19] - read-only - - - DISABLE_BOOTSEL_USB_PICOBOOT_IFC - [18:18] - read-only - - - DISABLE_BOOTSEL_USB_MSD_IFC - [17:17] - read-only - - - DISABLE_WATCHDOG_SCRATCH - [16:16] - read-only - - - DISABLE_POWER_SCRATCH - [15:15] - read-only - - - ENABLE_OTP_BOOT - Enable OTP boot. A number of OTP rows specified by OTPBOOT_LEN will be loaded, starting from OTPBOOT_SRC, into the SRAM location specified by OTPBOOT_DST1 and OTPBOOT_DST0. - - The loaded program image is stored with ECC, 16 bits per row, and must contain a valid IMAGE_DEF. Do not set this bit without first programming an image into OTP and configuring OTPBOOT_LEN, OTPBOOT_SRC, OTPBOOT_DST0 and OTPBOOT_DST1. - - Note that OTPBOOT_LEN and OTPBOOT_SRC must be even numbers of OTP rows. Equivalently, the image must be a multiple of 32 bits in size, and must start at a 32-bit-aligned address in the ECC read data address window. - [14:14] - read-only - - - DISABLE_OTP_BOOT - Takes precedence over ENABLE_OTP_BOOT. - [13:13] - read-only - - - DISABLE_FLASH_BOOT - [12:12] - read-only - - - ROLLBACK_REQUIRED - Require binaries to have a rollback version. Set automatically the first time a binary with a rollback version is booted. - [11:11] - read-only - - - HASHED_PARTITION_TABLE - Require a partition table to be hashed (if not signed) - [10:10] - read-only - - - SECURE_PARTITION_TABLE - Require a partition table to be signed - [9:9] - read-only - - - DISABLE_AUTO_SWITCH_ARCH - Disable auto-switch of CPU architecture on boot when the (only) binary to be booted is for the other Arm/RISC-V architecture and both architectures are enabled - [8:8] - read-only - - - SINGLE_FLASH_BINARY - Restrict flash boot path to use of a single binary at the start of flash - [7:7] - read-only - - - OVERRIDE_FLASH_PARTITION_SLOT_SIZE - Override the limit for default flash metadata scanning. - - The value is specified in FLASH_PARTITION_SLOT_SIZE. Make sure FLASH_PARTITION_SLOT_SIZE is valid before setting this bit - [6:6] - read-only - - - FLASH_DEVINFO_ENABLE - Mark FLASH_DEVINFO as containing valid, ECC'd data which describes external flash devices. - [5:5] - read-only - - - FAST_SIGCHECK_ROSC_DIV - Enable quartering of ROSC divisor during signature check, to reduce secure boot time - [4:4] - read-only - - - FLASH_IO_VOLTAGE_1V8 - If 1, configure the QSPI pads for 1.8 V operation when accessing flash for the first time from the bootrom, using the VOLTAGE_SELECT register for the QSPI pads bank. This slightly improves the input timing of the pads at low voltages, but does not affect their output characteristics. - - If 0, leave VOLTAGE_SELECT in its reset state (suitable for operation at and above 2.5 V) - [3:3] - read-only - - - ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG - Enable loading of the non-default XOSC and PLL configuration before entering BOOTSEL mode. - - Ensure that BOOTSEL_XOSC_CFG and BOOTSEL_PLL_CFG are correctly programmed before setting this bit. - - If this bit is set, user software may use the contents of BOOTSEL_PLL_CFG to calculated the expected XOSC frequency based on the fixed USB boot frequency of 48 MHz. - [2:2] - read-only - - - ENABLE_BOOTSEL_LED - Enable bootloader activity LED. If set, bootsel_led_cfg is assumed to be valid - [1:1] - read-only - - - DISABLE_BOOTSEL_EXEC2 - [0:0] - read-only - - - - - BOOT_FLAGS0_R1 - 0x00000124 - Redundant copy of BOOT_FLAGS0 - 0x00000000 - - - BOOT_FLAGS0_R1 - [23:0] - read-only - - - - - BOOT_FLAGS0_R2 - 0x00000128 - Redundant copy of BOOT_FLAGS0 - 0x00000000 - - - BOOT_FLAGS0_R2 - [23:0] - read-only - - - - - BOOT_FLAGS1 - 0x0000012c - Disable/Enable boot paths/features in the RP2350 mask ROM. Disables always supersede enables. Enables are provided where there are other configurations in OTP that must be valid. (RBIT-3) - 0x00000000 - - - DOUBLE_TAP - Enable entering BOOTSEL mode via double-tap of the RUN/RSTn pin. Adds a significant delay to boot time, as configured by DOUBLE_TAP_DELAY. - - This functions by waiting at startup (i.e. following a reset) to see if a second reset is applied soon afterward. The second reset is detected by the bootrom with help of the POWMAN_CHIP_RESET_DOUBLE_TAP flag, which is not reset by the external reset pin, and the bootrom enters BOOTSEL mode (NSBOOT) to await further instruction over USB or UART. - [19:19] - read-only - - - DOUBLE_TAP_DELAY - Adjust how long to wait for a second reset when double tap BOOTSEL mode is enabled via DOUBLE_TAP. The minimum is 50 milliseconds, and each unit of this field adds an additional 50 milliseconds. - - For example, settings this field to its maximum value of 7 will cause the chip to wait for 400 milliseconds at boot to check for a second reset which requests entry to BOOTSEL mode. - - 200 milliseconds (DOUBLE_TAP_DELAY=3) is a good intermediate value. - [18:16] - read-only - - - KEY_INVALID - Mark a boot key as invalid, or prevent it from ever becoming valid. The bootrom will ignore any boot key marked as invalid during secure boot signature checks. - - Each bit in this field corresponds to one of the four 256-bit boot key hashes that may be stored in page 2 of the OTP. - - When provisioning boot keys, it's recommended to mark any boot key slots you don't intend to use as KEY_INVALID, so that spurious keys can not be installed at a later time. - [11:8] - read-only - - - KEY_VALID - Mark each of the possible boot keys as valid. The bootrom will check signatures against all valid boot keys, and ignore invalid boot keys. - - Each bit in this field corresponds to one of the four 256-bit boot key hashes that may be stored in page 2 of the OTP. - - A KEY_VALID bit is ignored if the corresponding KEY_INVALID bit is set. Boot keys are considered valid only when KEY_VALID is set and KEY_INVALID is clear. - - Do not mark a boot key as KEY_VALID if it does not contain a valid SHA-256 hash of your secp256k1 public key. Verify keys after programming, before setting the KEY_VALID bits -- a boot key with uncorrectable ECC faults will render your device unbootable if secure boot is enabled. - - Do not enable secure boot without first installing a valid key. This will render your device unbootable. - [3:0] - read-only - - - - - BOOT_FLAGS1_R1 - 0x00000130 - Redundant copy of BOOT_FLAGS1 - 0x00000000 - - - BOOT_FLAGS1_R1 - [23:0] - read-only - - - - - BOOT_FLAGS1_R2 - 0x00000134 - Redundant copy of BOOT_FLAGS1 - 0x00000000 - - - BOOT_FLAGS1_R2 - [23:0] - read-only - - - - - DEFAULT_BOOT_VERSION0 - 0x00000138 - Default boot version thermometer counter, bits 23:0 (RBIT-3) - 0x00000000 - - - DEFAULT_BOOT_VERSION0 - [23:0] - read-only - - - - - DEFAULT_BOOT_VERSION0_R1 - 0x0000013c - Redundant copy of DEFAULT_BOOT_VERSION0 - 0x00000000 - - - DEFAULT_BOOT_VERSION0_R1 - [23:0] - read-only - - - - - DEFAULT_BOOT_VERSION0_R2 - 0x00000140 - Redundant copy of DEFAULT_BOOT_VERSION0 - 0x00000000 - - - DEFAULT_BOOT_VERSION0_R2 - [23:0] - read-only - - - - - DEFAULT_BOOT_VERSION1 - 0x00000144 - Default boot version thermometer counter, bits 47:24 (RBIT-3) - 0x00000000 - - - DEFAULT_BOOT_VERSION1 - [23:0] - read-only - - - - - DEFAULT_BOOT_VERSION1_R1 - 0x00000148 - Redundant copy of DEFAULT_BOOT_VERSION1 - 0x00000000 - - - DEFAULT_BOOT_VERSION1_R1 - [23:0] - read-only - - - - - DEFAULT_BOOT_VERSION1_R2 - 0x0000014c - Redundant copy of DEFAULT_BOOT_VERSION1 - 0x00000000 - - - DEFAULT_BOOT_VERSION1_R2 - [23:0] - read-only - - - - - FLASH_DEVINFO - 0x00000150 - Stores information about external flash device(s). (ECC) - - Assumed to be valid if BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is set. - 0x00000000 - - - CS1_SIZE - The size of the flash/PSRAM device on chip select 1 (addressable at 0x11000000 through 0x11ffffff). - - A value of zero is decoded as a size of zero (no device). Nonzero values are decoded as 4kiB << CS1_SIZE. For example, four megabytes is encoded with a CS1_SIZE value of 10, and 16 megabytes is encoded with a CS1_SIZE value of 12. - - When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, a default of zero is used. - [15:12] - read-only - - - NONE - 0 - - - 8K - 1 - - - 16K - 2 - - - 32K - 3 - - - 64k - 4 - - - 128K - 5 - - - 256K - 6 - - - 512K - 7 - - - 1M - 8 - - - 2M - 9 - - - 4M - 10 - - - 8M - 11 - - - 16M - 12 - - - - - CS0_SIZE - The size of the flash/PSRAM device on chip select 0 (addressable at 0x10000000 through 0x10ffffff). - - A value of zero is decoded as a size of zero (no device). Nonzero values are decoded as 4kiB << CS0_SIZE. For example, four megabytes is encoded with a CS0_SIZE value of 10, and 16 megabytes is encoded with a CS0_SIZE value of 12. - - When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, a default of 12 (16 MiB) is used. - [11:8] - read-only - - - NONE - 0 - - - 8K - 1 - - - 16K - 2 - - - 32K - 3 - - - 64k - 4 - - - 128K - 5 - - - 256K - 6 - - - 512K - 7 - - - 1M - 8 - - - 2M - 9 - - - 4M - 10 - - - 8M - 11 - - - 16M - 12 - - - - - D8H_ERASE_SUPPORTED - If true, all attached devices are assumed to support (or ignore, in the case of PSRAM) a block erase command with a command prefix of D8h, an erase size of 64 kiB, and a 24-bit address. Almost all 25-series flash devices support this command. - - If set, the bootrom will use the D8h erase command where it is able, to accelerate bulk erase operations. This makes flash programming faster. - - When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, this field defaults to false. - [7:7] - read-only - - - CS1_GPIO - Indicate a GPIO number to be used for the secondary flash chip select (CS1), which selects the external QSPI device mapped at system addresses 0x11000000 through 0x11ffffff. There is no such configuration for CS0, as the primary chip select has a dedicated pin. - - On RP2350 the permissible GPIO numbers are 0, 8, 19 and 47. - - Ignored if CS1_size is zero. If CS1_SIZE is nonzero, the bootrom will automatically configure this GPIO as a second chip select upon entering the flash boot path, or entering any other path that may use the QSPI flash interface, such as BOOTSEL mode (nsboot). - [5:0] - read-only - - - - - FLASH_PARTITION_SLOT_SIZE - 0x00000154 - Gap between partition table slot 0 and slot 1 at the start of flash (the default size is 4096 bytes) (ECC) Enabled by the OVERRIDE_FLASH_PARTITION_SLOT_SIZE bit in BOOT_FLAGS, the size is 4096 * (value + 1) - 0x00000000 - - - FLASH_PARTITION_SLOT_SIZE - [15:0] - read-only - - - - - BOOTSEL_LED_CFG - 0x00000158 - Pin configuration for LED status, used by USB bootloader. (ECC) - Must be valid if BOOT_FLAGS0_ENABLE_BOOTSEL_LED is set. - 0x00000000 - - - ACTIVELOW - LED is active-low. (Default: active-high.) - [8:8] - read-only - - - PIN - GPIO index to use for bootloader activity LED. - [5:0] - read-only - - - - - BOOTSEL_PLL_CFG - 0x0000015c - Optional PLL configuration for BOOTSEL mode. (ECC) - - This should be configured to produce an exact 48 MHz based on the crystal oscillator frequency. User mode software may also use this value to calculate the expected crystal frequency based on an assumed 48 MHz PLL output. - - If no configuration is given, the crystal is assumed to be 12 MHz. - - The PLL frequency can be calculated as: - - PLL out = (XOSC frequency / (REFDIV+1)) x FBDIV / (POSTDIV1 x POSTDIV2) - - Conversely the crystal frequency can be calculated as: - - XOSC frequency = 48 MHz x (REFDIV+1) x (POSTDIV1 x POSTDIV2) / FBDIV - - (Note the +1 on REFDIV is because the value stored in this OTP location is the actual divisor value minus one.) - - Used if and only if ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG is set in BOOT_FLAGS0. That bit should be set only after this row and BOOTSEL_XOSC_CFG are both correctly programmed. - 0x00000000 - - - REFDIV - PLL reference divisor, minus one. - - Programming a value of 0 means a reference divisor of 1. Programming a value of 1 means a reference divisor of 2 (for exceptionally fast XIN inputs) - [15:15] - read-only - - - POSTDIV2 - PLL post-divide 2 divisor, in the range 1..7 inclusive. - [14:12] - read-only - - - POSTDIV1 - PLL post-divide 1 divisor, in the range 1..7 inclusive. - [11:9] - read-only - - - FBDIV - PLL feedback divisor, in the range 16..320 inclusive. - [8:0] - read-only - - - - - BOOTSEL_XOSC_CFG - 0x00000160 - Non-default crystal oscillator configuration for the USB bootloader. (ECC) - - These values may also be used by user code configuring the crystal oscillator. - - Used if and only if ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG is set in BOOT_FLAGS0. That bit should be set only after this row and BOOTSEL_PLL_CFG are both correctly programmed. - 0x00000000 - - - RANGE - Value of the XOSC_CTRL_FREQ_RANGE register. - [15:14] - read-only - - - 1_15MHZ - 0 - - - 10_30MHZ - 1 - - - 25_60MHZ - 2 - - - 40_100MHZ - 3 - - - - - STARTUP - Value of the XOSC_STARTUP register - [13:0] - read-only - - - - - USB_BOOT_FLAGS - 0x00000164 - USB boot specific feature flags (RBIT-3) - 0x00000000 - - - DP_DM_SWAP - Swap DM/DP during USB boot, to support board layouts with mirrored USB routing (deliberate or accidental). - [23:23] - read-only - - - WHITE_LABEL_ADDR_VALID - valid flag for INFO_UF2_TXT_BOARD_ID_STRDEF entry of the USB_WHITE_LABEL struct (index 15) - [22:22] - read-only - - - WL_INFO_UF2_TXT_BOARD_ID_STRDEF_VALID - valid flag for the USB_WHITE_LABEL_ADDR field - [15:15] - read-only - - - WL_INFO_UF2_TXT_MODEL_STRDEF_VALID - valid flag for INFO_UF2_TXT_MODEL_STRDEF entry of the USB_WHITE_LABEL struct (index 14) - [14:14] - read-only - - - WL_INDEX_HTM_REDIRECT_NAME_STRDEF_VALID - valid flag for INDEX_HTM_REDIRECT_NAME_STRDEF entry of the USB_WHITE_LABEL struct (index 13) - [13:13] - read-only - - - WL_INDEX_HTM_REDIRECT_URL_STRDEF_VALID - valid flag for INDEX_HTM_REDIRECT_URL_STRDEF entry of the USB_WHITE_LABEL struct (index 12) - [12:12] - read-only - - - WL_SCSI_INQUIRY_VERSION_STRDEF_VALID - valid flag for SCSI_INQUIRY_VERSION_STRDEF entry of the USB_WHITE_LABEL struct (index 11) - [11:11] - read-only - - - WL_SCSI_INQUIRY_PRODUCT_STRDEF_VALID - valid flag for SCSI_INQUIRY_PRODUCT_STRDEF entry of the USB_WHITE_LABEL struct (index 10) - [10:10] - read-only - - - WL_SCSI_INQUIRY_VENDOR_STRDEF_VALID - valid flag for SCSI_INQUIRY_VENDOR_STRDEF entry of the USB_WHITE_LABEL struct (index 9) - [9:9] - read-only - - - WL_VOLUME_LABEL_STRDEF_VALID - valid flag for VOLUME_LABEL_STRDEF entry of the USB_WHITE_LABEL struct (index 8) - [8:8] - read-only - - - WL_USB_CONFIG_ATTRIBUTES_MAX_POWER_VALUES_VALID - valid flag for USB_CONFIG_ATTRIBUTES_MAX_POWER_VALUES entry of the USB_WHITE_LABEL struct (index 7) - [7:7] - read-only - - - WL_USB_DEVICE_SERIAL_NUMBER_STRDEF_VALID - valid flag for USB_DEVICE_SERIAL_NUMBER_STRDEF entry of the USB_WHITE_LABEL struct (index 6) - [6:6] - read-only - - - WL_USB_DEVICE_PRODUCT_STRDEF_VALID - valid flag for USB_DEVICE_PRODUCT_STRDEF entry of the USB_WHITE_LABEL struct (index 5) - [5:5] - read-only - - - WL_USB_DEVICE_MANUFACTURER_STRDEF_VALID - valid flag for USB_DEVICE_MANUFACTURER_STRDEF entry of the USB_WHITE_LABEL struct (index 4) - [4:4] - read-only - - - WL_USB_DEVICE_LANG_ID_VALUE_VALID - valid flag for USB_DEVICE_LANG_ID_VALUE entry of the USB_WHITE_LABEL struct (index 3) - [3:3] - read-only - - - WL_USB_DEVICE_SERIAL_NUMBER_VALUE_VALID - valid flag for USB_DEVICE_BCD_DEVICEVALUE entry of the USB_WHITE_LABEL struct (index 2) - [2:2] - read-only - - - WL_USB_DEVICE_PID_VALUE_VALID - valid flag for USB_DEVICE_PID_VALUE entry of the USB_WHITE_LABEL struct (index 1) - [1:1] - read-only - - - WL_USB_DEVICE_VID_VALUE_VALID - valid flag for USB_DEVICE_VID_VALUE entry of the USB_WHITE_LABEL struct (index 0) - [0:0] - read-only - - - - - USB_BOOT_FLAGS_R1 - 0x00000168 - Redundant copy of USB_BOOT_FLAGS - 0x00000000 - - - USB_BOOT_FLAGS_R1 - [23:0] - read-only - - - - - USB_BOOT_FLAGS_R2 - 0x0000016c - Redundant copy of USB_BOOT_FLAGS - 0x00000000 - - - USB_BOOT_FLAGS_R2 - [23:0] - read-only - - - - - USB_WHITE_LABEL_ADDR - 0x00000170 - Row index of the USB_WHITE_LABEL structure within OTP (ECC) - - The table has 16 rows, each of which are also ECC and marked valid by the corresponding valid bit in USB_BOOT_FLAGS (ECC). - - The entries are either _VALUEs where the 16 bit value is used as is, or _STRDEFs which acts as a pointers to a string value. - - The value stored in a _STRDEF is two separate bytes: The low seven bits of the first (LSB) byte indicates the number of characters in the string, and the top bit of the first (LSB) byte if set to indicate that each character in the string is two bytes (Unicode) versus one byte if unset. The second (MSB) byte represents the location of the string data, and is encoded as the number of rows from this USB_WHITE_LABEL_ADDR; i.e. the row of the start of the string is USB_WHITE_LABEL_ADDR value + msb_byte. - - In each case, the corresponding valid bit enables replacing the default value for the corresponding item provided by the boot rom. - - Note that Unicode _STRDEFs are only supported for USB_DEVICE_PRODUCT_STRDEF, USB_DEVICE_SERIAL_NUMBER_STRDEF and USB_DEVICE_MANUFACTURER_STRDEF. Unicode values will be ignored if specified for other fields, and non-unicode values for these three items will be converted to Unicode characters by setting the upper 8 bits to zero. - - Note that if the USB_WHITE_LABEL structure or the corresponding strings are not readable by BOOTSEL mode based on OTP permissions, or if alignment requirements are not met, then the corresponding default values are used. - - The index values indicate where each field is located (row USB_WHITE_LABEL_ADDR value + index): - 0x00000000 - - - USB_WHITE_LABEL_ADDR - [15:0] - read-only - - - INDEX_USB_DEVICE_VID_VALUE - 0 - - - INDEX_USB_DEVICE_PID_VALUE - 1 - - - INDEX_USB_DEVICE_BCD_DEVICE_VALUE - 2 - - - INDEX_USB_DEVICE_LANG_ID_VALUE - 3 - - - INDEX_USB_DEVICE_MANUFACTURER_STRDEF - 4 - - - INDEX_USB_DEVICE_PRODUCT_STRDEF - 5 - - - INDEX_USB_DEVICE_SERIAL_NUMBER_STRDEF - 6 - - - INDEX_USB_CONFIG_ATTRIBUTES_MAX_POWER_VALUES - 7 - - - INDEX_VOLUME_LABEL_STRDEF - 8 - - - INDEX_SCSI_INQUIRY_VENDOR_STRDEF - 9 - - - INDEX_SCSI_INQUIRY_PRODUCT_STRDEF - 10 - - - INDEX_SCSI_INQUIRY_VERSION_STRDEF - 11 - - - INDEX_INDEX_HTM_REDIRECT_URL_STRDEF - 12 - - - INDEX_INDEX_HTM_REDIRECT_NAME_STRDEF - 13 - - - INDEX_INFO_UF2_TXT_MODEL_STRDEF - 14 - - - INDEX_INFO_UF2_TXT_BOARD_ID_STRDEF - 15 - - - - - - - OTPBOOT_SRC - 0x00000178 - OTP start row for the OTP boot image. (ECC) - - If OTP boot is enabled, the bootrom will load from this location into SRAM and then directly enter the loaded image. Note that the image must be signed if SECURE_BOOT_ENABLE is set. The image itself is assumed to be ECC-protected. - - This must be an even number. Equivalently, the OTP boot image must start at a word-aligned location in the ECC read data address window. - 0x00000000 - - - OTPBOOT_SRC - [15:0] - read-only - - - - - OTPBOOT_LEN - 0x0000017c - Length in rows of the OTP boot image. (ECC) - - OTPBOOT_LEN must be even. The total image size must be a multiple of 4 bytes (32 bits). - 0x00000000 - - - OTPBOOT_LEN - [15:0] - read-only - - - - - OTPBOOT_DST0 - 0x00000180 - Bits 15:0 of the OTP boot image load destination (and entry point). (ECC) - - This must be a location in main SRAM (main SRAM is addresses 0x20000000 through 0x20082000) and must be word-aligned. - 0x00000000 - - - OTPBOOT_DST0 - [15:0] - read-only - - - - - OTPBOOT_DST1 - 0x00000184 - Bits 31:16 of the OTP boot image load destination (and entry point). (ECC) - - This must be a location in main SRAM (main SRAM is addresses 0x20000000 through 0x20082000) and must be word-aligned. - 0x00000000 - - - OTPBOOT_DST1 - [15:0] - read-only - - - - - BOOTKEY0_0 - 0x00000200 - Bits 15:0 of SHA-256 hash of boot key 0 (ECC) - 0x00000000 - - - BOOTKEY0_0 - [15:0] - read-only - - - - - BOOTKEY0_1 - 0x00000204 - Bits 31:16 of SHA-256 hash of boot key 0 (ECC) - 0x00000000 - - - BOOTKEY0_1 - [15:0] - read-only - - - - - BOOTKEY0_2 - 0x00000208 - Bits 47:32 of SHA-256 hash of boot key 0 (ECC) - 0x00000000 - - - BOOTKEY0_2 - [15:0] - read-only - - - - - BOOTKEY0_3 - 0x0000020c - Bits 63:48 of SHA-256 hash of boot key 0 (ECC) - 0x00000000 - - - BOOTKEY0_3 - [15:0] - read-only - - - - - BOOTKEY0_4 - 0x00000210 - Bits 79:64 of SHA-256 hash of boot key 0 (ECC) - 0x00000000 - - - BOOTKEY0_4 - [15:0] - read-only - - - - - BOOTKEY0_5 - 0x00000214 - Bits 95:80 of SHA-256 hash of boot key 0 (ECC) - 0x00000000 - - - BOOTKEY0_5 - [15:0] - read-only - - - - - BOOTKEY0_6 - 0x00000218 - Bits 111:96 of SHA-256 hash of boot key 0 (ECC) - 0x00000000 - - - BOOTKEY0_6 - [15:0] - read-only - - - - - BOOTKEY0_7 - 0x0000021c - Bits 127:112 of SHA-256 hash of boot key 0 (ECC) - 0x00000000 - - - BOOTKEY0_7 - [15:0] - read-only - - - - - BOOTKEY0_8 - 0x00000220 - Bits 143:128 of SHA-256 hash of boot key 0 (ECC) - 0x00000000 - - - BOOTKEY0_8 - [15:0] - read-only - - - - - BOOTKEY0_9 - 0x00000224 - Bits 159:144 of SHA-256 hash of boot key 0 (ECC) - 0x00000000 - - - BOOTKEY0_9 - [15:0] - read-only - - - - - BOOTKEY0_10 - 0x00000228 - Bits 175:160 of SHA-256 hash of boot key 0 (ECC) - 0x00000000 - - - BOOTKEY0_10 - [15:0] - read-only - - - - - BOOTKEY0_11 - 0x0000022c - Bits 191:176 of SHA-256 hash of boot key 0 (ECC) - 0x00000000 - - - BOOTKEY0_11 - [15:0] - read-only - - - - - BOOTKEY0_12 - 0x00000230 - Bits 207:192 of SHA-256 hash of boot key 0 (ECC) - 0x00000000 - - - BOOTKEY0_12 - [15:0] - read-only - - - - - BOOTKEY0_13 - 0x00000234 - Bits 223:208 of SHA-256 hash of boot key 0 (ECC) - 0x00000000 - - - BOOTKEY0_13 - [15:0] - read-only - - - - - BOOTKEY0_14 - 0x00000238 - Bits 239:224 of SHA-256 hash of boot key 0 (ECC) - 0x00000000 - - - BOOTKEY0_14 - [15:0] - read-only - - - - - BOOTKEY0_15 - 0x0000023c - Bits 255:240 of SHA-256 hash of boot key 0 (ECC) - 0x00000000 - - - BOOTKEY0_15 - [15:0] - read-only - - - - - BOOTKEY1_0 - 0x00000240 - Bits 15:0 of SHA-256 hash of boot key 1 (ECC) - 0x00000000 - - - BOOTKEY1_0 - [15:0] - read-only - - - - - BOOTKEY1_1 - 0x00000244 - Bits 31:16 of SHA-256 hash of boot key 1 (ECC) - 0x00000000 - - - BOOTKEY1_1 - [15:0] - read-only - - - - - BOOTKEY1_2 - 0x00000248 - Bits 47:32 of SHA-256 hash of boot key 1 (ECC) - 0x00000000 - - - BOOTKEY1_2 - [15:0] - read-only - - - - - BOOTKEY1_3 - 0x0000024c - Bits 63:48 of SHA-256 hash of boot key 1 (ECC) - 0x00000000 - - - BOOTKEY1_3 - [15:0] - read-only - - - - - BOOTKEY1_4 - 0x00000250 - Bits 79:64 of SHA-256 hash of boot key 1 (ECC) - 0x00000000 - - - BOOTKEY1_4 - [15:0] - read-only - - - - - BOOTKEY1_5 - 0x00000254 - Bits 95:80 of SHA-256 hash of boot key 1 (ECC) - 0x00000000 - - - BOOTKEY1_5 - [15:0] - read-only - - - - - BOOTKEY1_6 - 0x00000258 - Bits 111:96 of SHA-256 hash of boot key 1 (ECC) - 0x00000000 - - - BOOTKEY1_6 - [15:0] - read-only - - - - - BOOTKEY1_7 - 0x0000025c - Bits 127:112 of SHA-256 hash of boot key 1 (ECC) - 0x00000000 - - - BOOTKEY1_7 - [15:0] - read-only - - - - - BOOTKEY1_8 - 0x00000260 - Bits 143:128 of SHA-256 hash of boot key 1 (ECC) - 0x00000000 - - - BOOTKEY1_8 - [15:0] - read-only - - - - - BOOTKEY1_9 - 0x00000264 - Bits 159:144 of SHA-256 hash of boot key 1 (ECC) - 0x00000000 - - - BOOTKEY1_9 - [15:0] - read-only - - - - - BOOTKEY1_10 - 0x00000268 - Bits 175:160 of SHA-256 hash of boot key 1 (ECC) - 0x00000000 - - - BOOTKEY1_10 - [15:0] - read-only - - - - - BOOTKEY1_11 - 0x0000026c - Bits 191:176 of SHA-256 hash of boot key 1 (ECC) - 0x00000000 - - - BOOTKEY1_11 - [15:0] - read-only - - - - - BOOTKEY1_12 - 0x00000270 - Bits 207:192 of SHA-256 hash of boot key 1 (ECC) - 0x00000000 - - - BOOTKEY1_12 - [15:0] - read-only - - - - - BOOTKEY1_13 - 0x00000274 - Bits 223:208 of SHA-256 hash of boot key 1 (ECC) - 0x00000000 - - - BOOTKEY1_13 - [15:0] - read-only - - - - - BOOTKEY1_14 - 0x00000278 - Bits 239:224 of SHA-256 hash of boot key 1 (ECC) - 0x00000000 - - - BOOTKEY1_14 - [15:0] - read-only - - - - - BOOTKEY1_15 - 0x0000027c - Bits 255:240 of SHA-256 hash of boot key 1 (ECC) - 0x00000000 - - - BOOTKEY1_15 - [15:0] - read-only - - - - - BOOTKEY2_0 - 0x00000280 - Bits 15:0 of SHA-256 hash of boot key 2 (ECC) - 0x00000000 - - - BOOTKEY2_0 - [15:0] - read-only - - - - - BOOTKEY2_1 - 0x00000284 - Bits 31:16 of SHA-256 hash of boot key 2 (ECC) - 0x00000000 - - - BOOTKEY2_1 - [15:0] - read-only - - - - - BOOTKEY2_2 - 0x00000288 - Bits 47:32 of SHA-256 hash of boot key 2 (ECC) - 0x00000000 - - - BOOTKEY2_2 - [15:0] - read-only - - - - - BOOTKEY2_3 - 0x0000028c - Bits 63:48 of SHA-256 hash of boot key 2 (ECC) - 0x00000000 - - - BOOTKEY2_3 - [15:0] - read-only - - - - - BOOTKEY2_4 - 0x00000290 - Bits 79:64 of SHA-256 hash of boot key 2 (ECC) - 0x00000000 - - - BOOTKEY2_4 - [15:0] - read-only - - - - - BOOTKEY2_5 - 0x00000294 - Bits 95:80 of SHA-256 hash of boot key 2 (ECC) - 0x00000000 - - - BOOTKEY2_5 - [15:0] - read-only - - - - - BOOTKEY2_6 - 0x00000298 - Bits 111:96 of SHA-256 hash of boot key 2 (ECC) - 0x00000000 - - - BOOTKEY2_6 - [15:0] - read-only - - - - - BOOTKEY2_7 - 0x0000029c - Bits 127:112 of SHA-256 hash of boot key 2 (ECC) - 0x00000000 - - - BOOTKEY2_7 - [15:0] - read-only - - - - - BOOTKEY2_8 - 0x000002a0 - Bits 143:128 of SHA-256 hash of boot key 2 (ECC) - 0x00000000 - - - BOOTKEY2_8 - [15:0] - read-only - - - - - BOOTKEY2_9 - 0x000002a4 - Bits 159:144 of SHA-256 hash of boot key 2 (ECC) - 0x00000000 - - - BOOTKEY2_9 - [15:0] - read-only - - - - - BOOTKEY2_10 - 0x000002a8 - Bits 175:160 of SHA-256 hash of boot key 2 (ECC) - 0x00000000 - - - BOOTKEY2_10 - [15:0] - read-only - - - - - BOOTKEY2_11 - 0x000002ac - Bits 191:176 of SHA-256 hash of boot key 2 (ECC) - 0x00000000 - - - BOOTKEY2_11 - [15:0] - read-only - - - - - BOOTKEY2_12 - 0x000002b0 - Bits 207:192 of SHA-256 hash of boot key 2 (ECC) - 0x00000000 - - - BOOTKEY2_12 - [15:0] - read-only - - - - - BOOTKEY2_13 - 0x000002b4 - Bits 223:208 of SHA-256 hash of boot key 2 (ECC) - 0x00000000 - - - BOOTKEY2_13 - [15:0] - read-only - - - - - BOOTKEY2_14 - 0x000002b8 - Bits 239:224 of SHA-256 hash of boot key 2 (ECC) - 0x00000000 - - - BOOTKEY2_14 - [15:0] - read-only - - - - - BOOTKEY2_15 - 0x000002bc - Bits 255:240 of SHA-256 hash of boot key 2 (ECC) - 0x00000000 - - - BOOTKEY2_15 - [15:0] - read-only - - - - - BOOTKEY3_0 - 0x000002c0 - Bits 15:0 of SHA-256 hash of boot key 3 (ECC) - 0x00000000 - - - BOOTKEY3_0 - [15:0] - read-only - - - - - BOOTKEY3_1 - 0x000002c4 - Bits 31:16 of SHA-256 hash of boot key 3 (ECC) - 0x00000000 - - - BOOTKEY3_1 - [15:0] - read-only - - - - - BOOTKEY3_2 - 0x000002c8 - Bits 47:32 of SHA-256 hash of boot key 3 (ECC) - 0x00000000 - - - BOOTKEY3_2 - [15:0] - read-only - - - - - BOOTKEY3_3 - 0x000002cc - Bits 63:48 of SHA-256 hash of boot key 3 (ECC) - 0x00000000 - - - BOOTKEY3_3 - [15:0] - read-only - - - - - BOOTKEY3_4 - 0x000002d0 - Bits 79:64 of SHA-256 hash of boot key 3 (ECC) - 0x00000000 - - - BOOTKEY3_4 - [15:0] - read-only - - - - - BOOTKEY3_5 - 0x000002d4 - Bits 95:80 of SHA-256 hash of boot key 3 (ECC) - 0x00000000 - - - BOOTKEY3_5 - [15:0] - read-only - - - - - BOOTKEY3_6 - 0x000002d8 - Bits 111:96 of SHA-256 hash of boot key 3 (ECC) - 0x00000000 - - - BOOTKEY3_6 - [15:0] - read-only - - - - - BOOTKEY3_7 - 0x000002dc - Bits 127:112 of SHA-256 hash of boot key 3 (ECC) - 0x00000000 - - - BOOTKEY3_7 - [15:0] - read-only - - - - - BOOTKEY3_8 - 0x000002e0 - Bits 143:128 of SHA-256 hash of boot key 3 (ECC) - 0x00000000 - - - BOOTKEY3_8 - [15:0] - read-only - - - - - BOOTKEY3_9 - 0x000002e4 - Bits 159:144 of SHA-256 hash of boot key 3 (ECC) - 0x00000000 - - - BOOTKEY3_9 - [15:0] - read-only - - - - - BOOTKEY3_10 - 0x000002e8 - Bits 175:160 of SHA-256 hash of boot key 3 (ECC) - 0x00000000 - - - BOOTKEY3_10 - [15:0] - read-only - - - - - BOOTKEY3_11 - 0x000002ec - Bits 191:176 of SHA-256 hash of boot key 3 (ECC) - 0x00000000 - - - BOOTKEY3_11 - [15:0] - read-only - - - - - BOOTKEY3_12 - 0x000002f0 - Bits 207:192 of SHA-256 hash of boot key 3 (ECC) - 0x00000000 - - - BOOTKEY3_12 - [15:0] - read-only - - - - - BOOTKEY3_13 - 0x000002f4 - Bits 223:208 of SHA-256 hash of boot key 3 (ECC) - 0x00000000 - - - BOOTKEY3_13 - [15:0] - read-only - - - - - BOOTKEY3_14 - 0x000002f8 - Bits 239:224 of SHA-256 hash of boot key 3 (ECC) - 0x00000000 - - - BOOTKEY3_14 - [15:0] - read-only - - - - - BOOTKEY3_15 - 0x000002fc - Bits 255:240 of SHA-256 hash of boot key 3 (ECC) - 0x00000000 - - - BOOTKEY3_15 - [15:0] - read-only - - - - - KEY1_0 - 0x00003d20 - Bits 15:0 of OTP access key 1 (ECC) - 0x00000000 - - - KEY1_0 - [15:0] - read-only - - - - - KEY1_1 - 0x00003d24 - Bits 31:16 of OTP access key 1 (ECC) - 0x00000000 - - - KEY1_1 - [15:0] - read-only - - - - - KEY1_2 - 0x00003d28 - Bits 47:32 of OTP access key 1 (ECC) - 0x00000000 - - - KEY1_2 - [15:0] - read-only - - - - - KEY1_3 - 0x00003d2c - Bits 63:48 of OTP access key 1 (ECC) - 0x00000000 - - - KEY1_3 - [15:0] - read-only - - - - - KEY1_4 - 0x00003d30 - Bits 79:64 of OTP access key 1 (ECC) - 0x00000000 - - - KEY1_4 - [15:0] - read-only - - - - - KEY1_5 - 0x00003d34 - Bits 95:80 of OTP access key 1 (ECC) - 0x00000000 - - - KEY1_5 - [15:0] - read-only - - - - - KEY1_6 - 0x00003d38 - Bits 111:96 of OTP access key 1 (ECC) - 0x00000000 - - - KEY1_6 - [15:0] - read-only - - - - - KEY1_7 - 0x00003d3c - Bits 127:112 of OTP access key 1 (ECC) - 0x00000000 - - - KEY1_7 - [15:0] - read-only - - - - - KEY2_0 - 0x00003d40 - Bits 15:0 of OTP access key 2 (ECC) - 0x00000000 - - - KEY2_0 - [15:0] - read-only - - - - - KEY2_1 - 0x00003d44 - Bits 31:16 of OTP access key 2 (ECC) - 0x00000000 - - - KEY2_1 - [15:0] - read-only - - - - - KEY2_2 - 0x00003d48 - Bits 47:32 of OTP access key 2 (ECC) - 0x00000000 - - - KEY2_2 - [15:0] - read-only - - - - - KEY2_3 - 0x00003d4c - Bits 63:48 of OTP access key 2 (ECC) - 0x00000000 - - - KEY2_3 - [15:0] - read-only - - - - - KEY2_4 - 0x00003d50 - Bits 79:64 of OTP access key 2 (ECC) - 0x00000000 - - - KEY2_4 - [15:0] - read-only - - - - - KEY2_5 - 0x00003d54 - Bits 95:80 of OTP access key 2 (ECC) - 0x00000000 - - - KEY2_5 - [15:0] - read-only - - - - - KEY2_6 - 0x00003d58 - Bits 111:96 of OTP access key 2 (ECC) - 0x00000000 - - - KEY2_6 - [15:0] - read-only - - - - - KEY2_7 - 0x00003d5c - Bits 127:112 of OTP access key 2 (ECC) - 0x00000000 - - - KEY2_7 - [15:0] - read-only - - - - - KEY3_0 - 0x00003d60 - Bits 15:0 of OTP access key 3 (ECC) - 0x00000000 - - - KEY3_0 - [15:0] - read-only - - - - - KEY3_1 - 0x00003d64 - Bits 31:16 of OTP access key 3 (ECC) - 0x00000000 - - - KEY3_1 - [15:0] - read-only - - - - - KEY3_2 - 0x00003d68 - Bits 47:32 of OTP access key 3 (ECC) - 0x00000000 - - - KEY3_2 - [15:0] - read-only - - - - - KEY3_3 - 0x00003d6c - Bits 63:48 of OTP access key 3 (ECC) - 0x00000000 - - - KEY3_3 - [15:0] - read-only - - - - - KEY3_4 - 0x00003d70 - Bits 79:64 of OTP access key 3 (ECC) - 0x00000000 - - - KEY3_4 - [15:0] - read-only - - - - - KEY3_5 - 0x00003d74 - Bits 95:80 of OTP access key 3 (ECC) - 0x00000000 - - - KEY3_5 - [15:0] - read-only - - - - - KEY3_6 - 0x00003d78 - Bits 111:96 of OTP access key 3 (ECC) - 0x00000000 - - - KEY3_6 - [15:0] - read-only - - - - - KEY3_7 - 0x00003d7c - Bits 127:112 of OTP access key 3 (ECC) - 0x00000000 - - - KEY3_7 - [15:0] - read-only - - - - - KEY4_0 - 0x00003d80 - Bits 15:0 of OTP access key 4 (ECC) - 0x00000000 - - - KEY4_0 - [15:0] - read-only - - - - - KEY4_1 - 0x00003d84 - Bits 31:16 of OTP access key 4 (ECC) - 0x00000000 - - - KEY4_1 - [15:0] - read-only - - - - - KEY4_2 - 0x00003d88 - Bits 47:32 of OTP access key 4 (ECC) - 0x00000000 - - - KEY4_2 - [15:0] - read-only - - - - - KEY4_3 - 0x00003d8c - Bits 63:48 of OTP access key 4 (ECC) - 0x00000000 - - - KEY4_3 - [15:0] - read-only - - - - - KEY4_4 - 0x00003d90 - Bits 79:64 of OTP access key 4 (ECC) - 0x00000000 - - - KEY4_4 - [15:0] - read-only - - - - - KEY4_5 - 0x00003d94 - Bits 95:80 of OTP access key 4 (ECC) - 0x00000000 - - - KEY4_5 - [15:0] - read-only - - - - - KEY4_6 - 0x00003d98 - Bits 111:96 of OTP access key 4 (ECC) - 0x00000000 - - - KEY4_6 - [15:0] - read-only - - - - - KEY4_7 - 0x00003d9c - Bits 127:112 of OTP access key 4 (ECC) - 0x00000000 - - - KEY4_7 - [15:0] - read-only - - - - - KEY5_0 - 0x00003da0 - Bits 15:0 of OTP access key 5 (ECC) - 0x00000000 - - - KEY5_0 - [15:0] - read-only - - - - - KEY5_1 - 0x00003da4 - Bits 31:16 of OTP access key 5 (ECC) - 0x00000000 - - - KEY5_1 - [15:0] - read-only - - - - - KEY5_2 - 0x00003da8 - Bits 47:32 of OTP access key 5 (ECC) - 0x00000000 - - - KEY5_2 - [15:0] - read-only - - - - - KEY5_3 - 0x00003dac - Bits 63:48 of OTP access key 5 (ECC) - 0x00000000 - - - KEY5_3 - [15:0] - read-only - - - - - KEY5_4 - 0x00003db0 - Bits 79:64 of OTP access key 5 (ECC) - 0x00000000 - - - KEY5_4 - [15:0] - read-only - - - - - KEY5_5 - 0x00003db4 - Bits 95:80 of OTP access key 5 (ECC) - 0x00000000 - - - KEY5_5 - [15:0] - read-only - - - - - KEY5_6 - 0x00003db8 - Bits 111:96 of OTP access key 5 (ECC) - 0x00000000 - - - KEY5_6 - [15:0] - read-only - - - - - KEY5_7 - 0x00003dbc - Bits 127:112 of OTP access key 5 (ECC) - 0x00000000 - - - KEY5_7 - [15:0] - read-only - - - - - KEY6_0 - 0x00003dc0 - Bits 15:0 of OTP access key 6 (ECC) - 0x00000000 - - - KEY6_0 - [15:0] - read-only - - - - - KEY6_1 - 0x00003dc4 - Bits 31:16 of OTP access key 6 (ECC) - 0x00000000 - - - KEY6_1 - [15:0] - read-only - - - - - KEY6_2 - 0x00003dc8 - Bits 47:32 of OTP access key 6 (ECC) - 0x00000000 - - - KEY6_2 - [15:0] - read-only - - - - - KEY6_3 - 0x00003dcc - Bits 63:48 of OTP access key 6 (ECC) - 0x00000000 - - - KEY6_3 - [15:0] - read-only - - - - - KEY6_4 - 0x00003dd0 - Bits 79:64 of OTP access key 6 (ECC) - 0x00000000 - - - KEY6_4 - [15:0] - read-only - - - - - KEY6_5 - 0x00003dd4 - Bits 95:80 of OTP access key 6 (ECC) - 0x00000000 - - - KEY6_5 - [15:0] - read-only - - - - - KEY6_6 - 0x00003dd8 - Bits 111:96 of OTP access key 6 (ECC) - 0x00000000 - - - KEY6_6 - [15:0] - read-only - - - - - KEY6_7 - 0x00003ddc - Bits 127:112 of OTP access key 6 (ECC) - 0x00000000 - - - KEY6_7 - [15:0] - read-only - - - - - KEY1_VALID - 0x00003de4 - Valid flag for key 1. Once the valid flag is set, the key can no longer be read or written, and becomes a valid fixed key for protecting OTP pages. - 0x00000000 - - - VALID_R2 - Redundant copy of VALID, with 3-way majority vote - [16:16] - read-only - - - VALID_R1 - Redundant copy of VALID, with 3-way majority vote - [8:8] - read-only - - - VALID - [0:0] - read-only - - - - - KEY2_VALID - 0x00003de8 - Valid flag for key 2. Once the valid flag is set, the key can no longer be read or written, and becomes a valid fixed key for protecting OTP pages. - 0x00000000 - - - VALID_R2 - Redundant copy of VALID, with 3-way majority vote - [16:16] - read-only - - - VALID_R1 - Redundant copy of VALID, with 3-way majority vote - [8:8] - read-only - - - VALID - [0:0] - read-only - - - - - KEY3_VALID - 0x00003dec - Valid flag for key 3. Once the valid flag is set, the key can no longer be read or written, and becomes a valid fixed key for protecting OTP pages. - 0x00000000 - - - VALID_R2 - Redundant copy of VALID, with 3-way majority vote - [16:16] - read-only - - - VALID_R1 - Redundant copy of VALID, with 3-way majority vote - [8:8] - read-only - - - VALID - [0:0] - read-only - - - - - KEY4_VALID - 0x00003df0 - Valid flag for key 4. Once the valid flag is set, the key can no longer be read or written, and becomes a valid fixed key for protecting OTP pages. - 0x00000000 - - - VALID_R2 - Redundant copy of VALID, with 3-way majority vote - [16:16] - read-only - - - VALID_R1 - Redundant copy of VALID, with 3-way majority vote - [8:8] - read-only - - - VALID - [0:0] - read-only - - - - - KEY5_VALID - 0x00003df4 - Valid flag for key 5. Once the valid flag is set, the key can no longer be read or written, and becomes a valid fixed key for protecting OTP pages. - 0x00000000 - - - VALID_R2 - Redundant copy of VALID, with 3-way majority vote - [16:16] - read-only - - - VALID_R1 - Redundant copy of VALID, with 3-way majority vote - [8:8] - read-only - - - VALID - [0:0] - read-only - - - - - KEY6_VALID - 0x00003df8 - Valid flag for key 6. Once the valid flag is set, the key can no longer be read or written, and becomes a valid fixed key for protecting OTP pages. - 0x00000000 - - - VALID_R2 - Redundant copy of VALID, with 3-way majority vote - [16:16] - read-only - - - VALID_R1 - Redundant copy of VALID, with 3-way majority vote - [8:8] - read-only - - - VALID - [0:0] - read-only - - - - - PAGE0_LOCK0 - 0x00003e00 - Lock configuration LSBs for page 0 (rows 0x0 through 0x3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - NO_KEY_STATE - State when at least one key is registered for this page and no matching key has been entered. - [6:6] - read-only - - - read_only - 0 - - - inaccessible - 1 - - - - - KEY_R - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. - [5:3] - read-only - - - KEY_W - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. - [2:0] - read-only - - - - - PAGE0_LOCK1 - 0x00003e04 - Lock configuration MSBs for page 0 (rows 0x0 through 0x3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - LOCK_BL - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. - [5:4] - read-only - - - read_write - 0 - Bootloader permits user reads and writes to this page - - - read_only - 1 - Bootloader permits user reads of this page - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE - - - inaccessible - 3 - Bootloader does not permit user access to this page - - - - - LOCK_NS - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - - Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. - [3:2] - read-only - - - read_write - 0 - Page can be read by Non-secure software, and Secure software may permit Non-secure writes. - - - read_only - 1 - Page can be read by Non-secure software - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE. - - - inaccessible - 3 - Page can not be accessed by Non-secure software. - - - - - LOCK_S - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - [1:0] - read-only - - - read_write - 0 - Page is fully accessible by Secure software. - - - read_only - 1 - Page can be read by Secure software, but can not be written. - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE. - - - inaccessible - 3 - Page can not be accessed by Secure software. - - - - - - - PAGE1_LOCK0 - 0x00003e08 - Lock configuration LSBs for page 1 (rows 0x40 through 0x7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - NO_KEY_STATE - State when at least one key is registered for this page and no matching key has been entered. - [6:6] - read-only - - - read_only - 0 - - - inaccessible - 1 - - - - - KEY_R - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. - [5:3] - read-only - - - KEY_W - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. - [2:0] - read-only - - - - - PAGE1_LOCK1 - 0x00003e0c - Lock configuration MSBs for page 1 (rows 0x40 through 0x7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - LOCK_BL - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. - [5:4] - read-only - - - read_write - 0 - Bootloader permits user reads and writes to this page - - - read_only - 1 - Bootloader permits user reads of this page - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE - - - inaccessible - 3 - Bootloader does not permit user access to this page - - - - - LOCK_NS - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - - Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. - [3:2] - read-only - - - read_write - 0 - Page can be read by Non-secure software, and Secure software may permit Non-secure writes. - - - read_only - 1 - Page can be read by Non-secure software - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE. - - - inaccessible - 3 - Page can not be accessed by Non-secure software. - - - - - LOCK_S - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - [1:0] - read-only - - - read_write - 0 - Page is fully accessible by Secure software. - - - read_only - 1 - Page can be read by Secure software, but can not be written. - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE. - - - inaccessible - 3 - Page can not be accessed by Secure software. - - - - - - - PAGE2_LOCK0 - 0x00003e10 - Lock configuration LSBs for page 2 (rows 0x80 through 0xbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - NO_KEY_STATE - State when at least one key is registered for this page and no matching key has been entered. - [6:6] - read-only - - - read_only - 0 - - - inaccessible - 1 - - - - - KEY_R - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. - [5:3] - read-only - - - KEY_W - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. - [2:0] - read-only - - - - - PAGE2_LOCK1 - 0x00003e14 - Lock configuration MSBs for page 2 (rows 0x80 through 0xbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - LOCK_BL - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. - [5:4] - read-only - - - read_write - 0 - Bootloader permits user reads and writes to this page - - - read_only - 1 - Bootloader permits user reads of this page - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE - - - inaccessible - 3 - Bootloader does not permit user access to this page - - - - - LOCK_NS - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - - Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. - [3:2] - read-only - - - read_write - 0 - Page can be read by Non-secure software, and Secure software may permit Non-secure writes. - - - read_only - 1 - Page can be read by Non-secure software - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE. - - - inaccessible - 3 - Page can not be accessed by Non-secure software. - - - - - LOCK_S - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - [1:0] - read-only - - - read_write - 0 - Page is fully accessible by Secure software. - - - read_only - 1 - Page can be read by Secure software, but can not be written. - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE. - - - inaccessible - 3 - Page can not be accessed by Secure software. - - - - - - - PAGE3_LOCK0 - 0x00003e18 - Lock configuration LSBs for page 3 (rows 0xc0 through 0xff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - NO_KEY_STATE - State when at least one key is registered for this page and no matching key has been entered. - [6:6] - read-only - - - read_only - 0 - - - inaccessible - 1 - - - - - KEY_R - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. - [5:3] - read-only - - - KEY_W - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. - [2:0] - read-only - - - - - PAGE3_LOCK1 - 0x00003e1c - Lock configuration MSBs for page 3 (rows 0xc0 through 0xff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - LOCK_BL - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. - [5:4] - read-only - - - read_write - 0 - Bootloader permits user reads and writes to this page - - - read_only - 1 - Bootloader permits user reads of this page - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE - - - inaccessible - 3 - Bootloader does not permit user access to this page - - - - - LOCK_NS - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - - Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. - [3:2] - read-only - - - read_write - 0 - Page can be read by Non-secure software, and Secure software may permit Non-secure writes. - - - read_only - 1 - Page can be read by Non-secure software - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE. - - - inaccessible - 3 - Page can not be accessed by Non-secure software. - - - - - LOCK_S - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - [1:0] - read-only - - - read_write - 0 - Page is fully accessible by Secure software. - - - read_only - 1 - Page can be read by Secure software, but can not be written. - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE. - - - inaccessible - 3 - Page can not be accessed by Secure software. - - - - - - - PAGE4_LOCK0 - 0x00003e20 - Lock configuration LSBs for page 4 (rows 0x100 through 0x13f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - NO_KEY_STATE - State when at least one key is registered for this page and no matching key has been entered. - [6:6] - read-only - - - read_only - 0 - - - inaccessible - 1 - - - - - KEY_R - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. - [5:3] - read-only - - - KEY_W - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. - [2:0] - read-only - - - - - PAGE4_LOCK1 - 0x00003e24 - Lock configuration MSBs for page 4 (rows 0x100 through 0x13f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - LOCK_BL - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. - [5:4] - read-only - - - read_write - 0 - Bootloader permits user reads and writes to this page - - - read_only - 1 - Bootloader permits user reads of this page - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE - - - inaccessible - 3 - Bootloader does not permit user access to this page - - - - - LOCK_NS - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - - Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. - [3:2] - read-only - - - read_write - 0 - Page can be read by Non-secure software, and Secure software may permit Non-secure writes. - - - read_only - 1 - Page can be read by Non-secure software - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE. - - - inaccessible - 3 - Page can not be accessed by Non-secure software. - - - - - LOCK_S - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - [1:0] - read-only - - - read_write - 0 - Page is fully accessible by Secure software. - - - read_only - 1 - Page can be read by Secure software, but can not be written. - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE. - - - inaccessible - 3 - Page can not be accessed by Secure software. - - - - - - - PAGE5_LOCK0 - 0x00003e28 - Lock configuration LSBs for page 5 (rows 0x140 through 0x17f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - NO_KEY_STATE - State when at least one key is registered for this page and no matching key has been entered. - [6:6] - read-only - - - read_only - 0 - - - inaccessible - 1 - - - - - KEY_R - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. - [5:3] - read-only - - - KEY_W - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. - [2:0] - read-only - - - - - PAGE5_LOCK1 - 0x00003e2c - Lock configuration MSBs for page 5 (rows 0x140 through 0x17f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - LOCK_BL - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. - [5:4] - read-only - - - read_write - 0 - Bootloader permits user reads and writes to this page - - - read_only - 1 - Bootloader permits user reads of this page - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE - - - inaccessible - 3 - Bootloader does not permit user access to this page - - - - - LOCK_NS - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - - Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. - [3:2] - read-only - - - read_write - 0 - Page can be read by Non-secure software, and Secure software may permit Non-secure writes. - - - read_only - 1 - Page can be read by Non-secure software - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE. - - - inaccessible - 3 - Page can not be accessed by Non-secure software. - - - - - LOCK_S - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - [1:0] - read-only - - - read_write - 0 - Page is fully accessible by Secure software. - - - read_only - 1 - Page can be read by Secure software, but can not be written. - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE. - - - inaccessible - 3 - Page can not be accessed by Secure software. - - - - - - - PAGE6_LOCK0 - 0x00003e30 - Lock configuration LSBs for page 6 (rows 0x180 through 0x1bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - NO_KEY_STATE - State when at least one key is registered for this page and no matching key has been entered. - [6:6] - read-only - - - read_only - 0 - - - inaccessible - 1 - - - - - KEY_R - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. - [5:3] - read-only - - - KEY_W - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. - [2:0] - read-only - - - - - PAGE6_LOCK1 - 0x00003e34 - Lock configuration MSBs for page 6 (rows 0x180 through 0x1bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - LOCK_BL - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. - [5:4] - read-only - - - read_write - 0 - Bootloader permits user reads and writes to this page - - - read_only - 1 - Bootloader permits user reads of this page - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE - - - inaccessible - 3 - Bootloader does not permit user access to this page - - - - - LOCK_NS - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - - Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. - [3:2] - read-only - - - read_write - 0 - Page can be read by Non-secure software, and Secure software may permit Non-secure writes. - - - read_only - 1 - Page can be read by Non-secure software - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE. - - - inaccessible - 3 - Page can not be accessed by Non-secure software. - - - - - LOCK_S - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - [1:0] - read-only - - - read_write - 0 - Page is fully accessible by Secure software. - - - read_only - 1 - Page can be read by Secure software, but can not be written. - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE. - - - inaccessible - 3 - Page can not be accessed by Secure software. - - - - - - - PAGE7_LOCK0 - 0x00003e38 - Lock configuration LSBs for page 7 (rows 0x1c0 through 0x1ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - NO_KEY_STATE - State when at least one key is registered for this page and no matching key has been entered. - [6:6] - read-only - - - read_only - 0 - - - inaccessible - 1 - - - - - KEY_R - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. - [5:3] - read-only - - - KEY_W - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. - [2:0] - read-only - - - - - PAGE7_LOCK1 - 0x00003e3c - Lock configuration MSBs for page 7 (rows 0x1c0 through 0x1ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - LOCK_BL - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. - [5:4] - read-only - - - read_write - 0 - Bootloader permits user reads and writes to this page - - - read_only - 1 - Bootloader permits user reads of this page - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE - - - inaccessible - 3 - Bootloader does not permit user access to this page - - - - - LOCK_NS - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - - Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. - [3:2] - read-only - - - read_write - 0 - Page can be read by Non-secure software, and Secure software may permit Non-secure writes. - - - read_only - 1 - Page can be read by Non-secure software - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE. - - - inaccessible - 3 - Page can not be accessed by Non-secure software. - - - - - LOCK_S - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - [1:0] - read-only - - - read_write - 0 - Page is fully accessible by Secure software. - - - read_only - 1 - Page can be read by Secure software, but can not be written. - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE. - - - inaccessible - 3 - Page can not be accessed by Secure software. - - - - - - - PAGE8_LOCK0 - 0x00003e40 - Lock configuration LSBs for page 8 (rows 0x200 through 0x23f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - NO_KEY_STATE - State when at least one key is registered for this page and no matching key has been entered. - [6:6] - read-only - - - read_only - 0 - - - inaccessible - 1 - - - - - KEY_R - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. - [5:3] - read-only - - - KEY_W - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. - [2:0] - read-only - - - - - PAGE8_LOCK1 - 0x00003e44 - Lock configuration MSBs for page 8 (rows 0x200 through 0x23f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - LOCK_BL - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. - [5:4] - read-only - - - read_write - 0 - Bootloader permits user reads and writes to this page - - - read_only - 1 - Bootloader permits user reads of this page - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE - - - inaccessible - 3 - Bootloader does not permit user access to this page - - - - - LOCK_NS - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - - Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. - [3:2] - read-only - - - read_write - 0 - Page can be read by Non-secure software, and Secure software may permit Non-secure writes. - - - read_only - 1 - Page can be read by Non-secure software - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE. - - - inaccessible - 3 - Page can not be accessed by Non-secure software. - - - - - LOCK_S - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - [1:0] - read-only - - - read_write - 0 - Page is fully accessible by Secure software. - - - read_only - 1 - Page can be read by Secure software, but can not be written. - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE. - - - inaccessible - 3 - Page can not be accessed by Secure software. - - - - - - - PAGE9_LOCK0 - 0x00003e48 - Lock configuration LSBs for page 9 (rows 0x240 through 0x27f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - NO_KEY_STATE - State when at least one key is registered for this page and no matching key has been entered. - [6:6] - read-only - - - read_only - 0 - - - inaccessible - 1 - - - - - KEY_R - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. - [5:3] - read-only - - - KEY_W - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. - [2:0] - read-only - - - - - PAGE9_LOCK1 - 0x00003e4c - Lock configuration MSBs for page 9 (rows 0x240 through 0x27f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - LOCK_BL - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. - [5:4] - read-only - - - read_write - 0 - Bootloader permits user reads and writes to this page - - - read_only - 1 - Bootloader permits user reads of this page - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE - - - inaccessible - 3 - Bootloader does not permit user access to this page - - - - - LOCK_NS - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - - Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. - [3:2] - read-only - - - read_write - 0 - Page can be read by Non-secure software, and Secure software may permit Non-secure writes. - - - read_only - 1 - Page can be read by Non-secure software - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE. - - - inaccessible - 3 - Page can not be accessed by Non-secure software. - - - - - LOCK_S - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - [1:0] - read-only - - - read_write - 0 - Page is fully accessible by Secure software. - - - read_only - 1 - Page can be read by Secure software, but can not be written. - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE. - - - inaccessible - 3 - Page can not be accessed by Secure software. - - - - - - - PAGE10_LOCK0 - 0x00003e50 - Lock configuration LSBs for page 10 (rows 0x280 through 0x2bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - NO_KEY_STATE - State when at least one key is registered for this page and no matching key has been entered. - [6:6] - read-only - - - read_only - 0 - - - inaccessible - 1 - - - - - KEY_R - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. - [5:3] - read-only - - - KEY_W - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. - [2:0] - read-only - - - - - PAGE10_LOCK1 - 0x00003e54 - Lock configuration MSBs for page 10 (rows 0x280 through 0x2bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - LOCK_BL - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. - [5:4] - read-only - - - read_write - 0 - Bootloader permits user reads and writes to this page - - - read_only - 1 - Bootloader permits user reads of this page - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE - - - inaccessible - 3 - Bootloader does not permit user access to this page - - - - - LOCK_NS - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - - Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. - [3:2] - read-only - - - read_write - 0 - Page can be read by Non-secure software, and Secure software may permit Non-secure writes. - - - read_only - 1 - Page can be read by Non-secure software - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE. - - - inaccessible - 3 - Page can not be accessed by Non-secure software. - - - - - LOCK_S - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - [1:0] - read-only - - - read_write - 0 - Page is fully accessible by Secure software. - - - read_only - 1 - Page can be read by Secure software, but can not be written. - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE. - - - inaccessible - 3 - Page can not be accessed by Secure software. - - - - - - - PAGE11_LOCK0 - 0x00003e58 - Lock configuration LSBs for page 11 (rows 0x2c0 through 0x2ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - NO_KEY_STATE - State when at least one key is registered for this page and no matching key has been entered. - [6:6] - read-only - - - read_only - 0 - - - inaccessible - 1 - - - - - KEY_R - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. - [5:3] - read-only - - - KEY_W - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. - [2:0] - read-only - - - - - PAGE11_LOCK1 - 0x00003e5c - Lock configuration MSBs for page 11 (rows 0x2c0 through 0x2ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - LOCK_BL - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. - [5:4] - read-only - - - read_write - 0 - Bootloader permits user reads and writes to this page - - - read_only - 1 - Bootloader permits user reads of this page - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE - - - inaccessible - 3 - Bootloader does not permit user access to this page - - - - - LOCK_NS - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - - Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. - [3:2] - read-only - - - read_write - 0 - Page can be read by Non-secure software, and Secure software may permit Non-secure writes. - - - read_only - 1 - Page can be read by Non-secure software - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE. - - - inaccessible - 3 - Page can not be accessed by Non-secure software. - - - - - LOCK_S - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - [1:0] - read-only - - - read_write - 0 - Page is fully accessible by Secure software. - - - read_only - 1 - Page can be read by Secure software, but can not be written. - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE. - - - inaccessible - 3 - Page can not be accessed by Secure software. - - - - - - - PAGE12_LOCK0 - 0x00003e60 - Lock configuration LSBs for page 12 (rows 0x300 through 0x33f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - NO_KEY_STATE - State when at least one key is registered for this page and no matching key has been entered. - [6:6] - read-only - - - read_only - 0 - - - inaccessible - 1 - - - - - KEY_R - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. - [5:3] - read-only - - - KEY_W - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. - [2:0] - read-only - - - - - PAGE12_LOCK1 - 0x00003e64 - Lock configuration MSBs for page 12 (rows 0x300 through 0x33f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - LOCK_BL - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. - [5:4] - read-only - - - read_write - 0 - Bootloader permits user reads and writes to this page - - - read_only - 1 - Bootloader permits user reads of this page - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE - - - inaccessible - 3 - Bootloader does not permit user access to this page - - - - - LOCK_NS - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - - Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. - [3:2] - read-only - - - read_write - 0 - Page can be read by Non-secure software, and Secure software may permit Non-secure writes. - - - read_only - 1 - Page can be read by Non-secure software - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE. - - - inaccessible - 3 - Page can not be accessed by Non-secure software. - - - - - LOCK_S - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - [1:0] - read-only - - - read_write - 0 - Page is fully accessible by Secure software. - - - read_only - 1 - Page can be read by Secure software, but can not be written. - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE. - - - inaccessible - 3 - Page can not be accessed by Secure software. - - - - - - - PAGE13_LOCK0 - 0x00003e68 - Lock configuration LSBs for page 13 (rows 0x340 through 0x37f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - NO_KEY_STATE - State when at least one key is registered for this page and no matching key has been entered. - [6:6] - read-only - - - read_only - 0 - - - inaccessible - 1 - - - - - KEY_R - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. - [5:3] - read-only - - - KEY_W - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. - [2:0] - read-only - - - - - PAGE13_LOCK1 - 0x00003e6c - Lock configuration MSBs for page 13 (rows 0x340 through 0x37f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - LOCK_BL - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. - [5:4] - read-only - - - read_write - 0 - Bootloader permits user reads and writes to this page - - - read_only - 1 - Bootloader permits user reads of this page - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE - - - inaccessible - 3 - Bootloader does not permit user access to this page - - - - - LOCK_NS - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - - Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. - [3:2] - read-only - - - read_write - 0 - Page can be read by Non-secure software, and Secure software may permit Non-secure writes. - - - read_only - 1 - Page can be read by Non-secure software - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE. - - - inaccessible - 3 - Page can not be accessed by Non-secure software. - - - - - LOCK_S - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - [1:0] - read-only - - - read_write - 0 - Page is fully accessible by Secure software. - - - read_only - 1 - Page can be read by Secure software, but can not be written. - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE. - - - inaccessible - 3 - Page can not be accessed by Secure software. - - - - - - - PAGE14_LOCK0 - 0x00003e70 - Lock configuration LSBs for page 14 (rows 0x380 through 0x3bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - NO_KEY_STATE - State when at least one key is registered for this page and no matching key has been entered. - [6:6] - read-only - - - read_only - 0 - - - inaccessible - 1 - - - - - KEY_R - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. - [5:3] - read-only - - - KEY_W - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. - [2:0] - read-only - - - - - PAGE14_LOCK1 - 0x00003e74 - Lock configuration MSBs for page 14 (rows 0x380 through 0x3bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - LOCK_BL - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. - [5:4] - read-only - - - read_write - 0 - Bootloader permits user reads and writes to this page - - - read_only - 1 - Bootloader permits user reads of this page - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE - - - inaccessible - 3 - Bootloader does not permit user access to this page - - - - - LOCK_NS - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - - Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. - [3:2] - read-only - - - read_write - 0 - Page can be read by Non-secure software, and Secure software may permit Non-secure writes. - - - read_only - 1 - Page can be read by Non-secure software - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE. - - - inaccessible - 3 - Page can not be accessed by Non-secure software. - - - - - LOCK_S - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - [1:0] - read-only - - - read_write - 0 - Page is fully accessible by Secure software. - - - read_only - 1 - Page can be read by Secure software, but can not be written. - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE. - - - inaccessible - 3 - Page can not be accessed by Secure software. - - - - - - - PAGE15_LOCK0 - 0x00003e78 - Lock configuration LSBs for page 15 (rows 0x3c0 through 0x3ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - NO_KEY_STATE - State when at least one key is registered for this page and no matching key has been entered. - [6:6] - read-only - - - read_only - 0 - - - inaccessible - 1 - - - - - KEY_R - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. - [5:3] - read-only - - - KEY_W - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. - [2:0] - read-only - - - - - PAGE15_LOCK1 - 0x00003e7c - Lock configuration MSBs for page 15 (rows 0x3c0 through 0x3ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - LOCK_BL - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. - [5:4] - read-only - - - read_write - 0 - Bootloader permits user reads and writes to this page - - - read_only - 1 - Bootloader permits user reads of this page - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE - - - inaccessible - 3 - Bootloader does not permit user access to this page - - - - - LOCK_NS - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - - Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. - [3:2] - read-only - - - read_write - 0 - Page can be read by Non-secure software, and Secure software may permit Non-secure writes. - - - read_only - 1 - Page can be read by Non-secure software - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE. - - - inaccessible - 3 - Page can not be accessed by Non-secure software. - - - - - LOCK_S - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - [1:0] - read-only - - - read_write - 0 - Page is fully accessible by Secure software. - - - read_only - 1 - Page can be read by Secure software, but can not be written. - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE. - - - inaccessible - 3 - Page can not be accessed by Secure software. - - - - - - - PAGE16_LOCK0 - 0x00003e80 - Lock configuration LSBs for page 16 (rows 0x400 through 0x43f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - NO_KEY_STATE - State when at least one key is registered for this page and no matching key has been entered. - [6:6] - read-only - - - read_only - 0 - - - inaccessible - 1 - - - - - KEY_R - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. - [5:3] - read-only - - - KEY_W - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. - [2:0] - read-only - - - - - PAGE16_LOCK1 - 0x00003e84 - Lock configuration MSBs for page 16 (rows 0x400 through 0x43f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - LOCK_BL - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. - [5:4] - read-only - - - read_write - 0 - Bootloader permits user reads and writes to this page - - - read_only - 1 - Bootloader permits user reads of this page - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE - - - inaccessible - 3 - Bootloader does not permit user access to this page - - - - - LOCK_NS - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - - Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. - [3:2] - read-only - - - read_write - 0 - Page can be read by Non-secure software, and Secure software may permit Non-secure writes. - - - read_only - 1 - Page can be read by Non-secure software - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE. - - - inaccessible - 3 - Page can not be accessed by Non-secure software. - - - - - LOCK_S - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - [1:0] - read-only - - - read_write - 0 - Page is fully accessible by Secure software. - - - read_only - 1 - Page can be read by Secure software, but can not be written. - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE. - - - inaccessible - 3 - Page can not be accessed by Secure software. - - - - - - - PAGE17_LOCK0 - 0x00003e88 - Lock configuration LSBs for page 17 (rows 0x440 through 0x47f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - NO_KEY_STATE - State when at least one key is registered for this page and no matching key has been entered. - [6:6] - read-only - - - read_only - 0 - - - inaccessible - 1 - - - - - KEY_R - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. - [5:3] - read-only - - - KEY_W - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. - [2:0] - read-only - - - - - PAGE17_LOCK1 - 0x00003e8c - Lock configuration MSBs for page 17 (rows 0x440 through 0x47f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - LOCK_BL - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. - [5:4] - read-only - - - read_write - 0 - Bootloader permits user reads and writes to this page - - - read_only - 1 - Bootloader permits user reads of this page - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE - - - inaccessible - 3 - Bootloader does not permit user access to this page - - - - - LOCK_NS - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - - Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. - [3:2] - read-only - - - read_write - 0 - Page can be read by Non-secure software, and Secure software may permit Non-secure writes. - - - read_only - 1 - Page can be read by Non-secure software - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE. - - - inaccessible - 3 - Page can not be accessed by Non-secure software. - - - - - LOCK_S - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - [1:0] - read-only - - - read_write - 0 - Page is fully accessible by Secure software. - - - read_only - 1 - Page can be read by Secure software, but can not be written. - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE. - - - inaccessible - 3 - Page can not be accessed by Secure software. - - - - - - - PAGE18_LOCK0 - 0x00003e90 - Lock configuration LSBs for page 18 (rows 0x480 through 0x4bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - NO_KEY_STATE - State when at least one key is registered for this page and no matching key has been entered. - [6:6] - read-only - - - read_only - 0 - - - inaccessible - 1 - - - - - KEY_R - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. - [5:3] - read-only - - - KEY_W - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. - [2:0] - read-only - - - - - PAGE18_LOCK1 - 0x00003e94 - Lock configuration MSBs for page 18 (rows 0x480 through 0x4bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - LOCK_BL - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. - [5:4] - read-only - - - read_write - 0 - Bootloader permits user reads and writes to this page - - - read_only - 1 - Bootloader permits user reads of this page - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE - - - inaccessible - 3 - Bootloader does not permit user access to this page - - - - - LOCK_NS - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - - Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. - [3:2] - read-only - - - read_write - 0 - Page can be read by Non-secure software, and Secure software may permit Non-secure writes. - - - read_only - 1 - Page can be read by Non-secure software - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE. - - - inaccessible - 3 - Page can not be accessed by Non-secure software. - - - - - LOCK_S - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - [1:0] - read-only - - - read_write - 0 - Page is fully accessible by Secure software. - - - read_only - 1 - Page can be read by Secure software, but can not be written. - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE. - - - inaccessible - 3 - Page can not be accessed by Secure software. - - - - - - - PAGE19_LOCK0 - 0x00003e98 - Lock configuration LSBs for page 19 (rows 0x4c0 through 0x4ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - NO_KEY_STATE - State when at least one key is registered for this page and no matching key has been entered. - [6:6] - read-only - - - read_only - 0 - - - inaccessible - 1 - - - - - KEY_R - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. - [5:3] - read-only - - - KEY_W - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. - [2:0] - read-only - - - - - PAGE19_LOCK1 - 0x00003e9c - Lock configuration MSBs for page 19 (rows 0x4c0 through 0x4ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - LOCK_BL - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. - [5:4] - read-only - - - read_write - 0 - Bootloader permits user reads and writes to this page - - - read_only - 1 - Bootloader permits user reads of this page - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE - - - inaccessible - 3 - Bootloader does not permit user access to this page - - - - - LOCK_NS - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - - Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. - [3:2] - read-only - - - read_write - 0 - Page can be read by Non-secure software, and Secure software may permit Non-secure writes. - - - read_only - 1 - Page can be read by Non-secure software - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE. - - - inaccessible - 3 - Page can not be accessed by Non-secure software. - - - - - LOCK_S - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - [1:0] - read-only - - - read_write - 0 - Page is fully accessible by Secure software. - - - read_only - 1 - Page can be read by Secure software, but can not be written. - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE. - - - inaccessible - 3 - Page can not be accessed by Secure software. - - - - - - - PAGE20_LOCK0 - 0x00003ea0 - Lock configuration LSBs for page 20 (rows 0x500 through 0x53f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - NO_KEY_STATE - State when at least one key is registered for this page and no matching key has been entered. - [6:6] - read-only - - - read_only - 0 - - - inaccessible - 1 - - - - - KEY_R - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. - [5:3] - read-only - - - KEY_W - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. - [2:0] - read-only - - - - - PAGE20_LOCK1 - 0x00003ea4 - Lock configuration MSBs for page 20 (rows 0x500 through 0x53f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - LOCK_BL - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. - [5:4] - read-only - - - read_write - 0 - Bootloader permits user reads and writes to this page - - - read_only - 1 - Bootloader permits user reads of this page - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE - - - inaccessible - 3 - Bootloader does not permit user access to this page - - - - - LOCK_NS - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - - Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. - [3:2] - read-only - - - read_write - 0 - Page can be read by Non-secure software, and Secure software may permit Non-secure writes. - - - read_only - 1 - Page can be read by Non-secure software - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE. - - - inaccessible - 3 - Page can not be accessed by Non-secure software. - - - - - LOCK_S - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - [1:0] - read-only - - - read_write - 0 - Page is fully accessible by Secure software. - - - read_only - 1 - Page can be read by Secure software, but can not be written. - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE. - - - inaccessible - 3 - Page can not be accessed by Secure software. - - - - - - - PAGE21_LOCK0 - 0x00003ea8 - Lock configuration LSBs for page 21 (rows 0x540 through 0x57f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - NO_KEY_STATE - State when at least one key is registered for this page and no matching key has been entered. - [6:6] - read-only - - - read_only - 0 - - - inaccessible - 1 - - - - - KEY_R - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. - [5:3] - read-only - - - KEY_W - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. - [2:0] - read-only - - - - - PAGE21_LOCK1 - 0x00003eac - Lock configuration MSBs for page 21 (rows 0x540 through 0x57f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - LOCK_BL - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. - [5:4] - read-only - - - read_write - 0 - Bootloader permits user reads and writes to this page - - - read_only - 1 - Bootloader permits user reads of this page - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE - - - inaccessible - 3 - Bootloader does not permit user access to this page - - - - - LOCK_NS - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - - Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. - [3:2] - read-only - - - read_write - 0 - Page can be read by Non-secure software, and Secure software may permit Non-secure writes. - - - read_only - 1 - Page can be read by Non-secure software - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE. - - - inaccessible - 3 - Page can not be accessed by Non-secure software. - - - - - LOCK_S - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - [1:0] - read-only - - - read_write - 0 - Page is fully accessible by Secure software. - - - read_only - 1 - Page can be read by Secure software, but can not be written. - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE. - - - inaccessible - 3 - Page can not be accessed by Secure software. - - - - - - - PAGE22_LOCK0 - 0x00003eb0 - Lock configuration LSBs for page 22 (rows 0x580 through 0x5bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - NO_KEY_STATE - State when at least one key is registered for this page and no matching key has been entered. - [6:6] - read-only - - - read_only - 0 - - - inaccessible - 1 - - - - - KEY_R - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. - [5:3] - read-only - - - KEY_W - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. - [2:0] - read-only - - - - - PAGE22_LOCK1 - 0x00003eb4 - Lock configuration MSBs for page 22 (rows 0x580 through 0x5bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - LOCK_BL - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. - [5:4] - read-only - - - read_write - 0 - Bootloader permits user reads and writes to this page - - - read_only - 1 - Bootloader permits user reads of this page - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE - - - inaccessible - 3 - Bootloader does not permit user access to this page - - - - - LOCK_NS - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - - Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. - [3:2] - read-only - - - read_write - 0 - Page can be read by Non-secure software, and Secure software may permit Non-secure writes. - - - read_only - 1 - Page can be read by Non-secure software - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE. - - - inaccessible - 3 - Page can not be accessed by Non-secure software. - - - - - LOCK_S - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - [1:0] - read-only - - - read_write - 0 - Page is fully accessible by Secure software. - - - read_only - 1 - Page can be read by Secure software, but can not be written. - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE. - - - inaccessible - 3 - Page can not be accessed by Secure software. - - - - - - - PAGE23_LOCK0 - 0x00003eb8 - Lock configuration LSBs for page 23 (rows 0x5c0 through 0x5ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - NO_KEY_STATE - State when at least one key is registered for this page and no matching key has been entered. - [6:6] - read-only - - - read_only - 0 - - - inaccessible - 1 - - - - - KEY_R - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. - [5:3] - read-only - - - KEY_W - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. - [2:0] - read-only - - - - - PAGE23_LOCK1 - 0x00003ebc - Lock configuration MSBs for page 23 (rows 0x5c0 through 0x5ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - LOCK_BL - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. - [5:4] - read-only - - - read_write - 0 - Bootloader permits user reads and writes to this page - - - read_only - 1 - Bootloader permits user reads of this page - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE - - - inaccessible - 3 - Bootloader does not permit user access to this page - - - - - LOCK_NS - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - - Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. - [3:2] - read-only - - - read_write - 0 - Page can be read by Non-secure software, and Secure software may permit Non-secure writes. - - - read_only - 1 - Page can be read by Non-secure software - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE. - - - inaccessible - 3 - Page can not be accessed by Non-secure software. - - - - - LOCK_S - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - [1:0] - read-only - - - read_write - 0 - Page is fully accessible by Secure software. - - - read_only - 1 - Page can be read by Secure software, but can not be written. - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE. - - - inaccessible - 3 - Page can not be accessed by Secure software. - - - - - - - PAGE24_LOCK0 - 0x00003ec0 - Lock configuration LSBs for page 24 (rows 0x600 through 0x63f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - NO_KEY_STATE - State when at least one key is registered for this page and no matching key has been entered. - [6:6] - read-only - - - read_only - 0 - - - inaccessible - 1 - - - - - KEY_R - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. - [5:3] - read-only - - - KEY_W - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. - [2:0] - read-only - - - - - PAGE24_LOCK1 - 0x00003ec4 - Lock configuration MSBs for page 24 (rows 0x600 through 0x63f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - LOCK_BL - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. - [5:4] - read-only - - - read_write - 0 - Bootloader permits user reads and writes to this page - - - read_only - 1 - Bootloader permits user reads of this page - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE - - - inaccessible - 3 - Bootloader does not permit user access to this page - - - - - LOCK_NS - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - - Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. - [3:2] - read-only - - - read_write - 0 - Page can be read by Non-secure software, and Secure software may permit Non-secure writes. - - - read_only - 1 - Page can be read by Non-secure software - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE. - - - inaccessible - 3 - Page can not be accessed by Non-secure software. - - - - - LOCK_S - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - [1:0] - read-only - - - read_write - 0 - Page is fully accessible by Secure software. - - - read_only - 1 - Page can be read by Secure software, but can not be written. - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE. - - - inaccessible - 3 - Page can not be accessed by Secure software. - - - - - - - PAGE25_LOCK0 - 0x00003ec8 - Lock configuration LSBs for page 25 (rows 0x640 through 0x67f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - NO_KEY_STATE - State when at least one key is registered for this page and no matching key has been entered. - [6:6] - read-only - - - read_only - 0 - - - inaccessible - 1 - - - - - KEY_R - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. - [5:3] - read-only - - - KEY_W - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. - [2:0] - read-only - - - - - PAGE25_LOCK1 - 0x00003ecc - Lock configuration MSBs for page 25 (rows 0x640 through 0x67f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - LOCK_BL - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. - [5:4] - read-only - - - read_write - 0 - Bootloader permits user reads and writes to this page - - - read_only - 1 - Bootloader permits user reads of this page - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE - - - inaccessible - 3 - Bootloader does not permit user access to this page - - - - - LOCK_NS - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - - Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. - [3:2] - read-only - - - read_write - 0 - Page can be read by Non-secure software, and Secure software may permit Non-secure writes. - - - read_only - 1 - Page can be read by Non-secure software - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE. - - - inaccessible - 3 - Page can not be accessed by Non-secure software. - - - - - LOCK_S - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - [1:0] - read-only - - - read_write - 0 - Page is fully accessible by Secure software. - - - read_only - 1 - Page can be read by Secure software, but can not be written. - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE. - - - inaccessible - 3 - Page can not be accessed by Secure software. - - - - - - - PAGE26_LOCK0 - 0x00003ed0 - Lock configuration LSBs for page 26 (rows 0x680 through 0x6bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - NO_KEY_STATE - State when at least one key is registered for this page and no matching key has been entered. - [6:6] - read-only - - - read_only - 0 - - - inaccessible - 1 - - - - - KEY_R - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. - [5:3] - read-only - - - KEY_W - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. - [2:0] - read-only - - - - - PAGE26_LOCK1 - 0x00003ed4 - Lock configuration MSBs for page 26 (rows 0x680 through 0x6bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - LOCK_BL - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. - [5:4] - read-only - - - read_write - 0 - Bootloader permits user reads and writes to this page - - - read_only - 1 - Bootloader permits user reads of this page - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE - - - inaccessible - 3 - Bootloader does not permit user access to this page - - - - - LOCK_NS - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - - Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. - [3:2] - read-only - - - read_write - 0 - Page can be read by Non-secure software, and Secure software may permit Non-secure writes. - - - read_only - 1 - Page can be read by Non-secure software - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE. - - - inaccessible - 3 - Page can not be accessed by Non-secure software. - - - - - LOCK_S - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - [1:0] - read-only - - - read_write - 0 - Page is fully accessible by Secure software. - - - read_only - 1 - Page can be read by Secure software, but can not be written. - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE. - - - inaccessible - 3 - Page can not be accessed by Secure software. - - - - - - - PAGE27_LOCK0 - 0x00003ed8 - Lock configuration LSBs for page 27 (rows 0x6c0 through 0x6ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - NO_KEY_STATE - State when at least one key is registered for this page and no matching key has been entered. - [6:6] - read-only - - - read_only - 0 - - - inaccessible - 1 - - - - - KEY_R - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. - [5:3] - read-only - - - KEY_W - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. - [2:0] - read-only - - - - - PAGE27_LOCK1 - 0x00003edc - Lock configuration MSBs for page 27 (rows 0x6c0 through 0x6ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - LOCK_BL - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. - [5:4] - read-only - - - read_write - 0 - Bootloader permits user reads and writes to this page - - - read_only - 1 - Bootloader permits user reads of this page - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE - - - inaccessible - 3 - Bootloader does not permit user access to this page - - - - - LOCK_NS - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - - Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. - [3:2] - read-only - - - read_write - 0 - Page can be read by Non-secure software, and Secure software may permit Non-secure writes. - - - read_only - 1 - Page can be read by Non-secure software - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE. - - - inaccessible - 3 - Page can not be accessed by Non-secure software. - - - - - LOCK_S - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - [1:0] - read-only - - - read_write - 0 - Page is fully accessible by Secure software. - - - read_only - 1 - Page can be read by Secure software, but can not be written. - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE. - - - inaccessible - 3 - Page can not be accessed by Secure software. - - - - - - - PAGE28_LOCK0 - 0x00003ee0 - Lock configuration LSBs for page 28 (rows 0x700 through 0x73f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - NO_KEY_STATE - State when at least one key is registered for this page and no matching key has been entered. - [6:6] - read-only - - - read_only - 0 - - - inaccessible - 1 - - - - - KEY_R - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. - [5:3] - read-only - - - KEY_W - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. - [2:0] - read-only - - - - - PAGE28_LOCK1 - 0x00003ee4 - Lock configuration MSBs for page 28 (rows 0x700 through 0x73f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - LOCK_BL - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. - [5:4] - read-only - - - read_write - 0 - Bootloader permits user reads and writes to this page - - - read_only - 1 - Bootloader permits user reads of this page - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE - - - inaccessible - 3 - Bootloader does not permit user access to this page - - - - - LOCK_NS - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - - Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. - [3:2] - read-only - - - read_write - 0 - Page can be read by Non-secure software, and Secure software may permit Non-secure writes. - - - read_only - 1 - Page can be read by Non-secure software - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE. - - - inaccessible - 3 - Page can not be accessed by Non-secure software. - - - - - LOCK_S - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - [1:0] - read-only - - - read_write - 0 - Page is fully accessible by Secure software. - - - read_only - 1 - Page can be read by Secure software, but can not be written. - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE. - - - inaccessible - 3 - Page can not be accessed by Secure software. - - - - - - - PAGE29_LOCK0 - 0x00003ee8 - Lock configuration LSBs for page 29 (rows 0x740 through 0x77f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - NO_KEY_STATE - State when at least one key is registered for this page and no matching key has been entered. - [6:6] - read-only - - - read_only - 0 - - - inaccessible - 1 - - - - - KEY_R - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. - [5:3] - read-only - - - KEY_W - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. - [2:0] - read-only - - - - - PAGE29_LOCK1 - 0x00003eec - Lock configuration MSBs for page 29 (rows 0x740 through 0x77f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - LOCK_BL - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. - [5:4] - read-only - - - read_write - 0 - Bootloader permits user reads and writes to this page - - - read_only - 1 - Bootloader permits user reads of this page - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE - - - inaccessible - 3 - Bootloader does not permit user access to this page - - - - - LOCK_NS - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - - Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. - [3:2] - read-only - - - read_write - 0 - Page can be read by Non-secure software, and Secure software may permit Non-secure writes. - - - read_only - 1 - Page can be read by Non-secure software - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE. - - - inaccessible - 3 - Page can not be accessed by Non-secure software. - - - - - LOCK_S - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - [1:0] - read-only - - - read_write - 0 - Page is fully accessible by Secure software. - - - read_only - 1 - Page can be read by Secure software, but can not be written. - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE. - - - inaccessible - 3 - Page can not be accessed by Secure software. - - - - - - - PAGE30_LOCK0 - 0x00003ef0 - Lock configuration LSBs for page 30 (rows 0x780 through 0x7bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - NO_KEY_STATE - State when at least one key is registered for this page and no matching key has been entered. - [6:6] - read-only - - - read_only - 0 - - - inaccessible - 1 - - - - - KEY_R - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. - [5:3] - read-only - - - KEY_W - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. - [2:0] - read-only - - - - - PAGE30_LOCK1 - 0x00003ef4 - Lock configuration MSBs for page 30 (rows 0x780 through 0x7bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - LOCK_BL - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. - [5:4] - read-only - - - read_write - 0 - Bootloader permits user reads and writes to this page - - - read_only - 1 - Bootloader permits user reads of this page - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE - - - inaccessible - 3 - Bootloader does not permit user access to this page - - - - - LOCK_NS - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - - Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. - [3:2] - read-only - - - read_write - 0 - Page can be read by Non-secure software, and Secure software may permit Non-secure writes. - - - read_only - 1 - Page can be read by Non-secure software - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE. - - - inaccessible - 3 - Page can not be accessed by Non-secure software. - - - - - LOCK_S - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - [1:0] - read-only - - - read_write - 0 - Page is fully accessible by Secure software. - - - read_only - 1 - Page can be read by Secure software, but can not be written. - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE. - - - inaccessible - 3 - Page can not be accessed by Secure software. - - - - - - - PAGE31_LOCK0 - 0x00003ef8 - Lock configuration LSBs for page 31 (rows 0x7c0 through 0x7ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - NO_KEY_STATE - State when at least one key is registered for this page and no matching key has been entered. - [6:6] - read-only - - - read_only - 0 - - - inaccessible - 1 - - - - - KEY_R - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. - [5:3] - read-only - - - KEY_W - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. - [2:0] - read-only - - - - - PAGE31_LOCK1 - 0x00003efc - Lock configuration MSBs for page 31 (rows 0x7c0 through 0x7ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - LOCK_BL - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. - [5:4] - read-only - - - read_write - 0 - Bootloader permits user reads and writes to this page - - - read_only - 1 - Bootloader permits user reads of this page - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE - - - inaccessible - 3 - Bootloader does not permit user access to this page - - - - - LOCK_NS - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - - Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. - [3:2] - read-only - - - read_write - 0 - Page can be read by Non-secure software, and Secure software may permit Non-secure writes. - - - read_only - 1 - Page can be read by Non-secure software - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE. - - - inaccessible - 3 - Page can not be accessed by Non-secure software. - - - - - LOCK_S - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - [1:0] - read-only - - - read_write - 0 - Page is fully accessible by Secure software. - - - read_only - 1 - Page can be read by Secure software, but can not be written. - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE. - - - inaccessible - 3 - Page can not be accessed by Secure software. - - - - - - - PAGE32_LOCK0 - 0x00003f00 - Lock configuration LSBs for page 32 (rows 0x800 through 0x83f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - NO_KEY_STATE - State when at least one key is registered for this page and no matching key has been entered. - [6:6] - read-only - - - read_only - 0 - - - inaccessible - 1 - - - - - KEY_R - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. - [5:3] - read-only - - - KEY_W - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. - [2:0] - read-only - - - - - PAGE32_LOCK1 - 0x00003f04 - Lock configuration MSBs for page 32 (rows 0x800 through 0x83f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - LOCK_BL - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. - [5:4] - read-only - - - read_write - 0 - Bootloader permits user reads and writes to this page - - - read_only - 1 - Bootloader permits user reads of this page - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE - - - inaccessible - 3 - Bootloader does not permit user access to this page - - - - - LOCK_NS - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - - Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. - [3:2] - read-only - - - read_write - 0 - Page can be read by Non-secure software, and Secure software may permit Non-secure writes. - - - read_only - 1 - Page can be read by Non-secure software - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE. - - - inaccessible - 3 - Page can not be accessed by Non-secure software. - - - - - LOCK_S - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - [1:0] - read-only - - - read_write - 0 - Page is fully accessible by Secure software. - - - read_only - 1 - Page can be read by Secure software, but can not be written. - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE. - - - inaccessible - 3 - Page can not be accessed by Secure software. - - - - - - - PAGE33_LOCK0 - 0x00003f08 - Lock configuration LSBs for page 33 (rows 0x840 through 0x87f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - NO_KEY_STATE - State when at least one key is registered for this page and no matching key has been entered. - [6:6] - read-only - - - read_only - 0 - - - inaccessible - 1 - - - - - KEY_R - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. - [5:3] - read-only - - - KEY_W - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. - [2:0] - read-only - - - - - PAGE33_LOCK1 - 0x00003f0c - Lock configuration MSBs for page 33 (rows 0x840 through 0x87f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - LOCK_BL - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. - [5:4] - read-only - - - read_write - 0 - Bootloader permits user reads and writes to this page - - - read_only - 1 - Bootloader permits user reads of this page - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE - - - inaccessible - 3 - Bootloader does not permit user access to this page - - - - - LOCK_NS - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - - Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. - [3:2] - read-only - - - read_write - 0 - Page can be read by Non-secure software, and Secure software may permit Non-secure writes. - - - read_only - 1 - Page can be read by Non-secure software - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE. - - - inaccessible - 3 - Page can not be accessed by Non-secure software. - - - - - LOCK_S - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - [1:0] - read-only - - - read_write - 0 - Page is fully accessible by Secure software. - - - read_only - 1 - Page can be read by Secure software, but can not be written. - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE. - - - inaccessible - 3 - Page can not be accessed by Secure software. - - - - - - - PAGE34_LOCK0 - 0x00003f10 - Lock configuration LSBs for page 34 (rows 0x880 through 0x8bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - NO_KEY_STATE - State when at least one key is registered for this page and no matching key has been entered. - [6:6] - read-only - - - read_only - 0 - - - inaccessible - 1 - - - - - KEY_R - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. - [5:3] - read-only - - - KEY_W - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. - [2:0] - read-only - - - - - PAGE34_LOCK1 - 0x00003f14 - Lock configuration MSBs for page 34 (rows 0x880 through 0x8bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - LOCK_BL - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. - [5:4] - read-only - - - read_write - 0 - Bootloader permits user reads and writes to this page - - - read_only - 1 - Bootloader permits user reads of this page - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE - - - inaccessible - 3 - Bootloader does not permit user access to this page - - - - - LOCK_NS - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - - Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. - [3:2] - read-only - - - read_write - 0 - Page can be read by Non-secure software, and Secure software may permit Non-secure writes. - - - read_only - 1 - Page can be read by Non-secure software - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE. - - - inaccessible - 3 - Page can not be accessed by Non-secure software. - - - - - LOCK_S - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - [1:0] - read-only - - - read_write - 0 - Page is fully accessible by Secure software. - - - read_only - 1 - Page can be read by Secure software, but can not be written. - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE. - - - inaccessible - 3 - Page can not be accessed by Secure software. - - - - - - - PAGE35_LOCK0 - 0x00003f18 - Lock configuration LSBs for page 35 (rows 0x8c0 through 0x8ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - NO_KEY_STATE - State when at least one key is registered for this page and no matching key has been entered. - [6:6] - read-only - - - read_only - 0 - - - inaccessible - 1 - - - - - KEY_R - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. - [5:3] - read-only - - - KEY_W - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. - [2:0] - read-only - - - - - PAGE35_LOCK1 - 0x00003f1c - Lock configuration MSBs for page 35 (rows 0x8c0 through 0x8ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - LOCK_BL - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. - [5:4] - read-only - - - read_write - 0 - Bootloader permits user reads and writes to this page - - - read_only - 1 - Bootloader permits user reads of this page - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE - - - inaccessible - 3 - Bootloader does not permit user access to this page - - - - - LOCK_NS - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - - Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. - [3:2] - read-only - - - read_write - 0 - Page can be read by Non-secure software, and Secure software may permit Non-secure writes. - - - read_only - 1 - Page can be read by Non-secure software - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE. - - - inaccessible - 3 - Page can not be accessed by Non-secure software. - - - - - LOCK_S - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - [1:0] - read-only - - - read_write - 0 - Page is fully accessible by Secure software. - - - read_only - 1 - Page can be read by Secure software, but can not be written. - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE. - - - inaccessible - 3 - Page can not be accessed by Secure software. - - - - - - - PAGE36_LOCK0 - 0x00003f20 - Lock configuration LSBs for page 36 (rows 0x900 through 0x93f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - NO_KEY_STATE - State when at least one key is registered for this page and no matching key has been entered. - [6:6] - read-only - - - read_only - 0 - - - inaccessible - 1 - - - - - KEY_R - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. - [5:3] - read-only - - - KEY_W - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. - [2:0] - read-only - - - - - PAGE36_LOCK1 - 0x00003f24 - Lock configuration MSBs for page 36 (rows 0x900 through 0x93f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - LOCK_BL - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. - [5:4] - read-only - - - read_write - 0 - Bootloader permits user reads and writes to this page - - - read_only - 1 - Bootloader permits user reads of this page - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE - - - inaccessible - 3 - Bootloader does not permit user access to this page - - - - - LOCK_NS - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - - Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. - [3:2] - read-only - - - read_write - 0 - Page can be read by Non-secure software, and Secure software may permit Non-secure writes. - - - read_only - 1 - Page can be read by Non-secure software - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE. - - - inaccessible - 3 - Page can not be accessed by Non-secure software. - - - - - LOCK_S - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - [1:0] - read-only - - - read_write - 0 - Page is fully accessible by Secure software. - - - read_only - 1 - Page can be read by Secure software, but can not be written. - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE. - - - inaccessible - 3 - Page can not be accessed by Secure software. - - - - - - - PAGE37_LOCK0 - 0x00003f28 - Lock configuration LSBs for page 37 (rows 0x940 through 0x97f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - NO_KEY_STATE - State when at least one key is registered for this page and no matching key has been entered. - [6:6] - read-only - - - read_only - 0 - - - inaccessible - 1 - - - - - KEY_R - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. - [5:3] - read-only - - - KEY_W - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. - [2:0] - read-only - - - - - PAGE37_LOCK1 - 0x00003f2c - Lock configuration MSBs for page 37 (rows 0x940 through 0x97f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - LOCK_BL - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. - [5:4] - read-only - - - read_write - 0 - Bootloader permits user reads and writes to this page - - - read_only - 1 - Bootloader permits user reads of this page - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE - - - inaccessible - 3 - Bootloader does not permit user access to this page - - - - - LOCK_NS - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - - Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. - [3:2] - read-only - - - read_write - 0 - Page can be read by Non-secure software, and Secure software may permit Non-secure writes. - - - read_only - 1 - Page can be read by Non-secure software - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE. - - - inaccessible - 3 - Page can not be accessed by Non-secure software. - - - - - LOCK_S - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - [1:0] - read-only - - - read_write - 0 - Page is fully accessible by Secure software. - - - read_only - 1 - Page can be read by Secure software, but can not be written. - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE. - - - inaccessible - 3 - Page can not be accessed by Secure software. - - - - - - - PAGE38_LOCK0 - 0x00003f30 - Lock configuration LSBs for page 38 (rows 0x980 through 0x9bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - NO_KEY_STATE - State when at least one key is registered for this page and no matching key has been entered. - [6:6] - read-only - - - read_only - 0 - - - inaccessible - 1 - - - - - KEY_R - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. - [5:3] - read-only - - - KEY_W - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. - [2:0] - read-only - - - - - PAGE38_LOCK1 - 0x00003f34 - Lock configuration MSBs for page 38 (rows 0x980 through 0x9bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - LOCK_BL - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. - [5:4] - read-only - - - read_write - 0 - Bootloader permits user reads and writes to this page - - - read_only - 1 - Bootloader permits user reads of this page - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE - - - inaccessible - 3 - Bootloader does not permit user access to this page - - - - - LOCK_NS - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - - Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. - [3:2] - read-only - - - read_write - 0 - Page can be read by Non-secure software, and Secure software may permit Non-secure writes. - - - read_only - 1 - Page can be read by Non-secure software - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE. - - - inaccessible - 3 - Page can not be accessed by Non-secure software. - - - - - LOCK_S - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - [1:0] - read-only - - - read_write - 0 - Page is fully accessible by Secure software. - - - read_only - 1 - Page can be read by Secure software, but can not be written. - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE. - - - inaccessible - 3 - Page can not be accessed by Secure software. - - - - - - - PAGE39_LOCK0 - 0x00003f38 - Lock configuration LSBs for page 39 (rows 0x9c0 through 0x9ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - NO_KEY_STATE - State when at least one key is registered for this page and no matching key has been entered. - [6:6] - read-only - - - read_only - 0 - - - inaccessible - 1 - - - - - KEY_R - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. - [5:3] - read-only - - - KEY_W - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. - [2:0] - read-only - - - - - PAGE39_LOCK1 - 0x00003f3c - Lock configuration MSBs for page 39 (rows 0x9c0 through 0x9ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - LOCK_BL - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. - [5:4] - read-only - - - read_write - 0 - Bootloader permits user reads and writes to this page - - - read_only - 1 - Bootloader permits user reads of this page - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE - - - inaccessible - 3 - Bootloader does not permit user access to this page - - - - - LOCK_NS - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - - Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. - [3:2] - read-only - - - read_write - 0 - Page can be read by Non-secure software, and Secure software may permit Non-secure writes. - - - read_only - 1 - Page can be read by Non-secure software - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE. - - - inaccessible - 3 - Page can not be accessed by Non-secure software. - - - - - LOCK_S - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - [1:0] - read-only - - - read_write - 0 - Page is fully accessible by Secure software. - - - read_only - 1 - Page can be read by Secure software, but can not be written. - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE. - - - inaccessible - 3 - Page can not be accessed by Secure software. - - - - - - - PAGE40_LOCK0 - 0x00003f40 - Lock configuration LSBs for page 40 (rows 0xa00 through 0xa3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - NO_KEY_STATE - State when at least one key is registered for this page and no matching key has been entered. - [6:6] - read-only - - - read_only - 0 - - - inaccessible - 1 - - - - - KEY_R - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. - [5:3] - read-only - - - KEY_W - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. - [2:0] - read-only - - - - - PAGE40_LOCK1 - 0x00003f44 - Lock configuration MSBs for page 40 (rows 0xa00 through 0xa3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - LOCK_BL - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. - [5:4] - read-only - - - read_write - 0 - Bootloader permits user reads and writes to this page - - - read_only - 1 - Bootloader permits user reads of this page - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE - - - inaccessible - 3 - Bootloader does not permit user access to this page - - - - - LOCK_NS - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - - Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. - [3:2] - read-only - - - read_write - 0 - Page can be read by Non-secure software, and Secure software may permit Non-secure writes. - - - read_only - 1 - Page can be read by Non-secure software - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE. - - - inaccessible - 3 - Page can not be accessed by Non-secure software. - - - - - LOCK_S - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - [1:0] - read-only - - - read_write - 0 - Page is fully accessible by Secure software. - - - read_only - 1 - Page can be read by Secure software, but can not be written. - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE. - - - inaccessible - 3 - Page can not be accessed by Secure software. - - - - - - - PAGE41_LOCK0 - 0x00003f48 - Lock configuration LSBs for page 41 (rows 0xa40 through 0xa7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - NO_KEY_STATE - State when at least one key is registered for this page and no matching key has been entered. - [6:6] - read-only - - - read_only - 0 - - - inaccessible - 1 - - - - - KEY_R - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. - [5:3] - read-only - - - KEY_W - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. - [2:0] - read-only - - - - - PAGE41_LOCK1 - 0x00003f4c - Lock configuration MSBs for page 41 (rows 0xa40 through 0xa7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - LOCK_BL - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. - [5:4] - read-only - - - read_write - 0 - Bootloader permits user reads and writes to this page - - - read_only - 1 - Bootloader permits user reads of this page - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE - - - inaccessible - 3 - Bootloader does not permit user access to this page - - - - - LOCK_NS - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - - Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. - [3:2] - read-only - - - read_write - 0 - Page can be read by Non-secure software, and Secure software may permit Non-secure writes. - - - read_only - 1 - Page can be read by Non-secure software - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE. - - - inaccessible - 3 - Page can not be accessed by Non-secure software. - - - - - LOCK_S - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - [1:0] - read-only - - - read_write - 0 - Page is fully accessible by Secure software. - - - read_only - 1 - Page can be read by Secure software, but can not be written. - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE. - - - inaccessible - 3 - Page can not be accessed by Secure software. - - - - - - - PAGE42_LOCK0 - 0x00003f50 - Lock configuration LSBs for page 42 (rows 0xa80 through 0xabf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - NO_KEY_STATE - State when at least one key is registered for this page and no matching key has been entered. - [6:6] - read-only - - - read_only - 0 - - - inaccessible - 1 - - - - - KEY_R - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. - [5:3] - read-only - - - KEY_W - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. - [2:0] - read-only - - - - - PAGE42_LOCK1 - 0x00003f54 - Lock configuration MSBs for page 42 (rows 0xa80 through 0xabf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - LOCK_BL - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. - [5:4] - read-only - - - read_write - 0 - Bootloader permits user reads and writes to this page - - - read_only - 1 - Bootloader permits user reads of this page - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE - - - inaccessible - 3 - Bootloader does not permit user access to this page - - - - - LOCK_NS - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - - Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. - [3:2] - read-only - - - read_write - 0 - Page can be read by Non-secure software, and Secure software may permit Non-secure writes. - - - read_only - 1 - Page can be read by Non-secure software - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE. - - - inaccessible - 3 - Page can not be accessed by Non-secure software. - - - - - LOCK_S - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - [1:0] - read-only - - - read_write - 0 - Page is fully accessible by Secure software. - - - read_only - 1 - Page can be read by Secure software, but can not be written. - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE. - - - inaccessible - 3 - Page can not be accessed by Secure software. - - - - - - - PAGE43_LOCK0 - 0x00003f58 - Lock configuration LSBs for page 43 (rows 0xac0 through 0xaff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - NO_KEY_STATE - State when at least one key is registered for this page and no matching key has been entered. - [6:6] - read-only - - - read_only - 0 - - - inaccessible - 1 - - - - - KEY_R - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. - [5:3] - read-only - - - KEY_W - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. - [2:0] - read-only - - - - - PAGE43_LOCK1 - 0x00003f5c - Lock configuration MSBs for page 43 (rows 0xac0 through 0xaff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - LOCK_BL - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. - [5:4] - read-only - - - read_write - 0 - Bootloader permits user reads and writes to this page - - - read_only - 1 - Bootloader permits user reads of this page - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE - - - inaccessible - 3 - Bootloader does not permit user access to this page - - - - - LOCK_NS - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - - Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. - [3:2] - read-only - - - read_write - 0 - Page can be read by Non-secure software, and Secure software may permit Non-secure writes. - - - read_only - 1 - Page can be read by Non-secure software - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE. - - - inaccessible - 3 - Page can not be accessed by Non-secure software. - - - - - LOCK_S - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - [1:0] - read-only - - - read_write - 0 - Page is fully accessible by Secure software. - - - read_only - 1 - Page can be read by Secure software, but can not be written. - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE. - - - inaccessible - 3 - Page can not be accessed by Secure software. - - - - - - - PAGE44_LOCK0 - 0x00003f60 - Lock configuration LSBs for page 44 (rows 0xb00 through 0xb3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - NO_KEY_STATE - State when at least one key is registered for this page and no matching key has been entered. - [6:6] - read-only - - - read_only - 0 - - - inaccessible - 1 - - - - - KEY_R - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. - [5:3] - read-only - - - KEY_W - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. - [2:0] - read-only - - - - - PAGE44_LOCK1 - 0x00003f64 - Lock configuration MSBs for page 44 (rows 0xb00 through 0xb3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - LOCK_BL - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. - [5:4] - read-only - - - read_write - 0 - Bootloader permits user reads and writes to this page - - - read_only - 1 - Bootloader permits user reads of this page - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE - - - inaccessible - 3 - Bootloader does not permit user access to this page - - - - - LOCK_NS - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - - Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. - [3:2] - read-only - - - read_write - 0 - Page can be read by Non-secure software, and Secure software may permit Non-secure writes. - - - read_only - 1 - Page can be read by Non-secure software - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE. - - - inaccessible - 3 - Page can not be accessed by Non-secure software. - - - - - LOCK_S - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - [1:0] - read-only - - - read_write - 0 - Page is fully accessible by Secure software. - - - read_only - 1 - Page can be read by Secure software, but can not be written. - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE. - - - inaccessible - 3 - Page can not be accessed by Secure software. - - - - - - - PAGE45_LOCK0 - 0x00003f68 - Lock configuration LSBs for page 45 (rows 0xb40 through 0xb7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - NO_KEY_STATE - State when at least one key is registered for this page and no matching key has been entered. - [6:6] - read-only - - - read_only - 0 - - - inaccessible - 1 - - - - - KEY_R - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. - [5:3] - read-only - - - KEY_W - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. - [2:0] - read-only - - - - - PAGE45_LOCK1 - 0x00003f6c - Lock configuration MSBs for page 45 (rows 0xb40 through 0xb7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - LOCK_BL - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. - [5:4] - read-only - - - read_write - 0 - Bootloader permits user reads and writes to this page - - - read_only - 1 - Bootloader permits user reads of this page - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE - - - inaccessible - 3 - Bootloader does not permit user access to this page - - - - - LOCK_NS - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - - Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. - [3:2] - read-only - - - read_write - 0 - Page can be read by Non-secure software, and Secure software may permit Non-secure writes. - - - read_only - 1 - Page can be read by Non-secure software - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE. - - - inaccessible - 3 - Page can not be accessed by Non-secure software. - - - - - LOCK_S - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - [1:0] - read-only - - - read_write - 0 - Page is fully accessible by Secure software. - - - read_only - 1 - Page can be read by Secure software, but can not be written. - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE. - - - inaccessible - 3 - Page can not be accessed by Secure software. - - - - - - - PAGE46_LOCK0 - 0x00003f70 - Lock configuration LSBs for page 46 (rows 0xb80 through 0xbbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - NO_KEY_STATE - State when at least one key is registered for this page and no matching key has been entered. - [6:6] - read-only - - - read_only - 0 - - - inaccessible - 1 - - - - - KEY_R - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. - [5:3] - read-only - - - KEY_W - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. - [2:0] - read-only - - - - - PAGE46_LOCK1 - 0x00003f74 - Lock configuration MSBs for page 46 (rows 0xb80 through 0xbbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - LOCK_BL - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. - [5:4] - read-only - - - read_write - 0 - Bootloader permits user reads and writes to this page - - - read_only - 1 - Bootloader permits user reads of this page - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE - - - inaccessible - 3 - Bootloader does not permit user access to this page - - - - - LOCK_NS - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - - Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. - [3:2] - read-only - - - read_write - 0 - Page can be read by Non-secure software, and Secure software may permit Non-secure writes. - - - read_only - 1 - Page can be read by Non-secure software - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE. - - - inaccessible - 3 - Page can not be accessed by Non-secure software. - - - - - LOCK_S - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - [1:0] - read-only - - - read_write - 0 - Page is fully accessible by Secure software. - - - read_only - 1 - Page can be read by Secure software, but can not be written. - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE. - - - inaccessible - 3 - Page can not be accessed by Secure software. - - - - - - - PAGE47_LOCK0 - 0x00003f78 - Lock configuration LSBs for page 47 (rows 0xbc0 through 0xbff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - NO_KEY_STATE - State when at least one key is registered for this page and no matching key has been entered. - [6:6] - read-only - - - read_only - 0 - - - inaccessible - 1 - - - - - KEY_R - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. - [5:3] - read-only - - - KEY_W - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. - [2:0] - read-only - - - - - PAGE47_LOCK1 - 0x00003f7c - Lock configuration MSBs for page 47 (rows 0xbc0 through 0xbff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - LOCK_BL - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. - [5:4] - read-only - - - read_write - 0 - Bootloader permits user reads and writes to this page - - - read_only - 1 - Bootloader permits user reads of this page - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE - - - inaccessible - 3 - Bootloader does not permit user access to this page - - - - - LOCK_NS - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - - Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. - [3:2] - read-only - - - read_write - 0 - Page can be read by Non-secure software, and Secure software may permit Non-secure writes. - - - read_only - 1 - Page can be read by Non-secure software - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE. - - - inaccessible - 3 - Page can not be accessed by Non-secure software. - - - - - LOCK_S - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - [1:0] - read-only - - - read_write - 0 - Page is fully accessible by Secure software. - - - read_only - 1 - Page can be read by Secure software, but can not be written. - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE. - - - inaccessible - 3 - Page can not be accessed by Secure software. - - - - - - - PAGE48_LOCK0 - 0x00003f80 - Lock configuration LSBs for page 48 (rows 0xc00 through 0xc3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - NO_KEY_STATE - State when at least one key is registered for this page and no matching key has been entered. - [6:6] - read-only - - - read_only - 0 - - - inaccessible - 1 - - - - - KEY_R - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. - [5:3] - read-only - - - KEY_W - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. - [2:0] - read-only - - - - - PAGE48_LOCK1 - 0x00003f84 - Lock configuration MSBs for page 48 (rows 0xc00 through 0xc3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - LOCK_BL - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. - [5:4] - read-only - - - read_write - 0 - Bootloader permits user reads and writes to this page - - - read_only - 1 - Bootloader permits user reads of this page - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE - - - inaccessible - 3 - Bootloader does not permit user access to this page - - - - - LOCK_NS - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - - Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. - [3:2] - read-only - - - read_write - 0 - Page can be read by Non-secure software, and Secure software may permit Non-secure writes. - - - read_only - 1 - Page can be read by Non-secure software - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE. - - - inaccessible - 3 - Page can not be accessed by Non-secure software. - - - - - LOCK_S - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - [1:0] - read-only - - - read_write - 0 - Page is fully accessible by Secure software. - - - read_only - 1 - Page can be read by Secure software, but can not be written. - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE. - - - inaccessible - 3 - Page can not be accessed by Secure software. - - - - - - - PAGE49_LOCK0 - 0x00003f88 - Lock configuration LSBs for page 49 (rows 0xc40 through 0xc7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - NO_KEY_STATE - State when at least one key is registered for this page and no matching key has been entered. - [6:6] - read-only - - - read_only - 0 - - - inaccessible - 1 - - - - - KEY_R - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. - [5:3] - read-only - - - KEY_W - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. - [2:0] - read-only - - - - - PAGE49_LOCK1 - 0x00003f8c - Lock configuration MSBs for page 49 (rows 0xc40 through 0xc7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - LOCK_BL - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. - [5:4] - read-only - - - read_write - 0 - Bootloader permits user reads and writes to this page - - - read_only - 1 - Bootloader permits user reads of this page - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE - - - inaccessible - 3 - Bootloader does not permit user access to this page - - - - - LOCK_NS - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - - Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. - [3:2] - read-only - - - read_write - 0 - Page can be read by Non-secure software, and Secure software may permit Non-secure writes. - - - read_only - 1 - Page can be read by Non-secure software - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE. - - - inaccessible - 3 - Page can not be accessed by Non-secure software. - - - - - LOCK_S - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - [1:0] - read-only - - - read_write - 0 - Page is fully accessible by Secure software. - - - read_only - 1 - Page can be read by Secure software, but can not be written. - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE. - - - inaccessible - 3 - Page can not be accessed by Secure software. - - - - - - - PAGE50_LOCK0 - 0x00003f90 - Lock configuration LSBs for page 50 (rows 0xc80 through 0xcbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - NO_KEY_STATE - State when at least one key is registered for this page and no matching key has been entered. - [6:6] - read-only - - - read_only - 0 - - - inaccessible - 1 - - - - - KEY_R - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. - [5:3] - read-only - - - KEY_W - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. - [2:0] - read-only - - - - - PAGE50_LOCK1 - 0x00003f94 - Lock configuration MSBs for page 50 (rows 0xc80 through 0xcbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - LOCK_BL - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. - [5:4] - read-only - - - read_write - 0 - Bootloader permits user reads and writes to this page - - - read_only - 1 - Bootloader permits user reads of this page - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE - - - inaccessible - 3 - Bootloader does not permit user access to this page - - - - - LOCK_NS - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - - Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. - [3:2] - read-only - - - read_write - 0 - Page can be read by Non-secure software, and Secure software may permit Non-secure writes. - - - read_only - 1 - Page can be read by Non-secure software - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE. - - - inaccessible - 3 - Page can not be accessed by Non-secure software. - - - - - LOCK_S - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - [1:0] - read-only - - - read_write - 0 - Page is fully accessible by Secure software. - - - read_only - 1 - Page can be read by Secure software, but can not be written. - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE. - - - inaccessible - 3 - Page can not be accessed by Secure software. - - - - - - - PAGE51_LOCK0 - 0x00003f98 - Lock configuration LSBs for page 51 (rows 0xcc0 through 0xcff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - NO_KEY_STATE - State when at least one key is registered for this page and no matching key has been entered. - [6:6] - read-only - - - read_only - 0 - - - inaccessible - 1 - - - - - KEY_R - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. - [5:3] - read-only - - - KEY_W - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. - [2:0] - read-only - - - - - PAGE51_LOCK1 - 0x00003f9c - Lock configuration MSBs for page 51 (rows 0xcc0 through 0xcff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - LOCK_BL - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. - [5:4] - read-only - - - read_write - 0 - Bootloader permits user reads and writes to this page - - - read_only - 1 - Bootloader permits user reads of this page - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE - - - inaccessible - 3 - Bootloader does not permit user access to this page - - - - - LOCK_NS - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - - Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. - [3:2] - read-only - - - read_write - 0 - Page can be read by Non-secure software, and Secure software may permit Non-secure writes. - - - read_only - 1 - Page can be read by Non-secure software - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE. - - - inaccessible - 3 - Page can not be accessed by Non-secure software. - - - - - LOCK_S - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - [1:0] - read-only - - - read_write - 0 - Page is fully accessible by Secure software. - - - read_only - 1 - Page can be read by Secure software, but can not be written. - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE. - - - inaccessible - 3 - Page can not be accessed by Secure software. - - - - - - - PAGE52_LOCK0 - 0x00003fa0 - Lock configuration LSBs for page 52 (rows 0xd00 through 0xd3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - NO_KEY_STATE - State when at least one key is registered for this page and no matching key has been entered. - [6:6] - read-only - - - read_only - 0 - - - inaccessible - 1 - - - - - KEY_R - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. - [5:3] - read-only - - - KEY_W - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. - [2:0] - read-only - - - - - PAGE52_LOCK1 - 0x00003fa4 - Lock configuration MSBs for page 52 (rows 0xd00 through 0xd3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - LOCK_BL - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. - [5:4] - read-only - - - read_write - 0 - Bootloader permits user reads and writes to this page - - - read_only - 1 - Bootloader permits user reads of this page - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE - - - inaccessible - 3 - Bootloader does not permit user access to this page - - - - - LOCK_NS - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - - Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. - [3:2] - read-only - - - read_write - 0 - Page can be read by Non-secure software, and Secure software may permit Non-secure writes. - - - read_only - 1 - Page can be read by Non-secure software - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE. - - - inaccessible - 3 - Page can not be accessed by Non-secure software. - - - - - LOCK_S - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - [1:0] - read-only - - - read_write - 0 - Page is fully accessible by Secure software. - - - read_only - 1 - Page can be read by Secure software, but can not be written. - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE. - - - inaccessible - 3 - Page can not be accessed by Secure software. - - - - - - - PAGE53_LOCK0 - 0x00003fa8 - Lock configuration LSBs for page 53 (rows 0xd40 through 0xd7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - NO_KEY_STATE - State when at least one key is registered for this page and no matching key has been entered. - [6:6] - read-only - - - read_only - 0 - - - inaccessible - 1 - - - - - KEY_R - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. - [5:3] - read-only - - - KEY_W - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. - [2:0] - read-only - - - - - PAGE53_LOCK1 - 0x00003fac - Lock configuration MSBs for page 53 (rows 0xd40 through 0xd7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - LOCK_BL - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. - [5:4] - read-only - - - read_write - 0 - Bootloader permits user reads and writes to this page - - - read_only - 1 - Bootloader permits user reads of this page - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE - - - inaccessible - 3 - Bootloader does not permit user access to this page - - - - - LOCK_NS - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - - Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. - [3:2] - read-only - - - read_write - 0 - Page can be read by Non-secure software, and Secure software may permit Non-secure writes. - - - read_only - 1 - Page can be read by Non-secure software - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE. - - - inaccessible - 3 - Page can not be accessed by Non-secure software. - - - - - LOCK_S - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - [1:0] - read-only - - - read_write - 0 - Page is fully accessible by Secure software. - - - read_only - 1 - Page can be read by Secure software, but can not be written. - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE. - - - inaccessible - 3 - Page can not be accessed by Secure software. - - - - - - - PAGE54_LOCK0 - 0x00003fb0 - Lock configuration LSBs for page 54 (rows 0xd80 through 0xdbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - NO_KEY_STATE - State when at least one key is registered for this page and no matching key has been entered. - [6:6] - read-only - - - read_only - 0 - - - inaccessible - 1 - - - - - KEY_R - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. - [5:3] - read-only - - - KEY_W - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. - [2:0] - read-only - - - - - PAGE54_LOCK1 - 0x00003fb4 - Lock configuration MSBs for page 54 (rows 0xd80 through 0xdbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - LOCK_BL - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. - [5:4] - read-only - - - read_write - 0 - Bootloader permits user reads and writes to this page - - - read_only - 1 - Bootloader permits user reads of this page - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE - - - inaccessible - 3 - Bootloader does not permit user access to this page - - - - - LOCK_NS - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - - Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. - [3:2] - read-only - - - read_write - 0 - Page can be read by Non-secure software, and Secure software may permit Non-secure writes. - - - read_only - 1 - Page can be read by Non-secure software - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE. - - - inaccessible - 3 - Page can not be accessed by Non-secure software. - - - - - LOCK_S - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - [1:0] - read-only - - - read_write - 0 - Page is fully accessible by Secure software. - - - read_only - 1 - Page can be read by Secure software, but can not be written. - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE. - - - inaccessible - 3 - Page can not be accessed by Secure software. - - - - - - - PAGE55_LOCK0 - 0x00003fb8 - Lock configuration LSBs for page 55 (rows 0xdc0 through 0xdff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - NO_KEY_STATE - State when at least one key is registered for this page and no matching key has been entered. - [6:6] - read-only - - - read_only - 0 - - - inaccessible - 1 - - - - - KEY_R - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. - [5:3] - read-only - - - KEY_W - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. - [2:0] - read-only - - - - - PAGE55_LOCK1 - 0x00003fbc - Lock configuration MSBs for page 55 (rows 0xdc0 through 0xdff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - LOCK_BL - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. - [5:4] - read-only - - - read_write - 0 - Bootloader permits user reads and writes to this page - - - read_only - 1 - Bootloader permits user reads of this page - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE - - - inaccessible - 3 - Bootloader does not permit user access to this page - - - - - LOCK_NS - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - - Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. - [3:2] - read-only - - - read_write - 0 - Page can be read by Non-secure software, and Secure software may permit Non-secure writes. - - - read_only - 1 - Page can be read by Non-secure software - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE. - - - inaccessible - 3 - Page can not be accessed by Non-secure software. - - - - - LOCK_S - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - [1:0] - read-only - - - read_write - 0 - Page is fully accessible by Secure software. - - - read_only - 1 - Page can be read by Secure software, but can not be written. - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE. - - - inaccessible - 3 - Page can not be accessed by Secure software. - - - - - - - PAGE56_LOCK0 - 0x00003fc0 - Lock configuration LSBs for page 56 (rows 0xe00 through 0xe3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - NO_KEY_STATE - State when at least one key is registered for this page and no matching key has been entered. - [6:6] - read-only - - - read_only - 0 - - - inaccessible - 1 - - - - - KEY_R - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. - [5:3] - read-only - - - KEY_W - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. - [2:0] - read-only - - - - - PAGE56_LOCK1 - 0x00003fc4 - Lock configuration MSBs for page 56 (rows 0xe00 through 0xe3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - LOCK_BL - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. - [5:4] - read-only - - - read_write - 0 - Bootloader permits user reads and writes to this page - - - read_only - 1 - Bootloader permits user reads of this page - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE - - - inaccessible - 3 - Bootloader does not permit user access to this page - - - - - LOCK_NS - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - - Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. - [3:2] - read-only - - - read_write - 0 - Page can be read by Non-secure software, and Secure software may permit Non-secure writes. - - - read_only - 1 - Page can be read by Non-secure software - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE. - - - inaccessible - 3 - Page can not be accessed by Non-secure software. - - - - - LOCK_S - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - [1:0] - read-only - - - read_write - 0 - Page is fully accessible by Secure software. - - - read_only - 1 - Page can be read by Secure software, but can not be written. - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE. - - - inaccessible - 3 - Page can not be accessed by Secure software. - - - - - - - PAGE57_LOCK0 - 0x00003fc8 - Lock configuration LSBs for page 57 (rows 0xe40 through 0xe7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - NO_KEY_STATE - State when at least one key is registered for this page and no matching key has been entered. - [6:6] - read-only - - - read_only - 0 - - - inaccessible - 1 - - - - - KEY_R - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. - [5:3] - read-only - - - KEY_W - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. - [2:0] - read-only - - - - - PAGE57_LOCK1 - 0x00003fcc - Lock configuration MSBs for page 57 (rows 0xe40 through 0xe7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - LOCK_BL - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. - [5:4] - read-only - - - read_write - 0 - Bootloader permits user reads and writes to this page - - - read_only - 1 - Bootloader permits user reads of this page - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE - - - inaccessible - 3 - Bootloader does not permit user access to this page - - - - - LOCK_NS - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - - Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. - [3:2] - read-only - - - read_write - 0 - Page can be read by Non-secure software, and Secure software may permit Non-secure writes. - - - read_only - 1 - Page can be read by Non-secure software - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE. - - - inaccessible - 3 - Page can not be accessed by Non-secure software. - - - - - LOCK_S - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - [1:0] - read-only - - - read_write - 0 - Page is fully accessible by Secure software. - - - read_only - 1 - Page can be read by Secure software, but can not be written. - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE. - - - inaccessible - 3 - Page can not be accessed by Secure software. - - - - - - - PAGE58_LOCK0 - 0x00003fd0 - Lock configuration LSBs for page 58 (rows 0xe80 through 0xebf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - NO_KEY_STATE - State when at least one key is registered for this page and no matching key has been entered. - [6:6] - read-only - - - read_only - 0 - - - inaccessible - 1 - - - - - KEY_R - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. - [5:3] - read-only - - - KEY_W - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. - [2:0] - read-only - - - - - PAGE58_LOCK1 - 0x00003fd4 - Lock configuration MSBs for page 58 (rows 0xe80 through 0xebf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - LOCK_BL - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. - [5:4] - read-only - - - read_write - 0 - Bootloader permits user reads and writes to this page - - - read_only - 1 - Bootloader permits user reads of this page - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE - - - inaccessible - 3 - Bootloader does not permit user access to this page - - - - - LOCK_NS - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - - Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. - [3:2] - read-only - - - read_write - 0 - Page can be read by Non-secure software, and Secure software may permit Non-secure writes. - - - read_only - 1 - Page can be read by Non-secure software - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE. - - - inaccessible - 3 - Page can not be accessed by Non-secure software. - - - - - LOCK_S - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - [1:0] - read-only - - - read_write - 0 - Page is fully accessible by Secure software. - - - read_only - 1 - Page can be read by Secure software, but can not be written. - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE. - - - inaccessible - 3 - Page can not be accessed by Secure software. - - - - - - - PAGE59_LOCK0 - 0x00003fd8 - Lock configuration LSBs for page 59 (rows 0xec0 through 0xeff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - NO_KEY_STATE - State when at least one key is registered for this page and no matching key has been entered. - [6:6] - read-only - - - read_only - 0 - - - inaccessible - 1 - - - - - KEY_R - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. - [5:3] - read-only - - - KEY_W - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. - [2:0] - read-only - - - - - PAGE59_LOCK1 - 0x00003fdc - Lock configuration MSBs for page 59 (rows 0xec0 through 0xeff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - LOCK_BL - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. - [5:4] - read-only - - - read_write - 0 - Bootloader permits user reads and writes to this page - - - read_only - 1 - Bootloader permits user reads of this page - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE - - - inaccessible - 3 - Bootloader does not permit user access to this page - - - - - LOCK_NS - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - - Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. - [3:2] - read-only - - - read_write - 0 - Page can be read by Non-secure software, and Secure software may permit Non-secure writes. - - - read_only - 1 - Page can be read by Non-secure software - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE. - - - inaccessible - 3 - Page can not be accessed by Non-secure software. - - - - - LOCK_S - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - [1:0] - read-only - - - read_write - 0 - Page is fully accessible by Secure software. - - - read_only - 1 - Page can be read by Secure software, but can not be written. - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE. - - - inaccessible - 3 - Page can not be accessed by Secure software. - - - - - - - PAGE60_LOCK0 - 0x00003fe0 - Lock configuration LSBs for page 60 (rows 0xf00 through 0xf3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - NO_KEY_STATE - State when at least one key is registered for this page and no matching key has been entered. - [6:6] - read-only - - - read_only - 0 - - - inaccessible - 1 - - - - - KEY_R - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. - [5:3] - read-only - - - KEY_W - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. - [2:0] - read-only - - - - - PAGE60_LOCK1 - 0x00003fe4 - Lock configuration MSBs for page 60 (rows 0xf00 through 0xf3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - LOCK_BL - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. - [5:4] - read-only - - - read_write - 0 - Bootloader permits user reads and writes to this page - - - read_only - 1 - Bootloader permits user reads of this page - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE - - - inaccessible - 3 - Bootloader does not permit user access to this page - - - - - LOCK_NS - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - - Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. - [3:2] - read-only - - - read_write - 0 - Page can be read by Non-secure software, and Secure software may permit Non-secure writes. - - - read_only - 1 - Page can be read by Non-secure software - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE. - - - inaccessible - 3 - Page can not be accessed by Non-secure software. - - - - - LOCK_S - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - [1:0] - read-only - - - read_write - 0 - Page is fully accessible by Secure software. - - - read_only - 1 - Page can be read by Secure software, but can not be written. - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE. - - - inaccessible - 3 - Page can not be accessed by Secure software. - - - - - - - PAGE61_LOCK0 - 0x00003fe8 - Lock configuration LSBs for page 61 (rows 0xf40 through 0xf7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - NO_KEY_STATE - State when at least one key is registered for this page and no matching key has been entered. - [6:6] - read-only - - - read_only - 0 - - - inaccessible - 1 - - - - - KEY_R - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. - [5:3] - read-only - - - KEY_W - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. - [2:0] - read-only - - - - - PAGE61_LOCK1 - 0x00003fec - Lock configuration MSBs for page 61 (rows 0xf40 through 0xf7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - LOCK_BL - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. - [5:4] - read-only - - - read_write - 0 - Bootloader permits user reads and writes to this page - - - read_only - 1 - Bootloader permits user reads of this page - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE - - - inaccessible - 3 - Bootloader does not permit user access to this page - - - - - LOCK_NS - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - - Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. - [3:2] - read-only - - - read_write - 0 - Page can be read by Non-secure software, and Secure software may permit Non-secure writes. - - - read_only - 1 - Page can be read by Non-secure software - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE. - - - inaccessible - 3 - Page can not be accessed by Non-secure software. - - - - - LOCK_S - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - [1:0] - read-only - - - read_write - 0 - Page is fully accessible by Secure software. - - - read_only - 1 - Page can be read by Secure software, but can not be written. - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE. - - - inaccessible - 3 - Page can not be accessed by Secure software. - - - - - - - PAGE62_LOCK0 - 0x00003ff0 - Lock configuration LSBs for page 62 (rows 0xf80 through 0xfbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - NO_KEY_STATE - State when at least one key is registered for this page and no matching key has been entered. - [6:6] - read-only - - - read_only - 0 - - - inaccessible - 1 - - - - - KEY_R - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. - [5:3] - read-only - - - KEY_W - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. - [2:0] - read-only - - - - - PAGE62_LOCK1 - 0x00003ff4 - Lock configuration MSBs for page 62 (rows 0xf80 through 0xfbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - LOCK_BL - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. - [5:4] - read-only - - - read_write - 0 - Bootloader permits user reads and writes to this page - - - read_only - 1 - Bootloader permits user reads of this page - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE - - - inaccessible - 3 - Bootloader does not permit user access to this page - - - - - LOCK_NS - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - - Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. - [3:2] - read-only - - - read_write - 0 - Page can be read by Non-secure software, and Secure software may permit Non-secure writes. - - - read_only - 1 - Page can be read by Non-secure software - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE. - - - inaccessible - 3 - Page can not be accessed by Non-secure software. - - - - - LOCK_S - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - [1:0] - read-only - - - read_write - 0 - Page is fully accessible by Secure software. - - - read_only - 1 - Page can be read by Secure software, but can not be written. - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE. - - - inaccessible - 3 - Page can not be accessed by Secure software. - - - - - - - PAGE63_LOCK0 - 0x00003ff8 - Lock configuration LSBs for page 63 (rows 0xfc0 through 0xfff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - RMA - Decommission for RMA of a suspected faulty device. This re-enables the factory test JTAG interface, and makes pages 3 through 61 of the OTP permanently inaccessible. - [7:7] - read-only - - - NO_KEY_STATE - State when at least one key is registered for this page and no matching key has been entered. - [6:6] - read-only - - - read_only - 0 - - - inaccessible - 1 - - - - - KEY_R - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. - [5:3] - read-only - - - KEY_W - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. - [2:0] - read-only - - - - - PAGE63_LOCK1 - 0x00003ffc - Lock configuration MSBs for page 63 (rows 0xfc0 through 0xfff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. - - This OTP location is always readable, and is write-protected by its own permissions. - 0x00000000 - - - R2 - Redundant copy of bits 7:0 - [23:16] - read-only - - - R1 - Redundant copy of bits 7:0 - [15:8] - read-only - - - LOCK_BL - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. - [5:4] - read-only - - - read_write - 0 - Bootloader permits user reads and writes to this page - - - read_only - 1 - Bootloader permits user reads of this page - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE - - - inaccessible - 3 - Bootloader does not permit user access to this page - - - - - LOCK_NS - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - - Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. - [3:2] - read-only - - - read_write - 0 - Page can be read by Non-secure software, and Secure software may permit Non-secure writes. - - - read_only - 1 - Page can be read by Non-secure software - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE. - - - inaccessible - 3 - Page can not be accessed by Non-secure software. - - - - - LOCK_S - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. - [1:0] - read-only - - - read_write - 0 - Page is fully accessible by Secure software. - - - read_only - 1 - Page can be read by Secure software, but can not be written. - - - reserved - 2 - Do not use. Behaves the same as INACCESSIBLE. - - - inaccessible - 3 - Page can not be accessed by Secure software. - - - - - - - - - TBMAN - For managing simulation testbenches - 0x40160000 - - 0 - 4 - registers - - - - PLATFORM - 0x00000000 - Indicates the type of platform in use - 0x00000001 - - - HDLSIM - Indicates the platform is a simulation - [2:2] - read-only - - - FPGA - Indicates the platform is an FPGA - [1:1] - read-only - - - ASIC - Indicates the platform is an ASIC - [0:0] - read-only - - - - - - - USB_DPRAM - DPRAM layout for USB device. - 0x50100000 - - 0 - 256 - registers - - - - SETUP_PACKET_LOW - 0x00000000 - Bytes 0-3 of the SETUP packet from the host. - 0x00000000 - - - WVALUE - [31:16] - read-write - - - BREQUEST - [15:8] - read-write - - - BMREQUESTTYPE - [7:0] - read-write - - - - - SETUP_PACKET_HIGH - 0x00000004 - Bytes 4-7 of the setup packet from the host. - 0x00000000 - - - WLENGTH - [31:16] - read-write - - - WINDEX - [15:0] - read-write - - - - - EP1_IN_CONTROL - 0x00000008 - 0x00000000 - - - ENABLE - Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. - [31:31] - read-write - - - DOUBLE_BUFFERED - This endpoint is double buffered. - [30:30] - read-write - - - INTERRUPT_PER_BUFF - Trigger an interrupt each time a buffer is done. - [29:29] - read-write - - - INTERRUPT_PER_DOUBLE_BUFF - Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. - [28:28] - read-write - - - ENDPOINT_TYPE - [27:26] - read-write - - - Control - 0 - - - Isochronous - 1 - - - Bulk - 2 - - - Interrupt - 3 - - - - - INTERRUPT_ON_STALL - Trigger an interrupt if a STALL is sent. Intended for debug only. - [17:17] - read-write - - - INTERRUPT_ON_NAK - Trigger an interrupt if a NAK is sent. Intended for debug only. - [16:16] - read-write - - - BUFFER_ADDRESS - 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. - [15:0] - read-write - - - - - EP1_OUT_CONTROL - 0x0000000c - 0x00000000 - - - ENABLE - Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. - [31:31] - read-write - - - DOUBLE_BUFFERED - This endpoint is double buffered. - [30:30] - read-write - - - INTERRUPT_PER_BUFF - Trigger an interrupt each time a buffer is done. - [29:29] - read-write - - - INTERRUPT_PER_DOUBLE_BUFF - Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. - [28:28] - read-write - - - ENDPOINT_TYPE - [27:26] - read-write - - - Control - 0 - - - Isochronous - 1 - - - Bulk - 2 - - - Interrupt - 3 - - - - - INTERRUPT_ON_STALL - Trigger an interrupt if a STALL is sent. Intended for debug only. - [17:17] - read-write - - - INTERRUPT_ON_NAK - Trigger an interrupt if a NAK is sent. Intended for debug only. - [16:16] - read-write - - - BUFFER_ADDRESS - 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. - [15:0] - read-write - - - - - EP2_IN_CONTROL - 0x00000010 - 0x00000000 - - - ENABLE - Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. - [31:31] - read-write - - - DOUBLE_BUFFERED - This endpoint is double buffered. - [30:30] - read-write - - - INTERRUPT_PER_BUFF - Trigger an interrupt each time a buffer is done. - [29:29] - read-write - - - INTERRUPT_PER_DOUBLE_BUFF - Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. - [28:28] - read-write - - - ENDPOINT_TYPE - [27:26] - read-write - - - Control - 0 - - - Isochronous - 1 - - - Bulk - 2 - - - Interrupt - 3 - - - - - INTERRUPT_ON_STALL - Trigger an interrupt if a STALL is sent. Intended for debug only. - [17:17] - read-write - - - INTERRUPT_ON_NAK - Trigger an interrupt if a NAK is sent. Intended for debug only. - [16:16] - read-write - - - BUFFER_ADDRESS - 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. - [15:0] - read-write - - - - - EP2_OUT_CONTROL - 0x00000014 - 0x00000000 - - - ENABLE - Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. - [31:31] - read-write - - - DOUBLE_BUFFERED - This endpoint is double buffered. - [30:30] - read-write - - - INTERRUPT_PER_BUFF - Trigger an interrupt each time a buffer is done. - [29:29] - read-write - - - INTERRUPT_PER_DOUBLE_BUFF - Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. - [28:28] - read-write - - - ENDPOINT_TYPE - [27:26] - read-write - - - Control - 0 - - - Isochronous - 1 - - - Bulk - 2 - - - Interrupt - 3 - - - - - INTERRUPT_ON_STALL - Trigger an interrupt if a STALL is sent. Intended for debug only. - [17:17] - read-write - - - INTERRUPT_ON_NAK - Trigger an interrupt if a NAK is sent. Intended for debug only. - [16:16] - read-write - - - BUFFER_ADDRESS - 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. - [15:0] - read-write - - - - - EP3_IN_CONTROL - 0x00000018 - 0x00000000 - - - ENABLE - Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. - [31:31] - read-write - - - DOUBLE_BUFFERED - This endpoint is double buffered. - [30:30] - read-write - - - INTERRUPT_PER_BUFF - Trigger an interrupt each time a buffer is done. - [29:29] - read-write - - - INTERRUPT_PER_DOUBLE_BUFF - Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. - [28:28] - read-write - - - ENDPOINT_TYPE - [27:26] - read-write - - - Control - 0 - - - Isochronous - 1 - - - Bulk - 2 - - - Interrupt - 3 - - - - - INTERRUPT_ON_STALL - Trigger an interrupt if a STALL is sent. Intended for debug only. - [17:17] - read-write - - - INTERRUPT_ON_NAK - Trigger an interrupt if a NAK is sent. Intended for debug only. - [16:16] - read-write - - - BUFFER_ADDRESS - 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. - [15:0] - read-write - - - - - EP3_OUT_CONTROL - 0x0000001c - 0x00000000 - - - ENABLE - Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. - [31:31] - read-write - - - DOUBLE_BUFFERED - This endpoint is double buffered. - [30:30] - read-write - - - INTERRUPT_PER_BUFF - Trigger an interrupt each time a buffer is done. - [29:29] - read-write - - - INTERRUPT_PER_DOUBLE_BUFF - Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. - [28:28] - read-write - - - ENDPOINT_TYPE - [27:26] - read-write - - - Control - 0 - - - Isochronous - 1 - - - Bulk - 2 - - - Interrupt - 3 - - - - - INTERRUPT_ON_STALL - Trigger an interrupt if a STALL is sent. Intended for debug only. - [17:17] - read-write - - - INTERRUPT_ON_NAK - Trigger an interrupt if a NAK is sent. Intended for debug only. - [16:16] - read-write - - - BUFFER_ADDRESS - 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. - [15:0] - read-write - - - - - EP4_IN_CONTROL - 0x00000020 - 0x00000000 - - - ENABLE - Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. - [31:31] - read-write - - - DOUBLE_BUFFERED - This endpoint is double buffered. - [30:30] - read-write - - - INTERRUPT_PER_BUFF - Trigger an interrupt each time a buffer is done. - [29:29] - read-write - - - INTERRUPT_PER_DOUBLE_BUFF - Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. - [28:28] - read-write - - - ENDPOINT_TYPE - [27:26] - read-write - - - Control - 0 - - - Isochronous - 1 - - - Bulk - 2 - - - Interrupt - 3 - - - - - INTERRUPT_ON_STALL - Trigger an interrupt if a STALL is sent. Intended for debug only. - [17:17] - read-write - - - INTERRUPT_ON_NAK - Trigger an interrupt if a NAK is sent. Intended for debug only. - [16:16] - read-write - - - BUFFER_ADDRESS - 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. - [15:0] - read-write - - - - - EP4_OUT_CONTROL - 0x00000024 - 0x00000000 - - - ENABLE - Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. - [31:31] - read-write - - - DOUBLE_BUFFERED - This endpoint is double buffered. - [30:30] - read-write - - - INTERRUPT_PER_BUFF - Trigger an interrupt each time a buffer is done. - [29:29] - read-write - - - INTERRUPT_PER_DOUBLE_BUFF - Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. - [28:28] - read-write - - - ENDPOINT_TYPE - [27:26] - read-write - - - Control - 0 - - - Isochronous - 1 - - - Bulk - 2 - - - Interrupt - 3 - - - - - INTERRUPT_ON_STALL - Trigger an interrupt if a STALL is sent. Intended for debug only. - [17:17] - read-write - - - INTERRUPT_ON_NAK - Trigger an interrupt if a NAK is sent. Intended for debug only. - [16:16] - read-write - - - BUFFER_ADDRESS - 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. - [15:0] - read-write - - - - - EP5_IN_CONTROL - 0x00000028 - 0x00000000 - - - ENABLE - Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. - [31:31] - read-write - - - DOUBLE_BUFFERED - This endpoint is double buffered. - [30:30] - read-write - - - INTERRUPT_PER_BUFF - Trigger an interrupt each time a buffer is done. - [29:29] - read-write - - - INTERRUPT_PER_DOUBLE_BUFF - Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. - [28:28] - read-write - - - ENDPOINT_TYPE - [27:26] - read-write - - - Control - 0 - - - Isochronous - 1 - - - Bulk - 2 - - - Interrupt - 3 - - - - - INTERRUPT_ON_STALL - Trigger an interrupt if a STALL is sent. Intended for debug only. - [17:17] - read-write - - - INTERRUPT_ON_NAK - Trigger an interrupt if a NAK is sent. Intended for debug only. - [16:16] - read-write - - - BUFFER_ADDRESS - 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. - [15:0] - read-write - - - - - EP5_OUT_CONTROL - 0x0000002c - 0x00000000 - - - ENABLE - Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. - [31:31] - read-write - - - DOUBLE_BUFFERED - This endpoint is double buffered. - [30:30] - read-write - - - INTERRUPT_PER_BUFF - Trigger an interrupt each time a buffer is done. - [29:29] - read-write - - - INTERRUPT_PER_DOUBLE_BUFF - Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. - [28:28] - read-write - - - ENDPOINT_TYPE - [27:26] - read-write - - - Control - 0 - - - Isochronous - 1 - - - Bulk - 2 - - - Interrupt - 3 - - - - - INTERRUPT_ON_STALL - Trigger an interrupt if a STALL is sent. Intended for debug only. - [17:17] - read-write - - - INTERRUPT_ON_NAK - Trigger an interrupt if a NAK is sent. Intended for debug only. - [16:16] - read-write - - - BUFFER_ADDRESS - 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. - [15:0] - read-write - - - - - EP6_IN_CONTROL - 0x00000030 - 0x00000000 - - - ENABLE - Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. - [31:31] - read-write - - - DOUBLE_BUFFERED - This endpoint is double buffered. - [30:30] - read-write - - - INTERRUPT_PER_BUFF - Trigger an interrupt each time a buffer is done. - [29:29] - read-write - - - INTERRUPT_PER_DOUBLE_BUFF - Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. - [28:28] - read-write - - - ENDPOINT_TYPE - [27:26] - read-write - - - Control - 0 - - - Isochronous - 1 - - - Bulk - 2 - - - Interrupt - 3 - - - - - INTERRUPT_ON_STALL - Trigger an interrupt if a STALL is sent. Intended for debug only. - [17:17] - read-write - - - INTERRUPT_ON_NAK - Trigger an interrupt if a NAK is sent. Intended for debug only. - [16:16] - read-write - - - BUFFER_ADDRESS - 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. - [15:0] - read-write - - - - - EP6_OUT_CONTROL - 0x00000034 - 0x00000000 - - - ENABLE - Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. - [31:31] - read-write - - - DOUBLE_BUFFERED - This endpoint is double buffered. - [30:30] - read-write - - - INTERRUPT_PER_BUFF - Trigger an interrupt each time a buffer is done. - [29:29] - read-write - - - INTERRUPT_PER_DOUBLE_BUFF - Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. - [28:28] - read-write - - - ENDPOINT_TYPE - [27:26] - read-write - - - Control - 0 - - - Isochronous - 1 - - - Bulk - 2 - - - Interrupt - 3 - - - - - INTERRUPT_ON_STALL - Trigger an interrupt if a STALL is sent. Intended for debug only. - [17:17] - read-write - - - INTERRUPT_ON_NAK - Trigger an interrupt if a NAK is sent. Intended for debug only. - [16:16] - read-write - - - BUFFER_ADDRESS - 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. - [15:0] - read-write - - - - - EP7_IN_CONTROL - 0x00000038 - 0x00000000 - - - ENABLE - Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. - [31:31] - read-write - - - DOUBLE_BUFFERED - This endpoint is double buffered. - [30:30] - read-write - - - INTERRUPT_PER_BUFF - Trigger an interrupt each time a buffer is done. - [29:29] - read-write - - - INTERRUPT_PER_DOUBLE_BUFF - Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. - [28:28] - read-write - - - ENDPOINT_TYPE - [27:26] - read-write - - - Control - 0 - - - Isochronous - 1 - - - Bulk - 2 - - - Interrupt - 3 - - - - - INTERRUPT_ON_STALL - Trigger an interrupt if a STALL is sent. Intended for debug only. - [17:17] - read-write - - - INTERRUPT_ON_NAK - Trigger an interrupt if a NAK is sent. Intended for debug only. - [16:16] - read-write - - - BUFFER_ADDRESS - 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. - [15:0] - read-write - - - - - EP7_OUT_CONTROL - 0x0000003c - 0x00000000 - - - ENABLE - Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. - [31:31] - read-write - - - DOUBLE_BUFFERED - This endpoint is double buffered. - [30:30] - read-write - - - INTERRUPT_PER_BUFF - Trigger an interrupt each time a buffer is done. - [29:29] - read-write - - - INTERRUPT_PER_DOUBLE_BUFF - Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. - [28:28] - read-write - - - ENDPOINT_TYPE - [27:26] - read-write - - - Control - 0 - - - Isochronous - 1 - - - Bulk - 2 - - - Interrupt - 3 - - - - - INTERRUPT_ON_STALL - Trigger an interrupt if a STALL is sent. Intended for debug only. - [17:17] - read-write - - - INTERRUPT_ON_NAK - Trigger an interrupt if a NAK is sent. Intended for debug only. - [16:16] - read-write - - - BUFFER_ADDRESS - 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. - [15:0] - read-write - - - - - EP8_IN_CONTROL - 0x00000040 - 0x00000000 - - - ENABLE - Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. - [31:31] - read-write - - - DOUBLE_BUFFERED - This endpoint is double buffered. - [30:30] - read-write - - - INTERRUPT_PER_BUFF - Trigger an interrupt each time a buffer is done. - [29:29] - read-write - - - INTERRUPT_PER_DOUBLE_BUFF - Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. - [28:28] - read-write - - - ENDPOINT_TYPE - [27:26] - read-write - - - Control - 0 - - - Isochronous - 1 - - - Bulk - 2 - - - Interrupt - 3 - - - - - INTERRUPT_ON_STALL - Trigger an interrupt if a STALL is sent. Intended for debug only. - [17:17] - read-write - - - INTERRUPT_ON_NAK - Trigger an interrupt if a NAK is sent. Intended for debug only. - [16:16] - read-write - - - BUFFER_ADDRESS - 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. - [15:0] - read-write - - - - - EP8_OUT_CONTROL - 0x00000044 - 0x00000000 - - - ENABLE - Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. - [31:31] - read-write - - - DOUBLE_BUFFERED - This endpoint is double buffered. - [30:30] - read-write - - - INTERRUPT_PER_BUFF - Trigger an interrupt each time a buffer is done. - [29:29] - read-write - - - INTERRUPT_PER_DOUBLE_BUFF - Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. - [28:28] - read-write - - - ENDPOINT_TYPE - [27:26] - read-write - - - Control - 0 - - - Isochronous - 1 - - - Bulk - 2 - - - Interrupt - 3 - - - - - INTERRUPT_ON_STALL - Trigger an interrupt if a STALL is sent. Intended for debug only. - [17:17] - read-write - - - INTERRUPT_ON_NAK - Trigger an interrupt if a NAK is sent. Intended for debug only. - [16:16] - read-write - - - BUFFER_ADDRESS - 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. - [15:0] - read-write - - - - - EP9_IN_CONTROL - 0x00000048 - 0x00000000 - - - ENABLE - Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. - [31:31] - read-write - - - DOUBLE_BUFFERED - This endpoint is double buffered. - [30:30] - read-write - - - INTERRUPT_PER_BUFF - Trigger an interrupt each time a buffer is done. - [29:29] - read-write - - - INTERRUPT_PER_DOUBLE_BUFF - Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. - [28:28] - read-write - - - ENDPOINT_TYPE - [27:26] - read-write - - - Control - 0 - - - Isochronous - 1 - - - Bulk - 2 - - - Interrupt - 3 - - - - - INTERRUPT_ON_STALL - Trigger an interrupt if a STALL is sent. Intended for debug only. - [17:17] - read-write - - - INTERRUPT_ON_NAK - Trigger an interrupt if a NAK is sent. Intended for debug only. - [16:16] - read-write - - - BUFFER_ADDRESS - 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. - [15:0] - read-write - - - - - EP9_OUT_CONTROL - 0x0000004c - 0x00000000 - - - ENABLE - Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. - [31:31] - read-write - - - DOUBLE_BUFFERED - This endpoint is double buffered. - [30:30] - read-write - - - INTERRUPT_PER_BUFF - Trigger an interrupt each time a buffer is done. - [29:29] - read-write - - - INTERRUPT_PER_DOUBLE_BUFF - Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. - [28:28] - read-write - - - ENDPOINT_TYPE - [27:26] - read-write - - - Control - 0 - - - Isochronous - 1 - - - Bulk - 2 - - - Interrupt - 3 - - - - - INTERRUPT_ON_STALL - Trigger an interrupt if a STALL is sent. Intended for debug only. - [17:17] - read-write - - - INTERRUPT_ON_NAK - Trigger an interrupt if a NAK is sent. Intended for debug only. - [16:16] - read-write - - - BUFFER_ADDRESS - 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. - [15:0] - read-write - - - - - EP10_IN_CONTROL - 0x00000050 - 0x00000000 - - - ENABLE - Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. - [31:31] - read-write - - - DOUBLE_BUFFERED - This endpoint is double buffered. - [30:30] - read-write - - - INTERRUPT_PER_BUFF - Trigger an interrupt each time a buffer is done. - [29:29] - read-write - - - INTERRUPT_PER_DOUBLE_BUFF - Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. - [28:28] - read-write - - - ENDPOINT_TYPE - [27:26] - read-write - - - Control - 0 - - - Isochronous - 1 - - - Bulk - 2 - - - Interrupt - 3 - - - - - INTERRUPT_ON_STALL - Trigger an interrupt if a STALL is sent. Intended for debug only. - [17:17] - read-write - - - INTERRUPT_ON_NAK - Trigger an interrupt if a NAK is sent. Intended for debug only. - [16:16] - read-write - - - BUFFER_ADDRESS - 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. - [15:0] - read-write - - - - - EP10_OUT_CONTROL - 0x00000054 - 0x00000000 - - - ENABLE - Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. - [31:31] - read-write - - - DOUBLE_BUFFERED - This endpoint is double buffered. - [30:30] - read-write - - - INTERRUPT_PER_BUFF - Trigger an interrupt each time a buffer is done. - [29:29] - read-write - - - INTERRUPT_PER_DOUBLE_BUFF - Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. - [28:28] - read-write - - - ENDPOINT_TYPE - [27:26] - read-write - - - Control - 0 - - - Isochronous - 1 - - - Bulk - 2 - - - Interrupt - 3 - - - - - INTERRUPT_ON_STALL - Trigger an interrupt if a STALL is sent. Intended for debug only. - [17:17] - read-write - - - INTERRUPT_ON_NAK - Trigger an interrupt if a NAK is sent. Intended for debug only. - [16:16] - read-write - - - BUFFER_ADDRESS - 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. - [15:0] - read-write - - - - - EP11_IN_CONTROL - 0x00000058 - 0x00000000 - - - ENABLE - Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. - [31:31] - read-write - - - DOUBLE_BUFFERED - This endpoint is double buffered. - [30:30] - read-write - - - INTERRUPT_PER_BUFF - Trigger an interrupt each time a buffer is done. - [29:29] - read-write - - - INTERRUPT_PER_DOUBLE_BUFF - Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. - [28:28] - read-write - - - ENDPOINT_TYPE - [27:26] - read-write - - - Control - 0 - - - Isochronous - 1 - - - Bulk - 2 - - - Interrupt - 3 - - - - - INTERRUPT_ON_STALL - Trigger an interrupt if a STALL is sent. Intended for debug only. - [17:17] - read-write - - - INTERRUPT_ON_NAK - Trigger an interrupt if a NAK is sent. Intended for debug only. - [16:16] - read-write - - - BUFFER_ADDRESS - 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. - [15:0] - read-write - - - - - EP11_OUT_CONTROL - 0x0000005c - 0x00000000 - - - ENABLE - Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. - [31:31] - read-write - - - DOUBLE_BUFFERED - This endpoint is double buffered. - [30:30] - read-write - - - INTERRUPT_PER_BUFF - Trigger an interrupt each time a buffer is done. - [29:29] - read-write - - - INTERRUPT_PER_DOUBLE_BUFF - Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. - [28:28] - read-write - - - ENDPOINT_TYPE - [27:26] - read-write - - - Control - 0 - - - Isochronous - 1 - - - Bulk - 2 - - - Interrupt - 3 - - - - - INTERRUPT_ON_STALL - Trigger an interrupt if a STALL is sent. Intended for debug only. - [17:17] - read-write - - - INTERRUPT_ON_NAK - Trigger an interrupt if a NAK is sent. Intended for debug only. - [16:16] - read-write - - - BUFFER_ADDRESS - 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. - [15:0] - read-write - - - - - EP12_IN_CONTROL - 0x00000060 - 0x00000000 - - - ENABLE - Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. - [31:31] - read-write - - - DOUBLE_BUFFERED - This endpoint is double buffered. - [30:30] - read-write - - - INTERRUPT_PER_BUFF - Trigger an interrupt each time a buffer is done. - [29:29] - read-write - - - INTERRUPT_PER_DOUBLE_BUFF - Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. - [28:28] - read-write - - - ENDPOINT_TYPE - [27:26] - read-write - - - Control - 0 - - - Isochronous - 1 - - - Bulk - 2 - - - Interrupt - 3 - - - - - INTERRUPT_ON_STALL - Trigger an interrupt if a STALL is sent. Intended for debug only. - [17:17] - read-write - - - INTERRUPT_ON_NAK - Trigger an interrupt if a NAK is sent. Intended for debug only. - [16:16] - read-write - - - BUFFER_ADDRESS - 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. - [15:0] - read-write - - - - - EP12_OUT_CONTROL - 0x00000064 - 0x00000000 - - - ENABLE - Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. - [31:31] - read-write - - - DOUBLE_BUFFERED - This endpoint is double buffered. - [30:30] - read-write - - - INTERRUPT_PER_BUFF - Trigger an interrupt each time a buffer is done. - [29:29] - read-write - - - INTERRUPT_PER_DOUBLE_BUFF - Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. - [28:28] - read-write - - - ENDPOINT_TYPE - [27:26] - read-write - - - Control - 0 - - - Isochronous - 1 - - - Bulk - 2 - - - Interrupt - 3 - - - - - INTERRUPT_ON_STALL - Trigger an interrupt if a STALL is sent. Intended for debug only. - [17:17] - read-write - - - INTERRUPT_ON_NAK - Trigger an interrupt if a NAK is sent. Intended for debug only. - [16:16] - read-write - - - BUFFER_ADDRESS - 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. - [15:0] - read-write - - - - - EP13_IN_CONTROL - 0x00000068 - 0x00000000 - - - ENABLE - Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. - [31:31] - read-write - - - DOUBLE_BUFFERED - This endpoint is double buffered. - [30:30] - read-write - - - INTERRUPT_PER_BUFF - Trigger an interrupt each time a buffer is done. - [29:29] - read-write - - - INTERRUPT_PER_DOUBLE_BUFF - Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. - [28:28] - read-write - - - ENDPOINT_TYPE - [27:26] - read-write - - - Control - 0 - - - Isochronous - 1 - - - Bulk - 2 - - - Interrupt - 3 - - - - - INTERRUPT_ON_STALL - Trigger an interrupt if a STALL is sent. Intended for debug only. - [17:17] - read-write - - - INTERRUPT_ON_NAK - Trigger an interrupt if a NAK is sent. Intended for debug only. - [16:16] - read-write - - - BUFFER_ADDRESS - 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. - [15:0] - read-write - - - - - EP13_OUT_CONTROL - 0x0000006c - 0x00000000 - - - ENABLE - Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. - [31:31] - read-write - - - DOUBLE_BUFFERED - This endpoint is double buffered. - [30:30] - read-write - - - INTERRUPT_PER_BUFF - Trigger an interrupt each time a buffer is done. - [29:29] - read-write - - - INTERRUPT_PER_DOUBLE_BUFF - Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. - [28:28] - read-write - - - ENDPOINT_TYPE - [27:26] - read-write - - - Control - 0 - - - Isochronous - 1 - - - Bulk - 2 - - - Interrupt - 3 - - - - - INTERRUPT_ON_STALL - Trigger an interrupt if a STALL is sent. Intended for debug only. - [17:17] - read-write - - - INTERRUPT_ON_NAK - Trigger an interrupt if a NAK is sent. Intended for debug only. - [16:16] - read-write - - - BUFFER_ADDRESS - 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. - [15:0] - read-write - - - - - EP14_IN_CONTROL - 0x00000070 - 0x00000000 - - - ENABLE - Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. - [31:31] - read-write - - - DOUBLE_BUFFERED - This endpoint is double buffered. - [30:30] - read-write - - - INTERRUPT_PER_BUFF - Trigger an interrupt each time a buffer is done. - [29:29] - read-write - - - INTERRUPT_PER_DOUBLE_BUFF - Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. - [28:28] - read-write - - - ENDPOINT_TYPE - [27:26] - read-write - - - Control - 0 - - - Isochronous - 1 - - - Bulk - 2 - - - Interrupt - 3 - - - - - INTERRUPT_ON_STALL - Trigger an interrupt if a STALL is sent. Intended for debug only. - [17:17] - read-write - - - INTERRUPT_ON_NAK - Trigger an interrupt if a NAK is sent. Intended for debug only. - [16:16] - read-write - - - BUFFER_ADDRESS - 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. - [15:0] - read-write - - - - - EP14_OUT_CONTROL - 0x00000074 - 0x00000000 - - - ENABLE - Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. - [31:31] - read-write - - - DOUBLE_BUFFERED - This endpoint is double buffered. - [30:30] - read-write - - - INTERRUPT_PER_BUFF - Trigger an interrupt each time a buffer is done. - [29:29] - read-write - - - INTERRUPT_PER_DOUBLE_BUFF - Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. - [28:28] - read-write - - - ENDPOINT_TYPE - [27:26] - read-write - - - Control - 0 - - - Isochronous - 1 - - - Bulk - 2 - - - Interrupt - 3 - - - - - INTERRUPT_ON_STALL - Trigger an interrupt if a STALL is sent. Intended for debug only. - [17:17] - read-write - - - INTERRUPT_ON_NAK - Trigger an interrupt if a NAK is sent. Intended for debug only. - [16:16] - read-write - - - BUFFER_ADDRESS - 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. - [15:0] - read-write - - - - - EP15_IN_CONTROL - 0x00000078 - 0x00000000 - - - ENABLE - Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. - [31:31] - read-write - - - DOUBLE_BUFFERED - This endpoint is double buffered. - [30:30] - read-write - - - INTERRUPT_PER_BUFF - Trigger an interrupt each time a buffer is done. - [29:29] - read-write - - - INTERRUPT_PER_DOUBLE_BUFF - Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. - [28:28] - read-write - - - ENDPOINT_TYPE - [27:26] - read-write - - - Control - 0 - - - Isochronous - 1 - - - Bulk - 2 - - - Interrupt - 3 - - - - - INTERRUPT_ON_STALL - Trigger an interrupt if a STALL is sent. Intended for debug only. - [17:17] - read-write - - - INTERRUPT_ON_NAK - Trigger an interrupt if a NAK is sent. Intended for debug only. - [16:16] - read-write - - - BUFFER_ADDRESS - 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. - [15:0] - read-write - - - - - EP15_OUT_CONTROL - 0x0000007c - 0x00000000 - - - ENABLE - Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. - [31:31] - read-write - - - DOUBLE_BUFFERED - This endpoint is double buffered. - [30:30] - read-write - - - INTERRUPT_PER_BUFF - Trigger an interrupt each time a buffer is done. - [29:29] - read-write - - - INTERRUPT_PER_DOUBLE_BUFF - Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. - [28:28] - read-write - - - ENDPOINT_TYPE - [27:26] - read-write - - - Control - 0 - - - Isochronous - 1 - - - Bulk - 2 - - - Interrupt - 3 - - - - - INTERRUPT_ON_STALL - Trigger an interrupt if a STALL is sent. Intended for debug only. - [17:17] - read-write - - - INTERRUPT_ON_NAK - Trigger an interrupt if a NAK is sent. Intended for debug only. - [16:16] - read-write - - - BUFFER_ADDRESS - 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. - [15:0] - read-write - - - - - EP0_IN_BUFFER_CONTROL - 0x00000080 - Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. - Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. - 0x00000000 - - - FULL_1 - Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [31:31] - read-write - - - LAST_1 - Buffer 1 is the last buffer of the transfer. - [30:30] - read-write - - - PID_1 - The data pid of buffer 1. - [29:29] - read-write - - - DOUBLE_BUFFER_ISO_OFFSET - The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. - For a non Isochronous endpoint the offset is always 64 bytes. - [28:27] - read-write - - - 128 - 0 - - - 256 - 1 - - - 512 - 2 - - - 1024 - 3 - - - - - AVAILABLE_1 - Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [26:26] - read-write - - - LENGTH_1 - The length of the data in buffer 1. - [25:16] - read-write - - - FULL_0 - Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [15:15] - read-write - - - LAST_0 - Buffer 0 is the last buffer of the transfer. - [14:14] - read-write - - - PID_0 - The data pid of buffer 0. - [13:13] - read-write - - - RESET - Reset the buffer selector to buffer 0. - [12:12] - read-write - - - STALL - Reply with a stall (valid for both buffers). - [11:11] - read-write - - - AVAILABLE_0 - Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [10:10] - read-write - - - LENGTH_0 - The length of the data in buffer 1. - [9:0] - read-write - - - - - EP0_OUT_BUFFER_CONTROL - 0x00000084 - Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. - Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. - 0x00000000 - - - FULL_1 - Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [31:31] - read-write - - - LAST_1 - Buffer 1 is the last buffer of the transfer. - [30:30] - read-write - - - PID_1 - The data pid of buffer 1. - [29:29] - read-write - - - DOUBLE_BUFFER_ISO_OFFSET - The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. - For a non Isochronous endpoint the offset is always 64 bytes. - [28:27] - read-write - - - 128 - 0 - - - 256 - 1 - - - 512 - 2 - - - 1024 - 3 - - - - - AVAILABLE_1 - Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [26:26] - read-write - - - LENGTH_1 - The length of the data in buffer 1. - [25:16] - read-write - - - FULL_0 - Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [15:15] - read-write - - - LAST_0 - Buffer 0 is the last buffer of the transfer. - [14:14] - read-write - - - PID_0 - The data pid of buffer 0. - [13:13] - read-write - - - RESET - Reset the buffer selector to buffer 0. - [12:12] - read-write - - - STALL - Reply with a stall (valid for both buffers). - [11:11] - read-write - - - AVAILABLE_0 - Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [10:10] - read-write - - - LENGTH_0 - The length of the data in buffer 1. - [9:0] - read-write - - - - - EP1_IN_BUFFER_CONTROL - 0x00000088 - Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. - Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. - 0x00000000 - - - FULL_1 - Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [31:31] - read-write - - - LAST_1 - Buffer 1 is the last buffer of the transfer. - [30:30] - read-write - - - PID_1 - The data pid of buffer 1. - [29:29] - read-write - - - DOUBLE_BUFFER_ISO_OFFSET - The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. - For a non Isochronous endpoint the offset is always 64 bytes. - [28:27] - read-write - - - 128 - 0 - - - 256 - 1 - - - 512 - 2 - - - 1024 - 3 - - - - - AVAILABLE_1 - Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [26:26] - read-write - - - LENGTH_1 - The length of the data in buffer 1. - [25:16] - read-write - - - FULL_0 - Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [15:15] - read-write - - - LAST_0 - Buffer 0 is the last buffer of the transfer. - [14:14] - read-write - - - PID_0 - The data pid of buffer 0. - [13:13] - read-write - - - RESET - Reset the buffer selector to buffer 0. - [12:12] - read-write - - - STALL - Reply with a stall (valid for both buffers). - [11:11] - read-write - - - AVAILABLE_0 - Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [10:10] - read-write - - - LENGTH_0 - The length of the data in buffer 1. - [9:0] - read-write - - - - - EP1_OUT_BUFFER_CONTROL - 0x0000008c - Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. - Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. - 0x00000000 - - - FULL_1 - Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [31:31] - read-write - - - LAST_1 - Buffer 1 is the last buffer of the transfer. - [30:30] - read-write - - - PID_1 - The data pid of buffer 1. - [29:29] - read-write - - - DOUBLE_BUFFER_ISO_OFFSET - The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. - For a non Isochronous endpoint the offset is always 64 bytes. - [28:27] - read-write - - - 128 - 0 - - - 256 - 1 - - - 512 - 2 - - - 1024 - 3 - - - - - AVAILABLE_1 - Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [26:26] - read-write - - - LENGTH_1 - The length of the data in buffer 1. - [25:16] - read-write - - - FULL_0 - Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [15:15] - read-write - - - LAST_0 - Buffer 0 is the last buffer of the transfer. - [14:14] - read-write - - - PID_0 - The data pid of buffer 0. - [13:13] - read-write - - - RESET - Reset the buffer selector to buffer 0. - [12:12] - read-write - - - STALL - Reply with a stall (valid for both buffers). - [11:11] - read-write - - - AVAILABLE_0 - Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [10:10] - read-write - - - LENGTH_0 - The length of the data in buffer 1. - [9:0] - read-write - - - - - EP2_IN_BUFFER_CONTROL - 0x00000090 - Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. - Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. - 0x00000000 - - - FULL_1 - Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [31:31] - read-write - - - LAST_1 - Buffer 1 is the last buffer of the transfer. - [30:30] - read-write - - - PID_1 - The data pid of buffer 1. - [29:29] - read-write - - - DOUBLE_BUFFER_ISO_OFFSET - The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. - For a non Isochronous endpoint the offset is always 64 bytes. - [28:27] - read-write - - - 128 - 0 - - - 256 - 1 - - - 512 - 2 - - - 1024 - 3 - - - - - AVAILABLE_1 - Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [26:26] - read-write - - - LENGTH_1 - The length of the data in buffer 1. - [25:16] - read-write - - - FULL_0 - Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [15:15] - read-write - - - LAST_0 - Buffer 0 is the last buffer of the transfer. - [14:14] - read-write - - - PID_0 - The data pid of buffer 0. - [13:13] - read-write - - - RESET - Reset the buffer selector to buffer 0. - [12:12] - read-write - - - STALL - Reply with a stall (valid for both buffers). - [11:11] - read-write - - - AVAILABLE_0 - Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [10:10] - read-write - - - LENGTH_0 - The length of the data in buffer 1. - [9:0] - read-write - - - - - EP2_OUT_BUFFER_CONTROL - 0x00000094 - Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. - Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. - 0x00000000 - - - FULL_1 - Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [31:31] - read-write - - - LAST_1 - Buffer 1 is the last buffer of the transfer. - [30:30] - read-write - - - PID_1 - The data pid of buffer 1. - [29:29] - read-write - - - DOUBLE_BUFFER_ISO_OFFSET - The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. - For a non Isochronous endpoint the offset is always 64 bytes. - [28:27] - read-write - - - 128 - 0 - - - 256 - 1 - - - 512 - 2 - - - 1024 - 3 - - - - - AVAILABLE_1 - Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [26:26] - read-write - - - LENGTH_1 - The length of the data in buffer 1. - [25:16] - read-write - - - FULL_0 - Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [15:15] - read-write - - - LAST_0 - Buffer 0 is the last buffer of the transfer. - [14:14] - read-write - - - PID_0 - The data pid of buffer 0. - [13:13] - read-write - - - RESET - Reset the buffer selector to buffer 0. - [12:12] - read-write - - - STALL - Reply with a stall (valid for both buffers). - [11:11] - read-write - - - AVAILABLE_0 - Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [10:10] - read-write - - - LENGTH_0 - The length of the data in buffer 1. - [9:0] - read-write - - - - - EP3_IN_BUFFER_CONTROL - 0x00000098 - Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. - Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. - 0x00000000 - - - FULL_1 - Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [31:31] - read-write - - - LAST_1 - Buffer 1 is the last buffer of the transfer. - [30:30] - read-write - - - PID_1 - The data pid of buffer 1. - [29:29] - read-write - - - DOUBLE_BUFFER_ISO_OFFSET - The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. - For a non Isochronous endpoint the offset is always 64 bytes. - [28:27] - read-write - - - 128 - 0 - - - 256 - 1 - - - 512 - 2 - - - 1024 - 3 - - - - - AVAILABLE_1 - Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [26:26] - read-write - - - LENGTH_1 - The length of the data in buffer 1. - [25:16] - read-write - - - FULL_0 - Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [15:15] - read-write - - - LAST_0 - Buffer 0 is the last buffer of the transfer. - [14:14] - read-write - - - PID_0 - The data pid of buffer 0. - [13:13] - read-write - - - RESET - Reset the buffer selector to buffer 0. - [12:12] - read-write - - - STALL - Reply with a stall (valid for both buffers). - [11:11] - read-write - - - AVAILABLE_0 - Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [10:10] - read-write - - - LENGTH_0 - The length of the data in buffer 1. - [9:0] - read-write - - - - - EP3_OUT_BUFFER_CONTROL - 0x0000009c - Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. - Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. - 0x00000000 - - - FULL_1 - Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [31:31] - read-write - - - LAST_1 - Buffer 1 is the last buffer of the transfer. - [30:30] - read-write - - - PID_1 - The data pid of buffer 1. - [29:29] - read-write - - - DOUBLE_BUFFER_ISO_OFFSET - The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. - For a non Isochronous endpoint the offset is always 64 bytes. - [28:27] - read-write - - - 128 - 0 - - - 256 - 1 - - - 512 - 2 - - - 1024 - 3 - - - - - AVAILABLE_1 - Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [26:26] - read-write - - - LENGTH_1 - The length of the data in buffer 1. - [25:16] - read-write - - - FULL_0 - Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [15:15] - read-write - - - LAST_0 - Buffer 0 is the last buffer of the transfer. - [14:14] - read-write - - - PID_0 - The data pid of buffer 0. - [13:13] - read-write - - - RESET - Reset the buffer selector to buffer 0. - [12:12] - read-write - - - STALL - Reply with a stall (valid for both buffers). - [11:11] - read-write - - - AVAILABLE_0 - Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [10:10] - read-write - - - LENGTH_0 - The length of the data in buffer 1. - [9:0] - read-write - - - - - EP4_IN_BUFFER_CONTROL - 0x000000a0 - Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. - Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. - 0x00000000 - - - FULL_1 - Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [31:31] - read-write - - - LAST_1 - Buffer 1 is the last buffer of the transfer. - [30:30] - read-write - - - PID_1 - The data pid of buffer 1. - [29:29] - read-write - - - DOUBLE_BUFFER_ISO_OFFSET - The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. - For a non Isochronous endpoint the offset is always 64 bytes. - [28:27] - read-write - - - 128 - 0 - - - 256 - 1 - - - 512 - 2 - - - 1024 - 3 - - - - - AVAILABLE_1 - Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [26:26] - read-write - - - LENGTH_1 - The length of the data in buffer 1. - [25:16] - read-write - - - FULL_0 - Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [15:15] - read-write - - - LAST_0 - Buffer 0 is the last buffer of the transfer. - [14:14] - read-write - - - PID_0 - The data pid of buffer 0. - [13:13] - read-write - - - RESET - Reset the buffer selector to buffer 0. - [12:12] - read-write - - - STALL - Reply with a stall (valid for both buffers). - [11:11] - read-write - - - AVAILABLE_0 - Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [10:10] - read-write - - - LENGTH_0 - The length of the data in buffer 1. - [9:0] - read-write - - - - - EP4_OUT_BUFFER_CONTROL - 0x000000a4 - Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. - Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. - 0x00000000 - - - FULL_1 - Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [31:31] - read-write - - - LAST_1 - Buffer 1 is the last buffer of the transfer. - [30:30] - read-write - - - PID_1 - The data pid of buffer 1. - [29:29] - read-write - - - DOUBLE_BUFFER_ISO_OFFSET - The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. - For a non Isochronous endpoint the offset is always 64 bytes. - [28:27] - read-write - - - 128 - 0 - - - 256 - 1 - - - 512 - 2 - - - 1024 - 3 - - - - - AVAILABLE_1 - Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [26:26] - read-write - - - LENGTH_1 - The length of the data in buffer 1. - [25:16] - read-write - - - FULL_0 - Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [15:15] - read-write - - - LAST_0 - Buffer 0 is the last buffer of the transfer. - [14:14] - read-write - - - PID_0 - The data pid of buffer 0. - [13:13] - read-write - - - RESET - Reset the buffer selector to buffer 0. - [12:12] - read-write - - - STALL - Reply with a stall (valid for both buffers). - [11:11] - read-write - - - AVAILABLE_0 - Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [10:10] - read-write - - - LENGTH_0 - The length of the data in buffer 1. - [9:0] - read-write - - - - - EP5_IN_BUFFER_CONTROL - 0x000000a8 - Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. - Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. - 0x00000000 - - - FULL_1 - Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [31:31] - read-write - - - LAST_1 - Buffer 1 is the last buffer of the transfer. - [30:30] - read-write - - - PID_1 - The data pid of buffer 1. - [29:29] - read-write - - - DOUBLE_BUFFER_ISO_OFFSET - The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. - For a non Isochronous endpoint the offset is always 64 bytes. - [28:27] - read-write - - - 128 - 0 - - - 256 - 1 - - - 512 - 2 - - - 1024 - 3 - - - - - AVAILABLE_1 - Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [26:26] - read-write - - - LENGTH_1 - The length of the data in buffer 1. - [25:16] - read-write - - - FULL_0 - Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [15:15] - read-write - - - LAST_0 - Buffer 0 is the last buffer of the transfer. - [14:14] - read-write - - - PID_0 - The data pid of buffer 0. - [13:13] - read-write - - - RESET - Reset the buffer selector to buffer 0. - [12:12] - read-write - - - STALL - Reply with a stall (valid for both buffers). - [11:11] - read-write - - - AVAILABLE_0 - Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [10:10] - read-write - - - LENGTH_0 - The length of the data in buffer 1. - [9:0] - read-write - - - - - EP5_OUT_BUFFER_CONTROL - 0x000000ac - Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. - Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. - 0x00000000 - - - FULL_1 - Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [31:31] - read-write - - - LAST_1 - Buffer 1 is the last buffer of the transfer. - [30:30] - read-write - - - PID_1 - The data pid of buffer 1. - [29:29] - read-write - - - DOUBLE_BUFFER_ISO_OFFSET - The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. - For a non Isochronous endpoint the offset is always 64 bytes. - [28:27] - read-write - - - 128 - 0 - - - 256 - 1 - - - 512 - 2 - - - 1024 - 3 - - - - - AVAILABLE_1 - Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [26:26] - read-write - - - LENGTH_1 - The length of the data in buffer 1. - [25:16] - read-write - - - FULL_0 - Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [15:15] - read-write - - - LAST_0 - Buffer 0 is the last buffer of the transfer. - [14:14] - read-write - - - PID_0 - The data pid of buffer 0. - [13:13] - read-write - - - RESET - Reset the buffer selector to buffer 0. - [12:12] - read-write - - - STALL - Reply with a stall (valid for both buffers). - [11:11] - read-write - - - AVAILABLE_0 - Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [10:10] - read-write - - - LENGTH_0 - The length of the data in buffer 1. - [9:0] - read-write - - - - - EP6_IN_BUFFER_CONTROL - 0x000000b0 - Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. - Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. - 0x00000000 - - - FULL_1 - Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [31:31] - read-write - - - LAST_1 - Buffer 1 is the last buffer of the transfer. - [30:30] - read-write - - - PID_1 - The data pid of buffer 1. - [29:29] - read-write - - - DOUBLE_BUFFER_ISO_OFFSET - The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. - For a non Isochronous endpoint the offset is always 64 bytes. - [28:27] - read-write - - - 128 - 0 - - - 256 - 1 - - - 512 - 2 - - - 1024 - 3 - - - - - AVAILABLE_1 - Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [26:26] - read-write - - - LENGTH_1 - The length of the data in buffer 1. - [25:16] - read-write - - - FULL_0 - Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [15:15] - read-write - - - LAST_0 - Buffer 0 is the last buffer of the transfer. - [14:14] - read-write - - - PID_0 - The data pid of buffer 0. - [13:13] - read-write - - - RESET - Reset the buffer selector to buffer 0. - [12:12] - read-write - - - STALL - Reply with a stall (valid for both buffers). - [11:11] - read-write - - - AVAILABLE_0 - Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [10:10] - read-write - - - LENGTH_0 - The length of the data in buffer 1. - [9:0] - read-write - - - - - EP6_OUT_BUFFER_CONTROL - 0x000000b4 - Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. - Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. - 0x00000000 - - - FULL_1 - Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [31:31] - read-write - - - LAST_1 - Buffer 1 is the last buffer of the transfer. - [30:30] - read-write - - - PID_1 - The data pid of buffer 1. - [29:29] - read-write - - - DOUBLE_BUFFER_ISO_OFFSET - The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. - For a non Isochronous endpoint the offset is always 64 bytes. - [28:27] - read-write - - - 128 - 0 - - - 256 - 1 - - - 512 - 2 - - - 1024 - 3 - - - - - AVAILABLE_1 - Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [26:26] - read-write - - - LENGTH_1 - The length of the data in buffer 1. - [25:16] - read-write - - - FULL_0 - Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [15:15] - read-write - - - LAST_0 - Buffer 0 is the last buffer of the transfer. - [14:14] - read-write - - - PID_0 - The data pid of buffer 0. - [13:13] - read-write - - - RESET - Reset the buffer selector to buffer 0. - [12:12] - read-write - - - STALL - Reply with a stall (valid for both buffers). - [11:11] - read-write - - - AVAILABLE_0 - Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [10:10] - read-write - - - LENGTH_0 - The length of the data in buffer 1. - [9:0] - read-write - - - - - EP7_IN_BUFFER_CONTROL - 0x000000b8 - Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. - Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. - 0x00000000 - - - FULL_1 - Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [31:31] - read-write - - - LAST_1 - Buffer 1 is the last buffer of the transfer. - [30:30] - read-write - - - PID_1 - The data pid of buffer 1. - [29:29] - read-write - - - DOUBLE_BUFFER_ISO_OFFSET - The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. - For a non Isochronous endpoint the offset is always 64 bytes. - [28:27] - read-write - - - 128 - 0 - - - 256 - 1 - - - 512 - 2 - - - 1024 - 3 - - - - - AVAILABLE_1 - Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [26:26] - read-write - - - LENGTH_1 - The length of the data in buffer 1. - [25:16] - read-write - - - FULL_0 - Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [15:15] - read-write - - - LAST_0 - Buffer 0 is the last buffer of the transfer. - [14:14] - read-write - - - PID_0 - The data pid of buffer 0. - [13:13] - read-write - - - RESET - Reset the buffer selector to buffer 0. - [12:12] - read-write - - - STALL - Reply with a stall (valid for both buffers). - [11:11] - read-write - - - AVAILABLE_0 - Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [10:10] - read-write - - - LENGTH_0 - The length of the data in buffer 1. - [9:0] - read-write - - - - - EP7_OUT_BUFFER_CONTROL - 0x000000bc - Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. - Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. - 0x00000000 - - - FULL_1 - Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [31:31] - read-write - - - LAST_1 - Buffer 1 is the last buffer of the transfer. - [30:30] - read-write - - - PID_1 - The data pid of buffer 1. - [29:29] - read-write - - - DOUBLE_BUFFER_ISO_OFFSET - The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. - For a non Isochronous endpoint the offset is always 64 bytes. - [28:27] - read-write - - - 128 - 0 - - - 256 - 1 - - - 512 - 2 - - - 1024 - 3 - - - - - AVAILABLE_1 - Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [26:26] - read-write - - - LENGTH_1 - The length of the data in buffer 1. - [25:16] - read-write - - - FULL_0 - Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [15:15] - read-write - - - LAST_0 - Buffer 0 is the last buffer of the transfer. - [14:14] - read-write - - - PID_0 - The data pid of buffer 0. - [13:13] - read-write - - - RESET - Reset the buffer selector to buffer 0. - [12:12] - read-write - - - STALL - Reply with a stall (valid for both buffers). - [11:11] - read-write - - - AVAILABLE_0 - Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [10:10] - read-write - - - LENGTH_0 - The length of the data in buffer 1. - [9:0] - read-write - - - - - EP8_IN_BUFFER_CONTROL - 0x000000c0 - Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. - Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. - 0x00000000 - - - FULL_1 - Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [31:31] - read-write - - - LAST_1 - Buffer 1 is the last buffer of the transfer. - [30:30] - read-write - - - PID_1 - The data pid of buffer 1. - [29:29] - read-write - - - DOUBLE_BUFFER_ISO_OFFSET - The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. - For a non Isochronous endpoint the offset is always 64 bytes. - [28:27] - read-write - - - 128 - 0 - - - 256 - 1 - - - 512 - 2 - - - 1024 - 3 - - - - - AVAILABLE_1 - Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [26:26] - read-write - - - LENGTH_1 - The length of the data in buffer 1. - [25:16] - read-write - - - FULL_0 - Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [15:15] - read-write - - - LAST_0 - Buffer 0 is the last buffer of the transfer. - [14:14] - read-write - - - PID_0 - The data pid of buffer 0. - [13:13] - read-write - - - RESET - Reset the buffer selector to buffer 0. - [12:12] - read-write - - - STALL - Reply with a stall (valid for both buffers). - [11:11] - read-write - - - AVAILABLE_0 - Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [10:10] - read-write - - - LENGTH_0 - The length of the data in buffer 1. - [9:0] - read-write - - - - - EP8_OUT_BUFFER_CONTROL - 0x000000c4 - Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. - Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. - 0x00000000 - - - FULL_1 - Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [31:31] - read-write - - - LAST_1 - Buffer 1 is the last buffer of the transfer. - [30:30] - read-write - - - PID_1 - The data pid of buffer 1. - [29:29] - read-write - - - DOUBLE_BUFFER_ISO_OFFSET - The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. - For a non Isochronous endpoint the offset is always 64 bytes. - [28:27] - read-write - - - 128 - 0 - - - 256 - 1 - - - 512 - 2 - - - 1024 - 3 - - - - - AVAILABLE_1 - Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [26:26] - read-write - - - LENGTH_1 - The length of the data in buffer 1. - [25:16] - read-write - - - FULL_0 - Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [15:15] - read-write - - - LAST_0 - Buffer 0 is the last buffer of the transfer. - [14:14] - read-write - - - PID_0 - The data pid of buffer 0. - [13:13] - read-write - - - RESET - Reset the buffer selector to buffer 0. - [12:12] - read-write - - - STALL - Reply with a stall (valid for both buffers). - [11:11] - read-write - - - AVAILABLE_0 - Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [10:10] - read-write - - - LENGTH_0 - The length of the data in buffer 1. - [9:0] - read-write - - - - - EP9_IN_BUFFER_CONTROL - 0x000000c8 - Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. - Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. - 0x00000000 - - - FULL_1 - Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [31:31] - read-write - - - LAST_1 - Buffer 1 is the last buffer of the transfer. - [30:30] - read-write - - - PID_1 - The data pid of buffer 1. - [29:29] - read-write - - - DOUBLE_BUFFER_ISO_OFFSET - The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. - For a non Isochronous endpoint the offset is always 64 bytes. - [28:27] - read-write - - - 128 - 0 - - - 256 - 1 - - - 512 - 2 - - - 1024 - 3 - - - - - AVAILABLE_1 - Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [26:26] - read-write - - - LENGTH_1 - The length of the data in buffer 1. - [25:16] - read-write - - - FULL_0 - Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [15:15] - read-write - - - LAST_0 - Buffer 0 is the last buffer of the transfer. - [14:14] - read-write - - - PID_0 - The data pid of buffer 0. - [13:13] - read-write - - - RESET - Reset the buffer selector to buffer 0. - [12:12] - read-write - - - STALL - Reply with a stall (valid for both buffers). - [11:11] - read-write - - - AVAILABLE_0 - Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [10:10] - read-write - - - LENGTH_0 - The length of the data in buffer 1. - [9:0] - read-write - - - - - EP9_OUT_BUFFER_CONTROL - 0x000000cc - Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. - Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. - 0x00000000 - - - FULL_1 - Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [31:31] - read-write - - - LAST_1 - Buffer 1 is the last buffer of the transfer. - [30:30] - read-write - - - PID_1 - The data pid of buffer 1. - [29:29] - read-write - - - DOUBLE_BUFFER_ISO_OFFSET - The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. - For a non Isochronous endpoint the offset is always 64 bytes. - [28:27] - read-write - - - 128 - 0 - - - 256 - 1 - - - 512 - 2 - - - 1024 - 3 - - - - - AVAILABLE_1 - Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [26:26] - read-write - - - LENGTH_1 - The length of the data in buffer 1. - [25:16] - read-write - - - FULL_0 - Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [15:15] - read-write - - - LAST_0 - Buffer 0 is the last buffer of the transfer. - [14:14] - read-write - - - PID_0 - The data pid of buffer 0. - [13:13] - read-write - - - RESET - Reset the buffer selector to buffer 0. - [12:12] - read-write - - - STALL - Reply with a stall (valid for both buffers). - [11:11] - read-write - - - AVAILABLE_0 - Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [10:10] - read-write - - - LENGTH_0 - The length of the data in buffer 1. - [9:0] - read-write - - - - - EP10_IN_BUFFER_CONTROL - 0x000000d0 - Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. - Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. - 0x00000000 - - - FULL_1 - Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [31:31] - read-write - - - LAST_1 - Buffer 1 is the last buffer of the transfer. - [30:30] - read-write - - - PID_1 - The data pid of buffer 1. - [29:29] - read-write - - - DOUBLE_BUFFER_ISO_OFFSET - The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. - For a non Isochronous endpoint the offset is always 64 bytes. - [28:27] - read-write - - - 128 - 0 - - - 256 - 1 - - - 512 - 2 - - - 1024 - 3 - - - - - AVAILABLE_1 - Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [26:26] - read-write - - - LENGTH_1 - The length of the data in buffer 1. - [25:16] - read-write - - - FULL_0 - Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [15:15] - read-write - - - LAST_0 - Buffer 0 is the last buffer of the transfer. - [14:14] - read-write - - - PID_0 - The data pid of buffer 0. - [13:13] - read-write - - - RESET - Reset the buffer selector to buffer 0. - [12:12] - read-write - - - STALL - Reply with a stall (valid for both buffers). - [11:11] - read-write - - - AVAILABLE_0 - Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [10:10] - read-write - - - LENGTH_0 - The length of the data in buffer 1. - [9:0] - read-write - - - - - EP10_OUT_BUFFER_CONTROL - 0x000000d4 - Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. - Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. - 0x00000000 - - - FULL_1 - Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [31:31] - read-write - - - LAST_1 - Buffer 1 is the last buffer of the transfer. - [30:30] - read-write - - - PID_1 - The data pid of buffer 1. - [29:29] - read-write - - - DOUBLE_BUFFER_ISO_OFFSET - The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. - For a non Isochronous endpoint the offset is always 64 bytes. - [28:27] - read-write - - - 128 - 0 - - - 256 - 1 - - - 512 - 2 - - - 1024 - 3 - - - - - AVAILABLE_1 - Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [26:26] - read-write - - - LENGTH_1 - The length of the data in buffer 1. - [25:16] - read-write - - - FULL_0 - Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [15:15] - read-write - - - LAST_0 - Buffer 0 is the last buffer of the transfer. - [14:14] - read-write - - - PID_0 - The data pid of buffer 0. - [13:13] - read-write - - - RESET - Reset the buffer selector to buffer 0. - [12:12] - read-write - - - STALL - Reply with a stall (valid for both buffers). - [11:11] - read-write - - - AVAILABLE_0 - Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [10:10] - read-write - - - LENGTH_0 - The length of the data in buffer 1. - [9:0] - read-write - - - - - EP11_IN_BUFFER_CONTROL - 0x000000d8 - Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. - Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. - 0x00000000 - - - FULL_1 - Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [31:31] - read-write - - - LAST_1 - Buffer 1 is the last buffer of the transfer. - [30:30] - read-write - - - PID_1 - The data pid of buffer 1. - [29:29] - read-write - - - DOUBLE_BUFFER_ISO_OFFSET - The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. - For a non Isochronous endpoint the offset is always 64 bytes. - [28:27] - read-write - - - 128 - 0 - - - 256 - 1 - - - 512 - 2 - - - 1024 - 3 - - - - - AVAILABLE_1 - Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [26:26] - read-write - - - LENGTH_1 - The length of the data in buffer 1. - [25:16] - read-write - - - FULL_0 - Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [15:15] - read-write - - - LAST_0 - Buffer 0 is the last buffer of the transfer. - [14:14] - read-write - - - PID_0 - The data pid of buffer 0. - [13:13] - read-write - - - RESET - Reset the buffer selector to buffer 0. - [12:12] - read-write - - - STALL - Reply with a stall (valid for both buffers). - [11:11] - read-write - - - AVAILABLE_0 - Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [10:10] - read-write - - - LENGTH_0 - The length of the data in buffer 1. - [9:0] - read-write - - - - - EP11_OUT_BUFFER_CONTROL - 0x000000dc - Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. - Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. - 0x00000000 - - - FULL_1 - Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [31:31] - read-write - - - LAST_1 - Buffer 1 is the last buffer of the transfer. - [30:30] - read-write - - - PID_1 - The data pid of buffer 1. - [29:29] - read-write - - - DOUBLE_BUFFER_ISO_OFFSET - The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. - For a non Isochronous endpoint the offset is always 64 bytes. - [28:27] - read-write - - - 128 - 0 - - - 256 - 1 - - - 512 - 2 - - - 1024 - 3 - - - - - AVAILABLE_1 - Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [26:26] - read-write - - - LENGTH_1 - The length of the data in buffer 1. - [25:16] - read-write - - - FULL_0 - Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [15:15] - read-write - - - LAST_0 - Buffer 0 is the last buffer of the transfer. - [14:14] - read-write - - - PID_0 - The data pid of buffer 0. - [13:13] - read-write - - - RESET - Reset the buffer selector to buffer 0. - [12:12] - read-write - - - STALL - Reply with a stall (valid for both buffers). - [11:11] - read-write - - - AVAILABLE_0 - Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [10:10] - read-write - - - LENGTH_0 - The length of the data in buffer 1. - [9:0] - read-write - - - - - EP12_IN_BUFFER_CONTROL - 0x000000e0 - Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. - Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. - 0x00000000 - - - FULL_1 - Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [31:31] - read-write - - - LAST_1 - Buffer 1 is the last buffer of the transfer. - [30:30] - read-write - - - PID_1 - The data pid of buffer 1. - [29:29] - read-write - - - DOUBLE_BUFFER_ISO_OFFSET - The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. - For a non Isochronous endpoint the offset is always 64 bytes. - [28:27] - read-write - - - 128 - 0 - - - 256 - 1 - - - 512 - 2 - - - 1024 - 3 - - - - - AVAILABLE_1 - Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [26:26] - read-write - - - LENGTH_1 - The length of the data in buffer 1. - [25:16] - read-write - - - FULL_0 - Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [15:15] - read-write - - - LAST_0 - Buffer 0 is the last buffer of the transfer. - [14:14] - read-write - - - PID_0 - The data pid of buffer 0. - [13:13] - read-write - - - RESET - Reset the buffer selector to buffer 0. - [12:12] - read-write - - - STALL - Reply with a stall (valid for both buffers). - [11:11] - read-write - - - AVAILABLE_0 - Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [10:10] - read-write - - - LENGTH_0 - The length of the data in buffer 1. - [9:0] - read-write - - - - - EP12_OUT_BUFFER_CONTROL - 0x000000e4 - Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. - Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. - 0x00000000 - - - FULL_1 - Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [31:31] - read-write - - - LAST_1 - Buffer 1 is the last buffer of the transfer. - [30:30] - read-write - - - PID_1 - The data pid of buffer 1. - [29:29] - read-write - - - DOUBLE_BUFFER_ISO_OFFSET - The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. - For a non Isochronous endpoint the offset is always 64 bytes. - [28:27] - read-write - - - 128 - 0 - - - 256 - 1 - - - 512 - 2 - - - 1024 - 3 - - - - - AVAILABLE_1 - Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [26:26] - read-write - - - LENGTH_1 - The length of the data in buffer 1. - [25:16] - read-write - - - FULL_0 - Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [15:15] - read-write - - - LAST_0 - Buffer 0 is the last buffer of the transfer. - [14:14] - read-write - - - PID_0 - The data pid of buffer 0. - [13:13] - read-write - - - RESET - Reset the buffer selector to buffer 0. - [12:12] - read-write - - - STALL - Reply with a stall (valid for both buffers). - [11:11] - read-write - - - AVAILABLE_0 - Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [10:10] - read-write - - - LENGTH_0 - The length of the data in buffer 1. - [9:0] - read-write - - - - - EP13_IN_BUFFER_CONTROL - 0x000000e8 - Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. - Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. - 0x00000000 - - - FULL_1 - Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [31:31] - read-write - - - LAST_1 - Buffer 1 is the last buffer of the transfer. - [30:30] - read-write - - - PID_1 - The data pid of buffer 1. - [29:29] - read-write - - - DOUBLE_BUFFER_ISO_OFFSET - The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. - For a non Isochronous endpoint the offset is always 64 bytes. - [28:27] - read-write - - - 128 - 0 - - - 256 - 1 - - - 512 - 2 - - - 1024 - 3 - - - - - AVAILABLE_1 - Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [26:26] - read-write - - - LENGTH_1 - The length of the data in buffer 1. - [25:16] - read-write - - - FULL_0 - Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [15:15] - read-write - - - LAST_0 - Buffer 0 is the last buffer of the transfer. - [14:14] - read-write - - - PID_0 - The data pid of buffer 0. - [13:13] - read-write - - - RESET - Reset the buffer selector to buffer 0. - [12:12] - read-write - - - STALL - Reply with a stall (valid for both buffers). - [11:11] - read-write - - - AVAILABLE_0 - Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [10:10] - read-write - - - LENGTH_0 - The length of the data in buffer 1. - [9:0] - read-write - - - - - EP13_OUT_BUFFER_CONTROL - 0x000000ec - Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. - Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. - 0x00000000 - - - FULL_1 - Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [31:31] - read-write - - - LAST_1 - Buffer 1 is the last buffer of the transfer. - [30:30] - read-write - - - PID_1 - The data pid of buffer 1. - [29:29] - read-write - - - DOUBLE_BUFFER_ISO_OFFSET - The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. - For a non Isochronous endpoint the offset is always 64 bytes. - [28:27] - read-write - - - 128 - 0 - - - 256 - 1 - - - 512 - 2 - - - 1024 - 3 - - - - - AVAILABLE_1 - Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [26:26] - read-write - - - LENGTH_1 - The length of the data in buffer 1. - [25:16] - read-write - - - FULL_0 - Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [15:15] - read-write - - - LAST_0 - Buffer 0 is the last buffer of the transfer. - [14:14] - read-write - - - PID_0 - The data pid of buffer 0. - [13:13] - read-write - - - RESET - Reset the buffer selector to buffer 0. - [12:12] - read-write - - - STALL - Reply with a stall (valid for both buffers). - [11:11] - read-write - - - AVAILABLE_0 - Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [10:10] - read-write - - - LENGTH_0 - The length of the data in buffer 1. - [9:0] - read-write - - - - - EP14_IN_BUFFER_CONTROL - 0x000000f0 - Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. - Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. - 0x00000000 - - - FULL_1 - Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [31:31] - read-write - - - LAST_1 - Buffer 1 is the last buffer of the transfer. - [30:30] - read-write - - - PID_1 - The data pid of buffer 1. - [29:29] - read-write - - - DOUBLE_BUFFER_ISO_OFFSET - The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. - For a non Isochronous endpoint the offset is always 64 bytes. - [28:27] - read-write - - - 128 - 0 - - - 256 - 1 - - - 512 - 2 - - - 1024 - 3 - - - - - AVAILABLE_1 - Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [26:26] - read-write - - - LENGTH_1 - The length of the data in buffer 1. - [25:16] - read-write - - - FULL_0 - Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [15:15] - read-write - - - LAST_0 - Buffer 0 is the last buffer of the transfer. - [14:14] - read-write - - - PID_0 - The data pid of buffer 0. - [13:13] - read-write - - - RESET - Reset the buffer selector to buffer 0. - [12:12] - read-write - - - STALL - Reply with a stall (valid for both buffers). - [11:11] - read-write - - - AVAILABLE_0 - Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [10:10] - read-write - - - LENGTH_0 - The length of the data in buffer 1. - [9:0] - read-write - - - - - EP14_OUT_BUFFER_CONTROL - 0x000000f4 - Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. - Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. - 0x00000000 - - - FULL_1 - Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [31:31] - read-write - - - LAST_1 - Buffer 1 is the last buffer of the transfer. - [30:30] - read-write - - - PID_1 - The data pid of buffer 1. - [29:29] - read-write - - - DOUBLE_BUFFER_ISO_OFFSET - The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. - For a non Isochronous endpoint the offset is always 64 bytes. - [28:27] - read-write - - - 128 - 0 - - - 256 - 1 - - - 512 - 2 - - - 1024 - 3 - - - - - AVAILABLE_1 - Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [26:26] - read-write - - - LENGTH_1 - The length of the data in buffer 1. - [25:16] - read-write - - - FULL_0 - Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [15:15] - read-write - - - LAST_0 - Buffer 0 is the last buffer of the transfer. - [14:14] - read-write - - - PID_0 - The data pid of buffer 0. - [13:13] - read-write - - - RESET - Reset the buffer selector to buffer 0. - [12:12] - read-write - - - STALL - Reply with a stall (valid for both buffers). - [11:11] - read-write - - - AVAILABLE_0 - Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [10:10] - read-write - - - LENGTH_0 - The length of the data in buffer 1. - [9:0] - read-write - - - - - EP15_IN_BUFFER_CONTROL - 0x000000f8 - Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. - Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. - 0x00000000 - - - FULL_1 - Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [31:31] - read-write - - - LAST_1 - Buffer 1 is the last buffer of the transfer. - [30:30] - read-write - - - PID_1 - The data pid of buffer 1. - [29:29] - read-write - - - DOUBLE_BUFFER_ISO_OFFSET - The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. - For a non Isochronous endpoint the offset is always 64 bytes. - [28:27] - read-write - - - 128 - 0 - - - 256 - 1 - - - 512 - 2 - - - 1024 - 3 - - - - - AVAILABLE_1 - Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [26:26] - read-write - - - LENGTH_1 - The length of the data in buffer 1. - [25:16] - read-write - - - FULL_0 - Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [15:15] - read-write - - - LAST_0 - Buffer 0 is the last buffer of the transfer. - [14:14] - read-write - - - PID_0 - The data pid of buffer 0. - [13:13] - read-write - - - RESET - Reset the buffer selector to buffer 0. - [12:12] - read-write - - - STALL - Reply with a stall (valid for both buffers). - [11:11] - read-write - - - AVAILABLE_0 - Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [10:10] - read-write - - - LENGTH_0 - The length of the data in buffer 1. - [9:0] - read-write - - - - - EP15_OUT_BUFFER_CONTROL - 0x000000fc - Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. - Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. - 0x00000000 - - - FULL_1 - Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [31:31] - read-write - - - LAST_1 - Buffer 1 is the last buffer of the transfer. - [30:30] - read-write - - - PID_1 - The data pid of buffer 1. - [29:29] - read-write - - - DOUBLE_BUFFER_ISO_OFFSET - The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. - For a non Isochronous endpoint the offset is always 64 bytes. - [28:27] - read-write - - - 128 - 0 - - - 256 - 1 - - - 512 - 2 - - - 1024 - 3 - - - - - AVAILABLE_1 - Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [26:26] - read-write - - - LENGTH_1 - The length of the data in buffer 1. - [25:16] - read-write - - - FULL_0 - Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [15:15] - read-write - - - LAST_0 - Buffer 0 is the last buffer of the transfer. - [14:14] - read-write - - - PID_0 - The data pid of buffer 0. - [13:13] - read-write - - - RESET - Reset the buffer selector to buffer 0. - [12:12] - read-write - - - STALL - Reply with a stall (valid for both buffers). - [11:11] - read-write - - - AVAILABLE_0 - Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [10:10] - read-write - - - LENGTH_0 - The length of the data in buffer 1. - [9:0] - read-write - - - - - - - diff --git a/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/platform_defs.h b/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/platform_defs.h deleted file mode 100644 index 6e5eba2f79..0000000000 --- a/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/platform_defs.h +++ /dev/null @@ -1,163 +0,0 @@ -/* - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _HARDWARE_PLATFORM_DEFS_H -#define _HARDWARE_PLATFORM_DEFS_H - -// This header is included from C and assembler - intended mostly for #defines; guard other stuff with #ifdef __ASSEMBLER__ - -#ifndef _u -#ifdef __ASSEMBLER__ -#define _u(x) x -#else -#define _u(x) x ## u -#endif -#endif - -#define NUM_CORES _u(2) -#define NUM_DMA_CHANNELS _u(16) -#define NUM_DMA_TIMERS _u(4) -#define NUM_DMA_MPU_REGIONS _u(8) -#define NUM_DMA_IRQS _u(4) -#define NUM_IRQS _u(52) -#define NUM_USER_IRQS _u(6) -#define NUM_PIOS _u(3) -#define NUM_PIO_STATE_MACHINES _u(4) -#define NUM_PIO_IRQS _u(2) -#define NUM_PWM_SLICES _u(12) -#define NUM_PWM_IRQS _u(2) -#define NUM_SPIN_LOCKS _u(32) -#define NUM_UARTS _u(2) -#define NUM_I2CS _u(2) -#define NUM_SPIS _u(2) -#define NUM_GENERIC_TIMERS _u(2) -#define NUM_ALARMS _u(4) -#if PICO_RP2350A -#define NUM_ADC_CHANNELS _u(5) -#define ADC_BASE_PIN _u(26) -#else -#define NUM_ADC_CHANNELS _u(9) -#define ADC_BASE_PIN _u(40) -#endif -#define NUM_RESETS _u(28) -#define NUM_DOORBELLS _u(8) - -#if PICO_RP2350A -#define NUM_BANK0_GPIOS _u(30) -#else -#define NUM_BANK0_GPIOS _u(48) -#endif -#define NUM_QSPI_GPIOS _u(6) - -#define NUM_OTP_PAGES _u(64) -#define NUM_OTP_PAGE_ROWS _u(64) -#define NUM_OTP_ROWS (NUM_OTP_PAGES * NUM_OTP_PAGE_ROWS) - -#define PIO_INSTRUCTION_COUNT _u(32) - -#define NUM_MPU_REGIONS _u(8) -#define NUM_SAU_REGIONS _u(8) -#define NUM_BOOT_LOCKS _u(8) - -#define BOOTRAM_SIZE _u(0x400) -#define USBCTRL_DPRAM_SIZE _u(4096) - -#ifndef __riscv -#define HAS_GPIO_COPROCESSOR 1 -#define HAS_DOUBLE_COPROCESSOR 1 -#define HAS_REDUNDANCY_COPROCESSOR 1 -#endif -#define HAS_POWMAN_TIMER 1 -#define HAS_RP2350_TRNG 1 -#define HAS_HSTX 1 - -// PICO_CONFIG: XOSC_HZ, Crystal oscillator frequency in Hz, type=int, default=12000000, advanced=true, group=hardware_base -// NOTE: The system and USB clocks are generated from the frequency using two PLLs. -// If you override this define, or SYS_CLK_HZ/USB_CLK_HZ below, you will *also* need to add your own adjusted PLL set-up defines to -// override the defaults which live in src/rp2_common/hardware_clocks/include/hardware/clocks.h -// Please see the comments there about calculating the new PLL setting values. -#ifndef XOSC_HZ -#ifdef XOSC_KHZ -#define XOSC_HZ ((XOSC_KHZ) * _u(1000)) -#elif defined(XOSC_MHZ) -#define XOSC_HZ ((XOSC_MHZ) * _u(1000000)) -#else -#define XOSC_HZ _u(12000000) -#endif -#endif - -// PICO_CONFIG: SYS_CLK_HZ, System operating frequency in Hz, type=int, default=150000000, advanced=true, group=hardware_base -#ifndef SYS_CLK_HZ -#ifdef SYS_CLK_KHZ -#define SYS_CLK_HZ ((SYS_CLK_KHZ) * _u(1000)) -#elif defined(SYS_CLK_MHZ) -#define SYS_CLK_HZ ((SYS_CLK_MHZ) * _u(1000000)) -#else -#define SYS_CLK_HZ _u(150000000) -#endif -#endif - -// PICO_CONFIG: USB_CLK_HZ, USB clock frequency. Must be 48MHz for the USB interface to operate correctly, type=int, default=48000000, advanced=true, group=hardware_base -#ifndef USB_CLK_HZ -#ifdef USB_CLK_KHZ -#define USB_CLK_HZ ((USB_CLK_KHZ) * _u(1000)) -#elif defined(USB_CLK_MHZ) -#define USB_CLK_HZ ((USB_CLK_MHZ) * _u(1000000)) -#else -#define USB_CLK_HZ _u(48000000) -#endif -#endif - -// For backwards compatibility define XOSC_KHZ if the frequency is indeed an integer number of Khz. -#if defined(XOSC_HZ) && !defined(XOSC_KHZ) && (XOSC_HZ % 1000 == 0) -#define XOSC_KHZ (XOSC_HZ / 1000) -#endif - -// For backwards compatibility define XOSC_MHZ if the frequency is indeed an integer number of Mhz. -#if defined(XOSC_KHZ) && !defined(XOSC_MHZ) && (XOSC_KHZ % 1000 == 0) -#define XOSC_MHZ (XOSC_KHZ / 1000) -#endif - -// For backwards compatibility define SYS_CLK_KHZ if the frequency is indeed an integer number of Khz. -#if defined(SYS_CLK_HZ) && !defined(SYS_CLK_KHZ) && (SYS_CLK_HZ % 1000 == 0) -#define SYS_CLK_KHZ (SYS_CLK_HZ / 1000) -#endif - -// For backwards compatibility define SYS_CLK_MHZ if the frequency is indeed an integer number of Mhz. -#if defined(SYS_CLK_KHZ) && !defined(SYS_CLK_MHZ) && (SYS_CLK_KHZ % 1000 == 0) -#define SYS_CLK_MHZ (SYS_CLK_KHZ / 1000) -#endif - -// For backwards compatibility define USB_CLK_KHZ if the frequency is indeed an integer number of Khz. -#if defined(USB_CLK_HZ) && !defined(USB_CLK_KHZ) && (USB_CLK_HZ % 1000 == 0) -#define USB_CLK_KHZ (USB_CLK_HZ / 1000) -#endif - -// For backwards compatibility define USB_CLK_MHZ if the frequency is indeed an integer number of Mhz. -#if defined(USB_CLK_KHZ) && !defined(USB_CLK_MHZ) && (USB_CLK_KHZ % 1000 == 0) -#define USB_CLK_MHZ (USB_CLK_KHZ / 1000) -#endif - -#define ACCESSCTRL_PASSWORD_BITS _u(0xacce0000) -#define POWMAN_PASSWORD_BITS _u(0x5afe0000) - -#ifdef __riscv -// Note the soft-table dispatch code is between the hard and soft vector -// tables, as it's inlined into the last slot of the hard table: -#if defined(__riscv_c) || defined(__riscv_zca) -// RISC-V with compressed instructions: NOTE that this is dependent on the size of the code in crt0_riscv.S -#define VTABLE_FIRST_IRQ 0x34 -#else -// RISC-V without compressed instructions: -#define VTABLE_FIRST_IRQ 0x48 -#endif -#else -// Armv8-M: -#define VTABLE_FIRST_IRQ 16 -#endif -#define FIRST_USER_IRQ (NUM_IRQS - NUM_USER_IRQS) - -#endif diff --git a/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/accessctrl.h b/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/accessctrl.h deleted file mode 100644 index 2b8c4ca1f4..0000000000 --- a/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/accessctrl.h +++ /dev/null @@ -1,4953 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -// ============================================================================= -// Register block : ACCESSCTRL -// Version : 1 -// Bus type : apb -// Description : Hardware access control registers -// ============================================================================= -#ifndef _HARDWARE_REGS_ACCESSCTRL_H -#define _HARDWARE_REGS_ACCESSCTRL_H -// ============================================================================= -// Register : ACCESSCTRL_LOCK -// Description : Once a LOCK bit is written to 1, ACCESSCTRL silently ignores -// writes from that master. LOCK is writable only by a Secure, -// Privileged processor or debugger. -// -// LOCK bits are only writable when their value is zero. Once set, -// they can never be cleared, except by a full reset of ACCESSCTRL -// -// Setting the LOCK bit does not affect whether an access raises a -// bus error. Unprivileged writes, or writes from the DMA, will -// continue to raise bus errors. All other accesses will continue -// not to. -#define ACCESSCTRL_LOCK_OFFSET _u(0x00000000) -#define ACCESSCTRL_LOCK_BITS _u(0x0000000f) -#define ACCESSCTRL_LOCK_RESET _u(0x00000004) -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_LOCK_DEBUG -#define ACCESSCTRL_LOCK_DEBUG_RESET _u(0x0) -#define ACCESSCTRL_LOCK_DEBUG_BITS _u(0x00000008) -#define ACCESSCTRL_LOCK_DEBUG_MSB _u(3) -#define ACCESSCTRL_LOCK_DEBUG_LSB _u(3) -#define ACCESSCTRL_LOCK_DEBUG_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_LOCK_DMA -#define ACCESSCTRL_LOCK_DMA_RESET _u(0x1) -#define ACCESSCTRL_LOCK_DMA_BITS _u(0x00000004) -#define ACCESSCTRL_LOCK_DMA_MSB _u(2) -#define ACCESSCTRL_LOCK_DMA_LSB _u(2) -#define ACCESSCTRL_LOCK_DMA_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_LOCK_CORE1 -#define ACCESSCTRL_LOCK_CORE1_RESET _u(0x0) -#define ACCESSCTRL_LOCK_CORE1_BITS _u(0x00000002) -#define ACCESSCTRL_LOCK_CORE1_MSB _u(1) -#define ACCESSCTRL_LOCK_CORE1_LSB _u(1) -#define ACCESSCTRL_LOCK_CORE1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_LOCK_CORE0 -#define ACCESSCTRL_LOCK_CORE0_RESET _u(0x0) -#define ACCESSCTRL_LOCK_CORE0_BITS _u(0x00000001) -#define ACCESSCTRL_LOCK_CORE0_MSB _u(0) -#define ACCESSCTRL_LOCK_CORE0_LSB _u(0) -#define ACCESSCTRL_LOCK_CORE0_ACCESS "RW" -// ============================================================================= -// Register : ACCESSCTRL_FORCE_CORE_NS -// Description : Force core 1's bus accesses to always be Non-secure, no matter -// the core's internal state. -// -// Useful for schemes where one core is designated as the Non- -// secure core, since some peripherals may filter individual -// registers internally based on security state but not on master -// ID. -#define ACCESSCTRL_FORCE_CORE_NS_OFFSET _u(0x00000004) -#define ACCESSCTRL_FORCE_CORE_NS_BITS _u(0x00000002) -#define ACCESSCTRL_FORCE_CORE_NS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_FORCE_CORE_NS_CORE1 -#define ACCESSCTRL_FORCE_CORE_NS_CORE1_RESET _u(0x0) -#define ACCESSCTRL_FORCE_CORE_NS_CORE1_BITS _u(0x00000002) -#define ACCESSCTRL_FORCE_CORE_NS_CORE1_MSB _u(1) -#define ACCESSCTRL_FORCE_CORE_NS_CORE1_LSB _u(1) -#define ACCESSCTRL_FORCE_CORE_NS_CORE1_ACCESS "RW" -// ============================================================================= -// Register : ACCESSCTRL_CFGRESET -// Description : Write 1 to reset all ACCESSCTRL configuration, except for the -// LOCK and FORCE_CORE_NS registers. -// -// This bit is used in the RP2350 bootrom to quickly restore -// ACCESSCTRL to a known state during the boot path. -// -// Note that, like all registers in ACCESSCTRL, this register is -// not writable when the writer's corresponding LOCK bit is set, -// therefore a master which has been locked out of ACCESSCTRL can -// not use the CFGRESET register to disturb its contents. -#define ACCESSCTRL_CFGRESET_OFFSET _u(0x00000008) -#define ACCESSCTRL_CFGRESET_BITS _u(0x00000001) -#define ACCESSCTRL_CFGRESET_RESET _u(0x00000000) -#define ACCESSCTRL_CFGRESET_MSB _u(0) -#define ACCESSCTRL_CFGRESET_LSB _u(0) -#define ACCESSCTRL_CFGRESET_ACCESS "SC" -// ============================================================================= -// Register : ACCESSCTRL_GPIO_NSMASK0 -// Description : Control whether GPIO0...31 are accessible to Non-secure code. -// Writable only by a Secure, Privileged processor or debugger. -// -// 0 -> Secure access only -// -// 1 -> Secure + Non-secure access -#define ACCESSCTRL_GPIO_NSMASK0_OFFSET _u(0x0000000c) -#define ACCESSCTRL_GPIO_NSMASK0_BITS _u(0xffffffff) -#define ACCESSCTRL_GPIO_NSMASK0_RESET _u(0x00000000) -#define ACCESSCTRL_GPIO_NSMASK0_MSB _u(31) -#define ACCESSCTRL_GPIO_NSMASK0_LSB _u(0) -#define ACCESSCTRL_GPIO_NSMASK0_ACCESS "RW" -// ============================================================================= -// Register : ACCESSCTRL_GPIO_NSMASK1 -// Description : Control whether GPIO32..47 are accessible to Non-secure code, -// and whether QSPI and USB bitbang are accessible through the -// Non-secure SIO. Writable only by a Secure, Privileged processor -// or debugger. -#define ACCESSCTRL_GPIO_NSMASK1_OFFSET _u(0x00000010) -#define ACCESSCTRL_GPIO_NSMASK1_BITS _u(0xff00ffff) -#define ACCESSCTRL_GPIO_NSMASK1_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_GPIO_NSMASK1_QSPI_SD -#define ACCESSCTRL_GPIO_NSMASK1_QSPI_SD_RESET _u(0x0) -#define ACCESSCTRL_GPIO_NSMASK1_QSPI_SD_BITS _u(0xf0000000) -#define ACCESSCTRL_GPIO_NSMASK1_QSPI_SD_MSB _u(31) -#define ACCESSCTRL_GPIO_NSMASK1_QSPI_SD_LSB _u(28) -#define ACCESSCTRL_GPIO_NSMASK1_QSPI_SD_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_GPIO_NSMASK1_QSPI_CSN -#define ACCESSCTRL_GPIO_NSMASK1_QSPI_CSN_RESET _u(0x0) -#define ACCESSCTRL_GPIO_NSMASK1_QSPI_CSN_BITS _u(0x08000000) -#define ACCESSCTRL_GPIO_NSMASK1_QSPI_CSN_MSB _u(27) -#define ACCESSCTRL_GPIO_NSMASK1_QSPI_CSN_LSB _u(27) -#define ACCESSCTRL_GPIO_NSMASK1_QSPI_CSN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_GPIO_NSMASK1_QSPI_SCK -#define ACCESSCTRL_GPIO_NSMASK1_QSPI_SCK_RESET _u(0x0) -#define ACCESSCTRL_GPIO_NSMASK1_QSPI_SCK_BITS _u(0x04000000) -#define ACCESSCTRL_GPIO_NSMASK1_QSPI_SCK_MSB _u(26) -#define ACCESSCTRL_GPIO_NSMASK1_QSPI_SCK_LSB _u(26) -#define ACCESSCTRL_GPIO_NSMASK1_QSPI_SCK_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_GPIO_NSMASK1_USB_DM -#define ACCESSCTRL_GPIO_NSMASK1_USB_DM_RESET _u(0x0) -#define ACCESSCTRL_GPIO_NSMASK1_USB_DM_BITS _u(0x02000000) -#define ACCESSCTRL_GPIO_NSMASK1_USB_DM_MSB _u(25) -#define ACCESSCTRL_GPIO_NSMASK1_USB_DM_LSB _u(25) -#define ACCESSCTRL_GPIO_NSMASK1_USB_DM_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_GPIO_NSMASK1_USB_DP -#define ACCESSCTRL_GPIO_NSMASK1_USB_DP_RESET _u(0x0) -#define ACCESSCTRL_GPIO_NSMASK1_USB_DP_BITS _u(0x01000000) -#define ACCESSCTRL_GPIO_NSMASK1_USB_DP_MSB _u(24) -#define ACCESSCTRL_GPIO_NSMASK1_USB_DP_LSB _u(24) -#define ACCESSCTRL_GPIO_NSMASK1_USB_DP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_GPIO_NSMASK1_GPIO -#define ACCESSCTRL_GPIO_NSMASK1_GPIO_RESET _u(0x0000) -#define ACCESSCTRL_GPIO_NSMASK1_GPIO_BITS _u(0x0000ffff) -#define ACCESSCTRL_GPIO_NSMASK1_GPIO_MSB _u(15) -#define ACCESSCTRL_GPIO_NSMASK1_GPIO_LSB _u(0) -#define ACCESSCTRL_GPIO_NSMASK1_GPIO_ACCESS "RW" -// ============================================================================= -// Register : ACCESSCTRL_ROM -// Description : Control whether debugger, DMA, core 0 and core 1 can access -// ROM, and at what security/privilege levels they can do so. -// -// Defaults to fully open access. -// -// This register is writable only from a Secure, Privileged -// processor or debugger, with the exception of the NSU bit, which -// becomes Non-secure-Privileged-writable when the NSP bit is set. -#define ACCESSCTRL_ROM_OFFSET _u(0x00000014) -#define ACCESSCTRL_ROM_BITS _u(0x000000ff) -#define ACCESSCTRL_ROM_RESET _u(0x000000ff) -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_ROM_DBG -// Description : If 1, ROM can be accessed by the debugger, at -// security/privilege levels permitted by SP/NSP/SU/NSU in this -// register. -#define ACCESSCTRL_ROM_DBG_RESET _u(0x1) -#define ACCESSCTRL_ROM_DBG_BITS _u(0x00000080) -#define ACCESSCTRL_ROM_DBG_MSB _u(7) -#define ACCESSCTRL_ROM_DBG_LSB _u(7) -#define ACCESSCTRL_ROM_DBG_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_ROM_DMA -// Description : If 1, ROM can be accessed by the DMA, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_ROM_DMA_RESET _u(0x1) -#define ACCESSCTRL_ROM_DMA_BITS _u(0x00000040) -#define ACCESSCTRL_ROM_DMA_MSB _u(6) -#define ACCESSCTRL_ROM_DMA_LSB _u(6) -#define ACCESSCTRL_ROM_DMA_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_ROM_CORE1 -// Description : If 1, ROM can be accessed by core 1, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_ROM_CORE1_RESET _u(0x1) -#define ACCESSCTRL_ROM_CORE1_BITS _u(0x00000020) -#define ACCESSCTRL_ROM_CORE1_MSB _u(5) -#define ACCESSCTRL_ROM_CORE1_LSB _u(5) -#define ACCESSCTRL_ROM_CORE1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_ROM_CORE0 -// Description : If 1, ROM can be accessed by core 0, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_ROM_CORE0_RESET _u(0x1) -#define ACCESSCTRL_ROM_CORE0_BITS _u(0x00000010) -#define ACCESSCTRL_ROM_CORE0_MSB _u(4) -#define ACCESSCTRL_ROM_CORE0_LSB _u(4) -#define ACCESSCTRL_ROM_CORE0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_ROM_SP -// Description : If 1, ROM can be accessed from a Secure, Privileged context. -#define ACCESSCTRL_ROM_SP_RESET _u(0x1) -#define ACCESSCTRL_ROM_SP_BITS _u(0x00000008) -#define ACCESSCTRL_ROM_SP_MSB _u(3) -#define ACCESSCTRL_ROM_SP_LSB _u(3) -#define ACCESSCTRL_ROM_SP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_ROM_SU -// Description : If 1, and SP is also set, ROM can be accessed from a Secure, -// Unprivileged context. -#define ACCESSCTRL_ROM_SU_RESET _u(0x1) -#define ACCESSCTRL_ROM_SU_BITS _u(0x00000004) -#define ACCESSCTRL_ROM_SU_MSB _u(2) -#define ACCESSCTRL_ROM_SU_LSB _u(2) -#define ACCESSCTRL_ROM_SU_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_ROM_NSP -// Description : If 1, ROM can be accessed from a Non-secure, Privileged -// context. -#define ACCESSCTRL_ROM_NSP_RESET _u(0x1) -#define ACCESSCTRL_ROM_NSP_BITS _u(0x00000002) -#define ACCESSCTRL_ROM_NSP_MSB _u(1) -#define ACCESSCTRL_ROM_NSP_LSB _u(1) -#define ACCESSCTRL_ROM_NSP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_ROM_NSU -// Description : If 1, and NSP is also set, ROM can be accessed from a Non- -// secure, Unprivileged context. -// -// This bit is writable from a Non-secure, Privileged context, if -// and only if the NSP bit is set. -#define ACCESSCTRL_ROM_NSU_RESET _u(0x1) -#define ACCESSCTRL_ROM_NSU_BITS _u(0x00000001) -#define ACCESSCTRL_ROM_NSU_MSB _u(0) -#define ACCESSCTRL_ROM_NSU_LSB _u(0) -#define ACCESSCTRL_ROM_NSU_ACCESS "RW" -// ============================================================================= -// Register : ACCESSCTRL_XIP_MAIN -// Description : Control whether debugger, DMA, core 0 and core 1 can access -// XIP_MAIN, and at what security/privilege levels they can do so. -// -// Defaults to fully open access. -// -// This register is writable only from a Secure, Privileged -// processor or debugger, with the exception of the NSU bit, which -// becomes Non-secure-Privileged-writable when the NSP bit is set. -#define ACCESSCTRL_XIP_MAIN_OFFSET _u(0x00000018) -#define ACCESSCTRL_XIP_MAIN_BITS _u(0x000000ff) -#define ACCESSCTRL_XIP_MAIN_RESET _u(0x000000ff) -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_XIP_MAIN_DBG -// Description : If 1, XIP_MAIN can be accessed by the debugger, at -// security/privilege levels permitted by SP/NSP/SU/NSU in this -// register. -#define ACCESSCTRL_XIP_MAIN_DBG_RESET _u(0x1) -#define ACCESSCTRL_XIP_MAIN_DBG_BITS _u(0x00000080) -#define ACCESSCTRL_XIP_MAIN_DBG_MSB _u(7) -#define ACCESSCTRL_XIP_MAIN_DBG_LSB _u(7) -#define ACCESSCTRL_XIP_MAIN_DBG_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_XIP_MAIN_DMA -// Description : If 1, XIP_MAIN can be accessed by the DMA, at -// security/privilege levels permitted by SP/NSP/SU/NSU in this -// register. -#define ACCESSCTRL_XIP_MAIN_DMA_RESET _u(0x1) -#define ACCESSCTRL_XIP_MAIN_DMA_BITS _u(0x00000040) -#define ACCESSCTRL_XIP_MAIN_DMA_MSB _u(6) -#define ACCESSCTRL_XIP_MAIN_DMA_LSB _u(6) -#define ACCESSCTRL_XIP_MAIN_DMA_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_XIP_MAIN_CORE1 -// Description : If 1, XIP_MAIN can be accessed by core 1, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_XIP_MAIN_CORE1_RESET _u(0x1) -#define ACCESSCTRL_XIP_MAIN_CORE1_BITS _u(0x00000020) -#define ACCESSCTRL_XIP_MAIN_CORE1_MSB _u(5) -#define ACCESSCTRL_XIP_MAIN_CORE1_LSB _u(5) -#define ACCESSCTRL_XIP_MAIN_CORE1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_XIP_MAIN_CORE0 -// Description : If 1, XIP_MAIN can be accessed by core 0, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_XIP_MAIN_CORE0_RESET _u(0x1) -#define ACCESSCTRL_XIP_MAIN_CORE0_BITS _u(0x00000010) -#define ACCESSCTRL_XIP_MAIN_CORE0_MSB _u(4) -#define ACCESSCTRL_XIP_MAIN_CORE0_LSB _u(4) -#define ACCESSCTRL_XIP_MAIN_CORE0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_XIP_MAIN_SP -// Description : If 1, XIP_MAIN can be accessed from a Secure, Privileged -// context. -#define ACCESSCTRL_XIP_MAIN_SP_RESET _u(0x1) -#define ACCESSCTRL_XIP_MAIN_SP_BITS _u(0x00000008) -#define ACCESSCTRL_XIP_MAIN_SP_MSB _u(3) -#define ACCESSCTRL_XIP_MAIN_SP_LSB _u(3) -#define ACCESSCTRL_XIP_MAIN_SP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_XIP_MAIN_SU -// Description : If 1, and SP is also set, XIP_MAIN can be accessed from a -// Secure, Unprivileged context. -#define ACCESSCTRL_XIP_MAIN_SU_RESET _u(0x1) -#define ACCESSCTRL_XIP_MAIN_SU_BITS _u(0x00000004) -#define ACCESSCTRL_XIP_MAIN_SU_MSB _u(2) -#define ACCESSCTRL_XIP_MAIN_SU_LSB _u(2) -#define ACCESSCTRL_XIP_MAIN_SU_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_XIP_MAIN_NSP -// Description : If 1, XIP_MAIN can be accessed from a Non-secure, Privileged -// context. -#define ACCESSCTRL_XIP_MAIN_NSP_RESET _u(0x1) -#define ACCESSCTRL_XIP_MAIN_NSP_BITS _u(0x00000002) -#define ACCESSCTRL_XIP_MAIN_NSP_MSB _u(1) -#define ACCESSCTRL_XIP_MAIN_NSP_LSB _u(1) -#define ACCESSCTRL_XIP_MAIN_NSP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_XIP_MAIN_NSU -// Description : If 1, and NSP is also set, XIP_MAIN can be accessed from a Non- -// secure, Unprivileged context. -// -// This bit is writable from a Non-secure, Privileged context, if -// and only if the NSP bit is set. -#define ACCESSCTRL_XIP_MAIN_NSU_RESET _u(0x1) -#define ACCESSCTRL_XIP_MAIN_NSU_BITS _u(0x00000001) -#define ACCESSCTRL_XIP_MAIN_NSU_MSB _u(0) -#define ACCESSCTRL_XIP_MAIN_NSU_LSB _u(0) -#define ACCESSCTRL_XIP_MAIN_NSU_ACCESS "RW" -// ============================================================================= -// Register : ACCESSCTRL_SRAM0 -// Description : Control whether debugger, DMA, core 0 and core 1 can access -// SRAM0, and at what security/privilege levels they can do so. -// -// Defaults to fully open access. -// -// This register is writable only from a Secure, Privileged -// processor or debugger, with the exception of the NSU bit, which -// becomes Non-secure-Privileged-writable when the NSP bit is set. -#define ACCESSCTRL_SRAM0_OFFSET _u(0x0000001c) -#define ACCESSCTRL_SRAM0_BITS _u(0x000000ff) -#define ACCESSCTRL_SRAM0_RESET _u(0x000000ff) -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_SRAM0_DBG -// Description : If 1, SRAM0 can be accessed by the debugger, at -// security/privilege levels permitted by SP/NSP/SU/NSU in this -// register. -#define ACCESSCTRL_SRAM0_DBG_RESET _u(0x1) -#define ACCESSCTRL_SRAM0_DBG_BITS _u(0x00000080) -#define ACCESSCTRL_SRAM0_DBG_MSB _u(7) -#define ACCESSCTRL_SRAM0_DBG_LSB _u(7) -#define ACCESSCTRL_SRAM0_DBG_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_SRAM0_DMA -// Description : If 1, SRAM0 can be accessed by the DMA, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_SRAM0_DMA_RESET _u(0x1) -#define ACCESSCTRL_SRAM0_DMA_BITS _u(0x00000040) -#define ACCESSCTRL_SRAM0_DMA_MSB _u(6) -#define ACCESSCTRL_SRAM0_DMA_LSB _u(6) -#define ACCESSCTRL_SRAM0_DMA_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_SRAM0_CORE1 -// Description : If 1, SRAM0 can be accessed by core 1, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_SRAM0_CORE1_RESET _u(0x1) -#define ACCESSCTRL_SRAM0_CORE1_BITS _u(0x00000020) -#define ACCESSCTRL_SRAM0_CORE1_MSB _u(5) -#define ACCESSCTRL_SRAM0_CORE1_LSB _u(5) -#define ACCESSCTRL_SRAM0_CORE1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_SRAM0_CORE0 -// Description : If 1, SRAM0 can be accessed by core 0, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_SRAM0_CORE0_RESET _u(0x1) -#define ACCESSCTRL_SRAM0_CORE0_BITS _u(0x00000010) -#define ACCESSCTRL_SRAM0_CORE0_MSB _u(4) -#define ACCESSCTRL_SRAM0_CORE0_LSB _u(4) -#define ACCESSCTRL_SRAM0_CORE0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_SRAM0_SP -// Description : If 1, SRAM0 can be accessed from a Secure, Privileged context. -#define ACCESSCTRL_SRAM0_SP_RESET _u(0x1) -#define ACCESSCTRL_SRAM0_SP_BITS _u(0x00000008) -#define ACCESSCTRL_SRAM0_SP_MSB _u(3) -#define ACCESSCTRL_SRAM0_SP_LSB _u(3) -#define ACCESSCTRL_SRAM0_SP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_SRAM0_SU -// Description : If 1, and SP is also set, SRAM0 can be accessed from a Secure, -// Unprivileged context. -#define ACCESSCTRL_SRAM0_SU_RESET _u(0x1) -#define ACCESSCTRL_SRAM0_SU_BITS _u(0x00000004) -#define ACCESSCTRL_SRAM0_SU_MSB _u(2) -#define ACCESSCTRL_SRAM0_SU_LSB _u(2) -#define ACCESSCTRL_SRAM0_SU_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_SRAM0_NSP -// Description : If 1, SRAM0 can be accessed from a Non-secure, Privileged -// context. -#define ACCESSCTRL_SRAM0_NSP_RESET _u(0x1) -#define ACCESSCTRL_SRAM0_NSP_BITS _u(0x00000002) -#define ACCESSCTRL_SRAM0_NSP_MSB _u(1) -#define ACCESSCTRL_SRAM0_NSP_LSB _u(1) -#define ACCESSCTRL_SRAM0_NSP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_SRAM0_NSU -// Description : If 1, and NSP is also set, SRAM0 can be accessed from a Non- -// secure, Unprivileged context. -// -// This bit is writable from a Non-secure, Privileged context, if -// and only if the NSP bit is set. -#define ACCESSCTRL_SRAM0_NSU_RESET _u(0x1) -#define ACCESSCTRL_SRAM0_NSU_BITS _u(0x00000001) -#define ACCESSCTRL_SRAM0_NSU_MSB _u(0) -#define ACCESSCTRL_SRAM0_NSU_LSB _u(0) -#define ACCESSCTRL_SRAM0_NSU_ACCESS "RW" -// ============================================================================= -// Register : ACCESSCTRL_SRAM1 -// Description : Control whether debugger, DMA, core 0 and core 1 can access -// SRAM1, and at what security/privilege levels they can do so. -// -// Defaults to fully open access. -// -// This register is writable only from a Secure, Privileged -// processor or debugger, with the exception of the NSU bit, which -// becomes Non-secure-Privileged-writable when the NSP bit is set. -#define ACCESSCTRL_SRAM1_OFFSET _u(0x00000020) -#define ACCESSCTRL_SRAM1_BITS _u(0x000000ff) -#define ACCESSCTRL_SRAM1_RESET _u(0x000000ff) -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_SRAM1_DBG -// Description : If 1, SRAM1 can be accessed by the debugger, at -// security/privilege levels permitted by SP/NSP/SU/NSU in this -// register. -#define ACCESSCTRL_SRAM1_DBG_RESET _u(0x1) -#define ACCESSCTRL_SRAM1_DBG_BITS _u(0x00000080) -#define ACCESSCTRL_SRAM1_DBG_MSB _u(7) -#define ACCESSCTRL_SRAM1_DBG_LSB _u(7) -#define ACCESSCTRL_SRAM1_DBG_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_SRAM1_DMA -// Description : If 1, SRAM1 can be accessed by the DMA, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_SRAM1_DMA_RESET _u(0x1) -#define ACCESSCTRL_SRAM1_DMA_BITS _u(0x00000040) -#define ACCESSCTRL_SRAM1_DMA_MSB _u(6) -#define ACCESSCTRL_SRAM1_DMA_LSB _u(6) -#define ACCESSCTRL_SRAM1_DMA_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_SRAM1_CORE1 -// Description : If 1, SRAM1 can be accessed by core 1, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_SRAM1_CORE1_RESET _u(0x1) -#define ACCESSCTRL_SRAM1_CORE1_BITS _u(0x00000020) -#define ACCESSCTRL_SRAM1_CORE1_MSB _u(5) -#define ACCESSCTRL_SRAM1_CORE1_LSB _u(5) -#define ACCESSCTRL_SRAM1_CORE1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_SRAM1_CORE0 -// Description : If 1, SRAM1 can be accessed by core 0, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_SRAM1_CORE0_RESET _u(0x1) -#define ACCESSCTRL_SRAM1_CORE0_BITS _u(0x00000010) -#define ACCESSCTRL_SRAM1_CORE0_MSB _u(4) -#define ACCESSCTRL_SRAM1_CORE0_LSB _u(4) -#define ACCESSCTRL_SRAM1_CORE0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_SRAM1_SP -// Description : If 1, SRAM1 can be accessed from a Secure, Privileged context. -#define ACCESSCTRL_SRAM1_SP_RESET _u(0x1) -#define ACCESSCTRL_SRAM1_SP_BITS _u(0x00000008) -#define ACCESSCTRL_SRAM1_SP_MSB _u(3) -#define ACCESSCTRL_SRAM1_SP_LSB _u(3) -#define ACCESSCTRL_SRAM1_SP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_SRAM1_SU -// Description : If 1, and SP is also set, SRAM1 can be accessed from a Secure, -// Unprivileged context. -#define ACCESSCTRL_SRAM1_SU_RESET _u(0x1) -#define ACCESSCTRL_SRAM1_SU_BITS _u(0x00000004) -#define ACCESSCTRL_SRAM1_SU_MSB _u(2) -#define ACCESSCTRL_SRAM1_SU_LSB _u(2) -#define ACCESSCTRL_SRAM1_SU_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_SRAM1_NSP -// Description : If 1, SRAM1 can be accessed from a Non-secure, Privileged -// context. -#define ACCESSCTRL_SRAM1_NSP_RESET _u(0x1) -#define ACCESSCTRL_SRAM1_NSP_BITS _u(0x00000002) -#define ACCESSCTRL_SRAM1_NSP_MSB _u(1) -#define ACCESSCTRL_SRAM1_NSP_LSB _u(1) -#define ACCESSCTRL_SRAM1_NSP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_SRAM1_NSU -// Description : If 1, and NSP is also set, SRAM1 can be accessed from a Non- -// secure, Unprivileged context. -// -// This bit is writable from a Non-secure, Privileged context, if -// and only if the NSP bit is set. -#define ACCESSCTRL_SRAM1_NSU_RESET _u(0x1) -#define ACCESSCTRL_SRAM1_NSU_BITS _u(0x00000001) -#define ACCESSCTRL_SRAM1_NSU_MSB _u(0) -#define ACCESSCTRL_SRAM1_NSU_LSB _u(0) -#define ACCESSCTRL_SRAM1_NSU_ACCESS "RW" -// ============================================================================= -// Register : ACCESSCTRL_SRAM2 -// Description : Control whether debugger, DMA, core 0 and core 1 can access -// SRAM2, and at what security/privilege levels they can do so. -// -// Defaults to fully open access. -// -// This register is writable only from a Secure, Privileged -// processor or debugger, with the exception of the NSU bit, which -// becomes Non-secure-Privileged-writable when the NSP bit is set. -#define ACCESSCTRL_SRAM2_OFFSET _u(0x00000024) -#define ACCESSCTRL_SRAM2_BITS _u(0x000000ff) -#define ACCESSCTRL_SRAM2_RESET _u(0x000000ff) -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_SRAM2_DBG -// Description : If 1, SRAM2 can be accessed by the debugger, at -// security/privilege levels permitted by SP/NSP/SU/NSU in this -// register. -#define ACCESSCTRL_SRAM2_DBG_RESET _u(0x1) -#define ACCESSCTRL_SRAM2_DBG_BITS _u(0x00000080) -#define ACCESSCTRL_SRAM2_DBG_MSB _u(7) -#define ACCESSCTRL_SRAM2_DBG_LSB _u(7) -#define ACCESSCTRL_SRAM2_DBG_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_SRAM2_DMA -// Description : If 1, SRAM2 can be accessed by the DMA, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_SRAM2_DMA_RESET _u(0x1) -#define ACCESSCTRL_SRAM2_DMA_BITS _u(0x00000040) -#define ACCESSCTRL_SRAM2_DMA_MSB _u(6) -#define ACCESSCTRL_SRAM2_DMA_LSB _u(6) -#define ACCESSCTRL_SRAM2_DMA_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_SRAM2_CORE1 -// Description : If 1, SRAM2 can be accessed by core 1, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_SRAM2_CORE1_RESET _u(0x1) -#define ACCESSCTRL_SRAM2_CORE1_BITS _u(0x00000020) -#define ACCESSCTRL_SRAM2_CORE1_MSB _u(5) -#define ACCESSCTRL_SRAM2_CORE1_LSB _u(5) -#define ACCESSCTRL_SRAM2_CORE1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_SRAM2_CORE0 -// Description : If 1, SRAM2 can be accessed by core 0, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_SRAM2_CORE0_RESET _u(0x1) -#define ACCESSCTRL_SRAM2_CORE0_BITS _u(0x00000010) -#define ACCESSCTRL_SRAM2_CORE0_MSB _u(4) -#define ACCESSCTRL_SRAM2_CORE0_LSB _u(4) -#define ACCESSCTRL_SRAM2_CORE0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_SRAM2_SP -// Description : If 1, SRAM2 can be accessed from a Secure, Privileged context. -#define ACCESSCTRL_SRAM2_SP_RESET _u(0x1) -#define ACCESSCTRL_SRAM2_SP_BITS _u(0x00000008) -#define ACCESSCTRL_SRAM2_SP_MSB _u(3) -#define ACCESSCTRL_SRAM2_SP_LSB _u(3) -#define ACCESSCTRL_SRAM2_SP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_SRAM2_SU -// Description : If 1, and SP is also set, SRAM2 can be accessed from a Secure, -// Unprivileged context. -#define ACCESSCTRL_SRAM2_SU_RESET _u(0x1) -#define ACCESSCTRL_SRAM2_SU_BITS _u(0x00000004) -#define ACCESSCTRL_SRAM2_SU_MSB _u(2) -#define ACCESSCTRL_SRAM2_SU_LSB _u(2) -#define ACCESSCTRL_SRAM2_SU_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_SRAM2_NSP -// Description : If 1, SRAM2 can be accessed from a Non-secure, Privileged -// context. -#define ACCESSCTRL_SRAM2_NSP_RESET _u(0x1) -#define ACCESSCTRL_SRAM2_NSP_BITS _u(0x00000002) -#define ACCESSCTRL_SRAM2_NSP_MSB _u(1) -#define ACCESSCTRL_SRAM2_NSP_LSB _u(1) -#define ACCESSCTRL_SRAM2_NSP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_SRAM2_NSU -// Description : If 1, and NSP is also set, SRAM2 can be accessed from a Non- -// secure, Unprivileged context. -// -// This bit is writable from a Non-secure, Privileged context, if -// and only if the NSP bit is set. -#define ACCESSCTRL_SRAM2_NSU_RESET _u(0x1) -#define ACCESSCTRL_SRAM2_NSU_BITS _u(0x00000001) -#define ACCESSCTRL_SRAM2_NSU_MSB _u(0) -#define ACCESSCTRL_SRAM2_NSU_LSB _u(0) -#define ACCESSCTRL_SRAM2_NSU_ACCESS "RW" -// ============================================================================= -// Register : ACCESSCTRL_SRAM3 -// Description : Control whether debugger, DMA, core 0 and core 1 can access -// SRAM3, and at what security/privilege levels they can do so. -// -// Defaults to fully open access. -// -// This register is writable only from a Secure, Privileged -// processor or debugger, with the exception of the NSU bit, which -// becomes Non-secure-Privileged-writable when the NSP bit is set. -#define ACCESSCTRL_SRAM3_OFFSET _u(0x00000028) -#define ACCESSCTRL_SRAM3_BITS _u(0x000000ff) -#define ACCESSCTRL_SRAM3_RESET _u(0x000000ff) -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_SRAM3_DBG -// Description : If 1, SRAM3 can be accessed by the debugger, at -// security/privilege levels permitted by SP/NSP/SU/NSU in this -// register. -#define ACCESSCTRL_SRAM3_DBG_RESET _u(0x1) -#define ACCESSCTRL_SRAM3_DBG_BITS _u(0x00000080) -#define ACCESSCTRL_SRAM3_DBG_MSB _u(7) -#define ACCESSCTRL_SRAM3_DBG_LSB _u(7) -#define ACCESSCTRL_SRAM3_DBG_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_SRAM3_DMA -// Description : If 1, SRAM3 can be accessed by the DMA, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_SRAM3_DMA_RESET _u(0x1) -#define ACCESSCTRL_SRAM3_DMA_BITS _u(0x00000040) -#define ACCESSCTRL_SRAM3_DMA_MSB _u(6) -#define ACCESSCTRL_SRAM3_DMA_LSB _u(6) -#define ACCESSCTRL_SRAM3_DMA_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_SRAM3_CORE1 -// Description : If 1, SRAM3 can be accessed by core 1, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_SRAM3_CORE1_RESET _u(0x1) -#define ACCESSCTRL_SRAM3_CORE1_BITS _u(0x00000020) -#define ACCESSCTRL_SRAM3_CORE1_MSB _u(5) -#define ACCESSCTRL_SRAM3_CORE1_LSB _u(5) -#define ACCESSCTRL_SRAM3_CORE1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_SRAM3_CORE0 -// Description : If 1, SRAM3 can be accessed by core 0, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_SRAM3_CORE0_RESET _u(0x1) -#define ACCESSCTRL_SRAM3_CORE0_BITS _u(0x00000010) -#define ACCESSCTRL_SRAM3_CORE0_MSB _u(4) -#define ACCESSCTRL_SRAM3_CORE0_LSB _u(4) -#define ACCESSCTRL_SRAM3_CORE0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_SRAM3_SP -// Description : If 1, SRAM3 can be accessed from a Secure, Privileged context. -#define ACCESSCTRL_SRAM3_SP_RESET _u(0x1) -#define ACCESSCTRL_SRAM3_SP_BITS _u(0x00000008) -#define ACCESSCTRL_SRAM3_SP_MSB _u(3) -#define ACCESSCTRL_SRAM3_SP_LSB _u(3) -#define ACCESSCTRL_SRAM3_SP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_SRAM3_SU -// Description : If 1, and SP is also set, SRAM3 can be accessed from a Secure, -// Unprivileged context. -#define ACCESSCTRL_SRAM3_SU_RESET _u(0x1) -#define ACCESSCTRL_SRAM3_SU_BITS _u(0x00000004) -#define ACCESSCTRL_SRAM3_SU_MSB _u(2) -#define ACCESSCTRL_SRAM3_SU_LSB _u(2) -#define ACCESSCTRL_SRAM3_SU_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_SRAM3_NSP -// Description : If 1, SRAM3 can be accessed from a Non-secure, Privileged -// context. -#define ACCESSCTRL_SRAM3_NSP_RESET _u(0x1) -#define ACCESSCTRL_SRAM3_NSP_BITS _u(0x00000002) -#define ACCESSCTRL_SRAM3_NSP_MSB _u(1) -#define ACCESSCTRL_SRAM3_NSP_LSB _u(1) -#define ACCESSCTRL_SRAM3_NSP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_SRAM3_NSU -// Description : If 1, and NSP is also set, SRAM3 can be accessed from a Non- -// secure, Unprivileged context. -// -// This bit is writable from a Non-secure, Privileged context, if -// and only if the NSP bit is set. -#define ACCESSCTRL_SRAM3_NSU_RESET _u(0x1) -#define ACCESSCTRL_SRAM3_NSU_BITS _u(0x00000001) -#define ACCESSCTRL_SRAM3_NSU_MSB _u(0) -#define ACCESSCTRL_SRAM3_NSU_LSB _u(0) -#define ACCESSCTRL_SRAM3_NSU_ACCESS "RW" -// ============================================================================= -// Register : ACCESSCTRL_SRAM4 -// Description : Control whether debugger, DMA, core 0 and core 1 can access -// SRAM4, and at what security/privilege levels they can do so. -// -// Defaults to fully open access. -// -// This register is writable only from a Secure, Privileged -// processor or debugger, with the exception of the NSU bit, which -// becomes Non-secure-Privileged-writable when the NSP bit is set. -#define ACCESSCTRL_SRAM4_OFFSET _u(0x0000002c) -#define ACCESSCTRL_SRAM4_BITS _u(0x000000ff) -#define ACCESSCTRL_SRAM4_RESET _u(0x000000ff) -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_SRAM4_DBG -// Description : If 1, SRAM4 can be accessed by the debugger, at -// security/privilege levels permitted by SP/NSP/SU/NSU in this -// register. -#define ACCESSCTRL_SRAM4_DBG_RESET _u(0x1) -#define ACCESSCTRL_SRAM4_DBG_BITS _u(0x00000080) -#define ACCESSCTRL_SRAM4_DBG_MSB _u(7) -#define ACCESSCTRL_SRAM4_DBG_LSB _u(7) -#define ACCESSCTRL_SRAM4_DBG_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_SRAM4_DMA -// Description : If 1, SRAM4 can be accessed by the DMA, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_SRAM4_DMA_RESET _u(0x1) -#define ACCESSCTRL_SRAM4_DMA_BITS _u(0x00000040) -#define ACCESSCTRL_SRAM4_DMA_MSB _u(6) -#define ACCESSCTRL_SRAM4_DMA_LSB _u(6) -#define ACCESSCTRL_SRAM4_DMA_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_SRAM4_CORE1 -// Description : If 1, SRAM4 can be accessed by core 1, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_SRAM4_CORE1_RESET _u(0x1) -#define ACCESSCTRL_SRAM4_CORE1_BITS _u(0x00000020) -#define ACCESSCTRL_SRAM4_CORE1_MSB _u(5) -#define ACCESSCTRL_SRAM4_CORE1_LSB _u(5) -#define ACCESSCTRL_SRAM4_CORE1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_SRAM4_CORE0 -// Description : If 1, SRAM4 can be accessed by core 0, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_SRAM4_CORE0_RESET _u(0x1) -#define ACCESSCTRL_SRAM4_CORE0_BITS _u(0x00000010) -#define ACCESSCTRL_SRAM4_CORE0_MSB _u(4) -#define ACCESSCTRL_SRAM4_CORE0_LSB _u(4) -#define ACCESSCTRL_SRAM4_CORE0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_SRAM4_SP -// Description : If 1, SRAM4 can be accessed from a Secure, Privileged context. -#define ACCESSCTRL_SRAM4_SP_RESET _u(0x1) -#define ACCESSCTRL_SRAM4_SP_BITS _u(0x00000008) -#define ACCESSCTRL_SRAM4_SP_MSB _u(3) -#define ACCESSCTRL_SRAM4_SP_LSB _u(3) -#define ACCESSCTRL_SRAM4_SP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_SRAM4_SU -// Description : If 1, and SP is also set, SRAM4 can be accessed from a Secure, -// Unprivileged context. -#define ACCESSCTRL_SRAM4_SU_RESET _u(0x1) -#define ACCESSCTRL_SRAM4_SU_BITS _u(0x00000004) -#define ACCESSCTRL_SRAM4_SU_MSB _u(2) -#define ACCESSCTRL_SRAM4_SU_LSB _u(2) -#define ACCESSCTRL_SRAM4_SU_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_SRAM4_NSP -// Description : If 1, SRAM4 can be accessed from a Non-secure, Privileged -// context. -#define ACCESSCTRL_SRAM4_NSP_RESET _u(0x1) -#define ACCESSCTRL_SRAM4_NSP_BITS _u(0x00000002) -#define ACCESSCTRL_SRAM4_NSP_MSB _u(1) -#define ACCESSCTRL_SRAM4_NSP_LSB _u(1) -#define ACCESSCTRL_SRAM4_NSP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_SRAM4_NSU -// Description : If 1, and NSP is also set, SRAM4 can be accessed from a Non- -// secure, Unprivileged context. -// -// This bit is writable from a Non-secure, Privileged context, if -// and only if the NSP bit is set. -#define ACCESSCTRL_SRAM4_NSU_RESET _u(0x1) -#define ACCESSCTRL_SRAM4_NSU_BITS _u(0x00000001) -#define ACCESSCTRL_SRAM4_NSU_MSB _u(0) -#define ACCESSCTRL_SRAM4_NSU_LSB _u(0) -#define ACCESSCTRL_SRAM4_NSU_ACCESS "RW" -// ============================================================================= -// Register : ACCESSCTRL_SRAM5 -// Description : Control whether debugger, DMA, core 0 and core 1 can access -// SRAM5, and at what security/privilege levels they can do so. -// -// Defaults to fully open access. -// -// This register is writable only from a Secure, Privileged -// processor or debugger, with the exception of the NSU bit, which -// becomes Non-secure-Privileged-writable when the NSP bit is set. -#define ACCESSCTRL_SRAM5_OFFSET _u(0x00000030) -#define ACCESSCTRL_SRAM5_BITS _u(0x000000ff) -#define ACCESSCTRL_SRAM5_RESET _u(0x000000ff) -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_SRAM5_DBG -// Description : If 1, SRAM5 can be accessed by the debugger, at -// security/privilege levels permitted by SP/NSP/SU/NSU in this -// register. -#define ACCESSCTRL_SRAM5_DBG_RESET _u(0x1) -#define ACCESSCTRL_SRAM5_DBG_BITS _u(0x00000080) -#define ACCESSCTRL_SRAM5_DBG_MSB _u(7) -#define ACCESSCTRL_SRAM5_DBG_LSB _u(7) -#define ACCESSCTRL_SRAM5_DBG_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_SRAM5_DMA -// Description : If 1, SRAM5 can be accessed by the DMA, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_SRAM5_DMA_RESET _u(0x1) -#define ACCESSCTRL_SRAM5_DMA_BITS _u(0x00000040) -#define ACCESSCTRL_SRAM5_DMA_MSB _u(6) -#define ACCESSCTRL_SRAM5_DMA_LSB _u(6) -#define ACCESSCTRL_SRAM5_DMA_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_SRAM5_CORE1 -// Description : If 1, SRAM5 can be accessed by core 1, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_SRAM5_CORE1_RESET _u(0x1) -#define ACCESSCTRL_SRAM5_CORE1_BITS _u(0x00000020) -#define ACCESSCTRL_SRAM5_CORE1_MSB _u(5) -#define ACCESSCTRL_SRAM5_CORE1_LSB _u(5) -#define ACCESSCTRL_SRAM5_CORE1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_SRAM5_CORE0 -// Description : If 1, SRAM5 can be accessed by core 0, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_SRAM5_CORE0_RESET _u(0x1) -#define ACCESSCTRL_SRAM5_CORE0_BITS _u(0x00000010) -#define ACCESSCTRL_SRAM5_CORE0_MSB _u(4) -#define ACCESSCTRL_SRAM5_CORE0_LSB _u(4) -#define ACCESSCTRL_SRAM5_CORE0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_SRAM5_SP -// Description : If 1, SRAM5 can be accessed from a Secure, Privileged context. -#define ACCESSCTRL_SRAM5_SP_RESET _u(0x1) -#define ACCESSCTRL_SRAM5_SP_BITS _u(0x00000008) -#define ACCESSCTRL_SRAM5_SP_MSB _u(3) -#define ACCESSCTRL_SRAM5_SP_LSB _u(3) -#define ACCESSCTRL_SRAM5_SP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_SRAM5_SU -// Description : If 1, and SP is also set, SRAM5 can be accessed from a Secure, -// Unprivileged context. -#define ACCESSCTRL_SRAM5_SU_RESET _u(0x1) -#define ACCESSCTRL_SRAM5_SU_BITS _u(0x00000004) -#define ACCESSCTRL_SRAM5_SU_MSB _u(2) -#define ACCESSCTRL_SRAM5_SU_LSB _u(2) -#define ACCESSCTRL_SRAM5_SU_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_SRAM5_NSP -// Description : If 1, SRAM5 can be accessed from a Non-secure, Privileged -// context. -#define ACCESSCTRL_SRAM5_NSP_RESET _u(0x1) -#define ACCESSCTRL_SRAM5_NSP_BITS _u(0x00000002) -#define ACCESSCTRL_SRAM5_NSP_MSB _u(1) -#define ACCESSCTRL_SRAM5_NSP_LSB _u(1) -#define ACCESSCTRL_SRAM5_NSP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_SRAM5_NSU -// Description : If 1, and NSP is also set, SRAM5 can be accessed from a Non- -// secure, Unprivileged context. -// -// This bit is writable from a Non-secure, Privileged context, if -// and only if the NSP bit is set. -#define ACCESSCTRL_SRAM5_NSU_RESET _u(0x1) -#define ACCESSCTRL_SRAM5_NSU_BITS _u(0x00000001) -#define ACCESSCTRL_SRAM5_NSU_MSB _u(0) -#define ACCESSCTRL_SRAM5_NSU_LSB _u(0) -#define ACCESSCTRL_SRAM5_NSU_ACCESS "RW" -// ============================================================================= -// Register : ACCESSCTRL_SRAM6 -// Description : Control whether debugger, DMA, core 0 and core 1 can access -// SRAM6, and at what security/privilege levels they can do so. -// -// Defaults to fully open access. -// -// This register is writable only from a Secure, Privileged -// processor or debugger, with the exception of the NSU bit, which -// becomes Non-secure-Privileged-writable when the NSP bit is set. -#define ACCESSCTRL_SRAM6_OFFSET _u(0x00000034) -#define ACCESSCTRL_SRAM6_BITS _u(0x000000ff) -#define ACCESSCTRL_SRAM6_RESET _u(0x000000ff) -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_SRAM6_DBG -// Description : If 1, SRAM6 can be accessed by the debugger, at -// security/privilege levels permitted by SP/NSP/SU/NSU in this -// register. -#define ACCESSCTRL_SRAM6_DBG_RESET _u(0x1) -#define ACCESSCTRL_SRAM6_DBG_BITS _u(0x00000080) -#define ACCESSCTRL_SRAM6_DBG_MSB _u(7) -#define ACCESSCTRL_SRAM6_DBG_LSB _u(7) -#define ACCESSCTRL_SRAM6_DBG_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_SRAM6_DMA -// Description : If 1, SRAM6 can be accessed by the DMA, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_SRAM6_DMA_RESET _u(0x1) -#define ACCESSCTRL_SRAM6_DMA_BITS _u(0x00000040) -#define ACCESSCTRL_SRAM6_DMA_MSB _u(6) -#define ACCESSCTRL_SRAM6_DMA_LSB _u(6) -#define ACCESSCTRL_SRAM6_DMA_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_SRAM6_CORE1 -// Description : If 1, SRAM6 can be accessed by core 1, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_SRAM6_CORE1_RESET _u(0x1) -#define ACCESSCTRL_SRAM6_CORE1_BITS _u(0x00000020) -#define ACCESSCTRL_SRAM6_CORE1_MSB _u(5) -#define ACCESSCTRL_SRAM6_CORE1_LSB _u(5) -#define ACCESSCTRL_SRAM6_CORE1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_SRAM6_CORE0 -// Description : If 1, SRAM6 can be accessed by core 0, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_SRAM6_CORE0_RESET _u(0x1) -#define ACCESSCTRL_SRAM6_CORE0_BITS _u(0x00000010) -#define ACCESSCTRL_SRAM6_CORE0_MSB _u(4) -#define ACCESSCTRL_SRAM6_CORE0_LSB _u(4) -#define ACCESSCTRL_SRAM6_CORE0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_SRAM6_SP -// Description : If 1, SRAM6 can be accessed from a Secure, Privileged context. -#define ACCESSCTRL_SRAM6_SP_RESET _u(0x1) -#define ACCESSCTRL_SRAM6_SP_BITS _u(0x00000008) -#define ACCESSCTRL_SRAM6_SP_MSB _u(3) -#define ACCESSCTRL_SRAM6_SP_LSB _u(3) -#define ACCESSCTRL_SRAM6_SP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_SRAM6_SU -// Description : If 1, and SP is also set, SRAM6 can be accessed from a Secure, -// Unprivileged context. -#define ACCESSCTRL_SRAM6_SU_RESET _u(0x1) -#define ACCESSCTRL_SRAM6_SU_BITS _u(0x00000004) -#define ACCESSCTRL_SRAM6_SU_MSB _u(2) -#define ACCESSCTRL_SRAM6_SU_LSB _u(2) -#define ACCESSCTRL_SRAM6_SU_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_SRAM6_NSP -// Description : If 1, SRAM6 can be accessed from a Non-secure, Privileged -// context. -#define ACCESSCTRL_SRAM6_NSP_RESET _u(0x1) -#define ACCESSCTRL_SRAM6_NSP_BITS _u(0x00000002) -#define ACCESSCTRL_SRAM6_NSP_MSB _u(1) -#define ACCESSCTRL_SRAM6_NSP_LSB _u(1) -#define ACCESSCTRL_SRAM6_NSP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_SRAM6_NSU -// Description : If 1, and NSP is also set, SRAM6 can be accessed from a Non- -// secure, Unprivileged context. -// -// This bit is writable from a Non-secure, Privileged context, if -// and only if the NSP bit is set. -#define ACCESSCTRL_SRAM6_NSU_RESET _u(0x1) -#define ACCESSCTRL_SRAM6_NSU_BITS _u(0x00000001) -#define ACCESSCTRL_SRAM6_NSU_MSB _u(0) -#define ACCESSCTRL_SRAM6_NSU_LSB _u(0) -#define ACCESSCTRL_SRAM6_NSU_ACCESS "RW" -// ============================================================================= -// Register : ACCESSCTRL_SRAM7 -// Description : Control whether debugger, DMA, core 0 and core 1 can access -// SRAM7, and at what security/privilege levels they can do so. -// -// Defaults to fully open access. -// -// This register is writable only from a Secure, Privileged -// processor or debugger, with the exception of the NSU bit, which -// becomes Non-secure-Privileged-writable when the NSP bit is set. -#define ACCESSCTRL_SRAM7_OFFSET _u(0x00000038) -#define ACCESSCTRL_SRAM7_BITS _u(0x000000ff) -#define ACCESSCTRL_SRAM7_RESET _u(0x000000ff) -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_SRAM7_DBG -// Description : If 1, SRAM7 can be accessed by the debugger, at -// security/privilege levels permitted by SP/NSP/SU/NSU in this -// register. -#define ACCESSCTRL_SRAM7_DBG_RESET _u(0x1) -#define ACCESSCTRL_SRAM7_DBG_BITS _u(0x00000080) -#define ACCESSCTRL_SRAM7_DBG_MSB _u(7) -#define ACCESSCTRL_SRAM7_DBG_LSB _u(7) -#define ACCESSCTRL_SRAM7_DBG_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_SRAM7_DMA -// Description : If 1, SRAM7 can be accessed by the DMA, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_SRAM7_DMA_RESET _u(0x1) -#define ACCESSCTRL_SRAM7_DMA_BITS _u(0x00000040) -#define ACCESSCTRL_SRAM7_DMA_MSB _u(6) -#define ACCESSCTRL_SRAM7_DMA_LSB _u(6) -#define ACCESSCTRL_SRAM7_DMA_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_SRAM7_CORE1 -// Description : If 1, SRAM7 can be accessed by core 1, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_SRAM7_CORE1_RESET _u(0x1) -#define ACCESSCTRL_SRAM7_CORE1_BITS _u(0x00000020) -#define ACCESSCTRL_SRAM7_CORE1_MSB _u(5) -#define ACCESSCTRL_SRAM7_CORE1_LSB _u(5) -#define ACCESSCTRL_SRAM7_CORE1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_SRAM7_CORE0 -// Description : If 1, SRAM7 can be accessed by core 0, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_SRAM7_CORE0_RESET _u(0x1) -#define ACCESSCTRL_SRAM7_CORE0_BITS _u(0x00000010) -#define ACCESSCTRL_SRAM7_CORE0_MSB _u(4) -#define ACCESSCTRL_SRAM7_CORE0_LSB _u(4) -#define ACCESSCTRL_SRAM7_CORE0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_SRAM7_SP -// Description : If 1, SRAM7 can be accessed from a Secure, Privileged context. -#define ACCESSCTRL_SRAM7_SP_RESET _u(0x1) -#define ACCESSCTRL_SRAM7_SP_BITS _u(0x00000008) -#define ACCESSCTRL_SRAM7_SP_MSB _u(3) -#define ACCESSCTRL_SRAM7_SP_LSB _u(3) -#define ACCESSCTRL_SRAM7_SP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_SRAM7_SU -// Description : If 1, and SP is also set, SRAM7 can be accessed from a Secure, -// Unprivileged context. -#define ACCESSCTRL_SRAM7_SU_RESET _u(0x1) -#define ACCESSCTRL_SRAM7_SU_BITS _u(0x00000004) -#define ACCESSCTRL_SRAM7_SU_MSB _u(2) -#define ACCESSCTRL_SRAM7_SU_LSB _u(2) -#define ACCESSCTRL_SRAM7_SU_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_SRAM7_NSP -// Description : If 1, SRAM7 can be accessed from a Non-secure, Privileged -// context. -#define ACCESSCTRL_SRAM7_NSP_RESET _u(0x1) -#define ACCESSCTRL_SRAM7_NSP_BITS _u(0x00000002) -#define ACCESSCTRL_SRAM7_NSP_MSB _u(1) -#define ACCESSCTRL_SRAM7_NSP_LSB _u(1) -#define ACCESSCTRL_SRAM7_NSP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_SRAM7_NSU -// Description : If 1, and NSP is also set, SRAM7 can be accessed from a Non- -// secure, Unprivileged context. -// -// This bit is writable from a Non-secure, Privileged context, if -// and only if the NSP bit is set. -#define ACCESSCTRL_SRAM7_NSU_RESET _u(0x1) -#define ACCESSCTRL_SRAM7_NSU_BITS _u(0x00000001) -#define ACCESSCTRL_SRAM7_NSU_MSB _u(0) -#define ACCESSCTRL_SRAM7_NSU_LSB _u(0) -#define ACCESSCTRL_SRAM7_NSU_ACCESS "RW" -// ============================================================================= -// Register : ACCESSCTRL_SRAM8 -// Description : Control whether debugger, DMA, core 0 and core 1 can access -// SRAM8, and at what security/privilege levels they can do so. -// -// Defaults to fully open access. -// -// This register is writable only from a Secure, Privileged -// processor or debugger, with the exception of the NSU bit, which -// becomes Non-secure-Privileged-writable when the NSP bit is set. -#define ACCESSCTRL_SRAM8_OFFSET _u(0x0000003c) -#define ACCESSCTRL_SRAM8_BITS _u(0x000000ff) -#define ACCESSCTRL_SRAM8_RESET _u(0x000000ff) -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_SRAM8_DBG -// Description : If 1, SRAM8 can be accessed by the debugger, at -// security/privilege levels permitted by SP/NSP/SU/NSU in this -// register. -#define ACCESSCTRL_SRAM8_DBG_RESET _u(0x1) -#define ACCESSCTRL_SRAM8_DBG_BITS _u(0x00000080) -#define ACCESSCTRL_SRAM8_DBG_MSB _u(7) -#define ACCESSCTRL_SRAM8_DBG_LSB _u(7) -#define ACCESSCTRL_SRAM8_DBG_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_SRAM8_DMA -// Description : If 1, SRAM8 can be accessed by the DMA, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_SRAM8_DMA_RESET _u(0x1) -#define ACCESSCTRL_SRAM8_DMA_BITS _u(0x00000040) -#define ACCESSCTRL_SRAM8_DMA_MSB _u(6) -#define ACCESSCTRL_SRAM8_DMA_LSB _u(6) -#define ACCESSCTRL_SRAM8_DMA_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_SRAM8_CORE1 -// Description : If 1, SRAM8 can be accessed by core 1, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_SRAM8_CORE1_RESET _u(0x1) -#define ACCESSCTRL_SRAM8_CORE1_BITS _u(0x00000020) -#define ACCESSCTRL_SRAM8_CORE1_MSB _u(5) -#define ACCESSCTRL_SRAM8_CORE1_LSB _u(5) -#define ACCESSCTRL_SRAM8_CORE1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_SRAM8_CORE0 -// Description : If 1, SRAM8 can be accessed by core 0, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_SRAM8_CORE0_RESET _u(0x1) -#define ACCESSCTRL_SRAM8_CORE0_BITS _u(0x00000010) -#define ACCESSCTRL_SRAM8_CORE0_MSB _u(4) -#define ACCESSCTRL_SRAM8_CORE0_LSB _u(4) -#define ACCESSCTRL_SRAM8_CORE0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_SRAM8_SP -// Description : If 1, SRAM8 can be accessed from a Secure, Privileged context. -#define ACCESSCTRL_SRAM8_SP_RESET _u(0x1) -#define ACCESSCTRL_SRAM8_SP_BITS _u(0x00000008) -#define ACCESSCTRL_SRAM8_SP_MSB _u(3) -#define ACCESSCTRL_SRAM8_SP_LSB _u(3) -#define ACCESSCTRL_SRAM8_SP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_SRAM8_SU -// Description : If 1, and SP is also set, SRAM8 can be accessed from a Secure, -// Unprivileged context. -#define ACCESSCTRL_SRAM8_SU_RESET _u(0x1) -#define ACCESSCTRL_SRAM8_SU_BITS _u(0x00000004) -#define ACCESSCTRL_SRAM8_SU_MSB _u(2) -#define ACCESSCTRL_SRAM8_SU_LSB _u(2) -#define ACCESSCTRL_SRAM8_SU_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_SRAM8_NSP -// Description : If 1, SRAM8 can be accessed from a Non-secure, Privileged -// context. -#define ACCESSCTRL_SRAM8_NSP_RESET _u(0x1) -#define ACCESSCTRL_SRAM8_NSP_BITS _u(0x00000002) -#define ACCESSCTRL_SRAM8_NSP_MSB _u(1) -#define ACCESSCTRL_SRAM8_NSP_LSB _u(1) -#define ACCESSCTRL_SRAM8_NSP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_SRAM8_NSU -// Description : If 1, and NSP is also set, SRAM8 can be accessed from a Non- -// secure, Unprivileged context. -// -// This bit is writable from a Non-secure, Privileged context, if -// and only if the NSP bit is set. -#define ACCESSCTRL_SRAM8_NSU_RESET _u(0x1) -#define ACCESSCTRL_SRAM8_NSU_BITS _u(0x00000001) -#define ACCESSCTRL_SRAM8_NSU_MSB _u(0) -#define ACCESSCTRL_SRAM8_NSU_LSB _u(0) -#define ACCESSCTRL_SRAM8_NSU_ACCESS "RW" -// ============================================================================= -// Register : ACCESSCTRL_SRAM9 -// Description : Control whether debugger, DMA, core 0 and core 1 can access -// SRAM9, and at what security/privilege levels they can do so. -// -// Defaults to fully open access. -// -// This register is writable only from a Secure, Privileged -// processor or debugger, with the exception of the NSU bit, which -// becomes Non-secure-Privileged-writable when the NSP bit is set. -#define ACCESSCTRL_SRAM9_OFFSET _u(0x00000040) -#define ACCESSCTRL_SRAM9_BITS _u(0x000000ff) -#define ACCESSCTRL_SRAM9_RESET _u(0x000000ff) -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_SRAM9_DBG -// Description : If 1, SRAM9 can be accessed by the debugger, at -// security/privilege levels permitted by SP/NSP/SU/NSU in this -// register. -#define ACCESSCTRL_SRAM9_DBG_RESET _u(0x1) -#define ACCESSCTRL_SRAM9_DBG_BITS _u(0x00000080) -#define ACCESSCTRL_SRAM9_DBG_MSB _u(7) -#define ACCESSCTRL_SRAM9_DBG_LSB _u(7) -#define ACCESSCTRL_SRAM9_DBG_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_SRAM9_DMA -// Description : If 1, SRAM9 can be accessed by the DMA, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_SRAM9_DMA_RESET _u(0x1) -#define ACCESSCTRL_SRAM9_DMA_BITS _u(0x00000040) -#define ACCESSCTRL_SRAM9_DMA_MSB _u(6) -#define ACCESSCTRL_SRAM9_DMA_LSB _u(6) -#define ACCESSCTRL_SRAM9_DMA_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_SRAM9_CORE1 -// Description : If 1, SRAM9 can be accessed by core 1, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_SRAM9_CORE1_RESET _u(0x1) -#define ACCESSCTRL_SRAM9_CORE1_BITS _u(0x00000020) -#define ACCESSCTRL_SRAM9_CORE1_MSB _u(5) -#define ACCESSCTRL_SRAM9_CORE1_LSB _u(5) -#define ACCESSCTRL_SRAM9_CORE1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_SRAM9_CORE0 -// Description : If 1, SRAM9 can be accessed by core 0, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_SRAM9_CORE0_RESET _u(0x1) -#define ACCESSCTRL_SRAM9_CORE0_BITS _u(0x00000010) -#define ACCESSCTRL_SRAM9_CORE0_MSB _u(4) -#define ACCESSCTRL_SRAM9_CORE0_LSB _u(4) -#define ACCESSCTRL_SRAM9_CORE0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_SRAM9_SP -// Description : If 1, SRAM9 can be accessed from a Secure, Privileged context. -#define ACCESSCTRL_SRAM9_SP_RESET _u(0x1) -#define ACCESSCTRL_SRAM9_SP_BITS _u(0x00000008) -#define ACCESSCTRL_SRAM9_SP_MSB _u(3) -#define ACCESSCTRL_SRAM9_SP_LSB _u(3) -#define ACCESSCTRL_SRAM9_SP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_SRAM9_SU -// Description : If 1, and SP is also set, SRAM9 can be accessed from a Secure, -// Unprivileged context. -#define ACCESSCTRL_SRAM9_SU_RESET _u(0x1) -#define ACCESSCTRL_SRAM9_SU_BITS _u(0x00000004) -#define ACCESSCTRL_SRAM9_SU_MSB _u(2) -#define ACCESSCTRL_SRAM9_SU_LSB _u(2) -#define ACCESSCTRL_SRAM9_SU_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_SRAM9_NSP -// Description : If 1, SRAM9 can be accessed from a Non-secure, Privileged -// context. -#define ACCESSCTRL_SRAM9_NSP_RESET _u(0x1) -#define ACCESSCTRL_SRAM9_NSP_BITS _u(0x00000002) -#define ACCESSCTRL_SRAM9_NSP_MSB _u(1) -#define ACCESSCTRL_SRAM9_NSP_LSB _u(1) -#define ACCESSCTRL_SRAM9_NSP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_SRAM9_NSU -// Description : If 1, and NSP is also set, SRAM9 can be accessed from a Non- -// secure, Unprivileged context. -// -// This bit is writable from a Non-secure, Privileged context, if -// and only if the NSP bit is set. -#define ACCESSCTRL_SRAM9_NSU_RESET _u(0x1) -#define ACCESSCTRL_SRAM9_NSU_BITS _u(0x00000001) -#define ACCESSCTRL_SRAM9_NSU_MSB _u(0) -#define ACCESSCTRL_SRAM9_NSU_LSB _u(0) -#define ACCESSCTRL_SRAM9_NSU_ACCESS "RW" -// ============================================================================= -// Register : ACCESSCTRL_DMA -// Description : Control whether debugger, DMA, core 0 and core 1 can access -// DMA, and at what security/privilege levels they can do so. -// -// Defaults to Secure access from any master. -// -// This register is writable only from a Secure, Privileged -// processor or debugger, with the exception of the NSU bit, which -// becomes Non-secure-Privileged-writable when the NSP bit is set. -#define ACCESSCTRL_DMA_OFFSET _u(0x00000044) -#define ACCESSCTRL_DMA_BITS _u(0x000000ff) -#define ACCESSCTRL_DMA_RESET _u(0x000000fc) -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_DMA_DBG -// Description : If 1, DMA can be accessed by the debugger, at -// security/privilege levels permitted by SP/NSP/SU/NSU in this -// register. -#define ACCESSCTRL_DMA_DBG_RESET _u(0x1) -#define ACCESSCTRL_DMA_DBG_BITS _u(0x00000080) -#define ACCESSCTRL_DMA_DBG_MSB _u(7) -#define ACCESSCTRL_DMA_DBG_LSB _u(7) -#define ACCESSCTRL_DMA_DBG_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_DMA_DMA -// Description : If 1, DMA can be accessed by the DMA, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_DMA_DMA_RESET _u(0x1) -#define ACCESSCTRL_DMA_DMA_BITS _u(0x00000040) -#define ACCESSCTRL_DMA_DMA_MSB _u(6) -#define ACCESSCTRL_DMA_DMA_LSB _u(6) -#define ACCESSCTRL_DMA_DMA_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_DMA_CORE1 -// Description : If 1, DMA can be accessed by core 1, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_DMA_CORE1_RESET _u(0x1) -#define ACCESSCTRL_DMA_CORE1_BITS _u(0x00000020) -#define ACCESSCTRL_DMA_CORE1_MSB _u(5) -#define ACCESSCTRL_DMA_CORE1_LSB _u(5) -#define ACCESSCTRL_DMA_CORE1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_DMA_CORE0 -// Description : If 1, DMA can be accessed by core 0, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_DMA_CORE0_RESET _u(0x1) -#define ACCESSCTRL_DMA_CORE0_BITS _u(0x00000010) -#define ACCESSCTRL_DMA_CORE0_MSB _u(4) -#define ACCESSCTRL_DMA_CORE0_LSB _u(4) -#define ACCESSCTRL_DMA_CORE0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_DMA_SP -// Description : If 1, DMA can be accessed from a Secure, Privileged context. -#define ACCESSCTRL_DMA_SP_RESET _u(0x1) -#define ACCESSCTRL_DMA_SP_BITS _u(0x00000008) -#define ACCESSCTRL_DMA_SP_MSB _u(3) -#define ACCESSCTRL_DMA_SP_LSB _u(3) -#define ACCESSCTRL_DMA_SP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_DMA_SU -// Description : If 1, and SP is also set, DMA can be accessed from a Secure, -// Unprivileged context. -#define ACCESSCTRL_DMA_SU_RESET _u(0x1) -#define ACCESSCTRL_DMA_SU_BITS _u(0x00000004) -#define ACCESSCTRL_DMA_SU_MSB _u(2) -#define ACCESSCTRL_DMA_SU_LSB _u(2) -#define ACCESSCTRL_DMA_SU_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_DMA_NSP -// Description : If 1, DMA can be accessed from a Non-secure, Privileged -// context. -#define ACCESSCTRL_DMA_NSP_RESET _u(0x0) -#define ACCESSCTRL_DMA_NSP_BITS _u(0x00000002) -#define ACCESSCTRL_DMA_NSP_MSB _u(1) -#define ACCESSCTRL_DMA_NSP_LSB _u(1) -#define ACCESSCTRL_DMA_NSP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_DMA_NSU -// Description : If 1, and NSP is also set, DMA can be accessed from a Non- -// secure, Unprivileged context. -// -// This bit is writable from a Non-secure, Privileged context, if -// and only if the NSP bit is set. -#define ACCESSCTRL_DMA_NSU_RESET _u(0x0) -#define ACCESSCTRL_DMA_NSU_BITS _u(0x00000001) -#define ACCESSCTRL_DMA_NSU_MSB _u(0) -#define ACCESSCTRL_DMA_NSU_LSB _u(0) -#define ACCESSCTRL_DMA_NSU_ACCESS "RW" -// ============================================================================= -// Register : ACCESSCTRL_USBCTRL -// Description : Control whether debugger, DMA, core 0 and core 1 can access -// USBCTRL, and at what security/privilege levels they can do so. -// -// Defaults to Secure access from any master. -// -// This register is writable only from a Secure, Privileged -// processor or debugger, with the exception of the NSU bit, which -// becomes Non-secure-Privileged-writable when the NSP bit is set. -#define ACCESSCTRL_USBCTRL_OFFSET _u(0x00000048) -#define ACCESSCTRL_USBCTRL_BITS _u(0x000000ff) -#define ACCESSCTRL_USBCTRL_RESET _u(0x000000fc) -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_USBCTRL_DBG -// Description : If 1, USBCTRL can be accessed by the debugger, at -// security/privilege levels permitted by SP/NSP/SU/NSU in this -// register. -#define ACCESSCTRL_USBCTRL_DBG_RESET _u(0x1) -#define ACCESSCTRL_USBCTRL_DBG_BITS _u(0x00000080) -#define ACCESSCTRL_USBCTRL_DBG_MSB _u(7) -#define ACCESSCTRL_USBCTRL_DBG_LSB _u(7) -#define ACCESSCTRL_USBCTRL_DBG_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_USBCTRL_DMA -// Description : If 1, USBCTRL can be accessed by the DMA, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_USBCTRL_DMA_RESET _u(0x1) -#define ACCESSCTRL_USBCTRL_DMA_BITS _u(0x00000040) -#define ACCESSCTRL_USBCTRL_DMA_MSB _u(6) -#define ACCESSCTRL_USBCTRL_DMA_LSB _u(6) -#define ACCESSCTRL_USBCTRL_DMA_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_USBCTRL_CORE1 -// Description : If 1, USBCTRL can be accessed by core 1, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_USBCTRL_CORE1_RESET _u(0x1) -#define ACCESSCTRL_USBCTRL_CORE1_BITS _u(0x00000020) -#define ACCESSCTRL_USBCTRL_CORE1_MSB _u(5) -#define ACCESSCTRL_USBCTRL_CORE1_LSB _u(5) -#define ACCESSCTRL_USBCTRL_CORE1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_USBCTRL_CORE0 -// Description : If 1, USBCTRL can be accessed by core 0, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_USBCTRL_CORE0_RESET _u(0x1) -#define ACCESSCTRL_USBCTRL_CORE0_BITS _u(0x00000010) -#define ACCESSCTRL_USBCTRL_CORE0_MSB _u(4) -#define ACCESSCTRL_USBCTRL_CORE0_LSB _u(4) -#define ACCESSCTRL_USBCTRL_CORE0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_USBCTRL_SP -// Description : If 1, USBCTRL can be accessed from a Secure, Privileged -// context. -#define ACCESSCTRL_USBCTRL_SP_RESET _u(0x1) -#define ACCESSCTRL_USBCTRL_SP_BITS _u(0x00000008) -#define ACCESSCTRL_USBCTRL_SP_MSB _u(3) -#define ACCESSCTRL_USBCTRL_SP_LSB _u(3) -#define ACCESSCTRL_USBCTRL_SP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_USBCTRL_SU -// Description : If 1, and SP is also set, USBCTRL can be accessed from a -// Secure, Unprivileged context. -#define ACCESSCTRL_USBCTRL_SU_RESET _u(0x1) -#define ACCESSCTRL_USBCTRL_SU_BITS _u(0x00000004) -#define ACCESSCTRL_USBCTRL_SU_MSB _u(2) -#define ACCESSCTRL_USBCTRL_SU_LSB _u(2) -#define ACCESSCTRL_USBCTRL_SU_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_USBCTRL_NSP -// Description : If 1, USBCTRL can be accessed from a Non-secure, Privileged -// context. -#define ACCESSCTRL_USBCTRL_NSP_RESET _u(0x0) -#define ACCESSCTRL_USBCTRL_NSP_BITS _u(0x00000002) -#define ACCESSCTRL_USBCTRL_NSP_MSB _u(1) -#define ACCESSCTRL_USBCTRL_NSP_LSB _u(1) -#define ACCESSCTRL_USBCTRL_NSP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_USBCTRL_NSU -// Description : If 1, and NSP is also set, USBCTRL can be accessed from a Non- -// secure, Unprivileged context. -// -// This bit is writable from a Non-secure, Privileged context, if -// and only if the NSP bit is set. -#define ACCESSCTRL_USBCTRL_NSU_RESET _u(0x0) -#define ACCESSCTRL_USBCTRL_NSU_BITS _u(0x00000001) -#define ACCESSCTRL_USBCTRL_NSU_MSB _u(0) -#define ACCESSCTRL_USBCTRL_NSU_LSB _u(0) -#define ACCESSCTRL_USBCTRL_NSU_ACCESS "RW" -// ============================================================================= -// Register : ACCESSCTRL_PIO0 -// Description : Control whether debugger, DMA, core 0 and core 1 can access -// PIO0, and at what security/privilege levels they can do so. -// -// Defaults to Secure access from any master. -// -// This register is writable only from a Secure, Privileged -// processor or debugger, with the exception of the NSU bit, which -// becomes Non-secure-Privileged-writable when the NSP bit is set. -#define ACCESSCTRL_PIO0_OFFSET _u(0x0000004c) -#define ACCESSCTRL_PIO0_BITS _u(0x000000ff) -#define ACCESSCTRL_PIO0_RESET _u(0x000000fc) -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_PIO0_DBG -// Description : If 1, PIO0 can be accessed by the debugger, at -// security/privilege levels permitted by SP/NSP/SU/NSU in this -// register. -#define ACCESSCTRL_PIO0_DBG_RESET _u(0x1) -#define ACCESSCTRL_PIO0_DBG_BITS _u(0x00000080) -#define ACCESSCTRL_PIO0_DBG_MSB _u(7) -#define ACCESSCTRL_PIO0_DBG_LSB _u(7) -#define ACCESSCTRL_PIO0_DBG_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_PIO0_DMA -// Description : If 1, PIO0 can be accessed by the DMA, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_PIO0_DMA_RESET _u(0x1) -#define ACCESSCTRL_PIO0_DMA_BITS _u(0x00000040) -#define ACCESSCTRL_PIO0_DMA_MSB _u(6) -#define ACCESSCTRL_PIO0_DMA_LSB _u(6) -#define ACCESSCTRL_PIO0_DMA_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_PIO0_CORE1 -// Description : If 1, PIO0 can be accessed by core 1, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_PIO0_CORE1_RESET _u(0x1) -#define ACCESSCTRL_PIO0_CORE1_BITS _u(0x00000020) -#define ACCESSCTRL_PIO0_CORE1_MSB _u(5) -#define ACCESSCTRL_PIO0_CORE1_LSB _u(5) -#define ACCESSCTRL_PIO0_CORE1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_PIO0_CORE0 -// Description : If 1, PIO0 can be accessed by core 0, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_PIO0_CORE0_RESET _u(0x1) -#define ACCESSCTRL_PIO0_CORE0_BITS _u(0x00000010) -#define ACCESSCTRL_PIO0_CORE0_MSB _u(4) -#define ACCESSCTRL_PIO0_CORE0_LSB _u(4) -#define ACCESSCTRL_PIO0_CORE0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_PIO0_SP -// Description : If 1, PIO0 can be accessed from a Secure, Privileged context. -#define ACCESSCTRL_PIO0_SP_RESET _u(0x1) -#define ACCESSCTRL_PIO0_SP_BITS _u(0x00000008) -#define ACCESSCTRL_PIO0_SP_MSB _u(3) -#define ACCESSCTRL_PIO0_SP_LSB _u(3) -#define ACCESSCTRL_PIO0_SP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_PIO0_SU -// Description : If 1, and SP is also set, PIO0 can be accessed from a Secure, -// Unprivileged context. -#define ACCESSCTRL_PIO0_SU_RESET _u(0x1) -#define ACCESSCTRL_PIO0_SU_BITS _u(0x00000004) -#define ACCESSCTRL_PIO0_SU_MSB _u(2) -#define ACCESSCTRL_PIO0_SU_LSB _u(2) -#define ACCESSCTRL_PIO0_SU_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_PIO0_NSP -// Description : If 1, PIO0 can be accessed from a Non-secure, Privileged -// context. -#define ACCESSCTRL_PIO0_NSP_RESET _u(0x0) -#define ACCESSCTRL_PIO0_NSP_BITS _u(0x00000002) -#define ACCESSCTRL_PIO0_NSP_MSB _u(1) -#define ACCESSCTRL_PIO0_NSP_LSB _u(1) -#define ACCESSCTRL_PIO0_NSP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_PIO0_NSU -// Description : If 1, and NSP is also set, PIO0 can be accessed from a Non- -// secure, Unprivileged context. -// -// This bit is writable from a Non-secure, Privileged context, if -// and only if the NSP bit is set. -#define ACCESSCTRL_PIO0_NSU_RESET _u(0x0) -#define ACCESSCTRL_PIO0_NSU_BITS _u(0x00000001) -#define ACCESSCTRL_PIO0_NSU_MSB _u(0) -#define ACCESSCTRL_PIO0_NSU_LSB _u(0) -#define ACCESSCTRL_PIO0_NSU_ACCESS "RW" -// ============================================================================= -// Register : ACCESSCTRL_PIO1 -// Description : Control whether debugger, DMA, core 0 and core 1 can access -// PIO1, and at what security/privilege levels they can do so. -// -// Defaults to Secure access from any master. -// -// This register is writable only from a Secure, Privileged -// processor or debugger, with the exception of the NSU bit, which -// becomes Non-secure-Privileged-writable when the NSP bit is set. -#define ACCESSCTRL_PIO1_OFFSET _u(0x00000050) -#define ACCESSCTRL_PIO1_BITS _u(0x000000ff) -#define ACCESSCTRL_PIO1_RESET _u(0x000000fc) -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_PIO1_DBG -// Description : If 1, PIO1 can be accessed by the debugger, at -// security/privilege levels permitted by SP/NSP/SU/NSU in this -// register. -#define ACCESSCTRL_PIO1_DBG_RESET _u(0x1) -#define ACCESSCTRL_PIO1_DBG_BITS _u(0x00000080) -#define ACCESSCTRL_PIO1_DBG_MSB _u(7) -#define ACCESSCTRL_PIO1_DBG_LSB _u(7) -#define ACCESSCTRL_PIO1_DBG_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_PIO1_DMA -// Description : If 1, PIO1 can be accessed by the DMA, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_PIO1_DMA_RESET _u(0x1) -#define ACCESSCTRL_PIO1_DMA_BITS _u(0x00000040) -#define ACCESSCTRL_PIO1_DMA_MSB _u(6) -#define ACCESSCTRL_PIO1_DMA_LSB _u(6) -#define ACCESSCTRL_PIO1_DMA_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_PIO1_CORE1 -// Description : If 1, PIO1 can be accessed by core 1, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_PIO1_CORE1_RESET _u(0x1) -#define ACCESSCTRL_PIO1_CORE1_BITS _u(0x00000020) -#define ACCESSCTRL_PIO1_CORE1_MSB _u(5) -#define ACCESSCTRL_PIO1_CORE1_LSB _u(5) -#define ACCESSCTRL_PIO1_CORE1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_PIO1_CORE0 -// Description : If 1, PIO1 can be accessed by core 0, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_PIO1_CORE0_RESET _u(0x1) -#define ACCESSCTRL_PIO1_CORE0_BITS _u(0x00000010) -#define ACCESSCTRL_PIO1_CORE0_MSB _u(4) -#define ACCESSCTRL_PIO1_CORE0_LSB _u(4) -#define ACCESSCTRL_PIO1_CORE0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_PIO1_SP -// Description : If 1, PIO1 can be accessed from a Secure, Privileged context. -#define ACCESSCTRL_PIO1_SP_RESET _u(0x1) -#define ACCESSCTRL_PIO1_SP_BITS _u(0x00000008) -#define ACCESSCTRL_PIO1_SP_MSB _u(3) -#define ACCESSCTRL_PIO1_SP_LSB _u(3) -#define ACCESSCTRL_PIO1_SP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_PIO1_SU -// Description : If 1, and SP is also set, PIO1 can be accessed from a Secure, -// Unprivileged context. -#define ACCESSCTRL_PIO1_SU_RESET _u(0x1) -#define ACCESSCTRL_PIO1_SU_BITS _u(0x00000004) -#define ACCESSCTRL_PIO1_SU_MSB _u(2) -#define ACCESSCTRL_PIO1_SU_LSB _u(2) -#define ACCESSCTRL_PIO1_SU_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_PIO1_NSP -// Description : If 1, PIO1 can be accessed from a Non-secure, Privileged -// context. -#define ACCESSCTRL_PIO1_NSP_RESET _u(0x0) -#define ACCESSCTRL_PIO1_NSP_BITS _u(0x00000002) -#define ACCESSCTRL_PIO1_NSP_MSB _u(1) -#define ACCESSCTRL_PIO1_NSP_LSB _u(1) -#define ACCESSCTRL_PIO1_NSP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_PIO1_NSU -// Description : If 1, and NSP is also set, PIO1 can be accessed from a Non- -// secure, Unprivileged context. -// -// This bit is writable from a Non-secure, Privileged context, if -// and only if the NSP bit is set. -#define ACCESSCTRL_PIO1_NSU_RESET _u(0x0) -#define ACCESSCTRL_PIO1_NSU_BITS _u(0x00000001) -#define ACCESSCTRL_PIO1_NSU_MSB _u(0) -#define ACCESSCTRL_PIO1_NSU_LSB _u(0) -#define ACCESSCTRL_PIO1_NSU_ACCESS "RW" -// ============================================================================= -// Register : ACCESSCTRL_PIO2 -// Description : Control whether debugger, DMA, core 0 and core 1 can access -// PIO2, and at what security/privilege levels they can do so. -// -// Defaults to Secure access from any master. -// -// This register is writable only from a Secure, Privileged -// processor or debugger, with the exception of the NSU bit, which -// becomes Non-secure-Privileged-writable when the NSP bit is set. -#define ACCESSCTRL_PIO2_OFFSET _u(0x00000054) -#define ACCESSCTRL_PIO2_BITS _u(0x000000ff) -#define ACCESSCTRL_PIO2_RESET _u(0x000000fc) -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_PIO2_DBG -// Description : If 1, PIO2 can be accessed by the debugger, at -// security/privilege levels permitted by SP/NSP/SU/NSU in this -// register. -#define ACCESSCTRL_PIO2_DBG_RESET _u(0x1) -#define ACCESSCTRL_PIO2_DBG_BITS _u(0x00000080) -#define ACCESSCTRL_PIO2_DBG_MSB _u(7) -#define ACCESSCTRL_PIO2_DBG_LSB _u(7) -#define ACCESSCTRL_PIO2_DBG_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_PIO2_DMA -// Description : If 1, PIO2 can be accessed by the DMA, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_PIO2_DMA_RESET _u(0x1) -#define ACCESSCTRL_PIO2_DMA_BITS _u(0x00000040) -#define ACCESSCTRL_PIO2_DMA_MSB _u(6) -#define ACCESSCTRL_PIO2_DMA_LSB _u(6) -#define ACCESSCTRL_PIO2_DMA_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_PIO2_CORE1 -// Description : If 1, PIO2 can be accessed by core 1, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_PIO2_CORE1_RESET _u(0x1) -#define ACCESSCTRL_PIO2_CORE1_BITS _u(0x00000020) -#define ACCESSCTRL_PIO2_CORE1_MSB _u(5) -#define ACCESSCTRL_PIO2_CORE1_LSB _u(5) -#define ACCESSCTRL_PIO2_CORE1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_PIO2_CORE0 -// Description : If 1, PIO2 can be accessed by core 0, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_PIO2_CORE0_RESET _u(0x1) -#define ACCESSCTRL_PIO2_CORE0_BITS _u(0x00000010) -#define ACCESSCTRL_PIO2_CORE0_MSB _u(4) -#define ACCESSCTRL_PIO2_CORE0_LSB _u(4) -#define ACCESSCTRL_PIO2_CORE0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_PIO2_SP -// Description : If 1, PIO2 can be accessed from a Secure, Privileged context. -#define ACCESSCTRL_PIO2_SP_RESET _u(0x1) -#define ACCESSCTRL_PIO2_SP_BITS _u(0x00000008) -#define ACCESSCTRL_PIO2_SP_MSB _u(3) -#define ACCESSCTRL_PIO2_SP_LSB _u(3) -#define ACCESSCTRL_PIO2_SP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_PIO2_SU -// Description : If 1, and SP is also set, PIO2 can be accessed from a Secure, -// Unprivileged context. -#define ACCESSCTRL_PIO2_SU_RESET _u(0x1) -#define ACCESSCTRL_PIO2_SU_BITS _u(0x00000004) -#define ACCESSCTRL_PIO2_SU_MSB _u(2) -#define ACCESSCTRL_PIO2_SU_LSB _u(2) -#define ACCESSCTRL_PIO2_SU_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_PIO2_NSP -// Description : If 1, PIO2 can be accessed from a Non-secure, Privileged -// context. -#define ACCESSCTRL_PIO2_NSP_RESET _u(0x0) -#define ACCESSCTRL_PIO2_NSP_BITS _u(0x00000002) -#define ACCESSCTRL_PIO2_NSP_MSB _u(1) -#define ACCESSCTRL_PIO2_NSP_LSB _u(1) -#define ACCESSCTRL_PIO2_NSP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_PIO2_NSU -// Description : If 1, and NSP is also set, PIO2 can be accessed from a Non- -// secure, Unprivileged context. -// -// This bit is writable from a Non-secure, Privileged context, if -// and only if the NSP bit is set. -#define ACCESSCTRL_PIO2_NSU_RESET _u(0x0) -#define ACCESSCTRL_PIO2_NSU_BITS _u(0x00000001) -#define ACCESSCTRL_PIO2_NSU_MSB _u(0) -#define ACCESSCTRL_PIO2_NSU_LSB _u(0) -#define ACCESSCTRL_PIO2_NSU_ACCESS "RW" -// ============================================================================= -// Register : ACCESSCTRL_CORESIGHT_TRACE -// Description : Control whether debugger, DMA, core 0 and core 1 can access -// CORESIGHT_TRACE, and at what security/privilege levels they can -// do so. -// -// Defaults to Secure, Privileged processor or debug access only. -// -// This register is writable only from a Secure, Privileged -// processor or debugger, with the exception of the NSU bit, which -// becomes Non-secure-Privileged-writable when the NSP bit is set. -#define ACCESSCTRL_CORESIGHT_TRACE_OFFSET _u(0x00000058) -#define ACCESSCTRL_CORESIGHT_TRACE_BITS _u(0x000000ff) -#define ACCESSCTRL_CORESIGHT_TRACE_RESET _u(0x000000b8) -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_CORESIGHT_TRACE_DBG -// Description : If 1, CORESIGHT_TRACE can be accessed by the debugger, at -// security/privilege levels permitted by SP/NSP/SU/NSU in this -// register. -#define ACCESSCTRL_CORESIGHT_TRACE_DBG_RESET _u(0x1) -#define ACCESSCTRL_CORESIGHT_TRACE_DBG_BITS _u(0x00000080) -#define ACCESSCTRL_CORESIGHT_TRACE_DBG_MSB _u(7) -#define ACCESSCTRL_CORESIGHT_TRACE_DBG_LSB _u(7) -#define ACCESSCTRL_CORESIGHT_TRACE_DBG_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_CORESIGHT_TRACE_DMA -// Description : If 1, CORESIGHT_TRACE can be accessed by the DMA, at -// security/privilege levels permitted by SP/NSP/SU/NSU in this -// register. -#define ACCESSCTRL_CORESIGHT_TRACE_DMA_RESET _u(0x0) -#define ACCESSCTRL_CORESIGHT_TRACE_DMA_BITS _u(0x00000040) -#define ACCESSCTRL_CORESIGHT_TRACE_DMA_MSB _u(6) -#define ACCESSCTRL_CORESIGHT_TRACE_DMA_LSB _u(6) -#define ACCESSCTRL_CORESIGHT_TRACE_DMA_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_CORESIGHT_TRACE_CORE1 -// Description : If 1, CORESIGHT_TRACE can be accessed by core 1, at -// security/privilege levels permitted by SP/NSP/SU/NSU in this -// register. -#define ACCESSCTRL_CORESIGHT_TRACE_CORE1_RESET _u(0x1) -#define ACCESSCTRL_CORESIGHT_TRACE_CORE1_BITS _u(0x00000020) -#define ACCESSCTRL_CORESIGHT_TRACE_CORE1_MSB _u(5) -#define ACCESSCTRL_CORESIGHT_TRACE_CORE1_LSB _u(5) -#define ACCESSCTRL_CORESIGHT_TRACE_CORE1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_CORESIGHT_TRACE_CORE0 -// Description : If 1, CORESIGHT_TRACE can be accessed by core 0, at -// security/privilege levels permitted by SP/NSP/SU/NSU in this -// register. -#define ACCESSCTRL_CORESIGHT_TRACE_CORE0_RESET _u(0x1) -#define ACCESSCTRL_CORESIGHT_TRACE_CORE0_BITS _u(0x00000010) -#define ACCESSCTRL_CORESIGHT_TRACE_CORE0_MSB _u(4) -#define ACCESSCTRL_CORESIGHT_TRACE_CORE0_LSB _u(4) -#define ACCESSCTRL_CORESIGHT_TRACE_CORE0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_CORESIGHT_TRACE_SP -// Description : If 1, CORESIGHT_TRACE can be accessed from a Secure, Privileged -// context. -#define ACCESSCTRL_CORESIGHT_TRACE_SP_RESET _u(0x1) -#define ACCESSCTRL_CORESIGHT_TRACE_SP_BITS _u(0x00000008) -#define ACCESSCTRL_CORESIGHT_TRACE_SP_MSB _u(3) -#define ACCESSCTRL_CORESIGHT_TRACE_SP_LSB _u(3) -#define ACCESSCTRL_CORESIGHT_TRACE_SP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_CORESIGHT_TRACE_SU -// Description : If 1, and SP is also set, CORESIGHT_TRACE can be accessed from -// a Secure, Unprivileged context. -#define ACCESSCTRL_CORESIGHT_TRACE_SU_RESET _u(0x0) -#define ACCESSCTRL_CORESIGHT_TRACE_SU_BITS _u(0x00000004) -#define ACCESSCTRL_CORESIGHT_TRACE_SU_MSB _u(2) -#define ACCESSCTRL_CORESIGHT_TRACE_SU_LSB _u(2) -#define ACCESSCTRL_CORESIGHT_TRACE_SU_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_CORESIGHT_TRACE_NSP -// Description : If 1, CORESIGHT_TRACE can be accessed from a Non-secure, -// Privileged context. -#define ACCESSCTRL_CORESIGHT_TRACE_NSP_RESET _u(0x0) -#define ACCESSCTRL_CORESIGHT_TRACE_NSP_BITS _u(0x00000002) -#define ACCESSCTRL_CORESIGHT_TRACE_NSP_MSB _u(1) -#define ACCESSCTRL_CORESIGHT_TRACE_NSP_LSB _u(1) -#define ACCESSCTRL_CORESIGHT_TRACE_NSP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_CORESIGHT_TRACE_NSU -// Description : If 1, and NSP is also set, CORESIGHT_TRACE can be accessed from -// a Non-secure, Unprivileged context. -// -// This bit is writable from a Non-secure, Privileged context, if -// and only if the NSP bit is set. -#define ACCESSCTRL_CORESIGHT_TRACE_NSU_RESET _u(0x0) -#define ACCESSCTRL_CORESIGHT_TRACE_NSU_BITS _u(0x00000001) -#define ACCESSCTRL_CORESIGHT_TRACE_NSU_MSB _u(0) -#define ACCESSCTRL_CORESIGHT_TRACE_NSU_LSB _u(0) -#define ACCESSCTRL_CORESIGHT_TRACE_NSU_ACCESS "RW" -// ============================================================================= -// Register : ACCESSCTRL_CORESIGHT_PERIPH -// Description : Control whether debugger, DMA, core 0 and core 1 can access -// CORESIGHT_PERIPH, and at what security/privilege levels they -// can do so. -// -// Defaults to Secure, Privileged processor or debug access only. -// -// This register is writable only from a Secure, Privileged -// processor or debugger, with the exception of the NSU bit, which -// becomes Non-secure-Privileged-writable when the NSP bit is set. -#define ACCESSCTRL_CORESIGHT_PERIPH_OFFSET _u(0x0000005c) -#define ACCESSCTRL_CORESIGHT_PERIPH_BITS _u(0x000000ff) -#define ACCESSCTRL_CORESIGHT_PERIPH_RESET _u(0x000000b8) -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_CORESIGHT_PERIPH_DBG -// Description : If 1, CORESIGHT_PERIPH can be accessed by the debugger, at -// security/privilege levels permitted by SP/NSP/SU/NSU in this -// register. -#define ACCESSCTRL_CORESIGHT_PERIPH_DBG_RESET _u(0x1) -#define ACCESSCTRL_CORESIGHT_PERIPH_DBG_BITS _u(0x00000080) -#define ACCESSCTRL_CORESIGHT_PERIPH_DBG_MSB _u(7) -#define ACCESSCTRL_CORESIGHT_PERIPH_DBG_LSB _u(7) -#define ACCESSCTRL_CORESIGHT_PERIPH_DBG_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_CORESIGHT_PERIPH_DMA -// Description : If 1, CORESIGHT_PERIPH can be accessed by the DMA, at -// security/privilege levels permitted by SP/NSP/SU/NSU in this -// register. -#define ACCESSCTRL_CORESIGHT_PERIPH_DMA_RESET _u(0x0) -#define ACCESSCTRL_CORESIGHT_PERIPH_DMA_BITS _u(0x00000040) -#define ACCESSCTRL_CORESIGHT_PERIPH_DMA_MSB _u(6) -#define ACCESSCTRL_CORESIGHT_PERIPH_DMA_LSB _u(6) -#define ACCESSCTRL_CORESIGHT_PERIPH_DMA_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_CORESIGHT_PERIPH_CORE1 -// Description : If 1, CORESIGHT_PERIPH can be accessed by core 1, at -// security/privilege levels permitted by SP/NSP/SU/NSU in this -// register. -#define ACCESSCTRL_CORESIGHT_PERIPH_CORE1_RESET _u(0x1) -#define ACCESSCTRL_CORESIGHT_PERIPH_CORE1_BITS _u(0x00000020) -#define ACCESSCTRL_CORESIGHT_PERIPH_CORE1_MSB _u(5) -#define ACCESSCTRL_CORESIGHT_PERIPH_CORE1_LSB _u(5) -#define ACCESSCTRL_CORESIGHT_PERIPH_CORE1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_CORESIGHT_PERIPH_CORE0 -// Description : If 1, CORESIGHT_PERIPH can be accessed by core 0, at -// security/privilege levels permitted by SP/NSP/SU/NSU in this -// register. -#define ACCESSCTRL_CORESIGHT_PERIPH_CORE0_RESET _u(0x1) -#define ACCESSCTRL_CORESIGHT_PERIPH_CORE0_BITS _u(0x00000010) -#define ACCESSCTRL_CORESIGHT_PERIPH_CORE0_MSB _u(4) -#define ACCESSCTRL_CORESIGHT_PERIPH_CORE0_LSB _u(4) -#define ACCESSCTRL_CORESIGHT_PERIPH_CORE0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_CORESIGHT_PERIPH_SP -// Description : If 1, CORESIGHT_PERIPH can be accessed from a Secure, -// Privileged context. -#define ACCESSCTRL_CORESIGHT_PERIPH_SP_RESET _u(0x1) -#define ACCESSCTRL_CORESIGHT_PERIPH_SP_BITS _u(0x00000008) -#define ACCESSCTRL_CORESIGHT_PERIPH_SP_MSB _u(3) -#define ACCESSCTRL_CORESIGHT_PERIPH_SP_LSB _u(3) -#define ACCESSCTRL_CORESIGHT_PERIPH_SP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_CORESIGHT_PERIPH_SU -// Description : If 1, and SP is also set, CORESIGHT_PERIPH can be accessed from -// a Secure, Unprivileged context. -#define ACCESSCTRL_CORESIGHT_PERIPH_SU_RESET _u(0x0) -#define ACCESSCTRL_CORESIGHT_PERIPH_SU_BITS _u(0x00000004) -#define ACCESSCTRL_CORESIGHT_PERIPH_SU_MSB _u(2) -#define ACCESSCTRL_CORESIGHT_PERIPH_SU_LSB _u(2) -#define ACCESSCTRL_CORESIGHT_PERIPH_SU_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_CORESIGHT_PERIPH_NSP -// Description : If 1, CORESIGHT_PERIPH can be accessed from a Non-secure, -// Privileged context. -#define ACCESSCTRL_CORESIGHT_PERIPH_NSP_RESET _u(0x0) -#define ACCESSCTRL_CORESIGHT_PERIPH_NSP_BITS _u(0x00000002) -#define ACCESSCTRL_CORESIGHT_PERIPH_NSP_MSB _u(1) -#define ACCESSCTRL_CORESIGHT_PERIPH_NSP_LSB _u(1) -#define ACCESSCTRL_CORESIGHT_PERIPH_NSP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_CORESIGHT_PERIPH_NSU -// Description : If 1, and NSP is also set, CORESIGHT_PERIPH can be accessed -// from a Non-secure, Unprivileged context. -// -// This bit is writable from a Non-secure, Privileged context, if -// and only if the NSP bit is set. -#define ACCESSCTRL_CORESIGHT_PERIPH_NSU_RESET _u(0x0) -#define ACCESSCTRL_CORESIGHT_PERIPH_NSU_BITS _u(0x00000001) -#define ACCESSCTRL_CORESIGHT_PERIPH_NSU_MSB _u(0) -#define ACCESSCTRL_CORESIGHT_PERIPH_NSU_LSB _u(0) -#define ACCESSCTRL_CORESIGHT_PERIPH_NSU_ACCESS "RW" -// ============================================================================= -// Register : ACCESSCTRL_SYSINFO -// Description : Control whether debugger, DMA, core 0 and core 1 can access -// SYSINFO, and at what security/privilege levels they can do so. -// -// Defaults to fully open access. -// -// This register is writable only from a Secure, Privileged -// processor or debugger, with the exception of the NSU bit, which -// becomes Non-secure-Privileged-writable when the NSP bit is set. -#define ACCESSCTRL_SYSINFO_OFFSET _u(0x00000060) -#define ACCESSCTRL_SYSINFO_BITS _u(0x000000ff) -#define ACCESSCTRL_SYSINFO_RESET _u(0x000000ff) -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_SYSINFO_DBG -// Description : If 1, SYSINFO can be accessed by the debugger, at -// security/privilege levels permitted by SP/NSP/SU/NSU in this -// register. -#define ACCESSCTRL_SYSINFO_DBG_RESET _u(0x1) -#define ACCESSCTRL_SYSINFO_DBG_BITS _u(0x00000080) -#define ACCESSCTRL_SYSINFO_DBG_MSB _u(7) -#define ACCESSCTRL_SYSINFO_DBG_LSB _u(7) -#define ACCESSCTRL_SYSINFO_DBG_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_SYSINFO_DMA -// Description : If 1, SYSINFO can be accessed by the DMA, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_SYSINFO_DMA_RESET _u(0x1) -#define ACCESSCTRL_SYSINFO_DMA_BITS _u(0x00000040) -#define ACCESSCTRL_SYSINFO_DMA_MSB _u(6) -#define ACCESSCTRL_SYSINFO_DMA_LSB _u(6) -#define ACCESSCTRL_SYSINFO_DMA_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_SYSINFO_CORE1 -// Description : If 1, SYSINFO can be accessed by core 1, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_SYSINFO_CORE1_RESET _u(0x1) -#define ACCESSCTRL_SYSINFO_CORE1_BITS _u(0x00000020) -#define ACCESSCTRL_SYSINFO_CORE1_MSB _u(5) -#define ACCESSCTRL_SYSINFO_CORE1_LSB _u(5) -#define ACCESSCTRL_SYSINFO_CORE1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_SYSINFO_CORE0 -// Description : If 1, SYSINFO can be accessed by core 0, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_SYSINFO_CORE0_RESET _u(0x1) -#define ACCESSCTRL_SYSINFO_CORE0_BITS _u(0x00000010) -#define ACCESSCTRL_SYSINFO_CORE0_MSB _u(4) -#define ACCESSCTRL_SYSINFO_CORE0_LSB _u(4) -#define ACCESSCTRL_SYSINFO_CORE0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_SYSINFO_SP -// Description : If 1, SYSINFO can be accessed from a Secure, Privileged -// context. -#define ACCESSCTRL_SYSINFO_SP_RESET _u(0x1) -#define ACCESSCTRL_SYSINFO_SP_BITS _u(0x00000008) -#define ACCESSCTRL_SYSINFO_SP_MSB _u(3) -#define ACCESSCTRL_SYSINFO_SP_LSB _u(3) -#define ACCESSCTRL_SYSINFO_SP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_SYSINFO_SU -// Description : If 1, and SP is also set, SYSINFO can be accessed from a -// Secure, Unprivileged context. -#define ACCESSCTRL_SYSINFO_SU_RESET _u(0x1) -#define ACCESSCTRL_SYSINFO_SU_BITS _u(0x00000004) -#define ACCESSCTRL_SYSINFO_SU_MSB _u(2) -#define ACCESSCTRL_SYSINFO_SU_LSB _u(2) -#define ACCESSCTRL_SYSINFO_SU_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_SYSINFO_NSP -// Description : If 1, SYSINFO can be accessed from a Non-secure, Privileged -// context. -#define ACCESSCTRL_SYSINFO_NSP_RESET _u(0x1) -#define ACCESSCTRL_SYSINFO_NSP_BITS _u(0x00000002) -#define ACCESSCTRL_SYSINFO_NSP_MSB _u(1) -#define ACCESSCTRL_SYSINFO_NSP_LSB _u(1) -#define ACCESSCTRL_SYSINFO_NSP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_SYSINFO_NSU -// Description : If 1, and NSP is also set, SYSINFO can be accessed from a Non- -// secure, Unprivileged context. -// -// This bit is writable from a Non-secure, Privileged context, if -// and only if the NSP bit is set. -#define ACCESSCTRL_SYSINFO_NSU_RESET _u(0x1) -#define ACCESSCTRL_SYSINFO_NSU_BITS _u(0x00000001) -#define ACCESSCTRL_SYSINFO_NSU_MSB _u(0) -#define ACCESSCTRL_SYSINFO_NSU_LSB _u(0) -#define ACCESSCTRL_SYSINFO_NSU_ACCESS "RW" -// ============================================================================= -// Register : ACCESSCTRL_RESETS -// Description : Control whether debugger, DMA, core 0 and core 1 can access -// RESETS, and at what security/privilege levels they can do so. -// -// Defaults to Secure access from any master. -// -// This register is writable only from a Secure, Privileged -// processor or debugger, with the exception of the NSU bit, which -// becomes Non-secure-Privileged-writable when the NSP bit is set. -#define ACCESSCTRL_RESETS_OFFSET _u(0x00000064) -#define ACCESSCTRL_RESETS_BITS _u(0x000000ff) -#define ACCESSCTRL_RESETS_RESET _u(0x000000fc) -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_RESETS_DBG -// Description : If 1, RESETS can be accessed by the debugger, at -// security/privilege levels permitted by SP/NSP/SU/NSU in this -// register. -#define ACCESSCTRL_RESETS_DBG_RESET _u(0x1) -#define ACCESSCTRL_RESETS_DBG_BITS _u(0x00000080) -#define ACCESSCTRL_RESETS_DBG_MSB _u(7) -#define ACCESSCTRL_RESETS_DBG_LSB _u(7) -#define ACCESSCTRL_RESETS_DBG_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_RESETS_DMA -// Description : If 1, RESETS can be accessed by the DMA, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_RESETS_DMA_RESET _u(0x1) -#define ACCESSCTRL_RESETS_DMA_BITS _u(0x00000040) -#define ACCESSCTRL_RESETS_DMA_MSB _u(6) -#define ACCESSCTRL_RESETS_DMA_LSB _u(6) -#define ACCESSCTRL_RESETS_DMA_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_RESETS_CORE1 -// Description : If 1, RESETS can be accessed by core 1, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_RESETS_CORE1_RESET _u(0x1) -#define ACCESSCTRL_RESETS_CORE1_BITS _u(0x00000020) -#define ACCESSCTRL_RESETS_CORE1_MSB _u(5) -#define ACCESSCTRL_RESETS_CORE1_LSB _u(5) -#define ACCESSCTRL_RESETS_CORE1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_RESETS_CORE0 -// Description : If 1, RESETS can be accessed by core 0, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_RESETS_CORE0_RESET _u(0x1) -#define ACCESSCTRL_RESETS_CORE0_BITS _u(0x00000010) -#define ACCESSCTRL_RESETS_CORE0_MSB _u(4) -#define ACCESSCTRL_RESETS_CORE0_LSB _u(4) -#define ACCESSCTRL_RESETS_CORE0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_RESETS_SP -// Description : If 1, RESETS can be accessed from a Secure, Privileged context. -#define ACCESSCTRL_RESETS_SP_RESET _u(0x1) -#define ACCESSCTRL_RESETS_SP_BITS _u(0x00000008) -#define ACCESSCTRL_RESETS_SP_MSB _u(3) -#define ACCESSCTRL_RESETS_SP_LSB _u(3) -#define ACCESSCTRL_RESETS_SP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_RESETS_SU -// Description : If 1, and SP is also set, RESETS can be accessed from a Secure, -// Unprivileged context. -#define ACCESSCTRL_RESETS_SU_RESET _u(0x1) -#define ACCESSCTRL_RESETS_SU_BITS _u(0x00000004) -#define ACCESSCTRL_RESETS_SU_MSB _u(2) -#define ACCESSCTRL_RESETS_SU_LSB _u(2) -#define ACCESSCTRL_RESETS_SU_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_RESETS_NSP -// Description : If 1, RESETS can be accessed from a Non-secure, Privileged -// context. -#define ACCESSCTRL_RESETS_NSP_RESET _u(0x0) -#define ACCESSCTRL_RESETS_NSP_BITS _u(0x00000002) -#define ACCESSCTRL_RESETS_NSP_MSB _u(1) -#define ACCESSCTRL_RESETS_NSP_LSB _u(1) -#define ACCESSCTRL_RESETS_NSP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_RESETS_NSU -// Description : If 1, and NSP is also set, RESETS can be accessed from a Non- -// secure, Unprivileged context. -// -// This bit is writable from a Non-secure, Privileged context, if -// and only if the NSP bit is set. -#define ACCESSCTRL_RESETS_NSU_RESET _u(0x0) -#define ACCESSCTRL_RESETS_NSU_BITS _u(0x00000001) -#define ACCESSCTRL_RESETS_NSU_MSB _u(0) -#define ACCESSCTRL_RESETS_NSU_LSB _u(0) -#define ACCESSCTRL_RESETS_NSU_ACCESS "RW" -// ============================================================================= -// Register : ACCESSCTRL_IO_BANK0 -// Description : Control whether debugger, DMA, core 0 and core 1 can access -// IO_BANK0, and at what security/privilege levels they can do so. -// -// Defaults to Secure access from any master. -// -// This register is writable only from a Secure, Privileged -// processor or debugger, with the exception of the NSU bit, which -// becomes Non-secure-Privileged-writable when the NSP bit is set. -#define ACCESSCTRL_IO_BANK0_OFFSET _u(0x00000068) -#define ACCESSCTRL_IO_BANK0_BITS _u(0x000000ff) -#define ACCESSCTRL_IO_BANK0_RESET _u(0x000000fc) -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_IO_BANK0_DBG -// Description : If 1, IO_BANK0 can be accessed by the debugger, at -// security/privilege levels permitted by SP/NSP/SU/NSU in this -// register. -#define ACCESSCTRL_IO_BANK0_DBG_RESET _u(0x1) -#define ACCESSCTRL_IO_BANK0_DBG_BITS _u(0x00000080) -#define ACCESSCTRL_IO_BANK0_DBG_MSB _u(7) -#define ACCESSCTRL_IO_BANK0_DBG_LSB _u(7) -#define ACCESSCTRL_IO_BANK0_DBG_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_IO_BANK0_DMA -// Description : If 1, IO_BANK0 can be accessed by the DMA, at -// security/privilege levels permitted by SP/NSP/SU/NSU in this -// register. -#define ACCESSCTRL_IO_BANK0_DMA_RESET _u(0x1) -#define ACCESSCTRL_IO_BANK0_DMA_BITS _u(0x00000040) -#define ACCESSCTRL_IO_BANK0_DMA_MSB _u(6) -#define ACCESSCTRL_IO_BANK0_DMA_LSB _u(6) -#define ACCESSCTRL_IO_BANK0_DMA_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_IO_BANK0_CORE1 -// Description : If 1, IO_BANK0 can be accessed by core 1, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_IO_BANK0_CORE1_RESET _u(0x1) -#define ACCESSCTRL_IO_BANK0_CORE1_BITS _u(0x00000020) -#define ACCESSCTRL_IO_BANK0_CORE1_MSB _u(5) -#define ACCESSCTRL_IO_BANK0_CORE1_LSB _u(5) -#define ACCESSCTRL_IO_BANK0_CORE1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_IO_BANK0_CORE0 -// Description : If 1, IO_BANK0 can be accessed by core 0, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_IO_BANK0_CORE0_RESET _u(0x1) -#define ACCESSCTRL_IO_BANK0_CORE0_BITS _u(0x00000010) -#define ACCESSCTRL_IO_BANK0_CORE0_MSB _u(4) -#define ACCESSCTRL_IO_BANK0_CORE0_LSB _u(4) -#define ACCESSCTRL_IO_BANK0_CORE0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_IO_BANK0_SP -// Description : If 1, IO_BANK0 can be accessed from a Secure, Privileged -// context. -#define ACCESSCTRL_IO_BANK0_SP_RESET _u(0x1) -#define ACCESSCTRL_IO_BANK0_SP_BITS _u(0x00000008) -#define ACCESSCTRL_IO_BANK0_SP_MSB _u(3) -#define ACCESSCTRL_IO_BANK0_SP_LSB _u(3) -#define ACCESSCTRL_IO_BANK0_SP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_IO_BANK0_SU -// Description : If 1, and SP is also set, IO_BANK0 can be accessed from a -// Secure, Unprivileged context. -#define ACCESSCTRL_IO_BANK0_SU_RESET _u(0x1) -#define ACCESSCTRL_IO_BANK0_SU_BITS _u(0x00000004) -#define ACCESSCTRL_IO_BANK0_SU_MSB _u(2) -#define ACCESSCTRL_IO_BANK0_SU_LSB _u(2) -#define ACCESSCTRL_IO_BANK0_SU_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_IO_BANK0_NSP -// Description : If 1, IO_BANK0 can be accessed from a Non-secure, Privileged -// context. -#define ACCESSCTRL_IO_BANK0_NSP_RESET _u(0x0) -#define ACCESSCTRL_IO_BANK0_NSP_BITS _u(0x00000002) -#define ACCESSCTRL_IO_BANK0_NSP_MSB _u(1) -#define ACCESSCTRL_IO_BANK0_NSP_LSB _u(1) -#define ACCESSCTRL_IO_BANK0_NSP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_IO_BANK0_NSU -// Description : If 1, and NSP is also set, IO_BANK0 can be accessed from a Non- -// secure, Unprivileged context. -// -// This bit is writable from a Non-secure, Privileged context, if -// and only if the NSP bit is set. -#define ACCESSCTRL_IO_BANK0_NSU_RESET _u(0x0) -#define ACCESSCTRL_IO_BANK0_NSU_BITS _u(0x00000001) -#define ACCESSCTRL_IO_BANK0_NSU_MSB _u(0) -#define ACCESSCTRL_IO_BANK0_NSU_LSB _u(0) -#define ACCESSCTRL_IO_BANK0_NSU_ACCESS "RW" -// ============================================================================= -// Register : ACCESSCTRL_IO_BANK1 -// Description : Control whether debugger, DMA, core 0 and core 1 can access -// IO_BANK1, and at what security/privilege levels they can do so. -// -// Defaults to Secure access from any master. -// -// This register is writable only from a Secure, Privileged -// processor or debugger, with the exception of the NSU bit, which -// becomes Non-secure-Privileged-writable when the NSP bit is set. -#define ACCESSCTRL_IO_BANK1_OFFSET _u(0x0000006c) -#define ACCESSCTRL_IO_BANK1_BITS _u(0x000000ff) -#define ACCESSCTRL_IO_BANK1_RESET _u(0x000000fc) -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_IO_BANK1_DBG -// Description : If 1, IO_BANK1 can be accessed by the debugger, at -// security/privilege levels permitted by SP/NSP/SU/NSU in this -// register. -#define ACCESSCTRL_IO_BANK1_DBG_RESET _u(0x1) -#define ACCESSCTRL_IO_BANK1_DBG_BITS _u(0x00000080) -#define ACCESSCTRL_IO_BANK1_DBG_MSB _u(7) -#define ACCESSCTRL_IO_BANK1_DBG_LSB _u(7) -#define ACCESSCTRL_IO_BANK1_DBG_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_IO_BANK1_DMA -// Description : If 1, IO_BANK1 can be accessed by the DMA, at -// security/privilege levels permitted by SP/NSP/SU/NSU in this -// register. -#define ACCESSCTRL_IO_BANK1_DMA_RESET _u(0x1) -#define ACCESSCTRL_IO_BANK1_DMA_BITS _u(0x00000040) -#define ACCESSCTRL_IO_BANK1_DMA_MSB _u(6) -#define ACCESSCTRL_IO_BANK1_DMA_LSB _u(6) -#define ACCESSCTRL_IO_BANK1_DMA_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_IO_BANK1_CORE1 -// Description : If 1, IO_BANK1 can be accessed by core 1, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_IO_BANK1_CORE1_RESET _u(0x1) -#define ACCESSCTRL_IO_BANK1_CORE1_BITS _u(0x00000020) -#define ACCESSCTRL_IO_BANK1_CORE1_MSB _u(5) -#define ACCESSCTRL_IO_BANK1_CORE1_LSB _u(5) -#define ACCESSCTRL_IO_BANK1_CORE1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_IO_BANK1_CORE0 -// Description : If 1, IO_BANK1 can be accessed by core 0, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_IO_BANK1_CORE0_RESET _u(0x1) -#define ACCESSCTRL_IO_BANK1_CORE0_BITS _u(0x00000010) -#define ACCESSCTRL_IO_BANK1_CORE0_MSB _u(4) -#define ACCESSCTRL_IO_BANK1_CORE0_LSB _u(4) -#define ACCESSCTRL_IO_BANK1_CORE0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_IO_BANK1_SP -// Description : If 1, IO_BANK1 can be accessed from a Secure, Privileged -// context. -#define ACCESSCTRL_IO_BANK1_SP_RESET _u(0x1) -#define ACCESSCTRL_IO_BANK1_SP_BITS _u(0x00000008) -#define ACCESSCTRL_IO_BANK1_SP_MSB _u(3) -#define ACCESSCTRL_IO_BANK1_SP_LSB _u(3) -#define ACCESSCTRL_IO_BANK1_SP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_IO_BANK1_SU -// Description : If 1, and SP is also set, IO_BANK1 can be accessed from a -// Secure, Unprivileged context. -#define ACCESSCTRL_IO_BANK1_SU_RESET _u(0x1) -#define ACCESSCTRL_IO_BANK1_SU_BITS _u(0x00000004) -#define ACCESSCTRL_IO_BANK1_SU_MSB _u(2) -#define ACCESSCTRL_IO_BANK1_SU_LSB _u(2) -#define ACCESSCTRL_IO_BANK1_SU_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_IO_BANK1_NSP -// Description : If 1, IO_BANK1 can be accessed from a Non-secure, Privileged -// context. -#define ACCESSCTRL_IO_BANK1_NSP_RESET _u(0x0) -#define ACCESSCTRL_IO_BANK1_NSP_BITS _u(0x00000002) -#define ACCESSCTRL_IO_BANK1_NSP_MSB _u(1) -#define ACCESSCTRL_IO_BANK1_NSP_LSB _u(1) -#define ACCESSCTRL_IO_BANK1_NSP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_IO_BANK1_NSU -// Description : If 1, and NSP is also set, IO_BANK1 can be accessed from a Non- -// secure, Unprivileged context. -// -// This bit is writable from a Non-secure, Privileged context, if -// and only if the NSP bit is set. -#define ACCESSCTRL_IO_BANK1_NSU_RESET _u(0x0) -#define ACCESSCTRL_IO_BANK1_NSU_BITS _u(0x00000001) -#define ACCESSCTRL_IO_BANK1_NSU_MSB _u(0) -#define ACCESSCTRL_IO_BANK1_NSU_LSB _u(0) -#define ACCESSCTRL_IO_BANK1_NSU_ACCESS "RW" -// ============================================================================= -// Register : ACCESSCTRL_PADS_BANK0 -// Description : Control whether debugger, DMA, core 0 and core 1 can access -// PADS_BANK0, and at what security/privilege levels they can do -// so. -// -// Defaults to Secure access from any master. -// -// This register is writable only from a Secure, Privileged -// processor or debugger, with the exception of the NSU bit, which -// becomes Non-secure-Privileged-writable when the NSP bit is set. -#define ACCESSCTRL_PADS_BANK0_OFFSET _u(0x00000070) -#define ACCESSCTRL_PADS_BANK0_BITS _u(0x000000ff) -#define ACCESSCTRL_PADS_BANK0_RESET _u(0x000000fc) -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_PADS_BANK0_DBG -// Description : If 1, PADS_BANK0 can be accessed by the debugger, at -// security/privilege levels permitted by SP/NSP/SU/NSU in this -// register. -#define ACCESSCTRL_PADS_BANK0_DBG_RESET _u(0x1) -#define ACCESSCTRL_PADS_BANK0_DBG_BITS _u(0x00000080) -#define ACCESSCTRL_PADS_BANK0_DBG_MSB _u(7) -#define ACCESSCTRL_PADS_BANK0_DBG_LSB _u(7) -#define ACCESSCTRL_PADS_BANK0_DBG_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_PADS_BANK0_DMA -// Description : If 1, PADS_BANK0 can be accessed by the DMA, at -// security/privilege levels permitted by SP/NSP/SU/NSU in this -// register. -#define ACCESSCTRL_PADS_BANK0_DMA_RESET _u(0x1) -#define ACCESSCTRL_PADS_BANK0_DMA_BITS _u(0x00000040) -#define ACCESSCTRL_PADS_BANK0_DMA_MSB _u(6) -#define ACCESSCTRL_PADS_BANK0_DMA_LSB _u(6) -#define ACCESSCTRL_PADS_BANK0_DMA_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_PADS_BANK0_CORE1 -// Description : If 1, PADS_BANK0 can be accessed by core 1, at -// security/privilege levels permitted by SP/NSP/SU/NSU in this -// register. -#define ACCESSCTRL_PADS_BANK0_CORE1_RESET _u(0x1) -#define ACCESSCTRL_PADS_BANK0_CORE1_BITS _u(0x00000020) -#define ACCESSCTRL_PADS_BANK0_CORE1_MSB _u(5) -#define ACCESSCTRL_PADS_BANK0_CORE1_LSB _u(5) -#define ACCESSCTRL_PADS_BANK0_CORE1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_PADS_BANK0_CORE0 -// Description : If 1, PADS_BANK0 can be accessed by core 0, at -// security/privilege levels permitted by SP/NSP/SU/NSU in this -// register. -#define ACCESSCTRL_PADS_BANK0_CORE0_RESET _u(0x1) -#define ACCESSCTRL_PADS_BANK0_CORE0_BITS _u(0x00000010) -#define ACCESSCTRL_PADS_BANK0_CORE0_MSB _u(4) -#define ACCESSCTRL_PADS_BANK0_CORE0_LSB _u(4) -#define ACCESSCTRL_PADS_BANK0_CORE0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_PADS_BANK0_SP -// Description : If 1, PADS_BANK0 can be accessed from a Secure, Privileged -// context. -#define ACCESSCTRL_PADS_BANK0_SP_RESET _u(0x1) -#define ACCESSCTRL_PADS_BANK0_SP_BITS _u(0x00000008) -#define ACCESSCTRL_PADS_BANK0_SP_MSB _u(3) -#define ACCESSCTRL_PADS_BANK0_SP_LSB _u(3) -#define ACCESSCTRL_PADS_BANK0_SP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_PADS_BANK0_SU -// Description : If 1, and SP is also set, PADS_BANK0 can be accessed from a -// Secure, Unprivileged context. -#define ACCESSCTRL_PADS_BANK0_SU_RESET _u(0x1) -#define ACCESSCTRL_PADS_BANK0_SU_BITS _u(0x00000004) -#define ACCESSCTRL_PADS_BANK0_SU_MSB _u(2) -#define ACCESSCTRL_PADS_BANK0_SU_LSB _u(2) -#define ACCESSCTRL_PADS_BANK0_SU_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_PADS_BANK0_NSP -// Description : If 1, PADS_BANK0 can be accessed from a Non-secure, Privileged -// context. -#define ACCESSCTRL_PADS_BANK0_NSP_RESET _u(0x0) -#define ACCESSCTRL_PADS_BANK0_NSP_BITS _u(0x00000002) -#define ACCESSCTRL_PADS_BANK0_NSP_MSB _u(1) -#define ACCESSCTRL_PADS_BANK0_NSP_LSB _u(1) -#define ACCESSCTRL_PADS_BANK0_NSP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_PADS_BANK0_NSU -// Description : If 1, and NSP is also set, PADS_BANK0 can be accessed from a -// Non-secure, Unprivileged context. -// -// This bit is writable from a Non-secure, Privileged context, if -// and only if the NSP bit is set. -#define ACCESSCTRL_PADS_BANK0_NSU_RESET _u(0x0) -#define ACCESSCTRL_PADS_BANK0_NSU_BITS _u(0x00000001) -#define ACCESSCTRL_PADS_BANK0_NSU_MSB _u(0) -#define ACCESSCTRL_PADS_BANK0_NSU_LSB _u(0) -#define ACCESSCTRL_PADS_BANK0_NSU_ACCESS "RW" -// ============================================================================= -// Register : ACCESSCTRL_PADS_QSPI -// Description : Control whether debugger, DMA, core 0 and core 1 can access -// PADS_QSPI, and at what security/privilege levels they can do -// so. -// -// Defaults to Secure access from any master. -// -// This register is writable only from a Secure, Privileged -// processor or debugger, with the exception of the NSU bit, which -// becomes Non-secure-Privileged-writable when the NSP bit is set. -#define ACCESSCTRL_PADS_QSPI_OFFSET _u(0x00000074) -#define ACCESSCTRL_PADS_QSPI_BITS _u(0x000000ff) -#define ACCESSCTRL_PADS_QSPI_RESET _u(0x000000fc) -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_PADS_QSPI_DBG -// Description : If 1, PADS_QSPI can be accessed by the debugger, at -// security/privilege levels permitted by SP/NSP/SU/NSU in this -// register. -#define ACCESSCTRL_PADS_QSPI_DBG_RESET _u(0x1) -#define ACCESSCTRL_PADS_QSPI_DBG_BITS _u(0x00000080) -#define ACCESSCTRL_PADS_QSPI_DBG_MSB _u(7) -#define ACCESSCTRL_PADS_QSPI_DBG_LSB _u(7) -#define ACCESSCTRL_PADS_QSPI_DBG_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_PADS_QSPI_DMA -// Description : If 1, PADS_QSPI can be accessed by the DMA, at -// security/privilege levels permitted by SP/NSP/SU/NSU in this -// register. -#define ACCESSCTRL_PADS_QSPI_DMA_RESET _u(0x1) -#define ACCESSCTRL_PADS_QSPI_DMA_BITS _u(0x00000040) -#define ACCESSCTRL_PADS_QSPI_DMA_MSB _u(6) -#define ACCESSCTRL_PADS_QSPI_DMA_LSB _u(6) -#define ACCESSCTRL_PADS_QSPI_DMA_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_PADS_QSPI_CORE1 -// Description : If 1, PADS_QSPI can be accessed by core 1, at -// security/privilege levels permitted by SP/NSP/SU/NSU in this -// register. -#define ACCESSCTRL_PADS_QSPI_CORE1_RESET _u(0x1) -#define ACCESSCTRL_PADS_QSPI_CORE1_BITS _u(0x00000020) -#define ACCESSCTRL_PADS_QSPI_CORE1_MSB _u(5) -#define ACCESSCTRL_PADS_QSPI_CORE1_LSB _u(5) -#define ACCESSCTRL_PADS_QSPI_CORE1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_PADS_QSPI_CORE0 -// Description : If 1, PADS_QSPI can be accessed by core 0, at -// security/privilege levels permitted by SP/NSP/SU/NSU in this -// register. -#define ACCESSCTRL_PADS_QSPI_CORE0_RESET _u(0x1) -#define ACCESSCTRL_PADS_QSPI_CORE0_BITS _u(0x00000010) -#define ACCESSCTRL_PADS_QSPI_CORE0_MSB _u(4) -#define ACCESSCTRL_PADS_QSPI_CORE0_LSB _u(4) -#define ACCESSCTRL_PADS_QSPI_CORE0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_PADS_QSPI_SP -// Description : If 1, PADS_QSPI can be accessed from a Secure, Privileged -// context. -#define ACCESSCTRL_PADS_QSPI_SP_RESET _u(0x1) -#define ACCESSCTRL_PADS_QSPI_SP_BITS _u(0x00000008) -#define ACCESSCTRL_PADS_QSPI_SP_MSB _u(3) -#define ACCESSCTRL_PADS_QSPI_SP_LSB _u(3) -#define ACCESSCTRL_PADS_QSPI_SP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_PADS_QSPI_SU -// Description : If 1, and SP is also set, PADS_QSPI can be accessed from a -// Secure, Unprivileged context. -#define ACCESSCTRL_PADS_QSPI_SU_RESET _u(0x1) -#define ACCESSCTRL_PADS_QSPI_SU_BITS _u(0x00000004) -#define ACCESSCTRL_PADS_QSPI_SU_MSB _u(2) -#define ACCESSCTRL_PADS_QSPI_SU_LSB _u(2) -#define ACCESSCTRL_PADS_QSPI_SU_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_PADS_QSPI_NSP -// Description : If 1, PADS_QSPI can be accessed from a Non-secure, Privileged -// context. -#define ACCESSCTRL_PADS_QSPI_NSP_RESET _u(0x0) -#define ACCESSCTRL_PADS_QSPI_NSP_BITS _u(0x00000002) -#define ACCESSCTRL_PADS_QSPI_NSP_MSB _u(1) -#define ACCESSCTRL_PADS_QSPI_NSP_LSB _u(1) -#define ACCESSCTRL_PADS_QSPI_NSP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_PADS_QSPI_NSU -// Description : If 1, and NSP is also set, PADS_QSPI can be accessed from a -// Non-secure, Unprivileged context. -// -// This bit is writable from a Non-secure, Privileged context, if -// and only if the NSP bit is set. -#define ACCESSCTRL_PADS_QSPI_NSU_RESET _u(0x0) -#define ACCESSCTRL_PADS_QSPI_NSU_BITS _u(0x00000001) -#define ACCESSCTRL_PADS_QSPI_NSU_MSB _u(0) -#define ACCESSCTRL_PADS_QSPI_NSU_LSB _u(0) -#define ACCESSCTRL_PADS_QSPI_NSU_ACCESS "RW" -// ============================================================================= -// Register : ACCESSCTRL_BUSCTRL -// Description : Control whether debugger, DMA, core 0 and core 1 can access -// BUSCTRL, and at what security/privilege levels they can do so. -// -// Defaults to Secure access from any master. -// -// This register is writable only from a Secure, Privileged -// processor or debugger, with the exception of the NSU bit, which -// becomes Non-secure-Privileged-writable when the NSP bit is set. -#define ACCESSCTRL_BUSCTRL_OFFSET _u(0x00000078) -#define ACCESSCTRL_BUSCTRL_BITS _u(0x000000ff) -#define ACCESSCTRL_BUSCTRL_RESET _u(0x000000fc) -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_BUSCTRL_DBG -// Description : If 1, BUSCTRL can be accessed by the debugger, at -// security/privilege levels permitted by SP/NSP/SU/NSU in this -// register. -#define ACCESSCTRL_BUSCTRL_DBG_RESET _u(0x1) -#define ACCESSCTRL_BUSCTRL_DBG_BITS _u(0x00000080) -#define ACCESSCTRL_BUSCTRL_DBG_MSB _u(7) -#define ACCESSCTRL_BUSCTRL_DBG_LSB _u(7) -#define ACCESSCTRL_BUSCTRL_DBG_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_BUSCTRL_DMA -// Description : If 1, BUSCTRL can be accessed by the DMA, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_BUSCTRL_DMA_RESET _u(0x1) -#define ACCESSCTRL_BUSCTRL_DMA_BITS _u(0x00000040) -#define ACCESSCTRL_BUSCTRL_DMA_MSB _u(6) -#define ACCESSCTRL_BUSCTRL_DMA_LSB _u(6) -#define ACCESSCTRL_BUSCTRL_DMA_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_BUSCTRL_CORE1 -// Description : If 1, BUSCTRL can be accessed by core 1, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_BUSCTRL_CORE1_RESET _u(0x1) -#define ACCESSCTRL_BUSCTRL_CORE1_BITS _u(0x00000020) -#define ACCESSCTRL_BUSCTRL_CORE1_MSB _u(5) -#define ACCESSCTRL_BUSCTRL_CORE1_LSB _u(5) -#define ACCESSCTRL_BUSCTRL_CORE1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_BUSCTRL_CORE0 -// Description : If 1, BUSCTRL can be accessed by core 0, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_BUSCTRL_CORE0_RESET _u(0x1) -#define ACCESSCTRL_BUSCTRL_CORE0_BITS _u(0x00000010) -#define ACCESSCTRL_BUSCTRL_CORE0_MSB _u(4) -#define ACCESSCTRL_BUSCTRL_CORE0_LSB _u(4) -#define ACCESSCTRL_BUSCTRL_CORE0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_BUSCTRL_SP -// Description : If 1, BUSCTRL can be accessed from a Secure, Privileged -// context. -#define ACCESSCTRL_BUSCTRL_SP_RESET _u(0x1) -#define ACCESSCTRL_BUSCTRL_SP_BITS _u(0x00000008) -#define ACCESSCTRL_BUSCTRL_SP_MSB _u(3) -#define ACCESSCTRL_BUSCTRL_SP_LSB _u(3) -#define ACCESSCTRL_BUSCTRL_SP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_BUSCTRL_SU -// Description : If 1, and SP is also set, BUSCTRL can be accessed from a -// Secure, Unprivileged context. -#define ACCESSCTRL_BUSCTRL_SU_RESET _u(0x1) -#define ACCESSCTRL_BUSCTRL_SU_BITS _u(0x00000004) -#define ACCESSCTRL_BUSCTRL_SU_MSB _u(2) -#define ACCESSCTRL_BUSCTRL_SU_LSB _u(2) -#define ACCESSCTRL_BUSCTRL_SU_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_BUSCTRL_NSP -// Description : If 1, BUSCTRL can be accessed from a Non-secure, Privileged -// context. -#define ACCESSCTRL_BUSCTRL_NSP_RESET _u(0x0) -#define ACCESSCTRL_BUSCTRL_NSP_BITS _u(0x00000002) -#define ACCESSCTRL_BUSCTRL_NSP_MSB _u(1) -#define ACCESSCTRL_BUSCTRL_NSP_LSB _u(1) -#define ACCESSCTRL_BUSCTRL_NSP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_BUSCTRL_NSU -// Description : If 1, and NSP is also set, BUSCTRL can be accessed from a Non- -// secure, Unprivileged context. -// -// This bit is writable from a Non-secure, Privileged context, if -// and only if the NSP bit is set. -#define ACCESSCTRL_BUSCTRL_NSU_RESET _u(0x0) -#define ACCESSCTRL_BUSCTRL_NSU_BITS _u(0x00000001) -#define ACCESSCTRL_BUSCTRL_NSU_MSB _u(0) -#define ACCESSCTRL_BUSCTRL_NSU_LSB _u(0) -#define ACCESSCTRL_BUSCTRL_NSU_ACCESS "RW" -// ============================================================================= -// Register : ACCESSCTRL_ADC0 -// Description : Control whether debugger, DMA, core 0 and core 1 can access -// ADC0, and at what security/privilege levels they can do so. -// -// Defaults to Secure access from any master. -// -// This register is writable only from a Secure, Privileged -// processor or debugger, with the exception of the NSU bit, which -// becomes Non-secure-Privileged-writable when the NSP bit is set. -#define ACCESSCTRL_ADC0_OFFSET _u(0x0000007c) -#define ACCESSCTRL_ADC0_BITS _u(0x000000ff) -#define ACCESSCTRL_ADC0_RESET _u(0x000000fc) -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_ADC0_DBG -// Description : If 1, ADC0 can be accessed by the debugger, at -// security/privilege levels permitted by SP/NSP/SU/NSU in this -// register. -#define ACCESSCTRL_ADC0_DBG_RESET _u(0x1) -#define ACCESSCTRL_ADC0_DBG_BITS _u(0x00000080) -#define ACCESSCTRL_ADC0_DBG_MSB _u(7) -#define ACCESSCTRL_ADC0_DBG_LSB _u(7) -#define ACCESSCTRL_ADC0_DBG_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_ADC0_DMA -// Description : If 1, ADC0 can be accessed by the DMA, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_ADC0_DMA_RESET _u(0x1) -#define ACCESSCTRL_ADC0_DMA_BITS _u(0x00000040) -#define ACCESSCTRL_ADC0_DMA_MSB _u(6) -#define ACCESSCTRL_ADC0_DMA_LSB _u(6) -#define ACCESSCTRL_ADC0_DMA_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_ADC0_CORE1 -// Description : If 1, ADC0 can be accessed by core 1, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_ADC0_CORE1_RESET _u(0x1) -#define ACCESSCTRL_ADC0_CORE1_BITS _u(0x00000020) -#define ACCESSCTRL_ADC0_CORE1_MSB _u(5) -#define ACCESSCTRL_ADC0_CORE1_LSB _u(5) -#define ACCESSCTRL_ADC0_CORE1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_ADC0_CORE0 -// Description : If 1, ADC0 can be accessed by core 0, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_ADC0_CORE0_RESET _u(0x1) -#define ACCESSCTRL_ADC0_CORE0_BITS _u(0x00000010) -#define ACCESSCTRL_ADC0_CORE0_MSB _u(4) -#define ACCESSCTRL_ADC0_CORE0_LSB _u(4) -#define ACCESSCTRL_ADC0_CORE0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_ADC0_SP -// Description : If 1, ADC0 can be accessed from a Secure, Privileged context. -#define ACCESSCTRL_ADC0_SP_RESET _u(0x1) -#define ACCESSCTRL_ADC0_SP_BITS _u(0x00000008) -#define ACCESSCTRL_ADC0_SP_MSB _u(3) -#define ACCESSCTRL_ADC0_SP_LSB _u(3) -#define ACCESSCTRL_ADC0_SP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_ADC0_SU -// Description : If 1, and SP is also set, ADC0 can be accessed from a Secure, -// Unprivileged context. -#define ACCESSCTRL_ADC0_SU_RESET _u(0x1) -#define ACCESSCTRL_ADC0_SU_BITS _u(0x00000004) -#define ACCESSCTRL_ADC0_SU_MSB _u(2) -#define ACCESSCTRL_ADC0_SU_LSB _u(2) -#define ACCESSCTRL_ADC0_SU_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_ADC0_NSP -// Description : If 1, ADC0 can be accessed from a Non-secure, Privileged -// context. -#define ACCESSCTRL_ADC0_NSP_RESET _u(0x0) -#define ACCESSCTRL_ADC0_NSP_BITS _u(0x00000002) -#define ACCESSCTRL_ADC0_NSP_MSB _u(1) -#define ACCESSCTRL_ADC0_NSP_LSB _u(1) -#define ACCESSCTRL_ADC0_NSP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_ADC0_NSU -// Description : If 1, and NSP is also set, ADC0 can be accessed from a Non- -// secure, Unprivileged context. -// -// This bit is writable from a Non-secure, Privileged context, if -// and only if the NSP bit is set. -#define ACCESSCTRL_ADC0_NSU_RESET _u(0x0) -#define ACCESSCTRL_ADC0_NSU_BITS _u(0x00000001) -#define ACCESSCTRL_ADC0_NSU_MSB _u(0) -#define ACCESSCTRL_ADC0_NSU_LSB _u(0) -#define ACCESSCTRL_ADC0_NSU_ACCESS "RW" -// ============================================================================= -// Register : ACCESSCTRL_HSTX -// Description : Control whether debugger, DMA, core 0 and core 1 can access -// HSTX, and at what security/privilege levels they can do so. -// -// Defaults to Secure access from any master. -// -// This register is writable only from a Secure, Privileged -// processor or debugger, with the exception of the NSU bit, which -// becomes Non-secure-Privileged-writable when the NSP bit is set. -#define ACCESSCTRL_HSTX_OFFSET _u(0x00000080) -#define ACCESSCTRL_HSTX_BITS _u(0x000000ff) -#define ACCESSCTRL_HSTX_RESET _u(0x000000fc) -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_HSTX_DBG -// Description : If 1, HSTX can be accessed by the debugger, at -// security/privilege levels permitted by SP/NSP/SU/NSU in this -// register. -#define ACCESSCTRL_HSTX_DBG_RESET _u(0x1) -#define ACCESSCTRL_HSTX_DBG_BITS _u(0x00000080) -#define ACCESSCTRL_HSTX_DBG_MSB _u(7) -#define ACCESSCTRL_HSTX_DBG_LSB _u(7) -#define ACCESSCTRL_HSTX_DBG_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_HSTX_DMA -// Description : If 1, HSTX can be accessed by the DMA, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_HSTX_DMA_RESET _u(0x1) -#define ACCESSCTRL_HSTX_DMA_BITS _u(0x00000040) -#define ACCESSCTRL_HSTX_DMA_MSB _u(6) -#define ACCESSCTRL_HSTX_DMA_LSB _u(6) -#define ACCESSCTRL_HSTX_DMA_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_HSTX_CORE1 -// Description : If 1, HSTX can be accessed by core 1, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_HSTX_CORE1_RESET _u(0x1) -#define ACCESSCTRL_HSTX_CORE1_BITS _u(0x00000020) -#define ACCESSCTRL_HSTX_CORE1_MSB _u(5) -#define ACCESSCTRL_HSTX_CORE1_LSB _u(5) -#define ACCESSCTRL_HSTX_CORE1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_HSTX_CORE0 -// Description : If 1, HSTX can be accessed by core 0, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_HSTX_CORE0_RESET _u(0x1) -#define ACCESSCTRL_HSTX_CORE0_BITS _u(0x00000010) -#define ACCESSCTRL_HSTX_CORE0_MSB _u(4) -#define ACCESSCTRL_HSTX_CORE0_LSB _u(4) -#define ACCESSCTRL_HSTX_CORE0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_HSTX_SP -// Description : If 1, HSTX can be accessed from a Secure, Privileged context. -#define ACCESSCTRL_HSTX_SP_RESET _u(0x1) -#define ACCESSCTRL_HSTX_SP_BITS _u(0x00000008) -#define ACCESSCTRL_HSTX_SP_MSB _u(3) -#define ACCESSCTRL_HSTX_SP_LSB _u(3) -#define ACCESSCTRL_HSTX_SP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_HSTX_SU -// Description : If 1, and SP is also set, HSTX can be accessed from a Secure, -// Unprivileged context. -#define ACCESSCTRL_HSTX_SU_RESET _u(0x1) -#define ACCESSCTRL_HSTX_SU_BITS _u(0x00000004) -#define ACCESSCTRL_HSTX_SU_MSB _u(2) -#define ACCESSCTRL_HSTX_SU_LSB _u(2) -#define ACCESSCTRL_HSTX_SU_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_HSTX_NSP -// Description : If 1, HSTX can be accessed from a Non-secure, Privileged -// context. -#define ACCESSCTRL_HSTX_NSP_RESET _u(0x0) -#define ACCESSCTRL_HSTX_NSP_BITS _u(0x00000002) -#define ACCESSCTRL_HSTX_NSP_MSB _u(1) -#define ACCESSCTRL_HSTX_NSP_LSB _u(1) -#define ACCESSCTRL_HSTX_NSP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_HSTX_NSU -// Description : If 1, and NSP is also set, HSTX can be accessed from a Non- -// secure, Unprivileged context. -// -// This bit is writable from a Non-secure, Privileged context, if -// and only if the NSP bit is set. -#define ACCESSCTRL_HSTX_NSU_RESET _u(0x0) -#define ACCESSCTRL_HSTX_NSU_BITS _u(0x00000001) -#define ACCESSCTRL_HSTX_NSU_MSB _u(0) -#define ACCESSCTRL_HSTX_NSU_LSB _u(0) -#define ACCESSCTRL_HSTX_NSU_ACCESS "RW" -// ============================================================================= -// Register : ACCESSCTRL_I2C0 -// Description : Control whether debugger, DMA, core 0 and core 1 can access -// I2C0, and at what security/privilege levels they can do so. -// -// Defaults to Secure access from any master. -// -// This register is writable only from a Secure, Privileged -// processor or debugger, with the exception of the NSU bit, which -// becomes Non-secure-Privileged-writable when the NSP bit is set. -#define ACCESSCTRL_I2C0_OFFSET _u(0x00000084) -#define ACCESSCTRL_I2C0_BITS _u(0x000000ff) -#define ACCESSCTRL_I2C0_RESET _u(0x000000fc) -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_I2C0_DBG -// Description : If 1, I2C0 can be accessed by the debugger, at -// security/privilege levels permitted by SP/NSP/SU/NSU in this -// register. -#define ACCESSCTRL_I2C0_DBG_RESET _u(0x1) -#define ACCESSCTRL_I2C0_DBG_BITS _u(0x00000080) -#define ACCESSCTRL_I2C0_DBG_MSB _u(7) -#define ACCESSCTRL_I2C0_DBG_LSB _u(7) -#define ACCESSCTRL_I2C0_DBG_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_I2C0_DMA -// Description : If 1, I2C0 can be accessed by the DMA, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_I2C0_DMA_RESET _u(0x1) -#define ACCESSCTRL_I2C0_DMA_BITS _u(0x00000040) -#define ACCESSCTRL_I2C0_DMA_MSB _u(6) -#define ACCESSCTRL_I2C0_DMA_LSB _u(6) -#define ACCESSCTRL_I2C0_DMA_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_I2C0_CORE1 -// Description : If 1, I2C0 can be accessed by core 1, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_I2C0_CORE1_RESET _u(0x1) -#define ACCESSCTRL_I2C0_CORE1_BITS _u(0x00000020) -#define ACCESSCTRL_I2C0_CORE1_MSB _u(5) -#define ACCESSCTRL_I2C0_CORE1_LSB _u(5) -#define ACCESSCTRL_I2C0_CORE1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_I2C0_CORE0 -// Description : If 1, I2C0 can be accessed by core 0, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_I2C0_CORE0_RESET _u(0x1) -#define ACCESSCTRL_I2C0_CORE0_BITS _u(0x00000010) -#define ACCESSCTRL_I2C0_CORE0_MSB _u(4) -#define ACCESSCTRL_I2C0_CORE0_LSB _u(4) -#define ACCESSCTRL_I2C0_CORE0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_I2C0_SP -// Description : If 1, I2C0 can be accessed from a Secure, Privileged context. -#define ACCESSCTRL_I2C0_SP_RESET _u(0x1) -#define ACCESSCTRL_I2C0_SP_BITS _u(0x00000008) -#define ACCESSCTRL_I2C0_SP_MSB _u(3) -#define ACCESSCTRL_I2C0_SP_LSB _u(3) -#define ACCESSCTRL_I2C0_SP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_I2C0_SU -// Description : If 1, and SP is also set, I2C0 can be accessed from a Secure, -// Unprivileged context. -#define ACCESSCTRL_I2C0_SU_RESET _u(0x1) -#define ACCESSCTRL_I2C0_SU_BITS _u(0x00000004) -#define ACCESSCTRL_I2C0_SU_MSB _u(2) -#define ACCESSCTRL_I2C0_SU_LSB _u(2) -#define ACCESSCTRL_I2C0_SU_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_I2C0_NSP -// Description : If 1, I2C0 can be accessed from a Non-secure, Privileged -// context. -#define ACCESSCTRL_I2C0_NSP_RESET _u(0x0) -#define ACCESSCTRL_I2C0_NSP_BITS _u(0x00000002) -#define ACCESSCTRL_I2C0_NSP_MSB _u(1) -#define ACCESSCTRL_I2C0_NSP_LSB _u(1) -#define ACCESSCTRL_I2C0_NSP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_I2C0_NSU -// Description : If 1, and NSP is also set, I2C0 can be accessed from a Non- -// secure, Unprivileged context. -// -// This bit is writable from a Non-secure, Privileged context, if -// and only if the NSP bit is set. -#define ACCESSCTRL_I2C0_NSU_RESET _u(0x0) -#define ACCESSCTRL_I2C0_NSU_BITS _u(0x00000001) -#define ACCESSCTRL_I2C0_NSU_MSB _u(0) -#define ACCESSCTRL_I2C0_NSU_LSB _u(0) -#define ACCESSCTRL_I2C0_NSU_ACCESS "RW" -// ============================================================================= -// Register : ACCESSCTRL_I2C1 -// Description : Control whether debugger, DMA, core 0 and core 1 can access -// I2C1, and at what security/privilege levels they can do so. -// -// Defaults to Secure access from any master. -// -// This register is writable only from a Secure, Privileged -// processor or debugger, with the exception of the NSU bit, which -// becomes Non-secure-Privileged-writable when the NSP bit is set. -#define ACCESSCTRL_I2C1_OFFSET _u(0x00000088) -#define ACCESSCTRL_I2C1_BITS _u(0x000000ff) -#define ACCESSCTRL_I2C1_RESET _u(0x000000fc) -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_I2C1_DBG -// Description : If 1, I2C1 can be accessed by the debugger, at -// security/privilege levels permitted by SP/NSP/SU/NSU in this -// register. -#define ACCESSCTRL_I2C1_DBG_RESET _u(0x1) -#define ACCESSCTRL_I2C1_DBG_BITS _u(0x00000080) -#define ACCESSCTRL_I2C1_DBG_MSB _u(7) -#define ACCESSCTRL_I2C1_DBG_LSB _u(7) -#define ACCESSCTRL_I2C1_DBG_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_I2C1_DMA -// Description : If 1, I2C1 can be accessed by the DMA, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_I2C1_DMA_RESET _u(0x1) -#define ACCESSCTRL_I2C1_DMA_BITS _u(0x00000040) -#define ACCESSCTRL_I2C1_DMA_MSB _u(6) -#define ACCESSCTRL_I2C1_DMA_LSB _u(6) -#define ACCESSCTRL_I2C1_DMA_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_I2C1_CORE1 -// Description : If 1, I2C1 can be accessed by core 1, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_I2C1_CORE1_RESET _u(0x1) -#define ACCESSCTRL_I2C1_CORE1_BITS _u(0x00000020) -#define ACCESSCTRL_I2C1_CORE1_MSB _u(5) -#define ACCESSCTRL_I2C1_CORE1_LSB _u(5) -#define ACCESSCTRL_I2C1_CORE1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_I2C1_CORE0 -// Description : If 1, I2C1 can be accessed by core 0, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_I2C1_CORE0_RESET _u(0x1) -#define ACCESSCTRL_I2C1_CORE0_BITS _u(0x00000010) -#define ACCESSCTRL_I2C1_CORE0_MSB _u(4) -#define ACCESSCTRL_I2C1_CORE0_LSB _u(4) -#define ACCESSCTRL_I2C1_CORE0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_I2C1_SP -// Description : If 1, I2C1 can be accessed from a Secure, Privileged context. -#define ACCESSCTRL_I2C1_SP_RESET _u(0x1) -#define ACCESSCTRL_I2C1_SP_BITS _u(0x00000008) -#define ACCESSCTRL_I2C1_SP_MSB _u(3) -#define ACCESSCTRL_I2C1_SP_LSB _u(3) -#define ACCESSCTRL_I2C1_SP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_I2C1_SU -// Description : If 1, and SP is also set, I2C1 can be accessed from a Secure, -// Unprivileged context. -#define ACCESSCTRL_I2C1_SU_RESET _u(0x1) -#define ACCESSCTRL_I2C1_SU_BITS _u(0x00000004) -#define ACCESSCTRL_I2C1_SU_MSB _u(2) -#define ACCESSCTRL_I2C1_SU_LSB _u(2) -#define ACCESSCTRL_I2C1_SU_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_I2C1_NSP -// Description : If 1, I2C1 can be accessed from a Non-secure, Privileged -// context. -#define ACCESSCTRL_I2C1_NSP_RESET _u(0x0) -#define ACCESSCTRL_I2C1_NSP_BITS _u(0x00000002) -#define ACCESSCTRL_I2C1_NSP_MSB _u(1) -#define ACCESSCTRL_I2C1_NSP_LSB _u(1) -#define ACCESSCTRL_I2C1_NSP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_I2C1_NSU -// Description : If 1, and NSP is also set, I2C1 can be accessed from a Non- -// secure, Unprivileged context. -// -// This bit is writable from a Non-secure, Privileged context, if -// and only if the NSP bit is set. -#define ACCESSCTRL_I2C1_NSU_RESET _u(0x0) -#define ACCESSCTRL_I2C1_NSU_BITS _u(0x00000001) -#define ACCESSCTRL_I2C1_NSU_MSB _u(0) -#define ACCESSCTRL_I2C1_NSU_LSB _u(0) -#define ACCESSCTRL_I2C1_NSU_ACCESS "RW" -// ============================================================================= -// Register : ACCESSCTRL_PWM -// Description : Control whether debugger, DMA, core 0 and core 1 can access -// PWM, and at what security/privilege levels they can do so. -// -// Defaults to Secure access from any master. -// -// This register is writable only from a Secure, Privileged -// processor or debugger, with the exception of the NSU bit, which -// becomes Non-secure-Privileged-writable when the NSP bit is set. -#define ACCESSCTRL_PWM_OFFSET _u(0x0000008c) -#define ACCESSCTRL_PWM_BITS _u(0x000000ff) -#define ACCESSCTRL_PWM_RESET _u(0x000000fc) -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_PWM_DBG -// Description : If 1, PWM can be accessed by the debugger, at -// security/privilege levels permitted by SP/NSP/SU/NSU in this -// register. -#define ACCESSCTRL_PWM_DBG_RESET _u(0x1) -#define ACCESSCTRL_PWM_DBG_BITS _u(0x00000080) -#define ACCESSCTRL_PWM_DBG_MSB _u(7) -#define ACCESSCTRL_PWM_DBG_LSB _u(7) -#define ACCESSCTRL_PWM_DBG_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_PWM_DMA -// Description : If 1, PWM can be accessed by the DMA, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_PWM_DMA_RESET _u(0x1) -#define ACCESSCTRL_PWM_DMA_BITS _u(0x00000040) -#define ACCESSCTRL_PWM_DMA_MSB _u(6) -#define ACCESSCTRL_PWM_DMA_LSB _u(6) -#define ACCESSCTRL_PWM_DMA_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_PWM_CORE1 -// Description : If 1, PWM can be accessed by core 1, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_PWM_CORE1_RESET _u(0x1) -#define ACCESSCTRL_PWM_CORE1_BITS _u(0x00000020) -#define ACCESSCTRL_PWM_CORE1_MSB _u(5) -#define ACCESSCTRL_PWM_CORE1_LSB _u(5) -#define ACCESSCTRL_PWM_CORE1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_PWM_CORE0 -// Description : If 1, PWM can be accessed by core 0, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_PWM_CORE0_RESET _u(0x1) -#define ACCESSCTRL_PWM_CORE0_BITS _u(0x00000010) -#define ACCESSCTRL_PWM_CORE0_MSB _u(4) -#define ACCESSCTRL_PWM_CORE0_LSB _u(4) -#define ACCESSCTRL_PWM_CORE0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_PWM_SP -// Description : If 1, PWM can be accessed from a Secure, Privileged context. -#define ACCESSCTRL_PWM_SP_RESET _u(0x1) -#define ACCESSCTRL_PWM_SP_BITS _u(0x00000008) -#define ACCESSCTRL_PWM_SP_MSB _u(3) -#define ACCESSCTRL_PWM_SP_LSB _u(3) -#define ACCESSCTRL_PWM_SP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_PWM_SU -// Description : If 1, and SP is also set, PWM can be accessed from a Secure, -// Unprivileged context. -#define ACCESSCTRL_PWM_SU_RESET _u(0x1) -#define ACCESSCTRL_PWM_SU_BITS _u(0x00000004) -#define ACCESSCTRL_PWM_SU_MSB _u(2) -#define ACCESSCTRL_PWM_SU_LSB _u(2) -#define ACCESSCTRL_PWM_SU_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_PWM_NSP -// Description : If 1, PWM can be accessed from a Non-secure, Privileged -// context. -#define ACCESSCTRL_PWM_NSP_RESET _u(0x0) -#define ACCESSCTRL_PWM_NSP_BITS _u(0x00000002) -#define ACCESSCTRL_PWM_NSP_MSB _u(1) -#define ACCESSCTRL_PWM_NSP_LSB _u(1) -#define ACCESSCTRL_PWM_NSP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_PWM_NSU -// Description : If 1, and NSP is also set, PWM can be accessed from a Non- -// secure, Unprivileged context. -// -// This bit is writable from a Non-secure, Privileged context, if -// and only if the NSP bit is set. -#define ACCESSCTRL_PWM_NSU_RESET _u(0x0) -#define ACCESSCTRL_PWM_NSU_BITS _u(0x00000001) -#define ACCESSCTRL_PWM_NSU_MSB _u(0) -#define ACCESSCTRL_PWM_NSU_LSB _u(0) -#define ACCESSCTRL_PWM_NSU_ACCESS "RW" -// ============================================================================= -// Register : ACCESSCTRL_SPI0 -// Description : Control whether debugger, DMA, core 0 and core 1 can access -// SPI0, and at what security/privilege levels they can do so. -// -// Defaults to Secure access from any master. -// -// This register is writable only from a Secure, Privileged -// processor or debugger, with the exception of the NSU bit, which -// becomes Non-secure-Privileged-writable when the NSP bit is set. -#define ACCESSCTRL_SPI0_OFFSET _u(0x00000090) -#define ACCESSCTRL_SPI0_BITS _u(0x000000ff) -#define ACCESSCTRL_SPI0_RESET _u(0x000000fc) -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_SPI0_DBG -// Description : If 1, SPI0 can be accessed by the debugger, at -// security/privilege levels permitted by SP/NSP/SU/NSU in this -// register. -#define ACCESSCTRL_SPI0_DBG_RESET _u(0x1) -#define ACCESSCTRL_SPI0_DBG_BITS _u(0x00000080) -#define ACCESSCTRL_SPI0_DBG_MSB _u(7) -#define ACCESSCTRL_SPI0_DBG_LSB _u(7) -#define ACCESSCTRL_SPI0_DBG_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_SPI0_DMA -// Description : If 1, SPI0 can be accessed by the DMA, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_SPI0_DMA_RESET _u(0x1) -#define ACCESSCTRL_SPI0_DMA_BITS _u(0x00000040) -#define ACCESSCTRL_SPI0_DMA_MSB _u(6) -#define ACCESSCTRL_SPI0_DMA_LSB _u(6) -#define ACCESSCTRL_SPI0_DMA_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_SPI0_CORE1 -// Description : If 1, SPI0 can be accessed by core 1, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_SPI0_CORE1_RESET _u(0x1) -#define ACCESSCTRL_SPI0_CORE1_BITS _u(0x00000020) -#define ACCESSCTRL_SPI0_CORE1_MSB _u(5) -#define ACCESSCTRL_SPI0_CORE1_LSB _u(5) -#define ACCESSCTRL_SPI0_CORE1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_SPI0_CORE0 -// Description : If 1, SPI0 can be accessed by core 0, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_SPI0_CORE0_RESET _u(0x1) -#define ACCESSCTRL_SPI0_CORE0_BITS _u(0x00000010) -#define ACCESSCTRL_SPI0_CORE0_MSB _u(4) -#define ACCESSCTRL_SPI0_CORE0_LSB _u(4) -#define ACCESSCTRL_SPI0_CORE0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_SPI0_SP -// Description : If 1, SPI0 can be accessed from a Secure, Privileged context. -#define ACCESSCTRL_SPI0_SP_RESET _u(0x1) -#define ACCESSCTRL_SPI0_SP_BITS _u(0x00000008) -#define ACCESSCTRL_SPI0_SP_MSB _u(3) -#define ACCESSCTRL_SPI0_SP_LSB _u(3) -#define ACCESSCTRL_SPI0_SP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_SPI0_SU -// Description : If 1, and SP is also set, SPI0 can be accessed from a Secure, -// Unprivileged context. -#define ACCESSCTRL_SPI0_SU_RESET _u(0x1) -#define ACCESSCTRL_SPI0_SU_BITS _u(0x00000004) -#define ACCESSCTRL_SPI0_SU_MSB _u(2) -#define ACCESSCTRL_SPI0_SU_LSB _u(2) -#define ACCESSCTRL_SPI0_SU_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_SPI0_NSP -// Description : If 1, SPI0 can be accessed from a Non-secure, Privileged -// context. -#define ACCESSCTRL_SPI0_NSP_RESET _u(0x0) -#define ACCESSCTRL_SPI0_NSP_BITS _u(0x00000002) -#define ACCESSCTRL_SPI0_NSP_MSB _u(1) -#define ACCESSCTRL_SPI0_NSP_LSB _u(1) -#define ACCESSCTRL_SPI0_NSP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_SPI0_NSU -// Description : If 1, and NSP is also set, SPI0 can be accessed from a Non- -// secure, Unprivileged context. -// -// This bit is writable from a Non-secure, Privileged context, if -// and only if the NSP bit is set. -#define ACCESSCTRL_SPI0_NSU_RESET _u(0x0) -#define ACCESSCTRL_SPI0_NSU_BITS _u(0x00000001) -#define ACCESSCTRL_SPI0_NSU_MSB _u(0) -#define ACCESSCTRL_SPI0_NSU_LSB _u(0) -#define ACCESSCTRL_SPI0_NSU_ACCESS "RW" -// ============================================================================= -// Register : ACCESSCTRL_SPI1 -// Description : Control whether debugger, DMA, core 0 and core 1 can access -// SPI1, and at what security/privilege levels they can do so. -// -// Defaults to Secure access from any master. -// -// This register is writable only from a Secure, Privileged -// processor or debugger, with the exception of the NSU bit, which -// becomes Non-secure-Privileged-writable when the NSP bit is set. -#define ACCESSCTRL_SPI1_OFFSET _u(0x00000094) -#define ACCESSCTRL_SPI1_BITS _u(0x000000ff) -#define ACCESSCTRL_SPI1_RESET _u(0x000000fc) -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_SPI1_DBG -// Description : If 1, SPI1 can be accessed by the debugger, at -// security/privilege levels permitted by SP/NSP/SU/NSU in this -// register. -#define ACCESSCTRL_SPI1_DBG_RESET _u(0x1) -#define ACCESSCTRL_SPI1_DBG_BITS _u(0x00000080) -#define ACCESSCTRL_SPI1_DBG_MSB _u(7) -#define ACCESSCTRL_SPI1_DBG_LSB _u(7) -#define ACCESSCTRL_SPI1_DBG_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_SPI1_DMA -// Description : If 1, SPI1 can be accessed by the DMA, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_SPI1_DMA_RESET _u(0x1) -#define ACCESSCTRL_SPI1_DMA_BITS _u(0x00000040) -#define ACCESSCTRL_SPI1_DMA_MSB _u(6) -#define ACCESSCTRL_SPI1_DMA_LSB _u(6) -#define ACCESSCTRL_SPI1_DMA_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_SPI1_CORE1 -// Description : If 1, SPI1 can be accessed by core 1, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_SPI1_CORE1_RESET _u(0x1) -#define ACCESSCTRL_SPI1_CORE1_BITS _u(0x00000020) -#define ACCESSCTRL_SPI1_CORE1_MSB _u(5) -#define ACCESSCTRL_SPI1_CORE1_LSB _u(5) -#define ACCESSCTRL_SPI1_CORE1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_SPI1_CORE0 -// Description : If 1, SPI1 can be accessed by core 0, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_SPI1_CORE0_RESET _u(0x1) -#define ACCESSCTRL_SPI1_CORE0_BITS _u(0x00000010) -#define ACCESSCTRL_SPI1_CORE0_MSB _u(4) -#define ACCESSCTRL_SPI1_CORE0_LSB _u(4) -#define ACCESSCTRL_SPI1_CORE0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_SPI1_SP -// Description : If 1, SPI1 can be accessed from a Secure, Privileged context. -#define ACCESSCTRL_SPI1_SP_RESET _u(0x1) -#define ACCESSCTRL_SPI1_SP_BITS _u(0x00000008) -#define ACCESSCTRL_SPI1_SP_MSB _u(3) -#define ACCESSCTRL_SPI1_SP_LSB _u(3) -#define ACCESSCTRL_SPI1_SP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_SPI1_SU -// Description : If 1, and SP is also set, SPI1 can be accessed from a Secure, -// Unprivileged context. -#define ACCESSCTRL_SPI1_SU_RESET _u(0x1) -#define ACCESSCTRL_SPI1_SU_BITS _u(0x00000004) -#define ACCESSCTRL_SPI1_SU_MSB _u(2) -#define ACCESSCTRL_SPI1_SU_LSB _u(2) -#define ACCESSCTRL_SPI1_SU_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_SPI1_NSP -// Description : If 1, SPI1 can be accessed from a Non-secure, Privileged -// context. -#define ACCESSCTRL_SPI1_NSP_RESET _u(0x0) -#define ACCESSCTRL_SPI1_NSP_BITS _u(0x00000002) -#define ACCESSCTRL_SPI1_NSP_MSB _u(1) -#define ACCESSCTRL_SPI1_NSP_LSB _u(1) -#define ACCESSCTRL_SPI1_NSP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_SPI1_NSU -// Description : If 1, and NSP is also set, SPI1 can be accessed from a Non- -// secure, Unprivileged context. -// -// This bit is writable from a Non-secure, Privileged context, if -// and only if the NSP bit is set. -#define ACCESSCTRL_SPI1_NSU_RESET _u(0x0) -#define ACCESSCTRL_SPI1_NSU_BITS _u(0x00000001) -#define ACCESSCTRL_SPI1_NSU_MSB _u(0) -#define ACCESSCTRL_SPI1_NSU_LSB _u(0) -#define ACCESSCTRL_SPI1_NSU_ACCESS "RW" -// ============================================================================= -// Register : ACCESSCTRL_TIMER0 -// Description : Control whether debugger, DMA, core 0 and core 1 can access -// TIMER0, and at what security/privilege levels they can do so. -// -// Defaults to Secure access from any master. -// -// This register is writable only from a Secure, Privileged -// processor or debugger, with the exception of the NSU bit, which -// becomes Non-secure-Privileged-writable when the NSP bit is set. -#define ACCESSCTRL_TIMER0_OFFSET _u(0x00000098) -#define ACCESSCTRL_TIMER0_BITS _u(0x000000ff) -#define ACCESSCTRL_TIMER0_RESET _u(0x000000fc) -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_TIMER0_DBG -// Description : If 1, TIMER0 can be accessed by the debugger, at -// security/privilege levels permitted by SP/NSP/SU/NSU in this -// register. -#define ACCESSCTRL_TIMER0_DBG_RESET _u(0x1) -#define ACCESSCTRL_TIMER0_DBG_BITS _u(0x00000080) -#define ACCESSCTRL_TIMER0_DBG_MSB _u(7) -#define ACCESSCTRL_TIMER0_DBG_LSB _u(7) -#define ACCESSCTRL_TIMER0_DBG_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_TIMER0_DMA -// Description : If 1, TIMER0 can be accessed by the DMA, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_TIMER0_DMA_RESET _u(0x1) -#define ACCESSCTRL_TIMER0_DMA_BITS _u(0x00000040) -#define ACCESSCTRL_TIMER0_DMA_MSB _u(6) -#define ACCESSCTRL_TIMER0_DMA_LSB _u(6) -#define ACCESSCTRL_TIMER0_DMA_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_TIMER0_CORE1 -// Description : If 1, TIMER0 can be accessed by core 1, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_TIMER0_CORE1_RESET _u(0x1) -#define ACCESSCTRL_TIMER0_CORE1_BITS _u(0x00000020) -#define ACCESSCTRL_TIMER0_CORE1_MSB _u(5) -#define ACCESSCTRL_TIMER0_CORE1_LSB _u(5) -#define ACCESSCTRL_TIMER0_CORE1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_TIMER0_CORE0 -// Description : If 1, TIMER0 can be accessed by core 0, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_TIMER0_CORE0_RESET _u(0x1) -#define ACCESSCTRL_TIMER0_CORE0_BITS _u(0x00000010) -#define ACCESSCTRL_TIMER0_CORE0_MSB _u(4) -#define ACCESSCTRL_TIMER0_CORE0_LSB _u(4) -#define ACCESSCTRL_TIMER0_CORE0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_TIMER0_SP -// Description : If 1, TIMER0 can be accessed from a Secure, Privileged context. -#define ACCESSCTRL_TIMER0_SP_RESET _u(0x1) -#define ACCESSCTRL_TIMER0_SP_BITS _u(0x00000008) -#define ACCESSCTRL_TIMER0_SP_MSB _u(3) -#define ACCESSCTRL_TIMER0_SP_LSB _u(3) -#define ACCESSCTRL_TIMER0_SP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_TIMER0_SU -// Description : If 1, and SP is also set, TIMER0 can be accessed from a Secure, -// Unprivileged context. -#define ACCESSCTRL_TIMER0_SU_RESET _u(0x1) -#define ACCESSCTRL_TIMER0_SU_BITS _u(0x00000004) -#define ACCESSCTRL_TIMER0_SU_MSB _u(2) -#define ACCESSCTRL_TIMER0_SU_LSB _u(2) -#define ACCESSCTRL_TIMER0_SU_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_TIMER0_NSP -// Description : If 1, TIMER0 can be accessed from a Non-secure, Privileged -// context. -#define ACCESSCTRL_TIMER0_NSP_RESET _u(0x0) -#define ACCESSCTRL_TIMER0_NSP_BITS _u(0x00000002) -#define ACCESSCTRL_TIMER0_NSP_MSB _u(1) -#define ACCESSCTRL_TIMER0_NSP_LSB _u(1) -#define ACCESSCTRL_TIMER0_NSP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_TIMER0_NSU -// Description : If 1, and NSP is also set, TIMER0 can be accessed from a Non- -// secure, Unprivileged context. -// -// This bit is writable from a Non-secure, Privileged context, if -// and only if the NSP bit is set. -#define ACCESSCTRL_TIMER0_NSU_RESET _u(0x0) -#define ACCESSCTRL_TIMER0_NSU_BITS _u(0x00000001) -#define ACCESSCTRL_TIMER0_NSU_MSB _u(0) -#define ACCESSCTRL_TIMER0_NSU_LSB _u(0) -#define ACCESSCTRL_TIMER0_NSU_ACCESS "RW" -// ============================================================================= -// Register : ACCESSCTRL_TIMER1 -// Description : Control whether debugger, DMA, core 0 and core 1 can access -// TIMER1, and at what security/privilege levels they can do so. -// -// Defaults to Secure access from any master. -// -// This register is writable only from a Secure, Privileged -// processor or debugger, with the exception of the NSU bit, which -// becomes Non-secure-Privileged-writable when the NSP bit is set. -#define ACCESSCTRL_TIMER1_OFFSET _u(0x0000009c) -#define ACCESSCTRL_TIMER1_BITS _u(0x000000ff) -#define ACCESSCTRL_TIMER1_RESET _u(0x000000fc) -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_TIMER1_DBG -// Description : If 1, TIMER1 can be accessed by the debugger, at -// security/privilege levels permitted by SP/NSP/SU/NSU in this -// register. -#define ACCESSCTRL_TIMER1_DBG_RESET _u(0x1) -#define ACCESSCTRL_TIMER1_DBG_BITS _u(0x00000080) -#define ACCESSCTRL_TIMER1_DBG_MSB _u(7) -#define ACCESSCTRL_TIMER1_DBG_LSB _u(7) -#define ACCESSCTRL_TIMER1_DBG_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_TIMER1_DMA -// Description : If 1, TIMER1 can be accessed by the DMA, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_TIMER1_DMA_RESET _u(0x1) -#define ACCESSCTRL_TIMER1_DMA_BITS _u(0x00000040) -#define ACCESSCTRL_TIMER1_DMA_MSB _u(6) -#define ACCESSCTRL_TIMER1_DMA_LSB _u(6) -#define ACCESSCTRL_TIMER1_DMA_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_TIMER1_CORE1 -// Description : If 1, TIMER1 can be accessed by core 1, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_TIMER1_CORE1_RESET _u(0x1) -#define ACCESSCTRL_TIMER1_CORE1_BITS _u(0x00000020) -#define ACCESSCTRL_TIMER1_CORE1_MSB _u(5) -#define ACCESSCTRL_TIMER1_CORE1_LSB _u(5) -#define ACCESSCTRL_TIMER1_CORE1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_TIMER1_CORE0 -// Description : If 1, TIMER1 can be accessed by core 0, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_TIMER1_CORE0_RESET _u(0x1) -#define ACCESSCTRL_TIMER1_CORE0_BITS _u(0x00000010) -#define ACCESSCTRL_TIMER1_CORE0_MSB _u(4) -#define ACCESSCTRL_TIMER1_CORE0_LSB _u(4) -#define ACCESSCTRL_TIMER1_CORE0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_TIMER1_SP -// Description : If 1, TIMER1 can be accessed from a Secure, Privileged context. -#define ACCESSCTRL_TIMER1_SP_RESET _u(0x1) -#define ACCESSCTRL_TIMER1_SP_BITS _u(0x00000008) -#define ACCESSCTRL_TIMER1_SP_MSB _u(3) -#define ACCESSCTRL_TIMER1_SP_LSB _u(3) -#define ACCESSCTRL_TIMER1_SP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_TIMER1_SU -// Description : If 1, and SP is also set, TIMER1 can be accessed from a Secure, -// Unprivileged context. -#define ACCESSCTRL_TIMER1_SU_RESET _u(0x1) -#define ACCESSCTRL_TIMER1_SU_BITS _u(0x00000004) -#define ACCESSCTRL_TIMER1_SU_MSB _u(2) -#define ACCESSCTRL_TIMER1_SU_LSB _u(2) -#define ACCESSCTRL_TIMER1_SU_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_TIMER1_NSP -// Description : If 1, TIMER1 can be accessed from a Non-secure, Privileged -// context. -#define ACCESSCTRL_TIMER1_NSP_RESET _u(0x0) -#define ACCESSCTRL_TIMER1_NSP_BITS _u(0x00000002) -#define ACCESSCTRL_TIMER1_NSP_MSB _u(1) -#define ACCESSCTRL_TIMER1_NSP_LSB _u(1) -#define ACCESSCTRL_TIMER1_NSP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_TIMER1_NSU -// Description : If 1, and NSP is also set, TIMER1 can be accessed from a Non- -// secure, Unprivileged context. -// -// This bit is writable from a Non-secure, Privileged context, if -// and only if the NSP bit is set. -#define ACCESSCTRL_TIMER1_NSU_RESET _u(0x0) -#define ACCESSCTRL_TIMER1_NSU_BITS _u(0x00000001) -#define ACCESSCTRL_TIMER1_NSU_MSB _u(0) -#define ACCESSCTRL_TIMER1_NSU_LSB _u(0) -#define ACCESSCTRL_TIMER1_NSU_ACCESS "RW" -// ============================================================================= -// Register : ACCESSCTRL_UART0 -// Description : Control whether debugger, DMA, core 0 and core 1 can access -// UART0, and at what security/privilege levels they can do so. -// -// Defaults to Secure access from any master. -// -// This register is writable only from a Secure, Privileged -// processor or debugger, with the exception of the NSU bit, which -// becomes Non-secure-Privileged-writable when the NSP bit is set. -#define ACCESSCTRL_UART0_OFFSET _u(0x000000a0) -#define ACCESSCTRL_UART0_BITS _u(0x000000ff) -#define ACCESSCTRL_UART0_RESET _u(0x000000fc) -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_UART0_DBG -// Description : If 1, UART0 can be accessed by the debugger, at -// security/privilege levels permitted by SP/NSP/SU/NSU in this -// register. -#define ACCESSCTRL_UART0_DBG_RESET _u(0x1) -#define ACCESSCTRL_UART0_DBG_BITS _u(0x00000080) -#define ACCESSCTRL_UART0_DBG_MSB _u(7) -#define ACCESSCTRL_UART0_DBG_LSB _u(7) -#define ACCESSCTRL_UART0_DBG_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_UART0_DMA -// Description : If 1, UART0 can be accessed by the DMA, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_UART0_DMA_RESET _u(0x1) -#define ACCESSCTRL_UART0_DMA_BITS _u(0x00000040) -#define ACCESSCTRL_UART0_DMA_MSB _u(6) -#define ACCESSCTRL_UART0_DMA_LSB _u(6) -#define ACCESSCTRL_UART0_DMA_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_UART0_CORE1 -// Description : If 1, UART0 can be accessed by core 1, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_UART0_CORE1_RESET _u(0x1) -#define ACCESSCTRL_UART0_CORE1_BITS _u(0x00000020) -#define ACCESSCTRL_UART0_CORE1_MSB _u(5) -#define ACCESSCTRL_UART0_CORE1_LSB _u(5) -#define ACCESSCTRL_UART0_CORE1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_UART0_CORE0 -// Description : If 1, UART0 can be accessed by core 0, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_UART0_CORE0_RESET _u(0x1) -#define ACCESSCTRL_UART0_CORE0_BITS _u(0x00000010) -#define ACCESSCTRL_UART0_CORE0_MSB _u(4) -#define ACCESSCTRL_UART0_CORE0_LSB _u(4) -#define ACCESSCTRL_UART0_CORE0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_UART0_SP -// Description : If 1, UART0 can be accessed from a Secure, Privileged context. -#define ACCESSCTRL_UART0_SP_RESET _u(0x1) -#define ACCESSCTRL_UART0_SP_BITS _u(0x00000008) -#define ACCESSCTRL_UART0_SP_MSB _u(3) -#define ACCESSCTRL_UART0_SP_LSB _u(3) -#define ACCESSCTRL_UART0_SP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_UART0_SU -// Description : If 1, and SP is also set, UART0 can be accessed from a Secure, -// Unprivileged context. -#define ACCESSCTRL_UART0_SU_RESET _u(0x1) -#define ACCESSCTRL_UART0_SU_BITS _u(0x00000004) -#define ACCESSCTRL_UART0_SU_MSB _u(2) -#define ACCESSCTRL_UART0_SU_LSB _u(2) -#define ACCESSCTRL_UART0_SU_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_UART0_NSP -// Description : If 1, UART0 can be accessed from a Non-secure, Privileged -// context. -#define ACCESSCTRL_UART0_NSP_RESET _u(0x0) -#define ACCESSCTRL_UART0_NSP_BITS _u(0x00000002) -#define ACCESSCTRL_UART0_NSP_MSB _u(1) -#define ACCESSCTRL_UART0_NSP_LSB _u(1) -#define ACCESSCTRL_UART0_NSP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_UART0_NSU -// Description : If 1, and NSP is also set, UART0 can be accessed from a Non- -// secure, Unprivileged context. -// -// This bit is writable from a Non-secure, Privileged context, if -// and only if the NSP bit is set. -#define ACCESSCTRL_UART0_NSU_RESET _u(0x0) -#define ACCESSCTRL_UART0_NSU_BITS _u(0x00000001) -#define ACCESSCTRL_UART0_NSU_MSB _u(0) -#define ACCESSCTRL_UART0_NSU_LSB _u(0) -#define ACCESSCTRL_UART0_NSU_ACCESS "RW" -// ============================================================================= -// Register : ACCESSCTRL_UART1 -// Description : Control whether debugger, DMA, core 0 and core 1 can access -// UART1, and at what security/privilege levels they can do so. -// -// Defaults to Secure access from any master. -// -// This register is writable only from a Secure, Privileged -// processor or debugger, with the exception of the NSU bit, which -// becomes Non-secure-Privileged-writable when the NSP bit is set. -#define ACCESSCTRL_UART1_OFFSET _u(0x000000a4) -#define ACCESSCTRL_UART1_BITS _u(0x000000ff) -#define ACCESSCTRL_UART1_RESET _u(0x000000fc) -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_UART1_DBG -// Description : If 1, UART1 can be accessed by the debugger, at -// security/privilege levels permitted by SP/NSP/SU/NSU in this -// register. -#define ACCESSCTRL_UART1_DBG_RESET _u(0x1) -#define ACCESSCTRL_UART1_DBG_BITS _u(0x00000080) -#define ACCESSCTRL_UART1_DBG_MSB _u(7) -#define ACCESSCTRL_UART1_DBG_LSB _u(7) -#define ACCESSCTRL_UART1_DBG_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_UART1_DMA -// Description : If 1, UART1 can be accessed by the DMA, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_UART1_DMA_RESET _u(0x1) -#define ACCESSCTRL_UART1_DMA_BITS _u(0x00000040) -#define ACCESSCTRL_UART1_DMA_MSB _u(6) -#define ACCESSCTRL_UART1_DMA_LSB _u(6) -#define ACCESSCTRL_UART1_DMA_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_UART1_CORE1 -// Description : If 1, UART1 can be accessed by core 1, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_UART1_CORE1_RESET _u(0x1) -#define ACCESSCTRL_UART1_CORE1_BITS _u(0x00000020) -#define ACCESSCTRL_UART1_CORE1_MSB _u(5) -#define ACCESSCTRL_UART1_CORE1_LSB _u(5) -#define ACCESSCTRL_UART1_CORE1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_UART1_CORE0 -// Description : If 1, UART1 can be accessed by core 0, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_UART1_CORE0_RESET _u(0x1) -#define ACCESSCTRL_UART1_CORE0_BITS _u(0x00000010) -#define ACCESSCTRL_UART1_CORE0_MSB _u(4) -#define ACCESSCTRL_UART1_CORE0_LSB _u(4) -#define ACCESSCTRL_UART1_CORE0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_UART1_SP -// Description : If 1, UART1 can be accessed from a Secure, Privileged context. -#define ACCESSCTRL_UART1_SP_RESET _u(0x1) -#define ACCESSCTRL_UART1_SP_BITS _u(0x00000008) -#define ACCESSCTRL_UART1_SP_MSB _u(3) -#define ACCESSCTRL_UART1_SP_LSB _u(3) -#define ACCESSCTRL_UART1_SP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_UART1_SU -// Description : If 1, and SP is also set, UART1 can be accessed from a Secure, -// Unprivileged context. -#define ACCESSCTRL_UART1_SU_RESET _u(0x1) -#define ACCESSCTRL_UART1_SU_BITS _u(0x00000004) -#define ACCESSCTRL_UART1_SU_MSB _u(2) -#define ACCESSCTRL_UART1_SU_LSB _u(2) -#define ACCESSCTRL_UART1_SU_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_UART1_NSP -// Description : If 1, UART1 can be accessed from a Non-secure, Privileged -// context. -#define ACCESSCTRL_UART1_NSP_RESET _u(0x0) -#define ACCESSCTRL_UART1_NSP_BITS _u(0x00000002) -#define ACCESSCTRL_UART1_NSP_MSB _u(1) -#define ACCESSCTRL_UART1_NSP_LSB _u(1) -#define ACCESSCTRL_UART1_NSP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_UART1_NSU -// Description : If 1, and NSP is also set, UART1 can be accessed from a Non- -// secure, Unprivileged context. -// -// This bit is writable from a Non-secure, Privileged context, if -// and only if the NSP bit is set. -#define ACCESSCTRL_UART1_NSU_RESET _u(0x0) -#define ACCESSCTRL_UART1_NSU_BITS _u(0x00000001) -#define ACCESSCTRL_UART1_NSU_MSB _u(0) -#define ACCESSCTRL_UART1_NSU_LSB _u(0) -#define ACCESSCTRL_UART1_NSU_ACCESS "RW" -// ============================================================================= -// Register : ACCESSCTRL_OTP -// Description : Control whether debugger, DMA, core 0 and core 1 can access -// OTP, and at what security/privilege levels they can do so. -// -// Defaults to Secure access from any master. -// -// This register is writable only from a Secure, Privileged -// processor or debugger, with the exception of the NSU bit, which -// becomes Non-secure-Privileged-writable when the NSP bit is set. -#define ACCESSCTRL_OTP_OFFSET _u(0x000000a8) -#define ACCESSCTRL_OTP_BITS _u(0x000000ff) -#define ACCESSCTRL_OTP_RESET _u(0x000000fc) -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_OTP_DBG -// Description : If 1, OTP can be accessed by the debugger, at -// security/privilege levels permitted by SP/NSP/SU/NSU in this -// register. -#define ACCESSCTRL_OTP_DBG_RESET _u(0x1) -#define ACCESSCTRL_OTP_DBG_BITS _u(0x00000080) -#define ACCESSCTRL_OTP_DBG_MSB _u(7) -#define ACCESSCTRL_OTP_DBG_LSB _u(7) -#define ACCESSCTRL_OTP_DBG_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_OTP_DMA -// Description : If 1, OTP can be accessed by the DMA, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_OTP_DMA_RESET _u(0x1) -#define ACCESSCTRL_OTP_DMA_BITS _u(0x00000040) -#define ACCESSCTRL_OTP_DMA_MSB _u(6) -#define ACCESSCTRL_OTP_DMA_LSB _u(6) -#define ACCESSCTRL_OTP_DMA_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_OTP_CORE1 -// Description : If 1, OTP can be accessed by core 1, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_OTP_CORE1_RESET _u(0x1) -#define ACCESSCTRL_OTP_CORE1_BITS _u(0x00000020) -#define ACCESSCTRL_OTP_CORE1_MSB _u(5) -#define ACCESSCTRL_OTP_CORE1_LSB _u(5) -#define ACCESSCTRL_OTP_CORE1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_OTP_CORE0 -// Description : If 1, OTP can be accessed by core 0, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_OTP_CORE0_RESET _u(0x1) -#define ACCESSCTRL_OTP_CORE0_BITS _u(0x00000010) -#define ACCESSCTRL_OTP_CORE0_MSB _u(4) -#define ACCESSCTRL_OTP_CORE0_LSB _u(4) -#define ACCESSCTRL_OTP_CORE0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_OTP_SP -// Description : If 1, OTP can be accessed from a Secure, Privileged context. -#define ACCESSCTRL_OTP_SP_RESET _u(0x1) -#define ACCESSCTRL_OTP_SP_BITS _u(0x00000008) -#define ACCESSCTRL_OTP_SP_MSB _u(3) -#define ACCESSCTRL_OTP_SP_LSB _u(3) -#define ACCESSCTRL_OTP_SP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_OTP_SU -// Description : If 1, and SP is also set, OTP can be accessed from a Secure, -// Unprivileged context. -#define ACCESSCTRL_OTP_SU_RESET _u(0x1) -#define ACCESSCTRL_OTP_SU_BITS _u(0x00000004) -#define ACCESSCTRL_OTP_SU_MSB _u(2) -#define ACCESSCTRL_OTP_SU_LSB _u(2) -#define ACCESSCTRL_OTP_SU_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_OTP_NSP -// Description : If 1, OTP can be accessed from a Non-secure, Privileged -// context. -#define ACCESSCTRL_OTP_NSP_RESET _u(0x0) -#define ACCESSCTRL_OTP_NSP_BITS _u(0x00000002) -#define ACCESSCTRL_OTP_NSP_MSB _u(1) -#define ACCESSCTRL_OTP_NSP_LSB _u(1) -#define ACCESSCTRL_OTP_NSP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_OTP_NSU -// Description : If 1, and NSP is also set, OTP can be accessed from a Non- -// secure, Unprivileged context. -// -// This bit is writable from a Non-secure, Privileged context, if -// and only if the NSP bit is set. -#define ACCESSCTRL_OTP_NSU_RESET _u(0x0) -#define ACCESSCTRL_OTP_NSU_BITS _u(0x00000001) -#define ACCESSCTRL_OTP_NSU_MSB _u(0) -#define ACCESSCTRL_OTP_NSU_LSB _u(0) -#define ACCESSCTRL_OTP_NSU_ACCESS "RW" -// ============================================================================= -// Register : ACCESSCTRL_TBMAN -// Description : Control whether debugger, DMA, core 0 and core 1 can access -// TBMAN, and at what security/privilege levels they can do so. -// -// Defaults to Secure access from any master. -// -// This register is writable only from a Secure, Privileged -// processor or debugger, with the exception of the NSU bit, which -// becomes Non-secure-Privileged-writable when the NSP bit is set. -#define ACCESSCTRL_TBMAN_OFFSET _u(0x000000ac) -#define ACCESSCTRL_TBMAN_BITS _u(0x000000ff) -#define ACCESSCTRL_TBMAN_RESET _u(0x000000fc) -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_TBMAN_DBG -// Description : If 1, TBMAN can be accessed by the debugger, at -// security/privilege levels permitted by SP/NSP/SU/NSU in this -// register. -#define ACCESSCTRL_TBMAN_DBG_RESET _u(0x1) -#define ACCESSCTRL_TBMAN_DBG_BITS _u(0x00000080) -#define ACCESSCTRL_TBMAN_DBG_MSB _u(7) -#define ACCESSCTRL_TBMAN_DBG_LSB _u(7) -#define ACCESSCTRL_TBMAN_DBG_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_TBMAN_DMA -// Description : If 1, TBMAN can be accessed by the DMA, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_TBMAN_DMA_RESET _u(0x1) -#define ACCESSCTRL_TBMAN_DMA_BITS _u(0x00000040) -#define ACCESSCTRL_TBMAN_DMA_MSB _u(6) -#define ACCESSCTRL_TBMAN_DMA_LSB _u(6) -#define ACCESSCTRL_TBMAN_DMA_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_TBMAN_CORE1 -// Description : If 1, TBMAN can be accessed by core 1, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_TBMAN_CORE1_RESET _u(0x1) -#define ACCESSCTRL_TBMAN_CORE1_BITS _u(0x00000020) -#define ACCESSCTRL_TBMAN_CORE1_MSB _u(5) -#define ACCESSCTRL_TBMAN_CORE1_LSB _u(5) -#define ACCESSCTRL_TBMAN_CORE1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_TBMAN_CORE0 -// Description : If 1, TBMAN can be accessed by core 0, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_TBMAN_CORE0_RESET _u(0x1) -#define ACCESSCTRL_TBMAN_CORE0_BITS _u(0x00000010) -#define ACCESSCTRL_TBMAN_CORE0_MSB _u(4) -#define ACCESSCTRL_TBMAN_CORE0_LSB _u(4) -#define ACCESSCTRL_TBMAN_CORE0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_TBMAN_SP -// Description : If 1, TBMAN can be accessed from a Secure, Privileged context. -#define ACCESSCTRL_TBMAN_SP_RESET _u(0x1) -#define ACCESSCTRL_TBMAN_SP_BITS _u(0x00000008) -#define ACCESSCTRL_TBMAN_SP_MSB _u(3) -#define ACCESSCTRL_TBMAN_SP_LSB _u(3) -#define ACCESSCTRL_TBMAN_SP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_TBMAN_SU -// Description : If 1, and SP is also set, TBMAN can be accessed from a Secure, -// Unprivileged context. -#define ACCESSCTRL_TBMAN_SU_RESET _u(0x1) -#define ACCESSCTRL_TBMAN_SU_BITS _u(0x00000004) -#define ACCESSCTRL_TBMAN_SU_MSB _u(2) -#define ACCESSCTRL_TBMAN_SU_LSB _u(2) -#define ACCESSCTRL_TBMAN_SU_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_TBMAN_NSP -// Description : If 1, TBMAN can be accessed from a Non-secure, Privileged -// context. -#define ACCESSCTRL_TBMAN_NSP_RESET _u(0x0) -#define ACCESSCTRL_TBMAN_NSP_BITS _u(0x00000002) -#define ACCESSCTRL_TBMAN_NSP_MSB _u(1) -#define ACCESSCTRL_TBMAN_NSP_LSB _u(1) -#define ACCESSCTRL_TBMAN_NSP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_TBMAN_NSU -// Description : If 1, and NSP is also set, TBMAN can be accessed from a Non- -// secure, Unprivileged context. -// -// This bit is writable from a Non-secure, Privileged context, if -// and only if the NSP bit is set. -#define ACCESSCTRL_TBMAN_NSU_RESET _u(0x0) -#define ACCESSCTRL_TBMAN_NSU_BITS _u(0x00000001) -#define ACCESSCTRL_TBMAN_NSU_MSB _u(0) -#define ACCESSCTRL_TBMAN_NSU_LSB _u(0) -#define ACCESSCTRL_TBMAN_NSU_ACCESS "RW" -// ============================================================================= -// Register : ACCESSCTRL_POWMAN -// Description : Control whether debugger, DMA, core 0 and core 1 can access -// POWMAN, and at what security/privilege levels they can do so. -// -// Defaults to Secure, Privileged processor or debug access only. -// -// This register is writable only from a Secure, Privileged -// processor or debugger, with the exception of the NSU bit, which -// becomes Non-secure-Privileged-writable when the NSP bit is set. -#define ACCESSCTRL_POWMAN_OFFSET _u(0x000000b0) -#define ACCESSCTRL_POWMAN_BITS _u(0x000000ff) -#define ACCESSCTRL_POWMAN_RESET _u(0x000000b8) -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_POWMAN_DBG -// Description : If 1, POWMAN can be accessed by the debugger, at -// security/privilege levels permitted by SP/NSP/SU/NSU in this -// register. -#define ACCESSCTRL_POWMAN_DBG_RESET _u(0x1) -#define ACCESSCTRL_POWMAN_DBG_BITS _u(0x00000080) -#define ACCESSCTRL_POWMAN_DBG_MSB _u(7) -#define ACCESSCTRL_POWMAN_DBG_LSB _u(7) -#define ACCESSCTRL_POWMAN_DBG_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_POWMAN_DMA -// Description : If 1, POWMAN can be accessed by the DMA, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_POWMAN_DMA_RESET _u(0x0) -#define ACCESSCTRL_POWMAN_DMA_BITS _u(0x00000040) -#define ACCESSCTRL_POWMAN_DMA_MSB _u(6) -#define ACCESSCTRL_POWMAN_DMA_LSB _u(6) -#define ACCESSCTRL_POWMAN_DMA_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_POWMAN_CORE1 -// Description : If 1, POWMAN can be accessed by core 1, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_POWMAN_CORE1_RESET _u(0x1) -#define ACCESSCTRL_POWMAN_CORE1_BITS _u(0x00000020) -#define ACCESSCTRL_POWMAN_CORE1_MSB _u(5) -#define ACCESSCTRL_POWMAN_CORE1_LSB _u(5) -#define ACCESSCTRL_POWMAN_CORE1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_POWMAN_CORE0 -// Description : If 1, POWMAN can be accessed by core 0, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_POWMAN_CORE0_RESET _u(0x1) -#define ACCESSCTRL_POWMAN_CORE0_BITS _u(0x00000010) -#define ACCESSCTRL_POWMAN_CORE0_MSB _u(4) -#define ACCESSCTRL_POWMAN_CORE0_LSB _u(4) -#define ACCESSCTRL_POWMAN_CORE0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_POWMAN_SP -// Description : If 1, POWMAN can be accessed from a Secure, Privileged context. -#define ACCESSCTRL_POWMAN_SP_RESET _u(0x1) -#define ACCESSCTRL_POWMAN_SP_BITS _u(0x00000008) -#define ACCESSCTRL_POWMAN_SP_MSB _u(3) -#define ACCESSCTRL_POWMAN_SP_LSB _u(3) -#define ACCESSCTRL_POWMAN_SP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_POWMAN_SU -// Description : If 1, and SP is also set, POWMAN can be accessed from a Secure, -// Unprivileged context. -#define ACCESSCTRL_POWMAN_SU_RESET _u(0x0) -#define ACCESSCTRL_POWMAN_SU_BITS _u(0x00000004) -#define ACCESSCTRL_POWMAN_SU_MSB _u(2) -#define ACCESSCTRL_POWMAN_SU_LSB _u(2) -#define ACCESSCTRL_POWMAN_SU_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_POWMAN_NSP -// Description : If 1, POWMAN can be accessed from a Non-secure, Privileged -// context. -#define ACCESSCTRL_POWMAN_NSP_RESET _u(0x0) -#define ACCESSCTRL_POWMAN_NSP_BITS _u(0x00000002) -#define ACCESSCTRL_POWMAN_NSP_MSB _u(1) -#define ACCESSCTRL_POWMAN_NSP_LSB _u(1) -#define ACCESSCTRL_POWMAN_NSP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_POWMAN_NSU -// Description : If 1, and NSP is also set, POWMAN can be accessed from a Non- -// secure, Unprivileged context. -// -// This bit is writable from a Non-secure, Privileged context, if -// and only if the NSP bit is set. -#define ACCESSCTRL_POWMAN_NSU_RESET _u(0x0) -#define ACCESSCTRL_POWMAN_NSU_BITS _u(0x00000001) -#define ACCESSCTRL_POWMAN_NSU_MSB _u(0) -#define ACCESSCTRL_POWMAN_NSU_LSB _u(0) -#define ACCESSCTRL_POWMAN_NSU_ACCESS "RW" -// ============================================================================= -// Register : ACCESSCTRL_TRNG -// Description : Control whether debugger, DMA, core 0 and core 1 can access -// TRNG, and at what security/privilege levels they can do so. -// -// Defaults to Secure, Privileged processor or debug access only. -// -// This register is writable only from a Secure, Privileged -// processor or debugger, with the exception of the NSU bit, which -// becomes Non-secure-Privileged-writable when the NSP bit is set. -#define ACCESSCTRL_TRNG_OFFSET _u(0x000000b4) -#define ACCESSCTRL_TRNG_BITS _u(0x000000ff) -#define ACCESSCTRL_TRNG_RESET _u(0x000000b8) -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_TRNG_DBG -// Description : If 1, TRNG can be accessed by the debugger, at -// security/privilege levels permitted by SP/NSP/SU/NSU in this -// register. -#define ACCESSCTRL_TRNG_DBG_RESET _u(0x1) -#define ACCESSCTRL_TRNG_DBG_BITS _u(0x00000080) -#define ACCESSCTRL_TRNG_DBG_MSB _u(7) -#define ACCESSCTRL_TRNG_DBG_LSB _u(7) -#define ACCESSCTRL_TRNG_DBG_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_TRNG_DMA -// Description : If 1, TRNG can be accessed by the DMA, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_TRNG_DMA_RESET _u(0x0) -#define ACCESSCTRL_TRNG_DMA_BITS _u(0x00000040) -#define ACCESSCTRL_TRNG_DMA_MSB _u(6) -#define ACCESSCTRL_TRNG_DMA_LSB _u(6) -#define ACCESSCTRL_TRNG_DMA_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_TRNG_CORE1 -// Description : If 1, TRNG can be accessed by core 1, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_TRNG_CORE1_RESET _u(0x1) -#define ACCESSCTRL_TRNG_CORE1_BITS _u(0x00000020) -#define ACCESSCTRL_TRNG_CORE1_MSB _u(5) -#define ACCESSCTRL_TRNG_CORE1_LSB _u(5) -#define ACCESSCTRL_TRNG_CORE1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_TRNG_CORE0 -// Description : If 1, TRNG can be accessed by core 0, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_TRNG_CORE0_RESET _u(0x1) -#define ACCESSCTRL_TRNG_CORE0_BITS _u(0x00000010) -#define ACCESSCTRL_TRNG_CORE0_MSB _u(4) -#define ACCESSCTRL_TRNG_CORE0_LSB _u(4) -#define ACCESSCTRL_TRNG_CORE0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_TRNG_SP -// Description : If 1, TRNG can be accessed from a Secure, Privileged context. -#define ACCESSCTRL_TRNG_SP_RESET _u(0x1) -#define ACCESSCTRL_TRNG_SP_BITS _u(0x00000008) -#define ACCESSCTRL_TRNG_SP_MSB _u(3) -#define ACCESSCTRL_TRNG_SP_LSB _u(3) -#define ACCESSCTRL_TRNG_SP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_TRNG_SU -// Description : If 1, and SP is also set, TRNG can be accessed from a Secure, -// Unprivileged context. -#define ACCESSCTRL_TRNG_SU_RESET _u(0x0) -#define ACCESSCTRL_TRNG_SU_BITS _u(0x00000004) -#define ACCESSCTRL_TRNG_SU_MSB _u(2) -#define ACCESSCTRL_TRNG_SU_LSB _u(2) -#define ACCESSCTRL_TRNG_SU_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_TRNG_NSP -// Description : If 1, TRNG can be accessed from a Non-secure, Privileged -// context. -#define ACCESSCTRL_TRNG_NSP_RESET _u(0x0) -#define ACCESSCTRL_TRNG_NSP_BITS _u(0x00000002) -#define ACCESSCTRL_TRNG_NSP_MSB _u(1) -#define ACCESSCTRL_TRNG_NSP_LSB _u(1) -#define ACCESSCTRL_TRNG_NSP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_TRNG_NSU -// Description : If 1, and NSP is also set, TRNG can be accessed from a Non- -// secure, Unprivileged context. -// -// This bit is writable from a Non-secure, Privileged context, if -// and only if the NSP bit is set. -#define ACCESSCTRL_TRNG_NSU_RESET _u(0x0) -#define ACCESSCTRL_TRNG_NSU_BITS _u(0x00000001) -#define ACCESSCTRL_TRNG_NSU_MSB _u(0) -#define ACCESSCTRL_TRNG_NSU_LSB _u(0) -#define ACCESSCTRL_TRNG_NSU_ACCESS "RW" -// ============================================================================= -// Register : ACCESSCTRL_SHA256 -// Description : Control whether debugger, DMA, core 0 and core 1 can access -// SHA256, and at what security/privilege levels they can do so. -// -// Defaults to Secure, Privileged access only. -// -// This register is writable only from a Secure, Privileged -// processor or debugger, with the exception of the NSU bit, which -// becomes Non-secure-Privileged-writable when the NSP bit is set. -#define ACCESSCTRL_SHA256_OFFSET _u(0x000000b8) -#define ACCESSCTRL_SHA256_BITS _u(0x000000ff) -#define ACCESSCTRL_SHA256_RESET _u(0x000000f8) -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_SHA256_DBG -// Description : If 1, SHA256 can be accessed by the debugger, at -// security/privilege levels permitted by SP/NSP/SU/NSU in this -// register. -#define ACCESSCTRL_SHA256_DBG_RESET _u(0x1) -#define ACCESSCTRL_SHA256_DBG_BITS _u(0x00000080) -#define ACCESSCTRL_SHA256_DBG_MSB _u(7) -#define ACCESSCTRL_SHA256_DBG_LSB _u(7) -#define ACCESSCTRL_SHA256_DBG_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_SHA256_DMA -// Description : If 1, SHA256 can be accessed by the DMA, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_SHA256_DMA_RESET _u(0x1) -#define ACCESSCTRL_SHA256_DMA_BITS _u(0x00000040) -#define ACCESSCTRL_SHA256_DMA_MSB _u(6) -#define ACCESSCTRL_SHA256_DMA_LSB _u(6) -#define ACCESSCTRL_SHA256_DMA_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_SHA256_CORE1 -// Description : If 1, SHA256 can be accessed by core 1, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_SHA256_CORE1_RESET _u(0x1) -#define ACCESSCTRL_SHA256_CORE1_BITS _u(0x00000020) -#define ACCESSCTRL_SHA256_CORE1_MSB _u(5) -#define ACCESSCTRL_SHA256_CORE1_LSB _u(5) -#define ACCESSCTRL_SHA256_CORE1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_SHA256_CORE0 -// Description : If 1, SHA256 can be accessed by core 0, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_SHA256_CORE0_RESET _u(0x1) -#define ACCESSCTRL_SHA256_CORE0_BITS _u(0x00000010) -#define ACCESSCTRL_SHA256_CORE0_MSB _u(4) -#define ACCESSCTRL_SHA256_CORE0_LSB _u(4) -#define ACCESSCTRL_SHA256_CORE0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_SHA256_SP -// Description : If 1, SHA256 can be accessed from a Secure, Privileged context. -#define ACCESSCTRL_SHA256_SP_RESET _u(0x1) -#define ACCESSCTRL_SHA256_SP_BITS _u(0x00000008) -#define ACCESSCTRL_SHA256_SP_MSB _u(3) -#define ACCESSCTRL_SHA256_SP_LSB _u(3) -#define ACCESSCTRL_SHA256_SP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_SHA256_SU -// Description : If 1, and SP is also set, SHA256 can be accessed from a Secure, -// Unprivileged context. -#define ACCESSCTRL_SHA256_SU_RESET _u(0x0) -#define ACCESSCTRL_SHA256_SU_BITS _u(0x00000004) -#define ACCESSCTRL_SHA256_SU_MSB _u(2) -#define ACCESSCTRL_SHA256_SU_LSB _u(2) -#define ACCESSCTRL_SHA256_SU_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_SHA256_NSP -// Description : If 1, SHA256 can be accessed from a Non-secure, Privileged -// context. -#define ACCESSCTRL_SHA256_NSP_RESET _u(0x0) -#define ACCESSCTRL_SHA256_NSP_BITS _u(0x00000002) -#define ACCESSCTRL_SHA256_NSP_MSB _u(1) -#define ACCESSCTRL_SHA256_NSP_LSB _u(1) -#define ACCESSCTRL_SHA256_NSP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_SHA256_NSU -// Description : If 1, and NSP is also set, SHA256 can be accessed from a Non- -// secure, Unprivileged context. -// -// This bit is writable from a Non-secure, Privileged context, if -// and only if the NSP bit is set. -#define ACCESSCTRL_SHA256_NSU_RESET _u(0x0) -#define ACCESSCTRL_SHA256_NSU_BITS _u(0x00000001) -#define ACCESSCTRL_SHA256_NSU_MSB _u(0) -#define ACCESSCTRL_SHA256_NSU_LSB _u(0) -#define ACCESSCTRL_SHA256_NSU_ACCESS "RW" -// ============================================================================= -// Register : ACCESSCTRL_SYSCFG -// Description : Control whether debugger, DMA, core 0 and core 1 can access -// SYSCFG, and at what security/privilege levels they can do so. -// -// Defaults to Secure, Privileged processor or debug access only. -// -// This register is writable only from a Secure, Privileged -// processor or debugger, with the exception of the NSU bit, which -// becomes Non-secure-Privileged-writable when the NSP bit is set. -#define ACCESSCTRL_SYSCFG_OFFSET _u(0x000000bc) -#define ACCESSCTRL_SYSCFG_BITS _u(0x000000ff) -#define ACCESSCTRL_SYSCFG_RESET _u(0x000000b8) -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_SYSCFG_DBG -// Description : If 1, SYSCFG can be accessed by the debugger, at -// security/privilege levels permitted by SP/NSP/SU/NSU in this -// register. -#define ACCESSCTRL_SYSCFG_DBG_RESET _u(0x1) -#define ACCESSCTRL_SYSCFG_DBG_BITS _u(0x00000080) -#define ACCESSCTRL_SYSCFG_DBG_MSB _u(7) -#define ACCESSCTRL_SYSCFG_DBG_LSB _u(7) -#define ACCESSCTRL_SYSCFG_DBG_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_SYSCFG_DMA -// Description : If 1, SYSCFG can be accessed by the DMA, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_SYSCFG_DMA_RESET _u(0x0) -#define ACCESSCTRL_SYSCFG_DMA_BITS _u(0x00000040) -#define ACCESSCTRL_SYSCFG_DMA_MSB _u(6) -#define ACCESSCTRL_SYSCFG_DMA_LSB _u(6) -#define ACCESSCTRL_SYSCFG_DMA_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_SYSCFG_CORE1 -// Description : If 1, SYSCFG can be accessed by core 1, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_SYSCFG_CORE1_RESET _u(0x1) -#define ACCESSCTRL_SYSCFG_CORE1_BITS _u(0x00000020) -#define ACCESSCTRL_SYSCFG_CORE1_MSB _u(5) -#define ACCESSCTRL_SYSCFG_CORE1_LSB _u(5) -#define ACCESSCTRL_SYSCFG_CORE1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_SYSCFG_CORE0 -// Description : If 1, SYSCFG can be accessed by core 0, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_SYSCFG_CORE0_RESET _u(0x1) -#define ACCESSCTRL_SYSCFG_CORE0_BITS _u(0x00000010) -#define ACCESSCTRL_SYSCFG_CORE0_MSB _u(4) -#define ACCESSCTRL_SYSCFG_CORE0_LSB _u(4) -#define ACCESSCTRL_SYSCFG_CORE0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_SYSCFG_SP -// Description : If 1, SYSCFG can be accessed from a Secure, Privileged context. -#define ACCESSCTRL_SYSCFG_SP_RESET _u(0x1) -#define ACCESSCTRL_SYSCFG_SP_BITS _u(0x00000008) -#define ACCESSCTRL_SYSCFG_SP_MSB _u(3) -#define ACCESSCTRL_SYSCFG_SP_LSB _u(3) -#define ACCESSCTRL_SYSCFG_SP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_SYSCFG_SU -// Description : If 1, and SP is also set, SYSCFG can be accessed from a Secure, -// Unprivileged context. -#define ACCESSCTRL_SYSCFG_SU_RESET _u(0x0) -#define ACCESSCTRL_SYSCFG_SU_BITS _u(0x00000004) -#define ACCESSCTRL_SYSCFG_SU_MSB _u(2) -#define ACCESSCTRL_SYSCFG_SU_LSB _u(2) -#define ACCESSCTRL_SYSCFG_SU_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_SYSCFG_NSP -// Description : If 1, SYSCFG can be accessed from a Non-secure, Privileged -// context. -#define ACCESSCTRL_SYSCFG_NSP_RESET _u(0x0) -#define ACCESSCTRL_SYSCFG_NSP_BITS _u(0x00000002) -#define ACCESSCTRL_SYSCFG_NSP_MSB _u(1) -#define ACCESSCTRL_SYSCFG_NSP_LSB _u(1) -#define ACCESSCTRL_SYSCFG_NSP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_SYSCFG_NSU -// Description : If 1, and NSP is also set, SYSCFG can be accessed from a Non- -// secure, Unprivileged context. -// -// This bit is writable from a Non-secure, Privileged context, if -// and only if the NSP bit is set. -#define ACCESSCTRL_SYSCFG_NSU_RESET _u(0x0) -#define ACCESSCTRL_SYSCFG_NSU_BITS _u(0x00000001) -#define ACCESSCTRL_SYSCFG_NSU_MSB _u(0) -#define ACCESSCTRL_SYSCFG_NSU_LSB _u(0) -#define ACCESSCTRL_SYSCFG_NSU_ACCESS "RW" -// ============================================================================= -// Register : ACCESSCTRL_CLOCKS -// Description : Control whether debugger, DMA, core 0 and core 1 can access -// CLOCKS, and at what security/privilege levels they can do so. -// -// Defaults to Secure, Privileged processor or debug access only. -// -// This register is writable only from a Secure, Privileged -// processor or debugger, with the exception of the NSU bit, which -// becomes Non-secure-Privileged-writable when the NSP bit is set. -#define ACCESSCTRL_CLOCKS_OFFSET _u(0x000000c0) -#define ACCESSCTRL_CLOCKS_BITS _u(0x000000ff) -#define ACCESSCTRL_CLOCKS_RESET _u(0x000000b8) -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_CLOCKS_DBG -// Description : If 1, CLOCKS can be accessed by the debugger, at -// security/privilege levels permitted by SP/NSP/SU/NSU in this -// register. -#define ACCESSCTRL_CLOCKS_DBG_RESET _u(0x1) -#define ACCESSCTRL_CLOCKS_DBG_BITS _u(0x00000080) -#define ACCESSCTRL_CLOCKS_DBG_MSB _u(7) -#define ACCESSCTRL_CLOCKS_DBG_LSB _u(7) -#define ACCESSCTRL_CLOCKS_DBG_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_CLOCKS_DMA -// Description : If 1, CLOCKS can be accessed by the DMA, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_CLOCKS_DMA_RESET _u(0x0) -#define ACCESSCTRL_CLOCKS_DMA_BITS _u(0x00000040) -#define ACCESSCTRL_CLOCKS_DMA_MSB _u(6) -#define ACCESSCTRL_CLOCKS_DMA_LSB _u(6) -#define ACCESSCTRL_CLOCKS_DMA_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_CLOCKS_CORE1 -// Description : If 1, CLOCKS can be accessed by core 1, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_CLOCKS_CORE1_RESET _u(0x1) -#define ACCESSCTRL_CLOCKS_CORE1_BITS _u(0x00000020) -#define ACCESSCTRL_CLOCKS_CORE1_MSB _u(5) -#define ACCESSCTRL_CLOCKS_CORE1_LSB _u(5) -#define ACCESSCTRL_CLOCKS_CORE1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_CLOCKS_CORE0 -// Description : If 1, CLOCKS can be accessed by core 0, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_CLOCKS_CORE0_RESET _u(0x1) -#define ACCESSCTRL_CLOCKS_CORE0_BITS _u(0x00000010) -#define ACCESSCTRL_CLOCKS_CORE0_MSB _u(4) -#define ACCESSCTRL_CLOCKS_CORE0_LSB _u(4) -#define ACCESSCTRL_CLOCKS_CORE0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_CLOCKS_SP -// Description : If 1, CLOCKS can be accessed from a Secure, Privileged context. -#define ACCESSCTRL_CLOCKS_SP_RESET _u(0x1) -#define ACCESSCTRL_CLOCKS_SP_BITS _u(0x00000008) -#define ACCESSCTRL_CLOCKS_SP_MSB _u(3) -#define ACCESSCTRL_CLOCKS_SP_LSB _u(3) -#define ACCESSCTRL_CLOCKS_SP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_CLOCKS_SU -// Description : If 1, and SP is also set, CLOCKS can be accessed from a Secure, -// Unprivileged context. -#define ACCESSCTRL_CLOCKS_SU_RESET _u(0x0) -#define ACCESSCTRL_CLOCKS_SU_BITS _u(0x00000004) -#define ACCESSCTRL_CLOCKS_SU_MSB _u(2) -#define ACCESSCTRL_CLOCKS_SU_LSB _u(2) -#define ACCESSCTRL_CLOCKS_SU_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_CLOCKS_NSP -// Description : If 1, CLOCKS can be accessed from a Non-secure, Privileged -// context. -#define ACCESSCTRL_CLOCKS_NSP_RESET _u(0x0) -#define ACCESSCTRL_CLOCKS_NSP_BITS _u(0x00000002) -#define ACCESSCTRL_CLOCKS_NSP_MSB _u(1) -#define ACCESSCTRL_CLOCKS_NSP_LSB _u(1) -#define ACCESSCTRL_CLOCKS_NSP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_CLOCKS_NSU -// Description : If 1, and NSP is also set, CLOCKS can be accessed from a Non- -// secure, Unprivileged context. -// -// This bit is writable from a Non-secure, Privileged context, if -// and only if the NSP bit is set. -#define ACCESSCTRL_CLOCKS_NSU_RESET _u(0x0) -#define ACCESSCTRL_CLOCKS_NSU_BITS _u(0x00000001) -#define ACCESSCTRL_CLOCKS_NSU_MSB _u(0) -#define ACCESSCTRL_CLOCKS_NSU_LSB _u(0) -#define ACCESSCTRL_CLOCKS_NSU_ACCESS "RW" -// ============================================================================= -// Register : ACCESSCTRL_XOSC -// Description : Control whether debugger, DMA, core 0 and core 1 can access -// XOSC, and at what security/privilege levels they can do so. -// -// Defaults to Secure, Privileged processor or debug access only. -// -// This register is writable only from a Secure, Privileged -// processor or debugger, with the exception of the NSU bit, which -// becomes Non-secure-Privileged-writable when the NSP bit is set. -#define ACCESSCTRL_XOSC_OFFSET _u(0x000000c4) -#define ACCESSCTRL_XOSC_BITS _u(0x000000ff) -#define ACCESSCTRL_XOSC_RESET _u(0x000000b8) -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_XOSC_DBG -// Description : If 1, XOSC can be accessed by the debugger, at -// security/privilege levels permitted by SP/NSP/SU/NSU in this -// register. -#define ACCESSCTRL_XOSC_DBG_RESET _u(0x1) -#define ACCESSCTRL_XOSC_DBG_BITS _u(0x00000080) -#define ACCESSCTRL_XOSC_DBG_MSB _u(7) -#define ACCESSCTRL_XOSC_DBG_LSB _u(7) -#define ACCESSCTRL_XOSC_DBG_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_XOSC_DMA -// Description : If 1, XOSC can be accessed by the DMA, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_XOSC_DMA_RESET _u(0x0) -#define ACCESSCTRL_XOSC_DMA_BITS _u(0x00000040) -#define ACCESSCTRL_XOSC_DMA_MSB _u(6) -#define ACCESSCTRL_XOSC_DMA_LSB _u(6) -#define ACCESSCTRL_XOSC_DMA_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_XOSC_CORE1 -// Description : If 1, XOSC can be accessed by core 1, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_XOSC_CORE1_RESET _u(0x1) -#define ACCESSCTRL_XOSC_CORE1_BITS _u(0x00000020) -#define ACCESSCTRL_XOSC_CORE1_MSB _u(5) -#define ACCESSCTRL_XOSC_CORE1_LSB _u(5) -#define ACCESSCTRL_XOSC_CORE1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_XOSC_CORE0 -// Description : If 1, XOSC can be accessed by core 0, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_XOSC_CORE0_RESET _u(0x1) -#define ACCESSCTRL_XOSC_CORE0_BITS _u(0x00000010) -#define ACCESSCTRL_XOSC_CORE0_MSB _u(4) -#define ACCESSCTRL_XOSC_CORE0_LSB _u(4) -#define ACCESSCTRL_XOSC_CORE0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_XOSC_SP -// Description : If 1, XOSC can be accessed from a Secure, Privileged context. -#define ACCESSCTRL_XOSC_SP_RESET _u(0x1) -#define ACCESSCTRL_XOSC_SP_BITS _u(0x00000008) -#define ACCESSCTRL_XOSC_SP_MSB _u(3) -#define ACCESSCTRL_XOSC_SP_LSB _u(3) -#define ACCESSCTRL_XOSC_SP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_XOSC_SU -// Description : If 1, and SP is also set, XOSC can be accessed from a Secure, -// Unprivileged context. -#define ACCESSCTRL_XOSC_SU_RESET _u(0x0) -#define ACCESSCTRL_XOSC_SU_BITS _u(0x00000004) -#define ACCESSCTRL_XOSC_SU_MSB _u(2) -#define ACCESSCTRL_XOSC_SU_LSB _u(2) -#define ACCESSCTRL_XOSC_SU_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_XOSC_NSP -// Description : If 1, XOSC can be accessed from a Non-secure, Privileged -// context. -#define ACCESSCTRL_XOSC_NSP_RESET _u(0x0) -#define ACCESSCTRL_XOSC_NSP_BITS _u(0x00000002) -#define ACCESSCTRL_XOSC_NSP_MSB _u(1) -#define ACCESSCTRL_XOSC_NSP_LSB _u(1) -#define ACCESSCTRL_XOSC_NSP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_XOSC_NSU -// Description : If 1, and NSP is also set, XOSC can be accessed from a Non- -// secure, Unprivileged context. -// -// This bit is writable from a Non-secure, Privileged context, if -// and only if the NSP bit is set. -#define ACCESSCTRL_XOSC_NSU_RESET _u(0x0) -#define ACCESSCTRL_XOSC_NSU_BITS _u(0x00000001) -#define ACCESSCTRL_XOSC_NSU_MSB _u(0) -#define ACCESSCTRL_XOSC_NSU_LSB _u(0) -#define ACCESSCTRL_XOSC_NSU_ACCESS "RW" -// ============================================================================= -// Register : ACCESSCTRL_ROSC -// Description : Control whether debugger, DMA, core 0 and core 1 can access -// ROSC, and at what security/privilege levels they can do so. -// -// Defaults to Secure, Privileged processor or debug access only. -// -// This register is writable only from a Secure, Privileged -// processor or debugger, with the exception of the NSU bit, which -// becomes Non-secure-Privileged-writable when the NSP bit is set. -#define ACCESSCTRL_ROSC_OFFSET _u(0x000000c8) -#define ACCESSCTRL_ROSC_BITS _u(0x000000ff) -#define ACCESSCTRL_ROSC_RESET _u(0x000000b8) -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_ROSC_DBG -// Description : If 1, ROSC can be accessed by the debugger, at -// security/privilege levels permitted by SP/NSP/SU/NSU in this -// register. -#define ACCESSCTRL_ROSC_DBG_RESET _u(0x1) -#define ACCESSCTRL_ROSC_DBG_BITS _u(0x00000080) -#define ACCESSCTRL_ROSC_DBG_MSB _u(7) -#define ACCESSCTRL_ROSC_DBG_LSB _u(7) -#define ACCESSCTRL_ROSC_DBG_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_ROSC_DMA -// Description : If 1, ROSC can be accessed by the DMA, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_ROSC_DMA_RESET _u(0x0) -#define ACCESSCTRL_ROSC_DMA_BITS _u(0x00000040) -#define ACCESSCTRL_ROSC_DMA_MSB _u(6) -#define ACCESSCTRL_ROSC_DMA_LSB _u(6) -#define ACCESSCTRL_ROSC_DMA_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_ROSC_CORE1 -// Description : If 1, ROSC can be accessed by core 1, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_ROSC_CORE1_RESET _u(0x1) -#define ACCESSCTRL_ROSC_CORE1_BITS _u(0x00000020) -#define ACCESSCTRL_ROSC_CORE1_MSB _u(5) -#define ACCESSCTRL_ROSC_CORE1_LSB _u(5) -#define ACCESSCTRL_ROSC_CORE1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_ROSC_CORE0 -// Description : If 1, ROSC can be accessed by core 0, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_ROSC_CORE0_RESET _u(0x1) -#define ACCESSCTRL_ROSC_CORE0_BITS _u(0x00000010) -#define ACCESSCTRL_ROSC_CORE0_MSB _u(4) -#define ACCESSCTRL_ROSC_CORE0_LSB _u(4) -#define ACCESSCTRL_ROSC_CORE0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_ROSC_SP -// Description : If 1, ROSC can be accessed from a Secure, Privileged context. -#define ACCESSCTRL_ROSC_SP_RESET _u(0x1) -#define ACCESSCTRL_ROSC_SP_BITS _u(0x00000008) -#define ACCESSCTRL_ROSC_SP_MSB _u(3) -#define ACCESSCTRL_ROSC_SP_LSB _u(3) -#define ACCESSCTRL_ROSC_SP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_ROSC_SU -// Description : If 1, and SP is also set, ROSC can be accessed from a Secure, -// Unprivileged context. -#define ACCESSCTRL_ROSC_SU_RESET _u(0x0) -#define ACCESSCTRL_ROSC_SU_BITS _u(0x00000004) -#define ACCESSCTRL_ROSC_SU_MSB _u(2) -#define ACCESSCTRL_ROSC_SU_LSB _u(2) -#define ACCESSCTRL_ROSC_SU_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_ROSC_NSP -// Description : If 1, ROSC can be accessed from a Non-secure, Privileged -// context. -#define ACCESSCTRL_ROSC_NSP_RESET _u(0x0) -#define ACCESSCTRL_ROSC_NSP_BITS _u(0x00000002) -#define ACCESSCTRL_ROSC_NSP_MSB _u(1) -#define ACCESSCTRL_ROSC_NSP_LSB _u(1) -#define ACCESSCTRL_ROSC_NSP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_ROSC_NSU -// Description : If 1, and NSP is also set, ROSC can be accessed from a Non- -// secure, Unprivileged context. -// -// This bit is writable from a Non-secure, Privileged context, if -// and only if the NSP bit is set. -#define ACCESSCTRL_ROSC_NSU_RESET _u(0x0) -#define ACCESSCTRL_ROSC_NSU_BITS _u(0x00000001) -#define ACCESSCTRL_ROSC_NSU_MSB _u(0) -#define ACCESSCTRL_ROSC_NSU_LSB _u(0) -#define ACCESSCTRL_ROSC_NSU_ACCESS "RW" -// ============================================================================= -// Register : ACCESSCTRL_PLL_SYS -// Description : Control whether debugger, DMA, core 0 and core 1 can access -// PLL_SYS, and at what security/privilege levels they can do so. -// -// Defaults to Secure, Privileged processor or debug access only. -// -// This register is writable only from a Secure, Privileged -// processor or debugger, with the exception of the NSU bit, which -// becomes Non-secure-Privileged-writable when the NSP bit is set. -#define ACCESSCTRL_PLL_SYS_OFFSET _u(0x000000cc) -#define ACCESSCTRL_PLL_SYS_BITS _u(0x000000ff) -#define ACCESSCTRL_PLL_SYS_RESET _u(0x000000b8) -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_PLL_SYS_DBG -// Description : If 1, PLL_SYS can be accessed by the debugger, at -// security/privilege levels permitted by SP/NSP/SU/NSU in this -// register. -#define ACCESSCTRL_PLL_SYS_DBG_RESET _u(0x1) -#define ACCESSCTRL_PLL_SYS_DBG_BITS _u(0x00000080) -#define ACCESSCTRL_PLL_SYS_DBG_MSB _u(7) -#define ACCESSCTRL_PLL_SYS_DBG_LSB _u(7) -#define ACCESSCTRL_PLL_SYS_DBG_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_PLL_SYS_DMA -// Description : If 1, PLL_SYS can be accessed by the DMA, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_PLL_SYS_DMA_RESET _u(0x0) -#define ACCESSCTRL_PLL_SYS_DMA_BITS _u(0x00000040) -#define ACCESSCTRL_PLL_SYS_DMA_MSB _u(6) -#define ACCESSCTRL_PLL_SYS_DMA_LSB _u(6) -#define ACCESSCTRL_PLL_SYS_DMA_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_PLL_SYS_CORE1 -// Description : If 1, PLL_SYS can be accessed by core 1, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_PLL_SYS_CORE1_RESET _u(0x1) -#define ACCESSCTRL_PLL_SYS_CORE1_BITS _u(0x00000020) -#define ACCESSCTRL_PLL_SYS_CORE1_MSB _u(5) -#define ACCESSCTRL_PLL_SYS_CORE1_LSB _u(5) -#define ACCESSCTRL_PLL_SYS_CORE1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_PLL_SYS_CORE0 -// Description : If 1, PLL_SYS can be accessed by core 0, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_PLL_SYS_CORE0_RESET _u(0x1) -#define ACCESSCTRL_PLL_SYS_CORE0_BITS _u(0x00000010) -#define ACCESSCTRL_PLL_SYS_CORE0_MSB _u(4) -#define ACCESSCTRL_PLL_SYS_CORE0_LSB _u(4) -#define ACCESSCTRL_PLL_SYS_CORE0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_PLL_SYS_SP -// Description : If 1, PLL_SYS can be accessed from a Secure, Privileged -// context. -#define ACCESSCTRL_PLL_SYS_SP_RESET _u(0x1) -#define ACCESSCTRL_PLL_SYS_SP_BITS _u(0x00000008) -#define ACCESSCTRL_PLL_SYS_SP_MSB _u(3) -#define ACCESSCTRL_PLL_SYS_SP_LSB _u(3) -#define ACCESSCTRL_PLL_SYS_SP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_PLL_SYS_SU -// Description : If 1, and SP is also set, PLL_SYS can be accessed from a -// Secure, Unprivileged context. -#define ACCESSCTRL_PLL_SYS_SU_RESET _u(0x0) -#define ACCESSCTRL_PLL_SYS_SU_BITS _u(0x00000004) -#define ACCESSCTRL_PLL_SYS_SU_MSB _u(2) -#define ACCESSCTRL_PLL_SYS_SU_LSB _u(2) -#define ACCESSCTRL_PLL_SYS_SU_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_PLL_SYS_NSP -// Description : If 1, PLL_SYS can be accessed from a Non-secure, Privileged -// context. -#define ACCESSCTRL_PLL_SYS_NSP_RESET _u(0x0) -#define ACCESSCTRL_PLL_SYS_NSP_BITS _u(0x00000002) -#define ACCESSCTRL_PLL_SYS_NSP_MSB _u(1) -#define ACCESSCTRL_PLL_SYS_NSP_LSB _u(1) -#define ACCESSCTRL_PLL_SYS_NSP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_PLL_SYS_NSU -// Description : If 1, and NSP is also set, PLL_SYS can be accessed from a Non- -// secure, Unprivileged context. -// -// This bit is writable from a Non-secure, Privileged context, if -// and only if the NSP bit is set. -#define ACCESSCTRL_PLL_SYS_NSU_RESET _u(0x0) -#define ACCESSCTRL_PLL_SYS_NSU_BITS _u(0x00000001) -#define ACCESSCTRL_PLL_SYS_NSU_MSB _u(0) -#define ACCESSCTRL_PLL_SYS_NSU_LSB _u(0) -#define ACCESSCTRL_PLL_SYS_NSU_ACCESS "RW" -// ============================================================================= -// Register : ACCESSCTRL_PLL_USB -// Description : Control whether debugger, DMA, core 0 and core 1 can access -// PLL_USB, and at what security/privilege levels they can do so. -// -// Defaults to Secure, Privileged processor or debug access only. -// -// This register is writable only from a Secure, Privileged -// processor or debugger, with the exception of the NSU bit, which -// becomes Non-secure-Privileged-writable when the NSP bit is set. -#define ACCESSCTRL_PLL_USB_OFFSET _u(0x000000d0) -#define ACCESSCTRL_PLL_USB_BITS _u(0x000000ff) -#define ACCESSCTRL_PLL_USB_RESET _u(0x000000b8) -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_PLL_USB_DBG -// Description : If 1, PLL_USB can be accessed by the debugger, at -// security/privilege levels permitted by SP/NSP/SU/NSU in this -// register. -#define ACCESSCTRL_PLL_USB_DBG_RESET _u(0x1) -#define ACCESSCTRL_PLL_USB_DBG_BITS _u(0x00000080) -#define ACCESSCTRL_PLL_USB_DBG_MSB _u(7) -#define ACCESSCTRL_PLL_USB_DBG_LSB _u(7) -#define ACCESSCTRL_PLL_USB_DBG_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_PLL_USB_DMA -// Description : If 1, PLL_USB can be accessed by the DMA, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_PLL_USB_DMA_RESET _u(0x0) -#define ACCESSCTRL_PLL_USB_DMA_BITS _u(0x00000040) -#define ACCESSCTRL_PLL_USB_DMA_MSB _u(6) -#define ACCESSCTRL_PLL_USB_DMA_LSB _u(6) -#define ACCESSCTRL_PLL_USB_DMA_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_PLL_USB_CORE1 -// Description : If 1, PLL_USB can be accessed by core 1, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_PLL_USB_CORE1_RESET _u(0x1) -#define ACCESSCTRL_PLL_USB_CORE1_BITS _u(0x00000020) -#define ACCESSCTRL_PLL_USB_CORE1_MSB _u(5) -#define ACCESSCTRL_PLL_USB_CORE1_LSB _u(5) -#define ACCESSCTRL_PLL_USB_CORE1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_PLL_USB_CORE0 -// Description : If 1, PLL_USB can be accessed by core 0, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_PLL_USB_CORE0_RESET _u(0x1) -#define ACCESSCTRL_PLL_USB_CORE0_BITS _u(0x00000010) -#define ACCESSCTRL_PLL_USB_CORE0_MSB _u(4) -#define ACCESSCTRL_PLL_USB_CORE0_LSB _u(4) -#define ACCESSCTRL_PLL_USB_CORE0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_PLL_USB_SP -// Description : If 1, PLL_USB can be accessed from a Secure, Privileged -// context. -#define ACCESSCTRL_PLL_USB_SP_RESET _u(0x1) -#define ACCESSCTRL_PLL_USB_SP_BITS _u(0x00000008) -#define ACCESSCTRL_PLL_USB_SP_MSB _u(3) -#define ACCESSCTRL_PLL_USB_SP_LSB _u(3) -#define ACCESSCTRL_PLL_USB_SP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_PLL_USB_SU -// Description : If 1, and SP is also set, PLL_USB can be accessed from a -// Secure, Unprivileged context. -#define ACCESSCTRL_PLL_USB_SU_RESET _u(0x0) -#define ACCESSCTRL_PLL_USB_SU_BITS _u(0x00000004) -#define ACCESSCTRL_PLL_USB_SU_MSB _u(2) -#define ACCESSCTRL_PLL_USB_SU_LSB _u(2) -#define ACCESSCTRL_PLL_USB_SU_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_PLL_USB_NSP -// Description : If 1, PLL_USB can be accessed from a Non-secure, Privileged -// context. -#define ACCESSCTRL_PLL_USB_NSP_RESET _u(0x0) -#define ACCESSCTRL_PLL_USB_NSP_BITS _u(0x00000002) -#define ACCESSCTRL_PLL_USB_NSP_MSB _u(1) -#define ACCESSCTRL_PLL_USB_NSP_LSB _u(1) -#define ACCESSCTRL_PLL_USB_NSP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_PLL_USB_NSU -// Description : If 1, and NSP is also set, PLL_USB can be accessed from a Non- -// secure, Unprivileged context. -// -// This bit is writable from a Non-secure, Privileged context, if -// and only if the NSP bit is set. -#define ACCESSCTRL_PLL_USB_NSU_RESET _u(0x0) -#define ACCESSCTRL_PLL_USB_NSU_BITS _u(0x00000001) -#define ACCESSCTRL_PLL_USB_NSU_MSB _u(0) -#define ACCESSCTRL_PLL_USB_NSU_LSB _u(0) -#define ACCESSCTRL_PLL_USB_NSU_ACCESS "RW" -// ============================================================================= -// Register : ACCESSCTRL_TICKS -// Description : Control whether debugger, DMA, core 0 and core 1 can access -// TICKS, and at what security/privilege levels they can do so. -// -// Defaults to Secure, Privileged processor or debug access only. -// -// This register is writable only from a Secure, Privileged -// processor or debugger, with the exception of the NSU bit, which -// becomes Non-secure-Privileged-writable when the NSP bit is set. -#define ACCESSCTRL_TICKS_OFFSET _u(0x000000d4) -#define ACCESSCTRL_TICKS_BITS _u(0x000000ff) -#define ACCESSCTRL_TICKS_RESET _u(0x000000b8) -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_TICKS_DBG -// Description : If 1, TICKS can be accessed by the debugger, at -// security/privilege levels permitted by SP/NSP/SU/NSU in this -// register. -#define ACCESSCTRL_TICKS_DBG_RESET _u(0x1) -#define ACCESSCTRL_TICKS_DBG_BITS _u(0x00000080) -#define ACCESSCTRL_TICKS_DBG_MSB _u(7) -#define ACCESSCTRL_TICKS_DBG_LSB _u(7) -#define ACCESSCTRL_TICKS_DBG_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_TICKS_DMA -// Description : If 1, TICKS can be accessed by the DMA, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_TICKS_DMA_RESET _u(0x0) -#define ACCESSCTRL_TICKS_DMA_BITS _u(0x00000040) -#define ACCESSCTRL_TICKS_DMA_MSB _u(6) -#define ACCESSCTRL_TICKS_DMA_LSB _u(6) -#define ACCESSCTRL_TICKS_DMA_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_TICKS_CORE1 -// Description : If 1, TICKS can be accessed by core 1, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_TICKS_CORE1_RESET _u(0x1) -#define ACCESSCTRL_TICKS_CORE1_BITS _u(0x00000020) -#define ACCESSCTRL_TICKS_CORE1_MSB _u(5) -#define ACCESSCTRL_TICKS_CORE1_LSB _u(5) -#define ACCESSCTRL_TICKS_CORE1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_TICKS_CORE0 -// Description : If 1, TICKS can be accessed by core 0, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_TICKS_CORE0_RESET _u(0x1) -#define ACCESSCTRL_TICKS_CORE0_BITS _u(0x00000010) -#define ACCESSCTRL_TICKS_CORE0_MSB _u(4) -#define ACCESSCTRL_TICKS_CORE0_LSB _u(4) -#define ACCESSCTRL_TICKS_CORE0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_TICKS_SP -// Description : If 1, TICKS can be accessed from a Secure, Privileged context. -#define ACCESSCTRL_TICKS_SP_RESET _u(0x1) -#define ACCESSCTRL_TICKS_SP_BITS _u(0x00000008) -#define ACCESSCTRL_TICKS_SP_MSB _u(3) -#define ACCESSCTRL_TICKS_SP_LSB _u(3) -#define ACCESSCTRL_TICKS_SP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_TICKS_SU -// Description : If 1, and SP is also set, TICKS can be accessed from a Secure, -// Unprivileged context. -#define ACCESSCTRL_TICKS_SU_RESET _u(0x0) -#define ACCESSCTRL_TICKS_SU_BITS _u(0x00000004) -#define ACCESSCTRL_TICKS_SU_MSB _u(2) -#define ACCESSCTRL_TICKS_SU_LSB _u(2) -#define ACCESSCTRL_TICKS_SU_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_TICKS_NSP -// Description : If 1, TICKS can be accessed from a Non-secure, Privileged -// context. -#define ACCESSCTRL_TICKS_NSP_RESET _u(0x0) -#define ACCESSCTRL_TICKS_NSP_BITS _u(0x00000002) -#define ACCESSCTRL_TICKS_NSP_MSB _u(1) -#define ACCESSCTRL_TICKS_NSP_LSB _u(1) -#define ACCESSCTRL_TICKS_NSP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_TICKS_NSU -// Description : If 1, and NSP is also set, TICKS can be accessed from a Non- -// secure, Unprivileged context. -// -// This bit is writable from a Non-secure, Privileged context, if -// and only if the NSP bit is set. -#define ACCESSCTRL_TICKS_NSU_RESET _u(0x0) -#define ACCESSCTRL_TICKS_NSU_BITS _u(0x00000001) -#define ACCESSCTRL_TICKS_NSU_MSB _u(0) -#define ACCESSCTRL_TICKS_NSU_LSB _u(0) -#define ACCESSCTRL_TICKS_NSU_ACCESS "RW" -// ============================================================================= -// Register : ACCESSCTRL_WATCHDOG -// Description : Control whether debugger, DMA, core 0 and core 1 can access -// WATCHDOG, and at what security/privilege levels they can do so. -// -// Defaults to Secure, Privileged processor or debug access only. -// -// This register is writable only from a Secure, Privileged -// processor or debugger, with the exception of the NSU bit, which -// becomes Non-secure-Privileged-writable when the NSP bit is set. -#define ACCESSCTRL_WATCHDOG_OFFSET _u(0x000000d8) -#define ACCESSCTRL_WATCHDOG_BITS _u(0x000000ff) -#define ACCESSCTRL_WATCHDOG_RESET _u(0x000000b8) -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_WATCHDOG_DBG -// Description : If 1, WATCHDOG can be accessed by the debugger, at -// security/privilege levels permitted by SP/NSP/SU/NSU in this -// register. -#define ACCESSCTRL_WATCHDOG_DBG_RESET _u(0x1) -#define ACCESSCTRL_WATCHDOG_DBG_BITS _u(0x00000080) -#define ACCESSCTRL_WATCHDOG_DBG_MSB _u(7) -#define ACCESSCTRL_WATCHDOG_DBG_LSB _u(7) -#define ACCESSCTRL_WATCHDOG_DBG_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_WATCHDOG_DMA -// Description : If 1, WATCHDOG can be accessed by the DMA, at -// security/privilege levels permitted by SP/NSP/SU/NSU in this -// register. -#define ACCESSCTRL_WATCHDOG_DMA_RESET _u(0x0) -#define ACCESSCTRL_WATCHDOG_DMA_BITS _u(0x00000040) -#define ACCESSCTRL_WATCHDOG_DMA_MSB _u(6) -#define ACCESSCTRL_WATCHDOG_DMA_LSB _u(6) -#define ACCESSCTRL_WATCHDOG_DMA_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_WATCHDOG_CORE1 -// Description : If 1, WATCHDOG can be accessed by core 1, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_WATCHDOG_CORE1_RESET _u(0x1) -#define ACCESSCTRL_WATCHDOG_CORE1_BITS _u(0x00000020) -#define ACCESSCTRL_WATCHDOG_CORE1_MSB _u(5) -#define ACCESSCTRL_WATCHDOG_CORE1_LSB _u(5) -#define ACCESSCTRL_WATCHDOG_CORE1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_WATCHDOG_CORE0 -// Description : If 1, WATCHDOG can be accessed by core 0, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_WATCHDOG_CORE0_RESET _u(0x1) -#define ACCESSCTRL_WATCHDOG_CORE0_BITS _u(0x00000010) -#define ACCESSCTRL_WATCHDOG_CORE0_MSB _u(4) -#define ACCESSCTRL_WATCHDOG_CORE0_LSB _u(4) -#define ACCESSCTRL_WATCHDOG_CORE0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_WATCHDOG_SP -// Description : If 1, WATCHDOG can be accessed from a Secure, Privileged -// context. -#define ACCESSCTRL_WATCHDOG_SP_RESET _u(0x1) -#define ACCESSCTRL_WATCHDOG_SP_BITS _u(0x00000008) -#define ACCESSCTRL_WATCHDOG_SP_MSB _u(3) -#define ACCESSCTRL_WATCHDOG_SP_LSB _u(3) -#define ACCESSCTRL_WATCHDOG_SP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_WATCHDOG_SU -// Description : If 1, and SP is also set, WATCHDOG can be accessed from a -// Secure, Unprivileged context. -#define ACCESSCTRL_WATCHDOG_SU_RESET _u(0x0) -#define ACCESSCTRL_WATCHDOG_SU_BITS _u(0x00000004) -#define ACCESSCTRL_WATCHDOG_SU_MSB _u(2) -#define ACCESSCTRL_WATCHDOG_SU_LSB _u(2) -#define ACCESSCTRL_WATCHDOG_SU_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_WATCHDOG_NSP -// Description : If 1, WATCHDOG can be accessed from a Non-secure, Privileged -// context. -#define ACCESSCTRL_WATCHDOG_NSP_RESET _u(0x0) -#define ACCESSCTRL_WATCHDOG_NSP_BITS _u(0x00000002) -#define ACCESSCTRL_WATCHDOG_NSP_MSB _u(1) -#define ACCESSCTRL_WATCHDOG_NSP_LSB _u(1) -#define ACCESSCTRL_WATCHDOG_NSP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_WATCHDOG_NSU -// Description : If 1, and NSP is also set, WATCHDOG can be accessed from a Non- -// secure, Unprivileged context. -// -// This bit is writable from a Non-secure, Privileged context, if -// and only if the NSP bit is set. -#define ACCESSCTRL_WATCHDOG_NSU_RESET _u(0x0) -#define ACCESSCTRL_WATCHDOG_NSU_BITS _u(0x00000001) -#define ACCESSCTRL_WATCHDOG_NSU_MSB _u(0) -#define ACCESSCTRL_WATCHDOG_NSU_LSB _u(0) -#define ACCESSCTRL_WATCHDOG_NSU_ACCESS "RW" -// ============================================================================= -// Register : ACCESSCTRL_RSM -// Description : Control whether debugger, DMA, core 0 and core 1 can access -// RSM, and at what security/privilege levels they can do so. -// -// Defaults to Secure, Privileged processor or debug access only. -// -// This register is writable only from a Secure, Privileged -// processor or debugger, with the exception of the NSU bit, which -// becomes Non-secure-Privileged-writable when the NSP bit is set. -#define ACCESSCTRL_RSM_OFFSET _u(0x000000dc) -#define ACCESSCTRL_RSM_BITS _u(0x000000ff) -#define ACCESSCTRL_RSM_RESET _u(0x000000b8) -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_RSM_DBG -// Description : If 1, RSM can be accessed by the debugger, at -// security/privilege levels permitted by SP/NSP/SU/NSU in this -// register. -#define ACCESSCTRL_RSM_DBG_RESET _u(0x1) -#define ACCESSCTRL_RSM_DBG_BITS _u(0x00000080) -#define ACCESSCTRL_RSM_DBG_MSB _u(7) -#define ACCESSCTRL_RSM_DBG_LSB _u(7) -#define ACCESSCTRL_RSM_DBG_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_RSM_DMA -// Description : If 1, RSM can be accessed by the DMA, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_RSM_DMA_RESET _u(0x0) -#define ACCESSCTRL_RSM_DMA_BITS _u(0x00000040) -#define ACCESSCTRL_RSM_DMA_MSB _u(6) -#define ACCESSCTRL_RSM_DMA_LSB _u(6) -#define ACCESSCTRL_RSM_DMA_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_RSM_CORE1 -// Description : If 1, RSM can be accessed by core 1, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_RSM_CORE1_RESET _u(0x1) -#define ACCESSCTRL_RSM_CORE1_BITS _u(0x00000020) -#define ACCESSCTRL_RSM_CORE1_MSB _u(5) -#define ACCESSCTRL_RSM_CORE1_LSB _u(5) -#define ACCESSCTRL_RSM_CORE1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_RSM_CORE0 -// Description : If 1, RSM can be accessed by core 0, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_RSM_CORE0_RESET _u(0x1) -#define ACCESSCTRL_RSM_CORE0_BITS _u(0x00000010) -#define ACCESSCTRL_RSM_CORE0_MSB _u(4) -#define ACCESSCTRL_RSM_CORE0_LSB _u(4) -#define ACCESSCTRL_RSM_CORE0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_RSM_SP -// Description : If 1, RSM can be accessed from a Secure, Privileged context. -#define ACCESSCTRL_RSM_SP_RESET _u(0x1) -#define ACCESSCTRL_RSM_SP_BITS _u(0x00000008) -#define ACCESSCTRL_RSM_SP_MSB _u(3) -#define ACCESSCTRL_RSM_SP_LSB _u(3) -#define ACCESSCTRL_RSM_SP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_RSM_SU -// Description : If 1, and SP is also set, RSM can be accessed from a Secure, -// Unprivileged context. -#define ACCESSCTRL_RSM_SU_RESET _u(0x0) -#define ACCESSCTRL_RSM_SU_BITS _u(0x00000004) -#define ACCESSCTRL_RSM_SU_MSB _u(2) -#define ACCESSCTRL_RSM_SU_LSB _u(2) -#define ACCESSCTRL_RSM_SU_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_RSM_NSP -// Description : If 1, RSM can be accessed from a Non-secure, Privileged -// context. -#define ACCESSCTRL_RSM_NSP_RESET _u(0x0) -#define ACCESSCTRL_RSM_NSP_BITS _u(0x00000002) -#define ACCESSCTRL_RSM_NSP_MSB _u(1) -#define ACCESSCTRL_RSM_NSP_LSB _u(1) -#define ACCESSCTRL_RSM_NSP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_RSM_NSU -// Description : If 1, and NSP is also set, RSM can be accessed from a Non- -// secure, Unprivileged context. -// -// This bit is writable from a Non-secure, Privileged context, if -// and only if the NSP bit is set. -#define ACCESSCTRL_RSM_NSU_RESET _u(0x0) -#define ACCESSCTRL_RSM_NSU_BITS _u(0x00000001) -#define ACCESSCTRL_RSM_NSU_MSB _u(0) -#define ACCESSCTRL_RSM_NSU_LSB _u(0) -#define ACCESSCTRL_RSM_NSU_ACCESS "RW" -// ============================================================================= -// Register : ACCESSCTRL_XIP_CTRL -// Description : Control whether debugger, DMA, core 0 and core 1 can access -// XIP_CTRL, and at what security/privilege levels they can do so. -// -// Defaults to Secure, Privileged processor or debug access only. -// -// This register is writable only from a Secure, Privileged -// processor or debugger, with the exception of the NSU bit, which -// becomes Non-secure-Privileged-writable when the NSP bit is set. -#define ACCESSCTRL_XIP_CTRL_OFFSET _u(0x000000e0) -#define ACCESSCTRL_XIP_CTRL_BITS _u(0x000000ff) -#define ACCESSCTRL_XIP_CTRL_RESET _u(0x000000b8) -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_XIP_CTRL_DBG -// Description : If 1, XIP_CTRL can be accessed by the debugger, at -// security/privilege levels permitted by SP/NSP/SU/NSU in this -// register. -#define ACCESSCTRL_XIP_CTRL_DBG_RESET _u(0x1) -#define ACCESSCTRL_XIP_CTRL_DBG_BITS _u(0x00000080) -#define ACCESSCTRL_XIP_CTRL_DBG_MSB _u(7) -#define ACCESSCTRL_XIP_CTRL_DBG_LSB _u(7) -#define ACCESSCTRL_XIP_CTRL_DBG_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_XIP_CTRL_DMA -// Description : If 1, XIP_CTRL can be accessed by the DMA, at -// security/privilege levels permitted by SP/NSP/SU/NSU in this -// register. -#define ACCESSCTRL_XIP_CTRL_DMA_RESET _u(0x0) -#define ACCESSCTRL_XIP_CTRL_DMA_BITS _u(0x00000040) -#define ACCESSCTRL_XIP_CTRL_DMA_MSB _u(6) -#define ACCESSCTRL_XIP_CTRL_DMA_LSB _u(6) -#define ACCESSCTRL_XIP_CTRL_DMA_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_XIP_CTRL_CORE1 -// Description : If 1, XIP_CTRL can be accessed by core 1, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_XIP_CTRL_CORE1_RESET _u(0x1) -#define ACCESSCTRL_XIP_CTRL_CORE1_BITS _u(0x00000020) -#define ACCESSCTRL_XIP_CTRL_CORE1_MSB _u(5) -#define ACCESSCTRL_XIP_CTRL_CORE1_LSB _u(5) -#define ACCESSCTRL_XIP_CTRL_CORE1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_XIP_CTRL_CORE0 -// Description : If 1, XIP_CTRL can be accessed by core 0, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_XIP_CTRL_CORE0_RESET _u(0x1) -#define ACCESSCTRL_XIP_CTRL_CORE0_BITS _u(0x00000010) -#define ACCESSCTRL_XIP_CTRL_CORE0_MSB _u(4) -#define ACCESSCTRL_XIP_CTRL_CORE0_LSB _u(4) -#define ACCESSCTRL_XIP_CTRL_CORE0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_XIP_CTRL_SP -// Description : If 1, XIP_CTRL can be accessed from a Secure, Privileged -// context. -#define ACCESSCTRL_XIP_CTRL_SP_RESET _u(0x1) -#define ACCESSCTRL_XIP_CTRL_SP_BITS _u(0x00000008) -#define ACCESSCTRL_XIP_CTRL_SP_MSB _u(3) -#define ACCESSCTRL_XIP_CTRL_SP_LSB _u(3) -#define ACCESSCTRL_XIP_CTRL_SP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_XIP_CTRL_SU -// Description : If 1, and SP is also set, XIP_CTRL can be accessed from a -// Secure, Unprivileged context. -#define ACCESSCTRL_XIP_CTRL_SU_RESET _u(0x0) -#define ACCESSCTRL_XIP_CTRL_SU_BITS _u(0x00000004) -#define ACCESSCTRL_XIP_CTRL_SU_MSB _u(2) -#define ACCESSCTRL_XIP_CTRL_SU_LSB _u(2) -#define ACCESSCTRL_XIP_CTRL_SU_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_XIP_CTRL_NSP -// Description : If 1, XIP_CTRL can be accessed from a Non-secure, Privileged -// context. -#define ACCESSCTRL_XIP_CTRL_NSP_RESET _u(0x0) -#define ACCESSCTRL_XIP_CTRL_NSP_BITS _u(0x00000002) -#define ACCESSCTRL_XIP_CTRL_NSP_MSB _u(1) -#define ACCESSCTRL_XIP_CTRL_NSP_LSB _u(1) -#define ACCESSCTRL_XIP_CTRL_NSP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_XIP_CTRL_NSU -// Description : If 1, and NSP is also set, XIP_CTRL can be accessed from a Non- -// secure, Unprivileged context. -// -// This bit is writable from a Non-secure, Privileged context, if -// and only if the NSP bit is set. -#define ACCESSCTRL_XIP_CTRL_NSU_RESET _u(0x0) -#define ACCESSCTRL_XIP_CTRL_NSU_BITS _u(0x00000001) -#define ACCESSCTRL_XIP_CTRL_NSU_MSB _u(0) -#define ACCESSCTRL_XIP_CTRL_NSU_LSB _u(0) -#define ACCESSCTRL_XIP_CTRL_NSU_ACCESS "RW" -// ============================================================================= -// Register : ACCESSCTRL_XIP_QMI -// Description : Control whether debugger, DMA, core 0 and core 1 can access -// XIP_QMI, and at what security/privilege levels they can do so. -// -// Defaults to Secure, Privileged processor or debug access only. -// -// This register is writable only from a Secure, Privileged -// processor or debugger, with the exception of the NSU bit, which -// becomes Non-secure-Privileged-writable when the NSP bit is set. -#define ACCESSCTRL_XIP_QMI_OFFSET _u(0x000000e4) -#define ACCESSCTRL_XIP_QMI_BITS _u(0x000000ff) -#define ACCESSCTRL_XIP_QMI_RESET _u(0x000000b8) -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_XIP_QMI_DBG -// Description : If 1, XIP_QMI can be accessed by the debugger, at -// security/privilege levels permitted by SP/NSP/SU/NSU in this -// register. -#define ACCESSCTRL_XIP_QMI_DBG_RESET _u(0x1) -#define ACCESSCTRL_XIP_QMI_DBG_BITS _u(0x00000080) -#define ACCESSCTRL_XIP_QMI_DBG_MSB _u(7) -#define ACCESSCTRL_XIP_QMI_DBG_LSB _u(7) -#define ACCESSCTRL_XIP_QMI_DBG_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_XIP_QMI_DMA -// Description : If 1, XIP_QMI can be accessed by the DMA, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_XIP_QMI_DMA_RESET _u(0x0) -#define ACCESSCTRL_XIP_QMI_DMA_BITS _u(0x00000040) -#define ACCESSCTRL_XIP_QMI_DMA_MSB _u(6) -#define ACCESSCTRL_XIP_QMI_DMA_LSB _u(6) -#define ACCESSCTRL_XIP_QMI_DMA_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_XIP_QMI_CORE1 -// Description : If 1, XIP_QMI can be accessed by core 1, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_XIP_QMI_CORE1_RESET _u(0x1) -#define ACCESSCTRL_XIP_QMI_CORE1_BITS _u(0x00000020) -#define ACCESSCTRL_XIP_QMI_CORE1_MSB _u(5) -#define ACCESSCTRL_XIP_QMI_CORE1_LSB _u(5) -#define ACCESSCTRL_XIP_QMI_CORE1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_XIP_QMI_CORE0 -// Description : If 1, XIP_QMI can be accessed by core 0, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_XIP_QMI_CORE0_RESET _u(0x1) -#define ACCESSCTRL_XIP_QMI_CORE0_BITS _u(0x00000010) -#define ACCESSCTRL_XIP_QMI_CORE0_MSB _u(4) -#define ACCESSCTRL_XIP_QMI_CORE0_LSB _u(4) -#define ACCESSCTRL_XIP_QMI_CORE0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_XIP_QMI_SP -// Description : If 1, XIP_QMI can be accessed from a Secure, Privileged -// context. -#define ACCESSCTRL_XIP_QMI_SP_RESET _u(0x1) -#define ACCESSCTRL_XIP_QMI_SP_BITS _u(0x00000008) -#define ACCESSCTRL_XIP_QMI_SP_MSB _u(3) -#define ACCESSCTRL_XIP_QMI_SP_LSB _u(3) -#define ACCESSCTRL_XIP_QMI_SP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_XIP_QMI_SU -// Description : If 1, and SP is also set, XIP_QMI can be accessed from a -// Secure, Unprivileged context. -#define ACCESSCTRL_XIP_QMI_SU_RESET _u(0x0) -#define ACCESSCTRL_XIP_QMI_SU_BITS _u(0x00000004) -#define ACCESSCTRL_XIP_QMI_SU_MSB _u(2) -#define ACCESSCTRL_XIP_QMI_SU_LSB _u(2) -#define ACCESSCTRL_XIP_QMI_SU_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_XIP_QMI_NSP -// Description : If 1, XIP_QMI can be accessed from a Non-secure, Privileged -// context. -#define ACCESSCTRL_XIP_QMI_NSP_RESET _u(0x0) -#define ACCESSCTRL_XIP_QMI_NSP_BITS _u(0x00000002) -#define ACCESSCTRL_XIP_QMI_NSP_MSB _u(1) -#define ACCESSCTRL_XIP_QMI_NSP_LSB _u(1) -#define ACCESSCTRL_XIP_QMI_NSP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_XIP_QMI_NSU -// Description : If 1, and NSP is also set, XIP_QMI can be accessed from a Non- -// secure, Unprivileged context. -// -// This bit is writable from a Non-secure, Privileged context, if -// and only if the NSP bit is set. -#define ACCESSCTRL_XIP_QMI_NSU_RESET _u(0x0) -#define ACCESSCTRL_XIP_QMI_NSU_BITS _u(0x00000001) -#define ACCESSCTRL_XIP_QMI_NSU_MSB _u(0) -#define ACCESSCTRL_XIP_QMI_NSU_LSB _u(0) -#define ACCESSCTRL_XIP_QMI_NSU_ACCESS "RW" -// ============================================================================= -// Register : ACCESSCTRL_XIP_AUX -// Description : Control whether debugger, DMA, core 0 and core 1 can access -// XIP_AUX, and at what security/privilege levels they can do so. -// -// Defaults to Secure, Privileged access only. -// -// This register is writable only from a Secure, Privileged -// processor or debugger, with the exception of the NSU bit, which -// becomes Non-secure-Privileged-writable when the NSP bit is set. -#define ACCESSCTRL_XIP_AUX_OFFSET _u(0x000000e8) -#define ACCESSCTRL_XIP_AUX_BITS _u(0x000000ff) -#define ACCESSCTRL_XIP_AUX_RESET _u(0x000000f8) -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_XIP_AUX_DBG -// Description : If 1, XIP_AUX can be accessed by the debugger, at -// security/privilege levels permitted by SP/NSP/SU/NSU in this -// register. -#define ACCESSCTRL_XIP_AUX_DBG_RESET _u(0x1) -#define ACCESSCTRL_XIP_AUX_DBG_BITS _u(0x00000080) -#define ACCESSCTRL_XIP_AUX_DBG_MSB _u(7) -#define ACCESSCTRL_XIP_AUX_DBG_LSB _u(7) -#define ACCESSCTRL_XIP_AUX_DBG_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_XIP_AUX_DMA -// Description : If 1, XIP_AUX can be accessed by the DMA, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_XIP_AUX_DMA_RESET _u(0x1) -#define ACCESSCTRL_XIP_AUX_DMA_BITS _u(0x00000040) -#define ACCESSCTRL_XIP_AUX_DMA_MSB _u(6) -#define ACCESSCTRL_XIP_AUX_DMA_LSB _u(6) -#define ACCESSCTRL_XIP_AUX_DMA_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_XIP_AUX_CORE1 -// Description : If 1, XIP_AUX can be accessed by core 1, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_XIP_AUX_CORE1_RESET _u(0x1) -#define ACCESSCTRL_XIP_AUX_CORE1_BITS _u(0x00000020) -#define ACCESSCTRL_XIP_AUX_CORE1_MSB _u(5) -#define ACCESSCTRL_XIP_AUX_CORE1_LSB _u(5) -#define ACCESSCTRL_XIP_AUX_CORE1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_XIP_AUX_CORE0 -// Description : If 1, XIP_AUX can be accessed by core 0, at security/privilege -// levels permitted by SP/NSP/SU/NSU in this register. -#define ACCESSCTRL_XIP_AUX_CORE0_RESET _u(0x1) -#define ACCESSCTRL_XIP_AUX_CORE0_BITS _u(0x00000010) -#define ACCESSCTRL_XIP_AUX_CORE0_MSB _u(4) -#define ACCESSCTRL_XIP_AUX_CORE0_LSB _u(4) -#define ACCESSCTRL_XIP_AUX_CORE0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_XIP_AUX_SP -// Description : If 1, XIP_AUX can be accessed from a Secure, Privileged -// context. -#define ACCESSCTRL_XIP_AUX_SP_RESET _u(0x1) -#define ACCESSCTRL_XIP_AUX_SP_BITS _u(0x00000008) -#define ACCESSCTRL_XIP_AUX_SP_MSB _u(3) -#define ACCESSCTRL_XIP_AUX_SP_LSB _u(3) -#define ACCESSCTRL_XIP_AUX_SP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_XIP_AUX_SU -// Description : If 1, and SP is also set, XIP_AUX can be accessed from a -// Secure, Unprivileged context. -#define ACCESSCTRL_XIP_AUX_SU_RESET _u(0x0) -#define ACCESSCTRL_XIP_AUX_SU_BITS _u(0x00000004) -#define ACCESSCTRL_XIP_AUX_SU_MSB _u(2) -#define ACCESSCTRL_XIP_AUX_SU_LSB _u(2) -#define ACCESSCTRL_XIP_AUX_SU_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_XIP_AUX_NSP -// Description : If 1, XIP_AUX can be accessed from a Non-secure, Privileged -// context. -#define ACCESSCTRL_XIP_AUX_NSP_RESET _u(0x0) -#define ACCESSCTRL_XIP_AUX_NSP_BITS _u(0x00000002) -#define ACCESSCTRL_XIP_AUX_NSP_MSB _u(1) -#define ACCESSCTRL_XIP_AUX_NSP_LSB _u(1) -#define ACCESSCTRL_XIP_AUX_NSP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ACCESSCTRL_XIP_AUX_NSU -// Description : If 1, and NSP is also set, XIP_AUX can be accessed from a Non- -// secure, Unprivileged context. -// -// This bit is writable from a Non-secure, Privileged context, if -// and only if the NSP bit is set. -#define ACCESSCTRL_XIP_AUX_NSU_RESET _u(0x0) -#define ACCESSCTRL_XIP_AUX_NSU_BITS _u(0x00000001) -#define ACCESSCTRL_XIP_AUX_NSU_MSB _u(0) -#define ACCESSCTRL_XIP_AUX_NSU_LSB _u(0) -#define ACCESSCTRL_XIP_AUX_NSU_ACCESS "RW" -// ============================================================================= -#endif // _HARDWARE_REGS_ACCESSCTRL_H - diff --git a/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/adc.h b/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/adc.h deleted file mode 100644 index 1778d502df..0000000000 --- a/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/adc.h +++ /dev/null @@ -1,316 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -// ============================================================================= -// Register block : ADC -// Version : 2 -// Bus type : apb -// Description : Control and data interface to SAR ADC -// ============================================================================= -#ifndef _HARDWARE_REGS_ADC_H -#define _HARDWARE_REGS_ADC_H -// ============================================================================= -// Register : ADC_CS -// Description : ADC Control and Status -#define ADC_CS_OFFSET _u(0x00000000) -#define ADC_CS_BITS _u(0x01fff70f) -#define ADC_CS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : ADC_CS_RROBIN -// Description : Round-robin sampling. 1 bit per channel. Set all bits to 0 to -// disable. -// Otherwise, the ADC will cycle through each enabled channel in a -// round-robin fashion. -// The first channel to be sampled will be the one currently -// indicated by AINSEL. -// AINSEL will be updated after each conversion with the newly- -// selected channel. -#define ADC_CS_RROBIN_RESET _u(0x000) -#define ADC_CS_RROBIN_BITS _u(0x01ff0000) -#define ADC_CS_RROBIN_MSB _u(24) -#define ADC_CS_RROBIN_LSB _u(16) -#define ADC_CS_RROBIN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ADC_CS_AINSEL -// Description : Select analog mux input. Updated automatically in round-robin -// mode. -// This is corrected for the package option so only ADC channels -// which are bonded are available, and in the correct order -#define ADC_CS_AINSEL_RESET _u(0x0) -#define ADC_CS_AINSEL_BITS _u(0x0000f000) -#define ADC_CS_AINSEL_MSB _u(15) -#define ADC_CS_AINSEL_LSB _u(12) -#define ADC_CS_AINSEL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ADC_CS_ERR_STICKY -// Description : Some past ADC conversion encountered an error. Write 1 to -// clear. -#define ADC_CS_ERR_STICKY_RESET _u(0x0) -#define ADC_CS_ERR_STICKY_BITS _u(0x00000400) -#define ADC_CS_ERR_STICKY_MSB _u(10) -#define ADC_CS_ERR_STICKY_LSB _u(10) -#define ADC_CS_ERR_STICKY_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : ADC_CS_ERR -// Description : The most recent ADC conversion encountered an error; result is -// undefined or noisy. -#define ADC_CS_ERR_RESET _u(0x0) -#define ADC_CS_ERR_BITS _u(0x00000200) -#define ADC_CS_ERR_MSB _u(9) -#define ADC_CS_ERR_LSB _u(9) -#define ADC_CS_ERR_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : ADC_CS_READY -// Description : 1 if the ADC is ready to start a new conversion. Implies any -// previous conversion has completed. -// 0 whilst conversion in progress. -#define ADC_CS_READY_RESET _u(0x0) -#define ADC_CS_READY_BITS _u(0x00000100) -#define ADC_CS_READY_MSB _u(8) -#define ADC_CS_READY_LSB _u(8) -#define ADC_CS_READY_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : ADC_CS_START_MANY -// Description : Continuously perform conversions whilst this bit is 1. A new -// conversion will start immediately after the previous finishes. -#define ADC_CS_START_MANY_RESET _u(0x0) -#define ADC_CS_START_MANY_BITS _u(0x00000008) -#define ADC_CS_START_MANY_MSB _u(3) -#define ADC_CS_START_MANY_LSB _u(3) -#define ADC_CS_START_MANY_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ADC_CS_START_ONCE -// Description : Start a single conversion. Self-clearing. Ignored if start_many -// is asserted. -#define ADC_CS_START_ONCE_RESET _u(0x0) -#define ADC_CS_START_ONCE_BITS _u(0x00000004) -#define ADC_CS_START_ONCE_MSB _u(2) -#define ADC_CS_START_ONCE_LSB _u(2) -#define ADC_CS_START_ONCE_ACCESS "SC" -// ----------------------------------------------------------------------------- -// Field : ADC_CS_TS_EN -// Description : Power on temperature sensor. 1 - enabled. 0 - disabled. -#define ADC_CS_TS_EN_RESET _u(0x0) -#define ADC_CS_TS_EN_BITS _u(0x00000002) -#define ADC_CS_TS_EN_MSB _u(1) -#define ADC_CS_TS_EN_LSB _u(1) -#define ADC_CS_TS_EN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ADC_CS_EN -// Description : Power on ADC and enable its clock. -// 1 - enabled. 0 - disabled. -#define ADC_CS_EN_RESET _u(0x0) -#define ADC_CS_EN_BITS _u(0x00000001) -#define ADC_CS_EN_MSB _u(0) -#define ADC_CS_EN_LSB _u(0) -#define ADC_CS_EN_ACCESS "RW" -// ============================================================================= -// Register : ADC_RESULT -// Description : Result of most recent ADC conversion -#define ADC_RESULT_OFFSET _u(0x00000004) -#define ADC_RESULT_BITS _u(0x00000fff) -#define ADC_RESULT_RESET _u(0x00000000) -#define ADC_RESULT_MSB _u(11) -#define ADC_RESULT_LSB _u(0) -#define ADC_RESULT_ACCESS "RO" -// ============================================================================= -// Register : ADC_FCS -// Description : FIFO control and status -#define ADC_FCS_OFFSET _u(0x00000008) -#define ADC_FCS_BITS _u(0x0f0f0f0f) -#define ADC_FCS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : ADC_FCS_THRESH -// Description : DREQ/IRQ asserted when level >= threshold -#define ADC_FCS_THRESH_RESET _u(0x0) -#define ADC_FCS_THRESH_BITS _u(0x0f000000) -#define ADC_FCS_THRESH_MSB _u(27) -#define ADC_FCS_THRESH_LSB _u(24) -#define ADC_FCS_THRESH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ADC_FCS_LEVEL -// Description : The number of conversion results currently waiting in the FIFO -#define ADC_FCS_LEVEL_RESET _u(0x0) -#define ADC_FCS_LEVEL_BITS _u(0x000f0000) -#define ADC_FCS_LEVEL_MSB _u(19) -#define ADC_FCS_LEVEL_LSB _u(16) -#define ADC_FCS_LEVEL_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : ADC_FCS_OVER -// Description : 1 if the FIFO has been overflowed. Write 1 to clear. -#define ADC_FCS_OVER_RESET _u(0x0) -#define ADC_FCS_OVER_BITS _u(0x00000800) -#define ADC_FCS_OVER_MSB _u(11) -#define ADC_FCS_OVER_LSB _u(11) -#define ADC_FCS_OVER_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : ADC_FCS_UNDER -// Description : 1 if the FIFO has been underflowed. Write 1 to clear. -#define ADC_FCS_UNDER_RESET _u(0x0) -#define ADC_FCS_UNDER_BITS _u(0x00000400) -#define ADC_FCS_UNDER_MSB _u(10) -#define ADC_FCS_UNDER_LSB _u(10) -#define ADC_FCS_UNDER_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : ADC_FCS_FULL -#define ADC_FCS_FULL_RESET _u(0x0) -#define ADC_FCS_FULL_BITS _u(0x00000200) -#define ADC_FCS_FULL_MSB _u(9) -#define ADC_FCS_FULL_LSB _u(9) -#define ADC_FCS_FULL_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : ADC_FCS_EMPTY -#define ADC_FCS_EMPTY_RESET _u(0x0) -#define ADC_FCS_EMPTY_BITS _u(0x00000100) -#define ADC_FCS_EMPTY_MSB _u(8) -#define ADC_FCS_EMPTY_LSB _u(8) -#define ADC_FCS_EMPTY_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : ADC_FCS_DREQ_EN -// Description : If 1: assert DMA requests when FIFO contains data -#define ADC_FCS_DREQ_EN_RESET _u(0x0) -#define ADC_FCS_DREQ_EN_BITS _u(0x00000008) -#define ADC_FCS_DREQ_EN_MSB _u(3) -#define ADC_FCS_DREQ_EN_LSB _u(3) -#define ADC_FCS_DREQ_EN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ADC_FCS_ERR -// Description : If 1: conversion error bit appears in the FIFO alongside the -// result -#define ADC_FCS_ERR_RESET _u(0x0) -#define ADC_FCS_ERR_BITS _u(0x00000004) -#define ADC_FCS_ERR_MSB _u(2) -#define ADC_FCS_ERR_LSB _u(2) -#define ADC_FCS_ERR_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ADC_FCS_SHIFT -// Description : If 1: FIFO results are right-shifted to be one byte in size. -// Enables DMA to byte buffers. -#define ADC_FCS_SHIFT_RESET _u(0x0) -#define ADC_FCS_SHIFT_BITS _u(0x00000002) -#define ADC_FCS_SHIFT_MSB _u(1) -#define ADC_FCS_SHIFT_LSB _u(1) -#define ADC_FCS_SHIFT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ADC_FCS_EN -// Description : If 1: write result to the FIFO after each conversion. -#define ADC_FCS_EN_RESET _u(0x0) -#define ADC_FCS_EN_BITS _u(0x00000001) -#define ADC_FCS_EN_MSB _u(0) -#define ADC_FCS_EN_LSB _u(0) -#define ADC_FCS_EN_ACCESS "RW" -// ============================================================================= -// Register : ADC_FIFO -// Description : Conversion result FIFO -#define ADC_FIFO_OFFSET _u(0x0000000c) -#define ADC_FIFO_BITS _u(0x00008fff) -#define ADC_FIFO_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : ADC_FIFO_ERR -// Description : 1 if this particular sample experienced a conversion error. -// Remains in the same location if the sample is shifted. -#define ADC_FIFO_ERR_RESET "-" -#define ADC_FIFO_ERR_BITS _u(0x00008000) -#define ADC_FIFO_ERR_MSB _u(15) -#define ADC_FIFO_ERR_LSB _u(15) -#define ADC_FIFO_ERR_ACCESS "RF" -// ----------------------------------------------------------------------------- -// Field : ADC_FIFO_VAL -#define ADC_FIFO_VAL_RESET "-" -#define ADC_FIFO_VAL_BITS _u(0x00000fff) -#define ADC_FIFO_VAL_MSB _u(11) -#define ADC_FIFO_VAL_LSB _u(0) -#define ADC_FIFO_VAL_ACCESS "RF" -// ============================================================================= -// Register : ADC_DIV -// Description : Clock divider. If non-zero, CS_START_MANY will start -// conversions -// at regular intervals rather than back-to-back. -// The divider is reset when either of these fields are written. -// Total period is 1 + INT + FRAC / 256 -#define ADC_DIV_OFFSET _u(0x00000010) -#define ADC_DIV_BITS _u(0x00ffffff) -#define ADC_DIV_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : ADC_DIV_INT -// Description : Integer part of clock divisor. -#define ADC_DIV_INT_RESET _u(0x0000) -#define ADC_DIV_INT_BITS _u(0x00ffff00) -#define ADC_DIV_INT_MSB _u(23) -#define ADC_DIV_INT_LSB _u(8) -#define ADC_DIV_INT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ADC_DIV_FRAC -// Description : Fractional part of clock divisor. First-order delta-sigma. -#define ADC_DIV_FRAC_RESET _u(0x00) -#define ADC_DIV_FRAC_BITS _u(0x000000ff) -#define ADC_DIV_FRAC_MSB _u(7) -#define ADC_DIV_FRAC_LSB _u(0) -#define ADC_DIV_FRAC_ACCESS "RW" -// ============================================================================= -// Register : ADC_INTR -// Description : Raw Interrupts -#define ADC_INTR_OFFSET _u(0x00000014) -#define ADC_INTR_BITS _u(0x00000001) -#define ADC_INTR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : ADC_INTR_FIFO -// Description : Triggered when the sample FIFO reaches a certain level. -// This level can be programmed via the FCS_THRESH field. -#define ADC_INTR_FIFO_RESET _u(0x0) -#define ADC_INTR_FIFO_BITS _u(0x00000001) -#define ADC_INTR_FIFO_MSB _u(0) -#define ADC_INTR_FIFO_LSB _u(0) -#define ADC_INTR_FIFO_ACCESS "RO" -// ============================================================================= -// Register : ADC_INTE -// Description : Interrupt Enable -#define ADC_INTE_OFFSET _u(0x00000018) -#define ADC_INTE_BITS _u(0x00000001) -#define ADC_INTE_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : ADC_INTE_FIFO -// Description : Triggered when the sample FIFO reaches a certain level. -// This level can be programmed via the FCS_THRESH field. -#define ADC_INTE_FIFO_RESET _u(0x0) -#define ADC_INTE_FIFO_BITS _u(0x00000001) -#define ADC_INTE_FIFO_MSB _u(0) -#define ADC_INTE_FIFO_LSB _u(0) -#define ADC_INTE_FIFO_ACCESS "RW" -// ============================================================================= -// Register : ADC_INTF -// Description : Interrupt Force -#define ADC_INTF_OFFSET _u(0x0000001c) -#define ADC_INTF_BITS _u(0x00000001) -#define ADC_INTF_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : ADC_INTF_FIFO -// Description : Triggered when the sample FIFO reaches a certain level. -// This level can be programmed via the FCS_THRESH field. -#define ADC_INTF_FIFO_RESET _u(0x0) -#define ADC_INTF_FIFO_BITS _u(0x00000001) -#define ADC_INTF_FIFO_MSB _u(0) -#define ADC_INTF_FIFO_LSB _u(0) -#define ADC_INTF_FIFO_ACCESS "RW" -// ============================================================================= -// Register : ADC_INTS -// Description : Interrupt status after masking & forcing -#define ADC_INTS_OFFSET _u(0x00000020) -#define ADC_INTS_BITS _u(0x00000001) -#define ADC_INTS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : ADC_INTS_FIFO -// Description : Triggered when the sample FIFO reaches a certain level. -// This level can be programmed via the FCS_THRESH field. -#define ADC_INTS_FIFO_RESET _u(0x0) -#define ADC_INTS_FIFO_BITS _u(0x00000001) -#define ADC_INTS_FIFO_MSB _u(0) -#define ADC_INTS_FIFO_LSB _u(0) -#define ADC_INTS_FIFO_ACCESS "RO" -// ============================================================================= -#endif // _HARDWARE_REGS_ADC_H - diff --git a/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/addressmap.h b/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/addressmap.h deleted file mode 100644 index 0e8df52013..0000000000 --- a/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/addressmap.h +++ /dev/null @@ -1,112 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _ADDRESSMAP_H -#define _ADDRESSMAP_H - -/** - * \file rp2350/addressmap.h - */ - -#include "hardware/platform_defs.h" - -// Register address offsets for atomic RMW aliases -#define REG_ALIAS_RW_BITS (_u(0x0) << _u(12)) -#define REG_ALIAS_XOR_BITS (_u(0x1) << _u(12)) -#define REG_ALIAS_SET_BITS (_u(0x2) << _u(12)) -#define REG_ALIAS_CLR_BITS (_u(0x3) << _u(12)) - -#define ROM_BASE _u(0x00000000) -#define XIP_BASE _u(0x10000000) -#define XIP_SRAM_BASE _u(0x13ffc000) -#define XIP_END _u(0x14000000) -#define XIP_NOCACHE_NOALLOC_BASE _u(0x14000000) -#define XIP_SRAM_END _u(0x14000000) -#define XIP_NOCACHE_NOALLOC_END _u(0x18000000) -#define XIP_MAINTENANCE_BASE _u(0x18000000) -#define XIP_NOCACHE_NOALLOC_NOTRANSLATE_BASE _u(0x1c000000) -#define SRAM0_BASE _u(0x20000000) -#define XIP_NOCACHE_NOALLOC_NOTRANSLATE_END _u(0x20000000) -#define SRAM_BASE _u(0x20000000) -#define SRAM_STRIPED_BASE _u(0x20000000) -#define SRAM4_BASE _u(0x20040000) -#define SRAM8_BASE _u(0x20080000) -#define SRAM_STRIPED_END _u(0x20080000) -#define SRAM_SCRATCH_X_BASE _u(0x20080000) -#define SRAM9_BASE _u(0x20081000) -#define SRAM_SCRATCH_Y_BASE _u(0x20081000) -#define SRAM_END _u(0x20082000) -#define SYSINFO_BASE _u(0x40000000) -#define SYSCFG_BASE _u(0x40008000) -#define CLOCKS_BASE _u(0x40010000) -#define PSM_BASE _u(0x40018000) -#define RESETS_BASE _u(0x40020000) -#define IO_BANK0_BASE _u(0x40028000) -#define IO_QSPI_BASE _u(0x40030000) -#define PADS_BANK0_BASE _u(0x40038000) -#define PADS_QSPI_BASE _u(0x40040000) -#define XOSC_BASE _u(0x40048000) -#define PLL_SYS_BASE _u(0x40050000) -#define PLL_USB_BASE _u(0x40058000) -#define ACCESSCTRL_BASE _u(0x40060000) -#define BUSCTRL_BASE _u(0x40068000) -#define UART0_BASE _u(0x40070000) -#define UART1_BASE _u(0x40078000) -#define SPI0_BASE _u(0x40080000) -#define SPI1_BASE _u(0x40088000) -#define I2C0_BASE _u(0x40090000) -#define I2C1_BASE _u(0x40098000) -#define ADC_BASE _u(0x400a0000) -#define PWM_BASE _u(0x400a8000) -#define TIMER0_BASE _u(0x400b0000) -#define TIMER1_BASE _u(0x400b8000) -#define HSTX_CTRL_BASE _u(0x400c0000) -#define XIP_CTRL_BASE _u(0x400c8000) -#define XIP_QMI_BASE _u(0x400d0000) -#define WATCHDOG_BASE _u(0x400d8000) -#define BOOTRAM_BASE _u(0x400e0000) -#define BOOTRAM_END _u(0x400e0400) -#define ROSC_BASE _u(0x400e8000) -#define TRNG_BASE _u(0x400f0000) -#define SHA256_BASE _u(0x400f8000) -#define POWMAN_BASE _u(0x40100000) -#define TICKS_BASE _u(0x40108000) -#define OTP_BASE _u(0x40120000) -#define OTP_DATA_BASE _u(0x40130000) -#define OTP_DATA_RAW_BASE _u(0x40134000) -#define OTP_DATA_GUARDED_BASE _u(0x40138000) -#define OTP_DATA_RAW_GUARDED_BASE _u(0x4013c000) -#define CORESIGHT_PERIPH_BASE _u(0x40140000) -#define CORESIGHT_ROMTABLE_BASE _u(0x40140000) -#define CORESIGHT_AHB_AP_CORE0_BASE _u(0x40142000) -#define CORESIGHT_AHB_AP_CORE1_BASE _u(0x40144000) -#define CORESIGHT_TIMESTAMP_GEN_BASE _u(0x40146000) -#define CORESIGHT_ATB_FUNNEL_BASE _u(0x40147000) -#define CORESIGHT_TPIU_BASE _u(0x40148000) -#define CORESIGHT_CTI_BASE _u(0x40149000) -#define CORESIGHT_APB_AP_RISCV_BASE _u(0x4014a000) -#define DFT_BASE _u(0x40150000) -#define GLITCH_DETECTOR_BASE _u(0x40158000) -#define TBMAN_BASE _u(0x40160000) -#define DMA_BASE _u(0x50000000) -#define USBCTRL_BASE _u(0x50100000) -#define USBCTRL_DPRAM_BASE _u(0x50100000) -#define USBCTRL_REGS_BASE _u(0x50110000) -#define PIO0_BASE _u(0x50200000) -#define PIO1_BASE _u(0x50300000) -#define PIO2_BASE _u(0x50400000) -#define XIP_AUX_BASE _u(0x50500000) -#define HSTX_FIFO_BASE _u(0x50600000) -#define CORESIGHT_TRACE_BASE _u(0x50700000) -#define SIO_BASE _u(0xd0000000) -#define SIO_NONSEC_BASE _u(0xd0020000) -#define PPB_BASE _u(0xe0000000) -#define PPB_NONSEC_BASE _u(0xe0020000) -#define EPPB_BASE _u(0xe0080000) - -#endif // _ADDRESSMAP_H - diff --git a/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/bootram.h b/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/bootram.h deleted file mode 100644 index 0d8695cb00..0000000000 --- a/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/bootram.h +++ /dev/null @@ -1,130 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -// ============================================================================= -// Register block : BOOTRAM -// Version : 1 -// Bus type : apb -// Description : Additional registers mapped adjacent to the bootram, for use -// by the bootrom. -// ============================================================================= -#ifndef _HARDWARE_REGS_BOOTRAM_H -#define _HARDWARE_REGS_BOOTRAM_H -// ============================================================================= -// Register : BOOTRAM_WRITE_ONCE0 -// Description : This registers always ORs writes into its current contents. -// Once a bit is set, it can only be cleared by a reset. -#define BOOTRAM_WRITE_ONCE0_OFFSET _u(0x00000800) -#define BOOTRAM_WRITE_ONCE0_BITS _u(0xffffffff) -#define BOOTRAM_WRITE_ONCE0_RESET _u(0x00000000) -#define BOOTRAM_WRITE_ONCE0_MSB _u(31) -#define BOOTRAM_WRITE_ONCE0_LSB _u(0) -#define BOOTRAM_WRITE_ONCE0_ACCESS "RW" -// ============================================================================= -// Register : BOOTRAM_WRITE_ONCE1 -// Description : This registers always ORs writes into its current contents. -// Once a bit is set, it can only be cleared by a reset. -#define BOOTRAM_WRITE_ONCE1_OFFSET _u(0x00000804) -#define BOOTRAM_WRITE_ONCE1_BITS _u(0xffffffff) -#define BOOTRAM_WRITE_ONCE1_RESET _u(0x00000000) -#define BOOTRAM_WRITE_ONCE1_MSB _u(31) -#define BOOTRAM_WRITE_ONCE1_LSB _u(0) -#define BOOTRAM_WRITE_ONCE1_ACCESS "RW" -// ============================================================================= -// Register : BOOTRAM_BOOTLOCK_STAT -// Description : Bootlock status register. 1=unclaimed, 0=claimed. These locks -// function identically to the SIO spinlocks, but are reserved for -// bootrom use. -#define BOOTRAM_BOOTLOCK_STAT_OFFSET _u(0x00000808) -#define BOOTRAM_BOOTLOCK_STAT_BITS _u(0x000000ff) -#define BOOTRAM_BOOTLOCK_STAT_RESET _u(0x000000ff) -#define BOOTRAM_BOOTLOCK_STAT_MSB _u(7) -#define BOOTRAM_BOOTLOCK_STAT_LSB _u(0) -#define BOOTRAM_BOOTLOCK_STAT_ACCESS "RW" -// ============================================================================= -// Register : BOOTRAM_BOOTLOCK0 -// Description : Read to claim and check. Write to unclaim. The value returned -// on successful claim is 1 << n, and on failed claim is zero. -#define BOOTRAM_BOOTLOCK0_OFFSET _u(0x0000080c) -#define BOOTRAM_BOOTLOCK0_BITS _u(0xffffffff) -#define BOOTRAM_BOOTLOCK0_RESET _u(0x00000000) -#define BOOTRAM_BOOTLOCK0_MSB _u(31) -#define BOOTRAM_BOOTLOCK0_LSB _u(0) -#define BOOTRAM_BOOTLOCK0_ACCESS "RW" -// ============================================================================= -// Register : BOOTRAM_BOOTLOCK1 -// Description : Read to claim and check. Write to unclaim. The value returned -// on successful claim is 1 << n, and on failed claim is zero. -#define BOOTRAM_BOOTLOCK1_OFFSET _u(0x00000810) -#define BOOTRAM_BOOTLOCK1_BITS _u(0xffffffff) -#define BOOTRAM_BOOTLOCK1_RESET _u(0x00000000) -#define BOOTRAM_BOOTLOCK1_MSB _u(31) -#define BOOTRAM_BOOTLOCK1_LSB _u(0) -#define BOOTRAM_BOOTLOCK1_ACCESS "RW" -// ============================================================================= -// Register : BOOTRAM_BOOTLOCK2 -// Description : Read to claim and check. Write to unclaim. The value returned -// on successful claim is 1 << n, and on failed claim is zero. -#define BOOTRAM_BOOTLOCK2_OFFSET _u(0x00000814) -#define BOOTRAM_BOOTLOCK2_BITS _u(0xffffffff) -#define BOOTRAM_BOOTLOCK2_RESET _u(0x00000000) -#define BOOTRAM_BOOTLOCK2_MSB _u(31) -#define BOOTRAM_BOOTLOCK2_LSB _u(0) -#define BOOTRAM_BOOTLOCK2_ACCESS "RW" -// ============================================================================= -// Register : BOOTRAM_BOOTLOCK3 -// Description : Read to claim and check. Write to unclaim. The value returned -// on successful claim is 1 << n, and on failed claim is zero. -#define BOOTRAM_BOOTLOCK3_OFFSET _u(0x00000818) -#define BOOTRAM_BOOTLOCK3_BITS _u(0xffffffff) -#define BOOTRAM_BOOTLOCK3_RESET _u(0x00000000) -#define BOOTRAM_BOOTLOCK3_MSB _u(31) -#define BOOTRAM_BOOTLOCK3_LSB _u(0) -#define BOOTRAM_BOOTLOCK3_ACCESS "RW" -// ============================================================================= -// Register : BOOTRAM_BOOTLOCK4 -// Description : Read to claim and check. Write to unclaim. The value returned -// on successful claim is 1 << n, and on failed claim is zero. -#define BOOTRAM_BOOTLOCK4_OFFSET _u(0x0000081c) -#define BOOTRAM_BOOTLOCK4_BITS _u(0xffffffff) -#define BOOTRAM_BOOTLOCK4_RESET _u(0x00000000) -#define BOOTRAM_BOOTLOCK4_MSB _u(31) -#define BOOTRAM_BOOTLOCK4_LSB _u(0) -#define BOOTRAM_BOOTLOCK4_ACCESS "RW" -// ============================================================================= -// Register : BOOTRAM_BOOTLOCK5 -// Description : Read to claim and check. Write to unclaim. The value returned -// on successful claim is 1 << n, and on failed claim is zero. -#define BOOTRAM_BOOTLOCK5_OFFSET _u(0x00000820) -#define BOOTRAM_BOOTLOCK5_BITS _u(0xffffffff) -#define BOOTRAM_BOOTLOCK5_RESET _u(0x00000000) -#define BOOTRAM_BOOTLOCK5_MSB _u(31) -#define BOOTRAM_BOOTLOCK5_LSB _u(0) -#define BOOTRAM_BOOTLOCK5_ACCESS "RW" -// ============================================================================= -// Register : BOOTRAM_BOOTLOCK6 -// Description : Read to claim and check. Write to unclaim. The value returned -// on successful claim is 1 << n, and on failed claim is zero. -#define BOOTRAM_BOOTLOCK6_OFFSET _u(0x00000824) -#define BOOTRAM_BOOTLOCK6_BITS _u(0xffffffff) -#define BOOTRAM_BOOTLOCK6_RESET _u(0x00000000) -#define BOOTRAM_BOOTLOCK6_MSB _u(31) -#define BOOTRAM_BOOTLOCK6_LSB _u(0) -#define BOOTRAM_BOOTLOCK6_ACCESS "RW" -// ============================================================================= -// Register : BOOTRAM_BOOTLOCK7 -// Description : Read to claim and check. Write to unclaim. The value returned -// on successful claim is 1 << n, and on failed claim is zero. -#define BOOTRAM_BOOTLOCK7_OFFSET _u(0x00000828) -#define BOOTRAM_BOOTLOCK7_BITS _u(0xffffffff) -#define BOOTRAM_BOOTLOCK7_RESET _u(0x00000000) -#define BOOTRAM_BOOTLOCK7_MSB _u(31) -#define BOOTRAM_BOOTLOCK7_LSB _u(0) -#define BOOTRAM_BOOTLOCK7_ACCESS "RW" -// ============================================================================= -#endif // _HARDWARE_REGS_BOOTRAM_H - diff --git a/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/busctrl.h b/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/busctrl.h deleted file mode 100644 index c3bf3e139e..0000000000 --- a/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/busctrl.h +++ /dev/null @@ -1,753 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -// ============================================================================= -// Register block : BUSCTRL -// Version : 1 -// Bus type : apb -// Description : Register block for busfabric control signals and performance -// counters -// ============================================================================= -#ifndef _HARDWARE_REGS_BUSCTRL_H -#define _HARDWARE_REGS_BUSCTRL_H -// ============================================================================= -// Register : BUSCTRL_BUS_PRIORITY -// Description : Set the priority of each master for bus arbitration. -#define BUSCTRL_BUS_PRIORITY_OFFSET _u(0x00000000) -#define BUSCTRL_BUS_PRIORITY_BITS _u(0x00001111) -#define BUSCTRL_BUS_PRIORITY_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : BUSCTRL_BUS_PRIORITY_DMA_W -// Description : 0 - low priority, 1 - high priority -#define BUSCTRL_BUS_PRIORITY_DMA_W_RESET _u(0x0) -#define BUSCTRL_BUS_PRIORITY_DMA_W_BITS _u(0x00001000) -#define BUSCTRL_BUS_PRIORITY_DMA_W_MSB _u(12) -#define BUSCTRL_BUS_PRIORITY_DMA_W_LSB _u(12) -#define BUSCTRL_BUS_PRIORITY_DMA_W_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : BUSCTRL_BUS_PRIORITY_DMA_R -// Description : 0 - low priority, 1 - high priority -#define BUSCTRL_BUS_PRIORITY_DMA_R_RESET _u(0x0) -#define BUSCTRL_BUS_PRIORITY_DMA_R_BITS _u(0x00000100) -#define BUSCTRL_BUS_PRIORITY_DMA_R_MSB _u(8) -#define BUSCTRL_BUS_PRIORITY_DMA_R_LSB _u(8) -#define BUSCTRL_BUS_PRIORITY_DMA_R_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : BUSCTRL_BUS_PRIORITY_PROC1 -// Description : 0 - low priority, 1 - high priority -#define BUSCTRL_BUS_PRIORITY_PROC1_RESET _u(0x0) -#define BUSCTRL_BUS_PRIORITY_PROC1_BITS _u(0x00000010) -#define BUSCTRL_BUS_PRIORITY_PROC1_MSB _u(4) -#define BUSCTRL_BUS_PRIORITY_PROC1_LSB _u(4) -#define BUSCTRL_BUS_PRIORITY_PROC1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : BUSCTRL_BUS_PRIORITY_PROC0 -// Description : 0 - low priority, 1 - high priority -#define BUSCTRL_BUS_PRIORITY_PROC0_RESET _u(0x0) -#define BUSCTRL_BUS_PRIORITY_PROC0_BITS _u(0x00000001) -#define BUSCTRL_BUS_PRIORITY_PROC0_MSB _u(0) -#define BUSCTRL_BUS_PRIORITY_PROC0_LSB _u(0) -#define BUSCTRL_BUS_PRIORITY_PROC0_ACCESS "RW" -// ============================================================================= -// Register : BUSCTRL_BUS_PRIORITY_ACK -// Description : Bus priority acknowledge -// Goes to 1 once all arbiters have registered the new global -// priority levels. -// Arbiters update their local priority when servicing a new -// nonsequential access. -// In normal circumstances this will happen almost immediately. -#define BUSCTRL_BUS_PRIORITY_ACK_OFFSET _u(0x00000004) -#define BUSCTRL_BUS_PRIORITY_ACK_BITS _u(0x00000001) -#define BUSCTRL_BUS_PRIORITY_ACK_RESET _u(0x00000000) -#define BUSCTRL_BUS_PRIORITY_ACK_MSB _u(0) -#define BUSCTRL_BUS_PRIORITY_ACK_LSB _u(0) -#define BUSCTRL_BUS_PRIORITY_ACK_ACCESS "RO" -// ============================================================================= -// Register : BUSCTRL_PERFCTR_EN -// Description : Enable the performance counters. If 0, the performance counters -// do not increment. This can be used to precisely start/stop -// event sampling around the profiled section of code. -// -// The performance counters are initially disabled, to save -// energy. -#define BUSCTRL_PERFCTR_EN_OFFSET _u(0x00000008) -#define BUSCTRL_PERFCTR_EN_BITS _u(0x00000001) -#define BUSCTRL_PERFCTR_EN_RESET _u(0x00000000) -#define BUSCTRL_PERFCTR_EN_MSB _u(0) -#define BUSCTRL_PERFCTR_EN_LSB _u(0) -#define BUSCTRL_PERFCTR_EN_ACCESS "RW" -// ============================================================================= -// Register : BUSCTRL_PERFCTR0 -// Description : Bus fabric performance counter 0 -// Busfabric saturating performance counter 0 -// Count some event signal from the busfabric arbiters, if -// PERFCTR_EN is set. -// Write any value to clear. Select an event to count using -// PERFSEL0 -#define BUSCTRL_PERFCTR0_OFFSET _u(0x0000000c) -#define BUSCTRL_PERFCTR0_BITS _u(0x00ffffff) -#define BUSCTRL_PERFCTR0_RESET _u(0x00000000) -#define BUSCTRL_PERFCTR0_MSB _u(23) -#define BUSCTRL_PERFCTR0_LSB _u(0) -#define BUSCTRL_PERFCTR0_ACCESS "WC" -// ============================================================================= -// Register : BUSCTRL_PERFSEL0 -// Description : Bus fabric performance event select for PERFCTR0 -// Select an event for PERFCTR0. For each downstream port of the -// main crossbar, four events are available: ACCESS, an access -// took place; ACCESS_CONTESTED, an access took place that -// previously stalled due to contention from other masters; -// STALL_DOWNSTREAM, count cycles where any master stalled due to -// a stall on the downstream bus; STALL_UPSTREAM, count cycles -// where any master stalled for any reason, including contention -// from other masters. -// 0x00 -> siob_proc1_stall_upstream -// 0x01 -> siob_proc1_stall_downstream -// 0x02 -> siob_proc1_access_contested -// 0x03 -> siob_proc1_access -// 0x04 -> siob_proc0_stall_upstream -// 0x05 -> siob_proc0_stall_downstream -// 0x06 -> siob_proc0_access_contested -// 0x07 -> siob_proc0_access -// 0x08 -> apb_stall_upstream -// 0x09 -> apb_stall_downstream -// 0x0a -> apb_access_contested -// 0x0b -> apb_access -// 0x0c -> fastperi_stall_upstream -// 0x0d -> fastperi_stall_downstream -// 0x0e -> fastperi_access_contested -// 0x0f -> fastperi_access -// 0x10 -> sram9_stall_upstream -// 0x11 -> sram9_stall_downstream -// 0x12 -> sram9_access_contested -// 0x13 -> sram9_access -// 0x14 -> sram8_stall_upstream -// 0x15 -> sram8_stall_downstream -// 0x16 -> sram8_access_contested -// 0x17 -> sram8_access -// 0x18 -> sram7_stall_upstream -// 0x19 -> sram7_stall_downstream -// 0x1a -> sram7_access_contested -// 0x1b -> sram7_access -// 0x1c -> sram6_stall_upstream -// 0x1d -> sram6_stall_downstream -// 0x1e -> sram6_access_contested -// 0x1f -> sram6_access -// 0x20 -> sram5_stall_upstream -// 0x21 -> sram5_stall_downstream -// 0x22 -> sram5_access_contested -// 0x23 -> sram5_access -// 0x24 -> sram4_stall_upstream -// 0x25 -> sram4_stall_downstream -// 0x26 -> sram4_access_contested -// 0x27 -> sram4_access -// 0x28 -> sram3_stall_upstream -// 0x29 -> sram3_stall_downstream -// 0x2a -> sram3_access_contested -// 0x2b -> sram3_access -// 0x2c -> sram2_stall_upstream -// 0x2d -> sram2_stall_downstream -// 0x2e -> sram2_access_contested -// 0x2f -> sram2_access -// 0x30 -> sram1_stall_upstream -// 0x31 -> sram1_stall_downstream -// 0x32 -> sram1_access_contested -// 0x33 -> sram1_access -// 0x34 -> sram0_stall_upstream -// 0x35 -> sram0_stall_downstream -// 0x36 -> sram0_access_contested -// 0x37 -> sram0_access -// 0x38 -> xip_main1_stall_upstream -// 0x39 -> xip_main1_stall_downstream -// 0x3a -> xip_main1_access_contested -// 0x3b -> xip_main1_access -// 0x3c -> xip_main0_stall_upstream -// 0x3d -> xip_main0_stall_downstream -// 0x3e -> xip_main0_access_contested -// 0x3f -> xip_main0_access -// 0x40 -> rom_stall_upstream -// 0x41 -> rom_stall_downstream -// 0x42 -> rom_access_contested -// 0x43 -> rom_access -#define BUSCTRL_PERFSEL0_OFFSET _u(0x00000010) -#define BUSCTRL_PERFSEL0_BITS _u(0x0000007f) -#define BUSCTRL_PERFSEL0_RESET _u(0x0000001f) -#define BUSCTRL_PERFSEL0_MSB _u(6) -#define BUSCTRL_PERFSEL0_LSB _u(0) -#define BUSCTRL_PERFSEL0_ACCESS "RW" -#define BUSCTRL_PERFSEL0_VALUE_SIOB_PROC1_STALL_UPSTREAM _u(0x00) -#define BUSCTRL_PERFSEL0_VALUE_SIOB_PROC1_STALL_DOWNSTREAM _u(0x01) -#define BUSCTRL_PERFSEL0_VALUE_SIOB_PROC1_ACCESS_CONTESTED _u(0x02) -#define BUSCTRL_PERFSEL0_VALUE_SIOB_PROC1_ACCESS _u(0x03) -#define BUSCTRL_PERFSEL0_VALUE_SIOB_PROC0_STALL_UPSTREAM _u(0x04) -#define BUSCTRL_PERFSEL0_VALUE_SIOB_PROC0_STALL_DOWNSTREAM _u(0x05) -#define BUSCTRL_PERFSEL0_VALUE_SIOB_PROC0_ACCESS_CONTESTED _u(0x06) -#define BUSCTRL_PERFSEL0_VALUE_SIOB_PROC0_ACCESS _u(0x07) -#define BUSCTRL_PERFSEL0_VALUE_APB_STALL_UPSTREAM _u(0x08) -#define BUSCTRL_PERFSEL0_VALUE_APB_STALL_DOWNSTREAM _u(0x09) -#define BUSCTRL_PERFSEL0_VALUE_APB_ACCESS_CONTESTED _u(0x0a) -#define BUSCTRL_PERFSEL0_VALUE_APB_ACCESS _u(0x0b) -#define BUSCTRL_PERFSEL0_VALUE_FASTPERI_STALL_UPSTREAM _u(0x0c) -#define BUSCTRL_PERFSEL0_VALUE_FASTPERI_STALL_DOWNSTREAM _u(0x0d) -#define BUSCTRL_PERFSEL0_VALUE_FASTPERI_ACCESS_CONTESTED _u(0x0e) -#define BUSCTRL_PERFSEL0_VALUE_FASTPERI_ACCESS _u(0x0f) -#define BUSCTRL_PERFSEL0_VALUE_SRAM9_STALL_UPSTREAM _u(0x10) -#define BUSCTRL_PERFSEL0_VALUE_SRAM9_STALL_DOWNSTREAM _u(0x11) -#define BUSCTRL_PERFSEL0_VALUE_SRAM9_ACCESS_CONTESTED _u(0x12) -#define BUSCTRL_PERFSEL0_VALUE_SRAM9_ACCESS _u(0x13) -#define BUSCTRL_PERFSEL0_VALUE_SRAM8_STALL_UPSTREAM _u(0x14) -#define BUSCTRL_PERFSEL0_VALUE_SRAM8_STALL_DOWNSTREAM _u(0x15) -#define BUSCTRL_PERFSEL0_VALUE_SRAM8_ACCESS_CONTESTED _u(0x16) -#define BUSCTRL_PERFSEL0_VALUE_SRAM8_ACCESS _u(0x17) -#define BUSCTRL_PERFSEL0_VALUE_SRAM7_STALL_UPSTREAM _u(0x18) -#define BUSCTRL_PERFSEL0_VALUE_SRAM7_STALL_DOWNSTREAM _u(0x19) -#define BUSCTRL_PERFSEL0_VALUE_SRAM7_ACCESS_CONTESTED _u(0x1a) -#define BUSCTRL_PERFSEL0_VALUE_SRAM7_ACCESS _u(0x1b) -#define BUSCTRL_PERFSEL0_VALUE_SRAM6_STALL_UPSTREAM _u(0x1c) -#define BUSCTRL_PERFSEL0_VALUE_SRAM6_STALL_DOWNSTREAM _u(0x1d) -#define BUSCTRL_PERFSEL0_VALUE_SRAM6_ACCESS_CONTESTED _u(0x1e) -#define BUSCTRL_PERFSEL0_VALUE_SRAM6_ACCESS _u(0x1f) -#define BUSCTRL_PERFSEL0_VALUE_SRAM5_STALL_UPSTREAM _u(0x20) -#define BUSCTRL_PERFSEL0_VALUE_SRAM5_STALL_DOWNSTREAM _u(0x21) -#define BUSCTRL_PERFSEL0_VALUE_SRAM5_ACCESS_CONTESTED _u(0x22) -#define BUSCTRL_PERFSEL0_VALUE_SRAM5_ACCESS _u(0x23) -#define BUSCTRL_PERFSEL0_VALUE_SRAM4_STALL_UPSTREAM _u(0x24) -#define BUSCTRL_PERFSEL0_VALUE_SRAM4_STALL_DOWNSTREAM _u(0x25) -#define BUSCTRL_PERFSEL0_VALUE_SRAM4_ACCESS_CONTESTED _u(0x26) -#define BUSCTRL_PERFSEL0_VALUE_SRAM4_ACCESS _u(0x27) -#define BUSCTRL_PERFSEL0_VALUE_SRAM3_STALL_UPSTREAM _u(0x28) -#define BUSCTRL_PERFSEL0_VALUE_SRAM3_STALL_DOWNSTREAM _u(0x29) -#define BUSCTRL_PERFSEL0_VALUE_SRAM3_ACCESS_CONTESTED _u(0x2a) -#define BUSCTRL_PERFSEL0_VALUE_SRAM3_ACCESS _u(0x2b) -#define BUSCTRL_PERFSEL0_VALUE_SRAM2_STALL_UPSTREAM _u(0x2c) -#define BUSCTRL_PERFSEL0_VALUE_SRAM2_STALL_DOWNSTREAM _u(0x2d) -#define BUSCTRL_PERFSEL0_VALUE_SRAM2_ACCESS_CONTESTED _u(0x2e) -#define BUSCTRL_PERFSEL0_VALUE_SRAM2_ACCESS _u(0x2f) -#define BUSCTRL_PERFSEL0_VALUE_SRAM1_STALL_UPSTREAM _u(0x30) -#define BUSCTRL_PERFSEL0_VALUE_SRAM1_STALL_DOWNSTREAM _u(0x31) -#define BUSCTRL_PERFSEL0_VALUE_SRAM1_ACCESS_CONTESTED _u(0x32) -#define BUSCTRL_PERFSEL0_VALUE_SRAM1_ACCESS _u(0x33) -#define BUSCTRL_PERFSEL0_VALUE_SRAM0_STALL_UPSTREAM _u(0x34) -#define BUSCTRL_PERFSEL0_VALUE_SRAM0_STALL_DOWNSTREAM _u(0x35) -#define BUSCTRL_PERFSEL0_VALUE_SRAM0_ACCESS_CONTESTED _u(0x36) -#define BUSCTRL_PERFSEL0_VALUE_SRAM0_ACCESS _u(0x37) -#define BUSCTRL_PERFSEL0_VALUE_XIP_MAIN1_STALL_UPSTREAM _u(0x38) -#define BUSCTRL_PERFSEL0_VALUE_XIP_MAIN1_STALL_DOWNSTREAM _u(0x39) -#define BUSCTRL_PERFSEL0_VALUE_XIP_MAIN1_ACCESS_CONTESTED _u(0x3a) -#define BUSCTRL_PERFSEL0_VALUE_XIP_MAIN1_ACCESS _u(0x3b) -#define BUSCTRL_PERFSEL0_VALUE_XIP_MAIN0_STALL_UPSTREAM _u(0x3c) -#define BUSCTRL_PERFSEL0_VALUE_XIP_MAIN0_STALL_DOWNSTREAM _u(0x3d) -#define BUSCTRL_PERFSEL0_VALUE_XIP_MAIN0_ACCESS_CONTESTED _u(0x3e) -#define BUSCTRL_PERFSEL0_VALUE_XIP_MAIN0_ACCESS _u(0x3f) -#define BUSCTRL_PERFSEL0_VALUE_ROM_STALL_UPSTREAM _u(0x40) -#define BUSCTRL_PERFSEL0_VALUE_ROM_STALL_DOWNSTREAM _u(0x41) -#define BUSCTRL_PERFSEL0_VALUE_ROM_ACCESS_CONTESTED _u(0x42) -#define BUSCTRL_PERFSEL0_VALUE_ROM_ACCESS _u(0x43) -// ============================================================================= -// Register : BUSCTRL_PERFCTR1 -// Description : Bus fabric performance counter 1 -// Busfabric saturating performance counter 1 -// Count some event signal from the busfabric arbiters, if -// PERFCTR_EN is set. -// Write any value to clear. Select an event to count using -// PERFSEL1 -#define BUSCTRL_PERFCTR1_OFFSET _u(0x00000014) -#define BUSCTRL_PERFCTR1_BITS _u(0x00ffffff) -#define BUSCTRL_PERFCTR1_RESET _u(0x00000000) -#define BUSCTRL_PERFCTR1_MSB _u(23) -#define BUSCTRL_PERFCTR1_LSB _u(0) -#define BUSCTRL_PERFCTR1_ACCESS "WC" -// ============================================================================= -// Register : BUSCTRL_PERFSEL1 -// Description : Bus fabric performance event select for PERFCTR1 -// Select an event for PERFCTR1. For each downstream port of the -// main crossbar, four events are available: ACCESS, an access -// took place; ACCESS_CONTESTED, an access took place that -// previously stalled due to contention from other masters; -// STALL_DOWNSTREAM, count cycles where any master stalled due to -// a stall on the downstream bus; STALL_UPSTREAM, count cycles -// where any master stalled for any reason, including contention -// from other masters. -// 0x00 -> siob_proc1_stall_upstream -// 0x01 -> siob_proc1_stall_downstream -// 0x02 -> siob_proc1_access_contested -// 0x03 -> siob_proc1_access -// 0x04 -> siob_proc0_stall_upstream -// 0x05 -> siob_proc0_stall_downstream -// 0x06 -> siob_proc0_access_contested -// 0x07 -> siob_proc0_access -// 0x08 -> apb_stall_upstream -// 0x09 -> apb_stall_downstream -// 0x0a -> apb_access_contested -// 0x0b -> apb_access -// 0x0c -> fastperi_stall_upstream -// 0x0d -> fastperi_stall_downstream -// 0x0e -> fastperi_access_contested -// 0x0f -> fastperi_access -// 0x10 -> sram9_stall_upstream -// 0x11 -> sram9_stall_downstream -// 0x12 -> sram9_access_contested -// 0x13 -> sram9_access -// 0x14 -> sram8_stall_upstream -// 0x15 -> sram8_stall_downstream -// 0x16 -> sram8_access_contested -// 0x17 -> sram8_access -// 0x18 -> sram7_stall_upstream -// 0x19 -> sram7_stall_downstream -// 0x1a -> sram7_access_contested -// 0x1b -> sram7_access -// 0x1c -> sram6_stall_upstream -// 0x1d -> sram6_stall_downstream -// 0x1e -> sram6_access_contested -// 0x1f -> sram6_access -// 0x20 -> sram5_stall_upstream -// 0x21 -> sram5_stall_downstream -// 0x22 -> sram5_access_contested -// 0x23 -> sram5_access -// 0x24 -> sram4_stall_upstream -// 0x25 -> sram4_stall_downstream -// 0x26 -> sram4_access_contested -// 0x27 -> sram4_access -// 0x28 -> sram3_stall_upstream -// 0x29 -> sram3_stall_downstream -// 0x2a -> sram3_access_contested -// 0x2b -> sram3_access -// 0x2c -> sram2_stall_upstream -// 0x2d -> sram2_stall_downstream -// 0x2e -> sram2_access_contested -// 0x2f -> sram2_access -// 0x30 -> sram1_stall_upstream -// 0x31 -> sram1_stall_downstream -// 0x32 -> sram1_access_contested -// 0x33 -> sram1_access -// 0x34 -> sram0_stall_upstream -// 0x35 -> sram0_stall_downstream -// 0x36 -> sram0_access_contested -// 0x37 -> sram0_access -// 0x38 -> xip_main1_stall_upstream -// 0x39 -> xip_main1_stall_downstream -// 0x3a -> xip_main1_access_contested -// 0x3b -> xip_main1_access -// 0x3c -> xip_main0_stall_upstream -// 0x3d -> xip_main0_stall_downstream -// 0x3e -> xip_main0_access_contested -// 0x3f -> xip_main0_access -// 0x40 -> rom_stall_upstream -// 0x41 -> rom_stall_downstream -// 0x42 -> rom_access_contested -// 0x43 -> rom_access -#define BUSCTRL_PERFSEL1_OFFSET _u(0x00000018) -#define BUSCTRL_PERFSEL1_BITS _u(0x0000007f) -#define BUSCTRL_PERFSEL1_RESET _u(0x0000001f) -#define BUSCTRL_PERFSEL1_MSB _u(6) -#define BUSCTRL_PERFSEL1_LSB _u(0) -#define BUSCTRL_PERFSEL1_ACCESS "RW" -#define BUSCTRL_PERFSEL1_VALUE_SIOB_PROC1_STALL_UPSTREAM _u(0x00) -#define BUSCTRL_PERFSEL1_VALUE_SIOB_PROC1_STALL_DOWNSTREAM _u(0x01) -#define BUSCTRL_PERFSEL1_VALUE_SIOB_PROC1_ACCESS_CONTESTED _u(0x02) -#define BUSCTRL_PERFSEL1_VALUE_SIOB_PROC1_ACCESS _u(0x03) -#define BUSCTRL_PERFSEL1_VALUE_SIOB_PROC0_STALL_UPSTREAM _u(0x04) -#define BUSCTRL_PERFSEL1_VALUE_SIOB_PROC0_STALL_DOWNSTREAM _u(0x05) -#define BUSCTRL_PERFSEL1_VALUE_SIOB_PROC0_ACCESS_CONTESTED _u(0x06) -#define BUSCTRL_PERFSEL1_VALUE_SIOB_PROC0_ACCESS _u(0x07) -#define BUSCTRL_PERFSEL1_VALUE_APB_STALL_UPSTREAM _u(0x08) -#define BUSCTRL_PERFSEL1_VALUE_APB_STALL_DOWNSTREAM _u(0x09) -#define BUSCTRL_PERFSEL1_VALUE_APB_ACCESS_CONTESTED _u(0x0a) -#define BUSCTRL_PERFSEL1_VALUE_APB_ACCESS _u(0x0b) -#define BUSCTRL_PERFSEL1_VALUE_FASTPERI_STALL_UPSTREAM _u(0x0c) -#define BUSCTRL_PERFSEL1_VALUE_FASTPERI_STALL_DOWNSTREAM _u(0x0d) -#define BUSCTRL_PERFSEL1_VALUE_FASTPERI_ACCESS_CONTESTED _u(0x0e) -#define BUSCTRL_PERFSEL1_VALUE_FASTPERI_ACCESS _u(0x0f) -#define BUSCTRL_PERFSEL1_VALUE_SRAM9_STALL_UPSTREAM _u(0x10) -#define BUSCTRL_PERFSEL1_VALUE_SRAM9_STALL_DOWNSTREAM _u(0x11) -#define BUSCTRL_PERFSEL1_VALUE_SRAM9_ACCESS_CONTESTED _u(0x12) -#define BUSCTRL_PERFSEL1_VALUE_SRAM9_ACCESS _u(0x13) -#define BUSCTRL_PERFSEL1_VALUE_SRAM8_STALL_UPSTREAM _u(0x14) -#define BUSCTRL_PERFSEL1_VALUE_SRAM8_STALL_DOWNSTREAM _u(0x15) -#define BUSCTRL_PERFSEL1_VALUE_SRAM8_ACCESS_CONTESTED _u(0x16) -#define BUSCTRL_PERFSEL1_VALUE_SRAM8_ACCESS _u(0x17) -#define BUSCTRL_PERFSEL1_VALUE_SRAM7_STALL_UPSTREAM _u(0x18) -#define BUSCTRL_PERFSEL1_VALUE_SRAM7_STALL_DOWNSTREAM _u(0x19) -#define BUSCTRL_PERFSEL1_VALUE_SRAM7_ACCESS_CONTESTED _u(0x1a) -#define BUSCTRL_PERFSEL1_VALUE_SRAM7_ACCESS _u(0x1b) -#define BUSCTRL_PERFSEL1_VALUE_SRAM6_STALL_UPSTREAM _u(0x1c) -#define BUSCTRL_PERFSEL1_VALUE_SRAM6_STALL_DOWNSTREAM _u(0x1d) -#define BUSCTRL_PERFSEL1_VALUE_SRAM6_ACCESS_CONTESTED _u(0x1e) -#define BUSCTRL_PERFSEL1_VALUE_SRAM6_ACCESS _u(0x1f) -#define BUSCTRL_PERFSEL1_VALUE_SRAM5_STALL_UPSTREAM _u(0x20) -#define BUSCTRL_PERFSEL1_VALUE_SRAM5_STALL_DOWNSTREAM _u(0x21) -#define BUSCTRL_PERFSEL1_VALUE_SRAM5_ACCESS_CONTESTED _u(0x22) -#define BUSCTRL_PERFSEL1_VALUE_SRAM5_ACCESS _u(0x23) -#define BUSCTRL_PERFSEL1_VALUE_SRAM4_STALL_UPSTREAM _u(0x24) -#define BUSCTRL_PERFSEL1_VALUE_SRAM4_STALL_DOWNSTREAM _u(0x25) -#define BUSCTRL_PERFSEL1_VALUE_SRAM4_ACCESS_CONTESTED _u(0x26) -#define BUSCTRL_PERFSEL1_VALUE_SRAM4_ACCESS _u(0x27) -#define BUSCTRL_PERFSEL1_VALUE_SRAM3_STALL_UPSTREAM _u(0x28) -#define BUSCTRL_PERFSEL1_VALUE_SRAM3_STALL_DOWNSTREAM _u(0x29) -#define BUSCTRL_PERFSEL1_VALUE_SRAM3_ACCESS_CONTESTED _u(0x2a) -#define BUSCTRL_PERFSEL1_VALUE_SRAM3_ACCESS _u(0x2b) -#define BUSCTRL_PERFSEL1_VALUE_SRAM2_STALL_UPSTREAM _u(0x2c) -#define BUSCTRL_PERFSEL1_VALUE_SRAM2_STALL_DOWNSTREAM _u(0x2d) -#define BUSCTRL_PERFSEL1_VALUE_SRAM2_ACCESS_CONTESTED _u(0x2e) -#define BUSCTRL_PERFSEL1_VALUE_SRAM2_ACCESS _u(0x2f) -#define BUSCTRL_PERFSEL1_VALUE_SRAM1_STALL_UPSTREAM _u(0x30) -#define BUSCTRL_PERFSEL1_VALUE_SRAM1_STALL_DOWNSTREAM _u(0x31) -#define BUSCTRL_PERFSEL1_VALUE_SRAM1_ACCESS_CONTESTED _u(0x32) -#define BUSCTRL_PERFSEL1_VALUE_SRAM1_ACCESS _u(0x33) -#define BUSCTRL_PERFSEL1_VALUE_SRAM0_STALL_UPSTREAM _u(0x34) -#define BUSCTRL_PERFSEL1_VALUE_SRAM0_STALL_DOWNSTREAM _u(0x35) -#define BUSCTRL_PERFSEL1_VALUE_SRAM0_ACCESS_CONTESTED _u(0x36) -#define BUSCTRL_PERFSEL1_VALUE_SRAM0_ACCESS _u(0x37) -#define BUSCTRL_PERFSEL1_VALUE_XIP_MAIN1_STALL_UPSTREAM _u(0x38) -#define BUSCTRL_PERFSEL1_VALUE_XIP_MAIN1_STALL_DOWNSTREAM _u(0x39) -#define BUSCTRL_PERFSEL1_VALUE_XIP_MAIN1_ACCESS_CONTESTED _u(0x3a) -#define BUSCTRL_PERFSEL1_VALUE_XIP_MAIN1_ACCESS _u(0x3b) -#define BUSCTRL_PERFSEL1_VALUE_XIP_MAIN0_STALL_UPSTREAM _u(0x3c) -#define BUSCTRL_PERFSEL1_VALUE_XIP_MAIN0_STALL_DOWNSTREAM _u(0x3d) -#define BUSCTRL_PERFSEL1_VALUE_XIP_MAIN0_ACCESS_CONTESTED _u(0x3e) -#define BUSCTRL_PERFSEL1_VALUE_XIP_MAIN0_ACCESS _u(0x3f) -#define BUSCTRL_PERFSEL1_VALUE_ROM_STALL_UPSTREAM _u(0x40) -#define BUSCTRL_PERFSEL1_VALUE_ROM_STALL_DOWNSTREAM _u(0x41) -#define BUSCTRL_PERFSEL1_VALUE_ROM_ACCESS_CONTESTED _u(0x42) -#define BUSCTRL_PERFSEL1_VALUE_ROM_ACCESS _u(0x43) -// ============================================================================= -// Register : BUSCTRL_PERFCTR2 -// Description : Bus fabric performance counter 2 -// Busfabric saturating performance counter 2 -// Count some event signal from the busfabric arbiters, if -// PERFCTR_EN is set. -// Write any value to clear. Select an event to count using -// PERFSEL2 -#define BUSCTRL_PERFCTR2_OFFSET _u(0x0000001c) -#define BUSCTRL_PERFCTR2_BITS _u(0x00ffffff) -#define BUSCTRL_PERFCTR2_RESET _u(0x00000000) -#define BUSCTRL_PERFCTR2_MSB _u(23) -#define BUSCTRL_PERFCTR2_LSB _u(0) -#define BUSCTRL_PERFCTR2_ACCESS "WC" -// ============================================================================= -// Register : BUSCTRL_PERFSEL2 -// Description : Bus fabric performance event select for PERFCTR2 -// Select an event for PERFCTR2. For each downstream port of the -// main crossbar, four events are available: ACCESS, an access -// took place; ACCESS_CONTESTED, an access took place that -// previously stalled due to contention from other masters; -// STALL_DOWNSTREAM, count cycles where any master stalled due to -// a stall on the downstream bus; STALL_UPSTREAM, count cycles -// where any master stalled for any reason, including contention -// from other masters. -// 0x00 -> siob_proc1_stall_upstream -// 0x01 -> siob_proc1_stall_downstream -// 0x02 -> siob_proc1_access_contested -// 0x03 -> siob_proc1_access -// 0x04 -> siob_proc0_stall_upstream -// 0x05 -> siob_proc0_stall_downstream -// 0x06 -> siob_proc0_access_contested -// 0x07 -> siob_proc0_access -// 0x08 -> apb_stall_upstream -// 0x09 -> apb_stall_downstream -// 0x0a -> apb_access_contested -// 0x0b -> apb_access -// 0x0c -> fastperi_stall_upstream -// 0x0d -> fastperi_stall_downstream -// 0x0e -> fastperi_access_contested -// 0x0f -> fastperi_access -// 0x10 -> sram9_stall_upstream -// 0x11 -> sram9_stall_downstream -// 0x12 -> sram9_access_contested -// 0x13 -> sram9_access -// 0x14 -> sram8_stall_upstream -// 0x15 -> sram8_stall_downstream -// 0x16 -> sram8_access_contested -// 0x17 -> sram8_access -// 0x18 -> sram7_stall_upstream -// 0x19 -> sram7_stall_downstream -// 0x1a -> sram7_access_contested -// 0x1b -> sram7_access -// 0x1c -> sram6_stall_upstream -// 0x1d -> sram6_stall_downstream -// 0x1e -> sram6_access_contested -// 0x1f -> sram6_access -// 0x20 -> sram5_stall_upstream -// 0x21 -> sram5_stall_downstream -// 0x22 -> sram5_access_contested -// 0x23 -> sram5_access -// 0x24 -> sram4_stall_upstream -// 0x25 -> sram4_stall_downstream -// 0x26 -> sram4_access_contested -// 0x27 -> sram4_access -// 0x28 -> sram3_stall_upstream -// 0x29 -> sram3_stall_downstream -// 0x2a -> sram3_access_contested -// 0x2b -> sram3_access -// 0x2c -> sram2_stall_upstream -// 0x2d -> sram2_stall_downstream -// 0x2e -> sram2_access_contested -// 0x2f -> sram2_access -// 0x30 -> sram1_stall_upstream -// 0x31 -> sram1_stall_downstream -// 0x32 -> sram1_access_contested -// 0x33 -> sram1_access -// 0x34 -> sram0_stall_upstream -// 0x35 -> sram0_stall_downstream -// 0x36 -> sram0_access_contested -// 0x37 -> sram0_access -// 0x38 -> xip_main1_stall_upstream -// 0x39 -> xip_main1_stall_downstream -// 0x3a -> xip_main1_access_contested -// 0x3b -> xip_main1_access -// 0x3c -> xip_main0_stall_upstream -// 0x3d -> xip_main0_stall_downstream -// 0x3e -> xip_main0_access_contested -// 0x3f -> xip_main0_access -// 0x40 -> rom_stall_upstream -// 0x41 -> rom_stall_downstream -// 0x42 -> rom_access_contested -// 0x43 -> rom_access -#define BUSCTRL_PERFSEL2_OFFSET _u(0x00000020) -#define BUSCTRL_PERFSEL2_BITS _u(0x0000007f) -#define BUSCTRL_PERFSEL2_RESET _u(0x0000001f) -#define BUSCTRL_PERFSEL2_MSB _u(6) -#define BUSCTRL_PERFSEL2_LSB _u(0) -#define BUSCTRL_PERFSEL2_ACCESS "RW" -#define BUSCTRL_PERFSEL2_VALUE_SIOB_PROC1_STALL_UPSTREAM _u(0x00) -#define BUSCTRL_PERFSEL2_VALUE_SIOB_PROC1_STALL_DOWNSTREAM _u(0x01) -#define BUSCTRL_PERFSEL2_VALUE_SIOB_PROC1_ACCESS_CONTESTED _u(0x02) -#define BUSCTRL_PERFSEL2_VALUE_SIOB_PROC1_ACCESS _u(0x03) -#define BUSCTRL_PERFSEL2_VALUE_SIOB_PROC0_STALL_UPSTREAM _u(0x04) -#define BUSCTRL_PERFSEL2_VALUE_SIOB_PROC0_STALL_DOWNSTREAM _u(0x05) -#define BUSCTRL_PERFSEL2_VALUE_SIOB_PROC0_ACCESS_CONTESTED _u(0x06) -#define BUSCTRL_PERFSEL2_VALUE_SIOB_PROC0_ACCESS _u(0x07) -#define BUSCTRL_PERFSEL2_VALUE_APB_STALL_UPSTREAM _u(0x08) -#define BUSCTRL_PERFSEL2_VALUE_APB_STALL_DOWNSTREAM _u(0x09) -#define BUSCTRL_PERFSEL2_VALUE_APB_ACCESS_CONTESTED _u(0x0a) -#define BUSCTRL_PERFSEL2_VALUE_APB_ACCESS _u(0x0b) -#define BUSCTRL_PERFSEL2_VALUE_FASTPERI_STALL_UPSTREAM _u(0x0c) -#define BUSCTRL_PERFSEL2_VALUE_FASTPERI_STALL_DOWNSTREAM _u(0x0d) -#define BUSCTRL_PERFSEL2_VALUE_FASTPERI_ACCESS_CONTESTED _u(0x0e) -#define BUSCTRL_PERFSEL2_VALUE_FASTPERI_ACCESS _u(0x0f) -#define BUSCTRL_PERFSEL2_VALUE_SRAM9_STALL_UPSTREAM _u(0x10) -#define BUSCTRL_PERFSEL2_VALUE_SRAM9_STALL_DOWNSTREAM _u(0x11) -#define BUSCTRL_PERFSEL2_VALUE_SRAM9_ACCESS_CONTESTED _u(0x12) -#define BUSCTRL_PERFSEL2_VALUE_SRAM9_ACCESS _u(0x13) -#define BUSCTRL_PERFSEL2_VALUE_SRAM8_STALL_UPSTREAM _u(0x14) -#define BUSCTRL_PERFSEL2_VALUE_SRAM8_STALL_DOWNSTREAM _u(0x15) -#define BUSCTRL_PERFSEL2_VALUE_SRAM8_ACCESS_CONTESTED _u(0x16) -#define BUSCTRL_PERFSEL2_VALUE_SRAM8_ACCESS _u(0x17) -#define BUSCTRL_PERFSEL2_VALUE_SRAM7_STALL_UPSTREAM _u(0x18) -#define BUSCTRL_PERFSEL2_VALUE_SRAM7_STALL_DOWNSTREAM _u(0x19) -#define BUSCTRL_PERFSEL2_VALUE_SRAM7_ACCESS_CONTESTED _u(0x1a) -#define BUSCTRL_PERFSEL2_VALUE_SRAM7_ACCESS _u(0x1b) -#define BUSCTRL_PERFSEL2_VALUE_SRAM6_STALL_UPSTREAM _u(0x1c) -#define BUSCTRL_PERFSEL2_VALUE_SRAM6_STALL_DOWNSTREAM _u(0x1d) -#define BUSCTRL_PERFSEL2_VALUE_SRAM6_ACCESS_CONTESTED _u(0x1e) -#define BUSCTRL_PERFSEL2_VALUE_SRAM6_ACCESS _u(0x1f) -#define BUSCTRL_PERFSEL2_VALUE_SRAM5_STALL_UPSTREAM _u(0x20) -#define BUSCTRL_PERFSEL2_VALUE_SRAM5_STALL_DOWNSTREAM _u(0x21) -#define BUSCTRL_PERFSEL2_VALUE_SRAM5_ACCESS_CONTESTED _u(0x22) -#define BUSCTRL_PERFSEL2_VALUE_SRAM5_ACCESS _u(0x23) -#define BUSCTRL_PERFSEL2_VALUE_SRAM4_STALL_UPSTREAM _u(0x24) -#define BUSCTRL_PERFSEL2_VALUE_SRAM4_STALL_DOWNSTREAM _u(0x25) -#define BUSCTRL_PERFSEL2_VALUE_SRAM4_ACCESS_CONTESTED _u(0x26) -#define BUSCTRL_PERFSEL2_VALUE_SRAM4_ACCESS _u(0x27) -#define BUSCTRL_PERFSEL2_VALUE_SRAM3_STALL_UPSTREAM _u(0x28) -#define BUSCTRL_PERFSEL2_VALUE_SRAM3_STALL_DOWNSTREAM _u(0x29) -#define BUSCTRL_PERFSEL2_VALUE_SRAM3_ACCESS_CONTESTED _u(0x2a) -#define BUSCTRL_PERFSEL2_VALUE_SRAM3_ACCESS _u(0x2b) -#define BUSCTRL_PERFSEL2_VALUE_SRAM2_STALL_UPSTREAM _u(0x2c) -#define BUSCTRL_PERFSEL2_VALUE_SRAM2_STALL_DOWNSTREAM _u(0x2d) -#define BUSCTRL_PERFSEL2_VALUE_SRAM2_ACCESS_CONTESTED _u(0x2e) -#define BUSCTRL_PERFSEL2_VALUE_SRAM2_ACCESS _u(0x2f) -#define BUSCTRL_PERFSEL2_VALUE_SRAM1_STALL_UPSTREAM _u(0x30) -#define BUSCTRL_PERFSEL2_VALUE_SRAM1_STALL_DOWNSTREAM _u(0x31) -#define BUSCTRL_PERFSEL2_VALUE_SRAM1_ACCESS_CONTESTED _u(0x32) -#define BUSCTRL_PERFSEL2_VALUE_SRAM1_ACCESS _u(0x33) -#define BUSCTRL_PERFSEL2_VALUE_SRAM0_STALL_UPSTREAM _u(0x34) -#define BUSCTRL_PERFSEL2_VALUE_SRAM0_STALL_DOWNSTREAM _u(0x35) -#define BUSCTRL_PERFSEL2_VALUE_SRAM0_ACCESS_CONTESTED _u(0x36) -#define BUSCTRL_PERFSEL2_VALUE_SRAM0_ACCESS _u(0x37) -#define BUSCTRL_PERFSEL2_VALUE_XIP_MAIN1_STALL_UPSTREAM _u(0x38) -#define BUSCTRL_PERFSEL2_VALUE_XIP_MAIN1_STALL_DOWNSTREAM _u(0x39) -#define BUSCTRL_PERFSEL2_VALUE_XIP_MAIN1_ACCESS_CONTESTED _u(0x3a) -#define BUSCTRL_PERFSEL2_VALUE_XIP_MAIN1_ACCESS _u(0x3b) -#define BUSCTRL_PERFSEL2_VALUE_XIP_MAIN0_STALL_UPSTREAM _u(0x3c) -#define BUSCTRL_PERFSEL2_VALUE_XIP_MAIN0_STALL_DOWNSTREAM _u(0x3d) -#define BUSCTRL_PERFSEL2_VALUE_XIP_MAIN0_ACCESS_CONTESTED _u(0x3e) -#define BUSCTRL_PERFSEL2_VALUE_XIP_MAIN0_ACCESS _u(0x3f) -#define BUSCTRL_PERFSEL2_VALUE_ROM_STALL_UPSTREAM _u(0x40) -#define BUSCTRL_PERFSEL2_VALUE_ROM_STALL_DOWNSTREAM _u(0x41) -#define BUSCTRL_PERFSEL2_VALUE_ROM_ACCESS_CONTESTED _u(0x42) -#define BUSCTRL_PERFSEL2_VALUE_ROM_ACCESS _u(0x43) -// ============================================================================= -// Register : BUSCTRL_PERFCTR3 -// Description : Bus fabric performance counter 3 -// Busfabric saturating performance counter 3 -// Count some event signal from the busfabric arbiters, if -// PERFCTR_EN is set. -// Write any value to clear. Select an event to count using -// PERFSEL3 -#define BUSCTRL_PERFCTR3_OFFSET _u(0x00000024) -#define BUSCTRL_PERFCTR3_BITS _u(0x00ffffff) -#define BUSCTRL_PERFCTR3_RESET _u(0x00000000) -#define BUSCTRL_PERFCTR3_MSB _u(23) -#define BUSCTRL_PERFCTR3_LSB _u(0) -#define BUSCTRL_PERFCTR3_ACCESS "WC" -// ============================================================================= -// Register : BUSCTRL_PERFSEL3 -// Description : Bus fabric performance event select for PERFCTR3 -// Select an event for PERFCTR3. For each downstream port of the -// main crossbar, four events are available: ACCESS, an access -// took place; ACCESS_CONTESTED, an access took place that -// previously stalled due to contention from other masters; -// STALL_DOWNSTREAM, count cycles where any master stalled due to -// a stall on the downstream bus; STALL_UPSTREAM, count cycles -// where any master stalled for any reason, including contention -// from other masters. -// 0x00 -> siob_proc1_stall_upstream -// 0x01 -> siob_proc1_stall_downstream -// 0x02 -> siob_proc1_access_contested -// 0x03 -> siob_proc1_access -// 0x04 -> siob_proc0_stall_upstream -// 0x05 -> siob_proc0_stall_downstream -// 0x06 -> siob_proc0_access_contested -// 0x07 -> siob_proc0_access -// 0x08 -> apb_stall_upstream -// 0x09 -> apb_stall_downstream -// 0x0a -> apb_access_contested -// 0x0b -> apb_access -// 0x0c -> fastperi_stall_upstream -// 0x0d -> fastperi_stall_downstream -// 0x0e -> fastperi_access_contested -// 0x0f -> fastperi_access -// 0x10 -> sram9_stall_upstream -// 0x11 -> sram9_stall_downstream -// 0x12 -> sram9_access_contested -// 0x13 -> sram9_access -// 0x14 -> sram8_stall_upstream -// 0x15 -> sram8_stall_downstream -// 0x16 -> sram8_access_contested -// 0x17 -> sram8_access -// 0x18 -> sram7_stall_upstream -// 0x19 -> sram7_stall_downstream -// 0x1a -> sram7_access_contested -// 0x1b -> sram7_access -// 0x1c -> sram6_stall_upstream -// 0x1d -> sram6_stall_downstream -// 0x1e -> sram6_access_contested -// 0x1f -> sram6_access -// 0x20 -> sram5_stall_upstream -// 0x21 -> sram5_stall_downstream -// 0x22 -> sram5_access_contested -// 0x23 -> sram5_access -// 0x24 -> sram4_stall_upstream -// 0x25 -> sram4_stall_downstream -// 0x26 -> sram4_access_contested -// 0x27 -> sram4_access -// 0x28 -> sram3_stall_upstream -// 0x29 -> sram3_stall_downstream -// 0x2a -> sram3_access_contested -// 0x2b -> sram3_access -// 0x2c -> sram2_stall_upstream -// 0x2d -> sram2_stall_downstream -// 0x2e -> sram2_access_contested -// 0x2f -> sram2_access -// 0x30 -> sram1_stall_upstream -// 0x31 -> sram1_stall_downstream -// 0x32 -> sram1_access_contested -// 0x33 -> sram1_access -// 0x34 -> sram0_stall_upstream -// 0x35 -> sram0_stall_downstream -// 0x36 -> sram0_access_contested -// 0x37 -> sram0_access -// 0x38 -> xip_main1_stall_upstream -// 0x39 -> xip_main1_stall_downstream -// 0x3a -> xip_main1_access_contested -// 0x3b -> xip_main1_access -// 0x3c -> xip_main0_stall_upstream -// 0x3d -> xip_main0_stall_downstream -// 0x3e -> xip_main0_access_contested -// 0x3f -> xip_main0_access -// 0x40 -> rom_stall_upstream -// 0x41 -> rom_stall_downstream -// 0x42 -> rom_access_contested -// 0x43 -> rom_access -#define BUSCTRL_PERFSEL3_OFFSET _u(0x00000028) -#define BUSCTRL_PERFSEL3_BITS _u(0x0000007f) -#define BUSCTRL_PERFSEL3_RESET _u(0x0000001f) -#define BUSCTRL_PERFSEL3_MSB _u(6) -#define BUSCTRL_PERFSEL3_LSB _u(0) -#define BUSCTRL_PERFSEL3_ACCESS "RW" -#define BUSCTRL_PERFSEL3_VALUE_SIOB_PROC1_STALL_UPSTREAM _u(0x00) -#define BUSCTRL_PERFSEL3_VALUE_SIOB_PROC1_STALL_DOWNSTREAM _u(0x01) -#define BUSCTRL_PERFSEL3_VALUE_SIOB_PROC1_ACCESS_CONTESTED _u(0x02) -#define BUSCTRL_PERFSEL3_VALUE_SIOB_PROC1_ACCESS _u(0x03) -#define BUSCTRL_PERFSEL3_VALUE_SIOB_PROC0_STALL_UPSTREAM _u(0x04) -#define BUSCTRL_PERFSEL3_VALUE_SIOB_PROC0_STALL_DOWNSTREAM _u(0x05) -#define BUSCTRL_PERFSEL3_VALUE_SIOB_PROC0_ACCESS_CONTESTED _u(0x06) -#define BUSCTRL_PERFSEL3_VALUE_SIOB_PROC0_ACCESS _u(0x07) -#define BUSCTRL_PERFSEL3_VALUE_APB_STALL_UPSTREAM _u(0x08) -#define BUSCTRL_PERFSEL3_VALUE_APB_STALL_DOWNSTREAM _u(0x09) -#define BUSCTRL_PERFSEL3_VALUE_APB_ACCESS_CONTESTED _u(0x0a) -#define BUSCTRL_PERFSEL3_VALUE_APB_ACCESS _u(0x0b) -#define BUSCTRL_PERFSEL3_VALUE_FASTPERI_STALL_UPSTREAM _u(0x0c) -#define BUSCTRL_PERFSEL3_VALUE_FASTPERI_STALL_DOWNSTREAM _u(0x0d) -#define BUSCTRL_PERFSEL3_VALUE_FASTPERI_ACCESS_CONTESTED _u(0x0e) -#define BUSCTRL_PERFSEL3_VALUE_FASTPERI_ACCESS _u(0x0f) -#define BUSCTRL_PERFSEL3_VALUE_SRAM9_STALL_UPSTREAM _u(0x10) -#define BUSCTRL_PERFSEL3_VALUE_SRAM9_STALL_DOWNSTREAM _u(0x11) -#define BUSCTRL_PERFSEL3_VALUE_SRAM9_ACCESS_CONTESTED _u(0x12) -#define BUSCTRL_PERFSEL3_VALUE_SRAM9_ACCESS _u(0x13) -#define BUSCTRL_PERFSEL3_VALUE_SRAM8_STALL_UPSTREAM _u(0x14) -#define BUSCTRL_PERFSEL3_VALUE_SRAM8_STALL_DOWNSTREAM _u(0x15) -#define BUSCTRL_PERFSEL3_VALUE_SRAM8_ACCESS_CONTESTED _u(0x16) -#define BUSCTRL_PERFSEL3_VALUE_SRAM8_ACCESS _u(0x17) -#define BUSCTRL_PERFSEL3_VALUE_SRAM7_STALL_UPSTREAM _u(0x18) -#define BUSCTRL_PERFSEL3_VALUE_SRAM7_STALL_DOWNSTREAM _u(0x19) -#define BUSCTRL_PERFSEL3_VALUE_SRAM7_ACCESS_CONTESTED _u(0x1a) -#define BUSCTRL_PERFSEL3_VALUE_SRAM7_ACCESS _u(0x1b) -#define BUSCTRL_PERFSEL3_VALUE_SRAM6_STALL_UPSTREAM _u(0x1c) -#define BUSCTRL_PERFSEL3_VALUE_SRAM6_STALL_DOWNSTREAM _u(0x1d) -#define BUSCTRL_PERFSEL3_VALUE_SRAM6_ACCESS_CONTESTED _u(0x1e) -#define BUSCTRL_PERFSEL3_VALUE_SRAM6_ACCESS _u(0x1f) -#define BUSCTRL_PERFSEL3_VALUE_SRAM5_STALL_UPSTREAM _u(0x20) -#define BUSCTRL_PERFSEL3_VALUE_SRAM5_STALL_DOWNSTREAM _u(0x21) -#define BUSCTRL_PERFSEL3_VALUE_SRAM5_ACCESS_CONTESTED _u(0x22) -#define BUSCTRL_PERFSEL3_VALUE_SRAM5_ACCESS _u(0x23) -#define BUSCTRL_PERFSEL3_VALUE_SRAM4_STALL_UPSTREAM _u(0x24) -#define BUSCTRL_PERFSEL3_VALUE_SRAM4_STALL_DOWNSTREAM _u(0x25) -#define BUSCTRL_PERFSEL3_VALUE_SRAM4_ACCESS_CONTESTED _u(0x26) -#define BUSCTRL_PERFSEL3_VALUE_SRAM4_ACCESS _u(0x27) -#define BUSCTRL_PERFSEL3_VALUE_SRAM3_STALL_UPSTREAM _u(0x28) -#define BUSCTRL_PERFSEL3_VALUE_SRAM3_STALL_DOWNSTREAM _u(0x29) -#define BUSCTRL_PERFSEL3_VALUE_SRAM3_ACCESS_CONTESTED _u(0x2a) -#define BUSCTRL_PERFSEL3_VALUE_SRAM3_ACCESS _u(0x2b) -#define BUSCTRL_PERFSEL3_VALUE_SRAM2_STALL_UPSTREAM _u(0x2c) -#define BUSCTRL_PERFSEL3_VALUE_SRAM2_STALL_DOWNSTREAM _u(0x2d) -#define BUSCTRL_PERFSEL3_VALUE_SRAM2_ACCESS_CONTESTED _u(0x2e) -#define BUSCTRL_PERFSEL3_VALUE_SRAM2_ACCESS _u(0x2f) -#define BUSCTRL_PERFSEL3_VALUE_SRAM1_STALL_UPSTREAM _u(0x30) -#define BUSCTRL_PERFSEL3_VALUE_SRAM1_STALL_DOWNSTREAM _u(0x31) -#define BUSCTRL_PERFSEL3_VALUE_SRAM1_ACCESS_CONTESTED _u(0x32) -#define BUSCTRL_PERFSEL3_VALUE_SRAM1_ACCESS _u(0x33) -#define BUSCTRL_PERFSEL3_VALUE_SRAM0_STALL_UPSTREAM _u(0x34) -#define BUSCTRL_PERFSEL3_VALUE_SRAM0_STALL_DOWNSTREAM _u(0x35) -#define BUSCTRL_PERFSEL3_VALUE_SRAM0_ACCESS_CONTESTED _u(0x36) -#define BUSCTRL_PERFSEL3_VALUE_SRAM0_ACCESS _u(0x37) -#define BUSCTRL_PERFSEL3_VALUE_XIP_MAIN1_STALL_UPSTREAM _u(0x38) -#define BUSCTRL_PERFSEL3_VALUE_XIP_MAIN1_STALL_DOWNSTREAM _u(0x39) -#define BUSCTRL_PERFSEL3_VALUE_XIP_MAIN1_ACCESS_CONTESTED _u(0x3a) -#define BUSCTRL_PERFSEL3_VALUE_XIP_MAIN1_ACCESS _u(0x3b) -#define BUSCTRL_PERFSEL3_VALUE_XIP_MAIN0_STALL_UPSTREAM _u(0x3c) -#define BUSCTRL_PERFSEL3_VALUE_XIP_MAIN0_STALL_DOWNSTREAM _u(0x3d) -#define BUSCTRL_PERFSEL3_VALUE_XIP_MAIN0_ACCESS_CONTESTED _u(0x3e) -#define BUSCTRL_PERFSEL3_VALUE_XIP_MAIN0_ACCESS _u(0x3f) -#define BUSCTRL_PERFSEL3_VALUE_ROM_STALL_UPSTREAM _u(0x40) -#define BUSCTRL_PERFSEL3_VALUE_ROM_STALL_DOWNSTREAM _u(0x41) -#define BUSCTRL_PERFSEL3_VALUE_ROM_ACCESS_CONTESTED _u(0x42) -#define BUSCTRL_PERFSEL3_VALUE_ROM_ACCESS _u(0x43) -// ============================================================================= -#endif // _HARDWARE_REGS_BUSCTRL_H - diff --git a/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/clocks.h b/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/clocks.h deleted file mode 100644 index fd560c9102..0000000000 --- a/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/clocks.h +++ /dev/null @@ -1,2764 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -// ============================================================================= -// Register block : CLOCKS -// Version : 1 -// Bus type : apb -// ============================================================================= -#ifndef _HARDWARE_REGS_CLOCKS_H -#define _HARDWARE_REGS_CLOCKS_H -// ============================================================================= -// Register : CLOCKS_CLK_GPOUT0_CTRL -// Description : Clock control, can be changed on-the-fly (except for auxsrc) -#define CLOCKS_CLK_GPOUT0_CTRL_OFFSET _u(0x00000000) -#define CLOCKS_CLK_GPOUT0_CTRL_BITS _u(0x10131de0) -#define CLOCKS_CLK_GPOUT0_CTRL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_GPOUT0_CTRL_ENABLED -// Description : clock generator is enabled -#define CLOCKS_CLK_GPOUT0_CTRL_ENABLED_RESET _u(0x0) -#define CLOCKS_CLK_GPOUT0_CTRL_ENABLED_BITS _u(0x10000000) -#define CLOCKS_CLK_GPOUT0_CTRL_ENABLED_MSB _u(28) -#define CLOCKS_CLK_GPOUT0_CTRL_ENABLED_LSB _u(28) -#define CLOCKS_CLK_GPOUT0_CTRL_ENABLED_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_GPOUT0_CTRL_NUDGE -// Description : An edge on this signal shifts the phase of the output by 1 -// cycle of the input clock -// This can be done at any time -#define CLOCKS_CLK_GPOUT0_CTRL_NUDGE_RESET _u(0x0) -#define CLOCKS_CLK_GPOUT0_CTRL_NUDGE_BITS _u(0x00100000) -#define CLOCKS_CLK_GPOUT0_CTRL_NUDGE_MSB _u(20) -#define CLOCKS_CLK_GPOUT0_CTRL_NUDGE_LSB _u(20) -#define CLOCKS_CLK_GPOUT0_CTRL_NUDGE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_GPOUT0_CTRL_PHASE -// Description : This delays the enable signal by up to 3 cycles of the input -// clock -// This must be set before the clock is enabled to have any effect -#define CLOCKS_CLK_GPOUT0_CTRL_PHASE_RESET _u(0x0) -#define CLOCKS_CLK_GPOUT0_CTRL_PHASE_BITS _u(0x00030000) -#define CLOCKS_CLK_GPOUT0_CTRL_PHASE_MSB _u(17) -#define CLOCKS_CLK_GPOUT0_CTRL_PHASE_LSB _u(16) -#define CLOCKS_CLK_GPOUT0_CTRL_PHASE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_GPOUT0_CTRL_DC50 -// Description : Enables duty cycle correction for odd divisors, can be changed -// on-the-fly -#define CLOCKS_CLK_GPOUT0_CTRL_DC50_RESET _u(0x0) -#define CLOCKS_CLK_GPOUT0_CTRL_DC50_BITS _u(0x00001000) -#define CLOCKS_CLK_GPOUT0_CTRL_DC50_MSB _u(12) -#define CLOCKS_CLK_GPOUT0_CTRL_DC50_LSB _u(12) -#define CLOCKS_CLK_GPOUT0_CTRL_DC50_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_GPOUT0_CTRL_ENABLE -// Description : Starts and stops the clock generator cleanly -#define CLOCKS_CLK_GPOUT0_CTRL_ENABLE_RESET _u(0x0) -#define CLOCKS_CLK_GPOUT0_CTRL_ENABLE_BITS _u(0x00000800) -#define CLOCKS_CLK_GPOUT0_CTRL_ENABLE_MSB _u(11) -#define CLOCKS_CLK_GPOUT0_CTRL_ENABLE_LSB _u(11) -#define CLOCKS_CLK_GPOUT0_CTRL_ENABLE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_GPOUT0_CTRL_KILL -// Description : Asynchronously kills the clock generator, enable must be set -// low before deasserting kill -#define CLOCKS_CLK_GPOUT0_CTRL_KILL_RESET _u(0x0) -#define CLOCKS_CLK_GPOUT0_CTRL_KILL_BITS _u(0x00000400) -#define CLOCKS_CLK_GPOUT0_CTRL_KILL_MSB _u(10) -#define CLOCKS_CLK_GPOUT0_CTRL_KILL_LSB _u(10) -#define CLOCKS_CLK_GPOUT0_CTRL_KILL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_GPOUT0_CTRL_AUXSRC -// Description : Selects the auxiliary clock source, will glitch when switching -// 0x0 -> clksrc_pll_sys -// 0x1 -> clksrc_gpin0 -// 0x2 -> clksrc_gpin1 -// 0x3 -> clksrc_pll_usb -// 0x4 -> clksrc_pll_usb_primary_ref_opcg -// 0x5 -> rosc_clksrc -// 0x6 -> xosc_clksrc -// 0x7 -> lposc_clksrc -// 0x8 -> clk_sys -// 0x9 -> clk_usb -// 0xa -> clk_adc -// 0xb -> clk_ref -// 0xc -> clk_peri -// 0xd -> clk_hstx -// 0xe -> otp_clk2fc -#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_RESET _u(0x0) -#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_BITS _u(0x000001e0) -#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_MSB _u(8) -#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_LSB _u(5) -#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_ACCESS "RW" -#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS _u(0x0) -#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 _u(0x1) -#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 _u(0x2) -#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB _u(0x3) -#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB_PRIMARY_REF_OPCG _u(0x4) -#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_ROSC_CLKSRC _u(0x5) -#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_XOSC_CLKSRC _u(0x6) -#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_LPOSC_CLKSRC _u(0x7) -#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLK_SYS _u(0x8) -#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLK_USB _u(0x9) -#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLK_ADC _u(0xa) -#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLK_REF _u(0xb) -#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLK_PERI _u(0xc) -#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLK_HSTX _u(0xd) -#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_OTP_CLK2FC _u(0xe) -// ============================================================================= -// Register : CLOCKS_CLK_GPOUT0_DIV -#define CLOCKS_CLK_GPOUT0_DIV_OFFSET _u(0x00000004) -#define CLOCKS_CLK_GPOUT0_DIV_BITS _u(0xffffffff) -#define CLOCKS_CLK_GPOUT0_DIV_RESET _u(0x00010000) -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_GPOUT0_DIV_INT -// Description : Integer part of clock divisor, 0 -> max+1, can be changed on- -// the-fly -#define CLOCKS_CLK_GPOUT0_DIV_INT_RESET _u(0x0001) -#define CLOCKS_CLK_GPOUT0_DIV_INT_BITS _u(0xffff0000) -#define CLOCKS_CLK_GPOUT0_DIV_INT_MSB _u(31) -#define CLOCKS_CLK_GPOUT0_DIV_INT_LSB _u(16) -#define CLOCKS_CLK_GPOUT0_DIV_INT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_GPOUT0_DIV_FRAC -// Description : Fractional component of the divisor, can be changed on-the-fly -#define CLOCKS_CLK_GPOUT0_DIV_FRAC_RESET _u(0x0000) -#define CLOCKS_CLK_GPOUT0_DIV_FRAC_BITS _u(0x0000ffff) -#define CLOCKS_CLK_GPOUT0_DIV_FRAC_MSB _u(15) -#define CLOCKS_CLK_GPOUT0_DIV_FRAC_LSB _u(0) -#define CLOCKS_CLK_GPOUT0_DIV_FRAC_ACCESS "RW" -// ============================================================================= -// Register : CLOCKS_CLK_GPOUT0_SELECTED -// Description : Indicates which src is currently selected (one-hot) -// This slice does not have a glitchless mux (only the AUX_SRC -// field is present, not SRC) so this register is hardwired to -// 0x1. -#define CLOCKS_CLK_GPOUT0_SELECTED_OFFSET _u(0x00000008) -#define CLOCKS_CLK_GPOUT0_SELECTED_BITS _u(0x00000001) -#define CLOCKS_CLK_GPOUT0_SELECTED_RESET _u(0x00000001) -#define CLOCKS_CLK_GPOUT0_SELECTED_MSB _u(0) -#define CLOCKS_CLK_GPOUT0_SELECTED_LSB _u(0) -#define CLOCKS_CLK_GPOUT0_SELECTED_ACCESS "RO" -// ============================================================================= -// Register : CLOCKS_CLK_GPOUT1_CTRL -// Description : Clock control, can be changed on-the-fly (except for auxsrc) -#define CLOCKS_CLK_GPOUT1_CTRL_OFFSET _u(0x0000000c) -#define CLOCKS_CLK_GPOUT1_CTRL_BITS _u(0x10131de0) -#define CLOCKS_CLK_GPOUT1_CTRL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_GPOUT1_CTRL_ENABLED -// Description : clock generator is enabled -#define CLOCKS_CLK_GPOUT1_CTRL_ENABLED_RESET _u(0x0) -#define CLOCKS_CLK_GPOUT1_CTRL_ENABLED_BITS _u(0x10000000) -#define CLOCKS_CLK_GPOUT1_CTRL_ENABLED_MSB _u(28) -#define CLOCKS_CLK_GPOUT1_CTRL_ENABLED_LSB _u(28) -#define CLOCKS_CLK_GPOUT1_CTRL_ENABLED_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_GPOUT1_CTRL_NUDGE -// Description : An edge on this signal shifts the phase of the output by 1 -// cycle of the input clock -// This can be done at any time -#define CLOCKS_CLK_GPOUT1_CTRL_NUDGE_RESET _u(0x0) -#define CLOCKS_CLK_GPOUT1_CTRL_NUDGE_BITS _u(0x00100000) -#define CLOCKS_CLK_GPOUT1_CTRL_NUDGE_MSB _u(20) -#define CLOCKS_CLK_GPOUT1_CTRL_NUDGE_LSB _u(20) -#define CLOCKS_CLK_GPOUT1_CTRL_NUDGE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_GPOUT1_CTRL_PHASE -// Description : This delays the enable signal by up to 3 cycles of the input -// clock -// This must be set before the clock is enabled to have any effect -#define CLOCKS_CLK_GPOUT1_CTRL_PHASE_RESET _u(0x0) -#define CLOCKS_CLK_GPOUT1_CTRL_PHASE_BITS _u(0x00030000) -#define CLOCKS_CLK_GPOUT1_CTRL_PHASE_MSB _u(17) -#define CLOCKS_CLK_GPOUT1_CTRL_PHASE_LSB _u(16) -#define CLOCKS_CLK_GPOUT1_CTRL_PHASE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_GPOUT1_CTRL_DC50 -// Description : Enables duty cycle correction for odd divisors, can be changed -// on-the-fly -#define CLOCKS_CLK_GPOUT1_CTRL_DC50_RESET _u(0x0) -#define CLOCKS_CLK_GPOUT1_CTRL_DC50_BITS _u(0x00001000) -#define CLOCKS_CLK_GPOUT1_CTRL_DC50_MSB _u(12) -#define CLOCKS_CLK_GPOUT1_CTRL_DC50_LSB _u(12) -#define CLOCKS_CLK_GPOUT1_CTRL_DC50_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_GPOUT1_CTRL_ENABLE -// Description : Starts and stops the clock generator cleanly -#define CLOCKS_CLK_GPOUT1_CTRL_ENABLE_RESET _u(0x0) -#define CLOCKS_CLK_GPOUT1_CTRL_ENABLE_BITS _u(0x00000800) -#define CLOCKS_CLK_GPOUT1_CTRL_ENABLE_MSB _u(11) -#define CLOCKS_CLK_GPOUT1_CTRL_ENABLE_LSB _u(11) -#define CLOCKS_CLK_GPOUT1_CTRL_ENABLE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_GPOUT1_CTRL_KILL -// Description : Asynchronously kills the clock generator, enable must be set -// low before deasserting kill -#define CLOCKS_CLK_GPOUT1_CTRL_KILL_RESET _u(0x0) -#define CLOCKS_CLK_GPOUT1_CTRL_KILL_BITS _u(0x00000400) -#define CLOCKS_CLK_GPOUT1_CTRL_KILL_MSB _u(10) -#define CLOCKS_CLK_GPOUT1_CTRL_KILL_LSB _u(10) -#define CLOCKS_CLK_GPOUT1_CTRL_KILL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_GPOUT1_CTRL_AUXSRC -// Description : Selects the auxiliary clock source, will glitch when switching -// 0x0 -> clksrc_pll_sys -// 0x1 -> clksrc_gpin0 -// 0x2 -> clksrc_gpin1 -// 0x3 -> clksrc_pll_usb -// 0x4 -> clksrc_pll_usb_primary_ref_opcg -// 0x5 -> rosc_clksrc -// 0x6 -> xosc_clksrc -// 0x7 -> lposc_clksrc -// 0x8 -> clk_sys -// 0x9 -> clk_usb -// 0xa -> clk_adc -// 0xb -> clk_ref -// 0xc -> clk_peri -// 0xd -> clk_hstx -// 0xe -> otp_clk2fc -#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_RESET _u(0x0) -#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_BITS _u(0x000001e0) -#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_MSB _u(8) -#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_LSB _u(5) -#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_ACCESS "RW" -#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS _u(0x0) -#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 _u(0x1) -#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 _u(0x2) -#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB _u(0x3) -#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB_PRIMARY_REF_OPCG _u(0x4) -#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_ROSC_CLKSRC _u(0x5) -#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_XOSC_CLKSRC _u(0x6) -#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_LPOSC_CLKSRC _u(0x7) -#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLK_SYS _u(0x8) -#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLK_USB _u(0x9) -#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLK_ADC _u(0xa) -#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLK_REF _u(0xb) -#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLK_PERI _u(0xc) -#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLK_HSTX _u(0xd) -#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_OTP_CLK2FC _u(0xe) -// ============================================================================= -// Register : CLOCKS_CLK_GPOUT1_DIV -#define CLOCKS_CLK_GPOUT1_DIV_OFFSET _u(0x00000010) -#define CLOCKS_CLK_GPOUT1_DIV_BITS _u(0xffffffff) -#define CLOCKS_CLK_GPOUT1_DIV_RESET _u(0x00010000) -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_GPOUT1_DIV_INT -// Description : Integer part of clock divisor, 0 -> max+1, can be changed on- -// the-fly -#define CLOCKS_CLK_GPOUT1_DIV_INT_RESET _u(0x0001) -#define CLOCKS_CLK_GPOUT1_DIV_INT_BITS _u(0xffff0000) -#define CLOCKS_CLK_GPOUT1_DIV_INT_MSB _u(31) -#define CLOCKS_CLK_GPOUT1_DIV_INT_LSB _u(16) -#define CLOCKS_CLK_GPOUT1_DIV_INT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_GPOUT1_DIV_FRAC -// Description : Fractional component of the divisor, can be changed on-the-fly -#define CLOCKS_CLK_GPOUT1_DIV_FRAC_RESET _u(0x0000) -#define CLOCKS_CLK_GPOUT1_DIV_FRAC_BITS _u(0x0000ffff) -#define CLOCKS_CLK_GPOUT1_DIV_FRAC_MSB _u(15) -#define CLOCKS_CLK_GPOUT1_DIV_FRAC_LSB _u(0) -#define CLOCKS_CLK_GPOUT1_DIV_FRAC_ACCESS "RW" -// ============================================================================= -// Register : CLOCKS_CLK_GPOUT1_SELECTED -// Description : Indicates which src is currently selected (one-hot) -// This slice does not have a glitchless mux (only the AUX_SRC -// field is present, not SRC) so this register is hardwired to -// 0x1. -#define CLOCKS_CLK_GPOUT1_SELECTED_OFFSET _u(0x00000014) -#define CLOCKS_CLK_GPOUT1_SELECTED_BITS _u(0x00000001) -#define CLOCKS_CLK_GPOUT1_SELECTED_RESET _u(0x00000001) -#define CLOCKS_CLK_GPOUT1_SELECTED_MSB _u(0) -#define CLOCKS_CLK_GPOUT1_SELECTED_LSB _u(0) -#define CLOCKS_CLK_GPOUT1_SELECTED_ACCESS "RO" -// ============================================================================= -// Register : CLOCKS_CLK_GPOUT2_CTRL -// Description : Clock control, can be changed on-the-fly (except for auxsrc) -#define CLOCKS_CLK_GPOUT2_CTRL_OFFSET _u(0x00000018) -#define CLOCKS_CLK_GPOUT2_CTRL_BITS _u(0x10131de0) -#define CLOCKS_CLK_GPOUT2_CTRL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_GPOUT2_CTRL_ENABLED -// Description : clock generator is enabled -#define CLOCKS_CLK_GPOUT2_CTRL_ENABLED_RESET _u(0x0) -#define CLOCKS_CLK_GPOUT2_CTRL_ENABLED_BITS _u(0x10000000) -#define CLOCKS_CLK_GPOUT2_CTRL_ENABLED_MSB _u(28) -#define CLOCKS_CLK_GPOUT2_CTRL_ENABLED_LSB _u(28) -#define CLOCKS_CLK_GPOUT2_CTRL_ENABLED_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_GPOUT2_CTRL_NUDGE -// Description : An edge on this signal shifts the phase of the output by 1 -// cycle of the input clock -// This can be done at any time -#define CLOCKS_CLK_GPOUT2_CTRL_NUDGE_RESET _u(0x0) -#define CLOCKS_CLK_GPOUT2_CTRL_NUDGE_BITS _u(0x00100000) -#define CLOCKS_CLK_GPOUT2_CTRL_NUDGE_MSB _u(20) -#define CLOCKS_CLK_GPOUT2_CTRL_NUDGE_LSB _u(20) -#define CLOCKS_CLK_GPOUT2_CTRL_NUDGE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_GPOUT2_CTRL_PHASE -// Description : This delays the enable signal by up to 3 cycles of the input -// clock -// This must be set before the clock is enabled to have any effect -#define CLOCKS_CLK_GPOUT2_CTRL_PHASE_RESET _u(0x0) -#define CLOCKS_CLK_GPOUT2_CTRL_PHASE_BITS _u(0x00030000) -#define CLOCKS_CLK_GPOUT2_CTRL_PHASE_MSB _u(17) -#define CLOCKS_CLK_GPOUT2_CTRL_PHASE_LSB _u(16) -#define CLOCKS_CLK_GPOUT2_CTRL_PHASE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_GPOUT2_CTRL_DC50 -// Description : Enables duty cycle correction for odd divisors, can be changed -// on-the-fly -#define CLOCKS_CLK_GPOUT2_CTRL_DC50_RESET _u(0x0) -#define CLOCKS_CLK_GPOUT2_CTRL_DC50_BITS _u(0x00001000) -#define CLOCKS_CLK_GPOUT2_CTRL_DC50_MSB _u(12) -#define CLOCKS_CLK_GPOUT2_CTRL_DC50_LSB _u(12) -#define CLOCKS_CLK_GPOUT2_CTRL_DC50_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_GPOUT2_CTRL_ENABLE -// Description : Starts and stops the clock generator cleanly -#define CLOCKS_CLK_GPOUT2_CTRL_ENABLE_RESET _u(0x0) -#define CLOCKS_CLK_GPOUT2_CTRL_ENABLE_BITS _u(0x00000800) -#define CLOCKS_CLK_GPOUT2_CTRL_ENABLE_MSB _u(11) -#define CLOCKS_CLK_GPOUT2_CTRL_ENABLE_LSB _u(11) -#define CLOCKS_CLK_GPOUT2_CTRL_ENABLE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_GPOUT2_CTRL_KILL -// Description : Asynchronously kills the clock generator, enable must be set -// low before deasserting kill -#define CLOCKS_CLK_GPOUT2_CTRL_KILL_RESET _u(0x0) -#define CLOCKS_CLK_GPOUT2_CTRL_KILL_BITS _u(0x00000400) -#define CLOCKS_CLK_GPOUT2_CTRL_KILL_MSB _u(10) -#define CLOCKS_CLK_GPOUT2_CTRL_KILL_LSB _u(10) -#define CLOCKS_CLK_GPOUT2_CTRL_KILL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_GPOUT2_CTRL_AUXSRC -// Description : Selects the auxiliary clock source, will glitch when switching -// 0x0 -> clksrc_pll_sys -// 0x1 -> clksrc_gpin0 -// 0x2 -> clksrc_gpin1 -// 0x3 -> clksrc_pll_usb -// 0x4 -> clksrc_pll_usb_primary_ref_opcg -// 0x5 -> rosc_clksrc_ph -// 0x6 -> xosc_clksrc -// 0x7 -> lposc_clksrc -// 0x8 -> clk_sys -// 0x9 -> clk_usb -// 0xa -> clk_adc -// 0xb -> clk_ref -// 0xc -> clk_peri -// 0xd -> clk_hstx -// 0xe -> otp_clk2fc -#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_RESET _u(0x0) -#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_BITS _u(0x000001e0) -#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_MSB _u(8) -#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_LSB _u(5) -#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_ACCESS "RW" -#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS _u(0x0) -#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 _u(0x1) -#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 _u(0x2) -#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB _u(0x3) -#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB_PRIMARY_REF_OPCG _u(0x4) -#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH _u(0x5) -#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_XOSC_CLKSRC _u(0x6) -#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_LPOSC_CLKSRC _u(0x7) -#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLK_SYS _u(0x8) -#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLK_USB _u(0x9) -#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLK_ADC _u(0xa) -#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLK_REF _u(0xb) -#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLK_PERI _u(0xc) -#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLK_HSTX _u(0xd) -#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_OTP_CLK2FC _u(0xe) -// ============================================================================= -// Register : CLOCKS_CLK_GPOUT2_DIV -#define CLOCKS_CLK_GPOUT2_DIV_OFFSET _u(0x0000001c) -#define CLOCKS_CLK_GPOUT2_DIV_BITS _u(0xffffffff) -#define CLOCKS_CLK_GPOUT2_DIV_RESET _u(0x00010000) -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_GPOUT2_DIV_INT -// Description : Integer part of clock divisor, 0 -> max+1, can be changed on- -// the-fly -#define CLOCKS_CLK_GPOUT2_DIV_INT_RESET _u(0x0001) -#define CLOCKS_CLK_GPOUT2_DIV_INT_BITS _u(0xffff0000) -#define CLOCKS_CLK_GPOUT2_DIV_INT_MSB _u(31) -#define CLOCKS_CLK_GPOUT2_DIV_INT_LSB _u(16) -#define CLOCKS_CLK_GPOUT2_DIV_INT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_GPOUT2_DIV_FRAC -// Description : Fractional component of the divisor, can be changed on-the-fly -#define CLOCKS_CLK_GPOUT2_DIV_FRAC_RESET _u(0x0000) -#define CLOCKS_CLK_GPOUT2_DIV_FRAC_BITS _u(0x0000ffff) -#define CLOCKS_CLK_GPOUT2_DIV_FRAC_MSB _u(15) -#define CLOCKS_CLK_GPOUT2_DIV_FRAC_LSB _u(0) -#define CLOCKS_CLK_GPOUT2_DIV_FRAC_ACCESS "RW" -// ============================================================================= -// Register : CLOCKS_CLK_GPOUT2_SELECTED -// Description : Indicates which src is currently selected (one-hot) -// This slice does not have a glitchless mux (only the AUX_SRC -// field is present, not SRC) so this register is hardwired to -// 0x1. -#define CLOCKS_CLK_GPOUT2_SELECTED_OFFSET _u(0x00000020) -#define CLOCKS_CLK_GPOUT2_SELECTED_BITS _u(0x00000001) -#define CLOCKS_CLK_GPOUT2_SELECTED_RESET _u(0x00000001) -#define CLOCKS_CLK_GPOUT2_SELECTED_MSB _u(0) -#define CLOCKS_CLK_GPOUT2_SELECTED_LSB _u(0) -#define CLOCKS_CLK_GPOUT2_SELECTED_ACCESS "RO" -// ============================================================================= -// Register : CLOCKS_CLK_GPOUT3_CTRL -// Description : Clock control, can be changed on-the-fly (except for auxsrc) -#define CLOCKS_CLK_GPOUT3_CTRL_OFFSET _u(0x00000024) -#define CLOCKS_CLK_GPOUT3_CTRL_BITS _u(0x10131de0) -#define CLOCKS_CLK_GPOUT3_CTRL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_GPOUT3_CTRL_ENABLED -// Description : clock generator is enabled -#define CLOCKS_CLK_GPOUT3_CTRL_ENABLED_RESET _u(0x0) -#define CLOCKS_CLK_GPOUT3_CTRL_ENABLED_BITS _u(0x10000000) -#define CLOCKS_CLK_GPOUT3_CTRL_ENABLED_MSB _u(28) -#define CLOCKS_CLK_GPOUT3_CTRL_ENABLED_LSB _u(28) -#define CLOCKS_CLK_GPOUT3_CTRL_ENABLED_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_GPOUT3_CTRL_NUDGE -// Description : An edge on this signal shifts the phase of the output by 1 -// cycle of the input clock -// This can be done at any time -#define CLOCKS_CLK_GPOUT3_CTRL_NUDGE_RESET _u(0x0) -#define CLOCKS_CLK_GPOUT3_CTRL_NUDGE_BITS _u(0x00100000) -#define CLOCKS_CLK_GPOUT3_CTRL_NUDGE_MSB _u(20) -#define CLOCKS_CLK_GPOUT3_CTRL_NUDGE_LSB _u(20) -#define CLOCKS_CLK_GPOUT3_CTRL_NUDGE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_GPOUT3_CTRL_PHASE -// Description : This delays the enable signal by up to 3 cycles of the input -// clock -// This must be set before the clock is enabled to have any effect -#define CLOCKS_CLK_GPOUT3_CTRL_PHASE_RESET _u(0x0) -#define CLOCKS_CLK_GPOUT3_CTRL_PHASE_BITS _u(0x00030000) -#define CLOCKS_CLK_GPOUT3_CTRL_PHASE_MSB _u(17) -#define CLOCKS_CLK_GPOUT3_CTRL_PHASE_LSB _u(16) -#define CLOCKS_CLK_GPOUT3_CTRL_PHASE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_GPOUT3_CTRL_DC50 -// Description : Enables duty cycle correction for odd divisors, can be changed -// on-the-fly -#define CLOCKS_CLK_GPOUT3_CTRL_DC50_RESET _u(0x0) -#define CLOCKS_CLK_GPOUT3_CTRL_DC50_BITS _u(0x00001000) -#define CLOCKS_CLK_GPOUT3_CTRL_DC50_MSB _u(12) -#define CLOCKS_CLK_GPOUT3_CTRL_DC50_LSB _u(12) -#define CLOCKS_CLK_GPOUT3_CTRL_DC50_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_GPOUT3_CTRL_ENABLE -// Description : Starts and stops the clock generator cleanly -#define CLOCKS_CLK_GPOUT3_CTRL_ENABLE_RESET _u(0x0) -#define CLOCKS_CLK_GPOUT3_CTRL_ENABLE_BITS _u(0x00000800) -#define CLOCKS_CLK_GPOUT3_CTRL_ENABLE_MSB _u(11) -#define CLOCKS_CLK_GPOUT3_CTRL_ENABLE_LSB _u(11) -#define CLOCKS_CLK_GPOUT3_CTRL_ENABLE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_GPOUT3_CTRL_KILL -// Description : Asynchronously kills the clock generator, enable must be set -// low before deasserting kill -#define CLOCKS_CLK_GPOUT3_CTRL_KILL_RESET _u(0x0) -#define CLOCKS_CLK_GPOUT3_CTRL_KILL_BITS _u(0x00000400) -#define CLOCKS_CLK_GPOUT3_CTRL_KILL_MSB _u(10) -#define CLOCKS_CLK_GPOUT3_CTRL_KILL_LSB _u(10) -#define CLOCKS_CLK_GPOUT3_CTRL_KILL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_GPOUT3_CTRL_AUXSRC -// Description : Selects the auxiliary clock source, will glitch when switching -// 0x0 -> clksrc_pll_sys -// 0x1 -> clksrc_gpin0 -// 0x2 -> clksrc_gpin1 -// 0x3 -> clksrc_pll_usb -// 0x4 -> clksrc_pll_usb_primary_ref_opcg -// 0x5 -> rosc_clksrc_ph -// 0x6 -> xosc_clksrc -// 0x7 -> lposc_clksrc -// 0x8 -> clk_sys -// 0x9 -> clk_usb -// 0xa -> clk_adc -// 0xb -> clk_ref -// 0xc -> clk_peri -// 0xd -> clk_hstx -// 0xe -> otp_clk2fc -#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_RESET _u(0x0) -#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_BITS _u(0x000001e0) -#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_MSB _u(8) -#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_LSB _u(5) -#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_ACCESS "RW" -#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS _u(0x0) -#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 _u(0x1) -#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 _u(0x2) -#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB _u(0x3) -#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB_PRIMARY_REF_OPCG _u(0x4) -#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH _u(0x5) -#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_XOSC_CLKSRC _u(0x6) -#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_LPOSC_CLKSRC _u(0x7) -#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLK_SYS _u(0x8) -#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLK_USB _u(0x9) -#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLK_ADC _u(0xa) -#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLK_REF _u(0xb) -#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLK_PERI _u(0xc) -#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLK_HSTX _u(0xd) -#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_OTP_CLK2FC _u(0xe) -// ============================================================================= -// Register : CLOCKS_CLK_GPOUT3_DIV -#define CLOCKS_CLK_GPOUT3_DIV_OFFSET _u(0x00000028) -#define CLOCKS_CLK_GPOUT3_DIV_BITS _u(0xffffffff) -#define CLOCKS_CLK_GPOUT3_DIV_RESET _u(0x00010000) -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_GPOUT3_DIV_INT -// Description : Integer part of clock divisor, 0 -> max+1, can be changed on- -// the-fly -#define CLOCKS_CLK_GPOUT3_DIV_INT_RESET _u(0x0001) -#define CLOCKS_CLK_GPOUT3_DIV_INT_BITS _u(0xffff0000) -#define CLOCKS_CLK_GPOUT3_DIV_INT_MSB _u(31) -#define CLOCKS_CLK_GPOUT3_DIV_INT_LSB _u(16) -#define CLOCKS_CLK_GPOUT3_DIV_INT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_GPOUT3_DIV_FRAC -// Description : Fractional component of the divisor, can be changed on-the-fly -#define CLOCKS_CLK_GPOUT3_DIV_FRAC_RESET _u(0x0000) -#define CLOCKS_CLK_GPOUT3_DIV_FRAC_BITS _u(0x0000ffff) -#define CLOCKS_CLK_GPOUT3_DIV_FRAC_MSB _u(15) -#define CLOCKS_CLK_GPOUT3_DIV_FRAC_LSB _u(0) -#define CLOCKS_CLK_GPOUT3_DIV_FRAC_ACCESS "RW" -// ============================================================================= -// Register : CLOCKS_CLK_GPOUT3_SELECTED -// Description : Indicates which src is currently selected (one-hot) -// This slice does not have a glitchless mux (only the AUX_SRC -// field is present, not SRC) so this register is hardwired to -// 0x1. -#define CLOCKS_CLK_GPOUT3_SELECTED_OFFSET _u(0x0000002c) -#define CLOCKS_CLK_GPOUT3_SELECTED_BITS _u(0x00000001) -#define CLOCKS_CLK_GPOUT3_SELECTED_RESET _u(0x00000001) -#define CLOCKS_CLK_GPOUT3_SELECTED_MSB _u(0) -#define CLOCKS_CLK_GPOUT3_SELECTED_LSB _u(0) -#define CLOCKS_CLK_GPOUT3_SELECTED_ACCESS "RO" -// ============================================================================= -// Register : CLOCKS_CLK_REF_CTRL -// Description : Clock control, can be changed on-the-fly (except for auxsrc) -#define CLOCKS_CLK_REF_CTRL_OFFSET _u(0x00000030) -#define CLOCKS_CLK_REF_CTRL_BITS _u(0x00000063) -#define CLOCKS_CLK_REF_CTRL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_REF_CTRL_AUXSRC -// Description : Selects the auxiliary clock source, will glitch when switching -// 0x0 -> clksrc_pll_usb -// 0x1 -> clksrc_gpin0 -// 0x2 -> clksrc_gpin1 -// 0x3 -> clksrc_pll_usb_primary_ref_opcg -#define CLOCKS_CLK_REF_CTRL_AUXSRC_RESET _u(0x0) -#define CLOCKS_CLK_REF_CTRL_AUXSRC_BITS _u(0x00000060) -#define CLOCKS_CLK_REF_CTRL_AUXSRC_MSB _u(6) -#define CLOCKS_CLK_REF_CTRL_AUXSRC_LSB _u(5) -#define CLOCKS_CLK_REF_CTRL_AUXSRC_ACCESS "RW" -#define CLOCKS_CLK_REF_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB _u(0x0) -#define CLOCKS_CLK_REF_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 _u(0x1) -#define CLOCKS_CLK_REF_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 _u(0x2) -#define CLOCKS_CLK_REF_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB_PRIMARY_REF_OPCG _u(0x3) -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_REF_CTRL_SRC -// Description : Selects the clock source glitchlessly, can be changed on-the- -// fly -// 0x0 -> rosc_clksrc_ph -// 0x1 -> clksrc_clk_ref_aux -// 0x2 -> xosc_clksrc -// 0x3 -> lposc_clksrc -#define CLOCKS_CLK_REF_CTRL_SRC_RESET "-" -#define CLOCKS_CLK_REF_CTRL_SRC_BITS _u(0x00000003) -#define CLOCKS_CLK_REF_CTRL_SRC_MSB _u(1) -#define CLOCKS_CLK_REF_CTRL_SRC_LSB _u(0) -#define CLOCKS_CLK_REF_CTRL_SRC_ACCESS "RW" -#define CLOCKS_CLK_REF_CTRL_SRC_VALUE_ROSC_CLKSRC_PH _u(0x0) -#define CLOCKS_CLK_REF_CTRL_SRC_VALUE_CLKSRC_CLK_REF_AUX _u(0x1) -#define CLOCKS_CLK_REF_CTRL_SRC_VALUE_XOSC_CLKSRC _u(0x2) -#define CLOCKS_CLK_REF_CTRL_SRC_VALUE_LPOSC_CLKSRC _u(0x3) -// ============================================================================= -// Register : CLOCKS_CLK_REF_DIV -#define CLOCKS_CLK_REF_DIV_OFFSET _u(0x00000034) -#define CLOCKS_CLK_REF_DIV_BITS _u(0x00ff0000) -#define CLOCKS_CLK_REF_DIV_RESET _u(0x00010000) -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_REF_DIV_INT -// Description : Integer part of clock divisor, 0 -> max+1, can be changed on- -// the-fly -#define CLOCKS_CLK_REF_DIV_INT_RESET _u(0x01) -#define CLOCKS_CLK_REF_DIV_INT_BITS _u(0x00ff0000) -#define CLOCKS_CLK_REF_DIV_INT_MSB _u(23) -#define CLOCKS_CLK_REF_DIV_INT_LSB _u(16) -#define CLOCKS_CLK_REF_DIV_INT_ACCESS "RW" -// ============================================================================= -// Register : CLOCKS_CLK_REF_SELECTED -// Description : Indicates which src is currently selected (one-hot) -// The glitchless multiplexer does not switch instantaneously (to -// avoid glitches), so software should poll this register to wait -// for the switch to complete. This register contains one decoded -// bit for each of the clock sources enumerated in the CTRL SRC -// field. At most one of these bits will be set at any time, -// indicating that clock is currently present at the output of the -// glitchless mux. Whilst switching is in progress, this register -// may briefly show all-0s. -#define CLOCKS_CLK_REF_SELECTED_OFFSET _u(0x00000038) -#define CLOCKS_CLK_REF_SELECTED_BITS _u(0x0000000f) -#define CLOCKS_CLK_REF_SELECTED_RESET _u(0x00000001) -#define CLOCKS_CLK_REF_SELECTED_MSB _u(3) -#define CLOCKS_CLK_REF_SELECTED_LSB _u(0) -#define CLOCKS_CLK_REF_SELECTED_ACCESS "RO" -// ============================================================================= -// Register : CLOCKS_CLK_SYS_CTRL -// Description : Clock control, can be changed on-the-fly (except for auxsrc) -#define CLOCKS_CLK_SYS_CTRL_OFFSET _u(0x0000003c) -#define CLOCKS_CLK_SYS_CTRL_BITS _u(0x000000e1) -#define CLOCKS_CLK_SYS_CTRL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_SYS_CTRL_AUXSRC -// Description : Selects the auxiliary clock source, will glitch when switching -// 0x0 -> clksrc_pll_sys -// 0x1 -> clksrc_pll_usb -// 0x2 -> rosc_clksrc -// 0x3 -> xosc_clksrc -// 0x4 -> clksrc_gpin0 -// 0x5 -> clksrc_gpin1 -#define CLOCKS_CLK_SYS_CTRL_AUXSRC_RESET _u(0x0) -#define CLOCKS_CLK_SYS_CTRL_AUXSRC_BITS _u(0x000000e0) -#define CLOCKS_CLK_SYS_CTRL_AUXSRC_MSB _u(7) -#define CLOCKS_CLK_SYS_CTRL_AUXSRC_LSB _u(5) -#define CLOCKS_CLK_SYS_CTRL_AUXSRC_ACCESS "RW" -#define CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS _u(0x0) -#define CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB _u(0x1) -#define CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_ROSC_CLKSRC _u(0x2) -#define CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_XOSC_CLKSRC _u(0x3) -#define CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 _u(0x4) -#define CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 _u(0x5) -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_SYS_CTRL_SRC -// Description : Selects the clock source glitchlessly, can be changed on-the- -// fly -// 0x0 -> clk_ref -// 0x1 -> clksrc_clk_sys_aux -#define CLOCKS_CLK_SYS_CTRL_SRC_RESET _u(0x0) -#define CLOCKS_CLK_SYS_CTRL_SRC_BITS _u(0x00000001) -#define CLOCKS_CLK_SYS_CTRL_SRC_MSB _u(0) -#define CLOCKS_CLK_SYS_CTRL_SRC_LSB _u(0) -#define CLOCKS_CLK_SYS_CTRL_SRC_ACCESS "RW" -#define CLOCKS_CLK_SYS_CTRL_SRC_VALUE_CLK_REF _u(0x0) -#define CLOCKS_CLK_SYS_CTRL_SRC_VALUE_CLKSRC_CLK_SYS_AUX _u(0x1) -// ============================================================================= -// Register : CLOCKS_CLK_SYS_DIV -#define CLOCKS_CLK_SYS_DIV_OFFSET _u(0x00000040) -#define CLOCKS_CLK_SYS_DIV_BITS _u(0xffffffff) -#define CLOCKS_CLK_SYS_DIV_RESET _u(0x00010000) -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_SYS_DIV_INT -// Description : Integer part of clock divisor, 0 -> max+1, can be changed on- -// the-fly -#define CLOCKS_CLK_SYS_DIV_INT_RESET _u(0x0001) -#define CLOCKS_CLK_SYS_DIV_INT_BITS _u(0xffff0000) -#define CLOCKS_CLK_SYS_DIV_INT_MSB _u(31) -#define CLOCKS_CLK_SYS_DIV_INT_LSB _u(16) -#define CLOCKS_CLK_SYS_DIV_INT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_SYS_DIV_FRAC -// Description : Fractional component of the divisor, can be changed on-the-fly -#define CLOCKS_CLK_SYS_DIV_FRAC_RESET _u(0x0000) -#define CLOCKS_CLK_SYS_DIV_FRAC_BITS _u(0x0000ffff) -#define CLOCKS_CLK_SYS_DIV_FRAC_MSB _u(15) -#define CLOCKS_CLK_SYS_DIV_FRAC_LSB _u(0) -#define CLOCKS_CLK_SYS_DIV_FRAC_ACCESS "RW" -// ============================================================================= -// Register : CLOCKS_CLK_SYS_SELECTED -// Description : Indicates which src is currently selected (one-hot) -// The glitchless multiplexer does not switch instantaneously (to -// avoid glitches), so software should poll this register to wait -// for the switch to complete. This register contains one decoded -// bit for each of the clock sources enumerated in the CTRL SRC -// field. At most one of these bits will be set at any time, -// indicating that clock is currently present at the output of the -// glitchless mux. Whilst switching is in progress, this register -// may briefly show all-0s. -#define CLOCKS_CLK_SYS_SELECTED_OFFSET _u(0x00000044) -#define CLOCKS_CLK_SYS_SELECTED_BITS _u(0x00000003) -#define CLOCKS_CLK_SYS_SELECTED_RESET _u(0x00000001) -#define CLOCKS_CLK_SYS_SELECTED_MSB _u(1) -#define CLOCKS_CLK_SYS_SELECTED_LSB _u(0) -#define CLOCKS_CLK_SYS_SELECTED_ACCESS "RO" -// ============================================================================= -// Register : CLOCKS_CLK_PERI_CTRL -// Description : Clock control, can be changed on-the-fly (except for auxsrc) -#define CLOCKS_CLK_PERI_CTRL_OFFSET _u(0x00000048) -#define CLOCKS_CLK_PERI_CTRL_BITS _u(0x10000ce0) -#define CLOCKS_CLK_PERI_CTRL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_PERI_CTRL_ENABLED -// Description : clock generator is enabled -#define CLOCKS_CLK_PERI_CTRL_ENABLED_RESET _u(0x0) -#define CLOCKS_CLK_PERI_CTRL_ENABLED_BITS _u(0x10000000) -#define CLOCKS_CLK_PERI_CTRL_ENABLED_MSB _u(28) -#define CLOCKS_CLK_PERI_CTRL_ENABLED_LSB _u(28) -#define CLOCKS_CLK_PERI_CTRL_ENABLED_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_PERI_CTRL_ENABLE -// Description : Starts and stops the clock generator cleanly -#define CLOCKS_CLK_PERI_CTRL_ENABLE_RESET _u(0x0) -#define CLOCKS_CLK_PERI_CTRL_ENABLE_BITS _u(0x00000800) -#define CLOCKS_CLK_PERI_CTRL_ENABLE_MSB _u(11) -#define CLOCKS_CLK_PERI_CTRL_ENABLE_LSB _u(11) -#define CLOCKS_CLK_PERI_CTRL_ENABLE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_PERI_CTRL_KILL -// Description : Asynchronously kills the clock generator, enable must be set -// low before deasserting kill -#define CLOCKS_CLK_PERI_CTRL_KILL_RESET _u(0x0) -#define CLOCKS_CLK_PERI_CTRL_KILL_BITS _u(0x00000400) -#define CLOCKS_CLK_PERI_CTRL_KILL_MSB _u(10) -#define CLOCKS_CLK_PERI_CTRL_KILL_LSB _u(10) -#define CLOCKS_CLK_PERI_CTRL_KILL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_PERI_CTRL_AUXSRC -// Description : Selects the auxiliary clock source, will glitch when switching -// 0x0 -> clk_sys -// 0x1 -> clksrc_pll_sys -// 0x2 -> clksrc_pll_usb -// 0x3 -> rosc_clksrc_ph -// 0x4 -> xosc_clksrc -// 0x5 -> clksrc_gpin0 -// 0x6 -> clksrc_gpin1 -#define CLOCKS_CLK_PERI_CTRL_AUXSRC_RESET _u(0x0) -#define CLOCKS_CLK_PERI_CTRL_AUXSRC_BITS _u(0x000000e0) -#define CLOCKS_CLK_PERI_CTRL_AUXSRC_MSB _u(7) -#define CLOCKS_CLK_PERI_CTRL_AUXSRC_LSB _u(5) -#define CLOCKS_CLK_PERI_CTRL_AUXSRC_ACCESS "RW" -#define CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLK_SYS _u(0x0) -#define CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS _u(0x1) -#define CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB _u(0x2) -#define CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH _u(0x3) -#define CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_XOSC_CLKSRC _u(0x4) -#define CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 _u(0x5) -#define CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 _u(0x6) -// ============================================================================= -// Register : CLOCKS_CLK_PERI_DIV -#define CLOCKS_CLK_PERI_DIV_OFFSET _u(0x0000004c) -#define CLOCKS_CLK_PERI_DIV_BITS _u(0x00030000) -#define CLOCKS_CLK_PERI_DIV_RESET _u(0x00010000) -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_PERI_DIV_INT -// Description : Integer part of clock divisor, 0 -> max+1, can be changed on- -// the-fly -#define CLOCKS_CLK_PERI_DIV_INT_RESET _u(0x1) -#define CLOCKS_CLK_PERI_DIV_INT_BITS _u(0x00030000) -#define CLOCKS_CLK_PERI_DIV_INT_MSB _u(17) -#define CLOCKS_CLK_PERI_DIV_INT_LSB _u(16) -#define CLOCKS_CLK_PERI_DIV_INT_ACCESS "RW" -// ============================================================================= -// Register : CLOCKS_CLK_PERI_SELECTED -// Description : Indicates which src is currently selected (one-hot) -// This slice does not have a glitchless mux (only the AUX_SRC -// field is present, not SRC) so this register is hardwired to -// 0x1. -#define CLOCKS_CLK_PERI_SELECTED_OFFSET _u(0x00000050) -#define CLOCKS_CLK_PERI_SELECTED_BITS _u(0x00000001) -#define CLOCKS_CLK_PERI_SELECTED_RESET _u(0x00000001) -#define CLOCKS_CLK_PERI_SELECTED_MSB _u(0) -#define CLOCKS_CLK_PERI_SELECTED_LSB _u(0) -#define CLOCKS_CLK_PERI_SELECTED_ACCESS "RO" -// ============================================================================= -// Register : CLOCKS_CLK_HSTX_CTRL -// Description : Clock control, can be changed on-the-fly (except for auxsrc) -#define CLOCKS_CLK_HSTX_CTRL_OFFSET _u(0x00000054) -#define CLOCKS_CLK_HSTX_CTRL_BITS _u(0x10130ce0) -#define CLOCKS_CLK_HSTX_CTRL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_HSTX_CTRL_ENABLED -// Description : clock generator is enabled -#define CLOCKS_CLK_HSTX_CTRL_ENABLED_RESET _u(0x0) -#define CLOCKS_CLK_HSTX_CTRL_ENABLED_BITS _u(0x10000000) -#define CLOCKS_CLK_HSTX_CTRL_ENABLED_MSB _u(28) -#define CLOCKS_CLK_HSTX_CTRL_ENABLED_LSB _u(28) -#define CLOCKS_CLK_HSTX_CTRL_ENABLED_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_HSTX_CTRL_NUDGE -// Description : An edge on this signal shifts the phase of the output by 1 -// cycle of the input clock -// This can be done at any time -#define CLOCKS_CLK_HSTX_CTRL_NUDGE_RESET _u(0x0) -#define CLOCKS_CLK_HSTX_CTRL_NUDGE_BITS _u(0x00100000) -#define CLOCKS_CLK_HSTX_CTRL_NUDGE_MSB _u(20) -#define CLOCKS_CLK_HSTX_CTRL_NUDGE_LSB _u(20) -#define CLOCKS_CLK_HSTX_CTRL_NUDGE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_HSTX_CTRL_PHASE -// Description : This delays the enable signal by up to 3 cycles of the input -// clock -// This must be set before the clock is enabled to have any effect -#define CLOCKS_CLK_HSTX_CTRL_PHASE_RESET _u(0x0) -#define CLOCKS_CLK_HSTX_CTRL_PHASE_BITS _u(0x00030000) -#define CLOCKS_CLK_HSTX_CTRL_PHASE_MSB _u(17) -#define CLOCKS_CLK_HSTX_CTRL_PHASE_LSB _u(16) -#define CLOCKS_CLK_HSTX_CTRL_PHASE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_HSTX_CTRL_ENABLE -// Description : Starts and stops the clock generator cleanly -#define CLOCKS_CLK_HSTX_CTRL_ENABLE_RESET _u(0x0) -#define CLOCKS_CLK_HSTX_CTRL_ENABLE_BITS _u(0x00000800) -#define CLOCKS_CLK_HSTX_CTRL_ENABLE_MSB _u(11) -#define CLOCKS_CLK_HSTX_CTRL_ENABLE_LSB _u(11) -#define CLOCKS_CLK_HSTX_CTRL_ENABLE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_HSTX_CTRL_KILL -// Description : Asynchronously kills the clock generator, enable must be set -// low before deasserting kill -#define CLOCKS_CLK_HSTX_CTRL_KILL_RESET _u(0x0) -#define CLOCKS_CLK_HSTX_CTRL_KILL_BITS _u(0x00000400) -#define CLOCKS_CLK_HSTX_CTRL_KILL_MSB _u(10) -#define CLOCKS_CLK_HSTX_CTRL_KILL_LSB _u(10) -#define CLOCKS_CLK_HSTX_CTRL_KILL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_HSTX_CTRL_AUXSRC -// Description : Selects the auxiliary clock source, will glitch when switching -// 0x0 -> clk_sys -// 0x1 -> clksrc_pll_sys -// 0x2 -> clksrc_pll_usb -// 0x3 -> clksrc_gpin0 -// 0x4 -> clksrc_gpin1 -#define CLOCKS_CLK_HSTX_CTRL_AUXSRC_RESET _u(0x0) -#define CLOCKS_CLK_HSTX_CTRL_AUXSRC_BITS _u(0x000000e0) -#define CLOCKS_CLK_HSTX_CTRL_AUXSRC_MSB _u(7) -#define CLOCKS_CLK_HSTX_CTRL_AUXSRC_LSB _u(5) -#define CLOCKS_CLK_HSTX_CTRL_AUXSRC_ACCESS "RW" -#define CLOCKS_CLK_HSTX_CTRL_AUXSRC_VALUE_CLK_SYS _u(0x0) -#define CLOCKS_CLK_HSTX_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS _u(0x1) -#define CLOCKS_CLK_HSTX_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB _u(0x2) -#define CLOCKS_CLK_HSTX_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 _u(0x3) -#define CLOCKS_CLK_HSTX_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 _u(0x4) -// ============================================================================= -// Register : CLOCKS_CLK_HSTX_DIV -#define CLOCKS_CLK_HSTX_DIV_OFFSET _u(0x00000058) -#define CLOCKS_CLK_HSTX_DIV_BITS _u(0x00030000) -#define CLOCKS_CLK_HSTX_DIV_RESET _u(0x00010000) -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_HSTX_DIV_INT -// Description : Integer part of clock divisor, 0 -> max+1, can be changed on- -// the-fly -#define CLOCKS_CLK_HSTX_DIV_INT_RESET _u(0x1) -#define CLOCKS_CLK_HSTX_DIV_INT_BITS _u(0x00030000) -#define CLOCKS_CLK_HSTX_DIV_INT_MSB _u(17) -#define CLOCKS_CLK_HSTX_DIV_INT_LSB _u(16) -#define CLOCKS_CLK_HSTX_DIV_INT_ACCESS "RW" -// ============================================================================= -// Register : CLOCKS_CLK_HSTX_SELECTED -// Description : Indicates which src is currently selected (one-hot) -// This slice does not have a glitchless mux (only the AUX_SRC -// field is present, not SRC) so this register is hardwired to -// 0x1. -#define CLOCKS_CLK_HSTX_SELECTED_OFFSET _u(0x0000005c) -#define CLOCKS_CLK_HSTX_SELECTED_BITS _u(0x00000001) -#define CLOCKS_CLK_HSTX_SELECTED_RESET _u(0x00000001) -#define CLOCKS_CLK_HSTX_SELECTED_MSB _u(0) -#define CLOCKS_CLK_HSTX_SELECTED_LSB _u(0) -#define CLOCKS_CLK_HSTX_SELECTED_ACCESS "RO" -// ============================================================================= -// Register : CLOCKS_CLK_USB_CTRL -// Description : Clock control, can be changed on-the-fly (except for auxsrc) -#define CLOCKS_CLK_USB_CTRL_OFFSET _u(0x00000060) -#define CLOCKS_CLK_USB_CTRL_BITS _u(0x10130ce0) -#define CLOCKS_CLK_USB_CTRL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_USB_CTRL_ENABLED -// Description : clock generator is enabled -#define CLOCKS_CLK_USB_CTRL_ENABLED_RESET _u(0x0) -#define CLOCKS_CLK_USB_CTRL_ENABLED_BITS _u(0x10000000) -#define CLOCKS_CLK_USB_CTRL_ENABLED_MSB _u(28) -#define CLOCKS_CLK_USB_CTRL_ENABLED_LSB _u(28) -#define CLOCKS_CLK_USB_CTRL_ENABLED_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_USB_CTRL_NUDGE -// Description : An edge on this signal shifts the phase of the output by 1 -// cycle of the input clock -// This can be done at any time -#define CLOCKS_CLK_USB_CTRL_NUDGE_RESET _u(0x0) -#define CLOCKS_CLK_USB_CTRL_NUDGE_BITS _u(0x00100000) -#define CLOCKS_CLK_USB_CTRL_NUDGE_MSB _u(20) -#define CLOCKS_CLK_USB_CTRL_NUDGE_LSB _u(20) -#define CLOCKS_CLK_USB_CTRL_NUDGE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_USB_CTRL_PHASE -// Description : This delays the enable signal by up to 3 cycles of the input -// clock -// This must be set before the clock is enabled to have any effect -#define CLOCKS_CLK_USB_CTRL_PHASE_RESET _u(0x0) -#define CLOCKS_CLK_USB_CTRL_PHASE_BITS _u(0x00030000) -#define CLOCKS_CLK_USB_CTRL_PHASE_MSB _u(17) -#define CLOCKS_CLK_USB_CTRL_PHASE_LSB _u(16) -#define CLOCKS_CLK_USB_CTRL_PHASE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_USB_CTRL_ENABLE -// Description : Starts and stops the clock generator cleanly -#define CLOCKS_CLK_USB_CTRL_ENABLE_RESET _u(0x0) -#define CLOCKS_CLK_USB_CTRL_ENABLE_BITS _u(0x00000800) -#define CLOCKS_CLK_USB_CTRL_ENABLE_MSB _u(11) -#define CLOCKS_CLK_USB_CTRL_ENABLE_LSB _u(11) -#define CLOCKS_CLK_USB_CTRL_ENABLE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_USB_CTRL_KILL -// Description : Asynchronously kills the clock generator, enable must be set -// low before deasserting kill -#define CLOCKS_CLK_USB_CTRL_KILL_RESET _u(0x0) -#define CLOCKS_CLK_USB_CTRL_KILL_BITS _u(0x00000400) -#define CLOCKS_CLK_USB_CTRL_KILL_MSB _u(10) -#define CLOCKS_CLK_USB_CTRL_KILL_LSB _u(10) -#define CLOCKS_CLK_USB_CTRL_KILL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_USB_CTRL_AUXSRC -// Description : Selects the auxiliary clock source, will glitch when switching -// 0x0 -> clksrc_pll_usb -// 0x1 -> clksrc_pll_sys -// 0x2 -> rosc_clksrc_ph -// 0x3 -> xosc_clksrc -// 0x4 -> clksrc_gpin0 -// 0x5 -> clksrc_gpin1 -#define CLOCKS_CLK_USB_CTRL_AUXSRC_RESET _u(0x0) -#define CLOCKS_CLK_USB_CTRL_AUXSRC_BITS _u(0x000000e0) -#define CLOCKS_CLK_USB_CTRL_AUXSRC_MSB _u(7) -#define CLOCKS_CLK_USB_CTRL_AUXSRC_LSB _u(5) -#define CLOCKS_CLK_USB_CTRL_AUXSRC_ACCESS "RW" -#define CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB _u(0x0) -#define CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS _u(0x1) -#define CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH _u(0x2) -#define CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_XOSC_CLKSRC _u(0x3) -#define CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 _u(0x4) -#define CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 _u(0x5) -// ============================================================================= -// Register : CLOCKS_CLK_USB_DIV -#define CLOCKS_CLK_USB_DIV_OFFSET _u(0x00000064) -#define CLOCKS_CLK_USB_DIV_BITS _u(0x000f0000) -#define CLOCKS_CLK_USB_DIV_RESET _u(0x00010000) -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_USB_DIV_INT -// Description : Integer part of clock divisor, 0 -> max+1, can be changed on- -// the-fly -#define CLOCKS_CLK_USB_DIV_INT_RESET _u(0x1) -#define CLOCKS_CLK_USB_DIV_INT_BITS _u(0x000f0000) -#define CLOCKS_CLK_USB_DIV_INT_MSB _u(19) -#define CLOCKS_CLK_USB_DIV_INT_LSB _u(16) -#define CLOCKS_CLK_USB_DIV_INT_ACCESS "RW" -// ============================================================================= -// Register : CLOCKS_CLK_USB_SELECTED -// Description : Indicates which src is currently selected (one-hot) -// This slice does not have a glitchless mux (only the AUX_SRC -// field is present, not SRC) so this register is hardwired to -// 0x1. -#define CLOCKS_CLK_USB_SELECTED_OFFSET _u(0x00000068) -#define CLOCKS_CLK_USB_SELECTED_BITS _u(0x00000001) -#define CLOCKS_CLK_USB_SELECTED_RESET _u(0x00000001) -#define CLOCKS_CLK_USB_SELECTED_MSB _u(0) -#define CLOCKS_CLK_USB_SELECTED_LSB _u(0) -#define CLOCKS_CLK_USB_SELECTED_ACCESS "RO" -// ============================================================================= -// Register : CLOCKS_CLK_ADC_CTRL -// Description : Clock control, can be changed on-the-fly (except for auxsrc) -#define CLOCKS_CLK_ADC_CTRL_OFFSET _u(0x0000006c) -#define CLOCKS_CLK_ADC_CTRL_BITS _u(0x10130ce0) -#define CLOCKS_CLK_ADC_CTRL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_ADC_CTRL_ENABLED -// Description : clock generator is enabled -#define CLOCKS_CLK_ADC_CTRL_ENABLED_RESET _u(0x0) -#define CLOCKS_CLK_ADC_CTRL_ENABLED_BITS _u(0x10000000) -#define CLOCKS_CLK_ADC_CTRL_ENABLED_MSB _u(28) -#define CLOCKS_CLK_ADC_CTRL_ENABLED_LSB _u(28) -#define CLOCKS_CLK_ADC_CTRL_ENABLED_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_ADC_CTRL_NUDGE -// Description : An edge on this signal shifts the phase of the output by 1 -// cycle of the input clock -// This can be done at any time -#define CLOCKS_CLK_ADC_CTRL_NUDGE_RESET _u(0x0) -#define CLOCKS_CLK_ADC_CTRL_NUDGE_BITS _u(0x00100000) -#define CLOCKS_CLK_ADC_CTRL_NUDGE_MSB _u(20) -#define CLOCKS_CLK_ADC_CTRL_NUDGE_LSB _u(20) -#define CLOCKS_CLK_ADC_CTRL_NUDGE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_ADC_CTRL_PHASE -// Description : This delays the enable signal by up to 3 cycles of the input -// clock -// This must be set before the clock is enabled to have any effect -#define CLOCKS_CLK_ADC_CTRL_PHASE_RESET _u(0x0) -#define CLOCKS_CLK_ADC_CTRL_PHASE_BITS _u(0x00030000) -#define CLOCKS_CLK_ADC_CTRL_PHASE_MSB _u(17) -#define CLOCKS_CLK_ADC_CTRL_PHASE_LSB _u(16) -#define CLOCKS_CLK_ADC_CTRL_PHASE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_ADC_CTRL_ENABLE -// Description : Starts and stops the clock generator cleanly -#define CLOCKS_CLK_ADC_CTRL_ENABLE_RESET _u(0x0) -#define CLOCKS_CLK_ADC_CTRL_ENABLE_BITS _u(0x00000800) -#define CLOCKS_CLK_ADC_CTRL_ENABLE_MSB _u(11) -#define CLOCKS_CLK_ADC_CTRL_ENABLE_LSB _u(11) -#define CLOCKS_CLK_ADC_CTRL_ENABLE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_ADC_CTRL_KILL -// Description : Asynchronously kills the clock generator, enable must be set -// low before deasserting kill -#define CLOCKS_CLK_ADC_CTRL_KILL_RESET _u(0x0) -#define CLOCKS_CLK_ADC_CTRL_KILL_BITS _u(0x00000400) -#define CLOCKS_CLK_ADC_CTRL_KILL_MSB _u(10) -#define CLOCKS_CLK_ADC_CTRL_KILL_LSB _u(10) -#define CLOCKS_CLK_ADC_CTRL_KILL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_ADC_CTRL_AUXSRC -// Description : Selects the auxiliary clock source, will glitch when switching -// 0x0 -> clksrc_pll_usb -// 0x1 -> clksrc_pll_sys -// 0x2 -> rosc_clksrc_ph -// 0x3 -> xosc_clksrc -// 0x4 -> clksrc_gpin0 -// 0x5 -> clksrc_gpin1 -#define CLOCKS_CLK_ADC_CTRL_AUXSRC_RESET _u(0x0) -#define CLOCKS_CLK_ADC_CTRL_AUXSRC_BITS _u(0x000000e0) -#define CLOCKS_CLK_ADC_CTRL_AUXSRC_MSB _u(7) -#define CLOCKS_CLK_ADC_CTRL_AUXSRC_LSB _u(5) -#define CLOCKS_CLK_ADC_CTRL_AUXSRC_ACCESS "RW" -#define CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB _u(0x0) -#define CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS _u(0x1) -#define CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH _u(0x2) -#define CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_XOSC_CLKSRC _u(0x3) -#define CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 _u(0x4) -#define CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 _u(0x5) -// ============================================================================= -// Register : CLOCKS_CLK_ADC_DIV -#define CLOCKS_CLK_ADC_DIV_OFFSET _u(0x00000070) -#define CLOCKS_CLK_ADC_DIV_BITS _u(0x000f0000) -#define CLOCKS_CLK_ADC_DIV_RESET _u(0x00010000) -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_ADC_DIV_INT -// Description : Integer part of clock divisor, 0 -> max+1, can be changed on- -// the-fly -#define CLOCKS_CLK_ADC_DIV_INT_RESET _u(0x1) -#define CLOCKS_CLK_ADC_DIV_INT_BITS _u(0x000f0000) -#define CLOCKS_CLK_ADC_DIV_INT_MSB _u(19) -#define CLOCKS_CLK_ADC_DIV_INT_LSB _u(16) -#define CLOCKS_CLK_ADC_DIV_INT_ACCESS "RW" -// ============================================================================= -// Register : CLOCKS_CLK_ADC_SELECTED -// Description : Indicates which src is currently selected (one-hot) -// This slice does not have a glitchless mux (only the AUX_SRC -// field is present, not SRC) so this register is hardwired to -// 0x1. -#define CLOCKS_CLK_ADC_SELECTED_OFFSET _u(0x00000074) -#define CLOCKS_CLK_ADC_SELECTED_BITS _u(0x00000001) -#define CLOCKS_CLK_ADC_SELECTED_RESET _u(0x00000001) -#define CLOCKS_CLK_ADC_SELECTED_MSB _u(0) -#define CLOCKS_CLK_ADC_SELECTED_LSB _u(0) -#define CLOCKS_CLK_ADC_SELECTED_ACCESS "RO" -// ============================================================================= -// Register : CLOCKS_DFTCLK_XOSC_CTRL -#define CLOCKS_DFTCLK_XOSC_CTRL_OFFSET _u(0x00000078) -#define CLOCKS_DFTCLK_XOSC_CTRL_BITS _u(0x00000003) -#define CLOCKS_DFTCLK_XOSC_CTRL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : CLOCKS_DFTCLK_XOSC_CTRL_SRC -// 0x0 -> NULL -// 0x1 -> clksrc_pll_usb_primary -// 0x2 -> clksrc_gpin0 -#define CLOCKS_DFTCLK_XOSC_CTRL_SRC_RESET _u(0x0) -#define CLOCKS_DFTCLK_XOSC_CTRL_SRC_BITS _u(0x00000003) -#define CLOCKS_DFTCLK_XOSC_CTRL_SRC_MSB _u(1) -#define CLOCKS_DFTCLK_XOSC_CTRL_SRC_LSB _u(0) -#define CLOCKS_DFTCLK_XOSC_CTRL_SRC_ACCESS "RW" -#define CLOCKS_DFTCLK_XOSC_CTRL_SRC_VALUE_NULL _u(0x0) -#define CLOCKS_DFTCLK_XOSC_CTRL_SRC_VALUE_CLKSRC_PLL_USB_PRIMARY _u(0x1) -#define CLOCKS_DFTCLK_XOSC_CTRL_SRC_VALUE_CLKSRC_GPIN0 _u(0x2) -// ============================================================================= -// Register : CLOCKS_DFTCLK_ROSC_CTRL -#define CLOCKS_DFTCLK_ROSC_CTRL_OFFSET _u(0x0000007c) -#define CLOCKS_DFTCLK_ROSC_CTRL_BITS _u(0x00000003) -#define CLOCKS_DFTCLK_ROSC_CTRL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : CLOCKS_DFTCLK_ROSC_CTRL_SRC -// 0x0 -> NULL -// 0x1 -> clksrc_pll_sys_primary_rosc -// 0x2 -> clksrc_gpin1 -#define CLOCKS_DFTCLK_ROSC_CTRL_SRC_RESET _u(0x0) -#define CLOCKS_DFTCLK_ROSC_CTRL_SRC_BITS _u(0x00000003) -#define CLOCKS_DFTCLK_ROSC_CTRL_SRC_MSB _u(1) -#define CLOCKS_DFTCLK_ROSC_CTRL_SRC_LSB _u(0) -#define CLOCKS_DFTCLK_ROSC_CTRL_SRC_ACCESS "RW" -#define CLOCKS_DFTCLK_ROSC_CTRL_SRC_VALUE_NULL _u(0x0) -#define CLOCKS_DFTCLK_ROSC_CTRL_SRC_VALUE_CLKSRC_PLL_SYS_PRIMARY_ROSC _u(0x1) -#define CLOCKS_DFTCLK_ROSC_CTRL_SRC_VALUE_CLKSRC_GPIN1 _u(0x2) -// ============================================================================= -// Register : CLOCKS_DFTCLK_LPOSC_CTRL -#define CLOCKS_DFTCLK_LPOSC_CTRL_OFFSET _u(0x00000080) -#define CLOCKS_DFTCLK_LPOSC_CTRL_BITS _u(0x00000003) -#define CLOCKS_DFTCLK_LPOSC_CTRL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : CLOCKS_DFTCLK_LPOSC_CTRL_SRC -// 0x0 -> NULL -// 0x1 -> clksrc_pll_usb_primary_lposc -// 0x2 -> clksrc_gpin1 -#define CLOCKS_DFTCLK_LPOSC_CTRL_SRC_RESET _u(0x0) -#define CLOCKS_DFTCLK_LPOSC_CTRL_SRC_BITS _u(0x00000003) -#define CLOCKS_DFTCLK_LPOSC_CTRL_SRC_MSB _u(1) -#define CLOCKS_DFTCLK_LPOSC_CTRL_SRC_LSB _u(0) -#define CLOCKS_DFTCLK_LPOSC_CTRL_SRC_ACCESS "RW" -#define CLOCKS_DFTCLK_LPOSC_CTRL_SRC_VALUE_NULL _u(0x0) -#define CLOCKS_DFTCLK_LPOSC_CTRL_SRC_VALUE_CLKSRC_PLL_USB_PRIMARY_LPOSC _u(0x1) -#define CLOCKS_DFTCLK_LPOSC_CTRL_SRC_VALUE_CLKSRC_GPIN1 _u(0x2) -// ============================================================================= -// Register : CLOCKS_CLK_SYS_RESUS_CTRL -#define CLOCKS_CLK_SYS_RESUS_CTRL_OFFSET _u(0x00000084) -#define CLOCKS_CLK_SYS_RESUS_CTRL_BITS _u(0x000111ff) -#define CLOCKS_CLK_SYS_RESUS_CTRL_RESET _u(0x000000ff) -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_SYS_RESUS_CTRL_CLEAR -// Description : For clearing the resus after the fault that triggered it has -// been corrected -#define CLOCKS_CLK_SYS_RESUS_CTRL_CLEAR_RESET _u(0x0) -#define CLOCKS_CLK_SYS_RESUS_CTRL_CLEAR_BITS _u(0x00010000) -#define CLOCKS_CLK_SYS_RESUS_CTRL_CLEAR_MSB _u(16) -#define CLOCKS_CLK_SYS_RESUS_CTRL_CLEAR_LSB _u(16) -#define CLOCKS_CLK_SYS_RESUS_CTRL_CLEAR_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_SYS_RESUS_CTRL_FRCE -// Description : Force a resus, for test purposes only -#define CLOCKS_CLK_SYS_RESUS_CTRL_FRCE_RESET _u(0x0) -#define CLOCKS_CLK_SYS_RESUS_CTRL_FRCE_BITS _u(0x00001000) -#define CLOCKS_CLK_SYS_RESUS_CTRL_FRCE_MSB _u(12) -#define CLOCKS_CLK_SYS_RESUS_CTRL_FRCE_LSB _u(12) -#define CLOCKS_CLK_SYS_RESUS_CTRL_FRCE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_SYS_RESUS_CTRL_ENABLE -// Description : Enable resus -#define CLOCKS_CLK_SYS_RESUS_CTRL_ENABLE_RESET _u(0x0) -#define CLOCKS_CLK_SYS_RESUS_CTRL_ENABLE_BITS _u(0x00000100) -#define CLOCKS_CLK_SYS_RESUS_CTRL_ENABLE_MSB _u(8) -#define CLOCKS_CLK_SYS_RESUS_CTRL_ENABLE_LSB _u(8) -#define CLOCKS_CLK_SYS_RESUS_CTRL_ENABLE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_SYS_RESUS_CTRL_TIMEOUT -// Description : This is expressed as a number of clk_ref cycles -// and must be >= 2x clk_ref_freq/min_clk_tst_freq -#define CLOCKS_CLK_SYS_RESUS_CTRL_TIMEOUT_RESET _u(0xff) -#define CLOCKS_CLK_SYS_RESUS_CTRL_TIMEOUT_BITS _u(0x000000ff) -#define CLOCKS_CLK_SYS_RESUS_CTRL_TIMEOUT_MSB _u(7) -#define CLOCKS_CLK_SYS_RESUS_CTRL_TIMEOUT_LSB _u(0) -#define CLOCKS_CLK_SYS_RESUS_CTRL_TIMEOUT_ACCESS "RW" -// ============================================================================= -// Register : CLOCKS_CLK_SYS_RESUS_STATUS -#define CLOCKS_CLK_SYS_RESUS_STATUS_OFFSET _u(0x00000088) -#define CLOCKS_CLK_SYS_RESUS_STATUS_BITS _u(0x00000001) -#define CLOCKS_CLK_SYS_RESUS_STATUS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : CLOCKS_CLK_SYS_RESUS_STATUS_RESUSSED -// Description : Clock has been resuscitated, correct the error then send -// ctrl_clear=1 -#define CLOCKS_CLK_SYS_RESUS_STATUS_RESUSSED_RESET _u(0x0) -#define CLOCKS_CLK_SYS_RESUS_STATUS_RESUSSED_BITS _u(0x00000001) -#define CLOCKS_CLK_SYS_RESUS_STATUS_RESUSSED_MSB _u(0) -#define CLOCKS_CLK_SYS_RESUS_STATUS_RESUSSED_LSB _u(0) -#define CLOCKS_CLK_SYS_RESUS_STATUS_RESUSSED_ACCESS "RO" -// ============================================================================= -// Register : CLOCKS_FC0_REF_KHZ -// Description : Reference clock frequency in kHz -#define CLOCKS_FC0_REF_KHZ_OFFSET _u(0x0000008c) -#define CLOCKS_FC0_REF_KHZ_BITS _u(0x000fffff) -#define CLOCKS_FC0_REF_KHZ_RESET _u(0x00000000) -#define CLOCKS_FC0_REF_KHZ_MSB _u(19) -#define CLOCKS_FC0_REF_KHZ_LSB _u(0) -#define CLOCKS_FC0_REF_KHZ_ACCESS "RW" -// ============================================================================= -// Register : CLOCKS_FC0_MIN_KHZ -// Description : Minimum pass frequency in kHz. This is optional. Set to 0 if -// you are not using the pass/fail flags -#define CLOCKS_FC0_MIN_KHZ_OFFSET _u(0x00000090) -#define CLOCKS_FC0_MIN_KHZ_BITS _u(0x01ffffff) -#define CLOCKS_FC0_MIN_KHZ_RESET _u(0x00000000) -#define CLOCKS_FC0_MIN_KHZ_MSB _u(24) -#define CLOCKS_FC0_MIN_KHZ_LSB _u(0) -#define CLOCKS_FC0_MIN_KHZ_ACCESS "RW" -// ============================================================================= -// Register : CLOCKS_FC0_MAX_KHZ -// Description : Maximum pass frequency in kHz. This is optional. Set to -// 0x1ffffff if you are not using the pass/fail flags -#define CLOCKS_FC0_MAX_KHZ_OFFSET _u(0x00000094) -#define CLOCKS_FC0_MAX_KHZ_BITS _u(0x01ffffff) -#define CLOCKS_FC0_MAX_KHZ_RESET _u(0x01ffffff) -#define CLOCKS_FC0_MAX_KHZ_MSB _u(24) -#define CLOCKS_FC0_MAX_KHZ_LSB _u(0) -#define CLOCKS_FC0_MAX_KHZ_ACCESS "RW" -// ============================================================================= -// Register : CLOCKS_FC0_DELAY -// Description : Delays the start of frequency counting to allow the mux to -// settle -// Delay is measured in multiples of the reference clock period -#define CLOCKS_FC0_DELAY_OFFSET _u(0x00000098) -#define CLOCKS_FC0_DELAY_BITS _u(0x00000007) -#define CLOCKS_FC0_DELAY_RESET _u(0x00000001) -#define CLOCKS_FC0_DELAY_MSB _u(2) -#define CLOCKS_FC0_DELAY_LSB _u(0) -#define CLOCKS_FC0_DELAY_ACCESS "RW" -// ============================================================================= -// Register : CLOCKS_FC0_INTERVAL -// Description : The test interval is 0.98us * 2**interval, but let's call it -// 1us * 2**interval -// The default gives a test interval of 250us -#define CLOCKS_FC0_INTERVAL_OFFSET _u(0x0000009c) -#define CLOCKS_FC0_INTERVAL_BITS _u(0x0000000f) -#define CLOCKS_FC0_INTERVAL_RESET _u(0x00000008) -#define CLOCKS_FC0_INTERVAL_MSB _u(3) -#define CLOCKS_FC0_INTERVAL_LSB _u(0) -#define CLOCKS_FC0_INTERVAL_ACCESS "RW" -// ============================================================================= -// Register : CLOCKS_FC0_SRC -// Description : Clock sent to frequency counter, set to 0 when not required -// Writing to this register initiates the frequency count -// 0x00 -> NULL -// 0x01 -> pll_sys_clksrc_primary -// 0x02 -> pll_usb_clksrc_primary -// 0x03 -> rosc_clksrc -// 0x04 -> rosc_clksrc_ph -// 0x05 -> xosc_clksrc -// 0x06 -> clksrc_gpin0 -// 0x07 -> clksrc_gpin1 -// 0x08 -> clk_ref -// 0x09 -> clk_sys -// 0x0a -> clk_peri -// 0x0b -> clk_usb -// 0x0c -> clk_adc -// 0x0d -> clk_hstx -// 0x0e -> lposc_clksrc -// 0x0f -> otp_clk2fc -// 0x10 -> pll_usb_clksrc_primary_dft -#define CLOCKS_FC0_SRC_OFFSET _u(0x000000a0) -#define CLOCKS_FC0_SRC_BITS _u(0x000000ff) -#define CLOCKS_FC0_SRC_RESET _u(0x00000000) -#define CLOCKS_FC0_SRC_MSB _u(7) -#define CLOCKS_FC0_SRC_LSB _u(0) -#define CLOCKS_FC0_SRC_ACCESS "RW" -#define CLOCKS_FC0_SRC_VALUE_NULL _u(0x00) -#define CLOCKS_FC0_SRC_VALUE_PLL_SYS_CLKSRC_PRIMARY _u(0x01) -#define CLOCKS_FC0_SRC_VALUE_PLL_USB_CLKSRC_PRIMARY _u(0x02) -#define CLOCKS_FC0_SRC_VALUE_ROSC_CLKSRC _u(0x03) -#define CLOCKS_FC0_SRC_VALUE_ROSC_CLKSRC_PH _u(0x04) -#define CLOCKS_FC0_SRC_VALUE_XOSC_CLKSRC _u(0x05) -#define CLOCKS_FC0_SRC_VALUE_CLKSRC_GPIN0 _u(0x06) -#define CLOCKS_FC0_SRC_VALUE_CLKSRC_GPIN1 _u(0x07) -#define CLOCKS_FC0_SRC_VALUE_CLK_REF _u(0x08) -#define CLOCKS_FC0_SRC_VALUE_CLK_SYS _u(0x09) -#define CLOCKS_FC0_SRC_VALUE_CLK_PERI _u(0x0a) -#define CLOCKS_FC0_SRC_VALUE_CLK_USB _u(0x0b) -#define CLOCKS_FC0_SRC_VALUE_CLK_ADC _u(0x0c) -#define CLOCKS_FC0_SRC_VALUE_CLK_HSTX _u(0x0d) -#define CLOCKS_FC0_SRC_VALUE_LPOSC_CLKSRC _u(0x0e) -#define CLOCKS_FC0_SRC_VALUE_OTP_CLK2FC _u(0x0f) -#define CLOCKS_FC0_SRC_VALUE_PLL_USB_CLKSRC_PRIMARY_DFT _u(0x10) -// ============================================================================= -// Register : CLOCKS_FC0_STATUS -// Description : Frequency counter status -#define CLOCKS_FC0_STATUS_OFFSET _u(0x000000a4) -#define CLOCKS_FC0_STATUS_BITS _u(0x11111111) -#define CLOCKS_FC0_STATUS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : CLOCKS_FC0_STATUS_DIED -// Description : Test clock stopped during test -#define CLOCKS_FC0_STATUS_DIED_RESET _u(0x0) -#define CLOCKS_FC0_STATUS_DIED_BITS _u(0x10000000) -#define CLOCKS_FC0_STATUS_DIED_MSB _u(28) -#define CLOCKS_FC0_STATUS_DIED_LSB _u(28) -#define CLOCKS_FC0_STATUS_DIED_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_FC0_STATUS_FAST -// Description : Test clock faster than expected, only valid when status_done=1 -#define CLOCKS_FC0_STATUS_FAST_RESET _u(0x0) -#define CLOCKS_FC0_STATUS_FAST_BITS _u(0x01000000) -#define CLOCKS_FC0_STATUS_FAST_MSB _u(24) -#define CLOCKS_FC0_STATUS_FAST_LSB _u(24) -#define CLOCKS_FC0_STATUS_FAST_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_FC0_STATUS_SLOW -// Description : Test clock slower than expected, only valid when status_done=1 -#define CLOCKS_FC0_STATUS_SLOW_RESET _u(0x0) -#define CLOCKS_FC0_STATUS_SLOW_BITS _u(0x00100000) -#define CLOCKS_FC0_STATUS_SLOW_MSB _u(20) -#define CLOCKS_FC0_STATUS_SLOW_LSB _u(20) -#define CLOCKS_FC0_STATUS_SLOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_FC0_STATUS_FAIL -// Description : Test failed -#define CLOCKS_FC0_STATUS_FAIL_RESET _u(0x0) -#define CLOCKS_FC0_STATUS_FAIL_BITS _u(0x00010000) -#define CLOCKS_FC0_STATUS_FAIL_MSB _u(16) -#define CLOCKS_FC0_STATUS_FAIL_LSB _u(16) -#define CLOCKS_FC0_STATUS_FAIL_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_FC0_STATUS_WAITING -// Description : Waiting for test clock to start -#define CLOCKS_FC0_STATUS_WAITING_RESET _u(0x0) -#define CLOCKS_FC0_STATUS_WAITING_BITS _u(0x00001000) -#define CLOCKS_FC0_STATUS_WAITING_MSB _u(12) -#define CLOCKS_FC0_STATUS_WAITING_LSB _u(12) -#define CLOCKS_FC0_STATUS_WAITING_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_FC0_STATUS_RUNNING -// Description : Test running -#define CLOCKS_FC0_STATUS_RUNNING_RESET _u(0x0) -#define CLOCKS_FC0_STATUS_RUNNING_BITS _u(0x00000100) -#define CLOCKS_FC0_STATUS_RUNNING_MSB _u(8) -#define CLOCKS_FC0_STATUS_RUNNING_LSB _u(8) -#define CLOCKS_FC0_STATUS_RUNNING_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_FC0_STATUS_DONE -// Description : Test complete -#define CLOCKS_FC0_STATUS_DONE_RESET _u(0x0) -#define CLOCKS_FC0_STATUS_DONE_BITS _u(0x00000010) -#define CLOCKS_FC0_STATUS_DONE_MSB _u(4) -#define CLOCKS_FC0_STATUS_DONE_LSB _u(4) -#define CLOCKS_FC0_STATUS_DONE_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_FC0_STATUS_PASS -// Description : Test passed -#define CLOCKS_FC0_STATUS_PASS_RESET _u(0x0) -#define CLOCKS_FC0_STATUS_PASS_BITS _u(0x00000001) -#define CLOCKS_FC0_STATUS_PASS_MSB _u(0) -#define CLOCKS_FC0_STATUS_PASS_LSB _u(0) -#define CLOCKS_FC0_STATUS_PASS_ACCESS "RO" -// ============================================================================= -// Register : CLOCKS_FC0_RESULT -// Description : Result of frequency measurement, only valid when status_done=1 -#define CLOCKS_FC0_RESULT_OFFSET _u(0x000000a8) -#define CLOCKS_FC0_RESULT_BITS _u(0x3fffffff) -#define CLOCKS_FC0_RESULT_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : CLOCKS_FC0_RESULT_KHZ -#define CLOCKS_FC0_RESULT_KHZ_RESET _u(0x0000000) -#define CLOCKS_FC0_RESULT_KHZ_BITS _u(0x3fffffe0) -#define CLOCKS_FC0_RESULT_KHZ_MSB _u(29) -#define CLOCKS_FC0_RESULT_KHZ_LSB _u(5) -#define CLOCKS_FC0_RESULT_KHZ_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_FC0_RESULT_FRAC -#define CLOCKS_FC0_RESULT_FRAC_RESET _u(0x00) -#define CLOCKS_FC0_RESULT_FRAC_BITS _u(0x0000001f) -#define CLOCKS_FC0_RESULT_FRAC_MSB _u(4) -#define CLOCKS_FC0_RESULT_FRAC_LSB _u(0) -#define CLOCKS_FC0_RESULT_FRAC_ACCESS "RO" -// ============================================================================= -// Register : CLOCKS_WAKE_EN0 -// Description : enable clock in wake mode -#define CLOCKS_WAKE_EN0_OFFSET _u(0x000000ac) -#define CLOCKS_WAKE_EN0_BITS _u(0xffffffff) -#define CLOCKS_WAKE_EN0_RESET _u(0xffffffff) -// ----------------------------------------------------------------------------- -// Field : CLOCKS_WAKE_EN0_CLK_SYS_SIO -#define CLOCKS_WAKE_EN0_CLK_SYS_SIO_RESET _u(0x1) -#define CLOCKS_WAKE_EN0_CLK_SYS_SIO_BITS _u(0x80000000) -#define CLOCKS_WAKE_EN0_CLK_SYS_SIO_MSB _u(31) -#define CLOCKS_WAKE_EN0_CLK_SYS_SIO_LSB _u(31) -#define CLOCKS_WAKE_EN0_CLK_SYS_SIO_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_WAKE_EN0_CLK_SYS_SHA256 -#define CLOCKS_WAKE_EN0_CLK_SYS_SHA256_RESET _u(0x1) -#define CLOCKS_WAKE_EN0_CLK_SYS_SHA256_BITS _u(0x40000000) -#define CLOCKS_WAKE_EN0_CLK_SYS_SHA256_MSB _u(30) -#define CLOCKS_WAKE_EN0_CLK_SYS_SHA256_LSB _u(30) -#define CLOCKS_WAKE_EN0_CLK_SYS_SHA256_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_WAKE_EN0_CLK_SYS_PSM -#define CLOCKS_WAKE_EN0_CLK_SYS_PSM_RESET _u(0x1) -#define CLOCKS_WAKE_EN0_CLK_SYS_PSM_BITS _u(0x20000000) -#define CLOCKS_WAKE_EN0_CLK_SYS_PSM_MSB _u(29) -#define CLOCKS_WAKE_EN0_CLK_SYS_PSM_LSB _u(29) -#define CLOCKS_WAKE_EN0_CLK_SYS_PSM_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_WAKE_EN0_CLK_SYS_ROSC -#define CLOCKS_WAKE_EN0_CLK_SYS_ROSC_RESET _u(0x1) -#define CLOCKS_WAKE_EN0_CLK_SYS_ROSC_BITS _u(0x10000000) -#define CLOCKS_WAKE_EN0_CLK_SYS_ROSC_MSB _u(28) -#define CLOCKS_WAKE_EN0_CLK_SYS_ROSC_LSB _u(28) -#define CLOCKS_WAKE_EN0_CLK_SYS_ROSC_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_WAKE_EN0_CLK_SYS_ROM -#define CLOCKS_WAKE_EN0_CLK_SYS_ROM_RESET _u(0x1) -#define CLOCKS_WAKE_EN0_CLK_SYS_ROM_BITS _u(0x08000000) -#define CLOCKS_WAKE_EN0_CLK_SYS_ROM_MSB _u(27) -#define CLOCKS_WAKE_EN0_CLK_SYS_ROM_LSB _u(27) -#define CLOCKS_WAKE_EN0_CLK_SYS_ROM_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_WAKE_EN0_CLK_SYS_RESETS -#define CLOCKS_WAKE_EN0_CLK_SYS_RESETS_RESET _u(0x1) -#define CLOCKS_WAKE_EN0_CLK_SYS_RESETS_BITS _u(0x04000000) -#define CLOCKS_WAKE_EN0_CLK_SYS_RESETS_MSB _u(26) -#define CLOCKS_WAKE_EN0_CLK_SYS_RESETS_LSB _u(26) -#define CLOCKS_WAKE_EN0_CLK_SYS_RESETS_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_WAKE_EN0_CLK_SYS_PWM -#define CLOCKS_WAKE_EN0_CLK_SYS_PWM_RESET _u(0x1) -#define CLOCKS_WAKE_EN0_CLK_SYS_PWM_BITS _u(0x02000000) -#define CLOCKS_WAKE_EN0_CLK_SYS_PWM_MSB _u(25) -#define CLOCKS_WAKE_EN0_CLK_SYS_PWM_LSB _u(25) -#define CLOCKS_WAKE_EN0_CLK_SYS_PWM_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_WAKE_EN0_CLK_SYS_POWMAN -#define CLOCKS_WAKE_EN0_CLK_SYS_POWMAN_RESET _u(0x1) -#define CLOCKS_WAKE_EN0_CLK_SYS_POWMAN_BITS _u(0x01000000) -#define CLOCKS_WAKE_EN0_CLK_SYS_POWMAN_MSB _u(24) -#define CLOCKS_WAKE_EN0_CLK_SYS_POWMAN_LSB _u(24) -#define CLOCKS_WAKE_EN0_CLK_SYS_POWMAN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_WAKE_EN0_CLK_REF_POWMAN -#define CLOCKS_WAKE_EN0_CLK_REF_POWMAN_RESET _u(0x1) -#define CLOCKS_WAKE_EN0_CLK_REF_POWMAN_BITS _u(0x00800000) -#define CLOCKS_WAKE_EN0_CLK_REF_POWMAN_MSB _u(23) -#define CLOCKS_WAKE_EN0_CLK_REF_POWMAN_LSB _u(23) -#define CLOCKS_WAKE_EN0_CLK_REF_POWMAN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_WAKE_EN0_CLK_SYS_PLL_USB -#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_USB_RESET _u(0x1) -#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_USB_BITS _u(0x00400000) -#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_USB_MSB _u(22) -#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_USB_LSB _u(22) -#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_USB_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_WAKE_EN0_CLK_SYS_PLL_SYS -#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_SYS_RESET _u(0x1) -#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_SYS_BITS _u(0x00200000) -#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_SYS_MSB _u(21) -#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_SYS_LSB _u(21) -#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_SYS_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_WAKE_EN0_CLK_SYS_PIO2 -#define CLOCKS_WAKE_EN0_CLK_SYS_PIO2_RESET _u(0x1) -#define CLOCKS_WAKE_EN0_CLK_SYS_PIO2_BITS _u(0x00100000) -#define CLOCKS_WAKE_EN0_CLK_SYS_PIO2_MSB _u(20) -#define CLOCKS_WAKE_EN0_CLK_SYS_PIO2_LSB _u(20) -#define CLOCKS_WAKE_EN0_CLK_SYS_PIO2_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_WAKE_EN0_CLK_SYS_PIO1 -#define CLOCKS_WAKE_EN0_CLK_SYS_PIO1_RESET _u(0x1) -#define CLOCKS_WAKE_EN0_CLK_SYS_PIO1_BITS _u(0x00080000) -#define CLOCKS_WAKE_EN0_CLK_SYS_PIO1_MSB _u(19) -#define CLOCKS_WAKE_EN0_CLK_SYS_PIO1_LSB _u(19) -#define CLOCKS_WAKE_EN0_CLK_SYS_PIO1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_WAKE_EN0_CLK_SYS_PIO0 -#define CLOCKS_WAKE_EN0_CLK_SYS_PIO0_RESET _u(0x1) -#define CLOCKS_WAKE_EN0_CLK_SYS_PIO0_BITS _u(0x00040000) -#define CLOCKS_WAKE_EN0_CLK_SYS_PIO0_MSB _u(18) -#define CLOCKS_WAKE_EN0_CLK_SYS_PIO0_LSB _u(18) -#define CLOCKS_WAKE_EN0_CLK_SYS_PIO0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_WAKE_EN0_CLK_SYS_PADS -#define CLOCKS_WAKE_EN0_CLK_SYS_PADS_RESET _u(0x1) -#define CLOCKS_WAKE_EN0_CLK_SYS_PADS_BITS _u(0x00020000) -#define CLOCKS_WAKE_EN0_CLK_SYS_PADS_MSB _u(17) -#define CLOCKS_WAKE_EN0_CLK_SYS_PADS_LSB _u(17) -#define CLOCKS_WAKE_EN0_CLK_SYS_PADS_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_WAKE_EN0_CLK_SYS_OTP -#define CLOCKS_WAKE_EN0_CLK_SYS_OTP_RESET _u(0x1) -#define CLOCKS_WAKE_EN0_CLK_SYS_OTP_BITS _u(0x00010000) -#define CLOCKS_WAKE_EN0_CLK_SYS_OTP_MSB _u(16) -#define CLOCKS_WAKE_EN0_CLK_SYS_OTP_LSB _u(16) -#define CLOCKS_WAKE_EN0_CLK_SYS_OTP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_WAKE_EN0_CLK_REF_OTP -#define CLOCKS_WAKE_EN0_CLK_REF_OTP_RESET _u(0x1) -#define CLOCKS_WAKE_EN0_CLK_REF_OTP_BITS _u(0x00008000) -#define CLOCKS_WAKE_EN0_CLK_REF_OTP_MSB _u(15) -#define CLOCKS_WAKE_EN0_CLK_REF_OTP_LSB _u(15) -#define CLOCKS_WAKE_EN0_CLK_REF_OTP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_WAKE_EN0_CLK_SYS_JTAG -#define CLOCKS_WAKE_EN0_CLK_SYS_JTAG_RESET _u(0x1) -#define CLOCKS_WAKE_EN0_CLK_SYS_JTAG_BITS _u(0x00004000) -#define CLOCKS_WAKE_EN0_CLK_SYS_JTAG_MSB _u(14) -#define CLOCKS_WAKE_EN0_CLK_SYS_JTAG_LSB _u(14) -#define CLOCKS_WAKE_EN0_CLK_SYS_JTAG_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_WAKE_EN0_CLK_SYS_IO -#define CLOCKS_WAKE_EN0_CLK_SYS_IO_RESET _u(0x1) -#define CLOCKS_WAKE_EN0_CLK_SYS_IO_BITS _u(0x00002000) -#define CLOCKS_WAKE_EN0_CLK_SYS_IO_MSB _u(13) -#define CLOCKS_WAKE_EN0_CLK_SYS_IO_LSB _u(13) -#define CLOCKS_WAKE_EN0_CLK_SYS_IO_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_WAKE_EN0_CLK_SYS_I2C1 -#define CLOCKS_WAKE_EN0_CLK_SYS_I2C1_RESET _u(0x1) -#define CLOCKS_WAKE_EN0_CLK_SYS_I2C1_BITS _u(0x00001000) -#define CLOCKS_WAKE_EN0_CLK_SYS_I2C1_MSB _u(12) -#define CLOCKS_WAKE_EN0_CLK_SYS_I2C1_LSB _u(12) -#define CLOCKS_WAKE_EN0_CLK_SYS_I2C1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_WAKE_EN0_CLK_SYS_I2C0 -#define CLOCKS_WAKE_EN0_CLK_SYS_I2C0_RESET _u(0x1) -#define CLOCKS_WAKE_EN0_CLK_SYS_I2C0_BITS _u(0x00000800) -#define CLOCKS_WAKE_EN0_CLK_SYS_I2C0_MSB _u(11) -#define CLOCKS_WAKE_EN0_CLK_SYS_I2C0_LSB _u(11) -#define CLOCKS_WAKE_EN0_CLK_SYS_I2C0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_WAKE_EN0_CLK_SYS_HSTX -#define CLOCKS_WAKE_EN0_CLK_SYS_HSTX_RESET _u(0x1) -#define CLOCKS_WAKE_EN0_CLK_SYS_HSTX_BITS _u(0x00000400) -#define CLOCKS_WAKE_EN0_CLK_SYS_HSTX_MSB _u(10) -#define CLOCKS_WAKE_EN0_CLK_SYS_HSTX_LSB _u(10) -#define CLOCKS_WAKE_EN0_CLK_SYS_HSTX_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_WAKE_EN0_CLK_HSTX -#define CLOCKS_WAKE_EN0_CLK_HSTX_RESET _u(0x1) -#define CLOCKS_WAKE_EN0_CLK_HSTX_BITS _u(0x00000200) -#define CLOCKS_WAKE_EN0_CLK_HSTX_MSB _u(9) -#define CLOCKS_WAKE_EN0_CLK_HSTX_LSB _u(9) -#define CLOCKS_WAKE_EN0_CLK_HSTX_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_WAKE_EN0_CLK_SYS_GLITCH_DETECTOR -#define CLOCKS_WAKE_EN0_CLK_SYS_GLITCH_DETECTOR_RESET _u(0x1) -#define CLOCKS_WAKE_EN0_CLK_SYS_GLITCH_DETECTOR_BITS _u(0x00000100) -#define CLOCKS_WAKE_EN0_CLK_SYS_GLITCH_DETECTOR_MSB _u(8) -#define CLOCKS_WAKE_EN0_CLK_SYS_GLITCH_DETECTOR_LSB _u(8) -#define CLOCKS_WAKE_EN0_CLK_SYS_GLITCH_DETECTOR_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_WAKE_EN0_CLK_SYS_DMA -#define CLOCKS_WAKE_EN0_CLK_SYS_DMA_RESET _u(0x1) -#define CLOCKS_WAKE_EN0_CLK_SYS_DMA_BITS _u(0x00000080) -#define CLOCKS_WAKE_EN0_CLK_SYS_DMA_MSB _u(7) -#define CLOCKS_WAKE_EN0_CLK_SYS_DMA_LSB _u(7) -#define CLOCKS_WAKE_EN0_CLK_SYS_DMA_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_WAKE_EN0_CLK_SYS_BUSFABRIC -#define CLOCKS_WAKE_EN0_CLK_SYS_BUSFABRIC_RESET _u(0x1) -#define CLOCKS_WAKE_EN0_CLK_SYS_BUSFABRIC_BITS _u(0x00000040) -#define CLOCKS_WAKE_EN0_CLK_SYS_BUSFABRIC_MSB _u(6) -#define CLOCKS_WAKE_EN0_CLK_SYS_BUSFABRIC_LSB _u(6) -#define CLOCKS_WAKE_EN0_CLK_SYS_BUSFABRIC_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_WAKE_EN0_CLK_SYS_BUSCTRL -#define CLOCKS_WAKE_EN0_CLK_SYS_BUSCTRL_RESET _u(0x1) -#define CLOCKS_WAKE_EN0_CLK_SYS_BUSCTRL_BITS _u(0x00000020) -#define CLOCKS_WAKE_EN0_CLK_SYS_BUSCTRL_MSB _u(5) -#define CLOCKS_WAKE_EN0_CLK_SYS_BUSCTRL_LSB _u(5) -#define CLOCKS_WAKE_EN0_CLK_SYS_BUSCTRL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_WAKE_EN0_CLK_SYS_BOOTRAM -#define CLOCKS_WAKE_EN0_CLK_SYS_BOOTRAM_RESET _u(0x1) -#define CLOCKS_WAKE_EN0_CLK_SYS_BOOTRAM_BITS _u(0x00000010) -#define CLOCKS_WAKE_EN0_CLK_SYS_BOOTRAM_MSB _u(4) -#define CLOCKS_WAKE_EN0_CLK_SYS_BOOTRAM_LSB _u(4) -#define CLOCKS_WAKE_EN0_CLK_SYS_BOOTRAM_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_WAKE_EN0_CLK_SYS_ADC -#define CLOCKS_WAKE_EN0_CLK_SYS_ADC_RESET _u(0x1) -#define CLOCKS_WAKE_EN0_CLK_SYS_ADC_BITS _u(0x00000008) -#define CLOCKS_WAKE_EN0_CLK_SYS_ADC_MSB _u(3) -#define CLOCKS_WAKE_EN0_CLK_SYS_ADC_LSB _u(3) -#define CLOCKS_WAKE_EN0_CLK_SYS_ADC_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_WAKE_EN0_CLK_ADC -#define CLOCKS_WAKE_EN0_CLK_ADC_RESET _u(0x1) -#define CLOCKS_WAKE_EN0_CLK_ADC_BITS _u(0x00000004) -#define CLOCKS_WAKE_EN0_CLK_ADC_MSB _u(2) -#define CLOCKS_WAKE_EN0_CLK_ADC_LSB _u(2) -#define CLOCKS_WAKE_EN0_CLK_ADC_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_WAKE_EN0_CLK_SYS_ACCESSCTRL -#define CLOCKS_WAKE_EN0_CLK_SYS_ACCESSCTRL_RESET _u(0x1) -#define CLOCKS_WAKE_EN0_CLK_SYS_ACCESSCTRL_BITS _u(0x00000002) -#define CLOCKS_WAKE_EN0_CLK_SYS_ACCESSCTRL_MSB _u(1) -#define CLOCKS_WAKE_EN0_CLK_SYS_ACCESSCTRL_LSB _u(1) -#define CLOCKS_WAKE_EN0_CLK_SYS_ACCESSCTRL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_WAKE_EN0_CLK_SYS_CLOCKS -#define CLOCKS_WAKE_EN0_CLK_SYS_CLOCKS_RESET _u(0x1) -#define CLOCKS_WAKE_EN0_CLK_SYS_CLOCKS_BITS _u(0x00000001) -#define CLOCKS_WAKE_EN0_CLK_SYS_CLOCKS_MSB _u(0) -#define CLOCKS_WAKE_EN0_CLK_SYS_CLOCKS_LSB _u(0) -#define CLOCKS_WAKE_EN0_CLK_SYS_CLOCKS_ACCESS "RW" -// ============================================================================= -// Register : CLOCKS_WAKE_EN1 -// Description : enable clock in wake mode -#define CLOCKS_WAKE_EN1_OFFSET _u(0x000000b0) -#define CLOCKS_WAKE_EN1_BITS _u(0x7fffffff) -#define CLOCKS_WAKE_EN1_RESET _u(0x7fffffff) -// ----------------------------------------------------------------------------- -// Field : CLOCKS_WAKE_EN1_CLK_SYS_XOSC -#define CLOCKS_WAKE_EN1_CLK_SYS_XOSC_RESET _u(0x1) -#define CLOCKS_WAKE_EN1_CLK_SYS_XOSC_BITS _u(0x40000000) -#define CLOCKS_WAKE_EN1_CLK_SYS_XOSC_MSB _u(30) -#define CLOCKS_WAKE_EN1_CLK_SYS_XOSC_LSB _u(30) -#define CLOCKS_WAKE_EN1_CLK_SYS_XOSC_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_WAKE_EN1_CLK_SYS_XIP -#define CLOCKS_WAKE_EN1_CLK_SYS_XIP_RESET _u(0x1) -#define CLOCKS_WAKE_EN1_CLK_SYS_XIP_BITS _u(0x20000000) -#define CLOCKS_WAKE_EN1_CLK_SYS_XIP_MSB _u(29) -#define CLOCKS_WAKE_EN1_CLK_SYS_XIP_LSB _u(29) -#define CLOCKS_WAKE_EN1_CLK_SYS_XIP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_WAKE_EN1_CLK_SYS_WATCHDOG -#define CLOCKS_WAKE_EN1_CLK_SYS_WATCHDOG_RESET _u(0x1) -#define CLOCKS_WAKE_EN1_CLK_SYS_WATCHDOG_BITS _u(0x10000000) -#define CLOCKS_WAKE_EN1_CLK_SYS_WATCHDOG_MSB _u(28) -#define CLOCKS_WAKE_EN1_CLK_SYS_WATCHDOG_LSB _u(28) -#define CLOCKS_WAKE_EN1_CLK_SYS_WATCHDOG_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_WAKE_EN1_CLK_USB -#define CLOCKS_WAKE_EN1_CLK_USB_RESET _u(0x1) -#define CLOCKS_WAKE_EN1_CLK_USB_BITS _u(0x08000000) -#define CLOCKS_WAKE_EN1_CLK_USB_MSB _u(27) -#define CLOCKS_WAKE_EN1_CLK_USB_LSB _u(27) -#define CLOCKS_WAKE_EN1_CLK_USB_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_WAKE_EN1_CLK_SYS_USBCTRL -#define CLOCKS_WAKE_EN1_CLK_SYS_USBCTRL_RESET _u(0x1) -#define CLOCKS_WAKE_EN1_CLK_SYS_USBCTRL_BITS _u(0x04000000) -#define CLOCKS_WAKE_EN1_CLK_SYS_USBCTRL_MSB _u(26) -#define CLOCKS_WAKE_EN1_CLK_SYS_USBCTRL_LSB _u(26) -#define CLOCKS_WAKE_EN1_CLK_SYS_USBCTRL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_WAKE_EN1_CLK_SYS_UART1 -#define CLOCKS_WAKE_EN1_CLK_SYS_UART1_RESET _u(0x1) -#define CLOCKS_WAKE_EN1_CLK_SYS_UART1_BITS _u(0x02000000) -#define CLOCKS_WAKE_EN1_CLK_SYS_UART1_MSB _u(25) -#define CLOCKS_WAKE_EN1_CLK_SYS_UART1_LSB _u(25) -#define CLOCKS_WAKE_EN1_CLK_SYS_UART1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_WAKE_EN1_CLK_PERI_UART1 -#define CLOCKS_WAKE_EN1_CLK_PERI_UART1_RESET _u(0x1) -#define CLOCKS_WAKE_EN1_CLK_PERI_UART1_BITS _u(0x01000000) -#define CLOCKS_WAKE_EN1_CLK_PERI_UART1_MSB _u(24) -#define CLOCKS_WAKE_EN1_CLK_PERI_UART1_LSB _u(24) -#define CLOCKS_WAKE_EN1_CLK_PERI_UART1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_WAKE_EN1_CLK_SYS_UART0 -#define CLOCKS_WAKE_EN1_CLK_SYS_UART0_RESET _u(0x1) -#define CLOCKS_WAKE_EN1_CLK_SYS_UART0_BITS _u(0x00800000) -#define CLOCKS_WAKE_EN1_CLK_SYS_UART0_MSB _u(23) -#define CLOCKS_WAKE_EN1_CLK_SYS_UART0_LSB _u(23) -#define CLOCKS_WAKE_EN1_CLK_SYS_UART0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_WAKE_EN1_CLK_PERI_UART0 -#define CLOCKS_WAKE_EN1_CLK_PERI_UART0_RESET _u(0x1) -#define CLOCKS_WAKE_EN1_CLK_PERI_UART0_BITS _u(0x00400000) -#define CLOCKS_WAKE_EN1_CLK_PERI_UART0_MSB _u(22) -#define CLOCKS_WAKE_EN1_CLK_PERI_UART0_LSB _u(22) -#define CLOCKS_WAKE_EN1_CLK_PERI_UART0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_WAKE_EN1_CLK_SYS_TRNG -#define CLOCKS_WAKE_EN1_CLK_SYS_TRNG_RESET _u(0x1) -#define CLOCKS_WAKE_EN1_CLK_SYS_TRNG_BITS _u(0x00200000) -#define CLOCKS_WAKE_EN1_CLK_SYS_TRNG_MSB _u(21) -#define CLOCKS_WAKE_EN1_CLK_SYS_TRNG_LSB _u(21) -#define CLOCKS_WAKE_EN1_CLK_SYS_TRNG_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_WAKE_EN1_CLK_SYS_TIMER1 -#define CLOCKS_WAKE_EN1_CLK_SYS_TIMER1_RESET _u(0x1) -#define CLOCKS_WAKE_EN1_CLK_SYS_TIMER1_BITS _u(0x00100000) -#define CLOCKS_WAKE_EN1_CLK_SYS_TIMER1_MSB _u(20) -#define CLOCKS_WAKE_EN1_CLK_SYS_TIMER1_LSB _u(20) -#define CLOCKS_WAKE_EN1_CLK_SYS_TIMER1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_WAKE_EN1_CLK_SYS_TIMER0 -#define CLOCKS_WAKE_EN1_CLK_SYS_TIMER0_RESET _u(0x1) -#define CLOCKS_WAKE_EN1_CLK_SYS_TIMER0_BITS _u(0x00080000) -#define CLOCKS_WAKE_EN1_CLK_SYS_TIMER0_MSB _u(19) -#define CLOCKS_WAKE_EN1_CLK_SYS_TIMER0_LSB _u(19) -#define CLOCKS_WAKE_EN1_CLK_SYS_TIMER0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_WAKE_EN1_CLK_SYS_TICKS -#define CLOCKS_WAKE_EN1_CLK_SYS_TICKS_RESET _u(0x1) -#define CLOCKS_WAKE_EN1_CLK_SYS_TICKS_BITS _u(0x00040000) -#define CLOCKS_WAKE_EN1_CLK_SYS_TICKS_MSB _u(18) -#define CLOCKS_WAKE_EN1_CLK_SYS_TICKS_LSB _u(18) -#define CLOCKS_WAKE_EN1_CLK_SYS_TICKS_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_WAKE_EN1_CLK_REF_TICKS -#define CLOCKS_WAKE_EN1_CLK_REF_TICKS_RESET _u(0x1) -#define CLOCKS_WAKE_EN1_CLK_REF_TICKS_BITS _u(0x00020000) -#define CLOCKS_WAKE_EN1_CLK_REF_TICKS_MSB _u(17) -#define CLOCKS_WAKE_EN1_CLK_REF_TICKS_LSB _u(17) -#define CLOCKS_WAKE_EN1_CLK_REF_TICKS_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_WAKE_EN1_CLK_SYS_TBMAN -#define CLOCKS_WAKE_EN1_CLK_SYS_TBMAN_RESET _u(0x1) -#define CLOCKS_WAKE_EN1_CLK_SYS_TBMAN_BITS _u(0x00010000) -#define CLOCKS_WAKE_EN1_CLK_SYS_TBMAN_MSB _u(16) -#define CLOCKS_WAKE_EN1_CLK_SYS_TBMAN_LSB _u(16) -#define CLOCKS_WAKE_EN1_CLK_SYS_TBMAN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_WAKE_EN1_CLK_SYS_SYSINFO -#define CLOCKS_WAKE_EN1_CLK_SYS_SYSINFO_RESET _u(0x1) -#define CLOCKS_WAKE_EN1_CLK_SYS_SYSINFO_BITS _u(0x00008000) -#define CLOCKS_WAKE_EN1_CLK_SYS_SYSINFO_MSB _u(15) -#define CLOCKS_WAKE_EN1_CLK_SYS_SYSINFO_LSB _u(15) -#define CLOCKS_WAKE_EN1_CLK_SYS_SYSINFO_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_WAKE_EN1_CLK_SYS_SYSCFG -#define CLOCKS_WAKE_EN1_CLK_SYS_SYSCFG_RESET _u(0x1) -#define CLOCKS_WAKE_EN1_CLK_SYS_SYSCFG_BITS _u(0x00004000) -#define CLOCKS_WAKE_EN1_CLK_SYS_SYSCFG_MSB _u(14) -#define CLOCKS_WAKE_EN1_CLK_SYS_SYSCFG_LSB _u(14) -#define CLOCKS_WAKE_EN1_CLK_SYS_SYSCFG_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_WAKE_EN1_CLK_SYS_SRAM9 -#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM9_RESET _u(0x1) -#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM9_BITS _u(0x00002000) -#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM9_MSB _u(13) -#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM9_LSB _u(13) -#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM9_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_WAKE_EN1_CLK_SYS_SRAM8 -#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM8_RESET _u(0x1) -#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM8_BITS _u(0x00001000) -#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM8_MSB _u(12) -#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM8_LSB _u(12) -#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM8_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_WAKE_EN1_CLK_SYS_SRAM7 -#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM7_RESET _u(0x1) -#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM7_BITS _u(0x00000800) -#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM7_MSB _u(11) -#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM7_LSB _u(11) -#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM7_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_WAKE_EN1_CLK_SYS_SRAM6 -#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM6_RESET _u(0x1) -#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM6_BITS _u(0x00000400) -#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM6_MSB _u(10) -#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM6_LSB _u(10) -#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM6_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_WAKE_EN1_CLK_SYS_SRAM5 -#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM5_RESET _u(0x1) -#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM5_BITS _u(0x00000200) -#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM5_MSB _u(9) -#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM5_LSB _u(9) -#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM5_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_WAKE_EN1_CLK_SYS_SRAM4 -#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM4_RESET _u(0x1) -#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM4_BITS _u(0x00000100) -#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM4_MSB _u(8) -#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM4_LSB _u(8) -#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM4_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_WAKE_EN1_CLK_SYS_SRAM3 -#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM3_RESET _u(0x1) -#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM3_BITS _u(0x00000080) -#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM3_MSB _u(7) -#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM3_LSB _u(7) -#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM3_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_WAKE_EN1_CLK_SYS_SRAM2 -#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM2_RESET _u(0x1) -#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM2_BITS _u(0x00000040) -#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM2_MSB _u(6) -#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM2_LSB _u(6) -#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM2_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_WAKE_EN1_CLK_SYS_SRAM1 -#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM1_RESET _u(0x1) -#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM1_BITS _u(0x00000020) -#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM1_MSB _u(5) -#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM1_LSB _u(5) -#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_WAKE_EN1_CLK_SYS_SRAM0 -#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM0_RESET _u(0x1) -#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM0_BITS _u(0x00000010) -#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM0_MSB _u(4) -#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM0_LSB _u(4) -#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_WAKE_EN1_CLK_SYS_SPI1 -#define CLOCKS_WAKE_EN1_CLK_SYS_SPI1_RESET _u(0x1) -#define CLOCKS_WAKE_EN1_CLK_SYS_SPI1_BITS _u(0x00000008) -#define CLOCKS_WAKE_EN1_CLK_SYS_SPI1_MSB _u(3) -#define CLOCKS_WAKE_EN1_CLK_SYS_SPI1_LSB _u(3) -#define CLOCKS_WAKE_EN1_CLK_SYS_SPI1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_WAKE_EN1_CLK_PERI_SPI1 -#define CLOCKS_WAKE_EN1_CLK_PERI_SPI1_RESET _u(0x1) -#define CLOCKS_WAKE_EN1_CLK_PERI_SPI1_BITS _u(0x00000004) -#define CLOCKS_WAKE_EN1_CLK_PERI_SPI1_MSB _u(2) -#define CLOCKS_WAKE_EN1_CLK_PERI_SPI1_LSB _u(2) -#define CLOCKS_WAKE_EN1_CLK_PERI_SPI1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_WAKE_EN1_CLK_SYS_SPI0 -#define CLOCKS_WAKE_EN1_CLK_SYS_SPI0_RESET _u(0x1) -#define CLOCKS_WAKE_EN1_CLK_SYS_SPI0_BITS _u(0x00000002) -#define CLOCKS_WAKE_EN1_CLK_SYS_SPI0_MSB _u(1) -#define CLOCKS_WAKE_EN1_CLK_SYS_SPI0_LSB _u(1) -#define CLOCKS_WAKE_EN1_CLK_SYS_SPI0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_WAKE_EN1_CLK_PERI_SPI0 -#define CLOCKS_WAKE_EN1_CLK_PERI_SPI0_RESET _u(0x1) -#define CLOCKS_WAKE_EN1_CLK_PERI_SPI0_BITS _u(0x00000001) -#define CLOCKS_WAKE_EN1_CLK_PERI_SPI0_MSB _u(0) -#define CLOCKS_WAKE_EN1_CLK_PERI_SPI0_LSB _u(0) -#define CLOCKS_WAKE_EN1_CLK_PERI_SPI0_ACCESS "RW" -// ============================================================================= -// Register : CLOCKS_SLEEP_EN0 -// Description : enable clock in sleep mode -#define CLOCKS_SLEEP_EN0_OFFSET _u(0x000000b4) -#define CLOCKS_SLEEP_EN0_BITS _u(0xffffffff) -#define CLOCKS_SLEEP_EN0_RESET _u(0xffffffff) -// ----------------------------------------------------------------------------- -// Field : CLOCKS_SLEEP_EN0_CLK_SYS_SIO -#define CLOCKS_SLEEP_EN0_CLK_SYS_SIO_RESET _u(0x1) -#define CLOCKS_SLEEP_EN0_CLK_SYS_SIO_BITS _u(0x80000000) -#define CLOCKS_SLEEP_EN0_CLK_SYS_SIO_MSB _u(31) -#define CLOCKS_SLEEP_EN0_CLK_SYS_SIO_LSB _u(31) -#define CLOCKS_SLEEP_EN0_CLK_SYS_SIO_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_SLEEP_EN0_CLK_SYS_SHA256 -#define CLOCKS_SLEEP_EN0_CLK_SYS_SHA256_RESET _u(0x1) -#define CLOCKS_SLEEP_EN0_CLK_SYS_SHA256_BITS _u(0x40000000) -#define CLOCKS_SLEEP_EN0_CLK_SYS_SHA256_MSB _u(30) -#define CLOCKS_SLEEP_EN0_CLK_SYS_SHA256_LSB _u(30) -#define CLOCKS_SLEEP_EN0_CLK_SYS_SHA256_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_SLEEP_EN0_CLK_SYS_PSM -#define CLOCKS_SLEEP_EN0_CLK_SYS_PSM_RESET _u(0x1) -#define CLOCKS_SLEEP_EN0_CLK_SYS_PSM_BITS _u(0x20000000) -#define CLOCKS_SLEEP_EN0_CLK_SYS_PSM_MSB _u(29) -#define CLOCKS_SLEEP_EN0_CLK_SYS_PSM_LSB _u(29) -#define CLOCKS_SLEEP_EN0_CLK_SYS_PSM_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_SLEEP_EN0_CLK_SYS_ROSC -#define CLOCKS_SLEEP_EN0_CLK_SYS_ROSC_RESET _u(0x1) -#define CLOCKS_SLEEP_EN0_CLK_SYS_ROSC_BITS _u(0x10000000) -#define CLOCKS_SLEEP_EN0_CLK_SYS_ROSC_MSB _u(28) -#define CLOCKS_SLEEP_EN0_CLK_SYS_ROSC_LSB _u(28) -#define CLOCKS_SLEEP_EN0_CLK_SYS_ROSC_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_SLEEP_EN0_CLK_SYS_ROM -#define CLOCKS_SLEEP_EN0_CLK_SYS_ROM_RESET _u(0x1) -#define CLOCKS_SLEEP_EN0_CLK_SYS_ROM_BITS _u(0x08000000) -#define CLOCKS_SLEEP_EN0_CLK_SYS_ROM_MSB _u(27) -#define CLOCKS_SLEEP_EN0_CLK_SYS_ROM_LSB _u(27) -#define CLOCKS_SLEEP_EN0_CLK_SYS_ROM_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_SLEEP_EN0_CLK_SYS_RESETS -#define CLOCKS_SLEEP_EN0_CLK_SYS_RESETS_RESET _u(0x1) -#define CLOCKS_SLEEP_EN0_CLK_SYS_RESETS_BITS _u(0x04000000) -#define CLOCKS_SLEEP_EN0_CLK_SYS_RESETS_MSB _u(26) -#define CLOCKS_SLEEP_EN0_CLK_SYS_RESETS_LSB _u(26) -#define CLOCKS_SLEEP_EN0_CLK_SYS_RESETS_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_SLEEP_EN0_CLK_SYS_PWM -#define CLOCKS_SLEEP_EN0_CLK_SYS_PWM_RESET _u(0x1) -#define CLOCKS_SLEEP_EN0_CLK_SYS_PWM_BITS _u(0x02000000) -#define CLOCKS_SLEEP_EN0_CLK_SYS_PWM_MSB _u(25) -#define CLOCKS_SLEEP_EN0_CLK_SYS_PWM_LSB _u(25) -#define CLOCKS_SLEEP_EN0_CLK_SYS_PWM_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_SLEEP_EN0_CLK_SYS_POWMAN -#define CLOCKS_SLEEP_EN0_CLK_SYS_POWMAN_RESET _u(0x1) -#define CLOCKS_SLEEP_EN0_CLK_SYS_POWMAN_BITS _u(0x01000000) -#define CLOCKS_SLEEP_EN0_CLK_SYS_POWMAN_MSB _u(24) -#define CLOCKS_SLEEP_EN0_CLK_SYS_POWMAN_LSB _u(24) -#define CLOCKS_SLEEP_EN0_CLK_SYS_POWMAN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_SLEEP_EN0_CLK_REF_POWMAN -#define CLOCKS_SLEEP_EN0_CLK_REF_POWMAN_RESET _u(0x1) -#define CLOCKS_SLEEP_EN0_CLK_REF_POWMAN_BITS _u(0x00800000) -#define CLOCKS_SLEEP_EN0_CLK_REF_POWMAN_MSB _u(23) -#define CLOCKS_SLEEP_EN0_CLK_REF_POWMAN_LSB _u(23) -#define CLOCKS_SLEEP_EN0_CLK_REF_POWMAN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_SLEEP_EN0_CLK_SYS_PLL_USB -#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_USB_RESET _u(0x1) -#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_USB_BITS _u(0x00400000) -#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_USB_MSB _u(22) -#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_USB_LSB _u(22) -#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_USB_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_SLEEP_EN0_CLK_SYS_PLL_SYS -#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_SYS_RESET _u(0x1) -#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_SYS_BITS _u(0x00200000) -#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_SYS_MSB _u(21) -#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_SYS_LSB _u(21) -#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_SYS_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_SLEEP_EN0_CLK_SYS_PIO2 -#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO2_RESET _u(0x1) -#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO2_BITS _u(0x00100000) -#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO2_MSB _u(20) -#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO2_LSB _u(20) -#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO2_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_SLEEP_EN0_CLK_SYS_PIO1 -#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO1_RESET _u(0x1) -#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO1_BITS _u(0x00080000) -#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO1_MSB _u(19) -#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO1_LSB _u(19) -#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_SLEEP_EN0_CLK_SYS_PIO0 -#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO0_RESET _u(0x1) -#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO0_BITS _u(0x00040000) -#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO0_MSB _u(18) -#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO0_LSB _u(18) -#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_SLEEP_EN0_CLK_SYS_PADS -#define CLOCKS_SLEEP_EN0_CLK_SYS_PADS_RESET _u(0x1) -#define CLOCKS_SLEEP_EN0_CLK_SYS_PADS_BITS _u(0x00020000) -#define CLOCKS_SLEEP_EN0_CLK_SYS_PADS_MSB _u(17) -#define CLOCKS_SLEEP_EN0_CLK_SYS_PADS_LSB _u(17) -#define CLOCKS_SLEEP_EN0_CLK_SYS_PADS_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_SLEEP_EN0_CLK_SYS_OTP -#define CLOCKS_SLEEP_EN0_CLK_SYS_OTP_RESET _u(0x1) -#define CLOCKS_SLEEP_EN0_CLK_SYS_OTP_BITS _u(0x00010000) -#define CLOCKS_SLEEP_EN0_CLK_SYS_OTP_MSB _u(16) -#define CLOCKS_SLEEP_EN0_CLK_SYS_OTP_LSB _u(16) -#define CLOCKS_SLEEP_EN0_CLK_SYS_OTP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_SLEEP_EN0_CLK_REF_OTP -#define CLOCKS_SLEEP_EN0_CLK_REF_OTP_RESET _u(0x1) -#define CLOCKS_SLEEP_EN0_CLK_REF_OTP_BITS _u(0x00008000) -#define CLOCKS_SLEEP_EN0_CLK_REF_OTP_MSB _u(15) -#define CLOCKS_SLEEP_EN0_CLK_REF_OTP_LSB _u(15) -#define CLOCKS_SLEEP_EN0_CLK_REF_OTP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_SLEEP_EN0_CLK_SYS_JTAG -#define CLOCKS_SLEEP_EN0_CLK_SYS_JTAG_RESET _u(0x1) -#define CLOCKS_SLEEP_EN0_CLK_SYS_JTAG_BITS _u(0x00004000) -#define CLOCKS_SLEEP_EN0_CLK_SYS_JTAG_MSB _u(14) -#define CLOCKS_SLEEP_EN0_CLK_SYS_JTAG_LSB _u(14) -#define CLOCKS_SLEEP_EN0_CLK_SYS_JTAG_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_SLEEP_EN0_CLK_SYS_IO -#define CLOCKS_SLEEP_EN0_CLK_SYS_IO_RESET _u(0x1) -#define CLOCKS_SLEEP_EN0_CLK_SYS_IO_BITS _u(0x00002000) -#define CLOCKS_SLEEP_EN0_CLK_SYS_IO_MSB _u(13) -#define CLOCKS_SLEEP_EN0_CLK_SYS_IO_LSB _u(13) -#define CLOCKS_SLEEP_EN0_CLK_SYS_IO_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_SLEEP_EN0_CLK_SYS_I2C1 -#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C1_RESET _u(0x1) -#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C1_BITS _u(0x00001000) -#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C1_MSB _u(12) -#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C1_LSB _u(12) -#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_SLEEP_EN0_CLK_SYS_I2C0 -#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C0_RESET _u(0x1) -#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C0_BITS _u(0x00000800) -#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C0_MSB _u(11) -#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C0_LSB _u(11) -#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_SLEEP_EN0_CLK_SYS_HSTX -#define CLOCKS_SLEEP_EN0_CLK_SYS_HSTX_RESET _u(0x1) -#define CLOCKS_SLEEP_EN0_CLK_SYS_HSTX_BITS _u(0x00000400) -#define CLOCKS_SLEEP_EN0_CLK_SYS_HSTX_MSB _u(10) -#define CLOCKS_SLEEP_EN0_CLK_SYS_HSTX_LSB _u(10) -#define CLOCKS_SLEEP_EN0_CLK_SYS_HSTX_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_SLEEP_EN0_CLK_HSTX -#define CLOCKS_SLEEP_EN0_CLK_HSTX_RESET _u(0x1) -#define CLOCKS_SLEEP_EN0_CLK_HSTX_BITS _u(0x00000200) -#define CLOCKS_SLEEP_EN0_CLK_HSTX_MSB _u(9) -#define CLOCKS_SLEEP_EN0_CLK_HSTX_LSB _u(9) -#define CLOCKS_SLEEP_EN0_CLK_HSTX_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_SLEEP_EN0_CLK_SYS_GLITCH_DETECTOR -#define CLOCKS_SLEEP_EN0_CLK_SYS_GLITCH_DETECTOR_RESET _u(0x1) -#define CLOCKS_SLEEP_EN0_CLK_SYS_GLITCH_DETECTOR_BITS _u(0x00000100) -#define CLOCKS_SLEEP_EN0_CLK_SYS_GLITCH_DETECTOR_MSB _u(8) -#define CLOCKS_SLEEP_EN0_CLK_SYS_GLITCH_DETECTOR_LSB _u(8) -#define CLOCKS_SLEEP_EN0_CLK_SYS_GLITCH_DETECTOR_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_SLEEP_EN0_CLK_SYS_DMA -#define CLOCKS_SLEEP_EN0_CLK_SYS_DMA_RESET _u(0x1) -#define CLOCKS_SLEEP_EN0_CLK_SYS_DMA_BITS _u(0x00000080) -#define CLOCKS_SLEEP_EN0_CLK_SYS_DMA_MSB _u(7) -#define CLOCKS_SLEEP_EN0_CLK_SYS_DMA_LSB _u(7) -#define CLOCKS_SLEEP_EN0_CLK_SYS_DMA_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_SLEEP_EN0_CLK_SYS_BUSFABRIC -#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSFABRIC_RESET _u(0x1) -#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSFABRIC_BITS _u(0x00000040) -#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSFABRIC_MSB _u(6) -#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSFABRIC_LSB _u(6) -#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSFABRIC_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_SLEEP_EN0_CLK_SYS_BUSCTRL -#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSCTRL_RESET _u(0x1) -#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSCTRL_BITS _u(0x00000020) -#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSCTRL_MSB _u(5) -#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSCTRL_LSB _u(5) -#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSCTRL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_SLEEP_EN0_CLK_SYS_BOOTRAM -#define CLOCKS_SLEEP_EN0_CLK_SYS_BOOTRAM_RESET _u(0x1) -#define CLOCKS_SLEEP_EN0_CLK_SYS_BOOTRAM_BITS _u(0x00000010) -#define CLOCKS_SLEEP_EN0_CLK_SYS_BOOTRAM_MSB _u(4) -#define CLOCKS_SLEEP_EN0_CLK_SYS_BOOTRAM_LSB _u(4) -#define CLOCKS_SLEEP_EN0_CLK_SYS_BOOTRAM_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_SLEEP_EN0_CLK_SYS_ADC -#define CLOCKS_SLEEP_EN0_CLK_SYS_ADC_RESET _u(0x1) -#define CLOCKS_SLEEP_EN0_CLK_SYS_ADC_BITS _u(0x00000008) -#define CLOCKS_SLEEP_EN0_CLK_SYS_ADC_MSB _u(3) -#define CLOCKS_SLEEP_EN0_CLK_SYS_ADC_LSB _u(3) -#define CLOCKS_SLEEP_EN0_CLK_SYS_ADC_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_SLEEP_EN0_CLK_ADC -#define CLOCKS_SLEEP_EN0_CLK_ADC_RESET _u(0x1) -#define CLOCKS_SLEEP_EN0_CLK_ADC_BITS _u(0x00000004) -#define CLOCKS_SLEEP_EN0_CLK_ADC_MSB _u(2) -#define CLOCKS_SLEEP_EN0_CLK_ADC_LSB _u(2) -#define CLOCKS_SLEEP_EN0_CLK_ADC_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_SLEEP_EN0_CLK_SYS_ACCESSCTRL -#define CLOCKS_SLEEP_EN0_CLK_SYS_ACCESSCTRL_RESET _u(0x1) -#define CLOCKS_SLEEP_EN0_CLK_SYS_ACCESSCTRL_BITS _u(0x00000002) -#define CLOCKS_SLEEP_EN0_CLK_SYS_ACCESSCTRL_MSB _u(1) -#define CLOCKS_SLEEP_EN0_CLK_SYS_ACCESSCTRL_LSB _u(1) -#define CLOCKS_SLEEP_EN0_CLK_SYS_ACCESSCTRL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_SLEEP_EN0_CLK_SYS_CLOCKS -#define CLOCKS_SLEEP_EN0_CLK_SYS_CLOCKS_RESET _u(0x1) -#define CLOCKS_SLEEP_EN0_CLK_SYS_CLOCKS_BITS _u(0x00000001) -#define CLOCKS_SLEEP_EN0_CLK_SYS_CLOCKS_MSB _u(0) -#define CLOCKS_SLEEP_EN0_CLK_SYS_CLOCKS_LSB _u(0) -#define CLOCKS_SLEEP_EN0_CLK_SYS_CLOCKS_ACCESS "RW" -// ============================================================================= -// Register : CLOCKS_SLEEP_EN1 -// Description : enable clock in sleep mode -#define CLOCKS_SLEEP_EN1_OFFSET _u(0x000000b8) -#define CLOCKS_SLEEP_EN1_BITS _u(0x7fffffff) -#define CLOCKS_SLEEP_EN1_RESET _u(0x7fffffff) -// ----------------------------------------------------------------------------- -// Field : CLOCKS_SLEEP_EN1_CLK_SYS_XOSC -#define CLOCKS_SLEEP_EN1_CLK_SYS_XOSC_RESET _u(0x1) -#define CLOCKS_SLEEP_EN1_CLK_SYS_XOSC_BITS _u(0x40000000) -#define CLOCKS_SLEEP_EN1_CLK_SYS_XOSC_MSB _u(30) -#define CLOCKS_SLEEP_EN1_CLK_SYS_XOSC_LSB _u(30) -#define CLOCKS_SLEEP_EN1_CLK_SYS_XOSC_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_SLEEP_EN1_CLK_SYS_XIP -#define CLOCKS_SLEEP_EN1_CLK_SYS_XIP_RESET _u(0x1) -#define CLOCKS_SLEEP_EN1_CLK_SYS_XIP_BITS _u(0x20000000) -#define CLOCKS_SLEEP_EN1_CLK_SYS_XIP_MSB _u(29) -#define CLOCKS_SLEEP_EN1_CLK_SYS_XIP_LSB _u(29) -#define CLOCKS_SLEEP_EN1_CLK_SYS_XIP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_SLEEP_EN1_CLK_SYS_WATCHDOG -#define CLOCKS_SLEEP_EN1_CLK_SYS_WATCHDOG_RESET _u(0x1) -#define CLOCKS_SLEEP_EN1_CLK_SYS_WATCHDOG_BITS _u(0x10000000) -#define CLOCKS_SLEEP_EN1_CLK_SYS_WATCHDOG_MSB _u(28) -#define CLOCKS_SLEEP_EN1_CLK_SYS_WATCHDOG_LSB _u(28) -#define CLOCKS_SLEEP_EN1_CLK_SYS_WATCHDOG_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_SLEEP_EN1_CLK_USB -#define CLOCKS_SLEEP_EN1_CLK_USB_RESET _u(0x1) -#define CLOCKS_SLEEP_EN1_CLK_USB_BITS _u(0x08000000) -#define CLOCKS_SLEEP_EN1_CLK_USB_MSB _u(27) -#define CLOCKS_SLEEP_EN1_CLK_USB_LSB _u(27) -#define CLOCKS_SLEEP_EN1_CLK_USB_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_SLEEP_EN1_CLK_SYS_USBCTRL -#define CLOCKS_SLEEP_EN1_CLK_SYS_USBCTRL_RESET _u(0x1) -#define CLOCKS_SLEEP_EN1_CLK_SYS_USBCTRL_BITS _u(0x04000000) -#define CLOCKS_SLEEP_EN1_CLK_SYS_USBCTRL_MSB _u(26) -#define CLOCKS_SLEEP_EN1_CLK_SYS_USBCTRL_LSB _u(26) -#define CLOCKS_SLEEP_EN1_CLK_SYS_USBCTRL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_SLEEP_EN1_CLK_SYS_UART1 -#define CLOCKS_SLEEP_EN1_CLK_SYS_UART1_RESET _u(0x1) -#define CLOCKS_SLEEP_EN1_CLK_SYS_UART1_BITS _u(0x02000000) -#define CLOCKS_SLEEP_EN1_CLK_SYS_UART1_MSB _u(25) -#define CLOCKS_SLEEP_EN1_CLK_SYS_UART1_LSB _u(25) -#define CLOCKS_SLEEP_EN1_CLK_SYS_UART1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_SLEEP_EN1_CLK_PERI_UART1 -#define CLOCKS_SLEEP_EN1_CLK_PERI_UART1_RESET _u(0x1) -#define CLOCKS_SLEEP_EN1_CLK_PERI_UART1_BITS _u(0x01000000) -#define CLOCKS_SLEEP_EN1_CLK_PERI_UART1_MSB _u(24) -#define CLOCKS_SLEEP_EN1_CLK_PERI_UART1_LSB _u(24) -#define CLOCKS_SLEEP_EN1_CLK_PERI_UART1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_SLEEP_EN1_CLK_SYS_UART0 -#define CLOCKS_SLEEP_EN1_CLK_SYS_UART0_RESET _u(0x1) -#define CLOCKS_SLEEP_EN1_CLK_SYS_UART0_BITS _u(0x00800000) -#define CLOCKS_SLEEP_EN1_CLK_SYS_UART0_MSB _u(23) -#define CLOCKS_SLEEP_EN1_CLK_SYS_UART0_LSB _u(23) -#define CLOCKS_SLEEP_EN1_CLK_SYS_UART0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_SLEEP_EN1_CLK_PERI_UART0 -#define CLOCKS_SLEEP_EN1_CLK_PERI_UART0_RESET _u(0x1) -#define CLOCKS_SLEEP_EN1_CLK_PERI_UART0_BITS _u(0x00400000) -#define CLOCKS_SLEEP_EN1_CLK_PERI_UART0_MSB _u(22) -#define CLOCKS_SLEEP_EN1_CLK_PERI_UART0_LSB _u(22) -#define CLOCKS_SLEEP_EN1_CLK_PERI_UART0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_SLEEP_EN1_CLK_SYS_TRNG -#define CLOCKS_SLEEP_EN1_CLK_SYS_TRNG_RESET _u(0x1) -#define CLOCKS_SLEEP_EN1_CLK_SYS_TRNG_BITS _u(0x00200000) -#define CLOCKS_SLEEP_EN1_CLK_SYS_TRNG_MSB _u(21) -#define CLOCKS_SLEEP_EN1_CLK_SYS_TRNG_LSB _u(21) -#define CLOCKS_SLEEP_EN1_CLK_SYS_TRNG_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_SLEEP_EN1_CLK_SYS_TIMER1 -#define CLOCKS_SLEEP_EN1_CLK_SYS_TIMER1_RESET _u(0x1) -#define CLOCKS_SLEEP_EN1_CLK_SYS_TIMER1_BITS _u(0x00100000) -#define CLOCKS_SLEEP_EN1_CLK_SYS_TIMER1_MSB _u(20) -#define CLOCKS_SLEEP_EN1_CLK_SYS_TIMER1_LSB _u(20) -#define CLOCKS_SLEEP_EN1_CLK_SYS_TIMER1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_SLEEP_EN1_CLK_SYS_TIMER0 -#define CLOCKS_SLEEP_EN1_CLK_SYS_TIMER0_RESET _u(0x1) -#define CLOCKS_SLEEP_EN1_CLK_SYS_TIMER0_BITS _u(0x00080000) -#define CLOCKS_SLEEP_EN1_CLK_SYS_TIMER0_MSB _u(19) -#define CLOCKS_SLEEP_EN1_CLK_SYS_TIMER0_LSB _u(19) -#define CLOCKS_SLEEP_EN1_CLK_SYS_TIMER0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_SLEEP_EN1_CLK_SYS_TICKS -#define CLOCKS_SLEEP_EN1_CLK_SYS_TICKS_RESET _u(0x1) -#define CLOCKS_SLEEP_EN1_CLK_SYS_TICKS_BITS _u(0x00040000) -#define CLOCKS_SLEEP_EN1_CLK_SYS_TICKS_MSB _u(18) -#define CLOCKS_SLEEP_EN1_CLK_SYS_TICKS_LSB _u(18) -#define CLOCKS_SLEEP_EN1_CLK_SYS_TICKS_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_SLEEP_EN1_CLK_REF_TICKS -#define CLOCKS_SLEEP_EN1_CLK_REF_TICKS_RESET _u(0x1) -#define CLOCKS_SLEEP_EN1_CLK_REF_TICKS_BITS _u(0x00020000) -#define CLOCKS_SLEEP_EN1_CLK_REF_TICKS_MSB _u(17) -#define CLOCKS_SLEEP_EN1_CLK_REF_TICKS_LSB _u(17) -#define CLOCKS_SLEEP_EN1_CLK_REF_TICKS_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_SLEEP_EN1_CLK_SYS_TBMAN -#define CLOCKS_SLEEP_EN1_CLK_SYS_TBMAN_RESET _u(0x1) -#define CLOCKS_SLEEP_EN1_CLK_SYS_TBMAN_BITS _u(0x00010000) -#define CLOCKS_SLEEP_EN1_CLK_SYS_TBMAN_MSB _u(16) -#define CLOCKS_SLEEP_EN1_CLK_SYS_TBMAN_LSB _u(16) -#define CLOCKS_SLEEP_EN1_CLK_SYS_TBMAN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_SLEEP_EN1_CLK_SYS_SYSINFO -#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSINFO_RESET _u(0x1) -#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSINFO_BITS _u(0x00008000) -#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSINFO_MSB _u(15) -#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSINFO_LSB _u(15) -#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSINFO_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_SLEEP_EN1_CLK_SYS_SYSCFG -#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSCFG_RESET _u(0x1) -#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSCFG_BITS _u(0x00004000) -#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSCFG_MSB _u(14) -#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSCFG_LSB _u(14) -#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSCFG_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_SLEEP_EN1_CLK_SYS_SRAM9 -#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM9_RESET _u(0x1) -#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM9_BITS _u(0x00002000) -#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM9_MSB _u(13) -#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM9_LSB _u(13) -#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM9_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_SLEEP_EN1_CLK_SYS_SRAM8 -#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM8_RESET _u(0x1) -#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM8_BITS _u(0x00001000) -#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM8_MSB _u(12) -#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM8_LSB _u(12) -#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM8_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_SLEEP_EN1_CLK_SYS_SRAM7 -#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM7_RESET _u(0x1) -#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM7_BITS _u(0x00000800) -#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM7_MSB _u(11) -#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM7_LSB _u(11) -#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM7_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_SLEEP_EN1_CLK_SYS_SRAM6 -#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM6_RESET _u(0x1) -#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM6_BITS _u(0x00000400) -#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM6_MSB _u(10) -#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM6_LSB _u(10) -#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM6_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_SLEEP_EN1_CLK_SYS_SRAM5 -#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM5_RESET _u(0x1) -#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM5_BITS _u(0x00000200) -#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM5_MSB _u(9) -#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM5_LSB _u(9) -#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM5_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_SLEEP_EN1_CLK_SYS_SRAM4 -#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM4_RESET _u(0x1) -#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM4_BITS _u(0x00000100) -#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM4_MSB _u(8) -#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM4_LSB _u(8) -#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM4_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_SLEEP_EN1_CLK_SYS_SRAM3 -#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM3_RESET _u(0x1) -#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM3_BITS _u(0x00000080) -#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM3_MSB _u(7) -#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM3_LSB _u(7) -#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM3_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_SLEEP_EN1_CLK_SYS_SRAM2 -#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM2_RESET _u(0x1) -#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM2_BITS _u(0x00000040) -#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM2_MSB _u(6) -#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM2_LSB _u(6) -#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM2_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_SLEEP_EN1_CLK_SYS_SRAM1 -#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM1_RESET _u(0x1) -#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM1_BITS _u(0x00000020) -#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM1_MSB _u(5) -#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM1_LSB _u(5) -#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_SLEEP_EN1_CLK_SYS_SRAM0 -#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM0_RESET _u(0x1) -#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM0_BITS _u(0x00000010) -#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM0_MSB _u(4) -#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM0_LSB _u(4) -#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_SLEEP_EN1_CLK_SYS_SPI1 -#define CLOCKS_SLEEP_EN1_CLK_SYS_SPI1_RESET _u(0x1) -#define CLOCKS_SLEEP_EN1_CLK_SYS_SPI1_BITS _u(0x00000008) -#define CLOCKS_SLEEP_EN1_CLK_SYS_SPI1_MSB _u(3) -#define CLOCKS_SLEEP_EN1_CLK_SYS_SPI1_LSB _u(3) -#define CLOCKS_SLEEP_EN1_CLK_SYS_SPI1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_SLEEP_EN1_CLK_PERI_SPI1 -#define CLOCKS_SLEEP_EN1_CLK_PERI_SPI1_RESET _u(0x1) -#define CLOCKS_SLEEP_EN1_CLK_PERI_SPI1_BITS _u(0x00000004) -#define CLOCKS_SLEEP_EN1_CLK_PERI_SPI1_MSB _u(2) -#define CLOCKS_SLEEP_EN1_CLK_PERI_SPI1_LSB _u(2) -#define CLOCKS_SLEEP_EN1_CLK_PERI_SPI1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_SLEEP_EN1_CLK_SYS_SPI0 -#define CLOCKS_SLEEP_EN1_CLK_SYS_SPI0_RESET _u(0x1) -#define CLOCKS_SLEEP_EN1_CLK_SYS_SPI0_BITS _u(0x00000002) -#define CLOCKS_SLEEP_EN1_CLK_SYS_SPI0_MSB _u(1) -#define CLOCKS_SLEEP_EN1_CLK_SYS_SPI0_LSB _u(1) -#define CLOCKS_SLEEP_EN1_CLK_SYS_SPI0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_SLEEP_EN1_CLK_PERI_SPI0 -#define CLOCKS_SLEEP_EN1_CLK_PERI_SPI0_RESET _u(0x1) -#define CLOCKS_SLEEP_EN1_CLK_PERI_SPI0_BITS _u(0x00000001) -#define CLOCKS_SLEEP_EN1_CLK_PERI_SPI0_MSB _u(0) -#define CLOCKS_SLEEP_EN1_CLK_PERI_SPI0_LSB _u(0) -#define CLOCKS_SLEEP_EN1_CLK_PERI_SPI0_ACCESS "RW" -// ============================================================================= -// Register : CLOCKS_ENABLED0 -// Description : indicates the state of the clock enable -#define CLOCKS_ENABLED0_OFFSET _u(0x000000bc) -#define CLOCKS_ENABLED0_BITS _u(0xffffffff) -#define CLOCKS_ENABLED0_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : CLOCKS_ENABLED0_CLK_SYS_SIO -#define CLOCKS_ENABLED0_CLK_SYS_SIO_RESET _u(0x0) -#define CLOCKS_ENABLED0_CLK_SYS_SIO_BITS _u(0x80000000) -#define CLOCKS_ENABLED0_CLK_SYS_SIO_MSB _u(31) -#define CLOCKS_ENABLED0_CLK_SYS_SIO_LSB _u(31) -#define CLOCKS_ENABLED0_CLK_SYS_SIO_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_ENABLED0_CLK_SYS_SHA256 -#define CLOCKS_ENABLED0_CLK_SYS_SHA256_RESET _u(0x0) -#define CLOCKS_ENABLED0_CLK_SYS_SHA256_BITS _u(0x40000000) -#define CLOCKS_ENABLED0_CLK_SYS_SHA256_MSB _u(30) -#define CLOCKS_ENABLED0_CLK_SYS_SHA256_LSB _u(30) -#define CLOCKS_ENABLED0_CLK_SYS_SHA256_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_ENABLED0_CLK_SYS_PSM -#define CLOCKS_ENABLED0_CLK_SYS_PSM_RESET _u(0x0) -#define CLOCKS_ENABLED0_CLK_SYS_PSM_BITS _u(0x20000000) -#define CLOCKS_ENABLED0_CLK_SYS_PSM_MSB _u(29) -#define CLOCKS_ENABLED0_CLK_SYS_PSM_LSB _u(29) -#define CLOCKS_ENABLED0_CLK_SYS_PSM_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_ENABLED0_CLK_SYS_ROSC -#define CLOCKS_ENABLED0_CLK_SYS_ROSC_RESET _u(0x0) -#define CLOCKS_ENABLED0_CLK_SYS_ROSC_BITS _u(0x10000000) -#define CLOCKS_ENABLED0_CLK_SYS_ROSC_MSB _u(28) -#define CLOCKS_ENABLED0_CLK_SYS_ROSC_LSB _u(28) -#define CLOCKS_ENABLED0_CLK_SYS_ROSC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_ENABLED0_CLK_SYS_ROM -#define CLOCKS_ENABLED0_CLK_SYS_ROM_RESET _u(0x0) -#define CLOCKS_ENABLED0_CLK_SYS_ROM_BITS _u(0x08000000) -#define CLOCKS_ENABLED0_CLK_SYS_ROM_MSB _u(27) -#define CLOCKS_ENABLED0_CLK_SYS_ROM_LSB _u(27) -#define CLOCKS_ENABLED0_CLK_SYS_ROM_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_ENABLED0_CLK_SYS_RESETS -#define CLOCKS_ENABLED0_CLK_SYS_RESETS_RESET _u(0x0) -#define CLOCKS_ENABLED0_CLK_SYS_RESETS_BITS _u(0x04000000) -#define CLOCKS_ENABLED0_CLK_SYS_RESETS_MSB _u(26) -#define CLOCKS_ENABLED0_CLK_SYS_RESETS_LSB _u(26) -#define CLOCKS_ENABLED0_CLK_SYS_RESETS_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_ENABLED0_CLK_SYS_PWM -#define CLOCKS_ENABLED0_CLK_SYS_PWM_RESET _u(0x0) -#define CLOCKS_ENABLED0_CLK_SYS_PWM_BITS _u(0x02000000) -#define CLOCKS_ENABLED0_CLK_SYS_PWM_MSB _u(25) -#define CLOCKS_ENABLED0_CLK_SYS_PWM_LSB _u(25) -#define CLOCKS_ENABLED0_CLK_SYS_PWM_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_ENABLED0_CLK_SYS_POWMAN -#define CLOCKS_ENABLED0_CLK_SYS_POWMAN_RESET _u(0x0) -#define CLOCKS_ENABLED0_CLK_SYS_POWMAN_BITS _u(0x01000000) -#define CLOCKS_ENABLED0_CLK_SYS_POWMAN_MSB _u(24) -#define CLOCKS_ENABLED0_CLK_SYS_POWMAN_LSB _u(24) -#define CLOCKS_ENABLED0_CLK_SYS_POWMAN_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_ENABLED0_CLK_REF_POWMAN -#define CLOCKS_ENABLED0_CLK_REF_POWMAN_RESET _u(0x0) -#define CLOCKS_ENABLED0_CLK_REF_POWMAN_BITS _u(0x00800000) -#define CLOCKS_ENABLED0_CLK_REF_POWMAN_MSB _u(23) -#define CLOCKS_ENABLED0_CLK_REF_POWMAN_LSB _u(23) -#define CLOCKS_ENABLED0_CLK_REF_POWMAN_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_ENABLED0_CLK_SYS_PLL_USB -#define CLOCKS_ENABLED0_CLK_SYS_PLL_USB_RESET _u(0x0) -#define CLOCKS_ENABLED0_CLK_SYS_PLL_USB_BITS _u(0x00400000) -#define CLOCKS_ENABLED0_CLK_SYS_PLL_USB_MSB _u(22) -#define CLOCKS_ENABLED0_CLK_SYS_PLL_USB_LSB _u(22) -#define CLOCKS_ENABLED0_CLK_SYS_PLL_USB_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_ENABLED0_CLK_SYS_PLL_SYS -#define CLOCKS_ENABLED0_CLK_SYS_PLL_SYS_RESET _u(0x0) -#define CLOCKS_ENABLED0_CLK_SYS_PLL_SYS_BITS _u(0x00200000) -#define CLOCKS_ENABLED0_CLK_SYS_PLL_SYS_MSB _u(21) -#define CLOCKS_ENABLED0_CLK_SYS_PLL_SYS_LSB _u(21) -#define CLOCKS_ENABLED0_CLK_SYS_PLL_SYS_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_ENABLED0_CLK_SYS_PIO2 -#define CLOCKS_ENABLED0_CLK_SYS_PIO2_RESET _u(0x0) -#define CLOCKS_ENABLED0_CLK_SYS_PIO2_BITS _u(0x00100000) -#define CLOCKS_ENABLED0_CLK_SYS_PIO2_MSB _u(20) -#define CLOCKS_ENABLED0_CLK_SYS_PIO2_LSB _u(20) -#define CLOCKS_ENABLED0_CLK_SYS_PIO2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_ENABLED0_CLK_SYS_PIO1 -#define CLOCKS_ENABLED0_CLK_SYS_PIO1_RESET _u(0x0) -#define CLOCKS_ENABLED0_CLK_SYS_PIO1_BITS _u(0x00080000) -#define CLOCKS_ENABLED0_CLK_SYS_PIO1_MSB _u(19) -#define CLOCKS_ENABLED0_CLK_SYS_PIO1_LSB _u(19) -#define CLOCKS_ENABLED0_CLK_SYS_PIO1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_ENABLED0_CLK_SYS_PIO0 -#define CLOCKS_ENABLED0_CLK_SYS_PIO0_RESET _u(0x0) -#define CLOCKS_ENABLED0_CLK_SYS_PIO0_BITS _u(0x00040000) -#define CLOCKS_ENABLED0_CLK_SYS_PIO0_MSB _u(18) -#define CLOCKS_ENABLED0_CLK_SYS_PIO0_LSB _u(18) -#define CLOCKS_ENABLED0_CLK_SYS_PIO0_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_ENABLED0_CLK_SYS_PADS -#define CLOCKS_ENABLED0_CLK_SYS_PADS_RESET _u(0x0) -#define CLOCKS_ENABLED0_CLK_SYS_PADS_BITS _u(0x00020000) -#define CLOCKS_ENABLED0_CLK_SYS_PADS_MSB _u(17) -#define CLOCKS_ENABLED0_CLK_SYS_PADS_LSB _u(17) -#define CLOCKS_ENABLED0_CLK_SYS_PADS_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_ENABLED0_CLK_SYS_OTP -#define CLOCKS_ENABLED0_CLK_SYS_OTP_RESET _u(0x0) -#define CLOCKS_ENABLED0_CLK_SYS_OTP_BITS _u(0x00010000) -#define CLOCKS_ENABLED0_CLK_SYS_OTP_MSB _u(16) -#define CLOCKS_ENABLED0_CLK_SYS_OTP_LSB _u(16) -#define CLOCKS_ENABLED0_CLK_SYS_OTP_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_ENABLED0_CLK_REF_OTP -#define CLOCKS_ENABLED0_CLK_REF_OTP_RESET _u(0x0) -#define CLOCKS_ENABLED0_CLK_REF_OTP_BITS _u(0x00008000) -#define CLOCKS_ENABLED0_CLK_REF_OTP_MSB _u(15) -#define CLOCKS_ENABLED0_CLK_REF_OTP_LSB _u(15) -#define CLOCKS_ENABLED0_CLK_REF_OTP_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_ENABLED0_CLK_SYS_JTAG -#define CLOCKS_ENABLED0_CLK_SYS_JTAG_RESET _u(0x0) -#define CLOCKS_ENABLED0_CLK_SYS_JTAG_BITS _u(0x00004000) -#define CLOCKS_ENABLED0_CLK_SYS_JTAG_MSB _u(14) -#define CLOCKS_ENABLED0_CLK_SYS_JTAG_LSB _u(14) -#define CLOCKS_ENABLED0_CLK_SYS_JTAG_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_ENABLED0_CLK_SYS_IO -#define CLOCKS_ENABLED0_CLK_SYS_IO_RESET _u(0x0) -#define CLOCKS_ENABLED0_CLK_SYS_IO_BITS _u(0x00002000) -#define CLOCKS_ENABLED0_CLK_SYS_IO_MSB _u(13) -#define CLOCKS_ENABLED0_CLK_SYS_IO_LSB _u(13) -#define CLOCKS_ENABLED0_CLK_SYS_IO_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_ENABLED0_CLK_SYS_I2C1 -#define CLOCKS_ENABLED0_CLK_SYS_I2C1_RESET _u(0x0) -#define CLOCKS_ENABLED0_CLK_SYS_I2C1_BITS _u(0x00001000) -#define CLOCKS_ENABLED0_CLK_SYS_I2C1_MSB _u(12) -#define CLOCKS_ENABLED0_CLK_SYS_I2C1_LSB _u(12) -#define CLOCKS_ENABLED0_CLK_SYS_I2C1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_ENABLED0_CLK_SYS_I2C0 -#define CLOCKS_ENABLED0_CLK_SYS_I2C0_RESET _u(0x0) -#define CLOCKS_ENABLED0_CLK_SYS_I2C0_BITS _u(0x00000800) -#define CLOCKS_ENABLED0_CLK_SYS_I2C0_MSB _u(11) -#define CLOCKS_ENABLED0_CLK_SYS_I2C0_LSB _u(11) -#define CLOCKS_ENABLED0_CLK_SYS_I2C0_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_ENABLED0_CLK_SYS_HSTX -#define CLOCKS_ENABLED0_CLK_SYS_HSTX_RESET _u(0x0) -#define CLOCKS_ENABLED0_CLK_SYS_HSTX_BITS _u(0x00000400) -#define CLOCKS_ENABLED0_CLK_SYS_HSTX_MSB _u(10) -#define CLOCKS_ENABLED0_CLK_SYS_HSTX_LSB _u(10) -#define CLOCKS_ENABLED0_CLK_SYS_HSTX_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_ENABLED0_CLK_HSTX -#define CLOCKS_ENABLED0_CLK_HSTX_RESET _u(0x0) -#define CLOCKS_ENABLED0_CLK_HSTX_BITS _u(0x00000200) -#define CLOCKS_ENABLED0_CLK_HSTX_MSB _u(9) -#define CLOCKS_ENABLED0_CLK_HSTX_LSB _u(9) -#define CLOCKS_ENABLED0_CLK_HSTX_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_ENABLED0_CLK_SYS_GLITCH_DETECTOR -#define CLOCKS_ENABLED0_CLK_SYS_GLITCH_DETECTOR_RESET _u(0x0) -#define CLOCKS_ENABLED0_CLK_SYS_GLITCH_DETECTOR_BITS _u(0x00000100) -#define CLOCKS_ENABLED0_CLK_SYS_GLITCH_DETECTOR_MSB _u(8) -#define CLOCKS_ENABLED0_CLK_SYS_GLITCH_DETECTOR_LSB _u(8) -#define CLOCKS_ENABLED0_CLK_SYS_GLITCH_DETECTOR_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_ENABLED0_CLK_SYS_DMA -#define CLOCKS_ENABLED0_CLK_SYS_DMA_RESET _u(0x0) -#define CLOCKS_ENABLED0_CLK_SYS_DMA_BITS _u(0x00000080) -#define CLOCKS_ENABLED0_CLK_SYS_DMA_MSB _u(7) -#define CLOCKS_ENABLED0_CLK_SYS_DMA_LSB _u(7) -#define CLOCKS_ENABLED0_CLK_SYS_DMA_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_ENABLED0_CLK_SYS_BUSFABRIC -#define CLOCKS_ENABLED0_CLK_SYS_BUSFABRIC_RESET _u(0x0) -#define CLOCKS_ENABLED0_CLK_SYS_BUSFABRIC_BITS _u(0x00000040) -#define CLOCKS_ENABLED0_CLK_SYS_BUSFABRIC_MSB _u(6) -#define CLOCKS_ENABLED0_CLK_SYS_BUSFABRIC_LSB _u(6) -#define CLOCKS_ENABLED0_CLK_SYS_BUSFABRIC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_ENABLED0_CLK_SYS_BUSCTRL -#define CLOCKS_ENABLED0_CLK_SYS_BUSCTRL_RESET _u(0x0) -#define CLOCKS_ENABLED0_CLK_SYS_BUSCTRL_BITS _u(0x00000020) -#define CLOCKS_ENABLED0_CLK_SYS_BUSCTRL_MSB _u(5) -#define CLOCKS_ENABLED0_CLK_SYS_BUSCTRL_LSB _u(5) -#define CLOCKS_ENABLED0_CLK_SYS_BUSCTRL_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_ENABLED0_CLK_SYS_BOOTRAM -#define CLOCKS_ENABLED0_CLK_SYS_BOOTRAM_RESET _u(0x0) -#define CLOCKS_ENABLED0_CLK_SYS_BOOTRAM_BITS _u(0x00000010) -#define CLOCKS_ENABLED0_CLK_SYS_BOOTRAM_MSB _u(4) -#define CLOCKS_ENABLED0_CLK_SYS_BOOTRAM_LSB _u(4) -#define CLOCKS_ENABLED0_CLK_SYS_BOOTRAM_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_ENABLED0_CLK_SYS_ADC -#define CLOCKS_ENABLED0_CLK_SYS_ADC_RESET _u(0x0) -#define CLOCKS_ENABLED0_CLK_SYS_ADC_BITS _u(0x00000008) -#define CLOCKS_ENABLED0_CLK_SYS_ADC_MSB _u(3) -#define CLOCKS_ENABLED0_CLK_SYS_ADC_LSB _u(3) -#define CLOCKS_ENABLED0_CLK_SYS_ADC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_ENABLED0_CLK_ADC -#define CLOCKS_ENABLED0_CLK_ADC_RESET _u(0x0) -#define CLOCKS_ENABLED0_CLK_ADC_BITS _u(0x00000004) -#define CLOCKS_ENABLED0_CLK_ADC_MSB _u(2) -#define CLOCKS_ENABLED0_CLK_ADC_LSB _u(2) -#define CLOCKS_ENABLED0_CLK_ADC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_ENABLED0_CLK_SYS_ACCESSCTRL -#define CLOCKS_ENABLED0_CLK_SYS_ACCESSCTRL_RESET _u(0x0) -#define CLOCKS_ENABLED0_CLK_SYS_ACCESSCTRL_BITS _u(0x00000002) -#define CLOCKS_ENABLED0_CLK_SYS_ACCESSCTRL_MSB _u(1) -#define CLOCKS_ENABLED0_CLK_SYS_ACCESSCTRL_LSB _u(1) -#define CLOCKS_ENABLED0_CLK_SYS_ACCESSCTRL_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_ENABLED0_CLK_SYS_CLOCKS -#define CLOCKS_ENABLED0_CLK_SYS_CLOCKS_RESET _u(0x0) -#define CLOCKS_ENABLED0_CLK_SYS_CLOCKS_BITS _u(0x00000001) -#define CLOCKS_ENABLED0_CLK_SYS_CLOCKS_MSB _u(0) -#define CLOCKS_ENABLED0_CLK_SYS_CLOCKS_LSB _u(0) -#define CLOCKS_ENABLED0_CLK_SYS_CLOCKS_ACCESS "RO" -// ============================================================================= -// Register : CLOCKS_ENABLED1 -// Description : indicates the state of the clock enable -#define CLOCKS_ENABLED1_OFFSET _u(0x000000c0) -#define CLOCKS_ENABLED1_BITS _u(0x7fffffff) -#define CLOCKS_ENABLED1_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : CLOCKS_ENABLED1_CLK_SYS_XOSC -#define CLOCKS_ENABLED1_CLK_SYS_XOSC_RESET _u(0x0) -#define CLOCKS_ENABLED1_CLK_SYS_XOSC_BITS _u(0x40000000) -#define CLOCKS_ENABLED1_CLK_SYS_XOSC_MSB _u(30) -#define CLOCKS_ENABLED1_CLK_SYS_XOSC_LSB _u(30) -#define CLOCKS_ENABLED1_CLK_SYS_XOSC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_ENABLED1_CLK_SYS_XIP -#define CLOCKS_ENABLED1_CLK_SYS_XIP_RESET _u(0x0) -#define CLOCKS_ENABLED1_CLK_SYS_XIP_BITS _u(0x20000000) -#define CLOCKS_ENABLED1_CLK_SYS_XIP_MSB _u(29) -#define CLOCKS_ENABLED1_CLK_SYS_XIP_LSB _u(29) -#define CLOCKS_ENABLED1_CLK_SYS_XIP_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_ENABLED1_CLK_SYS_WATCHDOG -#define CLOCKS_ENABLED1_CLK_SYS_WATCHDOG_RESET _u(0x0) -#define CLOCKS_ENABLED1_CLK_SYS_WATCHDOG_BITS _u(0x10000000) -#define CLOCKS_ENABLED1_CLK_SYS_WATCHDOG_MSB _u(28) -#define CLOCKS_ENABLED1_CLK_SYS_WATCHDOG_LSB _u(28) -#define CLOCKS_ENABLED1_CLK_SYS_WATCHDOG_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_ENABLED1_CLK_USB -#define CLOCKS_ENABLED1_CLK_USB_RESET _u(0x0) -#define CLOCKS_ENABLED1_CLK_USB_BITS _u(0x08000000) -#define CLOCKS_ENABLED1_CLK_USB_MSB _u(27) -#define CLOCKS_ENABLED1_CLK_USB_LSB _u(27) -#define CLOCKS_ENABLED1_CLK_USB_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_ENABLED1_CLK_SYS_USBCTRL -#define CLOCKS_ENABLED1_CLK_SYS_USBCTRL_RESET _u(0x0) -#define CLOCKS_ENABLED1_CLK_SYS_USBCTRL_BITS _u(0x04000000) -#define CLOCKS_ENABLED1_CLK_SYS_USBCTRL_MSB _u(26) -#define CLOCKS_ENABLED1_CLK_SYS_USBCTRL_LSB _u(26) -#define CLOCKS_ENABLED1_CLK_SYS_USBCTRL_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_ENABLED1_CLK_SYS_UART1 -#define CLOCKS_ENABLED1_CLK_SYS_UART1_RESET _u(0x0) -#define CLOCKS_ENABLED1_CLK_SYS_UART1_BITS _u(0x02000000) -#define CLOCKS_ENABLED1_CLK_SYS_UART1_MSB _u(25) -#define CLOCKS_ENABLED1_CLK_SYS_UART1_LSB _u(25) -#define CLOCKS_ENABLED1_CLK_SYS_UART1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_ENABLED1_CLK_PERI_UART1 -#define CLOCKS_ENABLED1_CLK_PERI_UART1_RESET _u(0x0) -#define CLOCKS_ENABLED1_CLK_PERI_UART1_BITS _u(0x01000000) -#define CLOCKS_ENABLED1_CLK_PERI_UART1_MSB _u(24) -#define CLOCKS_ENABLED1_CLK_PERI_UART1_LSB _u(24) -#define CLOCKS_ENABLED1_CLK_PERI_UART1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_ENABLED1_CLK_SYS_UART0 -#define CLOCKS_ENABLED1_CLK_SYS_UART0_RESET _u(0x0) -#define CLOCKS_ENABLED1_CLK_SYS_UART0_BITS _u(0x00800000) -#define CLOCKS_ENABLED1_CLK_SYS_UART0_MSB _u(23) -#define CLOCKS_ENABLED1_CLK_SYS_UART0_LSB _u(23) -#define CLOCKS_ENABLED1_CLK_SYS_UART0_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_ENABLED1_CLK_PERI_UART0 -#define CLOCKS_ENABLED1_CLK_PERI_UART0_RESET _u(0x0) -#define CLOCKS_ENABLED1_CLK_PERI_UART0_BITS _u(0x00400000) -#define CLOCKS_ENABLED1_CLK_PERI_UART0_MSB _u(22) -#define CLOCKS_ENABLED1_CLK_PERI_UART0_LSB _u(22) -#define CLOCKS_ENABLED1_CLK_PERI_UART0_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_ENABLED1_CLK_SYS_TRNG -#define CLOCKS_ENABLED1_CLK_SYS_TRNG_RESET _u(0x0) -#define CLOCKS_ENABLED1_CLK_SYS_TRNG_BITS _u(0x00200000) -#define CLOCKS_ENABLED1_CLK_SYS_TRNG_MSB _u(21) -#define CLOCKS_ENABLED1_CLK_SYS_TRNG_LSB _u(21) -#define CLOCKS_ENABLED1_CLK_SYS_TRNG_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_ENABLED1_CLK_SYS_TIMER1 -#define CLOCKS_ENABLED1_CLK_SYS_TIMER1_RESET _u(0x0) -#define CLOCKS_ENABLED1_CLK_SYS_TIMER1_BITS _u(0x00100000) -#define CLOCKS_ENABLED1_CLK_SYS_TIMER1_MSB _u(20) -#define CLOCKS_ENABLED1_CLK_SYS_TIMER1_LSB _u(20) -#define CLOCKS_ENABLED1_CLK_SYS_TIMER1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_ENABLED1_CLK_SYS_TIMER0 -#define CLOCKS_ENABLED1_CLK_SYS_TIMER0_RESET _u(0x0) -#define CLOCKS_ENABLED1_CLK_SYS_TIMER0_BITS _u(0x00080000) -#define CLOCKS_ENABLED1_CLK_SYS_TIMER0_MSB _u(19) -#define CLOCKS_ENABLED1_CLK_SYS_TIMER0_LSB _u(19) -#define CLOCKS_ENABLED1_CLK_SYS_TIMER0_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_ENABLED1_CLK_SYS_TICKS -#define CLOCKS_ENABLED1_CLK_SYS_TICKS_RESET _u(0x0) -#define CLOCKS_ENABLED1_CLK_SYS_TICKS_BITS _u(0x00040000) -#define CLOCKS_ENABLED1_CLK_SYS_TICKS_MSB _u(18) -#define CLOCKS_ENABLED1_CLK_SYS_TICKS_LSB _u(18) -#define CLOCKS_ENABLED1_CLK_SYS_TICKS_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_ENABLED1_CLK_REF_TICKS -#define CLOCKS_ENABLED1_CLK_REF_TICKS_RESET _u(0x0) -#define CLOCKS_ENABLED1_CLK_REF_TICKS_BITS _u(0x00020000) -#define CLOCKS_ENABLED1_CLK_REF_TICKS_MSB _u(17) -#define CLOCKS_ENABLED1_CLK_REF_TICKS_LSB _u(17) -#define CLOCKS_ENABLED1_CLK_REF_TICKS_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_ENABLED1_CLK_SYS_TBMAN -#define CLOCKS_ENABLED1_CLK_SYS_TBMAN_RESET _u(0x0) -#define CLOCKS_ENABLED1_CLK_SYS_TBMAN_BITS _u(0x00010000) -#define CLOCKS_ENABLED1_CLK_SYS_TBMAN_MSB _u(16) -#define CLOCKS_ENABLED1_CLK_SYS_TBMAN_LSB _u(16) -#define CLOCKS_ENABLED1_CLK_SYS_TBMAN_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_ENABLED1_CLK_SYS_SYSINFO -#define CLOCKS_ENABLED1_CLK_SYS_SYSINFO_RESET _u(0x0) -#define CLOCKS_ENABLED1_CLK_SYS_SYSINFO_BITS _u(0x00008000) -#define CLOCKS_ENABLED1_CLK_SYS_SYSINFO_MSB _u(15) -#define CLOCKS_ENABLED1_CLK_SYS_SYSINFO_LSB _u(15) -#define CLOCKS_ENABLED1_CLK_SYS_SYSINFO_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_ENABLED1_CLK_SYS_SYSCFG -#define CLOCKS_ENABLED1_CLK_SYS_SYSCFG_RESET _u(0x0) -#define CLOCKS_ENABLED1_CLK_SYS_SYSCFG_BITS _u(0x00004000) -#define CLOCKS_ENABLED1_CLK_SYS_SYSCFG_MSB _u(14) -#define CLOCKS_ENABLED1_CLK_SYS_SYSCFG_LSB _u(14) -#define CLOCKS_ENABLED1_CLK_SYS_SYSCFG_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_ENABLED1_CLK_SYS_SRAM9 -#define CLOCKS_ENABLED1_CLK_SYS_SRAM9_RESET _u(0x0) -#define CLOCKS_ENABLED1_CLK_SYS_SRAM9_BITS _u(0x00002000) -#define CLOCKS_ENABLED1_CLK_SYS_SRAM9_MSB _u(13) -#define CLOCKS_ENABLED1_CLK_SYS_SRAM9_LSB _u(13) -#define CLOCKS_ENABLED1_CLK_SYS_SRAM9_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_ENABLED1_CLK_SYS_SRAM8 -#define CLOCKS_ENABLED1_CLK_SYS_SRAM8_RESET _u(0x0) -#define CLOCKS_ENABLED1_CLK_SYS_SRAM8_BITS _u(0x00001000) -#define CLOCKS_ENABLED1_CLK_SYS_SRAM8_MSB _u(12) -#define CLOCKS_ENABLED1_CLK_SYS_SRAM8_LSB _u(12) -#define CLOCKS_ENABLED1_CLK_SYS_SRAM8_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_ENABLED1_CLK_SYS_SRAM7 -#define CLOCKS_ENABLED1_CLK_SYS_SRAM7_RESET _u(0x0) -#define CLOCKS_ENABLED1_CLK_SYS_SRAM7_BITS _u(0x00000800) -#define CLOCKS_ENABLED1_CLK_SYS_SRAM7_MSB _u(11) -#define CLOCKS_ENABLED1_CLK_SYS_SRAM7_LSB _u(11) -#define CLOCKS_ENABLED1_CLK_SYS_SRAM7_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_ENABLED1_CLK_SYS_SRAM6 -#define CLOCKS_ENABLED1_CLK_SYS_SRAM6_RESET _u(0x0) -#define CLOCKS_ENABLED1_CLK_SYS_SRAM6_BITS _u(0x00000400) -#define CLOCKS_ENABLED1_CLK_SYS_SRAM6_MSB _u(10) -#define CLOCKS_ENABLED1_CLK_SYS_SRAM6_LSB _u(10) -#define CLOCKS_ENABLED1_CLK_SYS_SRAM6_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_ENABLED1_CLK_SYS_SRAM5 -#define CLOCKS_ENABLED1_CLK_SYS_SRAM5_RESET _u(0x0) -#define CLOCKS_ENABLED1_CLK_SYS_SRAM5_BITS _u(0x00000200) -#define CLOCKS_ENABLED1_CLK_SYS_SRAM5_MSB _u(9) -#define CLOCKS_ENABLED1_CLK_SYS_SRAM5_LSB _u(9) -#define CLOCKS_ENABLED1_CLK_SYS_SRAM5_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_ENABLED1_CLK_SYS_SRAM4 -#define CLOCKS_ENABLED1_CLK_SYS_SRAM4_RESET _u(0x0) -#define CLOCKS_ENABLED1_CLK_SYS_SRAM4_BITS _u(0x00000100) -#define CLOCKS_ENABLED1_CLK_SYS_SRAM4_MSB _u(8) -#define CLOCKS_ENABLED1_CLK_SYS_SRAM4_LSB _u(8) -#define CLOCKS_ENABLED1_CLK_SYS_SRAM4_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_ENABLED1_CLK_SYS_SRAM3 -#define CLOCKS_ENABLED1_CLK_SYS_SRAM3_RESET _u(0x0) -#define CLOCKS_ENABLED1_CLK_SYS_SRAM3_BITS _u(0x00000080) -#define CLOCKS_ENABLED1_CLK_SYS_SRAM3_MSB _u(7) -#define CLOCKS_ENABLED1_CLK_SYS_SRAM3_LSB _u(7) -#define CLOCKS_ENABLED1_CLK_SYS_SRAM3_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_ENABLED1_CLK_SYS_SRAM2 -#define CLOCKS_ENABLED1_CLK_SYS_SRAM2_RESET _u(0x0) -#define CLOCKS_ENABLED1_CLK_SYS_SRAM2_BITS _u(0x00000040) -#define CLOCKS_ENABLED1_CLK_SYS_SRAM2_MSB _u(6) -#define CLOCKS_ENABLED1_CLK_SYS_SRAM2_LSB _u(6) -#define CLOCKS_ENABLED1_CLK_SYS_SRAM2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_ENABLED1_CLK_SYS_SRAM1 -#define CLOCKS_ENABLED1_CLK_SYS_SRAM1_RESET _u(0x0) -#define CLOCKS_ENABLED1_CLK_SYS_SRAM1_BITS _u(0x00000020) -#define CLOCKS_ENABLED1_CLK_SYS_SRAM1_MSB _u(5) -#define CLOCKS_ENABLED1_CLK_SYS_SRAM1_LSB _u(5) -#define CLOCKS_ENABLED1_CLK_SYS_SRAM1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_ENABLED1_CLK_SYS_SRAM0 -#define CLOCKS_ENABLED1_CLK_SYS_SRAM0_RESET _u(0x0) -#define CLOCKS_ENABLED1_CLK_SYS_SRAM0_BITS _u(0x00000010) -#define CLOCKS_ENABLED1_CLK_SYS_SRAM0_MSB _u(4) -#define CLOCKS_ENABLED1_CLK_SYS_SRAM0_LSB _u(4) -#define CLOCKS_ENABLED1_CLK_SYS_SRAM0_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_ENABLED1_CLK_SYS_SPI1 -#define CLOCKS_ENABLED1_CLK_SYS_SPI1_RESET _u(0x0) -#define CLOCKS_ENABLED1_CLK_SYS_SPI1_BITS _u(0x00000008) -#define CLOCKS_ENABLED1_CLK_SYS_SPI1_MSB _u(3) -#define CLOCKS_ENABLED1_CLK_SYS_SPI1_LSB _u(3) -#define CLOCKS_ENABLED1_CLK_SYS_SPI1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_ENABLED1_CLK_PERI_SPI1 -#define CLOCKS_ENABLED1_CLK_PERI_SPI1_RESET _u(0x0) -#define CLOCKS_ENABLED1_CLK_PERI_SPI1_BITS _u(0x00000004) -#define CLOCKS_ENABLED1_CLK_PERI_SPI1_MSB _u(2) -#define CLOCKS_ENABLED1_CLK_PERI_SPI1_LSB _u(2) -#define CLOCKS_ENABLED1_CLK_PERI_SPI1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_ENABLED1_CLK_SYS_SPI0 -#define CLOCKS_ENABLED1_CLK_SYS_SPI0_RESET _u(0x0) -#define CLOCKS_ENABLED1_CLK_SYS_SPI0_BITS _u(0x00000002) -#define CLOCKS_ENABLED1_CLK_SYS_SPI0_MSB _u(1) -#define CLOCKS_ENABLED1_CLK_SYS_SPI0_LSB _u(1) -#define CLOCKS_ENABLED1_CLK_SYS_SPI0_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : CLOCKS_ENABLED1_CLK_PERI_SPI0 -#define CLOCKS_ENABLED1_CLK_PERI_SPI0_RESET _u(0x0) -#define CLOCKS_ENABLED1_CLK_PERI_SPI0_BITS _u(0x00000001) -#define CLOCKS_ENABLED1_CLK_PERI_SPI0_MSB _u(0) -#define CLOCKS_ENABLED1_CLK_PERI_SPI0_LSB _u(0) -#define CLOCKS_ENABLED1_CLK_PERI_SPI0_ACCESS "RO" -// ============================================================================= -// Register : CLOCKS_INTR -// Description : Raw Interrupts -#define CLOCKS_INTR_OFFSET _u(0x000000c4) -#define CLOCKS_INTR_BITS _u(0x00000001) -#define CLOCKS_INTR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : CLOCKS_INTR_CLK_SYS_RESUS -#define CLOCKS_INTR_CLK_SYS_RESUS_RESET _u(0x0) -#define CLOCKS_INTR_CLK_SYS_RESUS_BITS _u(0x00000001) -#define CLOCKS_INTR_CLK_SYS_RESUS_MSB _u(0) -#define CLOCKS_INTR_CLK_SYS_RESUS_LSB _u(0) -#define CLOCKS_INTR_CLK_SYS_RESUS_ACCESS "RO" -// ============================================================================= -// Register : CLOCKS_INTE -// Description : Interrupt Enable -#define CLOCKS_INTE_OFFSET _u(0x000000c8) -#define CLOCKS_INTE_BITS _u(0x00000001) -#define CLOCKS_INTE_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : CLOCKS_INTE_CLK_SYS_RESUS -#define CLOCKS_INTE_CLK_SYS_RESUS_RESET _u(0x0) -#define CLOCKS_INTE_CLK_SYS_RESUS_BITS _u(0x00000001) -#define CLOCKS_INTE_CLK_SYS_RESUS_MSB _u(0) -#define CLOCKS_INTE_CLK_SYS_RESUS_LSB _u(0) -#define CLOCKS_INTE_CLK_SYS_RESUS_ACCESS "RW" -// ============================================================================= -// Register : CLOCKS_INTF -// Description : Interrupt Force -#define CLOCKS_INTF_OFFSET _u(0x000000cc) -#define CLOCKS_INTF_BITS _u(0x00000001) -#define CLOCKS_INTF_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : CLOCKS_INTF_CLK_SYS_RESUS -#define CLOCKS_INTF_CLK_SYS_RESUS_RESET _u(0x0) -#define CLOCKS_INTF_CLK_SYS_RESUS_BITS _u(0x00000001) -#define CLOCKS_INTF_CLK_SYS_RESUS_MSB _u(0) -#define CLOCKS_INTF_CLK_SYS_RESUS_LSB _u(0) -#define CLOCKS_INTF_CLK_SYS_RESUS_ACCESS "RW" -// ============================================================================= -// Register : CLOCKS_INTS -// Description : Interrupt status after masking & forcing -#define CLOCKS_INTS_OFFSET _u(0x000000d0) -#define CLOCKS_INTS_BITS _u(0x00000001) -#define CLOCKS_INTS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : CLOCKS_INTS_CLK_SYS_RESUS -#define CLOCKS_INTS_CLK_SYS_RESUS_RESET _u(0x0) -#define CLOCKS_INTS_CLK_SYS_RESUS_BITS _u(0x00000001) -#define CLOCKS_INTS_CLK_SYS_RESUS_MSB _u(0) -#define CLOCKS_INTS_CLK_SYS_RESUS_LSB _u(0) -#define CLOCKS_INTS_CLK_SYS_RESUS_ACCESS "RO" -// ============================================================================= -#endif // _HARDWARE_REGS_CLOCKS_H - diff --git a/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/coresight_trace.h b/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/coresight_trace.h deleted file mode 100644 index cb4f990d7a..0000000000 --- a/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/coresight_trace.h +++ /dev/null @@ -1,85 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -// ============================================================================= -// Register block : CORESIGHT_TRACE -// Version : 1 -// Bus type : ahbl -// Description : Coresight block - RP specific registers -// ============================================================================= -#ifndef _HARDWARE_REGS_CORESIGHT_TRACE_H -#define _HARDWARE_REGS_CORESIGHT_TRACE_H -// ============================================================================= -// Register : CORESIGHT_TRACE_CTRL_STATUS -// Description : Control and status register -#define CORESIGHT_TRACE_CTRL_STATUS_OFFSET _u(0x00000000) -#define CORESIGHT_TRACE_CTRL_STATUS_BITS _u(0x00000003) -#define CORESIGHT_TRACE_CTRL_STATUS_RESET _u(0x00000001) -// ----------------------------------------------------------------------------- -// Field : CORESIGHT_TRACE_CTRL_STATUS_TRACE_CAPTURE_FIFO_OVERFLOW -// Description : This status flag is set high when trace data has been dropped -// due to the FIFO being full at the point trace data was sampled. -// Write 1 to acknowledge and clear the bit. -#define CORESIGHT_TRACE_CTRL_STATUS_TRACE_CAPTURE_FIFO_OVERFLOW_RESET _u(0x0) -#define CORESIGHT_TRACE_CTRL_STATUS_TRACE_CAPTURE_FIFO_OVERFLOW_BITS _u(0x00000002) -#define CORESIGHT_TRACE_CTRL_STATUS_TRACE_CAPTURE_FIFO_OVERFLOW_MSB _u(1) -#define CORESIGHT_TRACE_CTRL_STATUS_TRACE_CAPTURE_FIFO_OVERFLOW_LSB _u(1) -#define CORESIGHT_TRACE_CTRL_STATUS_TRACE_CAPTURE_FIFO_OVERFLOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : CORESIGHT_TRACE_CTRL_STATUS_TRACE_CAPTURE_FIFO_FLUSH -// Description : Set to 1 to continuously hold the trace FIFO in a flushed state -// and prevent overflow. -// -// Before clearing this flag, configure and start a DMA channel -// with the correct DREQ for the TRACE_CAPTURE_FIFO register. -// -// Clear this flag to begin sampling trace data, and set once -// again once the trace capture buffer is full. You must configure -// the TPIU in order to generate trace packets to be captured, as -// well as components like the ETM further upstream to generate -// the event stream propagated to the TPIU. -#define CORESIGHT_TRACE_CTRL_STATUS_TRACE_CAPTURE_FIFO_FLUSH_RESET _u(0x1) -#define CORESIGHT_TRACE_CTRL_STATUS_TRACE_CAPTURE_FIFO_FLUSH_BITS _u(0x00000001) -#define CORESIGHT_TRACE_CTRL_STATUS_TRACE_CAPTURE_FIFO_FLUSH_MSB _u(0) -#define CORESIGHT_TRACE_CTRL_STATUS_TRACE_CAPTURE_FIFO_FLUSH_LSB _u(0) -#define CORESIGHT_TRACE_CTRL_STATUS_TRACE_CAPTURE_FIFO_FLUSH_ACCESS "RW" -// ============================================================================= -// Register : CORESIGHT_TRACE_TRACE_CAPTURE_FIFO -// Description : FIFO for trace data captured from the TPIU -#define CORESIGHT_TRACE_TRACE_CAPTURE_FIFO_OFFSET _u(0x00000004) -#define CORESIGHT_TRACE_TRACE_CAPTURE_FIFO_BITS _u(0xffffffff) -#define CORESIGHT_TRACE_TRACE_CAPTURE_FIFO_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : CORESIGHT_TRACE_TRACE_CAPTURE_FIFO_RDATA -// Description : Read from an 8 x 32-bit FIFO containing trace data captured -// from the TPIU. -// -// Hardware pushes to the FIFO on rising edges of clk_sys, when -// either of the following is true: -// -// * TPIU TRACECTL output is low (normal trace data) -// -// * TPIU TRACETCL output is high, and TPIU TRACEDATA0 and -// TRACEDATA1 are both low (trigger packet) -// -// These conditions are in accordance with Arm Coresight -// Architecture Spec v3.0 section D3.3.3: Decoding requirements -// for Trace Capture Devices -// -// The data captured into the FIFO is the full 32-bit TRACEDATA -// bus output by the TPIU. Note that the TPIU is a DDR output at -// half of clk_sys, therefore this interface can capture the full -// 32-bit TPIU DDR output bandwidth as it samples once per active -// edge of the TPIU output clock. -#define CORESIGHT_TRACE_TRACE_CAPTURE_FIFO_RDATA_RESET _u(0x00000000) -#define CORESIGHT_TRACE_TRACE_CAPTURE_FIFO_RDATA_BITS _u(0xffffffff) -#define CORESIGHT_TRACE_TRACE_CAPTURE_FIFO_RDATA_MSB _u(31) -#define CORESIGHT_TRACE_TRACE_CAPTURE_FIFO_RDATA_LSB _u(0) -#define CORESIGHT_TRACE_TRACE_CAPTURE_FIFO_RDATA_ACCESS "RF" -// ============================================================================= -#endif // _HARDWARE_REGS_CORESIGHT_TRACE_H - diff --git a/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/dma.h b/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/dma.h deleted file mode 100644 index 00ecde1867..0000000000 --- a/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/dma.h +++ /dev/null @@ -1,9914 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -// ============================================================================= -// Register block : DMA -// Version : 1 -// Bus type : apb -// Description : DMA with separate read and write masters -// ============================================================================= -#ifndef _HARDWARE_REGS_DMA_H -#define _HARDWARE_REGS_DMA_H -// ============================================================================= -// Register : DMA_CH0_READ_ADDR -// Description : DMA Channel 0 Read Address pointer -// This register updates automatically each time a read completes. -// The current value is the next address to be read by this -// channel. -#define DMA_CH0_READ_ADDR_OFFSET _u(0x00000000) -#define DMA_CH0_READ_ADDR_BITS _u(0xffffffff) -#define DMA_CH0_READ_ADDR_RESET _u(0x00000000) -#define DMA_CH0_READ_ADDR_MSB _u(31) -#define DMA_CH0_READ_ADDR_LSB _u(0) -#define DMA_CH0_READ_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH0_WRITE_ADDR -// Description : DMA Channel 0 Write Address pointer -// This register updates automatically each time a write -// completes. The current value is the next address to be written -// by this channel. -#define DMA_CH0_WRITE_ADDR_OFFSET _u(0x00000004) -#define DMA_CH0_WRITE_ADDR_BITS _u(0xffffffff) -#define DMA_CH0_WRITE_ADDR_RESET _u(0x00000000) -#define DMA_CH0_WRITE_ADDR_MSB _u(31) -#define DMA_CH0_WRITE_ADDR_LSB _u(0) -#define DMA_CH0_WRITE_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH0_TRANS_COUNT -// Description : DMA Channel 0 Transfer Count -#define DMA_CH0_TRANS_COUNT_OFFSET _u(0x00000008) -#define DMA_CH0_TRANS_COUNT_BITS _u(0xffffffff) -#define DMA_CH0_TRANS_COUNT_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : DMA_CH0_TRANS_COUNT_MODE -// Description : When MODE is 0x0, the transfer count decrements with each -// transfer until 0, and then the channel triggers the next -// channel indicated by CTRL_CHAIN_TO. -// -// When MODE is 0x1, the transfer count decrements with each -// transfer until 0, and then the channel re-triggers itself, in -// addition to the trigger indicated by CTRL_CHAIN_TO. This is -// useful for e.g. an endless ring-buffer DMA with periodic -// interrupts. -// -// When MODE is 0xf, the transfer count does not decrement. The -// DMA channel performs an endless sequence of transfers, never -// triggering other channels or raising interrupts, until an ABORT -// is raised. -// -// All other values are reserved. -// 0x0 -> NORMAL -// 0x1 -> TRIGGER_SELF -// 0xf -> ENDLESS -#define DMA_CH0_TRANS_COUNT_MODE_RESET _u(0x0) -#define DMA_CH0_TRANS_COUNT_MODE_BITS _u(0xf0000000) -#define DMA_CH0_TRANS_COUNT_MODE_MSB _u(31) -#define DMA_CH0_TRANS_COUNT_MODE_LSB _u(28) -#define DMA_CH0_TRANS_COUNT_MODE_ACCESS "RW" -#define DMA_CH0_TRANS_COUNT_MODE_VALUE_NORMAL _u(0x0) -#define DMA_CH0_TRANS_COUNT_MODE_VALUE_TRIGGER_SELF _u(0x1) -#define DMA_CH0_TRANS_COUNT_MODE_VALUE_ENDLESS _u(0xf) -// ----------------------------------------------------------------------------- -// Field : DMA_CH0_TRANS_COUNT_COUNT -// Description : 28-bit transfer count (256 million transfers maximum). -// -// Program the number of bus transfers a channel will perform -// before halting. Note that, if transfers are larger than one -// byte in size, this is not equal to the number of bytes -// transferred (see CTRL_DATA_SIZE). -// -// When the channel is active, reading this register shows the -// number of transfers remaining, updating automatically each time -// a write transfer completes. -// -// Writing this register sets the RELOAD value for the transfer -// counter. Each time this channel is triggered, the RELOAD value -// is copied into the live transfer counter. The channel can be -// started multiple times, and will perform the same number of -// transfers each time, as programmed by most recent write. -// -// The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT -// is used as a trigger, the written value is used immediately as -// the length of the new transfer sequence, as well as being -// written to RELOAD. -#define DMA_CH0_TRANS_COUNT_COUNT_RESET _u(0x0000000) -#define DMA_CH0_TRANS_COUNT_COUNT_BITS _u(0x0fffffff) -#define DMA_CH0_TRANS_COUNT_COUNT_MSB _u(27) -#define DMA_CH0_TRANS_COUNT_COUNT_LSB _u(0) -#define DMA_CH0_TRANS_COUNT_COUNT_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH0_CTRL_TRIG -// Description : DMA Channel 0 Control and Status -#define DMA_CH0_CTRL_TRIG_OFFSET _u(0x0000000c) -#define DMA_CH0_CTRL_TRIG_BITS _u(0xe7ffffff) -#define DMA_CH0_CTRL_TRIG_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : DMA_CH0_CTRL_TRIG_AHB_ERROR -// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel -// halts when it encounters any bus error, and always raises its -// channel IRQ flag. -#define DMA_CH0_CTRL_TRIG_AHB_ERROR_RESET _u(0x0) -#define DMA_CH0_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000) -#define DMA_CH0_CTRL_TRIG_AHB_ERROR_MSB _u(31) -#define DMA_CH0_CTRL_TRIG_AHB_ERROR_LSB _u(31) -#define DMA_CH0_CTRL_TRIG_AHB_ERROR_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : DMA_CH0_CTRL_TRIG_READ_ERROR -// Description : If 1, the channel received a read bus error. Write one to -// clear. -// READ_ADDR shows the approximate address where the bus error was -// encountered (will not be earlier, or more than 3 transfers -// later) -#define DMA_CH0_CTRL_TRIG_READ_ERROR_RESET _u(0x0) -#define DMA_CH0_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000) -#define DMA_CH0_CTRL_TRIG_READ_ERROR_MSB _u(30) -#define DMA_CH0_CTRL_TRIG_READ_ERROR_LSB _u(30) -#define DMA_CH0_CTRL_TRIG_READ_ERROR_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : DMA_CH0_CTRL_TRIG_WRITE_ERROR -// Description : If 1, the channel received a write bus error. Write one to -// clear. -// WRITE_ADDR shows the approximate address where the bus error -// was encountered (will not be earlier, or more than 5 transfers -// later) -#define DMA_CH0_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0) -#define DMA_CH0_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000) -#define DMA_CH0_CTRL_TRIG_WRITE_ERROR_MSB _u(29) -#define DMA_CH0_CTRL_TRIG_WRITE_ERROR_LSB _u(29) -#define DMA_CH0_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : DMA_CH0_CTRL_TRIG_BUSY -// Description : This flag goes high when the channel starts a new transfer -// sequence, and low when the last transfer of that sequence -// completes. Clearing EN while BUSY is high pauses the channel, -// and BUSY will stay high while paused. -// -// To terminate a sequence early (and clear the BUSY flag), see -// CHAN_ABORT. -#define DMA_CH0_CTRL_TRIG_BUSY_RESET _u(0x0) -#define DMA_CH0_CTRL_TRIG_BUSY_BITS _u(0x04000000) -#define DMA_CH0_CTRL_TRIG_BUSY_MSB _u(26) -#define DMA_CH0_CTRL_TRIG_BUSY_LSB _u(26) -#define DMA_CH0_CTRL_TRIG_BUSY_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : DMA_CH0_CTRL_TRIG_SNIFF_EN -// Description : If 1, this channel's data transfers are visible to the sniff -// hardware, and each transfer will advance the state of the -// checksum. This only applies if the sniff hardware is enabled, -// and has this channel selected. -// -// This allows checksum to be enabled or disabled on a per- -// control- block basis. -#define DMA_CH0_CTRL_TRIG_SNIFF_EN_RESET _u(0x0) -#define DMA_CH0_CTRL_TRIG_SNIFF_EN_BITS _u(0x02000000) -#define DMA_CH0_CTRL_TRIG_SNIFF_EN_MSB _u(25) -#define DMA_CH0_CTRL_TRIG_SNIFF_EN_LSB _u(25) -#define DMA_CH0_CTRL_TRIG_SNIFF_EN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH0_CTRL_TRIG_BSWAP -// Description : Apply byte-swap transformation to DMA data. -// For byte data, this has no effect. For halfword data, the two -// bytes of each halfword are swapped. For word data, the four -// bytes of each word are swapped to reverse order. -#define DMA_CH0_CTRL_TRIG_BSWAP_RESET _u(0x0) -#define DMA_CH0_CTRL_TRIG_BSWAP_BITS _u(0x01000000) -#define DMA_CH0_CTRL_TRIG_BSWAP_MSB _u(24) -#define DMA_CH0_CTRL_TRIG_BSWAP_LSB _u(24) -#define DMA_CH0_CTRL_TRIG_BSWAP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH0_CTRL_TRIG_IRQ_QUIET -// Description : In QUIET mode, the channel does not generate IRQs at the end of -// every transfer block. Instead, an IRQ is raised when NULL is -// written to a trigger register, indicating the end of a control -// block chain. -// -// This reduces the number of interrupts to be serviced by the CPU -// when transferring a DMA chain of many small control blocks. -#define DMA_CH0_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0) -#define DMA_CH0_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00800000) -#define DMA_CH0_CTRL_TRIG_IRQ_QUIET_MSB _u(23) -#define DMA_CH0_CTRL_TRIG_IRQ_QUIET_LSB _u(23) -#define DMA_CH0_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH0_CTRL_TRIG_TREQ_SEL -// Description : Select a Transfer Request signal. -// The channel uses the transfer request signal to pace its data -// transfer rate. Sources for TREQ signals are internal (TIMERS) -// or external (DREQ, a Data Request from the system). -// 0x0 to 0x3a -> select DREQ n as TREQ -// 0x3b -> Select Timer 0 as TREQ -// 0x3c -> Select Timer 1 as TREQ -// 0x3d -> Select Timer 2 as TREQ (Optional) -// 0x3e -> Select Timer 3 as TREQ (Optional) -// 0x3f -> Permanent request, for unpaced transfers. -#define DMA_CH0_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) -#define DMA_CH0_CTRL_TRIG_TREQ_SEL_BITS _u(0x007e0000) -#define DMA_CH0_CTRL_TRIG_TREQ_SEL_MSB _u(22) -#define DMA_CH0_CTRL_TRIG_TREQ_SEL_LSB _u(17) -#define DMA_CH0_CTRL_TRIG_TREQ_SEL_ACCESS "RW" -#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) -#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) -#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) -#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) -#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) -// ----------------------------------------------------------------------------- -// Field : DMA_CH0_CTRL_TRIG_CHAIN_TO -// Description : When this channel completes, it will trigger the channel -// indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this -// channel)_. -// -// Note this field resets to 0, so channels 1 and above will chain -// to channel 0 by default. Set this field to avoid this -// behaviour. -#define DMA_CH0_CTRL_TRIG_CHAIN_TO_RESET _u(0x0) -#define DMA_CH0_CTRL_TRIG_CHAIN_TO_BITS _u(0x0001e000) -#define DMA_CH0_CTRL_TRIG_CHAIN_TO_MSB _u(16) -#define DMA_CH0_CTRL_TRIG_CHAIN_TO_LSB _u(13) -#define DMA_CH0_CTRL_TRIG_CHAIN_TO_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH0_CTRL_TRIG_RING_SEL -// Description : Select whether RING_SIZE applies to read or write addresses. -// If 0, read addresses are wrapped on a (1 << RING_SIZE) -// boundary. If 1, write addresses are wrapped. -#define DMA_CH0_CTRL_TRIG_RING_SEL_RESET _u(0x0) -#define DMA_CH0_CTRL_TRIG_RING_SEL_BITS _u(0x00001000) -#define DMA_CH0_CTRL_TRIG_RING_SEL_MSB _u(12) -#define DMA_CH0_CTRL_TRIG_RING_SEL_LSB _u(12) -#define DMA_CH0_CTRL_TRIG_RING_SEL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH0_CTRL_TRIG_RING_SIZE -// Description : Size of address wrap region. If 0, don't wrap. For values n > -// 0, only the lower n bits of the address will change. This wraps -// the address on a (1 << n) byte boundary, facilitating access to -// naturally-aligned ring buffers. -// -// Ring sizes between 2 and 32768 bytes are possible. This can -// apply to either read or write addresses, based on value of -// RING_SEL. -// 0x0 -> RING_NONE -#define DMA_CH0_CTRL_TRIG_RING_SIZE_RESET _u(0x0) -#define DMA_CH0_CTRL_TRIG_RING_SIZE_BITS _u(0x00000f00) -#define DMA_CH0_CTRL_TRIG_RING_SIZE_MSB _u(11) -#define DMA_CH0_CTRL_TRIG_RING_SIZE_LSB _u(8) -#define DMA_CH0_CTRL_TRIG_RING_SIZE_ACCESS "RW" -#define DMA_CH0_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0) -// ----------------------------------------------------------------------------- -// Field : DMA_CH0_CTRL_TRIG_INCR_WRITE_REV -// Description : If 1, and INCR_WRITE is 1, the write address is decremented -// rather than incremented with each transfer. -// -// If 1, and INCR_WRITE is 0, this otherwise-unused combination -// causes the write address to be incremented by twice the -// transfer size, i.e. skipping over alternate addresses. -#define DMA_CH0_CTRL_TRIG_INCR_WRITE_REV_RESET _u(0x0) -#define DMA_CH0_CTRL_TRIG_INCR_WRITE_REV_BITS _u(0x00000080) -#define DMA_CH0_CTRL_TRIG_INCR_WRITE_REV_MSB _u(7) -#define DMA_CH0_CTRL_TRIG_INCR_WRITE_REV_LSB _u(7) -#define DMA_CH0_CTRL_TRIG_INCR_WRITE_REV_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH0_CTRL_TRIG_INCR_WRITE -// Description : If 1, the write address increments with each transfer. If 0, -// each write is directed to the same, initial address. -// -// Generally this should be disabled for memory-to-peripheral -// transfers. -#define DMA_CH0_CTRL_TRIG_INCR_WRITE_RESET _u(0x0) -#define DMA_CH0_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000040) -#define DMA_CH0_CTRL_TRIG_INCR_WRITE_MSB _u(6) -#define DMA_CH0_CTRL_TRIG_INCR_WRITE_LSB _u(6) -#define DMA_CH0_CTRL_TRIG_INCR_WRITE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH0_CTRL_TRIG_INCR_READ_REV -// Description : If 1, and INCR_READ is 1, the read address is decremented -// rather than incremented with each transfer. -// -// If 1, and INCR_READ is 0, this otherwise-unused combination -// causes the read address to be incremented by twice the transfer -// size, i.e. skipping over alternate addresses. -#define DMA_CH0_CTRL_TRIG_INCR_READ_REV_RESET _u(0x0) -#define DMA_CH0_CTRL_TRIG_INCR_READ_REV_BITS _u(0x00000020) -#define DMA_CH0_CTRL_TRIG_INCR_READ_REV_MSB _u(5) -#define DMA_CH0_CTRL_TRIG_INCR_READ_REV_LSB _u(5) -#define DMA_CH0_CTRL_TRIG_INCR_READ_REV_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH0_CTRL_TRIG_INCR_READ -// Description : If 1, the read address increments with each transfer. If 0, -// each read is directed to the same, initial address. -// -// Generally this should be disabled for peripheral-to-memory -// transfers. -#define DMA_CH0_CTRL_TRIG_INCR_READ_RESET _u(0x0) -#define DMA_CH0_CTRL_TRIG_INCR_READ_BITS _u(0x00000010) -#define DMA_CH0_CTRL_TRIG_INCR_READ_MSB _u(4) -#define DMA_CH0_CTRL_TRIG_INCR_READ_LSB _u(4) -#define DMA_CH0_CTRL_TRIG_INCR_READ_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH0_CTRL_TRIG_DATA_SIZE -// Description : Set the size of each bus transfer (byte/halfword/word). -// READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) -// with each transfer. -// 0x0 -> SIZE_BYTE -// 0x1 -> SIZE_HALFWORD -// 0x2 -> SIZE_WORD -#define DMA_CH0_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) -#define DMA_CH0_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) -#define DMA_CH0_CTRL_TRIG_DATA_SIZE_MSB _u(3) -#define DMA_CH0_CTRL_TRIG_DATA_SIZE_LSB _u(2) -#define DMA_CH0_CTRL_TRIG_DATA_SIZE_ACCESS "RW" -#define DMA_CH0_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) -#define DMA_CH0_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1) -#define DMA_CH0_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) -// ----------------------------------------------------------------------------- -// Field : DMA_CH0_CTRL_TRIG_HIGH_PRIORITY -// Description : HIGH_PRIORITY gives a channel preferential treatment in issue -// scheduling: in each scheduling round, all high priority -// channels are considered first, and then only a single low -// priority channel, before returning to the high priority -// channels. -// -// This only affects the order in which the DMA schedules -// channels. The DMA's bus priority is not changed. If the DMA is -// not saturated then a low priority channel will see no loss of -// throughput. -#define DMA_CH0_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0) -#define DMA_CH0_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002) -#define DMA_CH0_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1) -#define DMA_CH0_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1) -#define DMA_CH0_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH0_CTRL_TRIG_EN -// Description : DMA Channel Enable. -// When 1, the channel will respond to triggering events, which -// will cause it to become BUSY and start transferring data. When -// 0, the channel will ignore triggers, stop issuing transfers, -// and pause the current transfer sequence (i.e. BUSY will remain -// high if already high) -#define DMA_CH0_CTRL_TRIG_EN_RESET _u(0x0) -#define DMA_CH0_CTRL_TRIG_EN_BITS _u(0x00000001) -#define DMA_CH0_CTRL_TRIG_EN_MSB _u(0) -#define DMA_CH0_CTRL_TRIG_EN_LSB _u(0) -#define DMA_CH0_CTRL_TRIG_EN_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH0_AL1_CTRL -// Description : Alias for channel 0 CTRL register -#define DMA_CH0_AL1_CTRL_OFFSET _u(0x00000010) -#define DMA_CH0_AL1_CTRL_BITS _u(0xffffffff) -#define DMA_CH0_AL1_CTRL_RESET "-" -#define DMA_CH0_AL1_CTRL_MSB _u(31) -#define DMA_CH0_AL1_CTRL_LSB _u(0) -#define DMA_CH0_AL1_CTRL_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH0_AL1_READ_ADDR -// Description : Alias for channel 0 READ_ADDR register -#define DMA_CH0_AL1_READ_ADDR_OFFSET _u(0x00000014) -#define DMA_CH0_AL1_READ_ADDR_BITS _u(0xffffffff) -#define DMA_CH0_AL1_READ_ADDR_RESET "-" -#define DMA_CH0_AL1_READ_ADDR_MSB _u(31) -#define DMA_CH0_AL1_READ_ADDR_LSB _u(0) -#define DMA_CH0_AL1_READ_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH0_AL1_WRITE_ADDR -// Description : Alias for channel 0 WRITE_ADDR register -#define DMA_CH0_AL1_WRITE_ADDR_OFFSET _u(0x00000018) -#define DMA_CH0_AL1_WRITE_ADDR_BITS _u(0xffffffff) -#define DMA_CH0_AL1_WRITE_ADDR_RESET "-" -#define DMA_CH0_AL1_WRITE_ADDR_MSB _u(31) -#define DMA_CH0_AL1_WRITE_ADDR_LSB _u(0) -#define DMA_CH0_AL1_WRITE_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH0_AL1_TRANS_COUNT_TRIG -// Description : Alias for channel 0 TRANS_COUNT register -// This is a trigger register (0xc). Writing a nonzero value will -// reload the channel counter and start the channel. -#define DMA_CH0_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x0000001c) -#define DMA_CH0_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff) -#define DMA_CH0_AL1_TRANS_COUNT_TRIG_RESET "-" -#define DMA_CH0_AL1_TRANS_COUNT_TRIG_MSB _u(31) -#define DMA_CH0_AL1_TRANS_COUNT_TRIG_LSB _u(0) -#define DMA_CH0_AL1_TRANS_COUNT_TRIG_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH0_AL2_CTRL -// Description : Alias for channel 0 CTRL register -#define DMA_CH0_AL2_CTRL_OFFSET _u(0x00000020) -#define DMA_CH0_AL2_CTRL_BITS _u(0xffffffff) -#define DMA_CH0_AL2_CTRL_RESET "-" -#define DMA_CH0_AL2_CTRL_MSB _u(31) -#define DMA_CH0_AL2_CTRL_LSB _u(0) -#define DMA_CH0_AL2_CTRL_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH0_AL2_TRANS_COUNT -// Description : Alias for channel 0 TRANS_COUNT register -#define DMA_CH0_AL2_TRANS_COUNT_OFFSET _u(0x00000024) -#define DMA_CH0_AL2_TRANS_COUNT_BITS _u(0xffffffff) -#define DMA_CH0_AL2_TRANS_COUNT_RESET "-" -#define DMA_CH0_AL2_TRANS_COUNT_MSB _u(31) -#define DMA_CH0_AL2_TRANS_COUNT_LSB _u(0) -#define DMA_CH0_AL2_TRANS_COUNT_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH0_AL2_READ_ADDR -// Description : Alias for channel 0 READ_ADDR register -#define DMA_CH0_AL2_READ_ADDR_OFFSET _u(0x00000028) -#define DMA_CH0_AL2_READ_ADDR_BITS _u(0xffffffff) -#define DMA_CH0_AL2_READ_ADDR_RESET "-" -#define DMA_CH0_AL2_READ_ADDR_MSB _u(31) -#define DMA_CH0_AL2_READ_ADDR_LSB _u(0) -#define DMA_CH0_AL2_READ_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH0_AL2_WRITE_ADDR_TRIG -// Description : Alias for channel 0 WRITE_ADDR register -// This is a trigger register (0xc). Writing a nonzero value will -// reload the channel counter and start the channel. -#define DMA_CH0_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x0000002c) -#define DMA_CH0_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff) -#define DMA_CH0_AL2_WRITE_ADDR_TRIG_RESET "-" -#define DMA_CH0_AL2_WRITE_ADDR_TRIG_MSB _u(31) -#define DMA_CH0_AL2_WRITE_ADDR_TRIG_LSB _u(0) -#define DMA_CH0_AL2_WRITE_ADDR_TRIG_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH0_AL3_CTRL -// Description : Alias for channel 0 CTRL register -#define DMA_CH0_AL3_CTRL_OFFSET _u(0x00000030) -#define DMA_CH0_AL3_CTRL_BITS _u(0xffffffff) -#define DMA_CH0_AL3_CTRL_RESET "-" -#define DMA_CH0_AL3_CTRL_MSB _u(31) -#define DMA_CH0_AL3_CTRL_LSB _u(0) -#define DMA_CH0_AL3_CTRL_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH0_AL3_WRITE_ADDR -// Description : Alias for channel 0 WRITE_ADDR register -#define DMA_CH0_AL3_WRITE_ADDR_OFFSET _u(0x00000034) -#define DMA_CH0_AL3_WRITE_ADDR_BITS _u(0xffffffff) -#define DMA_CH0_AL3_WRITE_ADDR_RESET "-" -#define DMA_CH0_AL3_WRITE_ADDR_MSB _u(31) -#define DMA_CH0_AL3_WRITE_ADDR_LSB _u(0) -#define DMA_CH0_AL3_WRITE_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH0_AL3_TRANS_COUNT -// Description : Alias for channel 0 TRANS_COUNT register -#define DMA_CH0_AL3_TRANS_COUNT_OFFSET _u(0x00000038) -#define DMA_CH0_AL3_TRANS_COUNT_BITS _u(0xffffffff) -#define DMA_CH0_AL3_TRANS_COUNT_RESET "-" -#define DMA_CH0_AL3_TRANS_COUNT_MSB _u(31) -#define DMA_CH0_AL3_TRANS_COUNT_LSB _u(0) -#define DMA_CH0_AL3_TRANS_COUNT_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH0_AL3_READ_ADDR_TRIG -// Description : Alias for channel 0 READ_ADDR register -// This is a trigger register (0xc). Writing a nonzero value will -// reload the channel counter and start the channel. -#define DMA_CH0_AL3_READ_ADDR_TRIG_OFFSET _u(0x0000003c) -#define DMA_CH0_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff) -#define DMA_CH0_AL3_READ_ADDR_TRIG_RESET "-" -#define DMA_CH0_AL3_READ_ADDR_TRIG_MSB _u(31) -#define DMA_CH0_AL3_READ_ADDR_TRIG_LSB _u(0) -#define DMA_CH0_AL3_READ_ADDR_TRIG_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH1_READ_ADDR -// Description : DMA Channel 1 Read Address pointer -// This register updates automatically each time a read completes. -// The current value is the next address to be read by this -// channel. -#define DMA_CH1_READ_ADDR_OFFSET _u(0x00000040) -#define DMA_CH1_READ_ADDR_BITS _u(0xffffffff) -#define DMA_CH1_READ_ADDR_RESET _u(0x00000000) -#define DMA_CH1_READ_ADDR_MSB _u(31) -#define DMA_CH1_READ_ADDR_LSB _u(0) -#define DMA_CH1_READ_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH1_WRITE_ADDR -// Description : DMA Channel 1 Write Address pointer -// This register updates automatically each time a write -// completes. The current value is the next address to be written -// by this channel. -#define DMA_CH1_WRITE_ADDR_OFFSET _u(0x00000044) -#define DMA_CH1_WRITE_ADDR_BITS _u(0xffffffff) -#define DMA_CH1_WRITE_ADDR_RESET _u(0x00000000) -#define DMA_CH1_WRITE_ADDR_MSB _u(31) -#define DMA_CH1_WRITE_ADDR_LSB _u(0) -#define DMA_CH1_WRITE_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH1_TRANS_COUNT -// Description : DMA Channel 1 Transfer Count -#define DMA_CH1_TRANS_COUNT_OFFSET _u(0x00000048) -#define DMA_CH1_TRANS_COUNT_BITS _u(0xffffffff) -#define DMA_CH1_TRANS_COUNT_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : DMA_CH1_TRANS_COUNT_MODE -// Description : When MODE is 0x0, the transfer count decrements with each -// transfer until 0, and then the channel triggers the next -// channel indicated by CTRL_CHAIN_TO. -// -// When MODE is 0x1, the transfer count decrements with each -// transfer until 0, and then the channel re-triggers itself, in -// addition to the trigger indicated by CTRL_CHAIN_TO. This is -// useful for e.g. an endless ring-buffer DMA with periodic -// interrupts. -// -// When MODE is 0xf, the transfer count does not decrement. The -// DMA channel performs an endless sequence of transfers, never -// triggering other channels or raising interrupts, until an ABORT -// is raised. -// -// All other values are reserved. -// 0x0 -> NORMAL -// 0x1 -> TRIGGER_SELF -// 0xf -> ENDLESS -#define DMA_CH1_TRANS_COUNT_MODE_RESET _u(0x0) -#define DMA_CH1_TRANS_COUNT_MODE_BITS _u(0xf0000000) -#define DMA_CH1_TRANS_COUNT_MODE_MSB _u(31) -#define DMA_CH1_TRANS_COUNT_MODE_LSB _u(28) -#define DMA_CH1_TRANS_COUNT_MODE_ACCESS "RW" -#define DMA_CH1_TRANS_COUNT_MODE_VALUE_NORMAL _u(0x0) -#define DMA_CH1_TRANS_COUNT_MODE_VALUE_TRIGGER_SELF _u(0x1) -#define DMA_CH1_TRANS_COUNT_MODE_VALUE_ENDLESS _u(0xf) -// ----------------------------------------------------------------------------- -// Field : DMA_CH1_TRANS_COUNT_COUNT -// Description : 28-bit transfer count (256 million transfers maximum). -// -// Program the number of bus transfers a channel will perform -// before halting. Note that, if transfers are larger than one -// byte in size, this is not equal to the number of bytes -// transferred (see CTRL_DATA_SIZE). -// -// When the channel is active, reading this register shows the -// number of transfers remaining, updating automatically each time -// a write transfer completes. -// -// Writing this register sets the RELOAD value for the transfer -// counter. Each time this channel is triggered, the RELOAD value -// is copied into the live transfer counter. The channel can be -// started multiple times, and will perform the same number of -// transfers each time, as programmed by most recent write. -// -// The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT -// is used as a trigger, the written value is used immediately as -// the length of the new transfer sequence, as well as being -// written to RELOAD. -#define DMA_CH1_TRANS_COUNT_COUNT_RESET _u(0x0000000) -#define DMA_CH1_TRANS_COUNT_COUNT_BITS _u(0x0fffffff) -#define DMA_CH1_TRANS_COUNT_COUNT_MSB _u(27) -#define DMA_CH1_TRANS_COUNT_COUNT_LSB _u(0) -#define DMA_CH1_TRANS_COUNT_COUNT_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH1_CTRL_TRIG -// Description : DMA Channel 1 Control and Status -#define DMA_CH1_CTRL_TRIG_OFFSET _u(0x0000004c) -#define DMA_CH1_CTRL_TRIG_BITS _u(0xe7ffffff) -#define DMA_CH1_CTRL_TRIG_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : DMA_CH1_CTRL_TRIG_AHB_ERROR -// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel -// halts when it encounters any bus error, and always raises its -// channel IRQ flag. -#define DMA_CH1_CTRL_TRIG_AHB_ERROR_RESET _u(0x0) -#define DMA_CH1_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000) -#define DMA_CH1_CTRL_TRIG_AHB_ERROR_MSB _u(31) -#define DMA_CH1_CTRL_TRIG_AHB_ERROR_LSB _u(31) -#define DMA_CH1_CTRL_TRIG_AHB_ERROR_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : DMA_CH1_CTRL_TRIG_READ_ERROR -// Description : If 1, the channel received a read bus error. Write one to -// clear. -// READ_ADDR shows the approximate address where the bus error was -// encountered (will not be earlier, or more than 3 transfers -// later) -#define DMA_CH1_CTRL_TRIG_READ_ERROR_RESET _u(0x0) -#define DMA_CH1_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000) -#define DMA_CH1_CTRL_TRIG_READ_ERROR_MSB _u(30) -#define DMA_CH1_CTRL_TRIG_READ_ERROR_LSB _u(30) -#define DMA_CH1_CTRL_TRIG_READ_ERROR_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : DMA_CH1_CTRL_TRIG_WRITE_ERROR -// Description : If 1, the channel received a write bus error. Write one to -// clear. -// WRITE_ADDR shows the approximate address where the bus error -// was encountered (will not be earlier, or more than 5 transfers -// later) -#define DMA_CH1_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0) -#define DMA_CH1_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000) -#define DMA_CH1_CTRL_TRIG_WRITE_ERROR_MSB _u(29) -#define DMA_CH1_CTRL_TRIG_WRITE_ERROR_LSB _u(29) -#define DMA_CH1_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : DMA_CH1_CTRL_TRIG_BUSY -// Description : This flag goes high when the channel starts a new transfer -// sequence, and low when the last transfer of that sequence -// completes. Clearing EN while BUSY is high pauses the channel, -// and BUSY will stay high while paused. -// -// To terminate a sequence early (and clear the BUSY flag), see -// CHAN_ABORT. -#define DMA_CH1_CTRL_TRIG_BUSY_RESET _u(0x0) -#define DMA_CH1_CTRL_TRIG_BUSY_BITS _u(0x04000000) -#define DMA_CH1_CTRL_TRIG_BUSY_MSB _u(26) -#define DMA_CH1_CTRL_TRIG_BUSY_LSB _u(26) -#define DMA_CH1_CTRL_TRIG_BUSY_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : DMA_CH1_CTRL_TRIG_SNIFF_EN -// Description : If 1, this channel's data transfers are visible to the sniff -// hardware, and each transfer will advance the state of the -// checksum. This only applies if the sniff hardware is enabled, -// and has this channel selected. -// -// This allows checksum to be enabled or disabled on a per- -// control- block basis. -#define DMA_CH1_CTRL_TRIG_SNIFF_EN_RESET _u(0x0) -#define DMA_CH1_CTRL_TRIG_SNIFF_EN_BITS _u(0x02000000) -#define DMA_CH1_CTRL_TRIG_SNIFF_EN_MSB _u(25) -#define DMA_CH1_CTRL_TRIG_SNIFF_EN_LSB _u(25) -#define DMA_CH1_CTRL_TRIG_SNIFF_EN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH1_CTRL_TRIG_BSWAP -// Description : Apply byte-swap transformation to DMA data. -// For byte data, this has no effect. For halfword data, the two -// bytes of each halfword are swapped. For word data, the four -// bytes of each word are swapped to reverse order. -#define DMA_CH1_CTRL_TRIG_BSWAP_RESET _u(0x0) -#define DMA_CH1_CTRL_TRIG_BSWAP_BITS _u(0x01000000) -#define DMA_CH1_CTRL_TRIG_BSWAP_MSB _u(24) -#define DMA_CH1_CTRL_TRIG_BSWAP_LSB _u(24) -#define DMA_CH1_CTRL_TRIG_BSWAP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH1_CTRL_TRIG_IRQ_QUIET -// Description : In QUIET mode, the channel does not generate IRQs at the end of -// every transfer block. Instead, an IRQ is raised when NULL is -// written to a trigger register, indicating the end of a control -// block chain. -// -// This reduces the number of interrupts to be serviced by the CPU -// when transferring a DMA chain of many small control blocks. -#define DMA_CH1_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0) -#define DMA_CH1_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00800000) -#define DMA_CH1_CTRL_TRIG_IRQ_QUIET_MSB _u(23) -#define DMA_CH1_CTRL_TRIG_IRQ_QUIET_LSB _u(23) -#define DMA_CH1_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH1_CTRL_TRIG_TREQ_SEL -// Description : Select a Transfer Request signal. -// The channel uses the transfer request signal to pace its data -// transfer rate. Sources for TREQ signals are internal (TIMERS) -// or external (DREQ, a Data Request from the system). -// 0x0 to 0x3a -> select DREQ n as TREQ -// 0x3b -> Select Timer 0 as TREQ -// 0x3c -> Select Timer 1 as TREQ -// 0x3d -> Select Timer 2 as TREQ (Optional) -// 0x3e -> Select Timer 3 as TREQ (Optional) -// 0x3f -> Permanent request, for unpaced transfers. -#define DMA_CH1_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) -#define DMA_CH1_CTRL_TRIG_TREQ_SEL_BITS _u(0x007e0000) -#define DMA_CH1_CTRL_TRIG_TREQ_SEL_MSB _u(22) -#define DMA_CH1_CTRL_TRIG_TREQ_SEL_LSB _u(17) -#define DMA_CH1_CTRL_TRIG_TREQ_SEL_ACCESS "RW" -#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) -#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) -#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) -#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) -#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) -// ----------------------------------------------------------------------------- -// Field : DMA_CH1_CTRL_TRIG_CHAIN_TO -// Description : When this channel completes, it will trigger the channel -// indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this -// channel)_. -// -// Note this field resets to 0, so channels 1 and above will chain -// to channel 0 by default. Set this field to avoid this -// behaviour. -#define DMA_CH1_CTRL_TRIG_CHAIN_TO_RESET _u(0x0) -#define DMA_CH1_CTRL_TRIG_CHAIN_TO_BITS _u(0x0001e000) -#define DMA_CH1_CTRL_TRIG_CHAIN_TO_MSB _u(16) -#define DMA_CH1_CTRL_TRIG_CHAIN_TO_LSB _u(13) -#define DMA_CH1_CTRL_TRIG_CHAIN_TO_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH1_CTRL_TRIG_RING_SEL -// Description : Select whether RING_SIZE applies to read or write addresses. -// If 0, read addresses are wrapped on a (1 << RING_SIZE) -// boundary. If 1, write addresses are wrapped. -#define DMA_CH1_CTRL_TRIG_RING_SEL_RESET _u(0x0) -#define DMA_CH1_CTRL_TRIG_RING_SEL_BITS _u(0x00001000) -#define DMA_CH1_CTRL_TRIG_RING_SEL_MSB _u(12) -#define DMA_CH1_CTRL_TRIG_RING_SEL_LSB _u(12) -#define DMA_CH1_CTRL_TRIG_RING_SEL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH1_CTRL_TRIG_RING_SIZE -// Description : Size of address wrap region. If 0, don't wrap. For values n > -// 0, only the lower n bits of the address will change. This wraps -// the address on a (1 << n) byte boundary, facilitating access to -// naturally-aligned ring buffers. -// -// Ring sizes between 2 and 32768 bytes are possible. This can -// apply to either read or write addresses, based on value of -// RING_SEL. -// 0x0 -> RING_NONE -#define DMA_CH1_CTRL_TRIG_RING_SIZE_RESET _u(0x0) -#define DMA_CH1_CTRL_TRIG_RING_SIZE_BITS _u(0x00000f00) -#define DMA_CH1_CTRL_TRIG_RING_SIZE_MSB _u(11) -#define DMA_CH1_CTRL_TRIG_RING_SIZE_LSB _u(8) -#define DMA_CH1_CTRL_TRIG_RING_SIZE_ACCESS "RW" -#define DMA_CH1_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0) -// ----------------------------------------------------------------------------- -// Field : DMA_CH1_CTRL_TRIG_INCR_WRITE_REV -// Description : If 1, and INCR_WRITE is 1, the write address is decremented -// rather than incremented with each transfer. -// -// If 1, and INCR_WRITE is 0, this otherwise-unused combination -// causes the write address to be incremented by twice the -// transfer size, i.e. skipping over alternate addresses. -#define DMA_CH1_CTRL_TRIG_INCR_WRITE_REV_RESET _u(0x0) -#define DMA_CH1_CTRL_TRIG_INCR_WRITE_REV_BITS _u(0x00000080) -#define DMA_CH1_CTRL_TRIG_INCR_WRITE_REV_MSB _u(7) -#define DMA_CH1_CTRL_TRIG_INCR_WRITE_REV_LSB _u(7) -#define DMA_CH1_CTRL_TRIG_INCR_WRITE_REV_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH1_CTRL_TRIG_INCR_WRITE -// Description : If 1, the write address increments with each transfer. If 0, -// each write is directed to the same, initial address. -// -// Generally this should be disabled for memory-to-peripheral -// transfers. -#define DMA_CH1_CTRL_TRIG_INCR_WRITE_RESET _u(0x0) -#define DMA_CH1_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000040) -#define DMA_CH1_CTRL_TRIG_INCR_WRITE_MSB _u(6) -#define DMA_CH1_CTRL_TRIG_INCR_WRITE_LSB _u(6) -#define DMA_CH1_CTRL_TRIG_INCR_WRITE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH1_CTRL_TRIG_INCR_READ_REV -// Description : If 1, and INCR_READ is 1, the read address is decremented -// rather than incremented with each transfer. -// -// If 1, and INCR_READ is 0, this otherwise-unused combination -// causes the read address to be incremented by twice the transfer -// size, i.e. skipping over alternate addresses. -#define DMA_CH1_CTRL_TRIG_INCR_READ_REV_RESET _u(0x0) -#define DMA_CH1_CTRL_TRIG_INCR_READ_REV_BITS _u(0x00000020) -#define DMA_CH1_CTRL_TRIG_INCR_READ_REV_MSB _u(5) -#define DMA_CH1_CTRL_TRIG_INCR_READ_REV_LSB _u(5) -#define DMA_CH1_CTRL_TRIG_INCR_READ_REV_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH1_CTRL_TRIG_INCR_READ -// Description : If 1, the read address increments with each transfer. If 0, -// each read is directed to the same, initial address. -// -// Generally this should be disabled for peripheral-to-memory -// transfers. -#define DMA_CH1_CTRL_TRIG_INCR_READ_RESET _u(0x0) -#define DMA_CH1_CTRL_TRIG_INCR_READ_BITS _u(0x00000010) -#define DMA_CH1_CTRL_TRIG_INCR_READ_MSB _u(4) -#define DMA_CH1_CTRL_TRIG_INCR_READ_LSB _u(4) -#define DMA_CH1_CTRL_TRIG_INCR_READ_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH1_CTRL_TRIG_DATA_SIZE -// Description : Set the size of each bus transfer (byte/halfword/word). -// READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) -// with each transfer. -// 0x0 -> SIZE_BYTE -// 0x1 -> SIZE_HALFWORD -// 0x2 -> SIZE_WORD -#define DMA_CH1_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) -#define DMA_CH1_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) -#define DMA_CH1_CTRL_TRIG_DATA_SIZE_MSB _u(3) -#define DMA_CH1_CTRL_TRIG_DATA_SIZE_LSB _u(2) -#define DMA_CH1_CTRL_TRIG_DATA_SIZE_ACCESS "RW" -#define DMA_CH1_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) -#define DMA_CH1_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1) -#define DMA_CH1_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) -// ----------------------------------------------------------------------------- -// Field : DMA_CH1_CTRL_TRIG_HIGH_PRIORITY -// Description : HIGH_PRIORITY gives a channel preferential treatment in issue -// scheduling: in each scheduling round, all high priority -// channels are considered first, and then only a single low -// priority channel, before returning to the high priority -// channels. -// -// This only affects the order in which the DMA schedules -// channels. The DMA's bus priority is not changed. If the DMA is -// not saturated then a low priority channel will see no loss of -// throughput. -#define DMA_CH1_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0) -#define DMA_CH1_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002) -#define DMA_CH1_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1) -#define DMA_CH1_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1) -#define DMA_CH1_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH1_CTRL_TRIG_EN -// Description : DMA Channel Enable. -// When 1, the channel will respond to triggering events, which -// will cause it to become BUSY and start transferring data. When -// 0, the channel will ignore triggers, stop issuing transfers, -// and pause the current transfer sequence (i.e. BUSY will remain -// high if already high) -#define DMA_CH1_CTRL_TRIG_EN_RESET _u(0x0) -#define DMA_CH1_CTRL_TRIG_EN_BITS _u(0x00000001) -#define DMA_CH1_CTRL_TRIG_EN_MSB _u(0) -#define DMA_CH1_CTRL_TRIG_EN_LSB _u(0) -#define DMA_CH1_CTRL_TRIG_EN_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH1_AL1_CTRL -// Description : Alias for channel 1 CTRL register -#define DMA_CH1_AL1_CTRL_OFFSET _u(0x00000050) -#define DMA_CH1_AL1_CTRL_BITS _u(0xffffffff) -#define DMA_CH1_AL1_CTRL_RESET "-" -#define DMA_CH1_AL1_CTRL_MSB _u(31) -#define DMA_CH1_AL1_CTRL_LSB _u(0) -#define DMA_CH1_AL1_CTRL_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH1_AL1_READ_ADDR -// Description : Alias for channel 1 READ_ADDR register -#define DMA_CH1_AL1_READ_ADDR_OFFSET _u(0x00000054) -#define DMA_CH1_AL1_READ_ADDR_BITS _u(0xffffffff) -#define DMA_CH1_AL1_READ_ADDR_RESET "-" -#define DMA_CH1_AL1_READ_ADDR_MSB _u(31) -#define DMA_CH1_AL1_READ_ADDR_LSB _u(0) -#define DMA_CH1_AL1_READ_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH1_AL1_WRITE_ADDR -// Description : Alias for channel 1 WRITE_ADDR register -#define DMA_CH1_AL1_WRITE_ADDR_OFFSET _u(0x00000058) -#define DMA_CH1_AL1_WRITE_ADDR_BITS _u(0xffffffff) -#define DMA_CH1_AL1_WRITE_ADDR_RESET "-" -#define DMA_CH1_AL1_WRITE_ADDR_MSB _u(31) -#define DMA_CH1_AL1_WRITE_ADDR_LSB _u(0) -#define DMA_CH1_AL1_WRITE_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH1_AL1_TRANS_COUNT_TRIG -// Description : Alias for channel 1 TRANS_COUNT register -// This is a trigger register (0xc). Writing a nonzero value will -// reload the channel counter and start the channel. -#define DMA_CH1_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x0000005c) -#define DMA_CH1_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff) -#define DMA_CH1_AL1_TRANS_COUNT_TRIG_RESET "-" -#define DMA_CH1_AL1_TRANS_COUNT_TRIG_MSB _u(31) -#define DMA_CH1_AL1_TRANS_COUNT_TRIG_LSB _u(0) -#define DMA_CH1_AL1_TRANS_COUNT_TRIG_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH1_AL2_CTRL -// Description : Alias for channel 1 CTRL register -#define DMA_CH1_AL2_CTRL_OFFSET _u(0x00000060) -#define DMA_CH1_AL2_CTRL_BITS _u(0xffffffff) -#define DMA_CH1_AL2_CTRL_RESET "-" -#define DMA_CH1_AL2_CTRL_MSB _u(31) -#define DMA_CH1_AL2_CTRL_LSB _u(0) -#define DMA_CH1_AL2_CTRL_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH1_AL2_TRANS_COUNT -// Description : Alias for channel 1 TRANS_COUNT register -#define DMA_CH1_AL2_TRANS_COUNT_OFFSET _u(0x00000064) -#define DMA_CH1_AL2_TRANS_COUNT_BITS _u(0xffffffff) -#define DMA_CH1_AL2_TRANS_COUNT_RESET "-" -#define DMA_CH1_AL2_TRANS_COUNT_MSB _u(31) -#define DMA_CH1_AL2_TRANS_COUNT_LSB _u(0) -#define DMA_CH1_AL2_TRANS_COUNT_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH1_AL2_READ_ADDR -// Description : Alias for channel 1 READ_ADDR register -#define DMA_CH1_AL2_READ_ADDR_OFFSET _u(0x00000068) -#define DMA_CH1_AL2_READ_ADDR_BITS _u(0xffffffff) -#define DMA_CH1_AL2_READ_ADDR_RESET "-" -#define DMA_CH1_AL2_READ_ADDR_MSB _u(31) -#define DMA_CH1_AL2_READ_ADDR_LSB _u(0) -#define DMA_CH1_AL2_READ_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH1_AL2_WRITE_ADDR_TRIG -// Description : Alias for channel 1 WRITE_ADDR register -// This is a trigger register (0xc). Writing a nonzero value will -// reload the channel counter and start the channel. -#define DMA_CH1_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x0000006c) -#define DMA_CH1_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff) -#define DMA_CH1_AL2_WRITE_ADDR_TRIG_RESET "-" -#define DMA_CH1_AL2_WRITE_ADDR_TRIG_MSB _u(31) -#define DMA_CH1_AL2_WRITE_ADDR_TRIG_LSB _u(0) -#define DMA_CH1_AL2_WRITE_ADDR_TRIG_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH1_AL3_CTRL -// Description : Alias for channel 1 CTRL register -#define DMA_CH1_AL3_CTRL_OFFSET _u(0x00000070) -#define DMA_CH1_AL3_CTRL_BITS _u(0xffffffff) -#define DMA_CH1_AL3_CTRL_RESET "-" -#define DMA_CH1_AL3_CTRL_MSB _u(31) -#define DMA_CH1_AL3_CTRL_LSB _u(0) -#define DMA_CH1_AL3_CTRL_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH1_AL3_WRITE_ADDR -// Description : Alias for channel 1 WRITE_ADDR register -#define DMA_CH1_AL3_WRITE_ADDR_OFFSET _u(0x00000074) -#define DMA_CH1_AL3_WRITE_ADDR_BITS _u(0xffffffff) -#define DMA_CH1_AL3_WRITE_ADDR_RESET "-" -#define DMA_CH1_AL3_WRITE_ADDR_MSB _u(31) -#define DMA_CH1_AL3_WRITE_ADDR_LSB _u(0) -#define DMA_CH1_AL3_WRITE_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH1_AL3_TRANS_COUNT -// Description : Alias for channel 1 TRANS_COUNT register -#define DMA_CH1_AL3_TRANS_COUNT_OFFSET _u(0x00000078) -#define DMA_CH1_AL3_TRANS_COUNT_BITS _u(0xffffffff) -#define DMA_CH1_AL3_TRANS_COUNT_RESET "-" -#define DMA_CH1_AL3_TRANS_COUNT_MSB _u(31) -#define DMA_CH1_AL3_TRANS_COUNT_LSB _u(0) -#define DMA_CH1_AL3_TRANS_COUNT_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH1_AL3_READ_ADDR_TRIG -// Description : Alias for channel 1 READ_ADDR register -// This is a trigger register (0xc). Writing a nonzero value will -// reload the channel counter and start the channel. -#define DMA_CH1_AL3_READ_ADDR_TRIG_OFFSET _u(0x0000007c) -#define DMA_CH1_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff) -#define DMA_CH1_AL3_READ_ADDR_TRIG_RESET "-" -#define DMA_CH1_AL3_READ_ADDR_TRIG_MSB _u(31) -#define DMA_CH1_AL3_READ_ADDR_TRIG_LSB _u(0) -#define DMA_CH1_AL3_READ_ADDR_TRIG_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH2_READ_ADDR -// Description : DMA Channel 2 Read Address pointer -// This register updates automatically each time a read completes. -// The current value is the next address to be read by this -// channel. -#define DMA_CH2_READ_ADDR_OFFSET _u(0x00000080) -#define DMA_CH2_READ_ADDR_BITS _u(0xffffffff) -#define DMA_CH2_READ_ADDR_RESET _u(0x00000000) -#define DMA_CH2_READ_ADDR_MSB _u(31) -#define DMA_CH2_READ_ADDR_LSB _u(0) -#define DMA_CH2_READ_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH2_WRITE_ADDR -// Description : DMA Channel 2 Write Address pointer -// This register updates automatically each time a write -// completes. The current value is the next address to be written -// by this channel. -#define DMA_CH2_WRITE_ADDR_OFFSET _u(0x00000084) -#define DMA_CH2_WRITE_ADDR_BITS _u(0xffffffff) -#define DMA_CH2_WRITE_ADDR_RESET _u(0x00000000) -#define DMA_CH2_WRITE_ADDR_MSB _u(31) -#define DMA_CH2_WRITE_ADDR_LSB _u(0) -#define DMA_CH2_WRITE_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH2_TRANS_COUNT -// Description : DMA Channel 2 Transfer Count -#define DMA_CH2_TRANS_COUNT_OFFSET _u(0x00000088) -#define DMA_CH2_TRANS_COUNT_BITS _u(0xffffffff) -#define DMA_CH2_TRANS_COUNT_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : DMA_CH2_TRANS_COUNT_MODE -// Description : When MODE is 0x0, the transfer count decrements with each -// transfer until 0, and then the channel triggers the next -// channel indicated by CTRL_CHAIN_TO. -// -// When MODE is 0x1, the transfer count decrements with each -// transfer until 0, and then the channel re-triggers itself, in -// addition to the trigger indicated by CTRL_CHAIN_TO. This is -// useful for e.g. an endless ring-buffer DMA with periodic -// interrupts. -// -// When MODE is 0xf, the transfer count does not decrement. The -// DMA channel performs an endless sequence of transfers, never -// triggering other channels or raising interrupts, until an ABORT -// is raised. -// -// All other values are reserved. -// 0x0 -> NORMAL -// 0x1 -> TRIGGER_SELF -// 0xf -> ENDLESS -#define DMA_CH2_TRANS_COUNT_MODE_RESET _u(0x0) -#define DMA_CH2_TRANS_COUNT_MODE_BITS _u(0xf0000000) -#define DMA_CH2_TRANS_COUNT_MODE_MSB _u(31) -#define DMA_CH2_TRANS_COUNT_MODE_LSB _u(28) -#define DMA_CH2_TRANS_COUNT_MODE_ACCESS "RW" -#define DMA_CH2_TRANS_COUNT_MODE_VALUE_NORMAL _u(0x0) -#define DMA_CH2_TRANS_COUNT_MODE_VALUE_TRIGGER_SELF _u(0x1) -#define DMA_CH2_TRANS_COUNT_MODE_VALUE_ENDLESS _u(0xf) -// ----------------------------------------------------------------------------- -// Field : DMA_CH2_TRANS_COUNT_COUNT -// Description : 28-bit transfer count (256 million transfers maximum). -// -// Program the number of bus transfers a channel will perform -// before halting. Note that, if transfers are larger than one -// byte in size, this is not equal to the number of bytes -// transferred (see CTRL_DATA_SIZE). -// -// When the channel is active, reading this register shows the -// number of transfers remaining, updating automatically each time -// a write transfer completes. -// -// Writing this register sets the RELOAD value for the transfer -// counter. Each time this channel is triggered, the RELOAD value -// is copied into the live transfer counter. The channel can be -// started multiple times, and will perform the same number of -// transfers each time, as programmed by most recent write. -// -// The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT -// is used as a trigger, the written value is used immediately as -// the length of the new transfer sequence, as well as being -// written to RELOAD. -#define DMA_CH2_TRANS_COUNT_COUNT_RESET _u(0x0000000) -#define DMA_CH2_TRANS_COUNT_COUNT_BITS _u(0x0fffffff) -#define DMA_CH2_TRANS_COUNT_COUNT_MSB _u(27) -#define DMA_CH2_TRANS_COUNT_COUNT_LSB _u(0) -#define DMA_CH2_TRANS_COUNT_COUNT_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH2_CTRL_TRIG -// Description : DMA Channel 2 Control and Status -#define DMA_CH2_CTRL_TRIG_OFFSET _u(0x0000008c) -#define DMA_CH2_CTRL_TRIG_BITS _u(0xe7ffffff) -#define DMA_CH2_CTRL_TRIG_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : DMA_CH2_CTRL_TRIG_AHB_ERROR -// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel -// halts when it encounters any bus error, and always raises its -// channel IRQ flag. -#define DMA_CH2_CTRL_TRIG_AHB_ERROR_RESET _u(0x0) -#define DMA_CH2_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000) -#define DMA_CH2_CTRL_TRIG_AHB_ERROR_MSB _u(31) -#define DMA_CH2_CTRL_TRIG_AHB_ERROR_LSB _u(31) -#define DMA_CH2_CTRL_TRIG_AHB_ERROR_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : DMA_CH2_CTRL_TRIG_READ_ERROR -// Description : If 1, the channel received a read bus error. Write one to -// clear. -// READ_ADDR shows the approximate address where the bus error was -// encountered (will not be earlier, or more than 3 transfers -// later) -#define DMA_CH2_CTRL_TRIG_READ_ERROR_RESET _u(0x0) -#define DMA_CH2_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000) -#define DMA_CH2_CTRL_TRIG_READ_ERROR_MSB _u(30) -#define DMA_CH2_CTRL_TRIG_READ_ERROR_LSB _u(30) -#define DMA_CH2_CTRL_TRIG_READ_ERROR_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : DMA_CH2_CTRL_TRIG_WRITE_ERROR -// Description : If 1, the channel received a write bus error. Write one to -// clear. -// WRITE_ADDR shows the approximate address where the bus error -// was encountered (will not be earlier, or more than 5 transfers -// later) -#define DMA_CH2_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0) -#define DMA_CH2_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000) -#define DMA_CH2_CTRL_TRIG_WRITE_ERROR_MSB _u(29) -#define DMA_CH2_CTRL_TRIG_WRITE_ERROR_LSB _u(29) -#define DMA_CH2_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : DMA_CH2_CTRL_TRIG_BUSY -// Description : This flag goes high when the channel starts a new transfer -// sequence, and low when the last transfer of that sequence -// completes. Clearing EN while BUSY is high pauses the channel, -// and BUSY will stay high while paused. -// -// To terminate a sequence early (and clear the BUSY flag), see -// CHAN_ABORT. -#define DMA_CH2_CTRL_TRIG_BUSY_RESET _u(0x0) -#define DMA_CH2_CTRL_TRIG_BUSY_BITS _u(0x04000000) -#define DMA_CH2_CTRL_TRIG_BUSY_MSB _u(26) -#define DMA_CH2_CTRL_TRIG_BUSY_LSB _u(26) -#define DMA_CH2_CTRL_TRIG_BUSY_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : DMA_CH2_CTRL_TRIG_SNIFF_EN -// Description : If 1, this channel's data transfers are visible to the sniff -// hardware, and each transfer will advance the state of the -// checksum. This only applies if the sniff hardware is enabled, -// and has this channel selected. -// -// This allows checksum to be enabled or disabled on a per- -// control- block basis. -#define DMA_CH2_CTRL_TRIG_SNIFF_EN_RESET _u(0x0) -#define DMA_CH2_CTRL_TRIG_SNIFF_EN_BITS _u(0x02000000) -#define DMA_CH2_CTRL_TRIG_SNIFF_EN_MSB _u(25) -#define DMA_CH2_CTRL_TRIG_SNIFF_EN_LSB _u(25) -#define DMA_CH2_CTRL_TRIG_SNIFF_EN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH2_CTRL_TRIG_BSWAP -// Description : Apply byte-swap transformation to DMA data. -// For byte data, this has no effect. For halfword data, the two -// bytes of each halfword are swapped. For word data, the four -// bytes of each word are swapped to reverse order. -#define DMA_CH2_CTRL_TRIG_BSWAP_RESET _u(0x0) -#define DMA_CH2_CTRL_TRIG_BSWAP_BITS _u(0x01000000) -#define DMA_CH2_CTRL_TRIG_BSWAP_MSB _u(24) -#define DMA_CH2_CTRL_TRIG_BSWAP_LSB _u(24) -#define DMA_CH2_CTRL_TRIG_BSWAP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH2_CTRL_TRIG_IRQ_QUIET -// Description : In QUIET mode, the channel does not generate IRQs at the end of -// every transfer block. Instead, an IRQ is raised when NULL is -// written to a trigger register, indicating the end of a control -// block chain. -// -// This reduces the number of interrupts to be serviced by the CPU -// when transferring a DMA chain of many small control blocks. -#define DMA_CH2_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0) -#define DMA_CH2_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00800000) -#define DMA_CH2_CTRL_TRIG_IRQ_QUIET_MSB _u(23) -#define DMA_CH2_CTRL_TRIG_IRQ_QUIET_LSB _u(23) -#define DMA_CH2_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH2_CTRL_TRIG_TREQ_SEL -// Description : Select a Transfer Request signal. -// The channel uses the transfer request signal to pace its data -// transfer rate. Sources for TREQ signals are internal (TIMERS) -// or external (DREQ, a Data Request from the system). -// 0x0 to 0x3a -> select DREQ n as TREQ -// 0x3b -> Select Timer 0 as TREQ -// 0x3c -> Select Timer 1 as TREQ -// 0x3d -> Select Timer 2 as TREQ (Optional) -// 0x3e -> Select Timer 3 as TREQ (Optional) -// 0x3f -> Permanent request, for unpaced transfers. -#define DMA_CH2_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) -#define DMA_CH2_CTRL_TRIG_TREQ_SEL_BITS _u(0x007e0000) -#define DMA_CH2_CTRL_TRIG_TREQ_SEL_MSB _u(22) -#define DMA_CH2_CTRL_TRIG_TREQ_SEL_LSB _u(17) -#define DMA_CH2_CTRL_TRIG_TREQ_SEL_ACCESS "RW" -#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) -#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) -#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) -#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) -#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) -// ----------------------------------------------------------------------------- -// Field : DMA_CH2_CTRL_TRIG_CHAIN_TO -// Description : When this channel completes, it will trigger the channel -// indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this -// channel)_. -// -// Note this field resets to 0, so channels 1 and above will chain -// to channel 0 by default. Set this field to avoid this -// behaviour. -#define DMA_CH2_CTRL_TRIG_CHAIN_TO_RESET _u(0x0) -#define DMA_CH2_CTRL_TRIG_CHAIN_TO_BITS _u(0x0001e000) -#define DMA_CH2_CTRL_TRIG_CHAIN_TO_MSB _u(16) -#define DMA_CH2_CTRL_TRIG_CHAIN_TO_LSB _u(13) -#define DMA_CH2_CTRL_TRIG_CHAIN_TO_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH2_CTRL_TRIG_RING_SEL -// Description : Select whether RING_SIZE applies to read or write addresses. -// If 0, read addresses are wrapped on a (1 << RING_SIZE) -// boundary. If 1, write addresses are wrapped. -#define DMA_CH2_CTRL_TRIG_RING_SEL_RESET _u(0x0) -#define DMA_CH2_CTRL_TRIG_RING_SEL_BITS _u(0x00001000) -#define DMA_CH2_CTRL_TRIG_RING_SEL_MSB _u(12) -#define DMA_CH2_CTRL_TRIG_RING_SEL_LSB _u(12) -#define DMA_CH2_CTRL_TRIG_RING_SEL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH2_CTRL_TRIG_RING_SIZE -// Description : Size of address wrap region. If 0, don't wrap. For values n > -// 0, only the lower n bits of the address will change. This wraps -// the address on a (1 << n) byte boundary, facilitating access to -// naturally-aligned ring buffers. -// -// Ring sizes between 2 and 32768 bytes are possible. This can -// apply to either read or write addresses, based on value of -// RING_SEL. -// 0x0 -> RING_NONE -#define DMA_CH2_CTRL_TRIG_RING_SIZE_RESET _u(0x0) -#define DMA_CH2_CTRL_TRIG_RING_SIZE_BITS _u(0x00000f00) -#define DMA_CH2_CTRL_TRIG_RING_SIZE_MSB _u(11) -#define DMA_CH2_CTRL_TRIG_RING_SIZE_LSB _u(8) -#define DMA_CH2_CTRL_TRIG_RING_SIZE_ACCESS "RW" -#define DMA_CH2_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0) -// ----------------------------------------------------------------------------- -// Field : DMA_CH2_CTRL_TRIG_INCR_WRITE_REV -// Description : If 1, and INCR_WRITE is 1, the write address is decremented -// rather than incremented with each transfer. -// -// If 1, and INCR_WRITE is 0, this otherwise-unused combination -// causes the write address to be incremented by twice the -// transfer size, i.e. skipping over alternate addresses. -#define DMA_CH2_CTRL_TRIG_INCR_WRITE_REV_RESET _u(0x0) -#define DMA_CH2_CTRL_TRIG_INCR_WRITE_REV_BITS _u(0x00000080) -#define DMA_CH2_CTRL_TRIG_INCR_WRITE_REV_MSB _u(7) -#define DMA_CH2_CTRL_TRIG_INCR_WRITE_REV_LSB _u(7) -#define DMA_CH2_CTRL_TRIG_INCR_WRITE_REV_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH2_CTRL_TRIG_INCR_WRITE -// Description : If 1, the write address increments with each transfer. If 0, -// each write is directed to the same, initial address. -// -// Generally this should be disabled for memory-to-peripheral -// transfers. -#define DMA_CH2_CTRL_TRIG_INCR_WRITE_RESET _u(0x0) -#define DMA_CH2_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000040) -#define DMA_CH2_CTRL_TRIG_INCR_WRITE_MSB _u(6) -#define DMA_CH2_CTRL_TRIG_INCR_WRITE_LSB _u(6) -#define DMA_CH2_CTRL_TRIG_INCR_WRITE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH2_CTRL_TRIG_INCR_READ_REV -// Description : If 1, and INCR_READ is 1, the read address is decremented -// rather than incremented with each transfer. -// -// If 1, and INCR_READ is 0, this otherwise-unused combination -// causes the read address to be incremented by twice the transfer -// size, i.e. skipping over alternate addresses. -#define DMA_CH2_CTRL_TRIG_INCR_READ_REV_RESET _u(0x0) -#define DMA_CH2_CTRL_TRIG_INCR_READ_REV_BITS _u(0x00000020) -#define DMA_CH2_CTRL_TRIG_INCR_READ_REV_MSB _u(5) -#define DMA_CH2_CTRL_TRIG_INCR_READ_REV_LSB _u(5) -#define DMA_CH2_CTRL_TRIG_INCR_READ_REV_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH2_CTRL_TRIG_INCR_READ -// Description : If 1, the read address increments with each transfer. If 0, -// each read is directed to the same, initial address. -// -// Generally this should be disabled for peripheral-to-memory -// transfers. -#define DMA_CH2_CTRL_TRIG_INCR_READ_RESET _u(0x0) -#define DMA_CH2_CTRL_TRIG_INCR_READ_BITS _u(0x00000010) -#define DMA_CH2_CTRL_TRIG_INCR_READ_MSB _u(4) -#define DMA_CH2_CTRL_TRIG_INCR_READ_LSB _u(4) -#define DMA_CH2_CTRL_TRIG_INCR_READ_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH2_CTRL_TRIG_DATA_SIZE -// Description : Set the size of each bus transfer (byte/halfword/word). -// READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) -// with each transfer. -// 0x0 -> SIZE_BYTE -// 0x1 -> SIZE_HALFWORD -// 0x2 -> SIZE_WORD -#define DMA_CH2_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) -#define DMA_CH2_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) -#define DMA_CH2_CTRL_TRIG_DATA_SIZE_MSB _u(3) -#define DMA_CH2_CTRL_TRIG_DATA_SIZE_LSB _u(2) -#define DMA_CH2_CTRL_TRIG_DATA_SIZE_ACCESS "RW" -#define DMA_CH2_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) -#define DMA_CH2_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1) -#define DMA_CH2_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) -// ----------------------------------------------------------------------------- -// Field : DMA_CH2_CTRL_TRIG_HIGH_PRIORITY -// Description : HIGH_PRIORITY gives a channel preferential treatment in issue -// scheduling: in each scheduling round, all high priority -// channels are considered first, and then only a single low -// priority channel, before returning to the high priority -// channels. -// -// This only affects the order in which the DMA schedules -// channels. The DMA's bus priority is not changed. If the DMA is -// not saturated then a low priority channel will see no loss of -// throughput. -#define DMA_CH2_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0) -#define DMA_CH2_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002) -#define DMA_CH2_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1) -#define DMA_CH2_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1) -#define DMA_CH2_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH2_CTRL_TRIG_EN -// Description : DMA Channel Enable. -// When 1, the channel will respond to triggering events, which -// will cause it to become BUSY and start transferring data. When -// 0, the channel will ignore triggers, stop issuing transfers, -// and pause the current transfer sequence (i.e. BUSY will remain -// high if already high) -#define DMA_CH2_CTRL_TRIG_EN_RESET _u(0x0) -#define DMA_CH2_CTRL_TRIG_EN_BITS _u(0x00000001) -#define DMA_CH2_CTRL_TRIG_EN_MSB _u(0) -#define DMA_CH2_CTRL_TRIG_EN_LSB _u(0) -#define DMA_CH2_CTRL_TRIG_EN_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH2_AL1_CTRL -// Description : Alias for channel 2 CTRL register -#define DMA_CH2_AL1_CTRL_OFFSET _u(0x00000090) -#define DMA_CH2_AL1_CTRL_BITS _u(0xffffffff) -#define DMA_CH2_AL1_CTRL_RESET "-" -#define DMA_CH2_AL1_CTRL_MSB _u(31) -#define DMA_CH2_AL1_CTRL_LSB _u(0) -#define DMA_CH2_AL1_CTRL_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH2_AL1_READ_ADDR -// Description : Alias for channel 2 READ_ADDR register -#define DMA_CH2_AL1_READ_ADDR_OFFSET _u(0x00000094) -#define DMA_CH2_AL1_READ_ADDR_BITS _u(0xffffffff) -#define DMA_CH2_AL1_READ_ADDR_RESET "-" -#define DMA_CH2_AL1_READ_ADDR_MSB _u(31) -#define DMA_CH2_AL1_READ_ADDR_LSB _u(0) -#define DMA_CH2_AL1_READ_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH2_AL1_WRITE_ADDR -// Description : Alias for channel 2 WRITE_ADDR register -#define DMA_CH2_AL1_WRITE_ADDR_OFFSET _u(0x00000098) -#define DMA_CH2_AL1_WRITE_ADDR_BITS _u(0xffffffff) -#define DMA_CH2_AL1_WRITE_ADDR_RESET "-" -#define DMA_CH2_AL1_WRITE_ADDR_MSB _u(31) -#define DMA_CH2_AL1_WRITE_ADDR_LSB _u(0) -#define DMA_CH2_AL1_WRITE_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH2_AL1_TRANS_COUNT_TRIG -// Description : Alias for channel 2 TRANS_COUNT register -// This is a trigger register (0xc). Writing a nonzero value will -// reload the channel counter and start the channel. -#define DMA_CH2_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x0000009c) -#define DMA_CH2_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff) -#define DMA_CH2_AL1_TRANS_COUNT_TRIG_RESET "-" -#define DMA_CH2_AL1_TRANS_COUNT_TRIG_MSB _u(31) -#define DMA_CH2_AL1_TRANS_COUNT_TRIG_LSB _u(0) -#define DMA_CH2_AL1_TRANS_COUNT_TRIG_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH2_AL2_CTRL -// Description : Alias for channel 2 CTRL register -#define DMA_CH2_AL2_CTRL_OFFSET _u(0x000000a0) -#define DMA_CH2_AL2_CTRL_BITS _u(0xffffffff) -#define DMA_CH2_AL2_CTRL_RESET "-" -#define DMA_CH2_AL2_CTRL_MSB _u(31) -#define DMA_CH2_AL2_CTRL_LSB _u(0) -#define DMA_CH2_AL2_CTRL_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH2_AL2_TRANS_COUNT -// Description : Alias for channel 2 TRANS_COUNT register -#define DMA_CH2_AL2_TRANS_COUNT_OFFSET _u(0x000000a4) -#define DMA_CH2_AL2_TRANS_COUNT_BITS _u(0xffffffff) -#define DMA_CH2_AL2_TRANS_COUNT_RESET "-" -#define DMA_CH2_AL2_TRANS_COUNT_MSB _u(31) -#define DMA_CH2_AL2_TRANS_COUNT_LSB _u(0) -#define DMA_CH2_AL2_TRANS_COUNT_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH2_AL2_READ_ADDR -// Description : Alias for channel 2 READ_ADDR register -#define DMA_CH2_AL2_READ_ADDR_OFFSET _u(0x000000a8) -#define DMA_CH2_AL2_READ_ADDR_BITS _u(0xffffffff) -#define DMA_CH2_AL2_READ_ADDR_RESET "-" -#define DMA_CH2_AL2_READ_ADDR_MSB _u(31) -#define DMA_CH2_AL2_READ_ADDR_LSB _u(0) -#define DMA_CH2_AL2_READ_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH2_AL2_WRITE_ADDR_TRIG -// Description : Alias for channel 2 WRITE_ADDR register -// This is a trigger register (0xc). Writing a nonzero value will -// reload the channel counter and start the channel. -#define DMA_CH2_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x000000ac) -#define DMA_CH2_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff) -#define DMA_CH2_AL2_WRITE_ADDR_TRIG_RESET "-" -#define DMA_CH2_AL2_WRITE_ADDR_TRIG_MSB _u(31) -#define DMA_CH2_AL2_WRITE_ADDR_TRIG_LSB _u(0) -#define DMA_CH2_AL2_WRITE_ADDR_TRIG_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH2_AL3_CTRL -// Description : Alias for channel 2 CTRL register -#define DMA_CH2_AL3_CTRL_OFFSET _u(0x000000b0) -#define DMA_CH2_AL3_CTRL_BITS _u(0xffffffff) -#define DMA_CH2_AL3_CTRL_RESET "-" -#define DMA_CH2_AL3_CTRL_MSB _u(31) -#define DMA_CH2_AL3_CTRL_LSB _u(0) -#define DMA_CH2_AL3_CTRL_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH2_AL3_WRITE_ADDR -// Description : Alias for channel 2 WRITE_ADDR register -#define DMA_CH2_AL3_WRITE_ADDR_OFFSET _u(0x000000b4) -#define DMA_CH2_AL3_WRITE_ADDR_BITS _u(0xffffffff) -#define DMA_CH2_AL3_WRITE_ADDR_RESET "-" -#define DMA_CH2_AL3_WRITE_ADDR_MSB _u(31) -#define DMA_CH2_AL3_WRITE_ADDR_LSB _u(0) -#define DMA_CH2_AL3_WRITE_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH2_AL3_TRANS_COUNT -// Description : Alias for channel 2 TRANS_COUNT register -#define DMA_CH2_AL3_TRANS_COUNT_OFFSET _u(0x000000b8) -#define DMA_CH2_AL3_TRANS_COUNT_BITS _u(0xffffffff) -#define DMA_CH2_AL3_TRANS_COUNT_RESET "-" -#define DMA_CH2_AL3_TRANS_COUNT_MSB _u(31) -#define DMA_CH2_AL3_TRANS_COUNT_LSB _u(0) -#define DMA_CH2_AL3_TRANS_COUNT_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH2_AL3_READ_ADDR_TRIG -// Description : Alias for channel 2 READ_ADDR register -// This is a trigger register (0xc). Writing a nonzero value will -// reload the channel counter and start the channel. -#define DMA_CH2_AL3_READ_ADDR_TRIG_OFFSET _u(0x000000bc) -#define DMA_CH2_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff) -#define DMA_CH2_AL3_READ_ADDR_TRIG_RESET "-" -#define DMA_CH2_AL3_READ_ADDR_TRIG_MSB _u(31) -#define DMA_CH2_AL3_READ_ADDR_TRIG_LSB _u(0) -#define DMA_CH2_AL3_READ_ADDR_TRIG_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH3_READ_ADDR -// Description : DMA Channel 3 Read Address pointer -// This register updates automatically each time a read completes. -// The current value is the next address to be read by this -// channel. -#define DMA_CH3_READ_ADDR_OFFSET _u(0x000000c0) -#define DMA_CH3_READ_ADDR_BITS _u(0xffffffff) -#define DMA_CH3_READ_ADDR_RESET _u(0x00000000) -#define DMA_CH3_READ_ADDR_MSB _u(31) -#define DMA_CH3_READ_ADDR_LSB _u(0) -#define DMA_CH3_READ_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH3_WRITE_ADDR -// Description : DMA Channel 3 Write Address pointer -// This register updates automatically each time a write -// completes. The current value is the next address to be written -// by this channel. -#define DMA_CH3_WRITE_ADDR_OFFSET _u(0x000000c4) -#define DMA_CH3_WRITE_ADDR_BITS _u(0xffffffff) -#define DMA_CH3_WRITE_ADDR_RESET _u(0x00000000) -#define DMA_CH3_WRITE_ADDR_MSB _u(31) -#define DMA_CH3_WRITE_ADDR_LSB _u(0) -#define DMA_CH3_WRITE_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH3_TRANS_COUNT -// Description : DMA Channel 3 Transfer Count -#define DMA_CH3_TRANS_COUNT_OFFSET _u(0x000000c8) -#define DMA_CH3_TRANS_COUNT_BITS _u(0xffffffff) -#define DMA_CH3_TRANS_COUNT_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : DMA_CH3_TRANS_COUNT_MODE -// Description : When MODE is 0x0, the transfer count decrements with each -// transfer until 0, and then the channel triggers the next -// channel indicated by CTRL_CHAIN_TO. -// -// When MODE is 0x1, the transfer count decrements with each -// transfer until 0, and then the channel re-triggers itself, in -// addition to the trigger indicated by CTRL_CHAIN_TO. This is -// useful for e.g. an endless ring-buffer DMA with periodic -// interrupts. -// -// When MODE is 0xf, the transfer count does not decrement. The -// DMA channel performs an endless sequence of transfers, never -// triggering other channels or raising interrupts, until an ABORT -// is raised. -// -// All other values are reserved. -// 0x0 -> NORMAL -// 0x1 -> TRIGGER_SELF -// 0xf -> ENDLESS -#define DMA_CH3_TRANS_COUNT_MODE_RESET _u(0x0) -#define DMA_CH3_TRANS_COUNT_MODE_BITS _u(0xf0000000) -#define DMA_CH3_TRANS_COUNT_MODE_MSB _u(31) -#define DMA_CH3_TRANS_COUNT_MODE_LSB _u(28) -#define DMA_CH3_TRANS_COUNT_MODE_ACCESS "RW" -#define DMA_CH3_TRANS_COUNT_MODE_VALUE_NORMAL _u(0x0) -#define DMA_CH3_TRANS_COUNT_MODE_VALUE_TRIGGER_SELF _u(0x1) -#define DMA_CH3_TRANS_COUNT_MODE_VALUE_ENDLESS _u(0xf) -// ----------------------------------------------------------------------------- -// Field : DMA_CH3_TRANS_COUNT_COUNT -// Description : 28-bit transfer count (256 million transfers maximum). -// -// Program the number of bus transfers a channel will perform -// before halting. Note that, if transfers are larger than one -// byte in size, this is not equal to the number of bytes -// transferred (see CTRL_DATA_SIZE). -// -// When the channel is active, reading this register shows the -// number of transfers remaining, updating automatically each time -// a write transfer completes. -// -// Writing this register sets the RELOAD value for the transfer -// counter. Each time this channel is triggered, the RELOAD value -// is copied into the live transfer counter. The channel can be -// started multiple times, and will perform the same number of -// transfers each time, as programmed by most recent write. -// -// The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT -// is used as a trigger, the written value is used immediately as -// the length of the new transfer sequence, as well as being -// written to RELOAD. -#define DMA_CH3_TRANS_COUNT_COUNT_RESET _u(0x0000000) -#define DMA_CH3_TRANS_COUNT_COUNT_BITS _u(0x0fffffff) -#define DMA_CH3_TRANS_COUNT_COUNT_MSB _u(27) -#define DMA_CH3_TRANS_COUNT_COUNT_LSB _u(0) -#define DMA_CH3_TRANS_COUNT_COUNT_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH3_CTRL_TRIG -// Description : DMA Channel 3 Control and Status -#define DMA_CH3_CTRL_TRIG_OFFSET _u(0x000000cc) -#define DMA_CH3_CTRL_TRIG_BITS _u(0xe7ffffff) -#define DMA_CH3_CTRL_TRIG_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : DMA_CH3_CTRL_TRIG_AHB_ERROR -// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel -// halts when it encounters any bus error, and always raises its -// channel IRQ flag. -#define DMA_CH3_CTRL_TRIG_AHB_ERROR_RESET _u(0x0) -#define DMA_CH3_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000) -#define DMA_CH3_CTRL_TRIG_AHB_ERROR_MSB _u(31) -#define DMA_CH3_CTRL_TRIG_AHB_ERROR_LSB _u(31) -#define DMA_CH3_CTRL_TRIG_AHB_ERROR_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : DMA_CH3_CTRL_TRIG_READ_ERROR -// Description : If 1, the channel received a read bus error. Write one to -// clear. -// READ_ADDR shows the approximate address where the bus error was -// encountered (will not be earlier, or more than 3 transfers -// later) -#define DMA_CH3_CTRL_TRIG_READ_ERROR_RESET _u(0x0) -#define DMA_CH3_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000) -#define DMA_CH3_CTRL_TRIG_READ_ERROR_MSB _u(30) -#define DMA_CH3_CTRL_TRIG_READ_ERROR_LSB _u(30) -#define DMA_CH3_CTRL_TRIG_READ_ERROR_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : DMA_CH3_CTRL_TRIG_WRITE_ERROR -// Description : If 1, the channel received a write bus error. Write one to -// clear. -// WRITE_ADDR shows the approximate address where the bus error -// was encountered (will not be earlier, or more than 5 transfers -// later) -#define DMA_CH3_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0) -#define DMA_CH3_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000) -#define DMA_CH3_CTRL_TRIG_WRITE_ERROR_MSB _u(29) -#define DMA_CH3_CTRL_TRIG_WRITE_ERROR_LSB _u(29) -#define DMA_CH3_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : DMA_CH3_CTRL_TRIG_BUSY -// Description : This flag goes high when the channel starts a new transfer -// sequence, and low when the last transfer of that sequence -// completes. Clearing EN while BUSY is high pauses the channel, -// and BUSY will stay high while paused. -// -// To terminate a sequence early (and clear the BUSY flag), see -// CHAN_ABORT. -#define DMA_CH3_CTRL_TRIG_BUSY_RESET _u(0x0) -#define DMA_CH3_CTRL_TRIG_BUSY_BITS _u(0x04000000) -#define DMA_CH3_CTRL_TRIG_BUSY_MSB _u(26) -#define DMA_CH3_CTRL_TRIG_BUSY_LSB _u(26) -#define DMA_CH3_CTRL_TRIG_BUSY_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : DMA_CH3_CTRL_TRIG_SNIFF_EN -// Description : If 1, this channel's data transfers are visible to the sniff -// hardware, and each transfer will advance the state of the -// checksum. This only applies if the sniff hardware is enabled, -// and has this channel selected. -// -// This allows checksum to be enabled or disabled on a per- -// control- block basis. -#define DMA_CH3_CTRL_TRIG_SNIFF_EN_RESET _u(0x0) -#define DMA_CH3_CTRL_TRIG_SNIFF_EN_BITS _u(0x02000000) -#define DMA_CH3_CTRL_TRIG_SNIFF_EN_MSB _u(25) -#define DMA_CH3_CTRL_TRIG_SNIFF_EN_LSB _u(25) -#define DMA_CH3_CTRL_TRIG_SNIFF_EN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH3_CTRL_TRIG_BSWAP -// Description : Apply byte-swap transformation to DMA data. -// For byte data, this has no effect. For halfword data, the two -// bytes of each halfword are swapped. For word data, the four -// bytes of each word are swapped to reverse order. -#define DMA_CH3_CTRL_TRIG_BSWAP_RESET _u(0x0) -#define DMA_CH3_CTRL_TRIG_BSWAP_BITS _u(0x01000000) -#define DMA_CH3_CTRL_TRIG_BSWAP_MSB _u(24) -#define DMA_CH3_CTRL_TRIG_BSWAP_LSB _u(24) -#define DMA_CH3_CTRL_TRIG_BSWAP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH3_CTRL_TRIG_IRQ_QUIET -// Description : In QUIET mode, the channel does not generate IRQs at the end of -// every transfer block. Instead, an IRQ is raised when NULL is -// written to a trigger register, indicating the end of a control -// block chain. -// -// This reduces the number of interrupts to be serviced by the CPU -// when transferring a DMA chain of many small control blocks. -#define DMA_CH3_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0) -#define DMA_CH3_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00800000) -#define DMA_CH3_CTRL_TRIG_IRQ_QUIET_MSB _u(23) -#define DMA_CH3_CTRL_TRIG_IRQ_QUIET_LSB _u(23) -#define DMA_CH3_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH3_CTRL_TRIG_TREQ_SEL -// Description : Select a Transfer Request signal. -// The channel uses the transfer request signal to pace its data -// transfer rate. Sources for TREQ signals are internal (TIMERS) -// or external (DREQ, a Data Request from the system). -// 0x0 to 0x3a -> select DREQ n as TREQ -// 0x3b -> Select Timer 0 as TREQ -// 0x3c -> Select Timer 1 as TREQ -// 0x3d -> Select Timer 2 as TREQ (Optional) -// 0x3e -> Select Timer 3 as TREQ (Optional) -// 0x3f -> Permanent request, for unpaced transfers. -#define DMA_CH3_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) -#define DMA_CH3_CTRL_TRIG_TREQ_SEL_BITS _u(0x007e0000) -#define DMA_CH3_CTRL_TRIG_TREQ_SEL_MSB _u(22) -#define DMA_CH3_CTRL_TRIG_TREQ_SEL_LSB _u(17) -#define DMA_CH3_CTRL_TRIG_TREQ_SEL_ACCESS "RW" -#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) -#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) -#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) -#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) -#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) -// ----------------------------------------------------------------------------- -// Field : DMA_CH3_CTRL_TRIG_CHAIN_TO -// Description : When this channel completes, it will trigger the channel -// indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this -// channel)_. -// -// Note this field resets to 0, so channels 1 and above will chain -// to channel 0 by default. Set this field to avoid this -// behaviour. -#define DMA_CH3_CTRL_TRIG_CHAIN_TO_RESET _u(0x0) -#define DMA_CH3_CTRL_TRIG_CHAIN_TO_BITS _u(0x0001e000) -#define DMA_CH3_CTRL_TRIG_CHAIN_TO_MSB _u(16) -#define DMA_CH3_CTRL_TRIG_CHAIN_TO_LSB _u(13) -#define DMA_CH3_CTRL_TRIG_CHAIN_TO_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH3_CTRL_TRIG_RING_SEL -// Description : Select whether RING_SIZE applies to read or write addresses. -// If 0, read addresses are wrapped on a (1 << RING_SIZE) -// boundary. If 1, write addresses are wrapped. -#define DMA_CH3_CTRL_TRIG_RING_SEL_RESET _u(0x0) -#define DMA_CH3_CTRL_TRIG_RING_SEL_BITS _u(0x00001000) -#define DMA_CH3_CTRL_TRIG_RING_SEL_MSB _u(12) -#define DMA_CH3_CTRL_TRIG_RING_SEL_LSB _u(12) -#define DMA_CH3_CTRL_TRIG_RING_SEL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH3_CTRL_TRIG_RING_SIZE -// Description : Size of address wrap region. If 0, don't wrap. For values n > -// 0, only the lower n bits of the address will change. This wraps -// the address on a (1 << n) byte boundary, facilitating access to -// naturally-aligned ring buffers. -// -// Ring sizes between 2 and 32768 bytes are possible. This can -// apply to either read or write addresses, based on value of -// RING_SEL. -// 0x0 -> RING_NONE -#define DMA_CH3_CTRL_TRIG_RING_SIZE_RESET _u(0x0) -#define DMA_CH3_CTRL_TRIG_RING_SIZE_BITS _u(0x00000f00) -#define DMA_CH3_CTRL_TRIG_RING_SIZE_MSB _u(11) -#define DMA_CH3_CTRL_TRIG_RING_SIZE_LSB _u(8) -#define DMA_CH3_CTRL_TRIG_RING_SIZE_ACCESS "RW" -#define DMA_CH3_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0) -// ----------------------------------------------------------------------------- -// Field : DMA_CH3_CTRL_TRIG_INCR_WRITE_REV -// Description : If 1, and INCR_WRITE is 1, the write address is decremented -// rather than incremented with each transfer. -// -// If 1, and INCR_WRITE is 0, this otherwise-unused combination -// causes the write address to be incremented by twice the -// transfer size, i.e. skipping over alternate addresses. -#define DMA_CH3_CTRL_TRIG_INCR_WRITE_REV_RESET _u(0x0) -#define DMA_CH3_CTRL_TRIG_INCR_WRITE_REV_BITS _u(0x00000080) -#define DMA_CH3_CTRL_TRIG_INCR_WRITE_REV_MSB _u(7) -#define DMA_CH3_CTRL_TRIG_INCR_WRITE_REV_LSB _u(7) -#define DMA_CH3_CTRL_TRIG_INCR_WRITE_REV_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH3_CTRL_TRIG_INCR_WRITE -// Description : If 1, the write address increments with each transfer. If 0, -// each write is directed to the same, initial address. -// -// Generally this should be disabled for memory-to-peripheral -// transfers. -#define DMA_CH3_CTRL_TRIG_INCR_WRITE_RESET _u(0x0) -#define DMA_CH3_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000040) -#define DMA_CH3_CTRL_TRIG_INCR_WRITE_MSB _u(6) -#define DMA_CH3_CTRL_TRIG_INCR_WRITE_LSB _u(6) -#define DMA_CH3_CTRL_TRIG_INCR_WRITE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH3_CTRL_TRIG_INCR_READ_REV -// Description : If 1, and INCR_READ is 1, the read address is decremented -// rather than incremented with each transfer. -// -// If 1, and INCR_READ is 0, this otherwise-unused combination -// causes the read address to be incremented by twice the transfer -// size, i.e. skipping over alternate addresses. -#define DMA_CH3_CTRL_TRIG_INCR_READ_REV_RESET _u(0x0) -#define DMA_CH3_CTRL_TRIG_INCR_READ_REV_BITS _u(0x00000020) -#define DMA_CH3_CTRL_TRIG_INCR_READ_REV_MSB _u(5) -#define DMA_CH3_CTRL_TRIG_INCR_READ_REV_LSB _u(5) -#define DMA_CH3_CTRL_TRIG_INCR_READ_REV_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH3_CTRL_TRIG_INCR_READ -// Description : If 1, the read address increments with each transfer. If 0, -// each read is directed to the same, initial address. -// -// Generally this should be disabled for peripheral-to-memory -// transfers. -#define DMA_CH3_CTRL_TRIG_INCR_READ_RESET _u(0x0) -#define DMA_CH3_CTRL_TRIG_INCR_READ_BITS _u(0x00000010) -#define DMA_CH3_CTRL_TRIG_INCR_READ_MSB _u(4) -#define DMA_CH3_CTRL_TRIG_INCR_READ_LSB _u(4) -#define DMA_CH3_CTRL_TRIG_INCR_READ_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH3_CTRL_TRIG_DATA_SIZE -// Description : Set the size of each bus transfer (byte/halfword/word). -// READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) -// with each transfer. -// 0x0 -> SIZE_BYTE -// 0x1 -> SIZE_HALFWORD -// 0x2 -> SIZE_WORD -#define DMA_CH3_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) -#define DMA_CH3_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) -#define DMA_CH3_CTRL_TRIG_DATA_SIZE_MSB _u(3) -#define DMA_CH3_CTRL_TRIG_DATA_SIZE_LSB _u(2) -#define DMA_CH3_CTRL_TRIG_DATA_SIZE_ACCESS "RW" -#define DMA_CH3_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) -#define DMA_CH3_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1) -#define DMA_CH3_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) -// ----------------------------------------------------------------------------- -// Field : DMA_CH3_CTRL_TRIG_HIGH_PRIORITY -// Description : HIGH_PRIORITY gives a channel preferential treatment in issue -// scheduling: in each scheduling round, all high priority -// channels are considered first, and then only a single low -// priority channel, before returning to the high priority -// channels. -// -// This only affects the order in which the DMA schedules -// channels. The DMA's bus priority is not changed. If the DMA is -// not saturated then a low priority channel will see no loss of -// throughput. -#define DMA_CH3_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0) -#define DMA_CH3_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002) -#define DMA_CH3_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1) -#define DMA_CH3_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1) -#define DMA_CH3_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH3_CTRL_TRIG_EN -// Description : DMA Channel Enable. -// When 1, the channel will respond to triggering events, which -// will cause it to become BUSY and start transferring data. When -// 0, the channel will ignore triggers, stop issuing transfers, -// and pause the current transfer sequence (i.e. BUSY will remain -// high if already high) -#define DMA_CH3_CTRL_TRIG_EN_RESET _u(0x0) -#define DMA_CH3_CTRL_TRIG_EN_BITS _u(0x00000001) -#define DMA_CH3_CTRL_TRIG_EN_MSB _u(0) -#define DMA_CH3_CTRL_TRIG_EN_LSB _u(0) -#define DMA_CH3_CTRL_TRIG_EN_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH3_AL1_CTRL -// Description : Alias for channel 3 CTRL register -#define DMA_CH3_AL1_CTRL_OFFSET _u(0x000000d0) -#define DMA_CH3_AL1_CTRL_BITS _u(0xffffffff) -#define DMA_CH3_AL1_CTRL_RESET "-" -#define DMA_CH3_AL1_CTRL_MSB _u(31) -#define DMA_CH3_AL1_CTRL_LSB _u(0) -#define DMA_CH3_AL1_CTRL_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH3_AL1_READ_ADDR -// Description : Alias for channel 3 READ_ADDR register -#define DMA_CH3_AL1_READ_ADDR_OFFSET _u(0x000000d4) -#define DMA_CH3_AL1_READ_ADDR_BITS _u(0xffffffff) -#define DMA_CH3_AL1_READ_ADDR_RESET "-" -#define DMA_CH3_AL1_READ_ADDR_MSB _u(31) -#define DMA_CH3_AL1_READ_ADDR_LSB _u(0) -#define DMA_CH3_AL1_READ_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH3_AL1_WRITE_ADDR -// Description : Alias for channel 3 WRITE_ADDR register -#define DMA_CH3_AL1_WRITE_ADDR_OFFSET _u(0x000000d8) -#define DMA_CH3_AL1_WRITE_ADDR_BITS _u(0xffffffff) -#define DMA_CH3_AL1_WRITE_ADDR_RESET "-" -#define DMA_CH3_AL1_WRITE_ADDR_MSB _u(31) -#define DMA_CH3_AL1_WRITE_ADDR_LSB _u(0) -#define DMA_CH3_AL1_WRITE_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH3_AL1_TRANS_COUNT_TRIG -// Description : Alias for channel 3 TRANS_COUNT register -// This is a trigger register (0xc). Writing a nonzero value will -// reload the channel counter and start the channel. -#define DMA_CH3_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x000000dc) -#define DMA_CH3_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff) -#define DMA_CH3_AL1_TRANS_COUNT_TRIG_RESET "-" -#define DMA_CH3_AL1_TRANS_COUNT_TRIG_MSB _u(31) -#define DMA_CH3_AL1_TRANS_COUNT_TRIG_LSB _u(0) -#define DMA_CH3_AL1_TRANS_COUNT_TRIG_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH3_AL2_CTRL -// Description : Alias for channel 3 CTRL register -#define DMA_CH3_AL2_CTRL_OFFSET _u(0x000000e0) -#define DMA_CH3_AL2_CTRL_BITS _u(0xffffffff) -#define DMA_CH3_AL2_CTRL_RESET "-" -#define DMA_CH3_AL2_CTRL_MSB _u(31) -#define DMA_CH3_AL2_CTRL_LSB _u(0) -#define DMA_CH3_AL2_CTRL_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH3_AL2_TRANS_COUNT -// Description : Alias for channel 3 TRANS_COUNT register -#define DMA_CH3_AL2_TRANS_COUNT_OFFSET _u(0x000000e4) -#define DMA_CH3_AL2_TRANS_COUNT_BITS _u(0xffffffff) -#define DMA_CH3_AL2_TRANS_COUNT_RESET "-" -#define DMA_CH3_AL2_TRANS_COUNT_MSB _u(31) -#define DMA_CH3_AL2_TRANS_COUNT_LSB _u(0) -#define DMA_CH3_AL2_TRANS_COUNT_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH3_AL2_READ_ADDR -// Description : Alias for channel 3 READ_ADDR register -#define DMA_CH3_AL2_READ_ADDR_OFFSET _u(0x000000e8) -#define DMA_CH3_AL2_READ_ADDR_BITS _u(0xffffffff) -#define DMA_CH3_AL2_READ_ADDR_RESET "-" -#define DMA_CH3_AL2_READ_ADDR_MSB _u(31) -#define DMA_CH3_AL2_READ_ADDR_LSB _u(0) -#define DMA_CH3_AL2_READ_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH3_AL2_WRITE_ADDR_TRIG -// Description : Alias for channel 3 WRITE_ADDR register -// This is a trigger register (0xc). Writing a nonzero value will -// reload the channel counter and start the channel. -#define DMA_CH3_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x000000ec) -#define DMA_CH3_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff) -#define DMA_CH3_AL2_WRITE_ADDR_TRIG_RESET "-" -#define DMA_CH3_AL2_WRITE_ADDR_TRIG_MSB _u(31) -#define DMA_CH3_AL2_WRITE_ADDR_TRIG_LSB _u(0) -#define DMA_CH3_AL2_WRITE_ADDR_TRIG_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH3_AL3_CTRL -// Description : Alias for channel 3 CTRL register -#define DMA_CH3_AL3_CTRL_OFFSET _u(0x000000f0) -#define DMA_CH3_AL3_CTRL_BITS _u(0xffffffff) -#define DMA_CH3_AL3_CTRL_RESET "-" -#define DMA_CH3_AL3_CTRL_MSB _u(31) -#define DMA_CH3_AL3_CTRL_LSB _u(0) -#define DMA_CH3_AL3_CTRL_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH3_AL3_WRITE_ADDR -// Description : Alias for channel 3 WRITE_ADDR register -#define DMA_CH3_AL3_WRITE_ADDR_OFFSET _u(0x000000f4) -#define DMA_CH3_AL3_WRITE_ADDR_BITS _u(0xffffffff) -#define DMA_CH3_AL3_WRITE_ADDR_RESET "-" -#define DMA_CH3_AL3_WRITE_ADDR_MSB _u(31) -#define DMA_CH3_AL3_WRITE_ADDR_LSB _u(0) -#define DMA_CH3_AL3_WRITE_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH3_AL3_TRANS_COUNT -// Description : Alias for channel 3 TRANS_COUNT register -#define DMA_CH3_AL3_TRANS_COUNT_OFFSET _u(0x000000f8) -#define DMA_CH3_AL3_TRANS_COUNT_BITS _u(0xffffffff) -#define DMA_CH3_AL3_TRANS_COUNT_RESET "-" -#define DMA_CH3_AL3_TRANS_COUNT_MSB _u(31) -#define DMA_CH3_AL3_TRANS_COUNT_LSB _u(0) -#define DMA_CH3_AL3_TRANS_COUNT_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH3_AL3_READ_ADDR_TRIG -// Description : Alias for channel 3 READ_ADDR register -// This is a trigger register (0xc). Writing a nonzero value will -// reload the channel counter and start the channel. -#define DMA_CH3_AL3_READ_ADDR_TRIG_OFFSET _u(0x000000fc) -#define DMA_CH3_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff) -#define DMA_CH3_AL3_READ_ADDR_TRIG_RESET "-" -#define DMA_CH3_AL3_READ_ADDR_TRIG_MSB _u(31) -#define DMA_CH3_AL3_READ_ADDR_TRIG_LSB _u(0) -#define DMA_CH3_AL3_READ_ADDR_TRIG_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH4_READ_ADDR -// Description : DMA Channel 4 Read Address pointer -// This register updates automatically each time a read completes. -// The current value is the next address to be read by this -// channel. -#define DMA_CH4_READ_ADDR_OFFSET _u(0x00000100) -#define DMA_CH4_READ_ADDR_BITS _u(0xffffffff) -#define DMA_CH4_READ_ADDR_RESET _u(0x00000000) -#define DMA_CH4_READ_ADDR_MSB _u(31) -#define DMA_CH4_READ_ADDR_LSB _u(0) -#define DMA_CH4_READ_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH4_WRITE_ADDR -// Description : DMA Channel 4 Write Address pointer -// This register updates automatically each time a write -// completes. The current value is the next address to be written -// by this channel. -#define DMA_CH4_WRITE_ADDR_OFFSET _u(0x00000104) -#define DMA_CH4_WRITE_ADDR_BITS _u(0xffffffff) -#define DMA_CH4_WRITE_ADDR_RESET _u(0x00000000) -#define DMA_CH4_WRITE_ADDR_MSB _u(31) -#define DMA_CH4_WRITE_ADDR_LSB _u(0) -#define DMA_CH4_WRITE_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH4_TRANS_COUNT -// Description : DMA Channel 4 Transfer Count -#define DMA_CH4_TRANS_COUNT_OFFSET _u(0x00000108) -#define DMA_CH4_TRANS_COUNT_BITS _u(0xffffffff) -#define DMA_CH4_TRANS_COUNT_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : DMA_CH4_TRANS_COUNT_MODE -// Description : When MODE is 0x0, the transfer count decrements with each -// transfer until 0, and then the channel triggers the next -// channel indicated by CTRL_CHAIN_TO. -// -// When MODE is 0x1, the transfer count decrements with each -// transfer until 0, and then the channel re-triggers itself, in -// addition to the trigger indicated by CTRL_CHAIN_TO. This is -// useful for e.g. an endless ring-buffer DMA with periodic -// interrupts. -// -// When MODE is 0xf, the transfer count does not decrement. The -// DMA channel performs an endless sequence of transfers, never -// triggering other channels or raising interrupts, until an ABORT -// is raised. -// -// All other values are reserved. -// 0x0 -> NORMAL -// 0x1 -> TRIGGER_SELF -// 0xf -> ENDLESS -#define DMA_CH4_TRANS_COUNT_MODE_RESET _u(0x0) -#define DMA_CH4_TRANS_COUNT_MODE_BITS _u(0xf0000000) -#define DMA_CH4_TRANS_COUNT_MODE_MSB _u(31) -#define DMA_CH4_TRANS_COUNT_MODE_LSB _u(28) -#define DMA_CH4_TRANS_COUNT_MODE_ACCESS "RW" -#define DMA_CH4_TRANS_COUNT_MODE_VALUE_NORMAL _u(0x0) -#define DMA_CH4_TRANS_COUNT_MODE_VALUE_TRIGGER_SELF _u(0x1) -#define DMA_CH4_TRANS_COUNT_MODE_VALUE_ENDLESS _u(0xf) -// ----------------------------------------------------------------------------- -// Field : DMA_CH4_TRANS_COUNT_COUNT -// Description : 28-bit transfer count (256 million transfers maximum). -// -// Program the number of bus transfers a channel will perform -// before halting. Note that, if transfers are larger than one -// byte in size, this is not equal to the number of bytes -// transferred (see CTRL_DATA_SIZE). -// -// When the channel is active, reading this register shows the -// number of transfers remaining, updating automatically each time -// a write transfer completes. -// -// Writing this register sets the RELOAD value for the transfer -// counter. Each time this channel is triggered, the RELOAD value -// is copied into the live transfer counter. The channel can be -// started multiple times, and will perform the same number of -// transfers each time, as programmed by most recent write. -// -// The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT -// is used as a trigger, the written value is used immediately as -// the length of the new transfer sequence, as well as being -// written to RELOAD. -#define DMA_CH4_TRANS_COUNT_COUNT_RESET _u(0x0000000) -#define DMA_CH4_TRANS_COUNT_COUNT_BITS _u(0x0fffffff) -#define DMA_CH4_TRANS_COUNT_COUNT_MSB _u(27) -#define DMA_CH4_TRANS_COUNT_COUNT_LSB _u(0) -#define DMA_CH4_TRANS_COUNT_COUNT_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH4_CTRL_TRIG -// Description : DMA Channel 4 Control and Status -#define DMA_CH4_CTRL_TRIG_OFFSET _u(0x0000010c) -#define DMA_CH4_CTRL_TRIG_BITS _u(0xe7ffffff) -#define DMA_CH4_CTRL_TRIG_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : DMA_CH4_CTRL_TRIG_AHB_ERROR -// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel -// halts when it encounters any bus error, and always raises its -// channel IRQ flag. -#define DMA_CH4_CTRL_TRIG_AHB_ERROR_RESET _u(0x0) -#define DMA_CH4_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000) -#define DMA_CH4_CTRL_TRIG_AHB_ERROR_MSB _u(31) -#define DMA_CH4_CTRL_TRIG_AHB_ERROR_LSB _u(31) -#define DMA_CH4_CTRL_TRIG_AHB_ERROR_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : DMA_CH4_CTRL_TRIG_READ_ERROR -// Description : If 1, the channel received a read bus error. Write one to -// clear. -// READ_ADDR shows the approximate address where the bus error was -// encountered (will not be earlier, or more than 3 transfers -// later) -#define DMA_CH4_CTRL_TRIG_READ_ERROR_RESET _u(0x0) -#define DMA_CH4_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000) -#define DMA_CH4_CTRL_TRIG_READ_ERROR_MSB _u(30) -#define DMA_CH4_CTRL_TRIG_READ_ERROR_LSB _u(30) -#define DMA_CH4_CTRL_TRIG_READ_ERROR_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : DMA_CH4_CTRL_TRIG_WRITE_ERROR -// Description : If 1, the channel received a write bus error. Write one to -// clear. -// WRITE_ADDR shows the approximate address where the bus error -// was encountered (will not be earlier, or more than 5 transfers -// later) -#define DMA_CH4_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0) -#define DMA_CH4_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000) -#define DMA_CH4_CTRL_TRIG_WRITE_ERROR_MSB _u(29) -#define DMA_CH4_CTRL_TRIG_WRITE_ERROR_LSB _u(29) -#define DMA_CH4_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : DMA_CH4_CTRL_TRIG_BUSY -// Description : This flag goes high when the channel starts a new transfer -// sequence, and low when the last transfer of that sequence -// completes. Clearing EN while BUSY is high pauses the channel, -// and BUSY will stay high while paused. -// -// To terminate a sequence early (and clear the BUSY flag), see -// CHAN_ABORT. -#define DMA_CH4_CTRL_TRIG_BUSY_RESET _u(0x0) -#define DMA_CH4_CTRL_TRIG_BUSY_BITS _u(0x04000000) -#define DMA_CH4_CTRL_TRIG_BUSY_MSB _u(26) -#define DMA_CH4_CTRL_TRIG_BUSY_LSB _u(26) -#define DMA_CH4_CTRL_TRIG_BUSY_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : DMA_CH4_CTRL_TRIG_SNIFF_EN -// Description : If 1, this channel's data transfers are visible to the sniff -// hardware, and each transfer will advance the state of the -// checksum. This only applies if the sniff hardware is enabled, -// and has this channel selected. -// -// This allows checksum to be enabled or disabled on a per- -// control- block basis. -#define DMA_CH4_CTRL_TRIG_SNIFF_EN_RESET _u(0x0) -#define DMA_CH4_CTRL_TRIG_SNIFF_EN_BITS _u(0x02000000) -#define DMA_CH4_CTRL_TRIG_SNIFF_EN_MSB _u(25) -#define DMA_CH4_CTRL_TRIG_SNIFF_EN_LSB _u(25) -#define DMA_CH4_CTRL_TRIG_SNIFF_EN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH4_CTRL_TRIG_BSWAP -// Description : Apply byte-swap transformation to DMA data. -// For byte data, this has no effect. For halfword data, the two -// bytes of each halfword are swapped. For word data, the four -// bytes of each word are swapped to reverse order. -#define DMA_CH4_CTRL_TRIG_BSWAP_RESET _u(0x0) -#define DMA_CH4_CTRL_TRIG_BSWAP_BITS _u(0x01000000) -#define DMA_CH4_CTRL_TRIG_BSWAP_MSB _u(24) -#define DMA_CH4_CTRL_TRIG_BSWAP_LSB _u(24) -#define DMA_CH4_CTRL_TRIG_BSWAP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH4_CTRL_TRIG_IRQ_QUIET -// Description : In QUIET mode, the channel does not generate IRQs at the end of -// every transfer block. Instead, an IRQ is raised when NULL is -// written to a trigger register, indicating the end of a control -// block chain. -// -// This reduces the number of interrupts to be serviced by the CPU -// when transferring a DMA chain of many small control blocks. -#define DMA_CH4_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0) -#define DMA_CH4_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00800000) -#define DMA_CH4_CTRL_TRIG_IRQ_QUIET_MSB _u(23) -#define DMA_CH4_CTRL_TRIG_IRQ_QUIET_LSB _u(23) -#define DMA_CH4_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH4_CTRL_TRIG_TREQ_SEL -// Description : Select a Transfer Request signal. -// The channel uses the transfer request signal to pace its data -// transfer rate. Sources for TREQ signals are internal (TIMERS) -// or external (DREQ, a Data Request from the system). -// 0x0 to 0x3a -> select DREQ n as TREQ -// 0x3b -> Select Timer 0 as TREQ -// 0x3c -> Select Timer 1 as TREQ -// 0x3d -> Select Timer 2 as TREQ (Optional) -// 0x3e -> Select Timer 3 as TREQ (Optional) -// 0x3f -> Permanent request, for unpaced transfers. -#define DMA_CH4_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) -#define DMA_CH4_CTRL_TRIG_TREQ_SEL_BITS _u(0x007e0000) -#define DMA_CH4_CTRL_TRIG_TREQ_SEL_MSB _u(22) -#define DMA_CH4_CTRL_TRIG_TREQ_SEL_LSB _u(17) -#define DMA_CH4_CTRL_TRIG_TREQ_SEL_ACCESS "RW" -#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) -#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) -#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) -#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) -#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) -// ----------------------------------------------------------------------------- -// Field : DMA_CH4_CTRL_TRIG_CHAIN_TO -// Description : When this channel completes, it will trigger the channel -// indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this -// channel)_. -// -// Note this field resets to 0, so channels 1 and above will chain -// to channel 0 by default. Set this field to avoid this -// behaviour. -#define DMA_CH4_CTRL_TRIG_CHAIN_TO_RESET _u(0x0) -#define DMA_CH4_CTRL_TRIG_CHAIN_TO_BITS _u(0x0001e000) -#define DMA_CH4_CTRL_TRIG_CHAIN_TO_MSB _u(16) -#define DMA_CH4_CTRL_TRIG_CHAIN_TO_LSB _u(13) -#define DMA_CH4_CTRL_TRIG_CHAIN_TO_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH4_CTRL_TRIG_RING_SEL -// Description : Select whether RING_SIZE applies to read or write addresses. -// If 0, read addresses are wrapped on a (1 << RING_SIZE) -// boundary. If 1, write addresses are wrapped. -#define DMA_CH4_CTRL_TRIG_RING_SEL_RESET _u(0x0) -#define DMA_CH4_CTRL_TRIG_RING_SEL_BITS _u(0x00001000) -#define DMA_CH4_CTRL_TRIG_RING_SEL_MSB _u(12) -#define DMA_CH4_CTRL_TRIG_RING_SEL_LSB _u(12) -#define DMA_CH4_CTRL_TRIG_RING_SEL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH4_CTRL_TRIG_RING_SIZE -// Description : Size of address wrap region. If 0, don't wrap. For values n > -// 0, only the lower n bits of the address will change. This wraps -// the address on a (1 << n) byte boundary, facilitating access to -// naturally-aligned ring buffers. -// -// Ring sizes between 2 and 32768 bytes are possible. This can -// apply to either read or write addresses, based on value of -// RING_SEL. -// 0x0 -> RING_NONE -#define DMA_CH4_CTRL_TRIG_RING_SIZE_RESET _u(0x0) -#define DMA_CH4_CTRL_TRIG_RING_SIZE_BITS _u(0x00000f00) -#define DMA_CH4_CTRL_TRIG_RING_SIZE_MSB _u(11) -#define DMA_CH4_CTRL_TRIG_RING_SIZE_LSB _u(8) -#define DMA_CH4_CTRL_TRIG_RING_SIZE_ACCESS "RW" -#define DMA_CH4_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0) -// ----------------------------------------------------------------------------- -// Field : DMA_CH4_CTRL_TRIG_INCR_WRITE_REV -// Description : If 1, and INCR_WRITE is 1, the write address is decremented -// rather than incremented with each transfer. -// -// If 1, and INCR_WRITE is 0, this otherwise-unused combination -// causes the write address to be incremented by twice the -// transfer size, i.e. skipping over alternate addresses. -#define DMA_CH4_CTRL_TRIG_INCR_WRITE_REV_RESET _u(0x0) -#define DMA_CH4_CTRL_TRIG_INCR_WRITE_REV_BITS _u(0x00000080) -#define DMA_CH4_CTRL_TRIG_INCR_WRITE_REV_MSB _u(7) -#define DMA_CH4_CTRL_TRIG_INCR_WRITE_REV_LSB _u(7) -#define DMA_CH4_CTRL_TRIG_INCR_WRITE_REV_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH4_CTRL_TRIG_INCR_WRITE -// Description : If 1, the write address increments with each transfer. If 0, -// each write is directed to the same, initial address. -// -// Generally this should be disabled for memory-to-peripheral -// transfers. -#define DMA_CH4_CTRL_TRIG_INCR_WRITE_RESET _u(0x0) -#define DMA_CH4_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000040) -#define DMA_CH4_CTRL_TRIG_INCR_WRITE_MSB _u(6) -#define DMA_CH4_CTRL_TRIG_INCR_WRITE_LSB _u(6) -#define DMA_CH4_CTRL_TRIG_INCR_WRITE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH4_CTRL_TRIG_INCR_READ_REV -// Description : If 1, and INCR_READ is 1, the read address is decremented -// rather than incremented with each transfer. -// -// If 1, and INCR_READ is 0, this otherwise-unused combination -// causes the read address to be incremented by twice the transfer -// size, i.e. skipping over alternate addresses. -#define DMA_CH4_CTRL_TRIG_INCR_READ_REV_RESET _u(0x0) -#define DMA_CH4_CTRL_TRIG_INCR_READ_REV_BITS _u(0x00000020) -#define DMA_CH4_CTRL_TRIG_INCR_READ_REV_MSB _u(5) -#define DMA_CH4_CTRL_TRIG_INCR_READ_REV_LSB _u(5) -#define DMA_CH4_CTRL_TRIG_INCR_READ_REV_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH4_CTRL_TRIG_INCR_READ -// Description : If 1, the read address increments with each transfer. If 0, -// each read is directed to the same, initial address. -// -// Generally this should be disabled for peripheral-to-memory -// transfers. -#define DMA_CH4_CTRL_TRIG_INCR_READ_RESET _u(0x0) -#define DMA_CH4_CTRL_TRIG_INCR_READ_BITS _u(0x00000010) -#define DMA_CH4_CTRL_TRIG_INCR_READ_MSB _u(4) -#define DMA_CH4_CTRL_TRIG_INCR_READ_LSB _u(4) -#define DMA_CH4_CTRL_TRIG_INCR_READ_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH4_CTRL_TRIG_DATA_SIZE -// Description : Set the size of each bus transfer (byte/halfword/word). -// READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) -// with each transfer. -// 0x0 -> SIZE_BYTE -// 0x1 -> SIZE_HALFWORD -// 0x2 -> SIZE_WORD -#define DMA_CH4_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) -#define DMA_CH4_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) -#define DMA_CH4_CTRL_TRIG_DATA_SIZE_MSB _u(3) -#define DMA_CH4_CTRL_TRIG_DATA_SIZE_LSB _u(2) -#define DMA_CH4_CTRL_TRIG_DATA_SIZE_ACCESS "RW" -#define DMA_CH4_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) -#define DMA_CH4_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1) -#define DMA_CH4_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) -// ----------------------------------------------------------------------------- -// Field : DMA_CH4_CTRL_TRIG_HIGH_PRIORITY -// Description : HIGH_PRIORITY gives a channel preferential treatment in issue -// scheduling: in each scheduling round, all high priority -// channels are considered first, and then only a single low -// priority channel, before returning to the high priority -// channels. -// -// This only affects the order in which the DMA schedules -// channels. The DMA's bus priority is not changed. If the DMA is -// not saturated then a low priority channel will see no loss of -// throughput. -#define DMA_CH4_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0) -#define DMA_CH4_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002) -#define DMA_CH4_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1) -#define DMA_CH4_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1) -#define DMA_CH4_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH4_CTRL_TRIG_EN -// Description : DMA Channel Enable. -// When 1, the channel will respond to triggering events, which -// will cause it to become BUSY and start transferring data. When -// 0, the channel will ignore triggers, stop issuing transfers, -// and pause the current transfer sequence (i.e. BUSY will remain -// high if already high) -#define DMA_CH4_CTRL_TRIG_EN_RESET _u(0x0) -#define DMA_CH4_CTRL_TRIG_EN_BITS _u(0x00000001) -#define DMA_CH4_CTRL_TRIG_EN_MSB _u(0) -#define DMA_CH4_CTRL_TRIG_EN_LSB _u(0) -#define DMA_CH4_CTRL_TRIG_EN_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH4_AL1_CTRL -// Description : Alias for channel 4 CTRL register -#define DMA_CH4_AL1_CTRL_OFFSET _u(0x00000110) -#define DMA_CH4_AL1_CTRL_BITS _u(0xffffffff) -#define DMA_CH4_AL1_CTRL_RESET "-" -#define DMA_CH4_AL1_CTRL_MSB _u(31) -#define DMA_CH4_AL1_CTRL_LSB _u(0) -#define DMA_CH4_AL1_CTRL_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH4_AL1_READ_ADDR -// Description : Alias for channel 4 READ_ADDR register -#define DMA_CH4_AL1_READ_ADDR_OFFSET _u(0x00000114) -#define DMA_CH4_AL1_READ_ADDR_BITS _u(0xffffffff) -#define DMA_CH4_AL1_READ_ADDR_RESET "-" -#define DMA_CH4_AL1_READ_ADDR_MSB _u(31) -#define DMA_CH4_AL1_READ_ADDR_LSB _u(0) -#define DMA_CH4_AL1_READ_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH4_AL1_WRITE_ADDR -// Description : Alias for channel 4 WRITE_ADDR register -#define DMA_CH4_AL1_WRITE_ADDR_OFFSET _u(0x00000118) -#define DMA_CH4_AL1_WRITE_ADDR_BITS _u(0xffffffff) -#define DMA_CH4_AL1_WRITE_ADDR_RESET "-" -#define DMA_CH4_AL1_WRITE_ADDR_MSB _u(31) -#define DMA_CH4_AL1_WRITE_ADDR_LSB _u(0) -#define DMA_CH4_AL1_WRITE_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH4_AL1_TRANS_COUNT_TRIG -// Description : Alias for channel 4 TRANS_COUNT register -// This is a trigger register (0xc). Writing a nonzero value will -// reload the channel counter and start the channel. -#define DMA_CH4_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x0000011c) -#define DMA_CH4_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff) -#define DMA_CH4_AL1_TRANS_COUNT_TRIG_RESET "-" -#define DMA_CH4_AL1_TRANS_COUNT_TRIG_MSB _u(31) -#define DMA_CH4_AL1_TRANS_COUNT_TRIG_LSB _u(0) -#define DMA_CH4_AL1_TRANS_COUNT_TRIG_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH4_AL2_CTRL -// Description : Alias for channel 4 CTRL register -#define DMA_CH4_AL2_CTRL_OFFSET _u(0x00000120) -#define DMA_CH4_AL2_CTRL_BITS _u(0xffffffff) -#define DMA_CH4_AL2_CTRL_RESET "-" -#define DMA_CH4_AL2_CTRL_MSB _u(31) -#define DMA_CH4_AL2_CTRL_LSB _u(0) -#define DMA_CH4_AL2_CTRL_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH4_AL2_TRANS_COUNT -// Description : Alias for channel 4 TRANS_COUNT register -#define DMA_CH4_AL2_TRANS_COUNT_OFFSET _u(0x00000124) -#define DMA_CH4_AL2_TRANS_COUNT_BITS _u(0xffffffff) -#define DMA_CH4_AL2_TRANS_COUNT_RESET "-" -#define DMA_CH4_AL2_TRANS_COUNT_MSB _u(31) -#define DMA_CH4_AL2_TRANS_COUNT_LSB _u(0) -#define DMA_CH4_AL2_TRANS_COUNT_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH4_AL2_READ_ADDR -// Description : Alias for channel 4 READ_ADDR register -#define DMA_CH4_AL2_READ_ADDR_OFFSET _u(0x00000128) -#define DMA_CH4_AL2_READ_ADDR_BITS _u(0xffffffff) -#define DMA_CH4_AL2_READ_ADDR_RESET "-" -#define DMA_CH4_AL2_READ_ADDR_MSB _u(31) -#define DMA_CH4_AL2_READ_ADDR_LSB _u(0) -#define DMA_CH4_AL2_READ_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH4_AL2_WRITE_ADDR_TRIG -// Description : Alias for channel 4 WRITE_ADDR register -// This is a trigger register (0xc). Writing a nonzero value will -// reload the channel counter and start the channel. -#define DMA_CH4_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x0000012c) -#define DMA_CH4_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff) -#define DMA_CH4_AL2_WRITE_ADDR_TRIG_RESET "-" -#define DMA_CH4_AL2_WRITE_ADDR_TRIG_MSB _u(31) -#define DMA_CH4_AL2_WRITE_ADDR_TRIG_LSB _u(0) -#define DMA_CH4_AL2_WRITE_ADDR_TRIG_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH4_AL3_CTRL -// Description : Alias for channel 4 CTRL register -#define DMA_CH4_AL3_CTRL_OFFSET _u(0x00000130) -#define DMA_CH4_AL3_CTRL_BITS _u(0xffffffff) -#define DMA_CH4_AL3_CTRL_RESET "-" -#define DMA_CH4_AL3_CTRL_MSB _u(31) -#define DMA_CH4_AL3_CTRL_LSB _u(0) -#define DMA_CH4_AL3_CTRL_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH4_AL3_WRITE_ADDR -// Description : Alias for channel 4 WRITE_ADDR register -#define DMA_CH4_AL3_WRITE_ADDR_OFFSET _u(0x00000134) -#define DMA_CH4_AL3_WRITE_ADDR_BITS _u(0xffffffff) -#define DMA_CH4_AL3_WRITE_ADDR_RESET "-" -#define DMA_CH4_AL3_WRITE_ADDR_MSB _u(31) -#define DMA_CH4_AL3_WRITE_ADDR_LSB _u(0) -#define DMA_CH4_AL3_WRITE_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH4_AL3_TRANS_COUNT -// Description : Alias for channel 4 TRANS_COUNT register -#define DMA_CH4_AL3_TRANS_COUNT_OFFSET _u(0x00000138) -#define DMA_CH4_AL3_TRANS_COUNT_BITS _u(0xffffffff) -#define DMA_CH4_AL3_TRANS_COUNT_RESET "-" -#define DMA_CH4_AL3_TRANS_COUNT_MSB _u(31) -#define DMA_CH4_AL3_TRANS_COUNT_LSB _u(0) -#define DMA_CH4_AL3_TRANS_COUNT_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH4_AL3_READ_ADDR_TRIG -// Description : Alias for channel 4 READ_ADDR register -// This is a trigger register (0xc). Writing a nonzero value will -// reload the channel counter and start the channel. -#define DMA_CH4_AL3_READ_ADDR_TRIG_OFFSET _u(0x0000013c) -#define DMA_CH4_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff) -#define DMA_CH4_AL3_READ_ADDR_TRIG_RESET "-" -#define DMA_CH4_AL3_READ_ADDR_TRIG_MSB _u(31) -#define DMA_CH4_AL3_READ_ADDR_TRIG_LSB _u(0) -#define DMA_CH4_AL3_READ_ADDR_TRIG_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH5_READ_ADDR -// Description : DMA Channel 5 Read Address pointer -// This register updates automatically each time a read completes. -// The current value is the next address to be read by this -// channel. -#define DMA_CH5_READ_ADDR_OFFSET _u(0x00000140) -#define DMA_CH5_READ_ADDR_BITS _u(0xffffffff) -#define DMA_CH5_READ_ADDR_RESET _u(0x00000000) -#define DMA_CH5_READ_ADDR_MSB _u(31) -#define DMA_CH5_READ_ADDR_LSB _u(0) -#define DMA_CH5_READ_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH5_WRITE_ADDR -// Description : DMA Channel 5 Write Address pointer -// This register updates automatically each time a write -// completes. The current value is the next address to be written -// by this channel. -#define DMA_CH5_WRITE_ADDR_OFFSET _u(0x00000144) -#define DMA_CH5_WRITE_ADDR_BITS _u(0xffffffff) -#define DMA_CH5_WRITE_ADDR_RESET _u(0x00000000) -#define DMA_CH5_WRITE_ADDR_MSB _u(31) -#define DMA_CH5_WRITE_ADDR_LSB _u(0) -#define DMA_CH5_WRITE_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH5_TRANS_COUNT -// Description : DMA Channel 5 Transfer Count -#define DMA_CH5_TRANS_COUNT_OFFSET _u(0x00000148) -#define DMA_CH5_TRANS_COUNT_BITS _u(0xffffffff) -#define DMA_CH5_TRANS_COUNT_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : DMA_CH5_TRANS_COUNT_MODE -// Description : When MODE is 0x0, the transfer count decrements with each -// transfer until 0, and then the channel triggers the next -// channel indicated by CTRL_CHAIN_TO. -// -// When MODE is 0x1, the transfer count decrements with each -// transfer until 0, and then the channel re-triggers itself, in -// addition to the trigger indicated by CTRL_CHAIN_TO. This is -// useful for e.g. an endless ring-buffer DMA with periodic -// interrupts. -// -// When MODE is 0xf, the transfer count does not decrement. The -// DMA channel performs an endless sequence of transfers, never -// triggering other channels or raising interrupts, until an ABORT -// is raised. -// -// All other values are reserved. -// 0x0 -> NORMAL -// 0x1 -> TRIGGER_SELF -// 0xf -> ENDLESS -#define DMA_CH5_TRANS_COUNT_MODE_RESET _u(0x0) -#define DMA_CH5_TRANS_COUNT_MODE_BITS _u(0xf0000000) -#define DMA_CH5_TRANS_COUNT_MODE_MSB _u(31) -#define DMA_CH5_TRANS_COUNT_MODE_LSB _u(28) -#define DMA_CH5_TRANS_COUNT_MODE_ACCESS "RW" -#define DMA_CH5_TRANS_COUNT_MODE_VALUE_NORMAL _u(0x0) -#define DMA_CH5_TRANS_COUNT_MODE_VALUE_TRIGGER_SELF _u(0x1) -#define DMA_CH5_TRANS_COUNT_MODE_VALUE_ENDLESS _u(0xf) -// ----------------------------------------------------------------------------- -// Field : DMA_CH5_TRANS_COUNT_COUNT -// Description : 28-bit transfer count (256 million transfers maximum). -// -// Program the number of bus transfers a channel will perform -// before halting. Note that, if transfers are larger than one -// byte in size, this is not equal to the number of bytes -// transferred (see CTRL_DATA_SIZE). -// -// When the channel is active, reading this register shows the -// number of transfers remaining, updating automatically each time -// a write transfer completes. -// -// Writing this register sets the RELOAD value for the transfer -// counter. Each time this channel is triggered, the RELOAD value -// is copied into the live transfer counter. The channel can be -// started multiple times, and will perform the same number of -// transfers each time, as programmed by most recent write. -// -// The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT -// is used as a trigger, the written value is used immediately as -// the length of the new transfer sequence, as well as being -// written to RELOAD. -#define DMA_CH5_TRANS_COUNT_COUNT_RESET _u(0x0000000) -#define DMA_CH5_TRANS_COUNT_COUNT_BITS _u(0x0fffffff) -#define DMA_CH5_TRANS_COUNT_COUNT_MSB _u(27) -#define DMA_CH5_TRANS_COUNT_COUNT_LSB _u(0) -#define DMA_CH5_TRANS_COUNT_COUNT_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH5_CTRL_TRIG -// Description : DMA Channel 5 Control and Status -#define DMA_CH5_CTRL_TRIG_OFFSET _u(0x0000014c) -#define DMA_CH5_CTRL_TRIG_BITS _u(0xe7ffffff) -#define DMA_CH5_CTRL_TRIG_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : DMA_CH5_CTRL_TRIG_AHB_ERROR -// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel -// halts when it encounters any bus error, and always raises its -// channel IRQ flag. -#define DMA_CH5_CTRL_TRIG_AHB_ERROR_RESET _u(0x0) -#define DMA_CH5_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000) -#define DMA_CH5_CTRL_TRIG_AHB_ERROR_MSB _u(31) -#define DMA_CH5_CTRL_TRIG_AHB_ERROR_LSB _u(31) -#define DMA_CH5_CTRL_TRIG_AHB_ERROR_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : DMA_CH5_CTRL_TRIG_READ_ERROR -// Description : If 1, the channel received a read bus error. Write one to -// clear. -// READ_ADDR shows the approximate address where the bus error was -// encountered (will not be earlier, or more than 3 transfers -// later) -#define DMA_CH5_CTRL_TRIG_READ_ERROR_RESET _u(0x0) -#define DMA_CH5_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000) -#define DMA_CH5_CTRL_TRIG_READ_ERROR_MSB _u(30) -#define DMA_CH5_CTRL_TRIG_READ_ERROR_LSB _u(30) -#define DMA_CH5_CTRL_TRIG_READ_ERROR_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : DMA_CH5_CTRL_TRIG_WRITE_ERROR -// Description : If 1, the channel received a write bus error. Write one to -// clear. -// WRITE_ADDR shows the approximate address where the bus error -// was encountered (will not be earlier, or more than 5 transfers -// later) -#define DMA_CH5_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0) -#define DMA_CH5_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000) -#define DMA_CH5_CTRL_TRIG_WRITE_ERROR_MSB _u(29) -#define DMA_CH5_CTRL_TRIG_WRITE_ERROR_LSB _u(29) -#define DMA_CH5_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : DMA_CH5_CTRL_TRIG_BUSY -// Description : This flag goes high when the channel starts a new transfer -// sequence, and low when the last transfer of that sequence -// completes. Clearing EN while BUSY is high pauses the channel, -// and BUSY will stay high while paused. -// -// To terminate a sequence early (and clear the BUSY flag), see -// CHAN_ABORT. -#define DMA_CH5_CTRL_TRIG_BUSY_RESET _u(0x0) -#define DMA_CH5_CTRL_TRIG_BUSY_BITS _u(0x04000000) -#define DMA_CH5_CTRL_TRIG_BUSY_MSB _u(26) -#define DMA_CH5_CTRL_TRIG_BUSY_LSB _u(26) -#define DMA_CH5_CTRL_TRIG_BUSY_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : DMA_CH5_CTRL_TRIG_SNIFF_EN -// Description : If 1, this channel's data transfers are visible to the sniff -// hardware, and each transfer will advance the state of the -// checksum. This only applies if the sniff hardware is enabled, -// and has this channel selected. -// -// This allows checksum to be enabled or disabled on a per- -// control- block basis. -#define DMA_CH5_CTRL_TRIG_SNIFF_EN_RESET _u(0x0) -#define DMA_CH5_CTRL_TRIG_SNIFF_EN_BITS _u(0x02000000) -#define DMA_CH5_CTRL_TRIG_SNIFF_EN_MSB _u(25) -#define DMA_CH5_CTRL_TRIG_SNIFF_EN_LSB _u(25) -#define DMA_CH5_CTRL_TRIG_SNIFF_EN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH5_CTRL_TRIG_BSWAP -// Description : Apply byte-swap transformation to DMA data. -// For byte data, this has no effect. For halfword data, the two -// bytes of each halfword are swapped. For word data, the four -// bytes of each word are swapped to reverse order. -#define DMA_CH5_CTRL_TRIG_BSWAP_RESET _u(0x0) -#define DMA_CH5_CTRL_TRIG_BSWAP_BITS _u(0x01000000) -#define DMA_CH5_CTRL_TRIG_BSWAP_MSB _u(24) -#define DMA_CH5_CTRL_TRIG_BSWAP_LSB _u(24) -#define DMA_CH5_CTRL_TRIG_BSWAP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH5_CTRL_TRIG_IRQ_QUIET -// Description : In QUIET mode, the channel does not generate IRQs at the end of -// every transfer block. Instead, an IRQ is raised when NULL is -// written to a trigger register, indicating the end of a control -// block chain. -// -// This reduces the number of interrupts to be serviced by the CPU -// when transferring a DMA chain of many small control blocks. -#define DMA_CH5_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0) -#define DMA_CH5_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00800000) -#define DMA_CH5_CTRL_TRIG_IRQ_QUIET_MSB _u(23) -#define DMA_CH5_CTRL_TRIG_IRQ_QUIET_LSB _u(23) -#define DMA_CH5_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH5_CTRL_TRIG_TREQ_SEL -// Description : Select a Transfer Request signal. -// The channel uses the transfer request signal to pace its data -// transfer rate. Sources for TREQ signals are internal (TIMERS) -// or external (DREQ, a Data Request from the system). -// 0x0 to 0x3a -> select DREQ n as TREQ -// 0x3b -> Select Timer 0 as TREQ -// 0x3c -> Select Timer 1 as TREQ -// 0x3d -> Select Timer 2 as TREQ (Optional) -// 0x3e -> Select Timer 3 as TREQ (Optional) -// 0x3f -> Permanent request, for unpaced transfers. -#define DMA_CH5_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) -#define DMA_CH5_CTRL_TRIG_TREQ_SEL_BITS _u(0x007e0000) -#define DMA_CH5_CTRL_TRIG_TREQ_SEL_MSB _u(22) -#define DMA_CH5_CTRL_TRIG_TREQ_SEL_LSB _u(17) -#define DMA_CH5_CTRL_TRIG_TREQ_SEL_ACCESS "RW" -#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) -#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) -#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) -#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) -#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) -// ----------------------------------------------------------------------------- -// Field : DMA_CH5_CTRL_TRIG_CHAIN_TO -// Description : When this channel completes, it will trigger the channel -// indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this -// channel)_. -// -// Note this field resets to 0, so channels 1 and above will chain -// to channel 0 by default. Set this field to avoid this -// behaviour. -#define DMA_CH5_CTRL_TRIG_CHAIN_TO_RESET _u(0x0) -#define DMA_CH5_CTRL_TRIG_CHAIN_TO_BITS _u(0x0001e000) -#define DMA_CH5_CTRL_TRIG_CHAIN_TO_MSB _u(16) -#define DMA_CH5_CTRL_TRIG_CHAIN_TO_LSB _u(13) -#define DMA_CH5_CTRL_TRIG_CHAIN_TO_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH5_CTRL_TRIG_RING_SEL -// Description : Select whether RING_SIZE applies to read or write addresses. -// If 0, read addresses are wrapped on a (1 << RING_SIZE) -// boundary. If 1, write addresses are wrapped. -#define DMA_CH5_CTRL_TRIG_RING_SEL_RESET _u(0x0) -#define DMA_CH5_CTRL_TRIG_RING_SEL_BITS _u(0x00001000) -#define DMA_CH5_CTRL_TRIG_RING_SEL_MSB _u(12) -#define DMA_CH5_CTRL_TRIG_RING_SEL_LSB _u(12) -#define DMA_CH5_CTRL_TRIG_RING_SEL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH5_CTRL_TRIG_RING_SIZE -// Description : Size of address wrap region. If 0, don't wrap. For values n > -// 0, only the lower n bits of the address will change. This wraps -// the address on a (1 << n) byte boundary, facilitating access to -// naturally-aligned ring buffers. -// -// Ring sizes between 2 and 32768 bytes are possible. This can -// apply to either read or write addresses, based on value of -// RING_SEL. -// 0x0 -> RING_NONE -#define DMA_CH5_CTRL_TRIG_RING_SIZE_RESET _u(0x0) -#define DMA_CH5_CTRL_TRIG_RING_SIZE_BITS _u(0x00000f00) -#define DMA_CH5_CTRL_TRIG_RING_SIZE_MSB _u(11) -#define DMA_CH5_CTRL_TRIG_RING_SIZE_LSB _u(8) -#define DMA_CH5_CTRL_TRIG_RING_SIZE_ACCESS "RW" -#define DMA_CH5_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0) -// ----------------------------------------------------------------------------- -// Field : DMA_CH5_CTRL_TRIG_INCR_WRITE_REV -// Description : If 1, and INCR_WRITE is 1, the write address is decremented -// rather than incremented with each transfer. -// -// If 1, and INCR_WRITE is 0, this otherwise-unused combination -// causes the write address to be incremented by twice the -// transfer size, i.e. skipping over alternate addresses. -#define DMA_CH5_CTRL_TRIG_INCR_WRITE_REV_RESET _u(0x0) -#define DMA_CH5_CTRL_TRIG_INCR_WRITE_REV_BITS _u(0x00000080) -#define DMA_CH5_CTRL_TRIG_INCR_WRITE_REV_MSB _u(7) -#define DMA_CH5_CTRL_TRIG_INCR_WRITE_REV_LSB _u(7) -#define DMA_CH5_CTRL_TRIG_INCR_WRITE_REV_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH5_CTRL_TRIG_INCR_WRITE -// Description : If 1, the write address increments with each transfer. If 0, -// each write is directed to the same, initial address. -// -// Generally this should be disabled for memory-to-peripheral -// transfers. -#define DMA_CH5_CTRL_TRIG_INCR_WRITE_RESET _u(0x0) -#define DMA_CH5_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000040) -#define DMA_CH5_CTRL_TRIG_INCR_WRITE_MSB _u(6) -#define DMA_CH5_CTRL_TRIG_INCR_WRITE_LSB _u(6) -#define DMA_CH5_CTRL_TRIG_INCR_WRITE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH5_CTRL_TRIG_INCR_READ_REV -// Description : If 1, and INCR_READ is 1, the read address is decremented -// rather than incremented with each transfer. -// -// If 1, and INCR_READ is 0, this otherwise-unused combination -// causes the read address to be incremented by twice the transfer -// size, i.e. skipping over alternate addresses. -#define DMA_CH5_CTRL_TRIG_INCR_READ_REV_RESET _u(0x0) -#define DMA_CH5_CTRL_TRIG_INCR_READ_REV_BITS _u(0x00000020) -#define DMA_CH5_CTRL_TRIG_INCR_READ_REV_MSB _u(5) -#define DMA_CH5_CTRL_TRIG_INCR_READ_REV_LSB _u(5) -#define DMA_CH5_CTRL_TRIG_INCR_READ_REV_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH5_CTRL_TRIG_INCR_READ -// Description : If 1, the read address increments with each transfer. If 0, -// each read is directed to the same, initial address. -// -// Generally this should be disabled for peripheral-to-memory -// transfers. -#define DMA_CH5_CTRL_TRIG_INCR_READ_RESET _u(0x0) -#define DMA_CH5_CTRL_TRIG_INCR_READ_BITS _u(0x00000010) -#define DMA_CH5_CTRL_TRIG_INCR_READ_MSB _u(4) -#define DMA_CH5_CTRL_TRIG_INCR_READ_LSB _u(4) -#define DMA_CH5_CTRL_TRIG_INCR_READ_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH5_CTRL_TRIG_DATA_SIZE -// Description : Set the size of each bus transfer (byte/halfword/word). -// READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) -// with each transfer. -// 0x0 -> SIZE_BYTE -// 0x1 -> SIZE_HALFWORD -// 0x2 -> SIZE_WORD -#define DMA_CH5_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) -#define DMA_CH5_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) -#define DMA_CH5_CTRL_TRIG_DATA_SIZE_MSB _u(3) -#define DMA_CH5_CTRL_TRIG_DATA_SIZE_LSB _u(2) -#define DMA_CH5_CTRL_TRIG_DATA_SIZE_ACCESS "RW" -#define DMA_CH5_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) -#define DMA_CH5_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1) -#define DMA_CH5_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) -// ----------------------------------------------------------------------------- -// Field : DMA_CH5_CTRL_TRIG_HIGH_PRIORITY -// Description : HIGH_PRIORITY gives a channel preferential treatment in issue -// scheduling: in each scheduling round, all high priority -// channels are considered first, and then only a single low -// priority channel, before returning to the high priority -// channels. -// -// This only affects the order in which the DMA schedules -// channels. The DMA's bus priority is not changed. If the DMA is -// not saturated then a low priority channel will see no loss of -// throughput. -#define DMA_CH5_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0) -#define DMA_CH5_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002) -#define DMA_CH5_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1) -#define DMA_CH5_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1) -#define DMA_CH5_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH5_CTRL_TRIG_EN -// Description : DMA Channel Enable. -// When 1, the channel will respond to triggering events, which -// will cause it to become BUSY and start transferring data. When -// 0, the channel will ignore triggers, stop issuing transfers, -// and pause the current transfer sequence (i.e. BUSY will remain -// high if already high) -#define DMA_CH5_CTRL_TRIG_EN_RESET _u(0x0) -#define DMA_CH5_CTRL_TRIG_EN_BITS _u(0x00000001) -#define DMA_CH5_CTRL_TRIG_EN_MSB _u(0) -#define DMA_CH5_CTRL_TRIG_EN_LSB _u(0) -#define DMA_CH5_CTRL_TRIG_EN_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH5_AL1_CTRL -// Description : Alias for channel 5 CTRL register -#define DMA_CH5_AL1_CTRL_OFFSET _u(0x00000150) -#define DMA_CH5_AL1_CTRL_BITS _u(0xffffffff) -#define DMA_CH5_AL1_CTRL_RESET "-" -#define DMA_CH5_AL1_CTRL_MSB _u(31) -#define DMA_CH5_AL1_CTRL_LSB _u(0) -#define DMA_CH5_AL1_CTRL_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH5_AL1_READ_ADDR -// Description : Alias for channel 5 READ_ADDR register -#define DMA_CH5_AL1_READ_ADDR_OFFSET _u(0x00000154) -#define DMA_CH5_AL1_READ_ADDR_BITS _u(0xffffffff) -#define DMA_CH5_AL1_READ_ADDR_RESET "-" -#define DMA_CH5_AL1_READ_ADDR_MSB _u(31) -#define DMA_CH5_AL1_READ_ADDR_LSB _u(0) -#define DMA_CH5_AL1_READ_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH5_AL1_WRITE_ADDR -// Description : Alias for channel 5 WRITE_ADDR register -#define DMA_CH5_AL1_WRITE_ADDR_OFFSET _u(0x00000158) -#define DMA_CH5_AL1_WRITE_ADDR_BITS _u(0xffffffff) -#define DMA_CH5_AL1_WRITE_ADDR_RESET "-" -#define DMA_CH5_AL1_WRITE_ADDR_MSB _u(31) -#define DMA_CH5_AL1_WRITE_ADDR_LSB _u(0) -#define DMA_CH5_AL1_WRITE_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH5_AL1_TRANS_COUNT_TRIG -// Description : Alias for channel 5 TRANS_COUNT register -// This is a trigger register (0xc). Writing a nonzero value will -// reload the channel counter and start the channel. -#define DMA_CH5_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x0000015c) -#define DMA_CH5_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff) -#define DMA_CH5_AL1_TRANS_COUNT_TRIG_RESET "-" -#define DMA_CH5_AL1_TRANS_COUNT_TRIG_MSB _u(31) -#define DMA_CH5_AL1_TRANS_COUNT_TRIG_LSB _u(0) -#define DMA_CH5_AL1_TRANS_COUNT_TRIG_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH5_AL2_CTRL -// Description : Alias for channel 5 CTRL register -#define DMA_CH5_AL2_CTRL_OFFSET _u(0x00000160) -#define DMA_CH5_AL2_CTRL_BITS _u(0xffffffff) -#define DMA_CH5_AL2_CTRL_RESET "-" -#define DMA_CH5_AL2_CTRL_MSB _u(31) -#define DMA_CH5_AL2_CTRL_LSB _u(0) -#define DMA_CH5_AL2_CTRL_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH5_AL2_TRANS_COUNT -// Description : Alias for channel 5 TRANS_COUNT register -#define DMA_CH5_AL2_TRANS_COUNT_OFFSET _u(0x00000164) -#define DMA_CH5_AL2_TRANS_COUNT_BITS _u(0xffffffff) -#define DMA_CH5_AL2_TRANS_COUNT_RESET "-" -#define DMA_CH5_AL2_TRANS_COUNT_MSB _u(31) -#define DMA_CH5_AL2_TRANS_COUNT_LSB _u(0) -#define DMA_CH5_AL2_TRANS_COUNT_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH5_AL2_READ_ADDR -// Description : Alias for channel 5 READ_ADDR register -#define DMA_CH5_AL2_READ_ADDR_OFFSET _u(0x00000168) -#define DMA_CH5_AL2_READ_ADDR_BITS _u(0xffffffff) -#define DMA_CH5_AL2_READ_ADDR_RESET "-" -#define DMA_CH5_AL2_READ_ADDR_MSB _u(31) -#define DMA_CH5_AL2_READ_ADDR_LSB _u(0) -#define DMA_CH5_AL2_READ_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH5_AL2_WRITE_ADDR_TRIG -// Description : Alias for channel 5 WRITE_ADDR register -// This is a trigger register (0xc). Writing a nonzero value will -// reload the channel counter and start the channel. -#define DMA_CH5_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x0000016c) -#define DMA_CH5_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff) -#define DMA_CH5_AL2_WRITE_ADDR_TRIG_RESET "-" -#define DMA_CH5_AL2_WRITE_ADDR_TRIG_MSB _u(31) -#define DMA_CH5_AL2_WRITE_ADDR_TRIG_LSB _u(0) -#define DMA_CH5_AL2_WRITE_ADDR_TRIG_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH5_AL3_CTRL -// Description : Alias for channel 5 CTRL register -#define DMA_CH5_AL3_CTRL_OFFSET _u(0x00000170) -#define DMA_CH5_AL3_CTRL_BITS _u(0xffffffff) -#define DMA_CH5_AL3_CTRL_RESET "-" -#define DMA_CH5_AL3_CTRL_MSB _u(31) -#define DMA_CH5_AL3_CTRL_LSB _u(0) -#define DMA_CH5_AL3_CTRL_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH5_AL3_WRITE_ADDR -// Description : Alias for channel 5 WRITE_ADDR register -#define DMA_CH5_AL3_WRITE_ADDR_OFFSET _u(0x00000174) -#define DMA_CH5_AL3_WRITE_ADDR_BITS _u(0xffffffff) -#define DMA_CH5_AL3_WRITE_ADDR_RESET "-" -#define DMA_CH5_AL3_WRITE_ADDR_MSB _u(31) -#define DMA_CH5_AL3_WRITE_ADDR_LSB _u(0) -#define DMA_CH5_AL3_WRITE_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH5_AL3_TRANS_COUNT -// Description : Alias for channel 5 TRANS_COUNT register -#define DMA_CH5_AL3_TRANS_COUNT_OFFSET _u(0x00000178) -#define DMA_CH5_AL3_TRANS_COUNT_BITS _u(0xffffffff) -#define DMA_CH5_AL3_TRANS_COUNT_RESET "-" -#define DMA_CH5_AL3_TRANS_COUNT_MSB _u(31) -#define DMA_CH5_AL3_TRANS_COUNT_LSB _u(0) -#define DMA_CH5_AL3_TRANS_COUNT_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH5_AL3_READ_ADDR_TRIG -// Description : Alias for channel 5 READ_ADDR register -// This is a trigger register (0xc). Writing a nonzero value will -// reload the channel counter and start the channel. -#define DMA_CH5_AL3_READ_ADDR_TRIG_OFFSET _u(0x0000017c) -#define DMA_CH5_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff) -#define DMA_CH5_AL3_READ_ADDR_TRIG_RESET "-" -#define DMA_CH5_AL3_READ_ADDR_TRIG_MSB _u(31) -#define DMA_CH5_AL3_READ_ADDR_TRIG_LSB _u(0) -#define DMA_CH5_AL3_READ_ADDR_TRIG_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH6_READ_ADDR -// Description : DMA Channel 6 Read Address pointer -// This register updates automatically each time a read completes. -// The current value is the next address to be read by this -// channel. -#define DMA_CH6_READ_ADDR_OFFSET _u(0x00000180) -#define DMA_CH6_READ_ADDR_BITS _u(0xffffffff) -#define DMA_CH6_READ_ADDR_RESET _u(0x00000000) -#define DMA_CH6_READ_ADDR_MSB _u(31) -#define DMA_CH6_READ_ADDR_LSB _u(0) -#define DMA_CH6_READ_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH6_WRITE_ADDR -// Description : DMA Channel 6 Write Address pointer -// This register updates automatically each time a write -// completes. The current value is the next address to be written -// by this channel. -#define DMA_CH6_WRITE_ADDR_OFFSET _u(0x00000184) -#define DMA_CH6_WRITE_ADDR_BITS _u(0xffffffff) -#define DMA_CH6_WRITE_ADDR_RESET _u(0x00000000) -#define DMA_CH6_WRITE_ADDR_MSB _u(31) -#define DMA_CH6_WRITE_ADDR_LSB _u(0) -#define DMA_CH6_WRITE_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH6_TRANS_COUNT -// Description : DMA Channel 6 Transfer Count -#define DMA_CH6_TRANS_COUNT_OFFSET _u(0x00000188) -#define DMA_CH6_TRANS_COUNT_BITS _u(0xffffffff) -#define DMA_CH6_TRANS_COUNT_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : DMA_CH6_TRANS_COUNT_MODE -// Description : When MODE is 0x0, the transfer count decrements with each -// transfer until 0, and then the channel triggers the next -// channel indicated by CTRL_CHAIN_TO. -// -// When MODE is 0x1, the transfer count decrements with each -// transfer until 0, and then the channel re-triggers itself, in -// addition to the trigger indicated by CTRL_CHAIN_TO. This is -// useful for e.g. an endless ring-buffer DMA with periodic -// interrupts. -// -// When MODE is 0xf, the transfer count does not decrement. The -// DMA channel performs an endless sequence of transfers, never -// triggering other channels or raising interrupts, until an ABORT -// is raised. -// -// All other values are reserved. -// 0x0 -> NORMAL -// 0x1 -> TRIGGER_SELF -// 0xf -> ENDLESS -#define DMA_CH6_TRANS_COUNT_MODE_RESET _u(0x0) -#define DMA_CH6_TRANS_COUNT_MODE_BITS _u(0xf0000000) -#define DMA_CH6_TRANS_COUNT_MODE_MSB _u(31) -#define DMA_CH6_TRANS_COUNT_MODE_LSB _u(28) -#define DMA_CH6_TRANS_COUNT_MODE_ACCESS "RW" -#define DMA_CH6_TRANS_COUNT_MODE_VALUE_NORMAL _u(0x0) -#define DMA_CH6_TRANS_COUNT_MODE_VALUE_TRIGGER_SELF _u(0x1) -#define DMA_CH6_TRANS_COUNT_MODE_VALUE_ENDLESS _u(0xf) -// ----------------------------------------------------------------------------- -// Field : DMA_CH6_TRANS_COUNT_COUNT -// Description : 28-bit transfer count (256 million transfers maximum). -// -// Program the number of bus transfers a channel will perform -// before halting. Note that, if transfers are larger than one -// byte in size, this is not equal to the number of bytes -// transferred (see CTRL_DATA_SIZE). -// -// When the channel is active, reading this register shows the -// number of transfers remaining, updating automatically each time -// a write transfer completes. -// -// Writing this register sets the RELOAD value for the transfer -// counter. Each time this channel is triggered, the RELOAD value -// is copied into the live transfer counter. The channel can be -// started multiple times, and will perform the same number of -// transfers each time, as programmed by most recent write. -// -// The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT -// is used as a trigger, the written value is used immediately as -// the length of the new transfer sequence, as well as being -// written to RELOAD. -#define DMA_CH6_TRANS_COUNT_COUNT_RESET _u(0x0000000) -#define DMA_CH6_TRANS_COUNT_COUNT_BITS _u(0x0fffffff) -#define DMA_CH6_TRANS_COUNT_COUNT_MSB _u(27) -#define DMA_CH6_TRANS_COUNT_COUNT_LSB _u(0) -#define DMA_CH6_TRANS_COUNT_COUNT_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH6_CTRL_TRIG -// Description : DMA Channel 6 Control and Status -#define DMA_CH6_CTRL_TRIG_OFFSET _u(0x0000018c) -#define DMA_CH6_CTRL_TRIG_BITS _u(0xe7ffffff) -#define DMA_CH6_CTRL_TRIG_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : DMA_CH6_CTRL_TRIG_AHB_ERROR -// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel -// halts when it encounters any bus error, and always raises its -// channel IRQ flag. -#define DMA_CH6_CTRL_TRIG_AHB_ERROR_RESET _u(0x0) -#define DMA_CH6_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000) -#define DMA_CH6_CTRL_TRIG_AHB_ERROR_MSB _u(31) -#define DMA_CH6_CTRL_TRIG_AHB_ERROR_LSB _u(31) -#define DMA_CH6_CTRL_TRIG_AHB_ERROR_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : DMA_CH6_CTRL_TRIG_READ_ERROR -// Description : If 1, the channel received a read bus error. Write one to -// clear. -// READ_ADDR shows the approximate address where the bus error was -// encountered (will not be earlier, or more than 3 transfers -// later) -#define DMA_CH6_CTRL_TRIG_READ_ERROR_RESET _u(0x0) -#define DMA_CH6_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000) -#define DMA_CH6_CTRL_TRIG_READ_ERROR_MSB _u(30) -#define DMA_CH6_CTRL_TRIG_READ_ERROR_LSB _u(30) -#define DMA_CH6_CTRL_TRIG_READ_ERROR_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : DMA_CH6_CTRL_TRIG_WRITE_ERROR -// Description : If 1, the channel received a write bus error. Write one to -// clear. -// WRITE_ADDR shows the approximate address where the bus error -// was encountered (will not be earlier, or more than 5 transfers -// later) -#define DMA_CH6_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0) -#define DMA_CH6_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000) -#define DMA_CH6_CTRL_TRIG_WRITE_ERROR_MSB _u(29) -#define DMA_CH6_CTRL_TRIG_WRITE_ERROR_LSB _u(29) -#define DMA_CH6_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : DMA_CH6_CTRL_TRIG_BUSY -// Description : This flag goes high when the channel starts a new transfer -// sequence, and low when the last transfer of that sequence -// completes. Clearing EN while BUSY is high pauses the channel, -// and BUSY will stay high while paused. -// -// To terminate a sequence early (and clear the BUSY flag), see -// CHAN_ABORT. -#define DMA_CH6_CTRL_TRIG_BUSY_RESET _u(0x0) -#define DMA_CH6_CTRL_TRIG_BUSY_BITS _u(0x04000000) -#define DMA_CH6_CTRL_TRIG_BUSY_MSB _u(26) -#define DMA_CH6_CTRL_TRIG_BUSY_LSB _u(26) -#define DMA_CH6_CTRL_TRIG_BUSY_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : DMA_CH6_CTRL_TRIG_SNIFF_EN -// Description : If 1, this channel's data transfers are visible to the sniff -// hardware, and each transfer will advance the state of the -// checksum. This only applies if the sniff hardware is enabled, -// and has this channel selected. -// -// This allows checksum to be enabled or disabled on a per- -// control- block basis. -#define DMA_CH6_CTRL_TRIG_SNIFF_EN_RESET _u(0x0) -#define DMA_CH6_CTRL_TRIG_SNIFF_EN_BITS _u(0x02000000) -#define DMA_CH6_CTRL_TRIG_SNIFF_EN_MSB _u(25) -#define DMA_CH6_CTRL_TRIG_SNIFF_EN_LSB _u(25) -#define DMA_CH6_CTRL_TRIG_SNIFF_EN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH6_CTRL_TRIG_BSWAP -// Description : Apply byte-swap transformation to DMA data. -// For byte data, this has no effect. For halfword data, the two -// bytes of each halfword are swapped. For word data, the four -// bytes of each word are swapped to reverse order. -#define DMA_CH6_CTRL_TRIG_BSWAP_RESET _u(0x0) -#define DMA_CH6_CTRL_TRIG_BSWAP_BITS _u(0x01000000) -#define DMA_CH6_CTRL_TRIG_BSWAP_MSB _u(24) -#define DMA_CH6_CTRL_TRIG_BSWAP_LSB _u(24) -#define DMA_CH6_CTRL_TRIG_BSWAP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH6_CTRL_TRIG_IRQ_QUIET -// Description : In QUIET mode, the channel does not generate IRQs at the end of -// every transfer block. Instead, an IRQ is raised when NULL is -// written to a trigger register, indicating the end of a control -// block chain. -// -// This reduces the number of interrupts to be serviced by the CPU -// when transferring a DMA chain of many small control blocks. -#define DMA_CH6_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0) -#define DMA_CH6_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00800000) -#define DMA_CH6_CTRL_TRIG_IRQ_QUIET_MSB _u(23) -#define DMA_CH6_CTRL_TRIG_IRQ_QUIET_LSB _u(23) -#define DMA_CH6_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH6_CTRL_TRIG_TREQ_SEL -// Description : Select a Transfer Request signal. -// The channel uses the transfer request signal to pace its data -// transfer rate. Sources for TREQ signals are internal (TIMERS) -// or external (DREQ, a Data Request from the system). -// 0x0 to 0x3a -> select DREQ n as TREQ -// 0x3b -> Select Timer 0 as TREQ -// 0x3c -> Select Timer 1 as TREQ -// 0x3d -> Select Timer 2 as TREQ (Optional) -// 0x3e -> Select Timer 3 as TREQ (Optional) -// 0x3f -> Permanent request, for unpaced transfers. -#define DMA_CH6_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) -#define DMA_CH6_CTRL_TRIG_TREQ_SEL_BITS _u(0x007e0000) -#define DMA_CH6_CTRL_TRIG_TREQ_SEL_MSB _u(22) -#define DMA_CH6_CTRL_TRIG_TREQ_SEL_LSB _u(17) -#define DMA_CH6_CTRL_TRIG_TREQ_SEL_ACCESS "RW" -#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) -#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) -#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) -#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) -#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) -// ----------------------------------------------------------------------------- -// Field : DMA_CH6_CTRL_TRIG_CHAIN_TO -// Description : When this channel completes, it will trigger the channel -// indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this -// channel)_. -// -// Note this field resets to 0, so channels 1 and above will chain -// to channel 0 by default. Set this field to avoid this -// behaviour. -#define DMA_CH6_CTRL_TRIG_CHAIN_TO_RESET _u(0x0) -#define DMA_CH6_CTRL_TRIG_CHAIN_TO_BITS _u(0x0001e000) -#define DMA_CH6_CTRL_TRIG_CHAIN_TO_MSB _u(16) -#define DMA_CH6_CTRL_TRIG_CHAIN_TO_LSB _u(13) -#define DMA_CH6_CTRL_TRIG_CHAIN_TO_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH6_CTRL_TRIG_RING_SEL -// Description : Select whether RING_SIZE applies to read or write addresses. -// If 0, read addresses are wrapped on a (1 << RING_SIZE) -// boundary. If 1, write addresses are wrapped. -#define DMA_CH6_CTRL_TRIG_RING_SEL_RESET _u(0x0) -#define DMA_CH6_CTRL_TRIG_RING_SEL_BITS _u(0x00001000) -#define DMA_CH6_CTRL_TRIG_RING_SEL_MSB _u(12) -#define DMA_CH6_CTRL_TRIG_RING_SEL_LSB _u(12) -#define DMA_CH6_CTRL_TRIG_RING_SEL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH6_CTRL_TRIG_RING_SIZE -// Description : Size of address wrap region. If 0, don't wrap. For values n > -// 0, only the lower n bits of the address will change. This wraps -// the address on a (1 << n) byte boundary, facilitating access to -// naturally-aligned ring buffers. -// -// Ring sizes between 2 and 32768 bytes are possible. This can -// apply to either read or write addresses, based on value of -// RING_SEL. -// 0x0 -> RING_NONE -#define DMA_CH6_CTRL_TRIG_RING_SIZE_RESET _u(0x0) -#define DMA_CH6_CTRL_TRIG_RING_SIZE_BITS _u(0x00000f00) -#define DMA_CH6_CTRL_TRIG_RING_SIZE_MSB _u(11) -#define DMA_CH6_CTRL_TRIG_RING_SIZE_LSB _u(8) -#define DMA_CH6_CTRL_TRIG_RING_SIZE_ACCESS "RW" -#define DMA_CH6_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0) -// ----------------------------------------------------------------------------- -// Field : DMA_CH6_CTRL_TRIG_INCR_WRITE_REV -// Description : If 1, and INCR_WRITE is 1, the write address is decremented -// rather than incremented with each transfer. -// -// If 1, and INCR_WRITE is 0, this otherwise-unused combination -// causes the write address to be incremented by twice the -// transfer size, i.e. skipping over alternate addresses. -#define DMA_CH6_CTRL_TRIG_INCR_WRITE_REV_RESET _u(0x0) -#define DMA_CH6_CTRL_TRIG_INCR_WRITE_REV_BITS _u(0x00000080) -#define DMA_CH6_CTRL_TRIG_INCR_WRITE_REV_MSB _u(7) -#define DMA_CH6_CTRL_TRIG_INCR_WRITE_REV_LSB _u(7) -#define DMA_CH6_CTRL_TRIG_INCR_WRITE_REV_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH6_CTRL_TRIG_INCR_WRITE -// Description : If 1, the write address increments with each transfer. If 0, -// each write is directed to the same, initial address. -// -// Generally this should be disabled for memory-to-peripheral -// transfers. -#define DMA_CH6_CTRL_TRIG_INCR_WRITE_RESET _u(0x0) -#define DMA_CH6_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000040) -#define DMA_CH6_CTRL_TRIG_INCR_WRITE_MSB _u(6) -#define DMA_CH6_CTRL_TRIG_INCR_WRITE_LSB _u(6) -#define DMA_CH6_CTRL_TRIG_INCR_WRITE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH6_CTRL_TRIG_INCR_READ_REV -// Description : If 1, and INCR_READ is 1, the read address is decremented -// rather than incremented with each transfer. -// -// If 1, and INCR_READ is 0, this otherwise-unused combination -// causes the read address to be incremented by twice the transfer -// size, i.e. skipping over alternate addresses. -#define DMA_CH6_CTRL_TRIG_INCR_READ_REV_RESET _u(0x0) -#define DMA_CH6_CTRL_TRIG_INCR_READ_REV_BITS _u(0x00000020) -#define DMA_CH6_CTRL_TRIG_INCR_READ_REV_MSB _u(5) -#define DMA_CH6_CTRL_TRIG_INCR_READ_REV_LSB _u(5) -#define DMA_CH6_CTRL_TRIG_INCR_READ_REV_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH6_CTRL_TRIG_INCR_READ -// Description : If 1, the read address increments with each transfer. If 0, -// each read is directed to the same, initial address. -// -// Generally this should be disabled for peripheral-to-memory -// transfers. -#define DMA_CH6_CTRL_TRIG_INCR_READ_RESET _u(0x0) -#define DMA_CH6_CTRL_TRIG_INCR_READ_BITS _u(0x00000010) -#define DMA_CH6_CTRL_TRIG_INCR_READ_MSB _u(4) -#define DMA_CH6_CTRL_TRIG_INCR_READ_LSB _u(4) -#define DMA_CH6_CTRL_TRIG_INCR_READ_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH6_CTRL_TRIG_DATA_SIZE -// Description : Set the size of each bus transfer (byte/halfword/word). -// READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) -// with each transfer. -// 0x0 -> SIZE_BYTE -// 0x1 -> SIZE_HALFWORD -// 0x2 -> SIZE_WORD -#define DMA_CH6_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) -#define DMA_CH6_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) -#define DMA_CH6_CTRL_TRIG_DATA_SIZE_MSB _u(3) -#define DMA_CH6_CTRL_TRIG_DATA_SIZE_LSB _u(2) -#define DMA_CH6_CTRL_TRIG_DATA_SIZE_ACCESS "RW" -#define DMA_CH6_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) -#define DMA_CH6_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1) -#define DMA_CH6_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) -// ----------------------------------------------------------------------------- -// Field : DMA_CH6_CTRL_TRIG_HIGH_PRIORITY -// Description : HIGH_PRIORITY gives a channel preferential treatment in issue -// scheduling: in each scheduling round, all high priority -// channels are considered first, and then only a single low -// priority channel, before returning to the high priority -// channels. -// -// This only affects the order in which the DMA schedules -// channels. The DMA's bus priority is not changed. If the DMA is -// not saturated then a low priority channel will see no loss of -// throughput. -#define DMA_CH6_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0) -#define DMA_CH6_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002) -#define DMA_CH6_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1) -#define DMA_CH6_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1) -#define DMA_CH6_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH6_CTRL_TRIG_EN -// Description : DMA Channel Enable. -// When 1, the channel will respond to triggering events, which -// will cause it to become BUSY and start transferring data. When -// 0, the channel will ignore triggers, stop issuing transfers, -// and pause the current transfer sequence (i.e. BUSY will remain -// high if already high) -#define DMA_CH6_CTRL_TRIG_EN_RESET _u(0x0) -#define DMA_CH6_CTRL_TRIG_EN_BITS _u(0x00000001) -#define DMA_CH6_CTRL_TRIG_EN_MSB _u(0) -#define DMA_CH6_CTRL_TRIG_EN_LSB _u(0) -#define DMA_CH6_CTRL_TRIG_EN_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH6_AL1_CTRL -// Description : Alias for channel 6 CTRL register -#define DMA_CH6_AL1_CTRL_OFFSET _u(0x00000190) -#define DMA_CH6_AL1_CTRL_BITS _u(0xffffffff) -#define DMA_CH6_AL1_CTRL_RESET "-" -#define DMA_CH6_AL1_CTRL_MSB _u(31) -#define DMA_CH6_AL1_CTRL_LSB _u(0) -#define DMA_CH6_AL1_CTRL_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH6_AL1_READ_ADDR -// Description : Alias for channel 6 READ_ADDR register -#define DMA_CH6_AL1_READ_ADDR_OFFSET _u(0x00000194) -#define DMA_CH6_AL1_READ_ADDR_BITS _u(0xffffffff) -#define DMA_CH6_AL1_READ_ADDR_RESET "-" -#define DMA_CH6_AL1_READ_ADDR_MSB _u(31) -#define DMA_CH6_AL1_READ_ADDR_LSB _u(0) -#define DMA_CH6_AL1_READ_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH6_AL1_WRITE_ADDR -// Description : Alias for channel 6 WRITE_ADDR register -#define DMA_CH6_AL1_WRITE_ADDR_OFFSET _u(0x00000198) -#define DMA_CH6_AL1_WRITE_ADDR_BITS _u(0xffffffff) -#define DMA_CH6_AL1_WRITE_ADDR_RESET "-" -#define DMA_CH6_AL1_WRITE_ADDR_MSB _u(31) -#define DMA_CH6_AL1_WRITE_ADDR_LSB _u(0) -#define DMA_CH6_AL1_WRITE_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH6_AL1_TRANS_COUNT_TRIG -// Description : Alias for channel 6 TRANS_COUNT register -// This is a trigger register (0xc). Writing a nonzero value will -// reload the channel counter and start the channel. -#define DMA_CH6_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x0000019c) -#define DMA_CH6_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff) -#define DMA_CH6_AL1_TRANS_COUNT_TRIG_RESET "-" -#define DMA_CH6_AL1_TRANS_COUNT_TRIG_MSB _u(31) -#define DMA_CH6_AL1_TRANS_COUNT_TRIG_LSB _u(0) -#define DMA_CH6_AL1_TRANS_COUNT_TRIG_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH6_AL2_CTRL -// Description : Alias for channel 6 CTRL register -#define DMA_CH6_AL2_CTRL_OFFSET _u(0x000001a0) -#define DMA_CH6_AL2_CTRL_BITS _u(0xffffffff) -#define DMA_CH6_AL2_CTRL_RESET "-" -#define DMA_CH6_AL2_CTRL_MSB _u(31) -#define DMA_CH6_AL2_CTRL_LSB _u(0) -#define DMA_CH6_AL2_CTRL_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH6_AL2_TRANS_COUNT -// Description : Alias for channel 6 TRANS_COUNT register -#define DMA_CH6_AL2_TRANS_COUNT_OFFSET _u(0x000001a4) -#define DMA_CH6_AL2_TRANS_COUNT_BITS _u(0xffffffff) -#define DMA_CH6_AL2_TRANS_COUNT_RESET "-" -#define DMA_CH6_AL2_TRANS_COUNT_MSB _u(31) -#define DMA_CH6_AL2_TRANS_COUNT_LSB _u(0) -#define DMA_CH6_AL2_TRANS_COUNT_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH6_AL2_READ_ADDR -// Description : Alias for channel 6 READ_ADDR register -#define DMA_CH6_AL2_READ_ADDR_OFFSET _u(0x000001a8) -#define DMA_CH6_AL2_READ_ADDR_BITS _u(0xffffffff) -#define DMA_CH6_AL2_READ_ADDR_RESET "-" -#define DMA_CH6_AL2_READ_ADDR_MSB _u(31) -#define DMA_CH6_AL2_READ_ADDR_LSB _u(0) -#define DMA_CH6_AL2_READ_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH6_AL2_WRITE_ADDR_TRIG -// Description : Alias for channel 6 WRITE_ADDR register -// This is a trigger register (0xc). Writing a nonzero value will -// reload the channel counter and start the channel. -#define DMA_CH6_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x000001ac) -#define DMA_CH6_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff) -#define DMA_CH6_AL2_WRITE_ADDR_TRIG_RESET "-" -#define DMA_CH6_AL2_WRITE_ADDR_TRIG_MSB _u(31) -#define DMA_CH6_AL2_WRITE_ADDR_TRIG_LSB _u(0) -#define DMA_CH6_AL2_WRITE_ADDR_TRIG_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH6_AL3_CTRL -// Description : Alias for channel 6 CTRL register -#define DMA_CH6_AL3_CTRL_OFFSET _u(0x000001b0) -#define DMA_CH6_AL3_CTRL_BITS _u(0xffffffff) -#define DMA_CH6_AL3_CTRL_RESET "-" -#define DMA_CH6_AL3_CTRL_MSB _u(31) -#define DMA_CH6_AL3_CTRL_LSB _u(0) -#define DMA_CH6_AL3_CTRL_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH6_AL3_WRITE_ADDR -// Description : Alias for channel 6 WRITE_ADDR register -#define DMA_CH6_AL3_WRITE_ADDR_OFFSET _u(0x000001b4) -#define DMA_CH6_AL3_WRITE_ADDR_BITS _u(0xffffffff) -#define DMA_CH6_AL3_WRITE_ADDR_RESET "-" -#define DMA_CH6_AL3_WRITE_ADDR_MSB _u(31) -#define DMA_CH6_AL3_WRITE_ADDR_LSB _u(0) -#define DMA_CH6_AL3_WRITE_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH6_AL3_TRANS_COUNT -// Description : Alias for channel 6 TRANS_COUNT register -#define DMA_CH6_AL3_TRANS_COUNT_OFFSET _u(0x000001b8) -#define DMA_CH6_AL3_TRANS_COUNT_BITS _u(0xffffffff) -#define DMA_CH6_AL3_TRANS_COUNT_RESET "-" -#define DMA_CH6_AL3_TRANS_COUNT_MSB _u(31) -#define DMA_CH6_AL3_TRANS_COUNT_LSB _u(0) -#define DMA_CH6_AL3_TRANS_COUNT_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH6_AL3_READ_ADDR_TRIG -// Description : Alias for channel 6 READ_ADDR register -// This is a trigger register (0xc). Writing a nonzero value will -// reload the channel counter and start the channel. -#define DMA_CH6_AL3_READ_ADDR_TRIG_OFFSET _u(0x000001bc) -#define DMA_CH6_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff) -#define DMA_CH6_AL3_READ_ADDR_TRIG_RESET "-" -#define DMA_CH6_AL3_READ_ADDR_TRIG_MSB _u(31) -#define DMA_CH6_AL3_READ_ADDR_TRIG_LSB _u(0) -#define DMA_CH6_AL3_READ_ADDR_TRIG_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH7_READ_ADDR -// Description : DMA Channel 7 Read Address pointer -// This register updates automatically each time a read completes. -// The current value is the next address to be read by this -// channel. -#define DMA_CH7_READ_ADDR_OFFSET _u(0x000001c0) -#define DMA_CH7_READ_ADDR_BITS _u(0xffffffff) -#define DMA_CH7_READ_ADDR_RESET _u(0x00000000) -#define DMA_CH7_READ_ADDR_MSB _u(31) -#define DMA_CH7_READ_ADDR_LSB _u(0) -#define DMA_CH7_READ_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH7_WRITE_ADDR -// Description : DMA Channel 7 Write Address pointer -// This register updates automatically each time a write -// completes. The current value is the next address to be written -// by this channel. -#define DMA_CH7_WRITE_ADDR_OFFSET _u(0x000001c4) -#define DMA_CH7_WRITE_ADDR_BITS _u(0xffffffff) -#define DMA_CH7_WRITE_ADDR_RESET _u(0x00000000) -#define DMA_CH7_WRITE_ADDR_MSB _u(31) -#define DMA_CH7_WRITE_ADDR_LSB _u(0) -#define DMA_CH7_WRITE_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH7_TRANS_COUNT -// Description : DMA Channel 7 Transfer Count -#define DMA_CH7_TRANS_COUNT_OFFSET _u(0x000001c8) -#define DMA_CH7_TRANS_COUNT_BITS _u(0xffffffff) -#define DMA_CH7_TRANS_COUNT_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : DMA_CH7_TRANS_COUNT_MODE -// Description : When MODE is 0x0, the transfer count decrements with each -// transfer until 0, and then the channel triggers the next -// channel indicated by CTRL_CHAIN_TO. -// -// When MODE is 0x1, the transfer count decrements with each -// transfer until 0, and then the channel re-triggers itself, in -// addition to the trigger indicated by CTRL_CHAIN_TO. This is -// useful for e.g. an endless ring-buffer DMA with periodic -// interrupts. -// -// When MODE is 0xf, the transfer count does not decrement. The -// DMA channel performs an endless sequence of transfers, never -// triggering other channels or raising interrupts, until an ABORT -// is raised. -// -// All other values are reserved. -// 0x0 -> NORMAL -// 0x1 -> TRIGGER_SELF -// 0xf -> ENDLESS -#define DMA_CH7_TRANS_COUNT_MODE_RESET _u(0x0) -#define DMA_CH7_TRANS_COUNT_MODE_BITS _u(0xf0000000) -#define DMA_CH7_TRANS_COUNT_MODE_MSB _u(31) -#define DMA_CH7_TRANS_COUNT_MODE_LSB _u(28) -#define DMA_CH7_TRANS_COUNT_MODE_ACCESS "RW" -#define DMA_CH7_TRANS_COUNT_MODE_VALUE_NORMAL _u(0x0) -#define DMA_CH7_TRANS_COUNT_MODE_VALUE_TRIGGER_SELF _u(0x1) -#define DMA_CH7_TRANS_COUNT_MODE_VALUE_ENDLESS _u(0xf) -// ----------------------------------------------------------------------------- -// Field : DMA_CH7_TRANS_COUNT_COUNT -// Description : 28-bit transfer count (256 million transfers maximum). -// -// Program the number of bus transfers a channel will perform -// before halting. Note that, if transfers are larger than one -// byte in size, this is not equal to the number of bytes -// transferred (see CTRL_DATA_SIZE). -// -// When the channel is active, reading this register shows the -// number of transfers remaining, updating automatically each time -// a write transfer completes. -// -// Writing this register sets the RELOAD value for the transfer -// counter. Each time this channel is triggered, the RELOAD value -// is copied into the live transfer counter. The channel can be -// started multiple times, and will perform the same number of -// transfers each time, as programmed by most recent write. -// -// The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT -// is used as a trigger, the written value is used immediately as -// the length of the new transfer sequence, as well as being -// written to RELOAD. -#define DMA_CH7_TRANS_COUNT_COUNT_RESET _u(0x0000000) -#define DMA_CH7_TRANS_COUNT_COUNT_BITS _u(0x0fffffff) -#define DMA_CH7_TRANS_COUNT_COUNT_MSB _u(27) -#define DMA_CH7_TRANS_COUNT_COUNT_LSB _u(0) -#define DMA_CH7_TRANS_COUNT_COUNT_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH7_CTRL_TRIG -// Description : DMA Channel 7 Control and Status -#define DMA_CH7_CTRL_TRIG_OFFSET _u(0x000001cc) -#define DMA_CH7_CTRL_TRIG_BITS _u(0xe7ffffff) -#define DMA_CH7_CTRL_TRIG_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : DMA_CH7_CTRL_TRIG_AHB_ERROR -// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel -// halts when it encounters any bus error, and always raises its -// channel IRQ flag. -#define DMA_CH7_CTRL_TRIG_AHB_ERROR_RESET _u(0x0) -#define DMA_CH7_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000) -#define DMA_CH7_CTRL_TRIG_AHB_ERROR_MSB _u(31) -#define DMA_CH7_CTRL_TRIG_AHB_ERROR_LSB _u(31) -#define DMA_CH7_CTRL_TRIG_AHB_ERROR_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : DMA_CH7_CTRL_TRIG_READ_ERROR -// Description : If 1, the channel received a read bus error. Write one to -// clear. -// READ_ADDR shows the approximate address where the bus error was -// encountered (will not be earlier, or more than 3 transfers -// later) -#define DMA_CH7_CTRL_TRIG_READ_ERROR_RESET _u(0x0) -#define DMA_CH7_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000) -#define DMA_CH7_CTRL_TRIG_READ_ERROR_MSB _u(30) -#define DMA_CH7_CTRL_TRIG_READ_ERROR_LSB _u(30) -#define DMA_CH7_CTRL_TRIG_READ_ERROR_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : DMA_CH7_CTRL_TRIG_WRITE_ERROR -// Description : If 1, the channel received a write bus error. Write one to -// clear. -// WRITE_ADDR shows the approximate address where the bus error -// was encountered (will not be earlier, or more than 5 transfers -// later) -#define DMA_CH7_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0) -#define DMA_CH7_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000) -#define DMA_CH7_CTRL_TRIG_WRITE_ERROR_MSB _u(29) -#define DMA_CH7_CTRL_TRIG_WRITE_ERROR_LSB _u(29) -#define DMA_CH7_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : DMA_CH7_CTRL_TRIG_BUSY -// Description : This flag goes high when the channel starts a new transfer -// sequence, and low when the last transfer of that sequence -// completes. Clearing EN while BUSY is high pauses the channel, -// and BUSY will stay high while paused. -// -// To terminate a sequence early (and clear the BUSY flag), see -// CHAN_ABORT. -#define DMA_CH7_CTRL_TRIG_BUSY_RESET _u(0x0) -#define DMA_CH7_CTRL_TRIG_BUSY_BITS _u(0x04000000) -#define DMA_CH7_CTRL_TRIG_BUSY_MSB _u(26) -#define DMA_CH7_CTRL_TRIG_BUSY_LSB _u(26) -#define DMA_CH7_CTRL_TRIG_BUSY_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : DMA_CH7_CTRL_TRIG_SNIFF_EN -// Description : If 1, this channel's data transfers are visible to the sniff -// hardware, and each transfer will advance the state of the -// checksum. This only applies if the sniff hardware is enabled, -// and has this channel selected. -// -// This allows checksum to be enabled or disabled on a per- -// control- block basis. -#define DMA_CH7_CTRL_TRIG_SNIFF_EN_RESET _u(0x0) -#define DMA_CH7_CTRL_TRIG_SNIFF_EN_BITS _u(0x02000000) -#define DMA_CH7_CTRL_TRIG_SNIFF_EN_MSB _u(25) -#define DMA_CH7_CTRL_TRIG_SNIFF_EN_LSB _u(25) -#define DMA_CH7_CTRL_TRIG_SNIFF_EN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH7_CTRL_TRIG_BSWAP -// Description : Apply byte-swap transformation to DMA data. -// For byte data, this has no effect. For halfword data, the two -// bytes of each halfword are swapped. For word data, the four -// bytes of each word are swapped to reverse order. -#define DMA_CH7_CTRL_TRIG_BSWAP_RESET _u(0x0) -#define DMA_CH7_CTRL_TRIG_BSWAP_BITS _u(0x01000000) -#define DMA_CH7_CTRL_TRIG_BSWAP_MSB _u(24) -#define DMA_CH7_CTRL_TRIG_BSWAP_LSB _u(24) -#define DMA_CH7_CTRL_TRIG_BSWAP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH7_CTRL_TRIG_IRQ_QUIET -// Description : In QUIET mode, the channel does not generate IRQs at the end of -// every transfer block. Instead, an IRQ is raised when NULL is -// written to a trigger register, indicating the end of a control -// block chain. -// -// This reduces the number of interrupts to be serviced by the CPU -// when transferring a DMA chain of many small control blocks. -#define DMA_CH7_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0) -#define DMA_CH7_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00800000) -#define DMA_CH7_CTRL_TRIG_IRQ_QUIET_MSB _u(23) -#define DMA_CH7_CTRL_TRIG_IRQ_QUIET_LSB _u(23) -#define DMA_CH7_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH7_CTRL_TRIG_TREQ_SEL -// Description : Select a Transfer Request signal. -// The channel uses the transfer request signal to pace its data -// transfer rate. Sources for TREQ signals are internal (TIMERS) -// or external (DREQ, a Data Request from the system). -// 0x0 to 0x3a -> select DREQ n as TREQ -// 0x3b -> Select Timer 0 as TREQ -// 0x3c -> Select Timer 1 as TREQ -// 0x3d -> Select Timer 2 as TREQ (Optional) -// 0x3e -> Select Timer 3 as TREQ (Optional) -// 0x3f -> Permanent request, for unpaced transfers. -#define DMA_CH7_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) -#define DMA_CH7_CTRL_TRIG_TREQ_SEL_BITS _u(0x007e0000) -#define DMA_CH7_CTRL_TRIG_TREQ_SEL_MSB _u(22) -#define DMA_CH7_CTRL_TRIG_TREQ_SEL_LSB _u(17) -#define DMA_CH7_CTRL_TRIG_TREQ_SEL_ACCESS "RW" -#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) -#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) -#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) -#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) -#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) -// ----------------------------------------------------------------------------- -// Field : DMA_CH7_CTRL_TRIG_CHAIN_TO -// Description : When this channel completes, it will trigger the channel -// indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this -// channel)_. -// -// Note this field resets to 0, so channels 1 and above will chain -// to channel 0 by default. Set this field to avoid this -// behaviour. -#define DMA_CH7_CTRL_TRIG_CHAIN_TO_RESET _u(0x0) -#define DMA_CH7_CTRL_TRIG_CHAIN_TO_BITS _u(0x0001e000) -#define DMA_CH7_CTRL_TRIG_CHAIN_TO_MSB _u(16) -#define DMA_CH7_CTRL_TRIG_CHAIN_TO_LSB _u(13) -#define DMA_CH7_CTRL_TRIG_CHAIN_TO_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH7_CTRL_TRIG_RING_SEL -// Description : Select whether RING_SIZE applies to read or write addresses. -// If 0, read addresses are wrapped on a (1 << RING_SIZE) -// boundary. If 1, write addresses are wrapped. -#define DMA_CH7_CTRL_TRIG_RING_SEL_RESET _u(0x0) -#define DMA_CH7_CTRL_TRIG_RING_SEL_BITS _u(0x00001000) -#define DMA_CH7_CTRL_TRIG_RING_SEL_MSB _u(12) -#define DMA_CH7_CTRL_TRIG_RING_SEL_LSB _u(12) -#define DMA_CH7_CTRL_TRIG_RING_SEL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH7_CTRL_TRIG_RING_SIZE -// Description : Size of address wrap region. If 0, don't wrap. For values n > -// 0, only the lower n bits of the address will change. This wraps -// the address on a (1 << n) byte boundary, facilitating access to -// naturally-aligned ring buffers. -// -// Ring sizes between 2 and 32768 bytes are possible. This can -// apply to either read or write addresses, based on value of -// RING_SEL. -// 0x0 -> RING_NONE -#define DMA_CH7_CTRL_TRIG_RING_SIZE_RESET _u(0x0) -#define DMA_CH7_CTRL_TRIG_RING_SIZE_BITS _u(0x00000f00) -#define DMA_CH7_CTRL_TRIG_RING_SIZE_MSB _u(11) -#define DMA_CH7_CTRL_TRIG_RING_SIZE_LSB _u(8) -#define DMA_CH7_CTRL_TRIG_RING_SIZE_ACCESS "RW" -#define DMA_CH7_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0) -// ----------------------------------------------------------------------------- -// Field : DMA_CH7_CTRL_TRIG_INCR_WRITE_REV -// Description : If 1, and INCR_WRITE is 1, the write address is decremented -// rather than incremented with each transfer. -// -// If 1, and INCR_WRITE is 0, this otherwise-unused combination -// causes the write address to be incremented by twice the -// transfer size, i.e. skipping over alternate addresses. -#define DMA_CH7_CTRL_TRIG_INCR_WRITE_REV_RESET _u(0x0) -#define DMA_CH7_CTRL_TRIG_INCR_WRITE_REV_BITS _u(0x00000080) -#define DMA_CH7_CTRL_TRIG_INCR_WRITE_REV_MSB _u(7) -#define DMA_CH7_CTRL_TRIG_INCR_WRITE_REV_LSB _u(7) -#define DMA_CH7_CTRL_TRIG_INCR_WRITE_REV_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH7_CTRL_TRIG_INCR_WRITE -// Description : If 1, the write address increments with each transfer. If 0, -// each write is directed to the same, initial address. -// -// Generally this should be disabled for memory-to-peripheral -// transfers. -#define DMA_CH7_CTRL_TRIG_INCR_WRITE_RESET _u(0x0) -#define DMA_CH7_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000040) -#define DMA_CH7_CTRL_TRIG_INCR_WRITE_MSB _u(6) -#define DMA_CH7_CTRL_TRIG_INCR_WRITE_LSB _u(6) -#define DMA_CH7_CTRL_TRIG_INCR_WRITE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH7_CTRL_TRIG_INCR_READ_REV -// Description : If 1, and INCR_READ is 1, the read address is decremented -// rather than incremented with each transfer. -// -// If 1, and INCR_READ is 0, this otherwise-unused combination -// causes the read address to be incremented by twice the transfer -// size, i.e. skipping over alternate addresses. -#define DMA_CH7_CTRL_TRIG_INCR_READ_REV_RESET _u(0x0) -#define DMA_CH7_CTRL_TRIG_INCR_READ_REV_BITS _u(0x00000020) -#define DMA_CH7_CTRL_TRIG_INCR_READ_REV_MSB _u(5) -#define DMA_CH7_CTRL_TRIG_INCR_READ_REV_LSB _u(5) -#define DMA_CH7_CTRL_TRIG_INCR_READ_REV_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH7_CTRL_TRIG_INCR_READ -// Description : If 1, the read address increments with each transfer. If 0, -// each read is directed to the same, initial address. -// -// Generally this should be disabled for peripheral-to-memory -// transfers. -#define DMA_CH7_CTRL_TRIG_INCR_READ_RESET _u(0x0) -#define DMA_CH7_CTRL_TRIG_INCR_READ_BITS _u(0x00000010) -#define DMA_CH7_CTRL_TRIG_INCR_READ_MSB _u(4) -#define DMA_CH7_CTRL_TRIG_INCR_READ_LSB _u(4) -#define DMA_CH7_CTRL_TRIG_INCR_READ_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH7_CTRL_TRIG_DATA_SIZE -// Description : Set the size of each bus transfer (byte/halfword/word). -// READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) -// with each transfer. -// 0x0 -> SIZE_BYTE -// 0x1 -> SIZE_HALFWORD -// 0x2 -> SIZE_WORD -#define DMA_CH7_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) -#define DMA_CH7_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) -#define DMA_CH7_CTRL_TRIG_DATA_SIZE_MSB _u(3) -#define DMA_CH7_CTRL_TRIG_DATA_SIZE_LSB _u(2) -#define DMA_CH7_CTRL_TRIG_DATA_SIZE_ACCESS "RW" -#define DMA_CH7_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) -#define DMA_CH7_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1) -#define DMA_CH7_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) -// ----------------------------------------------------------------------------- -// Field : DMA_CH7_CTRL_TRIG_HIGH_PRIORITY -// Description : HIGH_PRIORITY gives a channel preferential treatment in issue -// scheduling: in each scheduling round, all high priority -// channels are considered first, and then only a single low -// priority channel, before returning to the high priority -// channels. -// -// This only affects the order in which the DMA schedules -// channels. The DMA's bus priority is not changed. If the DMA is -// not saturated then a low priority channel will see no loss of -// throughput. -#define DMA_CH7_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0) -#define DMA_CH7_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002) -#define DMA_CH7_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1) -#define DMA_CH7_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1) -#define DMA_CH7_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH7_CTRL_TRIG_EN -// Description : DMA Channel Enable. -// When 1, the channel will respond to triggering events, which -// will cause it to become BUSY and start transferring data. When -// 0, the channel will ignore triggers, stop issuing transfers, -// and pause the current transfer sequence (i.e. BUSY will remain -// high if already high) -#define DMA_CH7_CTRL_TRIG_EN_RESET _u(0x0) -#define DMA_CH7_CTRL_TRIG_EN_BITS _u(0x00000001) -#define DMA_CH7_CTRL_TRIG_EN_MSB _u(0) -#define DMA_CH7_CTRL_TRIG_EN_LSB _u(0) -#define DMA_CH7_CTRL_TRIG_EN_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH7_AL1_CTRL -// Description : Alias for channel 7 CTRL register -#define DMA_CH7_AL1_CTRL_OFFSET _u(0x000001d0) -#define DMA_CH7_AL1_CTRL_BITS _u(0xffffffff) -#define DMA_CH7_AL1_CTRL_RESET "-" -#define DMA_CH7_AL1_CTRL_MSB _u(31) -#define DMA_CH7_AL1_CTRL_LSB _u(0) -#define DMA_CH7_AL1_CTRL_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH7_AL1_READ_ADDR -// Description : Alias for channel 7 READ_ADDR register -#define DMA_CH7_AL1_READ_ADDR_OFFSET _u(0x000001d4) -#define DMA_CH7_AL1_READ_ADDR_BITS _u(0xffffffff) -#define DMA_CH7_AL1_READ_ADDR_RESET "-" -#define DMA_CH7_AL1_READ_ADDR_MSB _u(31) -#define DMA_CH7_AL1_READ_ADDR_LSB _u(0) -#define DMA_CH7_AL1_READ_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH7_AL1_WRITE_ADDR -// Description : Alias for channel 7 WRITE_ADDR register -#define DMA_CH7_AL1_WRITE_ADDR_OFFSET _u(0x000001d8) -#define DMA_CH7_AL1_WRITE_ADDR_BITS _u(0xffffffff) -#define DMA_CH7_AL1_WRITE_ADDR_RESET "-" -#define DMA_CH7_AL1_WRITE_ADDR_MSB _u(31) -#define DMA_CH7_AL1_WRITE_ADDR_LSB _u(0) -#define DMA_CH7_AL1_WRITE_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH7_AL1_TRANS_COUNT_TRIG -// Description : Alias for channel 7 TRANS_COUNT register -// This is a trigger register (0xc). Writing a nonzero value will -// reload the channel counter and start the channel. -#define DMA_CH7_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x000001dc) -#define DMA_CH7_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff) -#define DMA_CH7_AL1_TRANS_COUNT_TRIG_RESET "-" -#define DMA_CH7_AL1_TRANS_COUNT_TRIG_MSB _u(31) -#define DMA_CH7_AL1_TRANS_COUNT_TRIG_LSB _u(0) -#define DMA_CH7_AL1_TRANS_COUNT_TRIG_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH7_AL2_CTRL -// Description : Alias for channel 7 CTRL register -#define DMA_CH7_AL2_CTRL_OFFSET _u(0x000001e0) -#define DMA_CH7_AL2_CTRL_BITS _u(0xffffffff) -#define DMA_CH7_AL2_CTRL_RESET "-" -#define DMA_CH7_AL2_CTRL_MSB _u(31) -#define DMA_CH7_AL2_CTRL_LSB _u(0) -#define DMA_CH7_AL2_CTRL_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH7_AL2_TRANS_COUNT -// Description : Alias for channel 7 TRANS_COUNT register -#define DMA_CH7_AL2_TRANS_COUNT_OFFSET _u(0x000001e4) -#define DMA_CH7_AL2_TRANS_COUNT_BITS _u(0xffffffff) -#define DMA_CH7_AL2_TRANS_COUNT_RESET "-" -#define DMA_CH7_AL2_TRANS_COUNT_MSB _u(31) -#define DMA_CH7_AL2_TRANS_COUNT_LSB _u(0) -#define DMA_CH7_AL2_TRANS_COUNT_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH7_AL2_READ_ADDR -// Description : Alias for channel 7 READ_ADDR register -#define DMA_CH7_AL2_READ_ADDR_OFFSET _u(0x000001e8) -#define DMA_CH7_AL2_READ_ADDR_BITS _u(0xffffffff) -#define DMA_CH7_AL2_READ_ADDR_RESET "-" -#define DMA_CH7_AL2_READ_ADDR_MSB _u(31) -#define DMA_CH7_AL2_READ_ADDR_LSB _u(0) -#define DMA_CH7_AL2_READ_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH7_AL2_WRITE_ADDR_TRIG -// Description : Alias for channel 7 WRITE_ADDR register -// This is a trigger register (0xc). Writing a nonzero value will -// reload the channel counter and start the channel. -#define DMA_CH7_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x000001ec) -#define DMA_CH7_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff) -#define DMA_CH7_AL2_WRITE_ADDR_TRIG_RESET "-" -#define DMA_CH7_AL2_WRITE_ADDR_TRIG_MSB _u(31) -#define DMA_CH7_AL2_WRITE_ADDR_TRIG_LSB _u(0) -#define DMA_CH7_AL2_WRITE_ADDR_TRIG_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH7_AL3_CTRL -// Description : Alias for channel 7 CTRL register -#define DMA_CH7_AL3_CTRL_OFFSET _u(0x000001f0) -#define DMA_CH7_AL3_CTRL_BITS _u(0xffffffff) -#define DMA_CH7_AL3_CTRL_RESET "-" -#define DMA_CH7_AL3_CTRL_MSB _u(31) -#define DMA_CH7_AL3_CTRL_LSB _u(0) -#define DMA_CH7_AL3_CTRL_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH7_AL3_WRITE_ADDR -// Description : Alias for channel 7 WRITE_ADDR register -#define DMA_CH7_AL3_WRITE_ADDR_OFFSET _u(0x000001f4) -#define DMA_CH7_AL3_WRITE_ADDR_BITS _u(0xffffffff) -#define DMA_CH7_AL3_WRITE_ADDR_RESET "-" -#define DMA_CH7_AL3_WRITE_ADDR_MSB _u(31) -#define DMA_CH7_AL3_WRITE_ADDR_LSB _u(0) -#define DMA_CH7_AL3_WRITE_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH7_AL3_TRANS_COUNT -// Description : Alias for channel 7 TRANS_COUNT register -#define DMA_CH7_AL3_TRANS_COUNT_OFFSET _u(0x000001f8) -#define DMA_CH7_AL3_TRANS_COUNT_BITS _u(0xffffffff) -#define DMA_CH7_AL3_TRANS_COUNT_RESET "-" -#define DMA_CH7_AL3_TRANS_COUNT_MSB _u(31) -#define DMA_CH7_AL3_TRANS_COUNT_LSB _u(0) -#define DMA_CH7_AL3_TRANS_COUNT_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH7_AL3_READ_ADDR_TRIG -// Description : Alias for channel 7 READ_ADDR register -// This is a trigger register (0xc). Writing a nonzero value will -// reload the channel counter and start the channel. -#define DMA_CH7_AL3_READ_ADDR_TRIG_OFFSET _u(0x000001fc) -#define DMA_CH7_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff) -#define DMA_CH7_AL3_READ_ADDR_TRIG_RESET "-" -#define DMA_CH7_AL3_READ_ADDR_TRIG_MSB _u(31) -#define DMA_CH7_AL3_READ_ADDR_TRIG_LSB _u(0) -#define DMA_CH7_AL3_READ_ADDR_TRIG_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH8_READ_ADDR -// Description : DMA Channel 8 Read Address pointer -// This register updates automatically each time a read completes. -// The current value is the next address to be read by this -// channel. -#define DMA_CH8_READ_ADDR_OFFSET _u(0x00000200) -#define DMA_CH8_READ_ADDR_BITS _u(0xffffffff) -#define DMA_CH8_READ_ADDR_RESET _u(0x00000000) -#define DMA_CH8_READ_ADDR_MSB _u(31) -#define DMA_CH8_READ_ADDR_LSB _u(0) -#define DMA_CH8_READ_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH8_WRITE_ADDR -// Description : DMA Channel 8 Write Address pointer -// This register updates automatically each time a write -// completes. The current value is the next address to be written -// by this channel. -#define DMA_CH8_WRITE_ADDR_OFFSET _u(0x00000204) -#define DMA_CH8_WRITE_ADDR_BITS _u(0xffffffff) -#define DMA_CH8_WRITE_ADDR_RESET _u(0x00000000) -#define DMA_CH8_WRITE_ADDR_MSB _u(31) -#define DMA_CH8_WRITE_ADDR_LSB _u(0) -#define DMA_CH8_WRITE_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH8_TRANS_COUNT -// Description : DMA Channel 8 Transfer Count -#define DMA_CH8_TRANS_COUNT_OFFSET _u(0x00000208) -#define DMA_CH8_TRANS_COUNT_BITS _u(0xffffffff) -#define DMA_CH8_TRANS_COUNT_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : DMA_CH8_TRANS_COUNT_MODE -// Description : When MODE is 0x0, the transfer count decrements with each -// transfer until 0, and then the channel triggers the next -// channel indicated by CTRL_CHAIN_TO. -// -// When MODE is 0x1, the transfer count decrements with each -// transfer until 0, and then the channel re-triggers itself, in -// addition to the trigger indicated by CTRL_CHAIN_TO. This is -// useful for e.g. an endless ring-buffer DMA with periodic -// interrupts. -// -// When MODE is 0xf, the transfer count does not decrement. The -// DMA channel performs an endless sequence of transfers, never -// triggering other channels or raising interrupts, until an ABORT -// is raised. -// -// All other values are reserved. -// 0x0 -> NORMAL -// 0x1 -> TRIGGER_SELF -// 0xf -> ENDLESS -#define DMA_CH8_TRANS_COUNT_MODE_RESET _u(0x0) -#define DMA_CH8_TRANS_COUNT_MODE_BITS _u(0xf0000000) -#define DMA_CH8_TRANS_COUNT_MODE_MSB _u(31) -#define DMA_CH8_TRANS_COUNT_MODE_LSB _u(28) -#define DMA_CH8_TRANS_COUNT_MODE_ACCESS "RW" -#define DMA_CH8_TRANS_COUNT_MODE_VALUE_NORMAL _u(0x0) -#define DMA_CH8_TRANS_COUNT_MODE_VALUE_TRIGGER_SELF _u(0x1) -#define DMA_CH8_TRANS_COUNT_MODE_VALUE_ENDLESS _u(0xf) -// ----------------------------------------------------------------------------- -// Field : DMA_CH8_TRANS_COUNT_COUNT -// Description : 28-bit transfer count (256 million transfers maximum). -// -// Program the number of bus transfers a channel will perform -// before halting. Note that, if transfers are larger than one -// byte in size, this is not equal to the number of bytes -// transferred (see CTRL_DATA_SIZE). -// -// When the channel is active, reading this register shows the -// number of transfers remaining, updating automatically each time -// a write transfer completes. -// -// Writing this register sets the RELOAD value for the transfer -// counter. Each time this channel is triggered, the RELOAD value -// is copied into the live transfer counter. The channel can be -// started multiple times, and will perform the same number of -// transfers each time, as programmed by most recent write. -// -// The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT -// is used as a trigger, the written value is used immediately as -// the length of the new transfer sequence, as well as being -// written to RELOAD. -#define DMA_CH8_TRANS_COUNT_COUNT_RESET _u(0x0000000) -#define DMA_CH8_TRANS_COUNT_COUNT_BITS _u(0x0fffffff) -#define DMA_CH8_TRANS_COUNT_COUNT_MSB _u(27) -#define DMA_CH8_TRANS_COUNT_COUNT_LSB _u(0) -#define DMA_CH8_TRANS_COUNT_COUNT_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH8_CTRL_TRIG -// Description : DMA Channel 8 Control and Status -#define DMA_CH8_CTRL_TRIG_OFFSET _u(0x0000020c) -#define DMA_CH8_CTRL_TRIG_BITS _u(0xe7ffffff) -#define DMA_CH8_CTRL_TRIG_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : DMA_CH8_CTRL_TRIG_AHB_ERROR -// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel -// halts when it encounters any bus error, and always raises its -// channel IRQ flag. -#define DMA_CH8_CTRL_TRIG_AHB_ERROR_RESET _u(0x0) -#define DMA_CH8_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000) -#define DMA_CH8_CTRL_TRIG_AHB_ERROR_MSB _u(31) -#define DMA_CH8_CTRL_TRIG_AHB_ERROR_LSB _u(31) -#define DMA_CH8_CTRL_TRIG_AHB_ERROR_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : DMA_CH8_CTRL_TRIG_READ_ERROR -// Description : If 1, the channel received a read bus error. Write one to -// clear. -// READ_ADDR shows the approximate address where the bus error was -// encountered (will not be earlier, or more than 3 transfers -// later) -#define DMA_CH8_CTRL_TRIG_READ_ERROR_RESET _u(0x0) -#define DMA_CH8_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000) -#define DMA_CH8_CTRL_TRIG_READ_ERROR_MSB _u(30) -#define DMA_CH8_CTRL_TRIG_READ_ERROR_LSB _u(30) -#define DMA_CH8_CTRL_TRIG_READ_ERROR_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : DMA_CH8_CTRL_TRIG_WRITE_ERROR -// Description : If 1, the channel received a write bus error. Write one to -// clear. -// WRITE_ADDR shows the approximate address where the bus error -// was encountered (will not be earlier, or more than 5 transfers -// later) -#define DMA_CH8_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0) -#define DMA_CH8_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000) -#define DMA_CH8_CTRL_TRIG_WRITE_ERROR_MSB _u(29) -#define DMA_CH8_CTRL_TRIG_WRITE_ERROR_LSB _u(29) -#define DMA_CH8_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : DMA_CH8_CTRL_TRIG_BUSY -// Description : This flag goes high when the channel starts a new transfer -// sequence, and low when the last transfer of that sequence -// completes. Clearing EN while BUSY is high pauses the channel, -// and BUSY will stay high while paused. -// -// To terminate a sequence early (and clear the BUSY flag), see -// CHAN_ABORT. -#define DMA_CH8_CTRL_TRIG_BUSY_RESET _u(0x0) -#define DMA_CH8_CTRL_TRIG_BUSY_BITS _u(0x04000000) -#define DMA_CH8_CTRL_TRIG_BUSY_MSB _u(26) -#define DMA_CH8_CTRL_TRIG_BUSY_LSB _u(26) -#define DMA_CH8_CTRL_TRIG_BUSY_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : DMA_CH8_CTRL_TRIG_SNIFF_EN -// Description : If 1, this channel's data transfers are visible to the sniff -// hardware, and each transfer will advance the state of the -// checksum. This only applies if the sniff hardware is enabled, -// and has this channel selected. -// -// This allows checksum to be enabled or disabled on a per- -// control- block basis. -#define DMA_CH8_CTRL_TRIG_SNIFF_EN_RESET _u(0x0) -#define DMA_CH8_CTRL_TRIG_SNIFF_EN_BITS _u(0x02000000) -#define DMA_CH8_CTRL_TRIG_SNIFF_EN_MSB _u(25) -#define DMA_CH8_CTRL_TRIG_SNIFF_EN_LSB _u(25) -#define DMA_CH8_CTRL_TRIG_SNIFF_EN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH8_CTRL_TRIG_BSWAP -// Description : Apply byte-swap transformation to DMA data. -// For byte data, this has no effect. For halfword data, the two -// bytes of each halfword are swapped. For word data, the four -// bytes of each word are swapped to reverse order. -#define DMA_CH8_CTRL_TRIG_BSWAP_RESET _u(0x0) -#define DMA_CH8_CTRL_TRIG_BSWAP_BITS _u(0x01000000) -#define DMA_CH8_CTRL_TRIG_BSWAP_MSB _u(24) -#define DMA_CH8_CTRL_TRIG_BSWAP_LSB _u(24) -#define DMA_CH8_CTRL_TRIG_BSWAP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH8_CTRL_TRIG_IRQ_QUIET -// Description : In QUIET mode, the channel does not generate IRQs at the end of -// every transfer block. Instead, an IRQ is raised when NULL is -// written to a trigger register, indicating the end of a control -// block chain. -// -// This reduces the number of interrupts to be serviced by the CPU -// when transferring a DMA chain of many small control blocks. -#define DMA_CH8_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0) -#define DMA_CH8_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00800000) -#define DMA_CH8_CTRL_TRIG_IRQ_QUIET_MSB _u(23) -#define DMA_CH8_CTRL_TRIG_IRQ_QUIET_LSB _u(23) -#define DMA_CH8_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH8_CTRL_TRIG_TREQ_SEL -// Description : Select a Transfer Request signal. -// The channel uses the transfer request signal to pace its data -// transfer rate. Sources for TREQ signals are internal (TIMERS) -// or external (DREQ, a Data Request from the system). -// 0x0 to 0x3a -> select DREQ n as TREQ -// 0x3b -> Select Timer 0 as TREQ -// 0x3c -> Select Timer 1 as TREQ -// 0x3d -> Select Timer 2 as TREQ (Optional) -// 0x3e -> Select Timer 3 as TREQ (Optional) -// 0x3f -> Permanent request, for unpaced transfers. -#define DMA_CH8_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) -#define DMA_CH8_CTRL_TRIG_TREQ_SEL_BITS _u(0x007e0000) -#define DMA_CH8_CTRL_TRIG_TREQ_SEL_MSB _u(22) -#define DMA_CH8_CTRL_TRIG_TREQ_SEL_LSB _u(17) -#define DMA_CH8_CTRL_TRIG_TREQ_SEL_ACCESS "RW" -#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) -#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) -#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) -#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) -#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) -// ----------------------------------------------------------------------------- -// Field : DMA_CH8_CTRL_TRIG_CHAIN_TO -// Description : When this channel completes, it will trigger the channel -// indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this -// channel)_. -// -// Note this field resets to 0, so channels 1 and above will chain -// to channel 0 by default. Set this field to avoid this -// behaviour. -#define DMA_CH8_CTRL_TRIG_CHAIN_TO_RESET _u(0x0) -#define DMA_CH8_CTRL_TRIG_CHAIN_TO_BITS _u(0x0001e000) -#define DMA_CH8_CTRL_TRIG_CHAIN_TO_MSB _u(16) -#define DMA_CH8_CTRL_TRIG_CHAIN_TO_LSB _u(13) -#define DMA_CH8_CTRL_TRIG_CHAIN_TO_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH8_CTRL_TRIG_RING_SEL -// Description : Select whether RING_SIZE applies to read or write addresses. -// If 0, read addresses are wrapped on a (1 << RING_SIZE) -// boundary. If 1, write addresses are wrapped. -#define DMA_CH8_CTRL_TRIG_RING_SEL_RESET _u(0x0) -#define DMA_CH8_CTRL_TRIG_RING_SEL_BITS _u(0x00001000) -#define DMA_CH8_CTRL_TRIG_RING_SEL_MSB _u(12) -#define DMA_CH8_CTRL_TRIG_RING_SEL_LSB _u(12) -#define DMA_CH8_CTRL_TRIG_RING_SEL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH8_CTRL_TRIG_RING_SIZE -// Description : Size of address wrap region. If 0, don't wrap. For values n > -// 0, only the lower n bits of the address will change. This wraps -// the address on a (1 << n) byte boundary, facilitating access to -// naturally-aligned ring buffers. -// -// Ring sizes between 2 and 32768 bytes are possible. This can -// apply to either read or write addresses, based on value of -// RING_SEL. -// 0x0 -> RING_NONE -#define DMA_CH8_CTRL_TRIG_RING_SIZE_RESET _u(0x0) -#define DMA_CH8_CTRL_TRIG_RING_SIZE_BITS _u(0x00000f00) -#define DMA_CH8_CTRL_TRIG_RING_SIZE_MSB _u(11) -#define DMA_CH8_CTRL_TRIG_RING_SIZE_LSB _u(8) -#define DMA_CH8_CTRL_TRIG_RING_SIZE_ACCESS "RW" -#define DMA_CH8_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0) -// ----------------------------------------------------------------------------- -// Field : DMA_CH8_CTRL_TRIG_INCR_WRITE_REV -// Description : If 1, and INCR_WRITE is 1, the write address is decremented -// rather than incremented with each transfer. -// -// If 1, and INCR_WRITE is 0, this otherwise-unused combination -// causes the write address to be incremented by twice the -// transfer size, i.e. skipping over alternate addresses. -#define DMA_CH8_CTRL_TRIG_INCR_WRITE_REV_RESET _u(0x0) -#define DMA_CH8_CTRL_TRIG_INCR_WRITE_REV_BITS _u(0x00000080) -#define DMA_CH8_CTRL_TRIG_INCR_WRITE_REV_MSB _u(7) -#define DMA_CH8_CTRL_TRIG_INCR_WRITE_REV_LSB _u(7) -#define DMA_CH8_CTRL_TRIG_INCR_WRITE_REV_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH8_CTRL_TRIG_INCR_WRITE -// Description : If 1, the write address increments with each transfer. If 0, -// each write is directed to the same, initial address. -// -// Generally this should be disabled for memory-to-peripheral -// transfers. -#define DMA_CH8_CTRL_TRIG_INCR_WRITE_RESET _u(0x0) -#define DMA_CH8_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000040) -#define DMA_CH8_CTRL_TRIG_INCR_WRITE_MSB _u(6) -#define DMA_CH8_CTRL_TRIG_INCR_WRITE_LSB _u(6) -#define DMA_CH8_CTRL_TRIG_INCR_WRITE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH8_CTRL_TRIG_INCR_READ_REV -// Description : If 1, and INCR_READ is 1, the read address is decremented -// rather than incremented with each transfer. -// -// If 1, and INCR_READ is 0, this otherwise-unused combination -// causes the read address to be incremented by twice the transfer -// size, i.e. skipping over alternate addresses. -#define DMA_CH8_CTRL_TRIG_INCR_READ_REV_RESET _u(0x0) -#define DMA_CH8_CTRL_TRIG_INCR_READ_REV_BITS _u(0x00000020) -#define DMA_CH8_CTRL_TRIG_INCR_READ_REV_MSB _u(5) -#define DMA_CH8_CTRL_TRIG_INCR_READ_REV_LSB _u(5) -#define DMA_CH8_CTRL_TRIG_INCR_READ_REV_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH8_CTRL_TRIG_INCR_READ -// Description : If 1, the read address increments with each transfer. If 0, -// each read is directed to the same, initial address. -// -// Generally this should be disabled for peripheral-to-memory -// transfers. -#define DMA_CH8_CTRL_TRIG_INCR_READ_RESET _u(0x0) -#define DMA_CH8_CTRL_TRIG_INCR_READ_BITS _u(0x00000010) -#define DMA_CH8_CTRL_TRIG_INCR_READ_MSB _u(4) -#define DMA_CH8_CTRL_TRIG_INCR_READ_LSB _u(4) -#define DMA_CH8_CTRL_TRIG_INCR_READ_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH8_CTRL_TRIG_DATA_SIZE -// Description : Set the size of each bus transfer (byte/halfword/word). -// READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) -// with each transfer. -// 0x0 -> SIZE_BYTE -// 0x1 -> SIZE_HALFWORD -// 0x2 -> SIZE_WORD -#define DMA_CH8_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) -#define DMA_CH8_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) -#define DMA_CH8_CTRL_TRIG_DATA_SIZE_MSB _u(3) -#define DMA_CH8_CTRL_TRIG_DATA_SIZE_LSB _u(2) -#define DMA_CH8_CTRL_TRIG_DATA_SIZE_ACCESS "RW" -#define DMA_CH8_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) -#define DMA_CH8_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1) -#define DMA_CH8_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) -// ----------------------------------------------------------------------------- -// Field : DMA_CH8_CTRL_TRIG_HIGH_PRIORITY -// Description : HIGH_PRIORITY gives a channel preferential treatment in issue -// scheduling: in each scheduling round, all high priority -// channels are considered first, and then only a single low -// priority channel, before returning to the high priority -// channels. -// -// This only affects the order in which the DMA schedules -// channels. The DMA's bus priority is not changed. If the DMA is -// not saturated then a low priority channel will see no loss of -// throughput. -#define DMA_CH8_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0) -#define DMA_CH8_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002) -#define DMA_CH8_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1) -#define DMA_CH8_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1) -#define DMA_CH8_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH8_CTRL_TRIG_EN -// Description : DMA Channel Enable. -// When 1, the channel will respond to triggering events, which -// will cause it to become BUSY and start transferring data. When -// 0, the channel will ignore triggers, stop issuing transfers, -// and pause the current transfer sequence (i.e. BUSY will remain -// high if already high) -#define DMA_CH8_CTRL_TRIG_EN_RESET _u(0x0) -#define DMA_CH8_CTRL_TRIG_EN_BITS _u(0x00000001) -#define DMA_CH8_CTRL_TRIG_EN_MSB _u(0) -#define DMA_CH8_CTRL_TRIG_EN_LSB _u(0) -#define DMA_CH8_CTRL_TRIG_EN_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH8_AL1_CTRL -// Description : Alias for channel 8 CTRL register -#define DMA_CH8_AL1_CTRL_OFFSET _u(0x00000210) -#define DMA_CH8_AL1_CTRL_BITS _u(0xffffffff) -#define DMA_CH8_AL1_CTRL_RESET "-" -#define DMA_CH8_AL1_CTRL_MSB _u(31) -#define DMA_CH8_AL1_CTRL_LSB _u(0) -#define DMA_CH8_AL1_CTRL_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH8_AL1_READ_ADDR -// Description : Alias for channel 8 READ_ADDR register -#define DMA_CH8_AL1_READ_ADDR_OFFSET _u(0x00000214) -#define DMA_CH8_AL1_READ_ADDR_BITS _u(0xffffffff) -#define DMA_CH8_AL1_READ_ADDR_RESET "-" -#define DMA_CH8_AL1_READ_ADDR_MSB _u(31) -#define DMA_CH8_AL1_READ_ADDR_LSB _u(0) -#define DMA_CH8_AL1_READ_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH8_AL1_WRITE_ADDR -// Description : Alias for channel 8 WRITE_ADDR register -#define DMA_CH8_AL1_WRITE_ADDR_OFFSET _u(0x00000218) -#define DMA_CH8_AL1_WRITE_ADDR_BITS _u(0xffffffff) -#define DMA_CH8_AL1_WRITE_ADDR_RESET "-" -#define DMA_CH8_AL1_WRITE_ADDR_MSB _u(31) -#define DMA_CH8_AL1_WRITE_ADDR_LSB _u(0) -#define DMA_CH8_AL1_WRITE_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH8_AL1_TRANS_COUNT_TRIG -// Description : Alias for channel 8 TRANS_COUNT register -// This is a trigger register (0xc). Writing a nonzero value will -// reload the channel counter and start the channel. -#define DMA_CH8_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x0000021c) -#define DMA_CH8_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff) -#define DMA_CH8_AL1_TRANS_COUNT_TRIG_RESET "-" -#define DMA_CH8_AL1_TRANS_COUNT_TRIG_MSB _u(31) -#define DMA_CH8_AL1_TRANS_COUNT_TRIG_LSB _u(0) -#define DMA_CH8_AL1_TRANS_COUNT_TRIG_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH8_AL2_CTRL -// Description : Alias for channel 8 CTRL register -#define DMA_CH8_AL2_CTRL_OFFSET _u(0x00000220) -#define DMA_CH8_AL2_CTRL_BITS _u(0xffffffff) -#define DMA_CH8_AL2_CTRL_RESET "-" -#define DMA_CH8_AL2_CTRL_MSB _u(31) -#define DMA_CH8_AL2_CTRL_LSB _u(0) -#define DMA_CH8_AL2_CTRL_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH8_AL2_TRANS_COUNT -// Description : Alias for channel 8 TRANS_COUNT register -#define DMA_CH8_AL2_TRANS_COUNT_OFFSET _u(0x00000224) -#define DMA_CH8_AL2_TRANS_COUNT_BITS _u(0xffffffff) -#define DMA_CH8_AL2_TRANS_COUNT_RESET "-" -#define DMA_CH8_AL2_TRANS_COUNT_MSB _u(31) -#define DMA_CH8_AL2_TRANS_COUNT_LSB _u(0) -#define DMA_CH8_AL2_TRANS_COUNT_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH8_AL2_READ_ADDR -// Description : Alias for channel 8 READ_ADDR register -#define DMA_CH8_AL2_READ_ADDR_OFFSET _u(0x00000228) -#define DMA_CH8_AL2_READ_ADDR_BITS _u(0xffffffff) -#define DMA_CH8_AL2_READ_ADDR_RESET "-" -#define DMA_CH8_AL2_READ_ADDR_MSB _u(31) -#define DMA_CH8_AL2_READ_ADDR_LSB _u(0) -#define DMA_CH8_AL2_READ_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH8_AL2_WRITE_ADDR_TRIG -// Description : Alias for channel 8 WRITE_ADDR register -// This is a trigger register (0xc). Writing a nonzero value will -// reload the channel counter and start the channel. -#define DMA_CH8_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x0000022c) -#define DMA_CH8_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff) -#define DMA_CH8_AL2_WRITE_ADDR_TRIG_RESET "-" -#define DMA_CH8_AL2_WRITE_ADDR_TRIG_MSB _u(31) -#define DMA_CH8_AL2_WRITE_ADDR_TRIG_LSB _u(0) -#define DMA_CH8_AL2_WRITE_ADDR_TRIG_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH8_AL3_CTRL -// Description : Alias for channel 8 CTRL register -#define DMA_CH8_AL3_CTRL_OFFSET _u(0x00000230) -#define DMA_CH8_AL3_CTRL_BITS _u(0xffffffff) -#define DMA_CH8_AL3_CTRL_RESET "-" -#define DMA_CH8_AL3_CTRL_MSB _u(31) -#define DMA_CH8_AL3_CTRL_LSB _u(0) -#define DMA_CH8_AL3_CTRL_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH8_AL3_WRITE_ADDR -// Description : Alias for channel 8 WRITE_ADDR register -#define DMA_CH8_AL3_WRITE_ADDR_OFFSET _u(0x00000234) -#define DMA_CH8_AL3_WRITE_ADDR_BITS _u(0xffffffff) -#define DMA_CH8_AL3_WRITE_ADDR_RESET "-" -#define DMA_CH8_AL3_WRITE_ADDR_MSB _u(31) -#define DMA_CH8_AL3_WRITE_ADDR_LSB _u(0) -#define DMA_CH8_AL3_WRITE_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH8_AL3_TRANS_COUNT -// Description : Alias for channel 8 TRANS_COUNT register -#define DMA_CH8_AL3_TRANS_COUNT_OFFSET _u(0x00000238) -#define DMA_CH8_AL3_TRANS_COUNT_BITS _u(0xffffffff) -#define DMA_CH8_AL3_TRANS_COUNT_RESET "-" -#define DMA_CH8_AL3_TRANS_COUNT_MSB _u(31) -#define DMA_CH8_AL3_TRANS_COUNT_LSB _u(0) -#define DMA_CH8_AL3_TRANS_COUNT_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH8_AL3_READ_ADDR_TRIG -// Description : Alias for channel 8 READ_ADDR register -// This is a trigger register (0xc). Writing a nonzero value will -// reload the channel counter and start the channel. -#define DMA_CH8_AL3_READ_ADDR_TRIG_OFFSET _u(0x0000023c) -#define DMA_CH8_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff) -#define DMA_CH8_AL3_READ_ADDR_TRIG_RESET "-" -#define DMA_CH8_AL3_READ_ADDR_TRIG_MSB _u(31) -#define DMA_CH8_AL3_READ_ADDR_TRIG_LSB _u(0) -#define DMA_CH8_AL3_READ_ADDR_TRIG_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH9_READ_ADDR -// Description : DMA Channel 9 Read Address pointer -// This register updates automatically each time a read completes. -// The current value is the next address to be read by this -// channel. -#define DMA_CH9_READ_ADDR_OFFSET _u(0x00000240) -#define DMA_CH9_READ_ADDR_BITS _u(0xffffffff) -#define DMA_CH9_READ_ADDR_RESET _u(0x00000000) -#define DMA_CH9_READ_ADDR_MSB _u(31) -#define DMA_CH9_READ_ADDR_LSB _u(0) -#define DMA_CH9_READ_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH9_WRITE_ADDR -// Description : DMA Channel 9 Write Address pointer -// This register updates automatically each time a write -// completes. The current value is the next address to be written -// by this channel. -#define DMA_CH9_WRITE_ADDR_OFFSET _u(0x00000244) -#define DMA_CH9_WRITE_ADDR_BITS _u(0xffffffff) -#define DMA_CH9_WRITE_ADDR_RESET _u(0x00000000) -#define DMA_CH9_WRITE_ADDR_MSB _u(31) -#define DMA_CH9_WRITE_ADDR_LSB _u(0) -#define DMA_CH9_WRITE_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH9_TRANS_COUNT -// Description : DMA Channel 9 Transfer Count -#define DMA_CH9_TRANS_COUNT_OFFSET _u(0x00000248) -#define DMA_CH9_TRANS_COUNT_BITS _u(0xffffffff) -#define DMA_CH9_TRANS_COUNT_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : DMA_CH9_TRANS_COUNT_MODE -// Description : When MODE is 0x0, the transfer count decrements with each -// transfer until 0, and then the channel triggers the next -// channel indicated by CTRL_CHAIN_TO. -// -// When MODE is 0x1, the transfer count decrements with each -// transfer until 0, and then the channel re-triggers itself, in -// addition to the trigger indicated by CTRL_CHAIN_TO. This is -// useful for e.g. an endless ring-buffer DMA with periodic -// interrupts. -// -// When MODE is 0xf, the transfer count does not decrement. The -// DMA channel performs an endless sequence of transfers, never -// triggering other channels or raising interrupts, until an ABORT -// is raised. -// -// All other values are reserved. -// 0x0 -> NORMAL -// 0x1 -> TRIGGER_SELF -// 0xf -> ENDLESS -#define DMA_CH9_TRANS_COUNT_MODE_RESET _u(0x0) -#define DMA_CH9_TRANS_COUNT_MODE_BITS _u(0xf0000000) -#define DMA_CH9_TRANS_COUNT_MODE_MSB _u(31) -#define DMA_CH9_TRANS_COUNT_MODE_LSB _u(28) -#define DMA_CH9_TRANS_COUNT_MODE_ACCESS "RW" -#define DMA_CH9_TRANS_COUNT_MODE_VALUE_NORMAL _u(0x0) -#define DMA_CH9_TRANS_COUNT_MODE_VALUE_TRIGGER_SELF _u(0x1) -#define DMA_CH9_TRANS_COUNT_MODE_VALUE_ENDLESS _u(0xf) -// ----------------------------------------------------------------------------- -// Field : DMA_CH9_TRANS_COUNT_COUNT -// Description : 28-bit transfer count (256 million transfers maximum). -// -// Program the number of bus transfers a channel will perform -// before halting. Note that, if transfers are larger than one -// byte in size, this is not equal to the number of bytes -// transferred (see CTRL_DATA_SIZE). -// -// When the channel is active, reading this register shows the -// number of transfers remaining, updating automatically each time -// a write transfer completes. -// -// Writing this register sets the RELOAD value for the transfer -// counter. Each time this channel is triggered, the RELOAD value -// is copied into the live transfer counter. The channel can be -// started multiple times, and will perform the same number of -// transfers each time, as programmed by most recent write. -// -// The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT -// is used as a trigger, the written value is used immediately as -// the length of the new transfer sequence, as well as being -// written to RELOAD. -#define DMA_CH9_TRANS_COUNT_COUNT_RESET _u(0x0000000) -#define DMA_CH9_TRANS_COUNT_COUNT_BITS _u(0x0fffffff) -#define DMA_CH9_TRANS_COUNT_COUNT_MSB _u(27) -#define DMA_CH9_TRANS_COUNT_COUNT_LSB _u(0) -#define DMA_CH9_TRANS_COUNT_COUNT_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH9_CTRL_TRIG -// Description : DMA Channel 9 Control and Status -#define DMA_CH9_CTRL_TRIG_OFFSET _u(0x0000024c) -#define DMA_CH9_CTRL_TRIG_BITS _u(0xe7ffffff) -#define DMA_CH9_CTRL_TRIG_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : DMA_CH9_CTRL_TRIG_AHB_ERROR -// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel -// halts when it encounters any bus error, and always raises its -// channel IRQ flag. -#define DMA_CH9_CTRL_TRIG_AHB_ERROR_RESET _u(0x0) -#define DMA_CH9_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000) -#define DMA_CH9_CTRL_TRIG_AHB_ERROR_MSB _u(31) -#define DMA_CH9_CTRL_TRIG_AHB_ERROR_LSB _u(31) -#define DMA_CH9_CTRL_TRIG_AHB_ERROR_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : DMA_CH9_CTRL_TRIG_READ_ERROR -// Description : If 1, the channel received a read bus error. Write one to -// clear. -// READ_ADDR shows the approximate address where the bus error was -// encountered (will not be earlier, or more than 3 transfers -// later) -#define DMA_CH9_CTRL_TRIG_READ_ERROR_RESET _u(0x0) -#define DMA_CH9_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000) -#define DMA_CH9_CTRL_TRIG_READ_ERROR_MSB _u(30) -#define DMA_CH9_CTRL_TRIG_READ_ERROR_LSB _u(30) -#define DMA_CH9_CTRL_TRIG_READ_ERROR_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : DMA_CH9_CTRL_TRIG_WRITE_ERROR -// Description : If 1, the channel received a write bus error. Write one to -// clear. -// WRITE_ADDR shows the approximate address where the bus error -// was encountered (will not be earlier, or more than 5 transfers -// later) -#define DMA_CH9_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0) -#define DMA_CH9_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000) -#define DMA_CH9_CTRL_TRIG_WRITE_ERROR_MSB _u(29) -#define DMA_CH9_CTRL_TRIG_WRITE_ERROR_LSB _u(29) -#define DMA_CH9_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : DMA_CH9_CTRL_TRIG_BUSY -// Description : This flag goes high when the channel starts a new transfer -// sequence, and low when the last transfer of that sequence -// completes. Clearing EN while BUSY is high pauses the channel, -// and BUSY will stay high while paused. -// -// To terminate a sequence early (and clear the BUSY flag), see -// CHAN_ABORT. -#define DMA_CH9_CTRL_TRIG_BUSY_RESET _u(0x0) -#define DMA_CH9_CTRL_TRIG_BUSY_BITS _u(0x04000000) -#define DMA_CH9_CTRL_TRIG_BUSY_MSB _u(26) -#define DMA_CH9_CTRL_TRIG_BUSY_LSB _u(26) -#define DMA_CH9_CTRL_TRIG_BUSY_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : DMA_CH9_CTRL_TRIG_SNIFF_EN -// Description : If 1, this channel's data transfers are visible to the sniff -// hardware, and each transfer will advance the state of the -// checksum. This only applies if the sniff hardware is enabled, -// and has this channel selected. -// -// This allows checksum to be enabled or disabled on a per- -// control- block basis. -#define DMA_CH9_CTRL_TRIG_SNIFF_EN_RESET _u(0x0) -#define DMA_CH9_CTRL_TRIG_SNIFF_EN_BITS _u(0x02000000) -#define DMA_CH9_CTRL_TRIG_SNIFF_EN_MSB _u(25) -#define DMA_CH9_CTRL_TRIG_SNIFF_EN_LSB _u(25) -#define DMA_CH9_CTRL_TRIG_SNIFF_EN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH9_CTRL_TRIG_BSWAP -// Description : Apply byte-swap transformation to DMA data. -// For byte data, this has no effect. For halfword data, the two -// bytes of each halfword are swapped. For word data, the four -// bytes of each word are swapped to reverse order. -#define DMA_CH9_CTRL_TRIG_BSWAP_RESET _u(0x0) -#define DMA_CH9_CTRL_TRIG_BSWAP_BITS _u(0x01000000) -#define DMA_CH9_CTRL_TRIG_BSWAP_MSB _u(24) -#define DMA_CH9_CTRL_TRIG_BSWAP_LSB _u(24) -#define DMA_CH9_CTRL_TRIG_BSWAP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH9_CTRL_TRIG_IRQ_QUIET -// Description : In QUIET mode, the channel does not generate IRQs at the end of -// every transfer block. Instead, an IRQ is raised when NULL is -// written to a trigger register, indicating the end of a control -// block chain. -// -// This reduces the number of interrupts to be serviced by the CPU -// when transferring a DMA chain of many small control blocks. -#define DMA_CH9_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0) -#define DMA_CH9_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00800000) -#define DMA_CH9_CTRL_TRIG_IRQ_QUIET_MSB _u(23) -#define DMA_CH9_CTRL_TRIG_IRQ_QUIET_LSB _u(23) -#define DMA_CH9_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH9_CTRL_TRIG_TREQ_SEL -// Description : Select a Transfer Request signal. -// The channel uses the transfer request signal to pace its data -// transfer rate. Sources for TREQ signals are internal (TIMERS) -// or external (DREQ, a Data Request from the system). -// 0x0 to 0x3a -> select DREQ n as TREQ -// 0x3b -> Select Timer 0 as TREQ -// 0x3c -> Select Timer 1 as TREQ -// 0x3d -> Select Timer 2 as TREQ (Optional) -// 0x3e -> Select Timer 3 as TREQ (Optional) -// 0x3f -> Permanent request, for unpaced transfers. -#define DMA_CH9_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) -#define DMA_CH9_CTRL_TRIG_TREQ_SEL_BITS _u(0x007e0000) -#define DMA_CH9_CTRL_TRIG_TREQ_SEL_MSB _u(22) -#define DMA_CH9_CTRL_TRIG_TREQ_SEL_LSB _u(17) -#define DMA_CH9_CTRL_TRIG_TREQ_SEL_ACCESS "RW" -#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) -#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) -#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) -#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) -#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) -// ----------------------------------------------------------------------------- -// Field : DMA_CH9_CTRL_TRIG_CHAIN_TO -// Description : When this channel completes, it will trigger the channel -// indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this -// channel)_. -// -// Note this field resets to 0, so channels 1 and above will chain -// to channel 0 by default. Set this field to avoid this -// behaviour. -#define DMA_CH9_CTRL_TRIG_CHAIN_TO_RESET _u(0x0) -#define DMA_CH9_CTRL_TRIG_CHAIN_TO_BITS _u(0x0001e000) -#define DMA_CH9_CTRL_TRIG_CHAIN_TO_MSB _u(16) -#define DMA_CH9_CTRL_TRIG_CHAIN_TO_LSB _u(13) -#define DMA_CH9_CTRL_TRIG_CHAIN_TO_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH9_CTRL_TRIG_RING_SEL -// Description : Select whether RING_SIZE applies to read or write addresses. -// If 0, read addresses are wrapped on a (1 << RING_SIZE) -// boundary. If 1, write addresses are wrapped. -#define DMA_CH9_CTRL_TRIG_RING_SEL_RESET _u(0x0) -#define DMA_CH9_CTRL_TRIG_RING_SEL_BITS _u(0x00001000) -#define DMA_CH9_CTRL_TRIG_RING_SEL_MSB _u(12) -#define DMA_CH9_CTRL_TRIG_RING_SEL_LSB _u(12) -#define DMA_CH9_CTRL_TRIG_RING_SEL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH9_CTRL_TRIG_RING_SIZE -// Description : Size of address wrap region. If 0, don't wrap. For values n > -// 0, only the lower n bits of the address will change. This wraps -// the address on a (1 << n) byte boundary, facilitating access to -// naturally-aligned ring buffers. -// -// Ring sizes between 2 and 32768 bytes are possible. This can -// apply to either read or write addresses, based on value of -// RING_SEL. -// 0x0 -> RING_NONE -#define DMA_CH9_CTRL_TRIG_RING_SIZE_RESET _u(0x0) -#define DMA_CH9_CTRL_TRIG_RING_SIZE_BITS _u(0x00000f00) -#define DMA_CH9_CTRL_TRIG_RING_SIZE_MSB _u(11) -#define DMA_CH9_CTRL_TRIG_RING_SIZE_LSB _u(8) -#define DMA_CH9_CTRL_TRIG_RING_SIZE_ACCESS "RW" -#define DMA_CH9_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0) -// ----------------------------------------------------------------------------- -// Field : DMA_CH9_CTRL_TRIG_INCR_WRITE_REV -// Description : If 1, and INCR_WRITE is 1, the write address is decremented -// rather than incremented with each transfer. -// -// If 1, and INCR_WRITE is 0, this otherwise-unused combination -// causes the write address to be incremented by twice the -// transfer size, i.e. skipping over alternate addresses. -#define DMA_CH9_CTRL_TRIG_INCR_WRITE_REV_RESET _u(0x0) -#define DMA_CH9_CTRL_TRIG_INCR_WRITE_REV_BITS _u(0x00000080) -#define DMA_CH9_CTRL_TRIG_INCR_WRITE_REV_MSB _u(7) -#define DMA_CH9_CTRL_TRIG_INCR_WRITE_REV_LSB _u(7) -#define DMA_CH9_CTRL_TRIG_INCR_WRITE_REV_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH9_CTRL_TRIG_INCR_WRITE -// Description : If 1, the write address increments with each transfer. If 0, -// each write is directed to the same, initial address. -// -// Generally this should be disabled for memory-to-peripheral -// transfers. -#define DMA_CH9_CTRL_TRIG_INCR_WRITE_RESET _u(0x0) -#define DMA_CH9_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000040) -#define DMA_CH9_CTRL_TRIG_INCR_WRITE_MSB _u(6) -#define DMA_CH9_CTRL_TRIG_INCR_WRITE_LSB _u(6) -#define DMA_CH9_CTRL_TRIG_INCR_WRITE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH9_CTRL_TRIG_INCR_READ_REV -// Description : If 1, and INCR_READ is 1, the read address is decremented -// rather than incremented with each transfer. -// -// If 1, and INCR_READ is 0, this otherwise-unused combination -// causes the read address to be incremented by twice the transfer -// size, i.e. skipping over alternate addresses. -#define DMA_CH9_CTRL_TRIG_INCR_READ_REV_RESET _u(0x0) -#define DMA_CH9_CTRL_TRIG_INCR_READ_REV_BITS _u(0x00000020) -#define DMA_CH9_CTRL_TRIG_INCR_READ_REV_MSB _u(5) -#define DMA_CH9_CTRL_TRIG_INCR_READ_REV_LSB _u(5) -#define DMA_CH9_CTRL_TRIG_INCR_READ_REV_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH9_CTRL_TRIG_INCR_READ -// Description : If 1, the read address increments with each transfer. If 0, -// each read is directed to the same, initial address. -// -// Generally this should be disabled for peripheral-to-memory -// transfers. -#define DMA_CH9_CTRL_TRIG_INCR_READ_RESET _u(0x0) -#define DMA_CH9_CTRL_TRIG_INCR_READ_BITS _u(0x00000010) -#define DMA_CH9_CTRL_TRIG_INCR_READ_MSB _u(4) -#define DMA_CH9_CTRL_TRIG_INCR_READ_LSB _u(4) -#define DMA_CH9_CTRL_TRIG_INCR_READ_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH9_CTRL_TRIG_DATA_SIZE -// Description : Set the size of each bus transfer (byte/halfword/word). -// READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) -// with each transfer. -// 0x0 -> SIZE_BYTE -// 0x1 -> SIZE_HALFWORD -// 0x2 -> SIZE_WORD -#define DMA_CH9_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) -#define DMA_CH9_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) -#define DMA_CH9_CTRL_TRIG_DATA_SIZE_MSB _u(3) -#define DMA_CH9_CTRL_TRIG_DATA_SIZE_LSB _u(2) -#define DMA_CH9_CTRL_TRIG_DATA_SIZE_ACCESS "RW" -#define DMA_CH9_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) -#define DMA_CH9_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1) -#define DMA_CH9_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) -// ----------------------------------------------------------------------------- -// Field : DMA_CH9_CTRL_TRIG_HIGH_PRIORITY -// Description : HIGH_PRIORITY gives a channel preferential treatment in issue -// scheduling: in each scheduling round, all high priority -// channels are considered first, and then only a single low -// priority channel, before returning to the high priority -// channels. -// -// This only affects the order in which the DMA schedules -// channels. The DMA's bus priority is not changed. If the DMA is -// not saturated then a low priority channel will see no loss of -// throughput. -#define DMA_CH9_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0) -#define DMA_CH9_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002) -#define DMA_CH9_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1) -#define DMA_CH9_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1) -#define DMA_CH9_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH9_CTRL_TRIG_EN -// Description : DMA Channel Enable. -// When 1, the channel will respond to triggering events, which -// will cause it to become BUSY and start transferring data. When -// 0, the channel will ignore triggers, stop issuing transfers, -// and pause the current transfer sequence (i.e. BUSY will remain -// high if already high) -#define DMA_CH9_CTRL_TRIG_EN_RESET _u(0x0) -#define DMA_CH9_CTRL_TRIG_EN_BITS _u(0x00000001) -#define DMA_CH9_CTRL_TRIG_EN_MSB _u(0) -#define DMA_CH9_CTRL_TRIG_EN_LSB _u(0) -#define DMA_CH9_CTRL_TRIG_EN_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH9_AL1_CTRL -// Description : Alias for channel 9 CTRL register -#define DMA_CH9_AL1_CTRL_OFFSET _u(0x00000250) -#define DMA_CH9_AL1_CTRL_BITS _u(0xffffffff) -#define DMA_CH9_AL1_CTRL_RESET "-" -#define DMA_CH9_AL1_CTRL_MSB _u(31) -#define DMA_CH9_AL1_CTRL_LSB _u(0) -#define DMA_CH9_AL1_CTRL_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH9_AL1_READ_ADDR -// Description : Alias for channel 9 READ_ADDR register -#define DMA_CH9_AL1_READ_ADDR_OFFSET _u(0x00000254) -#define DMA_CH9_AL1_READ_ADDR_BITS _u(0xffffffff) -#define DMA_CH9_AL1_READ_ADDR_RESET "-" -#define DMA_CH9_AL1_READ_ADDR_MSB _u(31) -#define DMA_CH9_AL1_READ_ADDR_LSB _u(0) -#define DMA_CH9_AL1_READ_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH9_AL1_WRITE_ADDR -// Description : Alias for channel 9 WRITE_ADDR register -#define DMA_CH9_AL1_WRITE_ADDR_OFFSET _u(0x00000258) -#define DMA_CH9_AL1_WRITE_ADDR_BITS _u(0xffffffff) -#define DMA_CH9_AL1_WRITE_ADDR_RESET "-" -#define DMA_CH9_AL1_WRITE_ADDR_MSB _u(31) -#define DMA_CH9_AL1_WRITE_ADDR_LSB _u(0) -#define DMA_CH9_AL1_WRITE_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH9_AL1_TRANS_COUNT_TRIG -// Description : Alias for channel 9 TRANS_COUNT register -// This is a trigger register (0xc). Writing a nonzero value will -// reload the channel counter and start the channel. -#define DMA_CH9_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x0000025c) -#define DMA_CH9_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff) -#define DMA_CH9_AL1_TRANS_COUNT_TRIG_RESET "-" -#define DMA_CH9_AL1_TRANS_COUNT_TRIG_MSB _u(31) -#define DMA_CH9_AL1_TRANS_COUNT_TRIG_LSB _u(0) -#define DMA_CH9_AL1_TRANS_COUNT_TRIG_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH9_AL2_CTRL -// Description : Alias for channel 9 CTRL register -#define DMA_CH9_AL2_CTRL_OFFSET _u(0x00000260) -#define DMA_CH9_AL2_CTRL_BITS _u(0xffffffff) -#define DMA_CH9_AL2_CTRL_RESET "-" -#define DMA_CH9_AL2_CTRL_MSB _u(31) -#define DMA_CH9_AL2_CTRL_LSB _u(0) -#define DMA_CH9_AL2_CTRL_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH9_AL2_TRANS_COUNT -// Description : Alias for channel 9 TRANS_COUNT register -#define DMA_CH9_AL2_TRANS_COUNT_OFFSET _u(0x00000264) -#define DMA_CH9_AL2_TRANS_COUNT_BITS _u(0xffffffff) -#define DMA_CH9_AL2_TRANS_COUNT_RESET "-" -#define DMA_CH9_AL2_TRANS_COUNT_MSB _u(31) -#define DMA_CH9_AL2_TRANS_COUNT_LSB _u(0) -#define DMA_CH9_AL2_TRANS_COUNT_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH9_AL2_READ_ADDR -// Description : Alias for channel 9 READ_ADDR register -#define DMA_CH9_AL2_READ_ADDR_OFFSET _u(0x00000268) -#define DMA_CH9_AL2_READ_ADDR_BITS _u(0xffffffff) -#define DMA_CH9_AL2_READ_ADDR_RESET "-" -#define DMA_CH9_AL2_READ_ADDR_MSB _u(31) -#define DMA_CH9_AL2_READ_ADDR_LSB _u(0) -#define DMA_CH9_AL2_READ_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH9_AL2_WRITE_ADDR_TRIG -// Description : Alias for channel 9 WRITE_ADDR register -// This is a trigger register (0xc). Writing a nonzero value will -// reload the channel counter and start the channel. -#define DMA_CH9_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x0000026c) -#define DMA_CH9_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff) -#define DMA_CH9_AL2_WRITE_ADDR_TRIG_RESET "-" -#define DMA_CH9_AL2_WRITE_ADDR_TRIG_MSB _u(31) -#define DMA_CH9_AL2_WRITE_ADDR_TRIG_LSB _u(0) -#define DMA_CH9_AL2_WRITE_ADDR_TRIG_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH9_AL3_CTRL -// Description : Alias for channel 9 CTRL register -#define DMA_CH9_AL3_CTRL_OFFSET _u(0x00000270) -#define DMA_CH9_AL3_CTRL_BITS _u(0xffffffff) -#define DMA_CH9_AL3_CTRL_RESET "-" -#define DMA_CH9_AL3_CTRL_MSB _u(31) -#define DMA_CH9_AL3_CTRL_LSB _u(0) -#define DMA_CH9_AL3_CTRL_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH9_AL3_WRITE_ADDR -// Description : Alias for channel 9 WRITE_ADDR register -#define DMA_CH9_AL3_WRITE_ADDR_OFFSET _u(0x00000274) -#define DMA_CH9_AL3_WRITE_ADDR_BITS _u(0xffffffff) -#define DMA_CH9_AL3_WRITE_ADDR_RESET "-" -#define DMA_CH9_AL3_WRITE_ADDR_MSB _u(31) -#define DMA_CH9_AL3_WRITE_ADDR_LSB _u(0) -#define DMA_CH9_AL3_WRITE_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH9_AL3_TRANS_COUNT -// Description : Alias for channel 9 TRANS_COUNT register -#define DMA_CH9_AL3_TRANS_COUNT_OFFSET _u(0x00000278) -#define DMA_CH9_AL3_TRANS_COUNT_BITS _u(0xffffffff) -#define DMA_CH9_AL3_TRANS_COUNT_RESET "-" -#define DMA_CH9_AL3_TRANS_COUNT_MSB _u(31) -#define DMA_CH9_AL3_TRANS_COUNT_LSB _u(0) -#define DMA_CH9_AL3_TRANS_COUNT_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH9_AL3_READ_ADDR_TRIG -// Description : Alias for channel 9 READ_ADDR register -// This is a trigger register (0xc). Writing a nonzero value will -// reload the channel counter and start the channel. -#define DMA_CH9_AL3_READ_ADDR_TRIG_OFFSET _u(0x0000027c) -#define DMA_CH9_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff) -#define DMA_CH9_AL3_READ_ADDR_TRIG_RESET "-" -#define DMA_CH9_AL3_READ_ADDR_TRIG_MSB _u(31) -#define DMA_CH9_AL3_READ_ADDR_TRIG_LSB _u(0) -#define DMA_CH9_AL3_READ_ADDR_TRIG_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH10_READ_ADDR -// Description : DMA Channel 10 Read Address pointer -// This register updates automatically each time a read completes. -// The current value is the next address to be read by this -// channel. -#define DMA_CH10_READ_ADDR_OFFSET _u(0x00000280) -#define DMA_CH10_READ_ADDR_BITS _u(0xffffffff) -#define DMA_CH10_READ_ADDR_RESET _u(0x00000000) -#define DMA_CH10_READ_ADDR_MSB _u(31) -#define DMA_CH10_READ_ADDR_LSB _u(0) -#define DMA_CH10_READ_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH10_WRITE_ADDR -// Description : DMA Channel 10 Write Address pointer -// This register updates automatically each time a write -// completes. The current value is the next address to be written -// by this channel. -#define DMA_CH10_WRITE_ADDR_OFFSET _u(0x00000284) -#define DMA_CH10_WRITE_ADDR_BITS _u(0xffffffff) -#define DMA_CH10_WRITE_ADDR_RESET _u(0x00000000) -#define DMA_CH10_WRITE_ADDR_MSB _u(31) -#define DMA_CH10_WRITE_ADDR_LSB _u(0) -#define DMA_CH10_WRITE_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH10_TRANS_COUNT -// Description : DMA Channel 10 Transfer Count -#define DMA_CH10_TRANS_COUNT_OFFSET _u(0x00000288) -#define DMA_CH10_TRANS_COUNT_BITS _u(0xffffffff) -#define DMA_CH10_TRANS_COUNT_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : DMA_CH10_TRANS_COUNT_MODE -// Description : When MODE is 0x0, the transfer count decrements with each -// transfer until 0, and then the channel triggers the next -// channel indicated by CTRL_CHAIN_TO. -// -// When MODE is 0x1, the transfer count decrements with each -// transfer until 0, and then the channel re-triggers itself, in -// addition to the trigger indicated by CTRL_CHAIN_TO. This is -// useful for e.g. an endless ring-buffer DMA with periodic -// interrupts. -// -// When MODE is 0xf, the transfer count does not decrement. The -// DMA channel performs an endless sequence of transfers, never -// triggering other channels or raising interrupts, until an ABORT -// is raised. -// -// All other values are reserved. -// 0x0 -> NORMAL -// 0x1 -> TRIGGER_SELF -// 0xf -> ENDLESS -#define DMA_CH10_TRANS_COUNT_MODE_RESET _u(0x0) -#define DMA_CH10_TRANS_COUNT_MODE_BITS _u(0xf0000000) -#define DMA_CH10_TRANS_COUNT_MODE_MSB _u(31) -#define DMA_CH10_TRANS_COUNT_MODE_LSB _u(28) -#define DMA_CH10_TRANS_COUNT_MODE_ACCESS "RW" -#define DMA_CH10_TRANS_COUNT_MODE_VALUE_NORMAL _u(0x0) -#define DMA_CH10_TRANS_COUNT_MODE_VALUE_TRIGGER_SELF _u(0x1) -#define DMA_CH10_TRANS_COUNT_MODE_VALUE_ENDLESS _u(0xf) -// ----------------------------------------------------------------------------- -// Field : DMA_CH10_TRANS_COUNT_COUNT -// Description : 28-bit transfer count (256 million transfers maximum). -// -// Program the number of bus transfers a channel will perform -// before halting. Note that, if transfers are larger than one -// byte in size, this is not equal to the number of bytes -// transferred (see CTRL_DATA_SIZE). -// -// When the channel is active, reading this register shows the -// number of transfers remaining, updating automatically each time -// a write transfer completes. -// -// Writing this register sets the RELOAD value for the transfer -// counter. Each time this channel is triggered, the RELOAD value -// is copied into the live transfer counter. The channel can be -// started multiple times, and will perform the same number of -// transfers each time, as programmed by most recent write. -// -// The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT -// is used as a trigger, the written value is used immediately as -// the length of the new transfer sequence, as well as being -// written to RELOAD. -#define DMA_CH10_TRANS_COUNT_COUNT_RESET _u(0x0000000) -#define DMA_CH10_TRANS_COUNT_COUNT_BITS _u(0x0fffffff) -#define DMA_CH10_TRANS_COUNT_COUNT_MSB _u(27) -#define DMA_CH10_TRANS_COUNT_COUNT_LSB _u(0) -#define DMA_CH10_TRANS_COUNT_COUNT_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH10_CTRL_TRIG -// Description : DMA Channel 10 Control and Status -#define DMA_CH10_CTRL_TRIG_OFFSET _u(0x0000028c) -#define DMA_CH10_CTRL_TRIG_BITS _u(0xe7ffffff) -#define DMA_CH10_CTRL_TRIG_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : DMA_CH10_CTRL_TRIG_AHB_ERROR -// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel -// halts when it encounters any bus error, and always raises its -// channel IRQ flag. -#define DMA_CH10_CTRL_TRIG_AHB_ERROR_RESET _u(0x0) -#define DMA_CH10_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000) -#define DMA_CH10_CTRL_TRIG_AHB_ERROR_MSB _u(31) -#define DMA_CH10_CTRL_TRIG_AHB_ERROR_LSB _u(31) -#define DMA_CH10_CTRL_TRIG_AHB_ERROR_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : DMA_CH10_CTRL_TRIG_READ_ERROR -// Description : If 1, the channel received a read bus error. Write one to -// clear. -// READ_ADDR shows the approximate address where the bus error was -// encountered (will not be earlier, or more than 3 transfers -// later) -#define DMA_CH10_CTRL_TRIG_READ_ERROR_RESET _u(0x0) -#define DMA_CH10_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000) -#define DMA_CH10_CTRL_TRIG_READ_ERROR_MSB _u(30) -#define DMA_CH10_CTRL_TRIG_READ_ERROR_LSB _u(30) -#define DMA_CH10_CTRL_TRIG_READ_ERROR_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : DMA_CH10_CTRL_TRIG_WRITE_ERROR -// Description : If 1, the channel received a write bus error. Write one to -// clear. -// WRITE_ADDR shows the approximate address where the bus error -// was encountered (will not be earlier, or more than 5 transfers -// later) -#define DMA_CH10_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0) -#define DMA_CH10_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000) -#define DMA_CH10_CTRL_TRIG_WRITE_ERROR_MSB _u(29) -#define DMA_CH10_CTRL_TRIG_WRITE_ERROR_LSB _u(29) -#define DMA_CH10_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : DMA_CH10_CTRL_TRIG_BUSY -// Description : This flag goes high when the channel starts a new transfer -// sequence, and low when the last transfer of that sequence -// completes. Clearing EN while BUSY is high pauses the channel, -// and BUSY will stay high while paused. -// -// To terminate a sequence early (and clear the BUSY flag), see -// CHAN_ABORT. -#define DMA_CH10_CTRL_TRIG_BUSY_RESET _u(0x0) -#define DMA_CH10_CTRL_TRIG_BUSY_BITS _u(0x04000000) -#define DMA_CH10_CTRL_TRIG_BUSY_MSB _u(26) -#define DMA_CH10_CTRL_TRIG_BUSY_LSB _u(26) -#define DMA_CH10_CTRL_TRIG_BUSY_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : DMA_CH10_CTRL_TRIG_SNIFF_EN -// Description : If 1, this channel's data transfers are visible to the sniff -// hardware, and each transfer will advance the state of the -// checksum. This only applies if the sniff hardware is enabled, -// and has this channel selected. -// -// This allows checksum to be enabled or disabled on a per- -// control- block basis. -#define DMA_CH10_CTRL_TRIG_SNIFF_EN_RESET _u(0x0) -#define DMA_CH10_CTRL_TRIG_SNIFF_EN_BITS _u(0x02000000) -#define DMA_CH10_CTRL_TRIG_SNIFF_EN_MSB _u(25) -#define DMA_CH10_CTRL_TRIG_SNIFF_EN_LSB _u(25) -#define DMA_CH10_CTRL_TRIG_SNIFF_EN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH10_CTRL_TRIG_BSWAP -// Description : Apply byte-swap transformation to DMA data. -// For byte data, this has no effect. For halfword data, the two -// bytes of each halfword are swapped. For word data, the four -// bytes of each word are swapped to reverse order. -#define DMA_CH10_CTRL_TRIG_BSWAP_RESET _u(0x0) -#define DMA_CH10_CTRL_TRIG_BSWAP_BITS _u(0x01000000) -#define DMA_CH10_CTRL_TRIG_BSWAP_MSB _u(24) -#define DMA_CH10_CTRL_TRIG_BSWAP_LSB _u(24) -#define DMA_CH10_CTRL_TRIG_BSWAP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH10_CTRL_TRIG_IRQ_QUIET -// Description : In QUIET mode, the channel does not generate IRQs at the end of -// every transfer block. Instead, an IRQ is raised when NULL is -// written to a trigger register, indicating the end of a control -// block chain. -// -// This reduces the number of interrupts to be serviced by the CPU -// when transferring a DMA chain of many small control blocks. -#define DMA_CH10_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0) -#define DMA_CH10_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00800000) -#define DMA_CH10_CTRL_TRIG_IRQ_QUIET_MSB _u(23) -#define DMA_CH10_CTRL_TRIG_IRQ_QUIET_LSB _u(23) -#define DMA_CH10_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH10_CTRL_TRIG_TREQ_SEL -// Description : Select a Transfer Request signal. -// The channel uses the transfer request signal to pace its data -// transfer rate. Sources for TREQ signals are internal (TIMERS) -// or external (DREQ, a Data Request from the system). -// 0x0 to 0x3a -> select DREQ n as TREQ -// 0x3b -> Select Timer 0 as TREQ -// 0x3c -> Select Timer 1 as TREQ -// 0x3d -> Select Timer 2 as TREQ (Optional) -// 0x3e -> Select Timer 3 as TREQ (Optional) -// 0x3f -> Permanent request, for unpaced transfers. -#define DMA_CH10_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) -#define DMA_CH10_CTRL_TRIG_TREQ_SEL_BITS _u(0x007e0000) -#define DMA_CH10_CTRL_TRIG_TREQ_SEL_MSB _u(22) -#define DMA_CH10_CTRL_TRIG_TREQ_SEL_LSB _u(17) -#define DMA_CH10_CTRL_TRIG_TREQ_SEL_ACCESS "RW" -#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) -#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) -#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) -#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) -#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) -// ----------------------------------------------------------------------------- -// Field : DMA_CH10_CTRL_TRIG_CHAIN_TO -// Description : When this channel completes, it will trigger the channel -// indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this -// channel)_. -// -// Note this field resets to 0, so channels 1 and above will chain -// to channel 0 by default. Set this field to avoid this -// behaviour. -#define DMA_CH10_CTRL_TRIG_CHAIN_TO_RESET _u(0x0) -#define DMA_CH10_CTRL_TRIG_CHAIN_TO_BITS _u(0x0001e000) -#define DMA_CH10_CTRL_TRIG_CHAIN_TO_MSB _u(16) -#define DMA_CH10_CTRL_TRIG_CHAIN_TO_LSB _u(13) -#define DMA_CH10_CTRL_TRIG_CHAIN_TO_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH10_CTRL_TRIG_RING_SEL -// Description : Select whether RING_SIZE applies to read or write addresses. -// If 0, read addresses are wrapped on a (1 << RING_SIZE) -// boundary. If 1, write addresses are wrapped. -#define DMA_CH10_CTRL_TRIG_RING_SEL_RESET _u(0x0) -#define DMA_CH10_CTRL_TRIG_RING_SEL_BITS _u(0x00001000) -#define DMA_CH10_CTRL_TRIG_RING_SEL_MSB _u(12) -#define DMA_CH10_CTRL_TRIG_RING_SEL_LSB _u(12) -#define DMA_CH10_CTRL_TRIG_RING_SEL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH10_CTRL_TRIG_RING_SIZE -// Description : Size of address wrap region. If 0, don't wrap. For values n > -// 0, only the lower n bits of the address will change. This wraps -// the address on a (1 << n) byte boundary, facilitating access to -// naturally-aligned ring buffers. -// -// Ring sizes between 2 and 32768 bytes are possible. This can -// apply to either read or write addresses, based on value of -// RING_SEL. -// 0x0 -> RING_NONE -#define DMA_CH10_CTRL_TRIG_RING_SIZE_RESET _u(0x0) -#define DMA_CH10_CTRL_TRIG_RING_SIZE_BITS _u(0x00000f00) -#define DMA_CH10_CTRL_TRIG_RING_SIZE_MSB _u(11) -#define DMA_CH10_CTRL_TRIG_RING_SIZE_LSB _u(8) -#define DMA_CH10_CTRL_TRIG_RING_SIZE_ACCESS "RW" -#define DMA_CH10_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0) -// ----------------------------------------------------------------------------- -// Field : DMA_CH10_CTRL_TRIG_INCR_WRITE_REV -// Description : If 1, and INCR_WRITE is 1, the write address is decremented -// rather than incremented with each transfer. -// -// If 1, and INCR_WRITE is 0, this otherwise-unused combination -// causes the write address to be incremented by twice the -// transfer size, i.e. skipping over alternate addresses. -#define DMA_CH10_CTRL_TRIG_INCR_WRITE_REV_RESET _u(0x0) -#define DMA_CH10_CTRL_TRIG_INCR_WRITE_REV_BITS _u(0x00000080) -#define DMA_CH10_CTRL_TRIG_INCR_WRITE_REV_MSB _u(7) -#define DMA_CH10_CTRL_TRIG_INCR_WRITE_REV_LSB _u(7) -#define DMA_CH10_CTRL_TRIG_INCR_WRITE_REV_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH10_CTRL_TRIG_INCR_WRITE -// Description : If 1, the write address increments with each transfer. If 0, -// each write is directed to the same, initial address. -// -// Generally this should be disabled for memory-to-peripheral -// transfers. -#define DMA_CH10_CTRL_TRIG_INCR_WRITE_RESET _u(0x0) -#define DMA_CH10_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000040) -#define DMA_CH10_CTRL_TRIG_INCR_WRITE_MSB _u(6) -#define DMA_CH10_CTRL_TRIG_INCR_WRITE_LSB _u(6) -#define DMA_CH10_CTRL_TRIG_INCR_WRITE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH10_CTRL_TRIG_INCR_READ_REV -// Description : If 1, and INCR_READ is 1, the read address is decremented -// rather than incremented with each transfer. -// -// If 1, and INCR_READ is 0, this otherwise-unused combination -// causes the read address to be incremented by twice the transfer -// size, i.e. skipping over alternate addresses. -#define DMA_CH10_CTRL_TRIG_INCR_READ_REV_RESET _u(0x0) -#define DMA_CH10_CTRL_TRIG_INCR_READ_REV_BITS _u(0x00000020) -#define DMA_CH10_CTRL_TRIG_INCR_READ_REV_MSB _u(5) -#define DMA_CH10_CTRL_TRIG_INCR_READ_REV_LSB _u(5) -#define DMA_CH10_CTRL_TRIG_INCR_READ_REV_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH10_CTRL_TRIG_INCR_READ -// Description : If 1, the read address increments with each transfer. If 0, -// each read is directed to the same, initial address. -// -// Generally this should be disabled for peripheral-to-memory -// transfers. -#define DMA_CH10_CTRL_TRIG_INCR_READ_RESET _u(0x0) -#define DMA_CH10_CTRL_TRIG_INCR_READ_BITS _u(0x00000010) -#define DMA_CH10_CTRL_TRIG_INCR_READ_MSB _u(4) -#define DMA_CH10_CTRL_TRIG_INCR_READ_LSB _u(4) -#define DMA_CH10_CTRL_TRIG_INCR_READ_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH10_CTRL_TRIG_DATA_SIZE -// Description : Set the size of each bus transfer (byte/halfword/word). -// READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) -// with each transfer. -// 0x0 -> SIZE_BYTE -// 0x1 -> SIZE_HALFWORD -// 0x2 -> SIZE_WORD -#define DMA_CH10_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) -#define DMA_CH10_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) -#define DMA_CH10_CTRL_TRIG_DATA_SIZE_MSB _u(3) -#define DMA_CH10_CTRL_TRIG_DATA_SIZE_LSB _u(2) -#define DMA_CH10_CTRL_TRIG_DATA_SIZE_ACCESS "RW" -#define DMA_CH10_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) -#define DMA_CH10_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1) -#define DMA_CH10_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) -// ----------------------------------------------------------------------------- -// Field : DMA_CH10_CTRL_TRIG_HIGH_PRIORITY -// Description : HIGH_PRIORITY gives a channel preferential treatment in issue -// scheduling: in each scheduling round, all high priority -// channels are considered first, and then only a single low -// priority channel, before returning to the high priority -// channels. -// -// This only affects the order in which the DMA schedules -// channels. The DMA's bus priority is not changed. If the DMA is -// not saturated then a low priority channel will see no loss of -// throughput. -#define DMA_CH10_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0) -#define DMA_CH10_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002) -#define DMA_CH10_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1) -#define DMA_CH10_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1) -#define DMA_CH10_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH10_CTRL_TRIG_EN -// Description : DMA Channel Enable. -// When 1, the channel will respond to triggering events, which -// will cause it to become BUSY and start transferring data. When -// 0, the channel will ignore triggers, stop issuing transfers, -// and pause the current transfer sequence (i.e. BUSY will remain -// high if already high) -#define DMA_CH10_CTRL_TRIG_EN_RESET _u(0x0) -#define DMA_CH10_CTRL_TRIG_EN_BITS _u(0x00000001) -#define DMA_CH10_CTRL_TRIG_EN_MSB _u(0) -#define DMA_CH10_CTRL_TRIG_EN_LSB _u(0) -#define DMA_CH10_CTRL_TRIG_EN_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH10_AL1_CTRL -// Description : Alias for channel 10 CTRL register -#define DMA_CH10_AL1_CTRL_OFFSET _u(0x00000290) -#define DMA_CH10_AL1_CTRL_BITS _u(0xffffffff) -#define DMA_CH10_AL1_CTRL_RESET "-" -#define DMA_CH10_AL1_CTRL_MSB _u(31) -#define DMA_CH10_AL1_CTRL_LSB _u(0) -#define DMA_CH10_AL1_CTRL_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH10_AL1_READ_ADDR -// Description : Alias for channel 10 READ_ADDR register -#define DMA_CH10_AL1_READ_ADDR_OFFSET _u(0x00000294) -#define DMA_CH10_AL1_READ_ADDR_BITS _u(0xffffffff) -#define DMA_CH10_AL1_READ_ADDR_RESET "-" -#define DMA_CH10_AL1_READ_ADDR_MSB _u(31) -#define DMA_CH10_AL1_READ_ADDR_LSB _u(0) -#define DMA_CH10_AL1_READ_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH10_AL1_WRITE_ADDR -// Description : Alias for channel 10 WRITE_ADDR register -#define DMA_CH10_AL1_WRITE_ADDR_OFFSET _u(0x00000298) -#define DMA_CH10_AL1_WRITE_ADDR_BITS _u(0xffffffff) -#define DMA_CH10_AL1_WRITE_ADDR_RESET "-" -#define DMA_CH10_AL1_WRITE_ADDR_MSB _u(31) -#define DMA_CH10_AL1_WRITE_ADDR_LSB _u(0) -#define DMA_CH10_AL1_WRITE_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH10_AL1_TRANS_COUNT_TRIG -// Description : Alias for channel 10 TRANS_COUNT register -// This is a trigger register (0xc). Writing a nonzero value will -// reload the channel counter and start the channel. -#define DMA_CH10_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x0000029c) -#define DMA_CH10_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff) -#define DMA_CH10_AL1_TRANS_COUNT_TRIG_RESET "-" -#define DMA_CH10_AL1_TRANS_COUNT_TRIG_MSB _u(31) -#define DMA_CH10_AL1_TRANS_COUNT_TRIG_LSB _u(0) -#define DMA_CH10_AL1_TRANS_COUNT_TRIG_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH10_AL2_CTRL -// Description : Alias for channel 10 CTRL register -#define DMA_CH10_AL2_CTRL_OFFSET _u(0x000002a0) -#define DMA_CH10_AL2_CTRL_BITS _u(0xffffffff) -#define DMA_CH10_AL2_CTRL_RESET "-" -#define DMA_CH10_AL2_CTRL_MSB _u(31) -#define DMA_CH10_AL2_CTRL_LSB _u(0) -#define DMA_CH10_AL2_CTRL_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH10_AL2_TRANS_COUNT -// Description : Alias for channel 10 TRANS_COUNT register -#define DMA_CH10_AL2_TRANS_COUNT_OFFSET _u(0x000002a4) -#define DMA_CH10_AL2_TRANS_COUNT_BITS _u(0xffffffff) -#define DMA_CH10_AL2_TRANS_COUNT_RESET "-" -#define DMA_CH10_AL2_TRANS_COUNT_MSB _u(31) -#define DMA_CH10_AL2_TRANS_COUNT_LSB _u(0) -#define DMA_CH10_AL2_TRANS_COUNT_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH10_AL2_READ_ADDR -// Description : Alias for channel 10 READ_ADDR register -#define DMA_CH10_AL2_READ_ADDR_OFFSET _u(0x000002a8) -#define DMA_CH10_AL2_READ_ADDR_BITS _u(0xffffffff) -#define DMA_CH10_AL2_READ_ADDR_RESET "-" -#define DMA_CH10_AL2_READ_ADDR_MSB _u(31) -#define DMA_CH10_AL2_READ_ADDR_LSB _u(0) -#define DMA_CH10_AL2_READ_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH10_AL2_WRITE_ADDR_TRIG -// Description : Alias for channel 10 WRITE_ADDR register -// This is a trigger register (0xc). Writing a nonzero value will -// reload the channel counter and start the channel. -#define DMA_CH10_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x000002ac) -#define DMA_CH10_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff) -#define DMA_CH10_AL2_WRITE_ADDR_TRIG_RESET "-" -#define DMA_CH10_AL2_WRITE_ADDR_TRIG_MSB _u(31) -#define DMA_CH10_AL2_WRITE_ADDR_TRIG_LSB _u(0) -#define DMA_CH10_AL2_WRITE_ADDR_TRIG_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH10_AL3_CTRL -// Description : Alias for channel 10 CTRL register -#define DMA_CH10_AL3_CTRL_OFFSET _u(0x000002b0) -#define DMA_CH10_AL3_CTRL_BITS _u(0xffffffff) -#define DMA_CH10_AL3_CTRL_RESET "-" -#define DMA_CH10_AL3_CTRL_MSB _u(31) -#define DMA_CH10_AL3_CTRL_LSB _u(0) -#define DMA_CH10_AL3_CTRL_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH10_AL3_WRITE_ADDR -// Description : Alias for channel 10 WRITE_ADDR register -#define DMA_CH10_AL3_WRITE_ADDR_OFFSET _u(0x000002b4) -#define DMA_CH10_AL3_WRITE_ADDR_BITS _u(0xffffffff) -#define DMA_CH10_AL3_WRITE_ADDR_RESET "-" -#define DMA_CH10_AL3_WRITE_ADDR_MSB _u(31) -#define DMA_CH10_AL3_WRITE_ADDR_LSB _u(0) -#define DMA_CH10_AL3_WRITE_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH10_AL3_TRANS_COUNT -// Description : Alias for channel 10 TRANS_COUNT register -#define DMA_CH10_AL3_TRANS_COUNT_OFFSET _u(0x000002b8) -#define DMA_CH10_AL3_TRANS_COUNT_BITS _u(0xffffffff) -#define DMA_CH10_AL3_TRANS_COUNT_RESET "-" -#define DMA_CH10_AL3_TRANS_COUNT_MSB _u(31) -#define DMA_CH10_AL3_TRANS_COUNT_LSB _u(0) -#define DMA_CH10_AL3_TRANS_COUNT_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH10_AL3_READ_ADDR_TRIG -// Description : Alias for channel 10 READ_ADDR register -// This is a trigger register (0xc). Writing a nonzero value will -// reload the channel counter and start the channel. -#define DMA_CH10_AL3_READ_ADDR_TRIG_OFFSET _u(0x000002bc) -#define DMA_CH10_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff) -#define DMA_CH10_AL3_READ_ADDR_TRIG_RESET "-" -#define DMA_CH10_AL3_READ_ADDR_TRIG_MSB _u(31) -#define DMA_CH10_AL3_READ_ADDR_TRIG_LSB _u(0) -#define DMA_CH10_AL3_READ_ADDR_TRIG_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH11_READ_ADDR -// Description : DMA Channel 11 Read Address pointer -// This register updates automatically each time a read completes. -// The current value is the next address to be read by this -// channel. -#define DMA_CH11_READ_ADDR_OFFSET _u(0x000002c0) -#define DMA_CH11_READ_ADDR_BITS _u(0xffffffff) -#define DMA_CH11_READ_ADDR_RESET _u(0x00000000) -#define DMA_CH11_READ_ADDR_MSB _u(31) -#define DMA_CH11_READ_ADDR_LSB _u(0) -#define DMA_CH11_READ_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH11_WRITE_ADDR -// Description : DMA Channel 11 Write Address pointer -// This register updates automatically each time a write -// completes. The current value is the next address to be written -// by this channel. -#define DMA_CH11_WRITE_ADDR_OFFSET _u(0x000002c4) -#define DMA_CH11_WRITE_ADDR_BITS _u(0xffffffff) -#define DMA_CH11_WRITE_ADDR_RESET _u(0x00000000) -#define DMA_CH11_WRITE_ADDR_MSB _u(31) -#define DMA_CH11_WRITE_ADDR_LSB _u(0) -#define DMA_CH11_WRITE_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH11_TRANS_COUNT -// Description : DMA Channel 11 Transfer Count -#define DMA_CH11_TRANS_COUNT_OFFSET _u(0x000002c8) -#define DMA_CH11_TRANS_COUNT_BITS _u(0xffffffff) -#define DMA_CH11_TRANS_COUNT_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : DMA_CH11_TRANS_COUNT_MODE -// Description : When MODE is 0x0, the transfer count decrements with each -// transfer until 0, and then the channel triggers the next -// channel indicated by CTRL_CHAIN_TO. -// -// When MODE is 0x1, the transfer count decrements with each -// transfer until 0, and then the channel re-triggers itself, in -// addition to the trigger indicated by CTRL_CHAIN_TO. This is -// useful for e.g. an endless ring-buffer DMA with periodic -// interrupts. -// -// When MODE is 0xf, the transfer count does not decrement. The -// DMA channel performs an endless sequence of transfers, never -// triggering other channels or raising interrupts, until an ABORT -// is raised. -// -// All other values are reserved. -// 0x0 -> NORMAL -// 0x1 -> TRIGGER_SELF -// 0xf -> ENDLESS -#define DMA_CH11_TRANS_COUNT_MODE_RESET _u(0x0) -#define DMA_CH11_TRANS_COUNT_MODE_BITS _u(0xf0000000) -#define DMA_CH11_TRANS_COUNT_MODE_MSB _u(31) -#define DMA_CH11_TRANS_COUNT_MODE_LSB _u(28) -#define DMA_CH11_TRANS_COUNT_MODE_ACCESS "RW" -#define DMA_CH11_TRANS_COUNT_MODE_VALUE_NORMAL _u(0x0) -#define DMA_CH11_TRANS_COUNT_MODE_VALUE_TRIGGER_SELF _u(0x1) -#define DMA_CH11_TRANS_COUNT_MODE_VALUE_ENDLESS _u(0xf) -// ----------------------------------------------------------------------------- -// Field : DMA_CH11_TRANS_COUNT_COUNT -// Description : 28-bit transfer count (256 million transfers maximum). -// -// Program the number of bus transfers a channel will perform -// before halting. Note that, if transfers are larger than one -// byte in size, this is not equal to the number of bytes -// transferred (see CTRL_DATA_SIZE). -// -// When the channel is active, reading this register shows the -// number of transfers remaining, updating automatically each time -// a write transfer completes. -// -// Writing this register sets the RELOAD value for the transfer -// counter. Each time this channel is triggered, the RELOAD value -// is copied into the live transfer counter. The channel can be -// started multiple times, and will perform the same number of -// transfers each time, as programmed by most recent write. -// -// The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT -// is used as a trigger, the written value is used immediately as -// the length of the new transfer sequence, as well as being -// written to RELOAD. -#define DMA_CH11_TRANS_COUNT_COUNT_RESET _u(0x0000000) -#define DMA_CH11_TRANS_COUNT_COUNT_BITS _u(0x0fffffff) -#define DMA_CH11_TRANS_COUNT_COUNT_MSB _u(27) -#define DMA_CH11_TRANS_COUNT_COUNT_LSB _u(0) -#define DMA_CH11_TRANS_COUNT_COUNT_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH11_CTRL_TRIG -// Description : DMA Channel 11 Control and Status -#define DMA_CH11_CTRL_TRIG_OFFSET _u(0x000002cc) -#define DMA_CH11_CTRL_TRIG_BITS _u(0xe7ffffff) -#define DMA_CH11_CTRL_TRIG_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : DMA_CH11_CTRL_TRIG_AHB_ERROR -// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel -// halts when it encounters any bus error, and always raises its -// channel IRQ flag. -#define DMA_CH11_CTRL_TRIG_AHB_ERROR_RESET _u(0x0) -#define DMA_CH11_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000) -#define DMA_CH11_CTRL_TRIG_AHB_ERROR_MSB _u(31) -#define DMA_CH11_CTRL_TRIG_AHB_ERROR_LSB _u(31) -#define DMA_CH11_CTRL_TRIG_AHB_ERROR_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : DMA_CH11_CTRL_TRIG_READ_ERROR -// Description : If 1, the channel received a read bus error. Write one to -// clear. -// READ_ADDR shows the approximate address where the bus error was -// encountered (will not be earlier, or more than 3 transfers -// later) -#define DMA_CH11_CTRL_TRIG_READ_ERROR_RESET _u(0x0) -#define DMA_CH11_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000) -#define DMA_CH11_CTRL_TRIG_READ_ERROR_MSB _u(30) -#define DMA_CH11_CTRL_TRIG_READ_ERROR_LSB _u(30) -#define DMA_CH11_CTRL_TRIG_READ_ERROR_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : DMA_CH11_CTRL_TRIG_WRITE_ERROR -// Description : If 1, the channel received a write bus error. Write one to -// clear. -// WRITE_ADDR shows the approximate address where the bus error -// was encountered (will not be earlier, or more than 5 transfers -// later) -#define DMA_CH11_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0) -#define DMA_CH11_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000) -#define DMA_CH11_CTRL_TRIG_WRITE_ERROR_MSB _u(29) -#define DMA_CH11_CTRL_TRIG_WRITE_ERROR_LSB _u(29) -#define DMA_CH11_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : DMA_CH11_CTRL_TRIG_BUSY -// Description : This flag goes high when the channel starts a new transfer -// sequence, and low when the last transfer of that sequence -// completes. Clearing EN while BUSY is high pauses the channel, -// and BUSY will stay high while paused. -// -// To terminate a sequence early (and clear the BUSY flag), see -// CHAN_ABORT. -#define DMA_CH11_CTRL_TRIG_BUSY_RESET _u(0x0) -#define DMA_CH11_CTRL_TRIG_BUSY_BITS _u(0x04000000) -#define DMA_CH11_CTRL_TRIG_BUSY_MSB _u(26) -#define DMA_CH11_CTRL_TRIG_BUSY_LSB _u(26) -#define DMA_CH11_CTRL_TRIG_BUSY_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : DMA_CH11_CTRL_TRIG_SNIFF_EN -// Description : If 1, this channel's data transfers are visible to the sniff -// hardware, and each transfer will advance the state of the -// checksum. This only applies if the sniff hardware is enabled, -// and has this channel selected. -// -// This allows checksum to be enabled or disabled on a per- -// control- block basis. -#define DMA_CH11_CTRL_TRIG_SNIFF_EN_RESET _u(0x0) -#define DMA_CH11_CTRL_TRIG_SNIFF_EN_BITS _u(0x02000000) -#define DMA_CH11_CTRL_TRIG_SNIFF_EN_MSB _u(25) -#define DMA_CH11_CTRL_TRIG_SNIFF_EN_LSB _u(25) -#define DMA_CH11_CTRL_TRIG_SNIFF_EN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH11_CTRL_TRIG_BSWAP -// Description : Apply byte-swap transformation to DMA data. -// For byte data, this has no effect. For halfword data, the two -// bytes of each halfword are swapped. For word data, the four -// bytes of each word are swapped to reverse order. -#define DMA_CH11_CTRL_TRIG_BSWAP_RESET _u(0x0) -#define DMA_CH11_CTRL_TRIG_BSWAP_BITS _u(0x01000000) -#define DMA_CH11_CTRL_TRIG_BSWAP_MSB _u(24) -#define DMA_CH11_CTRL_TRIG_BSWAP_LSB _u(24) -#define DMA_CH11_CTRL_TRIG_BSWAP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH11_CTRL_TRIG_IRQ_QUIET -// Description : In QUIET mode, the channel does not generate IRQs at the end of -// every transfer block. Instead, an IRQ is raised when NULL is -// written to a trigger register, indicating the end of a control -// block chain. -// -// This reduces the number of interrupts to be serviced by the CPU -// when transferring a DMA chain of many small control blocks. -#define DMA_CH11_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0) -#define DMA_CH11_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00800000) -#define DMA_CH11_CTRL_TRIG_IRQ_QUIET_MSB _u(23) -#define DMA_CH11_CTRL_TRIG_IRQ_QUIET_LSB _u(23) -#define DMA_CH11_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH11_CTRL_TRIG_TREQ_SEL -// Description : Select a Transfer Request signal. -// The channel uses the transfer request signal to pace its data -// transfer rate. Sources for TREQ signals are internal (TIMERS) -// or external (DREQ, a Data Request from the system). -// 0x0 to 0x3a -> select DREQ n as TREQ -// 0x3b -> Select Timer 0 as TREQ -// 0x3c -> Select Timer 1 as TREQ -// 0x3d -> Select Timer 2 as TREQ (Optional) -// 0x3e -> Select Timer 3 as TREQ (Optional) -// 0x3f -> Permanent request, for unpaced transfers. -#define DMA_CH11_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) -#define DMA_CH11_CTRL_TRIG_TREQ_SEL_BITS _u(0x007e0000) -#define DMA_CH11_CTRL_TRIG_TREQ_SEL_MSB _u(22) -#define DMA_CH11_CTRL_TRIG_TREQ_SEL_LSB _u(17) -#define DMA_CH11_CTRL_TRIG_TREQ_SEL_ACCESS "RW" -#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) -#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) -#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) -#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) -#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) -// ----------------------------------------------------------------------------- -// Field : DMA_CH11_CTRL_TRIG_CHAIN_TO -// Description : When this channel completes, it will trigger the channel -// indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this -// channel)_. -// -// Note this field resets to 0, so channels 1 and above will chain -// to channel 0 by default. Set this field to avoid this -// behaviour. -#define DMA_CH11_CTRL_TRIG_CHAIN_TO_RESET _u(0x0) -#define DMA_CH11_CTRL_TRIG_CHAIN_TO_BITS _u(0x0001e000) -#define DMA_CH11_CTRL_TRIG_CHAIN_TO_MSB _u(16) -#define DMA_CH11_CTRL_TRIG_CHAIN_TO_LSB _u(13) -#define DMA_CH11_CTRL_TRIG_CHAIN_TO_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH11_CTRL_TRIG_RING_SEL -// Description : Select whether RING_SIZE applies to read or write addresses. -// If 0, read addresses are wrapped on a (1 << RING_SIZE) -// boundary. If 1, write addresses are wrapped. -#define DMA_CH11_CTRL_TRIG_RING_SEL_RESET _u(0x0) -#define DMA_CH11_CTRL_TRIG_RING_SEL_BITS _u(0x00001000) -#define DMA_CH11_CTRL_TRIG_RING_SEL_MSB _u(12) -#define DMA_CH11_CTRL_TRIG_RING_SEL_LSB _u(12) -#define DMA_CH11_CTRL_TRIG_RING_SEL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH11_CTRL_TRIG_RING_SIZE -// Description : Size of address wrap region. If 0, don't wrap. For values n > -// 0, only the lower n bits of the address will change. This wraps -// the address on a (1 << n) byte boundary, facilitating access to -// naturally-aligned ring buffers. -// -// Ring sizes between 2 and 32768 bytes are possible. This can -// apply to either read or write addresses, based on value of -// RING_SEL. -// 0x0 -> RING_NONE -#define DMA_CH11_CTRL_TRIG_RING_SIZE_RESET _u(0x0) -#define DMA_CH11_CTRL_TRIG_RING_SIZE_BITS _u(0x00000f00) -#define DMA_CH11_CTRL_TRIG_RING_SIZE_MSB _u(11) -#define DMA_CH11_CTRL_TRIG_RING_SIZE_LSB _u(8) -#define DMA_CH11_CTRL_TRIG_RING_SIZE_ACCESS "RW" -#define DMA_CH11_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0) -// ----------------------------------------------------------------------------- -// Field : DMA_CH11_CTRL_TRIG_INCR_WRITE_REV -// Description : If 1, and INCR_WRITE is 1, the write address is decremented -// rather than incremented with each transfer. -// -// If 1, and INCR_WRITE is 0, this otherwise-unused combination -// causes the write address to be incremented by twice the -// transfer size, i.e. skipping over alternate addresses. -#define DMA_CH11_CTRL_TRIG_INCR_WRITE_REV_RESET _u(0x0) -#define DMA_CH11_CTRL_TRIG_INCR_WRITE_REV_BITS _u(0x00000080) -#define DMA_CH11_CTRL_TRIG_INCR_WRITE_REV_MSB _u(7) -#define DMA_CH11_CTRL_TRIG_INCR_WRITE_REV_LSB _u(7) -#define DMA_CH11_CTRL_TRIG_INCR_WRITE_REV_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH11_CTRL_TRIG_INCR_WRITE -// Description : If 1, the write address increments with each transfer. If 0, -// each write is directed to the same, initial address. -// -// Generally this should be disabled for memory-to-peripheral -// transfers. -#define DMA_CH11_CTRL_TRIG_INCR_WRITE_RESET _u(0x0) -#define DMA_CH11_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000040) -#define DMA_CH11_CTRL_TRIG_INCR_WRITE_MSB _u(6) -#define DMA_CH11_CTRL_TRIG_INCR_WRITE_LSB _u(6) -#define DMA_CH11_CTRL_TRIG_INCR_WRITE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH11_CTRL_TRIG_INCR_READ_REV -// Description : If 1, and INCR_READ is 1, the read address is decremented -// rather than incremented with each transfer. -// -// If 1, and INCR_READ is 0, this otherwise-unused combination -// causes the read address to be incremented by twice the transfer -// size, i.e. skipping over alternate addresses. -#define DMA_CH11_CTRL_TRIG_INCR_READ_REV_RESET _u(0x0) -#define DMA_CH11_CTRL_TRIG_INCR_READ_REV_BITS _u(0x00000020) -#define DMA_CH11_CTRL_TRIG_INCR_READ_REV_MSB _u(5) -#define DMA_CH11_CTRL_TRIG_INCR_READ_REV_LSB _u(5) -#define DMA_CH11_CTRL_TRIG_INCR_READ_REV_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH11_CTRL_TRIG_INCR_READ -// Description : If 1, the read address increments with each transfer. If 0, -// each read is directed to the same, initial address. -// -// Generally this should be disabled for peripheral-to-memory -// transfers. -#define DMA_CH11_CTRL_TRIG_INCR_READ_RESET _u(0x0) -#define DMA_CH11_CTRL_TRIG_INCR_READ_BITS _u(0x00000010) -#define DMA_CH11_CTRL_TRIG_INCR_READ_MSB _u(4) -#define DMA_CH11_CTRL_TRIG_INCR_READ_LSB _u(4) -#define DMA_CH11_CTRL_TRIG_INCR_READ_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH11_CTRL_TRIG_DATA_SIZE -// Description : Set the size of each bus transfer (byte/halfword/word). -// READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) -// with each transfer. -// 0x0 -> SIZE_BYTE -// 0x1 -> SIZE_HALFWORD -// 0x2 -> SIZE_WORD -#define DMA_CH11_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) -#define DMA_CH11_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) -#define DMA_CH11_CTRL_TRIG_DATA_SIZE_MSB _u(3) -#define DMA_CH11_CTRL_TRIG_DATA_SIZE_LSB _u(2) -#define DMA_CH11_CTRL_TRIG_DATA_SIZE_ACCESS "RW" -#define DMA_CH11_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) -#define DMA_CH11_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1) -#define DMA_CH11_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) -// ----------------------------------------------------------------------------- -// Field : DMA_CH11_CTRL_TRIG_HIGH_PRIORITY -// Description : HIGH_PRIORITY gives a channel preferential treatment in issue -// scheduling: in each scheduling round, all high priority -// channels are considered first, and then only a single low -// priority channel, before returning to the high priority -// channels. -// -// This only affects the order in which the DMA schedules -// channels. The DMA's bus priority is not changed. If the DMA is -// not saturated then a low priority channel will see no loss of -// throughput. -#define DMA_CH11_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0) -#define DMA_CH11_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002) -#define DMA_CH11_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1) -#define DMA_CH11_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1) -#define DMA_CH11_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH11_CTRL_TRIG_EN -// Description : DMA Channel Enable. -// When 1, the channel will respond to triggering events, which -// will cause it to become BUSY and start transferring data. When -// 0, the channel will ignore triggers, stop issuing transfers, -// and pause the current transfer sequence (i.e. BUSY will remain -// high if already high) -#define DMA_CH11_CTRL_TRIG_EN_RESET _u(0x0) -#define DMA_CH11_CTRL_TRIG_EN_BITS _u(0x00000001) -#define DMA_CH11_CTRL_TRIG_EN_MSB _u(0) -#define DMA_CH11_CTRL_TRIG_EN_LSB _u(0) -#define DMA_CH11_CTRL_TRIG_EN_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH11_AL1_CTRL -// Description : Alias for channel 11 CTRL register -#define DMA_CH11_AL1_CTRL_OFFSET _u(0x000002d0) -#define DMA_CH11_AL1_CTRL_BITS _u(0xffffffff) -#define DMA_CH11_AL1_CTRL_RESET "-" -#define DMA_CH11_AL1_CTRL_MSB _u(31) -#define DMA_CH11_AL1_CTRL_LSB _u(0) -#define DMA_CH11_AL1_CTRL_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH11_AL1_READ_ADDR -// Description : Alias for channel 11 READ_ADDR register -#define DMA_CH11_AL1_READ_ADDR_OFFSET _u(0x000002d4) -#define DMA_CH11_AL1_READ_ADDR_BITS _u(0xffffffff) -#define DMA_CH11_AL1_READ_ADDR_RESET "-" -#define DMA_CH11_AL1_READ_ADDR_MSB _u(31) -#define DMA_CH11_AL1_READ_ADDR_LSB _u(0) -#define DMA_CH11_AL1_READ_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH11_AL1_WRITE_ADDR -// Description : Alias for channel 11 WRITE_ADDR register -#define DMA_CH11_AL1_WRITE_ADDR_OFFSET _u(0x000002d8) -#define DMA_CH11_AL1_WRITE_ADDR_BITS _u(0xffffffff) -#define DMA_CH11_AL1_WRITE_ADDR_RESET "-" -#define DMA_CH11_AL1_WRITE_ADDR_MSB _u(31) -#define DMA_CH11_AL1_WRITE_ADDR_LSB _u(0) -#define DMA_CH11_AL1_WRITE_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH11_AL1_TRANS_COUNT_TRIG -// Description : Alias for channel 11 TRANS_COUNT register -// This is a trigger register (0xc). Writing a nonzero value will -// reload the channel counter and start the channel. -#define DMA_CH11_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x000002dc) -#define DMA_CH11_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff) -#define DMA_CH11_AL1_TRANS_COUNT_TRIG_RESET "-" -#define DMA_CH11_AL1_TRANS_COUNT_TRIG_MSB _u(31) -#define DMA_CH11_AL1_TRANS_COUNT_TRIG_LSB _u(0) -#define DMA_CH11_AL1_TRANS_COUNT_TRIG_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH11_AL2_CTRL -// Description : Alias for channel 11 CTRL register -#define DMA_CH11_AL2_CTRL_OFFSET _u(0x000002e0) -#define DMA_CH11_AL2_CTRL_BITS _u(0xffffffff) -#define DMA_CH11_AL2_CTRL_RESET "-" -#define DMA_CH11_AL2_CTRL_MSB _u(31) -#define DMA_CH11_AL2_CTRL_LSB _u(0) -#define DMA_CH11_AL2_CTRL_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH11_AL2_TRANS_COUNT -// Description : Alias for channel 11 TRANS_COUNT register -#define DMA_CH11_AL2_TRANS_COUNT_OFFSET _u(0x000002e4) -#define DMA_CH11_AL2_TRANS_COUNT_BITS _u(0xffffffff) -#define DMA_CH11_AL2_TRANS_COUNT_RESET "-" -#define DMA_CH11_AL2_TRANS_COUNT_MSB _u(31) -#define DMA_CH11_AL2_TRANS_COUNT_LSB _u(0) -#define DMA_CH11_AL2_TRANS_COUNT_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH11_AL2_READ_ADDR -// Description : Alias for channel 11 READ_ADDR register -#define DMA_CH11_AL2_READ_ADDR_OFFSET _u(0x000002e8) -#define DMA_CH11_AL2_READ_ADDR_BITS _u(0xffffffff) -#define DMA_CH11_AL2_READ_ADDR_RESET "-" -#define DMA_CH11_AL2_READ_ADDR_MSB _u(31) -#define DMA_CH11_AL2_READ_ADDR_LSB _u(0) -#define DMA_CH11_AL2_READ_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH11_AL2_WRITE_ADDR_TRIG -// Description : Alias for channel 11 WRITE_ADDR register -// This is a trigger register (0xc). Writing a nonzero value will -// reload the channel counter and start the channel. -#define DMA_CH11_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x000002ec) -#define DMA_CH11_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff) -#define DMA_CH11_AL2_WRITE_ADDR_TRIG_RESET "-" -#define DMA_CH11_AL2_WRITE_ADDR_TRIG_MSB _u(31) -#define DMA_CH11_AL2_WRITE_ADDR_TRIG_LSB _u(0) -#define DMA_CH11_AL2_WRITE_ADDR_TRIG_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH11_AL3_CTRL -// Description : Alias for channel 11 CTRL register -#define DMA_CH11_AL3_CTRL_OFFSET _u(0x000002f0) -#define DMA_CH11_AL3_CTRL_BITS _u(0xffffffff) -#define DMA_CH11_AL3_CTRL_RESET "-" -#define DMA_CH11_AL3_CTRL_MSB _u(31) -#define DMA_CH11_AL3_CTRL_LSB _u(0) -#define DMA_CH11_AL3_CTRL_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH11_AL3_WRITE_ADDR -// Description : Alias for channel 11 WRITE_ADDR register -#define DMA_CH11_AL3_WRITE_ADDR_OFFSET _u(0x000002f4) -#define DMA_CH11_AL3_WRITE_ADDR_BITS _u(0xffffffff) -#define DMA_CH11_AL3_WRITE_ADDR_RESET "-" -#define DMA_CH11_AL3_WRITE_ADDR_MSB _u(31) -#define DMA_CH11_AL3_WRITE_ADDR_LSB _u(0) -#define DMA_CH11_AL3_WRITE_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH11_AL3_TRANS_COUNT -// Description : Alias for channel 11 TRANS_COUNT register -#define DMA_CH11_AL3_TRANS_COUNT_OFFSET _u(0x000002f8) -#define DMA_CH11_AL3_TRANS_COUNT_BITS _u(0xffffffff) -#define DMA_CH11_AL3_TRANS_COUNT_RESET "-" -#define DMA_CH11_AL3_TRANS_COUNT_MSB _u(31) -#define DMA_CH11_AL3_TRANS_COUNT_LSB _u(0) -#define DMA_CH11_AL3_TRANS_COUNT_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH11_AL3_READ_ADDR_TRIG -// Description : Alias for channel 11 READ_ADDR register -// This is a trigger register (0xc). Writing a nonzero value will -// reload the channel counter and start the channel. -#define DMA_CH11_AL3_READ_ADDR_TRIG_OFFSET _u(0x000002fc) -#define DMA_CH11_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff) -#define DMA_CH11_AL3_READ_ADDR_TRIG_RESET "-" -#define DMA_CH11_AL3_READ_ADDR_TRIG_MSB _u(31) -#define DMA_CH11_AL3_READ_ADDR_TRIG_LSB _u(0) -#define DMA_CH11_AL3_READ_ADDR_TRIG_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH12_READ_ADDR -// Description : DMA Channel 12 Read Address pointer -// This register updates automatically each time a read completes. -// The current value is the next address to be read by this -// channel. -#define DMA_CH12_READ_ADDR_OFFSET _u(0x00000300) -#define DMA_CH12_READ_ADDR_BITS _u(0xffffffff) -#define DMA_CH12_READ_ADDR_RESET _u(0x00000000) -#define DMA_CH12_READ_ADDR_MSB _u(31) -#define DMA_CH12_READ_ADDR_LSB _u(0) -#define DMA_CH12_READ_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH12_WRITE_ADDR -// Description : DMA Channel 12 Write Address pointer -// This register updates automatically each time a write -// completes. The current value is the next address to be written -// by this channel. -#define DMA_CH12_WRITE_ADDR_OFFSET _u(0x00000304) -#define DMA_CH12_WRITE_ADDR_BITS _u(0xffffffff) -#define DMA_CH12_WRITE_ADDR_RESET _u(0x00000000) -#define DMA_CH12_WRITE_ADDR_MSB _u(31) -#define DMA_CH12_WRITE_ADDR_LSB _u(0) -#define DMA_CH12_WRITE_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH12_TRANS_COUNT -// Description : DMA Channel 12 Transfer Count -#define DMA_CH12_TRANS_COUNT_OFFSET _u(0x00000308) -#define DMA_CH12_TRANS_COUNT_BITS _u(0xffffffff) -#define DMA_CH12_TRANS_COUNT_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : DMA_CH12_TRANS_COUNT_MODE -// Description : When MODE is 0x0, the transfer count decrements with each -// transfer until 0, and then the channel triggers the next -// channel indicated by CTRL_CHAIN_TO. -// -// When MODE is 0x1, the transfer count decrements with each -// transfer until 0, and then the channel re-triggers itself, in -// addition to the trigger indicated by CTRL_CHAIN_TO. This is -// useful for e.g. an endless ring-buffer DMA with periodic -// interrupts. -// -// When MODE is 0xf, the transfer count does not decrement. The -// DMA channel performs an endless sequence of transfers, never -// triggering other channels or raising interrupts, until an ABORT -// is raised. -// -// All other values are reserved. -// 0x0 -> NORMAL -// 0x1 -> TRIGGER_SELF -// 0xf -> ENDLESS -#define DMA_CH12_TRANS_COUNT_MODE_RESET _u(0x0) -#define DMA_CH12_TRANS_COUNT_MODE_BITS _u(0xf0000000) -#define DMA_CH12_TRANS_COUNT_MODE_MSB _u(31) -#define DMA_CH12_TRANS_COUNT_MODE_LSB _u(28) -#define DMA_CH12_TRANS_COUNT_MODE_ACCESS "RW" -#define DMA_CH12_TRANS_COUNT_MODE_VALUE_NORMAL _u(0x0) -#define DMA_CH12_TRANS_COUNT_MODE_VALUE_TRIGGER_SELF _u(0x1) -#define DMA_CH12_TRANS_COUNT_MODE_VALUE_ENDLESS _u(0xf) -// ----------------------------------------------------------------------------- -// Field : DMA_CH12_TRANS_COUNT_COUNT -// Description : 28-bit transfer count (256 million transfers maximum). -// -// Program the number of bus transfers a channel will perform -// before halting. Note that, if transfers are larger than one -// byte in size, this is not equal to the number of bytes -// transferred (see CTRL_DATA_SIZE). -// -// When the channel is active, reading this register shows the -// number of transfers remaining, updating automatically each time -// a write transfer completes. -// -// Writing this register sets the RELOAD value for the transfer -// counter. Each time this channel is triggered, the RELOAD value -// is copied into the live transfer counter. The channel can be -// started multiple times, and will perform the same number of -// transfers each time, as programmed by most recent write. -// -// The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT -// is used as a trigger, the written value is used immediately as -// the length of the new transfer sequence, as well as being -// written to RELOAD. -#define DMA_CH12_TRANS_COUNT_COUNT_RESET _u(0x0000000) -#define DMA_CH12_TRANS_COUNT_COUNT_BITS _u(0x0fffffff) -#define DMA_CH12_TRANS_COUNT_COUNT_MSB _u(27) -#define DMA_CH12_TRANS_COUNT_COUNT_LSB _u(0) -#define DMA_CH12_TRANS_COUNT_COUNT_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH12_CTRL_TRIG -// Description : DMA Channel 12 Control and Status -#define DMA_CH12_CTRL_TRIG_OFFSET _u(0x0000030c) -#define DMA_CH12_CTRL_TRIG_BITS _u(0xe7ffffff) -#define DMA_CH12_CTRL_TRIG_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : DMA_CH12_CTRL_TRIG_AHB_ERROR -// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel -// halts when it encounters any bus error, and always raises its -// channel IRQ flag. -#define DMA_CH12_CTRL_TRIG_AHB_ERROR_RESET _u(0x0) -#define DMA_CH12_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000) -#define DMA_CH12_CTRL_TRIG_AHB_ERROR_MSB _u(31) -#define DMA_CH12_CTRL_TRIG_AHB_ERROR_LSB _u(31) -#define DMA_CH12_CTRL_TRIG_AHB_ERROR_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : DMA_CH12_CTRL_TRIG_READ_ERROR -// Description : If 1, the channel received a read bus error. Write one to -// clear. -// READ_ADDR shows the approximate address where the bus error was -// encountered (will not be earlier, or more than 3 transfers -// later) -#define DMA_CH12_CTRL_TRIG_READ_ERROR_RESET _u(0x0) -#define DMA_CH12_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000) -#define DMA_CH12_CTRL_TRIG_READ_ERROR_MSB _u(30) -#define DMA_CH12_CTRL_TRIG_READ_ERROR_LSB _u(30) -#define DMA_CH12_CTRL_TRIG_READ_ERROR_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : DMA_CH12_CTRL_TRIG_WRITE_ERROR -// Description : If 1, the channel received a write bus error. Write one to -// clear. -// WRITE_ADDR shows the approximate address where the bus error -// was encountered (will not be earlier, or more than 5 transfers -// later) -#define DMA_CH12_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0) -#define DMA_CH12_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000) -#define DMA_CH12_CTRL_TRIG_WRITE_ERROR_MSB _u(29) -#define DMA_CH12_CTRL_TRIG_WRITE_ERROR_LSB _u(29) -#define DMA_CH12_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : DMA_CH12_CTRL_TRIG_BUSY -// Description : This flag goes high when the channel starts a new transfer -// sequence, and low when the last transfer of that sequence -// completes. Clearing EN while BUSY is high pauses the channel, -// and BUSY will stay high while paused. -// -// To terminate a sequence early (and clear the BUSY flag), see -// CHAN_ABORT. -#define DMA_CH12_CTRL_TRIG_BUSY_RESET _u(0x0) -#define DMA_CH12_CTRL_TRIG_BUSY_BITS _u(0x04000000) -#define DMA_CH12_CTRL_TRIG_BUSY_MSB _u(26) -#define DMA_CH12_CTRL_TRIG_BUSY_LSB _u(26) -#define DMA_CH12_CTRL_TRIG_BUSY_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : DMA_CH12_CTRL_TRIG_SNIFF_EN -// Description : If 1, this channel's data transfers are visible to the sniff -// hardware, and each transfer will advance the state of the -// checksum. This only applies if the sniff hardware is enabled, -// and has this channel selected. -// -// This allows checksum to be enabled or disabled on a per- -// control- block basis. -#define DMA_CH12_CTRL_TRIG_SNIFF_EN_RESET _u(0x0) -#define DMA_CH12_CTRL_TRIG_SNIFF_EN_BITS _u(0x02000000) -#define DMA_CH12_CTRL_TRIG_SNIFF_EN_MSB _u(25) -#define DMA_CH12_CTRL_TRIG_SNIFF_EN_LSB _u(25) -#define DMA_CH12_CTRL_TRIG_SNIFF_EN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH12_CTRL_TRIG_BSWAP -// Description : Apply byte-swap transformation to DMA data. -// For byte data, this has no effect. For halfword data, the two -// bytes of each halfword are swapped. For word data, the four -// bytes of each word are swapped to reverse order. -#define DMA_CH12_CTRL_TRIG_BSWAP_RESET _u(0x0) -#define DMA_CH12_CTRL_TRIG_BSWAP_BITS _u(0x01000000) -#define DMA_CH12_CTRL_TRIG_BSWAP_MSB _u(24) -#define DMA_CH12_CTRL_TRIG_BSWAP_LSB _u(24) -#define DMA_CH12_CTRL_TRIG_BSWAP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH12_CTRL_TRIG_IRQ_QUIET -// Description : In QUIET mode, the channel does not generate IRQs at the end of -// every transfer block. Instead, an IRQ is raised when NULL is -// written to a trigger register, indicating the end of a control -// block chain. -// -// This reduces the number of interrupts to be serviced by the CPU -// when transferring a DMA chain of many small control blocks. -#define DMA_CH12_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0) -#define DMA_CH12_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00800000) -#define DMA_CH12_CTRL_TRIG_IRQ_QUIET_MSB _u(23) -#define DMA_CH12_CTRL_TRIG_IRQ_QUIET_LSB _u(23) -#define DMA_CH12_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH12_CTRL_TRIG_TREQ_SEL -// Description : Select a Transfer Request signal. -// The channel uses the transfer request signal to pace its data -// transfer rate. Sources for TREQ signals are internal (TIMERS) -// or external (DREQ, a Data Request from the system). -// 0x0 to 0x3a -> select DREQ n as TREQ -// 0x3b -> Select Timer 0 as TREQ -// 0x3c -> Select Timer 1 as TREQ -// 0x3d -> Select Timer 2 as TREQ (Optional) -// 0x3e -> Select Timer 3 as TREQ (Optional) -// 0x3f -> Permanent request, for unpaced transfers. -#define DMA_CH12_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) -#define DMA_CH12_CTRL_TRIG_TREQ_SEL_BITS _u(0x007e0000) -#define DMA_CH12_CTRL_TRIG_TREQ_SEL_MSB _u(22) -#define DMA_CH12_CTRL_TRIG_TREQ_SEL_LSB _u(17) -#define DMA_CH12_CTRL_TRIG_TREQ_SEL_ACCESS "RW" -#define DMA_CH12_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) -#define DMA_CH12_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) -#define DMA_CH12_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) -#define DMA_CH12_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) -#define DMA_CH12_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) -// ----------------------------------------------------------------------------- -// Field : DMA_CH12_CTRL_TRIG_CHAIN_TO -// Description : When this channel completes, it will trigger the channel -// indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this -// channel)_. -// -// Note this field resets to 0, so channels 1 and above will chain -// to channel 0 by default. Set this field to avoid this -// behaviour. -#define DMA_CH12_CTRL_TRIG_CHAIN_TO_RESET _u(0x0) -#define DMA_CH12_CTRL_TRIG_CHAIN_TO_BITS _u(0x0001e000) -#define DMA_CH12_CTRL_TRIG_CHAIN_TO_MSB _u(16) -#define DMA_CH12_CTRL_TRIG_CHAIN_TO_LSB _u(13) -#define DMA_CH12_CTRL_TRIG_CHAIN_TO_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH12_CTRL_TRIG_RING_SEL -// Description : Select whether RING_SIZE applies to read or write addresses. -// If 0, read addresses are wrapped on a (1 << RING_SIZE) -// boundary. If 1, write addresses are wrapped. -#define DMA_CH12_CTRL_TRIG_RING_SEL_RESET _u(0x0) -#define DMA_CH12_CTRL_TRIG_RING_SEL_BITS _u(0x00001000) -#define DMA_CH12_CTRL_TRIG_RING_SEL_MSB _u(12) -#define DMA_CH12_CTRL_TRIG_RING_SEL_LSB _u(12) -#define DMA_CH12_CTRL_TRIG_RING_SEL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH12_CTRL_TRIG_RING_SIZE -// Description : Size of address wrap region. If 0, don't wrap. For values n > -// 0, only the lower n bits of the address will change. This wraps -// the address on a (1 << n) byte boundary, facilitating access to -// naturally-aligned ring buffers. -// -// Ring sizes between 2 and 32768 bytes are possible. This can -// apply to either read or write addresses, based on value of -// RING_SEL. -// 0x0 -> RING_NONE -#define DMA_CH12_CTRL_TRIG_RING_SIZE_RESET _u(0x0) -#define DMA_CH12_CTRL_TRIG_RING_SIZE_BITS _u(0x00000f00) -#define DMA_CH12_CTRL_TRIG_RING_SIZE_MSB _u(11) -#define DMA_CH12_CTRL_TRIG_RING_SIZE_LSB _u(8) -#define DMA_CH12_CTRL_TRIG_RING_SIZE_ACCESS "RW" -#define DMA_CH12_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0) -// ----------------------------------------------------------------------------- -// Field : DMA_CH12_CTRL_TRIG_INCR_WRITE_REV -// Description : If 1, and INCR_WRITE is 1, the write address is decremented -// rather than incremented with each transfer. -// -// If 1, and INCR_WRITE is 0, this otherwise-unused combination -// causes the write address to be incremented by twice the -// transfer size, i.e. skipping over alternate addresses. -#define DMA_CH12_CTRL_TRIG_INCR_WRITE_REV_RESET _u(0x0) -#define DMA_CH12_CTRL_TRIG_INCR_WRITE_REV_BITS _u(0x00000080) -#define DMA_CH12_CTRL_TRIG_INCR_WRITE_REV_MSB _u(7) -#define DMA_CH12_CTRL_TRIG_INCR_WRITE_REV_LSB _u(7) -#define DMA_CH12_CTRL_TRIG_INCR_WRITE_REV_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH12_CTRL_TRIG_INCR_WRITE -// Description : If 1, the write address increments with each transfer. If 0, -// each write is directed to the same, initial address. -// -// Generally this should be disabled for memory-to-peripheral -// transfers. -#define DMA_CH12_CTRL_TRIG_INCR_WRITE_RESET _u(0x0) -#define DMA_CH12_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000040) -#define DMA_CH12_CTRL_TRIG_INCR_WRITE_MSB _u(6) -#define DMA_CH12_CTRL_TRIG_INCR_WRITE_LSB _u(6) -#define DMA_CH12_CTRL_TRIG_INCR_WRITE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH12_CTRL_TRIG_INCR_READ_REV -// Description : If 1, and INCR_READ is 1, the read address is decremented -// rather than incremented with each transfer. -// -// If 1, and INCR_READ is 0, this otherwise-unused combination -// causes the read address to be incremented by twice the transfer -// size, i.e. skipping over alternate addresses. -#define DMA_CH12_CTRL_TRIG_INCR_READ_REV_RESET _u(0x0) -#define DMA_CH12_CTRL_TRIG_INCR_READ_REV_BITS _u(0x00000020) -#define DMA_CH12_CTRL_TRIG_INCR_READ_REV_MSB _u(5) -#define DMA_CH12_CTRL_TRIG_INCR_READ_REV_LSB _u(5) -#define DMA_CH12_CTRL_TRIG_INCR_READ_REV_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH12_CTRL_TRIG_INCR_READ -// Description : If 1, the read address increments with each transfer. If 0, -// each read is directed to the same, initial address. -// -// Generally this should be disabled for peripheral-to-memory -// transfers. -#define DMA_CH12_CTRL_TRIG_INCR_READ_RESET _u(0x0) -#define DMA_CH12_CTRL_TRIG_INCR_READ_BITS _u(0x00000010) -#define DMA_CH12_CTRL_TRIG_INCR_READ_MSB _u(4) -#define DMA_CH12_CTRL_TRIG_INCR_READ_LSB _u(4) -#define DMA_CH12_CTRL_TRIG_INCR_READ_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH12_CTRL_TRIG_DATA_SIZE -// Description : Set the size of each bus transfer (byte/halfword/word). -// READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) -// with each transfer. -// 0x0 -> SIZE_BYTE -// 0x1 -> SIZE_HALFWORD -// 0x2 -> SIZE_WORD -#define DMA_CH12_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) -#define DMA_CH12_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) -#define DMA_CH12_CTRL_TRIG_DATA_SIZE_MSB _u(3) -#define DMA_CH12_CTRL_TRIG_DATA_SIZE_LSB _u(2) -#define DMA_CH12_CTRL_TRIG_DATA_SIZE_ACCESS "RW" -#define DMA_CH12_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) -#define DMA_CH12_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1) -#define DMA_CH12_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) -// ----------------------------------------------------------------------------- -// Field : DMA_CH12_CTRL_TRIG_HIGH_PRIORITY -// Description : HIGH_PRIORITY gives a channel preferential treatment in issue -// scheduling: in each scheduling round, all high priority -// channels are considered first, and then only a single low -// priority channel, before returning to the high priority -// channels. -// -// This only affects the order in which the DMA schedules -// channels. The DMA's bus priority is not changed. If the DMA is -// not saturated then a low priority channel will see no loss of -// throughput. -#define DMA_CH12_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0) -#define DMA_CH12_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002) -#define DMA_CH12_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1) -#define DMA_CH12_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1) -#define DMA_CH12_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH12_CTRL_TRIG_EN -// Description : DMA Channel Enable. -// When 1, the channel will respond to triggering events, which -// will cause it to become BUSY and start transferring data. When -// 0, the channel will ignore triggers, stop issuing transfers, -// and pause the current transfer sequence (i.e. BUSY will remain -// high if already high) -#define DMA_CH12_CTRL_TRIG_EN_RESET _u(0x0) -#define DMA_CH12_CTRL_TRIG_EN_BITS _u(0x00000001) -#define DMA_CH12_CTRL_TRIG_EN_MSB _u(0) -#define DMA_CH12_CTRL_TRIG_EN_LSB _u(0) -#define DMA_CH12_CTRL_TRIG_EN_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH12_AL1_CTRL -// Description : Alias for channel 12 CTRL register -#define DMA_CH12_AL1_CTRL_OFFSET _u(0x00000310) -#define DMA_CH12_AL1_CTRL_BITS _u(0xffffffff) -#define DMA_CH12_AL1_CTRL_RESET "-" -#define DMA_CH12_AL1_CTRL_MSB _u(31) -#define DMA_CH12_AL1_CTRL_LSB _u(0) -#define DMA_CH12_AL1_CTRL_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH12_AL1_READ_ADDR -// Description : Alias for channel 12 READ_ADDR register -#define DMA_CH12_AL1_READ_ADDR_OFFSET _u(0x00000314) -#define DMA_CH12_AL1_READ_ADDR_BITS _u(0xffffffff) -#define DMA_CH12_AL1_READ_ADDR_RESET "-" -#define DMA_CH12_AL1_READ_ADDR_MSB _u(31) -#define DMA_CH12_AL1_READ_ADDR_LSB _u(0) -#define DMA_CH12_AL1_READ_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH12_AL1_WRITE_ADDR -// Description : Alias for channel 12 WRITE_ADDR register -#define DMA_CH12_AL1_WRITE_ADDR_OFFSET _u(0x00000318) -#define DMA_CH12_AL1_WRITE_ADDR_BITS _u(0xffffffff) -#define DMA_CH12_AL1_WRITE_ADDR_RESET "-" -#define DMA_CH12_AL1_WRITE_ADDR_MSB _u(31) -#define DMA_CH12_AL1_WRITE_ADDR_LSB _u(0) -#define DMA_CH12_AL1_WRITE_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH12_AL1_TRANS_COUNT_TRIG -// Description : Alias for channel 12 TRANS_COUNT register -// This is a trigger register (0xc). Writing a nonzero value will -// reload the channel counter and start the channel. -#define DMA_CH12_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x0000031c) -#define DMA_CH12_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff) -#define DMA_CH12_AL1_TRANS_COUNT_TRIG_RESET "-" -#define DMA_CH12_AL1_TRANS_COUNT_TRIG_MSB _u(31) -#define DMA_CH12_AL1_TRANS_COUNT_TRIG_LSB _u(0) -#define DMA_CH12_AL1_TRANS_COUNT_TRIG_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH12_AL2_CTRL -// Description : Alias for channel 12 CTRL register -#define DMA_CH12_AL2_CTRL_OFFSET _u(0x00000320) -#define DMA_CH12_AL2_CTRL_BITS _u(0xffffffff) -#define DMA_CH12_AL2_CTRL_RESET "-" -#define DMA_CH12_AL2_CTRL_MSB _u(31) -#define DMA_CH12_AL2_CTRL_LSB _u(0) -#define DMA_CH12_AL2_CTRL_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH12_AL2_TRANS_COUNT -// Description : Alias for channel 12 TRANS_COUNT register -#define DMA_CH12_AL2_TRANS_COUNT_OFFSET _u(0x00000324) -#define DMA_CH12_AL2_TRANS_COUNT_BITS _u(0xffffffff) -#define DMA_CH12_AL2_TRANS_COUNT_RESET "-" -#define DMA_CH12_AL2_TRANS_COUNT_MSB _u(31) -#define DMA_CH12_AL2_TRANS_COUNT_LSB _u(0) -#define DMA_CH12_AL2_TRANS_COUNT_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH12_AL2_READ_ADDR -// Description : Alias for channel 12 READ_ADDR register -#define DMA_CH12_AL2_READ_ADDR_OFFSET _u(0x00000328) -#define DMA_CH12_AL2_READ_ADDR_BITS _u(0xffffffff) -#define DMA_CH12_AL2_READ_ADDR_RESET "-" -#define DMA_CH12_AL2_READ_ADDR_MSB _u(31) -#define DMA_CH12_AL2_READ_ADDR_LSB _u(0) -#define DMA_CH12_AL2_READ_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH12_AL2_WRITE_ADDR_TRIG -// Description : Alias for channel 12 WRITE_ADDR register -// This is a trigger register (0xc). Writing a nonzero value will -// reload the channel counter and start the channel. -#define DMA_CH12_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x0000032c) -#define DMA_CH12_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff) -#define DMA_CH12_AL2_WRITE_ADDR_TRIG_RESET "-" -#define DMA_CH12_AL2_WRITE_ADDR_TRIG_MSB _u(31) -#define DMA_CH12_AL2_WRITE_ADDR_TRIG_LSB _u(0) -#define DMA_CH12_AL2_WRITE_ADDR_TRIG_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH12_AL3_CTRL -// Description : Alias for channel 12 CTRL register -#define DMA_CH12_AL3_CTRL_OFFSET _u(0x00000330) -#define DMA_CH12_AL3_CTRL_BITS _u(0xffffffff) -#define DMA_CH12_AL3_CTRL_RESET "-" -#define DMA_CH12_AL3_CTRL_MSB _u(31) -#define DMA_CH12_AL3_CTRL_LSB _u(0) -#define DMA_CH12_AL3_CTRL_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH12_AL3_WRITE_ADDR -// Description : Alias for channel 12 WRITE_ADDR register -#define DMA_CH12_AL3_WRITE_ADDR_OFFSET _u(0x00000334) -#define DMA_CH12_AL3_WRITE_ADDR_BITS _u(0xffffffff) -#define DMA_CH12_AL3_WRITE_ADDR_RESET "-" -#define DMA_CH12_AL3_WRITE_ADDR_MSB _u(31) -#define DMA_CH12_AL3_WRITE_ADDR_LSB _u(0) -#define DMA_CH12_AL3_WRITE_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH12_AL3_TRANS_COUNT -// Description : Alias for channel 12 TRANS_COUNT register -#define DMA_CH12_AL3_TRANS_COUNT_OFFSET _u(0x00000338) -#define DMA_CH12_AL3_TRANS_COUNT_BITS _u(0xffffffff) -#define DMA_CH12_AL3_TRANS_COUNT_RESET "-" -#define DMA_CH12_AL3_TRANS_COUNT_MSB _u(31) -#define DMA_CH12_AL3_TRANS_COUNT_LSB _u(0) -#define DMA_CH12_AL3_TRANS_COUNT_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH12_AL3_READ_ADDR_TRIG -// Description : Alias for channel 12 READ_ADDR register -// This is a trigger register (0xc). Writing a nonzero value will -// reload the channel counter and start the channel. -#define DMA_CH12_AL3_READ_ADDR_TRIG_OFFSET _u(0x0000033c) -#define DMA_CH12_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff) -#define DMA_CH12_AL3_READ_ADDR_TRIG_RESET "-" -#define DMA_CH12_AL3_READ_ADDR_TRIG_MSB _u(31) -#define DMA_CH12_AL3_READ_ADDR_TRIG_LSB _u(0) -#define DMA_CH12_AL3_READ_ADDR_TRIG_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH13_READ_ADDR -// Description : DMA Channel 13 Read Address pointer -// This register updates automatically each time a read completes. -// The current value is the next address to be read by this -// channel. -#define DMA_CH13_READ_ADDR_OFFSET _u(0x00000340) -#define DMA_CH13_READ_ADDR_BITS _u(0xffffffff) -#define DMA_CH13_READ_ADDR_RESET _u(0x00000000) -#define DMA_CH13_READ_ADDR_MSB _u(31) -#define DMA_CH13_READ_ADDR_LSB _u(0) -#define DMA_CH13_READ_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH13_WRITE_ADDR -// Description : DMA Channel 13 Write Address pointer -// This register updates automatically each time a write -// completes. The current value is the next address to be written -// by this channel. -#define DMA_CH13_WRITE_ADDR_OFFSET _u(0x00000344) -#define DMA_CH13_WRITE_ADDR_BITS _u(0xffffffff) -#define DMA_CH13_WRITE_ADDR_RESET _u(0x00000000) -#define DMA_CH13_WRITE_ADDR_MSB _u(31) -#define DMA_CH13_WRITE_ADDR_LSB _u(0) -#define DMA_CH13_WRITE_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH13_TRANS_COUNT -// Description : DMA Channel 13 Transfer Count -#define DMA_CH13_TRANS_COUNT_OFFSET _u(0x00000348) -#define DMA_CH13_TRANS_COUNT_BITS _u(0xffffffff) -#define DMA_CH13_TRANS_COUNT_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : DMA_CH13_TRANS_COUNT_MODE -// Description : When MODE is 0x0, the transfer count decrements with each -// transfer until 0, and then the channel triggers the next -// channel indicated by CTRL_CHAIN_TO. -// -// When MODE is 0x1, the transfer count decrements with each -// transfer until 0, and then the channel re-triggers itself, in -// addition to the trigger indicated by CTRL_CHAIN_TO. This is -// useful for e.g. an endless ring-buffer DMA with periodic -// interrupts. -// -// When MODE is 0xf, the transfer count does not decrement. The -// DMA channel performs an endless sequence of transfers, never -// triggering other channels or raising interrupts, until an ABORT -// is raised. -// -// All other values are reserved. -// 0x0 -> NORMAL -// 0x1 -> TRIGGER_SELF -// 0xf -> ENDLESS -#define DMA_CH13_TRANS_COUNT_MODE_RESET _u(0x0) -#define DMA_CH13_TRANS_COUNT_MODE_BITS _u(0xf0000000) -#define DMA_CH13_TRANS_COUNT_MODE_MSB _u(31) -#define DMA_CH13_TRANS_COUNT_MODE_LSB _u(28) -#define DMA_CH13_TRANS_COUNT_MODE_ACCESS "RW" -#define DMA_CH13_TRANS_COUNT_MODE_VALUE_NORMAL _u(0x0) -#define DMA_CH13_TRANS_COUNT_MODE_VALUE_TRIGGER_SELF _u(0x1) -#define DMA_CH13_TRANS_COUNT_MODE_VALUE_ENDLESS _u(0xf) -// ----------------------------------------------------------------------------- -// Field : DMA_CH13_TRANS_COUNT_COUNT -// Description : 28-bit transfer count (256 million transfers maximum). -// -// Program the number of bus transfers a channel will perform -// before halting. Note that, if transfers are larger than one -// byte in size, this is not equal to the number of bytes -// transferred (see CTRL_DATA_SIZE). -// -// When the channel is active, reading this register shows the -// number of transfers remaining, updating automatically each time -// a write transfer completes. -// -// Writing this register sets the RELOAD value for the transfer -// counter. Each time this channel is triggered, the RELOAD value -// is copied into the live transfer counter. The channel can be -// started multiple times, and will perform the same number of -// transfers each time, as programmed by most recent write. -// -// The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT -// is used as a trigger, the written value is used immediately as -// the length of the new transfer sequence, as well as being -// written to RELOAD. -#define DMA_CH13_TRANS_COUNT_COUNT_RESET _u(0x0000000) -#define DMA_CH13_TRANS_COUNT_COUNT_BITS _u(0x0fffffff) -#define DMA_CH13_TRANS_COUNT_COUNT_MSB _u(27) -#define DMA_CH13_TRANS_COUNT_COUNT_LSB _u(0) -#define DMA_CH13_TRANS_COUNT_COUNT_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH13_CTRL_TRIG -// Description : DMA Channel 13 Control and Status -#define DMA_CH13_CTRL_TRIG_OFFSET _u(0x0000034c) -#define DMA_CH13_CTRL_TRIG_BITS _u(0xe7ffffff) -#define DMA_CH13_CTRL_TRIG_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : DMA_CH13_CTRL_TRIG_AHB_ERROR -// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel -// halts when it encounters any bus error, and always raises its -// channel IRQ flag. -#define DMA_CH13_CTRL_TRIG_AHB_ERROR_RESET _u(0x0) -#define DMA_CH13_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000) -#define DMA_CH13_CTRL_TRIG_AHB_ERROR_MSB _u(31) -#define DMA_CH13_CTRL_TRIG_AHB_ERROR_LSB _u(31) -#define DMA_CH13_CTRL_TRIG_AHB_ERROR_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : DMA_CH13_CTRL_TRIG_READ_ERROR -// Description : If 1, the channel received a read bus error. Write one to -// clear. -// READ_ADDR shows the approximate address where the bus error was -// encountered (will not be earlier, or more than 3 transfers -// later) -#define DMA_CH13_CTRL_TRIG_READ_ERROR_RESET _u(0x0) -#define DMA_CH13_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000) -#define DMA_CH13_CTRL_TRIG_READ_ERROR_MSB _u(30) -#define DMA_CH13_CTRL_TRIG_READ_ERROR_LSB _u(30) -#define DMA_CH13_CTRL_TRIG_READ_ERROR_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : DMA_CH13_CTRL_TRIG_WRITE_ERROR -// Description : If 1, the channel received a write bus error. Write one to -// clear. -// WRITE_ADDR shows the approximate address where the bus error -// was encountered (will not be earlier, or more than 5 transfers -// later) -#define DMA_CH13_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0) -#define DMA_CH13_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000) -#define DMA_CH13_CTRL_TRIG_WRITE_ERROR_MSB _u(29) -#define DMA_CH13_CTRL_TRIG_WRITE_ERROR_LSB _u(29) -#define DMA_CH13_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : DMA_CH13_CTRL_TRIG_BUSY -// Description : This flag goes high when the channel starts a new transfer -// sequence, and low when the last transfer of that sequence -// completes. Clearing EN while BUSY is high pauses the channel, -// and BUSY will stay high while paused. -// -// To terminate a sequence early (and clear the BUSY flag), see -// CHAN_ABORT. -#define DMA_CH13_CTRL_TRIG_BUSY_RESET _u(0x0) -#define DMA_CH13_CTRL_TRIG_BUSY_BITS _u(0x04000000) -#define DMA_CH13_CTRL_TRIG_BUSY_MSB _u(26) -#define DMA_CH13_CTRL_TRIG_BUSY_LSB _u(26) -#define DMA_CH13_CTRL_TRIG_BUSY_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : DMA_CH13_CTRL_TRIG_SNIFF_EN -// Description : If 1, this channel's data transfers are visible to the sniff -// hardware, and each transfer will advance the state of the -// checksum. This only applies if the sniff hardware is enabled, -// and has this channel selected. -// -// This allows checksum to be enabled or disabled on a per- -// control- block basis. -#define DMA_CH13_CTRL_TRIG_SNIFF_EN_RESET _u(0x0) -#define DMA_CH13_CTRL_TRIG_SNIFF_EN_BITS _u(0x02000000) -#define DMA_CH13_CTRL_TRIG_SNIFF_EN_MSB _u(25) -#define DMA_CH13_CTRL_TRIG_SNIFF_EN_LSB _u(25) -#define DMA_CH13_CTRL_TRIG_SNIFF_EN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH13_CTRL_TRIG_BSWAP -// Description : Apply byte-swap transformation to DMA data. -// For byte data, this has no effect. For halfword data, the two -// bytes of each halfword are swapped. For word data, the four -// bytes of each word are swapped to reverse order. -#define DMA_CH13_CTRL_TRIG_BSWAP_RESET _u(0x0) -#define DMA_CH13_CTRL_TRIG_BSWAP_BITS _u(0x01000000) -#define DMA_CH13_CTRL_TRIG_BSWAP_MSB _u(24) -#define DMA_CH13_CTRL_TRIG_BSWAP_LSB _u(24) -#define DMA_CH13_CTRL_TRIG_BSWAP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH13_CTRL_TRIG_IRQ_QUIET -// Description : In QUIET mode, the channel does not generate IRQs at the end of -// every transfer block. Instead, an IRQ is raised when NULL is -// written to a trigger register, indicating the end of a control -// block chain. -// -// This reduces the number of interrupts to be serviced by the CPU -// when transferring a DMA chain of many small control blocks. -#define DMA_CH13_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0) -#define DMA_CH13_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00800000) -#define DMA_CH13_CTRL_TRIG_IRQ_QUIET_MSB _u(23) -#define DMA_CH13_CTRL_TRIG_IRQ_QUIET_LSB _u(23) -#define DMA_CH13_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH13_CTRL_TRIG_TREQ_SEL -// Description : Select a Transfer Request signal. -// The channel uses the transfer request signal to pace its data -// transfer rate. Sources for TREQ signals are internal (TIMERS) -// or external (DREQ, a Data Request from the system). -// 0x0 to 0x3a -> select DREQ n as TREQ -// 0x3b -> Select Timer 0 as TREQ -// 0x3c -> Select Timer 1 as TREQ -// 0x3d -> Select Timer 2 as TREQ (Optional) -// 0x3e -> Select Timer 3 as TREQ (Optional) -// 0x3f -> Permanent request, for unpaced transfers. -#define DMA_CH13_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) -#define DMA_CH13_CTRL_TRIG_TREQ_SEL_BITS _u(0x007e0000) -#define DMA_CH13_CTRL_TRIG_TREQ_SEL_MSB _u(22) -#define DMA_CH13_CTRL_TRIG_TREQ_SEL_LSB _u(17) -#define DMA_CH13_CTRL_TRIG_TREQ_SEL_ACCESS "RW" -#define DMA_CH13_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) -#define DMA_CH13_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) -#define DMA_CH13_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) -#define DMA_CH13_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) -#define DMA_CH13_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) -// ----------------------------------------------------------------------------- -// Field : DMA_CH13_CTRL_TRIG_CHAIN_TO -// Description : When this channel completes, it will trigger the channel -// indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this -// channel)_. -// -// Note this field resets to 0, so channels 1 and above will chain -// to channel 0 by default. Set this field to avoid this -// behaviour. -#define DMA_CH13_CTRL_TRIG_CHAIN_TO_RESET _u(0x0) -#define DMA_CH13_CTRL_TRIG_CHAIN_TO_BITS _u(0x0001e000) -#define DMA_CH13_CTRL_TRIG_CHAIN_TO_MSB _u(16) -#define DMA_CH13_CTRL_TRIG_CHAIN_TO_LSB _u(13) -#define DMA_CH13_CTRL_TRIG_CHAIN_TO_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH13_CTRL_TRIG_RING_SEL -// Description : Select whether RING_SIZE applies to read or write addresses. -// If 0, read addresses are wrapped on a (1 << RING_SIZE) -// boundary. If 1, write addresses are wrapped. -#define DMA_CH13_CTRL_TRIG_RING_SEL_RESET _u(0x0) -#define DMA_CH13_CTRL_TRIG_RING_SEL_BITS _u(0x00001000) -#define DMA_CH13_CTRL_TRIG_RING_SEL_MSB _u(12) -#define DMA_CH13_CTRL_TRIG_RING_SEL_LSB _u(12) -#define DMA_CH13_CTRL_TRIG_RING_SEL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH13_CTRL_TRIG_RING_SIZE -// Description : Size of address wrap region. If 0, don't wrap. For values n > -// 0, only the lower n bits of the address will change. This wraps -// the address on a (1 << n) byte boundary, facilitating access to -// naturally-aligned ring buffers. -// -// Ring sizes between 2 and 32768 bytes are possible. This can -// apply to either read or write addresses, based on value of -// RING_SEL. -// 0x0 -> RING_NONE -#define DMA_CH13_CTRL_TRIG_RING_SIZE_RESET _u(0x0) -#define DMA_CH13_CTRL_TRIG_RING_SIZE_BITS _u(0x00000f00) -#define DMA_CH13_CTRL_TRIG_RING_SIZE_MSB _u(11) -#define DMA_CH13_CTRL_TRIG_RING_SIZE_LSB _u(8) -#define DMA_CH13_CTRL_TRIG_RING_SIZE_ACCESS "RW" -#define DMA_CH13_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0) -// ----------------------------------------------------------------------------- -// Field : DMA_CH13_CTRL_TRIG_INCR_WRITE_REV -// Description : If 1, and INCR_WRITE is 1, the write address is decremented -// rather than incremented with each transfer. -// -// If 1, and INCR_WRITE is 0, this otherwise-unused combination -// causes the write address to be incremented by twice the -// transfer size, i.e. skipping over alternate addresses. -#define DMA_CH13_CTRL_TRIG_INCR_WRITE_REV_RESET _u(0x0) -#define DMA_CH13_CTRL_TRIG_INCR_WRITE_REV_BITS _u(0x00000080) -#define DMA_CH13_CTRL_TRIG_INCR_WRITE_REV_MSB _u(7) -#define DMA_CH13_CTRL_TRIG_INCR_WRITE_REV_LSB _u(7) -#define DMA_CH13_CTRL_TRIG_INCR_WRITE_REV_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH13_CTRL_TRIG_INCR_WRITE -// Description : If 1, the write address increments with each transfer. If 0, -// each write is directed to the same, initial address. -// -// Generally this should be disabled for memory-to-peripheral -// transfers. -#define DMA_CH13_CTRL_TRIG_INCR_WRITE_RESET _u(0x0) -#define DMA_CH13_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000040) -#define DMA_CH13_CTRL_TRIG_INCR_WRITE_MSB _u(6) -#define DMA_CH13_CTRL_TRIG_INCR_WRITE_LSB _u(6) -#define DMA_CH13_CTRL_TRIG_INCR_WRITE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH13_CTRL_TRIG_INCR_READ_REV -// Description : If 1, and INCR_READ is 1, the read address is decremented -// rather than incremented with each transfer. -// -// If 1, and INCR_READ is 0, this otherwise-unused combination -// causes the read address to be incremented by twice the transfer -// size, i.e. skipping over alternate addresses. -#define DMA_CH13_CTRL_TRIG_INCR_READ_REV_RESET _u(0x0) -#define DMA_CH13_CTRL_TRIG_INCR_READ_REV_BITS _u(0x00000020) -#define DMA_CH13_CTRL_TRIG_INCR_READ_REV_MSB _u(5) -#define DMA_CH13_CTRL_TRIG_INCR_READ_REV_LSB _u(5) -#define DMA_CH13_CTRL_TRIG_INCR_READ_REV_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH13_CTRL_TRIG_INCR_READ -// Description : If 1, the read address increments with each transfer. If 0, -// each read is directed to the same, initial address. -// -// Generally this should be disabled for peripheral-to-memory -// transfers. -#define DMA_CH13_CTRL_TRIG_INCR_READ_RESET _u(0x0) -#define DMA_CH13_CTRL_TRIG_INCR_READ_BITS _u(0x00000010) -#define DMA_CH13_CTRL_TRIG_INCR_READ_MSB _u(4) -#define DMA_CH13_CTRL_TRIG_INCR_READ_LSB _u(4) -#define DMA_CH13_CTRL_TRIG_INCR_READ_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH13_CTRL_TRIG_DATA_SIZE -// Description : Set the size of each bus transfer (byte/halfword/word). -// READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) -// with each transfer. -// 0x0 -> SIZE_BYTE -// 0x1 -> SIZE_HALFWORD -// 0x2 -> SIZE_WORD -#define DMA_CH13_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) -#define DMA_CH13_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) -#define DMA_CH13_CTRL_TRIG_DATA_SIZE_MSB _u(3) -#define DMA_CH13_CTRL_TRIG_DATA_SIZE_LSB _u(2) -#define DMA_CH13_CTRL_TRIG_DATA_SIZE_ACCESS "RW" -#define DMA_CH13_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) -#define DMA_CH13_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1) -#define DMA_CH13_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) -// ----------------------------------------------------------------------------- -// Field : DMA_CH13_CTRL_TRIG_HIGH_PRIORITY -// Description : HIGH_PRIORITY gives a channel preferential treatment in issue -// scheduling: in each scheduling round, all high priority -// channels are considered first, and then only a single low -// priority channel, before returning to the high priority -// channels. -// -// This only affects the order in which the DMA schedules -// channels. The DMA's bus priority is not changed. If the DMA is -// not saturated then a low priority channel will see no loss of -// throughput. -#define DMA_CH13_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0) -#define DMA_CH13_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002) -#define DMA_CH13_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1) -#define DMA_CH13_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1) -#define DMA_CH13_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH13_CTRL_TRIG_EN -// Description : DMA Channel Enable. -// When 1, the channel will respond to triggering events, which -// will cause it to become BUSY and start transferring data. When -// 0, the channel will ignore triggers, stop issuing transfers, -// and pause the current transfer sequence (i.e. BUSY will remain -// high if already high) -#define DMA_CH13_CTRL_TRIG_EN_RESET _u(0x0) -#define DMA_CH13_CTRL_TRIG_EN_BITS _u(0x00000001) -#define DMA_CH13_CTRL_TRIG_EN_MSB _u(0) -#define DMA_CH13_CTRL_TRIG_EN_LSB _u(0) -#define DMA_CH13_CTRL_TRIG_EN_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH13_AL1_CTRL -// Description : Alias for channel 13 CTRL register -#define DMA_CH13_AL1_CTRL_OFFSET _u(0x00000350) -#define DMA_CH13_AL1_CTRL_BITS _u(0xffffffff) -#define DMA_CH13_AL1_CTRL_RESET "-" -#define DMA_CH13_AL1_CTRL_MSB _u(31) -#define DMA_CH13_AL1_CTRL_LSB _u(0) -#define DMA_CH13_AL1_CTRL_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH13_AL1_READ_ADDR -// Description : Alias for channel 13 READ_ADDR register -#define DMA_CH13_AL1_READ_ADDR_OFFSET _u(0x00000354) -#define DMA_CH13_AL1_READ_ADDR_BITS _u(0xffffffff) -#define DMA_CH13_AL1_READ_ADDR_RESET "-" -#define DMA_CH13_AL1_READ_ADDR_MSB _u(31) -#define DMA_CH13_AL1_READ_ADDR_LSB _u(0) -#define DMA_CH13_AL1_READ_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH13_AL1_WRITE_ADDR -// Description : Alias for channel 13 WRITE_ADDR register -#define DMA_CH13_AL1_WRITE_ADDR_OFFSET _u(0x00000358) -#define DMA_CH13_AL1_WRITE_ADDR_BITS _u(0xffffffff) -#define DMA_CH13_AL1_WRITE_ADDR_RESET "-" -#define DMA_CH13_AL1_WRITE_ADDR_MSB _u(31) -#define DMA_CH13_AL1_WRITE_ADDR_LSB _u(0) -#define DMA_CH13_AL1_WRITE_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH13_AL1_TRANS_COUNT_TRIG -// Description : Alias for channel 13 TRANS_COUNT register -// This is a trigger register (0xc). Writing a nonzero value will -// reload the channel counter and start the channel. -#define DMA_CH13_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x0000035c) -#define DMA_CH13_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff) -#define DMA_CH13_AL1_TRANS_COUNT_TRIG_RESET "-" -#define DMA_CH13_AL1_TRANS_COUNT_TRIG_MSB _u(31) -#define DMA_CH13_AL1_TRANS_COUNT_TRIG_LSB _u(0) -#define DMA_CH13_AL1_TRANS_COUNT_TRIG_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH13_AL2_CTRL -// Description : Alias for channel 13 CTRL register -#define DMA_CH13_AL2_CTRL_OFFSET _u(0x00000360) -#define DMA_CH13_AL2_CTRL_BITS _u(0xffffffff) -#define DMA_CH13_AL2_CTRL_RESET "-" -#define DMA_CH13_AL2_CTRL_MSB _u(31) -#define DMA_CH13_AL2_CTRL_LSB _u(0) -#define DMA_CH13_AL2_CTRL_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH13_AL2_TRANS_COUNT -// Description : Alias for channel 13 TRANS_COUNT register -#define DMA_CH13_AL2_TRANS_COUNT_OFFSET _u(0x00000364) -#define DMA_CH13_AL2_TRANS_COUNT_BITS _u(0xffffffff) -#define DMA_CH13_AL2_TRANS_COUNT_RESET "-" -#define DMA_CH13_AL2_TRANS_COUNT_MSB _u(31) -#define DMA_CH13_AL2_TRANS_COUNT_LSB _u(0) -#define DMA_CH13_AL2_TRANS_COUNT_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH13_AL2_READ_ADDR -// Description : Alias for channel 13 READ_ADDR register -#define DMA_CH13_AL2_READ_ADDR_OFFSET _u(0x00000368) -#define DMA_CH13_AL2_READ_ADDR_BITS _u(0xffffffff) -#define DMA_CH13_AL2_READ_ADDR_RESET "-" -#define DMA_CH13_AL2_READ_ADDR_MSB _u(31) -#define DMA_CH13_AL2_READ_ADDR_LSB _u(0) -#define DMA_CH13_AL2_READ_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH13_AL2_WRITE_ADDR_TRIG -// Description : Alias for channel 13 WRITE_ADDR register -// This is a trigger register (0xc). Writing a nonzero value will -// reload the channel counter and start the channel. -#define DMA_CH13_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x0000036c) -#define DMA_CH13_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff) -#define DMA_CH13_AL2_WRITE_ADDR_TRIG_RESET "-" -#define DMA_CH13_AL2_WRITE_ADDR_TRIG_MSB _u(31) -#define DMA_CH13_AL2_WRITE_ADDR_TRIG_LSB _u(0) -#define DMA_CH13_AL2_WRITE_ADDR_TRIG_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH13_AL3_CTRL -// Description : Alias for channel 13 CTRL register -#define DMA_CH13_AL3_CTRL_OFFSET _u(0x00000370) -#define DMA_CH13_AL3_CTRL_BITS _u(0xffffffff) -#define DMA_CH13_AL3_CTRL_RESET "-" -#define DMA_CH13_AL3_CTRL_MSB _u(31) -#define DMA_CH13_AL3_CTRL_LSB _u(0) -#define DMA_CH13_AL3_CTRL_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH13_AL3_WRITE_ADDR -// Description : Alias for channel 13 WRITE_ADDR register -#define DMA_CH13_AL3_WRITE_ADDR_OFFSET _u(0x00000374) -#define DMA_CH13_AL3_WRITE_ADDR_BITS _u(0xffffffff) -#define DMA_CH13_AL3_WRITE_ADDR_RESET "-" -#define DMA_CH13_AL3_WRITE_ADDR_MSB _u(31) -#define DMA_CH13_AL3_WRITE_ADDR_LSB _u(0) -#define DMA_CH13_AL3_WRITE_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH13_AL3_TRANS_COUNT -// Description : Alias for channel 13 TRANS_COUNT register -#define DMA_CH13_AL3_TRANS_COUNT_OFFSET _u(0x00000378) -#define DMA_CH13_AL3_TRANS_COUNT_BITS _u(0xffffffff) -#define DMA_CH13_AL3_TRANS_COUNT_RESET "-" -#define DMA_CH13_AL3_TRANS_COUNT_MSB _u(31) -#define DMA_CH13_AL3_TRANS_COUNT_LSB _u(0) -#define DMA_CH13_AL3_TRANS_COUNT_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH13_AL3_READ_ADDR_TRIG -// Description : Alias for channel 13 READ_ADDR register -// This is a trigger register (0xc). Writing a nonzero value will -// reload the channel counter and start the channel. -#define DMA_CH13_AL3_READ_ADDR_TRIG_OFFSET _u(0x0000037c) -#define DMA_CH13_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff) -#define DMA_CH13_AL3_READ_ADDR_TRIG_RESET "-" -#define DMA_CH13_AL3_READ_ADDR_TRIG_MSB _u(31) -#define DMA_CH13_AL3_READ_ADDR_TRIG_LSB _u(0) -#define DMA_CH13_AL3_READ_ADDR_TRIG_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH14_READ_ADDR -// Description : DMA Channel 14 Read Address pointer -// This register updates automatically each time a read completes. -// The current value is the next address to be read by this -// channel. -#define DMA_CH14_READ_ADDR_OFFSET _u(0x00000380) -#define DMA_CH14_READ_ADDR_BITS _u(0xffffffff) -#define DMA_CH14_READ_ADDR_RESET _u(0x00000000) -#define DMA_CH14_READ_ADDR_MSB _u(31) -#define DMA_CH14_READ_ADDR_LSB _u(0) -#define DMA_CH14_READ_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH14_WRITE_ADDR -// Description : DMA Channel 14 Write Address pointer -// This register updates automatically each time a write -// completes. The current value is the next address to be written -// by this channel. -#define DMA_CH14_WRITE_ADDR_OFFSET _u(0x00000384) -#define DMA_CH14_WRITE_ADDR_BITS _u(0xffffffff) -#define DMA_CH14_WRITE_ADDR_RESET _u(0x00000000) -#define DMA_CH14_WRITE_ADDR_MSB _u(31) -#define DMA_CH14_WRITE_ADDR_LSB _u(0) -#define DMA_CH14_WRITE_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH14_TRANS_COUNT -// Description : DMA Channel 14 Transfer Count -#define DMA_CH14_TRANS_COUNT_OFFSET _u(0x00000388) -#define DMA_CH14_TRANS_COUNT_BITS _u(0xffffffff) -#define DMA_CH14_TRANS_COUNT_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : DMA_CH14_TRANS_COUNT_MODE -// Description : When MODE is 0x0, the transfer count decrements with each -// transfer until 0, and then the channel triggers the next -// channel indicated by CTRL_CHAIN_TO. -// -// When MODE is 0x1, the transfer count decrements with each -// transfer until 0, and then the channel re-triggers itself, in -// addition to the trigger indicated by CTRL_CHAIN_TO. This is -// useful for e.g. an endless ring-buffer DMA with periodic -// interrupts. -// -// When MODE is 0xf, the transfer count does not decrement. The -// DMA channel performs an endless sequence of transfers, never -// triggering other channels or raising interrupts, until an ABORT -// is raised. -// -// All other values are reserved. -// 0x0 -> NORMAL -// 0x1 -> TRIGGER_SELF -// 0xf -> ENDLESS -#define DMA_CH14_TRANS_COUNT_MODE_RESET _u(0x0) -#define DMA_CH14_TRANS_COUNT_MODE_BITS _u(0xf0000000) -#define DMA_CH14_TRANS_COUNT_MODE_MSB _u(31) -#define DMA_CH14_TRANS_COUNT_MODE_LSB _u(28) -#define DMA_CH14_TRANS_COUNT_MODE_ACCESS "RW" -#define DMA_CH14_TRANS_COUNT_MODE_VALUE_NORMAL _u(0x0) -#define DMA_CH14_TRANS_COUNT_MODE_VALUE_TRIGGER_SELF _u(0x1) -#define DMA_CH14_TRANS_COUNT_MODE_VALUE_ENDLESS _u(0xf) -// ----------------------------------------------------------------------------- -// Field : DMA_CH14_TRANS_COUNT_COUNT -// Description : 28-bit transfer count (256 million transfers maximum). -// -// Program the number of bus transfers a channel will perform -// before halting. Note that, if transfers are larger than one -// byte in size, this is not equal to the number of bytes -// transferred (see CTRL_DATA_SIZE). -// -// When the channel is active, reading this register shows the -// number of transfers remaining, updating automatically each time -// a write transfer completes. -// -// Writing this register sets the RELOAD value for the transfer -// counter. Each time this channel is triggered, the RELOAD value -// is copied into the live transfer counter. The channel can be -// started multiple times, and will perform the same number of -// transfers each time, as programmed by most recent write. -// -// The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT -// is used as a trigger, the written value is used immediately as -// the length of the new transfer sequence, as well as being -// written to RELOAD. -#define DMA_CH14_TRANS_COUNT_COUNT_RESET _u(0x0000000) -#define DMA_CH14_TRANS_COUNT_COUNT_BITS _u(0x0fffffff) -#define DMA_CH14_TRANS_COUNT_COUNT_MSB _u(27) -#define DMA_CH14_TRANS_COUNT_COUNT_LSB _u(0) -#define DMA_CH14_TRANS_COUNT_COUNT_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH14_CTRL_TRIG -// Description : DMA Channel 14 Control and Status -#define DMA_CH14_CTRL_TRIG_OFFSET _u(0x0000038c) -#define DMA_CH14_CTRL_TRIG_BITS _u(0xe7ffffff) -#define DMA_CH14_CTRL_TRIG_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : DMA_CH14_CTRL_TRIG_AHB_ERROR -// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel -// halts when it encounters any bus error, and always raises its -// channel IRQ flag. -#define DMA_CH14_CTRL_TRIG_AHB_ERROR_RESET _u(0x0) -#define DMA_CH14_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000) -#define DMA_CH14_CTRL_TRIG_AHB_ERROR_MSB _u(31) -#define DMA_CH14_CTRL_TRIG_AHB_ERROR_LSB _u(31) -#define DMA_CH14_CTRL_TRIG_AHB_ERROR_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : DMA_CH14_CTRL_TRIG_READ_ERROR -// Description : If 1, the channel received a read bus error. Write one to -// clear. -// READ_ADDR shows the approximate address where the bus error was -// encountered (will not be earlier, or more than 3 transfers -// later) -#define DMA_CH14_CTRL_TRIG_READ_ERROR_RESET _u(0x0) -#define DMA_CH14_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000) -#define DMA_CH14_CTRL_TRIG_READ_ERROR_MSB _u(30) -#define DMA_CH14_CTRL_TRIG_READ_ERROR_LSB _u(30) -#define DMA_CH14_CTRL_TRIG_READ_ERROR_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : DMA_CH14_CTRL_TRIG_WRITE_ERROR -// Description : If 1, the channel received a write bus error. Write one to -// clear. -// WRITE_ADDR shows the approximate address where the bus error -// was encountered (will not be earlier, or more than 5 transfers -// later) -#define DMA_CH14_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0) -#define DMA_CH14_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000) -#define DMA_CH14_CTRL_TRIG_WRITE_ERROR_MSB _u(29) -#define DMA_CH14_CTRL_TRIG_WRITE_ERROR_LSB _u(29) -#define DMA_CH14_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : DMA_CH14_CTRL_TRIG_BUSY -// Description : This flag goes high when the channel starts a new transfer -// sequence, and low when the last transfer of that sequence -// completes. Clearing EN while BUSY is high pauses the channel, -// and BUSY will stay high while paused. -// -// To terminate a sequence early (and clear the BUSY flag), see -// CHAN_ABORT. -#define DMA_CH14_CTRL_TRIG_BUSY_RESET _u(0x0) -#define DMA_CH14_CTRL_TRIG_BUSY_BITS _u(0x04000000) -#define DMA_CH14_CTRL_TRIG_BUSY_MSB _u(26) -#define DMA_CH14_CTRL_TRIG_BUSY_LSB _u(26) -#define DMA_CH14_CTRL_TRIG_BUSY_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : DMA_CH14_CTRL_TRIG_SNIFF_EN -// Description : If 1, this channel's data transfers are visible to the sniff -// hardware, and each transfer will advance the state of the -// checksum. This only applies if the sniff hardware is enabled, -// and has this channel selected. -// -// This allows checksum to be enabled or disabled on a per- -// control- block basis. -#define DMA_CH14_CTRL_TRIG_SNIFF_EN_RESET _u(0x0) -#define DMA_CH14_CTRL_TRIG_SNIFF_EN_BITS _u(0x02000000) -#define DMA_CH14_CTRL_TRIG_SNIFF_EN_MSB _u(25) -#define DMA_CH14_CTRL_TRIG_SNIFF_EN_LSB _u(25) -#define DMA_CH14_CTRL_TRIG_SNIFF_EN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH14_CTRL_TRIG_BSWAP -// Description : Apply byte-swap transformation to DMA data. -// For byte data, this has no effect. For halfword data, the two -// bytes of each halfword are swapped. For word data, the four -// bytes of each word are swapped to reverse order. -#define DMA_CH14_CTRL_TRIG_BSWAP_RESET _u(0x0) -#define DMA_CH14_CTRL_TRIG_BSWAP_BITS _u(0x01000000) -#define DMA_CH14_CTRL_TRIG_BSWAP_MSB _u(24) -#define DMA_CH14_CTRL_TRIG_BSWAP_LSB _u(24) -#define DMA_CH14_CTRL_TRIG_BSWAP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH14_CTRL_TRIG_IRQ_QUIET -// Description : In QUIET mode, the channel does not generate IRQs at the end of -// every transfer block. Instead, an IRQ is raised when NULL is -// written to a trigger register, indicating the end of a control -// block chain. -// -// This reduces the number of interrupts to be serviced by the CPU -// when transferring a DMA chain of many small control blocks. -#define DMA_CH14_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0) -#define DMA_CH14_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00800000) -#define DMA_CH14_CTRL_TRIG_IRQ_QUIET_MSB _u(23) -#define DMA_CH14_CTRL_TRIG_IRQ_QUIET_LSB _u(23) -#define DMA_CH14_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH14_CTRL_TRIG_TREQ_SEL -// Description : Select a Transfer Request signal. -// The channel uses the transfer request signal to pace its data -// transfer rate. Sources for TREQ signals are internal (TIMERS) -// or external (DREQ, a Data Request from the system). -// 0x0 to 0x3a -> select DREQ n as TREQ -// 0x3b -> Select Timer 0 as TREQ -// 0x3c -> Select Timer 1 as TREQ -// 0x3d -> Select Timer 2 as TREQ (Optional) -// 0x3e -> Select Timer 3 as TREQ (Optional) -// 0x3f -> Permanent request, for unpaced transfers. -#define DMA_CH14_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) -#define DMA_CH14_CTRL_TRIG_TREQ_SEL_BITS _u(0x007e0000) -#define DMA_CH14_CTRL_TRIG_TREQ_SEL_MSB _u(22) -#define DMA_CH14_CTRL_TRIG_TREQ_SEL_LSB _u(17) -#define DMA_CH14_CTRL_TRIG_TREQ_SEL_ACCESS "RW" -#define DMA_CH14_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) -#define DMA_CH14_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) -#define DMA_CH14_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) -#define DMA_CH14_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) -#define DMA_CH14_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) -// ----------------------------------------------------------------------------- -// Field : DMA_CH14_CTRL_TRIG_CHAIN_TO -// Description : When this channel completes, it will trigger the channel -// indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this -// channel)_. -// -// Note this field resets to 0, so channels 1 and above will chain -// to channel 0 by default. Set this field to avoid this -// behaviour. -#define DMA_CH14_CTRL_TRIG_CHAIN_TO_RESET _u(0x0) -#define DMA_CH14_CTRL_TRIG_CHAIN_TO_BITS _u(0x0001e000) -#define DMA_CH14_CTRL_TRIG_CHAIN_TO_MSB _u(16) -#define DMA_CH14_CTRL_TRIG_CHAIN_TO_LSB _u(13) -#define DMA_CH14_CTRL_TRIG_CHAIN_TO_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH14_CTRL_TRIG_RING_SEL -// Description : Select whether RING_SIZE applies to read or write addresses. -// If 0, read addresses are wrapped on a (1 << RING_SIZE) -// boundary. If 1, write addresses are wrapped. -#define DMA_CH14_CTRL_TRIG_RING_SEL_RESET _u(0x0) -#define DMA_CH14_CTRL_TRIG_RING_SEL_BITS _u(0x00001000) -#define DMA_CH14_CTRL_TRIG_RING_SEL_MSB _u(12) -#define DMA_CH14_CTRL_TRIG_RING_SEL_LSB _u(12) -#define DMA_CH14_CTRL_TRIG_RING_SEL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH14_CTRL_TRIG_RING_SIZE -// Description : Size of address wrap region. If 0, don't wrap. For values n > -// 0, only the lower n bits of the address will change. This wraps -// the address on a (1 << n) byte boundary, facilitating access to -// naturally-aligned ring buffers. -// -// Ring sizes between 2 and 32768 bytes are possible. This can -// apply to either read or write addresses, based on value of -// RING_SEL. -// 0x0 -> RING_NONE -#define DMA_CH14_CTRL_TRIG_RING_SIZE_RESET _u(0x0) -#define DMA_CH14_CTRL_TRIG_RING_SIZE_BITS _u(0x00000f00) -#define DMA_CH14_CTRL_TRIG_RING_SIZE_MSB _u(11) -#define DMA_CH14_CTRL_TRIG_RING_SIZE_LSB _u(8) -#define DMA_CH14_CTRL_TRIG_RING_SIZE_ACCESS "RW" -#define DMA_CH14_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0) -// ----------------------------------------------------------------------------- -// Field : DMA_CH14_CTRL_TRIG_INCR_WRITE_REV -// Description : If 1, and INCR_WRITE is 1, the write address is decremented -// rather than incremented with each transfer. -// -// If 1, and INCR_WRITE is 0, this otherwise-unused combination -// causes the write address to be incremented by twice the -// transfer size, i.e. skipping over alternate addresses. -#define DMA_CH14_CTRL_TRIG_INCR_WRITE_REV_RESET _u(0x0) -#define DMA_CH14_CTRL_TRIG_INCR_WRITE_REV_BITS _u(0x00000080) -#define DMA_CH14_CTRL_TRIG_INCR_WRITE_REV_MSB _u(7) -#define DMA_CH14_CTRL_TRIG_INCR_WRITE_REV_LSB _u(7) -#define DMA_CH14_CTRL_TRIG_INCR_WRITE_REV_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH14_CTRL_TRIG_INCR_WRITE -// Description : If 1, the write address increments with each transfer. If 0, -// each write is directed to the same, initial address. -// -// Generally this should be disabled for memory-to-peripheral -// transfers. -#define DMA_CH14_CTRL_TRIG_INCR_WRITE_RESET _u(0x0) -#define DMA_CH14_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000040) -#define DMA_CH14_CTRL_TRIG_INCR_WRITE_MSB _u(6) -#define DMA_CH14_CTRL_TRIG_INCR_WRITE_LSB _u(6) -#define DMA_CH14_CTRL_TRIG_INCR_WRITE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH14_CTRL_TRIG_INCR_READ_REV -// Description : If 1, and INCR_READ is 1, the read address is decremented -// rather than incremented with each transfer. -// -// If 1, and INCR_READ is 0, this otherwise-unused combination -// causes the read address to be incremented by twice the transfer -// size, i.e. skipping over alternate addresses. -#define DMA_CH14_CTRL_TRIG_INCR_READ_REV_RESET _u(0x0) -#define DMA_CH14_CTRL_TRIG_INCR_READ_REV_BITS _u(0x00000020) -#define DMA_CH14_CTRL_TRIG_INCR_READ_REV_MSB _u(5) -#define DMA_CH14_CTRL_TRIG_INCR_READ_REV_LSB _u(5) -#define DMA_CH14_CTRL_TRIG_INCR_READ_REV_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH14_CTRL_TRIG_INCR_READ -// Description : If 1, the read address increments with each transfer. If 0, -// each read is directed to the same, initial address. -// -// Generally this should be disabled for peripheral-to-memory -// transfers. -#define DMA_CH14_CTRL_TRIG_INCR_READ_RESET _u(0x0) -#define DMA_CH14_CTRL_TRIG_INCR_READ_BITS _u(0x00000010) -#define DMA_CH14_CTRL_TRIG_INCR_READ_MSB _u(4) -#define DMA_CH14_CTRL_TRIG_INCR_READ_LSB _u(4) -#define DMA_CH14_CTRL_TRIG_INCR_READ_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH14_CTRL_TRIG_DATA_SIZE -// Description : Set the size of each bus transfer (byte/halfword/word). -// READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) -// with each transfer. -// 0x0 -> SIZE_BYTE -// 0x1 -> SIZE_HALFWORD -// 0x2 -> SIZE_WORD -#define DMA_CH14_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) -#define DMA_CH14_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) -#define DMA_CH14_CTRL_TRIG_DATA_SIZE_MSB _u(3) -#define DMA_CH14_CTRL_TRIG_DATA_SIZE_LSB _u(2) -#define DMA_CH14_CTRL_TRIG_DATA_SIZE_ACCESS "RW" -#define DMA_CH14_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) -#define DMA_CH14_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1) -#define DMA_CH14_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) -// ----------------------------------------------------------------------------- -// Field : DMA_CH14_CTRL_TRIG_HIGH_PRIORITY -// Description : HIGH_PRIORITY gives a channel preferential treatment in issue -// scheduling: in each scheduling round, all high priority -// channels are considered first, and then only a single low -// priority channel, before returning to the high priority -// channels. -// -// This only affects the order in which the DMA schedules -// channels. The DMA's bus priority is not changed. If the DMA is -// not saturated then a low priority channel will see no loss of -// throughput. -#define DMA_CH14_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0) -#define DMA_CH14_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002) -#define DMA_CH14_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1) -#define DMA_CH14_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1) -#define DMA_CH14_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH14_CTRL_TRIG_EN -// Description : DMA Channel Enable. -// When 1, the channel will respond to triggering events, which -// will cause it to become BUSY and start transferring data. When -// 0, the channel will ignore triggers, stop issuing transfers, -// and pause the current transfer sequence (i.e. BUSY will remain -// high if already high) -#define DMA_CH14_CTRL_TRIG_EN_RESET _u(0x0) -#define DMA_CH14_CTRL_TRIG_EN_BITS _u(0x00000001) -#define DMA_CH14_CTRL_TRIG_EN_MSB _u(0) -#define DMA_CH14_CTRL_TRIG_EN_LSB _u(0) -#define DMA_CH14_CTRL_TRIG_EN_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH14_AL1_CTRL -// Description : Alias for channel 14 CTRL register -#define DMA_CH14_AL1_CTRL_OFFSET _u(0x00000390) -#define DMA_CH14_AL1_CTRL_BITS _u(0xffffffff) -#define DMA_CH14_AL1_CTRL_RESET "-" -#define DMA_CH14_AL1_CTRL_MSB _u(31) -#define DMA_CH14_AL1_CTRL_LSB _u(0) -#define DMA_CH14_AL1_CTRL_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH14_AL1_READ_ADDR -// Description : Alias for channel 14 READ_ADDR register -#define DMA_CH14_AL1_READ_ADDR_OFFSET _u(0x00000394) -#define DMA_CH14_AL1_READ_ADDR_BITS _u(0xffffffff) -#define DMA_CH14_AL1_READ_ADDR_RESET "-" -#define DMA_CH14_AL1_READ_ADDR_MSB _u(31) -#define DMA_CH14_AL1_READ_ADDR_LSB _u(0) -#define DMA_CH14_AL1_READ_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH14_AL1_WRITE_ADDR -// Description : Alias for channel 14 WRITE_ADDR register -#define DMA_CH14_AL1_WRITE_ADDR_OFFSET _u(0x00000398) -#define DMA_CH14_AL1_WRITE_ADDR_BITS _u(0xffffffff) -#define DMA_CH14_AL1_WRITE_ADDR_RESET "-" -#define DMA_CH14_AL1_WRITE_ADDR_MSB _u(31) -#define DMA_CH14_AL1_WRITE_ADDR_LSB _u(0) -#define DMA_CH14_AL1_WRITE_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH14_AL1_TRANS_COUNT_TRIG -// Description : Alias for channel 14 TRANS_COUNT register -// This is a trigger register (0xc). Writing a nonzero value will -// reload the channel counter and start the channel. -#define DMA_CH14_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x0000039c) -#define DMA_CH14_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff) -#define DMA_CH14_AL1_TRANS_COUNT_TRIG_RESET "-" -#define DMA_CH14_AL1_TRANS_COUNT_TRIG_MSB _u(31) -#define DMA_CH14_AL1_TRANS_COUNT_TRIG_LSB _u(0) -#define DMA_CH14_AL1_TRANS_COUNT_TRIG_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH14_AL2_CTRL -// Description : Alias for channel 14 CTRL register -#define DMA_CH14_AL2_CTRL_OFFSET _u(0x000003a0) -#define DMA_CH14_AL2_CTRL_BITS _u(0xffffffff) -#define DMA_CH14_AL2_CTRL_RESET "-" -#define DMA_CH14_AL2_CTRL_MSB _u(31) -#define DMA_CH14_AL2_CTRL_LSB _u(0) -#define DMA_CH14_AL2_CTRL_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH14_AL2_TRANS_COUNT -// Description : Alias for channel 14 TRANS_COUNT register -#define DMA_CH14_AL2_TRANS_COUNT_OFFSET _u(0x000003a4) -#define DMA_CH14_AL2_TRANS_COUNT_BITS _u(0xffffffff) -#define DMA_CH14_AL2_TRANS_COUNT_RESET "-" -#define DMA_CH14_AL2_TRANS_COUNT_MSB _u(31) -#define DMA_CH14_AL2_TRANS_COUNT_LSB _u(0) -#define DMA_CH14_AL2_TRANS_COUNT_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH14_AL2_READ_ADDR -// Description : Alias for channel 14 READ_ADDR register -#define DMA_CH14_AL2_READ_ADDR_OFFSET _u(0x000003a8) -#define DMA_CH14_AL2_READ_ADDR_BITS _u(0xffffffff) -#define DMA_CH14_AL2_READ_ADDR_RESET "-" -#define DMA_CH14_AL2_READ_ADDR_MSB _u(31) -#define DMA_CH14_AL2_READ_ADDR_LSB _u(0) -#define DMA_CH14_AL2_READ_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH14_AL2_WRITE_ADDR_TRIG -// Description : Alias for channel 14 WRITE_ADDR register -// This is a trigger register (0xc). Writing a nonzero value will -// reload the channel counter and start the channel. -#define DMA_CH14_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x000003ac) -#define DMA_CH14_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff) -#define DMA_CH14_AL2_WRITE_ADDR_TRIG_RESET "-" -#define DMA_CH14_AL2_WRITE_ADDR_TRIG_MSB _u(31) -#define DMA_CH14_AL2_WRITE_ADDR_TRIG_LSB _u(0) -#define DMA_CH14_AL2_WRITE_ADDR_TRIG_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH14_AL3_CTRL -// Description : Alias for channel 14 CTRL register -#define DMA_CH14_AL3_CTRL_OFFSET _u(0x000003b0) -#define DMA_CH14_AL3_CTRL_BITS _u(0xffffffff) -#define DMA_CH14_AL3_CTRL_RESET "-" -#define DMA_CH14_AL3_CTRL_MSB _u(31) -#define DMA_CH14_AL3_CTRL_LSB _u(0) -#define DMA_CH14_AL3_CTRL_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH14_AL3_WRITE_ADDR -// Description : Alias for channel 14 WRITE_ADDR register -#define DMA_CH14_AL3_WRITE_ADDR_OFFSET _u(0x000003b4) -#define DMA_CH14_AL3_WRITE_ADDR_BITS _u(0xffffffff) -#define DMA_CH14_AL3_WRITE_ADDR_RESET "-" -#define DMA_CH14_AL3_WRITE_ADDR_MSB _u(31) -#define DMA_CH14_AL3_WRITE_ADDR_LSB _u(0) -#define DMA_CH14_AL3_WRITE_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH14_AL3_TRANS_COUNT -// Description : Alias for channel 14 TRANS_COUNT register -#define DMA_CH14_AL3_TRANS_COUNT_OFFSET _u(0x000003b8) -#define DMA_CH14_AL3_TRANS_COUNT_BITS _u(0xffffffff) -#define DMA_CH14_AL3_TRANS_COUNT_RESET "-" -#define DMA_CH14_AL3_TRANS_COUNT_MSB _u(31) -#define DMA_CH14_AL3_TRANS_COUNT_LSB _u(0) -#define DMA_CH14_AL3_TRANS_COUNT_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH14_AL3_READ_ADDR_TRIG -// Description : Alias for channel 14 READ_ADDR register -// This is a trigger register (0xc). Writing a nonzero value will -// reload the channel counter and start the channel. -#define DMA_CH14_AL3_READ_ADDR_TRIG_OFFSET _u(0x000003bc) -#define DMA_CH14_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff) -#define DMA_CH14_AL3_READ_ADDR_TRIG_RESET "-" -#define DMA_CH14_AL3_READ_ADDR_TRIG_MSB _u(31) -#define DMA_CH14_AL3_READ_ADDR_TRIG_LSB _u(0) -#define DMA_CH14_AL3_READ_ADDR_TRIG_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH15_READ_ADDR -// Description : DMA Channel 15 Read Address pointer -// This register updates automatically each time a read completes. -// The current value is the next address to be read by this -// channel. -#define DMA_CH15_READ_ADDR_OFFSET _u(0x000003c0) -#define DMA_CH15_READ_ADDR_BITS _u(0xffffffff) -#define DMA_CH15_READ_ADDR_RESET _u(0x00000000) -#define DMA_CH15_READ_ADDR_MSB _u(31) -#define DMA_CH15_READ_ADDR_LSB _u(0) -#define DMA_CH15_READ_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH15_WRITE_ADDR -// Description : DMA Channel 15 Write Address pointer -// This register updates automatically each time a write -// completes. The current value is the next address to be written -// by this channel. -#define DMA_CH15_WRITE_ADDR_OFFSET _u(0x000003c4) -#define DMA_CH15_WRITE_ADDR_BITS _u(0xffffffff) -#define DMA_CH15_WRITE_ADDR_RESET _u(0x00000000) -#define DMA_CH15_WRITE_ADDR_MSB _u(31) -#define DMA_CH15_WRITE_ADDR_LSB _u(0) -#define DMA_CH15_WRITE_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH15_TRANS_COUNT -// Description : DMA Channel 15 Transfer Count -#define DMA_CH15_TRANS_COUNT_OFFSET _u(0x000003c8) -#define DMA_CH15_TRANS_COUNT_BITS _u(0xffffffff) -#define DMA_CH15_TRANS_COUNT_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : DMA_CH15_TRANS_COUNT_MODE -// Description : When MODE is 0x0, the transfer count decrements with each -// transfer until 0, and then the channel triggers the next -// channel indicated by CTRL_CHAIN_TO. -// -// When MODE is 0x1, the transfer count decrements with each -// transfer until 0, and then the channel re-triggers itself, in -// addition to the trigger indicated by CTRL_CHAIN_TO. This is -// useful for e.g. an endless ring-buffer DMA with periodic -// interrupts. -// -// When MODE is 0xf, the transfer count does not decrement. The -// DMA channel performs an endless sequence of transfers, never -// triggering other channels or raising interrupts, until an ABORT -// is raised. -// -// All other values are reserved. -// 0x0 -> NORMAL -// 0x1 -> TRIGGER_SELF -// 0xf -> ENDLESS -#define DMA_CH15_TRANS_COUNT_MODE_RESET _u(0x0) -#define DMA_CH15_TRANS_COUNT_MODE_BITS _u(0xf0000000) -#define DMA_CH15_TRANS_COUNT_MODE_MSB _u(31) -#define DMA_CH15_TRANS_COUNT_MODE_LSB _u(28) -#define DMA_CH15_TRANS_COUNT_MODE_ACCESS "RW" -#define DMA_CH15_TRANS_COUNT_MODE_VALUE_NORMAL _u(0x0) -#define DMA_CH15_TRANS_COUNT_MODE_VALUE_TRIGGER_SELF _u(0x1) -#define DMA_CH15_TRANS_COUNT_MODE_VALUE_ENDLESS _u(0xf) -// ----------------------------------------------------------------------------- -// Field : DMA_CH15_TRANS_COUNT_COUNT -// Description : 28-bit transfer count (256 million transfers maximum). -// -// Program the number of bus transfers a channel will perform -// before halting. Note that, if transfers are larger than one -// byte in size, this is not equal to the number of bytes -// transferred (see CTRL_DATA_SIZE). -// -// When the channel is active, reading this register shows the -// number of transfers remaining, updating automatically each time -// a write transfer completes. -// -// Writing this register sets the RELOAD value for the transfer -// counter. Each time this channel is triggered, the RELOAD value -// is copied into the live transfer counter. The channel can be -// started multiple times, and will perform the same number of -// transfers each time, as programmed by most recent write. -// -// The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT -// is used as a trigger, the written value is used immediately as -// the length of the new transfer sequence, as well as being -// written to RELOAD. -#define DMA_CH15_TRANS_COUNT_COUNT_RESET _u(0x0000000) -#define DMA_CH15_TRANS_COUNT_COUNT_BITS _u(0x0fffffff) -#define DMA_CH15_TRANS_COUNT_COUNT_MSB _u(27) -#define DMA_CH15_TRANS_COUNT_COUNT_LSB _u(0) -#define DMA_CH15_TRANS_COUNT_COUNT_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH15_CTRL_TRIG -// Description : DMA Channel 15 Control and Status -#define DMA_CH15_CTRL_TRIG_OFFSET _u(0x000003cc) -#define DMA_CH15_CTRL_TRIG_BITS _u(0xe7ffffff) -#define DMA_CH15_CTRL_TRIG_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : DMA_CH15_CTRL_TRIG_AHB_ERROR -// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel -// halts when it encounters any bus error, and always raises its -// channel IRQ flag. -#define DMA_CH15_CTRL_TRIG_AHB_ERROR_RESET _u(0x0) -#define DMA_CH15_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000) -#define DMA_CH15_CTRL_TRIG_AHB_ERROR_MSB _u(31) -#define DMA_CH15_CTRL_TRIG_AHB_ERROR_LSB _u(31) -#define DMA_CH15_CTRL_TRIG_AHB_ERROR_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : DMA_CH15_CTRL_TRIG_READ_ERROR -// Description : If 1, the channel received a read bus error. Write one to -// clear. -// READ_ADDR shows the approximate address where the bus error was -// encountered (will not be earlier, or more than 3 transfers -// later) -#define DMA_CH15_CTRL_TRIG_READ_ERROR_RESET _u(0x0) -#define DMA_CH15_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000) -#define DMA_CH15_CTRL_TRIG_READ_ERROR_MSB _u(30) -#define DMA_CH15_CTRL_TRIG_READ_ERROR_LSB _u(30) -#define DMA_CH15_CTRL_TRIG_READ_ERROR_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : DMA_CH15_CTRL_TRIG_WRITE_ERROR -// Description : If 1, the channel received a write bus error. Write one to -// clear. -// WRITE_ADDR shows the approximate address where the bus error -// was encountered (will not be earlier, or more than 5 transfers -// later) -#define DMA_CH15_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0) -#define DMA_CH15_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000) -#define DMA_CH15_CTRL_TRIG_WRITE_ERROR_MSB _u(29) -#define DMA_CH15_CTRL_TRIG_WRITE_ERROR_LSB _u(29) -#define DMA_CH15_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : DMA_CH15_CTRL_TRIG_BUSY -// Description : This flag goes high when the channel starts a new transfer -// sequence, and low when the last transfer of that sequence -// completes. Clearing EN while BUSY is high pauses the channel, -// and BUSY will stay high while paused. -// -// To terminate a sequence early (and clear the BUSY flag), see -// CHAN_ABORT. -#define DMA_CH15_CTRL_TRIG_BUSY_RESET _u(0x0) -#define DMA_CH15_CTRL_TRIG_BUSY_BITS _u(0x04000000) -#define DMA_CH15_CTRL_TRIG_BUSY_MSB _u(26) -#define DMA_CH15_CTRL_TRIG_BUSY_LSB _u(26) -#define DMA_CH15_CTRL_TRIG_BUSY_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : DMA_CH15_CTRL_TRIG_SNIFF_EN -// Description : If 1, this channel's data transfers are visible to the sniff -// hardware, and each transfer will advance the state of the -// checksum. This only applies if the sniff hardware is enabled, -// and has this channel selected. -// -// This allows checksum to be enabled or disabled on a per- -// control- block basis. -#define DMA_CH15_CTRL_TRIG_SNIFF_EN_RESET _u(0x0) -#define DMA_CH15_CTRL_TRIG_SNIFF_EN_BITS _u(0x02000000) -#define DMA_CH15_CTRL_TRIG_SNIFF_EN_MSB _u(25) -#define DMA_CH15_CTRL_TRIG_SNIFF_EN_LSB _u(25) -#define DMA_CH15_CTRL_TRIG_SNIFF_EN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH15_CTRL_TRIG_BSWAP -// Description : Apply byte-swap transformation to DMA data. -// For byte data, this has no effect. For halfword data, the two -// bytes of each halfword are swapped. For word data, the four -// bytes of each word are swapped to reverse order. -#define DMA_CH15_CTRL_TRIG_BSWAP_RESET _u(0x0) -#define DMA_CH15_CTRL_TRIG_BSWAP_BITS _u(0x01000000) -#define DMA_CH15_CTRL_TRIG_BSWAP_MSB _u(24) -#define DMA_CH15_CTRL_TRIG_BSWAP_LSB _u(24) -#define DMA_CH15_CTRL_TRIG_BSWAP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH15_CTRL_TRIG_IRQ_QUIET -// Description : In QUIET mode, the channel does not generate IRQs at the end of -// every transfer block. Instead, an IRQ is raised when NULL is -// written to a trigger register, indicating the end of a control -// block chain. -// -// This reduces the number of interrupts to be serviced by the CPU -// when transferring a DMA chain of many small control blocks. -#define DMA_CH15_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0) -#define DMA_CH15_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00800000) -#define DMA_CH15_CTRL_TRIG_IRQ_QUIET_MSB _u(23) -#define DMA_CH15_CTRL_TRIG_IRQ_QUIET_LSB _u(23) -#define DMA_CH15_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH15_CTRL_TRIG_TREQ_SEL -// Description : Select a Transfer Request signal. -// The channel uses the transfer request signal to pace its data -// transfer rate. Sources for TREQ signals are internal (TIMERS) -// or external (DREQ, a Data Request from the system). -// 0x0 to 0x3a -> select DREQ n as TREQ -// 0x3b -> Select Timer 0 as TREQ -// 0x3c -> Select Timer 1 as TREQ -// 0x3d -> Select Timer 2 as TREQ (Optional) -// 0x3e -> Select Timer 3 as TREQ (Optional) -// 0x3f -> Permanent request, for unpaced transfers. -#define DMA_CH15_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) -#define DMA_CH15_CTRL_TRIG_TREQ_SEL_BITS _u(0x007e0000) -#define DMA_CH15_CTRL_TRIG_TREQ_SEL_MSB _u(22) -#define DMA_CH15_CTRL_TRIG_TREQ_SEL_LSB _u(17) -#define DMA_CH15_CTRL_TRIG_TREQ_SEL_ACCESS "RW" -#define DMA_CH15_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) -#define DMA_CH15_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) -#define DMA_CH15_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) -#define DMA_CH15_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) -#define DMA_CH15_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) -// ----------------------------------------------------------------------------- -// Field : DMA_CH15_CTRL_TRIG_CHAIN_TO -// Description : When this channel completes, it will trigger the channel -// indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this -// channel)_. -// -// Note this field resets to 0, so channels 1 and above will chain -// to channel 0 by default. Set this field to avoid this -// behaviour. -#define DMA_CH15_CTRL_TRIG_CHAIN_TO_RESET _u(0x0) -#define DMA_CH15_CTRL_TRIG_CHAIN_TO_BITS _u(0x0001e000) -#define DMA_CH15_CTRL_TRIG_CHAIN_TO_MSB _u(16) -#define DMA_CH15_CTRL_TRIG_CHAIN_TO_LSB _u(13) -#define DMA_CH15_CTRL_TRIG_CHAIN_TO_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH15_CTRL_TRIG_RING_SEL -// Description : Select whether RING_SIZE applies to read or write addresses. -// If 0, read addresses are wrapped on a (1 << RING_SIZE) -// boundary. If 1, write addresses are wrapped. -#define DMA_CH15_CTRL_TRIG_RING_SEL_RESET _u(0x0) -#define DMA_CH15_CTRL_TRIG_RING_SEL_BITS _u(0x00001000) -#define DMA_CH15_CTRL_TRIG_RING_SEL_MSB _u(12) -#define DMA_CH15_CTRL_TRIG_RING_SEL_LSB _u(12) -#define DMA_CH15_CTRL_TRIG_RING_SEL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH15_CTRL_TRIG_RING_SIZE -// Description : Size of address wrap region. If 0, don't wrap. For values n > -// 0, only the lower n bits of the address will change. This wraps -// the address on a (1 << n) byte boundary, facilitating access to -// naturally-aligned ring buffers. -// -// Ring sizes between 2 and 32768 bytes are possible. This can -// apply to either read or write addresses, based on value of -// RING_SEL. -// 0x0 -> RING_NONE -#define DMA_CH15_CTRL_TRIG_RING_SIZE_RESET _u(0x0) -#define DMA_CH15_CTRL_TRIG_RING_SIZE_BITS _u(0x00000f00) -#define DMA_CH15_CTRL_TRIG_RING_SIZE_MSB _u(11) -#define DMA_CH15_CTRL_TRIG_RING_SIZE_LSB _u(8) -#define DMA_CH15_CTRL_TRIG_RING_SIZE_ACCESS "RW" -#define DMA_CH15_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0) -// ----------------------------------------------------------------------------- -// Field : DMA_CH15_CTRL_TRIG_INCR_WRITE_REV -// Description : If 1, and INCR_WRITE is 1, the write address is decremented -// rather than incremented with each transfer. -// -// If 1, and INCR_WRITE is 0, this otherwise-unused combination -// causes the write address to be incremented by twice the -// transfer size, i.e. skipping over alternate addresses. -#define DMA_CH15_CTRL_TRIG_INCR_WRITE_REV_RESET _u(0x0) -#define DMA_CH15_CTRL_TRIG_INCR_WRITE_REV_BITS _u(0x00000080) -#define DMA_CH15_CTRL_TRIG_INCR_WRITE_REV_MSB _u(7) -#define DMA_CH15_CTRL_TRIG_INCR_WRITE_REV_LSB _u(7) -#define DMA_CH15_CTRL_TRIG_INCR_WRITE_REV_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH15_CTRL_TRIG_INCR_WRITE -// Description : If 1, the write address increments with each transfer. If 0, -// each write is directed to the same, initial address. -// -// Generally this should be disabled for memory-to-peripheral -// transfers. -#define DMA_CH15_CTRL_TRIG_INCR_WRITE_RESET _u(0x0) -#define DMA_CH15_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000040) -#define DMA_CH15_CTRL_TRIG_INCR_WRITE_MSB _u(6) -#define DMA_CH15_CTRL_TRIG_INCR_WRITE_LSB _u(6) -#define DMA_CH15_CTRL_TRIG_INCR_WRITE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH15_CTRL_TRIG_INCR_READ_REV -// Description : If 1, and INCR_READ is 1, the read address is decremented -// rather than incremented with each transfer. -// -// If 1, and INCR_READ is 0, this otherwise-unused combination -// causes the read address to be incremented by twice the transfer -// size, i.e. skipping over alternate addresses. -#define DMA_CH15_CTRL_TRIG_INCR_READ_REV_RESET _u(0x0) -#define DMA_CH15_CTRL_TRIG_INCR_READ_REV_BITS _u(0x00000020) -#define DMA_CH15_CTRL_TRIG_INCR_READ_REV_MSB _u(5) -#define DMA_CH15_CTRL_TRIG_INCR_READ_REV_LSB _u(5) -#define DMA_CH15_CTRL_TRIG_INCR_READ_REV_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH15_CTRL_TRIG_INCR_READ -// Description : If 1, the read address increments with each transfer. If 0, -// each read is directed to the same, initial address. -// -// Generally this should be disabled for peripheral-to-memory -// transfers. -#define DMA_CH15_CTRL_TRIG_INCR_READ_RESET _u(0x0) -#define DMA_CH15_CTRL_TRIG_INCR_READ_BITS _u(0x00000010) -#define DMA_CH15_CTRL_TRIG_INCR_READ_MSB _u(4) -#define DMA_CH15_CTRL_TRIG_INCR_READ_LSB _u(4) -#define DMA_CH15_CTRL_TRIG_INCR_READ_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH15_CTRL_TRIG_DATA_SIZE -// Description : Set the size of each bus transfer (byte/halfword/word). -// READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) -// with each transfer. -// 0x0 -> SIZE_BYTE -// 0x1 -> SIZE_HALFWORD -// 0x2 -> SIZE_WORD -#define DMA_CH15_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) -#define DMA_CH15_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) -#define DMA_CH15_CTRL_TRIG_DATA_SIZE_MSB _u(3) -#define DMA_CH15_CTRL_TRIG_DATA_SIZE_LSB _u(2) -#define DMA_CH15_CTRL_TRIG_DATA_SIZE_ACCESS "RW" -#define DMA_CH15_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) -#define DMA_CH15_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1) -#define DMA_CH15_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) -// ----------------------------------------------------------------------------- -// Field : DMA_CH15_CTRL_TRIG_HIGH_PRIORITY -// Description : HIGH_PRIORITY gives a channel preferential treatment in issue -// scheduling: in each scheduling round, all high priority -// channels are considered first, and then only a single low -// priority channel, before returning to the high priority -// channels. -// -// This only affects the order in which the DMA schedules -// channels. The DMA's bus priority is not changed. If the DMA is -// not saturated then a low priority channel will see no loss of -// throughput. -#define DMA_CH15_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0) -#define DMA_CH15_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002) -#define DMA_CH15_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1) -#define DMA_CH15_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1) -#define DMA_CH15_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_CH15_CTRL_TRIG_EN -// Description : DMA Channel Enable. -// When 1, the channel will respond to triggering events, which -// will cause it to become BUSY and start transferring data. When -// 0, the channel will ignore triggers, stop issuing transfers, -// and pause the current transfer sequence (i.e. BUSY will remain -// high if already high) -#define DMA_CH15_CTRL_TRIG_EN_RESET _u(0x0) -#define DMA_CH15_CTRL_TRIG_EN_BITS _u(0x00000001) -#define DMA_CH15_CTRL_TRIG_EN_MSB _u(0) -#define DMA_CH15_CTRL_TRIG_EN_LSB _u(0) -#define DMA_CH15_CTRL_TRIG_EN_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH15_AL1_CTRL -// Description : Alias for channel 15 CTRL register -#define DMA_CH15_AL1_CTRL_OFFSET _u(0x000003d0) -#define DMA_CH15_AL1_CTRL_BITS _u(0xffffffff) -#define DMA_CH15_AL1_CTRL_RESET "-" -#define DMA_CH15_AL1_CTRL_MSB _u(31) -#define DMA_CH15_AL1_CTRL_LSB _u(0) -#define DMA_CH15_AL1_CTRL_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH15_AL1_READ_ADDR -// Description : Alias for channel 15 READ_ADDR register -#define DMA_CH15_AL1_READ_ADDR_OFFSET _u(0x000003d4) -#define DMA_CH15_AL1_READ_ADDR_BITS _u(0xffffffff) -#define DMA_CH15_AL1_READ_ADDR_RESET "-" -#define DMA_CH15_AL1_READ_ADDR_MSB _u(31) -#define DMA_CH15_AL1_READ_ADDR_LSB _u(0) -#define DMA_CH15_AL1_READ_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH15_AL1_WRITE_ADDR -// Description : Alias for channel 15 WRITE_ADDR register -#define DMA_CH15_AL1_WRITE_ADDR_OFFSET _u(0x000003d8) -#define DMA_CH15_AL1_WRITE_ADDR_BITS _u(0xffffffff) -#define DMA_CH15_AL1_WRITE_ADDR_RESET "-" -#define DMA_CH15_AL1_WRITE_ADDR_MSB _u(31) -#define DMA_CH15_AL1_WRITE_ADDR_LSB _u(0) -#define DMA_CH15_AL1_WRITE_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH15_AL1_TRANS_COUNT_TRIG -// Description : Alias for channel 15 TRANS_COUNT register -// This is a trigger register (0xc). Writing a nonzero value will -// reload the channel counter and start the channel. -#define DMA_CH15_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x000003dc) -#define DMA_CH15_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff) -#define DMA_CH15_AL1_TRANS_COUNT_TRIG_RESET "-" -#define DMA_CH15_AL1_TRANS_COUNT_TRIG_MSB _u(31) -#define DMA_CH15_AL1_TRANS_COUNT_TRIG_LSB _u(0) -#define DMA_CH15_AL1_TRANS_COUNT_TRIG_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH15_AL2_CTRL -// Description : Alias for channel 15 CTRL register -#define DMA_CH15_AL2_CTRL_OFFSET _u(0x000003e0) -#define DMA_CH15_AL2_CTRL_BITS _u(0xffffffff) -#define DMA_CH15_AL2_CTRL_RESET "-" -#define DMA_CH15_AL2_CTRL_MSB _u(31) -#define DMA_CH15_AL2_CTRL_LSB _u(0) -#define DMA_CH15_AL2_CTRL_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH15_AL2_TRANS_COUNT -// Description : Alias for channel 15 TRANS_COUNT register -#define DMA_CH15_AL2_TRANS_COUNT_OFFSET _u(0x000003e4) -#define DMA_CH15_AL2_TRANS_COUNT_BITS _u(0xffffffff) -#define DMA_CH15_AL2_TRANS_COUNT_RESET "-" -#define DMA_CH15_AL2_TRANS_COUNT_MSB _u(31) -#define DMA_CH15_AL2_TRANS_COUNT_LSB _u(0) -#define DMA_CH15_AL2_TRANS_COUNT_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH15_AL2_READ_ADDR -// Description : Alias for channel 15 READ_ADDR register -#define DMA_CH15_AL2_READ_ADDR_OFFSET _u(0x000003e8) -#define DMA_CH15_AL2_READ_ADDR_BITS _u(0xffffffff) -#define DMA_CH15_AL2_READ_ADDR_RESET "-" -#define DMA_CH15_AL2_READ_ADDR_MSB _u(31) -#define DMA_CH15_AL2_READ_ADDR_LSB _u(0) -#define DMA_CH15_AL2_READ_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH15_AL2_WRITE_ADDR_TRIG -// Description : Alias for channel 15 WRITE_ADDR register -// This is a trigger register (0xc). Writing a nonzero value will -// reload the channel counter and start the channel. -#define DMA_CH15_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x000003ec) -#define DMA_CH15_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff) -#define DMA_CH15_AL2_WRITE_ADDR_TRIG_RESET "-" -#define DMA_CH15_AL2_WRITE_ADDR_TRIG_MSB _u(31) -#define DMA_CH15_AL2_WRITE_ADDR_TRIG_LSB _u(0) -#define DMA_CH15_AL2_WRITE_ADDR_TRIG_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH15_AL3_CTRL -// Description : Alias for channel 15 CTRL register -#define DMA_CH15_AL3_CTRL_OFFSET _u(0x000003f0) -#define DMA_CH15_AL3_CTRL_BITS _u(0xffffffff) -#define DMA_CH15_AL3_CTRL_RESET "-" -#define DMA_CH15_AL3_CTRL_MSB _u(31) -#define DMA_CH15_AL3_CTRL_LSB _u(0) -#define DMA_CH15_AL3_CTRL_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH15_AL3_WRITE_ADDR -// Description : Alias for channel 15 WRITE_ADDR register -#define DMA_CH15_AL3_WRITE_ADDR_OFFSET _u(0x000003f4) -#define DMA_CH15_AL3_WRITE_ADDR_BITS _u(0xffffffff) -#define DMA_CH15_AL3_WRITE_ADDR_RESET "-" -#define DMA_CH15_AL3_WRITE_ADDR_MSB _u(31) -#define DMA_CH15_AL3_WRITE_ADDR_LSB _u(0) -#define DMA_CH15_AL3_WRITE_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH15_AL3_TRANS_COUNT -// Description : Alias for channel 15 TRANS_COUNT register -#define DMA_CH15_AL3_TRANS_COUNT_OFFSET _u(0x000003f8) -#define DMA_CH15_AL3_TRANS_COUNT_BITS _u(0xffffffff) -#define DMA_CH15_AL3_TRANS_COUNT_RESET "-" -#define DMA_CH15_AL3_TRANS_COUNT_MSB _u(31) -#define DMA_CH15_AL3_TRANS_COUNT_LSB _u(0) -#define DMA_CH15_AL3_TRANS_COUNT_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH15_AL3_READ_ADDR_TRIG -// Description : Alias for channel 15 READ_ADDR register -// This is a trigger register (0xc). Writing a nonzero value will -// reload the channel counter and start the channel. -#define DMA_CH15_AL3_READ_ADDR_TRIG_OFFSET _u(0x000003fc) -#define DMA_CH15_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff) -#define DMA_CH15_AL3_READ_ADDR_TRIG_RESET "-" -#define DMA_CH15_AL3_READ_ADDR_TRIG_MSB _u(31) -#define DMA_CH15_AL3_READ_ADDR_TRIG_LSB _u(0) -#define DMA_CH15_AL3_READ_ADDR_TRIG_ACCESS "RW" -// ============================================================================= -// Register : DMA_INTR -// Description : Interrupt Status (raw) -// Raw interrupt status for DMA Channels 0..15. Bit n corresponds -// to channel n. Ignores any masking or forcing. Channel -// interrupts can be cleared by writing a bit mask to INTR or -// INTS0/1/2/3. -// -// Channel interrupts can be routed to either of four system-level -// IRQs based on INTE0, INTE1, INTE2 and INTE3. -// -// The multiple system-level interrupts might be used to allow -// NVIC IRQ preemption for more time-critical channels, to spread -// IRQ load across different cores, or to target IRQs to different -// security domains. -// -// It is also valid to ignore the multiple IRQs, and just use -// INTE0/INTS0/IRQ 0. -// -// If this register is accessed at a security/privilege level less -// than that of a given channel (as defined by that channel's -// SECCFG_CHx register), then that channel's interrupt status will -// read as 0, ignore writes. -#define DMA_INTR_OFFSET _u(0x00000400) -#define DMA_INTR_BITS _u(0x0000ffff) -#define DMA_INTR_RESET _u(0x00000000) -#define DMA_INTR_MSB _u(15) -#define DMA_INTR_LSB _u(0) -#define DMA_INTR_ACCESS "WC" -// ============================================================================= -// Register : DMA_INTE0 -// Description : Interrupt Enables for IRQ 0 -// Set bit n to pass interrupts from channel n to DMA IRQ 0. -// -// Note this bit has no effect if the channel security/privilege -// level, defined by SECCFG_CHx, is greater than the IRQ -// security/privilege defined by SECCFG_IRQ0. -#define DMA_INTE0_OFFSET _u(0x00000404) -#define DMA_INTE0_BITS _u(0x0000ffff) -#define DMA_INTE0_RESET _u(0x00000000) -#define DMA_INTE0_MSB _u(15) -#define DMA_INTE0_LSB _u(0) -#define DMA_INTE0_ACCESS "RW" -// ============================================================================= -// Register : DMA_INTF0 -// Description : Force Interrupts -// Write 1s to force the corresponding bits in INTS0. The -// interrupt remains asserted until INTF0 is cleared. -#define DMA_INTF0_OFFSET _u(0x00000408) -#define DMA_INTF0_BITS _u(0x0000ffff) -#define DMA_INTF0_RESET _u(0x00000000) -#define DMA_INTF0_MSB _u(15) -#define DMA_INTF0_LSB _u(0) -#define DMA_INTF0_ACCESS "RW" -// ============================================================================= -// Register : DMA_INTS0 -// Description : Interrupt Status for IRQ 0 -// Indicates active channel interrupt requests which are currently -// causing IRQ 0 to be asserted. -// Channel interrupts can be cleared by writing a bit mask here. -// -// Channels with a security/privilege (SECCFG_CHx) greater -// SECCFG_IRQ0) read as 0 in this register, and ignore writes. -#define DMA_INTS0_OFFSET _u(0x0000040c) -#define DMA_INTS0_BITS _u(0x0000ffff) -#define DMA_INTS0_RESET _u(0x00000000) -#define DMA_INTS0_MSB _u(15) -#define DMA_INTS0_LSB _u(0) -#define DMA_INTS0_ACCESS "WC" -// ============================================================================= -// Register : DMA_INTE1 -// Description : Interrupt Enables for IRQ 1 -// Set bit n to pass interrupts from channel n to DMA IRQ 1. -// -// Note this bit has no effect if the channel security/privilege -// level, defined by SECCFG_CHx, is greater than the IRQ -// security/privilege defined by SECCFG_IRQ1. -#define DMA_INTE1_OFFSET _u(0x00000414) -#define DMA_INTE1_BITS _u(0x0000ffff) -#define DMA_INTE1_RESET _u(0x00000000) -#define DMA_INTE1_MSB _u(15) -#define DMA_INTE1_LSB _u(0) -#define DMA_INTE1_ACCESS "RW" -// ============================================================================= -// Register : DMA_INTF1 -// Description : Force Interrupts -// Write 1s to force the corresponding bits in INTS1. The -// interrupt remains asserted until INTF1 is cleared. -#define DMA_INTF1_OFFSET _u(0x00000418) -#define DMA_INTF1_BITS _u(0x0000ffff) -#define DMA_INTF1_RESET _u(0x00000000) -#define DMA_INTF1_MSB _u(15) -#define DMA_INTF1_LSB _u(0) -#define DMA_INTF1_ACCESS "RW" -// ============================================================================= -// Register : DMA_INTS1 -// Description : Interrupt Status for IRQ 1 -// Indicates active channel interrupt requests which are currently -// causing IRQ 1 to be asserted. -// Channel interrupts can be cleared by writing a bit mask here. -// -// Channels with a security/privilege (SECCFG_CHx) greater -// SECCFG_IRQ1) read as 0 in this register, and ignore writes. -#define DMA_INTS1_OFFSET _u(0x0000041c) -#define DMA_INTS1_BITS _u(0x0000ffff) -#define DMA_INTS1_RESET _u(0x00000000) -#define DMA_INTS1_MSB _u(15) -#define DMA_INTS1_LSB _u(0) -#define DMA_INTS1_ACCESS "WC" -// ============================================================================= -// Register : DMA_INTE2 -// Description : Interrupt Enables for IRQ 2 -// Set bit n to pass interrupts from channel n to DMA IRQ 2. -// -// Note this bit has no effect if the channel security/privilege -// level, defined by SECCFG_CHx, is greater than the IRQ -// security/privilege defined by SECCFG_IRQ2. -#define DMA_INTE2_OFFSET _u(0x00000424) -#define DMA_INTE2_BITS _u(0x0000ffff) -#define DMA_INTE2_RESET _u(0x00000000) -#define DMA_INTE2_MSB _u(15) -#define DMA_INTE2_LSB _u(0) -#define DMA_INTE2_ACCESS "RW" -// ============================================================================= -// Register : DMA_INTF2 -// Description : Force Interrupts -// Write 1s to force the corresponding bits in INTS2. The -// interrupt remains asserted until INTF2 is cleared. -#define DMA_INTF2_OFFSET _u(0x00000428) -#define DMA_INTF2_BITS _u(0x0000ffff) -#define DMA_INTF2_RESET _u(0x00000000) -#define DMA_INTF2_MSB _u(15) -#define DMA_INTF2_LSB _u(0) -#define DMA_INTF2_ACCESS "RW" -// ============================================================================= -// Register : DMA_INTS2 -// Description : Interrupt Status for IRQ 2 -// Indicates active channel interrupt requests which are currently -// causing IRQ 2 to be asserted. -// Channel interrupts can be cleared by writing a bit mask here. -// -// Channels with a security/privilege (SECCFG_CHx) greater -// SECCFG_IRQ2) read as 0 in this register, and ignore writes. -#define DMA_INTS2_OFFSET _u(0x0000042c) -#define DMA_INTS2_BITS _u(0x0000ffff) -#define DMA_INTS2_RESET _u(0x00000000) -#define DMA_INTS2_MSB _u(15) -#define DMA_INTS2_LSB _u(0) -#define DMA_INTS2_ACCESS "WC" -// ============================================================================= -// Register : DMA_INTE3 -// Description : Interrupt Enables for IRQ 3 -// Set bit n to pass interrupts from channel n to DMA IRQ 3. -// -// Note this bit has no effect if the channel security/privilege -// level, defined by SECCFG_CHx, is greater than the IRQ -// security/privilege defined by SECCFG_IRQ3. -#define DMA_INTE3_OFFSET _u(0x00000434) -#define DMA_INTE3_BITS _u(0x0000ffff) -#define DMA_INTE3_RESET _u(0x00000000) -#define DMA_INTE3_MSB _u(15) -#define DMA_INTE3_LSB _u(0) -#define DMA_INTE3_ACCESS "RW" -// ============================================================================= -// Register : DMA_INTF3 -// Description : Force Interrupts -// Write 1s to force the corresponding bits in INTS3. The -// interrupt remains asserted until INTF3 is cleared. -#define DMA_INTF3_OFFSET _u(0x00000438) -#define DMA_INTF3_BITS _u(0x0000ffff) -#define DMA_INTF3_RESET _u(0x00000000) -#define DMA_INTF3_MSB _u(15) -#define DMA_INTF3_LSB _u(0) -#define DMA_INTF3_ACCESS "RW" -// ============================================================================= -// Register : DMA_INTS3 -// Description : Interrupt Status for IRQ 3 -// Indicates active channel interrupt requests which are currently -// causing IRQ 3 to be asserted. -// Channel interrupts can be cleared by writing a bit mask here. -// -// Channels with a security/privilege (SECCFG_CHx) greater -// SECCFG_IRQ3) read as 0 in this register, and ignore writes. -#define DMA_INTS3_OFFSET _u(0x0000043c) -#define DMA_INTS3_BITS _u(0x0000ffff) -#define DMA_INTS3_RESET _u(0x00000000) -#define DMA_INTS3_MSB _u(15) -#define DMA_INTS3_LSB _u(0) -#define DMA_INTS3_ACCESS "WC" -// ============================================================================= -// Register : DMA_TIMER0 -// Description : Pacing (X/Y) fractional timer -// The pacing timer produces TREQ assertions at a rate set by -// ((X/Y) * sys_clk). This equation is evaluated every sys_clk -// cycles and therefore can only generate TREQs at a rate of 1 per -// sys_clk (i.e. permanent TREQ) or less. -#define DMA_TIMER0_OFFSET _u(0x00000440) -#define DMA_TIMER0_BITS _u(0xffffffff) -#define DMA_TIMER0_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : DMA_TIMER0_X -// Description : Pacing Timer Dividend. Specifies the X value for the (X/Y) -// fractional timer. -#define DMA_TIMER0_X_RESET _u(0x0000) -#define DMA_TIMER0_X_BITS _u(0xffff0000) -#define DMA_TIMER0_X_MSB _u(31) -#define DMA_TIMER0_X_LSB _u(16) -#define DMA_TIMER0_X_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_TIMER0_Y -// Description : Pacing Timer Divisor. Specifies the Y value for the (X/Y) -// fractional timer. -#define DMA_TIMER0_Y_RESET _u(0x0000) -#define DMA_TIMER0_Y_BITS _u(0x0000ffff) -#define DMA_TIMER0_Y_MSB _u(15) -#define DMA_TIMER0_Y_LSB _u(0) -#define DMA_TIMER0_Y_ACCESS "RW" -// ============================================================================= -// Register : DMA_TIMER1 -// Description : Pacing (X/Y) fractional timer -// The pacing timer produces TREQ assertions at a rate set by -// ((X/Y) * sys_clk). This equation is evaluated every sys_clk -// cycles and therefore can only generate TREQs at a rate of 1 per -// sys_clk (i.e. permanent TREQ) or less. -#define DMA_TIMER1_OFFSET _u(0x00000444) -#define DMA_TIMER1_BITS _u(0xffffffff) -#define DMA_TIMER1_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : DMA_TIMER1_X -// Description : Pacing Timer Dividend. Specifies the X value for the (X/Y) -// fractional timer. -#define DMA_TIMER1_X_RESET _u(0x0000) -#define DMA_TIMER1_X_BITS _u(0xffff0000) -#define DMA_TIMER1_X_MSB _u(31) -#define DMA_TIMER1_X_LSB _u(16) -#define DMA_TIMER1_X_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_TIMER1_Y -// Description : Pacing Timer Divisor. Specifies the Y value for the (X/Y) -// fractional timer. -#define DMA_TIMER1_Y_RESET _u(0x0000) -#define DMA_TIMER1_Y_BITS _u(0x0000ffff) -#define DMA_TIMER1_Y_MSB _u(15) -#define DMA_TIMER1_Y_LSB _u(0) -#define DMA_TIMER1_Y_ACCESS "RW" -// ============================================================================= -// Register : DMA_TIMER2 -// Description : Pacing (X/Y) fractional timer -// The pacing timer produces TREQ assertions at a rate set by -// ((X/Y) * sys_clk). This equation is evaluated every sys_clk -// cycles and therefore can only generate TREQs at a rate of 1 per -// sys_clk (i.e. permanent TREQ) or less. -#define DMA_TIMER2_OFFSET _u(0x00000448) -#define DMA_TIMER2_BITS _u(0xffffffff) -#define DMA_TIMER2_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : DMA_TIMER2_X -// Description : Pacing Timer Dividend. Specifies the X value for the (X/Y) -// fractional timer. -#define DMA_TIMER2_X_RESET _u(0x0000) -#define DMA_TIMER2_X_BITS _u(0xffff0000) -#define DMA_TIMER2_X_MSB _u(31) -#define DMA_TIMER2_X_LSB _u(16) -#define DMA_TIMER2_X_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_TIMER2_Y -// Description : Pacing Timer Divisor. Specifies the Y value for the (X/Y) -// fractional timer. -#define DMA_TIMER2_Y_RESET _u(0x0000) -#define DMA_TIMER2_Y_BITS _u(0x0000ffff) -#define DMA_TIMER2_Y_MSB _u(15) -#define DMA_TIMER2_Y_LSB _u(0) -#define DMA_TIMER2_Y_ACCESS "RW" -// ============================================================================= -// Register : DMA_TIMER3 -// Description : Pacing (X/Y) fractional timer -// The pacing timer produces TREQ assertions at a rate set by -// ((X/Y) * sys_clk). This equation is evaluated every sys_clk -// cycles and therefore can only generate TREQs at a rate of 1 per -// sys_clk (i.e. permanent TREQ) or less. -#define DMA_TIMER3_OFFSET _u(0x0000044c) -#define DMA_TIMER3_BITS _u(0xffffffff) -#define DMA_TIMER3_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : DMA_TIMER3_X -// Description : Pacing Timer Dividend. Specifies the X value for the (X/Y) -// fractional timer. -#define DMA_TIMER3_X_RESET _u(0x0000) -#define DMA_TIMER3_X_BITS _u(0xffff0000) -#define DMA_TIMER3_X_MSB _u(31) -#define DMA_TIMER3_X_LSB _u(16) -#define DMA_TIMER3_X_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_TIMER3_Y -// Description : Pacing Timer Divisor. Specifies the Y value for the (X/Y) -// fractional timer. -#define DMA_TIMER3_Y_RESET _u(0x0000) -#define DMA_TIMER3_Y_BITS _u(0x0000ffff) -#define DMA_TIMER3_Y_MSB _u(15) -#define DMA_TIMER3_Y_LSB _u(0) -#define DMA_TIMER3_Y_ACCESS "RW" -// ============================================================================= -// Register : DMA_MULTI_CHAN_TRIGGER -// Description : Trigger one or more channels simultaneously -// Each bit in this register corresponds to a DMA channel. Writing -// a 1 to the relevant bit is the same as writing to that -// channel's trigger register; the channel will start if it is -// currently enabled and not already busy. -#define DMA_MULTI_CHAN_TRIGGER_OFFSET _u(0x00000450) -#define DMA_MULTI_CHAN_TRIGGER_BITS _u(0x0000ffff) -#define DMA_MULTI_CHAN_TRIGGER_RESET _u(0x00000000) -#define DMA_MULTI_CHAN_TRIGGER_MSB _u(15) -#define DMA_MULTI_CHAN_TRIGGER_LSB _u(0) -#define DMA_MULTI_CHAN_TRIGGER_ACCESS "SC" -// ============================================================================= -// Register : DMA_SNIFF_CTRL -// Description : Sniffer Control -#define DMA_SNIFF_CTRL_OFFSET _u(0x00000454) -#define DMA_SNIFF_CTRL_BITS _u(0x00000fff) -#define DMA_SNIFF_CTRL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : DMA_SNIFF_CTRL_OUT_INV -// Description : If set, the result appears inverted (bitwise complement) when -// read. This does not affect the way the checksum is calculated; -// the result is transformed on-the-fly between the result -// register and the bus. -#define DMA_SNIFF_CTRL_OUT_INV_RESET _u(0x0) -#define DMA_SNIFF_CTRL_OUT_INV_BITS _u(0x00000800) -#define DMA_SNIFF_CTRL_OUT_INV_MSB _u(11) -#define DMA_SNIFF_CTRL_OUT_INV_LSB _u(11) -#define DMA_SNIFF_CTRL_OUT_INV_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_SNIFF_CTRL_OUT_REV -// Description : If set, the result appears bit-reversed when read. This does -// not affect the way the checksum is calculated; the result is -// transformed on-the-fly between the result register and the bus. -#define DMA_SNIFF_CTRL_OUT_REV_RESET _u(0x0) -#define DMA_SNIFF_CTRL_OUT_REV_BITS _u(0x00000400) -#define DMA_SNIFF_CTRL_OUT_REV_MSB _u(10) -#define DMA_SNIFF_CTRL_OUT_REV_LSB _u(10) -#define DMA_SNIFF_CTRL_OUT_REV_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_SNIFF_CTRL_BSWAP -// Description : Locally perform a byte reverse on the sniffed data, before -// feeding into checksum. -// -// Note that the sniff hardware is downstream of the DMA channel -// byteswap performed in the read master: if channel CTRL_BSWAP -// and SNIFF_CTRL_BSWAP are both enabled, their effects cancel -// from the sniffer's point of view. -#define DMA_SNIFF_CTRL_BSWAP_RESET _u(0x0) -#define DMA_SNIFF_CTRL_BSWAP_BITS _u(0x00000200) -#define DMA_SNIFF_CTRL_BSWAP_MSB _u(9) -#define DMA_SNIFF_CTRL_BSWAP_LSB _u(9) -#define DMA_SNIFF_CTRL_BSWAP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_SNIFF_CTRL_CALC -// 0x0 -> Calculate a CRC-32 (IEEE802.3 polynomial) -// 0x1 -> Calculate a CRC-32 (IEEE802.3 polynomial) with bit reversed data -// 0x2 -> Calculate a CRC-16-CCITT -// 0x3 -> Calculate a CRC-16-CCITT with bit reversed data -// 0xe -> XOR reduction over all data. == 1 if the total 1 population count is odd. -// 0xf -> Calculate a simple 32-bit checksum (addition with a 32 bit accumulator) -#define DMA_SNIFF_CTRL_CALC_RESET _u(0x0) -#define DMA_SNIFF_CTRL_CALC_BITS _u(0x000001e0) -#define DMA_SNIFF_CTRL_CALC_MSB _u(8) -#define DMA_SNIFF_CTRL_CALC_LSB _u(5) -#define DMA_SNIFF_CTRL_CALC_ACCESS "RW" -#define DMA_SNIFF_CTRL_CALC_VALUE_CRC32 _u(0x0) -#define DMA_SNIFF_CTRL_CALC_VALUE_CRC32R _u(0x1) -#define DMA_SNIFF_CTRL_CALC_VALUE_CRC16 _u(0x2) -#define DMA_SNIFF_CTRL_CALC_VALUE_CRC16R _u(0x3) -#define DMA_SNIFF_CTRL_CALC_VALUE_EVEN _u(0xe) -#define DMA_SNIFF_CTRL_CALC_VALUE_SUM _u(0xf) -// ----------------------------------------------------------------------------- -// Field : DMA_SNIFF_CTRL_DMACH -// Description : DMA channel for Sniffer to observe -#define DMA_SNIFF_CTRL_DMACH_RESET _u(0x0) -#define DMA_SNIFF_CTRL_DMACH_BITS _u(0x0000001e) -#define DMA_SNIFF_CTRL_DMACH_MSB _u(4) -#define DMA_SNIFF_CTRL_DMACH_LSB _u(1) -#define DMA_SNIFF_CTRL_DMACH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_SNIFF_CTRL_EN -// Description : Enable sniffer -#define DMA_SNIFF_CTRL_EN_RESET _u(0x0) -#define DMA_SNIFF_CTRL_EN_BITS _u(0x00000001) -#define DMA_SNIFF_CTRL_EN_MSB _u(0) -#define DMA_SNIFF_CTRL_EN_LSB _u(0) -#define DMA_SNIFF_CTRL_EN_ACCESS "RW" -// ============================================================================= -// Register : DMA_SNIFF_DATA -// Description : Data accumulator for sniff hardware -// Write an initial seed value here before starting a DMA transfer -// on the channel indicated by SNIFF_CTRL_DMACH. The hardware will -// update this register each time it observes a read from the -// indicated channel. Once the channel completes, the final result -// can be read from this register. -#define DMA_SNIFF_DATA_OFFSET _u(0x00000458) -#define DMA_SNIFF_DATA_BITS _u(0xffffffff) -#define DMA_SNIFF_DATA_RESET _u(0x00000000) -#define DMA_SNIFF_DATA_MSB _u(31) -#define DMA_SNIFF_DATA_LSB _u(0) -#define DMA_SNIFF_DATA_ACCESS "RW" -// ============================================================================= -// Register : DMA_FIFO_LEVELS -// Description : Debug RAF, WAF, TDF levels -#define DMA_FIFO_LEVELS_OFFSET _u(0x00000460) -#define DMA_FIFO_LEVELS_BITS _u(0x00ffffff) -#define DMA_FIFO_LEVELS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : DMA_FIFO_LEVELS_RAF_LVL -// Description : Current Read-Address-FIFO fill level -#define DMA_FIFO_LEVELS_RAF_LVL_RESET _u(0x00) -#define DMA_FIFO_LEVELS_RAF_LVL_BITS _u(0x00ff0000) -#define DMA_FIFO_LEVELS_RAF_LVL_MSB _u(23) -#define DMA_FIFO_LEVELS_RAF_LVL_LSB _u(16) -#define DMA_FIFO_LEVELS_RAF_LVL_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : DMA_FIFO_LEVELS_WAF_LVL -// Description : Current Write-Address-FIFO fill level -#define DMA_FIFO_LEVELS_WAF_LVL_RESET _u(0x00) -#define DMA_FIFO_LEVELS_WAF_LVL_BITS _u(0x0000ff00) -#define DMA_FIFO_LEVELS_WAF_LVL_MSB _u(15) -#define DMA_FIFO_LEVELS_WAF_LVL_LSB _u(8) -#define DMA_FIFO_LEVELS_WAF_LVL_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : DMA_FIFO_LEVELS_TDF_LVL -// Description : Current Transfer-Data-FIFO fill level -#define DMA_FIFO_LEVELS_TDF_LVL_RESET _u(0x00) -#define DMA_FIFO_LEVELS_TDF_LVL_BITS _u(0x000000ff) -#define DMA_FIFO_LEVELS_TDF_LVL_MSB _u(7) -#define DMA_FIFO_LEVELS_TDF_LVL_LSB _u(0) -#define DMA_FIFO_LEVELS_TDF_LVL_ACCESS "RO" -// ============================================================================= -// Register : DMA_CHAN_ABORT -// Description : Abort an in-progress transfer sequence on one or more channels -// Each bit corresponds to a channel. Writing a 1 aborts whatever -// transfer sequence is in progress on that channel. The bit will -// remain high until any in-flight transfers have been flushed -// through the address and data FIFOs. -// -// After writing, this register must be polled until it returns -// all-zero. Until this point, it is unsafe to restart the -// channel. -#define DMA_CHAN_ABORT_OFFSET _u(0x00000464) -#define DMA_CHAN_ABORT_BITS _u(0x0000ffff) -#define DMA_CHAN_ABORT_RESET _u(0x00000000) -#define DMA_CHAN_ABORT_MSB _u(15) -#define DMA_CHAN_ABORT_LSB _u(0) -#define DMA_CHAN_ABORT_ACCESS "SC" -// ============================================================================= -// Register : DMA_N_CHANNELS -// Description : The number of channels this DMA instance is equipped with. This -// DMA supports up to 16 hardware channels, but can be configured -// with as few as one, to minimise silicon area. -#define DMA_N_CHANNELS_OFFSET _u(0x00000468) -#define DMA_N_CHANNELS_BITS _u(0x0000001f) -#define DMA_N_CHANNELS_RESET "-" -#define DMA_N_CHANNELS_MSB _u(4) -#define DMA_N_CHANNELS_LSB _u(0) -#define DMA_N_CHANNELS_ACCESS "RO" -// ============================================================================= -// Register : DMA_SECCFG_CH0 -// Description : Security configuration for channel 0. Control whether this -// channel performs Secure/Non-secure and Privileged/Unprivileged -// bus accesses. -// -// If this channel generates bus accesses of some security level, -// an access of at least that level (in the order S+P > S+U > NS+P -// > NS+U) is required to program, trigger, abort, check the -// status of, interrupt on or acknowledge the interrupt of this -// channel. -// -// This register automatically locks down (becomes read-only) once -// software starts to configure the channel. -// -// This register is world-readable, but is writable only from a -// Secure, Privileged context. -#define DMA_SECCFG_CH0_OFFSET _u(0x00000480) -#define DMA_SECCFG_CH0_BITS _u(0x00000007) -#define DMA_SECCFG_CH0_RESET _u(0x00000003) -// ----------------------------------------------------------------------------- -// Field : DMA_SECCFG_CH0_LOCK -// Description : LOCK is 0 at reset, and is set to 1 automatically upon a -// successful write to this channel's control registers. That is, -// a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their -// aliases. -// -// Once its LOCK bit is set, this register becomes read-only. -// -// A failed write, for example due to the write's privilege being -// lower than that specified in the channel's SECCFG register, -// will not set the LOCK bit. -#define DMA_SECCFG_CH0_LOCK_RESET _u(0x0) -#define DMA_SECCFG_CH0_LOCK_BITS _u(0x00000004) -#define DMA_SECCFG_CH0_LOCK_MSB _u(2) -#define DMA_SECCFG_CH0_LOCK_LSB _u(2) -#define DMA_SECCFG_CH0_LOCK_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_SECCFG_CH0_S -// Description : Secure channel. If 1, this channel performs Secure bus -// accesses. If 0, it performs Non-secure bus accesses. -// -// If 1, this channel is controllable only from a Secure context. -#define DMA_SECCFG_CH0_S_RESET _u(0x1) -#define DMA_SECCFG_CH0_S_BITS _u(0x00000002) -#define DMA_SECCFG_CH0_S_MSB _u(1) -#define DMA_SECCFG_CH0_S_LSB _u(1) -#define DMA_SECCFG_CH0_S_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_SECCFG_CH0_P -// Description : Privileged channel. If 1, this channel performs Privileged bus -// accesses. If 0, it performs Unprivileged bus accesses. -// -// If 1, this channel is controllable only from a Privileged -// context of the same Secure/Non-secure level, or any context of -// a higher Secure/Non-secure level. -#define DMA_SECCFG_CH0_P_RESET _u(0x1) -#define DMA_SECCFG_CH0_P_BITS _u(0x00000001) -#define DMA_SECCFG_CH0_P_MSB _u(0) -#define DMA_SECCFG_CH0_P_LSB _u(0) -#define DMA_SECCFG_CH0_P_ACCESS "RW" -// ============================================================================= -// Register : DMA_SECCFG_CH1 -// Description : Security configuration for channel 1. Control whether this -// channel performs Secure/Non-secure and Privileged/Unprivileged -// bus accesses. -// -// If this channel generates bus accesses of some security level, -// an access of at least that level (in the order S+P > S+U > NS+P -// > NS+U) is required to program, trigger, abort, check the -// status of, interrupt on or acknowledge the interrupt of this -// channel. -// -// This register automatically locks down (becomes read-only) once -// software starts to configure the channel. -// -// This register is world-readable, but is writable only from a -// Secure, Privileged context. -#define DMA_SECCFG_CH1_OFFSET _u(0x00000484) -#define DMA_SECCFG_CH1_BITS _u(0x00000007) -#define DMA_SECCFG_CH1_RESET _u(0x00000003) -// ----------------------------------------------------------------------------- -// Field : DMA_SECCFG_CH1_LOCK -// Description : LOCK is 0 at reset, and is set to 1 automatically upon a -// successful write to this channel's control registers. That is, -// a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their -// aliases. -// -// Once its LOCK bit is set, this register becomes read-only. -// -// A failed write, for example due to the write's privilege being -// lower than that specified in the channel's SECCFG register, -// will not set the LOCK bit. -#define DMA_SECCFG_CH1_LOCK_RESET _u(0x0) -#define DMA_SECCFG_CH1_LOCK_BITS _u(0x00000004) -#define DMA_SECCFG_CH1_LOCK_MSB _u(2) -#define DMA_SECCFG_CH1_LOCK_LSB _u(2) -#define DMA_SECCFG_CH1_LOCK_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_SECCFG_CH1_S -// Description : Secure channel. If 1, this channel performs Secure bus -// accesses. If 0, it performs Non-secure bus accesses. -// -// If 1, this channel is controllable only from a Secure context. -#define DMA_SECCFG_CH1_S_RESET _u(0x1) -#define DMA_SECCFG_CH1_S_BITS _u(0x00000002) -#define DMA_SECCFG_CH1_S_MSB _u(1) -#define DMA_SECCFG_CH1_S_LSB _u(1) -#define DMA_SECCFG_CH1_S_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_SECCFG_CH1_P -// Description : Privileged channel. If 1, this channel performs Privileged bus -// accesses. If 0, it performs Unprivileged bus accesses. -// -// If 1, this channel is controllable only from a Privileged -// context of the same Secure/Non-secure level, or any context of -// a higher Secure/Non-secure level. -#define DMA_SECCFG_CH1_P_RESET _u(0x1) -#define DMA_SECCFG_CH1_P_BITS _u(0x00000001) -#define DMA_SECCFG_CH1_P_MSB _u(0) -#define DMA_SECCFG_CH1_P_LSB _u(0) -#define DMA_SECCFG_CH1_P_ACCESS "RW" -// ============================================================================= -// Register : DMA_SECCFG_CH2 -// Description : Security configuration for channel 2. Control whether this -// channel performs Secure/Non-secure and Privileged/Unprivileged -// bus accesses. -// -// If this channel generates bus accesses of some security level, -// an access of at least that level (in the order S+P > S+U > NS+P -// > NS+U) is required to program, trigger, abort, check the -// status of, interrupt on or acknowledge the interrupt of this -// channel. -// -// This register automatically locks down (becomes read-only) once -// software starts to configure the channel. -// -// This register is world-readable, but is writable only from a -// Secure, Privileged context. -#define DMA_SECCFG_CH2_OFFSET _u(0x00000488) -#define DMA_SECCFG_CH2_BITS _u(0x00000007) -#define DMA_SECCFG_CH2_RESET _u(0x00000003) -// ----------------------------------------------------------------------------- -// Field : DMA_SECCFG_CH2_LOCK -// Description : LOCK is 0 at reset, and is set to 1 automatically upon a -// successful write to this channel's control registers. That is, -// a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their -// aliases. -// -// Once its LOCK bit is set, this register becomes read-only. -// -// A failed write, for example due to the write's privilege being -// lower than that specified in the channel's SECCFG register, -// will not set the LOCK bit. -#define DMA_SECCFG_CH2_LOCK_RESET _u(0x0) -#define DMA_SECCFG_CH2_LOCK_BITS _u(0x00000004) -#define DMA_SECCFG_CH2_LOCK_MSB _u(2) -#define DMA_SECCFG_CH2_LOCK_LSB _u(2) -#define DMA_SECCFG_CH2_LOCK_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_SECCFG_CH2_S -// Description : Secure channel. If 1, this channel performs Secure bus -// accesses. If 0, it performs Non-secure bus accesses. -// -// If 1, this channel is controllable only from a Secure context. -#define DMA_SECCFG_CH2_S_RESET _u(0x1) -#define DMA_SECCFG_CH2_S_BITS _u(0x00000002) -#define DMA_SECCFG_CH2_S_MSB _u(1) -#define DMA_SECCFG_CH2_S_LSB _u(1) -#define DMA_SECCFG_CH2_S_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_SECCFG_CH2_P -// Description : Privileged channel. If 1, this channel performs Privileged bus -// accesses. If 0, it performs Unprivileged bus accesses. -// -// If 1, this channel is controllable only from a Privileged -// context of the same Secure/Non-secure level, or any context of -// a higher Secure/Non-secure level. -#define DMA_SECCFG_CH2_P_RESET _u(0x1) -#define DMA_SECCFG_CH2_P_BITS _u(0x00000001) -#define DMA_SECCFG_CH2_P_MSB _u(0) -#define DMA_SECCFG_CH2_P_LSB _u(0) -#define DMA_SECCFG_CH2_P_ACCESS "RW" -// ============================================================================= -// Register : DMA_SECCFG_CH3 -// Description : Security configuration for channel 3. Control whether this -// channel performs Secure/Non-secure and Privileged/Unprivileged -// bus accesses. -// -// If this channel generates bus accesses of some security level, -// an access of at least that level (in the order S+P > S+U > NS+P -// > NS+U) is required to program, trigger, abort, check the -// status of, interrupt on or acknowledge the interrupt of this -// channel. -// -// This register automatically locks down (becomes read-only) once -// software starts to configure the channel. -// -// This register is world-readable, but is writable only from a -// Secure, Privileged context. -#define DMA_SECCFG_CH3_OFFSET _u(0x0000048c) -#define DMA_SECCFG_CH3_BITS _u(0x00000007) -#define DMA_SECCFG_CH3_RESET _u(0x00000003) -// ----------------------------------------------------------------------------- -// Field : DMA_SECCFG_CH3_LOCK -// Description : LOCK is 0 at reset, and is set to 1 automatically upon a -// successful write to this channel's control registers. That is, -// a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their -// aliases. -// -// Once its LOCK bit is set, this register becomes read-only. -// -// A failed write, for example due to the write's privilege being -// lower than that specified in the channel's SECCFG register, -// will not set the LOCK bit. -#define DMA_SECCFG_CH3_LOCK_RESET _u(0x0) -#define DMA_SECCFG_CH3_LOCK_BITS _u(0x00000004) -#define DMA_SECCFG_CH3_LOCK_MSB _u(2) -#define DMA_SECCFG_CH3_LOCK_LSB _u(2) -#define DMA_SECCFG_CH3_LOCK_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_SECCFG_CH3_S -// Description : Secure channel. If 1, this channel performs Secure bus -// accesses. If 0, it performs Non-secure bus accesses. -// -// If 1, this channel is controllable only from a Secure context. -#define DMA_SECCFG_CH3_S_RESET _u(0x1) -#define DMA_SECCFG_CH3_S_BITS _u(0x00000002) -#define DMA_SECCFG_CH3_S_MSB _u(1) -#define DMA_SECCFG_CH3_S_LSB _u(1) -#define DMA_SECCFG_CH3_S_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_SECCFG_CH3_P -// Description : Privileged channel. If 1, this channel performs Privileged bus -// accesses. If 0, it performs Unprivileged bus accesses. -// -// If 1, this channel is controllable only from a Privileged -// context of the same Secure/Non-secure level, or any context of -// a higher Secure/Non-secure level. -#define DMA_SECCFG_CH3_P_RESET _u(0x1) -#define DMA_SECCFG_CH3_P_BITS _u(0x00000001) -#define DMA_SECCFG_CH3_P_MSB _u(0) -#define DMA_SECCFG_CH3_P_LSB _u(0) -#define DMA_SECCFG_CH3_P_ACCESS "RW" -// ============================================================================= -// Register : DMA_SECCFG_CH4 -// Description : Security configuration for channel 4. Control whether this -// channel performs Secure/Non-secure and Privileged/Unprivileged -// bus accesses. -// -// If this channel generates bus accesses of some security level, -// an access of at least that level (in the order S+P > S+U > NS+P -// > NS+U) is required to program, trigger, abort, check the -// status of, interrupt on or acknowledge the interrupt of this -// channel. -// -// This register automatically locks down (becomes read-only) once -// software starts to configure the channel. -// -// This register is world-readable, but is writable only from a -// Secure, Privileged context. -#define DMA_SECCFG_CH4_OFFSET _u(0x00000490) -#define DMA_SECCFG_CH4_BITS _u(0x00000007) -#define DMA_SECCFG_CH4_RESET _u(0x00000003) -// ----------------------------------------------------------------------------- -// Field : DMA_SECCFG_CH4_LOCK -// Description : LOCK is 0 at reset, and is set to 1 automatically upon a -// successful write to this channel's control registers. That is, -// a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their -// aliases. -// -// Once its LOCK bit is set, this register becomes read-only. -// -// A failed write, for example due to the write's privilege being -// lower than that specified in the channel's SECCFG register, -// will not set the LOCK bit. -#define DMA_SECCFG_CH4_LOCK_RESET _u(0x0) -#define DMA_SECCFG_CH4_LOCK_BITS _u(0x00000004) -#define DMA_SECCFG_CH4_LOCK_MSB _u(2) -#define DMA_SECCFG_CH4_LOCK_LSB _u(2) -#define DMA_SECCFG_CH4_LOCK_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_SECCFG_CH4_S -// Description : Secure channel. If 1, this channel performs Secure bus -// accesses. If 0, it performs Non-secure bus accesses. -// -// If 1, this channel is controllable only from a Secure context. -#define DMA_SECCFG_CH4_S_RESET _u(0x1) -#define DMA_SECCFG_CH4_S_BITS _u(0x00000002) -#define DMA_SECCFG_CH4_S_MSB _u(1) -#define DMA_SECCFG_CH4_S_LSB _u(1) -#define DMA_SECCFG_CH4_S_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_SECCFG_CH4_P -// Description : Privileged channel. If 1, this channel performs Privileged bus -// accesses. If 0, it performs Unprivileged bus accesses. -// -// If 1, this channel is controllable only from a Privileged -// context of the same Secure/Non-secure level, or any context of -// a higher Secure/Non-secure level. -#define DMA_SECCFG_CH4_P_RESET _u(0x1) -#define DMA_SECCFG_CH4_P_BITS _u(0x00000001) -#define DMA_SECCFG_CH4_P_MSB _u(0) -#define DMA_SECCFG_CH4_P_LSB _u(0) -#define DMA_SECCFG_CH4_P_ACCESS "RW" -// ============================================================================= -// Register : DMA_SECCFG_CH5 -// Description : Security configuration for channel 5. Control whether this -// channel performs Secure/Non-secure and Privileged/Unprivileged -// bus accesses. -// -// If this channel generates bus accesses of some security level, -// an access of at least that level (in the order S+P > S+U > NS+P -// > NS+U) is required to program, trigger, abort, check the -// status of, interrupt on or acknowledge the interrupt of this -// channel. -// -// This register automatically locks down (becomes read-only) once -// software starts to configure the channel. -// -// This register is world-readable, but is writable only from a -// Secure, Privileged context. -#define DMA_SECCFG_CH5_OFFSET _u(0x00000494) -#define DMA_SECCFG_CH5_BITS _u(0x00000007) -#define DMA_SECCFG_CH5_RESET _u(0x00000003) -// ----------------------------------------------------------------------------- -// Field : DMA_SECCFG_CH5_LOCK -// Description : LOCK is 0 at reset, and is set to 1 automatically upon a -// successful write to this channel's control registers. That is, -// a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their -// aliases. -// -// Once its LOCK bit is set, this register becomes read-only. -// -// A failed write, for example due to the write's privilege being -// lower than that specified in the channel's SECCFG register, -// will not set the LOCK bit. -#define DMA_SECCFG_CH5_LOCK_RESET _u(0x0) -#define DMA_SECCFG_CH5_LOCK_BITS _u(0x00000004) -#define DMA_SECCFG_CH5_LOCK_MSB _u(2) -#define DMA_SECCFG_CH5_LOCK_LSB _u(2) -#define DMA_SECCFG_CH5_LOCK_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_SECCFG_CH5_S -// Description : Secure channel. If 1, this channel performs Secure bus -// accesses. If 0, it performs Non-secure bus accesses. -// -// If 1, this channel is controllable only from a Secure context. -#define DMA_SECCFG_CH5_S_RESET _u(0x1) -#define DMA_SECCFG_CH5_S_BITS _u(0x00000002) -#define DMA_SECCFG_CH5_S_MSB _u(1) -#define DMA_SECCFG_CH5_S_LSB _u(1) -#define DMA_SECCFG_CH5_S_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_SECCFG_CH5_P -// Description : Privileged channel. If 1, this channel performs Privileged bus -// accesses. If 0, it performs Unprivileged bus accesses. -// -// If 1, this channel is controllable only from a Privileged -// context of the same Secure/Non-secure level, or any context of -// a higher Secure/Non-secure level. -#define DMA_SECCFG_CH5_P_RESET _u(0x1) -#define DMA_SECCFG_CH5_P_BITS _u(0x00000001) -#define DMA_SECCFG_CH5_P_MSB _u(0) -#define DMA_SECCFG_CH5_P_LSB _u(0) -#define DMA_SECCFG_CH5_P_ACCESS "RW" -// ============================================================================= -// Register : DMA_SECCFG_CH6 -// Description : Security configuration for channel 6. Control whether this -// channel performs Secure/Non-secure and Privileged/Unprivileged -// bus accesses. -// -// If this channel generates bus accesses of some security level, -// an access of at least that level (in the order S+P > S+U > NS+P -// > NS+U) is required to program, trigger, abort, check the -// status of, interrupt on or acknowledge the interrupt of this -// channel. -// -// This register automatically locks down (becomes read-only) once -// software starts to configure the channel. -// -// This register is world-readable, but is writable only from a -// Secure, Privileged context. -#define DMA_SECCFG_CH6_OFFSET _u(0x00000498) -#define DMA_SECCFG_CH6_BITS _u(0x00000007) -#define DMA_SECCFG_CH6_RESET _u(0x00000003) -// ----------------------------------------------------------------------------- -// Field : DMA_SECCFG_CH6_LOCK -// Description : LOCK is 0 at reset, and is set to 1 automatically upon a -// successful write to this channel's control registers. That is, -// a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their -// aliases. -// -// Once its LOCK bit is set, this register becomes read-only. -// -// A failed write, for example due to the write's privilege being -// lower than that specified in the channel's SECCFG register, -// will not set the LOCK bit. -#define DMA_SECCFG_CH6_LOCK_RESET _u(0x0) -#define DMA_SECCFG_CH6_LOCK_BITS _u(0x00000004) -#define DMA_SECCFG_CH6_LOCK_MSB _u(2) -#define DMA_SECCFG_CH6_LOCK_LSB _u(2) -#define DMA_SECCFG_CH6_LOCK_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_SECCFG_CH6_S -// Description : Secure channel. If 1, this channel performs Secure bus -// accesses. If 0, it performs Non-secure bus accesses. -// -// If 1, this channel is controllable only from a Secure context. -#define DMA_SECCFG_CH6_S_RESET _u(0x1) -#define DMA_SECCFG_CH6_S_BITS _u(0x00000002) -#define DMA_SECCFG_CH6_S_MSB _u(1) -#define DMA_SECCFG_CH6_S_LSB _u(1) -#define DMA_SECCFG_CH6_S_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_SECCFG_CH6_P -// Description : Privileged channel. If 1, this channel performs Privileged bus -// accesses. If 0, it performs Unprivileged bus accesses. -// -// If 1, this channel is controllable only from a Privileged -// context of the same Secure/Non-secure level, or any context of -// a higher Secure/Non-secure level. -#define DMA_SECCFG_CH6_P_RESET _u(0x1) -#define DMA_SECCFG_CH6_P_BITS _u(0x00000001) -#define DMA_SECCFG_CH6_P_MSB _u(0) -#define DMA_SECCFG_CH6_P_LSB _u(0) -#define DMA_SECCFG_CH6_P_ACCESS "RW" -// ============================================================================= -// Register : DMA_SECCFG_CH7 -// Description : Security configuration for channel 7. Control whether this -// channel performs Secure/Non-secure and Privileged/Unprivileged -// bus accesses. -// -// If this channel generates bus accesses of some security level, -// an access of at least that level (in the order S+P > S+U > NS+P -// > NS+U) is required to program, trigger, abort, check the -// status of, interrupt on or acknowledge the interrupt of this -// channel. -// -// This register automatically locks down (becomes read-only) once -// software starts to configure the channel. -// -// This register is world-readable, but is writable only from a -// Secure, Privileged context. -#define DMA_SECCFG_CH7_OFFSET _u(0x0000049c) -#define DMA_SECCFG_CH7_BITS _u(0x00000007) -#define DMA_SECCFG_CH7_RESET _u(0x00000003) -// ----------------------------------------------------------------------------- -// Field : DMA_SECCFG_CH7_LOCK -// Description : LOCK is 0 at reset, and is set to 1 automatically upon a -// successful write to this channel's control registers. That is, -// a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their -// aliases. -// -// Once its LOCK bit is set, this register becomes read-only. -// -// A failed write, for example due to the write's privilege being -// lower than that specified in the channel's SECCFG register, -// will not set the LOCK bit. -#define DMA_SECCFG_CH7_LOCK_RESET _u(0x0) -#define DMA_SECCFG_CH7_LOCK_BITS _u(0x00000004) -#define DMA_SECCFG_CH7_LOCK_MSB _u(2) -#define DMA_SECCFG_CH7_LOCK_LSB _u(2) -#define DMA_SECCFG_CH7_LOCK_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_SECCFG_CH7_S -// Description : Secure channel. If 1, this channel performs Secure bus -// accesses. If 0, it performs Non-secure bus accesses. -// -// If 1, this channel is controllable only from a Secure context. -#define DMA_SECCFG_CH7_S_RESET _u(0x1) -#define DMA_SECCFG_CH7_S_BITS _u(0x00000002) -#define DMA_SECCFG_CH7_S_MSB _u(1) -#define DMA_SECCFG_CH7_S_LSB _u(1) -#define DMA_SECCFG_CH7_S_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_SECCFG_CH7_P -// Description : Privileged channel. If 1, this channel performs Privileged bus -// accesses. If 0, it performs Unprivileged bus accesses. -// -// If 1, this channel is controllable only from a Privileged -// context of the same Secure/Non-secure level, or any context of -// a higher Secure/Non-secure level. -#define DMA_SECCFG_CH7_P_RESET _u(0x1) -#define DMA_SECCFG_CH7_P_BITS _u(0x00000001) -#define DMA_SECCFG_CH7_P_MSB _u(0) -#define DMA_SECCFG_CH7_P_LSB _u(0) -#define DMA_SECCFG_CH7_P_ACCESS "RW" -// ============================================================================= -// Register : DMA_SECCFG_CH8 -// Description : Security configuration for channel 8. Control whether this -// channel performs Secure/Non-secure and Privileged/Unprivileged -// bus accesses. -// -// If this channel generates bus accesses of some security level, -// an access of at least that level (in the order S+P > S+U > NS+P -// > NS+U) is required to program, trigger, abort, check the -// status of, interrupt on or acknowledge the interrupt of this -// channel. -// -// This register automatically locks down (becomes read-only) once -// software starts to configure the channel. -// -// This register is world-readable, but is writable only from a -// Secure, Privileged context. -#define DMA_SECCFG_CH8_OFFSET _u(0x000004a0) -#define DMA_SECCFG_CH8_BITS _u(0x00000007) -#define DMA_SECCFG_CH8_RESET _u(0x00000003) -// ----------------------------------------------------------------------------- -// Field : DMA_SECCFG_CH8_LOCK -// Description : LOCK is 0 at reset, and is set to 1 automatically upon a -// successful write to this channel's control registers. That is, -// a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their -// aliases. -// -// Once its LOCK bit is set, this register becomes read-only. -// -// A failed write, for example due to the write's privilege being -// lower than that specified in the channel's SECCFG register, -// will not set the LOCK bit. -#define DMA_SECCFG_CH8_LOCK_RESET _u(0x0) -#define DMA_SECCFG_CH8_LOCK_BITS _u(0x00000004) -#define DMA_SECCFG_CH8_LOCK_MSB _u(2) -#define DMA_SECCFG_CH8_LOCK_LSB _u(2) -#define DMA_SECCFG_CH8_LOCK_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_SECCFG_CH8_S -// Description : Secure channel. If 1, this channel performs Secure bus -// accesses. If 0, it performs Non-secure bus accesses. -// -// If 1, this channel is controllable only from a Secure context. -#define DMA_SECCFG_CH8_S_RESET _u(0x1) -#define DMA_SECCFG_CH8_S_BITS _u(0x00000002) -#define DMA_SECCFG_CH8_S_MSB _u(1) -#define DMA_SECCFG_CH8_S_LSB _u(1) -#define DMA_SECCFG_CH8_S_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_SECCFG_CH8_P -// Description : Privileged channel. If 1, this channel performs Privileged bus -// accesses. If 0, it performs Unprivileged bus accesses. -// -// If 1, this channel is controllable only from a Privileged -// context of the same Secure/Non-secure level, or any context of -// a higher Secure/Non-secure level. -#define DMA_SECCFG_CH8_P_RESET _u(0x1) -#define DMA_SECCFG_CH8_P_BITS _u(0x00000001) -#define DMA_SECCFG_CH8_P_MSB _u(0) -#define DMA_SECCFG_CH8_P_LSB _u(0) -#define DMA_SECCFG_CH8_P_ACCESS "RW" -// ============================================================================= -// Register : DMA_SECCFG_CH9 -// Description : Security configuration for channel 9. Control whether this -// channel performs Secure/Non-secure and Privileged/Unprivileged -// bus accesses. -// -// If this channel generates bus accesses of some security level, -// an access of at least that level (in the order S+P > S+U > NS+P -// > NS+U) is required to program, trigger, abort, check the -// status of, interrupt on or acknowledge the interrupt of this -// channel. -// -// This register automatically locks down (becomes read-only) once -// software starts to configure the channel. -// -// This register is world-readable, but is writable only from a -// Secure, Privileged context. -#define DMA_SECCFG_CH9_OFFSET _u(0x000004a4) -#define DMA_SECCFG_CH9_BITS _u(0x00000007) -#define DMA_SECCFG_CH9_RESET _u(0x00000003) -// ----------------------------------------------------------------------------- -// Field : DMA_SECCFG_CH9_LOCK -// Description : LOCK is 0 at reset, and is set to 1 automatically upon a -// successful write to this channel's control registers. That is, -// a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their -// aliases. -// -// Once its LOCK bit is set, this register becomes read-only. -// -// A failed write, for example due to the write's privilege being -// lower than that specified in the channel's SECCFG register, -// will not set the LOCK bit. -#define DMA_SECCFG_CH9_LOCK_RESET _u(0x0) -#define DMA_SECCFG_CH9_LOCK_BITS _u(0x00000004) -#define DMA_SECCFG_CH9_LOCK_MSB _u(2) -#define DMA_SECCFG_CH9_LOCK_LSB _u(2) -#define DMA_SECCFG_CH9_LOCK_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_SECCFG_CH9_S -// Description : Secure channel. If 1, this channel performs Secure bus -// accesses. If 0, it performs Non-secure bus accesses. -// -// If 1, this channel is controllable only from a Secure context. -#define DMA_SECCFG_CH9_S_RESET _u(0x1) -#define DMA_SECCFG_CH9_S_BITS _u(0x00000002) -#define DMA_SECCFG_CH9_S_MSB _u(1) -#define DMA_SECCFG_CH9_S_LSB _u(1) -#define DMA_SECCFG_CH9_S_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_SECCFG_CH9_P -// Description : Privileged channel. If 1, this channel performs Privileged bus -// accesses. If 0, it performs Unprivileged bus accesses. -// -// If 1, this channel is controllable only from a Privileged -// context of the same Secure/Non-secure level, or any context of -// a higher Secure/Non-secure level. -#define DMA_SECCFG_CH9_P_RESET _u(0x1) -#define DMA_SECCFG_CH9_P_BITS _u(0x00000001) -#define DMA_SECCFG_CH9_P_MSB _u(0) -#define DMA_SECCFG_CH9_P_LSB _u(0) -#define DMA_SECCFG_CH9_P_ACCESS "RW" -// ============================================================================= -// Register : DMA_SECCFG_CH10 -// Description : Security configuration for channel 10. Control whether this -// channel performs Secure/Non-secure and Privileged/Unprivileged -// bus accesses. -// -// If this channel generates bus accesses of some security level, -// an access of at least that level (in the order S+P > S+U > NS+P -// > NS+U) is required to program, trigger, abort, check the -// status of, interrupt on or acknowledge the interrupt of this -// channel. -// -// This register automatically locks down (becomes read-only) once -// software starts to configure the channel. -// -// This register is world-readable, but is writable only from a -// Secure, Privileged context. -#define DMA_SECCFG_CH10_OFFSET _u(0x000004a8) -#define DMA_SECCFG_CH10_BITS _u(0x00000007) -#define DMA_SECCFG_CH10_RESET _u(0x00000003) -// ----------------------------------------------------------------------------- -// Field : DMA_SECCFG_CH10_LOCK -// Description : LOCK is 0 at reset, and is set to 1 automatically upon a -// successful write to this channel's control registers. That is, -// a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their -// aliases. -// -// Once its LOCK bit is set, this register becomes read-only. -// -// A failed write, for example due to the write's privilege being -// lower than that specified in the channel's SECCFG register, -// will not set the LOCK bit. -#define DMA_SECCFG_CH10_LOCK_RESET _u(0x0) -#define DMA_SECCFG_CH10_LOCK_BITS _u(0x00000004) -#define DMA_SECCFG_CH10_LOCK_MSB _u(2) -#define DMA_SECCFG_CH10_LOCK_LSB _u(2) -#define DMA_SECCFG_CH10_LOCK_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_SECCFG_CH10_S -// Description : Secure channel. If 1, this channel performs Secure bus -// accesses. If 0, it performs Non-secure bus accesses. -// -// If 1, this channel is controllable only from a Secure context. -#define DMA_SECCFG_CH10_S_RESET _u(0x1) -#define DMA_SECCFG_CH10_S_BITS _u(0x00000002) -#define DMA_SECCFG_CH10_S_MSB _u(1) -#define DMA_SECCFG_CH10_S_LSB _u(1) -#define DMA_SECCFG_CH10_S_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_SECCFG_CH10_P -// Description : Privileged channel. If 1, this channel performs Privileged bus -// accesses. If 0, it performs Unprivileged bus accesses. -// -// If 1, this channel is controllable only from a Privileged -// context of the same Secure/Non-secure level, or any context of -// a higher Secure/Non-secure level. -#define DMA_SECCFG_CH10_P_RESET _u(0x1) -#define DMA_SECCFG_CH10_P_BITS _u(0x00000001) -#define DMA_SECCFG_CH10_P_MSB _u(0) -#define DMA_SECCFG_CH10_P_LSB _u(0) -#define DMA_SECCFG_CH10_P_ACCESS "RW" -// ============================================================================= -// Register : DMA_SECCFG_CH11 -// Description : Security configuration for channel 11. Control whether this -// channel performs Secure/Non-secure and Privileged/Unprivileged -// bus accesses. -// -// If this channel generates bus accesses of some security level, -// an access of at least that level (in the order S+P > S+U > NS+P -// > NS+U) is required to program, trigger, abort, check the -// status of, interrupt on or acknowledge the interrupt of this -// channel. -// -// This register automatically locks down (becomes read-only) once -// software starts to configure the channel. -// -// This register is world-readable, but is writable only from a -// Secure, Privileged context. -#define DMA_SECCFG_CH11_OFFSET _u(0x000004ac) -#define DMA_SECCFG_CH11_BITS _u(0x00000007) -#define DMA_SECCFG_CH11_RESET _u(0x00000003) -// ----------------------------------------------------------------------------- -// Field : DMA_SECCFG_CH11_LOCK -// Description : LOCK is 0 at reset, and is set to 1 automatically upon a -// successful write to this channel's control registers. That is, -// a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their -// aliases. -// -// Once its LOCK bit is set, this register becomes read-only. -// -// A failed write, for example due to the write's privilege being -// lower than that specified in the channel's SECCFG register, -// will not set the LOCK bit. -#define DMA_SECCFG_CH11_LOCK_RESET _u(0x0) -#define DMA_SECCFG_CH11_LOCK_BITS _u(0x00000004) -#define DMA_SECCFG_CH11_LOCK_MSB _u(2) -#define DMA_SECCFG_CH11_LOCK_LSB _u(2) -#define DMA_SECCFG_CH11_LOCK_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_SECCFG_CH11_S -// Description : Secure channel. If 1, this channel performs Secure bus -// accesses. If 0, it performs Non-secure bus accesses. -// -// If 1, this channel is controllable only from a Secure context. -#define DMA_SECCFG_CH11_S_RESET _u(0x1) -#define DMA_SECCFG_CH11_S_BITS _u(0x00000002) -#define DMA_SECCFG_CH11_S_MSB _u(1) -#define DMA_SECCFG_CH11_S_LSB _u(1) -#define DMA_SECCFG_CH11_S_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_SECCFG_CH11_P -// Description : Privileged channel. If 1, this channel performs Privileged bus -// accesses. If 0, it performs Unprivileged bus accesses. -// -// If 1, this channel is controllable only from a Privileged -// context of the same Secure/Non-secure level, or any context of -// a higher Secure/Non-secure level. -#define DMA_SECCFG_CH11_P_RESET _u(0x1) -#define DMA_SECCFG_CH11_P_BITS _u(0x00000001) -#define DMA_SECCFG_CH11_P_MSB _u(0) -#define DMA_SECCFG_CH11_P_LSB _u(0) -#define DMA_SECCFG_CH11_P_ACCESS "RW" -// ============================================================================= -// Register : DMA_SECCFG_CH12 -// Description : Security configuration for channel 12. Control whether this -// channel performs Secure/Non-secure and Privileged/Unprivileged -// bus accesses. -// -// If this channel generates bus accesses of some security level, -// an access of at least that level (in the order S+P > S+U > NS+P -// > NS+U) is required to program, trigger, abort, check the -// status of, interrupt on or acknowledge the interrupt of this -// channel. -// -// This register automatically locks down (becomes read-only) once -// software starts to configure the channel. -// -// This register is world-readable, but is writable only from a -// Secure, Privileged context. -#define DMA_SECCFG_CH12_OFFSET _u(0x000004b0) -#define DMA_SECCFG_CH12_BITS _u(0x00000007) -#define DMA_SECCFG_CH12_RESET _u(0x00000003) -// ----------------------------------------------------------------------------- -// Field : DMA_SECCFG_CH12_LOCK -// Description : LOCK is 0 at reset, and is set to 1 automatically upon a -// successful write to this channel's control registers. That is, -// a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their -// aliases. -// -// Once its LOCK bit is set, this register becomes read-only. -// -// A failed write, for example due to the write's privilege being -// lower than that specified in the channel's SECCFG register, -// will not set the LOCK bit. -#define DMA_SECCFG_CH12_LOCK_RESET _u(0x0) -#define DMA_SECCFG_CH12_LOCK_BITS _u(0x00000004) -#define DMA_SECCFG_CH12_LOCK_MSB _u(2) -#define DMA_SECCFG_CH12_LOCK_LSB _u(2) -#define DMA_SECCFG_CH12_LOCK_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_SECCFG_CH12_S -// Description : Secure channel. If 1, this channel performs Secure bus -// accesses. If 0, it performs Non-secure bus accesses. -// -// If 1, this channel is controllable only from a Secure context. -#define DMA_SECCFG_CH12_S_RESET _u(0x1) -#define DMA_SECCFG_CH12_S_BITS _u(0x00000002) -#define DMA_SECCFG_CH12_S_MSB _u(1) -#define DMA_SECCFG_CH12_S_LSB _u(1) -#define DMA_SECCFG_CH12_S_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_SECCFG_CH12_P -// Description : Privileged channel. If 1, this channel performs Privileged bus -// accesses. If 0, it performs Unprivileged bus accesses. -// -// If 1, this channel is controllable only from a Privileged -// context of the same Secure/Non-secure level, or any context of -// a higher Secure/Non-secure level. -#define DMA_SECCFG_CH12_P_RESET _u(0x1) -#define DMA_SECCFG_CH12_P_BITS _u(0x00000001) -#define DMA_SECCFG_CH12_P_MSB _u(0) -#define DMA_SECCFG_CH12_P_LSB _u(0) -#define DMA_SECCFG_CH12_P_ACCESS "RW" -// ============================================================================= -// Register : DMA_SECCFG_CH13 -// Description : Security configuration for channel 13. Control whether this -// channel performs Secure/Non-secure and Privileged/Unprivileged -// bus accesses. -// -// If this channel generates bus accesses of some security level, -// an access of at least that level (in the order S+P > S+U > NS+P -// > NS+U) is required to program, trigger, abort, check the -// status of, interrupt on or acknowledge the interrupt of this -// channel. -// -// This register automatically locks down (becomes read-only) once -// software starts to configure the channel. -// -// This register is world-readable, but is writable only from a -// Secure, Privileged context. -#define DMA_SECCFG_CH13_OFFSET _u(0x000004b4) -#define DMA_SECCFG_CH13_BITS _u(0x00000007) -#define DMA_SECCFG_CH13_RESET _u(0x00000003) -// ----------------------------------------------------------------------------- -// Field : DMA_SECCFG_CH13_LOCK -// Description : LOCK is 0 at reset, and is set to 1 automatically upon a -// successful write to this channel's control registers. That is, -// a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their -// aliases. -// -// Once its LOCK bit is set, this register becomes read-only. -// -// A failed write, for example due to the write's privilege being -// lower than that specified in the channel's SECCFG register, -// will not set the LOCK bit. -#define DMA_SECCFG_CH13_LOCK_RESET _u(0x0) -#define DMA_SECCFG_CH13_LOCK_BITS _u(0x00000004) -#define DMA_SECCFG_CH13_LOCK_MSB _u(2) -#define DMA_SECCFG_CH13_LOCK_LSB _u(2) -#define DMA_SECCFG_CH13_LOCK_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_SECCFG_CH13_S -// Description : Secure channel. If 1, this channel performs Secure bus -// accesses. If 0, it performs Non-secure bus accesses. -// -// If 1, this channel is controllable only from a Secure context. -#define DMA_SECCFG_CH13_S_RESET _u(0x1) -#define DMA_SECCFG_CH13_S_BITS _u(0x00000002) -#define DMA_SECCFG_CH13_S_MSB _u(1) -#define DMA_SECCFG_CH13_S_LSB _u(1) -#define DMA_SECCFG_CH13_S_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_SECCFG_CH13_P -// Description : Privileged channel. If 1, this channel performs Privileged bus -// accesses. If 0, it performs Unprivileged bus accesses. -// -// If 1, this channel is controllable only from a Privileged -// context of the same Secure/Non-secure level, or any context of -// a higher Secure/Non-secure level. -#define DMA_SECCFG_CH13_P_RESET _u(0x1) -#define DMA_SECCFG_CH13_P_BITS _u(0x00000001) -#define DMA_SECCFG_CH13_P_MSB _u(0) -#define DMA_SECCFG_CH13_P_LSB _u(0) -#define DMA_SECCFG_CH13_P_ACCESS "RW" -// ============================================================================= -// Register : DMA_SECCFG_CH14 -// Description : Security configuration for channel 14. Control whether this -// channel performs Secure/Non-secure and Privileged/Unprivileged -// bus accesses. -// -// If this channel generates bus accesses of some security level, -// an access of at least that level (in the order S+P > S+U > NS+P -// > NS+U) is required to program, trigger, abort, check the -// status of, interrupt on or acknowledge the interrupt of this -// channel. -// -// This register automatically locks down (becomes read-only) once -// software starts to configure the channel. -// -// This register is world-readable, but is writable only from a -// Secure, Privileged context. -#define DMA_SECCFG_CH14_OFFSET _u(0x000004b8) -#define DMA_SECCFG_CH14_BITS _u(0x00000007) -#define DMA_SECCFG_CH14_RESET _u(0x00000003) -// ----------------------------------------------------------------------------- -// Field : DMA_SECCFG_CH14_LOCK -// Description : LOCK is 0 at reset, and is set to 1 automatically upon a -// successful write to this channel's control registers. That is, -// a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their -// aliases. -// -// Once its LOCK bit is set, this register becomes read-only. -// -// A failed write, for example due to the write's privilege being -// lower than that specified in the channel's SECCFG register, -// will not set the LOCK bit. -#define DMA_SECCFG_CH14_LOCK_RESET _u(0x0) -#define DMA_SECCFG_CH14_LOCK_BITS _u(0x00000004) -#define DMA_SECCFG_CH14_LOCK_MSB _u(2) -#define DMA_SECCFG_CH14_LOCK_LSB _u(2) -#define DMA_SECCFG_CH14_LOCK_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_SECCFG_CH14_S -// Description : Secure channel. If 1, this channel performs Secure bus -// accesses. If 0, it performs Non-secure bus accesses. -// -// If 1, this channel is controllable only from a Secure context. -#define DMA_SECCFG_CH14_S_RESET _u(0x1) -#define DMA_SECCFG_CH14_S_BITS _u(0x00000002) -#define DMA_SECCFG_CH14_S_MSB _u(1) -#define DMA_SECCFG_CH14_S_LSB _u(1) -#define DMA_SECCFG_CH14_S_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_SECCFG_CH14_P -// Description : Privileged channel. If 1, this channel performs Privileged bus -// accesses. If 0, it performs Unprivileged bus accesses. -// -// If 1, this channel is controllable only from a Privileged -// context of the same Secure/Non-secure level, or any context of -// a higher Secure/Non-secure level. -#define DMA_SECCFG_CH14_P_RESET _u(0x1) -#define DMA_SECCFG_CH14_P_BITS _u(0x00000001) -#define DMA_SECCFG_CH14_P_MSB _u(0) -#define DMA_SECCFG_CH14_P_LSB _u(0) -#define DMA_SECCFG_CH14_P_ACCESS "RW" -// ============================================================================= -// Register : DMA_SECCFG_CH15 -// Description : Security configuration for channel 15. Control whether this -// channel performs Secure/Non-secure and Privileged/Unprivileged -// bus accesses. -// -// If this channel generates bus accesses of some security level, -// an access of at least that level (in the order S+P > S+U > NS+P -// > NS+U) is required to program, trigger, abort, check the -// status of, interrupt on or acknowledge the interrupt of this -// channel. -// -// This register automatically locks down (becomes read-only) once -// software starts to configure the channel. -// -// This register is world-readable, but is writable only from a -// Secure, Privileged context. -#define DMA_SECCFG_CH15_OFFSET _u(0x000004bc) -#define DMA_SECCFG_CH15_BITS _u(0x00000007) -#define DMA_SECCFG_CH15_RESET _u(0x00000003) -// ----------------------------------------------------------------------------- -// Field : DMA_SECCFG_CH15_LOCK -// Description : LOCK is 0 at reset, and is set to 1 automatically upon a -// successful write to this channel's control registers. That is, -// a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their -// aliases. -// -// Once its LOCK bit is set, this register becomes read-only. -// -// A failed write, for example due to the write's privilege being -// lower than that specified in the channel's SECCFG register, -// will not set the LOCK bit. -#define DMA_SECCFG_CH15_LOCK_RESET _u(0x0) -#define DMA_SECCFG_CH15_LOCK_BITS _u(0x00000004) -#define DMA_SECCFG_CH15_LOCK_MSB _u(2) -#define DMA_SECCFG_CH15_LOCK_LSB _u(2) -#define DMA_SECCFG_CH15_LOCK_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_SECCFG_CH15_S -// Description : Secure channel. If 1, this channel performs Secure bus -// accesses. If 0, it performs Non-secure bus accesses. -// -// If 1, this channel is controllable only from a Secure context. -#define DMA_SECCFG_CH15_S_RESET _u(0x1) -#define DMA_SECCFG_CH15_S_BITS _u(0x00000002) -#define DMA_SECCFG_CH15_S_MSB _u(1) -#define DMA_SECCFG_CH15_S_LSB _u(1) -#define DMA_SECCFG_CH15_S_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_SECCFG_CH15_P -// Description : Privileged channel. If 1, this channel performs Privileged bus -// accesses. If 0, it performs Unprivileged bus accesses. -// -// If 1, this channel is controllable only from a Privileged -// context of the same Secure/Non-secure level, or any context of -// a higher Secure/Non-secure level. -#define DMA_SECCFG_CH15_P_RESET _u(0x1) -#define DMA_SECCFG_CH15_P_BITS _u(0x00000001) -#define DMA_SECCFG_CH15_P_MSB _u(0) -#define DMA_SECCFG_CH15_P_LSB _u(0) -#define DMA_SECCFG_CH15_P_ACCESS "RW" -// ============================================================================= -// Register : DMA_SECCFG_IRQ0 -// Description : Security configuration for IRQ 0. Control whether the IRQ -// permits configuration by Non-secure/Unprivileged contexts, and -// whether it can observe Secure/Privileged channel interrupt -// flags. -#define DMA_SECCFG_IRQ0_OFFSET _u(0x000004c0) -#define DMA_SECCFG_IRQ0_BITS _u(0x00000003) -#define DMA_SECCFG_IRQ0_RESET _u(0x00000003) -// ----------------------------------------------------------------------------- -// Field : DMA_SECCFG_IRQ0_S -// Description : Secure IRQ. If 1, this IRQ's control registers can only be -// accessed from a Secure context. -// -// If 0, this IRQ's control registers can be accessed from a Non- -// secure context, but Secure channels (as per SECCFG_CHx) are -// masked from the IRQ status, and this IRQ's registers can not be -// used to acknowledge the channel interrupts of Secure channels. -#define DMA_SECCFG_IRQ0_S_RESET _u(0x1) -#define DMA_SECCFG_IRQ0_S_BITS _u(0x00000002) -#define DMA_SECCFG_IRQ0_S_MSB _u(1) -#define DMA_SECCFG_IRQ0_S_LSB _u(1) -#define DMA_SECCFG_IRQ0_S_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_SECCFG_IRQ0_P -// Description : Privileged IRQ. If 1, this IRQ's control registers can only be -// accessed from a Privileged context. -// -// If 0, this IRQ's control registers can be accessed from an -// Unprivileged context, but Privileged channels (as per -// SECCFG_CHx) are masked from the IRQ status, and this IRQ's -// registers can not be used to acknowledge the channel interrupts -// of Privileged channels. -#define DMA_SECCFG_IRQ0_P_RESET _u(0x1) -#define DMA_SECCFG_IRQ0_P_BITS _u(0x00000001) -#define DMA_SECCFG_IRQ0_P_MSB _u(0) -#define DMA_SECCFG_IRQ0_P_LSB _u(0) -#define DMA_SECCFG_IRQ0_P_ACCESS "RW" -// ============================================================================= -// Register : DMA_SECCFG_IRQ1 -// Description : Security configuration for IRQ 1. Control whether the IRQ -// permits configuration by Non-secure/Unprivileged contexts, and -// whether it can observe Secure/Privileged channel interrupt -// flags. -#define DMA_SECCFG_IRQ1_OFFSET _u(0x000004c4) -#define DMA_SECCFG_IRQ1_BITS _u(0x00000003) -#define DMA_SECCFG_IRQ1_RESET _u(0x00000003) -// ----------------------------------------------------------------------------- -// Field : DMA_SECCFG_IRQ1_S -// Description : Secure IRQ. If 1, this IRQ's control registers can only be -// accessed from a Secure context. -// -// If 0, this IRQ's control registers can be accessed from a Non- -// secure context, but Secure channels (as per SECCFG_CHx) are -// masked from the IRQ status, and this IRQ's registers can not be -// used to acknowledge the channel interrupts of Secure channels. -#define DMA_SECCFG_IRQ1_S_RESET _u(0x1) -#define DMA_SECCFG_IRQ1_S_BITS _u(0x00000002) -#define DMA_SECCFG_IRQ1_S_MSB _u(1) -#define DMA_SECCFG_IRQ1_S_LSB _u(1) -#define DMA_SECCFG_IRQ1_S_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_SECCFG_IRQ1_P -// Description : Privileged IRQ. If 1, this IRQ's control registers can only be -// accessed from a Privileged context. -// -// If 0, this IRQ's control registers can be accessed from an -// Unprivileged context, but Privileged channels (as per -// SECCFG_CHx) are masked from the IRQ status, and this IRQ's -// registers can not be used to acknowledge the channel interrupts -// of Privileged channels. -#define DMA_SECCFG_IRQ1_P_RESET _u(0x1) -#define DMA_SECCFG_IRQ1_P_BITS _u(0x00000001) -#define DMA_SECCFG_IRQ1_P_MSB _u(0) -#define DMA_SECCFG_IRQ1_P_LSB _u(0) -#define DMA_SECCFG_IRQ1_P_ACCESS "RW" -// ============================================================================= -// Register : DMA_SECCFG_IRQ2 -// Description : Security configuration for IRQ 2. Control whether the IRQ -// permits configuration by Non-secure/Unprivileged contexts, and -// whether it can observe Secure/Privileged channel interrupt -// flags. -#define DMA_SECCFG_IRQ2_OFFSET _u(0x000004c8) -#define DMA_SECCFG_IRQ2_BITS _u(0x00000003) -#define DMA_SECCFG_IRQ2_RESET _u(0x00000003) -// ----------------------------------------------------------------------------- -// Field : DMA_SECCFG_IRQ2_S -// Description : Secure IRQ. If 1, this IRQ's control registers can only be -// accessed from a Secure context. -// -// If 0, this IRQ's control registers can be accessed from a Non- -// secure context, but Secure channels (as per SECCFG_CHx) are -// masked from the IRQ status, and this IRQ's registers can not be -// used to acknowledge the channel interrupts of Secure channels. -#define DMA_SECCFG_IRQ2_S_RESET _u(0x1) -#define DMA_SECCFG_IRQ2_S_BITS _u(0x00000002) -#define DMA_SECCFG_IRQ2_S_MSB _u(1) -#define DMA_SECCFG_IRQ2_S_LSB _u(1) -#define DMA_SECCFG_IRQ2_S_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_SECCFG_IRQ2_P -// Description : Privileged IRQ. If 1, this IRQ's control registers can only be -// accessed from a Privileged context. -// -// If 0, this IRQ's control registers can be accessed from an -// Unprivileged context, but Privileged channels (as per -// SECCFG_CHx) are masked from the IRQ status, and this IRQ's -// registers can not be used to acknowledge the channel interrupts -// of Privileged channels. -#define DMA_SECCFG_IRQ2_P_RESET _u(0x1) -#define DMA_SECCFG_IRQ2_P_BITS _u(0x00000001) -#define DMA_SECCFG_IRQ2_P_MSB _u(0) -#define DMA_SECCFG_IRQ2_P_LSB _u(0) -#define DMA_SECCFG_IRQ2_P_ACCESS "RW" -// ============================================================================= -// Register : DMA_SECCFG_IRQ3 -// Description : Security configuration for IRQ 3. Control whether the IRQ -// permits configuration by Non-secure/Unprivileged contexts, and -// whether it can observe Secure/Privileged channel interrupt -// flags. -#define DMA_SECCFG_IRQ3_OFFSET _u(0x000004cc) -#define DMA_SECCFG_IRQ3_BITS _u(0x00000003) -#define DMA_SECCFG_IRQ3_RESET _u(0x00000003) -// ----------------------------------------------------------------------------- -// Field : DMA_SECCFG_IRQ3_S -// Description : Secure IRQ. If 1, this IRQ's control registers can only be -// accessed from a Secure context. -// -// If 0, this IRQ's control registers can be accessed from a Non- -// secure context, but Secure channels (as per SECCFG_CHx) are -// masked from the IRQ status, and this IRQ's registers can not be -// used to acknowledge the channel interrupts of Secure channels. -#define DMA_SECCFG_IRQ3_S_RESET _u(0x1) -#define DMA_SECCFG_IRQ3_S_BITS _u(0x00000002) -#define DMA_SECCFG_IRQ3_S_MSB _u(1) -#define DMA_SECCFG_IRQ3_S_LSB _u(1) -#define DMA_SECCFG_IRQ3_S_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_SECCFG_IRQ3_P -// Description : Privileged IRQ. If 1, this IRQ's control registers can only be -// accessed from a Privileged context. -// -// If 0, this IRQ's control registers can be accessed from an -// Unprivileged context, but Privileged channels (as per -// SECCFG_CHx) are masked from the IRQ status, and this IRQ's -// registers can not be used to acknowledge the channel interrupts -// of Privileged channels. -#define DMA_SECCFG_IRQ3_P_RESET _u(0x1) -#define DMA_SECCFG_IRQ3_P_BITS _u(0x00000001) -#define DMA_SECCFG_IRQ3_P_MSB _u(0) -#define DMA_SECCFG_IRQ3_P_LSB _u(0) -#define DMA_SECCFG_IRQ3_P_ACCESS "RW" -// ============================================================================= -// Register : DMA_SECCFG_MISC -// Description : Miscellaneous security configuration -#define DMA_SECCFG_MISC_OFFSET _u(0x000004d0) -#define DMA_SECCFG_MISC_BITS _u(0x000003ff) -#define DMA_SECCFG_MISC_RESET _u(0x000003ff) -// ----------------------------------------------------------------------------- -// Field : DMA_SECCFG_MISC_TIMER3_S -// Description : If 1, the TIMER3 register is only accessible from a Secure -// context, and timer DREQ 3 is only visible to Secure channels. -#define DMA_SECCFG_MISC_TIMER3_S_RESET _u(0x1) -#define DMA_SECCFG_MISC_TIMER3_S_BITS _u(0x00000200) -#define DMA_SECCFG_MISC_TIMER3_S_MSB _u(9) -#define DMA_SECCFG_MISC_TIMER3_S_LSB _u(9) -#define DMA_SECCFG_MISC_TIMER3_S_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_SECCFG_MISC_TIMER3_P -// Description : If 1, the TIMER3 register is only accessible from a Privileged -// (or more Secure) context, and timer DREQ 3 is only visible to -// Privileged (or more Secure) channels. -#define DMA_SECCFG_MISC_TIMER3_P_RESET _u(0x1) -#define DMA_SECCFG_MISC_TIMER3_P_BITS _u(0x00000100) -#define DMA_SECCFG_MISC_TIMER3_P_MSB _u(8) -#define DMA_SECCFG_MISC_TIMER3_P_LSB _u(8) -#define DMA_SECCFG_MISC_TIMER3_P_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_SECCFG_MISC_TIMER2_S -// Description : If 1, the TIMER2 register is only accessible from a Secure -// context, and timer DREQ 2 is only visible to Secure channels. -#define DMA_SECCFG_MISC_TIMER2_S_RESET _u(0x1) -#define DMA_SECCFG_MISC_TIMER2_S_BITS _u(0x00000080) -#define DMA_SECCFG_MISC_TIMER2_S_MSB _u(7) -#define DMA_SECCFG_MISC_TIMER2_S_LSB _u(7) -#define DMA_SECCFG_MISC_TIMER2_S_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_SECCFG_MISC_TIMER2_P -// Description : If 1, the TIMER2 register is only accessible from a Privileged -// (or more Secure) context, and timer DREQ 2 is only visible to -// Privileged (or more Secure) channels. -#define DMA_SECCFG_MISC_TIMER2_P_RESET _u(0x1) -#define DMA_SECCFG_MISC_TIMER2_P_BITS _u(0x00000040) -#define DMA_SECCFG_MISC_TIMER2_P_MSB _u(6) -#define DMA_SECCFG_MISC_TIMER2_P_LSB _u(6) -#define DMA_SECCFG_MISC_TIMER2_P_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_SECCFG_MISC_TIMER1_S -// Description : If 1, the TIMER1 register is only accessible from a Secure -// context, and timer DREQ 1 is only visible to Secure channels. -#define DMA_SECCFG_MISC_TIMER1_S_RESET _u(0x1) -#define DMA_SECCFG_MISC_TIMER1_S_BITS _u(0x00000020) -#define DMA_SECCFG_MISC_TIMER1_S_MSB _u(5) -#define DMA_SECCFG_MISC_TIMER1_S_LSB _u(5) -#define DMA_SECCFG_MISC_TIMER1_S_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_SECCFG_MISC_TIMER1_P -// Description : If 1, the TIMER1 register is only accessible from a Privileged -// (or more Secure) context, and timer DREQ 1 is only visible to -// Privileged (or more Secure) channels. -#define DMA_SECCFG_MISC_TIMER1_P_RESET _u(0x1) -#define DMA_SECCFG_MISC_TIMER1_P_BITS _u(0x00000010) -#define DMA_SECCFG_MISC_TIMER1_P_MSB _u(4) -#define DMA_SECCFG_MISC_TIMER1_P_LSB _u(4) -#define DMA_SECCFG_MISC_TIMER1_P_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_SECCFG_MISC_TIMER0_S -// Description : If 1, the TIMER0 register is only accessible from a Secure -// context, and timer DREQ 0 is only visible to Secure channels. -#define DMA_SECCFG_MISC_TIMER0_S_RESET _u(0x1) -#define DMA_SECCFG_MISC_TIMER0_S_BITS _u(0x00000008) -#define DMA_SECCFG_MISC_TIMER0_S_MSB _u(3) -#define DMA_SECCFG_MISC_TIMER0_S_LSB _u(3) -#define DMA_SECCFG_MISC_TIMER0_S_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_SECCFG_MISC_TIMER0_P -// Description : If 1, the TIMER0 register is only accessible from a Privileged -// (or more Secure) context, and timer DREQ 0 is only visible to -// Privileged (or more Secure) channels. -#define DMA_SECCFG_MISC_TIMER0_P_RESET _u(0x1) -#define DMA_SECCFG_MISC_TIMER0_P_BITS _u(0x00000004) -#define DMA_SECCFG_MISC_TIMER0_P_MSB _u(2) -#define DMA_SECCFG_MISC_TIMER0_P_LSB _u(2) -#define DMA_SECCFG_MISC_TIMER0_P_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_SECCFG_MISC_SNIFF_S -// Description : If 1, the sniffer can see data transfers from Secure channels, -// and can itself only be accessed from a Secure context. -// -// If 0, the sniffer can be accessed from either a Secure or Non- -// secure context, but can not see data transfers of Secure -// channels. -#define DMA_SECCFG_MISC_SNIFF_S_RESET _u(0x1) -#define DMA_SECCFG_MISC_SNIFF_S_BITS _u(0x00000002) -#define DMA_SECCFG_MISC_SNIFF_S_MSB _u(1) -#define DMA_SECCFG_MISC_SNIFF_S_LSB _u(1) -#define DMA_SECCFG_MISC_SNIFF_S_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_SECCFG_MISC_SNIFF_P -// Description : If 1, the sniffer can see data transfers from Privileged -// channels, and can itself only be accessed from a privileged -// context, or from a Secure context when SNIFF_S is 0. -// -// If 0, the sniffer can be accessed from either a Privileged or -// Unprivileged context (with sufficient security level) but can -// not see transfers from Privileged channels. -#define DMA_SECCFG_MISC_SNIFF_P_RESET _u(0x1) -#define DMA_SECCFG_MISC_SNIFF_P_BITS _u(0x00000001) -#define DMA_SECCFG_MISC_SNIFF_P_MSB _u(0) -#define DMA_SECCFG_MISC_SNIFF_P_LSB _u(0) -#define DMA_SECCFG_MISC_SNIFF_P_ACCESS "RW" -// ============================================================================= -// Register : DMA_MPU_CTRL -// Description : Control register for DMA MPU. Accessible only from a Privileged -// context. -#define DMA_MPU_CTRL_OFFSET _u(0x00000500) -#define DMA_MPU_CTRL_BITS _u(0x0000000e) -#define DMA_MPU_CTRL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : DMA_MPU_CTRL_NS_HIDE_ADDR -// Description : By default, when a region's S bit is clear, Non-secure- -// Privileged reads can see the region's base address and limit -// address. Set this bit to make the addresses appear as 0 to Non- -// secure reads, even when the region is Non-secure, to avoid -// leaking information about the processor SAU map. -#define DMA_MPU_CTRL_NS_HIDE_ADDR_RESET _u(0x0) -#define DMA_MPU_CTRL_NS_HIDE_ADDR_BITS _u(0x00000008) -#define DMA_MPU_CTRL_NS_HIDE_ADDR_MSB _u(3) -#define DMA_MPU_CTRL_NS_HIDE_ADDR_LSB _u(3) -#define DMA_MPU_CTRL_NS_HIDE_ADDR_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_MPU_CTRL_S -// Description : Determine whether an address not covered by an active MPU -// region is Secure (1) or Non-secure (0) -#define DMA_MPU_CTRL_S_RESET _u(0x0) -#define DMA_MPU_CTRL_S_BITS _u(0x00000004) -#define DMA_MPU_CTRL_S_MSB _u(2) -#define DMA_MPU_CTRL_S_LSB _u(2) -#define DMA_MPU_CTRL_S_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_MPU_CTRL_P -// Description : Determine whether an address not covered by an active MPU -// region is Privileged (1) or Unprivileged (0) -#define DMA_MPU_CTRL_P_RESET _u(0x0) -#define DMA_MPU_CTRL_P_BITS _u(0x00000002) -#define DMA_MPU_CTRL_P_MSB _u(1) -#define DMA_MPU_CTRL_P_LSB _u(1) -#define DMA_MPU_CTRL_P_ACCESS "RW" -// ============================================================================= -// Register : DMA_MPU_BAR0 -// Description : Base address register for MPU region 0. Writable only from a -// Secure, Privileged context. -#define DMA_MPU_BAR0_OFFSET _u(0x00000504) -#define DMA_MPU_BAR0_BITS _u(0xffffffe0) -#define DMA_MPU_BAR0_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : DMA_MPU_BAR0_ADDR -// Description : This MPU region matches addresses where addr[31:5] (the 27 most -// significant bits) are greater than or equal to BAR_ADDR, and -// less than or equal to LAR_ADDR. -// -// Readable from any Privileged context, if and only if this -// region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. -// Otherwise readable only from a Secure, Privileged context. -#define DMA_MPU_BAR0_ADDR_RESET _u(0x0000000) -#define DMA_MPU_BAR0_ADDR_BITS _u(0xffffffe0) -#define DMA_MPU_BAR0_ADDR_MSB _u(31) -#define DMA_MPU_BAR0_ADDR_LSB _u(5) -#define DMA_MPU_BAR0_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_MPU_LAR0 -// Description : Limit address register for MPU region 0. Writable only from a -// Secure, Privileged context, with the exception of the P bit. -#define DMA_MPU_LAR0_OFFSET _u(0x00000508) -#define DMA_MPU_LAR0_BITS _u(0xffffffe7) -#define DMA_MPU_LAR0_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : DMA_MPU_LAR0_ADDR -// Description : Limit address bits 31:5. Readable from any Privileged context, -// if and only if this region's S bit is clear, and -// MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a -// Secure, Privileged context. -#define DMA_MPU_LAR0_ADDR_RESET _u(0x0000000) -#define DMA_MPU_LAR0_ADDR_BITS _u(0xffffffe0) -#define DMA_MPU_LAR0_ADDR_MSB _u(31) -#define DMA_MPU_LAR0_ADDR_LSB _u(5) -#define DMA_MPU_LAR0_ADDR_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_MPU_LAR0_S -// Description : Determines the Secure/Non-secure (=1/0) status of addresses -// matching this region, if this region is enabled. -#define DMA_MPU_LAR0_S_RESET _u(0x0) -#define DMA_MPU_LAR0_S_BITS _u(0x00000004) -#define DMA_MPU_LAR0_S_MSB _u(2) -#define DMA_MPU_LAR0_S_LSB _u(2) -#define DMA_MPU_LAR0_S_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_MPU_LAR0_P -// Description : Determines the Privileged/Unprivileged (=1/0) status of -// addresses matching this region, if this region is enabled. -// Writable from any Privileged context, if and only if the S bit -// is clear. Otherwise, writable only from a Secure, Privileged -// context. -#define DMA_MPU_LAR0_P_RESET _u(0x0) -#define DMA_MPU_LAR0_P_BITS _u(0x00000002) -#define DMA_MPU_LAR0_P_MSB _u(1) -#define DMA_MPU_LAR0_P_LSB _u(1) -#define DMA_MPU_LAR0_P_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_MPU_LAR0_EN -// Description : Region enable. If 1, any address within range specified by the -// base address (BAR_ADDR) and limit address (LAR_ADDR) has the -// attributes specified by S and P. -#define DMA_MPU_LAR0_EN_RESET _u(0x0) -#define DMA_MPU_LAR0_EN_BITS _u(0x00000001) -#define DMA_MPU_LAR0_EN_MSB _u(0) -#define DMA_MPU_LAR0_EN_LSB _u(0) -#define DMA_MPU_LAR0_EN_ACCESS "RW" -// ============================================================================= -// Register : DMA_MPU_BAR1 -// Description : Base address register for MPU region 1. Writable only from a -// Secure, Privileged context. -#define DMA_MPU_BAR1_OFFSET _u(0x0000050c) -#define DMA_MPU_BAR1_BITS _u(0xffffffe0) -#define DMA_MPU_BAR1_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : DMA_MPU_BAR1_ADDR -// Description : This MPU region matches addresses where addr[31:5] (the 27 most -// significant bits) are greater than or equal to BAR_ADDR, and -// less than or equal to LAR_ADDR. -// -// Readable from any Privileged context, if and only if this -// region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. -// Otherwise readable only from a Secure, Privileged context. -#define DMA_MPU_BAR1_ADDR_RESET _u(0x0000000) -#define DMA_MPU_BAR1_ADDR_BITS _u(0xffffffe0) -#define DMA_MPU_BAR1_ADDR_MSB _u(31) -#define DMA_MPU_BAR1_ADDR_LSB _u(5) -#define DMA_MPU_BAR1_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_MPU_LAR1 -// Description : Limit address register for MPU region 1. Writable only from a -// Secure, Privileged context, with the exception of the P bit. -#define DMA_MPU_LAR1_OFFSET _u(0x00000510) -#define DMA_MPU_LAR1_BITS _u(0xffffffe7) -#define DMA_MPU_LAR1_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : DMA_MPU_LAR1_ADDR -// Description : Limit address bits 31:5. Readable from any Privileged context, -// if and only if this region's S bit is clear, and -// MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a -// Secure, Privileged context. -#define DMA_MPU_LAR1_ADDR_RESET _u(0x0000000) -#define DMA_MPU_LAR1_ADDR_BITS _u(0xffffffe0) -#define DMA_MPU_LAR1_ADDR_MSB _u(31) -#define DMA_MPU_LAR1_ADDR_LSB _u(5) -#define DMA_MPU_LAR1_ADDR_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_MPU_LAR1_S -// Description : Determines the Secure/Non-secure (=1/0) status of addresses -// matching this region, if this region is enabled. -#define DMA_MPU_LAR1_S_RESET _u(0x0) -#define DMA_MPU_LAR1_S_BITS _u(0x00000004) -#define DMA_MPU_LAR1_S_MSB _u(2) -#define DMA_MPU_LAR1_S_LSB _u(2) -#define DMA_MPU_LAR1_S_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_MPU_LAR1_P -// Description : Determines the Privileged/Unprivileged (=1/0) status of -// addresses matching this region, if this region is enabled. -// Writable from any Privileged context, if and only if the S bit -// is clear. Otherwise, writable only from a Secure, Privileged -// context. -#define DMA_MPU_LAR1_P_RESET _u(0x0) -#define DMA_MPU_LAR1_P_BITS _u(0x00000002) -#define DMA_MPU_LAR1_P_MSB _u(1) -#define DMA_MPU_LAR1_P_LSB _u(1) -#define DMA_MPU_LAR1_P_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_MPU_LAR1_EN -// Description : Region enable. If 1, any address within range specified by the -// base address (BAR_ADDR) and limit address (LAR_ADDR) has the -// attributes specified by S and P. -#define DMA_MPU_LAR1_EN_RESET _u(0x0) -#define DMA_MPU_LAR1_EN_BITS _u(0x00000001) -#define DMA_MPU_LAR1_EN_MSB _u(0) -#define DMA_MPU_LAR1_EN_LSB _u(0) -#define DMA_MPU_LAR1_EN_ACCESS "RW" -// ============================================================================= -// Register : DMA_MPU_BAR2 -// Description : Base address register for MPU region 2. Writable only from a -// Secure, Privileged context. -#define DMA_MPU_BAR2_OFFSET _u(0x00000514) -#define DMA_MPU_BAR2_BITS _u(0xffffffe0) -#define DMA_MPU_BAR2_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : DMA_MPU_BAR2_ADDR -// Description : This MPU region matches addresses where addr[31:5] (the 27 most -// significant bits) are greater than or equal to BAR_ADDR, and -// less than or equal to LAR_ADDR. -// -// Readable from any Privileged context, if and only if this -// region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. -// Otherwise readable only from a Secure, Privileged context. -#define DMA_MPU_BAR2_ADDR_RESET _u(0x0000000) -#define DMA_MPU_BAR2_ADDR_BITS _u(0xffffffe0) -#define DMA_MPU_BAR2_ADDR_MSB _u(31) -#define DMA_MPU_BAR2_ADDR_LSB _u(5) -#define DMA_MPU_BAR2_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_MPU_LAR2 -// Description : Limit address register for MPU region 2. Writable only from a -// Secure, Privileged context, with the exception of the P bit. -#define DMA_MPU_LAR2_OFFSET _u(0x00000518) -#define DMA_MPU_LAR2_BITS _u(0xffffffe7) -#define DMA_MPU_LAR2_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : DMA_MPU_LAR2_ADDR -// Description : Limit address bits 31:5. Readable from any Privileged context, -// if and only if this region's S bit is clear, and -// MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a -// Secure, Privileged context. -#define DMA_MPU_LAR2_ADDR_RESET _u(0x0000000) -#define DMA_MPU_LAR2_ADDR_BITS _u(0xffffffe0) -#define DMA_MPU_LAR2_ADDR_MSB _u(31) -#define DMA_MPU_LAR2_ADDR_LSB _u(5) -#define DMA_MPU_LAR2_ADDR_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_MPU_LAR2_S -// Description : Determines the Secure/Non-secure (=1/0) status of addresses -// matching this region, if this region is enabled. -#define DMA_MPU_LAR2_S_RESET _u(0x0) -#define DMA_MPU_LAR2_S_BITS _u(0x00000004) -#define DMA_MPU_LAR2_S_MSB _u(2) -#define DMA_MPU_LAR2_S_LSB _u(2) -#define DMA_MPU_LAR2_S_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_MPU_LAR2_P -// Description : Determines the Privileged/Unprivileged (=1/0) status of -// addresses matching this region, if this region is enabled. -// Writable from any Privileged context, if and only if the S bit -// is clear. Otherwise, writable only from a Secure, Privileged -// context. -#define DMA_MPU_LAR2_P_RESET _u(0x0) -#define DMA_MPU_LAR2_P_BITS _u(0x00000002) -#define DMA_MPU_LAR2_P_MSB _u(1) -#define DMA_MPU_LAR2_P_LSB _u(1) -#define DMA_MPU_LAR2_P_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_MPU_LAR2_EN -// Description : Region enable. If 1, any address within range specified by the -// base address (BAR_ADDR) and limit address (LAR_ADDR) has the -// attributes specified by S and P. -#define DMA_MPU_LAR2_EN_RESET _u(0x0) -#define DMA_MPU_LAR2_EN_BITS _u(0x00000001) -#define DMA_MPU_LAR2_EN_MSB _u(0) -#define DMA_MPU_LAR2_EN_LSB _u(0) -#define DMA_MPU_LAR2_EN_ACCESS "RW" -// ============================================================================= -// Register : DMA_MPU_BAR3 -// Description : Base address register for MPU region 3. Writable only from a -// Secure, Privileged context. -#define DMA_MPU_BAR3_OFFSET _u(0x0000051c) -#define DMA_MPU_BAR3_BITS _u(0xffffffe0) -#define DMA_MPU_BAR3_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : DMA_MPU_BAR3_ADDR -// Description : This MPU region matches addresses where addr[31:5] (the 27 most -// significant bits) are greater than or equal to BAR_ADDR, and -// less than or equal to LAR_ADDR. -// -// Readable from any Privileged context, if and only if this -// region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. -// Otherwise readable only from a Secure, Privileged context. -#define DMA_MPU_BAR3_ADDR_RESET _u(0x0000000) -#define DMA_MPU_BAR3_ADDR_BITS _u(0xffffffe0) -#define DMA_MPU_BAR3_ADDR_MSB _u(31) -#define DMA_MPU_BAR3_ADDR_LSB _u(5) -#define DMA_MPU_BAR3_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_MPU_LAR3 -// Description : Limit address register for MPU region 3. Writable only from a -// Secure, Privileged context, with the exception of the P bit. -#define DMA_MPU_LAR3_OFFSET _u(0x00000520) -#define DMA_MPU_LAR3_BITS _u(0xffffffe7) -#define DMA_MPU_LAR3_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : DMA_MPU_LAR3_ADDR -// Description : Limit address bits 31:5. Readable from any Privileged context, -// if and only if this region's S bit is clear, and -// MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a -// Secure, Privileged context. -#define DMA_MPU_LAR3_ADDR_RESET _u(0x0000000) -#define DMA_MPU_LAR3_ADDR_BITS _u(0xffffffe0) -#define DMA_MPU_LAR3_ADDR_MSB _u(31) -#define DMA_MPU_LAR3_ADDR_LSB _u(5) -#define DMA_MPU_LAR3_ADDR_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_MPU_LAR3_S -// Description : Determines the Secure/Non-secure (=1/0) status of addresses -// matching this region, if this region is enabled. -#define DMA_MPU_LAR3_S_RESET _u(0x0) -#define DMA_MPU_LAR3_S_BITS _u(0x00000004) -#define DMA_MPU_LAR3_S_MSB _u(2) -#define DMA_MPU_LAR3_S_LSB _u(2) -#define DMA_MPU_LAR3_S_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_MPU_LAR3_P -// Description : Determines the Privileged/Unprivileged (=1/0) status of -// addresses matching this region, if this region is enabled. -// Writable from any Privileged context, if and only if the S bit -// is clear. Otherwise, writable only from a Secure, Privileged -// context. -#define DMA_MPU_LAR3_P_RESET _u(0x0) -#define DMA_MPU_LAR3_P_BITS _u(0x00000002) -#define DMA_MPU_LAR3_P_MSB _u(1) -#define DMA_MPU_LAR3_P_LSB _u(1) -#define DMA_MPU_LAR3_P_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_MPU_LAR3_EN -// Description : Region enable. If 1, any address within range specified by the -// base address (BAR_ADDR) and limit address (LAR_ADDR) has the -// attributes specified by S and P. -#define DMA_MPU_LAR3_EN_RESET _u(0x0) -#define DMA_MPU_LAR3_EN_BITS _u(0x00000001) -#define DMA_MPU_LAR3_EN_MSB _u(0) -#define DMA_MPU_LAR3_EN_LSB _u(0) -#define DMA_MPU_LAR3_EN_ACCESS "RW" -// ============================================================================= -// Register : DMA_MPU_BAR4 -// Description : Base address register for MPU region 4. Writable only from a -// Secure, Privileged context. -#define DMA_MPU_BAR4_OFFSET _u(0x00000524) -#define DMA_MPU_BAR4_BITS _u(0xffffffe0) -#define DMA_MPU_BAR4_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : DMA_MPU_BAR4_ADDR -// Description : This MPU region matches addresses where addr[31:5] (the 27 most -// significant bits) are greater than or equal to BAR_ADDR, and -// less than or equal to LAR_ADDR. -// -// Readable from any Privileged context, if and only if this -// region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. -// Otherwise readable only from a Secure, Privileged context. -#define DMA_MPU_BAR4_ADDR_RESET _u(0x0000000) -#define DMA_MPU_BAR4_ADDR_BITS _u(0xffffffe0) -#define DMA_MPU_BAR4_ADDR_MSB _u(31) -#define DMA_MPU_BAR4_ADDR_LSB _u(5) -#define DMA_MPU_BAR4_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_MPU_LAR4 -// Description : Limit address register for MPU region 4. Writable only from a -// Secure, Privileged context, with the exception of the P bit. -#define DMA_MPU_LAR4_OFFSET _u(0x00000528) -#define DMA_MPU_LAR4_BITS _u(0xffffffe7) -#define DMA_MPU_LAR4_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : DMA_MPU_LAR4_ADDR -// Description : Limit address bits 31:5. Readable from any Privileged context, -// if and only if this region's S bit is clear, and -// MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a -// Secure, Privileged context. -#define DMA_MPU_LAR4_ADDR_RESET _u(0x0000000) -#define DMA_MPU_LAR4_ADDR_BITS _u(0xffffffe0) -#define DMA_MPU_LAR4_ADDR_MSB _u(31) -#define DMA_MPU_LAR4_ADDR_LSB _u(5) -#define DMA_MPU_LAR4_ADDR_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_MPU_LAR4_S -// Description : Determines the Secure/Non-secure (=1/0) status of addresses -// matching this region, if this region is enabled. -#define DMA_MPU_LAR4_S_RESET _u(0x0) -#define DMA_MPU_LAR4_S_BITS _u(0x00000004) -#define DMA_MPU_LAR4_S_MSB _u(2) -#define DMA_MPU_LAR4_S_LSB _u(2) -#define DMA_MPU_LAR4_S_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_MPU_LAR4_P -// Description : Determines the Privileged/Unprivileged (=1/0) status of -// addresses matching this region, if this region is enabled. -// Writable from any Privileged context, if and only if the S bit -// is clear. Otherwise, writable only from a Secure, Privileged -// context. -#define DMA_MPU_LAR4_P_RESET _u(0x0) -#define DMA_MPU_LAR4_P_BITS _u(0x00000002) -#define DMA_MPU_LAR4_P_MSB _u(1) -#define DMA_MPU_LAR4_P_LSB _u(1) -#define DMA_MPU_LAR4_P_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_MPU_LAR4_EN -// Description : Region enable. If 1, any address within range specified by the -// base address (BAR_ADDR) and limit address (LAR_ADDR) has the -// attributes specified by S and P. -#define DMA_MPU_LAR4_EN_RESET _u(0x0) -#define DMA_MPU_LAR4_EN_BITS _u(0x00000001) -#define DMA_MPU_LAR4_EN_MSB _u(0) -#define DMA_MPU_LAR4_EN_LSB _u(0) -#define DMA_MPU_LAR4_EN_ACCESS "RW" -// ============================================================================= -// Register : DMA_MPU_BAR5 -// Description : Base address register for MPU region 5. Writable only from a -// Secure, Privileged context. -#define DMA_MPU_BAR5_OFFSET _u(0x0000052c) -#define DMA_MPU_BAR5_BITS _u(0xffffffe0) -#define DMA_MPU_BAR5_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : DMA_MPU_BAR5_ADDR -// Description : This MPU region matches addresses where addr[31:5] (the 27 most -// significant bits) are greater than or equal to BAR_ADDR, and -// less than or equal to LAR_ADDR. -// -// Readable from any Privileged context, if and only if this -// region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. -// Otherwise readable only from a Secure, Privileged context. -#define DMA_MPU_BAR5_ADDR_RESET _u(0x0000000) -#define DMA_MPU_BAR5_ADDR_BITS _u(0xffffffe0) -#define DMA_MPU_BAR5_ADDR_MSB _u(31) -#define DMA_MPU_BAR5_ADDR_LSB _u(5) -#define DMA_MPU_BAR5_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_MPU_LAR5 -// Description : Limit address register for MPU region 5. Writable only from a -// Secure, Privileged context, with the exception of the P bit. -#define DMA_MPU_LAR5_OFFSET _u(0x00000530) -#define DMA_MPU_LAR5_BITS _u(0xffffffe7) -#define DMA_MPU_LAR5_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : DMA_MPU_LAR5_ADDR -// Description : Limit address bits 31:5. Readable from any Privileged context, -// if and only if this region's S bit is clear, and -// MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a -// Secure, Privileged context. -#define DMA_MPU_LAR5_ADDR_RESET _u(0x0000000) -#define DMA_MPU_LAR5_ADDR_BITS _u(0xffffffe0) -#define DMA_MPU_LAR5_ADDR_MSB _u(31) -#define DMA_MPU_LAR5_ADDR_LSB _u(5) -#define DMA_MPU_LAR5_ADDR_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_MPU_LAR5_S -// Description : Determines the Secure/Non-secure (=1/0) status of addresses -// matching this region, if this region is enabled. -#define DMA_MPU_LAR5_S_RESET _u(0x0) -#define DMA_MPU_LAR5_S_BITS _u(0x00000004) -#define DMA_MPU_LAR5_S_MSB _u(2) -#define DMA_MPU_LAR5_S_LSB _u(2) -#define DMA_MPU_LAR5_S_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_MPU_LAR5_P -// Description : Determines the Privileged/Unprivileged (=1/0) status of -// addresses matching this region, if this region is enabled. -// Writable from any Privileged context, if and only if the S bit -// is clear. Otherwise, writable only from a Secure, Privileged -// context. -#define DMA_MPU_LAR5_P_RESET _u(0x0) -#define DMA_MPU_LAR5_P_BITS _u(0x00000002) -#define DMA_MPU_LAR5_P_MSB _u(1) -#define DMA_MPU_LAR5_P_LSB _u(1) -#define DMA_MPU_LAR5_P_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_MPU_LAR5_EN -// Description : Region enable. If 1, any address within range specified by the -// base address (BAR_ADDR) and limit address (LAR_ADDR) has the -// attributes specified by S and P. -#define DMA_MPU_LAR5_EN_RESET _u(0x0) -#define DMA_MPU_LAR5_EN_BITS _u(0x00000001) -#define DMA_MPU_LAR5_EN_MSB _u(0) -#define DMA_MPU_LAR5_EN_LSB _u(0) -#define DMA_MPU_LAR5_EN_ACCESS "RW" -// ============================================================================= -// Register : DMA_MPU_BAR6 -// Description : Base address register for MPU region 6. Writable only from a -// Secure, Privileged context. -#define DMA_MPU_BAR6_OFFSET _u(0x00000534) -#define DMA_MPU_BAR6_BITS _u(0xffffffe0) -#define DMA_MPU_BAR6_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : DMA_MPU_BAR6_ADDR -// Description : This MPU region matches addresses where addr[31:5] (the 27 most -// significant bits) are greater than or equal to BAR_ADDR, and -// less than or equal to LAR_ADDR. -// -// Readable from any Privileged context, if and only if this -// region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. -// Otherwise readable only from a Secure, Privileged context. -#define DMA_MPU_BAR6_ADDR_RESET _u(0x0000000) -#define DMA_MPU_BAR6_ADDR_BITS _u(0xffffffe0) -#define DMA_MPU_BAR6_ADDR_MSB _u(31) -#define DMA_MPU_BAR6_ADDR_LSB _u(5) -#define DMA_MPU_BAR6_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_MPU_LAR6 -// Description : Limit address register for MPU region 6. Writable only from a -// Secure, Privileged context, with the exception of the P bit. -#define DMA_MPU_LAR6_OFFSET _u(0x00000538) -#define DMA_MPU_LAR6_BITS _u(0xffffffe7) -#define DMA_MPU_LAR6_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : DMA_MPU_LAR6_ADDR -// Description : Limit address bits 31:5. Readable from any Privileged context, -// if and only if this region's S bit is clear, and -// MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a -// Secure, Privileged context. -#define DMA_MPU_LAR6_ADDR_RESET _u(0x0000000) -#define DMA_MPU_LAR6_ADDR_BITS _u(0xffffffe0) -#define DMA_MPU_LAR6_ADDR_MSB _u(31) -#define DMA_MPU_LAR6_ADDR_LSB _u(5) -#define DMA_MPU_LAR6_ADDR_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_MPU_LAR6_S -// Description : Determines the Secure/Non-secure (=1/0) status of addresses -// matching this region, if this region is enabled. -#define DMA_MPU_LAR6_S_RESET _u(0x0) -#define DMA_MPU_LAR6_S_BITS _u(0x00000004) -#define DMA_MPU_LAR6_S_MSB _u(2) -#define DMA_MPU_LAR6_S_LSB _u(2) -#define DMA_MPU_LAR6_S_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_MPU_LAR6_P -// Description : Determines the Privileged/Unprivileged (=1/0) status of -// addresses matching this region, if this region is enabled. -// Writable from any Privileged context, if and only if the S bit -// is clear. Otherwise, writable only from a Secure, Privileged -// context. -#define DMA_MPU_LAR6_P_RESET _u(0x0) -#define DMA_MPU_LAR6_P_BITS _u(0x00000002) -#define DMA_MPU_LAR6_P_MSB _u(1) -#define DMA_MPU_LAR6_P_LSB _u(1) -#define DMA_MPU_LAR6_P_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_MPU_LAR6_EN -// Description : Region enable. If 1, any address within range specified by the -// base address (BAR_ADDR) and limit address (LAR_ADDR) has the -// attributes specified by S and P. -#define DMA_MPU_LAR6_EN_RESET _u(0x0) -#define DMA_MPU_LAR6_EN_BITS _u(0x00000001) -#define DMA_MPU_LAR6_EN_MSB _u(0) -#define DMA_MPU_LAR6_EN_LSB _u(0) -#define DMA_MPU_LAR6_EN_ACCESS "RW" -// ============================================================================= -// Register : DMA_MPU_BAR7 -// Description : Base address register for MPU region 7. Writable only from a -// Secure, Privileged context. -#define DMA_MPU_BAR7_OFFSET _u(0x0000053c) -#define DMA_MPU_BAR7_BITS _u(0xffffffe0) -#define DMA_MPU_BAR7_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : DMA_MPU_BAR7_ADDR -// Description : This MPU region matches addresses where addr[31:5] (the 27 most -// significant bits) are greater than or equal to BAR_ADDR, and -// less than or equal to LAR_ADDR. -// -// Readable from any Privileged context, if and only if this -// region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. -// Otherwise readable only from a Secure, Privileged context. -#define DMA_MPU_BAR7_ADDR_RESET _u(0x0000000) -#define DMA_MPU_BAR7_ADDR_BITS _u(0xffffffe0) -#define DMA_MPU_BAR7_ADDR_MSB _u(31) -#define DMA_MPU_BAR7_ADDR_LSB _u(5) -#define DMA_MPU_BAR7_ADDR_ACCESS "RW" -// ============================================================================= -// Register : DMA_MPU_LAR7 -// Description : Limit address register for MPU region 7. Writable only from a -// Secure, Privileged context, with the exception of the P bit. -#define DMA_MPU_LAR7_OFFSET _u(0x00000540) -#define DMA_MPU_LAR7_BITS _u(0xffffffe7) -#define DMA_MPU_LAR7_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : DMA_MPU_LAR7_ADDR -// Description : Limit address bits 31:5. Readable from any Privileged context, -// if and only if this region's S bit is clear, and -// MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a -// Secure, Privileged context. -#define DMA_MPU_LAR7_ADDR_RESET _u(0x0000000) -#define DMA_MPU_LAR7_ADDR_BITS _u(0xffffffe0) -#define DMA_MPU_LAR7_ADDR_MSB _u(31) -#define DMA_MPU_LAR7_ADDR_LSB _u(5) -#define DMA_MPU_LAR7_ADDR_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_MPU_LAR7_S -// Description : Determines the Secure/Non-secure (=1/0) status of addresses -// matching this region, if this region is enabled. -#define DMA_MPU_LAR7_S_RESET _u(0x0) -#define DMA_MPU_LAR7_S_BITS _u(0x00000004) -#define DMA_MPU_LAR7_S_MSB _u(2) -#define DMA_MPU_LAR7_S_LSB _u(2) -#define DMA_MPU_LAR7_S_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_MPU_LAR7_P -// Description : Determines the Privileged/Unprivileged (=1/0) status of -// addresses matching this region, if this region is enabled. -// Writable from any Privileged context, if and only if the S bit -// is clear. Otherwise, writable only from a Secure, Privileged -// context. -#define DMA_MPU_LAR7_P_RESET _u(0x0) -#define DMA_MPU_LAR7_P_BITS _u(0x00000002) -#define DMA_MPU_LAR7_P_MSB _u(1) -#define DMA_MPU_LAR7_P_LSB _u(1) -#define DMA_MPU_LAR7_P_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : DMA_MPU_LAR7_EN -// Description : Region enable. If 1, any address within range specified by the -// base address (BAR_ADDR) and limit address (LAR_ADDR) has the -// attributes specified by S and P. -#define DMA_MPU_LAR7_EN_RESET _u(0x0) -#define DMA_MPU_LAR7_EN_BITS _u(0x00000001) -#define DMA_MPU_LAR7_EN_MSB _u(0) -#define DMA_MPU_LAR7_EN_LSB _u(0) -#define DMA_MPU_LAR7_EN_ACCESS "RW" -// ============================================================================= -// Register : DMA_CH0_DBG_CTDREQ -// Description : Read: get channel DREQ counter (i.e. how many accesses the DMA -// expects it can perform on the peripheral without -// overflow/underflow. Write any value: clears the counter, and -// cause channel to re-initiate DREQ handshake. -#define DMA_CH0_DBG_CTDREQ_OFFSET _u(0x00000800) -#define DMA_CH0_DBG_CTDREQ_BITS _u(0x0000003f) -#define DMA_CH0_DBG_CTDREQ_RESET _u(0x00000000) -#define DMA_CH0_DBG_CTDREQ_MSB _u(5) -#define DMA_CH0_DBG_CTDREQ_LSB _u(0) -#define DMA_CH0_DBG_CTDREQ_ACCESS "WC" -// ============================================================================= -// Register : DMA_CH0_DBG_TCR -// Description : Read to get channel TRANS_COUNT reload value, i.e. the length -// of the next transfer -#define DMA_CH0_DBG_TCR_OFFSET _u(0x00000804) -#define DMA_CH0_DBG_TCR_BITS _u(0xffffffff) -#define DMA_CH0_DBG_TCR_RESET _u(0x00000000) -#define DMA_CH0_DBG_TCR_MSB _u(31) -#define DMA_CH0_DBG_TCR_LSB _u(0) -#define DMA_CH0_DBG_TCR_ACCESS "RO" -// ============================================================================= -// Register : DMA_CH1_DBG_CTDREQ -// Description : Read: get channel DREQ counter (i.e. how many accesses the DMA -// expects it can perform on the peripheral without -// overflow/underflow. Write any value: clears the counter, and -// cause channel to re-initiate DREQ handshake. -#define DMA_CH1_DBG_CTDREQ_OFFSET _u(0x00000840) -#define DMA_CH1_DBG_CTDREQ_BITS _u(0x0000003f) -#define DMA_CH1_DBG_CTDREQ_RESET _u(0x00000000) -#define DMA_CH1_DBG_CTDREQ_MSB _u(5) -#define DMA_CH1_DBG_CTDREQ_LSB _u(0) -#define DMA_CH1_DBG_CTDREQ_ACCESS "WC" -// ============================================================================= -// Register : DMA_CH1_DBG_TCR -// Description : Read to get channel TRANS_COUNT reload value, i.e. the length -// of the next transfer -#define DMA_CH1_DBG_TCR_OFFSET _u(0x00000844) -#define DMA_CH1_DBG_TCR_BITS _u(0xffffffff) -#define DMA_CH1_DBG_TCR_RESET _u(0x00000000) -#define DMA_CH1_DBG_TCR_MSB _u(31) -#define DMA_CH1_DBG_TCR_LSB _u(0) -#define DMA_CH1_DBG_TCR_ACCESS "RO" -// ============================================================================= -// Register : DMA_CH2_DBG_CTDREQ -// Description : Read: get channel DREQ counter (i.e. how many accesses the DMA -// expects it can perform on the peripheral without -// overflow/underflow. Write any value: clears the counter, and -// cause channel to re-initiate DREQ handshake. -#define DMA_CH2_DBG_CTDREQ_OFFSET _u(0x00000880) -#define DMA_CH2_DBG_CTDREQ_BITS _u(0x0000003f) -#define DMA_CH2_DBG_CTDREQ_RESET _u(0x00000000) -#define DMA_CH2_DBG_CTDREQ_MSB _u(5) -#define DMA_CH2_DBG_CTDREQ_LSB _u(0) -#define DMA_CH2_DBG_CTDREQ_ACCESS "WC" -// ============================================================================= -// Register : DMA_CH2_DBG_TCR -// Description : Read to get channel TRANS_COUNT reload value, i.e. the length -// of the next transfer -#define DMA_CH2_DBG_TCR_OFFSET _u(0x00000884) -#define DMA_CH2_DBG_TCR_BITS _u(0xffffffff) -#define DMA_CH2_DBG_TCR_RESET _u(0x00000000) -#define DMA_CH2_DBG_TCR_MSB _u(31) -#define DMA_CH2_DBG_TCR_LSB _u(0) -#define DMA_CH2_DBG_TCR_ACCESS "RO" -// ============================================================================= -// Register : DMA_CH3_DBG_CTDREQ -// Description : Read: get channel DREQ counter (i.e. how many accesses the DMA -// expects it can perform on the peripheral without -// overflow/underflow. Write any value: clears the counter, and -// cause channel to re-initiate DREQ handshake. -#define DMA_CH3_DBG_CTDREQ_OFFSET _u(0x000008c0) -#define DMA_CH3_DBG_CTDREQ_BITS _u(0x0000003f) -#define DMA_CH3_DBG_CTDREQ_RESET _u(0x00000000) -#define DMA_CH3_DBG_CTDREQ_MSB _u(5) -#define DMA_CH3_DBG_CTDREQ_LSB _u(0) -#define DMA_CH3_DBG_CTDREQ_ACCESS "WC" -// ============================================================================= -// Register : DMA_CH3_DBG_TCR -// Description : Read to get channel TRANS_COUNT reload value, i.e. the length -// of the next transfer -#define DMA_CH3_DBG_TCR_OFFSET _u(0x000008c4) -#define DMA_CH3_DBG_TCR_BITS _u(0xffffffff) -#define DMA_CH3_DBG_TCR_RESET _u(0x00000000) -#define DMA_CH3_DBG_TCR_MSB _u(31) -#define DMA_CH3_DBG_TCR_LSB _u(0) -#define DMA_CH3_DBG_TCR_ACCESS "RO" -// ============================================================================= -// Register : DMA_CH4_DBG_CTDREQ -// Description : Read: get channel DREQ counter (i.e. how many accesses the DMA -// expects it can perform on the peripheral without -// overflow/underflow. Write any value: clears the counter, and -// cause channel to re-initiate DREQ handshake. -#define DMA_CH4_DBG_CTDREQ_OFFSET _u(0x00000900) -#define DMA_CH4_DBG_CTDREQ_BITS _u(0x0000003f) -#define DMA_CH4_DBG_CTDREQ_RESET _u(0x00000000) -#define DMA_CH4_DBG_CTDREQ_MSB _u(5) -#define DMA_CH4_DBG_CTDREQ_LSB _u(0) -#define DMA_CH4_DBG_CTDREQ_ACCESS "WC" -// ============================================================================= -// Register : DMA_CH4_DBG_TCR -// Description : Read to get channel TRANS_COUNT reload value, i.e. the length -// of the next transfer -#define DMA_CH4_DBG_TCR_OFFSET _u(0x00000904) -#define DMA_CH4_DBG_TCR_BITS _u(0xffffffff) -#define DMA_CH4_DBG_TCR_RESET _u(0x00000000) -#define DMA_CH4_DBG_TCR_MSB _u(31) -#define DMA_CH4_DBG_TCR_LSB _u(0) -#define DMA_CH4_DBG_TCR_ACCESS "RO" -// ============================================================================= -// Register : DMA_CH5_DBG_CTDREQ -// Description : Read: get channel DREQ counter (i.e. how many accesses the DMA -// expects it can perform on the peripheral without -// overflow/underflow. Write any value: clears the counter, and -// cause channel to re-initiate DREQ handshake. -#define DMA_CH5_DBG_CTDREQ_OFFSET _u(0x00000940) -#define DMA_CH5_DBG_CTDREQ_BITS _u(0x0000003f) -#define DMA_CH5_DBG_CTDREQ_RESET _u(0x00000000) -#define DMA_CH5_DBG_CTDREQ_MSB _u(5) -#define DMA_CH5_DBG_CTDREQ_LSB _u(0) -#define DMA_CH5_DBG_CTDREQ_ACCESS "WC" -// ============================================================================= -// Register : DMA_CH5_DBG_TCR -// Description : Read to get channel TRANS_COUNT reload value, i.e. the length -// of the next transfer -#define DMA_CH5_DBG_TCR_OFFSET _u(0x00000944) -#define DMA_CH5_DBG_TCR_BITS _u(0xffffffff) -#define DMA_CH5_DBG_TCR_RESET _u(0x00000000) -#define DMA_CH5_DBG_TCR_MSB _u(31) -#define DMA_CH5_DBG_TCR_LSB _u(0) -#define DMA_CH5_DBG_TCR_ACCESS "RO" -// ============================================================================= -// Register : DMA_CH6_DBG_CTDREQ -// Description : Read: get channel DREQ counter (i.e. how many accesses the DMA -// expects it can perform on the peripheral without -// overflow/underflow. Write any value: clears the counter, and -// cause channel to re-initiate DREQ handshake. -#define DMA_CH6_DBG_CTDREQ_OFFSET _u(0x00000980) -#define DMA_CH6_DBG_CTDREQ_BITS _u(0x0000003f) -#define DMA_CH6_DBG_CTDREQ_RESET _u(0x00000000) -#define DMA_CH6_DBG_CTDREQ_MSB _u(5) -#define DMA_CH6_DBG_CTDREQ_LSB _u(0) -#define DMA_CH6_DBG_CTDREQ_ACCESS "WC" -// ============================================================================= -// Register : DMA_CH6_DBG_TCR -// Description : Read to get channel TRANS_COUNT reload value, i.e. the length -// of the next transfer -#define DMA_CH6_DBG_TCR_OFFSET _u(0x00000984) -#define DMA_CH6_DBG_TCR_BITS _u(0xffffffff) -#define DMA_CH6_DBG_TCR_RESET _u(0x00000000) -#define DMA_CH6_DBG_TCR_MSB _u(31) -#define DMA_CH6_DBG_TCR_LSB _u(0) -#define DMA_CH6_DBG_TCR_ACCESS "RO" -// ============================================================================= -// Register : DMA_CH7_DBG_CTDREQ -// Description : Read: get channel DREQ counter (i.e. how many accesses the DMA -// expects it can perform on the peripheral without -// overflow/underflow. Write any value: clears the counter, and -// cause channel to re-initiate DREQ handshake. -#define DMA_CH7_DBG_CTDREQ_OFFSET _u(0x000009c0) -#define DMA_CH7_DBG_CTDREQ_BITS _u(0x0000003f) -#define DMA_CH7_DBG_CTDREQ_RESET _u(0x00000000) -#define DMA_CH7_DBG_CTDREQ_MSB _u(5) -#define DMA_CH7_DBG_CTDREQ_LSB _u(0) -#define DMA_CH7_DBG_CTDREQ_ACCESS "WC" -// ============================================================================= -// Register : DMA_CH7_DBG_TCR -// Description : Read to get channel TRANS_COUNT reload value, i.e. the length -// of the next transfer -#define DMA_CH7_DBG_TCR_OFFSET _u(0x000009c4) -#define DMA_CH7_DBG_TCR_BITS _u(0xffffffff) -#define DMA_CH7_DBG_TCR_RESET _u(0x00000000) -#define DMA_CH7_DBG_TCR_MSB _u(31) -#define DMA_CH7_DBG_TCR_LSB _u(0) -#define DMA_CH7_DBG_TCR_ACCESS "RO" -// ============================================================================= -// Register : DMA_CH8_DBG_CTDREQ -// Description : Read: get channel DREQ counter (i.e. how many accesses the DMA -// expects it can perform on the peripheral without -// overflow/underflow. Write any value: clears the counter, and -// cause channel to re-initiate DREQ handshake. -#define DMA_CH8_DBG_CTDREQ_OFFSET _u(0x00000a00) -#define DMA_CH8_DBG_CTDREQ_BITS _u(0x0000003f) -#define DMA_CH8_DBG_CTDREQ_RESET _u(0x00000000) -#define DMA_CH8_DBG_CTDREQ_MSB _u(5) -#define DMA_CH8_DBG_CTDREQ_LSB _u(0) -#define DMA_CH8_DBG_CTDREQ_ACCESS "WC" -// ============================================================================= -// Register : DMA_CH8_DBG_TCR -// Description : Read to get channel TRANS_COUNT reload value, i.e. the length -// of the next transfer -#define DMA_CH8_DBG_TCR_OFFSET _u(0x00000a04) -#define DMA_CH8_DBG_TCR_BITS _u(0xffffffff) -#define DMA_CH8_DBG_TCR_RESET _u(0x00000000) -#define DMA_CH8_DBG_TCR_MSB _u(31) -#define DMA_CH8_DBG_TCR_LSB _u(0) -#define DMA_CH8_DBG_TCR_ACCESS "RO" -// ============================================================================= -// Register : DMA_CH9_DBG_CTDREQ -// Description : Read: get channel DREQ counter (i.e. how many accesses the DMA -// expects it can perform on the peripheral without -// overflow/underflow. Write any value: clears the counter, and -// cause channel to re-initiate DREQ handshake. -#define DMA_CH9_DBG_CTDREQ_OFFSET _u(0x00000a40) -#define DMA_CH9_DBG_CTDREQ_BITS _u(0x0000003f) -#define DMA_CH9_DBG_CTDREQ_RESET _u(0x00000000) -#define DMA_CH9_DBG_CTDREQ_MSB _u(5) -#define DMA_CH9_DBG_CTDREQ_LSB _u(0) -#define DMA_CH9_DBG_CTDREQ_ACCESS "WC" -// ============================================================================= -// Register : DMA_CH9_DBG_TCR -// Description : Read to get channel TRANS_COUNT reload value, i.e. the length -// of the next transfer -#define DMA_CH9_DBG_TCR_OFFSET _u(0x00000a44) -#define DMA_CH9_DBG_TCR_BITS _u(0xffffffff) -#define DMA_CH9_DBG_TCR_RESET _u(0x00000000) -#define DMA_CH9_DBG_TCR_MSB _u(31) -#define DMA_CH9_DBG_TCR_LSB _u(0) -#define DMA_CH9_DBG_TCR_ACCESS "RO" -// ============================================================================= -// Register : DMA_CH10_DBG_CTDREQ -// Description : Read: get channel DREQ counter (i.e. how many accesses the DMA -// expects it can perform on the peripheral without -// overflow/underflow. Write any value: clears the counter, and -// cause channel to re-initiate DREQ handshake. -#define DMA_CH10_DBG_CTDREQ_OFFSET _u(0x00000a80) -#define DMA_CH10_DBG_CTDREQ_BITS _u(0x0000003f) -#define DMA_CH10_DBG_CTDREQ_RESET _u(0x00000000) -#define DMA_CH10_DBG_CTDREQ_MSB _u(5) -#define DMA_CH10_DBG_CTDREQ_LSB _u(0) -#define DMA_CH10_DBG_CTDREQ_ACCESS "WC" -// ============================================================================= -// Register : DMA_CH10_DBG_TCR -// Description : Read to get channel TRANS_COUNT reload value, i.e. the length -// of the next transfer -#define DMA_CH10_DBG_TCR_OFFSET _u(0x00000a84) -#define DMA_CH10_DBG_TCR_BITS _u(0xffffffff) -#define DMA_CH10_DBG_TCR_RESET _u(0x00000000) -#define DMA_CH10_DBG_TCR_MSB _u(31) -#define DMA_CH10_DBG_TCR_LSB _u(0) -#define DMA_CH10_DBG_TCR_ACCESS "RO" -// ============================================================================= -// Register : DMA_CH11_DBG_CTDREQ -// Description : Read: get channel DREQ counter (i.e. how many accesses the DMA -// expects it can perform on the peripheral without -// overflow/underflow. Write any value: clears the counter, and -// cause channel to re-initiate DREQ handshake. -#define DMA_CH11_DBG_CTDREQ_OFFSET _u(0x00000ac0) -#define DMA_CH11_DBG_CTDREQ_BITS _u(0x0000003f) -#define DMA_CH11_DBG_CTDREQ_RESET _u(0x00000000) -#define DMA_CH11_DBG_CTDREQ_MSB _u(5) -#define DMA_CH11_DBG_CTDREQ_LSB _u(0) -#define DMA_CH11_DBG_CTDREQ_ACCESS "WC" -// ============================================================================= -// Register : DMA_CH11_DBG_TCR -// Description : Read to get channel TRANS_COUNT reload value, i.e. the length -// of the next transfer -#define DMA_CH11_DBG_TCR_OFFSET _u(0x00000ac4) -#define DMA_CH11_DBG_TCR_BITS _u(0xffffffff) -#define DMA_CH11_DBG_TCR_RESET _u(0x00000000) -#define DMA_CH11_DBG_TCR_MSB _u(31) -#define DMA_CH11_DBG_TCR_LSB _u(0) -#define DMA_CH11_DBG_TCR_ACCESS "RO" -// ============================================================================= -// Register : DMA_CH12_DBG_CTDREQ -// Description : Read: get channel DREQ counter (i.e. how many accesses the DMA -// expects it can perform on the peripheral without -// overflow/underflow. Write any value: clears the counter, and -// cause channel to re-initiate DREQ handshake. -#define DMA_CH12_DBG_CTDREQ_OFFSET _u(0x00000b00) -#define DMA_CH12_DBG_CTDREQ_BITS _u(0x0000003f) -#define DMA_CH12_DBG_CTDREQ_RESET _u(0x00000000) -#define DMA_CH12_DBG_CTDREQ_MSB _u(5) -#define DMA_CH12_DBG_CTDREQ_LSB _u(0) -#define DMA_CH12_DBG_CTDREQ_ACCESS "WC" -// ============================================================================= -// Register : DMA_CH12_DBG_TCR -// Description : Read to get channel TRANS_COUNT reload value, i.e. the length -// of the next transfer -#define DMA_CH12_DBG_TCR_OFFSET _u(0x00000b04) -#define DMA_CH12_DBG_TCR_BITS _u(0xffffffff) -#define DMA_CH12_DBG_TCR_RESET _u(0x00000000) -#define DMA_CH12_DBG_TCR_MSB _u(31) -#define DMA_CH12_DBG_TCR_LSB _u(0) -#define DMA_CH12_DBG_TCR_ACCESS "RO" -// ============================================================================= -// Register : DMA_CH13_DBG_CTDREQ -// Description : Read: get channel DREQ counter (i.e. how many accesses the DMA -// expects it can perform on the peripheral without -// overflow/underflow. Write any value: clears the counter, and -// cause channel to re-initiate DREQ handshake. -#define DMA_CH13_DBG_CTDREQ_OFFSET _u(0x00000b40) -#define DMA_CH13_DBG_CTDREQ_BITS _u(0x0000003f) -#define DMA_CH13_DBG_CTDREQ_RESET _u(0x00000000) -#define DMA_CH13_DBG_CTDREQ_MSB _u(5) -#define DMA_CH13_DBG_CTDREQ_LSB _u(0) -#define DMA_CH13_DBG_CTDREQ_ACCESS "WC" -// ============================================================================= -// Register : DMA_CH13_DBG_TCR -// Description : Read to get channel TRANS_COUNT reload value, i.e. the length -// of the next transfer -#define DMA_CH13_DBG_TCR_OFFSET _u(0x00000b44) -#define DMA_CH13_DBG_TCR_BITS _u(0xffffffff) -#define DMA_CH13_DBG_TCR_RESET _u(0x00000000) -#define DMA_CH13_DBG_TCR_MSB _u(31) -#define DMA_CH13_DBG_TCR_LSB _u(0) -#define DMA_CH13_DBG_TCR_ACCESS "RO" -// ============================================================================= -// Register : DMA_CH14_DBG_CTDREQ -// Description : Read: get channel DREQ counter (i.e. how many accesses the DMA -// expects it can perform on the peripheral without -// overflow/underflow. Write any value: clears the counter, and -// cause channel to re-initiate DREQ handshake. -#define DMA_CH14_DBG_CTDREQ_OFFSET _u(0x00000b80) -#define DMA_CH14_DBG_CTDREQ_BITS _u(0x0000003f) -#define DMA_CH14_DBG_CTDREQ_RESET _u(0x00000000) -#define DMA_CH14_DBG_CTDREQ_MSB _u(5) -#define DMA_CH14_DBG_CTDREQ_LSB _u(0) -#define DMA_CH14_DBG_CTDREQ_ACCESS "WC" -// ============================================================================= -// Register : DMA_CH14_DBG_TCR -// Description : Read to get channel TRANS_COUNT reload value, i.e. the length -// of the next transfer -#define DMA_CH14_DBG_TCR_OFFSET _u(0x00000b84) -#define DMA_CH14_DBG_TCR_BITS _u(0xffffffff) -#define DMA_CH14_DBG_TCR_RESET _u(0x00000000) -#define DMA_CH14_DBG_TCR_MSB _u(31) -#define DMA_CH14_DBG_TCR_LSB _u(0) -#define DMA_CH14_DBG_TCR_ACCESS "RO" -// ============================================================================= -// Register : DMA_CH15_DBG_CTDREQ -// Description : Read: get channel DREQ counter (i.e. how many accesses the DMA -// expects it can perform on the peripheral without -// overflow/underflow. Write any value: clears the counter, and -// cause channel to re-initiate DREQ handshake. -#define DMA_CH15_DBG_CTDREQ_OFFSET _u(0x00000bc0) -#define DMA_CH15_DBG_CTDREQ_BITS _u(0x0000003f) -#define DMA_CH15_DBG_CTDREQ_RESET _u(0x00000000) -#define DMA_CH15_DBG_CTDREQ_MSB _u(5) -#define DMA_CH15_DBG_CTDREQ_LSB _u(0) -#define DMA_CH15_DBG_CTDREQ_ACCESS "WC" -// ============================================================================= -// Register : DMA_CH15_DBG_TCR -// Description : Read to get channel TRANS_COUNT reload value, i.e. the length -// of the next transfer -#define DMA_CH15_DBG_TCR_OFFSET _u(0x00000bc4) -#define DMA_CH15_DBG_TCR_BITS _u(0xffffffff) -#define DMA_CH15_DBG_TCR_RESET _u(0x00000000) -#define DMA_CH15_DBG_TCR_MSB _u(31) -#define DMA_CH15_DBG_TCR_LSB _u(0) -#define DMA_CH15_DBG_TCR_ACCESS "RO" -// ============================================================================= -#endif // _HARDWARE_REGS_DMA_H - diff --git a/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/dreq.h b/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/dreq.h deleted file mode 100644 index 6d126c0df8..0000000000 --- a/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/dreq.h +++ /dev/null @@ -1,147 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _DREQ_H -#define _DREQ_H - -/** - * \file rp2350/dreq.h - */ - -#ifdef __ASSEMBLER__ -#define DREQ_PIO0_TX0 0 -#define DREQ_PIO0_TX1 1 -#define DREQ_PIO0_TX2 2 -#define DREQ_PIO0_TX3 3 -#define DREQ_PIO0_RX0 4 -#define DREQ_PIO0_RX1 5 -#define DREQ_PIO0_RX2 6 -#define DREQ_PIO0_RX3 7 -#define DREQ_PIO1_TX0 8 -#define DREQ_PIO1_TX1 9 -#define DREQ_PIO1_TX2 10 -#define DREQ_PIO1_TX3 11 -#define DREQ_PIO1_RX0 12 -#define DREQ_PIO1_RX1 13 -#define DREQ_PIO1_RX2 14 -#define DREQ_PIO1_RX3 15 -#define DREQ_PIO2_TX0 16 -#define DREQ_PIO2_TX1 17 -#define DREQ_PIO2_TX2 18 -#define DREQ_PIO2_TX3 19 -#define DREQ_PIO2_RX0 20 -#define DREQ_PIO2_RX1 21 -#define DREQ_PIO2_RX2 22 -#define DREQ_PIO2_RX3 23 -#define DREQ_SPI0_TX 24 -#define DREQ_SPI0_RX 25 -#define DREQ_SPI1_TX 26 -#define DREQ_SPI1_RX 27 -#define DREQ_UART0_TX 28 -#define DREQ_UART0_RX 29 -#define DREQ_UART1_TX 30 -#define DREQ_UART1_RX 31 -#define DREQ_PWM_WRAP0 32 -#define DREQ_PWM_WRAP1 33 -#define DREQ_PWM_WRAP2 34 -#define DREQ_PWM_WRAP3 35 -#define DREQ_PWM_WRAP4 36 -#define DREQ_PWM_WRAP5 37 -#define DREQ_PWM_WRAP6 38 -#define DREQ_PWM_WRAP7 39 -#define DREQ_PWM_WRAP8 40 -#define DREQ_PWM_WRAP9 41 -#define DREQ_PWM_WRAP10 42 -#define DREQ_PWM_WRAP11 43 -#define DREQ_I2C0_TX 44 -#define DREQ_I2C0_RX 45 -#define DREQ_I2C1_TX 46 -#define DREQ_I2C1_RX 47 -#define DREQ_ADC 48 -#define DREQ_XIP_STREAM 49 -#define DREQ_XIP_QMITX 50 -#define DREQ_XIP_QMIRX 51 -#define DREQ_HSTX 52 -#define DREQ_CORESIGHT 53 -#define DREQ_SHA256 54 -#define DREQ_DMA_TIMER0 59 -#define DREQ_DMA_TIMER1 60 -#define DREQ_DMA_TIMER2 61 -#define DREQ_DMA_TIMER3 62 -#define DREQ_FORCE 63 -#else -/** - * \brief DREQ numbers for DMA pacing on RP2350 (used as typedef \ref dreq_num_t) - * \ingroup hardware_dma - */ -typedef enum dreq_num_rp2350 { - DREQ_PIO0_TX0 = 0, ///< Select PIO0's TX FIFO 0 as DREQ - DREQ_PIO0_TX1 = 1, ///< Select PIO0's TX FIFO 1 as DREQ - DREQ_PIO0_TX2 = 2, ///< Select PIO0's TX FIFO 2 as DREQ - DREQ_PIO0_TX3 = 3, ///< Select PIO0's TX FIFO 3 as DREQ - DREQ_PIO0_RX0 = 4, ///< Select PIO0's RX FIFO 0 as DREQ - DREQ_PIO0_RX1 = 5, ///< Select PIO0's RX FIFO 1 as DREQ - DREQ_PIO0_RX2 = 6, ///< Select PIO0's RX FIFO 2 as DREQ - DREQ_PIO0_RX3 = 7, ///< Select PIO0's RX FIFO 3 as DREQ - DREQ_PIO1_TX0 = 8, ///< Select PIO1's TX FIFO 0 as DREQ - DREQ_PIO1_TX1 = 9, ///< Select PIO1's TX FIFO 1 as DREQ - DREQ_PIO1_TX2 = 10, ///< Select PIO1's TX FIFO 2 as DREQ - DREQ_PIO1_TX3 = 11, ///< Select PIO1's TX FIFO 3 as DREQ - DREQ_PIO1_RX0 = 12, ///< Select PIO1's RX FIFO 0 as DREQ - DREQ_PIO1_RX1 = 13, ///< Select PIO1's RX FIFO 1 as DREQ - DREQ_PIO1_RX2 = 14, ///< Select PIO1's RX FIFO 2 as DREQ - DREQ_PIO1_RX3 = 15, ///< Select PIO1's RX FIFO 3 as DREQ - DREQ_PIO2_TX0 = 16, ///< Select PIO2's TX FIFO 0 as DREQ - DREQ_PIO2_TX1 = 17, ///< Select PIO2's TX FIFO 1 as DREQ - DREQ_PIO2_TX2 = 18, ///< Select PIO2's TX FIFO 2 as DREQ - DREQ_PIO2_TX3 = 19, ///< Select PIO2's TX FIFO 3 as DREQ - DREQ_PIO2_RX0 = 20, ///< Select PIO2's RX FIFO 0 as DREQ - DREQ_PIO2_RX1 = 21, ///< Select PIO2's RX FIFO 1 as DREQ - DREQ_PIO2_RX2 = 22, ///< Select PIO2's RX FIFO 2 as DREQ - DREQ_PIO2_RX3 = 23, ///< Select PIO2's RX FIFO 3 as DREQ - DREQ_SPI0_TX = 24, ///< Select SPI0's TX FIFO as DREQ - DREQ_SPI0_RX = 25, ///< Select SPI0's RX FIFO as DREQ - DREQ_SPI1_TX = 26, ///< Select SPI1's TX FIFO as DREQ - DREQ_SPI1_RX = 27, ///< Select SPI1's RX FIFO as DREQ - DREQ_UART0_TX = 28, ///< Select UART0's TX FIFO as DREQ - DREQ_UART0_RX = 29, ///< Select UART0's RX FIFO as DREQ - DREQ_UART1_TX = 30, ///< Select UART1's TX FIFO as DREQ - DREQ_UART1_RX = 31, ///< Select UART1's RX FIFO as DREQ - DREQ_PWM_WRAP0 = 32, ///< Select PWM Counter 0's Wrap Value as DREQ - DREQ_PWM_WRAP1 = 33, ///< Select PWM Counter 1's Wrap Value as DREQ - DREQ_PWM_WRAP2 = 34, ///< Select PWM Counter 2's Wrap Value as DREQ - DREQ_PWM_WRAP3 = 35, ///< Select PWM Counter 3's Wrap Value as DREQ - DREQ_PWM_WRAP4 = 36, ///< Select PWM Counter 4's Wrap Value as DREQ - DREQ_PWM_WRAP5 = 37, ///< Select PWM Counter 5's Wrap Value as DREQ - DREQ_PWM_WRAP6 = 38, ///< Select PWM Counter 6's Wrap Value as DREQ - DREQ_PWM_WRAP7 = 39, ///< Select PWM Counter 7's Wrap Value as DREQ - DREQ_PWM_WRAP8 = 40, ///< Select PWM Counter 8's Wrap Value as DREQ - DREQ_PWM_WRAP9 = 41, ///< Select PWM Counter 9's Wrap Value as DREQ - DREQ_PWM_WRAP10 = 42, ///< Select PWM Counter 0's Wrap Value as DREQ - DREQ_PWM_WRAP11 = 43, ///< Select PWM Counter 1's Wrap Value as DREQ - DREQ_I2C0_TX = 44, ///< Select I2C0's TX FIFO as DREQ - DREQ_I2C0_RX = 45, ///< Select I2C0's RX FIFO as DREQ - DREQ_I2C1_TX = 46, ///< Select I2C1's TX FIFO as DREQ - DREQ_I2C1_RX = 47, ///< Select I2C1's RX FIFO as DREQ - DREQ_ADC = 48, ///< Select the ADC as DREQ - DREQ_XIP_STREAM = 49, ///< Select the XIP Streaming FIFO as DREQ - DREQ_XIP_QMITX = 50, ///< Select XIP_QMITX as DREQ - DREQ_XIP_QMIRX = 51, ///< Select XIP_QMIRX as DREQ - DREQ_HSTX = 52, ///< Select HSTX as DREQ - DREQ_CORESIGHT = 53, ///< Select CORESIGHT as DREQ - DREQ_SHA256 = 54, ///< Select SHA256 as DREQ - DREQ_DMA_TIMER0 = 59, ///< Select DMA_TIMER0 as DREQ - DREQ_DMA_TIMER1 = 60, ///< Select DMA_TIMER0 as DREQ - DREQ_DMA_TIMER2 = 61, ///< Select DMA_TIMER1 as DREQ - DREQ_DMA_TIMER3 = 62, ///< Select DMA_TIMER3 as DREQ - DREQ_FORCE = 63, ///< Select FORCE as DREQ - DREQ_COUNT -} dreq_num_t; -#endif - -#endif // _DREQ_H - diff --git a/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/glitch_detector.h b/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/glitch_detector.h deleted file mode 100644 index efdf434b3f..0000000000 --- a/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/glitch_detector.h +++ /dev/null @@ -1,213 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -// ============================================================================= -// Register block : GLITCH_DETECTOR -// Version : 1 -// Bus type : apb -// Description : Glitch detector controls -// ============================================================================= -#ifndef _HARDWARE_REGS_GLITCH_DETECTOR_H -#define _HARDWARE_REGS_GLITCH_DETECTOR_H -// ============================================================================= -// Register : GLITCH_DETECTOR_ARM -// Description : Forcibly arm the glitch detectors, if they are not already -// armed by OTP. When armed, any individual detector trigger will -// cause a restart of the switched core power domain's power-on -// reset state machine. -// -// Glitch detector triggers are recorded accumulatively in -// TRIG_STATUS. If the system is reset by a glitch detector -// trigger, this is recorded in POWMAN_CHIP_RESET. -// -// This register is Secure read/write only. -// 0x5bad -> Do not force the glitch detectors to be armed -// 0x0000 -> Force the glitch detectors to be armed. (Any value other than ARM_NO counts as YES) -#define GLITCH_DETECTOR_ARM_OFFSET _u(0x00000000) -#define GLITCH_DETECTOR_ARM_BITS _u(0x0000ffff) -#define GLITCH_DETECTOR_ARM_RESET _u(0x00005bad) -#define GLITCH_DETECTOR_ARM_MSB _u(15) -#define GLITCH_DETECTOR_ARM_LSB _u(0) -#define GLITCH_DETECTOR_ARM_ACCESS "RW" -#define GLITCH_DETECTOR_ARM_VALUE_NO _u(0x5bad) -#define GLITCH_DETECTOR_ARM_VALUE_YES _u(0x0000) -// ============================================================================= -// Register : GLITCH_DETECTOR_DISARM -// Description : None -// Forcibly disarm the glitch detectors, if they are armed by OTP. -// Ignored if ARM is YES. -// -// This register is Secure read/write only. -// 0x0000 -> Do not disarm the glitch detectors. (Any value other than DISARM_YES counts as NO) -// 0xdcaf -> Disarm the glitch detectors -#define GLITCH_DETECTOR_DISARM_OFFSET _u(0x00000004) -#define GLITCH_DETECTOR_DISARM_BITS _u(0x0000ffff) -#define GLITCH_DETECTOR_DISARM_RESET _u(0x00000000) -#define GLITCH_DETECTOR_DISARM_MSB _u(15) -#define GLITCH_DETECTOR_DISARM_LSB _u(0) -#define GLITCH_DETECTOR_DISARM_ACCESS "RW" -#define GLITCH_DETECTOR_DISARM_VALUE_NO _u(0x0000) -#define GLITCH_DETECTOR_DISARM_VALUE_YES _u(0xdcaf) -// ============================================================================= -// Register : GLITCH_DETECTOR_SENSITIVITY -// Description : Adjust the sensitivity of glitch detectors to values other than -// their OTP-provided defaults. -// -// This register is Secure read/write only. -#define GLITCH_DETECTOR_SENSITIVITY_OFFSET _u(0x00000008) -#define GLITCH_DETECTOR_SENSITIVITY_BITS _u(0xff00ffff) -#define GLITCH_DETECTOR_SENSITIVITY_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : GLITCH_DETECTOR_SENSITIVITY_DEFAULT -// 0x00 -> Use the default sensitivity configured in OTP for all detectors. (Any value other than DEFAULT_NO counts as YES) -// 0xde -> Do not use the default sensitivity configured in OTP. Instead use the value from this register. -#define GLITCH_DETECTOR_SENSITIVITY_DEFAULT_RESET _u(0x00) -#define GLITCH_DETECTOR_SENSITIVITY_DEFAULT_BITS _u(0xff000000) -#define GLITCH_DETECTOR_SENSITIVITY_DEFAULT_MSB _u(31) -#define GLITCH_DETECTOR_SENSITIVITY_DEFAULT_LSB _u(24) -#define GLITCH_DETECTOR_SENSITIVITY_DEFAULT_ACCESS "RW" -#define GLITCH_DETECTOR_SENSITIVITY_DEFAULT_VALUE_YES _u(0x00) -#define GLITCH_DETECTOR_SENSITIVITY_DEFAULT_VALUE_NO _u(0xde) -// ----------------------------------------------------------------------------- -// Field : GLITCH_DETECTOR_SENSITIVITY_DET3_INV -// Description : Must be the inverse of DET3, else the default value is used. -#define GLITCH_DETECTOR_SENSITIVITY_DET3_INV_RESET _u(0x0) -#define GLITCH_DETECTOR_SENSITIVITY_DET3_INV_BITS _u(0x0000c000) -#define GLITCH_DETECTOR_SENSITIVITY_DET3_INV_MSB _u(15) -#define GLITCH_DETECTOR_SENSITIVITY_DET3_INV_LSB _u(14) -#define GLITCH_DETECTOR_SENSITIVITY_DET3_INV_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : GLITCH_DETECTOR_SENSITIVITY_DET2_INV -// Description : Must be the inverse of DET2, else the default value is used. -#define GLITCH_DETECTOR_SENSITIVITY_DET2_INV_RESET _u(0x0) -#define GLITCH_DETECTOR_SENSITIVITY_DET2_INV_BITS _u(0x00003000) -#define GLITCH_DETECTOR_SENSITIVITY_DET2_INV_MSB _u(13) -#define GLITCH_DETECTOR_SENSITIVITY_DET2_INV_LSB _u(12) -#define GLITCH_DETECTOR_SENSITIVITY_DET2_INV_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : GLITCH_DETECTOR_SENSITIVITY_DET1_INV -// Description : Must be the inverse of DET1, else the default value is used. -#define GLITCH_DETECTOR_SENSITIVITY_DET1_INV_RESET _u(0x0) -#define GLITCH_DETECTOR_SENSITIVITY_DET1_INV_BITS _u(0x00000c00) -#define GLITCH_DETECTOR_SENSITIVITY_DET1_INV_MSB _u(11) -#define GLITCH_DETECTOR_SENSITIVITY_DET1_INV_LSB _u(10) -#define GLITCH_DETECTOR_SENSITIVITY_DET1_INV_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : GLITCH_DETECTOR_SENSITIVITY_DET0_INV -// Description : Must be the inverse of DET0, else the default value is used. -#define GLITCH_DETECTOR_SENSITIVITY_DET0_INV_RESET _u(0x0) -#define GLITCH_DETECTOR_SENSITIVITY_DET0_INV_BITS _u(0x00000300) -#define GLITCH_DETECTOR_SENSITIVITY_DET0_INV_MSB _u(9) -#define GLITCH_DETECTOR_SENSITIVITY_DET0_INV_LSB _u(8) -#define GLITCH_DETECTOR_SENSITIVITY_DET0_INV_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : GLITCH_DETECTOR_SENSITIVITY_DET3 -// Description : Set sensitivity for detector 3. Higher values are more -// sensitive. -#define GLITCH_DETECTOR_SENSITIVITY_DET3_RESET _u(0x0) -#define GLITCH_DETECTOR_SENSITIVITY_DET3_BITS _u(0x000000c0) -#define GLITCH_DETECTOR_SENSITIVITY_DET3_MSB _u(7) -#define GLITCH_DETECTOR_SENSITIVITY_DET3_LSB _u(6) -#define GLITCH_DETECTOR_SENSITIVITY_DET3_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : GLITCH_DETECTOR_SENSITIVITY_DET2 -// Description : Set sensitivity for detector 2. Higher values are more -// sensitive. -#define GLITCH_DETECTOR_SENSITIVITY_DET2_RESET _u(0x0) -#define GLITCH_DETECTOR_SENSITIVITY_DET2_BITS _u(0x00000030) -#define GLITCH_DETECTOR_SENSITIVITY_DET2_MSB _u(5) -#define GLITCH_DETECTOR_SENSITIVITY_DET2_LSB _u(4) -#define GLITCH_DETECTOR_SENSITIVITY_DET2_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : GLITCH_DETECTOR_SENSITIVITY_DET1 -// Description : Set sensitivity for detector 1. Higher values are more -// sensitive. -#define GLITCH_DETECTOR_SENSITIVITY_DET1_RESET _u(0x0) -#define GLITCH_DETECTOR_SENSITIVITY_DET1_BITS _u(0x0000000c) -#define GLITCH_DETECTOR_SENSITIVITY_DET1_MSB _u(3) -#define GLITCH_DETECTOR_SENSITIVITY_DET1_LSB _u(2) -#define GLITCH_DETECTOR_SENSITIVITY_DET1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : GLITCH_DETECTOR_SENSITIVITY_DET0 -// Description : Set sensitivity for detector 0. Higher values are more -// sensitive. -#define GLITCH_DETECTOR_SENSITIVITY_DET0_RESET _u(0x0) -#define GLITCH_DETECTOR_SENSITIVITY_DET0_BITS _u(0x00000003) -#define GLITCH_DETECTOR_SENSITIVITY_DET0_MSB _u(1) -#define GLITCH_DETECTOR_SENSITIVITY_DET0_LSB _u(0) -#define GLITCH_DETECTOR_SENSITIVITY_DET0_ACCESS "RW" -// ============================================================================= -// Register : GLITCH_DETECTOR_LOCK -// Description : None -// Write any nonzero value to disable writes to ARM, DISARM, -// SENSITIVITY and LOCK. This register is Secure read/write only. -#define GLITCH_DETECTOR_LOCK_OFFSET _u(0x0000000c) -#define GLITCH_DETECTOR_LOCK_BITS _u(0x000000ff) -#define GLITCH_DETECTOR_LOCK_RESET _u(0x00000000) -#define GLITCH_DETECTOR_LOCK_MSB _u(7) -#define GLITCH_DETECTOR_LOCK_LSB _u(0) -#define GLITCH_DETECTOR_LOCK_ACCESS "RW" -// ============================================================================= -// Register : GLITCH_DETECTOR_TRIG_STATUS -// Description : Set when a detector output triggers. Write-1-clear. -// -// (May immediately return high if the detector remains in a -// failed state. Detectors can only be cleared by a full reset of -// the switched core power domain.) -// -// This register is Secure read/write only. -#define GLITCH_DETECTOR_TRIG_STATUS_OFFSET _u(0x00000010) -#define GLITCH_DETECTOR_TRIG_STATUS_BITS _u(0x0000000f) -#define GLITCH_DETECTOR_TRIG_STATUS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : GLITCH_DETECTOR_TRIG_STATUS_DET3 -#define GLITCH_DETECTOR_TRIG_STATUS_DET3_RESET _u(0x0) -#define GLITCH_DETECTOR_TRIG_STATUS_DET3_BITS _u(0x00000008) -#define GLITCH_DETECTOR_TRIG_STATUS_DET3_MSB _u(3) -#define GLITCH_DETECTOR_TRIG_STATUS_DET3_LSB _u(3) -#define GLITCH_DETECTOR_TRIG_STATUS_DET3_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : GLITCH_DETECTOR_TRIG_STATUS_DET2 -#define GLITCH_DETECTOR_TRIG_STATUS_DET2_RESET _u(0x0) -#define GLITCH_DETECTOR_TRIG_STATUS_DET2_BITS _u(0x00000004) -#define GLITCH_DETECTOR_TRIG_STATUS_DET2_MSB _u(2) -#define GLITCH_DETECTOR_TRIG_STATUS_DET2_LSB _u(2) -#define GLITCH_DETECTOR_TRIG_STATUS_DET2_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : GLITCH_DETECTOR_TRIG_STATUS_DET1 -#define GLITCH_DETECTOR_TRIG_STATUS_DET1_RESET _u(0x0) -#define GLITCH_DETECTOR_TRIG_STATUS_DET1_BITS _u(0x00000002) -#define GLITCH_DETECTOR_TRIG_STATUS_DET1_MSB _u(1) -#define GLITCH_DETECTOR_TRIG_STATUS_DET1_LSB _u(1) -#define GLITCH_DETECTOR_TRIG_STATUS_DET1_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : GLITCH_DETECTOR_TRIG_STATUS_DET0 -#define GLITCH_DETECTOR_TRIG_STATUS_DET0_RESET _u(0x0) -#define GLITCH_DETECTOR_TRIG_STATUS_DET0_BITS _u(0x00000001) -#define GLITCH_DETECTOR_TRIG_STATUS_DET0_MSB _u(0) -#define GLITCH_DETECTOR_TRIG_STATUS_DET0_LSB _u(0) -#define GLITCH_DETECTOR_TRIG_STATUS_DET0_ACCESS "WC" -// ============================================================================= -// Register : GLITCH_DETECTOR_TRIG_FORCE -// Description : Simulate the firing of one or more detectors. Writing ones to -// this register will set the matching bits in STATUS_TRIG. -// -// If the glitch detectors are currently armed, writing ones will -// also immediately reset the switched core power domain, and set -// the reset reason latches in POWMAN_CHIP_RESET to indicate a -// glitch detector resets. -// -// This register is Secure read/write only. -#define GLITCH_DETECTOR_TRIG_FORCE_OFFSET _u(0x00000014) -#define GLITCH_DETECTOR_TRIG_FORCE_BITS _u(0x0000000f) -#define GLITCH_DETECTOR_TRIG_FORCE_RESET _u(0x00000000) -#define GLITCH_DETECTOR_TRIG_FORCE_MSB _u(3) -#define GLITCH_DETECTOR_TRIG_FORCE_LSB _u(0) -#define GLITCH_DETECTOR_TRIG_FORCE_ACCESS "SC" -// ============================================================================= -#endif // _HARDWARE_REGS_GLITCH_DETECTOR_H - diff --git a/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/hstx_ctrl.h b/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/hstx_ctrl.h deleted file mode 100644 index 8f21304451..0000000000 --- a/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/hstx_ctrl.h +++ /dev/null @@ -1,609 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -// ============================================================================= -// Register block : HSTX_CTRL -// Version : 0 -// Bus type : apb -// Description : Control interface to HSTX. For FIFO write access and status, -// see the HSTX_FIFO register block. -// ============================================================================= -#ifndef _HARDWARE_REGS_HSTX_CTRL_H -#define _HARDWARE_REGS_HSTX_CTRL_H -// ============================================================================= -// Register : HSTX_CTRL_CSR -#define HSTX_CTRL_CSR_OFFSET _u(0x00000000) -#define HSTX_CTRL_CSR_BITS _u(0xff1f1f73) -#define HSTX_CTRL_CSR_RESET _u(0x10050600) -// ----------------------------------------------------------------------------- -// Field : HSTX_CTRL_CSR_CLKDIV -// Description : Clock period of the generated clock, measured in HSTX clock -// cycles. Can be odd or even. The generated clock advances only -// on cycles where the shift register shifts. -// -// For example, a clkdiv of 5 would generate a complete output -// clock period for every 5 HSTX clocks (or every 10 half-clocks). -// -// A CLKDIV value of 0 is mapped to a period of 16 HSTX clock -// cycles. -#define HSTX_CTRL_CSR_CLKDIV_RESET _u(0x1) -#define HSTX_CTRL_CSR_CLKDIV_BITS _u(0xf0000000) -#define HSTX_CTRL_CSR_CLKDIV_MSB _u(31) -#define HSTX_CTRL_CSR_CLKDIV_LSB _u(28) -#define HSTX_CTRL_CSR_CLKDIV_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : HSTX_CTRL_CSR_CLKPHASE -// Description : Set the initial phase of the generated clock. -// -// A CLKPHASE of 0 means the clock is initially low, and the first -// rising edge occurs after one half period of the generated clock -// (i.e. CLKDIV/2 cycles of clk_hstx). Incrementing CLKPHASE by 1 -// will advance the initial clock phase by one half clk_hstx -// period. For example, if CLKDIV=2 and CLKPHASE=1: -// -// * The clock will be initially low -// -// * The first rising edge will be 0.5 clk_hstx cycles after -// asserting first data -// -// * The first falling edge will be 1.5 clk_hstx cycles after -// asserting first data -// -// This configuration would be suitable for serialising at a bit -// rate of clk_hstx with a centre-aligned DDR clock. -// -// When the HSTX is halted by clearing CSR_EN, the clock generator -// will return to its initial phase as configured by the CLKPHASE -// field. -// -// Note CLKPHASE must be strictly less than double the value of -// CLKDIV (one full period), else its operation is undefined. -#define HSTX_CTRL_CSR_CLKPHASE_RESET _u(0x0) -#define HSTX_CTRL_CSR_CLKPHASE_BITS _u(0x0f000000) -#define HSTX_CTRL_CSR_CLKPHASE_MSB _u(27) -#define HSTX_CTRL_CSR_CLKPHASE_LSB _u(24) -#define HSTX_CTRL_CSR_CLKPHASE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : HSTX_CTRL_CSR_N_SHIFTS -// Description : Number of times to shift the shift register before refilling it -// from the FIFO. (A count of how many times it has been shifted, -// *not* the total shift distance.) -// -// A register value of 0 means shift 32 times. -#define HSTX_CTRL_CSR_N_SHIFTS_RESET _u(0x05) -#define HSTX_CTRL_CSR_N_SHIFTS_BITS _u(0x001f0000) -#define HSTX_CTRL_CSR_N_SHIFTS_MSB _u(20) -#define HSTX_CTRL_CSR_N_SHIFTS_LSB _u(16) -#define HSTX_CTRL_CSR_N_SHIFTS_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : HSTX_CTRL_CSR_SHIFT -// Description : How many bits to right-rotate the shift register by each cycle. -// -// The use of a rotate rather than a shift allows left shifts to -// be emulated, by subtracting the left-shift amount from 32. It -// also allows data to be repeated, when the product of SHIFT and -// N_SHIFTS is greater than 32. -#define HSTX_CTRL_CSR_SHIFT_RESET _u(0x06) -#define HSTX_CTRL_CSR_SHIFT_BITS _u(0x00001f00) -#define HSTX_CTRL_CSR_SHIFT_MSB _u(12) -#define HSTX_CTRL_CSR_SHIFT_LSB _u(8) -#define HSTX_CTRL_CSR_SHIFT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : HSTX_CTRL_CSR_COUPLED_SEL -// Description : Select which PIO to use for coupled mode operation. -#define HSTX_CTRL_CSR_COUPLED_SEL_RESET _u(0x0) -#define HSTX_CTRL_CSR_COUPLED_SEL_BITS _u(0x00000060) -#define HSTX_CTRL_CSR_COUPLED_SEL_MSB _u(6) -#define HSTX_CTRL_CSR_COUPLED_SEL_LSB _u(5) -#define HSTX_CTRL_CSR_COUPLED_SEL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : HSTX_CTRL_CSR_COUPLED_MODE -// Description : Enable the PIO-to-HSTX 1:1 connection. The HSTX must be clocked -// *directly* from the system clock (not just from some other -// clock source of the same frequency) for this synchronous -// interface to function correctly. -// -// When COUPLED_MODE is set, BITx_SEL_P and SEL_N indices 24 -// through 31 will select bits from the 8-bit PIO-to-HSTX path, -// rather than shifter bits. Indices of 0 through 23 will still -// index the shift register as normal. -// -// The PIO outputs connected to the PIO-to-HSTX bus are those same -// outputs that would appear on the HSTX-capable pins if those -// pins' FUNCSELs were set to PIO instead of HSTX. -// -// For example, if HSTX is on GPIOs 12 through 19, then PIO -// outputs 12 through 19 are connected to the HSTX when coupled -// mode is engaged. -#define HSTX_CTRL_CSR_COUPLED_MODE_RESET _u(0x0) -#define HSTX_CTRL_CSR_COUPLED_MODE_BITS _u(0x00000010) -#define HSTX_CTRL_CSR_COUPLED_MODE_MSB _u(4) -#define HSTX_CTRL_CSR_COUPLED_MODE_LSB _u(4) -#define HSTX_CTRL_CSR_COUPLED_MODE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : HSTX_CTRL_CSR_EXPAND_EN -// Description : Enable the command expander. When 0, raw FIFO data is passed -// directly to the output shift register. When 1, the command -// expander can perform simple operations such as run length -// decoding on data between the FIFO and the shift register. -// -// Do not change CXPD_EN whilst EN is set. It's safe to set -// CXPD_EN simultaneously with setting EN. -#define HSTX_CTRL_CSR_EXPAND_EN_RESET _u(0x0) -#define HSTX_CTRL_CSR_EXPAND_EN_BITS _u(0x00000002) -#define HSTX_CTRL_CSR_EXPAND_EN_MSB _u(1) -#define HSTX_CTRL_CSR_EXPAND_EN_LSB _u(1) -#define HSTX_CTRL_CSR_EXPAND_EN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : HSTX_CTRL_CSR_EN -// Description : When EN is 1, the HSTX will shift out data as it appears in the -// FIFO. As long as there is data, the HSTX shift register will -// shift once per clock cycle, and the frequency of popping from -// the FIFO is determined by the ratio of SHIFT and SHIFT_THRESH. -// -// When EN is 0, the FIFO is not popped. The shift counter and -// clock generator are also reset to their initial state for as -// long as EN is low. Note the initial phase of the clock -// generator can be configured by the CLKPHASE field. -// -// Once the HSTX is enabled again, and data is pushed to the FIFO, -// the generated clock's first rising edge will be one half-period -// after the first data is launched. -#define HSTX_CTRL_CSR_EN_RESET _u(0x0) -#define HSTX_CTRL_CSR_EN_BITS _u(0x00000001) -#define HSTX_CTRL_CSR_EN_MSB _u(0) -#define HSTX_CTRL_CSR_EN_LSB _u(0) -#define HSTX_CTRL_CSR_EN_ACCESS "RW" -// ============================================================================= -// Register : HSTX_CTRL_BIT0 -// Description : Data control register for output bit 0 -#define HSTX_CTRL_BIT0_OFFSET _u(0x00000004) -#define HSTX_CTRL_BIT0_BITS _u(0x00031f1f) -#define HSTX_CTRL_BIT0_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : HSTX_CTRL_BIT0_CLK -// Description : Connect this output to the generated clock, rather than the -// data shift register. SEL_P and SEL_N are ignored if this bit is -// set, but INV can still be set to generate an antiphase clock. -#define HSTX_CTRL_BIT0_CLK_RESET _u(0x0) -#define HSTX_CTRL_BIT0_CLK_BITS _u(0x00020000) -#define HSTX_CTRL_BIT0_CLK_MSB _u(17) -#define HSTX_CTRL_BIT0_CLK_LSB _u(17) -#define HSTX_CTRL_BIT0_CLK_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : HSTX_CTRL_BIT0_INV -// Description : Invert this data output (logical NOT) -#define HSTX_CTRL_BIT0_INV_RESET _u(0x0) -#define HSTX_CTRL_BIT0_INV_BITS _u(0x00010000) -#define HSTX_CTRL_BIT0_INV_MSB _u(16) -#define HSTX_CTRL_BIT0_INV_LSB _u(16) -#define HSTX_CTRL_BIT0_INV_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : HSTX_CTRL_BIT0_SEL_N -// Description : Shift register data bit select for the second half of the HSTX -// clock cycle -#define HSTX_CTRL_BIT0_SEL_N_RESET _u(0x00) -#define HSTX_CTRL_BIT0_SEL_N_BITS _u(0x00001f00) -#define HSTX_CTRL_BIT0_SEL_N_MSB _u(12) -#define HSTX_CTRL_BIT0_SEL_N_LSB _u(8) -#define HSTX_CTRL_BIT0_SEL_N_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : HSTX_CTRL_BIT0_SEL_P -// Description : Shift register data bit select for the first half of the HSTX -// clock cycle -#define HSTX_CTRL_BIT0_SEL_P_RESET _u(0x00) -#define HSTX_CTRL_BIT0_SEL_P_BITS _u(0x0000001f) -#define HSTX_CTRL_BIT0_SEL_P_MSB _u(4) -#define HSTX_CTRL_BIT0_SEL_P_LSB _u(0) -#define HSTX_CTRL_BIT0_SEL_P_ACCESS "RW" -// ============================================================================= -// Register : HSTX_CTRL_BIT1 -// Description : Data control register for output bit 1 -#define HSTX_CTRL_BIT1_OFFSET _u(0x00000008) -#define HSTX_CTRL_BIT1_BITS _u(0x00031f1f) -#define HSTX_CTRL_BIT1_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : HSTX_CTRL_BIT1_CLK -// Description : Connect this output to the generated clock, rather than the -// data shift register. SEL_P and SEL_N are ignored if this bit is -// set, but INV can still be set to generate an antiphase clock. -#define HSTX_CTRL_BIT1_CLK_RESET _u(0x0) -#define HSTX_CTRL_BIT1_CLK_BITS _u(0x00020000) -#define HSTX_CTRL_BIT1_CLK_MSB _u(17) -#define HSTX_CTRL_BIT1_CLK_LSB _u(17) -#define HSTX_CTRL_BIT1_CLK_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : HSTX_CTRL_BIT1_INV -// Description : Invert this data output (logical NOT) -#define HSTX_CTRL_BIT1_INV_RESET _u(0x0) -#define HSTX_CTRL_BIT1_INV_BITS _u(0x00010000) -#define HSTX_CTRL_BIT1_INV_MSB _u(16) -#define HSTX_CTRL_BIT1_INV_LSB _u(16) -#define HSTX_CTRL_BIT1_INV_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : HSTX_CTRL_BIT1_SEL_N -// Description : Shift register data bit select for the second half of the HSTX -// clock cycle -#define HSTX_CTRL_BIT1_SEL_N_RESET _u(0x00) -#define HSTX_CTRL_BIT1_SEL_N_BITS _u(0x00001f00) -#define HSTX_CTRL_BIT1_SEL_N_MSB _u(12) -#define HSTX_CTRL_BIT1_SEL_N_LSB _u(8) -#define HSTX_CTRL_BIT1_SEL_N_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : HSTX_CTRL_BIT1_SEL_P -// Description : Shift register data bit select for the first half of the HSTX -// clock cycle -#define HSTX_CTRL_BIT1_SEL_P_RESET _u(0x00) -#define HSTX_CTRL_BIT1_SEL_P_BITS _u(0x0000001f) -#define HSTX_CTRL_BIT1_SEL_P_MSB _u(4) -#define HSTX_CTRL_BIT1_SEL_P_LSB _u(0) -#define HSTX_CTRL_BIT1_SEL_P_ACCESS "RW" -// ============================================================================= -// Register : HSTX_CTRL_BIT2 -// Description : Data control register for output bit 2 -#define HSTX_CTRL_BIT2_OFFSET _u(0x0000000c) -#define HSTX_CTRL_BIT2_BITS _u(0x00031f1f) -#define HSTX_CTRL_BIT2_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : HSTX_CTRL_BIT2_CLK -// Description : Connect this output to the generated clock, rather than the -// data shift register. SEL_P and SEL_N are ignored if this bit is -// set, but INV can still be set to generate an antiphase clock. -#define HSTX_CTRL_BIT2_CLK_RESET _u(0x0) -#define HSTX_CTRL_BIT2_CLK_BITS _u(0x00020000) -#define HSTX_CTRL_BIT2_CLK_MSB _u(17) -#define HSTX_CTRL_BIT2_CLK_LSB _u(17) -#define HSTX_CTRL_BIT2_CLK_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : HSTX_CTRL_BIT2_INV -// Description : Invert this data output (logical NOT) -#define HSTX_CTRL_BIT2_INV_RESET _u(0x0) -#define HSTX_CTRL_BIT2_INV_BITS _u(0x00010000) -#define HSTX_CTRL_BIT2_INV_MSB _u(16) -#define HSTX_CTRL_BIT2_INV_LSB _u(16) -#define HSTX_CTRL_BIT2_INV_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : HSTX_CTRL_BIT2_SEL_N -// Description : Shift register data bit select for the second half of the HSTX -// clock cycle -#define HSTX_CTRL_BIT2_SEL_N_RESET _u(0x00) -#define HSTX_CTRL_BIT2_SEL_N_BITS _u(0x00001f00) -#define HSTX_CTRL_BIT2_SEL_N_MSB _u(12) -#define HSTX_CTRL_BIT2_SEL_N_LSB _u(8) -#define HSTX_CTRL_BIT2_SEL_N_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : HSTX_CTRL_BIT2_SEL_P -// Description : Shift register data bit select for the first half of the HSTX -// clock cycle -#define HSTX_CTRL_BIT2_SEL_P_RESET _u(0x00) -#define HSTX_CTRL_BIT2_SEL_P_BITS _u(0x0000001f) -#define HSTX_CTRL_BIT2_SEL_P_MSB _u(4) -#define HSTX_CTRL_BIT2_SEL_P_LSB _u(0) -#define HSTX_CTRL_BIT2_SEL_P_ACCESS "RW" -// ============================================================================= -// Register : HSTX_CTRL_BIT3 -// Description : Data control register for output bit 3 -#define HSTX_CTRL_BIT3_OFFSET _u(0x00000010) -#define HSTX_CTRL_BIT3_BITS _u(0x00031f1f) -#define HSTX_CTRL_BIT3_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : HSTX_CTRL_BIT3_CLK -// Description : Connect this output to the generated clock, rather than the -// data shift register. SEL_P and SEL_N are ignored if this bit is -// set, but INV can still be set to generate an antiphase clock. -#define HSTX_CTRL_BIT3_CLK_RESET _u(0x0) -#define HSTX_CTRL_BIT3_CLK_BITS _u(0x00020000) -#define HSTX_CTRL_BIT3_CLK_MSB _u(17) -#define HSTX_CTRL_BIT3_CLK_LSB _u(17) -#define HSTX_CTRL_BIT3_CLK_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : HSTX_CTRL_BIT3_INV -// Description : Invert this data output (logical NOT) -#define HSTX_CTRL_BIT3_INV_RESET _u(0x0) -#define HSTX_CTRL_BIT3_INV_BITS _u(0x00010000) -#define HSTX_CTRL_BIT3_INV_MSB _u(16) -#define HSTX_CTRL_BIT3_INV_LSB _u(16) -#define HSTX_CTRL_BIT3_INV_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : HSTX_CTRL_BIT3_SEL_N -// Description : Shift register data bit select for the second half of the HSTX -// clock cycle -#define HSTX_CTRL_BIT3_SEL_N_RESET _u(0x00) -#define HSTX_CTRL_BIT3_SEL_N_BITS _u(0x00001f00) -#define HSTX_CTRL_BIT3_SEL_N_MSB _u(12) -#define HSTX_CTRL_BIT3_SEL_N_LSB _u(8) -#define HSTX_CTRL_BIT3_SEL_N_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : HSTX_CTRL_BIT3_SEL_P -// Description : Shift register data bit select for the first half of the HSTX -// clock cycle -#define HSTX_CTRL_BIT3_SEL_P_RESET _u(0x00) -#define HSTX_CTRL_BIT3_SEL_P_BITS _u(0x0000001f) -#define HSTX_CTRL_BIT3_SEL_P_MSB _u(4) -#define HSTX_CTRL_BIT3_SEL_P_LSB _u(0) -#define HSTX_CTRL_BIT3_SEL_P_ACCESS "RW" -// ============================================================================= -// Register : HSTX_CTRL_BIT4 -// Description : Data control register for output bit 4 -#define HSTX_CTRL_BIT4_OFFSET _u(0x00000014) -#define HSTX_CTRL_BIT4_BITS _u(0x00031f1f) -#define HSTX_CTRL_BIT4_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : HSTX_CTRL_BIT4_CLK -// Description : Connect this output to the generated clock, rather than the -// data shift register. SEL_P and SEL_N are ignored if this bit is -// set, but INV can still be set to generate an antiphase clock. -#define HSTX_CTRL_BIT4_CLK_RESET _u(0x0) -#define HSTX_CTRL_BIT4_CLK_BITS _u(0x00020000) -#define HSTX_CTRL_BIT4_CLK_MSB _u(17) -#define HSTX_CTRL_BIT4_CLK_LSB _u(17) -#define HSTX_CTRL_BIT4_CLK_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : HSTX_CTRL_BIT4_INV -// Description : Invert this data output (logical NOT) -#define HSTX_CTRL_BIT4_INV_RESET _u(0x0) -#define HSTX_CTRL_BIT4_INV_BITS _u(0x00010000) -#define HSTX_CTRL_BIT4_INV_MSB _u(16) -#define HSTX_CTRL_BIT4_INV_LSB _u(16) -#define HSTX_CTRL_BIT4_INV_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : HSTX_CTRL_BIT4_SEL_N -// Description : Shift register data bit select for the second half of the HSTX -// clock cycle -#define HSTX_CTRL_BIT4_SEL_N_RESET _u(0x00) -#define HSTX_CTRL_BIT4_SEL_N_BITS _u(0x00001f00) -#define HSTX_CTRL_BIT4_SEL_N_MSB _u(12) -#define HSTX_CTRL_BIT4_SEL_N_LSB _u(8) -#define HSTX_CTRL_BIT4_SEL_N_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : HSTX_CTRL_BIT4_SEL_P -// Description : Shift register data bit select for the first half of the HSTX -// clock cycle -#define HSTX_CTRL_BIT4_SEL_P_RESET _u(0x00) -#define HSTX_CTRL_BIT4_SEL_P_BITS _u(0x0000001f) -#define HSTX_CTRL_BIT4_SEL_P_MSB _u(4) -#define HSTX_CTRL_BIT4_SEL_P_LSB _u(0) -#define HSTX_CTRL_BIT4_SEL_P_ACCESS "RW" -// ============================================================================= -// Register : HSTX_CTRL_BIT5 -// Description : Data control register for output bit 5 -#define HSTX_CTRL_BIT5_OFFSET _u(0x00000018) -#define HSTX_CTRL_BIT5_BITS _u(0x00031f1f) -#define HSTX_CTRL_BIT5_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : HSTX_CTRL_BIT5_CLK -// Description : Connect this output to the generated clock, rather than the -// data shift register. SEL_P and SEL_N are ignored if this bit is -// set, but INV can still be set to generate an antiphase clock. -#define HSTX_CTRL_BIT5_CLK_RESET _u(0x0) -#define HSTX_CTRL_BIT5_CLK_BITS _u(0x00020000) -#define HSTX_CTRL_BIT5_CLK_MSB _u(17) -#define HSTX_CTRL_BIT5_CLK_LSB _u(17) -#define HSTX_CTRL_BIT5_CLK_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : HSTX_CTRL_BIT5_INV -// Description : Invert this data output (logical NOT) -#define HSTX_CTRL_BIT5_INV_RESET _u(0x0) -#define HSTX_CTRL_BIT5_INV_BITS _u(0x00010000) -#define HSTX_CTRL_BIT5_INV_MSB _u(16) -#define HSTX_CTRL_BIT5_INV_LSB _u(16) -#define HSTX_CTRL_BIT5_INV_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : HSTX_CTRL_BIT5_SEL_N -// Description : Shift register data bit select for the second half of the HSTX -// clock cycle -#define HSTX_CTRL_BIT5_SEL_N_RESET _u(0x00) -#define HSTX_CTRL_BIT5_SEL_N_BITS _u(0x00001f00) -#define HSTX_CTRL_BIT5_SEL_N_MSB _u(12) -#define HSTX_CTRL_BIT5_SEL_N_LSB _u(8) -#define HSTX_CTRL_BIT5_SEL_N_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : HSTX_CTRL_BIT5_SEL_P -// Description : Shift register data bit select for the first half of the HSTX -// clock cycle -#define HSTX_CTRL_BIT5_SEL_P_RESET _u(0x00) -#define HSTX_CTRL_BIT5_SEL_P_BITS _u(0x0000001f) -#define HSTX_CTRL_BIT5_SEL_P_MSB _u(4) -#define HSTX_CTRL_BIT5_SEL_P_LSB _u(0) -#define HSTX_CTRL_BIT5_SEL_P_ACCESS "RW" -// ============================================================================= -// Register : HSTX_CTRL_BIT6 -// Description : Data control register for output bit 6 -#define HSTX_CTRL_BIT6_OFFSET _u(0x0000001c) -#define HSTX_CTRL_BIT6_BITS _u(0x00031f1f) -#define HSTX_CTRL_BIT6_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : HSTX_CTRL_BIT6_CLK -// Description : Connect this output to the generated clock, rather than the -// data shift register. SEL_P and SEL_N are ignored if this bit is -// set, but INV can still be set to generate an antiphase clock. -#define HSTX_CTRL_BIT6_CLK_RESET _u(0x0) -#define HSTX_CTRL_BIT6_CLK_BITS _u(0x00020000) -#define HSTX_CTRL_BIT6_CLK_MSB _u(17) -#define HSTX_CTRL_BIT6_CLK_LSB _u(17) -#define HSTX_CTRL_BIT6_CLK_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : HSTX_CTRL_BIT6_INV -// Description : Invert this data output (logical NOT) -#define HSTX_CTRL_BIT6_INV_RESET _u(0x0) -#define HSTX_CTRL_BIT6_INV_BITS _u(0x00010000) -#define HSTX_CTRL_BIT6_INV_MSB _u(16) -#define HSTX_CTRL_BIT6_INV_LSB _u(16) -#define HSTX_CTRL_BIT6_INV_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : HSTX_CTRL_BIT6_SEL_N -// Description : Shift register data bit select for the second half of the HSTX -// clock cycle -#define HSTX_CTRL_BIT6_SEL_N_RESET _u(0x00) -#define HSTX_CTRL_BIT6_SEL_N_BITS _u(0x00001f00) -#define HSTX_CTRL_BIT6_SEL_N_MSB _u(12) -#define HSTX_CTRL_BIT6_SEL_N_LSB _u(8) -#define HSTX_CTRL_BIT6_SEL_N_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : HSTX_CTRL_BIT6_SEL_P -// Description : Shift register data bit select for the first half of the HSTX -// clock cycle -#define HSTX_CTRL_BIT6_SEL_P_RESET _u(0x00) -#define HSTX_CTRL_BIT6_SEL_P_BITS _u(0x0000001f) -#define HSTX_CTRL_BIT6_SEL_P_MSB _u(4) -#define HSTX_CTRL_BIT6_SEL_P_LSB _u(0) -#define HSTX_CTRL_BIT6_SEL_P_ACCESS "RW" -// ============================================================================= -// Register : HSTX_CTRL_BIT7 -// Description : Data control register for output bit 7 -#define HSTX_CTRL_BIT7_OFFSET _u(0x00000020) -#define HSTX_CTRL_BIT7_BITS _u(0x00031f1f) -#define HSTX_CTRL_BIT7_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : HSTX_CTRL_BIT7_CLK -// Description : Connect this output to the generated clock, rather than the -// data shift register. SEL_P and SEL_N are ignored if this bit is -// set, but INV can still be set to generate an antiphase clock. -#define HSTX_CTRL_BIT7_CLK_RESET _u(0x0) -#define HSTX_CTRL_BIT7_CLK_BITS _u(0x00020000) -#define HSTX_CTRL_BIT7_CLK_MSB _u(17) -#define HSTX_CTRL_BIT7_CLK_LSB _u(17) -#define HSTX_CTRL_BIT7_CLK_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : HSTX_CTRL_BIT7_INV -// Description : Invert this data output (logical NOT) -#define HSTX_CTRL_BIT7_INV_RESET _u(0x0) -#define HSTX_CTRL_BIT7_INV_BITS _u(0x00010000) -#define HSTX_CTRL_BIT7_INV_MSB _u(16) -#define HSTX_CTRL_BIT7_INV_LSB _u(16) -#define HSTX_CTRL_BIT7_INV_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : HSTX_CTRL_BIT7_SEL_N -// Description : Shift register data bit select for the second half of the HSTX -// clock cycle -#define HSTX_CTRL_BIT7_SEL_N_RESET _u(0x00) -#define HSTX_CTRL_BIT7_SEL_N_BITS _u(0x00001f00) -#define HSTX_CTRL_BIT7_SEL_N_MSB _u(12) -#define HSTX_CTRL_BIT7_SEL_N_LSB _u(8) -#define HSTX_CTRL_BIT7_SEL_N_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : HSTX_CTRL_BIT7_SEL_P -// Description : Shift register data bit select for the first half of the HSTX -// clock cycle -#define HSTX_CTRL_BIT7_SEL_P_RESET _u(0x00) -#define HSTX_CTRL_BIT7_SEL_P_BITS _u(0x0000001f) -#define HSTX_CTRL_BIT7_SEL_P_MSB _u(4) -#define HSTX_CTRL_BIT7_SEL_P_LSB _u(0) -#define HSTX_CTRL_BIT7_SEL_P_ACCESS "RW" -// ============================================================================= -// Register : HSTX_CTRL_EXPAND_SHIFT -// Description : Configure the optional shifter inside the command expander -#define HSTX_CTRL_EXPAND_SHIFT_OFFSET _u(0x00000024) -#define HSTX_CTRL_EXPAND_SHIFT_BITS _u(0x1f1f1f1f) -#define HSTX_CTRL_EXPAND_SHIFT_RESET _u(0x01000100) -// ----------------------------------------------------------------------------- -// Field : HSTX_CTRL_EXPAND_SHIFT_ENC_N_SHIFTS -// Description : Number of times to consume from the shift register before -// refilling it from the FIFO, when the current command is an -// encoded data command (e.g. TMDS). A register value of 0 means -// shift 32 times. -#define HSTX_CTRL_EXPAND_SHIFT_ENC_N_SHIFTS_RESET _u(0x01) -#define HSTX_CTRL_EXPAND_SHIFT_ENC_N_SHIFTS_BITS _u(0x1f000000) -#define HSTX_CTRL_EXPAND_SHIFT_ENC_N_SHIFTS_MSB _u(28) -#define HSTX_CTRL_EXPAND_SHIFT_ENC_N_SHIFTS_LSB _u(24) -#define HSTX_CTRL_EXPAND_SHIFT_ENC_N_SHIFTS_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : HSTX_CTRL_EXPAND_SHIFT_ENC_SHIFT -// Description : How many bits to right-rotate the shift register by each time -// data is pushed to the output shifter, when the current command -// is an encoded data command (e.g. TMDS). -#define HSTX_CTRL_EXPAND_SHIFT_ENC_SHIFT_RESET _u(0x00) -#define HSTX_CTRL_EXPAND_SHIFT_ENC_SHIFT_BITS _u(0x001f0000) -#define HSTX_CTRL_EXPAND_SHIFT_ENC_SHIFT_MSB _u(20) -#define HSTX_CTRL_EXPAND_SHIFT_ENC_SHIFT_LSB _u(16) -#define HSTX_CTRL_EXPAND_SHIFT_ENC_SHIFT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : HSTX_CTRL_EXPAND_SHIFT_RAW_N_SHIFTS -// Description : Number of times to consume from the shift register before -// refilling it from the FIFO, when the current command is a raw -// data command. A register value of 0 means shift 32 times. -#define HSTX_CTRL_EXPAND_SHIFT_RAW_N_SHIFTS_RESET _u(0x01) -#define HSTX_CTRL_EXPAND_SHIFT_RAW_N_SHIFTS_BITS _u(0x00001f00) -#define HSTX_CTRL_EXPAND_SHIFT_RAW_N_SHIFTS_MSB _u(12) -#define HSTX_CTRL_EXPAND_SHIFT_RAW_N_SHIFTS_LSB _u(8) -#define HSTX_CTRL_EXPAND_SHIFT_RAW_N_SHIFTS_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : HSTX_CTRL_EXPAND_SHIFT_RAW_SHIFT -// Description : How many bits to right-rotate the shift register by each time -// data is pushed to the output shifter, when the current command -// is a raw data command. -#define HSTX_CTRL_EXPAND_SHIFT_RAW_SHIFT_RESET _u(0x00) -#define HSTX_CTRL_EXPAND_SHIFT_RAW_SHIFT_BITS _u(0x0000001f) -#define HSTX_CTRL_EXPAND_SHIFT_RAW_SHIFT_MSB _u(4) -#define HSTX_CTRL_EXPAND_SHIFT_RAW_SHIFT_LSB _u(0) -#define HSTX_CTRL_EXPAND_SHIFT_RAW_SHIFT_ACCESS "RW" -// ============================================================================= -// Register : HSTX_CTRL_EXPAND_TMDS -// Description : Configure the optional TMDS encoder inside the command expander -#define HSTX_CTRL_EXPAND_TMDS_OFFSET _u(0x00000028) -#define HSTX_CTRL_EXPAND_TMDS_BITS _u(0x00ffffff) -#define HSTX_CTRL_EXPAND_TMDS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : HSTX_CTRL_EXPAND_TMDS_L2_NBITS -// Description : Number of valid data bits for the lane 2 TMDS encoder, starting -// from bit 7 of the rotated data. Field values of 0 -> 7 encode -// counts of 1 -> 8 bits. -#define HSTX_CTRL_EXPAND_TMDS_L2_NBITS_RESET _u(0x0) -#define HSTX_CTRL_EXPAND_TMDS_L2_NBITS_BITS _u(0x00e00000) -#define HSTX_CTRL_EXPAND_TMDS_L2_NBITS_MSB _u(23) -#define HSTX_CTRL_EXPAND_TMDS_L2_NBITS_LSB _u(21) -#define HSTX_CTRL_EXPAND_TMDS_L2_NBITS_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : HSTX_CTRL_EXPAND_TMDS_L2_ROT -// Description : Right-rotate applied to the current shifter data before the -// lane 2 TMDS encoder. -#define HSTX_CTRL_EXPAND_TMDS_L2_ROT_RESET _u(0x00) -#define HSTX_CTRL_EXPAND_TMDS_L2_ROT_BITS _u(0x001f0000) -#define HSTX_CTRL_EXPAND_TMDS_L2_ROT_MSB _u(20) -#define HSTX_CTRL_EXPAND_TMDS_L2_ROT_LSB _u(16) -#define HSTX_CTRL_EXPAND_TMDS_L2_ROT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : HSTX_CTRL_EXPAND_TMDS_L1_NBITS -// Description : Number of valid data bits for the lane 1 TMDS encoder, starting -// from bit 7 of the rotated data. Field values of 0 -> 7 encode -// counts of 1 -> 8 bits. -#define HSTX_CTRL_EXPAND_TMDS_L1_NBITS_RESET _u(0x0) -#define HSTX_CTRL_EXPAND_TMDS_L1_NBITS_BITS _u(0x0000e000) -#define HSTX_CTRL_EXPAND_TMDS_L1_NBITS_MSB _u(15) -#define HSTX_CTRL_EXPAND_TMDS_L1_NBITS_LSB _u(13) -#define HSTX_CTRL_EXPAND_TMDS_L1_NBITS_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : HSTX_CTRL_EXPAND_TMDS_L1_ROT -// Description : Right-rotate applied to the current shifter data before the -// lane 1 TMDS encoder. -#define HSTX_CTRL_EXPAND_TMDS_L1_ROT_RESET _u(0x00) -#define HSTX_CTRL_EXPAND_TMDS_L1_ROT_BITS _u(0x00001f00) -#define HSTX_CTRL_EXPAND_TMDS_L1_ROT_MSB _u(12) -#define HSTX_CTRL_EXPAND_TMDS_L1_ROT_LSB _u(8) -#define HSTX_CTRL_EXPAND_TMDS_L1_ROT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : HSTX_CTRL_EXPAND_TMDS_L0_NBITS -// Description : Number of valid data bits for the lane 0 TMDS encoder, starting -// from bit 7 of the rotated data. Field values of 0 -> 7 encode -// counts of 1 -> 8 bits. -#define HSTX_CTRL_EXPAND_TMDS_L0_NBITS_RESET _u(0x0) -#define HSTX_CTRL_EXPAND_TMDS_L0_NBITS_BITS _u(0x000000e0) -#define HSTX_CTRL_EXPAND_TMDS_L0_NBITS_MSB _u(7) -#define HSTX_CTRL_EXPAND_TMDS_L0_NBITS_LSB _u(5) -#define HSTX_CTRL_EXPAND_TMDS_L0_NBITS_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : HSTX_CTRL_EXPAND_TMDS_L0_ROT -// Description : Right-rotate applied to the current shifter data before the -// lane 0 TMDS encoder. -#define HSTX_CTRL_EXPAND_TMDS_L0_ROT_RESET _u(0x00) -#define HSTX_CTRL_EXPAND_TMDS_L0_ROT_BITS _u(0x0000001f) -#define HSTX_CTRL_EXPAND_TMDS_L0_ROT_MSB _u(4) -#define HSTX_CTRL_EXPAND_TMDS_L0_ROT_LSB _u(0) -#define HSTX_CTRL_EXPAND_TMDS_L0_ROT_ACCESS "RW" -// ============================================================================= -#endif // _HARDWARE_REGS_HSTX_CTRL_H - diff --git a/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/hstx_fifo.h b/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/hstx_fifo.h deleted file mode 100644 index d056447c8b..0000000000 --- a/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/hstx_fifo.h +++ /dev/null @@ -1,62 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -// ============================================================================= -// Register block : HSTX_FIFO -// Version : 1 -// Bus type : ahbl -// Description : FIFO status and write access for HSTX -// ============================================================================= -#ifndef _HARDWARE_REGS_HSTX_FIFO_H -#define _HARDWARE_REGS_HSTX_FIFO_H -// ============================================================================= -// Register : HSTX_FIFO_STAT -// Description : FIFO status -#define HSTX_FIFO_STAT_OFFSET _u(0x00000000) -#define HSTX_FIFO_STAT_BITS _u(0x000007ff) -#define HSTX_FIFO_STAT_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : HSTX_FIFO_STAT_WOF -// Description : FIFO was written when full. Write 1 to clear. -#define HSTX_FIFO_STAT_WOF_RESET _u(0x0) -#define HSTX_FIFO_STAT_WOF_BITS _u(0x00000400) -#define HSTX_FIFO_STAT_WOF_MSB _u(10) -#define HSTX_FIFO_STAT_WOF_LSB _u(10) -#define HSTX_FIFO_STAT_WOF_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : HSTX_FIFO_STAT_EMPTY -#define HSTX_FIFO_STAT_EMPTY_RESET "-" -#define HSTX_FIFO_STAT_EMPTY_BITS _u(0x00000200) -#define HSTX_FIFO_STAT_EMPTY_MSB _u(9) -#define HSTX_FIFO_STAT_EMPTY_LSB _u(9) -#define HSTX_FIFO_STAT_EMPTY_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : HSTX_FIFO_STAT_FULL -#define HSTX_FIFO_STAT_FULL_RESET "-" -#define HSTX_FIFO_STAT_FULL_BITS _u(0x00000100) -#define HSTX_FIFO_STAT_FULL_MSB _u(8) -#define HSTX_FIFO_STAT_FULL_LSB _u(8) -#define HSTX_FIFO_STAT_FULL_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : HSTX_FIFO_STAT_LEVEL -#define HSTX_FIFO_STAT_LEVEL_RESET _u(0x00) -#define HSTX_FIFO_STAT_LEVEL_BITS _u(0x000000ff) -#define HSTX_FIFO_STAT_LEVEL_MSB _u(7) -#define HSTX_FIFO_STAT_LEVEL_LSB _u(0) -#define HSTX_FIFO_STAT_LEVEL_ACCESS "RO" -// ============================================================================= -// Register : HSTX_FIFO_FIFO -// Description : Write access to FIFO -#define HSTX_FIFO_FIFO_OFFSET _u(0x00000004) -#define HSTX_FIFO_FIFO_BITS _u(0xffffffff) -#define HSTX_FIFO_FIFO_RESET _u(0x00000000) -#define HSTX_FIFO_FIFO_MSB _u(31) -#define HSTX_FIFO_FIFO_LSB _u(0) -#define HSTX_FIFO_FIFO_ACCESS "WF" -// ============================================================================= -#endif // _HARDWARE_REGS_HSTX_FIFO_H - diff --git a/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/i2c.h b/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/i2c.h deleted file mode 100644 index f44ceb4402..0000000000 --- a/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/i2c.h +++ /dev/null @@ -1,2700 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -// ============================================================================= -// Register block : I2C -// Version : 1 -// Bus type : apb -// Description : DW_apb_i2c address block -// -// List of configuration constants for the Synopsys I2C -// hardware (you may see references to these in I2C register -// header; these are *fixed* values, set at hardware design -// time): -// -// IC_ULTRA_FAST_MODE ................ 0x0 -// IC_UFM_TBUF_CNT_DEFAULT ........... 0x8 -// IC_UFM_SCL_LOW_COUNT .............. 0x0008 -// IC_UFM_SCL_HIGH_COUNT ............. 0x0006 -// IC_TX_TL .......................... 0x0 -// IC_TX_CMD_BLOCK ................... 0x1 -// IC_HAS_DMA ........................ 0x1 -// IC_HAS_ASYNC_FIFO ................. 0x0 -// IC_SMBUS_ARP ...................... 0x0 -// IC_FIRST_DATA_BYTE_STATUS ......... 0x1 -// IC_INTR_IO ........................ 0x1 -// IC_MASTER_MODE .................... 0x1 -// IC_DEFAULT_ACK_GENERAL_CALL ....... 0x1 -// IC_INTR_POL ....................... 0x1 -// IC_OPTIONAL_SAR ................... 0x0 -// IC_DEFAULT_TAR_SLAVE_ADDR ......... 0x055 -// IC_DEFAULT_SLAVE_ADDR ............. 0x055 -// IC_DEFAULT_HS_SPKLEN .............. 0x1 -// IC_FS_SCL_HIGH_COUNT .............. 0x0006 -// IC_HS_SCL_LOW_COUNT ............... 0x0008 -// IC_DEVICE_ID_VALUE ................ 0x0 -// IC_10BITADDR_MASTER ............... 0x0 -// IC_CLK_FREQ_OPTIMIZATION .......... 0x0 -// IC_DEFAULT_FS_SPKLEN .............. 0x7 -// IC_ADD_ENCODED_PARAMS ............. 0x0 -// IC_DEFAULT_SDA_HOLD ............... 0x000001 -// IC_DEFAULT_SDA_SETUP .............. 0x64 -// IC_AVOID_RX_FIFO_FLUSH_ON_TX_ABRT . 0x0 -// IC_CLOCK_PERIOD ................... 100 -// IC_EMPTYFIFO_HOLD_MASTER_EN ....... 1 -// IC_RESTART_EN ..................... 0x1 -// IC_TX_CMD_BLOCK_DEFAULT ........... 0x0 -// IC_BUS_CLEAR_FEATURE .............. 0x0 -// IC_CAP_LOADING .................... 100 -// IC_FS_SCL_LOW_COUNT ............... 0x000d -// APB_DATA_WIDTH .................... 32 -// IC_SDA_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff -// IC_SLV_DATA_NACK_ONLY ............. 0x1 -// IC_10BITADDR_SLAVE ................ 0x0 -// IC_CLK_TYPE ....................... 0x0 -// IC_SMBUS_UDID_MSB ................. 0x0 -// IC_SMBUS_SUSPEND_ALERT ............ 0x0 -// IC_HS_SCL_HIGH_COUNT .............. 0x0006 -// IC_SLV_RESTART_DET_EN ............. 0x1 -// IC_SMBUS .......................... 0x0 -// IC_OPTIONAL_SAR_DEFAULT ........... 0x0 -// IC_PERSISTANT_SLV_ADDR_DEFAULT .... 0x0 -// IC_USE_COUNTS ..................... 0x0 -// IC_RX_BUFFER_DEPTH ................ 16 -// IC_SCL_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff -// IC_RX_FULL_HLD_BUS_EN ............. 0x1 -// IC_SLAVE_DISABLE .................. 0x1 -// IC_RX_TL .......................... 0x0 -// IC_DEVICE_ID ...................... 0x0 -// IC_HC_COUNT_VALUES ................ 0x0 -// I2C_DYNAMIC_TAR_UPDATE ............ 0 -// IC_SMBUS_CLK_LOW_MEXT_DEFAULT ..... 0xffffffff -// IC_SMBUS_CLK_LOW_SEXT_DEFAULT ..... 0xffffffff -// IC_HS_MASTER_CODE ................. 0x1 -// IC_SMBUS_RST_IDLE_CNT_DEFAULT ..... 0xffff -// IC_SMBUS_UDID_LSB_DEFAULT ......... 0xffffffff -// IC_SS_SCL_HIGH_COUNT .............. 0x0028 -// IC_SS_SCL_LOW_COUNT ............... 0x002f -// IC_MAX_SPEED_MODE ................. 0x2 -// IC_STAT_FOR_CLK_STRETCH ........... 0x0 -// IC_STOP_DET_IF_MASTER_ACTIVE ...... 0x0 -// IC_DEFAULT_UFM_SPKLEN ............. 0x1 -// IC_TX_BUFFER_DEPTH ................ 16 -// ============================================================================= -#ifndef _HARDWARE_REGS_I2C_H -#define _HARDWARE_REGS_I2C_H -// ============================================================================= -// Register : I2C_IC_CON -// Description : I2C Control Register. This register can be written only when -// the DW_apb_i2c is disabled, which corresponds to the -// IC_ENABLE[0] register being set to 0. Writes at other times -// have no effect. -// -// Read/Write Access: - bit 10 is read only. - bit 11 is read only -// - bit 16 is read only - bit 17 is read only - bits 18 and 19 -// are read only. -#define I2C_IC_CON_OFFSET _u(0x00000000) -#define I2C_IC_CON_BITS _u(0x000007ff) -#define I2C_IC_CON_RESET _u(0x00000065) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_CON_STOP_DET_IF_MASTER_ACTIVE -// Description : Master issues the STOP_DET interrupt irrespective of whether -// master is active or not -#define I2C_IC_CON_STOP_DET_IF_MASTER_ACTIVE_RESET _u(0x0) -#define I2C_IC_CON_STOP_DET_IF_MASTER_ACTIVE_BITS _u(0x00000400) -#define I2C_IC_CON_STOP_DET_IF_MASTER_ACTIVE_MSB _u(10) -#define I2C_IC_CON_STOP_DET_IF_MASTER_ACTIVE_LSB _u(10) -#define I2C_IC_CON_STOP_DET_IF_MASTER_ACTIVE_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL -// Description : This bit controls whether DW_apb_i2c should hold the bus when -// the Rx FIFO is physically full to its RX_BUFFER_DEPTH, as -// described in the IC_RX_FULL_HLD_BUS_EN parameter. -// -// Reset value: 0x0. -// 0x0 -> Overflow when RX_FIFO is full -// 0x1 -> Hold bus when RX_FIFO is full -#define I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_RESET _u(0x0) -#define I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_BITS _u(0x00000200) -#define I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_MSB _u(9) -#define I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_LSB _u(9) -#define I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_ACCESS "RW" -#define I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_VALUE_DISABLED _u(0x0) -#define I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_VALUE_ENABLED _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_CON_TX_EMPTY_CTRL -// Description : This bit controls the generation of the TX_EMPTY interrupt, as -// described in the IC_RAW_INTR_STAT register. -// -// Reset value: 0x0. -// 0x0 -> Default behaviour of TX_EMPTY interrupt -// 0x1 -> Controlled generation of TX_EMPTY interrupt -#define I2C_IC_CON_TX_EMPTY_CTRL_RESET _u(0x0) -#define I2C_IC_CON_TX_EMPTY_CTRL_BITS _u(0x00000100) -#define I2C_IC_CON_TX_EMPTY_CTRL_MSB _u(8) -#define I2C_IC_CON_TX_EMPTY_CTRL_LSB _u(8) -#define I2C_IC_CON_TX_EMPTY_CTRL_ACCESS "RW" -#define I2C_IC_CON_TX_EMPTY_CTRL_VALUE_DISABLED _u(0x0) -#define I2C_IC_CON_TX_EMPTY_CTRL_VALUE_ENABLED _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_CON_STOP_DET_IFADDRESSED -// Description : In slave mode: - 1'b1: issues the STOP_DET interrupt only when -// it is addressed. - 1'b0: issues the STOP_DET irrespective of -// whether it's addressed or not. Reset value: 0x0 -// -// NOTE: During a general call address, this slave does not issue -// the STOP_DET interrupt if STOP_DET_IF_ADDRESSED = 1'b1, even if -// the slave responds to the general call address by generating -// ACK. The STOP_DET interrupt is generated only when the -// transmitted address matches the slave address (SAR). -// 0x0 -> slave issues STOP_DET intr always -// 0x1 -> slave issues STOP_DET intr only if addressed -#define I2C_IC_CON_STOP_DET_IFADDRESSED_RESET _u(0x0) -#define I2C_IC_CON_STOP_DET_IFADDRESSED_BITS _u(0x00000080) -#define I2C_IC_CON_STOP_DET_IFADDRESSED_MSB _u(7) -#define I2C_IC_CON_STOP_DET_IFADDRESSED_LSB _u(7) -#define I2C_IC_CON_STOP_DET_IFADDRESSED_ACCESS "RW" -#define I2C_IC_CON_STOP_DET_IFADDRESSED_VALUE_DISABLED _u(0x0) -#define I2C_IC_CON_STOP_DET_IFADDRESSED_VALUE_ENABLED _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_CON_IC_SLAVE_DISABLE -// Description : This bit controls whether I2C has its slave disabled, which -// means once the presetn signal is applied, then this bit is set -// and the slave is disabled. -// -// If this bit is set (slave is disabled), DW_apb_i2c functions -// only as a master and does not perform any action that requires -// a slave. -// -// NOTE: Software should ensure that if this bit is written with -// 0, then bit 0 should also be written with a 0. -// 0x0 -> Slave mode is enabled -// 0x1 -> Slave mode is disabled -#define I2C_IC_CON_IC_SLAVE_DISABLE_RESET _u(0x1) -#define I2C_IC_CON_IC_SLAVE_DISABLE_BITS _u(0x00000040) -#define I2C_IC_CON_IC_SLAVE_DISABLE_MSB _u(6) -#define I2C_IC_CON_IC_SLAVE_DISABLE_LSB _u(6) -#define I2C_IC_CON_IC_SLAVE_DISABLE_ACCESS "RW" -#define I2C_IC_CON_IC_SLAVE_DISABLE_VALUE_SLAVE_ENABLED _u(0x0) -#define I2C_IC_CON_IC_SLAVE_DISABLE_VALUE_SLAVE_DISABLED _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_CON_IC_RESTART_EN -// Description : Determines whether RESTART conditions may be sent when acting -// as a master. Some older slaves do not support handling RESTART -// conditions; however, RESTART conditions are used in several -// DW_apb_i2c operations. When RESTART is disabled, the master is -// prohibited from performing the following functions: - Sending a -// START BYTE - Performing any high-speed mode operation - High- -// speed mode operation - Performing direction changes in combined -// format mode - Performing a read operation with a 10-bit address -// By replacing RESTART condition followed by a STOP and a -// subsequent START condition, split operations are broken down -// into multiple DW_apb_i2c transfers. If the above operations are -// performed, it will result in setting bit 6 (TX_ABRT) of the -// IC_RAW_INTR_STAT register. -// -// Reset value: ENABLED -// 0x0 -> Master restart disabled -// 0x1 -> Master restart enabled -#define I2C_IC_CON_IC_RESTART_EN_RESET _u(0x1) -#define I2C_IC_CON_IC_RESTART_EN_BITS _u(0x00000020) -#define I2C_IC_CON_IC_RESTART_EN_MSB _u(5) -#define I2C_IC_CON_IC_RESTART_EN_LSB _u(5) -#define I2C_IC_CON_IC_RESTART_EN_ACCESS "RW" -#define I2C_IC_CON_IC_RESTART_EN_VALUE_DISABLED _u(0x0) -#define I2C_IC_CON_IC_RESTART_EN_VALUE_ENABLED _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_CON_IC_10BITADDR_MASTER -// Description : Controls whether the DW_apb_i2c starts its transfers in 7- or -// 10-bit addressing mode when acting as a master. - 0: 7-bit -// addressing - 1: 10-bit addressing -// 0x0 -> Master 7Bit addressing mode -// 0x1 -> Master 10Bit addressing mode -#define I2C_IC_CON_IC_10BITADDR_MASTER_RESET _u(0x0) -#define I2C_IC_CON_IC_10BITADDR_MASTER_BITS _u(0x00000010) -#define I2C_IC_CON_IC_10BITADDR_MASTER_MSB _u(4) -#define I2C_IC_CON_IC_10BITADDR_MASTER_LSB _u(4) -#define I2C_IC_CON_IC_10BITADDR_MASTER_ACCESS "RW" -#define I2C_IC_CON_IC_10BITADDR_MASTER_VALUE_ADDR_7BITS _u(0x0) -#define I2C_IC_CON_IC_10BITADDR_MASTER_VALUE_ADDR_10BITS _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_CON_IC_10BITADDR_SLAVE -// Description : When acting as a slave, this bit controls whether the -// DW_apb_i2c responds to 7- or 10-bit addresses. - 0: 7-bit -// addressing. The DW_apb_i2c ignores transactions that involve -// 10-bit addressing; for 7-bit addressing, only the lower 7 bits -// of the IC_SAR register are compared. - 1: 10-bit addressing. -// The DW_apb_i2c responds to only 10-bit addressing transfers -// that match the full 10 bits of the IC_SAR register. -// 0x0 -> Slave 7Bit addressing -// 0x1 -> Slave 10Bit addressing -#define I2C_IC_CON_IC_10BITADDR_SLAVE_RESET _u(0x0) -#define I2C_IC_CON_IC_10BITADDR_SLAVE_BITS _u(0x00000008) -#define I2C_IC_CON_IC_10BITADDR_SLAVE_MSB _u(3) -#define I2C_IC_CON_IC_10BITADDR_SLAVE_LSB _u(3) -#define I2C_IC_CON_IC_10BITADDR_SLAVE_ACCESS "RW" -#define I2C_IC_CON_IC_10BITADDR_SLAVE_VALUE_ADDR_7BITS _u(0x0) -#define I2C_IC_CON_IC_10BITADDR_SLAVE_VALUE_ADDR_10BITS _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_CON_SPEED -// Description : These bits control at which speed the DW_apb_i2c operates; its -// setting is relevant only if one is operating the DW_apb_i2c in -// master mode. Hardware protects against illegal values being -// programmed by software. These bits must be programmed -// appropriately for slave mode also, as it is used to capture -// correct value of spike filter as per the speed mode. -// -// This register should be programmed only with a value in the -// range of 1 to IC_MAX_SPEED_MODE; otherwise, hardware updates -// this register with the value of IC_MAX_SPEED_MODE. -// -// 1: standard mode (100 kbit/s) -// -// 2: fast mode (<=400 kbit/s) or fast mode plus (<=1000Kbit/s) -// -// 3: high speed mode (3.4 Mbit/s) -// -// Note: This field is not applicable when IC_ULTRA_FAST_MODE=1 -// 0x1 -> Standard Speed mode of operation -// 0x2 -> Fast or Fast Plus mode of operation -// 0x3 -> High Speed mode of operation -#define I2C_IC_CON_SPEED_RESET _u(0x2) -#define I2C_IC_CON_SPEED_BITS _u(0x00000006) -#define I2C_IC_CON_SPEED_MSB _u(2) -#define I2C_IC_CON_SPEED_LSB _u(1) -#define I2C_IC_CON_SPEED_ACCESS "RW" -#define I2C_IC_CON_SPEED_VALUE_STANDARD _u(0x1) -#define I2C_IC_CON_SPEED_VALUE_FAST _u(0x2) -#define I2C_IC_CON_SPEED_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_CON_MASTER_MODE -// Description : This bit controls whether the DW_apb_i2c master is enabled. -// -// NOTE: Software should ensure that if this bit is written with -// '1' then bit 6 should also be written with a '1'. -// 0x0 -> Master mode is disabled -// 0x1 -> Master mode is enabled -#define I2C_IC_CON_MASTER_MODE_RESET _u(0x1) -#define I2C_IC_CON_MASTER_MODE_BITS _u(0x00000001) -#define I2C_IC_CON_MASTER_MODE_MSB _u(0) -#define I2C_IC_CON_MASTER_MODE_LSB _u(0) -#define I2C_IC_CON_MASTER_MODE_ACCESS "RW" -#define I2C_IC_CON_MASTER_MODE_VALUE_DISABLED _u(0x0) -#define I2C_IC_CON_MASTER_MODE_VALUE_ENABLED _u(0x1) -// ============================================================================= -// Register : I2C_IC_TAR -// Description : I2C Target Address Register -// -// This register is 12 bits wide, and bits 31:12 are reserved. -// This register can be written to only when IC_ENABLE[0] is set -// to 0. -// -// Note: If the software or application is aware that the -// DW_apb_i2c is not using the TAR address for the pending -// commands in the Tx FIFO, then it is possible to update the TAR -// address even while the Tx FIFO has entries (IC_STATUS[2]= 0). - -// It is not necessary to perform any write to this register if -// DW_apb_i2c is enabled as an I2C slave only. -#define I2C_IC_TAR_OFFSET _u(0x00000004) -#define I2C_IC_TAR_BITS _u(0x00000fff) -#define I2C_IC_TAR_RESET _u(0x00000055) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_TAR_SPECIAL -// Description : This bit indicates whether software performs a Device-ID or -// General Call or START BYTE command. - 0: ignore bit 10 -// GC_OR_START and use IC_TAR normally - 1: perform special I2C -// command as specified in Device_ID or GC_OR_START bit Reset -// value: 0x0 -// 0x0 -> Disables programming of GENERAL_CALL or START_BYTE transmission -// 0x1 -> Enables programming of GENERAL_CALL or START_BYTE transmission -#define I2C_IC_TAR_SPECIAL_RESET _u(0x0) -#define I2C_IC_TAR_SPECIAL_BITS _u(0x00000800) -#define I2C_IC_TAR_SPECIAL_MSB _u(11) -#define I2C_IC_TAR_SPECIAL_LSB _u(11) -#define I2C_IC_TAR_SPECIAL_ACCESS "RW" -#define I2C_IC_TAR_SPECIAL_VALUE_DISABLED _u(0x0) -#define I2C_IC_TAR_SPECIAL_VALUE_ENABLED _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_TAR_GC_OR_START -// Description : If bit 11 (SPECIAL) is set to 1 and bit 13(Device-ID) is set to -// 0, then this bit indicates whether a General Call or START byte -// command is to be performed by the DW_apb_i2c. - 0: General Call -// Address - after issuing a General Call, only writes may be -// performed. Attempting to issue a read command results in -// setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register. The -// DW_apb_i2c remains in General Call mode until the SPECIAL bit -// value (bit 11) is cleared. - 1: START BYTE Reset value: 0x0 -// 0x0 -> GENERAL_CALL byte transmission -// 0x1 -> START byte transmission -#define I2C_IC_TAR_GC_OR_START_RESET _u(0x0) -#define I2C_IC_TAR_GC_OR_START_BITS _u(0x00000400) -#define I2C_IC_TAR_GC_OR_START_MSB _u(10) -#define I2C_IC_TAR_GC_OR_START_LSB _u(10) -#define I2C_IC_TAR_GC_OR_START_ACCESS "RW" -#define I2C_IC_TAR_GC_OR_START_VALUE_GENERAL_CALL _u(0x0) -#define I2C_IC_TAR_GC_OR_START_VALUE_START_BYTE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_TAR_IC_TAR -// Description : This is the target address for any master transaction. When -// transmitting a General Call, these bits are ignored. To -// generate a START BYTE, the CPU needs to write only once into -// these bits. -// -// If the IC_TAR and IC_SAR are the same, loopback exists but the -// FIFOs are shared between master and slave, so full loopback is -// not feasible. Only one direction loopback mode is supported -// (simplex), not duplex. A master cannot transmit to itself; it -// can transmit to only a slave. -#define I2C_IC_TAR_IC_TAR_RESET _u(0x055) -#define I2C_IC_TAR_IC_TAR_BITS _u(0x000003ff) -#define I2C_IC_TAR_IC_TAR_MSB _u(9) -#define I2C_IC_TAR_IC_TAR_LSB _u(0) -#define I2C_IC_TAR_IC_TAR_ACCESS "RW" -// ============================================================================= -// Register : I2C_IC_SAR -// Description : I2C Slave Address Register -#define I2C_IC_SAR_OFFSET _u(0x00000008) -#define I2C_IC_SAR_BITS _u(0x000003ff) -#define I2C_IC_SAR_RESET _u(0x00000055) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_SAR_IC_SAR -// Description : The IC_SAR holds the slave address when the I2C is operating as -// a slave. For 7-bit addressing, only IC_SAR[6:0] is used. -// -// This register can be written only when the I2C interface is -// disabled, which corresponds to the IC_ENABLE[0] register being -// set to 0. Writes at other times have no effect. -// -// Note: The default values cannot be any of the reserved address -// locations: that is, 0x00 to 0x07, or 0x78 to 0x7f. The correct -// operation of the device is not guaranteed if you program the -// IC_SAR or IC_TAR to a reserved value. Refer to -// <> for a complete list of these -// reserved values. -#define I2C_IC_SAR_IC_SAR_RESET _u(0x055) -#define I2C_IC_SAR_IC_SAR_BITS _u(0x000003ff) -#define I2C_IC_SAR_IC_SAR_MSB _u(9) -#define I2C_IC_SAR_IC_SAR_LSB _u(0) -#define I2C_IC_SAR_IC_SAR_ACCESS "RW" -// ============================================================================= -// Register : I2C_IC_DATA_CMD -// Description : I2C Rx/Tx Data Buffer and Command Register; this is the -// register the CPU writes to when filling the TX FIFO and the CPU -// reads from when retrieving bytes from RX FIFO. -// -// The size of the register changes as follows: -// -// Write: - 11 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=1 - 9 bits -// when IC_EMPTYFIFO_HOLD_MASTER_EN=0 Read: - 12 bits when -// IC_FIRST_DATA_BYTE_STATUS = 1 - 8 bits when -// IC_FIRST_DATA_BYTE_STATUS = 0 Note: In order for the DW_apb_i2c -// to continue acknowledging reads, a read command should be -// written for every byte that is to be received; otherwise the -// DW_apb_i2c will stop acknowledging. -#define I2C_IC_DATA_CMD_OFFSET _u(0x00000010) -#define I2C_IC_DATA_CMD_BITS _u(0x00000fff) -#define I2C_IC_DATA_CMD_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_DATA_CMD_FIRST_DATA_BYTE -// Description : Indicates the first data byte received after the address phase -// for receive transfer in Master receiver or Slave receiver mode. -// -// Reset value : 0x0 -// -// NOTE: In case of APB_DATA_WIDTH=8, -// -// 1. The user has to perform two APB Reads to IC_DATA_CMD in -// order to get status on 11 bit. -// -// 2. In order to read the 11 bit, the user has to perform the -// first data byte read [7:0] (offset 0x10) and then perform the -// second read [15:8] (offset 0x11) in order to know the status of -// 11 bit (whether the data received in previous read is a first -// data byte or not). -// -// 3. The 11th bit is an optional read field, user can ignore 2nd -// byte read [15:8] (offset 0x11) if not interested in -// FIRST_DATA_BYTE status. -// 0x0 -> Sequential data byte received -// 0x1 -> Non sequential data byte received -#define I2C_IC_DATA_CMD_FIRST_DATA_BYTE_RESET _u(0x0) -#define I2C_IC_DATA_CMD_FIRST_DATA_BYTE_BITS _u(0x00000800) -#define I2C_IC_DATA_CMD_FIRST_DATA_BYTE_MSB _u(11) -#define I2C_IC_DATA_CMD_FIRST_DATA_BYTE_LSB _u(11) -#define I2C_IC_DATA_CMD_FIRST_DATA_BYTE_ACCESS "RO" -#define I2C_IC_DATA_CMD_FIRST_DATA_BYTE_VALUE_INACTIVE _u(0x0) -#define I2C_IC_DATA_CMD_FIRST_DATA_BYTE_VALUE_ACTIVE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_DATA_CMD_RESTART -// Description : This bit controls whether a RESTART is issued before the byte -// is sent or received. -// -// 1 - If IC_RESTART_EN is 1, a RESTART is issued before the data -// is sent/received (according to the value of CMD), regardless of -// whether or not the transfer direction is changing from the -// previous command; if IC_RESTART_EN is 0, a STOP followed by a -// START is issued instead. -// -// 0 - If IC_RESTART_EN is 1, a RESTART is issued only if the -// transfer direction is changing from the previous command; if -// IC_RESTART_EN is 0, a STOP followed by a START is issued -// instead. -// -// Reset value: 0x0 -// 0x0 -> Don't Issue RESTART before this command -// 0x1 -> Issue RESTART before this command -#define I2C_IC_DATA_CMD_RESTART_RESET _u(0x0) -#define I2C_IC_DATA_CMD_RESTART_BITS _u(0x00000400) -#define I2C_IC_DATA_CMD_RESTART_MSB _u(10) -#define I2C_IC_DATA_CMD_RESTART_LSB _u(10) -#define I2C_IC_DATA_CMD_RESTART_ACCESS "SC" -#define I2C_IC_DATA_CMD_RESTART_VALUE_DISABLE _u(0x0) -#define I2C_IC_DATA_CMD_RESTART_VALUE_ENABLE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_DATA_CMD_STOP -// Description : This bit controls whether a STOP is issued after the byte is -// sent or received. -// -// - 1 - STOP is issued after this byte, regardless of whether or -// not the Tx FIFO is empty. If the Tx FIFO is not empty, the -// master immediately tries to start a new transfer by issuing a -// START and arbitrating for the bus. - 0 - STOP is not issued -// after this byte, regardless of whether or not the Tx FIFO is -// empty. If the Tx FIFO is not empty, the master continues the -// current transfer by sending/receiving data bytes according to -// the value of the CMD bit. If the Tx FIFO is empty, the master -// holds the SCL line low and stalls the bus until a new command -// is available in the Tx FIFO. Reset value: 0x0 -// 0x0 -> Don't Issue STOP after this command -// 0x1 -> Issue STOP after this command -#define I2C_IC_DATA_CMD_STOP_RESET _u(0x0) -#define I2C_IC_DATA_CMD_STOP_BITS _u(0x00000200) -#define I2C_IC_DATA_CMD_STOP_MSB _u(9) -#define I2C_IC_DATA_CMD_STOP_LSB _u(9) -#define I2C_IC_DATA_CMD_STOP_ACCESS "SC" -#define I2C_IC_DATA_CMD_STOP_VALUE_DISABLE _u(0x0) -#define I2C_IC_DATA_CMD_STOP_VALUE_ENABLE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_DATA_CMD_CMD -// Description : This bit controls whether a read or a write is performed. This -// bit does not control the direction when the DW_apb_i2con acts -// as a slave. It controls only the direction when it acts as a -// master. -// -// When a command is entered in the TX FIFO, this bit -// distinguishes the write and read commands. In slave-receiver -// mode, this bit is a 'don't care' because writes to this -// register are not required. In slave-transmitter mode, a '0' -// indicates that the data in IC_DATA_CMD is to be transmitted. -// -// When programming this bit, you should remember the following: -// attempting to perform a read operation after a General Call -// command has been sent results in a TX_ABRT interrupt (bit 6 of -// the IC_RAW_INTR_STAT register), unless bit 11 (SPECIAL) in the -// IC_TAR register has been cleared. If a '1' is written to this -// bit after receiving a RD_REQ interrupt, then a TX_ABRT -// interrupt occurs. -// -// Reset value: 0x0 -// 0x0 -> Master Write Command -// 0x1 -> Master Read Command -#define I2C_IC_DATA_CMD_CMD_RESET _u(0x0) -#define I2C_IC_DATA_CMD_CMD_BITS _u(0x00000100) -#define I2C_IC_DATA_CMD_CMD_MSB _u(8) -#define I2C_IC_DATA_CMD_CMD_LSB _u(8) -#define I2C_IC_DATA_CMD_CMD_ACCESS "SC" -#define I2C_IC_DATA_CMD_CMD_VALUE_WRITE _u(0x0) -#define I2C_IC_DATA_CMD_CMD_VALUE_READ _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_DATA_CMD_DAT -// Description : This register contains the data to be transmitted or received -// on the I2C bus. If you are writing to this register and want to -// perform a read, bits 7:0 (DAT) are ignored by the DW_apb_i2c. -// However, when you read this register, these bits return the -// value of data received on the DW_apb_i2c interface. -// -// Reset value: 0x0 -#define I2C_IC_DATA_CMD_DAT_RESET _u(0x00) -#define I2C_IC_DATA_CMD_DAT_BITS _u(0x000000ff) -#define I2C_IC_DATA_CMD_DAT_MSB _u(7) -#define I2C_IC_DATA_CMD_DAT_LSB _u(0) -#define I2C_IC_DATA_CMD_DAT_ACCESS "RW" -// ============================================================================= -// Register : I2C_IC_SS_SCL_HCNT -// Description : Standard Speed I2C Clock SCL High Count Register -#define I2C_IC_SS_SCL_HCNT_OFFSET _u(0x00000014) -#define I2C_IC_SS_SCL_HCNT_BITS _u(0x0000ffff) -#define I2C_IC_SS_SCL_HCNT_RESET _u(0x00000028) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_SS_SCL_HCNT_IC_SS_SCL_HCNT -// Description : This register must be set before any I2C bus transaction can -// take place to ensure proper I/O timing. This register sets the -// SCL clock high-period count for standard speed. For more -// information, refer to 'IC_CLK Frequency Configuration'. -// -// This register can be written only when the I2C interface is -// disabled which corresponds to the IC_ENABLE[0] register being -// set to 0. Writes at other times have no effect. -// -// The minimum valid value is 6; hardware prevents values less -// than this being written, and if attempted results in 6 being -// set. For designs with APB_DATA_WIDTH = 8, the order of -// programming is important to ensure the correct operation of the -// DW_apb_i2c. The lower byte must be programmed first. Then the -// upper byte is programmed. -// -// NOTE: This register must not be programmed to a value higher -// than 65525, because DW_apb_i2c uses a 16-bit counter to flag an -// I2C bus idle condition when this counter reaches a value of -// IC_SS_SCL_HCNT + 10. -#define I2C_IC_SS_SCL_HCNT_IC_SS_SCL_HCNT_RESET _u(0x0028) -#define I2C_IC_SS_SCL_HCNT_IC_SS_SCL_HCNT_BITS _u(0x0000ffff) -#define I2C_IC_SS_SCL_HCNT_IC_SS_SCL_HCNT_MSB _u(15) -#define I2C_IC_SS_SCL_HCNT_IC_SS_SCL_HCNT_LSB _u(0) -#define I2C_IC_SS_SCL_HCNT_IC_SS_SCL_HCNT_ACCESS "RW" -// ============================================================================= -// Register : I2C_IC_SS_SCL_LCNT -// Description : Standard Speed I2C Clock SCL Low Count Register -#define I2C_IC_SS_SCL_LCNT_OFFSET _u(0x00000018) -#define I2C_IC_SS_SCL_LCNT_BITS _u(0x0000ffff) -#define I2C_IC_SS_SCL_LCNT_RESET _u(0x0000002f) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_SS_SCL_LCNT_IC_SS_SCL_LCNT -// Description : This register must be set before any I2C bus transaction can -// take place to ensure proper I/O timing. This register sets the -// SCL clock low period count for standard speed. For more -// information, refer to 'IC_CLK Frequency Configuration' -// -// This register can be written only when the I2C interface is -// disabled which corresponds to the IC_ENABLE[0] register being -// set to 0. Writes at other times have no effect. -// -// The minimum valid value is 8; hardware prevents values less -// than this being written, and if attempted, results in 8 being -// set. For designs with APB_DATA_WIDTH = 8, the order of -// programming is important to ensure the correct operation of -// DW_apb_i2c. The lower byte must be programmed first, and then -// the upper byte is programmed. -#define I2C_IC_SS_SCL_LCNT_IC_SS_SCL_LCNT_RESET _u(0x002f) -#define I2C_IC_SS_SCL_LCNT_IC_SS_SCL_LCNT_BITS _u(0x0000ffff) -#define I2C_IC_SS_SCL_LCNT_IC_SS_SCL_LCNT_MSB _u(15) -#define I2C_IC_SS_SCL_LCNT_IC_SS_SCL_LCNT_LSB _u(0) -#define I2C_IC_SS_SCL_LCNT_IC_SS_SCL_LCNT_ACCESS "RW" -// ============================================================================= -// Register : I2C_IC_FS_SCL_HCNT -// Description : Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register -#define I2C_IC_FS_SCL_HCNT_OFFSET _u(0x0000001c) -#define I2C_IC_FS_SCL_HCNT_BITS _u(0x0000ffff) -#define I2C_IC_FS_SCL_HCNT_RESET _u(0x00000006) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_FS_SCL_HCNT_IC_FS_SCL_HCNT -// Description : This register must be set before any I2C bus transaction can -// take place to ensure proper I/O timing. This register sets the -// SCL clock high-period count for fast mode or fast mode plus. It -// is used in high-speed mode to send the Master Code and START -// BYTE or General CALL. For more information, refer to 'IC_CLK -// Frequency Configuration'. -// -// This register goes away and becomes read-only returning 0s if -// IC_MAX_SPEED_MODE = standard. This register can be written only -// when the I2C interface is disabled, which corresponds to the -// IC_ENABLE[0] register being set to 0. Writes at other times -// have no effect. -// -// The minimum valid value is 6; hardware prevents values less -// than this being written, and if attempted results in 6 being -// set. For designs with APB_DATA_WIDTH == 8 the order of -// programming is important to ensure the correct operation of the -// DW_apb_i2c. The lower byte must be programmed first. Then the -// upper byte is programmed. -#define I2C_IC_FS_SCL_HCNT_IC_FS_SCL_HCNT_RESET _u(0x0006) -#define I2C_IC_FS_SCL_HCNT_IC_FS_SCL_HCNT_BITS _u(0x0000ffff) -#define I2C_IC_FS_SCL_HCNT_IC_FS_SCL_HCNT_MSB _u(15) -#define I2C_IC_FS_SCL_HCNT_IC_FS_SCL_HCNT_LSB _u(0) -#define I2C_IC_FS_SCL_HCNT_IC_FS_SCL_HCNT_ACCESS "RW" -// ============================================================================= -// Register : I2C_IC_FS_SCL_LCNT -// Description : Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register -#define I2C_IC_FS_SCL_LCNT_OFFSET _u(0x00000020) -#define I2C_IC_FS_SCL_LCNT_BITS _u(0x0000ffff) -#define I2C_IC_FS_SCL_LCNT_RESET _u(0x0000000d) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT -// Description : This register must be set before any I2C bus transaction can -// take place to ensure proper I/O timing. This register sets the -// SCL clock low period count for fast speed. It is used in high- -// speed mode to send the Master Code and START BYTE or General -// CALL. For more information, refer to 'IC_CLK Frequency -// Configuration'. -// -// This register goes away and becomes read-only returning 0s if -// IC_MAX_SPEED_MODE = standard. -// -// This register can be written only when the I2C interface is -// disabled, which corresponds to the IC_ENABLE[0] register being -// set to 0. Writes at other times have no effect. -// -// The minimum valid value is 8; hardware prevents values less -// than this being written, and if attempted results in 8 being -// set. For designs with APB_DATA_WIDTH = 8 the order of -// programming is important to ensure the correct operation of the -// DW_apb_i2c. The lower byte must be programmed first. Then the -// upper byte is programmed. If the value is less than 8 then the -// count value gets changed to 8. -#define I2C_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT_RESET _u(0x000d) -#define I2C_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT_BITS _u(0x0000ffff) -#define I2C_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT_MSB _u(15) -#define I2C_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT_LSB _u(0) -#define I2C_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT_ACCESS "RW" -// ============================================================================= -// Register : I2C_IC_INTR_STAT -// Description : I2C Interrupt Status Register -// -// Each bit in this register has a corresponding mask bit in the -// IC_INTR_MASK register. These bits are cleared by reading the -// matching interrupt clear register. The unmasked raw versions of -// these bits are available in the IC_RAW_INTR_STAT register. -#define I2C_IC_INTR_STAT_OFFSET _u(0x0000002c) -#define I2C_IC_INTR_STAT_BITS _u(0x00001fff) -#define I2C_IC_INTR_STAT_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_INTR_STAT_R_RESTART_DET -// Description : See IC_RAW_INTR_STAT for a detailed description of -// R_RESTART_DET bit. -// -// Reset value: 0x0 -// 0x0 -> R_RESTART_DET interrupt is inactive -// 0x1 -> R_RESTART_DET interrupt is active -#define I2C_IC_INTR_STAT_R_RESTART_DET_RESET _u(0x0) -#define I2C_IC_INTR_STAT_R_RESTART_DET_BITS _u(0x00001000) -#define I2C_IC_INTR_STAT_R_RESTART_DET_MSB _u(12) -#define I2C_IC_INTR_STAT_R_RESTART_DET_LSB _u(12) -#define I2C_IC_INTR_STAT_R_RESTART_DET_ACCESS "RO" -#define I2C_IC_INTR_STAT_R_RESTART_DET_VALUE_INACTIVE _u(0x0) -#define I2C_IC_INTR_STAT_R_RESTART_DET_VALUE_ACTIVE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_INTR_STAT_R_GEN_CALL -// Description : See IC_RAW_INTR_STAT for a detailed description of R_GEN_CALL -// bit. -// -// Reset value: 0x0 -// 0x0 -> R_GEN_CALL interrupt is inactive -// 0x1 -> R_GEN_CALL interrupt is active -#define I2C_IC_INTR_STAT_R_GEN_CALL_RESET _u(0x0) -#define I2C_IC_INTR_STAT_R_GEN_CALL_BITS _u(0x00000800) -#define I2C_IC_INTR_STAT_R_GEN_CALL_MSB _u(11) -#define I2C_IC_INTR_STAT_R_GEN_CALL_LSB _u(11) -#define I2C_IC_INTR_STAT_R_GEN_CALL_ACCESS "RO" -#define I2C_IC_INTR_STAT_R_GEN_CALL_VALUE_INACTIVE _u(0x0) -#define I2C_IC_INTR_STAT_R_GEN_CALL_VALUE_ACTIVE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_INTR_STAT_R_START_DET -// Description : See IC_RAW_INTR_STAT for a detailed description of R_START_DET -// bit. -// -// Reset value: 0x0 -// 0x0 -> R_START_DET interrupt is inactive -// 0x1 -> R_START_DET interrupt is active -#define I2C_IC_INTR_STAT_R_START_DET_RESET _u(0x0) -#define I2C_IC_INTR_STAT_R_START_DET_BITS _u(0x00000400) -#define I2C_IC_INTR_STAT_R_START_DET_MSB _u(10) -#define I2C_IC_INTR_STAT_R_START_DET_LSB _u(10) -#define I2C_IC_INTR_STAT_R_START_DET_ACCESS "RO" -#define I2C_IC_INTR_STAT_R_START_DET_VALUE_INACTIVE _u(0x0) -#define I2C_IC_INTR_STAT_R_START_DET_VALUE_ACTIVE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_INTR_STAT_R_STOP_DET -// Description : See IC_RAW_INTR_STAT for a detailed description of R_STOP_DET -// bit. -// -// Reset value: 0x0 -// 0x0 -> R_STOP_DET interrupt is inactive -// 0x1 -> R_STOP_DET interrupt is active -#define I2C_IC_INTR_STAT_R_STOP_DET_RESET _u(0x0) -#define I2C_IC_INTR_STAT_R_STOP_DET_BITS _u(0x00000200) -#define I2C_IC_INTR_STAT_R_STOP_DET_MSB _u(9) -#define I2C_IC_INTR_STAT_R_STOP_DET_LSB _u(9) -#define I2C_IC_INTR_STAT_R_STOP_DET_ACCESS "RO" -#define I2C_IC_INTR_STAT_R_STOP_DET_VALUE_INACTIVE _u(0x0) -#define I2C_IC_INTR_STAT_R_STOP_DET_VALUE_ACTIVE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_INTR_STAT_R_ACTIVITY -// Description : See IC_RAW_INTR_STAT for a detailed description of R_ACTIVITY -// bit. -// -// Reset value: 0x0 -// 0x0 -> R_ACTIVITY interrupt is inactive -// 0x1 -> R_ACTIVITY interrupt is active -#define I2C_IC_INTR_STAT_R_ACTIVITY_RESET _u(0x0) -#define I2C_IC_INTR_STAT_R_ACTIVITY_BITS _u(0x00000100) -#define I2C_IC_INTR_STAT_R_ACTIVITY_MSB _u(8) -#define I2C_IC_INTR_STAT_R_ACTIVITY_LSB _u(8) -#define I2C_IC_INTR_STAT_R_ACTIVITY_ACCESS "RO" -#define I2C_IC_INTR_STAT_R_ACTIVITY_VALUE_INACTIVE _u(0x0) -#define I2C_IC_INTR_STAT_R_ACTIVITY_VALUE_ACTIVE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_INTR_STAT_R_RX_DONE -// Description : See IC_RAW_INTR_STAT for a detailed description of R_RX_DONE -// bit. -// -// Reset value: 0x0 -// 0x0 -> R_RX_DONE interrupt is inactive -// 0x1 -> R_RX_DONE interrupt is active -#define I2C_IC_INTR_STAT_R_RX_DONE_RESET _u(0x0) -#define I2C_IC_INTR_STAT_R_RX_DONE_BITS _u(0x00000080) -#define I2C_IC_INTR_STAT_R_RX_DONE_MSB _u(7) -#define I2C_IC_INTR_STAT_R_RX_DONE_LSB _u(7) -#define I2C_IC_INTR_STAT_R_RX_DONE_ACCESS "RO" -#define I2C_IC_INTR_STAT_R_RX_DONE_VALUE_INACTIVE _u(0x0) -#define I2C_IC_INTR_STAT_R_RX_DONE_VALUE_ACTIVE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_INTR_STAT_R_TX_ABRT -// Description : See IC_RAW_INTR_STAT for a detailed description of R_TX_ABRT -// bit. -// -// Reset value: 0x0 -// 0x0 -> R_TX_ABRT interrupt is inactive -// 0x1 -> R_TX_ABRT interrupt is active -#define I2C_IC_INTR_STAT_R_TX_ABRT_RESET _u(0x0) -#define I2C_IC_INTR_STAT_R_TX_ABRT_BITS _u(0x00000040) -#define I2C_IC_INTR_STAT_R_TX_ABRT_MSB _u(6) -#define I2C_IC_INTR_STAT_R_TX_ABRT_LSB _u(6) -#define I2C_IC_INTR_STAT_R_TX_ABRT_ACCESS "RO" -#define I2C_IC_INTR_STAT_R_TX_ABRT_VALUE_INACTIVE _u(0x0) -#define I2C_IC_INTR_STAT_R_TX_ABRT_VALUE_ACTIVE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_INTR_STAT_R_RD_REQ -// Description : See IC_RAW_INTR_STAT for a detailed description of R_RD_REQ -// bit. -// -// Reset value: 0x0 -// 0x0 -> R_RD_REQ interrupt is inactive -// 0x1 -> R_RD_REQ interrupt is active -#define I2C_IC_INTR_STAT_R_RD_REQ_RESET _u(0x0) -#define I2C_IC_INTR_STAT_R_RD_REQ_BITS _u(0x00000020) -#define I2C_IC_INTR_STAT_R_RD_REQ_MSB _u(5) -#define I2C_IC_INTR_STAT_R_RD_REQ_LSB _u(5) -#define I2C_IC_INTR_STAT_R_RD_REQ_ACCESS "RO" -#define I2C_IC_INTR_STAT_R_RD_REQ_VALUE_INACTIVE _u(0x0) -#define I2C_IC_INTR_STAT_R_RD_REQ_VALUE_ACTIVE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_INTR_STAT_R_TX_EMPTY -// Description : See IC_RAW_INTR_STAT for a detailed description of R_TX_EMPTY -// bit. -// -// Reset value: 0x0 -// 0x0 -> R_TX_EMPTY interrupt is inactive -// 0x1 -> R_TX_EMPTY interrupt is active -#define I2C_IC_INTR_STAT_R_TX_EMPTY_RESET _u(0x0) -#define I2C_IC_INTR_STAT_R_TX_EMPTY_BITS _u(0x00000010) -#define I2C_IC_INTR_STAT_R_TX_EMPTY_MSB _u(4) -#define I2C_IC_INTR_STAT_R_TX_EMPTY_LSB _u(4) -#define I2C_IC_INTR_STAT_R_TX_EMPTY_ACCESS "RO" -#define I2C_IC_INTR_STAT_R_TX_EMPTY_VALUE_INACTIVE _u(0x0) -#define I2C_IC_INTR_STAT_R_TX_EMPTY_VALUE_ACTIVE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_INTR_STAT_R_TX_OVER -// Description : See IC_RAW_INTR_STAT for a detailed description of R_TX_OVER -// bit. -// -// Reset value: 0x0 -// 0x0 -> R_TX_OVER interrupt is inactive -// 0x1 -> R_TX_OVER interrupt is active -#define I2C_IC_INTR_STAT_R_TX_OVER_RESET _u(0x0) -#define I2C_IC_INTR_STAT_R_TX_OVER_BITS _u(0x00000008) -#define I2C_IC_INTR_STAT_R_TX_OVER_MSB _u(3) -#define I2C_IC_INTR_STAT_R_TX_OVER_LSB _u(3) -#define I2C_IC_INTR_STAT_R_TX_OVER_ACCESS "RO" -#define I2C_IC_INTR_STAT_R_TX_OVER_VALUE_INACTIVE _u(0x0) -#define I2C_IC_INTR_STAT_R_TX_OVER_VALUE_ACTIVE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_INTR_STAT_R_RX_FULL -// Description : See IC_RAW_INTR_STAT for a detailed description of R_RX_FULL -// bit. -// -// Reset value: 0x0 -// 0x0 -> R_RX_FULL interrupt is inactive -// 0x1 -> R_RX_FULL interrupt is active -#define I2C_IC_INTR_STAT_R_RX_FULL_RESET _u(0x0) -#define I2C_IC_INTR_STAT_R_RX_FULL_BITS _u(0x00000004) -#define I2C_IC_INTR_STAT_R_RX_FULL_MSB _u(2) -#define I2C_IC_INTR_STAT_R_RX_FULL_LSB _u(2) -#define I2C_IC_INTR_STAT_R_RX_FULL_ACCESS "RO" -#define I2C_IC_INTR_STAT_R_RX_FULL_VALUE_INACTIVE _u(0x0) -#define I2C_IC_INTR_STAT_R_RX_FULL_VALUE_ACTIVE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_INTR_STAT_R_RX_OVER -// Description : See IC_RAW_INTR_STAT for a detailed description of R_RX_OVER -// bit. -// -// Reset value: 0x0 -// 0x0 -> R_RX_OVER interrupt is inactive -// 0x1 -> R_RX_OVER interrupt is active -#define I2C_IC_INTR_STAT_R_RX_OVER_RESET _u(0x0) -#define I2C_IC_INTR_STAT_R_RX_OVER_BITS _u(0x00000002) -#define I2C_IC_INTR_STAT_R_RX_OVER_MSB _u(1) -#define I2C_IC_INTR_STAT_R_RX_OVER_LSB _u(1) -#define I2C_IC_INTR_STAT_R_RX_OVER_ACCESS "RO" -#define I2C_IC_INTR_STAT_R_RX_OVER_VALUE_INACTIVE _u(0x0) -#define I2C_IC_INTR_STAT_R_RX_OVER_VALUE_ACTIVE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_INTR_STAT_R_RX_UNDER -// Description : See IC_RAW_INTR_STAT for a detailed description of R_RX_UNDER -// bit. -// -// Reset value: 0x0 -// 0x0 -> RX_UNDER interrupt is inactive -// 0x1 -> RX_UNDER interrupt is active -#define I2C_IC_INTR_STAT_R_RX_UNDER_RESET _u(0x0) -#define I2C_IC_INTR_STAT_R_RX_UNDER_BITS _u(0x00000001) -#define I2C_IC_INTR_STAT_R_RX_UNDER_MSB _u(0) -#define I2C_IC_INTR_STAT_R_RX_UNDER_LSB _u(0) -#define I2C_IC_INTR_STAT_R_RX_UNDER_ACCESS "RO" -#define I2C_IC_INTR_STAT_R_RX_UNDER_VALUE_INACTIVE _u(0x0) -#define I2C_IC_INTR_STAT_R_RX_UNDER_VALUE_ACTIVE _u(0x1) -// ============================================================================= -// Register : I2C_IC_INTR_MASK -// Description : I2C Interrupt Mask Register. -// -// These bits mask their corresponding interrupt status bits. This -// register is active low; a value of 0 masks the interrupt, -// whereas a value of 1 unmasks the interrupt. -#define I2C_IC_INTR_MASK_OFFSET _u(0x00000030) -#define I2C_IC_INTR_MASK_BITS _u(0x00001fff) -#define I2C_IC_INTR_MASK_RESET _u(0x000008ff) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_INTR_MASK_M_RESTART_DET -// Description : This bit masks the R_RESTART_DET interrupt in IC_INTR_STAT -// register. -// -// Reset value: 0x0 -// 0x0 -> RESTART_DET interrupt is masked -// 0x1 -> RESTART_DET interrupt is unmasked -#define I2C_IC_INTR_MASK_M_RESTART_DET_RESET _u(0x0) -#define I2C_IC_INTR_MASK_M_RESTART_DET_BITS _u(0x00001000) -#define I2C_IC_INTR_MASK_M_RESTART_DET_MSB _u(12) -#define I2C_IC_INTR_MASK_M_RESTART_DET_LSB _u(12) -#define I2C_IC_INTR_MASK_M_RESTART_DET_ACCESS "RW" -#define I2C_IC_INTR_MASK_M_RESTART_DET_VALUE_ENABLED _u(0x0) -#define I2C_IC_INTR_MASK_M_RESTART_DET_VALUE_DISABLED _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_INTR_MASK_M_GEN_CALL -// Description : This bit masks the R_GEN_CALL interrupt in IC_INTR_STAT -// register. -// -// Reset value: 0x1 -// 0x0 -> GEN_CALL interrupt is masked -// 0x1 -> GEN_CALL interrupt is unmasked -#define I2C_IC_INTR_MASK_M_GEN_CALL_RESET _u(0x1) -#define I2C_IC_INTR_MASK_M_GEN_CALL_BITS _u(0x00000800) -#define I2C_IC_INTR_MASK_M_GEN_CALL_MSB _u(11) -#define I2C_IC_INTR_MASK_M_GEN_CALL_LSB _u(11) -#define I2C_IC_INTR_MASK_M_GEN_CALL_ACCESS "RW" -#define I2C_IC_INTR_MASK_M_GEN_CALL_VALUE_ENABLED _u(0x0) -#define I2C_IC_INTR_MASK_M_GEN_CALL_VALUE_DISABLED _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_INTR_MASK_M_START_DET -// Description : This bit masks the R_START_DET interrupt in IC_INTR_STAT -// register. -// -// Reset value: 0x0 -// 0x0 -> START_DET interrupt is masked -// 0x1 -> START_DET interrupt is unmasked -#define I2C_IC_INTR_MASK_M_START_DET_RESET _u(0x0) -#define I2C_IC_INTR_MASK_M_START_DET_BITS _u(0x00000400) -#define I2C_IC_INTR_MASK_M_START_DET_MSB _u(10) -#define I2C_IC_INTR_MASK_M_START_DET_LSB _u(10) -#define I2C_IC_INTR_MASK_M_START_DET_ACCESS "RW" -#define I2C_IC_INTR_MASK_M_START_DET_VALUE_ENABLED _u(0x0) -#define I2C_IC_INTR_MASK_M_START_DET_VALUE_DISABLED _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_INTR_MASK_M_STOP_DET -// Description : This bit masks the R_STOP_DET interrupt in IC_INTR_STAT -// register. -// -// Reset value: 0x0 -// 0x0 -> STOP_DET interrupt is masked -// 0x1 -> STOP_DET interrupt is unmasked -#define I2C_IC_INTR_MASK_M_STOP_DET_RESET _u(0x0) -#define I2C_IC_INTR_MASK_M_STOP_DET_BITS _u(0x00000200) -#define I2C_IC_INTR_MASK_M_STOP_DET_MSB _u(9) -#define I2C_IC_INTR_MASK_M_STOP_DET_LSB _u(9) -#define I2C_IC_INTR_MASK_M_STOP_DET_ACCESS "RW" -#define I2C_IC_INTR_MASK_M_STOP_DET_VALUE_ENABLED _u(0x0) -#define I2C_IC_INTR_MASK_M_STOP_DET_VALUE_DISABLED _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_INTR_MASK_M_ACTIVITY -// Description : This bit masks the R_ACTIVITY interrupt in IC_INTR_STAT -// register. -// -// Reset value: 0x0 -// 0x0 -> ACTIVITY interrupt is masked -// 0x1 -> ACTIVITY interrupt is unmasked -#define I2C_IC_INTR_MASK_M_ACTIVITY_RESET _u(0x0) -#define I2C_IC_INTR_MASK_M_ACTIVITY_BITS _u(0x00000100) -#define I2C_IC_INTR_MASK_M_ACTIVITY_MSB _u(8) -#define I2C_IC_INTR_MASK_M_ACTIVITY_LSB _u(8) -#define I2C_IC_INTR_MASK_M_ACTIVITY_ACCESS "RW" -#define I2C_IC_INTR_MASK_M_ACTIVITY_VALUE_ENABLED _u(0x0) -#define I2C_IC_INTR_MASK_M_ACTIVITY_VALUE_DISABLED _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_INTR_MASK_M_RX_DONE -// Description : This bit masks the R_RX_DONE interrupt in IC_INTR_STAT -// register. -// -// Reset value: 0x1 -// 0x0 -> RX_DONE interrupt is masked -// 0x1 -> RX_DONE interrupt is unmasked -#define I2C_IC_INTR_MASK_M_RX_DONE_RESET _u(0x1) -#define I2C_IC_INTR_MASK_M_RX_DONE_BITS _u(0x00000080) -#define I2C_IC_INTR_MASK_M_RX_DONE_MSB _u(7) -#define I2C_IC_INTR_MASK_M_RX_DONE_LSB _u(7) -#define I2C_IC_INTR_MASK_M_RX_DONE_ACCESS "RW" -#define I2C_IC_INTR_MASK_M_RX_DONE_VALUE_ENABLED _u(0x0) -#define I2C_IC_INTR_MASK_M_RX_DONE_VALUE_DISABLED _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_INTR_MASK_M_TX_ABRT -// Description : This bit masks the R_TX_ABRT interrupt in IC_INTR_STAT -// register. -// -// Reset value: 0x1 -// 0x0 -> TX_ABORT interrupt is masked -// 0x1 -> TX_ABORT interrupt is unmasked -#define I2C_IC_INTR_MASK_M_TX_ABRT_RESET _u(0x1) -#define I2C_IC_INTR_MASK_M_TX_ABRT_BITS _u(0x00000040) -#define I2C_IC_INTR_MASK_M_TX_ABRT_MSB _u(6) -#define I2C_IC_INTR_MASK_M_TX_ABRT_LSB _u(6) -#define I2C_IC_INTR_MASK_M_TX_ABRT_ACCESS "RW" -#define I2C_IC_INTR_MASK_M_TX_ABRT_VALUE_ENABLED _u(0x0) -#define I2C_IC_INTR_MASK_M_TX_ABRT_VALUE_DISABLED _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_INTR_MASK_M_RD_REQ -// Description : This bit masks the R_RD_REQ interrupt in IC_INTR_STAT register. -// -// Reset value: 0x1 -// 0x0 -> RD_REQ interrupt is masked -// 0x1 -> RD_REQ interrupt is unmasked -#define I2C_IC_INTR_MASK_M_RD_REQ_RESET _u(0x1) -#define I2C_IC_INTR_MASK_M_RD_REQ_BITS _u(0x00000020) -#define I2C_IC_INTR_MASK_M_RD_REQ_MSB _u(5) -#define I2C_IC_INTR_MASK_M_RD_REQ_LSB _u(5) -#define I2C_IC_INTR_MASK_M_RD_REQ_ACCESS "RW" -#define I2C_IC_INTR_MASK_M_RD_REQ_VALUE_ENABLED _u(0x0) -#define I2C_IC_INTR_MASK_M_RD_REQ_VALUE_DISABLED _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_INTR_MASK_M_TX_EMPTY -// Description : This bit masks the R_TX_EMPTY interrupt in IC_INTR_STAT -// register. -// -// Reset value: 0x1 -// 0x0 -> TX_EMPTY interrupt is masked -// 0x1 -> TX_EMPTY interrupt is unmasked -#define I2C_IC_INTR_MASK_M_TX_EMPTY_RESET _u(0x1) -#define I2C_IC_INTR_MASK_M_TX_EMPTY_BITS _u(0x00000010) -#define I2C_IC_INTR_MASK_M_TX_EMPTY_MSB _u(4) -#define I2C_IC_INTR_MASK_M_TX_EMPTY_LSB _u(4) -#define I2C_IC_INTR_MASK_M_TX_EMPTY_ACCESS "RW" -#define I2C_IC_INTR_MASK_M_TX_EMPTY_VALUE_ENABLED _u(0x0) -#define I2C_IC_INTR_MASK_M_TX_EMPTY_VALUE_DISABLED _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_INTR_MASK_M_TX_OVER -// Description : This bit masks the R_TX_OVER interrupt in IC_INTR_STAT -// register. -// -// Reset value: 0x1 -// 0x0 -> TX_OVER interrupt is masked -// 0x1 -> TX_OVER interrupt is unmasked -#define I2C_IC_INTR_MASK_M_TX_OVER_RESET _u(0x1) -#define I2C_IC_INTR_MASK_M_TX_OVER_BITS _u(0x00000008) -#define I2C_IC_INTR_MASK_M_TX_OVER_MSB _u(3) -#define I2C_IC_INTR_MASK_M_TX_OVER_LSB _u(3) -#define I2C_IC_INTR_MASK_M_TX_OVER_ACCESS "RW" -#define I2C_IC_INTR_MASK_M_TX_OVER_VALUE_ENABLED _u(0x0) -#define I2C_IC_INTR_MASK_M_TX_OVER_VALUE_DISABLED _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_INTR_MASK_M_RX_FULL -// Description : This bit masks the R_RX_FULL interrupt in IC_INTR_STAT -// register. -// -// Reset value: 0x1 -// 0x0 -> RX_FULL interrupt is masked -// 0x1 -> RX_FULL interrupt is unmasked -#define I2C_IC_INTR_MASK_M_RX_FULL_RESET _u(0x1) -#define I2C_IC_INTR_MASK_M_RX_FULL_BITS _u(0x00000004) -#define I2C_IC_INTR_MASK_M_RX_FULL_MSB _u(2) -#define I2C_IC_INTR_MASK_M_RX_FULL_LSB _u(2) -#define I2C_IC_INTR_MASK_M_RX_FULL_ACCESS "RW" -#define I2C_IC_INTR_MASK_M_RX_FULL_VALUE_ENABLED _u(0x0) -#define I2C_IC_INTR_MASK_M_RX_FULL_VALUE_DISABLED _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_INTR_MASK_M_RX_OVER -// Description : This bit masks the R_RX_OVER interrupt in IC_INTR_STAT -// register. -// -// Reset value: 0x1 -// 0x0 -> RX_OVER interrupt is masked -// 0x1 -> RX_OVER interrupt is unmasked -#define I2C_IC_INTR_MASK_M_RX_OVER_RESET _u(0x1) -#define I2C_IC_INTR_MASK_M_RX_OVER_BITS _u(0x00000002) -#define I2C_IC_INTR_MASK_M_RX_OVER_MSB _u(1) -#define I2C_IC_INTR_MASK_M_RX_OVER_LSB _u(1) -#define I2C_IC_INTR_MASK_M_RX_OVER_ACCESS "RW" -#define I2C_IC_INTR_MASK_M_RX_OVER_VALUE_ENABLED _u(0x0) -#define I2C_IC_INTR_MASK_M_RX_OVER_VALUE_DISABLED _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_INTR_MASK_M_RX_UNDER -// Description : This bit masks the R_RX_UNDER interrupt in IC_INTR_STAT -// register. -// -// Reset value: 0x1 -// 0x0 -> RX_UNDER interrupt is masked -// 0x1 -> RX_UNDER interrupt is unmasked -#define I2C_IC_INTR_MASK_M_RX_UNDER_RESET _u(0x1) -#define I2C_IC_INTR_MASK_M_RX_UNDER_BITS _u(0x00000001) -#define I2C_IC_INTR_MASK_M_RX_UNDER_MSB _u(0) -#define I2C_IC_INTR_MASK_M_RX_UNDER_LSB _u(0) -#define I2C_IC_INTR_MASK_M_RX_UNDER_ACCESS "RW" -#define I2C_IC_INTR_MASK_M_RX_UNDER_VALUE_ENABLED _u(0x0) -#define I2C_IC_INTR_MASK_M_RX_UNDER_VALUE_DISABLED _u(0x1) -// ============================================================================= -// Register : I2C_IC_RAW_INTR_STAT -// Description : I2C Raw Interrupt Status Register -// -// Unlike the IC_INTR_STAT register, these bits are not masked so -// they always show the true status of the DW_apb_i2c. -#define I2C_IC_RAW_INTR_STAT_OFFSET _u(0x00000034) -#define I2C_IC_RAW_INTR_STAT_BITS _u(0x00001fff) -#define I2C_IC_RAW_INTR_STAT_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_RAW_INTR_STAT_RESTART_DET -// Description : Indicates whether a RESTART condition has occurred on the I2C -// interface when DW_apb_i2c is operating in Slave mode and the -// slave is being addressed. Enabled only when -// IC_SLV_RESTART_DET_EN=1. -// -// Note: However, in high-speed mode or during a START BYTE -// transfer, the RESTART comes before the address field as per the -// I2C protocol. In this case, the slave is not the addressed -// slave when the RESTART is issued, therefore DW_apb_i2c does not -// generate the RESTART_DET interrupt. -// -// Reset value: 0x0 -// 0x0 -> RESTART_DET interrupt is inactive -// 0x1 -> RESTART_DET interrupt is active -#define I2C_IC_RAW_INTR_STAT_RESTART_DET_RESET _u(0x0) -#define I2C_IC_RAW_INTR_STAT_RESTART_DET_BITS _u(0x00001000) -#define I2C_IC_RAW_INTR_STAT_RESTART_DET_MSB _u(12) -#define I2C_IC_RAW_INTR_STAT_RESTART_DET_LSB _u(12) -#define I2C_IC_RAW_INTR_STAT_RESTART_DET_ACCESS "RO" -#define I2C_IC_RAW_INTR_STAT_RESTART_DET_VALUE_INACTIVE _u(0x0) -#define I2C_IC_RAW_INTR_STAT_RESTART_DET_VALUE_ACTIVE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_RAW_INTR_STAT_GEN_CALL -// Description : Set only when a General Call address is received and it is -// acknowledged. It stays set until it is cleared either by -// disabling DW_apb_i2c or when the CPU reads bit 0 of the -// IC_CLR_GEN_CALL register. DW_apb_i2c stores the received data -// in the Rx buffer. -// -// Reset value: 0x0 -// 0x0 -> GEN_CALL interrupt is inactive -// 0x1 -> GEN_CALL interrupt is active -#define I2C_IC_RAW_INTR_STAT_GEN_CALL_RESET _u(0x0) -#define I2C_IC_RAW_INTR_STAT_GEN_CALL_BITS _u(0x00000800) -#define I2C_IC_RAW_INTR_STAT_GEN_CALL_MSB _u(11) -#define I2C_IC_RAW_INTR_STAT_GEN_CALL_LSB _u(11) -#define I2C_IC_RAW_INTR_STAT_GEN_CALL_ACCESS "RO" -#define I2C_IC_RAW_INTR_STAT_GEN_CALL_VALUE_INACTIVE _u(0x0) -#define I2C_IC_RAW_INTR_STAT_GEN_CALL_VALUE_ACTIVE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_RAW_INTR_STAT_START_DET -// Description : Indicates whether a START or RESTART condition has occurred on -// the I2C interface regardless of whether DW_apb_i2c is operating -// in slave or master mode. -// -// Reset value: 0x0 -// 0x0 -> START_DET interrupt is inactive -// 0x1 -> START_DET interrupt is active -#define I2C_IC_RAW_INTR_STAT_START_DET_RESET _u(0x0) -#define I2C_IC_RAW_INTR_STAT_START_DET_BITS _u(0x00000400) -#define I2C_IC_RAW_INTR_STAT_START_DET_MSB _u(10) -#define I2C_IC_RAW_INTR_STAT_START_DET_LSB _u(10) -#define I2C_IC_RAW_INTR_STAT_START_DET_ACCESS "RO" -#define I2C_IC_RAW_INTR_STAT_START_DET_VALUE_INACTIVE _u(0x0) -#define I2C_IC_RAW_INTR_STAT_START_DET_VALUE_ACTIVE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_RAW_INTR_STAT_STOP_DET -// Description : Indicates whether a STOP condition has occurred on the I2C -// interface regardless of whether DW_apb_i2c is operating in -// slave or master mode. -// -// In Slave Mode: - If IC_CON[7]=1'b1 (STOP_DET_IFADDRESSED), the -// STOP_DET interrupt will be issued only if slave is addressed. -// Note: During a general call address, this slave does not issue -// a STOP_DET interrupt if STOP_DET_IF_ADDRESSED=1'b1, even if the -// slave responds to the general call address by generating ACK. -// The STOP_DET interrupt is generated only when the transmitted -// address matches the slave address (SAR). - If IC_CON[7]=1'b0 -// (STOP_DET_IFADDRESSED), the STOP_DET interrupt is issued -// irrespective of whether it is being addressed. In Master Mode: -// - If IC_CON[10]=1'b1 (STOP_DET_IF_MASTER_ACTIVE),the STOP_DET -// interrupt will be issued only if Master is active. - If -// IC_CON[10]=1'b0 (STOP_DET_IFADDRESSED),the STOP_DET interrupt -// will be issued irrespective of whether master is active or not. -// Reset value: 0x0 -// 0x0 -> STOP_DET interrupt is inactive -// 0x1 -> STOP_DET interrupt is active -#define I2C_IC_RAW_INTR_STAT_STOP_DET_RESET _u(0x0) -#define I2C_IC_RAW_INTR_STAT_STOP_DET_BITS _u(0x00000200) -#define I2C_IC_RAW_INTR_STAT_STOP_DET_MSB _u(9) -#define I2C_IC_RAW_INTR_STAT_STOP_DET_LSB _u(9) -#define I2C_IC_RAW_INTR_STAT_STOP_DET_ACCESS "RO" -#define I2C_IC_RAW_INTR_STAT_STOP_DET_VALUE_INACTIVE _u(0x0) -#define I2C_IC_RAW_INTR_STAT_STOP_DET_VALUE_ACTIVE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_RAW_INTR_STAT_ACTIVITY -// Description : This bit captures DW_apb_i2c activity and stays set until it is -// cleared. There are four ways to clear it: - Disabling the -// DW_apb_i2c - Reading the IC_CLR_ACTIVITY register - Reading the -// IC_CLR_INTR register - System reset Once this bit is set, it -// stays set unless one of the four methods is used to clear it. -// Even if the DW_apb_i2c module is idle, this bit remains set -// until cleared, indicating that there was activity on the bus. -// -// Reset value: 0x0 -// 0x0 -> RAW_INTR_ACTIVITY interrupt is inactive -// 0x1 -> RAW_INTR_ACTIVITY interrupt is active -#define I2C_IC_RAW_INTR_STAT_ACTIVITY_RESET _u(0x0) -#define I2C_IC_RAW_INTR_STAT_ACTIVITY_BITS _u(0x00000100) -#define I2C_IC_RAW_INTR_STAT_ACTIVITY_MSB _u(8) -#define I2C_IC_RAW_INTR_STAT_ACTIVITY_LSB _u(8) -#define I2C_IC_RAW_INTR_STAT_ACTIVITY_ACCESS "RO" -#define I2C_IC_RAW_INTR_STAT_ACTIVITY_VALUE_INACTIVE _u(0x0) -#define I2C_IC_RAW_INTR_STAT_ACTIVITY_VALUE_ACTIVE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_RAW_INTR_STAT_RX_DONE -// Description : When the DW_apb_i2c is acting as a slave-transmitter, this bit -// is set to 1 if the master does not acknowledge a transmitted -// byte. This occurs on the last byte of the transmission, -// indicating that the transmission is done. -// -// Reset value: 0x0 -// 0x0 -> RX_DONE interrupt is inactive -// 0x1 -> RX_DONE interrupt is active -#define I2C_IC_RAW_INTR_STAT_RX_DONE_RESET _u(0x0) -#define I2C_IC_RAW_INTR_STAT_RX_DONE_BITS _u(0x00000080) -#define I2C_IC_RAW_INTR_STAT_RX_DONE_MSB _u(7) -#define I2C_IC_RAW_INTR_STAT_RX_DONE_LSB _u(7) -#define I2C_IC_RAW_INTR_STAT_RX_DONE_ACCESS "RO" -#define I2C_IC_RAW_INTR_STAT_RX_DONE_VALUE_INACTIVE _u(0x0) -#define I2C_IC_RAW_INTR_STAT_RX_DONE_VALUE_ACTIVE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_RAW_INTR_STAT_TX_ABRT -// Description : This bit indicates if DW_apb_i2c, as an I2C transmitter, is -// unable to complete the intended actions on the contents of the -// transmit FIFO. This situation can occur both as an I2C master -// or an I2C slave, and is referred to as a 'transmit abort'. When -// this bit is set to 1, the IC_TX_ABRT_SOURCE register indicates -// the reason why the transmit abort takes places. -// -// Note: The DW_apb_i2c flushes/resets/empties the TX_FIFO and -// RX_FIFO whenever there is a transmit abort caused by any of the -// events tracked by the IC_TX_ABRT_SOURCE register. The FIFOs -// remains in this flushed state until the register IC_CLR_TX_ABRT -// is read. Once this read is performed, the Tx FIFO is then ready -// to accept more data bytes from the APB interface. -// -// Reset value: 0x0 -// 0x0 -> TX_ABRT interrupt is inactive -// 0x1 -> TX_ABRT interrupt is active -#define I2C_IC_RAW_INTR_STAT_TX_ABRT_RESET _u(0x0) -#define I2C_IC_RAW_INTR_STAT_TX_ABRT_BITS _u(0x00000040) -#define I2C_IC_RAW_INTR_STAT_TX_ABRT_MSB _u(6) -#define I2C_IC_RAW_INTR_STAT_TX_ABRT_LSB _u(6) -#define I2C_IC_RAW_INTR_STAT_TX_ABRT_ACCESS "RO" -#define I2C_IC_RAW_INTR_STAT_TX_ABRT_VALUE_INACTIVE _u(0x0) -#define I2C_IC_RAW_INTR_STAT_TX_ABRT_VALUE_ACTIVE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_RAW_INTR_STAT_RD_REQ -// Description : This bit is set to 1 when DW_apb_i2c is acting as a slave and -// another I2C master is attempting to read data from DW_apb_i2c. -// The DW_apb_i2c holds the I2C bus in a wait state (SCL=0) until -// this interrupt is serviced, which means that the slave has been -// addressed by a remote master that is asking for data to be -// transferred. The processor must respond to this interrupt and -// then write the requested data to the IC_DATA_CMD register. This -// bit is set to 0 just after the processor reads the -// IC_CLR_RD_REQ register. -// -// Reset value: 0x0 -// 0x0 -> RD_REQ interrupt is inactive -// 0x1 -> RD_REQ interrupt is active -#define I2C_IC_RAW_INTR_STAT_RD_REQ_RESET _u(0x0) -#define I2C_IC_RAW_INTR_STAT_RD_REQ_BITS _u(0x00000020) -#define I2C_IC_RAW_INTR_STAT_RD_REQ_MSB _u(5) -#define I2C_IC_RAW_INTR_STAT_RD_REQ_LSB _u(5) -#define I2C_IC_RAW_INTR_STAT_RD_REQ_ACCESS "RO" -#define I2C_IC_RAW_INTR_STAT_RD_REQ_VALUE_INACTIVE _u(0x0) -#define I2C_IC_RAW_INTR_STAT_RD_REQ_VALUE_ACTIVE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_RAW_INTR_STAT_TX_EMPTY -// Description : The behavior of the TX_EMPTY interrupt status differs based on -// the TX_EMPTY_CTRL selection in the IC_CON register. - When -// TX_EMPTY_CTRL = 0: This bit is set to 1 when the transmit -// buffer is at or below the threshold value set in the IC_TX_TL -// register. - When TX_EMPTY_CTRL = 1: This bit is set to 1 when -// the transmit buffer is at or below the threshold value set in -// the IC_TX_TL register and the transmission of the address/data -// from the internal shift register for the most recently popped -// command is completed. It is automatically cleared by hardware -// when the buffer level goes above the threshold. When -// IC_ENABLE[0] is set to 0, the TX FIFO is flushed and held in -// reset. There the TX FIFO looks like it has no data within it, -// so this bit is set to 1, provided there is activity in the -// master or slave state machines. When there is no longer any -// activity, then with ic_en=0, this bit is set to 0. -// -// Reset value: 0x0. -// 0x0 -> TX_EMPTY interrupt is inactive -// 0x1 -> TX_EMPTY interrupt is active -#define I2C_IC_RAW_INTR_STAT_TX_EMPTY_RESET _u(0x0) -#define I2C_IC_RAW_INTR_STAT_TX_EMPTY_BITS _u(0x00000010) -#define I2C_IC_RAW_INTR_STAT_TX_EMPTY_MSB _u(4) -#define I2C_IC_RAW_INTR_STAT_TX_EMPTY_LSB _u(4) -#define I2C_IC_RAW_INTR_STAT_TX_EMPTY_ACCESS "RO" -#define I2C_IC_RAW_INTR_STAT_TX_EMPTY_VALUE_INACTIVE _u(0x0) -#define I2C_IC_RAW_INTR_STAT_TX_EMPTY_VALUE_ACTIVE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_RAW_INTR_STAT_TX_OVER -// Description : Set during transmit if the transmit buffer is filled to -// IC_TX_BUFFER_DEPTH and the processor attempts to issue another -// I2C command by writing to the IC_DATA_CMD register. When the -// module is disabled, this bit keeps its level until the master -// or slave state machines go into idle, and when ic_en goes to 0, -// this interrupt is cleared. -// -// Reset value: 0x0 -// 0x0 -> TX_OVER interrupt is inactive -// 0x1 -> TX_OVER interrupt is active -#define I2C_IC_RAW_INTR_STAT_TX_OVER_RESET _u(0x0) -#define I2C_IC_RAW_INTR_STAT_TX_OVER_BITS _u(0x00000008) -#define I2C_IC_RAW_INTR_STAT_TX_OVER_MSB _u(3) -#define I2C_IC_RAW_INTR_STAT_TX_OVER_LSB _u(3) -#define I2C_IC_RAW_INTR_STAT_TX_OVER_ACCESS "RO" -#define I2C_IC_RAW_INTR_STAT_TX_OVER_VALUE_INACTIVE _u(0x0) -#define I2C_IC_RAW_INTR_STAT_TX_OVER_VALUE_ACTIVE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_RAW_INTR_STAT_RX_FULL -// Description : Set when the receive buffer reaches or goes above the RX_TL -// threshold in the IC_RX_TL register. It is automatically cleared -// by hardware when buffer level goes below the threshold. If the -// module is disabled (IC_ENABLE[0]=0), the RX FIFO is flushed and -// held in reset; therefore the RX FIFO is not full. So this bit -// is cleared once the IC_ENABLE bit 0 is programmed with a 0, -// regardless of the activity that continues. -// -// Reset value: 0x0 -// 0x0 -> RX_FULL interrupt is inactive -// 0x1 -> RX_FULL interrupt is active -#define I2C_IC_RAW_INTR_STAT_RX_FULL_RESET _u(0x0) -#define I2C_IC_RAW_INTR_STAT_RX_FULL_BITS _u(0x00000004) -#define I2C_IC_RAW_INTR_STAT_RX_FULL_MSB _u(2) -#define I2C_IC_RAW_INTR_STAT_RX_FULL_LSB _u(2) -#define I2C_IC_RAW_INTR_STAT_RX_FULL_ACCESS "RO" -#define I2C_IC_RAW_INTR_STAT_RX_FULL_VALUE_INACTIVE _u(0x0) -#define I2C_IC_RAW_INTR_STAT_RX_FULL_VALUE_ACTIVE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_RAW_INTR_STAT_RX_OVER -// Description : Set if the receive buffer is completely filled to -// IC_RX_BUFFER_DEPTH and an additional byte is received from an -// external I2C device. The DW_apb_i2c acknowledges this, but any -// data bytes received after the FIFO is full are lost. If the -// module is disabled (IC_ENABLE[0]=0), this bit keeps its level -// until the master or slave state machines go into idle, and when -// ic_en goes to 0, this interrupt is cleared. -// -// Note: If bit 9 of the IC_CON register (RX_FIFO_FULL_HLD_CTRL) -// is programmed to HIGH, then the RX_OVER interrupt never occurs, -// because the Rx FIFO never overflows. -// -// Reset value: 0x0 -// 0x0 -> RX_OVER interrupt is inactive -// 0x1 -> RX_OVER interrupt is active -#define I2C_IC_RAW_INTR_STAT_RX_OVER_RESET _u(0x0) -#define I2C_IC_RAW_INTR_STAT_RX_OVER_BITS _u(0x00000002) -#define I2C_IC_RAW_INTR_STAT_RX_OVER_MSB _u(1) -#define I2C_IC_RAW_INTR_STAT_RX_OVER_LSB _u(1) -#define I2C_IC_RAW_INTR_STAT_RX_OVER_ACCESS "RO" -#define I2C_IC_RAW_INTR_STAT_RX_OVER_VALUE_INACTIVE _u(0x0) -#define I2C_IC_RAW_INTR_STAT_RX_OVER_VALUE_ACTIVE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_RAW_INTR_STAT_RX_UNDER -// Description : Set if the processor attempts to read the receive buffer when -// it is empty by reading from the IC_DATA_CMD register. If the -// module is disabled (IC_ENABLE[0]=0), this bit keeps its level -// until the master or slave state machines go into idle, and when -// ic_en goes to 0, this interrupt is cleared. -// -// Reset value: 0x0 -// 0x0 -> RX_UNDER interrupt is inactive -// 0x1 -> RX_UNDER interrupt is active -#define I2C_IC_RAW_INTR_STAT_RX_UNDER_RESET _u(0x0) -#define I2C_IC_RAW_INTR_STAT_RX_UNDER_BITS _u(0x00000001) -#define I2C_IC_RAW_INTR_STAT_RX_UNDER_MSB _u(0) -#define I2C_IC_RAW_INTR_STAT_RX_UNDER_LSB _u(0) -#define I2C_IC_RAW_INTR_STAT_RX_UNDER_ACCESS "RO" -#define I2C_IC_RAW_INTR_STAT_RX_UNDER_VALUE_INACTIVE _u(0x0) -#define I2C_IC_RAW_INTR_STAT_RX_UNDER_VALUE_ACTIVE _u(0x1) -// ============================================================================= -// Register : I2C_IC_RX_TL -// Description : I2C Receive FIFO Threshold Register -#define I2C_IC_RX_TL_OFFSET _u(0x00000038) -#define I2C_IC_RX_TL_BITS _u(0x000000ff) -#define I2C_IC_RX_TL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_RX_TL_RX_TL -// Description : Receive FIFO Threshold Level. -// -// Controls the level of entries (or above) that triggers the -// RX_FULL interrupt (bit 2 in IC_RAW_INTR_STAT register). The -// valid range is 0-255, with the additional restriction that -// hardware does not allow this value to be set to a value larger -// than the depth of the buffer. If an attempt is made to do that, -// the actual value set will be the maximum depth of the buffer. A -// value of 0 sets the threshold for 1 entry, and a value of 255 -// sets the threshold for 256 entries. -#define I2C_IC_RX_TL_RX_TL_RESET _u(0x00) -#define I2C_IC_RX_TL_RX_TL_BITS _u(0x000000ff) -#define I2C_IC_RX_TL_RX_TL_MSB _u(7) -#define I2C_IC_RX_TL_RX_TL_LSB _u(0) -#define I2C_IC_RX_TL_RX_TL_ACCESS "RW" -// ============================================================================= -// Register : I2C_IC_TX_TL -// Description : I2C Transmit FIFO Threshold Register -#define I2C_IC_TX_TL_OFFSET _u(0x0000003c) -#define I2C_IC_TX_TL_BITS _u(0x000000ff) -#define I2C_IC_TX_TL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_TX_TL_TX_TL -// Description : Transmit FIFO Threshold Level. -// -// Controls the level of entries (or below) that trigger the -// TX_EMPTY interrupt (bit 4 in IC_RAW_INTR_STAT register). The -// valid range is 0-255, with the additional restriction that it -// may not be set to value larger than the depth of the buffer. If -// an attempt is made to do that, the actual value set will be the -// maximum depth of the buffer. A value of 0 sets the threshold -// for 0 entries, and a value of 255 sets the threshold for 255 -// entries. -#define I2C_IC_TX_TL_TX_TL_RESET _u(0x00) -#define I2C_IC_TX_TL_TX_TL_BITS _u(0x000000ff) -#define I2C_IC_TX_TL_TX_TL_MSB _u(7) -#define I2C_IC_TX_TL_TX_TL_LSB _u(0) -#define I2C_IC_TX_TL_TX_TL_ACCESS "RW" -// ============================================================================= -// Register : I2C_IC_CLR_INTR -// Description : Clear Combined and Individual Interrupt Register -#define I2C_IC_CLR_INTR_OFFSET _u(0x00000040) -#define I2C_IC_CLR_INTR_BITS _u(0x00000001) -#define I2C_IC_CLR_INTR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_CLR_INTR_CLR_INTR -// Description : Read this register to clear the combined interrupt, all -// individual interrupts, and the IC_TX_ABRT_SOURCE register. This -// bit does not clear hardware clearable interrupts but software -// clearable interrupts. Refer to Bit 9 of the IC_TX_ABRT_SOURCE -// register for an exception to clearing IC_TX_ABRT_SOURCE. -// -// Reset value: 0x0 -#define I2C_IC_CLR_INTR_CLR_INTR_RESET _u(0x0) -#define I2C_IC_CLR_INTR_CLR_INTR_BITS _u(0x00000001) -#define I2C_IC_CLR_INTR_CLR_INTR_MSB _u(0) -#define I2C_IC_CLR_INTR_CLR_INTR_LSB _u(0) -#define I2C_IC_CLR_INTR_CLR_INTR_ACCESS "RO" -// ============================================================================= -// Register : I2C_IC_CLR_RX_UNDER -// Description : Clear RX_UNDER Interrupt Register -#define I2C_IC_CLR_RX_UNDER_OFFSET _u(0x00000044) -#define I2C_IC_CLR_RX_UNDER_BITS _u(0x00000001) -#define I2C_IC_CLR_RX_UNDER_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_CLR_RX_UNDER_CLR_RX_UNDER -// Description : Read this register to clear the RX_UNDER interrupt (bit 0) of -// the IC_RAW_INTR_STAT register. -// -// Reset value: 0x0 -#define I2C_IC_CLR_RX_UNDER_CLR_RX_UNDER_RESET _u(0x0) -#define I2C_IC_CLR_RX_UNDER_CLR_RX_UNDER_BITS _u(0x00000001) -#define I2C_IC_CLR_RX_UNDER_CLR_RX_UNDER_MSB _u(0) -#define I2C_IC_CLR_RX_UNDER_CLR_RX_UNDER_LSB _u(0) -#define I2C_IC_CLR_RX_UNDER_CLR_RX_UNDER_ACCESS "RO" -// ============================================================================= -// Register : I2C_IC_CLR_RX_OVER -// Description : Clear RX_OVER Interrupt Register -#define I2C_IC_CLR_RX_OVER_OFFSET _u(0x00000048) -#define I2C_IC_CLR_RX_OVER_BITS _u(0x00000001) -#define I2C_IC_CLR_RX_OVER_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_CLR_RX_OVER_CLR_RX_OVER -// Description : Read this register to clear the RX_OVER interrupt (bit 1) of -// the IC_RAW_INTR_STAT register. -// -// Reset value: 0x0 -#define I2C_IC_CLR_RX_OVER_CLR_RX_OVER_RESET _u(0x0) -#define I2C_IC_CLR_RX_OVER_CLR_RX_OVER_BITS _u(0x00000001) -#define I2C_IC_CLR_RX_OVER_CLR_RX_OVER_MSB _u(0) -#define I2C_IC_CLR_RX_OVER_CLR_RX_OVER_LSB _u(0) -#define I2C_IC_CLR_RX_OVER_CLR_RX_OVER_ACCESS "RO" -// ============================================================================= -// Register : I2C_IC_CLR_TX_OVER -// Description : Clear TX_OVER Interrupt Register -#define I2C_IC_CLR_TX_OVER_OFFSET _u(0x0000004c) -#define I2C_IC_CLR_TX_OVER_BITS _u(0x00000001) -#define I2C_IC_CLR_TX_OVER_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_CLR_TX_OVER_CLR_TX_OVER -// Description : Read this register to clear the TX_OVER interrupt (bit 3) of -// the IC_RAW_INTR_STAT register. -// -// Reset value: 0x0 -#define I2C_IC_CLR_TX_OVER_CLR_TX_OVER_RESET _u(0x0) -#define I2C_IC_CLR_TX_OVER_CLR_TX_OVER_BITS _u(0x00000001) -#define I2C_IC_CLR_TX_OVER_CLR_TX_OVER_MSB _u(0) -#define I2C_IC_CLR_TX_OVER_CLR_TX_OVER_LSB _u(0) -#define I2C_IC_CLR_TX_OVER_CLR_TX_OVER_ACCESS "RO" -// ============================================================================= -// Register : I2C_IC_CLR_RD_REQ -// Description : Clear RD_REQ Interrupt Register -#define I2C_IC_CLR_RD_REQ_OFFSET _u(0x00000050) -#define I2C_IC_CLR_RD_REQ_BITS _u(0x00000001) -#define I2C_IC_CLR_RD_REQ_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_CLR_RD_REQ_CLR_RD_REQ -// Description : Read this register to clear the RD_REQ interrupt (bit 5) of the -// IC_RAW_INTR_STAT register. -// -// Reset value: 0x0 -#define I2C_IC_CLR_RD_REQ_CLR_RD_REQ_RESET _u(0x0) -#define I2C_IC_CLR_RD_REQ_CLR_RD_REQ_BITS _u(0x00000001) -#define I2C_IC_CLR_RD_REQ_CLR_RD_REQ_MSB _u(0) -#define I2C_IC_CLR_RD_REQ_CLR_RD_REQ_LSB _u(0) -#define I2C_IC_CLR_RD_REQ_CLR_RD_REQ_ACCESS "RO" -// ============================================================================= -// Register : I2C_IC_CLR_TX_ABRT -// Description : Clear TX_ABRT Interrupt Register -#define I2C_IC_CLR_TX_ABRT_OFFSET _u(0x00000054) -#define I2C_IC_CLR_TX_ABRT_BITS _u(0x00000001) -#define I2C_IC_CLR_TX_ABRT_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_CLR_TX_ABRT_CLR_TX_ABRT -// Description : Read this register to clear the TX_ABRT interrupt (bit 6) of -// the IC_RAW_INTR_STAT register, and the IC_TX_ABRT_SOURCE -// register. This also releases the TX FIFO from the flushed/reset -// state, allowing more writes to the TX FIFO. Refer to Bit 9 of -// the IC_TX_ABRT_SOURCE register for an exception to clearing -// IC_TX_ABRT_SOURCE. -// -// Reset value: 0x0 -#define I2C_IC_CLR_TX_ABRT_CLR_TX_ABRT_RESET _u(0x0) -#define I2C_IC_CLR_TX_ABRT_CLR_TX_ABRT_BITS _u(0x00000001) -#define I2C_IC_CLR_TX_ABRT_CLR_TX_ABRT_MSB _u(0) -#define I2C_IC_CLR_TX_ABRT_CLR_TX_ABRT_LSB _u(0) -#define I2C_IC_CLR_TX_ABRT_CLR_TX_ABRT_ACCESS "RO" -// ============================================================================= -// Register : I2C_IC_CLR_RX_DONE -// Description : Clear RX_DONE Interrupt Register -#define I2C_IC_CLR_RX_DONE_OFFSET _u(0x00000058) -#define I2C_IC_CLR_RX_DONE_BITS _u(0x00000001) -#define I2C_IC_CLR_RX_DONE_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_CLR_RX_DONE_CLR_RX_DONE -// Description : Read this register to clear the RX_DONE interrupt (bit 7) of -// the IC_RAW_INTR_STAT register. -// -// Reset value: 0x0 -#define I2C_IC_CLR_RX_DONE_CLR_RX_DONE_RESET _u(0x0) -#define I2C_IC_CLR_RX_DONE_CLR_RX_DONE_BITS _u(0x00000001) -#define I2C_IC_CLR_RX_DONE_CLR_RX_DONE_MSB _u(0) -#define I2C_IC_CLR_RX_DONE_CLR_RX_DONE_LSB _u(0) -#define I2C_IC_CLR_RX_DONE_CLR_RX_DONE_ACCESS "RO" -// ============================================================================= -// Register : I2C_IC_CLR_ACTIVITY -// Description : Clear ACTIVITY Interrupt Register -#define I2C_IC_CLR_ACTIVITY_OFFSET _u(0x0000005c) -#define I2C_IC_CLR_ACTIVITY_BITS _u(0x00000001) -#define I2C_IC_CLR_ACTIVITY_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_CLR_ACTIVITY_CLR_ACTIVITY -// Description : Reading this register clears the ACTIVITY interrupt if the I2C -// is not active anymore. If the I2C module is still active on the -// bus, the ACTIVITY interrupt bit continues to be set. It is -// automatically cleared by hardware if the module is disabled and -// if there is no further activity on the bus. The value read from -// this register to get status of the ACTIVITY interrupt (bit 8) -// of the IC_RAW_INTR_STAT register. -// -// Reset value: 0x0 -#define I2C_IC_CLR_ACTIVITY_CLR_ACTIVITY_RESET _u(0x0) -#define I2C_IC_CLR_ACTIVITY_CLR_ACTIVITY_BITS _u(0x00000001) -#define I2C_IC_CLR_ACTIVITY_CLR_ACTIVITY_MSB _u(0) -#define I2C_IC_CLR_ACTIVITY_CLR_ACTIVITY_LSB _u(0) -#define I2C_IC_CLR_ACTIVITY_CLR_ACTIVITY_ACCESS "RO" -// ============================================================================= -// Register : I2C_IC_CLR_STOP_DET -// Description : Clear STOP_DET Interrupt Register -#define I2C_IC_CLR_STOP_DET_OFFSET _u(0x00000060) -#define I2C_IC_CLR_STOP_DET_BITS _u(0x00000001) -#define I2C_IC_CLR_STOP_DET_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_CLR_STOP_DET_CLR_STOP_DET -// Description : Read this register to clear the STOP_DET interrupt (bit 9) of -// the IC_RAW_INTR_STAT register. -// -// Reset value: 0x0 -#define I2C_IC_CLR_STOP_DET_CLR_STOP_DET_RESET _u(0x0) -#define I2C_IC_CLR_STOP_DET_CLR_STOP_DET_BITS _u(0x00000001) -#define I2C_IC_CLR_STOP_DET_CLR_STOP_DET_MSB _u(0) -#define I2C_IC_CLR_STOP_DET_CLR_STOP_DET_LSB _u(0) -#define I2C_IC_CLR_STOP_DET_CLR_STOP_DET_ACCESS "RO" -// ============================================================================= -// Register : I2C_IC_CLR_START_DET -// Description : Clear START_DET Interrupt Register -#define I2C_IC_CLR_START_DET_OFFSET _u(0x00000064) -#define I2C_IC_CLR_START_DET_BITS _u(0x00000001) -#define I2C_IC_CLR_START_DET_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_CLR_START_DET_CLR_START_DET -// Description : Read this register to clear the START_DET interrupt (bit 10) of -// the IC_RAW_INTR_STAT register. -// -// Reset value: 0x0 -#define I2C_IC_CLR_START_DET_CLR_START_DET_RESET _u(0x0) -#define I2C_IC_CLR_START_DET_CLR_START_DET_BITS _u(0x00000001) -#define I2C_IC_CLR_START_DET_CLR_START_DET_MSB _u(0) -#define I2C_IC_CLR_START_DET_CLR_START_DET_LSB _u(0) -#define I2C_IC_CLR_START_DET_CLR_START_DET_ACCESS "RO" -// ============================================================================= -// Register : I2C_IC_CLR_GEN_CALL -// Description : Clear GEN_CALL Interrupt Register -#define I2C_IC_CLR_GEN_CALL_OFFSET _u(0x00000068) -#define I2C_IC_CLR_GEN_CALL_BITS _u(0x00000001) -#define I2C_IC_CLR_GEN_CALL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_CLR_GEN_CALL_CLR_GEN_CALL -// Description : Read this register to clear the GEN_CALL interrupt (bit 11) of -// IC_RAW_INTR_STAT register. -// -// Reset value: 0x0 -#define I2C_IC_CLR_GEN_CALL_CLR_GEN_CALL_RESET _u(0x0) -#define I2C_IC_CLR_GEN_CALL_CLR_GEN_CALL_BITS _u(0x00000001) -#define I2C_IC_CLR_GEN_CALL_CLR_GEN_CALL_MSB _u(0) -#define I2C_IC_CLR_GEN_CALL_CLR_GEN_CALL_LSB _u(0) -#define I2C_IC_CLR_GEN_CALL_CLR_GEN_CALL_ACCESS "RO" -// ============================================================================= -// Register : I2C_IC_ENABLE -// Description : I2C Enable Register -#define I2C_IC_ENABLE_OFFSET _u(0x0000006c) -#define I2C_IC_ENABLE_BITS _u(0x00000007) -#define I2C_IC_ENABLE_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_ENABLE_TX_CMD_BLOCK -// Description : In Master mode: - 1'b1: Blocks the transmission of data on I2C -// bus even if Tx FIFO has data to transmit. - 1'b0: The -// transmission of data starts on I2C bus automatically, as soon -// as the first data is available in the Tx FIFO. Note: To block -// the execution of Master commands, set the TX_CMD_BLOCK bit only -// when Tx FIFO is empty (IC_STATUS[2]==1) and Master is in Idle -// state (IC_STATUS[5] == 0). Any further commands put in the Tx -// FIFO are not executed until TX_CMD_BLOCK bit is unset. Reset -// value: IC_TX_CMD_BLOCK_DEFAULT -// 0x0 -> Tx Command execution not blocked -// 0x1 -> Tx Command execution blocked -#define I2C_IC_ENABLE_TX_CMD_BLOCK_RESET _u(0x0) -#define I2C_IC_ENABLE_TX_CMD_BLOCK_BITS _u(0x00000004) -#define I2C_IC_ENABLE_TX_CMD_BLOCK_MSB _u(2) -#define I2C_IC_ENABLE_TX_CMD_BLOCK_LSB _u(2) -#define I2C_IC_ENABLE_TX_CMD_BLOCK_ACCESS "RW" -#define I2C_IC_ENABLE_TX_CMD_BLOCK_VALUE_NOT_BLOCKED _u(0x0) -#define I2C_IC_ENABLE_TX_CMD_BLOCK_VALUE_BLOCKED _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_ENABLE_ABORT -// Description : When set, the controller initiates the transfer abort. - 0: -// ABORT not initiated or ABORT done - 1: ABORT operation in -// progress The software can abort the I2C transfer in master mode -// by setting this bit. The software can set this bit only when -// ENABLE is already set; otherwise, the controller ignores any -// write to ABORT bit. The software cannot clear the ABORT bit -// once set. In response to an ABORT, the controller issues a STOP -// and flushes the Tx FIFO after completing the current transfer, -// then sets the TX_ABORT interrupt after the abort operation. The -// ABORT bit is cleared automatically after the abort operation. -// -// For a detailed description on how to abort I2C transfers, refer -// to 'Aborting I2C Transfers'. -// -// Reset value: 0x0 -// 0x0 -> ABORT operation not in progress -// 0x1 -> ABORT operation in progress -#define I2C_IC_ENABLE_ABORT_RESET _u(0x0) -#define I2C_IC_ENABLE_ABORT_BITS _u(0x00000002) -#define I2C_IC_ENABLE_ABORT_MSB _u(1) -#define I2C_IC_ENABLE_ABORT_LSB _u(1) -#define I2C_IC_ENABLE_ABORT_ACCESS "RW" -#define I2C_IC_ENABLE_ABORT_VALUE_DISABLE _u(0x0) -#define I2C_IC_ENABLE_ABORT_VALUE_ENABLED _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_ENABLE_ENABLE -// Description : Controls whether the DW_apb_i2c is enabled. - 0: Disables -// DW_apb_i2c (TX and RX FIFOs are held in an erased state) - 1: -// Enables DW_apb_i2c Software can disable DW_apb_i2c while it is -// active. However, it is important that care be taken to ensure -// that DW_apb_i2c is disabled properly. A recommended procedure -// is described in 'Disabling DW_apb_i2c'. -// -// When DW_apb_i2c is disabled, the following occurs: - The TX -// FIFO and RX FIFO get flushed. - Status bits in the IC_INTR_STAT -// register are still active until DW_apb_i2c goes into IDLE -// state. If the module is transmitting, it stops as well as -// deletes the contents of the transmit buffer after the current -// transfer is complete. If the module is receiving, the -// DW_apb_i2c stops the current transfer at the end of the current -// byte and does not acknowledge the transfer. -// -// In systems with asynchronous pclk and ic_clk when IC_CLK_TYPE -// parameter set to asynchronous (1), there is a two ic_clk delay -// when enabling or disabling the DW_apb_i2c. For a detailed -// description on how to disable DW_apb_i2c, refer to 'Disabling -// DW_apb_i2c' -// -// Reset value: 0x0 -// 0x0 -> I2C is disabled -// 0x1 -> I2C is enabled -#define I2C_IC_ENABLE_ENABLE_RESET _u(0x0) -#define I2C_IC_ENABLE_ENABLE_BITS _u(0x00000001) -#define I2C_IC_ENABLE_ENABLE_MSB _u(0) -#define I2C_IC_ENABLE_ENABLE_LSB _u(0) -#define I2C_IC_ENABLE_ENABLE_ACCESS "RW" -#define I2C_IC_ENABLE_ENABLE_VALUE_DISABLED _u(0x0) -#define I2C_IC_ENABLE_ENABLE_VALUE_ENABLED _u(0x1) -// ============================================================================= -// Register : I2C_IC_STATUS -// Description : I2C Status Register -// -// This is a read-only register used to indicate the current -// transfer status and FIFO status. The status register may be -// read at any time. None of the bits in this register request an -// interrupt. -// -// When the I2C is disabled by writing 0 in bit 0 of the IC_ENABLE -// register: - Bits 1 and 2 are set to 1 - Bits 3 and 10 are set -// to 0 When the master or slave state machines goes to idle and -// ic_en=0: - Bits 5 and 6 are set to 0 -#define I2C_IC_STATUS_OFFSET _u(0x00000070) -#define I2C_IC_STATUS_BITS _u(0x0000007f) -#define I2C_IC_STATUS_RESET _u(0x00000006) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_STATUS_SLV_ACTIVITY -// Description : Slave FSM Activity Status. When the Slave Finite State Machine -// (FSM) is not in the IDLE state, this bit is set. - 0: Slave FSM -// is in IDLE state so the Slave part of DW_apb_i2c is not Active -// - 1: Slave FSM is not in IDLE state so the Slave part of -// DW_apb_i2c is Active Reset value: 0x0 -// 0x0 -> Slave is idle -// 0x1 -> Slave not idle -#define I2C_IC_STATUS_SLV_ACTIVITY_RESET _u(0x0) -#define I2C_IC_STATUS_SLV_ACTIVITY_BITS _u(0x00000040) -#define I2C_IC_STATUS_SLV_ACTIVITY_MSB _u(6) -#define I2C_IC_STATUS_SLV_ACTIVITY_LSB _u(6) -#define I2C_IC_STATUS_SLV_ACTIVITY_ACCESS "RO" -#define I2C_IC_STATUS_SLV_ACTIVITY_VALUE_IDLE _u(0x0) -#define I2C_IC_STATUS_SLV_ACTIVITY_VALUE_ACTIVE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_STATUS_MST_ACTIVITY -// Description : Master FSM Activity Status. When the Master Finite State -// Machine (FSM) is not in the IDLE state, this bit is set. - 0: -// Master FSM is in IDLE state so the Master part of DW_apb_i2c is -// not Active - 1: Master FSM is not in IDLE state so the Master -// part of DW_apb_i2c is Active Note: IC_STATUS[0]-that is, -// ACTIVITY bit-is the OR of SLV_ACTIVITY and MST_ACTIVITY bits. -// -// Reset value: 0x0 -// 0x0 -> Master is idle -// 0x1 -> Master not idle -#define I2C_IC_STATUS_MST_ACTIVITY_RESET _u(0x0) -#define I2C_IC_STATUS_MST_ACTIVITY_BITS _u(0x00000020) -#define I2C_IC_STATUS_MST_ACTIVITY_MSB _u(5) -#define I2C_IC_STATUS_MST_ACTIVITY_LSB _u(5) -#define I2C_IC_STATUS_MST_ACTIVITY_ACCESS "RO" -#define I2C_IC_STATUS_MST_ACTIVITY_VALUE_IDLE _u(0x0) -#define I2C_IC_STATUS_MST_ACTIVITY_VALUE_ACTIVE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_STATUS_RFF -// Description : Receive FIFO Completely Full. When the receive FIFO is -// completely full, this bit is set. When the receive FIFO -// contains one or more empty location, this bit is cleared. - 0: -// Receive FIFO is not full - 1: Receive FIFO is full Reset value: -// 0x0 -// 0x0 -> Rx FIFO not full -// 0x1 -> Rx FIFO is full -#define I2C_IC_STATUS_RFF_RESET _u(0x0) -#define I2C_IC_STATUS_RFF_BITS _u(0x00000010) -#define I2C_IC_STATUS_RFF_MSB _u(4) -#define I2C_IC_STATUS_RFF_LSB _u(4) -#define I2C_IC_STATUS_RFF_ACCESS "RO" -#define I2C_IC_STATUS_RFF_VALUE_NOT_FULL _u(0x0) -#define I2C_IC_STATUS_RFF_VALUE_FULL _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_STATUS_RFNE -// Description : Receive FIFO Not Empty. This bit is set when the receive FIFO -// contains one or more entries; it is cleared when the receive -// FIFO is empty. - 0: Receive FIFO is empty - 1: Receive FIFO is -// not empty Reset value: 0x0 -// 0x0 -> Rx FIFO is empty -// 0x1 -> Rx FIFO not empty -#define I2C_IC_STATUS_RFNE_RESET _u(0x0) -#define I2C_IC_STATUS_RFNE_BITS _u(0x00000008) -#define I2C_IC_STATUS_RFNE_MSB _u(3) -#define I2C_IC_STATUS_RFNE_LSB _u(3) -#define I2C_IC_STATUS_RFNE_ACCESS "RO" -#define I2C_IC_STATUS_RFNE_VALUE_EMPTY _u(0x0) -#define I2C_IC_STATUS_RFNE_VALUE_NOT_EMPTY _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_STATUS_TFE -// Description : Transmit FIFO Completely Empty. When the transmit FIFO is -// completely empty, this bit is set. When it contains one or more -// valid entries, this bit is cleared. This bit field does not -// request an interrupt. - 0: Transmit FIFO is not empty - 1: -// Transmit FIFO is empty Reset value: 0x1 -// 0x0 -> Tx FIFO not empty -// 0x1 -> Tx FIFO is empty -#define I2C_IC_STATUS_TFE_RESET _u(0x1) -#define I2C_IC_STATUS_TFE_BITS _u(0x00000004) -#define I2C_IC_STATUS_TFE_MSB _u(2) -#define I2C_IC_STATUS_TFE_LSB _u(2) -#define I2C_IC_STATUS_TFE_ACCESS "RO" -#define I2C_IC_STATUS_TFE_VALUE_NON_EMPTY _u(0x0) -#define I2C_IC_STATUS_TFE_VALUE_EMPTY _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_STATUS_TFNF -// Description : Transmit FIFO Not Full. Set when the transmit FIFO contains one -// or more empty locations, and is cleared when the FIFO is full. -// - 0: Transmit FIFO is full - 1: Transmit FIFO is not full Reset -// value: 0x1 -// 0x0 -> Tx FIFO is full -// 0x1 -> Tx FIFO not full -#define I2C_IC_STATUS_TFNF_RESET _u(0x1) -#define I2C_IC_STATUS_TFNF_BITS _u(0x00000002) -#define I2C_IC_STATUS_TFNF_MSB _u(1) -#define I2C_IC_STATUS_TFNF_LSB _u(1) -#define I2C_IC_STATUS_TFNF_ACCESS "RO" -#define I2C_IC_STATUS_TFNF_VALUE_FULL _u(0x0) -#define I2C_IC_STATUS_TFNF_VALUE_NOT_FULL _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_STATUS_ACTIVITY -// Description : I2C Activity Status. Reset value: 0x0 -// 0x0 -> I2C is idle -// 0x1 -> I2C is active -#define I2C_IC_STATUS_ACTIVITY_RESET _u(0x0) -#define I2C_IC_STATUS_ACTIVITY_BITS _u(0x00000001) -#define I2C_IC_STATUS_ACTIVITY_MSB _u(0) -#define I2C_IC_STATUS_ACTIVITY_LSB _u(0) -#define I2C_IC_STATUS_ACTIVITY_ACCESS "RO" -#define I2C_IC_STATUS_ACTIVITY_VALUE_INACTIVE _u(0x0) -#define I2C_IC_STATUS_ACTIVITY_VALUE_ACTIVE _u(0x1) -// ============================================================================= -// Register : I2C_IC_TXFLR -// Description : I2C Transmit FIFO Level Register This register contains the -// number of valid data entries in the transmit FIFO buffer. It is -// cleared whenever: - The I2C is disabled - There is a transmit -// abort - that is, TX_ABRT bit is set in the IC_RAW_INTR_STAT -// register - The slave bulk transmit mode is aborted The register -// increments whenever data is placed into the transmit FIFO and -// decrements when data is taken from the transmit FIFO. -#define I2C_IC_TXFLR_OFFSET _u(0x00000074) -#define I2C_IC_TXFLR_BITS _u(0x0000001f) -#define I2C_IC_TXFLR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_TXFLR_TXFLR -// Description : Transmit FIFO Level. Contains the number of valid data entries -// in the transmit FIFO. -// -// Reset value: 0x0 -#define I2C_IC_TXFLR_TXFLR_RESET _u(0x00) -#define I2C_IC_TXFLR_TXFLR_BITS _u(0x0000001f) -#define I2C_IC_TXFLR_TXFLR_MSB _u(4) -#define I2C_IC_TXFLR_TXFLR_LSB _u(0) -#define I2C_IC_TXFLR_TXFLR_ACCESS "RO" -// ============================================================================= -// Register : I2C_IC_RXFLR -// Description : I2C Receive FIFO Level Register This register contains the -// number of valid data entries in the receive FIFO buffer. It is -// cleared whenever: - The I2C is disabled - Whenever there is a -// transmit abort caused by any of the events tracked in -// IC_TX_ABRT_SOURCE The register increments whenever data is -// placed into the receive FIFO and decrements when data is taken -// from the receive FIFO. -#define I2C_IC_RXFLR_OFFSET _u(0x00000078) -#define I2C_IC_RXFLR_BITS _u(0x0000001f) -#define I2C_IC_RXFLR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_RXFLR_RXFLR -// Description : Receive FIFO Level. Contains the number of valid data entries -// in the receive FIFO. -// -// Reset value: 0x0 -#define I2C_IC_RXFLR_RXFLR_RESET _u(0x00) -#define I2C_IC_RXFLR_RXFLR_BITS _u(0x0000001f) -#define I2C_IC_RXFLR_RXFLR_MSB _u(4) -#define I2C_IC_RXFLR_RXFLR_LSB _u(0) -#define I2C_IC_RXFLR_RXFLR_ACCESS "RO" -// ============================================================================= -// Register : I2C_IC_SDA_HOLD -// Description : I2C SDA Hold Time Length Register -// -// The bits [15:0] of this register are used to control the hold -// time of SDA during transmit in both slave and master mode -// (after SCL goes from HIGH to LOW). -// -// The bits [23:16] of this register are used to extend the SDA -// transition (if any) whenever SCL is HIGH in the receiver in -// either master or slave mode. -// -// Writes to this register succeed only when IC_ENABLE[0]=0. -// -// The values in this register are in units of ic_clk period. The -// value programmed in IC_SDA_TX_HOLD must be greater than the -// minimum hold time in each mode (one cycle in master mode, seven -// cycles in slave mode) for the value to be implemented. -// -// The programmed SDA hold time during transmit (IC_SDA_TX_HOLD) -// cannot exceed at any time the duration of the low part of scl. -// Therefore the programmed value cannot be larger than -// N_SCL_LOW-2, where N_SCL_LOW is the duration of the low part of -// the scl period measured in ic_clk cycles. -#define I2C_IC_SDA_HOLD_OFFSET _u(0x0000007c) -#define I2C_IC_SDA_HOLD_BITS _u(0x00ffffff) -#define I2C_IC_SDA_HOLD_RESET _u(0x00000001) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_SDA_HOLD_IC_SDA_RX_HOLD -// Description : Sets the required SDA hold time in units of ic_clk period, when -// DW_apb_i2c acts as a receiver. -// -// Reset value: IC_DEFAULT_SDA_HOLD[23:16]. -#define I2C_IC_SDA_HOLD_IC_SDA_RX_HOLD_RESET _u(0x00) -#define I2C_IC_SDA_HOLD_IC_SDA_RX_HOLD_BITS _u(0x00ff0000) -#define I2C_IC_SDA_HOLD_IC_SDA_RX_HOLD_MSB _u(23) -#define I2C_IC_SDA_HOLD_IC_SDA_RX_HOLD_LSB _u(16) -#define I2C_IC_SDA_HOLD_IC_SDA_RX_HOLD_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : I2C_IC_SDA_HOLD_IC_SDA_TX_HOLD -// Description : Sets the required SDA hold time in units of ic_clk period, when -// DW_apb_i2c acts as a transmitter. -// -// Reset value: IC_DEFAULT_SDA_HOLD[15:0]. -#define I2C_IC_SDA_HOLD_IC_SDA_TX_HOLD_RESET _u(0x0001) -#define I2C_IC_SDA_HOLD_IC_SDA_TX_HOLD_BITS _u(0x0000ffff) -#define I2C_IC_SDA_HOLD_IC_SDA_TX_HOLD_MSB _u(15) -#define I2C_IC_SDA_HOLD_IC_SDA_TX_HOLD_LSB _u(0) -#define I2C_IC_SDA_HOLD_IC_SDA_TX_HOLD_ACCESS "RW" -// ============================================================================= -// Register : I2C_IC_TX_ABRT_SOURCE -// Description : I2C Transmit Abort Source Register -// -// This register has 32 bits that indicate the source of the -// TX_ABRT bit. Except for Bit 9, this register is cleared -// whenever the IC_CLR_TX_ABRT register or the IC_CLR_INTR -// register is read. To clear Bit 9, the source of the -// ABRT_SBYTE_NORSTRT must be fixed first; RESTART must be enabled -// (IC_CON[5]=1), the SPECIAL bit must be cleared (IC_TAR[11]), or -// the GC_OR_START bit must be cleared (IC_TAR[10]). -// -// Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this -// bit can be cleared in the same manner as other bits in this -// register. If the source of the ABRT_SBYTE_NORSTRT is not fixed -// before attempting to clear this bit, Bit 9 clears for one cycle -// and is then re-asserted. -#define I2C_IC_TX_ABRT_SOURCE_OFFSET _u(0x00000080) -#define I2C_IC_TX_ABRT_SOURCE_BITS _u(0xff81ffff) -#define I2C_IC_TX_ABRT_SOURCE_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_TX_ABRT_SOURCE_TX_FLUSH_CNT -// Description : This field indicates the number of Tx FIFO Data Commands which -// are flushed due to TX_ABRT interrupt. It is cleared whenever -// I2C is disabled. -// -// Reset value: 0x0 -// -// Role of DW_apb_i2c: Master-Transmitter or Slave-Transmitter -#define I2C_IC_TX_ABRT_SOURCE_TX_FLUSH_CNT_RESET _u(0x000) -#define I2C_IC_TX_ABRT_SOURCE_TX_FLUSH_CNT_BITS _u(0xff800000) -#define I2C_IC_TX_ABRT_SOURCE_TX_FLUSH_CNT_MSB _u(31) -#define I2C_IC_TX_ABRT_SOURCE_TX_FLUSH_CNT_LSB _u(23) -#define I2C_IC_TX_ABRT_SOURCE_TX_FLUSH_CNT_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT -// Description : This is a master-mode-only bit. Master has detected the -// transfer abort (IC_ENABLE[1]) -// -// Reset value: 0x0 -// -// Role of DW_apb_i2c: Master-Transmitter -// 0x0 -> Transfer abort detected by master- scenario not present -// 0x1 -> Transfer abort detected by master -#define I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_RESET _u(0x0) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_BITS _u(0x00010000) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_MSB _u(16) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_LSB _u(16) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_ACCESS "RO" -#define I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_VALUE_ABRT_USER_ABRT_VOID _u(0x0) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_VALUE_ABRT_USER_ABRT_GENERATED _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX -// Description : 1: When the processor side responds to a slave mode request for -// data to be transmitted to a remote master and user writes a 1 -// in CMD (bit 8) of IC_DATA_CMD register. -// -// Reset value: 0x0 -// -// Role of DW_apb_i2c: Slave-Transmitter -// 0x0 -> Slave trying to transmit to remote master in read mode- scenario not present -// 0x1 -> Slave trying to transmit to remote master in read mode -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_RESET _u(0x0) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_BITS _u(0x00008000) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_MSB _u(15) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_LSB _u(15) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_ACCESS "RO" -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_VALUE_ABRT_SLVRD_INTX_VOID _u(0x0) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_VALUE_ABRT_SLVRD_INTX_GENERATED _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST -// Description : This field indicates that a Slave has lost the bus while -// transmitting data to a remote master. IC_TX_ABRT_SOURCE[12] is -// set at the same time. Note: Even though the slave never 'owns' -// the bus, something could go wrong on the bus. This is a fail -// safe check. For instance, during a data transmission at the -// low-to-high transition of SCL, if what is on the data bus is -// not what is supposed to be transmitted, then DW_apb_i2c no -// longer own the bus. -// -// Reset value: 0x0 -// -// Role of DW_apb_i2c: Slave-Transmitter -// 0x0 -> Slave lost arbitration to remote master- scenario not present -// 0x1 -> Slave lost arbitration to remote master -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_RESET _u(0x0) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_BITS _u(0x00004000) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_MSB _u(14) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_LSB _u(14) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_ACCESS "RO" -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_VALUE_ABRT_SLV_ARBLOST_VOID _u(0x0) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_VALUE_ABRT_SLV_ARBLOST_GENERATED _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO -// Description : This field specifies that the Slave has received a read command -// and some data exists in the TX FIFO, so the slave issues a -// TX_ABRT interrupt to flush old data in TX FIFO. -// -// Reset value: 0x0 -// -// Role of DW_apb_i2c: Slave-Transmitter -// 0x0 -> Slave flushes existing data in TX-FIFO upon getting read command- scenario not present -// 0x1 -> Slave flushes existing data in TX-FIFO upon getting read command -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_RESET _u(0x0) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_BITS _u(0x00002000) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_MSB _u(13) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_LSB _u(13) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_ACCESS "RO" -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_VALUE_ABRT_SLVFLUSH_TXFIFO_VOID _u(0x0) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_VALUE_ABRT_SLVFLUSH_TXFIFO_GENERATED _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_TX_ABRT_SOURCE_ARB_LOST -// Description : This field specifies that the Master has lost arbitration, or -// if IC_TX_ABRT_SOURCE[14] is also set, then the slave -// transmitter has lost arbitration. -// -// Reset value: 0x0 -// -// Role of DW_apb_i2c: Master-Transmitter or Slave-Transmitter -// 0x0 -> Master or Slave-Transmitter lost arbitration- scenario not present -// 0x1 -> Master or Slave-Transmitter lost arbitration -#define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_RESET _u(0x0) -#define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_BITS _u(0x00001000) -#define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_MSB _u(12) -#define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_LSB _u(12) -#define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_ACCESS "RO" -#define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_VALUE_ABRT_LOST_VOID _u(0x0) -#define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_VALUE_ABRT_LOST_GENERATED _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS -// Description : This field indicates that the User tries to initiate a Master -// operation with the Master mode disabled. -// -// Reset value: 0x0 -// -// Role of DW_apb_i2c: Master-Transmitter or Master-Receiver -// 0x0 -> User initiating master operation when MASTER disabled- scenario not present -// 0x1 -> User initiating master operation when MASTER disabled -#define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_RESET _u(0x0) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_BITS _u(0x00000800) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_MSB _u(11) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_LSB _u(11) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_ACCESS "RO" -#define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_VALUE_ABRT_MASTER_DIS_VOID _u(0x0) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_VALUE_ABRT_MASTER_DIS_GENERATED _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT -// Description : This field indicates that the restart is disabled -// (IC_RESTART_EN bit (IC_CON[5]) =0) and the master sends a read -// command in 10-bit addressing mode. -// -// Reset value: 0x0 -// -// Role of DW_apb_i2c: Master-Receiver -// 0x0 -> Master not trying to read in 10Bit addressing mode when RESTART disabled -// 0x1 -> Master trying to read in 10Bit addressing mode when RESTART disabled -#define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_RESET _u(0x0) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_BITS _u(0x00000400) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_MSB _u(10) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_LSB _u(10) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_ACCESS "RO" -#define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_VALUE_ABRT_10B_RD_VOID _u(0x0) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_VALUE_ABRT_10B_RD_GENERATED _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT -// Description : To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be -// fixed first; restart must be enabled (IC_CON[5]=1), the SPECIAL -// bit must be cleared (IC_TAR[11]), or the GC_OR_START bit must -// be cleared (IC_TAR[10]). Once the source of the -// ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in -// the same manner as other bits in this register. If the source -// of the ABRT_SBYTE_NORSTRT is not fixed before attempting to -// clear this bit, bit 9 clears for one cycle and then gets -// reasserted. When this field is set to 1, the restart is -// disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the user is -// trying to send a START Byte. -// -// Reset value: 0x0 -// -// Role of DW_apb_i2c: Master -// 0x0 -> User trying to send START byte when RESTART disabled- scenario not present -// 0x1 -> User trying to send START byte when RESTART disabled -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_RESET _u(0x0) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_BITS _u(0x00000200) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_MSB _u(9) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_LSB _u(9) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_ACCESS "RO" -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_VALUE_ABRT_SBYTE_NORSTRT_VOID _u(0x0) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_VALUE_ABRT_SBYTE_NORSTRT_GENERATED _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT -// Description : This field indicates that the restart is disabled -// (IC_RESTART_EN bit (IC_CON[5]) =0) and the user is trying to -// use the master to transfer data in High Speed mode. -// -// Reset value: 0x0 -// -// Role of DW_apb_i2c: Master-Transmitter or Master-Receiver -// 0x0 -> User trying to switch Master to HS mode when RESTART disabled- scenario not present -// 0x1 -> User trying to switch Master to HS mode when RESTART disabled -#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_RESET _u(0x0) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_BITS _u(0x00000100) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_MSB _u(8) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_LSB _u(8) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_ACCESS "RO" -#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_VALUE_ABRT_HS_NORSTRT_VOID _u(0x0) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_VALUE_ABRT_HS_NORSTRT_GENERATED _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET -// Description : This field indicates that the Master has sent a START Byte and -// the START Byte was acknowledged (wrong behavior). -// -// Reset value: 0x0 -// -// Role of DW_apb_i2c: Master -// 0x0 -> ACK detected for START byte- scenario not present -// 0x1 -> ACK detected for START byte -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_RESET _u(0x0) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_BITS _u(0x00000080) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_MSB _u(7) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_LSB _u(7) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_ACCESS "RO" -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_VALUE_ABRT_SBYTE_ACKDET_VOID _u(0x0) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_VALUE_ABRT_SBYTE_ACKDET_GENERATED _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET -// Description : This field indicates that the Master is in High Speed mode and -// the High Speed Master code was acknowledged (wrong behavior). -// -// Reset value: 0x0 -// -// Role of DW_apb_i2c: Master -// 0x0 -> HS Master code ACKed in HS Mode- scenario not present -// 0x1 -> HS Master code ACKed in HS Mode -#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_RESET _u(0x0) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_BITS _u(0x00000040) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_MSB _u(6) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_LSB _u(6) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_ACCESS "RO" -#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_VALUE_ABRT_HS_ACK_VOID _u(0x0) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_VALUE_ABRT_HS_ACK_GENERATED _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ -// Description : This field indicates that DW_apb_i2c in the master mode has -// sent a General Call but the user programmed the byte following -// the General Call to be a read from the bus (IC_DATA_CMD[9] is -// set to 1). -// -// Reset value: 0x0 -// -// Role of DW_apb_i2c: Master-Transmitter -// 0x0 -> GCALL is followed by read from bus-scenario not present -// 0x1 -> GCALL is followed by read from bus -#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_RESET _u(0x0) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_BITS _u(0x00000020) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_MSB _u(5) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_LSB _u(5) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_ACCESS "RO" -#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_VALUE_ABRT_GCALL_READ_VOID _u(0x0) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_VALUE_ABRT_GCALL_READ_GENERATED _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK -// Description : This field indicates that DW_apb_i2c in master mode has sent a -// General Call and no slave on the bus acknowledged the General -// Call. -// -// Reset value: 0x0 -// -// Role of DW_apb_i2c: Master-Transmitter -// 0x0 -> GCALL not ACKed by any slave-scenario not present -// 0x1 -> GCALL not ACKed by any slave -#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_RESET _u(0x0) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_BITS _u(0x00000010) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_MSB _u(4) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_LSB _u(4) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_ACCESS "RO" -#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_VALUE_ABRT_GCALL_NOACK_VOID _u(0x0) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_VALUE_ABRT_GCALL_NOACK_GENERATED _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK -// Description : This field indicates the master-mode only bit. When the master -// receives an acknowledgement for the address, but when it sends -// data byte(s) following the address, it did not receive an -// acknowledge from the remote slave(s). -// -// Reset value: 0x0 -// -// Role of DW_apb_i2c: Master-Transmitter -// 0x0 -> Transmitted data non-ACKed by addressed slave-scenario not present -// 0x1 -> Transmitted data not ACKed by addressed slave -#define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_RESET _u(0x0) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_BITS _u(0x00000008) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_MSB _u(3) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_LSB _u(3) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_ACCESS "RO" -#define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_VALUE_ABRT_TXDATA_NOACK_VOID _u(0x0) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_VALUE_ABRT_TXDATA_NOACK_GENERATED _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK -// Description : This field indicates that the Master is in 10-bit address mode -// and that the second address byte of the 10-bit address was not -// acknowledged by any slave. -// -// Reset value: 0x0 -// -// Role of DW_apb_i2c: Master-Transmitter or Master-Receiver -// 0x0 -> This abort is not generated -// 0x1 -> Byte 2 of 10Bit Address not ACKed by any slave -#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_RESET _u(0x0) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_BITS _u(0x00000004) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_MSB _u(2) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_LSB _u(2) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_ACCESS "RO" -#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_VALUE_INACTIVE _u(0x0) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_VALUE_ACTIVE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK -// Description : This field indicates that the Master is in 10-bit address mode -// and the first 10-bit address byte was not acknowledged by any -// slave. -// -// Reset value: 0x0 -// -// Role of DW_apb_i2c: Master-Transmitter or Master-Receiver -// 0x0 -> This abort is not generated -// 0x1 -> Byte 1 of 10Bit Address not ACKed by any slave -#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_RESET _u(0x0) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_BITS _u(0x00000002) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_MSB _u(1) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_LSB _u(1) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_ACCESS "RO" -#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_VALUE_INACTIVE _u(0x0) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_VALUE_ACTIVE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK -// Description : This field indicates that the Master is in 7-bit addressing -// mode and the address sent was not acknowledged by any slave. -// -// Reset value: 0x0 -// -// Role of DW_apb_i2c: Master-Transmitter or Master-Receiver -// 0x0 -> This abort is not generated -// 0x1 -> This abort is generated because of NOACK for 7-bit address -#define I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_RESET _u(0x0) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_BITS _u(0x00000001) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_MSB _u(0) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_LSB _u(0) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_ACCESS "RO" -#define I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_VALUE_INACTIVE _u(0x0) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_VALUE_ACTIVE _u(0x1) -// ============================================================================= -// Register : I2C_IC_SLV_DATA_NACK_ONLY -// Description : Generate Slave Data NACK Register -// -// The register is used to generate a NACK for the data part of a -// transfer when DW_apb_i2c is acting as a slave-receiver. This -// register only exists when the IC_SLV_DATA_NACK_ONLY parameter -// is set to 1. When this parameter disabled, this register does -// not exist and writing to the register's address has no effect. -// -// A write can occur on this register if both of the following -// conditions are met: - DW_apb_i2c is disabled (IC_ENABLE[0] = 0) -// - Slave part is inactive (IC_STATUS[6] = 0) Note: The -// IC_STATUS[6] is a register read-back location for the internal -// slv_activity signal; the user should poll this before writing -// the ic_slv_data_nack_only bit. -#define I2C_IC_SLV_DATA_NACK_ONLY_OFFSET _u(0x00000084) -#define I2C_IC_SLV_DATA_NACK_ONLY_BITS _u(0x00000001) -#define I2C_IC_SLV_DATA_NACK_ONLY_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_SLV_DATA_NACK_ONLY_NACK -// Description : Generate NACK. This NACK generation only occurs when DW_apb_i2c -// is a slave-receiver. If this register is set to a value of 1, -// it can only generate a NACK after a data byte is received; -// hence, the data transfer is aborted and the data received is -// not pushed to the receive buffer. -// -// When the register is set to a value of 0, it generates -// NACK/ACK, depending on normal criteria. - 1: generate NACK -// after data byte received - 0: generate NACK/ACK normally Reset -// value: 0x0 -// 0x0 -> Slave receiver generates NACK normally -// 0x1 -> Slave receiver generates NACK upon data reception only -#define I2C_IC_SLV_DATA_NACK_ONLY_NACK_RESET _u(0x0) -#define I2C_IC_SLV_DATA_NACK_ONLY_NACK_BITS _u(0x00000001) -#define I2C_IC_SLV_DATA_NACK_ONLY_NACK_MSB _u(0) -#define I2C_IC_SLV_DATA_NACK_ONLY_NACK_LSB _u(0) -#define I2C_IC_SLV_DATA_NACK_ONLY_NACK_ACCESS "RW" -#define I2C_IC_SLV_DATA_NACK_ONLY_NACK_VALUE_DISABLED _u(0x0) -#define I2C_IC_SLV_DATA_NACK_ONLY_NACK_VALUE_ENABLED _u(0x1) -// ============================================================================= -// Register : I2C_IC_DMA_CR -// Description : DMA Control Register -// -// The register is used to enable the DMA Controller interface -// operation. There is a separate bit for transmit and receive. -// This can be programmed regardless of the state of IC_ENABLE. -#define I2C_IC_DMA_CR_OFFSET _u(0x00000088) -#define I2C_IC_DMA_CR_BITS _u(0x00000003) -#define I2C_IC_DMA_CR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_DMA_CR_TDMAE -// Description : Transmit DMA Enable. This bit enables/disables the transmit -// FIFO DMA channel. Reset value: 0x0 -// 0x0 -> transmit FIFO DMA channel disabled -// 0x1 -> Transmit FIFO DMA channel enabled -#define I2C_IC_DMA_CR_TDMAE_RESET _u(0x0) -#define I2C_IC_DMA_CR_TDMAE_BITS _u(0x00000002) -#define I2C_IC_DMA_CR_TDMAE_MSB _u(1) -#define I2C_IC_DMA_CR_TDMAE_LSB _u(1) -#define I2C_IC_DMA_CR_TDMAE_ACCESS "RW" -#define I2C_IC_DMA_CR_TDMAE_VALUE_DISABLED _u(0x0) -#define I2C_IC_DMA_CR_TDMAE_VALUE_ENABLED _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_DMA_CR_RDMAE -// Description : Receive DMA Enable. This bit enables/disables the receive FIFO -// DMA channel. Reset value: 0x0 -// 0x0 -> Receive FIFO DMA channel disabled -// 0x1 -> Receive FIFO DMA channel enabled -#define I2C_IC_DMA_CR_RDMAE_RESET _u(0x0) -#define I2C_IC_DMA_CR_RDMAE_BITS _u(0x00000001) -#define I2C_IC_DMA_CR_RDMAE_MSB _u(0) -#define I2C_IC_DMA_CR_RDMAE_LSB _u(0) -#define I2C_IC_DMA_CR_RDMAE_ACCESS "RW" -#define I2C_IC_DMA_CR_RDMAE_VALUE_DISABLED _u(0x0) -#define I2C_IC_DMA_CR_RDMAE_VALUE_ENABLED _u(0x1) -// ============================================================================= -// Register : I2C_IC_DMA_TDLR -// Description : DMA Transmit Data Level Register -#define I2C_IC_DMA_TDLR_OFFSET _u(0x0000008c) -#define I2C_IC_DMA_TDLR_BITS _u(0x0000000f) -#define I2C_IC_DMA_TDLR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_DMA_TDLR_DMATDL -// Description : Transmit Data Level. This bit field controls the level at which -// a DMA request is made by the transmit logic. It is equal to the -// watermark level; that is, the dma_tx_req signal is generated -// when the number of valid data entries in the transmit FIFO is -// equal to or below this field value, and TDMAE = 1. -// -// Reset value: 0x0 -#define I2C_IC_DMA_TDLR_DMATDL_RESET _u(0x0) -#define I2C_IC_DMA_TDLR_DMATDL_BITS _u(0x0000000f) -#define I2C_IC_DMA_TDLR_DMATDL_MSB _u(3) -#define I2C_IC_DMA_TDLR_DMATDL_LSB _u(0) -#define I2C_IC_DMA_TDLR_DMATDL_ACCESS "RW" -// ============================================================================= -// Register : I2C_IC_DMA_RDLR -// Description : I2C Receive Data Level Register -#define I2C_IC_DMA_RDLR_OFFSET _u(0x00000090) -#define I2C_IC_DMA_RDLR_BITS _u(0x0000000f) -#define I2C_IC_DMA_RDLR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_DMA_RDLR_DMARDL -// Description : Receive Data Level. This bit field controls the level at which -// a DMA request is made by the receive logic. The watermark level -// = DMARDL+1; that is, dma_rx_req is generated when the number of -// valid data entries in the receive FIFO is equal to or more than -// this field value + 1, and RDMAE =1. For instance, when DMARDL -// is 0, then dma_rx_req is asserted when 1 or more data entries -// are present in the receive FIFO. -// -// Reset value: 0x0 -#define I2C_IC_DMA_RDLR_DMARDL_RESET _u(0x0) -#define I2C_IC_DMA_RDLR_DMARDL_BITS _u(0x0000000f) -#define I2C_IC_DMA_RDLR_DMARDL_MSB _u(3) -#define I2C_IC_DMA_RDLR_DMARDL_LSB _u(0) -#define I2C_IC_DMA_RDLR_DMARDL_ACCESS "RW" -// ============================================================================= -// Register : I2C_IC_SDA_SETUP -// Description : I2C SDA Setup Register -// -// This register controls the amount of time delay (in terms of -// number of ic_clk clock periods) introduced in the rising edge -// of SCL - relative to SDA changing - when DW_apb_i2c services a -// read request in a slave-transmitter operation. The relevant I2C -// requirement is tSU:DAT (note 4) as detailed in the I2C Bus -// Specification. This register must be programmed with a value -// equal to or greater than 2. -// -// Writes to this register succeed only when IC_ENABLE[0] = 0. -// -// Note: The length of setup time is calculated using -// [(IC_SDA_SETUP - 1) * (ic_clk_period)], so if the user requires -// 10 ic_clk periods of setup time, they should program a value of -// 11. The IC_SDA_SETUP register is only used by the DW_apb_i2c -// when operating as a slave transmitter. -#define I2C_IC_SDA_SETUP_OFFSET _u(0x00000094) -#define I2C_IC_SDA_SETUP_BITS _u(0x000000ff) -#define I2C_IC_SDA_SETUP_RESET _u(0x00000064) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_SDA_SETUP_SDA_SETUP -// Description : SDA Setup. It is recommended that if the required delay is -// 1000ns, then for an ic_clk frequency of 10 MHz, IC_SDA_SETUP -// should be programmed to a value of 11. IC_SDA_SETUP must be -// programmed with a minimum value of 2. -#define I2C_IC_SDA_SETUP_SDA_SETUP_RESET _u(0x64) -#define I2C_IC_SDA_SETUP_SDA_SETUP_BITS _u(0x000000ff) -#define I2C_IC_SDA_SETUP_SDA_SETUP_MSB _u(7) -#define I2C_IC_SDA_SETUP_SDA_SETUP_LSB _u(0) -#define I2C_IC_SDA_SETUP_SDA_SETUP_ACCESS "RW" -// ============================================================================= -// Register : I2C_IC_ACK_GENERAL_CALL -// Description : I2C ACK General Call Register -// -// The register controls whether DW_apb_i2c responds with a ACK or -// NACK when it receives an I2C General Call address. -// -// This register is applicable only when the DW_apb_i2c is in -// slave mode. -#define I2C_IC_ACK_GENERAL_CALL_OFFSET _u(0x00000098) -#define I2C_IC_ACK_GENERAL_CALL_BITS _u(0x00000001) -#define I2C_IC_ACK_GENERAL_CALL_RESET _u(0x00000001) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL -// Description : ACK General Call. When set to 1, DW_apb_i2c responds with a ACK -// (by asserting ic_data_oe) when it receives a General Call. -// Otherwise, DW_apb_i2c responds with a NACK (by negating -// ic_data_oe). -// 0x0 -> Generate NACK for a General Call -// 0x1 -> Generate ACK for a General Call -#define I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_RESET _u(0x1) -#define I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_BITS _u(0x00000001) -#define I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_MSB _u(0) -#define I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_LSB _u(0) -#define I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_ACCESS "RW" -#define I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_VALUE_DISABLED _u(0x0) -#define I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_VALUE_ENABLED _u(0x1) -// ============================================================================= -// Register : I2C_IC_ENABLE_STATUS -// Description : I2C Enable Status Register -// -// The register is used to report the DW_apb_i2c hardware status -// when the IC_ENABLE[0] register is set from 1 to 0; that is, -// when DW_apb_i2c is disabled. -// -// If IC_ENABLE[0] has been set to 1, bits 2:1 are forced to 0, -// and bit 0 is forced to 1. -// -// If IC_ENABLE[0] has been set to 0, bits 2:1 is only be valid as -// soon as bit 0 is read as '0'. -// -// Note: When IC_ENABLE[0] has been set to 0, a delay occurs for -// bit 0 to be read as 0 because disabling the DW_apb_i2c depends -// on I2C bus activities. -#define I2C_IC_ENABLE_STATUS_OFFSET _u(0x0000009c) -#define I2C_IC_ENABLE_STATUS_BITS _u(0x00000007) -#define I2C_IC_ENABLE_STATUS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST -// Description : Slave Received Data Lost. This bit indicates if a Slave- -// Receiver operation has been aborted with at least one data byte -// received from an I2C transfer due to the setting bit 0 of -// IC_ENABLE from 1 to 0. When read as 1, DW_apb_i2c is deemed to -// have been actively engaged in an aborted I2C transfer (with -// matching address) and the data phase of the I2C transfer has -// been entered, even though a data byte has been responded with a -// NACK. -// -// Note: If the remote I2C master terminates the transfer with a -// STOP condition before the DW_apb_i2c has a chance to NACK a -// transfer, and IC_ENABLE[0] has been set to 0, then this bit is -// also set to 1. -// -// When read as 0, DW_apb_i2c is deemed to have been disabled -// without being actively involved in the data phase of a Slave- -// Receiver transfer. -// -// Note: The CPU can safely read this bit when IC_EN (bit 0) is -// read as 0. -// -// Reset value: 0x0 -// 0x0 -> Slave RX Data is not lost -// 0x1 -> Slave RX Data is lost -#define I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_RESET _u(0x0) -#define I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_BITS _u(0x00000004) -#define I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_MSB _u(2) -#define I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_LSB _u(2) -#define I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_ACCESS "RO" -#define I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_VALUE_INACTIVE _u(0x0) -#define I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_VALUE_ACTIVE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY -// Description : Slave Disabled While Busy (Transmit, Receive). This bit -// indicates if a potential or active Slave operation has been -// aborted due to the setting bit 0 of the IC_ENABLE register from -// 1 to 0. This bit is set when the CPU writes a 0 to the -// IC_ENABLE register while: -// -// (a) DW_apb_i2c is receiving the address byte of the Slave- -// Transmitter operation from a remote master; -// -// OR, -// -// (b) address and data bytes of the Slave-Receiver operation from -// a remote master. -// -// When read as 1, DW_apb_i2c is deemed to have forced a NACK -// during any part of an I2C transfer, irrespective of whether the -// I2C address matches the slave address set in DW_apb_i2c (IC_SAR -// register) OR if the transfer is completed before IC_ENABLE is -// set to 0 but has not taken effect. -// -// Note: If the remote I2C master terminates the transfer with a -// STOP condition before the DW_apb_i2c has a chance to NACK a -// transfer, and IC_ENABLE[0] has been set to 0, then this bit -// will also be set to 1. -// -// When read as 0, DW_apb_i2c is deemed to have been disabled when -// there is master activity, or when the I2C bus is idle. -// -// Note: The CPU can safely read this bit when IC_EN (bit 0) is -// read as 0. -// -// Reset value: 0x0 -// 0x0 -> Slave is disabled when it is idle -// 0x1 -> Slave is disabled when it is active -#define I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_RESET _u(0x0) -#define I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_BITS _u(0x00000002) -#define I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_MSB _u(1) -#define I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_LSB _u(1) -#define I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_ACCESS "RO" -#define I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_VALUE_INACTIVE _u(0x0) -#define I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_VALUE_ACTIVE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_ENABLE_STATUS_IC_EN -// Description : ic_en Status. This bit always reflects the value driven on the -// output port ic_en. - When read as 1, DW_apb_i2c is deemed to be -// in an enabled state. - When read as 0, DW_apb_i2c is deemed -// completely inactive. Note: The CPU can safely read this bit -// anytime. When this bit is read as 0, the CPU can safely read -// SLV_RX_DATA_LOST (bit 2) and SLV_DISABLED_WHILE_BUSY (bit 1). -// -// Reset value: 0x0 -// 0x0 -> I2C disabled -// 0x1 -> I2C enabled -#define I2C_IC_ENABLE_STATUS_IC_EN_RESET _u(0x0) -#define I2C_IC_ENABLE_STATUS_IC_EN_BITS _u(0x00000001) -#define I2C_IC_ENABLE_STATUS_IC_EN_MSB _u(0) -#define I2C_IC_ENABLE_STATUS_IC_EN_LSB _u(0) -#define I2C_IC_ENABLE_STATUS_IC_EN_ACCESS "RO" -#define I2C_IC_ENABLE_STATUS_IC_EN_VALUE_DISABLED _u(0x0) -#define I2C_IC_ENABLE_STATUS_IC_EN_VALUE_ENABLED _u(0x1) -// ============================================================================= -// Register : I2C_IC_FS_SPKLEN -// Description : I2C SS, FS or FM+ spike suppression limit -// -// This register is used to store the duration, measured in ic_clk -// cycles, of the longest spike that is filtered out by the spike -// suppression logic when the component is operating in SS, FS or -// FM+ modes. The relevant I2C requirement is tSP (table 4) as -// detailed in the I2C Bus Specification. This register must be -// programmed with a minimum value of 1. -#define I2C_IC_FS_SPKLEN_OFFSET _u(0x000000a0) -#define I2C_IC_FS_SPKLEN_BITS _u(0x000000ff) -#define I2C_IC_FS_SPKLEN_RESET _u(0x00000007) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_FS_SPKLEN_IC_FS_SPKLEN -// Description : This register must be set before any I2C bus transaction can -// take place to ensure stable operation. This register sets the -// duration, measured in ic_clk cycles, of the longest spike in -// the SCL or SDA lines that will be filtered out by the spike -// suppression logic. This register can be written only when the -// I2C interface is disabled which corresponds to the IC_ENABLE[0] -// register being set to 0. Writes at other times have no effect. -// The minimum valid value is 1; hardware prevents values less -// than this being written, and if attempted results in 1 being -// set. or more information, refer to 'Spike Suppression'. -#define I2C_IC_FS_SPKLEN_IC_FS_SPKLEN_RESET _u(0x07) -#define I2C_IC_FS_SPKLEN_IC_FS_SPKLEN_BITS _u(0x000000ff) -#define I2C_IC_FS_SPKLEN_IC_FS_SPKLEN_MSB _u(7) -#define I2C_IC_FS_SPKLEN_IC_FS_SPKLEN_LSB _u(0) -#define I2C_IC_FS_SPKLEN_IC_FS_SPKLEN_ACCESS "RW" -// ============================================================================= -// Register : I2C_IC_CLR_RESTART_DET -// Description : Clear RESTART_DET Interrupt Register -#define I2C_IC_CLR_RESTART_DET_OFFSET _u(0x000000a8) -#define I2C_IC_CLR_RESTART_DET_BITS _u(0x00000001) -#define I2C_IC_CLR_RESTART_DET_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_CLR_RESTART_DET_CLR_RESTART_DET -// Description : Read this register to clear the RESTART_DET interrupt (bit 12) -// of IC_RAW_INTR_STAT register. -// -// Reset value: 0x0 -#define I2C_IC_CLR_RESTART_DET_CLR_RESTART_DET_RESET _u(0x0) -#define I2C_IC_CLR_RESTART_DET_CLR_RESTART_DET_BITS _u(0x00000001) -#define I2C_IC_CLR_RESTART_DET_CLR_RESTART_DET_MSB _u(0) -#define I2C_IC_CLR_RESTART_DET_CLR_RESTART_DET_LSB _u(0) -#define I2C_IC_CLR_RESTART_DET_CLR_RESTART_DET_ACCESS "RO" -// ============================================================================= -// Register : I2C_IC_COMP_PARAM_1 -// Description : Component Parameter Register 1 -// -// Note This register is not implemented and therefore reads as 0. -// If it was implemented it would be a constant read-only register -// that contains encoded information about the component's -// parameter settings. Fields shown below are the settings for -// those parameters -#define I2C_IC_COMP_PARAM_1_OFFSET _u(0x000000f4) -#define I2C_IC_COMP_PARAM_1_BITS _u(0x00ffffff) -#define I2C_IC_COMP_PARAM_1_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_COMP_PARAM_1_TX_BUFFER_DEPTH -// Description : TX Buffer Depth = 16 -#define I2C_IC_COMP_PARAM_1_TX_BUFFER_DEPTH_RESET _u(0x00) -#define I2C_IC_COMP_PARAM_1_TX_BUFFER_DEPTH_BITS _u(0x00ff0000) -#define I2C_IC_COMP_PARAM_1_TX_BUFFER_DEPTH_MSB _u(23) -#define I2C_IC_COMP_PARAM_1_TX_BUFFER_DEPTH_LSB _u(16) -#define I2C_IC_COMP_PARAM_1_TX_BUFFER_DEPTH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : I2C_IC_COMP_PARAM_1_RX_BUFFER_DEPTH -// Description : RX Buffer Depth = 16 -#define I2C_IC_COMP_PARAM_1_RX_BUFFER_DEPTH_RESET _u(0x00) -#define I2C_IC_COMP_PARAM_1_RX_BUFFER_DEPTH_BITS _u(0x0000ff00) -#define I2C_IC_COMP_PARAM_1_RX_BUFFER_DEPTH_MSB _u(15) -#define I2C_IC_COMP_PARAM_1_RX_BUFFER_DEPTH_LSB _u(8) -#define I2C_IC_COMP_PARAM_1_RX_BUFFER_DEPTH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : I2C_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS -// Description : Encoded parameters not visible -#define I2C_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS_RESET _u(0x0) -#define I2C_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS_BITS _u(0x00000080) -#define I2C_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS_MSB _u(7) -#define I2C_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS_LSB _u(7) -#define I2C_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : I2C_IC_COMP_PARAM_1_HAS_DMA -// Description : DMA handshaking signals are enabled -#define I2C_IC_COMP_PARAM_1_HAS_DMA_RESET _u(0x0) -#define I2C_IC_COMP_PARAM_1_HAS_DMA_BITS _u(0x00000040) -#define I2C_IC_COMP_PARAM_1_HAS_DMA_MSB _u(6) -#define I2C_IC_COMP_PARAM_1_HAS_DMA_LSB _u(6) -#define I2C_IC_COMP_PARAM_1_HAS_DMA_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : I2C_IC_COMP_PARAM_1_INTR_IO -// Description : COMBINED Interrupt outputs -#define I2C_IC_COMP_PARAM_1_INTR_IO_RESET _u(0x0) -#define I2C_IC_COMP_PARAM_1_INTR_IO_BITS _u(0x00000020) -#define I2C_IC_COMP_PARAM_1_INTR_IO_MSB _u(5) -#define I2C_IC_COMP_PARAM_1_INTR_IO_LSB _u(5) -#define I2C_IC_COMP_PARAM_1_INTR_IO_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : I2C_IC_COMP_PARAM_1_HC_COUNT_VALUES -// Description : Programmable count values for each mode. -#define I2C_IC_COMP_PARAM_1_HC_COUNT_VALUES_RESET _u(0x0) -#define I2C_IC_COMP_PARAM_1_HC_COUNT_VALUES_BITS _u(0x00000010) -#define I2C_IC_COMP_PARAM_1_HC_COUNT_VALUES_MSB _u(4) -#define I2C_IC_COMP_PARAM_1_HC_COUNT_VALUES_LSB _u(4) -#define I2C_IC_COMP_PARAM_1_HC_COUNT_VALUES_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE -// Description : MAX SPEED MODE = FAST MODE -#define I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE_RESET _u(0x0) -#define I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE_BITS _u(0x0000000c) -#define I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE_MSB _u(3) -#define I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE_LSB _u(2) -#define I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH -// Description : APB data bus width is 32 bits -#define I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH_RESET _u(0x0) -#define I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH_BITS _u(0x00000003) -#define I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH_MSB _u(1) -#define I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH_LSB _u(0) -#define I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH_ACCESS "RO" -// ============================================================================= -// Register : I2C_IC_COMP_VERSION -// Description : I2C Component Version Register -#define I2C_IC_COMP_VERSION_OFFSET _u(0x000000f8) -#define I2C_IC_COMP_VERSION_BITS _u(0xffffffff) -#define I2C_IC_COMP_VERSION_RESET _u(0x3230312a) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_COMP_VERSION_IC_COMP_VERSION -#define I2C_IC_COMP_VERSION_IC_COMP_VERSION_RESET _u(0x3230312a) -#define I2C_IC_COMP_VERSION_IC_COMP_VERSION_BITS _u(0xffffffff) -#define I2C_IC_COMP_VERSION_IC_COMP_VERSION_MSB _u(31) -#define I2C_IC_COMP_VERSION_IC_COMP_VERSION_LSB _u(0) -#define I2C_IC_COMP_VERSION_IC_COMP_VERSION_ACCESS "RO" -// ============================================================================= -// Register : I2C_IC_COMP_TYPE -// Description : I2C Component Type Register -#define I2C_IC_COMP_TYPE_OFFSET _u(0x000000fc) -#define I2C_IC_COMP_TYPE_BITS _u(0xffffffff) -#define I2C_IC_COMP_TYPE_RESET _u(0x44570140) -// ----------------------------------------------------------------------------- -// Field : I2C_IC_COMP_TYPE_IC_COMP_TYPE -// Description : Designware Component Type number = 0x44_57_01_40. This assigned -// unique hex value is constant and is derived from the two ASCII -// letters 'DW' followed by a 16-bit unsigned number. -#define I2C_IC_COMP_TYPE_IC_COMP_TYPE_RESET _u(0x44570140) -#define I2C_IC_COMP_TYPE_IC_COMP_TYPE_BITS _u(0xffffffff) -#define I2C_IC_COMP_TYPE_IC_COMP_TYPE_MSB _u(31) -#define I2C_IC_COMP_TYPE_IC_COMP_TYPE_LSB _u(0) -#define I2C_IC_COMP_TYPE_IC_COMP_TYPE_ACCESS "RO" -// ============================================================================= -#endif // _HARDWARE_REGS_I2C_H - diff --git a/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/intctrl.h b/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/intctrl.h deleted file mode 100644 index 96ce815e47..0000000000 --- a/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/intctrl.h +++ /dev/null @@ -1,184 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _INTCTRL_H -#define _INTCTRL_H - -/** - * \file rp2350/intctrl.h - */ - -#ifdef __ASSEMBLER__ -#define TIMER0_IRQ_0 0 -#define TIMER0_IRQ_1 1 -#define TIMER0_IRQ_2 2 -#define TIMER0_IRQ_3 3 -#define TIMER1_IRQ_0 4 -#define TIMER1_IRQ_1 5 -#define TIMER1_IRQ_2 6 -#define TIMER1_IRQ_3 7 -#define PWM_IRQ_WRAP_0 8 -#define PWM_IRQ_WRAP_1 9 -#define DMA_IRQ_0 10 -#define DMA_IRQ_1 11 -#define DMA_IRQ_2 12 -#define DMA_IRQ_3 13 -#define USBCTRL_IRQ 14 -#define PIO0_IRQ_0 15 -#define PIO0_IRQ_1 16 -#define PIO1_IRQ_0 17 -#define PIO1_IRQ_1 18 -#define PIO2_IRQ_0 19 -#define PIO2_IRQ_1 20 -#define IO_IRQ_BANK0 21 -#define IO_IRQ_BANK0_NS 22 -#define IO_IRQ_QSPI 23 -#define IO_IRQ_QSPI_NS 24 -#define SIO_IRQ_FIFO 25 -#define SIO_IRQ_BELL 26 -#define SIO_IRQ_FIFO_NS 27 -#define SIO_IRQ_BELL_NS 28 -#define SIO_IRQ_MTIMECMP 29 -#define CLOCKS_IRQ 30 -#define SPI0_IRQ 31 -#define SPI1_IRQ 32 -#define UART0_IRQ 33 -#define UART1_IRQ 34 -#define ADC_IRQ_FIFO 35 -#define I2C0_IRQ 36 -#define I2C1_IRQ 37 -#define OTP_IRQ 38 -#define TRNG_IRQ 39 -#define PROC0_IRQ_CTI 40 -#define PROC1_IRQ_CTI 41 -#define PLL_SYS_IRQ 42 -#define PLL_USB_IRQ 43 -#define POWMAN_IRQ_POW 44 -#define POWMAN_IRQ_TIMER 45 -#define SPAREIRQ_IRQ_0 46 -#define SPAREIRQ_IRQ_1 47 -#define SPAREIRQ_IRQ_2 48 -#define SPAREIRQ_IRQ_3 49 -#define SPAREIRQ_IRQ_4 50 -#define SPAREIRQ_IRQ_5 51 -#else -/** - * \brief Interrupt numbers on RP2350 (used as typedef \ref irq_num_t) - * \ingroup hardware_irq - */ -typedef enum irq_num_rp2350 { - TIMER0_IRQ_0 = 0, ///< Select TIMER0's IRQ 0 output - TIMER0_IRQ_1 = 1, ///< Select TIMER0's IRQ 1 output - TIMER0_IRQ_2 = 2, ///< Select TIMER0's IRQ 2 output - TIMER0_IRQ_3 = 3, ///< Select TIMER0's IRQ 3 output - TIMER1_IRQ_0 = 4, ///< Select TIMER1's IRQ 0 output - TIMER1_IRQ_1 = 5, ///< Select TIMER1's IRQ 1 output - TIMER1_IRQ_2 = 6, ///< Select TIMER1's IRQ 2 output - TIMER1_IRQ_3 = 7, ///< Select TIMER1's IRQ 3 output - PWM_IRQ_WRAP_0 = 8, ///< Select PWM's IRQ_WRAP 0 output - PWM_IRQ_WRAP_1 = 9, ///< Select PWM's IRQ_WRAP 1 output - DMA_IRQ_0 = 10, ///< Select DMA's IRQ 0 output - DMA_IRQ_1 = 11, ///< Select DMA's IRQ 1 output - DMA_IRQ_2 = 12, ///< Select DMA's IRQ 2 output - DMA_IRQ_3 = 13, ///< Select DMA's IRQ 3 output - USBCTRL_IRQ = 14, ///< Select USBCTRL's IRQ output - PIO0_IRQ_0 = 15, ///< Select PIO0's IRQ 0 output - PIO0_IRQ_1 = 16, ///< Select PIO0's IRQ 1 output - PIO1_IRQ_0 = 17, ///< Select PIO1's IRQ 0 output - PIO1_IRQ_1 = 18, ///< Select PIO1's IRQ 1 output - PIO2_IRQ_0 = 19, ///< Select PIO2's IRQ 0 output - PIO2_IRQ_1 = 20, ///< Select PIO2's IRQ 1 output - IO_IRQ_BANK0 = 21, ///< Select IO_BANK0's IRQ output - IO_IRQ_BANK0_NS = 22, ///< Select IO_BANK0_NS's IRQ output - IO_IRQ_QSPI = 23, ///< Select IO_QSPI's IRQ output - IO_IRQ_QSPI_NS = 24, ///< Select IO_QSPI_NS's IRQ output - SIO_IRQ_FIFO = 25, ///< Select SIO's IRQ_FIFO output - SIO_IRQ_BELL = 26, ///< Select SIO's IRQ_BELL output - SIO_IRQ_FIFO_NS = 27, ///< Select SIO_NS's IRQ_FIFO output - SIO_IRQ_BELL_NS = 28, ///< Select SIO_NS's IRQ_BELL output - SIO_IRQ_MTIMECMP = 29, ///< Select SIO_IRQ_MTIMECMP's IRQ output - CLOCKS_IRQ = 30, ///< Select CLOCKS's IRQ output - SPI0_IRQ = 31, ///< Select SPI0's IRQ output - SPI1_IRQ = 32, ///< Select SPI1's IRQ output - UART0_IRQ = 33, ///< Select UART0's IRQ output - UART1_IRQ = 34, ///< Select UART1's IRQ output - ADC_IRQ_FIFO = 35, ///< Select ADC's IRQ_FIFO output - I2C0_IRQ = 36, ///< Select I2C0's IRQ output - I2C1_IRQ = 37, ///< Select I2C1's IRQ output - OTP_IRQ = 38, ///< Select OTP's IRQ output - TRNG_IRQ = 39, ///< Select TRNG's IRQ output - PROC0_IRQ_CTI = 40, ///< Select PROC0's IRQ_CTI output - PROC1_IRQ_CTI = 41, ///< Select PROC1's IRQ_CTI output - PLL_SYS_IRQ = 42, ///< Select PLL_SYS's IRQ output - PLL_USB_IRQ = 43, ///< Select PLL_USB's IRQ output - POWMAN_IRQ_POW = 44, ///< Select POWMAN's IRQ_POW output - POWMAN_IRQ_TIMER = 45, ///< Select POWMAN's IRQ_TIMER output - SPARE_IRQ_0 = 46, ///< Select SPARE IRQ 0 - SPARE_IRQ_1 = 47, ///< Select SPARE IRQ 1 - SPARE_IRQ_2 = 48, ///< Select SPARE IRQ 2 - SPARE_IRQ_3 = 49, ///< Select SPARE IRQ 3 - SPARE_IRQ_4 = 50, ///< Select SPARE IRQ 4 - SPARE_IRQ_5 = 51, ///< Select SPARE IRQ 5 - IRQ_COUNT -} irq_num_t; -#endif - -#define isr_timer0_0 isr_irq0 -#define isr_timer0_1 isr_irq1 -#define isr_timer0_2 isr_irq2 -#define isr_timer0_3 isr_irq3 -#define isr_timer1_0 isr_irq4 -#define isr_timer1_1 isr_irq5 -#define isr_timer1_2 isr_irq6 -#define isr_timer1_3 isr_irq7 -#define isr_pwm_wrap_0 isr_irq8 -#define isr_pwm_wrap_1 isr_irq9 -#define isr_dma_0 isr_irq10 -#define isr_dma_1 isr_irq11 -#define isr_dma_2 isr_irq12 -#define isr_dma_3 isr_irq13 -#define isr_usbctrl isr_irq14 -#define isr_pio0_0 isr_irq15 -#define isr_pio0_1 isr_irq16 -#define isr_pio1_0 isr_irq17 -#define isr_pio1_1 isr_irq18 -#define isr_pio2_0 isr_irq19 -#define isr_pio2_1 isr_irq20 -#define isr_io_bank0 isr_irq21 -#define isr_io_bank0_ns isr_irq22 -#define isr_io_qspi isr_irq23 -#define isr_io_qspi_ns isr_irq24 -#define isr_sio_fifo isr_irq25 -#define isr_sio_bell isr_irq26 -#define isr_sio_fifo_ns isr_irq27 -#define isr_sio_bell_ns isr_irq28 -#define isr_sio_mtimecmp isr_irq29 -#define isr_clocks isr_irq30 -#define isr_spi0 isr_irq31 -#define isr_spi1 isr_irq32 -#define isr_uart0 isr_irq33 -#define isr_uart1 isr_irq34 -#define isr_adc_fifo isr_irq35 -#define isr_i2c0 isr_irq36 -#define isr_i2c1 isr_irq37 -#define isr_otp isr_irq38 -#define isr_trng isr_irq39 -#define isr_proc0_cti isr_irq40 -#define isr_proc1_cti isr_irq41 -#define isr_pll_sys isr_irq42 -#define isr_pll_usb isr_irq43 -#define isr_powman_pow isr_irq44 -#define isr_powman_timer isr_irq45 -#define isr_spare_0 isr_irq46 -#define isr_spare_1 isr_irq47 -#define isr_spare_2 isr_irq48 -#define isr_spare_3 isr_irq49 -#define isr_spare_4 isr_irq50 -#define isr_spare_5 isr_irq51 - -#endif // _INTCTRL_H - diff --git a/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/io_bank0.h b/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/io_bank0.h deleted file mode 100644 index 6c2f96ecb5..0000000000 --- a/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/io_bank0.h +++ /dev/null @@ -1,22339 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -// ============================================================================= -// Register block : IO_BANK0 -// Version : 1 -// Bus type : apb -// ============================================================================= -#ifndef _HARDWARE_REGS_IO_BANK0_H -#define _HARDWARE_REGS_IO_BANK0_H -// ============================================================================= -// Register : IO_BANK0_GPIO0_STATUS -#define IO_BANK0_GPIO0_STATUS_OFFSET _u(0x00000000) -#define IO_BANK0_GPIO0_STATUS_BITS _u(0x04022200) -#define IO_BANK0_GPIO0_STATUS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO0_STATUS_IRQTOPROC -// Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO0_STATUS_IRQTOPROC_RESET _u(0x0) -#define IO_BANK0_GPIO0_STATUS_IRQTOPROC_BITS _u(0x04000000) -#define IO_BANK0_GPIO0_STATUS_IRQTOPROC_MSB _u(26) -#define IO_BANK0_GPIO0_STATUS_IRQTOPROC_LSB _u(26) -#define IO_BANK0_GPIO0_STATUS_IRQTOPROC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO0_STATUS_INFROMPAD -// Description : input signal from pad, before filtering and override are -// applied -#define IO_BANK0_GPIO0_STATUS_INFROMPAD_RESET _u(0x0) -#define IO_BANK0_GPIO0_STATUS_INFROMPAD_BITS _u(0x00020000) -#define IO_BANK0_GPIO0_STATUS_INFROMPAD_MSB _u(17) -#define IO_BANK0_GPIO0_STATUS_INFROMPAD_LSB _u(17) -#define IO_BANK0_GPIO0_STATUS_INFROMPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO0_STATUS_OETOPAD -// Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO0_STATUS_OETOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO0_STATUS_OETOPAD_BITS _u(0x00002000) -#define IO_BANK0_GPIO0_STATUS_OETOPAD_MSB _u(13) -#define IO_BANK0_GPIO0_STATUS_OETOPAD_LSB _u(13) -#define IO_BANK0_GPIO0_STATUS_OETOPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO0_STATUS_OUTTOPAD -// Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO0_STATUS_OUTTOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO0_STATUS_OUTTOPAD_BITS _u(0x00000200) -#define IO_BANK0_GPIO0_STATUS_OUTTOPAD_MSB _u(9) -#define IO_BANK0_GPIO0_STATUS_OUTTOPAD_LSB _u(9) -#define IO_BANK0_GPIO0_STATUS_OUTTOPAD_ACCESS "RO" -// ============================================================================= -// Register : IO_BANK0_GPIO0_CTRL -#define IO_BANK0_GPIO0_CTRL_OFFSET _u(0x00000004) -#define IO_BANK0_GPIO0_CTRL_BITS _u(0x3003f01f) -#define IO_BANK0_GPIO0_CTRL_RESET _u(0x0000001f) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO0_CTRL_IRQOVER -// 0x0 -> don't invert the interrupt -// 0x1 -> invert the interrupt -// 0x2 -> drive interrupt low -// 0x3 -> drive interrupt high -#define IO_BANK0_GPIO0_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO0_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO0_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO0_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO0_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO0_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO0_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO0_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO0_CTRL_IRQOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO0_CTRL_INOVER -// 0x0 -> don't invert the peri input -// 0x1 -> invert the peri input -// 0x2 -> drive peri input low -// 0x3 -> drive peri input high -#define IO_BANK0_GPIO0_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO0_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO0_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO0_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO0_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO0_CTRL_INOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO0_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO0_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO0_CTRL_INOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO0_CTRL_OEOVER -// 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel -// 0x2 -> disable output -// 0x3 -> enable output -#define IO_BANK0_GPIO0_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO0_CTRL_OEOVER_BITS _u(0x0000c000) -#define IO_BANK0_GPIO0_CTRL_OEOVER_MSB _u(15) -#define IO_BANK0_GPIO0_CTRL_OEOVER_LSB _u(14) -#define IO_BANK0_GPIO0_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO0_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO0_CTRL_OEOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO0_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO0_CTRL_OEOVER_VALUE_ENABLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO0_CTRL_OUTOVER -// 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel -// 0x2 -> drive output low -// 0x3 -> drive output high -#define IO_BANK0_GPIO0_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO0_CTRL_OUTOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO0_CTRL_OUTOVER_MSB _u(13) -#define IO_BANK0_GPIO0_CTRL_OUTOVER_LSB _u(12) -#define IO_BANK0_GPIO0_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO0_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO0_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO0_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO0_CTRL_OUTOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO0_CTRL_FUNCSEL -// Description : 0-31 -> selects pin function according to the gpio table -// 31 == NULL -// 0x00 -> jtag_tck -// 0x01 -> spi0_rx -// 0x02 -> uart0_tx -// 0x03 -> i2c0_sda -// 0x04 -> pwm_a_0 -// 0x05 -> siob_proc_0 -// 0x06 -> pio0_0 -// 0x07 -> pio1_0 -// 0x08 -> pio2_0 -// 0x09 -> xip_ss_n_1 -// 0x0a -> usb_muxing_overcurr_detect -// 0x1f -> null -#define IO_BANK0_GPIO0_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO0_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO0_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO0_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO0_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_JTAG_TCK _u(0x00) -#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_SPI0_RX _u(0x01) -#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_UART0_TX _u(0x02) -#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03) -#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_PWM_A_0 _u(0x04) -#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_SIOB_PROC_0 _u(0x05) -#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_PIO0_0 _u(0x06) -#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_PIO1_0 _u(0x07) -#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_PIO2_0 _u(0x08) -#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_XIP_SS_N_1 _u(0x09) -#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x0a) -#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) -// ============================================================================= -// Register : IO_BANK0_GPIO1_STATUS -#define IO_BANK0_GPIO1_STATUS_OFFSET _u(0x00000008) -#define IO_BANK0_GPIO1_STATUS_BITS _u(0x04022200) -#define IO_BANK0_GPIO1_STATUS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO1_STATUS_IRQTOPROC -// Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO1_STATUS_IRQTOPROC_RESET _u(0x0) -#define IO_BANK0_GPIO1_STATUS_IRQTOPROC_BITS _u(0x04000000) -#define IO_BANK0_GPIO1_STATUS_IRQTOPROC_MSB _u(26) -#define IO_BANK0_GPIO1_STATUS_IRQTOPROC_LSB _u(26) -#define IO_BANK0_GPIO1_STATUS_IRQTOPROC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO1_STATUS_INFROMPAD -// Description : input signal from pad, before filtering and override are -// applied -#define IO_BANK0_GPIO1_STATUS_INFROMPAD_RESET _u(0x0) -#define IO_BANK0_GPIO1_STATUS_INFROMPAD_BITS _u(0x00020000) -#define IO_BANK0_GPIO1_STATUS_INFROMPAD_MSB _u(17) -#define IO_BANK0_GPIO1_STATUS_INFROMPAD_LSB _u(17) -#define IO_BANK0_GPIO1_STATUS_INFROMPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO1_STATUS_OETOPAD -// Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO1_STATUS_OETOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO1_STATUS_OETOPAD_BITS _u(0x00002000) -#define IO_BANK0_GPIO1_STATUS_OETOPAD_MSB _u(13) -#define IO_BANK0_GPIO1_STATUS_OETOPAD_LSB _u(13) -#define IO_BANK0_GPIO1_STATUS_OETOPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO1_STATUS_OUTTOPAD -// Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO1_STATUS_OUTTOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO1_STATUS_OUTTOPAD_BITS _u(0x00000200) -#define IO_BANK0_GPIO1_STATUS_OUTTOPAD_MSB _u(9) -#define IO_BANK0_GPIO1_STATUS_OUTTOPAD_LSB _u(9) -#define IO_BANK0_GPIO1_STATUS_OUTTOPAD_ACCESS "RO" -// ============================================================================= -// Register : IO_BANK0_GPIO1_CTRL -#define IO_BANK0_GPIO1_CTRL_OFFSET _u(0x0000000c) -#define IO_BANK0_GPIO1_CTRL_BITS _u(0x3003f01f) -#define IO_BANK0_GPIO1_CTRL_RESET _u(0x0000001f) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO1_CTRL_IRQOVER -// 0x0 -> don't invert the interrupt -// 0x1 -> invert the interrupt -// 0x2 -> drive interrupt low -// 0x3 -> drive interrupt high -#define IO_BANK0_GPIO1_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO1_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO1_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO1_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO1_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO1_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO1_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO1_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO1_CTRL_IRQOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO1_CTRL_INOVER -// 0x0 -> don't invert the peri input -// 0x1 -> invert the peri input -// 0x2 -> drive peri input low -// 0x3 -> drive peri input high -#define IO_BANK0_GPIO1_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO1_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO1_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO1_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO1_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO1_CTRL_INOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO1_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO1_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO1_CTRL_INOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO1_CTRL_OEOVER -// 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel -// 0x2 -> disable output -// 0x3 -> enable output -#define IO_BANK0_GPIO1_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO1_CTRL_OEOVER_BITS _u(0x0000c000) -#define IO_BANK0_GPIO1_CTRL_OEOVER_MSB _u(15) -#define IO_BANK0_GPIO1_CTRL_OEOVER_LSB _u(14) -#define IO_BANK0_GPIO1_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO1_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO1_CTRL_OEOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO1_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO1_CTRL_OEOVER_VALUE_ENABLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO1_CTRL_OUTOVER -// 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel -// 0x2 -> drive output low -// 0x3 -> drive output high -#define IO_BANK0_GPIO1_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO1_CTRL_OUTOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO1_CTRL_OUTOVER_MSB _u(13) -#define IO_BANK0_GPIO1_CTRL_OUTOVER_LSB _u(12) -#define IO_BANK0_GPIO1_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO1_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO1_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO1_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO1_CTRL_OUTOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO1_CTRL_FUNCSEL -// Description : 0-31 -> selects pin function according to the gpio table -// 31 == NULL -// 0x00 -> jtag_tms -// 0x01 -> spi0_ss_n -// 0x02 -> uart0_rx -// 0x03 -> i2c0_scl -// 0x04 -> pwm_b_0 -// 0x05 -> siob_proc_1 -// 0x06 -> pio0_1 -// 0x07 -> pio1_1 -// 0x08 -> pio2_1 -// 0x09 -> coresight_traceclk -// 0x0a -> usb_muxing_vbus_detect -// 0x1f -> null -#define IO_BANK0_GPIO1_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO1_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO1_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO1_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO1_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_JTAG_TMS _u(0x00) -#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_SPI0_SS_N _u(0x01) -#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_UART0_RX _u(0x02) -#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03) -#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_PWM_B_0 _u(0x04) -#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_SIOB_PROC_1 _u(0x05) -#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_PIO0_1 _u(0x06) -#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_PIO1_1 _u(0x07) -#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_PIO2_1 _u(0x08) -#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_CORESIGHT_TRACECLK _u(0x09) -#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x0a) -#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) -// ============================================================================= -// Register : IO_BANK0_GPIO2_STATUS -#define IO_BANK0_GPIO2_STATUS_OFFSET _u(0x00000010) -#define IO_BANK0_GPIO2_STATUS_BITS _u(0x04022200) -#define IO_BANK0_GPIO2_STATUS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO2_STATUS_IRQTOPROC -// Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO2_STATUS_IRQTOPROC_RESET _u(0x0) -#define IO_BANK0_GPIO2_STATUS_IRQTOPROC_BITS _u(0x04000000) -#define IO_BANK0_GPIO2_STATUS_IRQTOPROC_MSB _u(26) -#define IO_BANK0_GPIO2_STATUS_IRQTOPROC_LSB _u(26) -#define IO_BANK0_GPIO2_STATUS_IRQTOPROC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO2_STATUS_INFROMPAD -// Description : input signal from pad, before filtering and override are -// applied -#define IO_BANK0_GPIO2_STATUS_INFROMPAD_RESET _u(0x0) -#define IO_BANK0_GPIO2_STATUS_INFROMPAD_BITS _u(0x00020000) -#define IO_BANK0_GPIO2_STATUS_INFROMPAD_MSB _u(17) -#define IO_BANK0_GPIO2_STATUS_INFROMPAD_LSB _u(17) -#define IO_BANK0_GPIO2_STATUS_INFROMPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO2_STATUS_OETOPAD -// Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO2_STATUS_OETOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO2_STATUS_OETOPAD_BITS _u(0x00002000) -#define IO_BANK0_GPIO2_STATUS_OETOPAD_MSB _u(13) -#define IO_BANK0_GPIO2_STATUS_OETOPAD_LSB _u(13) -#define IO_BANK0_GPIO2_STATUS_OETOPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO2_STATUS_OUTTOPAD -// Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO2_STATUS_OUTTOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO2_STATUS_OUTTOPAD_BITS _u(0x00000200) -#define IO_BANK0_GPIO2_STATUS_OUTTOPAD_MSB _u(9) -#define IO_BANK0_GPIO2_STATUS_OUTTOPAD_LSB _u(9) -#define IO_BANK0_GPIO2_STATUS_OUTTOPAD_ACCESS "RO" -// ============================================================================= -// Register : IO_BANK0_GPIO2_CTRL -#define IO_BANK0_GPIO2_CTRL_OFFSET _u(0x00000014) -#define IO_BANK0_GPIO2_CTRL_BITS _u(0x3003f01f) -#define IO_BANK0_GPIO2_CTRL_RESET _u(0x0000001f) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO2_CTRL_IRQOVER -// 0x0 -> don't invert the interrupt -// 0x1 -> invert the interrupt -// 0x2 -> drive interrupt low -// 0x3 -> drive interrupt high -#define IO_BANK0_GPIO2_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO2_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO2_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO2_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO2_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO2_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO2_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO2_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO2_CTRL_IRQOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO2_CTRL_INOVER -// 0x0 -> don't invert the peri input -// 0x1 -> invert the peri input -// 0x2 -> drive peri input low -// 0x3 -> drive peri input high -#define IO_BANK0_GPIO2_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO2_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO2_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO2_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO2_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO2_CTRL_INOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO2_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO2_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO2_CTRL_INOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO2_CTRL_OEOVER -// 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel -// 0x2 -> disable output -// 0x3 -> enable output -#define IO_BANK0_GPIO2_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO2_CTRL_OEOVER_BITS _u(0x0000c000) -#define IO_BANK0_GPIO2_CTRL_OEOVER_MSB _u(15) -#define IO_BANK0_GPIO2_CTRL_OEOVER_LSB _u(14) -#define IO_BANK0_GPIO2_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO2_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO2_CTRL_OEOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO2_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO2_CTRL_OEOVER_VALUE_ENABLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO2_CTRL_OUTOVER -// 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel -// 0x2 -> drive output low -// 0x3 -> drive output high -#define IO_BANK0_GPIO2_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO2_CTRL_OUTOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO2_CTRL_OUTOVER_MSB _u(13) -#define IO_BANK0_GPIO2_CTRL_OUTOVER_LSB _u(12) -#define IO_BANK0_GPIO2_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO2_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO2_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO2_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO2_CTRL_OUTOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO2_CTRL_FUNCSEL -// Description : 0-31 -> selects pin function according to the gpio table -// 31 == NULL -// 0x00 -> jtag_tdi -// 0x01 -> spi0_sclk -// 0x02 -> uart0_cts -// 0x03 -> i2c1_sda -// 0x04 -> pwm_a_1 -// 0x05 -> siob_proc_2 -// 0x06 -> pio0_2 -// 0x07 -> pio1_2 -// 0x08 -> pio2_2 -// 0x09 -> coresight_tracedata_0 -// 0x0a -> usb_muxing_vbus_en -// 0x0b -> uart0_tx -// 0x1f -> null -#define IO_BANK0_GPIO2_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO2_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO2_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO2_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO2_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_JTAG_TDI _u(0x00) -#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_SPI0_SCLK _u(0x01) -#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_UART0_CTS _u(0x02) -#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03) -#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_PWM_A_1 _u(0x04) -#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_SIOB_PROC_2 _u(0x05) -#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_PIO0_2 _u(0x06) -#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_PIO1_2 _u(0x07) -#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_PIO2_2 _u(0x08) -#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_CORESIGHT_TRACEDATA_0 _u(0x09) -#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x0a) -#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_UART0_TX _u(0x0b) -#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) -// ============================================================================= -// Register : IO_BANK0_GPIO3_STATUS -#define IO_BANK0_GPIO3_STATUS_OFFSET _u(0x00000018) -#define IO_BANK0_GPIO3_STATUS_BITS _u(0x04022200) -#define IO_BANK0_GPIO3_STATUS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO3_STATUS_IRQTOPROC -// Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO3_STATUS_IRQTOPROC_RESET _u(0x0) -#define IO_BANK0_GPIO3_STATUS_IRQTOPROC_BITS _u(0x04000000) -#define IO_BANK0_GPIO3_STATUS_IRQTOPROC_MSB _u(26) -#define IO_BANK0_GPIO3_STATUS_IRQTOPROC_LSB _u(26) -#define IO_BANK0_GPIO3_STATUS_IRQTOPROC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO3_STATUS_INFROMPAD -// Description : input signal from pad, before filtering and override are -// applied -#define IO_BANK0_GPIO3_STATUS_INFROMPAD_RESET _u(0x0) -#define IO_BANK0_GPIO3_STATUS_INFROMPAD_BITS _u(0x00020000) -#define IO_BANK0_GPIO3_STATUS_INFROMPAD_MSB _u(17) -#define IO_BANK0_GPIO3_STATUS_INFROMPAD_LSB _u(17) -#define IO_BANK0_GPIO3_STATUS_INFROMPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO3_STATUS_OETOPAD -// Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO3_STATUS_OETOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO3_STATUS_OETOPAD_BITS _u(0x00002000) -#define IO_BANK0_GPIO3_STATUS_OETOPAD_MSB _u(13) -#define IO_BANK0_GPIO3_STATUS_OETOPAD_LSB _u(13) -#define IO_BANK0_GPIO3_STATUS_OETOPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO3_STATUS_OUTTOPAD -// Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO3_STATUS_OUTTOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO3_STATUS_OUTTOPAD_BITS _u(0x00000200) -#define IO_BANK0_GPIO3_STATUS_OUTTOPAD_MSB _u(9) -#define IO_BANK0_GPIO3_STATUS_OUTTOPAD_LSB _u(9) -#define IO_BANK0_GPIO3_STATUS_OUTTOPAD_ACCESS "RO" -// ============================================================================= -// Register : IO_BANK0_GPIO3_CTRL -#define IO_BANK0_GPIO3_CTRL_OFFSET _u(0x0000001c) -#define IO_BANK0_GPIO3_CTRL_BITS _u(0x3003f01f) -#define IO_BANK0_GPIO3_CTRL_RESET _u(0x0000001f) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO3_CTRL_IRQOVER -// 0x0 -> don't invert the interrupt -// 0x1 -> invert the interrupt -// 0x2 -> drive interrupt low -// 0x3 -> drive interrupt high -#define IO_BANK0_GPIO3_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO3_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO3_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO3_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO3_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO3_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO3_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO3_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO3_CTRL_IRQOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO3_CTRL_INOVER -// 0x0 -> don't invert the peri input -// 0x1 -> invert the peri input -// 0x2 -> drive peri input low -// 0x3 -> drive peri input high -#define IO_BANK0_GPIO3_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO3_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO3_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO3_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO3_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO3_CTRL_INOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO3_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO3_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO3_CTRL_INOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO3_CTRL_OEOVER -// 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel -// 0x2 -> disable output -// 0x3 -> enable output -#define IO_BANK0_GPIO3_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO3_CTRL_OEOVER_BITS _u(0x0000c000) -#define IO_BANK0_GPIO3_CTRL_OEOVER_MSB _u(15) -#define IO_BANK0_GPIO3_CTRL_OEOVER_LSB _u(14) -#define IO_BANK0_GPIO3_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO3_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO3_CTRL_OEOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO3_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO3_CTRL_OEOVER_VALUE_ENABLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO3_CTRL_OUTOVER -// 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel -// 0x2 -> drive output low -// 0x3 -> drive output high -#define IO_BANK0_GPIO3_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO3_CTRL_OUTOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO3_CTRL_OUTOVER_MSB _u(13) -#define IO_BANK0_GPIO3_CTRL_OUTOVER_LSB _u(12) -#define IO_BANK0_GPIO3_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO3_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO3_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO3_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO3_CTRL_OUTOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO3_CTRL_FUNCSEL -// Description : 0-31 -> selects pin function according to the gpio table -// 31 == NULL -// 0x00 -> jtag_tdo -// 0x01 -> spi0_tx -// 0x02 -> uart0_rts -// 0x03 -> i2c1_scl -// 0x04 -> pwm_b_1 -// 0x05 -> siob_proc_3 -// 0x06 -> pio0_3 -// 0x07 -> pio1_3 -// 0x08 -> pio2_3 -// 0x09 -> coresight_tracedata_1 -// 0x0a -> usb_muxing_overcurr_detect -// 0x0b -> uart0_rx -// 0x1f -> null -#define IO_BANK0_GPIO3_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO3_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO3_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO3_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO3_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_JTAG_TDO _u(0x00) -#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_SPI0_TX _u(0x01) -#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_UART0_RTS _u(0x02) -#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03) -#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_PWM_B_1 _u(0x04) -#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_SIOB_PROC_3 _u(0x05) -#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_PIO0_3 _u(0x06) -#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_PIO1_3 _u(0x07) -#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_PIO2_3 _u(0x08) -#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_CORESIGHT_TRACEDATA_1 _u(0x09) -#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x0a) -#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_UART0_RX _u(0x0b) -#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) -// ============================================================================= -// Register : IO_BANK0_GPIO4_STATUS -#define IO_BANK0_GPIO4_STATUS_OFFSET _u(0x00000020) -#define IO_BANK0_GPIO4_STATUS_BITS _u(0x04022200) -#define IO_BANK0_GPIO4_STATUS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO4_STATUS_IRQTOPROC -// Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO4_STATUS_IRQTOPROC_RESET _u(0x0) -#define IO_BANK0_GPIO4_STATUS_IRQTOPROC_BITS _u(0x04000000) -#define IO_BANK0_GPIO4_STATUS_IRQTOPROC_MSB _u(26) -#define IO_BANK0_GPIO4_STATUS_IRQTOPROC_LSB _u(26) -#define IO_BANK0_GPIO4_STATUS_IRQTOPROC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO4_STATUS_INFROMPAD -// Description : input signal from pad, before filtering and override are -// applied -#define IO_BANK0_GPIO4_STATUS_INFROMPAD_RESET _u(0x0) -#define IO_BANK0_GPIO4_STATUS_INFROMPAD_BITS _u(0x00020000) -#define IO_BANK0_GPIO4_STATUS_INFROMPAD_MSB _u(17) -#define IO_BANK0_GPIO4_STATUS_INFROMPAD_LSB _u(17) -#define IO_BANK0_GPIO4_STATUS_INFROMPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO4_STATUS_OETOPAD -// Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO4_STATUS_OETOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO4_STATUS_OETOPAD_BITS _u(0x00002000) -#define IO_BANK0_GPIO4_STATUS_OETOPAD_MSB _u(13) -#define IO_BANK0_GPIO4_STATUS_OETOPAD_LSB _u(13) -#define IO_BANK0_GPIO4_STATUS_OETOPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO4_STATUS_OUTTOPAD -// Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO4_STATUS_OUTTOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO4_STATUS_OUTTOPAD_BITS _u(0x00000200) -#define IO_BANK0_GPIO4_STATUS_OUTTOPAD_MSB _u(9) -#define IO_BANK0_GPIO4_STATUS_OUTTOPAD_LSB _u(9) -#define IO_BANK0_GPIO4_STATUS_OUTTOPAD_ACCESS "RO" -// ============================================================================= -// Register : IO_BANK0_GPIO4_CTRL -#define IO_BANK0_GPIO4_CTRL_OFFSET _u(0x00000024) -#define IO_BANK0_GPIO4_CTRL_BITS _u(0x3003f01f) -#define IO_BANK0_GPIO4_CTRL_RESET _u(0x0000001f) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO4_CTRL_IRQOVER -// 0x0 -> don't invert the interrupt -// 0x1 -> invert the interrupt -// 0x2 -> drive interrupt low -// 0x3 -> drive interrupt high -#define IO_BANK0_GPIO4_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO4_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO4_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO4_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO4_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO4_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO4_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO4_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO4_CTRL_IRQOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO4_CTRL_INOVER -// 0x0 -> don't invert the peri input -// 0x1 -> invert the peri input -// 0x2 -> drive peri input low -// 0x3 -> drive peri input high -#define IO_BANK0_GPIO4_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO4_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO4_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO4_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO4_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO4_CTRL_INOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO4_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO4_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO4_CTRL_INOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO4_CTRL_OEOVER -// 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel -// 0x2 -> disable output -// 0x3 -> enable output -#define IO_BANK0_GPIO4_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO4_CTRL_OEOVER_BITS _u(0x0000c000) -#define IO_BANK0_GPIO4_CTRL_OEOVER_MSB _u(15) -#define IO_BANK0_GPIO4_CTRL_OEOVER_LSB _u(14) -#define IO_BANK0_GPIO4_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO4_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO4_CTRL_OEOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO4_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO4_CTRL_OEOVER_VALUE_ENABLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO4_CTRL_OUTOVER -// 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel -// 0x2 -> drive output low -// 0x3 -> drive output high -#define IO_BANK0_GPIO4_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO4_CTRL_OUTOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO4_CTRL_OUTOVER_MSB _u(13) -#define IO_BANK0_GPIO4_CTRL_OUTOVER_LSB _u(12) -#define IO_BANK0_GPIO4_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO4_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO4_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO4_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO4_CTRL_OUTOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO4_CTRL_FUNCSEL -// Description : 0-31 -> selects pin function according to the gpio table -// 31 == NULL -// 0x01 -> spi0_rx -// 0x02 -> uart1_tx -// 0x03 -> i2c0_sda -// 0x04 -> pwm_a_2 -// 0x05 -> siob_proc_4 -// 0x06 -> pio0_4 -// 0x07 -> pio1_4 -// 0x08 -> pio2_4 -// 0x09 -> coresight_tracedata_2 -// 0x0a -> usb_muxing_vbus_detect -// 0x1f -> null -#define IO_BANK0_GPIO4_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO4_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO4_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO4_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO4_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_SPI0_RX _u(0x01) -#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_UART1_TX _u(0x02) -#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03) -#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_PWM_A_2 _u(0x04) -#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_SIOB_PROC_4 _u(0x05) -#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_PIO0_4 _u(0x06) -#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_PIO1_4 _u(0x07) -#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_PIO2_4 _u(0x08) -#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_CORESIGHT_TRACEDATA_2 _u(0x09) -#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x0a) -#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) -// ============================================================================= -// Register : IO_BANK0_GPIO5_STATUS -#define IO_BANK0_GPIO5_STATUS_OFFSET _u(0x00000028) -#define IO_BANK0_GPIO5_STATUS_BITS _u(0x04022200) -#define IO_BANK0_GPIO5_STATUS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO5_STATUS_IRQTOPROC -// Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO5_STATUS_IRQTOPROC_RESET _u(0x0) -#define IO_BANK0_GPIO5_STATUS_IRQTOPROC_BITS _u(0x04000000) -#define IO_BANK0_GPIO5_STATUS_IRQTOPROC_MSB _u(26) -#define IO_BANK0_GPIO5_STATUS_IRQTOPROC_LSB _u(26) -#define IO_BANK0_GPIO5_STATUS_IRQTOPROC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO5_STATUS_INFROMPAD -// Description : input signal from pad, before filtering and override are -// applied -#define IO_BANK0_GPIO5_STATUS_INFROMPAD_RESET _u(0x0) -#define IO_BANK0_GPIO5_STATUS_INFROMPAD_BITS _u(0x00020000) -#define IO_BANK0_GPIO5_STATUS_INFROMPAD_MSB _u(17) -#define IO_BANK0_GPIO5_STATUS_INFROMPAD_LSB _u(17) -#define IO_BANK0_GPIO5_STATUS_INFROMPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO5_STATUS_OETOPAD -// Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO5_STATUS_OETOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO5_STATUS_OETOPAD_BITS _u(0x00002000) -#define IO_BANK0_GPIO5_STATUS_OETOPAD_MSB _u(13) -#define IO_BANK0_GPIO5_STATUS_OETOPAD_LSB _u(13) -#define IO_BANK0_GPIO5_STATUS_OETOPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO5_STATUS_OUTTOPAD -// Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO5_STATUS_OUTTOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO5_STATUS_OUTTOPAD_BITS _u(0x00000200) -#define IO_BANK0_GPIO5_STATUS_OUTTOPAD_MSB _u(9) -#define IO_BANK0_GPIO5_STATUS_OUTTOPAD_LSB _u(9) -#define IO_BANK0_GPIO5_STATUS_OUTTOPAD_ACCESS "RO" -// ============================================================================= -// Register : IO_BANK0_GPIO5_CTRL -#define IO_BANK0_GPIO5_CTRL_OFFSET _u(0x0000002c) -#define IO_BANK0_GPIO5_CTRL_BITS _u(0x3003f01f) -#define IO_BANK0_GPIO5_CTRL_RESET _u(0x0000001f) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO5_CTRL_IRQOVER -// 0x0 -> don't invert the interrupt -// 0x1 -> invert the interrupt -// 0x2 -> drive interrupt low -// 0x3 -> drive interrupt high -#define IO_BANK0_GPIO5_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO5_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO5_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO5_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO5_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO5_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO5_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO5_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO5_CTRL_IRQOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO5_CTRL_INOVER -// 0x0 -> don't invert the peri input -// 0x1 -> invert the peri input -// 0x2 -> drive peri input low -// 0x3 -> drive peri input high -#define IO_BANK0_GPIO5_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO5_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO5_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO5_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO5_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO5_CTRL_INOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO5_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO5_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO5_CTRL_INOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO5_CTRL_OEOVER -// 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel -// 0x2 -> disable output -// 0x3 -> enable output -#define IO_BANK0_GPIO5_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO5_CTRL_OEOVER_BITS _u(0x0000c000) -#define IO_BANK0_GPIO5_CTRL_OEOVER_MSB _u(15) -#define IO_BANK0_GPIO5_CTRL_OEOVER_LSB _u(14) -#define IO_BANK0_GPIO5_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO5_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO5_CTRL_OEOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO5_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO5_CTRL_OEOVER_VALUE_ENABLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO5_CTRL_OUTOVER -// 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel -// 0x2 -> drive output low -// 0x3 -> drive output high -#define IO_BANK0_GPIO5_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO5_CTRL_OUTOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO5_CTRL_OUTOVER_MSB _u(13) -#define IO_BANK0_GPIO5_CTRL_OUTOVER_LSB _u(12) -#define IO_BANK0_GPIO5_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO5_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO5_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO5_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO5_CTRL_OUTOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO5_CTRL_FUNCSEL -// Description : 0-31 -> selects pin function according to the gpio table -// 31 == NULL -// 0x01 -> spi0_ss_n -// 0x02 -> uart1_rx -// 0x03 -> i2c0_scl -// 0x04 -> pwm_b_2 -// 0x05 -> siob_proc_5 -// 0x06 -> pio0_5 -// 0x07 -> pio1_5 -// 0x08 -> pio2_5 -// 0x09 -> coresight_tracedata_3 -// 0x0a -> usb_muxing_vbus_en -// 0x1f -> null -#define IO_BANK0_GPIO5_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO5_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO5_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO5_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO5_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_SPI0_SS_N _u(0x01) -#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_UART1_RX _u(0x02) -#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03) -#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_PWM_B_2 _u(0x04) -#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_SIOB_PROC_5 _u(0x05) -#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_PIO0_5 _u(0x06) -#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_PIO1_5 _u(0x07) -#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_PIO2_5 _u(0x08) -#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_CORESIGHT_TRACEDATA_3 _u(0x09) -#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x0a) -#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) -// ============================================================================= -// Register : IO_BANK0_GPIO6_STATUS -#define IO_BANK0_GPIO6_STATUS_OFFSET _u(0x00000030) -#define IO_BANK0_GPIO6_STATUS_BITS _u(0x04022200) -#define IO_BANK0_GPIO6_STATUS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO6_STATUS_IRQTOPROC -// Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO6_STATUS_IRQTOPROC_RESET _u(0x0) -#define IO_BANK0_GPIO6_STATUS_IRQTOPROC_BITS _u(0x04000000) -#define IO_BANK0_GPIO6_STATUS_IRQTOPROC_MSB _u(26) -#define IO_BANK0_GPIO6_STATUS_IRQTOPROC_LSB _u(26) -#define IO_BANK0_GPIO6_STATUS_IRQTOPROC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO6_STATUS_INFROMPAD -// Description : input signal from pad, before filtering and override are -// applied -#define IO_BANK0_GPIO6_STATUS_INFROMPAD_RESET _u(0x0) -#define IO_BANK0_GPIO6_STATUS_INFROMPAD_BITS _u(0x00020000) -#define IO_BANK0_GPIO6_STATUS_INFROMPAD_MSB _u(17) -#define IO_BANK0_GPIO6_STATUS_INFROMPAD_LSB _u(17) -#define IO_BANK0_GPIO6_STATUS_INFROMPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO6_STATUS_OETOPAD -// Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO6_STATUS_OETOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO6_STATUS_OETOPAD_BITS _u(0x00002000) -#define IO_BANK0_GPIO6_STATUS_OETOPAD_MSB _u(13) -#define IO_BANK0_GPIO6_STATUS_OETOPAD_LSB _u(13) -#define IO_BANK0_GPIO6_STATUS_OETOPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO6_STATUS_OUTTOPAD -// Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO6_STATUS_OUTTOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO6_STATUS_OUTTOPAD_BITS _u(0x00000200) -#define IO_BANK0_GPIO6_STATUS_OUTTOPAD_MSB _u(9) -#define IO_BANK0_GPIO6_STATUS_OUTTOPAD_LSB _u(9) -#define IO_BANK0_GPIO6_STATUS_OUTTOPAD_ACCESS "RO" -// ============================================================================= -// Register : IO_BANK0_GPIO6_CTRL -#define IO_BANK0_GPIO6_CTRL_OFFSET _u(0x00000034) -#define IO_BANK0_GPIO6_CTRL_BITS _u(0x3003f01f) -#define IO_BANK0_GPIO6_CTRL_RESET _u(0x0000001f) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO6_CTRL_IRQOVER -// 0x0 -> don't invert the interrupt -// 0x1 -> invert the interrupt -// 0x2 -> drive interrupt low -// 0x3 -> drive interrupt high -#define IO_BANK0_GPIO6_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO6_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO6_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO6_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO6_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO6_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO6_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO6_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO6_CTRL_IRQOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO6_CTRL_INOVER -// 0x0 -> don't invert the peri input -// 0x1 -> invert the peri input -// 0x2 -> drive peri input low -// 0x3 -> drive peri input high -#define IO_BANK0_GPIO6_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO6_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO6_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO6_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO6_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO6_CTRL_INOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO6_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO6_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO6_CTRL_INOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO6_CTRL_OEOVER -// 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel -// 0x2 -> disable output -// 0x3 -> enable output -#define IO_BANK0_GPIO6_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO6_CTRL_OEOVER_BITS _u(0x0000c000) -#define IO_BANK0_GPIO6_CTRL_OEOVER_MSB _u(15) -#define IO_BANK0_GPIO6_CTRL_OEOVER_LSB _u(14) -#define IO_BANK0_GPIO6_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO6_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO6_CTRL_OEOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO6_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO6_CTRL_OEOVER_VALUE_ENABLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO6_CTRL_OUTOVER -// 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel -// 0x2 -> drive output low -// 0x3 -> drive output high -#define IO_BANK0_GPIO6_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO6_CTRL_OUTOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO6_CTRL_OUTOVER_MSB _u(13) -#define IO_BANK0_GPIO6_CTRL_OUTOVER_LSB _u(12) -#define IO_BANK0_GPIO6_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO6_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO6_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO6_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO6_CTRL_OUTOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO6_CTRL_FUNCSEL -// Description : 0-31 -> selects pin function according to the gpio table -// 31 == NULL -// 0x01 -> spi0_sclk -// 0x02 -> uart1_cts -// 0x03 -> i2c1_sda -// 0x04 -> pwm_a_3 -// 0x05 -> siob_proc_6 -// 0x06 -> pio0_6 -// 0x07 -> pio1_6 -// 0x08 -> pio2_6 -// 0x0a -> usb_muxing_overcurr_detect -// 0x0b -> uart1_tx -// 0x1f -> null -#define IO_BANK0_GPIO6_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO6_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO6_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO6_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO6_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_SPI0_SCLK _u(0x01) -#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_UART1_CTS _u(0x02) -#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03) -#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_PWM_A_3 _u(0x04) -#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_SIOB_PROC_6 _u(0x05) -#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_PIO0_6 _u(0x06) -#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_PIO1_6 _u(0x07) -#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_PIO2_6 _u(0x08) -#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x0a) -#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_UART1_TX _u(0x0b) -#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) -// ============================================================================= -// Register : IO_BANK0_GPIO7_STATUS -#define IO_BANK0_GPIO7_STATUS_OFFSET _u(0x00000038) -#define IO_BANK0_GPIO7_STATUS_BITS _u(0x04022200) -#define IO_BANK0_GPIO7_STATUS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO7_STATUS_IRQTOPROC -// Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO7_STATUS_IRQTOPROC_RESET _u(0x0) -#define IO_BANK0_GPIO7_STATUS_IRQTOPROC_BITS _u(0x04000000) -#define IO_BANK0_GPIO7_STATUS_IRQTOPROC_MSB _u(26) -#define IO_BANK0_GPIO7_STATUS_IRQTOPROC_LSB _u(26) -#define IO_BANK0_GPIO7_STATUS_IRQTOPROC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO7_STATUS_INFROMPAD -// Description : input signal from pad, before filtering and override are -// applied -#define IO_BANK0_GPIO7_STATUS_INFROMPAD_RESET _u(0x0) -#define IO_BANK0_GPIO7_STATUS_INFROMPAD_BITS _u(0x00020000) -#define IO_BANK0_GPIO7_STATUS_INFROMPAD_MSB _u(17) -#define IO_BANK0_GPIO7_STATUS_INFROMPAD_LSB _u(17) -#define IO_BANK0_GPIO7_STATUS_INFROMPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO7_STATUS_OETOPAD -// Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO7_STATUS_OETOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO7_STATUS_OETOPAD_BITS _u(0x00002000) -#define IO_BANK0_GPIO7_STATUS_OETOPAD_MSB _u(13) -#define IO_BANK0_GPIO7_STATUS_OETOPAD_LSB _u(13) -#define IO_BANK0_GPIO7_STATUS_OETOPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO7_STATUS_OUTTOPAD -// Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO7_STATUS_OUTTOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO7_STATUS_OUTTOPAD_BITS _u(0x00000200) -#define IO_BANK0_GPIO7_STATUS_OUTTOPAD_MSB _u(9) -#define IO_BANK0_GPIO7_STATUS_OUTTOPAD_LSB _u(9) -#define IO_BANK0_GPIO7_STATUS_OUTTOPAD_ACCESS "RO" -// ============================================================================= -// Register : IO_BANK0_GPIO7_CTRL -#define IO_BANK0_GPIO7_CTRL_OFFSET _u(0x0000003c) -#define IO_BANK0_GPIO7_CTRL_BITS _u(0x3003f01f) -#define IO_BANK0_GPIO7_CTRL_RESET _u(0x0000001f) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO7_CTRL_IRQOVER -// 0x0 -> don't invert the interrupt -// 0x1 -> invert the interrupt -// 0x2 -> drive interrupt low -// 0x3 -> drive interrupt high -#define IO_BANK0_GPIO7_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO7_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO7_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO7_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO7_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO7_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO7_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO7_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO7_CTRL_IRQOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO7_CTRL_INOVER -// 0x0 -> don't invert the peri input -// 0x1 -> invert the peri input -// 0x2 -> drive peri input low -// 0x3 -> drive peri input high -#define IO_BANK0_GPIO7_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO7_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO7_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO7_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO7_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO7_CTRL_INOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO7_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO7_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO7_CTRL_INOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO7_CTRL_OEOVER -// 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel -// 0x2 -> disable output -// 0x3 -> enable output -#define IO_BANK0_GPIO7_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO7_CTRL_OEOVER_BITS _u(0x0000c000) -#define IO_BANK0_GPIO7_CTRL_OEOVER_MSB _u(15) -#define IO_BANK0_GPIO7_CTRL_OEOVER_LSB _u(14) -#define IO_BANK0_GPIO7_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO7_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO7_CTRL_OEOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO7_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO7_CTRL_OEOVER_VALUE_ENABLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO7_CTRL_OUTOVER -// 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel -// 0x2 -> drive output low -// 0x3 -> drive output high -#define IO_BANK0_GPIO7_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO7_CTRL_OUTOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO7_CTRL_OUTOVER_MSB _u(13) -#define IO_BANK0_GPIO7_CTRL_OUTOVER_LSB _u(12) -#define IO_BANK0_GPIO7_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO7_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO7_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO7_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO7_CTRL_OUTOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO7_CTRL_FUNCSEL -// Description : 0-31 -> selects pin function according to the gpio table -// 31 == NULL -// 0x01 -> spi0_tx -// 0x02 -> uart1_rts -// 0x03 -> i2c1_scl -// 0x04 -> pwm_b_3 -// 0x05 -> siob_proc_7 -// 0x06 -> pio0_7 -// 0x07 -> pio1_7 -// 0x08 -> pio2_7 -// 0x0a -> usb_muxing_vbus_detect -// 0x0b -> uart1_rx -// 0x1f -> null -#define IO_BANK0_GPIO7_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO7_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO7_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO7_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO7_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_SPI0_TX _u(0x01) -#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_UART1_RTS _u(0x02) -#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03) -#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_PWM_B_3 _u(0x04) -#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_SIOB_PROC_7 _u(0x05) -#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_PIO0_7 _u(0x06) -#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_PIO1_7 _u(0x07) -#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_PIO2_7 _u(0x08) -#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x0a) -#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_UART1_RX _u(0x0b) -#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) -// ============================================================================= -// Register : IO_BANK0_GPIO8_STATUS -#define IO_BANK0_GPIO8_STATUS_OFFSET _u(0x00000040) -#define IO_BANK0_GPIO8_STATUS_BITS _u(0x04022200) -#define IO_BANK0_GPIO8_STATUS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO8_STATUS_IRQTOPROC -// Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO8_STATUS_IRQTOPROC_RESET _u(0x0) -#define IO_BANK0_GPIO8_STATUS_IRQTOPROC_BITS _u(0x04000000) -#define IO_BANK0_GPIO8_STATUS_IRQTOPROC_MSB _u(26) -#define IO_BANK0_GPIO8_STATUS_IRQTOPROC_LSB _u(26) -#define IO_BANK0_GPIO8_STATUS_IRQTOPROC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO8_STATUS_INFROMPAD -// Description : input signal from pad, before filtering and override are -// applied -#define IO_BANK0_GPIO8_STATUS_INFROMPAD_RESET _u(0x0) -#define IO_BANK0_GPIO8_STATUS_INFROMPAD_BITS _u(0x00020000) -#define IO_BANK0_GPIO8_STATUS_INFROMPAD_MSB _u(17) -#define IO_BANK0_GPIO8_STATUS_INFROMPAD_LSB _u(17) -#define IO_BANK0_GPIO8_STATUS_INFROMPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO8_STATUS_OETOPAD -// Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO8_STATUS_OETOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO8_STATUS_OETOPAD_BITS _u(0x00002000) -#define IO_BANK0_GPIO8_STATUS_OETOPAD_MSB _u(13) -#define IO_BANK0_GPIO8_STATUS_OETOPAD_LSB _u(13) -#define IO_BANK0_GPIO8_STATUS_OETOPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO8_STATUS_OUTTOPAD -// Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO8_STATUS_OUTTOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO8_STATUS_OUTTOPAD_BITS _u(0x00000200) -#define IO_BANK0_GPIO8_STATUS_OUTTOPAD_MSB _u(9) -#define IO_BANK0_GPIO8_STATUS_OUTTOPAD_LSB _u(9) -#define IO_BANK0_GPIO8_STATUS_OUTTOPAD_ACCESS "RO" -// ============================================================================= -// Register : IO_BANK0_GPIO8_CTRL -#define IO_BANK0_GPIO8_CTRL_OFFSET _u(0x00000044) -#define IO_BANK0_GPIO8_CTRL_BITS _u(0x3003f01f) -#define IO_BANK0_GPIO8_CTRL_RESET _u(0x0000001f) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO8_CTRL_IRQOVER -// 0x0 -> don't invert the interrupt -// 0x1 -> invert the interrupt -// 0x2 -> drive interrupt low -// 0x3 -> drive interrupt high -#define IO_BANK0_GPIO8_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO8_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO8_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO8_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO8_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO8_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO8_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO8_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO8_CTRL_IRQOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO8_CTRL_INOVER -// 0x0 -> don't invert the peri input -// 0x1 -> invert the peri input -// 0x2 -> drive peri input low -// 0x3 -> drive peri input high -#define IO_BANK0_GPIO8_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO8_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO8_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO8_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO8_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO8_CTRL_INOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO8_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO8_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO8_CTRL_INOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO8_CTRL_OEOVER -// 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel -// 0x2 -> disable output -// 0x3 -> enable output -#define IO_BANK0_GPIO8_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO8_CTRL_OEOVER_BITS _u(0x0000c000) -#define IO_BANK0_GPIO8_CTRL_OEOVER_MSB _u(15) -#define IO_BANK0_GPIO8_CTRL_OEOVER_LSB _u(14) -#define IO_BANK0_GPIO8_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO8_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO8_CTRL_OEOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO8_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO8_CTRL_OEOVER_VALUE_ENABLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO8_CTRL_OUTOVER -// 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel -// 0x2 -> drive output low -// 0x3 -> drive output high -#define IO_BANK0_GPIO8_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO8_CTRL_OUTOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO8_CTRL_OUTOVER_MSB _u(13) -#define IO_BANK0_GPIO8_CTRL_OUTOVER_LSB _u(12) -#define IO_BANK0_GPIO8_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO8_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO8_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO8_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO8_CTRL_OUTOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO8_CTRL_FUNCSEL -// Description : 0-31 -> selects pin function according to the gpio table -// 31 == NULL -// 0x01 -> spi1_rx -// 0x02 -> uart1_tx -// 0x03 -> i2c0_sda -// 0x04 -> pwm_a_4 -// 0x05 -> siob_proc_8 -// 0x06 -> pio0_8 -// 0x07 -> pio1_8 -// 0x08 -> pio2_8 -// 0x09 -> xip_ss_n_1 -// 0x0a -> usb_muxing_vbus_en -// 0x1f -> null -#define IO_BANK0_GPIO8_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO8_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO8_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO8_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO8_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_SPI1_RX _u(0x01) -#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_UART1_TX _u(0x02) -#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03) -#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_PWM_A_4 _u(0x04) -#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_SIOB_PROC_8 _u(0x05) -#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_PIO0_8 _u(0x06) -#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_PIO1_8 _u(0x07) -#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_PIO2_8 _u(0x08) -#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_XIP_SS_N_1 _u(0x09) -#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x0a) -#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) -// ============================================================================= -// Register : IO_BANK0_GPIO9_STATUS -#define IO_BANK0_GPIO9_STATUS_OFFSET _u(0x00000048) -#define IO_BANK0_GPIO9_STATUS_BITS _u(0x04022200) -#define IO_BANK0_GPIO9_STATUS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO9_STATUS_IRQTOPROC -// Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO9_STATUS_IRQTOPROC_RESET _u(0x0) -#define IO_BANK0_GPIO9_STATUS_IRQTOPROC_BITS _u(0x04000000) -#define IO_BANK0_GPIO9_STATUS_IRQTOPROC_MSB _u(26) -#define IO_BANK0_GPIO9_STATUS_IRQTOPROC_LSB _u(26) -#define IO_BANK0_GPIO9_STATUS_IRQTOPROC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO9_STATUS_INFROMPAD -// Description : input signal from pad, before filtering and override are -// applied -#define IO_BANK0_GPIO9_STATUS_INFROMPAD_RESET _u(0x0) -#define IO_BANK0_GPIO9_STATUS_INFROMPAD_BITS _u(0x00020000) -#define IO_BANK0_GPIO9_STATUS_INFROMPAD_MSB _u(17) -#define IO_BANK0_GPIO9_STATUS_INFROMPAD_LSB _u(17) -#define IO_BANK0_GPIO9_STATUS_INFROMPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO9_STATUS_OETOPAD -// Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO9_STATUS_OETOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO9_STATUS_OETOPAD_BITS _u(0x00002000) -#define IO_BANK0_GPIO9_STATUS_OETOPAD_MSB _u(13) -#define IO_BANK0_GPIO9_STATUS_OETOPAD_LSB _u(13) -#define IO_BANK0_GPIO9_STATUS_OETOPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO9_STATUS_OUTTOPAD -// Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO9_STATUS_OUTTOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO9_STATUS_OUTTOPAD_BITS _u(0x00000200) -#define IO_BANK0_GPIO9_STATUS_OUTTOPAD_MSB _u(9) -#define IO_BANK0_GPIO9_STATUS_OUTTOPAD_LSB _u(9) -#define IO_BANK0_GPIO9_STATUS_OUTTOPAD_ACCESS "RO" -// ============================================================================= -// Register : IO_BANK0_GPIO9_CTRL -#define IO_BANK0_GPIO9_CTRL_OFFSET _u(0x0000004c) -#define IO_BANK0_GPIO9_CTRL_BITS _u(0x3003f01f) -#define IO_BANK0_GPIO9_CTRL_RESET _u(0x0000001f) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO9_CTRL_IRQOVER -// 0x0 -> don't invert the interrupt -// 0x1 -> invert the interrupt -// 0x2 -> drive interrupt low -// 0x3 -> drive interrupt high -#define IO_BANK0_GPIO9_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO9_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO9_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO9_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO9_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO9_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO9_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO9_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO9_CTRL_IRQOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO9_CTRL_INOVER -// 0x0 -> don't invert the peri input -// 0x1 -> invert the peri input -// 0x2 -> drive peri input low -// 0x3 -> drive peri input high -#define IO_BANK0_GPIO9_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO9_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO9_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO9_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO9_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO9_CTRL_INOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO9_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO9_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO9_CTRL_INOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO9_CTRL_OEOVER -// 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel -// 0x2 -> disable output -// 0x3 -> enable output -#define IO_BANK0_GPIO9_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO9_CTRL_OEOVER_BITS _u(0x0000c000) -#define IO_BANK0_GPIO9_CTRL_OEOVER_MSB _u(15) -#define IO_BANK0_GPIO9_CTRL_OEOVER_LSB _u(14) -#define IO_BANK0_GPIO9_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO9_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO9_CTRL_OEOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO9_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO9_CTRL_OEOVER_VALUE_ENABLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO9_CTRL_OUTOVER -// 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel -// 0x2 -> drive output low -// 0x3 -> drive output high -#define IO_BANK0_GPIO9_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO9_CTRL_OUTOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO9_CTRL_OUTOVER_MSB _u(13) -#define IO_BANK0_GPIO9_CTRL_OUTOVER_LSB _u(12) -#define IO_BANK0_GPIO9_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO9_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO9_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO9_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO9_CTRL_OUTOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO9_CTRL_FUNCSEL -// Description : 0-31 -> selects pin function according to the gpio table -// 31 == NULL -// 0x01 -> spi1_ss_n -// 0x02 -> uart1_rx -// 0x03 -> i2c0_scl -// 0x04 -> pwm_b_4 -// 0x05 -> siob_proc_9 -// 0x06 -> pio0_9 -// 0x07 -> pio1_9 -// 0x08 -> pio2_9 -// 0x0a -> usb_muxing_overcurr_detect -// 0x1f -> null -#define IO_BANK0_GPIO9_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO9_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO9_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO9_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO9_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_SPI1_SS_N _u(0x01) -#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_UART1_RX _u(0x02) -#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03) -#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_PWM_B_4 _u(0x04) -#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_SIOB_PROC_9 _u(0x05) -#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_PIO0_9 _u(0x06) -#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_PIO1_9 _u(0x07) -#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_PIO2_9 _u(0x08) -#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x0a) -#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) -// ============================================================================= -// Register : IO_BANK0_GPIO10_STATUS -#define IO_BANK0_GPIO10_STATUS_OFFSET _u(0x00000050) -#define IO_BANK0_GPIO10_STATUS_BITS _u(0x04022200) -#define IO_BANK0_GPIO10_STATUS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO10_STATUS_IRQTOPROC -// Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO10_STATUS_IRQTOPROC_RESET _u(0x0) -#define IO_BANK0_GPIO10_STATUS_IRQTOPROC_BITS _u(0x04000000) -#define IO_BANK0_GPIO10_STATUS_IRQTOPROC_MSB _u(26) -#define IO_BANK0_GPIO10_STATUS_IRQTOPROC_LSB _u(26) -#define IO_BANK0_GPIO10_STATUS_IRQTOPROC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO10_STATUS_INFROMPAD -// Description : input signal from pad, before filtering and override are -// applied -#define IO_BANK0_GPIO10_STATUS_INFROMPAD_RESET _u(0x0) -#define IO_BANK0_GPIO10_STATUS_INFROMPAD_BITS _u(0x00020000) -#define IO_BANK0_GPIO10_STATUS_INFROMPAD_MSB _u(17) -#define IO_BANK0_GPIO10_STATUS_INFROMPAD_LSB _u(17) -#define IO_BANK0_GPIO10_STATUS_INFROMPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO10_STATUS_OETOPAD -// Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO10_STATUS_OETOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO10_STATUS_OETOPAD_BITS _u(0x00002000) -#define IO_BANK0_GPIO10_STATUS_OETOPAD_MSB _u(13) -#define IO_BANK0_GPIO10_STATUS_OETOPAD_LSB _u(13) -#define IO_BANK0_GPIO10_STATUS_OETOPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO10_STATUS_OUTTOPAD -// Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO10_STATUS_OUTTOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO10_STATUS_OUTTOPAD_BITS _u(0x00000200) -#define IO_BANK0_GPIO10_STATUS_OUTTOPAD_MSB _u(9) -#define IO_BANK0_GPIO10_STATUS_OUTTOPAD_LSB _u(9) -#define IO_BANK0_GPIO10_STATUS_OUTTOPAD_ACCESS "RO" -// ============================================================================= -// Register : IO_BANK0_GPIO10_CTRL -#define IO_BANK0_GPIO10_CTRL_OFFSET _u(0x00000054) -#define IO_BANK0_GPIO10_CTRL_BITS _u(0x3003f01f) -#define IO_BANK0_GPIO10_CTRL_RESET _u(0x0000001f) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO10_CTRL_IRQOVER -// 0x0 -> don't invert the interrupt -// 0x1 -> invert the interrupt -// 0x2 -> drive interrupt low -// 0x3 -> drive interrupt high -#define IO_BANK0_GPIO10_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO10_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO10_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO10_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO10_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO10_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO10_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO10_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO10_CTRL_IRQOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO10_CTRL_INOVER -// 0x0 -> don't invert the peri input -// 0x1 -> invert the peri input -// 0x2 -> drive peri input low -// 0x3 -> drive peri input high -#define IO_BANK0_GPIO10_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO10_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO10_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO10_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO10_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO10_CTRL_INOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO10_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO10_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO10_CTRL_INOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO10_CTRL_OEOVER -// 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel -// 0x2 -> disable output -// 0x3 -> enable output -#define IO_BANK0_GPIO10_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO10_CTRL_OEOVER_BITS _u(0x0000c000) -#define IO_BANK0_GPIO10_CTRL_OEOVER_MSB _u(15) -#define IO_BANK0_GPIO10_CTRL_OEOVER_LSB _u(14) -#define IO_BANK0_GPIO10_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO10_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO10_CTRL_OEOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO10_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO10_CTRL_OEOVER_VALUE_ENABLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO10_CTRL_OUTOVER -// 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel -// 0x2 -> drive output low -// 0x3 -> drive output high -#define IO_BANK0_GPIO10_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO10_CTRL_OUTOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO10_CTRL_OUTOVER_MSB _u(13) -#define IO_BANK0_GPIO10_CTRL_OUTOVER_LSB _u(12) -#define IO_BANK0_GPIO10_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO10_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO10_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO10_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO10_CTRL_OUTOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO10_CTRL_FUNCSEL -// Description : 0-31 -> selects pin function according to the gpio table -// 31 == NULL -// 0x01 -> spi1_sclk -// 0x02 -> uart1_cts -// 0x03 -> i2c1_sda -// 0x04 -> pwm_a_5 -// 0x05 -> siob_proc_10 -// 0x06 -> pio0_10 -// 0x07 -> pio1_10 -// 0x08 -> pio2_10 -// 0x0a -> usb_muxing_vbus_detect -// 0x0b -> uart1_tx -// 0x1f -> null -#define IO_BANK0_GPIO10_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO10_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO10_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO10_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO10_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_SPI1_SCLK _u(0x01) -#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_UART1_CTS _u(0x02) -#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03) -#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_PWM_A_5 _u(0x04) -#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_SIOB_PROC_10 _u(0x05) -#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_PIO0_10 _u(0x06) -#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_PIO1_10 _u(0x07) -#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_PIO2_10 _u(0x08) -#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x0a) -#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_UART1_TX _u(0x0b) -#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) -// ============================================================================= -// Register : IO_BANK0_GPIO11_STATUS -#define IO_BANK0_GPIO11_STATUS_OFFSET _u(0x00000058) -#define IO_BANK0_GPIO11_STATUS_BITS _u(0x04022200) -#define IO_BANK0_GPIO11_STATUS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO11_STATUS_IRQTOPROC -// Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO11_STATUS_IRQTOPROC_RESET _u(0x0) -#define IO_BANK0_GPIO11_STATUS_IRQTOPROC_BITS _u(0x04000000) -#define IO_BANK0_GPIO11_STATUS_IRQTOPROC_MSB _u(26) -#define IO_BANK0_GPIO11_STATUS_IRQTOPROC_LSB _u(26) -#define IO_BANK0_GPIO11_STATUS_IRQTOPROC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO11_STATUS_INFROMPAD -// Description : input signal from pad, before filtering and override are -// applied -#define IO_BANK0_GPIO11_STATUS_INFROMPAD_RESET _u(0x0) -#define IO_BANK0_GPIO11_STATUS_INFROMPAD_BITS _u(0x00020000) -#define IO_BANK0_GPIO11_STATUS_INFROMPAD_MSB _u(17) -#define IO_BANK0_GPIO11_STATUS_INFROMPAD_LSB _u(17) -#define IO_BANK0_GPIO11_STATUS_INFROMPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO11_STATUS_OETOPAD -// Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO11_STATUS_OETOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO11_STATUS_OETOPAD_BITS _u(0x00002000) -#define IO_BANK0_GPIO11_STATUS_OETOPAD_MSB _u(13) -#define IO_BANK0_GPIO11_STATUS_OETOPAD_LSB _u(13) -#define IO_BANK0_GPIO11_STATUS_OETOPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO11_STATUS_OUTTOPAD -// Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO11_STATUS_OUTTOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO11_STATUS_OUTTOPAD_BITS _u(0x00000200) -#define IO_BANK0_GPIO11_STATUS_OUTTOPAD_MSB _u(9) -#define IO_BANK0_GPIO11_STATUS_OUTTOPAD_LSB _u(9) -#define IO_BANK0_GPIO11_STATUS_OUTTOPAD_ACCESS "RO" -// ============================================================================= -// Register : IO_BANK0_GPIO11_CTRL -#define IO_BANK0_GPIO11_CTRL_OFFSET _u(0x0000005c) -#define IO_BANK0_GPIO11_CTRL_BITS _u(0x3003f01f) -#define IO_BANK0_GPIO11_CTRL_RESET _u(0x0000001f) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO11_CTRL_IRQOVER -// 0x0 -> don't invert the interrupt -// 0x1 -> invert the interrupt -// 0x2 -> drive interrupt low -// 0x3 -> drive interrupt high -#define IO_BANK0_GPIO11_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO11_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO11_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO11_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO11_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO11_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO11_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO11_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO11_CTRL_IRQOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO11_CTRL_INOVER -// 0x0 -> don't invert the peri input -// 0x1 -> invert the peri input -// 0x2 -> drive peri input low -// 0x3 -> drive peri input high -#define IO_BANK0_GPIO11_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO11_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO11_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO11_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO11_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO11_CTRL_INOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO11_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO11_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO11_CTRL_INOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO11_CTRL_OEOVER -// 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel -// 0x2 -> disable output -// 0x3 -> enable output -#define IO_BANK0_GPIO11_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO11_CTRL_OEOVER_BITS _u(0x0000c000) -#define IO_BANK0_GPIO11_CTRL_OEOVER_MSB _u(15) -#define IO_BANK0_GPIO11_CTRL_OEOVER_LSB _u(14) -#define IO_BANK0_GPIO11_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO11_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO11_CTRL_OEOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO11_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO11_CTRL_OEOVER_VALUE_ENABLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO11_CTRL_OUTOVER -// 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel -// 0x2 -> drive output low -// 0x3 -> drive output high -#define IO_BANK0_GPIO11_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO11_CTRL_OUTOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO11_CTRL_OUTOVER_MSB _u(13) -#define IO_BANK0_GPIO11_CTRL_OUTOVER_LSB _u(12) -#define IO_BANK0_GPIO11_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO11_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO11_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO11_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO11_CTRL_OUTOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO11_CTRL_FUNCSEL -// Description : 0-31 -> selects pin function according to the gpio table -// 31 == NULL -// 0x01 -> spi1_tx -// 0x02 -> uart1_rts -// 0x03 -> i2c1_scl -// 0x04 -> pwm_b_5 -// 0x05 -> siob_proc_11 -// 0x06 -> pio0_11 -// 0x07 -> pio1_11 -// 0x08 -> pio2_11 -// 0x0a -> usb_muxing_vbus_en -// 0x0b -> uart1_rx -// 0x1f -> null -#define IO_BANK0_GPIO11_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO11_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO11_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO11_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO11_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_SPI1_TX _u(0x01) -#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_UART1_RTS _u(0x02) -#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03) -#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_PWM_B_5 _u(0x04) -#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_SIOB_PROC_11 _u(0x05) -#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_PIO0_11 _u(0x06) -#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_PIO1_11 _u(0x07) -#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_PIO2_11 _u(0x08) -#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x0a) -#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_UART1_RX _u(0x0b) -#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) -// ============================================================================= -// Register : IO_BANK0_GPIO12_STATUS -#define IO_BANK0_GPIO12_STATUS_OFFSET _u(0x00000060) -#define IO_BANK0_GPIO12_STATUS_BITS _u(0x04022200) -#define IO_BANK0_GPIO12_STATUS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO12_STATUS_IRQTOPROC -// Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO12_STATUS_IRQTOPROC_RESET _u(0x0) -#define IO_BANK0_GPIO12_STATUS_IRQTOPROC_BITS _u(0x04000000) -#define IO_BANK0_GPIO12_STATUS_IRQTOPROC_MSB _u(26) -#define IO_BANK0_GPIO12_STATUS_IRQTOPROC_LSB _u(26) -#define IO_BANK0_GPIO12_STATUS_IRQTOPROC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO12_STATUS_INFROMPAD -// Description : input signal from pad, before filtering and override are -// applied -#define IO_BANK0_GPIO12_STATUS_INFROMPAD_RESET _u(0x0) -#define IO_BANK0_GPIO12_STATUS_INFROMPAD_BITS _u(0x00020000) -#define IO_BANK0_GPIO12_STATUS_INFROMPAD_MSB _u(17) -#define IO_BANK0_GPIO12_STATUS_INFROMPAD_LSB _u(17) -#define IO_BANK0_GPIO12_STATUS_INFROMPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO12_STATUS_OETOPAD -// Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO12_STATUS_OETOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO12_STATUS_OETOPAD_BITS _u(0x00002000) -#define IO_BANK0_GPIO12_STATUS_OETOPAD_MSB _u(13) -#define IO_BANK0_GPIO12_STATUS_OETOPAD_LSB _u(13) -#define IO_BANK0_GPIO12_STATUS_OETOPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO12_STATUS_OUTTOPAD -// Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO12_STATUS_OUTTOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO12_STATUS_OUTTOPAD_BITS _u(0x00000200) -#define IO_BANK0_GPIO12_STATUS_OUTTOPAD_MSB _u(9) -#define IO_BANK0_GPIO12_STATUS_OUTTOPAD_LSB _u(9) -#define IO_BANK0_GPIO12_STATUS_OUTTOPAD_ACCESS "RO" -// ============================================================================= -// Register : IO_BANK0_GPIO12_CTRL -#define IO_BANK0_GPIO12_CTRL_OFFSET _u(0x00000064) -#define IO_BANK0_GPIO12_CTRL_BITS _u(0x3003f01f) -#define IO_BANK0_GPIO12_CTRL_RESET _u(0x0000001f) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO12_CTRL_IRQOVER -// 0x0 -> don't invert the interrupt -// 0x1 -> invert the interrupt -// 0x2 -> drive interrupt low -// 0x3 -> drive interrupt high -#define IO_BANK0_GPIO12_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO12_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO12_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO12_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO12_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO12_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO12_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO12_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO12_CTRL_IRQOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO12_CTRL_INOVER -// 0x0 -> don't invert the peri input -// 0x1 -> invert the peri input -// 0x2 -> drive peri input low -// 0x3 -> drive peri input high -#define IO_BANK0_GPIO12_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO12_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO12_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO12_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO12_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO12_CTRL_INOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO12_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO12_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO12_CTRL_INOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO12_CTRL_OEOVER -// 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel -// 0x2 -> disable output -// 0x3 -> enable output -#define IO_BANK0_GPIO12_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO12_CTRL_OEOVER_BITS _u(0x0000c000) -#define IO_BANK0_GPIO12_CTRL_OEOVER_MSB _u(15) -#define IO_BANK0_GPIO12_CTRL_OEOVER_LSB _u(14) -#define IO_BANK0_GPIO12_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO12_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO12_CTRL_OEOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO12_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO12_CTRL_OEOVER_VALUE_ENABLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO12_CTRL_OUTOVER -// 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel -// 0x2 -> drive output low -// 0x3 -> drive output high -#define IO_BANK0_GPIO12_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO12_CTRL_OUTOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO12_CTRL_OUTOVER_MSB _u(13) -#define IO_BANK0_GPIO12_CTRL_OUTOVER_LSB _u(12) -#define IO_BANK0_GPIO12_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO12_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO12_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO12_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO12_CTRL_OUTOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO12_CTRL_FUNCSEL -// Description : 0-31 -> selects pin function according to the gpio table -// 31 == NULL -// 0x00 -> hstx_0 -// 0x01 -> spi1_rx -// 0x02 -> uart0_tx -// 0x03 -> i2c0_sda -// 0x04 -> pwm_a_6 -// 0x05 -> siob_proc_12 -// 0x06 -> pio0_12 -// 0x07 -> pio1_12 -// 0x08 -> pio2_12 -// 0x09 -> clocks_gpin_0 -// 0x0a -> usb_muxing_overcurr_detect -// 0x1f -> null -#define IO_BANK0_GPIO12_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO12_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO12_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO12_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO12_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_HSTX_0 _u(0x00) -#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_SPI1_RX _u(0x01) -#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_UART0_TX _u(0x02) -#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03) -#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_PWM_A_6 _u(0x04) -#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_SIOB_PROC_12 _u(0x05) -#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_PIO0_12 _u(0x06) -#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_PIO1_12 _u(0x07) -#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_PIO2_12 _u(0x08) -#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_CLOCKS_GPIN_0 _u(0x09) -#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x0a) -#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) -// ============================================================================= -// Register : IO_BANK0_GPIO13_STATUS -#define IO_BANK0_GPIO13_STATUS_OFFSET _u(0x00000068) -#define IO_BANK0_GPIO13_STATUS_BITS _u(0x04022200) -#define IO_BANK0_GPIO13_STATUS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO13_STATUS_IRQTOPROC -// Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO13_STATUS_IRQTOPROC_RESET _u(0x0) -#define IO_BANK0_GPIO13_STATUS_IRQTOPROC_BITS _u(0x04000000) -#define IO_BANK0_GPIO13_STATUS_IRQTOPROC_MSB _u(26) -#define IO_BANK0_GPIO13_STATUS_IRQTOPROC_LSB _u(26) -#define IO_BANK0_GPIO13_STATUS_IRQTOPROC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO13_STATUS_INFROMPAD -// Description : input signal from pad, before filtering and override are -// applied -#define IO_BANK0_GPIO13_STATUS_INFROMPAD_RESET _u(0x0) -#define IO_BANK0_GPIO13_STATUS_INFROMPAD_BITS _u(0x00020000) -#define IO_BANK0_GPIO13_STATUS_INFROMPAD_MSB _u(17) -#define IO_BANK0_GPIO13_STATUS_INFROMPAD_LSB _u(17) -#define IO_BANK0_GPIO13_STATUS_INFROMPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO13_STATUS_OETOPAD -// Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO13_STATUS_OETOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO13_STATUS_OETOPAD_BITS _u(0x00002000) -#define IO_BANK0_GPIO13_STATUS_OETOPAD_MSB _u(13) -#define IO_BANK0_GPIO13_STATUS_OETOPAD_LSB _u(13) -#define IO_BANK0_GPIO13_STATUS_OETOPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO13_STATUS_OUTTOPAD -// Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO13_STATUS_OUTTOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO13_STATUS_OUTTOPAD_BITS _u(0x00000200) -#define IO_BANK0_GPIO13_STATUS_OUTTOPAD_MSB _u(9) -#define IO_BANK0_GPIO13_STATUS_OUTTOPAD_LSB _u(9) -#define IO_BANK0_GPIO13_STATUS_OUTTOPAD_ACCESS "RO" -// ============================================================================= -// Register : IO_BANK0_GPIO13_CTRL -#define IO_BANK0_GPIO13_CTRL_OFFSET _u(0x0000006c) -#define IO_BANK0_GPIO13_CTRL_BITS _u(0x3003f01f) -#define IO_BANK0_GPIO13_CTRL_RESET _u(0x0000001f) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO13_CTRL_IRQOVER -// 0x0 -> don't invert the interrupt -// 0x1 -> invert the interrupt -// 0x2 -> drive interrupt low -// 0x3 -> drive interrupt high -#define IO_BANK0_GPIO13_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO13_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO13_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO13_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO13_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO13_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO13_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO13_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO13_CTRL_IRQOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO13_CTRL_INOVER -// 0x0 -> don't invert the peri input -// 0x1 -> invert the peri input -// 0x2 -> drive peri input low -// 0x3 -> drive peri input high -#define IO_BANK0_GPIO13_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO13_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO13_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO13_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO13_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO13_CTRL_INOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO13_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO13_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO13_CTRL_INOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO13_CTRL_OEOVER -// 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel -// 0x2 -> disable output -// 0x3 -> enable output -#define IO_BANK0_GPIO13_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO13_CTRL_OEOVER_BITS _u(0x0000c000) -#define IO_BANK0_GPIO13_CTRL_OEOVER_MSB _u(15) -#define IO_BANK0_GPIO13_CTRL_OEOVER_LSB _u(14) -#define IO_BANK0_GPIO13_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO13_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO13_CTRL_OEOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO13_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO13_CTRL_OEOVER_VALUE_ENABLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO13_CTRL_OUTOVER -// 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel -// 0x2 -> drive output low -// 0x3 -> drive output high -#define IO_BANK0_GPIO13_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO13_CTRL_OUTOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO13_CTRL_OUTOVER_MSB _u(13) -#define IO_BANK0_GPIO13_CTRL_OUTOVER_LSB _u(12) -#define IO_BANK0_GPIO13_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO13_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO13_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO13_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO13_CTRL_OUTOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO13_CTRL_FUNCSEL -// Description : 0-31 -> selects pin function according to the gpio table -// 31 == NULL -// 0x00 -> hstx_1 -// 0x01 -> spi1_ss_n -// 0x02 -> uart0_rx -// 0x03 -> i2c0_scl -// 0x04 -> pwm_b_6 -// 0x05 -> siob_proc_13 -// 0x06 -> pio0_13 -// 0x07 -> pio1_13 -// 0x08 -> pio2_13 -// 0x09 -> clocks_gpout_0 -// 0x0a -> usb_muxing_vbus_detect -// 0x1f -> null -#define IO_BANK0_GPIO13_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO13_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO13_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO13_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO13_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_HSTX_1 _u(0x00) -#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_SPI1_SS_N _u(0x01) -#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_UART0_RX _u(0x02) -#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03) -#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_PWM_B_6 _u(0x04) -#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_SIOB_PROC_13 _u(0x05) -#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_PIO0_13 _u(0x06) -#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_PIO1_13 _u(0x07) -#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_PIO2_13 _u(0x08) -#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_CLOCKS_GPOUT_0 _u(0x09) -#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x0a) -#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) -// ============================================================================= -// Register : IO_BANK0_GPIO14_STATUS -#define IO_BANK0_GPIO14_STATUS_OFFSET _u(0x00000070) -#define IO_BANK0_GPIO14_STATUS_BITS _u(0x04022200) -#define IO_BANK0_GPIO14_STATUS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO14_STATUS_IRQTOPROC -// Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO14_STATUS_IRQTOPROC_RESET _u(0x0) -#define IO_BANK0_GPIO14_STATUS_IRQTOPROC_BITS _u(0x04000000) -#define IO_BANK0_GPIO14_STATUS_IRQTOPROC_MSB _u(26) -#define IO_BANK0_GPIO14_STATUS_IRQTOPROC_LSB _u(26) -#define IO_BANK0_GPIO14_STATUS_IRQTOPROC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO14_STATUS_INFROMPAD -// Description : input signal from pad, before filtering and override are -// applied -#define IO_BANK0_GPIO14_STATUS_INFROMPAD_RESET _u(0x0) -#define IO_BANK0_GPIO14_STATUS_INFROMPAD_BITS _u(0x00020000) -#define IO_BANK0_GPIO14_STATUS_INFROMPAD_MSB _u(17) -#define IO_BANK0_GPIO14_STATUS_INFROMPAD_LSB _u(17) -#define IO_BANK0_GPIO14_STATUS_INFROMPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO14_STATUS_OETOPAD -// Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO14_STATUS_OETOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO14_STATUS_OETOPAD_BITS _u(0x00002000) -#define IO_BANK0_GPIO14_STATUS_OETOPAD_MSB _u(13) -#define IO_BANK0_GPIO14_STATUS_OETOPAD_LSB _u(13) -#define IO_BANK0_GPIO14_STATUS_OETOPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO14_STATUS_OUTTOPAD -// Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO14_STATUS_OUTTOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO14_STATUS_OUTTOPAD_BITS _u(0x00000200) -#define IO_BANK0_GPIO14_STATUS_OUTTOPAD_MSB _u(9) -#define IO_BANK0_GPIO14_STATUS_OUTTOPAD_LSB _u(9) -#define IO_BANK0_GPIO14_STATUS_OUTTOPAD_ACCESS "RO" -// ============================================================================= -// Register : IO_BANK0_GPIO14_CTRL -#define IO_BANK0_GPIO14_CTRL_OFFSET _u(0x00000074) -#define IO_BANK0_GPIO14_CTRL_BITS _u(0x3003f01f) -#define IO_BANK0_GPIO14_CTRL_RESET _u(0x0000001f) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO14_CTRL_IRQOVER -// 0x0 -> don't invert the interrupt -// 0x1 -> invert the interrupt -// 0x2 -> drive interrupt low -// 0x3 -> drive interrupt high -#define IO_BANK0_GPIO14_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO14_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO14_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO14_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO14_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO14_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO14_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO14_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO14_CTRL_IRQOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO14_CTRL_INOVER -// 0x0 -> don't invert the peri input -// 0x1 -> invert the peri input -// 0x2 -> drive peri input low -// 0x3 -> drive peri input high -#define IO_BANK0_GPIO14_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO14_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO14_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO14_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO14_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO14_CTRL_INOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO14_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO14_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO14_CTRL_INOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO14_CTRL_OEOVER -// 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel -// 0x2 -> disable output -// 0x3 -> enable output -#define IO_BANK0_GPIO14_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO14_CTRL_OEOVER_BITS _u(0x0000c000) -#define IO_BANK0_GPIO14_CTRL_OEOVER_MSB _u(15) -#define IO_BANK0_GPIO14_CTRL_OEOVER_LSB _u(14) -#define IO_BANK0_GPIO14_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO14_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO14_CTRL_OEOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO14_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO14_CTRL_OEOVER_VALUE_ENABLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO14_CTRL_OUTOVER -// 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel -// 0x2 -> drive output low -// 0x3 -> drive output high -#define IO_BANK0_GPIO14_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO14_CTRL_OUTOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO14_CTRL_OUTOVER_MSB _u(13) -#define IO_BANK0_GPIO14_CTRL_OUTOVER_LSB _u(12) -#define IO_BANK0_GPIO14_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO14_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO14_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO14_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO14_CTRL_OUTOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO14_CTRL_FUNCSEL -// Description : 0-31 -> selects pin function according to the gpio table -// 31 == NULL -// 0x00 -> hstx_2 -// 0x01 -> spi1_sclk -// 0x02 -> uart0_cts -// 0x03 -> i2c1_sda -// 0x04 -> pwm_a_7 -// 0x05 -> siob_proc_14 -// 0x06 -> pio0_14 -// 0x07 -> pio1_14 -// 0x08 -> pio2_14 -// 0x09 -> clocks_gpin_1 -// 0x0a -> usb_muxing_vbus_en -// 0x0b -> uart0_tx -// 0x1f -> null -#define IO_BANK0_GPIO14_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO14_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO14_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO14_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO14_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_HSTX_2 _u(0x00) -#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_SPI1_SCLK _u(0x01) -#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_UART0_CTS _u(0x02) -#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03) -#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_PWM_A_7 _u(0x04) -#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_SIOB_PROC_14 _u(0x05) -#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_PIO0_14 _u(0x06) -#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_PIO1_14 _u(0x07) -#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_PIO2_14 _u(0x08) -#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_CLOCKS_GPIN_1 _u(0x09) -#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x0a) -#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_UART0_TX _u(0x0b) -#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) -// ============================================================================= -// Register : IO_BANK0_GPIO15_STATUS -#define IO_BANK0_GPIO15_STATUS_OFFSET _u(0x00000078) -#define IO_BANK0_GPIO15_STATUS_BITS _u(0x04022200) -#define IO_BANK0_GPIO15_STATUS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO15_STATUS_IRQTOPROC -// Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO15_STATUS_IRQTOPROC_RESET _u(0x0) -#define IO_BANK0_GPIO15_STATUS_IRQTOPROC_BITS _u(0x04000000) -#define IO_BANK0_GPIO15_STATUS_IRQTOPROC_MSB _u(26) -#define IO_BANK0_GPIO15_STATUS_IRQTOPROC_LSB _u(26) -#define IO_BANK0_GPIO15_STATUS_IRQTOPROC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO15_STATUS_INFROMPAD -// Description : input signal from pad, before filtering and override are -// applied -#define IO_BANK0_GPIO15_STATUS_INFROMPAD_RESET _u(0x0) -#define IO_BANK0_GPIO15_STATUS_INFROMPAD_BITS _u(0x00020000) -#define IO_BANK0_GPIO15_STATUS_INFROMPAD_MSB _u(17) -#define IO_BANK0_GPIO15_STATUS_INFROMPAD_LSB _u(17) -#define IO_BANK0_GPIO15_STATUS_INFROMPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO15_STATUS_OETOPAD -// Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO15_STATUS_OETOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO15_STATUS_OETOPAD_BITS _u(0x00002000) -#define IO_BANK0_GPIO15_STATUS_OETOPAD_MSB _u(13) -#define IO_BANK0_GPIO15_STATUS_OETOPAD_LSB _u(13) -#define IO_BANK0_GPIO15_STATUS_OETOPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO15_STATUS_OUTTOPAD -// Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO15_STATUS_OUTTOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO15_STATUS_OUTTOPAD_BITS _u(0x00000200) -#define IO_BANK0_GPIO15_STATUS_OUTTOPAD_MSB _u(9) -#define IO_BANK0_GPIO15_STATUS_OUTTOPAD_LSB _u(9) -#define IO_BANK0_GPIO15_STATUS_OUTTOPAD_ACCESS "RO" -// ============================================================================= -// Register : IO_BANK0_GPIO15_CTRL -#define IO_BANK0_GPIO15_CTRL_OFFSET _u(0x0000007c) -#define IO_BANK0_GPIO15_CTRL_BITS _u(0x3003f01f) -#define IO_BANK0_GPIO15_CTRL_RESET _u(0x0000001f) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO15_CTRL_IRQOVER -// 0x0 -> don't invert the interrupt -// 0x1 -> invert the interrupt -// 0x2 -> drive interrupt low -// 0x3 -> drive interrupt high -#define IO_BANK0_GPIO15_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO15_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO15_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO15_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO15_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO15_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO15_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO15_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO15_CTRL_IRQOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO15_CTRL_INOVER -// 0x0 -> don't invert the peri input -// 0x1 -> invert the peri input -// 0x2 -> drive peri input low -// 0x3 -> drive peri input high -#define IO_BANK0_GPIO15_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO15_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO15_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO15_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO15_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO15_CTRL_INOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO15_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO15_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO15_CTRL_INOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO15_CTRL_OEOVER -// 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel -// 0x2 -> disable output -// 0x3 -> enable output -#define IO_BANK0_GPIO15_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO15_CTRL_OEOVER_BITS _u(0x0000c000) -#define IO_BANK0_GPIO15_CTRL_OEOVER_MSB _u(15) -#define IO_BANK0_GPIO15_CTRL_OEOVER_LSB _u(14) -#define IO_BANK0_GPIO15_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO15_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO15_CTRL_OEOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO15_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO15_CTRL_OEOVER_VALUE_ENABLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO15_CTRL_OUTOVER -// 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel -// 0x2 -> drive output low -// 0x3 -> drive output high -#define IO_BANK0_GPIO15_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO15_CTRL_OUTOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO15_CTRL_OUTOVER_MSB _u(13) -#define IO_BANK0_GPIO15_CTRL_OUTOVER_LSB _u(12) -#define IO_BANK0_GPIO15_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO15_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO15_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO15_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO15_CTRL_OUTOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO15_CTRL_FUNCSEL -// Description : 0-31 -> selects pin function according to the gpio table -// 31 == NULL -// 0x00 -> hstx_3 -// 0x01 -> spi1_tx -// 0x02 -> uart0_rts -// 0x03 -> i2c1_scl -// 0x04 -> pwm_b_7 -// 0x05 -> siob_proc_15 -// 0x06 -> pio0_15 -// 0x07 -> pio1_15 -// 0x08 -> pio2_15 -// 0x09 -> clocks_gpout_1 -// 0x0a -> usb_muxing_overcurr_detect -// 0x0b -> uart0_rx -// 0x1f -> null -#define IO_BANK0_GPIO15_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO15_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO15_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO15_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO15_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_HSTX_3 _u(0x00) -#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_SPI1_TX _u(0x01) -#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_UART0_RTS _u(0x02) -#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03) -#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_PWM_B_7 _u(0x04) -#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_SIOB_PROC_15 _u(0x05) -#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_PIO0_15 _u(0x06) -#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_PIO1_15 _u(0x07) -#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_PIO2_15 _u(0x08) -#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_CLOCKS_GPOUT_1 _u(0x09) -#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x0a) -#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_UART0_RX _u(0x0b) -#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) -// ============================================================================= -// Register : IO_BANK0_GPIO16_STATUS -#define IO_BANK0_GPIO16_STATUS_OFFSET _u(0x00000080) -#define IO_BANK0_GPIO16_STATUS_BITS _u(0x04022200) -#define IO_BANK0_GPIO16_STATUS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO16_STATUS_IRQTOPROC -// Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO16_STATUS_IRQTOPROC_RESET _u(0x0) -#define IO_BANK0_GPIO16_STATUS_IRQTOPROC_BITS _u(0x04000000) -#define IO_BANK0_GPIO16_STATUS_IRQTOPROC_MSB _u(26) -#define IO_BANK0_GPIO16_STATUS_IRQTOPROC_LSB _u(26) -#define IO_BANK0_GPIO16_STATUS_IRQTOPROC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO16_STATUS_INFROMPAD -// Description : input signal from pad, before filtering and override are -// applied -#define IO_BANK0_GPIO16_STATUS_INFROMPAD_RESET _u(0x0) -#define IO_BANK0_GPIO16_STATUS_INFROMPAD_BITS _u(0x00020000) -#define IO_BANK0_GPIO16_STATUS_INFROMPAD_MSB _u(17) -#define IO_BANK0_GPIO16_STATUS_INFROMPAD_LSB _u(17) -#define IO_BANK0_GPIO16_STATUS_INFROMPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO16_STATUS_OETOPAD -// Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO16_STATUS_OETOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO16_STATUS_OETOPAD_BITS _u(0x00002000) -#define IO_BANK0_GPIO16_STATUS_OETOPAD_MSB _u(13) -#define IO_BANK0_GPIO16_STATUS_OETOPAD_LSB _u(13) -#define IO_BANK0_GPIO16_STATUS_OETOPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO16_STATUS_OUTTOPAD -// Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO16_STATUS_OUTTOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO16_STATUS_OUTTOPAD_BITS _u(0x00000200) -#define IO_BANK0_GPIO16_STATUS_OUTTOPAD_MSB _u(9) -#define IO_BANK0_GPIO16_STATUS_OUTTOPAD_LSB _u(9) -#define IO_BANK0_GPIO16_STATUS_OUTTOPAD_ACCESS "RO" -// ============================================================================= -// Register : IO_BANK0_GPIO16_CTRL -#define IO_BANK0_GPIO16_CTRL_OFFSET _u(0x00000084) -#define IO_BANK0_GPIO16_CTRL_BITS _u(0x3003f01f) -#define IO_BANK0_GPIO16_CTRL_RESET _u(0x0000001f) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO16_CTRL_IRQOVER -// 0x0 -> don't invert the interrupt -// 0x1 -> invert the interrupt -// 0x2 -> drive interrupt low -// 0x3 -> drive interrupt high -#define IO_BANK0_GPIO16_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO16_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO16_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO16_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO16_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO16_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO16_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO16_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO16_CTRL_IRQOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO16_CTRL_INOVER -// 0x0 -> don't invert the peri input -// 0x1 -> invert the peri input -// 0x2 -> drive peri input low -// 0x3 -> drive peri input high -#define IO_BANK0_GPIO16_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO16_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO16_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO16_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO16_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO16_CTRL_INOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO16_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO16_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO16_CTRL_INOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO16_CTRL_OEOVER -// 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel -// 0x2 -> disable output -// 0x3 -> enable output -#define IO_BANK0_GPIO16_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO16_CTRL_OEOVER_BITS _u(0x0000c000) -#define IO_BANK0_GPIO16_CTRL_OEOVER_MSB _u(15) -#define IO_BANK0_GPIO16_CTRL_OEOVER_LSB _u(14) -#define IO_BANK0_GPIO16_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO16_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO16_CTRL_OEOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO16_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO16_CTRL_OEOVER_VALUE_ENABLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO16_CTRL_OUTOVER -// 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel -// 0x2 -> drive output low -// 0x3 -> drive output high -#define IO_BANK0_GPIO16_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO16_CTRL_OUTOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO16_CTRL_OUTOVER_MSB _u(13) -#define IO_BANK0_GPIO16_CTRL_OUTOVER_LSB _u(12) -#define IO_BANK0_GPIO16_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO16_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO16_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO16_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO16_CTRL_OUTOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO16_CTRL_FUNCSEL -// Description : 0-31 -> selects pin function according to the gpio table -// 31 == NULL -// 0x00 -> hstx_4 -// 0x01 -> spi0_rx -// 0x02 -> uart0_tx -// 0x03 -> i2c0_sda -// 0x04 -> pwm_a_0 -// 0x05 -> siob_proc_16 -// 0x06 -> pio0_16 -// 0x07 -> pio1_16 -// 0x08 -> pio2_16 -// 0x0a -> usb_muxing_vbus_detect -// 0x1f -> null -#define IO_BANK0_GPIO16_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO16_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO16_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO16_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO16_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_HSTX_4 _u(0x00) -#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_SPI0_RX _u(0x01) -#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_UART0_TX _u(0x02) -#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03) -#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_PWM_A_0 _u(0x04) -#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_SIOB_PROC_16 _u(0x05) -#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_PIO0_16 _u(0x06) -#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_PIO1_16 _u(0x07) -#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_PIO2_16 _u(0x08) -#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x0a) -#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) -// ============================================================================= -// Register : IO_BANK0_GPIO17_STATUS -#define IO_BANK0_GPIO17_STATUS_OFFSET _u(0x00000088) -#define IO_BANK0_GPIO17_STATUS_BITS _u(0x04022200) -#define IO_BANK0_GPIO17_STATUS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO17_STATUS_IRQTOPROC -// Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO17_STATUS_IRQTOPROC_RESET _u(0x0) -#define IO_BANK0_GPIO17_STATUS_IRQTOPROC_BITS _u(0x04000000) -#define IO_BANK0_GPIO17_STATUS_IRQTOPROC_MSB _u(26) -#define IO_BANK0_GPIO17_STATUS_IRQTOPROC_LSB _u(26) -#define IO_BANK0_GPIO17_STATUS_IRQTOPROC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO17_STATUS_INFROMPAD -// Description : input signal from pad, before filtering and override are -// applied -#define IO_BANK0_GPIO17_STATUS_INFROMPAD_RESET _u(0x0) -#define IO_BANK0_GPIO17_STATUS_INFROMPAD_BITS _u(0x00020000) -#define IO_BANK0_GPIO17_STATUS_INFROMPAD_MSB _u(17) -#define IO_BANK0_GPIO17_STATUS_INFROMPAD_LSB _u(17) -#define IO_BANK0_GPIO17_STATUS_INFROMPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO17_STATUS_OETOPAD -// Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO17_STATUS_OETOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO17_STATUS_OETOPAD_BITS _u(0x00002000) -#define IO_BANK0_GPIO17_STATUS_OETOPAD_MSB _u(13) -#define IO_BANK0_GPIO17_STATUS_OETOPAD_LSB _u(13) -#define IO_BANK0_GPIO17_STATUS_OETOPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO17_STATUS_OUTTOPAD -// Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO17_STATUS_OUTTOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO17_STATUS_OUTTOPAD_BITS _u(0x00000200) -#define IO_BANK0_GPIO17_STATUS_OUTTOPAD_MSB _u(9) -#define IO_BANK0_GPIO17_STATUS_OUTTOPAD_LSB _u(9) -#define IO_BANK0_GPIO17_STATUS_OUTTOPAD_ACCESS "RO" -// ============================================================================= -// Register : IO_BANK0_GPIO17_CTRL -#define IO_BANK0_GPIO17_CTRL_OFFSET _u(0x0000008c) -#define IO_BANK0_GPIO17_CTRL_BITS _u(0x3003f01f) -#define IO_BANK0_GPIO17_CTRL_RESET _u(0x0000001f) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO17_CTRL_IRQOVER -// 0x0 -> don't invert the interrupt -// 0x1 -> invert the interrupt -// 0x2 -> drive interrupt low -// 0x3 -> drive interrupt high -#define IO_BANK0_GPIO17_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO17_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO17_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO17_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO17_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO17_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO17_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO17_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO17_CTRL_IRQOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO17_CTRL_INOVER -// 0x0 -> don't invert the peri input -// 0x1 -> invert the peri input -// 0x2 -> drive peri input low -// 0x3 -> drive peri input high -#define IO_BANK0_GPIO17_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO17_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO17_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO17_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO17_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO17_CTRL_INOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO17_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO17_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO17_CTRL_INOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO17_CTRL_OEOVER -// 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel -// 0x2 -> disable output -// 0x3 -> enable output -#define IO_BANK0_GPIO17_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO17_CTRL_OEOVER_BITS _u(0x0000c000) -#define IO_BANK0_GPIO17_CTRL_OEOVER_MSB _u(15) -#define IO_BANK0_GPIO17_CTRL_OEOVER_LSB _u(14) -#define IO_BANK0_GPIO17_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO17_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO17_CTRL_OEOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO17_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO17_CTRL_OEOVER_VALUE_ENABLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO17_CTRL_OUTOVER -// 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel -// 0x2 -> drive output low -// 0x3 -> drive output high -#define IO_BANK0_GPIO17_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO17_CTRL_OUTOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO17_CTRL_OUTOVER_MSB _u(13) -#define IO_BANK0_GPIO17_CTRL_OUTOVER_LSB _u(12) -#define IO_BANK0_GPIO17_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO17_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO17_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO17_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO17_CTRL_OUTOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO17_CTRL_FUNCSEL -// Description : 0-31 -> selects pin function according to the gpio table -// 31 == NULL -// 0x00 -> hstx_5 -// 0x01 -> spi0_ss_n -// 0x02 -> uart0_rx -// 0x03 -> i2c0_scl -// 0x04 -> pwm_b_0 -// 0x05 -> siob_proc_17 -// 0x06 -> pio0_17 -// 0x07 -> pio1_17 -// 0x08 -> pio2_17 -// 0x0a -> usb_muxing_vbus_en -// 0x1f -> null -#define IO_BANK0_GPIO17_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO17_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO17_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO17_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO17_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_HSTX_5 _u(0x00) -#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_SPI0_SS_N _u(0x01) -#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_UART0_RX _u(0x02) -#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03) -#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_PWM_B_0 _u(0x04) -#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_SIOB_PROC_17 _u(0x05) -#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_PIO0_17 _u(0x06) -#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_PIO1_17 _u(0x07) -#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_PIO2_17 _u(0x08) -#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x0a) -#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) -// ============================================================================= -// Register : IO_BANK0_GPIO18_STATUS -#define IO_BANK0_GPIO18_STATUS_OFFSET _u(0x00000090) -#define IO_BANK0_GPIO18_STATUS_BITS _u(0x04022200) -#define IO_BANK0_GPIO18_STATUS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO18_STATUS_IRQTOPROC -// Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO18_STATUS_IRQTOPROC_RESET _u(0x0) -#define IO_BANK0_GPIO18_STATUS_IRQTOPROC_BITS _u(0x04000000) -#define IO_BANK0_GPIO18_STATUS_IRQTOPROC_MSB _u(26) -#define IO_BANK0_GPIO18_STATUS_IRQTOPROC_LSB _u(26) -#define IO_BANK0_GPIO18_STATUS_IRQTOPROC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO18_STATUS_INFROMPAD -// Description : input signal from pad, before filtering and override are -// applied -#define IO_BANK0_GPIO18_STATUS_INFROMPAD_RESET _u(0x0) -#define IO_BANK0_GPIO18_STATUS_INFROMPAD_BITS _u(0x00020000) -#define IO_BANK0_GPIO18_STATUS_INFROMPAD_MSB _u(17) -#define IO_BANK0_GPIO18_STATUS_INFROMPAD_LSB _u(17) -#define IO_BANK0_GPIO18_STATUS_INFROMPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO18_STATUS_OETOPAD -// Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO18_STATUS_OETOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO18_STATUS_OETOPAD_BITS _u(0x00002000) -#define IO_BANK0_GPIO18_STATUS_OETOPAD_MSB _u(13) -#define IO_BANK0_GPIO18_STATUS_OETOPAD_LSB _u(13) -#define IO_BANK0_GPIO18_STATUS_OETOPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO18_STATUS_OUTTOPAD -// Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO18_STATUS_OUTTOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO18_STATUS_OUTTOPAD_BITS _u(0x00000200) -#define IO_BANK0_GPIO18_STATUS_OUTTOPAD_MSB _u(9) -#define IO_BANK0_GPIO18_STATUS_OUTTOPAD_LSB _u(9) -#define IO_BANK0_GPIO18_STATUS_OUTTOPAD_ACCESS "RO" -// ============================================================================= -// Register : IO_BANK0_GPIO18_CTRL -#define IO_BANK0_GPIO18_CTRL_OFFSET _u(0x00000094) -#define IO_BANK0_GPIO18_CTRL_BITS _u(0x3003f01f) -#define IO_BANK0_GPIO18_CTRL_RESET _u(0x0000001f) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO18_CTRL_IRQOVER -// 0x0 -> don't invert the interrupt -// 0x1 -> invert the interrupt -// 0x2 -> drive interrupt low -// 0x3 -> drive interrupt high -#define IO_BANK0_GPIO18_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO18_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO18_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO18_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO18_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO18_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO18_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO18_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO18_CTRL_IRQOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO18_CTRL_INOVER -// 0x0 -> don't invert the peri input -// 0x1 -> invert the peri input -// 0x2 -> drive peri input low -// 0x3 -> drive peri input high -#define IO_BANK0_GPIO18_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO18_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO18_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO18_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO18_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO18_CTRL_INOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO18_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO18_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO18_CTRL_INOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO18_CTRL_OEOVER -// 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel -// 0x2 -> disable output -// 0x3 -> enable output -#define IO_BANK0_GPIO18_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO18_CTRL_OEOVER_BITS _u(0x0000c000) -#define IO_BANK0_GPIO18_CTRL_OEOVER_MSB _u(15) -#define IO_BANK0_GPIO18_CTRL_OEOVER_LSB _u(14) -#define IO_BANK0_GPIO18_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO18_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO18_CTRL_OEOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO18_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO18_CTRL_OEOVER_VALUE_ENABLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO18_CTRL_OUTOVER -// 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel -// 0x2 -> drive output low -// 0x3 -> drive output high -#define IO_BANK0_GPIO18_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO18_CTRL_OUTOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO18_CTRL_OUTOVER_MSB _u(13) -#define IO_BANK0_GPIO18_CTRL_OUTOVER_LSB _u(12) -#define IO_BANK0_GPIO18_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO18_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO18_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO18_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO18_CTRL_OUTOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO18_CTRL_FUNCSEL -// Description : 0-31 -> selects pin function according to the gpio table -// 31 == NULL -// 0x00 -> hstx_6 -// 0x01 -> spi0_sclk -// 0x02 -> uart0_cts -// 0x03 -> i2c1_sda -// 0x04 -> pwm_a_1 -// 0x05 -> siob_proc_18 -// 0x06 -> pio0_18 -// 0x07 -> pio1_18 -// 0x08 -> pio2_18 -// 0x0a -> usb_muxing_overcurr_detect -// 0x0b -> uart0_tx -// 0x1f -> null -#define IO_BANK0_GPIO18_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO18_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO18_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO18_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO18_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_HSTX_6 _u(0x00) -#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_SPI0_SCLK _u(0x01) -#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_UART0_CTS _u(0x02) -#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03) -#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_PWM_A_1 _u(0x04) -#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_SIOB_PROC_18 _u(0x05) -#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_PIO0_18 _u(0x06) -#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_PIO1_18 _u(0x07) -#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_PIO2_18 _u(0x08) -#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x0a) -#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_UART0_TX _u(0x0b) -#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) -// ============================================================================= -// Register : IO_BANK0_GPIO19_STATUS -#define IO_BANK0_GPIO19_STATUS_OFFSET _u(0x00000098) -#define IO_BANK0_GPIO19_STATUS_BITS _u(0x04022200) -#define IO_BANK0_GPIO19_STATUS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO19_STATUS_IRQTOPROC -// Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO19_STATUS_IRQTOPROC_RESET _u(0x0) -#define IO_BANK0_GPIO19_STATUS_IRQTOPROC_BITS _u(0x04000000) -#define IO_BANK0_GPIO19_STATUS_IRQTOPROC_MSB _u(26) -#define IO_BANK0_GPIO19_STATUS_IRQTOPROC_LSB _u(26) -#define IO_BANK0_GPIO19_STATUS_IRQTOPROC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO19_STATUS_INFROMPAD -// Description : input signal from pad, before filtering and override are -// applied -#define IO_BANK0_GPIO19_STATUS_INFROMPAD_RESET _u(0x0) -#define IO_BANK0_GPIO19_STATUS_INFROMPAD_BITS _u(0x00020000) -#define IO_BANK0_GPIO19_STATUS_INFROMPAD_MSB _u(17) -#define IO_BANK0_GPIO19_STATUS_INFROMPAD_LSB _u(17) -#define IO_BANK0_GPIO19_STATUS_INFROMPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO19_STATUS_OETOPAD -// Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO19_STATUS_OETOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO19_STATUS_OETOPAD_BITS _u(0x00002000) -#define IO_BANK0_GPIO19_STATUS_OETOPAD_MSB _u(13) -#define IO_BANK0_GPIO19_STATUS_OETOPAD_LSB _u(13) -#define IO_BANK0_GPIO19_STATUS_OETOPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO19_STATUS_OUTTOPAD -// Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO19_STATUS_OUTTOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO19_STATUS_OUTTOPAD_BITS _u(0x00000200) -#define IO_BANK0_GPIO19_STATUS_OUTTOPAD_MSB _u(9) -#define IO_BANK0_GPIO19_STATUS_OUTTOPAD_LSB _u(9) -#define IO_BANK0_GPIO19_STATUS_OUTTOPAD_ACCESS "RO" -// ============================================================================= -// Register : IO_BANK0_GPIO19_CTRL -#define IO_BANK0_GPIO19_CTRL_OFFSET _u(0x0000009c) -#define IO_BANK0_GPIO19_CTRL_BITS _u(0x3003f01f) -#define IO_BANK0_GPIO19_CTRL_RESET _u(0x0000001f) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO19_CTRL_IRQOVER -// 0x0 -> don't invert the interrupt -// 0x1 -> invert the interrupt -// 0x2 -> drive interrupt low -// 0x3 -> drive interrupt high -#define IO_BANK0_GPIO19_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO19_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO19_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO19_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO19_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO19_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO19_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO19_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO19_CTRL_IRQOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO19_CTRL_INOVER -// 0x0 -> don't invert the peri input -// 0x1 -> invert the peri input -// 0x2 -> drive peri input low -// 0x3 -> drive peri input high -#define IO_BANK0_GPIO19_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO19_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO19_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO19_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO19_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO19_CTRL_INOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO19_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO19_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO19_CTRL_INOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO19_CTRL_OEOVER -// 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel -// 0x2 -> disable output -// 0x3 -> enable output -#define IO_BANK0_GPIO19_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO19_CTRL_OEOVER_BITS _u(0x0000c000) -#define IO_BANK0_GPIO19_CTRL_OEOVER_MSB _u(15) -#define IO_BANK0_GPIO19_CTRL_OEOVER_LSB _u(14) -#define IO_BANK0_GPIO19_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO19_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO19_CTRL_OEOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO19_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO19_CTRL_OEOVER_VALUE_ENABLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO19_CTRL_OUTOVER -// 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel -// 0x2 -> drive output low -// 0x3 -> drive output high -#define IO_BANK0_GPIO19_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO19_CTRL_OUTOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO19_CTRL_OUTOVER_MSB _u(13) -#define IO_BANK0_GPIO19_CTRL_OUTOVER_LSB _u(12) -#define IO_BANK0_GPIO19_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO19_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO19_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO19_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO19_CTRL_OUTOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO19_CTRL_FUNCSEL -// Description : 0-31 -> selects pin function according to the gpio table -// 31 == NULL -// 0x00 -> hstx_7 -// 0x01 -> spi0_tx -// 0x02 -> uart0_rts -// 0x03 -> i2c1_scl -// 0x04 -> pwm_b_1 -// 0x05 -> siob_proc_19 -// 0x06 -> pio0_19 -// 0x07 -> pio1_19 -// 0x08 -> pio2_19 -// 0x09 -> xip_ss_n_1 -// 0x0a -> usb_muxing_vbus_detect -// 0x0b -> uart0_rx -// 0x1f -> null -#define IO_BANK0_GPIO19_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO19_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO19_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO19_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO19_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_HSTX_7 _u(0x00) -#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_SPI0_TX _u(0x01) -#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_UART0_RTS _u(0x02) -#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03) -#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_PWM_B_1 _u(0x04) -#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_SIOB_PROC_19 _u(0x05) -#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_PIO0_19 _u(0x06) -#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_PIO1_19 _u(0x07) -#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_PIO2_19 _u(0x08) -#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_XIP_SS_N_1 _u(0x09) -#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x0a) -#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_UART0_RX _u(0x0b) -#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) -// ============================================================================= -// Register : IO_BANK0_GPIO20_STATUS -#define IO_BANK0_GPIO20_STATUS_OFFSET _u(0x000000a0) -#define IO_BANK0_GPIO20_STATUS_BITS _u(0x04022200) -#define IO_BANK0_GPIO20_STATUS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO20_STATUS_IRQTOPROC -// Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO20_STATUS_IRQTOPROC_RESET _u(0x0) -#define IO_BANK0_GPIO20_STATUS_IRQTOPROC_BITS _u(0x04000000) -#define IO_BANK0_GPIO20_STATUS_IRQTOPROC_MSB _u(26) -#define IO_BANK0_GPIO20_STATUS_IRQTOPROC_LSB _u(26) -#define IO_BANK0_GPIO20_STATUS_IRQTOPROC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO20_STATUS_INFROMPAD -// Description : input signal from pad, before filtering and override are -// applied -#define IO_BANK0_GPIO20_STATUS_INFROMPAD_RESET _u(0x0) -#define IO_BANK0_GPIO20_STATUS_INFROMPAD_BITS _u(0x00020000) -#define IO_BANK0_GPIO20_STATUS_INFROMPAD_MSB _u(17) -#define IO_BANK0_GPIO20_STATUS_INFROMPAD_LSB _u(17) -#define IO_BANK0_GPIO20_STATUS_INFROMPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO20_STATUS_OETOPAD -// Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO20_STATUS_OETOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO20_STATUS_OETOPAD_BITS _u(0x00002000) -#define IO_BANK0_GPIO20_STATUS_OETOPAD_MSB _u(13) -#define IO_BANK0_GPIO20_STATUS_OETOPAD_LSB _u(13) -#define IO_BANK0_GPIO20_STATUS_OETOPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO20_STATUS_OUTTOPAD -// Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO20_STATUS_OUTTOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO20_STATUS_OUTTOPAD_BITS _u(0x00000200) -#define IO_BANK0_GPIO20_STATUS_OUTTOPAD_MSB _u(9) -#define IO_BANK0_GPIO20_STATUS_OUTTOPAD_LSB _u(9) -#define IO_BANK0_GPIO20_STATUS_OUTTOPAD_ACCESS "RO" -// ============================================================================= -// Register : IO_BANK0_GPIO20_CTRL -#define IO_BANK0_GPIO20_CTRL_OFFSET _u(0x000000a4) -#define IO_BANK0_GPIO20_CTRL_BITS _u(0x3003f01f) -#define IO_BANK0_GPIO20_CTRL_RESET _u(0x0000001f) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO20_CTRL_IRQOVER -// 0x0 -> don't invert the interrupt -// 0x1 -> invert the interrupt -// 0x2 -> drive interrupt low -// 0x3 -> drive interrupt high -#define IO_BANK0_GPIO20_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO20_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO20_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO20_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO20_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO20_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO20_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO20_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO20_CTRL_IRQOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO20_CTRL_INOVER -// 0x0 -> don't invert the peri input -// 0x1 -> invert the peri input -// 0x2 -> drive peri input low -// 0x3 -> drive peri input high -#define IO_BANK0_GPIO20_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO20_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO20_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO20_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO20_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO20_CTRL_INOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO20_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO20_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO20_CTRL_INOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO20_CTRL_OEOVER -// 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel -// 0x2 -> disable output -// 0x3 -> enable output -#define IO_BANK0_GPIO20_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO20_CTRL_OEOVER_BITS _u(0x0000c000) -#define IO_BANK0_GPIO20_CTRL_OEOVER_MSB _u(15) -#define IO_BANK0_GPIO20_CTRL_OEOVER_LSB _u(14) -#define IO_BANK0_GPIO20_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO20_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO20_CTRL_OEOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO20_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO20_CTRL_OEOVER_VALUE_ENABLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO20_CTRL_OUTOVER -// 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel -// 0x2 -> drive output low -// 0x3 -> drive output high -#define IO_BANK0_GPIO20_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO20_CTRL_OUTOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO20_CTRL_OUTOVER_MSB _u(13) -#define IO_BANK0_GPIO20_CTRL_OUTOVER_LSB _u(12) -#define IO_BANK0_GPIO20_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO20_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO20_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO20_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO20_CTRL_OUTOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO20_CTRL_FUNCSEL -// Description : 0-31 -> selects pin function according to the gpio table -// 31 == NULL -// 0x01 -> spi0_rx -// 0x02 -> uart1_tx -// 0x03 -> i2c0_sda -// 0x04 -> pwm_a_2 -// 0x05 -> siob_proc_20 -// 0x06 -> pio0_20 -// 0x07 -> pio1_20 -// 0x08 -> pio2_20 -// 0x09 -> clocks_gpin_0 -// 0x0a -> usb_muxing_vbus_en -// 0x1f -> null -#define IO_BANK0_GPIO20_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO20_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO20_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO20_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO20_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_SPI0_RX _u(0x01) -#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_UART1_TX _u(0x02) -#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03) -#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_PWM_A_2 _u(0x04) -#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_SIOB_PROC_20 _u(0x05) -#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_PIO0_20 _u(0x06) -#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_PIO1_20 _u(0x07) -#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_PIO2_20 _u(0x08) -#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_CLOCKS_GPIN_0 _u(0x09) -#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x0a) -#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) -// ============================================================================= -// Register : IO_BANK0_GPIO21_STATUS -#define IO_BANK0_GPIO21_STATUS_OFFSET _u(0x000000a8) -#define IO_BANK0_GPIO21_STATUS_BITS _u(0x04022200) -#define IO_BANK0_GPIO21_STATUS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO21_STATUS_IRQTOPROC -// Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO21_STATUS_IRQTOPROC_RESET _u(0x0) -#define IO_BANK0_GPIO21_STATUS_IRQTOPROC_BITS _u(0x04000000) -#define IO_BANK0_GPIO21_STATUS_IRQTOPROC_MSB _u(26) -#define IO_BANK0_GPIO21_STATUS_IRQTOPROC_LSB _u(26) -#define IO_BANK0_GPIO21_STATUS_IRQTOPROC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO21_STATUS_INFROMPAD -// Description : input signal from pad, before filtering and override are -// applied -#define IO_BANK0_GPIO21_STATUS_INFROMPAD_RESET _u(0x0) -#define IO_BANK0_GPIO21_STATUS_INFROMPAD_BITS _u(0x00020000) -#define IO_BANK0_GPIO21_STATUS_INFROMPAD_MSB _u(17) -#define IO_BANK0_GPIO21_STATUS_INFROMPAD_LSB _u(17) -#define IO_BANK0_GPIO21_STATUS_INFROMPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO21_STATUS_OETOPAD -// Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO21_STATUS_OETOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO21_STATUS_OETOPAD_BITS _u(0x00002000) -#define IO_BANK0_GPIO21_STATUS_OETOPAD_MSB _u(13) -#define IO_BANK0_GPIO21_STATUS_OETOPAD_LSB _u(13) -#define IO_BANK0_GPIO21_STATUS_OETOPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO21_STATUS_OUTTOPAD -// Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO21_STATUS_OUTTOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO21_STATUS_OUTTOPAD_BITS _u(0x00000200) -#define IO_BANK0_GPIO21_STATUS_OUTTOPAD_MSB _u(9) -#define IO_BANK0_GPIO21_STATUS_OUTTOPAD_LSB _u(9) -#define IO_BANK0_GPIO21_STATUS_OUTTOPAD_ACCESS "RO" -// ============================================================================= -// Register : IO_BANK0_GPIO21_CTRL -#define IO_BANK0_GPIO21_CTRL_OFFSET _u(0x000000ac) -#define IO_BANK0_GPIO21_CTRL_BITS _u(0x3003f01f) -#define IO_BANK0_GPIO21_CTRL_RESET _u(0x0000001f) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO21_CTRL_IRQOVER -// 0x0 -> don't invert the interrupt -// 0x1 -> invert the interrupt -// 0x2 -> drive interrupt low -// 0x3 -> drive interrupt high -#define IO_BANK0_GPIO21_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO21_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO21_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO21_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO21_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO21_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO21_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO21_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO21_CTRL_IRQOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO21_CTRL_INOVER -// 0x0 -> don't invert the peri input -// 0x1 -> invert the peri input -// 0x2 -> drive peri input low -// 0x3 -> drive peri input high -#define IO_BANK0_GPIO21_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO21_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO21_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO21_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO21_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO21_CTRL_INOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO21_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO21_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO21_CTRL_INOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO21_CTRL_OEOVER -// 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel -// 0x2 -> disable output -// 0x3 -> enable output -#define IO_BANK0_GPIO21_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO21_CTRL_OEOVER_BITS _u(0x0000c000) -#define IO_BANK0_GPIO21_CTRL_OEOVER_MSB _u(15) -#define IO_BANK0_GPIO21_CTRL_OEOVER_LSB _u(14) -#define IO_BANK0_GPIO21_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO21_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO21_CTRL_OEOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO21_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO21_CTRL_OEOVER_VALUE_ENABLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO21_CTRL_OUTOVER -// 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel -// 0x2 -> drive output low -// 0x3 -> drive output high -#define IO_BANK0_GPIO21_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO21_CTRL_OUTOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO21_CTRL_OUTOVER_MSB _u(13) -#define IO_BANK0_GPIO21_CTRL_OUTOVER_LSB _u(12) -#define IO_BANK0_GPIO21_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO21_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO21_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO21_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO21_CTRL_OUTOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO21_CTRL_FUNCSEL -// Description : 0-31 -> selects pin function according to the gpio table -// 31 == NULL -// 0x01 -> spi0_ss_n -// 0x02 -> uart1_rx -// 0x03 -> i2c0_scl -// 0x04 -> pwm_b_2 -// 0x05 -> siob_proc_21 -// 0x06 -> pio0_21 -// 0x07 -> pio1_21 -// 0x08 -> pio2_21 -// 0x09 -> clocks_gpout_0 -// 0x0a -> usb_muxing_overcurr_detect -// 0x1f -> null -#define IO_BANK0_GPIO21_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO21_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO21_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO21_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO21_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_SPI0_SS_N _u(0x01) -#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_UART1_RX _u(0x02) -#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03) -#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_PWM_B_2 _u(0x04) -#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_SIOB_PROC_21 _u(0x05) -#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_PIO0_21 _u(0x06) -#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_PIO1_21 _u(0x07) -#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_PIO2_21 _u(0x08) -#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_CLOCKS_GPOUT_0 _u(0x09) -#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x0a) -#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) -// ============================================================================= -// Register : IO_BANK0_GPIO22_STATUS -#define IO_BANK0_GPIO22_STATUS_OFFSET _u(0x000000b0) -#define IO_BANK0_GPIO22_STATUS_BITS _u(0x04022200) -#define IO_BANK0_GPIO22_STATUS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO22_STATUS_IRQTOPROC -// Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO22_STATUS_IRQTOPROC_RESET _u(0x0) -#define IO_BANK0_GPIO22_STATUS_IRQTOPROC_BITS _u(0x04000000) -#define IO_BANK0_GPIO22_STATUS_IRQTOPROC_MSB _u(26) -#define IO_BANK0_GPIO22_STATUS_IRQTOPROC_LSB _u(26) -#define IO_BANK0_GPIO22_STATUS_IRQTOPROC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO22_STATUS_INFROMPAD -// Description : input signal from pad, before filtering and override are -// applied -#define IO_BANK0_GPIO22_STATUS_INFROMPAD_RESET _u(0x0) -#define IO_BANK0_GPIO22_STATUS_INFROMPAD_BITS _u(0x00020000) -#define IO_BANK0_GPIO22_STATUS_INFROMPAD_MSB _u(17) -#define IO_BANK0_GPIO22_STATUS_INFROMPAD_LSB _u(17) -#define IO_BANK0_GPIO22_STATUS_INFROMPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO22_STATUS_OETOPAD -// Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO22_STATUS_OETOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO22_STATUS_OETOPAD_BITS _u(0x00002000) -#define IO_BANK0_GPIO22_STATUS_OETOPAD_MSB _u(13) -#define IO_BANK0_GPIO22_STATUS_OETOPAD_LSB _u(13) -#define IO_BANK0_GPIO22_STATUS_OETOPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO22_STATUS_OUTTOPAD -// Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO22_STATUS_OUTTOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO22_STATUS_OUTTOPAD_BITS _u(0x00000200) -#define IO_BANK0_GPIO22_STATUS_OUTTOPAD_MSB _u(9) -#define IO_BANK0_GPIO22_STATUS_OUTTOPAD_LSB _u(9) -#define IO_BANK0_GPIO22_STATUS_OUTTOPAD_ACCESS "RO" -// ============================================================================= -// Register : IO_BANK0_GPIO22_CTRL -#define IO_BANK0_GPIO22_CTRL_OFFSET _u(0x000000b4) -#define IO_BANK0_GPIO22_CTRL_BITS _u(0x3003f01f) -#define IO_BANK0_GPIO22_CTRL_RESET _u(0x0000001f) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO22_CTRL_IRQOVER -// 0x0 -> don't invert the interrupt -// 0x1 -> invert the interrupt -// 0x2 -> drive interrupt low -// 0x3 -> drive interrupt high -#define IO_BANK0_GPIO22_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO22_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO22_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO22_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO22_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO22_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO22_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO22_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO22_CTRL_IRQOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO22_CTRL_INOVER -// 0x0 -> don't invert the peri input -// 0x1 -> invert the peri input -// 0x2 -> drive peri input low -// 0x3 -> drive peri input high -#define IO_BANK0_GPIO22_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO22_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO22_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO22_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO22_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO22_CTRL_INOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO22_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO22_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO22_CTRL_INOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO22_CTRL_OEOVER -// 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel -// 0x2 -> disable output -// 0x3 -> enable output -#define IO_BANK0_GPIO22_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO22_CTRL_OEOVER_BITS _u(0x0000c000) -#define IO_BANK0_GPIO22_CTRL_OEOVER_MSB _u(15) -#define IO_BANK0_GPIO22_CTRL_OEOVER_LSB _u(14) -#define IO_BANK0_GPIO22_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO22_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO22_CTRL_OEOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO22_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO22_CTRL_OEOVER_VALUE_ENABLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO22_CTRL_OUTOVER -// 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel -// 0x2 -> drive output low -// 0x3 -> drive output high -#define IO_BANK0_GPIO22_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO22_CTRL_OUTOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO22_CTRL_OUTOVER_MSB _u(13) -#define IO_BANK0_GPIO22_CTRL_OUTOVER_LSB _u(12) -#define IO_BANK0_GPIO22_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO22_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO22_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO22_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO22_CTRL_OUTOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO22_CTRL_FUNCSEL -// Description : 0-31 -> selects pin function according to the gpio table -// 31 == NULL -// 0x01 -> spi0_sclk -// 0x02 -> uart1_cts -// 0x03 -> i2c1_sda -// 0x04 -> pwm_a_3 -// 0x05 -> siob_proc_22 -// 0x06 -> pio0_22 -// 0x07 -> pio1_22 -// 0x08 -> pio2_22 -// 0x09 -> clocks_gpin_1 -// 0x0a -> usb_muxing_vbus_detect -// 0x0b -> uart1_tx -// 0x1f -> null -#define IO_BANK0_GPIO22_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO22_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO22_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO22_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO22_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_SPI0_SCLK _u(0x01) -#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_UART1_CTS _u(0x02) -#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03) -#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_PWM_A_3 _u(0x04) -#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_SIOB_PROC_22 _u(0x05) -#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_PIO0_22 _u(0x06) -#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_PIO1_22 _u(0x07) -#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_PIO2_22 _u(0x08) -#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_CLOCKS_GPIN_1 _u(0x09) -#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x0a) -#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_UART1_TX _u(0x0b) -#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) -// ============================================================================= -// Register : IO_BANK0_GPIO23_STATUS -#define IO_BANK0_GPIO23_STATUS_OFFSET _u(0x000000b8) -#define IO_BANK0_GPIO23_STATUS_BITS _u(0x04022200) -#define IO_BANK0_GPIO23_STATUS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO23_STATUS_IRQTOPROC -// Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO23_STATUS_IRQTOPROC_RESET _u(0x0) -#define IO_BANK0_GPIO23_STATUS_IRQTOPROC_BITS _u(0x04000000) -#define IO_BANK0_GPIO23_STATUS_IRQTOPROC_MSB _u(26) -#define IO_BANK0_GPIO23_STATUS_IRQTOPROC_LSB _u(26) -#define IO_BANK0_GPIO23_STATUS_IRQTOPROC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO23_STATUS_INFROMPAD -// Description : input signal from pad, before filtering and override are -// applied -#define IO_BANK0_GPIO23_STATUS_INFROMPAD_RESET _u(0x0) -#define IO_BANK0_GPIO23_STATUS_INFROMPAD_BITS _u(0x00020000) -#define IO_BANK0_GPIO23_STATUS_INFROMPAD_MSB _u(17) -#define IO_BANK0_GPIO23_STATUS_INFROMPAD_LSB _u(17) -#define IO_BANK0_GPIO23_STATUS_INFROMPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO23_STATUS_OETOPAD -// Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO23_STATUS_OETOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO23_STATUS_OETOPAD_BITS _u(0x00002000) -#define IO_BANK0_GPIO23_STATUS_OETOPAD_MSB _u(13) -#define IO_BANK0_GPIO23_STATUS_OETOPAD_LSB _u(13) -#define IO_BANK0_GPIO23_STATUS_OETOPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO23_STATUS_OUTTOPAD -// Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO23_STATUS_OUTTOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO23_STATUS_OUTTOPAD_BITS _u(0x00000200) -#define IO_BANK0_GPIO23_STATUS_OUTTOPAD_MSB _u(9) -#define IO_BANK0_GPIO23_STATUS_OUTTOPAD_LSB _u(9) -#define IO_BANK0_GPIO23_STATUS_OUTTOPAD_ACCESS "RO" -// ============================================================================= -// Register : IO_BANK0_GPIO23_CTRL -#define IO_BANK0_GPIO23_CTRL_OFFSET _u(0x000000bc) -#define IO_BANK0_GPIO23_CTRL_BITS _u(0x3003f01f) -#define IO_BANK0_GPIO23_CTRL_RESET _u(0x0000001f) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO23_CTRL_IRQOVER -// 0x0 -> don't invert the interrupt -// 0x1 -> invert the interrupt -// 0x2 -> drive interrupt low -// 0x3 -> drive interrupt high -#define IO_BANK0_GPIO23_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO23_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO23_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO23_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO23_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO23_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO23_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO23_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO23_CTRL_IRQOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO23_CTRL_INOVER -// 0x0 -> don't invert the peri input -// 0x1 -> invert the peri input -// 0x2 -> drive peri input low -// 0x3 -> drive peri input high -#define IO_BANK0_GPIO23_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO23_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO23_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO23_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO23_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO23_CTRL_INOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO23_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO23_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO23_CTRL_INOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO23_CTRL_OEOVER -// 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel -// 0x2 -> disable output -// 0x3 -> enable output -#define IO_BANK0_GPIO23_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO23_CTRL_OEOVER_BITS _u(0x0000c000) -#define IO_BANK0_GPIO23_CTRL_OEOVER_MSB _u(15) -#define IO_BANK0_GPIO23_CTRL_OEOVER_LSB _u(14) -#define IO_BANK0_GPIO23_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO23_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO23_CTRL_OEOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO23_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO23_CTRL_OEOVER_VALUE_ENABLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO23_CTRL_OUTOVER -// 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel -// 0x2 -> drive output low -// 0x3 -> drive output high -#define IO_BANK0_GPIO23_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO23_CTRL_OUTOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO23_CTRL_OUTOVER_MSB _u(13) -#define IO_BANK0_GPIO23_CTRL_OUTOVER_LSB _u(12) -#define IO_BANK0_GPIO23_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO23_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO23_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO23_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO23_CTRL_OUTOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO23_CTRL_FUNCSEL -// Description : 0-31 -> selects pin function according to the gpio table -// 31 == NULL -// 0x01 -> spi0_tx -// 0x02 -> uart1_rts -// 0x03 -> i2c1_scl -// 0x04 -> pwm_b_3 -// 0x05 -> siob_proc_23 -// 0x06 -> pio0_23 -// 0x07 -> pio1_23 -// 0x08 -> pio2_23 -// 0x09 -> clocks_gpout_1 -// 0x0a -> usb_muxing_vbus_en -// 0x0b -> uart1_rx -// 0x1f -> null -#define IO_BANK0_GPIO23_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO23_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO23_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO23_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO23_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_SPI0_TX _u(0x01) -#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_UART1_RTS _u(0x02) -#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03) -#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_PWM_B_3 _u(0x04) -#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_SIOB_PROC_23 _u(0x05) -#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_PIO0_23 _u(0x06) -#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_PIO1_23 _u(0x07) -#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_PIO2_23 _u(0x08) -#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_CLOCKS_GPOUT_1 _u(0x09) -#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x0a) -#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_UART1_RX _u(0x0b) -#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) -// ============================================================================= -// Register : IO_BANK0_GPIO24_STATUS -#define IO_BANK0_GPIO24_STATUS_OFFSET _u(0x000000c0) -#define IO_BANK0_GPIO24_STATUS_BITS _u(0x04022200) -#define IO_BANK0_GPIO24_STATUS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO24_STATUS_IRQTOPROC -// Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO24_STATUS_IRQTOPROC_RESET _u(0x0) -#define IO_BANK0_GPIO24_STATUS_IRQTOPROC_BITS _u(0x04000000) -#define IO_BANK0_GPIO24_STATUS_IRQTOPROC_MSB _u(26) -#define IO_BANK0_GPIO24_STATUS_IRQTOPROC_LSB _u(26) -#define IO_BANK0_GPIO24_STATUS_IRQTOPROC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO24_STATUS_INFROMPAD -// Description : input signal from pad, before filtering and override are -// applied -#define IO_BANK0_GPIO24_STATUS_INFROMPAD_RESET _u(0x0) -#define IO_BANK0_GPIO24_STATUS_INFROMPAD_BITS _u(0x00020000) -#define IO_BANK0_GPIO24_STATUS_INFROMPAD_MSB _u(17) -#define IO_BANK0_GPIO24_STATUS_INFROMPAD_LSB _u(17) -#define IO_BANK0_GPIO24_STATUS_INFROMPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO24_STATUS_OETOPAD -// Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO24_STATUS_OETOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO24_STATUS_OETOPAD_BITS _u(0x00002000) -#define IO_BANK0_GPIO24_STATUS_OETOPAD_MSB _u(13) -#define IO_BANK0_GPIO24_STATUS_OETOPAD_LSB _u(13) -#define IO_BANK0_GPIO24_STATUS_OETOPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO24_STATUS_OUTTOPAD -// Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO24_STATUS_OUTTOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO24_STATUS_OUTTOPAD_BITS _u(0x00000200) -#define IO_BANK0_GPIO24_STATUS_OUTTOPAD_MSB _u(9) -#define IO_BANK0_GPIO24_STATUS_OUTTOPAD_LSB _u(9) -#define IO_BANK0_GPIO24_STATUS_OUTTOPAD_ACCESS "RO" -// ============================================================================= -// Register : IO_BANK0_GPIO24_CTRL -#define IO_BANK0_GPIO24_CTRL_OFFSET _u(0x000000c4) -#define IO_BANK0_GPIO24_CTRL_BITS _u(0x3003f01f) -#define IO_BANK0_GPIO24_CTRL_RESET _u(0x0000001f) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO24_CTRL_IRQOVER -// 0x0 -> don't invert the interrupt -// 0x1 -> invert the interrupt -// 0x2 -> drive interrupt low -// 0x3 -> drive interrupt high -#define IO_BANK0_GPIO24_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO24_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO24_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO24_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO24_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO24_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO24_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO24_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO24_CTRL_IRQOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO24_CTRL_INOVER -// 0x0 -> don't invert the peri input -// 0x1 -> invert the peri input -// 0x2 -> drive peri input low -// 0x3 -> drive peri input high -#define IO_BANK0_GPIO24_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO24_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO24_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO24_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO24_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO24_CTRL_INOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO24_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO24_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO24_CTRL_INOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO24_CTRL_OEOVER -// 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel -// 0x2 -> disable output -// 0x3 -> enable output -#define IO_BANK0_GPIO24_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO24_CTRL_OEOVER_BITS _u(0x0000c000) -#define IO_BANK0_GPIO24_CTRL_OEOVER_MSB _u(15) -#define IO_BANK0_GPIO24_CTRL_OEOVER_LSB _u(14) -#define IO_BANK0_GPIO24_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO24_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO24_CTRL_OEOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO24_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO24_CTRL_OEOVER_VALUE_ENABLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO24_CTRL_OUTOVER -// 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel -// 0x2 -> drive output low -// 0x3 -> drive output high -#define IO_BANK0_GPIO24_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO24_CTRL_OUTOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO24_CTRL_OUTOVER_MSB _u(13) -#define IO_BANK0_GPIO24_CTRL_OUTOVER_LSB _u(12) -#define IO_BANK0_GPIO24_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO24_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO24_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO24_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO24_CTRL_OUTOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO24_CTRL_FUNCSEL -// Description : 0-31 -> selects pin function according to the gpio table -// 31 == NULL -// 0x01 -> spi1_rx -// 0x02 -> uart1_tx -// 0x03 -> i2c0_sda -// 0x04 -> pwm_a_4 -// 0x05 -> siob_proc_24 -// 0x06 -> pio0_24 -// 0x07 -> pio1_24 -// 0x08 -> pio2_24 -// 0x09 -> clocks_gpout_2 -// 0x0a -> usb_muxing_overcurr_detect -// 0x1f -> null -#define IO_BANK0_GPIO24_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO24_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO24_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO24_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO24_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_SPI1_RX _u(0x01) -#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_UART1_TX _u(0x02) -#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03) -#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_PWM_A_4 _u(0x04) -#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_SIOB_PROC_24 _u(0x05) -#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_PIO0_24 _u(0x06) -#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_PIO1_24 _u(0x07) -#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_PIO2_24 _u(0x08) -#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_CLOCKS_GPOUT_2 _u(0x09) -#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x0a) -#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) -// ============================================================================= -// Register : IO_BANK0_GPIO25_STATUS -#define IO_BANK0_GPIO25_STATUS_OFFSET _u(0x000000c8) -#define IO_BANK0_GPIO25_STATUS_BITS _u(0x04022200) -#define IO_BANK0_GPIO25_STATUS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO25_STATUS_IRQTOPROC -// Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO25_STATUS_IRQTOPROC_RESET _u(0x0) -#define IO_BANK0_GPIO25_STATUS_IRQTOPROC_BITS _u(0x04000000) -#define IO_BANK0_GPIO25_STATUS_IRQTOPROC_MSB _u(26) -#define IO_BANK0_GPIO25_STATUS_IRQTOPROC_LSB _u(26) -#define IO_BANK0_GPIO25_STATUS_IRQTOPROC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO25_STATUS_INFROMPAD -// Description : input signal from pad, before filtering and override are -// applied -#define IO_BANK0_GPIO25_STATUS_INFROMPAD_RESET _u(0x0) -#define IO_BANK0_GPIO25_STATUS_INFROMPAD_BITS _u(0x00020000) -#define IO_BANK0_GPIO25_STATUS_INFROMPAD_MSB _u(17) -#define IO_BANK0_GPIO25_STATUS_INFROMPAD_LSB _u(17) -#define IO_BANK0_GPIO25_STATUS_INFROMPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO25_STATUS_OETOPAD -// Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO25_STATUS_OETOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO25_STATUS_OETOPAD_BITS _u(0x00002000) -#define IO_BANK0_GPIO25_STATUS_OETOPAD_MSB _u(13) -#define IO_BANK0_GPIO25_STATUS_OETOPAD_LSB _u(13) -#define IO_BANK0_GPIO25_STATUS_OETOPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO25_STATUS_OUTTOPAD -// Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO25_STATUS_OUTTOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO25_STATUS_OUTTOPAD_BITS _u(0x00000200) -#define IO_BANK0_GPIO25_STATUS_OUTTOPAD_MSB _u(9) -#define IO_BANK0_GPIO25_STATUS_OUTTOPAD_LSB _u(9) -#define IO_BANK0_GPIO25_STATUS_OUTTOPAD_ACCESS "RO" -// ============================================================================= -// Register : IO_BANK0_GPIO25_CTRL -#define IO_BANK0_GPIO25_CTRL_OFFSET _u(0x000000cc) -#define IO_BANK0_GPIO25_CTRL_BITS _u(0x3003f01f) -#define IO_BANK0_GPIO25_CTRL_RESET _u(0x0000001f) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO25_CTRL_IRQOVER -// 0x0 -> don't invert the interrupt -// 0x1 -> invert the interrupt -// 0x2 -> drive interrupt low -// 0x3 -> drive interrupt high -#define IO_BANK0_GPIO25_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO25_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO25_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO25_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO25_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO25_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO25_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO25_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO25_CTRL_IRQOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO25_CTRL_INOVER -// 0x0 -> don't invert the peri input -// 0x1 -> invert the peri input -// 0x2 -> drive peri input low -// 0x3 -> drive peri input high -#define IO_BANK0_GPIO25_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO25_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO25_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO25_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO25_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO25_CTRL_INOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO25_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO25_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO25_CTRL_INOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO25_CTRL_OEOVER -// 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel -// 0x2 -> disable output -// 0x3 -> enable output -#define IO_BANK0_GPIO25_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO25_CTRL_OEOVER_BITS _u(0x0000c000) -#define IO_BANK0_GPIO25_CTRL_OEOVER_MSB _u(15) -#define IO_BANK0_GPIO25_CTRL_OEOVER_LSB _u(14) -#define IO_BANK0_GPIO25_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO25_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO25_CTRL_OEOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO25_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO25_CTRL_OEOVER_VALUE_ENABLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO25_CTRL_OUTOVER -// 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel -// 0x2 -> drive output low -// 0x3 -> drive output high -#define IO_BANK0_GPIO25_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO25_CTRL_OUTOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO25_CTRL_OUTOVER_MSB _u(13) -#define IO_BANK0_GPIO25_CTRL_OUTOVER_LSB _u(12) -#define IO_BANK0_GPIO25_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO25_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO25_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO25_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO25_CTRL_OUTOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO25_CTRL_FUNCSEL -// Description : 0-31 -> selects pin function according to the gpio table -// 31 == NULL -// 0x01 -> spi1_ss_n -// 0x02 -> uart1_rx -// 0x03 -> i2c0_scl -// 0x04 -> pwm_b_4 -// 0x05 -> siob_proc_25 -// 0x06 -> pio0_25 -// 0x07 -> pio1_25 -// 0x08 -> pio2_25 -// 0x09 -> clocks_gpout_3 -// 0x0a -> usb_muxing_vbus_detect -// 0x1f -> null -#define IO_BANK0_GPIO25_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO25_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO25_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO25_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO25_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_SPI1_SS_N _u(0x01) -#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_UART1_RX _u(0x02) -#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03) -#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_PWM_B_4 _u(0x04) -#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_SIOB_PROC_25 _u(0x05) -#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_PIO0_25 _u(0x06) -#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_PIO1_25 _u(0x07) -#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_PIO2_25 _u(0x08) -#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_CLOCKS_GPOUT_3 _u(0x09) -#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x0a) -#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) -// ============================================================================= -// Register : IO_BANK0_GPIO26_STATUS -#define IO_BANK0_GPIO26_STATUS_OFFSET _u(0x000000d0) -#define IO_BANK0_GPIO26_STATUS_BITS _u(0x04022200) -#define IO_BANK0_GPIO26_STATUS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO26_STATUS_IRQTOPROC -// Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO26_STATUS_IRQTOPROC_RESET _u(0x0) -#define IO_BANK0_GPIO26_STATUS_IRQTOPROC_BITS _u(0x04000000) -#define IO_BANK0_GPIO26_STATUS_IRQTOPROC_MSB _u(26) -#define IO_BANK0_GPIO26_STATUS_IRQTOPROC_LSB _u(26) -#define IO_BANK0_GPIO26_STATUS_IRQTOPROC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO26_STATUS_INFROMPAD -// Description : input signal from pad, before filtering and override are -// applied -#define IO_BANK0_GPIO26_STATUS_INFROMPAD_RESET _u(0x0) -#define IO_BANK0_GPIO26_STATUS_INFROMPAD_BITS _u(0x00020000) -#define IO_BANK0_GPIO26_STATUS_INFROMPAD_MSB _u(17) -#define IO_BANK0_GPIO26_STATUS_INFROMPAD_LSB _u(17) -#define IO_BANK0_GPIO26_STATUS_INFROMPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO26_STATUS_OETOPAD -// Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO26_STATUS_OETOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO26_STATUS_OETOPAD_BITS _u(0x00002000) -#define IO_BANK0_GPIO26_STATUS_OETOPAD_MSB _u(13) -#define IO_BANK0_GPIO26_STATUS_OETOPAD_LSB _u(13) -#define IO_BANK0_GPIO26_STATUS_OETOPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO26_STATUS_OUTTOPAD -// Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO26_STATUS_OUTTOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO26_STATUS_OUTTOPAD_BITS _u(0x00000200) -#define IO_BANK0_GPIO26_STATUS_OUTTOPAD_MSB _u(9) -#define IO_BANK0_GPIO26_STATUS_OUTTOPAD_LSB _u(9) -#define IO_BANK0_GPIO26_STATUS_OUTTOPAD_ACCESS "RO" -// ============================================================================= -// Register : IO_BANK0_GPIO26_CTRL -#define IO_BANK0_GPIO26_CTRL_OFFSET _u(0x000000d4) -#define IO_BANK0_GPIO26_CTRL_BITS _u(0x3003f01f) -#define IO_BANK0_GPIO26_CTRL_RESET _u(0x0000001f) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO26_CTRL_IRQOVER -// 0x0 -> don't invert the interrupt -// 0x1 -> invert the interrupt -// 0x2 -> drive interrupt low -// 0x3 -> drive interrupt high -#define IO_BANK0_GPIO26_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO26_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO26_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO26_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO26_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO26_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO26_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO26_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO26_CTRL_IRQOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO26_CTRL_INOVER -// 0x0 -> don't invert the peri input -// 0x1 -> invert the peri input -// 0x2 -> drive peri input low -// 0x3 -> drive peri input high -#define IO_BANK0_GPIO26_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO26_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO26_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO26_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO26_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO26_CTRL_INOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO26_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO26_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO26_CTRL_INOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO26_CTRL_OEOVER -// 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel -// 0x2 -> disable output -// 0x3 -> enable output -#define IO_BANK0_GPIO26_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO26_CTRL_OEOVER_BITS _u(0x0000c000) -#define IO_BANK0_GPIO26_CTRL_OEOVER_MSB _u(15) -#define IO_BANK0_GPIO26_CTRL_OEOVER_LSB _u(14) -#define IO_BANK0_GPIO26_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO26_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO26_CTRL_OEOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO26_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO26_CTRL_OEOVER_VALUE_ENABLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO26_CTRL_OUTOVER -// 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel -// 0x2 -> drive output low -// 0x3 -> drive output high -#define IO_BANK0_GPIO26_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO26_CTRL_OUTOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO26_CTRL_OUTOVER_MSB _u(13) -#define IO_BANK0_GPIO26_CTRL_OUTOVER_LSB _u(12) -#define IO_BANK0_GPIO26_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO26_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO26_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO26_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO26_CTRL_OUTOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO26_CTRL_FUNCSEL -// Description : 0-31 -> selects pin function according to the gpio table -// 31 == NULL -// 0x01 -> spi1_sclk -// 0x02 -> uart1_cts -// 0x03 -> i2c1_sda -// 0x04 -> pwm_a_5 -// 0x05 -> siob_proc_26 -// 0x06 -> pio0_26 -// 0x07 -> pio1_26 -// 0x08 -> pio2_26 -// 0x0a -> usb_muxing_vbus_en -// 0x0b -> uart1_tx -// 0x1f -> null -#define IO_BANK0_GPIO26_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO26_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO26_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO26_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO26_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_SPI1_SCLK _u(0x01) -#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_UART1_CTS _u(0x02) -#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03) -#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_PWM_A_5 _u(0x04) -#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_SIOB_PROC_26 _u(0x05) -#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_PIO0_26 _u(0x06) -#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_PIO1_26 _u(0x07) -#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_PIO2_26 _u(0x08) -#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x0a) -#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_UART1_TX _u(0x0b) -#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) -// ============================================================================= -// Register : IO_BANK0_GPIO27_STATUS -#define IO_BANK0_GPIO27_STATUS_OFFSET _u(0x000000d8) -#define IO_BANK0_GPIO27_STATUS_BITS _u(0x04022200) -#define IO_BANK0_GPIO27_STATUS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO27_STATUS_IRQTOPROC -// Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO27_STATUS_IRQTOPROC_RESET _u(0x0) -#define IO_BANK0_GPIO27_STATUS_IRQTOPROC_BITS _u(0x04000000) -#define IO_BANK0_GPIO27_STATUS_IRQTOPROC_MSB _u(26) -#define IO_BANK0_GPIO27_STATUS_IRQTOPROC_LSB _u(26) -#define IO_BANK0_GPIO27_STATUS_IRQTOPROC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO27_STATUS_INFROMPAD -// Description : input signal from pad, before filtering and override are -// applied -#define IO_BANK0_GPIO27_STATUS_INFROMPAD_RESET _u(0x0) -#define IO_BANK0_GPIO27_STATUS_INFROMPAD_BITS _u(0x00020000) -#define IO_BANK0_GPIO27_STATUS_INFROMPAD_MSB _u(17) -#define IO_BANK0_GPIO27_STATUS_INFROMPAD_LSB _u(17) -#define IO_BANK0_GPIO27_STATUS_INFROMPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO27_STATUS_OETOPAD -// Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO27_STATUS_OETOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO27_STATUS_OETOPAD_BITS _u(0x00002000) -#define IO_BANK0_GPIO27_STATUS_OETOPAD_MSB _u(13) -#define IO_BANK0_GPIO27_STATUS_OETOPAD_LSB _u(13) -#define IO_BANK0_GPIO27_STATUS_OETOPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO27_STATUS_OUTTOPAD -// Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO27_STATUS_OUTTOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO27_STATUS_OUTTOPAD_BITS _u(0x00000200) -#define IO_BANK0_GPIO27_STATUS_OUTTOPAD_MSB _u(9) -#define IO_BANK0_GPIO27_STATUS_OUTTOPAD_LSB _u(9) -#define IO_BANK0_GPIO27_STATUS_OUTTOPAD_ACCESS "RO" -// ============================================================================= -// Register : IO_BANK0_GPIO27_CTRL -#define IO_BANK0_GPIO27_CTRL_OFFSET _u(0x000000dc) -#define IO_BANK0_GPIO27_CTRL_BITS _u(0x3003f01f) -#define IO_BANK0_GPIO27_CTRL_RESET _u(0x0000001f) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO27_CTRL_IRQOVER -// 0x0 -> don't invert the interrupt -// 0x1 -> invert the interrupt -// 0x2 -> drive interrupt low -// 0x3 -> drive interrupt high -#define IO_BANK0_GPIO27_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO27_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO27_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO27_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO27_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO27_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO27_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO27_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO27_CTRL_IRQOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO27_CTRL_INOVER -// 0x0 -> don't invert the peri input -// 0x1 -> invert the peri input -// 0x2 -> drive peri input low -// 0x3 -> drive peri input high -#define IO_BANK0_GPIO27_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO27_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO27_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO27_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO27_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO27_CTRL_INOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO27_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO27_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO27_CTRL_INOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO27_CTRL_OEOVER -// 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel -// 0x2 -> disable output -// 0x3 -> enable output -#define IO_BANK0_GPIO27_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO27_CTRL_OEOVER_BITS _u(0x0000c000) -#define IO_BANK0_GPIO27_CTRL_OEOVER_MSB _u(15) -#define IO_BANK0_GPIO27_CTRL_OEOVER_LSB _u(14) -#define IO_BANK0_GPIO27_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO27_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO27_CTRL_OEOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO27_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO27_CTRL_OEOVER_VALUE_ENABLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO27_CTRL_OUTOVER -// 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel -// 0x2 -> drive output low -// 0x3 -> drive output high -#define IO_BANK0_GPIO27_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO27_CTRL_OUTOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO27_CTRL_OUTOVER_MSB _u(13) -#define IO_BANK0_GPIO27_CTRL_OUTOVER_LSB _u(12) -#define IO_BANK0_GPIO27_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO27_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO27_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO27_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO27_CTRL_OUTOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO27_CTRL_FUNCSEL -// Description : 0-31 -> selects pin function according to the gpio table -// 31 == NULL -// 0x01 -> spi1_tx -// 0x02 -> uart1_rts -// 0x03 -> i2c1_scl -// 0x04 -> pwm_b_5 -// 0x05 -> siob_proc_27 -// 0x06 -> pio0_27 -// 0x07 -> pio1_27 -// 0x08 -> pio2_27 -// 0x0a -> usb_muxing_overcurr_detect -// 0x0b -> uart1_rx -// 0x1f -> null -#define IO_BANK0_GPIO27_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO27_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO27_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO27_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO27_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_SPI1_TX _u(0x01) -#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_UART1_RTS _u(0x02) -#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03) -#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_PWM_B_5 _u(0x04) -#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_SIOB_PROC_27 _u(0x05) -#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_PIO0_27 _u(0x06) -#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_PIO1_27 _u(0x07) -#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_PIO2_27 _u(0x08) -#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x0a) -#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_UART1_RX _u(0x0b) -#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) -// ============================================================================= -// Register : IO_BANK0_GPIO28_STATUS -#define IO_BANK0_GPIO28_STATUS_OFFSET _u(0x000000e0) -#define IO_BANK0_GPIO28_STATUS_BITS _u(0x04022200) -#define IO_BANK0_GPIO28_STATUS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO28_STATUS_IRQTOPROC -// Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO28_STATUS_IRQTOPROC_RESET _u(0x0) -#define IO_BANK0_GPIO28_STATUS_IRQTOPROC_BITS _u(0x04000000) -#define IO_BANK0_GPIO28_STATUS_IRQTOPROC_MSB _u(26) -#define IO_BANK0_GPIO28_STATUS_IRQTOPROC_LSB _u(26) -#define IO_BANK0_GPIO28_STATUS_IRQTOPROC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO28_STATUS_INFROMPAD -// Description : input signal from pad, before filtering and override are -// applied -#define IO_BANK0_GPIO28_STATUS_INFROMPAD_RESET _u(0x0) -#define IO_BANK0_GPIO28_STATUS_INFROMPAD_BITS _u(0x00020000) -#define IO_BANK0_GPIO28_STATUS_INFROMPAD_MSB _u(17) -#define IO_BANK0_GPIO28_STATUS_INFROMPAD_LSB _u(17) -#define IO_BANK0_GPIO28_STATUS_INFROMPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO28_STATUS_OETOPAD -// Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO28_STATUS_OETOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO28_STATUS_OETOPAD_BITS _u(0x00002000) -#define IO_BANK0_GPIO28_STATUS_OETOPAD_MSB _u(13) -#define IO_BANK0_GPIO28_STATUS_OETOPAD_LSB _u(13) -#define IO_BANK0_GPIO28_STATUS_OETOPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO28_STATUS_OUTTOPAD -// Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO28_STATUS_OUTTOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO28_STATUS_OUTTOPAD_BITS _u(0x00000200) -#define IO_BANK0_GPIO28_STATUS_OUTTOPAD_MSB _u(9) -#define IO_BANK0_GPIO28_STATUS_OUTTOPAD_LSB _u(9) -#define IO_BANK0_GPIO28_STATUS_OUTTOPAD_ACCESS "RO" -// ============================================================================= -// Register : IO_BANK0_GPIO28_CTRL -#define IO_BANK0_GPIO28_CTRL_OFFSET _u(0x000000e4) -#define IO_BANK0_GPIO28_CTRL_BITS _u(0x3003f01f) -#define IO_BANK0_GPIO28_CTRL_RESET _u(0x0000001f) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO28_CTRL_IRQOVER -// 0x0 -> don't invert the interrupt -// 0x1 -> invert the interrupt -// 0x2 -> drive interrupt low -// 0x3 -> drive interrupt high -#define IO_BANK0_GPIO28_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO28_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO28_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO28_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO28_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO28_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO28_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO28_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO28_CTRL_IRQOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO28_CTRL_INOVER -// 0x0 -> don't invert the peri input -// 0x1 -> invert the peri input -// 0x2 -> drive peri input low -// 0x3 -> drive peri input high -#define IO_BANK0_GPIO28_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO28_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO28_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO28_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO28_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO28_CTRL_INOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO28_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO28_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO28_CTRL_INOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO28_CTRL_OEOVER -// 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel -// 0x2 -> disable output -// 0x3 -> enable output -#define IO_BANK0_GPIO28_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO28_CTRL_OEOVER_BITS _u(0x0000c000) -#define IO_BANK0_GPIO28_CTRL_OEOVER_MSB _u(15) -#define IO_BANK0_GPIO28_CTRL_OEOVER_LSB _u(14) -#define IO_BANK0_GPIO28_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO28_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO28_CTRL_OEOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO28_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO28_CTRL_OEOVER_VALUE_ENABLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO28_CTRL_OUTOVER -// 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel -// 0x2 -> drive output low -// 0x3 -> drive output high -#define IO_BANK0_GPIO28_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO28_CTRL_OUTOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO28_CTRL_OUTOVER_MSB _u(13) -#define IO_BANK0_GPIO28_CTRL_OUTOVER_LSB _u(12) -#define IO_BANK0_GPIO28_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO28_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO28_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO28_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO28_CTRL_OUTOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO28_CTRL_FUNCSEL -// Description : 0-31 -> selects pin function according to the gpio table -// 31 == NULL -// 0x01 -> spi1_rx -// 0x02 -> uart0_tx -// 0x03 -> i2c0_sda -// 0x04 -> pwm_a_6 -// 0x05 -> siob_proc_28 -// 0x06 -> pio0_28 -// 0x07 -> pio1_28 -// 0x08 -> pio2_28 -// 0x0a -> usb_muxing_vbus_detect -// 0x1f -> null -#define IO_BANK0_GPIO28_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO28_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO28_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO28_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO28_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_SPI1_RX _u(0x01) -#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_UART0_TX _u(0x02) -#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03) -#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_PWM_A_6 _u(0x04) -#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_SIOB_PROC_28 _u(0x05) -#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_PIO0_28 _u(0x06) -#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_PIO1_28 _u(0x07) -#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_PIO2_28 _u(0x08) -#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x0a) -#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) -// ============================================================================= -// Register : IO_BANK0_GPIO29_STATUS -#define IO_BANK0_GPIO29_STATUS_OFFSET _u(0x000000e8) -#define IO_BANK0_GPIO29_STATUS_BITS _u(0x04022200) -#define IO_BANK0_GPIO29_STATUS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO29_STATUS_IRQTOPROC -// Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO29_STATUS_IRQTOPROC_RESET _u(0x0) -#define IO_BANK0_GPIO29_STATUS_IRQTOPROC_BITS _u(0x04000000) -#define IO_BANK0_GPIO29_STATUS_IRQTOPROC_MSB _u(26) -#define IO_BANK0_GPIO29_STATUS_IRQTOPROC_LSB _u(26) -#define IO_BANK0_GPIO29_STATUS_IRQTOPROC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO29_STATUS_INFROMPAD -// Description : input signal from pad, before filtering and override are -// applied -#define IO_BANK0_GPIO29_STATUS_INFROMPAD_RESET _u(0x0) -#define IO_BANK0_GPIO29_STATUS_INFROMPAD_BITS _u(0x00020000) -#define IO_BANK0_GPIO29_STATUS_INFROMPAD_MSB _u(17) -#define IO_BANK0_GPIO29_STATUS_INFROMPAD_LSB _u(17) -#define IO_BANK0_GPIO29_STATUS_INFROMPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO29_STATUS_OETOPAD -// Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO29_STATUS_OETOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO29_STATUS_OETOPAD_BITS _u(0x00002000) -#define IO_BANK0_GPIO29_STATUS_OETOPAD_MSB _u(13) -#define IO_BANK0_GPIO29_STATUS_OETOPAD_LSB _u(13) -#define IO_BANK0_GPIO29_STATUS_OETOPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO29_STATUS_OUTTOPAD -// Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO29_STATUS_OUTTOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO29_STATUS_OUTTOPAD_BITS _u(0x00000200) -#define IO_BANK0_GPIO29_STATUS_OUTTOPAD_MSB _u(9) -#define IO_BANK0_GPIO29_STATUS_OUTTOPAD_LSB _u(9) -#define IO_BANK0_GPIO29_STATUS_OUTTOPAD_ACCESS "RO" -// ============================================================================= -// Register : IO_BANK0_GPIO29_CTRL -#define IO_BANK0_GPIO29_CTRL_OFFSET _u(0x000000ec) -#define IO_BANK0_GPIO29_CTRL_BITS _u(0x3003f01f) -#define IO_BANK0_GPIO29_CTRL_RESET _u(0x0000001f) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO29_CTRL_IRQOVER -// 0x0 -> don't invert the interrupt -// 0x1 -> invert the interrupt -// 0x2 -> drive interrupt low -// 0x3 -> drive interrupt high -#define IO_BANK0_GPIO29_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO29_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO29_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO29_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO29_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO29_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO29_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO29_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO29_CTRL_IRQOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO29_CTRL_INOVER -// 0x0 -> don't invert the peri input -// 0x1 -> invert the peri input -// 0x2 -> drive peri input low -// 0x3 -> drive peri input high -#define IO_BANK0_GPIO29_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO29_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO29_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO29_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO29_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO29_CTRL_INOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO29_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO29_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO29_CTRL_INOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO29_CTRL_OEOVER -// 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel -// 0x2 -> disable output -// 0x3 -> enable output -#define IO_BANK0_GPIO29_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO29_CTRL_OEOVER_BITS _u(0x0000c000) -#define IO_BANK0_GPIO29_CTRL_OEOVER_MSB _u(15) -#define IO_BANK0_GPIO29_CTRL_OEOVER_LSB _u(14) -#define IO_BANK0_GPIO29_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO29_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO29_CTRL_OEOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO29_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO29_CTRL_OEOVER_VALUE_ENABLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO29_CTRL_OUTOVER -// 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel -// 0x2 -> drive output low -// 0x3 -> drive output high -#define IO_BANK0_GPIO29_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO29_CTRL_OUTOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO29_CTRL_OUTOVER_MSB _u(13) -#define IO_BANK0_GPIO29_CTRL_OUTOVER_LSB _u(12) -#define IO_BANK0_GPIO29_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO29_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO29_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO29_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO29_CTRL_OUTOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO29_CTRL_FUNCSEL -// Description : 0-31 -> selects pin function according to the gpio table -// 31 == NULL -// 0x01 -> spi1_ss_n -// 0x02 -> uart0_rx -// 0x03 -> i2c0_scl -// 0x04 -> pwm_b_6 -// 0x05 -> siob_proc_29 -// 0x06 -> pio0_29 -// 0x07 -> pio1_29 -// 0x08 -> pio2_29 -// 0x0a -> usb_muxing_vbus_en -// 0x1f -> null -#define IO_BANK0_GPIO29_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO29_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO29_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO29_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO29_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_SPI1_SS_N _u(0x01) -#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_UART0_RX _u(0x02) -#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03) -#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_PWM_B_6 _u(0x04) -#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_SIOB_PROC_29 _u(0x05) -#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_PIO0_29 _u(0x06) -#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_PIO1_29 _u(0x07) -#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_PIO2_29 _u(0x08) -#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x0a) -#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) -// ============================================================================= -// Register : IO_BANK0_GPIO30_STATUS -#define IO_BANK0_GPIO30_STATUS_OFFSET _u(0x000000f0) -#define IO_BANK0_GPIO30_STATUS_BITS _u(0x04022200) -#define IO_BANK0_GPIO30_STATUS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO30_STATUS_IRQTOPROC -// Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO30_STATUS_IRQTOPROC_RESET _u(0x0) -#define IO_BANK0_GPIO30_STATUS_IRQTOPROC_BITS _u(0x04000000) -#define IO_BANK0_GPIO30_STATUS_IRQTOPROC_MSB _u(26) -#define IO_BANK0_GPIO30_STATUS_IRQTOPROC_LSB _u(26) -#define IO_BANK0_GPIO30_STATUS_IRQTOPROC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO30_STATUS_INFROMPAD -// Description : input signal from pad, before filtering and override are -// applied -#define IO_BANK0_GPIO30_STATUS_INFROMPAD_RESET _u(0x0) -#define IO_BANK0_GPIO30_STATUS_INFROMPAD_BITS _u(0x00020000) -#define IO_BANK0_GPIO30_STATUS_INFROMPAD_MSB _u(17) -#define IO_BANK0_GPIO30_STATUS_INFROMPAD_LSB _u(17) -#define IO_BANK0_GPIO30_STATUS_INFROMPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO30_STATUS_OETOPAD -// Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO30_STATUS_OETOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO30_STATUS_OETOPAD_BITS _u(0x00002000) -#define IO_BANK0_GPIO30_STATUS_OETOPAD_MSB _u(13) -#define IO_BANK0_GPIO30_STATUS_OETOPAD_LSB _u(13) -#define IO_BANK0_GPIO30_STATUS_OETOPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO30_STATUS_OUTTOPAD -// Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO30_STATUS_OUTTOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO30_STATUS_OUTTOPAD_BITS _u(0x00000200) -#define IO_BANK0_GPIO30_STATUS_OUTTOPAD_MSB _u(9) -#define IO_BANK0_GPIO30_STATUS_OUTTOPAD_LSB _u(9) -#define IO_BANK0_GPIO30_STATUS_OUTTOPAD_ACCESS "RO" -// ============================================================================= -// Register : IO_BANK0_GPIO30_CTRL -#define IO_BANK0_GPIO30_CTRL_OFFSET _u(0x000000f4) -#define IO_BANK0_GPIO30_CTRL_BITS _u(0x3003f01f) -#define IO_BANK0_GPIO30_CTRL_RESET _u(0x0000001f) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO30_CTRL_IRQOVER -// 0x0 -> don't invert the interrupt -// 0x1 -> invert the interrupt -// 0x2 -> drive interrupt low -// 0x3 -> drive interrupt high -#define IO_BANK0_GPIO30_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO30_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO30_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO30_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO30_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO30_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO30_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO30_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO30_CTRL_IRQOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO30_CTRL_INOVER -// 0x0 -> don't invert the peri input -// 0x1 -> invert the peri input -// 0x2 -> drive peri input low -// 0x3 -> drive peri input high -#define IO_BANK0_GPIO30_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO30_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO30_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO30_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO30_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO30_CTRL_INOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO30_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO30_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO30_CTRL_INOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO30_CTRL_OEOVER -// 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel -// 0x2 -> disable output -// 0x3 -> enable output -#define IO_BANK0_GPIO30_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO30_CTRL_OEOVER_BITS _u(0x0000c000) -#define IO_BANK0_GPIO30_CTRL_OEOVER_MSB _u(15) -#define IO_BANK0_GPIO30_CTRL_OEOVER_LSB _u(14) -#define IO_BANK0_GPIO30_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO30_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO30_CTRL_OEOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO30_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO30_CTRL_OEOVER_VALUE_ENABLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO30_CTRL_OUTOVER -// 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel -// 0x2 -> drive output low -// 0x3 -> drive output high -#define IO_BANK0_GPIO30_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO30_CTRL_OUTOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO30_CTRL_OUTOVER_MSB _u(13) -#define IO_BANK0_GPIO30_CTRL_OUTOVER_LSB _u(12) -#define IO_BANK0_GPIO30_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO30_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO30_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO30_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO30_CTRL_OUTOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO30_CTRL_FUNCSEL -// Description : 0-31 -> selects pin function according to the gpio table -// 31 == NULL -// 0x01 -> spi1_sclk -// 0x02 -> uart0_cts -// 0x03 -> i2c1_sda -// 0x04 -> pwm_a_7 -// 0x05 -> siob_proc_30 -// 0x06 -> pio0_30 -// 0x07 -> pio1_30 -// 0x08 -> pio2_30 -// 0x0a -> usb_muxing_overcurr_detect -// 0x0b -> uart0_tx -// 0x1f -> null -#define IO_BANK0_GPIO30_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO30_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO30_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO30_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO30_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO30_CTRL_FUNCSEL_VALUE_SPI1_SCLK _u(0x01) -#define IO_BANK0_GPIO30_CTRL_FUNCSEL_VALUE_UART0_CTS _u(0x02) -#define IO_BANK0_GPIO30_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03) -#define IO_BANK0_GPIO30_CTRL_FUNCSEL_VALUE_PWM_A_7 _u(0x04) -#define IO_BANK0_GPIO30_CTRL_FUNCSEL_VALUE_SIOB_PROC_30 _u(0x05) -#define IO_BANK0_GPIO30_CTRL_FUNCSEL_VALUE_PIO0_30 _u(0x06) -#define IO_BANK0_GPIO30_CTRL_FUNCSEL_VALUE_PIO1_30 _u(0x07) -#define IO_BANK0_GPIO30_CTRL_FUNCSEL_VALUE_PIO2_30 _u(0x08) -#define IO_BANK0_GPIO30_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x0a) -#define IO_BANK0_GPIO30_CTRL_FUNCSEL_VALUE_UART0_TX _u(0x0b) -#define IO_BANK0_GPIO30_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) -// ============================================================================= -// Register : IO_BANK0_GPIO31_STATUS -#define IO_BANK0_GPIO31_STATUS_OFFSET _u(0x000000f8) -#define IO_BANK0_GPIO31_STATUS_BITS _u(0x04022200) -#define IO_BANK0_GPIO31_STATUS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO31_STATUS_IRQTOPROC -// Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO31_STATUS_IRQTOPROC_RESET _u(0x0) -#define IO_BANK0_GPIO31_STATUS_IRQTOPROC_BITS _u(0x04000000) -#define IO_BANK0_GPIO31_STATUS_IRQTOPROC_MSB _u(26) -#define IO_BANK0_GPIO31_STATUS_IRQTOPROC_LSB _u(26) -#define IO_BANK0_GPIO31_STATUS_IRQTOPROC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO31_STATUS_INFROMPAD -// Description : input signal from pad, before filtering and override are -// applied -#define IO_BANK0_GPIO31_STATUS_INFROMPAD_RESET _u(0x0) -#define IO_BANK0_GPIO31_STATUS_INFROMPAD_BITS _u(0x00020000) -#define IO_BANK0_GPIO31_STATUS_INFROMPAD_MSB _u(17) -#define IO_BANK0_GPIO31_STATUS_INFROMPAD_LSB _u(17) -#define IO_BANK0_GPIO31_STATUS_INFROMPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO31_STATUS_OETOPAD -// Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO31_STATUS_OETOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO31_STATUS_OETOPAD_BITS _u(0x00002000) -#define IO_BANK0_GPIO31_STATUS_OETOPAD_MSB _u(13) -#define IO_BANK0_GPIO31_STATUS_OETOPAD_LSB _u(13) -#define IO_BANK0_GPIO31_STATUS_OETOPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO31_STATUS_OUTTOPAD -// Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO31_STATUS_OUTTOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO31_STATUS_OUTTOPAD_BITS _u(0x00000200) -#define IO_BANK0_GPIO31_STATUS_OUTTOPAD_MSB _u(9) -#define IO_BANK0_GPIO31_STATUS_OUTTOPAD_LSB _u(9) -#define IO_BANK0_GPIO31_STATUS_OUTTOPAD_ACCESS "RO" -// ============================================================================= -// Register : IO_BANK0_GPIO31_CTRL -#define IO_BANK0_GPIO31_CTRL_OFFSET _u(0x000000fc) -#define IO_BANK0_GPIO31_CTRL_BITS _u(0x3003f01f) -#define IO_BANK0_GPIO31_CTRL_RESET _u(0x0000001f) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO31_CTRL_IRQOVER -// 0x0 -> don't invert the interrupt -// 0x1 -> invert the interrupt -// 0x2 -> drive interrupt low -// 0x3 -> drive interrupt high -#define IO_BANK0_GPIO31_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO31_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO31_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO31_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO31_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO31_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO31_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO31_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO31_CTRL_IRQOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO31_CTRL_INOVER -// 0x0 -> don't invert the peri input -// 0x1 -> invert the peri input -// 0x2 -> drive peri input low -// 0x3 -> drive peri input high -#define IO_BANK0_GPIO31_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO31_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO31_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO31_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO31_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO31_CTRL_INOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO31_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO31_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO31_CTRL_INOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO31_CTRL_OEOVER -// 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel -// 0x2 -> disable output -// 0x3 -> enable output -#define IO_BANK0_GPIO31_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO31_CTRL_OEOVER_BITS _u(0x0000c000) -#define IO_BANK0_GPIO31_CTRL_OEOVER_MSB _u(15) -#define IO_BANK0_GPIO31_CTRL_OEOVER_LSB _u(14) -#define IO_BANK0_GPIO31_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO31_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO31_CTRL_OEOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO31_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO31_CTRL_OEOVER_VALUE_ENABLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO31_CTRL_OUTOVER -// 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel -// 0x2 -> drive output low -// 0x3 -> drive output high -#define IO_BANK0_GPIO31_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO31_CTRL_OUTOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO31_CTRL_OUTOVER_MSB _u(13) -#define IO_BANK0_GPIO31_CTRL_OUTOVER_LSB _u(12) -#define IO_BANK0_GPIO31_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO31_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO31_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO31_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO31_CTRL_OUTOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO31_CTRL_FUNCSEL -// Description : 0-31 -> selects pin function according to the gpio table -// 31 == NULL -// 0x01 -> spi1_tx -// 0x02 -> uart0_rts -// 0x03 -> i2c1_scl -// 0x04 -> pwm_b_7 -// 0x05 -> siob_proc_31 -// 0x06 -> pio0_31 -// 0x07 -> pio1_31 -// 0x08 -> pio2_31 -// 0x0a -> usb_muxing_vbus_detect -// 0x0b -> uart0_rx -// 0x1f -> null -#define IO_BANK0_GPIO31_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO31_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO31_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO31_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO31_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO31_CTRL_FUNCSEL_VALUE_SPI1_TX _u(0x01) -#define IO_BANK0_GPIO31_CTRL_FUNCSEL_VALUE_UART0_RTS _u(0x02) -#define IO_BANK0_GPIO31_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03) -#define IO_BANK0_GPIO31_CTRL_FUNCSEL_VALUE_PWM_B_7 _u(0x04) -#define IO_BANK0_GPIO31_CTRL_FUNCSEL_VALUE_SIOB_PROC_31 _u(0x05) -#define IO_BANK0_GPIO31_CTRL_FUNCSEL_VALUE_PIO0_31 _u(0x06) -#define IO_BANK0_GPIO31_CTRL_FUNCSEL_VALUE_PIO1_31 _u(0x07) -#define IO_BANK0_GPIO31_CTRL_FUNCSEL_VALUE_PIO2_31 _u(0x08) -#define IO_BANK0_GPIO31_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x0a) -#define IO_BANK0_GPIO31_CTRL_FUNCSEL_VALUE_UART0_RX _u(0x0b) -#define IO_BANK0_GPIO31_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) -// ============================================================================= -// Register : IO_BANK0_GPIO32_STATUS -#define IO_BANK0_GPIO32_STATUS_OFFSET _u(0x00000100) -#define IO_BANK0_GPIO32_STATUS_BITS _u(0x04022200) -#define IO_BANK0_GPIO32_STATUS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO32_STATUS_IRQTOPROC -// Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO32_STATUS_IRQTOPROC_RESET _u(0x0) -#define IO_BANK0_GPIO32_STATUS_IRQTOPROC_BITS _u(0x04000000) -#define IO_BANK0_GPIO32_STATUS_IRQTOPROC_MSB _u(26) -#define IO_BANK0_GPIO32_STATUS_IRQTOPROC_LSB _u(26) -#define IO_BANK0_GPIO32_STATUS_IRQTOPROC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO32_STATUS_INFROMPAD -// Description : input signal from pad, before filtering and override are -// applied -#define IO_BANK0_GPIO32_STATUS_INFROMPAD_RESET _u(0x0) -#define IO_BANK0_GPIO32_STATUS_INFROMPAD_BITS _u(0x00020000) -#define IO_BANK0_GPIO32_STATUS_INFROMPAD_MSB _u(17) -#define IO_BANK0_GPIO32_STATUS_INFROMPAD_LSB _u(17) -#define IO_BANK0_GPIO32_STATUS_INFROMPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO32_STATUS_OETOPAD -// Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO32_STATUS_OETOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO32_STATUS_OETOPAD_BITS _u(0x00002000) -#define IO_BANK0_GPIO32_STATUS_OETOPAD_MSB _u(13) -#define IO_BANK0_GPIO32_STATUS_OETOPAD_LSB _u(13) -#define IO_BANK0_GPIO32_STATUS_OETOPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO32_STATUS_OUTTOPAD -// Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO32_STATUS_OUTTOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO32_STATUS_OUTTOPAD_BITS _u(0x00000200) -#define IO_BANK0_GPIO32_STATUS_OUTTOPAD_MSB _u(9) -#define IO_BANK0_GPIO32_STATUS_OUTTOPAD_LSB _u(9) -#define IO_BANK0_GPIO32_STATUS_OUTTOPAD_ACCESS "RO" -// ============================================================================= -// Register : IO_BANK0_GPIO32_CTRL -#define IO_BANK0_GPIO32_CTRL_OFFSET _u(0x00000104) -#define IO_BANK0_GPIO32_CTRL_BITS _u(0x3003f01f) -#define IO_BANK0_GPIO32_CTRL_RESET _u(0x0000001f) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO32_CTRL_IRQOVER -// 0x0 -> don't invert the interrupt -// 0x1 -> invert the interrupt -// 0x2 -> drive interrupt low -// 0x3 -> drive interrupt high -#define IO_BANK0_GPIO32_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO32_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO32_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO32_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO32_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO32_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO32_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO32_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO32_CTRL_IRQOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO32_CTRL_INOVER -// 0x0 -> don't invert the peri input -// 0x1 -> invert the peri input -// 0x2 -> drive peri input low -// 0x3 -> drive peri input high -#define IO_BANK0_GPIO32_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO32_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO32_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO32_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO32_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO32_CTRL_INOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO32_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO32_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO32_CTRL_INOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO32_CTRL_OEOVER -// 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel -// 0x2 -> disable output -// 0x3 -> enable output -#define IO_BANK0_GPIO32_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO32_CTRL_OEOVER_BITS _u(0x0000c000) -#define IO_BANK0_GPIO32_CTRL_OEOVER_MSB _u(15) -#define IO_BANK0_GPIO32_CTRL_OEOVER_LSB _u(14) -#define IO_BANK0_GPIO32_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO32_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO32_CTRL_OEOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO32_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO32_CTRL_OEOVER_VALUE_ENABLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO32_CTRL_OUTOVER -// 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel -// 0x2 -> drive output low -// 0x3 -> drive output high -#define IO_BANK0_GPIO32_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO32_CTRL_OUTOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO32_CTRL_OUTOVER_MSB _u(13) -#define IO_BANK0_GPIO32_CTRL_OUTOVER_LSB _u(12) -#define IO_BANK0_GPIO32_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO32_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO32_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO32_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO32_CTRL_OUTOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO32_CTRL_FUNCSEL -// Description : 0-31 -> selects pin function according to the gpio table -// 31 == NULL -// 0x01 -> spi0_rx -// 0x02 -> uart0_tx -// 0x03 -> i2c0_sda -// 0x04 -> pwm_a_8 -// 0x05 -> siob_proc_32 -// 0x06 -> pio0_32 -// 0x07 -> pio1_32 -// 0x08 -> pio2_32 -// 0x0a -> usb_muxing_vbus_en -// 0x1f -> null -#define IO_BANK0_GPIO32_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO32_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO32_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO32_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO32_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO32_CTRL_FUNCSEL_VALUE_SPI0_RX _u(0x01) -#define IO_BANK0_GPIO32_CTRL_FUNCSEL_VALUE_UART0_TX _u(0x02) -#define IO_BANK0_GPIO32_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03) -#define IO_BANK0_GPIO32_CTRL_FUNCSEL_VALUE_PWM_A_8 _u(0x04) -#define IO_BANK0_GPIO32_CTRL_FUNCSEL_VALUE_SIOB_PROC_32 _u(0x05) -#define IO_BANK0_GPIO32_CTRL_FUNCSEL_VALUE_PIO0_32 _u(0x06) -#define IO_BANK0_GPIO32_CTRL_FUNCSEL_VALUE_PIO1_32 _u(0x07) -#define IO_BANK0_GPIO32_CTRL_FUNCSEL_VALUE_PIO2_32 _u(0x08) -#define IO_BANK0_GPIO32_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x0a) -#define IO_BANK0_GPIO32_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) -// ============================================================================= -// Register : IO_BANK0_GPIO33_STATUS -#define IO_BANK0_GPIO33_STATUS_OFFSET _u(0x00000108) -#define IO_BANK0_GPIO33_STATUS_BITS _u(0x04022200) -#define IO_BANK0_GPIO33_STATUS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO33_STATUS_IRQTOPROC -// Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO33_STATUS_IRQTOPROC_RESET _u(0x0) -#define IO_BANK0_GPIO33_STATUS_IRQTOPROC_BITS _u(0x04000000) -#define IO_BANK0_GPIO33_STATUS_IRQTOPROC_MSB _u(26) -#define IO_BANK0_GPIO33_STATUS_IRQTOPROC_LSB _u(26) -#define IO_BANK0_GPIO33_STATUS_IRQTOPROC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO33_STATUS_INFROMPAD -// Description : input signal from pad, before filtering and override are -// applied -#define IO_BANK0_GPIO33_STATUS_INFROMPAD_RESET _u(0x0) -#define IO_BANK0_GPIO33_STATUS_INFROMPAD_BITS _u(0x00020000) -#define IO_BANK0_GPIO33_STATUS_INFROMPAD_MSB _u(17) -#define IO_BANK0_GPIO33_STATUS_INFROMPAD_LSB _u(17) -#define IO_BANK0_GPIO33_STATUS_INFROMPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO33_STATUS_OETOPAD -// Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO33_STATUS_OETOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO33_STATUS_OETOPAD_BITS _u(0x00002000) -#define IO_BANK0_GPIO33_STATUS_OETOPAD_MSB _u(13) -#define IO_BANK0_GPIO33_STATUS_OETOPAD_LSB _u(13) -#define IO_BANK0_GPIO33_STATUS_OETOPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO33_STATUS_OUTTOPAD -// Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO33_STATUS_OUTTOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO33_STATUS_OUTTOPAD_BITS _u(0x00000200) -#define IO_BANK0_GPIO33_STATUS_OUTTOPAD_MSB _u(9) -#define IO_BANK0_GPIO33_STATUS_OUTTOPAD_LSB _u(9) -#define IO_BANK0_GPIO33_STATUS_OUTTOPAD_ACCESS "RO" -// ============================================================================= -// Register : IO_BANK0_GPIO33_CTRL -#define IO_BANK0_GPIO33_CTRL_OFFSET _u(0x0000010c) -#define IO_BANK0_GPIO33_CTRL_BITS _u(0x3003f01f) -#define IO_BANK0_GPIO33_CTRL_RESET _u(0x0000001f) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO33_CTRL_IRQOVER -// 0x0 -> don't invert the interrupt -// 0x1 -> invert the interrupt -// 0x2 -> drive interrupt low -// 0x3 -> drive interrupt high -#define IO_BANK0_GPIO33_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO33_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO33_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO33_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO33_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO33_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO33_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO33_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO33_CTRL_IRQOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO33_CTRL_INOVER -// 0x0 -> don't invert the peri input -// 0x1 -> invert the peri input -// 0x2 -> drive peri input low -// 0x3 -> drive peri input high -#define IO_BANK0_GPIO33_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO33_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO33_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO33_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO33_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO33_CTRL_INOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO33_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO33_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO33_CTRL_INOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO33_CTRL_OEOVER -// 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel -// 0x2 -> disable output -// 0x3 -> enable output -#define IO_BANK0_GPIO33_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO33_CTRL_OEOVER_BITS _u(0x0000c000) -#define IO_BANK0_GPIO33_CTRL_OEOVER_MSB _u(15) -#define IO_BANK0_GPIO33_CTRL_OEOVER_LSB _u(14) -#define IO_BANK0_GPIO33_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO33_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO33_CTRL_OEOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO33_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO33_CTRL_OEOVER_VALUE_ENABLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO33_CTRL_OUTOVER -// 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel -// 0x2 -> drive output low -// 0x3 -> drive output high -#define IO_BANK0_GPIO33_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO33_CTRL_OUTOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO33_CTRL_OUTOVER_MSB _u(13) -#define IO_BANK0_GPIO33_CTRL_OUTOVER_LSB _u(12) -#define IO_BANK0_GPIO33_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO33_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO33_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO33_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO33_CTRL_OUTOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO33_CTRL_FUNCSEL -// Description : 0-31 -> selects pin function according to the gpio table -// 31 == NULL -// 0x01 -> spi0_ss_n -// 0x02 -> uart0_rx -// 0x03 -> i2c0_scl -// 0x04 -> pwm_b_8 -// 0x05 -> siob_proc_33 -// 0x06 -> pio0_33 -// 0x07 -> pio1_33 -// 0x08 -> pio2_33 -// 0x0a -> usb_muxing_overcurr_detect -// 0x1f -> null -#define IO_BANK0_GPIO33_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO33_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO33_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO33_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO33_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO33_CTRL_FUNCSEL_VALUE_SPI0_SS_N _u(0x01) -#define IO_BANK0_GPIO33_CTRL_FUNCSEL_VALUE_UART0_RX _u(0x02) -#define IO_BANK0_GPIO33_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03) -#define IO_BANK0_GPIO33_CTRL_FUNCSEL_VALUE_PWM_B_8 _u(0x04) -#define IO_BANK0_GPIO33_CTRL_FUNCSEL_VALUE_SIOB_PROC_33 _u(0x05) -#define IO_BANK0_GPIO33_CTRL_FUNCSEL_VALUE_PIO0_33 _u(0x06) -#define IO_BANK0_GPIO33_CTRL_FUNCSEL_VALUE_PIO1_33 _u(0x07) -#define IO_BANK0_GPIO33_CTRL_FUNCSEL_VALUE_PIO2_33 _u(0x08) -#define IO_BANK0_GPIO33_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x0a) -#define IO_BANK0_GPIO33_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) -// ============================================================================= -// Register : IO_BANK0_GPIO34_STATUS -#define IO_BANK0_GPIO34_STATUS_OFFSET _u(0x00000110) -#define IO_BANK0_GPIO34_STATUS_BITS _u(0x04022200) -#define IO_BANK0_GPIO34_STATUS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO34_STATUS_IRQTOPROC -// Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO34_STATUS_IRQTOPROC_RESET _u(0x0) -#define IO_BANK0_GPIO34_STATUS_IRQTOPROC_BITS _u(0x04000000) -#define IO_BANK0_GPIO34_STATUS_IRQTOPROC_MSB _u(26) -#define IO_BANK0_GPIO34_STATUS_IRQTOPROC_LSB _u(26) -#define IO_BANK0_GPIO34_STATUS_IRQTOPROC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO34_STATUS_INFROMPAD -// Description : input signal from pad, before filtering and override are -// applied -#define IO_BANK0_GPIO34_STATUS_INFROMPAD_RESET _u(0x0) -#define IO_BANK0_GPIO34_STATUS_INFROMPAD_BITS _u(0x00020000) -#define IO_BANK0_GPIO34_STATUS_INFROMPAD_MSB _u(17) -#define IO_BANK0_GPIO34_STATUS_INFROMPAD_LSB _u(17) -#define IO_BANK0_GPIO34_STATUS_INFROMPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO34_STATUS_OETOPAD -// Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO34_STATUS_OETOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO34_STATUS_OETOPAD_BITS _u(0x00002000) -#define IO_BANK0_GPIO34_STATUS_OETOPAD_MSB _u(13) -#define IO_BANK0_GPIO34_STATUS_OETOPAD_LSB _u(13) -#define IO_BANK0_GPIO34_STATUS_OETOPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO34_STATUS_OUTTOPAD -// Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO34_STATUS_OUTTOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO34_STATUS_OUTTOPAD_BITS _u(0x00000200) -#define IO_BANK0_GPIO34_STATUS_OUTTOPAD_MSB _u(9) -#define IO_BANK0_GPIO34_STATUS_OUTTOPAD_LSB _u(9) -#define IO_BANK0_GPIO34_STATUS_OUTTOPAD_ACCESS "RO" -// ============================================================================= -// Register : IO_BANK0_GPIO34_CTRL -#define IO_BANK0_GPIO34_CTRL_OFFSET _u(0x00000114) -#define IO_BANK0_GPIO34_CTRL_BITS _u(0x3003f01f) -#define IO_BANK0_GPIO34_CTRL_RESET _u(0x0000001f) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO34_CTRL_IRQOVER -// 0x0 -> don't invert the interrupt -// 0x1 -> invert the interrupt -// 0x2 -> drive interrupt low -// 0x3 -> drive interrupt high -#define IO_BANK0_GPIO34_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO34_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO34_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO34_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO34_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO34_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO34_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO34_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO34_CTRL_IRQOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO34_CTRL_INOVER -// 0x0 -> don't invert the peri input -// 0x1 -> invert the peri input -// 0x2 -> drive peri input low -// 0x3 -> drive peri input high -#define IO_BANK0_GPIO34_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO34_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO34_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO34_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO34_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO34_CTRL_INOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO34_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO34_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO34_CTRL_INOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO34_CTRL_OEOVER -// 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel -// 0x2 -> disable output -// 0x3 -> enable output -#define IO_BANK0_GPIO34_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO34_CTRL_OEOVER_BITS _u(0x0000c000) -#define IO_BANK0_GPIO34_CTRL_OEOVER_MSB _u(15) -#define IO_BANK0_GPIO34_CTRL_OEOVER_LSB _u(14) -#define IO_BANK0_GPIO34_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO34_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO34_CTRL_OEOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO34_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO34_CTRL_OEOVER_VALUE_ENABLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO34_CTRL_OUTOVER -// 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel -// 0x2 -> drive output low -// 0x3 -> drive output high -#define IO_BANK0_GPIO34_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO34_CTRL_OUTOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO34_CTRL_OUTOVER_MSB _u(13) -#define IO_BANK0_GPIO34_CTRL_OUTOVER_LSB _u(12) -#define IO_BANK0_GPIO34_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO34_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO34_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO34_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO34_CTRL_OUTOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO34_CTRL_FUNCSEL -// Description : 0-31 -> selects pin function according to the gpio table -// 31 == NULL -// 0x01 -> spi0_sclk -// 0x02 -> uart0_cts -// 0x03 -> i2c1_sda -// 0x04 -> pwm_a_9 -// 0x05 -> siob_proc_34 -// 0x06 -> pio0_34 -// 0x07 -> pio1_34 -// 0x08 -> pio2_34 -// 0x0a -> usb_muxing_vbus_detect -// 0x0b -> uart0_tx -// 0x1f -> null -#define IO_BANK0_GPIO34_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO34_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO34_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO34_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO34_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO34_CTRL_FUNCSEL_VALUE_SPI0_SCLK _u(0x01) -#define IO_BANK0_GPIO34_CTRL_FUNCSEL_VALUE_UART0_CTS _u(0x02) -#define IO_BANK0_GPIO34_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03) -#define IO_BANK0_GPIO34_CTRL_FUNCSEL_VALUE_PWM_A_9 _u(0x04) -#define IO_BANK0_GPIO34_CTRL_FUNCSEL_VALUE_SIOB_PROC_34 _u(0x05) -#define IO_BANK0_GPIO34_CTRL_FUNCSEL_VALUE_PIO0_34 _u(0x06) -#define IO_BANK0_GPIO34_CTRL_FUNCSEL_VALUE_PIO1_34 _u(0x07) -#define IO_BANK0_GPIO34_CTRL_FUNCSEL_VALUE_PIO2_34 _u(0x08) -#define IO_BANK0_GPIO34_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x0a) -#define IO_BANK0_GPIO34_CTRL_FUNCSEL_VALUE_UART0_TX _u(0x0b) -#define IO_BANK0_GPIO34_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) -// ============================================================================= -// Register : IO_BANK0_GPIO35_STATUS -#define IO_BANK0_GPIO35_STATUS_OFFSET _u(0x00000118) -#define IO_BANK0_GPIO35_STATUS_BITS _u(0x04022200) -#define IO_BANK0_GPIO35_STATUS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO35_STATUS_IRQTOPROC -// Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO35_STATUS_IRQTOPROC_RESET _u(0x0) -#define IO_BANK0_GPIO35_STATUS_IRQTOPROC_BITS _u(0x04000000) -#define IO_BANK0_GPIO35_STATUS_IRQTOPROC_MSB _u(26) -#define IO_BANK0_GPIO35_STATUS_IRQTOPROC_LSB _u(26) -#define IO_BANK0_GPIO35_STATUS_IRQTOPROC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO35_STATUS_INFROMPAD -// Description : input signal from pad, before filtering and override are -// applied -#define IO_BANK0_GPIO35_STATUS_INFROMPAD_RESET _u(0x0) -#define IO_BANK0_GPIO35_STATUS_INFROMPAD_BITS _u(0x00020000) -#define IO_BANK0_GPIO35_STATUS_INFROMPAD_MSB _u(17) -#define IO_BANK0_GPIO35_STATUS_INFROMPAD_LSB _u(17) -#define IO_BANK0_GPIO35_STATUS_INFROMPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO35_STATUS_OETOPAD -// Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO35_STATUS_OETOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO35_STATUS_OETOPAD_BITS _u(0x00002000) -#define IO_BANK0_GPIO35_STATUS_OETOPAD_MSB _u(13) -#define IO_BANK0_GPIO35_STATUS_OETOPAD_LSB _u(13) -#define IO_BANK0_GPIO35_STATUS_OETOPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO35_STATUS_OUTTOPAD -// Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO35_STATUS_OUTTOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO35_STATUS_OUTTOPAD_BITS _u(0x00000200) -#define IO_BANK0_GPIO35_STATUS_OUTTOPAD_MSB _u(9) -#define IO_BANK0_GPIO35_STATUS_OUTTOPAD_LSB _u(9) -#define IO_BANK0_GPIO35_STATUS_OUTTOPAD_ACCESS "RO" -// ============================================================================= -// Register : IO_BANK0_GPIO35_CTRL -#define IO_BANK0_GPIO35_CTRL_OFFSET _u(0x0000011c) -#define IO_BANK0_GPIO35_CTRL_BITS _u(0x3003f01f) -#define IO_BANK0_GPIO35_CTRL_RESET _u(0x0000001f) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO35_CTRL_IRQOVER -// 0x0 -> don't invert the interrupt -// 0x1 -> invert the interrupt -// 0x2 -> drive interrupt low -// 0x3 -> drive interrupt high -#define IO_BANK0_GPIO35_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO35_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO35_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO35_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO35_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO35_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO35_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO35_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO35_CTRL_IRQOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO35_CTRL_INOVER -// 0x0 -> don't invert the peri input -// 0x1 -> invert the peri input -// 0x2 -> drive peri input low -// 0x3 -> drive peri input high -#define IO_BANK0_GPIO35_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO35_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO35_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO35_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO35_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO35_CTRL_INOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO35_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO35_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO35_CTRL_INOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO35_CTRL_OEOVER -// 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel -// 0x2 -> disable output -// 0x3 -> enable output -#define IO_BANK0_GPIO35_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO35_CTRL_OEOVER_BITS _u(0x0000c000) -#define IO_BANK0_GPIO35_CTRL_OEOVER_MSB _u(15) -#define IO_BANK0_GPIO35_CTRL_OEOVER_LSB _u(14) -#define IO_BANK0_GPIO35_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO35_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO35_CTRL_OEOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO35_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO35_CTRL_OEOVER_VALUE_ENABLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO35_CTRL_OUTOVER -// 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel -// 0x2 -> drive output low -// 0x3 -> drive output high -#define IO_BANK0_GPIO35_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO35_CTRL_OUTOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO35_CTRL_OUTOVER_MSB _u(13) -#define IO_BANK0_GPIO35_CTRL_OUTOVER_LSB _u(12) -#define IO_BANK0_GPIO35_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO35_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO35_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO35_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO35_CTRL_OUTOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO35_CTRL_FUNCSEL -// Description : 0-31 -> selects pin function according to the gpio table -// 31 == NULL -// 0x01 -> spi0_tx -// 0x02 -> uart0_rts -// 0x03 -> i2c1_scl -// 0x04 -> pwm_b_9 -// 0x05 -> siob_proc_35 -// 0x06 -> pio0_35 -// 0x07 -> pio1_35 -// 0x08 -> pio2_35 -// 0x0a -> usb_muxing_vbus_en -// 0x0b -> uart0_rx -// 0x1f -> null -#define IO_BANK0_GPIO35_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO35_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO35_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO35_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO35_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO35_CTRL_FUNCSEL_VALUE_SPI0_TX _u(0x01) -#define IO_BANK0_GPIO35_CTRL_FUNCSEL_VALUE_UART0_RTS _u(0x02) -#define IO_BANK0_GPIO35_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03) -#define IO_BANK0_GPIO35_CTRL_FUNCSEL_VALUE_PWM_B_9 _u(0x04) -#define IO_BANK0_GPIO35_CTRL_FUNCSEL_VALUE_SIOB_PROC_35 _u(0x05) -#define IO_BANK0_GPIO35_CTRL_FUNCSEL_VALUE_PIO0_35 _u(0x06) -#define IO_BANK0_GPIO35_CTRL_FUNCSEL_VALUE_PIO1_35 _u(0x07) -#define IO_BANK0_GPIO35_CTRL_FUNCSEL_VALUE_PIO2_35 _u(0x08) -#define IO_BANK0_GPIO35_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x0a) -#define IO_BANK0_GPIO35_CTRL_FUNCSEL_VALUE_UART0_RX _u(0x0b) -#define IO_BANK0_GPIO35_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) -// ============================================================================= -// Register : IO_BANK0_GPIO36_STATUS -#define IO_BANK0_GPIO36_STATUS_OFFSET _u(0x00000120) -#define IO_BANK0_GPIO36_STATUS_BITS _u(0x04022200) -#define IO_BANK0_GPIO36_STATUS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO36_STATUS_IRQTOPROC -// Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO36_STATUS_IRQTOPROC_RESET _u(0x0) -#define IO_BANK0_GPIO36_STATUS_IRQTOPROC_BITS _u(0x04000000) -#define IO_BANK0_GPIO36_STATUS_IRQTOPROC_MSB _u(26) -#define IO_BANK0_GPIO36_STATUS_IRQTOPROC_LSB _u(26) -#define IO_BANK0_GPIO36_STATUS_IRQTOPROC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO36_STATUS_INFROMPAD -// Description : input signal from pad, before filtering and override are -// applied -#define IO_BANK0_GPIO36_STATUS_INFROMPAD_RESET _u(0x0) -#define IO_BANK0_GPIO36_STATUS_INFROMPAD_BITS _u(0x00020000) -#define IO_BANK0_GPIO36_STATUS_INFROMPAD_MSB _u(17) -#define IO_BANK0_GPIO36_STATUS_INFROMPAD_LSB _u(17) -#define IO_BANK0_GPIO36_STATUS_INFROMPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO36_STATUS_OETOPAD -// Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO36_STATUS_OETOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO36_STATUS_OETOPAD_BITS _u(0x00002000) -#define IO_BANK0_GPIO36_STATUS_OETOPAD_MSB _u(13) -#define IO_BANK0_GPIO36_STATUS_OETOPAD_LSB _u(13) -#define IO_BANK0_GPIO36_STATUS_OETOPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO36_STATUS_OUTTOPAD -// Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO36_STATUS_OUTTOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO36_STATUS_OUTTOPAD_BITS _u(0x00000200) -#define IO_BANK0_GPIO36_STATUS_OUTTOPAD_MSB _u(9) -#define IO_BANK0_GPIO36_STATUS_OUTTOPAD_LSB _u(9) -#define IO_BANK0_GPIO36_STATUS_OUTTOPAD_ACCESS "RO" -// ============================================================================= -// Register : IO_BANK0_GPIO36_CTRL -#define IO_BANK0_GPIO36_CTRL_OFFSET _u(0x00000124) -#define IO_BANK0_GPIO36_CTRL_BITS _u(0x3003f01f) -#define IO_BANK0_GPIO36_CTRL_RESET _u(0x0000001f) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO36_CTRL_IRQOVER -// 0x0 -> don't invert the interrupt -// 0x1 -> invert the interrupt -// 0x2 -> drive interrupt low -// 0x3 -> drive interrupt high -#define IO_BANK0_GPIO36_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO36_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO36_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO36_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO36_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO36_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO36_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO36_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO36_CTRL_IRQOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO36_CTRL_INOVER -// 0x0 -> don't invert the peri input -// 0x1 -> invert the peri input -// 0x2 -> drive peri input low -// 0x3 -> drive peri input high -#define IO_BANK0_GPIO36_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO36_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO36_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO36_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO36_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO36_CTRL_INOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO36_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO36_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO36_CTRL_INOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO36_CTRL_OEOVER -// 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel -// 0x2 -> disable output -// 0x3 -> enable output -#define IO_BANK0_GPIO36_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO36_CTRL_OEOVER_BITS _u(0x0000c000) -#define IO_BANK0_GPIO36_CTRL_OEOVER_MSB _u(15) -#define IO_BANK0_GPIO36_CTRL_OEOVER_LSB _u(14) -#define IO_BANK0_GPIO36_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO36_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO36_CTRL_OEOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO36_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO36_CTRL_OEOVER_VALUE_ENABLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO36_CTRL_OUTOVER -// 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel -// 0x2 -> drive output low -// 0x3 -> drive output high -#define IO_BANK0_GPIO36_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO36_CTRL_OUTOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO36_CTRL_OUTOVER_MSB _u(13) -#define IO_BANK0_GPIO36_CTRL_OUTOVER_LSB _u(12) -#define IO_BANK0_GPIO36_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO36_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO36_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO36_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO36_CTRL_OUTOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO36_CTRL_FUNCSEL -// Description : 0-31 -> selects pin function according to the gpio table -// 31 == NULL -// 0x01 -> spi0_rx -// 0x02 -> uart1_tx -// 0x03 -> i2c0_sda -// 0x04 -> pwm_a_10 -// 0x05 -> siob_proc_36 -// 0x06 -> pio0_36 -// 0x07 -> pio1_36 -// 0x08 -> pio2_36 -// 0x0a -> usb_muxing_overcurr_detect -// 0x1f -> null -#define IO_BANK0_GPIO36_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO36_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO36_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO36_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO36_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO36_CTRL_FUNCSEL_VALUE_SPI0_RX _u(0x01) -#define IO_BANK0_GPIO36_CTRL_FUNCSEL_VALUE_UART1_TX _u(0x02) -#define IO_BANK0_GPIO36_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03) -#define IO_BANK0_GPIO36_CTRL_FUNCSEL_VALUE_PWM_A_10 _u(0x04) -#define IO_BANK0_GPIO36_CTRL_FUNCSEL_VALUE_SIOB_PROC_36 _u(0x05) -#define IO_BANK0_GPIO36_CTRL_FUNCSEL_VALUE_PIO0_36 _u(0x06) -#define IO_BANK0_GPIO36_CTRL_FUNCSEL_VALUE_PIO1_36 _u(0x07) -#define IO_BANK0_GPIO36_CTRL_FUNCSEL_VALUE_PIO2_36 _u(0x08) -#define IO_BANK0_GPIO36_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x0a) -#define IO_BANK0_GPIO36_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) -// ============================================================================= -// Register : IO_BANK0_GPIO37_STATUS -#define IO_BANK0_GPIO37_STATUS_OFFSET _u(0x00000128) -#define IO_BANK0_GPIO37_STATUS_BITS _u(0x04022200) -#define IO_BANK0_GPIO37_STATUS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO37_STATUS_IRQTOPROC -// Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO37_STATUS_IRQTOPROC_RESET _u(0x0) -#define IO_BANK0_GPIO37_STATUS_IRQTOPROC_BITS _u(0x04000000) -#define IO_BANK0_GPIO37_STATUS_IRQTOPROC_MSB _u(26) -#define IO_BANK0_GPIO37_STATUS_IRQTOPROC_LSB _u(26) -#define IO_BANK0_GPIO37_STATUS_IRQTOPROC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO37_STATUS_INFROMPAD -// Description : input signal from pad, before filtering and override are -// applied -#define IO_BANK0_GPIO37_STATUS_INFROMPAD_RESET _u(0x0) -#define IO_BANK0_GPIO37_STATUS_INFROMPAD_BITS _u(0x00020000) -#define IO_BANK0_GPIO37_STATUS_INFROMPAD_MSB _u(17) -#define IO_BANK0_GPIO37_STATUS_INFROMPAD_LSB _u(17) -#define IO_BANK0_GPIO37_STATUS_INFROMPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO37_STATUS_OETOPAD -// Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO37_STATUS_OETOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO37_STATUS_OETOPAD_BITS _u(0x00002000) -#define IO_BANK0_GPIO37_STATUS_OETOPAD_MSB _u(13) -#define IO_BANK0_GPIO37_STATUS_OETOPAD_LSB _u(13) -#define IO_BANK0_GPIO37_STATUS_OETOPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO37_STATUS_OUTTOPAD -// Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO37_STATUS_OUTTOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO37_STATUS_OUTTOPAD_BITS _u(0x00000200) -#define IO_BANK0_GPIO37_STATUS_OUTTOPAD_MSB _u(9) -#define IO_BANK0_GPIO37_STATUS_OUTTOPAD_LSB _u(9) -#define IO_BANK0_GPIO37_STATUS_OUTTOPAD_ACCESS "RO" -// ============================================================================= -// Register : IO_BANK0_GPIO37_CTRL -#define IO_BANK0_GPIO37_CTRL_OFFSET _u(0x0000012c) -#define IO_BANK0_GPIO37_CTRL_BITS _u(0x3003f01f) -#define IO_BANK0_GPIO37_CTRL_RESET _u(0x0000001f) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO37_CTRL_IRQOVER -// 0x0 -> don't invert the interrupt -// 0x1 -> invert the interrupt -// 0x2 -> drive interrupt low -// 0x3 -> drive interrupt high -#define IO_BANK0_GPIO37_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO37_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO37_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO37_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO37_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO37_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO37_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO37_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO37_CTRL_IRQOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO37_CTRL_INOVER -// 0x0 -> don't invert the peri input -// 0x1 -> invert the peri input -// 0x2 -> drive peri input low -// 0x3 -> drive peri input high -#define IO_BANK0_GPIO37_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO37_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO37_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO37_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO37_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO37_CTRL_INOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO37_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO37_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO37_CTRL_INOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO37_CTRL_OEOVER -// 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel -// 0x2 -> disable output -// 0x3 -> enable output -#define IO_BANK0_GPIO37_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO37_CTRL_OEOVER_BITS _u(0x0000c000) -#define IO_BANK0_GPIO37_CTRL_OEOVER_MSB _u(15) -#define IO_BANK0_GPIO37_CTRL_OEOVER_LSB _u(14) -#define IO_BANK0_GPIO37_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO37_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO37_CTRL_OEOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO37_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO37_CTRL_OEOVER_VALUE_ENABLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO37_CTRL_OUTOVER -// 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel -// 0x2 -> drive output low -// 0x3 -> drive output high -#define IO_BANK0_GPIO37_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO37_CTRL_OUTOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO37_CTRL_OUTOVER_MSB _u(13) -#define IO_BANK0_GPIO37_CTRL_OUTOVER_LSB _u(12) -#define IO_BANK0_GPIO37_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO37_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO37_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO37_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO37_CTRL_OUTOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO37_CTRL_FUNCSEL -// Description : 0-31 -> selects pin function according to the gpio table -// 31 == NULL -// 0x01 -> spi0_ss_n -// 0x02 -> uart1_rx -// 0x03 -> i2c0_scl -// 0x04 -> pwm_b_10 -// 0x05 -> siob_proc_37 -// 0x06 -> pio0_37 -// 0x07 -> pio1_37 -// 0x08 -> pio2_37 -// 0x0a -> usb_muxing_vbus_detect -// 0x1f -> null -#define IO_BANK0_GPIO37_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO37_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO37_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO37_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO37_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO37_CTRL_FUNCSEL_VALUE_SPI0_SS_N _u(0x01) -#define IO_BANK0_GPIO37_CTRL_FUNCSEL_VALUE_UART1_RX _u(0x02) -#define IO_BANK0_GPIO37_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03) -#define IO_BANK0_GPIO37_CTRL_FUNCSEL_VALUE_PWM_B_10 _u(0x04) -#define IO_BANK0_GPIO37_CTRL_FUNCSEL_VALUE_SIOB_PROC_37 _u(0x05) -#define IO_BANK0_GPIO37_CTRL_FUNCSEL_VALUE_PIO0_37 _u(0x06) -#define IO_BANK0_GPIO37_CTRL_FUNCSEL_VALUE_PIO1_37 _u(0x07) -#define IO_BANK0_GPIO37_CTRL_FUNCSEL_VALUE_PIO2_37 _u(0x08) -#define IO_BANK0_GPIO37_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x0a) -#define IO_BANK0_GPIO37_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) -// ============================================================================= -// Register : IO_BANK0_GPIO38_STATUS -#define IO_BANK0_GPIO38_STATUS_OFFSET _u(0x00000130) -#define IO_BANK0_GPIO38_STATUS_BITS _u(0x04022200) -#define IO_BANK0_GPIO38_STATUS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO38_STATUS_IRQTOPROC -// Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO38_STATUS_IRQTOPROC_RESET _u(0x0) -#define IO_BANK0_GPIO38_STATUS_IRQTOPROC_BITS _u(0x04000000) -#define IO_BANK0_GPIO38_STATUS_IRQTOPROC_MSB _u(26) -#define IO_BANK0_GPIO38_STATUS_IRQTOPROC_LSB _u(26) -#define IO_BANK0_GPIO38_STATUS_IRQTOPROC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO38_STATUS_INFROMPAD -// Description : input signal from pad, before filtering and override are -// applied -#define IO_BANK0_GPIO38_STATUS_INFROMPAD_RESET _u(0x0) -#define IO_BANK0_GPIO38_STATUS_INFROMPAD_BITS _u(0x00020000) -#define IO_BANK0_GPIO38_STATUS_INFROMPAD_MSB _u(17) -#define IO_BANK0_GPIO38_STATUS_INFROMPAD_LSB _u(17) -#define IO_BANK0_GPIO38_STATUS_INFROMPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO38_STATUS_OETOPAD -// Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO38_STATUS_OETOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO38_STATUS_OETOPAD_BITS _u(0x00002000) -#define IO_BANK0_GPIO38_STATUS_OETOPAD_MSB _u(13) -#define IO_BANK0_GPIO38_STATUS_OETOPAD_LSB _u(13) -#define IO_BANK0_GPIO38_STATUS_OETOPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO38_STATUS_OUTTOPAD -// Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO38_STATUS_OUTTOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO38_STATUS_OUTTOPAD_BITS _u(0x00000200) -#define IO_BANK0_GPIO38_STATUS_OUTTOPAD_MSB _u(9) -#define IO_BANK0_GPIO38_STATUS_OUTTOPAD_LSB _u(9) -#define IO_BANK0_GPIO38_STATUS_OUTTOPAD_ACCESS "RO" -// ============================================================================= -// Register : IO_BANK0_GPIO38_CTRL -#define IO_BANK0_GPIO38_CTRL_OFFSET _u(0x00000134) -#define IO_BANK0_GPIO38_CTRL_BITS _u(0x3003f01f) -#define IO_BANK0_GPIO38_CTRL_RESET _u(0x0000001f) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO38_CTRL_IRQOVER -// 0x0 -> don't invert the interrupt -// 0x1 -> invert the interrupt -// 0x2 -> drive interrupt low -// 0x3 -> drive interrupt high -#define IO_BANK0_GPIO38_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO38_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO38_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO38_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO38_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO38_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO38_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO38_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO38_CTRL_IRQOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO38_CTRL_INOVER -// 0x0 -> don't invert the peri input -// 0x1 -> invert the peri input -// 0x2 -> drive peri input low -// 0x3 -> drive peri input high -#define IO_BANK0_GPIO38_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO38_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO38_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO38_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO38_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO38_CTRL_INOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO38_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO38_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO38_CTRL_INOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO38_CTRL_OEOVER -// 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel -// 0x2 -> disable output -// 0x3 -> enable output -#define IO_BANK0_GPIO38_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO38_CTRL_OEOVER_BITS _u(0x0000c000) -#define IO_BANK0_GPIO38_CTRL_OEOVER_MSB _u(15) -#define IO_BANK0_GPIO38_CTRL_OEOVER_LSB _u(14) -#define IO_BANK0_GPIO38_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO38_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO38_CTRL_OEOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO38_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO38_CTRL_OEOVER_VALUE_ENABLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO38_CTRL_OUTOVER -// 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel -// 0x2 -> drive output low -// 0x3 -> drive output high -#define IO_BANK0_GPIO38_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO38_CTRL_OUTOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO38_CTRL_OUTOVER_MSB _u(13) -#define IO_BANK0_GPIO38_CTRL_OUTOVER_LSB _u(12) -#define IO_BANK0_GPIO38_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO38_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO38_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO38_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO38_CTRL_OUTOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO38_CTRL_FUNCSEL -// Description : 0-31 -> selects pin function according to the gpio table -// 31 == NULL -// 0x01 -> spi0_sclk -// 0x02 -> uart1_cts -// 0x03 -> i2c1_sda -// 0x04 -> pwm_a_11 -// 0x05 -> siob_proc_38 -// 0x06 -> pio0_38 -// 0x07 -> pio1_38 -// 0x08 -> pio2_38 -// 0x0a -> usb_muxing_vbus_en -// 0x0b -> uart1_tx -// 0x1f -> null -#define IO_BANK0_GPIO38_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO38_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO38_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO38_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO38_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO38_CTRL_FUNCSEL_VALUE_SPI0_SCLK _u(0x01) -#define IO_BANK0_GPIO38_CTRL_FUNCSEL_VALUE_UART1_CTS _u(0x02) -#define IO_BANK0_GPIO38_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03) -#define IO_BANK0_GPIO38_CTRL_FUNCSEL_VALUE_PWM_A_11 _u(0x04) -#define IO_BANK0_GPIO38_CTRL_FUNCSEL_VALUE_SIOB_PROC_38 _u(0x05) -#define IO_BANK0_GPIO38_CTRL_FUNCSEL_VALUE_PIO0_38 _u(0x06) -#define IO_BANK0_GPIO38_CTRL_FUNCSEL_VALUE_PIO1_38 _u(0x07) -#define IO_BANK0_GPIO38_CTRL_FUNCSEL_VALUE_PIO2_38 _u(0x08) -#define IO_BANK0_GPIO38_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x0a) -#define IO_BANK0_GPIO38_CTRL_FUNCSEL_VALUE_UART1_TX _u(0x0b) -#define IO_BANK0_GPIO38_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) -// ============================================================================= -// Register : IO_BANK0_GPIO39_STATUS -#define IO_BANK0_GPIO39_STATUS_OFFSET _u(0x00000138) -#define IO_BANK0_GPIO39_STATUS_BITS _u(0x04022200) -#define IO_BANK0_GPIO39_STATUS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO39_STATUS_IRQTOPROC -// Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO39_STATUS_IRQTOPROC_RESET _u(0x0) -#define IO_BANK0_GPIO39_STATUS_IRQTOPROC_BITS _u(0x04000000) -#define IO_BANK0_GPIO39_STATUS_IRQTOPROC_MSB _u(26) -#define IO_BANK0_GPIO39_STATUS_IRQTOPROC_LSB _u(26) -#define IO_BANK0_GPIO39_STATUS_IRQTOPROC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO39_STATUS_INFROMPAD -// Description : input signal from pad, before filtering and override are -// applied -#define IO_BANK0_GPIO39_STATUS_INFROMPAD_RESET _u(0x0) -#define IO_BANK0_GPIO39_STATUS_INFROMPAD_BITS _u(0x00020000) -#define IO_BANK0_GPIO39_STATUS_INFROMPAD_MSB _u(17) -#define IO_BANK0_GPIO39_STATUS_INFROMPAD_LSB _u(17) -#define IO_BANK0_GPIO39_STATUS_INFROMPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO39_STATUS_OETOPAD -// Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO39_STATUS_OETOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO39_STATUS_OETOPAD_BITS _u(0x00002000) -#define IO_BANK0_GPIO39_STATUS_OETOPAD_MSB _u(13) -#define IO_BANK0_GPIO39_STATUS_OETOPAD_LSB _u(13) -#define IO_BANK0_GPIO39_STATUS_OETOPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO39_STATUS_OUTTOPAD -// Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO39_STATUS_OUTTOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO39_STATUS_OUTTOPAD_BITS _u(0x00000200) -#define IO_BANK0_GPIO39_STATUS_OUTTOPAD_MSB _u(9) -#define IO_BANK0_GPIO39_STATUS_OUTTOPAD_LSB _u(9) -#define IO_BANK0_GPIO39_STATUS_OUTTOPAD_ACCESS "RO" -// ============================================================================= -// Register : IO_BANK0_GPIO39_CTRL -#define IO_BANK0_GPIO39_CTRL_OFFSET _u(0x0000013c) -#define IO_BANK0_GPIO39_CTRL_BITS _u(0x3003f01f) -#define IO_BANK0_GPIO39_CTRL_RESET _u(0x0000001f) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO39_CTRL_IRQOVER -// 0x0 -> don't invert the interrupt -// 0x1 -> invert the interrupt -// 0x2 -> drive interrupt low -// 0x3 -> drive interrupt high -#define IO_BANK0_GPIO39_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO39_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO39_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO39_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO39_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO39_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO39_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO39_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO39_CTRL_IRQOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO39_CTRL_INOVER -// 0x0 -> don't invert the peri input -// 0x1 -> invert the peri input -// 0x2 -> drive peri input low -// 0x3 -> drive peri input high -#define IO_BANK0_GPIO39_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO39_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO39_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO39_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO39_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO39_CTRL_INOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO39_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO39_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO39_CTRL_INOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO39_CTRL_OEOVER -// 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel -// 0x2 -> disable output -// 0x3 -> enable output -#define IO_BANK0_GPIO39_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO39_CTRL_OEOVER_BITS _u(0x0000c000) -#define IO_BANK0_GPIO39_CTRL_OEOVER_MSB _u(15) -#define IO_BANK0_GPIO39_CTRL_OEOVER_LSB _u(14) -#define IO_BANK0_GPIO39_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO39_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO39_CTRL_OEOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO39_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO39_CTRL_OEOVER_VALUE_ENABLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO39_CTRL_OUTOVER -// 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel -// 0x2 -> drive output low -// 0x3 -> drive output high -#define IO_BANK0_GPIO39_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO39_CTRL_OUTOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO39_CTRL_OUTOVER_MSB _u(13) -#define IO_BANK0_GPIO39_CTRL_OUTOVER_LSB _u(12) -#define IO_BANK0_GPIO39_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO39_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO39_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO39_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO39_CTRL_OUTOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO39_CTRL_FUNCSEL -// Description : 0-31 -> selects pin function according to the gpio table -// 31 == NULL -// 0x01 -> spi0_tx -// 0x02 -> uart1_rts -// 0x03 -> i2c1_scl -// 0x04 -> pwm_b_11 -// 0x05 -> siob_proc_39 -// 0x06 -> pio0_39 -// 0x07 -> pio1_39 -// 0x08 -> pio2_39 -// 0x0a -> usb_muxing_overcurr_detect -// 0x0b -> uart1_rx -// 0x1f -> null -#define IO_BANK0_GPIO39_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO39_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO39_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO39_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO39_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO39_CTRL_FUNCSEL_VALUE_SPI0_TX _u(0x01) -#define IO_BANK0_GPIO39_CTRL_FUNCSEL_VALUE_UART1_RTS _u(0x02) -#define IO_BANK0_GPIO39_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03) -#define IO_BANK0_GPIO39_CTRL_FUNCSEL_VALUE_PWM_B_11 _u(0x04) -#define IO_BANK0_GPIO39_CTRL_FUNCSEL_VALUE_SIOB_PROC_39 _u(0x05) -#define IO_BANK0_GPIO39_CTRL_FUNCSEL_VALUE_PIO0_39 _u(0x06) -#define IO_BANK0_GPIO39_CTRL_FUNCSEL_VALUE_PIO1_39 _u(0x07) -#define IO_BANK0_GPIO39_CTRL_FUNCSEL_VALUE_PIO2_39 _u(0x08) -#define IO_BANK0_GPIO39_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x0a) -#define IO_BANK0_GPIO39_CTRL_FUNCSEL_VALUE_UART1_RX _u(0x0b) -#define IO_BANK0_GPIO39_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) -// ============================================================================= -// Register : IO_BANK0_GPIO40_STATUS -#define IO_BANK0_GPIO40_STATUS_OFFSET _u(0x00000140) -#define IO_BANK0_GPIO40_STATUS_BITS _u(0x04022200) -#define IO_BANK0_GPIO40_STATUS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO40_STATUS_IRQTOPROC -// Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO40_STATUS_IRQTOPROC_RESET _u(0x0) -#define IO_BANK0_GPIO40_STATUS_IRQTOPROC_BITS _u(0x04000000) -#define IO_BANK0_GPIO40_STATUS_IRQTOPROC_MSB _u(26) -#define IO_BANK0_GPIO40_STATUS_IRQTOPROC_LSB _u(26) -#define IO_BANK0_GPIO40_STATUS_IRQTOPROC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO40_STATUS_INFROMPAD -// Description : input signal from pad, before filtering and override are -// applied -#define IO_BANK0_GPIO40_STATUS_INFROMPAD_RESET _u(0x0) -#define IO_BANK0_GPIO40_STATUS_INFROMPAD_BITS _u(0x00020000) -#define IO_BANK0_GPIO40_STATUS_INFROMPAD_MSB _u(17) -#define IO_BANK0_GPIO40_STATUS_INFROMPAD_LSB _u(17) -#define IO_BANK0_GPIO40_STATUS_INFROMPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO40_STATUS_OETOPAD -// Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO40_STATUS_OETOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO40_STATUS_OETOPAD_BITS _u(0x00002000) -#define IO_BANK0_GPIO40_STATUS_OETOPAD_MSB _u(13) -#define IO_BANK0_GPIO40_STATUS_OETOPAD_LSB _u(13) -#define IO_BANK0_GPIO40_STATUS_OETOPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO40_STATUS_OUTTOPAD -// Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO40_STATUS_OUTTOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO40_STATUS_OUTTOPAD_BITS _u(0x00000200) -#define IO_BANK0_GPIO40_STATUS_OUTTOPAD_MSB _u(9) -#define IO_BANK0_GPIO40_STATUS_OUTTOPAD_LSB _u(9) -#define IO_BANK0_GPIO40_STATUS_OUTTOPAD_ACCESS "RO" -// ============================================================================= -// Register : IO_BANK0_GPIO40_CTRL -#define IO_BANK0_GPIO40_CTRL_OFFSET _u(0x00000144) -#define IO_BANK0_GPIO40_CTRL_BITS _u(0x3003f01f) -#define IO_BANK0_GPIO40_CTRL_RESET _u(0x0000001f) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO40_CTRL_IRQOVER -// 0x0 -> don't invert the interrupt -// 0x1 -> invert the interrupt -// 0x2 -> drive interrupt low -// 0x3 -> drive interrupt high -#define IO_BANK0_GPIO40_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO40_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO40_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO40_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO40_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO40_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO40_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO40_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO40_CTRL_IRQOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO40_CTRL_INOVER -// 0x0 -> don't invert the peri input -// 0x1 -> invert the peri input -// 0x2 -> drive peri input low -// 0x3 -> drive peri input high -#define IO_BANK0_GPIO40_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO40_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO40_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO40_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO40_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO40_CTRL_INOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO40_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO40_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO40_CTRL_INOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO40_CTRL_OEOVER -// 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel -// 0x2 -> disable output -// 0x3 -> enable output -#define IO_BANK0_GPIO40_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO40_CTRL_OEOVER_BITS _u(0x0000c000) -#define IO_BANK0_GPIO40_CTRL_OEOVER_MSB _u(15) -#define IO_BANK0_GPIO40_CTRL_OEOVER_LSB _u(14) -#define IO_BANK0_GPIO40_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO40_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO40_CTRL_OEOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO40_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO40_CTRL_OEOVER_VALUE_ENABLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO40_CTRL_OUTOVER -// 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel -// 0x2 -> drive output low -// 0x3 -> drive output high -#define IO_BANK0_GPIO40_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO40_CTRL_OUTOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO40_CTRL_OUTOVER_MSB _u(13) -#define IO_BANK0_GPIO40_CTRL_OUTOVER_LSB _u(12) -#define IO_BANK0_GPIO40_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO40_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO40_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO40_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO40_CTRL_OUTOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO40_CTRL_FUNCSEL -// Description : 0-31 -> selects pin function according to the gpio table -// 31 == NULL -// 0x01 -> spi1_rx -// 0x02 -> uart1_tx -// 0x03 -> i2c0_sda -// 0x04 -> pwm_a_8 -// 0x05 -> siob_proc_40 -// 0x06 -> pio0_40 -// 0x07 -> pio1_40 -// 0x08 -> pio2_40 -// 0x0a -> usb_muxing_vbus_detect -// 0x1f -> null -#define IO_BANK0_GPIO40_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO40_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO40_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO40_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO40_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO40_CTRL_FUNCSEL_VALUE_SPI1_RX _u(0x01) -#define IO_BANK0_GPIO40_CTRL_FUNCSEL_VALUE_UART1_TX _u(0x02) -#define IO_BANK0_GPIO40_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03) -#define IO_BANK0_GPIO40_CTRL_FUNCSEL_VALUE_PWM_A_8 _u(0x04) -#define IO_BANK0_GPIO40_CTRL_FUNCSEL_VALUE_SIOB_PROC_40 _u(0x05) -#define IO_BANK0_GPIO40_CTRL_FUNCSEL_VALUE_PIO0_40 _u(0x06) -#define IO_BANK0_GPIO40_CTRL_FUNCSEL_VALUE_PIO1_40 _u(0x07) -#define IO_BANK0_GPIO40_CTRL_FUNCSEL_VALUE_PIO2_40 _u(0x08) -#define IO_BANK0_GPIO40_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x0a) -#define IO_BANK0_GPIO40_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) -// ============================================================================= -// Register : IO_BANK0_GPIO41_STATUS -#define IO_BANK0_GPIO41_STATUS_OFFSET _u(0x00000148) -#define IO_BANK0_GPIO41_STATUS_BITS _u(0x04022200) -#define IO_BANK0_GPIO41_STATUS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO41_STATUS_IRQTOPROC -// Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO41_STATUS_IRQTOPROC_RESET _u(0x0) -#define IO_BANK0_GPIO41_STATUS_IRQTOPROC_BITS _u(0x04000000) -#define IO_BANK0_GPIO41_STATUS_IRQTOPROC_MSB _u(26) -#define IO_BANK0_GPIO41_STATUS_IRQTOPROC_LSB _u(26) -#define IO_BANK0_GPIO41_STATUS_IRQTOPROC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO41_STATUS_INFROMPAD -// Description : input signal from pad, before filtering and override are -// applied -#define IO_BANK0_GPIO41_STATUS_INFROMPAD_RESET _u(0x0) -#define IO_BANK0_GPIO41_STATUS_INFROMPAD_BITS _u(0x00020000) -#define IO_BANK0_GPIO41_STATUS_INFROMPAD_MSB _u(17) -#define IO_BANK0_GPIO41_STATUS_INFROMPAD_LSB _u(17) -#define IO_BANK0_GPIO41_STATUS_INFROMPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO41_STATUS_OETOPAD -// Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO41_STATUS_OETOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO41_STATUS_OETOPAD_BITS _u(0x00002000) -#define IO_BANK0_GPIO41_STATUS_OETOPAD_MSB _u(13) -#define IO_BANK0_GPIO41_STATUS_OETOPAD_LSB _u(13) -#define IO_BANK0_GPIO41_STATUS_OETOPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO41_STATUS_OUTTOPAD -// Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO41_STATUS_OUTTOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO41_STATUS_OUTTOPAD_BITS _u(0x00000200) -#define IO_BANK0_GPIO41_STATUS_OUTTOPAD_MSB _u(9) -#define IO_BANK0_GPIO41_STATUS_OUTTOPAD_LSB _u(9) -#define IO_BANK0_GPIO41_STATUS_OUTTOPAD_ACCESS "RO" -// ============================================================================= -// Register : IO_BANK0_GPIO41_CTRL -#define IO_BANK0_GPIO41_CTRL_OFFSET _u(0x0000014c) -#define IO_BANK0_GPIO41_CTRL_BITS _u(0x3003f01f) -#define IO_BANK0_GPIO41_CTRL_RESET _u(0x0000001f) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO41_CTRL_IRQOVER -// 0x0 -> don't invert the interrupt -// 0x1 -> invert the interrupt -// 0x2 -> drive interrupt low -// 0x3 -> drive interrupt high -#define IO_BANK0_GPIO41_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO41_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO41_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO41_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO41_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO41_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO41_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO41_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO41_CTRL_IRQOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO41_CTRL_INOVER -// 0x0 -> don't invert the peri input -// 0x1 -> invert the peri input -// 0x2 -> drive peri input low -// 0x3 -> drive peri input high -#define IO_BANK0_GPIO41_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO41_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO41_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO41_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO41_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO41_CTRL_INOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO41_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO41_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO41_CTRL_INOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO41_CTRL_OEOVER -// 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel -// 0x2 -> disable output -// 0x3 -> enable output -#define IO_BANK0_GPIO41_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO41_CTRL_OEOVER_BITS _u(0x0000c000) -#define IO_BANK0_GPIO41_CTRL_OEOVER_MSB _u(15) -#define IO_BANK0_GPIO41_CTRL_OEOVER_LSB _u(14) -#define IO_BANK0_GPIO41_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO41_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO41_CTRL_OEOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO41_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO41_CTRL_OEOVER_VALUE_ENABLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO41_CTRL_OUTOVER -// 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel -// 0x2 -> drive output low -// 0x3 -> drive output high -#define IO_BANK0_GPIO41_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO41_CTRL_OUTOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO41_CTRL_OUTOVER_MSB _u(13) -#define IO_BANK0_GPIO41_CTRL_OUTOVER_LSB _u(12) -#define IO_BANK0_GPIO41_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO41_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO41_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO41_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO41_CTRL_OUTOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO41_CTRL_FUNCSEL -// Description : 0-31 -> selects pin function according to the gpio table -// 31 == NULL -// 0x01 -> spi1_ss_n -// 0x02 -> uart1_rx -// 0x03 -> i2c0_scl -// 0x04 -> pwm_b_8 -// 0x05 -> siob_proc_41 -// 0x06 -> pio0_41 -// 0x07 -> pio1_41 -// 0x08 -> pio2_41 -// 0x0a -> usb_muxing_vbus_en -// 0x1f -> null -#define IO_BANK0_GPIO41_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO41_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO41_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO41_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO41_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO41_CTRL_FUNCSEL_VALUE_SPI1_SS_N _u(0x01) -#define IO_BANK0_GPIO41_CTRL_FUNCSEL_VALUE_UART1_RX _u(0x02) -#define IO_BANK0_GPIO41_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03) -#define IO_BANK0_GPIO41_CTRL_FUNCSEL_VALUE_PWM_B_8 _u(0x04) -#define IO_BANK0_GPIO41_CTRL_FUNCSEL_VALUE_SIOB_PROC_41 _u(0x05) -#define IO_BANK0_GPIO41_CTRL_FUNCSEL_VALUE_PIO0_41 _u(0x06) -#define IO_BANK0_GPIO41_CTRL_FUNCSEL_VALUE_PIO1_41 _u(0x07) -#define IO_BANK0_GPIO41_CTRL_FUNCSEL_VALUE_PIO2_41 _u(0x08) -#define IO_BANK0_GPIO41_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x0a) -#define IO_BANK0_GPIO41_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) -// ============================================================================= -// Register : IO_BANK0_GPIO42_STATUS -#define IO_BANK0_GPIO42_STATUS_OFFSET _u(0x00000150) -#define IO_BANK0_GPIO42_STATUS_BITS _u(0x04022200) -#define IO_BANK0_GPIO42_STATUS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO42_STATUS_IRQTOPROC -// Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO42_STATUS_IRQTOPROC_RESET _u(0x0) -#define IO_BANK0_GPIO42_STATUS_IRQTOPROC_BITS _u(0x04000000) -#define IO_BANK0_GPIO42_STATUS_IRQTOPROC_MSB _u(26) -#define IO_BANK0_GPIO42_STATUS_IRQTOPROC_LSB _u(26) -#define IO_BANK0_GPIO42_STATUS_IRQTOPROC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO42_STATUS_INFROMPAD -// Description : input signal from pad, before filtering and override are -// applied -#define IO_BANK0_GPIO42_STATUS_INFROMPAD_RESET _u(0x0) -#define IO_BANK0_GPIO42_STATUS_INFROMPAD_BITS _u(0x00020000) -#define IO_BANK0_GPIO42_STATUS_INFROMPAD_MSB _u(17) -#define IO_BANK0_GPIO42_STATUS_INFROMPAD_LSB _u(17) -#define IO_BANK0_GPIO42_STATUS_INFROMPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO42_STATUS_OETOPAD -// Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO42_STATUS_OETOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO42_STATUS_OETOPAD_BITS _u(0x00002000) -#define IO_BANK0_GPIO42_STATUS_OETOPAD_MSB _u(13) -#define IO_BANK0_GPIO42_STATUS_OETOPAD_LSB _u(13) -#define IO_BANK0_GPIO42_STATUS_OETOPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO42_STATUS_OUTTOPAD -// Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO42_STATUS_OUTTOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO42_STATUS_OUTTOPAD_BITS _u(0x00000200) -#define IO_BANK0_GPIO42_STATUS_OUTTOPAD_MSB _u(9) -#define IO_BANK0_GPIO42_STATUS_OUTTOPAD_LSB _u(9) -#define IO_BANK0_GPIO42_STATUS_OUTTOPAD_ACCESS "RO" -// ============================================================================= -// Register : IO_BANK0_GPIO42_CTRL -#define IO_BANK0_GPIO42_CTRL_OFFSET _u(0x00000154) -#define IO_BANK0_GPIO42_CTRL_BITS _u(0x3003f01f) -#define IO_BANK0_GPIO42_CTRL_RESET _u(0x0000001f) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO42_CTRL_IRQOVER -// 0x0 -> don't invert the interrupt -// 0x1 -> invert the interrupt -// 0x2 -> drive interrupt low -// 0x3 -> drive interrupt high -#define IO_BANK0_GPIO42_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO42_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO42_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO42_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO42_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO42_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO42_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO42_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO42_CTRL_IRQOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO42_CTRL_INOVER -// 0x0 -> don't invert the peri input -// 0x1 -> invert the peri input -// 0x2 -> drive peri input low -// 0x3 -> drive peri input high -#define IO_BANK0_GPIO42_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO42_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO42_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO42_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO42_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO42_CTRL_INOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO42_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO42_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO42_CTRL_INOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO42_CTRL_OEOVER -// 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel -// 0x2 -> disable output -// 0x3 -> enable output -#define IO_BANK0_GPIO42_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO42_CTRL_OEOVER_BITS _u(0x0000c000) -#define IO_BANK0_GPIO42_CTRL_OEOVER_MSB _u(15) -#define IO_BANK0_GPIO42_CTRL_OEOVER_LSB _u(14) -#define IO_BANK0_GPIO42_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO42_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO42_CTRL_OEOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO42_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO42_CTRL_OEOVER_VALUE_ENABLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO42_CTRL_OUTOVER -// 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel -// 0x2 -> drive output low -// 0x3 -> drive output high -#define IO_BANK0_GPIO42_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO42_CTRL_OUTOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO42_CTRL_OUTOVER_MSB _u(13) -#define IO_BANK0_GPIO42_CTRL_OUTOVER_LSB _u(12) -#define IO_BANK0_GPIO42_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO42_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO42_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO42_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO42_CTRL_OUTOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO42_CTRL_FUNCSEL -// Description : 0-31 -> selects pin function according to the gpio table -// 31 == NULL -// 0x01 -> spi1_sclk -// 0x02 -> uart1_cts -// 0x03 -> i2c1_sda -// 0x04 -> pwm_a_9 -// 0x05 -> siob_proc_42 -// 0x06 -> pio0_42 -// 0x07 -> pio1_42 -// 0x08 -> pio2_42 -// 0x0a -> usb_muxing_overcurr_detect -// 0x0b -> uart1_tx -// 0x1f -> null -#define IO_BANK0_GPIO42_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO42_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO42_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO42_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO42_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO42_CTRL_FUNCSEL_VALUE_SPI1_SCLK _u(0x01) -#define IO_BANK0_GPIO42_CTRL_FUNCSEL_VALUE_UART1_CTS _u(0x02) -#define IO_BANK0_GPIO42_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03) -#define IO_BANK0_GPIO42_CTRL_FUNCSEL_VALUE_PWM_A_9 _u(0x04) -#define IO_BANK0_GPIO42_CTRL_FUNCSEL_VALUE_SIOB_PROC_42 _u(0x05) -#define IO_BANK0_GPIO42_CTRL_FUNCSEL_VALUE_PIO0_42 _u(0x06) -#define IO_BANK0_GPIO42_CTRL_FUNCSEL_VALUE_PIO1_42 _u(0x07) -#define IO_BANK0_GPIO42_CTRL_FUNCSEL_VALUE_PIO2_42 _u(0x08) -#define IO_BANK0_GPIO42_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x0a) -#define IO_BANK0_GPIO42_CTRL_FUNCSEL_VALUE_UART1_TX _u(0x0b) -#define IO_BANK0_GPIO42_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) -// ============================================================================= -// Register : IO_BANK0_GPIO43_STATUS -#define IO_BANK0_GPIO43_STATUS_OFFSET _u(0x00000158) -#define IO_BANK0_GPIO43_STATUS_BITS _u(0x04022200) -#define IO_BANK0_GPIO43_STATUS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO43_STATUS_IRQTOPROC -// Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO43_STATUS_IRQTOPROC_RESET _u(0x0) -#define IO_BANK0_GPIO43_STATUS_IRQTOPROC_BITS _u(0x04000000) -#define IO_BANK0_GPIO43_STATUS_IRQTOPROC_MSB _u(26) -#define IO_BANK0_GPIO43_STATUS_IRQTOPROC_LSB _u(26) -#define IO_BANK0_GPIO43_STATUS_IRQTOPROC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO43_STATUS_INFROMPAD -// Description : input signal from pad, before filtering and override are -// applied -#define IO_BANK0_GPIO43_STATUS_INFROMPAD_RESET _u(0x0) -#define IO_BANK0_GPIO43_STATUS_INFROMPAD_BITS _u(0x00020000) -#define IO_BANK0_GPIO43_STATUS_INFROMPAD_MSB _u(17) -#define IO_BANK0_GPIO43_STATUS_INFROMPAD_LSB _u(17) -#define IO_BANK0_GPIO43_STATUS_INFROMPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO43_STATUS_OETOPAD -// Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO43_STATUS_OETOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO43_STATUS_OETOPAD_BITS _u(0x00002000) -#define IO_BANK0_GPIO43_STATUS_OETOPAD_MSB _u(13) -#define IO_BANK0_GPIO43_STATUS_OETOPAD_LSB _u(13) -#define IO_BANK0_GPIO43_STATUS_OETOPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO43_STATUS_OUTTOPAD -// Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO43_STATUS_OUTTOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO43_STATUS_OUTTOPAD_BITS _u(0x00000200) -#define IO_BANK0_GPIO43_STATUS_OUTTOPAD_MSB _u(9) -#define IO_BANK0_GPIO43_STATUS_OUTTOPAD_LSB _u(9) -#define IO_BANK0_GPIO43_STATUS_OUTTOPAD_ACCESS "RO" -// ============================================================================= -// Register : IO_BANK0_GPIO43_CTRL -#define IO_BANK0_GPIO43_CTRL_OFFSET _u(0x0000015c) -#define IO_BANK0_GPIO43_CTRL_BITS _u(0x3003f01f) -#define IO_BANK0_GPIO43_CTRL_RESET _u(0x0000001f) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO43_CTRL_IRQOVER -// 0x0 -> don't invert the interrupt -// 0x1 -> invert the interrupt -// 0x2 -> drive interrupt low -// 0x3 -> drive interrupt high -#define IO_BANK0_GPIO43_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO43_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO43_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO43_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO43_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO43_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO43_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO43_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO43_CTRL_IRQOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO43_CTRL_INOVER -// 0x0 -> don't invert the peri input -// 0x1 -> invert the peri input -// 0x2 -> drive peri input low -// 0x3 -> drive peri input high -#define IO_BANK0_GPIO43_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO43_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO43_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO43_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO43_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO43_CTRL_INOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO43_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO43_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO43_CTRL_INOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO43_CTRL_OEOVER -// 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel -// 0x2 -> disable output -// 0x3 -> enable output -#define IO_BANK0_GPIO43_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO43_CTRL_OEOVER_BITS _u(0x0000c000) -#define IO_BANK0_GPIO43_CTRL_OEOVER_MSB _u(15) -#define IO_BANK0_GPIO43_CTRL_OEOVER_LSB _u(14) -#define IO_BANK0_GPIO43_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO43_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO43_CTRL_OEOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO43_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO43_CTRL_OEOVER_VALUE_ENABLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO43_CTRL_OUTOVER -// 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel -// 0x2 -> drive output low -// 0x3 -> drive output high -#define IO_BANK0_GPIO43_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO43_CTRL_OUTOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO43_CTRL_OUTOVER_MSB _u(13) -#define IO_BANK0_GPIO43_CTRL_OUTOVER_LSB _u(12) -#define IO_BANK0_GPIO43_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO43_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO43_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO43_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO43_CTRL_OUTOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO43_CTRL_FUNCSEL -// Description : 0-31 -> selects pin function according to the gpio table -// 31 == NULL -// 0x01 -> spi1_tx -// 0x02 -> uart1_rts -// 0x03 -> i2c1_scl -// 0x04 -> pwm_b_9 -// 0x05 -> siob_proc_43 -// 0x06 -> pio0_43 -// 0x07 -> pio1_43 -// 0x08 -> pio2_43 -// 0x0a -> usb_muxing_vbus_detect -// 0x0b -> uart1_rx -// 0x1f -> null -#define IO_BANK0_GPIO43_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO43_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO43_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO43_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO43_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO43_CTRL_FUNCSEL_VALUE_SPI1_TX _u(0x01) -#define IO_BANK0_GPIO43_CTRL_FUNCSEL_VALUE_UART1_RTS _u(0x02) -#define IO_BANK0_GPIO43_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03) -#define IO_BANK0_GPIO43_CTRL_FUNCSEL_VALUE_PWM_B_9 _u(0x04) -#define IO_BANK0_GPIO43_CTRL_FUNCSEL_VALUE_SIOB_PROC_43 _u(0x05) -#define IO_BANK0_GPIO43_CTRL_FUNCSEL_VALUE_PIO0_43 _u(0x06) -#define IO_BANK0_GPIO43_CTRL_FUNCSEL_VALUE_PIO1_43 _u(0x07) -#define IO_BANK0_GPIO43_CTRL_FUNCSEL_VALUE_PIO2_43 _u(0x08) -#define IO_BANK0_GPIO43_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x0a) -#define IO_BANK0_GPIO43_CTRL_FUNCSEL_VALUE_UART1_RX _u(0x0b) -#define IO_BANK0_GPIO43_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) -// ============================================================================= -// Register : IO_BANK0_GPIO44_STATUS -#define IO_BANK0_GPIO44_STATUS_OFFSET _u(0x00000160) -#define IO_BANK0_GPIO44_STATUS_BITS _u(0x04022200) -#define IO_BANK0_GPIO44_STATUS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO44_STATUS_IRQTOPROC -// Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO44_STATUS_IRQTOPROC_RESET _u(0x0) -#define IO_BANK0_GPIO44_STATUS_IRQTOPROC_BITS _u(0x04000000) -#define IO_BANK0_GPIO44_STATUS_IRQTOPROC_MSB _u(26) -#define IO_BANK0_GPIO44_STATUS_IRQTOPROC_LSB _u(26) -#define IO_BANK0_GPIO44_STATUS_IRQTOPROC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO44_STATUS_INFROMPAD -// Description : input signal from pad, before filtering and override are -// applied -#define IO_BANK0_GPIO44_STATUS_INFROMPAD_RESET _u(0x0) -#define IO_BANK0_GPIO44_STATUS_INFROMPAD_BITS _u(0x00020000) -#define IO_BANK0_GPIO44_STATUS_INFROMPAD_MSB _u(17) -#define IO_BANK0_GPIO44_STATUS_INFROMPAD_LSB _u(17) -#define IO_BANK0_GPIO44_STATUS_INFROMPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO44_STATUS_OETOPAD -// Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO44_STATUS_OETOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO44_STATUS_OETOPAD_BITS _u(0x00002000) -#define IO_BANK0_GPIO44_STATUS_OETOPAD_MSB _u(13) -#define IO_BANK0_GPIO44_STATUS_OETOPAD_LSB _u(13) -#define IO_BANK0_GPIO44_STATUS_OETOPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO44_STATUS_OUTTOPAD -// Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO44_STATUS_OUTTOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO44_STATUS_OUTTOPAD_BITS _u(0x00000200) -#define IO_BANK0_GPIO44_STATUS_OUTTOPAD_MSB _u(9) -#define IO_BANK0_GPIO44_STATUS_OUTTOPAD_LSB _u(9) -#define IO_BANK0_GPIO44_STATUS_OUTTOPAD_ACCESS "RO" -// ============================================================================= -// Register : IO_BANK0_GPIO44_CTRL -#define IO_BANK0_GPIO44_CTRL_OFFSET _u(0x00000164) -#define IO_BANK0_GPIO44_CTRL_BITS _u(0x3003f01f) -#define IO_BANK0_GPIO44_CTRL_RESET _u(0x0000001f) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO44_CTRL_IRQOVER -// 0x0 -> don't invert the interrupt -// 0x1 -> invert the interrupt -// 0x2 -> drive interrupt low -// 0x3 -> drive interrupt high -#define IO_BANK0_GPIO44_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO44_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO44_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO44_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO44_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO44_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO44_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO44_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO44_CTRL_IRQOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO44_CTRL_INOVER -// 0x0 -> don't invert the peri input -// 0x1 -> invert the peri input -// 0x2 -> drive peri input low -// 0x3 -> drive peri input high -#define IO_BANK0_GPIO44_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO44_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO44_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO44_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO44_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO44_CTRL_INOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO44_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO44_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO44_CTRL_INOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO44_CTRL_OEOVER -// 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel -// 0x2 -> disable output -// 0x3 -> enable output -#define IO_BANK0_GPIO44_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO44_CTRL_OEOVER_BITS _u(0x0000c000) -#define IO_BANK0_GPIO44_CTRL_OEOVER_MSB _u(15) -#define IO_BANK0_GPIO44_CTRL_OEOVER_LSB _u(14) -#define IO_BANK0_GPIO44_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO44_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO44_CTRL_OEOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO44_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO44_CTRL_OEOVER_VALUE_ENABLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO44_CTRL_OUTOVER -// 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel -// 0x2 -> drive output low -// 0x3 -> drive output high -#define IO_BANK0_GPIO44_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO44_CTRL_OUTOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO44_CTRL_OUTOVER_MSB _u(13) -#define IO_BANK0_GPIO44_CTRL_OUTOVER_LSB _u(12) -#define IO_BANK0_GPIO44_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO44_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO44_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO44_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO44_CTRL_OUTOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO44_CTRL_FUNCSEL -// Description : 0-31 -> selects pin function according to the gpio table -// 31 == NULL -// 0x01 -> spi1_rx -// 0x02 -> uart0_tx -// 0x03 -> i2c0_sda -// 0x04 -> pwm_a_10 -// 0x05 -> siob_proc_44 -// 0x06 -> pio0_44 -// 0x07 -> pio1_44 -// 0x08 -> pio2_44 -// 0x0a -> usb_muxing_vbus_en -// 0x1f -> null -#define IO_BANK0_GPIO44_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO44_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO44_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO44_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO44_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO44_CTRL_FUNCSEL_VALUE_SPI1_RX _u(0x01) -#define IO_BANK0_GPIO44_CTRL_FUNCSEL_VALUE_UART0_TX _u(0x02) -#define IO_BANK0_GPIO44_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03) -#define IO_BANK0_GPIO44_CTRL_FUNCSEL_VALUE_PWM_A_10 _u(0x04) -#define IO_BANK0_GPIO44_CTRL_FUNCSEL_VALUE_SIOB_PROC_44 _u(0x05) -#define IO_BANK0_GPIO44_CTRL_FUNCSEL_VALUE_PIO0_44 _u(0x06) -#define IO_BANK0_GPIO44_CTRL_FUNCSEL_VALUE_PIO1_44 _u(0x07) -#define IO_BANK0_GPIO44_CTRL_FUNCSEL_VALUE_PIO2_44 _u(0x08) -#define IO_BANK0_GPIO44_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x0a) -#define IO_BANK0_GPIO44_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) -// ============================================================================= -// Register : IO_BANK0_GPIO45_STATUS -#define IO_BANK0_GPIO45_STATUS_OFFSET _u(0x00000168) -#define IO_BANK0_GPIO45_STATUS_BITS _u(0x04022200) -#define IO_BANK0_GPIO45_STATUS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO45_STATUS_IRQTOPROC -// Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO45_STATUS_IRQTOPROC_RESET _u(0x0) -#define IO_BANK0_GPIO45_STATUS_IRQTOPROC_BITS _u(0x04000000) -#define IO_BANK0_GPIO45_STATUS_IRQTOPROC_MSB _u(26) -#define IO_BANK0_GPIO45_STATUS_IRQTOPROC_LSB _u(26) -#define IO_BANK0_GPIO45_STATUS_IRQTOPROC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO45_STATUS_INFROMPAD -// Description : input signal from pad, before filtering and override are -// applied -#define IO_BANK0_GPIO45_STATUS_INFROMPAD_RESET _u(0x0) -#define IO_BANK0_GPIO45_STATUS_INFROMPAD_BITS _u(0x00020000) -#define IO_BANK0_GPIO45_STATUS_INFROMPAD_MSB _u(17) -#define IO_BANK0_GPIO45_STATUS_INFROMPAD_LSB _u(17) -#define IO_BANK0_GPIO45_STATUS_INFROMPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO45_STATUS_OETOPAD -// Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO45_STATUS_OETOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO45_STATUS_OETOPAD_BITS _u(0x00002000) -#define IO_BANK0_GPIO45_STATUS_OETOPAD_MSB _u(13) -#define IO_BANK0_GPIO45_STATUS_OETOPAD_LSB _u(13) -#define IO_BANK0_GPIO45_STATUS_OETOPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO45_STATUS_OUTTOPAD -// Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO45_STATUS_OUTTOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO45_STATUS_OUTTOPAD_BITS _u(0x00000200) -#define IO_BANK0_GPIO45_STATUS_OUTTOPAD_MSB _u(9) -#define IO_BANK0_GPIO45_STATUS_OUTTOPAD_LSB _u(9) -#define IO_BANK0_GPIO45_STATUS_OUTTOPAD_ACCESS "RO" -// ============================================================================= -// Register : IO_BANK0_GPIO45_CTRL -#define IO_BANK0_GPIO45_CTRL_OFFSET _u(0x0000016c) -#define IO_BANK0_GPIO45_CTRL_BITS _u(0x3003f01f) -#define IO_BANK0_GPIO45_CTRL_RESET _u(0x0000001f) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO45_CTRL_IRQOVER -// 0x0 -> don't invert the interrupt -// 0x1 -> invert the interrupt -// 0x2 -> drive interrupt low -// 0x3 -> drive interrupt high -#define IO_BANK0_GPIO45_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO45_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO45_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO45_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO45_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO45_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO45_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO45_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO45_CTRL_IRQOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO45_CTRL_INOVER -// 0x0 -> don't invert the peri input -// 0x1 -> invert the peri input -// 0x2 -> drive peri input low -// 0x3 -> drive peri input high -#define IO_BANK0_GPIO45_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO45_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO45_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO45_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO45_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO45_CTRL_INOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO45_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO45_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO45_CTRL_INOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO45_CTRL_OEOVER -// 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel -// 0x2 -> disable output -// 0x3 -> enable output -#define IO_BANK0_GPIO45_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO45_CTRL_OEOVER_BITS _u(0x0000c000) -#define IO_BANK0_GPIO45_CTRL_OEOVER_MSB _u(15) -#define IO_BANK0_GPIO45_CTRL_OEOVER_LSB _u(14) -#define IO_BANK0_GPIO45_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO45_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO45_CTRL_OEOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO45_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO45_CTRL_OEOVER_VALUE_ENABLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO45_CTRL_OUTOVER -// 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel -// 0x2 -> drive output low -// 0x3 -> drive output high -#define IO_BANK0_GPIO45_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO45_CTRL_OUTOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO45_CTRL_OUTOVER_MSB _u(13) -#define IO_BANK0_GPIO45_CTRL_OUTOVER_LSB _u(12) -#define IO_BANK0_GPIO45_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO45_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO45_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO45_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO45_CTRL_OUTOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO45_CTRL_FUNCSEL -// Description : 0-31 -> selects pin function according to the gpio table -// 31 == NULL -// 0x01 -> spi1_ss_n -// 0x02 -> uart0_rx -// 0x03 -> i2c0_scl -// 0x04 -> pwm_b_10 -// 0x05 -> siob_proc_45 -// 0x06 -> pio0_45 -// 0x07 -> pio1_45 -// 0x08 -> pio2_45 -// 0x0a -> usb_muxing_overcurr_detect -// 0x1f -> null -#define IO_BANK0_GPIO45_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO45_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO45_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO45_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO45_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO45_CTRL_FUNCSEL_VALUE_SPI1_SS_N _u(0x01) -#define IO_BANK0_GPIO45_CTRL_FUNCSEL_VALUE_UART0_RX _u(0x02) -#define IO_BANK0_GPIO45_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03) -#define IO_BANK0_GPIO45_CTRL_FUNCSEL_VALUE_PWM_B_10 _u(0x04) -#define IO_BANK0_GPIO45_CTRL_FUNCSEL_VALUE_SIOB_PROC_45 _u(0x05) -#define IO_BANK0_GPIO45_CTRL_FUNCSEL_VALUE_PIO0_45 _u(0x06) -#define IO_BANK0_GPIO45_CTRL_FUNCSEL_VALUE_PIO1_45 _u(0x07) -#define IO_BANK0_GPIO45_CTRL_FUNCSEL_VALUE_PIO2_45 _u(0x08) -#define IO_BANK0_GPIO45_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x0a) -#define IO_BANK0_GPIO45_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) -// ============================================================================= -// Register : IO_BANK0_GPIO46_STATUS -#define IO_BANK0_GPIO46_STATUS_OFFSET _u(0x00000170) -#define IO_BANK0_GPIO46_STATUS_BITS _u(0x04022200) -#define IO_BANK0_GPIO46_STATUS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO46_STATUS_IRQTOPROC -// Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO46_STATUS_IRQTOPROC_RESET _u(0x0) -#define IO_BANK0_GPIO46_STATUS_IRQTOPROC_BITS _u(0x04000000) -#define IO_BANK0_GPIO46_STATUS_IRQTOPROC_MSB _u(26) -#define IO_BANK0_GPIO46_STATUS_IRQTOPROC_LSB _u(26) -#define IO_BANK0_GPIO46_STATUS_IRQTOPROC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO46_STATUS_INFROMPAD -// Description : input signal from pad, before filtering and override are -// applied -#define IO_BANK0_GPIO46_STATUS_INFROMPAD_RESET _u(0x0) -#define IO_BANK0_GPIO46_STATUS_INFROMPAD_BITS _u(0x00020000) -#define IO_BANK0_GPIO46_STATUS_INFROMPAD_MSB _u(17) -#define IO_BANK0_GPIO46_STATUS_INFROMPAD_LSB _u(17) -#define IO_BANK0_GPIO46_STATUS_INFROMPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO46_STATUS_OETOPAD -// Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO46_STATUS_OETOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO46_STATUS_OETOPAD_BITS _u(0x00002000) -#define IO_BANK0_GPIO46_STATUS_OETOPAD_MSB _u(13) -#define IO_BANK0_GPIO46_STATUS_OETOPAD_LSB _u(13) -#define IO_BANK0_GPIO46_STATUS_OETOPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO46_STATUS_OUTTOPAD -// Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO46_STATUS_OUTTOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO46_STATUS_OUTTOPAD_BITS _u(0x00000200) -#define IO_BANK0_GPIO46_STATUS_OUTTOPAD_MSB _u(9) -#define IO_BANK0_GPIO46_STATUS_OUTTOPAD_LSB _u(9) -#define IO_BANK0_GPIO46_STATUS_OUTTOPAD_ACCESS "RO" -// ============================================================================= -// Register : IO_BANK0_GPIO46_CTRL -#define IO_BANK0_GPIO46_CTRL_OFFSET _u(0x00000174) -#define IO_BANK0_GPIO46_CTRL_BITS _u(0x3003f01f) -#define IO_BANK0_GPIO46_CTRL_RESET _u(0x0000001f) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO46_CTRL_IRQOVER -// 0x0 -> don't invert the interrupt -// 0x1 -> invert the interrupt -// 0x2 -> drive interrupt low -// 0x3 -> drive interrupt high -#define IO_BANK0_GPIO46_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO46_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO46_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO46_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO46_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO46_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO46_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO46_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO46_CTRL_IRQOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO46_CTRL_INOVER -// 0x0 -> don't invert the peri input -// 0x1 -> invert the peri input -// 0x2 -> drive peri input low -// 0x3 -> drive peri input high -#define IO_BANK0_GPIO46_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO46_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO46_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO46_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO46_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO46_CTRL_INOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO46_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO46_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO46_CTRL_INOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO46_CTRL_OEOVER -// 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel -// 0x2 -> disable output -// 0x3 -> enable output -#define IO_BANK0_GPIO46_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO46_CTRL_OEOVER_BITS _u(0x0000c000) -#define IO_BANK0_GPIO46_CTRL_OEOVER_MSB _u(15) -#define IO_BANK0_GPIO46_CTRL_OEOVER_LSB _u(14) -#define IO_BANK0_GPIO46_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO46_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO46_CTRL_OEOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO46_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO46_CTRL_OEOVER_VALUE_ENABLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO46_CTRL_OUTOVER -// 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel -// 0x2 -> drive output low -// 0x3 -> drive output high -#define IO_BANK0_GPIO46_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO46_CTRL_OUTOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO46_CTRL_OUTOVER_MSB _u(13) -#define IO_BANK0_GPIO46_CTRL_OUTOVER_LSB _u(12) -#define IO_BANK0_GPIO46_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO46_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO46_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO46_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO46_CTRL_OUTOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO46_CTRL_FUNCSEL -// Description : 0-31 -> selects pin function according to the gpio table -// 31 == NULL -// 0x01 -> spi1_sclk -// 0x02 -> uart0_cts -// 0x03 -> i2c1_sda -// 0x04 -> pwm_a_11 -// 0x05 -> siob_proc_46 -// 0x06 -> pio0_46 -// 0x07 -> pio1_46 -// 0x08 -> pio2_46 -// 0x0a -> usb_muxing_vbus_detect -// 0x0b -> uart0_tx -// 0x1f -> null -#define IO_BANK0_GPIO46_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO46_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO46_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO46_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO46_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO46_CTRL_FUNCSEL_VALUE_SPI1_SCLK _u(0x01) -#define IO_BANK0_GPIO46_CTRL_FUNCSEL_VALUE_UART0_CTS _u(0x02) -#define IO_BANK0_GPIO46_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03) -#define IO_BANK0_GPIO46_CTRL_FUNCSEL_VALUE_PWM_A_11 _u(0x04) -#define IO_BANK0_GPIO46_CTRL_FUNCSEL_VALUE_SIOB_PROC_46 _u(0x05) -#define IO_BANK0_GPIO46_CTRL_FUNCSEL_VALUE_PIO0_46 _u(0x06) -#define IO_BANK0_GPIO46_CTRL_FUNCSEL_VALUE_PIO1_46 _u(0x07) -#define IO_BANK0_GPIO46_CTRL_FUNCSEL_VALUE_PIO2_46 _u(0x08) -#define IO_BANK0_GPIO46_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x0a) -#define IO_BANK0_GPIO46_CTRL_FUNCSEL_VALUE_UART0_TX _u(0x0b) -#define IO_BANK0_GPIO46_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) -// ============================================================================= -// Register : IO_BANK0_GPIO47_STATUS -#define IO_BANK0_GPIO47_STATUS_OFFSET _u(0x00000178) -#define IO_BANK0_GPIO47_STATUS_BITS _u(0x04022200) -#define IO_BANK0_GPIO47_STATUS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO47_STATUS_IRQTOPROC -// Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO47_STATUS_IRQTOPROC_RESET _u(0x0) -#define IO_BANK0_GPIO47_STATUS_IRQTOPROC_BITS _u(0x04000000) -#define IO_BANK0_GPIO47_STATUS_IRQTOPROC_MSB _u(26) -#define IO_BANK0_GPIO47_STATUS_IRQTOPROC_LSB _u(26) -#define IO_BANK0_GPIO47_STATUS_IRQTOPROC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO47_STATUS_INFROMPAD -// Description : input signal from pad, before filtering and override are -// applied -#define IO_BANK0_GPIO47_STATUS_INFROMPAD_RESET _u(0x0) -#define IO_BANK0_GPIO47_STATUS_INFROMPAD_BITS _u(0x00020000) -#define IO_BANK0_GPIO47_STATUS_INFROMPAD_MSB _u(17) -#define IO_BANK0_GPIO47_STATUS_INFROMPAD_LSB _u(17) -#define IO_BANK0_GPIO47_STATUS_INFROMPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO47_STATUS_OETOPAD -// Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO47_STATUS_OETOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO47_STATUS_OETOPAD_BITS _u(0x00002000) -#define IO_BANK0_GPIO47_STATUS_OETOPAD_MSB _u(13) -#define IO_BANK0_GPIO47_STATUS_OETOPAD_LSB _u(13) -#define IO_BANK0_GPIO47_STATUS_OETOPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO47_STATUS_OUTTOPAD -// Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO47_STATUS_OUTTOPAD_RESET _u(0x0) -#define IO_BANK0_GPIO47_STATUS_OUTTOPAD_BITS _u(0x00000200) -#define IO_BANK0_GPIO47_STATUS_OUTTOPAD_MSB _u(9) -#define IO_BANK0_GPIO47_STATUS_OUTTOPAD_LSB _u(9) -#define IO_BANK0_GPIO47_STATUS_OUTTOPAD_ACCESS "RO" -// ============================================================================= -// Register : IO_BANK0_GPIO47_CTRL -#define IO_BANK0_GPIO47_CTRL_OFFSET _u(0x0000017c) -#define IO_BANK0_GPIO47_CTRL_BITS _u(0x3003f01f) -#define IO_BANK0_GPIO47_CTRL_RESET _u(0x0000001f) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO47_CTRL_IRQOVER -// 0x0 -> don't invert the interrupt -// 0x1 -> invert the interrupt -// 0x2 -> drive interrupt low -// 0x3 -> drive interrupt high -#define IO_BANK0_GPIO47_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO47_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO47_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO47_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO47_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO47_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO47_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO47_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO47_CTRL_IRQOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO47_CTRL_INOVER -// 0x0 -> don't invert the peri input -// 0x1 -> invert the peri input -// 0x2 -> drive peri input low -// 0x3 -> drive peri input high -#define IO_BANK0_GPIO47_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO47_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO47_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO47_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO47_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO47_CTRL_INOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO47_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO47_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO47_CTRL_INOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO47_CTRL_OEOVER -// 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel -// 0x2 -> disable output -// 0x3 -> enable output -#define IO_BANK0_GPIO47_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO47_CTRL_OEOVER_BITS _u(0x0000c000) -#define IO_BANK0_GPIO47_CTRL_OEOVER_MSB _u(15) -#define IO_BANK0_GPIO47_CTRL_OEOVER_LSB _u(14) -#define IO_BANK0_GPIO47_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO47_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO47_CTRL_OEOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO47_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO47_CTRL_OEOVER_VALUE_ENABLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO47_CTRL_OUTOVER -// 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel -// 0x2 -> drive output low -// 0x3 -> drive output high -#define IO_BANK0_GPIO47_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO47_CTRL_OUTOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO47_CTRL_OUTOVER_MSB _u(13) -#define IO_BANK0_GPIO47_CTRL_OUTOVER_LSB _u(12) -#define IO_BANK0_GPIO47_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO47_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO47_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO47_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO47_CTRL_OUTOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_GPIO47_CTRL_FUNCSEL -// Description : 0-31 -> selects pin function according to the gpio table -// 31 == NULL -// 0x01 -> spi1_tx -// 0x02 -> uart0_rts -// 0x03 -> i2c1_scl -// 0x04 -> pwm_b_11 -// 0x05 -> siob_proc_47 -// 0x06 -> pio0_47 -// 0x07 -> pio1_47 -// 0x08 -> pio2_47 -// 0x09 -> xip_ss_n_1 -// 0x0a -> usb_muxing_vbus_en -// 0x0b -> uart0_rx -// 0x1f -> null -#define IO_BANK0_GPIO47_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO47_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO47_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO47_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO47_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO47_CTRL_FUNCSEL_VALUE_SPI1_TX _u(0x01) -#define IO_BANK0_GPIO47_CTRL_FUNCSEL_VALUE_UART0_RTS _u(0x02) -#define IO_BANK0_GPIO47_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03) -#define IO_BANK0_GPIO47_CTRL_FUNCSEL_VALUE_PWM_B_11 _u(0x04) -#define IO_BANK0_GPIO47_CTRL_FUNCSEL_VALUE_SIOB_PROC_47 _u(0x05) -#define IO_BANK0_GPIO47_CTRL_FUNCSEL_VALUE_PIO0_47 _u(0x06) -#define IO_BANK0_GPIO47_CTRL_FUNCSEL_VALUE_PIO1_47 _u(0x07) -#define IO_BANK0_GPIO47_CTRL_FUNCSEL_VALUE_PIO2_47 _u(0x08) -#define IO_BANK0_GPIO47_CTRL_FUNCSEL_VALUE_XIP_SS_N_1 _u(0x09) -#define IO_BANK0_GPIO47_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x0a) -#define IO_BANK0_GPIO47_CTRL_FUNCSEL_VALUE_UART0_RX _u(0x0b) -#define IO_BANK0_GPIO47_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) -// ============================================================================= -// Register : IO_BANK0_IRQSUMMARY_PROC0_SECURE0 -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_OFFSET _u(0x00000200) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_BITS _u(0xffffffff) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO31 -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO31_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO31_BITS _u(0x80000000) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO31_MSB _u(31) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO31_LSB _u(31) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO31_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO30 -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO30_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO30_BITS _u(0x40000000) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO30_MSB _u(30) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO30_LSB _u(30) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO30_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO29 -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO29_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO29_BITS _u(0x20000000) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO29_MSB _u(29) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO29_LSB _u(29) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO29_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO28 -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO28_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO28_BITS _u(0x10000000) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO28_MSB _u(28) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO28_LSB _u(28) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO28_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO27 -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO27_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO27_BITS _u(0x08000000) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO27_MSB _u(27) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO27_LSB _u(27) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO27_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO26 -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO26_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO26_BITS _u(0x04000000) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO26_MSB _u(26) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO26_LSB _u(26) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO26_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO25 -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO25_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO25_BITS _u(0x02000000) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO25_MSB _u(25) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO25_LSB _u(25) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO25_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO24 -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO24_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO24_BITS _u(0x01000000) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO24_MSB _u(24) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO24_LSB _u(24) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO24_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO23 -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO23_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO23_BITS _u(0x00800000) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO23_MSB _u(23) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO23_LSB _u(23) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO23_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO22 -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO22_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO22_BITS _u(0x00400000) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO22_MSB _u(22) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO22_LSB _u(22) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO22_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO21 -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO21_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO21_BITS _u(0x00200000) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO21_MSB _u(21) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO21_LSB _u(21) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO21_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO20 -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO20_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO20_BITS _u(0x00100000) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO20_MSB _u(20) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO20_LSB _u(20) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO20_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO19 -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO19_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO19_BITS _u(0x00080000) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO19_MSB _u(19) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO19_LSB _u(19) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO19_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO18 -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO18_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO18_BITS _u(0x00040000) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO18_MSB _u(18) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO18_LSB _u(18) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO18_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO17 -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO17_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO17_BITS _u(0x00020000) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO17_MSB _u(17) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO17_LSB _u(17) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO17_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO16 -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO16_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO16_BITS _u(0x00010000) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO16_MSB _u(16) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO16_LSB _u(16) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO16_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO15 -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO15_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO15_BITS _u(0x00008000) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO15_MSB _u(15) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO15_LSB _u(15) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO15_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO14 -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO14_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO14_BITS _u(0x00004000) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO14_MSB _u(14) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO14_LSB _u(14) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO14_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO13 -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO13_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO13_BITS _u(0x00002000) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO13_MSB _u(13) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO13_LSB _u(13) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO13_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO12 -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO12_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO12_BITS _u(0x00001000) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO12_MSB _u(12) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO12_LSB _u(12) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO12_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO11 -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO11_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO11_BITS _u(0x00000800) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO11_MSB _u(11) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO11_LSB _u(11) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO11_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO10 -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO10_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO10_BITS _u(0x00000400) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO10_MSB _u(10) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO10_LSB _u(10) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO10_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO9 -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO9_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO9_BITS _u(0x00000200) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO9_MSB _u(9) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO9_LSB _u(9) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO9_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO8 -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO8_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO8_BITS _u(0x00000100) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO8_MSB _u(8) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO8_LSB _u(8) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO8_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO7 -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO7_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO7_BITS _u(0x00000080) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO7_MSB _u(7) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO7_LSB _u(7) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO7_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO6 -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO6_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO6_BITS _u(0x00000040) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO6_MSB _u(6) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO6_LSB _u(6) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO6_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO5 -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO5_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO5_BITS _u(0x00000020) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO5_MSB _u(5) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO5_LSB _u(5) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO5_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO4 -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO4_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO4_BITS _u(0x00000010) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO4_MSB _u(4) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO4_LSB _u(4) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO4_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO3 -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO3_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO3_BITS _u(0x00000008) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO3_MSB _u(3) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO3_LSB _u(3) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO3_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO2 -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO2_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO2_BITS _u(0x00000004) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO2_MSB _u(2) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO2_LSB _u(2) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO1 -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO1_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO1_BITS _u(0x00000002) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO1_MSB _u(1) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO1_LSB _u(1) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO0 -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO0_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO0_BITS _u(0x00000001) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO0_MSB _u(0) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO0_LSB _u(0) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO0_ACCESS "RO" -// ============================================================================= -// Register : IO_BANK0_IRQSUMMARY_PROC0_SECURE1 -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_OFFSET _u(0x00000204) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_BITS _u(0x0000ffff) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO47 -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO47_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO47_BITS _u(0x00008000) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO47_MSB _u(15) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO47_LSB _u(15) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO47_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO46 -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO46_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO46_BITS _u(0x00004000) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO46_MSB _u(14) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO46_LSB _u(14) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO46_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO45 -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO45_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO45_BITS _u(0x00002000) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO45_MSB _u(13) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO45_LSB _u(13) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO45_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO44 -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO44_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO44_BITS _u(0x00001000) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO44_MSB _u(12) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO44_LSB _u(12) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO44_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO43 -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO43_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO43_BITS _u(0x00000800) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO43_MSB _u(11) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO43_LSB _u(11) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO43_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO42 -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO42_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO42_BITS _u(0x00000400) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO42_MSB _u(10) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO42_LSB _u(10) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO42_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO41 -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO41_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO41_BITS _u(0x00000200) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO41_MSB _u(9) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO41_LSB _u(9) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO41_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO40 -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO40_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO40_BITS _u(0x00000100) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO40_MSB _u(8) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO40_LSB _u(8) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO40_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO39 -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO39_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO39_BITS _u(0x00000080) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO39_MSB _u(7) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO39_LSB _u(7) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO39_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO38 -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO38_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO38_BITS _u(0x00000040) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO38_MSB _u(6) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO38_LSB _u(6) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO38_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO37 -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO37_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO37_BITS _u(0x00000020) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO37_MSB _u(5) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO37_LSB _u(5) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO37_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO36 -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO36_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO36_BITS _u(0x00000010) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO36_MSB _u(4) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO36_LSB _u(4) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO36_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO35 -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO35_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO35_BITS _u(0x00000008) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO35_MSB _u(3) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO35_LSB _u(3) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO35_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO34 -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO34_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO34_BITS _u(0x00000004) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO34_MSB _u(2) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO34_LSB _u(2) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO34_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO33 -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO33_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO33_BITS _u(0x00000002) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO33_MSB _u(1) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO33_LSB _u(1) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO33_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO32 -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO32_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO32_BITS _u(0x00000001) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO32_MSB _u(0) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO32_LSB _u(0) -#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO32_ACCESS "RO" -// ============================================================================= -// Register : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0 -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_OFFSET _u(0x00000208) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_BITS _u(0xffffffff) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO31 -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO31_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO31_BITS _u(0x80000000) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO31_MSB _u(31) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO31_LSB _u(31) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO31_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO30 -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO30_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO30_BITS _u(0x40000000) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO30_MSB _u(30) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO30_LSB _u(30) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO30_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO29 -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO29_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO29_BITS _u(0x20000000) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO29_MSB _u(29) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO29_LSB _u(29) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO29_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO28 -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO28_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO28_BITS _u(0x10000000) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO28_MSB _u(28) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO28_LSB _u(28) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO28_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO27 -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO27_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO27_BITS _u(0x08000000) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO27_MSB _u(27) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO27_LSB _u(27) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO27_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO26 -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO26_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO26_BITS _u(0x04000000) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO26_MSB _u(26) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO26_LSB _u(26) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO26_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO25 -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO25_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO25_BITS _u(0x02000000) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO25_MSB _u(25) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO25_LSB _u(25) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO25_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO24 -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO24_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO24_BITS _u(0x01000000) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO24_MSB _u(24) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO24_LSB _u(24) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO24_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO23 -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO23_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO23_BITS _u(0x00800000) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO23_MSB _u(23) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO23_LSB _u(23) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO23_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO22 -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO22_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO22_BITS _u(0x00400000) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO22_MSB _u(22) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO22_LSB _u(22) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO22_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO21 -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO21_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO21_BITS _u(0x00200000) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO21_MSB _u(21) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO21_LSB _u(21) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO21_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO20 -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO20_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO20_BITS _u(0x00100000) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO20_MSB _u(20) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO20_LSB _u(20) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO20_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO19 -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO19_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO19_BITS _u(0x00080000) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO19_MSB _u(19) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO19_LSB _u(19) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO19_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO18 -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO18_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO18_BITS _u(0x00040000) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO18_MSB _u(18) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO18_LSB _u(18) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO18_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO17 -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO17_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO17_BITS _u(0x00020000) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO17_MSB _u(17) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO17_LSB _u(17) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO17_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO16 -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO16_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO16_BITS _u(0x00010000) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO16_MSB _u(16) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO16_LSB _u(16) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO16_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO15 -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO15_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO15_BITS _u(0x00008000) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO15_MSB _u(15) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO15_LSB _u(15) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO15_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO14 -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO14_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO14_BITS _u(0x00004000) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO14_MSB _u(14) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO14_LSB _u(14) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO14_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO13 -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO13_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO13_BITS _u(0x00002000) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO13_MSB _u(13) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO13_LSB _u(13) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO13_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO12 -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO12_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO12_BITS _u(0x00001000) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO12_MSB _u(12) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO12_LSB _u(12) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO12_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO11 -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO11_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO11_BITS _u(0x00000800) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO11_MSB _u(11) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO11_LSB _u(11) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO11_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO10 -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO10_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO10_BITS _u(0x00000400) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO10_MSB _u(10) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO10_LSB _u(10) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO10_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO9 -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO9_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO9_BITS _u(0x00000200) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO9_MSB _u(9) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO9_LSB _u(9) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO9_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO8 -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO8_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO8_BITS _u(0x00000100) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO8_MSB _u(8) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO8_LSB _u(8) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO8_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO7 -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO7_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO7_BITS _u(0x00000080) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO7_MSB _u(7) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO7_LSB _u(7) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO7_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO6 -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO6_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO6_BITS _u(0x00000040) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO6_MSB _u(6) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO6_LSB _u(6) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO6_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO5 -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO5_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO5_BITS _u(0x00000020) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO5_MSB _u(5) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO5_LSB _u(5) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO5_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO4 -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO4_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO4_BITS _u(0x00000010) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO4_MSB _u(4) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO4_LSB _u(4) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO4_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO3 -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO3_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO3_BITS _u(0x00000008) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO3_MSB _u(3) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO3_LSB _u(3) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO3_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO2 -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO2_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO2_BITS _u(0x00000004) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO2_MSB _u(2) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO2_LSB _u(2) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO1 -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO1_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO1_BITS _u(0x00000002) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO1_MSB _u(1) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO1_LSB _u(1) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO0 -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO0_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO0_BITS _u(0x00000001) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO0_MSB _u(0) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO0_LSB _u(0) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO0_ACCESS "RO" -// ============================================================================= -// Register : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1 -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_OFFSET _u(0x0000020c) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_BITS _u(0x0000ffff) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO47 -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO47_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO47_BITS _u(0x00008000) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO47_MSB _u(15) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO47_LSB _u(15) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO47_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO46 -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO46_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO46_BITS _u(0x00004000) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO46_MSB _u(14) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO46_LSB _u(14) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO46_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO45 -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO45_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO45_BITS _u(0x00002000) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO45_MSB _u(13) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO45_LSB _u(13) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO45_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO44 -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO44_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO44_BITS _u(0x00001000) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO44_MSB _u(12) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO44_LSB _u(12) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO44_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO43 -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO43_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO43_BITS _u(0x00000800) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO43_MSB _u(11) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO43_LSB _u(11) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO43_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO42 -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO42_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO42_BITS _u(0x00000400) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO42_MSB _u(10) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO42_LSB _u(10) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO42_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO41 -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO41_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO41_BITS _u(0x00000200) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO41_MSB _u(9) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO41_LSB _u(9) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO41_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO40 -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO40_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO40_BITS _u(0x00000100) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO40_MSB _u(8) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO40_LSB _u(8) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO40_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO39 -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO39_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO39_BITS _u(0x00000080) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO39_MSB _u(7) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO39_LSB _u(7) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO39_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO38 -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO38_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO38_BITS _u(0x00000040) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO38_MSB _u(6) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO38_LSB _u(6) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO38_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO37 -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO37_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO37_BITS _u(0x00000020) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO37_MSB _u(5) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO37_LSB _u(5) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO37_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO36 -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO36_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO36_BITS _u(0x00000010) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO36_MSB _u(4) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO36_LSB _u(4) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO36_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO35 -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO35_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO35_BITS _u(0x00000008) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO35_MSB _u(3) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO35_LSB _u(3) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO35_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO34 -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO34_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO34_BITS _u(0x00000004) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO34_MSB _u(2) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO34_LSB _u(2) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO34_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO33 -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO33_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO33_BITS _u(0x00000002) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO33_MSB _u(1) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO33_LSB _u(1) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO33_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO32 -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO32_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO32_BITS _u(0x00000001) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO32_MSB _u(0) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO32_LSB _u(0) -#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO32_ACCESS "RO" -// ============================================================================= -// Register : IO_BANK0_IRQSUMMARY_PROC1_SECURE0 -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_OFFSET _u(0x00000210) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_BITS _u(0xffffffff) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO31 -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO31_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO31_BITS _u(0x80000000) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO31_MSB _u(31) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO31_LSB _u(31) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO31_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO30 -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO30_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO30_BITS _u(0x40000000) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO30_MSB _u(30) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO30_LSB _u(30) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO30_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO29 -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO29_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO29_BITS _u(0x20000000) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO29_MSB _u(29) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO29_LSB _u(29) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO29_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO28 -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO28_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO28_BITS _u(0x10000000) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO28_MSB _u(28) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO28_LSB _u(28) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO28_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO27 -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO27_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO27_BITS _u(0x08000000) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO27_MSB _u(27) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO27_LSB _u(27) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO27_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO26 -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO26_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO26_BITS _u(0x04000000) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO26_MSB _u(26) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO26_LSB _u(26) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO26_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO25 -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO25_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO25_BITS _u(0x02000000) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO25_MSB _u(25) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO25_LSB _u(25) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO25_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO24 -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO24_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO24_BITS _u(0x01000000) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO24_MSB _u(24) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO24_LSB _u(24) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO24_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO23 -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO23_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO23_BITS _u(0x00800000) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO23_MSB _u(23) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO23_LSB _u(23) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO23_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO22 -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO22_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO22_BITS _u(0x00400000) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO22_MSB _u(22) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO22_LSB _u(22) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO22_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO21 -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO21_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO21_BITS _u(0x00200000) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO21_MSB _u(21) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO21_LSB _u(21) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO21_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO20 -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO20_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO20_BITS _u(0x00100000) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO20_MSB _u(20) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO20_LSB _u(20) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO20_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO19 -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO19_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO19_BITS _u(0x00080000) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO19_MSB _u(19) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO19_LSB _u(19) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO19_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO18 -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO18_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO18_BITS _u(0x00040000) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO18_MSB _u(18) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO18_LSB _u(18) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO18_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO17 -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO17_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO17_BITS _u(0x00020000) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO17_MSB _u(17) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO17_LSB _u(17) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO17_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO16 -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO16_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO16_BITS _u(0x00010000) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO16_MSB _u(16) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO16_LSB _u(16) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO16_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO15 -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO15_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO15_BITS _u(0x00008000) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO15_MSB _u(15) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO15_LSB _u(15) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO15_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO14 -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO14_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO14_BITS _u(0x00004000) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO14_MSB _u(14) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO14_LSB _u(14) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO14_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO13 -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO13_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO13_BITS _u(0x00002000) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO13_MSB _u(13) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO13_LSB _u(13) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO13_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO12 -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO12_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO12_BITS _u(0x00001000) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO12_MSB _u(12) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO12_LSB _u(12) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO12_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO11 -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO11_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO11_BITS _u(0x00000800) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO11_MSB _u(11) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO11_LSB _u(11) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO11_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO10 -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO10_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO10_BITS _u(0x00000400) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO10_MSB _u(10) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO10_LSB _u(10) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO10_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO9 -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO9_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO9_BITS _u(0x00000200) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO9_MSB _u(9) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO9_LSB _u(9) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO9_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO8 -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO8_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO8_BITS _u(0x00000100) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO8_MSB _u(8) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO8_LSB _u(8) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO8_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO7 -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO7_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO7_BITS _u(0x00000080) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO7_MSB _u(7) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO7_LSB _u(7) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO7_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO6 -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO6_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO6_BITS _u(0x00000040) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO6_MSB _u(6) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO6_LSB _u(6) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO6_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO5 -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO5_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO5_BITS _u(0x00000020) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO5_MSB _u(5) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO5_LSB _u(5) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO5_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO4 -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO4_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO4_BITS _u(0x00000010) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO4_MSB _u(4) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO4_LSB _u(4) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO4_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO3 -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO3_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO3_BITS _u(0x00000008) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO3_MSB _u(3) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO3_LSB _u(3) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO3_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO2 -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO2_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO2_BITS _u(0x00000004) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO2_MSB _u(2) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO2_LSB _u(2) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO1 -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO1_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO1_BITS _u(0x00000002) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO1_MSB _u(1) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO1_LSB _u(1) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO0 -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO0_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO0_BITS _u(0x00000001) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO0_MSB _u(0) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO0_LSB _u(0) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO0_ACCESS "RO" -// ============================================================================= -// Register : IO_BANK0_IRQSUMMARY_PROC1_SECURE1 -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_OFFSET _u(0x00000214) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_BITS _u(0x0000ffff) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO47 -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO47_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO47_BITS _u(0x00008000) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO47_MSB _u(15) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO47_LSB _u(15) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO47_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO46 -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO46_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO46_BITS _u(0x00004000) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO46_MSB _u(14) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO46_LSB _u(14) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO46_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO45 -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO45_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO45_BITS _u(0x00002000) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO45_MSB _u(13) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO45_LSB _u(13) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO45_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO44 -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO44_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO44_BITS _u(0x00001000) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO44_MSB _u(12) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO44_LSB _u(12) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO44_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO43 -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO43_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO43_BITS _u(0x00000800) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO43_MSB _u(11) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO43_LSB _u(11) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO43_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO42 -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO42_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO42_BITS _u(0x00000400) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO42_MSB _u(10) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO42_LSB _u(10) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO42_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO41 -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO41_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO41_BITS _u(0x00000200) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO41_MSB _u(9) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO41_LSB _u(9) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO41_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO40 -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO40_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO40_BITS _u(0x00000100) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO40_MSB _u(8) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO40_LSB _u(8) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO40_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO39 -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO39_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO39_BITS _u(0x00000080) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO39_MSB _u(7) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO39_LSB _u(7) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO39_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO38 -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO38_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO38_BITS _u(0x00000040) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO38_MSB _u(6) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO38_LSB _u(6) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO38_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO37 -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO37_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO37_BITS _u(0x00000020) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO37_MSB _u(5) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO37_LSB _u(5) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO37_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO36 -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO36_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO36_BITS _u(0x00000010) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO36_MSB _u(4) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO36_LSB _u(4) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO36_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO35 -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO35_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO35_BITS _u(0x00000008) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO35_MSB _u(3) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO35_LSB _u(3) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO35_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO34 -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO34_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO34_BITS _u(0x00000004) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO34_MSB _u(2) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO34_LSB _u(2) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO34_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO33 -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO33_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO33_BITS _u(0x00000002) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO33_MSB _u(1) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO33_LSB _u(1) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO33_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO32 -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO32_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO32_BITS _u(0x00000001) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO32_MSB _u(0) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO32_LSB _u(0) -#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO32_ACCESS "RO" -// ============================================================================= -// Register : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0 -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_OFFSET _u(0x00000218) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_BITS _u(0xffffffff) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO31 -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO31_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO31_BITS _u(0x80000000) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO31_MSB _u(31) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO31_LSB _u(31) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO31_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO30 -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO30_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO30_BITS _u(0x40000000) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO30_MSB _u(30) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO30_LSB _u(30) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO30_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO29 -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO29_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO29_BITS _u(0x20000000) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO29_MSB _u(29) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO29_LSB _u(29) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO29_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO28 -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO28_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO28_BITS _u(0x10000000) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO28_MSB _u(28) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO28_LSB _u(28) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO28_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO27 -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO27_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO27_BITS _u(0x08000000) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO27_MSB _u(27) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO27_LSB _u(27) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO27_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO26 -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO26_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO26_BITS _u(0x04000000) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO26_MSB _u(26) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO26_LSB _u(26) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO26_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO25 -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO25_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO25_BITS _u(0x02000000) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO25_MSB _u(25) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO25_LSB _u(25) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO25_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO24 -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO24_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO24_BITS _u(0x01000000) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO24_MSB _u(24) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO24_LSB _u(24) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO24_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO23 -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO23_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO23_BITS _u(0x00800000) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO23_MSB _u(23) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO23_LSB _u(23) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO23_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO22 -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO22_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO22_BITS _u(0x00400000) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO22_MSB _u(22) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO22_LSB _u(22) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO22_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO21 -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO21_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO21_BITS _u(0x00200000) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO21_MSB _u(21) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO21_LSB _u(21) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO21_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO20 -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO20_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO20_BITS _u(0x00100000) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO20_MSB _u(20) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO20_LSB _u(20) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO20_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO19 -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO19_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO19_BITS _u(0x00080000) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO19_MSB _u(19) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO19_LSB _u(19) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO19_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO18 -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO18_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO18_BITS _u(0x00040000) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO18_MSB _u(18) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO18_LSB _u(18) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO18_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO17 -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO17_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO17_BITS _u(0x00020000) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO17_MSB _u(17) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO17_LSB _u(17) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO17_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO16 -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO16_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO16_BITS _u(0x00010000) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO16_MSB _u(16) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO16_LSB _u(16) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO16_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO15 -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO15_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO15_BITS _u(0x00008000) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO15_MSB _u(15) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO15_LSB _u(15) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO15_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO14 -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO14_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO14_BITS _u(0x00004000) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO14_MSB _u(14) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO14_LSB _u(14) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO14_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO13 -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO13_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO13_BITS _u(0x00002000) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO13_MSB _u(13) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO13_LSB _u(13) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO13_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO12 -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO12_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO12_BITS _u(0x00001000) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO12_MSB _u(12) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO12_LSB _u(12) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO12_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO11 -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO11_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO11_BITS _u(0x00000800) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO11_MSB _u(11) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO11_LSB _u(11) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO11_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO10 -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO10_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO10_BITS _u(0x00000400) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO10_MSB _u(10) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO10_LSB _u(10) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO10_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO9 -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO9_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO9_BITS _u(0x00000200) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO9_MSB _u(9) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO9_LSB _u(9) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO9_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO8 -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO8_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO8_BITS _u(0x00000100) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO8_MSB _u(8) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO8_LSB _u(8) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO8_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO7 -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO7_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO7_BITS _u(0x00000080) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO7_MSB _u(7) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO7_LSB _u(7) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO7_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO6 -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO6_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO6_BITS _u(0x00000040) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO6_MSB _u(6) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO6_LSB _u(6) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO6_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO5 -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO5_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO5_BITS _u(0x00000020) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO5_MSB _u(5) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO5_LSB _u(5) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO5_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO4 -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO4_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO4_BITS _u(0x00000010) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO4_MSB _u(4) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO4_LSB _u(4) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO4_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO3 -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO3_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO3_BITS _u(0x00000008) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO3_MSB _u(3) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO3_LSB _u(3) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO3_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO2 -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO2_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO2_BITS _u(0x00000004) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO2_MSB _u(2) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO2_LSB _u(2) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO1 -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO1_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO1_BITS _u(0x00000002) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO1_MSB _u(1) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO1_LSB _u(1) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO0 -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO0_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO0_BITS _u(0x00000001) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO0_MSB _u(0) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO0_LSB _u(0) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO0_ACCESS "RO" -// ============================================================================= -// Register : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1 -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_OFFSET _u(0x0000021c) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_BITS _u(0x0000ffff) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO47 -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO47_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO47_BITS _u(0x00008000) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO47_MSB _u(15) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO47_LSB _u(15) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO47_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO46 -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO46_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO46_BITS _u(0x00004000) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO46_MSB _u(14) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO46_LSB _u(14) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO46_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO45 -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO45_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO45_BITS _u(0x00002000) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO45_MSB _u(13) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO45_LSB _u(13) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO45_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO44 -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO44_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO44_BITS _u(0x00001000) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO44_MSB _u(12) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO44_LSB _u(12) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO44_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO43 -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO43_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO43_BITS _u(0x00000800) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO43_MSB _u(11) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO43_LSB _u(11) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO43_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO42 -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO42_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO42_BITS _u(0x00000400) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO42_MSB _u(10) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO42_LSB _u(10) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO42_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO41 -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO41_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO41_BITS _u(0x00000200) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO41_MSB _u(9) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO41_LSB _u(9) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO41_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO40 -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO40_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO40_BITS _u(0x00000100) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO40_MSB _u(8) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO40_LSB _u(8) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO40_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO39 -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO39_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO39_BITS _u(0x00000080) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO39_MSB _u(7) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO39_LSB _u(7) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO39_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO38 -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO38_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO38_BITS _u(0x00000040) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO38_MSB _u(6) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO38_LSB _u(6) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO38_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO37 -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO37_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO37_BITS _u(0x00000020) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO37_MSB _u(5) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO37_LSB _u(5) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO37_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO36 -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO36_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO36_BITS _u(0x00000010) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO36_MSB _u(4) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO36_LSB _u(4) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO36_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO35 -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO35_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO35_BITS _u(0x00000008) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO35_MSB _u(3) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO35_LSB _u(3) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO35_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO34 -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO34_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO34_BITS _u(0x00000004) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO34_MSB _u(2) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO34_LSB _u(2) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO34_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO33 -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO33_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO33_BITS _u(0x00000002) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO33_MSB _u(1) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO33_LSB _u(1) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO33_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO32 -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO32_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO32_BITS _u(0x00000001) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO32_MSB _u(0) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO32_LSB _u(0) -#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO32_ACCESS "RO" -// ============================================================================= -// Register : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0 -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_OFFSET _u(0x00000220) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_BITS _u(0xffffffff) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO31 -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO31_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO31_BITS _u(0x80000000) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO31_MSB _u(31) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO31_LSB _u(31) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO31_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO30 -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO30_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO30_BITS _u(0x40000000) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO30_MSB _u(30) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO30_LSB _u(30) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO30_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO29 -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO29_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO29_BITS _u(0x20000000) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO29_MSB _u(29) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO29_LSB _u(29) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO29_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO28 -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO28_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO28_BITS _u(0x10000000) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO28_MSB _u(28) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO28_LSB _u(28) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO28_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO27 -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO27_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO27_BITS _u(0x08000000) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO27_MSB _u(27) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO27_LSB _u(27) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO27_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO26 -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO26_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO26_BITS _u(0x04000000) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO26_MSB _u(26) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO26_LSB _u(26) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO26_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO25 -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO25_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO25_BITS _u(0x02000000) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO25_MSB _u(25) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO25_LSB _u(25) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO25_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO24 -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO24_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO24_BITS _u(0x01000000) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO24_MSB _u(24) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO24_LSB _u(24) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO24_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO23 -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO23_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO23_BITS _u(0x00800000) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO23_MSB _u(23) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO23_LSB _u(23) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO23_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO22 -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO22_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO22_BITS _u(0x00400000) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO22_MSB _u(22) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO22_LSB _u(22) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO22_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO21 -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO21_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO21_BITS _u(0x00200000) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO21_MSB _u(21) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO21_LSB _u(21) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO21_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO20 -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO20_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO20_BITS _u(0x00100000) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO20_MSB _u(20) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO20_LSB _u(20) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO20_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO19 -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO19_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO19_BITS _u(0x00080000) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO19_MSB _u(19) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO19_LSB _u(19) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO19_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO18 -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO18_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO18_BITS _u(0x00040000) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO18_MSB _u(18) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO18_LSB _u(18) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO18_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO17 -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO17_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO17_BITS _u(0x00020000) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO17_MSB _u(17) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO17_LSB _u(17) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO17_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO16 -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO16_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO16_BITS _u(0x00010000) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO16_MSB _u(16) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO16_LSB _u(16) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO16_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO15 -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO15_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO15_BITS _u(0x00008000) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO15_MSB _u(15) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO15_LSB _u(15) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO15_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO14 -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO14_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO14_BITS _u(0x00004000) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO14_MSB _u(14) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO14_LSB _u(14) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO14_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO13 -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO13_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO13_BITS _u(0x00002000) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO13_MSB _u(13) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO13_LSB _u(13) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO13_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO12 -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO12_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO12_BITS _u(0x00001000) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO12_MSB _u(12) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO12_LSB _u(12) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO12_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO11 -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO11_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO11_BITS _u(0x00000800) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO11_MSB _u(11) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO11_LSB _u(11) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO11_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO10 -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO10_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO10_BITS _u(0x00000400) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO10_MSB _u(10) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO10_LSB _u(10) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO10_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO9 -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO9_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO9_BITS _u(0x00000200) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO9_MSB _u(9) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO9_LSB _u(9) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO9_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO8 -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO8_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO8_BITS _u(0x00000100) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO8_MSB _u(8) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO8_LSB _u(8) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO8_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO7 -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO7_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO7_BITS _u(0x00000080) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO7_MSB _u(7) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO7_LSB _u(7) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO7_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO6 -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO6_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO6_BITS _u(0x00000040) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO6_MSB _u(6) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO6_LSB _u(6) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO6_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO5 -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO5_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO5_BITS _u(0x00000020) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO5_MSB _u(5) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO5_LSB _u(5) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO5_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO4 -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO4_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO4_BITS _u(0x00000010) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO4_MSB _u(4) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO4_LSB _u(4) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO4_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO3 -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO3_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO3_BITS _u(0x00000008) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO3_MSB _u(3) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO3_LSB _u(3) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO3_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO2 -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO2_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO2_BITS _u(0x00000004) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO2_MSB _u(2) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO2_LSB _u(2) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO1 -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO1_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO1_BITS _u(0x00000002) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO1_MSB _u(1) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO1_LSB _u(1) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO0 -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO0_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO0_BITS _u(0x00000001) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO0_MSB _u(0) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO0_LSB _u(0) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO0_ACCESS "RO" -// ============================================================================= -// Register : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1 -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_OFFSET _u(0x00000224) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_BITS _u(0x0000ffff) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO47 -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO47_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO47_BITS _u(0x00008000) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO47_MSB _u(15) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO47_LSB _u(15) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO47_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO46 -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO46_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO46_BITS _u(0x00004000) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO46_MSB _u(14) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO46_LSB _u(14) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO46_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO45 -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO45_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO45_BITS _u(0x00002000) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO45_MSB _u(13) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO45_LSB _u(13) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO45_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO44 -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO44_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO44_BITS _u(0x00001000) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO44_MSB _u(12) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO44_LSB _u(12) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO44_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO43 -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO43_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO43_BITS _u(0x00000800) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO43_MSB _u(11) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO43_LSB _u(11) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO43_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO42 -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO42_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO42_BITS _u(0x00000400) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO42_MSB _u(10) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO42_LSB _u(10) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO42_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO41 -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO41_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO41_BITS _u(0x00000200) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO41_MSB _u(9) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO41_LSB _u(9) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO41_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO40 -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO40_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO40_BITS _u(0x00000100) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO40_MSB _u(8) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO40_LSB _u(8) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO40_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO39 -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO39_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO39_BITS _u(0x00000080) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO39_MSB _u(7) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO39_LSB _u(7) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO39_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO38 -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO38_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO38_BITS _u(0x00000040) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO38_MSB _u(6) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO38_LSB _u(6) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO38_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO37 -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO37_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO37_BITS _u(0x00000020) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO37_MSB _u(5) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO37_LSB _u(5) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO37_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO36 -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO36_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO36_BITS _u(0x00000010) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO36_MSB _u(4) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO36_LSB _u(4) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO36_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO35 -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO35_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO35_BITS _u(0x00000008) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO35_MSB _u(3) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO35_LSB _u(3) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO35_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO34 -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO34_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO34_BITS _u(0x00000004) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO34_MSB _u(2) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO34_LSB _u(2) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO34_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO33 -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO33_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO33_BITS _u(0x00000002) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO33_MSB _u(1) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO33_LSB _u(1) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO33_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO32 -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO32_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO32_BITS _u(0x00000001) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO32_MSB _u(0) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO32_LSB _u(0) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO32_ACCESS "RO" -// ============================================================================= -// Register : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0 -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_OFFSET _u(0x00000228) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_BITS _u(0xffffffff) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO31 -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO31_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO31_BITS _u(0x80000000) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO31_MSB _u(31) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO31_LSB _u(31) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO31_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO30 -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO30_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO30_BITS _u(0x40000000) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO30_MSB _u(30) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO30_LSB _u(30) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO30_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO29 -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO29_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO29_BITS _u(0x20000000) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO29_MSB _u(29) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO29_LSB _u(29) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO29_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO28 -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO28_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO28_BITS _u(0x10000000) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO28_MSB _u(28) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO28_LSB _u(28) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO28_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO27 -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO27_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO27_BITS _u(0x08000000) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO27_MSB _u(27) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO27_LSB _u(27) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO27_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO26 -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO26_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO26_BITS _u(0x04000000) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO26_MSB _u(26) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO26_LSB _u(26) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO26_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO25 -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO25_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO25_BITS _u(0x02000000) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO25_MSB _u(25) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO25_LSB _u(25) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO25_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO24 -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO24_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO24_BITS _u(0x01000000) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO24_MSB _u(24) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO24_LSB _u(24) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO24_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO23 -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO23_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO23_BITS _u(0x00800000) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO23_MSB _u(23) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO23_LSB _u(23) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO23_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO22 -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO22_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO22_BITS _u(0x00400000) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO22_MSB _u(22) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO22_LSB _u(22) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO22_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO21 -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO21_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO21_BITS _u(0x00200000) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO21_MSB _u(21) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO21_LSB _u(21) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO21_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO20 -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO20_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO20_BITS _u(0x00100000) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO20_MSB _u(20) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO20_LSB _u(20) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO20_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO19 -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO19_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO19_BITS _u(0x00080000) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO19_MSB _u(19) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO19_LSB _u(19) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO19_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO18 -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO18_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO18_BITS _u(0x00040000) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO18_MSB _u(18) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO18_LSB _u(18) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO18_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO17 -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO17_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO17_BITS _u(0x00020000) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO17_MSB _u(17) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO17_LSB _u(17) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO17_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO16 -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO16_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO16_BITS _u(0x00010000) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO16_MSB _u(16) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO16_LSB _u(16) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO16_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO15 -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO15_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO15_BITS _u(0x00008000) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO15_MSB _u(15) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO15_LSB _u(15) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO15_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO14 -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO14_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO14_BITS _u(0x00004000) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO14_MSB _u(14) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO14_LSB _u(14) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO14_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO13 -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO13_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO13_BITS _u(0x00002000) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO13_MSB _u(13) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO13_LSB _u(13) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO13_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO12 -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO12_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO12_BITS _u(0x00001000) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO12_MSB _u(12) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO12_LSB _u(12) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO12_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO11 -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO11_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO11_BITS _u(0x00000800) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO11_MSB _u(11) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO11_LSB _u(11) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO11_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO10 -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO10_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO10_BITS _u(0x00000400) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO10_MSB _u(10) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO10_LSB _u(10) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO10_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO9 -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO9_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO9_BITS _u(0x00000200) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO9_MSB _u(9) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO9_LSB _u(9) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO9_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO8 -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO8_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO8_BITS _u(0x00000100) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO8_MSB _u(8) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO8_LSB _u(8) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO8_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO7 -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO7_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO7_BITS _u(0x00000080) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO7_MSB _u(7) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO7_LSB _u(7) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO7_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO6 -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO6_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO6_BITS _u(0x00000040) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO6_MSB _u(6) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO6_LSB _u(6) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO6_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO5 -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO5_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO5_BITS _u(0x00000020) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO5_MSB _u(5) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO5_LSB _u(5) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO5_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO4 -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO4_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO4_BITS _u(0x00000010) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO4_MSB _u(4) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO4_LSB _u(4) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO4_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO3 -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO3_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO3_BITS _u(0x00000008) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO3_MSB _u(3) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO3_LSB _u(3) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO3_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO2 -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO2_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO2_BITS _u(0x00000004) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO2_MSB _u(2) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO2_LSB _u(2) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO1 -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO1_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO1_BITS _u(0x00000002) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO1_MSB _u(1) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO1_LSB _u(1) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO0 -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO0_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO0_BITS _u(0x00000001) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO0_MSB _u(0) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO0_LSB _u(0) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO0_ACCESS "RO" -// ============================================================================= -// Register : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1 -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_OFFSET _u(0x0000022c) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_BITS _u(0x0000ffff) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO47 -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO47_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO47_BITS _u(0x00008000) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO47_MSB _u(15) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO47_LSB _u(15) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO47_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO46 -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO46_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO46_BITS _u(0x00004000) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO46_MSB _u(14) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO46_LSB _u(14) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO46_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO45 -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO45_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO45_BITS _u(0x00002000) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO45_MSB _u(13) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO45_LSB _u(13) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO45_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO44 -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO44_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO44_BITS _u(0x00001000) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO44_MSB _u(12) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO44_LSB _u(12) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO44_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO43 -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO43_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO43_BITS _u(0x00000800) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO43_MSB _u(11) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO43_LSB _u(11) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO43_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO42 -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO42_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO42_BITS _u(0x00000400) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO42_MSB _u(10) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO42_LSB _u(10) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO42_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO41 -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO41_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO41_BITS _u(0x00000200) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO41_MSB _u(9) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO41_LSB _u(9) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO41_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO40 -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO40_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO40_BITS _u(0x00000100) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO40_MSB _u(8) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO40_LSB _u(8) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO40_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO39 -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO39_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO39_BITS _u(0x00000080) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO39_MSB _u(7) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO39_LSB _u(7) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO39_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO38 -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO38_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO38_BITS _u(0x00000040) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO38_MSB _u(6) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO38_LSB _u(6) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO38_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO37 -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO37_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO37_BITS _u(0x00000020) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO37_MSB _u(5) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO37_LSB _u(5) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO37_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO36 -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO36_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO36_BITS _u(0x00000010) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO36_MSB _u(4) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO36_LSB _u(4) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO36_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO35 -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO35_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO35_BITS _u(0x00000008) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO35_MSB _u(3) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO35_LSB _u(3) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO35_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO34 -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO34_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO34_BITS _u(0x00000004) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO34_MSB _u(2) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO34_LSB _u(2) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO34_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO33 -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO33_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO33_BITS _u(0x00000002) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO33_MSB _u(1) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO33_LSB _u(1) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO33_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO32 -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO32_RESET _u(0x0) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO32_BITS _u(0x00000001) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO32_MSB _u(0) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO32_LSB _u(0) -#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO32_ACCESS "RO" -// ============================================================================= -// Register : IO_BANK0_INTR0 -// Description : Raw Interrupts -#define IO_BANK0_INTR0_OFFSET _u(0x00000230) -#define IO_BANK0_INTR0_BITS _u(0xffffffff) -#define IO_BANK0_INTR0_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR0_GPIO7_EDGE_HIGH -#define IO_BANK0_INTR0_GPIO7_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR0_GPIO7_EDGE_HIGH_BITS _u(0x80000000) -#define IO_BANK0_INTR0_GPIO7_EDGE_HIGH_MSB _u(31) -#define IO_BANK0_INTR0_GPIO7_EDGE_HIGH_LSB _u(31) -#define IO_BANK0_INTR0_GPIO7_EDGE_HIGH_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR0_GPIO7_EDGE_LOW -#define IO_BANK0_INTR0_GPIO7_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_INTR0_GPIO7_EDGE_LOW_BITS _u(0x40000000) -#define IO_BANK0_INTR0_GPIO7_EDGE_LOW_MSB _u(30) -#define IO_BANK0_INTR0_GPIO7_EDGE_LOW_LSB _u(30) -#define IO_BANK0_INTR0_GPIO7_EDGE_LOW_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR0_GPIO7_LEVEL_HIGH -#define IO_BANK0_INTR0_GPIO7_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR0_GPIO7_LEVEL_HIGH_BITS _u(0x20000000) -#define IO_BANK0_INTR0_GPIO7_LEVEL_HIGH_MSB _u(29) -#define IO_BANK0_INTR0_GPIO7_LEVEL_HIGH_LSB _u(29) -#define IO_BANK0_INTR0_GPIO7_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR0_GPIO7_LEVEL_LOW -#define IO_BANK0_INTR0_GPIO7_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_INTR0_GPIO7_LEVEL_LOW_BITS _u(0x10000000) -#define IO_BANK0_INTR0_GPIO7_LEVEL_LOW_MSB _u(28) -#define IO_BANK0_INTR0_GPIO7_LEVEL_LOW_LSB _u(28) -#define IO_BANK0_INTR0_GPIO7_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR0_GPIO6_EDGE_HIGH -#define IO_BANK0_INTR0_GPIO6_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR0_GPIO6_EDGE_HIGH_BITS _u(0x08000000) -#define IO_BANK0_INTR0_GPIO6_EDGE_HIGH_MSB _u(27) -#define IO_BANK0_INTR0_GPIO6_EDGE_HIGH_LSB _u(27) -#define IO_BANK0_INTR0_GPIO6_EDGE_HIGH_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR0_GPIO6_EDGE_LOW -#define IO_BANK0_INTR0_GPIO6_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_INTR0_GPIO6_EDGE_LOW_BITS _u(0x04000000) -#define IO_BANK0_INTR0_GPIO6_EDGE_LOW_MSB _u(26) -#define IO_BANK0_INTR0_GPIO6_EDGE_LOW_LSB _u(26) -#define IO_BANK0_INTR0_GPIO6_EDGE_LOW_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR0_GPIO6_LEVEL_HIGH -#define IO_BANK0_INTR0_GPIO6_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR0_GPIO6_LEVEL_HIGH_BITS _u(0x02000000) -#define IO_BANK0_INTR0_GPIO6_LEVEL_HIGH_MSB _u(25) -#define IO_BANK0_INTR0_GPIO6_LEVEL_HIGH_LSB _u(25) -#define IO_BANK0_INTR0_GPIO6_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR0_GPIO6_LEVEL_LOW -#define IO_BANK0_INTR0_GPIO6_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_INTR0_GPIO6_LEVEL_LOW_BITS _u(0x01000000) -#define IO_BANK0_INTR0_GPIO6_LEVEL_LOW_MSB _u(24) -#define IO_BANK0_INTR0_GPIO6_LEVEL_LOW_LSB _u(24) -#define IO_BANK0_INTR0_GPIO6_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR0_GPIO5_EDGE_HIGH -#define IO_BANK0_INTR0_GPIO5_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR0_GPIO5_EDGE_HIGH_BITS _u(0x00800000) -#define IO_BANK0_INTR0_GPIO5_EDGE_HIGH_MSB _u(23) -#define IO_BANK0_INTR0_GPIO5_EDGE_HIGH_LSB _u(23) -#define IO_BANK0_INTR0_GPIO5_EDGE_HIGH_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR0_GPIO5_EDGE_LOW -#define IO_BANK0_INTR0_GPIO5_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_INTR0_GPIO5_EDGE_LOW_BITS _u(0x00400000) -#define IO_BANK0_INTR0_GPIO5_EDGE_LOW_MSB _u(22) -#define IO_BANK0_INTR0_GPIO5_EDGE_LOW_LSB _u(22) -#define IO_BANK0_INTR0_GPIO5_EDGE_LOW_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR0_GPIO5_LEVEL_HIGH -#define IO_BANK0_INTR0_GPIO5_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR0_GPIO5_LEVEL_HIGH_BITS _u(0x00200000) -#define IO_BANK0_INTR0_GPIO5_LEVEL_HIGH_MSB _u(21) -#define IO_BANK0_INTR0_GPIO5_LEVEL_HIGH_LSB _u(21) -#define IO_BANK0_INTR0_GPIO5_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR0_GPIO5_LEVEL_LOW -#define IO_BANK0_INTR0_GPIO5_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_INTR0_GPIO5_LEVEL_LOW_BITS _u(0x00100000) -#define IO_BANK0_INTR0_GPIO5_LEVEL_LOW_MSB _u(20) -#define IO_BANK0_INTR0_GPIO5_LEVEL_LOW_LSB _u(20) -#define IO_BANK0_INTR0_GPIO5_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR0_GPIO4_EDGE_HIGH -#define IO_BANK0_INTR0_GPIO4_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR0_GPIO4_EDGE_HIGH_BITS _u(0x00080000) -#define IO_BANK0_INTR0_GPIO4_EDGE_HIGH_MSB _u(19) -#define IO_BANK0_INTR0_GPIO4_EDGE_HIGH_LSB _u(19) -#define IO_BANK0_INTR0_GPIO4_EDGE_HIGH_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR0_GPIO4_EDGE_LOW -#define IO_BANK0_INTR0_GPIO4_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_INTR0_GPIO4_EDGE_LOW_BITS _u(0x00040000) -#define IO_BANK0_INTR0_GPIO4_EDGE_LOW_MSB _u(18) -#define IO_BANK0_INTR0_GPIO4_EDGE_LOW_LSB _u(18) -#define IO_BANK0_INTR0_GPIO4_EDGE_LOW_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR0_GPIO4_LEVEL_HIGH -#define IO_BANK0_INTR0_GPIO4_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR0_GPIO4_LEVEL_HIGH_BITS _u(0x00020000) -#define IO_BANK0_INTR0_GPIO4_LEVEL_HIGH_MSB _u(17) -#define IO_BANK0_INTR0_GPIO4_LEVEL_HIGH_LSB _u(17) -#define IO_BANK0_INTR0_GPIO4_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR0_GPIO4_LEVEL_LOW -#define IO_BANK0_INTR0_GPIO4_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_INTR0_GPIO4_LEVEL_LOW_BITS _u(0x00010000) -#define IO_BANK0_INTR0_GPIO4_LEVEL_LOW_MSB _u(16) -#define IO_BANK0_INTR0_GPIO4_LEVEL_LOW_LSB _u(16) -#define IO_BANK0_INTR0_GPIO4_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR0_GPIO3_EDGE_HIGH -#define IO_BANK0_INTR0_GPIO3_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR0_GPIO3_EDGE_HIGH_BITS _u(0x00008000) -#define IO_BANK0_INTR0_GPIO3_EDGE_HIGH_MSB _u(15) -#define IO_BANK0_INTR0_GPIO3_EDGE_HIGH_LSB _u(15) -#define IO_BANK0_INTR0_GPIO3_EDGE_HIGH_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR0_GPIO3_EDGE_LOW -#define IO_BANK0_INTR0_GPIO3_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_INTR0_GPIO3_EDGE_LOW_BITS _u(0x00004000) -#define IO_BANK0_INTR0_GPIO3_EDGE_LOW_MSB _u(14) -#define IO_BANK0_INTR0_GPIO3_EDGE_LOW_LSB _u(14) -#define IO_BANK0_INTR0_GPIO3_EDGE_LOW_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR0_GPIO3_LEVEL_HIGH -#define IO_BANK0_INTR0_GPIO3_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR0_GPIO3_LEVEL_HIGH_BITS _u(0x00002000) -#define IO_BANK0_INTR0_GPIO3_LEVEL_HIGH_MSB _u(13) -#define IO_BANK0_INTR0_GPIO3_LEVEL_HIGH_LSB _u(13) -#define IO_BANK0_INTR0_GPIO3_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR0_GPIO3_LEVEL_LOW -#define IO_BANK0_INTR0_GPIO3_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_INTR0_GPIO3_LEVEL_LOW_BITS _u(0x00001000) -#define IO_BANK0_INTR0_GPIO3_LEVEL_LOW_MSB _u(12) -#define IO_BANK0_INTR0_GPIO3_LEVEL_LOW_LSB _u(12) -#define IO_BANK0_INTR0_GPIO3_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR0_GPIO2_EDGE_HIGH -#define IO_BANK0_INTR0_GPIO2_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR0_GPIO2_EDGE_HIGH_BITS _u(0x00000800) -#define IO_BANK0_INTR0_GPIO2_EDGE_HIGH_MSB _u(11) -#define IO_BANK0_INTR0_GPIO2_EDGE_HIGH_LSB _u(11) -#define IO_BANK0_INTR0_GPIO2_EDGE_HIGH_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR0_GPIO2_EDGE_LOW -#define IO_BANK0_INTR0_GPIO2_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_INTR0_GPIO2_EDGE_LOW_BITS _u(0x00000400) -#define IO_BANK0_INTR0_GPIO2_EDGE_LOW_MSB _u(10) -#define IO_BANK0_INTR0_GPIO2_EDGE_LOW_LSB _u(10) -#define IO_BANK0_INTR0_GPIO2_EDGE_LOW_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR0_GPIO2_LEVEL_HIGH -#define IO_BANK0_INTR0_GPIO2_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR0_GPIO2_LEVEL_HIGH_BITS _u(0x00000200) -#define IO_BANK0_INTR0_GPIO2_LEVEL_HIGH_MSB _u(9) -#define IO_BANK0_INTR0_GPIO2_LEVEL_HIGH_LSB _u(9) -#define IO_BANK0_INTR0_GPIO2_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR0_GPIO2_LEVEL_LOW -#define IO_BANK0_INTR0_GPIO2_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_INTR0_GPIO2_LEVEL_LOW_BITS _u(0x00000100) -#define IO_BANK0_INTR0_GPIO2_LEVEL_LOW_MSB _u(8) -#define IO_BANK0_INTR0_GPIO2_LEVEL_LOW_LSB _u(8) -#define IO_BANK0_INTR0_GPIO2_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR0_GPIO1_EDGE_HIGH -#define IO_BANK0_INTR0_GPIO1_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR0_GPIO1_EDGE_HIGH_BITS _u(0x00000080) -#define IO_BANK0_INTR0_GPIO1_EDGE_HIGH_MSB _u(7) -#define IO_BANK0_INTR0_GPIO1_EDGE_HIGH_LSB _u(7) -#define IO_BANK0_INTR0_GPIO1_EDGE_HIGH_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR0_GPIO1_EDGE_LOW -#define IO_BANK0_INTR0_GPIO1_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_INTR0_GPIO1_EDGE_LOW_BITS _u(0x00000040) -#define IO_BANK0_INTR0_GPIO1_EDGE_LOW_MSB _u(6) -#define IO_BANK0_INTR0_GPIO1_EDGE_LOW_LSB _u(6) -#define IO_BANK0_INTR0_GPIO1_EDGE_LOW_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR0_GPIO1_LEVEL_HIGH -#define IO_BANK0_INTR0_GPIO1_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR0_GPIO1_LEVEL_HIGH_BITS _u(0x00000020) -#define IO_BANK0_INTR0_GPIO1_LEVEL_HIGH_MSB _u(5) -#define IO_BANK0_INTR0_GPIO1_LEVEL_HIGH_LSB _u(5) -#define IO_BANK0_INTR0_GPIO1_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR0_GPIO1_LEVEL_LOW -#define IO_BANK0_INTR0_GPIO1_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_INTR0_GPIO1_LEVEL_LOW_BITS _u(0x00000010) -#define IO_BANK0_INTR0_GPIO1_LEVEL_LOW_MSB _u(4) -#define IO_BANK0_INTR0_GPIO1_LEVEL_LOW_LSB _u(4) -#define IO_BANK0_INTR0_GPIO1_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR0_GPIO0_EDGE_HIGH -#define IO_BANK0_INTR0_GPIO0_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR0_GPIO0_EDGE_HIGH_BITS _u(0x00000008) -#define IO_BANK0_INTR0_GPIO0_EDGE_HIGH_MSB _u(3) -#define IO_BANK0_INTR0_GPIO0_EDGE_HIGH_LSB _u(3) -#define IO_BANK0_INTR0_GPIO0_EDGE_HIGH_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR0_GPIO0_EDGE_LOW -#define IO_BANK0_INTR0_GPIO0_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_INTR0_GPIO0_EDGE_LOW_BITS _u(0x00000004) -#define IO_BANK0_INTR0_GPIO0_EDGE_LOW_MSB _u(2) -#define IO_BANK0_INTR0_GPIO0_EDGE_LOW_LSB _u(2) -#define IO_BANK0_INTR0_GPIO0_EDGE_LOW_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR0_GPIO0_LEVEL_HIGH -#define IO_BANK0_INTR0_GPIO0_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR0_GPIO0_LEVEL_HIGH_BITS _u(0x00000002) -#define IO_BANK0_INTR0_GPIO0_LEVEL_HIGH_MSB _u(1) -#define IO_BANK0_INTR0_GPIO0_LEVEL_HIGH_LSB _u(1) -#define IO_BANK0_INTR0_GPIO0_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR0_GPIO0_LEVEL_LOW -#define IO_BANK0_INTR0_GPIO0_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_INTR0_GPIO0_LEVEL_LOW_BITS _u(0x00000001) -#define IO_BANK0_INTR0_GPIO0_LEVEL_LOW_MSB _u(0) -#define IO_BANK0_INTR0_GPIO0_LEVEL_LOW_LSB _u(0) -#define IO_BANK0_INTR0_GPIO0_LEVEL_LOW_ACCESS "RO" -// ============================================================================= -// Register : IO_BANK0_INTR1 -// Description : Raw Interrupts -#define IO_BANK0_INTR1_OFFSET _u(0x00000234) -#define IO_BANK0_INTR1_BITS _u(0xffffffff) -#define IO_BANK0_INTR1_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR1_GPIO15_EDGE_HIGH -#define IO_BANK0_INTR1_GPIO15_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR1_GPIO15_EDGE_HIGH_BITS _u(0x80000000) -#define IO_BANK0_INTR1_GPIO15_EDGE_HIGH_MSB _u(31) -#define IO_BANK0_INTR1_GPIO15_EDGE_HIGH_LSB _u(31) -#define IO_BANK0_INTR1_GPIO15_EDGE_HIGH_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR1_GPIO15_EDGE_LOW -#define IO_BANK0_INTR1_GPIO15_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_INTR1_GPIO15_EDGE_LOW_BITS _u(0x40000000) -#define IO_BANK0_INTR1_GPIO15_EDGE_LOW_MSB _u(30) -#define IO_BANK0_INTR1_GPIO15_EDGE_LOW_LSB _u(30) -#define IO_BANK0_INTR1_GPIO15_EDGE_LOW_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR1_GPIO15_LEVEL_HIGH -#define IO_BANK0_INTR1_GPIO15_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR1_GPIO15_LEVEL_HIGH_BITS _u(0x20000000) -#define IO_BANK0_INTR1_GPIO15_LEVEL_HIGH_MSB _u(29) -#define IO_BANK0_INTR1_GPIO15_LEVEL_HIGH_LSB _u(29) -#define IO_BANK0_INTR1_GPIO15_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR1_GPIO15_LEVEL_LOW -#define IO_BANK0_INTR1_GPIO15_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_INTR1_GPIO15_LEVEL_LOW_BITS _u(0x10000000) -#define IO_BANK0_INTR1_GPIO15_LEVEL_LOW_MSB _u(28) -#define IO_BANK0_INTR1_GPIO15_LEVEL_LOW_LSB _u(28) -#define IO_BANK0_INTR1_GPIO15_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR1_GPIO14_EDGE_HIGH -#define IO_BANK0_INTR1_GPIO14_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR1_GPIO14_EDGE_HIGH_BITS _u(0x08000000) -#define IO_BANK0_INTR1_GPIO14_EDGE_HIGH_MSB _u(27) -#define IO_BANK0_INTR1_GPIO14_EDGE_HIGH_LSB _u(27) -#define IO_BANK0_INTR1_GPIO14_EDGE_HIGH_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR1_GPIO14_EDGE_LOW -#define IO_BANK0_INTR1_GPIO14_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_INTR1_GPIO14_EDGE_LOW_BITS _u(0x04000000) -#define IO_BANK0_INTR1_GPIO14_EDGE_LOW_MSB _u(26) -#define IO_BANK0_INTR1_GPIO14_EDGE_LOW_LSB _u(26) -#define IO_BANK0_INTR1_GPIO14_EDGE_LOW_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR1_GPIO14_LEVEL_HIGH -#define IO_BANK0_INTR1_GPIO14_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR1_GPIO14_LEVEL_HIGH_BITS _u(0x02000000) -#define IO_BANK0_INTR1_GPIO14_LEVEL_HIGH_MSB _u(25) -#define IO_BANK0_INTR1_GPIO14_LEVEL_HIGH_LSB _u(25) -#define IO_BANK0_INTR1_GPIO14_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR1_GPIO14_LEVEL_LOW -#define IO_BANK0_INTR1_GPIO14_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_INTR1_GPIO14_LEVEL_LOW_BITS _u(0x01000000) -#define IO_BANK0_INTR1_GPIO14_LEVEL_LOW_MSB _u(24) -#define IO_BANK0_INTR1_GPIO14_LEVEL_LOW_LSB _u(24) -#define IO_BANK0_INTR1_GPIO14_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR1_GPIO13_EDGE_HIGH -#define IO_BANK0_INTR1_GPIO13_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR1_GPIO13_EDGE_HIGH_BITS _u(0x00800000) -#define IO_BANK0_INTR1_GPIO13_EDGE_HIGH_MSB _u(23) -#define IO_BANK0_INTR1_GPIO13_EDGE_HIGH_LSB _u(23) -#define IO_BANK0_INTR1_GPIO13_EDGE_HIGH_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR1_GPIO13_EDGE_LOW -#define IO_BANK0_INTR1_GPIO13_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_INTR1_GPIO13_EDGE_LOW_BITS _u(0x00400000) -#define IO_BANK0_INTR1_GPIO13_EDGE_LOW_MSB _u(22) -#define IO_BANK0_INTR1_GPIO13_EDGE_LOW_LSB _u(22) -#define IO_BANK0_INTR1_GPIO13_EDGE_LOW_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR1_GPIO13_LEVEL_HIGH -#define IO_BANK0_INTR1_GPIO13_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR1_GPIO13_LEVEL_HIGH_BITS _u(0x00200000) -#define IO_BANK0_INTR1_GPIO13_LEVEL_HIGH_MSB _u(21) -#define IO_BANK0_INTR1_GPIO13_LEVEL_HIGH_LSB _u(21) -#define IO_BANK0_INTR1_GPIO13_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR1_GPIO13_LEVEL_LOW -#define IO_BANK0_INTR1_GPIO13_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_INTR1_GPIO13_LEVEL_LOW_BITS _u(0x00100000) -#define IO_BANK0_INTR1_GPIO13_LEVEL_LOW_MSB _u(20) -#define IO_BANK0_INTR1_GPIO13_LEVEL_LOW_LSB _u(20) -#define IO_BANK0_INTR1_GPIO13_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR1_GPIO12_EDGE_HIGH -#define IO_BANK0_INTR1_GPIO12_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR1_GPIO12_EDGE_HIGH_BITS _u(0x00080000) -#define IO_BANK0_INTR1_GPIO12_EDGE_HIGH_MSB _u(19) -#define IO_BANK0_INTR1_GPIO12_EDGE_HIGH_LSB _u(19) -#define IO_BANK0_INTR1_GPIO12_EDGE_HIGH_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR1_GPIO12_EDGE_LOW -#define IO_BANK0_INTR1_GPIO12_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_INTR1_GPIO12_EDGE_LOW_BITS _u(0x00040000) -#define IO_BANK0_INTR1_GPIO12_EDGE_LOW_MSB _u(18) -#define IO_BANK0_INTR1_GPIO12_EDGE_LOW_LSB _u(18) -#define IO_BANK0_INTR1_GPIO12_EDGE_LOW_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR1_GPIO12_LEVEL_HIGH -#define IO_BANK0_INTR1_GPIO12_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR1_GPIO12_LEVEL_HIGH_BITS _u(0x00020000) -#define IO_BANK0_INTR1_GPIO12_LEVEL_HIGH_MSB _u(17) -#define IO_BANK0_INTR1_GPIO12_LEVEL_HIGH_LSB _u(17) -#define IO_BANK0_INTR1_GPIO12_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR1_GPIO12_LEVEL_LOW -#define IO_BANK0_INTR1_GPIO12_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_INTR1_GPIO12_LEVEL_LOW_BITS _u(0x00010000) -#define IO_BANK0_INTR1_GPIO12_LEVEL_LOW_MSB _u(16) -#define IO_BANK0_INTR1_GPIO12_LEVEL_LOW_LSB _u(16) -#define IO_BANK0_INTR1_GPIO12_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR1_GPIO11_EDGE_HIGH -#define IO_BANK0_INTR1_GPIO11_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR1_GPIO11_EDGE_HIGH_BITS _u(0x00008000) -#define IO_BANK0_INTR1_GPIO11_EDGE_HIGH_MSB _u(15) -#define IO_BANK0_INTR1_GPIO11_EDGE_HIGH_LSB _u(15) -#define IO_BANK0_INTR1_GPIO11_EDGE_HIGH_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR1_GPIO11_EDGE_LOW -#define IO_BANK0_INTR1_GPIO11_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_INTR1_GPIO11_EDGE_LOW_BITS _u(0x00004000) -#define IO_BANK0_INTR1_GPIO11_EDGE_LOW_MSB _u(14) -#define IO_BANK0_INTR1_GPIO11_EDGE_LOW_LSB _u(14) -#define IO_BANK0_INTR1_GPIO11_EDGE_LOW_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR1_GPIO11_LEVEL_HIGH -#define IO_BANK0_INTR1_GPIO11_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR1_GPIO11_LEVEL_HIGH_BITS _u(0x00002000) -#define IO_BANK0_INTR1_GPIO11_LEVEL_HIGH_MSB _u(13) -#define IO_BANK0_INTR1_GPIO11_LEVEL_HIGH_LSB _u(13) -#define IO_BANK0_INTR1_GPIO11_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR1_GPIO11_LEVEL_LOW -#define IO_BANK0_INTR1_GPIO11_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_INTR1_GPIO11_LEVEL_LOW_BITS _u(0x00001000) -#define IO_BANK0_INTR1_GPIO11_LEVEL_LOW_MSB _u(12) -#define IO_BANK0_INTR1_GPIO11_LEVEL_LOW_LSB _u(12) -#define IO_BANK0_INTR1_GPIO11_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR1_GPIO10_EDGE_HIGH -#define IO_BANK0_INTR1_GPIO10_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR1_GPIO10_EDGE_HIGH_BITS _u(0x00000800) -#define IO_BANK0_INTR1_GPIO10_EDGE_HIGH_MSB _u(11) -#define IO_BANK0_INTR1_GPIO10_EDGE_HIGH_LSB _u(11) -#define IO_BANK0_INTR1_GPIO10_EDGE_HIGH_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR1_GPIO10_EDGE_LOW -#define IO_BANK0_INTR1_GPIO10_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_INTR1_GPIO10_EDGE_LOW_BITS _u(0x00000400) -#define IO_BANK0_INTR1_GPIO10_EDGE_LOW_MSB _u(10) -#define IO_BANK0_INTR1_GPIO10_EDGE_LOW_LSB _u(10) -#define IO_BANK0_INTR1_GPIO10_EDGE_LOW_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR1_GPIO10_LEVEL_HIGH -#define IO_BANK0_INTR1_GPIO10_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR1_GPIO10_LEVEL_HIGH_BITS _u(0x00000200) -#define IO_BANK0_INTR1_GPIO10_LEVEL_HIGH_MSB _u(9) -#define IO_BANK0_INTR1_GPIO10_LEVEL_HIGH_LSB _u(9) -#define IO_BANK0_INTR1_GPIO10_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR1_GPIO10_LEVEL_LOW -#define IO_BANK0_INTR1_GPIO10_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_INTR1_GPIO10_LEVEL_LOW_BITS _u(0x00000100) -#define IO_BANK0_INTR1_GPIO10_LEVEL_LOW_MSB _u(8) -#define IO_BANK0_INTR1_GPIO10_LEVEL_LOW_LSB _u(8) -#define IO_BANK0_INTR1_GPIO10_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR1_GPIO9_EDGE_HIGH -#define IO_BANK0_INTR1_GPIO9_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR1_GPIO9_EDGE_HIGH_BITS _u(0x00000080) -#define IO_BANK0_INTR1_GPIO9_EDGE_HIGH_MSB _u(7) -#define IO_BANK0_INTR1_GPIO9_EDGE_HIGH_LSB _u(7) -#define IO_BANK0_INTR1_GPIO9_EDGE_HIGH_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR1_GPIO9_EDGE_LOW -#define IO_BANK0_INTR1_GPIO9_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_INTR1_GPIO9_EDGE_LOW_BITS _u(0x00000040) -#define IO_BANK0_INTR1_GPIO9_EDGE_LOW_MSB _u(6) -#define IO_BANK0_INTR1_GPIO9_EDGE_LOW_LSB _u(6) -#define IO_BANK0_INTR1_GPIO9_EDGE_LOW_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR1_GPIO9_LEVEL_HIGH -#define IO_BANK0_INTR1_GPIO9_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR1_GPIO9_LEVEL_HIGH_BITS _u(0x00000020) -#define IO_BANK0_INTR1_GPIO9_LEVEL_HIGH_MSB _u(5) -#define IO_BANK0_INTR1_GPIO9_LEVEL_HIGH_LSB _u(5) -#define IO_BANK0_INTR1_GPIO9_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR1_GPIO9_LEVEL_LOW -#define IO_BANK0_INTR1_GPIO9_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_INTR1_GPIO9_LEVEL_LOW_BITS _u(0x00000010) -#define IO_BANK0_INTR1_GPIO9_LEVEL_LOW_MSB _u(4) -#define IO_BANK0_INTR1_GPIO9_LEVEL_LOW_LSB _u(4) -#define IO_BANK0_INTR1_GPIO9_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR1_GPIO8_EDGE_HIGH -#define IO_BANK0_INTR1_GPIO8_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR1_GPIO8_EDGE_HIGH_BITS _u(0x00000008) -#define IO_BANK0_INTR1_GPIO8_EDGE_HIGH_MSB _u(3) -#define IO_BANK0_INTR1_GPIO8_EDGE_HIGH_LSB _u(3) -#define IO_BANK0_INTR1_GPIO8_EDGE_HIGH_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR1_GPIO8_EDGE_LOW -#define IO_BANK0_INTR1_GPIO8_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_INTR1_GPIO8_EDGE_LOW_BITS _u(0x00000004) -#define IO_BANK0_INTR1_GPIO8_EDGE_LOW_MSB _u(2) -#define IO_BANK0_INTR1_GPIO8_EDGE_LOW_LSB _u(2) -#define IO_BANK0_INTR1_GPIO8_EDGE_LOW_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR1_GPIO8_LEVEL_HIGH -#define IO_BANK0_INTR1_GPIO8_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR1_GPIO8_LEVEL_HIGH_BITS _u(0x00000002) -#define IO_BANK0_INTR1_GPIO8_LEVEL_HIGH_MSB _u(1) -#define IO_BANK0_INTR1_GPIO8_LEVEL_HIGH_LSB _u(1) -#define IO_BANK0_INTR1_GPIO8_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR1_GPIO8_LEVEL_LOW -#define IO_BANK0_INTR1_GPIO8_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_INTR1_GPIO8_LEVEL_LOW_BITS _u(0x00000001) -#define IO_BANK0_INTR1_GPIO8_LEVEL_LOW_MSB _u(0) -#define IO_BANK0_INTR1_GPIO8_LEVEL_LOW_LSB _u(0) -#define IO_BANK0_INTR1_GPIO8_LEVEL_LOW_ACCESS "RO" -// ============================================================================= -// Register : IO_BANK0_INTR2 -// Description : Raw Interrupts -#define IO_BANK0_INTR2_OFFSET _u(0x00000238) -#define IO_BANK0_INTR2_BITS _u(0xffffffff) -#define IO_BANK0_INTR2_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR2_GPIO23_EDGE_HIGH -#define IO_BANK0_INTR2_GPIO23_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR2_GPIO23_EDGE_HIGH_BITS _u(0x80000000) -#define IO_BANK0_INTR2_GPIO23_EDGE_HIGH_MSB _u(31) -#define IO_BANK0_INTR2_GPIO23_EDGE_HIGH_LSB _u(31) -#define IO_BANK0_INTR2_GPIO23_EDGE_HIGH_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR2_GPIO23_EDGE_LOW -#define IO_BANK0_INTR2_GPIO23_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_INTR2_GPIO23_EDGE_LOW_BITS _u(0x40000000) -#define IO_BANK0_INTR2_GPIO23_EDGE_LOW_MSB _u(30) -#define IO_BANK0_INTR2_GPIO23_EDGE_LOW_LSB _u(30) -#define IO_BANK0_INTR2_GPIO23_EDGE_LOW_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR2_GPIO23_LEVEL_HIGH -#define IO_BANK0_INTR2_GPIO23_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR2_GPIO23_LEVEL_HIGH_BITS _u(0x20000000) -#define IO_BANK0_INTR2_GPIO23_LEVEL_HIGH_MSB _u(29) -#define IO_BANK0_INTR2_GPIO23_LEVEL_HIGH_LSB _u(29) -#define IO_BANK0_INTR2_GPIO23_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR2_GPIO23_LEVEL_LOW -#define IO_BANK0_INTR2_GPIO23_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_INTR2_GPIO23_LEVEL_LOW_BITS _u(0x10000000) -#define IO_BANK0_INTR2_GPIO23_LEVEL_LOW_MSB _u(28) -#define IO_BANK0_INTR2_GPIO23_LEVEL_LOW_LSB _u(28) -#define IO_BANK0_INTR2_GPIO23_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR2_GPIO22_EDGE_HIGH -#define IO_BANK0_INTR2_GPIO22_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR2_GPIO22_EDGE_HIGH_BITS _u(0x08000000) -#define IO_BANK0_INTR2_GPIO22_EDGE_HIGH_MSB _u(27) -#define IO_BANK0_INTR2_GPIO22_EDGE_HIGH_LSB _u(27) -#define IO_BANK0_INTR2_GPIO22_EDGE_HIGH_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR2_GPIO22_EDGE_LOW -#define IO_BANK0_INTR2_GPIO22_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_INTR2_GPIO22_EDGE_LOW_BITS _u(0x04000000) -#define IO_BANK0_INTR2_GPIO22_EDGE_LOW_MSB _u(26) -#define IO_BANK0_INTR2_GPIO22_EDGE_LOW_LSB _u(26) -#define IO_BANK0_INTR2_GPIO22_EDGE_LOW_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR2_GPIO22_LEVEL_HIGH -#define IO_BANK0_INTR2_GPIO22_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR2_GPIO22_LEVEL_HIGH_BITS _u(0x02000000) -#define IO_BANK0_INTR2_GPIO22_LEVEL_HIGH_MSB _u(25) -#define IO_BANK0_INTR2_GPIO22_LEVEL_HIGH_LSB _u(25) -#define IO_BANK0_INTR2_GPIO22_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR2_GPIO22_LEVEL_LOW -#define IO_BANK0_INTR2_GPIO22_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_INTR2_GPIO22_LEVEL_LOW_BITS _u(0x01000000) -#define IO_BANK0_INTR2_GPIO22_LEVEL_LOW_MSB _u(24) -#define IO_BANK0_INTR2_GPIO22_LEVEL_LOW_LSB _u(24) -#define IO_BANK0_INTR2_GPIO22_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR2_GPIO21_EDGE_HIGH -#define IO_BANK0_INTR2_GPIO21_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR2_GPIO21_EDGE_HIGH_BITS _u(0x00800000) -#define IO_BANK0_INTR2_GPIO21_EDGE_HIGH_MSB _u(23) -#define IO_BANK0_INTR2_GPIO21_EDGE_HIGH_LSB _u(23) -#define IO_BANK0_INTR2_GPIO21_EDGE_HIGH_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR2_GPIO21_EDGE_LOW -#define IO_BANK0_INTR2_GPIO21_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_INTR2_GPIO21_EDGE_LOW_BITS _u(0x00400000) -#define IO_BANK0_INTR2_GPIO21_EDGE_LOW_MSB _u(22) -#define IO_BANK0_INTR2_GPIO21_EDGE_LOW_LSB _u(22) -#define IO_BANK0_INTR2_GPIO21_EDGE_LOW_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR2_GPIO21_LEVEL_HIGH -#define IO_BANK0_INTR2_GPIO21_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR2_GPIO21_LEVEL_HIGH_BITS _u(0x00200000) -#define IO_BANK0_INTR2_GPIO21_LEVEL_HIGH_MSB _u(21) -#define IO_BANK0_INTR2_GPIO21_LEVEL_HIGH_LSB _u(21) -#define IO_BANK0_INTR2_GPIO21_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR2_GPIO21_LEVEL_LOW -#define IO_BANK0_INTR2_GPIO21_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_INTR2_GPIO21_LEVEL_LOW_BITS _u(0x00100000) -#define IO_BANK0_INTR2_GPIO21_LEVEL_LOW_MSB _u(20) -#define IO_BANK0_INTR2_GPIO21_LEVEL_LOW_LSB _u(20) -#define IO_BANK0_INTR2_GPIO21_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR2_GPIO20_EDGE_HIGH -#define IO_BANK0_INTR2_GPIO20_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR2_GPIO20_EDGE_HIGH_BITS _u(0x00080000) -#define IO_BANK0_INTR2_GPIO20_EDGE_HIGH_MSB _u(19) -#define IO_BANK0_INTR2_GPIO20_EDGE_HIGH_LSB _u(19) -#define IO_BANK0_INTR2_GPIO20_EDGE_HIGH_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR2_GPIO20_EDGE_LOW -#define IO_BANK0_INTR2_GPIO20_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_INTR2_GPIO20_EDGE_LOW_BITS _u(0x00040000) -#define IO_BANK0_INTR2_GPIO20_EDGE_LOW_MSB _u(18) -#define IO_BANK0_INTR2_GPIO20_EDGE_LOW_LSB _u(18) -#define IO_BANK0_INTR2_GPIO20_EDGE_LOW_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR2_GPIO20_LEVEL_HIGH -#define IO_BANK0_INTR2_GPIO20_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR2_GPIO20_LEVEL_HIGH_BITS _u(0x00020000) -#define IO_BANK0_INTR2_GPIO20_LEVEL_HIGH_MSB _u(17) -#define IO_BANK0_INTR2_GPIO20_LEVEL_HIGH_LSB _u(17) -#define IO_BANK0_INTR2_GPIO20_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR2_GPIO20_LEVEL_LOW -#define IO_BANK0_INTR2_GPIO20_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_INTR2_GPIO20_LEVEL_LOW_BITS _u(0x00010000) -#define IO_BANK0_INTR2_GPIO20_LEVEL_LOW_MSB _u(16) -#define IO_BANK0_INTR2_GPIO20_LEVEL_LOW_LSB _u(16) -#define IO_BANK0_INTR2_GPIO20_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR2_GPIO19_EDGE_HIGH -#define IO_BANK0_INTR2_GPIO19_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR2_GPIO19_EDGE_HIGH_BITS _u(0x00008000) -#define IO_BANK0_INTR2_GPIO19_EDGE_HIGH_MSB _u(15) -#define IO_BANK0_INTR2_GPIO19_EDGE_HIGH_LSB _u(15) -#define IO_BANK0_INTR2_GPIO19_EDGE_HIGH_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR2_GPIO19_EDGE_LOW -#define IO_BANK0_INTR2_GPIO19_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_INTR2_GPIO19_EDGE_LOW_BITS _u(0x00004000) -#define IO_BANK0_INTR2_GPIO19_EDGE_LOW_MSB _u(14) -#define IO_BANK0_INTR2_GPIO19_EDGE_LOW_LSB _u(14) -#define IO_BANK0_INTR2_GPIO19_EDGE_LOW_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR2_GPIO19_LEVEL_HIGH -#define IO_BANK0_INTR2_GPIO19_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR2_GPIO19_LEVEL_HIGH_BITS _u(0x00002000) -#define IO_BANK0_INTR2_GPIO19_LEVEL_HIGH_MSB _u(13) -#define IO_BANK0_INTR2_GPIO19_LEVEL_HIGH_LSB _u(13) -#define IO_BANK0_INTR2_GPIO19_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR2_GPIO19_LEVEL_LOW -#define IO_BANK0_INTR2_GPIO19_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_INTR2_GPIO19_LEVEL_LOW_BITS _u(0x00001000) -#define IO_BANK0_INTR2_GPIO19_LEVEL_LOW_MSB _u(12) -#define IO_BANK0_INTR2_GPIO19_LEVEL_LOW_LSB _u(12) -#define IO_BANK0_INTR2_GPIO19_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR2_GPIO18_EDGE_HIGH -#define IO_BANK0_INTR2_GPIO18_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR2_GPIO18_EDGE_HIGH_BITS _u(0x00000800) -#define IO_BANK0_INTR2_GPIO18_EDGE_HIGH_MSB _u(11) -#define IO_BANK0_INTR2_GPIO18_EDGE_HIGH_LSB _u(11) -#define IO_BANK0_INTR2_GPIO18_EDGE_HIGH_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR2_GPIO18_EDGE_LOW -#define IO_BANK0_INTR2_GPIO18_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_INTR2_GPIO18_EDGE_LOW_BITS _u(0x00000400) -#define IO_BANK0_INTR2_GPIO18_EDGE_LOW_MSB _u(10) -#define IO_BANK0_INTR2_GPIO18_EDGE_LOW_LSB _u(10) -#define IO_BANK0_INTR2_GPIO18_EDGE_LOW_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR2_GPIO18_LEVEL_HIGH -#define IO_BANK0_INTR2_GPIO18_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR2_GPIO18_LEVEL_HIGH_BITS _u(0x00000200) -#define IO_BANK0_INTR2_GPIO18_LEVEL_HIGH_MSB _u(9) -#define IO_BANK0_INTR2_GPIO18_LEVEL_HIGH_LSB _u(9) -#define IO_BANK0_INTR2_GPIO18_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR2_GPIO18_LEVEL_LOW -#define IO_BANK0_INTR2_GPIO18_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_INTR2_GPIO18_LEVEL_LOW_BITS _u(0x00000100) -#define IO_BANK0_INTR2_GPIO18_LEVEL_LOW_MSB _u(8) -#define IO_BANK0_INTR2_GPIO18_LEVEL_LOW_LSB _u(8) -#define IO_BANK0_INTR2_GPIO18_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR2_GPIO17_EDGE_HIGH -#define IO_BANK0_INTR2_GPIO17_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR2_GPIO17_EDGE_HIGH_BITS _u(0x00000080) -#define IO_BANK0_INTR2_GPIO17_EDGE_HIGH_MSB _u(7) -#define IO_BANK0_INTR2_GPIO17_EDGE_HIGH_LSB _u(7) -#define IO_BANK0_INTR2_GPIO17_EDGE_HIGH_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR2_GPIO17_EDGE_LOW -#define IO_BANK0_INTR2_GPIO17_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_INTR2_GPIO17_EDGE_LOW_BITS _u(0x00000040) -#define IO_BANK0_INTR2_GPIO17_EDGE_LOW_MSB _u(6) -#define IO_BANK0_INTR2_GPIO17_EDGE_LOW_LSB _u(6) -#define IO_BANK0_INTR2_GPIO17_EDGE_LOW_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR2_GPIO17_LEVEL_HIGH -#define IO_BANK0_INTR2_GPIO17_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR2_GPIO17_LEVEL_HIGH_BITS _u(0x00000020) -#define IO_BANK0_INTR2_GPIO17_LEVEL_HIGH_MSB _u(5) -#define IO_BANK0_INTR2_GPIO17_LEVEL_HIGH_LSB _u(5) -#define IO_BANK0_INTR2_GPIO17_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR2_GPIO17_LEVEL_LOW -#define IO_BANK0_INTR2_GPIO17_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_INTR2_GPIO17_LEVEL_LOW_BITS _u(0x00000010) -#define IO_BANK0_INTR2_GPIO17_LEVEL_LOW_MSB _u(4) -#define IO_BANK0_INTR2_GPIO17_LEVEL_LOW_LSB _u(4) -#define IO_BANK0_INTR2_GPIO17_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR2_GPIO16_EDGE_HIGH -#define IO_BANK0_INTR2_GPIO16_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR2_GPIO16_EDGE_HIGH_BITS _u(0x00000008) -#define IO_BANK0_INTR2_GPIO16_EDGE_HIGH_MSB _u(3) -#define IO_BANK0_INTR2_GPIO16_EDGE_HIGH_LSB _u(3) -#define IO_BANK0_INTR2_GPIO16_EDGE_HIGH_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR2_GPIO16_EDGE_LOW -#define IO_BANK0_INTR2_GPIO16_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_INTR2_GPIO16_EDGE_LOW_BITS _u(0x00000004) -#define IO_BANK0_INTR2_GPIO16_EDGE_LOW_MSB _u(2) -#define IO_BANK0_INTR2_GPIO16_EDGE_LOW_LSB _u(2) -#define IO_BANK0_INTR2_GPIO16_EDGE_LOW_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR2_GPIO16_LEVEL_HIGH -#define IO_BANK0_INTR2_GPIO16_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR2_GPIO16_LEVEL_HIGH_BITS _u(0x00000002) -#define IO_BANK0_INTR2_GPIO16_LEVEL_HIGH_MSB _u(1) -#define IO_BANK0_INTR2_GPIO16_LEVEL_HIGH_LSB _u(1) -#define IO_BANK0_INTR2_GPIO16_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR2_GPIO16_LEVEL_LOW -#define IO_BANK0_INTR2_GPIO16_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_INTR2_GPIO16_LEVEL_LOW_BITS _u(0x00000001) -#define IO_BANK0_INTR2_GPIO16_LEVEL_LOW_MSB _u(0) -#define IO_BANK0_INTR2_GPIO16_LEVEL_LOW_LSB _u(0) -#define IO_BANK0_INTR2_GPIO16_LEVEL_LOW_ACCESS "RO" -// ============================================================================= -// Register : IO_BANK0_INTR3 -// Description : Raw Interrupts -#define IO_BANK0_INTR3_OFFSET _u(0x0000023c) -#define IO_BANK0_INTR3_BITS _u(0xffffffff) -#define IO_BANK0_INTR3_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR3_GPIO31_EDGE_HIGH -#define IO_BANK0_INTR3_GPIO31_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR3_GPIO31_EDGE_HIGH_BITS _u(0x80000000) -#define IO_BANK0_INTR3_GPIO31_EDGE_HIGH_MSB _u(31) -#define IO_BANK0_INTR3_GPIO31_EDGE_HIGH_LSB _u(31) -#define IO_BANK0_INTR3_GPIO31_EDGE_HIGH_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR3_GPIO31_EDGE_LOW -#define IO_BANK0_INTR3_GPIO31_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_INTR3_GPIO31_EDGE_LOW_BITS _u(0x40000000) -#define IO_BANK0_INTR3_GPIO31_EDGE_LOW_MSB _u(30) -#define IO_BANK0_INTR3_GPIO31_EDGE_LOW_LSB _u(30) -#define IO_BANK0_INTR3_GPIO31_EDGE_LOW_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR3_GPIO31_LEVEL_HIGH -#define IO_BANK0_INTR3_GPIO31_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR3_GPIO31_LEVEL_HIGH_BITS _u(0x20000000) -#define IO_BANK0_INTR3_GPIO31_LEVEL_HIGH_MSB _u(29) -#define IO_BANK0_INTR3_GPIO31_LEVEL_HIGH_LSB _u(29) -#define IO_BANK0_INTR3_GPIO31_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR3_GPIO31_LEVEL_LOW -#define IO_BANK0_INTR3_GPIO31_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_INTR3_GPIO31_LEVEL_LOW_BITS _u(0x10000000) -#define IO_BANK0_INTR3_GPIO31_LEVEL_LOW_MSB _u(28) -#define IO_BANK0_INTR3_GPIO31_LEVEL_LOW_LSB _u(28) -#define IO_BANK0_INTR3_GPIO31_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR3_GPIO30_EDGE_HIGH -#define IO_BANK0_INTR3_GPIO30_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR3_GPIO30_EDGE_HIGH_BITS _u(0x08000000) -#define IO_BANK0_INTR3_GPIO30_EDGE_HIGH_MSB _u(27) -#define IO_BANK0_INTR3_GPIO30_EDGE_HIGH_LSB _u(27) -#define IO_BANK0_INTR3_GPIO30_EDGE_HIGH_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR3_GPIO30_EDGE_LOW -#define IO_BANK0_INTR3_GPIO30_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_INTR3_GPIO30_EDGE_LOW_BITS _u(0x04000000) -#define IO_BANK0_INTR3_GPIO30_EDGE_LOW_MSB _u(26) -#define IO_BANK0_INTR3_GPIO30_EDGE_LOW_LSB _u(26) -#define IO_BANK0_INTR3_GPIO30_EDGE_LOW_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR3_GPIO30_LEVEL_HIGH -#define IO_BANK0_INTR3_GPIO30_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR3_GPIO30_LEVEL_HIGH_BITS _u(0x02000000) -#define IO_BANK0_INTR3_GPIO30_LEVEL_HIGH_MSB _u(25) -#define IO_BANK0_INTR3_GPIO30_LEVEL_HIGH_LSB _u(25) -#define IO_BANK0_INTR3_GPIO30_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR3_GPIO30_LEVEL_LOW -#define IO_BANK0_INTR3_GPIO30_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_INTR3_GPIO30_LEVEL_LOW_BITS _u(0x01000000) -#define IO_BANK0_INTR3_GPIO30_LEVEL_LOW_MSB _u(24) -#define IO_BANK0_INTR3_GPIO30_LEVEL_LOW_LSB _u(24) -#define IO_BANK0_INTR3_GPIO30_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR3_GPIO29_EDGE_HIGH -#define IO_BANK0_INTR3_GPIO29_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR3_GPIO29_EDGE_HIGH_BITS _u(0x00800000) -#define IO_BANK0_INTR3_GPIO29_EDGE_HIGH_MSB _u(23) -#define IO_BANK0_INTR3_GPIO29_EDGE_HIGH_LSB _u(23) -#define IO_BANK0_INTR3_GPIO29_EDGE_HIGH_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR3_GPIO29_EDGE_LOW -#define IO_BANK0_INTR3_GPIO29_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_INTR3_GPIO29_EDGE_LOW_BITS _u(0x00400000) -#define IO_BANK0_INTR3_GPIO29_EDGE_LOW_MSB _u(22) -#define IO_BANK0_INTR3_GPIO29_EDGE_LOW_LSB _u(22) -#define IO_BANK0_INTR3_GPIO29_EDGE_LOW_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR3_GPIO29_LEVEL_HIGH -#define IO_BANK0_INTR3_GPIO29_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR3_GPIO29_LEVEL_HIGH_BITS _u(0x00200000) -#define IO_BANK0_INTR3_GPIO29_LEVEL_HIGH_MSB _u(21) -#define IO_BANK0_INTR3_GPIO29_LEVEL_HIGH_LSB _u(21) -#define IO_BANK0_INTR3_GPIO29_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR3_GPIO29_LEVEL_LOW -#define IO_BANK0_INTR3_GPIO29_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_INTR3_GPIO29_LEVEL_LOW_BITS _u(0x00100000) -#define IO_BANK0_INTR3_GPIO29_LEVEL_LOW_MSB _u(20) -#define IO_BANK0_INTR3_GPIO29_LEVEL_LOW_LSB _u(20) -#define IO_BANK0_INTR3_GPIO29_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR3_GPIO28_EDGE_HIGH -#define IO_BANK0_INTR3_GPIO28_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR3_GPIO28_EDGE_HIGH_BITS _u(0x00080000) -#define IO_BANK0_INTR3_GPIO28_EDGE_HIGH_MSB _u(19) -#define IO_BANK0_INTR3_GPIO28_EDGE_HIGH_LSB _u(19) -#define IO_BANK0_INTR3_GPIO28_EDGE_HIGH_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR3_GPIO28_EDGE_LOW -#define IO_BANK0_INTR3_GPIO28_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_INTR3_GPIO28_EDGE_LOW_BITS _u(0x00040000) -#define IO_BANK0_INTR3_GPIO28_EDGE_LOW_MSB _u(18) -#define IO_BANK0_INTR3_GPIO28_EDGE_LOW_LSB _u(18) -#define IO_BANK0_INTR3_GPIO28_EDGE_LOW_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR3_GPIO28_LEVEL_HIGH -#define IO_BANK0_INTR3_GPIO28_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR3_GPIO28_LEVEL_HIGH_BITS _u(0x00020000) -#define IO_BANK0_INTR3_GPIO28_LEVEL_HIGH_MSB _u(17) -#define IO_BANK0_INTR3_GPIO28_LEVEL_HIGH_LSB _u(17) -#define IO_BANK0_INTR3_GPIO28_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR3_GPIO28_LEVEL_LOW -#define IO_BANK0_INTR3_GPIO28_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_INTR3_GPIO28_LEVEL_LOW_BITS _u(0x00010000) -#define IO_BANK0_INTR3_GPIO28_LEVEL_LOW_MSB _u(16) -#define IO_BANK0_INTR3_GPIO28_LEVEL_LOW_LSB _u(16) -#define IO_BANK0_INTR3_GPIO28_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR3_GPIO27_EDGE_HIGH -#define IO_BANK0_INTR3_GPIO27_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR3_GPIO27_EDGE_HIGH_BITS _u(0x00008000) -#define IO_BANK0_INTR3_GPIO27_EDGE_HIGH_MSB _u(15) -#define IO_BANK0_INTR3_GPIO27_EDGE_HIGH_LSB _u(15) -#define IO_BANK0_INTR3_GPIO27_EDGE_HIGH_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR3_GPIO27_EDGE_LOW -#define IO_BANK0_INTR3_GPIO27_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_INTR3_GPIO27_EDGE_LOW_BITS _u(0x00004000) -#define IO_BANK0_INTR3_GPIO27_EDGE_LOW_MSB _u(14) -#define IO_BANK0_INTR3_GPIO27_EDGE_LOW_LSB _u(14) -#define IO_BANK0_INTR3_GPIO27_EDGE_LOW_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR3_GPIO27_LEVEL_HIGH -#define IO_BANK0_INTR3_GPIO27_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR3_GPIO27_LEVEL_HIGH_BITS _u(0x00002000) -#define IO_BANK0_INTR3_GPIO27_LEVEL_HIGH_MSB _u(13) -#define IO_BANK0_INTR3_GPIO27_LEVEL_HIGH_LSB _u(13) -#define IO_BANK0_INTR3_GPIO27_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR3_GPIO27_LEVEL_LOW -#define IO_BANK0_INTR3_GPIO27_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_INTR3_GPIO27_LEVEL_LOW_BITS _u(0x00001000) -#define IO_BANK0_INTR3_GPIO27_LEVEL_LOW_MSB _u(12) -#define IO_BANK0_INTR3_GPIO27_LEVEL_LOW_LSB _u(12) -#define IO_BANK0_INTR3_GPIO27_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR3_GPIO26_EDGE_HIGH -#define IO_BANK0_INTR3_GPIO26_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR3_GPIO26_EDGE_HIGH_BITS _u(0x00000800) -#define IO_BANK0_INTR3_GPIO26_EDGE_HIGH_MSB _u(11) -#define IO_BANK0_INTR3_GPIO26_EDGE_HIGH_LSB _u(11) -#define IO_BANK0_INTR3_GPIO26_EDGE_HIGH_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR3_GPIO26_EDGE_LOW -#define IO_BANK0_INTR3_GPIO26_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_INTR3_GPIO26_EDGE_LOW_BITS _u(0x00000400) -#define IO_BANK0_INTR3_GPIO26_EDGE_LOW_MSB _u(10) -#define IO_BANK0_INTR3_GPIO26_EDGE_LOW_LSB _u(10) -#define IO_BANK0_INTR3_GPIO26_EDGE_LOW_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR3_GPIO26_LEVEL_HIGH -#define IO_BANK0_INTR3_GPIO26_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR3_GPIO26_LEVEL_HIGH_BITS _u(0x00000200) -#define IO_BANK0_INTR3_GPIO26_LEVEL_HIGH_MSB _u(9) -#define IO_BANK0_INTR3_GPIO26_LEVEL_HIGH_LSB _u(9) -#define IO_BANK0_INTR3_GPIO26_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR3_GPIO26_LEVEL_LOW -#define IO_BANK0_INTR3_GPIO26_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_INTR3_GPIO26_LEVEL_LOW_BITS _u(0x00000100) -#define IO_BANK0_INTR3_GPIO26_LEVEL_LOW_MSB _u(8) -#define IO_BANK0_INTR3_GPIO26_LEVEL_LOW_LSB _u(8) -#define IO_BANK0_INTR3_GPIO26_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR3_GPIO25_EDGE_HIGH -#define IO_BANK0_INTR3_GPIO25_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR3_GPIO25_EDGE_HIGH_BITS _u(0x00000080) -#define IO_BANK0_INTR3_GPIO25_EDGE_HIGH_MSB _u(7) -#define IO_BANK0_INTR3_GPIO25_EDGE_HIGH_LSB _u(7) -#define IO_BANK0_INTR3_GPIO25_EDGE_HIGH_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR3_GPIO25_EDGE_LOW -#define IO_BANK0_INTR3_GPIO25_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_INTR3_GPIO25_EDGE_LOW_BITS _u(0x00000040) -#define IO_BANK0_INTR3_GPIO25_EDGE_LOW_MSB _u(6) -#define IO_BANK0_INTR3_GPIO25_EDGE_LOW_LSB _u(6) -#define IO_BANK0_INTR3_GPIO25_EDGE_LOW_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR3_GPIO25_LEVEL_HIGH -#define IO_BANK0_INTR3_GPIO25_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR3_GPIO25_LEVEL_HIGH_BITS _u(0x00000020) -#define IO_BANK0_INTR3_GPIO25_LEVEL_HIGH_MSB _u(5) -#define IO_BANK0_INTR3_GPIO25_LEVEL_HIGH_LSB _u(5) -#define IO_BANK0_INTR3_GPIO25_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR3_GPIO25_LEVEL_LOW -#define IO_BANK0_INTR3_GPIO25_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_INTR3_GPIO25_LEVEL_LOW_BITS _u(0x00000010) -#define IO_BANK0_INTR3_GPIO25_LEVEL_LOW_MSB _u(4) -#define IO_BANK0_INTR3_GPIO25_LEVEL_LOW_LSB _u(4) -#define IO_BANK0_INTR3_GPIO25_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR3_GPIO24_EDGE_HIGH -#define IO_BANK0_INTR3_GPIO24_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR3_GPIO24_EDGE_HIGH_BITS _u(0x00000008) -#define IO_BANK0_INTR3_GPIO24_EDGE_HIGH_MSB _u(3) -#define IO_BANK0_INTR3_GPIO24_EDGE_HIGH_LSB _u(3) -#define IO_BANK0_INTR3_GPIO24_EDGE_HIGH_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR3_GPIO24_EDGE_LOW -#define IO_BANK0_INTR3_GPIO24_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_INTR3_GPIO24_EDGE_LOW_BITS _u(0x00000004) -#define IO_BANK0_INTR3_GPIO24_EDGE_LOW_MSB _u(2) -#define IO_BANK0_INTR3_GPIO24_EDGE_LOW_LSB _u(2) -#define IO_BANK0_INTR3_GPIO24_EDGE_LOW_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR3_GPIO24_LEVEL_HIGH -#define IO_BANK0_INTR3_GPIO24_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR3_GPIO24_LEVEL_HIGH_BITS _u(0x00000002) -#define IO_BANK0_INTR3_GPIO24_LEVEL_HIGH_MSB _u(1) -#define IO_BANK0_INTR3_GPIO24_LEVEL_HIGH_LSB _u(1) -#define IO_BANK0_INTR3_GPIO24_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR3_GPIO24_LEVEL_LOW -#define IO_BANK0_INTR3_GPIO24_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_INTR3_GPIO24_LEVEL_LOW_BITS _u(0x00000001) -#define IO_BANK0_INTR3_GPIO24_LEVEL_LOW_MSB _u(0) -#define IO_BANK0_INTR3_GPIO24_LEVEL_LOW_LSB _u(0) -#define IO_BANK0_INTR3_GPIO24_LEVEL_LOW_ACCESS "RO" -// ============================================================================= -// Register : IO_BANK0_INTR4 -// Description : Raw Interrupts -#define IO_BANK0_INTR4_OFFSET _u(0x00000240) -#define IO_BANK0_INTR4_BITS _u(0xffffffff) -#define IO_BANK0_INTR4_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR4_GPIO39_EDGE_HIGH -#define IO_BANK0_INTR4_GPIO39_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR4_GPIO39_EDGE_HIGH_BITS _u(0x80000000) -#define IO_BANK0_INTR4_GPIO39_EDGE_HIGH_MSB _u(31) -#define IO_BANK0_INTR4_GPIO39_EDGE_HIGH_LSB _u(31) -#define IO_BANK0_INTR4_GPIO39_EDGE_HIGH_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR4_GPIO39_EDGE_LOW -#define IO_BANK0_INTR4_GPIO39_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_INTR4_GPIO39_EDGE_LOW_BITS _u(0x40000000) -#define IO_BANK0_INTR4_GPIO39_EDGE_LOW_MSB _u(30) -#define IO_BANK0_INTR4_GPIO39_EDGE_LOW_LSB _u(30) -#define IO_BANK0_INTR4_GPIO39_EDGE_LOW_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR4_GPIO39_LEVEL_HIGH -#define IO_BANK0_INTR4_GPIO39_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR4_GPIO39_LEVEL_HIGH_BITS _u(0x20000000) -#define IO_BANK0_INTR4_GPIO39_LEVEL_HIGH_MSB _u(29) -#define IO_BANK0_INTR4_GPIO39_LEVEL_HIGH_LSB _u(29) -#define IO_BANK0_INTR4_GPIO39_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR4_GPIO39_LEVEL_LOW -#define IO_BANK0_INTR4_GPIO39_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_INTR4_GPIO39_LEVEL_LOW_BITS _u(0x10000000) -#define IO_BANK0_INTR4_GPIO39_LEVEL_LOW_MSB _u(28) -#define IO_BANK0_INTR4_GPIO39_LEVEL_LOW_LSB _u(28) -#define IO_BANK0_INTR4_GPIO39_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR4_GPIO38_EDGE_HIGH -#define IO_BANK0_INTR4_GPIO38_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR4_GPIO38_EDGE_HIGH_BITS _u(0x08000000) -#define IO_BANK0_INTR4_GPIO38_EDGE_HIGH_MSB _u(27) -#define IO_BANK0_INTR4_GPIO38_EDGE_HIGH_LSB _u(27) -#define IO_BANK0_INTR4_GPIO38_EDGE_HIGH_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR4_GPIO38_EDGE_LOW -#define IO_BANK0_INTR4_GPIO38_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_INTR4_GPIO38_EDGE_LOW_BITS _u(0x04000000) -#define IO_BANK0_INTR4_GPIO38_EDGE_LOW_MSB _u(26) -#define IO_BANK0_INTR4_GPIO38_EDGE_LOW_LSB _u(26) -#define IO_BANK0_INTR4_GPIO38_EDGE_LOW_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR4_GPIO38_LEVEL_HIGH -#define IO_BANK0_INTR4_GPIO38_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR4_GPIO38_LEVEL_HIGH_BITS _u(0x02000000) -#define IO_BANK0_INTR4_GPIO38_LEVEL_HIGH_MSB _u(25) -#define IO_BANK0_INTR4_GPIO38_LEVEL_HIGH_LSB _u(25) -#define IO_BANK0_INTR4_GPIO38_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR4_GPIO38_LEVEL_LOW -#define IO_BANK0_INTR4_GPIO38_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_INTR4_GPIO38_LEVEL_LOW_BITS _u(0x01000000) -#define IO_BANK0_INTR4_GPIO38_LEVEL_LOW_MSB _u(24) -#define IO_BANK0_INTR4_GPIO38_LEVEL_LOW_LSB _u(24) -#define IO_BANK0_INTR4_GPIO38_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR4_GPIO37_EDGE_HIGH -#define IO_BANK0_INTR4_GPIO37_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR4_GPIO37_EDGE_HIGH_BITS _u(0x00800000) -#define IO_BANK0_INTR4_GPIO37_EDGE_HIGH_MSB _u(23) -#define IO_BANK0_INTR4_GPIO37_EDGE_HIGH_LSB _u(23) -#define IO_BANK0_INTR4_GPIO37_EDGE_HIGH_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR4_GPIO37_EDGE_LOW -#define IO_BANK0_INTR4_GPIO37_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_INTR4_GPIO37_EDGE_LOW_BITS _u(0x00400000) -#define IO_BANK0_INTR4_GPIO37_EDGE_LOW_MSB _u(22) -#define IO_BANK0_INTR4_GPIO37_EDGE_LOW_LSB _u(22) -#define IO_BANK0_INTR4_GPIO37_EDGE_LOW_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR4_GPIO37_LEVEL_HIGH -#define IO_BANK0_INTR4_GPIO37_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR4_GPIO37_LEVEL_HIGH_BITS _u(0x00200000) -#define IO_BANK0_INTR4_GPIO37_LEVEL_HIGH_MSB _u(21) -#define IO_BANK0_INTR4_GPIO37_LEVEL_HIGH_LSB _u(21) -#define IO_BANK0_INTR4_GPIO37_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR4_GPIO37_LEVEL_LOW -#define IO_BANK0_INTR4_GPIO37_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_INTR4_GPIO37_LEVEL_LOW_BITS _u(0x00100000) -#define IO_BANK0_INTR4_GPIO37_LEVEL_LOW_MSB _u(20) -#define IO_BANK0_INTR4_GPIO37_LEVEL_LOW_LSB _u(20) -#define IO_BANK0_INTR4_GPIO37_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR4_GPIO36_EDGE_HIGH -#define IO_BANK0_INTR4_GPIO36_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR4_GPIO36_EDGE_HIGH_BITS _u(0x00080000) -#define IO_BANK0_INTR4_GPIO36_EDGE_HIGH_MSB _u(19) -#define IO_BANK0_INTR4_GPIO36_EDGE_HIGH_LSB _u(19) -#define IO_BANK0_INTR4_GPIO36_EDGE_HIGH_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR4_GPIO36_EDGE_LOW -#define IO_BANK0_INTR4_GPIO36_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_INTR4_GPIO36_EDGE_LOW_BITS _u(0x00040000) -#define IO_BANK0_INTR4_GPIO36_EDGE_LOW_MSB _u(18) -#define IO_BANK0_INTR4_GPIO36_EDGE_LOW_LSB _u(18) -#define IO_BANK0_INTR4_GPIO36_EDGE_LOW_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR4_GPIO36_LEVEL_HIGH -#define IO_BANK0_INTR4_GPIO36_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR4_GPIO36_LEVEL_HIGH_BITS _u(0x00020000) -#define IO_BANK0_INTR4_GPIO36_LEVEL_HIGH_MSB _u(17) -#define IO_BANK0_INTR4_GPIO36_LEVEL_HIGH_LSB _u(17) -#define IO_BANK0_INTR4_GPIO36_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR4_GPIO36_LEVEL_LOW -#define IO_BANK0_INTR4_GPIO36_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_INTR4_GPIO36_LEVEL_LOW_BITS _u(0x00010000) -#define IO_BANK0_INTR4_GPIO36_LEVEL_LOW_MSB _u(16) -#define IO_BANK0_INTR4_GPIO36_LEVEL_LOW_LSB _u(16) -#define IO_BANK0_INTR4_GPIO36_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR4_GPIO35_EDGE_HIGH -#define IO_BANK0_INTR4_GPIO35_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR4_GPIO35_EDGE_HIGH_BITS _u(0x00008000) -#define IO_BANK0_INTR4_GPIO35_EDGE_HIGH_MSB _u(15) -#define IO_BANK0_INTR4_GPIO35_EDGE_HIGH_LSB _u(15) -#define IO_BANK0_INTR4_GPIO35_EDGE_HIGH_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR4_GPIO35_EDGE_LOW -#define IO_BANK0_INTR4_GPIO35_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_INTR4_GPIO35_EDGE_LOW_BITS _u(0x00004000) -#define IO_BANK0_INTR4_GPIO35_EDGE_LOW_MSB _u(14) -#define IO_BANK0_INTR4_GPIO35_EDGE_LOW_LSB _u(14) -#define IO_BANK0_INTR4_GPIO35_EDGE_LOW_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR4_GPIO35_LEVEL_HIGH -#define IO_BANK0_INTR4_GPIO35_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR4_GPIO35_LEVEL_HIGH_BITS _u(0x00002000) -#define IO_BANK0_INTR4_GPIO35_LEVEL_HIGH_MSB _u(13) -#define IO_BANK0_INTR4_GPIO35_LEVEL_HIGH_LSB _u(13) -#define IO_BANK0_INTR4_GPIO35_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR4_GPIO35_LEVEL_LOW -#define IO_BANK0_INTR4_GPIO35_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_INTR4_GPIO35_LEVEL_LOW_BITS _u(0x00001000) -#define IO_BANK0_INTR4_GPIO35_LEVEL_LOW_MSB _u(12) -#define IO_BANK0_INTR4_GPIO35_LEVEL_LOW_LSB _u(12) -#define IO_BANK0_INTR4_GPIO35_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR4_GPIO34_EDGE_HIGH -#define IO_BANK0_INTR4_GPIO34_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR4_GPIO34_EDGE_HIGH_BITS _u(0x00000800) -#define IO_BANK0_INTR4_GPIO34_EDGE_HIGH_MSB _u(11) -#define IO_BANK0_INTR4_GPIO34_EDGE_HIGH_LSB _u(11) -#define IO_BANK0_INTR4_GPIO34_EDGE_HIGH_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR4_GPIO34_EDGE_LOW -#define IO_BANK0_INTR4_GPIO34_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_INTR4_GPIO34_EDGE_LOW_BITS _u(0x00000400) -#define IO_BANK0_INTR4_GPIO34_EDGE_LOW_MSB _u(10) -#define IO_BANK0_INTR4_GPIO34_EDGE_LOW_LSB _u(10) -#define IO_BANK0_INTR4_GPIO34_EDGE_LOW_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR4_GPIO34_LEVEL_HIGH -#define IO_BANK0_INTR4_GPIO34_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR4_GPIO34_LEVEL_HIGH_BITS _u(0x00000200) -#define IO_BANK0_INTR4_GPIO34_LEVEL_HIGH_MSB _u(9) -#define IO_BANK0_INTR4_GPIO34_LEVEL_HIGH_LSB _u(9) -#define IO_BANK0_INTR4_GPIO34_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR4_GPIO34_LEVEL_LOW -#define IO_BANK0_INTR4_GPIO34_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_INTR4_GPIO34_LEVEL_LOW_BITS _u(0x00000100) -#define IO_BANK0_INTR4_GPIO34_LEVEL_LOW_MSB _u(8) -#define IO_BANK0_INTR4_GPIO34_LEVEL_LOW_LSB _u(8) -#define IO_BANK0_INTR4_GPIO34_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR4_GPIO33_EDGE_HIGH -#define IO_BANK0_INTR4_GPIO33_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR4_GPIO33_EDGE_HIGH_BITS _u(0x00000080) -#define IO_BANK0_INTR4_GPIO33_EDGE_HIGH_MSB _u(7) -#define IO_BANK0_INTR4_GPIO33_EDGE_HIGH_LSB _u(7) -#define IO_BANK0_INTR4_GPIO33_EDGE_HIGH_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR4_GPIO33_EDGE_LOW -#define IO_BANK0_INTR4_GPIO33_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_INTR4_GPIO33_EDGE_LOW_BITS _u(0x00000040) -#define IO_BANK0_INTR4_GPIO33_EDGE_LOW_MSB _u(6) -#define IO_BANK0_INTR4_GPIO33_EDGE_LOW_LSB _u(6) -#define IO_BANK0_INTR4_GPIO33_EDGE_LOW_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR4_GPIO33_LEVEL_HIGH -#define IO_BANK0_INTR4_GPIO33_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR4_GPIO33_LEVEL_HIGH_BITS _u(0x00000020) -#define IO_BANK0_INTR4_GPIO33_LEVEL_HIGH_MSB _u(5) -#define IO_BANK0_INTR4_GPIO33_LEVEL_HIGH_LSB _u(5) -#define IO_BANK0_INTR4_GPIO33_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR4_GPIO33_LEVEL_LOW -#define IO_BANK0_INTR4_GPIO33_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_INTR4_GPIO33_LEVEL_LOW_BITS _u(0x00000010) -#define IO_BANK0_INTR4_GPIO33_LEVEL_LOW_MSB _u(4) -#define IO_BANK0_INTR4_GPIO33_LEVEL_LOW_LSB _u(4) -#define IO_BANK0_INTR4_GPIO33_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR4_GPIO32_EDGE_HIGH -#define IO_BANK0_INTR4_GPIO32_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR4_GPIO32_EDGE_HIGH_BITS _u(0x00000008) -#define IO_BANK0_INTR4_GPIO32_EDGE_HIGH_MSB _u(3) -#define IO_BANK0_INTR4_GPIO32_EDGE_HIGH_LSB _u(3) -#define IO_BANK0_INTR4_GPIO32_EDGE_HIGH_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR4_GPIO32_EDGE_LOW -#define IO_BANK0_INTR4_GPIO32_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_INTR4_GPIO32_EDGE_LOW_BITS _u(0x00000004) -#define IO_BANK0_INTR4_GPIO32_EDGE_LOW_MSB _u(2) -#define IO_BANK0_INTR4_GPIO32_EDGE_LOW_LSB _u(2) -#define IO_BANK0_INTR4_GPIO32_EDGE_LOW_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR4_GPIO32_LEVEL_HIGH -#define IO_BANK0_INTR4_GPIO32_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR4_GPIO32_LEVEL_HIGH_BITS _u(0x00000002) -#define IO_BANK0_INTR4_GPIO32_LEVEL_HIGH_MSB _u(1) -#define IO_BANK0_INTR4_GPIO32_LEVEL_HIGH_LSB _u(1) -#define IO_BANK0_INTR4_GPIO32_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR4_GPIO32_LEVEL_LOW -#define IO_BANK0_INTR4_GPIO32_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_INTR4_GPIO32_LEVEL_LOW_BITS _u(0x00000001) -#define IO_BANK0_INTR4_GPIO32_LEVEL_LOW_MSB _u(0) -#define IO_BANK0_INTR4_GPIO32_LEVEL_LOW_LSB _u(0) -#define IO_BANK0_INTR4_GPIO32_LEVEL_LOW_ACCESS "RO" -// ============================================================================= -// Register : IO_BANK0_INTR5 -// Description : Raw Interrupts -#define IO_BANK0_INTR5_OFFSET _u(0x00000244) -#define IO_BANK0_INTR5_BITS _u(0xffffffff) -#define IO_BANK0_INTR5_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR5_GPIO47_EDGE_HIGH -#define IO_BANK0_INTR5_GPIO47_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR5_GPIO47_EDGE_HIGH_BITS _u(0x80000000) -#define IO_BANK0_INTR5_GPIO47_EDGE_HIGH_MSB _u(31) -#define IO_BANK0_INTR5_GPIO47_EDGE_HIGH_LSB _u(31) -#define IO_BANK0_INTR5_GPIO47_EDGE_HIGH_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR5_GPIO47_EDGE_LOW -#define IO_BANK0_INTR5_GPIO47_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_INTR5_GPIO47_EDGE_LOW_BITS _u(0x40000000) -#define IO_BANK0_INTR5_GPIO47_EDGE_LOW_MSB _u(30) -#define IO_BANK0_INTR5_GPIO47_EDGE_LOW_LSB _u(30) -#define IO_BANK0_INTR5_GPIO47_EDGE_LOW_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR5_GPIO47_LEVEL_HIGH -#define IO_BANK0_INTR5_GPIO47_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR5_GPIO47_LEVEL_HIGH_BITS _u(0x20000000) -#define IO_BANK0_INTR5_GPIO47_LEVEL_HIGH_MSB _u(29) -#define IO_BANK0_INTR5_GPIO47_LEVEL_HIGH_LSB _u(29) -#define IO_BANK0_INTR5_GPIO47_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR5_GPIO47_LEVEL_LOW -#define IO_BANK0_INTR5_GPIO47_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_INTR5_GPIO47_LEVEL_LOW_BITS _u(0x10000000) -#define IO_BANK0_INTR5_GPIO47_LEVEL_LOW_MSB _u(28) -#define IO_BANK0_INTR5_GPIO47_LEVEL_LOW_LSB _u(28) -#define IO_BANK0_INTR5_GPIO47_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR5_GPIO46_EDGE_HIGH -#define IO_BANK0_INTR5_GPIO46_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR5_GPIO46_EDGE_HIGH_BITS _u(0x08000000) -#define IO_BANK0_INTR5_GPIO46_EDGE_HIGH_MSB _u(27) -#define IO_BANK0_INTR5_GPIO46_EDGE_HIGH_LSB _u(27) -#define IO_BANK0_INTR5_GPIO46_EDGE_HIGH_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR5_GPIO46_EDGE_LOW -#define IO_BANK0_INTR5_GPIO46_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_INTR5_GPIO46_EDGE_LOW_BITS _u(0x04000000) -#define IO_BANK0_INTR5_GPIO46_EDGE_LOW_MSB _u(26) -#define IO_BANK0_INTR5_GPIO46_EDGE_LOW_LSB _u(26) -#define IO_BANK0_INTR5_GPIO46_EDGE_LOW_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR5_GPIO46_LEVEL_HIGH -#define IO_BANK0_INTR5_GPIO46_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR5_GPIO46_LEVEL_HIGH_BITS _u(0x02000000) -#define IO_BANK0_INTR5_GPIO46_LEVEL_HIGH_MSB _u(25) -#define IO_BANK0_INTR5_GPIO46_LEVEL_HIGH_LSB _u(25) -#define IO_BANK0_INTR5_GPIO46_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR5_GPIO46_LEVEL_LOW -#define IO_BANK0_INTR5_GPIO46_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_INTR5_GPIO46_LEVEL_LOW_BITS _u(0x01000000) -#define IO_BANK0_INTR5_GPIO46_LEVEL_LOW_MSB _u(24) -#define IO_BANK0_INTR5_GPIO46_LEVEL_LOW_LSB _u(24) -#define IO_BANK0_INTR5_GPIO46_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR5_GPIO45_EDGE_HIGH -#define IO_BANK0_INTR5_GPIO45_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR5_GPIO45_EDGE_HIGH_BITS _u(0x00800000) -#define IO_BANK0_INTR5_GPIO45_EDGE_HIGH_MSB _u(23) -#define IO_BANK0_INTR5_GPIO45_EDGE_HIGH_LSB _u(23) -#define IO_BANK0_INTR5_GPIO45_EDGE_HIGH_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR5_GPIO45_EDGE_LOW -#define IO_BANK0_INTR5_GPIO45_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_INTR5_GPIO45_EDGE_LOW_BITS _u(0x00400000) -#define IO_BANK0_INTR5_GPIO45_EDGE_LOW_MSB _u(22) -#define IO_BANK0_INTR5_GPIO45_EDGE_LOW_LSB _u(22) -#define IO_BANK0_INTR5_GPIO45_EDGE_LOW_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR5_GPIO45_LEVEL_HIGH -#define IO_BANK0_INTR5_GPIO45_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR5_GPIO45_LEVEL_HIGH_BITS _u(0x00200000) -#define IO_BANK0_INTR5_GPIO45_LEVEL_HIGH_MSB _u(21) -#define IO_BANK0_INTR5_GPIO45_LEVEL_HIGH_LSB _u(21) -#define IO_BANK0_INTR5_GPIO45_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR5_GPIO45_LEVEL_LOW -#define IO_BANK0_INTR5_GPIO45_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_INTR5_GPIO45_LEVEL_LOW_BITS _u(0x00100000) -#define IO_BANK0_INTR5_GPIO45_LEVEL_LOW_MSB _u(20) -#define IO_BANK0_INTR5_GPIO45_LEVEL_LOW_LSB _u(20) -#define IO_BANK0_INTR5_GPIO45_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR5_GPIO44_EDGE_HIGH -#define IO_BANK0_INTR5_GPIO44_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR5_GPIO44_EDGE_HIGH_BITS _u(0x00080000) -#define IO_BANK0_INTR5_GPIO44_EDGE_HIGH_MSB _u(19) -#define IO_BANK0_INTR5_GPIO44_EDGE_HIGH_LSB _u(19) -#define IO_BANK0_INTR5_GPIO44_EDGE_HIGH_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR5_GPIO44_EDGE_LOW -#define IO_BANK0_INTR5_GPIO44_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_INTR5_GPIO44_EDGE_LOW_BITS _u(0x00040000) -#define IO_BANK0_INTR5_GPIO44_EDGE_LOW_MSB _u(18) -#define IO_BANK0_INTR5_GPIO44_EDGE_LOW_LSB _u(18) -#define IO_BANK0_INTR5_GPIO44_EDGE_LOW_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR5_GPIO44_LEVEL_HIGH -#define IO_BANK0_INTR5_GPIO44_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR5_GPIO44_LEVEL_HIGH_BITS _u(0x00020000) -#define IO_BANK0_INTR5_GPIO44_LEVEL_HIGH_MSB _u(17) -#define IO_BANK0_INTR5_GPIO44_LEVEL_HIGH_LSB _u(17) -#define IO_BANK0_INTR5_GPIO44_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR5_GPIO44_LEVEL_LOW -#define IO_BANK0_INTR5_GPIO44_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_INTR5_GPIO44_LEVEL_LOW_BITS _u(0x00010000) -#define IO_BANK0_INTR5_GPIO44_LEVEL_LOW_MSB _u(16) -#define IO_BANK0_INTR5_GPIO44_LEVEL_LOW_LSB _u(16) -#define IO_BANK0_INTR5_GPIO44_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR5_GPIO43_EDGE_HIGH -#define IO_BANK0_INTR5_GPIO43_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR5_GPIO43_EDGE_HIGH_BITS _u(0x00008000) -#define IO_BANK0_INTR5_GPIO43_EDGE_HIGH_MSB _u(15) -#define IO_BANK0_INTR5_GPIO43_EDGE_HIGH_LSB _u(15) -#define IO_BANK0_INTR5_GPIO43_EDGE_HIGH_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR5_GPIO43_EDGE_LOW -#define IO_BANK0_INTR5_GPIO43_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_INTR5_GPIO43_EDGE_LOW_BITS _u(0x00004000) -#define IO_BANK0_INTR5_GPIO43_EDGE_LOW_MSB _u(14) -#define IO_BANK0_INTR5_GPIO43_EDGE_LOW_LSB _u(14) -#define IO_BANK0_INTR5_GPIO43_EDGE_LOW_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR5_GPIO43_LEVEL_HIGH -#define IO_BANK0_INTR5_GPIO43_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR5_GPIO43_LEVEL_HIGH_BITS _u(0x00002000) -#define IO_BANK0_INTR5_GPIO43_LEVEL_HIGH_MSB _u(13) -#define IO_BANK0_INTR5_GPIO43_LEVEL_HIGH_LSB _u(13) -#define IO_BANK0_INTR5_GPIO43_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR5_GPIO43_LEVEL_LOW -#define IO_BANK0_INTR5_GPIO43_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_INTR5_GPIO43_LEVEL_LOW_BITS _u(0x00001000) -#define IO_BANK0_INTR5_GPIO43_LEVEL_LOW_MSB _u(12) -#define IO_BANK0_INTR5_GPIO43_LEVEL_LOW_LSB _u(12) -#define IO_BANK0_INTR5_GPIO43_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR5_GPIO42_EDGE_HIGH -#define IO_BANK0_INTR5_GPIO42_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR5_GPIO42_EDGE_HIGH_BITS _u(0x00000800) -#define IO_BANK0_INTR5_GPIO42_EDGE_HIGH_MSB _u(11) -#define IO_BANK0_INTR5_GPIO42_EDGE_HIGH_LSB _u(11) -#define IO_BANK0_INTR5_GPIO42_EDGE_HIGH_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR5_GPIO42_EDGE_LOW -#define IO_BANK0_INTR5_GPIO42_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_INTR5_GPIO42_EDGE_LOW_BITS _u(0x00000400) -#define IO_BANK0_INTR5_GPIO42_EDGE_LOW_MSB _u(10) -#define IO_BANK0_INTR5_GPIO42_EDGE_LOW_LSB _u(10) -#define IO_BANK0_INTR5_GPIO42_EDGE_LOW_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR5_GPIO42_LEVEL_HIGH -#define IO_BANK0_INTR5_GPIO42_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR5_GPIO42_LEVEL_HIGH_BITS _u(0x00000200) -#define IO_BANK0_INTR5_GPIO42_LEVEL_HIGH_MSB _u(9) -#define IO_BANK0_INTR5_GPIO42_LEVEL_HIGH_LSB _u(9) -#define IO_BANK0_INTR5_GPIO42_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR5_GPIO42_LEVEL_LOW -#define IO_BANK0_INTR5_GPIO42_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_INTR5_GPIO42_LEVEL_LOW_BITS _u(0x00000100) -#define IO_BANK0_INTR5_GPIO42_LEVEL_LOW_MSB _u(8) -#define IO_BANK0_INTR5_GPIO42_LEVEL_LOW_LSB _u(8) -#define IO_BANK0_INTR5_GPIO42_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR5_GPIO41_EDGE_HIGH -#define IO_BANK0_INTR5_GPIO41_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR5_GPIO41_EDGE_HIGH_BITS _u(0x00000080) -#define IO_BANK0_INTR5_GPIO41_EDGE_HIGH_MSB _u(7) -#define IO_BANK0_INTR5_GPIO41_EDGE_HIGH_LSB _u(7) -#define IO_BANK0_INTR5_GPIO41_EDGE_HIGH_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR5_GPIO41_EDGE_LOW -#define IO_BANK0_INTR5_GPIO41_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_INTR5_GPIO41_EDGE_LOW_BITS _u(0x00000040) -#define IO_BANK0_INTR5_GPIO41_EDGE_LOW_MSB _u(6) -#define IO_BANK0_INTR5_GPIO41_EDGE_LOW_LSB _u(6) -#define IO_BANK0_INTR5_GPIO41_EDGE_LOW_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR5_GPIO41_LEVEL_HIGH -#define IO_BANK0_INTR5_GPIO41_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR5_GPIO41_LEVEL_HIGH_BITS _u(0x00000020) -#define IO_BANK0_INTR5_GPIO41_LEVEL_HIGH_MSB _u(5) -#define IO_BANK0_INTR5_GPIO41_LEVEL_HIGH_LSB _u(5) -#define IO_BANK0_INTR5_GPIO41_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR5_GPIO41_LEVEL_LOW -#define IO_BANK0_INTR5_GPIO41_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_INTR5_GPIO41_LEVEL_LOW_BITS _u(0x00000010) -#define IO_BANK0_INTR5_GPIO41_LEVEL_LOW_MSB _u(4) -#define IO_BANK0_INTR5_GPIO41_LEVEL_LOW_LSB _u(4) -#define IO_BANK0_INTR5_GPIO41_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR5_GPIO40_EDGE_HIGH -#define IO_BANK0_INTR5_GPIO40_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR5_GPIO40_EDGE_HIGH_BITS _u(0x00000008) -#define IO_BANK0_INTR5_GPIO40_EDGE_HIGH_MSB _u(3) -#define IO_BANK0_INTR5_GPIO40_EDGE_HIGH_LSB _u(3) -#define IO_BANK0_INTR5_GPIO40_EDGE_HIGH_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR5_GPIO40_EDGE_LOW -#define IO_BANK0_INTR5_GPIO40_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_INTR5_GPIO40_EDGE_LOW_BITS _u(0x00000004) -#define IO_BANK0_INTR5_GPIO40_EDGE_LOW_MSB _u(2) -#define IO_BANK0_INTR5_GPIO40_EDGE_LOW_LSB _u(2) -#define IO_BANK0_INTR5_GPIO40_EDGE_LOW_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR5_GPIO40_LEVEL_HIGH -#define IO_BANK0_INTR5_GPIO40_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_INTR5_GPIO40_LEVEL_HIGH_BITS _u(0x00000002) -#define IO_BANK0_INTR5_GPIO40_LEVEL_HIGH_MSB _u(1) -#define IO_BANK0_INTR5_GPIO40_LEVEL_HIGH_LSB _u(1) -#define IO_BANK0_INTR5_GPIO40_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_INTR5_GPIO40_LEVEL_LOW -#define IO_BANK0_INTR5_GPIO40_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_INTR5_GPIO40_LEVEL_LOW_BITS _u(0x00000001) -#define IO_BANK0_INTR5_GPIO40_LEVEL_LOW_MSB _u(0) -#define IO_BANK0_INTR5_GPIO40_LEVEL_LOW_LSB _u(0) -#define IO_BANK0_INTR5_GPIO40_LEVEL_LOW_ACCESS "RO" -// ============================================================================= -// Register : IO_BANK0_PROC0_INTE0 -// Description : Interrupt Enable for proc0 -#define IO_BANK0_PROC0_INTE0_OFFSET _u(0x00000248) -#define IO_BANK0_PROC0_INTE0_BITS _u(0xffffffff) -#define IO_BANK0_PROC0_INTE0_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE0_GPIO7_EDGE_HIGH -#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_HIGH_BITS _u(0x80000000) -#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_HIGH_MSB _u(31) -#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_HIGH_LSB _u(31) -#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE0_GPIO7_EDGE_LOW -#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_LOW_BITS _u(0x40000000) -#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_LOW_MSB _u(30) -#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_LOW_LSB _u(30) -#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_HIGH -#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_HIGH_BITS _u(0x20000000) -#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_HIGH_MSB _u(29) -#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_HIGH_LSB _u(29) -#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_LOW -#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_LOW_BITS _u(0x10000000) -#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_LOW_MSB _u(28) -#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_LOW_LSB _u(28) -#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE0_GPIO6_EDGE_HIGH -#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_HIGH_BITS _u(0x08000000) -#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_HIGH_MSB _u(27) -#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_HIGH_LSB _u(27) -#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE0_GPIO6_EDGE_LOW -#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_LOW_BITS _u(0x04000000) -#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_LOW_MSB _u(26) -#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_LOW_LSB _u(26) -#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_HIGH -#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_HIGH_BITS _u(0x02000000) -#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_HIGH_MSB _u(25) -#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_HIGH_LSB _u(25) -#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_LOW -#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_LOW_BITS _u(0x01000000) -#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_LOW_MSB _u(24) -#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_LOW_LSB _u(24) -#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE0_GPIO5_EDGE_HIGH -#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_HIGH_BITS _u(0x00800000) -#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_HIGH_MSB _u(23) -#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_HIGH_LSB _u(23) -#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE0_GPIO5_EDGE_LOW -#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_LOW_BITS _u(0x00400000) -#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_LOW_MSB _u(22) -#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_LOW_LSB _u(22) -#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_HIGH -#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_HIGH_BITS _u(0x00200000) -#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_HIGH_MSB _u(21) -#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_HIGH_LSB _u(21) -#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_LOW -#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_LOW_BITS _u(0x00100000) -#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_LOW_MSB _u(20) -#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_LOW_LSB _u(20) -#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE0_GPIO4_EDGE_HIGH -#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_HIGH_BITS _u(0x00080000) -#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_HIGH_MSB _u(19) -#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_HIGH_LSB _u(19) -#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE0_GPIO4_EDGE_LOW -#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_LOW_BITS _u(0x00040000) -#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_LOW_MSB _u(18) -#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_LOW_LSB _u(18) -#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_HIGH -#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_HIGH_BITS _u(0x00020000) -#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_HIGH_MSB _u(17) -#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_HIGH_LSB _u(17) -#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_LOW -#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_LOW_BITS _u(0x00010000) -#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_LOW_MSB _u(16) -#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_LOW_LSB _u(16) -#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE0_GPIO3_EDGE_HIGH -#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_HIGH_BITS _u(0x00008000) -#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_HIGH_MSB _u(15) -#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_HIGH_LSB _u(15) -#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE0_GPIO3_EDGE_LOW -#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_LOW_BITS _u(0x00004000) -#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_LOW_MSB _u(14) -#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_LOW_LSB _u(14) -#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_HIGH -#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_HIGH_BITS _u(0x00002000) -#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_HIGH_MSB _u(13) -#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_HIGH_LSB _u(13) -#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_LOW -#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_LOW_BITS _u(0x00001000) -#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_LOW_MSB _u(12) -#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_LOW_LSB _u(12) -#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE0_GPIO2_EDGE_HIGH -#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_HIGH_BITS _u(0x00000800) -#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_HIGH_MSB _u(11) -#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_HIGH_LSB _u(11) -#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE0_GPIO2_EDGE_LOW -#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_LOW_BITS _u(0x00000400) -#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_LOW_MSB _u(10) -#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_LOW_LSB _u(10) -#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_HIGH -#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_HIGH_BITS _u(0x00000200) -#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_HIGH_MSB _u(9) -#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_HIGH_LSB _u(9) -#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_LOW -#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_LOW_BITS _u(0x00000100) -#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_LOW_MSB _u(8) -#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_LOW_LSB _u(8) -#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE0_GPIO1_EDGE_HIGH -#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_HIGH_BITS _u(0x00000080) -#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_HIGH_MSB _u(7) -#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_HIGH_LSB _u(7) -#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE0_GPIO1_EDGE_LOW -#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_LOW_BITS _u(0x00000040) -#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_LOW_MSB _u(6) -#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_LOW_LSB _u(6) -#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_HIGH -#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_HIGH_BITS _u(0x00000020) -#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_HIGH_MSB _u(5) -#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_HIGH_LSB _u(5) -#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_LOW -#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_LOW_BITS _u(0x00000010) -#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_LOW_MSB _u(4) -#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_LOW_LSB _u(4) -#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE0_GPIO0_EDGE_HIGH -#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_HIGH_BITS _u(0x00000008) -#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_HIGH_MSB _u(3) -#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_HIGH_LSB _u(3) -#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE0_GPIO0_EDGE_LOW -#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_LOW_BITS _u(0x00000004) -#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_LOW_MSB _u(2) -#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_LOW_LSB _u(2) -#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_HIGH -#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_HIGH_BITS _u(0x00000002) -#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_HIGH_MSB _u(1) -#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_HIGH_LSB _u(1) -#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_LOW -#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_LOW_BITS _u(0x00000001) -#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_LOW_MSB _u(0) -#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_LOW_LSB _u(0) -#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_LOW_ACCESS "RW" -// ============================================================================= -// Register : IO_BANK0_PROC0_INTE1 -// Description : Interrupt Enable for proc0 -#define IO_BANK0_PROC0_INTE1_OFFSET _u(0x0000024c) -#define IO_BANK0_PROC0_INTE1_BITS _u(0xffffffff) -#define IO_BANK0_PROC0_INTE1_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE1_GPIO15_EDGE_HIGH -#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_HIGH_BITS _u(0x80000000) -#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_HIGH_MSB _u(31) -#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_HIGH_LSB _u(31) -#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE1_GPIO15_EDGE_LOW -#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_LOW_BITS _u(0x40000000) -#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_LOW_MSB _u(30) -#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_LOW_LSB _u(30) -#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_HIGH -#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_HIGH_BITS _u(0x20000000) -#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_HIGH_MSB _u(29) -#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_HIGH_LSB _u(29) -#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_LOW -#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_LOW_BITS _u(0x10000000) -#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_LOW_MSB _u(28) -#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_LOW_LSB _u(28) -#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE1_GPIO14_EDGE_HIGH -#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_HIGH_BITS _u(0x08000000) -#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_HIGH_MSB _u(27) -#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_HIGH_LSB _u(27) -#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE1_GPIO14_EDGE_LOW -#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_LOW_BITS _u(0x04000000) -#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_LOW_MSB _u(26) -#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_LOW_LSB _u(26) -#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_HIGH -#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_HIGH_BITS _u(0x02000000) -#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_HIGH_MSB _u(25) -#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_HIGH_LSB _u(25) -#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_LOW -#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_LOW_BITS _u(0x01000000) -#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_LOW_MSB _u(24) -#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_LOW_LSB _u(24) -#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE1_GPIO13_EDGE_HIGH -#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_HIGH_BITS _u(0x00800000) -#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_HIGH_MSB _u(23) -#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_HIGH_LSB _u(23) -#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE1_GPIO13_EDGE_LOW -#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_LOW_BITS _u(0x00400000) -#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_LOW_MSB _u(22) -#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_LOW_LSB _u(22) -#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_HIGH -#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_HIGH_BITS _u(0x00200000) -#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_HIGH_MSB _u(21) -#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_HIGH_LSB _u(21) -#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_LOW -#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_LOW_BITS _u(0x00100000) -#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_LOW_MSB _u(20) -#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_LOW_LSB _u(20) -#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE1_GPIO12_EDGE_HIGH -#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_HIGH_BITS _u(0x00080000) -#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_HIGH_MSB _u(19) -#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_HIGH_LSB _u(19) -#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE1_GPIO12_EDGE_LOW -#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_LOW_BITS _u(0x00040000) -#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_LOW_MSB _u(18) -#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_LOW_LSB _u(18) -#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_HIGH -#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_HIGH_BITS _u(0x00020000) -#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_HIGH_MSB _u(17) -#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_HIGH_LSB _u(17) -#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_LOW -#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_LOW_BITS _u(0x00010000) -#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_LOW_MSB _u(16) -#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_LOW_LSB _u(16) -#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE1_GPIO11_EDGE_HIGH -#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_HIGH_BITS _u(0x00008000) -#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_HIGH_MSB _u(15) -#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_HIGH_LSB _u(15) -#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE1_GPIO11_EDGE_LOW -#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_LOW_BITS _u(0x00004000) -#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_LOW_MSB _u(14) -#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_LOW_LSB _u(14) -#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_HIGH -#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_HIGH_BITS _u(0x00002000) -#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_HIGH_MSB _u(13) -#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_HIGH_LSB _u(13) -#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_LOW -#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_LOW_BITS _u(0x00001000) -#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_LOW_MSB _u(12) -#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_LOW_LSB _u(12) -#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE1_GPIO10_EDGE_HIGH -#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_HIGH_BITS _u(0x00000800) -#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_HIGH_MSB _u(11) -#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_HIGH_LSB _u(11) -#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE1_GPIO10_EDGE_LOW -#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_LOW_BITS _u(0x00000400) -#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_LOW_MSB _u(10) -#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_LOW_LSB _u(10) -#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_HIGH -#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_HIGH_BITS _u(0x00000200) -#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_HIGH_MSB _u(9) -#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_HIGH_LSB _u(9) -#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_LOW -#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_LOW_BITS _u(0x00000100) -#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_LOW_MSB _u(8) -#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_LOW_LSB _u(8) -#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE1_GPIO9_EDGE_HIGH -#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_HIGH_BITS _u(0x00000080) -#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_HIGH_MSB _u(7) -#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_HIGH_LSB _u(7) -#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE1_GPIO9_EDGE_LOW -#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_LOW_BITS _u(0x00000040) -#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_LOW_MSB _u(6) -#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_LOW_LSB _u(6) -#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_HIGH -#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_HIGH_BITS _u(0x00000020) -#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_HIGH_MSB _u(5) -#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_HIGH_LSB _u(5) -#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_LOW -#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_LOW_BITS _u(0x00000010) -#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_LOW_MSB _u(4) -#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_LOW_LSB _u(4) -#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE1_GPIO8_EDGE_HIGH -#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_HIGH_BITS _u(0x00000008) -#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_HIGH_MSB _u(3) -#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_HIGH_LSB _u(3) -#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE1_GPIO8_EDGE_LOW -#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_LOW_BITS _u(0x00000004) -#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_LOW_MSB _u(2) -#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_LOW_LSB _u(2) -#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_HIGH -#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_HIGH_BITS _u(0x00000002) -#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_HIGH_MSB _u(1) -#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_HIGH_LSB _u(1) -#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_LOW -#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_LOW_BITS _u(0x00000001) -#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_LOW_MSB _u(0) -#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_LOW_LSB _u(0) -#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_LOW_ACCESS "RW" -// ============================================================================= -// Register : IO_BANK0_PROC0_INTE2 -// Description : Interrupt Enable for proc0 -#define IO_BANK0_PROC0_INTE2_OFFSET _u(0x00000250) -#define IO_BANK0_PROC0_INTE2_BITS _u(0xffffffff) -#define IO_BANK0_PROC0_INTE2_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE2_GPIO23_EDGE_HIGH -#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_HIGH_BITS _u(0x80000000) -#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_HIGH_MSB _u(31) -#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_HIGH_LSB _u(31) -#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE2_GPIO23_EDGE_LOW -#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_LOW_BITS _u(0x40000000) -#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_LOW_MSB _u(30) -#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_LOW_LSB _u(30) -#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_HIGH -#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_HIGH_BITS _u(0x20000000) -#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_HIGH_MSB _u(29) -#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_HIGH_LSB _u(29) -#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_LOW -#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_LOW_BITS _u(0x10000000) -#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_LOW_MSB _u(28) -#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_LOW_LSB _u(28) -#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE2_GPIO22_EDGE_HIGH -#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_HIGH_BITS _u(0x08000000) -#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_HIGH_MSB _u(27) -#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_HIGH_LSB _u(27) -#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE2_GPIO22_EDGE_LOW -#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_LOW_BITS _u(0x04000000) -#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_LOW_MSB _u(26) -#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_LOW_LSB _u(26) -#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_HIGH -#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_HIGH_BITS _u(0x02000000) -#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_HIGH_MSB _u(25) -#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_HIGH_LSB _u(25) -#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_LOW -#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_LOW_BITS _u(0x01000000) -#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_LOW_MSB _u(24) -#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_LOW_LSB _u(24) -#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE2_GPIO21_EDGE_HIGH -#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_HIGH_BITS _u(0x00800000) -#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_HIGH_MSB _u(23) -#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_HIGH_LSB _u(23) -#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE2_GPIO21_EDGE_LOW -#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_LOW_BITS _u(0x00400000) -#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_LOW_MSB _u(22) -#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_LOW_LSB _u(22) -#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_HIGH -#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_HIGH_BITS _u(0x00200000) -#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_HIGH_MSB _u(21) -#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_HIGH_LSB _u(21) -#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_LOW -#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_LOW_BITS _u(0x00100000) -#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_LOW_MSB _u(20) -#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_LOW_LSB _u(20) -#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE2_GPIO20_EDGE_HIGH -#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_HIGH_BITS _u(0x00080000) -#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_HIGH_MSB _u(19) -#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_HIGH_LSB _u(19) -#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE2_GPIO20_EDGE_LOW -#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_LOW_BITS _u(0x00040000) -#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_LOW_MSB _u(18) -#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_LOW_LSB _u(18) -#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_HIGH -#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_HIGH_BITS _u(0x00020000) -#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_HIGH_MSB _u(17) -#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_HIGH_LSB _u(17) -#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_LOW -#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_LOW_BITS _u(0x00010000) -#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_LOW_MSB _u(16) -#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_LOW_LSB _u(16) -#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE2_GPIO19_EDGE_HIGH -#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_HIGH_BITS _u(0x00008000) -#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_HIGH_MSB _u(15) -#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_HIGH_LSB _u(15) -#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE2_GPIO19_EDGE_LOW -#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_LOW_BITS _u(0x00004000) -#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_LOW_MSB _u(14) -#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_LOW_LSB _u(14) -#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_HIGH -#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_HIGH_BITS _u(0x00002000) -#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_HIGH_MSB _u(13) -#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_HIGH_LSB _u(13) -#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_LOW -#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_LOW_BITS _u(0x00001000) -#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_LOW_MSB _u(12) -#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_LOW_LSB _u(12) -#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE2_GPIO18_EDGE_HIGH -#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_HIGH_BITS _u(0x00000800) -#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_HIGH_MSB _u(11) -#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_HIGH_LSB _u(11) -#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE2_GPIO18_EDGE_LOW -#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_LOW_BITS _u(0x00000400) -#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_LOW_MSB _u(10) -#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_LOW_LSB _u(10) -#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_HIGH -#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_HIGH_BITS _u(0x00000200) -#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_HIGH_MSB _u(9) -#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_HIGH_LSB _u(9) -#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_LOW -#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_LOW_BITS _u(0x00000100) -#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_LOW_MSB _u(8) -#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_LOW_LSB _u(8) -#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE2_GPIO17_EDGE_HIGH -#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_HIGH_BITS _u(0x00000080) -#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_HIGH_MSB _u(7) -#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_HIGH_LSB _u(7) -#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE2_GPIO17_EDGE_LOW -#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_LOW_BITS _u(0x00000040) -#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_LOW_MSB _u(6) -#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_LOW_LSB _u(6) -#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_HIGH -#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_HIGH_BITS _u(0x00000020) -#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_HIGH_MSB _u(5) -#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_HIGH_LSB _u(5) -#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_LOW -#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_LOW_BITS _u(0x00000010) -#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_LOW_MSB _u(4) -#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_LOW_LSB _u(4) -#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE2_GPIO16_EDGE_HIGH -#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_HIGH_BITS _u(0x00000008) -#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_HIGH_MSB _u(3) -#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_HIGH_LSB _u(3) -#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE2_GPIO16_EDGE_LOW -#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_LOW_BITS _u(0x00000004) -#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_LOW_MSB _u(2) -#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_LOW_LSB _u(2) -#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_HIGH -#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_HIGH_BITS _u(0x00000002) -#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_HIGH_MSB _u(1) -#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_HIGH_LSB _u(1) -#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_LOW -#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_LOW_BITS _u(0x00000001) -#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_LOW_MSB _u(0) -#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_LOW_LSB _u(0) -#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_LOW_ACCESS "RW" -// ============================================================================= -// Register : IO_BANK0_PROC0_INTE3 -// Description : Interrupt Enable for proc0 -#define IO_BANK0_PROC0_INTE3_OFFSET _u(0x00000254) -#define IO_BANK0_PROC0_INTE3_BITS _u(0xffffffff) -#define IO_BANK0_PROC0_INTE3_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE3_GPIO31_EDGE_HIGH -#define IO_BANK0_PROC0_INTE3_GPIO31_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE3_GPIO31_EDGE_HIGH_BITS _u(0x80000000) -#define IO_BANK0_PROC0_INTE3_GPIO31_EDGE_HIGH_MSB _u(31) -#define IO_BANK0_PROC0_INTE3_GPIO31_EDGE_HIGH_LSB _u(31) -#define IO_BANK0_PROC0_INTE3_GPIO31_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE3_GPIO31_EDGE_LOW -#define IO_BANK0_PROC0_INTE3_GPIO31_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE3_GPIO31_EDGE_LOW_BITS _u(0x40000000) -#define IO_BANK0_PROC0_INTE3_GPIO31_EDGE_LOW_MSB _u(30) -#define IO_BANK0_PROC0_INTE3_GPIO31_EDGE_LOW_LSB _u(30) -#define IO_BANK0_PROC0_INTE3_GPIO31_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE3_GPIO31_LEVEL_HIGH -#define IO_BANK0_PROC0_INTE3_GPIO31_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE3_GPIO31_LEVEL_HIGH_BITS _u(0x20000000) -#define IO_BANK0_PROC0_INTE3_GPIO31_LEVEL_HIGH_MSB _u(29) -#define IO_BANK0_PROC0_INTE3_GPIO31_LEVEL_HIGH_LSB _u(29) -#define IO_BANK0_PROC0_INTE3_GPIO31_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE3_GPIO31_LEVEL_LOW -#define IO_BANK0_PROC0_INTE3_GPIO31_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE3_GPIO31_LEVEL_LOW_BITS _u(0x10000000) -#define IO_BANK0_PROC0_INTE3_GPIO31_LEVEL_LOW_MSB _u(28) -#define IO_BANK0_PROC0_INTE3_GPIO31_LEVEL_LOW_LSB _u(28) -#define IO_BANK0_PROC0_INTE3_GPIO31_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE3_GPIO30_EDGE_HIGH -#define IO_BANK0_PROC0_INTE3_GPIO30_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE3_GPIO30_EDGE_HIGH_BITS _u(0x08000000) -#define IO_BANK0_PROC0_INTE3_GPIO30_EDGE_HIGH_MSB _u(27) -#define IO_BANK0_PROC0_INTE3_GPIO30_EDGE_HIGH_LSB _u(27) -#define IO_BANK0_PROC0_INTE3_GPIO30_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE3_GPIO30_EDGE_LOW -#define IO_BANK0_PROC0_INTE3_GPIO30_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE3_GPIO30_EDGE_LOW_BITS _u(0x04000000) -#define IO_BANK0_PROC0_INTE3_GPIO30_EDGE_LOW_MSB _u(26) -#define IO_BANK0_PROC0_INTE3_GPIO30_EDGE_LOW_LSB _u(26) -#define IO_BANK0_PROC0_INTE3_GPIO30_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE3_GPIO30_LEVEL_HIGH -#define IO_BANK0_PROC0_INTE3_GPIO30_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE3_GPIO30_LEVEL_HIGH_BITS _u(0x02000000) -#define IO_BANK0_PROC0_INTE3_GPIO30_LEVEL_HIGH_MSB _u(25) -#define IO_BANK0_PROC0_INTE3_GPIO30_LEVEL_HIGH_LSB _u(25) -#define IO_BANK0_PROC0_INTE3_GPIO30_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE3_GPIO30_LEVEL_LOW -#define IO_BANK0_PROC0_INTE3_GPIO30_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE3_GPIO30_LEVEL_LOW_BITS _u(0x01000000) -#define IO_BANK0_PROC0_INTE3_GPIO30_LEVEL_LOW_MSB _u(24) -#define IO_BANK0_PROC0_INTE3_GPIO30_LEVEL_LOW_LSB _u(24) -#define IO_BANK0_PROC0_INTE3_GPIO30_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE3_GPIO29_EDGE_HIGH -#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_HIGH_BITS _u(0x00800000) -#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_HIGH_MSB _u(23) -#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_HIGH_LSB _u(23) -#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE3_GPIO29_EDGE_LOW -#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_LOW_BITS _u(0x00400000) -#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_LOW_MSB _u(22) -#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_LOW_LSB _u(22) -#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_HIGH -#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_HIGH_BITS _u(0x00200000) -#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_HIGH_MSB _u(21) -#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_HIGH_LSB _u(21) -#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_LOW -#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_LOW_BITS _u(0x00100000) -#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_LOW_MSB _u(20) -#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_LOW_LSB _u(20) -#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE3_GPIO28_EDGE_HIGH -#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_HIGH_BITS _u(0x00080000) -#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_HIGH_MSB _u(19) -#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_HIGH_LSB _u(19) -#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE3_GPIO28_EDGE_LOW -#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_LOW_BITS _u(0x00040000) -#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_LOW_MSB _u(18) -#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_LOW_LSB _u(18) -#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_HIGH -#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_HIGH_BITS _u(0x00020000) -#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_HIGH_MSB _u(17) -#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_HIGH_LSB _u(17) -#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_LOW -#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_LOW_BITS _u(0x00010000) -#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_LOW_MSB _u(16) -#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_LOW_LSB _u(16) -#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE3_GPIO27_EDGE_HIGH -#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_HIGH_BITS _u(0x00008000) -#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_HIGH_MSB _u(15) -#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_HIGH_LSB _u(15) -#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE3_GPIO27_EDGE_LOW -#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_LOW_BITS _u(0x00004000) -#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_LOW_MSB _u(14) -#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_LOW_LSB _u(14) -#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_HIGH -#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_HIGH_BITS _u(0x00002000) -#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_HIGH_MSB _u(13) -#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_HIGH_LSB _u(13) -#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_LOW -#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_LOW_BITS _u(0x00001000) -#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_LOW_MSB _u(12) -#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_LOW_LSB _u(12) -#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE3_GPIO26_EDGE_HIGH -#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_HIGH_BITS _u(0x00000800) -#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_HIGH_MSB _u(11) -#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_HIGH_LSB _u(11) -#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE3_GPIO26_EDGE_LOW -#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_LOW_BITS _u(0x00000400) -#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_LOW_MSB _u(10) -#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_LOW_LSB _u(10) -#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_HIGH -#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_HIGH_BITS _u(0x00000200) -#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_HIGH_MSB _u(9) -#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_HIGH_LSB _u(9) -#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_LOW -#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_LOW_BITS _u(0x00000100) -#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_LOW_MSB _u(8) -#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_LOW_LSB _u(8) -#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE3_GPIO25_EDGE_HIGH -#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_HIGH_BITS _u(0x00000080) -#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_HIGH_MSB _u(7) -#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_HIGH_LSB _u(7) -#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE3_GPIO25_EDGE_LOW -#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_LOW_BITS _u(0x00000040) -#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_LOW_MSB _u(6) -#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_LOW_LSB _u(6) -#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_HIGH -#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_HIGH_BITS _u(0x00000020) -#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_HIGH_MSB _u(5) -#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_HIGH_LSB _u(5) -#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_LOW -#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_LOW_BITS _u(0x00000010) -#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_LOW_MSB _u(4) -#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_LOW_LSB _u(4) -#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE3_GPIO24_EDGE_HIGH -#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_HIGH_BITS _u(0x00000008) -#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_HIGH_MSB _u(3) -#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_HIGH_LSB _u(3) -#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE3_GPIO24_EDGE_LOW -#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_LOW_BITS _u(0x00000004) -#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_LOW_MSB _u(2) -#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_LOW_LSB _u(2) -#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_HIGH -#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_HIGH_BITS _u(0x00000002) -#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_HIGH_MSB _u(1) -#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_HIGH_LSB _u(1) -#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_LOW -#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_LOW_BITS _u(0x00000001) -#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_LOW_MSB _u(0) -#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_LOW_LSB _u(0) -#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_LOW_ACCESS "RW" -// ============================================================================= -// Register : IO_BANK0_PROC0_INTE4 -// Description : Interrupt Enable for proc0 -#define IO_BANK0_PROC0_INTE4_OFFSET _u(0x00000258) -#define IO_BANK0_PROC0_INTE4_BITS _u(0xffffffff) -#define IO_BANK0_PROC0_INTE4_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE4_GPIO39_EDGE_HIGH -#define IO_BANK0_PROC0_INTE4_GPIO39_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE4_GPIO39_EDGE_HIGH_BITS _u(0x80000000) -#define IO_BANK0_PROC0_INTE4_GPIO39_EDGE_HIGH_MSB _u(31) -#define IO_BANK0_PROC0_INTE4_GPIO39_EDGE_HIGH_LSB _u(31) -#define IO_BANK0_PROC0_INTE4_GPIO39_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE4_GPIO39_EDGE_LOW -#define IO_BANK0_PROC0_INTE4_GPIO39_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE4_GPIO39_EDGE_LOW_BITS _u(0x40000000) -#define IO_BANK0_PROC0_INTE4_GPIO39_EDGE_LOW_MSB _u(30) -#define IO_BANK0_PROC0_INTE4_GPIO39_EDGE_LOW_LSB _u(30) -#define IO_BANK0_PROC0_INTE4_GPIO39_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE4_GPIO39_LEVEL_HIGH -#define IO_BANK0_PROC0_INTE4_GPIO39_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE4_GPIO39_LEVEL_HIGH_BITS _u(0x20000000) -#define IO_BANK0_PROC0_INTE4_GPIO39_LEVEL_HIGH_MSB _u(29) -#define IO_BANK0_PROC0_INTE4_GPIO39_LEVEL_HIGH_LSB _u(29) -#define IO_BANK0_PROC0_INTE4_GPIO39_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE4_GPIO39_LEVEL_LOW -#define IO_BANK0_PROC0_INTE4_GPIO39_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE4_GPIO39_LEVEL_LOW_BITS _u(0x10000000) -#define IO_BANK0_PROC0_INTE4_GPIO39_LEVEL_LOW_MSB _u(28) -#define IO_BANK0_PROC0_INTE4_GPIO39_LEVEL_LOW_LSB _u(28) -#define IO_BANK0_PROC0_INTE4_GPIO39_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE4_GPIO38_EDGE_HIGH -#define IO_BANK0_PROC0_INTE4_GPIO38_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE4_GPIO38_EDGE_HIGH_BITS _u(0x08000000) -#define IO_BANK0_PROC0_INTE4_GPIO38_EDGE_HIGH_MSB _u(27) -#define IO_BANK0_PROC0_INTE4_GPIO38_EDGE_HIGH_LSB _u(27) -#define IO_BANK0_PROC0_INTE4_GPIO38_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE4_GPIO38_EDGE_LOW -#define IO_BANK0_PROC0_INTE4_GPIO38_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE4_GPIO38_EDGE_LOW_BITS _u(0x04000000) -#define IO_BANK0_PROC0_INTE4_GPIO38_EDGE_LOW_MSB _u(26) -#define IO_BANK0_PROC0_INTE4_GPIO38_EDGE_LOW_LSB _u(26) -#define IO_BANK0_PROC0_INTE4_GPIO38_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE4_GPIO38_LEVEL_HIGH -#define IO_BANK0_PROC0_INTE4_GPIO38_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE4_GPIO38_LEVEL_HIGH_BITS _u(0x02000000) -#define IO_BANK0_PROC0_INTE4_GPIO38_LEVEL_HIGH_MSB _u(25) -#define IO_BANK0_PROC0_INTE4_GPIO38_LEVEL_HIGH_LSB _u(25) -#define IO_BANK0_PROC0_INTE4_GPIO38_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE4_GPIO38_LEVEL_LOW -#define IO_BANK0_PROC0_INTE4_GPIO38_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE4_GPIO38_LEVEL_LOW_BITS _u(0x01000000) -#define IO_BANK0_PROC0_INTE4_GPIO38_LEVEL_LOW_MSB _u(24) -#define IO_BANK0_PROC0_INTE4_GPIO38_LEVEL_LOW_LSB _u(24) -#define IO_BANK0_PROC0_INTE4_GPIO38_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE4_GPIO37_EDGE_HIGH -#define IO_BANK0_PROC0_INTE4_GPIO37_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE4_GPIO37_EDGE_HIGH_BITS _u(0x00800000) -#define IO_BANK0_PROC0_INTE4_GPIO37_EDGE_HIGH_MSB _u(23) -#define IO_BANK0_PROC0_INTE4_GPIO37_EDGE_HIGH_LSB _u(23) -#define IO_BANK0_PROC0_INTE4_GPIO37_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE4_GPIO37_EDGE_LOW -#define IO_BANK0_PROC0_INTE4_GPIO37_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE4_GPIO37_EDGE_LOW_BITS _u(0x00400000) -#define IO_BANK0_PROC0_INTE4_GPIO37_EDGE_LOW_MSB _u(22) -#define IO_BANK0_PROC0_INTE4_GPIO37_EDGE_LOW_LSB _u(22) -#define IO_BANK0_PROC0_INTE4_GPIO37_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE4_GPIO37_LEVEL_HIGH -#define IO_BANK0_PROC0_INTE4_GPIO37_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE4_GPIO37_LEVEL_HIGH_BITS _u(0x00200000) -#define IO_BANK0_PROC0_INTE4_GPIO37_LEVEL_HIGH_MSB _u(21) -#define IO_BANK0_PROC0_INTE4_GPIO37_LEVEL_HIGH_LSB _u(21) -#define IO_BANK0_PROC0_INTE4_GPIO37_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE4_GPIO37_LEVEL_LOW -#define IO_BANK0_PROC0_INTE4_GPIO37_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE4_GPIO37_LEVEL_LOW_BITS _u(0x00100000) -#define IO_BANK0_PROC0_INTE4_GPIO37_LEVEL_LOW_MSB _u(20) -#define IO_BANK0_PROC0_INTE4_GPIO37_LEVEL_LOW_LSB _u(20) -#define IO_BANK0_PROC0_INTE4_GPIO37_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE4_GPIO36_EDGE_HIGH -#define IO_BANK0_PROC0_INTE4_GPIO36_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE4_GPIO36_EDGE_HIGH_BITS _u(0x00080000) -#define IO_BANK0_PROC0_INTE4_GPIO36_EDGE_HIGH_MSB _u(19) -#define IO_BANK0_PROC0_INTE4_GPIO36_EDGE_HIGH_LSB _u(19) -#define IO_BANK0_PROC0_INTE4_GPIO36_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE4_GPIO36_EDGE_LOW -#define IO_BANK0_PROC0_INTE4_GPIO36_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE4_GPIO36_EDGE_LOW_BITS _u(0x00040000) -#define IO_BANK0_PROC0_INTE4_GPIO36_EDGE_LOW_MSB _u(18) -#define IO_BANK0_PROC0_INTE4_GPIO36_EDGE_LOW_LSB _u(18) -#define IO_BANK0_PROC0_INTE4_GPIO36_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE4_GPIO36_LEVEL_HIGH -#define IO_BANK0_PROC0_INTE4_GPIO36_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE4_GPIO36_LEVEL_HIGH_BITS _u(0x00020000) -#define IO_BANK0_PROC0_INTE4_GPIO36_LEVEL_HIGH_MSB _u(17) -#define IO_BANK0_PROC0_INTE4_GPIO36_LEVEL_HIGH_LSB _u(17) -#define IO_BANK0_PROC0_INTE4_GPIO36_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE4_GPIO36_LEVEL_LOW -#define IO_BANK0_PROC0_INTE4_GPIO36_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE4_GPIO36_LEVEL_LOW_BITS _u(0x00010000) -#define IO_BANK0_PROC0_INTE4_GPIO36_LEVEL_LOW_MSB _u(16) -#define IO_BANK0_PROC0_INTE4_GPIO36_LEVEL_LOW_LSB _u(16) -#define IO_BANK0_PROC0_INTE4_GPIO36_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE4_GPIO35_EDGE_HIGH -#define IO_BANK0_PROC0_INTE4_GPIO35_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE4_GPIO35_EDGE_HIGH_BITS _u(0x00008000) -#define IO_BANK0_PROC0_INTE4_GPIO35_EDGE_HIGH_MSB _u(15) -#define IO_BANK0_PROC0_INTE4_GPIO35_EDGE_HIGH_LSB _u(15) -#define IO_BANK0_PROC0_INTE4_GPIO35_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE4_GPIO35_EDGE_LOW -#define IO_BANK0_PROC0_INTE4_GPIO35_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE4_GPIO35_EDGE_LOW_BITS _u(0x00004000) -#define IO_BANK0_PROC0_INTE4_GPIO35_EDGE_LOW_MSB _u(14) -#define IO_BANK0_PROC0_INTE4_GPIO35_EDGE_LOW_LSB _u(14) -#define IO_BANK0_PROC0_INTE4_GPIO35_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE4_GPIO35_LEVEL_HIGH -#define IO_BANK0_PROC0_INTE4_GPIO35_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE4_GPIO35_LEVEL_HIGH_BITS _u(0x00002000) -#define IO_BANK0_PROC0_INTE4_GPIO35_LEVEL_HIGH_MSB _u(13) -#define IO_BANK0_PROC0_INTE4_GPIO35_LEVEL_HIGH_LSB _u(13) -#define IO_BANK0_PROC0_INTE4_GPIO35_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE4_GPIO35_LEVEL_LOW -#define IO_BANK0_PROC0_INTE4_GPIO35_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE4_GPIO35_LEVEL_LOW_BITS _u(0x00001000) -#define IO_BANK0_PROC0_INTE4_GPIO35_LEVEL_LOW_MSB _u(12) -#define IO_BANK0_PROC0_INTE4_GPIO35_LEVEL_LOW_LSB _u(12) -#define IO_BANK0_PROC0_INTE4_GPIO35_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE4_GPIO34_EDGE_HIGH -#define IO_BANK0_PROC0_INTE4_GPIO34_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE4_GPIO34_EDGE_HIGH_BITS _u(0x00000800) -#define IO_BANK0_PROC0_INTE4_GPIO34_EDGE_HIGH_MSB _u(11) -#define IO_BANK0_PROC0_INTE4_GPIO34_EDGE_HIGH_LSB _u(11) -#define IO_BANK0_PROC0_INTE4_GPIO34_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE4_GPIO34_EDGE_LOW -#define IO_BANK0_PROC0_INTE4_GPIO34_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE4_GPIO34_EDGE_LOW_BITS _u(0x00000400) -#define IO_BANK0_PROC0_INTE4_GPIO34_EDGE_LOW_MSB _u(10) -#define IO_BANK0_PROC0_INTE4_GPIO34_EDGE_LOW_LSB _u(10) -#define IO_BANK0_PROC0_INTE4_GPIO34_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE4_GPIO34_LEVEL_HIGH -#define IO_BANK0_PROC0_INTE4_GPIO34_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE4_GPIO34_LEVEL_HIGH_BITS _u(0x00000200) -#define IO_BANK0_PROC0_INTE4_GPIO34_LEVEL_HIGH_MSB _u(9) -#define IO_BANK0_PROC0_INTE4_GPIO34_LEVEL_HIGH_LSB _u(9) -#define IO_BANK0_PROC0_INTE4_GPIO34_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE4_GPIO34_LEVEL_LOW -#define IO_BANK0_PROC0_INTE4_GPIO34_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE4_GPIO34_LEVEL_LOW_BITS _u(0x00000100) -#define IO_BANK0_PROC0_INTE4_GPIO34_LEVEL_LOW_MSB _u(8) -#define IO_BANK0_PROC0_INTE4_GPIO34_LEVEL_LOW_LSB _u(8) -#define IO_BANK0_PROC0_INTE4_GPIO34_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE4_GPIO33_EDGE_HIGH -#define IO_BANK0_PROC0_INTE4_GPIO33_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE4_GPIO33_EDGE_HIGH_BITS _u(0x00000080) -#define IO_BANK0_PROC0_INTE4_GPIO33_EDGE_HIGH_MSB _u(7) -#define IO_BANK0_PROC0_INTE4_GPIO33_EDGE_HIGH_LSB _u(7) -#define IO_BANK0_PROC0_INTE4_GPIO33_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE4_GPIO33_EDGE_LOW -#define IO_BANK0_PROC0_INTE4_GPIO33_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE4_GPIO33_EDGE_LOW_BITS _u(0x00000040) -#define IO_BANK0_PROC0_INTE4_GPIO33_EDGE_LOW_MSB _u(6) -#define IO_BANK0_PROC0_INTE4_GPIO33_EDGE_LOW_LSB _u(6) -#define IO_BANK0_PROC0_INTE4_GPIO33_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE4_GPIO33_LEVEL_HIGH -#define IO_BANK0_PROC0_INTE4_GPIO33_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE4_GPIO33_LEVEL_HIGH_BITS _u(0x00000020) -#define IO_BANK0_PROC0_INTE4_GPIO33_LEVEL_HIGH_MSB _u(5) -#define IO_BANK0_PROC0_INTE4_GPIO33_LEVEL_HIGH_LSB _u(5) -#define IO_BANK0_PROC0_INTE4_GPIO33_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE4_GPIO33_LEVEL_LOW -#define IO_BANK0_PROC0_INTE4_GPIO33_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE4_GPIO33_LEVEL_LOW_BITS _u(0x00000010) -#define IO_BANK0_PROC0_INTE4_GPIO33_LEVEL_LOW_MSB _u(4) -#define IO_BANK0_PROC0_INTE4_GPIO33_LEVEL_LOW_LSB _u(4) -#define IO_BANK0_PROC0_INTE4_GPIO33_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE4_GPIO32_EDGE_HIGH -#define IO_BANK0_PROC0_INTE4_GPIO32_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE4_GPIO32_EDGE_HIGH_BITS _u(0x00000008) -#define IO_BANK0_PROC0_INTE4_GPIO32_EDGE_HIGH_MSB _u(3) -#define IO_BANK0_PROC0_INTE4_GPIO32_EDGE_HIGH_LSB _u(3) -#define IO_BANK0_PROC0_INTE4_GPIO32_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE4_GPIO32_EDGE_LOW -#define IO_BANK0_PROC0_INTE4_GPIO32_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE4_GPIO32_EDGE_LOW_BITS _u(0x00000004) -#define IO_BANK0_PROC0_INTE4_GPIO32_EDGE_LOW_MSB _u(2) -#define IO_BANK0_PROC0_INTE4_GPIO32_EDGE_LOW_LSB _u(2) -#define IO_BANK0_PROC0_INTE4_GPIO32_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE4_GPIO32_LEVEL_HIGH -#define IO_BANK0_PROC0_INTE4_GPIO32_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE4_GPIO32_LEVEL_HIGH_BITS _u(0x00000002) -#define IO_BANK0_PROC0_INTE4_GPIO32_LEVEL_HIGH_MSB _u(1) -#define IO_BANK0_PROC0_INTE4_GPIO32_LEVEL_HIGH_LSB _u(1) -#define IO_BANK0_PROC0_INTE4_GPIO32_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE4_GPIO32_LEVEL_LOW -#define IO_BANK0_PROC0_INTE4_GPIO32_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE4_GPIO32_LEVEL_LOW_BITS _u(0x00000001) -#define IO_BANK0_PROC0_INTE4_GPIO32_LEVEL_LOW_MSB _u(0) -#define IO_BANK0_PROC0_INTE4_GPIO32_LEVEL_LOW_LSB _u(0) -#define IO_BANK0_PROC0_INTE4_GPIO32_LEVEL_LOW_ACCESS "RW" -// ============================================================================= -// Register : IO_BANK0_PROC0_INTE5 -// Description : Interrupt Enable for proc0 -#define IO_BANK0_PROC0_INTE5_OFFSET _u(0x0000025c) -#define IO_BANK0_PROC0_INTE5_BITS _u(0xffffffff) -#define IO_BANK0_PROC0_INTE5_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE5_GPIO47_EDGE_HIGH -#define IO_BANK0_PROC0_INTE5_GPIO47_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE5_GPIO47_EDGE_HIGH_BITS _u(0x80000000) -#define IO_BANK0_PROC0_INTE5_GPIO47_EDGE_HIGH_MSB _u(31) -#define IO_BANK0_PROC0_INTE5_GPIO47_EDGE_HIGH_LSB _u(31) -#define IO_BANK0_PROC0_INTE5_GPIO47_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE5_GPIO47_EDGE_LOW -#define IO_BANK0_PROC0_INTE5_GPIO47_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE5_GPIO47_EDGE_LOW_BITS _u(0x40000000) -#define IO_BANK0_PROC0_INTE5_GPIO47_EDGE_LOW_MSB _u(30) -#define IO_BANK0_PROC0_INTE5_GPIO47_EDGE_LOW_LSB _u(30) -#define IO_BANK0_PROC0_INTE5_GPIO47_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE5_GPIO47_LEVEL_HIGH -#define IO_BANK0_PROC0_INTE5_GPIO47_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE5_GPIO47_LEVEL_HIGH_BITS _u(0x20000000) -#define IO_BANK0_PROC0_INTE5_GPIO47_LEVEL_HIGH_MSB _u(29) -#define IO_BANK0_PROC0_INTE5_GPIO47_LEVEL_HIGH_LSB _u(29) -#define IO_BANK0_PROC0_INTE5_GPIO47_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE5_GPIO47_LEVEL_LOW -#define IO_BANK0_PROC0_INTE5_GPIO47_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE5_GPIO47_LEVEL_LOW_BITS _u(0x10000000) -#define IO_BANK0_PROC0_INTE5_GPIO47_LEVEL_LOW_MSB _u(28) -#define IO_BANK0_PROC0_INTE5_GPIO47_LEVEL_LOW_LSB _u(28) -#define IO_BANK0_PROC0_INTE5_GPIO47_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE5_GPIO46_EDGE_HIGH -#define IO_BANK0_PROC0_INTE5_GPIO46_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE5_GPIO46_EDGE_HIGH_BITS _u(0x08000000) -#define IO_BANK0_PROC0_INTE5_GPIO46_EDGE_HIGH_MSB _u(27) -#define IO_BANK0_PROC0_INTE5_GPIO46_EDGE_HIGH_LSB _u(27) -#define IO_BANK0_PROC0_INTE5_GPIO46_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE5_GPIO46_EDGE_LOW -#define IO_BANK0_PROC0_INTE5_GPIO46_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE5_GPIO46_EDGE_LOW_BITS _u(0x04000000) -#define IO_BANK0_PROC0_INTE5_GPIO46_EDGE_LOW_MSB _u(26) -#define IO_BANK0_PROC0_INTE5_GPIO46_EDGE_LOW_LSB _u(26) -#define IO_BANK0_PROC0_INTE5_GPIO46_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE5_GPIO46_LEVEL_HIGH -#define IO_BANK0_PROC0_INTE5_GPIO46_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE5_GPIO46_LEVEL_HIGH_BITS _u(0x02000000) -#define IO_BANK0_PROC0_INTE5_GPIO46_LEVEL_HIGH_MSB _u(25) -#define IO_BANK0_PROC0_INTE5_GPIO46_LEVEL_HIGH_LSB _u(25) -#define IO_BANK0_PROC0_INTE5_GPIO46_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE5_GPIO46_LEVEL_LOW -#define IO_BANK0_PROC0_INTE5_GPIO46_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE5_GPIO46_LEVEL_LOW_BITS _u(0x01000000) -#define IO_BANK0_PROC0_INTE5_GPIO46_LEVEL_LOW_MSB _u(24) -#define IO_BANK0_PROC0_INTE5_GPIO46_LEVEL_LOW_LSB _u(24) -#define IO_BANK0_PROC0_INTE5_GPIO46_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE5_GPIO45_EDGE_HIGH -#define IO_BANK0_PROC0_INTE5_GPIO45_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE5_GPIO45_EDGE_HIGH_BITS _u(0x00800000) -#define IO_BANK0_PROC0_INTE5_GPIO45_EDGE_HIGH_MSB _u(23) -#define IO_BANK0_PROC0_INTE5_GPIO45_EDGE_HIGH_LSB _u(23) -#define IO_BANK0_PROC0_INTE5_GPIO45_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE5_GPIO45_EDGE_LOW -#define IO_BANK0_PROC0_INTE5_GPIO45_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE5_GPIO45_EDGE_LOW_BITS _u(0x00400000) -#define IO_BANK0_PROC0_INTE5_GPIO45_EDGE_LOW_MSB _u(22) -#define IO_BANK0_PROC0_INTE5_GPIO45_EDGE_LOW_LSB _u(22) -#define IO_BANK0_PROC0_INTE5_GPIO45_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE5_GPIO45_LEVEL_HIGH -#define IO_BANK0_PROC0_INTE5_GPIO45_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE5_GPIO45_LEVEL_HIGH_BITS _u(0x00200000) -#define IO_BANK0_PROC0_INTE5_GPIO45_LEVEL_HIGH_MSB _u(21) -#define IO_BANK0_PROC0_INTE5_GPIO45_LEVEL_HIGH_LSB _u(21) -#define IO_BANK0_PROC0_INTE5_GPIO45_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE5_GPIO45_LEVEL_LOW -#define IO_BANK0_PROC0_INTE5_GPIO45_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE5_GPIO45_LEVEL_LOW_BITS _u(0x00100000) -#define IO_BANK0_PROC0_INTE5_GPIO45_LEVEL_LOW_MSB _u(20) -#define IO_BANK0_PROC0_INTE5_GPIO45_LEVEL_LOW_LSB _u(20) -#define IO_BANK0_PROC0_INTE5_GPIO45_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE5_GPIO44_EDGE_HIGH -#define IO_BANK0_PROC0_INTE5_GPIO44_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE5_GPIO44_EDGE_HIGH_BITS _u(0x00080000) -#define IO_BANK0_PROC0_INTE5_GPIO44_EDGE_HIGH_MSB _u(19) -#define IO_BANK0_PROC0_INTE5_GPIO44_EDGE_HIGH_LSB _u(19) -#define IO_BANK0_PROC0_INTE5_GPIO44_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE5_GPIO44_EDGE_LOW -#define IO_BANK0_PROC0_INTE5_GPIO44_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE5_GPIO44_EDGE_LOW_BITS _u(0x00040000) -#define IO_BANK0_PROC0_INTE5_GPIO44_EDGE_LOW_MSB _u(18) -#define IO_BANK0_PROC0_INTE5_GPIO44_EDGE_LOW_LSB _u(18) -#define IO_BANK0_PROC0_INTE5_GPIO44_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE5_GPIO44_LEVEL_HIGH -#define IO_BANK0_PROC0_INTE5_GPIO44_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE5_GPIO44_LEVEL_HIGH_BITS _u(0x00020000) -#define IO_BANK0_PROC0_INTE5_GPIO44_LEVEL_HIGH_MSB _u(17) -#define IO_BANK0_PROC0_INTE5_GPIO44_LEVEL_HIGH_LSB _u(17) -#define IO_BANK0_PROC0_INTE5_GPIO44_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE5_GPIO44_LEVEL_LOW -#define IO_BANK0_PROC0_INTE5_GPIO44_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE5_GPIO44_LEVEL_LOW_BITS _u(0x00010000) -#define IO_BANK0_PROC0_INTE5_GPIO44_LEVEL_LOW_MSB _u(16) -#define IO_BANK0_PROC0_INTE5_GPIO44_LEVEL_LOW_LSB _u(16) -#define IO_BANK0_PROC0_INTE5_GPIO44_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE5_GPIO43_EDGE_HIGH -#define IO_BANK0_PROC0_INTE5_GPIO43_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE5_GPIO43_EDGE_HIGH_BITS _u(0x00008000) -#define IO_BANK0_PROC0_INTE5_GPIO43_EDGE_HIGH_MSB _u(15) -#define IO_BANK0_PROC0_INTE5_GPIO43_EDGE_HIGH_LSB _u(15) -#define IO_BANK0_PROC0_INTE5_GPIO43_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE5_GPIO43_EDGE_LOW -#define IO_BANK0_PROC0_INTE5_GPIO43_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE5_GPIO43_EDGE_LOW_BITS _u(0x00004000) -#define IO_BANK0_PROC0_INTE5_GPIO43_EDGE_LOW_MSB _u(14) -#define IO_BANK0_PROC0_INTE5_GPIO43_EDGE_LOW_LSB _u(14) -#define IO_BANK0_PROC0_INTE5_GPIO43_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE5_GPIO43_LEVEL_HIGH -#define IO_BANK0_PROC0_INTE5_GPIO43_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE5_GPIO43_LEVEL_HIGH_BITS _u(0x00002000) -#define IO_BANK0_PROC0_INTE5_GPIO43_LEVEL_HIGH_MSB _u(13) -#define IO_BANK0_PROC0_INTE5_GPIO43_LEVEL_HIGH_LSB _u(13) -#define IO_BANK0_PROC0_INTE5_GPIO43_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE5_GPIO43_LEVEL_LOW -#define IO_BANK0_PROC0_INTE5_GPIO43_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE5_GPIO43_LEVEL_LOW_BITS _u(0x00001000) -#define IO_BANK0_PROC0_INTE5_GPIO43_LEVEL_LOW_MSB _u(12) -#define IO_BANK0_PROC0_INTE5_GPIO43_LEVEL_LOW_LSB _u(12) -#define IO_BANK0_PROC0_INTE5_GPIO43_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE5_GPIO42_EDGE_HIGH -#define IO_BANK0_PROC0_INTE5_GPIO42_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE5_GPIO42_EDGE_HIGH_BITS _u(0x00000800) -#define IO_BANK0_PROC0_INTE5_GPIO42_EDGE_HIGH_MSB _u(11) -#define IO_BANK0_PROC0_INTE5_GPIO42_EDGE_HIGH_LSB _u(11) -#define IO_BANK0_PROC0_INTE5_GPIO42_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE5_GPIO42_EDGE_LOW -#define IO_BANK0_PROC0_INTE5_GPIO42_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE5_GPIO42_EDGE_LOW_BITS _u(0x00000400) -#define IO_BANK0_PROC0_INTE5_GPIO42_EDGE_LOW_MSB _u(10) -#define IO_BANK0_PROC0_INTE5_GPIO42_EDGE_LOW_LSB _u(10) -#define IO_BANK0_PROC0_INTE5_GPIO42_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE5_GPIO42_LEVEL_HIGH -#define IO_BANK0_PROC0_INTE5_GPIO42_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE5_GPIO42_LEVEL_HIGH_BITS _u(0x00000200) -#define IO_BANK0_PROC0_INTE5_GPIO42_LEVEL_HIGH_MSB _u(9) -#define IO_BANK0_PROC0_INTE5_GPIO42_LEVEL_HIGH_LSB _u(9) -#define IO_BANK0_PROC0_INTE5_GPIO42_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE5_GPIO42_LEVEL_LOW -#define IO_BANK0_PROC0_INTE5_GPIO42_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE5_GPIO42_LEVEL_LOW_BITS _u(0x00000100) -#define IO_BANK0_PROC0_INTE5_GPIO42_LEVEL_LOW_MSB _u(8) -#define IO_BANK0_PROC0_INTE5_GPIO42_LEVEL_LOW_LSB _u(8) -#define IO_BANK0_PROC0_INTE5_GPIO42_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE5_GPIO41_EDGE_HIGH -#define IO_BANK0_PROC0_INTE5_GPIO41_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE5_GPIO41_EDGE_HIGH_BITS _u(0x00000080) -#define IO_BANK0_PROC0_INTE5_GPIO41_EDGE_HIGH_MSB _u(7) -#define IO_BANK0_PROC0_INTE5_GPIO41_EDGE_HIGH_LSB _u(7) -#define IO_BANK0_PROC0_INTE5_GPIO41_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE5_GPIO41_EDGE_LOW -#define IO_BANK0_PROC0_INTE5_GPIO41_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE5_GPIO41_EDGE_LOW_BITS _u(0x00000040) -#define IO_BANK0_PROC0_INTE5_GPIO41_EDGE_LOW_MSB _u(6) -#define IO_BANK0_PROC0_INTE5_GPIO41_EDGE_LOW_LSB _u(6) -#define IO_BANK0_PROC0_INTE5_GPIO41_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE5_GPIO41_LEVEL_HIGH -#define IO_BANK0_PROC0_INTE5_GPIO41_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE5_GPIO41_LEVEL_HIGH_BITS _u(0x00000020) -#define IO_BANK0_PROC0_INTE5_GPIO41_LEVEL_HIGH_MSB _u(5) -#define IO_BANK0_PROC0_INTE5_GPIO41_LEVEL_HIGH_LSB _u(5) -#define IO_BANK0_PROC0_INTE5_GPIO41_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE5_GPIO41_LEVEL_LOW -#define IO_BANK0_PROC0_INTE5_GPIO41_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE5_GPIO41_LEVEL_LOW_BITS _u(0x00000010) -#define IO_BANK0_PROC0_INTE5_GPIO41_LEVEL_LOW_MSB _u(4) -#define IO_BANK0_PROC0_INTE5_GPIO41_LEVEL_LOW_LSB _u(4) -#define IO_BANK0_PROC0_INTE5_GPIO41_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE5_GPIO40_EDGE_HIGH -#define IO_BANK0_PROC0_INTE5_GPIO40_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE5_GPIO40_EDGE_HIGH_BITS _u(0x00000008) -#define IO_BANK0_PROC0_INTE5_GPIO40_EDGE_HIGH_MSB _u(3) -#define IO_BANK0_PROC0_INTE5_GPIO40_EDGE_HIGH_LSB _u(3) -#define IO_BANK0_PROC0_INTE5_GPIO40_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE5_GPIO40_EDGE_LOW -#define IO_BANK0_PROC0_INTE5_GPIO40_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE5_GPIO40_EDGE_LOW_BITS _u(0x00000004) -#define IO_BANK0_PROC0_INTE5_GPIO40_EDGE_LOW_MSB _u(2) -#define IO_BANK0_PROC0_INTE5_GPIO40_EDGE_LOW_LSB _u(2) -#define IO_BANK0_PROC0_INTE5_GPIO40_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE5_GPIO40_LEVEL_HIGH -#define IO_BANK0_PROC0_INTE5_GPIO40_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE5_GPIO40_LEVEL_HIGH_BITS _u(0x00000002) -#define IO_BANK0_PROC0_INTE5_GPIO40_LEVEL_HIGH_MSB _u(1) -#define IO_BANK0_PROC0_INTE5_GPIO40_LEVEL_HIGH_LSB _u(1) -#define IO_BANK0_PROC0_INTE5_GPIO40_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTE5_GPIO40_LEVEL_LOW -#define IO_BANK0_PROC0_INTE5_GPIO40_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTE5_GPIO40_LEVEL_LOW_BITS _u(0x00000001) -#define IO_BANK0_PROC0_INTE5_GPIO40_LEVEL_LOW_MSB _u(0) -#define IO_BANK0_PROC0_INTE5_GPIO40_LEVEL_LOW_LSB _u(0) -#define IO_BANK0_PROC0_INTE5_GPIO40_LEVEL_LOW_ACCESS "RW" -// ============================================================================= -// Register : IO_BANK0_PROC0_INTF0 -// Description : Interrupt Force for proc0 -#define IO_BANK0_PROC0_INTF0_OFFSET _u(0x00000260) -#define IO_BANK0_PROC0_INTF0_BITS _u(0xffffffff) -#define IO_BANK0_PROC0_INTF0_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF0_GPIO7_EDGE_HIGH -#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_HIGH_BITS _u(0x80000000) -#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_HIGH_MSB _u(31) -#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_HIGH_LSB _u(31) -#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF0_GPIO7_EDGE_LOW -#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_LOW_BITS _u(0x40000000) -#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_LOW_MSB _u(30) -#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_LOW_LSB _u(30) -#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_HIGH -#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_HIGH_BITS _u(0x20000000) -#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_HIGH_MSB _u(29) -#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_HIGH_LSB _u(29) -#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_LOW -#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_LOW_BITS _u(0x10000000) -#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_LOW_MSB _u(28) -#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_LOW_LSB _u(28) -#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF0_GPIO6_EDGE_HIGH -#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_HIGH_BITS _u(0x08000000) -#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_HIGH_MSB _u(27) -#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_HIGH_LSB _u(27) -#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF0_GPIO6_EDGE_LOW -#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_LOW_BITS _u(0x04000000) -#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_LOW_MSB _u(26) -#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_LOW_LSB _u(26) -#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_HIGH -#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_HIGH_BITS _u(0x02000000) -#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_HIGH_MSB _u(25) -#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_HIGH_LSB _u(25) -#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_LOW -#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_LOW_BITS _u(0x01000000) -#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_LOW_MSB _u(24) -#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_LOW_LSB _u(24) -#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF0_GPIO5_EDGE_HIGH -#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_HIGH_BITS _u(0x00800000) -#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_HIGH_MSB _u(23) -#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_HIGH_LSB _u(23) -#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF0_GPIO5_EDGE_LOW -#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_LOW_BITS _u(0x00400000) -#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_LOW_MSB _u(22) -#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_LOW_LSB _u(22) -#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_HIGH -#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_HIGH_BITS _u(0x00200000) -#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_HIGH_MSB _u(21) -#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_HIGH_LSB _u(21) -#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_LOW -#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_LOW_BITS _u(0x00100000) -#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_LOW_MSB _u(20) -#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_LOW_LSB _u(20) -#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF0_GPIO4_EDGE_HIGH -#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_HIGH_BITS _u(0x00080000) -#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_HIGH_MSB _u(19) -#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_HIGH_LSB _u(19) -#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF0_GPIO4_EDGE_LOW -#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_LOW_BITS _u(0x00040000) -#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_LOW_MSB _u(18) -#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_LOW_LSB _u(18) -#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_HIGH -#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_HIGH_BITS _u(0x00020000) -#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_HIGH_MSB _u(17) -#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_HIGH_LSB _u(17) -#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_LOW -#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_LOW_BITS _u(0x00010000) -#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_LOW_MSB _u(16) -#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_LOW_LSB _u(16) -#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF0_GPIO3_EDGE_HIGH -#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_HIGH_BITS _u(0x00008000) -#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_HIGH_MSB _u(15) -#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_HIGH_LSB _u(15) -#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF0_GPIO3_EDGE_LOW -#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_LOW_BITS _u(0x00004000) -#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_LOW_MSB _u(14) -#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_LOW_LSB _u(14) -#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_HIGH -#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_HIGH_BITS _u(0x00002000) -#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_HIGH_MSB _u(13) -#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_HIGH_LSB _u(13) -#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_LOW -#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_LOW_BITS _u(0x00001000) -#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_LOW_MSB _u(12) -#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_LOW_LSB _u(12) -#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF0_GPIO2_EDGE_HIGH -#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_HIGH_BITS _u(0x00000800) -#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_HIGH_MSB _u(11) -#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_HIGH_LSB _u(11) -#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF0_GPIO2_EDGE_LOW -#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_LOW_BITS _u(0x00000400) -#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_LOW_MSB _u(10) -#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_LOW_LSB _u(10) -#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_HIGH -#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_HIGH_BITS _u(0x00000200) -#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_HIGH_MSB _u(9) -#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_HIGH_LSB _u(9) -#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_LOW -#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_LOW_BITS _u(0x00000100) -#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_LOW_MSB _u(8) -#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_LOW_LSB _u(8) -#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF0_GPIO1_EDGE_HIGH -#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_HIGH_BITS _u(0x00000080) -#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_HIGH_MSB _u(7) -#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_HIGH_LSB _u(7) -#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF0_GPIO1_EDGE_LOW -#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_LOW_BITS _u(0x00000040) -#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_LOW_MSB _u(6) -#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_LOW_LSB _u(6) -#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_HIGH -#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_HIGH_BITS _u(0x00000020) -#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_HIGH_MSB _u(5) -#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_HIGH_LSB _u(5) -#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_LOW -#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_LOW_BITS _u(0x00000010) -#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_LOW_MSB _u(4) -#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_LOW_LSB _u(4) -#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF0_GPIO0_EDGE_HIGH -#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_HIGH_BITS _u(0x00000008) -#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_HIGH_MSB _u(3) -#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_HIGH_LSB _u(3) -#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF0_GPIO0_EDGE_LOW -#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_LOW_BITS _u(0x00000004) -#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_LOW_MSB _u(2) -#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_LOW_LSB _u(2) -#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_HIGH -#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_HIGH_BITS _u(0x00000002) -#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_HIGH_MSB _u(1) -#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_HIGH_LSB _u(1) -#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_LOW -#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_LOW_BITS _u(0x00000001) -#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_LOW_MSB _u(0) -#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_LOW_LSB _u(0) -#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_LOW_ACCESS "RW" -// ============================================================================= -// Register : IO_BANK0_PROC0_INTF1 -// Description : Interrupt Force for proc0 -#define IO_BANK0_PROC0_INTF1_OFFSET _u(0x00000264) -#define IO_BANK0_PROC0_INTF1_BITS _u(0xffffffff) -#define IO_BANK0_PROC0_INTF1_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF1_GPIO15_EDGE_HIGH -#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_HIGH_BITS _u(0x80000000) -#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_HIGH_MSB _u(31) -#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_HIGH_LSB _u(31) -#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF1_GPIO15_EDGE_LOW -#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_LOW_BITS _u(0x40000000) -#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_LOW_MSB _u(30) -#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_LOW_LSB _u(30) -#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_HIGH -#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_HIGH_BITS _u(0x20000000) -#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_HIGH_MSB _u(29) -#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_HIGH_LSB _u(29) -#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_LOW -#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_LOW_BITS _u(0x10000000) -#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_LOW_MSB _u(28) -#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_LOW_LSB _u(28) -#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF1_GPIO14_EDGE_HIGH -#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_HIGH_BITS _u(0x08000000) -#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_HIGH_MSB _u(27) -#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_HIGH_LSB _u(27) -#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF1_GPIO14_EDGE_LOW -#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_LOW_BITS _u(0x04000000) -#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_LOW_MSB _u(26) -#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_LOW_LSB _u(26) -#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_HIGH -#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_HIGH_BITS _u(0x02000000) -#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_HIGH_MSB _u(25) -#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_HIGH_LSB _u(25) -#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_LOW -#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_LOW_BITS _u(0x01000000) -#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_LOW_MSB _u(24) -#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_LOW_LSB _u(24) -#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF1_GPIO13_EDGE_HIGH -#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_HIGH_BITS _u(0x00800000) -#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_HIGH_MSB _u(23) -#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_HIGH_LSB _u(23) -#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF1_GPIO13_EDGE_LOW -#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_LOW_BITS _u(0x00400000) -#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_LOW_MSB _u(22) -#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_LOW_LSB _u(22) -#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_HIGH -#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_HIGH_BITS _u(0x00200000) -#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_HIGH_MSB _u(21) -#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_HIGH_LSB _u(21) -#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_LOW -#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_LOW_BITS _u(0x00100000) -#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_LOW_MSB _u(20) -#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_LOW_LSB _u(20) -#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF1_GPIO12_EDGE_HIGH -#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_HIGH_BITS _u(0x00080000) -#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_HIGH_MSB _u(19) -#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_HIGH_LSB _u(19) -#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF1_GPIO12_EDGE_LOW -#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_LOW_BITS _u(0x00040000) -#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_LOW_MSB _u(18) -#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_LOW_LSB _u(18) -#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_HIGH -#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_HIGH_BITS _u(0x00020000) -#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_HIGH_MSB _u(17) -#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_HIGH_LSB _u(17) -#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_LOW -#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_LOW_BITS _u(0x00010000) -#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_LOW_MSB _u(16) -#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_LOW_LSB _u(16) -#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF1_GPIO11_EDGE_HIGH -#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_HIGH_BITS _u(0x00008000) -#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_HIGH_MSB _u(15) -#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_HIGH_LSB _u(15) -#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF1_GPIO11_EDGE_LOW -#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_LOW_BITS _u(0x00004000) -#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_LOW_MSB _u(14) -#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_LOW_LSB _u(14) -#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_HIGH -#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_HIGH_BITS _u(0x00002000) -#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_HIGH_MSB _u(13) -#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_HIGH_LSB _u(13) -#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_LOW -#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_LOW_BITS _u(0x00001000) -#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_LOW_MSB _u(12) -#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_LOW_LSB _u(12) -#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF1_GPIO10_EDGE_HIGH -#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_HIGH_BITS _u(0x00000800) -#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_HIGH_MSB _u(11) -#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_HIGH_LSB _u(11) -#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF1_GPIO10_EDGE_LOW -#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_LOW_BITS _u(0x00000400) -#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_LOW_MSB _u(10) -#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_LOW_LSB _u(10) -#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_HIGH -#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_HIGH_BITS _u(0x00000200) -#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_HIGH_MSB _u(9) -#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_HIGH_LSB _u(9) -#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_LOW -#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_LOW_BITS _u(0x00000100) -#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_LOW_MSB _u(8) -#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_LOW_LSB _u(8) -#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF1_GPIO9_EDGE_HIGH -#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_HIGH_BITS _u(0x00000080) -#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_HIGH_MSB _u(7) -#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_HIGH_LSB _u(7) -#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF1_GPIO9_EDGE_LOW -#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_LOW_BITS _u(0x00000040) -#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_LOW_MSB _u(6) -#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_LOW_LSB _u(6) -#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_HIGH -#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_HIGH_BITS _u(0x00000020) -#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_HIGH_MSB _u(5) -#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_HIGH_LSB _u(5) -#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_LOW -#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_LOW_BITS _u(0x00000010) -#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_LOW_MSB _u(4) -#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_LOW_LSB _u(4) -#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF1_GPIO8_EDGE_HIGH -#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_HIGH_BITS _u(0x00000008) -#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_HIGH_MSB _u(3) -#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_HIGH_LSB _u(3) -#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF1_GPIO8_EDGE_LOW -#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_LOW_BITS _u(0x00000004) -#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_LOW_MSB _u(2) -#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_LOW_LSB _u(2) -#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_HIGH -#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_HIGH_BITS _u(0x00000002) -#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_HIGH_MSB _u(1) -#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_HIGH_LSB _u(1) -#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_LOW -#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_LOW_BITS _u(0x00000001) -#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_LOW_MSB _u(0) -#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_LOW_LSB _u(0) -#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_LOW_ACCESS "RW" -// ============================================================================= -// Register : IO_BANK0_PROC0_INTF2 -// Description : Interrupt Force for proc0 -#define IO_BANK0_PROC0_INTF2_OFFSET _u(0x00000268) -#define IO_BANK0_PROC0_INTF2_BITS _u(0xffffffff) -#define IO_BANK0_PROC0_INTF2_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF2_GPIO23_EDGE_HIGH -#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_HIGH_BITS _u(0x80000000) -#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_HIGH_MSB _u(31) -#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_HIGH_LSB _u(31) -#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF2_GPIO23_EDGE_LOW -#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_LOW_BITS _u(0x40000000) -#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_LOW_MSB _u(30) -#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_LOW_LSB _u(30) -#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_HIGH -#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_HIGH_BITS _u(0x20000000) -#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_HIGH_MSB _u(29) -#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_HIGH_LSB _u(29) -#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_LOW -#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_LOW_BITS _u(0x10000000) -#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_LOW_MSB _u(28) -#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_LOW_LSB _u(28) -#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF2_GPIO22_EDGE_HIGH -#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_HIGH_BITS _u(0x08000000) -#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_HIGH_MSB _u(27) -#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_HIGH_LSB _u(27) -#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF2_GPIO22_EDGE_LOW -#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_LOW_BITS _u(0x04000000) -#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_LOW_MSB _u(26) -#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_LOW_LSB _u(26) -#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_HIGH -#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_HIGH_BITS _u(0x02000000) -#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_HIGH_MSB _u(25) -#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_HIGH_LSB _u(25) -#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_LOW -#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_LOW_BITS _u(0x01000000) -#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_LOW_MSB _u(24) -#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_LOW_LSB _u(24) -#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF2_GPIO21_EDGE_HIGH -#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_HIGH_BITS _u(0x00800000) -#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_HIGH_MSB _u(23) -#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_HIGH_LSB _u(23) -#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF2_GPIO21_EDGE_LOW -#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_LOW_BITS _u(0x00400000) -#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_LOW_MSB _u(22) -#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_LOW_LSB _u(22) -#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_HIGH -#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_HIGH_BITS _u(0x00200000) -#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_HIGH_MSB _u(21) -#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_HIGH_LSB _u(21) -#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_LOW -#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_LOW_BITS _u(0x00100000) -#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_LOW_MSB _u(20) -#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_LOW_LSB _u(20) -#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF2_GPIO20_EDGE_HIGH -#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_HIGH_BITS _u(0x00080000) -#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_HIGH_MSB _u(19) -#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_HIGH_LSB _u(19) -#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF2_GPIO20_EDGE_LOW -#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_LOW_BITS _u(0x00040000) -#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_LOW_MSB _u(18) -#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_LOW_LSB _u(18) -#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_HIGH -#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_HIGH_BITS _u(0x00020000) -#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_HIGH_MSB _u(17) -#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_HIGH_LSB _u(17) -#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_LOW -#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_LOW_BITS _u(0x00010000) -#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_LOW_MSB _u(16) -#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_LOW_LSB _u(16) -#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF2_GPIO19_EDGE_HIGH -#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_HIGH_BITS _u(0x00008000) -#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_HIGH_MSB _u(15) -#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_HIGH_LSB _u(15) -#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF2_GPIO19_EDGE_LOW -#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_LOW_BITS _u(0x00004000) -#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_LOW_MSB _u(14) -#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_LOW_LSB _u(14) -#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_HIGH -#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_HIGH_BITS _u(0x00002000) -#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_HIGH_MSB _u(13) -#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_HIGH_LSB _u(13) -#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_LOW -#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_LOW_BITS _u(0x00001000) -#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_LOW_MSB _u(12) -#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_LOW_LSB _u(12) -#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF2_GPIO18_EDGE_HIGH -#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_HIGH_BITS _u(0x00000800) -#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_HIGH_MSB _u(11) -#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_HIGH_LSB _u(11) -#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF2_GPIO18_EDGE_LOW -#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_LOW_BITS _u(0x00000400) -#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_LOW_MSB _u(10) -#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_LOW_LSB _u(10) -#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_HIGH -#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_HIGH_BITS _u(0x00000200) -#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_HIGH_MSB _u(9) -#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_HIGH_LSB _u(9) -#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_LOW -#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_LOW_BITS _u(0x00000100) -#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_LOW_MSB _u(8) -#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_LOW_LSB _u(8) -#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF2_GPIO17_EDGE_HIGH -#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_HIGH_BITS _u(0x00000080) -#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_HIGH_MSB _u(7) -#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_HIGH_LSB _u(7) -#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF2_GPIO17_EDGE_LOW -#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_LOW_BITS _u(0x00000040) -#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_LOW_MSB _u(6) -#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_LOW_LSB _u(6) -#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_HIGH -#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_HIGH_BITS _u(0x00000020) -#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_HIGH_MSB _u(5) -#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_HIGH_LSB _u(5) -#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_LOW -#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_LOW_BITS _u(0x00000010) -#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_LOW_MSB _u(4) -#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_LOW_LSB _u(4) -#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF2_GPIO16_EDGE_HIGH -#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_HIGH_BITS _u(0x00000008) -#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_HIGH_MSB _u(3) -#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_HIGH_LSB _u(3) -#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF2_GPIO16_EDGE_LOW -#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_LOW_BITS _u(0x00000004) -#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_LOW_MSB _u(2) -#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_LOW_LSB _u(2) -#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_HIGH -#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_HIGH_BITS _u(0x00000002) -#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_HIGH_MSB _u(1) -#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_HIGH_LSB _u(1) -#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_LOW -#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_LOW_BITS _u(0x00000001) -#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_LOW_MSB _u(0) -#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_LOW_LSB _u(0) -#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_LOW_ACCESS "RW" -// ============================================================================= -// Register : IO_BANK0_PROC0_INTF3 -// Description : Interrupt Force for proc0 -#define IO_BANK0_PROC0_INTF3_OFFSET _u(0x0000026c) -#define IO_BANK0_PROC0_INTF3_BITS _u(0xffffffff) -#define IO_BANK0_PROC0_INTF3_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF3_GPIO31_EDGE_HIGH -#define IO_BANK0_PROC0_INTF3_GPIO31_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF3_GPIO31_EDGE_HIGH_BITS _u(0x80000000) -#define IO_BANK0_PROC0_INTF3_GPIO31_EDGE_HIGH_MSB _u(31) -#define IO_BANK0_PROC0_INTF3_GPIO31_EDGE_HIGH_LSB _u(31) -#define IO_BANK0_PROC0_INTF3_GPIO31_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF3_GPIO31_EDGE_LOW -#define IO_BANK0_PROC0_INTF3_GPIO31_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF3_GPIO31_EDGE_LOW_BITS _u(0x40000000) -#define IO_BANK0_PROC0_INTF3_GPIO31_EDGE_LOW_MSB _u(30) -#define IO_BANK0_PROC0_INTF3_GPIO31_EDGE_LOW_LSB _u(30) -#define IO_BANK0_PROC0_INTF3_GPIO31_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF3_GPIO31_LEVEL_HIGH -#define IO_BANK0_PROC0_INTF3_GPIO31_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF3_GPIO31_LEVEL_HIGH_BITS _u(0x20000000) -#define IO_BANK0_PROC0_INTF3_GPIO31_LEVEL_HIGH_MSB _u(29) -#define IO_BANK0_PROC0_INTF3_GPIO31_LEVEL_HIGH_LSB _u(29) -#define IO_BANK0_PROC0_INTF3_GPIO31_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF3_GPIO31_LEVEL_LOW -#define IO_BANK0_PROC0_INTF3_GPIO31_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF3_GPIO31_LEVEL_LOW_BITS _u(0x10000000) -#define IO_BANK0_PROC0_INTF3_GPIO31_LEVEL_LOW_MSB _u(28) -#define IO_BANK0_PROC0_INTF3_GPIO31_LEVEL_LOW_LSB _u(28) -#define IO_BANK0_PROC0_INTF3_GPIO31_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF3_GPIO30_EDGE_HIGH -#define IO_BANK0_PROC0_INTF3_GPIO30_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF3_GPIO30_EDGE_HIGH_BITS _u(0x08000000) -#define IO_BANK0_PROC0_INTF3_GPIO30_EDGE_HIGH_MSB _u(27) -#define IO_BANK0_PROC0_INTF3_GPIO30_EDGE_HIGH_LSB _u(27) -#define IO_BANK0_PROC0_INTF3_GPIO30_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF3_GPIO30_EDGE_LOW -#define IO_BANK0_PROC0_INTF3_GPIO30_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF3_GPIO30_EDGE_LOW_BITS _u(0x04000000) -#define IO_BANK0_PROC0_INTF3_GPIO30_EDGE_LOW_MSB _u(26) -#define IO_BANK0_PROC0_INTF3_GPIO30_EDGE_LOW_LSB _u(26) -#define IO_BANK0_PROC0_INTF3_GPIO30_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF3_GPIO30_LEVEL_HIGH -#define IO_BANK0_PROC0_INTF3_GPIO30_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF3_GPIO30_LEVEL_HIGH_BITS _u(0x02000000) -#define IO_BANK0_PROC0_INTF3_GPIO30_LEVEL_HIGH_MSB _u(25) -#define IO_BANK0_PROC0_INTF3_GPIO30_LEVEL_HIGH_LSB _u(25) -#define IO_BANK0_PROC0_INTF3_GPIO30_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF3_GPIO30_LEVEL_LOW -#define IO_BANK0_PROC0_INTF3_GPIO30_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF3_GPIO30_LEVEL_LOW_BITS _u(0x01000000) -#define IO_BANK0_PROC0_INTF3_GPIO30_LEVEL_LOW_MSB _u(24) -#define IO_BANK0_PROC0_INTF3_GPIO30_LEVEL_LOW_LSB _u(24) -#define IO_BANK0_PROC0_INTF3_GPIO30_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF3_GPIO29_EDGE_HIGH -#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_HIGH_BITS _u(0x00800000) -#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_HIGH_MSB _u(23) -#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_HIGH_LSB _u(23) -#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF3_GPIO29_EDGE_LOW -#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_LOW_BITS _u(0x00400000) -#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_LOW_MSB _u(22) -#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_LOW_LSB _u(22) -#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_HIGH -#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_HIGH_BITS _u(0x00200000) -#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_HIGH_MSB _u(21) -#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_HIGH_LSB _u(21) -#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_LOW -#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_LOW_BITS _u(0x00100000) -#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_LOW_MSB _u(20) -#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_LOW_LSB _u(20) -#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF3_GPIO28_EDGE_HIGH -#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_HIGH_BITS _u(0x00080000) -#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_HIGH_MSB _u(19) -#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_HIGH_LSB _u(19) -#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF3_GPIO28_EDGE_LOW -#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_LOW_BITS _u(0x00040000) -#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_LOW_MSB _u(18) -#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_LOW_LSB _u(18) -#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_HIGH -#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_HIGH_BITS _u(0x00020000) -#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_HIGH_MSB _u(17) -#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_HIGH_LSB _u(17) -#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_LOW -#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_LOW_BITS _u(0x00010000) -#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_LOW_MSB _u(16) -#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_LOW_LSB _u(16) -#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF3_GPIO27_EDGE_HIGH -#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_HIGH_BITS _u(0x00008000) -#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_HIGH_MSB _u(15) -#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_HIGH_LSB _u(15) -#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF3_GPIO27_EDGE_LOW -#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_LOW_BITS _u(0x00004000) -#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_LOW_MSB _u(14) -#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_LOW_LSB _u(14) -#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_HIGH -#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_HIGH_BITS _u(0x00002000) -#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_HIGH_MSB _u(13) -#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_HIGH_LSB _u(13) -#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_LOW -#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_LOW_BITS _u(0x00001000) -#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_LOW_MSB _u(12) -#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_LOW_LSB _u(12) -#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF3_GPIO26_EDGE_HIGH -#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_HIGH_BITS _u(0x00000800) -#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_HIGH_MSB _u(11) -#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_HIGH_LSB _u(11) -#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF3_GPIO26_EDGE_LOW -#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_LOW_BITS _u(0x00000400) -#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_LOW_MSB _u(10) -#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_LOW_LSB _u(10) -#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_HIGH -#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_HIGH_BITS _u(0x00000200) -#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_HIGH_MSB _u(9) -#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_HIGH_LSB _u(9) -#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_LOW -#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_LOW_BITS _u(0x00000100) -#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_LOW_MSB _u(8) -#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_LOW_LSB _u(8) -#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF3_GPIO25_EDGE_HIGH -#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_HIGH_BITS _u(0x00000080) -#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_HIGH_MSB _u(7) -#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_HIGH_LSB _u(7) -#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF3_GPIO25_EDGE_LOW -#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_LOW_BITS _u(0x00000040) -#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_LOW_MSB _u(6) -#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_LOW_LSB _u(6) -#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_HIGH -#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_HIGH_BITS _u(0x00000020) -#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_HIGH_MSB _u(5) -#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_HIGH_LSB _u(5) -#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_LOW -#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_LOW_BITS _u(0x00000010) -#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_LOW_MSB _u(4) -#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_LOW_LSB _u(4) -#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF3_GPIO24_EDGE_HIGH -#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_HIGH_BITS _u(0x00000008) -#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_HIGH_MSB _u(3) -#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_HIGH_LSB _u(3) -#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF3_GPIO24_EDGE_LOW -#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_LOW_BITS _u(0x00000004) -#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_LOW_MSB _u(2) -#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_LOW_LSB _u(2) -#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_HIGH -#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_HIGH_BITS _u(0x00000002) -#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_HIGH_MSB _u(1) -#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_HIGH_LSB _u(1) -#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_LOW -#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_LOW_BITS _u(0x00000001) -#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_LOW_MSB _u(0) -#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_LOW_LSB _u(0) -#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_LOW_ACCESS "RW" -// ============================================================================= -// Register : IO_BANK0_PROC0_INTF4 -// Description : Interrupt Force for proc0 -#define IO_BANK0_PROC0_INTF4_OFFSET _u(0x00000270) -#define IO_BANK0_PROC0_INTF4_BITS _u(0xffffffff) -#define IO_BANK0_PROC0_INTF4_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF4_GPIO39_EDGE_HIGH -#define IO_BANK0_PROC0_INTF4_GPIO39_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF4_GPIO39_EDGE_HIGH_BITS _u(0x80000000) -#define IO_BANK0_PROC0_INTF4_GPIO39_EDGE_HIGH_MSB _u(31) -#define IO_BANK0_PROC0_INTF4_GPIO39_EDGE_HIGH_LSB _u(31) -#define IO_BANK0_PROC0_INTF4_GPIO39_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF4_GPIO39_EDGE_LOW -#define IO_BANK0_PROC0_INTF4_GPIO39_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF4_GPIO39_EDGE_LOW_BITS _u(0x40000000) -#define IO_BANK0_PROC0_INTF4_GPIO39_EDGE_LOW_MSB _u(30) -#define IO_BANK0_PROC0_INTF4_GPIO39_EDGE_LOW_LSB _u(30) -#define IO_BANK0_PROC0_INTF4_GPIO39_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF4_GPIO39_LEVEL_HIGH -#define IO_BANK0_PROC0_INTF4_GPIO39_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF4_GPIO39_LEVEL_HIGH_BITS _u(0x20000000) -#define IO_BANK0_PROC0_INTF4_GPIO39_LEVEL_HIGH_MSB _u(29) -#define IO_BANK0_PROC0_INTF4_GPIO39_LEVEL_HIGH_LSB _u(29) -#define IO_BANK0_PROC0_INTF4_GPIO39_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF4_GPIO39_LEVEL_LOW -#define IO_BANK0_PROC0_INTF4_GPIO39_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF4_GPIO39_LEVEL_LOW_BITS _u(0x10000000) -#define IO_BANK0_PROC0_INTF4_GPIO39_LEVEL_LOW_MSB _u(28) -#define IO_BANK0_PROC0_INTF4_GPIO39_LEVEL_LOW_LSB _u(28) -#define IO_BANK0_PROC0_INTF4_GPIO39_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF4_GPIO38_EDGE_HIGH -#define IO_BANK0_PROC0_INTF4_GPIO38_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF4_GPIO38_EDGE_HIGH_BITS _u(0x08000000) -#define IO_BANK0_PROC0_INTF4_GPIO38_EDGE_HIGH_MSB _u(27) -#define IO_BANK0_PROC0_INTF4_GPIO38_EDGE_HIGH_LSB _u(27) -#define IO_BANK0_PROC0_INTF4_GPIO38_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF4_GPIO38_EDGE_LOW -#define IO_BANK0_PROC0_INTF4_GPIO38_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF4_GPIO38_EDGE_LOW_BITS _u(0x04000000) -#define IO_BANK0_PROC0_INTF4_GPIO38_EDGE_LOW_MSB _u(26) -#define IO_BANK0_PROC0_INTF4_GPIO38_EDGE_LOW_LSB _u(26) -#define IO_BANK0_PROC0_INTF4_GPIO38_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF4_GPIO38_LEVEL_HIGH -#define IO_BANK0_PROC0_INTF4_GPIO38_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF4_GPIO38_LEVEL_HIGH_BITS _u(0x02000000) -#define IO_BANK0_PROC0_INTF4_GPIO38_LEVEL_HIGH_MSB _u(25) -#define IO_BANK0_PROC0_INTF4_GPIO38_LEVEL_HIGH_LSB _u(25) -#define IO_BANK0_PROC0_INTF4_GPIO38_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF4_GPIO38_LEVEL_LOW -#define IO_BANK0_PROC0_INTF4_GPIO38_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF4_GPIO38_LEVEL_LOW_BITS _u(0x01000000) -#define IO_BANK0_PROC0_INTF4_GPIO38_LEVEL_LOW_MSB _u(24) -#define IO_BANK0_PROC0_INTF4_GPIO38_LEVEL_LOW_LSB _u(24) -#define IO_BANK0_PROC0_INTF4_GPIO38_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF4_GPIO37_EDGE_HIGH -#define IO_BANK0_PROC0_INTF4_GPIO37_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF4_GPIO37_EDGE_HIGH_BITS _u(0x00800000) -#define IO_BANK0_PROC0_INTF4_GPIO37_EDGE_HIGH_MSB _u(23) -#define IO_BANK0_PROC0_INTF4_GPIO37_EDGE_HIGH_LSB _u(23) -#define IO_BANK0_PROC0_INTF4_GPIO37_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF4_GPIO37_EDGE_LOW -#define IO_BANK0_PROC0_INTF4_GPIO37_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF4_GPIO37_EDGE_LOW_BITS _u(0x00400000) -#define IO_BANK0_PROC0_INTF4_GPIO37_EDGE_LOW_MSB _u(22) -#define IO_BANK0_PROC0_INTF4_GPIO37_EDGE_LOW_LSB _u(22) -#define IO_BANK0_PROC0_INTF4_GPIO37_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF4_GPIO37_LEVEL_HIGH -#define IO_BANK0_PROC0_INTF4_GPIO37_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF4_GPIO37_LEVEL_HIGH_BITS _u(0x00200000) -#define IO_BANK0_PROC0_INTF4_GPIO37_LEVEL_HIGH_MSB _u(21) -#define IO_BANK0_PROC0_INTF4_GPIO37_LEVEL_HIGH_LSB _u(21) -#define IO_BANK0_PROC0_INTF4_GPIO37_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF4_GPIO37_LEVEL_LOW -#define IO_BANK0_PROC0_INTF4_GPIO37_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF4_GPIO37_LEVEL_LOW_BITS _u(0x00100000) -#define IO_BANK0_PROC0_INTF4_GPIO37_LEVEL_LOW_MSB _u(20) -#define IO_BANK0_PROC0_INTF4_GPIO37_LEVEL_LOW_LSB _u(20) -#define IO_BANK0_PROC0_INTF4_GPIO37_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF4_GPIO36_EDGE_HIGH -#define IO_BANK0_PROC0_INTF4_GPIO36_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF4_GPIO36_EDGE_HIGH_BITS _u(0x00080000) -#define IO_BANK0_PROC0_INTF4_GPIO36_EDGE_HIGH_MSB _u(19) -#define IO_BANK0_PROC0_INTF4_GPIO36_EDGE_HIGH_LSB _u(19) -#define IO_BANK0_PROC0_INTF4_GPIO36_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF4_GPIO36_EDGE_LOW -#define IO_BANK0_PROC0_INTF4_GPIO36_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF4_GPIO36_EDGE_LOW_BITS _u(0x00040000) -#define IO_BANK0_PROC0_INTF4_GPIO36_EDGE_LOW_MSB _u(18) -#define IO_BANK0_PROC0_INTF4_GPIO36_EDGE_LOW_LSB _u(18) -#define IO_BANK0_PROC0_INTF4_GPIO36_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF4_GPIO36_LEVEL_HIGH -#define IO_BANK0_PROC0_INTF4_GPIO36_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF4_GPIO36_LEVEL_HIGH_BITS _u(0x00020000) -#define IO_BANK0_PROC0_INTF4_GPIO36_LEVEL_HIGH_MSB _u(17) -#define IO_BANK0_PROC0_INTF4_GPIO36_LEVEL_HIGH_LSB _u(17) -#define IO_BANK0_PROC0_INTF4_GPIO36_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF4_GPIO36_LEVEL_LOW -#define IO_BANK0_PROC0_INTF4_GPIO36_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF4_GPIO36_LEVEL_LOW_BITS _u(0x00010000) -#define IO_BANK0_PROC0_INTF4_GPIO36_LEVEL_LOW_MSB _u(16) -#define IO_BANK0_PROC0_INTF4_GPIO36_LEVEL_LOW_LSB _u(16) -#define IO_BANK0_PROC0_INTF4_GPIO36_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF4_GPIO35_EDGE_HIGH -#define IO_BANK0_PROC0_INTF4_GPIO35_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF4_GPIO35_EDGE_HIGH_BITS _u(0x00008000) -#define IO_BANK0_PROC0_INTF4_GPIO35_EDGE_HIGH_MSB _u(15) -#define IO_BANK0_PROC0_INTF4_GPIO35_EDGE_HIGH_LSB _u(15) -#define IO_BANK0_PROC0_INTF4_GPIO35_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF4_GPIO35_EDGE_LOW -#define IO_BANK0_PROC0_INTF4_GPIO35_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF4_GPIO35_EDGE_LOW_BITS _u(0x00004000) -#define IO_BANK0_PROC0_INTF4_GPIO35_EDGE_LOW_MSB _u(14) -#define IO_BANK0_PROC0_INTF4_GPIO35_EDGE_LOW_LSB _u(14) -#define IO_BANK0_PROC0_INTF4_GPIO35_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF4_GPIO35_LEVEL_HIGH -#define IO_BANK0_PROC0_INTF4_GPIO35_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF4_GPIO35_LEVEL_HIGH_BITS _u(0x00002000) -#define IO_BANK0_PROC0_INTF4_GPIO35_LEVEL_HIGH_MSB _u(13) -#define IO_BANK0_PROC0_INTF4_GPIO35_LEVEL_HIGH_LSB _u(13) -#define IO_BANK0_PROC0_INTF4_GPIO35_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF4_GPIO35_LEVEL_LOW -#define IO_BANK0_PROC0_INTF4_GPIO35_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF4_GPIO35_LEVEL_LOW_BITS _u(0x00001000) -#define IO_BANK0_PROC0_INTF4_GPIO35_LEVEL_LOW_MSB _u(12) -#define IO_BANK0_PROC0_INTF4_GPIO35_LEVEL_LOW_LSB _u(12) -#define IO_BANK0_PROC0_INTF4_GPIO35_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF4_GPIO34_EDGE_HIGH -#define IO_BANK0_PROC0_INTF4_GPIO34_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF4_GPIO34_EDGE_HIGH_BITS _u(0x00000800) -#define IO_BANK0_PROC0_INTF4_GPIO34_EDGE_HIGH_MSB _u(11) -#define IO_BANK0_PROC0_INTF4_GPIO34_EDGE_HIGH_LSB _u(11) -#define IO_BANK0_PROC0_INTF4_GPIO34_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF4_GPIO34_EDGE_LOW -#define IO_BANK0_PROC0_INTF4_GPIO34_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF4_GPIO34_EDGE_LOW_BITS _u(0x00000400) -#define IO_BANK0_PROC0_INTF4_GPIO34_EDGE_LOW_MSB _u(10) -#define IO_BANK0_PROC0_INTF4_GPIO34_EDGE_LOW_LSB _u(10) -#define IO_BANK0_PROC0_INTF4_GPIO34_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF4_GPIO34_LEVEL_HIGH -#define IO_BANK0_PROC0_INTF4_GPIO34_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF4_GPIO34_LEVEL_HIGH_BITS _u(0x00000200) -#define IO_BANK0_PROC0_INTF4_GPIO34_LEVEL_HIGH_MSB _u(9) -#define IO_BANK0_PROC0_INTF4_GPIO34_LEVEL_HIGH_LSB _u(9) -#define IO_BANK0_PROC0_INTF4_GPIO34_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF4_GPIO34_LEVEL_LOW -#define IO_BANK0_PROC0_INTF4_GPIO34_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF4_GPIO34_LEVEL_LOW_BITS _u(0x00000100) -#define IO_BANK0_PROC0_INTF4_GPIO34_LEVEL_LOW_MSB _u(8) -#define IO_BANK0_PROC0_INTF4_GPIO34_LEVEL_LOW_LSB _u(8) -#define IO_BANK0_PROC0_INTF4_GPIO34_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF4_GPIO33_EDGE_HIGH -#define IO_BANK0_PROC0_INTF4_GPIO33_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF4_GPIO33_EDGE_HIGH_BITS _u(0x00000080) -#define IO_BANK0_PROC0_INTF4_GPIO33_EDGE_HIGH_MSB _u(7) -#define IO_BANK0_PROC0_INTF4_GPIO33_EDGE_HIGH_LSB _u(7) -#define IO_BANK0_PROC0_INTF4_GPIO33_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF4_GPIO33_EDGE_LOW -#define IO_BANK0_PROC0_INTF4_GPIO33_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF4_GPIO33_EDGE_LOW_BITS _u(0x00000040) -#define IO_BANK0_PROC0_INTF4_GPIO33_EDGE_LOW_MSB _u(6) -#define IO_BANK0_PROC0_INTF4_GPIO33_EDGE_LOW_LSB _u(6) -#define IO_BANK0_PROC0_INTF4_GPIO33_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF4_GPIO33_LEVEL_HIGH -#define IO_BANK0_PROC0_INTF4_GPIO33_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF4_GPIO33_LEVEL_HIGH_BITS _u(0x00000020) -#define IO_BANK0_PROC0_INTF4_GPIO33_LEVEL_HIGH_MSB _u(5) -#define IO_BANK0_PROC0_INTF4_GPIO33_LEVEL_HIGH_LSB _u(5) -#define IO_BANK0_PROC0_INTF4_GPIO33_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF4_GPIO33_LEVEL_LOW -#define IO_BANK0_PROC0_INTF4_GPIO33_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF4_GPIO33_LEVEL_LOW_BITS _u(0x00000010) -#define IO_BANK0_PROC0_INTF4_GPIO33_LEVEL_LOW_MSB _u(4) -#define IO_BANK0_PROC0_INTF4_GPIO33_LEVEL_LOW_LSB _u(4) -#define IO_BANK0_PROC0_INTF4_GPIO33_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF4_GPIO32_EDGE_HIGH -#define IO_BANK0_PROC0_INTF4_GPIO32_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF4_GPIO32_EDGE_HIGH_BITS _u(0x00000008) -#define IO_BANK0_PROC0_INTF4_GPIO32_EDGE_HIGH_MSB _u(3) -#define IO_BANK0_PROC0_INTF4_GPIO32_EDGE_HIGH_LSB _u(3) -#define IO_BANK0_PROC0_INTF4_GPIO32_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF4_GPIO32_EDGE_LOW -#define IO_BANK0_PROC0_INTF4_GPIO32_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF4_GPIO32_EDGE_LOW_BITS _u(0x00000004) -#define IO_BANK0_PROC0_INTF4_GPIO32_EDGE_LOW_MSB _u(2) -#define IO_BANK0_PROC0_INTF4_GPIO32_EDGE_LOW_LSB _u(2) -#define IO_BANK0_PROC0_INTF4_GPIO32_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF4_GPIO32_LEVEL_HIGH -#define IO_BANK0_PROC0_INTF4_GPIO32_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF4_GPIO32_LEVEL_HIGH_BITS _u(0x00000002) -#define IO_BANK0_PROC0_INTF4_GPIO32_LEVEL_HIGH_MSB _u(1) -#define IO_BANK0_PROC0_INTF4_GPIO32_LEVEL_HIGH_LSB _u(1) -#define IO_BANK0_PROC0_INTF4_GPIO32_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF4_GPIO32_LEVEL_LOW -#define IO_BANK0_PROC0_INTF4_GPIO32_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF4_GPIO32_LEVEL_LOW_BITS _u(0x00000001) -#define IO_BANK0_PROC0_INTF4_GPIO32_LEVEL_LOW_MSB _u(0) -#define IO_BANK0_PROC0_INTF4_GPIO32_LEVEL_LOW_LSB _u(0) -#define IO_BANK0_PROC0_INTF4_GPIO32_LEVEL_LOW_ACCESS "RW" -// ============================================================================= -// Register : IO_BANK0_PROC0_INTF5 -// Description : Interrupt Force for proc0 -#define IO_BANK0_PROC0_INTF5_OFFSET _u(0x00000274) -#define IO_BANK0_PROC0_INTF5_BITS _u(0xffffffff) -#define IO_BANK0_PROC0_INTF5_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF5_GPIO47_EDGE_HIGH -#define IO_BANK0_PROC0_INTF5_GPIO47_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF5_GPIO47_EDGE_HIGH_BITS _u(0x80000000) -#define IO_BANK0_PROC0_INTF5_GPIO47_EDGE_HIGH_MSB _u(31) -#define IO_BANK0_PROC0_INTF5_GPIO47_EDGE_HIGH_LSB _u(31) -#define IO_BANK0_PROC0_INTF5_GPIO47_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF5_GPIO47_EDGE_LOW -#define IO_BANK0_PROC0_INTF5_GPIO47_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF5_GPIO47_EDGE_LOW_BITS _u(0x40000000) -#define IO_BANK0_PROC0_INTF5_GPIO47_EDGE_LOW_MSB _u(30) -#define IO_BANK0_PROC0_INTF5_GPIO47_EDGE_LOW_LSB _u(30) -#define IO_BANK0_PROC0_INTF5_GPIO47_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF5_GPIO47_LEVEL_HIGH -#define IO_BANK0_PROC0_INTF5_GPIO47_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF5_GPIO47_LEVEL_HIGH_BITS _u(0x20000000) -#define IO_BANK0_PROC0_INTF5_GPIO47_LEVEL_HIGH_MSB _u(29) -#define IO_BANK0_PROC0_INTF5_GPIO47_LEVEL_HIGH_LSB _u(29) -#define IO_BANK0_PROC0_INTF5_GPIO47_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF5_GPIO47_LEVEL_LOW -#define IO_BANK0_PROC0_INTF5_GPIO47_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF5_GPIO47_LEVEL_LOW_BITS _u(0x10000000) -#define IO_BANK0_PROC0_INTF5_GPIO47_LEVEL_LOW_MSB _u(28) -#define IO_BANK0_PROC0_INTF5_GPIO47_LEVEL_LOW_LSB _u(28) -#define IO_BANK0_PROC0_INTF5_GPIO47_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF5_GPIO46_EDGE_HIGH -#define IO_BANK0_PROC0_INTF5_GPIO46_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF5_GPIO46_EDGE_HIGH_BITS _u(0x08000000) -#define IO_BANK0_PROC0_INTF5_GPIO46_EDGE_HIGH_MSB _u(27) -#define IO_BANK0_PROC0_INTF5_GPIO46_EDGE_HIGH_LSB _u(27) -#define IO_BANK0_PROC0_INTF5_GPIO46_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF5_GPIO46_EDGE_LOW -#define IO_BANK0_PROC0_INTF5_GPIO46_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF5_GPIO46_EDGE_LOW_BITS _u(0x04000000) -#define IO_BANK0_PROC0_INTF5_GPIO46_EDGE_LOW_MSB _u(26) -#define IO_BANK0_PROC0_INTF5_GPIO46_EDGE_LOW_LSB _u(26) -#define IO_BANK0_PROC0_INTF5_GPIO46_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF5_GPIO46_LEVEL_HIGH -#define IO_BANK0_PROC0_INTF5_GPIO46_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF5_GPIO46_LEVEL_HIGH_BITS _u(0x02000000) -#define IO_BANK0_PROC0_INTF5_GPIO46_LEVEL_HIGH_MSB _u(25) -#define IO_BANK0_PROC0_INTF5_GPIO46_LEVEL_HIGH_LSB _u(25) -#define IO_BANK0_PROC0_INTF5_GPIO46_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF5_GPIO46_LEVEL_LOW -#define IO_BANK0_PROC0_INTF5_GPIO46_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF5_GPIO46_LEVEL_LOW_BITS _u(0x01000000) -#define IO_BANK0_PROC0_INTF5_GPIO46_LEVEL_LOW_MSB _u(24) -#define IO_BANK0_PROC0_INTF5_GPIO46_LEVEL_LOW_LSB _u(24) -#define IO_BANK0_PROC0_INTF5_GPIO46_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF5_GPIO45_EDGE_HIGH -#define IO_BANK0_PROC0_INTF5_GPIO45_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF5_GPIO45_EDGE_HIGH_BITS _u(0x00800000) -#define IO_BANK0_PROC0_INTF5_GPIO45_EDGE_HIGH_MSB _u(23) -#define IO_BANK0_PROC0_INTF5_GPIO45_EDGE_HIGH_LSB _u(23) -#define IO_BANK0_PROC0_INTF5_GPIO45_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF5_GPIO45_EDGE_LOW -#define IO_BANK0_PROC0_INTF5_GPIO45_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF5_GPIO45_EDGE_LOW_BITS _u(0x00400000) -#define IO_BANK0_PROC0_INTF5_GPIO45_EDGE_LOW_MSB _u(22) -#define IO_BANK0_PROC0_INTF5_GPIO45_EDGE_LOW_LSB _u(22) -#define IO_BANK0_PROC0_INTF5_GPIO45_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF5_GPIO45_LEVEL_HIGH -#define IO_BANK0_PROC0_INTF5_GPIO45_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF5_GPIO45_LEVEL_HIGH_BITS _u(0x00200000) -#define IO_BANK0_PROC0_INTF5_GPIO45_LEVEL_HIGH_MSB _u(21) -#define IO_BANK0_PROC0_INTF5_GPIO45_LEVEL_HIGH_LSB _u(21) -#define IO_BANK0_PROC0_INTF5_GPIO45_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF5_GPIO45_LEVEL_LOW -#define IO_BANK0_PROC0_INTF5_GPIO45_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF5_GPIO45_LEVEL_LOW_BITS _u(0x00100000) -#define IO_BANK0_PROC0_INTF5_GPIO45_LEVEL_LOW_MSB _u(20) -#define IO_BANK0_PROC0_INTF5_GPIO45_LEVEL_LOW_LSB _u(20) -#define IO_BANK0_PROC0_INTF5_GPIO45_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF5_GPIO44_EDGE_HIGH -#define IO_BANK0_PROC0_INTF5_GPIO44_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF5_GPIO44_EDGE_HIGH_BITS _u(0x00080000) -#define IO_BANK0_PROC0_INTF5_GPIO44_EDGE_HIGH_MSB _u(19) -#define IO_BANK0_PROC0_INTF5_GPIO44_EDGE_HIGH_LSB _u(19) -#define IO_BANK0_PROC0_INTF5_GPIO44_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF5_GPIO44_EDGE_LOW -#define IO_BANK0_PROC0_INTF5_GPIO44_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF5_GPIO44_EDGE_LOW_BITS _u(0x00040000) -#define IO_BANK0_PROC0_INTF5_GPIO44_EDGE_LOW_MSB _u(18) -#define IO_BANK0_PROC0_INTF5_GPIO44_EDGE_LOW_LSB _u(18) -#define IO_BANK0_PROC0_INTF5_GPIO44_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF5_GPIO44_LEVEL_HIGH -#define IO_BANK0_PROC0_INTF5_GPIO44_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF5_GPIO44_LEVEL_HIGH_BITS _u(0x00020000) -#define IO_BANK0_PROC0_INTF5_GPIO44_LEVEL_HIGH_MSB _u(17) -#define IO_BANK0_PROC0_INTF5_GPIO44_LEVEL_HIGH_LSB _u(17) -#define IO_BANK0_PROC0_INTF5_GPIO44_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF5_GPIO44_LEVEL_LOW -#define IO_BANK0_PROC0_INTF5_GPIO44_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF5_GPIO44_LEVEL_LOW_BITS _u(0x00010000) -#define IO_BANK0_PROC0_INTF5_GPIO44_LEVEL_LOW_MSB _u(16) -#define IO_BANK0_PROC0_INTF5_GPIO44_LEVEL_LOW_LSB _u(16) -#define IO_BANK0_PROC0_INTF5_GPIO44_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF5_GPIO43_EDGE_HIGH -#define IO_BANK0_PROC0_INTF5_GPIO43_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF5_GPIO43_EDGE_HIGH_BITS _u(0x00008000) -#define IO_BANK0_PROC0_INTF5_GPIO43_EDGE_HIGH_MSB _u(15) -#define IO_BANK0_PROC0_INTF5_GPIO43_EDGE_HIGH_LSB _u(15) -#define IO_BANK0_PROC0_INTF5_GPIO43_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF5_GPIO43_EDGE_LOW -#define IO_BANK0_PROC0_INTF5_GPIO43_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF5_GPIO43_EDGE_LOW_BITS _u(0x00004000) -#define IO_BANK0_PROC0_INTF5_GPIO43_EDGE_LOW_MSB _u(14) -#define IO_BANK0_PROC0_INTF5_GPIO43_EDGE_LOW_LSB _u(14) -#define IO_BANK0_PROC0_INTF5_GPIO43_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF5_GPIO43_LEVEL_HIGH -#define IO_BANK0_PROC0_INTF5_GPIO43_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF5_GPIO43_LEVEL_HIGH_BITS _u(0x00002000) -#define IO_BANK0_PROC0_INTF5_GPIO43_LEVEL_HIGH_MSB _u(13) -#define IO_BANK0_PROC0_INTF5_GPIO43_LEVEL_HIGH_LSB _u(13) -#define IO_BANK0_PROC0_INTF5_GPIO43_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF5_GPIO43_LEVEL_LOW -#define IO_BANK0_PROC0_INTF5_GPIO43_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF5_GPIO43_LEVEL_LOW_BITS _u(0x00001000) -#define IO_BANK0_PROC0_INTF5_GPIO43_LEVEL_LOW_MSB _u(12) -#define IO_BANK0_PROC0_INTF5_GPIO43_LEVEL_LOW_LSB _u(12) -#define IO_BANK0_PROC0_INTF5_GPIO43_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF5_GPIO42_EDGE_HIGH -#define IO_BANK0_PROC0_INTF5_GPIO42_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF5_GPIO42_EDGE_HIGH_BITS _u(0x00000800) -#define IO_BANK0_PROC0_INTF5_GPIO42_EDGE_HIGH_MSB _u(11) -#define IO_BANK0_PROC0_INTF5_GPIO42_EDGE_HIGH_LSB _u(11) -#define IO_BANK0_PROC0_INTF5_GPIO42_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF5_GPIO42_EDGE_LOW -#define IO_BANK0_PROC0_INTF5_GPIO42_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF5_GPIO42_EDGE_LOW_BITS _u(0x00000400) -#define IO_BANK0_PROC0_INTF5_GPIO42_EDGE_LOW_MSB _u(10) -#define IO_BANK0_PROC0_INTF5_GPIO42_EDGE_LOW_LSB _u(10) -#define IO_BANK0_PROC0_INTF5_GPIO42_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF5_GPIO42_LEVEL_HIGH -#define IO_BANK0_PROC0_INTF5_GPIO42_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF5_GPIO42_LEVEL_HIGH_BITS _u(0x00000200) -#define IO_BANK0_PROC0_INTF5_GPIO42_LEVEL_HIGH_MSB _u(9) -#define IO_BANK0_PROC0_INTF5_GPIO42_LEVEL_HIGH_LSB _u(9) -#define IO_BANK0_PROC0_INTF5_GPIO42_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF5_GPIO42_LEVEL_LOW -#define IO_BANK0_PROC0_INTF5_GPIO42_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF5_GPIO42_LEVEL_LOW_BITS _u(0x00000100) -#define IO_BANK0_PROC0_INTF5_GPIO42_LEVEL_LOW_MSB _u(8) -#define IO_BANK0_PROC0_INTF5_GPIO42_LEVEL_LOW_LSB _u(8) -#define IO_BANK0_PROC0_INTF5_GPIO42_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF5_GPIO41_EDGE_HIGH -#define IO_BANK0_PROC0_INTF5_GPIO41_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF5_GPIO41_EDGE_HIGH_BITS _u(0x00000080) -#define IO_BANK0_PROC0_INTF5_GPIO41_EDGE_HIGH_MSB _u(7) -#define IO_BANK0_PROC0_INTF5_GPIO41_EDGE_HIGH_LSB _u(7) -#define IO_BANK0_PROC0_INTF5_GPIO41_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF5_GPIO41_EDGE_LOW -#define IO_BANK0_PROC0_INTF5_GPIO41_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF5_GPIO41_EDGE_LOW_BITS _u(0x00000040) -#define IO_BANK0_PROC0_INTF5_GPIO41_EDGE_LOW_MSB _u(6) -#define IO_BANK0_PROC0_INTF5_GPIO41_EDGE_LOW_LSB _u(6) -#define IO_BANK0_PROC0_INTF5_GPIO41_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF5_GPIO41_LEVEL_HIGH -#define IO_BANK0_PROC0_INTF5_GPIO41_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF5_GPIO41_LEVEL_HIGH_BITS _u(0x00000020) -#define IO_BANK0_PROC0_INTF5_GPIO41_LEVEL_HIGH_MSB _u(5) -#define IO_BANK0_PROC0_INTF5_GPIO41_LEVEL_HIGH_LSB _u(5) -#define IO_BANK0_PROC0_INTF5_GPIO41_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF5_GPIO41_LEVEL_LOW -#define IO_BANK0_PROC0_INTF5_GPIO41_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF5_GPIO41_LEVEL_LOW_BITS _u(0x00000010) -#define IO_BANK0_PROC0_INTF5_GPIO41_LEVEL_LOW_MSB _u(4) -#define IO_BANK0_PROC0_INTF5_GPIO41_LEVEL_LOW_LSB _u(4) -#define IO_BANK0_PROC0_INTF5_GPIO41_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF5_GPIO40_EDGE_HIGH -#define IO_BANK0_PROC0_INTF5_GPIO40_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF5_GPIO40_EDGE_HIGH_BITS _u(0x00000008) -#define IO_BANK0_PROC0_INTF5_GPIO40_EDGE_HIGH_MSB _u(3) -#define IO_BANK0_PROC0_INTF5_GPIO40_EDGE_HIGH_LSB _u(3) -#define IO_BANK0_PROC0_INTF5_GPIO40_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF5_GPIO40_EDGE_LOW -#define IO_BANK0_PROC0_INTF5_GPIO40_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF5_GPIO40_EDGE_LOW_BITS _u(0x00000004) -#define IO_BANK0_PROC0_INTF5_GPIO40_EDGE_LOW_MSB _u(2) -#define IO_BANK0_PROC0_INTF5_GPIO40_EDGE_LOW_LSB _u(2) -#define IO_BANK0_PROC0_INTF5_GPIO40_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF5_GPIO40_LEVEL_HIGH -#define IO_BANK0_PROC0_INTF5_GPIO40_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF5_GPIO40_LEVEL_HIGH_BITS _u(0x00000002) -#define IO_BANK0_PROC0_INTF5_GPIO40_LEVEL_HIGH_MSB _u(1) -#define IO_BANK0_PROC0_INTF5_GPIO40_LEVEL_HIGH_LSB _u(1) -#define IO_BANK0_PROC0_INTF5_GPIO40_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTF5_GPIO40_LEVEL_LOW -#define IO_BANK0_PROC0_INTF5_GPIO40_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTF5_GPIO40_LEVEL_LOW_BITS _u(0x00000001) -#define IO_BANK0_PROC0_INTF5_GPIO40_LEVEL_LOW_MSB _u(0) -#define IO_BANK0_PROC0_INTF5_GPIO40_LEVEL_LOW_LSB _u(0) -#define IO_BANK0_PROC0_INTF5_GPIO40_LEVEL_LOW_ACCESS "RW" -// ============================================================================= -// Register : IO_BANK0_PROC0_INTS0 -// Description : Interrupt status after masking & forcing for proc0 -#define IO_BANK0_PROC0_INTS0_OFFSET _u(0x00000278) -#define IO_BANK0_PROC0_INTS0_BITS _u(0xffffffff) -#define IO_BANK0_PROC0_INTS0_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS0_GPIO7_EDGE_HIGH -#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_HIGH_BITS _u(0x80000000) -#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_HIGH_MSB _u(31) -#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_HIGH_LSB _u(31) -#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS0_GPIO7_EDGE_LOW -#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_LOW_BITS _u(0x40000000) -#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_LOW_MSB _u(30) -#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_LOW_LSB _u(30) -#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_HIGH -#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_HIGH_BITS _u(0x20000000) -#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_HIGH_MSB _u(29) -#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_HIGH_LSB _u(29) -#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_LOW -#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_LOW_BITS _u(0x10000000) -#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_LOW_MSB _u(28) -#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_LOW_LSB _u(28) -#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS0_GPIO6_EDGE_HIGH -#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_HIGH_BITS _u(0x08000000) -#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_HIGH_MSB _u(27) -#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_HIGH_LSB _u(27) -#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS0_GPIO6_EDGE_LOW -#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_LOW_BITS _u(0x04000000) -#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_LOW_MSB _u(26) -#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_LOW_LSB _u(26) -#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_HIGH -#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_HIGH_BITS _u(0x02000000) -#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_HIGH_MSB _u(25) -#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_HIGH_LSB _u(25) -#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_LOW -#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_LOW_BITS _u(0x01000000) -#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_LOW_MSB _u(24) -#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_LOW_LSB _u(24) -#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS0_GPIO5_EDGE_HIGH -#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_HIGH_BITS _u(0x00800000) -#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_HIGH_MSB _u(23) -#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_HIGH_LSB _u(23) -#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS0_GPIO5_EDGE_LOW -#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_LOW_BITS _u(0x00400000) -#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_LOW_MSB _u(22) -#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_LOW_LSB _u(22) -#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_HIGH -#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_HIGH_BITS _u(0x00200000) -#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_HIGH_MSB _u(21) -#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_HIGH_LSB _u(21) -#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_LOW -#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_LOW_BITS _u(0x00100000) -#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_LOW_MSB _u(20) -#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_LOW_LSB _u(20) -#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS0_GPIO4_EDGE_HIGH -#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_HIGH_BITS _u(0x00080000) -#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_HIGH_MSB _u(19) -#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_HIGH_LSB _u(19) -#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS0_GPIO4_EDGE_LOW -#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_LOW_BITS _u(0x00040000) -#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_LOW_MSB _u(18) -#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_LOW_LSB _u(18) -#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_HIGH -#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_HIGH_BITS _u(0x00020000) -#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_HIGH_MSB _u(17) -#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_HIGH_LSB _u(17) -#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_LOW -#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_LOW_BITS _u(0x00010000) -#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_LOW_MSB _u(16) -#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_LOW_LSB _u(16) -#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS0_GPIO3_EDGE_HIGH -#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_HIGH_BITS _u(0x00008000) -#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_HIGH_MSB _u(15) -#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_HIGH_LSB _u(15) -#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS0_GPIO3_EDGE_LOW -#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_LOW_BITS _u(0x00004000) -#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_LOW_MSB _u(14) -#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_LOW_LSB _u(14) -#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_HIGH -#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_HIGH_BITS _u(0x00002000) -#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_HIGH_MSB _u(13) -#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_HIGH_LSB _u(13) -#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_LOW -#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_LOW_BITS _u(0x00001000) -#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_LOW_MSB _u(12) -#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_LOW_LSB _u(12) -#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS0_GPIO2_EDGE_HIGH -#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_HIGH_BITS _u(0x00000800) -#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_HIGH_MSB _u(11) -#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_HIGH_LSB _u(11) -#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS0_GPIO2_EDGE_LOW -#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_LOW_BITS _u(0x00000400) -#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_LOW_MSB _u(10) -#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_LOW_LSB _u(10) -#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_HIGH -#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_HIGH_BITS _u(0x00000200) -#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_HIGH_MSB _u(9) -#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_HIGH_LSB _u(9) -#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_LOW -#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_LOW_BITS _u(0x00000100) -#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_LOW_MSB _u(8) -#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_LOW_LSB _u(8) -#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS0_GPIO1_EDGE_HIGH -#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_HIGH_BITS _u(0x00000080) -#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_HIGH_MSB _u(7) -#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_HIGH_LSB _u(7) -#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS0_GPIO1_EDGE_LOW -#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_LOW_BITS _u(0x00000040) -#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_LOW_MSB _u(6) -#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_LOW_LSB _u(6) -#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_HIGH -#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_HIGH_BITS _u(0x00000020) -#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_HIGH_MSB _u(5) -#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_HIGH_LSB _u(5) -#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_LOW -#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_LOW_BITS _u(0x00000010) -#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_LOW_MSB _u(4) -#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_LOW_LSB _u(4) -#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS0_GPIO0_EDGE_HIGH -#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_HIGH_BITS _u(0x00000008) -#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_HIGH_MSB _u(3) -#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_HIGH_LSB _u(3) -#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS0_GPIO0_EDGE_LOW -#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_LOW_BITS _u(0x00000004) -#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_LOW_MSB _u(2) -#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_LOW_LSB _u(2) -#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_HIGH -#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_HIGH_BITS _u(0x00000002) -#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_HIGH_MSB _u(1) -#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_HIGH_LSB _u(1) -#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_LOW -#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_LOW_BITS _u(0x00000001) -#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_LOW_MSB _u(0) -#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_LOW_LSB _u(0) -#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_LOW_ACCESS "RO" -// ============================================================================= -// Register : IO_BANK0_PROC0_INTS1 -// Description : Interrupt status after masking & forcing for proc0 -#define IO_BANK0_PROC0_INTS1_OFFSET _u(0x0000027c) -#define IO_BANK0_PROC0_INTS1_BITS _u(0xffffffff) -#define IO_BANK0_PROC0_INTS1_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS1_GPIO15_EDGE_HIGH -#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_HIGH_BITS _u(0x80000000) -#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_HIGH_MSB _u(31) -#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_HIGH_LSB _u(31) -#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS1_GPIO15_EDGE_LOW -#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_LOW_BITS _u(0x40000000) -#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_LOW_MSB _u(30) -#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_LOW_LSB _u(30) -#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_HIGH -#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_HIGH_BITS _u(0x20000000) -#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_HIGH_MSB _u(29) -#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_HIGH_LSB _u(29) -#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_LOW -#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_LOW_BITS _u(0x10000000) -#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_LOW_MSB _u(28) -#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_LOW_LSB _u(28) -#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS1_GPIO14_EDGE_HIGH -#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_HIGH_BITS _u(0x08000000) -#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_HIGH_MSB _u(27) -#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_HIGH_LSB _u(27) -#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS1_GPIO14_EDGE_LOW -#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_LOW_BITS _u(0x04000000) -#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_LOW_MSB _u(26) -#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_LOW_LSB _u(26) -#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_HIGH -#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_HIGH_BITS _u(0x02000000) -#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_HIGH_MSB _u(25) -#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_HIGH_LSB _u(25) -#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_LOW -#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_LOW_BITS _u(0x01000000) -#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_LOW_MSB _u(24) -#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_LOW_LSB _u(24) -#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS1_GPIO13_EDGE_HIGH -#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_HIGH_BITS _u(0x00800000) -#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_HIGH_MSB _u(23) -#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_HIGH_LSB _u(23) -#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS1_GPIO13_EDGE_LOW -#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_LOW_BITS _u(0x00400000) -#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_LOW_MSB _u(22) -#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_LOW_LSB _u(22) -#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_HIGH -#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_HIGH_BITS _u(0x00200000) -#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_HIGH_MSB _u(21) -#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_HIGH_LSB _u(21) -#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_LOW -#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_LOW_BITS _u(0x00100000) -#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_LOW_MSB _u(20) -#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_LOW_LSB _u(20) -#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS1_GPIO12_EDGE_HIGH -#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_HIGH_BITS _u(0x00080000) -#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_HIGH_MSB _u(19) -#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_HIGH_LSB _u(19) -#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS1_GPIO12_EDGE_LOW -#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_LOW_BITS _u(0x00040000) -#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_LOW_MSB _u(18) -#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_LOW_LSB _u(18) -#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_HIGH -#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_HIGH_BITS _u(0x00020000) -#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_HIGH_MSB _u(17) -#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_HIGH_LSB _u(17) -#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_LOW -#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_LOW_BITS _u(0x00010000) -#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_LOW_MSB _u(16) -#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_LOW_LSB _u(16) -#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS1_GPIO11_EDGE_HIGH -#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_HIGH_BITS _u(0x00008000) -#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_HIGH_MSB _u(15) -#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_HIGH_LSB _u(15) -#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS1_GPIO11_EDGE_LOW -#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_LOW_BITS _u(0x00004000) -#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_LOW_MSB _u(14) -#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_LOW_LSB _u(14) -#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_HIGH -#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_HIGH_BITS _u(0x00002000) -#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_HIGH_MSB _u(13) -#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_HIGH_LSB _u(13) -#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_LOW -#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_LOW_BITS _u(0x00001000) -#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_LOW_MSB _u(12) -#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_LOW_LSB _u(12) -#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS1_GPIO10_EDGE_HIGH -#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_HIGH_BITS _u(0x00000800) -#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_HIGH_MSB _u(11) -#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_HIGH_LSB _u(11) -#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS1_GPIO10_EDGE_LOW -#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_LOW_BITS _u(0x00000400) -#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_LOW_MSB _u(10) -#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_LOW_LSB _u(10) -#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_HIGH -#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_HIGH_BITS _u(0x00000200) -#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_HIGH_MSB _u(9) -#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_HIGH_LSB _u(9) -#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_LOW -#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_LOW_BITS _u(0x00000100) -#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_LOW_MSB _u(8) -#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_LOW_LSB _u(8) -#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS1_GPIO9_EDGE_HIGH -#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_HIGH_BITS _u(0x00000080) -#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_HIGH_MSB _u(7) -#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_HIGH_LSB _u(7) -#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS1_GPIO9_EDGE_LOW -#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_LOW_BITS _u(0x00000040) -#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_LOW_MSB _u(6) -#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_LOW_LSB _u(6) -#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_HIGH -#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_HIGH_BITS _u(0x00000020) -#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_HIGH_MSB _u(5) -#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_HIGH_LSB _u(5) -#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_LOW -#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_LOW_BITS _u(0x00000010) -#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_LOW_MSB _u(4) -#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_LOW_LSB _u(4) -#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS1_GPIO8_EDGE_HIGH -#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_HIGH_BITS _u(0x00000008) -#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_HIGH_MSB _u(3) -#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_HIGH_LSB _u(3) -#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS1_GPIO8_EDGE_LOW -#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_LOW_BITS _u(0x00000004) -#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_LOW_MSB _u(2) -#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_LOW_LSB _u(2) -#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_HIGH -#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_HIGH_BITS _u(0x00000002) -#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_HIGH_MSB _u(1) -#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_HIGH_LSB _u(1) -#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_LOW -#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_LOW_BITS _u(0x00000001) -#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_LOW_MSB _u(0) -#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_LOW_LSB _u(0) -#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_LOW_ACCESS "RO" -// ============================================================================= -// Register : IO_BANK0_PROC0_INTS2 -// Description : Interrupt status after masking & forcing for proc0 -#define IO_BANK0_PROC0_INTS2_OFFSET _u(0x00000280) -#define IO_BANK0_PROC0_INTS2_BITS _u(0xffffffff) -#define IO_BANK0_PROC0_INTS2_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS2_GPIO23_EDGE_HIGH -#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_HIGH_BITS _u(0x80000000) -#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_HIGH_MSB _u(31) -#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_HIGH_LSB _u(31) -#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS2_GPIO23_EDGE_LOW -#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_LOW_BITS _u(0x40000000) -#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_LOW_MSB _u(30) -#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_LOW_LSB _u(30) -#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_HIGH -#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_HIGH_BITS _u(0x20000000) -#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_HIGH_MSB _u(29) -#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_HIGH_LSB _u(29) -#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_LOW -#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_LOW_BITS _u(0x10000000) -#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_LOW_MSB _u(28) -#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_LOW_LSB _u(28) -#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS2_GPIO22_EDGE_HIGH -#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_HIGH_BITS _u(0x08000000) -#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_HIGH_MSB _u(27) -#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_HIGH_LSB _u(27) -#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS2_GPIO22_EDGE_LOW -#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_LOW_BITS _u(0x04000000) -#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_LOW_MSB _u(26) -#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_LOW_LSB _u(26) -#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_HIGH -#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_HIGH_BITS _u(0x02000000) -#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_HIGH_MSB _u(25) -#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_HIGH_LSB _u(25) -#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_LOW -#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_LOW_BITS _u(0x01000000) -#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_LOW_MSB _u(24) -#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_LOW_LSB _u(24) -#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS2_GPIO21_EDGE_HIGH -#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_HIGH_BITS _u(0x00800000) -#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_HIGH_MSB _u(23) -#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_HIGH_LSB _u(23) -#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS2_GPIO21_EDGE_LOW -#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_LOW_BITS _u(0x00400000) -#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_LOW_MSB _u(22) -#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_LOW_LSB _u(22) -#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_HIGH -#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_HIGH_BITS _u(0x00200000) -#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_HIGH_MSB _u(21) -#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_HIGH_LSB _u(21) -#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_LOW -#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_LOW_BITS _u(0x00100000) -#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_LOW_MSB _u(20) -#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_LOW_LSB _u(20) -#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS2_GPIO20_EDGE_HIGH -#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_HIGH_BITS _u(0x00080000) -#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_HIGH_MSB _u(19) -#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_HIGH_LSB _u(19) -#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS2_GPIO20_EDGE_LOW -#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_LOW_BITS _u(0x00040000) -#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_LOW_MSB _u(18) -#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_LOW_LSB _u(18) -#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_HIGH -#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_HIGH_BITS _u(0x00020000) -#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_HIGH_MSB _u(17) -#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_HIGH_LSB _u(17) -#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_LOW -#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_LOW_BITS _u(0x00010000) -#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_LOW_MSB _u(16) -#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_LOW_LSB _u(16) -#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS2_GPIO19_EDGE_HIGH -#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_HIGH_BITS _u(0x00008000) -#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_HIGH_MSB _u(15) -#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_HIGH_LSB _u(15) -#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS2_GPIO19_EDGE_LOW -#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_LOW_BITS _u(0x00004000) -#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_LOW_MSB _u(14) -#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_LOW_LSB _u(14) -#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_HIGH -#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_HIGH_BITS _u(0x00002000) -#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_HIGH_MSB _u(13) -#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_HIGH_LSB _u(13) -#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_LOW -#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_LOW_BITS _u(0x00001000) -#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_LOW_MSB _u(12) -#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_LOW_LSB _u(12) -#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS2_GPIO18_EDGE_HIGH -#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_HIGH_BITS _u(0x00000800) -#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_HIGH_MSB _u(11) -#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_HIGH_LSB _u(11) -#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS2_GPIO18_EDGE_LOW -#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_LOW_BITS _u(0x00000400) -#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_LOW_MSB _u(10) -#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_LOW_LSB _u(10) -#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_HIGH -#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_HIGH_BITS _u(0x00000200) -#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_HIGH_MSB _u(9) -#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_HIGH_LSB _u(9) -#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_LOW -#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_LOW_BITS _u(0x00000100) -#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_LOW_MSB _u(8) -#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_LOW_LSB _u(8) -#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS2_GPIO17_EDGE_HIGH -#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_HIGH_BITS _u(0x00000080) -#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_HIGH_MSB _u(7) -#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_HIGH_LSB _u(7) -#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS2_GPIO17_EDGE_LOW -#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_LOW_BITS _u(0x00000040) -#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_LOW_MSB _u(6) -#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_LOW_LSB _u(6) -#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_HIGH -#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_HIGH_BITS _u(0x00000020) -#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_HIGH_MSB _u(5) -#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_HIGH_LSB _u(5) -#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_LOW -#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_LOW_BITS _u(0x00000010) -#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_LOW_MSB _u(4) -#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_LOW_LSB _u(4) -#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS2_GPIO16_EDGE_HIGH -#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_HIGH_BITS _u(0x00000008) -#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_HIGH_MSB _u(3) -#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_HIGH_LSB _u(3) -#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS2_GPIO16_EDGE_LOW -#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_LOW_BITS _u(0x00000004) -#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_LOW_MSB _u(2) -#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_LOW_LSB _u(2) -#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_HIGH -#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_HIGH_BITS _u(0x00000002) -#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_HIGH_MSB _u(1) -#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_HIGH_LSB _u(1) -#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_LOW -#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_LOW_BITS _u(0x00000001) -#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_LOW_MSB _u(0) -#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_LOW_LSB _u(0) -#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_LOW_ACCESS "RO" -// ============================================================================= -// Register : IO_BANK0_PROC0_INTS3 -// Description : Interrupt status after masking & forcing for proc0 -#define IO_BANK0_PROC0_INTS3_OFFSET _u(0x00000284) -#define IO_BANK0_PROC0_INTS3_BITS _u(0xffffffff) -#define IO_BANK0_PROC0_INTS3_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS3_GPIO31_EDGE_HIGH -#define IO_BANK0_PROC0_INTS3_GPIO31_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS3_GPIO31_EDGE_HIGH_BITS _u(0x80000000) -#define IO_BANK0_PROC0_INTS3_GPIO31_EDGE_HIGH_MSB _u(31) -#define IO_BANK0_PROC0_INTS3_GPIO31_EDGE_HIGH_LSB _u(31) -#define IO_BANK0_PROC0_INTS3_GPIO31_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS3_GPIO31_EDGE_LOW -#define IO_BANK0_PROC0_INTS3_GPIO31_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS3_GPIO31_EDGE_LOW_BITS _u(0x40000000) -#define IO_BANK0_PROC0_INTS3_GPIO31_EDGE_LOW_MSB _u(30) -#define IO_BANK0_PROC0_INTS3_GPIO31_EDGE_LOW_LSB _u(30) -#define IO_BANK0_PROC0_INTS3_GPIO31_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS3_GPIO31_LEVEL_HIGH -#define IO_BANK0_PROC0_INTS3_GPIO31_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS3_GPIO31_LEVEL_HIGH_BITS _u(0x20000000) -#define IO_BANK0_PROC0_INTS3_GPIO31_LEVEL_HIGH_MSB _u(29) -#define IO_BANK0_PROC0_INTS3_GPIO31_LEVEL_HIGH_LSB _u(29) -#define IO_BANK0_PROC0_INTS3_GPIO31_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS3_GPIO31_LEVEL_LOW -#define IO_BANK0_PROC0_INTS3_GPIO31_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS3_GPIO31_LEVEL_LOW_BITS _u(0x10000000) -#define IO_BANK0_PROC0_INTS3_GPIO31_LEVEL_LOW_MSB _u(28) -#define IO_BANK0_PROC0_INTS3_GPIO31_LEVEL_LOW_LSB _u(28) -#define IO_BANK0_PROC0_INTS3_GPIO31_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS3_GPIO30_EDGE_HIGH -#define IO_BANK0_PROC0_INTS3_GPIO30_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS3_GPIO30_EDGE_HIGH_BITS _u(0x08000000) -#define IO_BANK0_PROC0_INTS3_GPIO30_EDGE_HIGH_MSB _u(27) -#define IO_BANK0_PROC0_INTS3_GPIO30_EDGE_HIGH_LSB _u(27) -#define IO_BANK0_PROC0_INTS3_GPIO30_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS3_GPIO30_EDGE_LOW -#define IO_BANK0_PROC0_INTS3_GPIO30_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS3_GPIO30_EDGE_LOW_BITS _u(0x04000000) -#define IO_BANK0_PROC0_INTS3_GPIO30_EDGE_LOW_MSB _u(26) -#define IO_BANK0_PROC0_INTS3_GPIO30_EDGE_LOW_LSB _u(26) -#define IO_BANK0_PROC0_INTS3_GPIO30_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS3_GPIO30_LEVEL_HIGH -#define IO_BANK0_PROC0_INTS3_GPIO30_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS3_GPIO30_LEVEL_HIGH_BITS _u(0x02000000) -#define IO_BANK0_PROC0_INTS3_GPIO30_LEVEL_HIGH_MSB _u(25) -#define IO_BANK0_PROC0_INTS3_GPIO30_LEVEL_HIGH_LSB _u(25) -#define IO_BANK0_PROC0_INTS3_GPIO30_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS3_GPIO30_LEVEL_LOW -#define IO_BANK0_PROC0_INTS3_GPIO30_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS3_GPIO30_LEVEL_LOW_BITS _u(0x01000000) -#define IO_BANK0_PROC0_INTS3_GPIO30_LEVEL_LOW_MSB _u(24) -#define IO_BANK0_PROC0_INTS3_GPIO30_LEVEL_LOW_LSB _u(24) -#define IO_BANK0_PROC0_INTS3_GPIO30_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS3_GPIO29_EDGE_HIGH -#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_HIGH_BITS _u(0x00800000) -#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_HIGH_MSB _u(23) -#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_HIGH_LSB _u(23) -#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS3_GPIO29_EDGE_LOW -#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_LOW_BITS _u(0x00400000) -#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_LOW_MSB _u(22) -#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_LOW_LSB _u(22) -#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_HIGH -#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_HIGH_BITS _u(0x00200000) -#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_HIGH_MSB _u(21) -#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_HIGH_LSB _u(21) -#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_LOW -#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_LOW_BITS _u(0x00100000) -#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_LOW_MSB _u(20) -#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_LOW_LSB _u(20) -#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS3_GPIO28_EDGE_HIGH -#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_HIGH_BITS _u(0x00080000) -#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_HIGH_MSB _u(19) -#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_HIGH_LSB _u(19) -#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS3_GPIO28_EDGE_LOW -#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_LOW_BITS _u(0x00040000) -#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_LOW_MSB _u(18) -#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_LOW_LSB _u(18) -#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_HIGH -#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_HIGH_BITS _u(0x00020000) -#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_HIGH_MSB _u(17) -#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_HIGH_LSB _u(17) -#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_LOW -#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_LOW_BITS _u(0x00010000) -#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_LOW_MSB _u(16) -#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_LOW_LSB _u(16) -#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS3_GPIO27_EDGE_HIGH -#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_HIGH_BITS _u(0x00008000) -#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_HIGH_MSB _u(15) -#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_HIGH_LSB _u(15) -#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS3_GPIO27_EDGE_LOW -#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_LOW_BITS _u(0x00004000) -#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_LOW_MSB _u(14) -#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_LOW_LSB _u(14) -#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_HIGH -#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_HIGH_BITS _u(0x00002000) -#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_HIGH_MSB _u(13) -#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_HIGH_LSB _u(13) -#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_LOW -#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_LOW_BITS _u(0x00001000) -#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_LOW_MSB _u(12) -#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_LOW_LSB _u(12) -#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS3_GPIO26_EDGE_HIGH -#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_HIGH_BITS _u(0x00000800) -#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_HIGH_MSB _u(11) -#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_HIGH_LSB _u(11) -#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS3_GPIO26_EDGE_LOW -#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_LOW_BITS _u(0x00000400) -#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_LOW_MSB _u(10) -#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_LOW_LSB _u(10) -#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_HIGH -#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_HIGH_BITS _u(0x00000200) -#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_HIGH_MSB _u(9) -#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_HIGH_LSB _u(9) -#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_LOW -#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_LOW_BITS _u(0x00000100) -#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_LOW_MSB _u(8) -#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_LOW_LSB _u(8) -#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS3_GPIO25_EDGE_HIGH -#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_HIGH_BITS _u(0x00000080) -#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_HIGH_MSB _u(7) -#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_HIGH_LSB _u(7) -#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS3_GPIO25_EDGE_LOW -#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_LOW_BITS _u(0x00000040) -#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_LOW_MSB _u(6) -#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_LOW_LSB _u(6) -#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_HIGH -#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_HIGH_BITS _u(0x00000020) -#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_HIGH_MSB _u(5) -#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_HIGH_LSB _u(5) -#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_LOW -#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_LOW_BITS _u(0x00000010) -#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_LOW_MSB _u(4) -#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_LOW_LSB _u(4) -#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS3_GPIO24_EDGE_HIGH -#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_HIGH_BITS _u(0x00000008) -#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_HIGH_MSB _u(3) -#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_HIGH_LSB _u(3) -#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS3_GPIO24_EDGE_LOW -#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_LOW_BITS _u(0x00000004) -#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_LOW_MSB _u(2) -#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_LOW_LSB _u(2) -#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_HIGH -#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_HIGH_BITS _u(0x00000002) -#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_HIGH_MSB _u(1) -#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_HIGH_LSB _u(1) -#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_LOW -#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_LOW_BITS _u(0x00000001) -#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_LOW_MSB _u(0) -#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_LOW_LSB _u(0) -#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_LOW_ACCESS "RO" -// ============================================================================= -// Register : IO_BANK0_PROC0_INTS4 -// Description : Interrupt status after masking & forcing for proc0 -#define IO_BANK0_PROC0_INTS4_OFFSET _u(0x00000288) -#define IO_BANK0_PROC0_INTS4_BITS _u(0xffffffff) -#define IO_BANK0_PROC0_INTS4_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS4_GPIO39_EDGE_HIGH -#define IO_BANK0_PROC0_INTS4_GPIO39_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS4_GPIO39_EDGE_HIGH_BITS _u(0x80000000) -#define IO_BANK0_PROC0_INTS4_GPIO39_EDGE_HIGH_MSB _u(31) -#define IO_BANK0_PROC0_INTS4_GPIO39_EDGE_HIGH_LSB _u(31) -#define IO_BANK0_PROC0_INTS4_GPIO39_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS4_GPIO39_EDGE_LOW -#define IO_BANK0_PROC0_INTS4_GPIO39_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS4_GPIO39_EDGE_LOW_BITS _u(0x40000000) -#define IO_BANK0_PROC0_INTS4_GPIO39_EDGE_LOW_MSB _u(30) -#define IO_BANK0_PROC0_INTS4_GPIO39_EDGE_LOW_LSB _u(30) -#define IO_BANK0_PROC0_INTS4_GPIO39_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS4_GPIO39_LEVEL_HIGH -#define IO_BANK0_PROC0_INTS4_GPIO39_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS4_GPIO39_LEVEL_HIGH_BITS _u(0x20000000) -#define IO_BANK0_PROC0_INTS4_GPIO39_LEVEL_HIGH_MSB _u(29) -#define IO_BANK0_PROC0_INTS4_GPIO39_LEVEL_HIGH_LSB _u(29) -#define IO_BANK0_PROC0_INTS4_GPIO39_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS4_GPIO39_LEVEL_LOW -#define IO_BANK0_PROC0_INTS4_GPIO39_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS4_GPIO39_LEVEL_LOW_BITS _u(0x10000000) -#define IO_BANK0_PROC0_INTS4_GPIO39_LEVEL_LOW_MSB _u(28) -#define IO_BANK0_PROC0_INTS4_GPIO39_LEVEL_LOW_LSB _u(28) -#define IO_BANK0_PROC0_INTS4_GPIO39_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS4_GPIO38_EDGE_HIGH -#define IO_BANK0_PROC0_INTS4_GPIO38_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS4_GPIO38_EDGE_HIGH_BITS _u(0x08000000) -#define IO_BANK0_PROC0_INTS4_GPIO38_EDGE_HIGH_MSB _u(27) -#define IO_BANK0_PROC0_INTS4_GPIO38_EDGE_HIGH_LSB _u(27) -#define IO_BANK0_PROC0_INTS4_GPIO38_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS4_GPIO38_EDGE_LOW -#define IO_BANK0_PROC0_INTS4_GPIO38_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS4_GPIO38_EDGE_LOW_BITS _u(0x04000000) -#define IO_BANK0_PROC0_INTS4_GPIO38_EDGE_LOW_MSB _u(26) -#define IO_BANK0_PROC0_INTS4_GPIO38_EDGE_LOW_LSB _u(26) -#define IO_BANK0_PROC0_INTS4_GPIO38_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS4_GPIO38_LEVEL_HIGH -#define IO_BANK0_PROC0_INTS4_GPIO38_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS4_GPIO38_LEVEL_HIGH_BITS _u(0x02000000) -#define IO_BANK0_PROC0_INTS4_GPIO38_LEVEL_HIGH_MSB _u(25) -#define IO_BANK0_PROC0_INTS4_GPIO38_LEVEL_HIGH_LSB _u(25) -#define IO_BANK0_PROC0_INTS4_GPIO38_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS4_GPIO38_LEVEL_LOW -#define IO_BANK0_PROC0_INTS4_GPIO38_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS4_GPIO38_LEVEL_LOW_BITS _u(0x01000000) -#define IO_BANK0_PROC0_INTS4_GPIO38_LEVEL_LOW_MSB _u(24) -#define IO_BANK0_PROC0_INTS4_GPIO38_LEVEL_LOW_LSB _u(24) -#define IO_BANK0_PROC0_INTS4_GPIO38_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS4_GPIO37_EDGE_HIGH -#define IO_BANK0_PROC0_INTS4_GPIO37_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS4_GPIO37_EDGE_HIGH_BITS _u(0x00800000) -#define IO_BANK0_PROC0_INTS4_GPIO37_EDGE_HIGH_MSB _u(23) -#define IO_BANK0_PROC0_INTS4_GPIO37_EDGE_HIGH_LSB _u(23) -#define IO_BANK0_PROC0_INTS4_GPIO37_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS4_GPIO37_EDGE_LOW -#define IO_BANK0_PROC0_INTS4_GPIO37_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS4_GPIO37_EDGE_LOW_BITS _u(0x00400000) -#define IO_BANK0_PROC0_INTS4_GPIO37_EDGE_LOW_MSB _u(22) -#define IO_BANK0_PROC0_INTS4_GPIO37_EDGE_LOW_LSB _u(22) -#define IO_BANK0_PROC0_INTS4_GPIO37_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS4_GPIO37_LEVEL_HIGH -#define IO_BANK0_PROC0_INTS4_GPIO37_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS4_GPIO37_LEVEL_HIGH_BITS _u(0x00200000) -#define IO_BANK0_PROC0_INTS4_GPIO37_LEVEL_HIGH_MSB _u(21) -#define IO_BANK0_PROC0_INTS4_GPIO37_LEVEL_HIGH_LSB _u(21) -#define IO_BANK0_PROC0_INTS4_GPIO37_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS4_GPIO37_LEVEL_LOW -#define IO_BANK0_PROC0_INTS4_GPIO37_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS4_GPIO37_LEVEL_LOW_BITS _u(0x00100000) -#define IO_BANK0_PROC0_INTS4_GPIO37_LEVEL_LOW_MSB _u(20) -#define IO_BANK0_PROC0_INTS4_GPIO37_LEVEL_LOW_LSB _u(20) -#define IO_BANK0_PROC0_INTS4_GPIO37_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS4_GPIO36_EDGE_HIGH -#define IO_BANK0_PROC0_INTS4_GPIO36_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS4_GPIO36_EDGE_HIGH_BITS _u(0x00080000) -#define IO_BANK0_PROC0_INTS4_GPIO36_EDGE_HIGH_MSB _u(19) -#define IO_BANK0_PROC0_INTS4_GPIO36_EDGE_HIGH_LSB _u(19) -#define IO_BANK0_PROC0_INTS4_GPIO36_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS4_GPIO36_EDGE_LOW -#define IO_BANK0_PROC0_INTS4_GPIO36_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS4_GPIO36_EDGE_LOW_BITS _u(0x00040000) -#define IO_BANK0_PROC0_INTS4_GPIO36_EDGE_LOW_MSB _u(18) -#define IO_BANK0_PROC0_INTS4_GPIO36_EDGE_LOW_LSB _u(18) -#define IO_BANK0_PROC0_INTS4_GPIO36_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS4_GPIO36_LEVEL_HIGH -#define IO_BANK0_PROC0_INTS4_GPIO36_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS4_GPIO36_LEVEL_HIGH_BITS _u(0x00020000) -#define IO_BANK0_PROC0_INTS4_GPIO36_LEVEL_HIGH_MSB _u(17) -#define IO_BANK0_PROC0_INTS4_GPIO36_LEVEL_HIGH_LSB _u(17) -#define IO_BANK0_PROC0_INTS4_GPIO36_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS4_GPIO36_LEVEL_LOW -#define IO_BANK0_PROC0_INTS4_GPIO36_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS4_GPIO36_LEVEL_LOW_BITS _u(0x00010000) -#define IO_BANK0_PROC0_INTS4_GPIO36_LEVEL_LOW_MSB _u(16) -#define IO_BANK0_PROC0_INTS4_GPIO36_LEVEL_LOW_LSB _u(16) -#define IO_BANK0_PROC0_INTS4_GPIO36_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS4_GPIO35_EDGE_HIGH -#define IO_BANK0_PROC0_INTS4_GPIO35_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS4_GPIO35_EDGE_HIGH_BITS _u(0x00008000) -#define IO_BANK0_PROC0_INTS4_GPIO35_EDGE_HIGH_MSB _u(15) -#define IO_BANK0_PROC0_INTS4_GPIO35_EDGE_HIGH_LSB _u(15) -#define IO_BANK0_PROC0_INTS4_GPIO35_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS4_GPIO35_EDGE_LOW -#define IO_BANK0_PROC0_INTS4_GPIO35_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS4_GPIO35_EDGE_LOW_BITS _u(0x00004000) -#define IO_BANK0_PROC0_INTS4_GPIO35_EDGE_LOW_MSB _u(14) -#define IO_BANK0_PROC0_INTS4_GPIO35_EDGE_LOW_LSB _u(14) -#define IO_BANK0_PROC0_INTS4_GPIO35_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS4_GPIO35_LEVEL_HIGH -#define IO_BANK0_PROC0_INTS4_GPIO35_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS4_GPIO35_LEVEL_HIGH_BITS _u(0x00002000) -#define IO_BANK0_PROC0_INTS4_GPIO35_LEVEL_HIGH_MSB _u(13) -#define IO_BANK0_PROC0_INTS4_GPIO35_LEVEL_HIGH_LSB _u(13) -#define IO_BANK0_PROC0_INTS4_GPIO35_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS4_GPIO35_LEVEL_LOW -#define IO_BANK0_PROC0_INTS4_GPIO35_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS4_GPIO35_LEVEL_LOW_BITS _u(0x00001000) -#define IO_BANK0_PROC0_INTS4_GPIO35_LEVEL_LOW_MSB _u(12) -#define IO_BANK0_PROC0_INTS4_GPIO35_LEVEL_LOW_LSB _u(12) -#define IO_BANK0_PROC0_INTS4_GPIO35_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS4_GPIO34_EDGE_HIGH -#define IO_BANK0_PROC0_INTS4_GPIO34_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS4_GPIO34_EDGE_HIGH_BITS _u(0x00000800) -#define IO_BANK0_PROC0_INTS4_GPIO34_EDGE_HIGH_MSB _u(11) -#define IO_BANK0_PROC0_INTS4_GPIO34_EDGE_HIGH_LSB _u(11) -#define IO_BANK0_PROC0_INTS4_GPIO34_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS4_GPIO34_EDGE_LOW -#define IO_BANK0_PROC0_INTS4_GPIO34_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS4_GPIO34_EDGE_LOW_BITS _u(0x00000400) -#define IO_BANK0_PROC0_INTS4_GPIO34_EDGE_LOW_MSB _u(10) -#define IO_BANK0_PROC0_INTS4_GPIO34_EDGE_LOW_LSB _u(10) -#define IO_BANK0_PROC0_INTS4_GPIO34_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS4_GPIO34_LEVEL_HIGH -#define IO_BANK0_PROC0_INTS4_GPIO34_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS4_GPIO34_LEVEL_HIGH_BITS _u(0x00000200) -#define IO_BANK0_PROC0_INTS4_GPIO34_LEVEL_HIGH_MSB _u(9) -#define IO_BANK0_PROC0_INTS4_GPIO34_LEVEL_HIGH_LSB _u(9) -#define IO_BANK0_PROC0_INTS4_GPIO34_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS4_GPIO34_LEVEL_LOW -#define IO_BANK0_PROC0_INTS4_GPIO34_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS4_GPIO34_LEVEL_LOW_BITS _u(0x00000100) -#define IO_BANK0_PROC0_INTS4_GPIO34_LEVEL_LOW_MSB _u(8) -#define IO_BANK0_PROC0_INTS4_GPIO34_LEVEL_LOW_LSB _u(8) -#define IO_BANK0_PROC0_INTS4_GPIO34_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS4_GPIO33_EDGE_HIGH -#define IO_BANK0_PROC0_INTS4_GPIO33_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS4_GPIO33_EDGE_HIGH_BITS _u(0x00000080) -#define IO_BANK0_PROC0_INTS4_GPIO33_EDGE_HIGH_MSB _u(7) -#define IO_BANK0_PROC0_INTS4_GPIO33_EDGE_HIGH_LSB _u(7) -#define IO_BANK0_PROC0_INTS4_GPIO33_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS4_GPIO33_EDGE_LOW -#define IO_BANK0_PROC0_INTS4_GPIO33_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS4_GPIO33_EDGE_LOW_BITS _u(0x00000040) -#define IO_BANK0_PROC0_INTS4_GPIO33_EDGE_LOW_MSB _u(6) -#define IO_BANK0_PROC0_INTS4_GPIO33_EDGE_LOW_LSB _u(6) -#define IO_BANK0_PROC0_INTS4_GPIO33_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS4_GPIO33_LEVEL_HIGH -#define IO_BANK0_PROC0_INTS4_GPIO33_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS4_GPIO33_LEVEL_HIGH_BITS _u(0x00000020) -#define IO_BANK0_PROC0_INTS4_GPIO33_LEVEL_HIGH_MSB _u(5) -#define IO_BANK0_PROC0_INTS4_GPIO33_LEVEL_HIGH_LSB _u(5) -#define IO_BANK0_PROC0_INTS4_GPIO33_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS4_GPIO33_LEVEL_LOW -#define IO_BANK0_PROC0_INTS4_GPIO33_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS4_GPIO33_LEVEL_LOW_BITS _u(0x00000010) -#define IO_BANK0_PROC0_INTS4_GPIO33_LEVEL_LOW_MSB _u(4) -#define IO_BANK0_PROC0_INTS4_GPIO33_LEVEL_LOW_LSB _u(4) -#define IO_BANK0_PROC0_INTS4_GPIO33_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS4_GPIO32_EDGE_HIGH -#define IO_BANK0_PROC0_INTS4_GPIO32_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS4_GPIO32_EDGE_HIGH_BITS _u(0x00000008) -#define IO_BANK0_PROC0_INTS4_GPIO32_EDGE_HIGH_MSB _u(3) -#define IO_BANK0_PROC0_INTS4_GPIO32_EDGE_HIGH_LSB _u(3) -#define IO_BANK0_PROC0_INTS4_GPIO32_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS4_GPIO32_EDGE_LOW -#define IO_BANK0_PROC0_INTS4_GPIO32_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS4_GPIO32_EDGE_LOW_BITS _u(0x00000004) -#define IO_BANK0_PROC0_INTS4_GPIO32_EDGE_LOW_MSB _u(2) -#define IO_BANK0_PROC0_INTS4_GPIO32_EDGE_LOW_LSB _u(2) -#define IO_BANK0_PROC0_INTS4_GPIO32_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS4_GPIO32_LEVEL_HIGH -#define IO_BANK0_PROC0_INTS4_GPIO32_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS4_GPIO32_LEVEL_HIGH_BITS _u(0x00000002) -#define IO_BANK0_PROC0_INTS4_GPIO32_LEVEL_HIGH_MSB _u(1) -#define IO_BANK0_PROC0_INTS4_GPIO32_LEVEL_HIGH_LSB _u(1) -#define IO_BANK0_PROC0_INTS4_GPIO32_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS4_GPIO32_LEVEL_LOW -#define IO_BANK0_PROC0_INTS4_GPIO32_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS4_GPIO32_LEVEL_LOW_BITS _u(0x00000001) -#define IO_BANK0_PROC0_INTS4_GPIO32_LEVEL_LOW_MSB _u(0) -#define IO_BANK0_PROC0_INTS4_GPIO32_LEVEL_LOW_LSB _u(0) -#define IO_BANK0_PROC0_INTS4_GPIO32_LEVEL_LOW_ACCESS "RO" -// ============================================================================= -// Register : IO_BANK0_PROC0_INTS5 -// Description : Interrupt status after masking & forcing for proc0 -#define IO_BANK0_PROC0_INTS5_OFFSET _u(0x0000028c) -#define IO_BANK0_PROC0_INTS5_BITS _u(0xffffffff) -#define IO_BANK0_PROC0_INTS5_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS5_GPIO47_EDGE_HIGH -#define IO_BANK0_PROC0_INTS5_GPIO47_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS5_GPIO47_EDGE_HIGH_BITS _u(0x80000000) -#define IO_BANK0_PROC0_INTS5_GPIO47_EDGE_HIGH_MSB _u(31) -#define IO_BANK0_PROC0_INTS5_GPIO47_EDGE_HIGH_LSB _u(31) -#define IO_BANK0_PROC0_INTS5_GPIO47_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS5_GPIO47_EDGE_LOW -#define IO_BANK0_PROC0_INTS5_GPIO47_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS5_GPIO47_EDGE_LOW_BITS _u(0x40000000) -#define IO_BANK0_PROC0_INTS5_GPIO47_EDGE_LOW_MSB _u(30) -#define IO_BANK0_PROC0_INTS5_GPIO47_EDGE_LOW_LSB _u(30) -#define IO_BANK0_PROC0_INTS5_GPIO47_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS5_GPIO47_LEVEL_HIGH -#define IO_BANK0_PROC0_INTS5_GPIO47_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS5_GPIO47_LEVEL_HIGH_BITS _u(0x20000000) -#define IO_BANK0_PROC0_INTS5_GPIO47_LEVEL_HIGH_MSB _u(29) -#define IO_BANK0_PROC0_INTS5_GPIO47_LEVEL_HIGH_LSB _u(29) -#define IO_BANK0_PROC0_INTS5_GPIO47_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS5_GPIO47_LEVEL_LOW -#define IO_BANK0_PROC0_INTS5_GPIO47_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS5_GPIO47_LEVEL_LOW_BITS _u(0x10000000) -#define IO_BANK0_PROC0_INTS5_GPIO47_LEVEL_LOW_MSB _u(28) -#define IO_BANK0_PROC0_INTS5_GPIO47_LEVEL_LOW_LSB _u(28) -#define IO_BANK0_PROC0_INTS5_GPIO47_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS5_GPIO46_EDGE_HIGH -#define IO_BANK0_PROC0_INTS5_GPIO46_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS5_GPIO46_EDGE_HIGH_BITS _u(0x08000000) -#define IO_BANK0_PROC0_INTS5_GPIO46_EDGE_HIGH_MSB _u(27) -#define IO_BANK0_PROC0_INTS5_GPIO46_EDGE_HIGH_LSB _u(27) -#define IO_BANK0_PROC0_INTS5_GPIO46_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS5_GPIO46_EDGE_LOW -#define IO_BANK0_PROC0_INTS5_GPIO46_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS5_GPIO46_EDGE_LOW_BITS _u(0x04000000) -#define IO_BANK0_PROC0_INTS5_GPIO46_EDGE_LOW_MSB _u(26) -#define IO_BANK0_PROC0_INTS5_GPIO46_EDGE_LOW_LSB _u(26) -#define IO_BANK0_PROC0_INTS5_GPIO46_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS5_GPIO46_LEVEL_HIGH -#define IO_BANK0_PROC0_INTS5_GPIO46_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS5_GPIO46_LEVEL_HIGH_BITS _u(0x02000000) -#define IO_BANK0_PROC0_INTS5_GPIO46_LEVEL_HIGH_MSB _u(25) -#define IO_BANK0_PROC0_INTS5_GPIO46_LEVEL_HIGH_LSB _u(25) -#define IO_BANK0_PROC0_INTS5_GPIO46_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS5_GPIO46_LEVEL_LOW -#define IO_BANK0_PROC0_INTS5_GPIO46_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS5_GPIO46_LEVEL_LOW_BITS _u(0x01000000) -#define IO_BANK0_PROC0_INTS5_GPIO46_LEVEL_LOW_MSB _u(24) -#define IO_BANK0_PROC0_INTS5_GPIO46_LEVEL_LOW_LSB _u(24) -#define IO_BANK0_PROC0_INTS5_GPIO46_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS5_GPIO45_EDGE_HIGH -#define IO_BANK0_PROC0_INTS5_GPIO45_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS5_GPIO45_EDGE_HIGH_BITS _u(0x00800000) -#define IO_BANK0_PROC0_INTS5_GPIO45_EDGE_HIGH_MSB _u(23) -#define IO_BANK0_PROC0_INTS5_GPIO45_EDGE_HIGH_LSB _u(23) -#define IO_BANK0_PROC0_INTS5_GPIO45_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS5_GPIO45_EDGE_LOW -#define IO_BANK0_PROC0_INTS5_GPIO45_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS5_GPIO45_EDGE_LOW_BITS _u(0x00400000) -#define IO_BANK0_PROC0_INTS5_GPIO45_EDGE_LOW_MSB _u(22) -#define IO_BANK0_PROC0_INTS5_GPIO45_EDGE_LOW_LSB _u(22) -#define IO_BANK0_PROC0_INTS5_GPIO45_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS5_GPIO45_LEVEL_HIGH -#define IO_BANK0_PROC0_INTS5_GPIO45_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS5_GPIO45_LEVEL_HIGH_BITS _u(0x00200000) -#define IO_BANK0_PROC0_INTS5_GPIO45_LEVEL_HIGH_MSB _u(21) -#define IO_BANK0_PROC0_INTS5_GPIO45_LEVEL_HIGH_LSB _u(21) -#define IO_BANK0_PROC0_INTS5_GPIO45_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS5_GPIO45_LEVEL_LOW -#define IO_BANK0_PROC0_INTS5_GPIO45_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS5_GPIO45_LEVEL_LOW_BITS _u(0x00100000) -#define IO_BANK0_PROC0_INTS5_GPIO45_LEVEL_LOW_MSB _u(20) -#define IO_BANK0_PROC0_INTS5_GPIO45_LEVEL_LOW_LSB _u(20) -#define IO_BANK0_PROC0_INTS5_GPIO45_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS5_GPIO44_EDGE_HIGH -#define IO_BANK0_PROC0_INTS5_GPIO44_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS5_GPIO44_EDGE_HIGH_BITS _u(0x00080000) -#define IO_BANK0_PROC0_INTS5_GPIO44_EDGE_HIGH_MSB _u(19) -#define IO_BANK0_PROC0_INTS5_GPIO44_EDGE_HIGH_LSB _u(19) -#define IO_BANK0_PROC0_INTS5_GPIO44_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS5_GPIO44_EDGE_LOW -#define IO_BANK0_PROC0_INTS5_GPIO44_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS5_GPIO44_EDGE_LOW_BITS _u(0x00040000) -#define IO_BANK0_PROC0_INTS5_GPIO44_EDGE_LOW_MSB _u(18) -#define IO_BANK0_PROC0_INTS5_GPIO44_EDGE_LOW_LSB _u(18) -#define IO_BANK0_PROC0_INTS5_GPIO44_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS5_GPIO44_LEVEL_HIGH -#define IO_BANK0_PROC0_INTS5_GPIO44_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS5_GPIO44_LEVEL_HIGH_BITS _u(0x00020000) -#define IO_BANK0_PROC0_INTS5_GPIO44_LEVEL_HIGH_MSB _u(17) -#define IO_BANK0_PROC0_INTS5_GPIO44_LEVEL_HIGH_LSB _u(17) -#define IO_BANK0_PROC0_INTS5_GPIO44_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS5_GPIO44_LEVEL_LOW -#define IO_BANK0_PROC0_INTS5_GPIO44_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS5_GPIO44_LEVEL_LOW_BITS _u(0x00010000) -#define IO_BANK0_PROC0_INTS5_GPIO44_LEVEL_LOW_MSB _u(16) -#define IO_BANK0_PROC0_INTS5_GPIO44_LEVEL_LOW_LSB _u(16) -#define IO_BANK0_PROC0_INTS5_GPIO44_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS5_GPIO43_EDGE_HIGH -#define IO_BANK0_PROC0_INTS5_GPIO43_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS5_GPIO43_EDGE_HIGH_BITS _u(0x00008000) -#define IO_BANK0_PROC0_INTS5_GPIO43_EDGE_HIGH_MSB _u(15) -#define IO_BANK0_PROC0_INTS5_GPIO43_EDGE_HIGH_LSB _u(15) -#define IO_BANK0_PROC0_INTS5_GPIO43_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS5_GPIO43_EDGE_LOW -#define IO_BANK0_PROC0_INTS5_GPIO43_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS5_GPIO43_EDGE_LOW_BITS _u(0x00004000) -#define IO_BANK0_PROC0_INTS5_GPIO43_EDGE_LOW_MSB _u(14) -#define IO_BANK0_PROC0_INTS5_GPIO43_EDGE_LOW_LSB _u(14) -#define IO_BANK0_PROC0_INTS5_GPIO43_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS5_GPIO43_LEVEL_HIGH -#define IO_BANK0_PROC0_INTS5_GPIO43_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS5_GPIO43_LEVEL_HIGH_BITS _u(0x00002000) -#define IO_BANK0_PROC0_INTS5_GPIO43_LEVEL_HIGH_MSB _u(13) -#define IO_BANK0_PROC0_INTS5_GPIO43_LEVEL_HIGH_LSB _u(13) -#define IO_BANK0_PROC0_INTS5_GPIO43_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS5_GPIO43_LEVEL_LOW -#define IO_BANK0_PROC0_INTS5_GPIO43_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS5_GPIO43_LEVEL_LOW_BITS _u(0x00001000) -#define IO_BANK0_PROC0_INTS5_GPIO43_LEVEL_LOW_MSB _u(12) -#define IO_BANK0_PROC0_INTS5_GPIO43_LEVEL_LOW_LSB _u(12) -#define IO_BANK0_PROC0_INTS5_GPIO43_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS5_GPIO42_EDGE_HIGH -#define IO_BANK0_PROC0_INTS5_GPIO42_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS5_GPIO42_EDGE_HIGH_BITS _u(0x00000800) -#define IO_BANK0_PROC0_INTS5_GPIO42_EDGE_HIGH_MSB _u(11) -#define IO_BANK0_PROC0_INTS5_GPIO42_EDGE_HIGH_LSB _u(11) -#define IO_BANK0_PROC0_INTS5_GPIO42_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS5_GPIO42_EDGE_LOW -#define IO_BANK0_PROC0_INTS5_GPIO42_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS5_GPIO42_EDGE_LOW_BITS _u(0x00000400) -#define IO_BANK0_PROC0_INTS5_GPIO42_EDGE_LOW_MSB _u(10) -#define IO_BANK0_PROC0_INTS5_GPIO42_EDGE_LOW_LSB _u(10) -#define IO_BANK0_PROC0_INTS5_GPIO42_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS5_GPIO42_LEVEL_HIGH -#define IO_BANK0_PROC0_INTS5_GPIO42_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS5_GPIO42_LEVEL_HIGH_BITS _u(0x00000200) -#define IO_BANK0_PROC0_INTS5_GPIO42_LEVEL_HIGH_MSB _u(9) -#define IO_BANK0_PROC0_INTS5_GPIO42_LEVEL_HIGH_LSB _u(9) -#define IO_BANK0_PROC0_INTS5_GPIO42_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS5_GPIO42_LEVEL_LOW -#define IO_BANK0_PROC0_INTS5_GPIO42_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS5_GPIO42_LEVEL_LOW_BITS _u(0x00000100) -#define IO_BANK0_PROC0_INTS5_GPIO42_LEVEL_LOW_MSB _u(8) -#define IO_BANK0_PROC0_INTS5_GPIO42_LEVEL_LOW_LSB _u(8) -#define IO_BANK0_PROC0_INTS5_GPIO42_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS5_GPIO41_EDGE_HIGH -#define IO_BANK0_PROC0_INTS5_GPIO41_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS5_GPIO41_EDGE_HIGH_BITS _u(0x00000080) -#define IO_BANK0_PROC0_INTS5_GPIO41_EDGE_HIGH_MSB _u(7) -#define IO_BANK0_PROC0_INTS5_GPIO41_EDGE_HIGH_LSB _u(7) -#define IO_BANK0_PROC0_INTS5_GPIO41_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS5_GPIO41_EDGE_LOW -#define IO_BANK0_PROC0_INTS5_GPIO41_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS5_GPIO41_EDGE_LOW_BITS _u(0x00000040) -#define IO_BANK0_PROC0_INTS5_GPIO41_EDGE_LOW_MSB _u(6) -#define IO_BANK0_PROC0_INTS5_GPIO41_EDGE_LOW_LSB _u(6) -#define IO_BANK0_PROC0_INTS5_GPIO41_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS5_GPIO41_LEVEL_HIGH -#define IO_BANK0_PROC0_INTS5_GPIO41_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS5_GPIO41_LEVEL_HIGH_BITS _u(0x00000020) -#define IO_BANK0_PROC0_INTS5_GPIO41_LEVEL_HIGH_MSB _u(5) -#define IO_BANK0_PROC0_INTS5_GPIO41_LEVEL_HIGH_LSB _u(5) -#define IO_BANK0_PROC0_INTS5_GPIO41_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS5_GPIO41_LEVEL_LOW -#define IO_BANK0_PROC0_INTS5_GPIO41_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS5_GPIO41_LEVEL_LOW_BITS _u(0x00000010) -#define IO_BANK0_PROC0_INTS5_GPIO41_LEVEL_LOW_MSB _u(4) -#define IO_BANK0_PROC0_INTS5_GPIO41_LEVEL_LOW_LSB _u(4) -#define IO_BANK0_PROC0_INTS5_GPIO41_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS5_GPIO40_EDGE_HIGH -#define IO_BANK0_PROC0_INTS5_GPIO40_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS5_GPIO40_EDGE_HIGH_BITS _u(0x00000008) -#define IO_BANK0_PROC0_INTS5_GPIO40_EDGE_HIGH_MSB _u(3) -#define IO_BANK0_PROC0_INTS5_GPIO40_EDGE_HIGH_LSB _u(3) -#define IO_BANK0_PROC0_INTS5_GPIO40_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS5_GPIO40_EDGE_LOW -#define IO_BANK0_PROC0_INTS5_GPIO40_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS5_GPIO40_EDGE_LOW_BITS _u(0x00000004) -#define IO_BANK0_PROC0_INTS5_GPIO40_EDGE_LOW_MSB _u(2) -#define IO_BANK0_PROC0_INTS5_GPIO40_EDGE_LOW_LSB _u(2) -#define IO_BANK0_PROC0_INTS5_GPIO40_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS5_GPIO40_LEVEL_HIGH -#define IO_BANK0_PROC0_INTS5_GPIO40_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS5_GPIO40_LEVEL_HIGH_BITS _u(0x00000002) -#define IO_BANK0_PROC0_INTS5_GPIO40_LEVEL_HIGH_MSB _u(1) -#define IO_BANK0_PROC0_INTS5_GPIO40_LEVEL_HIGH_LSB _u(1) -#define IO_BANK0_PROC0_INTS5_GPIO40_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC0_INTS5_GPIO40_LEVEL_LOW -#define IO_BANK0_PROC0_INTS5_GPIO40_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC0_INTS5_GPIO40_LEVEL_LOW_BITS _u(0x00000001) -#define IO_BANK0_PROC0_INTS5_GPIO40_LEVEL_LOW_MSB _u(0) -#define IO_BANK0_PROC0_INTS5_GPIO40_LEVEL_LOW_LSB _u(0) -#define IO_BANK0_PROC0_INTS5_GPIO40_LEVEL_LOW_ACCESS "RO" -// ============================================================================= -// Register : IO_BANK0_PROC1_INTE0 -// Description : Interrupt Enable for proc1 -#define IO_BANK0_PROC1_INTE0_OFFSET _u(0x00000290) -#define IO_BANK0_PROC1_INTE0_BITS _u(0xffffffff) -#define IO_BANK0_PROC1_INTE0_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE0_GPIO7_EDGE_HIGH -#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_HIGH_BITS _u(0x80000000) -#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_HIGH_MSB _u(31) -#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_HIGH_LSB _u(31) -#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE0_GPIO7_EDGE_LOW -#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_LOW_BITS _u(0x40000000) -#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_LOW_MSB _u(30) -#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_LOW_LSB _u(30) -#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_HIGH -#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_HIGH_BITS _u(0x20000000) -#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_HIGH_MSB _u(29) -#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_HIGH_LSB _u(29) -#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_LOW -#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_LOW_BITS _u(0x10000000) -#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_LOW_MSB _u(28) -#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_LOW_LSB _u(28) -#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE0_GPIO6_EDGE_HIGH -#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_HIGH_BITS _u(0x08000000) -#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_HIGH_MSB _u(27) -#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_HIGH_LSB _u(27) -#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE0_GPIO6_EDGE_LOW -#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_LOW_BITS _u(0x04000000) -#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_LOW_MSB _u(26) -#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_LOW_LSB _u(26) -#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_HIGH -#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_HIGH_BITS _u(0x02000000) -#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_HIGH_MSB _u(25) -#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_HIGH_LSB _u(25) -#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_LOW -#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_LOW_BITS _u(0x01000000) -#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_LOW_MSB _u(24) -#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_LOW_LSB _u(24) -#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE0_GPIO5_EDGE_HIGH -#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_HIGH_BITS _u(0x00800000) -#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_HIGH_MSB _u(23) -#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_HIGH_LSB _u(23) -#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE0_GPIO5_EDGE_LOW -#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_LOW_BITS _u(0x00400000) -#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_LOW_MSB _u(22) -#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_LOW_LSB _u(22) -#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_HIGH -#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_HIGH_BITS _u(0x00200000) -#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_HIGH_MSB _u(21) -#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_HIGH_LSB _u(21) -#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_LOW -#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_LOW_BITS _u(0x00100000) -#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_LOW_MSB _u(20) -#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_LOW_LSB _u(20) -#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE0_GPIO4_EDGE_HIGH -#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_HIGH_BITS _u(0x00080000) -#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_HIGH_MSB _u(19) -#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_HIGH_LSB _u(19) -#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE0_GPIO4_EDGE_LOW -#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_LOW_BITS _u(0x00040000) -#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_LOW_MSB _u(18) -#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_LOW_LSB _u(18) -#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_HIGH -#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_HIGH_BITS _u(0x00020000) -#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_HIGH_MSB _u(17) -#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_HIGH_LSB _u(17) -#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_LOW -#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_LOW_BITS _u(0x00010000) -#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_LOW_MSB _u(16) -#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_LOW_LSB _u(16) -#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE0_GPIO3_EDGE_HIGH -#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_HIGH_BITS _u(0x00008000) -#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_HIGH_MSB _u(15) -#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_HIGH_LSB _u(15) -#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE0_GPIO3_EDGE_LOW -#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_LOW_BITS _u(0x00004000) -#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_LOW_MSB _u(14) -#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_LOW_LSB _u(14) -#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_HIGH -#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_HIGH_BITS _u(0x00002000) -#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_HIGH_MSB _u(13) -#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_HIGH_LSB _u(13) -#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_LOW -#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_LOW_BITS _u(0x00001000) -#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_LOW_MSB _u(12) -#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_LOW_LSB _u(12) -#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE0_GPIO2_EDGE_HIGH -#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_HIGH_BITS _u(0x00000800) -#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_HIGH_MSB _u(11) -#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_HIGH_LSB _u(11) -#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE0_GPIO2_EDGE_LOW -#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_LOW_BITS _u(0x00000400) -#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_LOW_MSB _u(10) -#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_LOW_LSB _u(10) -#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_HIGH -#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_HIGH_BITS _u(0x00000200) -#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_HIGH_MSB _u(9) -#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_HIGH_LSB _u(9) -#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_LOW -#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_LOW_BITS _u(0x00000100) -#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_LOW_MSB _u(8) -#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_LOW_LSB _u(8) -#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE0_GPIO1_EDGE_HIGH -#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_HIGH_BITS _u(0x00000080) -#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_HIGH_MSB _u(7) -#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_HIGH_LSB _u(7) -#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE0_GPIO1_EDGE_LOW -#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_LOW_BITS _u(0x00000040) -#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_LOW_MSB _u(6) -#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_LOW_LSB _u(6) -#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_HIGH -#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_HIGH_BITS _u(0x00000020) -#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_HIGH_MSB _u(5) -#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_HIGH_LSB _u(5) -#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_LOW -#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_LOW_BITS _u(0x00000010) -#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_LOW_MSB _u(4) -#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_LOW_LSB _u(4) -#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE0_GPIO0_EDGE_HIGH -#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_HIGH_BITS _u(0x00000008) -#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_HIGH_MSB _u(3) -#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_HIGH_LSB _u(3) -#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE0_GPIO0_EDGE_LOW -#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_LOW_BITS _u(0x00000004) -#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_LOW_MSB _u(2) -#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_LOW_LSB _u(2) -#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_HIGH -#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_HIGH_BITS _u(0x00000002) -#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_HIGH_MSB _u(1) -#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_HIGH_LSB _u(1) -#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_LOW -#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_LOW_BITS _u(0x00000001) -#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_LOW_MSB _u(0) -#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_LOW_LSB _u(0) -#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_LOW_ACCESS "RW" -// ============================================================================= -// Register : IO_BANK0_PROC1_INTE1 -// Description : Interrupt Enable for proc1 -#define IO_BANK0_PROC1_INTE1_OFFSET _u(0x00000294) -#define IO_BANK0_PROC1_INTE1_BITS _u(0xffffffff) -#define IO_BANK0_PROC1_INTE1_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE1_GPIO15_EDGE_HIGH -#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_HIGH_BITS _u(0x80000000) -#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_HIGH_MSB _u(31) -#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_HIGH_LSB _u(31) -#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE1_GPIO15_EDGE_LOW -#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_LOW_BITS _u(0x40000000) -#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_LOW_MSB _u(30) -#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_LOW_LSB _u(30) -#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_HIGH -#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_HIGH_BITS _u(0x20000000) -#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_HIGH_MSB _u(29) -#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_HIGH_LSB _u(29) -#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_LOW -#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_LOW_BITS _u(0x10000000) -#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_LOW_MSB _u(28) -#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_LOW_LSB _u(28) -#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE1_GPIO14_EDGE_HIGH -#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_HIGH_BITS _u(0x08000000) -#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_HIGH_MSB _u(27) -#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_HIGH_LSB _u(27) -#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE1_GPIO14_EDGE_LOW -#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_LOW_BITS _u(0x04000000) -#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_LOW_MSB _u(26) -#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_LOW_LSB _u(26) -#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_HIGH -#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_HIGH_BITS _u(0x02000000) -#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_HIGH_MSB _u(25) -#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_HIGH_LSB _u(25) -#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_LOW -#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_LOW_BITS _u(0x01000000) -#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_LOW_MSB _u(24) -#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_LOW_LSB _u(24) -#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE1_GPIO13_EDGE_HIGH -#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_HIGH_BITS _u(0x00800000) -#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_HIGH_MSB _u(23) -#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_HIGH_LSB _u(23) -#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE1_GPIO13_EDGE_LOW -#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_LOW_BITS _u(0x00400000) -#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_LOW_MSB _u(22) -#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_LOW_LSB _u(22) -#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_HIGH -#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_HIGH_BITS _u(0x00200000) -#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_HIGH_MSB _u(21) -#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_HIGH_LSB _u(21) -#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_LOW -#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_LOW_BITS _u(0x00100000) -#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_LOW_MSB _u(20) -#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_LOW_LSB _u(20) -#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE1_GPIO12_EDGE_HIGH -#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_HIGH_BITS _u(0x00080000) -#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_HIGH_MSB _u(19) -#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_HIGH_LSB _u(19) -#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE1_GPIO12_EDGE_LOW -#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_LOW_BITS _u(0x00040000) -#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_LOW_MSB _u(18) -#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_LOW_LSB _u(18) -#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_HIGH -#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_HIGH_BITS _u(0x00020000) -#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_HIGH_MSB _u(17) -#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_HIGH_LSB _u(17) -#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_LOW -#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_LOW_BITS _u(0x00010000) -#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_LOW_MSB _u(16) -#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_LOW_LSB _u(16) -#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE1_GPIO11_EDGE_HIGH -#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_HIGH_BITS _u(0x00008000) -#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_HIGH_MSB _u(15) -#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_HIGH_LSB _u(15) -#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE1_GPIO11_EDGE_LOW -#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_LOW_BITS _u(0x00004000) -#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_LOW_MSB _u(14) -#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_LOW_LSB _u(14) -#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_HIGH -#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_HIGH_BITS _u(0x00002000) -#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_HIGH_MSB _u(13) -#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_HIGH_LSB _u(13) -#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_LOW -#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_LOW_BITS _u(0x00001000) -#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_LOW_MSB _u(12) -#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_LOW_LSB _u(12) -#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE1_GPIO10_EDGE_HIGH -#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_HIGH_BITS _u(0x00000800) -#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_HIGH_MSB _u(11) -#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_HIGH_LSB _u(11) -#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE1_GPIO10_EDGE_LOW -#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_LOW_BITS _u(0x00000400) -#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_LOW_MSB _u(10) -#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_LOW_LSB _u(10) -#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_HIGH -#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_HIGH_BITS _u(0x00000200) -#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_HIGH_MSB _u(9) -#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_HIGH_LSB _u(9) -#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_LOW -#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_LOW_BITS _u(0x00000100) -#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_LOW_MSB _u(8) -#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_LOW_LSB _u(8) -#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE1_GPIO9_EDGE_HIGH -#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_HIGH_BITS _u(0x00000080) -#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_HIGH_MSB _u(7) -#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_HIGH_LSB _u(7) -#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE1_GPIO9_EDGE_LOW -#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_LOW_BITS _u(0x00000040) -#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_LOW_MSB _u(6) -#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_LOW_LSB _u(6) -#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_HIGH -#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_HIGH_BITS _u(0x00000020) -#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_HIGH_MSB _u(5) -#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_HIGH_LSB _u(5) -#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_LOW -#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_LOW_BITS _u(0x00000010) -#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_LOW_MSB _u(4) -#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_LOW_LSB _u(4) -#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE1_GPIO8_EDGE_HIGH -#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_HIGH_BITS _u(0x00000008) -#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_HIGH_MSB _u(3) -#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_HIGH_LSB _u(3) -#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE1_GPIO8_EDGE_LOW -#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_LOW_BITS _u(0x00000004) -#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_LOW_MSB _u(2) -#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_LOW_LSB _u(2) -#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_HIGH -#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_HIGH_BITS _u(0x00000002) -#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_HIGH_MSB _u(1) -#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_HIGH_LSB _u(1) -#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_LOW -#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_LOW_BITS _u(0x00000001) -#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_LOW_MSB _u(0) -#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_LOW_LSB _u(0) -#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_LOW_ACCESS "RW" -// ============================================================================= -// Register : IO_BANK0_PROC1_INTE2 -// Description : Interrupt Enable for proc1 -#define IO_BANK0_PROC1_INTE2_OFFSET _u(0x00000298) -#define IO_BANK0_PROC1_INTE2_BITS _u(0xffffffff) -#define IO_BANK0_PROC1_INTE2_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE2_GPIO23_EDGE_HIGH -#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_HIGH_BITS _u(0x80000000) -#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_HIGH_MSB _u(31) -#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_HIGH_LSB _u(31) -#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE2_GPIO23_EDGE_LOW -#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_LOW_BITS _u(0x40000000) -#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_LOW_MSB _u(30) -#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_LOW_LSB _u(30) -#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_HIGH -#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_HIGH_BITS _u(0x20000000) -#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_HIGH_MSB _u(29) -#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_HIGH_LSB _u(29) -#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_LOW -#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_LOW_BITS _u(0x10000000) -#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_LOW_MSB _u(28) -#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_LOW_LSB _u(28) -#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE2_GPIO22_EDGE_HIGH -#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_HIGH_BITS _u(0x08000000) -#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_HIGH_MSB _u(27) -#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_HIGH_LSB _u(27) -#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE2_GPIO22_EDGE_LOW -#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_LOW_BITS _u(0x04000000) -#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_LOW_MSB _u(26) -#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_LOW_LSB _u(26) -#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_HIGH -#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_HIGH_BITS _u(0x02000000) -#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_HIGH_MSB _u(25) -#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_HIGH_LSB _u(25) -#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_LOW -#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_LOW_BITS _u(0x01000000) -#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_LOW_MSB _u(24) -#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_LOW_LSB _u(24) -#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE2_GPIO21_EDGE_HIGH -#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_HIGH_BITS _u(0x00800000) -#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_HIGH_MSB _u(23) -#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_HIGH_LSB _u(23) -#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE2_GPIO21_EDGE_LOW -#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_LOW_BITS _u(0x00400000) -#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_LOW_MSB _u(22) -#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_LOW_LSB _u(22) -#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_HIGH -#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_HIGH_BITS _u(0x00200000) -#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_HIGH_MSB _u(21) -#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_HIGH_LSB _u(21) -#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_LOW -#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_LOW_BITS _u(0x00100000) -#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_LOW_MSB _u(20) -#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_LOW_LSB _u(20) -#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE2_GPIO20_EDGE_HIGH -#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_HIGH_BITS _u(0x00080000) -#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_HIGH_MSB _u(19) -#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_HIGH_LSB _u(19) -#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE2_GPIO20_EDGE_LOW -#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_LOW_BITS _u(0x00040000) -#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_LOW_MSB _u(18) -#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_LOW_LSB _u(18) -#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_HIGH -#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_HIGH_BITS _u(0x00020000) -#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_HIGH_MSB _u(17) -#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_HIGH_LSB _u(17) -#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_LOW -#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_LOW_BITS _u(0x00010000) -#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_LOW_MSB _u(16) -#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_LOW_LSB _u(16) -#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE2_GPIO19_EDGE_HIGH -#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_HIGH_BITS _u(0x00008000) -#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_HIGH_MSB _u(15) -#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_HIGH_LSB _u(15) -#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE2_GPIO19_EDGE_LOW -#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_LOW_BITS _u(0x00004000) -#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_LOW_MSB _u(14) -#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_LOW_LSB _u(14) -#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_HIGH -#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_HIGH_BITS _u(0x00002000) -#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_HIGH_MSB _u(13) -#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_HIGH_LSB _u(13) -#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_LOW -#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_LOW_BITS _u(0x00001000) -#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_LOW_MSB _u(12) -#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_LOW_LSB _u(12) -#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE2_GPIO18_EDGE_HIGH -#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_HIGH_BITS _u(0x00000800) -#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_HIGH_MSB _u(11) -#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_HIGH_LSB _u(11) -#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE2_GPIO18_EDGE_LOW -#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_LOW_BITS _u(0x00000400) -#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_LOW_MSB _u(10) -#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_LOW_LSB _u(10) -#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_HIGH -#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_HIGH_BITS _u(0x00000200) -#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_HIGH_MSB _u(9) -#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_HIGH_LSB _u(9) -#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_LOW -#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_LOW_BITS _u(0x00000100) -#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_LOW_MSB _u(8) -#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_LOW_LSB _u(8) -#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE2_GPIO17_EDGE_HIGH -#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_HIGH_BITS _u(0x00000080) -#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_HIGH_MSB _u(7) -#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_HIGH_LSB _u(7) -#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE2_GPIO17_EDGE_LOW -#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_LOW_BITS _u(0x00000040) -#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_LOW_MSB _u(6) -#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_LOW_LSB _u(6) -#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_HIGH -#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_HIGH_BITS _u(0x00000020) -#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_HIGH_MSB _u(5) -#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_HIGH_LSB _u(5) -#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_LOW -#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_LOW_BITS _u(0x00000010) -#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_LOW_MSB _u(4) -#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_LOW_LSB _u(4) -#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE2_GPIO16_EDGE_HIGH -#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_HIGH_BITS _u(0x00000008) -#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_HIGH_MSB _u(3) -#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_HIGH_LSB _u(3) -#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE2_GPIO16_EDGE_LOW -#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_LOW_BITS _u(0x00000004) -#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_LOW_MSB _u(2) -#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_LOW_LSB _u(2) -#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_HIGH -#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_HIGH_BITS _u(0x00000002) -#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_HIGH_MSB _u(1) -#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_HIGH_LSB _u(1) -#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_LOW -#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_LOW_BITS _u(0x00000001) -#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_LOW_MSB _u(0) -#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_LOW_LSB _u(0) -#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_LOW_ACCESS "RW" -// ============================================================================= -// Register : IO_BANK0_PROC1_INTE3 -// Description : Interrupt Enable for proc1 -#define IO_BANK0_PROC1_INTE3_OFFSET _u(0x0000029c) -#define IO_BANK0_PROC1_INTE3_BITS _u(0xffffffff) -#define IO_BANK0_PROC1_INTE3_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE3_GPIO31_EDGE_HIGH -#define IO_BANK0_PROC1_INTE3_GPIO31_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE3_GPIO31_EDGE_HIGH_BITS _u(0x80000000) -#define IO_BANK0_PROC1_INTE3_GPIO31_EDGE_HIGH_MSB _u(31) -#define IO_BANK0_PROC1_INTE3_GPIO31_EDGE_HIGH_LSB _u(31) -#define IO_BANK0_PROC1_INTE3_GPIO31_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE3_GPIO31_EDGE_LOW -#define IO_BANK0_PROC1_INTE3_GPIO31_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE3_GPIO31_EDGE_LOW_BITS _u(0x40000000) -#define IO_BANK0_PROC1_INTE3_GPIO31_EDGE_LOW_MSB _u(30) -#define IO_BANK0_PROC1_INTE3_GPIO31_EDGE_LOW_LSB _u(30) -#define IO_BANK0_PROC1_INTE3_GPIO31_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE3_GPIO31_LEVEL_HIGH -#define IO_BANK0_PROC1_INTE3_GPIO31_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE3_GPIO31_LEVEL_HIGH_BITS _u(0x20000000) -#define IO_BANK0_PROC1_INTE3_GPIO31_LEVEL_HIGH_MSB _u(29) -#define IO_BANK0_PROC1_INTE3_GPIO31_LEVEL_HIGH_LSB _u(29) -#define IO_BANK0_PROC1_INTE3_GPIO31_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE3_GPIO31_LEVEL_LOW -#define IO_BANK0_PROC1_INTE3_GPIO31_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE3_GPIO31_LEVEL_LOW_BITS _u(0x10000000) -#define IO_BANK0_PROC1_INTE3_GPIO31_LEVEL_LOW_MSB _u(28) -#define IO_BANK0_PROC1_INTE3_GPIO31_LEVEL_LOW_LSB _u(28) -#define IO_BANK0_PROC1_INTE3_GPIO31_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE3_GPIO30_EDGE_HIGH -#define IO_BANK0_PROC1_INTE3_GPIO30_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE3_GPIO30_EDGE_HIGH_BITS _u(0x08000000) -#define IO_BANK0_PROC1_INTE3_GPIO30_EDGE_HIGH_MSB _u(27) -#define IO_BANK0_PROC1_INTE3_GPIO30_EDGE_HIGH_LSB _u(27) -#define IO_BANK0_PROC1_INTE3_GPIO30_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE3_GPIO30_EDGE_LOW -#define IO_BANK0_PROC1_INTE3_GPIO30_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE3_GPIO30_EDGE_LOW_BITS _u(0x04000000) -#define IO_BANK0_PROC1_INTE3_GPIO30_EDGE_LOW_MSB _u(26) -#define IO_BANK0_PROC1_INTE3_GPIO30_EDGE_LOW_LSB _u(26) -#define IO_BANK0_PROC1_INTE3_GPIO30_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE3_GPIO30_LEVEL_HIGH -#define IO_BANK0_PROC1_INTE3_GPIO30_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE3_GPIO30_LEVEL_HIGH_BITS _u(0x02000000) -#define IO_BANK0_PROC1_INTE3_GPIO30_LEVEL_HIGH_MSB _u(25) -#define IO_BANK0_PROC1_INTE3_GPIO30_LEVEL_HIGH_LSB _u(25) -#define IO_BANK0_PROC1_INTE3_GPIO30_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE3_GPIO30_LEVEL_LOW -#define IO_BANK0_PROC1_INTE3_GPIO30_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE3_GPIO30_LEVEL_LOW_BITS _u(0x01000000) -#define IO_BANK0_PROC1_INTE3_GPIO30_LEVEL_LOW_MSB _u(24) -#define IO_BANK0_PROC1_INTE3_GPIO30_LEVEL_LOW_LSB _u(24) -#define IO_BANK0_PROC1_INTE3_GPIO30_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE3_GPIO29_EDGE_HIGH -#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_HIGH_BITS _u(0x00800000) -#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_HIGH_MSB _u(23) -#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_HIGH_LSB _u(23) -#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE3_GPIO29_EDGE_LOW -#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_LOW_BITS _u(0x00400000) -#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_LOW_MSB _u(22) -#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_LOW_LSB _u(22) -#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_HIGH -#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_HIGH_BITS _u(0x00200000) -#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_HIGH_MSB _u(21) -#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_HIGH_LSB _u(21) -#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_LOW -#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_LOW_BITS _u(0x00100000) -#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_LOW_MSB _u(20) -#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_LOW_LSB _u(20) -#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE3_GPIO28_EDGE_HIGH -#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_HIGH_BITS _u(0x00080000) -#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_HIGH_MSB _u(19) -#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_HIGH_LSB _u(19) -#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE3_GPIO28_EDGE_LOW -#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_LOW_BITS _u(0x00040000) -#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_LOW_MSB _u(18) -#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_LOW_LSB _u(18) -#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_HIGH -#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_HIGH_BITS _u(0x00020000) -#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_HIGH_MSB _u(17) -#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_HIGH_LSB _u(17) -#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_LOW -#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_LOW_BITS _u(0x00010000) -#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_LOW_MSB _u(16) -#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_LOW_LSB _u(16) -#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE3_GPIO27_EDGE_HIGH -#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_HIGH_BITS _u(0x00008000) -#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_HIGH_MSB _u(15) -#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_HIGH_LSB _u(15) -#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE3_GPIO27_EDGE_LOW -#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_LOW_BITS _u(0x00004000) -#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_LOW_MSB _u(14) -#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_LOW_LSB _u(14) -#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_HIGH -#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_HIGH_BITS _u(0x00002000) -#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_HIGH_MSB _u(13) -#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_HIGH_LSB _u(13) -#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_LOW -#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_LOW_BITS _u(0x00001000) -#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_LOW_MSB _u(12) -#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_LOW_LSB _u(12) -#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE3_GPIO26_EDGE_HIGH -#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_HIGH_BITS _u(0x00000800) -#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_HIGH_MSB _u(11) -#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_HIGH_LSB _u(11) -#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE3_GPIO26_EDGE_LOW -#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_LOW_BITS _u(0x00000400) -#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_LOW_MSB _u(10) -#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_LOW_LSB _u(10) -#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_HIGH -#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_HIGH_BITS _u(0x00000200) -#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_HIGH_MSB _u(9) -#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_HIGH_LSB _u(9) -#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_LOW -#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_LOW_BITS _u(0x00000100) -#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_LOW_MSB _u(8) -#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_LOW_LSB _u(8) -#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE3_GPIO25_EDGE_HIGH -#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_HIGH_BITS _u(0x00000080) -#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_HIGH_MSB _u(7) -#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_HIGH_LSB _u(7) -#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE3_GPIO25_EDGE_LOW -#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_LOW_BITS _u(0x00000040) -#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_LOW_MSB _u(6) -#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_LOW_LSB _u(6) -#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_HIGH -#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_HIGH_BITS _u(0x00000020) -#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_HIGH_MSB _u(5) -#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_HIGH_LSB _u(5) -#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_LOW -#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_LOW_BITS _u(0x00000010) -#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_LOW_MSB _u(4) -#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_LOW_LSB _u(4) -#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE3_GPIO24_EDGE_HIGH -#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_HIGH_BITS _u(0x00000008) -#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_HIGH_MSB _u(3) -#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_HIGH_LSB _u(3) -#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE3_GPIO24_EDGE_LOW -#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_LOW_BITS _u(0x00000004) -#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_LOW_MSB _u(2) -#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_LOW_LSB _u(2) -#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_HIGH -#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_HIGH_BITS _u(0x00000002) -#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_HIGH_MSB _u(1) -#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_HIGH_LSB _u(1) -#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_LOW -#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_LOW_BITS _u(0x00000001) -#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_LOW_MSB _u(0) -#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_LOW_LSB _u(0) -#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_LOW_ACCESS "RW" -// ============================================================================= -// Register : IO_BANK0_PROC1_INTE4 -// Description : Interrupt Enable for proc1 -#define IO_BANK0_PROC1_INTE4_OFFSET _u(0x000002a0) -#define IO_BANK0_PROC1_INTE4_BITS _u(0xffffffff) -#define IO_BANK0_PROC1_INTE4_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE4_GPIO39_EDGE_HIGH -#define IO_BANK0_PROC1_INTE4_GPIO39_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE4_GPIO39_EDGE_HIGH_BITS _u(0x80000000) -#define IO_BANK0_PROC1_INTE4_GPIO39_EDGE_HIGH_MSB _u(31) -#define IO_BANK0_PROC1_INTE4_GPIO39_EDGE_HIGH_LSB _u(31) -#define IO_BANK0_PROC1_INTE4_GPIO39_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE4_GPIO39_EDGE_LOW -#define IO_BANK0_PROC1_INTE4_GPIO39_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE4_GPIO39_EDGE_LOW_BITS _u(0x40000000) -#define IO_BANK0_PROC1_INTE4_GPIO39_EDGE_LOW_MSB _u(30) -#define IO_BANK0_PROC1_INTE4_GPIO39_EDGE_LOW_LSB _u(30) -#define IO_BANK0_PROC1_INTE4_GPIO39_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE4_GPIO39_LEVEL_HIGH -#define IO_BANK0_PROC1_INTE4_GPIO39_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE4_GPIO39_LEVEL_HIGH_BITS _u(0x20000000) -#define IO_BANK0_PROC1_INTE4_GPIO39_LEVEL_HIGH_MSB _u(29) -#define IO_BANK0_PROC1_INTE4_GPIO39_LEVEL_HIGH_LSB _u(29) -#define IO_BANK0_PROC1_INTE4_GPIO39_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE4_GPIO39_LEVEL_LOW -#define IO_BANK0_PROC1_INTE4_GPIO39_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE4_GPIO39_LEVEL_LOW_BITS _u(0x10000000) -#define IO_BANK0_PROC1_INTE4_GPIO39_LEVEL_LOW_MSB _u(28) -#define IO_BANK0_PROC1_INTE4_GPIO39_LEVEL_LOW_LSB _u(28) -#define IO_BANK0_PROC1_INTE4_GPIO39_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE4_GPIO38_EDGE_HIGH -#define IO_BANK0_PROC1_INTE4_GPIO38_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE4_GPIO38_EDGE_HIGH_BITS _u(0x08000000) -#define IO_BANK0_PROC1_INTE4_GPIO38_EDGE_HIGH_MSB _u(27) -#define IO_BANK0_PROC1_INTE4_GPIO38_EDGE_HIGH_LSB _u(27) -#define IO_BANK0_PROC1_INTE4_GPIO38_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE4_GPIO38_EDGE_LOW -#define IO_BANK0_PROC1_INTE4_GPIO38_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE4_GPIO38_EDGE_LOW_BITS _u(0x04000000) -#define IO_BANK0_PROC1_INTE4_GPIO38_EDGE_LOW_MSB _u(26) -#define IO_BANK0_PROC1_INTE4_GPIO38_EDGE_LOW_LSB _u(26) -#define IO_BANK0_PROC1_INTE4_GPIO38_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE4_GPIO38_LEVEL_HIGH -#define IO_BANK0_PROC1_INTE4_GPIO38_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE4_GPIO38_LEVEL_HIGH_BITS _u(0x02000000) -#define IO_BANK0_PROC1_INTE4_GPIO38_LEVEL_HIGH_MSB _u(25) -#define IO_BANK0_PROC1_INTE4_GPIO38_LEVEL_HIGH_LSB _u(25) -#define IO_BANK0_PROC1_INTE4_GPIO38_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE4_GPIO38_LEVEL_LOW -#define IO_BANK0_PROC1_INTE4_GPIO38_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE4_GPIO38_LEVEL_LOW_BITS _u(0x01000000) -#define IO_BANK0_PROC1_INTE4_GPIO38_LEVEL_LOW_MSB _u(24) -#define IO_BANK0_PROC1_INTE4_GPIO38_LEVEL_LOW_LSB _u(24) -#define IO_BANK0_PROC1_INTE4_GPIO38_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE4_GPIO37_EDGE_HIGH -#define IO_BANK0_PROC1_INTE4_GPIO37_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE4_GPIO37_EDGE_HIGH_BITS _u(0x00800000) -#define IO_BANK0_PROC1_INTE4_GPIO37_EDGE_HIGH_MSB _u(23) -#define IO_BANK0_PROC1_INTE4_GPIO37_EDGE_HIGH_LSB _u(23) -#define IO_BANK0_PROC1_INTE4_GPIO37_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE4_GPIO37_EDGE_LOW -#define IO_BANK0_PROC1_INTE4_GPIO37_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE4_GPIO37_EDGE_LOW_BITS _u(0x00400000) -#define IO_BANK0_PROC1_INTE4_GPIO37_EDGE_LOW_MSB _u(22) -#define IO_BANK0_PROC1_INTE4_GPIO37_EDGE_LOW_LSB _u(22) -#define IO_BANK0_PROC1_INTE4_GPIO37_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE4_GPIO37_LEVEL_HIGH -#define IO_BANK0_PROC1_INTE4_GPIO37_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE4_GPIO37_LEVEL_HIGH_BITS _u(0x00200000) -#define IO_BANK0_PROC1_INTE4_GPIO37_LEVEL_HIGH_MSB _u(21) -#define IO_BANK0_PROC1_INTE4_GPIO37_LEVEL_HIGH_LSB _u(21) -#define IO_BANK0_PROC1_INTE4_GPIO37_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE4_GPIO37_LEVEL_LOW -#define IO_BANK0_PROC1_INTE4_GPIO37_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE4_GPIO37_LEVEL_LOW_BITS _u(0x00100000) -#define IO_BANK0_PROC1_INTE4_GPIO37_LEVEL_LOW_MSB _u(20) -#define IO_BANK0_PROC1_INTE4_GPIO37_LEVEL_LOW_LSB _u(20) -#define IO_BANK0_PROC1_INTE4_GPIO37_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE4_GPIO36_EDGE_HIGH -#define IO_BANK0_PROC1_INTE4_GPIO36_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE4_GPIO36_EDGE_HIGH_BITS _u(0x00080000) -#define IO_BANK0_PROC1_INTE4_GPIO36_EDGE_HIGH_MSB _u(19) -#define IO_BANK0_PROC1_INTE4_GPIO36_EDGE_HIGH_LSB _u(19) -#define IO_BANK0_PROC1_INTE4_GPIO36_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE4_GPIO36_EDGE_LOW -#define IO_BANK0_PROC1_INTE4_GPIO36_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE4_GPIO36_EDGE_LOW_BITS _u(0x00040000) -#define IO_BANK0_PROC1_INTE4_GPIO36_EDGE_LOW_MSB _u(18) -#define IO_BANK0_PROC1_INTE4_GPIO36_EDGE_LOW_LSB _u(18) -#define IO_BANK0_PROC1_INTE4_GPIO36_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE4_GPIO36_LEVEL_HIGH -#define IO_BANK0_PROC1_INTE4_GPIO36_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE4_GPIO36_LEVEL_HIGH_BITS _u(0x00020000) -#define IO_BANK0_PROC1_INTE4_GPIO36_LEVEL_HIGH_MSB _u(17) -#define IO_BANK0_PROC1_INTE4_GPIO36_LEVEL_HIGH_LSB _u(17) -#define IO_BANK0_PROC1_INTE4_GPIO36_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE4_GPIO36_LEVEL_LOW -#define IO_BANK0_PROC1_INTE4_GPIO36_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE4_GPIO36_LEVEL_LOW_BITS _u(0x00010000) -#define IO_BANK0_PROC1_INTE4_GPIO36_LEVEL_LOW_MSB _u(16) -#define IO_BANK0_PROC1_INTE4_GPIO36_LEVEL_LOW_LSB _u(16) -#define IO_BANK0_PROC1_INTE4_GPIO36_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE4_GPIO35_EDGE_HIGH -#define IO_BANK0_PROC1_INTE4_GPIO35_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE4_GPIO35_EDGE_HIGH_BITS _u(0x00008000) -#define IO_BANK0_PROC1_INTE4_GPIO35_EDGE_HIGH_MSB _u(15) -#define IO_BANK0_PROC1_INTE4_GPIO35_EDGE_HIGH_LSB _u(15) -#define IO_BANK0_PROC1_INTE4_GPIO35_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE4_GPIO35_EDGE_LOW -#define IO_BANK0_PROC1_INTE4_GPIO35_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE4_GPIO35_EDGE_LOW_BITS _u(0x00004000) -#define IO_BANK0_PROC1_INTE4_GPIO35_EDGE_LOW_MSB _u(14) -#define IO_BANK0_PROC1_INTE4_GPIO35_EDGE_LOW_LSB _u(14) -#define IO_BANK0_PROC1_INTE4_GPIO35_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE4_GPIO35_LEVEL_HIGH -#define IO_BANK0_PROC1_INTE4_GPIO35_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE4_GPIO35_LEVEL_HIGH_BITS _u(0x00002000) -#define IO_BANK0_PROC1_INTE4_GPIO35_LEVEL_HIGH_MSB _u(13) -#define IO_BANK0_PROC1_INTE4_GPIO35_LEVEL_HIGH_LSB _u(13) -#define IO_BANK0_PROC1_INTE4_GPIO35_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE4_GPIO35_LEVEL_LOW -#define IO_BANK0_PROC1_INTE4_GPIO35_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE4_GPIO35_LEVEL_LOW_BITS _u(0x00001000) -#define IO_BANK0_PROC1_INTE4_GPIO35_LEVEL_LOW_MSB _u(12) -#define IO_BANK0_PROC1_INTE4_GPIO35_LEVEL_LOW_LSB _u(12) -#define IO_BANK0_PROC1_INTE4_GPIO35_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE4_GPIO34_EDGE_HIGH -#define IO_BANK0_PROC1_INTE4_GPIO34_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE4_GPIO34_EDGE_HIGH_BITS _u(0x00000800) -#define IO_BANK0_PROC1_INTE4_GPIO34_EDGE_HIGH_MSB _u(11) -#define IO_BANK0_PROC1_INTE4_GPIO34_EDGE_HIGH_LSB _u(11) -#define IO_BANK0_PROC1_INTE4_GPIO34_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE4_GPIO34_EDGE_LOW -#define IO_BANK0_PROC1_INTE4_GPIO34_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE4_GPIO34_EDGE_LOW_BITS _u(0x00000400) -#define IO_BANK0_PROC1_INTE4_GPIO34_EDGE_LOW_MSB _u(10) -#define IO_BANK0_PROC1_INTE4_GPIO34_EDGE_LOW_LSB _u(10) -#define IO_BANK0_PROC1_INTE4_GPIO34_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE4_GPIO34_LEVEL_HIGH -#define IO_BANK0_PROC1_INTE4_GPIO34_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE4_GPIO34_LEVEL_HIGH_BITS _u(0x00000200) -#define IO_BANK0_PROC1_INTE4_GPIO34_LEVEL_HIGH_MSB _u(9) -#define IO_BANK0_PROC1_INTE4_GPIO34_LEVEL_HIGH_LSB _u(9) -#define IO_BANK0_PROC1_INTE4_GPIO34_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE4_GPIO34_LEVEL_LOW -#define IO_BANK0_PROC1_INTE4_GPIO34_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE4_GPIO34_LEVEL_LOW_BITS _u(0x00000100) -#define IO_BANK0_PROC1_INTE4_GPIO34_LEVEL_LOW_MSB _u(8) -#define IO_BANK0_PROC1_INTE4_GPIO34_LEVEL_LOW_LSB _u(8) -#define IO_BANK0_PROC1_INTE4_GPIO34_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE4_GPIO33_EDGE_HIGH -#define IO_BANK0_PROC1_INTE4_GPIO33_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE4_GPIO33_EDGE_HIGH_BITS _u(0x00000080) -#define IO_BANK0_PROC1_INTE4_GPIO33_EDGE_HIGH_MSB _u(7) -#define IO_BANK0_PROC1_INTE4_GPIO33_EDGE_HIGH_LSB _u(7) -#define IO_BANK0_PROC1_INTE4_GPIO33_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE4_GPIO33_EDGE_LOW -#define IO_BANK0_PROC1_INTE4_GPIO33_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE4_GPIO33_EDGE_LOW_BITS _u(0x00000040) -#define IO_BANK0_PROC1_INTE4_GPIO33_EDGE_LOW_MSB _u(6) -#define IO_BANK0_PROC1_INTE4_GPIO33_EDGE_LOW_LSB _u(6) -#define IO_BANK0_PROC1_INTE4_GPIO33_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE4_GPIO33_LEVEL_HIGH -#define IO_BANK0_PROC1_INTE4_GPIO33_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE4_GPIO33_LEVEL_HIGH_BITS _u(0x00000020) -#define IO_BANK0_PROC1_INTE4_GPIO33_LEVEL_HIGH_MSB _u(5) -#define IO_BANK0_PROC1_INTE4_GPIO33_LEVEL_HIGH_LSB _u(5) -#define IO_BANK0_PROC1_INTE4_GPIO33_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE4_GPIO33_LEVEL_LOW -#define IO_BANK0_PROC1_INTE4_GPIO33_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE4_GPIO33_LEVEL_LOW_BITS _u(0x00000010) -#define IO_BANK0_PROC1_INTE4_GPIO33_LEVEL_LOW_MSB _u(4) -#define IO_BANK0_PROC1_INTE4_GPIO33_LEVEL_LOW_LSB _u(4) -#define IO_BANK0_PROC1_INTE4_GPIO33_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE4_GPIO32_EDGE_HIGH -#define IO_BANK0_PROC1_INTE4_GPIO32_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE4_GPIO32_EDGE_HIGH_BITS _u(0x00000008) -#define IO_BANK0_PROC1_INTE4_GPIO32_EDGE_HIGH_MSB _u(3) -#define IO_BANK0_PROC1_INTE4_GPIO32_EDGE_HIGH_LSB _u(3) -#define IO_BANK0_PROC1_INTE4_GPIO32_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE4_GPIO32_EDGE_LOW -#define IO_BANK0_PROC1_INTE4_GPIO32_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE4_GPIO32_EDGE_LOW_BITS _u(0x00000004) -#define IO_BANK0_PROC1_INTE4_GPIO32_EDGE_LOW_MSB _u(2) -#define IO_BANK0_PROC1_INTE4_GPIO32_EDGE_LOW_LSB _u(2) -#define IO_BANK0_PROC1_INTE4_GPIO32_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE4_GPIO32_LEVEL_HIGH -#define IO_BANK0_PROC1_INTE4_GPIO32_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE4_GPIO32_LEVEL_HIGH_BITS _u(0x00000002) -#define IO_BANK0_PROC1_INTE4_GPIO32_LEVEL_HIGH_MSB _u(1) -#define IO_BANK0_PROC1_INTE4_GPIO32_LEVEL_HIGH_LSB _u(1) -#define IO_BANK0_PROC1_INTE4_GPIO32_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE4_GPIO32_LEVEL_LOW -#define IO_BANK0_PROC1_INTE4_GPIO32_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE4_GPIO32_LEVEL_LOW_BITS _u(0x00000001) -#define IO_BANK0_PROC1_INTE4_GPIO32_LEVEL_LOW_MSB _u(0) -#define IO_BANK0_PROC1_INTE4_GPIO32_LEVEL_LOW_LSB _u(0) -#define IO_BANK0_PROC1_INTE4_GPIO32_LEVEL_LOW_ACCESS "RW" -// ============================================================================= -// Register : IO_BANK0_PROC1_INTE5 -// Description : Interrupt Enable for proc1 -#define IO_BANK0_PROC1_INTE5_OFFSET _u(0x000002a4) -#define IO_BANK0_PROC1_INTE5_BITS _u(0xffffffff) -#define IO_BANK0_PROC1_INTE5_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE5_GPIO47_EDGE_HIGH -#define IO_BANK0_PROC1_INTE5_GPIO47_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE5_GPIO47_EDGE_HIGH_BITS _u(0x80000000) -#define IO_BANK0_PROC1_INTE5_GPIO47_EDGE_HIGH_MSB _u(31) -#define IO_BANK0_PROC1_INTE5_GPIO47_EDGE_HIGH_LSB _u(31) -#define IO_BANK0_PROC1_INTE5_GPIO47_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE5_GPIO47_EDGE_LOW -#define IO_BANK0_PROC1_INTE5_GPIO47_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE5_GPIO47_EDGE_LOW_BITS _u(0x40000000) -#define IO_BANK0_PROC1_INTE5_GPIO47_EDGE_LOW_MSB _u(30) -#define IO_BANK0_PROC1_INTE5_GPIO47_EDGE_LOW_LSB _u(30) -#define IO_BANK0_PROC1_INTE5_GPIO47_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE5_GPIO47_LEVEL_HIGH -#define IO_BANK0_PROC1_INTE5_GPIO47_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE5_GPIO47_LEVEL_HIGH_BITS _u(0x20000000) -#define IO_BANK0_PROC1_INTE5_GPIO47_LEVEL_HIGH_MSB _u(29) -#define IO_BANK0_PROC1_INTE5_GPIO47_LEVEL_HIGH_LSB _u(29) -#define IO_BANK0_PROC1_INTE5_GPIO47_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE5_GPIO47_LEVEL_LOW -#define IO_BANK0_PROC1_INTE5_GPIO47_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE5_GPIO47_LEVEL_LOW_BITS _u(0x10000000) -#define IO_BANK0_PROC1_INTE5_GPIO47_LEVEL_LOW_MSB _u(28) -#define IO_BANK0_PROC1_INTE5_GPIO47_LEVEL_LOW_LSB _u(28) -#define IO_BANK0_PROC1_INTE5_GPIO47_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE5_GPIO46_EDGE_HIGH -#define IO_BANK0_PROC1_INTE5_GPIO46_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE5_GPIO46_EDGE_HIGH_BITS _u(0x08000000) -#define IO_BANK0_PROC1_INTE5_GPIO46_EDGE_HIGH_MSB _u(27) -#define IO_BANK0_PROC1_INTE5_GPIO46_EDGE_HIGH_LSB _u(27) -#define IO_BANK0_PROC1_INTE5_GPIO46_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE5_GPIO46_EDGE_LOW -#define IO_BANK0_PROC1_INTE5_GPIO46_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE5_GPIO46_EDGE_LOW_BITS _u(0x04000000) -#define IO_BANK0_PROC1_INTE5_GPIO46_EDGE_LOW_MSB _u(26) -#define IO_BANK0_PROC1_INTE5_GPIO46_EDGE_LOW_LSB _u(26) -#define IO_BANK0_PROC1_INTE5_GPIO46_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE5_GPIO46_LEVEL_HIGH -#define IO_BANK0_PROC1_INTE5_GPIO46_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE5_GPIO46_LEVEL_HIGH_BITS _u(0x02000000) -#define IO_BANK0_PROC1_INTE5_GPIO46_LEVEL_HIGH_MSB _u(25) -#define IO_BANK0_PROC1_INTE5_GPIO46_LEVEL_HIGH_LSB _u(25) -#define IO_BANK0_PROC1_INTE5_GPIO46_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE5_GPIO46_LEVEL_LOW -#define IO_BANK0_PROC1_INTE5_GPIO46_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE5_GPIO46_LEVEL_LOW_BITS _u(0x01000000) -#define IO_BANK0_PROC1_INTE5_GPIO46_LEVEL_LOW_MSB _u(24) -#define IO_BANK0_PROC1_INTE5_GPIO46_LEVEL_LOW_LSB _u(24) -#define IO_BANK0_PROC1_INTE5_GPIO46_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE5_GPIO45_EDGE_HIGH -#define IO_BANK0_PROC1_INTE5_GPIO45_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE5_GPIO45_EDGE_HIGH_BITS _u(0x00800000) -#define IO_BANK0_PROC1_INTE5_GPIO45_EDGE_HIGH_MSB _u(23) -#define IO_BANK0_PROC1_INTE5_GPIO45_EDGE_HIGH_LSB _u(23) -#define IO_BANK0_PROC1_INTE5_GPIO45_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE5_GPIO45_EDGE_LOW -#define IO_BANK0_PROC1_INTE5_GPIO45_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE5_GPIO45_EDGE_LOW_BITS _u(0x00400000) -#define IO_BANK0_PROC1_INTE5_GPIO45_EDGE_LOW_MSB _u(22) -#define IO_BANK0_PROC1_INTE5_GPIO45_EDGE_LOW_LSB _u(22) -#define IO_BANK0_PROC1_INTE5_GPIO45_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE5_GPIO45_LEVEL_HIGH -#define IO_BANK0_PROC1_INTE5_GPIO45_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE5_GPIO45_LEVEL_HIGH_BITS _u(0x00200000) -#define IO_BANK0_PROC1_INTE5_GPIO45_LEVEL_HIGH_MSB _u(21) -#define IO_BANK0_PROC1_INTE5_GPIO45_LEVEL_HIGH_LSB _u(21) -#define IO_BANK0_PROC1_INTE5_GPIO45_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE5_GPIO45_LEVEL_LOW -#define IO_BANK0_PROC1_INTE5_GPIO45_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE5_GPIO45_LEVEL_LOW_BITS _u(0x00100000) -#define IO_BANK0_PROC1_INTE5_GPIO45_LEVEL_LOW_MSB _u(20) -#define IO_BANK0_PROC1_INTE5_GPIO45_LEVEL_LOW_LSB _u(20) -#define IO_BANK0_PROC1_INTE5_GPIO45_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE5_GPIO44_EDGE_HIGH -#define IO_BANK0_PROC1_INTE5_GPIO44_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE5_GPIO44_EDGE_HIGH_BITS _u(0x00080000) -#define IO_BANK0_PROC1_INTE5_GPIO44_EDGE_HIGH_MSB _u(19) -#define IO_BANK0_PROC1_INTE5_GPIO44_EDGE_HIGH_LSB _u(19) -#define IO_BANK0_PROC1_INTE5_GPIO44_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE5_GPIO44_EDGE_LOW -#define IO_BANK0_PROC1_INTE5_GPIO44_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE5_GPIO44_EDGE_LOW_BITS _u(0x00040000) -#define IO_BANK0_PROC1_INTE5_GPIO44_EDGE_LOW_MSB _u(18) -#define IO_BANK0_PROC1_INTE5_GPIO44_EDGE_LOW_LSB _u(18) -#define IO_BANK0_PROC1_INTE5_GPIO44_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE5_GPIO44_LEVEL_HIGH -#define IO_BANK0_PROC1_INTE5_GPIO44_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE5_GPIO44_LEVEL_HIGH_BITS _u(0x00020000) -#define IO_BANK0_PROC1_INTE5_GPIO44_LEVEL_HIGH_MSB _u(17) -#define IO_BANK0_PROC1_INTE5_GPIO44_LEVEL_HIGH_LSB _u(17) -#define IO_BANK0_PROC1_INTE5_GPIO44_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE5_GPIO44_LEVEL_LOW -#define IO_BANK0_PROC1_INTE5_GPIO44_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE5_GPIO44_LEVEL_LOW_BITS _u(0x00010000) -#define IO_BANK0_PROC1_INTE5_GPIO44_LEVEL_LOW_MSB _u(16) -#define IO_BANK0_PROC1_INTE5_GPIO44_LEVEL_LOW_LSB _u(16) -#define IO_BANK0_PROC1_INTE5_GPIO44_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE5_GPIO43_EDGE_HIGH -#define IO_BANK0_PROC1_INTE5_GPIO43_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE5_GPIO43_EDGE_HIGH_BITS _u(0x00008000) -#define IO_BANK0_PROC1_INTE5_GPIO43_EDGE_HIGH_MSB _u(15) -#define IO_BANK0_PROC1_INTE5_GPIO43_EDGE_HIGH_LSB _u(15) -#define IO_BANK0_PROC1_INTE5_GPIO43_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE5_GPIO43_EDGE_LOW -#define IO_BANK0_PROC1_INTE5_GPIO43_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE5_GPIO43_EDGE_LOW_BITS _u(0x00004000) -#define IO_BANK0_PROC1_INTE5_GPIO43_EDGE_LOW_MSB _u(14) -#define IO_BANK0_PROC1_INTE5_GPIO43_EDGE_LOW_LSB _u(14) -#define IO_BANK0_PROC1_INTE5_GPIO43_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE5_GPIO43_LEVEL_HIGH -#define IO_BANK0_PROC1_INTE5_GPIO43_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE5_GPIO43_LEVEL_HIGH_BITS _u(0x00002000) -#define IO_BANK0_PROC1_INTE5_GPIO43_LEVEL_HIGH_MSB _u(13) -#define IO_BANK0_PROC1_INTE5_GPIO43_LEVEL_HIGH_LSB _u(13) -#define IO_BANK0_PROC1_INTE5_GPIO43_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE5_GPIO43_LEVEL_LOW -#define IO_BANK0_PROC1_INTE5_GPIO43_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE5_GPIO43_LEVEL_LOW_BITS _u(0x00001000) -#define IO_BANK0_PROC1_INTE5_GPIO43_LEVEL_LOW_MSB _u(12) -#define IO_BANK0_PROC1_INTE5_GPIO43_LEVEL_LOW_LSB _u(12) -#define IO_BANK0_PROC1_INTE5_GPIO43_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE5_GPIO42_EDGE_HIGH -#define IO_BANK0_PROC1_INTE5_GPIO42_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE5_GPIO42_EDGE_HIGH_BITS _u(0x00000800) -#define IO_BANK0_PROC1_INTE5_GPIO42_EDGE_HIGH_MSB _u(11) -#define IO_BANK0_PROC1_INTE5_GPIO42_EDGE_HIGH_LSB _u(11) -#define IO_BANK0_PROC1_INTE5_GPIO42_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE5_GPIO42_EDGE_LOW -#define IO_BANK0_PROC1_INTE5_GPIO42_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE5_GPIO42_EDGE_LOW_BITS _u(0x00000400) -#define IO_BANK0_PROC1_INTE5_GPIO42_EDGE_LOW_MSB _u(10) -#define IO_BANK0_PROC1_INTE5_GPIO42_EDGE_LOW_LSB _u(10) -#define IO_BANK0_PROC1_INTE5_GPIO42_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE5_GPIO42_LEVEL_HIGH -#define IO_BANK0_PROC1_INTE5_GPIO42_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE5_GPIO42_LEVEL_HIGH_BITS _u(0x00000200) -#define IO_BANK0_PROC1_INTE5_GPIO42_LEVEL_HIGH_MSB _u(9) -#define IO_BANK0_PROC1_INTE5_GPIO42_LEVEL_HIGH_LSB _u(9) -#define IO_BANK0_PROC1_INTE5_GPIO42_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE5_GPIO42_LEVEL_LOW -#define IO_BANK0_PROC1_INTE5_GPIO42_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE5_GPIO42_LEVEL_LOW_BITS _u(0x00000100) -#define IO_BANK0_PROC1_INTE5_GPIO42_LEVEL_LOW_MSB _u(8) -#define IO_BANK0_PROC1_INTE5_GPIO42_LEVEL_LOW_LSB _u(8) -#define IO_BANK0_PROC1_INTE5_GPIO42_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE5_GPIO41_EDGE_HIGH -#define IO_BANK0_PROC1_INTE5_GPIO41_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE5_GPIO41_EDGE_HIGH_BITS _u(0x00000080) -#define IO_BANK0_PROC1_INTE5_GPIO41_EDGE_HIGH_MSB _u(7) -#define IO_BANK0_PROC1_INTE5_GPIO41_EDGE_HIGH_LSB _u(7) -#define IO_BANK0_PROC1_INTE5_GPIO41_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE5_GPIO41_EDGE_LOW -#define IO_BANK0_PROC1_INTE5_GPIO41_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE5_GPIO41_EDGE_LOW_BITS _u(0x00000040) -#define IO_BANK0_PROC1_INTE5_GPIO41_EDGE_LOW_MSB _u(6) -#define IO_BANK0_PROC1_INTE5_GPIO41_EDGE_LOW_LSB _u(6) -#define IO_BANK0_PROC1_INTE5_GPIO41_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE5_GPIO41_LEVEL_HIGH -#define IO_BANK0_PROC1_INTE5_GPIO41_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE5_GPIO41_LEVEL_HIGH_BITS _u(0x00000020) -#define IO_BANK0_PROC1_INTE5_GPIO41_LEVEL_HIGH_MSB _u(5) -#define IO_BANK0_PROC1_INTE5_GPIO41_LEVEL_HIGH_LSB _u(5) -#define IO_BANK0_PROC1_INTE5_GPIO41_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE5_GPIO41_LEVEL_LOW -#define IO_BANK0_PROC1_INTE5_GPIO41_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE5_GPIO41_LEVEL_LOW_BITS _u(0x00000010) -#define IO_BANK0_PROC1_INTE5_GPIO41_LEVEL_LOW_MSB _u(4) -#define IO_BANK0_PROC1_INTE5_GPIO41_LEVEL_LOW_LSB _u(4) -#define IO_BANK0_PROC1_INTE5_GPIO41_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE5_GPIO40_EDGE_HIGH -#define IO_BANK0_PROC1_INTE5_GPIO40_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE5_GPIO40_EDGE_HIGH_BITS _u(0x00000008) -#define IO_BANK0_PROC1_INTE5_GPIO40_EDGE_HIGH_MSB _u(3) -#define IO_BANK0_PROC1_INTE5_GPIO40_EDGE_HIGH_LSB _u(3) -#define IO_BANK0_PROC1_INTE5_GPIO40_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE5_GPIO40_EDGE_LOW -#define IO_BANK0_PROC1_INTE5_GPIO40_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE5_GPIO40_EDGE_LOW_BITS _u(0x00000004) -#define IO_BANK0_PROC1_INTE5_GPIO40_EDGE_LOW_MSB _u(2) -#define IO_BANK0_PROC1_INTE5_GPIO40_EDGE_LOW_LSB _u(2) -#define IO_BANK0_PROC1_INTE5_GPIO40_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE5_GPIO40_LEVEL_HIGH -#define IO_BANK0_PROC1_INTE5_GPIO40_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE5_GPIO40_LEVEL_HIGH_BITS _u(0x00000002) -#define IO_BANK0_PROC1_INTE5_GPIO40_LEVEL_HIGH_MSB _u(1) -#define IO_BANK0_PROC1_INTE5_GPIO40_LEVEL_HIGH_LSB _u(1) -#define IO_BANK0_PROC1_INTE5_GPIO40_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTE5_GPIO40_LEVEL_LOW -#define IO_BANK0_PROC1_INTE5_GPIO40_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTE5_GPIO40_LEVEL_LOW_BITS _u(0x00000001) -#define IO_BANK0_PROC1_INTE5_GPIO40_LEVEL_LOW_MSB _u(0) -#define IO_BANK0_PROC1_INTE5_GPIO40_LEVEL_LOW_LSB _u(0) -#define IO_BANK0_PROC1_INTE5_GPIO40_LEVEL_LOW_ACCESS "RW" -// ============================================================================= -// Register : IO_BANK0_PROC1_INTF0 -// Description : Interrupt Force for proc1 -#define IO_BANK0_PROC1_INTF0_OFFSET _u(0x000002a8) -#define IO_BANK0_PROC1_INTF0_BITS _u(0xffffffff) -#define IO_BANK0_PROC1_INTF0_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF0_GPIO7_EDGE_HIGH -#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_HIGH_BITS _u(0x80000000) -#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_HIGH_MSB _u(31) -#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_HIGH_LSB _u(31) -#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF0_GPIO7_EDGE_LOW -#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_LOW_BITS _u(0x40000000) -#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_LOW_MSB _u(30) -#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_LOW_LSB _u(30) -#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_HIGH -#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_HIGH_BITS _u(0x20000000) -#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_HIGH_MSB _u(29) -#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_HIGH_LSB _u(29) -#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_LOW -#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_LOW_BITS _u(0x10000000) -#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_LOW_MSB _u(28) -#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_LOW_LSB _u(28) -#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF0_GPIO6_EDGE_HIGH -#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_HIGH_BITS _u(0x08000000) -#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_HIGH_MSB _u(27) -#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_HIGH_LSB _u(27) -#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF0_GPIO6_EDGE_LOW -#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_LOW_BITS _u(0x04000000) -#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_LOW_MSB _u(26) -#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_LOW_LSB _u(26) -#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_HIGH -#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_HIGH_BITS _u(0x02000000) -#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_HIGH_MSB _u(25) -#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_HIGH_LSB _u(25) -#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_LOW -#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_LOW_BITS _u(0x01000000) -#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_LOW_MSB _u(24) -#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_LOW_LSB _u(24) -#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF0_GPIO5_EDGE_HIGH -#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_HIGH_BITS _u(0x00800000) -#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_HIGH_MSB _u(23) -#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_HIGH_LSB _u(23) -#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF0_GPIO5_EDGE_LOW -#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_LOW_BITS _u(0x00400000) -#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_LOW_MSB _u(22) -#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_LOW_LSB _u(22) -#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_HIGH -#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_HIGH_BITS _u(0x00200000) -#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_HIGH_MSB _u(21) -#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_HIGH_LSB _u(21) -#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_LOW -#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_LOW_BITS _u(0x00100000) -#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_LOW_MSB _u(20) -#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_LOW_LSB _u(20) -#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF0_GPIO4_EDGE_HIGH -#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_HIGH_BITS _u(0x00080000) -#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_HIGH_MSB _u(19) -#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_HIGH_LSB _u(19) -#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF0_GPIO4_EDGE_LOW -#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_LOW_BITS _u(0x00040000) -#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_LOW_MSB _u(18) -#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_LOW_LSB _u(18) -#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_HIGH -#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_HIGH_BITS _u(0x00020000) -#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_HIGH_MSB _u(17) -#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_HIGH_LSB _u(17) -#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_LOW -#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_LOW_BITS _u(0x00010000) -#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_LOW_MSB _u(16) -#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_LOW_LSB _u(16) -#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF0_GPIO3_EDGE_HIGH -#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_HIGH_BITS _u(0x00008000) -#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_HIGH_MSB _u(15) -#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_HIGH_LSB _u(15) -#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF0_GPIO3_EDGE_LOW -#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_LOW_BITS _u(0x00004000) -#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_LOW_MSB _u(14) -#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_LOW_LSB _u(14) -#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_HIGH -#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_HIGH_BITS _u(0x00002000) -#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_HIGH_MSB _u(13) -#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_HIGH_LSB _u(13) -#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_LOW -#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_LOW_BITS _u(0x00001000) -#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_LOW_MSB _u(12) -#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_LOW_LSB _u(12) -#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF0_GPIO2_EDGE_HIGH -#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_HIGH_BITS _u(0x00000800) -#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_HIGH_MSB _u(11) -#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_HIGH_LSB _u(11) -#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF0_GPIO2_EDGE_LOW -#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_LOW_BITS _u(0x00000400) -#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_LOW_MSB _u(10) -#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_LOW_LSB _u(10) -#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_HIGH -#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_HIGH_BITS _u(0x00000200) -#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_HIGH_MSB _u(9) -#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_HIGH_LSB _u(9) -#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_LOW -#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_LOW_BITS _u(0x00000100) -#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_LOW_MSB _u(8) -#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_LOW_LSB _u(8) -#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF0_GPIO1_EDGE_HIGH -#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_HIGH_BITS _u(0x00000080) -#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_HIGH_MSB _u(7) -#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_HIGH_LSB _u(7) -#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF0_GPIO1_EDGE_LOW -#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_LOW_BITS _u(0x00000040) -#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_LOW_MSB _u(6) -#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_LOW_LSB _u(6) -#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_HIGH -#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_HIGH_BITS _u(0x00000020) -#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_HIGH_MSB _u(5) -#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_HIGH_LSB _u(5) -#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_LOW -#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_LOW_BITS _u(0x00000010) -#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_LOW_MSB _u(4) -#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_LOW_LSB _u(4) -#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF0_GPIO0_EDGE_HIGH -#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_HIGH_BITS _u(0x00000008) -#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_HIGH_MSB _u(3) -#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_HIGH_LSB _u(3) -#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF0_GPIO0_EDGE_LOW -#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_LOW_BITS _u(0x00000004) -#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_LOW_MSB _u(2) -#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_LOW_LSB _u(2) -#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_HIGH -#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_HIGH_BITS _u(0x00000002) -#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_HIGH_MSB _u(1) -#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_HIGH_LSB _u(1) -#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_LOW -#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_LOW_BITS _u(0x00000001) -#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_LOW_MSB _u(0) -#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_LOW_LSB _u(0) -#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_LOW_ACCESS "RW" -// ============================================================================= -// Register : IO_BANK0_PROC1_INTF1 -// Description : Interrupt Force for proc1 -#define IO_BANK0_PROC1_INTF1_OFFSET _u(0x000002ac) -#define IO_BANK0_PROC1_INTF1_BITS _u(0xffffffff) -#define IO_BANK0_PROC1_INTF1_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF1_GPIO15_EDGE_HIGH -#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_HIGH_BITS _u(0x80000000) -#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_HIGH_MSB _u(31) -#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_HIGH_LSB _u(31) -#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF1_GPIO15_EDGE_LOW -#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_LOW_BITS _u(0x40000000) -#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_LOW_MSB _u(30) -#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_LOW_LSB _u(30) -#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_HIGH -#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_HIGH_BITS _u(0x20000000) -#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_HIGH_MSB _u(29) -#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_HIGH_LSB _u(29) -#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_LOW -#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_LOW_BITS _u(0x10000000) -#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_LOW_MSB _u(28) -#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_LOW_LSB _u(28) -#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF1_GPIO14_EDGE_HIGH -#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_HIGH_BITS _u(0x08000000) -#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_HIGH_MSB _u(27) -#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_HIGH_LSB _u(27) -#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF1_GPIO14_EDGE_LOW -#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_LOW_BITS _u(0x04000000) -#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_LOW_MSB _u(26) -#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_LOW_LSB _u(26) -#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_HIGH -#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_HIGH_BITS _u(0x02000000) -#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_HIGH_MSB _u(25) -#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_HIGH_LSB _u(25) -#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_LOW -#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_LOW_BITS _u(0x01000000) -#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_LOW_MSB _u(24) -#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_LOW_LSB _u(24) -#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF1_GPIO13_EDGE_HIGH -#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_HIGH_BITS _u(0x00800000) -#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_HIGH_MSB _u(23) -#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_HIGH_LSB _u(23) -#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF1_GPIO13_EDGE_LOW -#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_LOW_BITS _u(0x00400000) -#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_LOW_MSB _u(22) -#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_LOW_LSB _u(22) -#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_HIGH -#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_HIGH_BITS _u(0x00200000) -#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_HIGH_MSB _u(21) -#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_HIGH_LSB _u(21) -#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_LOW -#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_LOW_BITS _u(0x00100000) -#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_LOW_MSB _u(20) -#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_LOW_LSB _u(20) -#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF1_GPIO12_EDGE_HIGH -#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_HIGH_BITS _u(0x00080000) -#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_HIGH_MSB _u(19) -#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_HIGH_LSB _u(19) -#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF1_GPIO12_EDGE_LOW -#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_LOW_BITS _u(0x00040000) -#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_LOW_MSB _u(18) -#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_LOW_LSB _u(18) -#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_HIGH -#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_HIGH_BITS _u(0x00020000) -#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_HIGH_MSB _u(17) -#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_HIGH_LSB _u(17) -#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_LOW -#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_LOW_BITS _u(0x00010000) -#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_LOW_MSB _u(16) -#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_LOW_LSB _u(16) -#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF1_GPIO11_EDGE_HIGH -#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_HIGH_BITS _u(0x00008000) -#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_HIGH_MSB _u(15) -#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_HIGH_LSB _u(15) -#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF1_GPIO11_EDGE_LOW -#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_LOW_BITS _u(0x00004000) -#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_LOW_MSB _u(14) -#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_LOW_LSB _u(14) -#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_HIGH -#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_HIGH_BITS _u(0x00002000) -#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_HIGH_MSB _u(13) -#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_HIGH_LSB _u(13) -#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_LOW -#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_LOW_BITS _u(0x00001000) -#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_LOW_MSB _u(12) -#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_LOW_LSB _u(12) -#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF1_GPIO10_EDGE_HIGH -#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_HIGH_BITS _u(0x00000800) -#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_HIGH_MSB _u(11) -#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_HIGH_LSB _u(11) -#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF1_GPIO10_EDGE_LOW -#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_LOW_BITS _u(0x00000400) -#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_LOW_MSB _u(10) -#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_LOW_LSB _u(10) -#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_HIGH -#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_HIGH_BITS _u(0x00000200) -#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_HIGH_MSB _u(9) -#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_HIGH_LSB _u(9) -#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_LOW -#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_LOW_BITS _u(0x00000100) -#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_LOW_MSB _u(8) -#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_LOW_LSB _u(8) -#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF1_GPIO9_EDGE_HIGH -#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_HIGH_BITS _u(0x00000080) -#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_HIGH_MSB _u(7) -#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_HIGH_LSB _u(7) -#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF1_GPIO9_EDGE_LOW -#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_LOW_BITS _u(0x00000040) -#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_LOW_MSB _u(6) -#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_LOW_LSB _u(6) -#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_HIGH -#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_HIGH_BITS _u(0x00000020) -#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_HIGH_MSB _u(5) -#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_HIGH_LSB _u(5) -#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_LOW -#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_LOW_BITS _u(0x00000010) -#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_LOW_MSB _u(4) -#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_LOW_LSB _u(4) -#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF1_GPIO8_EDGE_HIGH -#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_HIGH_BITS _u(0x00000008) -#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_HIGH_MSB _u(3) -#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_HIGH_LSB _u(3) -#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF1_GPIO8_EDGE_LOW -#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_LOW_BITS _u(0x00000004) -#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_LOW_MSB _u(2) -#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_LOW_LSB _u(2) -#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_HIGH -#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_HIGH_BITS _u(0x00000002) -#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_HIGH_MSB _u(1) -#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_HIGH_LSB _u(1) -#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_LOW -#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_LOW_BITS _u(0x00000001) -#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_LOW_MSB _u(0) -#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_LOW_LSB _u(0) -#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_LOW_ACCESS "RW" -// ============================================================================= -// Register : IO_BANK0_PROC1_INTF2 -// Description : Interrupt Force for proc1 -#define IO_BANK0_PROC1_INTF2_OFFSET _u(0x000002b0) -#define IO_BANK0_PROC1_INTF2_BITS _u(0xffffffff) -#define IO_BANK0_PROC1_INTF2_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF2_GPIO23_EDGE_HIGH -#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_HIGH_BITS _u(0x80000000) -#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_HIGH_MSB _u(31) -#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_HIGH_LSB _u(31) -#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF2_GPIO23_EDGE_LOW -#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_LOW_BITS _u(0x40000000) -#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_LOW_MSB _u(30) -#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_LOW_LSB _u(30) -#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_HIGH -#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_HIGH_BITS _u(0x20000000) -#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_HIGH_MSB _u(29) -#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_HIGH_LSB _u(29) -#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_LOW -#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_LOW_BITS _u(0x10000000) -#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_LOW_MSB _u(28) -#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_LOW_LSB _u(28) -#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF2_GPIO22_EDGE_HIGH -#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_HIGH_BITS _u(0x08000000) -#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_HIGH_MSB _u(27) -#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_HIGH_LSB _u(27) -#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF2_GPIO22_EDGE_LOW -#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_LOW_BITS _u(0x04000000) -#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_LOW_MSB _u(26) -#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_LOW_LSB _u(26) -#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_HIGH -#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_HIGH_BITS _u(0x02000000) -#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_HIGH_MSB _u(25) -#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_HIGH_LSB _u(25) -#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_LOW -#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_LOW_BITS _u(0x01000000) -#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_LOW_MSB _u(24) -#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_LOW_LSB _u(24) -#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF2_GPIO21_EDGE_HIGH -#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_HIGH_BITS _u(0x00800000) -#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_HIGH_MSB _u(23) -#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_HIGH_LSB _u(23) -#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF2_GPIO21_EDGE_LOW -#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_LOW_BITS _u(0x00400000) -#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_LOW_MSB _u(22) -#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_LOW_LSB _u(22) -#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_HIGH -#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_HIGH_BITS _u(0x00200000) -#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_HIGH_MSB _u(21) -#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_HIGH_LSB _u(21) -#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_LOW -#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_LOW_BITS _u(0x00100000) -#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_LOW_MSB _u(20) -#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_LOW_LSB _u(20) -#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF2_GPIO20_EDGE_HIGH -#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_HIGH_BITS _u(0x00080000) -#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_HIGH_MSB _u(19) -#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_HIGH_LSB _u(19) -#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF2_GPIO20_EDGE_LOW -#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_LOW_BITS _u(0x00040000) -#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_LOW_MSB _u(18) -#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_LOW_LSB _u(18) -#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_HIGH -#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_HIGH_BITS _u(0x00020000) -#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_HIGH_MSB _u(17) -#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_HIGH_LSB _u(17) -#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_LOW -#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_LOW_BITS _u(0x00010000) -#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_LOW_MSB _u(16) -#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_LOW_LSB _u(16) -#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF2_GPIO19_EDGE_HIGH -#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_HIGH_BITS _u(0x00008000) -#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_HIGH_MSB _u(15) -#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_HIGH_LSB _u(15) -#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF2_GPIO19_EDGE_LOW -#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_LOW_BITS _u(0x00004000) -#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_LOW_MSB _u(14) -#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_LOW_LSB _u(14) -#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_HIGH -#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_HIGH_BITS _u(0x00002000) -#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_HIGH_MSB _u(13) -#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_HIGH_LSB _u(13) -#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_LOW -#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_LOW_BITS _u(0x00001000) -#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_LOW_MSB _u(12) -#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_LOW_LSB _u(12) -#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF2_GPIO18_EDGE_HIGH -#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_HIGH_BITS _u(0x00000800) -#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_HIGH_MSB _u(11) -#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_HIGH_LSB _u(11) -#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF2_GPIO18_EDGE_LOW -#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_LOW_BITS _u(0x00000400) -#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_LOW_MSB _u(10) -#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_LOW_LSB _u(10) -#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_HIGH -#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_HIGH_BITS _u(0x00000200) -#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_HIGH_MSB _u(9) -#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_HIGH_LSB _u(9) -#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_LOW -#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_LOW_BITS _u(0x00000100) -#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_LOW_MSB _u(8) -#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_LOW_LSB _u(8) -#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF2_GPIO17_EDGE_HIGH -#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_HIGH_BITS _u(0x00000080) -#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_HIGH_MSB _u(7) -#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_HIGH_LSB _u(7) -#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF2_GPIO17_EDGE_LOW -#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_LOW_BITS _u(0x00000040) -#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_LOW_MSB _u(6) -#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_LOW_LSB _u(6) -#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_HIGH -#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_HIGH_BITS _u(0x00000020) -#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_HIGH_MSB _u(5) -#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_HIGH_LSB _u(5) -#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_LOW -#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_LOW_BITS _u(0x00000010) -#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_LOW_MSB _u(4) -#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_LOW_LSB _u(4) -#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF2_GPIO16_EDGE_HIGH -#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_HIGH_BITS _u(0x00000008) -#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_HIGH_MSB _u(3) -#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_HIGH_LSB _u(3) -#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF2_GPIO16_EDGE_LOW -#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_LOW_BITS _u(0x00000004) -#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_LOW_MSB _u(2) -#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_LOW_LSB _u(2) -#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_HIGH -#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_HIGH_BITS _u(0x00000002) -#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_HIGH_MSB _u(1) -#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_HIGH_LSB _u(1) -#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_LOW -#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_LOW_BITS _u(0x00000001) -#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_LOW_MSB _u(0) -#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_LOW_LSB _u(0) -#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_LOW_ACCESS "RW" -// ============================================================================= -// Register : IO_BANK0_PROC1_INTF3 -// Description : Interrupt Force for proc1 -#define IO_BANK0_PROC1_INTF3_OFFSET _u(0x000002b4) -#define IO_BANK0_PROC1_INTF3_BITS _u(0xffffffff) -#define IO_BANK0_PROC1_INTF3_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF3_GPIO31_EDGE_HIGH -#define IO_BANK0_PROC1_INTF3_GPIO31_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF3_GPIO31_EDGE_HIGH_BITS _u(0x80000000) -#define IO_BANK0_PROC1_INTF3_GPIO31_EDGE_HIGH_MSB _u(31) -#define IO_BANK0_PROC1_INTF3_GPIO31_EDGE_HIGH_LSB _u(31) -#define IO_BANK0_PROC1_INTF3_GPIO31_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF3_GPIO31_EDGE_LOW -#define IO_BANK0_PROC1_INTF3_GPIO31_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF3_GPIO31_EDGE_LOW_BITS _u(0x40000000) -#define IO_BANK0_PROC1_INTF3_GPIO31_EDGE_LOW_MSB _u(30) -#define IO_BANK0_PROC1_INTF3_GPIO31_EDGE_LOW_LSB _u(30) -#define IO_BANK0_PROC1_INTF3_GPIO31_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF3_GPIO31_LEVEL_HIGH -#define IO_BANK0_PROC1_INTF3_GPIO31_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF3_GPIO31_LEVEL_HIGH_BITS _u(0x20000000) -#define IO_BANK0_PROC1_INTF3_GPIO31_LEVEL_HIGH_MSB _u(29) -#define IO_BANK0_PROC1_INTF3_GPIO31_LEVEL_HIGH_LSB _u(29) -#define IO_BANK0_PROC1_INTF3_GPIO31_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF3_GPIO31_LEVEL_LOW -#define IO_BANK0_PROC1_INTF3_GPIO31_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF3_GPIO31_LEVEL_LOW_BITS _u(0x10000000) -#define IO_BANK0_PROC1_INTF3_GPIO31_LEVEL_LOW_MSB _u(28) -#define IO_BANK0_PROC1_INTF3_GPIO31_LEVEL_LOW_LSB _u(28) -#define IO_BANK0_PROC1_INTF3_GPIO31_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF3_GPIO30_EDGE_HIGH -#define IO_BANK0_PROC1_INTF3_GPIO30_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF3_GPIO30_EDGE_HIGH_BITS _u(0x08000000) -#define IO_BANK0_PROC1_INTF3_GPIO30_EDGE_HIGH_MSB _u(27) -#define IO_BANK0_PROC1_INTF3_GPIO30_EDGE_HIGH_LSB _u(27) -#define IO_BANK0_PROC1_INTF3_GPIO30_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF3_GPIO30_EDGE_LOW -#define IO_BANK0_PROC1_INTF3_GPIO30_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF3_GPIO30_EDGE_LOW_BITS _u(0x04000000) -#define IO_BANK0_PROC1_INTF3_GPIO30_EDGE_LOW_MSB _u(26) -#define IO_BANK0_PROC1_INTF3_GPIO30_EDGE_LOW_LSB _u(26) -#define IO_BANK0_PROC1_INTF3_GPIO30_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF3_GPIO30_LEVEL_HIGH -#define IO_BANK0_PROC1_INTF3_GPIO30_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF3_GPIO30_LEVEL_HIGH_BITS _u(0x02000000) -#define IO_BANK0_PROC1_INTF3_GPIO30_LEVEL_HIGH_MSB _u(25) -#define IO_BANK0_PROC1_INTF3_GPIO30_LEVEL_HIGH_LSB _u(25) -#define IO_BANK0_PROC1_INTF3_GPIO30_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF3_GPIO30_LEVEL_LOW -#define IO_BANK0_PROC1_INTF3_GPIO30_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF3_GPIO30_LEVEL_LOW_BITS _u(0x01000000) -#define IO_BANK0_PROC1_INTF3_GPIO30_LEVEL_LOW_MSB _u(24) -#define IO_BANK0_PROC1_INTF3_GPIO30_LEVEL_LOW_LSB _u(24) -#define IO_BANK0_PROC1_INTF3_GPIO30_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF3_GPIO29_EDGE_HIGH -#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_HIGH_BITS _u(0x00800000) -#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_HIGH_MSB _u(23) -#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_HIGH_LSB _u(23) -#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF3_GPIO29_EDGE_LOW -#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_LOW_BITS _u(0x00400000) -#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_LOW_MSB _u(22) -#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_LOW_LSB _u(22) -#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_HIGH -#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_HIGH_BITS _u(0x00200000) -#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_HIGH_MSB _u(21) -#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_HIGH_LSB _u(21) -#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_LOW -#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_LOW_BITS _u(0x00100000) -#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_LOW_MSB _u(20) -#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_LOW_LSB _u(20) -#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF3_GPIO28_EDGE_HIGH -#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_HIGH_BITS _u(0x00080000) -#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_HIGH_MSB _u(19) -#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_HIGH_LSB _u(19) -#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF3_GPIO28_EDGE_LOW -#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_LOW_BITS _u(0x00040000) -#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_LOW_MSB _u(18) -#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_LOW_LSB _u(18) -#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_HIGH -#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_HIGH_BITS _u(0x00020000) -#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_HIGH_MSB _u(17) -#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_HIGH_LSB _u(17) -#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_LOW -#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_LOW_BITS _u(0x00010000) -#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_LOW_MSB _u(16) -#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_LOW_LSB _u(16) -#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF3_GPIO27_EDGE_HIGH -#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_HIGH_BITS _u(0x00008000) -#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_HIGH_MSB _u(15) -#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_HIGH_LSB _u(15) -#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF3_GPIO27_EDGE_LOW -#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_LOW_BITS _u(0x00004000) -#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_LOW_MSB _u(14) -#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_LOW_LSB _u(14) -#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_HIGH -#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_HIGH_BITS _u(0x00002000) -#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_HIGH_MSB _u(13) -#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_HIGH_LSB _u(13) -#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_LOW -#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_LOW_BITS _u(0x00001000) -#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_LOW_MSB _u(12) -#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_LOW_LSB _u(12) -#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF3_GPIO26_EDGE_HIGH -#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_HIGH_BITS _u(0x00000800) -#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_HIGH_MSB _u(11) -#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_HIGH_LSB _u(11) -#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF3_GPIO26_EDGE_LOW -#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_LOW_BITS _u(0x00000400) -#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_LOW_MSB _u(10) -#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_LOW_LSB _u(10) -#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_HIGH -#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_HIGH_BITS _u(0x00000200) -#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_HIGH_MSB _u(9) -#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_HIGH_LSB _u(9) -#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_LOW -#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_LOW_BITS _u(0x00000100) -#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_LOW_MSB _u(8) -#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_LOW_LSB _u(8) -#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF3_GPIO25_EDGE_HIGH -#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_HIGH_BITS _u(0x00000080) -#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_HIGH_MSB _u(7) -#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_HIGH_LSB _u(7) -#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF3_GPIO25_EDGE_LOW -#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_LOW_BITS _u(0x00000040) -#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_LOW_MSB _u(6) -#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_LOW_LSB _u(6) -#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_HIGH -#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_HIGH_BITS _u(0x00000020) -#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_HIGH_MSB _u(5) -#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_HIGH_LSB _u(5) -#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_LOW -#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_LOW_BITS _u(0x00000010) -#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_LOW_MSB _u(4) -#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_LOW_LSB _u(4) -#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF3_GPIO24_EDGE_HIGH -#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_HIGH_BITS _u(0x00000008) -#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_HIGH_MSB _u(3) -#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_HIGH_LSB _u(3) -#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF3_GPIO24_EDGE_LOW -#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_LOW_BITS _u(0x00000004) -#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_LOW_MSB _u(2) -#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_LOW_LSB _u(2) -#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_HIGH -#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_HIGH_BITS _u(0x00000002) -#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_HIGH_MSB _u(1) -#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_HIGH_LSB _u(1) -#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_LOW -#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_LOW_BITS _u(0x00000001) -#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_LOW_MSB _u(0) -#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_LOW_LSB _u(0) -#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_LOW_ACCESS "RW" -// ============================================================================= -// Register : IO_BANK0_PROC1_INTF4 -// Description : Interrupt Force for proc1 -#define IO_BANK0_PROC1_INTF4_OFFSET _u(0x000002b8) -#define IO_BANK0_PROC1_INTF4_BITS _u(0xffffffff) -#define IO_BANK0_PROC1_INTF4_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF4_GPIO39_EDGE_HIGH -#define IO_BANK0_PROC1_INTF4_GPIO39_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF4_GPIO39_EDGE_HIGH_BITS _u(0x80000000) -#define IO_BANK0_PROC1_INTF4_GPIO39_EDGE_HIGH_MSB _u(31) -#define IO_BANK0_PROC1_INTF4_GPIO39_EDGE_HIGH_LSB _u(31) -#define IO_BANK0_PROC1_INTF4_GPIO39_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF4_GPIO39_EDGE_LOW -#define IO_BANK0_PROC1_INTF4_GPIO39_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF4_GPIO39_EDGE_LOW_BITS _u(0x40000000) -#define IO_BANK0_PROC1_INTF4_GPIO39_EDGE_LOW_MSB _u(30) -#define IO_BANK0_PROC1_INTF4_GPIO39_EDGE_LOW_LSB _u(30) -#define IO_BANK0_PROC1_INTF4_GPIO39_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF4_GPIO39_LEVEL_HIGH -#define IO_BANK0_PROC1_INTF4_GPIO39_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF4_GPIO39_LEVEL_HIGH_BITS _u(0x20000000) -#define IO_BANK0_PROC1_INTF4_GPIO39_LEVEL_HIGH_MSB _u(29) -#define IO_BANK0_PROC1_INTF4_GPIO39_LEVEL_HIGH_LSB _u(29) -#define IO_BANK0_PROC1_INTF4_GPIO39_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF4_GPIO39_LEVEL_LOW -#define IO_BANK0_PROC1_INTF4_GPIO39_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF4_GPIO39_LEVEL_LOW_BITS _u(0x10000000) -#define IO_BANK0_PROC1_INTF4_GPIO39_LEVEL_LOW_MSB _u(28) -#define IO_BANK0_PROC1_INTF4_GPIO39_LEVEL_LOW_LSB _u(28) -#define IO_BANK0_PROC1_INTF4_GPIO39_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF4_GPIO38_EDGE_HIGH -#define IO_BANK0_PROC1_INTF4_GPIO38_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF4_GPIO38_EDGE_HIGH_BITS _u(0x08000000) -#define IO_BANK0_PROC1_INTF4_GPIO38_EDGE_HIGH_MSB _u(27) -#define IO_BANK0_PROC1_INTF4_GPIO38_EDGE_HIGH_LSB _u(27) -#define IO_BANK0_PROC1_INTF4_GPIO38_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF4_GPIO38_EDGE_LOW -#define IO_BANK0_PROC1_INTF4_GPIO38_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF4_GPIO38_EDGE_LOW_BITS _u(0x04000000) -#define IO_BANK0_PROC1_INTF4_GPIO38_EDGE_LOW_MSB _u(26) -#define IO_BANK0_PROC1_INTF4_GPIO38_EDGE_LOW_LSB _u(26) -#define IO_BANK0_PROC1_INTF4_GPIO38_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF4_GPIO38_LEVEL_HIGH -#define IO_BANK0_PROC1_INTF4_GPIO38_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF4_GPIO38_LEVEL_HIGH_BITS _u(0x02000000) -#define IO_BANK0_PROC1_INTF4_GPIO38_LEVEL_HIGH_MSB _u(25) -#define IO_BANK0_PROC1_INTF4_GPIO38_LEVEL_HIGH_LSB _u(25) -#define IO_BANK0_PROC1_INTF4_GPIO38_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF4_GPIO38_LEVEL_LOW -#define IO_BANK0_PROC1_INTF4_GPIO38_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF4_GPIO38_LEVEL_LOW_BITS _u(0x01000000) -#define IO_BANK0_PROC1_INTF4_GPIO38_LEVEL_LOW_MSB _u(24) -#define IO_BANK0_PROC1_INTF4_GPIO38_LEVEL_LOW_LSB _u(24) -#define IO_BANK0_PROC1_INTF4_GPIO38_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF4_GPIO37_EDGE_HIGH -#define IO_BANK0_PROC1_INTF4_GPIO37_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF4_GPIO37_EDGE_HIGH_BITS _u(0x00800000) -#define IO_BANK0_PROC1_INTF4_GPIO37_EDGE_HIGH_MSB _u(23) -#define IO_BANK0_PROC1_INTF4_GPIO37_EDGE_HIGH_LSB _u(23) -#define IO_BANK0_PROC1_INTF4_GPIO37_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF4_GPIO37_EDGE_LOW -#define IO_BANK0_PROC1_INTF4_GPIO37_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF4_GPIO37_EDGE_LOW_BITS _u(0x00400000) -#define IO_BANK0_PROC1_INTF4_GPIO37_EDGE_LOW_MSB _u(22) -#define IO_BANK0_PROC1_INTF4_GPIO37_EDGE_LOW_LSB _u(22) -#define IO_BANK0_PROC1_INTF4_GPIO37_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF4_GPIO37_LEVEL_HIGH -#define IO_BANK0_PROC1_INTF4_GPIO37_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF4_GPIO37_LEVEL_HIGH_BITS _u(0x00200000) -#define IO_BANK0_PROC1_INTF4_GPIO37_LEVEL_HIGH_MSB _u(21) -#define IO_BANK0_PROC1_INTF4_GPIO37_LEVEL_HIGH_LSB _u(21) -#define IO_BANK0_PROC1_INTF4_GPIO37_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF4_GPIO37_LEVEL_LOW -#define IO_BANK0_PROC1_INTF4_GPIO37_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF4_GPIO37_LEVEL_LOW_BITS _u(0x00100000) -#define IO_BANK0_PROC1_INTF4_GPIO37_LEVEL_LOW_MSB _u(20) -#define IO_BANK0_PROC1_INTF4_GPIO37_LEVEL_LOW_LSB _u(20) -#define IO_BANK0_PROC1_INTF4_GPIO37_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF4_GPIO36_EDGE_HIGH -#define IO_BANK0_PROC1_INTF4_GPIO36_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF4_GPIO36_EDGE_HIGH_BITS _u(0x00080000) -#define IO_BANK0_PROC1_INTF4_GPIO36_EDGE_HIGH_MSB _u(19) -#define IO_BANK0_PROC1_INTF4_GPIO36_EDGE_HIGH_LSB _u(19) -#define IO_BANK0_PROC1_INTF4_GPIO36_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF4_GPIO36_EDGE_LOW -#define IO_BANK0_PROC1_INTF4_GPIO36_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF4_GPIO36_EDGE_LOW_BITS _u(0x00040000) -#define IO_BANK0_PROC1_INTF4_GPIO36_EDGE_LOW_MSB _u(18) -#define IO_BANK0_PROC1_INTF4_GPIO36_EDGE_LOW_LSB _u(18) -#define IO_BANK0_PROC1_INTF4_GPIO36_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF4_GPIO36_LEVEL_HIGH -#define IO_BANK0_PROC1_INTF4_GPIO36_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF4_GPIO36_LEVEL_HIGH_BITS _u(0x00020000) -#define IO_BANK0_PROC1_INTF4_GPIO36_LEVEL_HIGH_MSB _u(17) -#define IO_BANK0_PROC1_INTF4_GPIO36_LEVEL_HIGH_LSB _u(17) -#define IO_BANK0_PROC1_INTF4_GPIO36_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF4_GPIO36_LEVEL_LOW -#define IO_BANK0_PROC1_INTF4_GPIO36_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF4_GPIO36_LEVEL_LOW_BITS _u(0x00010000) -#define IO_BANK0_PROC1_INTF4_GPIO36_LEVEL_LOW_MSB _u(16) -#define IO_BANK0_PROC1_INTF4_GPIO36_LEVEL_LOW_LSB _u(16) -#define IO_BANK0_PROC1_INTF4_GPIO36_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF4_GPIO35_EDGE_HIGH -#define IO_BANK0_PROC1_INTF4_GPIO35_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF4_GPIO35_EDGE_HIGH_BITS _u(0x00008000) -#define IO_BANK0_PROC1_INTF4_GPIO35_EDGE_HIGH_MSB _u(15) -#define IO_BANK0_PROC1_INTF4_GPIO35_EDGE_HIGH_LSB _u(15) -#define IO_BANK0_PROC1_INTF4_GPIO35_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF4_GPIO35_EDGE_LOW -#define IO_BANK0_PROC1_INTF4_GPIO35_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF4_GPIO35_EDGE_LOW_BITS _u(0x00004000) -#define IO_BANK0_PROC1_INTF4_GPIO35_EDGE_LOW_MSB _u(14) -#define IO_BANK0_PROC1_INTF4_GPIO35_EDGE_LOW_LSB _u(14) -#define IO_BANK0_PROC1_INTF4_GPIO35_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF4_GPIO35_LEVEL_HIGH -#define IO_BANK0_PROC1_INTF4_GPIO35_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF4_GPIO35_LEVEL_HIGH_BITS _u(0x00002000) -#define IO_BANK0_PROC1_INTF4_GPIO35_LEVEL_HIGH_MSB _u(13) -#define IO_BANK0_PROC1_INTF4_GPIO35_LEVEL_HIGH_LSB _u(13) -#define IO_BANK0_PROC1_INTF4_GPIO35_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF4_GPIO35_LEVEL_LOW -#define IO_BANK0_PROC1_INTF4_GPIO35_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF4_GPIO35_LEVEL_LOW_BITS _u(0x00001000) -#define IO_BANK0_PROC1_INTF4_GPIO35_LEVEL_LOW_MSB _u(12) -#define IO_BANK0_PROC1_INTF4_GPIO35_LEVEL_LOW_LSB _u(12) -#define IO_BANK0_PROC1_INTF4_GPIO35_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF4_GPIO34_EDGE_HIGH -#define IO_BANK0_PROC1_INTF4_GPIO34_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF4_GPIO34_EDGE_HIGH_BITS _u(0x00000800) -#define IO_BANK0_PROC1_INTF4_GPIO34_EDGE_HIGH_MSB _u(11) -#define IO_BANK0_PROC1_INTF4_GPIO34_EDGE_HIGH_LSB _u(11) -#define IO_BANK0_PROC1_INTF4_GPIO34_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF4_GPIO34_EDGE_LOW -#define IO_BANK0_PROC1_INTF4_GPIO34_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF4_GPIO34_EDGE_LOW_BITS _u(0x00000400) -#define IO_BANK0_PROC1_INTF4_GPIO34_EDGE_LOW_MSB _u(10) -#define IO_BANK0_PROC1_INTF4_GPIO34_EDGE_LOW_LSB _u(10) -#define IO_BANK0_PROC1_INTF4_GPIO34_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF4_GPIO34_LEVEL_HIGH -#define IO_BANK0_PROC1_INTF4_GPIO34_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF4_GPIO34_LEVEL_HIGH_BITS _u(0x00000200) -#define IO_BANK0_PROC1_INTF4_GPIO34_LEVEL_HIGH_MSB _u(9) -#define IO_BANK0_PROC1_INTF4_GPIO34_LEVEL_HIGH_LSB _u(9) -#define IO_BANK0_PROC1_INTF4_GPIO34_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF4_GPIO34_LEVEL_LOW -#define IO_BANK0_PROC1_INTF4_GPIO34_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF4_GPIO34_LEVEL_LOW_BITS _u(0x00000100) -#define IO_BANK0_PROC1_INTF4_GPIO34_LEVEL_LOW_MSB _u(8) -#define IO_BANK0_PROC1_INTF4_GPIO34_LEVEL_LOW_LSB _u(8) -#define IO_BANK0_PROC1_INTF4_GPIO34_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF4_GPIO33_EDGE_HIGH -#define IO_BANK0_PROC1_INTF4_GPIO33_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF4_GPIO33_EDGE_HIGH_BITS _u(0x00000080) -#define IO_BANK0_PROC1_INTF4_GPIO33_EDGE_HIGH_MSB _u(7) -#define IO_BANK0_PROC1_INTF4_GPIO33_EDGE_HIGH_LSB _u(7) -#define IO_BANK0_PROC1_INTF4_GPIO33_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF4_GPIO33_EDGE_LOW -#define IO_BANK0_PROC1_INTF4_GPIO33_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF4_GPIO33_EDGE_LOW_BITS _u(0x00000040) -#define IO_BANK0_PROC1_INTF4_GPIO33_EDGE_LOW_MSB _u(6) -#define IO_BANK0_PROC1_INTF4_GPIO33_EDGE_LOW_LSB _u(6) -#define IO_BANK0_PROC1_INTF4_GPIO33_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF4_GPIO33_LEVEL_HIGH -#define IO_BANK0_PROC1_INTF4_GPIO33_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF4_GPIO33_LEVEL_HIGH_BITS _u(0x00000020) -#define IO_BANK0_PROC1_INTF4_GPIO33_LEVEL_HIGH_MSB _u(5) -#define IO_BANK0_PROC1_INTF4_GPIO33_LEVEL_HIGH_LSB _u(5) -#define IO_BANK0_PROC1_INTF4_GPIO33_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF4_GPIO33_LEVEL_LOW -#define IO_BANK0_PROC1_INTF4_GPIO33_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF4_GPIO33_LEVEL_LOW_BITS _u(0x00000010) -#define IO_BANK0_PROC1_INTF4_GPIO33_LEVEL_LOW_MSB _u(4) -#define IO_BANK0_PROC1_INTF4_GPIO33_LEVEL_LOW_LSB _u(4) -#define IO_BANK0_PROC1_INTF4_GPIO33_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF4_GPIO32_EDGE_HIGH -#define IO_BANK0_PROC1_INTF4_GPIO32_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF4_GPIO32_EDGE_HIGH_BITS _u(0x00000008) -#define IO_BANK0_PROC1_INTF4_GPIO32_EDGE_HIGH_MSB _u(3) -#define IO_BANK0_PROC1_INTF4_GPIO32_EDGE_HIGH_LSB _u(3) -#define IO_BANK0_PROC1_INTF4_GPIO32_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF4_GPIO32_EDGE_LOW -#define IO_BANK0_PROC1_INTF4_GPIO32_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF4_GPIO32_EDGE_LOW_BITS _u(0x00000004) -#define IO_BANK0_PROC1_INTF4_GPIO32_EDGE_LOW_MSB _u(2) -#define IO_BANK0_PROC1_INTF4_GPIO32_EDGE_LOW_LSB _u(2) -#define IO_BANK0_PROC1_INTF4_GPIO32_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF4_GPIO32_LEVEL_HIGH -#define IO_BANK0_PROC1_INTF4_GPIO32_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF4_GPIO32_LEVEL_HIGH_BITS _u(0x00000002) -#define IO_BANK0_PROC1_INTF4_GPIO32_LEVEL_HIGH_MSB _u(1) -#define IO_BANK0_PROC1_INTF4_GPIO32_LEVEL_HIGH_LSB _u(1) -#define IO_BANK0_PROC1_INTF4_GPIO32_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF4_GPIO32_LEVEL_LOW -#define IO_BANK0_PROC1_INTF4_GPIO32_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF4_GPIO32_LEVEL_LOW_BITS _u(0x00000001) -#define IO_BANK0_PROC1_INTF4_GPIO32_LEVEL_LOW_MSB _u(0) -#define IO_BANK0_PROC1_INTF4_GPIO32_LEVEL_LOW_LSB _u(0) -#define IO_BANK0_PROC1_INTF4_GPIO32_LEVEL_LOW_ACCESS "RW" -// ============================================================================= -// Register : IO_BANK0_PROC1_INTF5 -// Description : Interrupt Force for proc1 -#define IO_BANK0_PROC1_INTF5_OFFSET _u(0x000002bc) -#define IO_BANK0_PROC1_INTF5_BITS _u(0xffffffff) -#define IO_BANK0_PROC1_INTF5_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF5_GPIO47_EDGE_HIGH -#define IO_BANK0_PROC1_INTF5_GPIO47_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF5_GPIO47_EDGE_HIGH_BITS _u(0x80000000) -#define IO_BANK0_PROC1_INTF5_GPIO47_EDGE_HIGH_MSB _u(31) -#define IO_BANK0_PROC1_INTF5_GPIO47_EDGE_HIGH_LSB _u(31) -#define IO_BANK0_PROC1_INTF5_GPIO47_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF5_GPIO47_EDGE_LOW -#define IO_BANK0_PROC1_INTF5_GPIO47_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF5_GPIO47_EDGE_LOW_BITS _u(0x40000000) -#define IO_BANK0_PROC1_INTF5_GPIO47_EDGE_LOW_MSB _u(30) -#define IO_BANK0_PROC1_INTF5_GPIO47_EDGE_LOW_LSB _u(30) -#define IO_BANK0_PROC1_INTF5_GPIO47_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF5_GPIO47_LEVEL_HIGH -#define IO_BANK0_PROC1_INTF5_GPIO47_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF5_GPIO47_LEVEL_HIGH_BITS _u(0x20000000) -#define IO_BANK0_PROC1_INTF5_GPIO47_LEVEL_HIGH_MSB _u(29) -#define IO_BANK0_PROC1_INTF5_GPIO47_LEVEL_HIGH_LSB _u(29) -#define IO_BANK0_PROC1_INTF5_GPIO47_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF5_GPIO47_LEVEL_LOW -#define IO_BANK0_PROC1_INTF5_GPIO47_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF5_GPIO47_LEVEL_LOW_BITS _u(0x10000000) -#define IO_BANK0_PROC1_INTF5_GPIO47_LEVEL_LOW_MSB _u(28) -#define IO_BANK0_PROC1_INTF5_GPIO47_LEVEL_LOW_LSB _u(28) -#define IO_BANK0_PROC1_INTF5_GPIO47_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF5_GPIO46_EDGE_HIGH -#define IO_BANK0_PROC1_INTF5_GPIO46_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF5_GPIO46_EDGE_HIGH_BITS _u(0x08000000) -#define IO_BANK0_PROC1_INTF5_GPIO46_EDGE_HIGH_MSB _u(27) -#define IO_BANK0_PROC1_INTF5_GPIO46_EDGE_HIGH_LSB _u(27) -#define IO_BANK0_PROC1_INTF5_GPIO46_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF5_GPIO46_EDGE_LOW -#define IO_BANK0_PROC1_INTF5_GPIO46_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF5_GPIO46_EDGE_LOW_BITS _u(0x04000000) -#define IO_BANK0_PROC1_INTF5_GPIO46_EDGE_LOW_MSB _u(26) -#define IO_BANK0_PROC1_INTF5_GPIO46_EDGE_LOW_LSB _u(26) -#define IO_BANK0_PROC1_INTF5_GPIO46_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF5_GPIO46_LEVEL_HIGH -#define IO_BANK0_PROC1_INTF5_GPIO46_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF5_GPIO46_LEVEL_HIGH_BITS _u(0x02000000) -#define IO_BANK0_PROC1_INTF5_GPIO46_LEVEL_HIGH_MSB _u(25) -#define IO_BANK0_PROC1_INTF5_GPIO46_LEVEL_HIGH_LSB _u(25) -#define IO_BANK0_PROC1_INTF5_GPIO46_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF5_GPIO46_LEVEL_LOW -#define IO_BANK0_PROC1_INTF5_GPIO46_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF5_GPIO46_LEVEL_LOW_BITS _u(0x01000000) -#define IO_BANK0_PROC1_INTF5_GPIO46_LEVEL_LOW_MSB _u(24) -#define IO_BANK0_PROC1_INTF5_GPIO46_LEVEL_LOW_LSB _u(24) -#define IO_BANK0_PROC1_INTF5_GPIO46_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF5_GPIO45_EDGE_HIGH -#define IO_BANK0_PROC1_INTF5_GPIO45_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF5_GPIO45_EDGE_HIGH_BITS _u(0x00800000) -#define IO_BANK0_PROC1_INTF5_GPIO45_EDGE_HIGH_MSB _u(23) -#define IO_BANK0_PROC1_INTF5_GPIO45_EDGE_HIGH_LSB _u(23) -#define IO_BANK0_PROC1_INTF5_GPIO45_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF5_GPIO45_EDGE_LOW -#define IO_BANK0_PROC1_INTF5_GPIO45_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF5_GPIO45_EDGE_LOW_BITS _u(0x00400000) -#define IO_BANK0_PROC1_INTF5_GPIO45_EDGE_LOW_MSB _u(22) -#define IO_BANK0_PROC1_INTF5_GPIO45_EDGE_LOW_LSB _u(22) -#define IO_BANK0_PROC1_INTF5_GPIO45_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF5_GPIO45_LEVEL_HIGH -#define IO_BANK0_PROC1_INTF5_GPIO45_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF5_GPIO45_LEVEL_HIGH_BITS _u(0x00200000) -#define IO_BANK0_PROC1_INTF5_GPIO45_LEVEL_HIGH_MSB _u(21) -#define IO_BANK0_PROC1_INTF5_GPIO45_LEVEL_HIGH_LSB _u(21) -#define IO_BANK0_PROC1_INTF5_GPIO45_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF5_GPIO45_LEVEL_LOW -#define IO_BANK0_PROC1_INTF5_GPIO45_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF5_GPIO45_LEVEL_LOW_BITS _u(0x00100000) -#define IO_BANK0_PROC1_INTF5_GPIO45_LEVEL_LOW_MSB _u(20) -#define IO_BANK0_PROC1_INTF5_GPIO45_LEVEL_LOW_LSB _u(20) -#define IO_BANK0_PROC1_INTF5_GPIO45_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF5_GPIO44_EDGE_HIGH -#define IO_BANK0_PROC1_INTF5_GPIO44_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF5_GPIO44_EDGE_HIGH_BITS _u(0x00080000) -#define IO_BANK0_PROC1_INTF5_GPIO44_EDGE_HIGH_MSB _u(19) -#define IO_BANK0_PROC1_INTF5_GPIO44_EDGE_HIGH_LSB _u(19) -#define IO_BANK0_PROC1_INTF5_GPIO44_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF5_GPIO44_EDGE_LOW -#define IO_BANK0_PROC1_INTF5_GPIO44_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF5_GPIO44_EDGE_LOW_BITS _u(0x00040000) -#define IO_BANK0_PROC1_INTF5_GPIO44_EDGE_LOW_MSB _u(18) -#define IO_BANK0_PROC1_INTF5_GPIO44_EDGE_LOW_LSB _u(18) -#define IO_BANK0_PROC1_INTF5_GPIO44_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF5_GPIO44_LEVEL_HIGH -#define IO_BANK0_PROC1_INTF5_GPIO44_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF5_GPIO44_LEVEL_HIGH_BITS _u(0x00020000) -#define IO_BANK0_PROC1_INTF5_GPIO44_LEVEL_HIGH_MSB _u(17) -#define IO_BANK0_PROC1_INTF5_GPIO44_LEVEL_HIGH_LSB _u(17) -#define IO_BANK0_PROC1_INTF5_GPIO44_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF5_GPIO44_LEVEL_LOW -#define IO_BANK0_PROC1_INTF5_GPIO44_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF5_GPIO44_LEVEL_LOW_BITS _u(0x00010000) -#define IO_BANK0_PROC1_INTF5_GPIO44_LEVEL_LOW_MSB _u(16) -#define IO_BANK0_PROC1_INTF5_GPIO44_LEVEL_LOW_LSB _u(16) -#define IO_BANK0_PROC1_INTF5_GPIO44_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF5_GPIO43_EDGE_HIGH -#define IO_BANK0_PROC1_INTF5_GPIO43_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF5_GPIO43_EDGE_HIGH_BITS _u(0x00008000) -#define IO_BANK0_PROC1_INTF5_GPIO43_EDGE_HIGH_MSB _u(15) -#define IO_BANK0_PROC1_INTF5_GPIO43_EDGE_HIGH_LSB _u(15) -#define IO_BANK0_PROC1_INTF5_GPIO43_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF5_GPIO43_EDGE_LOW -#define IO_BANK0_PROC1_INTF5_GPIO43_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF5_GPIO43_EDGE_LOW_BITS _u(0x00004000) -#define IO_BANK0_PROC1_INTF5_GPIO43_EDGE_LOW_MSB _u(14) -#define IO_BANK0_PROC1_INTF5_GPIO43_EDGE_LOW_LSB _u(14) -#define IO_BANK0_PROC1_INTF5_GPIO43_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF5_GPIO43_LEVEL_HIGH -#define IO_BANK0_PROC1_INTF5_GPIO43_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF5_GPIO43_LEVEL_HIGH_BITS _u(0x00002000) -#define IO_BANK0_PROC1_INTF5_GPIO43_LEVEL_HIGH_MSB _u(13) -#define IO_BANK0_PROC1_INTF5_GPIO43_LEVEL_HIGH_LSB _u(13) -#define IO_BANK0_PROC1_INTF5_GPIO43_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF5_GPIO43_LEVEL_LOW -#define IO_BANK0_PROC1_INTF5_GPIO43_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF5_GPIO43_LEVEL_LOW_BITS _u(0x00001000) -#define IO_BANK0_PROC1_INTF5_GPIO43_LEVEL_LOW_MSB _u(12) -#define IO_BANK0_PROC1_INTF5_GPIO43_LEVEL_LOW_LSB _u(12) -#define IO_BANK0_PROC1_INTF5_GPIO43_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF5_GPIO42_EDGE_HIGH -#define IO_BANK0_PROC1_INTF5_GPIO42_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF5_GPIO42_EDGE_HIGH_BITS _u(0x00000800) -#define IO_BANK0_PROC1_INTF5_GPIO42_EDGE_HIGH_MSB _u(11) -#define IO_BANK0_PROC1_INTF5_GPIO42_EDGE_HIGH_LSB _u(11) -#define IO_BANK0_PROC1_INTF5_GPIO42_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF5_GPIO42_EDGE_LOW -#define IO_BANK0_PROC1_INTF5_GPIO42_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF5_GPIO42_EDGE_LOW_BITS _u(0x00000400) -#define IO_BANK0_PROC1_INTF5_GPIO42_EDGE_LOW_MSB _u(10) -#define IO_BANK0_PROC1_INTF5_GPIO42_EDGE_LOW_LSB _u(10) -#define IO_BANK0_PROC1_INTF5_GPIO42_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF5_GPIO42_LEVEL_HIGH -#define IO_BANK0_PROC1_INTF5_GPIO42_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF5_GPIO42_LEVEL_HIGH_BITS _u(0x00000200) -#define IO_BANK0_PROC1_INTF5_GPIO42_LEVEL_HIGH_MSB _u(9) -#define IO_BANK0_PROC1_INTF5_GPIO42_LEVEL_HIGH_LSB _u(9) -#define IO_BANK0_PROC1_INTF5_GPIO42_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF5_GPIO42_LEVEL_LOW -#define IO_BANK0_PROC1_INTF5_GPIO42_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF5_GPIO42_LEVEL_LOW_BITS _u(0x00000100) -#define IO_BANK0_PROC1_INTF5_GPIO42_LEVEL_LOW_MSB _u(8) -#define IO_BANK0_PROC1_INTF5_GPIO42_LEVEL_LOW_LSB _u(8) -#define IO_BANK0_PROC1_INTF5_GPIO42_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF5_GPIO41_EDGE_HIGH -#define IO_BANK0_PROC1_INTF5_GPIO41_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF5_GPIO41_EDGE_HIGH_BITS _u(0x00000080) -#define IO_BANK0_PROC1_INTF5_GPIO41_EDGE_HIGH_MSB _u(7) -#define IO_BANK0_PROC1_INTF5_GPIO41_EDGE_HIGH_LSB _u(7) -#define IO_BANK0_PROC1_INTF5_GPIO41_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF5_GPIO41_EDGE_LOW -#define IO_BANK0_PROC1_INTF5_GPIO41_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF5_GPIO41_EDGE_LOW_BITS _u(0x00000040) -#define IO_BANK0_PROC1_INTF5_GPIO41_EDGE_LOW_MSB _u(6) -#define IO_BANK0_PROC1_INTF5_GPIO41_EDGE_LOW_LSB _u(6) -#define IO_BANK0_PROC1_INTF5_GPIO41_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF5_GPIO41_LEVEL_HIGH -#define IO_BANK0_PROC1_INTF5_GPIO41_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF5_GPIO41_LEVEL_HIGH_BITS _u(0x00000020) -#define IO_BANK0_PROC1_INTF5_GPIO41_LEVEL_HIGH_MSB _u(5) -#define IO_BANK0_PROC1_INTF5_GPIO41_LEVEL_HIGH_LSB _u(5) -#define IO_BANK0_PROC1_INTF5_GPIO41_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF5_GPIO41_LEVEL_LOW -#define IO_BANK0_PROC1_INTF5_GPIO41_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF5_GPIO41_LEVEL_LOW_BITS _u(0x00000010) -#define IO_BANK0_PROC1_INTF5_GPIO41_LEVEL_LOW_MSB _u(4) -#define IO_BANK0_PROC1_INTF5_GPIO41_LEVEL_LOW_LSB _u(4) -#define IO_BANK0_PROC1_INTF5_GPIO41_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF5_GPIO40_EDGE_HIGH -#define IO_BANK0_PROC1_INTF5_GPIO40_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF5_GPIO40_EDGE_HIGH_BITS _u(0x00000008) -#define IO_BANK0_PROC1_INTF5_GPIO40_EDGE_HIGH_MSB _u(3) -#define IO_BANK0_PROC1_INTF5_GPIO40_EDGE_HIGH_LSB _u(3) -#define IO_BANK0_PROC1_INTF5_GPIO40_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF5_GPIO40_EDGE_LOW -#define IO_BANK0_PROC1_INTF5_GPIO40_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF5_GPIO40_EDGE_LOW_BITS _u(0x00000004) -#define IO_BANK0_PROC1_INTF5_GPIO40_EDGE_LOW_MSB _u(2) -#define IO_BANK0_PROC1_INTF5_GPIO40_EDGE_LOW_LSB _u(2) -#define IO_BANK0_PROC1_INTF5_GPIO40_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF5_GPIO40_LEVEL_HIGH -#define IO_BANK0_PROC1_INTF5_GPIO40_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF5_GPIO40_LEVEL_HIGH_BITS _u(0x00000002) -#define IO_BANK0_PROC1_INTF5_GPIO40_LEVEL_HIGH_MSB _u(1) -#define IO_BANK0_PROC1_INTF5_GPIO40_LEVEL_HIGH_LSB _u(1) -#define IO_BANK0_PROC1_INTF5_GPIO40_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTF5_GPIO40_LEVEL_LOW -#define IO_BANK0_PROC1_INTF5_GPIO40_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTF5_GPIO40_LEVEL_LOW_BITS _u(0x00000001) -#define IO_BANK0_PROC1_INTF5_GPIO40_LEVEL_LOW_MSB _u(0) -#define IO_BANK0_PROC1_INTF5_GPIO40_LEVEL_LOW_LSB _u(0) -#define IO_BANK0_PROC1_INTF5_GPIO40_LEVEL_LOW_ACCESS "RW" -// ============================================================================= -// Register : IO_BANK0_PROC1_INTS0 -// Description : Interrupt status after masking & forcing for proc1 -#define IO_BANK0_PROC1_INTS0_OFFSET _u(0x000002c0) -#define IO_BANK0_PROC1_INTS0_BITS _u(0xffffffff) -#define IO_BANK0_PROC1_INTS0_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS0_GPIO7_EDGE_HIGH -#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_HIGH_BITS _u(0x80000000) -#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_HIGH_MSB _u(31) -#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_HIGH_LSB _u(31) -#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS0_GPIO7_EDGE_LOW -#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_LOW_BITS _u(0x40000000) -#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_LOW_MSB _u(30) -#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_LOW_LSB _u(30) -#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_HIGH -#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_HIGH_BITS _u(0x20000000) -#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_HIGH_MSB _u(29) -#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_HIGH_LSB _u(29) -#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_LOW -#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_LOW_BITS _u(0x10000000) -#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_LOW_MSB _u(28) -#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_LOW_LSB _u(28) -#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS0_GPIO6_EDGE_HIGH -#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_HIGH_BITS _u(0x08000000) -#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_HIGH_MSB _u(27) -#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_HIGH_LSB _u(27) -#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS0_GPIO6_EDGE_LOW -#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_LOW_BITS _u(0x04000000) -#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_LOW_MSB _u(26) -#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_LOW_LSB _u(26) -#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_HIGH -#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_HIGH_BITS _u(0x02000000) -#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_HIGH_MSB _u(25) -#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_HIGH_LSB _u(25) -#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_LOW -#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_LOW_BITS _u(0x01000000) -#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_LOW_MSB _u(24) -#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_LOW_LSB _u(24) -#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS0_GPIO5_EDGE_HIGH -#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_HIGH_BITS _u(0x00800000) -#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_HIGH_MSB _u(23) -#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_HIGH_LSB _u(23) -#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS0_GPIO5_EDGE_LOW -#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_LOW_BITS _u(0x00400000) -#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_LOW_MSB _u(22) -#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_LOW_LSB _u(22) -#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_HIGH -#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_HIGH_BITS _u(0x00200000) -#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_HIGH_MSB _u(21) -#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_HIGH_LSB _u(21) -#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_LOW -#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_LOW_BITS _u(0x00100000) -#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_LOW_MSB _u(20) -#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_LOW_LSB _u(20) -#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS0_GPIO4_EDGE_HIGH -#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_HIGH_BITS _u(0x00080000) -#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_HIGH_MSB _u(19) -#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_HIGH_LSB _u(19) -#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS0_GPIO4_EDGE_LOW -#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_LOW_BITS _u(0x00040000) -#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_LOW_MSB _u(18) -#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_LOW_LSB _u(18) -#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_HIGH -#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_HIGH_BITS _u(0x00020000) -#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_HIGH_MSB _u(17) -#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_HIGH_LSB _u(17) -#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_LOW -#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_LOW_BITS _u(0x00010000) -#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_LOW_MSB _u(16) -#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_LOW_LSB _u(16) -#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS0_GPIO3_EDGE_HIGH -#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_HIGH_BITS _u(0x00008000) -#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_HIGH_MSB _u(15) -#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_HIGH_LSB _u(15) -#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS0_GPIO3_EDGE_LOW -#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_LOW_BITS _u(0x00004000) -#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_LOW_MSB _u(14) -#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_LOW_LSB _u(14) -#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_HIGH -#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_HIGH_BITS _u(0x00002000) -#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_HIGH_MSB _u(13) -#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_HIGH_LSB _u(13) -#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_LOW -#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_LOW_BITS _u(0x00001000) -#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_LOW_MSB _u(12) -#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_LOW_LSB _u(12) -#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS0_GPIO2_EDGE_HIGH -#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_HIGH_BITS _u(0x00000800) -#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_HIGH_MSB _u(11) -#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_HIGH_LSB _u(11) -#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS0_GPIO2_EDGE_LOW -#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_LOW_BITS _u(0x00000400) -#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_LOW_MSB _u(10) -#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_LOW_LSB _u(10) -#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_HIGH -#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_HIGH_BITS _u(0x00000200) -#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_HIGH_MSB _u(9) -#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_HIGH_LSB _u(9) -#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_LOW -#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_LOW_BITS _u(0x00000100) -#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_LOW_MSB _u(8) -#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_LOW_LSB _u(8) -#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS0_GPIO1_EDGE_HIGH -#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_HIGH_BITS _u(0x00000080) -#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_HIGH_MSB _u(7) -#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_HIGH_LSB _u(7) -#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS0_GPIO1_EDGE_LOW -#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_LOW_BITS _u(0x00000040) -#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_LOW_MSB _u(6) -#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_LOW_LSB _u(6) -#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_HIGH -#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_HIGH_BITS _u(0x00000020) -#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_HIGH_MSB _u(5) -#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_HIGH_LSB _u(5) -#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_LOW -#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_LOW_BITS _u(0x00000010) -#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_LOW_MSB _u(4) -#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_LOW_LSB _u(4) -#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS0_GPIO0_EDGE_HIGH -#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_HIGH_BITS _u(0x00000008) -#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_HIGH_MSB _u(3) -#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_HIGH_LSB _u(3) -#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS0_GPIO0_EDGE_LOW -#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_LOW_BITS _u(0x00000004) -#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_LOW_MSB _u(2) -#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_LOW_LSB _u(2) -#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_HIGH -#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_HIGH_BITS _u(0x00000002) -#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_HIGH_MSB _u(1) -#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_HIGH_LSB _u(1) -#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_LOW -#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_LOW_BITS _u(0x00000001) -#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_LOW_MSB _u(0) -#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_LOW_LSB _u(0) -#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_LOW_ACCESS "RO" -// ============================================================================= -// Register : IO_BANK0_PROC1_INTS1 -// Description : Interrupt status after masking & forcing for proc1 -#define IO_BANK0_PROC1_INTS1_OFFSET _u(0x000002c4) -#define IO_BANK0_PROC1_INTS1_BITS _u(0xffffffff) -#define IO_BANK0_PROC1_INTS1_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS1_GPIO15_EDGE_HIGH -#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_HIGH_BITS _u(0x80000000) -#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_HIGH_MSB _u(31) -#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_HIGH_LSB _u(31) -#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS1_GPIO15_EDGE_LOW -#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_LOW_BITS _u(0x40000000) -#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_LOW_MSB _u(30) -#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_LOW_LSB _u(30) -#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_HIGH -#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_HIGH_BITS _u(0x20000000) -#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_HIGH_MSB _u(29) -#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_HIGH_LSB _u(29) -#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_LOW -#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_LOW_BITS _u(0x10000000) -#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_LOW_MSB _u(28) -#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_LOW_LSB _u(28) -#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS1_GPIO14_EDGE_HIGH -#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_HIGH_BITS _u(0x08000000) -#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_HIGH_MSB _u(27) -#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_HIGH_LSB _u(27) -#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS1_GPIO14_EDGE_LOW -#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_LOW_BITS _u(0x04000000) -#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_LOW_MSB _u(26) -#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_LOW_LSB _u(26) -#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_HIGH -#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_HIGH_BITS _u(0x02000000) -#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_HIGH_MSB _u(25) -#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_HIGH_LSB _u(25) -#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_LOW -#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_LOW_BITS _u(0x01000000) -#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_LOW_MSB _u(24) -#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_LOW_LSB _u(24) -#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS1_GPIO13_EDGE_HIGH -#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_HIGH_BITS _u(0x00800000) -#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_HIGH_MSB _u(23) -#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_HIGH_LSB _u(23) -#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS1_GPIO13_EDGE_LOW -#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_LOW_BITS _u(0x00400000) -#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_LOW_MSB _u(22) -#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_LOW_LSB _u(22) -#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_HIGH -#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_HIGH_BITS _u(0x00200000) -#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_HIGH_MSB _u(21) -#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_HIGH_LSB _u(21) -#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_LOW -#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_LOW_BITS _u(0x00100000) -#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_LOW_MSB _u(20) -#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_LOW_LSB _u(20) -#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS1_GPIO12_EDGE_HIGH -#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_HIGH_BITS _u(0x00080000) -#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_HIGH_MSB _u(19) -#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_HIGH_LSB _u(19) -#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS1_GPIO12_EDGE_LOW -#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_LOW_BITS _u(0x00040000) -#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_LOW_MSB _u(18) -#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_LOW_LSB _u(18) -#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_HIGH -#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_HIGH_BITS _u(0x00020000) -#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_HIGH_MSB _u(17) -#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_HIGH_LSB _u(17) -#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_LOW -#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_LOW_BITS _u(0x00010000) -#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_LOW_MSB _u(16) -#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_LOW_LSB _u(16) -#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS1_GPIO11_EDGE_HIGH -#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_HIGH_BITS _u(0x00008000) -#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_HIGH_MSB _u(15) -#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_HIGH_LSB _u(15) -#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS1_GPIO11_EDGE_LOW -#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_LOW_BITS _u(0x00004000) -#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_LOW_MSB _u(14) -#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_LOW_LSB _u(14) -#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_HIGH -#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_HIGH_BITS _u(0x00002000) -#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_HIGH_MSB _u(13) -#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_HIGH_LSB _u(13) -#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_LOW -#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_LOW_BITS _u(0x00001000) -#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_LOW_MSB _u(12) -#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_LOW_LSB _u(12) -#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS1_GPIO10_EDGE_HIGH -#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_HIGH_BITS _u(0x00000800) -#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_HIGH_MSB _u(11) -#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_HIGH_LSB _u(11) -#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS1_GPIO10_EDGE_LOW -#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_LOW_BITS _u(0x00000400) -#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_LOW_MSB _u(10) -#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_LOW_LSB _u(10) -#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_HIGH -#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_HIGH_BITS _u(0x00000200) -#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_HIGH_MSB _u(9) -#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_HIGH_LSB _u(9) -#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_LOW -#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_LOW_BITS _u(0x00000100) -#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_LOW_MSB _u(8) -#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_LOW_LSB _u(8) -#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS1_GPIO9_EDGE_HIGH -#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_HIGH_BITS _u(0x00000080) -#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_HIGH_MSB _u(7) -#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_HIGH_LSB _u(7) -#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS1_GPIO9_EDGE_LOW -#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_LOW_BITS _u(0x00000040) -#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_LOW_MSB _u(6) -#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_LOW_LSB _u(6) -#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_HIGH -#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_HIGH_BITS _u(0x00000020) -#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_HIGH_MSB _u(5) -#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_HIGH_LSB _u(5) -#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_LOW -#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_LOW_BITS _u(0x00000010) -#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_LOW_MSB _u(4) -#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_LOW_LSB _u(4) -#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS1_GPIO8_EDGE_HIGH -#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_HIGH_BITS _u(0x00000008) -#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_HIGH_MSB _u(3) -#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_HIGH_LSB _u(3) -#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS1_GPIO8_EDGE_LOW -#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_LOW_BITS _u(0x00000004) -#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_LOW_MSB _u(2) -#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_LOW_LSB _u(2) -#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_HIGH -#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_HIGH_BITS _u(0x00000002) -#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_HIGH_MSB _u(1) -#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_HIGH_LSB _u(1) -#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_LOW -#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_LOW_BITS _u(0x00000001) -#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_LOW_MSB _u(0) -#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_LOW_LSB _u(0) -#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_LOW_ACCESS "RO" -// ============================================================================= -// Register : IO_BANK0_PROC1_INTS2 -// Description : Interrupt status after masking & forcing for proc1 -#define IO_BANK0_PROC1_INTS2_OFFSET _u(0x000002c8) -#define IO_BANK0_PROC1_INTS2_BITS _u(0xffffffff) -#define IO_BANK0_PROC1_INTS2_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS2_GPIO23_EDGE_HIGH -#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_HIGH_BITS _u(0x80000000) -#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_HIGH_MSB _u(31) -#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_HIGH_LSB _u(31) -#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS2_GPIO23_EDGE_LOW -#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_LOW_BITS _u(0x40000000) -#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_LOW_MSB _u(30) -#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_LOW_LSB _u(30) -#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_HIGH -#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_HIGH_BITS _u(0x20000000) -#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_HIGH_MSB _u(29) -#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_HIGH_LSB _u(29) -#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_LOW -#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_LOW_BITS _u(0x10000000) -#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_LOW_MSB _u(28) -#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_LOW_LSB _u(28) -#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS2_GPIO22_EDGE_HIGH -#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_HIGH_BITS _u(0x08000000) -#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_HIGH_MSB _u(27) -#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_HIGH_LSB _u(27) -#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS2_GPIO22_EDGE_LOW -#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_LOW_BITS _u(0x04000000) -#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_LOW_MSB _u(26) -#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_LOW_LSB _u(26) -#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_HIGH -#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_HIGH_BITS _u(0x02000000) -#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_HIGH_MSB _u(25) -#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_HIGH_LSB _u(25) -#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_LOW -#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_LOW_BITS _u(0x01000000) -#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_LOW_MSB _u(24) -#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_LOW_LSB _u(24) -#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS2_GPIO21_EDGE_HIGH -#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_HIGH_BITS _u(0x00800000) -#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_HIGH_MSB _u(23) -#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_HIGH_LSB _u(23) -#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS2_GPIO21_EDGE_LOW -#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_LOW_BITS _u(0x00400000) -#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_LOW_MSB _u(22) -#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_LOW_LSB _u(22) -#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_HIGH -#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_HIGH_BITS _u(0x00200000) -#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_HIGH_MSB _u(21) -#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_HIGH_LSB _u(21) -#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_LOW -#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_LOW_BITS _u(0x00100000) -#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_LOW_MSB _u(20) -#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_LOW_LSB _u(20) -#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS2_GPIO20_EDGE_HIGH -#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_HIGH_BITS _u(0x00080000) -#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_HIGH_MSB _u(19) -#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_HIGH_LSB _u(19) -#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS2_GPIO20_EDGE_LOW -#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_LOW_BITS _u(0x00040000) -#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_LOW_MSB _u(18) -#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_LOW_LSB _u(18) -#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_HIGH -#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_HIGH_BITS _u(0x00020000) -#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_HIGH_MSB _u(17) -#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_HIGH_LSB _u(17) -#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_LOW -#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_LOW_BITS _u(0x00010000) -#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_LOW_MSB _u(16) -#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_LOW_LSB _u(16) -#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS2_GPIO19_EDGE_HIGH -#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_HIGH_BITS _u(0x00008000) -#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_HIGH_MSB _u(15) -#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_HIGH_LSB _u(15) -#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS2_GPIO19_EDGE_LOW -#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_LOW_BITS _u(0x00004000) -#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_LOW_MSB _u(14) -#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_LOW_LSB _u(14) -#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_HIGH -#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_HIGH_BITS _u(0x00002000) -#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_HIGH_MSB _u(13) -#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_HIGH_LSB _u(13) -#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_LOW -#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_LOW_BITS _u(0x00001000) -#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_LOW_MSB _u(12) -#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_LOW_LSB _u(12) -#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS2_GPIO18_EDGE_HIGH -#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_HIGH_BITS _u(0x00000800) -#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_HIGH_MSB _u(11) -#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_HIGH_LSB _u(11) -#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS2_GPIO18_EDGE_LOW -#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_LOW_BITS _u(0x00000400) -#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_LOW_MSB _u(10) -#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_LOW_LSB _u(10) -#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_HIGH -#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_HIGH_BITS _u(0x00000200) -#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_HIGH_MSB _u(9) -#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_HIGH_LSB _u(9) -#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_LOW -#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_LOW_BITS _u(0x00000100) -#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_LOW_MSB _u(8) -#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_LOW_LSB _u(8) -#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS2_GPIO17_EDGE_HIGH -#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_HIGH_BITS _u(0x00000080) -#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_HIGH_MSB _u(7) -#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_HIGH_LSB _u(7) -#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS2_GPIO17_EDGE_LOW -#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_LOW_BITS _u(0x00000040) -#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_LOW_MSB _u(6) -#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_LOW_LSB _u(6) -#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_HIGH -#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_HIGH_BITS _u(0x00000020) -#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_HIGH_MSB _u(5) -#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_HIGH_LSB _u(5) -#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_LOW -#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_LOW_BITS _u(0x00000010) -#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_LOW_MSB _u(4) -#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_LOW_LSB _u(4) -#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS2_GPIO16_EDGE_HIGH -#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_HIGH_BITS _u(0x00000008) -#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_HIGH_MSB _u(3) -#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_HIGH_LSB _u(3) -#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS2_GPIO16_EDGE_LOW -#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_LOW_BITS _u(0x00000004) -#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_LOW_MSB _u(2) -#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_LOW_LSB _u(2) -#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_HIGH -#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_HIGH_BITS _u(0x00000002) -#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_HIGH_MSB _u(1) -#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_HIGH_LSB _u(1) -#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_LOW -#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_LOW_BITS _u(0x00000001) -#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_LOW_MSB _u(0) -#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_LOW_LSB _u(0) -#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_LOW_ACCESS "RO" -// ============================================================================= -// Register : IO_BANK0_PROC1_INTS3 -// Description : Interrupt status after masking & forcing for proc1 -#define IO_BANK0_PROC1_INTS3_OFFSET _u(0x000002cc) -#define IO_BANK0_PROC1_INTS3_BITS _u(0xffffffff) -#define IO_BANK0_PROC1_INTS3_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS3_GPIO31_EDGE_HIGH -#define IO_BANK0_PROC1_INTS3_GPIO31_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS3_GPIO31_EDGE_HIGH_BITS _u(0x80000000) -#define IO_BANK0_PROC1_INTS3_GPIO31_EDGE_HIGH_MSB _u(31) -#define IO_BANK0_PROC1_INTS3_GPIO31_EDGE_HIGH_LSB _u(31) -#define IO_BANK0_PROC1_INTS3_GPIO31_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS3_GPIO31_EDGE_LOW -#define IO_BANK0_PROC1_INTS3_GPIO31_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS3_GPIO31_EDGE_LOW_BITS _u(0x40000000) -#define IO_BANK0_PROC1_INTS3_GPIO31_EDGE_LOW_MSB _u(30) -#define IO_BANK0_PROC1_INTS3_GPIO31_EDGE_LOW_LSB _u(30) -#define IO_BANK0_PROC1_INTS3_GPIO31_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS3_GPIO31_LEVEL_HIGH -#define IO_BANK0_PROC1_INTS3_GPIO31_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS3_GPIO31_LEVEL_HIGH_BITS _u(0x20000000) -#define IO_BANK0_PROC1_INTS3_GPIO31_LEVEL_HIGH_MSB _u(29) -#define IO_BANK0_PROC1_INTS3_GPIO31_LEVEL_HIGH_LSB _u(29) -#define IO_BANK0_PROC1_INTS3_GPIO31_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS3_GPIO31_LEVEL_LOW -#define IO_BANK0_PROC1_INTS3_GPIO31_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS3_GPIO31_LEVEL_LOW_BITS _u(0x10000000) -#define IO_BANK0_PROC1_INTS3_GPIO31_LEVEL_LOW_MSB _u(28) -#define IO_BANK0_PROC1_INTS3_GPIO31_LEVEL_LOW_LSB _u(28) -#define IO_BANK0_PROC1_INTS3_GPIO31_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS3_GPIO30_EDGE_HIGH -#define IO_BANK0_PROC1_INTS3_GPIO30_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS3_GPIO30_EDGE_HIGH_BITS _u(0x08000000) -#define IO_BANK0_PROC1_INTS3_GPIO30_EDGE_HIGH_MSB _u(27) -#define IO_BANK0_PROC1_INTS3_GPIO30_EDGE_HIGH_LSB _u(27) -#define IO_BANK0_PROC1_INTS3_GPIO30_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS3_GPIO30_EDGE_LOW -#define IO_BANK0_PROC1_INTS3_GPIO30_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS3_GPIO30_EDGE_LOW_BITS _u(0x04000000) -#define IO_BANK0_PROC1_INTS3_GPIO30_EDGE_LOW_MSB _u(26) -#define IO_BANK0_PROC1_INTS3_GPIO30_EDGE_LOW_LSB _u(26) -#define IO_BANK0_PROC1_INTS3_GPIO30_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS3_GPIO30_LEVEL_HIGH -#define IO_BANK0_PROC1_INTS3_GPIO30_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS3_GPIO30_LEVEL_HIGH_BITS _u(0x02000000) -#define IO_BANK0_PROC1_INTS3_GPIO30_LEVEL_HIGH_MSB _u(25) -#define IO_BANK0_PROC1_INTS3_GPIO30_LEVEL_HIGH_LSB _u(25) -#define IO_BANK0_PROC1_INTS3_GPIO30_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS3_GPIO30_LEVEL_LOW -#define IO_BANK0_PROC1_INTS3_GPIO30_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS3_GPIO30_LEVEL_LOW_BITS _u(0x01000000) -#define IO_BANK0_PROC1_INTS3_GPIO30_LEVEL_LOW_MSB _u(24) -#define IO_BANK0_PROC1_INTS3_GPIO30_LEVEL_LOW_LSB _u(24) -#define IO_BANK0_PROC1_INTS3_GPIO30_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS3_GPIO29_EDGE_HIGH -#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_HIGH_BITS _u(0x00800000) -#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_HIGH_MSB _u(23) -#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_HIGH_LSB _u(23) -#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS3_GPIO29_EDGE_LOW -#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_LOW_BITS _u(0x00400000) -#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_LOW_MSB _u(22) -#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_LOW_LSB _u(22) -#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_HIGH -#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_HIGH_BITS _u(0x00200000) -#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_HIGH_MSB _u(21) -#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_HIGH_LSB _u(21) -#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_LOW -#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_LOW_BITS _u(0x00100000) -#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_LOW_MSB _u(20) -#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_LOW_LSB _u(20) -#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS3_GPIO28_EDGE_HIGH -#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_HIGH_BITS _u(0x00080000) -#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_HIGH_MSB _u(19) -#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_HIGH_LSB _u(19) -#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS3_GPIO28_EDGE_LOW -#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_LOW_BITS _u(0x00040000) -#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_LOW_MSB _u(18) -#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_LOW_LSB _u(18) -#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_HIGH -#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_HIGH_BITS _u(0x00020000) -#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_HIGH_MSB _u(17) -#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_HIGH_LSB _u(17) -#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_LOW -#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_LOW_BITS _u(0x00010000) -#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_LOW_MSB _u(16) -#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_LOW_LSB _u(16) -#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS3_GPIO27_EDGE_HIGH -#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_HIGH_BITS _u(0x00008000) -#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_HIGH_MSB _u(15) -#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_HIGH_LSB _u(15) -#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS3_GPIO27_EDGE_LOW -#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_LOW_BITS _u(0x00004000) -#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_LOW_MSB _u(14) -#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_LOW_LSB _u(14) -#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_HIGH -#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_HIGH_BITS _u(0x00002000) -#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_HIGH_MSB _u(13) -#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_HIGH_LSB _u(13) -#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_LOW -#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_LOW_BITS _u(0x00001000) -#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_LOW_MSB _u(12) -#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_LOW_LSB _u(12) -#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS3_GPIO26_EDGE_HIGH -#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_HIGH_BITS _u(0x00000800) -#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_HIGH_MSB _u(11) -#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_HIGH_LSB _u(11) -#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS3_GPIO26_EDGE_LOW -#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_LOW_BITS _u(0x00000400) -#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_LOW_MSB _u(10) -#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_LOW_LSB _u(10) -#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_HIGH -#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_HIGH_BITS _u(0x00000200) -#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_HIGH_MSB _u(9) -#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_HIGH_LSB _u(9) -#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_LOW -#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_LOW_BITS _u(0x00000100) -#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_LOW_MSB _u(8) -#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_LOW_LSB _u(8) -#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS3_GPIO25_EDGE_HIGH -#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_HIGH_BITS _u(0x00000080) -#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_HIGH_MSB _u(7) -#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_HIGH_LSB _u(7) -#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS3_GPIO25_EDGE_LOW -#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_LOW_BITS _u(0x00000040) -#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_LOW_MSB _u(6) -#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_LOW_LSB _u(6) -#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_HIGH -#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_HIGH_BITS _u(0x00000020) -#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_HIGH_MSB _u(5) -#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_HIGH_LSB _u(5) -#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_LOW -#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_LOW_BITS _u(0x00000010) -#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_LOW_MSB _u(4) -#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_LOW_LSB _u(4) -#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS3_GPIO24_EDGE_HIGH -#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_HIGH_BITS _u(0x00000008) -#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_HIGH_MSB _u(3) -#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_HIGH_LSB _u(3) -#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS3_GPIO24_EDGE_LOW -#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_LOW_BITS _u(0x00000004) -#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_LOW_MSB _u(2) -#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_LOW_LSB _u(2) -#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_HIGH -#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_HIGH_BITS _u(0x00000002) -#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_HIGH_MSB _u(1) -#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_HIGH_LSB _u(1) -#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_LOW -#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_LOW_BITS _u(0x00000001) -#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_LOW_MSB _u(0) -#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_LOW_LSB _u(0) -#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_LOW_ACCESS "RO" -// ============================================================================= -// Register : IO_BANK0_PROC1_INTS4 -// Description : Interrupt status after masking & forcing for proc1 -#define IO_BANK0_PROC1_INTS4_OFFSET _u(0x000002d0) -#define IO_BANK0_PROC1_INTS4_BITS _u(0xffffffff) -#define IO_BANK0_PROC1_INTS4_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS4_GPIO39_EDGE_HIGH -#define IO_BANK0_PROC1_INTS4_GPIO39_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS4_GPIO39_EDGE_HIGH_BITS _u(0x80000000) -#define IO_BANK0_PROC1_INTS4_GPIO39_EDGE_HIGH_MSB _u(31) -#define IO_BANK0_PROC1_INTS4_GPIO39_EDGE_HIGH_LSB _u(31) -#define IO_BANK0_PROC1_INTS4_GPIO39_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS4_GPIO39_EDGE_LOW -#define IO_BANK0_PROC1_INTS4_GPIO39_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS4_GPIO39_EDGE_LOW_BITS _u(0x40000000) -#define IO_BANK0_PROC1_INTS4_GPIO39_EDGE_LOW_MSB _u(30) -#define IO_BANK0_PROC1_INTS4_GPIO39_EDGE_LOW_LSB _u(30) -#define IO_BANK0_PROC1_INTS4_GPIO39_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS4_GPIO39_LEVEL_HIGH -#define IO_BANK0_PROC1_INTS4_GPIO39_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS4_GPIO39_LEVEL_HIGH_BITS _u(0x20000000) -#define IO_BANK0_PROC1_INTS4_GPIO39_LEVEL_HIGH_MSB _u(29) -#define IO_BANK0_PROC1_INTS4_GPIO39_LEVEL_HIGH_LSB _u(29) -#define IO_BANK0_PROC1_INTS4_GPIO39_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS4_GPIO39_LEVEL_LOW -#define IO_BANK0_PROC1_INTS4_GPIO39_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS4_GPIO39_LEVEL_LOW_BITS _u(0x10000000) -#define IO_BANK0_PROC1_INTS4_GPIO39_LEVEL_LOW_MSB _u(28) -#define IO_BANK0_PROC1_INTS4_GPIO39_LEVEL_LOW_LSB _u(28) -#define IO_BANK0_PROC1_INTS4_GPIO39_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS4_GPIO38_EDGE_HIGH -#define IO_BANK0_PROC1_INTS4_GPIO38_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS4_GPIO38_EDGE_HIGH_BITS _u(0x08000000) -#define IO_BANK0_PROC1_INTS4_GPIO38_EDGE_HIGH_MSB _u(27) -#define IO_BANK0_PROC1_INTS4_GPIO38_EDGE_HIGH_LSB _u(27) -#define IO_BANK0_PROC1_INTS4_GPIO38_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS4_GPIO38_EDGE_LOW -#define IO_BANK0_PROC1_INTS4_GPIO38_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS4_GPIO38_EDGE_LOW_BITS _u(0x04000000) -#define IO_BANK0_PROC1_INTS4_GPIO38_EDGE_LOW_MSB _u(26) -#define IO_BANK0_PROC1_INTS4_GPIO38_EDGE_LOW_LSB _u(26) -#define IO_BANK0_PROC1_INTS4_GPIO38_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS4_GPIO38_LEVEL_HIGH -#define IO_BANK0_PROC1_INTS4_GPIO38_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS4_GPIO38_LEVEL_HIGH_BITS _u(0x02000000) -#define IO_BANK0_PROC1_INTS4_GPIO38_LEVEL_HIGH_MSB _u(25) -#define IO_BANK0_PROC1_INTS4_GPIO38_LEVEL_HIGH_LSB _u(25) -#define IO_BANK0_PROC1_INTS4_GPIO38_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS4_GPIO38_LEVEL_LOW -#define IO_BANK0_PROC1_INTS4_GPIO38_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS4_GPIO38_LEVEL_LOW_BITS _u(0x01000000) -#define IO_BANK0_PROC1_INTS4_GPIO38_LEVEL_LOW_MSB _u(24) -#define IO_BANK0_PROC1_INTS4_GPIO38_LEVEL_LOW_LSB _u(24) -#define IO_BANK0_PROC1_INTS4_GPIO38_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS4_GPIO37_EDGE_HIGH -#define IO_BANK0_PROC1_INTS4_GPIO37_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS4_GPIO37_EDGE_HIGH_BITS _u(0x00800000) -#define IO_BANK0_PROC1_INTS4_GPIO37_EDGE_HIGH_MSB _u(23) -#define IO_BANK0_PROC1_INTS4_GPIO37_EDGE_HIGH_LSB _u(23) -#define IO_BANK0_PROC1_INTS4_GPIO37_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS4_GPIO37_EDGE_LOW -#define IO_BANK0_PROC1_INTS4_GPIO37_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS4_GPIO37_EDGE_LOW_BITS _u(0x00400000) -#define IO_BANK0_PROC1_INTS4_GPIO37_EDGE_LOW_MSB _u(22) -#define IO_BANK0_PROC1_INTS4_GPIO37_EDGE_LOW_LSB _u(22) -#define IO_BANK0_PROC1_INTS4_GPIO37_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS4_GPIO37_LEVEL_HIGH -#define IO_BANK0_PROC1_INTS4_GPIO37_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS4_GPIO37_LEVEL_HIGH_BITS _u(0x00200000) -#define IO_BANK0_PROC1_INTS4_GPIO37_LEVEL_HIGH_MSB _u(21) -#define IO_BANK0_PROC1_INTS4_GPIO37_LEVEL_HIGH_LSB _u(21) -#define IO_BANK0_PROC1_INTS4_GPIO37_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS4_GPIO37_LEVEL_LOW -#define IO_BANK0_PROC1_INTS4_GPIO37_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS4_GPIO37_LEVEL_LOW_BITS _u(0x00100000) -#define IO_BANK0_PROC1_INTS4_GPIO37_LEVEL_LOW_MSB _u(20) -#define IO_BANK0_PROC1_INTS4_GPIO37_LEVEL_LOW_LSB _u(20) -#define IO_BANK0_PROC1_INTS4_GPIO37_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS4_GPIO36_EDGE_HIGH -#define IO_BANK0_PROC1_INTS4_GPIO36_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS4_GPIO36_EDGE_HIGH_BITS _u(0x00080000) -#define IO_BANK0_PROC1_INTS4_GPIO36_EDGE_HIGH_MSB _u(19) -#define IO_BANK0_PROC1_INTS4_GPIO36_EDGE_HIGH_LSB _u(19) -#define IO_BANK0_PROC1_INTS4_GPIO36_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS4_GPIO36_EDGE_LOW -#define IO_BANK0_PROC1_INTS4_GPIO36_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS4_GPIO36_EDGE_LOW_BITS _u(0x00040000) -#define IO_BANK0_PROC1_INTS4_GPIO36_EDGE_LOW_MSB _u(18) -#define IO_BANK0_PROC1_INTS4_GPIO36_EDGE_LOW_LSB _u(18) -#define IO_BANK0_PROC1_INTS4_GPIO36_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS4_GPIO36_LEVEL_HIGH -#define IO_BANK0_PROC1_INTS4_GPIO36_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS4_GPIO36_LEVEL_HIGH_BITS _u(0x00020000) -#define IO_BANK0_PROC1_INTS4_GPIO36_LEVEL_HIGH_MSB _u(17) -#define IO_BANK0_PROC1_INTS4_GPIO36_LEVEL_HIGH_LSB _u(17) -#define IO_BANK0_PROC1_INTS4_GPIO36_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS4_GPIO36_LEVEL_LOW -#define IO_BANK0_PROC1_INTS4_GPIO36_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS4_GPIO36_LEVEL_LOW_BITS _u(0x00010000) -#define IO_BANK0_PROC1_INTS4_GPIO36_LEVEL_LOW_MSB _u(16) -#define IO_BANK0_PROC1_INTS4_GPIO36_LEVEL_LOW_LSB _u(16) -#define IO_BANK0_PROC1_INTS4_GPIO36_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS4_GPIO35_EDGE_HIGH -#define IO_BANK0_PROC1_INTS4_GPIO35_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS4_GPIO35_EDGE_HIGH_BITS _u(0x00008000) -#define IO_BANK0_PROC1_INTS4_GPIO35_EDGE_HIGH_MSB _u(15) -#define IO_BANK0_PROC1_INTS4_GPIO35_EDGE_HIGH_LSB _u(15) -#define IO_BANK0_PROC1_INTS4_GPIO35_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS4_GPIO35_EDGE_LOW -#define IO_BANK0_PROC1_INTS4_GPIO35_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS4_GPIO35_EDGE_LOW_BITS _u(0x00004000) -#define IO_BANK0_PROC1_INTS4_GPIO35_EDGE_LOW_MSB _u(14) -#define IO_BANK0_PROC1_INTS4_GPIO35_EDGE_LOW_LSB _u(14) -#define IO_BANK0_PROC1_INTS4_GPIO35_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS4_GPIO35_LEVEL_HIGH -#define IO_BANK0_PROC1_INTS4_GPIO35_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS4_GPIO35_LEVEL_HIGH_BITS _u(0x00002000) -#define IO_BANK0_PROC1_INTS4_GPIO35_LEVEL_HIGH_MSB _u(13) -#define IO_BANK0_PROC1_INTS4_GPIO35_LEVEL_HIGH_LSB _u(13) -#define IO_BANK0_PROC1_INTS4_GPIO35_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS4_GPIO35_LEVEL_LOW -#define IO_BANK0_PROC1_INTS4_GPIO35_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS4_GPIO35_LEVEL_LOW_BITS _u(0x00001000) -#define IO_BANK0_PROC1_INTS4_GPIO35_LEVEL_LOW_MSB _u(12) -#define IO_BANK0_PROC1_INTS4_GPIO35_LEVEL_LOW_LSB _u(12) -#define IO_BANK0_PROC1_INTS4_GPIO35_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS4_GPIO34_EDGE_HIGH -#define IO_BANK0_PROC1_INTS4_GPIO34_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS4_GPIO34_EDGE_HIGH_BITS _u(0x00000800) -#define IO_BANK0_PROC1_INTS4_GPIO34_EDGE_HIGH_MSB _u(11) -#define IO_BANK0_PROC1_INTS4_GPIO34_EDGE_HIGH_LSB _u(11) -#define IO_BANK0_PROC1_INTS4_GPIO34_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS4_GPIO34_EDGE_LOW -#define IO_BANK0_PROC1_INTS4_GPIO34_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS4_GPIO34_EDGE_LOW_BITS _u(0x00000400) -#define IO_BANK0_PROC1_INTS4_GPIO34_EDGE_LOW_MSB _u(10) -#define IO_BANK0_PROC1_INTS4_GPIO34_EDGE_LOW_LSB _u(10) -#define IO_BANK0_PROC1_INTS4_GPIO34_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS4_GPIO34_LEVEL_HIGH -#define IO_BANK0_PROC1_INTS4_GPIO34_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS4_GPIO34_LEVEL_HIGH_BITS _u(0x00000200) -#define IO_BANK0_PROC1_INTS4_GPIO34_LEVEL_HIGH_MSB _u(9) -#define IO_BANK0_PROC1_INTS4_GPIO34_LEVEL_HIGH_LSB _u(9) -#define IO_BANK0_PROC1_INTS4_GPIO34_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS4_GPIO34_LEVEL_LOW -#define IO_BANK0_PROC1_INTS4_GPIO34_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS4_GPIO34_LEVEL_LOW_BITS _u(0x00000100) -#define IO_BANK0_PROC1_INTS4_GPIO34_LEVEL_LOW_MSB _u(8) -#define IO_BANK0_PROC1_INTS4_GPIO34_LEVEL_LOW_LSB _u(8) -#define IO_BANK0_PROC1_INTS4_GPIO34_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS4_GPIO33_EDGE_HIGH -#define IO_BANK0_PROC1_INTS4_GPIO33_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS4_GPIO33_EDGE_HIGH_BITS _u(0x00000080) -#define IO_BANK0_PROC1_INTS4_GPIO33_EDGE_HIGH_MSB _u(7) -#define IO_BANK0_PROC1_INTS4_GPIO33_EDGE_HIGH_LSB _u(7) -#define IO_BANK0_PROC1_INTS4_GPIO33_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS4_GPIO33_EDGE_LOW -#define IO_BANK0_PROC1_INTS4_GPIO33_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS4_GPIO33_EDGE_LOW_BITS _u(0x00000040) -#define IO_BANK0_PROC1_INTS4_GPIO33_EDGE_LOW_MSB _u(6) -#define IO_BANK0_PROC1_INTS4_GPIO33_EDGE_LOW_LSB _u(6) -#define IO_BANK0_PROC1_INTS4_GPIO33_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS4_GPIO33_LEVEL_HIGH -#define IO_BANK0_PROC1_INTS4_GPIO33_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS4_GPIO33_LEVEL_HIGH_BITS _u(0x00000020) -#define IO_BANK0_PROC1_INTS4_GPIO33_LEVEL_HIGH_MSB _u(5) -#define IO_BANK0_PROC1_INTS4_GPIO33_LEVEL_HIGH_LSB _u(5) -#define IO_BANK0_PROC1_INTS4_GPIO33_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS4_GPIO33_LEVEL_LOW -#define IO_BANK0_PROC1_INTS4_GPIO33_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS4_GPIO33_LEVEL_LOW_BITS _u(0x00000010) -#define IO_BANK0_PROC1_INTS4_GPIO33_LEVEL_LOW_MSB _u(4) -#define IO_BANK0_PROC1_INTS4_GPIO33_LEVEL_LOW_LSB _u(4) -#define IO_BANK0_PROC1_INTS4_GPIO33_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS4_GPIO32_EDGE_HIGH -#define IO_BANK0_PROC1_INTS4_GPIO32_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS4_GPIO32_EDGE_HIGH_BITS _u(0x00000008) -#define IO_BANK0_PROC1_INTS4_GPIO32_EDGE_HIGH_MSB _u(3) -#define IO_BANK0_PROC1_INTS4_GPIO32_EDGE_HIGH_LSB _u(3) -#define IO_BANK0_PROC1_INTS4_GPIO32_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS4_GPIO32_EDGE_LOW -#define IO_BANK0_PROC1_INTS4_GPIO32_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS4_GPIO32_EDGE_LOW_BITS _u(0x00000004) -#define IO_BANK0_PROC1_INTS4_GPIO32_EDGE_LOW_MSB _u(2) -#define IO_BANK0_PROC1_INTS4_GPIO32_EDGE_LOW_LSB _u(2) -#define IO_BANK0_PROC1_INTS4_GPIO32_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS4_GPIO32_LEVEL_HIGH -#define IO_BANK0_PROC1_INTS4_GPIO32_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS4_GPIO32_LEVEL_HIGH_BITS _u(0x00000002) -#define IO_BANK0_PROC1_INTS4_GPIO32_LEVEL_HIGH_MSB _u(1) -#define IO_BANK0_PROC1_INTS4_GPIO32_LEVEL_HIGH_LSB _u(1) -#define IO_BANK0_PROC1_INTS4_GPIO32_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS4_GPIO32_LEVEL_LOW -#define IO_BANK0_PROC1_INTS4_GPIO32_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS4_GPIO32_LEVEL_LOW_BITS _u(0x00000001) -#define IO_BANK0_PROC1_INTS4_GPIO32_LEVEL_LOW_MSB _u(0) -#define IO_BANK0_PROC1_INTS4_GPIO32_LEVEL_LOW_LSB _u(0) -#define IO_BANK0_PROC1_INTS4_GPIO32_LEVEL_LOW_ACCESS "RO" -// ============================================================================= -// Register : IO_BANK0_PROC1_INTS5 -// Description : Interrupt status after masking & forcing for proc1 -#define IO_BANK0_PROC1_INTS5_OFFSET _u(0x000002d4) -#define IO_BANK0_PROC1_INTS5_BITS _u(0xffffffff) -#define IO_BANK0_PROC1_INTS5_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS5_GPIO47_EDGE_HIGH -#define IO_BANK0_PROC1_INTS5_GPIO47_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS5_GPIO47_EDGE_HIGH_BITS _u(0x80000000) -#define IO_BANK0_PROC1_INTS5_GPIO47_EDGE_HIGH_MSB _u(31) -#define IO_BANK0_PROC1_INTS5_GPIO47_EDGE_HIGH_LSB _u(31) -#define IO_BANK0_PROC1_INTS5_GPIO47_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS5_GPIO47_EDGE_LOW -#define IO_BANK0_PROC1_INTS5_GPIO47_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS5_GPIO47_EDGE_LOW_BITS _u(0x40000000) -#define IO_BANK0_PROC1_INTS5_GPIO47_EDGE_LOW_MSB _u(30) -#define IO_BANK0_PROC1_INTS5_GPIO47_EDGE_LOW_LSB _u(30) -#define IO_BANK0_PROC1_INTS5_GPIO47_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS5_GPIO47_LEVEL_HIGH -#define IO_BANK0_PROC1_INTS5_GPIO47_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS5_GPIO47_LEVEL_HIGH_BITS _u(0x20000000) -#define IO_BANK0_PROC1_INTS5_GPIO47_LEVEL_HIGH_MSB _u(29) -#define IO_BANK0_PROC1_INTS5_GPIO47_LEVEL_HIGH_LSB _u(29) -#define IO_BANK0_PROC1_INTS5_GPIO47_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS5_GPIO47_LEVEL_LOW -#define IO_BANK0_PROC1_INTS5_GPIO47_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS5_GPIO47_LEVEL_LOW_BITS _u(0x10000000) -#define IO_BANK0_PROC1_INTS5_GPIO47_LEVEL_LOW_MSB _u(28) -#define IO_BANK0_PROC1_INTS5_GPIO47_LEVEL_LOW_LSB _u(28) -#define IO_BANK0_PROC1_INTS5_GPIO47_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS5_GPIO46_EDGE_HIGH -#define IO_BANK0_PROC1_INTS5_GPIO46_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS5_GPIO46_EDGE_HIGH_BITS _u(0x08000000) -#define IO_BANK0_PROC1_INTS5_GPIO46_EDGE_HIGH_MSB _u(27) -#define IO_BANK0_PROC1_INTS5_GPIO46_EDGE_HIGH_LSB _u(27) -#define IO_BANK0_PROC1_INTS5_GPIO46_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS5_GPIO46_EDGE_LOW -#define IO_BANK0_PROC1_INTS5_GPIO46_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS5_GPIO46_EDGE_LOW_BITS _u(0x04000000) -#define IO_BANK0_PROC1_INTS5_GPIO46_EDGE_LOW_MSB _u(26) -#define IO_BANK0_PROC1_INTS5_GPIO46_EDGE_LOW_LSB _u(26) -#define IO_BANK0_PROC1_INTS5_GPIO46_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS5_GPIO46_LEVEL_HIGH -#define IO_BANK0_PROC1_INTS5_GPIO46_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS5_GPIO46_LEVEL_HIGH_BITS _u(0x02000000) -#define IO_BANK0_PROC1_INTS5_GPIO46_LEVEL_HIGH_MSB _u(25) -#define IO_BANK0_PROC1_INTS5_GPIO46_LEVEL_HIGH_LSB _u(25) -#define IO_BANK0_PROC1_INTS5_GPIO46_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS5_GPIO46_LEVEL_LOW -#define IO_BANK0_PROC1_INTS5_GPIO46_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS5_GPIO46_LEVEL_LOW_BITS _u(0x01000000) -#define IO_BANK0_PROC1_INTS5_GPIO46_LEVEL_LOW_MSB _u(24) -#define IO_BANK0_PROC1_INTS5_GPIO46_LEVEL_LOW_LSB _u(24) -#define IO_BANK0_PROC1_INTS5_GPIO46_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS5_GPIO45_EDGE_HIGH -#define IO_BANK0_PROC1_INTS5_GPIO45_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS5_GPIO45_EDGE_HIGH_BITS _u(0x00800000) -#define IO_BANK0_PROC1_INTS5_GPIO45_EDGE_HIGH_MSB _u(23) -#define IO_BANK0_PROC1_INTS5_GPIO45_EDGE_HIGH_LSB _u(23) -#define IO_BANK0_PROC1_INTS5_GPIO45_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS5_GPIO45_EDGE_LOW -#define IO_BANK0_PROC1_INTS5_GPIO45_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS5_GPIO45_EDGE_LOW_BITS _u(0x00400000) -#define IO_BANK0_PROC1_INTS5_GPIO45_EDGE_LOW_MSB _u(22) -#define IO_BANK0_PROC1_INTS5_GPIO45_EDGE_LOW_LSB _u(22) -#define IO_BANK0_PROC1_INTS5_GPIO45_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS5_GPIO45_LEVEL_HIGH -#define IO_BANK0_PROC1_INTS5_GPIO45_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS5_GPIO45_LEVEL_HIGH_BITS _u(0x00200000) -#define IO_BANK0_PROC1_INTS5_GPIO45_LEVEL_HIGH_MSB _u(21) -#define IO_BANK0_PROC1_INTS5_GPIO45_LEVEL_HIGH_LSB _u(21) -#define IO_BANK0_PROC1_INTS5_GPIO45_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS5_GPIO45_LEVEL_LOW -#define IO_BANK0_PROC1_INTS5_GPIO45_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS5_GPIO45_LEVEL_LOW_BITS _u(0x00100000) -#define IO_BANK0_PROC1_INTS5_GPIO45_LEVEL_LOW_MSB _u(20) -#define IO_BANK0_PROC1_INTS5_GPIO45_LEVEL_LOW_LSB _u(20) -#define IO_BANK0_PROC1_INTS5_GPIO45_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS5_GPIO44_EDGE_HIGH -#define IO_BANK0_PROC1_INTS5_GPIO44_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS5_GPIO44_EDGE_HIGH_BITS _u(0x00080000) -#define IO_BANK0_PROC1_INTS5_GPIO44_EDGE_HIGH_MSB _u(19) -#define IO_BANK0_PROC1_INTS5_GPIO44_EDGE_HIGH_LSB _u(19) -#define IO_BANK0_PROC1_INTS5_GPIO44_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS5_GPIO44_EDGE_LOW -#define IO_BANK0_PROC1_INTS5_GPIO44_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS5_GPIO44_EDGE_LOW_BITS _u(0x00040000) -#define IO_BANK0_PROC1_INTS5_GPIO44_EDGE_LOW_MSB _u(18) -#define IO_BANK0_PROC1_INTS5_GPIO44_EDGE_LOW_LSB _u(18) -#define IO_BANK0_PROC1_INTS5_GPIO44_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS5_GPIO44_LEVEL_HIGH -#define IO_BANK0_PROC1_INTS5_GPIO44_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS5_GPIO44_LEVEL_HIGH_BITS _u(0x00020000) -#define IO_BANK0_PROC1_INTS5_GPIO44_LEVEL_HIGH_MSB _u(17) -#define IO_BANK0_PROC1_INTS5_GPIO44_LEVEL_HIGH_LSB _u(17) -#define IO_BANK0_PROC1_INTS5_GPIO44_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS5_GPIO44_LEVEL_LOW -#define IO_BANK0_PROC1_INTS5_GPIO44_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS5_GPIO44_LEVEL_LOW_BITS _u(0x00010000) -#define IO_BANK0_PROC1_INTS5_GPIO44_LEVEL_LOW_MSB _u(16) -#define IO_BANK0_PROC1_INTS5_GPIO44_LEVEL_LOW_LSB _u(16) -#define IO_BANK0_PROC1_INTS5_GPIO44_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS5_GPIO43_EDGE_HIGH -#define IO_BANK0_PROC1_INTS5_GPIO43_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS5_GPIO43_EDGE_HIGH_BITS _u(0x00008000) -#define IO_BANK0_PROC1_INTS5_GPIO43_EDGE_HIGH_MSB _u(15) -#define IO_BANK0_PROC1_INTS5_GPIO43_EDGE_HIGH_LSB _u(15) -#define IO_BANK0_PROC1_INTS5_GPIO43_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS5_GPIO43_EDGE_LOW -#define IO_BANK0_PROC1_INTS5_GPIO43_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS5_GPIO43_EDGE_LOW_BITS _u(0x00004000) -#define IO_BANK0_PROC1_INTS5_GPIO43_EDGE_LOW_MSB _u(14) -#define IO_BANK0_PROC1_INTS5_GPIO43_EDGE_LOW_LSB _u(14) -#define IO_BANK0_PROC1_INTS5_GPIO43_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS5_GPIO43_LEVEL_HIGH -#define IO_BANK0_PROC1_INTS5_GPIO43_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS5_GPIO43_LEVEL_HIGH_BITS _u(0x00002000) -#define IO_BANK0_PROC1_INTS5_GPIO43_LEVEL_HIGH_MSB _u(13) -#define IO_BANK0_PROC1_INTS5_GPIO43_LEVEL_HIGH_LSB _u(13) -#define IO_BANK0_PROC1_INTS5_GPIO43_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS5_GPIO43_LEVEL_LOW -#define IO_BANK0_PROC1_INTS5_GPIO43_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS5_GPIO43_LEVEL_LOW_BITS _u(0x00001000) -#define IO_BANK0_PROC1_INTS5_GPIO43_LEVEL_LOW_MSB _u(12) -#define IO_BANK0_PROC1_INTS5_GPIO43_LEVEL_LOW_LSB _u(12) -#define IO_BANK0_PROC1_INTS5_GPIO43_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS5_GPIO42_EDGE_HIGH -#define IO_BANK0_PROC1_INTS5_GPIO42_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS5_GPIO42_EDGE_HIGH_BITS _u(0x00000800) -#define IO_BANK0_PROC1_INTS5_GPIO42_EDGE_HIGH_MSB _u(11) -#define IO_BANK0_PROC1_INTS5_GPIO42_EDGE_HIGH_LSB _u(11) -#define IO_BANK0_PROC1_INTS5_GPIO42_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS5_GPIO42_EDGE_LOW -#define IO_BANK0_PROC1_INTS5_GPIO42_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS5_GPIO42_EDGE_LOW_BITS _u(0x00000400) -#define IO_BANK0_PROC1_INTS5_GPIO42_EDGE_LOW_MSB _u(10) -#define IO_BANK0_PROC1_INTS5_GPIO42_EDGE_LOW_LSB _u(10) -#define IO_BANK0_PROC1_INTS5_GPIO42_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS5_GPIO42_LEVEL_HIGH -#define IO_BANK0_PROC1_INTS5_GPIO42_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS5_GPIO42_LEVEL_HIGH_BITS _u(0x00000200) -#define IO_BANK0_PROC1_INTS5_GPIO42_LEVEL_HIGH_MSB _u(9) -#define IO_BANK0_PROC1_INTS5_GPIO42_LEVEL_HIGH_LSB _u(9) -#define IO_BANK0_PROC1_INTS5_GPIO42_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS5_GPIO42_LEVEL_LOW -#define IO_BANK0_PROC1_INTS5_GPIO42_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS5_GPIO42_LEVEL_LOW_BITS _u(0x00000100) -#define IO_BANK0_PROC1_INTS5_GPIO42_LEVEL_LOW_MSB _u(8) -#define IO_BANK0_PROC1_INTS5_GPIO42_LEVEL_LOW_LSB _u(8) -#define IO_BANK0_PROC1_INTS5_GPIO42_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS5_GPIO41_EDGE_HIGH -#define IO_BANK0_PROC1_INTS5_GPIO41_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS5_GPIO41_EDGE_HIGH_BITS _u(0x00000080) -#define IO_BANK0_PROC1_INTS5_GPIO41_EDGE_HIGH_MSB _u(7) -#define IO_BANK0_PROC1_INTS5_GPIO41_EDGE_HIGH_LSB _u(7) -#define IO_BANK0_PROC1_INTS5_GPIO41_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS5_GPIO41_EDGE_LOW -#define IO_BANK0_PROC1_INTS5_GPIO41_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS5_GPIO41_EDGE_LOW_BITS _u(0x00000040) -#define IO_BANK0_PROC1_INTS5_GPIO41_EDGE_LOW_MSB _u(6) -#define IO_BANK0_PROC1_INTS5_GPIO41_EDGE_LOW_LSB _u(6) -#define IO_BANK0_PROC1_INTS5_GPIO41_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS5_GPIO41_LEVEL_HIGH -#define IO_BANK0_PROC1_INTS5_GPIO41_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS5_GPIO41_LEVEL_HIGH_BITS _u(0x00000020) -#define IO_BANK0_PROC1_INTS5_GPIO41_LEVEL_HIGH_MSB _u(5) -#define IO_BANK0_PROC1_INTS5_GPIO41_LEVEL_HIGH_LSB _u(5) -#define IO_BANK0_PROC1_INTS5_GPIO41_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS5_GPIO41_LEVEL_LOW -#define IO_BANK0_PROC1_INTS5_GPIO41_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS5_GPIO41_LEVEL_LOW_BITS _u(0x00000010) -#define IO_BANK0_PROC1_INTS5_GPIO41_LEVEL_LOW_MSB _u(4) -#define IO_BANK0_PROC1_INTS5_GPIO41_LEVEL_LOW_LSB _u(4) -#define IO_BANK0_PROC1_INTS5_GPIO41_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS5_GPIO40_EDGE_HIGH -#define IO_BANK0_PROC1_INTS5_GPIO40_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS5_GPIO40_EDGE_HIGH_BITS _u(0x00000008) -#define IO_BANK0_PROC1_INTS5_GPIO40_EDGE_HIGH_MSB _u(3) -#define IO_BANK0_PROC1_INTS5_GPIO40_EDGE_HIGH_LSB _u(3) -#define IO_BANK0_PROC1_INTS5_GPIO40_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS5_GPIO40_EDGE_LOW -#define IO_BANK0_PROC1_INTS5_GPIO40_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS5_GPIO40_EDGE_LOW_BITS _u(0x00000004) -#define IO_BANK0_PROC1_INTS5_GPIO40_EDGE_LOW_MSB _u(2) -#define IO_BANK0_PROC1_INTS5_GPIO40_EDGE_LOW_LSB _u(2) -#define IO_BANK0_PROC1_INTS5_GPIO40_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS5_GPIO40_LEVEL_HIGH -#define IO_BANK0_PROC1_INTS5_GPIO40_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS5_GPIO40_LEVEL_HIGH_BITS _u(0x00000002) -#define IO_BANK0_PROC1_INTS5_GPIO40_LEVEL_HIGH_MSB _u(1) -#define IO_BANK0_PROC1_INTS5_GPIO40_LEVEL_HIGH_LSB _u(1) -#define IO_BANK0_PROC1_INTS5_GPIO40_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_PROC1_INTS5_GPIO40_LEVEL_LOW -#define IO_BANK0_PROC1_INTS5_GPIO40_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_PROC1_INTS5_GPIO40_LEVEL_LOW_BITS _u(0x00000001) -#define IO_BANK0_PROC1_INTS5_GPIO40_LEVEL_LOW_MSB _u(0) -#define IO_BANK0_PROC1_INTS5_GPIO40_LEVEL_LOW_LSB _u(0) -#define IO_BANK0_PROC1_INTS5_GPIO40_LEVEL_LOW_ACCESS "RO" -// ============================================================================= -// Register : IO_BANK0_DORMANT_WAKE_INTE0 -// Description : Interrupt Enable for dormant_wake -#define IO_BANK0_DORMANT_WAKE_INTE0_OFFSET _u(0x000002d8) -#define IO_BANK0_DORMANT_WAKE_INTE0_BITS _u(0xffffffff) -#define IO_BANK0_DORMANT_WAKE_INTE0_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_HIGH_BITS _u(0x80000000) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_HIGH_MSB _u(31) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_HIGH_LSB _u(31) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_LOW_BITS _u(0x40000000) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_LOW_MSB _u(30) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_LOW_LSB _u(30) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_HIGH_BITS _u(0x20000000) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_HIGH_MSB _u(29) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_HIGH_LSB _u(29) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_LOW_BITS _u(0x10000000) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_LOW_MSB _u(28) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_LOW_LSB _u(28) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_HIGH_BITS _u(0x08000000) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_HIGH_MSB _u(27) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_HIGH_LSB _u(27) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_LOW_BITS _u(0x04000000) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_LOW_MSB _u(26) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_LOW_LSB _u(26) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_HIGH_BITS _u(0x02000000) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_HIGH_MSB _u(25) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_HIGH_LSB _u(25) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_LOW_BITS _u(0x01000000) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_LOW_MSB _u(24) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_LOW_LSB _u(24) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_HIGH_BITS _u(0x00800000) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_HIGH_MSB _u(23) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_HIGH_LSB _u(23) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_LOW_BITS _u(0x00400000) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_LOW_MSB _u(22) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_LOW_LSB _u(22) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_HIGH_BITS _u(0x00200000) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_HIGH_MSB _u(21) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_HIGH_LSB _u(21) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_LOW_BITS _u(0x00100000) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_LOW_MSB _u(20) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_LOW_LSB _u(20) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_HIGH_BITS _u(0x00080000) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_HIGH_MSB _u(19) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_HIGH_LSB _u(19) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_LOW_BITS _u(0x00040000) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_LOW_MSB _u(18) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_LOW_LSB _u(18) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_HIGH_BITS _u(0x00020000) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_HIGH_MSB _u(17) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_HIGH_LSB _u(17) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_LOW_BITS _u(0x00010000) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_LOW_MSB _u(16) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_LOW_LSB _u(16) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_HIGH_BITS _u(0x00008000) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_HIGH_MSB _u(15) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_HIGH_LSB _u(15) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_LOW_BITS _u(0x00004000) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_LOW_MSB _u(14) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_LOW_LSB _u(14) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_HIGH_BITS _u(0x00002000) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_HIGH_MSB _u(13) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_HIGH_LSB _u(13) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_LOW_BITS _u(0x00001000) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_LOW_MSB _u(12) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_LOW_LSB _u(12) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_HIGH_BITS _u(0x00000800) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_HIGH_MSB _u(11) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_HIGH_LSB _u(11) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_LOW_BITS _u(0x00000400) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_LOW_MSB _u(10) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_LOW_LSB _u(10) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_HIGH_BITS _u(0x00000200) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_HIGH_MSB _u(9) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_HIGH_LSB _u(9) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_LOW_BITS _u(0x00000100) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_LOW_MSB _u(8) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_LOW_LSB _u(8) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_HIGH_BITS _u(0x00000080) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_HIGH_MSB _u(7) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_HIGH_LSB _u(7) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_LOW_BITS _u(0x00000040) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_LOW_MSB _u(6) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_LOW_LSB _u(6) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_HIGH_BITS _u(0x00000020) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_HIGH_MSB _u(5) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_HIGH_LSB _u(5) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_LOW_BITS _u(0x00000010) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_LOW_MSB _u(4) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_LOW_LSB _u(4) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_HIGH_BITS _u(0x00000008) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_HIGH_MSB _u(3) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_HIGH_LSB _u(3) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_LOW_BITS _u(0x00000004) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_LOW_MSB _u(2) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_LOW_LSB _u(2) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_HIGH_BITS _u(0x00000002) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_HIGH_MSB _u(1) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_HIGH_LSB _u(1) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_LOW_BITS _u(0x00000001) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_LOW_MSB _u(0) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_LOW_LSB _u(0) -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_LOW_ACCESS "RW" -// ============================================================================= -// Register : IO_BANK0_DORMANT_WAKE_INTE1 -// Description : Interrupt Enable for dormant_wake -#define IO_BANK0_DORMANT_WAKE_INTE1_OFFSET _u(0x000002dc) -#define IO_BANK0_DORMANT_WAKE_INTE1_BITS _u(0xffffffff) -#define IO_BANK0_DORMANT_WAKE_INTE1_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_HIGH_BITS _u(0x80000000) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_HIGH_MSB _u(31) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_HIGH_LSB _u(31) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_LOW_BITS _u(0x40000000) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_LOW_MSB _u(30) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_LOW_LSB _u(30) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_HIGH_BITS _u(0x20000000) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_HIGH_MSB _u(29) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_HIGH_LSB _u(29) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_LOW_BITS _u(0x10000000) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_LOW_MSB _u(28) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_LOW_LSB _u(28) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_HIGH_BITS _u(0x08000000) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_HIGH_MSB _u(27) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_HIGH_LSB _u(27) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_LOW_BITS _u(0x04000000) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_LOW_MSB _u(26) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_LOW_LSB _u(26) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_HIGH_BITS _u(0x02000000) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_HIGH_MSB _u(25) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_HIGH_LSB _u(25) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_LOW_BITS _u(0x01000000) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_LOW_MSB _u(24) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_LOW_LSB _u(24) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_HIGH_BITS _u(0x00800000) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_HIGH_MSB _u(23) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_HIGH_LSB _u(23) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_LOW_BITS _u(0x00400000) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_LOW_MSB _u(22) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_LOW_LSB _u(22) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_HIGH_BITS _u(0x00200000) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_HIGH_MSB _u(21) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_HIGH_LSB _u(21) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_LOW_BITS _u(0x00100000) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_LOW_MSB _u(20) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_LOW_LSB _u(20) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_HIGH_BITS _u(0x00080000) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_HIGH_MSB _u(19) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_HIGH_LSB _u(19) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_LOW_BITS _u(0x00040000) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_LOW_MSB _u(18) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_LOW_LSB _u(18) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_HIGH_BITS _u(0x00020000) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_HIGH_MSB _u(17) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_HIGH_LSB _u(17) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_LOW_BITS _u(0x00010000) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_LOW_MSB _u(16) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_LOW_LSB _u(16) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_HIGH_BITS _u(0x00008000) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_HIGH_MSB _u(15) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_HIGH_LSB _u(15) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_LOW_BITS _u(0x00004000) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_LOW_MSB _u(14) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_LOW_LSB _u(14) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_HIGH_BITS _u(0x00002000) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_HIGH_MSB _u(13) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_HIGH_LSB _u(13) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_LOW_BITS _u(0x00001000) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_LOW_MSB _u(12) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_LOW_LSB _u(12) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_HIGH_BITS _u(0x00000800) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_HIGH_MSB _u(11) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_HIGH_LSB _u(11) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_LOW_BITS _u(0x00000400) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_LOW_MSB _u(10) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_LOW_LSB _u(10) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_HIGH_BITS _u(0x00000200) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_HIGH_MSB _u(9) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_HIGH_LSB _u(9) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_LOW_BITS _u(0x00000100) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_LOW_MSB _u(8) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_LOW_LSB _u(8) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_HIGH_BITS _u(0x00000080) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_HIGH_MSB _u(7) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_HIGH_LSB _u(7) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_LOW_BITS _u(0x00000040) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_LOW_MSB _u(6) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_LOW_LSB _u(6) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_HIGH_BITS _u(0x00000020) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_HIGH_MSB _u(5) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_HIGH_LSB _u(5) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_LOW_BITS _u(0x00000010) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_LOW_MSB _u(4) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_LOW_LSB _u(4) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_HIGH_BITS _u(0x00000008) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_HIGH_MSB _u(3) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_HIGH_LSB _u(3) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_LOW_BITS _u(0x00000004) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_LOW_MSB _u(2) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_LOW_LSB _u(2) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_HIGH_BITS _u(0x00000002) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_HIGH_MSB _u(1) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_HIGH_LSB _u(1) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_LOW_BITS _u(0x00000001) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_LOW_MSB _u(0) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_LOW_LSB _u(0) -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_LOW_ACCESS "RW" -// ============================================================================= -// Register : IO_BANK0_DORMANT_WAKE_INTE2 -// Description : Interrupt Enable for dormant_wake -#define IO_BANK0_DORMANT_WAKE_INTE2_OFFSET _u(0x000002e0) -#define IO_BANK0_DORMANT_WAKE_INTE2_BITS _u(0xffffffff) -#define IO_BANK0_DORMANT_WAKE_INTE2_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_HIGH_BITS _u(0x80000000) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_HIGH_MSB _u(31) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_HIGH_LSB _u(31) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_LOW_BITS _u(0x40000000) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_LOW_MSB _u(30) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_LOW_LSB _u(30) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_HIGH_BITS _u(0x20000000) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_HIGH_MSB _u(29) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_HIGH_LSB _u(29) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_LOW_BITS _u(0x10000000) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_LOW_MSB _u(28) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_LOW_LSB _u(28) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_HIGH_BITS _u(0x08000000) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_HIGH_MSB _u(27) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_HIGH_LSB _u(27) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_LOW_BITS _u(0x04000000) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_LOW_MSB _u(26) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_LOW_LSB _u(26) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_HIGH_BITS _u(0x02000000) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_HIGH_MSB _u(25) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_HIGH_LSB _u(25) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_LOW_BITS _u(0x01000000) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_LOW_MSB _u(24) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_LOW_LSB _u(24) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_HIGH_BITS _u(0x00800000) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_HIGH_MSB _u(23) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_HIGH_LSB _u(23) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_LOW_BITS _u(0x00400000) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_LOW_MSB _u(22) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_LOW_LSB _u(22) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_HIGH_BITS _u(0x00200000) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_HIGH_MSB _u(21) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_HIGH_LSB _u(21) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_LOW_BITS _u(0x00100000) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_LOW_MSB _u(20) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_LOW_LSB _u(20) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_HIGH_BITS _u(0x00080000) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_HIGH_MSB _u(19) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_HIGH_LSB _u(19) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_LOW_BITS _u(0x00040000) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_LOW_MSB _u(18) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_LOW_LSB _u(18) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_HIGH_BITS _u(0x00020000) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_HIGH_MSB _u(17) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_HIGH_LSB _u(17) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_LOW_BITS _u(0x00010000) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_LOW_MSB _u(16) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_LOW_LSB _u(16) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_HIGH_BITS _u(0x00008000) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_HIGH_MSB _u(15) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_HIGH_LSB _u(15) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_LOW_BITS _u(0x00004000) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_LOW_MSB _u(14) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_LOW_LSB _u(14) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_HIGH_BITS _u(0x00002000) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_HIGH_MSB _u(13) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_HIGH_LSB _u(13) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_LOW_BITS _u(0x00001000) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_LOW_MSB _u(12) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_LOW_LSB _u(12) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_HIGH_BITS _u(0x00000800) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_HIGH_MSB _u(11) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_HIGH_LSB _u(11) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_LOW_BITS _u(0x00000400) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_LOW_MSB _u(10) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_LOW_LSB _u(10) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_HIGH_BITS _u(0x00000200) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_HIGH_MSB _u(9) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_HIGH_LSB _u(9) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_LOW_BITS _u(0x00000100) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_LOW_MSB _u(8) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_LOW_LSB _u(8) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_HIGH_BITS _u(0x00000080) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_HIGH_MSB _u(7) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_HIGH_LSB _u(7) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_LOW_BITS _u(0x00000040) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_LOW_MSB _u(6) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_LOW_LSB _u(6) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_HIGH_BITS _u(0x00000020) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_HIGH_MSB _u(5) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_HIGH_LSB _u(5) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_LOW_BITS _u(0x00000010) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_LOW_MSB _u(4) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_LOW_LSB _u(4) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_HIGH_BITS _u(0x00000008) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_HIGH_MSB _u(3) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_HIGH_LSB _u(3) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_LOW_BITS _u(0x00000004) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_LOW_MSB _u(2) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_LOW_LSB _u(2) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_HIGH_BITS _u(0x00000002) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_HIGH_MSB _u(1) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_HIGH_LSB _u(1) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_LOW_BITS _u(0x00000001) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_LOW_MSB _u(0) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_LOW_LSB _u(0) -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_LOW_ACCESS "RW" -// ============================================================================= -// Register : IO_BANK0_DORMANT_WAKE_INTE3 -// Description : Interrupt Enable for dormant_wake -#define IO_BANK0_DORMANT_WAKE_INTE3_OFFSET _u(0x000002e4) -#define IO_BANK0_DORMANT_WAKE_INTE3_BITS _u(0xffffffff) -#define IO_BANK0_DORMANT_WAKE_INTE3_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO31_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO31_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO31_EDGE_HIGH_BITS _u(0x80000000) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO31_EDGE_HIGH_MSB _u(31) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO31_EDGE_HIGH_LSB _u(31) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO31_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO31_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO31_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO31_EDGE_LOW_BITS _u(0x40000000) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO31_EDGE_LOW_MSB _u(30) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO31_EDGE_LOW_LSB _u(30) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO31_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO31_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO31_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO31_LEVEL_HIGH_BITS _u(0x20000000) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO31_LEVEL_HIGH_MSB _u(29) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO31_LEVEL_HIGH_LSB _u(29) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO31_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO31_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO31_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO31_LEVEL_LOW_BITS _u(0x10000000) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO31_LEVEL_LOW_MSB _u(28) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO31_LEVEL_LOW_LSB _u(28) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO31_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO30_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO30_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO30_EDGE_HIGH_BITS _u(0x08000000) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO30_EDGE_HIGH_MSB _u(27) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO30_EDGE_HIGH_LSB _u(27) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO30_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO30_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO30_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO30_EDGE_LOW_BITS _u(0x04000000) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO30_EDGE_LOW_MSB _u(26) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO30_EDGE_LOW_LSB _u(26) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO30_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO30_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO30_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO30_LEVEL_HIGH_BITS _u(0x02000000) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO30_LEVEL_HIGH_MSB _u(25) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO30_LEVEL_HIGH_LSB _u(25) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO30_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO30_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO30_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO30_LEVEL_LOW_BITS _u(0x01000000) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO30_LEVEL_LOW_MSB _u(24) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO30_LEVEL_LOW_LSB _u(24) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO30_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_HIGH_BITS _u(0x00800000) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_HIGH_MSB _u(23) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_HIGH_LSB _u(23) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_LOW_BITS _u(0x00400000) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_LOW_MSB _u(22) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_LOW_LSB _u(22) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_HIGH_BITS _u(0x00200000) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_HIGH_MSB _u(21) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_HIGH_LSB _u(21) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_LOW_BITS _u(0x00100000) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_LOW_MSB _u(20) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_LOW_LSB _u(20) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_HIGH_BITS _u(0x00080000) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_HIGH_MSB _u(19) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_HIGH_LSB _u(19) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_LOW_BITS _u(0x00040000) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_LOW_MSB _u(18) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_LOW_LSB _u(18) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_HIGH_BITS _u(0x00020000) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_HIGH_MSB _u(17) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_HIGH_LSB _u(17) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_LOW_BITS _u(0x00010000) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_LOW_MSB _u(16) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_LOW_LSB _u(16) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_HIGH_BITS _u(0x00008000) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_HIGH_MSB _u(15) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_HIGH_LSB _u(15) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_LOW_BITS _u(0x00004000) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_LOW_MSB _u(14) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_LOW_LSB _u(14) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_HIGH_BITS _u(0x00002000) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_HIGH_MSB _u(13) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_HIGH_LSB _u(13) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_LOW_BITS _u(0x00001000) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_LOW_MSB _u(12) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_LOW_LSB _u(12) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_HIGH_BITS _u(0x00000800) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_HIGH_MSB _u(11) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_HIGH_LSB _u(11) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_LOW_BITS _u(0x00000400) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_LOW_MSB _u(10) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_LOW_LSB _u(10) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_HIGH_BITS _u(0x00000200) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_HIGH_MSB _u(9) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_HIGH_LSB _u(9) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_LOW_BITS _u(0x00000100) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_LOW_MSB _u(8) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_LOW_LSB _u(8) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_HIGH_BITS _u(0x00000080) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_HIGH_MSB _u(7) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_HIGH_LSB _u(7) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_LOW_BITS _u(0x00000040) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_LOW_MSB _u(6) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_LOW_LSB _u(6) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_HIGH_BITS _u(0x00000020) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_HIGH_MSB _u(5) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_HIGH_LSB _u(5) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_LOW_BITS _u(0x00000010) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_LOW_MSB _u(4) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_LOW_LSB _u(4) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_HIGH_BITS _u(0x00000008) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_HIGH_MSB _u(3) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_HIGH_LSB _u(3) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_LOW_BITS _u(0x00000004) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_LOW_MSB _u(2) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_LOW_LSB _u(2) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_HIGH_BITS _u(0x00000002) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_HIGH_MSB _u(1) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_HIGH_LSB _u(1) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_LOW_BITS _u(0x00000001) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_LOW_MSB _u(0) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_LOW_LSB _u(0) -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_LOW_ACCESS "RW" -// ============================================================================= -// Register : IO_BANK0_DORMANT_WAKE_INTE4 -// Description : Interrupt Enable for dormant_wake -#define IO_BANK0_DORMANT_WAKE_INTE4_OFFSET _u(0x000002e8) -#define IO_BANK0_DORMANT_WAKE_INTE4_BITS _u(0xffffffff) -#define IO_BANK0_DORMANT_WAKE_INTE4_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE4_GPIO39_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO39_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO39_EDGE_HIGH_BITS _u(0x80000000) -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO39_EDGE_HIGH_MSB _u(31) -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO39_EDGE_HIGH_LSB _u(31) -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO39_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE4_GPIO39_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO39_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO39_EDGE_LOW_BITS _u(0x40000000) -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO39_EDGE_LOW_MSB _u(30) -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO39_EDGE_LOW_LSB _u(30) -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO39_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE4_GPIO39_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO39_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO39_LEVEL_HIGH_BITS _u(0x20000000) -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO39_LEVEL_HIGH_MSB _u(29) -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO39_LEVEL_HIGH_LSB _u(29) -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO39_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE4_GPIO39_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO39_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO39_LEVEL_LOW_BITS _u(0x10000000) -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO39_LEVEL_LOW_MSB _u(28) -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO39_LEVEL_LOW_LSB _u(28) -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO39_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE4_GPIO38_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO38_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO38_EDGE_HIGH_BITS _u(0x08000000) -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO38_EDGE_HIGH_MSB _u(27) -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO38_EDGE_HIGH_LSB _u(27) -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO38_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE4_GPIO38_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO38_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO38_EDGE_LOW_BITS _u(0x04000000) -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO38_EDGE_LOW_MSB _u(26) -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO38_EDGE_LOW_LSB _u(26) -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO38_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE4_GPIO38_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO38_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO38_LEVEL_HIGH_BITS _u(0x02000000) -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO38_LEVEL_HIGH_MSB _u(25) -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO38_LEVEL_HIGH_LSB _u(25) -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO38_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE4_GPIO38_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO38_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO38_LEVEL_LOW_BITS _u(0x01000000) -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO38_LEVEL_LOW_MSB _u(24) -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO38_LEVEL_LOW_LSB _u(24) -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO38_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE4_GPIO37_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO37_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO37_EDGE_HIGH_BITS _u(0x00800000) -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO37_EDGE_HIGH_MSB _u(23) -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO37_EDGE_HIGH_LSB _u(23) -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO37_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE4_GPIO37_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO37_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO37_EDGE_LOW_BITS _u(0x00400000) -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO37_EDGE_LOW_MSB _u(22) -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO37_EDGE_LOW_LSB _u(22) -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO37_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE4_GPIO37_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO37_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO37_LEVEL_HIGH_BITS _u(0x00200000) -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO37_LEVEL_HIGH_MSB _u(21) -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO37_LEVEL_HIGH_LSB _u(21) -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO37_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE4_GPIO37_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO37_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO37_LEVEL_LOW_BITS _u(0x00100000) -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO37_LEVEL_LOW_MSB _u(20) -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO37_LEVEL_LOW_LSB _u(20) -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO37_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE4_GPIO36_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO36_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO36_EDGE_HIGH_BITS _u(0x00080000) -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO36_EDGE_HIGH_MSB _u(19) -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO36_EDGE_HIGH_LSB _u(19) -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO36_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE4_GPIO36_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO36_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO36_EDGE_LOW_BITS _u(0x00040000) -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO36_EDGE_LOW_MSB _u(18) -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO36_EDGE_LOW_LSB _u(18) -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO36_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE4_GPIO36_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO36_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO36_LEVEL_HIGH_BITS _u(0x00020000) -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO36_LEVEL_HIGH_MSB _u(17) -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO36_LEVEL_HIGH_LSB _u(17) -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO36_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE4_GPIO36_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO36_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO36_LEVEL_LOW_BITS _u(0x00010000) -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO36_LEVEL_LOW_MSB _u(16) -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO36_LEVEL_LOW_LSB _u(16) -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO36_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE4_GPIO35_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO35_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO35_EDGE_HIGH_BITS _u(0x00008000) -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO35_EDGE_HIGH_MSB _u(15) -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO35_EDGE_HIGH_LSB _u(15) -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO35_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE4_GPIO35_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO35_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO35_EDGE_LOW_BITS _u(0x00004000) -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO35_EDGE_LOW_MSB _u(14) -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO35_EDGE_LOW_LSB _u(14) -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO35_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE4_GPIO35_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO35_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO35_LEVEL_HIGH_BITS _u(0x00002000) -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO35_LEVEL_HIGH_MSB _u(13) -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO35_LEVEL_HIGH_LSB _u(13) -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO35_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE4_GPIO35_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO35_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO35_LEVEL_LOW_BITS _u(0x00001000) -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO35_LEVEL_LOW_MSB _u(12) -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO35_LEVEL_LOW_LSB _u(12) -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO35_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE4_GPIO34_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO34_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO34_EDGE_HIGH_BITS _u(0x00000800) -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO34_EDGE_HIGH_MSB _u(11) -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO34_EDGE_HIGH_LSB _u(11) -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO34_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE4_GPIO34_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO34_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO34_EDGE_LOW_BITS _u(0x00000400) -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO34_EDGE_LOW_MSB _u(10) -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO34_EDGE_LOW_LSB _u(10) -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO34_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE4_GPIO34_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO34_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO34_LEVEL_HIGH_BITS _u(0x00000200) -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO34_LEVEL_HIGH_MSB _u(9) -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO34_LEVEL_HIGH_LSB _u(9) -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO34_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE4_GPIO34_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO34_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO34_LEVEL_LOW_BITS _u(0x00000100) -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO34_LEVEL_LOW_MSB _u(8) -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO34_LEVEL_LOW_LSB _u(8) -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO34_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE4_GPIO33_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO33_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO33_EDGE_HIGH_BITS _u(0x00000080) -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO33_EDGE_HIGH_MSB _u(7) -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO33_EDGE_HIGH_LSB _u(7) -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO33_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE4_GPIO33_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO33_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO33_EDGE_LOW_BITS _u(0x00000040) -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO33_EDGE_LOW_MSB _u(6) -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO33_EDGE_LOW_LSB _u(6) -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO33_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE4_GPIO33_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO33_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO33_LEVEL_HIGH_BITS _u(0x00000020) -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO33_LEVEL_HIGH_MSB _u(5) -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO33_LEVEL_HIGH_LSB _u(5) -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO33_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE4_GPIO33_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO33_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO33_LEVEL_LOW_BITS _u(0x00000010) -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO33_LEVEL_LOW_MSB _u(4) -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO33_LEVEL_LOW_LSB _u(4) -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO33_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE4_GPIO32_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO32_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO32_EDGE_HIGH_BITS _u(0x00000008) -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO32_EDGE_HIGH_MSB _u(3) -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO32_EDGE_HIGH_LSB _u(3) -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO32_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE4_GPIO32_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO32_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO32_EDGE_LOW_BITS _u(0x00000004) -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO32_EDGE_LOW_MSB _u(2) -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO32_EDGE_LOW_LSB _u(2) -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO32_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE4_GPIO32_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO32_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO32_LEVEL_HIGH_BITS _u(0x00000002) -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO32_LEVEL_HIGH_MSB _u(1) -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO32_LEVEL_HIGH_LSB _u(1) -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO32_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE4_GPIO32_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO32_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO32_LEVEL_LOW_BITS _u(0x00000001) -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO32_LEVEL_LOW_MSB _u(0) -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO32_LEVEL_LOW_LSB _u(0) -#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO32_LEVEL_LOW_ACCESS "RW" -// ============================================================================= -// Register : IO_BANK0_DORMANT_WAKE_INTE5 -// Description : Interrupt Enable for dormant_wake -#define IO_BANK0_DORMANT_WAKE_INTE5_OFFSET _u(0x000002ec) -#define IO_BANK0_DORMANT_WAKE_INTE5_BITS _u(0xffffffff) -#define IO_BANK0_DORMANT_WAKE_INTE5_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE5_GPIO47_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO47_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO47_EDGE_HIGH_BITS _u(0x80000000) -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO47_EDGE_HIGH_MSB _u(31) -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO47_EDGE_HIGH_LSB _u(31) -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO47_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE5_GPIO47_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO47_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO47_EDGE_LOW_BITS _u(0x40000000) -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO47_EDGE_LOW_MSB _u(30) -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO47_EDGE_LOW_LSB _u(30) -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO47_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE5_GPIO47_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO47_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO47_LEVEL_HIGH_BITS _u(0x20000000) -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO47_LEVEL_HIGH_MSB _u(29) -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO47_LEVEL_HIGH_LSB _u(29) -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO47_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE5_GPIO47_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO47_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO47_LEVEL_LOW_BITS _u(0x10000000) -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO47_LEVEL_LOW_MSB _u(28) -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO47_LEVEL_LOW_LSB _u(28) -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO47_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE5_GPIO46_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO46_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO46_EDGE_HIGH_BITS _u(0x08000000) -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO46_EDGE_HIGH_MSB _u(27) -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO46_EDGE_HIGH_LSB _u(27) -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO46_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE5_GPIO46_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO46_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO46_EDGE_LOW_BITS _u(0x04000000) -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO46_EDGE_LOW_MSB _u(26) -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO46_EDGE_LOW_LSB _u(26) -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO46_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE5_GPIO46_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO46_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO46_LEVEL_HIGH_BITS _u(0x02000000) -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO46_LEVEL_HIGH_MSB _u(25) -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO46_LEVEL_HIGH_LSB _u(25) -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO46_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE5_GPIO46_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO46_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO46_LEVEL_LOW_BITS _u(0x01000000) -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO46_LEVEL_LOW_MSB _u(24) -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO46_LEVEL_LOW_LSB _u(24) -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO46_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE5_GPIO45_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO45_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO45_EDGE_HIGH_BITS _u(0x00800000) -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO45_EDGE_HIGH_MSB _u(23) -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO45_EDGE_HIGH_LSB _u(23) -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO45_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE5_GPIO45_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO45_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO45_EDGE_LOW_BITS _u(0x00400000) -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO45_EDGE_LOW_MSB _u(22) -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO45_EDGE_LOW_LSB _u(22) -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO45_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE5_GPIO45_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO45_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO45_LEVEL_HIGH_BITS _u(0x00200000) -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO45_LEVEL_HIGH_MSB _u(21) -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO45_LEVEL_HIGH_LSB _u(21) -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO45_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE5_GPIO45_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO45_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO45_LEVEL_LOW_BITS _u(0x00100000) -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO45_LEVEL_LOW_MSB _u(20) -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO45_LEVEL_LOW_LSB _u(20) -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO45_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE5_GPIO44_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO44_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO44_EDGE_HIGH_BITS _u(0x00080000) -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO44_EDGE_HIGH_MSB _u(19) -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO44_EDGE_HIGH_LSB _u(19) -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO44_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE5_GPIO44_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO44_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO44_EDGE_LOW_BITS _u(0x00040000) -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO44_EDGE_LOW_MSB _u(18) -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO44_EDGE_LOW_LSB _u(18) -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO44_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE5_GPIO44_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO44_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO44_LEVEL_HIGH_BITS _u(0x00020000) -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO44_LEVEL_HIGH_MSB _u(17) -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO44_LEVEL_HIGH_LSB _u(17) -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO44_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE5_GPIO44_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO44_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO44_LEVEL_LOW_BITS _u(0x00010000) -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO44_LEVEL_LOW_MSB _u(16) -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO44_LEVEL_LOW_LSB _u(16) -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO44_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE5_GPIO43_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO43_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO43_EDGE_HIGH_BITS _u(0x00008000) -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO43_EDGE_HIGH_MSB _u(15) -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO43_EDGE_HIGH_LSB _u(15) -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO43_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE5_GPIO43_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO43_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO43_EDGE_LOW_BITS _u(0x00004000) -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO43_EDGE_LOW_MSB _u(14) -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO43_EDGE_LOW_LSB _u(14) -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO43_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE5_GPIO43_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO43_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO43_LEVEL_HIGH_BITS _u(0x00002000) -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO43_LEVEL_HIGH_MSB _u(13) -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO43_LEVEL_HIGH_LSB _u(13) -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO43_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE5_GPIO43_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO43_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO43_LEVEL_LOW_BITS _u(0x00001000) -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO43_LEVEL_LOW_MSB _u(12) -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO43_LEVEL_LOW_LSB _u(12) -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO43_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE5_GPIO42_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO42_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO42_EDGE_HIGH_BITS _u(0x00000800) -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO42_EDGE_HIGH_MSB _u(11) -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO42_EDGE_HIGH_LSB _u(11) -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO42_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE5_GPIO42_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO42_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO42_EDGE_LOW_BITS _u(0x00000400) -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO42_EDGE_LOW_MSB _u(10) -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO42_EDGE_LOW_LSB _u(10) -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO42_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE5_GPIO42_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO42_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO42_LEVEL_HIGH_BITS _u(0x00000200) -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO42_LEVEL_HIGH_MSB _u(9) -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO42_LEVEL_HIGH_LSB _u(9) -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO42_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE5_GPIO42_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO42_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO42_LEVEL_LOW_BITS _u(0x00000100) -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO42_LEVEL_LOW_MSB _u(8) -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO42_LEVEL_LOW_LSB _u(8) -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO42_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE5_GPIO41_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO41_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO41_EDGE_HIGH_BITS _u(0x00000080) -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO41_EDGE_HIGH_MSB _u(7) -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO41_EDGE_HIGH_LSB _u(7) -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO41_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE5_GPIO41_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO41_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO41_EDGE_LOW_BITS _u(0x00000040) -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO41_EDGE_LOW_MSB _u(6) -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO41_EDGE_LOW_LSB _u(6) -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO41_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE5_GPIO41_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO41_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO41_LEVEL_HIGH_BITS _u(0x00000020) -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO41_LEVEL_HIGH_MSB _u(5) -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO41_LEVEL_HIGH_LSB _u(5) -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO41_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE5_GPIO41_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO41_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO41_LEVEL_LOW_BITS _u(0x00000010) -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO41_LEVEL_LOW_MSB _u(4) -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO41_LEVEL_LOW_LSB _u(4) -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO41_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE5_GPIO40_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO40_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO40_EDGE_HIGH_BITS _u(0x00000008) -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO40_EDGE_HIGH_MSB _u(3) -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO40_EDGE_HIGH_LSB _u(3) -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO40_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE5_GPIO40_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO40_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO40_EDGE_LOW_BITS _u(0x00000004) -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO40_EDGE_LOW_MSB _u(2) -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO40_EDGE_LOW_LSB _u(2) -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO40_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE5_GPIO40_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO40_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO40_LEVEL_HIGH_BITS _u(0x00000002) -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO40_LEVEL_HIGH_MSB _u(1) -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO40_LEVEL_HIGH_LSB _u(1) -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO40_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTE5_GPIO40_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO40_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO40_LEVEL_LOW_BITS _u(0x00000001) -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO40_LEVEL_LOW_MSB _u(0) -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO40_LEVEL_LOW_LSB _u(0) -#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO40_LEVEL_LOW_ACCESS "RW" -// ============================================================================= -// Register : IO_BANK0_DORMANT_WAKE_INTF0 -// Description : Interrupt Force for dormant_wake -#define IO_BANK0_DORMANT_WAKE_INTF0_OFFSET _u(0x000002f0) -#define IO_BANK0_DORMANT_WAKE_INTF0_BITS _u(0xffffffff) -#define IO_BANK0_DORMANT_WAKE_INTF0_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_HIGH_BITS _u(0x80000000) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_HIGH_MSB _u(31) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_HIGH_LSB _u(31) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_LOW_BITS _u(0x40000000) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_LOW_MSB _u(30) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_LOW_LSB _u(30) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_HIGH_BITS _u(0x20000000) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_HIGH_MSB _u(29) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_HIGH_LSB _u(29) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_LOW_BITS _u(0x10000000) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_LOW_MSB _u(28) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_LOW_LSB _u(28) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_HIGH_BITS _u(0x08000000) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_HIGH_MSB _u(27) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_HIGH_LSB _u(27) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_LOW_BITS _u(0x04000000) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_LOW_MSB _u(26) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_LOW_LSB _u(26) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_HIGH_BITS _u(0x02000000) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_HIGH_MSB _u(25) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_HIGH_LSB _u(25) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_LOW_BITS _u(0x01000000) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_LOW_MSB _u(24) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_LOW_LSB _u(24) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_HIGH_BITS _u(0x00800000) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_HIGH_MSB _u(23) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_HIGH_LSB _u(23) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_LOW_BITS _u(0x00400000) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_LOW_MSB _u(22) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_LOW_LSB _u(22) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_HIGH_BITS _u(0x00200000) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_HIGH_MSB _u(21) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_HIGH_LSB _u(21) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_LOW_BITS _u(0x00100000) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_LOW_MSB _u(20) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_LOW_LSB _u(20) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_HIGH_BITS _u(0x00080000) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_HIGH_MSB _u(19) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_HIGH_LSB _u(19) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_LOW_BITS _u(0x00040000) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_LOW_MSB _u(18) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_LOW_LSB _u(18) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_HIGH_BITS _u(0x00020000) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_HIGH_MSB _u(17) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_HIGH_LSB _u(17) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_LOW_BITS _u(0x00010000) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_LOW_MSB _u(16) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_LOW_LSB _u(16) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_HIGH_BITS _u(0x00008000) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_HIGH_MSB _u(15) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_HIGH_LSB _u(15) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_LOW_BITS _u(0x00004000) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_LOW_MSB _u(14) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_LOW_LSB _u(14) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_HIGH_BITS _u(0x00002000) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_HIGH_MSB _u(13) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_HIGH_LSB _u(13) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_LOW_BITS _u(0x00001000) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_LOW_MSB _u(12) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_LOW_LSB _u(12) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_HIGH_BITS _u(0x00000800) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_HIGH_MSB _u(11) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_HIGH_LSB _u(11) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_LOW_BITS _u(0x00000400) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_LOW_MSB _u(10) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_LOW_LSB _u(10) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_HIGH_BITS _u(0x00000200) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_HIGH_MSB _u(9) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_HIGH_LSB _u(9) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_LOW_BITS _u(0x00000100) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_LOW_MSB _u(8) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_LOW_LSB _u(8) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_HIGH_BITS _u(0x00000080) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_HIGH_MSB _u(7) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_HIGH_LSB _u(7) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_LOW_BITS _u(0x00000040) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_LOW_MSB _u(6) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_LOW_LSB _u(6) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_HIGH_BITS _u(0x00000020) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_HIGH_MSB _u(5) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_HIGH_LSB _u(5) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_LOW_BITS _u(0x00000010) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_LOW_MSB _u(4) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_LOW_LSB _u(4) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_HIGH_BITS _u(0x00000008) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_HIGH_MSB _u(3) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_HIGH_LSB _u(3) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_LOW_BITS _u(0x00000004) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_LOW_MSB _u(2) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_LOW_LSB _u(2) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_HIGH_BITS _u(0x00000002) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_HIGH_MSB _u(1) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_HIGH_LSB _u(1) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_LOW_BITS _u(0x00000001) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_LOW_MSB _u(0) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_LOW_LSB _u(0) -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_LOW_ACCESS "RW" -// ============================================================================= -// Register : IO_BANK0_DORMANT_WAKE_INTF1 -// Description : Interrupt Force for dormant_wake -#define IO_BANK0_DORMANT_WAKE_INTF1_OFFSET _u(0x000002f4) -#define IO_BANK0_DORMANT_WAKE_INTF1_BITS _u(0xffffffff) -#define IO_BANK0_DORMANT_WAKE_INTF1_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_HIGH_BITS _u(0x80000000) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_HIGH_MSB _u(31) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_HIGH_LSB _u(31) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_LOW_BITS _u(0x40000000) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_LOW_MSB _u(30) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_LOW_LSB _u(30) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_HIGH_BITS _u(0x20000000) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_HIGH_MSB _u(29) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_HIGH_LSB _u(29) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_LOW_BITS _u(0x10000000) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_LOW_MSB _u(28) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_LOW_LSB _u(28) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_HIGH_BITS _u(0x08000000) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_HIGH_MSB _u(27) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_HIGH_LSB _u(27) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_LOW_BITS _u(0x04000000) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_LOW_MSB _u(26) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_LOW_LSB _u(26) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_HIGH_BITS _u(0x02000000) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_HIGH_MSB _u(25) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_HIGH_LSB _u(25) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_LOW_BITS _u(0x01000000) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_LOW_MSB _u(24) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_LOW_LSB _u(24) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_HIGH_BITS _u(0x00800000) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_HIGH_MSB _u(23) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_HIGH_LSB _u(23) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_LOW_BITS _u(0x00400000) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_LOW_MSB _u(22) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_LOW_LSB _u(22) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_HIGH_BITS _u(0x00200000) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_HIGH_MSB _u(21) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_HIGH_LSB _u(21) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_LOW_BITS _u(0x00100000) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_LOW_MSB _u(20) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_LOW_LSB _u(20) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_HIGH_BITS _u(0x00080000) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_HIGH_MSB _u(19) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_HIGH_LSB _u(19) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_LOW_BITS _u(0x00040000) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_LOW_MSB _u(18) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_LOW_LSB _u(18) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_HIGH_BITS _u(0x00020000) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_HIGH_MSB _u(17) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_HIGH_LSB _u(17) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_LOW_BITS _u(0x00010000) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_LOW_MSB _u(16) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_LOW_LSB _u(16) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_HIGH_BITS _u(0x00008000) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_HIGH_MSB _u(15) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_HIGH_LSB _u(15) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_LOW_BITS _u(0x00004000) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_LOW_MSB _u(14) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_LOW_LSB _u(14) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_HIGH_BITS _u(0x00002000) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_HIGH_MSB _u(13) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_HIGH_LSB _u(13) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_LOW_BITS _u(0x00001000) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_LOW_MSB _u(12) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_LOW_LSB _u(12) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_HIGH_BITS _u(0x00000800) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_HIGH_MSB _u(11) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_HIGH_LSB _u(11) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_LOW_BITS _u(0x00000400) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_LOW_MSB _u(10) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_LOW_LSB _u(10) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_HIGH_BITS _u(0x00000200) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_HIGH_MSB _u(9) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_HIGH_LSB _u(9) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_LOW_BITS _u(0x00000100) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_LOW_MSB _u(8) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_LOW_LSB _u(8) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_HIGH_BITS _u(0x00000080) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_HIGH_MSB _u(7) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_HIGH_LSB _u(7) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_LOW_BITS _u(0x00000040) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_LOW_MSB _u(6) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_LOW_LSB _u(6) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_HIGH_BITS _u(0x00000020) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_HIGH_MSB _u(5) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_HIGH_LSB _u(5) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_LOW_BITS _u(0x00000010) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_LOW_MSB _u(4) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_LOW_LSB _u(4) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_HIGH_BITS _u(0x00000008) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_HIGH_MSB _u(3) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_HIGH_LSB _u(3) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_LOW_BITS _u(0x00000004) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_LOW_MSB _u(2) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_LOW_LSB _u(2) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_HIGH_BITS _u(0x00000002) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_HIGH_MSB _u(1) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_HIGH_LSB _u(1) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_LOW_BITS _u(0x00000001) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_LOW_MSB _u(0) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_LOW_LSB _u(0) -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_LOW_ACCESS "RW" -// ============================================================================= -// Register : IO_BANK0_DORMANT_WAKE_INTF2 -// Description : Interrupt Force for dormant_wake -#define IO_BANK0_DORMANT_WAKE_INTF2_OFFSET _u(0x000002f8) -#define IO_BANK0_DORMANT_WAKE_INTF2_BITS _u(0xffffffff) -#define IO_BANK0_DORMANT_WAKE_INTF2_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_HIGH_BITS _u(0x80000000) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_HIGH_MSB _u(31) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_HIGH_LSB _u(31) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_LOW_BITS _u(0x40000000) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_LOW_MSB _u(30) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_LOW_LSB _u(30) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_HIGH_BITS _u(0x20000000) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_HIGH_MSB _u(29) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_HIGH_LSB _u(29) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_LOW_BITS _u(0x10000000) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_LOW_MSB _u(28) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_LOW_LSB _u(28) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_HIGH_BITS _u(0x08000000) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_HIGH_MSB _u(27) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_HIGH_LSB _u(27) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_LOW_BITS _u(0x04000000) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_LOW_MSB _u(26) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_LOW_LSB _u(26) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_HIGH_BITS _u(0x02000000) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_HIGH_MSB _u(25) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_HIGH_LSB _u(25) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_LOW_BITS _u(0x01000000) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_LOW_MSB _u(24) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_LOW_LSB _u(24) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_HIGH_BITS _u(0x00800000) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_HIGH_MSB _u(23) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_HIGH_LSB _u(23) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_LOW_BITS _u(0x00400000) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_LOW_MSB _u(22) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_LOW_LSB _u(22) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_HIGH_BITS _u(0x00200000) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_HIGH_MSB _u(21) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_HIGH_LSB _u(21) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_LOW_BITS _u(0x00100000) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_LOW_MSB _u(20) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_LOW_LSB _u(20) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_HIGH_BITS _u(0x00080000) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_HIGH_MSB _u(19) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_HIGH_LSB _u(19) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_LOW_BITS _u(0x00040000) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_LOW_MSB _u(18) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_LOW_LSB _u(18) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_HIGH_BITS _u(0x00020000) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_HIGH_MSB _u(17) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_HIGH_LSB _u(17) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_LOW_BITS _u(0x00010000) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_LOW_MSB _u(16) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_LOW_LSB _u(16) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_HIGH_BITS _u(0x00008000) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_HIGH_MSB _u(15) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_HIGH_LSB _u(15) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_LOW_BITS _u(0x00004000) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_LOW_MSB _u(14) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_LOW_LSB _u(14) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_HIGH_BITS _u(0x00002000) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_HIGH_MSB _u(13) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_HIGH_LSB _u(13) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_LOW_BITS _u(0x00001000) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_LOW_MSB _u(12) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_LOW_LSB _u(12) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_HIGH_BITS _u(0x00000800) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_HIGH_MSB _u(11) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_HIGH_LSB _u(11) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_LOW_BITS _u(0x00000400) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_LOW_MSB _u(10) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_LOW_LSB _u(10) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_HIGH_BITS _u(0x00000200) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_HIGH_MSB _u(9) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_HIGH_LSB _u(9) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_LOW_BITS _u(0x00000100) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_LOW_MSB _u(8) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_LOW_LSB _u(8) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_HIGH_BITS _u(0x00000080) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_HIGH_MSB _u(7) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_HIGH_LSB _u(7) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_LOW_BITS _u(0x00000040) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_LOW_MSB _u(6) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_LOW_LSB _u(6) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_HIGH_BITS _u(0x00000020) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_HIGH_MSB _u(5) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_HIGH_LSB _u(5) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_LOW_BITS _u(0x00000010) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_LOW_MSB _u(4) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_LOW_LSB _u(4) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_HIGH_BITS _u(0x00000008) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_HIGH_MSB _u(3) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_HIGH_LSB _u(3) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_LOW_BITS _u(0x00000004) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_LOW_MSB _u(2) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_LOW_LSB _u(2) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_HIGH_BITS _u(0x00000002) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_HIGH_MSB _u(1) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_HIGH_LSB _u(1) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_LOW_BITS _u(0x00000001) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_LOW_MSB _u(0) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_LOW_LSB _u(0) -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_LOW_ACCESS "RW" -// ============================================================================= -// Register : IO_BANK0_DORMANT_WAKE_INTF3 -// Description : Interrupt Force for dormant_wake -#define IO_BANK0_DORMANT_WAKE_INTF3_OFFSET _u(0x000002fc) -#define IO_BANK0_DORMANT_WAKE_INTF3_BITS _u(0xffffffff) -#define IO_BANK0_DORMANT_WAKE_INTF3_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO31_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO31_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO31_EDGE_HIGH_BITS _u(0x80000000) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO31_EDGE_HIGH_MSB _u(31) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO31_EDGE_HIGH_LSB _u(31) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO31_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO31_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO31_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO31_EDGE_LOW_BITS _u(0x40000000) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO31_EDGE_LOW_MSB _u(30) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO31_EDGE_LOW_LSB _u(30) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO31_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO31_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO31_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO31_LEVEL_HIGH_BITS _u(0x20000000) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO31_LEVEL_HIGH_MSB _u(29) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO31_LEVEL_HIGH_LSB _u(29) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO31_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO31_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO31_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO31_LEVEL_LOW_BITS _u(0x10000000) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO31_LEVEL_LOW_MSB _u(28) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO31_LEVEL_LOW_LSB _u(28) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO31_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO30_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO30_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO30_EDGE_HIGH_BITS _u(0x08000000) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO30_EDGE_HIGH_MSB _u(27) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO30_EDGE_HIGH_LSB _u(27) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO30_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO30_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO30_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO30_EDGE_LOW_BITS _u(0x04000000) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO30_EDGE_LOW_MSB _u(26) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO30_EDGE_LOW_LSB _u(26) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO30_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO30_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO30_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO30_LEVEL_HIGH_BITS _u(0x02000000) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO30_LEVEL_HIGH_MSB _u(25) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO30_LEVEL_HIGH_LSB _u(25) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO30_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO30_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO30_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO30_LEVEL_LOW_BITS _u(0x01000000) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO30_LEVEL_LOW_MSB _u(24) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO30_LEVEL_LOW_LSB _u(24) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO30_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_HIGH_BITS _u(0x00800000) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_HIGH_MSB _u(23) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_HIGH_LSB _u(23) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_LOW_BITS _u(0x00400000) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_LOW_MSB _u(22) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_LOW_LSB _u(22) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_HIGH_BITS _u(0x00200000) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_HIGH_MSB _u(21) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_HIGH_LSB _u(21) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_LOW_BITS _u(0x00100000) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_LOW_MSB _u(20) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_LOW_LSB _u(20) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_HIGH_BITS _u(0x00080000) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_HIGH_MSB _u(19) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_HIGH_LSB _u(19) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_LOW_BITS _u(0x00040000) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_LOW_MSB _u(18) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_LOW_LSB _u(18) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_HIGH_BITS _u(0x00020000) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_HIGH_MSB _u(17) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_HIGH_LSB _u(17) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_LOW_BITS _u(0x00010000) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_LOW_MSB _u(16) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_LOW_LSB _u(16) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_HIGH_BITS _u(0x00008000) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_HIGH_MSB _u(15) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_HIGH_LSB _u(15) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_LOW_BITS _u(0x00004000) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_LOW_MSB _u(14) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_LOW_LSB _u(14) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_HIGH_BITS _u(0x00002000) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_HIGH_MSB _u(13) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_HIGH_LSB _u(13) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_LOW_BITS _u(0x00001000) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_LOW_MSB _u(12) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_LOW_LSB _u(12) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_HIGH_BITS _u(0x00000800) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_HIGH_MSB _u(11) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_HIGH_LSB _u(11) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_LOW_BITS _u(0x00000400) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_LOW_MSB _u(10) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_LOW_LSB _u(10) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_HIGH_BITS _u(0x00000200) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_HIGH_MSB _u(9) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_HIGH_LSB _u(9) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_LOW_BITS _u(0x00000100) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_LOW_MSB _u(8) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_LOW_LSB _u(8) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_HIGH_BITS _u(0x00000080) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_HIGH_MSB _u(7) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_HIGH_LSB _u(7) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_LOW_BITS _u(0x00000040) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_LOW_MSB _u(6) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_LOW_LSB _u(6) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_HIGH_BITS _u(0x00000020) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_HIGH_MSB _u(5) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_HIGH_LSB _u(5) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_LOW_BITS _u(0x00000010) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_LOW_MSB _u(4) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_LOW_LSB _u(4) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_HIGH_BITS _u(0x00000008) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_HIGH_MSB _u(3) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_HIGH_LSB _u(3) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_LOW_BITS _u(0x00000004) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_LOW_MSB _u(2) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_LOW_LSB _u(2) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_HIGH_BITS _u(0x00000002) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_HIGH_MSB _u(1) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_HIGH_LSB _u(1) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_LOW_BITS _u(0x00000001) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_LOW_MSB _u(0) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_LOW_LSB _u(0) -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_LOW_ACCESS "RW" -// ============================================================================= -// Register : IO_BANK0_DORMANT_WAKE_INTF4 -// Description : Interrupt Force for dormant_wake -#define IO_BANK0_DORMANT_WAKE_INTF4_OFFSET _u(0x00000300) -#define IO_BANK0_DORMANT_WAKE_INTF4_BITS _u(0xffffffff) -#define IO_BANK0_DORMANT_WAKE_INTF4_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF4_GPIO39_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO39_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO39_EDGE_HIGH_BITS _u(0x80000000) -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO39_EDGE_HIGH_MSB _u(31) -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO39_EDGE_HIGH_LSB _u(31) -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO39_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF4_GPIO39_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO39_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO39_EDGE_LOW_BITS _u(0x40000000) -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO39_EDGE_LOW_MSB _u(30) -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO39_EDGE_LOW_LSB _u(30) -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO39_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF4_GPIO39_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO39_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO39_LEVEL_HIGH_BITS _u(0x20000000) -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO39_LEVEL_HIGH_MSB _u(29) -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO39_LEVEL_HIGH_LSB _u(29) -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO39_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF4_GPIO39_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO39_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO39_LEVEL_LOW_BITS _u(0x10000000) -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO39_LEVEL_LOW_MSB _u(28) -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO39_LEVEL_LOW_LSB _u(28) -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO39_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF4_GPIO38_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO38_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO38_EDGE_HIGH_BITS _u(0x08000000) -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO38_EDGE_HIGH_MSB _u(27) -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO38_EDGE_HIGH_LSB _u(27) -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO38_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF4_GPIO38_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO38_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO38_EDGE_LOW_BITS _u(0x04000000) -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO38_EDGE_LOW_MSB _u(26) -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO38_EDGE_LOW_LSB _u(26) -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO38_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF4_GPIO38_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO38_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO38_LEVEL_HIGH_BITS _u(0x02000000) -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO38_LEVEL_HIGH_MSB _u(25) -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO38_LEVEL_HIGH_LSB _u(25) -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO38_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF4_GPIO38_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO38_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO38_LEVEL_LOW_BITS _u(0x01000000) -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO38_LEVEL_LOW_MSB _u(24) -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO38_LEVEL_LOW_LSB _u(24) -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO38_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF4_GPIO37_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO37_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO37_EDGE_HIGH_BITS _u(0x00800000) -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO37_EDGE_HIGH_MSB _u(23) -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO37_EDGE_HIGH_LSB _u(23) -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO37_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF4_GPIO37_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO37_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO37_EDGE_LOW_BITS _u(0x00400000) -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO37_EDGE_LOW_MSB _u(22) -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO37_EDGE_LOW_LSB _u(22) -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO37_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF4_GPIO37_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO37_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO37_LEVEL_HIGH_BITS _u(0x00200000) -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO37_LEVEL_HIGH_MSB _u(21) -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO37_LEVEL_HIGH_LSB _u(21) -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO37_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF4_GPIO37_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO37_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO37_LEVEL_LOW_BITS _u(0x00100000) -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO37_LEVEL_LOW_MSB _u(20) -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO37_LEVEL_LOW_LSB _u(20) -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO37_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF4_GPIO36_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO36_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO36_EDGE_HIGH_BITS _u(0x00080000) -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO36_EDGE_HIGH_MSB _u(19) -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO36_EDGE_HIGH_LSB _u(19) -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO36_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF4_GPIO36_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO36_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO36_EDGE_LOW_BITS _u(0x00040000) -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO36_EDGE_LOW_MSB _u(18) -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO36_EDGE_LOW_LSB _u(18) -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO36_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF4_GPIO36_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO36_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO36_LEVEL_HIGH_BITS _u(0x00020000) -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO36_LEVEL_HIGH_MSB _u(17) -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO36_LEVEL_HIGH_LSB _u(17) -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO36_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF4_GPIO36_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO36_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO36_LEVEL_LOW_BITS _u(0x00010000) -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO36_LEVEL_LOW_MSB _u(16) -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO36_LEVEL_LOW_LSB _u(16) -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO36_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF4_GPIO35_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO35_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO35_EDGE_HIGH_BITS _u(0x00008000) -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO35_EDGE_HIGH_MSB _u(15) -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO35_EDGE_HIGH_LSB _u(15) -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO35_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF4_GPIO35_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO35_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO35_EDGE_LOW_BITS _u(0x00004000) -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO35_EDGE_LOW_MSB _u(14) -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO35_EDGE_LOW_LSB _u(14) -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO35_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF4_GPIO35_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO35_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO35_LEVEL_HIGH_BITS _u(0x00002000) -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO35_LEVEL_HIGH_MSB _u(13) -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO35_LEVEL_HIGH_LSB _u(13) -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO35_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF4_GPIO35_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO35_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO35_LEVEL_LOW_BITS _u(0x00001000) -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO35_LEVEL_LOW_MSB _u(12) -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO35_LEVEL_LOW_LSB _u(12) -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO35_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF4_GPIO34_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO34_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO34_EDGE_HIGH_BITS _u(0x00000800) -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO34_EDGE_HIGH_MSB _u(11) -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO34_EDGE_HIGH_LSB _u(11) -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO34_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF4_GPIO34_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO34_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO34_EDGE_LOW_BITS _u(0x00000400) -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO34_EDGE_LOW_MSB _u(10) -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO34_EDGE_LOW_LSB _u(10) -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO34_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF4_GPIO34_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO34_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO34_LEVEL_HIGH_BITS _u(0x00000200) -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO34_LEVEL_HIGH_MSB _u(9) -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO34_LEVEL_HIGH_LSB _u(9) -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO34_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF4_GPIO34_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO34_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO34_LEVEL_LOW_BITS _u(0x00000100) -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO34_LEVEL_LOW_MSB _u(8) -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO34_LEVEL_LOW_LSB _u(8) -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO34_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF4_GPIO33_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO33_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO33_EDGE_HIGH_BITS _u(0x00000080) -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO33_EDGE_HIGH_MSB _u(7) -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO33_EDGE_HIGH_LSB _u(7) -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO33_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF4_GPIO33_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO33_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO33_EDGE_LOW_BITS _u(0x00000040) -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO33_EDGE_LOW_MSB _u(6) -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO33_EDGE_LOW_LSB _u(6) -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO33_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF4_GPIO33_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO33_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO33_LEVEL_HIGH_BITS _u(0x00000020) -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO33_LEVEL_HIGH_MSB _u(5) -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO33_LEVEL_HIGH_LSB _u(5) -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO33_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF4_GPIO33_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO33_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO33_LEVEL_LOW_BITS _u(0x00000010) -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO33_LEVEL_LOW_MSB _u(4) -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO33_LEVEL_LOW_LSB _u(4) -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO33_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF4_GPIO32_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO32_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO32_EDGE_HIGH_BITS _u(0x00000008) -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO32_EDGE_HIGH_MSB _u(3) -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO32_EDGE_HIGH_LSB _u(3) -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO32_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF4_GPIO32_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO32_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO32_EDGE_LOW_BITS _u(0x00000004) -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO32_EDGE_LOW_MSB _u(2) -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO32_EDGE_LOW_LSB _u(2) -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO32_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF4_GPIO32_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO32_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO32_LEVEL_HIGH_BITS _u(0x00000002) -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO32_LEVEL_HIGH_MSB _u(1) -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO32_LEVEL_HIGH_LSB _u(1) -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO32_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF4_GPIO32_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO32_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO32_LEVEL_LOW_BITS _u(0x00000001) -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO32_LEVEL_LOW_MSB _u(0) -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO32_LEVEL_LOW_LSB _u(0) -#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO32_LEVEL_LOW_ACCESS "RW" -// ============================================================================= -// Register : IO_BANK0_DORMANT_WAKE_INTF5 -// Description : Interrupt Force for dormant_wake -#define IO_BANK0_DORMANT_WAKE_INTF5_OFFSET _u(0x00000304) -#define IO_BANK0_DORMANT_WAKE_INTF5_BITS _u(0xffffffff) -#define IO_BANK0_DORMANT_WAKE_INTF5_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF5_GPIO47_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO47_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO47_EDGE_HIGH_BITS _u(0x80000000) -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO47_EDGE_HIGH_MSB _u(31) -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO47_EDGE_HIGH_LSB _u(31) -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO47_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF5_GPIO47_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO47_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO47_EDGE_LOW_BITS _u(0x40000000) -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO47_EDGE_LOW_MSB _u(30) -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO47_EDGE_LOW_LSB _u(30) -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO47_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF5_GPIO47_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO47_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO47_LEVEL_HIGH_BITS _u(0x20000000) -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO47_LEVEL_HIGH_MSB _u(29) -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO47_LEVEL_HIGH_LSB _u(29) -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO47_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF5_GPIO47_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO47_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO47_LEVEL_LOW_BITS _u(0x10000000) -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO47_LEVEL_LOW_MSB _u(28) -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO47_LEVEL_LOW_LSB _u(28) -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO47_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF5_GPIO46_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO46_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO46_EDGE_HIGH_BITS _u(0x08000000) -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO46_EDGE_HIGH_MSB _u(27) -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO46_EDGE_HIGH_LSB _u(27) -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO46_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF5_GPIO46_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO46_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO46_EDGE_LOW_BITS _u(0x04000000) -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO46_EDGE_LOW_MSB _u(26) -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO46_EDGE_LOW_LSB _u(26) -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO46_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF5_GPIO46_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO46_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO46_LEVEL_HIGH_BITS _u(0x02000000) -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO46_LEVEL_HIGH_MSB _u(25) -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO46_LEVEL_HIGH_LSB _u(25) -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO46_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF5_GPIO46_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO46_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO46_LEVEL_LOW_BITS _u(0x01000000) -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO46_LEVEL_LOW_MSB _u(24) -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO46_LEVEL_LOW_LSB _u(24) -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO46_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF5_GPIO45_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO45_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO45_EDGE_HIGH_BITS _u(0x00800000) -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO45_EDGE_HIGH_MSB _u(23) -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO45_EDGE_HIGH_LSB _u(23) -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO45_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF5_GPIO45_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO45_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO45_EDGE_LOW_BITS _u(0x00400000) -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO45_EDGE_LOW_MSB _u(22) -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO45_EDGE_LOW_LSB _u(22) -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO45_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF5_GPIO45_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO45_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO45_LEVEL_HIGH_BITS _u(0x00200000) -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO45_LEVEL_HIGH_MSB _u(21) -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO45_LEVEL_HIGH_LSB _u(21) -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO45_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF5_GPIO45_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO45_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO45_LEVEL_LOW_BITS _u(0x00100000) -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO45_LEVEL_LOW_MSB _u(20) -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO45_LEVEL_LOW_LSB _u(20) -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO45_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF5_GPIO44_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO44_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO44_EDGE_HIGH_BITS _u(0x00080000) -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO44_EDGE_HIGH_MSB _u(19) -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO44_EDGE_HIGH_LSB _u(19) -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO44_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF5_GPIO44_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO44_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO44_EDGE_LOW_BITS _u(0x00040000) -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO44_EDGE_LOW_MSB _u(18) -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO44_EDGE_LOW_LSB _u(18) -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO44_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF5_GPIO44_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO44_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO44_LEVEL_HIGH_BITS _u(0x00020000) -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO44_LEVEL_HIGH_MSB _u(17) -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO44_LEVEL_HIGH_LSB _u(17) -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO44_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF5_GPIO44_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO44_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO44_LEVEL_LOW_BITS _u(0x00010000) -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO44_LEVEL_LOW_MSB _u(16) -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO44_LEVEL_LOW_LSB _u(16) -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO44_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF5_GPIO43_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO43_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO43_EDGE_HIGH_BITS _u(0x00008000) -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO43_EDGE_HIGH_MSB _u(15) -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO43_EDGE_HIGH_LSB _u(15) -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO43_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF5_GPIO43_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO43_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO43_EDGE_LOW_BITS _u(0x00004000) -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO43_EDGE_LOW_MSB _u(14) -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO43_EDGE_LOW_LSB _u(14) -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO43_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF5_GPIO43_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO43_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO43_LEVEL_HIGH_BITS _u(0x00002000) -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO43_LEVEL_HIGH_MSB _u(13) -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO43_LEVEL_HIGH_LSB _u(13) -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO43_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF5_GPIO43_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO43_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO43_LEVEL_LOW_BITS _u(0x00001000) -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO43_LEVEL_LOW_MSB _u(12) -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO43_LEVEL_LOW_LSB _u(12) -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO43_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF5_GPIO42_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO42_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO42_EDGE_HIGH_BITS _u(0x00000800) -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO42_EDGE_HIGH_MSB _u(11) -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO42_EDGE_HIGH_LSB _u(11) -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO42_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF5_GPIO42_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO42_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO42_EDGE_LOW_BITS _u(0x00000400) -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO42_EDGE_LOW_MSB _u(10) -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO42_EDGE_LOW_LSB _u(10) -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO42_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF5_GPIO42_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO42_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO42_LEVEL_HIGH_BITS _u(0x00000200) -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO42_LEVEL_HIGH_MSB _u(9) -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO42_LEVEL_HIGH_LSB _u(9) -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO42_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF5_GPIO42_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO42_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO42_LEVEL_LOW_BITS _u(0x00000100) -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO42_LEVEL_LOW_MSB _u(8) -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO42_LEVEL_LOW_LSB _u(8) -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO42_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF5_GPIO41_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO41_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO41_EDGE_HIGH_BITS _u(0x00000080) -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO41_EDGE_HIGH_MSB _u(7) -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO41_EDGE_HIGH_LSB _u(7) -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO41_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF5_GPIO41_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO41_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO41_EDGE_LOW_BITS _u(0x00000040) -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO41_EDGE_LOW_MSB _u(6) -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO41_EDGE_LOW_LSB _u(6) -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO41_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF5_GPIO41_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO41_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO41_LEVEL_HIGH_BITS _u(0x00000020) -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO41_LEVEL_HIGH_MSB _u(5) -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO41_LEVEL_HIGH_LSB _u(5) -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO41_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF5_GPIO41_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO41_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO41_LEVEL_LOW_BITS _u(0x00000010) -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO41_LEVEL_LOW_MSB _u(4) -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO41_LEVEL_LOW_LSB _u(4) -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO41_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF5_GPIO40_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO40_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO40_EDGE_HIGH_BITS _u(0x00000008) -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO40_EDGE_HIGH_MSB _u(3) -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO40_EDGE_HIGH_LSB _u(3) -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO40_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF5_GPIO40_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO40_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO40_EDGE_LOW_BITS _u(0x00000004) -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO40_EDGE_LOW_MSB _u(2) -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO40_EDGE_LOW_LSB _u(2) -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO40_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF5_GPIO40_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO40_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO40_LEVEL_HIGH_BITS _u(0x00000002) -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO40_LEVEL_HIGH_MSB _u(1) -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO40_LEVEL_HIGH_LSB _u(1) -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO40_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTF5_GPIO40_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO40_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO40_LEVEL_LOW_BITS _u(0x00000001) -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO40_LEVEL_LOW_MSB _u(0) -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO40_LEVEL_LOW_LSB _u(0) -#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO40_LEVEL_LOW_ACCESS "RW" -// ============================================================================= -// Register : IO_BANK0_DORMANT_WAKE_INTS0 -// Description : Interrupt status after masking & forcing for dormant_wake -#define IO_BANK0_DORMANT_WAKE_INTS0_OFFSET _u(0x00000308) -#define IO_BANK0_DORMANT_WAKE_INTS0_BITS _u(0xffffffff) -#define IO_BANK0_DORMANT_WAKE_INTS0_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_HIGH_BITS _u(0x80000000) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_HIGH_MSB _u(31) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_HIGH_LSB _u(31) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_LOW_BITS _u(0x40000000) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_LOW_MSB _u(30) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_LOW_LSB _u(30) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_HIGH_BITS _u(0x20000000) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_HIGH_MSB _u(29) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_HIGH_LSB _u(29) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_LOW_BITS _u(0x10000000) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_LOW_MSB _u(28) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_LOW_LSB _u(28) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_HIGH_BITS _u(0x08000000) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_HIGH_MSB _u(27) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_HIGH_LSB _u(27) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_LOW_BITS _u(0x04000000) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_LOW_MSB _u(26) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_LOW_LSB _u(26) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_HIGH_BITS _u(0x02000000) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_HIGH_MSB _u(25) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_HIGH_LSB _u(25) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_LOW_BITS _u(0x01000000) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_LOW_MSB _u(24) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_LOW_LSB _u(24) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_HIGH_BITS _u(0x00800000) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_HIGH_MSB _u(23) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_HIGH_LSB _u(23) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_LOW_BITS _u(0x00400000) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_LOW_MSB _u(22) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_LOW_LSB _u(22) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_HIGH_BITS _u(0x00200000) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_HIGH_MSB _u(21) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_HIGH_LSB _u(21) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_LOW_BITS _u(0x00100000) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_LOW_MSB _u(20) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_LOW_LSB _u(20) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_HIGH_BITS _u(0x00080000) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_HIGH_MSB _u(19) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_HIGH_LSB _u(19) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_LOW_BITS _u(0x00040000) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_LOW_MSB _u(18) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_LOW_LSB _u(18) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_HIGH_BITS _u(0x00020000) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_HIGH_MSB _u(17) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_HIGH_LSB _u(17) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_LOW_BITS _u(0x00010000) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_LOW_MSB _u(16) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_LOW_LSB _u(16) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_HIGH_BITS _u(0x00008000) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_HIGH_MSB _u(15) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_HIGH_LSB _u(15) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_LOW_BITS _u(0x00004000) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_LOW_MSB _u(14) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_LOW_LSB _u(14) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_HIGH_BITS _u(0x00002000) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_HIGH_MSB _u(13) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_HIGH_LSB _u(13) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_LOW_BITS _u(0x00001000) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_LOW_MSB _u(12) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_LOW_LSB _u(12) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_HIGH_BITS _u(0x00000800) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_HIGH_MSB _u(11) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_HIGH_LSB _u(11) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_LOW_BITS _u(0x00000400) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_LOW_MSB _u(10) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_LOW_LSB _u(10) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_HIGH_BITS _u(0x00000200) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_HIGH_MSB _u(9) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_HIGH_LSB _u(9) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_LOW_BITS _u(0x00000100) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_LOW_MSB _u(8) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_LOW_LSB _u(8) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_HIGH_BITS _u(0x00000080) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_HIGH_MSB _u(7) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_HIGH_LSB _u(7) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_LOW_BITS _u(0x00000040) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_LOW_MSB _u(6) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_LOW_LSB _u(6) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_HIGH_BITS _u(0x00000020) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_HIGH_MSB _u(5) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_HIGH_LSB _u(5) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_LOW_BITS _u(0x00000010) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_LOW_MSB _u(4) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_LOW_LSB _u(4) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_HIGH_BITS _u(0x00000008) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_HIGH_MSB _u(3) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_HIGH_LSB _u(3) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_LOW_BITS _u(0x00000004) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_LOW_MSB _u(2) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_LOW_LSB _u(2) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_HIGH_BITS _u(0x00000002) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_HIGH_MSB _u(1) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_HIGH_LSB _u(1) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_LOW_BITS _u(0x00000001) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_LOW_MSB _u(0) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_LOW_LSB _u(0) -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_LOW_ACCESS "RO" -// ============================================================================= -// Register : IO_BANK0_DORMANT_WAKE_INTS1 -// Description : Interrupt status after masking & forcing for dormant_wake -#define IO_BANK0_DORMANT_WAKE_INTS1_OFFSET _u(0x0000030c) -#define IO_BANK0_DORMANT_WAKE_INTS1_BITS _u(0xffffffff) -#define IO_BANK0_DORMANT_WAKE_INTS1_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_HIGH_BITS _u(0x80000000) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_HIGH_MSB _u(31) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_HIGH_LSB _u(31) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_LOW_BITS _u(0x40000000) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_LOW_MSB _u(30) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_LOW_LSB _u(30) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_HIGH_BITS _u(0x20000000) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_HIGH_MSB _u(29) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_HIGH_LSB _u(29) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_LOW_BITS _u(0x10000000) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_LOW_MSB _u(28) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_LOW_LSB _u(28) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_HIGH_BITS _u(0x08000000) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_HIGH_MSB _u(27) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_HIGH_LSB _u(27) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_LOW_BITS _u(0x04000000) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_LOW_MSB _u(26) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_LOW_LSB _u(26) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_HIGH_BITS _u(0x02000000) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_HIGH_MSB _u(25) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_HIGH_LSB _u(25) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_LOW_BITS _u(0x01000000) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_LOW_MSB _u(24) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_LOW_LSB _u(24) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_HIGH_BITS _u(0x00800000) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_HIGH_MSB _u(23) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_HIGH_LSB _u(23) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_LOW_BITS _u(0x00400000) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_LOW_MSB _u(22) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_LOW_LSB _u(22) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_HIGH_BITS _u(0x00200000) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_HIGH_MSB _u(21) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_HIGH_LSB _u(21) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_LOW_BITS _u(0x00100000) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_LOW_MSB _u(20) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_LOW_LSB _u(20) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_HIGH_BITS _u(0x00080000) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_HIGH_MSB _u(19) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_HIGH_LSB _u(19) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_LOW_BITS _u(0x00040000) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_LOW_MSB _u(18) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_LOW_LSB _u(18) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_HIGH_BITS _u(0x00020000) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_HIGH_MSB _u(17) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_HIGH_LSB _u(17) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_LOW_BITS _u(0x00010000) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_LOW_MSB _u(16) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_LOW_LSB _u(16) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_HIGH_BITS _u(0x00008000) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_HIGH_MSB _u(15) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_HIGH_LSB _u(15) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_LOW_BITS _u(0x00004000) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_LOW_MSB _u(14) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_LOW_LSB _u(14) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_HIGH_BITS _u(0x00002000) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_HIGH_MSB _u(13) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_HIGH_LSB _u(13) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_LOW_BITS _u(0x00001000) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_LOW_MSB _u(12) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_LOW_LSB _u(12) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_HIGH_BITS _u(0x00000800) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_HIGH_MSB _u(11) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_HIGH_LSB _u(11) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_LOW_BITS _u(0x00000400) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_LOW_MSB _u(10) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_LOW_LSB _u(10) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_HIGH_BITS _u(0x00000200) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_HIGH_MSB _u(9) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_HIGH_LSB _u(9) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_LOW_BITS _u(0x00000100) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_LOW_MSB _u(8) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_LOW_LSB _u(8) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_HIGH_BITS _u(0x00000080) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_HIGH_MSB _u(7) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_HIGH_LSB _u(7) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_LOW_BITS _u(0x00000040) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_LOW_MSB _u(6) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_LOW_LSB _u(6) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_HIGH_BITS _u(0x00000020) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_HIGH_MSB _u(5) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_HIGH_LSB _u(5) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_LOW_BITS _u(0x00000010) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_LOW_MSB _u(4) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_LOW_LSB _u(4) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_HIGH_BITS _u(0x00000008) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_HIGH_MSB _u(3) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_HIGH_LSB _u(3) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_LOW_BITS _u(0x00000004) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_LOW_MSB _u(2) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_LOW_LSB _u(2) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_HIGH_BITS _u(0x00000002) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_HIGH_MSB _u(1) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_HIGH_LSB _u(1) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_LOW_BITS _u(0x00000001) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_LOW_MSB _u(0) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_LOW_LSB _u(0) -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_LOW_ACCESS "RO" -// ============================================================================= -// Register : IO_BANK0_DORMANT_WAKE_INTS2 -// Description : Interrupt status after masking & forcing for dormant_wake -#define IO_BANK0_DORMANT_WAKE_INTS2_OFFSET _u(0x00000310) -#define IO_BANK0_DORMANT_WAKE_INTS2_BITS _u(0xffffffff) -#define IO_BANK0_DORMANT_WAKE_INTS2_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_HIGH_BITS _u(0x80000000) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_HIGH_MSB _u(31) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_HIGH_LSB _u(31) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_LOW_BITS _u(0x40000000) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_LOW_MSB _u(30) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_LOW_LSB _u(30) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_HIGH_BITS _u(0x20000000) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_HIGH_MSB _u(29) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_HIGH_LSB _u(29) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_LOW_BITS _u(0x10000000) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_LOW_MSB _u(28) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_LOW_LSB _u(28) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_HIGH_BITS _u(0x08000000) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_HIGH_MSB _u(27) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_HIGH_LSB _u(27) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_LOW_BITS _u(0x04000000) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_LOW_MSB _u(26) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_LOW_LSB _u(26) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_HIGH_BITS _u(0x02000000) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_HIGH_MSB _u(25) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_HIGH_LSB _u(25) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_LOW_BITS _u(0x01000000) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_LOW_MSB _u(24) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_LOW_LSB _u(24) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_HIGH_BITS _u(0x00800000) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_HIGH_MSB _u(23) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_HIGH_LSB _u(23) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_LOW_BITS _u(0x00400000) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_LOW_MSB _u(22) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_LOW_LSB _u(22) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_HIGH_BITS _u(0x00200000) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_HIGH_MSB _u(21) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_HIGH_LSB _u(21) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_LOW_BITS _u(0x00100000) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_LOW_MSB _u(20) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_LOW_LSB _u(20) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_HIGH_BITS _u(0x00080000) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_HIGH_MSB _u(19) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_HIGH_LSB _u(19) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_LOW_BITS _u(0x00040000) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_LOW_MSB _u(18) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_LOW_LSB _u(18) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_HIGH_BITS _u(0x00020000) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_HIGH_MSB _u(17) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_HIGH_LSB _u(17) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_LOW_BITS _u(0x00010000) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_LOW_MSB _u(16) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_LOW_LSB _u(16) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_HIGH_BITS _u(0x00008000) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_HIGH_MSB _u(15) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_HIGH_LSB _u(15) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_LOW_BITS _u(0x00004000) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_LOW_MSB _u(14) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_LOW_LSB _u(14) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_HIGH_BITS _u(0x00002000) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_HIGH_MSB _u(13) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_HIGH_LSB _u(13) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_LOW_BITS _u(0x00001000) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_LOW_MSB _u(12) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_LOW_LSB _u(12) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_HIGH_BITS _u(0x00000800) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_HIGH_MSB _u(11) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_HIGH_LSB _u(11) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_LOW_BITS _u(0x00000400) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_LOW_MSB _u(10) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_LOW_LSB _u(10) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_HIGH_BITS _u(0x00000200) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_HIGH_MSB _u(9) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_HIGH_LSB _u(9) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_LOW_BITS _u(0x00000100) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_LOW_MSB _u(8) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_LOW_LSB _u(8) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_HIGH_BITS _u(0x00000080) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_HIGH_MSB _u(7) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_HIGH_LSB _u(7) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_LOW_BITS _u(0x00000040) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_LOW_MSB _u(6) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_LOW_LSB _u(6) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_HIGH_BITS _u(0x00000020) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_HIGH_MSB _u(5) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_HIGH_LSB _u(5) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_LOW_BITS _u(0x00000010) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_LOW_MSB _u(4) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_LOW_LSB _u(4) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_HIGH_BITS _u(0x00000008) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_HIGH_MSB _u(3) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_HIGH_LSB _u(3) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_LOW_BITS _u(0x00000004) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_LOW_MSB _u(2) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_LOW_LSB _u(2) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_HIGH_BITS _u(0x00000002) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_HIGH_MSB _u(1) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_HIGH_LSB _u(1) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_LOW_BITS _u(0x00000001) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_LOW_MSB _u(0) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_LOW_LSB _u(0) -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_LOW_ACCESS "RO" -// ============================================================================= -// Register : IO_BANK0_DORMANT_WAKE_INTS3 -// Description : Interrupt status after masking & forcing for dormant_wake -#define IO_BANK0_DORMANT_WAKE_INTS3_OFFSET _u(0x00000314) -#define IO_BANK0_DORMANT_WAKE_INTS3_BITS _u(0xffffffff) -#define IO_BANK0_DORMANT_WAKE_INTS3_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO31_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO31_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO31_EDGE_HIGH_BITS _u(0x80000000) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO31_EDGE_HIGH_MSB _u(31) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO31_EDGE_HIGH_LSB _u(31) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO31_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO31_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO31_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO31_EDGE_LOW_BITS _u(0x40000000) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO31_EDGE_LOW_MSB _u(30) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO31_EDGE_LOW_LSB _u(30) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO31_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO31_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO31_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO31_LEVEL_HIGH_BITS _u(0x20000000) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO31_LEVEL_HIGH_MSB _u(29) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO31_LEVEL_HIGH_LSB _u(29) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO31_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO31_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO31_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO31_LEVEL_LOW_BITS _u(0x10000000) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO31_LEVEL_LOW_MSB _u(28) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO31_LEVEL_LOW_LSB _u(28) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO31_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO30_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO30_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO30_EDGE_HIGH_BITS _u(0x08000000) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO30_EDGE_HIGH_MSB _u(27) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO30_EDGE_HIGH_LSB _u(27) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO30_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO30_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO30_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO30_EDGE_LOW_BITS _u(0x04000000) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO30_EDGE_LOW_MSB _u(26) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO30_EDGE_LOW_LSB _u(26) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO30_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO30_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO30_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO30_LEVEL_HIGH_BITS _u(0x02000000) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO30_LEVEL_HIGH_MSB _u(25) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO30_LEVEL_HIGH_LSB _u(25) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO30_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO30_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO30_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO30_LEVEL_LOW_BITS _u(0x01000000) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO30_LEVEL_LOW_MSB _u(24) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO30_LEVEL_LOW_LSB _u(24) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO30_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_HIGH_BITS _u(0x00800000) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_HIGH_MSB _u(23) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_HIGH_LSB _u(23) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_LOW_BITS _u(0x00400000) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_LOW_MSB _u(22) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_LOW_LSB _u(22) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_HIGH_BITS _u(0x00200000) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_HIGH_MSB _u(21) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_HIGH_LSB _u(21) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_LOW_BITS _u(0x00100000) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_LOW_MSB _u(20) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_LOW_LSB _u(20) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_HIGH_BITS _u(0x00080000) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_HIGH_MSB _u(19) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_HIGH_LSB _u(19) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_LOW_BITS _u(0x00040000) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_LOW_MSB _u(18) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_LOW_LSB _u(18) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_HIGH_BITS _u(0x00020000) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_HIGH_MSB _u(17) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_HIGH_LSB _u(17) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_LOW_BITS _u(0x00010000) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_LOW_MSB _u(16) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_LOW_LSB _u(16) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_HIGH_BITS _u(0x00008000) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_HIGH_MSB _u(15) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_HIGH_LSB _u(15) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_LOW_BITS _u(0x00004000) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_LOW_MSB _u(14) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_LOW_LSB _u(14) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_HIGH_BITS _u(0x00002000) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_HIGH_MSB _u(13) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_HIGH_LSB _u(13) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_LOW_BITS _u(0x00001000) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_LOW_MSB _u(12) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_LOW_LSB _u(12) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_HIGH_BITS _u(0x00000800) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_HIGH_MSB _u(11) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_HIGH_LSB _u(11) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_LOW_BITS _u(0x00000400) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_LOW_MSB _u(10) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_LOW_LSB _u(10) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_HIGH_BITS _u(0x00000200) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_HIGH_MSB _u(9) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_HIGH_LSB _u(9) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_LOW_BITS _u(0x00000100) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_LOW_MSB _u(8) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_LOW_LSB _u(8) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_HIGH_BITS _u(0x00000080) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_HIGH_MSB _u(7) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_HIGH_LSB _u(7) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_LOW_BITS _u(0x00000040) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_LOW_MSB _u(6) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_LOW_LSB _u(6) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_HIGH_BITS _u(0x00000020) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_HIGH_MSB _u(5) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_HIGH_LSB _u(5) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_LOW_BITS _u(0x00000010) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_LOW_MSB _u(4) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_LOW_LSB _u(4) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_HIGH_BITS _u(0x00000008) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_HIGH_MSB _u(3) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_HIGH_LSB _u(3) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_LOW_BITS _u(0x00000004) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_LOW_MSB _u(2) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_LOW_LSB _u(2) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_HIGH_BITS _u(0x00000002) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_HIGH_MSB _u(1) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_HIGH_LSB _u(1) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_LOW_BITS _u(0x00000001) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_LOW_MSB _u(0) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_LOW_LSB _u(0) -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_LOW_ACCESS "RO" -// ============================================================================= -// Register : IO_BANK0_DORMANT_WAKE_INTS4 -// Description : Interrupt status after masking & forcing for dormant_wake -#define IO_BANK0_DORMANT_WAKE_INTS4_OFFSET _u(0x00000318) -#define IO_BANK0_DORMANT_WAKE_INTS4_BITS _u(0xffffffff) -#define IO_BANK0_DORMANT_WAKE_INTS4_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS4_GPIO39_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO39_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO39_EDGE_HIGH_BITS _u(0x80000000) -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO39_EDGE_HIGH_MSB _u(31) -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO39_EDGE_HIGH_LSB _u(31) -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO39_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS4_GPIO39_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO39_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO39_EDGE_LOW_BITS _u(0x40000000) -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO39_EDGE_LOW_MSB _u(30) -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO39_EDGE_LOW_LSB _u(30) -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO39_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS4_GPIO39_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO39_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO39_LEVEL_HIGH_BITS _u(0x20000000) -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO39_LEVEL_HIGH_MSB _u(29) -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO39_LEVEL_HIGH_LSB _u(29) -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO39_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS4_GPIO39_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO39_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO39_LEVEL_LOW_BITS _u(0x10000000) -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO39_LEVEL_LOW_MSB _u(28) -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO39_LEVEL_LOW_LSB _u(28) -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO39_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS4_GPIO38_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO38_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO38_EDGE_HIGH_BITS _u(0x08000000) -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO38_EDGE_HIGH_MSB _u(27) -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO38_EDGE_HIGH_LSB _u(27) -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO38_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS4_GPIO38_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO38_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO38_EDGE_LOW_BITS _u(0x04000000) -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO38_EDGE_LOW_MSB _u(26) -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO38_EDGE_LOW_LSB _u(26) -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO38_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS4_GPIO38_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO38_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO38_LEVEL_HIGH_BITS _u(0x02000000) -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO38_LEVEL_HIGH_MSB _u(25) -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO38_LEVEL_HIGH_LSB _u(25) -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO38_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS4_GPIO38_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO38_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO38_LEVEL_LOW_BITS _u(0x01000000) -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO38_LEVEL_LOW_MSB _u(24) -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO38_LEVEL_LOW_LSB _u(24) -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO38_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS4_GPIO37_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO37_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO37_EDGE_HIGH_BITS _u(0x00800000) -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO37_EDGE_HIGH_MSB _u(23) -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO37_EDGE_HIGH_LSB _u(23) -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO37_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS4_GPIO37_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO37_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO37_EDGE_LOW_BITS _u(0x00400000) -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO37_EDGE_LOW_MSB _u(22) -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO37_EDGE_LOW_LSB _u(22) -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO37_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS4_GPIO37_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO37_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO37_LEVEL_HIGH_BITS _u(0x00200000) -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO37_LEVEL_HIGH_MSB _u(21) -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO37_LEVEL_HIGH_LSB _u(21) -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO37_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS4_GPIO37_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO37_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO37_LEVEL_LOW_BITS _u(0x00100000) -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO37_LEVEL_LOW_MSB _u(20) -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO37_LEVEL_LOW_LSB _u(20) -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO37_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS4_GPIO36_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO36_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO36_EDGE_HIGH_BITS _u(0x00080000) -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO36_EDGE_HIGH_MSB _u(19) -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO36_EDGE_HIGH_LSB _u(19) -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO36_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS4_GPIO36_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO36_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO36_EDGE_LOW_BITS _u(0x00040000) -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO36_EDGE_LOW_MSB _u(18) -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO36_EDGE_LOW_LSB _u(18) -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO36_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS4_GPIO36_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO36_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO36_LEVEL_HIGH_BITS _u(0x00020000) -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO36_LEVEL_HIGH_MSB _u(17) -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO36_LEVEL_HIGH_LSB _u(17) -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO36_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS4_GPIO36_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO36_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO36_LEVEL_LOW_BITS _u(0x00010000) -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO36_LEVEL_LOW_MSB _u(16) -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO36_LEVEL_LOW_LSB _u(16) -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO36_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS4_GPIO35_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO35_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO35_EDGE_HIGH_BITS _u(0x00008000) -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO35_EDGE_HIGH_MSB _u(15) -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO35_EDGE_HIGH_LSB _u(15) -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO35_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS4_GPIO35_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO35_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO35_EDGE_LOW_BITS _u(0x00004000) -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO35_EDGE_LOW_MSB _u(14) -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO35_EDGE_LOW_LSB _u(14) -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO35_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS4_GPIO35_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO35_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO35_LEVEL_HIGH_BITS _u(0x00002000) -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO35_LEVEL_HIGH_MSB _u(13) -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO35_LEVEL_HIGH_LSB _u(13) -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO35_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS4_GPIO35_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO35_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO35_LEVEL_LOW_BITS _u(0x00001000) -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO35_LEVEL_LOW_MSB _u(12) -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO35_LEVEL_LOW_LSB _u(12) -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO35_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS4_GPIO34_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO34_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO34_EDGE_HIGH_BITS _u(0x00000800) -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO34_EDGE_HIGH_MSB _u(11) -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO34_EDGE_HIGH_LSB _u(11) -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO34_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS4_GPIO34_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO34_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO34_EDGE_LOW_BITS _u(0x00000400) -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO34_EDGE_LOW_MSB _u(10) -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO34_EDGE_LOW_LSB _u(10) -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO34_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS4_GPIO34_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO34_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO34_LEVEL_HIGH_BITS _u(0x00000200) -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO34_LEVEL_HIGH_MSB _u(9) -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO34_LEVEL_HIGH_LSB _u(9) -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO34_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS4_GPIO34_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO34_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO34_LEVEL_LOW_BITS _u(0x00000100) -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO34_LEVEL_LOW_MSB _u(8) -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO34_LEVEL_LOW_LSB _u(8) -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO34_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS4_GPIO33_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO33_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO33_EDGE_HIGH_BITS _u(0x00000080) -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO33_EDGE_HIGH_MSB _u(7) -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO33_EDGE_HIGH_LSB _u(7) -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO33_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS4_GPIO33_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO33_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO33_EDGE_LOW_BITS _u(0x00000040) -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO33_EDGE_LOW_MSB _u(6) -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO33_EDGE_LOW_LSB _u(6) -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO33_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS4_GPIO33_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO33_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO33_LEVEL_HIGH_BITS _u(0x00000020) -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO33_LEVEL_HIGH_MSB _u(5) -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO33_LEVEL_HIGH_LSB _u(5) -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO33_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS4_GPIO33_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO33_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO33_LEVEL_LOW_BITS _u(0x00000010) -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO33_LEVEL_LOW_MSB _u(4) -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO33_LEVEL_LOW_LSB _u(4) -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO33_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS4_GPIO32_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO32_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO32_EDGE_HIGH_BITS _u(0x00000008) -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO32_EDGE_HIGH_MSB _u(3) -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO32_EDGE_HIGH_LSB _u(3) -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO32_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS4_GPIO32_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO32_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO32_EDGE_LOW_BITS _u(0x00000004) -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO32_EDGE_LOW_MSB _u(2) -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO32_EDGE_LOW_LSB _u(2) -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO32_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS4_GPIO32_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO32_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO32_LEVEL_HIGH_BITS _u(0x00000002) -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO32_LEVEL_HIGH_MSB _u(1) -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO32_LEVEL_HIGH_LSB _u(1) -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO32_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS4_GPIO32_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO32_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO32_LEVEL_LOW_BITS _u(0x00000001) -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO32_LEVEL_LOW_MSB _u(0) -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO32_LEVEL_LOW_LSB _u(0) -#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO32_LEVEL_LOW_ACCESS "RO" -// ============================================================================= -// Register : IO_BANK0_DORMANT_WAKE_INTS5 -// Description : Interrupt status after masking & forcing for dormant_wake -#define IO_BANK0_DORMANT_WAKE_INTS5_OFFSET _u(0x0000031c) -#define IO_BANK0_DORMANT_WAKE_INTS5_BITS _u(0xffffffff) -#define IO_BANK0_DORMANT_WAKE_INTS5_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS5_GPIO47_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO47_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO47_EDGE_HIGH_BITS _u(0x80000000) -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO47_EDGE_HIGH_MSB _u(31) -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO47_EDGE_HIGH_LSB _u(31) -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO47_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS5_GPIO47_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO47_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO47_EDGE_LOW_BITS _u(0x40000000) -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO47_EDGE_LOW_MSB _u(30) -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO47_EDGE_LOW_LSB _u(30) -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO47_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS5_GPIO47_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO47_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO47_LEVEL_HIGH_BITS _u(0x20000000) -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO47_LEVEL_HIGH_MSB _u(29) -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO47_LEVEL_HIGH_LSB _u(29) -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO47_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS5_GPIO47_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO47_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO47_LEVEL_LOW_BITS _u(0x10000000) -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO47_LEVEL_LOW_MSB _u(28) -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO47_LEVEL_LOW_LSB _u(28) -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO47_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS5_GPIO46_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO46_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO46_EDGE_HIGH_BITS _u(0x08000000) -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO46_EDGE_HIGH_MSB _u(27) -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO46_EDGE_HIGH_LSB _u(27) -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO46_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS5_GPIO46_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO46_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO46_EDGE_LOW_BITS _u(0x04000000) -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO46_EDGE_LOW_MSB _u(26) -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO46_EDGE_LOW_LSB _u(26) -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO46_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS5_GPIO46_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO46_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO46_LEVEL_HIGH_BITS _u(0x02000000) -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO46_LEVEL_HIGH_MSB _u(25) -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO46_LEVEL_HIGH_LSB _u(25) -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO46_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS5_GPIO46_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO46_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO46_LEVEL_LOW_BITS _u(0x01000000) -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO46_LEVEL_LOW_MSB _u(24) -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO46_LEVEL_LOW_LSB _u(24) -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO46_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS5_GPIO45_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO45_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO45_EDGE_HIGH_BITS _u(0x00800000) -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO45_EDGE_HIGH_MSB _u(23) -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO45_EDGE_HIGH_LSB _u(23) -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO45_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS5_GPIO45_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO45_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO45_EDGE_LOW_BITS _u(0x00400000) -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO45_EDGE_LOW_MSB _u(22) -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO45_EDGE_LOW_LSB _u(22) -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO45_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS5_GPIO45_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO45_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO45_LEVEL_HIGH_BITS _u(0x00200000) -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO45_LEVEL_HIGH_MSB _u(21) -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO45_LEVEL_HIGH_LSB _u(21) -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO45_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS5_GPIO45_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO45_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO45_LEVEL_LOW_BITS _u(0x00100000) -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO45_LEVEL_LOW_MSB _u(20) -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO45_LEVEL_LOW_LSB _u(20) -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO45_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS5_GPIO44_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO44_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO44_EDGE_HIGH_BITS _u(0x00080000) -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO44_EDGE_HIGH_MSB _u(19) -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO44_EDGE_HIGH_LSB _u(19) -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO44_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS5_GPIO44_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO44_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO44_EDGE_LOW_BITS _u(0x00040000) -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO44_EDGE_LOW_MSB _u(18) -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO44_EDGE_LOW_LSB _u(18) -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO44_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS5_GPIO44_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO44_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO44_LEVEL_HIGH_BITS _u(0x00020000) -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO44_LEVEL_HIGH_MSB _u(17) -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO44_LEVEL_HIGH_LSB _u(17) -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO44_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS5_GPIO44_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO44_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO44_LEVEL_LOW_BITS _u(0x00010000) -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO44_LEVEL_LOW_MSB _u(16) -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO44_LEVEL_LOW_LSB _u(16) -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO44_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS5_GPIO43_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO43_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO43_EDGE_HIGH_BITS _u(0x00008000) -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO43_EDGE_HIGH_MSB _u(15) -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO43_EDGE_HIGH_LSB _u(15) -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO43_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS5_GPIO43_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO43_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO43_EDGE_LOW_BITS _u(0x00004000) -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO43_EDGE_LOW_MSB _u(14) -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO43_EDGE_LOW_LSB _u(14) -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO43_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS5_GPIO43_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO43_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO43_LEVEL_HIGH_BITS _u(0x00002000) -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO43_LEVEL_HIGH_MSB _u(13) -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO43_LEVEL_HIGH_LSB _u(13) -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO43_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS5_GPIO43_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO43_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO43_LEVEL_LOW_BITS _u(0x00001000) -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO43_LEVEL_LOW_MSB _u(12) -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO43_LEVEL_LOW_LSB _u(12) -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO43_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS5_GPIO42_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO42_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO42_EDGE_HIGH_BITS _u(0x00000800) -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO42_EDGE_HIGH_MSB _u(11) -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO42_EDGE_HIGH_LSB _u(11) -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO42_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS5_GPIO42_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO42_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO42_EDGE_LOW_BITS _u(0x00000400) -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO42_EDGE_LOW_MSB _u(10) -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO42_EDGE_LOW_LSB _u(10) -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO42_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS5_GPIO42_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO42_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO42_LEVEL_HIGH_BITS _u(0x00000200) -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO42_LEVEL_HIGH_MSB _u(9) -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO42_LEVEL_HIGH_LSB _u(9) -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO42_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS5_GPIO42_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO42_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO42_LEVEL_LOW_BITS _u(0x00000100) -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO42_LEVEL_LOW_MSB _u(8) -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO42_LEVEL_LOW_LSB _u(8) -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO42_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS5_GPIO41_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO41_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO41_EDGE_HIGH_BITS _u(0x00000080) -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO41_EDGE_HIGH_MSB _u(7) -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO41_EDGE_HIGH_LSB _u(7) -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO41_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS5_GPIO41_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO41_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO41_EDGE_LOW_BITS _u(0x00000040) -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO41_EDGE_LOW_MSB _u(6) -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO41_EDGE_LOW_LSB _u(6) -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO41_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS5_GPIO41_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO41_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO41_LEVEL_HIGH_BITS _u(0x00000020) -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO41_LEVEL_HIGH_MSB _u(5) -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO41_LEVEL_HIGH_LSB _u(5) -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO41_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS5_GPIO41_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO41_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO41_LEVEL_LOW_BITS _u(0x00000010) -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO41_LEVEL_LOW_MSB _u(4) -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO41_LEVEL_LOW_LSB _u(4) -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO41_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS5_GPIO40_EDGE_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO40_EDGE_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO40_EDGE_HIGH_BITS _u(0x00000008) -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO40_EDGE_HIGH_MSB _u(3) -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO40_EDGE_HIGH_LSB _u(3) -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO40_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS5_GPIO40_EDGE_LOW -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO40_EDGE_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO40_EDGE_LOW_BITS _u(0x00000004) -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO40_EDGE_LOW_MSB _u(2) -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO40_EDGE_LOW_LSB _u(2) -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO40_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS5_GPIO40_LEVEL_HIGH -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO40_LEVEL_HIGH_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO40_LEVEL_HIGH_BITS _u(0x00000002) -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO40_LEVEL_HIGH_MSB _u(1) -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO40_LEVEL_HIGH_LSB _u(1) -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO40_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_BANK0_DORMANT_WAKE_INTS5_GPIO40_LEVEL_LOW -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO40_LEVEL_LOW_RESET _u(0x0) -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO40_LEVEL_LOW_BITS _u(0x00000001) -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO40_LEVEL_LOW_MSB _u(0) -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO40_LEVEL_LOW_LSB _u(0) -#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO40_LEVEL_LOW_ACCESS "RO" -// ============================================================================= -#endif // _HARDWARE_REGS_IO_BANK0_H - diff --git a/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/io_qspi.h b/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/io_qspi.h deleted file mode 100644 index 6681052640..0000000000 --- a/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/io_qspi.h +++ /dev/null @@ -1,3663 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -// ============================================================================= -// Register block : IO_QSPI -// Version : 1 -// Bus type : apb -// ============================================================================= -#ifndef _HARDWARE_REGS_IO_QSPI_H -#define _HARDWARE_REGS_IO_QSPI_H -// ============================================================================= -// Register : IO_QSPI_USBPHY_DP_STATUS -#define IO_QSPI_USBPHY_DP_STATUS_OFFSET _u(0x00000000) -#define IO_QSPI_USBPHY_DP_STATUS_BITS _u(0x04022200) -#define IO_QSPI_USBPHY_DP_STATUS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_USBPHY_DP_STATUS_IRQTOPROC -// Description : interrupt to processors, after override is applied -#define IO_QSPI_USBPHY_DP_STATUS_IRQTOPROC_RESET _u(0x0) -#define IO_QSPI_USBPHY_DP_STATUS_IRQTOPROC_BITS _u(0x04000000) -#define IO_QSPI_USBPHY_DP_STATUS_IRQTOPROC_MSB _u(26) -#define IO_QSPI_USBPHY_DP_STATUS_IRQTOPROC_LSB _u(26) -#define IO_QSPI_USBPHY_DP_STATUS_IRQTOPROC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_USBPHY_DP_STATUS_INFROMPAD -// Description : input signal from pad, before filtering and override are -// applied -#define IO_QSPI_USBPHY_DP_STATUS_INFROMPAD_RESET _u(0x0) -#define IO_QSPI_USBPHY_DP_STATUS_INFROMPAD_BITS _u(0x00020000) -#define IO_QSPI_USBPHY_DP_STATUS_INFROMPAD_MSB _u(17) -#define IO_QSPI_USBPHY_DP_STATUS_INFROMPAD_LSB _u(17) -#define IO_QSPI_USBPHY_DP_STATUS_INFROMPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_USBPHY_DP_STATUS_OETOPAD -// Description : output enable to pad after register override is applied -#define IO_QSPI_USBPHY_DP_STATUS_OETOPAD_RESET _u(0x0) -#define IO_QSPI_USBPHY_DP_STATUS_OETOPAD_BITS _u(0x00002000) -#define IO_QSPI_USBPHY_DP_STATUS_OETOPAD_MSB _u(13) -#define IO_QSPI_USBPHY_DP_STATUS_OETOPAD_LSB _u(13) -#define IO_QSPI_USBPHY_DP_STATUS_OETOPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_USBPHY_DP_STATUS_OUTTOPAD -// Description : output signal to pad after register override is applied -#define IO_QSPI_USBPHY_DP_STATUS_OUTTOPAD_RESET _u(0x0) -#define IO_QSPI_USBPHY_DP_STATUS_OUTTOPAD_BITS _u(0x00000200) -#define IO_QSPI_USBPHY_DP_STATUS_OUTTOPAD_MSB _u(9) -#define IO_QSPI_USBPHY_DP_STATUS_OUTTOPAD_LSB _u(9) -#define IO_QSPI_USBPHY_DP_STATUS_OUTTOPAD_ACCESS "RO" -// ============================================================================= -// Register : IO_QSPI_USBPHY_DP_CTRL -#define IO_QSPI_USBPHY_DP_CTRL_OFFSET _u(0x00000004) -#define IO_QSPI_USBPHY_DP_CTRL_BITS _u(0x3003f01f) -#define IO_QSPI_USBPHY_DP_CTRL_RESET _u(0x0000001f) -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_USBPHY_DP_CTRL_IRQOVER -// 0x0 -> don't invert the interrupt -// 0x1 -> invert the interrupt -// 0x2 -> drive interrupt low -// 0x3 -> drive interrupt high -#define IO_QSPI_USBPHY_DP_CTRL_IRQOVER_RESET _u(0x0) -#define IO_QSPI_USBPHY_DP_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_QSPI_USBPHY_DP_CTRL_IRQOVER_MSB _u(29) -#define IO_QSPI_USBPHY_DP_CTRL_IRQOVER_LSB _u(28) -#define IO_QSPI_USBPHY_DP_CTRL_IRQOVER_ACCESS "RW" -#define IO_QSPI_USBPHY_DP_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) -#define IO_QSPI_USBPHY_DP_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_QSPI_USBPHY_DP_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_QSPI_USBPHY_DP_CTRL_IRQOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_USBPHY_DP_CTRL_INOVER -// 0x0 -> don't invert the peri input -// 0x1 -> invert the peri input -// 0x2 -> drive peri input low -// 0x3 -> drive peri input high -#define IO_QSPI_USBPHY_DP_CTRL_INOVER_RESET _u(0x0) -#define IO_QSPI_USBPHY_DP_CTRL_INOVER_BITS _u(0x00030000) -#define IO_QSPI_USBPHY_DP_CTRL_INOVER_MSB _u(17) -#define IO_QSPI_USBPHY_DP_CTRL_INOVER_LSB _u(16) -#define IO_QSPI_USBPHY_DP_CTRL_INOVER_ACCESS "RW" -#define IO_QSPI_USBPHY_DP_CTRL_INOVER_VALUE_NORMAL _u(0x0) -#define IO_QSPI_USBPHY_DP_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_QSPI_USBPHY_DP_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_QSPI_USBPHY_DP_CTRL_INOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_USBPHY_DP_CTRL_OEOVER -// 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel -// 0x2 -> disable output -// 0x3 -> enable output -#define IO_QSPI_USBPHY_DP_CTRL_OEOVER_RESET _u(0x0) -#define IO_QSPI_USBPHY_DP_CTRL_OEOVER_BITS _u(0x0000c000) -#define IO_QSPI_USBPHY_DP_CTRL_OEOVER_MSB _u(15) -#define IO_QSPI_USBPHY_DP_CTRL_OEOVER_LSB _u(14) -#define IO_QSPI_USBPHY_DP_CTRL_OEOVER_ACCESS "RW" -#define IO_QSPI_USBPHY_DP_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_QSPI_USBPHY_DP_CTRL_OEOVER_VALUE_INVERT _u(0x1) -#define IO_QSPI_USBPHY_DP_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_QSPI_USBPHY_DP_CTRL_OEOVER_VALUE_ENABLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_USBPHY_DP_CTRL_OUTOVER -// 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel -// 0x2 -> drive output low -// 0x3 -> drive output high -#define IO_QSPI_USBPHY_DP_CTRL_OUTOVER_RESET _u(0x0) -#define IO_QSPI_USBPHY_DP_CTRL_OUTOVER_BITS _u(0x00003000) -#define IO_QSPI_USBPHY_DP_CTRL_OUTOVER_MSB _u(13) -#define IO_QSPI_USBPHY_DP_CTRL_OUTOVER_LSB _u(12) -#define IO_QSPI_USBPHY_DP_CTRL_OUTOVER_ACCESS "RW" -#define IO_QSPI_USBPHY_DP_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) -#define IO_QSPI_USBPHY_DP_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_QSPI_USBPHY_DP_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_QSPI_USBPHY_DP_CTRL_OUTOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_USBPHY_DP_CTRL_FUNCSEL -// Description : 0-31 -> selects pin function according to the gpio table -// 31 == NULL -// 0x02 -> uart1_tx -// 0x03 -> i2c0_sda -// 0x05 -> siob_proc_56 -// 0x1f -> null -#define IO_QSPI_USBPHY_DP_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_QSPI_USBPHY_DP_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_QSPI_USBPHY_DP_CTRL_FUNCSEL_MSB _u(4) -#define IO_QSPI_USBPHY_DP_CTRL_FUNCSEL_LSB _u(0) -#define IO_QSPI_USBPHY_DP_CTRL_FUNCSEL_ACCESS "RW" -#define IO_QSPI_USBPHY_DP_CTRL_FUNCSEL_VALUE_UART1_TX _u(0x02) -#define IO_QSPI_USBPHY_DP_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03) -#define IO_QSPI_USBPHY_DP_CTRL_FUNCSEL_VALUE_SIOB_PROC_56 _u(0x05) -#define IO_QSPI_USBPHY_DP_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) -// ============================================================================= -// Register : IO_QSPI_USBPHY_DM_STATUS -#define IO_QSPI_USBPHY_DM_STATUS_OFFSET _u(0x00000008) -#define IO_QSPI_USBPHY_DM_STATUS_BITS _u(0x04022200) -#define IO_QSPI_USBPHY_DM_STATUS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_USBPHY_DM_STATUS_IRQTOPROC -// Description : interrupt to processors, after override is applied -#define IO_QSPI_USBPHY_DM_STATUS_IRQTOPROC_RESET _u(0x0) -#define IO_QSPI_USBPHY_DM_STATUS_IRQTOPROC_BITS _u(0x04000000) -#define IO_QSPI_USBPHY_DM_STATUS_IRQTOPROC_MSB _u(26) -#define IO_QSPI_USBPHY_DM_STATUS_IRQTOPROC_LSB _u(26) -#define IO_QSPI_USBPHY_DM_STATUS_IRQTOPROC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_USBPHY_DM_STATUS_INFROMPAD -// Description : input signal from pad, before filtering and override are -// applied -#define IO_QSPI_USBPHY_DM_STATUS_INFROMPAD_RESET _u(0x0) -#define IO_QSPI_USBPHY_DM_STATUS_INFROMPAD_BITS _u(0x00020000) -#define IO_QSPI_USBPHY_DM_STATUS_INFROMPAD_MSB _u(17) -#define IO_QSPI_USBPHY_DM_STATUS_INFROMPAD_LSB _u(17) -#define IO_QSPI_USBPHY_DM_STATUS_INFROMPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_USBPHY_DM_STATUS_OETOPAD -// Description : output enable to pad after register override is applied -#define IO_QSPI_USBPHY_DM_STATUS_OETOPAD_RESET _u(0x0) -#define IO_QSPI_USBPHY_DM_STATUS_OETOPAD_BITS _u(0x00002000) -#define IO_QSPI_USBPHY_DM_STATUS_OETOPAD_MSB _u(13) -#define IO_QSPI_USBPHY_DM_STATUS_OETOPAD_LSB _u(13) -#define IO_QSPI_USBPHY_DM_STATUS_OETOPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_USBPHY_DM_STATUS_OUTTOPAD -// Description : output signal to pad after register override is applied -#define IO_QSPI_USBPHY_DM_STATUS_OUTTOPAD_RESET _u(0x0) -#define IO_QSPI_USBPHY_DM_STATUS_OUTTOPAD_BITS _u(0x00000200) -#define IO_QSPI_USBPHY_DM_STATUS_OUTTOPAD_MSB _u(9) -#define IO_QSPI_USBPHY_DM_STATUS_OUTTOPAD_LSB _u(9) -#define IO_QSPI_USBPHY_DM_STATUS_OUTTOPAD_ACCESS "RO" -// ============================================================================= -// Register : IO_QSPI_USBPHY_DM_CTRL -#define IO_QSPI_USBPHY_DM_CTRL_OFFSET _u(0x0000000c) -#define IO_QSPI_USBPHY_DM_CTRL_BITS _u(0x3003f01f) -#define IO_QSPI_USBPHY_DM_CTRL_RESET _u(0x0000001f) -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_USBPHY_DM_CTRL_IRQOVER -// 0x0 -> don't invert the interrupt -// 0x1 -> invert the interrupt -// 0x2 -> drive interrupt low -// 0x3 -> drive interrupt high -#define IO_QSPI_USBPHY_DM_CTRL_IRQOVER_RESET _u(0x0) -#define IO_QSPI_USBPHY_DM_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_QSPI_USBPHY_DM_CTRL_IRQOVER_MSB _u(29) -#define IO_QSPI_USBPHY_DM_CTRL_IRQOVER_LSB _u(28) -#define IO_QSPI_USBPHY_DM_CTRL_IRQOVER_ACCESS "RW" -#define IO_QSPI_USBPHY_DM_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) -#define IO_QSPI_USBPHY_DM_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_QSPI_USBPHY_DM_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_QSPI_USBPHY_DM_CTRL_IRQOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_USBPHY_DM_CTRL_INOVER -// 0x0 -> don't invert the peri input -// 0x1 -> invert the peri input -// 0x2 -> drive peri input low -// 0x3 -> drive peri input high -#define IO_QSPI_USBPHY_DM_CTRL_INOVER_RESET _u(0x0) -#define IO_QSPI_USBPHY_DM_CTRL_INOVER_BITS _u(0x00030000) -#define IO_QSPI_USBPHY_DM_CTRL_INOVER_MSB _u(17) -#define IO_QSPI_USBPHY_DM_CTRL_INOVER_LSB _u(16) -#define IO_QSPI_USBPHY_DM_CTRL_INOVER_ACCESS "RW" -#define IO_QSPI_USBPHY_DM_CTRL_INOVER_VALUE_NORMAL _u(0x0) -#define IO_QSPI_USBPHY_DM_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_QSPI_USBPHY_DM_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_QSPI_USBPHY_DM_CTRL_INOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_USBPHY_DM_CTRL_OEOVER -// 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel -// 0x2 -> disable output -// 0x3 -> enable output -#define IO_QSPI_USBPHY_DM_CTRL_OEOVER_RESET _u(0x0) -#define IO_QSPI_USBPHY_DM_CTRL_OEOVER_BITS _u(0x0000c000) -#define IO_QSPI_USBPHY_DM_CTRL_OEOVER_MSB _u(15) -#define IO_QSPI_USBPHY_DM_CTRL_OEOVER_LSB _u(14) -#define IO_QSPI_USBPHY_DM_CTRL_OEOVER_ACCESS "RW" -#define IO_QSPI_USBPHY_DM_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_QSPI_USBPHY_DM_CTRL_OEOVER_VALUE_INVERT _u(0x1) -#define IO_QSPI_USBPHY_DM_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_QSPI_USBPHY_DM_CTRL_OEOVER_VALUE_ENABLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_USBPHY_DM_CTRL_OUTOVER -// 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel -// 0x2 -> drive output low -// 0x3 -> drive output high -#define IO_QSPI_USBPHY_DM_CTRL_OUTOVER_RESET _u(0x0) -#define IO_QSPI_USBPHY_DM_CTRL_OUTOVER_BITS _u(0x00003000) -#define IO_QSPI_USBPHY_DM_CTRL_OUTOVER_MSB _u(13) -#define IO_QSPI_USBPHY_DM_CTRL_OUTOVER_LSB _u(12) -#define IO_QSPI_USBPHY_DM_CTRL_OUTOVER_ACCESS "RW" -#define IO_QSPI_USBPHY_DM_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) -#define IO_QSPI_USBPHY_DM_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_QSPI_USBPHY_DM_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_QSPI_USBPHY_DM_CTRL_OUTOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_USBPHY_DM_CTRL_FUNCSEL -// Description : 0-31 -> selects pin function according to the gpio table -// 31 == NULL -// 0x02 -> uart1_rx -// 0x03 -> i2c0_scl -// 0x05 -> siob_proc_57 -// 0x1f -> null -#define IO_QSPI_USBPHY_DM_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_QSPI_USBPHY_DM_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_QSPI_USBPHY_DM_CTRL_FUNCSEL_MSB _u(4) -#define IO_QSPI_USBPHY_DM_CTRL_FUNCSEL_LSB _u(0) -#define IO_QSPI_USBPHY_DM_CTRL_FUNCSEL_ACCESS "RW" -#define IO_QSPI_USBPHY_DM_CTRL_FUNCSEL_VALUE_UART1_RX _u(0x02) -#define IO_QSPI_USBPHY_DM_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03) -#define IO_QSPI_USBPHY_DM_CTRL_FUNCSEL_VALUE_SIOB_PROC_57 _u(0x05) -#define IO_QSPI_USBPHY_DM_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) -// ============================================================================= -// Register : IO_QSPI_GPIO_QSPI_SCLK_STATUS -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OFFSET _u(0x00000010) -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_BITS _u(0x04022200) -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQTOPROC -// Description : interrupt to processors, after override is applied -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQTOPROC_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQTOPROC_BITS _u(0x04000000) -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQTOPROC_MSB _u(26) -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQTOPROC_LSB _u(26) -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQTOPROC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SCLK_STATUS_INFROMPAD -// Description : input signal from pad, before filtering and override are -// applied -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INFROMPAD_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INFROMPAD_BITS _u(0x00020000) -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INFROMPAD_MSB _u(17) -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INFROMPAD_LSB _u(17) -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INFROMPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SCLK_STATUS_OETOPAD -// Description : output enable to pad after register override is applied -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OETOPAD_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OETOPAD_BITS _u(0x00002000) -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OETOPAD_MSB _u(13) -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OETOPAD_LSB _u(13) -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OETOPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTTOPAD -// Description : output signal to pad after register override is applied -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTTOPAD_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTTOPAD_BITS _u(0x00000200) -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTTOPAD_MSB _u(9) -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTTOPAD_LSB _u(9) -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTTOPAD_ACCESS "RO" -// ============================================================================= -// Register : IO_QSPI_GPIO_QSPI_SCLK_CTRL -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OFFSET _u(0x00000014) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_BITS _u(0x3003f01f) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_RESET _u(0x0000001f) -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER -// 0x0 -> don't invert the interrupt -// 0x1 -> invert the interrupt -// 0x2 -> drive interrupt low -// 0x3 -> drive interrupt high -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_MSB _u(29) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_LSB _u(28) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER -// 0x0 -> don't invert the peri input -// 0x1 -> invert the peri input -// 0x2 -> drive peri input low -// 0x3 -> drive peri input high -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_BITS _u(0x00030000) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_MSB _u(17) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_LSB _u(16) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_VALUE_NORMAL _u(0x0) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER -// 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel -// 0x2 -> disable output -// 0x3 -> enable output -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_BITS _u(0x0000c000) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_MSB _u(15) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_LSB _u(14) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_VALUE_INVERT _u(0x1) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_VALUE_ENABLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER -// 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel -// 0x2 -> drive output low -// 0x3 -> drive output high -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_BITS _u(0x00003000) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_MSB _u(13) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_LSB _u(12) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL -// Description : 0-31 -> selects pin function according to the gpio table -// 31 == NULL -// 0x00 -> xip_sclk -// 0x02 -> uart1_cts -// 0x03 -> i2c1_sda -// 0x05 -> siob_proc_58 -// 0x0b -> uart1_tx -// 0x1f -> null -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_MSB _u(4) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_LSB _u(0) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_VALUE_XIP_SCLK _u(0x00) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_VALUE_UART1_CTS _u(0x02) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_VALUE_SIOB_PROC_58 _u(0x05) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_VALUE_UART1_TX _u(0x0b) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) -// ============================================================================= -// Register : IO_QSPI_GPIO_QSPI_SS_STATUS -#define IO_QSPI_GPIO_QSPI_SS_STATUS_OFFSET _u(0x00000018) -#define IO_QSPI_GPIO_QSPI_SS_STATUS_BITS _u(0x04022200) -#define IO_QSPI_GPIO_QSPI_SS_STATUS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SS_STATUS_IRQTOPROC -// Description : interrupt to processors, after override is applied -#define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQTOPROC_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQTOPROC_BITS _u(0x04000000) -#define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQTOPROC_MSB _u(26) -#define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQTOPROC_LSB _u(26) -#define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQTOPROC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SS_STATUS_INFROMPAD -// Description : input signal from pad, before filtering and override are -// applied -#define IO_QSPI_GPIO_QSPI_SS_STATUS_INFROMPAD_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SS_STATUS_INFROMPAD_BITS _u(0x00020000) -#define IO_QSPI_GPIO_QSPI_SS_STATUS_INFROMPAD_MSB _u(17) -#define IO_QSPI_GPIO_QSPI_SS_STATUS_INFROMPAD_LSB _u(17) -#define IO_QSPI_GPIO_QSPI_SS_STATUS_INFROMPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SS_STATUS_OETOPAD -// Description : output enable to pad after register override is applied -#define IO_QSPI_GPIO_QSPI_SS_STATUS_OETOPAD_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SS_STATUS_OETOPAD_BITS _u(0x00002000) -#define IO_QSPI_GPIO_QSPI_SS_STATUS_OETOPAD_MSB _u(13) -#define IO_QSPI_GPIO_QSPI_SS_STATUS_OETOPAD_LSB _u(13) -#define IO_QSPI_GPIO_QSPI_SS_STATUS_OETOPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SS_STATUS_OUTTOPAD -// Description : output signal to pad after register override is applied -#define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTTOPAD_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTTOPAD_BITS _u(0x00000200) -#define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTTOPAD_MSB _u(9) -#define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTTOPAD_LSB _u(9) -#define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTTOPAD_ACCESS "RO" -// ============================================================================= -// Register : IO_QSPI_GPIO_QSPI_SS_CTRL -#define IO_QSPI_GPIO_QSPI_SS_CTRL_OFFSET _u(0x0000001c) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_BITS _u(0x3003f01f) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_RESET _u(0x0000001f) -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER -// 0x0 -> don't invert the interrupt -// 0x1 -> invert the interrupt -// 0x2 -> drive interrupt low -// 0x3 -> drive interrupt high -#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_MSB _u(29) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_LSB _u(28) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER -// 0x0 -> don't invert the peri input -// 0x1 -> invert the peri input -// 0x2 -> drive peri input low -// 0x3 -> drive peri input high -#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_BITS _u(0x00030000) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_MSB _u(17) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_LSB _u(16) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_VALUE_NORMAL _u(0x0) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER -// 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel -// 0x2 -> disable output -// 0x3 -> enable output -#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_BITS _u(0x0000c000) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_MSB _u(15) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_LSB _u(14) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_VALUE_INVERT _u(0x1) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_VALUE_ENABLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER -// 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel -// 0x2 -> drive output low -// 0x3 -> drive output high -#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_BITS _u(0x00003000) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_MSB _u(13) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_LSB _u(12) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL -// Description : 0-31 -> selects pin function according to the gpio table -// 31 == NULL -// 0x00 -> xip_ss_n_0 -// 0x02 -> uart1_rts -// 0x03 -> i2c1_scl -// 0x05 -> siob_proc_59 -// 0x0b -> uart1_rx -// 0x1f -> null -#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_MSB _u(4) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_LSB _u(0) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_VALUE_XIP_SS_N_0 _u(0x00) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_VALUE_UART1_RTS _u(0x02) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_VALUE_SIOB_PROC_59 _u(0x05) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_VALUE_UART1_RX _u(0x0b) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) -// ============================================================================= -// Register : IO_QSPI_GPIO_QSPI_SD0_STATUS -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OFFSET _u(0x00000020) -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_BITS _u(0x04022200) -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQTOPROC -// Description : interrupt to processors, after override is applied -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQTOPROC_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQTOPROC_BITS _u(0x04000000) -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQTOPROC_MSB _u(26) -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQTOPROC_LSB _u(26) -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQTOPROC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SD0_STATUS_INFROMPAD -// Description : input signal from pad, before filtering and override are -// applied -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_INFROMPAD_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_INFROMPAD_BITS _u(0x00020000) -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_INFROMPAD_MSB _u(17) -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_INFROMPAD_LSB _u(17) -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_INFROMPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SD0_STATUS_OETOPAD -// Description : output enable to pad after register override is applied -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OETOPAD_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OETOPAD_BITS _u(0x00002000) -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OETOPAD_MSB _u(13) -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OETOPAD_LSB _u(13) -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OETOPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTTOPAD -// Description : output signal to pad after register override is applied -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTTOPAD_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTTOPAD_BITS _u(0x00000200) -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTTOPAD_MSB _u(9) -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTTOPAD_LSB _u(9) -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTTOPAD_ACCESS "RO" -// ============================================================================= -// Register : IO_QSPI_GPIO_QSPI_SD0_CTRL -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OFFSET _u(0x00000024) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_BITS _u(0x3003f01f) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_RESET _u(0x0000001f) -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER -// 0x0 -> don't invert the interrupt -// 0x1 -> invert the interrupt -// 0x2 -> drive interrupt low -// 0x3 -> drive interrupt high -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_MSB _u(29) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_LSB _u(28) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER -// 0x0 -> don't invert the peri input -// 0x1 -> invert the peri input -// 0x2 -> drive peri input low -// 0x3 -> drive peri input high -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_BITS _u(0x00030000) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_MSB _u(17) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_LSB _u(16) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_VALUE_NORMAL _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER -// 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel -// 0x2 -> disable output -// 0x3 -> enable output -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_BITS _u(0x0000c000) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_MSB _u(15) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_LSB _u(14) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_VALUE_INVERT _u(0x1) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_VALUE_ENABLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER -// 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel -// 0x2 -> drive output low -// 0x3 -> drive output high -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_BITS _u(0x00003000) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_MSB _u(13) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_LSB _u(12) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL -// Description : 0-31 -> selects pin function according to the gpio table -// 31 == NULL -// 0x00 -> xip_sd0 -// 0x02 -> uart0_tx -// 0x03 -> i2c0_sda -// 0x05 -> siob_proc_60 -// 0x1f -> null -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_MSB _u(4) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_LSB _u(0) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_VALUE_XIP_SD0 _u(0x00) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_VALUE_UART0_TX _u(0x02) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_VALUE_SIOB_PROC_60 _u(0x05) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) -// ============================================================================= -// Register : IO_QSPI_GPIO_QSPI_SD1_STATUS -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OFFSET _u(0x00000028) -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_BITS _u(0x04022200) -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQTOPROC -// Description : interrupt to processors, after override is applied -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQTOPROC_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQTOPROC_BITS _u(0x04000000) -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQTOPROC_MSB _u(26) -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQTOPROC_LSB _u(26) -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQTOPROC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SD1_STATUS_INFROMPAD -// Description : input signal from pad, before filtering and override are -// applied -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_INFROMPAD_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_INFROMPAD_BITS _u(0x00020000) -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_INFROMPAD_MSB _u(17) -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_INFROMPAD_LSB _u(17) -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_INFROMPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SD1_STATUS_OETOPAD -// Description : output enable to pad after register override is applied -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OETOPAD_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OETOPAD_BITS _u(0x00002000) -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OETOPAD_MSB _u(13) -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OETOPAD_LSB _u(13) -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OETOPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTTOPAD -// Description : output signal to pad after register override is applied -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTTOPAD_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTTOPAD_BITS _u(0x00000200) -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTTOPAD_MSB _u(9) -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTTOPAD_LSB _u(9) -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTTOPAD_ACCESS "RO" -// ============================================================================= -// Register : IO_QSPI_GPIO_QSPI_SD1_CTRL -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OFFSET _u(0x0000002c) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_BITS _u(0x3003f01f) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_RESET _u(0x0000001f) -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER -// 0x0 -> don't invert the interrupt -// 0x1 -> invert the interrupt -// 0x2 -> drive interrupt low -// 0x3 -> drive interrupt high -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_MSB _u(29) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_LSB _u(28) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER -// 0x0 -> don't invert the peri input -// 0x1 -> invert the peri input -// 0x2 -> drive peri input low -// 0x3 -> drive peri input high -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_BITS _u(0x00030000) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_MSB _u(17) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_LSB _u(16) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_VALUE_NORMAL _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER -// 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel -// 0x2 -> disable output -// 0x3 -> enable output -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_BITS _u(0x0000c000) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_MSB _u(15) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_LSB _u(14) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_VALUE_INVERT _u(0x1) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_VALUE_ENABLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER -// 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel -// 0x2 -> drive output low -// 0x3 -> drive output high -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_BITS _u(0x00003000) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_MSB _u(13) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_LSB _u(12) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL -// Description : 0-31 -> selects pin function according to the gpio table -// 31 == NULL -// 0x00 -> xip_sd1 -// 0x02 -> uart0_rx -// 0x03 -> i2c0_scl -// 0x05 -> siob_proc_61 -// 0x1f -> null -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_MSB _u(4) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_LSB _u(0) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_VALUE_XIP_SD1 _u(0x00) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_VALUE_UART0_RX _u(0x02) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_VALUE_SIOB_PROC_61 _u(0x05) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) -// ============================================================================= -// Register : IO_QSPI_GPIO_QSPI_SD2_STATUS -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OFFSET _u(0x00000030) -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_BITS _u(0x04022200) -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQTOPROC -// Description : interrupt to processors, after override is applied -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQTOPROC_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQTOPROC_BITS _u(0x04000000) -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQTOPROC_MSB _u(26) -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQTOPROC_LSB _u(26) -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQTOPROC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SD2_STATUS_INFROMPAD -// Description : input signal from pad, before filtering and override are -// applied -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_INFROMPAD_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_INFROMPAD_BITS _u(0x00020000) -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_INFROMPAD_MSB _u(17) -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_INFROMPAD_LSB _u(17) -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_INFROMPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SD2_STATUS_OETOPAD -// Description : output enable to pad after register override is applied -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OETOPAD_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OETOPAD_BITS _u(0x00002000) -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OETOPAD_MSB _u(13) -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OETOPAD_LSB _u(13) -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OETOPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTTOPAD -// Description : output signal to pad after register override is applied -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTTOPAD_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTTOPAD_BITS _u(0x00000200) -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTTOPAD_MSB _u(9) -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTTOPAD_LSB _u(9) -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTTOPAD_ACCESS "RO" -// ============================================================================= -// Register : IO_QSPI_GPIO_QSPI_SD2_CTRL -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OFFSET _u(0x00000034) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_BITS _u(0x3003f01f) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_RESET _u(0x0000001f) -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER -// 0x0 -> don't invert the interrupt -// 0x1 -> invert the interrupt -// 0x2 -> drive interrupt low -// 0x3 -> drive interrupt high -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_MSB _u(29) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_LSB _u(28) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER -// 0x0 -> don't invert the peri input -// 0x1 -> invert the peri input -// 0x2 -> drive peri input low -// 0x3 -> drive peri input high -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_BITS _u(0x00030000) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_MSB _u(17) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_LSB _u(16) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_VALUE_NORMAL _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER -// 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel -// 0x2 -> disable output -// 0x3 -> enable output -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_BITS _u(0x0000c000) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_MSB _u(15) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_LSB _u(14) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_VALUE_INVERT _u(0x1) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_VALUE_ENABLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER -// 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel -// 0x2 -> drive output low -// 0x3 -> drive output high -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_BITS _u(0x00003000) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_MSB _u(13) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_LSB _u(12) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL -// Description : 0-31 -> selects pin function according to the gpio table -// 31 == NULL -// 0x00 -> xip_sd2 -// 0x02 -> uart0_cts -// 0x03 -> i2c1_sda -// 0x05 -> siob_proc_62 -// 0x0b -> uart0_tx -// 0x1f -> null -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_MSB _u(4) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_LSB _u(0) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_VALUE_XIP_SD2 _u(0x00) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_VALUE_UART0_CTS _u(0x02) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_VALUE_SIOB_PROC_62 _u(0x05) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_VALUE_UART0_TX _u(0x0b) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) -// ============================================================================= -// Register : IO_QSPI_GPIO_QSPI_SD3_STATUS -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OFFSET _u(0x00000038) -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_BITS _u(0x04022200) -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQTOPROC -// Description : interrupt to processors, after override is applied -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQTOPROC_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQTOPROC_BITS _u(0x04000000) -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQTOPROC_MSB _u(26) -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQTOPROC_LSB _u(26) -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQTOPROC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SD3_STATUS_INFROMPAD -// Description : input signal from pad, before filtering and override are -// applied -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_INFROMPAD_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_INFROMPAD_BITS _u(0x00020000) -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_INFROMPAD_MSB _u(17) -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_INFROMPAD_LSB _u(17) -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_INFROMPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SD3_STATUS_OETOPAD -// Description : output enable to pad after register override is applied -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OETOPAD_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OETOPAD_BITS _u(0x00002000) -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OETOPAD_MSB _u(13) -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OETOPAD_LSB _u(13) -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OETOPAD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTTOPAD -// Description : output signal to pad after register override is applied -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTTOPAD_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTTOPAD_BITS _u(0x00000200) -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTTOPAD_MSB _u(9) -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTTOPAD_LSB _u(9) -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTTOPAD_ACCESS "RO" -// ============================================================================= -// Register : IO_QSPI_GPIO_QSPI_SD3_CTRL -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OFFSET _u(0x0000003c) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_BITS _u(0x3003f01f) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_RESET _u(0x0000001f) -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER -// 0x0 -> don't invert the interrupt -// 0x1 -> invert the interrupt -// 0x2 -> drive interrupt low -// 0x3 -> drive interrupt high -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_MSB _u(29) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_LSB _u(28) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER -// 0x0 -> don't invert the peri input -// 0x1 -> invert the peri input -// 0x2 -> drive peri input low -// 0x3 -> drive peri input high -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_BITS _u(0x00030000) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_MSB _u(17) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_LSB _u(16) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_VALUE_NORMAL _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER -// 0x0 -> drive output enable from peripheral signal selected by funcsel -// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel -// 0x2 -> disable output -// 0x3 -> enable output -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_BITS _u(0x0000c000) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_MSB _u(15) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_LSB _u(14) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_VALUE_INVERT _u(0x1) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_VALUE_ENABLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER -// 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected by funcsel -// 0x2 -> drive output low -// 0x3 -> drive output high -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_BITS _u(0x00003000) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_MSB _u(13) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_LSB _u(12) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_VALUE_HIGH _u(0x3) -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL -// Description : 0-31 -> selects pin function according to the gpio table -// 31 == NULL -// 0x00 -> xip_sd3 -// 0x02 -> uart0_rts -// 0x03 -> i2c1_scl -// 0x05 -> siob_proc_63 -// 0x0b -> uart0_rx -// 0x1f -> null -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_MSB _u(4) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_LSB _u(0) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_VALUE_XIP_SD3 _u(0x00) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_VALUE_UART0_RTS _u(0x02) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_VALUE_SIOB_PROC_63 _u(0x05) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_VALUE_UART0_RX _u(0x0b) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) -// ============================================================================= -// Register : IO_QSPI_IRQSUMMARY_PROC0_SECURE -#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_OFFSET _u(0x00000200) -#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_BITS _u(0x000000ff) -#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SD3 -#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SD3_RESET _u(0x0) -#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SD3_BITS _u(0x00000080) -#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SD3_MSB _u(7) -#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SD3_LSB _u(7) -#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SD3_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SD2 -#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SD2_RESET _u(0x0) -#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SD2_BITS _u(0x00000040) -#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SD2_MSB _u(6) -#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SD2_LSB _u(6) -#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SD2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SD1 -#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SD1_RESET _u(0x0) -#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SD1_BITS _u(0x00000020) -#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SD1_MSB _u(5) -#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SD1_LSB _u(5) -#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SD1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SD0 -#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SD0_RESET _u(0x0) -#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SD0_BITS _u(0x00000010) -#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SD0_MSB _u(4) -#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SD0_LSB _u(4) -#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SD0_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SS -#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SS_RESET _u(0x0) -#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SS_BITS _u(0x00000008) -#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SS_MSB _u(3) -#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SS_LSB _u(3) -#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SS_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SCLK -#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SCLK_RESET _u(0x0) -#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SCLK_BITS _u(0x00000004) -#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SCLK_MSB _u(2) -#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SCLK_LSB _u(2) -#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SCLK_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_IRQSUMMARY_PROC0_SECURE_USBPHY_DM -#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_USBPHY_DM_RESET _u(0x0) -#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_USBPHY_DM_BITS _u(0x00000002) -#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_USBPHY_DM_MSB _u(1) -#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_USBPHY_DM_LSB _u(1) -#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_USBPHY_DM_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_IRQSUMMARY_PROC0_SECURE_USBPHY_DP -#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_USBPHY_DP_RESET _u(0x0) -#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_USBPHY_DP_BITS _u(0x00000001) -#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_USBPHY_DP_MSB _u(0) -#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_USBPHY_DP_LSB _u(0) -#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_USBPHY_DP_ACCESS "RO" -// ============================================================================= -// Register : IO_QSPI_IRQSUMMARY_PROC0_NONSECURE -#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_OFFSET _u(0x00000204) -#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_BITS _u(0x000000ff) -#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SD3 -#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SD3_RESET _u(0x0) -#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SD3_BITS _u(0x00000080) -#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SD3_MSB _u(7) -#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SD3_LSB _u(7) -#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SD3_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SD2 -#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SD2_RESET _u(0x0) -#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SD2_BITS _u(0x00000040) -#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SD2_MSB _u(6) -#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SD2_LSB _u(6) -#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SD2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SD1 -#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SD1_RESET _u(0x0) -#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SD1_BITS _u(0x00000020) -#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SD1_MSB _u(5) -#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SD1_LSB _u(5) -#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SD1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SD0 -#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SD0_RESET _u(0x0) -#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SD0_BITS _u(0x00000010) -#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SD0_MSB _u(4) -#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SD0_LSB _u(4) -#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SD0_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SS -#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SS_RESET _u(0x0) -#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SS_BITS _u(0x00000008) -#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SS_MSB _u(3) -#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SS_LSB _u(3) -#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SS_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SCLK -#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SCLK_RESET _u(0x0) -#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SCLK_BITS _u(0x00000004) -#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SCLK_MSB _u(2) -#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SCLK_LSB _u(2) -#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SCLK_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_USBPHY_DM -#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_USBPHY_DM_RESET _u(0x0) -#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_USBPHY_DM_BITS _u(0x00000002) -#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_USBPHY_DM_MSB _u(1) -#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_USBPHY_DM_LSB _u(1) -#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_USBPHY_DM_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_USBPHY_DP -#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_USBPHY_DP_RESET _u(0x0) -#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_USBPHY_DP_BITS _u(0x00000001) -#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_USBPHY_DP_MSB _u(0) -#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_USBPHY_DP_LSB _u(0) -#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_USBPHY_DP_ACCESS "RO" -// ============================================================================= -// Register : IO_QSPI_IRQSUMMARY_PROC1_SECURE -#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_OFFSET _u(0x00000208) -#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_BITS _u(0x000000ff) -#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SD3 -#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SD3_RESET _u(0x0) -#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SD3_BITS _u(0x00000080) -#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SD3_MSB _u(7) -#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SD3_LSB _u(7) -#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SD3_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SD2 -#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SD2_RESET _u(0x0) -#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SD2_BITS _u(0x00000040) -#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SD2_MSB _u(6) -#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SD2_LSB _u(6) -#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SD2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SD1 -#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SD1_RESET _u(0x0) -#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SD1_BITS _u(0x00000020) -#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SD1_MSB _u(5) -#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SD1_LSB _u(5) -#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SD1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SD0 -#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SD0_RESET _u(0x0) -#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SD0_BITS _u(0x00000010) -#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SD0_MSB _u(4) -#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SD0_LSB _u(4) -#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SD0_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SS -#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SS_RESET _u(0x0) -#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SS_BITS _u(0x00000008) -#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SS_MSB _u(3) -#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SS_LSB _u(3) -#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SS_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SCLK -#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SCLK_RESET _u(0x0) -#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SCLK_BITS _u(0x00000004) -#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SCLK_MSB _u(2) -#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SCLK_LSB _u(2) -#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SCLK_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_IRQSUMMARY_PROC1_SECURE_USBPHY_DM -#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_USBPHY_DM_RESET _u(0x0) -#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_USBPHY_DM_BITS _u(0x00000002) -#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_USBPHY_DM_MSB _u(1) -#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_USBPHY_DM_LSB _u(1) -#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_USBPHY_DM_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_IRQSUMMARY_PROC1_SECURE_USBPHY_DP -#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_USBPHY_DP_RESET _u(0x0) -#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_USBPHY_DP_BITS _u(0x00000001) -#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_USBPHY_DP_MSB _u(0) -#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_USBPHY_DP_LSB _u(0) -#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_USBPHY_DP_ACCESS "RO" -// ============================================================================= -// Register : IO_QSPI_IRQSUMMARY_PROC1_NONSECURE -#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_OFFSET _u(0x0000020c) -#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_BITS _u(0x000000ff) -#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SD3 -#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SD3_RESET _u(0x0) -#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SD3_BITS _u(0x00000080) -#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SD3_MSB _u(7) -#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SD3_LSB _u(7) -#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SD3_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SD2 -#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SD2_RESET _u(0x0) -#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SD2_BITS _u(0x00000040) -#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SD2_MSB _u(6) -#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SD2_LSB _u(6) -#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SD2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SD1 -#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SD1_RESET _u(0x0) -#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SD1_BITS _u(0x00000020) -#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SD1_MSB _u(5) -#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SD1_LSB _u(5) -#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SD1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SD0 -#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SD0_RESET _u(0x0) -#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SD0_BITS _u(0x00000010) -#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SD0_MSB _u(4) -#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SD0_LSB _u(4) -#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SD0_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SS -#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SS_RESET _u(0x0) -#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SS_BITS _u(0x00000008) -#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SS_MSB _u(3) -#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SS_LSB _u(3) -#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SS_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SCLK -#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SCLK_RESET _u(0x0) -#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SCLK_BITS _u(0x00000004) -#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SCLK_MSB _u(2) -#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SCLK_LSB _u(2) -#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SCLK_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_USBPHY_DM -#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_USBPHY_DM_RESET _u(0x0) -#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_USBPHY_DM_BITS _u(0x00000002) -#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_USBPHY_DM_MSB _u(1) -#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_USBPHY_DM_LSB _u(1) -#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_USBPHY_DM_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_USBPHY_DP -#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_USBPHY_DP_RESET _u(0x0) -#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_USBPHY_DP_BITS _u(0x00000001) -#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_USBPHY_DP_MSB _u(0) -#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_USBPHY_DP_LSB _u(0) -#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_USBPHY_DP_ACCESS "RO" -// ============================================================================= -// Register : IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE -#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_OFFSET _u(0x00000210) -#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_BITS _u(0x000000ff) -#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SD3 -#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SD3_RESET _u(0x0) -#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SD3_BITS _u(0x00000080) -#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SD3_MSB _u(7) -#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SD3_LSB _u(7) -#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SD3_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SD2 -#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SD2_RESET _u(0x0) -#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SD2_BITS _u(0x00000040) -#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SD2_MSB _u(6) -#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SD2_LSB _u(6) -#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SD2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SD1 -#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SD1_RESET _u(0x0) -#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SD1_BITS _u(0x00000020) -#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SD1_MSB _u(5) -#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SD1_LSB _u(5) -#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SD1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SD0 -#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SD0_RESET _u(0x0) -#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SD0_BITS _u(0x00000010) -#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SD0_MSB _u(4) -#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SD0_LSB _u(4) -#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SD0_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SS -#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SS_RESET _u(0x0) -#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SS_BITS _u(0x00000008) -#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SS_MSB _u(3) -#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SS_LSB _u(3) -#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SS_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SCLK -#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SCLK_RESET _u(0x0) -#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SCLK_BITS _u(0x00000004) -#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SCLK_MSB _u(2) -#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SCLK_LSB _u(2) -#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SCLK_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_USBPHY_DM -#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_USBPHY_DM_RESET _u(0x0) -#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_USBPHY_DM_BITS _u(0x00000002) -#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_USBPHY_DM_MSB _u(1) -#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_USBPHY_DM_LSB _u(1) -#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_USBPHY_DM_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_USBPHY_DP -#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_USBPHY_DP_RESET _u(0x0) -#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_USBPHY_DP_BITS _u(0x00000001) -#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_USBPHY_DP_MSB _u(0) -#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_USBPHY_DP_LSB _u(0) -#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_USBPHY_DP_ACCESS "RO" -// ============================================================================= -// Register : IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE -#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_OFFSET _u(0x00000214) -#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_BITS _u(0x000000ff) -#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SD3 -#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SD3_RESET _u(0x0) -#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SD3_BITS _u(0x00000080) -#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SD3_MSB _u(7) -#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SD3_LSB _u(7) -#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SD3_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SD2 -#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SD2_RESET _u(0x0) -#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SD2_BITS _u(0x00000040) -#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SD2_MSB _u(6) -#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SD2_LSB _u(6) -#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SD2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SD1 -#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SD1_RESET _u(0x0) -#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SD1_BITS _u(0x00000020) -#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SD1_MSB _u(5) -#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SD1_LSB _u(5) -#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SD1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SD0 -#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SD0_RESET _u(0x0) -#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SD0_BITS _u(0x00000010) -#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SD0_MSB _u(4) -#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SD0_LSB _u(4) -#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SD0_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SS -#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SS_RESET _u(0x0) -#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SS_BITS _u(0x00000008) -#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SS_MSB _u(3) -#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SS_LSB _u(3) -#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SS_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SCLK -#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SCLK_RESET _u(0x0) -#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SCLK_BITS _u(0x00000004) -#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SCLK_MSB _u(2) -#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SCLK_LSB _u(2) -#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SCLK_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_USBPHY_DM -#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_USBPHY_DM_RESET _u(0x0) -#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_USBPHY_DM_BITS _u(0x00000002) -#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_USBPHY_DM_MSB _u(1) -#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_USBPHY_DM_LSB _u(1) -#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_USBPHY_DM_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_USBPHY_DP -#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_USBPHY_DP_RESET _u(0x0) -#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_USBPHY_DP_BITS _u(0x00000001) -#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_USBPHY_DP_MSB _u(0) -#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_USBPHY_DP_LSB _u(0) -#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_USBPHY_DP_ACCESS "RO" -// ============================================================================= -// Register : IO_QSPI_INTR -// Description : Raw Interrupts -#define IO_QSPI_INTR_OFFSET _u(0x00000218) -#define IO_QSPI_INTR_BITS _u(0xffffffff) -#define IO_QSPI_INTR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_HIGH -#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_HIGH_BITS _u(0x80000000) -#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_HIGH_MSB _u(31) -#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_HIGH_LSB _u(31) -#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_LOW -#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_LOW_BITS _u(0x40000000) -#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_LOW_MSB _u(30) -#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_LOW_LSB _u(30) -#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_HIGH -#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_HIGH_BITS _u(0x20000000) -#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_HIGH_MSB _u(29) -#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_HIGH_LSB _u(29) -#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_LOW -#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_LOW_BITS _u(0x10000000) -#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_LOW_MSB _u(28) -#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_LOW_LSB _u(28) -#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_HIGH -#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_HIGH_BITS _u(0x08000000) -#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_HIGH_MSB _u(27) -#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_HIGH_LSB _u(27) -#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_LOW -#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_LOW_BITS _u(0x04000000) -#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_LOW_MSB _u(26) -#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_LOW_LSB _u(26) -#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_HIGH -#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_HIGH_BITS _u(0x02000000) -#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_HIGH_MSB _u(25) -#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_HIGH_LSB _u(25) -#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_LOW -#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_LOW_BITS _u(0x01000000) -#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_LOW_MSB _u(24) -#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_LOW_LSB _u(24) -#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_HIGH -#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_HIGH_BITS _u(0x00800000) -#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_HIGH_MSB _u(23) -#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_HIGH_LSB _u(23) -#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_LOW -#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_LOW_BITS _u(0x00400000) -#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_LOW_MSB _u(22) -#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_LOW_LSB _u(22) -#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_HIGH -#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_HIGH_BITS _u(0x00200000) -#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_HIGH_MSB _u(21) -#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_HIGH_LSB _u(21) -#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_LOW -#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_LOW_BITS _u(0x00100000) -#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_LOW_MSB _u(20) -#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_LOW_LSB _u(20) -#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_HIGH -#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_HIGH_BITS _u(0x00080000) -#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_HIGH_MSB _u(19) -#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_HIGH_LSB _u(19) -#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_LOW -#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_LOW_BITS _u(0x00040000) -#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_LOW_MSB _u(18) -#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_LOW_LSB _u(18) -#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_HIGH -#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_HIGH_BITS _u(0x00020000) -#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_HIGH_MSB _u(17) -#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_HIGH_LSB _u(17) -#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_LOW -#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_LOW_BITS _u(0x00010000) -#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_LOW_MSB _u(16) -#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_LOW_LSB _u(16) -#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_HIGH -#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_HIGH_BITS _u(0x00008000) -#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_HIGH_MSB _u(15) -#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_HIGH_LSB _u(15) -#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_LOW -#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_LOW_BITS _u(0x00004000) -#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_LOW_MSB _u(14) -#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_LOW_LSB _u(14) -#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_LOW_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_HIGH -#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_HIGH_BITS _u(0x00002000) -#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_HIGH_MSB _u(13) -#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_HIGH_LSB _u(13) -#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_LOW -#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_LOW_BITS _u(0x00001000) -#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_LOW_MSB _u(12) -#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_LOW_LSB _u(12) -#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_HIGH -#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_HIGH_BITS _u(0x00000800) -#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_HIGH_MSB _u(11) -#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_HIGH_LSB _u(11) -#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_LOW -#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_LOW_BITS _u(0x00000400) -#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_LOW_MSB _u(10) -#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_LOW_LSB _u(10) -#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_HIGH -#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS _u(0x00000200) -#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB _u(9) -#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB _u(9) -#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_LOW -#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_LOW_BITS _u(0x00000100) -#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_LOW_MSB _u(8) -#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_LOW_LSB _u(8) -#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_INTR_USBPHY_DM_EDGE_HIGH -#define IO_QSPI_INTR_USBPHY_DM_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_INTR_USBPHY_DM_EDGE_HIGH_BITS _u(0x00000080) -#define IO_QSPI_INTR_USBPHY_DM_EDGE_HIGH_MSB _u(7) -#define IO_QSPI_INTR_USBPHY_DM_EDGE_HIGH_LSB _u(7) -#define IO_QSPI_INTR_USBPHY_DM_EDGE_HIGH_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_INTR_USBPHY_DM_EDGE_LOW -#define IO_QSPI_INTR_USBPHY_DM_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_INTR_USBPHY_DM_EDGE_LOW_BITS _u(0x00000040) -#define IO_QSPI_INTR_USBPHY_DM_EDGE_LOW_MSB _u(6) -#define IO_QSPI_INTR_USBPHY_DM_EDGE_LOW_LSB _u(6) -#define IO_QSPI_INTR_USBPHY_DM_EDGE_LOW_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_INTR_USBPHY_DM_LEVEL_HIGH -#define IO_QSPI_INTR_USBPHY_DM_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_INTR_USBPHY_DM_LEVEL_HIGH_BITS _u(0x00000020) -#define IO_QSPI_INTR_USBPHY_DM_LEVEL_HIGH_MSB _u(5) -#define IO_QSPI_INTR_USBPHY_DM_LEVEL_HIGH_LSB _u(5) -#define IO_QSPI_INTR_USBPHY_DM_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_INTR_USBPHY_DM_LEVEL_LOW -#define IO_QSPI_INTR_USBPHY_DM_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_INTR_USBPHY_DM_LEVEL_LOW_BITS _u(0x00000010) -#define IO_QSPI_INTR_USBPHY_DM_LEVEL_LOW_MSB _u(4) -#define IO_QSPI_INTR_USBPHY_DM_LEVEL_LOW_LSB _u(4) -#define IO_QSPI_INTR_USBPHY_DM_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_INTR_USBPHY_DP_EDGE_HIGH -#define IO_QSPI_INTR_USBPHY_DP_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_INTR_USBPHY_DP_EDGE_HIGH_BITS _u(0x00000008) -#define IO_QSPI_INTR_USBPHY_DP_EDGE_HIGH_MSB _u(3) -#define IO_QSPI_INTR_USBPHY_DP_EDGE_HIGH_LSB _u(3) -#define IO_QSPI_INTR_USBPHY_DP_EDGE_HIGH_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_INTR_USBPHY_DP_EDGE_LOW -#define IO_QSPI_INTR_USBPHY_DP_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_INTR_USBPHY_DP_EDGE_LOW_BITS _u(0x00000004) -#define IO_QSPI_INTR_USBPHY_DP_EDGE_LOW_MSB _u(2) -#define IO_QSPI_INTR_USBPHY_DP_EDGE_LOW_LSB _u(2) -#define IO_QSPI_INTR_USBPHY_DP_EDGE_LOW_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_INTR_USBPHY_DP_LEVEL_HIGH -#define IO_QSPI_INTR_USBPHY_DP_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_INTR_USBPHY_DP_LEVEL_HIGH_BITS _u(0x00000002) -#define IO_QSPI_INTR_USBPHY_DP_LEVEL_HIGH_MSB _u(1) -#define IO_QSPI_INTR_USBPHY_DP_LEVEL_HIGH_LSB _u(1) -#define IO_QSPI_INTR_USBPHY_DP_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_INTR_USBPHY_DP_LEVEL_LOW -#define IO_QSPI_INTR_USBPHY_DP_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_INTR_USBPHY_DP_LEVEL_LOW_BITS _u(0x00000001) -#define IO_QSPI_INTR_USBPHY_DP_LEVEL_LOW_MSB _u(0) -#define IO_QSPI_INTR_USBPHY_DP_LEVEL_LOW_LSB _u(0) -#define IO_QSPI_INTR_USBPHY_DP_LEVEL_LOW_ACCESS "RO" -// ============================================================================= -// Register : IO_QSPI_PROC0_INTE -// Description : Interrupt Enable for proc0 -#define IO_QSPI_PROC0_INTE_OFFSET _u(0x0000021c) -#define IO_QSPI_PROC0_INTE_BITS _u(0xffffffff) -#define IO_QSPI_PROC0_INTE_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_HIGH -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_HIGH_BITS _u(0x80000000) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_HIGH_MSB _u(31) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_HIGH_LSB _u(31) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_LOW -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_LOW_BITS _u(0x40000000) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_LOW_MSB _u(30) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_LOW_LSB _u(30) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_HIGH -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_BITS _u(0x20000000) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_MSB _u(29) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_LSB _u(29) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_LOW -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_LOW_BITS _u(0x10000000) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_LOW_MSB _u(28) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_LOW_LSB _u(28) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_HIGH -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_HIGH_BITS _u(0x08000000) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_HIGH_MSB _u(27) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_HIGH_LSB _u(27) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_LOW -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_LOW_BITS _u(0x04000000) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_LOW_MSB _u(26) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_LOW_LSB _u(26) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_HIGH -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_BITS _u(0x02000000) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_MSB _u(25) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_LSB _u(25) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_LOW -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_LOW_BITS _u(0x01000000) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_LOW_MSB _u(24) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_LOW_LSB _u(24) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_HIGH -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_HIGH_BITS _u(0x00800000) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_HIGH_MSB _u(23) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_HIGH_LSB _u(23) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_LOW -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_LOW_BITS _u(0x00400000) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_LOW_MSB _u(22) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_LOW_LSB _u(22) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_HIGH -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_BITS _u(0x00200000) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_MSB _u(21) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_LSB _u(21) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_LOW -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_LOW_BITS _u(0x00100000) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_LOW_MSB _u(20) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_LOW_LSB _u(20) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_HIGH -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_HIGH_BITS _u(0x00080000) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_HIGH_MSB _u(19) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_HIGH_LSB _u(19) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_LOW -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_LOW_BITS _u(0x00040000) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_LOW_MSB _u(18) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_LOW_LSB _u(18) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_HIGH -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_BITS _u(0x00020000) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_MSB _u(17) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_LSB _u(17) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_LOW -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_LOW_BITS _u(0x00010000) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_LOW_MSB _u(16) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_LOW_LSB _u(16) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_HIGH -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_HIGH_BITS _u(0x00008000) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_HIGH_MSB _u(15) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_HIGH_LSB _u(15) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_LOW -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_LOW_BITS _u(0x00004000) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_LOW_MSB _u(14) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_LOW_LSB _u(14) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_HIGH -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_HIGH_BITS _u(0x00002000) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_HIGH_MSB _u(13) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_HIGH_LSB _u(13) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_LOW -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_LOW_BITS _u(0x00001000) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_LOW_MSB _u(12) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_LOW_LSB _u(12) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_HIGH -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_BITS _u(0x00000800) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_MSB _u(11) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_LSB _u(11) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_LOW -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_LOW_BITS _u(0x00000400) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_LOW_MSB _u(10) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_LOW_LSB _u(10) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS _u(0x00000200) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB _u(9) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB _u(9) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_LOW -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_BITS _u(0x00000100) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_MSB _u(8) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_LSB _u(8) -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTE_USBPHY_DM_EDGE_HIGH -#define IO_QSPI_PROC0_INTE_USBPHY_DM_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC0_INTE_USBPHY_DM_EDGE_HIGH_BITS _u(0x00000080) -#define IO_QSPI_PROC0_INTE_USBPHY_DM_EDGE_HIGH_MSB _u(7) -#define IO_QSPI_PROC0_INTE_USBPHY_DM_EDGE_HIGH_LSB _u(7) -#define IO_QSPI_PROC0_INTE_USBPHY_DM_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTE_USBPHY_DM_EDGE_LOW -#define IO_QSPI_PROC0_INTE_USBPHY_DM_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_PROC0_INTE_USBPHY_DM_EDGE_LOW_BITS _u(0x00000040) -#define IO_QSPI_PROC0_INTE_USBPHY_DM_EDGE_LOW_MSB _u(6) -#define IO_QSPI_PROC0_INTE_USBPHY_DM_EDGE_LOW_LSB _u(6) -#define IO_QSPI_PROC0_INTE_USBPHY_DM_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTE_USBPHY_DM_LEVEL_HIGH -#define IO_QSPI_PROC0_INTE_USBPHY_DM_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC0_INTE_USBPHY_DM_LEVEL_HIGH_BITS _u(0x00000020) -#define IO_QSPI_PROC0_INTE_USBPHY_DM_LEVEL_HIGH_MSB _u(5) -#define IO_QSPI_PROC0_INTE_USBPHY_DM_LEVEL_HIGH_LSB _u(5) -#define IO_QSPI_PROC0_INTE_USBPHY_DM_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTE_USBPHY_DM_LEVEL_LOW -#define IO_QSPI_PROC0_INTE_USBPHY_DM_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_PROC0_INTE_USBPHY_DM_LEVEL_LOW_BITS _u(0x00000010) -#define IO_QSPI_PROC0_INTE_USBPHY_DM_LEVEL_LOW_MSB _u(4) -#define IO_QSPI_PROC0_INTE_USBPHY_DM_LEVEL_LOW_LSB _u(4) -#define IO_QSPI_PROC0_INTE_USBPHY_DM_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTE_USBPHY_DP_EDGE_HIGH -#define IO_QSPI_PROC0_INTE_USBPHY_DP_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC0_INTE_USBPHY_DP_EDGE_HIGH_BITS _u(0x00000008) -#define IO_QSPI_PROC0_INTE_USBPHY_DP_EDGE_HIGH_MSB _u(3) -#define IO_QSPI_PROC0_INTE_USBPHY_DP_EDGE_HIGH_LSB _u(3) -#define IO_QSPI_PROC0_INTE_USBPHY_DP_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTE_USBPHY_DP_EDGE_LOW -#define IO_QSPI_PROC0_INTE_USBPHY_DP_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_PROC0_INTE_USBPHY_DP_EDGE_LOW_BITS _u(0x00000004) -#define IO_QSPI_PROC0_INTE_USBPHY_DP_EDGE_LOW_MSB _u(2) -#define IO_QSPI_PROC0_INTE_USBPHY_DP_EDGE_LOW_LSB _u(2) -#define IO_QSPI_PROC0_INTE_USBPHY_DP_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTE_USBPHY_DP_LEVEL_HIGH -#define IO_QSPI_PROC0_INTE_USBPHY_DP_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC0_INTE_USBPHY_DP_LEVEL_HIGH_BITS _u(0x00000002) -#define IO_QSPI_PROC0_INTE_USBPHY_DP_LEVEL_HIGH_MSB _u(1) -#define IO_QSPI_PROC0_INTE_USBPHY_DP_LEVEL_HIGH_LSB _u(1) -#define IO_QSPI_PROC0_INTE_USBPHY_DP_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTE_USBPHY_DP_LEVEL_LOW -#define IO_QSPI_PROC0_INTE_USBPHY_DP_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_PROC0_INTE_USBPHY_DP_LEVEL_LOW_BITS _u(0x00000001) -#define IO_QSPI_PROC0_INTE_USBPHY_DP_LEVEL_LOW_MSB _u(0) -#define IO_QSPI_PROC0_INTE_USBPHY_DP_LEVEL_LOW_LSB _u(0) -#define IO_QSPI_PROC0_INTE_USBPHY_DP_LEVEL_LOW_ACCESS "RW" -// ============================================================================= -// Register : IO_QSPI_PROC0_INTF -// Description : Interrupt Force for proc0 -#define IO_QSPI_PROC0_INTF_OFFSET _u(0x00000220) -#define IO_QSPI_PROC0_INTF_BITS _u(0xffffffff) -#define IO_QSPI_PROC0_INTF_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_HIGH -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_HIGH_BITS _u(0x80000000) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_HIGH_MSB _u(31) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_HIGH_LSB _u(31) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_LOW -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_LOW_BITS _u(0x40000000) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_LOW_MSB _u(30) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_LOW_LSB _u(30) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_HIGH -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_BITS _u(0x20000000) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_MSB _u(29) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_LSB _u(29) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_LOW -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_LOW_BITS _u(0x10000000) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_LOW_MSB _u(28) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_LOW_LSB _u(28) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_HIGH -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_HIGH_BITS _u(0x08000000) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_HIGH_MSB _u(27) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_HIGH_LSB _u(27) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_LOW -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_LOW_BITS _u(0x04000000) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_LOW_MSB _u(26) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_LOW_LSB _u(26) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_HIGH -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_BITS _u(0x02000000) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_MSB _u(25) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_LSB _u(25) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_LOW -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_LOW_BITS _u(0x01000000) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_LOW_MSB _u(24) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_LOW_LSB _u(24) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_HIGH -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_HIGH_BITS _u(0x00800000) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_HIGH_MSB _u(23) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_HIGH_LSB _u(23) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_LOW -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_LOW_BITS _u(0x00400000) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_LOW_MSB _u(22) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_LOW_LSB _u(22) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_HIGH -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_BITS _u(0x00200000) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_MSB _u(21) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_LSB _u(21) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_LOW -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_LOW_BITS _u(0x00100000) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_LOW_MSB _u(20) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_LOW_LSB _u(20) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_HIGH -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_HIGH_BITS _u(0x00080000) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_HIGH_MSB _u(19) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_HIGH_LSB _u(19) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_LOW -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_LOW_BITS _u(0x00040000) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_LOW_MSB _u(18) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_LOW_LSB _u(18) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_HIGH -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_BITS _u(0x00020000) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_MSB _u(17) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_LSB _u(17) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_LOW -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_LOW_BITS _u(0x00010000) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_LOW_MSB _u(16) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_LOW_LSB _u(16) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_HIGH -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_HIGH_BITS _u(0x00008000) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_HIGH_MSB _u(15) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_HIGH_LSB _u(15) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_LOW -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_LOW_BITS _u(0x00004000) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_LOW_MSB _u(14) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_LOW_LSB _u(14) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_HIGH -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_HIGH_BITS _u(0x00002000) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_HIGH_MSB _u(13) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_HIGH_LSB _u(13) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_LOW -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_LOW_BITS _u(0x00001000) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_LOW_MSB _u(12) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_LOW_LSB _u(12) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_HIGH -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_BITS _u(0x00000800) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_MSB _u(11) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_LSB _u(11) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_LOW -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_LOW_BITS _u(0x00000400) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_LOW_MSB _u(10) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_LOW_LSB _u(10) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS _u(0x00000200) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB _u(9) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB _u(9) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_LOW -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_BITS _u(0x00000100) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_MSB _u(8) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_LSB _u(8) -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTF_USBPHY_DM_EDGE_HIGH -#define IO_QSPI_PROC0_INTF_USBPHY_DM_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC0_INTF_USBPHY_DM_EDGE_HIGH_BITS _u(0x00000080) -#define IO_QSPI_PROC0_INTF_USBPHY_DM_EDGE_HIGH_MSB _u(7) -#define IO_QSPI_PROC0_INTF_USBPHY_DM_EDGE_HIGH_LSB _u(7) -#define IO_QSPI_PROC0_INTF_USBPHY_DM_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTF_USBPHY_DM_EDGE_LOW -#define IO_QSPI_PROC0_INTF_USBPHY_DM_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_PROC0_INTF_USBPHY_DM_EDGE_LOW_BITS _u(0x00000040) -#define IO_QSPI_PROC0_INTF_USBPHY_DM_EDGE_LOW_MSB _u(6) -#define IO_QSPI_PROC0_INTF_USBPHY_DM_EDGE_LOW_LSB _u(6) -#define IO_QSPI_PROC0_INTF_USBPHY_DM_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTF_USBPHY_DM_LEVEL_HIGH -#define IO_QSPI_PROC0_INTF_USBPHY_DM_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC0_INTF_USBPHY_DM_LEVEL_HIGH_BITS _u(0x00000020) -#define IO_QSPI_PROC0_INTF_USBPHY_DM_LEVEL_HIGH_MSB _u(5) -#define IO_QSPI_PROC0_INTF_USBPHY_DM_LEVEL_HIGH_LSB _u(5) -#define IO_QSPI_PROC0_INTF_USBPHY_DM_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTF_USBPHY_DM_LEVEL_LOW -#define IO_QSPI_PROC0_INTF_USBPHY_DM_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_PROC0_INTF_USBPHY_DM_LEVEL_LOW_BITS _u(0x00000010) -#define IO_QSPI_PROC0_INTF_USBPHY_DM_LEVEL_LOW_MSB _u(4) -#define IO_QSPI_PROC0_INTF_USBPHY_DM_LEVEL_LOW_LSB _u(4) -#define IO_QSPI_PROC0_INTF_USBPHY_DM_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTF_USBPHY_DP_EDGE_HIGH -#define IO_QSPI_PROC0_INTF_USBPHY_DP_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC0_INTF_USBPHY_DP_EDGE_HIGH_BITS _u(0x00000008) -#define IO_QSPI_PROC0_INTF_USBPHY_DP_EDGE_HIGH_MSB _u(3) -#define IO_QSPI_PROC0_INTF_USBPHY_DP_EDGE_HIGH_LSB _u(3) -#define IO_QSPI_PROC0_INTF_USBPHY_DP_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTF_USBPHY_DP_EDGE_LOW -#define IO_QSPI_PROC0_INTF_USBPHY_DP_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_PROC0_INTF_USBPHY_DP_EDGE_LOW_BITS _u(0x00000004) -#define IO_QSPI_PROC0_INTF_USBPHY_DP_EDGE_LOW_MSB _u(2) -#define IO_QSPI_PROC0_INTF_USBPHY_DP_EDGE_LOW_LSB _u(2) -#define IO_QSPI_PROC0_INTF_USBPHY_DP_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTF_USBPHY_DP_LEVEL_HIGH -#define IO_QSPI_PROC0_INTF_USBPHY_DP_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC0_INTF_USBPHY_DP_LEVEL_HIGH_BITS _u(0x00000002) -#define IO_QSPI_PROC0_INTF_USBPHY_DP_LEVEL_HIGH_MSB _u(1) -#define IO_QSPI_PROC0_INTF_USBPHY_DP_LEVEL_HIGH_LSB _u(1) -#define IO_QSPI_PROC0_INTF_USBPHY_DP_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTF_USBPHY_DP_LEVEL_LOW -#define IO_QSPI_PROC0_INTF_USBPHY_DP_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_PROC0_INTF_USBPHY_DP_LEVEL_LOW_BITS _u(0x00000001) -#define IO_QSPI_PROC0_INTF_USBPHY_DP_LEVEL_LOW_MSB _u(0) -#define IO_QSPI_PROC0_INTF_USBPHY_DP_LEVEL_LOW_LSB _u(0) -#define IO_QSPI_PROC0_INTF_USBPHY_DP_LEVEL_LOW_ACCESS "RW" -// ============================================================================= -// Register : IO_QSPI_PROC0_INTS -// Description : Interrupt status after masking & forcing for proc0 -#define IO_QSPI_PROC0_INTS_OFFSET _u(0x00000224) -#define IO_QSPI_PROC0_INTS_BITS _u(0xffffffff) -#define IO_QSPI_PROC0_INTS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_HIGH -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_HIGH_BITS _u(0x80000000) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_HIGH_MSB _u(31) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_HIGH_LSB _u(31) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_LOW -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_LOW_BITS _u(0x40000000) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_LOW_MSB _u(30) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_LOW_LSB _u(30) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_HIGH -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_BITS _u(0x20000000) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_MSB _u(29) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_LSB _u(29) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_LOW -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_LOW_BITS _u(0x10000000) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_LOW_MSB _u(28) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_LOW_LSB _u(28) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_HIGH -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_HIGH_BITS _u(0x08000000) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_HIGH_MSB _u(27) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_HIGH_LSB _u(27) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_LOW -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_LOW_BITS _u(0x04000000) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_LOW_MSB _u(26) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_LOW_LSB _u(26) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_HIGH -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_BITS _u(0x02000000) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_MSB _u(25) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_LSB _u(25) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_LOW -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_LOW_BITS _u(0x01000000) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_LOW_MSB _u(24) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_LOW_LSB _u(24) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_HIGH -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_HIGH_BITS _u(0x00800000) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_HIGH_MSB _u(23) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_HIGH_LSB _u(23) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_LOW -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_LOW_BITS _u(0x00400000) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_LOW_MSB _u(22) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_LOW_LSB _u(22) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_HIGH -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_BITS _u(0x00200000) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_MSB _u(21) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_LSB _u(21) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_LOW -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_LOW_BITS _u(0x00100000) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_LOW_MSB _u(20) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_LOW_LSB _u(20) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_HIGH -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_HIGH_BITS _u(0x00080000) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_HIGH_MSB _u(19) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_HIGH_LSB _u(19) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_LOW -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_LOW_BITS _u(0x00040000) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_LOW_MSB _u(18) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_LOW_LSB _u(18) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_HIGH -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_BITS _u(0x00020000) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_MSB _u(17) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_LSB _u(17) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_LOW -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_LOW_BITS _u(0x00010000) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_LOW_MSB _u(16) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_LOW_LSB _u(16) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_HIGH -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_HIGH_BITS _u(0x00008000) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_HIGH_MSB _u(15) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_HIGH_LSB _u(15) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_LOW -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_LOW_BITS _u(0x00004000) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_LOW_MSB _u(14) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_LOW_LSB _u(14) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_HIGH -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_HIGH_BITS _u(0x00002000) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_HIGH_MSB _u(13) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_HIGH_LSB _u(13) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_LOW -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_LOW_BITS _u(0x00001000) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_LOW_MSB _u(12) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_LOW_LSB _u(12) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_HIGH -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_BITS _u(0x00000800) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_MSB _u(11) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_LSB _u(11) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_LOW -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_LOW_BITS _u(0x00000400) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_LOW_MSB _u(10) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_LOW_LSB _u(10) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS _u(0x00000200) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB _u(9) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB _u(9) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_LOW -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_BITS _u(0x00000100) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_MSB _u(8) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_LSB _u(8) -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTS_USBPHY_DM_EDGE_HIGH -#define IO_QSPI_PROC0_INTS_USBPHY_DM_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC0_INTS_USBPHY_DM_EDGE_HIGH_BITS _u(0x00000080) -#define IO_QSPI_PROC0_INTS_USBPHY_DM_EDGE_HIGH_MSB _u(7) -#define IO_QSPI_PROC0_INTS_USBPHY_DM_EDGE_HIGH_LSB _u(7) -#define IO_QSPI_PROC0_INTS_USBPHY_DM_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTS_USBPHY_DM_EDGE_LOW -#define IO_QSPI_PROC0_INTS_USBPHY_DM_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_PROC0_INTS_USBPHY_DM_EDGE_LOW_BITS _u(0x00000040) -#define IO_QSPI_PROC0_INTS_USBPHY_DM_EDGE_LOW_MSB _u(6) -#define IO_QSPI_PROC0_INTS_USBPHY_DM_EDGE_LOW_LSB _u(6) -#define IO_QSPI_PROC0_INTS_USBPHY_DM_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTS_USBPHY_DM_LEVEL_HIGH -#define IO_QSPI_PROC0_INTS_USBPHY_DM_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC0_INTS_USBPHY_DM_LEVEL_HIGH_BITS _u(0x00000020) -#define IO_QSPI_PROC0_INTS_USBPHY_DM_LEVEL_HIGH_MSB _u(5) -#define IO_QSPI_PROC0_INTS_USBPHY_DM_LEVEL_HIGH_LSB _u(5) -#define IO_QSPI_PROC0_INTS_USBPHY_DM_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTS_USBPHY_DM_LEVEL_LOW -#define IO_QSPI_PROC0_INTS_USBPHY_DM_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_PROC0_INTS_USBPHY_DM_LEVEL_LOW_BITS _u(0x00000010) -#define IO_QSPI_PROC0_INTS_USBPHY_DM_LEVEL_LOW_MSB _u(4) -#define IO_QSPI_PROC0_INTS_USBPHY_DM_LEVEL_LOW_LSB _u(4) -#define IO_QSPI_PROC0_INTS_USBPHY_DM_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTS_USBPHY_DP_EDGE_HIGH -#define IO_QSPI_PROC0_INTS_USBPHY_DP_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC0_INTS_USBPHY_DP_EDGE_HIGH_BITS _u(0x00000008) -#define IO_QSPI_PROC0_INTS_USBPHY_DP_EDGE_HIGH_MSB _u(3) -#define IO_QSPI_PROC0_INTS_USBPHY_DP_EDGE_HIGH_LSB _u(3) -#define IO_QSPI_PROC0_INTS_USBPHY_DP_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTS_USBPHY_DP_EDGE_LOW -#define IO_QSPI_PROC0_INTS_USBPHY_DP_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_PROC0_INTS_USBPHY_DP_EDGE_LOW_BITS _u(0x00000004) -#define IO_QSPI_PROC0_INTS_USBPHY_DP_EDGE_LOW_MSB _u(2) -#define IO_QSPI_PROC0_INTS_USBPHY_DP_EDGE_LOW_LSB _u(2) -#define IO_QSPI_PROC0_INTS_USBPHY_DP_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTS_USBPHY_DP_LEVEL_HIGH -#define IO_QSPI_PROC0_INTS_USBPHY_DP_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC0_INTS_USBPHY_DP_LEVEL_HIGH_BITS _u(0x00000002) -#define IO_QSPI_PROC0_INTS_USBPHY_DP_LEVEL_HIGH_MSB _u(1) -#define IO_QSPI_PROC0_INTS_USBPHY_DP_LEVEL_HIGH_LSB _u(1) -#define IO_QSPI_PROC0_INTS_USBPHY_DP_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC0_INTS_USBPHY_DP_LEVEL_LOW -#define IO_QSPI_PROC0_INTS_USBPHY_DP_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_PROC0_INTS_USBPHY_DP_LEVEL_LOW_BITS _u(0x00000001) -#define IO_QSPI_PROC0_INTS_USBPHY_DP_LEVEL_LOW_MSB _u(0) -#define IO_QSPI_PROC0_INTS_USBPHY_DP_LEVEL_LOW_LSB _u(0) -#define IO_QSPI_PROC0_INTS_USBPHY_DP_LEVEL_LOW_ACCESS "RO" -// ============================================================================= -// Register : IO_QSPI_PROC1_INTE -// Description : Interrupt Enable for proc1 -#define IO_QSPI_PROC1_INTE_OFFSET _u(0x00000228) -#define IO_QSPI_PROC1_INTE_BITS _u(0xffffffff) -#define IO_QSPI_PROC1_INTE_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_HIGH -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_HIGH_BITS _u(0x80000000) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_HIGH_MSB _u(31) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_HIGH_LSB _u(31) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_LOW -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_LOW_BITS _u(0x40000000) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_LOW_MSB _u(30) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_LOW_LSB _u(30) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_HIGH -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_BITS _u(0x20000000) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_MSB _u(29) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_LSB _u(29) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_LOW -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_LOW_BITS _u(0x10000000) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_LOW_MSB _u(28) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_LOW_LSB _u(28) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_HIGH -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_HIGH_BITS _u(0x08000000) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_HIGH_MSB _u(27) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_HIGH_LSB _u(27) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_LOW -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_LOW_BITS _u(0x04000000) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_LOW_MSB _u(26) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_LOW_LSB _u(26) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_HIGH -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_BITS _u(0x02000000) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_MSB _u(25) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_LSB _u(25) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_LOW -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_LOW_BITS _u(0x01000000) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_LOW_MSB _u(24) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_LOW_LSB _u(24) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_HIGH -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_HIGH_BITS _u(0x00800000) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_HIGH_MSB _u(23) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_HIGH_LSB _u(23) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_LOW -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_LOW_BITS _u(0x00400000) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_LOW_MSB _u(22) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_LOW_LSB _u(22) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_HIGH -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_BITS _u(0x00200000) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_MSB _u(21) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_LSB _u(21) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_LOW -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_LOW_BITS _u(0x00100000) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_LOW_MSB _u(20) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_LOW_LSB _u(20) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_HIGH -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_HIGH_BITS _u(0x00080000) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_HIGH_MSB _u(19) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_HIGH_LSB _u(19) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_LOW -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_LOW_BITS _u(0x00040000) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_LOW_MSB _u(18) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_LOW_LSB _u(18) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_HIGH -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_BITS _u(0x00020000) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_MSB _u(17) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_LSB _u(17) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_LOW -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_LOW_BITS _u(0x00010000) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_LOW_MSB _u(16) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_LOW_LSB _u(16) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_HIGH -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_HIGH_BITS _u(0x00008000) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_HIGH_MSB _u(15) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_HIGH_LSB _u(15) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_LOW -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_LOW_BITS _u(0x00004000) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_LOW_MSB _u(14) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_LOW_LSB _u(14) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_HIGH -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_HIGH_BITS _u(0x00002000) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_HIGH_MSB _u(13) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_HIGH_LSB _u(13) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_LOW -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_LOW_BITS _u(0x00001000) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_LOW_MSB _u(12) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_LOW_LSB _u(12) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_HIGH -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_BITS _u(0x00000800) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_MSB _u(11) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_LSB _u(11) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_LOW -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_LOW_BITS _u(0x00000400) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_LOW_MSB _u(10) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_LOW_LSB _u(10) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS _u(0x00000200) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB _u(9) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB _u(9) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_LOW -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_BITS _u(0x00000100) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_MSB _u(8) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_LSB _u(8) -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTE_USBPHY_DM_EDGE_HIGH -#define IO_QSPI_PROC1_INTE_USBPHY_DM_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC1_INTE_USBPHY_DM_EDGE_HIGH_BITS _u(0x00000080) -#define IO_QSPI_PROC1_INTE_USBPHY_DM_EDGE_HIGH_MSB _u(7) -#define IO_QSPI_PROC1_INTE_USBPHY_DM_EDGE_HIGH_LSB _u(7) -#define IO_QSPI_PROC1_INTE_USBPHY_DM_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTE_USBPHY_DM_EDGE_LOW -#define IO_QSPI_PROC1_INTE_USBPHY_DM_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_PROC1_INTE_USBPHY_DM_EDGE_LOW_BITS _u(0x00000040) -#define IO_QSPI_PROC1_INTE_USBPHY_DM_EDGE_LOW_MSB _u(6) -#define IO_QSPI_PROC1_INTE_USBPHY_DM_EDGE_LOW_LSB _u(6) -#define IO_QSPI_PROC1_INTE_USBPHY_DM_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTE_USBPHY_DM_LEVEL_HIGH -#define IO_QSPI_PROC1_INTE_USBPHY_DM_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC1_INTE_USBPHY_DM_LEVEL_HIGH_BITS _u(0x00000020) -#define IO_QSPI_PROC1_INTE_USBPHY_DM_LEVEL_HIGH_MSB _u(5) -#define IO_QSPI_PROC1_INTE_USBPHY_DM_LEVEL_HIGH_LSB _u(5) -#define IO_QSPI_PROC1_INTE_USBPHY_DM_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTE_USBPHY_DM_LEVEL_LOW -#define IO_QSPI_PROC1_INTE_USBPHY_DM_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_PROC1_INTE_USBPHY_DM_LEVEL_LOW_BITS _u(0x00000010) -#define IO_QSPI_PROC1_INTE_USBPHY_DM_LEVEL_LOW_MSB _u(4) -#define IO_QSPI_PROC1_INTE_USBPHY_DM_LEVEL_LOW_LSB _u(4) -#define IO_QSPI_PROC1_INTE_USBPHY_DM_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTE_USBPHY_DP_EDGE_HIGH -#define IO_QSPI_PROC1_INTE_USBPHY_DP_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC1_INTE_USBPHY_DP_EDGE_HIGH_BITS _u(0x00000008) -#define IO_QSPI_PROC1_INTE_USBPHY_DP_EDGE_HIGH_MSB _u(3) -#define IO_QSPI_PROC1_INTE_USBPHY_DP_EDGE_HIGH_LSB _u(3) -#define IO_QSPI_PROC1_INTE_USBPHY_DP_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTE_USBPHY_DP_EDGE_LOW -#define IO_QSPI_PROC1_INTE_USBPHY_DP_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_PROC1_INTE_USBPHY_DP_EDGE_LOW_BITS _u(0x00000004) -#define IO_QSPI_PROC1_INTE_USBPHY_DP_EDGE_LOW_MSB _u(2) -#define IO_QSPI_PROC1_INTE_USBPHY_DP_EDGE_LOW_LSB _u(2) -#define IO_QSPI_PROC1_INTE_USBPHY_DP_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTE_USBPHY_DP_LEVEL_HIGH -#define IO_QSPI_PROC1_INTE_USBPHY_DP_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC1_INTE_USBPHY_DP_LEVEL_HIGH_BITS _u(0x00000002) -#define IO_QSPI_PROC1_INTE_USBPHY_DP_LEVEL_HIGH_MSB _u(1) -#define IO_QSPI_PROC1_INTE_USBPHY_DP_LEVEL_HIGH_LSB _u(1) -#define IO_QSPI_PROC1_INTE_USBPHY_DP_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTE_USBPHY_DP_LEVEL_LOW -#define IO_QSPI_PROC1_INTE_USBPHY_DP_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_PROC1_INTE_USBPHY_DP_LEVEL_LOW_BITS _u(0x00000001) -#define IO_QSPI_PROC1_INTE_USBPHY_DP_LEVEL_LOW_MSB _u(0) -#define IO_QSPI_PROC1_INTE_USBPHY_DP_LEVEL_LOW_LSB _u(0) -#define IO_QSPI_PROC1_INTE_USBPHY_DP_LEVEL_LOW_ACCESS "RW" -// ============================================================================= -// Register : IO_QSPI_PROC1_INTF -// Description : Interrupt Force for proc1 -#define IO_QSPI_PROC1_INTF_OFFSET _u(0x0000022c) -#define IO_QSPI_PROC1_INTF_BITS _u(0xffffffff) -#define IO_QSPI_PROC1_INTF_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_HIGH -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_HIGH_BITS _u(0x80000000) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_HIGH_MSB _u(31) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_HIGH_LSB _u(31) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_LOW -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_LOW_BITS _u(0x40000000) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_LOW_MSB _u(30) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_LOW_LSB _u(30) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_HIGH -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_BITS _u(0x20000000) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_MSB _u(29) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_LSB _u(29) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_LOW -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_LOW_BITS _u(0x10000000) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_LOW_MSB _u(28) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_LOW_LSB _u(28) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_HIGH -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_HIGH_BITS _u(0x08000000) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_HIGH_MSB _u(27) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_HIGH_LSB _u(27) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_LOW -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_LOW_BITS _u(0x04000000) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_LOW_MSB _u(26) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_LOW_LSB _u(26) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_HIGH -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_BITS _u(0x02000000) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_MSB _u(25) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_LSB _u(25) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_LOW -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_LOW_BITS _u(0x01000000) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_LOW_MSB _u(24) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_LOW_LSB _u(24) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_HIGH -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_HIGH_BITS _u(0x00800000) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_HIGH_MSB _u(23) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_HIGH_LSB _u(23) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_LOW -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_LOW_BITS _u(0x00400000) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_LOW_MSB _u(22) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_LOW_LSB _u(22) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_HIGH -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_BITS _u(0x00200000) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_MSB _u(21) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_LSB _u(21) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_LOW -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_LOW_BITS _u(0x00100000) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_LOW_MSB _u(20) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_LOW_LSB _u(20) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_HIGH -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_HIGH_BITS _u(0x00080000) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_HIGH_MSB _u(19) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_HIGH_LSB _u(19) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_LOW -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_LOW_BITS _u(0x00040000) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_LOW_MSB _u(18) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_LOW_LSB _u(18) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_HIGH -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_BITS _u(0x00020000) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_MSB _u(17) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_LSB _u(17) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_LOW -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_LOW_BITS _u(0x00010000) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_LOW_MSB _u(16) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_LOW_LSB _u(16) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_HIGH -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_HIGH_BITS _u(0x00008000) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_HIGH_MSB _u(15) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_HIGH_LSB _u(15) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_LOW -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_LOW_BITS _u(0x00004000) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_LOW_MSB _u(14) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_LOW_LSB _u(14) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_HIGH -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_HIGH_BITS _u(0x00002000) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_HIGH_MSB _u(13) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_HIGH_LSB _u(13) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_LOW -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_LOW_BITS _u(0x00001000) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_LOW_MSB _u(12) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_LOW_LSB _u(12) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_HIGH -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_BITS _u(0x00000800) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_MSB _u(11) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_LSB _u(11) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_LOW -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_LOW_BITS _u(0x00000400) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_LOW_MSB _u(10) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_LOW_LSB _u(10) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS _u(0x00000200) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB _u(9) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB _u(9) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_LOW -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_BITS _u(0x00000100) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_MSB _u(8) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_LSB _u(8) -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTF_USBPHY_DM_EDGE_HIGH -#define IO_QSPI_PROC1_INTF_USBPHY_DM_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC1_INTF_USBPHY_DM_EDGE_HIGH_BITS _u(0x00000080) -#define IO_QSPI_PROC1_INTF_USBPHY_DM_EDGE_HIGH_MSB _u(7) -#define IO_QSPI_PROC1_INTF_USBPHY_DM_EDGE_HIGH_LSB _u(7) -#define IO_QSPI_PROC1_INTF_USBPHY_DM_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTF_USBPHY_DM_EDGE_LOW -#define IO_QSPI_PROC1_INTF_USBPHY_DM_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_PROC1_INTF_USBPHY_DM_EDGE_LOW_BITS _u(0x00000040) -#define IO_QSPI_PROC1_INTF_USBPHY_DM_EDGE_LOW_MSB _u(6) -#define IO_QSPI_PROC1_INTF_USBPHY_DM_EDGE_LOW_LSB _u(6) -#define IO_QSPI_PROC1_INTF_USBPHY_DM_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTF_USBPHY_DM_LEVEL_HIGH -#define IO_QSPI_PROC1_INTF_USBPHY_DM_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC1_INTF_USBPHY_DM_LEVEL_HIGH_BITS _u(0x00000020) -#define IO_QSPI_PROC1_INTF_USBPHY_DM_LEVEL_HIGH_MSB _u(5) -#define IO_QSPI_PROC1_INTF_USBPHY_DM_LEVEL_HIGH_LSB _u(5) -#define IO_QSPI_PROC1_INTF_USBPHY_DM_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTF_USBPHY_DM_LEVEL_LOW -#define IO_QSPI_PROC1_INTF_USBPHY_DM_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_PROC1_INTF_USBPHY_DM_LEVEL_LOW_BITS _u(0x00000010) -#define IO_QSPI_PROC1_INTF_USBPHY_DM_LEVEL_LOW_MSB _u(4) -#define IO_QSPI_PROC1_INTF_USBPHY_DM_LEVEL_LOW_LSB _u(4) -#define IO_QSPI_PROC1_INTF_USBPHY_DM_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTF_USBPHY_DP_EDGE_HIGH -#define IO_QSPI_PROC1_INTF_USBPHY_DP_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC1_INTF_USBPHY_DP_EDGE_HIGH_BITS _u(0x00000008) -#define IO_QSPI_PROC1_INTF_USBPHY_DP_EDGE_HIGH_MSB _u(3) -#define IO_QSPI_PROC1_INTF_USBPHY_DP_EDGE_HIGH_LSB _u(3) -#define IO_QSPI_PROC1_INTF_USBPHY_DP_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTF_USBPHY_DP_EDGE_LOW -#define IO_QSPI_PROC1_INTF_USBPHY_DP_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_PROC1_INTF_USBPHY_DP_EDGE_LOW_BITS _u(0x00000004) -#define IO_QSPI_PROC1_INTF_USBPHY_DP_EDGE_LOW_MSB _u(2) -#define IO_QSPI_PROC1_INTF_USBPHY_DP_EDGE_LOW_LSB _u(2) -#define IO_QSPI_PROC1_INTF_USBPHY_DP_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTF_USBPHY_DP_LEVEL_HIGH -#define IO_QSPI_PROC1_INTF_USBPHY_DP_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC1_INTF_USBPHY_DP_LEVEL_HIGH_BITS _u(0x00000002) -#define IO_QSPI_PROC1_INTF_USBPHY_DP_LEVEL_HIGH_MSB _u(1) -#define IO_QSPI_PROC1_INTF_USBPHY_DP_LEVEL_HIGH_LSB _u(1) -#define IO_QSPI_PROC1_INTF_USBPHY_DP_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTF_USBPHY_DP_LEVEL_LOW -#define IO_QSPI_PROC1_INTF_USBPHY_DP_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_PROC1_INTF_USBPHY_DP_LEVEL_LOW_BITS _u(0x00000001) -#define IO_QSPI_PROC1_INTF_USBPHY_DP_LEVEL_LOW_MSB _u(0) -#define IO_QSPI_PROC1_INTF_USBPHY_DP_LEVEL_LOW_LSB _u(0) -#define IO_QSPI_PROC1_INTF_USBPHY_DP_LEVEL_LOW_ACCESS "RW" -// ============================================================================= -// Register : IO_QSPI_PROC1_INTS -// Description : Interrupt status after masking & forcing for proc1 -#define IO_QSPI_PROC1_INTS_OFFSET _u(0x00000230) -#define IO_QSPI_PROC1_INTS_BITS _u(0xffffffff) -#define IO_QSPI_PROC1_INTS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_HIGH -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_HIGH_BITS _u(0x80000000) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_HIGH_MSB _u(31) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_HIGH_LSB _u(31) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_LOW -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_LOW_BITS _u(0x40000000) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_LOW_MSB _u(30) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_LOW_LSB _u(30) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_HIGH -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_BITS _u(0x20000000) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_MSB _u(29) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_LSB _u(29) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_LOW -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_LOW_BITS _u(0x10000000) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_LOW_MSB _u(28) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_LOW_LSB _u(28) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_HIGH -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_HIGH_BITS _u(0x08000000) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_HIGH_MSB _u(27) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_HIGH_LSB _u(27) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_LOW -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_LOW_BITS _u(0x04000000) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_LOW_MSB _u(26) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_LOW_LSB _u(26) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_HIGH -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_BITS _u(0x02000000) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_MSB _u(25) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_LSB _u(25) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_LOW -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_LOW_BITS _u(0x01000000) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_LOW_MSB _u(24) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_LOW_LSB _u(24) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_HIGH -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_HIGH_BITS _u(0x00800000) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_HIGH_MSB _u(23) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_HIGH_LSB _u(23) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_LOW -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_LOW_BITS _u(0x00400000) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_LOW_MSB _u(22) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_LOW_LSB _u(22) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_HIGH -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_BITS _u(0x00200000) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_MSB _u(21) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_LSB _u(21) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_LOW -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_LOW_BITS _u(0x00100000) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_LOW_MSB _u(20) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_LOW_LSB _u(20) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_HIGH -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_HIGH_BITS _u(0x00080000) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_HIGH_MSB _u(19) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_HIGH_LSB _u(19) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_LOW -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_LOW_BITS _u(0x00040000) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_LOW_MSB _u(18) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_LOW_LSB _u(18) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_HIGH -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_BITS _u(0x00020000) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_MSB _u(17) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_LSB _u(17) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_LOW -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_LOW_BITS _u(0x00010000) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_LOW_MSB _u(16) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_LOW_LSB _u(16) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_HIGH -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_HIGH_BITS _u(0x00008000) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_HIGH_MSB _u(15) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_HIGH_LSB _u(15) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_LOW -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_LOW_BITS _u(0x00004000) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_LOW_MSB _u(14) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_LOW_LSB _u(14) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_HIGH -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_HIGH_BITS _u(0x00002000) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_HIGH_MSB _u(13) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_HIGH_LSB _u(13) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_LOW -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_LOW_BITS _u(0x00001000) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_LOW_MSB _u(12) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_LOW_LSB _u(12) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_HIGH -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_BITS _u(0x00000800) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_MSB _u(11) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_LSB _u(11) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_LOW -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_LOW_BITS _u(0x00000400) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_LOW_MSB _u(10) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_LOW_LSB _u(10) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS _u(0x00000200) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB _u(9) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB _u(9) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_LOW -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_BITS _u(0x00000100) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_MSB _u(8) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_LSB _u(8) -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTS_USBPHY_DM_EDGE_HIGH -#define IO_QSPI_PROC1_INTS_USBPHY_DM_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC1_INTS_USBPHY_DM_EDGE_HIGH_BITS _u(0x00000080) -#define IO_QSPI_PROC1_INTS_USBPHY_DM_EDGE_HIGH_MSB _u(7) -#define IO_QSPI_PROC1_INTS_USBPHY_DM_EDGE_HIGH_LSB _u(7) -#define IO_QSPI_PROC1_INTS_USBPHY_DM_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTS_USBPHY_DM_EDGE_LOW -#define IO_QSPI_PROC1_INTS_USBPHY_DM_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_PROC1_INTS_USBPHY_DM_EDGE_LOW_BITS _u(0x00000040) -#define IO_QSPI_PROC1_INTS_USBPHY_DM_EDGE_LOW_MSB _u(6) -#define IO_QSPI_PROC1_INTS_USBPHY_DM_EDGE_LOW_LSB _u(6) -#define IO_QSPI_PROC1_INTS_USBPHY_DM_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTS_USBPHY_DM_LEVEL_HIGH -#define IO_QSPI_PROC1_INTS_USBPHY_DM_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC1_INTS_USBPHY_DM_LEVEL_HIGH_BITS _u(0x00000020) -#define IO_QSPI_PROC1_INTS_USBPHY_DM_LEVEL_HIGH_MSB _u(5) -#define IO_QSPI_PROC1_INTS_USBPHY_DM_LEVEL_HIGH_LSB _u(5) -#define IO_QSPI_PROC1_INTS_USBPHY_DM_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTS_USBPHY_DM_LEVEL_LOW -#define IO_QSPI_PROC1_INTS_USBPHY_DM_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_PROC1_INTS_USBPHY_DM_LEVEL_LOW_BITS _u(0x00000010) -#define IO_QSPI_PROC1_INTS_USBPHY_DM_LEVEL_LOW_MSB _u(4) -#define IO_QSPI_PROC1_INTS_USBPHY_DM_LEVEL_LOW_LSB _u(4) -#define IO_QSPI_PROC1_INTS_USBPHY_DM_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTS_USBPHY_DP_EDGE_HIGH -#define IO_QSPI_PROC1_INTS_USBPHY_DP_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC1_INTS_USBPHY_DP_EDGE_HIGH_BITS _u(0x00000008) -#define IO_QSPI_PROC1_INTS_USBPHY_DP_EDGE_HIGH_MSB _u(3) -#define IO_QSPI_PROC1_INTS_USBPHY_DP_EDGE_HIGH_LSB _u(3) -#define IO_QSPI_PROC1_INTS_USBPHY_DP_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTS_USBPHY_DP_EDGE_LOW -#define IO_QSPI_PROC1_INTS_USBPHY_DP_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_PROC1_INTS_USBPHY_DP_EDGE_LOW_BITS _u(0x00000004) -#define IO_QSPI_PROC1_INTS_USBPHY_DP_EDGE_LOW_MSB _u(2) -#define IO_QSPI_PROC1_INTS_USBPHY_DP_EDGE_LOW_LSB _u(2) -#define IO_QSPI_PROC1_INTS_USBPHY_DP_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTS_USBPHY_DP_LEVEL_HIGH -#define IO_QSPI_PROC1_INTS_USBPHY_DP_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_PROC1_INTS_USBPHY_DP_LEVEL_HIGH_BITS _u(0x00000002) -#define IO_QSPI_PROC1_INTS_USBPHY_DP_LEVEL_HIGH_MSB _u(1) -#define IO_QSPI_PROC1_INTS_USBPHY_DP_LEVEL_HIGH_LSB _u(1) -#define IO_QSPI_PROC1_INTS_USBPHY_DP_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_PROC1_INTS_USBPHY_DP_LEVEL_LOW -#define IO_QSPI_PROC1_INTS_USBPHY_DP_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_PROC1_INTS_USBPHY_DP_LEVEL_LOW_BITS _u(0x00000001) -#define IO_QSPI_PROC1_INTS_USBPHY_DP_LEVEL_LOW_MSB _u(0) -#define IO_QSPI_PROC1_INTS_USBPHY_DP_LEVEL_LOW_LSB _u(0) -#define IO_QSPI_PROC1_INTS_USBPHY_DP_LEVEL_LOW_ACCESS "RO" -// ============================================================================= -// Register : IO_QSPI_DORMANT_WAKE_INTE -// Description : Interrupt Enable for dormant_wake -#define IO_QSPI_DORMANT_WAKE_INTE_OFFSET _u(0x00000234) -#define IO_QSPI_DORMANT_WAKE_INTE_BITS _u(0xffffffff) -#define IO_QSPI_DORMANT_WAKE_INTE_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_HIGH -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_HIGH_BITS _u(0x80000000) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_HIGH_MSB _u(31) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_HIGH_LSB _u(31) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_LOW -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_LOW_BITS _u(0x40000000) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_LOW_MSB _u(30) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_LOW_LSB _u(30) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_HIGH -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_BITS _u(0x20000000) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_MSB _u(29) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_LSB _u(29) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_LOW -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_LOW_BITS _u(0x10000000) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_LOW_MSB _u(28) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_LOW_LSB _u(28) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_HIGH -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_HIGH_BITS _u(0x08000000) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_HIGH_MSB _u(27) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_HIGH_LSB _u(27) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_LOW -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_LOW_BITS _u(0x04000000) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_LOW_MSB _u(26) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_LOW_LSB _u(26) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_HIGH -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_BITS _u(0x02000000) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_MSB _u(25) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_LSB _u(25) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_LOW -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_LOW_BITS _u(0x01000000) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_LOW_MSB _u(24) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_LOW_LSB _u(24) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_HIGH -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_HIGH_BITS _u(0x00800000) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_HIGH_MSB _u(23) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_HIGH_LSB _u(23) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_LOW -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_LOW_BITS _u(0x00400000) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_LOW_MSB _u(22) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_LOW_LSB _u(22) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_HIGH -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_BITS _u(0x00200000) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_MSB _u(21) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_LSB _u(21) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_LOW -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_LOW_BITS _u(0x00100000) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_LOW_MSB _u(20) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_LOW_LSB _u(20) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_HIGH -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_HIGH_BITS _u(0x00080000) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_HIGH_MSB _u(19) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_HIGH_LSB _u(19) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_LOW -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_LOW_BITS _u(0x00040000) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_LOW_MSB _u(18) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_LOW_LSB _u(18) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_HIGH -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_BITS _u(0x00020000) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_MSB _u(17) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_LSB _u(17) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_LOW -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_LOW_BITS _u(0x00010000) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_LOW_MSB _u(16) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_LOW_LSB _u(16) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_HIGH -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_HIGH_BITS _u(0x00008000) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_HIGH_MSB _u(15) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_HIGH_LSB _u(15) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_LOW -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_LOW_BITS _u(0x00004000) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_LOW_MSB _u(14) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_LOW_LSB _u(14) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_HIGH -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_HIGH_BITS _u(0x00002000) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_HIGH_MSB _u(13) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_HIGH_LSB _u(13) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_LOW -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_LOW_BITS _u(0x00001000) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_LOW_MSB _u(12) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_LOW_LSB _u(12) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_HIGH -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_BITS _u(0x00000800) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_MSB _u(11) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_LSB _u(11) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_LOW -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_LOW_BITS _u(0x00000400) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_LOW_MSB _u(10) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_LOW_LSB _u(10) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS _u(0x00000200) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB _u(9) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB _u(9) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_LOW -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_BITS _u(0x00000100) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_MSB _u(8) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_LSB _u(8) -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DM_EDGE_HIGH -#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DM_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DM_EDGE_HIGH_BITS _u(0x00000080) -#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DM_EDGE_HIGH_MSB _u(7) -#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DM_EDGE_HIGH_LSB _u(7) -#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DM_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DM_EDGE_LOW -#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DM_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DM_EDGE_LOW_BITS _u(0x00000040) -#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DM_EDGE_LOW_MSB _u(6) -#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DM_EDGE_LOW_LSB _u(6) -#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DM_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DM_LEVEL_HIGH -#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DM_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DM_LEVEL_HIGH_BITS _u(0x00000020) -#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DM_LEVEL_HIGH_MSB _u(5) -#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DM_LEVEL_HIGH_LSB _u(5) -#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DM_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DM_LEVEL_LOW -#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DM_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DM_LEVEL_LOW_BITS _u(0x00000010) -#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DM_LEVEL_LOW_MSB _u(4) -#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DM_LEVEL_LOW_LSB _u(4) -#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DM_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DP_EDGE_HIGH -#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DP_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DP_EDGE_HIGH_BITS _u(0x00000008) -#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DP_EDGE_HIGH_MSB _u(3) -#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DP_EDGE_HIGH_LSB _u(3) -#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DP_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DP_EDGE_LOW -#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DP_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DP_EDGE_LOW_BITS _u(0x00000004) -#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DP_EDGE_LOW_MSB _u(2) -#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DP_EDGE_LOW_LSB _u(2) -#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DP_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DP_LEVEL_HIGH -#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DP_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DP_LEVEL_HIGH_BITS _u(0x00000002) -#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DP_LEVEL_HIGH_MSB _u(1) -#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DP_LEVEL_HIGH_LSB _u(1) -#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DP_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DP_LEVEL_LOW -#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DP_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DP_LEVEL_LOW_BITS _u(0x00000001) -#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DP_LEVEL_LOW_MSB _u(0) -#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DP_LEVEL_LOW_LSB _u(0) -#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DP_LEVEL_LOW_ACCESS "RW" -// ============================================================================= -// Register : IO_QSPI_DORMANT_WAKE_INTF -// Description : Interrupt Force for dormant_wake -#define IO_QSPI_DORMANT_WAKE_INTF_OFFSET _u(0x00000238) -#define IO_QSPI_DORMANT_WAKE_INTF_BITS _u(0xffffffff) -#define IO_QSPI_DORMANT_WAKE_INTF_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_HIGH -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_HIGH_BITS _u(0x80000000) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_HIGH_MSB _u(31) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_HIGH_LSB _u(31) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_LOW -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_LOW_BITS _u(0x40000000) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_LOW_MSB _u(30) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_LOW_LSB _u(30) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_HIGH -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_BITS _u(0x20000000) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_MSB _u(29) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_LSB _u(29) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_LOW -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_LOW_BITS _u(0x10000000) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_LOW_MSB _u(28) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_LOW_LSB _u(28) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_HIGH -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_HIGH_BITS _u(0x08000000) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_HIGH_MSB _u(27) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_HIGH_LSB _u(27) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_LOW -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_LOW_BITS _u(0x04000000) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_LOW_MSB _u(26) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_LOW_LSB _u(26) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_HIGH -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_BITS _u(0x02000000) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_MSB _u(25) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_LSB _u(25) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_LOW -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_LOW_BITS _u(0x01000000) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_LOW_MSB _u(24) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_LOW_LSB _u(24) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_HIGH -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_HIGH_BITS _u(0x00800000) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_HIGH_MSB _u(23) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_HIGH_LSB _u(23) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_LOW -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_LOW_BITS _u(0x00400000) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_LOW_MSB _u(22) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_LOW_LSB _u(22) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_HIGH -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_BITS _u(0x00200000) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_MSB _u(21) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_LSB _u(21) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_LOW -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_LOW_BITS _u(0x00100000) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_LOW_MSB _u(20) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_LOW_LSB _u(20) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_HIGH -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_HIGH_BITS _u(0x00080000) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_HIGH_MSB _u(19) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_HIGH_LSB _u(19) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_LOW -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_LOW_BITS _u(0x00040000) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_LOW_MSB _u(18) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_LOW_LSB _u(18) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_HIGH -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_BITS _u(0x00020000) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_MSB _u(17) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_LSB _u(17) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_LOW -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_LOW_BITS _u(0x00010000) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_LOW_MSB _u(16) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_LOW_LSB _u(16) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_HIGH -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_HIGH_BITS _u(0x00008000) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_HIGH_MSB _u(15) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_HIGH_LSB _u(15) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_LOW -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_LOW_BITS _u(0x00004000) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_LOW_MSB _u(14) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_LOW_LSB _u(14) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_HIGH -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_HIGH_BITS _u(0x00002000) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_HIGH_MSB _u(13) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_HIGH_LSB _u(13) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_LOW -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_LOW_BITS _u(0x00001000) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_LOW_MSB _u(12) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_LOW_LSB _u(12) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_HIGH -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_BITS _u(0x00000800) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_MSB _u(11) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_LSB _u(11) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_LOW -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_LOW_BITS _u(0x00000400) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_LOW_MSB _u(10) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_LOW_LSB _u(10) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS _u(0x00000200) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB _u(9) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB _u(9) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_LOW -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_BITS _u(0x00000100) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_MSB _u(8) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_LSB _u(8) -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DM_EDGE_HIGH -#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DM_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DM_EDGE_HIGH_BITS _u(0x00000080) -#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DM_EDGE_HIGH_MSB _u(7) -#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DM_EDGE_HIGH_LSB _u(7) -#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DM_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DM_EDGE_LOW -#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DM_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DM_EDGE_LOW_BITS _u(0x00000040) -#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DM_EDGE_LOW_MSB _u(6) -#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DM_EDGE_LOW_LSB _u(6) -#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DM_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DM_LEVEL_HIGH -#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DM_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DM_LEVEL_HIGH_BITS _u(0x00000020) -#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DM_LEVEL_HIGH_MSB _u(5) -#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DM_LEVEL_HIGH_LSB _u(5) -#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DM_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DM_LEVEL_LOW -#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DM_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DM_LEVEL_LOW_BITS _u(0x00000010) -#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DM_LEVEL_LOW_MSB _u(4) -#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DM_LEVEL_LOW_LSB _u(4) -#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DM_LEVEL_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DP_EDGE_HIGH -#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DP_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DP_EDGE_HIGH_BITS _u(0x00000008) -#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DP_EDGE_HIGH_MSB _u(3) -#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DP_EDGE_HIGH_LSB _u(3) -#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DP_EDGE_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DP_EDGE_LOW -#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DP_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DP_EDGE_LOW_BITS _u(0x00000004) -#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DP_EDGE_LOW_MSB _u(2) -#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DP_EDGE_LOW_LSB _u(2) -#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DP_EDGE_LOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DP_LEVEL_HIGH -#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DP_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DP_LEVEL_HIGH_BITS _u(0x00000002) -#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DP_LEVEL_HIGH_MSB _u(1) -#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DP_LEVEL_HIGH_LSB _u(1) -#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DP_LEVEL_HIGH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DP_LEVEL_LOW -#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DP_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DP_LEVEL_LOW_BITS _u(0x00000001) -#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DP_LEVEL_LOW_MSB _u(0) -#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DP_LEVEL_LOW_LSB _u(0) -#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DP_LEVEL_LOW_ACCESS "RW" -// ============================================================================= -// Register : IO_QSPI_DORMANT_WAKE_INTS -// Description : Interrupt status after masking & forcing for dormant_wake -#define IO_QSPI_DORMANT_WAKE_INTS_OFFSET _u(0x0000023c) -#define IO_QSPI_DORMANT_WAKE_INTS_BITS _u(0xffffffff) -#define IO_QSPI_DORMANT_WAKE_INTS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_HIGH -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_HIGH_BITS _u(0x80000000) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_HIGH_MSB _u(31) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_HIGH_LSB _u(31) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_LOW -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_LOW_BITS _u(0x40000000) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_LOW_MSB _u(30) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_LOW_LSB _u(30) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_HIGH -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_BITS _u(0x20000000) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_MSB _u(29) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_LSB _u(29) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_LOW -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_LOW_BITS _u(0x10000000) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_LOW_MSB _u(28) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_LOW_LSB _u(28) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_HIGH -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_HIGH_BITS _u(0x08000000) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_HIGH_MSB _u(27) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_HIGH_LSB _u(27) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_LOW -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_LOW_BITS _u(0x04000000) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_LOW_MSB _u(26) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_LOW_LSB _u(26) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_HIGH -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_BITS _u(0x02000000) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_MSB _u(25) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_LSB _u(25) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_LOW -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_LOW_BITS _u(0x01000000) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_LOW_MSB _u(24) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_LOW_LSB _u(24) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_HIGH -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_HIGH_BITS _u(0x00800000) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_HIGH_MSB _u(23) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_HIGH_LSB _u(23) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_LOW -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_LOW_BITS _u(0x00400000) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_LOW_MSB _u(22) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_LOW_LSB _u(22) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_HIGH -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_BITS _u(0x00200000) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_MSB _u(21) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_LSB _u(21) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_LOW -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_LOW_BITS _u(0x00100000) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_LOW_MSB _u(20) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_LOW_LSB _u(20) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_HIGH -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_HIGH_BITS _u(0x00080000) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_HIGH_MSB _u(19) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_HIGH_LSB _u(19) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_LOW -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_LOW_BITS _u(0x00040000) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_LOW_MSB _u(18) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_LOW_LSB _u(18) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_HIGH -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_BITS _u(0x00020000) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_MSB _u(17) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_LSB _u(17) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_LOW -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_LOW_BITS _u(0x00010000) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_LOW_MSB _u(16) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_LOW_LSB _u(16) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_HIGH -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_HIGH_BITS _u(0x00008000) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_HIGH_MSB _u(15) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_HIGH_LSB _u(15) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_LOW -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_LOW_BITS _u(0x00004000) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_LOW_MSB _u(14) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_LOW_LSB _u(14) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_HIGH -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_HIGH_BITS _u(0x00002000) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_HIGH_MSB _u(13) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_HIGH_LSB _u(13) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_LOW -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_LOW_BITS _u(0x00001000) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_LOW_MSB _u(12) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_LOW_LSB _u(12) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_HIGH -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_BITS _u(0x00000800) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_MSB _u(11) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_LSB _u(11) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_LOW -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_LOW_BITS _u(0x00000400) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_LOW_MSB _u(10) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_LOW_LSB _u(10) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS _u(0x00000200) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB _u(9) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB _u(9) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_LOW -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_BITS _u(0x00000100) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_MSB _u(8) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_LSB _u(8) -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DM_EDGE_HIGH -#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DM_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DM_EDGE_HIGH_BITS _u(0x00000080) -#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DM_EDGE_HIGH_MSB _u(7) -#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DM_EDGE_HIGH_LSB _u(7) -#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DM_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DM_EDGE_LOW -#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DM_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DM_EDGE_LOW_BITS _u(0x00000040) -#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DM_EDGE_LOW_MSB _u(6) -#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DM_EDGE_LOW_LSB _u(6) -#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DM_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DM_LEVEL_HIGH -#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DM_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DM_LEVEL_HIGH_BITS _u(0x00000020) -#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DM_LEVEL_HIGH_MSB _u(5) -#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DM_LEVEL_HIGH_LSB _u(5) -#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DM_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DM_LEVEL_LOW -#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DM_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DM_LEVEL_LOW_BITS _u(0x00000010) -#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DM_LEVEL_LOW_MSB _u(4) -#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DM_LEVEL_LOW_LSB _u(4) -#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DM_LEVEL_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DP_EDGE_HIGH -#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DP_EDGE_HIGH_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DP_EDGE_HIGH_BITS _u(0x00000008) -#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DP_EDGE_HIGH_MSB _u(3) -#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DP_EDGE_HIGH_LSB _u(3) -#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DP_EDGE_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DP_EDGE_LOW -#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DP_EDGE_LOW_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DP_EDGE_LOW_BITS _u(0x00000004) -#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DP_EDGE_LOW_MSB _u(2) -#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DP_EDGE_LOW_LSB _u(2) -#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DP_EDGE_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DP_LEVEL_HIGH -#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DP_LEVEL_HIGH_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DP_LEVEL_HIGH_BITS _u(0x00000002) -#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DP_LEVEL_HIGH_MSB _u(1) -#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DP_LEVEL_HIGH_LSB _u(1) -#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DP_LEVEL_HIGH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DP_LEVEL_LOW -#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DP_LEVEL_LOW_RESET _u(0x0) -#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DP_LEVEL_LOW_BITS _u(0x00000001) -#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DP_LEVEL_LOW_MSB _u(0) -#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DP_LEVEL_LOW_LSB _u(0) -#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DP_LEVEL_LOW_ACCESS "RO" -// ============================================================================= -#endif // _HARDWARE_REGS_IO_QSPI_H - diff --git a/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/m33.h b/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/m33.h deleted file mode 100644 index b555317dec..0000000000 --- a/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/m33.h +++ /dev/null @@ -1,8988 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -// ============================================================================= -// Register block : M33 -// Version : 1 -// Bus type : apb -// Description : TEAL registers accessible through the debug interface -// ============================================================================= -#ifndef _HARDWARE_REGS_M33_H -#define _HARDWARE_REGS_M33_H -// ============================================================================= -// Register : M33_ITM_STIM0 -// Description : Provides the interface for generating Instrumentation packets -#define M33_ITM_STIM0_OFFSET _u(0x00000000) -#define M33_ITM_STIM0_BITS _u(0xffffffff) -#define M33_ITM_STIM0_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_ITM_STIM0_STIMULUS -// Description : Data to write to the Stimulus Port FIFO, for forwarding as an -// Instrumentation packet. The size of write access determines the -// type of Instrumentation packet generated. -#define M33_ITM_STIM0_STIMULUS_RESET _u(0x00000000) -#define M33_ITM_STIM0_STIMULUS_BITS _u(0xffffffff) -#define M33_ITM_STIM0_STIMULUS_MSB _u(31) -#define M33_ITM_STIM0_STIMULUS_LSB _u(0) -#define M33_ITM_STIM0_STIMULUS_ACCESS "RW" -// ============================================================================= -// Register : M33_ITM_STIM1 -// Description : Provides the interface for generating Instrumentation packets -#define M33_ITM_STIM1_OFFSET _u(0x00000004) -#define M33_ITM_STIM1_BITS _u(0xffffffff) -#define M33_ITM_STIM1_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_ITM_STIM1_STIMULUS -// Description : Data to write to the Stimulus Port FIFO, for forwarding as an -// Instrumentation packet. The size of write access determines the -// type of Instrumentation packet generated. -#define M33_ITM_STIM1_STIMULUS_RESET _u(0x00000000) -#define M33_ITM_STIM1_STIMULUS_BITS _u(0xffffffff) -#define M33_ITM_STIM1_STIMULUS_MSB _u(31) -#define M33_ITM_STIM1_STIMULUS_LSB _u(0) -#define M33_ITM_STIM1_STIMULUS_ACCESS "RW" -// ============================================================================= -// Register : M33_ITM_STIM2 -// Description : Provides the interface for generating Instrumentation packets -#define M33_ITM_STIM2_OFFSET _u(0x00000008) -#define M33_ITM_STIM2_BITS _u(0xffffffff) -#define M33_ITM_STIM2_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_ITM_STIM2_STIMULUS -// Description : Data to write to the Stimulus Port FIFO, for forwarding as an -// Instrumentation packet. The size of write access determines the -// type of Instrumentation packet generated. -#define M33_ITM_STIM2_STIMULUS_RESET _u(0x00000000) -#define M33_ITM_STIM2_STIMULUS_BITS _u(0xffffffff) -#define M33_ITM_STIM2_STIMULUS_MSB _u(31) -#define M33_ITM_STIM2_STIMULUS_LSB _u(0) -#define M33_ITM_STIM2_STIMULUS_ACCESS "RW" -// ============================================================================= -// Register : M33_ITM_STIM3 -// Description : Provides the interface for generating Instrumentation packets -#define M33_ITM_STIM3_OFFSET _u(0x0000000c) -#define M33_ITM_STIM3_BITS _u(0xffffffff) -#define M33_ITM_STIM3_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_ITM_STIM3_STIMULUS -// Description : Data to write to the Stimulus Port FIFO, for forwarding as an -// Instrumentation packet. The size of write access determines the -// type of Instrumentation packet generated. -#define M33_ITM_STIM3_STIMULUS_RESET _u(0x00000000) -#define M33_ITM_STIM3_STIMULUS_BITS _u(0xffffffff) -#define M33_ITM_STIM3_STIMULUS_MSB _u(31) -#define M33_ITM_STIM3_STIMULUS_LSB _u(0) -#define M33_ITM_STIM3_STIMULUS_ACCESS "RW" -// ============================================================================= -// Register : M33_ITM_STIM4 -// Description : Provides the interface for generating Instrumentation packets -#define M33_ITM_STIM4_OFFSET _u(0x00000010) -#define M33_ITM_STIM4_BITS _u(0xffffffff) -#define M33_ITM_STIM4_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_ITM_STIM4_STIMULUS -// Description : Data to write to the Stimulus Port FIFO, for forwarding as an -// Instrumentation packet. The size of write access determines the -// type of Instrumentation packet generated. -#define M33_ITM_STIM4_STIMULUS_RESET _u(0x00000000) -#define M33_ITM_STIM4_STIMULUS_BITS _u(0xffffffff) -#define M33_ITM_STIM4_STIMULUS_MSB _u(31) -#define M33_ITM_STIM4_STIMULUS_LSB _u(0) -#define M33_ITM_STIM4_STIMULUS_ACCESS "RW" -// ============================================================================= -// Register : M33_ITM_STIM5 -// Description : Provides the interface for generating Instrumentation packets -#define M33_ITM_STIM5_OFFSET _u(0x00000014) -#define M33_ITM_STIM5_BITS _u(0xffffffff) -#define M33_ITM_STIM5_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_ITM_STIM5_STIMULUS -// Description : Data to write to the Stimulus Port FIFO, for forwarding as an -// Instrumentation packet. The size of write access determines the -// type of Instrumentation packet generated. -#define M33_ITM_STIM5_STIMULUS_RESET _u(0x00000000) -#define M33_ITM_STIM5_STIMULUS_BITS _u(0xffffffff) -#define M33_ITM_STIM5_STIMULUS_MSB _u(31) -#define M33_ITM_STIM5_STIMULUS_LSB _u(0) -#define M33_ITM_STIM5_STIMULUS_ACCESS "RW" -// ============================================================================= -// Register : M33_ITM_STIM6 -// Description : Provides the interface for generating Instrumentation packets -#define M33_ITM_STIM6_OFFSET _u(0x00000018) -#define M33_ITM_STIM6_BITS _u(0xffffffff) -#define M33_ITM_STIM6_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_ITM_STIM6_STIMULUS -// Description : Data to write to the Stimulus Port FIFO, for forwarding as an -// Instrumentation packet. The size of write access determines the -// type of Instrumentation packet generated. -#define M33_ITM_STIM6_STIMULUS_RESET _u(0x00000000) -#define M33_ITM_STIM6_STIMULUS_BITS _u(0xffffffff) -#define M33_ITM_STIM6_STIMULUS_MSB _u(31) -#define M33_ITM_STIM6_STIMULUS_LSB _u(0) -#define M33_ITM_STIM6_STIMULUS_ACCESS "RW" -// ============================================================================= -// Register : M33_ITM_STIM7 -// Description : Provides the interface for generating Instrumentation packets -#define M33_ITM_STIM7_OFFSET _u(0x0000001c) -#define M33_ITM_STIM7_BITS _u(0xffffffff) -#define M33_ITM_STIM7_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_ITM_STIM7_STIMULUS -// Description : Data to write to the Stimulus Port FIFO, for forwarding as an -// Instrumentation packet. The size of write access determines the -// type of Instrumentation packet generated. -#define M33_ITM_STIM7_STIMULUS_RESET _u(0x00000000) -#define M33_ITM_STIM7_STIMULUS_BITS _u(0xffffffff) -#define M33_ITM_STIM7_STIMULUS_MSB _u(31) -#define M33_ITM_STIM7_STIMULUS_LSB _u(0) -#define M33_ITM_STIM7_STIMULUS_ACCESS "RW" -// ============================================================================= -// Register : M33_ITM_STIM8 -// Description : Provides the interface for generating Instrumentation packets -#define M33_ITM_STIM8_OFFSET _u(0x00000020) -#define M33_ITM_STIM8_BITS _u(0xffffffff) -#define M33_ITM_STIM8_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_ITM_STIM8_STIMULUS -// Description : Data to write to the Stimulus Port FIFO, for forwarding as an -// Instrumentation packet. The size of write access determines the -// type of Instrumentation packet generated. -#define M33_ITM_STIM8_STIMULUS_RESET _u(0x00000000) -#define M33_ITM_STIM8_STIMULUS_BITS _u(0xffffffff) -#define M33_ITM_STIM8_STIMULUS_MSB _u(31) -#define M33_ITM_STIM8_STIMULUS_LSB _u(0) -#define M33_ITM_STIM8_STIMULUS_ACCESS "RW" -// ============================================================================= -// Register : M33_ITM_STIM9 -// Description : Provides the interface for generating Instrumentation packets -#define M33_ITM_STIM9_OFFSET _u(0x00000024) -#define M33_ITM_STIM9_BITS _u(0xffffffff) -#define M33_ITM_STIM9_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_ITM_STIM9_STIMULUS -// Description : Data to write to the Stimulus Port FIFO, for forwarding as an -// Instrumentation packet. The size of write access determines the -// type of Instrumentation packet generated. -#define M33_ITM_STIM9_STIMULUS_RESET _u(0x00000000) -#define M33_ITM_STIM9_STIMULUS_BITS _u(0xffffffff) -#define M33_ITM_STIM9_STIMULUS_MSB _u(31) -#define M33_ITM_STIM9_STIMULUS_LSB _u(0) -#define M33_ITM_STIM9_STIMULUS_ACCESS "RW" -// ============================================================================= -// Register : M33_ITM_STIM10 -// Description : Provides the interface for generating Instrumentation packets -#define M33_ITM_STIM10_OFFSET _u(0x00000028) -#define M33_ITM_STIM10_BITS _u(0xffffffff) -#define M33_ITM_STIM10_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_ITM_STIM10_STIMULUS -// Description : Data to write to the Stimulus Port FIFO, for forwarding as an -// Instrumentation packet. The size of write access determines the -// type of Instrumentation packet generated. -#define M33_ITM_STIM10_STIMULUS_RESET _u(0x00000000) -#define M33_ITM_STIM10_STIMULUS_BITS _u(0xffffffff) -#define M33_ITM_STIM10_STIMULUS_MSB _u(31) -#define M33_ITM_STIM10_STIMULUS_LSB _u(0) -#define M33_ITM_STIM10_STIMULUS_ACCESS "RW" -// ============================================================================= -// Register : M33_ITM_STIM11 -// Description : Provides the interface for generating Instrumentation packets -#define M33_ITM_STIM11_OFFSET _u(0x0000002c) -#define M33_ITM_STIM11_BITS _u(0xffffffff) -#define M33_ITM_STIM11_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_ITM_STIM11_STIMULUS -// Description : Data to write to the Stimulus Port FIFO, for forwarding as an -// Instrumentation packet. The size of write access determines the -// type of Instrumentation packet generated. -#define M33_ITM_STIM11_STIMULUS_RESET _u(0x00000000) -#define M33_ITM_STIM11_STIMULUS_BITS _u(0xffffffff) -#define M33_ITM_STIM11_STIMULUS_MSB _u(31) -#define M33_ITM_STIM11_STIMULUS_LSB _u(0) -#define M33_ITM_STIM11_STIMULUS_ACCESS "RW" -// ============================================================================= -// Register : M33_ITM_STIM12 -// Description : Provides the interface for generating Instrumentation packets -#define M33_ITM_STIM12_OFFSET _u(0x00000030) -#define M33_ITM_STIM12_BITS _u(0xffffffff) -#define M33_ITM_STIM12_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_ITM_STIM12_STIMULUS -// Description : Data to write to the Stimulus Port FIFO, for forwarding as an -// Instrumentation packet. The size of write access determines the -// type of Instrumentation packet generated. -#define M33_ITM_STIM12_STIMULUS_RESET _u(0x00000000) -#define M33_ITM_STIM12_STIMULUS_BITS _u(0xffffffff) -#define M33_ITM_STIM12_STIMULUS_MSB _u(31) -#define M33_ITM_STIM12_STIMULUS_LSB _u(0) -#define M33_ITM_STIM12_STIMULUS_ACCESS "RW" -// ============================================================================= -// Register : M33_ITM_STIM13 -// Description : Provides the interface for generating Instrumentation packets -#define M33_ITM_STIM13_OFFSET _u(0x00000034) -#define M33_ITM_STIM13_BITS _u(0xffffffff) -#define M33_ITM_STIM13_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_ITM_STIM13_STIMULUS -// Description : Data to write to the Stimulus Port FIFO, for forwarding as an -// Instrumentation packet. The size of write access determines the -// type of Instrumentation packet generated. -#define M33_ITM_STIM13_STIMULUS_RESET _u(0x00000000) -#define M33_ITM_STIM13_STIMULUS_BITS _u(0xffffffff) -#define M33_ITM_STIM13_STIMULUS_MSB _u(31) -#define M33_ITM_STIM13_STIMULUS_LSB _u(0) -#define M33_ITM_STIM13_STIMULUS_ACCESS "RW" -// ============================================================================= -// Register : M33_ITM_STIM14 -// Description : Provides the interface for generating Instrumentation packets -#define M33_ITM_STIM14_OFFSET _u(0x00000038) -#define M33_ITM_STIM14_BITS _u(0xffffffff) -#define M33_ITM_STIM14_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_ITM_STIM14_STIMULUS -// Description : Data to write to the Stimulus Port FIFO, for forwarding as an -// Instrumentation packet. The size of write access determines the -// type of Instrumentation packet generated. -#define M33_ITM_STIM14_STIMULUS_RESET _u(0x00000000) -#define M33_ITM_STIM14_STIMULUS_BITS _u(0xffffffff) -#define M33_ITM_STIM14_STIMULUS_MSB _u(31) -#define M33_ITM_STIM14_STIMULUS_LSB _u(0) -#define M33_ITM_STIM14_STIMULUS_ACCESS "RW" -// ============================================================================= -// Register : M33_ITM_STIM15 -// Description : Provides the interface for generating Instrumentation packets -#define M33_ITM_STIM15_OFFSET _u(0x0000003c) -#define M33_ITM_STIM15_BITS _u(0xffffffff) -#define M33_ITM_STIM15_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_ITM_STIM15_STIMULUS -// Description : Data to write to the Stimulus Port FIFO, for forwarding as an -// Instrumentation packet. The size of write access determines the -// type of Instrumentation packet generated. -#define M33_ITM_STIM15_STIMULUS_RESET _u(0x00000000) -#define M33_ITM_STIM15_STIMULUS_BITS _u(0xffffffff) -#define M33_ITM_STIM15_STIMULUS_MSB _u(31) -#define M33_ITM_STIM15_STIMULUS_LSB _u(0) -#define M33_ITM_STIM15_STIMULUS_ACCESS "RW" -// ============================================================================= -// Register : M33_ITM_STIM16 -// Description : Provides the interface for generating Instrumentation packets -#define M33_ITM_STIM16_OFFSET _u(0x00000040) -#define M33_ITM_STIM16_BITS _u(0xffffffff) -#define M33_ITM_STIM16_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_ITM_STIM16_STIMULUS -// Description : Data to write to the Stimulus Port FIFO, for forwarding as an -// Instrumentation packet. The size of write access determines the -// type of Instrumentation packet generated. -#define M33_ITM_STIM16_STIMULUS_RESET _u(0x00000000) -#define M33_ITM_STIM16_STIMULUS_BITS _u(0xffffffff) -#define M33_ITM_STIM16_STIMULUS_MSB _u(31) -#define M33_ITM_STIM16_STIMULUS_LSB _u(0) -#define M33_ITM_STIM16_STIMULUS_ACCESS "RW" -// ============================================================================= -// Register : M33_ITM_STIM17 -// Description : Provides the interface for generating Instrumentation packets -#define M33_ITM_STIM17_OFFSET _u(0x00000044) -#define M33_ITM_STIM17_BITS _u(0xffffffff) -#define M33_ITM_STIM17_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_ITM_STIM17_STIMULUS -// Description : Data to write to the Stimulus Port FIFO, for forwarding as an -// Instrumentation packet. The size of write access determines the -// type of Instrumentation packet generated. -#define M33_ITM_STIM17_STIMULUS_RESET _u(0x00000000) -#define M33_ITM_STIM17_STIMULUS_BITS _u(0xffffffff) -#define M33_ITM_STIM17_STIMULUS_MSB _u(31) -#define M33_ITM_STIM17_STIMULUS_LSB _u(0) -#define M33_ITM_STIM17_STIMULUS_ACCESS "RW" -// ============================================================================= -// Register : M33_ITM_STIM18 -// Description : Provides the interface for generating Instrumentation packets -#define M33_ITM_STIM18_OFFSET _u(0x00000048) -#define M33_ITM_STIM18_BITS _u(0xffffffff) -#define M33_ITM_STIM18_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_ITM_STIM18_STIMULUS -// Description : Data to write to the Stimulus Port FIFO, for forwarding as an -// Instrumentation packet. The size of write access determines the -// type of Instrumentation packet generated. -#define M33_ITM_STIM18_STIMULUS_RESET _u(0x00000000) -#define M33_ITM_STIM18_STIMULUS_BITS _u(0xffffffff) -#define M33_ITM_STIM18_STIMULUS_MSB _u(31) -#define M33_ITM_STIM18_STIMULUS_LSB _u(0) -#define M33_ITM_STIM18_STIMULUS_ACCESS "RW" -// ============================================================================= -// Register : M33_ITM_STIM19 -// Description : Provides the interface for generating Instrumentation packets -#define M33_ITM_STIM19_OFFSET _u(0x0000004c) -#define M33_ITM_STIM19_BITS _u(0xffffffff) -#define M33_ITM_STIM19_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_ITM_STIM19_STIMULUS -// Description : Data to write to the Stimulus Port FIFO, for forwarding as an -// Instrumentation packet. The size of write access determines the -// type of Instrumentation packet generated. -#define M33_ITM_STIM19_STIMULUS_RESET _u(0x00000000) -#define M33_ITM_STIM19_STIMULUS_BITS _u(0xffffffff) -#define M33_ITM_STIM19_STIMULUS_MSB _u(31) -#define M33_ITM_STIM19_STIMULUS_LSB _u(0) -#define M33_ITM_STIM19_STIMULUS_ACCESS "RW" -// ============================================================================= -// Register : M33_ITM_STIM20 -// Description : Provides the interface for generating Instrumentation packets -#define M33_ITM_STIM20_OFFSET _u(0x00000050) -#define M33_ITM_STIM20_BITS _u(0xffffffff) -#define M33_ITM_STIM20_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_ITM_STIM20_STIMULUS -// Description : Data to write to the Stimulus Port FIFO, for forwarding as an -// Instrumentation packet. The size of write access determines the -// type of Instrumentation packet generated. -#define M33_ITM_STIM20_STIMULUS_RESET _u(0x00000000) -#define M33_ITM_STIM20_STIMULUS_BITS _u(0xffffffff) -#define M33_ITM_STIM20_STIMULUS_MSB _u(31) -#define M33_ITM_STIM20_STIMULUS_LSB _u(0) -#define M33_ITM_STIM20_STIMULUS_ACCESS "RW" -// ============================================================================= -// Register : M33_ITM_STIM21 -// Description : Provides the interface for generating Instrumentation packets -#define M33_ITM_STIM21_OFFSET _u(0x00000054) -#define M33_ITM_STIM21_BITS _u(0xffffffff) -#define M33_ITM_STIM21_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_ITM_STIM21_STIMULUS -// Description : Data to write to the Stimulus Port FIFO, for forwarding as an -// Instrumentation packet. The size of write access determines the -// type of Instrumentation packet generated. -#define M33_ITM_STIM21_STIMULUS_RESET _u(0x00000000) -#define M33_ITM_STIM21_STIMULUS_BITS _u(0xffffffff) -#define M33_ITM_STIM21_STIMULUS_MSB _u(31) -#define M33_ITM_STIM21_STIMULUS_LSB _u(0) -#define M33_ITM_STIM21_STIMULUS_ACCESS "RW" -// ============================================================================= -// Register : M33_ITM_STIM22 -// Description : Provides the interface for generating Instrumentation packets -#define M33_ITM_STIM22_OFFSET _u(0x00000058) -#define M33_ITM_STIM22_BITS _u(0xffffffff) -#define M33_ITM_STIM22_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_ITM_STIM22_STIMULUS -// Description : Data to write to the Stimulus Port FIFO, for forwarding as an -// Instrumentation packet. The size of write access determines the -// type of Instrumentation packet generated. -#define M33_ITM_STIM22_STIMULUS_RESET _u(0x00000000) -#define M33_ITM_STIM22_STIMULUS_BITS _u(0xffffffff) -#define M33_ITM_STIM22_STIMULUS_MSB _u(31) -#define M33_ITM_STIM22_STIMULUS_LSB _u(0) -#define M33_ITM_STIM22_STIMULUS_ACCESS "RW" -// ============================================================================= -// Register : M33_ITM_STIM23 -// Description : Provides the interface for generating Instrumentation packets -#define M33_ITM_STIM23_OFFSET _u(0x0000005c) -#define M33_ITM_STIM23_BITS _u(0xffffffff) -#define M33_ITM_STIM23_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_ITM_STIM23_STIMULUS -// Description : Data to write to the Stimulus Port FIFO, for forwarding as an -// Instrumentation packet. The size of write access determines the -// type of Instrumentation packet generated. -#define M33_ITM_STIM23_STIMULUS_RESET _u(0x00000000) -#define M33_ITM_STIM23_STIMULUS_BITS _u(0xffffffff) -#define M33_ITM_STIM23_STIMULUS_MSB _u(31) -#define M33_ITM_STIM23_STIMULUS_LSB _u(0) -#define M33_ITM_STIM23_STIMULUS_ACCESS "RW" -// ============================================================================= -// Register : M33_ITM_STIM24 -// Description : Provides the interface for generating Instrumentation packets -#define M33_ITM_STIM24_OFFSET _u(0x00000060) -#define M33_ITM_STIM24_BITS _u(0xffffffff) -#define M33_ITM_STIM24_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_ITM_STIM24_STIMULUS -// Description : Data to write to the Stimulus Port FIFO, for forwarding as an -// Instrumentation packet. The size of write access determines the -// type of Instrumentation packet generated. -#define M33_ITM_STIM24_STIMULUS_RESET _u(0x00000000) -#define M33_ITM_STIM24_STIMULUS_BITS _u(0xffffffff) -#define M33_ITM_STIM24_STIMULUS_MSB _u(31) -#define M33_ITM_STIM24_STIMULUS_LSB _u(0) -#define M33_ITM_STIM24_STIMULUS_ACCESS "RW" -// ============================================================================= -// Register : M33_ITM_STIM25 -// Description : Provides the interface for generating Instrumentation packets -#define M33_ITM_STIM25_OFFSET _u(0x00000064) -#define M33_ITM_STIM25_BITS _u(0xffffffff) -#define M33_ITM_STIM25_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_ITM_STIM25_STIMULUS -// Description : Data to write to the Stimulus Port FIFO, for forwarding as an -// Instrumentation packet. The size of write access determines the -// type of Instrumentation packet generated. -#define M33_ITM_STIM25_STIMULUS_RESET _u(0x00000000) -#define M33_ITM_STIM25_STIMULUS_BITS _u(0xffffffff) -#define M33_ITM_STIM25_STIMULUS_MSB _u(31) -#define M33_ITM_STIM25_STIMULUS_LSB _u(0) -#define M33_ITM_STIM25_STIMULUS_ACCESS "RW" -// ============================================================================= -// Register : M33_ITM_STIM26 -// Description : Provides the interface for generating Instrumentation packets -#define M33_ITM_STIM26_OFFSET _u(0x00000068) -#define M33_ITM_STIM26_BITS _u(0xffffffff) -#define M33_ITM_STIM26_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_ITM_STIM26_STIMULUS -// Description : Data to write to the Stimulus Port FIFO, for forwarding as an -// Instrumentation packet. The size of write access determines the -// type of Instrumentation packet generated. -#define M33_ITM_STIM26_STIMULUS_RESET _u(0x00000000) -#define M33_ITM_STIM26_STIMULUS_BITS _u(0xffffffff) -#define M33_ITM_STIM26_STIMULUS_MSB _u(31) -#define M33_ITM_STIM26_STIMULUS_LSB _u(0) -#define M33_ITM_STIM26_STIMULUS_ACCESS "RW" -// ============================================================================= -// Register : M33_ITM_STIM27 -// Description : Provides the interface for generating Instrumentation packets -#define M33_ITM_STIM27_OFFSET _u(0x0000006c) -#define M33_ITM_STIM27_BITS _u(0xffffffff) -#define M33_ITM_STIM27_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_ITM_STIM27_STIMULUS -// Description : Data to write to the Stimulus Port FIFO, for forwarding as an -// Instrumentation packet. The size of write access determines the -// type of Instrumentation packet generated. -#define M33_ITM_STIM27_STIMULUS_RESET _u(0x00000000) -#define M33_ITM_STIM27_STIMULUS_BITS _u(0xffffffff) -#define M33_ITM_STIM27_STIMULUS_MSB _u(31) -#define M33_ITM_STIM27_STIMULUS_LSB _u(0) -#define M33_ITM_STIM27_STIMULUS_ACCESS "RW" -// ============================================================================= -// Register : M33_ITM_STIM28 -// Description : Provides the interface for generating Instrumentation packets -#define M33_ITM_STIM28_OFFSET _u(0x00000070) -#define M33_ITM_STIM28_BITS _u(0xffffffff) -#define M33_ITM_STIM28_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_ITM_STIM28_STIMULUS -// Description : Data to write to the Stimulus Port FIFO, for forwarding as an -// Instrumentation packet. The size of write access determines the -// type of Instrumentation packet generated. -#define M33_ITM_STIM28_STIMULUS_RESET _u(0x00000000) -#define M33_ITM_STIM28_STIMULUS_BITS _u(0xffffffff) -#define M33_ITM_STIM28_STIMULUS_MSB _u(31) -#define M33_ITM_STIM28_STIMULUS_LSB _u(0) -#define M33_ITM_STIM28_STIMULUS_ACCESS "RW" -// ============================================================================= -// Register : M33_ITM_STIM29 -// Description : Provides the interface for generating Instrumentation packets -#define M33_ITM_STIM29_OFFSET _u(0x00000074) -#define M33_ITM_STIM29_BITS _u(0xffffffff) -#define M33_ITM_STIM29_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_ITM_STIM29_STIMULUS -// Description : Data to write to the Stimulus Port FIFO, for forwarding as an -// Instrumentation packet. The size of write access determines the -// type of Instrumentation packet generated. -#define M33_ITM_STIM29_STIMULUS_RESET _u(0x00000000) -#define M33_ITM_STIM29_STIMULUS_BITS _u(0xffffffff) -#define M33_ITM_STIM29_STIMULUS_MSB _u(31) -#define M33_ITM_STIM29_STIMULUS_LSB _u(0) -#define M33_ITM_STIM29_STIMULUS_ACCESS "RW" -// ============================================================================= -// Register : M33_ITM_STIM30 -// Description : Provides the interface for generating Instrumentation packets -#define M33_ITM_STIM30_OFFSET _u(0x00000078) -#define M33_ITM_STIM30_BITS _u(0xffffffff) -#define M33_ITM_STIM30_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_ITM_STIM30_STIMULUS -// Description : Data to write to the Stimulus Port FIFO, for forwarding as an -// Instrumentation packet. The size of write access determines the -// type of Instrumentation packet generated. -#define M33_ITM_STIM30_STIMULUS_RESET _u(0x00000000) -#define M33_ITM_STIM30_STIMULUS_BITS _u(0xffffffff) -#define M33_ITM_STIM30_STIMULUS_MSB _u(31) -#define M33_ITM_STIM30_STIMULUS_LSB _u(0) -#define M33_ITM_STIM30_STIMULUS_ACCESS "RW" -// ============================================================================= -// Register : M33_ITM_STIM31 -// Description : Provides the interface for generating Instrumentation packets -#define M33_ITM_STIM31_OFFSET _u(0x0000007c) -#define M33_ITM_STIM31_BITS _u(0xffffffff) -#define M33_ITM_STIM31_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_ITM_STIM31_STIMULUS -// Description : Data to write to the Stimulus Port FIFO, for forwarding as an -// Instrumentation packet. The size of write access determines the -// type of Instrumentation packet generated. -#define M33_ITM_STIM31_STIMULUS_RESET _u(0x00000000) -#define M33_ITM_STIM31_STIMULUS_BITS _u(0xffffffff) -#define M33_ITM_STIM31_STIMULUS_MSB _u(31) -#define M33_ITM_STIM31_STIMULUS_LSB _u(0) -#define M33_ITM_STIM31_STIMULUS_ACCESS "RW" -// ============================================================================= -// Register : M33_ITM_TER0 -// Description : Provide an individual enable bit for each ITM_STIM register -#define M33_ITM_TER0_OFFSET _u(0x00000e00) -#define M33_ITM_TER0_BITS _u(0xffffffff) -#define M33_ITM_TER0_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_ITM_TER0_STIMENA -// Description : For STIMENA[m] in ITM_TER*n, controls whether ITM_STIM(32*n + -// m) is enabled -#define M33_ITM_TER0_STIMENA_RESET _u(0x00000000) -#define M33_ITM_TER0_STIMENA_BITS _u(0xffffffff) -#define M33_ITM_TER0_STIMENA_MSB _u(31) -#define M33_ITM_TER0_STIMENA_LSB _u(0) -#define M33_ITM_TER0_STIMENA_ACCESS "RW" -// ============================================================================= -// Register : M33_ITM_TPR -// Description : Controls which stimulus ports can be accessed by unprivileged -// code -#define M33_ITM_TPR_OFFSET _u(0x00000e40) -#define M33_ITM_TPR_BITS _u(0x0000000f) -#define M33_ITM_TPR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_ITM_TPR_PRIVMASK -// Description : Bit mask to enable tracing on ITM stimulus ports -#define M33_ITM_TPR_PRIVMASK_RESET _u(0x0) -#define M33_ITM_TPR_PRIVMASK_BITS _u(0x0000000f) -#define M33_ITM_TPR_PRIVMASK_MSB _u(3) -#define M33_ITM_TPR_PRIVMASK_LSB _u(0) -#define M33_ITM_TPR_PRIVMASK_ACCESS "RW" -// ============================================================================= -// Register : M33_ITM_TCR -// Description : Configures and controls transfers through the ITM interface -#define M33_ITM_TCR_OFFSET _u(0x00000e80) -#define M33_ITM_TCR_BITS _u(0x00ff0f3f) -#define M33_ITM_TCR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_ITM_TCR_BUSY -// Description : Indicates whether the ITM is currently processing events -#define M33_ITM_TCR_BUSY_RESET _u(0x0) -#define M33_ITM_TCR_BUSY_BITS _u(0x00800000) -#define M33_ITM_TCR_BUSY_MSB _u(23) -#define M33_ITM_TCR_BUSY_LSB _u(23) -#define M33_ITM_TCR_BUSY_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_ITM_TCR_TRACEBUSID -// Description : Identifier for multi-source trace stream formatting. If multi- -// source trace is in use, the debugger must write a unique non- -// zero trace ID value to this field -#define M33_ITM_TCR_TRACEBUSID_RESET _u(0x00) -#define M33_ITM_TCR_TRACEBUSID_BITS _u(0x007f0000) -#define M33_ITM_TCR_TRACEBUSID_MSB _u(22) -#define M33_ITM_TCR_TRACEBUSID_LSB _u(16) -#define M33_ITM_TCR_TRACEBUSID_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_ITM_TCR_GTSFREQ -// Description : Defines how often the ITM generates a global timestamp, based -// on the global timestamp clock frequency, or disables generation -// of global timestamps -#define M33_ITM_TCR_GTSFREQ_RESET _u(0x0) -#define M33_ITM_TCR_GTSFREQ_BITS _u(0x00000c00) -#define M33_ITM_TCR_GTSFREQ_MSB _u(11) -#define M33_ITM_TCR_GTSFREQ_LSB _u(10) -#define M33_ITM_TCR_GTSFREQ_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_ITM_TCR_TSPRESCALE -// Description : Local timestamp prescaler, used with the trace packet reference -// clock -#define M33_ITM_TCR_TSPRESCALE_RESET _u(0x0) -#define M33_ITM_TCR_TSPRESCALE_BITS _u(0x00000300) -#define M33_ITM_TCR_TSPRESCALE_MSB _u(9) -#define M33_ITM_TCR_TSPRESCALE_LSB _u(8) -#define M33_ITM_TCR_TSPRESCALE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_ITM_TCR_STALLENA -// Description : Stall the PE to guarantee delivery of Data Trace packets. -#define M33_ITM_TCR_STALLENA_RESET _u(0x0) -#define M33_ITM_TCR_STALLENA_BITS _u(0x00000020) -#define M33_ITM_TCR_STALLENA_MSB _u(5) -#define M33_ITM_TCR_STALLENA_LSB _u(5) -#define M33_ITM_TCR_STALLENA_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_ITM_TCR_SWOENA -// Description : Enables asynchronous clocking of the timestamp counter -#define M33_ITM_TCR_SWOENA_RESET _u(0x0) -#define M33_ITM_TCR_SWOENA_BITS _u(0x00000010) -#define M33_ITM_TCR_SWOENA_MSB _u(4) -#define M33_ITM_TCR_SWOENA_LSB _u(4) -#define M33_ITM_TCR_SWOENA_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_ITM_TCR_TXENA -// Description : Enables forwarding of hardware event packet from the DWT unit -// to the ITM for output to the TPIU -#define M33_ITM_TCR_TXENA_RESET _u(0x0) -#define M33_ITM_TCR_TXENA_BITS _u(0x00000008) -#define M33_ITM_TCR_TXENA_MSB _u(3) -#define M33_ITM_TCR_TXENA_LSB _u(3) -#define M33_ITM_TCR_TXENA_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_ITM_TCR_SYNCENA -// Description : Enables Synchronization packet transmission for a synchronous -// TPIU -#define M33_ITM_TCR_SYNCENA_RESET _u(0x0) -#define M33_ITM_TCR_SYNCENA_BITS _u(0x00000004) -#define M33_ITM_TCR_SYNCENA_MSB _u(2) -#define M33_ITM_TCR_SYNCENA_LSB _u(2) -#define M33_ITM_TCR_SYNCENA_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_ITM_TCR_TSENA -// Description : Enables Local timestamp generation -#define M33_ITM_TCR_TSENA_RESET _u(0x0) -#define M33_ITM_TCR_TSENA_BITS _u(0x00000002) -#define M33_ITM_TCR_TSENA_MSB _u(1) -#define M33_ITM_TCR_TSENA_LSB _u(1) -#define M33_ITM_TCR_TSENA_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_ITM_TCR_ITMENA -// Description : Enables the ITM -#define M33_ITM_TCR_ITMENA_RESET _u(0x0) -#define M33_ITM_TCR_ITMENA_BITS _u(0x00000001) -#define M33_ITM_TCR_ITMENA_MSB _u(0) -#define M33_ITM_TCR_ITMENA_LSB _u(0) -#define M33_ITM_TCR_ITMENA_ACCESS "RW" -// ============================================================================= -// Register : M33_INT_ATREADY -// Description : Integration Mode: Read ATB Ready -#define M33_INT_ATREADY_OFFSET _u(0x00000ef0) -#define M33_INT_ATREADY_BITS _u(0x00000003) -#define M33_INT_ATREADY_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_INT_ATREADY_AFVALID -// Description : A read of this bit returns the value of AFVALID -#define M33_INT_ATREADY_AFVALID_RESET _u(0x0) -#define M33_INT_ATREADY_AFVALID_BITS _u(0x00000002) -#define M33_INT_ATREADY_AFVALID_MSB _u(1) -#define M33_INT_ATREADY_AFVALID_LSB _u(1) -#define M33_INT_ATREADY_AFVALID_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_INT_ATREADY_ATREADY -// Description : A read of this bit returns the value of ATREADY -#define M33_INT_ATREADY_ATREADY_RESET _u(0x0) -#define M33_INT_ATREADY_ATREADY_BITS _u(0x00000001) -#define M33_INT_ATREADY_ATREADY_MSB _u(0) -#define M33_INT_ATREADY_ATREADY_LSB _u(0) -#define M33_INT_ATREADY_ATREADY_ACCESS "RO" -// ============================================================================= -// Register : M33_INT_ATVALID -// Description : Integration Mode: Write ATB Valid -#define M33_INT_ATVALID_OFFSET _u(0x00000ef8) -#define M33_INT_ATVALID_BITS _u(0x00000003) -#define M33_INT_ATVALID_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_INT_ATVALID_AFREADY -// Description : A write to this bit gives the value of AFREADY -#define M33_INT_ATVALID_AFREADY_RESET _u(0x0) -#define M33_INT_ATVALID_AFREADY_BITS _u(0x00000002) -#define M33_INT_ATVALID_AFREADY_MSB _u(1) -#define M33_INT_ATVALID_AFREADY_LSB _u(1) -#define M33_INT_ATVALID_AFREADY_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_INT_ATVALID_ATREADY -// Description : A write to this bit gives the value of ATVALID -#define M33_INT_ATVALID_ATREADY_RESET _u(0x0) -#define M33_INT_ATVALID_ATREADY_BITS _u(0x00000001) -#define M33_INT_ATVALID_ATREADY_MSB _u(0) -#define M33_INT_ATVALID_ATREADY_LSB _u(0) -#define M33_INT_ATVALID_ATREADY_ACCESS "RW" -// ============================================================================= -// Register : M33_ITM_ITCTRL -// Description : Integration Mode Control Register -#define M33_ITM_ITCTRL_OFFSET _u(0x00000f00) -#define M33_ITM_ITCTRL_BITS _u(0x00000001) -#define M33_ITM_ITCTRL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_ITM_ITCTRL_IME -// Description : Integration mode enable bit - The possible values are: 0 - The -// trace unit is not in integration mode. 1 - The trace unit is in -// integration mode. This mode enables: A debug agent to perform -// topology detection. SoC test software to perform integration -// testing. -#define M33_ITM_ITCTRL_IME_RESET _u(0x0) -#define M33_ITM_ITCTRL_IME_BITS _u(0x00000001) -#define M33_ITM_ITCTRL_IME_MSB _u(0) -#define M33_ITM_ITCTRL_IME_LSB _u(0) -#define M33_ITM_ITCTRL_IME_ACCESS "RW" -// ============================================================================= -// Register : M33_ITM_DEVARCH -// Description : Provides CoreSight discovery information for the ITM -#define M33_ITM_DEVARCH_OFFSET _u(0x00000fbc) -#define M33_ITM_DEVARCH_BITS _u(0xffffffff) -#define M33_ITM_DEVARCH_RESET _u(0x47701a01) -// ----------------------------------------------------------------------------- -// Field : M33_ITM_DEVARCH_ARCHITECT -// Description : Defines the architect of the component. Bits [31:28] are the -// JEP106 continuation code (JEP106 bank ID, minus 1) and bits -// [27:21] are the JEP106 ID code. -#define M33_ITM_DEVARCH_ARCHITECT_RESET _u(0x23b) -#define M33_ITM_DEVARCH_ARCHITECT_BITS _u(0xffe00000) -#define M33_ITM_DEVARCH_ARCHITECT_MSB _u(31) -#define M33_ITM_DEVARCH_ARCHITECT_LSB _u(21) -#define M33_ITM_DEVARCH_ARCHITECT_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_ITM_DEVARCH_PRESENT -// Description : Defines that the DEVARCH register is present -#define M33_ITM_DEVARCH_PRESENT_RESET _u(0x1) -#define M33_ITM_DEVARCH_PRESENT_BITS _u(0x00100000) -#define M33_ITM_DEVARCH_PRESENT_MSB _u(20) -#define M33_ITM_DEVARCH_PRESENT_LSB _u(20) -#define M33_ITM_DEVARCH_PRESENT_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_ITM_DEVARCH_REVISION -// Description : Defines the architecture revision of the component -#define M33_ITM_DEVARCH_REVISION_RESET _u(0x0) -#define M33_ITM_DEVARCH_REVISION_BITS _u(0x000f0000) -#define M33_ITM_DEVARCH_REVISION_MSB _u(19) -#define M33_ITM_DEVARCH_REVISION_LSB _u(16) -#define M33_ITM_DEVARCH_REVISION_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_ITM_DEVARCH_ARCHVER -// Description : Defines the architecture version of the component -#define M33_ITM_DEVARCH_ARCHVER_RESET _u(0x1) -#define M33_ITM_DEVARCH_ARCHVER_BITS _u(0x0000f000) -#define M33_ITM_DEVARCH_ARCHVER_MSB _u(15) -#define M33_ITM_DEVARCH_ARCHVER_LSB _u(12) -#define M33_ITM_DEVARCH_ARCHVER_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_ITM_DEVARCH_ARCHPART -// Description : Defines the architecture of the component -#define M33_ITM_DEVARCH_ARCHPART_RESET _u(0xa01) -#define M33_ITM_DEVARCH_ARCHPART_BITS _u(0x00000fff) -#define M33_ITM_DEVARCH_ARCHPART_MSB _u(11) -#define M33_ITM_DEVARCH_ARCHPART_LSB _u(0) -#define M33_ITM_DEVARCH_ARCHPART_ACCESS "RO" -// ============================================================================= -// Register : M33_ITM_DEVTYPE -// Description : Provides CoreSight discovery information for the ITM -#define M33_ITM_DEVTYPE_OFFSET _u(0x00000fcc) -#define M33_ITM_DEVTYPE_BITS _u(0x000000ff) -#define M33_ITM_DEVTYPE_RESET _u(0x00000043) -// ----------------------------------------------------------------------------- -// Field : M33_ITM_DEVTYPE_SUB -// Description : Component sub-type -#define M33_ITM_DEVTYPE_SUB_RESET _u(0x4) -#define M33_ITM_DEVTYPE_SUB_BITS _u(0x000000f0) -#define M33_ITM_DEVTYPE_SUB_MSB _u(7) -#define M33_ITM_DEVTYPE_SUB_LSB _u(4) -#define M33_ITM_DEVTYPE_SUB_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_ITM_DEVTYPE_MAJOR -// Description : Component major type -#define M33_ITM_DEVTYPE_MAJOR_RESET _u(0x3) -#define M33_ITM_DEVTYPE_MAJOR_BITS _u(0x0000000f) -#define M33_ITM_DEVTYPE_MAJOR_MSB _u(3) -#define M33_ITM_DEVTYPE_MAJOR_LSB _u(0) -#define M33_ITM_DEVTYPE_MAJOR_ACCESS "RO" -// ============================================================================= -// Register : M33_ITM_PIDR4 -// Description : Provides CoreSight discovery information for the ITM -#define M33_ITM_PIDR4_OFFSET _u(0x00000fd0) -#define M33_ITM_PIDR4_BITS _u(0x000000ff) -#define M33_ITM_PIDR4_RESET _u(0x00000004) -// ----------------------------------------------------------------------------- -// Field : M33_ITM_PIDR4_SIZE -// Description : See CoreSight Architecture Specification -#define M33_ITM_PIDR4_SIZE_RESET _u(0x0) -#define M33_ITM_PIDR4_SIZE_BITS _u(0x000000f0) -#define M33_ITM_PIDR4_SIZE_MSB _u(7) -#define M33_ITM_PIDR4_SIZE_LSB _u(4) -#define M33_ITM_PIDR4_SIZE_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_ITM_PIDR4_DES_2 -// Description : See CoreSight Architecture Specification -#define M33_ITM_PIDR4_DES_2_RESET _u(0x4) -#define M33_ITM_PIDR4_DES_2_BITS _u(0x0000000f) -#define M33_ITM_PIDR4_DES_2_MSB _u(3) -#define M33_ITM_PIDR4_DES_2_LSB _u(0) -#define M33_ITM_PIDR4_DES_2_ACCESS "RO" -// ============================================================================= -// Register : M33_ITM_PIDR5 -// Description : Provides CoreSight discovery information for the ITM -#define M33_ITM_PIDR5_OFFSET _u(0x00000fd4) -#define M33_ITM_PIDR5_BITS _u(0x00000000) -#define M33_ITM_PIDR5_RESET _u(0x00000000) -#define M33_ITM_PIDR5_MSB _u(31) -#define M33_ITM_PIDR5_LSB _u(0) -#define M33_ITM_PIDR5_ACCESS "RW" -// ============================================================================= -// Register : M33_ITM_PIDR6 -// Description : Provides CoreSight discovery information for the ITM -#define M33_ITM_PIDR6_OFFSET _u(0x00000fd8) -#define M33_ITM_PIDR6_BITS _u(0x00000000) -#define M33_ITM_PIDR6_RESET _u(0x00000000) -#define M33_ITM_PIDR6_MSB _u(31) -#define M33_ITM_PIDR6_LSB _u(0) -#define M33_ITM_PIDR6_ACCESS "RW" -// ============================================================================= -// Register : M33_ITM_PIDR7 -// Description : Provides CoreSight discovery information for the ITM -#define M33_ITM_PIDR7_OFFSET _u(0x00000fdc) -#define M33_ITM_PIDR7_BITS _u(0x00000000) -#define M33_ITM_PIDR7_RESET _u(0x00000000) -#define M33_ITM_PIDR7_MSB _u(31) -#define M33_ITM_PIDR7_LSB _u(0) -#define M33_ITM_PIDR7_ACCESS "RW" -// ============================================================================= -// Register : M33_ITM_PIDR0 -// Description : Provides CoreSight discovery information for the ITM -#define M33_ITM_PIDR0_OFFSET _u(0x00000fe0) -#define M33_ITM_PIDR0_BITS _u(0x000000ff) -#define M33_ITM_PIDR0_RESET _u(0x00000021) -// ----------------------------------------------------------------------------- -// Field : M33_ITM_PIDR0_PART_0 -// Description : See CoreSight Architecture Specification -#define M33_ITM_PIDR0_PART_0_RESET _u(0x21) -#define M33_ITM_PIDR0_PART_0_BITS _u(0x000000ff) -#define M33_ITM_PIDR0_PART_0_MSB _u(7) -#define M33_ITM_PIDR0_PART_0_LSB _u(0) -#define M33_ITM_PIDR0_PART_0_ACCESS "RO" -// ============================================================================= -// Register : M33_ITM_PIDR1 -// Description : Provides CoreSight discovery information for the ITM -#define M33_ITM_PIDR1_OFFSET _u(0x00000fe4) -#define M33_ITM_PIDR1_BITS _u(0x000000ff) -#define M33_ITM_PIDR1_RESET _u(0x000000bd) -// ----------------------------------------------------------------------------- -// Field : M33_ITM_PIDR1_DES_0 -// Description : See CoreSight Architecture Specification -#define M33_ITM_PIDR1_DES_0_RESET _u(0xb) -#define M33_ITM_PIDR1_DES_0_BITS _u(0x000000f0) -#define M33_ITM_PIDR1_DES_0_MSB _u(7) -#define M33_ITM_PIDR1_DES_0_LSB _u(4) -#define M33_ITM_PIDR1_DES_0_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_ITM_PIDR1_PART_1 -// Description : See CoreSight Architecture Specification -#define M33_ITM_PIDR1_PART_1_RESET _u(0xd) -#define M33_ITM_PIDR1_PART_1_BITS _u(0x0000000f) -#define M33_ITM_PIDR1_PART_1_MSB _u(3) -#define M33_ITM_PIDR1_PART_1_LSB _u(0) -#define M33_ITM_PIDR1_PART_1_ACCESS "RO" -// ============================================================================= -// Register : M33_ITM_PIDR2 -// Description : Provides CoreSight discovery information for the ITM -#define M33_ITM_PIDR2_OFFSET _u(0x00000fe8) -#define M33_ITM_PIDR2_BITS _u(0x000000ff) -#define M33_ITM_PIDR2_RESET _u(0x0000000b) -// ----------------------------------------------------------------------------- -// Field : M33_ITM_PIDR2_REVISION -// Description : See CoreSight Architecture Specification -#define M33_ITM_PIDR2_REVISION_RESET _u(0x0) -#define M33_ITM_PIDR2_REVISION_BITS _u(0x000000f0) -#define M33_ITM_PIDR2_REVISION_MSB _u(7) -#define M33_ITM_PIDR2_REVISION_LSB _u(4) -#define M33_ITM_PIDR2_REVISION_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_ITM_PIDR2_JEDEC -// Description : See CoreSight Architecture Specification -#define M33_ITM_PIDR2_JEDEC_RESET _u(0x1) -#define M33_ITM_PIDR2_JEDEC_BITS _u(0x00000008) -#define M33_ITM_PIDR2_JEDEC_MSB _u(3) -#define M33_ITM_PIDR2_JEDEC_LSB _u(3) -#define M33_ITM_PIDR2_JEDEC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_ITM_PIDR2_DES_1 -// Description : See CoreSight Architecture Specification -#define M33_ITM_PIDR2_DES_1_RESET _u(0x3) -#define M33_ITM_PIDR2_DES_1_BITS _u(0x00000007) -#define M33_ITM_PIDR2_DES_1_MSB _u(2) -#define M33_ITM_PIDR2_DES_1_LSB _u(0) -#define M33_ITM_PIDR2_DES_1_ACCESS "RO" -// ============================================================================= -// Register : M33_ITM_PIDR3 -// Description : Provides CoreSight discovery information for the ITM -#define M33_ITM_PIDR3_OFFSET _u(0x00000fec) -#define M33_ITM_PIDR3_BITS _u(0x000000ff) -#define M33_ITM_PIDR3_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_ITM_PIDR3_REVAND -// Description : See CoreSight Architecture Specification -#define M33_ITM_PIDR3_REVAND_RESET _u(0x0) -#define M33_ITM_PIDR3_REVAND_BITS _u(0x000000f0) -#define M33_ITM_PIDR3_REVAND_MSB _u(7) -#define M33_ITM_PIDR3_REVAND_LSB _u(4) -#define M33_ITM_PIDR3_REVAND_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_ITM_PIDR3_CMOD -// Description : See CoreSight Architecture Specification -#define M33_ITM_PIDR3_CMOD_RESET _u(0x0) -#define M33_ITM_PIDR3_CMOD_BITS _u(0x0000000f) -#define M33_ITM_PIDR3_CMOD_MSB _u(3) -#define M33_ITM_PIDR3_CMOD_LSB _u(0) -#define M33_ITM_PIDR3_CMOD_ACCESS "RO" -// ============================================================================= -// Register : M33_ITM_CIDR0 -// Description : Provides CoreSight discovery information for the ITM -#define M33_ITM_CIDR0_OFFSET _u(0x00000ff0) -#define M33_ITM_CIDR0_BITS _u(0x000000ff) -#define M33_ITM_CIDR0_RESET _u(0x0000000d) -// ----------------------------------------------------------------------------- -// Field : M33_ITM_CIDR0_PRMBL_0 -// Description : See CoreSight Architecture Specification -#define M33_ITM_CIDR0_PRMBL_0_RESET _u(0x0d) -#define M33_ITM_CIDR0_PRMBL_0_BITS _u(0x000000ff) -#define M33_ITM_CIDR0_PRMBL_0_MSB _u(7) -#define M33_ITM_CIDR0_PRMBL_0_LSB _u(0) -#define M33_ITM_CIDR0_PRMBL_0_ACCESS "RO" -// ============================================================================= -// Register : M33_ITM_CIDR1 -// Description : Provides CoreSight discovery information for the ITM -#define M33_ITM_CIDR1_OFFSET _u(0x00000ff4) -#define M33_ITM_CIDR1_BITS _u(0x000000ff) -#define M33_ITM_CIDR1_RESET _u(0x00000090) -// ----------------------------------------------------------------------------- -// Field : M33_ITM_CIDR1_CLASS -// Description : See CoreSight Architecture Specification -#define M33_ITM_CIDR1_CLASS_RESET _u(0x9) -#define M33_ITM_CIDR1_CLASS_BITS _u(0x000000f0) -#define M33_ITM_CIDR1_CLASS_MSB _u(7) -#define M33_ITM_CIDR1_CLASS_LSB _u(4) -#define M33_ITM_CIDR1_CLASS_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_ITM_CIDR1_PRMBL_1 -// Description : See CoreSight Architecture Specification -#define M33_ITM_CIDR1_PRMBL_1_RESET _u(0x0) -#define M33_ITM_CIDR1_PRMBL_1_BITS _u(0x0000000f) -#define M33_ITM_CIDR1_PRMBL_1_MSB _u(3) -#define M33_ITM_CIDR1_PRMBL_1_LSB _u(0) -#define M33_ITM_CIDR1_PRMBL_1_ACCESS "RO" -// ============================================================================= -// Register : M33_ITM_CIDR2 -// Description : Provides CoreSight discovery information for the ITM -#define M33_ITM_CIDR2_OFFSET _u(0x00000ff8) -#define M33_ITM_CIDR2_BITS _u(0x000000ff) -#define M33_ITM_CIDR2_RESET _u(0x00000005) -// ----------------------------------------------------------------------------- -// Field : M33_ITM_CIDR2_PRMBL_2 -// Description : See CoreSight Architecture Specification -#define M33_ITM_CIDR2_PRMBL_2_RESET _u(0x05) -#define M33_ITM_CIDR2_PRMBL_2_BITS _u(0x000000ff) -#define M33_ITM_CIDR2_PRMBL_2_MSB _u(7) -#define M33_ITM_CIDR2_PRMBL_2_LSB _u(0) -#define M33_ITM_CIDR2_PRMBL_2_ACCESS "RO" -// ============================================================================= -// Register : M33_ITM_CIDR3 -// Description : Provides CoreSight discovery information for the ITM -#define M33_ITM_CIDR3_OFFSET _u(0x00000ffc) -#define M33_ITM_CIDR3_BITS _u(0x000000ff) -#define M33_ITM_CIDR3_RESET _u(0x000000b1) -// ----------------------------------------------------------------------------- -// Field : M33_ITM_CIDR3_PRMBL_3 -// Description : See CoreSight Architecture Specification -#define M33_ITM_CIDR3_PRMBL_3_RESET _u(0xb1) -#define M33_ITM_CIDR3_PRMBL_3_BITS _u(0x000000ff) -#define M33_ITM_CIDR3_PRMBL_3_MSB _u(7) -#define M33_ITM_CIDR3_PRMBL_3_LSB _u(0) -#define M33_ITM_CIDR3_PRMBL_3_ACCESS "RO" -// ============================================================================= -// Register : M33_DWT_CTRL -// Description : Provides configuration and status information for the DWT unit, -// and used to control features of the unit -#define M33_DWT_CTRL_OFFSET _u(0x00001000) -#define M33_DWT_CTRL_BITS _u(0xffff1fff) -#define M33_DWT_CTRL_RESET _u(0x73741824) -// ----------------------------------------------------------------------------- -// Field : M33_DWT_CTRL_NUMCOMP -// Description : Number of DWT comparators implemented -#define M33_DWT_CTRL_NUMCOMP_RESET _u(0x7) -#define M33_DWT_CTRL_NUMCOMP_BITS _u(0xf0000000) -#define M33_DWT_CTRL_NUMCOMP_MSB _u(31) -#define M33_DWT_CTRL_NUMCOMP_LSB _u(28) -#define M33_DWT_CTRL_NUMCOMP_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_DWT_CTRL_NOTRCPKT -// Description : Indicates whether the implementation does not support trace -#define M33_DWT_CTRL_NOTRCPKT_RESET _u(0x0) -#define M33_DWT_CTRL_NOTRCPKT_BITS _u(0x08000000) -#define M33_DWT_CTRL_NOTRCPKT_MSB _u(27) -#define M33_DWT_CTRL_NOTRCPKT_LSB _u(27) -#define M33_DWT_CTRL_NOTRCPKT_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_DWT_CTRL_NOEXTTRIG -// Description : Reserved, RAZ -#define M33_DWT_CTRL_NOEXTTRIG_RESET _u(0x0) -#define M33_DWT_CTRL_NOEXTTRIG_BITS _u(0x04000000) -#define M33_DWT_CTRL_NOEXTTRIG_MSB _u(26) -#define M33_DWT_CTRL_NOEXTTRIG_LSB _u(26) -#define M33_DWT_CTRL_NOEXTTRIG_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_DWT_CTRL_NOCYCCNT -// Description : Indicates whether the implementation does not include a cycle -// counter -#define M33_DWT_CTRL_NOCYCCNT_RESET _u(0x1) -#define M33_DWT_CTRL_NOCYCCNT_BITS _u(0x02000000) -#define M33_DWT_CTRL_NOCYCCNT_MSB _u(25) -#define M33_DWT_CTRL_NOCYCCNT_LSB _u(25) -#define M33_DWT_CTRL_NOCYCCNT_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_DWT_CTRL_NOPRFCNT -// Description : Indicates whether the implementation does not include the -// profiling counters -#define M33_DWT_CTRL_NOPRFCNT_RESET _u(0x1) -#define M33_DWT_CTRL_NOPRFCNT_BITS _u(0x01000000) -#define M33_DWT_CTRL_NOPRFCNT_MSB _u(24) -#define M33_DWT_CTRL_NOPRFCNT_LSB _u(24) -#define M33_DWT_CTRL_NOPRFCNT_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_DWT_CTRL_CYCDISS -// Description : Controls whether the cycle counter is disabled in Secure state -#define M33_DWT_CTRL_CYCDISS_RESET _u(0x0) -#define M33_DWT_CTRL_CYCDISS_BITS _u(0x00800000) -#define M33_DWT_CTRL_CYCDISS_MSB _u(23) -#define M33_DWT_CTRL_CYCDISS_LSB _u(23) -#define M33_DWT_CTRL_CYCDISS_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_DWT_CTRL_CYCEVTENA -// Description : Enables Event Counter packet generation on POSTCNT underflow -#define M33_DWT_CTRL_CYCEVTENA_RESET _u(0x1) -#define M33_DWT_CTRL_CYCEVTENA_BITS _u(0x00400000) -#define M33_DWT_CTRL_CYCEVTENA_MSB _u(22) -#define M33_DWT_CTRL_CYCEVTENA_LSB _u(22) -#define M33_DWT_CTRL_CYCEVTENA_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_DWT_CTRL_FOLDEVTENA -// Description : Enables DWT_FOLDCNT counter -#define M33_DWT_CTRL_FOLDEVTENA_RESET _u(0x1) -#define M33_DWT_CTRL_FOLDEVTENA_BITS _u(0x00200000) -#define M33_DWT_CTRL_FOLDEVTENA_MSB _u(21) -#define M33_DWT_CTRL_FOLDEVTENA_LSB _u(21) -#define M33_DWT_CTRL_FOLDEVTENA_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_DWT_CTRL_LSUEVTENA -// Description : Enables DWT_LSUCNT counter -#define M33_DWT_CTRL_LSUEVTENA_RESET _u(0x1) -#define M33_DWT_CTRL_LSUEVTENA_BITS _u(0x00100000) -#define M33_DWT_CTRL_LSUEVTENA_MSB _u(20) -#define M33_DWT_CTRL_LSUEVTENA_LSB _u(20) -#define M33_DWT_CTRL_LSUEVTENA_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_DWT_CTRL_SLEEPEVTENA -// Description : Enable DWT_SLEEPCNT counter -#define M33_DWT_CTRL_SLEEPEVTENA_RESET _u(0x0) -#define M33_DWT_CTRL_SLEEPEVTENA_BITS _u(0x00080000) -#define M33_DWT_CTRL_SLEEPEVTENA_MSB _u(19) -#define M33_DWT_CTRL_SLEEPEVTENA_LSB _u(19) -#define M33_DWT_CTRL_SLEEPEVTENA_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_DWT_CTRL_EXCEVTENA -// Description : Enables DWT_EXCCNT counter -#define M33_DWT_CTRL_EXCEVTENA_RESET _u(0x1) -#define M33_DWT_CTRL_EXCEVTENA_BITS _u(0x00040000) -#define M33_DWT_CTRL_EXCEVTENA_MSB _u(18) -#define M33_DWT_CTRL_EXCEVTENA_LSB _u(18) -#define M33_DWT_CTRL_EXCEVTENA_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_DWT_CTRL_CPIEVTENA -// Description : Enables DWT_CPICNT counter -#define M33_DWT_CTRL_CPIEVTENA_RESET _u(0x0) -#define M33_DWT_CTRL_CPIEVTENA_BITS _u(0x00020000) -#define M33_DWT_CTRL_CPIEVTENA_MSB _u(17) -#define M33_DWT_CTRL_CPIEVTENA_LSB _u(17) -#define M33_DWT_CTRL_CPIEVTENA_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_DWT_CTRL_EXTTRCENA -// Description : Enables generation of Exception Trace packets -#define M33_DWT_CTRL_EXTTRCENA_RESET _u(0x0) -#define M33_DWT_CTRL_EXTTRCENA_BITS _u(0x00010000) -#define M33_DWT_CTRL_EXTTRCENA_MSB _u(16) -#define M33_DWT_CTRL_EXTTRCENA_LSB _u(16) -#define M33_DWT_CTRL_EXTTRCENA_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_DWT_CTRL_PCSAMPLENA -// Description : Enables use of POSTCNT counter as a timer for Periodic PC -// Sample packet generation -#define M33_DWT_CTRL_PCSAMPLENA_RESET _u(0x1) -#define M33_DWT_CTRL_PCSAMPLENA_BITS _u(0x00001000) -#define M33_DWT_CTRL_PCSAMPLENA_MSB _u(12) -#define M33_DWT_CTRL_PCSAMPLENA_LSB _u(12) -#define M33_DWT_CTRL_PCSAMPLENA_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_DWT_CTRL_SYNCTAP -// Description : Selects the position of the synchronization packet counter tap -// on the CYCCNT counter. This determines the Synchronization -// packet rate -#define M33_DWT_CTRL_SYNCTAP_RESET _u(0x2) -#define M33_DWT_CTRL_SYNCTAP_BITS _u(0x00000c00) -#define M33_DWT_CTRL_SYNCTAP_MSB _u(11) -#define M33_DWT_CTRL_SYNCTAP_LSB _u(10) -#define M33_DWT_CTRL_SYNCTAP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_DWT_CTRL_CYCTAP -// Description : Selects the position of the POSTCNT tap on the CYCCNT counter -#define M33_DWT_CTRL_CYCTAP_RESET _u(0x0) -#define M33_DWT_CTRL_CYCTAP_BITS _u(0x00000200) -#define M33_DWT_CTRL_CYCTAP_MSB _u(9) -#define M33_DWT_CTRL_CYCTAP_LSB _u(9) -#define M33_DWT_CTRL_CYCTAP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_DWT_CTRL_POSTINIT -// Description : Initial value for the POSTCNT counter -#define M33_DWT_CTRL_POSTINIT_RESET _u(0x1) -#define M33_DWT_CTRL_POSTINIT_BITS _u(0x000001e0) -#define M33_DWT_CTRL_POSTINIT_MSB _u(8) -#define M33_DWT_CTRL_POSTINIT_LSB _u(5) -#define M33_DWT_CTRL_POSTINIT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_DWT_CTRL_POSTPRESET -// Description : Reload value for the POSTCNT counter -#define M33_DWT_CTRL_POSTPRESET_RESET _u(0x2) -#define M33_DWT_CTRL_POSTPRESET_BITS _u(0x0000001e) -#define M33_DWT_CTRL_POSTPRESET_MSB _u(4) -#define M33_DWT_CTRL_POSTPRESET_LSB _u(1) -#define M33_DWT_CTRL_POSTPRESET_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_DWT_CTRL_CYCCNTENA -// Description : Enables CYCCNT -#define M33_DWT_CTRL_CYCCNTENA_RESET _u(0x0) -#define M33_DWT_CTRL_CYCCNTENA_BITS _u(0x00000001) -#define M33_DWT_CTRL_CYCCNTENA_MSB _u(0) -#define M33_DWT_CTRL_CYCCNTENA_LSB _u(0) -#define M33_DWT_CTRL_CYCCNTENA_ACCESS "RW" -// ============================================================================= -// Register : M33_DWT_CYCCNT -// Description : Shows or sets the value of the processor cycle counter, CYCCNT -#define M33_DWT_CYCCNT_OFFSET _u(0x00001004) -#define M33_DWT_CYCCNT_BITS _u(0xffffffff) -#define M33_DWT_CYCCNT_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_DWT_CYCCNT_CYCCNT -// Description : Increments one on each processor clock cycle when -// DWT_CTRL.CYCCNTENA == 1 and DEMCR.TRCENA == 1. On overflow, -// CYCCNT wraps to zero -#define M33_DWT_CYCCNT_CYCCNT_RESET _u(0x00000000) -#define M33_DWT_CYCCNT_CYCCNT_BITS _u(0xffffffff) -#define M33_DWT_CYCCNT_CYCCNT_MSB _u(31) -#define M33_DWT_CYCCNT_CYCCNT_LSB _u(0) -#define M33_DWT_CYCCNT_CYCCNT_ACCESS "RW" -// ============================================================================= -// Register : M33_DWT_EXCCNT -// Description : Counts the total cycles spent in exception processing -#define M33_DWT_EXCCNT_OFFSET _u(0x0000100c) -#define M33_DWT_EXCCNT_BITS _u(0x000000ff) -#define M33_DWT_EXCCNT_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_DWT_EXCCNT_EXCCNT -// Description : Counts one on each cycle when all of the following are true: - -// DWT_CTRL.EXCEVTENA == 1 and DEMCR.TRCENA == 1. - No instruction -// is executed, see DWT_CPICNT. - An exception-entry or exception- -// exit related operation is in progress. - Either -// SecureNoninvasiveDebugAllowed() == TRUE, or NS-Req for the -// operation is set to Non-secure and NoninvasiveDebugAllowed() == -// TRUE. -#define M33_DWT_EXCCNT_EXCCNT_RESET _u(0x00) -#define M33_DWT_EXCCNT_EXCCNT_BITS _u(0x000000ff) -#define M33_DWT_EXCCNT_EXCCNT_MSB _u(7) -#define M33_DWT_EXCCNT_EXCCNT_LSB _u(0) -#define M33_DWT_EXCCNT_EXCCNT_ACCESS "RW" -// ============================================================================= -// Register : M33_DWT_LSUCNT -// Description : Increments on the additional cycles required to execute all -// load or store instructions -#define M33_DWT_LSUCNT_OFFSET _u(0x00001014) -#define M33_DWT_LSUCNT_BITS _u(0x000000ff) -#define M33_DWT_LSUCNT_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_DWT_LSUCNT_LSUCNT -// Description : Counts one on each cycle when all of the following are true: - -// DWT_CTRL.LSUEVTENA == 1 and DEMCR.TRCENA == 1. - No instruction -// is executed, see DWT_CPICNT. - No exception-entry or exception- -// exit operation is in progress, see DWT_EXCCNT. - A load-store -// operation is in progress. - Either -// SecureNoninvasiveDebugAllowed() == TRUE, or NS-Req for the -// operation is set to Non-secure and NoninvasiveDebugAllowed() == -// TRUE. -#define M33_DWT_LSUCNT_LSUCNT_RESET _u(0x00) -#define M33_DWT_LSUCNT_LSUCNT_BITS _u(0x000000ff) -#define M33_DWT_LSUCNT_LSUCNT_MSB _u(7) -#define M33_DWT_LSUCNT_LSUCNT_LSB _u(0) -#define M33_DWT_LSUCNT_LSUCNT_ACCESS "RW" -// ============================================================================= -// Register : M33_DWT_FOLDCNT -// Description : Increments on the additional cycles required to execute all -// load or store instructions -#define M33_DWT_FOLDCNT_OFFSET _u(0x00001018) -#define M33_DWT_FOLDCNT_BITS _u(0x000000ff) -#define M33_DWT_FOLDCNT_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_DWT_FOLDCNT_FOLDCNT -// Description : Counts on each cycle when all of the following are true: - -// DWT_CTRL.FOLDEVTENA == 1 and DEMCR.TRCENA == 1. - At least two -// instructions are executed, see DWT_CPICNT. - Either -// SecureNoninvasiveDebugAllowed() == TRUE, or the PE is in Non- -// secure state and NoninvasiveDebugAllowed() == TRUE. The counter -// is incremented by the number of instructions executed, minus -// one -#define M33_DWT_FOLDCNT_FOLDCNT_RESET _u(0x00) -#define M33_DWT_FOLDCNT_FOLDCNT_BITS _u(0x000000ff) -#define M33_DWT_FOLDCNT_FOLDCNT_MSB _u(7) -#define M33_DWT_FOLDCNT_FOLDCNT_LSB _u(0) -#define M33_DWT_FOLDCNT_FOLDCNT_ACCESS "RW" -// ============================================================================= -// Register : M33_DWT_COMP0 -// Description : Provides a reference value for use by watchpoint comparator 0 -#define M33_DWT_COMP0_OFFSET _u(0x00001020) -#define M33_DWT_COMP0_BITS _u(0xffffffff) -#define M33_DWT_COMP0_RESET _u(0x00000000) -#define M33_DWT_COMP0_MSB _u(31) -#define M33_DWT_COMP0_LSB _u(0) -#define M33_DWT_COMP0_ACCESS "RW" -// ============================================================================= -// Register : M33_DWT_FUNCTION0 -// Description : Controls the operation of watchpoint comparator 0 -#define M33_DWT_FUNCTION0_OFFSET _u(0x00001028) -#define M33_DWT_FUNCTION0_BITS _u(0xf9000c3f) -#define M33_DWT_FUNCTION0_RESET _u(0x58000000) -// ----------------------------------------------------------------------------- -// Field : M33_DWT_FUNCTION0_ID -// Description : Identifies the capabilities for MATCH for comparator *n -#define M33_DWT_FUNCTION0_ID_RESET _u(0x0b) -#define M33_DWT_FUNCTION0_ID_BITS _u(0xf8000000) -#define M33_DWT_FUNCTION0_ID_MSB _u(31) -#define M33_DWT_FUNCTION0_ID_LSB _u(27) -#define M33_DWT_FUNCTION0_ID_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_DWT_FUNCTION0_MATCHED -// Description : Set to 1 when the comparator matches -#define M33_DWT_FUNCTION0_MATCHED_RESET _u(0x0) -#define M33_DWT_FUNCTION0_MATCHED_BITS _u(0x01000000) -#define M33_DWT_FUNCTION0_MATCHED_MSB _u(24) -#define M33_DWT_FUNCTION0_MATCHED_LSB _u(24) -#define M33_DWT_FUNCTION0_MATCHED_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_DWT_FUNCTION0_DATAVSIZE -// Description : Defines the size of the object being watched for by Data Value -// and Data Address comparators -#define M33_DWT_FUNCTION0_DATAVSIZE_RESET _u(0x0) -#define M33_DWT_FUNCTION0_DATAVSIZE_BITS _u(0x00000c00) -#define M33_DWT_FUNCTION0_DATAVSIZE_MSB _u(11) -#define M33_DWT_FUNCTION0_DATAVSIZE_LSB _u(10) -#define M33_DWT_FUNCTION0_DATAVSIZE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_DWT_FUNCTION0_ACTION -// Description : Defines the action on a match. This field is ignored and the -// comparator generates no actions if it is disabled by MATCH -#define M33_DWT_FUNCTION0_ACTION_RESET _u(0x0) -#define M33_DWT_FUNCTION0_ACTION_BITS _u(0x00000030) -#define M33_DWT_FUNCTION0_ACTION_MSB _u(5) -#define M33_DWT_FUNCTION0_ACTION_LSB _u(4) -#define M33_DWT_FUNCTION0_ACTION_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_DWT_FUNCTION0_MATCH -// Description : Controls the type of match generated by this comparator -#define M33_DWT_FUNCTION0_MATCH_RESET _u(0x0) -#define M33_DWT_FUNCTION0_MATCH_BITS _u(0x0000000f) -#define M33_DWT_FUNCTION0_MATCH_MSB _u(3) -#define M33_DWT_FUNCTION0_MATCH_LSB _u(0) -#define M33_DWT_FUNCTION0_MATCH_ACCESS "RW" -// ============================================================================= -// Register : M33_DWT_COMP1 -// Description : Provides a reference value for use by watchpoint comparator 1 -#define M33_DWT_COMP1_OFFSET _u(0x00001030) -#define M33_DWT_COMP1_BITS _u(0xffffffff) -#define M33_DWT_COMP1_RESET _u(0x00000000) -#define M33_DWT_COMP1_MSB _u(31) -#define M33_DWT_COMP1_LSB _u(0) -#define M33_DWT_COMP1_ACCESS "RW" -// ============================================================================= -// Register : M33_DWT_FUNCTION1 -// Description : Controls the operation of watchpoint comparator 1 -#define M33_DWT_FUNCTION1_OFFSET _u(0x00001038) -#define M33_DWT_FUNCTION1_BITS _u(0xf9000c3f) -#define M33_DWT_FUNCTION1_RESET _u(0x89000828) -// ----------------------------------------------------------------------------- -// Field : M33_DWT_FUNCTION1_ID -// Description : Identifies the capabilities for MATCH for comparator *n -#define M33_DWT_FUNCTION1_ID_RESET _u(0x11) -#define M33_DWT_FUNCTION1_ID_BITS _u(0xf8000000) -#define M33_DWT_FUNCTION1_ID_MSB _u(31) -#define M33_DWT_FUNCTION1_ID_LSB _u(27) -#define M33_DWT_FUNCTION1_ID_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_DWT_FUNCTION1_MATCHED -// Description : Set to 1 when the comparator matches -#define M33_DWT_FUNCTION1_MATCHED_RESET _u(0x1) -#define M33_DWT_FUNCTION1_MATCHED_BITS _u(0x01000000) -#define M33_DWT_FUNCTION1_MATCHED_MSB _u(24) -#define M33_DWT_FUNCTION1_MATCHED_LSB _u(24) -#define M33_DWT_FUNCTION1_MATCHED_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_DWT_FUNCTION1_DATAVSIZE -// Description : Defines the size of the object being watched for by Data Value -// and Data Address comparators -#define M33_DWT_FUNCTION1_DATAVSIZE_RESET _u(0x2) -#define M33_DWT_FUNCTION1_DATAVSIZE_BITS _u(0x00000c00) -#define M33_DWT_FUNCTION1_DATAVSIZE_MSB _u(11) -#define M33_DWT_FUNCTION1_DATAVSIZE_LSB _u(10) -#define M33_DWT_FUNCTION1_DATAVSIZE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_DWT_FUNCTION1_ACTION -// Description : Defines the action on a match. This field is ignored and the -// comparator generates no actions if it is disabled by MATCH -#define M33_DWT_FUNCTION1_ACTION_RESET _u(0x2) -#define M33_DWT_FUNCTION1_ACTION_BITS _u(0x00000030) -#define M33_DWT_FUNCTION1_ACTION_MSB _u(5) -#define M33_DWT_FUNCTION1_ACTION_LSB _u(4) -#define M33_DWT_FUNCTION1_ACTION_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_DWT_FUNCTION1_MATCH -// Description : Controls the type of match generated by this comparator -#define M33_DWT_FUNCTION1_MATCH_RESET _u(0x8) -#define M33_DWT_FUNCTION1_MATCH_BITS _u(0x0000000f) -#define M33_DWT_FUNCTION1_MATCH_MSB _u(3) -#define M33_DWT_FUNCTION1_MATCH_LSB _u(0) -#define M33_DWT_FUNCTION1_MATCH_ACCESS "RW" -// ============================================================================= -// Register : M33_DWT_COMP2 -// Description : Provides a reference value for use by watchpoint comparator 2 -#define M33_DWT_COMP2_OFFSET _u(0x00001040) -#define M33_DWT_COMP2_BITS _u(0xffffffff) -#define M33_DWT_COMP2_RESET _u(0x00000000) -#define M33_DWT_COMP2_MSB _u(31) -#define M33_DWT_COMP2_LSB _u(0) -#define M33_DWT_COMP2_ACCESS "RW" -// ============================================================================= -// Register : M33_DWT_FUNCTION2 -// Description : Controls the operation of watchpoint comparator 2 -#define M33_DWT_FUNCTION2_OFFSET _u(0x00001048) -#define M33_DWT_FUNCTION2_BITS _u(0xf9000c3f) -#define M33_DWT_FUNCTION2_RESET _u(0x50000000) -// ----------------------------------------------------------------------------- -// Field : M33_DWT_FUNCTION2_ID -// Description : Identifies the capabilities for MATCH for comparator *n -#define M33_DWT_FUNCTION2_ID_RESET _u(0x0a) -#define M33_DWT_FUNCTION2_ID_BITS _u(0xf8000000) -#define M33_DWT_FUNCTION2_ID_MSB _u(31) -#define M33_DWT_FUNCTION2_ID_LSB _u(27) -#define M33_DWT_FUNCTION2_ID_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_DWT_FUNCTION2_MATCHED -// Description : Set to 1 when the comparator matches -#define M33_DWT_FUNCTION2_MATCHED_RESET _u(0x0) -#define M33_DWT_FUNCTION2_MATCHED_BITS _u(0x01000000) -#define M33_DWT_FUNCTION2_MATCHED_MSB _u(24) -#define M33_DWT_FUNCTION2_MATCHED_LSB _u(24) -#define M33_DWT_FUNCTION2_MATCHED_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_DWT_FUNCTION2_DATAVSIZE -// Description : Defines the size of the object being watched for by Data Value -// and Data Address comparators -#define M33_DWT_FUNCTION2_DATAVSIZE_RESET _u(0x0) -#define M33_DWT_FUNCTION2_DATAVSIZE_BITS _u(0x00000c00) -#define M33_DWT_FUNCTION2_DATAVSIZE_MSB _u(11) -#define M33_DWT_FUNCTION2_DATAVSIZE_LSB _u(10) -#define M33_DWT_FUNCTION2_DATAVSIZE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_DWT_FUNCTION2_ACTION -// Description : Defines the action on a match. This field is ignored and the -// comparator generates no actions if it is disabled by MATCH -#define M33_DWT_FUNCTION2_ACTION_RESET _u(0x0) -#define M33_DWT_FUNCTION2_ACTION_BITS _u(0x00000030) -#define M33_DWT_FUNCTION2_ACTION_MSB _u(5) -#define M33_DWT_FUNCTION2_ACTION_LSB _u(4) -#define M33_DWT_FUNCTION2_ACTION_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_DWT_FUNCTION2_MATCH -// Description : Controls the type of match generated by this comparator -#define M33_DWT_FUNCTION2_MATCH_RESET _u(0x0) -#define M33_DWT_FUNCTION2_MATCH_BITS _u(0x0000000f) -#define M33_DWT_FUNCTION2_MATCH_MSB _u(3) -#define M33_DWT_FUNCTION2_MATCH_LSB _u(0) -#define M33_DWT_FUNCTION2_MATCH_ACCESS "RW" -// ============================================================================= -// Register : M33_DWT_COMP3 -// Description : Provides a reference value for use by watchpoint comparator 3 -#define M33_DWT_COMP3_OFFSET _u(0x00001050) -#define M33_DWT_COMP3_BITS _u(0xffffffff) -#define M33_DWT_COMP3_RESET _u(0x00000000) -#define M33_DWT_COMP3_MSB _u(31) -#define M33_DWT_COMP3_LSB _u(0) -#define M33_DWT_COMP3_ACCESS "RW" -// ============================================================================= -// Register : M33_DWT_FUNCTION3 -// Description : Controls the operation of watchpoint comparator 3 -#define M33_DWT_FUNCTION3_OFFSET _u(0x00001058) -#define M33_DWT_FUNCTION3_BITS _u(0xf9000c3f) -#define M33_DWT_FUNCTION3_RESET _u(0x20000800) -// ----------------------------------------------------------------------------- -// Field : M33_DWT_FUNCTION3_ID -// Description : Identifies the capabilities for MATCH for comparator *n -#define M33_DWT_FUNCTION3_ID_RESET _u(0x04) -#define M33_DWT_FUNCTION3_ID_BITS _u(0xf8000000) -#define M33_DWT_FUNCTION3_ID_MSB _u(31) -#define M33_DWT_FUNCTION3_ID_LSB _u(27) -#define M33_DWT_FUNCTION3_ID_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_DWT_FUNCTION3_MATCHED -// Description : Set to 1 when the comparator matches -#define M33_DWT_FUNCTION3_MATCHED_RESET _u(0x0) -#define M33_DWT_FUNCTION3_MATCHED_BITS _u(0x01000000) -#define M33_DWT_FUNCTION3_MATCHED_MSB _u(24) -#define M33_DWT_FUNCTION3_MATCHED_LSB _u(24) -#define M33_DWT_FUNCTION3_MATCHED_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_DWT_FUNCTION3_DATAVSIZE -// Description : Defines the size of the object being watched for by Data Value -// and Data Address comparators -#define M33_DWT_FUNCTION3_DATAVSIZE_RESET _u(0x2) -#define M33_DWT_FUNCTION3_DATAVSIZE_BITS _u(0x00000c00) -#define M33_DWT_FUNCTION3_DATAVSIZE_MSB _u(11) -#define M33_DWT_FUNCTION3_DATAVSIZE_LSB _u(10) -#define M33_DWT_FUNCTION3_DATAVSIZE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_DWT_FUNCTION3_ACTION -// Description : Defines the action on a match. This field is ignored and the -// comparator generates no actions if it is disabled by MATCH -#define M33_DWT_FUNCTION3_ACTION_RESET _u(0x0) -#define M33_DWT_FUNCTION3_ACTION_BITS _u(0x00000030) -#define M33_DWT_FUNCTION3_ACTION_MSB _u(5) -#define M33_DWT_FUNCTION3_ACTION_LSB _u(4) -#define M33_DWT_FUNCTION3_ACTION_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_DWT_FUNCTION3_MATCH -// Description : Controls the type of match generated by this comparator -#define M33_DWT_FUNCTION3_MATCH_RESET _u(0x0) -#define M33_DWT_FUNCTION3_MATCH_BITS _u(0x0000000f) -#define M33_DWT_FUNCTION3_MATCH_MSB _u(3) -#define M33_DWT_FUNCTION3_MATCH_LSB _u(0) -#define M33_DWT_FUNCTION3_MATCH_ACCESS "RW" -// ============================================================================= -// Register : M33_DWT_DEVARCH -// Description : Provides CoreSight discovery information for the DWT -#define M33_DWT_DEVARCH_OFFSET _u(0x00001fbc) -#define M33_DWT_DEVARCH_BITS _u(0xffffffff) -#define M33_DWT_DEVARCH_RESET _u(0x47701a02) -// ----------------------------------------------------------------------------- -// Field : M33_DWT_DEVARCH_ARCHITECT -// Description : Defines the architect of the component. Bits [31:28] are the -// JEP106 continuation code (JEP106 bank ID, minus 1) and bits -// [27:21] are the JEP106 ID code. -#define M33_DWT_DEVARCH_ARCHITECT_RESET _u(0x23b) -#define M33_DWT_DEVARCH_ARCHITECT_BITS _u(0xffe00000) -#define M33_DWT_DEVARCH_ARCHITECT_MSB _u(31) -#define M33_DWT_DEVARCH_ARCHITECT_LSB _u(21) -#define M33_DWT_DEVARCH_ARCHITECT_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_DWT_DEVARCH_PRESENT -// Description : Defines that the DEVARCH register is present -#define M33_DWT_DEVARCH_PRESENT_RESET _u(0x1) -#define M33_DWT_DEVARCH_PRESENT_BITS _u(0x00100000) -#define M33_DWT_DEVARCH_PRESENT_MSB _u(20) -#define M33_DWT_DEVARCH_PRESENT_LSB _u(20) -#define M33_DWT_DEVARCH_PRESENT_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_DWT_DEVARCH_REVISION -// Description : Defines the architecture revision of the component -#define M33_DWT_DEVARCH_REVISION_RESET _u(0x0) -#define M33_DWT_DEVARCH_REVISION_BITS _u(0x000f0000) -#define M33_DWT_DEVARCH_REVISION_MSB _u(19) -#define M33_DWT_DEVARCH_REVISION_LSB _u(16) -#define M33_DWT_DEVARCH_REVISION_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_DWT_DEVARCH_ARCHVER -// Description : Defines the architecture version of the component -#define M33_DWT_DEVARCH_ARCHVER_RESET _u(0x1) -#define M33_DWT_DEVARCH_ARCHVER_BITS _u(0x0000f000) -#define M33_DWT_DEVARCH_ARCHVER_MSB _u(15) -#define M33_DWT_DEVARCH_ARCHVER_LSB _u(12) -#define M33_DWT_DEVARCH_ARCHVER_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_DWT_DEVARCH_ARCHPART -// Description : Defines the architecture of the component -#define M33_DWT_DEVARCH_ARCHPART_RESET _u(0xa02) -#define M33_DWT_DEVARCH_ARCHPART_BITS _u(0x00000fff) -#define M33_DWT_DEVARCH_ARCHPART_MSB _u(11) -#define M33_DWT_DEVARCH_ARCHPART_LSB _u(0) -#define M33_DWT_DEVARCH_ARCHPART_ACCESS "RO" -// ============================================================================= -// Register : M33_DWT_DEVTYPE -// Description : Provides CoreSight discovery information for the DWT -#define M33_DWT_DEVTYPE_OFFSET _u(0x00001fcc) -#define M33_DWT_DEVTYPE_BITS _u(0x000000ff) -#define M33_DWT_DEVTYPE_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_DWT_DEVTYPE_SUB -// Description : Component sub-type -#define M33_DWT_DEVTYPE_SUB_RESET _u(0x0) -#define M33_DWT_DEVTYPE_SUB_BITS _u(0x000000f0) -#define M33_DWT_DEVTYPE_SUB_MSB _u(7) -#define M33_DWT_DEVTYPE_SUB_LSB _u(4) -#define M33_DWT_DEVTYPE_SUB_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_DWT_DEVTYPE_MAJOR -// Description : Component major type -#define M33_DWT_DEVTYPE_MAJOR_RESET _u(0x0) -#define M33_DWT_DEVTYPE_MAJOR_BITS _u(0x0000000f) -#define M33_DWT_DEVTYPE_MAJOR_MSB _u(3) -#define M33_DWT_DEVTYPE_MAJOR_LSB _u(0) -#define M33_DWT_DEVTYPE_MAJOR_ACCESS "RO" -// ============================================================================= -// Register : M33_DWT_PIDR4 -// Description : Provides CoreSight discovery information for the DWT -#define M33_DWT_PIDR4_OFFSET _u(0x00001fd0) -#define M33_DWT_PIDR4_BITS _u(0x000000ff) -#define M33_DWT_PIDR4_RESET _u(0x00000004) -// ----------------------------------------------------------------------------- -// Field : M33_DWT_PIDR4_SIZE -// Description : See CoreSight Architecture Specification -#define M33_DWT_PIDR4_SIZE_RESET _u(0x0) -#define M33_DWT_PIDR4_SIZE_BITS _u(0x000000f0) -#define M33_DWT_PIDR4_SIZE_MSB _u(7) -#define M33_DWT_PIDR4_SIZE_LSB _u(4) -#define M33_DWT_PIDR4_SIZE_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_DWT_PIDR4_DES_2 -// Description : See CoreSight Architecture Specification -#define M33_DWT_PIDR4_DES_2_RESET _u(0x4) -#define M33_DWT_PIDR4_DES_2_BITS _u(0x0000000f) -#define M33_DWT_PIDR4_DES_2_MSB _u(3) -#define M33_DWT_PIDR4_DES_2_LSB _u(0) -#define M33_DWT_PIDR4_DES_2_ACCESS "RO" -// ============================================================================= -// Register : M33_DWT_PIDR5 -// Description : Provides CoreSight discovery information for the DWT -#define M33_DWT_PIDR5_OFFSET _u(0x00001fd4) -#define M33_DWT_PIDR5_BITS _u(0x00000000) -#define M33_DWT_PIDR5_RESET _u(0x00000000) -#define M33_DWT_PIDR5_MSB _u(31) -#define M33_DWT_PIDR5_LSB _u(0) -#define M33_DWT_PIDR5_ACCESS "RW" -// ============================================================================= -// Register : M33_DWT_PIDR6 -// Description : Provides CoreSight discovery information for the DWT -#define M33_DWT_PIDR6_OFFSET _u(0x00001fd8) -#define M33_DWT_PIDR6_BITS _u(0x00000000) -#define M33_DWT_PIDR6_RESET _u(0x00000000) -#define M33_DWT_PIDR6_MSB _u(31) -#define M33_DWT_PIDR6_LSB _u(0) -#define M33_DWT_PIDR6_ACCESS "RW" -// ============================================================================= -// Register : M33_DWT_PIDR7 -// Description : Provides CoreSight discovery information for the DWT -#define M33_DWT_PIDR7_OFFSET _u(0x00001fdc) -#define M33_DWT_PIDR7_BITS _u(0x00000000) -#define M33_DWT_PIDR7_RESET _u(0x00000000) -#define M33_DWT_PIDR7_MSB _u(31) -#define M33_DWT_PIDR7_LSB _u(0) -#define M33_DWT_PIDR7_ACCESS "RW" -// ============================================================================= -// Register : M33_DWT_PIDR0 -// Description : Provides CoreSight discovery information for the DWT -#define M33_DWT_PIDR0_OFFSET _u(0x00001fe0) -#define M33_DWT_PIDR0_BITS _u(0x000000ff) -#define M33_DWT_PIDR0_RESET _u(0x00000021) -// ----------------------------------------------------------------------------- -// Field : M33_DWT_PIDR0_PART_0 -// Description : See CoreSight Architecture Specification -#define M33_DWT_PIDR0_PART_0_RESET _u(0x21) -#define M33_DWT_PIDR0_PART_0_BITS _u(0x000000ff) -#define M33_DWT_PIDR0_PART_0_MSB _u(7) -#define M33_DWT_PIDR0_PART_0_LSB _u(0) -#define M33_DWT_PIDR0_PART_0_ACCESS "RO" -// ============================================================================= -// Register : M33_DWT_PIDR1 -// Description : Provides CoreSight discovery information for the DWT -#define M33_DWT_PIDR1_OFFSET _u(0x00001fe4) -#define M33_DWT_PIDR1_BITS _u(0x000000ff) -#define M33_DWT_PIDR1_RESET _u(0x000000bd) -// ----------------------------------------------------------------------------- -// Field : M33_DWT_PIDR1_DES_0 -// Description : See CoreSight Architecture Specification -#define M33_DWT_PIDR1_DES_0_RESET _u(0xb) -#define M33_DWT_PIDR1_DES_0_BITS _u(0x000000f0) -#define M33_DWT_PIDR1_DES_0_MSB _u(7) -#define M33_DWT_PIDR1_DES_0_LSB _u(4) -#define M33_DWT_PIDR1_DES_0_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_DWT_PIDR1_PART_1 -// Description : See CoreSight Architecture Specification -#define M33_DWT_PIDR1_PART_1_RESET _u(0xd) -#define M33_DWT_PIDR1_PART_1_BITS _u(0x0000000f) -#define M33_DWT_PIDR1_PART_1_MSB _u(3) -#define M33_DWT_PIDR1_PART_1_LSB _u(0) -#define M33_DWT_PIDR1_PART_1_ACCESS "RO" -// ============================================================================= -// Register : M33_DWT_PIDR2 -// Description : Provides CoreSight discovery information for the DWT -#define M33_DWT_PIDR2_OFFSET _u(0x00001fe8) -#define M33_DWT_PIDR2_BITS _u(0x000000ff) -#define M33_DWT_PIDR2_RESET _u(0x0000000b) -// ----------------------------------------------------------------------------- -// Field : M33_DWT_PIDR2_REVISION -// Description : See CoreSight Architecture Specification -#define M33_DWT_PIDR2_REVISION_RESET _u(0x0) -#define M33_DWT_PIDR2_REVISION_BITS _u(0x000000f0) -#define M33_DWT_PIDR2_REVISION_MSB _u(7) -#define M33_DWT_PIDR2_REVISION_LSB _u(4) -#define M33_DWT_PIDR2_REVISION_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_DWT_PIDR2_JEDEC -// Description : See CoreSight Architecture Specification -#define M33_DWT_PIDR2_JEDEC_RESET _u(0x1) -#define M33_DWT_PIDR2_JEDEC_BITS _u(0x00000008) -#define M33_DWT_PIDR2_JEDEC_MSB _u(3) -#define M33_DWT_PIDR2_JEDEC_LSB _u(3) -#define M33_DWT_PIDR2_JEDEC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_DWT_PIDR2_DES_1 -// Description : See CoreSight Architecture Specification -#define M33_DWT_PIDR2_DES_1_RESET _u(0x3) -#define M33_DWT_PIDR2_DES_1_BITS _u(0x00000007) -#define M33_DWT_PIDR2_DES_1_MSB _u(2) -#define M33_DWT_PIDR2_DES_1_LSB _u(0) -#define M33_DWT_PIDR2_DES_1_ACCESS "RO" -// ============================================================================= -// Register : M33_DWT_PIDR3 -// Description : Provides CoreSight discovery information for the DWT -#define M33_DWT_PIDR3_OFFSET _u(0x00001fec) -#define M33_DWT_PIDR3_BITS _u(0x000000ff) -#define M33_DWT_PIDR3_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_DWT_PIDR3_REVAND -// Description : See CoreSight Architecture Specification -#define M33_DWT_PIDR3_REVAND_RESET _u(0x0) -#define M33_DWT_PIDR3_REVAND_BITS _u(0x000000f0) -#define M33_DWT_PIDR3_REVAND_MSB _u(7) -#define M33_DWT_PIDR3_REVAND_LSB _u(4) -#define M33_DWT_PIDR3_REVAND_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_DWT_PIDR3_CMOD -// Description : See CoreSight Architecture Specification -#define M33_DWT_PIDR3_CMOD_RESET _u(0x0) -#define M33_DWT_PIDR3_CMOD_BITS _u(0x0000000f) -#define M33_DWT_PIDR3_CMOD_MSB _u(3) -#define M33_DWT_PIDR3_CMOD_LSB _u(0) -#define M33_DWT_PIDR3_CMOD_ACCESS "RO" -// ============================================================================= -// Register : M33_DWT_CIDR0 -// Description : Provides CoreSight discovery information for the DWT -#define M33_DWT_CIDR0_OFFSET _u(0x00001ff0) -#define M33_DWT_CIDR0_BITS _u(0x000000ff) -#define M33_DWT_CIDR0_RESET _u(0x0000000d) -// ----------------------------------------------------------------------------- -// Field : M33_DWT_CIDR0_PRMBL_0 -// Description : See CoreSight Architecture Specification -#define M33_DWT_CIDR0_PRMBL_0_RESET _u(0x0d) -#define M33_DWT_CIDR0_PRMBL_0_BITS _u(0x000000ff) -#define M33_DWT_CIDR0_PRMBL_0_MSB _u(7) -#define M33_DWT_CIDR0_PRMBL_0_LSB _u(0) -#define M33_DWT_CIDR0_PRMBL_0_ACCESS "RO" -// ============================================================================= -// Register : M33_DWT_CIDR1 -// Description : Provides CoreSight discovery information for the DWT -#define M33_DWT_CIDR1_OFFSET _u(0x00001ff4) -#define M33_DWT_CIDR1_BITS _u(0x000000ff) -#define M33_DWT_CIDR1_RESET _u(0x00000090) -// ----------------------------------------------------------------------------- -// Field : M33_DWT_CIDR1_CLASS -// Description : See CoreSight Architecture Specification -#define M33_DWT_CIDR1_CLASS_RESET _u(0x9) -#define M33_DWT_CIDR1_CLASS_BITS _u(0x000000f0) -#define M33_DWT_CIDR1_CLASS_MSB _u(7) -#define M33_DWT_CIDR1_CLASS_LSB _u(4) -#define M33_DWT_CIDR1_CLASS_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_DWT_CIDR1_PRMBL_1 -// Description : See CoreSight Architecture Specification -#define M33_DWT_CIDR1_PRMBL_1_RESET _u(0x0) -#define M33_DWT_CIDR1_PRMBL_1_BITS _u(0x0000000f) -#define M33_DWT_CIDR1_PRMBL_1_MSB _u(3) -#define M33_DWT_CIDR1_PRMBL_1_LSB _u(0) -#define M33_DWT_CIDR1_PRMBL_1_ACCESS "RO" -// ============================================================================= -// Register : M33_DWT_CIDR2 -// Description : Provides CoreSight discovery information for the DWT -#define M33_DWT_CIDR2_OFFSET _u(0x00001ff8) -#define M33_DWT_CIDR2_BITS _u(0x000000ff) -#define M33_DWT_CIDR2_RESET _u(0x00000005) -// ----------------------------------------------------------------------------- -// Field : M33_DWT_CIDR2_PRMBL_2 -// Description : See CoreSight Architecture Specification -#define M33_DWT_CIDR2_PRMBL_2_RESET _u(0x05) -#define M33_DWT_CIDR2_PRMBL_2_BITS _u(0x000000ff) -#define M33_DWT_CIDR2_PRMBL_2_MSB _u(7) -#define M33_DWT_CIDR2_PRMBL_2_LSB _u(0) -#define M33_DWT_CIDR2_PRMBL_2_ACCESS "RO" -// ============================================================================= -// Register : M33_DWT_CIDR3 -// Description : Provides CoreSight discovery information for the DWT -#define M33_DWT_CIDR3_OFFSET _u(0x00001ffc) -#define M33_DWT_CIDR3_BITS _u(0x000000ff) -#define M33_DWT_CIDR3_RESET _u(0x000000b1) -// ----------------------------------------------------------------------------- -// Field : M33_DWT_CIDR3_PRMBL_3 -// Description : See CoreSight Architecture Specification -#define M33_DWT_CIDR3_PRMBL_3_RESET _u(0xb1) -#define M33_DWT_CIDR3_PRMBL_3_BITS _u(0x000000ff) -#define M33_DWT_CIDR3_PRMBL_3_MSB _u(7) -#define M33_DWT_CIDR3_PRMBL_3_LSB _u(0) -#define M33_DWT_CIDR3_PRMBL_3_ACCESS "RO" -// ============================================================================= -// Register : M33_FP_CTRL -// Description : Provides FPB implementation information, and the global enable -// for the FPB unit -#define M33_FP_CTRL_OFFSET _u(0x00002000) -#define M33_FP_CTRL_BITS _u(0xf0007ff3) -#define M33_FP_CTRL_RESET _u(0x60005580) -// ----------------------------------------------------------------------------- -// Field : M33_FP_CTRL_REV -// Description : Flash Patch and Breakpoint Unit architecture revision -#define M33_FP_CTRL_REV_RESET _u(0x6) -#define M33_FP_CTRL_REV_BITS _u(0xf0000000) -#define M33_FP_CTRL_REV_MSB _u(31) -#define M33_FP_CTRL_REV_LSB _u(28) -#define M33_FP_CTRL_REV_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_FP_CTRL_NUM_CODE_14_12_ -// Description : Indicates the number of implemented instruction address -// comparators. Zero indicates no Instruction Address comparators -// are implemented. The Instruction Address comparators are -// numbered from 0 to NUM_CODE - 1 -#define M33_FP_CTRL_NUM_CODE_14_12__RESET _u(0x5) -#define M33_FP_CTRL_NUM_CODE_14_12__BITS _u(0x00007000) -#define M33_FP_CTRL_NUM_CODE_14_12__MSB _u(14) -#define M33_FP_CTRL_NUM_CODE_14_12__LSB _u(12) -#define M33_FP_CTRL_NUM_CODE_14_12__ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_FP_CTRL_NUM_LIT -// Description : Indicates the number of implemented literal address -// comparators. The Literal Address comparators are numbered from -// NUM_CODE to NUM_CODE + NUM_LIT - 1 -#define M33_FP_CTRL_NUM_LIT_RESET _u(0x5) -#define M33_FP_CTRL_NUM_LIT_BITS _u(0x00000f00) -#define M33_FP_CTRL_NUM_LIT_MSB _u(11) -#define M33_FP_CTRL_NUM_LIT_LSB _u(8) -#define M33_FP_CTRL_NUM_LIT_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_FP_CTRL_NUM_CODE_7_4_ -// Description : Indicates the number of implemented instruction address -// comparators. Zero indicates no Instruction Address comparators -// are implemented. The Instruction Address comparators are -// numbered from 0 to NUM_CODE - 1 -#define M33_FP_CTRL_NUM_CODE_7_4__RESET _u(0x8) -#define M33_FP_CTRL_NUM_CODE_7_4__BITS _u(0x000000f0) -#define M33_FP_CTRL_NUM_CODE_7_4__MSB _u(7) -#define M33_FP_CTRL_NUM_CODE_7_4__LSB _u(4) -#define M33_FP_CTRL_NUM_CODE_7_4__ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_FP_CTRL_KEY -// Description : Writes to the FP_CTRL are ignored unless KEY is concurrently -// written to one -#define M33_FP_CTRL_KEY_RESET _u(0x0) -#define M33_FP_CTRL_KEY_BITS _u(0x00000002) -#define M33_FP_CTRL_KEY_MSB _u(1) -#define M33_FP_CTRL_KEY_LSB _u(1) -#define M33_FP_CTRL_KEY_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_FP_CTRL_ENABLE -// Description : Enables the FPB -#define M33_FP_CTRL_ENABLE_RESET _u(0x0) -#define M33_FP_CTRL_ENABLE_BITS _u(0x00000001) -#define M33_FP_CTRL_ENABLE_MSB _u(0) -#define M33_FP_CTRL_ENABLE_LSB _u(0) -#define M33_FP_CTRL_ENABLE_ACCESS "RW" -// ============================================================================= -// Register : M33_FP_REMAP -// Description : Indicates whether the implementation supports Flash Patch remap -// and, if it does, holds the target address for remap -#define M33_FP_REMAP_OFFSET _u(0x00002004) -#define M33_FP_REMAP_BITS _u(0x3fffffe0) -#define M33_FP_REMAP_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_FP_REMAP_RMPSPT -// Description : Indicates whether the FPB unit supports the Flash Patch remap -// function -#define M33_FP_REMAP_RMPSPT_RESET _u(0x0) -#define M33_FP_REMAP_RMPSPT_BITS _u(0x20000000) -#define M33_FP_REMAP_RMPSPT_MSB _u(29) -#define M33_FP_REMAP_RMPSPT_LSB _u(29) -#define M33_FP_REMAP_RMPSPT_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_FP_REMAP_REMAP -// Description : Holds the bits[28:5] of the Flash Patch remap address -#define M33_FP_REMAP_REMAP_RESET _u(0x000000) -#define M33_FP_REMAP_REMAP_BITS _u(0x1fffffe0) -#define M33_FP_REMAP_REMAP_MSB _u(28) -#define M33_FP_REMAP_REMAP_LSB _u(5) -#define M33_FP_REMAP_REMAP_ACCESS "RO" -// ============================================================================= -// Register : M33_FP_COMP0 -// Description : Holds an address for comparison. The effect of the match -// depends on the configuration of the FPB and whether the -// comparator is an instruction address comparator or a literal -// address comparator -#define M33_FP_COMP0_OFFSET _u(0x00002008) -#define M33_FP_COMP0_BITS _u(0x00000001) -#define M33_FP_COMP0_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_FP_COMP0_BE -// Description : Selects between flashpatch and breakpoint functionality -#define M33_FP_COMP0_BE_RESET _u(0x0) -#define M33_FP_COMP0_BE_BITS _u(0x00000001) -#define M33_FP_COMP0_BE_MSB _u(0) -#define M33_FP_COMP0_BE_LSB _u(0) -#define M33_FP_COMP0_BE_ACCESS "RW" -// ============================================================================= -// Register : M33_FP_COMP1 -// Description : Holds an address for comparison. The effect of the match -// depends on the configuration of the FPB and whether the -// comparator is an instruction address comparator or a literal -// address comparator -#define M33_FP_COMP1_OFFSET _u(0x0000200c) -#define M33_FP_COMP1_BITS _u(0x00000001) -#define M33_FP_COMP1_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_FP_COMP1_BE -// Description : Selects between flashpatch and breakpoint functionality -#define M33_FP_COMP1_BE_RESET _u(0x0) -#define M33_FP_COMP1_BE_BITS _u(0x00000001) -#define M33_FP_COMP1_BE_MSB _u(0) -#define M33_FP_COMP1_BE_LSB _u(0) -#define M33_FP_COMP1_BE_ACCESS "RW" -// ============================================================================= -// Register : M33_FP_COMP2 -// Description : Holds an address for comparison. The effect of the match -// depends on the configuration of the FPB and whether the -// comparator is an instruction address comparator or a literal -// address comparator -#define M33_FP_COMP2_OFFSET _u(0x00002010) -#define M33_FP_COMP2_BITS _u(0x00000001) -#define M33_FP_COMP2_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_FP_COMP2_BE -// Description : Selects between flashpatch and breakpoint functionality -#define M33_FP_COMP2_BE_RESET _u(0x0) -#define M33_FP_COMP2_BE_BITS _u(0x00000001) -#define M33_FP_COMP2_BE_MSB _u(0) -#define M33_FP_COMP2_BE_LSB _u(0) -#define M33_FP_COMP2_BE_ACCESS "RW" -// ============================================================================= -// Register : M33_FP_COMP3 -// Description : Holds an address for comparison. The effect of the match -// depends on the configuration of the FPB and whether the -// comparator is an instruction address comparator or a literal -// address comparator -#define M33_FP_COMP3_OFFSET _u(0x00002014) -#define M33_FP_COMP3_BITS _u(0x00000001) -#define M33_FP_COMP3_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_FP_COMP3_BE -// Description : Selects between flashpatch and breakpoint functionality -#define M33_FP_COMP3_BE_RESET _u(0x0) -#define M33_FP_COMP3_BE_BITS _u(0x00000001) -#define M33_FP_COMP3_BE_MSB _u(0) -#define M33_FP_COMP3_BE_LSB _u(0) -#define M33_FP_COMP3_BE_ACCESS "RW" -// ============================================================================= -// Register : M33_FP_COMP4 -// Description : Holds an address for comparison. The effect of the match -// depends on the configuration of the FPB and whether the -// comparator is an instruction address comparator or a literal -// address comparator -#define M33_FP_COMP4_OFFSET _u(0x00002018) -#define M33_FP_COMP4_BITS _u(0x00000001) -#define M33_FP_COMP4_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_FP_COMP4_BE -// Description : Selects between flashpatch and breakpoint functionality -#define M33_FP_COMP4_BE_RESET _u(0x0) -#define M33_FP_COMP4_BE_BITS _u(0x00000001) -#define M33_FP_COMP4_BE_MSB _u(0) -#define M33_FP_COMP4_BE_LSB _u(0) -#define M33_FP_COMP4_BE_ACCESS "RW" -// ============================================================================= -// Register : M33_FP_COMP5 -// Description : Holds an address for comparison. The effect of the match -// depends on the configuration of the FPB and whether the -// comparator is an instruction address comparator or a literal -// address comparator -#define M33_FP_COMP5_OFFSET _u(0x0000201c) -#define M33_FP_COMP5_BITS _u(0x00000001) -#define M33_FP_COMP5_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_FP_COMP5_BE -// Description : Selects between flashpatch and breakpoint functionality -#define M33_FP_COMP5_BE_RESET _u(0x0) -#define M33_FP_COMP5_BE_BITS _u(0x00000001) -#define M33_FP_COMP5_BE_MSB _u(0) -#define M33_FP_COMP5_BE_LSB _u(0) -#define M33_FP_COMP5_BE_ACCESS "RW" -// ============================================================================= -// Register : M33_FP_COMP6 -// Description : Holds an address for comparison. The effect of the match -// depends on the configuration of the FPB and whether the -// comparator is an instruction address comparator or a literal -// address comparator -#define M33_FP_COMP6_OFFSET _u(0x00002020) -#define M33_FP_COMP6_BITS _u(0x00000001) -#define M33_FP_COMP6_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_FP_COMP6_BE -// Description : Selects between flashpatch and breakpoint functionality -#define M33_FP_COMP6_BE_RESET _u(0x0) -#define M33_FP_COMP6_BE_BITS _u(0x00000001) -#define M33_FP_COMP6_BE_MSB _u(0) -#define M33_FP_COMP6_BE_LSB _u(0) -#define M33_FP_COMP6_BE_ACCESS "RW" -// ============================================================================= -// Register : M33_FP_COMP7 -// Description : Holds an address for comparison. The effect of the match -// depends on the configuration of the FPB and whether the -// comparator is an instruction address comparator or a literal -// address comparator -#define M33_FP_COMP7_OFFSET _u(0x00002024) -#define M33_FP_COMP7_BITS _u(0x00000001) -#define M33_FP_COMP7_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_FP_COMP7_BE -// Description : Selects between flashpatch and breakpoint functionality -#define M33_FP_COMP7_BE_RESET _u(0x0) -#define M33_FP_COMP7_BE_BITS _u(0x00000001) -#define M33_FP_COMP7_BE_MSB _u(0) -#define M33_FP_COMP7_BE_LSB _u(0) -#define M33_FP_COMP7_BE_ACCESS "RW" -// ============================================================================= -// Register : M33_FP_DEVARCH -// Description : Provides CoreSight discovery information for the FPB -#define M33_FP_DEVARCH_OFFSET _u(0x00002fbc) -#define M33_FP_DEVARCH_BITS _u(0xffffffff) -#define M33_FP_DEVARCH_RESET _u(0x47701a03) -// ----------------------------------------------------------------------------- -// Field : M33_FP_DEVARCH_ARCHITECT -// Description : Defines the architect of the component. Bits [31:28] are the -// JEP106 continuation code (JEP106 bank ID, minus 1) and bits -// [27:21] are the JEP106 ID code. -#define M33_FP_DEVARCH_ARCHITECT_RESET _u(0x23b) -#define M33_FP_DEVARCH_ARCHITECT_BITS _u(0xffe00000) -#define M33_FP_DEVARCH_ARCHITECT_MSB _u(31) -#define M33_FP_DEVARCH_ARCHITECT_LSB _u(21) -#define M33_FP_DEVARCH_ARCHITECT_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_FP_DEVARCH_PRESENT -// Description : Defines that the DEVARCH register is present -#define M33_FP_DEVARCH_PRESENT_RESET _u(0x1) -#define M33_FP_DEVARCH_PRESENT_BITS _u(0x00100000) -#define M33_FP_DEVARCH_PRESENT_MSB _u(20) -#define M33_FP_DEVARCH_PRESENT_LSB _u(20) -#define M33_FP_DEVARCH_PRESENT_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_FP_DEVARCH_REVISION -// Description : Defines the architecture revision of the component -#define M33_FP_DEVARCH_REVISION_RESET _u(0x0) -#define M33_FP_DEVARCH_REVISION_BITS _u(0x000f0000) -#define M33_FP_DEVARCH_REVISION_MSB _u(19) -#define M33_FP_DEVARCH_REVISION_LSB _u(16) -#define M33_FP_DEVARCH_REVISION_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_FP_DEVARCH_ARCHVER -// Description : Defines the architecture version of the component -#define M33_FP_DEVARCH_ARCHVER_RESET _u(0x1) -#define M33_FP_DEVARCH_ARCHVER_BITS _u(0x0000f000) -#define M33_FP_DEVARCH_ARCHVER_MSB _u(15) -#define M33_FP_DEVARCH_ARCHVER_LSB _u(12) -#define M33_FP_DEVARCH_ARCHVER_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_FP_DEVARCH_ARCHPART -// Description : Defines the architecture of the component -#define M33_FP_DEVARCH_ARCHPART_RESET _u(0xa03) -#define M33_FP_DEVARCH_ARCHPART_BITS _u(0x00000fff) -#define M33_FP_DEVARCH_ARCHPART_MSB _u(11) -#define M33_FP_DEVARCH_ARCHPART_LSB _u(0) -#define M33_FP_DEVARCH_ARCHPART_ACCESS "RO" -// ============================================================================= -// Register : M33_FP_DEVTYPE -// Description : Provides CoreSight discovery information for the FPB -#define M33_FP_DEVTYPE_OFFSET _u(0x00002fcc) -#define M33_FP_DEVTYPE_BITS _u(0x000000ff) -#define M33_FP_DEVTYPE_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_FP_DEVTYPE_SUB -// Description : Component sub-type -#define M33_FP_DEVTYPE_SUB_RESET _u(0x0) -#define M33_FP_DEVTYPE_SUB_BITS _u(0x000000f0) -#define M33_FP_DEVTYPE_SUB_MSB _u(7) -#define M33_FP_DEVTYPE_SUB_LSB _u(4) -#define M33_FP_DEVTYPE_SUB_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_FP_DEVTYPE_MAJOR -// Description : Component major type -#define M33_FP_DEVTYPE_MAJOR_RESET _u(0x0) -#define M33_FP_DEVTYPE_MAJOR_BITS _u(0x0000000f) -#define M33_FP_DEVTYPE_MAJOR_MSB _u(3) -#define M33_FP_DEVTYPE_MAJOR_LSB _u(0) -#define M33_FP_DEVTYPE_MAJOR_ACCESS "RO" -// ============================================================================= -// Register : M33_FP_PIDR4 -// Description : Provides CoreSight discovery information for the FP -#define M33_FP_PIDR4_OFFSET _u(0x00002fd0) -#define M33_FP_PIDR4_BITS _u(0x000000ff) -#define M33_FP_PIDR4_RESET _u(0x00000004) -// ----------------------------------------------------------------------------- -// Field : M33_FP_PIDR4_SIZE -// Description : See CoreSight Architecture Specification -#define M33_FP_PIDR4_SIZE_RESET _u(0x0) -#define M33_FP_PIDR4_SIZE_BITS _u(0x000000f0) -#define M33_FP_PIDR4_SIZE_MSB _u(7) -#define M33_FP_PIDR4_SIZE_LSB _u(4) -#define M33_FP_PIDR4_SIZE_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_FP_PIDR4_DES_2 -// Description : See CoreSight Architecture Specification -#define M33_FP_PIDR4_DES_2_RESET _u(0x4) -#define M33_FP_PIDR4_DES_2_BITS _u(0x0000000f) -#define M33_FP_PIDR4_DES_2_MSB _u(3) -#define M33_FP_PIDR4_DES_2_LSB _u(0) -#define M33_FP_PIDR4_DES_2_ACCESS "RO" -// ============================================================================= -// Register : M33_FP_PIDR5 -// Description : Provides CoreSight discovery information for the FP -#define M33_FP_PIDR5_OFFSET _u(0x00002fd4) -#define M33_FP_PIDR5_BITS _u(0x00000000) -#define M33_FP_PIDR5_RESET _u(0x00000000) -#define M33_FP_PIDR5_MSB _u(31) -#define M33_FP_PIDR5_LSB _u(0) -#define M33_FP_PIDR5_ACCESS "RW" -// ============================================================================= -// Register : M33_FP_PIDR6 -// Description : Provides CoreSight discovery information for the FP -#define M33_FP_PIDR6_OFFSET _u(0x00002fd8) -#define M33_FP_PIDR6_BITS _u(0x00000000) -#define M33_FP_PIDR6_RESET _u(0x00000000) -#define M33_FP_PIDR6_MSB _u(31) -#define M33_FP_PIDR6_LSB _u(0) -#define M33_FP_PIDR6_ACCESS "RW" -// ============================================================================= -// Register : M33_FP_PIDR7 -// Description : Provides CoreSight discovery information for the FP -#define M33_FP_PIDR7_OFFSET _u(0x00002fdc) -#define M33_FP_PIDR7_BITS _u(0x00000000) -#define M33_FP_PIDR7_RESET _u(0x00000000) -#define M33_FP_PIDR7_MSB _u(31) -#define M33_FP_PIDR7_LSB _u(0) -#define M33_FP_PIDR7_ACCESS "RW" -// ============================================================================= -// Register : M33_FP_PIDR0 -// Description : Provides CoreSight discovery information for the FP -#define M33_FP_PIDR0_OFFSET _u(0x00002fe0) -#define M33_FP_PIDR0_BITS _u(0x000000ff) -#define M33_FP_PIDR0_RESET _u(0x00000021) -// ----------------------------------------------------------------------------- -// Field : M33_FP_PIDR0_PART_0 -// Description : See CoreSight Architecture Specification -#define M33_FP_PIDR0_PART_0_RESET _u(0x21) -#define M33_FP_PIDR0_PART_0_BITS _u(0x000000ff) -#define M33_FP_PIDR0_PART_0_MSB _u(7) -#define M33_FP_PIDR0_PART_0_LSB _u(0) -#define M33_FP_PIDR0_PART_0_ACCESS "RO" -// ============================================================================= -// Register : M33_FP_PIDR1 -// Description : Provides CoreSight discovery information for the FP -#define M33_FP_PIDR1_OFFSET _u(0x00002fe4) -#define M33_FP_PIDR1_BITS _u(0x000000ff) -#define M33_FP_PIDR1_RESET _u(0x000000bd) -// ----------------------------------------------------------------------------- -// Field : M33_FP_PIDR1_DES_0 -// Description : See CoreSight Architecture Specification -#define M33_FP_PIDR1_DES_0_RESET _u(0xb) -#define M33_FP_PIDR1_DES_0_BITS _u(0x000000f0) -#define M33_FP_PIDR1_DES_0_MSB _u(7) -#define M33_FP_PIDR1_DES_0_LSB _u(4) -#define M33_FP_PIDR1_DES_0_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_FP_PIDR1_PART_1 -// Description : See CoreSight Architecture Specification -#define M33_FP_PIDR1_PART_1_RESET _u(0xd) -#define M33_FP_PIDR1_PART_1_BITS _u(0x0000000f) -#define M33_FP_PIDR1_PART_1_MSB _u(3) -#define M33_FP_PIDR1_PART_1_LSB _u(0) -#define M33_FP_PIDR1_PART_1_ACCESS "RO" -// ============================================================================= -// Register : M33_FP_PIDR2 -// Description : Provides CoreSight discovery information for the FP -#define M33_FP_PIDR2_OFFSET _u(0x00002fe8) -#define M33_FP_PIDR2_BITS _u(0x000000ff) -#define M33_FP_PIDR2_RESET _u(0x0000000b) -// ----------------------------------------------------------------------------- -// Field : M33_FP_PIDR2_REVISION -// Description : See CoreSight Architecture Specification -#define M33_FP_PIDR2_REVISION_RESET _u(0x0) -#define M33_FP_PIDR2_REVISION_BITS _u(0x000000f0) -#define M33_FP_PIDR2_REVISION_MSB _u(7) -#define M33_FP_PIDR2_REVISION_LSB _u(4) -#define M33_FP_PIDR2_REVISION_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_FP_PIDR2_JEDEC -// Description : See CoreSight Architecture Specification -#define M33_FP_PIDR2_JEDEC_RESET _u(0x1) -#define M33_FP_PIDR2_JEDEC_BITS _u(0x00000008) -#define M33_FP_PIDR2_JEDEC_MSB _u(3) -#define M33_FP_PIDR2_JEDEC_LSB _u(3) -#define M33_FP_PIDR2_JEDEC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_FP_PIDR2_DES_1 -// Description : See CoreSight Architecture Specification -#define M33_FP_PIDR2_DES_1_RESET _u(0x3) -#define M33_FP_PIDR2_DES_1_BITS _u(0x00000007) -#define M33_FP_PIDR2_DES_1_MSB _u(2) -#define M33_FP_PIDR2_DES_1_LSB _u(0) -#define M33_FP_PIDR2_DES_1_ACCESS "RO" -// ============================================================================= -// Register : M33_FP_PIDR3 -// Description : Provides CoreSight discovery information for the FP -#define M33_FP_PIDR3_OFFSET _u(0x00002fec) -#define M33_FP_PIDR3_BITS _u(0x000000ff) -#define M33_FP_PIDR3_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_FP_PIDR3_REVAND -// Description : See CoreSight Architecture Specification -#define M33_FP_PIDR3_REVAND_RESET _u(0x0) -#define M33_FP_PIDR3_REVAND_BITS _u(0x000000f0) -#define M33_FP_PIDR3_REVAND_MSB _u(7) -#define M33_FP_PIDR3_REVAND_LSB _u(4) -#define M33_FP_PIDR3_REVAND_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_FP_PIDR3_CMOD -// Description : See CoreSight Architecture Specification -#define M33_FP_PIDR3_CMOD_RESET _u(0x0) -#define M33_FP_PIDR3_CMOD_BITS _u(0x0000000f) -#define M33_FP_PIDR3_CMOD_MSB _u(3) -#define M33_FP_PIDR3_CMOD_LSB _u(0) -#define M33_FP_PIDR3_CMOD_ACCESS "RO" -// ============================================================================= -// Register : M33_FP_CIDR0 -// Description : Provides CoreSight discovery information for the FP -#define M33_FP_CIDR0_OFFSET _u(0x00002ff0) -#define M33_FP_CIDR0_BITS _u(0x000000ff) -#define M33_FP_CIDR0_RESET _u(0x0000000d) -// ----------------------------------------------------------------------------- -// Field : M33_FP_CIDR0_PRMBL_0 -// Description : See CoreSight Architecture Specification -#define M33_FP_CIDR0_PRMBL_0_RESET _u(0x0d) -#define M33_FP_CIDR0_PRMBL_0_BITS _u(0x000000ff) -#define M33_FP_CIDR0_PRMBL_0_MSB _u(7) -#define M33_FP_CIDR0_PRMBL_0_LSB _u(0) -#define M33_FP_CIDR0_PRMBL_0_ACCESS "RO" -// ============================================================================= -// Register : M33_FP_CIDR1 -// Description : Provides CoreSight discovery information for the FP -#define M33_FP_CIDR1_OFFSET _u(0x00002ff4) -#define M33_FP_CIDR1_BITS _u(0x000000ff) -#define M33_FP_CIDR1_RESET _u(0x00000090) -// ----------------------------------------------------------------------------- -// Field : M33_FP_CIDR1_CLASS -// Description : See CoreSight Architecture Specification -#define M33_FP_CIDR1_CLASS_RESET _u(0x9) -#define M33_FP_CIDR1_CLASS_BITS _u(0x000000f0) -#define M33_FP_CIDR1_CLASS_MSB _u(7) -#define M33_FP_CIDR1_CLASS_LSB _u(4) -#define M33_FP_CIDR1_CLASS_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_FP_CIDR1_PRMBL_1 -// Description : See CoreSight Architecture Specification -#define M33_FP_CIDR1_PRMBL_1_RESET _u(0x0) -#define M33_FP_CIDR1_PRMBL_1_BITS _u(0x0000000f) -#define M33_FP_CIDR1_PRMBL_1_MSB _u(3) -#define M33_FP_CIDR1_PRMBL_1_LSB _u(0) -#define M33_FP_CIDR1_PRMBL_1_ACCESS "RO" -// ============================================================================= -// Register : M33_FP_CIDR2 -// Description : Provides CoreSight discovery information for the FP -#define M33_FP_CIDR2_OFFSET _u(0x00002ff8) -#define M33_FP_CIDR2_BITS _u(0x000000ff) -#define M33_FP_CIDR2_RESET _u(0x00000005) -// ----------------------------------------------------------------------------- -// Field : M33_FP_CIDR2_PRMBL_2 -// Description : See CoreSight Architecture Specification -#define M33_FP_CIDR2_PRMBL_2_RESET _u(0x05) -#define M33_FP_CIDR2_PRMBL_2_BITS _u(0x000000ff) -#define M33_FP_CIDR2_PRMBL_2_MSB _u(7) -#define M33_FP_CIDR2_PRMBL_2_LSB _u(0) -#define M33_FP_CIDR2_PRMBL_2_ACCESS "RO" -// ============================================================================= -// Register : M33_FP_CIDR3 -// Description : Provides CoreSight discovery information for the FP -#define M33_FP_CIDR3_OFFSET _u(0x00002ffc) -#define M33_FP_CIDR3_BITS _u(0x000000ff) -#define M33_FP_CIDR3_RESET _u(0x000000b1) -// ----------------------------------------------------------------------------- -// Field : M33_FP_CIDR3_PRMBL_3 -// Description : See CoreSight Architecture Specification -#define M33_FP_CIDR3_PRMBL_3_RESET _u(0xb1) -#define M33_FP_CIDR3_PRMBL_3_BITS _u(0x000000ff) -#define M33_FP_CIDR3_PRMBL_3_MSB _u(7) -#define M33_FP_CIDR3_PRMBL_3_LSB _u(0) -#define M33_FP_CIDR3_PRMBL_3_ACCESS "RO" -// ============================================================================= -// Register : M33_ICTR -// Description : Provides information about the interrupt controller -#define M33_ICTR_OFFSET _u(0x0000e004) -#define M33_ICTR_BITS _u(0x0000000f) -#define M33_ICTR_RESET _u(0x00000001) -// ----------------------------------------------------------------------------- -// Field : M33_ICTR_INTLINESNUM -// Description : Indicates the number of the highest implemented register in -// each of the NVIC control register sets, or in the case of -// NVIC_IPR*n, 4×INTLINESNUM -#define M33_ICTR_INTLINESNUM_RESET _u(0x1) -#define M33_ICTR_INTLINESNUM_BITS _u(0x0000000f) -#define M33_ICTR_INTLINESNUM_MSB _u(3) -#define M33_ICTR_INTLINESNUM_LSB _u(0) -#define M33_ICTR_INTLINESNUM_ACCESS "RO" -// ============================================================================= -// Register : M33_ACTLR -// Description : Provides IMPLEMENTATION DEFINED configuration and control -// options -#define M33_ACTLR_OFFSET _u(0x0000e008) -#define M33_ACTLR_BITS _u(0x20001605) -#define M33_ACTLR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_ACTLR_EXTEXCLALL -// Description : External Exclusives Allowed with no MPU -#define M33_ACTLR_EXTEXCLALL_RESET _u(0x0) -#define M33_ACTLR_EXTEXCLALL_BITS _u(0x20000000) -#define M33_ACTLR_EXTEXCLALL_MSB _u(29) -#define M33_ACTLR_EXTEXCLALL_LSB _u(29) -#define M33_ACTLR_EXTEXCLALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_ACTLR_DISITMATBFLUSH -// Description : Disable ATB Flush -#define M33_ACTLR_DISITMATBFLUSH_RESET _u(0x0) -#define M33_ACTLR_DISITMATBFLUSH_BITS _u(0x00001000) -#define M33_ACTLR_DISITMATBFLUSH_MSB _u(12) -#define M33_ACTLR_DISITMATBFLUSH_LSB _u(12) -#define M33_ACTLR_DISITMATBFLUSH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_ACTLR_FPEXCODIS -// Description : Disable FPU exception outputs -#define M33_ACTLR_FPEXCODIS_RESET _u(0x0) -#define M33_ACTLR_FPEXCODIS_BITS _u(0x00000400) -#define M33_ACTLR_FPEXCODIS_MSB _u(10) -#define M33_ACTLR_FPEXCODIS_LSB _u(10) -#define M33_ACTLR_FPEXCODIS_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_ACTLR_DISOOFP -// Description : Disable out-of-order FP instruction completion -#define M33_ACTLR_DISOOFP_RESET _u(0x0) -#define M33_ACTLR_DISOOFP_BITS _u(0x00000200) -#define M33_ACTLR_DISOOFP_MSB _u(9) -#define M33_ACTLR_DISOOFP_LSB _u(9) -#define M33_ACTLR_DISOOFP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_ACTLR_DISFOLD -// Description : Disable dual-issue. -#define M33_ACTLR_DISFOLD_RESET _u(0x0) -#define M33_ACTLR_DISFOLD_BITS _u(0x00000004) -#define M33_ACTLR_DISFOLD_MSB _u(2) -#define M33_ACTLR_DISFOLD_LSB _u(2) -#define M33_ACTLR_DISFOLD_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_ACTLR_DISMCYCINT -// Description : Disable dual-issue. -#define M33_ACTLR_DISMCYCINT_RESET _u(0x0) -#define M33_ACTLR_DISMCYCINT_BITS _u(0x00000001) -#define M33_ACTLR_DISMCYCINT_MSB _u(0) -#define M33_ACTLR_DISMCYCINT_LSB _u(0) -#define M33_ACTLR_DISMCYCINT_ACCESS "RW" -// ============================================================================= -// Register : M33_SYST_CSR -// Description : Use the SysTick Control and Status Register to enable the -// SysTick features. -#define M33_SYST_CSR_OFFSET _u(0x0000e010) -#define M33_SYST_CSR_BITS _u(0x00010007) -#define M33_SYST_CSR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_SYST_CSR_COUNTFLAG -// Description : Returns 1 if timer counted to 0 since last time this was read. -// Clears on read by application or debugger. -#define M33_SYST_CSR_COUNTFLAG_RESET _u(0x0) -#define M33_SYST_CSR_COUNTFLAG_BITS _u(0x00010000) -#define M33_SYST_CSR_COUNTFLAG_MSB _u(16) -#define M33_SYST_CSR_COUNTFLAG_LSB _u(16) -#define M33_SYST_CSR_COUNTFLAG_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_SYST_CSR_CLKSOURCE -// Description : SysTick clock source. Always reads as one if SYST_CALIB reports -// NOREF. -// Selects the SysTick timer clock source: -// 0 = External reference clock. -// 1 = Processor clock. -#define M33_SYST_CSR_CLKSOURCE_RESET _u(0x0) -#define M33_SYST_CSR_CLKSOURCE_BITS _u(0x00000004) -#define M33_SYST_CSR_CLKSOURCE_MSB _u(2) -#define M33_SYST_CSR_CLKSOURCE_LSB _u(2) -#define M33_SYST_CSR_CLKSOURCE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_SYST_CSR_TICKINT -// Description : Enables SysTick exception request: -// 0 = Counting down to zero does not assert the SysTick exception -// request. -// 1 = Counting down to zero to asserts the SysTick exception -// request. -#define M33_SYST_CSR_TICKINT_RESET _u(0x0) -#define M33_SYST_CSR_TICKINT_BITS _u(0x00000002) -#define M33_SYST_CSR_TICKINT_MSB _u(1) -#define M33_SYST_CSR_TICKINT_LSB _u(1) -#define M33_SYST_CSR_TICKINT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_SYST_CSR_ENABLE -// Description : Enable SysTick counter: -// 0 = Counter disabled. -// 1 = Counter enabled. -#define M33_SYST_CSR_ENABLE_RESET _u(0x0) -#define M33_SYST_CSR_ENABLE_BITS _u(0x00000001) -#define M33_SYST_CSR_ENABLE_MSB _u(0) -#define M33_SYST_CSR_ENABLE_LSB _u(0) -#define M33_SYST_CSR_ENABLE_ACCESS "RW" -// ============================================================================= -// Register : M33_SYST_RVR -// Description : Use the SysTick Reload Value Register to specify the start -// value to load into the current value register when the counter -// reaches 0. It can be any value between 0 and 0x00FFFFFF. A -// start value of 0 is possible, but has no effect because the -// SysTick interrupt and COUNTFLAG are activated when counting -// from 1 to 0. The reset value of this register is UNKNOWN. -// To generate a multi-shot timer with a period of N processor -// clock cycles, use a RELOAD value of N-1. For example, if the -// SysTick interrupt is required every 100 clock pulses, set -// RELOAD to 99. -#define M33_SYST_RVR_OFFSET _u(0x0000e014) -#define M33_SYST_RVR_BITS _u(0x00ffffff) -#define M33_SYST_RVR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_SYST_RVR_RELOAD -// Description : Value to load into the SysTick Current Value Register when the -// counter reaches 0. -#define M33_SYST_RVR_RELOAD_RESET _u(0x000000) -#define M33_SYST_RVR_RELOAD_BITS _u(0x00ffffff) -#define M33_SYST_RVR_RELOAD_MSB _u(23) -#define M33_SYST_RVR_RELOAD_LSB _u(0) -#define M33_SYST_RVR_RELOAD_ACCESS "RW" -// ============================================================================= -// Register : M33_SYST_CVR -// Description : Use the SysTick Current Value Register to find the current -// value in the register. The reset value of this register is -// UNKNOWN. -#define M33_SYST_CVR_OFFSET _u(0x0000e018) -#define M33_SYST_CVR_BITS _u(0x00ffffff) -#define M33_SYST_CVR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_SYST_CVR_CURRENT -// Description : Reads return the current value of the SysTick counter. This -// register is write-clear. Writing to it with any value clears -// the register to 0. Clearing this register also clears the -// COUNTFLAG bit of the SysTick Control and Status Register. -#define M33_SYST_CVR_CURRENT_RESET _u(0x000000) -#define M33_SYST_CVR_CURRENT_BITS _u(0x00ffffff) -#define M33_SYST_CVR_CURRENT_MSB _u(23) -#define M33_SYST_CVR_CURRENT_LSB _u(0) -#define M33_SYST_CVR_CURRENT_ACCESS "RW" -// ============================================================================= -// Register : M33_SYST_CALIB -// Description : Use the SysTick Calibration Value Register to enable software -// to scale to any required speed using divide and multiply. -#define M33_SYST_CALIB_OFFSET _u(0x0000e01c) -#define M33_SYST_CALIB_BITS _u(0xc0ffffff) -#define M33_SYST_CALIB_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_SYST_CALIB_NOREF -// Description : If reads as 1, the Reference clock is not provided - the -// CLKSOURCE bit of the SysTick Control and Status register will -// be forced to 1 and cannot be cleared to 0. -#define M33_SYST_CALIB_NOREF_RESET _u(0x0) -#define M33_SYST_CALIB_NOREF_BITS _u(0x80000000) -#define M33_SYST_CALIB_NOREF_MSB _u(31) -#define M33_SYST_CALIB_NOREF_LSB _u(31) -#define M33_SYST_CALIB_NOREF_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_SYST_CALIB_SKEW -// Description : If reads as 1, the calibration value for 10ms is inexact (due -// to clock frequency). -#define M33_SYST_CALIB_SKEW_RESET _u(0x0) -#define M33_SYST_CALIB_SKEW_BITS _u(0x40000000) -#define M33_SYST_CALIB_SKEW_MSB _u(30) -#define M33_SYST_CALIB_SKEW_LSB _u(30) -#define M33_SYST_CALIB_SKEW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_SYST_CALIB_TENMS -// Description : An optional Reload value to be used for 10ms (100Hz) timing, -// subject to system clock skew errors. If the value reads as 0, -// the calibration value is not known. -#define M33_SYST_CALIB_TENMS_RESET _u(0x000000) -#define M33_SYST_CALIB_TENMS_BITS _u(0x00ffffff) -#define M33_SYST_CALIB_TENMS_MSB _u(23) -#define M33_SYST_CALIB_TENMS_LSB _u(0) -#define M33_SYST_CALIB_TENMS_ACCESS "RO" -// ============================================================================= -// Register : M33_NVIC_ISER0 -// Description : Enables or reads the enabled state of each group of 32 -// interrupts -#define M33_NVIC_ISER0_OFFSET _u(0x0000e100) -#define M33_NVIC_ISER0_BITS _u(0xffffffff) -#define M33_NVIC_ISER0_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_NVIC_ISER0_SETENA -// Description : For SETENA[m] in NVIC_ISER*n, indicates whether interrupt 32*n -// + m is enabled -#define M33_NVIC_ISER0_SETENA_RESET _u(0x00000000) -#define M33_NVIC_ISER0_SETENA_BITS _u(0xffffffff) -#define M33_NVIC_ISER0_SETENA_MSB _u(31) -#define M33_NVIC_ISER0_SETENA_LSB _u(0) -#define M33_NVIC_ISER0_SETENA_ACCESS "RW" -// ============================================================================= -// Register : M33_NVIC_ISER1 -// Description : Enables or reads the enabled state of each group of 32 -// interrupts -#define M33_NVIC_ISER1_OFFSET _u(0x0000e104) -#define M33_NVIC_ISER1_BITS _u(0xffffffff) -#define M33_NVIC_ISER1_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_NVIC_ISER1_SETENA -// Description : For SETENA[m] in NVIC_ISER*n, indicates whether interrupt 32*n -// + m is enabled -#define M33_NVIC_ISER1_SETENA_RESET _u(0x00000000) -#define M33_NVIC_ISER1_SETENA_BITS _u(0xffffffff) -#define M33_NVIC_ISER1_SETENA_MSB _u(31) -#define M33_NVIC_ISER1_SETENA_LSB _u(0) -#define M33_NVIC_ISER1_SETENA_ACCESS "RW" -// ============================================================================= -// Register : M33_NVIC_ICER0 -// Description : Clears or reads the enabled state of each group of 32 -// interrupts -#define M33_NVIC_ICER0_OFFSET _u(0x0000e180) -#define M33_NVIC_ICER0_BITS _u(0xffffffff) -#define M33_NVIC_ICER0_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_NVIC_ICER0_CLRENA -// Description : For CLRENA[m] in NVIC_ICER*n, indicates whether interrupt 32*n -// + m is enabled -#define M33_NVIC_ICER0_CLRENA_RESET _u(0x00000000) -#define M33_NVIC_ICER0_CLRENA_BITS _u(0xffffffff) -#define M33_NVIC_ICER0_CLRENA_MSB _u(31) -#define M33_NVIC_ICER0_CLRENA_LSB _u(0) -#define M33_NVIC_ICER0_CLRENA_ACCESS "RW" -// ============================================================================= -// Register : M33_NVIC_ICER1 -// Description : Clears or reads the enabled state of each group of 32 -// interrupts -#define M33_NVIC_ICER1_OFFSET _u(0x0000e184) -#define M33_NVIC_ICER1_BITS _u(0xffffffff) -#define M33_NVIC_ICER1_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_NVIC_ICER1_CLRENA -// Description : For CLRENA[m] in NVIC_ICER*n, indicates whether interrupt 32*n -// + m is enabled -#define M33_NVIC_ICER1_CLRENA_RESET _u(0x00000000) -#define M33_NVIC_ICER1_CLRENA_BITS _u(0xffffffff) -#define M33_NVIC_ICER1_CLRENA_MSB _u(31) -#define M33_NVIC_ICER1_CLRENA_LSB _u(0) -#define M33_NVIC_ICER1_CLRENA_ACCESS "RW" -// ============================================================================= -// Register : M33_NVIC_ISPR0 -// Description : Enables or reads the pending state of each group of 32 -// interrupts -#define M33_NVIC_ISPR0_OFFSET _u(0x0000e200) -#define M33_NVIC_ISPR0_BITS _u(0xffffffff) -#define M33_NVIC_ISPR0_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_NVIC_ISPR0_SETPEND -// Description : For SETPEND[m] in NVIC_ISPR*n, indicates whether interrupt 32*n -// + m is pending -#define M33_NVIC_ISPR0_SETPEND_RESET _u(0x00000000) -#define M33_NVIC_ISPR0_SETPEND_BITS _u(0xffffffff) -#define M33_NVIC_ISPR0_SETPEND_MSB _u(31) -#define M33_NVIC_ISPR0_SETPEND_LSB _u(0) -#define M33_NVIC_ISPR0_SETPEND_ACCESS "RW" -// ============================================================================= -// Register : M33_NVIC_ISPR1 -// Description : Enables or reads the pending state of each group of 32 -// interrupts -#define M33_NVIC_ISPR1_OFFSET _u(0x0000e204) -#define M33_NVIC_ISPR1_BITS _u(0xffffffff) -#define M33_NVIC_ISPR1_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_NVIC_ISPR1_SETPEND -// Description : For SETPEND[m] in NVIC_ISPR*n, indicates whether interrupt 32*n -// + m is pending -#define M33_NVIC_ISPR1_SETPEND_RESET _u(0x00000000) -#define M33_NVIC_ISPR1_SETPEND_BITS _u(0xffffffff) -#define M33_NVIC_ISPR1_SETPEND_MSB _u(31) -#define M33_NVIC_ISPR1_SETPEND_LSB _u(0) -#define M33_NVIC_ISPR1_SETPEND_ACCESS "RW" -// ============================================================================= -// Register : M33_NVIC_ICPR0 -// Description : Clears or reads the pending state of each group of 32 -// interrupts -#define M33_NVIC_ICPR0_OFFSET _u(0x0000e280) -#define M33_NVIC_ICPR0_BITS _u(0xffffffff) -#define M33_NVIC_ICPR0_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_NVIC_ICPR0_CLRPEND -// Description : For CLRPEND[m] in NVIC_ICPR*n, indicates whether interrupt 32*n -// + m is pending -#define M33_NVIC_ICPR0_CLRPEND_RESET _u(0x00000000) -#define M33_NVIC_ICPR0_CLRPEND_BITS _u(0xffffffff) -#define M33_NVIC_ICPR0_CLRPEND_MSB _u(31) -#define M33_NVIC_ICPR0_CLRPEND_LSB _u(0) -#define M33_NVIC_ICPR0_CLRPEND_ACCESS "RW" -// ============================================================================= -// Register : M33_NVIC_ICPR1 -// Description : Clears or reads the pending state of each group of 32 -// interrupts -#define M33_NVIC_ICPR1_OFFSET _u(0x0000e284) -#define M33_NVIC_ICPR1_BITS _u(0xffffffff) -#define M33_NVIC_ICPR1_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_NVIC_ICPR1_CLRPEND -// Description : For CLRPEND[m] in NVIC_ICPR*n, indicates whether interrupt 32*n -// + m is pending -#define M33_NVIC_ICPR1_CLRPEND_RESET _u(0x00000000) -#define M33_NVIC_ICPR1_CLRPEND_BITS _u(0xffffffff) -#define M33_NVIC_ICPR1_CLRPEND_MSB _u(31) -#define M33_NVIC_ICPR1_CLRPEND_LSB _u(0) -#define M33_NVIC_ICPR1_CLRPEND_ACCESS "RW" -// ============================================================================= -// Register : M33_NVIC_IABR0 -// Description : For each group of 32 interrupts, shows the active state of each -// interrupt -#define M33_NVIC_IABR0_OFFSET _u(0x0000e300) -#define M33_NVIC_IABR0_BITS _u(0xffffffff) -#define M33_NVIC_IABR0_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_NVIC_IABR0_ACTIVE -// Description : For ACTIVE[m] in NVIC_IABR*n, indicates the active state for -// interrupt 32*n+m -#define M33_NVIC_IABR0_ACTIVE_RESET _u(0x00000000) -#define M33_NVIC_IABR0_ACTIVE_BITS _u(0xffffffff) -#define M33_NVIC_IABR0_ACTIVE_MSB _u(31) -#define M33_NVIC_IABR0_ACTIVE_LSB _u(0) -#define M33_NVIC_IABR0_ACTIVE_ACCESS "RW" -// ============================================================================= -// Register : M33_NVIC_IABR1 -// Description : For each group of 32 interrupts, shows the active state of each -// interrupt -#define M33_NVIC_IABR1_OFFSET _u(0x0000e304) -#define M33_NVIC_IABR1_BITS _u(0xffffffff) -#define M33_NVIC_IABR1_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_NVIC_IABR1_ACTIVE -// Description : For ACTIVE[m] in NVIC_IABR*n, indicates the active state for -// interrupt 32*n+m -#define M33_NVIC_IABR1_ACTIVE_RESET _u(0x00000000) -#define M33_NVIC_IABR1_ACTIVE_BITS _u(0xffffffff) -#define M33_NVIC_IABR1_ACTIVE_MSB _u(31) -#define M33_NVIC_IABR1_ACTIVE_LSB _u(0) -#define M33_NVIC_IABR1_ACTIVE_ACCESS "RW" -// ============================================================================= -// Register : M33_NVIC_ITNS0 -// Description : For each group of 32 interrupts, determines whether each -// interrupt targets Non-secure or Secure state -#define M33_NVIC_ITNS0_OFFSET _u(0x0000e380) -#define M33_NVIC_ITNS0_BITS _u(0xffffffff) -#define M33_NVIC_ITNS0_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_NVIC_ITNS0_ITNS -// Description : For ITNS[m] in NVIC_ITNS*n, `IAAMO the target Security state -// for interrupt 32*n+m -#define M33_NVIC_ITNS0_ITNS_RESET _u(0x00000000) -#define M33_NVIC_ITNS0_ITNS_BITS _u(0xffffffff) -#define M33_NVIC_ITNS0_ITNS_MSB _u(31) -#define M33_NVIC_ITNS0_ITNS_LSB _u(0) -#define M33_NVIC_ITNS0_ITNS_ACCESS "RW" -// ============================================================================= -// Register : M33_NVIC_ITNS1 -// Description : For each group of 32 interrupts, determines whether each -// interrupt targets Non-secure or Secure state -#define M33_NVIC_ITNS1_OFFSET _u(0x0000e384) -#define M33_NVIC_ITNS1_BITS _u(0xffffffff) -#define M33_NVIC_ITNS1_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_NVIC_ITNS1_ITNS -// Description : For ITNS[m] in NVIC_ITNS*n, `IAAMO the target Security state -// for interrupt 32*n+m -#define M33_NVIC_ITNS1_ITNS_RESET _u(0x00000000) -#define M33_NVIC_ITNS1_ITNS_BITS _u(0xffffffff) -#define M33_NVIC_ITNS1_ITNS_MSB _u(31) -#define M33_NVIC_ITNS1_ITNS_LSB _u(0) -#define M33_NVIC_ITNS1_ITNS_ACCESS "RW" -// ============================================================================= -// Register : M33_NVIC_IPR0 -// Description : Sets or reads interrupt priorities -#define M33_NVIC_IPR0_OFFSET _u(0x0000e400) -#define M33_NVIC_IPR0_BITS _u(0xf0f0f0f0) -#define M33_NVIC_IPR0_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_NVIC_IPR0_PRI_N3 -// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+3, -// or RES0 if the PE does not implement this interrupt -#define M33_NVIC_IPR0_PRI_N3_RESET _u(0x0) -#define M33_NVIC_IPR0_PRI_N3_BITS _u(0xf0000000) -#define M33_NVIC_IPR0_PRI_N3_MSB _u(31) -#define M33_NVIC_IPR0_PRI_N3_LSB _u(28) -#define M33_NVIC_IPR0_PRI_N3_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_NVIC_IPR0_PRI_N2 -// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+2, -// or RES0 if the PE does not implement this interrupt -#define M33_NVIC_IPR0_PRI_N2_RESET _u(0x0) -#define M33_NVIC_IPR0_PRI_N2_BITS _u(0x00f00000) -#define M33_NVIC_IPR0_PRI_N2_MSB _u(23) -#define M33_NVIC_IPR0_PRI_N2_LSB _u(20) -#define M33_NVIC_IPR0_PRI_N2_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_NVIC_IPR0_PRI_N1 -// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+1, -// or RES0 if the PE does not implement this interrupt -#define M33_NVIC_IPR0_PRI_N1_RESET _u(0x0) -#define M33_NVIC_IPR0_PRI_N1_BITS _u(0x0000f000) -#define M33_NVIC_IPR0_PRI_N1_MSB _u(15) -#define M33_NVIC_IPR0_PRI_N1_LSB _u(12) -#define M33_NVIC_IPR0_PRI_N1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_NVIC_IPR0_PRI_N0 -// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+0, -// or RES0 if the PE does not implement this interrupt -#define M33_NVIC_IPR0_PRI_N0_RESET _u(0x0) -#define M33_NVIC_IPR0_PRI_N0_BITS _u(0x000000f0) -#define M33_NVIC_IPR0_PRI_N0_MSB _u(7) -#define M33_NVIC_IPR0_PRI_N0_LSB _u(4) -#define M33_NVIC_IPR0_PRI_N0_ACCESS "RW" -// ============================================================================= -// Register : M33_NVIC_IPR1 -// Description : Sets or reads interrupt priorities -#define M33_NVIC_IPR1_OFFSET _u(0x0000e404) -#define M33_NVIC_IPR1_BITS _u(0xf0f0f0f0) -#define M33_NVIC_IPR1_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_NVIC_IPR1_PRI_N3 -// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+3, -// or RES0 if the PE does not implement this interrupt -#define M33_NVIC_IPR1_PRI_N3_RESET _u(0x0) -#define M33_NVIC_IPR1_PRI_N3_BITS _u(0xf0000000) -#define M33_NVIC_IPR1_PRI_N3_MSB _u(31) -#define M33_NVIC_IPR1_PRI_N3_LSB _u(28) -#define M33_NVIC_IPR1_PRI_N3_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_NVIC_IPR1_PRI_N2 -// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+2, -// or RES0 if the PE does not implement this interrupt -#define M33_NVIC_IPR1_PRI_N2_RESET _u(0x0) -#define M33_NVIC_IPR1_PRI_N2_BITS _u(0x00f00000) -#define M33_NVIC_IPR1_PRI_N2_MSB _u(23) -#define M33_NVIC_IPR1_PRI_N2_LSB _u(20) -#define M33_NVIC_IPR1_PRI_N2_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_NVIC_IPR1_PRI_N1 -// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+1, -// or RES0 if the PE does not implement this interrupt -#define M33_NVIC_IPR1_PRI_N1_RESET _u(0x0) -#define M33_NVIC_IPR1_PRI_N1_BITS _u(0x0000f000) -#define M33_NVIC_IPR1_PRI_N1_MSB _u(15) -#define M33_NVIC_IPR1_PRI_N1_LSB _u(12) -#define M33_NVIC_IPR1_PRI_N1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_NVIC_IPR1_PRI_N0 -// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+0, -// or RES0 if the PE does not implement this interrupt -#define M33_NVIC_IPR1_PRI_N0_RESET _u(0x0) -#define M33_NVIC_IPR1_PRI_N0_BITS _u(0x000000f0) -#define M33_NVIC_IPR1_PRI_N0_MSB _u(7) -#define M33_NVIC_IPR1_PRI_N0_LSB _u(4) -#define M33_NVIC_IPR1_PRI_N0_ACCESS "RW" -// ============================================================================= -// Register : M33_NVIC_IPR2 -// Description : Sets or reads interrupt priorities -#define M33_NVIC_IPR2_OFFSET _u(0x0000e408) -#define M33_NVIC_IPR2_BITS _u(0xf0f0f0f0) -#define M33_NVIC_IPR2_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_NVIC_IPR2_PRI_N3 -// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+3, -// or RES0 if the PE does not implement this interrupt -#define M33_NVIC_IPR2_PRI_N3_RESET _u(0x0) -#define M33_NVIC_IPR2_PRI_N3_BITS _u(0xf0000000) -#define M33_NVIC_IPR2_PRI_N3_MSB _u(31) -#define M33_NVIC_IPR2_PRI_N3_LSB _u(28) -#define M33_NVIC_IPR2_PRI_N3_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_NVIC_IPR2_PRI_N2 -// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+2, -// or RES0 if the PE does not implement this interrupt -#define M33_NVIC_IPR2_PRI_N2_RESET _u(0x0) -#define M33_NVIC_IPR2_PRI_N2_BITS _u(0x00f00000) -#define M33_NVIC_IPR2_PRI_N2_MSB _u(23) -#define M33_NVIC_IPR2_PRI_N2_LSB _u(20) -#define M33_NVIC_IPR2_PRI_N2_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_NVIC_IPR2_PRI_N1 -// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+1, -// or RES0 if the PE does not implement this interrupt -#define M33_NVIC_IPR2_PRI_N1_RESET _u(0x0) -#define M33_NVIC_IPR2_PRI_N1_BITS _u(0x0000f000) -#define M33_NVIC_IPR2_PRI_N1_MSB _u(15) -#define M33_NVIC_IPR2_PRI_N1_LSB _u(12) -#define M33_NVIC_IPR2_PRI_N1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_NVIC_IPR2_PRI_N0 -// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+0, -// or RES0 if the PE does not implement this interrupt -#define M33_NVIC_IPR2_PRI_N0_RESET _u(0x0) -#define M33_NVIC_IPR2_PRI_N0_BITS _u(0x000000f0) -#define M33_NVIC_IPR2_PRI_N0_MSB _u(7) -#define M33_NVIC_IPR2_PRI_N0_LSB _u(4) -#define M33_NVIC_IPR2_PRI_N0_ACCESS "RW" -// ============================================================================= -// Register : M33_NVIC_IPR3 -// Description : Sets or reads interrupt priorities -#define M33_NVIC_IPR3_OFFSET _u(0x0000e40c) -#define M33_NVIC_IPR3_BITS _u(0xf0f0f0f0) -#define M33_NVIC_IPR3_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_NVIC_IPR3_PRI_N3 -// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+3, -// or RES0 if the PE does not implement this interrupt -#define M33_NVIC_IPR3_PRI_N3_RESET _u(0x0) -#define M33_NVIC_IPR3_PRI_N3_BITS _u(0xf0000000) -#define M33_NVIC_IPR3_PRI_N3_MSB _u(31) -#define M33_NVIC_IPR3_PRI_N3_LSB _u(28) -#define M33_NVIC_IPR3_PRI_N3_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_NVIC_IPR3_PRI_N2 -// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+2, -// or RES0 if the PE does not implement this interrupt -#define M33_NVIC_IPR3_PRI_N2_RESET _u(0x0) -#define M33_NVIC_IPR3_PRI_N2_BITS _u(0x00f00000) -#define M33_NVIC_IPR3_PRI_N2_MSB _u(23) -#define M33_NVIC_IPR3_PRI_N2_LSB _u(20) -#define M33_NVIC_IPR3_PRI_N2_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_NVIC_IPR3_PRI_N1 -// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+1, -// or RES0 if the PE does not implement this interrupt -#define M33_NVIC_IPR3_PRI_N1_RESET _u(0x0) -#define M33_NVIC_IPR3_PRI_N1_BITS _u(0x0000f000) -#define M33_NVIC_IPR3_PRI_N1_MSB _u(15) -#define M33_NVIC_IPR3_PRI_N1_LSB _u(12) -#define M33_NVIC_IPR3_PRI_N1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_NVIC_IPR3_PRI_N0 -// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+0, -// or RES0 if the PE does not implement this interrupt -#define M33_NVIC_IPR3_PRI_N0_RESET _u(0x0) -#define M33_NVIC_IPR3_PRI_N0_BITS _u(0x000000f0) -#define M33_NVIC_IPR3_PRI_N0_MSB _u(7) -#define M33_NVIC_IPR3_PRI_N0_LSB _u(4) -#define M33_NVIC_IPR3_PRI_N0_ACCESS "RW" -// ============================================================================= -// Register : M33_NVIC_IPR4 -// Description : Sets or reads interrupt priorities -#define M33_NVIC_IPR4_OFFSET _u(0x0000e410) -#define M33_NVIC_IPR4_BITS _u(0xf0f0f0f0) -#define M33_NVIC_IPR4_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_NVIC_IPR4_PRI_N3 -// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+3, -// or RES0 if the PE does not implement this interrupt -#define M33_NVIC_IPR4_PRI_N3_RESET _u(0x0) -#define M33_NVIC_IPR4_PRI_N3_BITS _u(0xf0000000) -#define M33_NVIC_IPR4_PRI_N3_MSB _u(31) -#define M33_NVIC_IPR4_PRI_N3_LSB _u(28) -#define M33_NVIC_IPR4_PRI_N3_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_NVIC_IPR4_PRI_N2 -// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+2, -// or RES0 if the PE does not implement this interrupt -#define M33_NVIC_IPR4_PRI_N2_RESET _u(0x0) -#define M33_NVIC_IPR4_PRI_N2_BITS _u(0x00f00000) -#define M33_NVIC_IPR4_PRI_N2_MSB _u(23) -#define M33_NVIC_IPR4_PRI_N2_LSB _u(20) -#define M33_NVIC_IPR4_PRI_N2_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_NVIC_IPR4_PRI_N1 -// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+1, -// or RES0 if the PE does not implement this interrupt -#define M33_NVIC_IPR4_PRI_N1_RESET _u(0x0) -#define M33_NVIC_IPR4_PRI_N1_BITS _u(0x0000f000) -#define M33_NVIC_IPR4_PRI_N1_MSB _u(15) -#define M33_NVIC_IPR4_PRI_N1_LSB _u(12) -#define M33_NVIC_IPR4_PRI_N1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_NVIC_IPR4_PRI_N0 -// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+0, -// or RES0 if the PE does not implement this interrupt -#define M33_NVIC_IPR4_PRI_N0_RESET _u(0x0) -#define M33_NVIC_IPR4_PRI_N0_BITS _u(0x000000f0) -#define M33_NVIC_IPR4_PRI_N0_MSB _u(7) -#define M33_NVIC_IPR4_PRI_N0_LSB _u(4) -#define M33_NVIC_IPR4_PRI_N0_ACCESS "RW" -// ============================================================================= -// Register : M33_NVIC_IPR5 -// Description : Sets or reads interrupt priorities -#define M33_NVIC_IPR5_OFFSET _u(0x0000e414) -#define M33_NVIC_IPR5_BITS _u(0xf0f0f0f0) -#define M33_NVIC_IPR5_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_NVIC_IPR5_PRI_N3 -// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+3, -// or RES0 if the PE does not implement this interrupt -#define M33_NVIC_IPR5_PRI_N3_RESET _u(0x0) -#define M33_NVIC_IPR5_PRI_N3_BITS _u(0xf0000000) -#define M33_NVIC_IPR5_PRI_N3_MSB _u(31) -#define M33_NVIC_IPR5_PRI_N3_LSB _u(28) -#define M33_NVIC_IPR5_PRI_N3_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_NVIC_IPR5_PRI_N2 -// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+2, -// or RES0 if the PE does not implement this interrupt -#define M33_NVIC_IPR5_PRI_N2_RESET _u(0x0) -#define M33_NVIC_IPR5_PRI_N2_BITS _u(0x00f00000) -#define M33_NVIC_IPR5_PRI_N2_MSB _u(23) -#define M33_NVIC_IPR5_PRI_N2_LSB _u(20) -#define M33_NVIC_IPR5_PRI_N2_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_NVIC_IPR5_PRI_N1 -// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+1, -// or RES0 if the PE does not implement this interrupt -#define M33_NVIC_IPR5_PRI_N1_RESET _u(0x0) -#define M33_NVIC_IPR5_PRI_N1_BITS _u(0x0000f000) -#define M33_NVIC_IPR5_PRI_N1_MSB _u(15) -#define M33_NVIC_IPR5_PRI_N1_LSB _u(12) -#define M33_NVIC_IPR5_PRI_N1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_NVIC_IPR5_PRI_N0 -// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+0, -// or RES0 if the PE does not implement this interrupt -#define M33_NVIC_IPR5_PRI_N0_RESET _u(0x0) -#define M33_NVIC_IPR5_PRI_N0_BITS _u(0x000000f0) -#define M33_NVIC_IPR5_PRI_N0_MSB _u(7) -#define M33_NVIC_IPR5_PRI_N0_LSB _u(4) -#define M33_NVIC_IPR5_PRI_N0_ACCESS "RW" -// ============================================================================= -// Register : M33_NVIC_IPR6 -// Description : Sets or reads interrupt priorities -#define M33_NVIC_IPR6_OFFSET _u(0x0000e418) -#define M33_NVIC_IPR6_BITS _u(0xf0f0f0f0) -#define M33_NVIC_IPR6_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_NVIC_IPR6_PRI_N3 -// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+3, -// or RES0 if the PE does not implement this interrupt -#define M33_NVIC_IPR6_PRI_N3_RESET _u(0x0) -#define M33_NVIC_IPR6_PRI_N3_BITS _u(0xf0000000) -#define M33_NVIC_IPR6_PRI_N3_MSB _u(31) -#define M33_NVIC_IPR6_PRI_N3_LSB _u(28) -#define M33_NVIC_IPR6_PRI_N3_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_NVIC_IPR6_PRI_N2 -// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+2, -// or RES0 if the PE does not implement this interrupt -#define M33_NVIC_IPR6_PRI_N2_RESET _u(0x0) -#define M33_NVIC_IPR6_PRI_N2_BITS _u(0x00f00000) -#define M33_NVIC_IPR6_PRI_N2_MSB _u(23) -#define M33_NVIC_IPR6_PRI_N2_LSB _u(20) -#define M33_NVIC_IPR6_PRI_N2_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_NVIC_IPR6_PRI_N1 -// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+1, -// or RES0 if the PE does not implement this interrupt -#define M33_NVIC_IPR6_PRI_N1_RESET _u(0x0) -#define M33_NVIC_IPR6_PRI_N1_BITS _u(0x0000f000) -#define M33_NVIC_IPR6_PRI_N1_MSB _u(15) -#define M33_NVIC_IPR6_PRI_N1_LSB _u(12) -#define M33_NVIC_IPR6_PRI_N1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_NVIC_IPR6_PRI_N0 -// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+0, -// or RES0 if the PE does not implement this interrupt -#define M33_NVIC_IPR6_PRI_N0_RESET _u(0x0) -#define M33_NVIC_IPR6_PRI_N0_BITS _u(0x000000f0) -#define M33_NVIC_IPR6_PRI_N0_MSB _u(7) -#define M33_NVIC_IPR6_PRI_N0_LSB _u(4) -#define M33_NVIC_IPR6_PRI_N0_ACCESS "RW" -// ============================================================================= -// Register : M33_NVIC_IPR7 -// Description : Sets or reads interrupt priorities -#define M33_NVIC_IPR7_OFFSET _u(0x0000e41c) -#define M33_NVIC_IPR7_BITS _u(0xf0f0f0f0) -#define M33_NVIC_IPR7_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_NVIC_IPR7_PRI_N3 -// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+3, -// or RES0 if the PE does not implement this interrupt -#define M33_NVIC_IPR7_PRI_N3_RESET _u(0x0) -#define M33_NVIC_IPR7_PRI_N3_BITS _u(0xf0000000) -#define M33_NVIC_IPR7_PRI_N3_MSB _u(31) -#define M33_NVIC_IPR7_PRI_N3_LSB _u(28) -#define M33_NVIC_IPR7_PRI_N3_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_NVIC_IPR7_PRI_N2 -// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+2, -// or RES0 if the PE does not implement this interrupt -#define M33_NVIC_IPR7_PRI_N2_RESET _u(0x0) -#define M33_NVIC_IPR7_PRI_N2_BITS _u(0x00f00000) -#define M33_NVIC_IPR7_PRI_N2_MSB _u(23) -#define M33_NVIC_IPR7_PRI_N2_LSB _u(20) -#define M33_NVIC_IPR7_PRI_N2_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_NVIC_IPR7_PRI_N1 -// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+1, -// or RES0 if the PE does not implement this interrupt -#define M33_NVIC_IPR7_PRI_N1_RESET _u(0x0) -#define M33_NVIC_IPR7_PRI_N1_BITS _u(0x0000f000) -#define M33_NVIC_IPR7_PRI_N1_MSB _u(15) -#define M33_NVIC_IPR7_PRI_N1_LSB _u(12) -#define M33_NVIC_IPR7_PRI_N1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_NVIC_IPR7_PRI_N0 -// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+0, -// or RES0 if the PE does not implement this interrupt -#define M33_NVIC_IPR7_PRI_N0_RESET _u(0x0) -#define M33_NVIC_IPR7_PRI_N0_BITS _u(0x000000f0) -#define M33_NVIC_IPR7_PRI_N0_MSB _u(7) -#define M33_NVIC_IPR7_PRI_N0_LSB _u(4) -#define M33_NVIC_IPR7_PRI_N0_ACCESS "RW" -// ============================================================================= -// Register : M33_NVIC_IPR8 -// Description : Sets or reads interrupt priorities -#define M33_NVIC_IPR8_OFFSET _u(0x0000e420) -#define M33_NVIC_IPR8_BITS _u(0xf0f0f0f0) -#define M33_NVIC_IPR8_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_NVIC_IPR8_PRI_N3 -// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+3, -// or RES0 if the PE does not implement this interrupt -#define M33_NVIC_IPR8_PRI_N3_RESET _u(0x0) -#define M33_NVIC_IPR8_PRI_N3_BITS _u(0xf0000000) -#define M33_NVIC_IPR8_PRI_N3_MSB _u(31) -#define M33_NVIC_IPR8_PRI_N3_LSB _u(28) -#define M33_NVIC_IPR8_PRI_N3_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_NVIC_IPR8_PRI_N2 -// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+2, -// or RES0 if the PE does not implement this interrupt -#define M33_NVIC_IPR8_PRI_N2_RESET _u(0x0) -#define M33_NVIC_IPR8_PRI_N2_BITS _u(0x00f00000) -#define M33_NVIC_IPR8_PRI_N2_MSB _u(23) -#define M33_NVIC_IPR8_PRI_N2_LSB _u(20) -#define M33_NVIC_IPR8_PRI_N2_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_NVIC_IPR8_PRI_N1 -// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+1, -// or RES0 if the PE does not implement this interrupt -#define M33_NVIC_IPR8_PRI_N1_RESET _u(0x0) -#define M33_NVIC_IPR8_PRI_N1_BITS _u(0x0000f000) -#define M33_NVIC_IPR8_PRI_N1_MSB _u(15) -#define M33_NVIC_IPR8_PRI_N1_LSB _u(12) -#define M33_NVIC_IPR8_PRI_N1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_NVIC_IPR8_PRI_N0 -// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+0, -// or RES0 if the PE does not implement this interrupt -#define M33_NVIC_IPR8_PRI_N0_RESET _u(0x0) -#define M33_NVIC_IPR8_PRI_N0_BITS _u(0x000000f0) -#define M33_NVIC_IPR8_PRI_N0_MSB _u(7) -#define M33_NVIC_IPR8_PRI_N0_LSB _u(4) -#define M33_NVIC_IPR8_PRI_N0_ACCESS "RW" -// ============================================================================= -// Register : M33_NVIC_IPR9 -// Description : Sets or reads interrupt priorities -#define M33_NVIC_IPR9_OFFSET _u(0x0000e424) -#define M33_NVIC_IPR9_BITS _u(0xf0f0f0f0) -#define M33_NVIC_IPR9_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_NVIC_IPR9_PRI_N3 -// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+3, -// or RES0 if the PE does not implement this interrupt -#define M33_NVIC_IPR9_PRI_N3_RESET _u(0x0) -#define M33_NVIC_IPR9_PRI_N3_BITS _u(0xf0000000) -#define M33_NVIC_IPR9_PRI_N3_MSB _u(31) -#define M33_NVIC_IPR9_PRI_N3_LSB _u(28) -#define M33_NVIC_IPR9_PRI_N3_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_NVIC_IPR9_PRI_N2 -// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+2, -// or RES0 if the PE does not implement this interrupt -#define M33_NVIC_IPR9_PRI_N2_RESET _u(0x0) -#define M33_NVIC_IPR9_PRI_N2_BITS _u(0x00f00000) -#define M33_NVIC_IPR9_PRI_N2_MSB _u(23) -#define M33_NVIC_IPR9_PRI_N2_LSB _u(20) -#define M33_NVIC_IPR9_PRI_N2_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_NVIC_IPR9_PRI_N1 -// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+1, -// or RES0 if the PE does not implement this interrupt -#define M33_NVIC_IPR9_PRI_N1_RESET _u(0x0) -#define M33_NVIC_IPR9_PRI_N1_BITS _u(0x0000f000) -#define M33_NVIC_IPR9_PRI_N1_MSB _u(15) -#define M33_NVIC_IPR9_PRI_N1_LSB _u(12) -#define M33_NVIC_IPR9_PRI_N1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_NVIC_IPR9_PRI_N0 -// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+0, -// or RES0 if the PE does not implement this interrupt -#define M33_NVIC_IPR9_PRI_N0_RESET _u(0x0) -#define M33_NVIC_IPR9_PRI_N0_BITS _u(0x000000f0) -#define M33_NVIC_IPR9_PRI_N0_MSB _u(7) -#define M33_NVIC_IPR9_PRI_N0_LSB _u(4) -#define M33_NVIC_IPR9_PRI_N0_ACCESS "RW" -// ============================================================================= -// Register : M33_NVIC_IPR10 -// Description : Sets or reads interrupt priorities -#define M33_NVIC_IPR10_OFFSET _u(0x0000e428) -#define M33_NVIC_IPR10_BITS _u(0xf0f0f0f0) -#define M33_NVIC_IPR10_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_NVIC_IPR10_PRI_N3 -// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+3, -// or RES0 if the PE does not implement this interrupt -#define M33_NVIC_IPR10_PRI_N3_RESET _u(0x0) -#define M33_NVIC_IPR10_PRI_N3_BITS _u(0xf0000000) -#define M33_NVIC_IPR10_PRI_N3_MSB _u(31) -#define M33_NVIC_IPR10_PRI_N3_LSB _u(28) -#define M33_NVIC_IPR10_PRI_N3_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_NVIC_IPR10_PRI_N2 -// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+2, -// or RES0 if the PE does not implement this interrupt -#define M33_NVIC_IPR10_PRI_N2_RESET _u(0x0) -#define M33_NVIC_IPR10_PRI_N2_BITS _u(0x00f00000) -#define M33_NVIC_IPR10_PRI_N2_MSB _u(23) -#define M33_NVIC_IPR10_PRI_N2_LSB _u(20) -#define M33_NVIC_IPR10_PRI_N2_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_NVIC_IPR10_PRI_N1 -// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+1, -// or RES0 if the PE does not implement this interrupt -#define M33_NVIC_IPR10_PRI_N1_RESET _u(0x0) -#define M33_NVIC_IPR10_PRI_N1_BITS _u(0x0000f000) -#define M33_NVIC_IPR10_PRI_N1_MSB _u(15) -#define M33_NVIC_IPR10_PRI_N1_LSB _u(12) -#define M33_NVIC_IPR10_PRI_N1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_NVIC_IPR10_PRI_N0 -// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+0, -// or RES0 if the PE does not implement this interrupt -#define M33_NVIC_IPR10_PRI_N0_RESET _u(0x0) -#define M33_NVIC_IPR10_PRI_N0_BITS _u(0x000000f0) -#define M33_NVIC_IPR10_PRI_N0_MSB _u(7) -#define M33_NVIC_IPR10_PRI_N0_LSB _u(4) -#define M33_NVIC_IPR10_PRI_N0_ACCESS "RW" -// ============================================================================= -// Register : M33_NVIC_IPR11 -// Description : Sets or reads interrupt priorities -#define M33_NVIC_IPR11_OFFSET _u(0x0000e42c) -#define M33_NVIC_IPR11_BITS _u(0xf0f0f0f0) -#define M33_NVIC_IPR11_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_NVIC_IPR11_PRI_N3 -// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+3, -// or RES0 if the PE does not implement this interrupt -#define M33_NVIC_IPR11_PRI_N3_RESET _u(0x0) -#define M33_NVIC_IPR11_PRI_N3_BITS _u(0xf0000000) -#define M33_NVIC_IPR11_PRI_N3_MSB _u(31) -#define M33_NVIC_IPR11_PRI_N3_LSB _u(28) -#define M33_NVIC_IPR11_PRI_N3_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_NVIC_IPR11_PRI_N2 -// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+2, -// or RES0 if the PE does not implement this interrupt -#define M33_NVIC_IPR11_PRI_N2_RESET _u(0x0) -#define M33_NVIC_IPR11_PRI_N2_BITS _u(0x00f00000) -#define M33_NVIC_IPR11_PRI_N2_MSB _u(23) -#define M33_NVIC_IPR11_PRI_N2_LSB _u(20) -#define M33_NVIC_IPR11_PRI_N2_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_NVIC_IPR11_PRI_N1 -// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+1, -// or RES0 if the PE does not implement this interrupt -#define M33_NVIC_IPR11_PRI_N1_RESET _u(0x0) -#define M33_NVIC_IPR11_PRI_N1_BITS _u(0x0000f000) -#define M33_NVIC_IPR11_PRI_N1_MSB _u(15) -#define M33_NVIC_IPR11_PRI_N1_LSB _u(12) -#define M33_NVIC_IPR11_PRI_N1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_NVIC_IPR11_PRI_N0 -// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+0, -// or RES0 if the PE does not implement this interrupt -#define M33_NVIC_IPR11_PRI_N0_RESET _u(0x0) -#define M33_NVIC_IPR11_PRI_N0_BITS _u(0x000000f0) -#define M33_NVIC_IPR11_PRI_N0_MSB _u(7) -#define M33_NVIC_IPR11_PRI_N0_LSB _u(4) -#define M33_NVIC_IPR11_PRI_N0_ACCESS "RW" -// ============================================================================= -// Register : M33_NVIC_IPR12 -// Description : Sets or reads interrupt priorities -#define M33_NVIC_IPR12_OFFSET _u(0x0000e430) -#define M33_NVIC_IPR12_BITS _u(0xf0f0f0f0) -#define M33_NVIC_IPR12_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_NVIC_IPR12_PRI_N3 -// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+3, -// or RES0 if the PE does not implement this interrupt -#define M33_NVIC_IPR12_PRI_N3_RESET _u(0x0) -#define M33_NVIC_IPR12_PRI_N3_BITS _u(0xf0000000) -#define M33_NVIC_IPR12_PRI_N3_MSB _u(31) -#define M33_NVIC_IPR12_PRI_N3_LSB _u(28) -#define M33_NVIC_IPR12_PRI_N3_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_NVIC_IPR12_PRI_N2 -// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+2, -// or RES0 if the PE does not implement this interrupt -#define M33_NVIC_IPR12_PRI_N2_RESET _u(0x0) -#define M33_NVIC_IPR12_PRI_N2_BITS _u(0x00f00000) -#define M33_NVIC_IPR12_PRI_N2_MSB _u(23) -#define M33_NVIC_IPR12_PRI_N2_LSB _u(20) -#define M33_NVIC_IPR12_PRI_N2_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_NVIC_IPR12_PRI_N1 -// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+1, -// or RES0 if the PE does not implement this interrupt -#define M33_NVIC_IPR12_PRI_N1_RESET _u(0x0) -#define M33_NVIC_IPR12_PRI_N1_BITS _u(0x0000f000) -#define M33_NVIC_IPR12_PRI_N1_MSB _u(15) -#define M33_NVIC_IPR12_PRI_N1_LSB _u(12) -#define M33_NVIC_IPR12_PRI_N1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_NVIC_IPR12_PRI_N0 -// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+0, -// or RES0 if the PE does not implement this interrupt -#define M33_NVIC_IPR12_PRI_N0_RESET _u(0x0) -#define M33_NVIC_IPR12_PRI_N0_BITS _u(0x000000f0) -#define M33_NVIC_IPR12_PRI_N0_MSB _u(7) -#define M33_NVIC_IPR12_PRI_N0_LSB _u(4) -#define M33_NVIC_IPR12_PRI_N0_ACCESS "RW" -// ============================================================================= -// Register : M33_NVIC_IPR13 -// Description : Sets or reads interrupt priorities -#define M33_NVIC_IPR13_OFFSET _u(0x0000e434) -#define M33_NVIC_IPR13_BITS _u(0xf0f0f0f0) -#define M33_NVIC_IPR13_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_NVIC_IPR13_PRI_N3 -// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+3, -// or RES0 if the PE does not implement this interrupt -#define M33_NVIC_IPR13_PRI_N3_RESET _u(0x0) -#define M33_NVIC_IPR13_PRI_N3_BITS _u(0xf0000000) -#define M33_NVIC_IPR13_PRI_N3_MSB _u(31) -#define M33_NVIC_IPR13_PRI_N3_LSB _u(28) -#define M33_NVIC_IPR13_PRI_N3_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_NVIC_IPR13_PRI_N2 -// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+2, -// or RES0 if the PE does not implement this interrupt -#define M33_NVIC_IPR13_PRI_N2_RESET _u(0x0) -#define M33_NVIC_IPR13_PRI_N2_BITS _u(0x00f00000) -#define M33_NVIC_IPR13_PRI_N2_MSB _u(23) -#define M33_NVIC_IPR13_PRI_N2_LSB _u(20) -#define M33_NVIC_IPR13_PRI_N2_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_NVIC_IPR13_PRI_N1 -// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+1, -// or RES0 if the PE does not implement this interrupt -#define M33_NVIC_IPR13_PRI_N1_RESET _u(0x0) -#define M33_NVIC_IPR13_PRI_N1_BITS _u(0x0000f000) -#define M33_NVIC_IPR13_PRI_N1_MSB _u(15) -#define M33_NVIC_IPR13_PRI_N1_LSB _u(12) -#define M33_NVIC_IPR13_PRI_N1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_NVIC_IPR13_PRI_N0 -// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+0, -// or RES0 if the PE does not implement this interrupt -#define M33_NVIC_IPR13_PRI_N0_RESET _u(0x0) -#define M33_NVIC_IPR13_PRI_N0_BITS _u(0x000000f0) -#define M33_NVIC_IPR13_PRI_N0_MSB _u(7) -#define M33_NVIC_IPR13_PRI_N0_LSB _u(4) -#define M33_NVIC_IPR13_PRI_N0_ACCESS "RW" -// ============================================================================= -// Register : M33_NVIC_IPR14 -// Description : Sets or reads interrupt priorities -#define M33_NVIC_IPR14_OFFSET _u(0x0000e438) -#define M33_NVIC_IPR14_BITS _u(0xf0f0f0f0) -#define M33_NVIC_IPR14_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_NVIC_IPR14_PRI_N3 -// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+3, -// or RES0 if the PE does not implement this interrupt -#define M33_NVIC_IPR14_PRI_N3_RESET _u(0x0) -#define M33_NVIC_IPR14_PRI_N3_BITS _u(0xf0000000) -#define M33_NVIC_IPR14_PRI_N3_MSB _u(31) -#define M33_NVIC_IPR14_PRI_N3_LSB _u(28) -#define M33_NVIC_IPR14_PRI_N3_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_NVIC_IPR14_PRI_N2 -// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+2, -// or RES0 if the PE does not implement this interrupt -#define M33_NVIC_IPR14_PRI_N2_RESET _u(0x0) -#define M33_NVIC_IPR14_PRI_N2_BITS _u(0x00f00000) -#define M33_NVIC_IPR14_PRI_N2_MSB _u(23) -#define M33_NVIC_IPR14_PRI_N2_LSB _u(20) -#define M33_NVIC_IPR14_PRI_N2_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_NVIC_IPR14_PRI_N1 -// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+1, -// or RES0 if the PE does not implement this interrupt -#define M33_NVIC_IPR14_PRI_N1_RESET _u(0x0) -#define M33_NVIC_IPR14_PRI_N1_BITS _u(0x0000f000) -#define M33_NVIC_IPR14_PRI_N1_MSB _u(15) -#define M33_NVIC_IPR14_PRI_N1_LSB _u(12) -#define M33_NVIC_IPR14_PRI_N1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_NVIC_IPR14_PRI_N0 -// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+0, -// or RES0 if the PE does not implement this interrupt -#define M33_NVIC_IPR14_PRI_N0_RESET _u(0x0) -#define M33_NVIC_IPR14_PRI_N0_BITS _u(0x000000f0) -#define M33_NVIC_IPR14_PRI_N0_MSB _u(7) -#define M33_NVIC_IPR14_PRI_N0_LSB _u(4) -#define M33_NVIC_IPR14_PRI_N0_ACCESS "RW" -// ============================================================================= -// Register : M33_NVIC_IPR15 -// Description : Sets or reads interrupt priorities -#define M33_NVIC_IPR15_OFFSET _u(0x0000e43c) -#define M33_NVIC_IPR15_BITS _u(0xf0f0f0f0) -#define M33_NVIC_IPR15_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_NVIC_IPR15_PRI_N3 -// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+3, -// or RES0 if the PE does not implement this interrupt -#define M33_NVIC_IPR15_PRI_N3_RESET _u(0x0) -#define M33_NVIC_IPR15_PRI_N3_BITS _u(0xf0000000) -#define M33_NVIC_IPR15_PRI_N3_MSB _u(31) -#define M33_NVIC_IPR15_PRI_N3_LSB _u(28) -#define M33_NVIC_IPR15_PRI_N3_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_NVIC_IPR15_PRI_N2 -// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+2, -// or RES0 if the PE does not implement this interrupt -#define M33_NVIC_IPR15_PRI_N2_RESET _u(0x0) -#define M33_NVIC_IPR15_PRI_N2_BITS _u(0x00f00000) -#define M33_NVIC_IPR15_PRI_N2_MSB _u(23) -#define M33_NVIC_IPR15_PRI_N2_LSB _u(20) -#define M33_NVIC_IPR15_PRI_N2_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_NVIC_IPR15_PRI_N1 -// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+1, -// or RES0 if the PE does not implement this interrupt -#define M33_NVIC_IPR15_PRI_N1_RESET _u(0x0) -#define M33_NVIC_IPR15_PRI_N1_BITS _u(0x0000f000) -#define M33_NVIC_IPR15_PRI_N1_MSB _u(15) -#define M33_NVIC_IPR15_PRI_N1_LSB _u(12) -#define M33_NVIC_IPR15_PRI_N1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_NVIC_IPR15_PRI_N0 -// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+0, -// or RES0 if the PE does not implement this interrupt -#define M33_NVIC_IPR15_PRI_N0_RESET _u(0x0) -#define M33_NVIC_IPR15_PRI_N0_BITS _u(0x000000f0) -#define M33_NVIC_IPR15_PRI_N0_MSB _u(7) -#define M33_NVIC_IPR15_PRI_N0_LSB _u(4) -#define M33_NVIC_IPR15_PRI_N0_ACCESS "RW" -// ============================================================================= -// Register : M33_CPUID -// Description : Provides identification information for the PE, including an -// implementer code for the device and a device ID number -#define M33_CPUID_OFFSET _u(0x0000ed00) -#define M33_CPUID_BITS _u(0xffffffff) -#define M33_CPUID_RESET _u(0x411fd210) -// ----------------------------------------------------------------------------- -// Field : M33_CPUID_IMPLEMENTER -// Description : This field must hold an implementer code that has been assigned -// by ARM -#define M33_CPUID_IMPLEMENTER_RESET _u(0x41) -#define M33_CPUID_IMPLEMENTER_BITS _u(0xff000000) -#define M33_CPUID_IMPLEMENTER_MSB _u(31) -#define M33_CPUID_IMPLEMENTER_LSB _u(24) -#define M33_CPUID_IMPLEMENTER_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_CPUID_VARIANT -// Description : IMPLEMENTATION DEFINED variant number. Typically, this field is -// used to distinguish between different product variants, or -// major revisions of a product -#define M33_CPUID_VARIANT_RESET _u(0x1) -#define M33_CPUID_VARIANT_BITS _u(0x00f00000) -#define M33_CPUID_VARIANT_MSB _u(23) -#define M33_CPUID_VARIANT_LSB _u(20) -#define M33_CPUID_VARIANT_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_CPUID_ARCHITECTURE -// Description : Defines the Architecture implemented by the PE -#define M33_CPUID_ARCHITECTURE_RESET _u(0xf) -#define M33_CPUID_ARCHITECTURE_BITS _u(0x000f0000) -#define M33_CPUID_ARCHITECTURE_MSB _u(19) -#define M33_CPUID_ARCHITECTURE_LSB _u(16) -#define M33_CPUID_ARCHITECTURE_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_CPUID_PARTNO -// Description : IMPLEMENTATION DEFINED primary part number for the device -#define M33_CPUID_PARTNO_RESET _u(0xd21) -#define M33_CPUID_PARTNO_BITS _u(0x0000fff0) -#define M33_CPUID_PARTNO_MSB _u(15) -#define M33_CPUID_PARTNO_LSB _u(4) -#define M33_CPUID_PARTNO_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_CPUID_REVISION -// Description : IMPLEMENTATION DEFINED revision number for the device -#define M33_CPUID_REVISION_RESET _u(0x0) -#define M33_CPUID_REVISION_BITS _u(0x0000000f) -#define M33_CPUID_REVISION_MSB _u(3) -#define M33_CPUID_REVISION_LSB _u(0) -#define M33_CPUID_REVISION_ACCESS "RO" -// ============================================================================= -// Register : M33_ICSR -// Description : Controls and provides status information for NMI, PendSV, -// SysTick and interrupts -#define M33_ICSR_OFFSET _u(0x0000ed04) -#define M33_ICSR_BITS _u(0xdfdff9ff) -#define M33_ICSR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_ICSR_PENDNMISET -// Description : Indicates whether the NMI exception is pending -#define M33_ICSR_PENDNMISET_RESET _u(0x0) -#define M33_ICSR_PENDNMISET_BITS _u(0x80000000) -#define M33_ICSR_PENDNMISET_MSB _u(31) -#define M33_ICSR_PENDNMISET_LSB _u(31) -#define M33_ICSR_PENDNMISET_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_ICSR_PENDNMICLR -// Description : Allows the NMI exception pend state to be cleared -#define M33_ICSR_PENDNMICLR_RESET _u(0x0) -#define M33_ICSR_PENDNMICLR_BITS _u(0x40000000) -#define M33_ICSR_PENDNMICLR_MSB _u(30) -#define M33_ICSR_PENDNMICLR_LSB _u(30) -#define M33_ICSR_PENDNMICLR_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_ICSR_PENDSVSET -// Description : Indicates whether the PendSV `FTSSS exception is pending -#define M33_ICSR_PENDSVSET_RESET _u(0x0) -#define M33_ICSR_PENDSVSET_BITS _u(0x10000000) -#define M33_ICSR_PENDSVSET_MSB _u(28) -#define M33_ICSR_PENDSVSET_LSB _u(28) -#define M33_ICSR_PENDSVSET_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_ICSR_PENDSVCLR -// Description : Allows the PendSV exception pend state to be cleared `FTSSS -#define M33_ICSR_PENDSVCLR_RESET _u(0x0) -#define M33_ICSR_PENDSVCLR_BITS _u(0x08000000) -#define M33_ICSR_PENDSVCLR_MSB _u(27) -#define M33_ICSR_PENDSVCLR_LSB _u(27) -#define M33_ICSR_PENDSVCLR_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_ICSR_PENDSTSET -// Description : Indicates whether the SysTick `FTSSS exception is pending -#define M33_ICSR_PENDSTSET_RESET _u(0x0) -#define M33_ICSR_PENDSTSET_BITS _u(0x04000000) -#define M33_ICSR_PENDSTSET_MSB _u(26) -#define M33_ICSR_PENDSTSET_LSB _u(26) -#define M33_ICSR_PENDSTSET_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_ICSR_PENDSTCLR -// Description : Allows the SysTick exception pend state to be cleared `FTSSS -#define M33_ICSR_PENDSTCLR_RESET _u(0x0) -#define M33_ICSR_PENDSTCLR_BITS _u(0x02000000) -#define M33_ICSR_PENDSTCLR_MSB _u(25) -#define M33_ICSR_PENDSTCLR_LSB _u(25) -#define M33_ICSR_PENDSTCLR_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_ICSR_STTNS -// Description : Controls whether in a single SysTick implementation, the -// SysTick is Secure or Non-secure -#define M33_ICSR_STTNS_RESET _u(0x0) -#define M33_ICSR_STTNS_BITS _u(0x01000000) -#define M33_ICSR_STTNS_MSB _u(24) -#define M33_ICSR_STTNS_LSB _u(24) -#define M33_ICSR_STTNS_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_ICSR_ISRPREEMPT -// Description : Indicates whether a pending exception will be serviced on exit -// from debug halt state -#define M33_ICSR_ISRPREEMPT_RESET _u(0x0) -#define M33_ICSR_ISRPREEMPT_BITS _u(0x00800000) -#define M33_ICSR_ISRPREEMPT_MSB _u(23) -#define M33_ICSR_ISRPREEMPT_LSB _u(23) -#define M33_ICSR_ISRPREEMPT_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_ICSR_ISRPENDING -// Description : Indicates whether an external interrupt, generated by the NVIC, -// is pending -#define M33_ICSR_ISRPENDING_RESET _u(0x0) -#define M33_ICSR_ISRPENDING_BITS _u(0x00400000) -#define M33_ICSR_ISRPENDING_MSB _u(22) -#define M33_ICSR_ISRPENDING_LSB _u(22) -#define M33_ICSR_ISRPENDING_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_ICSR_VECTPENDING -// Description : The exception number of the highest priority pending and -// enabled interrupt -#define M33_ICSR_VECTPENDING_RESET _u(0x000) -#define M33_ICSR_VECTPENDING_BITS _u(0x001ff000) -#define M33_ICSR_VECTPENDING_MSB _u(20) -#define M33_ICSR_VECTPENDING_LSB _u(12) -#define M33_ICSR_VECTPENDING_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_ICSR_RETTOBASE -// Description : In Handler mode, indicates whether there is more than one -// active exception -#define M33_ICSR_RETTOBASE_RESET _u(0x0) -#define M33_ICSR_RETTOBASE_BITS _u(0x00000800) -#define M33_ICSR_RETTOBASE_MSB _u(11) -#define M33_ICSR_RETTOBASE_LSB _u(11) -#define M33_ICSR_RETTOBASE_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_ICSR_VECTACTIVE -// Description : The exception number of the current executing exception -#define M33_ICSR_VECTACTIVE_RESET _u(0x000) -#define M33_ICSR_VECTACTIVE_BITS _u(0x000001ff) -#define M33_ICSR_VECTACTIVE_MSB _u(8) -#define M33_ICSR_VECTACTIVE_LSB _u(0) -#define M33_ICSR_VECTACTIVE_ACCESS "RO" -// ============================================================================= -// Register : M33_VTOR -// Description : The VTOR indicates the offset of the vector table base address -// from memory address 0x00000000. -#define M33_VTOR_OFFSET _u(0x0000ed08) -#define M33_VTOR_BITS _u(0xffffff80) -#define M33_VTOR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_VTOR_TBLOFF -// Description : Vector table base offset field. It contains bits[31:7] of the -// offset of the table base from the bottom of the memory map. -#define M33_VTOR_TBLOFF_RESET _u(0x0000000) -#define M33_VTOR_TBLOFF_BITS _u(0xffffff80) -#define M33_VTOR_TBLOFF_MSB _u(31) -#define M33_VTOR_TBLOFF_LSB _u(7) -#define M33_VTOR_TBLOFF_ACCESS "RW" -// ============================================================================= -// Register : M33_AIRCR -// Description : Use the Application Interrupt and Reset Control Register to: -// determine data endianness, clear all active state information -// from debug halt mode, request a system reset. -#define M33_AIRCR_OFFSET _u(0x0000ed0c) -#define M33_AIRCR_BITS _u(0xffffe70e) -#define M33_AIRCR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_AIRCR_VECTKEY -// Description : Register key: -// Reads as Unknown -// On writes, write 0x05FA to VECTKEY, otherwise the write is -// ignored. -#define M33_AIRCR_VECTKEY_RESET _u(0x0000) -#define M33_AIRCR_VECTKEY_BITS _u(0xffff0000) -#define M33_AIRCR_VECTKEY_MSB _u(31) -#define M33_AIRCR_VECTKEY_LSB _u(16) -#define M33_AIRCR_VECTKEY_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_AIRCR_ENDIANESS -// Description : Data endianness implemented: -// 0 = Little-endian. -#define M33_AIRCR_ENDIANESS_RESET _u(0x0) -#define M33_AIRCR_ENDIANESS_BITS _u(0x00008000) -#define M33_AIRCR_ENDIANESS_MSB _u(15) -#define M33_AIRCR_ENDIANESS_LSB _u(15) -#define M33_AIRCR_ENDIANESS_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_AIRCR_PRIS -// Description : Prioritize Secure exceptions. The value of this bit defines -// whether Secure exception priority boosting is enabled. -// 0 Priority ranges of Secure and Non-secure exceptions are -// identical. -// 1 Non-secure exceptions are de-prioritized. -#define M33_AIRCR_PRIS_RESET _u(0x0) -#define M33_AIRCR_PRIS_BITS _u(0x00004000) -#define M33_AIRCR_PRIS_MSB _u(14) -#define M33_AIRCR_PRIS_LSB _u(14) -#define M33_AIRCR_PRIS_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_AIRCR_BFHFNMINS -// Description : BusFault, HardFault, and NMI Non-secure enable. -// 0 BusFault, HardFault, and NMI are Secure. -// 1 BusFault and NMI are Non-secure and exceptions can target -// Non-secure HardFault. -#define M33_AIRCR_BFHFNMINS_RESET _u(0x0) -#define M33_AIRCR_BFHFNMINS_BITS _u(0x00002000) -#define M33_AIRCR_BFHFNMINS_MSB _u(13) -#define M33_AIRCR_BFHFNMINS_LSB _u(13) -#define M33_AIRCR_BFHFNMINS_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_AIRCR_PRIGROUP -// Description : Interrupt priority grouping field. This field determines the -// split of group priority from subpriority. -// See https://developer.arm.com/documentation/100235/0004/the- -// cortex-m33-peripherals/system-control-block/application- -// interrupt-and-reset-control-register?lang=en -#define M33_AIRCR_PRIGROUP_RESET _u(0x0) -#define M33_AIRCR_PRIGROUP_BITS _u(0x00000700) -#define M33_AIRCR_PRIGROUP_MSB _u(10) -#define M33_AIRCR_PRIGROUP_LSB _u(8) -#define M33_AIRCR_PRIGROUP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_AIRCR_SYSRESETREQS -// Description : System reset request, Secure state only. -// 0 SYSRESETREQ functionality is available to both Security -// states. -// 1 SYSRESETREQ functionality is only available to Secure state. -#define M33_AIRCR_SYSRESETREQS_RESET _u(0x0) -#define M33_AIRCR_SYSRESETREQS_BITS _u(0x00000008) -#define M33_AIRCR_SYSRESETREQS_MSB _u(3) -#define M33_AIRCR_SYSRESETREQS_LSB _u(3) -#define M33_AIRCR_SYSRESETREQS_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_AIRCR_SYSRESETREQ -// Description : Writing 1 to this bit causes the SYSRESETREQ signal to the -// outer system to be asserted to request a reset. The intention -// is to force a large system reset of all major components except -// for debug. The C_HALT bit in the DHCSR is cleared as a result -// of the system reset requested. The debugger does not lose -// contact with the device. -#define M33_AIRCR_SYSRESETREQ_RESET _u(0x0) -#define M33_AIRCR_SYSRESETREQ_BITS _u(0x00000004) -#define M33_AIRCR_SYSRESETREQ_MSB _u(2) -#define M33_AIRCR_SYSRESETREQ_LSB _u(2) -#define M33_AIRCR_SYSRESETREQ_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_AIRCR_VECTCLRACTIVE -// Description : Clears all active state information for fixed and configurable -// exceptions. This bit: is self-clearing, can only be set by the -// DAP when the core is halted. When set: clears all active -// exception status of the processor, forces a return to Thread -// mode, forces an IPSR of 0. A debugger must re-initialize the -// stack. -#define M33_AIRCR_VECTCLRACTIVE_RESET _u(0x0) -#define M33_AIRCR_VECTCLRACTIVE_BITS _u(0x00000002) -#define M33_AIRCR_VECTCLRACTIVE_MSB _u(1) -#define M33_AIRCR_VECTCLRACTIVE_LSB _u(1) -#define M33_AIRCR_VECTCLRACTIVE_ACCESS "RW" -// ============================================================================= -// Register : M33_SCR -// Description : System Control Register. Use the System Control Register for -// power-management functions: signal to the system when the -// processor can enter a low power state, control how the -// processor enters and exits low power states. -#define M33_SCR_OFFSET _u(0x0000ed10) -#define M33_SCR_BITS _u(0x0000001e) -#define M33_SCR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_SCR_SEVONPEND -// Description : Send Event on Pending bit: -// 0 = Only enabled interrupts or events can wakeup the processor, -// disabled interrupts are excluded. -// 1 = Enabled events and all interrupts, including disabled -// interrupts, can wakeup the processor. -// When an event or interrupt becomes pending, the event signal -// wakes up the processor from WFE. If the -// processor is not waiting for an event, the event is registered -// and affects the next WFE. -// The processor also wakes up on execution of an SEV instruction -// or an external event. -#define M33_SCR_SEVONPEND_RESET _u(0x0) -#define M33_SCR_SEVONPEND_BITS _u(0x00000010) -#define M33_SCR_SEVONPEND_MSB _u(4) -#define M33_SCR_SEVONPEND_LSB _u(4) -#define M33_SCR_SEVONPEND_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_SCR_SLEEPDEEPS -// Description : 0 SLEEPDEEP is available to both security states -// 1 SLEEPDEEP is only available to Secure state -#define M33_SCR_SLEEPDEEPS_RESET _u(0x0) -#define M33_SCR_SLEEPDEEPS_BITS _u(0x00000008) -#define M33_SCR_SLEEPDEEPS_MSB _u(3) -#define M33_SCR_SLEEPDEEPS_LSB _u(3) -#define M33_SCR_SLEEPDEEPS_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_SCR_SLEEPDEEP -// Description : Controls whether the processor uses sleep or deep sleep as its -// low power mode: -// 0 = Sleep. -// 1 = Deep sleep. -#define M33_SCR_SLEEPDEEP_RESET _u(0x0) -#define M33_SCR_SLEEPDEEP_BITS _u(0x00000004) -#define M33_SCR_SLEEPDEEP_MSB _u(2) -#define M33_SCR_SLEEPDEEP_LSB _u(2) -#define M33_SCR_SLEEPDEEP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_SCR_SLEEPONEXIT -// Description : Indicates sleep-on-exit when returning from Handler mode to -// Thread mode: -// 0 = Do not sleep when returning to Thread mode. -// 1 = Enter sleep, or deep sleep, on return from an ISR to Thread -// mode. -// Setting this bit to 1 enables an interrupt driven application -// to avoid returning to an empty main application. -#define M33_SCR_SLEEPONEXIT_RESET _u(0x0) -#define M33_SCR_SLEEPONEXIT_BITS _u(0x00000002) -#define M33_SCR_SLEEPONEXIT_MSB _u(1) -#define M33_SCR_SLEEPONEXIT_LSB _u(1) -#define M33_SCR_SLEEPONEXIT_ACCESS "RW" -// ============================================================================= -// Register : M33_CCR -// Description : Sets or returns configuration and control data -#define M33_CCR_OFFSET _u(0x0000ed14) -#define M33_CCR_BITS _u(0x0007071b) -#define M33_CCR_RESET _u(0x00000201) -// ----------------------------------------------------------------------------- -// Field : M33_CCR_BP -// Description : Enables program flow prediction `FTSSS -#define M33_CCR_BP_RESET _u(0x0) -#define M33_CCR_BP_BITS _u(0x00040000) -#define M33_CCR_BP_MSB _u(18) -#define M33_CCR_BP_LSB _u(18) -#define M33_CCR_BP_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_CCR_IC -// Description : This is a global enable bit for instruction caches in the -// selected Security state -#define M33_CCR_IC_RESET _u(0x0) -#define M33_CCR_IC_BITS _u(0x00020000) -#define M33_CCR_IC_MSB _u(17) -#define M33_CCR_IC_LSB _u(17) -#define M33_CCR_IC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_CCR_DC -// Description : Enables data caching of all data accesses to Normal memory -// `FTSSS -#define M33_CCR_DC_RESET _u(0x0) -#define M33_CCR_DC_BITS _u(0x00010000) -#define M33_CCR_DC_MSB _u(16) -#define M33_CCR_DC_LSB _u(16) -#define M33_CCR_DC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_CCR_STKOFHFNMIGN -// Description : Controls the effect of a stack limit violation while executing -// at a requested priority less than 0 -#define M33_CCR_STKOFHFNMIGN_RESET _u(0x0) -#define M33_CCR_STKOFHFNMIGN_BITS _u(0x00000400) -#define M33_CCR_STKOFHFNMIGN_MSB _u(10) -#define M33_CCR_STKOFHFNMIGN_LSB _u(10) -#define M33_CCR_STKOFHFNMIGN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_CCR_RES1 -// Description : Reserved, RES1 -#define M33_CCR_RES1_RESET _u(0x1) -#define M33_CCR_RES1_BITS _u(0x00000200) -#define M33_CCR_RES1_MSB _u(9) -#define M33_CCR_RES1_LSB _u(9) -#define M33_CCR_RES1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_CCR_BFHFNMIGN -// Description : Determines the effect of precise BusFaults on handlers running -// at a requested priority less than 0 -#define M33_CCR_BFHFNMIGN_RESET _u(0x0) -#define M33_CCR_BFHFNMIGN_BITS _u(0x00000100) -#define M33_CCR_BFHFNMIGN_MSB _u(8) -#define M33_CCR_BFHFNMIGN_LSB _u(8) -#define M33_CCR_BFHFNMIGN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_CCR_DIV_0_TRP -// Description : Controls the generation of a DIVBYZERO UsageFault when -// attempting to perform integer division by zero -#define M33_CCR_DIV_0_TRP_RESET _u(0x0) -#define M33_CCR_DIV_0_TRP_BITS _u(0x00000010) -#define M33_CCR_DIV_0_TRP_MSB _u(4) -#define M33_CCR_DIV_0_TRP_LSB _u(4) -#define M33_CCR_DIV_0_TRP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_CCR_UNALIGN_TRP -// Description : Controls the trapping of unaligned word or halfword accesses -#define M33_CCR_UNALIGN_TRP_RESET _u(0x0) -#define M33_CCR_UNALIGN_TRP_BITS _u(0x00000008) -#define M33_CCR_UNALIGN_TRP_MSB _u(3) -#define M33_CCR_UNALIGN_TRP_LSB _u(3) -#define M33_CCR_UNALIGN_TRP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_CCR_USERSETMPEND -// Description : Determines whether unprivileged accesses are permitted to pend -// interrupts via the STIR -#define M33_CCR_USERSETMPEND_RESET _u(0x0) -#define M33_CCR_USERSETMPEND_BITS _u(0x00000002) -#define M33_CCR_USERSETMPEND_MSB _u(1) -#define M33_CCR_USERSETMPEND_LSB _u(1) -#define M33_CCR_USERSETMPEND_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_CCR_RES1_1 -// Description : Reserved, RES1 -#define M33_CCR_RES1_1_RESET _u(0x1) -#define M33_CCR_RES1_1_BITS _u(0x00000001) -#define M33_CCR_RES1_1_MSB _u(0) -#define M33_CCR_RES1_1_LSB _u(0) -#define M33_CCR_RES1_1_ACCESS "RO" -// ============================================================================= -// Register : M33_SHPR1 -// Description : Sets or returns priority for system handlers 4 - 7 -#define M33_SHPR1_OFFSET _u(0x0000ed18) -#define M33_SHPR1_BITS _u(0xe0e0e0e0) -#define M33_SHPR1_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_SHPR1_PRI_7_3 -// Description : Priority of system handler 7, SecureFault -#define M33_SHPR1_PRI_7_3_RESET _u(0x0) -#define M33_SHPR1_PRI_7_3_BITS _u(0xe0000000) -#define M33_SHPR1_PRI_7_3_MSB _u(31) -#define M33_SHPR1_PRI_7_3_LSB _u(29) -#define M33_SHPR1_PRI_7_3_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_SHPR1_PRI_6_3 -// Description : Priority of system handler 6, SecureFault -#define M33_SHPR1_PRI_6_3_RESET _u(0x0) -#define M33_SHPR1_PRI_6_3_BITS _u(0x00e00000) -#define M33_SHPR1_PRI_6_3_MSB _u(23) -#define M33_SHPR1_PRI_6_3_LSB _u(21) -#define M33_SHPR1_PRI_6_3_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_SHPR1_PRI_5_3 -// Description : Priority of system handler 5, SecureFault -#define M33_SHPR1_PRI_5_3_RESET _u(0x0) -#define M33_SHPR1_PRI_5_3_BITS _u(0x0000e000) -#define M33_SHPR1_PRI_5_3_MSB _u(15) -#define M33_SHPR1_PRI_5_3_LSB _u(13) -#define M33_SHPR1_PRI_5_3_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_SHPR1_PRI_4_3 -// Description : Priority of system handler 4, SecureFault -#define M33_SHPR1_PRI_4_3_RESET _u(0x0) -#define M33_SHPR1_PRI_4_3_BITS _u(0x000000e0) -#define M33_SHPR1_PRI_4_3_MSB _u(7) -#define M33_SHPR1_PRI_4_3_LSB _u(5) -#define M33_SHPR1_PRI_4_3_ACCESS "RW" -// ============================================================================= -// Register : M33_SHPR2 -// Description : Sets or returns priority for system handlers 8 - 11 -#define M33_SHPR2_OFFSET _u(0x0000ed1c) -#define M33_SHPR2_BITS _u(0xe0ffffff) -#define M33_SHPR2_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_SHPR2_PRI_11_3 -// Description : Priority of system handler 11, SecureFault -#define M33_SHPR2_PRI_11_3_RESET _u(0x0) -#define M33_SHPR2_PRI_11_3_BITS _u(0xe0000000) -#define M33_SHPR2_PRI_11_3_MSB _u(31) -#define M33_SHPR2_PRI_11_3_LSB _u(29) -#define M33_SHPR2_PRI_11_3_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_SHPR2_PRI_10 -// Description : Reserved, RES0 -#define M33_SHPR2_PRI_10_RESET _u(0x00) -#define M33_SHPR2_PRI_10_BITS _u(0x00ff0000) -#define M33_SHPR2_PRI_10_MSB _u(23) -#define M33_SHPR2_PRI_10_LSB _u(16) -#define M33_SHPR2_PRI_10_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_SHPR2_PRI_9 -// Description : Reserved, RES0 -#define M33_SHPR2_PRI_9_RESET _u(0x00) -#define M33_SHPR2_PRI_9_BITS _u(0x0000ff00) -#define M33_SHPR2_PRI_9_MSB _u(15) -#define M33_SHPR2_PRI_9_LSB _u(8) -#define M33_SHPR2_PRI_9_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_SHPR2_PRI_8 -// Description : Reserved, RES0 -#define M33_SHPR2_PRI_8_RESET _u(0x00) -#define M33_SHPR2_PRI_8_BITS _u(0x000000ff) -#define M33_SHPR2_PRI_8_MSB _u(7) -#define M33_SHPR2_PRI_8_LSB _u(0) -#define M33_SHPR2_PRI_8_ACCESS "RO" -// ============================================================================= -// Register : M33_SHPR3 -// Description : Sets or returns priority for system handlers 12 - 15 -#define M33_SHPR3_OFFSET _u(0x0000ed20) -#define M33_SHPR3_BITS _u(0xe0e0ffe0) -#define M33_SHPR3_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_SHPR3_PRI_15_3 -// Description : Priority of system handler 15, SecureFault -#define M33_SHPR3_PRI_15_3_RESET _u(0x0) -#define M33_SHPR3_PRI_15_3_BITS _u(0xe0000000) -#define M33_SHPR3_PRI_15_3_MSB _u(31) -#define M33_SHPR3_PRI_15_3_LSB _u(29) -#define M33_SHPR3_PRI_15_3_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_SHPR3_PRI_14_3 -// Description : Priority of system handler 14, SecureFault -#define M33_SHPR3_PRI_14_3_RESET _u(0x0) -#define M33_SHPR3_PRI_14_3_BITS _u(0x00e00000) -#define M33_SHPR3_PRI_14_3_MSB _u(23) -#define M33_SHPR3_PRI_14_3_LSB _u(21) -#define M33_SHPR3_PRI_14_3_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_SHPR3_PRI_13 -// Description : Reserved, RES0 -#define M33_SHPR3_PRI_13_RESET _u(0x00) -#define M33_SHPR3_PRI_13_BITS _u(0x0000ff00) -#define M33_SHPR3_PRI_13_MSB _u(15) -#define M33_SHPR3_PRI_13_LSB _u(8) -#define M33_SHPR3_PRI_13_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_SHPR3_PRI_12_3 -// Description : Priority of system handler 12, SecureFault -#define M33_SHPR3_PRI_12_3_RESET _u(0x0) -#define M33_SHPR3_PRI_12_3_BITS _u(0x000000e0) -#define M33_SHPR3_PRI_12_3_MSB _u(7) -#define M33_SHPR3_PRI_12_3_LSB _u(5) -#define M33_SHPR3_PRI_12_3_ACCESS "RW" -// ============================================================================= -// Register : M33_SHCSR -// Description : Provides access to the active and pending status of system -// exceptions -#define M33_SHCSR_OFFSET _u(0x0000ed24) -#define M33_SHCSR_BITS _u(0x003ffdbf) -#define M33_SHCSR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_SHCSR_HARDFAULTPENDED -// Description : `IAAMO the pending state of the HardFault exception `CTTSSS -#define M33_SHCSR_HARDFAULTPENDED_RESET _u(0x0) -#define M33_SHCSR_HARDFAULTPENDED_BITS _u(0x00200000) -#define M33_SHCSR_HARDFAULTPENDED_MSB _u(21) -#define M33_SHCSR_HARDFAULTPENDED_LSB _u(21) -#define M33_SHCSR_HARDFAULTPENDED_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_SHCSR_SECUREFAULTPENDED -// Description : `IAAMO the pending state of the SecureFault exception -#define M33_SHCSR_SECUREFAULTPENDED_RESET _u(0x0) -#define M33_SHCSR_SECUREFAULTPENDED_BITS _u(0x00100000) -#define M33_SHCSR_SECUREFAULTPENDED_MSB _u(20) -#define M33_SHCSR_SECUREFAULTPENDED_LSB _u(20) -#define M33_SHCSR_SECUREFAULTPENDED_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_SHCSR_SECUREFAULTENA -// Description : `DW the SecureFault exception is enabled -#define M33_SHCSR_SECUREFAULTENA_RESET _u(0x0) -#define M33_SHCSR_SECUREFAULTENA_BITS _u(0x00080000) -#define M33_SHCSR_SECUREFAULTENA_MSB _u(19) -#define M33_SHCSR_SECUREFAULTENA_LSB _u(19) -#define M33_SHCSR_SECUREFAULTENA_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_SHCSR_USGFAULTENA -// Description : `DW the UsageFault exception is enabled `FTSSS -#define M33_SHCSR_USGFAULTENA_RESET _u(0x0) -#define M33_SHCSR_USGFAULTENA_BITS _u(0x00040000) -#define M33_SHCSR_USGFAULTENA_MSB _u(18) -#define M33_SHCSR_USGFAULTENA_LSB _u(18) -#define M33_SHCSR_USGFAULTENA_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_SHCSR_BUSFAULTENA -// Description : `DW the BusFault exception is enabled -#define M33_SHCSR_BUSFAULTENA_RESET _u(0x0) -#define M33_SHCSR_BUSFAULTENA_BITS _u(0x00020000) -#define M33_SHCSR_BUSFAULTENA_MSB _u(17) -#define M33_SHCSR_BUSFAULTENA_LSB _u(17) -#define M33_SHCSR_BUSFAULTENA_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_SHCSR_MEMFAULTENA -// Description : `DW the MemManage exception is enabled `FTSSS -#define M33_SHCSR_MEMFAULTENA_RESET _u(0x0) -#define M33_SHCSR_MEMFAULTENA_BITS _u(0x00010000) -#define M33_SHCSR_MEMFAULTENA_MSB _u(16) -#define M33_SHCSR_MEMFAULTENA_LSB _u(16) -#define M33_SHCSR_MEMFAULTENA_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_SHCSR_SVCALLPENDED -// Description : `IAAMO the pending state of the SVCall exception `FTSSS -#define M33_SHCSR_SVCALLPENDED_RESET _u(0x0) -#define M33_SHCSR_SVCALLPENDED_BITS _u(0x00008000) -#define M33_SHCSR_SVCALLPENDED_MSB _u(15) -#define M33_SHCSR_SVCALLPENDED_LSB _u(15) -#define M33_SHCSR_SVCALLPENDED_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_SHCSR_BUSFAULTPENDED -// Description : `IAAMO the pending state of the BusFault exception -#define M33_SHCSR_BUSFAULTPENDED_RESET _u(0x0) -#define M33_SHCSR_BUSFAULTPENDED_BITS _u(0x00004000) -#define M33_SHCSR_BUSFAULTPENDED_MSB _u(14) -#define M33_SHCSR_BUSFAULTPENDED_LSB _u(14) -#define M33_SHCSR_BUSFAULTPENDED_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_SHCSR_MEMFAULTPENDED -// Description : `IAAMO the pending state of the MemManage exception `FTSSS -#define M33_SHCSR_MEMFAULTPENDED_RESET _u(0x0) -#define M33_SHCSR_MEMFAULTPENDED_BITS _u(0x00002000) -#define M33_SHCSR_MEMFAULTPENDED_MSB _u(13) -#define M33_SHCSR_MEMFAULTPENDED_LSB _u(13) -#define M33_SHCSR_MEMFAULTPENDED_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_SHCSR_USGFAULTPENDED -// Description : The UsageFault exception is banked between Security states, -// `IAAMO the pending state of the UsageFault exception `FTSSS -#define M33_SHCSR_USGFAULTPENDED_RESET _u(0x0) -#define M33_SHCSR_USGFAULTPENDED_BITS _u(0x00001000) -#define M33_SHCSR_USGFAULTPENDED_MSB _u(12) -#define M33_SHCSR_USGFAULTPENDED_LSB _u(12) -#define M33_SHCSR_USGFAULTPENDED_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_SHCSR_SYSTICKACT -// Description : `IAAMO the active state of the SysTick exception `FTSSS -#define M33_SHCSR_SYSTICKACT_RESET _u(0x0) -#define M33_SHCSR_SYSTICKACT_BITS _u(0x00000800) -#define M33_SHCSR_SYSTICKACT_MSB _u(11) -#define M33_SHCSR_SYSTICKACT_LSB _u(11) -#define M33_SHCSR_SYSTICKACT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_SHCSR_PENDSVACT -// Description : `IAAMO the active state of the PendSV exception `FTSSS -#define M33_SHCSR_PENDSVACT_RESET _u(0x0) -#define M33_SHCSR_PENDSVACT_BITS _u(0x00000400) -#define M33_SHCSR_PENDSVACT_MSB _u(10) -#define M33_SHCSR_PENDSVACT_LSB _u(10) -#define M33_SHCSR_PENDSVACT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_SHCSR_MONITORACT -// Description : `IAAMO the active state of the DebugMonitor exception -#define M33_SHCSR_MONITORACT_RESET _u(0x0) -#define M33_SHCSR_MONITORACT_BITS _u(0x00000100) -#define M33_SHCSR_MONITORACT_MSB _u(8) -#define M33_SHCSR_MONITORACT_LSB _u(8) -#define M33_SHCSR_MONITORACT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_SHCSR_SVCALLACT -// Description : `IAAMO the active state of the SVCall exception `FTSSS -#define M33_SHCSR_SVCALLACT_RESET _u(0x0) -#define M33_SHCSR_SVCALLACT_BITS _u(0x00000080) -#define M33_SHCSR_SVCALLACT_MSB _u(7) -#define M33_SHCSR_SVCALLACT_LSB _u(7) -#define M33_SHCSR_SVCALLACT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_SHCSR_NMIACT -// Description : `IAAMO the active state of the NMI exception -#define M33_SHCSR_NMIACT_RESET _u(0x0) -#define M33_SHCSR_NMIACT_BITS _u(0x00000020) -#define M33_SHCSR_NMIACT_MSB _u(5) -#define M33_SHCSR_NMIACT_LSB _u(5) -#define M33_SHCSR_NMIACT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_SHCSR_SECUREFAULTACT -// Description : `IAAMO the active state of the SecureFault exception -#define M33_SHCSR_SECUREFAULTACT_RESET _u(0x0) -#define M33_SHCSR_SECUREFAULTACT_BITS _u(0x00000010) -#define M33_SHCSR_SECUREFAULTACT_MSB _u(4) -#define M33_SHCSR_SECUREFAULTACT_LSB _u(4) -#define M33_SHCSR_SECUREFAULTACT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_SHCSR_USGFAULTACT -// Description : `IAAMO the active state of the UsageFault exception `FTSSS -#define M33_SHCSR_USGFAULTACT_RESET _u(0x0) -#define M33_SHCSR_USGFAULTACT_BITS _u(0x00000008) -#define M33_SHCSR_USGFAULTACT_MSB _u(3) -#define M33_SHCSR_USGFAULTACT_LSB _u(3) -#define M33_SHCSR_USGFAULTACT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_SHCSR_HARDFAULTACT -// Description : Indicates and allows limited modification of the active state -// of the HardFault exception `FTSSS -#define M33_SHCSR_HARDFAULTACT_RESET _u(0x0) -#define M33_SHCSR_HARDFAULTACT_BITS _u(0x00000004) -#define M33_SHCSR_HARDFAULTACT_MSB _u(2) -#define M33_SHCSR_HARDFAULTACT_LSB _u(2) -#define M33_SHCSR_HARDFAULTACT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_SHCSR_BUSFAULTACT -// Description : `IAAMO the active state of the BusFault exception -#define M33_SHCSR_BUSFAULTACT_RESET _u(0x0) -#define M33_SHCSR_BUSFAULTACT_BITS _u(0x00000002) -#define M33_SHCSR_BUSFAULTACT_MSB _u(1) -#define M33_SHCSR_BUSFAULTACT_LSB _u(1) -#define M33_SHCSR_BUSFAULTACT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_SHCSR_MEMFAULTACT -// Description : `IAAMO the active state of the MemManage exception `FTSSS -#define M33_SHCSR_MEMFAULTACT_RESET _u(0x0) -#define M33_SHCSR_MEMFAULTACT_BITS _u(0x00000001) -#define M33_SHCSR_MEMFAULTACT_MSB _u(0) -#define M33_SHCSR_MEMFAULTACT_LSB _u(0) -#define M33_SHCSR_MEMFAULTACT_ACCESS "RW" -// ============================================================================= -// Register : M33_CFSR -// Description : Contains the three Configurable Fault Status Registers. -// -// 31:16 UFSR: Provides information on UsageFault exceptions -// -// 15:8 BFSR: Provides information on BusFault exceptions -// -// 7:0 MMFSR: Provides information on MemManage exceptions -#define M33_CFSR_OFFSET _u(0x0000ed28) -#define M33_CFSR_BITS _u(0x031fbfff) -#define M33_CFSR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_CFSR_UFSR_DIVBYZERO -// Description : Sticky flag indicating whether an integer division by zero -// error has occurred -#define M33_CFSR_UFSR_DIVBYZERO_RESET _u(0x0) -#define M33_CFSR_UFSR_DIVBYZERO_BITS _u(0x02000000) -#define M33_CFSR_UFSR_DIVBYZERO_MSB _u(25) -#define M33_CFSR_UFSR_DIVBYZERO_LSB _u(25) -#define M33_CFSR_UFSR_DIVBYZERO_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_CFSR_UFSR_UNALIGNED -// Description : Sticky flag indicating whether an unaligned access error has -// occurred -#define M33_CFSR_UFSR_UNALIGNED_RESET _u(0x0) -#define M33_CFSR_UFSR_UNALIGNED_BITS _u(0x01000000) -#define M33_CFSR_UFSR_UNALIGNED_MSB _u(24) -#define M33_CFSR_UFSR_UNALIGNED_LSB _u(24) -#define M33_CFSR_UFSR_UNALIGNED_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_CFSR_UFSR_STKOF -// Description : Sticky flag indicating whether a stack overflow error has -// occurred -#define M33_CFSR_UFSR_STKOF_RESET _u(0x0) -#define M33_CFSR_UFSR_STKOF_BITS _u(0x00100000) -#define M33_CFSR_UFSR_STKOF_MSB _u(20) -#define M33_CFSR_UFSR_STKOF_LSB _u(20) -#define M33_CFSR_UFSR_STKOF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_CFSR_UFSR_NOCP -// Description : Sticky flag indicating whether a coprocessor disabled or not -// present error has occurred -#define M33_CFSR_UFSR_NOCP_RESET _u(0x0) -#define M33_CFSR_UFSR_NOCP_BITS _u(0x00080000) -#define M33_CFSR_UFSR_NOCP_MSB _u(19) -#define M33_CFSR_UFSR_NOCP_LSB _u(19) -#define M33_CFSR_UFSR_NOCP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_CFSR_UFSR_INVPC -// Description : Sticky flag indicating whether an integrity check error has -// occurred -#define M33_CFSR_UFSR_INVPC_RESET _u(0x0) -#define M33_CFSR_UFSR_INVPC_BITS _u(0x00040000) -#define M33_CFSR_UFSR_INVPC_MSB _u(18) -#define M33_CFSR_UFSR_INVPC_LSB _u(18) -#define M33_CFSR_UFSR_INVPC_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_CFSR_UFSR_INVSTATE -// Description : Sticky flag indicating whether an EPSR.T or EPSR.IT validity -// error has occurred -#define M33_CFSR_UFSR_INVSTATE_RESET _u(0x0) -#define M33_CFSR_UFSR_INVSTATE_BITS _u(0x00020000) -#define M33_CFSR_UFSR_INVSTATE_MSB _u(17) -#define M33_CFSR_UFSR_INVSTATE_LSB _u(17) -#define M33_CFSR_UFSR_INVSTATE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_CFSR_UFSR_UNDEFINSTR -// Description : Sticky flag indicating whether an undefined instruction error -// has occurred -#define M33_CFSR_UFSR_UNDEFINSTR_RESET _u(0x0) -#define M33_CFSR_UFSR_UNDEFINSTR_BITS _u(0x00010000) -#define M33_CFSR_UFSR_UNDEFINSTR_MSB _u(16) -#define M33_CFSR_UFSR_UNDEFINSTR_LSB _u(16) -#define M33_CFSR_UFSR_UNDEFINSTR_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_CFSR_BFSR_BFARVALID -// Description : Indicates validity of the contents of the BFAR register -#define M33_CFSR_BFSR_BFARVALID_RESET _u(0x0) -#define M33_CFSR_BFSR_BFARVALID_BITS _u(0x00008000) -#define M33_CFSR_BFSR_BFARVALID_MSB _u(15) -#define M33_CFSR_BFSR_BFARVALID_LSB _u(15) -#define M33_CFSR_BFSR_BFARVALID_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_CFSR_BFSR_LSPERR -// Description : Records whether a BusFault occurred during FP lazy state -// preservation -#define M33_CFSR_BFSR_LSPERR_RESET _u(0x0) -#define M33_CFSR_BFSR_LSPERR_BITS _u(0x00002000) -#define M33_CFSR_BFSR_LSPERR_MSB _u(13) -#define M33_CFSR_BFSR_LSPERR_LSB _u(13) -#define M33_CFSR_BFSR_LSPERR_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_CFSR_BFSR_STKERR -// Description : Records whether a derived BusFault occurred during exception -// entry stacking -#define M33_CFSR_BFSR_STKERR_RESET _u(0x0) -#define M33_CFSR_BFSR_STKERR_BITS _u(0x00001000) -#define M33_CFSR_BFSR_STKERR_MSB _u(12) -#define M33_CFSR_BFSR_STKERR_LSB _u(12) -#define M33_CFSR_BFSR_STKERR_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_CFSR_BFSR_UNSTKERR -// Description : Records whether a derived BusFault occurred during exception -// return unstacking -#define M33_CFSR_BFSR_UNSTKERR_RESET _u(0x0) -#define M33_CFSR_BFSR_UNSTKERR_BITS _u(0x00000800) -#define M33_CFSR_BFSR_UNSTKERR_MSB _u(11) -#define M33_CFSR_BFSR_UNSTKERR_LSB _u(11) -#define M33_CFSR_BFSR_UNSTKERR_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_CFSR_BFSR_IMPRECISERR -// Description : Records whether an imprecise data access error has occurred -#define M33_CFSR_BFSR_IMPRECISERR_RESET _u(0x0) -#define M33_CFSR_BFSR_IMPRECISERR_BITS _u(0x00000400) -#define M33_CFSR_BFSR_IMPRECISERR_MSB _u(10) -#define M33_CFSR_BFSR_IMPRECISERR_LSB _u(10) -#define M33_CFSR_BFSR_IMPRECISERR_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_CFSR_BFSR_PRECISERR -// Description : Records whether a precise data access error has occurred -#define M33_CFSR_BFSR_PRECISERR_RESET _u(0x0) -#define M33_CFSR_BFSR_PRECISERR_BITS _u(0x00000200) -#define M33_CFSR_BFSR_PRECISERR_MSB _u(9) -#define M33_CFSR_BFSR_PRECISERR_LSB _u(9) -#define M33_CFSR_BFSR_PRECISERR_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_CFSR_BFSR_IBUSERR -// Description : Records whether a BusFault on an instruction prefetch has -// occurred -#define M33_CFSR_BFSR_IBUSERR_RESET _u(0x0) -#define M33_CFSR_BFSR_IBUSERR_BITS _u(0x00000100) -#define M33_CFSR_BFSR_IBUSERR_MSB _u(8) -#define M33_CFSR_BFSR_IBUSERR_LSB _u(8) -#define M33_CFSR_BFSR_IBUSERR_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_CFSR_MMFSR -// Description : Provides information on MemManage exceptions -#define M33_CFSR_MMFSR_RESET _u(0x00) -#define M33_CFSR_MMFSR_BITS _u(0x000000ff) -#define M33_CFSR_MMFSR_MSB _u(7) -#define M33_CFSR_MMFSR_LSB _u(0) -#define M33_CFSR_MMFSR_ACCESS "RW" -// ============================================================================= -// Register : M33_HFSR -// Description : Shows the cause of any HardFaults -#define M33_HFSR_OFFSET _u(0x0000ed2c) -#define M33_HFSR_BITS _u(0xc0000002) -#define M33_HFSR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_HFSR_DEBUGEVT -// Description : Indicates when a Debug event has occurred -#define M33_HFSR_DEBUGEVT_RESET _u(0x0) -#define M33_HFSR_DEBUGEVT_BITS _u(0x80000000) -#define M33_HFSR_DEBUGEVT_MSB _u(31) -#define M33_HFSR_DEBUGEVT_LSB _u(31) -#define M33_HFSR_DEBUGEVT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_HFSR_FORCED -// Description : Indicates that a fault with configurable priority has been -// escalated to a HardFault exception, because it could not be -// made active, because of priority, or because it was disabled -#define M33_HFSR_FORCED_RESET _u(0x0) -#define M33_HFSR_FORCED_BITS _u(0x40000000) -#define M33_HFSR_FORCED_MSB _u(30) -#define M33_HFSR_FORCED_LSB _u(30) -#define M33_HFSR_FORCED_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_HFSR_VECTTBL -// Description : Indicates when a fault has occurred because of a vector table -// read error on exception processing -#define M33_HFSR_VECTTBL_RESET _u(0x0) -#define M33_HFSR_VECTTBL_BITS _u(0x00000002) -#define M33_HFSR_VECTTBL_MSB _u(1) -#define M33_HFSR_VECTTBL_LSB _u(1) -#define M33_HFSR_VECTTBL_ACCESS "RW" -// ============================================================================= -// Register : M33_DFSR -// Description : Shows which debug event occurred -#define M33_DFSR_OFFSET _u(0x0000ed30) -#define M33_DFSR_BITS _u(0x0000001f) -#define M33_DFSR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_DFSR_EXTERNAL -// Description : Sticky flag indicating whether an External debug request debug -// event has occurred -#define M33_DFSR_EXTERNAL_RESET _u(0x0) -#define M33_DFSR_EXTERNAL_BITS _u(0x00000010) -#define M33_DFSR_EXTERNAL_MSB _u(4) -#define M33_DFSR_EXTERNAL_LSB _u(4) -#define M33_DFSR_EXTERNAL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_DFSR_VCATCH -// Description : Sticky flag indicating whether a Vector catch debug event has -// occurred -#define M33_DFSR_VCATCH_RESET _u(0x0) -#define M33_DFSR_VCATCH_BITS _u(0x00000008) -#define M33_DFSR_VCATCH_MSB _u(3) -#define M33_DFSR_VCATCH_LSB _u(3) -#define M33_DFSR_VCATCH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_DFSR_DWTTRAP -// Description : Sticky flag indicating whether a Watchpoint debug event has -// occurred -#define M33_DFSR_DWTTRAP_RESET _u(0x0) -#define M33_DFSR_DWTTRAP_BITS _u(0x00000004) -#define M33_DFSR_DWTTRAP_MSB _u(2) -#define M33_DFSR_DWTTRAP_LSB _u(2) -#define M33_DFSR_DWTTRAP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_DFSR_BKPT -// Description : Sticky flag indicating whether a Breakpoint debug event has -// occurred -#define M33_DFSR_BKPT_RESET _u(0x0) -#define M33_DFSR_BKPT_BITS _u(0x00000002) -#define M33_DFSR_BKPT_MSB _u(1) -#define M33_DFSR_BKPT_LSB _u(1) -#define M33_DFSR_BKPT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_DFSR_HALTED -// Description : Sticky flag indicating that a Halt request debug event or Step -// debug event has occurred -#define M33_DFSR_HALTED_RESET _u(0x0) -#define M33_DFSR_HALTED_BITS _u(0x00000001) -#define M33_DFSR_HALTED_MSB _u(0) -#define M33_DFSR_HALTED_LSB _u(0) -#define M33_DFSR_HALTED_ACCESS "RW" -// ============================================================================= -// Register : M33_MMFAR -// Description : Shows the address of the memory location that caused an MPU -// fault -#define M33_MMFAR_OFFSET _u(0x0000ed34) -#define M33_MMFAR_BITS _u(0xffffffff) -#define M33_MMFAR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_MMFAR_ADDRESS -// Description : This register is updated with the address of a location that -// produced a MemManage fault. The MMFSR shows the cause of the -// fault, and whether this field is valid. This field is valid -// only when MMFSR.MMARVALID is set, otherwise it is UNKNOWN -#define M33_MMFAR_ADDRESS_RESET _u(0x00000000) -#define M33_MMFAR_ADDRESS_BITS _u(0xffffffff) -#define M33_MMFAR_ADDRESS_MSB _u(31) -#define M33_MMFAR_ADDRESS_LSB _u(0) -#define M33_MMFAR_ADDRESS_ACCESS "RW" -// ============================================================================= -// Register : M33_BFAR -// Description : Shows the address associated with a precise data access -// BusFault -#define M33_BFAR_OFFSET _u(0x0000ed38) -#define M33_BFAR_BITS _u(0xffffffff) -#define M33_BFAR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_BFAR_ADDRESS -// Description : This register is updated with the address of a location that -// produced a BusFault. The BFSR shows the reason for the fault. -// This field is valid only when BFSR.BFARVALID is set, otherwise -// it is UNKNOWN -#define M33_BFAR_ADDRESS_RESET _u(0x00000000) -#define M33_BFAR_ADDRESS_BITS _u(0xffffffff) -#define M33_BFAR_ADDRESS_MSB _u(31) -#define M33_BFAR_ADDRESS_LSB _u(0) -#define M33_BFAR_ADDRESS_ACCESS "RW" -// ============================================================================= -// Register : M33_ID_PFR0 -// Description : Gives top-level information about the instruction set supported -// by the PE -#define M33_ID_PFR0_OFFSET _u(0x0000ed40) -#define M33_ID_PFR0_BITS _u(0x000000ff) -#define M33_ID_PFR0_RESET _u(0x00000030) -// ----------------------------------------------------------------------------- -// Field : M33_ID_PFR0_STATE1 -// Description : T32 instruction set support -#define M33_ID_PFR0_STATE1_RESET _u(0x3) -#define M33_ID_PFR0_STATE1_BITS _u(0x000000f0) -#define M33_ID_PFR0_STATE1_MSB _u(7) -#define M33_ID_PFR0_STATE1_LSB _u(4) -#define M33_ID_PFR0_STATE1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_ID_PFR0_STATE0 -// Description : A32 instruction set support -#define M33_ID_PFR0_STATE0_RESET _u(0x0) -#define M33_ID_PFR0_STATE0_BITS _u(0x0000000f) -#define M33_ID_PFR0_STATE0_MSB _u(3) -#define M33_ID_PFR0_STATE0_LSB _u(0) -#define M33_ID_PFR0_STATE0_ACCESS "RO" -// ============================================================================= -// Register : M33_ID_PFR1 -// Description : Gives information about the programmers' model and Extensions -// support -#define M33_ID_PFR1_OFFSET _u(0x0000ed44) -#define M33_ID_PFR1_BITS _u(0x00000ff0) -#define M33_ID_PFR1_RESET _u(0x00000520) -// ----------------------------------------------------------------------------- -// Field : M33_ID_PFR1_MPROGMOD -// Description : Identifies support for the M-Profile programmers' model support -#define M33_ID_PFR1_MPROGMOD_RESET _u(0x5) -#define M33_ID_PFR1_MPROGMOD_BITS _u(0x00000f00) -#define M33_ID_PFR1_MPROGMOD_MSB _u(11) -#define M33_ID_PFR1_MPROGMOD_LSB _u(8) -#define M33_ID_PFR1_MPROGMOD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_ID_PFR1_SECURITY -// Description : Identifies whether the Security Extension is implemented -#define M33_ID_PFR1_SECURITY_RESET _u(0x2) -#define M33_ID_PFR1_SECURITY_BITS _u(0x000000f0) -#define M33_ID_PFR1_SECURITY_MSB _u(7) -#define M33_ID_PFR1_SECURITY_LSB _u(4) -#define M33_ID_PFR1_SECURITY_ACCESS "RO" -// ============================================================================= -// Register : M33_ID_DFR0 -// Description : Provides top level information about the debug system -#define M33_ID_DFR0_OFFSET _u(0x0000ed48) -#define M33_ID_DFR0_BITS _u(0x00f00000) -#define M33_ID_DFR0_RESET _u(0x00200000) -// ----------------------------------------------------------------------------- -// Field : M33_ID_DFR0_MPROFDBG -// Description : Indicates the supported M-profile debug architecture -#define M33_ID_DFR0_MPROFDBG_RESET _u(0x2) -#define M33_ID_DFR0_MPROFDBG_BITS _u(0x00f00000) -#define M33_ID_DFR0_MPROFDBG_MSB _u(23) -#define M33_ID_DFR0_MPROFDBG_LSB _u(20) -#define M33_ID_DFR0_MPROFDBG_ACCESS "RO" -// ============================================================================= -// Register : M33_ID_AFR0 -// Description : Provides information about the IMPLEMENTATION DEFINED features -// of the PE -#define M33_ID_AFR0_OFFSET _u(0x0000ed4c) -#define M33_ID_AFR0_BITS _u(0x0000ffff) -#define M33_ID_AFR0_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_ID_AFR0_IMPDEF3 -// Description : IMPLEMENTATION DEFINED meaning -#define M33_ID_AFR0_IMPDEF3_RESET _u(0x0) -#define M33_ID_AFR0_IMPDEF3_BITS _u(0x0000f000) -#define M33_ID_AFR0_IMPDEF3_MSB _u(15) -#define M33_ID_AFR0_IMPDEF3_LSB _u(12) -#define M33_ID_AFR0_IMPDEF3_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_ID_AFR0_IMPDEF2 -// Description : IMPLEMENTATION DEFINED meaning -#define M33_ID_AFR0_IMPDEF2_RESET _u(0x0) -#define M33_ID_AFR0_IMPDEF2_BITS _u(0x00000f00) -#define M33_ID_AFR0_IMPDEF2_MSB _u(11) -#define M33_ID_AFR0_IMPDEF2_LSB _u(8) -#define M33_ID_AFR0_IMPDEF2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_ID_AFR0_IMPDEF1 -// Description : IMPLEMENTATION DEFINED meaning -#define M33_ID_AFR0_IMPDEF1_RESET _u(0x0) -#define M33_ID_AFR0_IMPDEF1_BITS _u(0x000000f0) -#define M33_ID_AFR0_IMPDEF1_MSB _u(7) -#define M33_ID_AFR0_IMPDEF1_LSB _u(4) -#define M33_ID_AFR0_IMPDEF1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_ID_AFR0_IMPDEF0 -// Description : IMPLEMENTATION DEFINED meaning -#define M33_ID_AFR0_IMPDEF0_RESET _u(0x0) -#define M33_ID_AFR0_IMPDEF0_BITS _u(0x0000000f) -#define M33_ID_AFR0_IMPDEF0_MSB _u(3) -#define M33_ID_AFR0_IMPDEF0_LSB _u(0) -#define M33_ID_AFR0_IMPDEF0_ACCESS "RO" -// ============================================================================= -// Register : M33_ID_MMFR0 -// Description : Provides information about the implemented memory model and -// memory management support -#define M33_ID_MMFR0_OFFSET _u(0x0000ed50) -#define M33_ID_MMFR0_BITS _u(0x00fffff0) -#define M33_ID_MMFR0_RESET _u(0x00101f40) -// ----------------------------------------------------------------------------- -// Field : M33_ID_MMFR0_AUXREG -// Description : Indicates support for Auxiliary Control Registers -#define M33_ID_MMFR0_AUXREG_RESET _u(0x1) -#define M33_ID_MMFR0_AUXREG_BITS _u(0x00f00000) -#define M33_ID_MMFR0_AUXREG_MSB _u(23) -#define M33_ID_MMFR0_AUXREG_LSB _u(20) -#define M33_ID_MMFR0_AUXREG_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_ID_MMFR0_TCM -// Description : Indicates support for tightly coupled memories (TCMs) -#define M33_ID_MMFR0_TCM_RESET _u(0x0) -#define M33_ID_MMFR0_TCM_BITS _u(0x000f0000) -#define M33_ID_MMFR0_TCM_MSB _u(19) -#define M33_ID_MMFR0_TCM_LSB _u(16) -#define M33_ID_MMFR0_TCM_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_ID_MMFR0_SHARELVL -// Description : Indicates the number of shareability levels implemented -#define M33_ID_MMFR0_SHARELVL_RESET _u(0x1) -#define M33_ID_MMFR0_SHARELVL_BITS _u(0x0000f000) -#define M33_ID_MMFR0_SHARELVL_MSB _u(15) -#define M33_ID_MMFR0_SHARELVL_LSB _u(12) -#define M33_ID_MMFR0_SHARELVL_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_ID_MMFR0_OUTERSHR -// Description : Indicates the outermost shareability domain implemented -#define M33_ID_MMFR0_OUTERSHR_RESET _u(0xf) -#define M33_ID_MMFR0_OUTERSHR_BITS _u(0x00000f00) -#define M33_ID_MMFR0_OUTERSHR_MSB _u(11) -#define M33_ID_MMFR0_OUTERSHR_LSB _u(8) -#define M33_ID_MMFR0_OUTERSHR_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_ID_MMFR0_PMSA -// Description : Indicates support for the protected memory system architecture -// (PMSA) -#define M33_ID_MMFR0_PMSA_RESET _u(0x4) -#define M33_ID_MMFR0_PMSA_BITS _u(0x000000f0) -#define M33_ID_MMFR0_PMSA_MSB _u(7) -#define M33_ID_MMFR0_PMSA_LSB _u(4) -#define M33_ID_MMFR0_PMSA_ACCESS "RO" -// ============================================================================= -// Register : M33_ID_MMFR1 -// Description : Provides information about the implemented memory model and -// memory management support -#define M33_ID_MMFR1_OFFSET _u(0x0000ed54) -#define M33_ID_MMFR1_BITS _u(0x00000000) -#define M33_ID_MMFR1_RESET _u(0x00000000) -#define M33_ID_MMFR1_MSB _u(31) -#define M33_ID_MMFR1_LSB _u(0) -#define M33_ID_MMFR1_ACCESS "RW" -// ============================================================================= -// Register : M33_ID_MMFR2 -// Description : Provides information about the implemented memory model and -// memory management support -#define M33_ID_MMFR2_OFFSET _u(0x0000ed58) -#define M33_ID_MMFR2_BITS _u(0x0f000000) -#define M33_ID_MMFR2_RESET _u(0x01000000) -// ----------------------------------------------------------------------------- -// Field : M33_ID_MMFR2_WFISTALL -// Description : Indicates the support for Wait For Interrupt (WFI) stalling -#define M33_ID_MMFR2_WFISTALL_RESET _u(0x1) -#define M33_ID_MMFR2_WFISTALL_BITS _u(0x0f000000) -#define M33_ID_MMFR2_WFISTALL_MSB _u(27) -#define M33_ID_MMFR2_WFISTALL_LSB _u(24) -#define M33_ID_MMFR2_WFISTALL_ACCESS "RO" -// ============================================================================= -// Register : M33_ID_MMFR3 -// Description : Provides information about the implemented memory model and -// memory management support -#define M33_ID_MMFR3_OFFSET _u(0x0000ed5c) -#define M33_ID_MMFR3_BITS _u(0x00000fff) -#define M33_ID_MMFR3_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_ID_MMFR3_BPMAINT -// Description : Indicates the supported branch predictor maintenance -#define M33_ID_MMFR3_BPMAINT_RESET _u(0x0) -#define M33_ID_MMFR3_BPMAINT_BITS _u(0x00000f00) -#define M33_ID_MMFR3_BPMAINT_MSB _u(11) -#define M33_ID_MMFR3_BPMAINT_LSB _u(8) -#define M33_ID_MMFR3_BPMAINT_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_ID_MMFR3_CMAINTSW -// Description : Indicates the supported cache maintenance operations by set/way -#define M33_ID_MMFR3_CMAINTSW_RESET _u(0x0) -#define M33_ID_MMFR3_CMAINTSW_BITS _u(0x000000f0) -#define M33_ID_MMFR3_CMAINTSW_MSB _u(7) -#define M33_ID_MMFR3_CMAINTSW_LSB _u(4) -#define M33_ID_MMFR3_CMAINTSW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_ID_MMFR3_CMAINTVA -// Description : Indicates the supported cache maintenance operations by address -#define M33_ID_MMFR3_CMAINTVA_RESET _u(0x0) -#define M33_ID_MMFR3_CMAINTVA_BITS _u(0x0000000f) -#define M33_ID_MMFR3_CMAINTVA_MSB _u(3) -#define M33_ID_MMFR3_CMAINTVA_LSB _u(0) -#define M33_ID_MMFR3_CMAINTVA_ACCESS "RO" -// ============================================================================= -// Register : M33_ID_ISAR0 -// Description : Provides information about the instruction set implemented by -// the PE -#define M33_ID_ISAR0_OFFSET _u(0x0000ed60) -#define M33_ID_ISAR0_BITS _u(0x0ffffff0) -#define M33_ID_ISAR0_RESET _u(0x08092300) -// ----------------------------------------------------------------------------- -// Field : M33_ID_ISAR0_DIVIDE -// Description : Indicates the supported Divide instructions -#define M33_ID_ISAR0_DIVIDE_RESET _u(0x8) -#define M33_ID_ISAR0_DIVIDE_BITS _u(0x0f000000) -#define M33_ID_ISAR0_DIVIDE_MSB _u(27) -#define M33_ID_ISAR0_DIVIDE_LSB _u(24) -#define M33_ID_ISAR0_DIVIDE_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_ID_ISAR0_DEBUG -// Description : Indicates the implemented Debug instructions -#define M33_ID_ISAR0_DEBUG_RESET _u(0x0) -#define M33_ID_ISAR0_DEBUG_BITS _u(0x00f00000) -#define M33_ID_ISAR0_DEBUG_MSB _u(23) -#define M33_ID_ISAR0_DEBUG_LSB _u(20) -#define M33_ID_ISAR0_DEBUG_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_ID_ISAR0_COPROC -// Description : Indicates the supported Coprocessor instructions -#define M33_ID_ISAR0_COPROC_RESET _u(0x9) -#define M33_ID_ISAR0_COPROC_BITS _u(0x000f0000) -#define M33_ID_ISAR0_COPROC_MSB _u(19) -#define M33_ID_ISAR0_COPROC_LSB _u(16) -#define M33_ID_ISAR0_COPROC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_ID_ISAR0_CMPBRANCH -// Description : Indicates the supported combined Compare and Branch -// instructions -#define M33_ID_ISAR0_CMPBRANCH_RESET _u(0x2) -#define M33_ID_ISAR0_CMPBRANCH_BITS _u(0x0000f000) -#define M33_ID_ISAR0_CMPBRANCH_MSB _u(15) -#define M33_ID_ISAR0_CMPBRANCH_LSB _u(12) -#define M33_ID_ISAR0_CMPBRANCH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_ID_ISAR0_BITFIELD -// Description : Indicates the supported bit field instructions -#define M33_ID_ISAR0_BITFIELD_RESET _u(0x3) -#define M33_ID_ISAR0_BITFIELD_BITS _u(0x00000f00) -#define M33_ID_ISAR0_BITFIELD_MSB _u(11) -#define M33_ID_ISAR0_BITFIELD_LSB _u(8) -#define M33_ID_ISAR0_BITFIELD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_ID_ISAR0_BITCOUNT -// Description : Indicates the supported bit count instructions -#define M33_ID_ISAR0_BITCOUNT_RESET _u(0x0) -#define M33_ID_ISAR0_BITCOUNT_BITS _u(0x000000f0) -#define M33_ID_ISAR0_BITCOUNT_MSB _u(7) -#define M33_ID_ISAR0_BITCOUNT_LSB _u(4) -#define M33_ID_ISAR0_BITCOUNT_ACCESS "RO" -// ============================================================================= -// Register : M33_ID_ISAR1 -// Description : Provides information about the instruction set implemented by -// the PE -#define M33_ID_ISAR1_OFFSET _u(0x0000ed64) -#define M33_ID_ISAR1_BITS _u(0x0ffff000) -#define M33_ID_ISAR1_RESET _u(0x05725000) -// ----------------------------------------------------------------------------- -// Field : M33_ID_ISAR1_INTERWORK -// Description : Indicates the implemented Interworking instructions -#define M33_ID_ISAR1_INTERWORK_RESET _u(0x5) -#define M33_ID_ISAR1_INTERWORK_BITS _u(0x0f000000) -#define M33_ID_ISAR1_INTERWORK_MSB _u(27) -#define M33_ID_ISAR1_INTERWORK_LSB _u(24) -#define M33_ID_ISAR1_INTERWORK_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_ID_ISAR1_IMMEDIATE -// Description : Indicates the implemented for data-processing instructions with -// long immediates -#define M33_ID_ISAR1_IMMEDIATE_RESET _u(0x7) -#define M33_ID_ISAR1_IMMEDIATE_BITS _u(0x00f00000) -#define M33_ID_ISAR1_IMMEDIATE_MSB _u(23) -#define M33_ID_ISAR1_IMMEDIATE_LSB _u(20) -#define M33_ID_ISAR1_IMMEDIATE_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_ID_ISAR1_IFTHEN -// Description : Indicates the implemented If-Then instructions -#define M33_ID_ISAR1_IFTHEN_RESET _u(0x2) -#define M33_ID_ISAR1_IFTHEN_BITS _u(0x000f0000) -#define M33_ID_ISAR1_IFTHEN_MSB _u(19) -#define M33_ID_ISAR1_IFTHEN_LSB _u(16) -#define M33_ID_ISAR1_IFTHEN_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_ID_ISAR1_EXTEND -// Description : Indicates the implemented Extend instructions -#define M33_ID_ISAR1_EXTEND_RESET _u(0x5) -#define M33_ID_ISAR1_EXTEND_BITS _u(0x0000f000) -#define M33_ID_ISAR1_EXTEND_MSB _u(15) -#define M33_ID_ISAR1_EXTEND_LSB _u(12) -#define M33_ID_ISAR1_EXTEND_ACCESS "RO" -// ============================================================================= -// Register : M33_ID_ISAR2 -// Description : Provides information about the instruction set implemented by -// the PE -#define M33_ID_ISAR2_OFFSET _u(0x0000ed68) -#define M33_ID_ISAR2_BITS _u(0xf0ffffff) -#define M33_ID_ISAR2_RESET _u(0x30173426) -// ----------------------------------------------------------------------------- -// Field : M33_ID_ISAR2_REVERSAL -// Description : Indicates the implemented Reversal instructions -#define M33_ID_ISAR2_REVERSAL_RESET _u(0x3) -#define M33_ID_ISAR2_REVERSAL_BITS _u(0xf0000000) -#define M33_ID_ISAR2_REVERSAL_MSB _u(31) -#define M33_ID_ISAR2_REVERSAL_LSB _u(28) -#define M33_ID_ISAR2_REVERSAL_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_ID_ISAR2_MULTU -// Description : Indicates the implemented advanced unsigned Multiply -// instructions -#define M33_ID_ISAR2_MULTU_RESET _u(0x1) -#define M33_ID_ISAR2_MULTU_BITS _u(0x00f00000) -#define M33_ID_ISAR2_MULTU_MSB _u(23) -#define M33_ID_ISAR2_MULTU_LSB _u(20) -#define M33_ID_ISAR2_MULTU_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_ID_ISAR2_MULTS -// Description : Indicates the implemented advanced signed Multiply instructions -#define M33_ID_ISAR2_MULTS_RESET _u(0x7) -#define M33_ID_ISAR2_MULTS_BITS _u(0x000f0000) -#define M33_ID_ISAR2_MULTS_MSB _u(19) -#define M33_ID_ISAR2_MULTS_LSB _u(16) -#define M33_ID_ISAR2_MULTS_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_ID_ISAR2_MULT -// Description : Indicates the implemented additional Multiply instructions -#define M33_ID_ISAR2_MULT_RESET _u(0x3) -#define M33_ID_ISAR2_MULT_BITS _u(0x0000f000) -#define M33_ID_ISAR2_MULT_MSB _u(15) -#define M33_ID_ISAR2_MULT_LSB _u(12) -#define M33_ID_ISAR2_MULT_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_ID_ISAR2_MULTIACCESSINT -// Description : Indicates the support for interruptible multi-access -// instructions -#define M33_ID_ISAR2_MULTIACCESSINT_RESET _u(0x4) -#define M33_ID_ISAR2_MULTIACCESSINT_BITS _u(0x00000f00) -#define M33_ID_ISAR2_MULTIACCESSINT_MSB _u(11) -#define M33_ID_ISAR2_MULTIACCESSINT_LSB _u(8) -#define M33_ID_ISAR2_MULTIACCESSINT_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_ID_ISAR2_MEMHINT -// Description : Indicates the implemented Memory Hint instructions -#define M33_ID_ISAR2_MEMHINT_RESET _u(0x2) -#define M33_ID_ISAR2_MEMHINT_BITS _u(0x000000f0) -#define M33_ID_ISAR2_MEMHINT_MSB _u(7) -#define M33_ID_ISAR2_MEMHINT_LSB _u(4) -#define M33_ID_ISAR2_MEMHINT_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_ID_ISAR2_LOADSTORE -// Description : Indicates the implemented additional load/store instructions -#define M33_ID_ISAR2_LOADSTORE_RESET _u(0x6) -#define M33_ID_ISAR2_LOADSTORE_BITS _u(0x0000000f) -#define M33_ID_ISAR2_LOADSTORE_MSB _u(3) -#define M33_ID_ISAR2_LOADSTORE_LSB _u(0) -#define M33_ID_ISAR2_LOADSTORE_ACCESS "RO" -// ============================================================================= -// Register : M33_ID_ISAR3 -// Description : Provides information about the instruction set implemented by -// the PE -#define M33_ID_ISAR3_OFFSET _u(0x0000ed6c) -#define M33_ID_ISAR3_BITS _u(0x0fffffff) -#define M33_ID_ISAR3_RESET _u(0x07895729) -// ----------------------------------------------------------------------------- -// Field : M33_ID_ISAR3_TRUENOP -// Description : Indicates the implemented true NOP instructions -#define M33_ID_ISAR3_TRUENOP_RESET _u(0x7) -#define M33_ID_ISAR3_TRUENOP_BITS _u(0x0f000000) -#define M33_ID_ISAR3_TRUENOP_MSB _u(27) -#define M33_ID_ISAR3_TRUENOP_LSB _u(24) -#define M33_ID_ISAR3_TRUENOP_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_ID_ISAR3_T32COPY -// Description : Indicates the support for T32 non flag-setting MOV instructions -#define M33_ID_ISAR3_T32COPY_RESET _u(0x8) -#define M33_ID_ISAR3_T32COPY_BITS _u(0x00f00000) -#define M33_ID_ISAR3_T32COPY_MSB _u(23) -#define M33_ID_ISAR3_T32COPY_LSB _u(20) -#define M33_ID_ISAR3_T32COPY_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_ID_ISAR3_TABBRANCH -// Description : Indicates the implemented Table Branch instructions -#define M33_ID_ISAR3_TABBRANCH_RESET _u(0x9) -#define M33_ID_ISAR3_TABBRANCH_BITS _u(0x000f0000) -#define M33_ID_ISAR3_TABBRANCH_MSB _u(19) -#define M33_ID_ISAR3_TABBRANCH_LSB _u(16) -#define M33_ID_ISAR3_TABBRANCH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_ID_ISAR3_SYNCHPRIM -// Description : Used in conjunction with ID_ISAR4.SynchPrim_frac to indicate -// the implemented Synchronization Primitive instructions -#define M33_ID_ISAR3_SYNCHPRIM_RESET _u(0x5) -#define M33_ID_ISAR3_SYNCHPRIM_BITS _u(0x0000f000) -#define M33_ID_ISAR3_SYNCHPRIM_MSB _u(15) -#define M33_ID_ISAR3_SYNCHPRIM_LSB _u(12) -#define M33_ID_ISAR3_SYNCHPRIM_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_ID_ISAR3_SVC -// Description : Indicates the implemented SVC instructions -#define M33_ID_ISAR3_SVC_RESET _u(0x7) -#define M33_ID_ISAR3_SVC_BITS _u(0x00000f00) -#define M33_ID_ISAR3_SVC_MSB _u(11) -#define M33_ID_ISAR3_SVC_LSB _u(8) -#define M33_ID_ISAR3_SVC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_ID_ISAR3_SIMD -// Description : Indicates the implemented SIMD instructions -#define M33_ID_ISAR3_SIMD_RESET _u(0x2) -#define M33_ID_ISAR3_SIMD_BITS _u(0x000000f0) -#define M33_ID_ISAR3_SIMD_MSB _u(7) -#define M33_ID_ISAR3_SIMD_LSB _u(4) -#define M33_ID_ISAR3_SIMD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_ID_ISAR3_SATURATE -// Description : Indicates the implemented saturating instructions -#define M33_ID_ISAR3_SATURATE_RESET _u(0x9) -#define M33_ID_ISAR3_SATURATE_BITS _u(0x0000000f) -#define M33_ID_ISAR3_SATURATE_MSB _u(3) -#define M33_ID_ISAR3_SATURATE_LSB _u(0) -#define M33_ID_ISAR3_SATURATE_ACCESS "RO" -// ============================================================================= -// Register : M33_ID_ISAR4 -// Description : Provides information about the instruction set implemented by -// the PE -#define M33_ID_ISAR4_OFFSET _u(0x0000ed70) -#define M33_ID_ISAR4_BITS _u(0x0fff0fff) -#define M33_ID_ISAR4_RESET _u(0x01310132) -// ----------------------------------------------------------------------------- -// Field : M33_ID_ISAR4_PSR_M -// Description : Indicates the implemented M profile instructions to modify the -// PSRs -#define M33_ID_ISAR4_PSR_M_RESET _u(0x1) -#define M33_ID_ISAR4_PSR_M_BITS _u(0x0f000000) -#define M33_ID_ISAR4_PSR_M_MSB _u(27) -#define M33_ID_ISAR4_PSR_M_LSB _u(24) -#define M33_ID_ISAR4_PSR_M_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_ID_ISAR4_SYNCPRIM_FRAC -// Description : Used in conjunction with ID_ISAR3.SynchPrim to indicate the -// implemented Synchronization Primitive instructions -#define M33_ID_ISAR4_SYNCPRIM_FRAC_RESET _u(0x3) -#define M33_ID_ISAR4_SYNCPRIM_FRAC_BITS _u(0x00f00000) -#define M33_ID_ISAR4_SYNCPRIM_FRAC_MSB _u(23) -#define M33_ID_ISAR4_SYNCPRIM_FRAC_LSB _u(20) -#define M33_ID_ISAR4_SYNCPRIM_FRAC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_ID_ISAR4_BARRIER -// Description : Indicates the implemented Barrier instructions -#define M33_ID_ISAR4_BARRIER_RESET _u(0x1) -#define M33_ID_ISAR4_BARRIER_BITS _u(0x000f0000) -#define M33_ID_ISAR4_BARRIER_MSB _u(19) -#define M33_ID_ISAR4_BARRIER_LSB _u(16) -#define M33_ID_ISAR4_BARRIER_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_ID_ISAR4_WRITEBACK -// Description : Indicates the support for writeback addressing modes -#define M33_ID_ISAR4_WRITEBACK_RESET _u(0x1) -#define M33_ID_ISAR4_WRITEBACK_BITS _u(0x00000f00) -#define M33_ID_ISAR4_WRITEBACK_MSB _u(11) -#define M33_ID_ISAR4_WRITEBACK_LSB _u(8) -#define M33_ID_ISAR4_WRITEBACK_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_ID_ISAR4_WITHSHIFTS -// Description : Indicates the support for writeback addressing modes -#define M33_ID_ISAR4_WITHSHIFTS_RESET _u(0x3) -#define M33_ID_ISAR4_WITHSHIFTS_BITS _u(0x000000f0) -#define M33_ID_ISAR4_WITHSHIFTS_MSB _u(7) -#define M33_ID_ISAR4_WITHSHIFTS_LSB _u(4) -#define M33_ID_ISAR4_WITHSHIFTS_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_ID_ISAR4_UNPRIV -// Description : Indicates the implemented unprivileged instructions -#define M33_ID_ISAR4_UNPRIV_RESET _u(0x2) -#define M33_ID_ISAR4_UNPRIV_BITS _u(0x0000000f) -#define M33_ID_ISAR4_UNPRIV_MSB _u(3) -#define M33_ID_ISAR4_UNPRIV_LSB _u(0) -#define M33_ID_ISAR4_UNPRIV_ACCESS "RO" -// ============================================================================= -// Register : M33_ID_ISAR5 -// Description : Provides information about the instruction set implemented by -// the PE -#define M33_ID_ISAR5_OFFSET _u(0x0000ed74) -#define M33_ID_ISAR5_BITS _u(0x00000000) -#define M33_ID_ISAR5_RESET _u(0x00000000) -#define M33_ID_ISAR5_MSB _u(31) -#define M33_ID_ISAR5_LSB _u(0) -#define M33_ID_ISAR5_ACCESS "RW" -// ============================================================================= -// Register : M33_CTR -// Description : Provides information about the architecture of the caches. CTR -// is RES0 if CLIDR is zero. -#define M33_CTR_OFFSET _u(0x0000ed7c) -#define M33_CTR_BITS _u(0x8fffc00f) -#define M33_CTR_RESET _u(0x8000c000) -// ----------------------------------------------------------------------------- -// Field : M33_CTR_RES1 -// Description : Reserved, RES1 -#define M33_CTR_RES1_RESET _u(0x1) -#define M33_CTR_RES1_BITS _u(0x80000000) -#define M33_CTR_RES1_MSB _u(31) -#define M33_CTR_RES1_LSB _u(31) -#define M33_CTR_RES1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_CTR_CWG -// Description : Log2 of the number of words of the maximum size of memory that -// can be overwritten as a result of the eviction of a cache entry -// that has had a memory location in it modified -#define M33_CTR_CWG_RESET _u(0x0) -#define M33_CTR_CWG_BITS _u(0x0f000000) -#define M33_CTR_CWG_MSB _u(27) -#define M33_CTR_CWG_LSB _u(24) -#define M33_CTR_CWG_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_CTR_ERG -// Description : Log2 of the number of words of the maximum size of the -// reservation granule that has been implemented for the Load- -// Exclusive and Store-Exclusive instructions -#define M33_CTR_ERG_RESET _u(0x0) -#define M33_CTR_ERG_BITS _u(0x00f00000) -#define M33_CTR_ERG_MSB _u(23) -#define M33_CTR_ERG_LSB _u(20) -#define M33_CTR_ERG_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_CTR_DMINLINE -// Description : Log2 of the number of words in the smallest cache line of all -// the data caches and unified caches that are controlled by the -// PE -#define M33_CTR_DMINLINE_RESET _u(0x0) -#define M33_CTR_DMINLINE_BITS _u(0x000f0000) -#define M33_CTR_DMINLINE_MSB _u(19) -#define M33_CTR_DMINLINE_LSB _u(16) -#define M33_CTR_DMINLINE_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_CTR_RES1_1 -// Description : Reserved, RES1 -#define M33_CTR_RES1_1_RESET _u(0x3) -#define M33_CTR_RES1_1_BITS _u(0x0000c000) -#define M33_CTR_RES1_1_MSB _u(15) -#define M33_CTR_RES1_1_LSB _u(14) -#define M33_CTR_RES1_1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_CTR_IMINLINE -// Description : Log2 of the number of words in the smallest cache line of all -// the instruction caches that are controlled by the PE -#define M33_CTR_IMINLINE_RESET _u(0x0) -#define M33_CTR_IMINLINE_BITS _u(0x0000000f) -#define M33_CTR_IMINLINE_MSB _u(3) -#define M33_CTR_IMINLINE_LSB _u(0) -#define M33_CTR_IMINLINE_ACCESS "RO" -// ============================================================================= -// Register : M33_CPACR -// Description : Specifies the access privileges for coprocessors and the FP -// Extension -#define M33_CPACR_OFFSET _u(0x0000ed88) -#define M33_CPACR_BITS _u(0x00f0ffff) -#define M33_CPACR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_CPACR_CP11 -// Description : The value in this field is ignored. If the implementation does -// not include the FP Extension, this field is RAZ/WI. If the -// value of this bit is not programmed to the same value as the -// CP10 field, then the value is UNKNOWN -#define M33_CPACR_CP11_RESET _u(0x0) -#define M33_CPACR_CP11_BITS _u(0x00c00000) -#define M33_CPACR_CP11_MSB _u(23) -#define M33_CPACR_CP11_LSB _u(22) -#define M33_CPACR_CP11_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_CPACR_CP10 -// Description : Defines the access rights for the floating-point functionality -#define M33_CPACR_CP10_RESET _u(0x0) -#define M33_CPACR_CP10_BITS _u(0x00300000) -#define M33_CPACR_CP10_MSB _u(21) -#define M33_CPACR_CP10_LSB _u(20) -#define M33_CPACR_CP10_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_CPACR_CP7 -// Description : Controls access privileges for coprocessor 7 -#define M33_CPACR_CP7_RESET _u(0x0) -#define M33_CPACR_CP7_BITS _u(0x0000c000) -#define M33_CPACR_CP7_MSB _u(15) -#define M33_CPACR_CP7_LSB _u(14) -#define M33_CPACR_CP7_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_CPACR_CP6 -// Description : Controls access privileges for coprocessor 6 -#define M33_CPACR_CP6_RESET _u(0x0) -#define M33_CPACR_CP6_BITS _u(0x00003000) -#define M33_CPACR_CP6_MSB _u(13) -#define M33_CPACR_CP6_LSB _u(12) -#define M33_CPACR_CP6_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_CPACR_CP5 -// Description : Controls access privileges for coprocessor 5 -#define M33_CPACR_CP5_RESET _u(0x0) -#define M33_CPACR_CP5_BITS _u(0x00000c00) -#define M33_CPACR_CP5_MSB _u(11) -#define M33_CPACR_CP5_LSB _u(10) -#define M33_CPACR_CP5_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_CPACR_CP4 -// Description : Controls access privileges for coprocessor 4 -#define M33_CPACR_CP4_RESET _u(0x0) -#define M33_CPACR_CP4_BITS _u(0x00000300) -#define M33_CPACR_CP4_MSB _u(9) -#define M33_CPACR_CP4_LSB _u(8) -#define M33_CPACR_CP4_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_CPACR_CP3 -// Description : Controls access privileges for coprocessor 3 -#define M33_CPACR_CP3_RESET _u(0x0) -#define M33_CPACR_CP3_BITS _u(0x000000c0) -#define M33_CPACR_CP3_MSB _u(7) -#define M33_CPACR_CP3_LSB _u(6) -#define M33_CPACR_CP3_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_CPACR_CP2 -// Description : Controls access privileges for coprocessor 2 -#define M33_CPACR_CP2_RESET _u(0x0) -#define M33_CPACR_CP2_BITS _u(0x00000030) -#define M33_CPACR_CP2_MSB _u(5) -#define M33_CPACR_CP2_LSB _u(4) -#define M33_CPACR_CP2_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_CPACR_CP1 -// Description : Controls access privileges for coprocessor 1 -#define M33_CPACR_CP1_RESET _u(0x0) -#define M33_CPACR_CP1_BITS _u(0x0000000c) -#define M33_CPACR_CP1_MSB _u(3) -#define M33_CPACR_CP1_LSB _u(2) -#define M33_CPACR_CP1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_CPACR_CP0 -// Description : Controls access privileges for coprocessor 0 -#define M33_CPACR_CP0_RESET _u(0x0) -#define M33_CPACR_CP0_BITS _u(0x00000003) -#define M33_CPACR_CP0_MSB _u(1) -#define M33_CPACR_CP0_LSB _u(0) -#define M33_CPACR_CP0_ACCESS "RW" -// ============================================================================= -// Register : M33_NSACR -// Description : Defines the Non-secure access permissions for both the FP -// Extension and coprocessors CP0 to CP7 -#define M33_NSACR_OFFSET _u(0x0000ed8c) -#define M33_NSACR_BITS _u(0x00000cff) -#define M33_NSACR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_NSACR_CP11 -// Description : Enables Non-secure access to the Floating-point Extension -#define M33_NSACR_CP11_RESET _u(0x0) -#define M33_NSACR_CP11_BITS _u(0x00000800) -#define M33_NSACR_CP11_MSB _u(11) -#define M33_NSACR_CP11_LSB _u(11) -#define M33_NSACR_CP11_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_NSACR_CP10 -// Description : Enables Non-secure access to the Floating-point Extension -#define M33_NSACR_CP10_RESET _u(0x0) -#define M33_NSACR_CP10_BITS _u(0x00000400) -#define M33_NSACR_CP10_MSB _u(10) -#define M33_NSACR_CP10_LSB _u(10) -#define M33_NSACR_CP10_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_NSACR_CP7 -// Description : Enables Non-secure access to coprocessor CP7 -#define M33_NSACR_CP7_RESET _u(0x0) -#define M33_NSACR_CP7_BITS _u(0x00000080) -#define M33_NSACR_CP7_MSB _u(7) -#define M33_NSACR_CP7_LSB _u(7) -#define M33_NSACR_CP7_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_NSACR_CP6 -// Description : Enables Non-secure access to coprocessor CP6 -#define M33_NSACR_CP6_RESET _u(0x0) -#define M33_NSACR_CP6_BITS _u(0x00000040) -#define M33_NSACR_CP6_MSB _u(6) -#define M33_NSACR_CP6_LSB _u(6) -#define M33_NSACR_CP6_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_NSACR_CP5 -// Description : Enables Non-secure access to coprocessor CP5 -#define M33_NSACR_CP5_RESET _u(0x0) -#define M33_NSACR_CP5_BITS _u(0x00000020) -#define M33_NSACR_CP5_MSB _u(5) -#define M33_NSACR_CP5_LSB _u(5) -#define M33_NSACR_CP5_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_NSACR_CP4 -// Description : Enables Non-secure access to coprocessor CP4 -#define M33_NSACR_CP4_RESET _u(0x0) -#define M33_NSACR_CP4_BITS _u(0x00000010) -#define M33_NSACR_CP4_MSB _u(4) -#define M33_NSACR_CP4_LSB _u(4) -#define M33_NSACR_CP4_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_NSACR_CP3 -// Description : Enables Non-secure access to coprocessor CP3 -#define M33_NSACR_CP3_RESET _u(0x0) -#define M33_NSACR_CP3_BITS _u(0x00000008) -#define M33_NSACR_CP3_MSB _u(3) -#define M33_NSACR_CP3_LSB _u(3) -#define M33_NSACR_CP3_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_NSACR_CP2 -// Description : Enables Non-secure access to coprocessor CP2 -#define M33_NSACR_CP2_RESET _u(0x0) -#define M33_NSACR_CP2_BITS _u(0x00000004) -#define M33_NSACR_CP2_MSB _u(2) -#define M33_NSACR_CP2_LSB _u(2) -#define M33_NSACR_CP2_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_NSACR_CP1 -// Description : Enables Non-secure access to coprocessor CP1 -#define M33_NSACR_CP1_RESET _u(0x0) -#define M33_NSACR_CP1_BITS _u(0x00000002) -#define M33_NSACR_CP1_MSB _u(1) -#define M33_NSACR_CP1_LSB _u(1) -#define M33_NSACR_CP1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_NSACR_CP0 -// Description : Enables Non-secure access to coprocessor CP0 -#define M33_NSACR_CP0_RESET _u(0x0) -#define M33_NSACR_CP0_BITS _u(0x00000001) -#define M33_NSACR_CP0_MSB _u(0) -#define M33_NSACR_CP0_LSB _u(0) -#define M33_NSACR_CP0_ACCESS "RW" -// ============================================================================= -// Register : M33_MPU_TYPE -// Description : The MPU Type Register indicates how many regions the MPU `FTSSS -// supports -#define M33_MPU_TYPE_OFFSET _u(0x0000ed90) -#define M33_MPU_TYPE_BITS _u(0x0000ff01) -#define M33_MPU_TYPE_RESET _u(0x00000800) -// ----------------------------------------------------------------------------- -// Field : M33_MPU_TYPE_DREGION -// Description : Number of regions supported by the MPU -#define M33_MPU_TYPE_DREGION_RESET _u(0x08) -#define M33_MPU_TYPE_DREGION_BITS _u(0x0000ff00) -#define M33_MPU_TYPE_DREGION_MSB _u(15) -#define M33_MPU_TYPE_DREGION_LSB _u(8) -#define M33_MPU_TYPE_DREGION_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_MPU_TYPE_SEPARATE -// Description : Indicates support for separate instructions and data address -// regions -#define M33_MPU_TYPE_SEPARATE_RESET _u(0x0) -#define M33_MPU_TYPE_SEPARATE_BITS _u(0x00000001) -#define M33_MPU_TYPE_SEPARATE_MSB _u(0) -#define M33_MPU_TYPE_SEPARATE_LSB _u(0) -#define M33_MPU_TYPE_SEPARATE_ACCESS "RO" -// ============================================================================= -// Register : M33_MPU_CTRL -// Description : Enables the MPU and, when the MPU is enabled, controls whether -// the default memory map is enabled as a background region for -// privileged accesses, and whether the MPU is enabled for -// HardFaults, NMIs, and exception handlers when FAULTMASK is set -// to 1 -#define M33_MPU_CTRL_OFFSET _u(0x0000ed94) -#define M33_MPU_CTRL_BITS _u(0x00000007) -#define M33_MPU_CTRL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_MPU_CTRL_PRIVDEFENA -// Description : Controls whether the default memory map is enabled for -// privileged software -#define M33_MPU_CTRL_PRIVDEFENA_RESET _u(0x0) -#define M33_MPU_CTRL_PRIVDEFENA_BITS _u(0x00000004) -#define M33_MPU_CTRL_PRIVDEFENA_MSB _u(2) -#define M33_MPU_CTRL_PRIVDEFENA_LSB _u(2) -#define M33_MPU_CTRL_PRIVDEFENA_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_MPU_CTRL_HFNMIENA -// Description : Controls whether handlers executing with priority less than 0 -// access memory with the MPU enabled or disabled. This applies to -// HardFaults, NMIs, and exception handlers when FAULTMASK is set -// to 1 -#define M33_MPU_CTRL_HFNMIENA_RESET _u(0x0) -#define M33_MPU_CTRL_HFNMIENA_BITS _u(0x00000002) -#define M33_MPU_CTRL_HFNMIENA_MSB _u(1) -#define M33_MPU_CTRL_HFNMIENA_LSB _u(1) -#define M33_MPU_CTRL_HFNMIENA_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_MPU_CTRL_ENABLE -// Description : Enables the MPU -#define M33_MPU_CTRL_ENABLE_RESET _u(0x0) -#define M33_MPU_CTRL_ENABLE_BITS _u(0x00000001) -#define M33_MPU_CTRL_ENABLE_MSB _u(0) -#define M33_MPU_CTRL_ENABLE_LSB _u(0) -#define M33_MPU_CTRL_ENABLE_ACCESS "RW" -// ============================================================================= -// Register : M33_MPU_RNR -// Description : Selects the region currently accessed by MPU_RBAR and MPU_RLAR -#define M33_MPU_RNR_OFFSET _u(0x0000ed98) -#define M33_MPU_RNR_BITS _u(0x00000007) -#define M33_MPU_RNR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_MPU_RNR_REGION -// Description : Indicates the memory region accessed by MPU_RBAR and MPU_RLAR -#define M33_MPU_RNR_REGION_RESET _u(0x0) -#define M33_MPU_RNR_REGION_BITS _u(0x00000007) -#define M33_MPU_RNR_REGION_MSB _u(2) -#define M33_MPU_RNR_REGION_LSB _u(0) -#define M33_MPU_RNR_REGION_ACCESS "RW" -// ============================================================================= -// Register : M33_MPU_RBAR -// Description : Provides indirect read and write access to the base address of -// the currently selected MPU region `FTSSS -#define M33_MPU_RBAR_OFFSET _u(0x0000ed9c) -#define M33_MPU_RBAR_BITS _u(0xffffffff) -#define M33_MPU_RBAR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_MPU_RBAR_BASE -// Description : Contains bits [31:5] of the lower inclusive limit of the -// selected MPU memory region. This value is zero extended to -// provide the base address to be checked against -#define M33_MPU_RBAR_BASE_RESET _u(0x0000000) -#define M33_MPU_RBAR_BASE_BITS _u(0xffffffe0) -#define M33_MPU_RBAR_BASE_MSB _u(31) -#define M33_MPU_RBAR_BASE_LSB _u(5) -#define M33_MPU_RBAR_BASE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_MPU_RBAR_SH -// Description : Defines the Shareability domain of this region for Normal -// memory -#define M33_MPU_RBAR_SH_RESET _u(0x0) -#define M33_MPU_RBAR_SH_BITS _u(0x00000018) -#define M33_MPU_RBAR_SH_MSB _u(4) -#define M33_MPU_RBAR_SH_LSB _u(3) -#define M33_MPU_RBAR_SH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_MPU_RBAR_AP -// Description : Defines the access permissions for this region -#define M33_MPU_RBAR_AP_RESET _u(0x0) -#define M33_MPU_RBAR_AP_BITS _u(0x00000006) -#define M33_MPU_RBAR_AP_MSB _u(2) -#define M33_MPU_RBAR_AP_LSB _u(1) -#define M33_MPU_RBAR_AP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_MPU_RBAR_XN -// Description : Defines whether code can be executed from this region -#define M33_MPU_RBAR_XN_RESET _u(0x0) -#define M33_MPU_RBAR_XN_BITS _u(0x00000001) -#define M33_MPU_RBAR_XN_MSB _u(0) -#define M33_MPU_RBAR_XN_LSB _u(0) -#define M33_MPU_RBAR_XN_ACCESS "RW" -// ============================================================================= -// Register : M33_MPU_RLAR -// Description : Provides indirect read and write access to the limit address of -// the currently selected MPU region `FTSSS -#define M33_MPU_RLAR_OFFSET _u(0x0000eda0) -#define M33_MPU_RLAR_BITS _u(0xffffffef) -#define M33_MPU_RLAR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_MPU_RLAR_LIMIT -// Description : Contains bits [31:5] of the upper inclusive limit of the -// selected MPU memory region. This value is postfixed with 0x1F -// to provide the limit address to be checked against -#define M33_MPU_RLAR_LIMIT_RESET _u(0x0000000) -#define M33_MPU_RLAR_LIMIT_BITS _u(0xffffffe0) -#define M33_MPU_RLAR_LIMIT_MSB _u(31) -#define M33_MPU_RLAR_LIMIT_LSB _u(5) -#define M33_MPU_RLAR_LIMIT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_MPU_RLAR_ATTRINDX -// Description : Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 -// fields -#define M33_MPU_RLAR_ATTRINDX_RESET _u(0x0) -#define M33_MPU_RLAR_ATTRINDX_BITS _u(0x0000000e) -#define M33_MPU_RLAR_ATTRINDX_MSB _u(3) -#define M33_MPU_RLAR_ATTRINDX_LSB _u(1) -#define M33_MPU_RLAR_ATTRINDX_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_MPU_RLAR_EN -// Description : Region enable -#define M33_MPU_RLAR_EN_RESET _u(0x0) -#define M33_MPU_RLAR_EN_BITS _u(0x00000001) -#define M33_MPU_RLAR_EN_MSB _u(0) -#define M33_MPU_RLAR_EN_LSB _u(0) -#define M33_MPU_RLAR_EN_ACCESS "RW" -// ============================================================================= -// Register : M33_MPU_RBAR_A1 -// Description : Provides indirect read and write access to the base address of -// the MPU region selected by MPU_RNR[7:2]:(1[1:0]) `FTSSS -#define M33_MPU_RBAR_A1_OFFSET _u(0x0000eda4) -#define M33_MPU_RBAR_A1_BITS _u(0xffffffff) -#define M33_MPU_RBAR_A1_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_MPU_RBAR_A1_BASE -// Description : Contains bits [31:5] of the lower inclusive limit of the -// selected MPU memory region. This value is zero extended to -// provide the base address to be checked against -#define M33_MPU_RBAR_A1_BASE_RESET _u(0x0000000) -#define M33_MPU_RBAR_A1_BASE_BITS _u(0xffffffe0) -#define M33_MPU_RBAR_A1_BASE_MSB _u(31) -#define M33_MPU_RBAR_A1_BASE_LSB _u(5) -#define M33_MPU_RBAR_A1_BASE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_MPU_RBAR_A1_SH -// Description : Defines the Shareability domain of this region for Normal -// memory -#define M33_MPU_RBAR_A1_SH_RESET _u(0x0) -#define M33_MPU_RBAR_A1_SH_BITS _u(0x00000018) -#define M33_MPU_RBAR_A1_SH_MSB _u(4) -#define M33_MPU_RBAR_A1_SH_LSB _u(3) -#define M33_MPU_RBAR_A1_SH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_MPU_RBAR_A1_AP -// Description : Defines the access permissions for this region -#define M33_MPU_RBAR_A1_AP_RESET _u(0x0) -#define M33_MPU_RBAR_A1_AP_BITS _u(0x00000006) -#define M33_MPU_RBAR_A1_AP_MSB _u(2) -#define M33_MPU_RBAR_A1_AP_LSB _u(1) -#define M33_MPU_RBAR_A1_AP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_MPU_RBAR_A1_XN -// Description : Defines whether code can be executed from this region -#define M33_MPU_RBAR_A1_XN_RESET _u(0x0) -#define M33_MPU_RBAR_A1_XN_BITS _u(0x00000001) -#define M33_MPU_RBAR_A1_XN_MSB _u(0) -#define M33_MPU_RBAR_A1_XN_LSB _u(0) -#define M33_MPU_RBAR_A1_XN_ACCESS "RW" -// ============================================================================= -// Register : M33_MPU_RLAR_A1 -// Description : Provides indirect read and write access to the limit address of -// the currently selected MPU region selected by -// MPU_RNR[7:2]:(1[1:0]) `FTSSS -#define M33_MPU_RLAR_A1_OFFSET _u(0x0000eda8) -#define M33_MPU_RLAR_A1_BITS _u(0xffffffef) -#define M33_MPU_RLAR_A1_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_MPU_RLAR_A1_LIMIT -// Description : Contains bits [31:5] of the upper inclusive limit of the -// selected MPU memory region. This value is postfixed with 0x1F -// to provide the limit address to be checked against -#define M33_MPU_RLAR_A1_LIMIT_RESET _u(0x0000000) -#define M33_MPU_RLAR_A1_LIMIT_BITS _u(0xffffffe0) -#define M33_MPU_RLAR_A1_LIMIT_MSB _u(31) -#define M33_MPU_RLAR_A1_LIMIT_LSB _u(5) -#define M33_MPU_RLAR_A1_LIMIT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_MPU_RLAR_A1_ATTRINDX -// Description : Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 -// fields -#define M33_MPU_RLAR_A1_ATTRINDX_RESET _u(0x0) -#define M33_MPU_RLAR_A1_ATTRINDX_BITS _u(0x0000000e) -#define M33_MPU_RLAR_A1_ATTRINDX_MSB _u(3) -#define M33_MPU_RLAR_A1_ATTRINDX_LSB _u(1) -#define M33_MPU_RLAR_A1_ATTRINDX_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_MPU_RLAR_A1_EN -// Description : Region enable -#define M33_MPU_RLAR_A1_EN_RESET _u(0x0) -#define M33_MPU_RLAR_A1_EN_BITS _u(0x00000001) -#define M33_MPU_RLAR_A1_EN_MSB _u(0) -#define M33_MPU_RLAR_A1_EN_LSB _u(0) -#define M33_MPU_RLAR_A1_EN_ACCESS "RW" -// ============================================================================= -// Register : M33_MPU_RBAR_A2 -// Description : Provides indirect read and write access to the base address of -// the MPU region selected by MPU_RNR[7:2]:(2[1:0]) `FTSSS -#define M33_MPU_RBAR_A2_OFFSET _u(0x0000edac) -#define M33_MPU_RBAR_A2_BITS _u(0xffffffff) -#define M33_MPU_RBAR_A2_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_MPU_RBAR_A2_BASE -// Description : Contains bits [31:5] of the lower inclusive limit of the -// selected MPU memory region. This value is zero extended to -// provide the base address to be checked against -#define M33_MPU_RBAR_A2_BASE_RESET _u(0x0000000) -#define M33_MPU_RBAR_A2_BASE_BITS _u(0xffffffe0) -#define M33_MPU_RBAR_A2_BASE_MSB _u(31) -#define M33_MPU_RBAR_A2_BASE_LSB _u(5) -#define M33_MPU_RBAR_A2_BASE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_MPU_RBAR_A2_SH -// Description : Defines the Shareability domain of this region for Normal -// memory -#define M33_MPU_RBAR_A2_SH_RESET _u(0x0) -#define M33_MPU_RBAR_A2_SH_BITS _u(0x00000018) -#define M33_MPU_RBAR_A2_SH_MSB _u(4) -#define M33_MPU_RBAR_A2_SH_LSB _u(3) -#define M33_MPU_RBAR_A2_SH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_MPU_RBAR_A2_AP -// Description : Defines the access permissions for this region -#define M33_MPU_RBAR_A2_AP_RESET _u(0x0) -#define M33_MPU_RBAR_A2_AP_BITS _u(0x00000006) -#define M33_MPU_RBAR_A2_AP_MSB _u(2) -#define M33_MPU_RBAR_A2_AP_LSB _u(1) -#define M33_MPU_RBAR_A2_AP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_MPU_RBAR_A2_XN -// Description : Defines whether code can be executed from this region -#define M33_MPU_RBAR_A2_XN_RESET _u(0x0) -#define M33_MPU_RBAR_A2_XN_BITS _u(0x00000001) -#define M33_MPU_RBAR_A2_XN_MSB _u(0) -#define M33_MPU_RBAR_A2_XN_LSB _u(0) -#define M33_MPU_RBAR_A2_XN_ACCESS "RW" -// ============================================================================= -// Register : M33_MPU_RLAR_A2 -// Description : Provides indirect read and write access to the limit address of -// the currently selected MPU region selected by -// MPU_RNR[7:2]:(2[1:0]) `FTSSS -#define M33_MPU_RLAR_A2_OFFSET _u(0x0000edb0) -#define M33_MPU_RLAR_A2_BITS _u(0xffffffef) -#define M33_MPU_RLAR_A2_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_MPU_RLAR_A2_LIMIT -// Description : Contains bits [31:5] of the upper inclusive limit of the -// selected MPU memory region. This value is postfixed with 0x1F -// to provide the limit address to be checked against -#define M33_MPU_RLAR_A2_LIMIT_RESET _u(0x0000000) -#define M33_MPU_RLAR_A2_LIMIT_BITS _u(0xffffffe0) -#define M33_MPU_RLAR_A2_LIMIT_MSB _u(31) -#define M33_MPU_RLAR_A2_LIMIT_LSB _u(5) -#define M33_MPU_RLAR_A2_LIMIT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_MPU_RLAR_A2_ATTRINDX -// Description : Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 -// fields -#define M33_MPU_RLAR_A2_ATTRINDX_RESET _u(0x0) -#define M33_MPU_RLAR_A2_ATTRINDX_BITS _u(0x0000000e) -#define M33_MPU_RLAR_A2_ATTRINDX_MSB _u(3) -#define M33_MPU_RLAR_A2_ATTRINDX_LSB _u(1) -#define M33_MPU_RLAR_A2_ATTRINDX_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_MPU_RLAR_A2_EN -// Description : Region enable -#define M33_MPU_RLAR_A2_EN_RESET _u(0x0) -#define M33_MPU_RLAR_A2_EN_BITS _u(0x00000001) -#define M33_MPU_RLAR_A2_EN_MSB _u(0) -#define M33_MPU_RLAR_A2_EN_LSB _u(0) -#define M33_MPU_RLAR_A2_EN_ACCESS "RW" -// ============================================================================= -// Register : M33_MPU_RBAR_A3 -// Description : Provides indirect read and write access to the base address of -// the MPU region selected by MPU_RNR[7:2]:(3[1:0]) `FTSSS -#define M33_MPU_RBAR_A3_OFFSET _u(0x0000edb4) -#define M33_MPU_RBAR_A3_BITS _u(0xffffffff) -#define M33_MPU_RBAR_A3_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_MPU_RBAR_A3_BASE -// Description : Contains bits [31:5] of the lower inclusive limit of the -// selected MPU memory region. This value is zero extended to -// provide the base address to be checked against -#define M33_MPU_RBAR_A3_BASE_RESET _u(0x0000000) -#define M33_MPU_RBAR_A3_BASE_BITS _u(0xffffffe0) -#define M33_MPU_RBAR_A3_BASE_MSB _u(31) -#define M33_MPU_RBAR_A3_BASE_LSB _u(5) -#define M33_MPU_RBAR_A3_BASE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_MPU_RBAR_A3_SH -// Description : Defines the Shareability domain of this region for Normal -// memory -#define M33_MPU_RBAR_A3_SH_RESET _u(0x0) -#define M33_MPU_RBAR_A3_SH_BITS _u(0x00000018) -#define M33_MPU_RBAR_A3_SH_MSB _u(4) -#define M33_MPU_RBAR_A3_SH_LSB _u(3) -#define M33_MPU_RBAR_A3_SH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_MPU_RBAR_A3_AP -// Description : Defines the access permissions for this region -#define M33_MPU_RBAR_A3_AP_RESET _u(0x0) -#define M33_MPU_RBAR_A3_AP_BITS _u(0x00000006) -#define M33_MPU_RBAR_A3_AP_MSB _u(2) -#define M33_MPU_RBAR_A3_AP_LSB _u(1) -#define M33_MPU_RBAR_A3_AP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_MPU_RBAR_A3_XN -// Description : Defines whether code can be executed from this region -#define M33_MPU_RBAR_A3_XN_RESET _u(0x0) -#define M33_MPU_RBAR_A3_XN_BITS _u(0x00000001) -#define M33_MPU_RBAR_A3_XN_MSB _u(0) -#define M33_MPU_RBAR_A3_XN_LSB _u(0) -#define M33_MPU_RBAR_A3_XN_ACCESS "RW" -// ============================================================================= -// Register : M33_MPU_RLAR_A3 -// Description : Provides indirect read and write access to the limit address of -// the currently selected MPU region selected by -// MPU_RNR[7:2]:(3[1:0]) `FTSSS -#define M33_MPU_RLAR_A3_OFFSET _u(0x0000edb8) -#define M33_MPU_RLAR_A3_BITS _u(0xffffffef) -#define M33_MPU_RLAR_A3_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_MPU_RLAR_A3_LIMIT -// Description : Contains bits [31:5] of the upper inclusive limit of the -// selected MPU memory region. This value is postfixed with 0x1F -// to provide the limit address to be checked against -#define M33_MPU_RLAR_A3_LIMIT_RESET _u(0x0000000) -#define M33_MPU_RLAR_A3_LIMIT_BITS _u(0xffffffe0) -#define M33_MPU_RLAR_A3_LIMIT_MSB _u(31) -#define M33_MPU_RLAR_A3_LIMIT_LSB _u(5) -#define M33_MPU_RLAR_A3_LIMIT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_MPU_RLAR_A3_ATTRINDX -// Description : Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 -// fields -#define M33_MPU_RLAR_A3_ATTRINDX_RESET _u(0x0) -#define M33_MPU_RLAR_A3_ATTRINDX_BITS _u(0x0000000e) -#define M33_MPU_RLAR_A3_ATTRINDX_MSB _u(3) -#define M33_MPU_RLAR_A3_ATTRINDX_LSB _u(1) -#define M33_MPU_RLAR_A3_ATTRINDX_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_MPU_RLAR_A3_EN -// Description : Region enable -#define M33_MPU_RLAR_A3_EN_RESET _u(0x0) -#define M33_MPU_RLAR_A3_EN_BITS _u(0x00000001) -#define M33_MPU_RLAR_A3_EN_MSB _u(0) -#define M33_MPU_RLAR_A3_EN_LSB _u(0) -#define M33_MPU_RLAR_A3_EN_ACCESS "RW" -// ============================================================================= -// Register : M33_MPU_MAIR0 -// Description : Along with MPU_MAIR1, provides the memory attribute encodings -// corresponding to the AttrIndex values -#define M33_MPU_MAIR0_OFFSET _u(0x0000edc0) -#define M33_MPU_MAIR0_BITS _u(0xffffffff) -#define M33_MPU_MAIR0_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_MPU_MAIR0_ATTR3 -// Description : Memory attribute encoding for MPU regions with an AttrIndex of -// 3 -#define M33_MPU_MAIR0_ATTR3_RESET _u(0x00) -#define M33_MPU_MAIR0_ATTR3_BITS _u(0xff000000) -#define M33_MPU_MAIR0_ATTR3_MSB _u(31) -#define M33_MPU_MAIR0_ATTR3_LSB _u(24) -#define M33_MPU_MAIR0_ATTR3_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_MPU_MAIR0_ATTR2 -// Description : Memory attribute encoding for MPU regions with an AttrIndex of -// 2 -#define M33_MPU_MAIR0_ATTR2_RESET _u(0x00) -#define M33_MPU_MAIR0_ATTR2_BITS _u(0x00ff0000) -#define M33_MPU_MAIR0_ATTR2_MSB _u(23) -#define M33_MPU_MAIR0_ATTR2_LSB _u(16) -#define M33_MPU_MAIR0_ATTR2_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_MPU_MAIR0_ATTR1 -// Description : Memory attribute encoding for MPU regions with an AttrIndex of -// 1 -#define M33_MPU_MAIR0_ATTR1_RESET _u(0x00) -#define M33_MPU_MAIR0_ATTR1_BITS _u(0x0000ff00) -#define M33_MPU_MAIR0_ATTR1_MSB _u(15) -#define M33_MPU_MAIR0_ATTR1_LSB _u(8) -#define M33_MPU_MAIR0_ATTR1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_MPU_MAIR0_ATTR0 -// Description : Memory attribute encoding for MPU regions with an AttrIndex of -// 0 -#define M33_MPU_MAIR0_ATTR0_RESET _u(0x00) -#define M33_MPU_MAIR0_ATTR0_BITS _u(0x000000ff) -#define M33_MPU_MAIR0_ATTR0_MSB _u(7) -#define M33_MPU_MAIR0_ATTR0_LSB _u(0) -#define M33_MPU_MAIR0_ATTR0_ACCESS "RW" -// ============================================================================= -// Register : M33_MPU_MAIR1 -// Description : Along with MPU_MAIR0, provides the memory attribute encodings -// corresponding to the AttrIndex values -#define M33_MPU_MAIR1_OFFSET _u(0x0000edc4) -#define M33_MPU_MAIR1_BITS _u(0xffffffff) -#define M33_MPU_MAIR1_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_MPU_MAIR1_ATTR7 -// Description : Memory attribute encoding for MPU regions with an AttrIndex of -// 7 -#define M33_MPU_MAIR1_ATTR7_RESET _u(0x00) -#define M33_MPU_MAIR1_ATTR7_BITS _u(0xff000000) -#define M33_MPU_MAIR1_ATTR7_MSB _u(31) -#define M33_MPU_MAIR1_ATTR7_LSB _u(24) -#define M33_MPU_MAIR1_ATTR7_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_MPU_MAIR1_ATTR6 -// Description : Memory attribute encoding for MPU regions with an AttrIndex of -// 6 -#define M33_MPU_MAIR1_ATTR6_RESET _u(0x00) -#define M33_MPU_MAIR1_ATTR6_BITS _u(0x00ff0000) -#define M33_MPU_MAIR1_ATTR6_MSB _u(23) -#define M33_MPU_MAIR1_ATTR6_LSB _u(16) -#define M33_MPU_MAIR1_ATTR6_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_MPU_MAIR1_ATTR5 -// Description : Memory attribute encoding for MPU regions with an AttrIndex of -// 5 -#define M33_MPU_MAIR1_ATTR5_RESET _u(0x00) -#define M33_MPU_MAIR1_ATTR5_BITS _u(0x0000ff00) -#define M33_MPU_MAIR1_ATTR5_MSB _u(15) -#define M33_MPU_MAIR1_ATTR5_LSB _u(8) -#define M33_MPU_MAIR1_ATTR5_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_MPU_MAIR1_ATTR4 -// Description : Memory attribute encoding for MPU regions with an AttrIndex of -// 4 -#define M33_MPU_MAIR1_ATTR4_RESET _u(0x00) -#define M33_MPU_MAIR1_ATTR4_BITS _u(0x000000ff) -#define M33_MPU_MAIR1_ATTR4_MSB _u(7) -#define M33_MPU_MAIR1_ATTR4_LSB _u(0) -#define M33_MPU_MAIR1_ATTR4_ACCESS "RW" -// ============================================================================= -// Register : M33_SAU_CTRL -// Description : Allows enabling of the Security Attribution Unit -#define M33_SAU_CTRL_OFFSET _u(0x0000edd0) -#define M33_SAU_CTRL_BITS _u(0x00000003) -#define M33_SAU_CTRL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_SAU_CTRL_ALLNS -// Description : When SAU_CTRL.ENABLE is 0 this bit controls if the memory is -// marked as Non-secure or Secure -#define M33_SAU_CTRL_ALLNS_RESET _u(0x0) -#define M33_SAU_CTRL_ALLNS_BITS _u(0x00000002) -#define M33_SAU_CTRL_ALLNS_MSB _u(1) -#define M33_SAU_CTRL_ALLNS_LSB _u(1) -#define M33_SAU_CTRL_ALLNS_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_SAU_CTRL_ENABLE -// Description : Enables the SAU -#define M33_SAU_CTRL_ENABLE_RESET _u(0x0) -#define M33_SAU_CTRL_ENABLE_BITS _u(0x00000001) -#define M33_SAU_CTRL_ENABLE_MSB _u(0) -#define M33_SAU_CTRL_ENABLE_LSB _u(0) -#define M33_SAU_CTRL_ENABLE_ACCESS "RW" -// ============================================================================= -// Register : M33_SAU_TYPE -// Description : Indicates the number of regions implemented by the Security -// Attribution Unit -#define M33_SAU_TYPE_OFFSET _u(0x0000edd4) -#define M33_SAU_TYPE_BITS _u(0x000000ff) -#define M33_SAU_TYPE_RESET _u(0x00000008) -// ----------------------------------------------------------------------------- -// Field : M33_SAU_TYPE_SREGION -// Description : The number of implemented SAU regions -#define M33_SAU_TYPE_SREGION_RESET _u(0x08) -#define M33_SAU_TYPE_SREGION_BITS _u(0x000000ff) -#define M33_SAU_TYPE_SREGION_MSB _u(7) -#define M33_SAU_TYPE_SREGION_LSB _u(0) -#define M33_SAU_TYPE_SREGION_ACCESS "RO" -// ============================================================================= -// Register : M33_SAU_RNR -// Description : Selects the region currently accessed by SAU_RBAR and SAU_RLAR -#define M33_SAU_RNR_OFFSET _u(0x0000edd8) -#define M33_SAU_RNR_BITS _u(0x000000ff) -#define M33_SAU_RNR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_SAU_RNR_REGION -// Description : Indicates the SAU region accessed by SAU_RBAR and SAU_RLAR -#define M33_SAU_RNR_REGION_RESET _u(0x00) -#define M33_SAU_RNR_REGION_BITS _u(0x000000ff) -#define M33_SAU_RNR_REGION_MSB _u(7) -#define M33_SAU_RNR_REGION_LSB _u(0) -#define M33_SAU_RNR_REGION_ACCESS "RW" -// ============================================================================= -// Register : M33_SAU_RBAR -// Description : Provides indirect read and write access to the base address of -// the currently selected SAU region -#define M33_SAU_RBAR_OFFSET _u(0x0000eddc) -#define M33_SAU_RBAR_BITS _u(0xffffffe0) -#define M33_SAU_RBAR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_SAU_RBAR_BADDR -// Description : Holds bits [31:5] of the base address for the selected SAU -// region -#define M33_SAU_RBAR_BADDR_RESET _u(0x0000000) -#define M33_SAU_RBAR_BADDR_BITS _u(0xffffffe0) -#define M33_SAU_RBAR_BADDR_MSB _u(31) -#define M33_SAU_RBAR_BADDR_LSB _u(5) -#define M33_SAU_RBAR_BADDR_ACCESS "RW" -// ============================================================================= -// Register : M33_SAU_RLAR -// Description : Provides indirect read and write access to the limit address of -// the currently selected SAU region -#define M33_SAU_RLAR_OFFSET _u(0x0000ede0) -#define M33_SAU_RLAR_BITS _u(0xffffffe3) -#define M33_SAU_RLAR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_SAU_RLAR_LADDR -// Description : Holds bits [31:5] of the limit address for the selected SAU -// region -#define M33_SAU_RLAR_LADDR_RESET _u(0x0000000) -#define M33_SAU_RLAR_LADDR_BITS _u(0xffffffe0) -#define M33_SAU_RLAR_LADDR_MSB _u(31) -#define M33_SAU_RLAR_LADDR_LSB _u(5) -#define M33_SAU_RLAR_LADDR_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_SAU_RLAR_NSC -// Description : Controls whether Non-secure state is permitted to execute an SG -// instruction from this region -#define M33_SAU_RLAR_NSC_RESET _u(0x0) -#define M33_SAU_RLAR_NSC_BITS _u(0x00000002) -#define M33_SAU_RLAR_NSC_MSB _u(1) -#define M33_SAU_RLAR_NSC_LSB _u(1) -#define M33_SAU_RLAR_NSC_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_SAU_RLAR_ENABLE -// Description : SAU region enable -#define M33_SAU_RLAR_ENABLE_RESET _u(0x0) -#define M33_SAU_RLAR_ENABLE_BITS _u(0x00000001) -#define M33_SAU_RLAR_ENABLE_MSB _u(0) -#define M33_SAU_RLAR_ENABLE_LSB _u(0) -#define M33_SAU_RLAR_ENABLE_ACCESS "RW" -// ============================================================================= -// Register : M33_SFSR -// Description : Provides information about any security related faults -#define M33_SFSR_OFFSET _u(0x0000ede4) -#define M33_SFSR_BITS _u(0x000000ff) -#define M33_SFSR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_SFSR_LSERR -// Description : Sticky flag indicating that an error occurred during lazy state -// activation or deactivation -#define M33_SFSR_LSERR_RESET _u(0x0) -#define M33_SFSR_LSERR_BITS _u(0x00000080) -#define M33_SFSR_LSERR_MSB _u(7) -#define M33_SFSR_LSERR_LSB _u(7) -#define M33_SFSR_LSERR_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_SFSR_SFARVALID -// Description : This bit is set when the SFAR register contains a valid value. -// As with similar fields, such as BFSR.BFARVALID and -// MMFSR.MMARVALID, this bit can be cleared by other exceptions, -// such as BusFault -#define M33_SFSR_SFARVALID_RESET _u(0x0) -#define M33_SFSR_SFARVALID_BITS _u(0x00000040) -#define M33_SFSR_SFARVALID_MSB _u(6) -#define M33_SFSR_SFARVALID_LSB _u(6) -#define M33_SFSR_SFARVALID_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_SFSR_LSPERR -// Description : Stick flag indicating that an SAU or IDAU violation occurred -// during the lazy preservation of floating-point state -#define M33_SFSR_LSPERR_RESET _u(0x0) -#define M33_SFSR_LSPERR_BITS _u(0x00000020) -#define M33_SFSR_LSPERR_MSB _u(5) -#define M33_SFSR_LSPERR_LSB _u(5) -#define M33_SFSR_LSPERR_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_SFSR_INVTRAN -// Description : Sticky flag indicating that an exception was raised due to a -// branch that was not flagged as being domain crossing causing a -// transition from Secure to Non-secure memory -#define M33_SFSR_INVTRAN_RESET _u(0x0) -#define M33_SFSR_INVTRAN_BITS _u(0x00000010) -#define M33_SFSR_INVTRAN_MSB _u(4) -#define M33_SFSR_INVTRAN_LSB _u(4) -#define M33_SFSR_INVTRAN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_SFSR_AUVIOL -// Description : Sticky flag indicating that an attempt was made to access parts -// of the address space that are marked as Secure with NS-Req for -// the transaction set to Non-secure. This bit is not set if the -// violation occurred during lazy state preservation. See LSPERR -#define M33_SFSR_AUVIOL_RESET _u(0x0) -#define M33_SFSR_AUVIOL_BITS _u(0x00000008) -#define M33_SFSR_AUVIOL_MSB _u(3) -#define M33_SFSR_AUVIOL_LSB _u(3) -#define M33_SFSR_AUVIOL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_SFSR_INVER -// Description : This can be caused by EXC_RETURN.DCRS being set to 0 when -// returning from an exception in the Non-secure state, or by -// EXC_RETURN.ES being set to 1 when returning from an exception -// in the Non-secure state -#define M33_SFSR_INVER_RESET _u(0x0) -#define M33_SFSR_INVER_BITS _u(0x00000004) -#define M33_SFSR_INVER_MSB _u(2) -#define M33_SFSR_INVER_LSB _u(2) -#define M33_SFSR_INVER_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_SFSR_INVIS -// Description : This bit is set if the integrity signature in an exception -// stack frame is found to be invalid during the unstacking -// operation -#define M33_SFSR_INVIS_RESET _u(0x0) -#define M33_SFSR_INVIS_BITS _u(0x00000002) -#define M33_SFSR_INVIS_MSB _u(1) -#define M33_SFSR_INVIS_LSB _u(1) -#define M33_SFSR_INVIS_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_SFSR_INVEP -// Description : This bit is set if a function call from the Non-secure state or -// exception targets a non-SG instruction in the Secure state. -// This bit is also set if the target address is a SG instruction, -// but there is no matching SAU/IDAU region with the NSC flag set -#define M33_SFSR_INVEP_RESET _u(0x0) -#define M33_SFSR_INVEP_BITS _u(0x00000001) -#define M33_SFSR_INVEP_MSB _u(0) -#define M33_SFSR_INVEP_LSB _u(0) -#define M33_SFSR_INVEP_ACCESS "RW" -// ============================================================================= -// Register : M33_SFAR -// Description : Shows the address of the memory location that caused a Security -// violation -#define M33_SFAR_OFFSET _u(0x0000ede8) -#define M33_SFAR_BITS _u(0xffffffff) -#define M33_SFAR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_SFAR_ADDRESS -// Description : The address of an access that caused a attribution unit -// violation. This field is only valid when SFSR.SFARVALID is set. -// This allows the actual flip flops associated with this register -// to be shared with other fault address registers. If an -// implementation chooses to share the storage in this way, care -// must be taken to not leak Secure address information to the -// Non-secure state. One way of achieving this is to share the -// SFAR register with the MMFAR_S register, which is not -// accessible to the Non-secure state -#define M33_SFAR_ADDRESS_RESET _u(0x00000000) -#define M33_SFAR_ADDRESS_BITS _u(0xffffffff) -#define M33_SFAR_ADDRESS_MSB _u(31) -#define M33_SFAR_ADDRESS_LSB _u(0) -#define M33_SFAR_ADDRESS_ACCESS "RW" -// ============================================================================= -// Register : M33_DHCSR -// Description : Controls halting debug -#define M33_DHCSR_OFFSET _u(0x0000edf0) -#define M33_DHCSR_BITS _u(0x071f002f) -#define M33_DHCSR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_DHCSR_S_RESTART_ST -// Description : Indicates the PE has processed a request to clear DHCSR.C_HALT -// to 0. That is, either a write to DHCSR that clears DHCSR.C_HALT -// from 1 to 0, or an External Restart Request -#define M33_DHCSR_S_RESTART_ST_RESET _u(0x0) -#define M33_DHCSR_S_RESTART_ST_BITS _u(0x04000000) -#define M33_DHCSR_S_RESTART_ST_MSB _u(26) -#define M33_DHCSR_S_RESTART_ST_LSB _u(26) -#define M33_DHCSR_S_RESTART_ST_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_DHCSR_S_RESET_ST -// Description : Indicates whether the PE has been reset since the last read of -// the DHCSR -#define M33_DHCSR_S_RESET_ST_RESET _u(0x0) -#define M33_DHCSR_S_RESET_ST_BITS _u(0x02000000) -#define M33_DHCSR_S_RESET_ST_MSB _u(25) -#define M33_DHCSR_S_RESET_ST_LSB _u(25) -#define M33_DHCSR_S_RESET_ST_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_DHCSR_S_RETIRE_ST -// Description : Set to 1 every time the PE retires one of more instructions -#define M33_DHCSR_S_RETIRE_ST_RESET _u(0x0) -#define M33_DHCSR_S_RETIRE_ST_BITS _u(0x01000000) -#define M33_DHCSR_S_RETIRE_ST_MSB _u(24) -#define M33_DHCSR_S_RETIRE_ST_LSB _u(24) -#define M33_DHCSR_S_RETIRE_ST_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_DHCSR_S_SDE -// Description : Indicates whether Secure invasive debug is allowed -#define M33_DHCSR_S_SDE_RESET _u(0x0) -#define M33_DHCSR_S_SDE_BITS _u(0x00100000) -#define M33_DHCSR_S_SDE_MSB _u(20) -#define M33_DHCSR_S_SDE_LSB _u(20) -#define M33_DHCSR_S_SDE_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_DHCSR_S_LOCKUP -// Description : Indicates whether the PE is in Lockup state -#define M33_DHCSR_S_LOCKUP_RESET _u(0x0) -#define M33_DHCSR_S_LOCKUP_BITS _u(0x00080000) -#define M33_DHCSR_S_LOCKUP_MSB _u(19) -#define M33_DHCSR_S_LOCKUP_LSB _u(19) -#define M33_DHCSR_S_LOCKUP_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_DHCSR_S_SLEEP -// Description : Indicates whether the PE is sleeping -#define M33_DHCSR_S_SLEEP_RESET _u(0x0) -#define M33_DHCSR_S_SLEEP_BITS _u(0x00040000) -#define M33_DHCSR_S_SLEEP_MSB _u(18) -#define M33_DHCSR_S_SLEEP_LSB _u(18) -#define M33_DHCSR_S_SLEEP_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_DHCSR_S_HALT -// Description : Indicates whether the PE is in Debug state -#define M33_DHCSR_S_HALT_RESET _u(0x0) -#define M33_DHCSR_S_HALT_BITS _u(0x00020000) -#define M33_DHCSR_S_HALT_MSB _u(17) -#define M33_DHCSR_S_HALT_LSB _u(17) -#define M33_DHCSR_S_HALT_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_DHCSR_S_REGRDY -// Description : Handshake flag to transfers through the DCRDR -#define M33_DHCSR_S_REGRDY_RESET _u(0x0) -#define M33_DHCSR_S_REGRDY_BITS _u(0x00010000) -#define M33_DHCSR_S_REGRDY_MSB _u(16) -#define M33_DHCSR_S_REGRDY_LSB _u(16) -#define M33_DHCSR_S_REGRDY_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_DHCSR_C_SNAPSTALL -// Description : Allow imprecise entry to Debug state -#define M33_DHCSR_C_SNAPSTALL_RESET _u(0x0) -#define M33_DHCSR_C_SNAPSTALL_BITS _u(0x00000020) -#define M33_DHCSR_C_SNAPSTALL_MSB _u(5) -#define M33_DHCSR_C_SNAPSTALL_LSB _u(5) -#define M33_DHCSR_C_SNAPSTALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_DHCSR_C_MASKINTS -// Description : When debug is enabled, the debugger can write to this bit to -// mask PendSV, SysTick and external configurable interrupts -#define M33_DHCSR_C_MASKINTS_RESET _u(0x0) -#define M33_DHCSR_C_MASKINTS_BITS _u(0x00000008) -#define M33_DHCSR_C_MASKINTS_MSB _u(3) -#define M33_DHCSR_C_MASKINTS_LSB _u(3) -#define M33_DHCSR_C_MASKINTS_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_DHCSR_C_STEP -// Description : Enable single instruction step -#define M33_DHCSR_C_STEP_RESET _u(0x0) -#define M33_DHCSR_C_STEP_BITS _u(0x00000004) -#define M33_DHCSR_C_STEP_MSB _u(2) -#define M33_DHCSR_C_STEP_LSB _u(2) -#define M33_DHCSR_C_STEP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_DHCSR_C_HALT -// Description : PE enter Debug state halt request -#define M33_DHCSR_C_HALT_RESET _u(0x0) -#define M33_DHCSR_C_HALT_BITS _u(0x00000002) -#define M33_DHCSR_C_HALT_MSB _u(1) -#define M33_DHCSR_C_HALT_LSB _u(1) -#define M33_DHCSR_C_HALT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_DHCSR_C_DEBUGEN -// Description : Enable Halting debug -#define M33_DHCSR_C_DEBUGEN_RESET _u(0x0) -#define M33_DHCSR_C_DEBUGEN_BITS _u(0x00000001) -#define M33_DHCSR_C_DEBUGEN_MSB _u(0) -#define M33_DHCSR_C_DEBUGEN_LSB _u(0) -#define M33_DHCSR_C_DEBUGEN_ACCESS "RW" -// ============================================================================= -// Register : M33_DCRSR -// Description : With the DCRDR, provides debug access to the general-purpose -// registers, special-purpose registers, and the FP extension -// registers. A write to the DCRSR specifies the register to -// transfer, whether the transfer is a read or write, and starts -// the transfer -#define M33_DCRSR_OFFSET _u(0x0000edf4) -#define M33_DCRSR_BITS _u(0x0001007f) -#define M33_DCRSR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_DCRSR_REGWNR -// Description : Specifies the access type for the transfer -#define M33_DCRSR_REGWNR_RESET _u(0x0) -#define M33_DCRSR_REGWNR_BITS _u(0x00010000) -#define M33_DCRSR_REGWNR_MSB _u(16) -#define M33_DCRSR_REGWNR_LSB _u(16) -#define M33_DCRSR_REGWNR_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_DCRSR_REGSEL -// Description : Specifies the general-purpose register, special-purpose -// register, or FP register to transfer -#define M33_DCRSR_REGSEL_RESET _u(0x00) -#define M33_DCRSR_REGSEL_BITS _u(0x0000007f) -#define M33_DCRSR_REGSEL_MSB _u(6) -#define M33_DCRSR_REGSEL_LSB _u(0) -#define M33_DCRSR_REGSEL_ACCESS "RW" -// ============================================================================= -// Register : M33_DCRDR -// Description : With the DCRSR, provides debug access to the general-purpose -// registers, special-purpose registers, and the FP Extension -// registers. If the Main Extension is implemented, it can also be -// used for message passing between an external debugger and a -// debug agent running on the PE -#define M33_DCRDR_OFFSET _u(0x0000edf8) -#define M33_DCRDR_BITS _u(0xffffffff) -#define M33_DCRDR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_DCRDR_DBGTMP -// Description : Provides debug access for reading and writing the general- -// purpose registers, special-purpose registers, and Floating- -// point Extension registers -#define M33_DCRDR_DBGTMP_RESET _u(0x00000000) -#define M33_DCRDR_DBGTMP_BITS _u(0xffffffff) -#define M33_DCRDR_DBGTMP_MSB _u(31) -#define M33_DCRDR_DBGTMP_LSB _u(0) -#define M33_DCRDR_DBGTMP_ACCESS "RW" -// ============================================================================= -// Register : M33_DEMCR -// Description : Manages vector catch behavior and DebugMonitor handling when -// debugging -#define M33_DEMCR_OFFSET _u(0x0000edfc) -#define M33_DEMCR_BITS _u(0x011f0ff1) -#define M33_DEMCR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_DEMCR_TRCENA -// Description : Global enable for all DWT and ITM features -#define M33_DEMCR_TRCENA_RESET _u(0x0) -#define M33_DEMCR_TRCENA_BITS _u(0x01000000) -#define M33_DEMCR_TRCENA_MSB _u(24) -#define M33_DEMCR_TRCENA_LSB _u(24) -#define M33_DEMCR_TRCENA_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_DEMCR_SDME -// Description : Indicates whether the DebugMonitor targets the Secure or the -// Non-secure state and whether debug events are allowed in Secure -// state -#define M33_DEMCR_SDME_RESET _u(0x0) -#define M33_DEMCR_SDME_BITS _u(0x00100000) -#define M33_DEMCR_SDME_MSB _u(20) -#define M33_DEMCR_SDME_LSB _u(20) -#define M33_DEMCR_SDME_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_DEMCR_MON_REQ -// Description : DebugMonitor semaphore bit -#define M33_DEMCR_MON_REQ_RESET _u(0x0) -#define M33_DEMCR_MON_REQ_BITS _u(0x00080000) -#define M33_DEMCR_MON_REQ_MSB _u(19) -#define M33_DEMCR_MON_REQ_LSB _u(19) -#define M33_DEMCR_MON_REQ_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_DEMCR_MON_STEP -// Description : Enable DebugMonitor stepping -#define M33_DEMCR_MON_STEP_RESET _u(0x0) -#define M33_DEMCR_MON_STEP_BITS _u(0x00040000) -#define M33_DEMCR_MON_STEP_MSB _u(18) -#define M33_DEMCR_MON_STEP_LSB _u(18) -#define M33_DEMCR_MON_STEP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_DEMCR_MON_PEND -// Description : Sets or clears the pending state of the DebugMonitor exception -#define M33_DEMCR_MON_PEND_RESET _u(0x0) -#define M33_DEMCR_MON_PEND_BITS _u(0x00020000) -#define M33_DEMCR_MON_PEND_MSB _u(17) -#define M33_DEMCR_MON_PEND_LSB _u(17) -#define M33_DEMCR_MON_PEND_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_DEMCR_MON_EN -// Description : Enable the DebugMonitor exception -#define M33_DEMCR_MON_EN_RESET _u(0x0) -#define M33_DEMCR_MON_EN_BITS _u(0x00010000) -#define M33_DEMCR_MON_EN_MSB _u(16) -#define M33_DEMCR_MON_EN_LSB _u(16) -#define M33_DEMCR_MON_EN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_DEMCR_VC_SFERR -// Description : SecureFault exception halting debug vector catch enable -#define M33_DEMCR_VC_SFERR_RESET _u(0x0) -#define M33_DEMCR_VC_SFERR_BITS _u(0x00000800) -#define M33_DEMCR_VC_SFERR_MSB _u(11) -#define M33_DEMCR_VC_SFERR_LSB _u(11) -#define M33_DEMCR_VC_SFERR_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_DEMCR_VC_HARDERR -// Description : HardFault exception halting debug vector catch enable -#define M33_DEMCR_VC_HARDERR_RESET _u(0x0) -#define M33_DEMCR_VC_HARDERR_BITS _u(0x00000400) -#define M33_DEMCR_VC_HARDERR_MSB _u(10) -#define M33_DEMCR_VC_HARDERR_LSB _u(10) -#define M33_DEMCR_VC_HARDERR_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_DEMCR_VC_INTERR -// Description : Enable halting debug vector catch for faults during exception -// entry and return -#define M33_DEMCR_VC_INTERR_RESET _u(0x0) -#define M33_DEMCR_VC_INTERR_BITS _u(0x00000200) -#define M33_DEMCR_VC_INTERR_MSB _u(9) -#define M33_DEMCR_VC_INTERR_LSB _u(9) -#define M33_DEMCR_VC_INTERR_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_DEMCR_VC_BUSERR -// Description : BusFault exception halting debug vector catch enable -#define M33_DEMCR_VC_BUSERR_RESET _u(0x0) -#define M33_DEMCR_VC_BUSERR_BITS _u(0x00000100) -#define M33_DEMCR_VC_BUSERR_MSB _u(8) -#define M33_DEMCR_VC_BUSERR_LSB _u(8) -#define M33_DEMCR_VC_BUSERR_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_DEMCR_VC_STATERR -// Description : Enable halting debug trap on a UsageFault exception caused by a -// state information error, for example an Undefined Instruction -// exception -#define M33_DEMCR_VC_STATERR_RESET _u(0x0) -#define M33_DEMCR_VC_STATERR_BITS _u(0x00000080) -#define M33_DEMCR_VC_STATERR_MSB _u(7) -#define M33_DEMCR_VC_STATERR_LSB _u(7) -#define M33_DEMCR_VC_STATERR_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_DEMCR_VC_CHKERR -// Description : Enable halting debug trap on a UsageFault exception caused by a -// checking error, for example an alignment check error -#define M33_DEMCR_VC_CHKERR_RESET _u(0x0) -#define M33_DEMCR_VC_CHKERR_BITS _u(0x00000040) -#define M33_DEMCR_VC_CHKERR_MSB _u(6) -#define M33_DEMCR_VC_CHKERR_LSB _u(6) -#define M33_DEMCR_VC_CHKERR_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_DEMCR_VC_NOCPERR -// Description : Enable halting debug trap on a UsageFault caused by an access -// to a coprocessor -#define M33_DEMCR_VC_NOCPERR_RESET _u(0x0) -#define M33_DEMCR_VC_NOCPERR_BITS _u(0x00000020) -#define M33_DEMCR_VC_NOCPERR_MSB _u(5) -#define M33_DEMCR_VC_NOCPERR_LSB _u(5) -#define M33_DEMCR_VC_NOCPERR_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_DEMCR_VC_MMERR -// Description : Enable halting debug trap on a MemManage exception -#define M33_DEMCR_VC_MMERR_RESET _u(0x0) -#define M33_DEMCR_VC_MMERR_BITS _u(0x00000010) -#define M33_DEMCR_VC_MMERR_MSB _u(4) -#define M33_DEMCR_VC_MMERR_LSB _u(4) -#define M33_DEMCR_VC_MMERR_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_DEMCR_VC_CORERESET -// Description : Enable Reset Vector Catch. This causes a warm reset to halt a -// running system -#define M33_DEMCR_VC_CORERESET_RESET _u(0x0) -#define M33_DEMCR_VC_CORERESET_BITS _u(0x00000001) -#define M33_DEMCR_VC_CORERESET_MSB _u(0) -#define M33_DEMCR_VC_CORERESET_LSB _u(0) -#define M33_DEMCR_VC_CORERESET_ACCESS "RW" -// ============================================================================= -// Register : M33_DSCSR -// Description : Provides control and status information for Secure debug -#define M33_DSCSR_OFFSET _u(0x0000ee08) -#define M33_DSCSR_BITS _u(0x00030003) -#define M33_DSCSR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_DSCSR_CDSKEY -// Description : Writes to the CDS bit are ignored unless CDSKEY is concurrently -// written to zero -#define M33_DSCSR_CDSKEY_RESET _u(0x0) -#define M33_DSCSR_CDSKEY_BITS _u(0x00020000) -#define M33_DSCSR_CDSKEY_MSB _u(17) -#define M33_DSCSR_CDSKEY_LSB _u(17) -#define M33_DSCSR_CDSKEY_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_DSCSR_CDS -// Description : This field indicates the current Security state of the -// processor -#define M33_DSCSR_CDS_RESET _u(0x0) -#define M33_DSCSR_CDS_BITS _u(0x00010000) -#define M33_DSCSR_CDS_MSB _u(16) -#define M33_DSCSR_CDS_LSB _u(16) -#define M33_DSCSR_CDS_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_DSCSR_SBRSEL -// Description : If SBRSELEN is 1 this bit selects whether the Non-secure or the -// Secure version of the memory-mapped Banked registers are -// accessible to the debugger -#define M33_DSCSR_SBRSEL_RESET _u(0x0) -#define M33_DSCSR_SBRSEL_BITS _u(0x00000002) -#define M33_DSCSR_SBRSEL_MSB _u(1) -#define M33_DSCSR_SBRSEL_LSB _u(1) -#define M33_DSCSR_SBRSEL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_DSCSR_SBRSELEN -// Description : Controls whether the SBRSEL field or the current Security state -// of the processor selects which version of the memory-mapped -// Banked registers are accessed to the debugger -#define M33_DSCSR_SBRSELEN_RESET _u(0x0) -#define M33_DSCSR_SBRSELEN_BITS _u(0x00000001) -#define M33_DSCSR_SBRSELEN_MSB _u(0) -#define M33_DSCSR_SBRSELEN_LSB _u(0) -#define M33_DSCSR_SBRSELEN_ACCESS "RW" -// ============================================================================= -// Register : M33_STIR -// Description : Provides a mechanism for software to generate an interrupt -#define M33_STIR_OFFSET _u(0x0000ef00) -#define M33_STIR_BITS _u(0x000001ff) -#define M33_STIR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_STIR_INTID -// Description : Indicates the interrupt to be pended. The value written is -// (ExceptionNumber - 16) -#define M33_STIR_INTID_RESET _u(0x000) -#define M33_STIR_INTID_BITS _u(0x000001ff) -#define M33_STIR_INTID_MSB _u(8) -#define M33_STIR_INTID_LSB _u(0) -#define M33_STIR_INTID_ACCESS "RW" -// ============================================================================= -// Register : M33_FPCCR -// Description : Holds control data for the Floating-point extension -#define M33_FPCCR_OFFSET _u(0x0000ef34) -#define M33_FPCCR_BITS _u(0xfc0007ff) -#define M33_FPCCR_RESET _u(0x20000472) -// ----------------------------------------------------------------------------- -// Field : M33_FPCCR_ASPEN -// Description : When this bit is set to 1, execution of a floating-point -// instruction sets the CONTROL.FPCA bit to 1 -#define M33_FPCCR_ASPEN_RESET _u(0x0) -#define M33_FPCCR_ASPEN_BITS _u(0x80000000) -#define M33_FPCCR_ASPEN_MSB _u(31) -#define M33_FPCCR_ASPEN_LSB _u(31) -#define M33_FPCCR_ASPEN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_FPCCR_LSPEN -// Description : Enables lazy context save of floating-point state -#define M33_FPCCR_LSPEN_RESET _u(0x0) -#define M33_FPCCR_LSPEN_BITS _u(0x40000000) -#define M33_FPCCR_LSPEN_MSB _u(30) -#define M33_FPCCR_LSPEN_LSB _u(30) -#define M33_FPCCR_LSPEN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_FPCCR_LSPENS -// Description : This bit controls whether the LSPEN bit is writeable from the -// Non-secure state -#define M33_FPCCR_LSPENS_RESET _u(0x1) -#define M33_FPCCR_LSPENS_BITS _u(0x20000000) -#define M33_FPCCR_LSPENS_MSB _u(29) -#define M33_FPCCR_LSPENS_LSB _u(29) -#define M33_FPCCR_LSPENS_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_FPCCR_CLRONRET -// Description : Clear floating-point caller saved registers on exception return -#define M33_FPCCR_CLRONRET_RESET _u(0x0) -#define M33_FPCCR_CLRONRET_BITS _u(0x10000000) -#define M33_FPCCR_CLRONRET_MSB _u(28) -#define M33_FPCCR_CLRONRET_LSB _u(28) -#define M33_FPCCR_CLRONRET_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_FPCCR_CLRONRETS -// Description : This bit controls whether the CLRONRET bit is writeable from -// the Non-secure state -#define M33_FPCCR_CLRONRETS_RESET _u(0x0) -#define M33_FPCCR_CLRONRETS_BITS _u(0x08000000) -#define M33_FPCCR_CLRONRETS_MSB _u(27) -#define M33_FPCCR_CLRONRETS_LSB _u(27) -#define M33_FPCCR_CLRONRETS_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_FPCCR_TS -// Description : Treat floating-point registers as Secure enable -#define M33_FPCCR_TS_RESET _u(0x0) -#define M33_FPCCR_TS_BITS _u(0x04000000) -#define M33_FPCCR_TS_MSB _u(26) -#define M33_FPCCR_TS_LSB _u(26) -#define M33_FPCCR_TS_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_FPCCR_UFRDY -// Description : Indicates whether the software executing when the PE allocated -// the floating-point stack frame was able to set the UsageFault -// exception to pending -#define M33_FPCCR_UFRDY_RESET _u(0x1) -#define M33_FPCCR_UFRDY_BITS _u(0x00000400) -#define M33_FPCCR_UFRDY_MSB _u(10) -#define M33_FPCCR_UFRDY_LSB _u(10) -#define M33_FPCCR_UFRDY_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_FPCCR_SPLIMVIOL -// Description : This bit is banked between the Security states and indicates -// whether the floating-point context violates the stack pointer -// limit that was active when lazy state preservation was -// activated. SPLIMVIOL modifies the lazy floating-point state -// preservation behavior -#define M33_FPCCR_SPLIMVIOL_RESET _u(0x0) -#define M33_FPCCR_SPLIMVIOL_BITS _u(0x00000200) -#define M33_FPCCR_SPLIMVIOL_MSB _u(9) -#define M33_FPCCR_SPLIMVIOL_LSB _u(9) -#define M33_FPCCR_SPLIMVIOL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_FPCCR_MONRDY -// Description : Indicates whether the software executing when the PE allocated -// the floating-point stack frame was able to set the DebugMonitor -// exception to pending -#define M33_FPCCR_MONRDY_RESET _u(0x0) -#define M33_FPCCR_MONRDY_BITS _u(0x00000100) -#define M33_FPCCR_MONRDY_MSB _u(8) -#define M33_FPCCR_MONRDY_LSB _u(8) -#define M33_FPCCR_MONRDY_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_FPCCR_SFRDY -// Description : Indicates whether the software executing when the PE allocated -// the floating-point stack frame was able to set the SecureFault -// exception to pending. This bit is only present in the Secure -// version of the register, and behaves as RAZ/WI when accessed -// from the Non-secure state -#define M33_FPCCR_SFRDY_RESET _u(0x0) -#define M33_FPCCR_SFRDY_BITS _u(0x00000080) -#define M33_FPCCR_SFRDY_MSB _u(7) -#define M33_FPCCR_SFRDY_LSB _u(7) -#define M33_FPCCR_SFRDY_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_FPCCR_BFRDY -// Description : Indicates whether the software executing when the PE allocated -// the floating-point stack frame was able to set the BusFault -// exception to pending -#define M33_FPCCR_BFRDY_RESET _u(0x1) -#define M33_FPCCR_BFRDY_BITS _u(0x00000040) -#define M33_FPCCR_BFRDY_MSB _u(6) -#define M33_FPCCR_BFRDY_LSB _u(6) -#define M33_FPCCR_BFRDY_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_FPCCR_MMRDY -// Description : Indicates whether the software executing when the PE allocated -// the floating-point stack frame was able to set the MemManage -// exception to pending -#define M33_FPCCR_MMRDY_RESET _u(0x1) -#define M33_FPCCR_MMRDY_BITS _u(0x00000020) -#define M33_FPCCR_MMRDY_MSB _u(5) -#define M33_FPCCR_MMRDY_LSB _u(5) -#define M33_FPCCR_MMRDY_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_FPCCR_HFRDY -// Description : Indicates whether the software executing when the PE allocated -// the floating-point stack frame was able to set the HardFault -// exception to pending -#define M33_FPCCR_HFRDY_RESET _u(0x1) -#define M33_FPCCR_HFRDY_BITS _u(0x00000010) -#define M33_FPCCR_HFRDY_MSB _u(4) -#define M33_FPCCR_HFRDY_LSB _u(4) -#define M33_FPCCR_HFRDY_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_FPCCR_THREAD -// Description : Indicates the PE mode when it allocated the floating-point -// stack frame -#define M33_FPCCR_THREAD_RESET _u(0x0) -#define M33_FPCCR_THREAD_BITS _u(0x00000008) -#define M33_FPCCR_THREAD_MSB _u(3) -#define M33_FPCCR_THREAD_LSB _u(3) -#define M33_FPCCR_THREAD_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_FPCCR_S -// Description : Security status of the floating-point context. This bit is only -// present in the Secure version of the register, and behaves as -// RAZ/WI when accessed from the Non-secure state. This bit is -// updated whenever lazy state preservation is activated, or when -// a floating-point instruction is executed -#define M33_FPCCR_S_RESET _u(0x0) -#define M33_FPCCR_S_BITS _u(0x00000004) -#define M33_FPCCR_S_MSB _u(2) -#define M33_FPCCR_S_LSB _u(2) -#define M33_FPCCR_S_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_FPCCR_USER -// Description : Indicates the privilege level of the software executing when -// the PE allocated the floating-point stack frame -#define M33_FPCCR_USER_RESET _u(0x1) -#define M33_FPCCR_USER_BITS _u(0x00000002) -#define M33_FPCCR_USER_MSB _u(1) -#define M33_FPCCR_USER_LSB _u(1) -#define M33_FPCCR_USER_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_FPCCR_LSPACT -// Description : Indicates whether lazy preservation of the floating-point state -// is active -#define M33_FPCCR_LSPACT_RESET _u(0x0) -#define M33_FPCCR_LSPACT_BITS _u(0x00000001) -#define M33_FPCCR_LSPACT_MSB _u(0) -#define M33_FPCCR_LSPACT_LSB _u(0) -#define M33_FPCCR_LSPACT_ACCESS "RW" -// ============================================================================= -// Register : M33_FPCAR -// Description : Holds the location of the unpopulated floating-point register -// space allocated on an exception stack frame -#define M33_FPCAR_OFFSET _u(0x0000ef38) -#define M33_FPCAR_BITS _u(0xfffffff8) -#define M33_FPCAR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_FPCAR_ADDRESS -// Description : The location of the unpopulated floating-point register space -// allocated on an exception stack frame -#define M33_FPCAR_ADDRESS_RESET _u(0x00000000) -#define M33_FPCAR_ADDRESS_BITS _u(0xfffffff8) -#define M33_FPCAR_ADDRESS_MSB _u(31) -#define M33_FPCAR_ADDRESS_LSB _u(3) -#define M33_FPCAR_ADDRESS_ACCESS "RW" -// ============================================================================= -// Register : M33_FPDSCR -// Description : Holds the default values for the floating-point status control -// data that the PE assigns to the FPSCR when it creates a new -// floating-point context -#define M33_FPDSCR_OFFSET _u(0x0000ef3c) -#define M33_FPDSCR_BITS _u(0x07c00000) -#define M33_FPDSCR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_FPDSCR_AHP -// Description : Default value for FPSCR.AHP -#define M33_FPDSCR_AHP_RESET _u(0x0) -#define M33_FPDSCR_AHP_BITS _u(0x04000000) -#define M33_FPDSCR_AHP_MSB _u(26) -#define M33_FPDSCR_AHP_LSB _u(26) -#define M33_FPDSCR_AHP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_FPDSCR_DN -// Description : Default value for FPSCR.DN -#define M33_FPDSCR_DN_RESET _u(0x0) -#define M33_FPDSCR_DN_BITS _u(0x02000000) -#define M33_FPDSCR_DN_MSB _u(25) -#define M33_FPDSCR_DN_LSB _u(25) -#define M33_FPDSCR_DN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_FPDSCR_FZ -// Description : Default value for FPSCR.FZ -#define M33_FPDSCR_FZ_RESET _u(0x0) -#define M33_FPDSCR_FZ_BITS _u(0x01000000) -#define M33_FPDSCR_FZ_MSB _u(24) -#define M33_FPDSCR_FZ_LSB _u(24) -#define M33_FPDSCR_FZ_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_FPDSCR_RMODE -// Description : Default value for FPSCR.RMode -#define M33_FPDSCR_RMODE_RESET _u(0x0) -#define M33_FPDSCR_RMODE_BITS _u(0x00c00000) -#define M33_FPDSCR_RMODE_MSB _u(23) -#define M33_FPDSCR_RMODE_LSB _u(22) -#define M33_FPDSCR_RMODE_ACCESS "RW" -// ============================================================================= -// Register : M33_MVFR0 -// Description : Describes the features provided by the Floating-point Extension -#define M33_MVFR0_OFFSET _u(0x0000ef40) -#define M33_MVFR0_BITS _u(0xf0ff0fff) -#define M33_MVFR0_RESET _u(0x60540601) -// ----------------------------------------------------------------------------- -// Field : M33_MVFR0_FPROUND -// Description : Indicates the rounding modes supported by the FP Extension -#define M33_MVFR0_FPROUND_RESET _u(0x6) -#define M33_MVFR0_FPROUND_BITS _u(0xf0000000) -#define M33_MVFR0_FPROUND_MSB _u(31) -#define M33_MVFR0_FPROUND_LSB _u(28) -#define M33_MVFR0_FPROUND_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_MVFR0_FPSQRT -// Description : Indicates the support for FP square root operations -#define M33_MVFR0_FPSQRT_RESET _u(0x5) -#define M33_MVFR0_FPSQRT_BITS _u(0x00f00000) -#define M33_MVFR0_FPSQRT_MSB _u(23) -#define M33_MVFR0_FPSQRT_LSB _u(20) -#define M33_MVFR0_FPSQRT_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_MVFR0_FPDIVIDE -// Description : Indicates the support for FP divide operations -#define M33_MVFR0_FPDIVIDE_RESET _u(0x4) -#define M33_MVFR0_FPDIVIDE_BITS _u(0x000f0000) -#define M33_MVFR0_FPDIVIDE_MSB _u(19) -#define M33_MVFR0_FPDIVIDE_LSB _u(16) -#define M33_MVFR0_FPDIVIDE_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_MVFR0_FPDP -// Description : Indicates support for FP double-precision operations -#define M33_MVFR0_FPDP_RESET _u(0x6) -#define M33_MVFR0_FPDP_BITS _u(0x00000f00) -#define M33_MVFR0_FPDP_MSB _u(11) -#define M33_MVFR0_FPDP_LSB _u(8) -#define M33_MVFR0_FPDP_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_MVFR0_FPSP -// Description : Indicates support for FP single-precision operations -#define M33_MVFR0_FPSP_RESET _u(0x0) -#define M33_MVFR0_FPSP_BITS _u(0x000000f0) -#define M33_MVFR0_FPSP_MSB _u(7) -#define M33_MVFR0_FPSP_LSB _u(4) -#define M33_MVFR0_FPSP_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_MVFR0_SIMDREG -// Description : Indicates size of FP register file -#define M33_MVFR0_SIMDREG_RESET _u(0x1) -#define M33_MVFR0_SIMDREG_BITS _u(0x0000000f) -#define M33_MVFR0_SIMDREG_MSB _u(3) -#define M33_MVFR0_SIMDREG_LSB _u(0) -#define M33_MVFR0_SIMDREG_ACCESS "RO" -// ============================================================================= -// Register : M33_MVFR1 -// Description : Describes the features provided by the Floating-point Extension -#define M33_MVFR1_OFFSET _u(0x0000ef44) -#define M33_MVFR1_BITS _u(0xff0000ff) -#define M33_MVFR1_RESET _u(0x85000089) -// ----------------------------------------------------------------------------- -// Field : M33_MVFR1_FMAC -// Description : Indicates whether the FP Extension implements the fused -// multiply accumulate instructions -#define M33_MVFR1_FMAC_RESET _u(0x8) -#define M33_MVFR1_FMAC_BITS _u(0xf0000000) -#define M33_MVFR1_FMAC_MSB _u(31) -#define M33_MVFR1_FMAC_LSB _u(28) -#define M33_MVFR1_FMAC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_MVFR1_FPHP -// Description : Indicates whether the FP Extension implements half-precision FP -// conversion instructions -#define M33_MVFR1_FPHP_RESET _u(0x5) -#define M33_MVFR1_FPHP_BITS _u(0x0f000000) -#define M33_MVFR1_FPHP_MSB _u(27) -#define M33_MVFR1_FPHP_LSB _u(24) -#define M33_MVFR1_FPHP_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_MVFR1_FPDNAN -// Description : Indicates whether the FP hardware implementation supports NaN -// propagation -#define M33_MVFR1_FPDNAN_RESET _u(0x8) -#define M33_MVFR1_FPDNAN_BITS _u(0x000000f0) -#define M33_MVFR1_FPDNAN_MSB _u(7) -#define M33_MVFR1_FPDNAN_LSB _u(4) -#define M33_MVFR1_FPDNAN_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_MVFR1_FPFTZ -// Description : Indicates whether subnormals are always flushed-to-zero -#define M33_MVFR1_FPFTZ_RESET _u(0x9) -#define M33_MVFR1_FPFTZ_BITS _u(0x0000000f) -#define M33_MVFR1_FPFTZ_MSB _u(3) -#define M33_MVFR1_FPFTZ_LSB _u(0) -#define M33_MVFR1_FPFTZ_ACCESS "RO" -// ============================================================================= -// Register : M33_MVFR2 -// Description : Describes the features provided by the Floating-point Extension -#define M33_MVFR2_OFFSET _u(0x0000ef48) -#define M33_MVFR2_BITS _u(0x000000f0) -#define M33_MVFR2_RESET _u(0x00000060) -// ----------------------------------------------------------------------------- -// Field : M33_MVFR2_FPMISC -// Description : Indicates support for miscellaneous FP features -#define M33_MVFR2_FPMISC_RESET _u(0x6) -#define M33_MVFR2_FPMISC_BITS _u(0x000000f0) -#define M33_MVFR2_FPMISC_MSB _u(7) -#define M33_MVFR2_FPMISC_LSB _u(4) -#define M33_MVFR2_FPMISC_ACCESS "RO" -// ============================================================================= -// Register : M33_DDEVARCH -// Description : Provides CoreSight discovery information for the SCS -#define M33_DDEVARCH_OFFSET _u(0x0000efbc) -#define M33_DDEVARCH_BITS _u(0xffffffff) -#define M33_DDEVARCH_RESET _u(0x47702a04) -// ----------------------------------------------------------------------------- -// Field : M33_DDEVARCH_ARCHITECT -// Description : Defines the architect of the component. Bits [31:28] are the -// JEP106 continuation code (JEP106 bank ID, minus 1) and bits -// [27:21] are the JEP106 ID code. -#define M33_DDEVARCH_ARCHITECT_RESET _u(0x23b) -#define M33_DDEVARCH_ARCHITECT_BITS _u(0xffe00000) -#define M33_DDEVARCH_ARCHITECT_MSB _u(31) -#define M33_DDEVARCH_ARCHITECT_LSB _u(21) -#define M33_DDEVARCH_ARCHITECT_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_DDEVARCH_PRESENT -// Description : Defines that the DEVARCH register is present -#define M33_DDEVARCH_PRESENT_RESET _u(0x1) -#define M33_DDEVARCH_PRESENT_BITS _u(0x00100000) -#define M33_DDEVARCH_PRESENT_MSB _u(20) -#define M33_DDEVARCH_PRESENT_LSB _u(20) -#define M33_DDEVARCH_PRESENT_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_DDEVARCH_REVISION -// Description : Defines the architecture revision of the component -#define M33_DDEVARCH_REVISION_RESET _u(0x0) -#define M33_DDEVARCH_REVISION_BITS _u(0x000f0000) -#define M33_DDEVARCH_REVISION_MSB _u(19) -#define M33_DDEVARCH_REVISION_LSB _u(16) -#define M33_DDEVARCH_REVISION_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_DDEVARCH_ARCHVER -// Description : Defines the architecture version of the component -#define M33_DDEVARCH_ARCHVER_RESET _u(0x2) -#define M33_DDEVARCH_ARCHVER_BITS _u(0x0000f000) -#define M33_DDEVARCH_ARCHVER_MSB _u(15) -#define M33_DDEVARCH_ARCHVER_LSB _u(12) -#define M33_DDEVARCH_ARCHVER_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_DDEVARCH_ARCHPART -// Description : Defines the architecture of the component -#define M33_DDEVARCH_ARCHPART_RESET _u(0xa04) -#define M33_DDEVARCH_ARCHPART_BITS _u(0x00000fff) -#define M33_DDEVARCH_ARCHPART_MSB _u(11) -#define M33_DDEVARCH_ARCHPART_LSB _u(0) -#define M33_DDEVARCH_ARCHPART_ACCESS "RO" -// ============================================================================= -// Register : M33_DDEVTYPE -// Description : Provides CoreSight discovery information for the SCS -#define M33_DDEVTYPE_OFFSET _u(0x0000efcc) -#define M33_DDEVTYPE_BITS _u(0x000000ff) -#define M33_DDEVTYPE_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_DDEVTYPE_SUB -// Description : Component sub-type -#define M33_DDEVTYPE_SUB_RESET _u(0x0) -#define M33_DDEVTYPE_SUB_BITS _u(0x000000f0) -#define M33_DDEVTYPE_SUB_MSB _u(7) -#define M33_DDEVTYPE_SUB_LSB _u(4) -#define M33_DDEVTYPE_SUB_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_DDEVTYPE_MAJOR -// Description : CoreSight major type -#define M33_DDEVTYPE_MAJOR_RESET _u(0x0) -#define M33_DDEVTYPE_MAJOR_BITS _u(0x0000000f) -#define M33_DDEVTYPE_MAJOR_MSB _u(3) -#define M33_DDEVTYPE_MAJOR_LSB _u(0) -#define M33_DDEVTYPE_MAJOR_ACCESS "RO" -// ============================================================================= -// Register : M33_DPIDR4 -// Description : Provides CoreSight discovery information for the SCS -#define M33_DPIDR4_OFFSET _u(0x0000efd0) -#define M33_DPIDR4_BITS _u(0x000000ff) -#define M33_DPIDR4_RESET _u(0x00000004) -// ----------------------------------------------------------------------------- -// Field : M33_DPIDR4_SIZE -// Description : See CoreSight Architecture Specification -#define M33_DPIDR4_SIZE_RESET _u(0x0) -#define M33_DPIDR4_SIZE_BITS _u(0x000000f0) -#define M33_DPIDR4_SIZE_MSB _u(7) -#define M33_DPIDR4_SIZE_LSB _u(4) -#define M33_DPIDR4_SIZE_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_DPIDR4_DES_2 -// Description : See CoreSight Architecture Specification -#define M33_DPIDR4_DES_2_RESET _u(0x4) -#define M33_DPIDR4_DES_2_BITS _u(0x0000000f) -#define M33_DPIDR4_DES_2_MSB _u(3) -#define M33_DPIDR4_DES_2_LSB _u(0) -#define M33_DPIDR4_DES_2_ACCESS "RO" -// ============================================================================= -// Register : M33_DPIDR5 -// Description : Provides CoreSight discovery information for the SCS -#define M33_DPIDR5_OFFSET _u(0x0000efd4) -#define M33_DPIDR5_BITS _u(0x00000000) -#define M33_DPIDR5_RESET _u(0x00000000) -#define M33_DPIDR5_MSB _u(31) -#define M33_DPIDR5_LSB _u(0) -#define M33_DPIDR5_ACCESS "RW" -// ============================================================================= -// Register : M33_DPIDR6 -// Description : Provides CoreSight discovery information for the SCS -#define M33_DPIDR6_OFFSET _u(0x0000efd8) -#define M33_DPIDR6_BITS _u(0x00000000) -#define M33_DPIDR6_RESET _u(0x00000000) -#define M33_DPIDR6_MSB _u(31) -#define M33_DPIDR6_LSB _u(0) -#define M33_DPIDR6_ACCESS "RW" -// ============================================================================= -// Register : M33_DPIDR7 -// Description : Provides CoreSight discovery information for the SCS -#define M33_DPIDR7_OFFSET _u(0x0000efdc) -#define M33_DPIDR7_BITS _u(0x00000000) -#define M33_DPIDR7_RESET _u(0x00000000) -#define M33_DPIDR7_MSB _u(31) -#define M33_DPIDR7_LSB _u(0) -#define M33_DPIDR7_ACCESS "RW" -// ============================================================================= -// Register : M33_DPIDR0 -// Description : Provides CoreSight discovery information for the SCS -#define M33_DPIDR0_OFFSET _u(0x0000efe0) -#define M33_DPIDR0_BITS _u(0x000000ff) -#define M33_DPIDR0_RESET _u(0x00000021) -// ----------------------------------------------------------------------------- -// Field : M33_DPIDR0_PART_0 -// Description : See CoreSight Architecture Specification -#define M33_DPIDR0_PART_0_RESET _u(0x21) -#define M33_DPIDR0_PART_0_BITS _u(0x000000ff) -#define M33_DPIDR0_PART_0_MSB _u(7) -#define M33_DPIDR0_PART_0_LSB _u(0) -#define M33_DPIDR0_PART_0_ACCESS "RO" -// ============================================================================= -// Register : M33_DPIDR1 -// Description : Provides CoreSight discovery information for the SCS -#define M33_DPIDR1_OFFSET _u(0x0000efe4) -#define M33_DPIDR1_BITS _u(0x000000ff) -#define M33_DPIDR1_RESET _u(0x000000bd) -// ----------------------------------------------------------------------------- -// Field : M33_DPIDR1_DES_0 -// Description : See CoreSight Architecture Specification -#define M33_DPIDR1_DES_0_RESET _u(0xb) -#define M33_DPIDR1_DES_0_BITS _u(0x000000f0) -#define M33_DPIDR1_DES_0_MSB _u(7) -#define M33_DPIDR1_DES_0_LSB _u(4) -#define M33_DPIDR1_DES_0_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_DPIDR1_PART_1 -// Description : See CoreSight Architecture Specification -#define M33_DPIDR1_PART_1_RESET _u(0xd) -#define M33_DPIDR1_PART_1_BITS _u(0x0000000f) -#define M33_DPIDR1_PART_1_MSB _u(3) -#define M33_DPIDR1_PART_1_LSB _u(0) -#define M33_DPIDR1_PART_1_ACCESS "RO" -// ============================================================================= -// Register : M33_DPIDR2 -// Description : Provides CoreSight discovery information for the SCS -#define M33_DPIDR2_OFFSET _u(0x0000efe8) -#define M33_DPIDR2_BITS _u(0x000000ff) -#define M33_DPIDR2_RESET _u(0x0000000b) -// ----------------------------------------------------------------------------- -// Field : M33_DPIDR2_REVISION -// Description : See CoreSight Architecture Specification -#define M33_DPIDR2_REVISION_RESET _u(0x0) -#define M33_DPIDR2_REVISION_BITS _u(0x000000f0) -#define M33_DPIDR2_REVISION_MSB _u(7) -#define M33_DPIDR2_REVISION_LSB _u(4) -#define M33_DPIDR2_REVISION_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_DPIDR2_JEDEC -// Description : See CoreSight Architecture Specification -#define M33_DPIDR2_JEDEC_RESET _u(0x1) -#define M33_DPIDR2_JEDEC_BITS _u(0x00000008) -#define M33_DPIDR2_JEDEC_MSB _u(3) -#define M33_DPIDR2_JEDEC_LSB _u(3) -#define M33_DPIDR2_JEDEC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_DPIDR2_DES_1 -// Description : See CoreSight Architecture Specification -#define M33_DPIDR2_DES_1_RESET _u(0x3) -#define M33_DPIDR2_DES_1_BITS _u(0x00000007) -#define M33_DPIDR2_DES_1_MSB _u(2) -#define M33_DPIDR2_DES_1_LSB _u(0) -#define M33_DPIDR2_DES_1_ACCESS "RO" -// ============================================================================= -// Register : M33_DPIDR3 -// Description : Provides CoreSight discovery information for the SCS -#define M33_DPIDR3_OFFSET _u(0x0000efec) -#define M33_DPIDR3_BITS _u(0x000000ff) -#define M33_DPIDR3_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_DPIDR3_REVAND -// Description : See CoreSight Architecture Specification -#define M33_DPIDR3_REVAND_RESET _u(0x0) -#define M33_DPIDR3_REVAND_BITS _u(0x000000f0) -#define M33_DPIDR3_REVAND_MSB _u(7) -#define M33_DPIDR3_REVAND_LSB _u(4) -#define M33_DPIDR3_REVAND_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_DPIDR3_CMOD -// Description : See CoreSight Architecture Specification -#define M33_DPIDR3_CMOD_RESET _u(0x0) -#define M33_DPIDR3_CMOD_BITS _u(0x0000000f) -#define M33_DPIDR3_CMOD_MSB _u(3) -#define M33_DPIDR3_CMOD_LSB _u(0) -#define M33_DPIDR3_CMOD_ACCESS "RO" -// ============================================================================= -// Register : M33_DCIDR0 -// Description : Provides CoreSight discovery information for the SCS -#define M33_DCIDR0_OFFSET _u(0x0000eff0) -#define M33_DCIDR0_BITS _u(0x000000ff) -#define M33_DCIDR0_RESET _u(0x0000000d) -// ----------------------------------------------------------------------------- -// Field : M33_DCIDR0_PRMBL_0 -// Description : See CoreSight Architecture Specification -#define M33_DCIDR0_PRMBL_0_RESET _u(0x0d) -#define M33_DCIDR0_PRMBL_0_BITS _u(0x000000ff) -#define M33_DCIDR0_PRMBL_0_MSB _u(7) -#define M33_DCIDR0_PRMBL_0_LSB _u(0) -#define M33_DCIDR0_PRMBL_0_ACCESS "RO" -// ============================================================================= -// Register : M33_DCIDR1 -// Description : Provides CoreSight discovery information for the SCS -#define M33_DCIDR1_OFFSET _u(0x0000eff4) -#define M33_DCIDR1_BITS _u(0x000000ff) -#define M33_DCIDR1_RESET _u(0x00000090) -// ----------------------------------------------------------------------------- -// Field : M33_DCIDR1_CLASS -// Description : See CoreSight Architecture Specification -#define M33_DCIDR1_CLASS_RESET _u(0x9) -#define M33_DCIDR1_CLASS_BITS _u(0x000000f0) -#define M33_DCIDR1_CLASS_MSB _u(7) -#define M33_DCIDR1_CLASS_LSB _u(4) -#define M33_DCIDR1_CLASS_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_DCIDR1_PRMBL_1 -// Description : See CoreSight Architecture Specification -#define M33_DCIDR1_PRMBL_1_RESET _u(0x0) -#define M33_DCIDR1_PRMBL_1_BITS _u(0x0000000f) -#define M33_DCIDR1_PRMBL_1_MSB _u(3) -#define M33_DCIDR1_PRMBL_1_LSB _u(0) -#define M33_DCIDR1_PRMBL_1_ACCESS "RO" -// ============================================================================= -// Register : M33_DCIDR2 -// Description : Provides CoreSight discovery information for the SCS -#define M33_DCIDR2_OFFSET _u(0x0000eff8) -#define M33_DCIDR2_BITS _u(0x000000ff) -#define M33_DCIDR2_RESET _u(0x00000005) -// ----------------------------------------------------------------------------- -// Field : M33_DCIDR2_PRMBL_2 -// Description : See CoreSight Architecture Specification -#define M33_DCIDR2_PRMBL_2_RESET _u(0x05) -#define M33_DCIDR2_PRMBL_2_BITS _u(0x000000ff) -#define M33_DCIDR2_PRMBL_2_MSB _u(7) -#define M33_DCIDR2_PRMBL_2_LSB _u(0) -#define M33_DCIDR2_PRMBL_2_ACCESS "RO" -// ============================================================================= -// Register : M33_DCIDR3 -// Description : Provides CoreSight discovery information for the SCS -#define M33_DCIDR3_OFFSET _u(0x0000effc) -#define M33_DCIDR3_BITS _u(0x000000ff) -#define M33_DCIDR3_RESET _u(0x000000b1) -// ----------------------------------------------------------------------------- -// Field : M33_DCIDR3_PRMBL_3 -// Description : See CoreSight Architecture Specification -#define M33_DCIDR3_PRMBL_3_RESET _u(0xb1) -#define M33_DCIDR3_PRMBL_3_BITS _u(0x000000ff) -#define M33_DCIDR3_PRMBL_3_MSB _u(7) -#define M33_DCIDR3_PRMBL_3_LSB _u(0) -#define M33_DCIDR3_PRMBL_3_ACCESS "RO" -// ============================================================================= -// Register : M33_TRCPRGCTLR -// Description : Programming Control Register -#define M33_TRCPRGCTLR_OFFSET _u(0x00041004) -#define M33_TRCPRGCTLR_BITS _u(0x00000001) -#define M33_TRCPRGCTLR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_TRCPRGCTLR_EN -// Description : Trace Unit Enable -#define M33_TRCPRGCTLR_EN_RESET _u(0x0) -#define M33_TRCPRGCTLR_EN_BITS _u(0x00000001) -#define M33_TRCPRGCTLR_EN_MSB _u(0) -#define M33_TRCPRGCTLR_EN_LSB _u(0) -#define M33_TRCPRGCTLR_EN_ACCESS "RW" -// ============================================================================= -// Register : M33_TRCSTATR -// Description : The TRCSTATR indicates the ETM-Teal status -#define M33_TRCSTATR_OFFSET _u(0x0004100c) -#define M33_TRCSTATR_BITS _u(0x00000003) -#define M33_TRCSTATR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_TRCSTATR_PMSTABLE -// Description : Indicates whether the ETM-Teal registers are stable and can be -// read -#define M33_TRCSTATR_PMSTABLE_RESET _u(0x0) -#define M33_TRCSTATR_PMSTABLE_BITS _u(0x00000002) -#define M33_TRCSTATR_PMSTABLE_MSB _u(1) -#define M33_TRCSTATR_PMSTABLE_LSB _u(1) -#define M33_TRCSTATR_PMSTABLE_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_TRCSTATR_IDLE -// Description : Indicates that the trace unit is inactive -#define M33_TRCSTATR_IDLE_RESET _u(0x0) -#define M33_TRCSTATR_IDLE_BITS _u(0x00000001) -#define M33_TRCSTATR_IDLE_MSB _u(0) -#define M33_TRCSTATR_IDLE_LSB _u(0) -#define M33_TRCSTATR_IDLE_ACCESS "RO" -// ============================================================================= -// Register : M33_TRCCONFIGR -// Description : The TRCCONFIGR sets the basic tracing options for the trace -// unit -#define M33_TRCCONFIGR_OFFSET _u(0x00041010) -#define M33_TRCCONFIGR_BITS _u(0x00001ff8) -#define M33_TRCCONFIGR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_TRCCONFIGR_RS -// Description : Return stack enable -#define M33_TRCCONFIGR_RS_RESET _u(0x0) -#define M33_TRCCONFIGR_RS_BITS _u(0x00001000) -#define M33_TRCCONFIGR_RS_MSB _u(12) -#define M33_TRCCONFIGR_RS_LSB _u(12) -#define M33_TRCCONFIGR_RS_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_TRCCONFIGR_TS -// Description : Global timestamp tracing -#define M33_TRCCONFIGR_TS_RESET _u(0x0) -#define M33_TRCCONFIGR_TS_BITS _u(0x00000800) -#define M33_TRCCONFIGR_TS_MSB _u(11) -#define M33_TRCCONFIGR_TS_LSB _u(11) -#define M33_TRCCONFIGR_TS_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_TRCCONFIGR_COND -// Description : Conditional instruction tracing -#define M33_TRCCONFIGR_COND_RESET _u(0x00) -#define M33_TRCCONFIGR_COND_BITS _u(0x000007e0) -#define M33_TRCCONFIGR_COND_MSB _u(10) -#define M33_TRCCONFIGR_COND_LSB _u(5) -#define M33_TRCCONFIGR_COND_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_TRCCONFIGR_CCI -// Description : Cycle counting in instruction trace -#define M33_TRCCONFIGR_CCI_RESET _u(0x0) -#define M33_TRCCONFIGR_CCI_BITS _u(0x00000010) -#define M33_TRCCONFIGR_CCI_MSB _u(4) -#define M33_TRCCONFIGR_CCI_LSB _u(4) -#define M33_TRCCONFIGR_CCI_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_TRCCONFIGR_BB -// Description : Branch broadcast mode -#define M33_TRCCONFIGR_BB_RESET _u(0x0) -#define M33_TRCCONFIGR_BB_BITS _u(0x00000008) -#define M33_TRCCONFIGR_BB_MSB _u(3) -#define M33_TRCCONFIGR_BB_LSB _u(3) -#define M33_TRCCONFIGR_BB_ACCESS "RW" -// ============================================================================= -// Register : M33_TRCEVENTCTL0R -// Description : The TRCEVENTCTL0R controls the tracing of events in the trace -// stream. The events also drive the ETM-Teal external outputs. -#define M33_TRCEVENTCTL0R_OFFSET _u(0x00041020) -#define M33_TRCEVENTCTL0R_BITS _u(0x00008787) -#define M33_TRCEVENTCTL0R_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_TRCEVENTCTL0R_TYPE1 -// Description : Selects the resource type for event 1 -#define M33_TRCEVENTCTL0R_TYPE1_RESET _u(0x0) -#define M33_TRCEVENTCTL0R_TYPE1_BITS _u(0x00008000) -#define M33_TRCEVENTCTL0R_TYPE1_MSB _u(15) -#define M33_TRCEVENTCTL0R_TYPE1_LSB _u(15) -#define M33_TRCEVENTCTL0R_TYPE1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_TRCEVENTCTL0R_SEL1 -// Description : Selects the resource number, based on the value of TYPE1: When -// TYPE1 is 0, selects a single selected resource from 0-15 -// defined by SEL1[2:0]. When TYPE1 is 1, selects a Boolean -// combined resource pair from 0-7 defined by SEL1[2:0] -#define M33_TRCEVENTCTL0R_SEL1_RESET _u(0x0) -#define M33_TRCEVENTCTL0R_SEL1_BITS _u(0x00000700) -#define M33_TRCEVENTCTL0R_SEL1_MSB _u(10) -#define M33_TRCEVENTCTL0R_SEL1_LSB _u(8) -#define M33_TRCEVENTCTL0R_SEL1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_TRCEVENTCTL0R_TYPE0 -// Description : Selects the resource type for event 0 -#define M33_TRCEVENTCTL0R_TYPE0_RESET _u(0x0) -#define M33_TRCEVENTCTL0R_TYPE0_BITS _u(0x00000080) -#define M33_TRCEVENTCTL0R_TYPE0_MSB _u(7) -#define M33_TRCEVENTCTL0R_TYPE0_LSB _u(7) -#define M33_TRCEVENTCTL0R_TYPE0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_TRCEVENTCTL0R_SEL0 -// Description : Selects the resource number, based on the value of TYPE0: When -// TYPE1 is 0, selects a single selected resource from 0-15 -// defined by SEL0[2:0]. When TYPE1 is 1, selects a Boolean -// combined resource pair from 0-7 defined by SEL0[2:0] -#define M33_TRCEVENTCTL0R_SEL0_RESET _u(0x0) -#define M33_TRCEVENTCTL0R_SEL0_BITS _u(0x00000007) -#define M33_TRCEVENTCTL0R_SEL0_MSB _u(2) -#define M33_TRCEVENTCTL0R_SEL0_LSB _u(0) -#define M33_TRCEVENTCTL0R_SEL0_ACCESS "RW" -// ============================================================================= -// Register : M33_TRCEVENTCTL1R -// Description : The TRCEVENTCTL1R controls how the events selected by -// TRCEVENTCTL0R behave -#define M33_TRCEVENTCTL1R_OFFSET _u(0x00041024) -#define M33_TRCEVENTCTL1R_BITS _u(0x00001803) -#define M33_TRCEVENTCTL1R_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_TRCEVENTCTL1R_LPOVERRIDE -// Description : Low power state behavior override -#define M33_TRCEVENTCTL1R_LPOVERRIDE_RESET _u(0x0) -#define M33_TRCEVENTCTL1R_LPOVERRIDE_BITS _u(0x00001000) -#define M33_TRCEVENTCTL1R_LPOVERRIDE_MSB _u(12) -#define M33_TRCEVENTCTL1R_LPOVERRIDE_LSB _u(12) -#define M33_TRCEVENTCTL1R_LPOVERRIDE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_TRCEVENTCTL1R_ATB -// Description : ATB enabled -#define M33_TRCEVENTCTL1R_ATB_RESET _u(0x0) -#define M33_TRCEVENTCTL1R_ATB_BITS _u(0x00000800) -#define M33_TRCEVENTCTL1R_ATB_MSB _u(11) -#define M33_TRCEVENTCTL1R_ATB_LSB _u(11) -#define M33_TRCEVENTCTL1R_ATB_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_TRCEVENTCTL1R_INSTEN1 -// Description : One bit per event, to enable generation of an event element in -// the instruction trace stream when the selected event occurs -#define M33_TRCEVENTCTL1R_INSTEN1_RESET _u(0x0) -#define M33_TRCEVENTCTL1R_INSTEN1_BITS _u(0x00000002) -#define M33_TRCEVENTCTL1R_INSTEN1_MSB _u(1) -#define M33_TRCEVENTCTL1R_INSTEN1_LSB _u(1) -#define M33_TRCEVENTCTL1R_INSTEN1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_TRCEVENTCTL1R_INSTEN0 -// Description : One bit per event, to enable generation of an event element in -// the instruction trace stream when the selected event occurs -#define M33_TRCEVENTCTL1R_INSTEN0_RESET _u(0x0) -#define M33_TRCEVENTCTL1R_INSTEN0_BITS _u(0x00000001) -#define M33_TRCEVENTCTL1R_INSTEN0_MSB _u(0) -#define M33_TRCEVENTCTL1R_INSTEN0_LSB _u(0) -#define M33_TRCEVENTCTL1R_INSTEN0_ACCESS "RW" -// ============================================================================= -// Register : M33_TRCSTALLCTLR -// Description : The TRCSTALLCTLR enables ETM-Teal to stall the processor if the -// ETM-Teal FIFO goes over the programmed level to minimize risk -// of overflow -#define M33_TRCSTALLCTLR_OFFSET _u(0x0004102c) -#define M33_TRCSTALLCTLR_BITS _u(0x0000050c) -#define M33_TRCSTALLCTLR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_TRCSTALLCTLR_INSTPRIORITY -// Description : Reserved, RES0 -#define M33_TRCSTALLCTLR_INSTPRIORITY_RESET _u(0x0) -#define M33_TRCSTALLCTLR_INSTPRIORITY_BITS _u(0x00000400) -#define M33_TRCSTALLCTLR_INSTPRIORITY_MSB _u(10) -#define M33_TRCSTALLCTLR_INSTPRIORITY_LSB _u(10) -#define M33_TRCSTALLCTLR_INSTPRIORITY_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_TRCSTALLCTLR_ISTALL -// Description : Stall processor based on instruction trace buffer space -#define M33_TRCSTALLCTLR_ISTALL_RESET _u(0x0) -#define M33_TRCSTALLCTLR_ISTALL_BITS _u(0x00000100) -#define M33_TRCSTALLCTLR_ISTALL_MSB _u(8) -#define M33_TRCSTALLCTLR_ISTALL_LSB _u(8) -#define M33_TRCSTALLCTLR_ISTALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_TRCSTALLCTLR_LEVEL -// Description : Threshold at which stalling becomes active. This provides four -// levels. This level can be varied to optimize the level of -// invasion caused by stalling, balanced against the risk of a -// FIFO overflow -#define M33_TRCSTALLCTLR_LEVEL_RESET _u(0x0) -#define M33_TRCSTALLCTLR_LEVEL_BITS _u(0x0000000c) -#define M33_TRCSTALLCTLR_LEVEL_MSB _u(3) -#define M33_TRCSTALLCTLR_LEVEL_LSB _u(2) -#define M33_TRCSTALLCTLR_LEVEL_ACCESS "RW" -// ============================================================================= -// Register : M33_TRCTSCTLR -// Description : The TRCTSCTLR controls the insertion of global timestamps into -// the trace stream. A timestamp is always inserted into the -// instruction trace stream -#define M33_TRCTSCTLR_OFFSET _u(0x00041030) -#define M33_TRCTSCTLR_BITS _u(0x00000083) -#define M33_TRCTSCTLR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_TRCTSCTLR_TYPE0 -// Description : Selects the resource type for event 0 -#define M33_TRCTSCTLR_TYPE0_RESET _u(0x0) -#define M33_TRCTSCTLR_TYPE0_BITS _u(0x00000080) -#define M33_TRCTSCTLR_TYPE0_MSB _u(7) -#define M33_TRCTSCTLR_TYPE0_LSB _u(7) -#define M33_TRCTSCTLR_TYPE0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_TRCTSCTLR_SEL0 -// Description : Selects the resource number, based on the value of TYPE0: When -// TYPE1 is 0, selects a single selected resource from 0-15 -// defined by SEL0[2:0]. When TYPE1 is 1, selects a Boolean -// combined resource pair from 0-7 defined by SEL0[2:0] -#define M33_TRCTSCTLR_SEL0_RESET _u(0x0) -#define M33_TRCTSCTLR_SEL0_BITS _u(0x00000003) -#define M33_TRCTSCTLR_SEL0_MSB _u(1) -#define M33_TRCTSCTLR_SEL0_LSB _u(0) -#define M33_TRCTSCTLR_SEL0_ACCESS "RW" -// ============================================================================= -// Register : M33_TRCSYNCPR -// Description : The TRCSYNCPR specifies the period of trace synchronization of -// the trace streams. TRCSYNCPR defines a number of bytes of trace -// between requests for trace synchronization. This value is -// always a power of two -#define M33_TRCSYNCPR_OFFSET _u(0x00041034) -#define M33_TRCSYNCPR_BITS _u(0x0000001f) -#define M33_TRCSYNCPR_RESET _u(0x0000000a) -// ----------------------------------------------------------------------------- -// Field : M33_TRCSYNCPR_PERIOD -// Description : Defines the number of bytes of trace between trace -// synchronization requests as a total of the number of bytes -// generated by the instruction stream. The number of bytes is 2N -// where N is the value of this field: - A value of zero disables -// these periodic trace synchronization requests, but does not -// disable other trace synchronization requests. - The minimum -// value that can be programmed, other than zero, is 8, providing -// a minimum trace synchronization period of 256 bytes. - The -// maximum value is 20, providing a maximum trace synchronization -// period of 2^20 bytes -#define M33_TRCSYNCPR_PERIOD_RESET _u(0x0a) -#define M33_TRCSYNCPR_PERIOD_BITS _u(0x0000001f) -#define M33_TRCSYNCPR_PERIOD_MSB _u(4) -#define M33_TRCSYNCPR_PERIOD_LSB _u(0) -#define M33_TRCSYNCPR_PERIOD_ACCESS "RO" -// ============================================================================= -// Register : M33_TRCCCCTLR -// Description : The TRCCCCTLR sets the threshold value for instruction trace -// cycle counting. The threshold represents the minimum interval -// between cycle count trace packets -#define M33_TRCCCCTLR_OFFSET _u(0x00041038) -#define M33_TRCCCCTLR_BITS _u(0x00000fff) -#define M33_TRCCCCTLR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_TRCCCCTLR_THRESHOLD -// Description : Instruction trace cycle count threshold -#define M33_TRCCCCTLR_THRESHOLD_RESET _u(0x000) -#define M33_TRCCCCTLR_THRESHOLD_BITS _u(0x00000fff) -#define M33_TRCCCCTLR_THRESHOLD_MSB _u(11) -#define M33_TRCCCCTLR_THRESHOLD_LSB _u(0) -#define M33_TRCCCCTLR_THRESHOLD_ACCESS "RW" -// ============================================================================= -// Register : M33_TRCVICTLR -// Description : The TRCVICTLR controls instruction trace filtering -#define M33_TRCVICTLR_OFFSET _u(0x00041080) -#define M33_TRCVICTLR_BITS _u(0x00090e83) -#define M33_TRCVICTLR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_TRCVICTLR_EXLEVEL_S3 -// Description : In Secure state, each bit controls whether instruction tracing -// is enabled for the corresponding exception level -#define M33_TRCVICTLR_EXLEVEL_S3_RESET _u(0x0) -#define M33_TRCVICTLR_EXLEVEL_S3_BITS _u(0x00080000) -#define M33_TRCVICTLR_EXLEVEL_S3_MSB _u(19) -#define M33_TRCVICTLR_EXLEVEL_S3_LSB _u(19) -#define M33_TRCVICTLR_EXLEVEL_S3_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_TRCVICTLR_EXLEVEL_S0 -// Description : In Secure state, each bit controls whether instruction tracing -// is enabled for the corresponding exception level -#define M33_TRCVICTLR_EXLEVEL_S0_RESET _u(0x0) -#define M33_TRCVICTLR_EXLEVEL_S0_BITS _u(0x00010000) -#define M33_TRCVICTLR_EXLEVEL_S0_MSB _u(16) -#define M33_TRCVICTLR_EXLEVEL_S0_LSB _u(16) -#define M33_TRCVICTLR_EXLEVEL_S0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_TRCVICTLR_TRCERR -// Description : Selects whether a system error exception must always be traced -#define M33_TRCVICTLR_TRCERR_RESET _u(0x0) -#define M33_TRCVICTLR_TRCERR_BITS _u(0x00000800) -#define M33_TRCVICTLR_TRCERR_MSB _u(11) -#define M33_TRCVICTLR_TRCERR_LSB _u(11) -#define M33_TRCVICTLR_TRCERR_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_TRCVICTLR_TRCRESET -// Description : Selects whether a reset exception must always be traced -#define M33_TRCVICTLR_TRCRESET_RESET _u(0x0) -#define M33_TRCVICTLR_TRCRESET_BITS _u(0x00000400) -#define M33_TRCVICTLR_TRCRESET_MSB _u(10) -#define M33_TRCVICTLR_TRCRESET_LSB _u(10) -#define M33_TRCVICTLR_TRCRESET_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_TRCVICTLR_SSSTATUS -// Description : Indicates the current status of the start/stop logic -#define M33_TRCVICTLR_SSSTATUS_RESET _u(0x0) -#define M33_TRCVICTLR_SSSTATUS_BITS _u(0x00000200) -#define M33_TRCVICTLR_SSSTATUS_MSB _u(9) -#define M33_TRCVICTLR_SSSTATUS_LSB _u(9) -#define M33_TRCVICTLR_SSSTATUS_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_TRCVICTLR_TYPE0 -// Description : Selects the resource type for event 0 -#define M33_TRCVICTLR_TYPE0_RESET _u(0x0) -#define M33_TRCVICTLR_TYPE0_BITS _u(0x00000080) -#define M33_TRCVICTLR_TYPE0_MSB _u(7) -#define M33_TRCVICTLR_TYPE0_LSB _u(7) -#define M33_TRCVICTLR_TYPE0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_TRCVICTLR_SEL0 -// Description : Selects the resource number, based on the value of TYPE0: When -// TYPE1 is 0, selects a single selected resource from 0-15 -// defined by SEL0[2:0]. When TYPE1 is 1, selects a Boolean -// combined resource pair from 0-7 defined by SEL0[2:0] -#define M33_TRCVICTLR_SEL0_RESET _u(0x0) -#define M33_TRCVICTLR_SEL0_BITS _u(0x00000003) -#define M33_TRCVICTLR_SEL0_MSB _u(1) -#define M33_TRCVICTLR_SEL0_LSB _u(0) -#define M33_TRCVICTLR_SEL0_ACCESS "RW" -// ============================================================================= -// Register : M33_TRCCNTRLDVR0 -// Description : The TRCCNTRLDVR defines the reload value for the reduced -// function counter -#define M33_TRCCNTRLDVR0_OFFSET _u(0x00041140) -#define M33_TRCCNTRLDVR0_BITS _u(0x0000ffff) -#define M33_TRCCNTRLDVR0_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_TRCCNTRLDVR0_VALUE -// Description : Defines the reload value for the counter. This value is loaded -// into the counter each time the reload event occurs -#define M33_TRCCNTRLDVR0_VALUE_RESET _u(0x0000) -#define M33_TRCCNTRLDVR0_VALUE_BITS _u(0x0000ffff) -#define M33_TRCCNTRLDVR0_VALUE_MSB _u(15) -#define M33_TRCCNTRLDVR0_VALUE_LSB _u(0) -#define M33_TRCCNTRLDVR0_VALUE_ACCESS "RW" -// ============================================================================= -// Register : M33_TRCIDR8 -// Description : TRCIDR8 -#define M33_TRCIDR8_OFFSET _u(0x00041180) -#define M33_TRCIDR8_BITS _u(0xffffffff) -#define M33_TRCIDR8_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_TRCIDR8_MAXSPEC -// Description : reads as `ImpDef -#define M33_TRCIDR8_MAXSPEC_RESET _u(0x00000000) -#define M33_TRCIDR8_MAXSPEC_BITS _u(0xffffffff) -#define M33_TRCIDR8_MAXSPEC_MSB _u(31) -#define M33_TRCIDR8_MAXSPEC_LSB _u(0) -#define M33_TRCIDR8_MAXSPEC_ACCESS "RO" -// ============================================================================= -// Register : M33_TRCIDR9 -// Description : TRCIDR9 -#define M33_TRCIDR9_OFFSET _u(0x00041184) -#define M33_TRCIDR9_BITS _u(0xffffffff) -#define M33_TRCIDR9_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_TRCIDR9_NUMP0KEY -// Description : reads as `ImpDef -#define M33_TRCIDR9_NUMP0KEY_RESET _u(0x00000000) -#define M33_TRCIDR9_NUMP0KEY_BITS _u(0xffffffff) -#define M33_TRCIDR9_NUMP0KEY_MSB _u(31) -#define M33_TRCIDR9_NUMP0KEY_LSB _u(0) -#define M33_TRCIDR9_NUMP0KEY_ACCESS "RO" -// ============================================================================= -// Register : M33_TRCIDR10 -// Description : TRCIDR10 -#define M33_TRCIDR10_OFFSET _u(0x00041188) -#define M33_TRCIDR10_BITS _u(0xffffffff) -#define M33_TRCIDR10_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_TRCIDR10_NUMP1KEY -// Description : reads as `ImpDef -#define M33_TRCIDR10_NUMP1KEY_RESET _u(0x00000000) -#define M33_TRCIDR10_NUMP1KEY_BITS _u(0xffffffff) -#define M33_TRCIDR10_NUMP1KEY_MSB _u(31) -#define M33_TRCIDR10_NUMP1KEY_LSB _u(0) -#define M33_TRCIDR10_NUMP1KEY_ACCESS "RO" -// ============================================================================= -// Register : M33_TRCIDR11 -// Description : TRCIDR11 -#define M33_TRCIDR11_OFFSET _u(0x0004118c) -#define M33_TRCIDR11_BITS _u(0xffffffff) -#define M33_TRCIDR11_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_TRCIDR11_NUMP1SPC -// Description : reads as `ImpDef -#define M33_TRCIDR11_NUMP1SPC_RESET _u(0x00000000) -#define M33_TRCIDR11_NUMP1SPC_BITS _u(0xffffffff) -#define M33_TRCIDR11_NUMP1SPC_MSB _u(31) -#define M33_TRCIDR11_NUMP1SPC_LSB _u(0) -#define M33_TRCIDR11_NUMP1SPC_ACCESS "RO" -// ============================================================================= -// Register : M33_TRCIDR12 -// Description : TRCIDR12 -#define M33_TRCIDR12_OFFSET _u(0x00041190) -#define M33_TRCIDR12_BITS _u(0xffffffff) -#define M33_TRCIDR12_RESET _u(0x00000001) -// ----------------------------------------------------------------------------- -// Field : M33_TRCIDR12_NUMCONDKEY -// Description : reads as `ImpDef -#define M33_TRCIDR12_NUMCONDKEY_RESET _u(0x00000001) -#define M33_TRCIDR12_NUMCONDKEY_BITS _u(0xffffffff) -#define M33_TRCIDR12_NUMCONDKEY_MSB _u(31) -#define M33_TRCIDR12_NUMCONDKEY_LSB _u(0) -#define M33_TRCIDR12_NUMCONDKEY_ACCESS "RO" -// ============================================================================= -// Register : M33_TRCIDR13 -// Description : TRCIDR13 -#define M33_TRCIDR13_OFFSET _u(0x00041194) -#define M33_TRCIDR13_BITS _u(0xffffffff) -#define M33_TRCIDR13_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_TRCIDR13_NUMCONDSPC -// Description : reads as `ImpDef -#define M33_TRCIDR13_NUMCONDSPC_RESET _u(0x00000000) -#define M33_TRCIDR13_NUMCONDSPC_BITS _u(0xffffffff) -#define M33_TRCIDR13_NUMCONDSPC_MSB _u(31) -#define M33_TRCIDR13_NUMCONDSPC_LSB _u(0) -#define M33_TRCIDR13_NUMCONDSPC_ACCESS "RO" -// ============================================================================= -// Register : M33_TRCIMSPEC -// Description : The TRCIMSPEC shows the presence of any IMPLEMENTATION SPECIFIC -// features, and enables any features that are provided -#define M33_TRCIMSPEC_OFFSET _u(0x000411c0) -#define M33_TRCIMSPEC_BITS _u(0x0000000f) -#define M33_TRCIMSPEC_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_TRCIMSPEC_SUPPORT -// Description : Reserved, RES0 -#define M33_TRCIMSPEC_SUPPORT_RESET _u(0x0) -#define M33_TRCIMSPEC_SUPPORT_BITS _u(0x0000000f) -#define M33_TRCIMSPEC_SUPPORT_MSB _u(3) -#define M33_TRCIMSPEC_SUPPORT_LSB _u(0) -#define M33_TRCIMSPEC_SUPPORT_ACCESS "RO" -// ============================================================================= -// Register : M33_TRCIDR0 -// Description : TRCIDR0 -#define M33_TRCIDR0_OFFSET _u(0x000411e0) -#define M33_TRCIDR0_BITS _u(0x3f03feff) -#define M33_TRCIDR0_RESET _u(0x280006e1) -// ----------------------------------------------------------------------------- -// Field : M33_TRCIDR0_COMMOPT -// Description : reads as `ImpDef -#define M33_TRCIDR0_COMMOPT_RESET _u(0x1) -#define M33_TRCIDR0_COMMOPT_BITS _u(0x20000000) -#define M33_TRCIDR0_COMMOPT_MSB _u(29) -#define M33_TRCIDR0_COMMOPT_LSB _u(29) -#define M33_TRCIDR0_COMMOPT_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_TRCIDR0_TSSIZE -// Description : reads as `ImpDef -#define M33_TRCIDR0_TSSIZE_RESET _u(0x08) -#define M33_TRCIDR0_TSSIZE_BITS _u(0x1f000000) -#define M33_TRCIDR0_TSSIZE_MSB _u(28) -#define M33_TRCIDR0_TSSIZE_LSB _u(24) -#define M33_TRCIDR0_TSSIZE_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_TRCIDR0_TRCEXDATA -// Description : reads as `ImpDef -#define M33_TRCIDR0_TRCEXDATA_RESET _u(0x0) -#define M33_TRCIDR0_TRCEXDATA_BITS _u(0x00020000) -#define M33_TRCIDR0_TRCEXDATA_MSB _u(17) -#define M33_TRCIDR0_TRCEXDATA_LSB _u(17) -#define M33_TRCIDR0_TRCEXDATA_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_TRCIDR0_QSUPP -// Description : reads as `ImpDef -#define M33_TRCIDR0_QSUPP_RESET _u(0x0) -#define M33_TRCIDR0_QSUPP_BITS _u(0x00018000) -#define M33_TRCIDR0_QSUPP_MSB _u(16) -#define M33_TRCIDR0_QSUPP_LSB _u(15) -#define M33_TRCIDR0_QSUPP_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_TRCIDR0_QFILT -// Description : reads as `ImpDef -#define M33_TRCIDR0_QFILT_RESET _u(0x0) -#define M33_TRCIDR0_QFILT_BITS _u(0x00004000) -#define M33_TRCIDR0_QFILT_MSB _u(14) -#define M33_TRCIDR0_QFILT_LSB _u(14) -#define M33_TRCIDR0_QFILT_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_TRCIDR0_CONDTYPE -// Description : reads as `ImpDef -#define M33_TRCIDR0_CONDTYPE_RESET _u(0x0) -#define M33_TRCIDR0_CONDTYPE_BITS _u(0x00003000) -#define M33_TRCIDR0_CONDTYPE_MSB _u(13) -#define M33_TRCIDR0_CONDTYPE_LSB _u(12) -#define M33_TRCIDR0_CONDTYPE_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_TRCIDR0_NUMEVENT -// Description : reads as `ImpDef -#define M33_TRCIDR0_NUMEVENT_RESET _u(0x1) -#define M33_TRCIDR0_NUMEVENT_BITS _u(0x00000c00) -#define M33_TRCIDR0_NUMEVENT_MSB _u(11) -#define M33_TRCIDR0_NUMEVENT_LSB _u(10) -#define M33_TRCIDR0_NUMEVENT_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_TRCIDR0_RETSTACK -// Description : reads as `ImpDef -#define M33_TRCIDR0_RETSTACK_RESET _u(0x1) -#define M33_TRCIDR0_RETSTACK_BITS _u(0x00000200) -#define M33_TRCIDR0_RETSTACK_MSB _u(9) -#define M33_TRCIDR0_RETSTACK_LSB _u(9) -#define M33_TRCIDR0_RETSTACK_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_TRCIDR0_TRCCCI -// Description : reads as `ImpDef -#define M33_TRCIDR0_TRCCCI_RESET _u(0x1) -#define M33_TRCIDR0_TRCCCI_BITS _u(0x00000080) -#define M33_TRCIDR0_TRCCCI_MSB _u(7) -#define M33_TRCIDR0_TRCCCI_LSB _u(7) -#define M33_TRCIDR0_TRCCCI_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_TRCIDR0_TRCCOND -// Description : reads as `ImpDef -#define M33_TRCIDR0_TRCCOND_RESET _u(0x1) -#define M33_TRCIDR0_TRCCOND_BITS _u(0x00000040) -#define M33_TRCIDR0_TRCCOND_MSB _u(6) -#define M33_TRCIDR0_TRCCOND_LSB _u(6) -#define M33_TRCIDR0_TRCCOND_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_TRCIDR0_TRCBB -// Description : reads as `ImpDef -#define M33_TRCIDR0_TRCBB_RESET _u(0x1) -#define M33_TRCIDR0_TRCBB_BITS _u(0x00000020) -#define M33_TRCIDR0_TRCBB_MSB _u(5) -#define M33_TRCIDR0_TRCBB_LSB _u(5) -#define M33_TRCIDR0_TRCBB_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_TRCIDR0_TRCDATA -// Description : reads as `ImpDef -#define M33_TRCIDR0_TRCDATA_RESET _u(0x0) -#define M33_TRCIDR0_TRCDATA_BITS _u(0x00000018) -#define M33_TRCIDR0_TRCDATA_MSB _u(4) -#define M33_TRCIDR0_TRCDATA_LSB _u(3) -#define M33_TRCIDR0_TRCDATA_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_TRCIDR0_INSTP0 -// Description : reads as `ImpDef -#define M33_TRCIDR0_INSTP0_RESET _u(0x0) -#define M33_TRCIDR0_INSTP0_BITS _u(0x00000006) -#define M33_TRCIDR0_INSTP0_MSB _u(2) -#define M33_TRCIDR0_INSTP0_LSB _u(1) -#define M33_TRCIDR0_INSTP0_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_TRCIDR0_RES1 -// Description : Reserved, RES1 -#define M33_TRCIDR0_RES1_RESET _u(0x1) -#define M33_TRCIDR0_RES1_BITS _u(0x00000001) -#define M33_TRCIDR0_RES1_MSB _u(0) -#define M33_TRCIDR0_RES1_LSB _u(0) -#define M33_TRCIDR0_RES1_ACCESS "RO" -// ============================================================================= -// Register : M33_TRCIDR1 -// Description : TRCIDR1 -#define M33_TRCIDR1_OFFSET _u(0x000411e4) -#define M33_TRCIDR1_BITS _u(0xff00ffff) -#define M33_TRCIDR1_RESET _u(0x4100f421) -// ----------------------------------------------------------------------------- -// Field : M33_TRCIDR1_DESIGNER -// Description : reads as `ImpDef -#define M33_TRCIDR1_DESIGNER_RESET _u(0x41) -#define M33_TRCIDR1_DESIGNER_BITS _u(0xff000000) -#define M33_TRCIDR1_DESIGNER_MSB _u(31) -#define M33_TRCIDR1_DESIGNER_LSB _u(24) -#define M33_TRCIDR1_DESIGNER_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_TRCIDR1_RES1 -// Description : Reserved, RES1 -#define M33_TRCIDR1_RES1_RESET _u(0xf) -#define M33_TRCIDR1_RES1_BITS _u(0x0000f000) -#define M33_TRCIDR1_RES1_MSB _u(15) -#define M33_TRCIDR1_RES1_LSB _u(12) -#define M33_TRCIDR1_RES1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_TRCIDR1_TRCARCHMAJ -// Description : reads as 0b0100 -#define M33_TRCIDR1_TRCARCHMAJ_RESET _u(0x4) -#define M33_TRCIDR1_TRCARCHMAJ_BITS _u(0x00000f00) -#define M33_TRCIDR1_TRCARCHMAJ_MSB _u(11) -#define M33_TRCIDR1_TRCARCHMAJ_LSB _u(8) -#define M33_TRCIDR1_TRCARCHMAJ_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_TRCIDR1_TRCARCHMIN -// Description : reads as 0b0000 -#define M33_TRCIDR1_TRCARCHMIN_RESET _u(0x2) -#define M33_TRCIDR1_TRCARCHMIN_BITS _u(0x000000f0) -#define M33_TRCIDR1_TRCARCHMIN_MSB _u(7) -#define M33_TRCIDR1_TRCARCHMIN_LSB _u(4) -#define M33_TRCIDR1_TRCARCHMIN_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_TRCIDR1_REVISION -// Description : reads as `ImpDef -#define M33_TRCIDR1_REVISION_RESET _u(0x1) -#define M33_TRCIDR1_REVISION_BITS _u(0x0000000f) -#define M33_TRCIDR1_REVISION_MSB _u(3) -#define M33_TRCIDR1_REVISION_LSB _u(0) -#define M33_TRCIDR1_REVISION_ACCESS "RO" -// ============================================================================= -// Register : M33_TRCIDR2 -// Description : TRCIDR2 -#define M33_TRCIDR2_OFFSET _u(0x000411e8) -#define M33_TRCIDR2_BITS _u(0x1fffffff) -#define M33_TRCIDR2_RESET _u(0x00000004) -// ----------------------------------------------------------------------------- -// Field : M33_TRCIDR2_CCSIZE -// Description : reads as `ImpDef -#define M33_TRCIDR2_CCSIZE_RESET _u(0x0) -#define M33_TRCIDR2_CCSIZE_BITS _u(0x1e000000) -#define M33_TRCIDR2_CCSIZE_MSB _u(28) -#define M33_TRCIDR2_CCSIZE_LSB _u(25) -#define M33_TRCIDR2_CCSIZE_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_TRCIDR2_DVSIZE -// Description : reads as `ImpDef -#define M33_TRCIDR2_DVSIZE_RESET _u(0x00) -#define M33_TRCIDR2_DVSIZE_BITS _u(0x01f00000) -#define M33_TRCIDR2_DVSIZE_MSB _u(24) -#define M33_TRCIDR2_DVSIZE_LSB _u(20) -#define M33_TRCIDR2_DVSIZE_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_TRCIDR2_DASIZE -// Description : reads as `ImpDef -#define M33_TRCIDR2_DASIZE_RESET _u(0x00) -#define M33_TRCIDR2_DASIZE_BITS _u(0x000f8000) -#define M33_TRCIDR2_DASIZE_MSB _u(19) -#define M33_TRCIDR2_DASIZE_LSB _u(15) -#define M33_TRCIDR2_DASIZE_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_TRCIDR2_VMIDSIZE -// Description : reads as `ImpDef -#define M33_TRCIDR2_VMIDSIZE_RESET _u(0x00) -#define M33_TRCIDR2_VMIDSIZE_BITS _u(0x00007c00) -#define M33_TRCIDR2_VMIDSIZE_MSB _u(14) -#define M33_TRCIDR2_VMIDSIZE_LSB _u(10) -#define M33_TRCIDR2_VMIDSIZE_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_TRCIDR2_CIDSIZE -// Description : reads as `ImpDef -#define M33_TRCIDR2_CIDSIZE_RESET _u(0x00) -#define M33_TRCIDR2_CIDSIZE_BITS _u(0x000003e0) -#define M33_TRCIDR2_CIDSIZE_MSB _u(9) -#define M33_TRCIDR2_CIDSIZE_LSB _u(5) -#define M33_TRCIDR2_CIDSIZE_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_TRCIDR2_IASIZE -// Description : reads as `ImpDef -#define M33_TRCIDR2_IASIZE_RESET _u(0x04) -#define M33_TRCIDR2_IASIZE_BITS _u(0x0000001f) -#define M33_TRCIDR2_IASIZE_MSB _u(4) -#define M33_TRCIDR2_IASIZE_LSB _u(0) -#define M33_TRCIDR2_IASIZE_ACCESS "RO" -// ============================================================================= -// Register : M33_TRCIDR3 -// Description : TRCIDR3 -#define M33_TRCIDR3_OFFSET _u(0x000411ec) -#define M33_TRCIDR3_BITS _u(0xffff0fff) -#define M33_TRCIDR3_RESET _u(0x0f090004) -// ----------------------------------------------------------------------------- -// Field : M33_TRCIDR3_NOOVERFLOW -// Description : reads as `ImpDef -#define M33_TRCIDR3_NOOVERFLOW_RESET _u(0x0) -#define M33_TRCIDR3_NOOVERFLOW_BITS _u(0x80000000) -#define M33_TRCIDR3_NOOVERFLOW_MSB _u(31) -#define M33_TRCIDR3_NOOVERFLOW_LSB _u(31) -#define M33_TRCIDR3_NOOVERFLOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_TRCIDR3_NUMPROC -// Description : reads as `ImpDef -#define M33_TRCIDR3_NUMPROC_RESET _u(0x0) -#define M33_TRCIDR3_NUMPROC_BITS _u(0x70000000) -#define M33_TRCIDR3_NUMPROC_MSB _u(30) -#define M33_TRCIDR3_NUMPROC_LSB _u(28) -#define M33_TRCIDR3_NUMPROC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_TRCIDR3_SYSSTALL -// Description : reads as `ImpDef -#define M33_TRCIDR3_SYSSTALL_RESET _u(0x1) -#define M33_TRCIDR3_SYSSTALL_BITS _u(0x08000000) -#define M33_TRCIDR3_SYSSTALL_MSB _u(27) -#define M33_TRCIDR3_SYSSTALL_LSB _u(27) -#define M33_TRCIDR3_SYSSTALL_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_TRCIDR3_STALLCTL -// Description : reads as `ImpDef -#define M33_TRCIDR3_STALLCTL_RESET _u(0x1) -#define M33_TRCIDR3_STALLCTL_BITS _u(0x04000000) -#define M33_TRCIDR3_STALLCTL_MSB _u(26) -#define M33_TRCIDR3_STALLCTL_LSB _u(26) -#define M33_TRCIDR3_STALLCTL_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_TRCIDR3_SYNCPR -// Description : reads as `ImpDef -#define M33_TRCIDR3_SYNCPR_RESET _u(0x1) -#define M33_TRCIDR3_SYNCPR_BITS _u(0x02000000) -#define M33_TRCIDR3_SYNCPR_MSB _u(25) -#define M33_TRCIDR3_SYNCPR_LSB _u(25) -#define M33_TRCIDR3_SYNCPR_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_TRCIDR3_TRCERR -// Description : reads as `ImpDef -#define M33_TRCIDR3_TRCERR_RESET _u(0x1) -#define M33_TRCIDR3_TRCERR_BITS _u(0x01000000) -#define M33_TRCIDR3_TRCERR_MSB _u(24) -#define M33_TRCIDR3_TRCERR_LSB _u(24) -#define M33_TRCIDR3_TRCERR_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_TRCIDR3_EXLEVEL_NS -// Description : reads as `ImpDef -#define M33_TRCIDR3_EXLEVEL_NS_RESET _u(0x0) -#define M33_TRCIDR3_EXLEVEL_NS_BITS _u(0x00f00000) -#define M33_TRCIDR3_EXLEVEL_NS_MSB _u(23) -#define M33_TRCIDR3_EXLEVEL_NS_LSB _u(20) -#define M33_TRCIDR3_EXLEVEL_NS_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_TRCIDR3_EXLEVEL_S -// Description : reads as `ImpDef -#define M33_TRCIDR3_EXLEVEL_S_RESET _u(0x9) -#define M33_TRCIDR3_EXLEVEL_S_BITS _u(0x000f0000) -#define M33_TRCIDR3_EXLEVEL_S_MSB _u(19) -#define M33_TRCIDR3_EXLEVEL_S_LSB _u(16) -#define M33_TRCIDR3_EXLEVEL_S_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_TRCIDR3_CCITMIN -// Description : reads as `ImpDef -#define M33_TRCIDR3_CCITMIN_RESET _u(0x004) -#define M33_TRCIDR3_CCITMIN_BITS _u(0x00000fff) -#define M33_TRCIDR3_CCITMIN_MSB _u(11) -#define M33_TRCIDR3_CCITMIN_LSB _u(0) -#define M33_TRCIDR3_CCITMIN_ACCESS "RO" -// ============================================================================= -// Register : M33_TRCIDR4 -// Description : TRCIDR4 -#define M33_TRCIDR4_OFFSET _u(0x000411f0) -#define M33_TRCIDR4_BITS _u(0xfffff1ff) -#define M33_TRCIDR4_RESET _u(0x00114000) -// ----------------------------------------------------------------------------- -// Field : M33_TRCIDR4_NUMVMIDC -// Description : reads as `ImpDef -#define M33_TRCIDR4_NUMVMIDC_RESET _u(0x0) -#define M33_TRCIDR4_NUMVMIDC_BITS _u(0xf0000000) -#define M33_TRCIDR4_NUMVMIDC_MSB _u(31) -#define M33_TRCIDR4_NUMVMIDC_LSB _u(28) -#define M33_TRCIDR4_NUMVMIDC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_TRCIDR4_NUMCIDC -// Description : reads as `ImpDef -#define M33_TRCIDR4_NUMCIDC_RESET _u(0x0) -#define M33_TRCIDR4_NUMCIDC_BITS _u(0x0f000000) -#define M33_TRCIDR4_NUMCIDC_MSB _u(27) -#define M33_TRCIDR4_NUMCIDC_LSB _u(24) -#define M33_TRCIDR4_NUMCIDC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_TRCIDR4_NUMSSCC -// Description : reads as `ImpDef -#define M33_TRCIDR4_NUMSSCC_RESET _u(0x1) -#define M33_TRCIDR4_NUMSSCC_BITS _u(0x00f00000) -#define M33_TRCIDR4_NUMSSCC_MSB _u(23) -#define M33_TRCIDR4_NUMSSCC_LSB _u(20) -#define M33_TRCIDR4_NUMSSCC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_TRCIDR4_NUMRSPAIR -// Description : reads as `ImpDef -#define M33_TRCIDR4_NUMRSPAIR_RESET _u(0x1) -#define M33_TRCIDR4_NUMRSPAIR_BITS _u(0x000f0000) -#define M33_TRCIDR4_NUMRSPAIR_MSB _u(19) -#define M33_TRCIDR4_NUMRSPAIR_LSB _u(16) -#define M33_TRCIDR4_NUMRSPAIR_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_TRCIDR4_NUMPC -// Description : reads as `ImpDef -#define M33_TRCIDR4_NUMPC_RESET _u(0x4) -#define M33_TRCIDR4_NUMPC_BITS _u(0x0000f000) -#define M33_TRCIDR4_NUMPC_MSB _u(15) -#define M33_TRCIDR4_NUMPC_LSB _u(12) -#define M33_TRCIDR4_NUMPC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_TRCIDR4_SUPPDAC -// Description : reads as `ImpDef -#define M33_TRCIDR4_SUPPDAC_RESET _u(0x0) -#define M33_TRCIDR4_SUPPDAC_BITS _u(0x00000100) -#define M33_TRCIDR4_SUPPDAC_MSB _u(8) -#define M33_TRCIDR4_SUPPDAC_LSB _u(8) -#define M33_TRCIDR4_SUPPDAC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_TRCIDR4_NUMDVC -// Description : reads as `ImpDef -#define M33_TRCIDR4_NUMDVC_RESET _u(0x0) -#define M33_TRCIDR4_NUMDVC_BITS _u(0x000000f0) -#define M33_TRCIDR4_NUMDVC_MSB _u(7) -#define M33_TRCIDR4_NUMDVC_LSB _u(4) -#define M33_TRCIDR4_NUMDVC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_TRCIDR4_NUMACPAIRS -// Description : reads as `ImpDef -#define M33_TRCIDR4_NUMACPAIRS_RESET _u(0x0) -#define M33_TRCIDR4_NUMACPAIRS_BITS _u(0x0000000f) -#define M33_TRCIDR4_NUMACPAIRS_MSB _u(3) -#define M33_TRCIDR4_NUMACPAIRS_LSB _u(0) -#define M33_TRCIDR4_NUMACPAIRS_ACCESS "RO" -// ============================================================================= -// Register : M33_TRCIDR5 -// Description : TRCIDR5 -#define M33_TRCIDR5_OFFSET _u(0x000411f4) -#define M33_TRCIDR5_BITS _u(0xfeff0fff) -#define M33_TRCIDR5_RESET _u(0x90c70004) -// ----------------------------------------------------------------------------- -// Field : M33_TRCIDR5_REDFUNCNTR -// Description : reads as `ImpDef -#define M33_TRCIDR5_REDFUNCNTR_RESET _u(0x1) -#define M33_TRCIDR5_REDFUNCNTR_BITS _u(0x80000000) -#define M33_TRCIDR5_REDFUNCNTR_MSB _u(31) -#define M33_TRCIDR5_REDFUNCNTR_LSB _u(31) -#define M33_TRCIDR5_REDFUNCNTR_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_TRCIDR5_NUMCNTR -// Description : reads as `ImpDef -#define M33_TRCIDR5_NUMCNTR_RESET _u(0x1) -#define M33_TRCIDR5_NUMCNTR_BITS _u(0x70000000) -#define M33_TRCIDR5_NUMCNTR_MSB _u(30) -#define M33_TRCIDR5_NUMCNTR_LSB _u(28) -#define M33_TRCIDR5_NUMCNTR_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_TRCIDR5_NUMSEQSTATE -// Description : reads as `ImpDef -#define M33_TRCIDR5_NUMSEQSTATE_RESET _u(0x0) -#define M33_TRCIDR5_NUMSEQSTATE_BITS _u(0x0e000000) -#define M33_TRCIDR5_NUMSEQSTATE_MSB _u(27) -#define M33_TRCIDR5_NUMSEQSTATE_LSB _u(25) -#define M33_TRCIDR5_NUMSEQSTATE_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_TRCIDR5_LPOVERRIDE -// Description : reads as `ImpDef -#define M33_TRCIDR5_LPOVERRIDE_RESET _u(0x1) -#define M33_TRCIDR5_LPOVERRIDE_BITS _u(0x00800000) -#define M33_TRCIDR5_LPOVERRIDE_MSB _u(23) -#define M33_TRCIDR5_LPOVERRIDE_LSB _u(23) -#define M33_TRCIDR5_LPOVERRIDE_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_TRCIDR5_ATBTRIG -// Description : reads as `ImpDef -#define M33_TRCIDR5_ATBTRIG_RESET _u(0x1) -#define M33_TRCIDR5_ATBTRIG_BITS _u(0x00400000) -#define M33_TRCIDR5_ATBTRIG_MSB _u(22) -#define M33_TRCIDR5_ATBTRIG_LSB _u(22) -#define M33_TRCIDR5_ATBTRIG_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_TRCIDR5_TRACEIDSIZE -// Description : reads as 0x07 -#define M33_TRCIDR5_TRACEIDSIZE_RESET _u(0x07) -#define M33_TRCIDR5_TRACEIDSIZE_BITS _u(0x003f0000) -#define M33_TRCIDR5_TRACEIDSIZE_MSB _u(21) -#define M33_TRCIDR5_TRACEIDSIZE_LSB _u(16) -#define M33_TRCIDR5_TRACEIDSIZE_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_TRCIDR5_NUMEXTINSEL -// Description : reads as `ImpDef -#define M33_TRCIDR5_NUMEXTINSEL_RESET _u(0x0) -#define M33_TRCIDR5_NUMEXTINSEL_BITS _u(0x00000e00) -#define M33_TRCIDR5_NUMEXTINSEL_MSB _u(11) -#define M33_TRCIDR5_NUMEXTINSEL_LSB _u(9) -#define M33_TRCIDR5_NUMEXTINSEL_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_TRCIDR5_NUMEXTIN -// Description : reads as `ImpDef -#define M33_TRCIDR5_NUMEXTIN_RESET _u(0x004) -#define M33_TRCIDR5_NUMEXTIN_BITS _u(0x000001ff) -#define M33_TRCIDR5_NUMEXTIN_MSB _u(8) -#define M33_TRCIDR5_NUMEXTIN_LSB _u(0) -#define M33_TRCIDR5_NUMEXTIN_ACCESS "RO" -// ============================================================================= -// Register : M33_TRCIDR6 -// Description : TRCIDR6 -#define M33_TRCIDR6_OFFSET _u(0x000411f8) -#define M33_TRCIDR6_BITS _u(0x00000000) -#define M33_TRCIDR6_RESET _u(0x00000000) -#define M33_TRCIDR6_MSB _u(31) -#define M33_TRCIDR6_LSB _u(0) -#define M33_TRCIDR6_ACCESS "RW" -// ============================================================================= -// Register : M33_TRCIDR7 -// Description : TRCIDR7 -#define M33_TRCIDR7_OFFSET _u(0x000411fc) -#define M33_TRCIDR7_BITS _u(0x00000000) -#define M33_TRCIDR7_RESET _u(0x00000000) -#define M33_TRCIDR7_MSB _u(31) -#define M33_TRCIDR7_LSB _u(0) -#define M33_TRCIDR7_ACCESS "RW" -// ============================================================================= -// Register : M33_TRCRSCTLR2 -// Description : The TRCRSCTLR controls the trace resources -#define M33_TRCRSCTLR2_OFFSET _u(0x00041208) -#define M33_TRCRSCTLR2_BITS _u(0x003700ff) -#define M33_TRCRSCTLR2_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_TRCRSCTLR2_PAIRINV -// Description : Inverts the result of a combined pair of resources. This bit -// is only implemented on the lower register for a pair of -// resource selectors -#define M33_TRCRSCTLR2_PAIRINV_RESET _u(0x0) -#define M33_TRCRSCTLR2_PAIRINV_BITS _u(0x00200000) -#define M33_TRCRSCTLR2_PAIRINV_MSB _u(21) -#define M33_TRCRSCTLR2_PAIRINV_LSB _u(21) -#define M33_TRCRSCTLR2_PAIRINV_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_TRCRSCTLR2_INV -// Description : Inverts the selected resources -#define M33_TRCRSCTLR2_INV_RESET _u(0x0) -#define M33_TRCRSCTLR2_INV_BITS _u(0x00100000) -#define M33_TRCRSCTLR2_INV_MSB _u(20) -#define M33_TRCRSCTLR2_INV_LSB _u(20) -#define M33_TRCRSCTLR2_INV_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_TRCRSCTLR2_GROUP -// Description : Selects a group of resource -#define M33_TRCRSCTLR2_GROUP_RESET _u(0x0) -#define M33_TRCRSCTLR2_GROUP_BITS _u(0x00070000) -#define M33_TRCRSCTLR2_GROUP_MSB _u(18) -#define M33_TRCRSCTLR2_GROUP_LSB _u(16) -#define M33_TRCRSCTLR2_GROUP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_TRCRSCTLR2_SELECT -// Description : Selects one or more resources from the wanted group. One bit is -// provided per resource from the group -#define M33_TRCRSCTLR2_SELECT_RESET _u(0x00) -#define M33_TRCRSCTLR2_SELECT_BITS _u(0x000000ff) -#define M33_TRCRSCTLR2_SELECT_MSB _u(7) -#define M33_TRCRSCTLR2_SELECT_LSB _u(0) -#define M33_TRCRSCTLR2_SELECT_ACCESS "RW" -// ============================================================================= -// Register : M33_TRCRSCTLR3 -// Description : The TRCRSCTLR controls the trace resources -#define M33_TRCRSCTLR3_OFFSET _u(0x0004120c) -#define M33_TRCRSCTLR3_BITS _u(0x003700ff) -#define M33_TRCRSCTLR3_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_TRCRSCTLR3_PAIRINV -// Description : Inverts the result of a combined pair of resources. This bit -// is only implemented on the lower register for a pair of -// resource selectors -#define M33_TRCRSCTLR3_PAIRINV_RESET _u(0x0) -#define M33_TRCRSCTLR3_PAIRINV_BITS _u(0x00200000) -#define M33_TRCRSCTLR3_PAIRINV_MSB _u(21) -#define M33_TRCRSCTLR3_PAIRINV_LSB _u(21) -#define M33_TRCRSCTLR3_PAIRINV_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_TRCRSCTLR3_INV -// Description : Inverts the selected resources -#define M33_TRCRSCTLR3_INV_RESET _u(0x0) -#define M33_TRCRSCTLR3_INV_BITS _u(0x00100000) -#define M33_TRCRSCTLR3_INV_MSB _u(20) -#define M33_TRCRSCTLR3_INV_LSB _u(20) -#define M33_TRCRSCTLR3_INV_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_TRCRSCTLR3_GROUP -// Description : Selects a group of resource -#define M33_TRCRSCTLR3_GROUP_RESET _u(0x0) -#define M33_TRCRSCTLR3_GROUP_BITS _u(0x00070000) -#define M33_TRCRSCTLR3_GROUP_MSB _u(18) -#define M33_TRCRSCTLR3_GROUP_LSB _u(16) -#define M33_TRCRSCTLR3_GROUP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_TRCRSCTLR3_SELECT -// Description : Selects one or more resources from the wanted group. One bit is -// provided per resource from the group -#define M33_TRCRSCTLR3_SELECT_RESET _u(0x00) -#define M33_TRCRSCTLR3_SELECT_BITS _u(0x000000ff) -#define M33_TRCRSCTLR3_SELECT_MSB _u(7) -#define M33_TRCRSCTLR3_SELECT_LSB _u(0) -#define M33_TRCRSCTLR3_SELECT_ACCESS "RW" -// ============================================================================= -// Register : M33_TRCSSCSR -// Description : Controls the corresponding single-shot comparator resource -#define M33_TRCSSCSR_OFFSET _u(0x000412a0) -#define M33_TRCSSCSR_BITS _u(0x8000000f) -#define M33_TRCSSCSR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_TRCSSCSR_STATUS -// Description : Single-shot status bit. Indicates if any of the comparators, -// that TRCSSCCRn.SAC or TRCSSCCRn.ARC selects, have matched -#define M33_TRCSSCSR_STATUS_RESET _u(0x0) -#define M33_TRCSSCSR_STATUS_BITS _u(0x80000000) -#define M33_TRCSSCSR_STATUS_MSB _u(31) -#define M33_TRCSSCSR_STATUS_LSB _u(31) -#define M33_TRCSSCSR_STATUS_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_TRCSSCSR_PC -// Description : Reserved, RES1 -#define M33_TRCSSCSR_PC_RESET _u(0x0) -#define M33_TRCSSCSR_PC_BITS _u(0x00000008) -#define M33_TRCSSCSR_PC_MSB _u(3) -#define M33_TRCSSCSR_PC_LSB _u(3) -#define M33_TRCSSCSR_PC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_TRCSSCSR_DV -// Description : Reserved, RES0 -#define M33_TRCSSCSR_DV_RESET _u(0x0) -#define M33_TRCSSCSR_DV_BITS _u(0x00000004) -#define M33_TRCSSCSR_DV_MSB _u(2) -#define M33_TRCSSCSR_DV_LSB _u(2) -#define M33_TRCSSCSR_DV_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_TRCSSCSR_DA -// Description : Reserved, RES0 -#define M33_TRCSSCSR_DA_RESET _u(0x0) -#define M33_TRCSSCSR_DA_BITS _u(0x00000002) -#define M33_TRCSSCSR_DA_MSB _u(1) -#define M33_TRCSSCSR_DA_LSB _u(1) -#define M33_TRCSSCSR_DA_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_TRCSSCSR_INST -// Description : Reserved, RES0 -#define M33_TRCSSCSR_INST_RESET _u(0x0) -#define M33_TRCSSCSR_INST_BITS _u(0x00000001) -#define M33_TRCSSCSR_INST_MSB _u(0) -#define M33_TRCSSCSR_INST_LSB _u(0) -#define M33_TRCSSCSR_INST_ACCESS "RO" -// ============================================================================= -// Register : M33_TRCSSPCICR -// Description : Selects the PE comparator inputs for Single-shot control -#define M33_TRCSSPCICR_OFFSET _u(0x000412c0) -#define M33_TRCSSPCICR_BITS _u(0x0000000f) -#define M33_TRCSSPCICR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_TRCSSPCICR_PC -// Description : Selects one or more PE comparator inputs for Single-shot -// control. TRCIDR4.NUMPC defines the size of the PC field. 1 -// bit is provided for each implemented PE comparator input. For -// example, if bit[1] == 1 this selects PE comparator input 1 for -// Single-shot control -#define M33_TRCSSPCICR_PC_RESET _u(0x0) -#define M33_TRCSSPCICR_PC_BITS _u(0x0000000f) -#define M33_TRCSSPCICR_PC_MSB _u(3) -#define M33_TRCSSPCICR_PC_LSB _u(0) -#define M33_TRCSSPCICR_PC_ACCESS "RW" -// ============================================================================= -// Register : M33_TRCPDCR -// Description : Requests the system to provide power to the trace unit -#define M33_TRCPDCR_OFFSET _u(0x00041310) -#define M33_TRCPDCR_BITS _u(0x00000008) -#define M33_TRCPDCR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_TRCPDCR_PU -// Description : Powerup request bit: -#define M33_TRCPDCR_PU_RESET _u(0x0) -#define M33_TRCPDCR_PU_BITS _u(0x00000008) -#define M33_TRCPDCR_PU_MSB _u(3) -#define M33_TRCPDCR_PU_LSB _u(3) -#define M33_TRCPDCR_PU_ACCESS "RW" -// ============================================================================= -// Register : M33_TRCPDSR -// Description : Returns the following information about the trace unit: - OS -// Lock status. - Core power domain status. - Power interruption -// status -#define M33_TRCPDSR_OFFSET _u(0x00041314) -#define M33_TRCPDSR_BITS _u(0x00000023) -#define M33_TRCPDSR_RESET _u(0x00000003) -// ----------------------------------------------------------------------------- -// Field : M33_TRCPDSR_OSLK -// Description : OS Lock status bit: -#define M33_TRCPDSR_OSLK_RESET _u(0x0) -#define M33_TRCPDSR_OSLK_BITS _u(0x00000020) -#define M33_TRCPDSR_OSLK_MSB _u(5) -#define M33_TRCPDSR_OSLK_LSB _u(5) -#define M33_TRCPDSR_OSLK_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_TRCPDSR_STICKYPD -// Description : Sticky powerdown status bit. Indicates whether the trace -// register state is valid: -#define M33_TRCPDSR_STICKYPD_RESET _u(0x1) -#define M33_TRCPDSR_STICKYPD_BITS _u(0x00000002) -#define M33_TRCPDSR_STICKYPD_MSB _u(1) -#define M33_TRCPDSR_STICKYPD_LSB _u(1) -#define M33_TRCPDSR_STICKYPD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_TRCPDSR_POWER -// Description : Power status bit: -#define M33_TRCPDSR_POWER_RESET _u(0x1) -#define M33_TRCPDSR_POWER_BITS _u(0x00000001) -#define M33_TRCPDSR_POWER_MSB _u(0) -#define M33_TRCPDSR_POWER_LSB _u(0) -#define M33_TRCPDSR_POWER_ACCESS "RO" -// ============================================================================= -// Register : M33_TRCITATBIDR -// Description : Trace Integration ATB Identification Register -#define M33_TRCITATBIDR_OFFSET _u(0x00041ee4) -#define M33_TRCITATBIDR_BITS _u(0x0000007f) -#define M33_TRCITATBIDR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_TRCITATBIDR_ID -// Description : Trace ID -#define M33_TRCITATBIDR_ID_RESET _u(0x00) -#define M33_TRCITATBIDR_ID_BITS _u(0x0000007f) -#define M33_TRCITATBIDR_ID_MSB _u(6) -#define M33_TRCITATBIDR_ID_LSB _u(0) -#define M33_TRCITATBIDR_ID_ACCESS "RW" -// ============================================================================= -// Register : M33_TRCITIATBINR -// Description : Trace Integration Instruction ATB In Register -#define M33_TRCITIATBINR_OFFSET _u(0x00041ef4) -#define M33_TRCITIATBINR_BITS _u(0x00000003) -#define M33_TRCITIATBINR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_TRCITIATBINR_AFVALIDM -// Description : Integration Mode instruction AFVALIDM in -#define M33_TRCITIATBINR_AFVALIDM_RESET _u(0x0) -#define M33_TRCITIATBINR_AFVALIDM_BITS _u(0x00000002) -#define M33_TRCITIATBINR_AFVALIDM_MSB _u(1) -#define M33_TRCITIATBINR_AFVALIDM_LSB _u(1) -#define M33_TRCITIATBINR_AFVALIDM_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_TRCITIATBINR_ATREADYM -// Description : Integration Mode instruction ATREADYM in -#define M33_TRCITIATBINR_ATREADYM_RESET _u(0x0) -#define M33_TRCITIATBINR_ATREADYM_BITS _u(0x00000001) -#define M33_TRCITIATBINR_ATREADYM_MSB _u(0) -#define M33_TRCITIATBINR_ATREADYM_LSB _u(0) -#define M33_TRCITIATBINR_ATREADYM_ACCESS "RW" -// ============================================================================= -// Register : M33_TRCITIATBOUTR -// Description : Trace Integration Instruction ATB Out Register -#define M33_TRCITIATBOUTR_OFFSET _u(0x00041efc) -#define M33_TRCITIATBOUTR_BITS _u(0x00000003) -#define M33_TRCITIATBOUTR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_TRCITIATBOUTR_AFREADY -// Description : Integration Mode instruction AFREADY out -#define M33_TRCITIATBOUTR_AFREADY_RESET _u(0x0) -#define M33_TRCITIATBOUTR_AFREADY_BITS _u(0x00000002) -#define M33_TRCITIATBOUTR_AFREADY_MSB _u(1) -#define M33_TRCITIATBOUTR_AFREADY_LSB _u(1) -#define M33_TRCITIATBOUTR_AFREADY_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_TRCITIATBOUTR_ATVALID -// Description : Integration Mode instruction ATVALID out -#define M33_TRCITIATBOUTR_ATVALID_RESET _u(0x0) -#define M33_TRCITIATBOUTR_ATVALID_BITS _u(0x00000001) -#define M33_TRCITIATBOUTR_ATVALID_MSB _u(0) -#define M33_TRCITIATBOUTR_ATVALID_LSB _u(0) -#define M33_TRCITIATBOUTR_ATVALID_ACCESS "RW" -// ============================================================================= -// Register : M33_TRCCLAIMSET -// Description : Claim Tag Set Register -#define M33_TRCCLAIMSET_OFFSET _u(0x00041fa0) -#define M33_TRCCLAIMSET_BITS _u(0x0000000f) -#define M33_TRCCLAIMSET_RESET _u(0x0000000f) -// ----------------------------------------------------------------------------- -// Field : M33_TRCCLAIMSET_SET3 -// Description : When a write to one of these bits occurs, with the value: -#define M33_TRCCLAIMSET_SET3_RESET _u(0x1) -#define M33_TRCCLAIMSET_SET3_BITS _u(0x00000008) -#define M33_TRCCLAIMSET_SET3_MSB _u(3) -#define M33_TRCCLAIMSET_SET3_LSB _u(3) -#define M33_TRCCLAIMSET_SET3_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_TRCCLAIMSET_SET2 -// Description : When a write to one of these bits occurs, with the value: -#define M33_TRCCLAIMSET_SET2_RESET _u(0x1) -#define M33_TRCCLAIMSET_SET2_BITS _u(0x00000004) -#define M33_TRCCLAIMSET_SET2_MSB _u(2) -#define M33_TRCCLAIMSET_SET2_LSB _u(2) -#define M33_TRCCLAIMSET_SET2_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_TRCCLAIMSET_SET1 -// Description : When a write to one of these bits occurs, with the value: -#define M33_TRCCLAIMSET_SET1_RESET _u(0x1) -#define M33_TRCCLAIMSET_SET1_BITS _u(0x00000002) -#define M33_TRCCLAIMSET_SET1_MSB _u(1) -#define M33_TRCCLAIMSET_SET1_LSB _u(1) -#define M33_TRCCLAIMSET_SET1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_TRCCLAIMSET_SET0 -// Description : When a write to one of these bits occurs, with the value: -#define M33_TRCCLAIMSET_SET0_RESET _u(0x1) -#define M33_TRCCLAIMSET_SET0_BITS _u(0x00000001) -#define M33_TRCCLAIMSET_SET0_MSB _u(0) -#define M33_TRCCLAIMSET_SET0_LSB _u(0) -#define M33_TRCCLAIMSET_SET0_ACCESS "RW" -// ============================================================================= -// Register : M33_TRCCLAIMCLR -// Description : Claim Tag Clear Register -#define M33_TRCCLAIMCLR_OFFSET _u(0x00041fa4) -#define M33_TRCCLAIMCLR_BITS _u(0x0000000f) -#define M33_TRCCLAIMCLR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_TRCCLAIMCLR_CLR3 -// Description : When a write to one of these bits occurs, with the value: -#define M33_TRCCLAIMCLR_CLR3_RESET _u(0x0) -#define M33_TRCCLAIMCLR_CLR3_BITS _u(0x00000008) -#define M33_TRCCLAIMCLR_CLR3_MSB _u(3) -#define M33_TRCCLAIMCLR_CLR3_LSB _u(3) -#define M33_TRCCLAIMCLR_CLR3_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_TRCCLAIMCLR_CLR2 -// Description : When a write to one of these bits occurs, with the value: -#define M33_TRCCLAIMCLR_CLR2_RESET _u(0x0) -#define M33_TRCCLAIMCLR_CLR2_BITS _u(0x00000004) -#define M33_TRCCLAIMCLR_CLR2_MSB _u(2) -#define M33_TRCCLAIMCLR_CLR2_LSB _u(2) -#define M33_TRCCLAIMCLR_CLR2_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_TRCCLAIMCLR_CLR1 -// Description : When a write to one of these bits occurs, with the value: -#define M33_TRCCLAIMCLR_CLR1_RESET _u(0x0) -#define M33_TRCCLAIMCLR_CLR1_BITS _u(0x00000002) -#define M33_TRCCLAIMCLR_CLR1_MSB _u(1) -#define M33_TRCCLAIMCLR_CLR1_LSB _u(1) -#define M33_TRCCLAIMCLR_CLR1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_TRCCLAIMCLR_CLR0 -// Description : When a write to one of these bits occurs, with the value: -#define M33_TRCCLAIMCLR_CLR0_RESET _u(0x0) -#define M33_TRCCLAIMCLR_CLR0_BITS _u(0x00000001) -#define M33_TRCCLAIMCLR_CLR0_MSB _u(0) -#define M33_TRCCLAIMCLR_CLR0_LSB _u(0) -#define M33_TRCCLAIMCLR_CLR0_ACCESS "RW" -// ============================================================================= -// Register : M33_TRCAUTHSTATUS -// Description : Returns the level of tracing that the trace unit can support -#define M33_TRCAUTHSTATUS_OFFSET _u(0x00041fb8) -#define M33_TRCAUTHSTATUS_BITS _u(0x000000ff) -#define M33_TRCAUTHSTATUS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_TRCAUTHSTATUS_SNID -// Description : Indicates whether the system enables the trace unit to support -// Secure non-invasive debug: -#define M33_TRCAUTHSTATUS_SNID_RESET _u(0x0) -#define M33_TRCAUTHSTATUS_SNID_BITS _u(0x000000c0) -#define M33_TRCAUTHSTATUS_SNID_MSB _u(7) -#define M33_TRCAUTHSTATUS_SNID_LSB _u(6) -#define M33_TRCAUTHSTATUS_SNID_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_TRCAUTHSTATUS_SID -// Description : Indicates whether the trace unit supports Secure invasive -// debug: -#define M33_TRCAUTHSTATUS_SID_RESET _u(0x0) -#define M33_TRCAUTHSTATUS_SID_BITS _u(0x00000030) -#define M33_TRCAUTHSTATUS_SID_MSB _u(5) -#define M33_TRCAUTHSTATUS_SID_LSB _u(4) -#define M33_TRCAUTHSTATUS_SID_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_TRCAUTHSTATUS_NSNID -// Description : Indicates whether the system enables the trace unit to support -// Non-secure non-invasive debug: -#define M33_TRCAUTHSTATUS_NSNID_RESET _u(0x0) -#define M33_TRCAUTHSTATUS_NSNID_BITS _u(0x0000000c) -#define M33_TRCAUTHSTATUS_NSNID_MSB _u(3) -#define M33_TRCAUTHSTATUS_NSNID_LSB _u(2) -#define M33_TRCAUTHSTATUS_NSNID_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_TRCAUTHSTATUS_NSID -// Description : Indicates whether the trace unit supports Non-secure invasive -// debug: -#define M33_TRCAUTHSTATUS_NSID_RESET _u(0x0) -#define M33_TRCAUTHSTATUS_NSID_BITS _u(0x00000003) -#define M33_TRCAUTHSTATUS_NSID_MSB _u(1) -#define M33_TRCAUTHSTATUS_NSID_LSB _u(0) -#define M33_TRCAUTHSTATUS_NSID_ACCESS "RO" -// ============================================================================= -// Register : M33_TRCDEVARCH -// Description : TRCDEVARCH -#define M33_TRCDEVARCH_OFFSET _u(0x00041fbc) -#define M33_TRCDEVARCH_BITS _u(0xffffffff) -#define M33_TRCDEVARCH_RESET _u(0x47724a13) -// ----------------------------------------------------------------------------- -// Field : M33_TRCDEVARCH_ARCHITECT -// Description : reads as 0b01000111011 -#define M33_TRCDEVARCH_ARCHITECT_RESET _u(0x23b) -#define M33_TRCDEVARCH_ARCHITECT_BITS _u(0xffe00000) -#define M33_TRCDEVARCH_ARCHITECT_MSB _u(31) -#define M33_TRCDEVARCH_ARCHITECT_LSB _u(21) -#define M33_TRCDEVARCH_ARCHITECT_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_TRCDEVARCH_PRESENT -// Description : reads as 0b1 -#define M33_TRCDEVARCH_PRESENT_RESET _u(0x1) -#define M33_TRCDEVARCH_PRESENT_BITS _u(0x00100000) -#define M33_TRCDEVARCH_PRESENT_MSB _u(20) -#define M33_TRCDEVARCH_PRESENT_LSB _u(20) -#define M33_TRCDEVARCH_PRESENT_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_TRCDEVARCH_REVISION -// Description : reads as 0b0000 -#define M33_TRCDEVARCH_REVISION_RESET _u(0x2) -#define M33_TRCDEVARCH_REVISION_BITS _u(0x000f0000) -#define M33_TRCDEVARCH_REVISION_MSB _u(19) -#define M33_TRCDEVARCH_REVISION_LSB _u(16) -#define M33_TRCDEVARCH_REVISION_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_TRCDEVARCH_ARCHID -// Description : reads as 0b0100101000010011 -#define M33_TRCDEVARCH_ARCHID_RESET _u(0x4a13) -#define M33_TRCDEVARCH_ARCHID_BITS _u(0x0000ffff) -#define M33_TRCDEVARCH_ARCHID_MSB _u(15) -#define M33_TRCDEVARCH_ARCHID_LSB _u(0) -#define M33_TRCDEVARCH_ARCHID_ACCESS "RO" -// ============================================================================= -// Register : M33_TRCDEVID -// Description : TRCDEVID -#define M33_TRCDEVID_OFFSET _u(0x00041fc8) -#define M33_TRCDEVID_BITS _u(0x00000000) -#define M33_TRCDEVID_RESET _u(0x00000000) -#define M33_TRCDEVID_MSB _u(31) -#define M33_TRCDEVID_LSB _u(0) -#define M33_TRCDEVID_ACCESS "RW" -// ============================================================================= -// Register : M33_TRCDEVTYPE -// Description : TRCDEVTYPE -#define M33_TRCDEVTYPE_OFFSET _u(0x00041fcc) -#define M33_TRCDEVTYPE_BITS _u(0x000000ff) -#define M33_TRCDEVTYPE_RESET _u(0x00000013) -// ----------------------------------------------------------------------------- -// Field : M33_TRCDEVTYPE_SUB -// Description : reads as 0b0001 -#define M33_TRCDEVTYPE_SUB_RESET _u(0x1) -#define M33_TRCDEVTYPE_SUB_BITS _u(0x000000f0) -#define M33_TRCDEVTYPE_SUB_MSB _u(7) -#define M33_TRCDEVTYPE_SUB_LSB _u(4) -#define M33_TRCDEVTYPE_SUB_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_TRCDEVTYPE_MAJOR -// Description : reads as 0b0011 -#define M33_TRCDEVTYPE_MAJOR_RESET _u(0x3) -#define M33_TRCDEVTYPE_MAJOR_BITS _u(0x0000000f) -#define M33_TRCDEVTYPE_MAJOR_MSB _u(3) -#define M33_TRCDEVTYPE_MAJOR_LSB _u(0) -#define M33_TRCDEVTYPE_MAJOR_ACCESS "RO" -// ============================================================================= -// Register : M33_TRCPIDR4 -// Description : TRCPIDR4 -#define M33_TRCPIDR4_OFFSET _u(0x00041fd0) -#define M33_TRCPIDR4_BITS _u(0x000000ff) -#define M33_TRCPIDR4_RESET _u(0x00000004) -// ----------------------------------------------------------------------------- -// Field : M33_TRCPIDR4_SIZE -// Description : reads as `ImpDef -#define M33_TRCPIDR4_SIZE_RESET _u(0x0) -#define M33_TRCPIDR4_SIZE_BITS _u(0x000000f0) -#define M33_TRCPIDR4_SIZE_MSB _u(7) -#define M33_TRCPIDR4_SIZE_LSB _u(4) -#define M33_TRCPIDR4_SIZE_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_TRCPIDR4_DES_2 -// Description : reads as `ImpDef -#define M33_TRCPIDR4_DES_2_RESET _u(0x4) -#define M33_TRCPIDR4_DES_2_BITS _u(0x0000000f) -#define M33_TRCPIDR4_DES_2_MSB _u(3) -#define M33_TRCPIDR4_DES_2_LSB _u(0) -#define M33_TRCPIDR4_DES_2_ACCESS "RO" -// ============================================================================= -// Register : M33_TRCPIDR5 -// Description : TRCPIDR5 -#define M33_TRCPIDR5_OFFSET _u(0x00041fd4) -#define M33_TRCPIDR5_BITS _u(0x00000000) -#define M33_TRCPIDR5_RESET _u(0x00000000) -#define M33_TRCPIDR5_MSB _u(31) -#define M33_TRCPIDR5_LSB _u(0) -#define M33_TRCPIDR5_ACCESS "RW" -// ============================================================================= -// Register : M33_TRCPIDR6 -// Description : TRCPIDR6 -#define M33_TRCPIDR6_OFFSET _u(0x00041fd8) -#define M33_TRCPIDR6_BITS _u(0x00000000) -#define M33_TRCPIDR6_RESET _u(0x00000000) -#define M33_TRCPIDR6_MSB _u(31) -#define M33_TRCPIDR6_LSB _u(0) -#define M33_TRCPIDR6_ACCESS "RW" -// ============================================================================= -// Register : M33_TRCPIDR7 -// Description : TRCPIDR7 -#define M33_TRCPIDR7_OFFSET _u(0x00041fdc) -#define M33_TRCPIDR7_BITS _u(0x00000000) -#define M33_TRCPIDR7_RESET _u(0x00000000) -#define M33_TRCPIDR7_MSB _u(31) -#define M33_TRCPIDR7_LSB _u(0) -#define M33_TRCPIDR7_ACCESS "RW" -// ============================================================================= -// Register : M33_TRCPIDR0 -// Description : TRCPIDR0 -#define M33_TRCPIDR0_OFFSET _u(0x00041fe0) -#define M33_TRCPIDR0_BITS _u(0x000000ff) -#define M33_TRCPIDR0_RESET _u(0x00000021) -// ----------------------------------------------------------------------------- -// Field : M33_TRCPIDR0_PART_0 -// Description : reads as `ImpDef -#define M33_TRCPIDR0_PART_0_RESET _u(0x21) -#define M33_TRCPIDR0_PART_0_BITS _u(0x000000ff) -#define M33_TRCPIDR0_PART_0_MSB _u(7) -#define M33_TRCPIDR0_PART_0_LSB _u(0) -#define M33_TRCPIDR0_PART_0_ACCESS "RO" -// ============================================================================= -// Register : M33_TRCPIDR1 -// Description : TRCPIDR1 -#define M33_TRCPIDR1_OFFSET _u(0x00041fe4) -#define M33_TRCPIDR1_BITS _u(0x000000ff) -#define M33_TRCPIDR1_RESET _u(0x000000bd) -// ----------------------------------------------------------------------------- -// Field : M33_TRCPIDR1_DES_0 -// Description : reads as `ImpDef -#define M33_TRCPIDR1_DES_0_RESET _u(0xb) -#define M33_TRCPIDR1_DES_0_BITS _u(0x000000f0) -#define M33_TRCPIDR1_DES_0_MSB _u(7) -#define M33_TRCPIDR1_DES_0_LSB _u(4) -#define M33_TRCPIDR1_DES_0_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_TRCPIDR1_PART_0 -// Description : reads as `ImpDef -#define M33_TRCPIDR1_PART_0_RESET _u(0xd) -#define M33_TRCPIDR1_PART_0_BITS _u(0x0000000f) -#define M33_TRCPIDR1_PART_0_MSB _u(3) -#define M33_TRCPIDR1_PART_0_LSB _u(0) -#define M33_TRCPIDR1_PART_0_ACCESS "RO" -// ============================================================================= -// Register : M33_TRCPIDR2 -// Description : TRCPIDR2 -#define M33_TRCPIDR2_OFFSET _u(0x00041fe8) -#define M33_TRCPIDR2_BITS _u(0x000000ff) -#define M33_TRCPIDR2_RESET _u(0x0000002b) -// ----------------------------------------------------------------------------- -// Field : M33_TRCPIDR2_REVISION -// Description : reads as `ImpDef -#define M33_TRCPIDR2_REVISION_RESET _u(0x2) -#define M33_TRCPIDR2_REVISION_BITS _u(0x000000f0) -#define M33_TRCPIDR2_REVISION_MSB _u(7) -#define M33_TRCPIDR2_REVISION_LSB _u(4) -#define M33_TRCPIDR2_REVISION_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_TRCPIDR2_JEDEC -// Description : reads as 0b1 -#define M33_TRCPIDR2_JEDEC_RESET _u(0x1) -#define M33_TRCPIDR2_JEDEC_BITS _u(0x00000008) -#define M33_TRCPIDR2_JEDEC_MSB _u(3) -#define M33_TRCPIDR2_JEDEC_LSB _u(3) -#define M33_TRCPIDR2_JEDEC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_TRCPIDR2_DES_0 -// Description : reads as `ImpDef -#define M33_TRCPIDR2_DES_0_RESET _u(0x3) -#define M33_TRCPIDR2_DES_0_BITS _u(0x00000007) -#define M33_TRCPIDR2_DES_0_MSB _u(2) -#define M33_TRCPIDR2_DES_0_LSB _u(0) -#define M33_TRCPIDR2_DES_0_ACCESS "RO" -// ============================================================================= -// Register : M33_TRCPIDR3 -// Description : TRCPIDR3 -#define M33_TRCPIDR3_OFFSET _u(0x00041fec) -#define M33_TRCPIDR3_BITS _u(0x000000ff) -#define M33_TRCPIDR3_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_TRCPIDR3_REVAND -// Description : reads as `ImpDef -#define M33_TRCPIDR3_REVAND_RESET _u(0x0) -#define M33_TRCPIDR3_REVAND_BITS _u(0x000000f0) -#define M33_TRCPIDR3_REVAND_MSB _u(7) -#define M33_TRCPIDR3_REVAND_LSB _u(4) -#define M33_TRCPIDR3_REVAND_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_TRCPIDR3_CMOD -// Description : reads as `ImpDef -#define M33_TRCPIDR3_CMOD_RESET _u(0x0) -#define M33_TRCPIDR3_CMOD_BITS _u(0x0000000f) -#define M33_TRCPIDR3_CMOD_MSB _u(3) -#define M33_TRCPIDR3_CMOD_LSB _u(0) -#define M33_TRCPIDR3_CMOD_ACCESS "RO" -// ============================================================================= -// Register : M33_TRCCIDR0 -// Description : TRCCIDR0 -#define M33_TRCCIDR0_OFFSET _u(0x00041ff0) -#define M33_TRCCIDR0_BITS _u(0x000000ff) -#define M33_TRCCIDR0_RESET _u(0x0000000d) -// ----------------------------------------------------------------------------- -// Field : M33_TRCCIDR0_PRMBL_0 -// Description : reads as 0b00001101 -#define M33_TRCCIDR0_PRMBL_0_RESET _u(0x0d) -#define M33_TRCCIDR0_PRMBL_0_BITS _u(0x000000ff) -#define M33_TRCCIDR0_PRMBL_0_MSB _u(7) -#define M33_TRCCIDR0_PRMBL_0_LSB _u(0) -#define M33_TRCCIDR0_PRMBL_0_ACCESS "RO" -// ============================================================================= -// Register : M33_TRCCIDR1 -// Description : TRCCIDR1 -#define M33_TRCCIDR1_OFFSET _u(0x00041ff4) -#define M33_TRCCIDR1_BITS _u(0x000000ff) -#define M33_TRCCIDR1_RESET _u(0x00000090) -// ----------------------------------------------------------------------------- -// Field : M33_TRCCIDR1_CLASS -// Description : reads as 0b1001 -#define M33_TRCCIDR1_CLASS_RESET _u(0x9) -#define M33_TRCCIDR1_CLASS_BITS _u(0x000000f0) -#define M33_TRCCIDR1_CLASS_MSB _u(7) -#define M33_TRCCIDR1_CLASS_LSB _u(4) -#define M33_TRCCIDR1_CLASS_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_TRCCIDR1_PRMBL_1 -// Description : reads as 0b0000 -#define M33_TRCCIDR1_PRMBL_1_RESET _u(0x0) -#define M33_TRCCIDR1_PRMBL_1_BITS _u(0x0000000f) -#define M33_TRCCIDR1_PRMBL_1_MSB _u(3) -#define M33_TRCCIDR1_PRMBL_1_LSB _u(0) -#define M33_TRCCIDR1_PRMBL_1_ACCESS "RO" -// ============================================================================= -// Register : M33_TRCCIDR2 -// Description : TRCCIDR2 -#define M33_TRCCIDR2_OFFSET _u(0x00041ff8) -#define M33_TRCCIDR2_BITS _u(0x000000ff) -#define M33_TRCCIDR2_RESET _u(0x00000005) -// ----------------------------------------------------------------------------- -// Field : M33_TRCCIDR2_PRMBL_2 -// Description : reads as 0b00000101 -#define M33_TRCCIDR2_PRMBL_2_RESET _u(0x05) -#define M33_TRCCIDR2_PRMBL_2_BITS _u(0x000000ff) -#define M33_TRCCIDR2_PRMBL_2_MSB _u(7) -#define M33_TRCCIDR2_PRMBL_2_LSB _u(0) -#define M33_TRCCIDR2_PRMBL_2_ACCESS "RO" -// ============================================================================= -// Register : M33_TRCCIDR3 -// Description : TRCCIDR3 -#define M33_TRCCIDR3_OFFSET _u(0x00041ffc) -#define M33_TRCCIDR3_BITS _u(0x000000ff) -#define M33_TRCCIDR3_RESET _u(0x000000b1) -// ----------------------------------------------------------------------------- -// Field : M33_TRCCIDR3_PRMBL_3 -// Description : reads as 0b10110001 -#define M33_TRCCIDR3_PRMBL_3_RESET _u(0xb1) -#define M33_TRCCIDR3_PRMBL_3_BITS _u(0x000000ff) -#define M33_TRCCIDR3_PRMBL_3_MSB _u(7) -#define M33_TRCCIDR3_PRMBL_3_LSB _u(0) -#define M33_TRCCIDR3_PRMBL_3_ACCESS "RO" -// ============================================================================= -// Register : M33_CTICONTROL -// Description : CTI Control Register -#define M33_CTICONTROL_OFFSET _u(0x00042000) -#define M33_CTICONTROL_BITS _u(0x00000001) -#define M33_CTICONTROL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_CTICONTROL_GLBEN -// Description : Enables or disables the CTI -#define M33_CTICONTROL_GLBEN_RESET _u(0x0) -#define M33_CTICONTROL_GLBEN_BITS _u(0x00000001) -#define M33_CTICONTROL_GLBEN_MSB _u(0) -#define M33_CTICONTROL_GLBEN_LSB _u(0) -#define M33_CTICONTROL_GLBEN_ACCESS "RW" -// ============================================================================= -// Register : M33_CTIINTACK -// Description : CTI Interrupt Acknowledge Register -#define M33_CTIINTACK_OFFSET _u(0x00042010) -#define M33_CTIINTACK_BITS _u(0x000000ff) -#define M33_CTIINTACK_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_CTIINTACK_INTACK -// Description : Acknowledges the corresponding ctitrigout output. There is one -// bit of the register for each ctitrigout output. When a 1 is -// written to a bit in this register, the corresponding ctitrigout -// is acknowledged, causing it to be cleared. -#define M33_CTIINTACK_INTACK_RESET _u(0x00) -#define M33_CTIINTACK_INTACK_BITS _u(0x000000ff) -#define M33_CTIINTACK_INTACK_MSB _u(7) -#define M33_CTIINTACK_INTACK_LSB _u(0) -#define M33_CTIINTACK_INTACK_ACCESS "RW" -// ============================================================================= -// Register : M33_CTIAPPSET -// Description : CTI Application Trigger Set Register -#define M33_CTIAPPSET_OFFSET _u(0x00042014) -#define M33_CTIAPPSET_BITS _u(0x0000000f) -#define M33_CTIAPPSET_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_CTIAPPSET_APPSET -// Description : Setting a bit HIGH generates a channel event for the selected -// channel. There is one bit of the register for each channel -#define M33_CTIAPPSET_APPSET_RESET _u(0x0) -#define M33_CTIAPPSET_APPSET_BITS _u(0x0000000f) -#define M33_CTIAPPSET_APPSET_MSB _u(3) -#define M33_CTIAPPSET_APPSET_LSB _u(0) -#define M33_CTIAPPSET_APPSET_ACCESS "RW" -// ============================================================================= -// Register : M33_CTIAPPCLEAR -// Description : CTI Application Trigger Clear Register -#define M33_CTIAPPCLEAR_OFFSET _u(0x00042018) -#define M33_CTIAPPCLEAR_BITS _u(0x0000000f) -#define M33_CTIAPPCLEAR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_CTIAPPCLEAR_APPCLEAR -// Description : Sets the corresponding bits in the CTIAPPSET to 0. There is one -// bit of the register for each channel. -#define M33_CTIAPPCLEAR_APPCLEAR_RESET _u(0x0) -#define M33_CTIAPPCLEAR_APPCLEAR_BITS _u(0x0000000f) -#define M33_CTIAPPCLEAR_APPCLEAR_MSB _u(3) -#define M33_CTIAPPCLEAR_APPCLEAR_LSB _u(0) -#define M33_CTIAPPCLEAR_APPCLEAR_ACCESS "RW" -// ============================================================================= -// Register : M33_CTIAPPPULSE -// Description : CTI Application Pulse Register -#define M33_CTIAPPPULSE_OFFSET _u(0x0004201c) -#define M33_CTIAPPPULSE_BITS _u(0x0000000f) -#define M33_CTIAPPPULSE_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_CTIAPPPULSE_APPULSE -// Description : Setting a bit HIGH generates a channel event pulse for the -// selected channel. There is one bit of the register for each -// channel. -#define M33_CTIAPPPULSE_APPULSE_RESET _u(0x0) -#define M33_CTIAPPPULSE_APPULSE_BITS _u(0x0000000f) -#define M33_CTIAPPPULSE_APPULSE_MSB _u(3) -#define M33_CTIAPPPULSE_APPULSE_LSB _u(0) -#define M33_CTIAPPPULSE_APPULSE_ACCESS "RW" -// ============================================================================= -// Register : M33_CTIINEN0 -// Description : CTI Trigger to Channel Enable Registers -#define M33_CTIINEN0_OFFSET _u(0x00042020) -#define M33_CTIINEN0_BITS _u(0x0000000f) -#define M33_CTIINEN0_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_CTIINEN0_TRIGINEN -// Description : Enables a cross trigger event to the corresponding channel when -// a ctitrigin input is activated. There is one bit of the field -// for each of the four channels -#define M33_CTIINEN0_TRIGINEN_RESET _u(0x0) -#define M33_CTIINEN0_TRIGINEN_BITS _u(0x0000000f) -#define M33_CTIINEN0_TRIGINEN_MSB _u(3) -#define M33_CTIINEN0_TRIGINEN_LSB _u(0) -#define M33_CTIINEN0_TRIGINEN_ACCESS "RW" -// ============================================================================= -// Register : M33_CTIINEN1 -// Description : CTI Trigger to Channel Enable Registers -#define M33_CTIINEN1_OFFSET _u(0x00042024) -#define M33_CTIINEN1_BITS _u(0x0000000f) -#define M33_CTIINEN1_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_CTIINEN1_TRIGINEN -// Description : Enables a cross trigger event to the corresponding channel when -// a ctitrigin input is activated. There is one bit of the field -// for each of the four channels -#define M33_CTIINEN1_TRIGINEN_RESET _u(0x0) -#define M33_CTIINEN1_TRIGINEN_BITS _u(0x0000000f) -#define M33_CTIINEN1_TRIGINEN_MSB _u(3) -#define M33_CTIINEN1_TRIGINEN_LSB _u(0) -#define M33_CTIINEN1_TRIGINEN_ACCESS "RW" -// ============================================================================= -// Register : M33_CTIINEN2 -// Description : CTI Trigger to Channel Enable Registers -#define M33_CTIINEN2_OFFSET _u(0x00042028) -#define M33_CTIINEN2_BITS _u(0x0000000f) -#define M33_CTIINEN2_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_CTIINEN2_TRIGINEN -// Description : Enables a cross trigger event to the corresponding channel when -// a ctitrigin input is activated. There is one bit of the field -// for each of the four channels -#define M33_CTIINEN2_TRIGINEN_RESET _u(0x0) -#define M33_CTIINEN2_TRIGINEN_BITS _u(0x0000000f) -#define M33_CTIINEN2_TRIGINEN_MSB _u(3) -#define M33_CTIINEN2_TRIGINEN_LSB _u(0) -#define M33_CTIINEN2_TRIGINEN_ACCESS "RW" -// ============================================================================= -// Register : M33_CTIINEN3 -// Description : CTI Trigger to Channel Enable Registers -#define M33_CTIINEN3_OFFSET _u(0x0004202c) -#define M33_CTIINEN3_BITS _u(0x0000000f) -#define M33_CTIINEN3_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_CTIINEN3_TRIGINEN -// Description : Enables a cross trigger event to the corresponding channel when -// a ctitrigin input is activated. There is one bit of the field -// for each of the four channels -#define M33_CTIINEN3_TRIGINEN_RESET _u(0x0) -#define M33_CTIINEN3_TRIGINEN_BITS _u(0x0000000f) -#define M33_CTIINEN3_TRIGINEN_MSB _u(3) -#define M33_CTIINEN3_TRIGINEN_LSB _u(0) -#define M33_CTIINEN3_TRIGINEN_ACCESS "RW" -// ============================================================================= -// Register : M33_CTIINEN4 -// Description : CTI Trigger to Channel Enable Registers -#define M33_CTIINEN4_OFFSET _u(0x00042030) -#define M33_CTIINEN4_BITS _u(0x0000000f) -#define M33_CTIINEN4_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_CTIINEN4_TRIGINEN -// Description : Enables a cross trigger event to the corresponding channel when -// a ctitrigin input is activated. There is one bit of the field -// for each of the four channels -#define M33_CTIINEN4_TRIGINEN_RESET _u(0x0) -#define M33_CTIINEN4_TRIGINEN_BITS _u(0x0000000f) -#define M33_CTIINEN4_TRIGINEN_MSB _u(3) -#define M33_CTIINEN4_TRIGINEN_LSB _u(0) -#define M33_CTIINEN4_TRIGINEN_ACCESS "RW" -// ============================================================================= -// Register : M33_CTIINEN5 -// Description : CTI Trigger to Channel Enable Registers -#define M33_CTIINEN5_OFFSET _u(0x00042034) -#define M33_CTIINEN5_BITS _u(0x0000000f) -#define M33_CTIINEN5_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_CTIINEN5_TRIGINEN -// Description : Enables a cross trigger event to the corresponding channel when -// a ctitrigin input is activated. There is one bit of the field -// for each of the four channels -#define M33_CTIINEN5_TRIGINEN_RESET _u(0x0) -#define M33_CTIINEN5_TRIGINEN_BITS _u(0x0000000f) -#define M33_CTIINEN5_TRIGINEN_MSB _u(3) -#define M33_CTIINEN5_TRIGINEN_LSB _u(0) -#define M33_CTIINEN5_TRIGINEN_ACCESS "RW" -// ============================================================================= -// Register : M33_CTIINEN6 -// Description : CTI Trigger to Channel Enable Registers -#define M33_CTIINEN6_OFFSET _u(0x00042038) -#define M33_CTIINEN6_BITS _u(0x0000000f) -#define M33_CTIINEN6_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_CTIINEN6_TRIGINEN -// Description : Enables a cross trigger event to the corresponding channel when -// a ctitrigin input is activated. There is one bit of the field -// for each of the four channels -#define M33_CTIINEN6_TRIGINEN_RESET _u(0x0) -#define M33_CTIINEN6_TRIGINEN_BITS _u(0x0000000f) -#define M33_CTIINEN6_TRIGINEN_MSB _u(3) -#define M33_CTIINEN6_TRIGINEN_LSB _u(0) -#define M33_CTIINEN6_TRIGINEN_ACCESS "RW" -// ============================================================================= -// Register : M33_CTIINEN7 -// Description : CTI Trigger to Channel Enable Registers -#define M33_CTIINEN7_OFFSET _u(0x0004203c) -#define M33_CTIINEN7_BITS _u(0x0000000f) -#define M33_CTIINEN7_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_CTIINEN7_TRIGINEN -// Description : Enables a cross trigger event to the corresponding channel when -// a ctitrigin input is activated. There is one bit of the field -// for each of the four channels -#define M33_CTIINEN7_TRIGINEN_RESET _u(0x0) -#define M33_CTIINEN7_TRIGINEN_BITS _u(0x0000000f) -#define M33_CTIINEN7_TRIGINEN_MSB _u(3) -#define M33_CTIINEN7_TRIGINEN_LSB _u(0) -#define M33_CTIINEN7_TRIGINEN_ACCESS "RW" -// ============================================================================= -// Register : M33_CTIOUTEN0 -// Description : CTI Trigger to Channel Enable Registers -#define M33_CTIOUTEN0_OFFSET _u(0x000420a0) -#define M33_CTIOUTEN0_BITS _u(0x0000000f) -#define M33_CTIOUTEN0_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_CTIOUTEN0_TRIGOUTEN -// Description : Enables a cross trigger event to ctitrigout when the -// corresponding channel is activated. There is one bit of the -// field for each of the four channels. -#define M33_CTIOUTEN0_TRIGOUTEN_RESET _u(0x0) -#define M33_CTIOUTEN0_TRIGOUTEN_BITS _u(0x0000000f) -#define M33_CTIOUTEN0_TRIGOUTEN_MSB _u(3) -#define M33_CTIOUTEN0_TRIGOUTEN_LSB _u(0) -#define M33_CTIOUTEN0_TRIGOUTEN_ACCESS "RW" -// ============================================================================= -// Register : M33_CTIOUTEN1 -// Description : CTI Trigger to Channel Enable Registers -#define M33_CTIOUTEN1_OFFSET _u(0x000420a4) -#define M33_CTIOUTEN1_BITS _u(0x0000000f) -#define M33_CTIOUTEN1_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_CTIOUTEN1_TRIGOUTEN -// Description : Enables a cross trigger event to ctitrigout when the -// corresponding channel is activated. There is one bit of the -// field for each of the four channels. -#define M33_CTIOUTEN1_TRIGOUTEN_RESET _u(0x0) -#define M33_CTIOUTEN1_TRIGOUTEN_BITS _u(0x0000000f) -#define M33_CTIOUTEN1_TRIGOUTEN_MSB _u(3) -#define M33_CTIOUTEN1_TRIGOUTEN_LSB _u(0) -#define M33_CTIOUTEN1_TRIGOUTEN_ACCESS "RW" -// ============================================================================= -// Register : M33_CTIOUTEN2 -// Description : CTI Trigger to Channel Enable Registers -#define M33_CTIOUTEN2_OFFSET _u(0x000420a8) -#define M33_CTIOUTEN2_BITS _u(0x0000000f) -#define M33_CTIOUTEN2_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_CTIOUTEN2_TRIGOUTEN -// Description : Enables a cross trigger event to ctitrigout when the -// corresponding channel is activated. There is one bit of the -// field for each of the four channels. -#define M33_CTIOUTEN2_TRIGOUTEN_RESET _u(0x0) -#define M33_CTIOUTEN2_TRIGOUTEN_BITS _u(0x0000000f) -#define M33_CTIOUTEN2_TRIGOUTEN_MSB _u(3) -#define M33_CTIOUTEN2_TRIGOUTEN_LSB _u(0) -#define M33_CTIOUTEN2_TRIGOUTEN_ACCESS "RW" -// ============================================================================= -// Register : M33_CTIOUTEN3 -// Description : CTI Trigger to Channel Enable Registers -#define M33_CTIOUTEN3_OFFSET _u(0x000420ac) -#define M33_CTIOUTEN3_BITS _u(0x0000000f) -#define M33_CTIOUTEN3_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_CTIOUTEN3_TRIGOUTEN -// Description : Enables a cross trigger event to ctitrigout when the -// corresponding channel is activated. There is one bit of the -// field for each of the four channels. -#define M33_CTIOUTEN3_TRIGOUTEN_RESET _u(0x0) -#define M33_CTIOUTEN3_TRIGOUTEN_BITS _u(0x0000000f) -#define M33_CTIOUTEN3_TRIGOUTEN_MSB _u(3) -#define M33_CTIOUTEN3_TRIGOUTEN_LSB _u(0) -#define M33_CTIOUTEN3_TRIGOUTEN_ACCESS "RW" -// ============================================================================= -// Register : M33_CTIOUTEN4 -// Description : CTI Trigger to Channel Enable Registers -#define M33_CTIOUTEN4_OFFSET _u(0x000420b0) -#define M33_CTIOUTEN4_BITS _u(0x0000000f) -#define M33_CTIOUTEN4_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_CTIOUTEN4_TRIGOUTEN -// Description : Enables a cross trigger event to ctitrigout when the -// corresponding channel is activated. There is one bit of the -// field for each of the four channels. -#define M33_CTIOUTEN4_TRIGOUTEN_RESET _u(0x0) -#define M33_CTIOUTEN4_TRIGOUTEN_BITS _u(0x0000000f) -#define M33_CTIOUTEN4_TRIGOUTEN_MSB _u(3) -#define M33_CTIOUTEN4_TRIGOUTEN_LSB _u(0) -#define M33_CTIOUTEN4_TRIGOUTEN_ACCESS "RW" -// ============================================================================= -// Register : M33_CTIOUTEN5 -// Description : CTI Trigger to Channel Enable Registers -#define M33_CTIOUTEN5_OFFSET _u(0x000420b4) -#define M33_CTIOUTEN5_BITS _u(0x0000000f) -#define M33_CTIOUTEN5_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_CTIOUTEN5_TRIGOUTEN -// Description : Enables a cross trigger event to ctitrigout when the -// corresponding channel is activated. There is one bit of the -// field for each of the four channels. -#define M33_CTIOUTEN5_TRIGOUTEN_RESET _u(0x0) -#define M33_CTIOUTEN5_TRIGOUTEN_BITS _u(0x0000000f) -#define M33_CTIOUTEN5_TRIGOUTEN_MSB _u(3) -#define M33_CTIOUTEN5_TRIGOUTEN_LSB _u(0) -#define M33_CTIOUTEN5_TRIGOUTEN_ACCESS "RW" -// ============================================================================= -// Register : M33_CTIOUTEN6 -// Description : CTI Trigger to Channel Enable Registers -#define M33_CTIOUTEN6_OFFSET _u(0x000420b8) -#define M33_CTIOUTEN6_BITS _u(0x0000000f) -#define M33_CTIOUTEN6_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_CTIOUTEN6_TRIGOUTEN -// Description : Enables a cross trigger event to ctitrigout when the -// corresponding channel is activated. There is one bit of the -// field for each of the four channels. -#define M33_CTIOUTEN6_TRIGOUTEN_RESET _u(0x0) -#define M33_CTIOUTEN6_TRIGOUTEN_BITS _u(0x0000000f) -#define M33_CTIOUTEN6_TRIGOUTEN_MSB _u(3) -#define M33_CTIOUTEN6_TRIGOUTEN_LSB _u(0) -#define M33_CTIOUTEN6_TRIGOUTEN_ACCESS "RW" -// ============================================================================= -// Register : M33_CTIOUTEN7 -// Description : CTI Trigger to Channel Enable Registers -#define M33_CTIOUTEN7_OFFSET _u(0x000420bc) -#define M33_CTIOUTEN7_BITS _u(0x0000000f) -#define M33_CTIOUTEN7_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_CTIOUTEN7_TRIGOUTEN -// Description : Enables a cross trigger event to ctitrigout when the -// corresponding channel is activated. There is one bit of the -// field for each of the four channels. -#define M33_CTIOUTEN7_TRIGOUTEN_RESET _u(0x0) -#define M33_CTIOUTEN7_TRIGOUTEN_BITS _u(0x0000000f) -#define M33_CTIOUTEN7_TRIGOUTEN_MSB _u(3) -#define M33_CTIOUTEN7_TRIGOUTEN_LSB _u(0) -#define M33_CTIOUTEN7_TRIGOUTEN_ACCESS "RW" -// ============================================================================= -// Register : M33_CTITRIGINSTATUS -// Description : CTI Trigger to Channel Enable Registers -#define M33_CTITRIGINSTATUS_OFFSET _u(0x00042130) -#define M33_CTITRIGINSTATUS_BITS _u(0x000000ff) -#define M33_CTITRIGINSTATUS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_CTITRIGINSTATUS_TRIGINSTATUS -// Description : Shows the status of the ctitrigin inputs. There is one bit of -// the field for each trigger input.Because the register provides -// a view of the raw ctitrigin inputs, the reset value is UNKNOWN. -#define M33_CTITRIGINSTATUS_TRIGINSTATUS_RESET _u(0x00) -#define M33_CTITRIGINSTATUS_TRIGINSTATUS_BITS _u(0x000000ff) -#define M33_CTITRIGINSTATUS_TRIGINSTATUS_MSB _u(7) -#define M33_CTITRIGINSTATUS_TRIGINSTATUS_LSB _u(0) -#define M33_CTITRIGINSTATUS_TRIGINSTATUS_ACCESS "RO" -// ============================================================================= -// Register : M33_CTITRIGOUTSTATUS -// Description : CTI Trigger In Status Register -#define M33_CTITRIGOUTSTATUS_OFFSET _u(0x00042134) -#define M33_CTITRIGOUTSTATUS_BITS _u(0x000000ff) -#define M33_CTITRIGOUTSTATUS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_CTITRIGOUTSTATUS_TRIGOUTSTATUS -// Description : Shows the status of the ctitrigout outputs. There is one bit of -// the field for each trigger output. -#define M33_CTITRIGOUTSTATUS_TRIGOUTSTATUS_RESET _u(0x00) -#define M33_CTITRIGOUTSTATUS_TRIGOUTSTATUS_BITS _u(0x000000ff) -#define M33_CTITRIGOUTSTATUS_TRIGOUTSTATUS_MSB _u(7) -#define M33_CTITRIGOUTSTATUS_TRIGOUTSTATUS_LSB _u(0) -#define M33_CTITRIGOUTSTATUS_TRIGOUTSTATUS_ACCESS "RO" -// ============================================================================= -// Register : M33_CTICHINSTATUS -// Description : CTI Channel In Status Register -#define M33_CTICHINSTATUS_OFFSET _u(0x00042138) -#define M33_CTICHINSTATUS_BITS _u(0x0000000f) -#define M33_CTICHINSTATUS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_CTICHINSTATUS_CTICHOUTSTATUS -// Description : Shows the status of the ctichout outputs. There is one bit of -// the field for each channel output -#define M33_CTICHINSTATUS_CTICHOUTSTATUS_RESET _u(0x0) -#define M33_CTICHINSTATUS_CTICHOUTSTATUS_BITS _u(0x0000000f) -#define M33_CTICHINSTATUS_CTICHOUTSTATUS_MSB _u(3) -#define M33_CTICHINSTATUS_CTICHOUTSTATUS_LSB _u(0) -#define M33_CTICHINSTATUS_CTICHOUTSTATUS_ACCESS "RO" -// ============================================================================= -// Register : M33_CTIGATE -// Description : Enable CTI Channel Gate register -#define M33_CTIGATE_OFFSET _u(0x00042140) -#define M33_CTIGATE_BITS _u(0x0000000f) -#define M33_CTIGATE_RESET _u(0x0000000f) -// ----------------------------------------------------------------------------- -// Field : M33_CTIGATE_CTIGATEEN3 -// Description : Enable ctichout3. Set to 0 to disable channel propagation. -#define M33_CTIGATE_CTIGATEEN3_RESET _u(0x1) -#define M33_CTIGATE_CTIGATEEN3_BITS _u(0x00000008) -#define M33_CTIGATE_CTIGATEEN3_MSB _u(3) -#define M33_CTIGATE_CTIGATEEN3_LSB _u(3) -#define M33_CTIGATE_CTIGATEEN3_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_CTIGATE_CTIGATEEN2 -// Description : Enable ctichout2. Set to 0 to disable channel propagation. -#define M33_CTIGATE_CTIGATEEN2_RESET _u(0x1) -#define M33_CTIGATE_CTIGATEEN2_BITS _u(0x00000004) -#define M33_CTIGATE_CTIGATEEN2_MSB _u(2) -#define M33_CTIGATE_CTIGATEEN2_LSB _u(2) -#define M33_CTIGATE_CTIGATEEN2_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_CTIGATE_CTIGATEEN1 -// Description : Enable ctichout1. Set to 0 to disable channel propagation. -#define M33_CTIGATE_CTIGATEEN1_RESET _u(0x1) -#define M33_CTIGATE_CTIGATEEN1_BITS _u(0x00000002) -#define M33_CTIGATE_CTIGATEEN1_MSB _u(1) -#define M33_CTIGATE_CTIGATEEN1_LSB _u(1) -#define M33_CTIGATE_CTIGATEEN1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_CTIGATE_CTIGATEEN0 -// Description : Enable ctichout0. Set to 0 to disable channel propagation. -#define M33_CTIGATE_CTIGATEEN0_RESET _u(0x1) -#define M33_CTIGATE_CTIGATEEN0_BITS _u(0x00000001) -#define M33_CTIGATE_CTIGATEEN0_MSB _u(0) -#define M33_CTIGATE_CTIGATEEN0_LSB _u(0) -#define M33_CTIGATE_CTIGATEEN0_ACCESS "RW" -// ============================================================================= -// Register : M33_ASICCTL -// Description : External Multiplexer Control register -#define M33_ASICCTL_OFFSET _u(0x00042144) -#define M33_ASICCTL_BITS _u(0x00000000) -#define M33_ASICCTL_RESET _u(0x00000000) -#define M33_ASICCTL_MSB _u(31) -#define M33_ASICCTL_LSB _u(0) -#define M33_ASICCTL_ACCESS "RW" -// ============================================================================= -// Register : M33_ITCHOUT -// Description : Integration Test Channel Output register -#define M33_ITCHOUT_OFFSET _u(0x00042ee4) -#define M33_ITCHOUT_BITS _u(0x0000000f) -#define M33_ITCHOUT_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_ITCHOUT_CTCHOUT -// Description : Sets the value of the ctichout outputs -#define M33_ITCHOUT_CTCHOUT_RESET _u(0x0) -#define M33_ITCHOUT_CTCHOUT_BITS _u(0x0000000f) -#define M33_ITCHOUT_CTCHOUT_MSB _u(3) -#define M33_ITCHOUT_CTCHOUT_LSB _u(0) -#define M33_ITCHOUT_CTCHOUT_ACCESS "RW" -// ============================================================================= -// Register : M33_ITTRIGOUT -// Description : Integration Test Trigger Output register -#define M33_ITTRIGOUT_OFFSET _u(0x00042ee8) -#define M33_ITTRIGOUT_BITS _u(0x000000ff) -#define M33_ITTRIGOUT_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_ITTRIGOUT_CTTRIGOUT -// Description : Sets the value of the ctitrigout outputs -#define M33_ITTRIGOUT_CTTRIGOUT_RESET _u(0x00) -#define M33_ITTRIGOUT_CTTRIGOUT_BITS _u(0x000000ff) -#define M33_ITTRIGOUT_CTTRIGOUT_MSB _u(7) -#define M33_ITTRIGOUT_CTTRIGOUT_LSB _u(0) -#define M33_ITTRIGOUT_CTTRIGOUT_ACCESS "RW" -// ============================================================================= -// Register : M33_ITCHIN -// Description : Integration Test Channel Input register -#define M33_ITCHIN_OFFSET _u(0x00042ef4) -#define M33_ITCHIN_BITS _u(0x0000000f) -#define M33_ITCHIN_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_ITCHIN_CTCHIN -// Description : Reads the value of the ctichin inputs. -#define M33_ITCHIN_CTCHIN_RESET _u(0x0) -#define M33_ITCHIN_CTCHIN_BITS _u(0x0000000f) -#define M33_ITCHIN_CTCHIN_MSB _u(3) -#define M33_ITCHIN_CTCHIN_LSB _u(0) -#define M33_ITCHIN_CTCHIN_ACCESS "RO" -// ============================================================================= -// Register : M33_ITCTRL -// Description : Integration Mode Control register -#define M33_ITCTRL_OFFSET _u(0x00042f00) -#define M33_ITCTRL_BITS _u(0x00000001) -#define M33_ITCTRL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_ITCTRL_IME -// Description : Integration Mode Enable -#define M33_ITCTRL_IME_RESET _u(0x0) -#define M33_ITCTRL_IME_BITS _u(0x00000001) -#define M33_ITCTRL_IME_MSB _u(0) -#define M33_ITCTRL_IME_LSB _u(0) -#define M33_ITCTRL_IME_ACCESS "RW" -// ============================================================================= -// Register : M33_DEVARCH -// Description : Device Architecture register -#define M33_DEVARCH_OFFSET _u(0x00042fbc) -#define M33_DEVARCH_BITS _u(0xffffffff) -#define M33_DEVARCH_RESET _u(0x47701a14) -// ----------------------------------------------------------------------------- -// Field : M33_DEVARCH_ARCHITECT -// Description : Indicates the component architect -#define M33_DEVARCH_ARCHITECT_RESET _u(0x23b) -#define M33_DEVARCH_ARCHITECT_BITS _u(0xffe00000) -#define M33_DEVARCH_ARCHITECT_MSB _u(31) -#define M33_DEVARCH_ARCHITECT_LSB _u(21) -#define M33_DEVARCH_ARCHITECT_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_DEVARCH_PRESENT -// Description : Indicates whether the DEVARCH register is present -#define M33_DEVARCH_PRESENT_RESET _u(0x1) -#define M33_DEVARCH_PRESENT_BITS _u(0x00100000) -#define M33_DEVARCH_PRESENT_MSB _u(20) -#define M33_DEVARCH_PRESENT_LSB _u(20) -#define M33_DEVARCH_PRESENT_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_DEVARCH_REVISION -// Description : Indicates the architecture revision -#define M33_DEVARCH_REVISION_RESET _u(0x0) -#define M33_DEVARCH_REVISION_BITS _u(0x000f0000) -#define M33_DEVARCH_REVISION_MSB _u(19) -#define M33_DEVARCH_REVISION_LSB _u(16) -#define M33_DEVARCH_REVISION_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_DEVARCH_ARCHID -// Description : Indicates the component -#define M33_DEVARCH_ARCHID_RESET _u(0x1a14) -#define M33_DEVARCH_ARCHID_BITS _u(0x0000ffff) -#define M33_DEVARCH_ARCHID_MSB _u(15) -#define M33_DEVARCH_ARCHID_LSB _u(0) -#define M33_DEVARCH_ARCHID_ACCESS "RO" -// ============================================================================= -// Register : M33_DEVID -// Description : Device Configuration register -#define M33_DEVID_OFFSET _u(0x00042fc8) -#define M33_DEVID_BITS _u(0x000fff1f) -#define M33_DEVID_RESET _u(0x00040800) -// ----------------------------------------------------------------------------- -// Field : M33_DEVID_NUMCH -// Description : Number of ECT channels available -#define M33_DEVID_NUMCH_RESET _u(0x4) -#define M33_DEVID_NUMCH_BITS _u(0x000f0000) -#define M33_DEVID_NUMCH_MSB _u(19) -#define M33_DEVID_NUMCH_LSB _u(16) -#define M33_DEVID_NUMCH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_DEVID_NUMTRIG -// Description : Number of ECT triggers available. -#define M33_DEVID_NUMTRIG_RESET _u(0x08) -#define M33_DEVID_NUMTRIG_BITS _u(0x0000ff00) -#define M33_DEVID_NUMTRIG_MSB _u(15) -#define M33_DEVID_NUMTRIG_LSB _u(8) -#define M33_DEVID_NUMTRIG_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_DEVID_EXTMUXNUM -// Description : Indicates the number of multiplexers available on Trigger -// Inputs and Trigger Outputs that are using asicctl. The default -// value of 0b00000 indicates that no multiplexing is present. -// This value of this bit depends on the Verilog define EXTMUXNUM -// that you must change accordingly. -#define M33_DEVID_EXTMUXNUM_RESET _u(0x00) -#define M33_DEVID_EXTMUXNUM_BITS _u(0x0000001f) -#define M33_DEVID_EXTMUXNUM_MSB _u(4) -#define M33_DEVID_EXTMUXNUM_LSB _u(0) -#define M33_DEVID_EXTMUXNUM_ACCESS "RO" -// ============================================================================= -// Register : M33_DEVTYPE -// Description : Device Type Identifier register -#define M33_DEVTYPE_OFFSET _u(0x00042fcc) -#define M33_DEVTYPE_BITS _u(0x000000ff) -#define M33_DEVTYPE_RESET _u(0x00000014) -// ----------------------------------------------------------------------------- -// Field : M33_DEVTYPE_SUB -// Description : Sub-classification of the type of the debug component as -// specified in the ARM Architecture Specification within the -// major classification as specified in the MAJOR field. -#define M33_DEVTYPE_SUB_RESET _u(0x1) -#define M33_DEVTYPE_SUB_BITS _u(0x000000f0) -#define M33_DEVTYPE_SUB_MSB _u(7) -#define M33_DEVTYPE_SUB_LSB _u(4) -#define M33_DEVTYPE_SUB_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_DEVTYPE_MAJOR -// Description : Major classification of the type of the debug component as -// specified in the ARM Architecture Specification for this debug -// and trace component. -#define M33_DEVTYPE_MAJOR_RESET _u(0x4) -#define M33_DEVTYPE_MAJOR_BITS _u(0x0000000f) -#define M33_DEVTYPE_MAJOR_MSB _u(3) -#define M33_DEVTYPE_MAJOR_LSB _u(0) -#define M33_DEVTYPE_MAJOR_ACCESS "RO" -// ============================================================================= -// Register : M33_PIDR4 -// Description : CoreSight Peripheral ID4 -#define M33_PIDR4_OFFSET _u(0x00042fd0) -#define M33_PIDR4_BITS _u(0x000000ff) -#define M33_PIDR4_RESET _u(0x00000004) -// ----------------------------------------------------------------------------- -// Field : M33_PIDR4_SIZE -// Description : Always 0b0000. Indicates that the device only occupies 4KB of -// memory -#define M33_PIDR4_SIZE_RESET _u(0x0) -#define M33_PIDR4_SIZE_BITS _u(0x000000f0) -#define M33_PIDR4_SIZE_MSB _u(7) -#define M33_PIDR4_SIZE_LSB _u(4) -#define M33_PIDR4_SIZE_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_PIDR4_DES_2 -// Description : Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify -// the designer of the component. -#define M33_PIDR4_DES_2_RESET _u(0x4) -#define M33_PIDR4_DES_2_BITS _u(0x0000000f) -#define M33_PIDR4_DES_2_MSB _u(3) -#define M33_PIDR4_DES_2_LSB _u(0) -#define M33_PIDR4_DES_2_ACCESS "RO" -// ============================================================================= -// Register : M33_PIDR5 -// Description : CoreSight Peripheral ID5 -#define M33_PIDR5_OFFSET _u(0x00042fd4) -#define M33_PIDR5_BITS _u(0x00000000) -#define M33_PIDR5_RESET _u(0x00000000) -#define M33_PIDR5_MSB _u(31) -#define M33_PIDR5_LSB _u(0) -#define M33_PIDR5_ACCESS "RW" -// ============================================================================= -// Register : M33_PIDR6 -// Description : CoreSight Peripheral ID6 -#define M33_PIDR6_OFFSET _u(0x00042fd8) -#define M33_PIDR6_BITS _u(0x00000000) -#define M33_PIDR6_RESET _u(0x00000000) -#define M33_PIDR6_MSB _u(31) -#define M33_PIDR6_LSB _u(0) -#define M33_PIDR6_ACCESS "RW" -// ============================================================================= -// Register : M33_PIDR7 -// Description : CoreSight Peripheral ID7 -#define M33_PIDR7_OFFSET _u(0x00042fdc) -#define M33_PIDR7_BITS _u(0x00000000) -#define M33_PIDR7_RESET _u(0x00000000) -#define M33_PIDR7_MSB _u(31) -#define M33_PIDR7_LSB _u(0) -#define M33_PIDR7_ACCESS "RW" -// ============================================================================= -// Register : M33_PIDR0 -// Description : CoreSight Peripheral ID0 -#define M33_PIDR0_OFFSET _u(0x00042fe0) -#define M33_PIDR0_BITS _u(0x000000ff) -#define M33_PIDR0_RESET _u(0x00000021) -// ----------------------------------------------------------------------------- -// Field : M33_PIDR0_PART_0 -// Description : Bits[7:0] of the 12-bit part number of the component. The -// designer of the component assigns this part number. -#define M33_PIDR0_PART_0_RESET _u(0x21) -#define M33_PIDR0_PART_0_BITS _u(0x000000ff) -#define M33_PIDR0_PART_0_MSB _u(7) -#define M33_PIDR0_PART_0_LSB _u(0) -#define M33_PIDR0_PART_0_ACCESS "RO" -// ============================================================================= -// Register : M33_PIDR1 -// Description : CoreSight Peripheral ID1 -#define M33_PIDR1_OFFSET _u(0x00042fe4) -#define M33_PIDR1_BITS _u(0x000000ff) -#define M33_PIDR1_RESET _u(0x000000bd) -// ----------------------------------------------------------------------------- -// Field : M33_PIDR1_DES_0 -// Description : Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify -// the designer of the component. -#define M33_PIDR1_DES_0_RESET _u(0xb) -#define M33_PIDR1_DES_0_BITS _u(0x000000f0) -#define M33_PIDR1_DES_0_MSB _u(7) -#define M33_PIDR1_DES_0_LSB _u(4) -#define M33_PIDR1_DES_0_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_PIDR1_PART_1 -// Description : Bits[11:8] of the 12-bit part number of the component. The -// designer of the component assigns this part number. -#define M33_PIDR1_PART_1_RESET _u(0xd) -#define M33_PIDR1_PART_1_BITS _u(0x0000000f) -#define M33_PIDR1_PART_1_MSB _u(3) -#define M33_PIDR1_PART_1_LSB _u(0) -#define M33_PIDR1_PART_1_ACCESS "RO" -// ============================================================================= -// Register : M33_PIDR2 -// Description : CoreSight Peripheral ID2 -#define M33_PIDR2_OFFSET _u(0x00042fe8) -#define M33_PIDR2_BITS _u(0x000000ff) -#define M33_PIDR2_RESET _u(0x0000000b) -// ----------------------------------------------------------------------------- -// Field : M33_PIDR2_REVISION -// Description : This device is at r1p0 -#define M33_PIDR2_REVISION_RESET _u(0x0) -#define M33_PIDR2_REVISION_BITS _u(0x000000f0) -#define M33_PIDR2_REVISION_MSB _u(7) -#define M33_PIDR2_REVISION_LSB _u(4) -#define M33_PIDR2_REVISION_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_PIDR2_JEDEC -// Description : Always 1. Indicates that the JEDEC-assigned designer ID is -// used. -#define M33_PIDR2_JEDEC_RESET _u(0x1) -#define M33_PIDR2_JEDEC_BITS _u(0x00000008) -#define M33_PIDR2_JEDEC_MSB _u(3) -#define M33_PIDR2_JEDEC_LSB _u(3) -#define M33_PIDR2_JEDEC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_PIDR2_DES_1 -// Description : Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify -// the designer of the component. -#define M33_PIDR2_DES_1_RESET _u(0x3) -#define M33_PIDR2_DES_1_BITS _u(0x00000007) -#define M33_PIDR2_DES_1_MSB _u(2) -#define M33_PIDR2_DES_1_LSB _u(0) -#define M33_PIDR2_DES_1_ACCESS "RO" -// ============================================================================= -// Register : M33_PIDR3 -// Description : CoreSight Peripheral ID3 -#define M33_PIDR3_OFFSET _u(0x00042fec) -#define M33_PIDR3_BITS _u(0x000000ff) -#define M33_PIDR3_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : M33_PIDR3_REVAND -// Description : Indicates minor errata fixes specific to the revision of the -// component being used, for example metal fixes after -// implementation. In most cases, this field is 0b0000. ARM -// recommends that the component designers ensure that a metal fix -// can change this field if required, for example, by driving it -// from registers that reset to 0b0000. -#define M33_PIDR3_REVAND_RESET _u(0x0) -#define M33_PIDR3_REVAND_BITS _u(0x000000f0) -#define M33_PIDR3_REVAND_MSB _u(7) -#define M33_PIDR3_REVAND_LSB _u(4) -#define M33_PIDR3_REVAND_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_PIDR3_CMOD -// Description : Customer Modified. Indicates whether the customer has modified -// the behavior of the component. In most cases, this field is -// 0b0000. Customers change this value when they make authorized -// modifications to this component. -#define M33_PIDR3_CMOD_RESET _u(0x0) -#define M33_PIDR3_CMOD_BITS _u(0x0000000f) -#define M33_PIDR3_CMOD_MSB _u(3) -#define M33_PIDR3_CMOD_LSB _u(0) -#define M33_PIDR3_CMOD_ACCESS "RO" -// ============================================================================= -// Register : M33_CIDR0 -// Description : CoreSight Component ID0 -#define M33_CIDR0_OFFSET _u(0x00042ff0) -#define M33_CIDR0_BITS _u(0x000000ff) -#define M33_CIDR0_RESET _u(0x0000000d) -// ----------------------------------------------------------------------------- -// Field : M33_CIDR0_PRMBL_0 -// Description : Preamble[0]. Contains bits[7:0] of the component identification -// code -#define M33_CIDR0_PRMBL_0_RESET _u(0x0d) -#define M33_CIDR0_PRMBL_0_BITS _u(0x000000ff) -#define M33_CIDR0_PRMBL_0_MSB _u(7) -#define M33_CIDR0_PRMBL_0_LSB _u(0) -#define M33_CIDR0_PRMBL_0_ACCESS "RO" -// ============================================================================= -// Register : M33_CIDR1 -// Description : CoreSight Component ID1 -#define M33_CIDR1_OFFSET _u(0x00042ff4) -#define M33_CIDR1_BITS _u(0x000000ff) -#define M33_CIDR1_RESET _u(0x00000090) -// ----------------------------------------------------------------------------- -// Field : M33_CIDR1_CLASS -// Description : Class of the component, for example, whether the component is a -// ROM table or a generic CoreSight component. Contains -// bits[15:12] of the component identification code. -#define M33_CIDR1_CLASS_RESET _u(0x9) -#define M33_CIDR1_CLASS_BITS _u(0x000000f0) -#define M33_CIDR1_CLASS_MSB _u(7) -#define M33_CIDR1_CLASS_LSB _u(4) -#define M33_CIDR1_CLASS_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_CIDR1_PRMBL_1 -// Description : Preamble[1]. Contains bits[11:8] of the component -// identification code. -#define M33_CIDR1_PRMBL_1_RESET _u(0x0) -#define M33_CIDR1_PRMBL_1_BITS _u(0x0000000f) -#define M33_CIDR1_PRMBL_1_MSB _u(3) -#define M33_CIDR1_PRMBL_1_LSB _u(0) -#define M33_CIDR1_PRMBL_1_ACCESS "RO" -// ============================================================================= -// Register : M33_CIDR2 -// Description : CoreSight Component ID2 -#define M33_CIDR2_OFFSET _u(0x00042ff8) -#define M33_CIDR2_BITS _u(0x000000ff) -#define M33_CIDR2_RESET _u(0x00000005) -// ----------------------------------------------------------------------------- -// Field : M33_CIDR2_PRMBL_2 -// Description : Preamble[2]. Contains bits[23:16] of the component -// identification code. -#define M33_CIDR2_PRMBL_2_RESET _u(0x05) -#define M33_CIDR2_PRMBL_2_BITS _u(0x000000ff) -#define M33_CIDR2_PRMBL_2_MSB _u(7) -#define M33_CIDR2_PRMBL_2_LSB _u(0) -#define M33_CIDR2_PRMBL_2_ACCESS "RO" -// ============================================================================= -// Register : M33_CIDR3 -// Description : CoreSight Component ID3 -#define M33_CIDR3_OFFSET _u(0x00042ffc) -#define M33_CIDR3_BITS _u(0x000000ff) -#define M33_CIDR3_RESET _u(0x000000b1) -// ----------------------------------------------------------------------------- -// Field : M33_CIDR3_PRMBL_3 -// Description : Preamble[3]. Contains bits[31:24] of the component -// identification code. -#define M33_CIDR3_PRMBL_3_RESET _u(0xb1) -#define M33_CIDR3_PRMBL_3_BITS _u(0x000000ff) -#define M33_CIDR3_PRMBL_3_MSB _u(7) -#define M33_CIDR3_PRMBL_3_LSB _u(0) -#define M33_CIDR3_PRMBL_3_ACCESS "RO" -// ============================================================================= -#endif // _HARDWARE_REGS_M33_H - diff --git a/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/m33_eppb.h b/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/m33_eppb.h deleted file mode 100644 index 93b5143b2c..0000000000 --- a/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/m33_eppb.h +++ /dev/null @@ -1,80 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -// ============================================================================= -// Register block : M33_EPPB -// Version : 1 -// Bus type : apb -// Description : Cortex-M33 EPPB vendor register block for RP2350 -// ============================================================================= -#ifndef _HARDWARE_REGS_M33_EPPB_H -#define _HARDWARE_REGS_M33_EPPB_H -// ============================================================================= -// Register : M33_EPPB_NMI_MASK0 -// Description : NMI mask for IRQs 0 through 31. This register is core-local, -// and is reset by a processor warm reset. -#define M33_EPPB_NMI_MASK0_OFFSET _u(0x00000000) -#define M33_EPPB_NMI_MASK0_BITS _u(0xffffffff) -#define M33_EPPB_NMI_MASK0_RESET _u(0x00000000) -#define M33_EPPB_NMI_MASK0_MSB _u(31) -#define M33_EPPB_NMI_MASK0_LSB _u(0) -#define M33_EPPB_NMI_MASK0_ACCESS "RW" -// ============================================================================= -// Register : M33_EPPB_NMI_MASK1 -// Description : NMI mask for IRQs 0 though 51. This register is core-local, and -// is reset by a processor warm reset. -#define M33_EPPB_NMI_MASK1_OFFSET _u(0x00000004) -#define M33_EPPB_NMI_MASK1_BITS _u(0x000fffff) -#define M33_EPPB_NMI_MASK1_RESET _u(0x00000000) -#define M33_EPPB_NMI_MASK1_MSB _u(19) -#define M33_EPPB_NMI_MASK1_LSB _u(0) -#define M33_EPPB_NMI_MASK1_ACCESS "RW" -// ============================================================================= -// Register : M33_EPPB_SLEEPCTRL -// Description : Nonstandard sleep control register -#define M33_EPPB_SLEEPCTRL_OFFSET _u(0x00000008) -#define M33_EPPB_SLEEPCTRL_BITS _u(0x00000007) -#define M33_EPPB_SLEEPCTRL_RESET _u(0x00000002) -// ----------------------------------------------------------------------------- -// Field : M33_EPPB_SLEEPCTRL_WICENACK -// Description : Status signal from the processor's interrupt controller. -// Changes to WICENREQ are eventually reflected in WICENACK. -#define M33_EPPB_SLEEPCTRL_WICENACK_RESET _u(0x0) -#define M33_EPPB_SLEEPCTRL_WICENACK_BITS _u(0x00000004) -#define M33_EPPB_SLEEPCTRL_WICENACK_MSB _u(2) -#define M33_EPPB_SLEEPCTRL_WICENACK_LSB _u(2) -#define M33_EPPB_SLEEPCTRL_WICENACK_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : M33_EPPB_SLEEPCTRL_WICENREQ -// Description : Request that the next processor deep sleep is a WIC sleep. -// After setting this bit, before sleeping, poll WICENACK to -// ensure the processor interrupt controller has acknowledged the -// change. -#define M33_EPPB_SLEEPCTRL_WICENREQ_RESET _u(0x1) -#define M33_EPPB_SLEEPCTRL_WICENREQ_BITS _u(0x00000002) -#define M33_EPPB_SLEEPCTRL_WICENREQ_MSB _u(1) -#define M33_EPPB_SLEEPCTRL_WICENREQ_LSB _u(1) -#define M33_EPPB_SLEEPCTRL_WICENREQ_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : M33_EPPB_SLEEPCTRL_LIGHT_SLEEP -// Description : By default, any processor sleep will deassert the system-level -// clock request. Reenabling the clocks incurs 5 cycles of -// additional latency on wakeup. -// -// Setting LIGHT_SLEEP to 1 keeps the clock request asserted -// during a normal sleep (Arm SCR.SLEEPDEEP = 0), for faster -// wakeup. Processor deep sleep (Arm SCR.SLEEPDEEP = 1) is not -// affected, and will always deassert the system-level clock -// request. -#define M33_EPPB_SLEEPCTRL_LIGHT_SLEEP_RESET _u(0x0) -#define M33_EPPB_SLEEPCTRL_LIGHT_SLEEP_BITS _u(0x00000001) -#define M33_EPPB_SLEEPCTRL_LIGHT_SLEEP_MSB _u(0) -#define M33_EPPB_SLEEPCTRL_LIGHT_SLEEP_LSB _u(0) -#define M33_EPPB_SLEEPCTRL_LIGHT_SLEEP_ACCESS "RW" -// ============================================================================= -#endif // _HARDWARE_REGS_M33_EPPB_H - diff --git a/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/otp.h b/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/otp.h deleted file mode 100644 index cd9c6e85e2..0000000000 --- a/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/otp.h +++ /dev/null @@ -1,3467 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -// ============================================================================= -// Register block : OTP -// Version : 1 -// Bus type : apb -// Description : SNPS OTP control IF (SBPI and RPi wrapper control) -// ============================================================================= -#ifndef _HARDWARE_REGS_OTP_H -#define _HARDWARE_REGS_OTP_H -// ============================================================================= -// Register : OTP_SW_LOCK0 -// Description : Software lock register for page 0. -// -// Locks are initialised from the OTP lock pages at reset. This -// register can be written to further advance the lock state of -// each page (until next reset), and read to check the current -// lock state of a page. -#define OTP_SW_LOCK0_OFFSET _u(0x00000000) -#define OTP_SW_LOCK0_BITS _u(0x0000000f) -#define OTP_SW_LOCK0_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : OTP_SW_LOCK0_NSEC -// Description : Non-secure lock status. Writes are OR'd with the current value. -// 0x0 -> read_write -// 0x1 -> read_only -// 0x3 -> inaccessible -#define OTP_SW_LOCK0_NSEC_RESET "-" -#define OTP_SW_LOCK0_NSEC_BITS _u(0x0000000c) -#define OTP_SW_LOCK0_NSEC_MSB _u(3) -#define OTP_SW_LOCK0_NSEC_LSB _u(2) -#define OTP_SW_LOCK0_NSEC_ACCESS "RW" -#define OTP_SW_LOCK0_NSEC_VALUE_READ_WRITE _u(0x0) -#define OTP_SW_LOCK0_NSEC_VALUE_READ_ONLY _u(0x1) -#define OTP_SW_LOCK0_NSEC_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_SW_LOCK0_SEC -// Description : Secure lock status. Writes are OR'd with the current value. -// This field is read-only to Non-secure code. -// 0x0 -> read_write -// 0x1 -> read_only -// 0x3 -> inaccessible -#define OTP_SW_LOCK0_SEC_RESET "-" -#define OTP_SW_LOCK0_SEC_BITS _u(0x00000003) -#define OTP_SW_LOCK0_SEC_MSB _u(1) -#define OTP_SW_LOCK0_SEC_LSB _u(0) -#define OTP_SW_LOCK0_SEC_ACCESS "RW" -#define OTP_SW_LOCK0_SEC_VALUE_READ_WRITE _u(0x0) -#define OTP_SW_LOCK0_SEC_VALUE_READ_ONLY _u(0x1) -#define OTP_SW_LOCK0_SEC_VALUE_INACCESSIBLE _u(0x3) -// ============================================================================= -// Register : OTP_SW_LOCK1 -// Description : Software lock register for page 1. -// -// Locks are initialised from the OTP lock pages at reset. This -// register can be written to further advance the lock state of -// each page (until next reset), and read to check the current -// lock state of a page. -#define OTP_SW_LOCK1_OFFSET _u(0x00000004) -#define OTP_SW_LOCK1_BITS _u(0x0000000f) -#define OTP_SW_LOCK1_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : OTP_SW_LOCK1_NSEC -// Description : Non-secure lock status. Writes are OR'd with the current value. -// 0x0 -> read_write -// 0x1 -> read_only -// 0x3 -> inaccessible -#define OTP_SW_LOCK1_NSEC_RESET "-" -#define OTP_SW_LOCK1_NSEC_BITS _u(0x0000000c) -#define OTP_SW_LOCK1_NSEC_MSB _u(3) -#define OTP_SW_LOCK1_NSEC_LSB _u(2) -#define OTP_SW_LOCK1_NSEC_ACCESS "RW" -#define OTP_SW_LOCK1_NSEC_VALUE_READ_WRITE _u(0x0) -#define OTP_SW_LOCK1_NSEC_VALUE_READ_ONLY _u(0x1) -#define OTP_SW_LOCK1_NSEC_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_SW_LOCK1_SEC -// Description : Secure lock status. Writes are OR'd with the current value. -// This field is read-only to Non-secure code. -// 0x0 -> read_write -// 0x1 -> read_only -// 0x3 -> inaccessible -#define OTP_SW_LOCK1_SEC_RESET "-" -#define OTP_SW_LOCK1_SEC_BITS _u(0x00000003) -#define OTP_SW_LOCK1_SEC_MSB _u(1) -#define OTP_SW_LOCK1_SEC_LSB _u(0) -#define OTP_SW_LOCK1_SEC_ACCESS "RW" -#define OTP_SW_LOCK1_SEC_VALUE_READ_WRITE _u(0x0) -#define OTP_SW_LOCK1_SEC_VALUE_READ_ONLY _u(0x1) -#define OTP_SW_LOCK1_SEC_VALUE_INACCESSIBLE _u(0x3) -// ============================================================================= -// Register : OTP_SW_LOCK2 -// Description : Software lock register for page 2. -// -// Locks are initialised from the OTP lock pages at reset. This -// register can be written to further advance the lock state of -// each page (until next reset), and read to check the current -// lock state of a page. -#define OTP_SW_LOCK2_OFFSET _u(0x00000008) -#define OTP_SW_LOCK2_BITS _u(0x0000000f) -#define OTP_SW_LOCK2_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : OTP_SW_LOCK2_NSEC -// Description : Non-secure lock status. Writes are OR'd with the current value. -// 0x0 -> read_write -// 0x1 -> read_only -// 0x3 -> inaccessible -#define OTP_SW_LOCK2_NSEC_RESET "-" -#define OTP_SW_LOCK2_NSEC_BITS _u(0x0000000c) -#define OTP_SW_LOCK2_NSEC_MSB _u(3) -#define OTP_SW_LOCK2_NSEC_LSB _u(2) -#define OTP_SW_LOCK2_NSEC_ACCESS "RW" -#define OTP_SW_LOCK2_NSEC_VALUE_READ_WRITE _u(0x0) -#define OTP_SW_LOCK2_NSEC_VALUE_READ_ONLY _u(0x1) -#define OTP_SW_LOCK2_NSEC_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_SW_LOCK2_SEC -// Description : Secure lock status. Writes are OR'd with the current value. -// This field is read-only to Non-secure code. -// 0x0 -> read_write -// 0x1 -> read_only -// 0x3 -> inaccessible -#define OTP_SW_LOCK2_SEC_RESET "-" -#define OTP_SW_LOCK2_SEC_BITS _u(0x00000003) -#define OTP_SW_LOCK2_SEC_MSB _u(1) -#define OTP_SW_LOCK2_SEC_LSB _u(0) -#define OTP_SW_LOCK2_SEC_ACCESS "RW" -#define OTP_SW_LOCK2_SEC_VALUE_READ_WRITE _u(0x0) -#define OTP_SW_LOCK2_SEC_VALUE_READ_ONLY _u(0x1) -#define OTP_SW_LOCK2_SEC_VALUE_INACCESSIBLE _u(0x3) -// ============================================================================= -// Register : OTP_SW_LOCK3 -// Description : Software lock register for page 3. -// -// Locks are initialised from the OTP lock pages at reset. This -// register can be written to further advance the lock state of -// each page (until next reset), and read to check the current -// lock state of a page. -#define OTP_SW_LOCK3_OFFSET _u(0x0000000c) -#define OTP_SW_LOCK3_BITS _u(0x0000000f) -#define OTP_SW_LOCK3_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : OTP_SW_LOCK3_NSEC -// Description : Non-secure lock status. Writes are OR'd with the current value. -// 0x0 -> read_write -// 0x1 -> read_only -// 0x3 -> inaccessible -#define OTP_SW_LOCK3_NSEC_RESET "-" -#define OTP_SW_LOCK3_NSEC_BITS _u(0x0000000c) -#define OTP_SW_LOCK3_NSEC_MSB _u(3) -#define OTP_SW_LOCK3_NSEC_LSB _u(2) -#define OTP_SW_LOCK3_NSEC_ACCESS "RW" -#define OTP_SW_LOCK3_NSEC_VALUE_READ_WRITE _u(0x0) -#define OTP_SW_LOCK3_NSEC_VALUE_READ_ONLY _u(0x1) -#define OTP_SW_LOCK3_NSEC_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_SW_LOCK3_SEC -// Description : Secure lock status. Writes are OR'd with the current value. -// This field is read-only to Non-secure code. -// 0x0 -> read_write -// 0x1 -> read_only -// 0x3 -> inaccessible -#define OTP_SW_LOCK3_SEC_RESET "-" -#define OTP_SW_LOCK3_SEC_BITS _u(0x00000003) -#define OTP_SW_LOCK3_SEC_MSB _u(1) -#define OTP_SW_LOCK3_SEC_LSB _u(0) -#define OTP_SW_LOCK3_SEC_ACCESS "RW" -#define OTP_SW_LOCK3_SEC_VALUE_READ_WRITE _u(0x0) -#define OTP_SW_LOCK3_SEC_VALUE_READ_ONLY _u(0x1) -#define OTP_SW_LOCK3_SEC_VALUE_INACCESSIBLE _u(0x3) -// ============================================================================= -// Register : OTP_SW_LOCK4 -// Description : Software lock register for page 4. -// -// Locks are initialised from the OTP lock pages at reset. This -// register can be written to further advance the lock state of -// each page (until next reset), and read to check the current -// lock state of a page. -#define OTP_SW_LOCK4_OFFSET _u(0x00000010) -#define OTP_SW_LOCK4_BITS _u(0x0000000f) -#define OTP_SW_LOCK4_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : OTP_SW_LOCK4_NSEC -// Description : Non-secure lock status. Writes are OR'd with the current value. -// 0x0 -> read_write -// 0x1 -> read_only -// 0x3 -> inaccessible -#define OTP_SW_LOCK4_NSEC_RESET "-" -#define OTP_SW_LOCK4_NSEC_BITS _u(0x0000000c) -#define OTP_SW_LOCK4_NSEC_MSB _u(3) -#define OTP_SW_LOCK4_NSEC_LSB _u(2) -#define OTP_SW_LOCK4_NSEC_ACCESS "RW" -#define OTP_SW_LOCK4_NSEC_VALUE_READ_WRITE _u(0x0) -#define OTP_SW_LOCK4_NSEC_VALUE_READ_ONLY _u(0x1) -#define OTP_SW_LOCK4_NSEC_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_SW_LOCK4_SEC -// Description : Secure lock status. Writes are OR'd with the current value. -// This field is read-only to Non-secure code. -// 0x0 -> read_write -// 0x1 -> read_only -// 0x3 -> inaccessible -#define OTP_SW_LOCK4_SEC_RESET "-" -#define OTP_SW_LOCK4_SEC_BITS _u(0x00000003) -#define OTP_SW_LOCK4_SEC_MSB _u(1) -#define OTP_SW_LOCK4_SEC_LSB _u(0) -#define OTP_SW_LOCK4_SEC_ACCESS "RW" -#define OTP_SW_LOCK4_SEC_VALUE_READ_WRITE _u(0x0) -#define OTP_SW_LOCK4_SEC_VALUE_READ_ONLY _u(0x1) -#define OTP_SW_LOCK4_SEC_VALUE_INACCESSIBLE _u(0x3) -// ============================================================================= -// Register : OTP_SW_LOCK5 -// Description : Software lock register for page 5. -// -// Locks are initialised from the OTP lock pages at reset. This -// register can be written to further advance the lock state of -// each page (until next reset), and read to check the current -// lock state of a page. -#define OTP_SW_LOCK5_OFFSET _u(0x00000014) -#define OTP_SW_LOCK5_BITS _u(0x0000000f) -#define OTP_SW_LOCK5_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : OTP_SW_LOCK5_NSEC -// Description : Non-secure lock status. Writes are OR'd with the current value. -// 0x0 -> read_write -// 0x1 -> read_only -// 0x3 -> inaccessible -#define OTP_SW_LOCK5_NSEC_RESET "-" -#define OTP_SW_LOCK5_NSEC_BITS _u(0x0000000c) -#define OTP_SW_LOCK5_NSEC_MSB _u(3) -#define OTP_SW_LOCK5_NSEC_LSB _u(2) -#define OTP_SW_LOCK5_NSEC_ACCESS "RW" -#define OTP_SW_LOCK5_NSEC_VALUE_READ_WRITE _u(0x0) -#define OTP_SW_LOCK5_NSEC_VALUE_READ_ONLY _u(0x1) -#define OTP_SW_LOCK5_NSEC_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_SW_LOCK5_SEC -// Description : Secure lock status. Writes are OR'd with the current value. -// This field is read-only to Non-secure code. -// 0x0 -> read_write -// 0x1 -> read_only -// 0x3 -> inaccessible -#define OTP_SW_LOCK5_SEC_RESET "-" -#define OTP_SW_LOCK5_SEC_BITS _u(0x00000003) -#define OTP_SW_LOCK5_SEC_MSB _u(1) -#define OTP_SW_LOCK5_SEC_LSB _u(0) -#define OTP_SW_LOCK5_SEC_ACCESS "RW" -#define OTP_SW_LOCK5_SEC_VALUE_READ_WRITE _u(0x0) -#define OTP_SW_LOCK5_SEC_VALUE_READ_ONLY _u(0x1) -#define OTP_SW_LOCK5_SEC_VALUE_INACCESSIBLE _u(0x3) -// ============================================================================= -// Register : OTP_SW_LOCK6 -// Description : Software lock register for page 6. -// -// Locks are initialised from the OTP lock pages at reset. This -// register can be written to further advance the lock state of -// each page (until next reset), and read to check the current -// lock state of a page. -#define OTP_SW_LOCK6_OFFSET _u(0x00000018) -#define OTP_SW_LOCK6_BITS _u(0x0000000f) -#define OTP_SW_LOCK6_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : OTP_SW_LOCK6_NSEC -// Description : Non-secure lock status. Writes are OR'd with the current value. -// 0x0 -> read_write -// 0x1 -> read_only -// 0x3 -> inaccessible -#define OTP_SW_LOCK6_NSEC_RESET "-" -#define OTP_SW_LOCK6_NSEC_BITS _u(0x0000000c) -#define OTP_SW_LOCK6_NSEC_MSB _u(3) -#define OTP_SW_LOCK6_NSEC_LSB _u(2) -#define OTP_SW_LOCK6_NSEC_ACCESS "RW" -#define OTP_SW_LOCK6_NSEC_VALUE_READ_WRITE _u(0x0) -#define OTP_SW_LOCK6_NSEC_VALUE_READ_ONLY _u(0x1) -#define OTP_SW_LOCK6_NSEC_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_SW_LOCK6_SEC -// Description : Secure lock status. Writes are OR'd with the current value. -// This field is read-only to Non-secure code. -// 0x0 -> read_write -// 0x1 -> read_only -// 0x3 -> inaccessible -#define OTP_SW_LOCK6_SEC_RESET "-" -#define OTP_SW_LOCK6_SEC_BITS _u(0x00000003) -#define OTP_SW_LOCK6_SEC_MSB _u(1) -#define OTP_SW_LOCK6_SEC_LSB _u(0) -#define OTP_SW_LOCK6_SEC_ACCESS "RW" -#define OTP_SW_LOCK6_SEC_VALUE_READ_WRITE _u(0x0) -#define OTP_SW_LOCK6_SEC_VALUE_READ_ONLY _u(0x1) -#define OTP_SW_LOCK6_SEC_VALUE_INACCESSIBLE _u(0x3) -// ============================================================================= -// Register : OTP_SW_LOCK7 -// Description : Software lock register for page 7. -// -// Locks are initialised from the OTP lock pages at reset. This -// register can be written to further advance the lock state of -// each page (until next reset), and read to check the current -// lock state of a page. -#define OTP_SW_LOCK7_OFFSET _u(0x0000001c) -#define OTP_SW_LOCK7_BITS _u(0x0000000f) -#define OTP_SW_LOCK7_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : OTP_SW_LOCK7_NSEC -// Description : Non-secure lock status. Writes are OR'd with the current value. -// 0x0 -> read_write -// 0x1 -> read_only -// 0x3 -> inaccessible -#define OTP_SW_LOCK7_NSEC_RESET "-" -#define OTP_SW_LOCK7_NSEC_BITS _u(0x0000000c) -#define OTP_SW_LOCK7_NSEC_MSB _u(3) -#define OTP_SW_LOCK7_NSEC_LSB _u(2) -#define OTP_SW_LOCK7_NSEC_ACCESS "RW" -#define OTP_SW_LOCK7_NSEC_VALUE_READ_WRITE _u(0x0) -#define OTP_SW_LOCK7_NSEC_VALUE_READ_ONLY _u(0x1) -#define OTP_SW_LOCK7_NSEC_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_SW_LOCK7_SEC -// Description : Secure lock status. Writes are OR'd with the current value. -// This field is read-only to Non-secure code. -// 0x0 -> read_write -// 0x1 -> read_only -// 0x3 -> inaccessible -#define OTP_SW_LOCK7_SEC_RESET "-" -#define OTP_SW_LOCK7_SEC_BITS _u(0x00000003) -#define OTP_SW_LOCK7_SEC_MSB _u(1) -#define OTP_SW_LOCK7_SEC_LSB _u(0) -#define OTP_SW_LOCK7_SEC_ACCESS "RW" -#define OTP_SW_LOCK7_SEC_VALUE_READ_WRITE _u(0x0) -#define OTP_SW_LOCK7_SEC_VALUE_READ_ONLY _u(0x1) -#define OTP_SW_LOCK7_SEC_VALUE_INACCESSIBLE _u(0x3) -// ============================================================================= -// Register : OTP_SW_LOCK8 -// Description : Software lock register for page 8. -// -// Locks are initialised from the OTP lock pages at reset. This -// register can be written to further advance the lock state of -// each page (until next reset), and read to check the current -// lock state of a page. -#define OTP_SW_LOCK8_OFFSET _u(0x00000020) -#define OTP_SW_LOCK8_BITS _u(0x0000000f) -#define OTP_SW_LOCK8_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : OTP_SW_LOCK8_NSEC -// Description : Non-secure lock status. Writes are OR'd with the current value. -// 0x0 -> read_write -// 0x1 -> read_only -// 0x3 -> inaccessible -#define OTP_SW_LOCK8_NSEC_RESET "-" -#define OTP_SW_LOCK8_NSEC_BITS _u(0x0000000c) -#define OTP_SW_LOCK8_NSEC_MSB _u(3) -#define OTP_SW_LOCK8_NSEC_LSB _u(2) -#define OTP_SW_LOCK8_NSEC_ACCESS "RW" -#define OTP_SW_LOCK8_NSEC_VALUE_READ_WRITE _u(0x0) -#define OTP_SW_LOCK8_NSEC_VALUE_READ_ONLY _u(0x1) -#define OTP_SW_LOCK8_NSEC_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_SW_LOCK8_SEC -// Description : Secure lock status. Writes are OR'd with the current value. -// This field is read-only to Non-secure code. -// 0x0 -> read_write -// 0x1 -> read_only -// 0x3 -> inaccessible -#define OTP_SW_LOCK8_SEC_RESET "-" -#define OTP_SW_LOCK8_SEC_BITS _u(0x00000003) -#define OTP_SW_LOCK8_SEC_MSB _u(1) -#define OTP_SW_LOCK8_SEC_LSB _u(0) -#define OTP_SW_LOCK8_SEC_ACCESS "RW" -#define OTP_SW_LOCK8_SEC_VALUE_READ_WRITE _u(0x0) -#define OTP_SW_LOCK8_SEC_VALUE_READ_ONLY _u(0x1) -#define OTP_SW_LOCK8_SEC_VALUE_INACCESSIBLE _u(0x3) -// ============================================================================= -// Register : OTP_SW_LOCK9 -// Description : Software lock register for page 9. -// -// Locks are initialised from the OTP lock pages at reset. This -// register can be written to further advance the lock state of -// each page (until next reset), and read to check the current -// lock state of a page. -#define OTP_SW_LOCK9_OFFSET _u(0x00000024) -#define OTP_SW_LOCK9_BITS _u(0x0000000f) -#define OTP_SW_LOCK9_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : OTP_SW_LOCK9_NSEC -// Description : Non-secure lock status. Writes are OR'd with the current value. -// 0x0 -> read_write -// 0x1 -> read_only -// 0x3 -> inaccessible -#define OTP_SW_LOCK9_NSEC_RESET "-" -#define OTP_SW_LOCK9_NSEC_BITS _u(0x0000000c) -#define OTP_SW_LOCK9_NSEC_MSB _u(3) -#define OTP_SW_LOCK9_NSEC_LSB _u(2) -#define OTP_SW_LOCK9_NSEC_ACCESS "RW" -#define OTP_SW_LOCK9_NSEC_VALUE_READ_WRITE _u(0x0) -#define OTP_SW_LOCK9_NSEC_VALUE_READ_ONLY _u(0x1) -#define OTP_SW_LOCK9_NSEC_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_SW_LOCK9_SEC -// Description : Secure lock status. Writes are OR'd with the current value. -// This field is read-only to Non-secure code. -// 0x0 -> read_write -// 0x1 -> read_only -// 0x3 -> inaccessible -#define OTP_SW_LOCK9_SEC_RESET "-" -#define OTP_SW_LOCK9_SEC_BITS _u(0x00000003) -#define OTP_SW_LOCK9_SEC_MSB _u(1) -#define OTP_SW_LOCK9_SEC_LSB _u(0) -#define OTP_SW_LOCK9_SEC_ACCESS "RW" -#define OTP_SW_LOCK9_SEC_VALUE_READ_WRITE _u(0x0) -#define OTP_SW_LOCK9_SEC_VALUE_READ_ONLY _u(0x1) -#define OTP_SW_LOCK9_SEC_VALUE_INACCESSIBLE _u(0x3) -// ============================================================================= -// Register : OTP_SW_LOCK10 -// Description : Software lock register for page 10. -// -// Locks are initialised from the OTP lock pages at reset. This -// register can be written to further advance the lock state of -// each page (until next reset), and read to check the current -// lock state of a page. -#define OTP_SW_LOCK10_OFFSET _u(0x00000028) -#define OTP_SW_LOCK10_BITS _u(0x0000000f) -#define OTP_SW_LOCK10_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : OTP_SW_LOCK10_NSEC -// Description : Non-secure lock status. Writes are OR'd with the current value. -// 0x0 -> read_write -// 0x1 -> read_only -// 0x3 -> inaccessible -#define OTP_SW_LOCK10_NSEC_RESET "-" -#define OTP_SW_LOCK10_NSEC_BITS _u(0x0000000c) -#define OTP_SW_LOCK10_NSEC_MSB _u(3) -#define OTP_SW_LOCK10_NSEC_LSB _u(2) -#define OTP_SW_LOCK10_NSEC_ACCESS "RW" -#define OTP_SW_LOCK10_NSEC_VALUE_READ_WRITE _u(0x0) -#define OTP_SW_LOCK10_NSEC_VALUE_READ_ONLY _u(0x1) -#define OTP_SW_LOCK10_NSEC_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_SW_LOCK10_SEC -// Description : Secure lock status. Writes are OR'd with the current value. -// This field is read-only to Non-secure code. -// 0x0 -> read_write -// 0x1 -> read_only -// 0x3 -> inaccessible -#define OTP_SW_LOCK10_SEC_RESET "-" -#define OTP_SW_LOCK10_SEC_BITS _u(0x00000003) -#define OTP_SW_LOCK10_SEC_MSB _u(1) -#define OTP_SW_LOCK10_SEC_LSB _u(0) -#define OTP_SW_LOCK10_SEC_ACCESS "RW" -#define OTP_SW_LOCK10_SEC_VALUE_READ_WRITE _u(0x0) -#define OTP_SW_LOCK10_SEC_VALUE_READ_ONLY _u(0x1) -#define OTP_SW_LOCK10_SEC_VALUE_INACCESSIBLE _u(0x3) -// ============================================================================= -// Register : OTP_SW_LOCK11 -// Description : Software lock register for page 11. -// -// Locks are initialised from the OTP lock pages at reset. This -// register can be written to further advance the lock state of -// each page (until next reset), and read to check the current -// lock state of a page. -#define OTP_SW_LOCK11_OFFSET _u(0x0000002c) -#define OTP_SW_LOCK11_BITS _u(0x0000000f) -#define OTP_SW_LOCK11_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : OTP_SW_LOCK11_NSEC -// Description : Non-secure lock status. Writes are OR'd with the current value. -// 0x0 -> read_write -// 0x1 -> read_only -// 0x3 -> inaccessible -#define OTP_SW_LOCK11_NSEC_RESET "-" -#define OTP_SW_LOCK11_NSEC_BITS _u(0x0000000c) -#define OTP_SW_LOCK11_NSEC_MSB _u(3) -#define OTP_SW_LOCK11_NSEC_LSB _u(2) -#define OTP_SW_LOCK11_NSEC_ACCESS "RW" -#define OTP_SW_LOCK11_NSEC_VALUE_READ_WRITE _u(0x0) -#define OTP_SW_LOCK11_NSEC_VALUE_READ_ONLY _u(0x1) -#define OTP_SW_LOCK11_NSEC_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_SW_LOCK11_SEC -// Description : Secure lock status. Writes are OR'd with the current value. -// This field is read-only to Non-secure code. -// 0x0 -> read_write -// 0x1 -> read_only -// 0x3 -> inaccessible -#define OTP_SW_LOCK11_SEC_RESET "-" -#define OTP_SW_LOCK11_SEC_BITS _u(0x00000003) -#define OTP_SW_LOCK11_SEC_MSB _u(1) -#define OTP_SW_LOCK11_SEC_LSB _u(0) -#define OTP_SW_LOCK11_SEC_ACCESS "RW" -#define OTP_SW_LOCK11_SEC_VALUE_READ_WRITE _u(0x0) -#define OTP_SW_LOCK11_SEC_VALUE_READ_ONLY _u(0x1) -#define OTP_SW_LOCK11_SEC_VALUE_INACCESSIBLE _u(0x3) -// ============================================================================= -// Register : OTP_SW_LOCK12 -// Description : Software lock register for page 12. -// -// Locks are initialised from the OTP lock pages at reset. This -// register can be written to further advance the lock state of -// each page (until next reset), and read to check the current -// lock state of a page. -#define OTP_SW_LOCK12_OFFSET _u(0x00000030) -#define OTP_SW_LOCK12_BITS _u(0x0000000f) -#define OTP_SW_LOCK12_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : OTP_SW_LOCK12_NSEC -// Description : Non-secure lock status. Writes are OR'd with the current value. -// 0x0 -> read_write -// 0x1 -> read_only -// 0x3 -> inaccessible -#define OTP_SW_LOCK12_NSEC_RESET "-" -#define OTP_SW_LOCK12_NSEC_BITS _u(0x0000000c) -#define OTP_SW_LOCK12_NSEC_MSB _u(3) -#define OTP_SW_LOCK12_NSEC_LSB _u(2) -#define OTP_SW_LOCK12_NSEC_ACCESS "RW" -#define OTP_SW_LOCK12_NSEC_VALUE_READ_WRITE _u(0x0) -#define OTP_SW_LOCK12_NSEC_VALUE_READ_ONLY _u(0x1) -#define OTP_SW_LOCK12_NSEC_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_SW_LOCK12_SEC -// Description : Secure lock status. Writes are OR'd with the current value. -// This field is read-only to Non-secure code. -// 0x0 -> read_write -// 0x1 -> read_only -// 0x3 -> inaccessible -#define OTP_SW_LOCK12_SEC_RESET "-" -#define OTP_SW_LOCK12_SEC_BITS _u(0x00000003) -#define OTP_SW_LOCK12_SEC_MSB _u(1) -#define OTP_SW_LOCK12_SEC_LSB _u(0) -#define OTP_SW_LOCK12_SEC_ACCESS "RW" -#define OTP_SW_LOCK12_SEC_VALUE_READ_WRITE _u(0x0) -#define OTP_SW_LOCK12_SEC_VALUE_READ_ONLY _u(0x1) -#define OTP_SW_LOCK12_SEC_VALUE_INACCESSIBLE _u(0x3) -// ============================================================================= -// Register : OTP_SW_LOCK13 -// Description : Software lock register for page 13. -// -// Locks are initialised from the OTP lock pages at reset. This -// register can be written to further advance the lock state of -// each page (until next reset), and read to check the current -// lock state of a page. -#define OTP_SW_LOCK13_OFFSET _u(0x00000034) -#define OTP_SW_LOCK13_BITS _u(0x0000000f) -#define OTP_SW_LOCK13_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : OTP_SW_LOCK13_NSEC -// Description : Non-secure lock status. Writes are OR'd with the current value. -// 0x0 -> read_write -// 0x1 -> read_only -// 0x3 -> inaccessible -#define OTP_SW_LOCK13_NSEC_RESET "-" -#define OTP_SW_LOCK13_NSEC_BITS _u(0x0000000c) -#define OTP_SW_LOCK13_NSEC_MSB _u(3) -#define OTP_SW_LOCK13_NSEC_LSB _u(2) -#define OTP_SW_LOCK13_NSEC_ACCESS "RW" -#define OTP_SW_LOCK13_NSEC_VALUE_READ_WRITE _u(0x0) -#define OTP_SW_LOCK13_NSEC_VALUE_READ_ONLY _u(0x1) -#define OTP_SW_LOCK13_NSEC_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_SW_LOCK13_SEC -// Description : Secure lock status. Writes are OR'd with the current value. -// This field is read-only to Non-secure code. -// 0x0 -> read_write -// 0x1 -> read_only -// 0x3 -> inaccessible -#define OTP_SW_LOCK13_SEC_RESET "-" -#define OTP_SW_LOCK13_SEC_BITS _u(0x00000003) -#define OTP_SW_LOCK13_SEC_MSB _u(1) -#define OTP_SW_LOCK13_SEC_LSB _u(0) -#define OTP_SW_LOCK13_SEC_ACCESS "RW" -#define OTP_SW_LOCK13_SEC_VALUE_READ_WRITE _u(0x0) -#define OTP_SW_LOCK13_SEC_VALUE_READ_ONLY _u(0x1) -#define OTP_SW_LOCK13_SEC_VALUE_INACCESSIBLE _u(0x3) -// ============================================================================= -// Register : OTP_SW_LOCK14 -// Description : Software lock register for page 14. -// -// Locks are initialised from the OTP lock pages at reset. This -// register can be written to further advance the lock state of -// each page (until next reset), and read to check the current -// lock state of a page. -#define OTP_SW_LOCK14_OFFSET _u(0x00000038) -#define OTP_SW_LOCK14_BITS _u(0x0000000f) -#define OTP_SW_LOCK14_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : OTP_SW_LOCK14_NSEC -// Description : Non-secure lock status. Writes are OR'd with the current value. -// 0x0 -> read_write -// 0x1 -> read_only -// 0x3 -> inaccessible -#define OTP_SW_LOCK14_NSEC_RESET "-" -#define OTP_SW_LOCK14_NSEC_BITS _u(0x0000000c) -#define OTP_SW_LOCK14_NSEC_MSB _u(3) -#define OTP_SW_LOCK14_NSEC_LSB _u(2) -#define OTP_SW_LOCK14_NSEC_ACCESS "RW" -#define OTP_SW_LOCK14_NSEC_VALUE_READ_WRITE _u(0x0) -#define OTP_SW_LOCK14_NSEC_VALUE_READ_ONLY _u(0x1) -#define OTP_SW_LOCK14_NSEC_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_SW_LOCK14_SEC -// Description : Secure lock status. Writes are OR'd with the current value. -// This field is read-only to Non-secure code. -// 0x0 -> read_write -// 0x1 -> read_only -// 0x3 -> inaccessible -#define OTP_SW_LOCK14_SEC_RESET "-" -#define OTP_SW_LOCK14_SEC_BITS _u(0x00000003) -#define OTP_SW_LOCK14_SEC_MSB _u(1) -#define OTP_SW_LOCK14_SEC_LSB _u(0) -#define OTP_SW_LOCK14_SEC_ACCESS "RW" -#define OTP_SW_LOCK14_SEC_VALUE_READ_WRITE _u(0x0) -#define OTP_SW_LOCK14_SEC_VALUE_READ_ONLY _u(0x1) -#define OTP_SW_LOCK14_SEC_VALUE_INACCESSIBLE _u(0x3) -// ============================================================================= -// Register : OTP_SW_LOCK15 -// Description : Software lock register for page 15. -// -// Locks are initialised from the OTP lock pages at reset. This -// register can be written to further advance the lock state of -// each page (until next reset), and read to check the current -// lock state of a page. -#define OTP_SW_LOCK15_OFFSET _u(0x0000003c) -#define OTP_SW_LOCK15_BITS _u(0x0000000f) -#define OTP_SW_LOCK15_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : OTP_SW_LOCK15_NSEC -// Description : Non-secure lock status. Writes are OR'd with the current value. -// 0x0 -> read_write -// 0x1 -> read_only -// 0x3 -> inaccessible -#define OTP_SW_LOCK15_NSEC_RESET "-" -#define OTP_SW_LOCK15_NSEC_BITS _u(0x0000000c) -#define OTP_SW_LOCK15_NSEC_MSB _u(3) -#define OTP_SW_LOCK15_NSEC_LSB _u(2) -#define OTP_SW_LOCK15_NSEC_ACCESS "RW" -#define OTP_SW_LOCK15_NSEC_VALUE_READ_WRITE _u(0x0) -#define OTP_SW_LOCK15_NSEC_VALUE_READ_ONLY _u(0x1) -#define OTP_SW_LOCK15_NSEC_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_SW_LOCK15_SEC -// Description : Secure lock status. Writes are OR'd with the current value. -// This field is read-only to Non-secure code. -// 0x0 -> read_write -// 0x1 -> read_only -// 0x3 -> inaccessible -#define OTP_SW_LOCK15_SEC_RESET "-" -#define OTP_SW_LOCK15_SEC_BITS _u(0x00000003) -#define OTP_SW_LOCK15_SEC_MSB _u(1) -#define OTP_SW_LOCK15_SEC_LSB _u(0) -#define OTP_SW_LOCK15_SEC_ACCESS "RW" -#define OTP_SW_LOCK15_SEC_VALUE_READ_WRITE _u(0x0) -#define OTP_SW_LOCK15_SEC_VALUE_READ_ONLY _u(0x1) -#define OTP_SW_LOCK15_SEC_VALUE_INACCESSIBLE _u(0x3) -// ============================================================================= -// Register : OTP_SW_LOCK16 -// Description : Software lock register for page 16. -// -// Locks are initialised from the OTP lock pages at reset. This -// register can be written to further advance the lock state of -// each page (until next reset), and read to check the current -// lock state of a page. -#define OTP_SW_LOCK16_OFFSET _u(0x00000040) -#define OTP_SW_LOCK16_BITS _u(0x0000000f) -#define OTP_SW_LOCK16_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : OTP_SW_LOCK16_NSEC -// Description : Non-secure lock status. Writes are OR'd with the current value. -// 0x0 -> read_write -// 0x1 -> read_only -// 0x3 -> inaccessible -#define OTP_SW_LOCK16_NSEC_RESET "-" -#define OTP_SW_LOCK16_NSEC_BITS _u(0x0000000c) -#define OTP_SW_LOCK16_NSEC_MSB _u(3) -#define OTP_SW_LOCK16_NSEC_LSB _u(2) -#define OTP_SW_LOCK16_NSEC_ACCESS "RW" -#define OTP_SW_LOCK16_NSEC_VALUE_READ_WRITE _u(0x0) -#define OTP_SW_LOCK16_NSEC_VALUE_READ_ONLY _u(0x1) -#define OTP_SW_LOCK16_NSEC_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_SW_LOCK16_SEC -// Description : Secure lock status. Writes are OR'd with the current value. -// This field is read-only to Non-secure code. -// 0x0 -> read_write -// 0x1 -> read_only -// 0x3 -> inaccessible -#define OTP_SW_LOCK16_SEC_RESET "-" -#define OTP_SW_LOCK16_SEC_BITS _u(0x00000003) -#define OTP_SW_LOCK16_SEC_MSB _u(1) -#define OTP_SW_LOCK16_SEC_LSB _u(0) -#define OTP_SW_LOCK16_SEC_ACCESS "RW" -#define OTP_SW_LOCK16_SEC_VALUE_READ_WRITE _u(0x0) -#define OTP_SW_LOCK16_SEC_VALUE_READ_ONLY _u(0x1) -#define OTP_SW_LOCK16_SEC_VALUE_INACCESSIBLE _u(0x3) -// ============================================================================= -// Register : OTP_SW_LOCK17 -// Description : Software lock register for page 17. -// -// Locks are initialised from the OTP lock pages at reset. This -// register can be written to further advance the lock state of -// each page (until next reset), and read to check the current -// lock state of a page. -#define OTP_SW_LOCK17_OFFSET _u(0x00000044) -#define OTP_SW_LOCK17_BITS _u(0x0000000f) -#define OTP_SW_LOCK17_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : OTP_SW_LOCK17_NSEC -// Description : Non-secure lock status. Writes are OR'd with the current value. -// 0x0 -> read_write -// 0x1 -> read_only -// 0x3 -> inaccessible -#define OTP_SW_LOCK17_NSEC_RESET "-" -#define OTP_SW_LOCK17_NSEC_BITS _u(0x0000000c) -#define OTP_SW_LOCK17_NSEC_MSB _u(3) -#define OTP_SW_LOCK17_NSEC_LSB _u(2) -#define OTP_SW_LOCK17_NSEC_ACCESS "RW" -#define OTP_SW_LOCK17_NSEC_VALUE_READ_WRITE _u(0x0) -#define OTP_SW_LOCK17_NSEC_VALUE_READ_ONLY _u(0x1) -#define OTP_SW_LOCK17_NSEC_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_SW_LOCK17_SEC -// Description : Secure lock status. Writes are OR'd with the current value. -// This field is read-only to Non-secure code. -// 0x0 -> read_write -// 0x1 -> read_only -// 0x3 -> inaccessible -#define OTP_SW_LOCK17_SEC_RESET "-" -#define OTP_SW_LOCK17_SEC_BITS _u(0x00000003) -#define OTP_SW_LOCK17_SEC_MSB _u(1) -#define OTP_SW_LOCK17_SEC_LSB _u(0) -#define OTP_SW_LOCK17_SEC_ACCESS "RW" -#define OTP_SW_LOCK17_SEC_VALUE_READ_WRITE _u(0x0) -#define OTP_SW_LOCK17_SEC_VALUE_READ_ONLY _u(0x1) -#define OTP_SW_LOCK17_SEC_VALUE_INACCESSIBLE _u(0x3) -// ============================================================================= -// Register : OTP_SW_LOCK18 -// Description : Software lock register for page 18. -// -// Locks are initialised from the OTP lock pages at reset. This -// register can be written to further advance the lock state of -// each page (until next reset), and read to check the current -// lock state of a page. -#define OTP_SW_LOCK18_OFFSET _u(0x00000048) -#define OTP_SW_LOCK18_BITS _u(0x0000000f) -#define OTP_SW_LOCK18_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : OTP_SW_LOCK18_NSEC -// Description : Non-secure lock status. Writes are OR'd with the current value. -// 0x0 -> read_write -// 0x1 -> read_only -// 0x3 -> inaccessible -#define OTP_SW_LOCK18_NSEC_RESET "-" -#define OTP_SW_LOCK18_NSEC_BITS _u(0x0000000c) -#define OTP_SW_LOCK18_NSEC_MSB _u(3) -#define OTP_SW_LOCK18_NSEC_LSB _u(2) -#define OTP_SW_LOCK18_NSEC_ACCESS "RW" -#define OTP_SW_LOCK18_NSEC_VALUE_READ_WRITE _u(0x0) -#define OTP_SW_LOCK18_NSEC_VALUE_READ_ONLY _u(0x1) -#define OTP_SW_LOCK18_NSEC_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_SW_LOCK18_SEC -// Description : Secure lock status. Writes are OR'd with the current value. -// This field is read-only to Non-secure code. -// 0x0 -> read_write -// 0x1 -> read_only -// 0x3 -> inaccessible -#define OTP_SW_LOCK18_SEC_RESET "-" -#define OTP_SW_LOCK18_SEC_BITS _u(0x00000003) -#define OTP_SW_LOCK18_SEC_MSB _u(1) -#define OTP_SW_LOCK18_SEC_LSB _u(0) -#define OTP_SW_LOCK18_SEC_ACCESS "RW" -#define OTP_SW_LOCK18_SEC_VALUE_READ_WRITE _u(0x0) -#define OTP_SW_LOCK18_SEC_VALUE_READ_ONLY _u(0x1) -#define OTP_SW_LOCK18_SEC_VALUE_INACCESSIBLE _u(0x3) -// ============================================================================= -// Register : OTP_SW_LOCK19 -// Description : Software lock register for page 19. -// -// Locks are initialised from the OTP lock pages at reset. This -// register can be written to further advance the lock state of -// each page (until next reset), and read to check the current -// lock state of a page. -#define OTP_SW_LOCK19_OFFSET _u(0x0000004c) -#define OTP_SW_LOCK19_BITS _u(0x0000000f) -#define OTP_SW_LOCK19_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : OTP_SW_LOCK19_NSEC -// Description : Non-secure lock status. Writes are OR'd with the current value. -// 0x0 -> read_write -// 0x1 -> read_only -// 0x3 -> inaccessible -#define OTP_SW_LOCK19_NSEC_RESET "-" -#define OTP_SW_LOCK19_NSEC_BITS _u(0x0000000c) -#define OTP_SW_LOCK19_NSEC_MSB _u(3) -#define OTP_SW_LOCK19_NSEC_LSB _u(2) -#define OTP_SW_LOCK19_NSEC_ACCESS "RW" -#define OTP_SW_LOCK19_NSEC_VALUE_READ_WRITE _u(0x0) -#define OTP_SW_LOCK19_NSEC_VALUE_READ_ONLY _u(0x1) -#define OTP_SW_LOCK19_NSEC_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_SW_LOCK19_SEC -// Description : Secure lock status. Writes are OR'd with the current value. -// This field is read-only to Non-secure code. -// 0x0 -> read_write -// 0x1 -> read_only -// 0x3 -> inaccessible -#define OTP_SW_LOCK19_SEC_RESET "-" -#define OTP_SW_LOCK19_SEC_BITS _u(0x00000003) -#define OTP_SW_LOCK19_SEC_MSB _u(1) -#define OTP_SW_LOCK19_SEC_LSB _u(0) -#define OTP_SW_LOCK19_SEC_ACCESS "RW" -#define OTP_SW_LOCK19_SEC_VALUE_READ_WRITE _u(0x0) -#define OTP_SW_LOCK19_SEC_VALUE_READ_ONLY _u(0x1) -#define OTP_SW_LOCK19_SEC_VALUE_INACCESSIBLE _u(0x3) -// ============================================================================= -// Register : OTP_SW_LOCK20 -// Description : Software lock register for page 20. -// -// Locks are initialised from the OTP lock pages at reset. This -// register can be written to further advance the lock state of -// each page (until next reset), and read to check the current -// lock state of a page. -#define OTP_SW_LOCK20_OFFSET _u(0x00000050) -#define OTP_SW_LOCK20_BITS _u(0x0000000f) -#define OTP_SW_LOCK20_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : OTP_SW_LOCK20_NSEC -// Description : Non-secure lock status. Writes are OR'd with the current value. -// 0x0 -> read_write -// 0x1 -> read_only -// 0x3 -> inaccessible -#define OTP_SW_LOCK20_NSEC_RESET "-" -#define OTP_SW_LOCK20_NSEC_BITS _u(0x0000000c) -#define OTP_SW_LOCK20_NSEC_MSB _u(3) -#define OTP_SW_LOCK20_NSEC_LSB _u(2) -#define OTP_SW_LOCK20_NSEC_ACCESS "RW" -#define OTP_SW_LOCK20_NSEC_VALUE_READ_WRITE _u(0x0) -#define OTP_SW_LOCK20_NSEC_VALUE_READ_ONLY _u(0x1) -#define OTP_SW_LOCK20_NSEC_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_SW_LOCK20_SEC -// Description : Secure lock status. Writes are OR'd with the current value. -// This field is read-only to Non-secure code. -// 0x0 -> read_write -// 0x1 -> read_only -// 0x3 -> inaccessible -#define OTP_SW_LOCK20_SEC_RESET "-" -#define OTP_SW_LOCK20_SEC_BITS _u(0x00000003) -#define OTP_SW_LOCK20_SEC_MSB _u(1) -#define OTP_SW_LOCK20_SEC_LSB _u(0) -#define OTP_SW_LOCK20_SEC_ACCESS "RW" -#define OTP_SW_LOCK20_SEC_VALUE_READ_WRITE _u(0x0) -#define OTP_SW_LOCK20_SEC_VALUE_READ_ONLY _u(0x1) -#define OTP_SW_LOCK20_SEC_VALUE_INACCESSIBLE _u(0x3) -// ============================================================================= -// Register : OTP_SW_LOCK21 -// Description : Software lock register for page 21. -// -// Locks are initialised from the OTP lock pages at reset. This -// register can be written to further advance the lock state of -// each page (until next reset), and read to check the current -// lock state of a page. -#define OTP_SW_LOCK21_OFFSET _u(0x00000054) -#define OTP_SW_LOCK21_BITS _u(0x0000000f) -#define OTP_SW_LOCK21_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : OTP_SW_LOCK21_NSEC -// Description : Non-secure lock status. Writes are OR'd with the current value. -// 0x0 -> read_write -// 0x1 -> read_only -// 0x3 -> inaccessible -#define OTP_SW_LOCK21_NSEC_RESET "-" -#define OTP_SW_LOCK21_NSEC_BITS _u(0x0000000c) -#define OTP_SW_LOCK21_NSEC_MSB _u(3) -#define OTP_SW_LOCK21_NSEC_LSB _u(2) -#define OTP_SW_LOCK21_NSEC_ACCESS "RW" -#define OTP_SW_LOCK21_NSEC_VALUE_READ_WRITE _u(0x0) -#define OTP_SW_LOCK21_NSEC_VALUE_READ_ONLY _u(0x1) -#define OTP_SW_LOCK21_NSEC_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_SW_LOCK21_SEC -// Description : Secure lock status. Writes are OR'd with the current value. -// This field is read-only to Non-secure code. -// 0x0 -> read_write -// 0x1 -> read_only -// 0x3 -> inaccessible -#define OTP_SW_LOCK21_SEC_RESET "-" -#define OTP_SW_LOCK21_SEC_BITS _u(0x00000003) -#define OTP_SW_LOCK21_SEC_MSB _u(1) -#define OTP_SW_LOCK21_SEC_LSB _u(0) -#define OTP_SW_LOCK21_SEC_ACCESS "RW" -#define OTP_SW_LOCK21_SEC_VALUE_READ_WRITE _u(0x0) -#define OTP_SW_LOCK21_SEC_VALUE_READ_ONLY _u(0x1) -#define OTP_SW_LOCK21_SEC_VALUE_INACCESSIBLE _u(0x3) -// ============================================================================= -// Register : OTP_SW_LOCK22 -// Description : Software lock register for page 22. -// -// Locks are initialised from the OTP lock pages at reset. This -// register can be written to further advance the lock state of -// each page (until next reset), and read to check the current -// lock state of a page. -#define OTP_SW_LOCK22_OFFSET _u(0x00000058) -#define OTP_SW_LOCK22_BITS _u(0x0000000f) -#define OTP_SW_LOCK22_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : OTP_SW_LOCK22_NSEC -// Description : Non-secure lock status. Writes are OR'd with the current value. -// 0x0 -> read_write -// 0x1 -> read_only -// 0x3 -> inaccessible -#define OTP_SW_LOCK22_NSEC_RESET "-" -#define OTP_SW_LOCK22_NSEC_BITS _u(0x0000000c) -#define OTP_SW_LOCK22_NSEC_MSB _u(3) -#define OTP_SW_LOCK22_NSEC_LSB _u(2) -#define OTP_SW_LOCK22_NSEC_ACCESS "RW" -#define OTP_SW_LOCK22_NSEC_VALUE_READ_WRITE _u(0x0) -#define OTP_SW_LOCK22_NSEC_VALUE_READ_ONLY _u(0x1) -#define OTP_SW_LOCK22_NSEC_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_SW_LOCK22_SEC -// Description : Secure lock status. Writes are OR'd with the current value. -// This field is read-only to Non-secure code. -// 0x0 -> read_write -// 0x1 -> read_only -// 0x3 -> inaccessible -#define OTP_SW_LOCK22_SEC_RESET "-" -#define OTP_SW_LOCK22_SEC_BITS _u(0x00000003) -#define OTP_SW_LOCK22_SEC_MSB _u(1) -#define OTP_SW_LOCK22_SEC_LSB _u(0) -#define OTP_SW_LOCK22_SEC_ACCESS "RW" -#define OTP_SW_LOCK22_SEC_VALUE_READ_WRITE _u(0x0) -#define OTP_SW_LOCK22_SEC_VALUE_READ_ONLY _u(0x1) -#define OTP_SW_LOCK22_SEC_VALUE_INACCESSIBLE _u(0x3) -// ============================================================================= -// Register : OTP_SW_LOCK23 -// Description : Software lock register for page 23. -// -// Locks are initialised from the OTP lock pages at reset. This -// register can be written to further advance the lock state of -// each page (until next reset), and read to check the current -// lock state of a page. -#define OTP_SW_LOCK23_OFFSET _u(0x0000005c) -#define OTP_SW_LOCK23_BITS _u(0x0000000f) -#define OTP_SW_LOCK23_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : OTP_SW_LOCK23_NSEC -// Description : Non-secure lock status. Writes are OR'd with the current value. -// 0x0 -> read_write -// 0x1 -> read_only -// 0x3 -> inaccessible -#define OTP_SW_LOCK23_NSEC_RESET "-" -#define OTP_SW_LOCK23_NSEC_BITS _u(0x0000000c) -#define OTP_SW_LOCK23_NSEC_MSB _u(3) -#define OTP_SW_LOCK23_NSEC_LSB _u(2) -#define OTP_SW_LOCK23_NSEC_ACCESS "RW" -#define OTP_SW_LOCK23_NSEC_VALUE_READ_WRITE _u(0x0) -#define OTP_SW_LOCK23_NSEC_VALUE_READ_ONLY _u(0x1) -#define OTP_SW_LOCK23_NSEC_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_SW_LOCK23_SEC -// Description : Secure lock status. Writes are OR'd with the current value. -// This field is read-only to Non-secure code. -// 0x0 -> read_write -// 0x1 -> read_only -// 0x3 -> inaccessible -#define OTP_SW_LOCK23_SEC_RESET "-" -#define OTP_SW_LOCK23_SEC_BITS _u(0x00000003) -#define OTP_SW_LOCK23_SEC_MSB _u(1) -#define OTP_SW_LOCK23_SEC_LSB _u(0) -#define OTP_SW_LOCK23_SEC_ACCESS "RW" -#define OTP_SW_LOCK23_SEC_VALUE_READ_WRITE _u(0x0) -#define OTP_SW_LOCK23_SEC_VALUE_READ_ONLY _u(0x1) -#define OTP_SW_LOCK23_SEC_VALUE_INACCESSIBLE _u(0x3) -// ============================================================================= -// Register : OTP_SW_LOCK24 -// Description : Software lock register for page 24. -// -// Locks are initialised from the OTP lock pages at reset. This -// register can be written to further advance the lock state of -// each page (until next reset), and read to check the current -// lock state of a page. -#define OTP_SW_LOCK24_OFFSET _u(0x00000060) -#define OTP_SW_LOCK24_BITS _u(0x0000000f) -#define OTP_SW_LOCK24_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : OTP_SW_LOCK24_NSEC -// Description : Non-secure lock status. Writes are OR'd with the current value. -// 0x0 -> read_write -// 0x1 -> read_only -// 0x3 -> inaccessible -#define OTP_SW_LOCK24_NSEC_RESET "-" -#define OTP_SW_LOCK24_NSEC_BITS _u(0x0000000c) -#define OTP_SW_LOCK24_NSEC_MSB _u(3) -#define OTP_SW_LOCK24_NSEC_LSB _u(2) -#define OTP_SW_LOCK24_NSEC_ACCESS "RW" -#define OTP_SW_LOCK24_NSEC_VALUE_READ_WRITE _u(0x0) -#define OTP_SW_LOCK24_NSEC_VALUE_READ_ONLY _u(0x1) -#define OTP_SW_LOCK24_NSEC_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_SW_LOCK24_SEC -// Description : Secure lock status. Writes are OR'd with the current value. -// This field is read-only to Non-secure code. -// 0x0 -> read_write -// 0x1 -> read_only -// 0x3 -> inaccessible -#define OTP_SW_LOCK24_SEC_RESET "-" -#define OTP_SW_LOCK24_SEC_BITS _u(0x00000003) -#define OTP_SW_LOCK24_SEC_MSB _u(1) -#define OTP_SW_LOCK24_SEC_LSB _u(0) -#define OTP_SW_LOCK24_SEC_ACCESS "RW" -#define OTP_SW_LOCK24_SEC_VALUE_READ_WRITE _u(0x0) -#define OTP_SW_LOCK24_SEC_VALUE_READ_ONLY _u(0x1) -#define OTP_SW_LOCK24_SEC_VALUE_INACCESSIBLE _u(0x3) -// ============================================================================= -// Register : OTP_SW_LOCK25 -// Description : Software lock register for page 25. -// -// Locks are initialised from the OTP lock pages at reset. This -// register can be written to further advance the lock state of -// each page (until next reset), and read to check the current -// lock state of a page. -#define OTP_SW_LOCK25_OFFSET _u(0x00000064) -#define OTP_SW_LOCK25_BITS _u(0x0000000f) -#define OTP_SW_LOCK25_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : OTP_SW_LOCK25_NSEC -// Description : Non-secure lock status. Writes are OR'd with the current value. -// 0x0 -> read_write -// 0x1 -> read_only -// 0x3 -> inaccessible -#define OTP_SW_LOCK25_NSEC_RESET "-" -#define OTP_SW_LOCK25_NSEC_BITS _u(0x0000000c) -#define OTP_SW_LOCK25_NSEC_MSB _u(3) -#define OTP_SW_LOCK25_NSEC_LSB _u(2) -#define OTP_SW_LOCK25_NSEC_ACCESS "RW" -#define OTP_SW_LOCK25_NSEC_VALUE_READ_WRITE _u(0x0) -#define OTP_SW_LOCK25_NSEC_VALUE_READ_ONLY _u(0x1) -#define OTP_SW_LOCK25_NSEC_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_SW_LOCK25_SEC -// Description : Secure lock status. Writes are OR'd with the current value. -// This field is read-only to Non-secure code. -// 0x0 -> read_write -// 0x1 -> read_only -// 0x3 -> inaccessible -#define OTP_SW_LOCK25_SEC_RESET "-" -#define OTP_SW_LOCK25_SEC_BITS _u(0x00000003) -#define OTP_SW_LOCK25_SEC_MSB _u(1) -#define OTP_SW_LOCK25_SEC_LSB _u(0) -#define OTP_SW_LOCK25_SEC_ACCESS "RW" -#define OTP_SW_LOCK25_SEC_VALUE_READ_WRITE _u(0x0) -#define OTP_SW_LOCK25_SEC_VALUE_READ_ONLY _u(0x1) -#define OTP_SW_LOCK25_SEC_VALUE_INACCESSIBLE _u(0x3) -// ============================================================================= -// Register : OTP_SW_LOCK26 -// Description : Software lock register for page 26. -// -// Locks are initialised from the OTP lock pages at reset. This -// register can be written to further advance the lock state of -// each page (until next reset), and read to check the current -// lock state of a page. -#define OTP_SW_LOCK26_OFFSET _u(0x00000068) -#define OTP_SW_LOCK26_BITS _u(0x0000000f) -#define OTP_SW_LOCK26_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : OTP_SW_LOCK26_NSEC -// Description : Non-secure lock status. Writes are OR'd with the current value. -// 0x0 -> read_write -// 0x1 -> read_only -// 0x3 -> inaccessible -#define OTP_SW_LOCK26_NSEC_RESET "-" -#define OTP_SW_LOCK26_NSEC_BITS _u(0x0000000c) -#define OTP_SW_LOCK26_NSEC_MSB _u(3) -#define OTP_SW_LOCK26_NSEC_LSB _u(2) -#define OTP_SW_LOCK26_NSEC_ACCESS "RW" -#define OTP_SW_LOCK26_NSEC_VALUE_READ_WRITE _u(0x0) -#define OTP_SW_LOCK26_NSEC_VALUE_READ_ONLY _u(0x1) -#define OTP_SW_LOCK26_NSEC_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_SW_LOCK26_SEC -// Description : Secure lock status. Writes are OR'd with the current value. -// This field is read-only to Non-secure code. -// 0x0 -> read_write -// 0x1 -> read_only -// 0x3 -> inaccessible -#define OTP_SW_LOCK26_SEC_RESET "-" -#define OTP_SW_LOCK26_SEC_BITS _u(0x00000003) -#define OTP_SW_LOCK26_SEC_MSB _u(1) -#define OTP_SW_LOCK26_SEC_LSB _u(0) -#define OTP_SW_LOCK26_SEC_ACCESS "RW" -#define OTP_SW_LOCK26_SEC_VALUE_READ_WRITE _u(0x0) -#define OTP_SW_LOCK26_SEC_VALUE_READ_ONLY _u(0x1) -#define OTP_SW_LOCK26_SEC_VALUE_INACCESSIBLE _u(0x3) -// ============================================================================= -// Register : OTP_SW_LOCK27 -// Description : Software lock register for page 27. -// -// Locks are initialised from the OTP lock pages at reset. This -// register can be written to further advance the lock state of -// each page (until next reset), and read to check the current -// lock state of a page. -#define OTP_SW_LOCK27_OFFSET _u(0x0000006c) -#define OTP_SW_LOCK27_BITS _u(0x0000000f) -#define OTP_SW_LOCK27_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : OTP_SW_LOCK27_NSEC -// Description : Non-secure lock status. Writes are OR'd with the current value. -// 0x0 -> read_write -// 0x1 -> read_only -// 0x3 -> inaccessible -#define OTP_SW_LOCK27_NSEC_RESET "-" -#define OTP_SW_LOCK27_NSEC_BITS _u(0x0000000c) -#define OTP_SW_LOCK27_NSEC_MSB _u(3) -#define OTP_SW_LOCK27_NSEC_LSB _u(2) -#define OTP_SW_LOCK27_NSEC_ACCESS "RW" -#define OTP_SW_LOCK27_NSEC_VALUE_READ_WRITE _u(0x0) -#define OTP_SW_LOCK27_NSEC_VALUE_READ_ONLY _u(0x1) -#define OTP_SW_LOCK27_NSEC_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_SW_LOCK27_SEC -// Description : Secure lock status. Writes are OR'd with the current value. -// This field is read-only to Non-secure code. -// 0x0 -> read_write -// 0x1 -> read_only -// 0x3 -> inaccessible -#define OTP_SW_LOCK27_SEC_RESET "-" -#define OTP_SW_LOCK27_SEC_BITS _u(0x00000003) -#define OTP_SW_LOCK27_SEC_MSB _u(1) -#define OTP_SW_LOCK27_SEC_LSB _u(0) -#define OTP_SW_LOCK27_SEC_ACCESS "RW" -#define OTP_SW_LOCK27_SEC_VALUE_READ_WRITE _u(0x0) -#define OTP_SW_LOCK27_SEC_VALUE_READ_ONLY _u(0x1) -#define OTP_SW_LOCK27_SEC_VALUE_INACCESSIBLE _u(0x3) -// ============================================================================= -// Register : OTP_SW_LOCK28 -// Description : Software lock register for page 28. -// -// Locks are initialised from the OTP lock pages at reset. This -// register can be written to further advance the lock state of -// each page (until next reset), and read to check the current -// lock state of a page. -#define OTP_SW_LOCK28_OFFSET _u(0x00000070) -#define OTP_SW_LOCK28_BITS _u(0x0000000f) -#define OTP_SW_LOCK28_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : OTP_SW_LOCK28_NSEC -// Description : Non-secure lock status. Writes are OR'd with the current value. -// 0x0 -> read_write -// 0x1 -> read_only -// 0x3 -> inaccessible -#define OTP_SW_LOCK28_NSEC_RESET "-" -#define OTP_SW_LOCK28_NSEC_BITS _u(0x0000000c) -#define OTP_SW_LOCK28_NSEC_MSB _u(3) -#define OTP_SW_LOCK28_NSEC_LSB _u(2) -#define OTP_SW_LOCK28_NSEC_ACCESS "RW" -#define OTP_SW_LOCK28_NSEC_VALUE_READ_WRITE _u(0x0) -#define OTP_SW_LOCK28_NSEC_VALUE_READ_ONLY _u(0x1) -#define OTP_SW_LOCK28_NSEC_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_SW_LOCK28_SEC -// Description : Secure lock status. Writes are OR'd with the current value. -// This field is read-only to Non-secure code. -// 0x0 -> read_write -// 0x1 -> read_only -// 0x3 -> inaccessible -#define OTP_SW_LOCK28_SEC_RESET "-" -#define OTP_SW_LOCK28_SEC_BITS _u(0x00000003) -#define OTP_SW_LOCK28_SEC_MSB _u(1) -#define OTP_SW_LOCK28_SEC_LSB _u(0) -#define OTP_SW_LOCK28_SEC_ACCESS "RW" -#define OTP_SW_LOCK28_SEC_VALUE_READ_WRITE _u(0x0) -#define OTP_SW_LOCK28_SEC_VALUE_READ_ONLY _u(0x1) -#define OTP_SW_LOCK28_SEC_VALUE_INACCESSIBLE _u(0x3) -// ============================================================================= -// Register : OTP_SW_LOCK29 -// Description : Software lock register for page 29. -// -// Locks are initialised from the OTP lock pages at reset. This -// register can be written to further advance the lock state of -// each page (until next reset), and read to check the current -// lock state of a page. -#define OTP_SW_LOCK29_OFFSET _u(0x00000074) -#define OTP_SW_LOCK29_BITS _u(0x0000000f) -#define OTP_SW_LOCK29_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : OTP_SW_LOCK29_NSEC -// Description : Non-secure lock status. Writes are OR'd with the current value. -// 0x0 -> read_write -// 0x1 -> read_only -// 0x3 -> inaccessible -#define OTP_SW_LOCK29_NSEC_RESET "-" -#define OTP_SW_LOCK29_NSEC_BITS _u(0x0000000c) -#define OTP_SW_LOCK29_NSEC_MSB _u(3) -#define OTP_SW_LOCK29_NSEC_LSB _u(2) -#define OTP_SW_LOCK29_NSEC_ACCESS "RW" -#define OTP_SW_LOCK29_NSEC_VALUE_READ_WRITE _u(0x0) -#define OTP_SW_LOCK29_NSEC_VALUE_READ_ONLY _u(0x1) -#define OTP_SW_LOCK29_NSEC_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_SW_LOCK29_SEC -// Description : Secure lock status. Writes are OR'd with the current value. -// This field is read-only to Non-secure code. -// 0x0 -> read_write -// 0x1 -> read_only -// 0x3 -> inaccessible -#define OTP_SW_LOCK29_SEC_RESET "-" -#define OTP_SW_LOCK29_SEC_BITS _u(0x00000003) -#define OTP_SW_LOCK29_SEC_MSB _u(1) -#define OTP_SW_LOCK29_SEC_LSB _u(0) -#define OTP_SW_LOCK29_SEC_ACCESS "RW" -#define OTP_SW_LOCK29_SEC_VALUE_READ_WRITE _u(0x0) -#define OTP_SW_LOCK29_SEC_VALUE_READ_ONLY _u(0x1) -#define OTP_SW_LOCK29_SEC_VALUE_INACCESSIBLE _u(0x3) -// ============================================================================= -// Register : OTP_SW_LOCK30 -// Description : Software lock register for page 30. -// -// Locks are initialised from the OTP lock pages at reset. This -// register can be written to further advance the lock state of -// each page (until next reset), and read to check the current -// lock state of a page. -#define OTP_SW_LOCK30_OFFSET _u(0x00000078) -#define OTP_SW_LOCK30_BITS _u(0x0000000f) -#define OTP_SW_LOCK30_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : OTP_SW_LOCK30_NSEC -// Description : Non-secure lock status. Writes are OR'd with the current value. -// 0x0 -> read_write -// 0x1 -> read_only -// 0x3 -> inaccessible -#define OTP_SW_LOCK30_NSEC_RESET "-" -#define OTP_SW_LOCK30_NSEC_BITS _u(0x0000000c) -#define OTP_SW_LOCK30_NSEC_MSB _u(3) -#define OTP_SW_LOCK30_NSEC_LSB _u(2) -#define OTP_SW_LOCK30_NSEC_ACCESS "RW" -#define OTP_SW_LOCK30_NSEC_VALUE_READ_WRITE _u(0x0) -#define OTP_SW_LOCK30_NSEC_VALUE_READ_ONLY _u(0x1) -#define OTP_SW_LOCK30_NSEC_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_SW_LOCK30_SEC -// Description : Secure lock status. Writes are OR'd with the current value. -// This field is read-only to Non-secure code. -// 0x0 -> read_write -// 0x1 -> read_only -// 0x3 -> inaccessible -#define OTP_SW_LOCK30_SEC_RESET "-" -#define OTP_SW_LOCK30_SEC_BITS _u(0x00000003) -#define OTP_SW_LOCK30_SEC_MSB _u(1) -#define OTP_SW_LOCK30_SEC_LSB _u(0) -#define OTP_SW_LOCK30_SEC_ACCESS "RW" -#define OTP_SW_LOCK30_SEC_VALUE_READ_WRITE _u(0x0) -#define OTP_SW_LOCK30_SEC_VALUE_READ_ONLY _u(0x1) -#define OTP_SW_LOCK30_SEC_VALUE_INACCESSIBLE _u(0x3) -// ============================================================================= -// Register : OTP_SW_LOCK31 -// Description : Software lock register for page 31. -// -// Locks are initialised from the OTP lock pages at reset. This -// register can be written to further advance the lock state of -// each page (until next reset), and read to check the current -// lock state of a page. -#define OTP_SW_LOCK31_OFFSET _u(0x0000007c) -#define OTP_SW_LOCK31_BITS _u(0x0000000f) -#define OTP_SW_LOCK31_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : OTP_SW_LOCK31_NSEC -// Description : Non-secure lock status. Writes are OR'd with the current value. -// 0x0 -> read_write -// 0x1 -> read_only -// 0x3 -> inaccessible -#define OTP_SW_LOCK31_NSEC_RESET "-" -#define OTP_SW_LOCK31_NSEC_BITS _u(0x0000000c) -#define OTP_SW_LOCK31_NSEC_MSB _u(3) -#define OTP_SW_LOCK31_NSEC_LSB _u(2) -#define OTP_SW_LOCK31_NSEC_ACCESS "RW" -#define OTP_SW_LOCK31_NSEC_VALUE_READ_WRITE _u(0x0) -#define OTP_SW_LOCK31_NSEC_VALUE_READ_ONLY _u(0x1) -#define OTP_SW_LOCK31_NSEC_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_SW_LOCK31_SEC -// Description : Secure lock status. Writes are OR'd with the current value. -// This field is read-only to Non-secure code. -// 0x0 -> read_write -// 0x1 -> read_only -// 0x3 -> inaccessible -#define OTP_SW_LOCK31_SEC_RESET "-" -#define OTP_SW_LOCK31_SEC_BITS _u(0x00000003) -#define OTP_SW_LOCK31_SEC_MSB _u(1) -#define OTP_SW_LOCK31_SEC_LSB _u(0) -#define OTP_SW_LOCK31_SEC_ACCESS "RW" -#define OTP_SW_LOCK31_SEC_VALUE_READ_WRITE _u(0x0) -#define OTP_SW_LOCK31_SEC_VALUE_READ_ONLY _u(0x1) -#define OTP_SW_LOCK31_SEC_VALUE_INACCESSIBLE _u(0x3) -// ============================================================================= -// Register : OTP_SW_LOCK32 -// Description : Software lock register for page 32. -// -// Locks are initialised from the OTP lock pages at reset. This -// register can be written to further advance the lock state of -// each page (until next reset), and read to check the current -// lock state of a page. -#define OTP_SW_LOCK32_OFFSET _u(0x00000080) -#define OTP_SW_LOCK32_BITS _u(0x0000000f) -#define OTP_SW_LOCK32_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : OTP_SW_LOCK32_NSEC -// Description : Non-secure lock status. Writes are OR'd with the current value. -// 0x0 -> read_write -// 0x1 -> read_only -// 0x3 -> inaccessible -#define OTP_SW_LOCK32_NSEC_RESET "-" -#define OTP_SW_LOCK32_NSEC_BITS _u(0x0000000c) -#define OTP_SW_LOCK32_NSEC_MSB _u(3) -#define OTP_SW_LOCK32_NSEC_LSB _u(2) -#define OTP_SW_LOCK32_NSEC_ACCESS "RW" -#define OTP_SW_LOCK32_NSEC_VALUE_READ_WRITE _u(0x0) -#define OTP_SW_LOCK32_NSEC_VALUE_READ_ONLY _u(0x1) -#define OTP_SW_LOCK32_NSEC_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_SW_LOCK32_SEC -// Description : Secure lock status. Writes are OR'd with the current value. -// This field is read-only to Non-secure code. -// 0x0 -> read_write -// 0x1 -> read_only -// 0x3 -> inaccessible -#define OTP_SW_LOCK32_SEC_RESET "-" -#define OTP_SW_LOCK32_SEC_BITS _u(0x00000003) -#define OTP_SW_LOCK32_SEC_MSB _u(1) -#define OTP_SW_LOCK32_SEC_LSB _u(0) -#define OTP_SW_LOCK32_SEC_ACCESS "RW" -#define OTP_SW_LOCK32_SEC_VALUE_READ_WRITE _u(0x0) -#define OTP_SW_LOCK32_SEC_VALUE_READ_ONLY _u(0x1) -#define OTP_SW_LOCK32_SEC_VALUE_INACCESSIBLE _u(0x3) -// ============================================================================= -// Register : OTP_SW_LOCK33 -// Description : Software lock register for page 33. -// -// Locks are initialised from the OTP lock pages at reset. This -// register can be written to further advance the lock state of -// each page (until next reset), and read to check the current -// lock state of a page. -#define OTP_SW_LOCK33_OFFSET _u(0x00000084) -#define OTP_SW_LOCK33_BITS _u(0x0000000f) -#define OTP_SW_LOCK33_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : OTP_SW_LOCK33_NSEC -// Description : Non-secure lock status. Writes are OR'd with the current value. -// 0x0 -> read_write -// 0x1 -> read_only -// 0x3 -> inaccessible -#define OTP_SW_LOCK33_NSEC_RESET "-" -#define OTP_SW_LOCK33_NSEC_BITS _u(0x0000000c) -#define OTP_SW_LOCK33_NSEC_MSB _u(3) -#define OTP_SW_LOCK33_NSEC_LSB _u(2) -#define OTP_SW_LOCK33_NSEC_ACCESS "RW" -#define OTP_SW_LOCK33_NSEC_VALUE_READ_WRITE _u(0x0) -#define OTP_SW_LOCK33_NSEC_VALUE_READ_ONLY _u(0x1) -#define OTP_SW_LOCK33_NSEC_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_SW_LOCK33_SEC -// Description : Secure lock status. Writes are OR'd with the current value. -// This field is read-only to Non-secure code. -// 0x0 -> read_write -// 0x1 -> read_only -// 0x3 -> inaccessible -#define OTP_SW_LOCK33_SEC_RESET "-" -#define OTP_SW_LOCK33_SEC_BITS _u(0x00000003) -#define OTP_SW_LOCK33_SEC_MSB _u(1) -#define OTP_SW_LOCK33_SEC_LSB _u(0) -#define OTP_SW_LOCK33_SEC_ACCESS "RW" -#define OTP_SW_LOCK33_SEC_VALUE_READ_WRITE _u(0x0) -#define OTP_SW_LOCK33_SEC_VALUE_READ_ONLY _u(0x1) -#define OTP_SW_LOCK33_SEC_VALUE_INACCESSIBLE _u(0x3) -// ============================================================================= -// Register : OTP_SW_LOCK34 -// Description : Software lock register for page 34. -// -// Locks are initialised from the OTP lock pages at reset. This -// register can be written to further advance the lock state of -// each page (until next reset), and read to check the current -// lock state of a page. -#define OTP_SW_LOCK34_OFFSET _u(0x00000088) -#define OTP_SW_LOCK34_BITS _u(0x0000000f) -#define OTP_SW_LOCK34_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : OTP_SW_LOCK34_NSEC -// Description : Non-secure lock status. Writes are OR'd with the current value. -// 0x0 -> read_write -// 0x1 -> read_only -// 0x3 -> inaccessible -#define OTP_SW_LOCK34_NSEC_RESET "-" -#define OTP_SW_LOCK34_NSEC_BITS _u(0x0000000c) -#define OTP_SW_LOCK34_NSEC_MSB _u(3) -#define OTP_SW_LOCK34_NSEC_LSB _u(2) -#define OTP_SW_LOCK34_NSEC_ACCESS "RW" -#define OTP_SW_LOCK34_NSEC_VALUE_READ_WRITE _u(0x0) -#define OTP_SW_LOCK34_NSEC_VALUE_READ_ONLY _u(0x1) -#define OTP_SW_LOCK34_NSEC_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_SW_LOCK34_SEC -// Description : Secure lock status. Writes are OR'd with the current value. -// This field is read-only to Non-secure code. -// 0x0 -> read_write -// 0x1 -> read_only -// 0x3 -> inaccessible -#define OTP_SW_LOCK34_SEC_RESET "-" -#define OTP_SW_LOCK34_SEC_BITS _u(0x00000003) -#define OTP_SW_LOCK34_SEC_MSB _u(1) -#define OTP_SW_LOCK34_SEC_LSB _u(0) -#define OTP_SW_LOCK34_SEC_ACCESS "RW" -#define OTP_SW_LOCK34_SEC_VALUE_READ_WRITE _u(0x0) -#define OTP_SW_LOCK34_SEC_VALUE_READ_ONLY _u(0x1) -#define OTP_SW_LOCK34_SEC_VALUE_INACCESSIBLE _u(0x3) -// ============================================================================= -// Register : OTP_SW_LOCK35 -// Description : Software lock register for page 35. -// -// Locks are initialised from the OTP lock pages at reset. This -// register can be written to further advance the lock state of -// each page (until next reset), and read to check the current -// lock state of a page. -#define OTP_SW_LOCK35_OFFSET _u(0x0000008c) -#define OTP_SW_LOCK35_BITS _u(0x0000000f) -#define OTP_SW_LOCK35_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : OTP_SW_LOCK35_NSEC -// Description : Non-secure lock status. Writes are OR'd with the current value. -// 0x0 -> read_write -// 0x1 -> read_only -// 0x3 -> inaccessible -#define OTP_SW_LOCK35_NSEC_RESET "-" -#define OTP_SW_LOCK35_NSEC_BITS _u(0x0000000c) -#define OTP_SW_LOCK35_NSEC_MSB _u(3) -#define OTP_SW_LOCK35_NSEC_LSB _u(2) -#define OTP_SW_LOCK35_NSEC_ACCESS "RW" -#define OTP_SW_LOCK35_NSEC_VALUE_READ_WRITE _u(0x0) -#define OTP_SW_LOCK35_NSEC_VALUE_READ_ONLY _u(0x1) -#define OTP_SW_LOCK35_NSEC_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_SW_LOCK35_SEC -// Description : Secure lock status. Writes are OR'd with the current value. -// This field is read-only to Non-secure code. -// 0x0 -> read_write -// 0x1 -> read_only -// 0x3 -> inaccessible -#define OTP_SW_LOCK35_SEC_RESET "-" -#define OTP_SW_LOCK35_SEC_BITS _u(0x00000003) -#define OTP_SW_LOCK35_SEC_MSB _u(1) -#define OTP_SW_LOCK35_SEC_LSB _u(0) -#define OTP_SW_LOCK35_SEC_ACCESS "RW" -#define OTP_SW_LOCK35_SEC_VALUE_READ_WRITE _u(0x0) -#define OTP_SW_LOCK35_SEC_VALUE_READ_ONLY _u(0x1) -#define OTP_SW_LOCK35_SEC_VALUE_INACCESSIBLE _u(0x3) -// ============================================================================= -// Register : OTP_SW_LOCK36 -// Description : Software lock register for page 36. -// -// Locks are initialised from the OTP lock pages at reset. This -// register can be written to further advance the lock state of -// each page (until next reset), and read to check the current -// lock state of a page. -#define OTP_SW_LOCK36_OFFSET _u(0x00000090) -#define OTP_SW_LOCK36_BITS _u(0x0000000f) -#define OTP_SW_LOCK36_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : OTP_SW_LOCK36_NSEC -// Description : Non-secure lock status. Writes are OR'd with the current value. -// 0x0 -> read_write -// 0x1 -> read_only -// 0x3 -> inaccessible -#define OTP_SW_LOCK36_NSEC_RESET "-" -#define OTP_SW_LOCK36_NSEC_BITS _u(0x0000000c) -#define OTP_SW_LOCK36_NSEC_MSB _u(3) -#define OTP_SW_LOCK36_NSEC_LSB _u(2) -#define OTP_SW_LOCK36_NSEC_ACCESS "RW" -#define OTP_SW_LOCK36_NSEC_VALUE_READ_WRITE _u(0x0) -#define OTP_SW_LOCK36_NSEC_VALUE_READ_ONLY _u(0x1) -#define OTP_SW_LOCK36_NSEC_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_SW_LOCK36_SEC -// Description : Secure lock status. Writes are OR'd with the current value. -// This field is read-only to Non-secure code. -// 0x0 -> read_write -// 0x1 -> read_only -// 0x3 -> inaccessible -#define OTP_SW_LOCK36_SEC_RESET "-" -#define OTP_SW_LOCK36_SEC_BITS _u(0x00000003) -#define OTP_SW_LOCK36_SEC_MSB _u(1) -#define OTP_SW_LOCK36_SEC_LSB _u(0) -#define OTP_SW_LOCK36_SEC_ACCESS "RW" -#define OTP_SW_LOCK36_SEC_VALUE_READ_WRITE _u(0x0) -#define OTP_SW_LOCK36_SEC_VALUE_READ_ONLY _u(0x1) -#define OTP_SW_LOCK36_SEC_VALUE_INACCESSIBLE _u(0x3) -// ============================================================================= -// Register : OTP_SW_LOCK37 -// Description : Software lock register for page 37. -// -// Locks are initialised from the OTP lock pages at reset. This -// register can be written to further advance the lock state of -// each page (until next reset), and read to check the current -// lock state of a page. -#define OTP_SW_LOCK37_OFFSET _u(0x00000094) -#define OTP_SW_LOCK37_BITS _u(0x0000000f) -#define OTP_SW_LOCK37_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : OTP_SW_LOCK37_NSEC -// Description : Non-secure lock status. Writes are OR'd with the current value. -// 0x0 -> read_write -// 0x1 -> read_only -// 0x3 -> inaccessible -#define OTP_SW_LOCK37_NSEC_RESET "-" -#define OTP_SW_LOCK37_NSEC_BITS _u(0x0000000c) -#define OTP_SW_LOCK37_NSEC_MSB _u(3) -#define OTP_SW_LOCK37_NSEC_LSB _u(2) -#define OTP_SW_LOCK37_NSEC_ACCESS "RW" -#define OTP_SW_LOCK37_NSEC_VALUE_READ_WRITE _u(0x0) -#define OTP_SW_LOCK37_NSEC_VALUE_READ_ONLY _u(0x1) -#define OTP_SW_LOCK37_NSEC_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_SW_LOCK37_SEC -// Description : Secure lock status. Writes are OR'd with the current value. -// This field is read-only to Non-secure code. -// 0x0 -> read_write -// 0x1 -> read_only -// 0x3 -> inaccessible -#define OTP_SW_LOCK37_SEC_RESET "-" -#define OTP_SW_LOCK37_SEC_BITS _u(0x00000003) -#define OTP_SW_LOCK37_SEC_MSB _u(1) -#define OTP_SW_LOCK37_SEC_LSB _u(0) -#define OTP_SW_LOCK37_SEC_ACCESS "RW" -#define OTP_SW_LOCK37_SEC_VALUE_READ_WRITE _u(0x0) -#define OTP_SW_LOCK37_SEC_VALUE_READ_ONLY _u(0x1) -#define OTP_SW_LOCK37_SEC_VALUE_INACCESSIBLE _u(0x3) -// ============================================================================= -// Register : OTP_SW_LOCK38 -// Description : Software lock register for page 38. -// -// Locks are initialised from the OTP lock pages at reset. This -// register can be written to further advance the lock state of -// each page (until next reset), and read to check the current -// lock state of a page. -#define OTP_SW_LOCK38_OFFSET _u(0x00000098) -#define OTP_SW_LOCK38_BITS _u(0x0000000f) -#define OTP_SW_LOCK38_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : OTP_SW_LOCK38_NSEC -// Description : Non-secure lock status. Writes are OR'd with the current value. -// 0x0 -> read_write -// 0x1 -> read_only -// 0x3 -> inaccessible -#define OTP_SW_LOCK38_NSEC_RESET "-" -#define OTP_SW_LOCK38_NSEC_BITS _u(0x0000000c) -#define OTP_SW_LOCK38_NSEC_MSB _u(3) -#define OTP_SW_LOCK38_NSEC_LSB _u(2) -#define OTP_SW_LOCK38_NSEC_ACCESS "RW" -#define OTP_SW_LOCK38_NSEC_VALUE_READ_WRITE _u(0x0) -#define OTP_SW_LOCK38_NSEC_VALUE_READ_ONLY _u(0x1) -#define OTP_SW_LOCK38_NSEC_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_SW_LOCK38_SEC -// Description : Secure lock status. Writes are OR'd with the current value. -// This field is read-only to Non-secure code. -// 0x0 -> read_write -// 0x1 -> read_only -// 0x3 -> inaccessible -#define OTP_SW_LOCK38_SEC_RESET "-" -#define OTP_SW_LOCK38_SEC_BITS _u(0x00000003) -#define OTP_SW_LOCK38_SEC_MSB _u(1) -#define OTP_SW_LOCK38_SEC_LSB _u(0) -#define OTP_SW_LOCK38_SEC_ACCESS "RW" -#define OTP_SW_LOCK38_SEC_VALUE_READ_WRITE _u(0x0) -#define OTP_SW_LOCK38_SEC_VALUE_READ_ONLY _u(0x1) -#define OTP_SW_LOCK38_SEC_VALUE_INACCESSIBLE _u(0x3) -// ============================================================================= -// Register : OTP_SW_LOCK39 -// Description : Software lock register for page 39. -// -// Locks are initialised from the OTP lock pages at reset. This -// register can be written to further advance the lock state of -// each page (until next reset), and read to check the current -// lock state of a page. -#define OTP_SW_LOCK39_OFFSET _u(0x0000009c) -#define OTP_SW_LOCK39_BITS _u(0x0000000f) -#define OTP_SW_LOCK39_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : OTP_SW_LOCK39_NSEC -// Description : Non-secure lock status. Writes are OR'd with the current value. -// 0x0 -> read_write -// 0x1 -> read_only -// 0x3 -> inaccessible -#define OTP_SW_LOCK39_NSEC_RESET "-" -#define OTP_SW_LOCK39_NSEC_BITS _u(0x0000000c) -#define OTP_SW_LOCK39_NSEC_MSB _u(3) -#define OTP_SW_LOCK39_NSEC_LSB _u(2) -#define OTP_SW_LOCK39_NSEC_ACCESS "RW" -#define OTP_SW_LOCK39_NSEC_VALUE_READ_WRITE _u(0x0) -#define OTP_SW_LOCK39_NSEC_VALUE_READ_ONLY _u(0x1) -#define OTP_SW_LOCK39_NSEC_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_SW_LOCK39_SEC -// Description : Secure lock status. Writes are OR'd with the current value. -// This field is read-only to Non-secure code. -// 0x0 -> read_write -// 0x1 -> read_only -// 0x3 -> inaccessible -#define OTP_SW_LOCK39_SEC_RESET "-" -#define OTP_SW_LOCK39_SEC_BITS _u(0x00000003) -#define OTP_SW_LOCK39_SEC_MSB _u(1) -#define OTP_SW_LOCK39_SEC_LSB _u(0) -#define OTP_SW_LOCK39_SEC_ACCESS "RW" -#define OTP_SW_LOCK39_SEC_VALUE_READ_WRITE _u(0x0) -#define OTP_SW_LOCK39_SEC_VALUE_READ_ONLY _u(0x1) -#define OTP_SW_LOCK39_SEC_VALUE_INACCESSIBLE _u(0x3) -// ============================================================================= -// Register : OTP_SW_LOCK40 -// Description : Software lock register for page 40. -// -// Locks are initialised from the OTP lock pages at reset. This -// register can be written to further advance the lock state of -// each page (until next reset), and read to check the current -// lock state of a page. -#define OTP_SW_LOCK40_OFFSET _u(0x000000a0) -#define OTP_SW_LOCK40_BITS _u(0x0000000f) -#define OTP_SW_LOCK40_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : OTP_SW_LOCK40_NSEC -// Description : Non-secure lock status. Writes are OR'd with the current value. -// 0x0 -> read_write -// 0x1 -> read_only -// 0x3 -> inaccessible -#define OTP_SW_LOCK40_NSEC_RESET "-" -#define OTP_SW_LOCK40_NSEC_BITS _u(0x0000000c) -#define OTP_SW_LOCK40_NSEC_MSB _u(3) -#define OTP_SW_LOCK40_NSEC_LSB _u(2) -#define OTP_SW_LOCK40_NSEC_ACCESS "RW" -#define OTP_SW_LOCK40_NSEC_VALUE_READ_WRITE _u(0x0) -#define OTP_SW_LOCK40_NSEC_VALUE_READ_ONLY _u(0x1) -#define OTP_SW_LOCK40_NSEC_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_SW_LOCK40_SEC -// Description : Secure lock status. Writes are OR'd with the current value. -// This field is read-only to Non-secure code. -// 0x0 -> read_write -// 0x1 -> read_only -// 0x3 -> inaccessible -#define OTP_SW_LOCK40_SEC_RESET "-" -#define OTP_SW_LOCK40_SEC_BITS _u(0x00000003) -#define OTP_SW_LOCK40_SEC_MSB _u(1) -#define OTP_SW_LOCK40_SEC_LSB _u(0) -#define OTP_SW_LOCK40_SEC_ACCESS "RW" -#define OTP_SW_LOCK40_SEC_VALUE_READ_WRITE _u(0x0) -#define OTP_SW_LOCK40_SEC_VALUE_READ_ONLY _u(0x1) -#define OTP_SW_LOCK40_SEC_VALUE_INACCESSIBLE _u(0x3) -// ============================================================================= -// Register : OTP_SW_LOCK41 -// Description : Software lock register for page 41. -// -// Locks are initialised from the OTP lock pages at reset. This -// register can be written to further advance the lock state of -// each page (until next reset), and read to check the current -// lock state of a page. -#define OTP_SW_LOCK41_OFFSET _u(0x000000a4) -#define OTP_SW_LOCK41_BITS _u(0x0000000f) -#define OTP_SW_LOCK41_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : OTP_SW_LOCK41_NSEC -// Description : Non-secure lock status. Writes are OR'd with the current value. -// 0x0 -> read_write -// 0x1 -> read_only -// 0x3 -> inaccessible -#define OTP_SW_LOCK41_NSEC_RESET "-" -#define OTP_SW_LOCK41_NSEC_BITS _u(0x0000000c) -#define OTP_SW_LOCK41_NSEC_MSB _u(3) -#define OTP_SW_LOCK41_NSEC_LSB _u(2) -#define OTP_SW_LOCK41_NSEC_ACCESS "RW" -#define OTP_SW_LOCK41_NSEC_VALUE_READ_WRITE _u(0x0) -#define OTP_SW_LOCK41_NSEC_VALUE_READ_ONLY _u(0x1) -#define OTP_SW_LOCK41_NSEC_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_SW_LOCK41_SEC -// Description : Secure lock status. Writes are OR'd with the current value. -// This field is read-only to Non-secure code. -// 0x0 -> read_write -// 0x1 -> read_only -// 0x3 -> inaccessible -#define OTP_SW_LOCK41_SEC_RESET "-" -#define OTP_SW_LOCK41_SEC_BITS _u(0x00000003) -#define OTP_SW_LOCK41_SEC_MSB _u(1) -#define OTP_SW_LOCK41_SEC_LSB _u(0) -#define OTP_SW_LOCK41_SEC_ACCESS "RW" -#define OTP_SW_LOCK41_SEC_VALUE_READ_WRITE _u(0x0) -#define OTP_SW_LOCK41_SEC_VALUE_READ_ONLY _u(0x1) -#define OTP_SW_LOCK41_SEC_VALUE_INACCESSIBLE _u(0x3) -// ============================================================================= -// Register : OTP_SW_LOCK42 -// Description : Software lock register for page 42. -// -// Locks are initialised from the OTP lock pages at reset. This -// register can be written to further advance the lock state of -// each page (until next reset), and read to check the current -// lock state of a page. -#define OTP_SW_LOCK42_OFFSET _u(0x000000a8) -#define OTP_SW_LOCK42_BITS _u(0x0000000f) -#define OTP_SW_LOCK42_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : OTP_SW_LOCK42_NSEC -// Description : Non-secure lock status. Writes are OR'd with the current value. -// 0x0 -> read_write -// 0x1 -> read_only -// 0x3 -> inaccessible -#define OTP_SW_LOCK42_NSEC_RESET "-" -#define OTP_SW_LOCK42_NSEC_BITS _u(0x0000000c) -#define OTP_SW_LOCK42_NSEC_MSB _u(3) -#define OTP_SW_LOCK42_NSEC_LSB _u(2) -#define OTP_SW_LOCK42_NSEC_ACCESS "RW" -#define OTP_SW_LOCK42_NSEC_VALUE_READ_WRITE _u(0x0) -#define OTP_SW_LOCK42_NSEC_VALUE_READ_ONLY _u(0x1) -#define OTP_SW_LOCK42_NSEC_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_SW_LOCK42_SEC -// Description : Secure lock status. Writes are OR'd with the current value. -// This field is read-only to Non-secure code. -// 0x0 -> read_write -// 0x1 -> read_only -// 0x3 -> inaccessible -#define OTP_SW_LOCK42_SEC_RESET "-" -#define OTP_SW_LOCK42_SEC_BITS _u(0x00000003) -#define OTP_SW_LOCK42_SEC_MSB _u(1) -#define OTP_SW_LOCK42_SEC_LSB _u(0) -#define OTP_SW_LOCK42_SEC_ACCESS "RW" -#define OTP_SW_LOCK42_SEC_VALUE_READ_WRITE _u(0x0) -#define OTP_SW_LOCK42_SEC_VALUE_READ_ONLY _u(0x1) -#define OTP_SW_LOCK42_SEC_VALUE_INACCESSIBLE _u(0x3) -// ============================================================================= -// Register : OTP_SW_LOCK43 -// Description : Software lock register for page 43. -// -// Locks are initialised from the OTP lock pages at reset. This -// register can be written to further advance the lock state of -// each page (until next reset), and read to check the current -// lock state of a page. -#define OTP_SW_LOCK43_OFFSET _u(0x000000ac) -#define OTP_SW_LOCK43_BITS _u(0x0000000f) -#define OTP_SW_LOCK43_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : OTP_SW_LOCK43_NSEC -// Description : Non-secure lock status. Writes are OR'd with the current value. -// 0x0 -> read_write -// 0x1 -> read_only -// 0x3 -> inaccessible -#define OTP_SW_LOCK43_NSEC_RESET "-" -#define OTP_SW_LOCK43_NSEC_BITS _u(0x0000000c) -#define OTP_SW_LOCK43_NSEC_MSB _u(3) -#define OTP_SW_LOCK43_NSEC_LSB _u(2) -#define OTP_SW_LOCK43_NSEC_ACCESS "RW" -#define OTP_SW_LOCK43_NSEC_VALUE_READ_WRITE _u(0x0) -#define OTP_SW_LOCK43_NSEC_VALUE_READ_ONLY _u(0x1) -#define OTP_SW_LOCK43_NSEC_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_SW_LOCK43_SEC -// Description : Secure lock status. Writes are OR'd with the current value. -// This field is read-only to Non-secure code. -// 0x0 -> read_write -// 0x1 -> read_only -// 0x3 -> inaccessible -#define OTP_SW_LOCK43_SEC_RESET "-" -#define OTP_SW_LOCK43_SEC_BITS _u(0x00000003) -#define OTP_SW_LOCK43_SEC_MSB _u(1) -#define OTP_SW_LOCK43_SEC_LSB _u(0) -#define OTP_SW_LOCK43_SEC_ACCESS "RW" -#define OTP_SW_LOCK43_SEC_VALUE_READ_WRITE _u(0x0) -#define OTP_SW_LOCK43_SEC_VALUE_READ_ONLY _u(0x1) -#define OTP_SW_LOCK43_SEC_VALUE_INACCESSIBLE _u(0x3) -// ============================================================================= -// Register : OTP_SW_LOCK44 -// Description : Software lock register for page 44. -// -// Locks are initialised from the OTP lock pages at reset. This -// register can be written to further advance the lock state of -// each page (until next reset), and read to check the current -// lock state of a page. -#define OTP_SW_LOCK44_OFFSET _u(0x000000b0) -#define OTP_SW_LOCK44_BITS _u(0x0000000f) -#define OTP_SW_LOCK44_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : OTP_SW_LOCK44_NSEC -// Description : Non-secure lock status. Writes are OR'd with the current value. -// 0x0 -> read_write -// 0x1 -> read_only -// 0x3 -> inaccessible -#define OTP_SW_LOCK44_NSEC_RESET "-" -#define OTP_SW_LOCK44_NSEC_BITS _u(0x0000000c) -#define OTP_SW_LOCK44_NSEC_MSB _u(3) -#define OTP_SW_LOCK44_NSEC_LSB _u(2) -#define OTP_SW_LOCK44_NSEC_ACCESS "RW" -#define OTP_SW_LOCK44_NSEC_VALUE_READ_WRITE _u(0x0) -#define OTP_SW_LOCK44_NSEC_VALUE_READ_ONLY _u(0x1) -#define OTP_SW_LOCK44_NSEC_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_SW_LOCK44_SEC -// Description : Secure lock status. Writes are OR'd with the current value. -// This field is read-only to Non-secure code. -// 0x0 -> read_write -// 0x1 -> read_only -// 0x3 -> inaccessible -#define OTP_SW_LOCK44_SEC_RESET "-" -#define OTP_SW_LOCK44_SEC_BITS _u(0x00000003) -#define OTP_SW_LOCK44_SEC_MSB _u(1) -#define OTP_SW_LOCK44_SEC_LSB _u(0) -#define OTP_SW_LOCK44_SEC_ACCESS "RW" -#define OTP_SW_LOCK44_SEC_VALUE_READ_WRITE _u(0x0) -#define OTP_SW_LOCK44_SEC_VALUE_READ_ONLY _u(0x1) -#define OTP_SW_LOCK44_SEC_VALUE_INACCESSIBLE _u(0x3) -// ============================================================================= -// Register : OTP_SW_LOCK45 -// Description : Software lock register for page 45. -// -// Locks are initialised from the OTP lock pages at reset. This -// register can be written to further advance the lock state of -// each page (until next reset), and read to check the current -// lock state of a page. -#define OTP_SW_LOCK45_OFFSET _u(0x000000b4) -#define OTP_SW_LOCK45_BITS _u(0x0000000f) -#define OTP_SW_LOCK45_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : OTP_SW_LOCK45_NSEC -// Description : Non-secure lock status. Writes are OR'd with the current value. -// 0x0 -> read_write -// 0x1 -> read_only -// 0x3 -> inaccessible -#define OTP_SW_LOCK45_NSEC_RESET "-" -#define OTP_SW_LOCK45_NSEC_BITS _u(0x0000000c) -#define OTP_SW_LOCK45_NSEC_MSB _u(3) -#define OTP_SW_LOCK45_NSEC_LSB _u(2) -#define OTP_SW_LOCK45_NSEC_ACCESS "RW" -#define OTP_SW_LOCK45_NSEC_VALUE_READ_WRITE _u(0x0) -#define OTP_SW_LOCK45_NSEC_VALUE_READ_ONLY _u(0x1) -#define OTP_SW_LOCK45_NSEC_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_SW_LOCK45_SEC -// Description : Secure lock status. Writes are OR'd with the current value. -// This field is read-only to Non-secure code. -// 0x0 -> read_write -// 0x1 -> read_only -// 0x3 -> inaccessible -#define OTP_SW_LOCK45_SEC_RESET "-" -#define OTP_SW_LOCK45_SEC_BITS _u(0x00000003) -#define OTP_SW_LOCK45_SEC_MSB _u(1) -#define OTP_SW_LOCK45_SEC_LSB _u(0) -#define OTP_SW_LOCK45_SEC_ACCESS "RW" -#define OTP_SW_LOCK45_SEC_VALUE_READ_WRITE _u(0x0) -#define OTP_SW_LOCK45_SEC_VALUE_READ_ONLY _u(0x1) -#define OTP_SW_LOCK45_SEC_VALUE_INACCESSIBLE _u(0x3) -// ============================================================================= -// Register : OTP_SW_LOCK46 -// Description : Software lock register for page 46. -// -// Locks are initialised from the OTP lock pages at reset. This -// register can be written to further advance the lock state of -// each page (until next reset), and read to check the current -// lock state of a page. -#define OTP_SW_LOCK46_OFFSET _u(0x000000b8) -#define OTP_SW_LOCK46_BITS _u(0x0000000f) -#define OTP_SW_LOCK46_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : OTP_SW_LOCK46_NSEC -// Description : Non-secure lock status. Writes are OR'd with the current value. -// 0x0 -> read_write -// 0x1 -> read_only -// 0x3 -> inaccessible -#define OTP_SW_LOCK46_NSEC_RESET "-" -#define OTP_SW_LOCK46_NSEC_BITS _u(0x0000000c) -#define OTP_SW_LOCK46_NSEC_MSB _u(3) -#define OTP_SW_LOCK46_NSEC_LSB _u(2) -#define OTP_SW_LOCK46_NSEC_ACCESS "RW" -#define OTP_SW_LOCK46_NSEC_VALUE_READ_WRITE _u(0x0) -#define OTP_SW_LOCK46_NSEC_VALUE_READ_ONLY _u(0x1) -#define OTP_SW_LOCK46_NSEC_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_SW_LOCK46_SEC -// Description : Secure lock status. Writes are OR'd with the current value. -// This field is read-only to Non-secure code. -// 0x0 -> read_write -// 0x1 -> read_only -// 0x3 -> inaccessible -#define OTP_SW_LOCK46_SEC_RESET "-" -#define OTP_SW_LOCK46_SEC_BITS _u(0x00000003) -#define OTP_SW_LOCK46_SEC_MSB _u(1) -#define OTP_SW_LOCK46_SEC_LSB _u(0) -#define OTP_SW_LOCK46_SEC_ACCESS "RW" -#define OTP_SW_LOCK46_SEC_VALUE_READ_WRITE _u(0x0) -#define OTP_SW_LOCK46_SEC_VALUE_READ_ONLY _u(0x1) -#define OTP_SW_LOCK46_SEC_VALUE_INACCESSIBLE _u(0x3) -// ============================================================================= -// Register : OTP_SW_LOCK47 -// Description : Software lock register for page 47. -// -// Locks are initialised from the OTP lock pages at reset. This -// register can be written to further advance the lock state of -// each page (until next reset), and read to check the current -// lock state of a page. -#define OTP_SW_LOCK47_OFFSET _u(0x000000bc) -#define OTP_SW_LOCK47_BITS _u(0x0000000f) -#define OTP_SW_LOCK47_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : OTP_SW_LOCK47_NSEC -// Description : Non-secure lock status. Writes are OR'd with the current value. -// 0x0 -> read_write -// 0x1 -> read_only -// 0x3 -> inaccessible -#define OTP_SW_LOCK47_NSEC_RESET "-" -#define OTP_SW_LOCK47_NSEC_BITS _u(0x0000000c) -#define OTP_SW_LOCK47_NSEC_MSB _u(3) -#define OTP_SW_LOCK47_NSEC_LSB _u(2) -#define OTP_SW_LOCK47_NSEC_ACCESS "RW" -#define OTP_SW_LOCK47_NSEC_VALUE_READ_WRITE _u(0x0) -#define OTP_SW_LOCK47_NSEC_VALUE_READ_ONLY _u(0x1) -#define OTP_SW_LOCK47_NSEC_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_SW_LOCK47_SEC -// Description : Secure lock status. Writes are OR'd with the current value. -// This field is read-only to Non-secure code. -// 0x0 -> read_write -// 0x1 -> read_only -// 0x3 -> inaccessible -#define OTP_SW_LOCK47_SEC_RESET "-" -#define OTP_SW_LOCK47_SEC_BITS _u(0x00000003) -#define OTP_SW_LOCK47_SEC_MSB _u(1) -#define OTP_SW_LOCK47_SEC_LSB _u(0) -#define OTP_SW_LOCK47_SEC_ACCESS "RW" -#define OTP_SW_LOCK47_SEC_VALUE_READ_WRITE _u(0x0) -#define OTP_SW_LOCK47_SEC_VALUE_READ_ONLY _u(0x1) -#define OTP_SW_LOCK47_SEC_VALUE_INACCESSIBLE _u(0x3) -// ============================================================================= -// Register : OTP_SW_LOCK48 -// Description : Software lock register for page 48. -// -// Locks are initialised from the OTP lock pages at reset. This -// register can be written to further advance the lock state of -// each page (until next reset), and read to check the current -// lock state of a page. -#define OTP_SW_LOCK48_OFFSET _u(0x000000c0) -#define OTP_SW_LOCK48_BITS _u(0x0000000f) -#define OTP_SW_LOCK48_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : OTP_SW_LOCK48_NSEC -// Description : Non-secure lock status. Writes are OR'd with the current value. -// 0x0 -> read_write -// 0x1 -> read_only -// 0x3 -> inaccessible -#define OTP_SW_LOCK48_NSEC_RESET "-" -#define OTP_SW_LOCK48_NSEC_BITS _u(0x0000000c) -#define OTP_SW_LOCK48_NSEC_MSB _u(3) -#define OTP_SW_LOCK48_NSEC_LSB _u(2) -#define OTP_SW_LOCK48_NSEC_ACCESS "RW" -#define OTP_SW_LOCK48_NSEC_VALUE_READ_WRITE _u(0x0) -#define OTP_SW_LOCK48_NSEC_VALUE_READ_ONLY _u(0x1) -#define OTP_SW_LOCK48_NSEC_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_SW_LOCK48_SEC -// Description : Secure lock status. Writes are OR'd with the current value. -// This field is read-only to Non-secure code. -// 0x0 -> read_write -// 0x1 -> read_only -// 0x3 -> inaccessible -#define OTP_SW_LOCK48_SEC_RESET "-" -#define OTP_SW_LOCK48_SEC_BITS _u(0x00000003) -#define OTP_SW_LOCK48_SEC_MSB _u(1) -#define OTP_SW_LOCK48_SEC_LSB _u(0) -#define OTP_SW_LOCK48_SEC_ACCESS "RW" -#define OTP_SW_LOCK48_SEC_VALUE_READ_WRITE _u(0x0) -#define OTP_SW_LOCK48_SEC_VALUE_READ_ONLY _u(0x1) -#define OTP_SW_LOCK48_SEC_VALUE_INACCESSIBLE _u(0x3) -// ============================================================================= -// Register : OTP_SW_LOCK49 -// Description : Software lock register for page 49. -// -// Locks are initialised from the OTP lock pages at reset. This -// register can be written to further advance the lock state of -// each page (until next reset), and read to check the current -// lock state of a page. -#define OTP_SW_LOCK49_OFFSET _u(0x000000c4) -#define OTP_SW_LOCK49_BITS _u(0x0000000f) -#define OTP_SW_LOCK49_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : OTP_SW_LOCK49_NSEC -// Description : Non-secure lock status. Writes are OR'd with the current value. -// 0x0 -> read_write -// 0x1 -> read_only -// 0x3 -> inaccessible -#define OTP_SW_LOCK49_NSEC_RESET "-" -#define OTP_SW_LOCK49_NSEC_BITS _u(0x0000000c) -#define OTP_SW_LOCK49_NSEC_MSB _u(3) -#define OTP_SW_LOCK49_NSEC_LSB _u(2) -#define OTP_SW_LOCK49_NSEC_ACCESS "RW" -#define OTP_SW_LOCK49_NSEC_VALUE_READ_WRITE _u(0x0) -#define OTP_SW_LOCK49_NSEC_VALUE_READ_ONLY _u(0x1) -#define OTP_SW_LOCK49_NSEC_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_SW_LOCK49_SEC -// Description : Secure lock status. Writes are OR'd with the current value. -// This field is read-only to Non-secure code. -// 0x0 -> read_write -// 0x1 -> read_only -// 0x3 -> inaccessible -#define OTP_SW_LOCK49_SEC_RESET "-" -#define OTP_SW_LOCK49_SEC_BITS _u(0x00000003) -#define OTP_SW_LOCK49_SEC_MSB _u(1) -#define OTP_SW_LOCK49_SEC_LSB _u(0) -#define OTP_SW_LOCK49_SEC_ACCESS "RW" -#define OTP_SW_LOCK49_SEC_VALUE_READ_WRITE _u(0x0) -#define OTP_SW_LOCK49_SEC_VALUE_READ_ONLY _u(0x1) -#define OTP_SW_LOCK49_SEC_VALUE_INACCESSIBLE _u(0x3) -// ============================================================================= -// Register : OTP_SW_LOCK50 -// Description : Software lock register for page 50. -// -// Locks are initialised from the OTP lock pages at reset. This -// register can be written to further advance the lock state of -// each page (until next reset), and read to check the current -// lock state of a page. -#define OTP_SW_LOCK50_OFFSET _u(0x000000c8) -#define OTP_SW_LOCK50_BITS _u(0x0000000f) -#define OTP_SW_LOCK50_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : OTP_SW_LOCK50_NSEC -// Description : Non-secure lock status. Writes are OR'd with the current value. -// 0x0 -> read_write -// 0x1 -> read_only -// 0x3 -> inaccessible -#define OTP_SW_LOCK50_NSEC_RESET "-" -#define OTP_SW_LOCK50_NSEC_BITS _u(0x0000000c) -#define OTP_SW_LOCK50_NSEC_MSB _u(3) -#define OTP_SW_LOCK50_NSEC_LSB _u(2) -#define OTP_SW_LOCK50_NSEC_ACCESS "RW" -#define OTP_SW_LOCK50_NSEC_VALUE_READ_WRITE _u(0x0) -#define OTP_SW_LOCK50_NSEC_VALUE_READ_ONLY _u(0x1) -#define OTP_SW_LOCK50_NSEC_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_SW_LOCK50_SEC -// Description : Secure lock status. Writes are OR'd with the current value. -// This field is read-only to Non-secure code. -// 0x0 -> read_write -// 0x1 -> read_only -// 0x3 -> inaccessible -#define OTP_SW_LOCK50_SEC_RESET "-" -#define OTP_SW_LOCK50_SEC_BITS _u(0x00000003) -#define OTP_SW_LOCK50_SEC_MSB _u(1) -#define OTP_SW_LOCK50_SEC_LSB _u(0) -#define OTP_SW_LOCK50_SEC_ACCESS "RW" -#define OTP_SW_LOCK50_SEC_VALUE_READ_WRITE _u(0x0) -#define OTP_SW_LOCK50_SEC_VALUE_READ_ONLY _u(0x1) -#define OTP_SW_LOCK50_SEC_VALUE_INACCESSIBLE _u(0x3) -// ============================================================================= -// Register : OTP_SW_LOCK51 -// Description : Software lock register for page 51. -// -// Locks are initialised from the OTP lock pages at reset. This -// register can be written to further advance the lock state of -// each page (until next reset), and read to check the current -// lock state of a page. -#define OTP_SW_LOCK51_OFFSET _u(0x000000cc) -#define OTP_SW_LOCK51_BITS _u(0x0000000f) -#define OTP_SW_LOCK51_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : OTP_SW_LOCK51_NSEC -// Description : Non-secure lock status. Writes are OR'd with the current value. -// 0x0 -> read_write -// 0x1 -> read_only -// 0x3 -> inaccessible -#define OTP_SW_LOCK51_NSEC_RESET "-" -#define OTP_SW_LOCK51_NSEC_BITS _u(0x0000000c) -#define OTP_SW_LOCK51_NSEC_MSB _u(3) -#define OTP_SW_LOCK51_NSEC_LSB _u(2) -#define OTP_SW_LOCK51_NSEC_ACCESS "RW" -#define OTP_SW_LOCK51_NSEC_VALUE_READ_WRITE _u(0x0) -#define OTP_SW_LOCK51_NSEC_VALUE_READ_ONLY _u(0x1) -#define OTP_SW_LOCK51_NSEC_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_SW_LOCK51_SEC -// Description : Secure lock status. Writes are OR'd with the current value. -// This field is read-only to Non-secure code. -// 0x0 -> read_write -// 0x1 -> read_only -// 0x3 -> inaccessible -#define OTP_SW_LOCK51_SEC_RESET "-" -#define OTP_SW_LOCK51_SEC_BITS _u(0x00000003) -#define OTP_SW_LOCK51_SEC_MSB _u(1) -#define OTP_SW_LOCK51_SEC_LSB _u(0) -#define OTP_SW_LOCK51_SEC_ACCESS "RW" -#define OTP_SW_LOCK51_SEC_VALUE_READ_WRITE _u(0x0) -#define OTP_SW_LOCK51_SEC_VALUE_READ_ONLY _u(0x1) -#define OTP_SW_LOCK51_SEC_VALUE_INACCESSIBLE _u(0x3) -// ============================================================================= -// Register : OTP_SW_LOCK52 -// Description : Software lock register for page 52. -// -// Locks are initialised from the OTP lock pages at reset. This -// register can be written to further advance the lock state of -// each page (until next reset), and read to check the current -// lock state of a page. -#define OTP_SW_LOCK52_OFFSET _u(0x000000d0) -#define OTP_SW_LOCK52_BITS _u(0x0000000f) -#define OTP_SW_LOCK52_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : OTP_SW_LOCK52_NSEC -// Description : Non-secure lock status. Writes are OR'd with the current value. -// 0x0 -> read_write -// 0x1 -> read_only -// 0x3 -> inaccessible -#define OTP_SW_LOCK52_NSEC_RESET "-" -#define OTP_SW_LOCK52_NSEC_BITS _u(0x0000000c) -#define OTP_SW_LOCK52_NSEC_MSB _u(3) -#define OTP_SW_LOCK52_NSEC_LSB _u(2) -#define OTP_SW_LOCK52_NSEC_ACCESS "RW" -#define OTP_SW_LOCK52_NSEC_VALUE_READ_WRITE _u(0x0) -#define OTP_SW_LOCK52_NSEC_VALUE_READ_ONLY _u(0x1) -#define OTP_SW_LOCK52_NSEC_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_SW_LOCK52_SEC -// Description : Secure lock status. Writes are OR'd with the current value. -// This field is read-only to Non-secure code. -// 0x0 -> read_write -// 0x1 -> read_only -// 0x3 -> inaccessible -#define OTP_SW_LOCK52_SEC_RESET "-" -#define OTP_SW_LOCK52_SEC_BITS _u(0x00000003) -#define OTP_SW_LOCK52_SEC_MSB _u(1) -#define OTP_SW_LOCK52_SEC_LSB _u(0) -#define OTP_SW_LOCK52_SEC_ACCESS "RW" -#define OTP_SW_LOCK52_SEC_VALUE_READ_WRITE _u(0x0) -#define OTP_SW_LOCK52_SEC_VALUE_READ_ONLY _u(0x1) -#define OTP_SW_LOCK52_SEC_VALUE_INACCESSIBLE _u(0x3) -// ============================================================================= -// Register : OTP_SW_LOCK53 -// Description : Software lock register for page 53. -// -// Locks are initialised from the OTP lock pages at reset. This -// register can be written to further advance the lock state of -// each page (until next reset), and read to check the current -// lock state of a page. -#define OTP_SW_LOCK53_OFFSET _u(0x000000d4) -#define OTP_SW_LOCK53_BITS _u(0x0000000f) -#define OTP_SW_LOCK53_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : OTP_SW_LOCK53_NSEC -// Description : Non-secure lock status. Writes are OR'd with the current value. -// 0x0 -> read_write -// 0x1 -> read_only -// 0x3 -> inaccessible -#define OTP_SW_LOCK53_NSEC_RESET "-" -#define OTP_SW_LOCK53_NSEC_BITS _u(0x0000000c) -#define OTP_SW_LOCK53_NSEC_MSB _u(3) -#define OTP_SW_LOCK53_NSEC_LSB _u(2) -#define OTP_SW_LOCK53_NSEC_ACCESS "RW" -#define OTP_SW_LOCK53_NSEC_VALUE_READ_WRITE _u(0x0) -#define OTP_SW_LOCK53_NSEC_VALUE_READ_ONLY _u(0x1) -#define OTP_SW_LOCK53_NSEC_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_SW_LOCK53_SEC -// Description : Secure lock status. Writes are OR'd with the current value. -// This field is read-only to Non-secure code. -// 0x0 -> read_write -// 0x1 -> read_only -// 0x3 -> inaccessible -#define OTP_SW_LOCK53_SEC_RESET "-" -#define OTP_SW_LOCK53_SEC_BITS _u(0x00000003) -#define OTP_SW_LOCK53_SEC_MSB _u(1) -#define OTP_SW_LOCK53_SEC_LSB _u(0) -#define OTP_SW_LOCK53_SEC_ACCESS "RW" -#define OTP_SW_LOCK53_SEC_VALUE_READ_WRITE _u(0x0) -#define OTP_SW_LOCK53_SEC_VALUE_READ_ONLY _u(0x1) -#define OTP_SW_LOCK53_SEC_VALUE_INACCESSIBLE _u(0x3) -// ============================================================================= -// Register : OTP_SW_LOCK54 -// Description : Software lock register for page 54. -// -// Locks are initialised from the OTP lock pages at reset. This -// register can be written to further advance the lock state of -// each page (until next reset), and read to check the current -// lock state of a page. -#define OTP_SW_LOCK54_OFFSET _u(0x000000d8) -#define OTP_SW_LOCK54_BITS _u(0x0000000f) -#define OTP_SW_LOCK54_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : OTP_SW_LOCK54_NSEC -// Description : Non-secure lock status. Writes are OR'd with the current value. -// 0x0 -> read_write -// 0x1 -> read_only -// 0x3 -> inaccessible -#define OTP_SW_LOCK54_NSEC_RESET "-" -#define OTP_SW_LOCK54_NSEC_BITS _u(0x0000000c) -#define OTP_SW_LOCK54_NSEC_MSB _u(3) -#define OTP_SW_LOCK54_NSEC_LSB _u(2) -#define OTP_SW_LOCK54_NSEC_ACCESS "RW" -#define OTP_SW_LOCK54_NSEC_VALUE_READ_WRITE _u(0x0) -#define OTP_SW_LOCK54_NSEC_VALUE_READ_ONLY _u(0x1) -#define OTP_SW_LOCK54_NSEC_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_SW_LOCK54_SEC -// Description : Secure lock status. Writes are OR'd with the current value. -// This field is read-only to Non-secure code. -// 0x0 -> read_write -// 0x1 -> read_only -// 0x3 -> inaccessible -#define OTP_SW_LOCK54_SEC_RESET "-" -#define OTP_SW_LOCK54_SEC_BITS _u(0x00000003) -#define OTP_SW_LOCK54_SEC_MSB _u(1) -#define OTP_SW_LOCK54_SEC_LSB _u(0) -#define OTP_SW_LOCK54_SEC_ACCESS "RW" -#define OTP_SW_LOCK54_SEC_VALUE_READ_WRITE _u(0x0) -#define OTP_SW_LOCK54_SEC_VALUE_READ_ONLY _u(0x1) -#define OTP_SW_LOCK54_SEC_VALUE_INACCESSIBLE _u(0x3) -// ============================================================================= -// Register : OTP_SW_LOCK55 -// Description : Software lock register for page 55. -// -// Locks are initialised from the OTP lock pages at reset. This -// register can be written to further advance the lock state of -// each page (until next reset), and read to check the current -// lock state of a page. -#define OTP_SW_LOCK55_OFFSET _u(0x000000dc) -#define OTP_SW_LOCK55_BITS _u(0x0000000f) -#define OTP_SW_LOCK55_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : OTP_SW_LOCK55_NSEC -// Description : Non-secure lock status. Writes are OR'd with the current value. -// 0x0 -> read_write -// 0x1 -> read_only -// 0x3 -> inaccessible -#define OTP_SW_LOCK55_NSEC_RESET "-" -#define OTP_SW_LOCK55_NSEC_BITS _u(0x0000000c) -#define OTP_SW_LOCK55_NSEC_MSB _u(3) -#define OTP_SW_LOCK55_NSEC_LSB _u(2) -#define OTP_SW_LOCK55_NSEC_ACCESS "RW" -#define OTP_SW_LOCK55_NSEC_VALUE_READ_WRITE _u(0x0) -#define OTP_SW_LOCK55_NSEC_VALUE_READ_ONLY _u(0x1) -#define OTP_SW_LOCK55_NSEC_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_SW_LOCK55_SEC -// Description : Secure lock status. Writes are OR'd with the current value. -// This field is read-only to Non-secure code. -// 0x0 -> read_write -// 0x1 -> read_only -// 0x3 -> inaccessible -#define OTP_SW_LOCK55_SEC_RESET "-" -#define OTP_SW_LOCK55_SEC_BITS _u(0x00000003) -#define OTP_SW_LOCK55_SEC_MSB _u(1) -#define OTP_SW_LOCK55_SEC_LSB _u(0) -#define OTP_SW_LOCK55_SEC_ACCESS "RW" -#define OTP_SW_LOCK55_SEC_VALUE_READ_WRITE _u(0x0) -#define OTP_SW_LOCK55_SEC_VALUE_READ_ONLY _u(0x1) -#define OTP_SW_LOCK55_SEC_VALUE_INACCESSIBLE _u(0x3) -// ============================================================================= -// Register : OTP_SW_LOCK56 -// Description : Software lock register for page 56. -// -// Locks are initialised from the OTP lock pages at reset. This -// register can be written to further advance the lock state of -// each page (until next reset), and read to check the current -// lock state of a page. -#define OTP_SW_LOCK56_OFFSET _u(0x000000e0) -#define OTP_SW_LOCK56_BITS _u(0x0000000f) -#define OTP_SW_LOCK56_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : OTP_SW_LOCK56_NSEC -// Description : Non-secure lock status. Writes are OR'd with the current value. -// 0x0 -> read_write -// 0x1 -> read_only -// 0x3 -> inaccessible -#define OTP_SW_LOCK56_NSEC_RESET "-" -#define OTP_SW_LOCK56_NSEC_BITS _u(0x0000000c) -#define OTP_SW_LOCK56_NSEC_MSB _u(3) -#define OTP_SW_LOCK56_NSEC_LSB _u(2) -#define OTP_SW_LOCK56_NSEC_ACCESS "RW" -#define OTP_SW_LOCK56_NSEC_VALUE_READ_WRITE _u(0x0) -#define OTP_SW_LOCK56_NSEC_VALUE_READ_ONLY _u(0x1) -#define OTP_SW_LOCK56_NSEC_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_SW_LOCK56_SEC -// Description : Secure lock status. Writes are OR'd with the current value. -// This field is read-only to Non-secure code. -// 0x0 -> read_write -// 0x1 -> read_only -// 0x3 -> inaccessible -#define OTP_SW_LOCK56_SEC_RESET "-" -#define OTP_SW_LOCK56_SEC_BITS _u(0x00000003) -#define OTP_SW_LOCK56_SEC_MSB _u(1) -#define OTP_SW_LOCK56_SEC_LSB _u(0) -#define OTP_SW_LOCK56_SEC_ACCESS "RW" -#define OTP_SW_LOCK56_SEC_VALUE_READ_WRITE _u(0x0) -#define OTP_SW_LOCK56_SEC_VALUE_READ_ONLY _u(0x1) -#define OTP_SW_LOCK56_SEC_VALUE_INACCESSIBLE _u(0x3) -// ============================================================================= -// Register : OTP_SW_LOCK57 -// Description : Software lock register for page 57. -// -// Locks are initialised from the OTP lock pages at reset. This -// register can be written to further advance the lock state of -// each page (until next reset), and read to check the current -// lock state of a page. -#define OTP_SW_LOCK57_OFFSET _u(0x000000e4) -#define OTP_SW_LOCK57_BITS _u(0x0000000f) -#define OTP_SW_LOCK57_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : OTP_SW_LOCK57_NSEC -// Description : Non-secure lock status. Writes are OR'd with the current value. -// 0x0 -> read_write -// 0x1 -> read_only -// 0x3 -> inaccessible -#define OTP_SW_LOCK57_NSEC_RESET "-" -#define OTP_SW_LOCK57_NSEC_BITS _u(0x0000000c) -#define OTP_SW_LOCK57_NSEC_MSB _u(3) -#define OTP_SW_LOCK57_NSEC_LSB _u(2) -#define OTP_SW_LOCK57_NSEC_ACCESS "RW" -#define OTP_SW_LOCK57_NSEC_VALUE_READ_WRITE _u(0x0) -#define OTP_SW_LOCK57_NSEC_VALUE_READ_ONLY _u(0x1) -#define OTP_SW_LOCK57_NSEC_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_SW_LOCK57_SEC -// Description : Secure lock status. Writes are OR'd with the current value. -// This field is read-only to Non-secure code. -// 0x0 -> read_write -// 0x1 -> read_only -// 0x3 -> inaccessible -#define OTP_SW_LOCK57_SEC_RESET "-" -#define OTP_SW_LOCK57_SEC_BITS _u(0x00000003) -#define OTP_SW_LOCK57_SEC_MSB _u(1) -#define OTP_SW_LOCK57_SEC_LSB _u(0) -#define OTP_SW_LOCK57_SEC_ACCESS "RW" -#define OTP_SW_LOCK57_SEC_VALUE_READ_WRITE _u(0x0) -#define OTP_SW_LOCK57_SEC_VALUE_READ_ONLY _u(0x1) -#define OTP_SW_LOCK57_SEC_VALUE_INACCESSIBLE _u(0x3) -// ============================================================================= -// Register : OTP_SW_LOCK58 -// Description : Software lock register for page 58. -// -// Locks are initialised from the OTP lock pages at reset. This -// register can be written to further advance the lock state of -// each page (until next reset), and read to check the current -// lock state of a page. -#define OTP_SW_LOCK58_OFFSET _u(0x000000e8) -#define OTP_SW_LOCK58_BITS _u(0x0000000f) -#define OTP_SW_LOCK58_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : OTP_SW_LOCK58_NSEC -// Description : Non-secure lock status. Writes are OR'd with the current value. -// 0x0 -> read_write -// 0x1 -> read_only -// 0x3 -> inaccessible -#define OTP_SW_LOCK58_NSEC_RESET "-" -#define OTP_SW_LOCK58_NSEC_BITS _u(0x0000000c) -#define OTP_SW_LOCK58_NSEC_MSB _u(3) -#define OTP_SW_LOCK58_NSEC_LSB _u(2) -#define OTP_SW_LOCK58_NSEC_ACCESS "RW" -#define OTP_SW_LOCK58_NSEC_VALUE_READ_WRITE _u(0x0) -#define OTP_SW_LOCK58_NSEC_VALUE_READ_ONLY _u(0x1) -#define OTP_SW_LOCK58_NSEC_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_SW_LOCK58_SEC -// Description : Secure lock status. Writes are OR'd with the current value. -// This field is read-only to Non-secure code. -// 0x0 -> read_write -// 0x1 -> read_only -// 0x3 -> inaccessible -#define OTP_SW_LOCK58_SEC_RESET "-" -#define OTP_SW_LOCK58_SEC_BITS _u(0x00000003) -#define OTP_SW_LOCK58_SEC_MSB _u(1) -#define OTP_SW_LOCK58_SEC_LSB _u(0) -#define OTP_SW_LOCK58_SEC_ACCESS "RW" -#define OTP_SW_LOCK58_SEC_VALUE_READ_WRITE _u(0x0) -#define OTP_SW_LOCK58_SEC_VALUE_READ_ONLY _u(0x1) -#define OTP_SW_LOCK58_SEC_VALUE_INACCESSIBLE _u(0x3) -// ============================================================================= -// Register : OTP_SW_LOCK59 -// Description : Software lock register for page 59. -// -// Locks are initialised from the OTP lock pages at reset. This -// register can be written to further advance the lock state of -// each page (until next reset), and read to check the current -// lock state of a page. -#define OTP_SW_LOCK59_OFFSET _u(0x000000ec) -#define OTP_SW_LOCK59_BITS _u(0x0000000f) -#define OTP_SW_LOCK59_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : OTP_SW_LOCK59_NSEC -// Description : Non-secure lock status. Writes are OR'd with the current value. -// 0x0 -> read_write -// 0x1 -> read_only -// 0x3 -> inaccessible -#define OTP_SW_LOCK59_NSEC_RESET "-" -#define OTP_SW_LOCK59_NSEC_BITS _u(0x0000000c) -#define OTP_SW_LOCK59_NSEC_MSB _u(3) -#define OTP_SW_LOCK59_NSEC_LSB _u(2) -#define OTP_SW_LOCK59_NSEC_ACCESS "RW" -#define OTP_SW_LOCK59_NSEC_VALUE_READ_WRITE _u(0x0) -#define OTP_SW_LOCK59_NSEC_VALUE_READ_ONLY _u(0x1) -#define OTP_SW_LOCK59_NSEC_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_SW_LOCK59_SEC -// Description : Secure lock status. Writes are OR'd with the current value. -// This field is read-only to Non-secure code. -// 0x0 -> read_write -// 0x1 -> read_only -// 0x3 -> inaccessible -#define OTP_SW_LOCK59_SEC_RESET "-" -#define OTP_SW_LOCK59_SEC_BITS _u(0x00000003) -#define OTP_SW_LOCK59_SEC_MSB _u(1) -#define OTP_SW_LOCK59_SEC_LSB _u(0) -#define OTP_SW_LOCK59_SEC_ACCESS "RW" -#define OTP_SW_LOCK59_SEC_VALUE_READ_WRITE _u(0x0) -#define OTP_SW_LOCK59_SEC_VALUE_READ_ONLY _u(0x1) -#define OTP_SW_LOCK59_SEC_VALUE_INACCESSIBLE _u(0x3) -// ============================================================================= -// Register : OTP_SW_LOCK60 -// Description : Software lock register for page 60. -// -// Locks are initialised from the OTP lock pages at reset. This -// register can be written to further advance the lock state of -// each page (until next reset), and read to check the current -// lock state of a page. -#define OTP_SW_LOCK60_OFFSET _u(0x000000f0) -#define OTP_SW_LOCK60_BITS _u(0x0000000f) -#define OTP_SW_LOCK60_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : OTP_SW_LOCK60_NSEC -// Description : Non-secure lock status. Writes are OR'd with the current value. -// 0x0 -> read_write -// 0x1 -> read_only -// 0x3 -> inaccessible -#define OTP_SW_LOCK60_NSEC_RESET "-" -#define OTP_SW_LOCK60_NSEC_BITS _u(0x0000000c) -#define OTP_SW_LOCK60_NSEC_MSB _u(3) -#define OTP_SW_LOCK60_NSEC_LSB _u(2) -#define OTP_SW_LOCK60_NSEC_ACCESS "RW" -#define OTP_SW_LOCK60_NSEC_VALUE_READ_WRITE _u(0x0) -#define OTP_SW_LOCK60_NSEC_VALUE_READ_ONLY _u(0x1) -#define OTP_SW_LOCK60_NSEC_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_SW_LOCK60_SEC -// Description : Secure lock status. Writes are OR'd with the current value. -// This field is read-only to Non-secure code. -// 0x0 -> read_write -// 0x1 -> read_only -// 0x3 -> inaccessible -#define OTP_SW_LOCK60_SEC_RESET "-" -#define OTP_SW_LOCK60_SEC_BITS _u(0x00000003) -#define OTP_SW_LOCK60_SEC_MSB _u(1) -#define OTP_SW_LOCK60_SEC_LSB _u(0) -#define OTP_SW_LOCK60_SEC_ACCESS "RW" -#define OTP_SW_LOCK60_SEC_VALUE_READ_WRITE _u(0x0) -#define OTP_SW_LOCK60_SEC_VALUE_READ_ONLY _u(0x1) -#define OTP_SW_LOCK60_SEC_VALUE_INACCESSIBLE _u(0x3) -// ============================================================================= -// Register : OTP_SW_LOCK61 -// Description : Software lock register for page 61. -// -// Locks are initialised from the OTP lock pages at reset. This -// register can be written to further advance the lock state of -// each page (until next reset), and read to check the current -// lock state of a page. -#define OTP_SW_LOCK61_OFFSET _u(0x000000f4) -#define OTP_SW_LOCK61_BITS _u(0x0000000f) -#define OTP_SW_LOCK61_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : OTP_SW_LOCK61_NSEC -// Description : Non-secure lock status. Writes are OR'd with the current value. -// 0x0 -> read_write -// 0x1 -> read_only -// 0x3 -> inaccessible -#define OTP_SW_LOCK61_NSEC_RESET "-" -#define OTP_SW_LOCK61_NSEC_BITS _u(0x0000000c) -#define OTP_SW_LOCK61_NSEC_MSB _u(3) -#define OTP_SW_LOCK61_NSEC_LSB _u(2) -#define OTP_SW_LOCK61_NSEC_ACCESS "RW" -#define OTP_SW_LOCK61_NSEC_VALUE_READ_WRITE _u(0x0) -#define OTP_SW_LOCK61_NSEC_VALUE_READ_ONLY _u(0x1) -#define OTP_SW_LOCK61_NSEC_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_SW_LOCK61_SEC -// Description : Secure lock status. Writes are OR'd with the current value. -// This field is read-only to Non-secure code. -// 0x0 -> read_write -// 0x1 -> read_only -// 0x3 -> inaccessible -#define OTP_SW_LOCK61_SEC_RESET "-" -#define OTP_SW_LOCK61_SEC_BITS _u(0x00000003) -#define OTP_SW_LOCK61_SEC_MSB _u(1) -#define OTP_SW_LOCK61_SEC_LSB _u(0) -#define OTP_SW_LOCK61_SEC_ACCESS "RW" -#define OTP_SW_LOCK61_SEC_VALUE_READ_WRITE _u(0x0) -#define OTP_SW_LOCK61_SEC_VALUE_READ_ONLY _u(0x1) -#define OTP_SW_LOCK61_SEC_VALUE_INACCESSIBLE _u(0x3) -// ============================================================================= -// Register : OTP_SW_LOCK62 -// Description : Software lock register for page 62. -// -// Locks are initialised from the OTP lock pages at reset. This -// register can be written to further advance the lock state of -// each page (until next reset), and read to check the current -// lock state of a page. -#define OTP_SW_LOCK62_OFFSET _u(0x000000f8) -#define OTP_SW_LOCK62_BITS _u(0x0000000f) -#define OTP_SW_LOCK62_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : OTP_SW_LOCK62_NSEC -// Description : Non-secure lock status. Writes are OR'd with the current value. -// 0x0 -> read_write -// 0x1 -> read_only -// 0x3 -> inaccessible -#define OTP_SW_LOCK62_NSEC_RESET "-" -#define OTP_SW_LOCK62_NSEC_BITS _u(0x0000000c) -#define OTP_SW_LOCK62_NSEC_MSB _u(3) -#define OTP_SW_LOCK62_NSEC_LSB _u(2) -#define OTP_SW_LOCK62_NSEC_ACCESS "RW" -#define OTP_SW_LOCK62_NSEC_VALUE_READ_WRITE _u(0x0) -#define OTP_SW_LOCK62_NSEC_VALUE_READ_ONLY _u(0x1) -#define OTP_SW_LOCK62_NSEC_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_SW_LOCK62_SEC -// Description : Secure lock status. Writes are OR'd with the current value. -// This field is read-only to Non-secure code. -// 0x0 -> read_write -// 0x1 -> read_only -// 0x3 -> inaccessible -#define OTP_SW_LOCK62_SEC_RESET "-" -#define OTP_SW_LOCK62_SEC_BITS _u(0x00000003) -#define OTP_SW_LOCK62_SEC_MSB _u(1) -#define OTP_SW_LOCK62_SEC_LSB _u(0) -#define OTP_SW_LOCK62_SEC_ACCESS "RW" -#define OTP_SW_LOCK62_SEC_VALUE_READ_WRITE _u(0x0) -#define OTP_SW_LOCK62_SEC_VALUE_READ_ONLY _u(0x1) -#define OTP_SW_LOCK62_SEC_VALUE_INACCESSIBLE _u(0x3) -// ============================================================================= -// Register : OTP_SW_LOCK63 -// Description : Software lock register for page 63. -// -// Locks are initialised from the OTP lock pages at reset. This -// register can be written to further advance the lock state of -// each page (until next reset), and read to check the current -// lock state of a page. -#define OTP_SW_LOCK63_OFFSET _u(0x000000fc) -#define OTP_SW_LOCK63_BITS _u(0x0000000f) -#define OTP_SW_LOCK63_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : OTP_SW_LOCK63_NSEC -// Description : Non-secure lock status. Writes are OR'd with the current value. -// 0x0 -> read_write -// 0x1 -> read_only -// 0x3 -> inaccessible -#define OTP_SW_LOCK63_NSEC_RESET "-" -#define OTP_SW_LOCK63_NSEC_BITS _u(0x0000000c) -#define OTP_SW_LOCK63_NSEC_MSB _u(3) -#define OTP_SW_LOCK63_NSEC_LSB _u(2) -#define OTP_SW_LOCK63_NSEC_ACCESS "RW" -#define OTP_SW_LOCK63_NSEC_VALUE_READ_WRITE _u(0x0) -#define OTP_SW_LOCK63_NSEC_VALUE_READ_ONLY _u(0x1) -#define OTP_SW_LOCK63_NSEC_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_SW_LOCK63_SEC -// Description : Secure lock status. Writes are OR'd with the current value. -// This field is read-only to Non-secure code. -// 0x0 -> read_write -// 0x1 -> read_only -// 0x3 -> inaccessible -#define OTP_SW_LOCK63_SEC_RESET "-" -#define OTP_SW_LOCK63_SEC_BITS _u(0x00000003) -#define OTP_SW_LOCK63_SEC_MSB _u(1) -#define OTP_SW_LOCK63_SEC_LSB _u(0) -#define OTP_SW_LOCK63_SEC_ACCESS "RW" -#define OTP_SW_LOCK63_SEC_VALUE_READ_WRITE _u(0x0) -#define OTP_SW_LOCK63_SEC_VALUE_READ_ONLY _u(0x1) -#define OTP_SW_LOCK63_SEC_VALUE_INACCESSIBLE _u(0x3) -// ============================================================================= -// Register : OTP_SBPI_INSTR -// Description : Dispatch instructions to the SBPI interface, used for -// programming the OTP fuses. -#define OTP_SBPI_INSTR_OFFSET _u(0x00000100) -#define OTP_SBPI_INSTR_BITS _u(0x7fffffff) -#define OTP_SBPI_INSTR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : OTP_SBPI_INSTR_EXEC -// Description : Execute instruction -#define OTP_SBPI_INSTR_EXEC_RESET _u(0x0) -#define OTP_SBPI_INSTR_EXEC_BITS _u(0x40000000) -#define OTP_SBPI_INSTR_EXEC_MSB _u(30) -#define OTP_SBPI_INSTR_EXEC_LSB _u(30) -#define OTP_SBPI_INSTR_EXEC_ACCESS "SC" -// ----------------------------------------------------------------------------- -// Field : OTP_SBPI_INSTR_IS_WR -// Description : Payload type is write -#define OTP_SBPI_INSTR_IS_WR_RESET _u(0x0) -#define OTP_SBPI_INSTR_IS_WR_BITS _u(0x20000000) -#define OTP_SBPI_INSTR_IS_WR_MSB _u(29) -#define OTP_SBPI_INSTR_IS_WR_LSB _u(29) -#define OTP_SBPI_INSTR_IS_WR_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : OTP_SBPI_INSTR_HAS_PAYLOAD -// Description : Instruction has payload (data to be written or to be read) -#define OTP_SBPI_INSTR_HAS_PAYLOAD_RESET _u(0x0) -#define OTP_SBPI_INSTR_HAS_PAYLOAD_BITS _u(0x10000000) -#define OTP_SBPI_INSTR_HAS_PAYLOAD_MSB _u(28) -#define OTP_SBPI_INSTR_HAS_PAYLOAD_LSB _u(28) -#define OTP_SBPI_INSTR_HAS_PAYLOAD_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : OTP_SBPI_INSTR_PAYLOAD_SIZE_M1 -// Description : Instruction payload size in bytes minus 1 -#define OTP_SBPI_INSTR_PAYLOAD_SIZE_M1_RESET _u(0x0) -#define OTP_SBPI_INSTR_PAYLOAD_SIZE_M1_BITS _u(0x0f000000) -#define OTP_SBPI_INSTR_PAYLOAD_SIZE_M1_MSB _u(27) -#define OTP_SBPI_INSTR_PAYLOAD_SIZE_M1_LSB _u(24) -#define OTP_SBPI_INSTR_PAYLOAD_SIZE_M1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : OTP_SBPI_INSTR_TARGET -// Description : Instruction target, it can be PMC (0x3a) or DAP (0x02) -#define OTP_SBPI_INSTR_TARGET_RESET _u(0x00) -#define OTP_SBPI_INSTR_TARGET_BITS _u(0x00ff0000) -#define OTP_SBPI_INSTR_TARGET_MSB _u(23) -#define OTP_SBPI_INSTR_TARGET_LSB _u(16) -#define OTP_SBPI_INSTR_TARGET_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : OTP_SBPI_INSTR_CMD -#define OTP_SBPI_INSTR_CMD_RESET _u(0x00) -#define OTP_SBPI_INSTR_CMD_BITS _u(0x0000ff00) -#define OTP_SBPI_INSTR_CMD_MSB _u(15) -#define OTP_SBPI_INSTR_CMD_LSB _u(8) -#define OTP_SBPI_INSTR_CMD_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : OTP_SBPI_INSTR_SHORT_WDATA -// Description : wdata to be used only when payload_size_m1=0 -#define OTP_SBPI_INSTR_SHORT_WDATA_RESET _u(0x00) -#define OTP_SBPI_INSTR_SHORT_WDATA_BITS _u(0x000000ff) -#define OTP_SBPI_INSTR_SHORT_WDATA_MSB _u(7) -#define OTP_SBPI_INSTR_SHORT_WDATA_LSB _u(0) -#define OTP_SBPI_INSTR_SHORT_WDATA_ACCESS "RW" -// ============================================================================= -// Register : OTP_SBPI_WDATA_0 -// Description : SBPI write payload bytes 3..0 -#define OTP_SBPI_WDATA_0_OFFSET _u(0x00000104) -#define OTP_SBPI_WDATA_0_BITS _u(0xffffffff) -#define OTP_SBPI_WDATA_0_RESET _u(0x00000000) -#define OTP_SBPI_WDATA_0_MSB _u(31) -#define OTP_SBPI_WDATA_0_LSB _u(0) -#define OTP_SBPI_WDATA_0_ACCESS "RW" -// ============================================================================= -// Register : OTP_SBPI_WDATA_1 -// Description : SBPI write payload bytes 7..4 -#define OTP_SBPI_WDATA_1_OFFSET _u(0x00000108) -#define OTP_SBPI_WDATA_1_BITS _u(0xffffffff) -#define OTP_SBPI_WDATA_1_RESET _u(0x00000000) -#define OTP_SBPI_WDATA_1_MSB _u(31) -#define OTP_SBPI_WDATA_1_LSB _u(0) -#define OTP_SBPI_WDATA_1_ACCESS "RW" -// ============================================================================= -// Register : OTP_SBPI_WDATA_2 -// Description : SBPI write payload bytes 11..8 -#define OTP_SBPI_WDATA_2_OFFSET _u(0x0000010c) -#define OTP_SBPI_WDATA_2_BITS _u(0xffffffff) -#define OTP_SBPI_WDATA_2_RESET _u(0x00000000) -#define OTP_SBPI_WDATA_2_MSB _u(31) -#define OTP_SBPI_WDATA_2_LSB _u(0) -#define OTP_SBPI_WDATA_2_ACCESS "RW" -// ============================================================================= -// Register : OTP_SBPI_WDATA_3 -// Description : SBPI write payload bytes 15..12 -#define OTP_SBPI_WDATA_3_OFFSET _u(0x00000110) -#define OTP_SBPI_WDATA_3_BITS _u(0xffffffff) -#define OTP_SBPI_WDATA_3_RESET _u(0x00000000) -#define OTP_SBPI_WDATA_3_MSB _u(31) -#define OTP_SBPI_WDATA_3_LSB _u(0) -#define OTP_SBPI_WDATA_3_ACCESS "RW" -// ============================================================================= -// Register : OTP_SBPI_RDATA_0 -// Description : Read payload bytes 3..0. Once read, the data in the register -// will automatically clear to 0. -#define OTP_SBPI_RDATA_0_OFFSET _u(0x00000114) -#define OTP_SBPI_RDATA_0_BITS _u(0xffffffff) -#define OTP_SBPI_RDATA_0_RESET _u(0x00000000) -#define OTP_SBPI_RDATA_0_MSB _u(31) -#define OTP_SBPI_RDATA_0_LSB _u(0) -#define OTP_SBPI_RDATA_0_ACCESS "RO" -// ============================================================================= -// Register : OTP_SBPI_RDATA_1 -// Description : Read payload bytes 7..4. Once read, the data in the register -// will automatically clear to 0. -#define OTP_SBPI_RDATA_1_OFFSET _u(0x00000118) -#define OTP_SBPI_RDATA_1_BITS _u(0xffffffff) -#define OTP_SBPI_RDATA_1_RESET _u(0x00000000) -#define OTP_SBPI_RDATA_1_MSB _u(31) -#define OTP_SBPI_RDATA_1_LSB _u(0) -#define OTP_SBPI_RDATA_1_ACCESS "RO" -// ============================================================================= -// Register : OTP_SBPI_RDATA_2 -// Description : Read payload bytes 11..8. Once read, the data in the register -// will automatically clear to 0. -#define OTP_SBPI_RDATA_2_OFFSET _u(0x0000011c) -#define OTP_SBPI_RDATA_2_BITS _u(0xffffffff) -#define OTP_SBPI_RDATA_2_RESET _u(0x00000000) -#define OTP_SBPI_RDATA_2_MSB _u(31) -#define OTP_SBPI_RDATA_2_LSB _u(0) -#define OTP_SBPI_RDATA_2_ACCESS "RO" -// ============================================================================= -// Register : OTP_SBPI_RDATA_3 -// Description : Read payload bytes 15..12. Once read, the data in the register -// will automatically clear to 0. -#define OTP_SBPI_RDATA_3_OFFSET _u(0x00000120) -#define OTP_SBPI_RDATA_3_BITS _u(0xffffffff) -#define OTP_SBPI_RDATA_3_RESET _u(0x00000000) -#define OTP_SBPI_RDATA_3_MSB _u(31) -#define OTP_SBPI_RDATA_3_LSB _u(0) -#define OTP_SBPI_RDATA_3_ACCESS "RO" -// ============================================================================= -// Register : OTP_SBPI_STATUS -#define OTP_SBPI_STATUS_OFFSET _u(0x00000124) -#define OTP_SBPI_STATUS_BITS _u(0x00ff1111) -#define OTP_SBPI_STATUS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : OTP_SBPI_STATUS_MISO -// Description : SBPI MISO (master in - slave out): response from SBPI -#define OTP_SBPI_STATUS_MISO_RESET "-" -#define OTP_SBPI_STATUS_MISO_BITS _u(0x00ff0000) -#define OTP_SBPI_STATUS_MISO_MSB _u(23) -#define OTP_SBPI_STATUS_MISO_LSB _u(16) -#define OTP_SBPI_STATUS_MISO_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_SBPI_STATUS_FLAG -// Description : SBPI flag -#define OTP_SBPI_STATUS_FLAG_RESET "-" -#define OTP_SBPI_STATUS_FLAG_BITS _u(0x00001000) -#define OTP_SBPI_STATUS_FLAG_MSB _u(12) -#define OTP_SBPI_STATUS_FLAG_LSB _u(12) -#define OTP_SBPI_STATUS_FLAG_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_SBPI_STATUS_INSTR_MISS -// Description : Last instruction missed (dropped), as the previous has not -// finished running -#define OTP_SBPI_STATUS_INSTR_MISS_RESET _u(0x0) -#define OTP_SBPI_STATUS_INSTR_MISS_BITS _u(0x00000100) -#define OTP_SBPI_STATUS_INSTR_MISS_MSB _u(8) -#define OTP_SBPI_STATUS_INSTR_MISS_LSB _u(8) -#define OTP_SBPI_STATUS_INSTR_MISS_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : OTP_SBPI_STATUS_INSTR_DONE -// Description : Last instruction done -#define OTP_SBPI_STATUS_INSTR_DONE_RESET _u(0x0) -#define OTP_SBPI_STATUS_INSTR_DONE_BITS _u(0x00000010) -#define OTP_SBPI_STATUS_INSTR_DONE_MSB _u(4) -#define OTP_SBPI_STATUS_INSTR_DONE_LSB _u(4) -#define OTP_SBPI_STATUS_INSTR_DONE_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : OTP_SBPI_STATUS_RDATA_VLD -// Description : Read command has returned data -#define OTP_SBPI_STATUS_RDATA_VLD_RESET _u(0x0) -#define OTP_SBPI_STATUS_RDATA_VLD_BITS _u(0x00000001) -#define OTP_SBPI_STATUS_RDATA_VLD_MSB _u(0) -#define OTP_SBPI_STATUS_RDATA_VLD_LSB _u(0) -#define OTP_SBPI_STATUS_RDATA_VLD_ACCESS "WC" -// ============================================================================= -// Register : OTP_USR -// Description : Controls for APB data read interface (USER interface) -#define OTP_USR_OFFSET _u(0x00000128) -#define OTP_USR_BITS _u(0x00000011) -#define OTP_USR_RESET _u(0x00000001) -// ----------------------------------------------------------------------------- -// Field : OTP_USR_PD -// Description : Power-down; 1 disables current reference. Must be 0 to read -// data from the OTP. -#define OTP_USR_PD_RESET _u(0x0) -#define OTP_USR_PD_BITS _u(0x00000010) -#define OTP_USR_PD_MSB _u(4) -#define OTP_USR_PD_LSB _u(4) -#define OTP_USR_PD_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : OTP_USR_DCTRL -// Description : 1 enables USER interface; 0 disables USER interface (enables -// SBPI). -// -// This bit must be cleared before performing any SBPI access, -// such as when programming the OTP. The APB data read interface -// (USER interface) will be inaccessible during this time, and -// will return a bus error if any read is attempted. -#define OTP_USR_DCTRL_RESET _u(0x1) -#define OTP_USR_DCTRL_BITS _u(0x00000001) -#define OTP_USR_DCTRL_MSB _u(0) -#define OTP_USR_DCTRL_LSB _u(0) -#define OTP_USR_DCTRL_ACCESS "RW" -// ============================================================================= -// Register : OTP_DBG -// Description : Debug for OTP power-on state machine -#define OTP_DBG_OFFSET _u(0x0000012c) -#define OTP_DBG_BITS _u(0x000010ff) -#define OTP_DBG_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : OTP_DBG_CUSTOMER_RMA_FLAG -// Description : The chip is in RMA mode -#define OTP_DBG_CUSTOMER_RMA_FLAG_RESET "-" -#define OTP_DBG_CUSTOMER_RMA_FLAG_BITS _u(0x00001000) -#define OTP_DBG_CUSTOMER_RMA_FLAG_MSB _u(12) -#define OTP_DBG_CUSTOMER_RMA_FLAG_LSB _u(12) -#define OTP_DBG_CUSTOMER_RMA_FLAG_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DBG_PSM_STATE -// Description : Monitor the PSM FSM's state -#define OTP_DBG_PSM_STATE_RESET "-" -#define OTP_DBG_PSM_STATE_BITS _u(0x000000f0) -#define OTP_DBG_PSM_STATE_MSB _u(7) -#define OTP_DBG_PSM_STATE_LSB _u(4) -#define OTP_DBG_PSM_STATE_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DBG_ROSC_UP -// Description : Ring oscillator is up and running -#define OTP_DBG_ROSC_UP_RESET "-" -#define OTP_DBG_ROSC_UP_BITS _u(0x00000008) -#define OTP_DBG_ROSC_UP_MSB _u(3) -#define OTP_DBG_ROSC_UP_LSB _u(3) -#define OTP_DBG_ROSC_UP_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DBG_ROSC_UP_SEEN -// Description : Ring oscillator was seen up and running -#define OTP_DBG_ROSC_UP_SEEN_RESET _u(0x0) -#define OTP_DBG_ROSC_UP_SEEN_BITS _u(0x00000004) -#define OTP_DBG_ROSC_UP_SEEN_MSB _u(2) -#define OTP_DBG_ROSC_UP_SEEN_LSB _u(2) -#define OTP_DBG_ROSC_UP_SEEN_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : OTP_DBG_BOOT_DONE -// Description : PSM boot done status flag -#define OTP_DBG_BOOT_DONE_RESET "-" -#define OTP_DBG_BOOT_DONE_BITS _u(0x00000002) -#define OTP_DBG_BOOT_DONE_MSB _u(1) -#define OTP_DBG_BOOT_DONE_LSB _u(1) -#define OTP_DBG_BOOT_DONE_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DBG_PSM_DONE -// Description : PSM done status flag -#define OTP_DBG_PSM_DONE_RESET "-" -#define OTP_DBG_PSM_DONE_BITS _u(0x00000001) -#define OTP_DBG_PSM_DONE_MSB _u(0) -#define OTP_DBG_PSM_DONE_LSB _u(0) -#define OTP_DBG_PSM_DONE_ACCESS "RO" -// ============================================================================= -// Register : OTP_BIST -// Description : During BIST, count address locations that have at least one -// leaky bit -#define OTP_BIST_OFFSET _u(0x00000134) -#define OTP_BIST_BITS _u(0x7fff1fff) -#define OTP_BIST_RESET _u(0x0fff0000) -// ----------------------------------------------------------------------------- -// Field : OTP_BIST_CNT_FAIL -// Description : Flag if the count of address locations with at least one leaky -// bit exceeds cnt_max -#define OTP_BIST_CNT_FAIL_RESET "-" -#define OTP_BIST_CNT_FAIL_BITS _u(0x40000000) -#define OTP_BIST_CNT_FAIL_MSB _u(30) -#define OTP_BIST_CNT_FAIL_LSB _u(30) -#define OTP_BIST_CNT_FAIL_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_BIST_CNT_CLR -// Description : Clear counter before use -#define OTP_BIST_CNT_CLR_RESET _u(0x0) -#define OTP_BIST_CNT_CLR_BITS _u(0x20000000) -#define OTP_BIST_CNT_CLR_MSB _u(29) -#define OTP_BIST_CNT_CLR_LSB _u(29) -#define OTP_BIST_CNT_CLR_ACCESS "SC" -// ----------------------------------------------------------------------------- -// Field : OTP_BIST_CNT_ENA -// Description : Enable the counter before the BIST function is initiated -#define OTP_BIST_CNT_ENA_RESET _u(0x0) -#define OTP_BIST_CNT_ENA_BITS _u(0x10000000) -#define OTP_BIST_CNT_ENA_MSB _u(28) -#define OTP_BIST_CNT_ENA_LSB _u(28) -#define OTP_BIST_CNT_ENA_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : OTP_BIST_CNT_MAX -// Description : The cnt_fail flag will be set if the number of leaky locations -// exceeds this number -#define OTP_BIST_CNT_MAX_RESET _u(0xfff) -#define OTP_BIST_CNT_MAX_BITS _u(0x0fff0000) -#define OTP_BIST_CNT_MAX_MSB _u(27) -#define OTP_BIST_CNT_MAX_LSB _u(16) -#define OTP_BIST_CNT_MAX_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : OTP_BIST_CNT -// Description : Number of locations that have at least one leaky bit. Note: -// This count is true only if the BIST was initiated without the -// fix option. -#define OTP_BIST_CNT_RESET "-" -#define OTP_BIST_CNT_BITS _u(0x00001fff) -#define OTP_BIST_CNT_MSB _u(12) -#define OTP_BIST_CNT_LSB _u(0) -#define OTP_BIST_CNT_ACCESS "RO" -// ============================================================================= -// Register : OTP_CRT_KEY_W0 -// Description : Word 0 (bits 31..0) of the key. Write only, read returns 0x0 -#define OTP_CRT_KEY_W0_OFFSET _u(0x00000138) -#define OTP_CRT_KEY_W0_BITS _u(0xffffffff) -#define OTP_CRT_KEY_W0_RESET _u(0x00000000) -#define OTP_CRT_KEY_W0_MSB _u(31) -#define OTP_CRT_KEY_W0_LSB _u(0) -#define OTP_CRT_KEY_W0_ACCESS "WO" -// ============================================================================= -// Register : OTP_CRT_KEY_W1 -// Description : Word 1 (bits 63..32) of the key. Write only, read returns 0x0 -#define OTP_CRT_KEY_W1_OFFSET _u(0x0000013c) -#define OTP_CRT_KEY_W1_BITS _u(0xffffffff) -#define OTP_CRT_KEY_W1_RESET _u(0x00000000) -#define OTP_CRT_KEY_W1_MSB _u(31) -#define OTP_CRT_KEY_W1_LSB _u(0) -#define OTP_CRT_KEY_W1_ACCESS "WO" -// ============================================================================= -// Register : OTP_CRT_KEY_W2 -// Description : Word 2 (bits 95..64) of the key. Write only, read returns 0x0 -#define OTP_CRT_KEY_W2_OFFSET _u(0x00000140) -#define OTP_CRT_KEY_W2_BITS _u(0xffffffff) -#define OTP_CRT_KEY_W2_RESET _u(0x00000000) -#define OTP_CRT_KEY_W2_MSB _u(31) -#define OTP_CRT_KEY_W2_LSB _u(0) -#define OTP_CRT_KEY_W2_ACCESS "WO" -// ============================================================================= -// Register : OTP_CRT_KEY_W3 -// Description : Word 3 (bits 127..96) of the key. Write only, read returns 0x0 -#define OTP_CRT_KEY_W3_OFFSET _u(0x00000144) -#define OTP_CRT_KEY_W3_BITS _u(0xffffffff) -#define OTP_CRT_KEY_W3_RESET _u(0x00000000) -#define OTP_CRT_KEY_W3_MSB _u(31) -#define OTP_CRT_KEY_W3_LSB _u(0) -#define OTP_CRT_KEY_W3_ACCESS "WO" -// ============================================================================= -// Register : OTP_CRITICAL -// Description : Quickly check values of critical flags read during boot up -#define OTP_CRITICAL_OFFSET _u(0x00000148) -#define OTP_CRITICAL_BITS _u(0x0003007f) -#define OTP_CRITICAL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : OTP_CRITICAL_RISCV_DISABLE -#define OTP_CRITICAL_RISCV_DISABLE_RESET _u(0x0) -#define OTP_CRITICAL_RISCV_DISABLE_BITS _u(0x00020000) -#define OTP_CRITICAL_RISCV_DISABLE_MSB _u(17) -#define OTP_CRITICAL_RISCV_DISABLE_LSB _u(17) -#define OTP_CRITICAL_RISCV_DISABLE_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_CRITICAL_ARM_DISABLE -#define OTP_CRITICAL_ARM_DISABLE_RESET _u(0x0) -#define OTP_CRITICAL_ARM_DISABLE_BITS _u(0x00010000) -#define OTP_CRITICAL_ARM_DISABLE_MSB _u(16) -#define OTP_CRITICAL_ARM_DISABLE_LSB _u(16) -#define OTP_CRITICAL_ARM_DISABLE_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_CRITICAL_GLITCH_DETECTOR_SENS -#define OTP_CRITICAL_GLITCH_DETECTOR_SENS_RESET _u(0x0) -#define OTP_CRITICAL_GLITCH_DETECTOR_SENS_BITS _u(0x00000060) -#define OTP_CRITICAL_GLITCH_DETECTOR_SENS_MSB _u(6) -#define OTP_CRITICAL_GLITCH_DETECTOR_SENS_LSB _u(5) -#define OTP_CRITICAL_GLITCH_DETECTOR_SENS_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_CRITICAL_GLITCH_DETECTOR_ENABLE -#define OTP_CRITICAL_GLITCH_DETECTOR_ENABLE_RESET _u(0x0) -#define OTP_CRITICAL_GLITCH_DETECTOR_ENABLE_BITS _u(0x00000010) -#define OTP_CRITICAL_GLITCH_DETECTOR_ENABLE_MSB _u(4) -#define OTP_CRITICAL_GLITCH_DETECTOR_ENABLE_LSB _u(4) -#define OTP_CRITICAL_GLITCH_DETECTOR_ENABLE_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_CRITICAL_DEFAULT_ARCHSEL -#define OTP_CRITICAL_DEFAULT_ARCHSEL_RESET _u(0x0) -#define OTP_CRITICAL_DEFAULT_ARCHSEL_BITS _u(0x00000008) -#define OTP_CRITICAL_DEFAULT_ARCHSEL_MSB _u(3) -#define OTP_CRITICAL_DEFAULT_ARCHSEL_LSB _u(3) -#define OTP_CRITICAL_DEFAULT_ARCHSEL_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_CRITICAL_DEBUG_DISABLE -#define OTP_CRITICAL_DEBUG_DISABLE_RESET _u(0x0) -#define OTP_CRITICAL_DEBUG_DISABLE_BITS _u(0x00000004) -#define OTP_CRITICAL_DEBUG_DISABLE_MSB _u(2) -#define OTP_CRITICAL_DEBUG_DISABLE_LSB _u(2) -#define OTP_CRITICAL_DEBUG_DISABLE_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_CRITICAL_SECURE_DEBUG_DISABLE -#define OTP_CRITICAL_SECURE_DEBUG_DISABLE_RESET _u(0x0) -#define OTP_CRITICAL_SECURE_DEBUG_DISABLE_BITS _u(0x00000002) -#define OTP_CRITICAL_SECURE_DEBUG_DISABLE_MSB _u(1) -#define OTP_CRITICAL_SECURE_DEBUG_DISABLE_LSB _u(1) -#define OTP_CRITICAL_SECURE_DEBUG_DISABLE_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_CRITICAL_SECURE_BOOT_ENABLE -#define OTP_CRITICAL_SECURE_BOOT_ENABLE_RESET _u(0x0) -#define OTP_CRITICAL_SECURE_BOOT_ENABLE_BITS _u(0x00000001) -#define OTP_CRITICAL_SECURE_BOOT_ENABLE_MSB _u(0) -#define OTP_CRITICAL_SECURE_BOOT_ENABLE_LSB _u(0) -#define OTP_CRITICAL_SECURE_BOOT_ENABLE_ACCESS "RO" -// ============================================================================= -// Register : OTP_KEY_VALID -// Description : Which keys were valid (enrolled) at boot time -#define OTP_KEY_VALID_OFFSET _u(0x0000014c) -#define OTP_KEY_VALID_BITS _u(0x000000ff) -#define OTP_KEY_VALID_RESET _u(0x00000000) -#define OTP_KEY_VALID_MSB _u(7) -#define OTP_KEY_VALID_LSB _u(0) -#define OTP_KEY_VALID_ACCESS "RO" -// ============================================================================= -// Register : OTP_DEBUGEN -// Description : Enable a debug feature that has been disabled. Debug features -// are disabled if one of the relevant critical boot flags is set -// in OTP (DEBUG_DISABLE or SECURE_DEBUG_DISABLE), OR if a debug -// key is marked valid in OTP, and the matching key value has not -// been supplied over SWD. -// -// Specifically: -// -// - The DEBUG_DISABLE flag disables all debug features. This can -// be fully overridden by setting all bits of this register. -// -// - The SECURE_DEBUG_DISABLE flag disables secure processor -// debug. This can be fully overridden by setting the PROC0_SECURE -// and PROC1_SECURE bits of this register. -// -// - If a single debug key has been registered, and no matching -// key value has been supplied over SWD, then all debug features -// are disabled. This can be fully overridden by setting all bits -// of this register. -// -// - If both debug keys have been registered, and the Non-secure -// key's value (key 6) has been supplied over SWD, secure -// processor debug is disabled. This can be fully overridden by -// setting the PROC0_SECURE and PROC1_SECURE bits of this -// register. -// -// - If both debug keys have been registered, and the Secure key's -// value (key 5) has been supplied over SWD, then no debug -// features are disabled by the key mechanism. However, note that -// in this case debug features may still be disabled by the -// critical boot flags. -#define OTP_DEBUGEN_OFFSET _u(0x00000150) -#define OTP_DEBUGEN_BITS _u(0x0000010f) -#define OTP_DEBUGEN_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : OTP_DEBUGEN_MISC -// Description : Enable other debug components. Specifically, the CTI, and the -// APB-AP used to access the RISC-V Debug Module. -// -// These components are disabled by default if either of the debug -// disable critical flags is set, or if at least one debug key has -// been enrolled and the least secure of these enrolled key values -// has not been provided over SWD. -#define OTP_DEBUGEN_MISC_RESET _u(0x0) -#define OTP_DEBUGEN_MISC_BITS _u(0x00000100) -#define OTP_DEBUGEN_MISC_MSB _u(8) -#define OTP_DEBUGEN_MISC_LSB _u(8) -#define OTP_DEBUGEN_MISC_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : OTP_DEBUGEN_PROC1_SECURE -// Description : Permit core 1's Mem-AP to generate Secure accesses, assuming it -// is enabled at all. Also enable secure debug of core 1 (SPIDEN -// and SPNIDEN). -// -// Secure debug of core 1 is disabled by default if the secure -// debug disable critical flag is set, or if at least one debug -// key has been enrolled and the most secure of these enrolled key -// values not yet provided over SWD. -#define OTP_DEBUGEN_PROC1_SECURE_RESET _u(0x0) -#define OTP_DEBUGEN_PROC1_SECURE_BITS _u(0x00000008) -#define OTP_DEBUGEN_PROC1_SECURE_MSB _u(3) -#define OTP_DEBUGEN_PROC1_SECURE_LSB _u(3) -#define OTP_DEBUGEN_PROC1_SECURE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : OTP_DEBUGEN_PROC1 -// Description : Enable core 1's Mem-AP if it is currently disabled. -// -// The Mem-AP is disabled by default if either of the debug -// disable critical flags is set, or if at least one debug key has -// been enrolled and the least secure of these enrolled key values -// has not been provided over SWD. -#define OTP_DEBUGEN_PROC1_RESET _u(0x0) -#define OTP_DEBUGEN_PROC1_BITS _u(0x00000004) -#define OTP_DEBUGEN_PROC1_MSB _u(2) -#define OTP_DEBUGEN_PROC1_LSB _u(2) -#define OTP_DEBUGEN_PROC1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : OTP_DEBUGEN_PROC0_SECURE -// Description : Permit core 0's Mem-AP to generate Secure accesses, assuming it -// is enabled at all. Also enable secure debug of core 0 (SPIDEN -// and SPNIDEN). -// -// Secure debug of core 0 is disabled by default if the secure -// debug disable critical flag is set, or if at least one debug -// key has been enrolled and the most secure of these enrolled key -// values not yet provided over SWD. -// -// Note also that core Mem-APs are unconditionally disabled when a -// core is switched to RISC-V mode (by setting the ARCHSEL bit and -// performing a warm reset of the core). -#define OTP_DEBUGEN_PROC0_SECURE_RESET _u(0x0) -#define OTP_DEBUGEN_PROC0_SECURE_BITS _u(0x00000002) -#define OTP_DEBUGEN_PROC0_SECURE_MSB _u(1) -#define OTP_DEBUGEN_PROC0_SECURE_LSB _u(1) -#define OTP_DEBUGEN_PROC0_SECURE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : OTP_DEBUGEN_PROC0 -// Description : Enable core 0's Mem-AP if it is currently disabled. -// -// The Mem-AP is disabled by default if either of the debug -// disable critical flags is set, or if at least one debug key has -// been enrolled and the least secure of these enrolled key values -// has not been provided over SWD. -// -// Note also that core Mem-APs are unconditionally disabled when a -// core is switched to RISC-V mode (by setting the ARCHSEL bit and -// performing a warm reset of the core). -#define OTP_DEBUGEN_PROC0_RESET _u(0x0) -#define OTP_DEBUGEN_PROC0_BITS _u(0x00000001) -#define OTP_DEBUGEN_PROC0_MSB _u(0) -#define OTP_DEBUGEN_PROC0_LSB _u(0) -#define OTP_DEBUGEN_PROC0_ACCESS "RW" -// ============================================================================= -// Register : OTP_DEBUGEN_LOCK -// Description : Write 1s to lock corresponding bits in DEBUGEN. This register -// is reset by the processor cold reset. -#define OTP_DEBUGEN_LOCK_OFFSET _u(0x00000154) -#define OTP_DEBUGEN_LOCK_BITS _u(0x0000010f) -#define OTP_DEBUGEN_LOCK_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : OTP_DEBUGEN_LOCK_MISC -// Description : Write 1 to lock the MISC bit of DEBUGEN. Can't be cleared once -// set. -#define OTP_DEBUGEN_LOCK_MISC_RESET _u(0x0) -#define OTP_DEBUGEN_LOCK_MISC_BITS _u(0x00000100) -#define OTP_DEBUGEN_LOCK_MISC_MSB _u(8) -#define OTP_DEBUGEN_LOCK_MISC_LSB _u(8) -#define OTP_DEBUGEN_LOCK_MISC_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : OTP_DEBUGEN_LOCK_PROC1_SECURE -// Description : Write 1 to lock the PROC1_SECURE bit of DEBUGEN. Can't be -// cleared once set. -#define OTP_DEBUGEN_LOCK_PROC1_SECURE_RESET _u(0x0) -#define OTP_DEBUGEN_LOCK_PROC1_SECURE_BITS _u(0x00000008) -#define OTP_DEBUGEN_LOCK_PROC1_SECURE_MSB _u(3) -#define OTP_DEBUGEN_LOCK_PROC1_SECURE_LSB _u(3) -#define OTP_DEBUGEN_LOCK_PROC1_SECURE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : OTP_DEBUGEN_LOCK_PROC1 -// Description : Write 1 to lock the PROC1 bit of DEBUGEN. Can't be cleared once -// set. -#define OTP_DEBUGEN_LOCK_PROC1_RESET _u(0x0) -#define OTP_DEBUGEN_LOCK_PROC1_BITS _u(0x00000004) -#define OTP_DEBUGEN_LOCK_PROC1_MSB _u(2) -#define OTP_DEBUGEN_LOCK_PROC1_LSB _u(2) -#define OTP_DEBUGEN_LOCK_PROC1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : OTP_DEBUGEN_LOCK_PROC0_SECURE -// Description : Write 1 to lock the PROC0_SECURE bit of DEBUGEN. Can't be -// cleared once set. -#define OTP_DEBUGEN_LOCK_PROC0_SECURE_RESET _u(0x0) -#define OTP_DEBUGEN_LOCK_PROC0_SECURE_BITS _u(0x00000002) -#define OTP_DEBUGEN_LOCK_PROC0_SECURE_MSB _u(1) -#define OTP_DEBUGEN_LOCK_PROC0_SECURE_LSB _u(1) -#define OTP_DEBUGEN_LOCK_PROC0_SECURE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : OTP_DEBUGEN_LOCK_PROC0 -// Description : Write 1 to lock the PROC0 bit of DEBUGEN. Can't be cleared once -// set. -#define OTP_DEBUGEN_LOCK_PROC0_RESET _u(0x0) -#define OTP_DEBUGEN_LOCK_PROC0_BITS _u(0x00000001) -#define OTP_DEBUGEN_LOCK_PROC0_MSB _u(0) -#define OTP_DEBUGEN_LOCK_PROC0_LSB _u(0) -#define OTP_DEBUGEN_LOCK_PROC0_ACCESS "RW" -// ============================================================================= -// Register : OTP_ARCHSEL -// Description : Architecture select (Arm/RISC-V). The default and allowable -// values of this register are constrained by the critical boot -// flags. -// -// This register is reset by the earliest reset in the switched -// core power domain (before a processor cold reset). -// -// Cores sample their architecture select signal on a warm reset. -// The source of the warm reset could be the system power-up state -// machine, the watchdog timer, Arm SYSRESETREQ or from RISC-V -// hartresetreq. -// -// Note that when an Arm core is deselected, its cold reset domain -// is also held in reset, since in particular the SYSRESETREQ bit -// becomes inaccessible once the core is deselected. Note also the -// RISC-V cores do not have a cold reset domain, since their -// corresponding controls are located in the Debug Module. -#define OTP_ARCHSEL_OFFSET _u(0x00000158) -#define OTP_ARCHSEL_BITS _u(0x00000003) -#define OTP_ARCHSEL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : OTP_ARCHSEL_CORE1 -// Description : Select architecture for core 1. -// 0x0 -> Switch core 1 to Arm (Cortex-M33) -// 0x1 -> Switch core 1 to RISC-V (Hazard3) -#define OTP_ARCHSEL_CORE1_RESET _u(0x0) -#define OTP_ARCHSEL_CORE1_BITS _u(0x00000002) -#define OTP_ARCHSEL_CORE1_MSB _u(1) -#define OTP_ARCHSEL_CORE1_LSB _u(1) -#define OTP_ARCHSEL_CORE1_ACCESS "RW" -#define OTP_ARCHSEL_CORE1_VALUE_ARM _u(0x0) -#define OTP_ARCHSEL_CORE1_VALUE_RISCV _u(0x1) -// ----------------------------------------------------------------------------- -// Field : OTP_ARCHSEL_CORE0 -// Description : Select architecture for core 0. -// 0x0 -> Switch core 0 to Arm (Cortex-M33) -// 0x1 -> Switch core 0 to RISC-V (Hazard3) -#define OTP_ARCHSEL_CORE0_RESET _u(0x0) -#define OTP_ARCHSEL_CORE0_BITS _u(0x00000001) -#define OTP_ARCHSEL_CORE0_MSB _u(0) -#define OTP_ARCHSEL_CORE0_LSB _u(0) -#define OTP_ARCHSEL_CORE0_ACCESS "RW" -#define OTP_ARCHSEL_CORE0_VALUE_ARM _u(0x0) -#define OTP_ARCHSEL_CORE0_VALUE_RISCV _u(0x1) -// ============================================================================= -// Register : OTP_ARCHSEL_STATUS -// Description : Get the current architecture select state of each core. Cores -// sample the current value of the ARCHSEL register when their -// warm reset is released, at which point the corresponding bit in -// this register will also update. -#define OTP_ARCHSEL_STATUS_OFFSET _u(0x0000015c) -#define OTP_ARCHSEL_STATUS_BITS _u(0x00000003) -#define OTP_ARCHSEL_STATUS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : OTP_ARCHSEL_STATUS_CORE1 -// Description : Current architecture for core 0. Updated on processor warm -// reset. -// 0x0 -> Core 1 is currently Arm (Cortex-M33) -// 0x1 -> Core 1 is currently RISC-V (Hazard3) -#define OTP_ARCHSEL_STATUS_CORE1_RESET _u(0x0) -#define OTP_ARCHSEL_STATUS_CORE1_BITS _u(0x00000002) -#define OTP_ARCHSEL_STATUS_CORE1_MSB _u(1) -#define OTP_ARCHSEL_STATUS_CORE1_LSB _u(1) -#define OTP_ARCHSEL_STATUS_CORE1_ACCESS "RO" -#define OTP_ARCHSEL_STATUS_CORE1_VALUE_ARM _u(0x0) -#define OTP_ARCHSEL_STATUS_CORE1_VALUE_RISCV _u(0x1) -// ----------------------------------------------------------------------------- -// Field : OTP_ARCHSEL_STATUS_CORE0 -// Description : Current architecture for core 0. Updated on processor warm -// reset. -// 0x0 -> Core 0 is currently Arm (Cortex-M33) -// 0x1 -> Core 0 is currently RISC-V (Hazard3) -#define OTP_ARCHSEL_STATUS_CORE0_RESET _u(0x0) -#define OTP_ARCHSEL_STATUS_CORE0_BITS _u(0x00000001) -#define OTP_ARCHSEL_STATUS_CORE0_MSB _u(0) -#define OTP_ARCHSEL_STATUS_CORE0_LSB _u(0) -#define OTP_ARCHSEL_STATUS_CORE0_ACCESS "RO" -#define OTP_ARCHSEL_STATUS_CORE0_VALUE_ARM _u(0x0) -#define OTP_ARCHSEL_STATUS_CORE0_VALUE_RISCV _u(0x1) -// ============================================================================= -// Register : OTP_BOOTDIS -// Description : Tell the bootrom to ignore scratch register boot vectors (both -// power manager and watchdog) on the next power up. -// -// If an early boot stage has soft-locked some OTP pages in order -// to protect their contents from later stages, there is a risk -// that Secure code running at a later stage can unlock the pages -// by performing a watchdog reset that resets the OTP. -// -// This register can be used to ensure that the bootloader runs as -// normal on the next power up, preventing Secure code at a later -// stage from accessing OTP in its unlocked state. -// -// Should be used in conjunction with the power manager BOOTDIS -// register. -#define OTP_BOOTDIS_OFFSET _u(0x00000160) -#define OTP_BOOTDIS_BITS _u(0x00000003) -#define OTP_BOOTDIS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : OTP_BOOTDIS_NEXT -// Description : This flag always ORs writes into its current contents. It can -// be set but not cleared by software. -// -// The BOOTDIS_NEXT bit is OR'd into the BOOTDIS_NOW bit when the -// core is powered down. Simultaneously, the BOOTDIS_NEXT bit is -// cleared. Setting this bit means that the boot scratch registers -// will be ignored following the next core power down. -// -// This flag should be set by an early boot stage that has soft- -// locked OTP pages, to prevent later stages from unlocking it via -// watchdog reset. -#define OTP_BOOTDIS_NEXT_RESET _u(0x0) -#define OTP_BOOTDIS_NEXT_BITS _u(0x00000002) -#define OTP_BOOTDIS_NEXT_MSB _u(1) -#define OTP_BOOTDIS_NEXT_LSB _u(1) -#define OTP_BOOTDIS_NEXT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : OTP_BOOTDIS_NOW -// Description : When the core is powered down, the current value of -// BOOTDIS_NEXT is OR'd into BOOTDIS_NOW, and BOOTDIS_NEXT is -// cleared. -// -// The bootrom checks this flag before reading the boot scratch -// registers. If it is set, the bootrom clears it, and ignores the -// BOOT registers. This prevents Secure software from diverting -// the boot path before a bootloader has had the chance to soft -// lock OTP pages containing sensitive data. -#define OTP_BOOTDIS_NOW_RESET _u(0x0) -#define OTP_BOOTDIS_NOW_BITS _u(0x00000001) -#define OTP_BOOTDIS_NOW_MSB _u(0) -#define OTP_BOOTDIS_NOW_LSB _u(0) -#define OTP_BOOTDIS_NOW_ACCESS "WC" -// ============================================================================= -// Register : OTP_INTR -// Description : Raw Interrupts -#define OTP_INTR_OFFSET _u(0x00000164) -#define OTP_INTR_BITS _u(0x0000001f) -#define OTP_INTR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : OTP_INTR_APB_RD_NSEC_FAIL -#define OTP_INTR_APB_RD_NSEC_FAIL_RESET _u(0x0) -#define OTP_INTR_APB_RD_NSEC_FAIL_BITS _u(0x00000010) -#define OTP_INTR_APB_RD_NSEC_FAIL_MSB _u(4) -#define OTP_INTR_APB_RD_NSEC_FAIL_LSB _u(4) -#define OTP_INTR_APB_RD_NSEC_FAIL_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : OTP_INTR_APB_RD_SEC_FAIL -#define OTP_INTR_APB_RD_SEC_FAIL_RESET _u(0x0) -#define OTP_INTR_APB_RD_SEC_FAIL_BITS _u(0x00000008) -#define OTP_INTR_APB_RD_SEC_FAIL_MSB _u(3) -#define OTP_INTR_APB_RD_SEC_FAIL_LSB _u(3) -#define OTP_INTR_APB_RD_SEC_FAIL_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : OTP_INTR_APB_DCTRL_FAIL -#define OTP_INTR_APB_DCTRL_FAIL_RESET _u(0x0) -#define OTP_INTR_APB_DCTRL_FAIL_BITS _u(0x00000004) -#define OTP_INTR_APB_DCTRL_FAIL_MSB _u(2) -#define OTP_INTR_APB_DCTRL_FAIL_LSB _u(2) -#define OTP_INTR_APB_DCTRL_FAIL_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : OTP_INTR_SBPI_WR_FAIL -#define OTP_INTR_SBPI_WR_FAIL_RESET _u(0x0) -#define OTP_INTR_SBPI_WR_FAIL_BITS _u(0x00000002) -#define OTP_INTR_SBPI_WR_FAIL_MSB _u(1) -#define OTP_INTR_SBPI_WR_FAIL_LSB _u(1) -#define OTP_INTR_SBPI_WR_FAIL_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : OTP_INTR_SBPI_FLAG_N -#define OTP_INTR_SBPI_FLAG_N_RESET _u(0x0) -#define OTP_INTR_SBPI_FLAG_N_BITS _u(0x00000001) -#define OTP_INTR_SBPI_FLAG_N_MSB _u(0) -#define OTP_INTR_SBPI_FLAG_N_LSB _u(0) -#define OTP_INTR_SBPI_FLAG_N_ACCESS "RO" -// ============================================================================= -// Register : OTP_INTE -// Description : Interrupt Enable -#define OTP_INTE_OFFSET _u(0x00000168) -#define OTP_INTE_BITS _u(0x0000001f) -#define OTP_INTE_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : OTP_INTE_APB_RD_NSEC_FAIL -#define OTP_INTE_APB_RD_NSEC_FAIL_RESET _u(0x0) -#define OTP_INTE_APB_RD_NSEC_FAIL_BITS _u(0x00000010) -#define OTP_INTE_APB_RD_NSEC_FAIL_MSB _u(4) -#define OTP_INTE_APB_RD_NSEC_FAIL_LSB _u(4) -#define OTP_INTE_APB_RD_NSEC_FAIL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : OTP_INTE_APB_RD_SEC_FAIL -#define OTP_INTE_APB_RD_SEC_FAIL_RESET _u(0x0) -#define OTP_INTE_APB_RD_SEC_FAIL_BITS _u(0x00000008) -#define OTP_INTE_APB_RD_SEC_FAIL_MSB _u(3) -#define OTP_INTE_APB_RD_SEC_FAIL_LSB _u(3) -#define OTP_INTE_APB_RD_SEC_FAIL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : OTP_INTE_APB_DCTRL_FAIL -#define OTP_INTE_APB_DCTRL_FAIL_RESET _u(0x0) -#define OTP_INTE_APB_DCTRL_FAIL_BITS _u(0x00000004) -#define OTP_INTE_APB_DCTRL_FAIL_MSB _u(2) -#define OTP_INTE_APB_DCTRL_FAIL_LSB _u(2) -#define OTP_INTE_APB_DCTRL_FAIL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : OTP_INTE_SBPI_WR_FAIL -#define OTP_INTE_SBPI_WR_FAIL_RESET _u(0x0) -#define OTP_INTE_SBPI_WR_FAIL_BITS _u(0x00000002) -#define OTP_INTE_SBPI_WR_FAIL_MSB _u(1) -#define OTP_INTE_SBPI_WR_FAIL_LSB _u(1) -#define OTP_INTE_SBPI_WR_FAIL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : OTP_INTE_SBPI_FLAG_N -#define OTP_INTE_SBPI_FLAG_N_RESET _u(0x0) -#define OTP_INTE_SBPI_FLAG_N_BITS _u(0x00000001) -#define OTP_INTE_SBPI_FLAG_N_MSB _u(0) -#define OTP_INTE_SBPI_FLAG_N_LSB _u(0) -#define OTP_INTE_SBPI_FLAG_N_ACCESS "RW" -// ============================================================================= -// Register : OTP_INTF -// Description : Interrupt Force -#define OTP_INTF_OFFSET _u(0x0000016c) -#define OTP_INTF_BITS _u(0x0000001f) -#define OTP_INTF_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : OTP_INTF_APB_RD_NSEC_FAIL -#define OTP_INTF_APB_RD_NSEC_FAIL_RESET _u(0x0) -#define OTP_INTF_APB_RD_NSEC_FAIL_BITS _u(0x00000010) -#define OTP_INTF_APB_RD_NSEC_FAIL_MSB _u(4) -#define OTP_INTF_APB_RD_NSEC_FAIL_LSB _u(4) -#define OTP_INTF_APB_RD_NSEC_FAIL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : OTP_INTF_APB_RD_SEC_FAIL -#define OTP_INTF_APB_RD_SEC_FAIL_RESET _u(0x0) -#define OTP_INTF_APB_RD_SEC_FAIL_BITS _u(0x00000008) -#define OTP_INTF_APB_RD_SEC_FAIL_MSB _u(3) -#define OTP_INTF_APB_RD_SEC_FAIL_LSB _u(3) -#define OTP_INTF_APB_RD_SEC_FAIL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : OTP_INTF_APB_DCTRL_FAIL -#define OTP_INTF_APB_DCTRL_FAIL_RESET _u(0x0) -#define OTP_INTF_APB_DCTRL_FAIL_BITS _u(0x00000004) -#define OTP_INTF_APB_DCTRL_FAIL_MSB _u(2) -#define OTP_INTF_APB_DCTRL_FAIL_LSB _u(2) -#define OTP_INTF_APB_DCTRL_FAIL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : OTP_INTF_SBPI_WR_FAIL -#define OTP_INTF_SBPI_WR_FAIL_RESET _u(0x0) -#define OTP_INTF_SBPI_WR_FAIL_BITS _u(0x00000002) -#define OTP_INTF_SBPI_WR_FAIL_MSB _u(1) -#define OTP_INTF_SBPI_WR_FAIL_LSB _u(1) -#define OTP_INTF_SBPI_WR_FAIL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : OTP_INTF_SBPI_FLAG_N -#define OTP_INTF_SBPI_FLAG_N_RESET _u(0x0) -#define OTP_INTF_SBPI_FLAG_N_BITS _u(0x00000001) -#define OTP_INTF_SBPI_FLAG_N_MSB _u(0) -#define OTP_INTF_SBPI_FLAG_N_LSB _u(0) -#define OTP_INTF_SBPI_FLAG_N_ACCESS "RW" -// ============================================================================= -// Register : OTP_INTS -// Description : Interrupt status after masking & forcing -#define OTP_INTS_OFFSET _u(0x00000170) -#define OTP_INTS_BITS _u(0x0000001f) -#define OTP_INTS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : OTP_INTS_APB_RD_NSEC_FAIL -#define OTP_INTS_APB_RD_NSEC_FAIL_RESET _u(0x0) -#define OTP_INTS_APB_RD_NSEC_FAIL_BITS _u(0x00000010) -#define OTP_INTS_APB_RD_NSEC_FAIL_MSB _u(4) -#define OTP_INTS_APB_RD_NSEC_FAIL_LSB _u(4) -#define OTP_INTS_APB_RD_NSEC_FAIL_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_INTS_APB_RD_SEC_FAIL -#define OTP_INTS_APB_RD_SEC_FAIL_RESET _u(0x0) -#define OTP_INTS_APB_RD_SEC_FAIL_BITS _u(0x00000008) -#define OTP_INTS_APB_RD_SEC_FAIL_MSB _u(3) -#define OTP_INTS_APB_RD_SEC_FAIL_LSB _u(3) -#define OTP_INTS_APB_RD_SEC_FAIL_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_INTS_APB_DCTRL_FAIL -#define OTP_INTS_APB_DCTRL_FAIL_RESET _u(0x0) -#define OTP_INTS_APB_DCTRL_FAIL_BITS _u(0x00000004) -#define OTP_INTS_APB_DCTRL_FAIL_MSB _u(2) -#define OTP_INTS_APB_DCTRL_FAIL_LSB _u(2) -#define OTP_INTS_APB_DCTRL_FAIL_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_INTS_SBPI_WR_FAIL -#define OTP_INTS_SBPI_WR_FAIL_RESET _u(0x0) -#define OTP_INTS_SBPI_WR_FAIL_BITS _u(0x00000002) -#define OTP_INTS_SBPI_WR_FAIL_MSB _u(1) -#define OTP_INTS_SBPI_WR_FAIL_LSB _u(1) -#define OTP_INTS_SBPI_WR_FAIL_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_INTS_SBPI_FLAG_N -#define OTP_INTS_SBPI_FLAG_N_RESET _u(0x0) -#define OTP_INTS_SBPI_FLAG_N_BITS _u(0x00000001) -#define OTP_INTS_SBPI_FLAG_N_MSB _u(0) -#define OTP_INTS_SBPI_FLAG_N_LSB _u(0) -#define OTP_INTS_SBPI_FLAG_N_ACCESS "RO" -// ============================================================================= -#endif // _HARDWARE_REGS_OTP_H - diff --git a/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/otp_data.h b/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/otp_data.h deleted file mode 100644 index 57d1d47d8f..0000000000 --- a/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/otp_data.h +++ /dev/null @@ -1,12373 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -// ============================================================================= -// Register block : OTP_DATA -// Version : 1 -// Bus type : apb -// Description : Predefined OTP data layout for RP2350 -// ============================================================================= -#ifndef _HARDWARE_REGS_OTP_DATA_H -#define _HARDWARE_REGS_OTP_DATA_H -// ============================================================================= -// Register : OTP_DATA_CHIPID0 -// Description : Bits 15:0 of public device ID. (ECC) -// -// The CHIPID0..3 rows contain a 64-bit random identifier for this -// chip, which can be read from the USB bootloader PICOBOOT -// interface or from the get_sys_info ROM API. -// -// The number of random bits makes the occurrence of twins -// exceedingly unlikely: for example, a fleet of a hundred million -// devices has a 99.97% probability of no twinned IDs. This is -// estimated to be lower than the occurrence of process errors in -// the assignment of sequential random IDs, and for practical -// purposes CHIPID may be treated as unique. -#define OTP_DATA_CHIPID0_ROW _u(0x00000000) -#define OTP_DATA_CHIPID0_BITS _u(0x0000ffff) -#define OTP_DATA_CHIPID0_RESET "-" -#define OTP_DATA_CHIPID0_WIDTH _u(16) -#define OTP_DATA_CHIPID0_MSB _u(15) -#define OTP_DATA_CHIPID0_LSB _u(0) -#define OTP_DATA_CHIPID0_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_CHIPID1 -// Description : Bits 31:16 of public device ID (ECC) -#define OTP_DATA_CHIPID1_ROW _u(0x00000001) -#define OTP_DATA_CHIPID1_BITS _u(0x0000ffff) -#define OTP_DATA_CHIPID1_RESET "-" -#define OTP_DATA_CHIPID1_WIDTH _u(16) -#define OTP_DATA_CHIPID1_MSB _u(15) -#define OTP_DATA_CHIPID1_LSB _u(0) -#define OTP_DATA_CHIPID1_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_CHIPID2 -// Description : Bits 47:32 of public device ID (ECC) -#define OTP_DATA_CHIPID2_ROW _u(0x00000002) -#define OTP_DATA_CHIPID2_BITS _u(0x0000ffff) -#define OTP_DATA_CHIPID2_RESET "-" -#define OTP_DATA_CHIPID2_WIDTH _u(16) -#define OTP_DATA_CHIPID2_MSB _u(15) -#define OTP_DATA_CHIPID2_LSB _u(0) -#define OTP_DATA_CHIPID2_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_CHIPID3 -// Description : Bits 63:48 of public device ID (ECC) -#define OTP_DATA_CHIPID3_ROW _u(0x00000003) -#define OTP_DATA_CHIPID3_BITS _u(0x0000ffff) -#define OTP_DATA_CHIPID3_RESET "-" -#define OTP_DATA_CHIPID3_WIDTH _u(16) -#define OTP_DATA_CHIPID3_MSB _u(15) -#define OTP_DATA_CHIPID3_LSB _u(0) -#define OTP_DATA_CHIPID3_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_RANDID0 -// Description : Bits 15:0 of private per-device random number (ECC) -// -// The RANDID0..7 rows form a 128-bit random number generated -// during device test. -// -// This ID is not exposed through the USB PICOBOOT GET_INFO -// command or the ROM `get_sys_info()` API. However note that the -// USB PICOBOOT OTP access point can read the entirety of page 0, -// so this value is not meaningfully private unless the USB -// PICOBOOT interface is disabled via the -// DISABLE_BOOTSEL_USB_PICOBOOT_IFC flag in BOOT_FLAGS0. -#define OTP_DATA_RANDID0_ROW _u(0x00000004) -#define OTP_DATA_RANDID0_BITS _u(0x0000ffff) -#define OTP_DATA_RANDID0_RESET "-" -#define OTP_DATA_RANDID0_WIDTH _u(16) -#define OTP_DATA_RANDID0_MSB _u(15) -#define OTP_DATA_RANDID0_LSB _u(0) -#define OTP_DATA_RANDID0_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_RANDID1 -// Description : Bits 31:16 of private per-device random number (ECC) -#define OTP_DATA_RANDID1_ROW _u(0x00000005) -#define OTP_DATA_RANDID1_BITS _u(0x0000ffff) -#define OTP_DATA_RANDID1_RESET "-" -#define OTP_DATA_RANDID1_WIDTH _u(16) -#define OTP_DATA_RANDID1_MSB _u(15) -#define OTP_DATA_RANDID1_LSB _u(0) -#define OTP_DATA_RANDID1_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_RANDID2 -// Description : Bits 47:32 of private per-device random number (ECC) -#define OTP_DATA_RANDID2_ROW _u(0x00000006) -#define OTP_DATA_RANDID2_BITS _u(0x0000ffff) -#define OTP_DATA_RANDID2_RESET "-" -#define OTP_DATA_RANDID2_WIDTH _u(16) -#define OTP_DATA_RANDID2_MSB _u(15) -#define OTP_DATA_RANDID2_LSB _u(0) -#define OTP_DATA_RANDID2_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_RANDID3 -// Description : Bits 63:48 of private per-device random number (ECC) -#define OTP_DATA_RANDID3_ROW _u(0x00000007) -#define OTP_DATA_RANDID3_BITS _u(0x0000ffff) -#define OTP_DATA_RANDID3_RESET "-" -#define OTP_DATA_RANDID3_WIDTH _u(16) -#define OTP_DATA_RANDID3_MSB _u(15) -#define OTP_DATA_RANDID3_LSB _u(0) -#define OTP_DATA_RANDID3_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_RANDID4 -// Description : Bits 79:64 of private per-device random number (ECC) -#define OTP_DATA_RANDID4_ROW _u(0x00000008) -#define OTP_DATA_RANDID4_BITS _u(0x0000ffff) -#define OTP_DATA_RANDID4_RESET "-" -#define OTP_DATA_RANDID4_WIDTH _u(16) -#define OTP_DATA_RANDID4_MSB _u(15) -#define OTP_DATA_RANDID4_LSB _u(0) -#define OTP_DATA_RANDID4_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_RANDID5 -// Description : Bits 95:80 of private per-device random number (ECC) -#define OTP_DATA_RANDID5_ROW _u(0x00000009) -#define OTP_DATA_RANDID5_BITS _u(0x0000ffff) -#define OTP_DATA_RANDID5_RESET "-" -#define OTP_DATA_RANDID5_WIDTH _u(16) -#define OTP_DATA_RANDID5_MSB _u(15) -#define OTP_DATA_RANDID5_LSB _u(0) -#define OTP_DATA_RANDID5_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_RANDID6 -// Description : Bits 111:96 of private per-device random number (ECC) -#define OTP_DATA_RANDID6_ROW _u(0x0000000a) -#define OTP_DATA_RANDID6_BITS _u(0x0000ffff) -#define OTP_DATA_RANDID6_RESET "-" -#define OTP_DATA_RANDID6_WIDTH _u(16) -#define OTP_DATA_RANDID6_MSB _u(15) -#define OTP_DATA_RANDID6_LSB _u(0) -#define OTP_DATA_RANDID6_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_RANDID7 -// Description : Bits 127:112 of private per-device random number (ECC) -#define OTP_DATA_RANDID7_ROW _u(0x0000000b) -#define OTP_DATA_RANDID7_BITS _u(0x0000ffff) -#define OTP_DATA_RANDID7_RESET "-" -#define OTP_DATA_RANDID7_WIDTH _u(16) -#define OTP_DATA_RANDID7_MSB _u(15) -#define OTP_DATA_RANDID7_LSB _u(0) -#define OTP_DATA_RANDID7_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_ROSC_CALIB -// Description : Ring oscillator frequency in kHz, measured during manufacturing -// (ECC) -// -// This is measured at 1.1 V, at room temperature, with the ROSC -// configuration registers in their reset state. -#define OTP_DATA_ROSC_CALIB_ROW _u(0x00000010) -#define OTP_DATA_ROSC_CALIB_BITS _u(0x0000ffff) -#define OTP_DATA_ROSC_CALIB_RESET "-" -#define OTP_DATA_ROSC_CALIB_WIDTH _u(16) -#define OTP_DATA_ROSC_CALIB_MSB _u(15) -#define OTP_DATA_ROSC_CALIB_LSB _u(0) -#define OTP_DATA_ROSC_CALIB_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_LPOSC_CALIB -// Description : Low-power oscillator frequency in Hz, measured during -// manufacturing (ECC) -// -// This is measured at 1.1V, at room temperature, with the LPOSC -// trim register in its reset state. -#define OTP_DATA_LPOSC_CALIB_ROW _u(0x00000011) -#define OTP_DATA_LPOSC_CALIB_BITS _u(0x0000ffff) -#define OTP_DATA_LPOSC_CALIB_RESET "-" -#define OTP_DATA_LPOSC_CALIB_WIDTH _u(16) -#define OTP_DATA_LPOSC_CALIB_MSB _u(15) -#define OTP_DATA_LPOSC_CALIB_LSB _u(0) -#define OTP_DATA_LPOSC_CALIB_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_NUM_GPIOS -// Description : The number of main user GPIOs (bank 0). Should read 48 in the -// QFN80 package, and 30 in the QFN60 package. (ECC) -#define OTP_DATA_NUM_GPIOS_ROW _u(0x00000018) -#define OTP_DATA_NUM_GPIOS_BITS _u(0x000000ff) -#define OTP_DATA_NUM_GPIOS_RESET "-" -#define OTP_DATA_NUM_GPIOS_WIDTH _u(16) -#define OTP_DATA_NUM_GPIOS_MSB _u(7) -#define OTP_DATA_NUM_GPIOS_LSB _u(0) -#define OTP_DATA_NUM_GPIOS_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_INFO_CRC0 -// Description : Lower 16 bits of CRC32 of OTP addresses 0x00 through 0x6b -// (polynomial 0x4c11db7, input reflected, output reflected, seed -// all-ones, final XOR all-ones) (ECC) -#define OTP_DATA_INFO_CRC0_ROW _u(0x00000036) -#define OTP_DATA_INFO_CRC0_BITS _u(0x0000ffff) -#define OTP_DATA_INFO_CRC0_RESET "-" -#define OTP_DATA_INFO_CRC0_WIDTH _u(16) -#define OTP_DATA_INFO_CRC0_MSB _u(15) -#define OTP_DATA_INFO_CRC0_LSB _u(0) -#define OTP_DATA_INFO_CRC0_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_INFO_CRC1 -// Description : Upper 16 bits of CRC32 of OTP addresses 0x00 through 0x6b (ECC) -#define OTP_DATA_INFO_CRC1_ROW _u(0x00000037) -#define OTP_DATA_INFO_CRC1_BITS _u(0x0000ffff) -#define OTP_DATA_INFO_CRC1_RESET "-" -#define OTP_DATA_INFO_CRC1_WIDTH _u(16) -#define OTP_DATA_INFO_CRC1_MSB _u(15) -#define OTP_DATA_INFO_CRC1_LSB _u(0) -#define OTP_DATA_INFO_CRC1_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_CRIT0 -// Description : Page 0 critical boot flags (RBIT-8) -#define OTP_DATA_CRIT0_ROW _u(0x00000038) -#define OTP_DATA_CRIT0_BITS _u(0x00000003) -#define OTP_DATA_CRIT0_RESET _u(0x00000000) -#define OTP_DATA_CRIT0_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_CRIT0_RISCV_DISABLE -// Description : Permanently disable RISC-V processors (Hazard3) -#define OTP_DATA_CRIT0_RISCV_DISABLE_RESET "-" -#define OTP_DATA_CRIT0_RISCV_DISABLE_BITS _u(0x00000002) -#define OTP_DATA_CRIT0_RISCV_DISABLE_MSB _u(1) -#define OTP_DATA_CRIT0_RISCV_DISABLE_LSB _u(1) -#define OTP_DATA_CRIT0_RISCV_DISABLE_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_CRIT0_ARM_DISABLE -// Description : Permanently disable ARM processors (Cortex-M33) -#define OTP_DATA_CRIT0_ARM_DISABLE_RESET "-" -#define OTP_DATA_CRIT0_ARM_DISABLE_BITS _u(0x00000001) -#define OTP_DATA_CRIT0_ARM_DISABLE_MSB _u(0) -#define OTP_DATA_CRIT0_ARM_DISABLE_LSB _u(0) -#define OTP_DATA_CRIT0_ARM_DISABLE_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_CRIT0_R1 -// Description : Redundant copy of CRIT0 -#define OTP_DATA_CRIT0_R1_ROW _u(0x00000039) -#define OTP_DATA_CRIT0_R1_BITS _u(0x00ffffff) -#define OTP_DATA_CRIT0_R1_RESET "-" -#define OTP_DATA_CRIT0_R1_WIDTH _u(24) -#define OTP_DATA_CRIT0_R1_MSB _u(23) -#define OTP_DATA_CRIT0_R1_LSB _u(0) -#define OTP_DATA_CRIT0_R1_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_CRIT0_R2 -// Description : Redundant copy of CRIT0 -#define OTP_DATA_CRIT0_R2_ROW _u(0x0000003a) -#define OTP_DATA_CRIT0_R2_BITS _u(0x00ffffff) -#define OTP_DATA_CRIT0_R2_RESET "-" -#define OTP_DATA_CRIT0_R2_WIDTH _u(24) -#define OTP_DATA_CRIT0_R2_MSB _u(23) -#define OTP_DATA_CRIT0_R2_LSB _u(0) -#define OTP_DATA_CRIT0_R2_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_CRIT0_R3 -// Description : Redundant copy of CRIT0 -#define OTP_DATA_CRIT0_R3_ROW _u(0x0000003b) -#define OTP_DATA_CRIT0_R3_BITS _u(0x00ffffff) -#define OTP_DATA_CRIT0_R3_RESET "-" -#define OTP_DATA_CRIT0_R3_WIDTH _u(24) -#define OTP_DATA_CRIT0_R3_MSB _u(23) -#define OTP_DATA_CRIT0_R3_LSB _u(0) -#define OTP_DATA_CRIT0_R3_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_CRIT0_R4 -// Description : Redundant copy of CRIT0 -#define OTP_DATA_CRIT0_R4_ROW _u(0x0000003c) -#define OTP_DATA_CRIT0_R4_BITS _u(0x00ffffff) -#define OTP_DATA_CRIT0_R4_RESET "-" -#define OTP_DATA_CRIT0_R4_WIDTH _u(24) -#define OTP_DATA_CRIT0_R4_MSB _u(23) -#define OTP_DATA_CRIT0_R4_LSB _u(0) -#define OTP_DATA_CRIT0_R4_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_CRIT0_R5 -// Description : Redundant copy of CRIT0 -#define OTP_DATA_CRIT0_R5_ROW _u(0x0000003d) -#define OTP_DATA_CRIT0_R5_BITS _u(0x00ffffff) -#define OTP_DATA_CRIT0_R5_RESET "-" -#define OTP_DATA_CRIT0_R5_WIDTH _u(24) -#define OTP_DATA_CRIT0_R5_MSB _u(23) -#define OTP_DATA_CRIT0_R5_LSB _u(0) -#define OTP_DATA_CRIT0_R5_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_CRIT0_R6 -// Description : Redundant copy of CRIT0 -#define OTP_DATA_CRIT0_R6_ROW _u(0x0000003e) -#define OTP_DATA_CRIT0_R6_BITS _u(0x00ffffff) -#define OTP_DATA_CRIT0_R6_RESET "-" -#define OTP_DATA_CRIT0_R6_WIDTH _u(24) -#define OTP_DATA_CRIT0_R6_MSB _u(23) -#define OTP_DATA_CRIT0_R6_LSB _u(0) -#define OTP_DATA_CRIT0_R6_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_CRIT0_R7 -// Description : Redundant copy of CRIT0 -#define OTP_DATA_CRIT0_R7_ROW _u(0x0000003f) -#define OTP_DATA_CRIT0_R7_BITS _u(0x00ffffff) -#define OTP_DATA_CRIT0_R7_RESET "-" -#define OTP_DATA_CRIT0_R7_WIDTH _u(24) -#define OTP_DATA_CRIT0_R7_MSB _u(23) -#define OTP_DATA_CRIT0_R7_LSB _u(0) -#define OTP_DATA_CRIT0_R7_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_CRIT1 -// Description : Page 1 critical boot flags (RBIT-8) -#define OTP_DATA_CRIT1_ROW _u(0x00000040) -#define OTP_DATA_CRIT1_BITS _u(0x0000007f) -#define OTP_DATA_CRIT1_RESET _u(0x00000000) -#define OTP_DATA_CRIT1_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_CRIT1_GLITCH_DETECTOR_SENS -// Description : Increase the sensitivity of the glitch detectors from their -// default. -#define OTP_DATA_CRIT1_GLITCH_DETECTOR_SENS_RESET "-" -#define OTP_DATA_CRIT1_GLITCH_DETECTOR_SENS_BITS _u(0x00000060) -#define OTP_DATA_CRIT1_GLITCH_DETECTOR_SENS_MSB _u(6) -#define OTP_DATA_CRIT1_GLITCH_DETECTOR_SENS_LSB _u(5) -#define OTP_DATA_CRIT1_GLITCH_DETECTOR_SENS_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_CRIT1_GLITCH_DETECTOR_ENABLE -// Description : Arm the glitch detectors to reset the system if an abnormal -// clock/power event is observed. -#define OTP_DATA_CRIT1_GLITCH_DETECTOR_ENABLE_RESET "-" -#define OTP_DATA_CRIT1_GLITCH_DETECTOR_ENABLE_BITS _u(0x00000010) -#define OTP_DATA_CRIT1_GLITCH_DETECTOR_ENABLE_MSB _u(4) -#define OTP_DATA_CRIT1_GLITCH_DETECTOR_ENABLE_LSB _u(4) -#define OTP_DATA_CRIT1_GLITCH_DETECTOR_ENABLE_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_CRIT1_BOOT_ARCH -// Description : Set the default boot architecture, 0=ARM 1=RISC-V. Ignored if -// ARM_DISABLE, RISCV_DISABLE or SECURE_BOOT_ENABLE is set. -#define OTP_DATA_CRIT1_BOOT_ARCH_RESET "-" -#define OTP_DATA_CRIT1_BOOT_ARCH_BITS _u(0x00000008) -#define OTP_DATA_CRIT1_BOOT_ARCH_MSB _u(3) -#define OTP_DATA_CRIT1_BOOT_ARCH_LSB _u(3) -#define OTP_DATA_CRIT1_BOOT_ARCH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_CRIT1_DEBUG_DISABLE -// Description : Disable all debug access -#define OTP_DATA_CRIT1_DEBUG_DISABLE_RESET "-" -#define OTP_DATA_CRIT1_DEBUG_DISABLE_BITS _u(0x00000004) -#define OTP_DATA_CRIT1_DEBUG_DISABLE_MSB _u(2) -#define OTP_DATA_CRIT1_DEBUG_DISABLE_LSB _u(2) -#define OTP_DATA_CRIT1_DEBUG_DISABLE_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_CRIT1_SECURE_DEBUG_DISABLE -// Description : Disable Secure debug access -#define OTP_DATA_CRIT1_SECURE_DEBUG_DISABLE_RESET "-" -#define OTP_DATA_CRIT1_SECURE_DEBUG_DISABLE_BITS _u(0x00000002) -#define OTP_DATA_CRIT1_SECURE_DEBUG_DISABLE_MSB _u(1) -#define OTP_DATA_CRIT1_SECURE_DEBUG_DISABLE_LSB _u(1) -#define OTP_DATA_CRIT1_SECURE_DEBUG_DISABLE_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_CRIT1_SECURE_BOOT_ENABLE -// Description : Enable boot signature enforcement, and permanently disable the -// RISC-V cores. -#define OTP_DATA_CRIT1_SECURE_BOOT_ENABLE_RESET "-" -#define OTP_DATA_CRIT1_SECURE_BOOT_ENABLE_BITS _u(0x00000001) -#define OTP_DATA_CRIT1_SECURE_BOOT_ENABLE_MSB _u(0) -#define OTP_DATA_CRIT1_SECURE_BOOT_ENABLE_LSB _u(0) -#define OTP_DATA_CRIT1_SECURE_BOOT_ENABLE_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_CRIT1_R1 -// Description : Redundant copy of CRIT1 -#define OTP_DATA_CRIT1_R1_ROW _u(0x00000041) -#define OTP_DATA_CRIT1_R1_BITS _u(0x00ffffff) -#define OTP_DATA_CRIT1_R1_RESET "-" -#define OTP_DATA_CRIT1_R1_WIDTH _u(24) -#define OTP_DATA_CRIT1_R1_MSB _u(23) -#define OTP_DATA_CRIT1_R1_LSB _u(0) -#define OTP_DATA_CRIT1_R1_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_CRIT1_R2 -// Description : Redundant copy of CRIT1 -#define OTP_DATA_CRIT1_R2_ROW _u(0x00000042) -#define OTP_DATA_CRIT1_R2_BITS _u(0x00ffffff) -#define OTP_DATA_CRIT1_R2_RESET "-" -#define OTP_DATA_CRIT1_R2_WIDTH _u(24) -#define OTP_DATA_CRIT1_R2_MSB _u(23) -#define OTP_DATA_CRIT1_R2_LSB _u(0) -#define OTP_DATA_CRIT1_R2_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_CRIT1_R3 -// Description : Redundant copy of CRIT1 -#define OTP_DATA_CRIT1_R3_ROW _u(0x00000043) -#define OTP_DATA_CRIT1_R3_BITS _u(0x00ffffff) -#define OTP_DATA_CRIT1_R3_RESET "-" -#define OTP_DATA_CRIT1_R3_WIDTH _u(24) -#define OTP_DATA_CRIT1_R3_MSB _u(23) -#define OTP_DATA_CRIT1_R3_LSB _u(0) -#define OTP_DATA_CRIT1_R3_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_CRIT1_R4 -// Description : Redundant copy of CRIT1 -#define OTP_DATA_CRIT1_R4_ROW _u(0x00000044) -#define OTP_DATA_CRIT1_R4_BITS _u(0x00ffffff) -#define OTP_DATA_CRIT1_R4_RESET "-" -#define OTP_DATA_CRIT1_R4_WIDTH _u(24) -#define OTP_DATA_CRIT1_R4_MSB _u(23) -#define OTP_DATA_CRIT1_R4_LSB _u(0) -#define OTP_DATA_CRIT1_R4_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_CRIT1_R5 -// Description : Redundant copy of CRIT1 -#define OTP_DATA_CRIT1_R5_ROW _u(0x00000045) -#define OTP_DATA_CRIT1_R5_BITS _u(0x00ffffff) -#define OTP_DATA_CRIT1_R5_RESET "-" -#define OTP_DATA_CRIT1_R5_WIDTH _u(24) -#define OTP_DATA_CRIT1_R5_MSB _u(23) -#define OTP_DATA_CRIT1_R5_LSB _u(0) -#define OTP_DATA_CRIT1_R5_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_CRIT1_R6 -// Description : Redundant copy of CRIT1 -#define OTP_DATA_CRIT1_R6_ROW _u(0x00000046) -#define OTP_DATA_CRIT1_R6_BITS _u(0x00ffffff) -#define OTP_DATA_CRIT1_R6_RESET "-" -#define OTP_DATA_CRIT1_R6_WIDTH _u(24) -#define OTP_DATA_CRIT1_R6_MSB _u(23) -#define OTP_DATA_CRIT1_R6_LSB _u(0) -#define OTP_DATA_CRIT1_R6_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_CRIT1_R7 -// Description : Redundant copy of CRIT1 -#define OTP_DATA_CRIT1_R7_ROW _u(0x00000047) -#define OTP_DATA_CRIT1_R7_BITS _u(0x00ffffff) -#define OTP_DATA_CRIT1_R7_RESET "-" -#define OTP_DATA_CRIT1_R7_WIDTH _u(24) -#define OTP_DATA_CRIT1_R7_MSB _u(23) -#define OTP_DATA_CRIT1_R7_LSB _u(0) -#define OTP_DATA_CRIT1_R7_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_BOOT_FLAGS0 -// Description : Disable/Enable boot paths/features in the RP2350 mask ROM. -// Disables always supersede enables. Enables are provided where -// there are other configurations in OTP that must be valid. -// (RBIT-3) -#define OTP_DATA_BOOT_FLAGS0_ROW _u(0x00000048) -#define OTP_DATA_BOOT_FLAGS0_BITS _u(0x003fffff) -#define OTP_DATA_BOOT_FLAGS0_RESET _u(0x00000000) -#define OTP_DATA_BOOT_FLAGS0_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_BOOT_FLAGS0_DISABLE_SRAM_WINDOW_BOOT -#define OTP_DATA_BOOT_FLAGS0_DISABLE_SRAM_WINDOW_BOOT_RESET "-" -#define OTP_DATA_BOOT_FLAGS0_DISABLE_SRAM_WINDOW_BOOT_BITS _u(0x00200000) -#define OTP_DATA_BOOT_FLAGS0_DISABLE_SRAM_WINDOW_BOOT_MSB _u(21) -#define OTP_DATA_BOOT_FLAGS0_DISABLE_SRAM_WINDOW_BOOT_LSB _u(21) -#define OTP_DATA_BOOT_FLAGS0_DISABLE_SRAM_WINDOW_BOOT_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_BOOT_FLAGS0_DISABLE_XIP_ACCESS_ON_SRAM_ENTRY -// Description : Disable all access to XIP after entering an SRAM binary. -// -// Note that this will cause bootrom APIs that access XIP to fail, -// including APIs that interact with the partition table. -#define OTP_DATA_BOOT_FLAGS0_DISABLE_XIP_ACCESS_ON_SRAM_ENTRY_RESET "-" -#define OTP_DATA_BOOT_FLAGS0_DISABLE_XIP_ACCESS_ON_SRAM_ENTRY_BITS _u(0x00100000) -#define OTP_DATA_BOOT_FLAGS0_DISABLE_XIP_ACCESS_ON_SRAM_ENTRY_MSB _u(20) -#define OTP_DATA_BOOT_FLAGS0_DISABLE_XIP_ACCESS_ON_SRAM_ENTRY_LSB _u(20) -#define OTP_DATA_BOOT_FLAGS0_DISABLE_XIP_ACCESS_ON_SRAM_ENTRY_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_BOOT_FLAGS0_DISABLE_BOOTSEL_UART_BOOT -#define OTP_DATA_BOOT_FLAGS0_DISABLE_BOOTSEL_UART_BOOT_RESET "-" -#define OTP_DATA_BOOT_FLAGS0_DISABLE_BOOTSEL_UART_BOOT_BITS _u(0x00080000) -#define OTP_DATA_BOOT_FLAGS0_DISABLE_BOOTSEL_UART_BOOT_MSB _u(19) -#define OTP_DATA_BOOT_FLAGS0_DISABLE_BOOTSEL_UART_BOOT_LSB _u(19) -#define OTP_DATA_BOOT_FLAGS0_DISABLE_BOOTSEL_UART_BOOT_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_BOOT_FLAGS0_DISABLE_BOOTSEL_USB_PICOBOOT_IFC -#define OTP_DATA_BOOT_FLAGS0_DISABLE_BOOTSEL_USB_PICOBOOT_IFC_RESET "-" -#define OTP_DATA_BOOT_FLAGS0_DISABLE_BOOTSEL_USB_PICOBOOT_IFC_BITS _u(0x00040000) -#define OTP_DATA_BOOT_FLAGS0_DISABLE_BOOTSEL_USB_PICOBOOT_IFC_MSB _u(18) -#define OTP_DATA_BOOT_FLAGS0_DISABLE_BOOTSEL_USB_PICOBOOT_IFC_LSB _u(18) -#define OTP_DATA_BOOT_FLAGS0_DISABLE_BOOTSEL_USB_PICOBOOT_IFC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_BOOT_FLAGS0_DISABLE_BOOTSEL_USB_MSD_IFC -#define OTP_DATA_BOOT_FLAGS0_DISABLE_BOOTSEL_USB_MSD_IFC_RESET "-" -#define OTP_DATA_BOOT_FLAGS0_DISABLE_BOOTSEL_USB_MSD_IFC_BITS _u(0x00020000) -#define OTP_DATA_BOOT_FLAGS0_DISABLE_BOOTSEL_USB_MSD_IFC_MSB _u(17) -#define OTP_DATA_BOOT_FLAGS0_DISABLE_BOOTSEL_USB_MSD_IFC_LSB _u(17) -#define OTP_DATA_BOOT_FLAGS0_DISABLE_BOOTSEL_USB_MSD_IFC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_BOOT_FLAGS0_DISABLE_WATCHDOG_SCRATCH -#define OTP_DATA_BOOT_FLAGS0_DISABLE_WATCHDOG_SCRATCH_RESET "-" -#define OTP_DATA_BOOT_FLAGS0_DISABLE_WATCHDOG_SCRATCH_BITS _u(0x00010000) -#define OTP_DATA_BOOT_FLAGS0_DISABLE_WATCHDOG_SCRATCH_MSB _u(16) -#define OTP_DATA_BOOT_FLAGS0_DISABLE_WATCHDOG_SCRATCH_LSB _u(16) -#define OTP_DATA_BOOT_FLAGS0_DISABLE_WATCHDOG_SCRATCH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_BOOT_FLAGS0_DISABLE_POWER_SCRATCH -#define OTP_DATA_BOOT_FLAGS0_DISABLE_POWER_SCRATCH_RESET "-" -#define OTP_DATA_BOOT_FLAGS0_DISABLE_POWER_SCRATCH_BITS _u(0x00008000) -#define OTP_DATA_BOOT_FLAGS0_DISABLE_POWER_SCRATCH_MSB _u(15) -#define OTP_DATA_BOOT_FLAGS0_DISABLE_POWER_SCRATCH_LSB _u(15) -#define OTP_DATA_BOOT_FLAGS0_DISABLE_POWER_SCRATCH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_BOOT_FLAGS0_ENABLE_OTP_BOOT -// Description : Enable OTP boot. A number of OTP rows specified by OTPBOOT_LEN -// will be loaded, starting from OTPBOOT_SRC, into the SRAM -// location specified by OTPBOOT_DST1 and OTPBOOT_DST0. -// -// The loaded program image is stored with ECC, 16 bits per row, -// and must contain a valid IMAGE_DEF. Do not set this bit without -// first programming an image into OTP and configuring -// OTPBOOT_LEN, OTPBOOT_SRC, OTPBOOT_DST0 and OTPBOOT_DST1. -// -// Note that OTPBOOT_LEN and OTPBOOT_SRC must be even numbers of -// OTP rows. Equivalently, the image must be a multiple of 32 bits -// in size, and must start at a 32-bit-aligned address in the ECC -// read data address window. -#define OTP_DATA_BOOT_FLAGS0_ENABLE_OTP_BOOT_RESET "-" -#define OTP_DATA_BOOT_FLAGS0_ENABLE_OTP_BOOT_BITS _u(0x00004000) -#define OTP_DATA_BOOT_FLAGS0_ENABLE_OTP_BOOT_MSB _u(14) -#define OTP_DATA_BOOT_FLAGS0_ENABLE_OTP_BOOT_LSB _u(14) -#define OTP_DATA_BOOT_FLAGS0_ENABLE_OTP_BOOT_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_BOOT_FLAGS0_DISABLE_OTP_BOOT -// Description : Takes precedence over ENABLE_OTP_BOOT. -#define OTP_DATA_BOOT_FLAGS0_DISABLE_OTP_BOOT_RESET "-" -#define OTP_DATA_BOOT_FLAGS0_DISABLE_OTP_BOOT_BITS _u(0x00002000) -#define OTP_DATA_BOOT_FLAGS0_DISABLE_OTP_BOOT_MSB _u(13) -#define OTP_DATA_BOOT_FLAGS0_DISABLE_OTP_BOOT_LSB _u(13) -#define OTP_DATA_BOOT_FLAGS0_DISABLE_OTP_BOOT_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_BOOT_FLAGS0_DISABLE_FLASH_BOOT -#define OTP_DATA_BOOT_FLAGS0_DISABLE_FLASH_BOOT_RESET "-" -#define OTP_DATA_BOOT_FLAGS0_DISABLE_FLASH_BOOT_BITS _u(0x00001000) -#define OTP_DATA_BOOT_FLAGS0_DISABLE_FLASH_BOOT_MSB _u(12) -#define OTP_DATA_BOOT_FLAGS0_DISABLE_FLASH_BOOT_LSB _u(12) -#define OTP_DATA_BOOT_FLAGS0_DISABLE_FLASH_BOOT_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_BOOT_FLAGS0_ROLLBACK_REQUIRED -// Description : Require binaries to have a rollback version. Set automatically -// the first time a binary with a rollback version is booted. -#define OTP_DATA_BOOT_FLAGS0_ROLLBACK_REQUIRED_RESET "-" -#define OTP_DATA_BOOT_FLAGS0_ROLLBACK_REQUIRED_BITS _u(0x00000800) -#define OTP_DATA_BOOT_FLAGS0_ROLLBACK_REQUIRED_MSB _u(11) -#define OTP_DATA_BOOT_FLAGS0_ROLLBACK_REQUIRED_LSB _u(11) -#define OTP_DATA_BOOT_FLAGS0_ROLLBACK_REQUIRED_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_BOOT_FLAGS0_HASHED_PARTITION_TABLE -// Description : Require a partition table to be hashed (if not signed) -#define OTP_DATA_BOOT_FLAGS0_HASHED_PARTITION_TABLE_RESET "-" -#define OTP_DATA_BOOT_FLAGS0_HASHED_PARTITION_TABLE_BITS _u(0x00000400) -#define OTP_DATA_BOOT_FLAGS0_HASHED_PARTITION_TABLE_MSB _u(10) -#define OTP_DATA_BOOT_FLAGS0_HASHED_PARTITION_TABLE_LSB _u(10) -#define OTP_DATA_BOOT_FLAGS0_HASHED_PARTITION_TABLE_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_BOOT_FLAGS0_SECURE_PARTITION_TABLE -// Description : Require a partition table to be signed -#define OTP_DATA_BOOT_FLAGS0_SECURE_PARTITION_TABLE_RESET "-" -#define OTP_DATA_BOOT_FLAGS0_SECURE_PARTITION_TABLE_BITS _u(0x00000200) -#define OTP_DATA_BOOT_FLAGS0_SECURE_PARTITION_TABLE_MSB _u(9) -#define OTP_DATA_BOOT_FLAGS0_SECURE_PARTITION_TABLE_LSB _u(9) -#define OTP_DATA_BOOT_FLAGS0_SECURE_PARTITION_TABLE_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_BOOT_FLAGS0_DISABLE_AUTO_SWITCH_ARCH -// Description : Disable auto-switch of CPU architecture on boot when the (only) -// binary to be booted is for the other Arm/RISC-V architecture -// and both architectures are enabled -#define OTP_DATA_BOOT_FLAGS0_DISABLE_AUTO_SWITCH_ARCH_RESET "-" -#define OTP_DATA_BOOT_FLAGS0_DISABLE_AUTO_SWITCH_ARCH_BITS _u(0x00000100) -#define OTP_DATA_BOOT_FLAGS0_DISABLE_AUTO_SWITCH_ARCH_MSB _u(8) -#define OTP_DATA_BOOT_FLAGS0_DISABLE_AUTO_SWITCH_ARCH_LSB _u(8) -#define OTP_DATA_BOOT_FLAGS0_DISABLE_AUTO_SWITCH_ARCH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_BOOT_FLAGS0_SINGLE_FLASH_BINARY -// Description : Restrict flash boot path to use of a single binary at the start -// of flash -#define OTP_DATA_BOOT_FLAGS0_SINGLE_FLASH_BINARY_RESET "-" -#define OTP_DATA_BOOT_FLAGS0_SINGLE_FLASH_BINARY_BITS _u(0x00000080) -#define OTP_DATA_BOOT_FLAGS0_SINGLE_FLASH_BINARY_MSB _u(7) -#define OTP_DATA_BOOT_FLAGS0_SINGLE_FLASH_BINARY_LSB _u(7) -#define OTP_DATA_BOOT_FLAGS0_SINGLE_FLASH_BINARY_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_BOOT_FLAGS0_OVERRIDE_FLASH_PARTITION_SLOT_SIZE -// Description : Override the limit for default flash metadata scanning. -// -// The value is specified in FLASH_PARTITION_SLOT_SIZE. Make sure -// FLASH_PARTITION_SLOT_SIZE is valid before setting this bit -#define OTP_DATA_BOOT_FLAGS0_OVERRIDE_FLASH_PARTITION_SLOT_SIZE_RESET "-" -#define OTP_DATA_BOOT_FLAGS0_OVERRIDE_FLASH_PARTITION_SLOT_SIZE_BITS _u(0x00000040) -#define OTP_DATA_BOOT_FLAGS0_OVERRIDE_FLASH_PARTITION_SLOT_SIZE_MSB _u(6) -#define OTP_DATA_BOOT_FLAGS0_OVERRIDE_FLASH_PARTITION_SLOT_SIZE_LSB _u(6) -#define OTP_DATA_BOOT_FLAGS0_OVERRIDE_FLASH_PARTITION_SLOT_SIZE_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_BOOT_FLAGS0_FLASH_DEVINFO_ENABLE -// Description : Mark FLASH_DEVINFO as containing valid, ECC'd data which -// describes external flash devices. -#define OTP_DATA_BOOT_FLAGS0_FLASH_DEVINFO_ENABLE_RESET "-" -#define OTP_DATA_BOOT_FLAGS0_FLASH_DEVINFO_ENABLE_BITS _u(0x00000020) -#define OTP_DATA_BOOT_FLAGS0_FLASH_DEVINFO_ENABLE_MSB _u(5) -#define OTP_DATA_BOOT_FLAGS0_FLASH_DEVINFO_ENABLE_LSB _u(5) -#define OTP_DATA_BOOT_FLAGS0_FLASH_DEVINFO_ENABLE_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_BOOT_FLAGS0_FAST_SIGCHECK_ROSC_DIV -// Description : Enable quartering of ROSC divisor during signature check, to -// reduce secure boot time -#define OTP_DATA_BOOT_FLAGS0_FAST_SIGCHECK_ROSC_DIV_RESET "-" -#define OTP_DATA_BOOT_FLAGS0_FAST_SIGCHECK_ROSC_DIV_BITS _u(0x00000010) -#define OTP_DATA_BOOT_FLAGS0_FAST_SIGCHECK_ROSC_DIV_MSB _u(4) -#define OTP_DATA_BOOT_FLAGS0_FAST_SIGCHECK_ROSC_DIV_LSB _u(4) -#define OTP_DATA_BOOT_FLAGS0_FAST_SIGCHECK_ROSC_DIV_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_BOOT_FLAGS0_FLASH_IO_VOLTAGE_1V8 -// Description : If 1, configure the QSPI pads for 1.8 V operation when -// accessing flash for the first time from the bootrom, using the -// VOLTAGE_SELECT register for the QSPI pads bank. This slightly -// improves the input timing of the pads at low voltages, but does -// not affect their output characteristics. -// -// If 0, leave VOLTAGE_SELECT in its reset state (suitable for -// operation at and above 2.5 V) -#define OTP_DATA_BOOT_FLAGS0_FLASH_IO_VOLTAGE_1V8_RESET "-" -#define OTP_DATA_BOOT_FLAGS0_FLASH_IO_VOLTAGE_1V8_BITS _u(0x00000008) -#define OTP_DATA_BOOT_FLAGS0_FLASH_IO_VOLTAGE_1V8_MSB _u(3) -#define OTP_DATA_BOOT_FLAGS0_FLASH_IO_VOLTAGE_1V8_LSB _u(3) -#define OTP_DATA_BOOT_FLAGS0_FLASH_IO_VOLTAGE_1V8_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_BOOT_FLAGS0_ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG -// Description : Enable loading of the non-default XOSC and PLL configuration -// before entering BOOTSEL mode. -// -// Ensure that BOOTSEL_XOSC_CFG and BOOTSEL_PLL_CFG are correctly -// programmed before setting this bit. -// -// If this bit is set, user software may use the contents of -// BOOTSEL_PLL_CFG to calculated the expected XOSC frequency based -// on the fixed USB boot frequency of 48 MHz. -#define OTP_DATA_BOOT_FLAGS0_ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG_RESET "-" -#define OTP_DATA_BOOT_FLAGS0_ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG_BITS _u(0x00000004) -#define OTP_DATA_BOOT_FLAGS0_ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG_MSB _u(2) -#define OTP_DATA_BOOT_FLAGS0_ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG_LSB _u(2) -#define OTP_DATA_BOOT_FLAGS0_ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_BOOT_FLAGS0_ENABLE_BOOTSEL_LED -// Description : Enable bootloader activity LED. If set, bootsel_led_cfg is -// assumed to be valid -#define OTP_DATA_BOOT_FLAGS0_ENABLE_BOOTSEL_LED_RESET "-" -#define OTP_DATA_BOOT_FLAGS0_ENABLE_BOOTSEL_LED_BITS _u(0x00000002) -#define OTP_DATA_BOOT_FLAGS0_ENABLE_BOOTSEL_LED_MSB _u(1) -#define OTP_DATA_BOOT_FLAGS0_ENABLE_BOOTSEL_LED_LSB _u(1) -#define OTP_DATA_BOOT_FLAGS0_ENABLE_BOOTSEL_LED_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_BOOT_FLAGS0_DISABLE_BOOTSEL_EXEC2 -#define OTP_DATA_BOOT_FLAGS0_DISABLE_BOOTSEL_EXEC2_RESET "-" -#define OTP_DATA_BOOT_FLAGS0_DISABLE_BOOTSEL_EXEC2_BITS _u(0x00000001) -#define OTP_DATA_BOOT_FLAGS0_DISABLE_BOOTSEL_EXEC2_MSB _u(0) -#define OTP_DATA_BOOT_FLAGS0_DISABLE_BOOTSEL_EXEC2_LSB _u(0) -#define OTP_DATA_BOOT_FLAGS0_DISABLE_BOOTSEL_EXEC2_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_BOOT_FLAGS0_R1 -// Description : Redundant copy of BOOT_FLAGS0 -#define OTP_DATA_BOOT_FLAGS0_R1_ROW _u(0x00000049) -#define OTP_DATA_BOOT_FLAGS0_R1_BITS _u(0x00ffffff) -#define OTP_DATA_BOOT_FLAGS0_R1_RESET "-" -#define OTP_DATA_BOOT_FLAGS0_R1_WIDTH _u(24) -#define OTP_DATA_BOOT_FLAGS0_R1_MSB _u(23) -#define OTP_DATA_BOOT_FLAGS0_R1_LSB _u(0) -#define OTP_DATA_BOOT_FLAGS0_R1_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_BOOT_FLAGS0_R2 -// Description : Redundant copy of BOOT_FLAGS0 -#define OTP_DATA_BOOT_FLAGS0_R2_ROW _u(0x0000004a) -#define OTP_DATA_BOOT_FLAGS0_R2_BITS _u(0x00ffffff) -#define OTP_DATA_BOOT_FLAGS0_R2_RESET "-" -#define OTP_DATA_BOOT_FLAGS0_R2_WIDTH _u(24) -#define OTP_DATA_BOOT_FLAGS0_R2_MSB _u(23) -#define OTP_DATA_BOOT_FLAGS0_R2_LSB _u(0) -#define OTP_DATA_BOOT_FLAGS0_R2_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_BOOT_FLAGS1 -// Description : Disable/Enable boot paths/features in the RP2350 mask ROM. -// Disables always supersede enables. Enables are provided where -// there are other configurations in OTP that must be valid. -// (RBIT-3) -#define OTP_DATA_BOOT_FLAGS1_ROW _u(0x0000004b) -#define OTP_DATA_BOOT_FLAGS1_BITS _u(0x000f0f0f) -#define OTP_DATA_BOOT_FLAGS1_RESET _u(0x00000000) -#define OTP_DATA_BOOT_FLAGS1_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_BOOT_FLAGS1_DOUBLE_TAP -// Description : Enable entering BOOTSEL mode via double-tap of the RUN/RSTn -// pin. Adds a significant delay to boot time, as configured by -// DOUBLE_TAP_DELAY. -// -// This functions by waiting at startup (i.e. following a reset) -// to see if a second reset is applied soon afterward. The second -// reset is detected by the bootrom with help of the -// POWMAN_CHIP_RESET_DOUBLE_TAP flag, which is not reset by the -// external reset pin, and the bootrom enters BOOTSEL mode -// (NSBOOT) to await further instruction over USB or UART. -#define OTP_DATA_BOOT_FLAGS1_DOUBLE_TAP_RESET "-" -#define OTP_DATA_BOOT_FLAGS1_DOUBLE_TAP_BITS _u(0x00080000) -#define OTP_DATA_BOOT_FLAGS1_DOUBLE_TAP_MSB _u(19) -#define OTP_DATA_BOOT_FLAGS1_DOUBLE_TAP_LSB _u(19) -#define OTP_DATA_BOOT_FLAGS1_DOUBLE_TAP_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_BOOT_FLAGS1_DOUBLE_TAP_DELAY -// Description : Adjust how long to wait for a second reset when double tap -// BOOTSEL mode is enabled via DOUBLE_TAP. The minimum is 50 -// milliseconds, and each unit of this field adds an additional 50 -// milliseconds. -// -// For example, settings this field to its maximum value of 7 will -// cause the chip to wait for 400 milliseconds at boot to check -// for a second reset which requests entry to BOOTSEL mode. -// -// 200 milliseconds (DOUBLE_TAP_DELAY=3) is a good intermediate -// value. -#define OTP_DATA_BOOT_FLAGS1_DOUBLE_TAP_DELAY_RESET "-" -#define OTP_DATA_BOOT_FLAGS1_DOUBLE_TAP_DELAY_BITS _u(0x00070000) -#define OTP_DATA_BOOT_FLAGS1_DOUBLE_TAP_DELAY_MSB _u(18) -#define OTP_DATA_BOOT_FLAGS1_DOUBLE_TAP_DELAY_LSB _u(16) -#define OTP_DATA_BOOT_FLAGS1_DOUBLE_TAP_DELAY_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_BOOT_FLAGS1_KEY_INVALID -// Description : Mark a boot key as invalid, or prevent it from ever becoming -// valid. The bootrom will ignore any boot key marked as invalid -// during secure boot signature checks. -// -// Each bit in this field corresponds to one of the four 256-bit -// boot key hashes that may be stored in page 2 of the OTP. -// -// When provisioning boot keys, it's recommended to mark any boot -// key slots you don't intend to use as KEY_INVALID, so that -// spurious keys can not be installed at a later time. -#define OTP_DATA_BOOT_FLAGS1_KEY_INVALID_RESET "-" -#define OTP_DATA_BOOT_FLAGS1_KEY_INVALID_BITS _u(0x00000f00) -#define OTP_DATA_BOOT_FLAGS1_KEY_INVALID_MSB _u(11) -#define OTP_DATA_BOOT_FLAGS1_KEY_INVALID_LSB _u(8) -#define OTP_DATA_BOOT_FLAGS1_KEY_INVALID_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_BOOT_FLAGS1_KEY_VALID -// Description : Mark each of the possible boot keys as valid. The bootrom will -// check signatures against all valid boot keys, and ignore -// invalid boot keys. -// -// Each bit in this field corresponds to one of the four 256-bit -// boot key hashes that may be stored in page 2 of the OTP. -// -// A KEY_VALID bit is ignored if the corresponding KEY_INVALID bit -// is set. Boot keys are considered valid only when KEY_VALID is -// set and KEY_INVALID is clear. -// -// Do not mark a boot key as KEY_VALID if it does not contain a -// valid SHA-256 hash of your secp256k1 public key. Verify keys -// after programming, before setting the KEY_VALID bits -- a boot -// key with uncorrectable ECC faults will render your device -// unbootable if secure boot is enabled. -// -// Do not enable secure boot without first installing a valid key. -// This will render your device unbootable. -#define OTP_DATA_BOOT_FLAGS1_KEY_VALID_RESET "-" -#define OTP_DATA_BOOT_FLAGS1_KEY_VALID_BITS _u(0x0000000f) -#define OTP_DATA_BOOT_FLAGS1_KEY_VALID_MSB _u(3) -#define OTP_DATA_BOOT_FLAGS1_KEY_VALID_LSB _u(0) -#define OTP_DATA_BOOT_FLAGS1_KEY_VALID_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_BOOT_FLAGS1_R1 -// Description : Redundant copy of BOOT_FLAGS1 -#define OTP_DATA_BOOT_FLAGS1_R1_ROW _u(0x0000004c) -#define OTP_DATA_BOOT_FLAGS1_R1_BITS _u(0x00ffffff) -#define OTP_DATA_BOOT_FLAGS1_R1_RESET "-" -#define OTP_DATA_BOOT_FLAGS1_R1_WIDTH _u(24) -#define OTP_DATA_BOOT_FLAGS1_R1_MSB _u(23) -#define OTP_DATA_BOOT_FLAGS1_R1_LSB _u(0) -#define OTP_DATA_BOOT_FLAGS1_R1_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_BOOT_FLAGS1_R2 -// Description : Redundant copy of BOOT_FLAGS1 -#define OTP_DATA_BOOT_FLAGS1_R2_ROW _u(0x0000004d) -#define OTP_DATA_BOOT_FLAGS1_R2_BITS _u(0x00ffffff) -#define OTP_DATA_BOOT_FLAGS1_R2_RESET "-" -#define OTP_DATA_BOOT_FLAGS1_R2_WIDTH _u(24) -#define OTP_DATA_BOOT_FLAGS1_R2_MSB _u(23) -#define OTP_DATA_BOOT_FLAGS1_R2_LSB _u(0) -#define OTP_DATA_BOOT_FLAGS1_R2_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_DEFAULT_BOOT_VERSION0 -// Description : Default boot version thermometer counter, bits 23:0 (RBIT-3) -#define OTP_DATA_DEFAULT_BOOT_VERSION0_ROW _u(0x0000004e) -#define OTP_DATA_DEFAULT_BOOT_VERSION0_BITS _u(0x00ffffff) -#define OTP_DATA_DEFAULT_BOOT_VERSION0_RESET "-" -#define OTP_DATA_DEFAULT_BOOT_VERSION0_WIDTH _u(24) -#define OTP_DATA_DEFAULT_BOOT_VERSION0_MSB _u(23) -#define OTP_DATA_DEFAULT_BOOT_VERSION0_LSB _u(0) -#define OTP_DATA_DEFAULT_BOOT_VERSION0_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_DEFAULT_BOOT_VERSION0_R1 -// Description : Redundant copy of DEFAULT_BOOT_VERSION0 -#define OTP_DATA_DEFAULT_BOOT_VERSION0_R1_ROW _u(0x0000004f) -#define OTP_DATA_DEFAULT_BOOT_VERSION0_R1_BITS _u(0x00ffffff) -#define OTP_DATA_DEFAULT_BOOT_VERSION0_R1_RESET "-" -#define OTP_DATA_DEFAULT_BOOT_VERSION0_R1_WIDTH _u(24) -#define OTP_DATA_DEFAULT_BOOT_VERSION0_R1_MSB _u(23) -#define OTP_DATA_DEFAULT_BOOT_VERSION0_R1_LSB _u(0) -#define OTP_DATA_DEFAULT_BOOT_VERSION0_R1_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_DEFAULT_BOOT_VERSION0_R2 -// Description : Redundant copy of DEFAULT_BOOT_VERSION0 -#define OTP_DATA_DEFAULT_BOOT_VERSION0_R2_ROW _u(0x00000050) -#define OTP_DATA_DEFAULT_BOOT_VERSION0_R2_BITS _u(0x00ffffff) -#define OTP_DATA_DEFAULT_BOOT_VERSION0_R2_RESET "-" -#define OTP_DATA_DEFAULT_BOOT_VERSION0_R2_WIDTH _u(24) -#define OTP_DATA_DEFAULT_BOOT_VERSION0_R2_MSB _u(23) -#define OTP_DATA_DEFAULT_BOOT_VERSION0_R2_LSB _u(0) -#define OTP_DATA_DEFAULT_BOOT_VERSION0_R2_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_DEFAULT_BOOT_VERSION1 -// Description : Default boot version thermometer counter, bits 47:24 (RBIT-3) -#define OTP_DATA_DEFAULT_BOOT_VERSION1_ROW _u(0x00000051) -#define OTP_DATA_DEFAULT_BOOT_VERSION1_BITS _u(0x00ffffff) -#define OTP_DATA_DEFAULT_BOOT_VERSION1_RESET "-" -#define OTP_DATA_DEFAULT_BOOT_VERSION1_WIDTH _u(24) -#define OTP_DATA_DEFAULT_BOOT_VERSION1_MSB _u(23) -#define OTP_DATA_DEFAULT_BOOT_VERSION1_LSB _u(0) -#define OTP_DATA_DEFAULT_BOOT_VERSION1_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_DEFAULT_BOOT_VERSION1_R1 -// Description : Redundant copy of DEFAULT_BOOT_VERSION1 -#define OTP_DATA_DEFAULT_BOOT_VERSION1_R1_ROW _u(0x00000052) -#define OTP_DATA_DEFAULT_BOOT_VERSION1_R1_BITS _u(0x00ffffff) -#define OTP_DATA_DEFAULT_BOOT_VERSION1_R1_RESET "-" -#define OTP_DATA_DEFAULT_BOOT_VERSION1_R1_WIDTH _u(24) -#define OTP_DATA_DEFAULT_BOOT_VERSION1_R1_MSB _u(23) -#define OTP_DATA_DEFAULT_BOOT_VERSION1_R1_LSB _u(0) -#define OTP_DATA_DEFAULT_BOOT_VERSION1_R1_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_DEFAULT_BOOT_VERSION1_R2 -// Description : Redundant copy of DEFAULT_BOOT_VERSION1 -#define OTP_DATA_DEFAULT_BOOT_VERSION1_R2_ROW _u(0x00000053) -#define OTP_DATA_DEFAULT_BOOT_VERSION1_R2_BITS _u(0x00ffffff) -#define OTP_DATA_DEFAULT_BOOT_VERSION1_R2_RESET "-" -#define OTP_DATA_DEFAULT_BOOT_VERSION1_R2_WIDTH _u(24) -#define OTP_DATA_DEFAULT_BOOT_VERSION1_R2_MSB _u(23) -#define OTP_DATA_DEFAULT_BOOT_VERSION1_R2_LSB _u(0) -#define OTP_DATA_DEFAULT_BOOT_VERSION1_R2_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_FLASH_DEVINFO -// Description : Stores information about external flash device(s). (ECC) -// -// Assumed to be valid if BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is set. -#define OTP_DATA_FLASH_DEVINFO_ROW _u(0x00000054) -#define OTP_DATA_FLASH_DEVINFO_BITS _u(0x0000ffbf) -#define OTP_DATA_FLASH_DEVINFO_RESET _u(0x00000000) -#define OTP_DATA_FLASH_DEVINFO_WIDTH _u(16) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_FLASH_DEVINFO_CS1_SIZE -// Description : The size of the flash/PSRAM device on chip select 1 -// (addressable at 0x11000000 through 0x11ffffff). -// -// A value of zero is decoded as a size of zero (no device). -// Nonzero values are decoded as 4kiB << CS1_SIZE. For example, -// four megabytes is encoded with a CS1_SIZE value of 10, and 16 -// megabytes is encoded with a CS1_SIZE value of 12. -// -// When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, a default of -// zero is used. -// 0x0 -> NONE -// 0x1 -> 8K -// 0x2 -> 16K -// 0x3 -> 32K -// 0x4 -> 64k -// 0x5 -> 128K -// 0x6 -> 256K -// 0x7 -> 512K -// 0x8 -> 1M -// 0x9 -> 2M -// 0xa -> 4M -// 0xb -> 8M -// 0xc -> 16M -#define OTP_DATA_FLASH_DEVINFO_CS1_SIZE_RESET "-" -#define OTP_DATA_FLASH_DEVINFO_CS1_SIZE_BITS _u(0x0000f000) -#define OTP_DATA_FLASH_DEVINFO_CS1_SIZE_MSB _u(15) -#define OTP_DATA_FLASH_DEVINFO_CS1_SIZE_LSB _u(12) -#define OTP_DATA_FLASH_DEVINFO_CS1_SIZE_ACCESS "RO" -#define OTP_DATA_FLASH_DEVINFO_CS1_SIZE_VALUE_NONE _u(0x0) -#define OTP_DATA_FLASH_DEVINFO_CS1_SIZE_VALUE_8K _u(0x1) -#define OTP_DATA_FLASH_DEVINFO_CS1_SIZE_VALUE_16K _u(0x2) -#define OTP_DATA_FLASH_DEVINFO_CS1_SIZE_VALUE_32K _u(0x3) -#define OTP_DATA_FLASH_DEVINFO_CS1_SIZE_VALUE_64K _u(0x4) -#define OTP_DATA_FLASH_DEVINFO_CS1_SIZE_VALUE_128K _u(0x5) -#define OTP_DATA_FLASH_DEVINFO_CS1_SIZE_VALUE_256K _u(0x6) -#define OTP_DATA_FLASH_DEVINFO_CS1_SIZE_VALUE_512K _u(0x7) -#define OTP_DATA_FLASH_DEVINFO_CS1_SIZE_VALUE_1M _u(0x8) -#define OTP_DATA_FLASH_DEVINFO_CS1_SIZE_VALUE_2M _u(0x9) -#define OTP_DATA_FLASH_DEVINFO_CS1_SIZE_VALUE_4M _u(0xa) -#define OTP_DATA_FLASH_DEVINFO_CS1_SIZE_VALUE_8M _u(0xb) -#define OTP_DATA_FLASH_DEVINFO_CS1_SIZE_VALUE_16M _u(0xc) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_FLASH_DEVINFO_CS0_SIZE -// Description : The size of the flash/PSRAM device on chip select 0 -// (addressable at 0x10000000 through 0x10ffffff). -// -// A value of zero is decoded as a size of zero (no device). -// Nonzero values are decoded as 4kiB << CS0_SIZE. For example, -// four megabytes is encoded with a CS0_SIZE value of 10, and 16 -// megabytes is encoded with a CS0_SIZE value of 12. -// -// When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, a default of -// 12 (16 MiB) is used. -// 0x0 -> NONE -// 0x1 -> 8K -// 0x2 -> 16K -// 0x3 -> 32K -// 0x4 -> 64k -// 0x5 -> 128K -// 0x6 -> 256K -// 0x7 -> 512K -// 0x8 -> 1M -// 0x9 -> 2M -// 0xa -> 4M -// 0xb -> 8M -// 0xc -> 16M -#define OTP_DATA_FLASH_DEVINFO_CS0_SIZE_RESET "-" -#define OTP_DATA_FLASH_DEVINFO_CS0_SIZE_BITS _u(0x00000f00) -#define OTP_DATA_FLASH_DEVINFO_CS0_SIZE_MSB _u(11) -#define OTP_DATA_FLASH_DEVINFO_CS0_SIZE_LSB _u(8) -#define OTP_DATA_FLASH_DEVINFO_CS0_SIZE_ACCESS "RO" -#define OTP_DATA_FLASH_DEVINFO_CS0_SIZE_VALUE_NONE _u(0x0) -#define OTP_DATA_FLASH_DEVINFO_CS0_SIZE_VALUE_8K _u(0x1) -#define OTP_DATA_FLASH_DEVINFO_CS0_SIZE_VALUE_16K _u(0x2) -#define OTP_DATA_FLASH_DEVINFO_CS0_SIZE_VALUE_32K _u(0x3) -#define OTP_DATA_FLASH_DEVINFO_CS0_SIZE_VALUE_64K _u(0x4) -#define OTP_DATA_FLASH_DEVINFO_CS0_SIZE_VALUE_128K _u(0x5) -#define OTP_DATA_FLASH_DEVINFO_CS0_SIZE_VALUE_256K _u(0x6) -#define OTP_DATA_FLASH_DEVINFO_CS0_SIZE_VALUE_512K _u(0x7) -#define OTP_DATA_FLASH_DEVINFO_CS0_SIZE_VALUE_1M _u(0x8) -#define OTP_DATA_FLASH_DEVINFO_CS0_SIZE_VALUE_2M _u(0x9) -#define OTP_DATA_FLASH_DEVINFO_CS0_SIZE_VALUE_4M _u(0xa) -#define OTP_DATA_FLASH_DEVINFO_CS0_SIZE_VALUE_8M _u(0xb) -#define OTP_DATA_FLASH_DEVINFO_CS0_SIZE_VALUE_16M _u(0xc) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_FLASH_DEVINFO_D8H_ERASE_SUPPORTED -// Description : If true, all attached devices are assumed to support (or -// ignore, in the case of PSRAM) a block erase command with a -// command prefix of D8h, an erase size of 64 kiB, and a 24-bit -// address. Almost all 25-series flash devices support this -// command. -// -// If set, the bootrom will use the D8h erase command where it is -// able, to accelerate bulk erase operations. This makes flash -// programming faster. -// -// When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, this field -// defaults to false. -#define OTP_DATA_FLASH_DEVINFO_D8H_ERASE_SUPPORTED_RESET "-" -#define OTP_DATA_FLASH_DEVINFO_D8H_ERASE_SUPPORTED_BITS _u(0x00000080) -#define OTP_DATA_FLASH_DEVINFO_D8H_ERASE_SUPPORTED_MSB _u(7) -#define OTP_DATA_FLASH_DEVINFO_D8H_ERASE_SUPPORTED_LSB _u(7) -#define OTP_DATA_FLASH_DEVINFO_D8H_ERASE_SUPPORTED_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_FLASH_DEVINFO_CS1_GPIO -// Description : Indicate a GPIO number to be used for the secondary flash chip -// select (CS1), which selects the external QSPI device mapped at -// system addresses 0x11000000 through 0x11ffffff. There is no -// such configuration for CS0, as the primary chip select has a -// dedicated pin. -// -// On RP2350 the permissible GPIO numbers are 0, 8, 19 and 47. -// -// Ignored if CS1_size is zero. If CS1_SIZE is nonzero, the -// bootrom will automatically configure this GPIO as a second chip -// select upon entering the flash boot path, or entering any other -// path that may use the QSPI flash interface, such as BOOTSEL -// mode (nsboot). -#define OTP_DATA_FLASH_DEVINFO_CS1_GPIO_RESET "-" -#define OTP_DATA_FLASH_DEVINFO_CS1_GPIO_BITS _u(0x0000003f) -#define OTP_DATA_FLASH_DEVINFO_CS1_GPIO_MSB _u(5) -#define OTP_DATA_FLASH_DEVINFO_CS1_GPIO_LSB _u(0) -#define OTP_DATA_FLASH_DEVINFO_CS1_GPIO_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_FLASH_PARTITION_SLOT_SIZE -// Description : Gap between partition table slot 0 and slot 1 at the start of -// flash (the default size is 4096 bytes) (ECC) Enabled by the -// OVERRIDE_FLASH_PARTITION_SLOT_SIZE bit in BOOT_FLAGS, the size -// is 4096 * (value + 1) -#define OTP_DATA_FLASH_PARTITION_SLOT_SIZE_ROW _u(0x00000055) -#define OTP_DATA_FLASH_PARTITION_SLOT_SIZE_BITS _u(0x0000ffff) -#define OTP_DATA_FLASH_PARTITION_SLOT_SIZE_RESET "-" -#define OTP_DATA_FLASH_PARTITION_SLOT_SIZE_WIDTH _u(16) -#define OTP_DATA_FLASH_PARTITION_SLOT_SIZE_MSB _u(15) -#define OTP_DATA_FLASH_PARTITION_SLOT_SIZE_LSB _u(0) -#define OTP_DATA_FLASH_PARTITION_SLOT_SIZE_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_BOOTSEL_LED_CFG -// Description : Pin configuration for LED status, used by USB bootloader. (ECC) -// Must be valid if BOOT_FLAGS0_ENABLE_BOOTSEL_LED is set. -#define OTP_DATA_BOOTSEL_LED_CFG_ROW _u(0x00000056) -#define OTP_DATA_BOOTSEL_LED_CFG_BITS _u(0x0000013f) -#define OTP_DATA_BOOTSEL_LED_CFG_RESET _u(0x00000000) -#define OTP_DATA_BOOTSEL_LED_CFG_WIDTH _u(16) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_BOOTSEL_LED_CFG_ACTIVELOW -// Description : LED is active-low. (Default: active-high.) -#define OTP_DATA_BOOTSEL_LED_CFG_ACTIVELOW_RESET "-" -#define OTP_DATA_BOOTSEL_LED_CFG_ACTIVELOW_BITS _u(0x00000100) -#define OTP_DATA_BOOTSEL_LED_CFG_ACTIVELOW_MSB _u(8) -#define OTP_DATA_BOOTSEL_LED_CFG_ACTIVELOW_LSB _u(8) -#define OTP_DATA_BOOTSEL_LED_CFG_ACTIVELOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_BOOTSEL_LED_CFG_PIN -// Description : GPIO index to use for bootloader activity LED. -#define OTP_DATA_BOOTSEL_LED_CFG_PIN_RESET "-" -#define OTP_DATA_BOOTSEL_LED_CFG_PIN_BITS _u(0x0000003f) -#define OTP_DATA_BOOTSEL_LED_CFG_PIN_MSB _u(5) -#define OTP_DATA_BOOTSEL_LED_CFG_PIN_LSB _u(0) -#define OTP_DATA_BOOTSEL_LED_CFG_PIN_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_BOOTSEL_PLL_CFG -// Description : Optional PLL configuration for BOOTSEL mode. (ECC) -// -// This should be configured to produce an exact 48 MHz based on -// the crystal oscillator frequency. User mode software may also -// use this value to calculate the expected crystal frequency -// based on an assumed 48 MHz PLL output. -// -// If no configuration is given, the crystal is assumed to be 12 -// MHz. -// -// The PLL frequency can be calculated as: -// -// PLL out = (XOSC frequency / (REFDIV+1)) x FBDIV / (POSTDIV1 x -// POSTDIV2) -// -// Conversely the crystal frequency can be calculated as: -// -// XOSC frequency = 48 MHz x (REFDIV+1) x (POSTDIV1 x POSTDIV2) / -// FBDIV -// -// (Note the +1 on REFDIV is because the value stored in this OTP -// location is the actual divisor value minus one.) -// -// Used if and only if ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG is -// set in BOOT_FLAGS0. That bit should be set only after this row -// and BOOTSEL_XOSC_CFG are both correctly programmed. -#define OTP_DATA_BOOTSEL_PLL_CFG_ROW _u(0x00000057) -#define OTP_DATA_BOOTSEL_PLL_CFG_BITS _u(0x0000ffff) -#define OTP_DATA_BOOTSEL_PLL_CFG_RESET _u(0x00000000) -#define OTP_DATA_BOOTSEL_PLL_CFG_WIDTH _u(16) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_BOOTSEL_PLL_CFG_REFDIV -// Description : PLL reference divisor, minus one. -// -// Programming a value of 0 means a reference divisor of 1. -// Programming a value of 1 means a reference divisor of 2 (for -// exceptionally fast XIN inputs) -#define OTP_DATA_BOOTSEL_PLL_CFG_REFDIV_RESET "-" -#define OTP_DATA_BOOTSEL_PLL_CFG_REFDIV_BITS _u(0x00008000) -#define OTP_DATA_BOOTSEL_PLL_CFG_REFDIV_MSB _u(15) -#define OTP_DATA_BOOTSEL_PLL_CFG_REFDIV_LSB _u(15) -#define OTP_DATA_BOOTSEL_PLL_CFG_REFDIV_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_BOOTSEL_PLL_CFG_POSTDIV2 -// Description : PLL post-divide 2 divisor, in the range 1..7 inclusive. -#define OTP_DATA_BOOTSEL_PLL_CFG_POSTDIV2_RESET "-" -#define OTP_DATA_BOOTSEL_PLL_CFG_POSTDIV2_BITS _u(0x00007000) -#define OTP_DATA_BOOTSEL_PLL_CFG_POSTDIV2_MSB _u(14) -#define OTP_DATA_BOOTSEL_PLL_CFG_POSTDIV2_LSB _u(12) -#define OTP_DATA_BOOTSEL_PLL_CFG_POSTDIV2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_BOOTSEL_PLL_CFG_POSTDIV1 -// Description : PLL post-divide 1 divisor, in the range 1..7 inclusive. -#define OTP_DATA_BOOTSEL_PLL_CFG_POSTDIV1_RESET "-" -#define OTP_DATA_BOOTSEL_PLL_CFG_POSTDIV1_BITS _u(0x00000e00) -#define OTP_DATA_BOOTSEL_PLL_CFG_POSTDIV1_MSB _u(11) -#define OTP_DATA_BOOTSEL_PLL_CFG_POSTDIV1_LSB _u(9) -#define OTP_DATA_BOOTSEL_PLL_CFG_POSTDIV1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_BOOTSEL_PLL_CFG_FBDIV -// Description : PLL feedback divisor, in the range 16..320 inclusive. -#define OTP_DATA_BOOTSEL_PLL_CFG_FBDIV_RESET "-" -#define OTP_DATA_BOOTSEL_PLL_CFG_FBDIV_BITS _u(0x000001ff) -#define OTP_DATA_BOOTSEL_PLL_CFG_FBDIV_MSB _u(8) -#define OTP_DATA_BOOTSEL_PLL_CFG_FBDIV_LSB _u(0) -#define OTP_DATA_BOOTSEL_PLL_CFG_FBDIV_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_BOOTSEL_XOSC_CFG -// Description : Non-default crystal oscillator configuration for the USB -// bootloader. (ECC) -// -// These values may also be used by user code configuring the -// crystal oscillator. -// -// Used if and only if ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG is -// set in BOOT_FLAGS0. That bit should be set only after this row -// and BOOTSEL_PLL_CFG are both correctly programmed. -#define OTP_DATA_BOOTSEL_XOSC_CFG_ROW _u(0x00000058) -#define OTP_DATA_BOOTSEL_XOSC_CFG_BITS _u(0x0000ffff) -#define OTP_DATA_BOOTSEL_XOSC_CFG_RESET _u(0x00000000) -#define OTP_DATA_BOOTSEL_XOSC_CFG_WIDTH _u(16) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_BOOTSEL_XOSC_CFG_RANGE -// Description : Value of the XOSC_CTRL_FREQ_RANGE register. -// 0x0 -> 1_15MHZ -// 0x1 -> 10_30MHZ -// 0x2 -> 25_60MHZ -// 0x3 -> 40_100MHZ -#define OTP_DATA_BOOTSEL_XOSC_CFG_RANGE_RESET "-" -#define OTP_DATA_BOOTSEL_XOSC_CFG_RANGE_BITS _u(0x0000c000) -#define OTP_DATA_BOOTSEL_XOSC_CFG_RANGE_MSB _u(15) -#define OTP_DATA_BOOTSEL_XOSC_CFG_RANGE_LSB _u(14) -#define OTP_DATA_BOOTSEL_XOSC_CFG_RANGE_ACCESS "RO" -#define OTP_DATA_BOOTSEL_XOSC_CFG_RANGE_VALUE_1_15MHZ _u(0x0) -#define OTP_DATA_BOOTSEL_XOSC_CFG_RANGE_VALUE_10_30MHZ _u(0x1) -#define OTP_DATA_BOOTSEL_XOSC_CFG_RANGE_VALUE_25_60MHZ _u(0x2) -#define OTP_DATA_BOOTSEL_XOSC_CFG_RANGE_VALUE_40_100MHZ _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_BOOTSEL_XOSC_CFG_STARTUP -// Description : Value of the XOSC_STARTUP register -#define OTP_DATA_BOOTSEL_XOSC_CFG_STARTUP_RESET "-" -#define OTP_DATA_BOOTSEL_XOSC_CFG_STARTUP_BITS _u(0x00003fff) -#define OTP_DATA_BOOTSEL_XOSC_CFG_STARTUP_MSB _u(13) -#define OTP_DATA_BOOTSEL_XOSC_CFG_STARTUP_LSB _u(0) -#define OTP_DATA_BOOTSEL_XOSC_CFG_STARTUP_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_USB_BOOT_FLAGS -// Description : USB boot specific feature flags (RBIT-3) -#define OTP_DATA_USB_BOOT_FLAGS_ROW _u(0x00000059) -#define OTP_DATA_USB_BOOT_FLAGS_BITS _u(0x00c0ffff) -#define OTP_DATA_USB_BOOT_FLAGS_RESET _u(0x00000000) -#define OTP_DATA_USB_BOOT_FLAGS_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_USB_BOOT_FLAGS_DP_DM_SWAP -// Description : Swap DM/DP during USB boot, to support board layouts with -// mirrored USB routing (deliberate or accidental). -#define OTP_DATA_USB_BOOT_FLAGS_DP_DM_SWAP_RESET "-" -#define OTP_DATA_USB_BOOT_FLAGS_DP_DM_SWAP_BITS _u(0x00800000) -#define OTP_DATA_USB_BOOT_FLAGS_DP_DM_SWAP_MSB _u(23) -#define OTP_DATA_USB_BOOT_FLAGS_DP_DM_SWAP_LSB _u(23) -#define OTP_DATA_USB_BOOT_FLAGS_DP_DM_SWAP_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_USB_BOOT_FLAGS_WHITE_LABEL_ADDR_VALID -// Description : valid flag for INFO_UF2_TXT_BOARD_ID_STRDEF entry of the -// USB_WHITE_LABEL struct (index 15) -#define OTP_DATA_USB_BOOT_FLAGS_WHITE_LABEL_ADDR_VALID_RESET "-" -#define OTP_DATA_USB_BOOT_FLAGS_WHITE_LABEL_ADDR_VALID_BITS _u(0x00400000) -#define OTP_DATA_USB_BOOT_FLAGS_WHITE_LABEL_ADDR_VALID_MSB _u(22) -#define OTP_DATA_USB_BOOT_FLAGS_WHITE_LABEL_ADDR_VALID_LSB _u(22) -#define OTP_DATA_USB_BOOT_FLAGS_WHITE_LABEL_ADDR_VALID_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_USB_BOOT_FLAGS_WL_INFO_UF2_TXT_BOARD_ID_STRDEF_VALID -// Description : valid flag for the USB_WHITE_LABEL_ADDR field -#define OTP_DATA_USB_BOOT_FLAGS_WL_INFO_UF2_TXT_BOARD_ID_STRDEF_VALID_RESET "-" -#define OTP_DATA_USB_BOOT_FLAGS_WL_INFO_UF2_TXT_BOARD_ID_STRDEF_VALID_BITS _u(0x00008000) -#define OTP_DATA_USB_BOOT_FLAGS_WL_INFO_UF2_TXT_BOARD_ID_STRDEF_VALID_MSB _u(15) -#define OTP_DATA_USB_BOOT_FLAGS_WL_INFO_UF2_TXT_BOARD_ID_STRDEF_VALID_LSB _u(15) -#define OTP_DATA_USB_BOOT_FLAGS_WL_INFO_UF2_TXT_BOARD_ID_STRDEF_VALID_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_USB_BOOT_FLAGS_WL_INFO_UF2_TXT_MODEL_STRDEF_VALID -// Description : valid flag for INFO_UF2_TXT_MODEL_STRDEF entry of the -// USB_WHITE_LABEL struct (index 14) -#define OTP_DATA_USB_BOOT_FLAGS_WL_INFO_UF2_TXT_MODEL_STRDEF_VALID_RESET "-" -#define OTP_DATA_USB_BOOT_FLAGS_WL_INFO_UF2_TXT_MODEL_STRDEF_VALID_BITS _u(0x00004000) -#define OTP_DATA_USB_BOOT_FLAGS_WL_INFO_UF2_TXT_MODEL_STRDEF_VALID_MSB _u(14) -#define OTP_DATA_USB_BOOT_FLAGS_WL_INFO_UF2_TXT_MODEL_STRDEF_VALID_LSB _u(14) -#define OTP_DATA_USB_BOOT_FLAGS_WL_INFO_UF2_TXT_MODEL_STRDEF_VALID_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_USB_BOOT_FLAGS_WL_INDEX_HTM_REDIRECT_NAME_STRDEF_VALID -// Description : valid flag for INDEX_HTM_REDIRECT_NAME_STRDEF entry of the -// USB_WHITE_LABEL struct (index 13) -#define OTP_DATA_USB_BOOT_FLAGS_WL_INDEX_HTM_REDIRECT_NAME_STRDEF_VALID_RESET "-" -#define OTP_DATA_USB_BOOT_FLAGS_WL_INDEX_HTM_REDIRECT_NAME_STRDEF_VALID_BITS _u(0x00002000) -#define OTP_DATA_USB_BOOT_FLAGS_WL_INDEX_HTM_REDIRECT_NAME_STRDEF_VALID_MSB _u(13) -#define OTP_DATA_USB_BOOT_FLAGS_WL_INDEX_HTM_REDIRECT_NAME_STRDEF_VALID_LSB _u(13) -#define OTP_DATA_USB_BOOT_FLAGS_WL_INDEX_HTM_REDIRECT_NAME_STRDEF_VALID_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_USB_BOOT_FLAGS_WL_INDEX_HTM_REDIRECT_URL_STRDEF_VALID -// Description : valid flag for INDEX_HTM_REDIRECT_URL_STRDEF entry of the -// USB_WHITE_LABEL struct (index 12) -#define OTP_DATA_USB_BOOT_FLAGS_WL_INDEX_HTM_REDIRECT_URL_STRDEF_VALID_RESET "-" -#define OTP_DATA_USB_BOOT_FLAGS_WL_INDEX_HTM_REDIRECT_URL_STRDEF_VALID_BITS _u(0x00001000) -#define OTP_DATA_USB_BOOT_FLAGS_WL_INDEX_HTM_REDIRECT_URL_STRDEF_VALID_MSB _u(12) -#define OTP_DATA_USB_BOOT_FLAGS_WL_INDEX_HTM_REDIRECT_URL_STRDEF_VALID_LSB _u(12) -#define OTP_DATA_USB_BOOT_FLAGS_WL_INDEX_HTM_REDIRECT_URL_STRDEF_VALID_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_USB_BOOT_FLAGS_WL_SCSI_INQUIRY_VERSION_STRDEF_VALID -// Description : valid flag for SCSI_INQUIRY_VERSION_STRDEF entry of the -// USB_WHITE_LABEL struct (index 11) -#define OTP_DATA_USB_BOOT_FLAGS_WL_SCSI_INQUIRY_VERSION_STRDEF_VALID_RESET "-" -#define OTP_DATA_USB_BOOT_FLAGS_WL_SCSI_INQUIRY_VERSION_STRDEF_VALID_BITS _u(0x00000800) -#define OTP_DATA_USB_BOOT_FLAGS_WL_SCSI_INQUIRY_VERSION_STRDEF_VALID_MSB _u(11) -#define OTP_DATA_USB_BOOT_FLAGS_WL_SCSI_INQUIRY_VERSION_STRDEF_VALID_LSB _u(11) -#define OTP_DATA_USB_BOOT_FLAGS_WL_SCSI_INQUIRY_VERSION_STRDEF_VALID_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_USB_BOOT_FLAGS_WL_SCSI_INQUIRY_PRODUCT_STRDEF_VALID -// Description : valid flag for SCSI_INQUIRY_PRODUCT_STRDEF entry of the -// USB_WHITE_LABEL struct (index 10) -#define OTP_DATA_USB_BOOT_FLAGS_WL_SCSI_INQUIRY_PRODUCT_STRDEF_VALID_RESET "-" -#define OTP_DATA_USB_BOOT_FLAGS_WL_SCSI_INQUIRY_PRODUCT_STRDEF_VALID_BITS _u(0x00000400) -#define OTP_DATA_USB_BOOT_FLAGS_WL_SCSI_INQUIRY_PRODUCT_STRDEF_VALID_MSB _u(10) -#define OTP_DATA_USB_BOOT_FLAGS_WL_SCSI_INQUIRY_PRODUCT_STRDEF_VALID_LSB _u(10) -#define OTP_DATA_USB_BOOT_FLAGS_WL_SCSI_INQUIRY_PRODUCT_STRDEF_VALID_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_USB_BOOT_FLAGS_WL_SCSI_INQUIRY_VENDOR_STRDEF_VALID -// Description : valid flag for SCSI_INQUIRY_VENDOR_STRDEF entry of the -// USB_WHITE_LABEL struct (index 9) -#define OTP_DATA_USB_BOOT_FLAGS_WL_SCSI_INQUIRY_VENDOR_STRDEF_VALID_RESET "-" -#define OTP_DATA_USB_BOOT_FLAGS_WL_SCSI_INQUIRY_VENDOR_STRDEF_VALID_BITS _u(0x00000200) -#define OTP_DATA_USB_BOOT_FLAGS_WL_SCSI_INQUIRY_VENDOR_STRDEF_VALID_MSB _u(9) -#define OTP_DATA_USB_BOOT_FLAGS_WL_SCSI_INQUIRY_VENDOR_STRDEF_VALID_LSB _u(9) -#define OTP_DATA_USB_BOOT_FLAGS_WL_SCSI_INQUIRY_VENDOR_STRDEF_VALID_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_USB_BOOT_FLAGS_WL_VOLUME_LABEL_STRDEF_VALID -// Description : valid flag for VOLUME_LABEL_STRDEF entry of the USB_WHITE_LABEL -// struct (index 8) -#define OTP_DATA_USB_BOOT_FLAGS_WL_VOLUME_LABEL_STRDEF_VALID_RESET "-" -#define OTP_DATA_USB_BOOT_FLAGS_WL_VOLUME_LABEL_STRDEF_VALID_BITS _u(0x00000100) -#define OTP_DATA_USB_BOOT_FLAGS_WL_VOLUME_LABEL_STRDEF_VALID_MSB _u(8) -#define OTP_DATA_USB_BOOT_FLAGS_WL_VOLUME_LABEL_STRDEF_VALID_LSB _u(8) -#define OTP_DATA_USB_BOOT_FLAGS_WL_VOLUME_LABEL_STRDEF_VALID_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_USB_BOOT_FLAGS_WL_USB_CONFIG_ATTRIBUTES_MAX_POWER_VALUES_VALID -// Description : valid flag for USB_CONFIG_ATTRIBUTES_MAX_POWER_VALUES entry of -// the USB_WHITE_LABEL struct (index 7) -#define OTP_DATA_USB_BOOT_FLAGS_WL_USB_CONFIG_ATTRIBUTES_MAX_POWER_VALUES_VALID_RESET "-" -#define OTP_DATA_USB_BOOT_FLAGS_WL_USB_CONFIG_ATTRIBUTES_MAX_POWER_VALUES_VALID_BITS _u(0x00000080) -#define OTP_DATA_USB_BOOT_FLAGS_WL_USB_CONFIG_ATTRIBUTES_MAX_POWER_VALUES_VALID_MSB _u(7) -#define OTP_DATA_USB_BOOT_FLAGS_WL_USB_CONFIG_ATTRIBUTES_MAX_POWER_VALUES_VALID_LSB _u(7) -#define OTP_DATA_USB_BOOT_FLAGS_WL_USB_CONFIG_ATTRIBUTES_MAX_POWER_VALUES_VALID_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_USB_BOOT_FLAGS_WL_USB_DEVICE_SERIAL_NUMBER_STRDEF_VALID -// Description : valid flag for USB_DEVICE_SERIAL_NUMBER_STRDEF entry of the -// USB_WHITE_LABEL struct (index 6) -#define OTP_DATA_USB_BOOT_FLAGS_WL_USB_DEVICE_SERIAL_NUMBER_STRDEF_VALID_RESET "-" -#define OTP_DATA_USB_BOOT_FLAGS_WL_USB_DEVICE_SERIAL_NUMBER_STRDEF_VALID_BITS _u(0x00000040) -#define OTP_DATA_USB_BOOT_FLAGS_WL_USB_DEVICE_SERIAL_NUMBER_STRDEF_VALID_MSB _u(6) -#define OTP_DATA_USB_BOOT_FLAGS_WL_USB_DEVICE_SERIAL_NUMBER_STRDEF_VALID_LSB _u(6) -#define OTP_DATA_USB_BOOT_FLAGS_WL_USB_DEVICE_SERIAL_NUMBER_STRDEF_VALID_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_USB_BOOT_FLAGS_WL_USB_DEVICE_PRODUCT_STRDEF_VALID -// Description : valid flag for USB_DEVICE_PRODUCT_STRDEF entry of the -// USB_WHITE_LABEL struct (index 5) -#define OTP_DATA_USB_BOOT_FLAGS_WL_USB_DEVICE_PRODUCT_STRDEF_VALID_RESET "-" -#define OTP_DATA_USB_BOOT_FLAGS_WL_USB_DEVICE_PRODUCT_STRDEF_VALID_BITS _u(0x00000020) -#define OTP_DATA_USB_BOOT_FLAGS_WL_USB_DEVICE_PRODUCT_STRDEF_VALID_MSB _u(5) -#define OTP_DATA_USB_BOOT_FLAGS_WL_USB_DEVICE_PRODUCT_STRDEF_VALID_LSB _u(5) -#define OTP_DATA_USB_BOOT_FLAGS_WL_USB_DEVICE_PRODUCT_STRDEF_VALID_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_USB_BOOT_FLAGS_WL_USB_DEVICE_MANUFACTURER_STRDEF_VALID -// Description : valid flag for USB_DEVICE_MANUFACTURER_STRDEF entry of the -// USB_WHITE_LABEL struct (index 4) -#define OTP_DATA_USB_BOOT_FLAGS_WL_USB_DEVICE_MANUFACTURER_STRDEF_VALID_RESET "-" -#define OTP_DATA_USB_BOOT_FLAGS_WL_USB_DEVICE_MANUFACTURER_STRDEF_VALID_BITS _u(0x00000010) -#define OTP_DATA_USB_BOOT_FLAGS_WL_USB_DEVICE_MANUFACTURER_STRDEF_VALID_MSB _u(4) -#define OTP_DATA_USB_BOOT_FLAGS_WL_USB_DEVICE_MANUFACTURER_STRDEF_VALID_LSB _u(4) -#define OTP_DATA_USB_BOOT_FLAGS_WL_USB_DEVICE_MANUFACTURER_STRDEF_VALID_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_USB_BOOT_FLAGS_WL_USB_DEVICE_LANG_ID_VALUE_VALID -// Description : valid flag for USB_DEVICE_LANG_ID_VALUE entry of the -// USB_WHITE_LABEL struct (index 3) -#define OTP_DATA_USB_BOOT_FLAGS_WL_USB_DEVICE_LANG_ID_VALUE_VALID_RESET "-" -#define OTP_DATA_USB_BOOT_FLAGS_WL_USB_DEVICE_LANG_ID_VALUE_VALID_BITS _u(0x00000008) -#define OTP_DATA_USB_BOOT_FLAGS_WL_USB_DEVICE_LANG_ID_VALUE_VALID_MSB _u(3) -#define OTP_DATA_USB_BOOT_FLAGS_WL_USB_DEVICE_LANG_ID_VALUE_VALID_LSB _u(3) -#define OTP_DATA_USB_BOOT_FLAGS_WL_USB_DEVICE_LANG_ID_VALUE_VALID_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_USB_BOOT_FLAGS_WL_USB_DEVICE_SERIAL_NUMBER_VALUE_VALID -// Description : valid flag for USB_DEVICE_BCD_DEVICEVALUE entry of the -// USB_WHITE_LABEL struct (index 2) -#define OTP_DATA_USB_BOOT_FLAGS_WL_USB_DEVICE_SERIAL_NUMBER_VALUE_VALID_RESET "-" -#define OTP_DATA_USB_BOOT_FLAGS_WL_USB_DEVICE_SERIAL_NUMBER_VALUE_VALID_BITS _u(0x00000004) -#define OTP_DATA_USB_BOOT_FLAGS_WL_USB_DEVICE_SERIAL_NUMBER_VALUE_VALID_MSB _u(2) -#define OTP_DATA_USB_BOOT_FLAGS_WL_USB_DEVICE_SERIAL_NUMBER_VALUE_VALID_LSB _u(2) -#define OTP_DATA_USB_BOOT_FLAGS_WL_USB_DEVICE_SERIAL_NUMBER_VALUE_VALID_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_USB_BOOT_FLAGS_WL_USB_DEVICE_PID_VALUE_VALID -// Description : valid flag for USB_DEVICE_PID_VALUE entry of the -// USB_WHITE_LABEL struct (index 1) -#define OTP_DATA_USB_BOOT_FLAGS_WL_USB_DEVICE_PID_VALUE_VALID_RESET "-" -#define OTP_DATA_USB_BOOT_FLAGS_WL_USB_DEVICE_PID_VALUE_VALID_BITS _u(0x00000002) -#define OTP_DATA_USB_BOOT_FLAGS_WL_USB_DEVICE_PID_VALUE_VALID_MSB _u(1) -#define OTP_DATA_USB_BOOT_FLAGS_WL_USB_DEVICE_PID_VALUE_VALID_LSB _u(1) -#define OTP_DATA_USB_BOOT_FLAGS_WL_USB_DEVICE_PID_VALUE_VALID_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_USB_BOOT_FLAGS_WL_USB_DEVICE_VID_VALUE_VALID -// Description : valid flag for USB_DEVICE_VID_VALUE entry of the -// USB_WHITE_LABEL struct (index 0) -#define OTP_DATA_USB_BOOT_FLAGS_WL_USB_DEVICE_VID_VALUE_VALID_RESET "-" -#define OTP_DATA_USB_BOOT_FLAGS_WL_USB_DEVICE_VID_VALUE_VALID_BITS _u(0x00000001) -#define OTP_DATA_USB_BOOT_FLAGS_WL_USB_DEVICE_VID_VALUE_VALID_MSB _u(0) -#define OTP_DATA_USB_BOOT_FLAGS_WL_USB_DEVICE_VID_VALUE_VALID_LSB _u(0) -#define OTP_DATA_USB_BOOT_FLAGS_WL_USB_DEVICE_VID_VALUE_VALID_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_USB_BOOT_FLAGS_R1 -// Description : Redundant copy of USB_BOOT_FLAGS -#define OTP_DATA_USB_BOOT_FLAGS_R1_ROW _u(0x0000005a) -#define OTP_DATA_USB_BOOT_FLAGS_R1_BITS _u(0x00ffffff) -#define OTP_DATA_USB_BOOT_FLAGS_R1_RESET "-" -#define OTP_DATA_USB_BOOT_FLAGS_R1_WIDTH _u(24) -#define OTP_DATA_USB_BOOT_FLAGS_R1_MSB _u(23) -#define OTP_DATA_USB_BOOT_FLAGS_R1_LSB _u(0) -#define OTP_DATA_USB_BOOT_FLAGS_R1_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_USB_BOOT_FLAGS_R2 -// Description : Redundant copy of USB_BOOT_FLAGS -#define OTP_DATA_USB_BOOT_FLAGS_R2_ROW _u(0x0000005b) -#define OTP_DATA_USB_BOOT_FLAGS_R2_BITS _u(0x00ffffff) -#define OTP_DATA_USB_BOOT_FLAGS_R2_RESET "-" -#define OTP_DATA_USB_BOOT_FLAGS_R2_WIDTH _u(24) -#define OTP_DATA_USB_BOOT_FLAGS_R2_MSB _u(23) -#define OTP_DATA_USB_BOOT_FLAGS_R2_LSB _u(0) -#define OTP_DATA_USB_BOOT_FLAGS_R2_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_USB_WHITE_LABEL_ADDR -// Description : Row index of the USB_WHITE_LABEL structure within OTP (ECC) -// -// The table has 16 rows, each of which are also ECC and marked -// valid by the corresponding valid bit in USB_BOOT_FLAGS (ECC). -// -// The entries are either _VALUEs where the 16 bit value is used -// as is, or _STRDEFs which acts as a pointers to a string value. -// -// The value stored in a _STRDEF is two separate bytes: The low -// seven bits of the first (LSB) byte indicates the number of -// characters in the string, and the top bit of the first (LSB) -// byte if set to indicate that each character in the string is -// two bytes (Unicode) versus one byte if unset. The second (MSB) -// byte represents the location of the string data, and is encoded -// as the number of rows from this USB_WHITE_LABEL_ADDR; i.e. the -// row of the start of the string is USB_WHITE_LABEL_ADDR value + -// msb_byte. -// -// In each case, the corresponding valid bit enables replacing the -// default value for the corresponding item provided by the boot -// rom. -// -// Note that Unicode _STRDEFs are only supported for -// USB_DEVICE_PRODUCT_STRDEF, USB_DEVICE_SERIAL_NUMBER_STRDEF and -// USB_DEVICE_MANUFACTURER_STRDEF. Unicode values will be ignored -// if specified for other fields, and non-unicode values for these -// three items will be converted to Unicode characters by setting -// the upper 8 bits to zero. -// -// Note that if the USB_WHITE_LABEL structure or the corresponding -// strings are not readable by BOOTSEL mode based on OTP -// permissions, or if alignment requirements are not met, then the -// corresponding default values are used. -// -// The index values indicate where each field is located (row -// USB_WHITE_LABEL_ADDR value + index): -// 0x0000 -> INDEX_USB_DEVICE_VID_VALUE -// 0x0001 -> INDEX_USB_DEVICE_PID_VALUE -// 0x0002 -> INDEX_USB_DEVICE_BCD_DEVICE_VALUE -// 0x0003 -> INDEX_USB_DEVICE_LANG_ID_VALUE -// 0x0004 -> INDEX_USB_DEVICE_MANUFACTURER_STRDEF -// 0x0005 -> INDEX_USB_DEVICE_PRODUCT_STRDEF -// 0x0006 -> INDEX_USB_DEVICE_SERIAL_NUMBER_STRDEF -// 0x0007 -> INDEX_USB_CONFIG_ATTRIBUTES_MAX_POWER_VALUES -// 0x0008 -> INDEX_VOLUME_LABEL_STRDEF -// 0x0009 -> INDEX_SCSI_INQUIRY_VENDOR_STRDEF -// 0x000a -> INDEX_SCSI_INQUIRY_PRODUCT_STRDEF -// 0x000b -> INDEX_SCSI_INQUIRY_VERSION_STRDEF -// 0x000c -> INDEX_INDEX_HTM_REDIRECT_URL_STRDEF -// 0x000d -> INDEX_INDEX_HTM_REDIRECT_NAME_STRDEF -// 0x000e -> INDEX_INFO_UF2_TXT_MODEL_STRDEF -// 0x000f -> INDEX_INFO_UF2_TXT_BOARD_ID_STRDEF -#define OTP_DATA_USB_WHITE_LABEL_ADDR_ROW _u(0x0000005c) -#define OTP_DATA_USB_WHITE_LABEL_ADDR_BITS _u(0x0000ffff) -#define OTP_DATA_USB_WHITE_LABEL_ADDR_RESET "-" -#define OTP_DATA_USB_WHITE_LABEL_ADDR_WIDTH _u(16) -#define OTP_DATA_USB_WHITE_LABEL_ADDR_MSB _u(15) -#define OTP_DATA_USB_WHITE_LABEL_ADDR_LSB _u(0) -#define OTP_DATA_USB_WHITE_LABEL_ADDR_ACCESS "RO" -#define OTP_DATA_USB_WHITE_LABEL_ADDR_VALUE_INDEX_USB_DEVICE_VID_VALUE _u(0x0000) -#define OTP_DATA_USB_WHITE_LABEL_ADDR_VALUE_INDEX_USB_DEVICE_PID_VALUE _u(0x0001) -#define OTP_DATA_USB_WHITE_LABEL_ADDR_VALUE_INDEX_USB_DEVICE_BCD_DEVICE_VALUE _u(0x0002) -#define OTP_DATA_USB_WHITE_LABEL_ADDR_VALUE_INDEX_USB_DEVICE_LANG_ID_VALUE _u(0x0003) -#define OTP_DATA_USB_WHITE_LABEL_ADDR_VALUE_INDEX_USB_DEVICE_MANUFACTURER_STRDEF _u(0x0004) -#define OTP_DATA_USB_WHITE_LABEL_ADDR_VALUE_INDEX_USB_DEVICE_PRODUCT_STRDEF _u(0x0005) -#define OTP_DATA_USB_WHITE_LABEL_ADDR_VALUE_INDEX_USB_DEVICE_SERIAL_NUMBER_STRDEF _u(0x0006) -#define OTP_DATA_USB_WHITE_LABEL_ADDR_VALUE_INDEX_USB_CONFIG_ATTRIBUTES_MAX_POWER_VALUES _u(0x0007) -#define OTP_DATA_USB_WHITE_LABEL_ADDR_VALUE_INDEX_VOLUME_LABEL_STRDEF _u(0x0008) -#define OTP_DATA_USB_WHITE_LABEL_ADDR_VALUE_INDEX_SCSI_INQUIRY_VENDOR_STRDEF _u(0x0009) -#define OTP_DATA_USB_WHITE_LABEL_ADDR_VALUE_INDEX_SCSI_INQUIRY_PRODUCT_STRDEF _u(0x000a) -#define OTP_DATA_USB_WHITE_LABEL_ADDR_VALUE_INDEX_SCSI_INQUIRY_VERSION_STRDEF _u(0x000b) -#define OTP_DATA_USB_WHITE_LABEL_ADDR_VALUE_INDEX_INDEX_HTM_REDIRECT_URL_STRDEF _u(0x000c) -#define OTP_DATA_USB_WHITE_LABEL_ADDR_VALUE_INDEX_INDEX_HTM_REDIRECT_NAME_STRDEF _u(0x000d) -#define OTP_DATA_USB_WHITE_LABEL_ADDR_VALUE_INDEX_INFO_UF2_TXT_MODEL_STRDEF _u(0x000e) -#define OTP_DATA_USB_WHITE_LABEL_ADDR_VALUE_INDEX_INFO_UF2_TXT_BOARD_ID_STRDEF _u(0x000f) -// ============================================================================= -// Register : OTP_DATA_OTPBOOT_SRC -// Description : OTP start row for the OTP boot image. (ECC) -// -// If OTP boot is enabled, the bootrom will load from this -// location into SRAM and then directly enter the loaded image. -// Note that the image must be signed if SECURE_BOOT_ENABLE is -// set. The image itself is assumed to be ECC-protected. -// -// This must be an even number. Equivalently, the OTP boot image -// must start at a word-aligned location in the ECC read data -// address window. -#define OTP_DATA_OTPBOOT_SRC_ROW _u(0x0000005e) -#define OTP_DATA_OTPBOOT_SRC_BITS _u(0x0000ffff) -#define OTP_DATA_OTPBOOT_SRC_RESET "-" -#define OTP_DATA_OTPBOOT_SRC_WIDTH _u(16) -#define OTP_DATA_OTPBOOT_SRC_MSB _u(15) -#define OTP_DATA_OTPBOOT_SRC_LSB _u(0) -#define OTP_DATA_OTPBOOT_SRC_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_OTPBOOT_LEN -// Description : Length in rows of the OTP boot image. (ECC) -// -// OTPBOOT_LEN must be even. The total image size must be a -// multiple of 4 bytes (32 bits). -#define OTP_DATA_OTPBOOT_LEN_ROW _u(0x0000005f) -#define OTP_DATA_OTPBOOT_LEN_BITS _u(0x0000ffff) -#define OTP_DATA_OTPBOOT_LEN_RESET "-" -#define OTP_DATA_OTPBOOT_LEN_WIDTH _u(16) -#define OTP_DATA_OTPBOOT_LEN_MSB _u(15) -#define OTP_DATA_OTPBOOT_LEN_LSB _u(0) -#define OTP_DATA_OTPBOOT_LEN_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_OTPBOOT_DST0 -// Description : Bits 15:0 of the OTP boot image load destination (and entry -// point). (ECC) -// -// This must be a location in main SRAM (main SRAM is addresses -// 0x20000000 through 0x20082000) and must be word-aligned. -#define OTP_DATA_OTPBOOT_DST0_ROW _u(0x00000060) -#define OTP_DATA_OTPBOOT_DST0_BITS _u(0x0000ffff) -#define OTP_DATA_OTPBOOT_DST0_RESET "-" -#define OTP_DATA_OTPBOOT_DST0_WIDTH _u(16) -#define OTP_DATA_OTPBOOT_DST0_MSB _u(15) -#define OTP_DATA_OTPBOOT_DST0_LSB _u(0) -#define OTP_DATA_OTPBOOT_DST0_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_OTPBOOT_DST1 -// Description : Bits 31:16 of the OTP boot image load destination (and entry -// point). (ECC) -// -// This must be a location in main SRAM (main SRAM is addresses -// 0x20000000 through 0x20082000) and must be word-aligned. -#define OTP_DATA_OTPBOOT_DST1_ROW _u(0x00000061) -#define OTP_DATA_OTPBOOT_DST1_BITS _u(0x0000ffff) -#define OTP_DATA_OTPBOOT_DST1_RESET "-" -#define OTP_DATA_OTPBOOT_DST1_WIDTH _u(16) -#define OTP_DATA_OTPBOOT_DST1_MSB _u(15) -#define OTP_DATA_OTPBOOT_DST1_LSB _u(0) -#define OTP_DATA_OTPBOOT_DST1_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_BOOTKEY0_0 -// Description : Bits 15:0 of SHA-256 hash of boot key 0 (ECC) -#define OTP_DATA_BOOTKEY0_0_ROW _u(0x00000080) -#define OTP_DATA_BOOTKEY0_0_BITS _u(0x0000ffff) -#define OTP_DATA_BOOTKEY0_0_RESET "-" -#define OTP_DATA_BOOTKEY0_0_WIDTH _u(16) -#define OTP_DATA_BOOTKEY0_0_MSB _u(15) -#define OTP_DATA_BOOTKEY0_0_LSB _u(0) -#define OTP_DATA_BOOTKEY0_0_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_BOOTKEY0_1 -// Description : Bits 31:16 of SHA-256 hash of boot key 0 (ECC) -#define OTP_DATA_BOOTKEY0_1_ROW _u(0x00000081) -#define OTP_DATA_BOOTKEY0_1_BITS _u(0x0000ffff) -#define OTP_DATA_BOOTKEY0_1_RESET "-" -#define OTP_DATA_BOOTKEY0_1_WIDTH _u(16) -#define OTP_DATA_BOOTKEY0_1_MSB _u(15) -#define OTP_DATA_BOOTKEY0_1_LSB _u(0) -#define OTP_DATA_BOOTKEY0_1_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_BOOTKEY0_2 -// Description : Bits 47:32 of SHA-256 hash of boot key 0 (ECC) -#define OTP_DATA_BOOTKEY0_2_ROW _u(0x00000082) -#define OTP_DATA_BOOTKEY0_2_BITS _u(0x0000ffff) -#define OTP_DATA_BOOTKEY0_2_RESET "-" -#define OTP_DATA_BOOTKEY0_2_WIDTH _u(16) -#define OTP_DATA_BOOTKEY0_2_MSB _u(15) -#define OTP_DATA_BOOTKEY0_2_LSB _u(0) -#define OTP_DATA_BOOTKEY0_2_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_BOOTKEY0_3 -// Description : Bits 63:48 of SHA-256 hash of boot key 0 (ECC) -#define OTP_DATA_BOOTKEY0_3_ROW _u(0x00000083) -#define OTP_DATA_BOOTKEY0_3_BITS _u(0x0000ffff) -#define OTP_DATA_BOOTKEY0_3_RESET "-" -#define OTP_DATA_BOOTKEY0_3_WIDTH _u(16) -#define OTP_DATA_BOOTKEY0_3_MSB _u(15) -#define OTP_DATA_BOOTKEY0_3_LSB _u(0) -#define OTP_DATA_BOOTKEY0_3_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_BOOTKEY0_4 -// Description : Bits 79:64 of SHA-256 hash of boot key 0 (ECC) -#define OTP_DATA_BOOTKEY0_4_ROW _u(0x00000084) -#define OTP_DATA_BOOTKEY0_4_BITS _u(0x0000ffff) -#define OTP_DATA_BOOTKEY0_4_RESET "-" -#define OTP_DATA_BOOTKEY0_4_WIDTH _u(16) -#define OTP_DATA_BOOTKEY0_4_MSB _u(15) -#define OTP_DATA_BOOTKEY0_4_LSB _u(0) -#define OTP_DATA_BOOTKEY0_4_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_BOOTKEY0_5 -// Description : Bits 95:80 of SHA-256 hash of boot key 0 (ECC) -#define OTP_DATA_BOOTKEY0_5_ROW _u(0x00000085) -#define OTP_DATA_BOOTKEY0_5_BITS _u(0x0000ffff) -#define OTP_DATA_BOOTKEY0_5_RESET "-" -#define OTP_DATA_BOOTKEY0_5_WIDTH _u(16) -#define OTP_DATA_BOOTKEY0_5_MSB _u(15) -#define OTP_DATA_BOOTKEY0_5_LSB _u(0) -#define OTP_DATA_BOOTKEY0_5_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_BOOTKEY0_6 -// Description : Bits 111:96 of SHA-256 hash of boot key 0 (ECC) -#define OTP_DATA_BOOTKEY0_6_ROW _u(0x00000086) -#define OTP_DATA_BOOTKEY0_6_BITS _u(0x0000ffff) -#define OTP_DATA_BOOTKEY0_6_RESET "-" -#define OTP_DATA_BOOTKEY0_6_WIDTH _u(16) -#define OTP_DATA_BOOTKEY0_6_MSB _u(15) -#define OTP_DATA_BOOTKEY0_6_LSB _u(0) -#define OTP_DATA_BOOTKEY0_6_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_BOOTKEY0_7 -// Description : Bits 127:112 of SHA-256 hash of boot key 0 (ECC) -#define OTP_DATA_BOOTKEY0_7_ROW _u(0x00000087) -#define OTP_DATA_BOOTKEY0_7_BITS _u(0x0000ffff) -#define OTP_DATA_BOOTKEY0_7_RESET "-" -#define OTP_DATA_BOOTKEY0_7_WIDTH _u(16) -#define OTP_DATA_BOOTKEY0_7_MSB _u(15) -#define OTP_DATA_BOOTKEY0_7_LSB _u(0) -#define OTP_DATA_BOOTKEY0_7_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_BOOTKEY0_8 -// Description : Bits 143:128 of SHA-256 hash of boot key 0 (ECC) -#define OTP_DATA_BOOTKEY0_8_ROW _u(0x00000088) -#define OTP_DATA_BOOTKEY0_8_BITS _u(0x0000ffff) -#define OTP_DATA_BOOTKEY0_8_RESET "-" -#define OTP_DATA_BOOTKEY0_8_WIDTH _u(16) -#define OTP_DATA_BOOTKEY0_8_MSB _u(15) -#define OTP_DATA_BOOTKEY0_8_LSB _u(0) -#define OTP_DATA_BOOTKEY0_8_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_BOOTKEY0_9 -// Description : Bits 159:144 of SHA-256 hash of boot key 0 (ECC) -#define OTP_DATA_BOOTKEY0_9_ROW _u(0x00000089) -#define OTP_DATA_BOOTKEY0_9_BITS _u(0x0000ffff) -#define OTP_DATA_BOOTKEY0_9_RESET "-" -#define OTP_DATA_BOOTKEY0_9_WIDTH _u(16) -#define OTP_DATA_BOOTKEY0_9_MSB _u(15) -#define OTP_DATA_BOOTKEY0_9_LSB _u(0) -#define OTP_DATA_BOOTKEY0_9_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_BOOTKEY0_10 -// Description : Bits 175:160 of SHA-256 hash of boot key 0 (ECC) -#define OTP_DATA_BOOTKEY0_10_ROW _u(0x0000008a) -#define OTP_DATA_BOOTKEY0_10_BITS _u(0x0000ffff) -#define OTP_DATA_BOOTKEY0_10_RESET "-" -#define OTP_DATA_BOOTKEY0_10_WIDTH _u(16) -#define OTP_DATA_BOOTKEY0_10_MSB _u(15) -#define OTP_DATA_BOOTKEY0_10_LSB _u(0) -#define OTP_DATA_BOOTKEY0_10_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_BOOTKEY0_11 -// Description : Bits 191:176 of SHA-256 hash of boot key 0 (ECC) -#define OTP_DATA_BOOTKEY0_11_ROW _u(0x0000008b) -#define OTP_DATA_BOOTKEY0_11_BITS _u(0x0000ffff) -#define OTP_DATA_BOOTKEY0_11_RESET "-" -#define OTP_DATA_BOOTKEY0_11_WIDTH _u(16) -#define OTP_DATA_BOOTKEY0_11_MSB _u(15) -#define OTP_DATA_BOOTKEY0_11_LSB _u(0) -#define OTP_DATA_BOOTKEY0_11_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_BOOTKEY0_12 -// Description : Bits 207:192 of SHA-256 hash of boot key 0 (ECC) -#define OTP_DATA_BOOTKEY0_12_ROW _u(0x0000008c) -#define OTP_DATA_BOOTKEY0_12_BITS _u(0x0000ffff) -#define OTP_DATA_BOOTKEY0_12_RESET "-" -#define OTP_DATA_BOOTKEY0_12_WIDTH _u(16) -#define OTP_DATA_BOOTKEY0_12_MSB _u(15) -#define OTP_DATA_BOOTKEY0_12_LSB _u(0) -#define OTP_DATA_BOOTKEY0_12_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_BOOTKEY0_13 -// Description : Bits 223:208 of SHA-256 hash of boot key 0 (ECC) -#define OTP_DATA_BOOTKEY0_13_ROW _u(0x0000008d) -#define OTP_DATA_BOOTKEY0_13_BITS _u(0x0000ffff) -#define OTP_DATA_BOOTKEY0_13_RESET "-" -#define OTP_DATA_BOOTKEY0_13_WIDTH _u(16) -#define OTP_DATA_BOOTKEY0_13_MSB _u(15) -#define OTP_DATA_BOOTKEY0_13_LSB _u(0) -#define OTP_DATA_BOOTKEY0_13_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_BOOTKEY0_14 -// Description : Bits 239:224 of SHA-256 hash of boot key 0 (ECC) -#define OTP_DATA_BOOTKEY0_14_ROW _u(0x0000008e) -#define OTP_DATA_BOOTKEY0_14_BITS _u(0x0000ffff) -#define OTP_DATA_BOOTKEY0_14_RESET "-" -#define OTP_DATA_BOOTKEY0_14_WIDTH _u(16) -#define OTP_DATA_BOOTKEY0_14_MSB _u(15) -#define OTP_DATA_BOOTKEY0_14_LSB _u(0) -#define OTP_DATA_BOOTKEY0_14_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_BOOTKEY0_15 -// Description : Bits 255:240 of SHA-256 hash of boot key 0 (ECC) -#define OTP_DATA_BOOTKEY0_15_ROW _u(0x0000008f) -#define OTP_DATA_BOOTKEY0_15_BITS _u(0x0000ffff) -#define OTP_DATA_BOOTKEY0_15_RESET "-" -#define OTP_DATA_BOOTKEY0_15_WIDTH _u(16) -#define OTP_DATA_BOOTKEY0_15_MSB _u(15) -#define OTP_DATA_BOOTKEY0_15_LSB _u(0) -#define OTP_DATA_BOOTKEY0_15_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_BOOTKEY1_0 -// Description : Bits 15:0 of SHA-256 hash of boot key 1 (ECC) -#define OTP_DATA_BOOTKEY1_0_ROW _u(0x00000090) -#define OTP_DATA_BOOTKEY1_0_BITS _u(0x0000ffff) -#define OTP_DATA_BOOTKEY1_0_RESET "-" -#define OTP_DATA_BOOTKEY1_0_WIDTH _u(16) -#define OTP_DATA_BOOTKEY1_0_MSB _u(15) -#define OTP_DATA_BOOTKEY1_0_LSB _u(0) -#define OTP_DATA_BOOTKEY1_0_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_BOOTKEY1_1 -// Description : Bits 31:16 of SHA-256 hash of boot key 1 (ECC) -#define OTP_DATA_BOOTKEY1_1_ROW _u(0x00000091) -#define OTP_DATA_BOOTKEY1_1_BITS _u(0x0000ffff) -#define OTP_DATA_BOOTKEY1_1_RESET "-" -#define OTP_DATA_BOOTKEY1_1_WIDTH _u(16) -#define OTP_DATA_BOOTKEY1_1_MSB _u(15) -#define OTP_DATA_BOOTKEY1_1_LSB _u(0) -#define OTP_DATA_BOOTKEY1_1_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_BOOTKEY1_2 -// Description : Bits 47:32 of SHA-256 hash of boot key 1 (ECC) -#define OTP_DATA_BOOTKEY1_2_ROW _u(0x00000092) -#define OTP_DATA_BOOTKEY1_2_BITS _u(0x0000ffff) -#define OTP_DATA_BOOTKEY1_2_RESET "-" -#define OTP_DATA_BOOTKEY1_2_WIDTH _u(16) -#define OTP_DATA_BOOTKEY1_2_MSB _u(15) -#define OTP_DATA_BOOTKEY1_2_LSB _u(0) -#define OTP_DATA_BOOTKEY1_2_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_BOOTKEY1_3 -// Description : Bits 63:48 of SHA-256 hash of boot key 1 (ECC) -#define OTP_DATA_BOOTKEY1_3_ROW _u(0x00000093) -#define OTP_DATA_BOOTKEY1_3_BITS _u(0x0000ffff) -#define OTP_DATA_BOOTKEY1_3_RESET "-" -#define OTP_DATA_BOOTKEY1_3_WIDTH _u(16) -#define OTP_DATA_BOOTKEY1_3_MSB _u(15) -#define OTP_DATA_BOOTKEY1_3_LSB _u(0) -#define OTP_DATA_BOOTKEY1_3_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_BOOTKEY1_4 -// Description : Bits 79:64 of SHA-256 hash of boot key 1 (ECC) -#define OTP_DATA_BOOTKEY1_4_ROW _u(0x00000094) -#define OTP_DATA_BOOTKEY1_4_BITS _u(0x0000ffff) -#define OTP_DATA_BOOTKEY1_4_RESET "-" -#define OTP_DATA_BOOTKEY1_4_WIDTH _u(16) -#define OTP_DATA_BOOTKEY1_4_MSB _u(15) -#define OTP_DATA_BOOTKEY1_4_LSB _u(0) -#define OTP_DATA_BOOTKEY1_4_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_BOOTKEY1_5 -// Description : Bits 95:80 of SHA-256 hash of boot key 1 (ECC) -#define OTP_DATA_BOOTKEY1_5_ROW _u(0x00000095) -#define OTP_DATA_BOOTKEY1_5_BITS _u(0x0000ffff) -#define OTP_DATA_BOOTKEY1_5_RESET "-" -#define OTP_DATA_BOOTKEY1_5_WIDTH _u(16) -#define OTP_DATA_BOOTKEY1_5_MSB _u(15) -#define OTP_DATA_BOOTKEY1_5_LSB _u(0) -#define OTP_DATA_BOOTKEY1_5_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_BOOTKEY1_6 -// Description : Bits 111:96 of SHA-256 hash of boot key 1 (ECC) -#define OTP_DATA_BOOTKEY1_6_ROW _u(0x00000096) -#define OTP_DATA_BOOTKEY1_6_BITS _u(0x0000ffff) -#define OTP_DATA_BOOTKEY1_6_RESET "-" -#define OTP_DATA_BOOTKEY1_6_WIDTH _u(16) -#define OTP_DATA_BOOTKEY1_6_MSB _u(15) -#define OTP_DATA_BOOTKEY1_6_LSB _u(0) -#define OTP_DATA_BOOTKEY1_6_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_BOOTKEY1_7 -// Description : Bits 127:112 of SHA-256 hash of boot key 1 (ECC) -#define OTP_DATA_BOOTKEY1_7_ROW _u(0x00000097) -#define OTP_DATA_BOOTKEY1_7_BITS _u(0x0000ffff) -#define OTP_DATA_BOOTKEY1_7_RESET "-" -#define OTP_DATA_BOOTKEY1_7_WIDTH _u(16) -#define OTP_DATA_BOOTKEY1_7_MSB _u(15) -#define OTP_DATA_BOOTKEY1_7_LSB _u(0) -#define OTP_DATA_BOOTKEY1_7_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_BOOTKEY1_8 -// Description : Bits 143:128 of SHA-256 hash of boot key 1 (ECC) -#define OTP_DATA_BOOTKEY1_8_ROW _u(0x00000098) -#define OTP_DATA_BOOTKEY1_8_BITS _u(0x0000ffff) -#define OTP_DATA_BOOTKEY1_8_RESET "-" -#define OTP_DATA_BOOTKEY1_8_WIDTH _u(16) -#define OTP_DATA_BOOTKEY1_8_MSB _u(15) -#define OTP_DATA_BOOTKEY1_8_LSB _u(0) -#define OTP_DATA_BOOTKEY1_8_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_BOOTKEY1_9 -// Description : Bits 159:144 of SHA-256 hash of boot key 1 (ECC) -#define OTP_DATA_BOOTKEY1_9_ROW _u(0x00000099) -#define OTP_DATA_BOOTKEY1_9_BITS _u(0x0000ffff) -#define OTP_DATA_BOOTKEY1_9_RESET "-" -#define OTP_DATA_BOOTKEY1_9_WIDTH _u(16) -#define OTP_DATA_BOOTKEY1_9_MSB _u(15) -#define OTP_DATA_BOOTKEY1_9_LSB _u(0) -#define OTP_DATA_BOOTKEY1_9_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_BOOTKEY1_10 -// Description : Bits 175:160 of SHA-256 hash of boot key 1 (ECC) -#define OTP_DATA_BOOTKEY1_10_ROW _u(0x0000009a) -#define OTP_DATA_BOOTKEY1_10_BITS _u(0x0000ffff) -#define OTP_DATA_BOOTKEY1_10_RESET "-" -#define OTP_DATA_BOOTKEY1_10_WIDTH _u(16) -#define OTP_DATA_BOOTKEY1_10_MSB _u(15) -#define OTP_DATA_BOOTKEY1_10_LSB _u(0) -#define OTP_DATA_BOOTKEY1_10_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_BOOTKEY1_11 -// Description : Bits 191:176 of SHA-256 hash of boot key 1 (ECC) -#define OTP_DATA_BOOTKEY1_11_ROW _u(0x0000009b) -#define OTP_DATA_BOOTKEY1_11_BITS _u(0x0000ffff) -#define OTP_DATA_BOOTKEY1_11_RESET "-" -#define OTP_DATA_BOOTKEY1_11_WIDTH _u(16) -#define OTP_DATA_BOOTKEY1_11_MSB _u(15) -#define OTP_DATA_BOOTKEY1_11_LSB _u(0) -#define OTP_DATA_BOOTKEY1_11_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_BOOTKEY1_12 -// Description : Bits 207:192 of SHA-256 hash of boot key 1 (ECC) -#define OTP_DATA_BOOTKEY1_12_ROW _u(0x0000009c) -#define OTP_DATA_BOOTKEY1_12_BITS _u(0x0000ffff) -#define OTP_DATA_BOOTKEY1_12_RESET "-" -#define OTP_DATA_BOOTKEY1_12_WIDTH _u(16) -#define OTP_DATA_BOOTKEY1_12_MSB _u(15) -#define OTP_DATA_BOOTKEY1_12_LSB _u(0) -#define OTP_DATA_BOOTKEY1_12_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_BOOTKEY1_13 -// Description : Bits 223:208 of SHA-256 hash of boot key 1 (ECC) -#define OTP_DATA_BOOTKEY1_13_ROW _u(0x0000009d) -#define OTP_DATA_BOOTKEY1_13_BITS _u(0x0000ffff) -#define OTP_DATA_BOOTKEY1_13_RESET "-" -#define OTP_DATA_BOOTKEY1_13_WIDTH _u(16) -#define OTP_DATA_BOOTKEY1_13_MSB _u(15) -#define OTP_DATA_BOOTKEY1_13_LSB _u(0) -#define OTP_DATA_BOOTKEY1_13_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_BOOTKEY1_14 -// Description : Bits 239:224 of SHA-256 hash of boot key 1 (ECC) -#define OTP_DATA_BOOTKEY1_14_ROW _u(0x0000009e) -#define OTP_DATA_BOOTKEY1_14_BITS _u(0x0000ffff) -#define OTP_DATA_BOOTKEY1_14_RESET "-" -#define OTP_DATA_BOOTKEY1_14_WIDTH _u(16) -#define OTP_DATA_BOOTKEY1_14_MSB _u(15) -#define OTP_DATA_BOOTKEY1_14_LSB _u(0) -#define OTP_DATA_BOOTKEY1_14_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_BOOTKEY1_15 -// Description : Bits 255:240 of SHA-256 hash of boot key 1 (ECC) -#define OTP_DATA_BOOTKEY1_15_ROW _u(0x0000009f) -#define OTP_DATA_BOOTKEY1_15_BITS _u(0x0000ffff) -#define OTP_DATA_BOOTKEY1_15_RESET "-" -#define OTP_DATA_BOOTKEY1_15_WIDTH _u(16) -#define OTP_DATA_BOOTKEY1_15_MSB _u(15) -#define OTP_DATA_BOOTKEY1_15_LSB _u(0) -#define OTP_DATA_BOOTKEY1_15_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_BOOTKEY2_0 -// Description : Bits 15:0 of SHA-256 hash of boot key 2 (ECC) -#define OTP_DATA_BOOTKEY2_0_ROW _u(0x000000a0) -#define OTP_DATA_BOOTKEY2_0_BITS _u(0x0000ffff) -#define OTP_DATA_BOOTKEY2_0_RESET "-" -#define OTP_DATA_BOOTKEY2_0_WIDTH _u(16) -#define OTP_DATA_BOOTKEY2_0_MSB _u(15) -#define OTP_DATA_BOOTKEY2_0_LSB _u(0) -#define OTP_DATA_BOOTKEY2_0_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_BOOTKEY2_1 -// Description : Bits 31:16 of SHA-256 hash of boot key 2 (ECC) -#define OTP_DATA_BOOTKEY2_1_ROW _u(0x000000a1) -#define OTP_DATA_BOOTKEY2_1_BITS _u(0x0000ffff) -#define OTP_DATA_BOOTKEY2_1_RESET "-" -#define OTP_DATA_BOOTKEY2_1_WIDTH _u(16) -#define OTP_DATA_BOOTKEY2_1_MSB _u(15) -#define OTP_DATA_BOOTKEY2_1_LSB _u(0) -#define OTP_DATA_BOOTKEY2_1_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_BOOTKEY2_2 -// Description : Bits 47:32 of SHA-256 hash of boot key 2 (ECC) -#define OTP_DATA_BOOTKEY2_2_ROW _u(0x000000a2) -#define OTP_DATA_BOOTKEY2_2_BITS _u(0x0000ffff) -#define OTP_DATA_BOOTKEY2_2_RESET "-" -#define OTP_DATA_BOOTKEY2_2_WIDTH _u(16) -#define OTP_DATA_BOOTKEY2_2_MSB _u(15) -#define OTP_DATA_BOOTKEY2_2_LSB _u(0) -#define OTP_DATA_BOOTKEY2_2_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_BOOTKEY2_3 -// Description : Bits 63:48 of SHA-256 hash of boot key 2 (ECC) -#define OTP_DATA_BOOTKEY2_3_ROW _u(0x000000a3) -#define OTP_DATA_BOOTKEY2_3_BITS _u(0x0000ffff) -#define OTP_DATA_BOOTKEY2_3_RESET "-" -#define OTP_DATA_BOOTKEY2_3_WIDTH _u(16) -#define OTP_DATA_BOOTKEY2_3_MSB _u(15) -#define OTP_DATA_BOOTKEY2_3_LSB _u(0) -#define OTP_DATA_BOOTKEY2_3_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_BOOTKEY2_4 -// Description : Bits 79:64 of SHA-256 hash of boot key 2 (ECC) -#define OTP_DATA_BOOTKEY2_4_ROW _u(0x000000a4) -#define OTP_DATA_BOOTKEY2_4_BITS _u(0x0000ffff) -#define OTP_DATA_BOOTKEY2_4_RESET "-" -#define OTP_DATA_BOOTKEY2_4_WIDTH _u(16) -#define OTP_DATA_BOOTKEY2_4_MSB _u(15) -#define OTP_DATA_BOOTKEY2_4_LSB _u(0) -#define OTP_DATA_BOOTKEY2_4_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_BOOTKEY2_5 -// Description : Bits 95:80 of SHA-256 hash of boot key 2 (ECC) -#define OTP_DATA_BOOTKEY2_5_ROW _u(0x000000a5) -#define OTP_DATA_BOOTKEY2_5_BITS _u(0x0000ffff) -#define OTP_DATA_BOOTKEY2_5_RESET "-" -#define OTP_DATA_BOOTKEY2_5_WIDTH _u(16) -#define OTP_DATA_BOOTKEY2_5_MSB _u(15) -#define OTP_DATA_BOOTKEY2_5_LSB _u(0) -#define OTP_DATA_BOOTKEY2_5_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_BOOTKEY2_6 -// Description : Bits 111:96 of SHA-256 hash of boot key 2 (ECC) -#define OTP_DATA_BOOTKEY2_6_ROW _u(0x000000a6) -#define OTP_DATA_BOOTKEY2_6_BITS _u(0x0000ffff) -#define OTP_DATA_BOOTKEY2_6_RESET "-" -#define OTP_DATA_BOOTKEY2_6_WIDTH _u(16) -#define OTP_DATA_BOOTKEY2_6_MSB _u(15) -#define OTP_DATA_BOOTKEY2_6_LSB _u(0) -#define OTP_DATA_BOOTKEY2_6_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_BOOTKEY2_7 -// Description : Bits 127:112 of SHA-256 hash of boot key 2 (ECC) -#define OTP_DATA_BOOTKEY2_7_ROW _u(0x000000a7) -#define OTP_DATA_BOOTKEY2_7_BITS _u(0x0000ffff) -#define OTP_DATA_BOOTKEY2_7_RESET "-" -#define OTP_DATA_BOOTKEY2_7_WIDTH _u(16) -#define OTP_DATA_BOOTKEY2_7_MSB _u(15) -#define OTP_DATA_BOOTKEY2_7_LSB _u(0) -#define OTP_DATA_BOOTKEY2_7_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_BOOTKEY2_8 -// Description : Bits 143:128 of SHA-256 hash of boot key 2 (ECC) -#define OTP_DATA_BOOTKEY2_8_ROW _u(0x000000a8) -#define OTP_DATA_BOOTKEY2_8_BITS _u(0x0000ffff) -#define OTP_DATA_BOOTKEY2_8_RESET "-" -#define OTP_DATA_BOOTKEY2_8_WIDTH _u(16) -#define OTP_DATA_BOOTKEY2_8_MSB _u(15) -#define OTP_DATA_BOOTKEY2_8_LSB _u(0) -#define OTP_DATA_BOOTKEY2_8_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_BOOTKEY2_9 -// Description : Bits 159:144 of SHA-256 hash of boot key 2 (ECC) -#define OTP_DATA_BOOTKEY2_9_ROW _u(0x000000a9) -#define OTP_DATA_BOOTKEY2_9_BITS _u(0x0000ffff) -#define OTP_DATA_BOOTKEY2_9_RESET "-" -#define OTP_DATA_BOOTKEY2_9_WIDTH _u(16) -#define OTP_DATA_BOOTKEY2_9_MSB _u(15) -#define OTP_DATA_BOOTKEY2_9_LSB _u(0) -#define OTP_DATA_BOOTKEY2_9_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_BOOTKEY2_10 -// Description : Bits 175:160 of SHA-256 hash of boot key 2 (ECC) -#define OTP_DATA_BOOTKEY2_10_ROW _u(0x000000aa) -#define OTP_DATA_BOOTKEY2_10_BITS _u(0x0000ffff) -#define OTP_DATA_BOOTKEY2_10_RESET "-" -#define OTP_DATA_BOOTKEY2_10_WIDTH _u(16) -#define OTP_DATA_BOOTKEY2_10_MSB _u(15) -#define OTP_DATA_BOOTKEY2_10_LSB _u(0) -#define OTP_DATA_BOOTKEY2_10_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_BOOTKEY2_11 -// Description : Bits 191:176 of SHA-256 hash of boot key 2 (ECC) -#define OTP_DATA_BOOTKEY2_11_ROW _u(0x000000ab) -#define OTP_DATA_BOOTKEY2_11_BITS _u(0x0000ffff) -#define OTP_DATA_BOOTKEY2_11_RESET "-" -#define OTP_DATA_BOOTKEY2_11_WIDTH _u(16) -#define OTP_DATA_BOOTKEY2_11_MSB _u(15) -#define OTP_DATA_BOOTKEY2_11_LSB _u(0) -#define OTP_DATA_BOOTKEY2_11_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_BOOTKEY2_12 -// Description : Bits 207:192 of SHA-256 hash of boot key 2 (ECC) -#define OTP_DATA_BOOTKEY2_12_ROW _u(0x000000ac) -#define OTP_DATA_BOOTKEY2_12_BITS _u(0x0000ffff) -#define OTP_DATA_BOOTKEY2_12_RESET "-" -#define OTP_DATA_BOOTKEY2_12_WIDTH _u(16) -#define OTP_DATA_BOOTKEY2_12_MSB _u(15) -#define OTP_DATA_BOOTKEY2_12_LSB _u(0) -#define OTP_DATA_BOOTKEY2_12_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_BOOTKEY2_13 -// Description : Bits 223:208 of SHA-256 hash of boot key 2 (ECC) -#define OTP_DATA_BOOTKEY2_13_ROW _u(0x000000ad) -#define OTP_DATA_BOOTKEY2_13_BITS _u(0x0000ffff) -#define OTP_DATA_BOOTKEY2_13_RESET "-" -#define OTP_DATA_BOOTKEY2_13_WIDTH _u(16) -#define OTP_DATA_BOOTKEY2_13_MSB _u(15) -#define OTP_DATA_BOOTKEY2_13_LSB _u(0) -#define OTP_DATA_BOOTKEY2_13_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_BOOTKEY2_14 -// Description : Bits 239:224 of SHA-256 hash of boot key 2 (ECC) -#define OTP_DATA_BOOTKEY2_14_ROW _u(0x000000ae) -#define OTP_DATA_BOOTKEY2_14_BITS _u(0x0000ffff) -#define OTP_DATA_BOOTKEY2_14_RESET "-" -#define OTP_DATA_BOOTKEY2_14_WIDTH _u(16) -#define OTP_DATA_BOOTKEY2_14_MSB _u(15) -#define OTP_DATA_BOOTKEY2_14_LSB _u(0) -#define OTP_DATA_BOOTKEY2_14_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_BOOTKEY2_15 -// Description : Bits 255:240 of SHA-256 hash of boot key 2 (ECC) -#define OTP_DATA_BOOTKEY2_15_ROW _u(0x000000af) -#define OTP_DATA_BOOTKEY2_15_BITS _u(0x0000ffff) -#define OTP_DATA_BOOTKEY2_15_RESET "-" -#define OTP_DATA_BOOTKEY2_15_WIDTH _u(16) -#define OTP_DATA_BOOTKEY2_15_MSB _u(15) -#define OTP_DATA_BOOTKEY2_15_LSB _u(0) -#define OTP_DATA_BOOTKEY2_15_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_BOOTKEY3_0 -// Description : Bits 15:0 of SHA-256 hash of boot key 3 (ECC) -#define OTP_DATA_BOOTKEY3_0_ROW _u(0x000000b0) -#define OTP_DATA_BOOTKEY3_0_BITS _u(0x0000ffff) -#define OTP_DATA_BOOTKEY3_0_RESET "-" -#define OTP_DATA_BOOTKEY3_0_WIDTH _u(16) -#define OTP_DATA_BOOTKEY3_0_MSB _u(15) -#define OTP_DATA_BOOTKEY3_0_LSB _u(0) -#define OTP_DATA_BOOTKEY3_0_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_BOOTKEY3_1 -// Description : Bits 31:16 of SHA-256 hash of boot key 3 (ECC) -#define OTP_DATA_BOOTKEY3_1_ROW _u(0x000000b1) -#define OTP_DATA_BOOTKEY3_1_BITS _u(0x0000ffff) -#define OTP_DATA_BOOTKEY3_1_RESET "-" -#define OTP_DATA_BOOTKEY3_1_WIDTH _u(16) -#define OTP_DATA_BOOTKEY3_1_MSB _u(15) -#define OTP_DATA_BOOTKEY3_1_LSB _u(0) -#define OTP_DATA_BOOTKEY3_1_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_BOOTKEY3_2 -// Description : Bits 47:32 of SHA-256 hash of boot key 3 (ECC) -#define OTP_DATA_BOOTKEY3_2_ROW _u(0x000000b2) -#define OTP_DATA_BOOTKEY3_2_BITS _u(0x0000ffff) -#define OTP_DATA_BOOTKEY3_2_RESET "-" -#define OTP_DATA_BOOTKEY3_2_WIDTH _u(16) -#define OTP_DATA_BOOTKEY3_2_MSB _u(15) -#define OTP_DATA_BOOTKEY3_2_LSB _u(0) -#define OTP_DATA_BOOTKEY3_2_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_BOOTKEY3_3 -// Description : Bits 63:48 of SHA-256 hash of boot key 3 (ECC) -#define OTP_DATA_BOOTKEY3_3_ROW _u(0x000000b3) -#define OTP_DATA_BOOTKEY3_3_BITS _u(0x0000ffff) -#define OTP_DATA_BOOTKEY3_3_RESET "-" -#define OTP_DATA_BOOTKEY3_3_WIDTH _u(16) -#define OTP_DATA_BOOTKEY3_3_MSB _u(15) -#define OTP_DATA_BOOTKEY3_3_LSB _u(0) -#define OTP_DATA_BOOTKEY3_3_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_BOOTKEY3_4 -// Description : Bits 79:64 of SHA-256 hash of boot key 3 (ECC) -#define OTP_DATA_BOOTKEY3_4_ROW _u(0x000000b4) -#define OTP_DATA_BOOTKEY3_4_BITS _u(0x0000ffff) -#define OTP_DATA_BOOTKEY3_4_RESET "-" -#define OTP_DATA_BOOTKEY3_4_WIDTH _u(16) -#define OTP_DATA_BOOTKEY3_4_MSB _u(15) -#define OTP_DATA_BOOTKEY3_4_LSB _u(0) -#define OTP_DATA_BOOTKEY3_4_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_BOOTKEY3_5 -// Description : Bits 95:80 of SHA-256 hash of boot key 3 (ECC) -#define OTP_DATA_BOOTKEY3_5_ROW _u(0x000000b5) -#define OTP_DATA_BOOTKEY3_5_BITS _u(0x0000ffff) -#define OTP_DATA_BOOTKEY3_5_RESET "-" -#define OTP_DATA_BOOTKEY3_5_WIDTH _u(16) -#define OTP_DATA_BOOTKEY3_5_MSB _u(15) -#define OTP_DATA_BOOTKEY3_5_LSB _u(0) -#define OTP_DATA_BOOTKEY3_5_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_BOOTKEY3_6 -// Description : Bits 111:96 of SHA-256 hash of boot key 3 (ECC) -#define OTP_DATA_BOOTKEY3_6_ROW _u(0x000000b6) -#define OTP_DATA_BOOTKEY3_6_BITS _u(0x0000ffff) -#define OTP_DATA_BOOTKEY3_6_RESET "-" -#define OTP_DATA_BOOTKEY3_6_WIDTH _u(16) -#define OTP_DATA_BOOTKEY3_6_MSB _u(15) -#define OTP_DATA_BOOTKEY3_6_LSB _u(0) -#define OTP_DATA_BOOTKEY3_6_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_BOOTKEY3_7 -// Description : Bits 127:112 of SHA-256 hash of boot key 3 (ECC) -#define OTP_DATA_BOOTKEY3_7_ROW _u(0x000000b7) -#define OTP_DATA_BOOTKEY3_7_BITS _u(0x0000ffff) -#define OTP_DATA_BOOTKEY3_7_RESET "-" -#define OTP_DATA_BOOTKEY3_7_WIDTH _u(16) -#define OTP_DATA_BOOTKEY3_7_MSB _u(15) -#define OTP_DATA_BOOTKEY3_7_LSB _u(0) -#define OTP_DATA_BOOTKEY3_7_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_BOOTKEY3_8 -// Description : Bits 143:128 of SHA-256 hash of boot key 3 (ECC) -#define OTP_DATA_BOOTKEY3_8_ROW _u(0x000000b8) -#define OTP_DATA_BOOTKEY3_8_BITS _u(0x0000ffff) -#define OTP_DATA_BOOTKEY3_8_RESET "-" -#define OTP_DATA_BOOTKEY3_8_WIDTH _u(16) -#define OTP_DATA_BOOTKEY3_8_MSB _u(15) -#define OTP_DATA_BOOTKEY3_8_LSB _u(0) -#define OTP_DATA_BOOTKEY3_8_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_BOOTKEY3_9 -// Description : Bits 159:144 of SHA-256 hash of boot key 3 (ECC) -#define OTP_DATA_BOOTKEY3_9_ROW _u(0x000000b9) -#define OTP_DATA_BOOTKEY3_9_BITS _u(0x0000ffff) -#define OTP_DATA_BOOTKEY3_9_RESET "-" -#define OTP_DATA_BOOTKEY3_9_WIDTH _u(16) -#define OTP_DATA_BOOTKEY3_9_MSB _u(15) -#define OTP_DATA_BOOTKEY3_9_LSB _u(0) -#define OTP_DATA_BOOTKEY3_9_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_BOOTKEY3_10 -// Description : Bits 175:160 of SHA-256 hash of boot key 3 (ECC) -#define OTP_DATA_BOOTKEY3_10_ROW _u(0x000000ba) -#define OTP_DATA_BOOTKEY3_10_BITS _u(0x0000ffff) -#define OTP_DATA_BOOTKEY3_10_RESET "-" -#define OTP_DATA_BOOTKEY3_10_WIDTH _u(16) -#define OTP_DATA_BOOTKEY3_10_MSB _u(15) -#define OTP_DATA_BOOTKEY3_10_LSB _u(0) -#define OTP_DATA_BOOTKEY3_10_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_BOOTKEY3_11 -// Description : Bits 191:176 of SHA-256 hash of boot key 3 (ECC) -#define OTP_DATA_BOOTKEY3_11_ROW _u(0x000000bb) -#define OTP_DATA_BOOTKEY3_11_BITS _u(0x0000ffff) -#define OTP_DATA_BOOTKEY3_11_RESET "-" -#define OTP_DATA_BOOTKEY3_11_WIDTH _u(16) -#define OTP_DATA_BOOTKEY3_11_MSB _u(15) -#define OTP_DATA_BOOTKEY3_11_LSB _u(0) -#define OTP_DATA_BOOTKEY3_11_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_BOOTKEY3_12 -// Description : Bits 207:192 of SHA-256 hash of boot key 3 (ECC) -#define OTP_DATA_BOOTKEY3_12_ROW _u(0x000000bc) -#define OTP_DATA_BOOTKEY3_12_BITS _u(0x0000ffff) -#define OTP_DATA_BOOTKEY3_12_RESET "-" -#define OTP_DATA_BOOTKEY3_12_WIDTH _u(16) -#define OTP_DATA_BOOTKEY3_12_MSB _u(15) -#define OTP_DATA_BOOTKEY3_12_LSB _u(0) -#define OTP_DATA_BOOTKEY3_12_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_BOOTKEY3_13 -// Description : Bits 223:208 of SHA-256 hash of boot key 3 (ECC) -#define OTP_DATA_BOOTKEY3_13_ROW _u(0x000000bd) -#define OTP_DATA_BOOTKEY3_13_BITS _u(0x0000ffff) -#define OTP_DATA_BOOTKEY3_13_RESET "-" -#define OTP_DATA_BOOTKEY3_13_WIDTH _u(16) -#define OTP_DATA_BOOTKEY3_13_MSB _u(15) -#define OTP_DATA_BOOTKEY3_13_LSB _u(0) -#define OTP_DATA_BOOTKEY3_13_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_BOOTKEY3_14 -// Description : Bits 239:224 of SHA-256 hash of boot key 3 (ECC) -#define OTP_DATA_BOOTKEY3_14_ROW _u(0x000000be) -#define OTP_DATA_BOOTKEY3_14_BITS _u(0x0000ffff) -#define OTP_DATA_BOOTKEY3_14_RESET "-" -#define OTP_DATA_BOOTKEY3_14_WIDTH _u(16) -#define OTP_DATA_BOOTKEY3_14_MSB _u(15) -#define OTP_DATA_BOOTKEY3_14_LSB _u(0) -#define OTP_DATA_BOOTKEY3_14_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_BOOTKEY3_15 -// Description : Bits 255:240 of SHA-256 hash of boot key 3 (ECC) -#define OTP_DATA_BOOTKEY3_15_ROW _u(0x000000bf) -#define OTP_DATA_BOOTKEY3_15_BITS _u(0x0000ffff) -#define OTP_DATA_BOOTKEY3_15_RESET "-" -#define OTP_DATA_BOOTKEY3_15_WIDTH _u(16) -#define OTP_DATA_BOOTKEY3_15_MSB _u(15) -#define OTP_DATA_BOOTKEY3_15_LSB _u(0) -#define OTP_DATA_BOOTKEY3_15_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_KEY1_0 -// Description : Bits 15:0 of OTP access key 1 (ECC) -#define OTP_DATA_KEY1_0_ROW _u(0x00000f48) -#define OTP_DATA_KEY1_0_BITS _u(0x0000ffff) -#define OTP_DATA_KEY1_0_RESET "-" -#define OTP_DATA_KEY1_0_WIDTH _u(16) -#define OTP_DATA_KEY1_0_MSB _u(15) -#define OTP_DATA_KEY1_0_LSB _u(0) -#define OTP_DATA_KEY1_0_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_KEY1_1 -// Description : Bits 31:16 of OTP access key 1 (ECC) -#define OTP_DATA_KEY1_1_ROW _u(0x00000f49) -#define OTP_DATA_KEY1_1_BITS _u(0x0000ffff) -#define OTP_DATA_KEY1_1_RESET "-" -#define OTP_DATA_KEY1_1_WIDTH _u(16) -#define OTP_DATA_KEY1_1_MSB _u(15) -#define OTP_DATA_KEY1_1_LSB _u(0) -#define OTP_DATA_KEY1_1_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_KEY1_2 -// Description : Bits 47:32 of OTP access key 1 (ECC) -#define OTP_DATA_KEY1_2_ROW _u(0x00000f4a) -#define OTP_DATA_KEY1_2_BITS _u(0x0000ffff) -#define OTP_DATA_KEY1_2_RESET "-" -#define OTP_DATA_KEY1_2_WIDTH _u(16) -#define OTP_DATA_KEY1_2_MSB _u(15) -#define OTP_DATA_KEY1_2_LSB _u(0) -#define OTP_DATA_KEY1_2_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_KEY1_3 -// Description : Bits 63:48 of OTP access key 1 (ECC) -#define OTP_DATA_KEY1_3_ROW _u(0x00000f4b) -#define OTP_DATA_KEY1_3_BITS _u(0x0000ffff) -#define OTP_DATA_KEY1_3_RESET "-" -#define OTP_DATA_KEY1_3_WIDTH _u(16) -#define OTP_DATA_KEY1_3_MSB _u(15) -#define OTP_DATA_KEY1_3_LSB _u(0) -#define OTP_DATA_KEY1_3_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_KEY1_4 -// Description : Bits 79:64 of OTP access key 1 (ECC) -#define OTP_DATA_KEY1_4_ROW _u(0x00000f4c) -#define OTP_DATA_KEY1_4_BITS _u(0x0000ffff) -#define OTP_DATA_KEY1_4_RESET "-" -#define OTP_DATA_KEY1_4_WIDTH _u(16) -#define OTP_DATA_KEY1_4_MSB _u(15) -#define OTP_DATA_KEY1_4_LSB _u(0) -#define OTP_DATA_KEY1_4_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_KEY1_5 -// Description : Bits 95:80 of OTP access key 1 (ECC) -#define OTP_DATA_KEY1_5_ROW _u(0x00000f4d) -#define OTP_DATA_KEY1_5_BITS _u(0x0000ffff) -#define OTP_DATA_KEY1_5_RESET "-" -#define OTP_DATA_KEY1_5_WIDTH _u(16) -#define OTP_DATA_KEY1_5_MSB _u(15) -#define OTP_DATA_KEY1_5_LSB _u(0) -#define OTP_DATA_KEY1_5_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_KEY1_6 -// Description : Bits 111:96 of OTP access key 1 (ECC) -#define OTP_DATA_KEY1_6_ROW _u(0x00000f4e) -#define OTP_DATA_KEY1_6_BITS _u(0x0000ffff) -#define OTP_DATA_KEY1_6_RESET "-" -#define OTP_DATA_KEY1_6_WIDTH _u(16) -#define OTP_DATA_KEY1_6_MSB _u(15) -#define OTP_DATA_KEY1_6_LSB _u(0) -#define OTP_DATA_KEY1_6_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_KEY1_7 -// Description : Bits 127:112 of OTP access key 1 (ECC) -#define OTP_DATA_KEY1_7_ROW _u(0x00000f4f) -#define OTP_DATA_KEY1_7_BITS _u(0x0000ffff) -#define OTP_DATA_KEY1_7_RESET "-" -#define OTP_DATA_KEY1_7_WIDTH _u(16) -#define OTP_DATA_KEY1_7_MSB _u(15) -#define OTP_DATA_KEY1_7_LSB _u(0) -#define OTP_DATA_KEY1_7_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_KEY2_0 -// Description : Bits 15:0 of OTP access key 2 (ECC) -#define OTP_DATA_KEY2_0_ROW _u(0x00000f50) -#define OTP_DATA_KEY2_0_BITS _u(0x0000ffff) -#define OTP_DATA_KEY2_0_RESET "-" -#define OTP_DATA_KEY2_0_WIDTH _u(16) -#define OTP_DATA_KEY2_0_MSB _u(15) -#define OTP_DATA_KEY2_0_LSB _u(0) -#define OTP_DATA_KEY2_0_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_KEY2_1 -// Description : Bits 31:16 of OTP access key 2 (ECC) -#define OTP_DATA_KEY2_1_ROW _u(0x00000f51) -#define OTP_DATA_KEY2_1_BITS _u(0x0000ffff) -#define OTP_DATA_KEY2_1_RESET "-" -#define OTP_DATA_KEY2_1_WIDTH _u(16) -#define OTP_DATA_KEY2_1_MSB _u(15) -#define OTP_DATA_KEY2_1_LSB _u(0) -#define OTP_DATA_KEY2_1_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_KEY2_2 -// Description : Bits 47:32 of OTP access key 2 (ECC) -#define OTP_DATA_KEY2_2_ROW _u(0x00000f52) -#define OTP_DATA_KEY2_2_BITS _u(0x0000ffff) -#define OTP_DATA_KEY2_2_RESET "-" -#define OTP_DATA_KEY2_2_WIDTH _u(16) -#define OTP_DATA_KEY2_2_MSB _u(15) -#define OTP_DATA_KEY2_2_LSB _u(0) -#define OTP_DATA_KEY2_2_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_KEY2_3 -// Description : Bits 63:48 of OTP access key 2 (ECC) -#define OTP_DATA_KEY2_3_ROW _u(0x00000f53) -#define OTP_DATA_KEY2_3_BITS _u(0x0000ffff) -#define OTP_DATA_KEY2_3_RESET "-" -#define OTP_DATA_KEY2_3_WIDTH _u(16) -#define OTP_DATA_KEY2_3_MSB _u(15) -#define OTP_DATA_KEY2_3_LSB _u(0) -#define OTP_DATA_KEY2_3_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_KEY2_4 -// Description : Bits 79:64 of OTP access key 2 (ECC) -#define OTP_DATA_KEY2_4_ROW _u(0x00000f54) -#define OTP_DATA_KEY2_4_BITS _u(0x0000ffff) -#define OTP_DATA_KEY2_4_RESET "-" -#define OTP_DATA_KEY2_4_WIDTH _u(16) -#define OTP_DATA_KEY2_4_MSB _u(15) -#define OTP_DATA_KEY2_4_LSB _u(0) -#define OTP_DATA_KEY2_4_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_KEY2_5 -// Description : Bits 95:80 of OTP access key 2 (ECC) -#define OTP_DATA_KEY2_5_ROW _u(0x00000f55) -#define OTP_DATA_KEY2_5_BITS _u(0x0000ffff) -#define OTP_DATA_KEY2_5_RESET "-" -#define OTP_DATA_KEY2_5_WIDTH _u(16) -#define OTP_DATA_KEY2_5_MSB _u(15) -#define OTP_DATA_KEY2_5_LSB _u(0) -#define OTP_DATA_KEY2_5_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_KEY2_6 -// Description : Bits 111:96 of OTP access key 2 (ECC) -#define OTP_DATA_KEY2_6_ROW _u(0x00000f56) -#define OTP_DATA_KEY2_6_BITS _u(0x0000ffff) -#define OTP_DATA_KEY2_6_RESET "-" -#define OTP_DATA_KEY2_6_WIDTH _u(16) -#define OTP_DATA_KEY2_6_MSB _u(15) -#define OTP_DATA_KEY2_6_LSB _u(0) -#define OTP_DATA_KEY2_6_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_KEY2_7 -// Description : Bits 127:112 of OTP access key 2 (ECC) -#define OTP_DATA_KEY2_7_ROW _u(0x00000f57) -#define OTP_DATA_KEY2_7_BITS _u(0x0000ffff) -#define OTP_DATA_KEY2_7_RESET "-" -#define OTP_DATA_KEY2_7_WIDTH _u(16) -#define OTP_DATA_KEY2_7_MSB _u(15) -#define OTP_DATA_KEY2_7_LSB _u(0) -#define OTP_DATA_KEY2_7_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_KEY3_0 -// Description : Bits 15:0 of OTP access key 3 (ECC) -#define OTP_DATA_KEY3_0_ROW _u(0x00000f58) -#define OTP_DATA_KEY3_0_BITS _u(0x0000ffff) -#define OTP_DATA_KEY3_0_RESET "-" -#define OTP_DATA_KEY3_0_WIDTH _u(16) -#define OTP_DATA_KEY3_0_MSB _u(15) -#define OTP_DATA_KEY3_0_LSB _u(0) -#define OTP_DATA_KEY3_0_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_KEY3_1 -// Description : Bits 31:16 of OTP access key 3 (ECC) -#define OTP_DATA_KEY3_1_ROW _u(0x00000f59) -#define OTP_DATA_KEY3_1_BITS _u(0x0000ffff) -#define OTP_DATA_KEY3_1_RESET "-" -#define OTP_DATA_KEY3_1_WIDTH _u(16) -#define OTP_DATA_KEY3_1_MSB _u(15) -#define OTP_DATA_KEY3_1_LSB _u(0) -#define OTP_DATA_KEY3_1_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_KEY3_2 -// Description : Bits 47:32 of OTP access key 3 (ECC) -#define OTP_DATA_KEY3_2_ROW _u(0x00000f5a) -#define OTP_DATA_KEY3_2_BITS _u(0x0000ffff) -#define OTP_DATA_KEY3_2_RESET "-" -#define OTP_DATA_KEY3_2_WIDTH _u(16) -#define OTP_DATA_KEY3_2_MSB _u(15) -#define OTP_DATA_KEY3_2_LSB _u(0) -#define OTP_DATA_KEY3_2_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_KEY3_3 -// Description : Bits 63:48 of OTP access key 3 (ECC) -#define OTP_DATA_KEY3_3_ROW _u(0x00000f5b) -#define OTP_DATA_KEY3_3_BITS _u(0x0000ffff) -#define OTP_DATA_KEY3_3_RESET "-" -#define OTP_DATA_KEY3_3_WIDTH _u(16) -#define OTP_DATA_KEY3_3_MSB _u(15) -#define OTP_DATA_KEY3_3_LSB _u(0) -#define OTP_DATA_KEY3_3_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_KEY3_4 -// Description : Bits 79:64 of OTP access key 3 (ECC) -#define OTP_DATA_KEY3_4_ROW _u(0x00000f5c) -#define OTP_DATA_KEY3_4_BITS _u(0x0000ffff) -#define OTP_DATA_KEY3_4_RESET "-" -#define OTP_DATA_KEY3_4_WIDTH _u(16) -#define OTP_DATA_KEY3_4_MSB _u(15) -#define OTP_DATA_KEY3_4_LSB _u(0) -#define OTP_DATA_KEY3_4_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_KEY3_5 -// Description : Bits 95:80 of OTP access key 3 (ECC) -#define OTP_DATA_KEY3_5_ROW _u(0x00000f5d) -#define OTP_DATA_KEY3_5_BITS _u(0x0000ffff) -#define OTP_DATA_KEY3_5_RESET "-" -#define OTP_DATA_KEY3_5_WIDTH _u(16) -#define OTP_DATA_KEY3_5_MSB _u(15) -#define OTP_DATA_KEY3_5_LSB _u(0) -#define OTP_DATA_KEY3_5_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_KEY3_6 -// Description : Bits 111:96 of OTP access key 3 (ECC) -#define OTP_DATA_KEY3_6_ROW _u(0x00000f5e) -#define OTP_DATA_KEY3_6_BITS _u(0x0000ffff) -#define OTP_DATA_KEY3_6_RESET "-" -#define OTP_DATA_KEY3_6_WIDTH _u(16) -#define OTP_DATA_KEY3_6_MSB _u(15) -#define OTP_DATA_KEY3_6_LSB _u(0) -#define OTP_DATA_KEY3_6_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_KEY3_7 -// Description : Bits 127:112 of OTP access key 3 (ECC) -#define OTP_DATA_KEY3_7_ROW _u(0x00000f5f) -#define OTP_DATA_KEY3_7_BITS _u(0x0000ffff) -#define OTP_DATA_KEY3_7_RESET "-" -#define OTP_DATA_KEY3_7_WIDTH _u(16) -#define OTP_DATA_KEY3_7_MSB _u(15) -#define OTP_DATA_KEY3_7_LSB _u(0) -#define OTP_DATA_KEY3_7_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_KEY4_0 -// Description : Bits 15:0 of OTP access key 4 (ECC) -#define OTP_DATA_KEY4_0_ROW _u(0x00000f60) -#define OTP_DATA_KEY4_0_BITS _u(0x0000ffff) -#define OTP_DATA_KEY4_0_RESET "-" -#define OTP_DATA_KEY4_0_WIDTH _u(16) -#define OTP_DATA_KEY4_0_MSB _u(15) -#define OTP_DATA_KEY4_0_LSB _u(0) -#define OTP_DATA_KEY4_0_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_KEY4_1 -// Description : Bits 31:16 of OTP access key 4 (ECC) -#define OTP_DATA_KEY4_1_ROW _u(0x00000f61) -#define OTP_DATA_KEY4_1_BITS _u(0x0000ffff) -#define OTP_DATA_KEY4_1_RESET "-" -#define OTP_DATA_KEY4_1_WIDTH _u(16) -#define OTP_DATA_KEY4_1_MSB _u(15) -#define OTP_DATA_KEY4_1_LSB _u(0) -#define OTP_DATA_KEY4_1_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_KEY4_2 -// Description : Bits 47:32 of OTP access key 4 (ECC) -#define OTP_DATA_KEY4_2_ROW _u(0x00000f62) -#define OTP_DATA_KEY4_2_BITS _u(0x0000ffff) -#define OTP_DATA_KEY4_2_RESET "-" -#define OTP_DATA_KEY4_2_WIDTH _u(16) -#define OTP_DATA_KEY4_2_MSB _u(15) -#define OTP_DATA_KEY4_2_LSB _u(0) -#define OTP_DATA_KEY4_2_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_KEY4_3 -// Description : Bits 63:48 of OTP access key 4 (ECC) -#define OTP_DATA_KEY4_3_ROW _u(0x00000f63) -#define OTP_DATA_KEY4_3_BITS _u(0x0000ffff) -#define OTP_DATA_KEY4_3_RESET "-" -#define OTP_DATA_KEY4_3_WIDTH _u(16) -#define OTP_DATA_KEY4_3_MSB _u(15) -#define OTP_DATA_KEY4_3_LSB _u(0) -#define OTP_DATA_KEY4_3_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_KEY4_4 -// Description : Bits 79:64 of OTP access key 4 (ECC) -#define OTP_DATA_KEY4_4_ROW _u(0x00000f64) -#define OTP_DATA_KEY4_4_BITS _u(0x0000ffff) -#define OTP_DATA_KEY4_4_RESET "-" -#define OTP_DATA_KEY4_4_WIDTH _u(16) -#define OTP_DATA_KEY4_4_MSB _u(15) -#define OTP_DATA_KEY4_4_LSB _u(0) -#define OTP_DATA_KEY4_4_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_KEY4_5 -// Description : Bits 95:80 of OTP access key 4 (ECC) -#define OTP_DATA_KEY4_5_ROW _u(0x00000f65) -#define OTP_DATA_KEY4_5_BITS _u(0x0000ffff) -#define OTP_DATA_KEY4_5_RESET "-" -#define OTP_DATA_KEY4_5_WIDTH _u(16) -#define OTP_DATA_KEY4_5_MSB _u(15) -#define OTP_DATA_KEY4_5_LSB _u(0) -#define OTP_DATA_KEY4_5_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_KEY4_6 -// Description : Bits 111:96 of OTP access key 4 (ECC) -#define OTP_DATA_KEY4_6_ROW _u(0x00000f66) -#define OTP_DATA_KEY4_6_BITS _u(0x0000ffff) -#define OTP_DATA_KEY4_6_RESET "-" -#define OTP_DATA_KEY4_6_WIDTH _u(16) -#define OTP_DATA_KEY4_6_MSB _u(15) -#define OTP_DATA_KEY4_6_LSB _u(0) -#define OTP_DATA_KEY4_6_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_KEY4_7 -// Description : Bits 127:112 of OTP access key 4 (ECC) -#define OTP_DATA_KEY4_7_ROW _u(0x00000f67) -#define OTP_DATA_KEY4_7_BITS _u(0x0000ffff) -#define OTP_DATA_KEY4_7_RESET "-" -#define OTP_DATA_KEY4_7_WIDTH _u(16) -#define OTP_DATA_KEY4_7_MSB _u(15) -#define OTP_DATA_KEY4_7_LSB _u(0) -#define OTP_DATA_KEY4_7_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_KEY5_0 -// Description : Bits 15:0 of OTP access key 5 (ECC) -#define OTP_DATA_KEY5_0_ROW _u(0x00000f68) -#define OTP_DATA_KEY5_0_BITS _u(0x0000ffff) -#define OTP_DATA_KEY5_0_RESET "-" -#define OTP_DATA_KEY5_0_WIDTH _u(16) -#define OTP_DATA_KEY5_0_MSB _u(15) -#define OTP_DATA_KEY5_0_LSB _u(0) -#define OTP_DATA_KEY5_0_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_KEY5_1 -// Description : Bits 31:16 of OTP access key 5 (ECC) -#define OTP_DATA_KEY5_1_ROW _u(0x00000f69) -#define OTP_DATA_KEY5_1_BITS _u(0x0000ffff) -#define OTP_DATA_KEY5_1_RESET "-" -#define OTP_DATA_KEY5_1_WIDTH _u(16) -#define OTP_DATA_KEY5_1_MSB _u(15) -#define OTP_DATA_KEY5_1_LSB _u(0) -#define OTP_DATA_KEY5_1_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_KEY5_2 -// Description : Bits 47:32 of OTP access key 5 (ECC) -#define OTP_DATA_KEY5_2_ROW _u(0x00000f6a) -#define OTP_DATA_KEY5_2_BITS _u(0x0000ffff) -#define OTP_DATA_KEY5_2_RESET "-" -#define OTP_DATA_KEY5_2_WIDTH _u(16) -#define OTP_DATA_KEY5_2_MSB _u(15) -#define OTP_DATA_KEY5_2_LSB _u(0) -#define OTP_DATA_KEY5_2_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_KEY5_3 -// Description : Bits 63:48 of OTP access key 5 (ECC) -#define OTP_DATA_KEY5_3_ROW _u(0x00000f6b) -#define OTP_DATA_KEY5_3_BITS _u(0x0000ffff) -#define OTP_DATA_KEY5_3_RESET "-" -#define OTP_DATA_KEY5_3_WIDTH _u(16) -#define OTP_DATA_KEY5_3_MSB _u(15) -#define OTP_DATA_KEY5_3_LSB _u(0) -#define OTP_DATA_KEY5_3_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_KEY5_4 -// Description : Bits 79:64 of OTP access key 5 (ECC) -#define OTP_DATA_KEY5_4_ROW _u(0x00000f6c) -#define OTP_DATA_KEY5_4_BITS _u(0x0000ffff) -#define OTP_DATA_KEY5_4_RESET "-" -#define OTP_DATA_KEY5_4_WIDTH _u(16) -#define OTP_DATA_KEY5_4_MSB _u(15) -#define OTP_DATA_KEY5_4_LSB _u(0) -#define OTP_DATA_KEY5_4_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_KEY5_5 -// Description : Bits 95:80 of OTP access key 5 (ECC) -#define OTP_DATA_KEY5_5_ROW _u(0x00000f6d) -#define OTP_DATA_KEY5_5_BITS _u(0x0000ffff) -#define OTP_DATA_KEY5_5_RESET "-" -#define OTP_DATA_KEY5_5_WIDTH _u(16) -#define OTP_DATA_KEY5_5_MSB _u(15) -#define OTP_DATA_KEY5_5_LSB _u(0) -#define OTP_DATA_KEY5_5_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_KEY5_6 -// Description : Bits 111:96 of OTP access key 5 (ECC) -#define OTP_DATA_KEY5_6_ROW _u(0x00000f6e) -#define OTP_DATA_KEY5_6_BITS _u(0x0000ffff) -#define OTP_DATA_KEY5_6_RESET "-" -#define OTP_DATA_KEY5_6_WIDTH _u(16) -#define OTP_DATA_KEY5_6_MSB _u(15) -#define OTP_DATA_KEY5_6_LSB _u(0) -#define OTP_DATA_KEY5_6_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_KEY5_7 -// Description : Bits 127:112 of OTP access key 5 (ECC) -#define OTP_DATA_KEY5_7_ROW _u(0x00000f6f) -#define OTP_DATA_KEY5_7_BITS _u(0x0000ffff) -#define OTP_DATA_KEY5_7_RESET "-" -#define OTP_DATA_KEY5_7_WIDTH _u(16) -#define OTP_DATA_KEY5_7_MSB _u(15) -#define OTP_DATA_KEY5_7_LSB _u(0) -#define OTP_DATA_KEY5_7_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_KEY6_0 -// Description : Bits 15:0 of OTP access key 6 (ECC) -#define OTP_DATA_KEY6_0_ROW _u(0x00000f70) -#define OTP_DATA_KEY6_0_BITS _u(0x0000ffff) -#define OTP_DATA_KEY6_0_RESET "-" -#define OTP_DATA_KEY6_0_WIDTH _u(16) -#define OTP_DATA_KEY6_0_MSB _u(15) -#define OTP_DATA_KEY6_0_LSB _u(0) -#define OTP_DATA_KEY6_0_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_KEY6_1 -// Description : Bits 31:16 of OTP access key 6 (ECC) -#define OTP_DATA_KEY6_1_ROW _u(0x00000f71) -#define OTP_DATA_KEY6_1_BITS _u(0x0000ffff) -#define OTP_DATA_KEY6_1_RESET "-" -#define OTP_DATA_KEY6_1_WIDTH _u(16) -#define OTP_DATA_KEY6_1_MSB _u(15) -#define OTP_DATA_KEY6_1_LSB _u(0) -#define OTP_DATA_KEY6_1_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_KEY6_2 -// Description : Bits 47:32 of OTP access key 6 (ECC) -#define OTP_DATA_KEY6_2_ROW _u(0x00000f72) -#define OTP_DATA_KEY6_2_BITS _u(0x0000ffff) -#define OTP_DATA_KEY6_2_RESET "-" -#define OTP_DATA_KEY6_2_WIDTH _u(16) -#define OTP_DATA_KEY6_2_MSB _u(15) -#define OTP_DATA_KEY6_2_LSB _u(0) -#define OTP_DATA_KEY6_2_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_KEY6_3 -// Description : Bits 63:48 of OTP access key 6 (ECC) -#define OTP_DATA_KEY6_3_ROW _u(0x00000f73) -#define OTP_DATA_KEY6_3_BITS _u(0x0000ffff) -#define OTP_DATA_KEY6_3_RESET "-" -#define OTP_DATA_KEY6_3_WIDTH _u(16) -#define OTP_DATA_KEY6_3_MSB _u(15) -#define OTP_DATA_KEY6_3_LSB _u(0) -#define OTP_DATA_KEY6_3_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_KEY6_4 -// Description : Bits 79:64 of OTP access key 6 (ECC) -#define OTP_DATA_KEY6_4_ROW _u(0x00000f74) -#define OTP_DATA_KEY6_4_BITS _u(0x0000ffff) -#define OTP_DATA_KEY6_4_RESET "-" -#define OTP_DATA_KEY6_4_WIDTH _u(16) -#define OTP_DATA_KEY6_4_MSB _u(15) -#define OTP_DATA_KEY6_4_LSB _u(0) -#define OTP_DATA_KEY6_4_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_KEY6_5 -// Description : Bits 95:80 of OTP access key 6 (ECC) -#define OTP_DATA_KEY6_5_ROW _u(0x00000f75) -#define OTP_DATA_KEY6_5_BITS _u(0x0000ffff) -#define OTP_DATA_KEY6_5_RESET "-" -#define OTP_DATA_KEY6_5_WIDTH _u(16) -#define OTP_DATA_KEY6_5_MSB _u(15) -#define OTP_DATA_KEY6_5_LSB _u(0) -#define OTP_DATA_KEY6_5_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_KEY6_6 -// Description : Bits 111:96 of OTP access key 6 (ECC) -#define OTP_DATA_KEY6_6_ROW _u(0x00000f76) -#define OTP_DATA_KEY6_6_BITS _u(0x0000ffff) -#define OTP_DATA_KEY6_6_RESET "-" -#define OTP_DATA_KEY6_6_WIDTH _u(16) -#define OTP_DATA_KEY6_6_MSB _u(15) -#define OTP_DATA_KEY6_6_LSB _u(0) -#define OTP_DATA_KEY6_6_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_KEY6_7 -// Description : Bits 127:112 of OTP access key 6 (ECC) -#define OTP_DATA_KEY6_7_ROW _u(0x00000f77) -#define OTP_DATA_KEY6_7_BITS _u(0x0000ffff) -#define OTP_DATA_KEY6_7_RESET "-" -#define OTP_DATA_KEY6_7_WIDTH _u(16) -#define OTP_DATA_KEY6_7_MSB _u(15) -#define OTP_DATA_KEY6_7_LSB _u(0) -#define OTP_DATA_KEY6_7_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_KEY1_VALID -// Description : Valid flag for key 1. Once the valid flag is set, the key can -// no longer be read or written, and becomes a valid fixed key for -// protecting OTP pages. -#define OTP_DATA_KEY1_VALID_ROW _u(0x00000f79) -#define OTP_DATA_KEY1_VALID_BITS _u(0x00010101) -#define OTP_DATA_KEY1_VALID_RESET _u(0x00000000) -#define OTP_DATA_KEY1_VALID_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_KEY1_VALID_VALID_R2 -// Description : Redundant copy of VALID, with 3-way majority vote -#define OTP_DATA_KEY1_VALID_VALID_R2_RESET "-" -#define OTP_DATA_KEY1_VALID_VALID_R2_BITS _u(0x00010000) -#define OTP_DATA_KEY1_VALID_VALID_R2_MSB _u(16) -#define OTP_DATA_KEY1_VALID_VALID_R2_LSB _u(16) -#define OTP_DATA_KEY1_VALID_VALID_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_KEY1_VALID_VALID_R1 -// Description : Redundant copy of VALID, with 3-way majority vote -#define OTP_DATA_KEY1_VALID_VALID_R1_RESET "-" -#define OTP_DATA_KEY1_VALID_VALID_R1_BITS _u(0x00000100) -#define OTP_DATA_KEY1_VALID_VALID_R1_MSB _u(8) -#define OTP_DATA_KEY1_VALID_VALID_R1_LSB _u(8) -#define OTP_DATA_KEY1_VALID_VALID_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_KEY1_VALID_VALID -#define OTP_DATA_KEY1_VALID_VALID_RESET "-" -#define OTP_DATA_KEY1_VALID_VALID_BITS _u(0x00000001) -#define OTP_DATA_KEY1_VALID_VALID_MSB _u(0) -#define OTP_DATA_KEY1_VALID_VALID_LSB _u(0) -#define OTP_DATA_KEY1_VALID_VALID_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_KEY2_VALID -// Description : Valid flag for key 2. Once the valid flag is set, the key can -// no longer be read or written, and becomes a valid fixed key for -// protecting OTP pages. -#define OTP_DATA_KEY2_VALID_ROW _u(0x00000f7a) -#define OTP_DATA_KEY2_VALID_BITS _u(0x00010101) -#define OTP_DATA_KEY2_VALID_RESET _u(0x00000000) -#define OTP_DATA_KEY2_VALID_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_KEY2_VALID_VALID_R2 -// Description : Redundant copy of VALID, with 3-way majority vote -#define OTP_DATA_KEY2_VALID_VALID_R2_RESET "-" -#define OTP_DATA_KEY2_VALID_VALID_R2_BITS _u(0x00010000) -#define OTP_DATA_KEY2_VALID_VALID_R2_MSB _u(16) -#define OTP_DATA_KEY2_VALID_VALID_R2_LSB _u(16) -#define OTP_DATA_KEY2_VALID_VALID_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_KEY2_VALID_VALID_R1 -// Description : Redundant copy of VALID, with 3-way majority vote -#define OTP_DATA_KEY2_VALID_VALID_R1_RESET "-" -#define OTP_DATA_KEY2_VALID_VALID_R1_BITS _u(0x00000100) -#define OTP_DATA_KEY2_VALID_VALID_R1_MSB _u(8) -#define OTP_DATA_KEY2_VALID_VALID_R1_LSB _u(8) -#define OTP_DATA_KEY2_VALID_VALID_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_KEY2_VALID_VALID -#define OTP_DATA_KEY2_VALID_VALID_RESET "-" -#define OTP_DATA_KEY2_VALID_VALID_BITS _u(0x00000001) -#define OTP_DATA_KEY2_VALID_VALID_MSB _u(0) -#define OTP_DATA_KEY2_VALID_VALID_LSB _u(0) -#define OTP_DATA_KEY2_VALID_VALID_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_KEY3_VALID -// Description : Valid flag for key 3. Once the valid flag is set, the key can -// no longer be read or written, and becomes a valid fixed key for -// protecting OTP pages. -#define OTP_DATA_KEY3_VALID_ROW _u(0x00000f7b) -#define OTP_DATA_KEY3_VALID_BITS _u(0x00010101) -#define OTP_DATA_KEY3_VALID_RESET _u(0x00000000) -#define OTP_DATA_KEY3_VALID_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_KEY3_VALID_VALID_R2 -// Description : Redundant copy of VALID, with 3-way majority vote -#define OTP_DATA_KEY3_VALID_VALID_R2_RESET "-" -#define OTP_DATA_KEY3_VALID_VALID_R2_BITS _u(0x00010000) -#define OTP_DATA_KEY3_VALID_VALID_R2_MSB _u(16) -#define OTP_DATA_KEY3_VALID_VALID_R2_LSB _u(16) -#define OTP_DATA_KEY3_VALID_VALID_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_KEY3_VALID_VALID_R1 -// Description : Redundant copy of VALID, with 3-way majority vote -#define OTP_DATA_KEY3_VALID_VALID_R1_RESET "-" -#define OTP_DATA_KEY3_VALID_VALID_R1_BITS _u(0x00000100) -#define OTP_DATA_KEY3_VALID_VALID_R1_MSB _u(8) -#define OTP_DATA_KEY3_VALID_VALID_R1_LSB _u(8) -#define OTP_DATA_KEY3_VALID_VALID_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_KEY3_VALID_VALID -#define OTP_DATA_KEY3_VALID_VALID_RESET "-" -#define OTP_DATA_KEY3_VALID_VALID_BITS _u(0x00000001) -#define OTP_DATA_KEY3_VALID_VALID_MSB _u(0) -#define OTP_DATA_KEY3_VALID_VALID_LSB _u(0) -#define OTP_DATA_KEY3_VALID_VALID_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_KEY4_VALID -// Description : Valid flag for key 4. Once the valid flag is set, the key can -// no longer be read or written, and becomes a valid fixed key for -// protecting OTP pages. -#define OTP_DATA_KEY4_VALID_ROW _u(0x00000f7c) -#define OTP_DATA_KEY4_VALID_BITS _u(0x00010101) -#define OTP_DATA_KEY4_VALID_RESET _u(0x00000000) -#define OTP_DATA_KEY4_VALID_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_KEY4_VALID_VALID_R2 -// Description : Redundant copy of VALID, with 3-way majority vote -#define OTP_DATA_KEY4_VALID_VALID_R2_RESET "-" -#define OTP_DATA_KEY4_VALID_VALID_R2_BITS _u(0x00010000) -#define OTP_DATA_KEY4_VALID_VALID_R2_MSB _u(16) -#define OTP_DATA_KEY4_VALID_VALID_R2_LSB _u(16) -#define OTP_DATA_KEY4_VALID_VALID_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_KEY4_VALID_VALID_R1 -// Description : Redundant copy of VALID, with 3-way majority vote -#define OTP_DATA_KEY4_VALID_VALID_R1_RESET "-" -#define OTP_DATA_KEY4_VALID_VALID_R1_BITS _u(0x00000100) -#define OTP_DATA_KEY4_VALID_VALID_R1_MSB _u(8) -#define OTP_DATA_KEY4_VALID_VALID_R1_LSB _u(8) -#define OTP_DATA_KEY4_VALID_VALID_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_KEY4_VALID_VALID -#define OTP_DATA_KEY4_VALID_VALID_RESET "-" -#define OTP_DATA_KEY4_VALID_VALID_BITS _u(0x00000001) -#define OTP_DATA_KEY4_VALID_VALID_MSB _u(0) -#define OTP_DATA_KEY4_VALID_VALID_LSB _u(0) -#define OTP_DATA_KEY4_VALID_VALID_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_KEY5_VALID -// Description : Valid flag for key 5. Once the valid flag is set, the key can -// no longer be read or written, and becomes a valid fixed key for -// protecting OTP pages. -#define OTP_DATA_KEY5_VALID_ROW _u(0x00000f7d) -#define OTP_DATA_KEY5_VALID_BITS _u(0x00010101) -#define OTP_DATA_KEY5_VALID_RESET _u(0x00000000) -#define OTP_DATA_KEY5_VALID_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_KEY5_VALID_VALID_R2 -// Description : Redundant copy of VALID, with 3-way majority vote -#define OTP_DATA_KEY5_VALID_VALID_R2_RESET "-" -#define OTP_DATA_KEY5_VALID_VALID_R2_BITS _u(0x00010000) -#define OTP_DATA_KEY5_VALID_VALID_R2_MSB _u(16) -#define OTP_DATA_KEY5_VALID_VALID_R2_LSB _u(16) -#define OTP_DATA_KEY5_VALID_VALID_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_KEY5_VALID_VALID_R1 -// Description : Redundant copy of VALID, with 3-way majority vote -#define OTP_DATA_KEY5_VALID_VALID_R1_RESET "-" -#define OTP_DATA_KEY5_VALID_VALID_R1_BITS _u(0x00000100) -#define OTP_DATA_KEY5_VALID_VALID_R1_MSB _u(8) -#define OTP_DATA_KEY5_VALID_VALID_R1_LSB _u(8) -#define OTP_DATA_KEY5_VALID_VALID_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_KEY5_VALID_VALID -#define OTP_DATA_KEY5_VALID_VALID_RESET "-" -#define OTP_DATA_KEY5_VALID_VALID_BITS _u(0x00000001) -#define OTP_DATA_KEY5_VALID_VALID_MSB _u(0) -#define OTP_DATA_KEY5_VALID_VALID_LSB _u(0) -#define OTP_DATA_KEY5_VALID_VALID_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_KEY6_VALID -// Description : Valid flag for key 6. Once the valid flag is set, the key can -// no longer be read or written, and becomes a valid fixed key for -// protecting OTP pages. -#define OTP_DATA_KEY6_VALID_ROW _u(0x00000f7e) -#define OTP_DATA_KEY6_VALID_BITS _u(0x00010101) -#define OTP_DATA_KEY6_VALID_RESET _u(0x00000000) -#define OTP_DATA_KEY6_VALID_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_KEY6_VALID_VALID_R2 -// Description : Redundant copy of VALID, with 3-way majority vote -#define OTP_DATA_KEY6_VALID_VALID_R2_RESET "-" -#define OTP_DATA_KEY6_VALID_VALID_R2_BITS _u(0x00010000) -#define OTP_DATA_KEY6_VALID_VALID_R2_MSB _u(16) -#define OTP_DATA_KEY6_VALID_VALID_R2_LSB _u(16) -#define OTP_DATA_KEY6_VALID_VALID_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_KEY6_VALID_VALID_R1 -// Description : Redundant copy of VALID, with 3-way majority vote -#define OTP_DATA_KEY6_VALID_VALID_R1_RESET "-" -#define OTP_DATA_KEY6_VALID_VALID_R1_BITS _u(0x00000100) -#define OTP_DATA_KEY6_VALID_VALID_R1_MSB _u(8) -#define OTP_DATA_KEY6_VALID_VALID_R1_LSB _u(8) -#define OTP_DATA_KEY6_VALID_VALID_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_KEY6_VALID_VALID -#define OTP_DATA_KEY6_VALID_VALID_RESET "-" -#define OTP_DATA_KEY6_VALID_VALID_BITS _u(0x00000001) -#define OTP_DATA_KEY6_VALID_VALID_MSB _u(0) -#define OTP_DATA_KEY6_VALID_VALID_LSB _u(0) -#define OTP_DATA_KEY6_VALID_VALID_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_PAGE0_LOCK0 -// Description : Lock configuration LSBs for page 0 (rows 0x0 through 0x3f). -// Locks are stored with 3-way majority vote encoding, so that -// bits can be set independently. -// -// This OTP location is always readable, and is write-protected by -// its own permissions. -#define OTP_DATA_PAGE0_LOCK0_ROW _u(0x00000f80) -#define OTP_DATA_PAGE0_LOCK0_BITS _u(0x00ffff7f) -#define OTP_DATA_PAGE0_LOCK0_RESET _u(0x00000000) -#define OTP_DATA_PAGE0_LOCK0_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE0_LOCK0_R2 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE0_LOCK0_R2_RESET "-" -#define OTP_DATA_PAGE0_LOCK0_R2_BITS _u(0x00ff0000) -#define OTP_DATA_PAGE0_LOCK0_R2_MSB _u(23) -#define OTP_DATA_PAGE0_LOCK0_R2_LSB _u(16) -#define OTP_DATA_PAGE0_LOCK0_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE0_LOCK0_R1 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE0_LOCK0_R1_RESET "-" -#define OTP_DATA_PAGE0_LOCK0_R1_BITS _u(0x0000ff00) -#define OTP_DATA_PAGE0_LOCK0_R1_MSB _u(15) -#define OTP_DATA_PAGE0_LOCK0_R1_LSB _u(8) -#define OTP_DATA_PAGE0_LOCK0_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE0_LOCK0_NO_KEY_STATE -// Description : State when at least one key is registered for this page and no -// matching key has been entered. -// 0x0 -> read_only -// 0x1 -> inaccessible -#define OTP_DATA_PAGE0_LOCK0_NO_KEY_STATE_RESET "-" -#define OTP_DATA_PAGE0_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) -#define OTP_DATA_PAGE0_LOCK0_NO_KEY_STATE_MSB _u(6) -#define OTP_DATA_PAGE0_LOCK0_NO_KEY_STATE_LSB _u(6) -#define OTP_DATA_PAGE0_LOCK0_NO_KEY_STATE_ACCESS "RO" -#define OTP_DATA_PAGE0_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) -#define OTP_DATA_PAGE0_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE0_LOCK0_KEY_R -// Description : Index 1-6 of a hardware key which must be entered to grant read -// access, or 0 if no such key is required. -#define OTP_DATA_PAGE0_LOCK0_KEY_R_RESET "-" -#define OTP_DATA_PAGE0_LOCK0_KEY_R_BITS _u(0x00000038) -#define OTP_DATA_PAGE0_LOCK0_KEY_R_MSB _u(5) -#define OTP_DATA_PAGE0_LOCK0_KEY_R_LSB _u(3) -#define OTP_DATA_PAGE0_LOCK0_KEY_R_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE0_LOCK0_KEY_W -// Description : Index 1-6 of a hardware key which must be entered to grant -// write access, or 0 if no such key is required. -#define OTP_DATA_PAGE0_LOCK0_KEY_W_RESET "-" -#define OTP_DATA_PAGE0_LOCK0_KEY_W_BITS _u(0x00000007) -#define OTP_DATA_PAGE0_LOCK0_KEY_W_MSB _u(2) -#define OTP_DATA_PAGE0_LOCK0_KEY_W_LSB _u(0) -#define OTP_DATA_PAGE0_LOCK0_KEY_W_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_PAGE0_LOCK1 -// Description : Lock configuration MSBs for page 0 (rows 0x0 through 0x3f). -// Locks are stored with 3-way majority vote encoding, so that -// bits can be set independently. -// -// This OTP location is always readable, and is write-protected by -// its own permissions. -#define OTP_DATA_PAGE0_LOCK1_ROW _u(0x00000f81) -#define OTP_DATA_PAGE0_LOCK1_BITS _u(0x00ffff3f) -#define OTP_DATA_PAGE0_LOCK1_RESET _u(0x00000000) -#define OTP_DATA_PAGE0_LOCK1_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE0_LOCK1_R2 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE0_LOCK1_R2_RESET "-" -#define OTP_DATA_PAGE0_LOCK1_R2_BITS _u(0x00ff0000) -#define OTP_DATA_PAGE0_LOCK1_R2_MSB _u(23) -#define OTP_DATA_PAGE0_LOCK1_R2_LSB _u(16) -#define OTP_DATA_PAGE0_LOCK1_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE0_LOCK1_R1 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE0_LOCK1_R1_RESET "-" -#define OTP_DATA_PAGE0_LOCK1_R1_BITS _u(0x0000ff00) -#define OTP_DATA_PAGE0_LOCK1_R1_MSB _u(15) -#define OTP_DATA_PAGE0_LOCK1_R1_LSB _u(8) -#define OTP_DATA_PAGE0_LOCK1_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE0_LOCK1_LOCK_BL -// Description : Dummy lock bits reserved for bootloaders (including the RP2350 -// USB bootloader) to store their own OTP access permissions. No -// hardware effect, and no corresponding SW_LOCKx registers. -// 0x0 -> Bootloader permits user reads and writes to this page -// 0x1 -> Bootloader permits user reads of this page -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE -// 0x3 -> Bootloader does not permit user access to this page -#define OTP_DATA_PAGE0_LOCK1_LOCK_BL_RESET "-" -#define OTP_DATA_PAGE0_LOCK1_LOCK_BL_BITS _u(0x00000030) -#define OTP_DATA_PAGE0_LOCK1_LOCK_BL_MSB _u(5) -#define OTP_DATA_PAGE0_LOCK1_LOCK_BL_LSB _u(4) -#define OTP_DATA_PAGE0_LOCK1_LOCK_BL_ACCESS "RO" -#define OTP_DATA_PAGE0_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE0_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE0_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE0_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE0_LOCK1_LOCK_NS -// Description : Lock state for Non-secure accesses to this page. Thermometer- -// coded, so lock state can be advanced permanently from any state -// to any less-permissive state by programming OTP. Software can -// also advance the lock state temporarily (until next OTP reset) -// using the SW_LOCKx registers. -// -// Note that READ_WRITE and READ_ONLY are equivalent in hardware, -// as the SBPI programming interface is not accessible to Non- -// secure software. However, Secure software may check these bits -// to apply write permissions to a Non-secure OTP programming API. -// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. -// 0x1 -> Page can be read by Non-secure software -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. -// 0x3 -> Page can not be accessed by Non-secure software. -#define OTP_DATA_PAGE0_LOCK1_LOCK_NS_RESET "-" -#define OTP_DATA_PAGE0_LOCK1_LOCK_NS_BITS _u(0x0000000c) -#define OTP_DATA_PAGE0_LOCK1_LOCK_NS_MSB _u(3) -#define OTP_DATA_PAGE0_LOCK1_LOCK_NS_LSB _u(2) -#define OTP_DATA_PAGE0_LOCK1_LOCK_NS_ACCESS "RO" -#define OTP_DATA_PAGE0_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE0_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE0_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE0_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE0_LOCK1_LOCK_S -// Description : Lock state for Secure accesses to this page. Thermometer-coded, -// so lock state can be advanced permanently from any state to any -// less-permissive state by programming OTP. Software can also -// advance the lock state temporarily (until next OTP reset) using -// the SW_LOCKx registers. -// 0x0 -> Page is fully accessible by Secure software. -// 0x1 -> Page can be read by Secure software, but can not be written. -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. -// 0x3 -> Page can not be accessed by Secure software. -#define OTP_DATA_PAGE0_LOCK1_LOCK_S_RESET "-" -#define OTP_DATA_PAGE0_LOCK1_LOCK_S_BITS _u(0x00000003) -#define OTP_DATA_PAGE0_LOCK1_LOCK_S_MSB _u(1) -#define OTP_DATA_PAGE0_LOCK1_LOCK_S_LSB _u(0) -#define OTP_DATA_PAGE0_LOCK1_LOCK_S_ACCESS "RO" -#define OTP_DATA_PAGE0_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE0_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE0_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE0_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) -// ============================================================================= -// Register : OTP_DATA_PAGE1_LOCK0 -// Description : Lock configuration LSBs for page 1 (rows 0x40 through 0x7f). -// Locks are stored with 3-way majority vote encoding, so that -// bits can be set independently. -// -// This OTP location is always readable, and is write-protected by -// its own permissions. -#define OTP_DATA_PAGE1_LOCK0_ROW _u(0x00000f82) -#define OTP_DATA_PAGE1_LOCK0_BITS _u(0x00ffff7f) -#define OTP_DATA_PAGE1_LOCK0_RESET _u(0x00000000) -#define OTP_DATA_PAGE1_LOCK0_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE1_LOCK0_R2 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE1_LOCK0_R2_RESET "-" -#define OTP_DATA_PAGE1_LOCK0_R2_BITS _u(0x00ff0000) -#define OTP_DATA_PAGE1_LOCK0_R2_MSB _u(23) -#define OTP_DATA_PAGE1_LOCK0_R2_LSB _u(16) -#define OTP_DATA_PAGE1_LOCK0_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE1_LOCK0_R1 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE1_LOCK0_R1_RESET "-" -#define OTP_DATA_PAGE1_LOCK0_R1_BITS _u(0x0000ff00) -#define OTP_DATA_PAGE1_LOCK0_R1_MSB _u(15) -#define OTP_DATA_PAGE1_LOCK0_R1_LSB _u(8) -#define OTP_DATA_PAGE1_LOCK0_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE1_LOCK0_NO_KEY_STATE -// Description : State when at least one key is registered for this page and no -// matching key has been entered. -// 0x0 -> read_only -// 0x1 -> inaccessible -#define OTP_DATA_PAGE1_LOCK0_NO_KEY_STATE_RESET "-" -#define OTP_DATA_PAGE1_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) -#define OTP_DATA_PAGE1_LOCK0_NO_KEY_STATE_MSB _u(6) -#define OTP_DATA_PAGE1_LOCK0_NO_KEY_STATE_LSB _u(6) -#define OTP_DATA_PAGE1_LOCK0_NO_KEY_STATE_ACCESS "RO" -#define OTP_DATA_PAGE1_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) -#define OTP_DATA_PAGE1_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE1_LOCK0_KEY_R -// Description : Index 1-6 of a hardware key which must be entered to grant read -// access, or 0 if no such key is required. -#define OTP_DATA_PAGE1_LOCK0_KEY_R_RESET "-" -#define OTP_DATA_PAGE1_LOCK0_KEY_R_BITS _u(0x00000038) -#define OTP_DATA_PAGE1_LOCK0_KEY_R_MSB _u(5) -#define OTP_DATA_PAGE1_LOCK0_KEY_R_LSB _u(3) -#define OTP_DATA_PAGE1_LOCK0_KEY_R_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE1_LOCK0_KEY_W -// Description : Index 1-6 of a hardware key which must be entered to grant -// write access, or 0 if no such key is required. -#define OTP_DATA_PAGE1_LOCK0_KEY_W_RESET "-" -#define OTP_DATA_PAGE1_LOCK0_KEY_W_BITS _u(0x00000007) -#define OTP_DATA_PAGE1_LOCK0_KEY_W_MSB _u(2) -#define OTP_DATA_PAGE1_LOCK0_KEY_W_LSB _u(0) -#define OTP_DATA_PAGE1_LOCK0_KEY_W_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_PAGE1_LOCK1 -// Description : Lock configuration MSBs for page 1 (rows 0x40 through 0x7f). -// Locks are stored with 3-way majority vote encoding, so that -// bits can be set independently. -// -// This OTP location is always readable, and is write-protected by -// its own permissions. -#define OTP_DATA_PAGE1_LOCK1_ROW _u(0x00000f83) -#define OTP_DATA_PAGE1_LOCK1_BITS _u(0x00ffff3f) -#define OTP_DATA_PAGE1_LOCK1_RESET _u(0x00000000) -#define OTP_DATA_PAGE1_LOCK1_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE1_LOCK1_R2 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE1_LOCK1_R2_RESET "-" -#define OTP_DATA_PAGE1_LOCK1_R2_BITS _u(0x00ff0000) -#define OTP_DATA_PAGE1_LOCK1_R2_MSB _u(23) -#define OTP_DATA_PAGE1_LOCK1_R2_LSB _u(16) -#define OTP_DATA_PAGE1_LOCK1_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE1_LOCK1_R1 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE1_LOCK1_R1_RESET "-" -#define OTP_DATA_PAGE1_LOCK1_R1_BITS _u(0x0000ff00) -#define OTP_DATA_PAGE1_LOCK1_R1_MSB _u(15) -#define OTP_DATA_PAGE1_LOCK1_R1_LSB _u(8) -#define OTP_DATA_PAGE1_LOCK1_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE1_LOCK1_LOCK_BL -// Description : Dummy lock bits reserved for bootloaders (including the RP2350 -// USB bootloader) to store their own OTP access permissions. No -// hardware effect, and no corresponding SW_LOCKx registers. -// 0x0 -> Bootloader permits user reads and writes to this page -// 0x1 -> Bootloader permits user reads of this page -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE -// 0x3 -> Bootloader does not permit user access to this page -#define OTP_DATA_PAGE1_LOCK1_LOCK_BL_RESET "-" -#define OTP_DATA_PAGE1_LOCK1_LOCK_BL_BITS _u(0x00000030) -#define OTP_DATA_PAGE1_LOCK1_LOCK_BL_MSB _u(5) -#define OTP_DATA_PAGE1_LOCK1_LOCK_BL_LSB _u(4) -#define OTP_DATA_PAGE1_LOCK1_LOCK_BL_ACCESS "RO" -#define OTP_DATA_PAGE1_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE1_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE1_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE1_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE1_LOCK1_LOCK_NS -// Description : Lock state for Non-secure accesses to this page. Thermometer- -// coded, so lock state can be advanced permanently from any state -// to any less-permissive state by programming OTP. Software can -// also advance the lock state temporarily (until next OTP reset) -// using the SW_LOCKx registers. -// -// Note that READ_WRITE and READ_ONLY are equivalent in hardware, -// as the SBPI programming interface is not accessible to Non- -// secure software. However, Secure software may check these bits -// to apply write permissions to a Non-secure OTP programming API. -// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. -// 0x1 -> Page can be read by Non-secure software -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. -// 0x3 -> Page can not be accessed by Non-secure software. -#define OTP_DATA_PAGE1_LOCK1_LOCK_NS_RESET "-" -#define OTP_DATA_PAGE1_LOCK1_LOCK_NS_BITS _u(0x0000000c) -#define OTP_DATA_PAGE1_LOCK1_LOCK_NS_MSB _u(3) -#define OTP_DATA_PAGE1_LOCK1_LOCK_NS_LSB _u(2) -#define OTP_DATA_PAGE1_LOCK1_LOCK_NS_ACCESS "RO" -#define OTP_DATA_PAGE1_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE1_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE1_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE1_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE1_LOCK1_LOCK_S -// Description : Lock state for Secure accesses to this page. Thermometer-coded, -// so lock state can be advanced permanently from any state to any -// less-permissive state by programming OTP. Software can also -// advance the lock state temporarily (until next OTP reset) using -// the SW_LOCKx registers. -// 0x0 -> Page is fully accessible by Secure software. -// 0x1 -> Page can be read by Secure software, but can not be written. -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. -// 0x3 -> Page can not be accessed by Secure software. -#define OTP_DATA_PAGE1_LOCK1_LOCK_S_RESET "-" -#define OTP_DATA_PAGE1_LOCK1_LOCK_S_BITS _u(0x00000003) -#define OTP_DATA_PAGE1_LOCK1_LOCK_S_MSB _u(1) -#define OTP_DATA_PAGE1_LOCK1_LOCK_S_LSB _u(0) -#define OTP_DATA_PAGE1_LOCK1_LOCK_S_ACCESS "RO" -#define OTP_DATA_PAGE1_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE1_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE1_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE1_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) -// ============================================================================= -// Register : OTP_DATA_PAGE2_LOCK0 -// Description : Lock configuration LSBs for page 2 (rows 0x80 through 0xbf). -// Locks are stored with 3-way majority vote encoding, so that -// bits can be set independently. -// -// This OTP location is always readable, and is write-protected by -// its own permissions. -#define OTP_DATA_PAGE2_LOCK0_ROW _u(0x00000f84) -#define OTP_DATA_PAGE2_LOCK0_BITS _u(0x00ffff7f) -#define OTP_DATA_PAGE2_LOCK0_RESET _u(0x00000000) -#define OTP_DATA_PAGE2_LOCK0_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE2_LOCK0_R2 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE2_LOCK0_R2_RESET "-" -#define OTP_DATA_PAGE2_LOCK0_R2_BITS _u(0x00ff0000) -#define OTP_DATA_PAGE2_LOCK0_R2_MSB _u(23) -#define OTP_DATA_PAGE2_LOCK0_R2_LSB _u(16) -#define OTP_DATA_PAGE2_LOCK0_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE2_LOCK0_R1 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE2_LOCK0_R1_RESET "-" -#define OTP_DATA_PAGE2_LOCK0_R1_BITS _u(0x0000ff00) -#define OTP_DATA_PAGE2_LOCK0_R1_MSB _u(15) -#define OTP_DATA_PAGE2_LOCK0_R1_LSB _u(8) -#define OTP_DATA_PAGE2_LOCK0_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE2_LOCK0_NO_KEY_STATE -// Description : State when at least one key is registered for this page and no -// matching key has been entered. -// 0x0 -> read_only -// 0x1 -> inaccessible -#define OTP_DATA_PAGE2_LOCK0_NO_KEY_STATE_RESET "-" -#define OTP_DATA_PAGE2_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) -#define OTP_DATA_PAGE2_LOCK0_NO_KEY_STATE_MSB _u(6) -#define OTP_DATA_PAGE2_LOCK0_NO_KEY_STATE_LSB _u(6) -#define OTP_DATA_PAGE2_LOCK0_NO_KEY_STATE_ACCESS "RO" -#define OTP_DATA_PAGE2_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) -#define OTP_DATA_PAGE2_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE2_LOCK0_KEY_R -// Description : Index 1-6 of a hardware key which must be entered to grant read -// access, or 0 if no such key is required. -#define OTP_DATA_PAGE2_LOCK0_KEY_R_RESET "-" -#define OTP_DATA_PAGE2_LOCK0_KEY_R_BITS _u(0x00000038) -#define OTP_DATA_PAGE2_LOCK0_KEY_R_MSB _u(5) -#define OTP_DATA_PAGE2_LOCK0_KEY_R_LSB _u(3) -#define OTP_DATA_PAGE2_LOCK0_KEY_R_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE2_LOCK0_KEY_W -// Description : Index 1-6 of a hardware key which must be entered to grant -// write access, or 0 if no such key is required. -#define OTP_DATA_PAGE2_LOCK0_KEY_W_RESET "-" -#define OTP_DATA_PAGE2_LOCK0_KEY_W_BITS _u(0x00000007) -#define OTP_DATA_PAGE2_LOCK0_KEY_W_MSB _u(2) -#define OTP_DATA_PAGE2_LOCK0_KEY_W_LSB _u(0) -#define OTP_DATA_PAGE2_LOCK0_KEY_W_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_PAGE2_LOCK1 -// Description : Lock configuration MSBs for page 2 (rows 0x80 through 0xbf). -// Locks are stored with 3-way majority vote encoding, so that -// bits can be set independently. -// -// This OTP location is always readable, and is write-protected by -// its own permissions. -#define OTP_DATA_PAGE2_LOCK1_ROW _u(0x00000f85) -#define OTP_DATA_PAGE2_LOCK1_BITS _u(0x00ffff3f) -#define OTP_DATA_PAGE2_LOCK1_RESET _u(0x00000000) -#define OTP_DATA_PAGE2_LOCK1_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE2_LOCK1_R2 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE2_LOCK1_R2_RESET "-" -#define OTP_DATA_PAGE2_LOCK1_R2_BITS _u(0x00ff0000) -#define OTP_DATA_PAGE2_LOCK1_R2_MSB _u(23) -#define OTP_DATA_PAGE2_LOCK1_R2_LSB _u(16) -#define OTP_DATA_PAGE2_LOCK1_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE2_LOCK1_R1 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE2_LOCK1_R1_RESET "-" -#define OTP_DATA_PAGE2_LOCK1_R1_BITS _u(0x0000ff00) -#define OTP_DATA_PAGE2_LOCK1_R1_MSB _u(15) -#define OTP_DATA_PAGE2_LOCK1_R1_LSB _u(8) -#define OTP_DATA_PAGE2_LOCK1_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE2_LOCK1_LOCK_BL -// Description : Dummy lock bits reserved for bootloaders (including the RP2350 -// USB bootloader) to store their own OTP access permissions. No -// hardware effect, and no corresponding SW_LOCKx registers. -// 0x0 -> Bootloader permits user reads and writes to this page -// 0x1 -> Bootloader permits user reads of this page -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE -// 0x3 -> Bootloader does not permit user access to this page -#define OTP_DATA_PAGE2_LOCK1_LOCK_BL_RESET "-" -#define OTP_DATA_PAGE2_LOCK1_LOCK_BL_BITS _u(0x00000030) -#define OTP_DATA_PAGE2_LOCK1_LOCK_BL_MSB _u(5) -#define OTP_DATA_PAGE2_LOCK1_LOCK_BL_LSB _u(4) -#define OTP_DATA_PAGE2_LOCK1_LOCK_BL_ACCESS "RO" -#define OTP_DATA_PAGE2_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE2_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE2_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE2_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE2_LOCK1_LOCK_NS -// Description : Lock state for Non-secure accesses to this page. Thermometer- -// coded, so lock state can be advanced permanently from any state -// to any less-permissive state by programming OTP. Software can -// also advance the lock state temporarily (until next OTP reset) -// using the SW_LOCKx registers. -// -// Note that READ_WRITE and READ_ONLY are equivalent in hardware, -// as the SBPI programming interface is not accessible to Non- -// secure software. However, Secure software may check these bits -// to apply write permissions to a Non-secure OTP programming API. -// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. -// 0x1 -> Page can be read by Non-secure software -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. -// 0x3 -> Page can not be accessed by Non-secure software. -#define OTP_DATA_PAGE2_LOCK1_LOCK_NS_RESET "-" -#define OTP_DATA_PAGE2_LOCK1_LOCK_NS_BITS _u(0x0000000c) -#define OTP_DATA_PAGE2_LOCK1_LOCK_NS_MSB _u(3) -#define OTP_DATA_PAGE2_LOCK1_LOCK_NS_LSB _u(2) -#define OTP_DATA_PAGE2_LOCK1_LOCK_NS_ACCESS "RO" -#define OTP_DATA_PAGE2_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE2_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE2_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE2_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE2_LOCK1_LOCK_S -// Description : Lock state for Secure accesses to this page. Thermometer-coded, -// so lock state can be advanced permanently from any state to any -// less-permissive state by programming OTP. Software can also -// advance the lock state temporarily (until next OTP reset) using -// the SW_LOCKx registers. -// 0x0 -> Page is fully accessible by Secure software. -// 0x1 -> Page can be read by Secure software, but can not be written. -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. -// 0x3 -> Page can not be accessed by Secure software. -#define OTP_DATA_PAGE2_LOCK1_LOCK_S_RESET "-" -#define OTP_DATA_PAGE2_LOCK1_LOCK_S_BITS _u(0x00000003) -#define OTP_DATA_PAGE2_LOCK1_LOCK_S_MSB _u(1) -#define OTP_DATA_PAGE2_LOCK1_LOCK_S_LSB _u(0) -#define OTP_DATA_PAGE2_LOCK1_LOCK_S_ACCESS "RO" -#define OTP_DATA_PAGE2_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE2_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE2_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE2_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) -// ============================================================================= -// Register : OTP_DATA_PAGE3_LOCK0 -// Description : Lock configuration LSBs for page 3 (rows 0xc0 through 0xff). -// Locks are stored with 3-way majority vote encoding, so that -// bits can be set independently. -// -// This OTP location is always readable, and is write-protected by -// its own permissions. -#define OTP_DATA_PAGE3_LOCK0_ROW _u(0x00000f86) -#define OTP_DATA_PAGE3_LOCK0_BITS _u(0x00ffff7f) -#define OTP_DATA_PAGE3_LOCK0_RESET _u(0x00000000) -#define OTP_DATA_PAGE3_LOCK0_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE3_LOCK0_R2 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE3_LOCK0_R2_RESET "-" -#define OTP_DATA_PAGE3_LOCK0_R2_BITS _u(0x00ff0000) -#define OTP_DATA_PAGE3_LOCK0_R2_MSB _u(23) -#define OTP_DATA_PAGE3_LOCK0_R2_LSB _u(16) -#define OTP_DATA_PAGE3_LOCK0_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE3_LOCK0_R1 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE3_LOCK0_R1_RESET "-" -#define OTP_DATA_PAGE3_LOCK0_R1_BITS _u(0x0000ff00) -#define OTP_DATA_PAGE3_LOCK0_R1_MSB _u(15) -#define OTP_DATA_PAGE3_LOCK0_R1_LSB _u(8) -#define OTP_DATA_PAGE3_LOCK0_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE3_LOCK0_NO_KEY_STATE -// Description : State when at least one key is registered for this page and no -// matching key has been entered. -// 0x0 -> read_only -// 0x1 -> inaccessible -#define OTP_DATA_PAGE3_LOCK0_NO_KEY_STATE_RESET "-" -#define OTP_DATA_PAGE3_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) -#define OTP_DATA_PAGE3_LOCK0_NO_KEY_STATE_MSB _u(6) -#define OTP_DATA_PAGE3_LOCK0_NO_KEY_STATE_LSB _u(6) -#define OTP_DATA_PAGE3_LOCK0_NO_KEY_STATE_ACCESS "RO" -#define OTP_DATA_PAGE3_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) -#define OTP_DATA_PAGE3_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE3_LOCK0_KEY_R -// Description : Index 1-6 of a hardware key which must be entered to grant read -// access, or 0 if no such key is required. -#define OTP_DATA_PAGE3_LOCK0_KEY_R_RESET "-" -#define OTP_DATA_PAGE3_LOCK0_KEY_R_BITS _u(0x00000038) -#define OTP_DATA_PAGE3_LOCK0_KEY_R_MSB _u(5) -#define OTP_DATA_PAGE3_LOCK0_KEY_R_LSB _u(3) -#define OTP_DATA_PAGE3_LOCK0_KEY_R_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE3_LOCK0_KEY_W -// Description : Index 1-6 of a hardware key which must be entered to grant -// write access, or 0 if no such key is required. -#define OTP_DATA_PAGE3_LOCK0_KEY_W_RESET "-" -#define OTP_DATA_PAGE3_LOCK0_KEY_W_BITS _u(0x00000007) -#define OTP_DATA_PAGE3_LOCK0_KEY_W_MSB _u(2) -#define OTP_DATA_PAGE3_LOCK0_KEY_W_LSB _u(0) -#define OTP_DATA_PAGE3_LOCK0_KEY_W_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_PAGE3_LOCK1 -// Description : Lock configuration MSBs for page 3 (rows 0xc0 through 0xff). -// Locks are stored with 3-way majority vote encoding, so that -// bits can be set independently. -// -// This OTP location is always readable, and is write-protected by -// its own permissions. -#define OTP_DATA_PAGE3_LOCK1_ROW _u(0x00000f87) -#define OTP_DATA_PAGE3_LOCK1_BITS _u(0x00ffff3f) -#define OTP_DATA_PAGE3_LOCK1_RESET _u(0x00000000) -#define OTP_DATA_PAGE3_LOCK1_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE3_LOCK1_R2 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE3_LOCK1_R2_RESET "-" -#define OTP_DATA_PAGE3_LOCK1_R2_BITS _u(0x00ff0000) -#define OTP_DATA_PAGE3_LOCK1_R2_MSB _u(23) -#define OTP_DATA_PAGE3_LOCK1_R2_LSB _u(16) -#define OTP_DATA_PAGE3_LOCK1_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE3_LOCK1_R1 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE3_LOCK1_R1_RESET "-" -#define OTP_DATA_PAGE3_LOCK1_R1_BITS _u(0x0000ff00) -#define OTP_DATA_PAGE3_LOCK1_R1_MSB _u(15) -#define OTP_DATA_PAGE3_LOCK1_R1_LSB _u(8) -#define OTP_DATA_PAGE3_LOCK1_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE3_LOCK1_LOCK_BL -// Description : Dummy lock bits reserved for bootloaders (including the RP2350 -// USB bootloader) to store their own OTP access permissions. No -// hardware effect, and no corresponding SW_LOCKx registers. -// 0x0 -> Bootloader permits user reads and writes to this page -// 0x1 -> Bootloader permits user reads of this page -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE -// 0x3 -> Bootloader does not permit user access to this page -#define OTP_DATA_PAGE3_LOCK1_LOCK_BL_RESET "-" -#define OTP_DATA_PAGE3_LOCK1_LOCK_BL_BITS _u(0x00000030) -#define OTP_DATA_PAGE3_LOCK1_LOCK_BL_MSB _u(5) -#define OTP_DATA_PAGE3_LOCK1_LOCK_BL_LSB _u(4) -#define OTP_DATA_PAGE3_LOCK1_LOCK_BL_ACCESS "RO" -#define OTP_DATA_PAGE3_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE3_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE3_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE3_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE3_LOCK1_LOCK_NS -// Description : Lock state for Non-secure accesses to this page. Thermometer- -// coded, so lock state can be advanced permanently from any state -// to any less-permissive state by programming OTP. Software can -// also advance the lock state temporarily (until next OTP reset) -// using the SW_LOCKx registers. -// -// Note that READ_WRITE and READ_ONLY are equivalent in hardware, -// as the SBPI programming interface is not accessible to Non- -// secure software. However, Secure software may check these bits -// to apply write permissions to a Non-secure OTP programming API. -// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. -// 0x1 -> Page can be read by Non-secure software -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. -// 0x3 -> Page can not be accessed by Non-secure software. -#define OTP_DATA_PAGE3_LOCK1_LOCK_NS_RESET "-" -#define OTP_DATA_PAGE3_LOCK1_LOCK_NS_BITS _u(0x0000000c) -#define OTP_DATA_PAGE3_LOCK1_LOCK_NS_MSB _u(3) -#define OTP_DATA_PAGE3_LOCK1_LOCK_NS_LSB _u(2) -#define OTP_DATA_PAGE3_LOCK1_LOCK_NS_ACCESS "RO" -#define OTP_DATA_PAGE3_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE3_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE3_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE3_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE3_LOCK1_LOCK_S -// Description : Lock state for Secure accesses to this page. Thermometer-coded, -// so lock state can be advanced permanently from any state to any -// less-permissive state by programming OTP. Software can also -// advance the lock state temporarily (until next OTP reset) using -// the SW_LOCKx registers. -// 0x0 -> Page is fully accessible by Secure software. -// 0x1 -> Page can be read by Secure software, but can not be written. -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. -// 0x3 -> Page can not be accessed by Secure software. -#define OTP_DATA_PAGE3_LOCK1_LOCK_S_RESET "-" -#define OTP_DATA_PAGE3_LOCK1_LOCK_S_BITS _u(0x00000003) -#define OTP_DATA_PAGE3_LOCK1_LOCK_S_MSB _u(1) -#define OTP_DATA_PAGE3_LOCK1_LOCK_S_LSB _u(0) -#define OTP_DATA_PAGE3_LOCK1_LOCK_S_ACCESS "RO" -#define OTP_DATA_PAGE3_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE3_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE3_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE3_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) -// ============================================================================= -// Register : OTP_DATA_PAGE4_LOCK0 -// Description : Lock configuration LSBs for page 4 (rows 0x100 through 0x13f). -// Locks are stored with 3-way majority vote encoding, so that -// bits can be set independently. -// -// This OTP location is always readable, and is write-protected by -// its own permissions. -#define OTP_DATA_PAGE4_LOCK0_ROW _u(0x00000f88) -#define OTP_DATA_PAGE4_LOCK0_BITS _u(0x00ffff7f) -#define OTP_DATA_PAGE4_LOCK0_RESET _u(0x00000000) -#define OTP_DATA_PAGE4_LOCK0_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE4_LOCK0_R2 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE4_LOCK0_R2_RESET "-" -#define OTP_DATA_PAGE4_LOCK0_R2_BITS _u(0x00ff0000) -#define OTP_DATA_PAGE4_LOCK0_R2_MSB _u(23) -#define OTP_DATA_PAGE4_LOCK0_R2_LSB _u(16) -#define OTP_DATA_PAGE4_LOCK0_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE4_LOCK0_R1 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE4_LOCK0_R1_RESET "-" -#define OTP_DATA_PAGE4_LOCK0_R1_BITS _u(0x0000ff00) -#define OTP_DATA_PAGE4_LOCK0_R1_MSB _u(15) -#define OTP_DATA_PAGE4_LOCK0_R1_LSB _u(8) -#define OTP_DATA_PAGE4_LOCK0_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE4_LOCK0_NO_KEY_STATE -// Description : State when at least one key is registered for this page and no -// matching key has been entered. -// 0x0 -> read_only -// 0x1 -> inaccessible -#define OTP_DATA_PAGE4_LOCK0_NO_KEY_STATE_RESET "-" -#define OTP_DATA_PAGE4_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) -#define OTP_DATA_PAGE4_LOCK0_NO_KEY_STATE_MSB _u(6) -#define OTP_DATA_PAGE4_LOCK0_NO_KEY_STATE_LSB _u(6) -#define OTP_DATA_PAGE4_LOCK0_NO_KEY_STATE_ACCESS "RO" -#define OTP_DATA_PAGE4_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) -#define OTP_DATA_PAGE4_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE4_LOCK0_KEY_R -// Description : Index 1-6 of a hardware key which must be entered to grant read -// access, or 0 if no such key is required. -#define OTP_DATA_PAGE4_LOCK0_KEY_R_RESET "-" -#define OTP_DATA_PAGE4_LOCK0_KEY_R_BITS _u(0x00000038) -#define OTP_DATA_PAGE4_LOCK0_KEY_R_MSB _u(5) -#define OTP_DATA_PAGE4_LOCK0_KEY_R_LSB _u(3) -#define OTP_DATA_PAGE4_LOCK0_KEY_R_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE4_LOCK0_KEY_W -// Description : Index 1-6 of a hardware key which must be entered to grant -// write access, or 0 if no such key is required. -#define OTP_DATA_PAGE4_LOCK0_KEY_W_RESET "-" -#define OTP_DATA_PAGE4_LOCK0_KEY_W_BITS _u(0x00000007) -#define OTP_DATA_PAGE4_LOCK0_KEY_W_MSB _u(2) -#define OTP_DATA_PAGE4_LOCK0_KEY_W_LSB _u(0) -#define OTP_DATA_PAGE4_LOCK0_KEY_W_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_PAGE4_LOCK1 -// Description : Lock configuration MSBs for page 4 (rows 0x100 through 0x13f). -// Locks are stored with 3-way majority vote encoding, so that -// bits can be set independently. -// -// This OTP location is always readable, and is write-protected by -// its own permissions. -#define OTP_DATA_PAGE4_LOCK1_ROW _u(0x00000f89) -#define OTP_DATA_PAGE4_LOCK1_BITS _u(0x00ffff3f) -#define OTP_DATA_PAGE4_LOCK1_RESET _u(0x00000000) -#define OTP_DATA_PAGE4_LOCK1_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE4_LOCK1_R2 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE4_LOCK1_R2_RESET "-" -#define OTP_DATA_PAGE4_LOCK1_R2_BITS _u(0x00ff0000) -#define OTP_DATA_PAGE4_LOCK1_R2_MSB _u(23) -#define OTP_DATA_PAGE4_LOCK1_R2_LSB _u(16) -#define OTP_DATA_PAGE4_LOCK1_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE4_LOCK1_R1 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE4_LOCK1_R1_RESET "-" -#define OTP_DATA_PAGE4_LOCK1_R1_BITS _u(0x0000ff00) -#define OTP_DATA_PAGE4_LOCK1_R1_MSB _u(15) -#define OTP_DATA_PAGE4_LOCK1_R1_LSB _u(8) -#define OTP_DATA_PAGE4_LOCK1_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE4_LOCK1_LOCK_BL -// Description : Dummy lock bits reserved for bootloaders (including the RP2350 -// USB bootloader) to store their own OTP access permissions. No -// hardware effect, and no corresponding SW_LOCKx registers. -// 0x0 -> Bootloader permits user reads and writes to this page -// 0x1 -> Bootloader permits user reads of this page -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE -// 0x3 -> Bootloader does not permit user access to this page -#define OTP_DATA_PAGE4_LOCK1_LOCK_BL_RESET "-" -#define OTP_DATA_PAGE4_LOCK1_LOCK_BL_BITS _u(0x00000030) -#define OTP_DATA_PAGE4_LOCK1_LOCK_BL_MSB _u(5) -#define OTP_DATA_PAGE4_LOCK1_LOCK_BL_LSB _u(4) -#define OTP_DATA_PAGE4_LOCK1_LOCK_BL_ACCESS "RO" -#define OTP_DATA_PAGE4_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE4_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE4_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE4_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE4_LOCK1_LOCK_NS -// Description : Lock state for Non-secure accesses to this page. Thermometer- -// coded, so lock state can be advanced permanently from any state -// to any less-permissive state by programming OTP. Software can -// also advance the lock state temporarily (until next OTP reset) -// using the SW_LOCKx registers. -// -// Note that READ_WRITE and READ_ONLY are equivalent in hardware, -// as the SBPI programming interface is not accessible to Non- -// secure software. However, Secure software may check these bits -// to apply write permissions to a Non-secure OTP programming API. -// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. -// 0x1 -> Page can be read by Non-secure software -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. -// 0x3 -> Page can not be accessed by Non-secure software. -#define OTP_DATA_PAGE4_LOCK1_LOCK_NS_RESET "-" -#define OTP_DATA_PAGE4_LOCK1_LOCK_NS_BITS _u(0x0000000c) -#define OTP_DATA_PAGE4_LOCK1_LOCK_NS_MSB _u(3) -#define OTP_DATA_PAGE4_LOCK1_LOCK_NS_LSB _u(2) -#define OTP_DATA_PAGE4_LOCK1_LOCK_NS_ACCESS "RO" -#define OTP_DATA_PAGE4_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE4_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE4_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE4_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE4_LOCK1_LOCK_S -// Description : Lock state for Secure accesses to this page. Thermometer-coded, -// so lock state can be advanced permanently from any state to any -// less-permissive state by programming OTP. Software can also -// advance the lock state temporarily (until next OTP reset) using -// the SW_LOCKx registers. -// 0x0 -> Page is fully accessible by Secure software. -// 0x1 -> Page can be read by Secure software, but can not be written. -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. -// 0x3 -> Page can not be accessed by Secure software. -#define OTP_DATA_PAGE4_LOCK1_LOCK_S_RESET "-" -#define OTP_DATA_PAGE4_LOCK1_LOCK_S_BITS _u(0x00000003) -#define OTP_DATA_PAGE4_LOCK1_LOCK_S_MSB _u(1) -#define OTP_DATA_PAGE4_LOCK1_LOCK_S_LSB _u(0) -#define OTP_DATA_PAGE4_LOCK1_LOCK_S_ACCESS "RO" -#define OTP_DATA_PAGE4_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE4_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE4_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE4_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) -// ============================================================================= -// Register : OTP_DATA_PAGE5_LOCK0 -// Description : Lock configuration LSBs for page 5 (rows 0x140 through 0x17f). -// Locks are stored with 3-way majority vote encoding, so that -// bits can be set independently. -// -// This OTP location is always readable, and is write-protected by -// its own permissions. -#define OTP_DATA_PAGE5_LOCK0_ROW _u(0x00000f8a) -#define OTP_DATA_PAGE5_LOCK0_BITS _u(0x00ffff7f) -#define OTP_DATA_PAGE5_LOCK0_RESET _u(0x00000000) -#define OTP_DATA_PAGE5_LOCK0_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE5_LOCK0_R2 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE5_LOCK0_R2_RESET "-" -#define OTP_DATA_PAGE5_LOCK0_R2_BITS _u(0x00ff0000) -#define OTP_DATA_PAGE5_LOCK0_R2_MSB _u(23) -#define OTP_DATA_PAGE5_LOCK0_R2_LSB _u(16) -#define OTP_DATA_PAGE5_LOCK0_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE5_LOCK0_R1 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE5_LOCK0_R1_RESET "-" -#define OTP_DATA_PAGE5_LOCK0_R1_BITS _u(0x0000ff00) -#define OTP_DATA_PAGE5_LOCK0_R1_MSB _u(15) -#define OTP_DATA_PAGE5_LOCK0_R1_LSB _u(8) -#define OTP_DATA_PAGE5_LOCK0_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE5_LOCK0_NO_KEY_STATE -// Description : State when at least one key is registered for this page and no -// matching key has been entered. -// 0x0 -> read_only -// 0x1 -> inaccessible -#define OTP_DATA_PAGE5_LOCK0_NO_KEY_STATE_RESET "-" -#define OTP_DATA_PAGE5_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) -#define OTP_DATA_PAGE5_LOCK0_NO_KEY_STATE_MSB _u(6) -#define OTP_DATA_PAGE5_LOCK0_NO_KEY_STATE_LSB _u(6) -#define OTP_DATA_PAGE5_LOCK0_NO_KEY_STATE_ACCESS "RO" -#define OTP_DATA_PAGE5_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) -#define OTP_DATA_PAGE5_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE5_LOCK0_KEY_R -// Description : Index 1-6 of a hardware key which must be entered to grant read -// access, or 0 if no such key is required. -#define OTP_DATA_PAGE5_LOCK0_KEY_R_RESET "-" -#define OTP_DATA_PAGE5_LOCK0_KEY_R_BITS _u(0x00000038) -#define OTP_DATA_PAGE5_LOCK0_KEY_R_MSB _u(5) -#define OTP_DATA_PAGE5_LOCK0_KEY_R_LSB _u(3) -#define OTP_DATA_PAGE5_LOCK0_KEY_R_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE5_LOCK0_KEY_W -// Description : Index 1-6 of a hardware key which must be entered to grant -// write access, or 0 if no such key is required. -#define OTP_DATA_PAGE5_LOCK0_KEY_W_RESET "-" -#define OTP_DATA_PAGE5_LOCK0_KEY_W_BITS _u(0x00000007) -#define OTP_DATA_PAGE5_LOCK0_KEY_W_MSB _u(2) -#define OTP_DATA_PAGE5_LOCK0_KEY_W_LSB _u(0) -#define OTP_DATA_PAGE5_LOCK0_KEY_W_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_PAGE5_LOCK1 -// Description : Lock configuration MSBs for page 5 (rows 0x140 through 0x17f). -// Locks are stored with 3-way majority vote encoding, so that -// bits can be set independently. -// -// This OTP location is always readable, and is write-protected by -// its own permissions. -#define OTP_DATA_PAGE5_LOCK1_ROW _u(0x00000f8b) -#define OTP_DATA_PAGE5_LOCK1_BITS _u(0x00ffff3f) -#define OTP_DATA_PAGE5_LOCK1_RESET _u(0x00000000) -#define OTP_DATA_PAGE5_LOCK1_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE5_LOCK1_R2 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE5_LOCK1_R2_RESET "-" -#define OTP_DATA_PAGE5_LOCK1_R2_BITS _u(0x00ff0000) -#define OTP_DATA_PAGE5_LOCK1_R2_MSB _u(23) -#define OTP_DATA_PAGE5_LOCK1_R2_LSB _u(16) -#define OTP_DATA_PAGE5_LOCK1_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE5_LOCK1_R1 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE5_LOCK1_R1_RESET "-" -#define OTP_DATA_PAGE5_LOCK1_R1_BITS _u(0x0000ff00) -#define OTP_DATA_PAGE5_LOCK1_R1_MSB _u(15) -#define OTP_DATA_PAGE5_LOCK1_R1_LSB _u(8) -#define OTP_DATA_PAGE5_LOCK1_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE5_LOCK1_LOCK_BL -// Description : Dummy lock bits reserved for bootloaders (including the RP2350 -// USB bootloader) to store their own OTP access permissions. No -// hardware effect, and no corresponding SW_LOCKx registers. -// 0x0 -> Bootloader permits user reads and writes to this page -// 0x1 -> Bootloader permits user reads of this page -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE -// 0x3 -> Bootloader does not permit user access to this page -#define OTP_DATA_PAGE5_LOCK1_LOCK_BL_RESET "-" -#define OTP_DATA_PAGE5_LOCK1_LOCK_BL_BITS _u(0x00000030) -#define OTP_DATA_PAGE5_LOCK1_LOCK_BL_MSB _u(5) -#define OTP_DATA_PAGE5_LOCK1_LOCK_BL_LSB _u(4) -#define OTP_DATA_PAGE5_LOCK1_LOCK_BL_ACCESS "RO" -#define OTP_DATA_PAGE5_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE5_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE5_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE5_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE5_LOCK1_LOCK_NS -// Description : Lock state for Non-secure accesses to this page. Thermometer- -// coded, so lock state can be advanced permanently from any state -// to any less-permissive state by programming OTP. Software can -// also advance the lock state temporarily (until next OTP reset) -// using the SW_LOCKx registers. -// -// Note that READ_WRITE and READ_ONLY are equivalent in hardware, -// as the SBPI programming interface is not accessible to Non- -// secure software. However, Secure software may check these bits -// to apply write permissions to a Non-secure OTP programming API. -// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. -// 0x1 -> Page can be read by Non-secure software -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. -// 0x3 -> Page can not be accessed by Non-secure software. -#define OTP_DATA_PAGE5_LOCK1_LOCK_NS_RESET "-" -#define OTP_DATA_PAGE5_LOCK1_LOCK_NS_BITS _u(0x0000000c) -#define OTP_DATA_PAGE5_LOCK1_LOCK_NS_MSB _u(3) -#define OTP_DATA_PAGE5_LOCK1_LOCK_NS_LSB _u(2) -#define OTP_DATA_PAGE5_LOCK1_LOCK_NS_ACCESS "RO" -#define OTP_DATA_PAGE5_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE5_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE5_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE5_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE5_LOCK1_LOCK_S -// Description : Lock state for Secure accesses to this page. Thermometer-coded, -// so lock state can be advanced permanently from any state to any -// less-permissive state by programming OTP. Software can also -// advance the lock state temporarily (until next OTP reset) using -// the SW_LOCKx registers. -// 0x0 -> Page is fully accessible by Secure software. -// 0x1 -> Page can be read by Secure software, but can not be written. -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. -// 0x3 -> Page can not be accessed by Secure software. -#define OTP_DATA_PAGE5_LOCK1_LOCK_S_RESET "-" -#define OTP_DATA_PAGE5_LOCK1_LOCK_S_BITS _u(0x00000003) -#define OTP_DATA_PAGE5_LOCK1_LOCK_S_MSB _u(1) -#define OTP_DATA_PAGE5_LOCK1_LOCK_S_LSB _u(0) -#define OTP_DATA_PAGE5_LOCK1_LOCK_S_ACCESS "RO" -#define OTP_DATA_PAGE5_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE5_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE5_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE5_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) -// ============================================================================= -// Register : OTP_DATA_PAGE6_LOCK0 -// Description : Lock configuration LSBs for page 6 (rows 0x180 through 0x1bf). -// Locks are stored with 3-way majority vote encoding, so that -// bits can be set independently. -// -// This OTP location is always readable, and is write-protected by -// its own permissions. -#define OTP_DATA_PAGE6_LOCK0_ROW _u(0x00000f8c) -#define OTP_DATA_PAGE6_LOCK0_BITS _u(0x00ffff7f) -#define OTP_DATA_PAGE6_LOCK0_RESET _u(0x00000000) -#define OTP_DATA_PAGE6_LOCK0_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE6_LOCK0_R2 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE6_LOCK0_R2_RESET "-" -#define OTP_DATA_PAGE6_LOCK0_R2_BITS _u(0x00ff0000) -#define OTP_DATA_PAGE6_LOCK0_R2_MSB _u(23) -#define OTP_DATA_PAGE6_LOCK0_R2_LSB _u(16) -#define OTP_DATA_PAGE6_LOCK0_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE6_LOCK0_R1 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE6_LOCK0_R1_RESET "-" -#define OTP_DATA_PAGE6_LOCK0_R1_BITS _u(0x0000ff00) -#define OTP_DATA_PAGE6_LOCK0_R1_MSB _u(15) -#define OTP_DATA_PAGE6_LOCK0_R1_LSB _u(8) -#define OTP_DATA_PAGE6_LOCK0_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE6_LOCK0_NO_KEY_STATE -// Description : State when at least one key is registered for this page and no -// matching key has been entered. -// 0x0 -> read_only -// 0x1 -> inaccessible -#define OTP_DATA_PAGE6_LOCK0_NO_KEY_STATE_RESET "-" -#define OTP_DATA_PAGE6_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) -#define OTP_DATA_PAGE6_LOCK0_NO_KEY_STATE_MSB _u(6) -#define OTP_DATA_PAGE6_LOCK0_NO_KEY_STATE_LSB _u(6) -#define OTP_DATA_PAGE6_LOCK0_NO_KEY_STATE_ACCESS "RO" -#define OTP_DATA_PAGE6_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) -#define OTP_DATA_PAGE6_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE6_LOCK0_KEY_R -// Description : Index 1-6 of a hardware key which must be entered to grant read -// access, or 0 if no such key is required. -#define OTP_DATA_PAGE6_LOCK0_KEY_R_RESET "-" -#define OTP_DATA_PAGE6_LOCK0_KEY_R_BITS _u(0x00000038) -#define OTP_DATA_PAGE6_LOCK0_KEY_R_MSB _u(5) -#define OTP_DATA_PAGE6_LOCK0_KEY_R_LSB _u(3) -#define OTP_DATA_PAGE6_LOCK0_KEY_R_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE6_LOCK0_KEY_W -// Description : Index 1-6 of a hardware key which must be entered to grant -// write access, or 0 if no such key is required. -#define OTP_DATA_PAGE6_LOCK0_KEY_W_RESET "-" -#define OTP_DATA_PAGE6_LOCK0_KEY_W_BITS _u(0x00000007) -#define OTP_DATA_PAGE6_LOCK0_KEY_W_MSB _u(2) -#define OTP_DATA_PAGE6_LOCK0_KEY_W_LSB _u(0) -#define OTP_DATA_PAGE6_LOCK0_KEY_W_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_PAGE6_LOCK1 -// Description : Lock configuration MSBs for page 6 (rows 0x180 through 0x1bf). -// Locks are stored with 3-way majority vote encoding, so that -// bits can be set independently. -// -// This OTP location is always readable, and is write-protected by -// its own permissions. -#define OTP_DATA_PAGE6_LOCK1_ROW _u(0x00000f8d) -#define OTP_DATA_PAGE6_LOCK1_BITS _u(0x00ffff3f) -#define OTP_DATA_PAGE6_LOCK1_RESET _u(0x00000000) -#define OTP_DATA_PAGE6_LOCK1_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE6_LOCK1_R2 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE6_LOCK1_R2_RESET "-" -#define OTP_DATA_PAGE6_LOCK1_R2_BITS _u(0x00ff0000) -#define OTP_DATA_PAGE6_LOCK1_R2_MSB _u(23) -#define OTP_DATA_PAGE6_LOCK1_R2_LSB _u(16) -#define OTP_DATA_PAGE6_LOCK1_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE6_LOCK1_R1 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE6_LOCK1_R1_RESET "-" -#define OTP_DATA_PAGE6_LOCK1_R1_BITS _u(0x0000ff00) -#define OTP_DATA_PAGE6_LOCK1_R1_MSB _u(15) -#define OTP_DATA_PAGE6_LOCK1_R1_LSB _u(8) -#define OTP_DATA_PAGE6_LOCK1_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE6_LOCK1_LOCK_BL -// Description : Dummy lock bits reserved for bootloaders (including the RP2350 -// USB bootloader) to store their own OTP access permissions. No -// hardware effect, and no corresponding SW_LOCKx registers. -// 0x0 -> Bootloader permits user reads and writes to this page -// 0x1 -> Bootloader permits user reads of this page -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE -// 0x3 -> Bootloader does not permit user access to this page -#define OTP_DATA_PAGE6_LOCK1_LOCK_BL_RESET "-" -#define OTP_DATA_PAGE6_LOCK1_LOCK_BL_BITS _u(0x00000030) -#define OTP_DATA_PAGE6_LOCK1_LOCK_BL_MSB _u(5) -#define OTP_DATA_PAGE6_LOCK1_LOCK_BL_LSB _u(4) -#define OTP_DATA_PAGE6_LOCK1_LOCK_BL_ACCESS "RO" -#define OTP_DATA_PAGE6_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE6_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE6_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE6_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE6_LOCK1_LOCK_NS -// Description : Lock state for Non-secure accesses to this page. Thermometer- -// coded, so lock state can be advanced permanently from any state -// to any less-permissive state by programming OTP. Software can -// also advance the lock state temporarily (until next OTP reset) -// using the SW_LOCKx registers. -// -// Note that READ_WRITE and READ_ONLY are equivalent in hardware, -// as the SBPI programming interface is not accessible to Non- -// secure software. However, Secure software may check these bits -// to apply write permissions to a Non-secure OTP programming API. -// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. -// 0x1 -> Page can be read by Non-secure software -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. -// 0x3 -> Page can not be accessed by Non-secure software. -#define OTP_DATA_PAGE6_LOCK1_LOCK_NS_RESET "-" -#define OTP_DATA_PAGE6_LOCK1_LOCK_NS_BITS _u(0x0000000c) -#define OTP_DATA_PAGE6_LOCK1_LOCK_NS_MSB _u(3) -#define OTP_DATA_PAGE6_LOCK1_LOCK_NS_LSB _u(2) -#define OTP_DATA_PAGE6_LOCK1_LOCK_NS_ACCESS "RO" -#define OTP_DATA_PAGE6_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE6_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE6_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE6_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE6_LOCK1_LOCK_S -// Description : Lock state for Secure accesses to this page. Thermometer-coded, -// so lock state can be advanced permanently from any state to any -// less-permissive state by programming OTP. Software can also -// advance the lock state temporarily (until next OTP reset) using -// the SW_LOCKx registers. -// 0x0 -> Page is fully accessible by Secure software. -// 0x1 -> Page can be read by Secure software, but can not be written. -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. -// 0x3 -> Page can not be accessed by Secure software. -#define OTP_DATA_PAGE6_LOCK1_LOCK_S_RESET "-" -#define OTP_DATA_PAGE6_LOCK1_LOCK_S_BITS _u(0x00000003) -#define OTP_DATA_PAGE6_LOCK1_LOCK_S_MSB _u(1) -#define OTP_DATA_PAGE6_LOCK1_LOCK_S_LSB _u(0) -#define OTP_DATA_PAGE6_LOCK1_LOCK_S_ACCESS "RO" -#define OTP_DATA_PAGE6_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE6_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE6_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE6_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) -// ============================================================================= -// Register : OTP_DATA_PAGE7_LOCK0 -// Description : Lock configuration LSBs for page 7 (rows 0x1c0 through 0x1ff). -// Locks are stored with 3-way majority vote encoding, so that -// bits can be set independently. -// -// This OTP location is always readable, and is write-protected by -// its own permissions. -#define OTP_DATA_PAGE7_LOCK0_ROW _u(0x00000f8e) -#define OTP_DATA_PAGE7_LOCK0_BITS _u(0x00ffff7f) -#define OTP_DATA_PAGE7_LOCK0_RESET _u(0x00000000) -#define OTP_DATA_PAGE7_LOCK0_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE7_LOCK0_R2 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE7_LOCK0_R2_RESET "-" -#define OTP_DATA_PAGE7_LOCK0_R2_BITS _u(0x00ff0000) -#define OTP_DATA_PAGE7_LOCK0_R2_MSB _u(23) -#define OTP_DATA_PAGE7_LOCK0_R2_LSB _u(16) -#define OTP_DATA_PAGE7_LOCK0_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE7_LOCK0_R1 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE7_LOCK0_R1_RESET "-" -#define OTP_DATA_PAGE7_LOCK0_R1_BITS _u(0x0000ff00) -#define OTP_DATA_PAGE7_LOCK0_R1_MSB _u(15) -#define OTP_DATA_PAGE7_LOCK0_R1_LSB _u(8) -#define OTP_DATA_PAGE7_LOCK0_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE7_LOCK0_NO_KEY_STATE -// Description : State when at least one key is registered for this page and no -// matching key has been entered. -// 0x0 -> read_only -// 0x1 -> inaccessible -#define OTP_DATA_PAGE7_LOCK0_NO_KEY_STATE_RESET "-" -#define OTP_DATA_PAGE7_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) -#define OTP_DATA_PAGE7_LOCK0_NO_KEY_STATE_MSB _u(6) -#define OTP_DATA_PAGE7_LOCK0_NO_KEY_STATE_LSB _u(6) -#define OTP_DATA_PAGE7_LOCK0_NO_KEY_STATE_ACCESS "RO" -#define OTP_DATA_PAGE7_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) -#define OTP_DATA_PAGE7_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE7_LOCK0_KEY_R -// Description : Index 1-6 of a hardware key which must be entered to grant read -// access, or 0 if no such key is required. -#define OTP_DATA_PAGE7_LOCK0_KEY_R_RESET "-" -#define OTP_DATA_PAGE7_LOCK0_KEY_R_BITS _u(0x00000038) -#define OTP_DATA_PAGE7_LOCK0_KEY_R_MSB _u(5) -#define OTP_DATA_PAGE7_LOCK0_KEY_R_LSB _u(3) -#define OTP_DATA_PAGE7_LOCK0_KEY_R_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE7_LOCK0_KEY_W -// Description : Index 1-6 of a hardware key which must be entered to grant -// write access, or 0 if no such key is required. -#define OTP_DATA_PAGE7_LOCK0_KEY_W_RESET "-" -#define OTP_DATA_PAGE7_LOCK0_KEY_W_BITS _u(0x00000007) -#define OTP_DATA_PAGE7_LOCK0_KEY_W_MSB _u(2) -#define OTP_DATA_PAGE7_LOCK0_KEY_W_LSB _u(0) -#define OTP_DATA_PAGE7_LOCK0_KEY_W_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_PAGE7_LOCK1 -// Description : Lock configuration MSBs for page 7 (rows 0x1c0 through 0x1ff). -// Locks are stored with 3-way majority vote encoding, so that -// bits can be set independently. -// -// This OTP location is always readable, and is write-protected by -// its own permissions. -#define OTP_DATA_PAGE7_LOCK1_ROW _u(0x00000f8f) -#define OTP_DATA_PAGE7_LOCK1_BITS _u(0x00ffff3f) -#define OTP_DATA_PAGE7_LOCK1_RESET _u(0x00000000) -#define OTP_DATA_PAGE7_LOCK1_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE7_LOCK1_R2 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE7_LOCK1_R2_RESET "-" -#define OTP_DATA_PAGE7_LOCK1_R2_BITS _u(0x00ff0000) -#define OTP_DATA_PAGE7_LOCK1_R2_MSB _u(23) -#define OTP_DATA_PAGE7_LOCK1_R2_LSB _u(16) -#define OTP_DATA_PAGE7_LOCK1_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE7_LOCK1_R1 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE7_LOCK1_R1_RESET "-" -#define OTP_DATA_PAGE7_LOCK1_R1_BITS _u(0x0000ff00) -#define OTP_DATA_PAGE7_LOCK1_R1_MSB _u(15) -#define OTP_DATA_PAGE7_LOCK1_R1_LSB _u(8) -#define OTP_DATA_PAGE7_LOCK1_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE7_LOCK1_LOCK_BL -// Description : Dummy lock bits reserved for bootloaders (including the RP2350 -// USB bootloader) to store their own OTP access permissions. No -// hardware effect, and no corresponding SW_LOCKx registers. -// 0x0 -> Bootloader permits user reads and writes to this page -// 0x1 -> Bootloader permits user reads of this page -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE -// 0x3 -> Bootloader does not permit user access to this page -#define OTP_DATA_PAGE7_LOCK1_LOCK_BL_RESET "-" -#define OTP_DATA_PAGE7_LOCK1_LOCK_BL_BITS _u(0x00000030) -#define OTP_DATA_PAGE7_LOCK1_LOCK_BL_MSB _u(5) -#define OTP_DATA_PAGE7_LOCK1_LOCK_BL_LSB _u(4) -#define OTP_DATA_PAGE7_LOCK1_LOCK_BL_ACCESS "RO" -#define OTP_DATA_PAGE7_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE7_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE7_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE7_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE7_LOCK1_LOCK_NS -// Description : Lock state for Non-secure accesses to this page. Thermometer- -// coded, so lock state can be advanced permanently from any state -// to any less-permissive state by programming OTP. Software can -// also advance the lock state temporarily (until next OTP reset) -// using the SW_LOCKx registers. -// -// Note that READ_WRITE and READ_ONLY are equivalent in hardware, -// as the SBPI programming interface is not accessible to Non- -// secure software. However, Secure software may check these bits -// to apply write permissions to a Non-secure OTP programming API. -// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. -// 0x1 -> Page can be read by Non-secure software -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. -// 0x3 -> Page can not be accessed by Non-secure software. -#define OTP_DATA_PAGE7_LOCK1_LOCK_NS_RESET "-" -#define OTP_DATA_PAGE7_LOCK1_LOCK_NS_BITS _u(0x0000000c) -#define OTP_DATA_PAGE7_LOCK1_LOCK_NS_MSB _u(3) -#define OTP_DATA_PAGE7_LOCK1_LOCK_NS_LSB _u(2) -#define OTP_DATA_PAGE7_LOCK1_LOCK_NS_ACCESS "RO" -#define OTP_DATA_PAGE7_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE7_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE7_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE7_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE7_LOCK1_LOCK_S -// Description : Lock state for Secure accesses to this page. Thermometer-coded, -// so lock state can be advanced permanently from any state to any -// less-permissive state by programming OTP. Software can also -// advance the lock state temporarily (until next OTP reset) using -// the SW_LOCKx registers. -// 0x0 -> Page is fully accessible by Secure software. -// 0x1 -> Page can be read by Secure software, but can not be written. -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. -// 0x3 -> Page can not be accessed by Secure software. -#define OTP_DATA_PAGE7_LOCK1_LOCK_S_RESET "-" -#define OTP_DATA_PAGE7_LOCK1_LOCK_S_BITS _u(0x00000003) -#define OTP_DATA_PAGE7_LOCK1_LOCK_S_MSB _u(1) -#define OTP_DATA_PAGE7_LOCK1_LOCK_S_LSB _u(0) -#define OTP_DATA_PAGE7_LOCK1_LOCK_S_ACCESS "RO" -#define OTP_DATA_PAGE7_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE7_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE7_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE7_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) -// ============================================================================= -// Register : OTP_DATA_PAGE8_LOCK0 -// Description : Lock configuration LSBs for page 8 (rows 0x200 through 0x23f). -// Locks are stored with 3-way majority vote encoding, so that -// bits can be set independently. -// -// This OTP location is always readable, and is write-protected by -// its own permissions. -#define OTP_DATA_PAGE8_LOCK0_ROW _u(0x00000f90) -#define OTP_DATA_PAGE8_LOCK0_BITS _u(0x00ffff7f) -#define OTP_DATA_PAGE8_LOCK0_RESET _u(0x00000000) -#define OTP_DATA_PAGE8_LOCK0_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE8_LOCK0_R2 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE8_LOCK0_R2_RESET "-" -#define OTP_DATA_PAGE8_LOCK0_R2_BITS _u(0x00ff0000) -#define OTP_DATA_PAGE8_LOCK0_R2_MSB _u(23) -#define OTP_DATA_PAGE8_LOCK0_R2_LSB _u(16) -#define OTP_DATA_PAGE8_LOCK0_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE8_LOCK0_R1 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE8_LOCK0_R1_RESET "-" -#define OTP_DATA_PAGE8_LOCK0_R1_BITS _u(0x0000ff00) -#define OTP_DATA_PAGE8_LOCK0_R1_MSB _u(15) -#define OTP_DATA_PAGE8_LOCK0_R1_LSB _u(8) -#define OTP_DATA_PAGE8_LOCK0_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE8_LOCK0_NO_KEY_STATE -// Description : State when at least one key is registered for this page and no -// matching key has been entered. -// 0x0 -> read_only -// 0x1 -> inaccessible -#define OTP_DATA_PAGE8_LOCK0_NO_KEY_STATE_RESET "-" -#define OTP_DATA_PAGE8_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) -#define OTP_DATA_PAGE8_LOCK0_NO_KEY_STATE_MSB _u(6) -#define OTP_DATA_PAGE8_LOCK0_NO_KEY_STATE_LSB _u(6) -#define OTP_DATA_PAGE8_LOCK0_NO_KEY_STATE_ACCESS "RO" -#define OTP_DATA_PAGE8_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) -#define OTP_DATA_PAGE8_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE8_LOCK0_KEY_R -// Description : Index 1-6 of a hardware key which must be entered to grant read -// access, or 0 if no such key is required. -#define OTP_DATA_PAGE8_LOCK0_KEY_R_RESET "-" -#define OTP_DATA_PAGE8_LOCK0_KEY_R_BITS _u(0x00000038) -#define OTP_DATA_PAGE8_LOCK0_KEY_R_MSB _u(5) -#define OTP_DATA_PAGE8_LOCK0_KEY_R_LSB _u(3) -#define OTP_DATA_PAGE8_LOCK0_KEY_R_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE8_LOCK0_KEY_W -// Description : Index 1-6 of a hardware key which must be entered to grant -// write access, or 0 if no such key is required. -#define OTP_DATA_PAGE8_LOCK0_KEY_W_RESET "-" -#define OTP_DATA_PAGE8_LOCK0_KEY_W_BITS _u(0x00000007) -#define OTP_DATA_PAGE8_LOCK0_KEY_W_MSB _u(2) -#define OTP_DATA_PAGE8_LOCK0_KEY_W_LSB _u(0) -#define OTP_DATA_PAGE8_LOCK0_KEY_W_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_PAGE8_LOCK1 -// Description : Lock configuration MSBs for page 8 (rows 0x200 through 0x23f). -// Locks are stored with 3-way majority vote encoding, so that -// bits can be set independently. -// -// This OTP location is always readable, and is write-protected by -// its own permissions. -#define OTP_DATA_PAGE8_LOCK1_ROW _u(0x00000f91) -#define OTP_DATA_PAGE8_LOCK1_BITS _u(0x00ffff3f) -#define OTP_DATA_PAGE8_LOCK1_RESET _u(0x00000000) -#define OTP_DATA_PAGE8_LOCK1_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE8_LOCK1_R2 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE8_LOCK1_R2_RESET "-" -#define OTP_DATA_PAGE8_LOCK1_R2_BITS _u(0x00ff0000) -#define OTP_DATA_PAGE8_LOCK1_R2_MSB _u(23) -#define OTP_DATA_PAGE8_LOCK1_R2_LSB _u(16) -#define OTP_DATA_PAGE8_LOCK1_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE8_LOCK1_R1 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE8_LOCK1_R1_RESET "-" -#define OTP_DATA_PAGE8_LOCK1_R1_BITS _u(0x0000ff00) -#define OTP_DATA_PAGE8_LOCK1_R1_MSB _u(15) -#define OTP_DATA_PAGE8_LOCK1_R1_LSB _u(8) -#define OTP_DATA_PAGE8_LOCK1_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE8_LOCK1_LOCK_BL -// Description : Dummy lock bits reserved for bootloaders (including the RP2350 -// USB bootloader) to store their own OTP access permissions. No -// hardware effect, and no corresponding SW_LOCKx registers. -// 0x0 -> Bootloader permits user reads and writes to this page -// 0x1 -> Bootloader permits user reads of this page -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE -// 0x3 -> Bootloader does not permit user access to this page -#define OTP_DATA_PAGE8_LOCK1_LOCK_BL_RESET "-" -#define OTP_DATA_PAGE8_LOCK1_LOCK_BL_BITS _u(0x00000030) -#define OTP_DATA_PAGE8_LOCK1_LOCK_BL_MSB _u(5) -#define OTP_DATA_PAGE8_LOCK1_LOCK_BL_LSB _u(4) -#define OTP_DATA_PAGE8_LOCK1_LOCK_BL_ACCESS "RO" -#define OTP_DATA_PAGE8_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE8_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE8_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE8_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE8_LOCK1_LOCK_NS -// Description : Lock state for Non-secure accesses to this page. Thermometer- -// coded, so lock state can be advanced permanently from any state -// to any less-permissive state by programming OTP. Software can -// also advance the lock state temporarily (until next OTP reset) -// using the SW_LOCKx registers. -// -// Note that READ_WRITE and READ_ONLY are equivalent in hardware, -// as the SBPI programming interface is not accessible to Non- -// secure software. However, Secure software may check these bits -// to apply write permissions to a Non-secure OTP programming API. -// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. -// 0x1 -> Page can be read by Non-secure software -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. -// 0x3 -> Page can not be accessed by Non-secure software. -#define OTP_DATA_PAGE8_LOCK1_LOCK_NS_RESET "-" -#define OTP_DATA_PAGE8_LOCK1_LOCK_NS_BITS _u(0x0000000c) -#define OTP_DATA_PAGE8_LOCK1_LOCK_NS_MSB _u(3) -#define OTP_DATA_PAGE8_LOCK1_LOCK_NS_LSB _u(2) -#define OTP_DATA_PAGE8_LOCK1_LOCK_NS_ACCESS "RO" -#define OTP_DATA_PAGE8_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE8_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE8_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE8_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE8_LOCK1_LOCK_S -// Description : Lock state for Secure accesses to this page. Thermometer-coded, -// so lock state can be advanced permanently from any state to any -// less-permissive state by programming OTP. Software can also -// advance the lock state temporarily (until next OTP reset) using -// the SW_LOCKx registers. -// 0x0 -> Page is fully accessible by Secure software. -// 0x1 -> Page can be read by Secure software, but can not be written. -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. -// 0x3 -> Page can not be accessed by Secure software. -#define OTP_DATA_PAGE8_LOCK1_LOCK_S_RESET "-" -#define OTP_DATA_PAGE8_LOCK1_LOCK_S_BITS _u(0x00000003) -#define OTP_DATA_PAGE8_LOCK1_LOCK_S_MSB _u(1) -#define OTP_DATA_PAGE8_LOCK1_LOCK_S_LSB _u(0) -#define OTP_DATA_PAGE8_LOCK1_LOCK_S_ACCESS "RO" -#define OTP_DATA_PAGE8_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE8_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE8_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE8_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) -// ============================================================================= -// Register : OTP_DATA_PAGE9_LOCK0 -// Description : Lock configuration LSBs for page 9 (rows 0x240 through 0x27f). -// Locks are stored with 3-way majority vote encoding, so that -// bits can be set independently. -// -// This OTP location is always readable, and is write-protected by -// its own permissions. -#define OTP_DATA_PAGE9_LOCK0_ROW _u(0x00000f92) -#define OTP_DATA_PAGE9_LOCK0_BITS _u(0x00ffff7f) -#define OTP_DATA_PAGE9_LOCK0_RESET _u(0x00000000) -#define OTP_DATA_PAGE9_LOCK0_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE9_LOCK0_R2 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE9_LOCK0_R2_RESET "-" -#define OTP_DATA_PAGE9_LOCK0_R2_BITS _u(0x00ff0000) -#define OTP_DATA_PAGE9_LOCK0_R2_MSB _u(23) -#define OTP_DATA_PAGE9_LOCK0_R2_LSB _u(16) -#define OTP_DATA_PAGE9_LOCK0_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE9_LOCK0_R1 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE9_LOCK0_R1_RESET "-" -#define OTP_DATA_PAGE9_LOCK0_R1_BITS _u(0x0000ff00) -#define OTP_DATA_PAGE9_LOCK0_R1_MSB _u(15) -#define OTP_DATA_PAGE9_LOCK0_R1_LSB _u(8) -#define OTP_DATA_PAGE9_LOCK0_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE9_LOCK0_NO_KEY_STATE -// Description : State when at least one key is registered for this page and no -// matching key has been entered. -// 0x0 -> read_only -// 0x1 -> inaccessible -#define OTP_DATA_PAGE9_LOCK0_NO_KEY_STATE_RESET "-" -#define OTP_DATA_PAGE9_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) -#define OTP_DATA_PAGE9_LOCK0_NO_KEY_STATE_MSB _u(6) -#define OTP_DATA_PAGE9_LOCK0_NO_KEY_STATE_LSB _u(6) -#define OTP_DATA_PAGE9_LOCK0_NO_KEY_STATE_ACCESS "RO" -#define OTP_DATA_PAGE9_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) -#define OTP_DATA_PAGE9_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE9_LOCK0_KEY_R -// Description : Index 1-6 of a hardware key which must be entered to grant read -// access, or 0 if no such key is required. -#define OTP_DATA_PAGE9_LOCK0_KEY_R_RESET "-" -#define OTP_DATA_PAGE9_LOCK0_KEY_R_BITS _u(0x00000038) -#define OTP_DATA_PAGE9_LOCK0_KEY_R_MSB _u(5) -#define OTP_DATA_PAGE9_LOCK0_KEY_R_LSB _u(3) -#define OTP_DATA_PAGE9_LOCK0_KEY_R_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE9_LOCK0_KEY_W -// Description : Index 1-6 of a hardware key which must be entered to grant -// write access, or 0 if no such key is required. -#define OTP_DATA_PAGE9_LOCK0_KEY_W_RESET "-" -#define OTP_DATA_PAGE9_LOCK0_KEY_W_BITS _u(0x00000007) -#define OTP_DATA_PAGE9_LOCK0_KEY_W_MSB _u(2) -#define OTP_DATA_PAGE9_LOCK0_KEY_W_LSB _u(0) -#define OTP_DATA_PAGE9_LOCK0_KEY_W_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_PAGE9_LOCK1 -// Description : Lock configuration MSBs for page 9 (rows 0x240 through 0x27f). -// Locks are stored with 3-way majority vote encoding, so that -// bits can be set independently. -// -// This OTP location is always readable, and is write-protected by -// its own permissions. -#define OTP_DATA_PAGE9_LOCK1_ROW _u(0x00000f93) -#define OTP_DATA_PAGE9_LOCK1_BITS _u(0x00ffff3f) -#define OTP_DATA_PAGE9_LOCK1_RESET _u(0x00000000) -#define OTP_DATA_PAGE9_LOCK1_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE9_LOCK1_R2 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE9_LOCK1_R2_RESET "-" -#define OTP_DATA_PAGE9_LOCK1_R2_BITS _u(0x00ff0000) -#define OTP_DATA_PAGE9_LOCK1_R2_MSB _u(23) -#define OTP_DATA_PAGE9_LOCK1_R2_LSB _u(16) -#define OTP_DATA_PAGE9_LOCK1_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE9_LOCK1_R1 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE9_LOCK1_R1_RESET "-" -#define OTP_DATA_PAGE9_LOCK1_R1_BITS _u(0x0000ff00) -#define OTP_DATA_PAGE9_LOCK1_R1_MSB _u(15) -#define OTP_DATA_PAGE9_LOCK1_R1_LSB _u(8) -#define OTP_DATA_PAGE9_LOCK1_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE9_LOCK1_LOCK_BL -// Description : Dummy lock bits reserved for bootloaders (including the RP2350 -// USB bootloader) to store their own OTP access permissions. No -// hardware effect, and no corresponding SW_LOCKx registers. -// 0x0 -> Bootloader permits user reads and writes to this page -// 0x1 -> Bootloader permits user reads of this page -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE -// 0x3 -> Bootloader does not permit user access to this page -#define OTP_DATA_PAGE9_LOCK1_LOCK_BL_RESET "-" -#define OTP_DATA_PAGE9_LOCK1_LOCK_BL_BITS _u(0x00000030) -#define OTP_DATA_PAGE9_LOCK1_LOCK_BL_MSB _u(5) -#define OTP_DATA_PAGE9_LOCK1_LOCK_BL_LSB _u(4) -#define OTP_DATA_PAGE9_LOCK1_LOCK_BL_ACCESS "RO" -#define OTP_DATA_PAGE9_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE9_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE9_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE9_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE9_LOCK1_LOCK_NS -// Description : Lock state for Non-secure accesses to this page. Thermometer- -// coded, so lock state can be advanced permanently from any state -// to any less-permissive state by programming OTP. Software can -// also advance the lock state temporarily (until next OTP reset) -// using the SW_LOCKx registers. -// -// Note that READ_WRITE and READ_ONLY are equivalent in hardware, -// as the SBPI programming interface is not accessible to Non- -// secure software. However, Secure software may check these bits -// to apply write permissions to a Non-secure OTP programming API. -// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. -// 0x1 -> Page can be read by Non-secure software -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. -// 0x3 -> Page can not be accessed by Non-secure software. -#define OTP_DATA_PAGE9_LOCK1_LOCK_NS_RESET "-" -#define OTP_DATA_PAGE9_LOCK1_LOCK_NS_BITS _u(0x0000000c) -#define OTP_DATA_PAGE9_LOCK1_LOCK_NS_MSB _u(3) -#define OTP_DATA_PAGE9_LOCK1_LOCK_NS_LSB _u(2) -#define OTP_DATA_PAGE9_LOCK1_LOCK_NS_ACCESS "RO" -#define OTP_DATA_PAGE9_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE9_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE9_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE9_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE9_LOCK1_LOCK_S -// Description : Lock state for Secure accesses to this page. Thermometer-coded, -// so lock state can be advanced permanently from any state to any -// less-permissive state by programming OTP. Software can also -// advance the lock state temporarily (until next OTP reset) using -// the SW_LOCKx registers. -// 0x0 -> Page is fully accessible by Secure software. -// 0x1 -> Page can be read by Secure software, but can not be written. -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. -// 0x3 -> Page can not be accessed by Secure software. -#define OTP_DATA_PAGE9_LOCK1_LOCK_S_RESET "-" -#define OTP_DATA_PAGE9_LOCK1_LOCK_S_BITS _u(0x00000003) -#define OTP_DATA_PAGE9_LOCK1_LOCK_S_MSB _u(1) -#define OTP_DATA_PAGE9_LOCK1_LOCK_S_LSB _u(0) -#define OTP_DATA_PAGE9_LOCK1_LOCK_S_ACCESS "RO" -#define OTP_DATA_PAGE9_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE9_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE9_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE9_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) -// ============================================================================= -// Register : OTP_DATA_PAGE10_LOCK0 -// Description : Lock configuration LSBs for page 10 (rows 0x280 through 0x2bf). -// Locks are stored with 3-way majority vote encoding, so that -// bits can be set independently. -// -// This OTP location is always readable, and is write-protected by -// its own permissions. -#define OTP_DATA_PAGE10_LOCK0_ROW _u(0x00000f94) -#define OTP_DATA_PAGE10_LOCK0_BITS _u(0x00ffff7f) -#define OTP_DATA_PAGE10_LOCK0_RESET _u(0x00000000) -#define OTP_DATA_PAGE10_LOCK0_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE10_LOCK0_R2 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE10_LOCK0_R2_RESET "-" -#define OTP_DATA_PAGE10_LOCK0_R2_BITS _u(0x00ff0000) -#define OTP_DATA_PAGE10_LOCK0_R2_MSB _u(23) -#define OTP_DATA_PAGE10_LOCK0_R2_LSB _u(16) -#define OTP_DATA_PAGE10_LOCK0_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE10_LOCK0_R1 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE10_LOCK0_R1_RESET "-" -#define OTP_DATA_PAGE10_LOCK0_R1_BITS _u(0x0000ff00) -#define OTP_DATA_PAGE10_LOCK0_R1_MSB _u(15) -#define OTP_DATA_PAGE10_LOCK0_R1_LSB _u(8) -#define OTP_DATA_PAGE10_LOCK0_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE10_LOCK0_NO_KEY_STATE -// Description : State when at least one key is registered for this page and no -// matching key has been entered. -// 0x0 -> read_only -// 0x1 -> inaccessible -#define OTP_DATA_PAGE10_LOCK0_NO_KEY_STATE_RESET "-" -#define OTP_DATA_PAGE10_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) -#define OTP_DATA_PAGE10_LOCK0_NO_KEY_STATE_MSB _u(6) -#define OTP_DATA_PAGE10_LOCK0_NO_KEY_STATE_LSB _u(6) -#define OTP_DATA_PAGE10_LOCK0_NO_KEY_STATE_ACCESS "RO" -#define OTP_DATA_PAGE10_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) -#define OTP_DATA_PAGE10_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE10_LOCK0_KEY_R -// Description : Index 1-6 of a hardware key which must be entered to grant read -// access, or 0 if no such key is required. -#define OTP_DATA_PAGE10_LOCK0_KEY_R_RESET "-" -#define OTP_DATA_PAGE10_LOCK0_KEY_R_BITS _u(0x00000038) -#define OTP_DATA_PAGE10_LOCK0_KEY_R_MSB _u(5) -#define OTP_DATA_PAGE10_LOCK0_KEY_R_LSB _u(3) -#define OTP_DATA_PAGE10_LOCK0_KEY_R_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE10_LOCK0_KEY_W -// Description : Index 1-6 of a hardware key which must be entered to grant -// write access, or 0 if no such key is required. -#define OTP_DATA_PAGE10_LOCK0_KEY_W_RESET "-" -#define OTP_DATA_PAGE10_LOCK0_KEY_W_BITS _u(0x00000007) -#define OTP_DATA_PAGE10_LOCK0_KEY_W_MSB _u(2) -#define OTP_DATA_PAGE10_LOCK0_KEY_W_LSB _u(0) -#define OTP_DATA_PAGE10_LOCK0_KEY_W_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_PAGE10_LOCK1 -// Description : Lock configuration MSBs for page 10 (rows 0x280 through 0x2bf). -// Locks are stored with 3-way majority vote encoding, so that -// bits can be set independently. -// -// This OTP location is always readable, and is write-protected by -// its own permissions. -#define OTP_DATA_PAGE10_LOCK1_ROW _u(0x00000f95) -#define OTP_DATA_PAGE10_LOCK1_BITS _u(0x00ffff3f) -#define OTP_DATA_PAGE10_LOCK1_RESET _u(0x00000000) -#define OTP_DATA_PAGE10_LOCK1_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE10_LOCK1_R2 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE10_LOCK1_R2_RESET "-" -#define OTP_DATA_PAGE10_LOCK1_R2_BITS _u(0x00ff0000) -#define OTP_DATA_PAGE10_LOCK1_R2_MSB _u(23) -#define OTP_DATA_PAGE10_LOCK1_R2_LSB _u(16) -#define OTP_DATA_PAGE10_LOCK1_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE10_LOCK1_R1 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE10_LOCK1_R1_RESET "-" -#define OTP_DATA_PAGE10_LOCK1_R1_BITS _u(0x0000ff00) -#define OTP_DATA_PAGE10_LOCK1_R1_MSB _u(15) -#define OTP_DATA_PAGE10_LOCK1_R1_LSB _u(8) -#define OTP_DATA_PAGE10_LOCK1_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE10_LOCK1_LOCK_BL -// Description : Dummy lock bits reserved for bootloaders (including the RP2350 -// USB bootloader) to store their own OTP access permissions. No -// hardware effect, and no corresponding SW_LOCKx registers. -// 0x0 -> Bootloader permits user reads and writes to this page -// 0x1 -> Bootloader permits user reads of this page -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE -// 0x3 -> Bootloader does not permit user access to this page -#define OTP_DATA_PAGE10_LOCK1_LOCK_BL_RESET "-" -#define OTP_DATA_PAGE10_LOCK1_LOCK_BL_BITS _u(0x00000030) -#define OTP_DATA_PAGE10_LOCK1_LOCK_BL_MSB _u(5) -#define OTP_DATA_PAGE10_LOCK1_LOCK_BL_LSB _u(4) -#define OTP_DATA_PAGE10_LOCK1_LOCK_BL_ACCESS "RO" -#define OTP_DATA_PAGE10_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE10_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE10_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE10_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE10_LOCK1_LOCK_NS -// Description : Lock state for Non-secure accesses to this page. Thermometer- -// coded, so lock state can be advanced permanently from any state -// to any less-permissive state by programming OTP. Software can -// also advance the lock state temporarily (until next OTP reset) -// using the SW_LOCKx registers. -// -// Note that READ_WRITE and READ_ONLY are equivalent in hardware, -// as the SBPI programming interface is not accessible to Non- -// secure software. However, Secure software may check these bits -// to apply write permissions to a Non-secure OTP programming API. -// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. -// 0x1 -> Page can be read by Non-secure software -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. -// 0x3 -> Page can not be accessed by Non-secure software. -#define OTP_DATA_PAGE10_LOCK1_LOCK_NS_RESET "-" -#define OTP_DATA_PAGE10_LOCK1_LOCK_NS_BITS _u(0x0000000c) -#define OTP_DATA_PAGE10_LOCK1_LOCK_NS_MSB _u(3) -#define OTP_DATA_PAGE10_LOCK1_LOCK_NS_LSB _u(2) -#define OTP_DATA_PAGE10_LOCK1_LOCK_NS_ACCESS "RO" -#define OTP_DATA_PAGE10_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE10_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE10_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE10_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE10_LOCK1_LOCK_S -// Description : Lock state for Secure accesses to this page. Thermometer-coded, -// so lock state can be advanced permanently from any state to any -// less-permissive state by programming OTP. Software can also -// advance the lock state temporarily (until next OTP reset) using -// the SW_LOCKx registers. -// 0x0 -> Page is fully accessible by Secure software. -// 0x1 -> Page can be read by Secure software, but can not be written. -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. -// 0x3 -> Page can not be accessed by Secure software. -#define OTP_DATA_PAGE10_LOCK1_LOCK_S_RESET "-" -#define OTP_DATA_PAGE10_LOCK1_LOCK_S_BITS _u(0x00000003) -#define OTP_DATA_PAGE10_LOCK1_LOCK_S_MSB _u(1) -#define OTP_DATA_PAGE10_LOCK1_LOCK_S_LSB _u(0) -#define OTP_DATA_PAGE10_LOCK1_LOCK_S_ACCESS "RO" -#define OTP_DATA_PAGE10_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE10_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE10_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE10_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) -// ============================================================================= -// Register : OTP_DATA_PAGE11_LOCK0 -// Description : Lock configuration LSBs for page 11 (rows 0x2c0 through 0x2ff). -// Locks are stored with 3-way majority vote encoding, so that -// bits can be set independently. -// -// This OTP location is always readable, and is write-protected by -// its own permissions. -#define OTP_DATA_PAGE11_LOCK0_ROW _u(0x00000f96) -#define OTP_DATA_PAGE11_LOCK0_BITS _u(0x00ffff7f) -#define OTP_DATA_PAGE11_LOCK0_RESET _u(0x00000000) -#define OTP_DATA_PAGE11_LOCK0_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE11_LOCK0_R2 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE11_LOCK0_R2_RESET "-" -#define OTP_DATA_PAGE11_LOCK0_R2_BITS _u(0x00ff0000) -#define OTP_DATA_PAGE11_LOCK0_R2_MSB _u(23) -#define OTP_DATA_PAGE11_LOCK0_R2_LSB _u(16) -#define OTP_DATA_PAGE11_LOCK0_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE11_LOCK0_R1 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE11_LOCK0_R1_RESET "-" -#define OTP_DATA_PAGE11_LOCK0_R1_BITS _u(0x0000ff00) -#define OTP_DATA_PAGE11_LOCK0_R1_MSB _u(15) -#define OTP_DATA_PAGE11_LOCK0_R1_LSB _u(8) -#define OTP_DATA_PAGE11_LOCK0_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE11_LOCK0_NO_KEY_STATE -// Description : State when at least one key is registered for this page and no -// matching key has been entered. -// 0x0 -> read_only -// 0x1 -> inaccessible -#define OTP_DATA_PAGE11_LOCK0_NO_KEY_STATE_RESET "-" -#define OTP_DATA_PAGE11_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) -#define OTP_DATA_PAGE11_LOCK0_NO_KEY_STATE_MSB _u(6) -#define OTP_DATA_PAGE11_LOCK0_NO_KEY_STATE_LSB _u(6) -#define OTP_DATA_PAGE11_LOCK0_NO_KEY_STATE_ACCESS "RO" -#define OTP_DATA_PAGE11_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) -#define OTP_DATA_PAGE11_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE11_LOCK0_KEY_R -// Description : Index 1-6 of a hardware key which must be entered to grant read -// access, or 0 if no such key is required. -#define OTP_DATA_PAGE11_LOCK0_KEY_R_RESET "-" -#define OTP_DATA_PAGE11_LOCK0_KEY_R_BITS _u(0x00000038) -#define OTP_DATA_PAGE11_LOCK0_KEY_R_MSB _u(5) -#define OTP_DATA_PAGE11_LOCK0_KEY_R_LSB _u(3) -#define OTP_DATA_PAGE11_LOCK0_KEY_R_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE11_LOCK0_KEY_W -// Description : Index 1-6 of a hardware key which must be entered to grant -// write access, or 0 if no such key is required. -#define OTP_DATA_PAGE11_LOCK0_KEY_W_RESET "-" -#define OTP_DATA_PAGE11_LOCK0_KEY_W_BITS _u(0x00000007) -#define OTP_DATA_PAGE11_LOCK0_KEY_W_MSB _u(2) -#define OTP_DATA_PAGE11_LOCK0_KEY_W_LSB _u(0) -#define OTP_DATA_PAGE11_LOCK0_KEY_W_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_PAGE11_LOCK1 -// Description : Lock configuration MSBs for page 11 (rows 0x2c0 through 0x2ff). -// Locks are stored with 3-way majority vote encoding, so that -// bits can be set independently. -// -// This OTP location is always readable, and is write-protected by -// its own permissions. -#define OTP_DATA_PAGE11_LOCK1_ROW _u(0x00000f97) -#define OTP_DATA_PAGE11_LOCK1_BITS _u(0x00ffff3f) -#define OTP_DATA_PAGE11_LOCK1_RESET _u(0x00000000) -#define OTP_DATA_PAGE11_LOCK1_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE11_LOCK1_R2 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE11_LOCK1_R2_RESET "-" -#define OTP_DATA_PAGE11_LOCK1_R2_BITS _u(0x00ff0000) -#define OTP_DATA_PAGE11_LOCK1_R2_MSB _u(23) -#define OTP_DATA_PAGE11_LOCK1_R2_LSB _u(16) -#define OTP_DATA_PAGE11_LOCK1_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE11_LOCK1_R1 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE11_LOCK1_R1_RESET "-" -#define OTP_DATA_PAGE11_LOCK1_R1_BITS _u(0x0000ff00) -#define OTP_DATA_PAGE11_LOCK1_R1_MSB _u(15) -#define OTP_DATA_PAGE11_LOCK1_R1_LSB _u(8) -#define OTP_DATA_PAGE11_LOCK1_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE11_LOCK1_LOCK_BL -// Description : Dummy lock bits reserved for bootloaders (including the RP2350 -// USB bootloader) to store their own OTP access permissions. No -// hardware effect, and no corresponding SW_LOCKx registers. -// 0x0 -> Bootloader permits user reads and writes to this page -// 0x1 -> Bootloader permits user reads of this page -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE -// 0x3 -> Bootloader does not permit user access to this page -#define OTP_DATA_PAGE11_LOCK1_LOCK_BL_RESET "-" -#define OTP_DATA_PAGE11_LOCK1_LOCK_BL_BITS _u(0x00000030) -#define OTP_DATA_PAGE11_LOCK1_LOCK_BL_MSB _u(5) -#define OTP_DATA_PAGE11_LOCK1_LOCK_BL_LSB _u(4) -#define OTP_DATA_PAGE11_LOCK1_LOCK_BL_ACCESS "RO" -#define OTP_DATA_PAGE11_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE11_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE11_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE11_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE11_LOCK1_LOCK_NS -// Description : Lock state for Non-secure accesses to this page. Thermometer- -// coded, so lock state can be advanced permanently from any state -// to any less-permissive state by programming OTP. Software can -// also advance the lock state temporarily (until next OTP reset) -// using the SW_LOCKx registers. -// -// Note that READ_WRITE and READ_ONLY are equivalent in hardware, -// as the SBPI programming interface is not accessible to Non- -// secure software. However, Secure software may check these bits -// to apply write permissions to a Non-secure OTP programming API. -// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. -// 0x1 -> Page can be read by Non-secure software -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. -// 0x3 -> Page can not be accessed by Non-secure software. -#define OTP_DATA_PAGE11_LOCK1_LOCK_NS_RESET "-" -#define OTP_DATA_PAGE11_LOCK1_LOCK_NS_BITS _u(0x0000000c) -#define OTP_DATA_PAGE11_LOCK1_LOCK_NS_MSB _u(3) -#define OTP_DATA_PAGE11_LOCK1_LOCK_NS_LSB _u(2) -#define OTP_DATA_PAGE11_LOCK1_LOCK_NS_ACCESS "RO" -#define OTP_DATA_PAGE11_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE11_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE11_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE11_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE11_LOCK1_LOCK_S -// Description : Lock state for Secure accesses to this page. Thermometer-coded, -// so lock state can be advanced permanently from any state to any -// less-permissive state by programming OTP. Software can also -// advance the lock state temporarily (until next OTP reset) using -// the SW_LOCKx registers. -// 0x0 -> Page is fully accessible by Secure software. -// 0x1 -> Page can be read by Secure software, but can not be written. -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. -// 0x3 -> Page can not be accessed by Secure software. -#define OTP_DATA_PAGE11_LOCK1_LOCK_S_RESET "-" -#define OTP_DATA_PAGE11_LOCK1_LOCK_S_BITS _u(0x00000003) -#define OTP_DATA_PAGE11_LOCK1_LOCK_S_MSB _u(1) -#define OTP_DATA_PAGE11_LOCK1_LOCK_S_LSB _u(0) -#define OTP_DATA_PAGE11_LOCK1_LOCK_S_ACCESS "RO" -#define OTP_DATA_PAGE11_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE11_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE11_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE11_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) -// ============================================================================= -// Register : OTP_DATA_PAGE12_LOCK0 -// Description : Lock configuration LSBs for page 12 (rows 0x300 through 0x33f). -// Locks are stored with 3-way majority vote encoding, so that -// bits can be set independently. -// -// This OTP location is always readable, and is write-protected by -// its own permissions. -#define OTP_DATA_PAGE12_LOCK0_ROW _u(0x00000f98) -#define OTP_DATA_PAGE12_LOCK0_BITS _u(0x00ffff7f) -#define OTP_DATA_PAGE12_LOCK0_RESET _u(0x00000000) -#define OTP_DATA_PAGE12_LOCK0_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE12_LOCK0_R2 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE12_LOCK0_R2_RESET "-" -#define OTP_DATA_PAGE12_LOCK0_R2_BITS _u(0x00ff0000) -#define OTP_DATA_PAGE12_LOCK0_R2_MSB _u(23) -#define OTP_DATA_PAGE12_LOCK0_R2_LSB _u(16) -#define OTP_DATA_PAGE12_LOCK0_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE12_LOCK0_R1 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE12_LOCK0_R1_RESET "-" -#define OTP_DATA_PAGE12_LOCK0_R1_BITS _u(0x0000ff00) -#define OTP_DATA_PAGE12_LOCK0_R1_MSB _u(15) -#define OTP_DATA_PAGE12_LOCK0_R1_LSB _u(8) -#define OTP_DATA_PAGE12_LOCK0_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE12_LOCK0_NO_KEY_STATE -// Description : State when at least one key is registered for this page and no -// matching key has been entered. -// 0x0 -> read_only -// 0x1 -> inaccessible -#define OTP_DATA_PAGE12_LOCK0_NO_KEY_STATE_RESET "-" -#define OTP_DATA_PAGE12_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) -#define OTP_DATA_PAGE12_LOCK0_NO_KEY_STATE_MSB _u(6) -#define OTP_DATA_PAGE12_LOCK0_NO_KEY_STATE_LSB _u(6) -#define OTP_DATA_PAGE12_LOCK0_NO_KEY_STATE_ACCESS "RO" -#define OTP_DATA_PAGE12_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) -#define OTP_DATA_PAGE12_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE12_LOCK0_KEY_R -// Description : Index 1-6 of a hardware key which must be entered to grant read -// access, or 0 if no such key is required. -#define OTP_DATA_PAGE12_LOCK0_KEY_R_RESET "-" -#define OTP_DATA_PAGE12_LOCK0_KEY_R_BITS _u(0x00000038) -#define OTP_DATA_PAGE12_LOCK0_KEY_R_MSB _u(5) -#define OTP_DATA_PAGE12_LOCK0_KEY_R_LSB _u(3) -#define OTP_DATA_PAGE12_LOCK0_KEY_R_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE12_LOCK0_KEY_W -// Description : Index 1-6 of a hardware key which must be entered to grant -// write access, or 0 if no such key is required. -#define OTP_DATA_PAGE12_LOCK0_KEY_W_RESET "-" -#define OTP_DATA_PAGE12_LOCK0_KEY_W_BITS _u(0x00000007) -#define OTP_DATA_PAGE12_LOCK0_KEY_W_MSB _u(2) -#define OTP_DATA_PAGE12_LOCK0_KEY_W_LSB _u(0) -#define OTP_DATA_PAGE12_LOCK0_KEY_W_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_PAGE12_LOCK1 -// Description : Lock configuration MSBs for page 12 (rows 0x300 through 0x33f). -// Locks are stored with 3-way majority vote encoding, so that -// bits can be set independently. -// -// This OTP location is always readable, and is write-protected by -// its own permissions. -#define OTP_DATA_PAGE12_LOCK1_ROW _u(0x00000f99) -#define OTP_DATA_PAGE12_LOCK1_BITS _u(0x00ffff3f) -#define OTP_DATA_PAGE12_LOCK1_RESET _u(0x00000000) -#define OTP_DATA_PAGE12_LOCK1_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE12_LOCK1_R2 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE12_LOCK1_R2_RESET "-" -#define OTP_DATA_PAGE12_LOCK1_R2_BITS _u(0x00ff0000) -#define OTP_DATA_PAGE12_LOCK1_R2_MSB _u(23) -#define OTP_DATA_PAGE12_LOCK1_R2_LSB _u(16) -#define OTP_DATA_PAGE12_LOCK1_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE12_LOCK1_R1 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE12_LOCK1_R1_RESET "-" -#define OTP_DATA_PAGE12_LOCK1_R1_BITS _u(0x0000ff00) -#define OTP_DATA_PAGE12_LOCK1_R1_MSB _u(15) -#define OTP_DATA_PAGE12_LOCK1_R1_LSB _u(8) -#define OTP_DATA_PAGE12_LOCK1_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE12_LOCK1_LOCK_BL -// Description : Dummy lock bits reserved for bootloaders (including the RP2350 -// USB bootloader) to store their own OTP access permissions. No -// hardware effect, and no corresponding SW_LOCKx registers. -// 0x0 -> Bootloader permits user reads and writes to this page -// 0x1 -> Bootloader permits user reads of this page -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE -// 0x3 -> Bootloader does not permit user access to this page -#define OTP_DATA_PAGE12_LOCK1_LOCK_BL_RESET "-" -#define OTP_DATA_PAGE12_LOCK1_LOCK_BL_BITS _u(0x00000030) -#define OTP_DATA_PAGE12_LOCK1_LOCK_BL_MSB _u(5) -#define OTP_DATA_PAGE12_LOCK1_LOCK_BL_LSB _u(4) -#define OTP_DATA_PAGE12_LOCK1_LOCK_BL_ACCESS "RO" -#define OTP_DATA_PAGE12_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE12_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE12_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE12_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE12_LOCK1_LOCK_NS -// Description : Lock state for Non-secure accesses to this page. Thermometer- -// coded, so lock state can be advanced permanently from any state -// to any less-permissive state by programming OTP. Software can -// also advance the lock state temporarily (until next OTP reset) -// using the SW_LOCKx registers. -// -// Note that READ_WRITE and READ_ONLY are equivalent in hardware, -// as the SBPI programming interface is not accessible to Non- -// secure software. However, Secure software may check these bits -// to apply write permissions to a Non-secure OTP programming API. -// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. -// 0x1 -> Page can be read by Non-secure software -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. -// 0x3 -> Page can not be accessed by Non-secure software. -#define OTP_DATA_PAGE12_LOCK1_LOCK_NS_RESET "-" -#define OTP_DATA_PAGE12_LOCK1_LOCK_NS_BITS _u(0x0000000c) -#define OTP_DATA_PAGE12_LOCK1_LOCK_NS_MSB _u(3) -#define OTP_DATA_PAGE12_LOCK1_LOCK_NS_LSB _u(2) -#define OTP_DATA_PAGE12_LOCK1_LOCK_NS_ACCESS "RO" -#define OTP_DATA_PAGE12_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE12_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE12_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE12_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE12_LOCK1_LOCK_S -// Description : Lock state for Secure accesses to this page. Thermometer-coded, -// so lock state can be advanced permanently from any state to any -// less-permissive state by programming OTP. Software can also -// advance the lock state temporarily (until next OTP reset) using -// the SW_LOCKx registers. -// 0x0 -> Page is fully accessible by Secure software. -// 0x1 -> Page can be read by Secure software, but can not be written. -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. -// 0x3 -> Page can not be accessed by Secure software. -#define OTP_DATA_PAGE12_LOCK1_LOCK_S_RESET "-" -#define OTP_DATA_PAGE12_LOCK1_LOCK_S_BITS _u(0x00000003) -#define OTP_DATA_PAGE12_LOCK1_LOCK_S_MSB _u(1) -#define OTP_DATA_PAGE12_LOCK1_LOCK_S_LSB _u(0) -#define OTP_DATA_PAGE12_LOCK1_LOCK_S_ACCESS "RO" -#define OTP_DATA_PAGE12_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE12_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE12_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE12_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) -// ============================================================================= -// Register : OTP_DATA_PAGE13_LOCK0 -// Description : Lock configuration LSBs for page 13 (rows 0x340 through 0x37f). -// Locks are stored with 3-way majority vote encoding, so that -// bits can be set independently. -// -// This OTP location is always readable, and is write-protected by -// its own permissions. -#define OTP_DATA_PAGE13_LOCK0_ROW _u(0x00000f9a) -#define OTP_DATA_PAGE13_LOCK0_BITS _u(0x00ffff7f) -#define OTP_DATA_PAGE13_LOCK0_RESET _u(0x00000000) -#define OTP_DATA_PAGE13_LOCK0_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE13_LOCK0_R2 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE13_LOCK0_R2_RESET "-" -#define OTP_DATA_PAGE13_LOCK0_R2_BITS _u(0x00ff0000) -#define OTP_DATA_PAGE13_LOCK0_R2_MSB _u(23) -#define OTP_DATA_PAGE13_LOCK0_R2_LSB _u(16) -#define OTP_DATA_PAGE13_LOCK0_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE13_LOCK0_R1 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE13_LOCK0_R1_RESET "-" -#define OTP_DATA_PAGE13_LOCK0_R1_BITS _u(0x0000ff00) -#define OTP_DATA_PAGE13_LOCK0_R1_MSB _u(15) -#define OTP_DATA_PAGE13_LOCK0_R1_LSB _u(8) -#define OTP_DATA_PAGE13_LOCK0_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE13_LOCK0_NO_KEY_STATE -// Description : State when at least one key is registered for this page and no -// matching key has been entered. -// 0x0 -> read_only -// 0x1 -> inaccessible -#define OTP_DATA_PAGE13_LOCK0_NO_KEY_STATE_RESET "-" -#define OTP_DATA_PAGE13_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) -#define OTP_DATA_PAGE13_LOCK0_NO_KEY_STATE_MSB _u(6) -#define OTP_DATA_PAGE13_LOCK0_NO_KEY_STATE_LSB _u(6) -#define OTP_DATA_PAGE13_LOCK0_NO_KEY_STATE_ACCESS "RO" -#define OTP_DATA_PAGE13_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) -#define OTP_DATA_PAGE13_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE13_LOCK0_KEY_R -// Description : Index 1-6 of a hardware key which must be entered to grant read -// access, or 0 if no such key is required. -#define OTP_DATA_PAGE13_LOCK0_KEY_R_RESET "-" -#define OTP_DATA_PAGE13_LOCK0_KEY_R_BITS _u(0x00000038) -#define OTP_DATA_PAGE13_LOCK0_KEY_R_MSB _u(5) -#define OTP_DATA_PAGE13_LOCK0_KEY_R_LSB _u(3) -#define OTP_DATA_PAGE13_LOCK0_KEY_R_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE13_LOCK0_KEY_W -// Description : Index 1-6 of a hardware key which must be entered to grant -// write access, or 0 if no such key is required. -#define OTP_DATA_PAGE13_LOCK0_KEY_W_RESET "-" -#define OTP_DATA_PAGE13_LOCK0_KEY_W_BITS _u(0x00000007) -#define OTP_DATA_PAGE13_LOCK0_KEY_W_MSB _u(2) -#define OTP_DATA_PAGE13_LOCK0_KEY_W_LSB _u(0) -#define OTP_DATA_PAGE13_LOCK0_KEY_W_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_PAGE13_LOCK1 -// Description : Lock configuration MSBs for page 13 (rows 0x340 through 0x37f). -// Locks are stored with 3-way majority vote encoding, so that -// bits can be set independently. -// -// This OTP location is always readable, and is write-protected by -// its own permissions. -#define OTP_DATA_PAGE13_LOCK1_ROW _u(0x00000f9b) -#define OTP_DATA_PAGE13_LOCK1_BITS _u(0x00ffff3f) -#define OTP_DATA_PAGE13_LOCK1_RESET _u(0x00000000) -#define OTP_DATA_PAGE13_LOCK1_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE13_LOCK1_R2 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE13_LOCK1_R2_RESET "-" -#define OTP_DATA_PAGE13_LOCK1_R2_BITS _u(0x00ff0000) -#define OTP_DATA_PAGE13_LOCK1_R2_MSB _u(23) -#define OTP_DATA_PAGE13_LOCK1_R2_LSB _u(16) -#define OTP_DATA_PAGE13_LOCK1_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE13_LOCK1_R1 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE13_LOCK1_R1_RESET "-" -#define OTP_DATA_PAGE13_LOCK1_R1_BITS _u(0x0000ff00) -#define OTP_DATA_PAGE13_LOCK1_R1_MSB _u(15) -#define OTP_DATA_PAGE13_LOCK1_R1_LSB _u(8) -#define OTP_DATA_PAGE13_LOCK1_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE13_LOCK1_LOCK_BL -// Description : Dummy lock bits reserved for bootloaders (including the RP2350 -// USB bootloader) to store their own OTP access permissions. No -// hardware effect, and no corresponding SW_LOCKx registers. -// 0x0 -> Bootloader permits user reads and writes to this page -// 0x1 -> Bootloader permits user reads of this page -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE -// 0x3 -> Bootloader does not permit user access to this page -#define OTP_DATA_PAGE13_LOCK1_LOCK_BL_RESET "-" -#define OTP_DATA_PAGE13_LOCK1_LOCK_BL_BITS _u(0x00000030) -#define OTP_DATA_PAGE13_LOCK1_LOCK_BL_MSB _u(5) -#define OTP_DATA_PAGE13_LOCK1_LOCK_BL_LSB _u(4) -#define OTP_DATA_PAGE13_LOCK1_LOCK_BL_ACCESS "RO" -#define OTP_DATA_PAGE13_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE13_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE13_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE13_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE13_LOCK1_LOCK_NS -// Description : Lock state for Non-secure accesses to this page. Thermometer- -// coded, so lock state can be advanced permanently from any state -// to any less-permissive state by programming OTP. Software can -// also advance the lock state temporarily (until next OTP reset) -// using the SW_LOCKx registers. -// -// Note that READ_WRITE and READ_ONLY are equivalent in hardware, -// as the SBPI programming interface is not accessible to Non- -// secure software. However, Secure software may check these bits -// to apply write permissions to a Non-secure OTP programming API. -// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. -// 0x1 -> Page can be read by Non-secure software -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. -// 0x3 -> Page can not be accessed by Non-secure software. -#define OTP_DATA_PAGE13_LOCK1_LOCK_NS_RESET "-" -#define OTP_DATA_PAGE13_LOCK1_LOCK_NS_BITS _u(0x0000000c) -#define OTP_DATA_PAGE13_LOCK1_LOCK_NS_MSB _u(3) -#define OTP_DATA_PAGE13_LOCK1_LOCK_NS_LSB _u(2) -#define OTP_DATA_PAGE13_LOCK1_LOCK_NS_ACCESS "RO" -#define OTP_DATA_PAGE13_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE13_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE13_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE13_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE13_LOCK1_LOCK_S -// Description : Lock state for Secure accesses to this page. Thermometer-coded, -// so lock state can be advanced permanently from any state to any -// less-permissive state by programming OTP. Software can also -// advance the lock state temporarily (until next OTP reset) using -// the SW_LOCKx registers. -// 0x0 -> Page is fully accessible by Secure software. -// 0x1 -> Page can be read by Secure software, but can not be written. -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. -// 0x3 -> Page can not be accessed by Secure software. -#define OTP_DATA_PAGE13_LOCK1_LOCK_S_RESET "-" -#define OTP_DATA_PAGE13_LOCK1_LOCK_S_BITS _u(0x00000003) -#define OTP_DATA_PAGE13_LOCK1_LOCK_S_MSB _u(1) -#define OTP_DATA_PAGE13_LOCK1_LOCK_S_LSB _u(0) -#define OTP_DATA_PAGE13_LOCK1_LOCK_S_ACCESS "RO" -#define OTP_DATA_PAGE13_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE13_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE13_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE13_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) -// ============================================================================= -// Register : OTP_DATA_PAGE14_LOCK0 -// Description : Lock configuration LSBs for page 14 (rows 0x380 through 0x3bf). -// Locks are stored with 3-way majority vote encoding, so that -// bits can be set independently. -// -// This OTP location is always readable, and is write-protected by -// its own permissions. -#define OTP_DATA_PAGE14_LOCK0_ROW _u(0x00000f9c) -#define OTP_DATA_PAGE14_LOCK0_BITS _u(0x00ffff7f) -#define OTP_DATA_PAGE14_LOCK0_RESET _u(0x00000000) -#define OTP_DATA_PAGE14_LOCK0_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE14_LOCK0_R2 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE14_LOCK0_R2_RESET "-" -#define OTP_DATA_PAGE14_LOCK0_R2_BITS _u(0x00ff0000) -#define OTP_DATA_PAGE14_LOCK0_R2_MSB _u(23) -#define OTP_DATA_PAGE14_LOCK0_R2_LSB _u(16) -#define OTP_DATA_PAGE14_LOCK0_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE14_LOCK0_R1 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE14_LOCK0_R1_RESET "-" -#define OTP_DATA_PAGE14_LOCK0_R1_BITS _u(0x0000ff00) -#define OTP_DATA_PAGE14_LOCK0_R1_MSB _u(15) -#define OTP_DATA_PAGE14_LOCK0_R1_LSB _u(8) -#define OTP_DATA_PAGE14_LOCK0_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE14_LOCK0_NO_KEY_STATE -// Description : State when at least one key is registered for this page and no -// matching key has been entered. -// 0x0 -> read_only -// 0x1 -> inaccessible -#define OTP_DATA_PAGE14_LOCK0_NO_KEY_STATE_RESET "-" -#define OTP_DATA_PAGE14_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) -#define OTP_DATA_PAGE14_LOCK0_NO_KEY_STATE_MSB _u(6) -#define OTP_DATA_PAGE14_LOCK0_NO_KEY_STATE_LSB _u(6) -#define OTP_DATA_PAGE14_LOCK0_NO_KEY_STATE_ACCESS "RO" -#define OTP_DATA_PAGE14_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) -#define OTP_DATA_PAGE14_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE14_LOCK0_KEY_R -// Description : Index 1-6 of a hardware key which must be entered to grant read -// access, or 0 if no such key is required. -#define OTP_DATA_PAGE14_LOCK0_KEY_R_RESET "-" -#define OTP_DATA_PAGE14_LOCK0_KEY_R_BITS _u(0x00000038) -#define OTP_DATA_PAGE14_LOCK0_KEY_R_MSB _u(5) -#define OTP_DATA_PAGE14_LOCK0_KEY_R_LSB _u(3) -#define OTP_DATA_PAGE14_LOCK0_KEY_R_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE14_LOCK0_KEY_W -// Description : Index 1-6 of a hardware key which must be entered to grant -// write access, or 0 if no such key is required. -#define OTP_DATA_PAGE14_LOCK0_KEY_W_RESET "-" -#define OTP_DATA_PAGE14_LOCK0_KEY_W_BITS _u(0x00000007) -#define OTP_DATA_PAGE14_LOCK0_KEY_W_MSB _u(2) -#define OTP_DATA_PAGE14_LOCK0_KEY_W_LSB _u(0) -#define OTP_DATA_PAGE14_LOCK0_KEY_W_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_PAGE14_LOCK1 -// Description : Lock configuration MSBs for page 14 (rows 0x380 through 0x3bf). -// Locks are stored with 3-way majority vote encoding, so that -// bits can be set independently. -// -// This OTP location is always readable, and is write-protected by -// its own permissions. -#define OTP_DATA_PAGE14_LOCK1_ROW _u(0x00000f9d) -#define OTP_DATA_PAGE14_LOCK1_BITS _u(0x00ffff3f) -#define OTP_DATA_PAGE14_LOCK1_RESET _u(0x00000000) -#define OTP_DATA_PAGE14_LOCK1_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE14_LOCK1_R2 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE14_LOCK1_R2_RESET "-" -#define OTP_DATA_PAGE14_LOCK1_R2_BITS _u(0x00ff0000) -#define OTP_DATA_PAGE14_LOCK1_R2_MSB _u(23) -#define OTP_DATA_PAGE14_LOCK1_R2_LSB _u(16) -#define OTP_DATA_PAGE14_LOCK1_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE14_LOCK1_R1 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE14_LOCK1_R1_RESET "-" -#define OTP_DATA_PAGE14_LOCK1_R1_BITS _u(0x0000ff00) -#define OTP_DATA_PAGE14_LOCK1_R1_MSB _u(15) -#define OTP_DATA_PAGE14_LOCK1_R1_LSB _u(8) -#define OTP_DATA_PAGE14_LOCK1_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE14_LOCK1_LOCK_BL -// Description : Dummy lock bits reserved for bootloaders (including the RP2350 -// USB bootloader) to store their own OTP access permissions. No -// hardware effect, and no corresponding SW_LOCKx registers. -// 0x0 -> Bootloader permits user reads and writes to this page -// 0x1 -> Bootloader permits user reads of this page -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE -// 0x3 -> Bootloader does not permit user access to this page -#define OTP_DATA_PAGE14_LOCK1_LOCK_BL_RESET "-" -#define OTP_DATA_PAGE14_LOCK1_LOCK_BL_BITS _u(0x00000030) -#define OTP_DATA_PAGE14_LOCK1_LOCK_BL_MSB _u(5) -#define OTP_DATA_PAGE14_LOCK1_LOCK_BL_LSB _u(4) -#define OTP_DATA_PAGE14_LOCK1_LOCK_BL_ACCESS "RO" -#define OTP_DATA_PAGE14_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE14_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE14_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE14_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE14_LOCK1_LOCK_NS -// Description : Lock state for Non-secure accesses to this page. Thermometer- -// coded, so lock state can be advanced permanently from any state -// to any less-permissive state by programming OTP. Software can -// also advance the lock state temporarily (until next OTP reset) -// using the SW_LOCKx registers. -// -// Note that READ_WRITE and READ_ONLY are equivalent in hardware, -// as the SBPI programming interface is not accessible to Non- -// secure software. However, Secure software may check these bits -// to apply write permissions to a Non-secure OTP programming API. -// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. -// 0x1 -> Page can be read by Non-secure software -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. -// 0x3 -> Page can not be accessed by Non-secure software. -#define OTP_DATA_PAGE14_LOCK1_LOCK_NS_RESET "-" -#define OTP_DATA_PAGE14_LOCK1_LOCK_NS_BITS _u(0x0000000c) -#define OTP_DATA_PAGE14_LOCK1_LOCK_NS_MSB _u(3) -#define OTP_DATA_PAGE14_LOCK1_LOCK_NS_LSB _u(2) -#define OTP_DATA_PAGE14_LOCK1_LOCK_NS_ACCESS "RO" -#define OTP_DATA_PAGE14_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE14_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE14_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE14_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE14_LOCK1_LOCK_S -// Description : Lock state for Secure accesses to this page. Thermometer-coded, -// so lock state can be advanced permanently from any state to any -// less-permissive state by programming OTP. Software can also -// advance the lock state temporarily (until next OTP reset) using -// the SW_LOCKx registers. -// 0x0 -> Page is fully accessible by Secure software. -// 0x1 -> Page can be read by Secure software, but can not be written. -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. -// 0x3 -> Page can not be accessed by Secure software. -#define OTP_DATA_PAGE14_LOCK1_LOCK_S_RESET "-" -#define OTP_DATA_PAGE14_LOCK1_LOCK_S_BITS _u(0x00000003) -#define OTP_DATA_PAGE14_LOCK1_LOCK_S_MSB _u(1) -#define OTP_DATA_PAGE14_LOCK1_LOCK_S_LSB _u(0) -#define OTP_DATA_PAGE14_LOCK1_LOCK_S_ACCESS "RO" -#define OTP_DATA_PAGE14_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE14_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE14_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE14_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) -// ============================================================================= -// Register : OTP_DATA_PAGE15_LOCK0 -// Description : Lock configuration LSBs for page 15 (rows 0x3c0 through 0x3ff). -// Locks are stored with 3-way majority vote encoding, so that -// bits can be set independently. -// -// This OTP location is always readable, and is write-protected by -// its own permissions. -#define OTP_DATA_PAGE15_LOCK0_ROW _u(0x00000f9e) -#define OTP_DATA_PAGE15_LOCK0_BITS _u(0x00ffff7f) -#define OTP_DATA_PAGE15_LOCK0_RESET _u(0x00000000) -#define OTP_DATA_PAGE15_LOCK0_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE15_LOCK0_R2 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE15_LOCK0_R2_RESET "-" -#define OTP_DATA_PAGE15_LOCK0_R2_BITS _u(0x00ff0000) -#define OTP_DATA_PAGE15_LOCK0_R2_MSB _u(23) -#define OTP_DATA_PAGE15_LOCK0_R2_LSB _u(16) -#define OTP_DATA_PAGE15_LOCK0_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE15_LOCK0_R1 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE15_LOCK0_R1_RESET "-" -#define OTP_DATA_PAGE15_LOCK0_R1_BITS _u(0x0000ff00) -#define OTP_DATA_PAGE15_LOCK0_R1_MSB _u(15) -#define OTP_DATA_PAGE15_LOCK0_R1_LSB _u(8) -#define OTP_DATA_PAGE15_LOCK0_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE15_LOCK0_NO_KEY_STATE -// Description : State when at least one key is registered for this page and no -// matching key has been entered. -// 0x0 -> read_only -// 0x1 -> inaccessible -#define OTP_DATA_PAGE15_LOCK0_NO_KEY_STATE_RESET "-" -#define OTP_DATA_PAGE15_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) -#define OTP_DATA_PAGE15_LOCK0_NO_KEY_STATE_MSB _u(6) -#define OTP_DATA_PAGE15_LOCK0_NO_KEY_STATE_LSB _u(6) -#define OTP_DATA_PAGE15_LOCK0_NO_KEY_STATE_ACCESS "RO" -#define OTP_DATA_PAGE15_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) -#define OTP_DATA_PAGE15_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE15_LOCK0_KEY_R -// Description : Index 1-6 of a hardware key which must be entered to grant read -// access, or 0 if no such key is required. -#define OTP_DATA_PAGE15_LOCK0_KEY_R_RESET "-" -#define OTP_DATA_PAGE15_LOCK0_KEY_R_BITS _u(0x00000038) -#define OTP_DATA_PAGE15_LOCK0_KEY_R_MSB _u(5) -#define OTP_DATA_PAGE15_LOCK0_KEY_R_LSB _u(3) -#define OTP_DATA_PAGE15_LOCK0_KEY_R_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE15_LOCK0_KEY_W -// Description : Index 1-6 of a hardware key which must be entered to grant -// write access, or 0 if no such key is required. -#define OTP_DATA_PAGE15_LOCK0_KEY_W_RESET "-" -#define OTP_DATA_PAGE15_LOCK0_KEY_W_BITS _u(0x00000007) -#define OTP_DATA_PAGE15_LOCK0_KEY_W_MSB _u(2) -#define OTP_DATA_PAGE15_LOCK0_KEY_W_LSB _u(0) -#define OTP_DATA_PAGE15_LOCK0_KEY_W_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_PAGE15_LOCK1 -// Description : Lock configuration MSBs for page 15 (rows 0x3c0 through 0x3ff). -// Locks are stored with 3-way majority vote encoding, so that -// bits can be set independently. -// -// This OTP location is always readable, and is write-protected by -// its own permissions. -#define OTP_DATA_PAGE15_LOCK1_ROW _u(0x00000f9f) -#define OTP_DATA_PAGE15_LOCK1_BITS _u(0x00ffff3f) -#define OTP_DATA_PAGE15_LOCK1_RESET _u(0x00000000) -#define OTP_DATA_PAGE15_LOCK1_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE15_LOCK1_R2 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE15_LOCK1_R2_RESET "-" -#define OTP_DATA_PAGE15_LOCK1_R2_BITS _u(0x00ff0000) -#define OTP_DATA_PAGE15_LOCK1_R2_MSB _u(23) -#define OTP_DATA_PAGE15_LOCK1_R2_LSB _u(16) -#define OTP_DATA_PAGE15_LOCK1_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE15_LOCK1_R1 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE15_LOCK1_R1_RESET "-" -#define OTP_DATA_PAGE15_LOCK1_R1_BITS _u(0x0000ff00) -#define OTP_DATA_PAGE15_LOCK1_R1_MSB _u(15) -#define OTP_DATA_PAGE15_LOCK1_R1_LSB _u(8) -#define OTP_DATA_PAGE15_LOCK1_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE15_LOCK1_LOCK_BL -// Description : Dummy lock bits reserved for bootloaders (including the RP2350 -// USB bootloader) to store their own OTP access permissions. No -// hardware effect, and no corresponding SW_LOCKx registers. -// 0x0 -> Bootloader permits user reads and writes to this page -// 0x1 -> Bootloader permits user reads of this page -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE -// 0x3 -> Bootloader does not permit user access to this page -#define OTP_DATA_PAGE15_LOCK1_LOCK_BL_RESET "-" -#define OTP_DATA_PAGE15_LOCK1_LOCK_BL_BITS _u(0x00000030) -#define OTP_DATA_PAGE15_LOCK1_LOCK_BL_MSB _u(5) -#define OTP_DATA_PAGE15_LOCK1_LOCK_BL_LSB _u(4) -#define OTP_DATA_PAGE15_LOCK1_LOCK_BL_ACCESS "RO" -#define OTP_DATA_PAGE15_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE15_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE15_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE15_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE15_LOCK1_LOCK_NS -// Description : Lock state for Non-secure accesses to this page. Thermometer- -// coded, so lock state can be advanced permanently from any state -// to any less-permissive state by programming OTP. Software can -// also advance the lock state temporarily (until next OTP reset) -// using the SW_LOCKx registers. -// -// Note that READ_WRITE and READ_ONLY are equivalent in hardware, -// as the SBPI programming interface is not accessible to Non- -// secure software. However, Secure software may check these bits -// to apply write permissions to a Non-secure OTP programming API. -// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. -// 0x1 -> Page can be read by Non-secure software -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. -// 0x3 -> Page can not be accessed by Non-secure software. -#define OTP_DATA_PAGE15_LOCK1_LOCK_NS_RESET "-" -#define OTP_DATA_PAGE15_LOCK1_LOCK_NS_BITS _u(0x0000000c) -#define OTP_DATA_PAGE15_LOCK1_LOCK_NS_MSB _u(3) -#define OTP_DATA_PAGE15_LOCK1_LOCK_NS_LSB _u(2) -#define OTP_DATA_PAGE15_LOCK1_LOCK_NS_ACCESS "RO" -#define OTP_DATA_PAGE15_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE15_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE15_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE15_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE15_LOCK1_LOCK_S -// Description : Lock state for Secure accesses to this page. Thermometer-coded, -// so lock state can be advanced permanently from any state to any -// less-permissive state by programming OTP. Software can also -// advance the lock state temporarily (until next OTP reset) using -// the SW_LOCKx registers. -// 0x0 -> Page is fully accessible by Secure software. -// 0x1 -> Page can be read by Secure software, but can not be written. -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. -// 0x3 -> Page can not be accessed by Secure software. -#define OTP_DATA_PAGE15_LOCK1_LOCK_S_RESET "-" -#define OTP_DATA_PAGE15_LOCK1_LOCK_S_BITS _u(0x00000003) -#define OTP_DATA_PAGE15_LOCK1_LOCK_S_MSB _u(1) -#define OTP_DATA_PAGE15_LOCK1_LOCK_S_LSB _u(0) -#define OTP_DATA_PAGE15_LOCK1_LOCK_S_ACCESS "RO" -#define OTP_DATA_PAGE15_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE15_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE15_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE15_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) -// ============================================================================= -// Register : OTP_DATA_PAGE16_LOCK0 -// Description : Lock configuration LSBs for page 16 (rows 0x400 through 0x43f). -// Locks are stored with 3-way majority vote encoding, so that -// bits can be set independently. -// -// This OTP location is always readable, and is write-protected by -// its own permissions. -#define OTP_DATA_PAGE16_LOCK0_ROW _u(0x00000fa0) -#define OTP_DATA_PAGE16_LOCK0_BITS _u(0x00ffff7f) -#define OTP_DATA_PAGE16_LOCK0_RESET _u(0x00000000) -#define OTP_DATA_PAGE16_LOCK0_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE16_LOCK0_R2 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE16_LOCK0_R2_RESET "-" -#define OTP_DATA_PAGE16_LOCK0_R2_BITS _u(0x00ff0000) -#define OTP_DATA_PAGE16_LOCK0_R2_MSB _u(23) -#define OTP_DATA_PAGE16_LOCK0_R2_LSB _u(16) -#define OTP_DATA_PAGE16_LOCK0_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE16_LOCK0_R1 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE16_LOCK0_R1_RESET "-" -#define OTP_DATA_PAGE16_LOCK0_R1_BITS _u(0x0000ff00) -#define OTP_DATA_PAGE16_LOCK0_R1_MSB _u(15) -#define OTP_DATA_PAGE16_LOCK0_R1_LSB _u(8) -#define OTP_DATA_PAGE16_LOCK0_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE16_LOCK0_NO_KEY_STATE -// Description : State when at least one key is registered for this page and no -// matching key has been entered. -// 0x0 -> read_only -// 0x1 -> inaccessible -#define OTP_DATA_PAGE16_LOCK0_NO_KEY_STATE_RESET "-" -#define OTP_DATA_PAGE16_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) -#define OTP_DATA_PAGE16_LOCK0_NO_KEY_STATE_MSB _u(6) -#define OTP_DATA_PAGE16_LOCK0_NO_KEY_STATE_LSB _u(6) -#define OTP_DATA_PAGE16_LOCK0_NO_KEY_STATE_ACCESS "RO" -#define OTP_DATA_PAGE16_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) -#define OTP_DATA_PAGE16_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE16_LOCK0_KEY_R -// Description : Index 1-6 of a hardware key which must be entered to grant read -// access, or 0 if no such key is required. -#define OTP_DATA_PAGE16_LOCK0_KEY_R_RESET "-" -#define OTP_DATA_PAGE16_LOCK0_KEY_R_BITS _u(0x00000038) -#define OTP_DATA_PAGE16_LOCK0_KEY_R_MSB _u(5) -#define OTP_DATA_PAGE16_LOCK0_KEY_R_LSB _u(3) -#define OTP_DATA_PAGE16_LOCK0_KEY_R_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE16_LOCK0_KEY_W -// Description : Index 1-6 of a hardware key which must be entered to grant -// write access, or 0 if no such key is required. -#define OTP_DATA_PAGE16_LOCK0_KEY_W_RESET "-" -#define OTP_DATA_PAGE16_LOCK0_KEY_W_BITS _u(0x00000007) -#define OTP_DATA_PAGE16_LOCK0_KEY_W_MSB _u(2) -#define OTP_DATA_PAGE16_LOCK0_KEY_W_LSB _u(0) -#define OTP_DATA_PAGE16_LOCK0_KEY_W_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_PAGE16_LOCK1 -// Description : Lock configuration MSBs for page 16 (rows 0x400 through 0x43f). -// Locks are stored with 3-way majority vote encoding, so that -// bits can be set independently. -// -// This OTP location is always readable, and is write-protected by -// its own permissions. -#define OTP_DATA_PAGE16_LOCK1_ROW _u(0x00000fa1) -#define OTP_DATA_PAGE16_LOCK1_BITS _u(0x00ffff3f) -#define OTP_DATA_PAGE16_LOCK1_RESET _u(0x00000000) -#define OTP_DATA_PAGE16_LOCK1_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE16_LOCK1_R2 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE16_LOCK1_R2_RESET "-" -#define OTP_DATA_PAGE16_LOCK1_R2_BITS _u(0x00ff0000) -#define OTP_DATA_PAGE16_LOCK1_R2_MSB _u(23) -#define OTP_DATA_PAGE16_LOCK1_R2_LSB _u(16) -#define OTP_DATA_PAGE16_LOCK1_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE16_LOCK1_R1 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE16_LOCK1_R1_RESET "-" -#define OTP_DATA_PAGE16_LOCK1_R1_BITS _u(0x0000ff00) -#define OTP_DATA_PAGE16_LOCK1_R1_MSB _u(15) -#define OTP_DATA_PAGE16_LOCK1_R1_LSB _u(8) -#define OTP_DATA_PAGE16_LOCK1_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE16_LOCK1_LOCK_BL -// Description : Dummy lock bits reserved for bootloaders (including the RP2350 -// USB bootloader) to store their own OTP access permissions. No -// hardware effect, and no corresponding SW_LOCKx registers. -// 0x0 -> Bootloader permits user reads and writes to this page -// 0x1 -> Bootloader permits user reads of this page -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE -// 0x3 -> Bootloader does not permit user access to this page -#define OTP_DATA_PAGE16_LOCK1_LOCK_BL_RESET "-" -#define OTP_DATA_PAGE16_LOCK1_LOCK_BL_BITS _u(0x00000030) -#define OTP_DATA_PAGE16_LOCK1_LOCK_BL_MSB _u(5) -#define OTP_DATA_PAGE16_LOCK1_LOCK_BL_LSB _u(4) -#define OTP_DATA_PAGE16_LOCK1_LOCK_BL_ACCESS "RO" -#define OTP_DATA_PAGE16_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE16_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE16_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE16_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE16_LOCK1_LOCK_NS -// Description : Lock state for Non-secure accesses to this page. Thermometer- -// coded, so lock state can be advanced permanently from any state -// to any less-permissive state by programming OTP. Software can -// also advance the lock state temporarily (until next OTP reset) -// using the SW_LOCKx registers. -// -// Note that READ_WRITE and READ_ONLY are equivalent in hardware, -// as the SBPI programming interface is not accessible to Non- -// secure software. However, Secure software may check these bits -// to apply write permissions to a Non-secure OTP programming API. -// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. -// 0x1 -> Page can be read by Non-secure software -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. -// 0x3 -> Page can not be accessed by Non-secure software. -#define OTP_DATA_PAGE16_LOCK1_LOCK_NS_RESET "-" -#define OTP_DATA_PAGE16_LOCK1_LOCK_NS_BITS _u(0x0000000c) -#define OTP_DATA_PAGE16_LOCK1_LOCK_NS_MSB _u(3) -#define OTP_DATA_PAGE16_LOCK1_LOCK_NS_LSB _u(2) -#define OTP_DATA_PAGE16_LOCK1_LOCK_NS_ACCESS "RO" -#define OTP_DATA_PAGE16_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE16_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE16_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE16_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE16_LOCK1_LOCK_S -// Description : Lock state for Secure accesses to this page. Thermometer-coded, -// so lock state can be advanced permanently from any state to any -// less-permissive state by programming OTP. Software can also -// advance the lock state temporarily (until next OTP reset) using -// the SW_LOCKx registers. -// 0x0 -> Page is fully accessible by Secure software. -// 0x1 -> Page can be read by Secure software, but can not be written. -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. -// 0x3 -> Page can not be accessed by Secure software. -#define OTP_DATA_PAGE16_LOCK1_LOCK_S_RESET "-" -#define OTP_DATA_PAGE16_LOCK1_LOCK_S_BITS _u(0x00000003) -#define OTP_DATA_PAGE16_LOCK1_LOCK_S_MSB _u(1) -#define OTP_DATA_PAGE16_LOCK1_LOCK_S_LSB _u(0) -#define OTP_DATA_PAGE16_LOCK1_LOCK_S_ACCESS "RO" -#define OTP_DATA_PAGE16_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE16_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE16_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE16_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) -// ============================================================================= -// Register : OTP_DATA_PAGE17_LOCK0 -// Description : Lock configuration LSBs for page 17 (rows 0x440 through 0x47f). -// Locks are stored with 3-way majority vote encoding, so that -// bits can be set independently. -// -// This OTP location is always readable, and is write-protected by -// its own permissions. -#define OTP_DATA_PAGE17_LOCK0_ROW _u(0x00000fa2) -#define OTP_DATA_PAGE17_LOCK0_BITS _u(0x00ffff7f) -#define OTP_DATA_PAGE17_LOCK0_RESET _u(0x00000000) -#define OTP_DATA_PAGE17_LOCK0_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE17_LOCK0_R2 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE17_LOCK0_R2_RESET "-" -#define OTP_DATA_PAGE17_LOCK0_R2_BITS _u(0x00ff0000) -#define OTP_DATA_PAGE17_LOCK0_R2_MSB _u(23) -#define OTP_DATA_PAGE17_LOCK0_R2_LSB _u(16) -#define OTP_DATA_PAGE17_LOCK0_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE17_LOCK0_R1 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE17_LOCK0_R1_RESET "-" -#define OTP_DATA_PAGE17_LOCK0_R1_BITS _u(0x0000ff00) -#define OTP_DATA_PAGE17_LOCK0_R1_MSB _u(15) -#define OTP_DATA_PAGE17_LOCK0_R1_LSB _u(8) -#define OTP_DATA_PAGE17_LOCK0_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE17_LOCK0_NO_KEY_STATE -// Description : State when at least one key is registered for this page and no -// matching key has been entered. -// 0x0 -> read_only -// 0x1 -> inaccessible -#define OTP_DATA_PAGE17_LOCK0_NO_KEY_STATE_RESET "-" -#define OTP_DATA_PAGE17_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) -#define OTP_DATA_PAGE17_LOCK0_NO_KEY_STATE_MSB _u(6) -#define OTP_DATA_PAGE17_LOCK0_NO_KEY_STATE_LSB _u(6) -#define OTP_DATA_PAGE17_LOCK0_NO_KEY_STATE_ACCESS "RO" -#define OTP_DATA_PAGE17_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) -#define OTP_DATA_PAGE17_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE17_LOCK0_KEY_R -// Description : Index 1-6 of a hardware key which must be entered to grant read -// access, or 0 if no such key is required. -#define OTP_DATA_PAGE17_LOCK0_KEY_R_RESET "-" -#define OTP_DATA_PAGE17_LOCK0_KEY_R_BITS _u(0x00000038) -#define OTP_DATA_PAGE17_LOCK0_KEY_R_MSB _u(5) -#define OTP_DATA_PAGE17_LOCK0_KEY_R_LSB _u(3) -#define OTP_DATA_PAGE17_LOCK0_KEY_R_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE17_LOCK0_KEY_W -// Description : Index 1-6 of a hardware key which must be entered to grant -// write access, or 0 if no such key is required. -#define OTP_DATA_PAGE17_LOCK0_KEY_W_RESET "-" -#define OTP_DATA_PAGE17_LOCK0_KEY_W_BITS _u(0x00000007) -#define OTP_DATA_PAGE17_LOCK0_KEY_W_MSB _u(2) -#define OTP_DATA_PAGE17_LOCK0_KEY_W_LSB _u(0) -#define OTP_DATA_PAGE17_LOCK0_KEY_W_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_PAGE17_LOCK1 -// Description : Lock configuration MSBs for page 17 (rows 0x440 through 0x47f). -// Locks are stored with 3-way majority vote encoding, so that -// bits can be set independently. -// -// This OTP location is always readable, and is write-protected by -// its own permissions. -#define OTP_DATA_PAGE17_LOCK1_ROW _u(0x00000fa3) -#define OTP_DATA_PAGE17_LOCK1_BITS _u(0x00ffff3f) -#define OTP_DATA_PAGE17_LOCK1_RESET _u(0x00000000) -#define OTP_DATA_PAGE17_LOCK1_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE17_LOCK1_R2 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE17_LOCK1_R2_RESET "-" -#define OTP_DATA_PAGE17_LOCK1_R2_BITS _u(0x00ff0000) -#define OTP_DATA_PAGE17_LOCK1_R2_MSB _u(23) -#define OTP_DATA_PAGE17_LOCK1_R2_LSB _u(16) -#define OTP_DATA_PAGE17_LOCK1_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE17_LOCK1_R1 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE17_LOCK1_R1_RESET "-" -#define OTP_DATA_PAGE17_LOCK1_R1_BITS _u(0x0000ff00) -#define OTP_DATA_PAGE17_LOCK1_R1_MSB _u(15) -#define OTP_DATA_PAGE17_LOCK1_R1_LSB _u(8) -#define OTP_DATA_PAGE17_LOCK1_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE17_LOCK1_LOCK_BL -// Description : Dummy lock bits reserved for bootloaders (including the RP2350 -// USB bootloader) to store their own OTP access permissions. No -// hardware effect, and no corresponding SW_LOCKx registers. -// 0x0 -> Bootloader permits user reads and writes to this page -// 0x1 -> Bootloader permits user reads of this page -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE -// 0x3 -> Bootloader does not permit user access to this page -#define OTP_DATA_PAGE17_LOCK1_LOCK_BL_RESET "-" -#define OTP_DATA_PAGE17_LOCK1_LOCK_BL_BITS _u(0x00000030) -#define OTP_DATA_PAGE17_LOCK1_LOCK_BL_MSB _u(5) -#define OTP_DATA_PAGE17_LOCK1_LOCK_BL_LSB _u(4) -#define OTP_DATA_PAGE17_LOCK1_LOCK_BL_ACCESS "RO" -#define OTP_DATA_PAGE17_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE17_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE17_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE17_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE17_LOCK1_LOCK_NS -// Description : Lock state for Non-secure accesses to this page. Thermometer- -// coded, so lock state can be advanced permanently from any state -// to any less-permissive state by programming OTP. Software can -// also advance the lock state temporarily (until next OTP reset) -// using the SW_LOCKx registers. -// -// Note that READ_WRITE and READ_ONLY are equivalent in hardware, -// as the SBPI programming interface is not accessible to Non- -// secure software. However, Secure software may check these bits -// to apply write permissions to a Non-secure OTP programming API. -// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. -// 0x1 -> Page can be read by Non-secure software -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. -// 0x3 -> Page can not be accessed by Non-secure software. -#define OTP_DATA_PAGE17_LOCK1_LOCK_NS_RESET "-" -#define OTP_DATA_PAGE17_LOCK1_LOCK_NS_BITS _u(0x0000000c) -#define OTP_DATA_PAGE17_LOCK1_LOCK_NS_MSB _u(3) -#define OTP_DATA_PAGE17_LOCK1_LOCK_NS_LSB _u(2) -#define OTP_DATA_PAGE17_LOCK1_LOCK_NS_ACCESS "RO" -#define OTP_DATA_PAGE17_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE17_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE17_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE17_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE17_LOCK1_LOCK_S -// Description : Lock state for Secure accesses to this page. Thermometer-coded, -// so lock state can be advanced permanently from any state to any -// less-permissive state by programming OTP. Software can also -// advance the lock state temporarily (until next OTP reset) using -// the SW_LOCKx registers. -// 0x0 -> Page is fully accessible by Secure software. -// 0x1 -> Page can be read by Secure software, but can not be written. -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. -// 0x3 -> Page can not be accessed by Secure software. -#define OTP_DATA_PAGE17_LOCK1_LOCK_S_RESET "-" -#define OTP_DATA_PAGE17_LOCK1_LOCK_S_BITS _u(0x00000003) -#define OTP_DATA_PAGE17_LOCK1_LOCK_S_MSB _u(1) -#define OTP_DATA_PAGE17_LOCK1_LOCK_S_LSB _u(0) -#define OTP_DATA_PAGE17_LOCK1_LOCK_S_ACCESS "RO" -#define OTP_DATA_PAGE17_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE17_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE17_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE17_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) -// ============================================================================= -// Register : OTP_DATA_PAGE18_LOCK0 -// Description : Lock configuration LSBs for page 18 (rows 0x480 through 0x4bf). -// Locks are stored with 3-way majority vote encoding, so that -// bits can be set independently. -// -// This OTP location is always readable, and is write-protected by -// its own permissions. -#define OTP_DATA_PAGE18_LOCK0_ROW _u(0x00000fa4) -#define OTP_DATA_PAGE18_LOCK0_BITS _u(0x00ffff7f) -#define OTP_DATA_PAGE18_LOCK0_RESET _u(0x00000000) -#define OTP_DATA_PAGE18_LOCK0_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE18_LOCK0_R2 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE18_LOCK0_R2_RESET "-" -#define OTP_DATA_PAGE18_LOCK0_R2_BITS _u(0x00ff0000) -#define OTP_DATA_PAGE18_LOCK0_R2_MSB _u(23) -#define OTP_DATA_PAGE18_LOCK0_R2_LSB _u(16) -#define OTP_DATA_PAGE18_LOCK0_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE18_LOCK0_R1 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE18_LOCK0_R1_RESET "-" -#define OTP_DATA_PAGE18_LOCK0_R1_BITS _u(0x0000ff00) -#define OTP_DATA_PAGE18_LOCK0_R1_MSB _u(15) -#define OTP_DATA_PAGE18_LOCK0_R1_LSB _u(8) -#define OTP_DATA_PAGE18_LOCK0_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE18_LOCK0_NO_KEY_STATE -// Description : State when at least one key is registered for this page and no -// matching key has been entered. -// 0x0 -> read_only -// 0x1 -> inaccessible -#define OTP_DATA_PAGE18_LOCK0_NO_KEY_STATE_RESET "-" -#define OTP_DATA_PAGE18_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) -#define OTP_DATA_PAGE18_LOCK0_NO_KEY_STATE_MSB _u(6) -#define OTP_DATA_PAGE18_LOCK0_NO_KEY_STATE_LSB _u(6) -#define OTP_DATA_PAGE18_LOCK0_NO_KEY_STATE_ACCESS "RO" -#define OTP_DATA_PAGE18_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) -#define OTP_DATA_PAGE18_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE18_LOCK0_KEY_R -// Description : Index 1-6 of a hardware key which must be entered to grant read -// access, or 0 if no such key is required. -#define OTP_DATA_PAGE18_LOCK0_KEY_R_RESET "-" -#define OTP_DATA_PAGE18_LOCK0_KEY_R_BITS _u(0x00000038) -#define OTP_DATA_PAGE18_LOCK0_KEY_R_MSB _u(5) -#define OTP_DATA_PAGE18_LOCK0_KEY_R_LSB _u(3) -#define OTP_DATA_PAGE18_LOCK0_KEY_R_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE18_LOCK0_KEY_W -// Description : Index 1-6 of a hardware key which must be entered to grant -// write access, or 0 if no such key is required. -#define OTP_DATA_PAGE18_LOCK0_KEY_W_RESET "-" -#define OTP_DATA_PAGE18_LOCK0_KEY_W_BITS _u(0x00000007) -#define OTP_DATA_PAGE18_LOCK0_KEY_W_MSB _u(2) -#define OTP_DATA_PAGE18_LOCK0_KEY_W_LSB _u(0) -#define OTP_DATA_PAGE18_LOCK0_KEY_W_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_PAGE18_LOCK1 -// Description : Lock configuration MSBs for page 18 (rows 0x480 through 0x4bf). -// Locks are stored with 3-way majority vote encoding, so that -// bits can be set independently. -// -// This OTP location is always readable, and is write-protected by -// its own permissions. -#define OTP_DATA_PAGE18_LOCK1_ROW _u(0x00000fa5) -#define OTP_DATA_PAGE18_LOCK1_BITS _u(0x00ffff3f) -#define OTP_DATA_PAGE18_LOCK1_RESET _u(0x00000000) -#define OTP_DATA_PAGE18_LOCK1_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE18_LOCK1_R2 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE18_LOCK1_R2_RESET "-" -#define OTP_DATA_PAGE18_LOCK1_R2_BITS _u(0x00ff0000) -#define OTP_DATA_PAGE18_LOCK1_R2_MSB _u(23) -#define OTP_DATA_PAGE18_LOCK1_R2_LSB _u(16) -#define OTP_DATA_PAGE18_LOCK1_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE18_LOCK1_R1 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE18_LOCK1_R1_RESET "-" -#define OTP_DATA_PAGE18_LOCK1_R1_BITS _u(0x0000ff00) -#define OTP_DATA_PAGE18_LOCK1_R1_MSB _u(15) -#define OTP_DATA_PAGE18_LOCK1_R1_LSB _u(8) -#define OTP_DATA_PAGE18_LOCK1_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE18_LOCK1_LOCK_BL -// Description : Dummy lock bits reserved for bootloaders (including the RP2350 -// USB bootloader) to store their own OTP access permissions. No -// hardware effect, and no corresponding SW_LOCKx registers. -// 0x0 -> Bootloader permits user reads and writes to this page -// 0x1 -> Bootloader permits user reads of this page -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE -// 0x3 -> Bootloader does not permit user access to this page -#define OTP_DATA_PAGE18_LOCK1_LOCK_BL_RESET "-" -#define OTP_DATA_PAGE18_LOCK1_LOCK_BL_BITS _u(0x00000030) -#define OTP_DATA_PAGE18_LOCK1_LOCK_BL_MSB _u(5) -#define OTP_DATA_PAGE18_LOCK1_LOCK_BL_LSB _u(4) -#define OTP_DATA_PAGE18_LOCK1_LOCK_BL_ACCESS "RO" -#define OTP_DATA_PAGE18_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE18_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE18_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE18_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE18_LOCK1_LOCK_NS -// Description : Lock state for Non-secure accesses to this page. Thermometer- -// coded, so lock state can be advanced permanently from any state -// to any less-permissive state by programming OTP. Software can -// also advance the lock state temporarily (until next OTP reset) -// using the SW_LOCKx registers. -// -// Note that READ_WRITE and READ_ONLY are equivalent in hardware, -// as the SBPI programming interface is not accessible to Non- -// secure software. However, Secure software may check these bits -// to apply write permissions to a Non-secure OTP programming API. -// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. -// 0x1 -> Page can be read by Non-secure software -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. -// 0x3 -> Page can not be accessed by Non-secure software. -#define OTP_DATA_PAGE18_LOCK1_LOCK_NS_RESET "-" -#define OTP_DATA_PAGE18_LOCK1_LOCK_NS_BITS _u(0x0000000c) -#define OTP_DATA_PAGE18_LOCK1_LOCK_NS_MSB _u(3) -#define OTP_DATA_PAGE18_LOCK1_LOCK_NS_LSB _u(2) -#define OTP_DATA_PAGE18_LOCK1_LOCK_NS_ACCESS "RO" -#define OTP_DATA_PAGE18_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE18_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE18_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE18_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE18_LOCK1_LOCK_S -// Description : Lock state for Secure accesses to this page. Thermometer-coded, -// so lock state can be advanced permanently from any state to any -// less-permissive state by programming OTP. Software can also -// advance the lock state temporarily (until next OTP reset) using -// the SW_LOCKx registers. -// 0x0 -> Page is fully accessible by Secure software. -// 0x1 -> Page can be read by Secure software, but can not be written. -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. -// 0x3 -> Page can not be accessed by Secure software. -#define OTP_DATA_PAGE18_LOCK1_LOCK_S_RESET "-" -#define OTP_DATA_PAGE18_LOCK1_LOCK_S_BITS _u(0x00000003) -#define OTP_DATA_PAGE18_LOCK1_LOCK_S_MSB _u(1) -#define OTP_DATA_PAGE18_LOCK1_LOCK_S_LSB _u(0) -#define OTP_DATA_PAGE18_LOCK1_LOCK_S_ACCESS "RO" -#define OTP_DATA_PAGE18_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE18_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE18_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE18_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) -// ============================================================================= -// Register : OTP_DATA_PAGE19_LOCK0 -// Description : Lock configuration LSBs for page 19 (rows 0x4c0 through 0x4ff). -// Locks are stored with 3-way majority vote encoding, so that -// bits can be set independently. -// -// This OTP location is always readable, and is write-protected by -// its own permissions. -#define OTP_DATA_PAGE19_LOCK0_ROW _u(0x00000fa6) -#define OTP_DATA_PAGE19_LOCK0_BITS _u(0x00ffff7f) -#define OTP_DATA_PAGE19_LOCK0_RESET _u(0x00000000) -#define OTP_DATA_PAGE19_LOCK0_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE19_LOCK0_R2 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE19_LOCK0_R2_RESET "-" -#define OTP_DATA_PAGE19_LOCK0_R2_BITS _u(0x00ff0000) -#define OTP_DATA_PAGE19_LOCK0_R2_MSB _u(23) -#define OTP_DATA_PAGE19_LOCK0_R2_LSB _u(16) -#define OTP_DATA_PAGE19_LOCK0_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE19_LOCK0_R1 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE19_LOCK0_R1_RESET "-" -#define OTP_DATA_PAGE19_LOCK0_R1_BITS _u(0x0000ff00) -#define OTP_DATA_PAGE19_LOCK0_R1_MSB _u(15) -#define OTP_DATA_PAGE19_LOCK0_R1_LSB _u(8) -#define OTP_DATA_PAGE19_LOCK0_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE19_LOCK0_NO_KEY_STATE -// Description : State when at least one key is registered for this page and no -// matching key has been entered. -// 0x0 -> read_only -// 0x1 -> inaccessible -#define OTP_DATA_PAGE19_LOCK0_NO_KEY_STATE_RESET "-" -#define OTP_DATA_PAGE19_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) -#define OTP_DATA_PAGE19_LOCK0_NO_KEY_STATE_MSB _u(6) -#define OTP_DATA_PAGE19_LOCK0_NO_KEY_STATE_LSB _u(6) -#define OTP_DATA_PAGE19_LOCK0_NO_KEY_STATE_ACCESS "RO" -#define OTP_DATA_PAGE19_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) -#define OTP_DATA_PAGE19_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE19_LOCK0_KEY_R -// Description : Index 1-6 of a hardware key which must be entered to grant read -// access, or 0 if no such key is required. -#define OTP_DATA_PAGE19_LOCK0_KEY_R_RESET "-" -#define OTP_DATA_PAGE19_LOCK0_KEY_R_BITS _u(0x00000038) -#define OTP_DATA_PAGE19_LOCK0_KEY_R_MSB _u(5) -#define OTP_DATA_PAGE19_LOCK0_KEY_R_LSB _u(3) -#define OTP_DATA_PAGE19_LOCK0_KEY_R_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE19_LOCK0_KEY_W -// Description : Index 1-6 of a hardware key which must be entered to grant -// write access, or 0 if no such key is required. -#define OTP_DATA_PAGE19_LOCK0_KEY_W_RESET "-" -#define OTP_DATA_PAGE19_LOCK0_KEY_W_BITS _u(0x00000007) -#define OTP_DATA_PAGE19_LOCK0_KEY_W_MSB _u(2) -#define OTP_DATA_PAGE19_LOCK0_KEY_W_LSB _u(0) -#define OTP_DATA_PAGE19_LOCK0_KEY_W_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_PAGE19_LOCK1 -// Description : Lock configuration MSBs for page 19 (rows 0x4c0 through 0x4ff). -// Locks are stored with 3-way majority vote encoding, so that -// bits can be set independently. -// -// This OTP location is always readable, and is write-protected by -// its own permissions. -#define OTP_DATA_PAGE19_LOCK1_ROW _u(0x00000fa7) -#define OTP_DATA_PAGE19_LOCK1_BITS _u(0x00ffff3f) -#define OTP_DATA_PAGE19_LOCK1_RESET _u(0x00000000) -#define OTP_DATA_PAGE19_LOCK1_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE19_LOCK1_R2 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE19_LOCK1_R2_RESET "-" -#define OTP_DATA_PAGE19_LOCK1_R2_BITS _u(0x00ff0000) -#define OTP_DATA_PAGE19_LOCK1_R2_MSB _u(23) -#define OTP_DATA_PAGE19_LOCK1_R2_LSB _u(16) -#define OTP_DATA_PAGE19_LOCK1_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE19_LOCK1_R1 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE19_LOCK1_R1_RESET "-" -#define OTP_DATA_PAGE19_LOCK1_R1_BITS _u(0x0000ff00) -#define OTP_DATA_PAGE19_LOCK1_R1_MSB _u(15) -#define OTP_DATA_PAGE19_LOCK1_R1_LSB _u(8) -#define OTP_DATA_PAGE19_LOCK1_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE19_LOCK1_LOCK_BL -// Description : Dummy lock bits reserved for bootloaders (including the RP2350 -// USB bootloader) to store their own OTP access permissions. No -// hardware effect, and no corresponding SW_LOCKx registers. -// 0x0 -> Bootloader permits user reads and writes to this page -// 0x1 -> Bootloader permits user reads of this page -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE -// 0x3 -> Bootloader does not permit user access to this page -#define OTP_DATA_PAGE19_LOCK1_LOCK_BL_RESET "-" -#define OTP_DATA_PAGE19_LOCK1_LOCK_BL_BITS _u(0x00000030) -#define OTP_DATA_PAGE19_LOCK1_LOCK_BL_MSB _u(5) -#define OTP_DATA_PAGE19_LOCK1_LOCK_BL_LSB _u(4) -#define OTP_DATA_PAGE19_LOCK1_LOCK_BL_ACCESS "RO" -#define OTP_DATA_PAGE19_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE19_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE19_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE19_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE19_LOCK1_LOCK_NS -// Description : Lock state for Non-secure accesses to this page. Thermometer- -// coded, so lock state can be advanced permanently from any state -// to any less-permissive state by programming OTP. Software can -// also advance the lock state temporarily (until next OTP reset) -// using the SW_LOCKx registers. -// -// Note that READ_WRITE and READ_ONLY are equivalent in hardware, -// as the SBPI programming interface is not accessible to Non- -// secure software. However, Secure software may check these bits -// to apply write permissions to a Non-secure OTP programming API. -// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. -// 0x1 -> Page can be read by Non-secure software -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. -// 0x3 -> Page can not be accessed by Non-secure software. -#define OTP_DATA_PAGE19_LOCK1_LOCK_NS_RESET "-" -#define OTP_DATA_PAGE19_LOCK1_LOCK_NS_BITS _u(0x0000000c) -#define OTP_DATA_PAGE19_LOCK1_LOCK_NS_MSB _u(3) -#define OTP_DATA_PAGE19_LOCK1_LOCK_NS_LSB _u(2) -#define OTP_DATA_PAGE19_LOCK1_LOCK_NS_ACCESS "RO" -#define OTP_DATA_PAGE19_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE19_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE19_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE19_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE19_LOCK1_LOCK_S -// Description : Lock state for Secure accesses to this page. Thermometer-coded, -// so lock state can be advanced permanently from any state to any -// less-permissive state by programming OTP. Software can also -// advance the lock state temporarily (until next OTP reset) using -// the SW_LOCKx registers. -// 0x0 -> Page is fully accessible by Secure software. -// 0x1 -> Page can be read by Secure software, but can not be written. -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. -// 0x3 -> Page can not be accessed by Secure software. -#define OTP_DATA_PAGE19_LOCK1_LOCK_S_RESET "-" -#define OTP_DATA_PAGE19_LOCK1_LOCK_S_BITS _u(0x00000003) -#define OTP_DATA_PAGE19_LOCK1_LOCK_S_MSB _u(1) -#define OTP_DATA_PAGE19_LOCK1_LOCK_S_LSB _u(0) -#define OTP_DATA_PAGE19_LOCK1_LOCK_S_ACCESS "RO" -#define OTP_DATA_PAGE19_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE19_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE19_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE19_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) -// ============================================================================= -// Register : OTP_DATA_PAGE20_LOCK0 -// Description : Lock configuration LSBs for page 20 (rows 0x500 through 0x53f). -// Locks are stored with 3-way majority vote encoding, so that -// bits can be set independently. -// -// This OTP location is always readable, and is write-protected by -// its own permissions. -#define OTP_DATA_PAGE20_LOCK0_ROW _u(0x00000fa8) -#define OTP_DATA_PAGE20_LOCK0_BITS _u(0x00ffff7f) -#define OTP_DATA_PAGE20_LOCK0_RESET _u(0x00000000) -#define OTP_DATA_PAGE20_LOCK0_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE20_LOCK0_R2 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE20_LOCK0_R2_RESET "-" -#define OTP_DATA_PAGE20_LOCK0_R2_BITS _u(0x00ff0000) -#define OTP_DATA_PAGE20_LOCK0_R2_MSB _u(23) -#define OTP_DATA_PAGE20_LOCK0_R2_LSB _u(16) -#define OTP_DATA_PAGE20_LOCK0_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE20_LOCK0_R1 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE20_LOCK0_R1_RESET "-" -#define OTP_DATA_PAGE20_LOCK0_R1_BITS _u(0x0000ff00) -#define OTP_DATA_PAGE20_LOCK0_R1_MSB _u(15) -#define OTP_DATA_PAGE20_LOCK0_R1_LSB _u(8) -#define OTP_DATA_PAGE20_LOCK0_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE20_LOCK0_NO_KEY_STATE -// Description : State when at least one key is registered for this page and no -// matching key has been entered. -// 0x0 -> read_only -// 0x1 -> inaccessible -#define OTP_DATA_PAGE20_LOCK0_NO_KEY_STATE_RESET "-" -#define OTP_DATA_PAGE20_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) -#define OTP_DATA_PAGE20_LOCK0_NO_KEY_STATE_MSB _u(6) -#define OTP_DATA_PAGE20_LOCK0_NO_KEY_STATE_LSB _u(6) -#define OTP_DATA_PAGE20_LOCK0_NO_KEY_STATE_ACCESS "RO" -#define OTP_DATA_PAGE20_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) -#define OTP_DATA_PAGE20_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE20_LOCK0_KEY_R -// Description : Index 1-6 of a hardware key which must be entered to grant read -// access, or 0 if no such key is required. -#define OTP_DATA_PAGE20_LOCK0_KEY_R_RESET "-" -#define OTP_DATA_PAGE20_LOCK0_KEY_R_BITS _u(0x00000038) -#define OTP_DATA_PAGE20_LOCK0_KEY_R_MSB _u(5) -#define OTP_DATA_PAGE20_LOCK0_KEY_R_LSB _u(3) -#define OTP_DATA_PAGE20_LOCK0_KEY_R_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE20_LOCK0_KEY_W -// Description : Index 1-6 of a hardware key which must be entered to grant -// write access, or 0 if no such key is required. -#define OTP_DATA_PAGE20_LOCK0_KEY_W_RESET "-" -#define OTP_DATA_PAGE20_LOCK0_KEY_W_BITS _u(0x00000007) -#define OTP_DATA_PAGE20_LOCK0_KEY_W_MSB _u(2) -#define OTP_DATA_PAGE20_LOCK0_KEY_W_LSB _u(0) -#define OTP_DATA_PAGE20_LOCK0_KEY_W_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_PAGE20_LOCK1 -// Description : Lock configuration MSBs for page 20 (rows 0x500 through 0x53f). -// Locks are stored with 3-way majority vote encoding, so that -// bits can be set independently. -// -// This OTP location is always readable, and is write-protected by -// its own permissions. -#define OTP_DATA_PAGE20_LOCK1_ROW _u(0x00000fa9) -#define OTP_DATA_PAGE20_LOCK1_BITS _u(0x00ffff3f) -#define OTP_DATA_PAGE20_LOCK1_RESET _u(0x00000000) -#define OTP_DATA_PAGE20_LOCK1_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE20_LOCK1_R2 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE20_LOCK1_R2_RESET "-" -#define OTP_DATA_PAGE20_LOCK1_R2_BITS _u(0x00ff0000) -#define OTP_DATA_PAGE20_LOCK1_R2_MSB _u(23) -#define OTP_DATA_PAGE20_LOCK1_R2_LSB _u(16) -#define OTP_DATA_PAGE20_LOCK1_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE20_LOCK1_R1 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE20_LOCK1_R1_RESET "-" -#define OTP_DATA_PAGE20_LOCK1_R1_BITS _u(0x0000ff00) -#define OTP_DATA_PAGE20_LOCK1_R1_MSB _u(15) -#define OTP_DATA_PAGE20_LOCK1_R1_LSB _u(8) -#define OTP_DATA_PAGE20_LOCK1_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE20_LOCK1_LOCK_BL -// Description : Dummy lock bits reserved for bootloaders (including the RP2350 -// USB bootloader) to store their own OTP access permissions. No -// hardware effect, and no corresponding SW_LOCKx registers. -// 0x0 -> Bootloader permits user reads and writes to this page -// 0x1 -> Bootloader permits user reads of this page -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE -// 0x3 -> Bootloader does not permit user access to this page -#define OTP_DATA_PAGE20_LOCK1_LOCK_BL_RESET "-" -#define OTP_DATA_PAGE20_LOCK1_LOCK_BL_BITS _u(0x00000030) -#define OTP_DATA_PAGE20_LOCK1_LOCK_BL_MSB _u(5) -#define OTP_DATA_PAGE20_LOCK1_LOCK_BL_LSB _u(4) -#define OTP_DATA_PAGE20_LOCK1_LOCK_BL_ACCESS "RO" -#define OTP_DATA_PAGE20_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE20_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE20_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE20_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE20_LOCK1_LOCK_NS -// Description : Lock state for Non-secure accesses to this page. Thermometer- -// coded, so lock state can be advanced permanently from any state -// to any less-permissive state by programming OTP. Software can -// also advance the lock state temporarily (until next OTP reset) -// using the SW_LOCKx registers. -// -// Note that READ_WRITE and READ_ONLY are equivalent in hardware, -// as the SBPI programming interface is not accessible to Non- -// secure software. However, Secure software may check these bits -// to apply write permissions to a Non-secure OTP programming API. -// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. -// 0x1 -> Page can be read by Non-secure software -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. -// 0x3 -> Page can not be accessed by Non-secure software. -#define OTP_DATA_PAGE20_LOCK1_LOCK_NS_RESET "-" -#define OTP_DATA_PAGE20_LOCK1_LOCK_NS_BITS _u(0x0000000c) -#define OTP_DATA_PAGE20_LOCK1_LOCK_NS_MSB _u(3) -#define OTP_DATA_PAGE20_LOCK1_LOCK_NS_LSB _u(2) -#define OTP_DATA_PAGE20_LOCK1_LOCK_NS_ACCESS "RO" -#define OTP_DATA_PAGE20_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE20_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE20_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE20_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE20_LOCK1_LOCK_S -// Description : Lock state for Secure accesses to this page. Thermometer-coded, -// so lock state can be advanced permanently from any state to any -// less-permissive state by programming OTP. Software can also -// advance the lock state temporarily (until next OTP reset) using -// the SW_LOCKx registers. -// 0x0 -> Page is fully accessible by Secure software. -// 0x1 -> Page can be read by Secure software, but can not be written. -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. -// 0x3 -> Page can not be accessed by Secure software. -#define OTP_DATA_PAGE20_LOCK1_LOCK_S_RESET "-" -#define OTP_DATA_PAGE20_LOCK1_LOCK_S_BITS _u(0x00000003) -#define OTP_DATA_PAGE20_LOCK1_LOCK_S_MSB _u(1) -#define OTP_DATA_PAGE20_LOCK1_LOCK_S_LSB _u(0) -#define OTP_DATA_PAGE20_LOCK1_LOCK_S_ACCESS "RO" -#define OTP_DATA_PAGE20_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE20_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE20_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE20_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) -// ============================================================================= -// Register : OTP_DATA_PAGE21_LOCK0 -// Description : Lock configuration LSBs for page 21 (rows 0x540 through 0x57f). -// Locks are stored with 3-way majority vote encoding, so that -// bits can be set independently. -// -// This OTP location is always readable, and is write-protected by -// its own permissions. -#define OTP_DATA_PAGE21_LOCK0_ROW _u(0x00000faa) -#define OTP_DATA_PAGE21_LOCK0_BITS _u(0x00ffff7f) -#define OTP_DATA_PAGE21_LOCK0_RESET _u(0x00000000) -#define OTP_DATA_PAGE21_LOCK0_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE21_LOCK0_R2 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE21_LOCK0_R2_RESET "-" -#define OTP_DATA_PAGE21_LOCK0_R2_BITS _u(0x00ff0000) -#define OTP_DATA_PAGE21_LOCK0_R2_MSB _u(23) -#define OTP_DATA_PAGE21_LOCK0_R2_LSB _u(16) -#define OTP_DATA_PAGE21_LOCK0_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE21_LOCK0_R1 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE21_LOCK0_R1_RESET "-" -#define OTP_DATA_PAGE21_LOCK0_R1_BITS _u(0x0000ff00) -#define OTP_DATA_PAGE21_LOCK0_R1_MSB _u(15) -#define OTP_DATA_PAGE21_LOCK0_R1_LSB _u(8) -#define OTP_DATA_PAGE21_LOCK0_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE21_LOCK0_NO_KEY_STATE -// Description : State when at least one key is registered for this page and no -// matching key has been entered. -// 0x0 -> read_only -// 0x1 -> inaccessible -#define OTP_DATA_PAGE21_LOCK0_NO_KEY_STATE_RESET "-" -#define OTP_DATA_PAGE21_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) -#define OTP_DATA_PAGE21_LOCK0_NO_KEY_STATE_MSB _u(6) -#define OTP_DATA_PAGE21_LOCK0_NO_KEY_STATE_LSB _u(6) -#define OTP_DATA_PAGE21_LOCK0_NO_KEY_STATE_ACCESS "RO" -#define OTP_DATA_PAGE21_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) -#define OTP_DATA_PAGE21_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE21_LOCK0_KEY_R -// Description : Index 1-6 of a hardware key which must be entered to grant read -// access, or 0 if no such key is required. -#define OTP_DATA_PAGE21_LOCK0_KEY_R_RESET "-" -#define OTP_DATA_PAGE21_LOCK0_KEY_R_BITS _u(0x00000038) -#define OTP_DATA_PAGE21_LOCK0_KEY_R_MSB _u(5) -#define OTP_DATA_PAGE21_LOCK0_KEY_R_LSB _u(3) -#define OTP_DATA_PAGE21_LOCK0_KEY_R_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE21_LOCK0_KEY_W -// Description : Index 1-6 of a hardware key which must be entered to grant -// write access, or 0 if no such key is required. -#define OTP_DATA_PAGE21_LOCK0_KEY_W_RESET "-" -#define OTP_DATA_PAGE21_LOCK0_KEY_W_BITS _u(0x00000007) -#define OTP_DATA_PAGE21_LOCK0_KEY_W_MSB _u(2) -#define OTP_DATA_PAGE21_LOCK0_KEY_W_LSB _u(0) -#define OTP_DATA_PAGE21_LOCK0_KEY_W_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_PAGE21_LOCK1 -// Description : Lock configuration MSBs for page 21 (rows 0x540 through 0x57f). -// Locks are stored with 3-way majority vote encoding, so that -// bits can be set independently. -// -// This OTP location is always readable, and is write-protected by -// its own permissions. -#define OTP_DATA_PAGE21_LOCK1_ROW _u(0x00000fab) -#define OTP_DATA_PAGE21_LOCK1_BITS _u(0x00ffff3f) -#define OTP_DATA_PAGE21_LOCK1_RESET _u(0x00000000) -#define OTP_DATA_PAGE21_LOCK1_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE21_LOCK1_R2 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE21_LOCK1_R2_RESET "-" -#define OTP_DATA_PAGE21_LOCK1_R2_BITS _u(0x00ff0000) -#define OTP_DATA_PAGE21_LOCK1_R2_MSB _u(23) -#define OTP_DATA_PAGE21_LOCK1_R2_LSB _u(16) -#define OTP_DATA_PAGE21_LOCK1_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE21_LOCK1_R1 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE21_LOCK1_R1_RESET "-" -#define OTP_DATA_PAGE21_LOCK1_R1_BITS _u(0x0000ff00) -#define OTP_DATA_PAGE21_LOCK1_R1_MSB _u(15) -#define OTP_DATA_PAGE21_LOCK1_R1_LSB _u(8) -#define OTP_DATA_PAGE21_LOCK1_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE21_LOCK1_LOCK_BL -// Description : Dummy lock bits reserved for bootloaders (including the RP2350 -// USB bootloader) to store their own OTP access permissions. No -// hardware effect, and no corresponding SW_LOCKx registers. -// 0x0 -> Bootloader permits user reads and writes to this page -// 0x1 -> Bootloader permits user reads of this page -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE -// 0x3 -> Bootloader does not permit user access to this page -#define OTP_DATA_PAGE21_LOCK1_LOCK_BL_RESET "-" -#define OTP_DATA_PAGE21_LOCK1_LOCK_BL_BITS _u(0x00000030) -#define OTP_DATA_PAGE21_LOCK1_LOCK_BL_MSB _u(5) -#define OTP_DATA_PAGE21_LOCK1_LOCK_BL_LSB _u(4) -#define OTP_DATA_PAGE21_LOCK1_LOCK_BL_ACCESS "RO" -#define OTP_DATA_PAGE21_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE21_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE21_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE21_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE21_LOCK1_LOCK_NS -// Description : Lock state for Non-secure accesses to this page. Thermometer- -// coded, so lock state can be advanced permanently from any state -// to any less-permissive state by programming OTP. Software can -// also advance the lock state temporarily (until next OTP reset) -// using the SW_LOCKx registers. -// -// Note that READ_WRITE and READ_ONLY are equivalent in hardware, -// as the SBPI programming interface is not accessible to Non- -// secure software. However, Secure software may check these bits -// to apply write permissions to a Non-secure OTP programming API. -// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. -// 0x1 -> Page can be read by Non-secure software -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. -// 0x3 -> Page can not be accessed by Non-secure software. -#define OTP_DATA_PAGE21_LOCK1_LOCK_NS_RESET "-" -#define OTP_DATA_PAGE21_LOCK1_LOCK_NS_BITS _u(0x0000000c) -#define OTP_DATA_PAGE21_LOCK1_LOCK_NS_MSB _u(3) -#define OTP_DATA_PAGE21_LOCK1_LOCK_NS_LSB _u(2) -#define OTP_DATA_PAGE21_LOCK1_LOCK_NS_ACCESS "RO" -#define OTP_DATA_PAGE21_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE21_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE21_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE21_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE21_LOCK1_LOCK_S -// Description : Lock state for Secure accesses to this page. Thermometer-coded, -// so lock state can be advanced permanently from any state to any -// less-permissive state by programming OTP. Software can also -// advance the lock state temporarily (until next OTP reset) using -// the SW_LOCKx registers. -// 0x0 -> Page is fully accessible by Secure software. -// 0x1 -> Page can be read by Secure software, but can not be written. -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. -// 0x3 -> Page can not be accessed by Secure software. -#define OTP_DATA_PAGE21_LOCK1_LOCK_S_RESET "-" -#define OTP_DATA_PAGE21_LOCK1_LOCK_S_BITS _u(0x00000003) -#define OTP_DATA_PAGE21_LOCK1_LOCK_S_MSB _u(1) -#define OTP_DATA_PAGE21_LOCK1_LOCK_S_LSB _u(0) -#define OTP_DATA_PAGE21_LOCK1_LOCK_S_ACCESS "RO" -#define OTP_DATA_PAGE21_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE21_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE21_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE21_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) -// ============================================================================= -// Register : OTP_DATA_PAGE22_LOCK0 -// Description : Lock configuration LSBs for page 22 (rows 0x580 through 0x5bf). -// Locks are stored with 3-way majority vote encoding, so that -// bits can be set independently. -// -// This OTP location is always readable, and is write-protected by -// its own permissions. -#define OTP_DATA_PAGE22_LOCK0_ROW _u(0x00000fac) -#define OTP_DATA_PAGE22_LOCK0_BITS _u(0x00ffff7f) -#define OTP_DATA_PAGE22_LOCK0_RESET _u(0x00000000) -#define OTP_DATA_PAGE22_LOCK0_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE22_LOCK0_R2 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE22_LOCK0_R2_RESET "-" -#define OTP_DATA_PAGE22_LOCK0_R2_BITS _u(0x00ff0000) -#define OTP_DATA_PAGE22_LOCK0_R2_MSB _u(23) -#define OTP_DATA_PAGE22_LOCK0_R2_LSB _u(16) -#define OTP_DATA_PAGE22_LOCK0_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE22_LOCK0_R1 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE22_LOCK0_R1_RESET "-" -#define OTP_DATA_PAGE22_LOCK0_R1_BITS _u(0x0000ff00) -#define OTP_DATA_PAGE22_LOCK0_R1_MSB _u(15) -#define OTP_DATA_PAGE22_LOCK0_R1_LSB _u(8) -#define OTP_DATA_PAGE22_LOCK0_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE22_LOCK0_NO_KEY_STATE -// Description : State when at least one key is registered for this page and no -// matching key has been entered. -// 0x0 -> read_only -// 0x1 -> inaccessible -#define OTP_DATA_PAGE22_LOCK0_NO_KEY_STATE_RESET "-" -#define OTP_DATA_PAGE22_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) -#define OTP_DATA_PAGE22_LOCK0_NO_KEY_STATE_MSB _u(6) -#define OTP_DATA_PAGE22_LOCK0_NO_KEY_STATE_LSB _u(6) -#define OTP_DATA_PAGE22_LOCK0_NO_KEY_STATE_ACCESS "RO" -#define OTP_DATA_PAGE22_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) -#define OTP_DATA_PAGE22_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE22_LOCK0_KEY_R -// Description : Index 1-6 of a hardware key which must be entered to grant read -// access, or 0 if no such key is required. -#define OTP_DATA_PAGE22_LOCK0_KEY_R_RESET "-" -#define OTP_DATA_PAGE22_LOCK0_KEY_R_BITS _u(0x00000038) -#define OTP_DATA_PAGE22_LOCK0_KEY_R_MSB _u(5) -#define OTP_DATA_PAGE22_LOCK0_KEY_R_LSB _u(3) -#define OTP_DATA_PAGE22_LOCK0_KEY_R_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE22_LOCK0_KEY_W -// Description : Index 1-6 of a hardware key which must be entered to grant -// write access, or 0 if no such key is required. -#define OTP_DATA_PAGE22_LOCK0_KEY_W_RESET "-" -#define OTP_DATA_PAGE22_LOCK0_KEY_W_BITS _u(0x00000007) -#define OTP_DATA_PAGE22_LOCK0_KEY_W_MSB _u(2) -#define OTP_DATA_PAGE22_LOCK0_KEY_W_LSB _u(0) -#define OTP_DATA_PAGE22_LOCK0_KEY_W_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_PAGE22_LOCK1 -// Description : Lock configuration MSBs for page 22 (rows 0x580 through 0x5bf). -// Locks are stored with 3-way majority vote encoding, so that -// bits can be set independently. -// -// This OTP location is always readable, and is write-protected by -// its own permissions. -#define OTP_DATA_PAGE22_LOCK1_ROW _u(0x00000fad) -#define OTP_DATA_PAGE22_LOCK1_BITS _u(0x00ffff3f) -#define OTP_DATA_PAGE22_LOCK1_RESET _u(0x00000000) -#define OTP_DATA_PAGE22_LOCK1_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE22_LOCK1_R2 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE22_LOCK1_R2_RESET "-" -#define OTP_DATA_PAGE22_LOCK1_R2_BITS _u(0x00ff0000) -#define OTP_DATA_PAGE22_LOCK1_R2_MSB _u(23) -#define OTP_DATA_PAGE22_LOCK1_R2_LSB _u(16) -#define OTP_DATA_PAGE22_LOCK1_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE22_LOCK1_R1 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE22_LOCK1_R1_RESET "-" -#define OTP_DATA_PAGE22_LOCK1_R1_BITS _u(0x0000ff00) -#define OTP_DATA_PAGE22_LOCK1_R1_MSB _u(15) -#define OTP_DATA_PAGE22_LOCK1_R1_LSB _u(8) -#define OTP_DATA_PAGE22_LOCK1_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE22_LOCK1_LOCK_BL -// Description : Dummy lock bits reserved for bootloaders (including the RP2350 -// USB bootloader) to store their own OTP access permissions. No -// hardware effect, and no corresponding SW_LOCKx registers. -// 0x0 -> Bootloader permits user reads and writes to this page -// 0x1 -> Bootloader permits user reads of this page -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE -// 0x3 -> Bootloader does not permit user access to this page -#define OTP_DATA_PAGE22_LOCK1_LOCK_BL_RESET "-" -#define OTP_DATA_PAGE22_LOCK1_LOCK_BL_BITS _u(0x00000030) -#define OTP_DATA_PAGE22_LOCK1_LOCK_BL_MSB _u(5) -#define OTP_DATA_PAGE22_LOCK1_LOCK_BL_LSB _u(4) -#define OTP_DATA_PAGE22_LOCK1_LOCK_BL_ACCESS "RO" -#define OTP_DATA_PAGE22_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE22_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE22_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE22_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE22_LOCK1_LOCK_NS -// Description : Lock state for Non-secure accesses to this page. Thermometer- -// coded, so lock state can be advanced permanently from any state -// to any less-permissive state by programming OTP. Software can -// also advance the lock state temporarily (until next OTP reset) -// using the SW_LOCKx registers. -// -// Note that READ_WRITE and READ_ONLY are equivalent in hardware, -// as the SBPI programming interface is not accessible to Non- -// secure software. However, Secure software may check these bits -// to apply write permissions to a Non-secure OTP programming API. -// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. -// 0x1 -> Page can be read by Non-secure software -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. -// 0x3 -> Page can not be accessed by Non-secure software. -#define OTP_DATA_PAGE22_LOCK1_LOCK_NS_RESET "-" -#define OTP_DATA_PAGE22_LOCK1_LOCK_NS_BITS _u(0x0000000c) -#define OTP_DATA_PAGE22_LOCK1_LOCK_NS_MSB _u(3) -#define OTP_DATA_PAGE22_LOCK1_LOCK_NS_LSB _u(2) -#define OTP_DATA_PAGE22_LOCK1_LOCK_NS_ACCESS "RO" -#define OTP_DATA_PAGE22_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE22_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE22_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE22_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE22_LOCK1_LOCK_S -// Description : Lock state for Secure accesses to this page. Thermometer-coded, -// so lock state can be advanced permanently from any state to any -// less-permissive state by programming OTP. Software can also -// advance the lock state temporarily (until next OTP reset) using -// the SW_LOCKx registers. -// 0x0 -> Page is fully accessible by Secure software. -// 0x1 -> Page can be read by Secure software, but can not be written. -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. -// 0x3 -> Page can not be accessed by Secure software. -#define OTP_DATA_PAGE22_LOCK1_LOCK_S_RESET "-" -#define OTP_DATA_PAGE22_LOCK1_LOCK_S_BITS _u(0x00000003) -#define OTP_DATA_PAGE22_LOCK1_LOCK_S_MSB _u(1) -#define OTP_DATA_PAGE22_LOCK1_LOCK_S_LSB _u(0) -#define OTP_DATA_PAGE22_LOCK1_LOCK_S_ACCESS "RO" -#define OTP_DATA_PAGE22_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE22_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE22_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE22_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) -// ============================================================================= -// Register : OTP_DATA_PAGE23_LOCK0 -// Description : Lock configuration LSBs for page 23 (rows 0x5c0 through 0x5ff). -// Locks are stored with 3-way majority vote encoding, so that -// bits can be set independently. -// -// This OTP location is always readable, and is write-protected by -// its own permissions. -#define OTP_DATA_PAGE23_LOCK0_ROW _u(0x00000fae) -#define OTP_DATA_PAGE23_LOCK0_BITS _u(0x00ffff7f) -#define OTP_DATA_PAGE23_LOCK0_RESET _u(0x00000000) -#define OTP_DATA_PAGE23_LOCK0_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE23_LOCK0_R2 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE23_LOCK0_R2_RESET "-" -#define OTP_DATA_PAGE23_LOCK0_R2_BITS _u(0x00ff0000) -#define OTP_DATA_PAGE23_LOCK0_R2_MSB _u(23) -#define OTP_DATA_PAGE23_LOCK0_R2_LSB _u(16) -#define OTP_DATA_PAGE23_LOCK0_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE23_LOCK0_R1 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE23_LOCK0_R1_RESET "-" -#define OTP_DATA_PAGE23_LOCK0_R1_BITS _u(0x0000ff00) -#define OTP_DATA_PAGE23_LOCK0_R1_MSB _u(15) -#define OTP_DATA_PAGE23_LOCK0_R1_LSB _u(8) -#define OTP_DATA_PAGE23_LOCK0_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE23_LOCK0_NO_KEY_STATE -// Description : State when at least one key is registered for this page and no -// matching key has been entered. -// 0x0 -> read_only -// 0x1 -> inaccessible -#define OTP_DATA_PAGE23_LOCK0_NO_KEY_STATE_RESET "-" -#define OTP_DATA_PAGE23_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) -#define OTP_DATA_PAGE23_LOCK0_NO_KEY_STATE_MSB _u(6) -#define OTP_DATA_PAGE23_LOCK0_NO_KEY_STATE_LSB _u(6) -#define OTP_DATA_PAGE23_LOCK0_NO_KEY_STATE_ACCESS "RO" -#define OTP_DATA_PAGE23_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) -#define OTP_DATA_PAGE23_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE23_LOCK0_KEY_R -// Description : Index 1-6 of a hardware key which must be entered to grant read -// access, or 0 if no such key is required. -#define OTP_DATA_PAGE23_LOCK0_KEY_R_RESET "-" -#define OTP_DATA_PAGE23_LOCK0_KEY_R_BITS _u(0x00000038) -#define OTP_DATA_PAGE23_LOCK0_KEY_R_MSB _u(5) -#define OTP_DATA_PAGE23_LOCK0_KEY_R_LSB _u(3) -#define OTP_DATA_PAGE23_LOCK0_KEY_R_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE23_LOCK0_KEY_W -// Description : Index 1-6 of a hardware key which must be entered to grant -// write access, or 0 if no such key is required. -#define OTP_DATA_PAGE23_LOCK0_KEY_W_RESET "-" -#define OTP_DATA_PAGE23_LOCK0_KEY_W_BITS _u(0x00000007) -#define OTP_DATA_PAGE23_LOCK0_KEY_W_MSB _u(2) -#define OTP_DATA_PAGE23_LOCK0_KEY_W_LSB _u(0) -#define OTP_DATA_PAGE23_LOCK0_KEY_W_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_PAGE23_LOCK1 -// Description : Lock configuration MSBs for page 23 (rows 0x5c0 through 0x5ff). -// Locks are stored with 3-way majority vote encoding, so that -// bits can be set independently. -// -// This OTP location is always readable, and is write-protected by -// its own permissions. -#define OTP_DATA_PAGE23_LOCK1_ROW _u(0x00000faf) -#define OTP_DATA_PAGE23_LOCK1_BITS _u(0x00ffff3f) -#define OTP_DATA_PAGE23_LOCK1_RESET _u(0x00000000) -#define OTP_DATA_PAGE23_LOCK1_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE23_LOCK1_R2 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE23_LOCK1_R2_RESET "-" -#define OTP_DATA_PAGE23_LOCK1_R2_BITS _u(0x00ff0000) -#define OTP_DATA_PAGE23_LOCK1_R2_MSB _u(23) -#define OTP_DATA_PAGE23_LOCK1_R2_LSB _u(16) -#define OTP_DATA_PAGE23_LOCK1_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE23_LOCK1_R1 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE23_LOCK1_R1_RESET "-" -#define OTP_DATA_PAGE23_LOCK1_R1_BITS _u(0x0000ff00) -#define OTP_DATA_PAGE23_LOCK1_R1_MSB _u(15) -#define OTP_DATA_PAGE23_LOCK1_R1_LSB _u(8) -#define OTP_DATA_PAGE23_LOCK1_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE23_LOCK1_LOCK_BL -// Description : Dummy lock bits reserved for bootloaders (including the RP2350 -// USB bootloader) to store their own OTP access permissions. No -// hardware effect, and no corresponding SW_LOCKx registers. -// 0x0 -> Bootloader permits user reads and writes to this page -// 0x1 -> Bootloader permits user reads of this page -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE -// 0x3 -> Bootloader does not permit user access to this page -#define OTP_DATA_PAGE23_LOCK1_LOCK_BL_RESET "-" -#define OTP_DATA_PAGE23_LOCK1_LOCK_BL_BITS _u(0x00000030) -#define OTP_DATA_PAGE23_LOCK1_LOCK_BL_MSB _u(5) -#define OTP_DATA_PAGE23_LOCK1_LOCK_BL_LSB _u(4) -#define OTP_DATA_PAGE23_LOCK1_LOCK_BL_ACCESS "RO" -#define OTP_DATA_PAGE23_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE23_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE23_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE23_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE23_LOCK1_LOCK_NS -// Description : Lock state for Non-secure accesses to this page. Thermometer- -// coded, so lock state can be advanced permanently from any state -// to any less-permissive state by programming OTP. Software can -// also advance the lock state temporarily (until next OTP reset) -// using the SW_LOCKx registers. -// -// Note that READ_WRITE and READ_ONLY are equivalent in hardware, -// as the SBPI programming interface is not accessible to Non- -// secure software. However, Secure software may check these bits -// to apply write permissions to a Non-secure OTP programming API. -// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. -// 0x1 -> Page can be read by Non-secure software -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. -// 0x3 -> Page can not be accessed by Non-secure software. -#define OTP_DATA_PAGE23_LOCK1_LOCK_NS_RESET "-" -#define OTP_DATA_PAGE23_LOCK1_LOCK_NS_BITS _u(0x0000000c) -#define OTP_DATA_PAGE23_LOCK1_LOCK_NS_MSB _u(3) -#define OTP_DATA_PAGE23_LOCK1_LOCK_NS_LSB _u(2) -#define OTP_DATA_PAGE23_LOCK1_LOCK_NS_ACCESS "RO" -#define OTP_DATA_PAGE23_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE23_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE23_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE23_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE23_LOCK1_LOCK_S -// Description : Lock state for Secure accesses to this page. Thermometer-coded, -// so lock state can be advanced permanently from any state to any -// less-permissive state by programming OTP. Software can also -// advance the lock state temporarily (until next OTP reset) using -// the SW_LOCKx registers. -// 0x0 -> Page is fully accessible by Secure software. -// 0x1 -> Page can be read by Secure software, but can not be written. -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. -// 0x3 -> Page can not be accessed by Secure software. -#define OTP_DATA_PAGE23_LOCK1_LOCK_S_RESET "-" -#define OTP_DATA_PAGE23_LOCK1_LOCK_S_BITS _u(0x00000003) -#define OTP_DATA_PAGE23_LOCK1_LOCK_S_MSB _u(1) -#define OTP_DATA_PAGE23_LOCK1_LOCK_S_LSB _u(0) -#define OTP_DATA_PAGE23_LOCK1_LOCK_S_ACCESS "RO" -#define OTP_DATA_PAGE23_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE23_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE23_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE23_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) -// ============================================================================= -// Register : OTP_DATA_PAGE24_LOCK0 -// Description : Lock configuration LSBs for page 24 (rows 0x600 through 0x63f). -// Locks are stored with 3-way majority vote encoding, so that -// bits can be set independently. -// -// This OTP location is always readable, and is write-protected by -// its own permissions. -#define OTP_DATA_PAGE24_LOCK0_ROW _u(0x00000fb0) -#define OTP_DATA_PAGE24_LOCK0_BITS _u(0x00ffff7f) -#define OTP_DATA_PAGE24_LOCK0_RESET _u(0x00000000) -#define OTP_DATA_PAGE24_LOCK0_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE24_LOCK0_R2 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE24_LOCK0_R2_RESET "-" -#define OTP_DATA_PAGE24_LOCK0_R2_BITS _u(0x00ff0000) -#define OTP_DATA_PAGE24_LOCK0_R2_MSB _u(23) -#define OTP_DATA_PAGE24_LOCK0_R2_LSB _u(16) -#define OTP_DATA_PAGE24_LOCK0_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE24_LOCK0_R1 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE24_LOCK0_R1_RESET "-" -#define OTP_DATA_PAGE24_LOCK0_R1_BITS _u(0x0000ff00) -#define OTP_DATA_PAGE24_LOCK0_R1_MSB _u(15) -#define OTP_DATA_PAGE24_LOCK0_R1_LSB _u(8) -#define OTP_DATA_PAGE24_LOCK0_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE24_LOCK0_NO_KEY_STATE -// Description : State when at least one key is registered for this page and no -// matching key has been entered. -// 0x0 -> read_only -// 0x1 -> inaccessible -#define OTP_DATA_PAGE24_LOCK0_NO_KEY_STATE_RESET "-" -#define OTP_DATA_PAGE24_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) -#define OTP_DATA_PAGE24_LOCK0_NO_KEY_STATE_MSB _u(6) -#define OTP_DATA_PAGE24_LOCK0_NO_KEY_STATE_LSB _u(6) -#define OTP_DATA_PAGE24_LOCK0_NO_KEY_STATE_ACCESS "RO" -#define OTP_DATA_PAGE24_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) -#define OTP_DATA_PAGE24_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE24_LOCK0_KEY_R -// Description : Index 1-6 of a hardware key which must be entered to grant read -// access, or 0 if no such key is required. -#define OTP_DATA_PAGE24_LOCK0_KEY_R_RESET "-" -#define OTP_DATA_PAGE24_LOCK0_KEY_R_BITS _u(0x00000038) -#define OTP_DATA_PAGE24_LOCK0_KEY_R_MSB _u(5) -#define OTP_DATA_PAGE24_LOCK0_KEY_R_LSB _u(3) -#define OTP_DATA_PAGE24_LOCK0_KEY_R_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE24_LOCK0_KEY_W -// Description : Index 1-6 of a hardware key which must be entered to grant -// write access, or 0 if no such key is required. -#define OTP_DATA_PAGE24_LOCK0_KEY_W_RESET "-" -#define OTP_DATA_PAGE24_LOCK0_KEY_W_BITS _u(0x00000007) -#define OTP_DATA_PAGE24_LOCK0_KEY_W_MSB _u(2) -#define OTP_DATA_PAGE24_LOCK0_KEY_W_LSB _u(0) -#define OTP_DATA_PAGE24_LOCK0_KEY_W_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_PAGE24_LOCK1 -// Description : Lock configuration MSBs for page 24 (rows 0x600 through 0x63f). -// Locks are stored with 3-way majority vote encoding, so that -// bits can be set independently. -// -// This OTP location is always readable, and is write-protected by -// its own permissions. -#define OTP_DATA_PAGE24_LOCK1_ROW _u(0x00000fb1) -#define OTP_DATA_PAGE24_LOCK1_BITS _u(0x00ffff3f) -#define OTP_DATA_PAGE24_LOCK1_RESET _u(0x00000000) -#define OTP_DATA_PAGE24_LOCK1_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE24_LOCK1_R2 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE24_LOCK1_R2_RESET "-" -#define OTP_DATA_PAGE24_LOCK1_R2_BITS _u(0x00ff0000) -#define OTP_DATA_PAGE24_LOCK1_R2_MSB _u(23) -#define OTP_DATA_PAGE24_LOCK1_R2_LSB _u(16) -#define OTP_DATA_PAGE24_LOCK1_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE24_LOCK1_R1 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE24_LOCK1_R1_RESET "-" -#define OTP_DATA_PAGE24_LOCK1_R1_BITS _u(0x0000ff00) -#define OTP_DATA_PAGE24_LOCK1_R1_MSB _u(15) -#define OTP_DATA_PAGE24_LOCK1_R1_LSB _u(8) -#define OTP_DATA_PAGE24_LOCK1_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE24_LOCK1_LOCK_BL -// Description : Dummy lock bits reserved for bootloaders (including the RP2350 -// USB bootloader) to store their own OTP access permissions. No -// hardware effect, and no corresponding SW_LOCKx registers. -// 0x0 -> Bootloader permits user reads and writes to this page -// 0x1 -> Bootloader permits user reads of this page -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE -// 0x3 -> Bootloader does not permit user access to this page -#define OTP_DATA_PAGE24_LOCK1_LOCK_BL_RESET "-" -#define OTP_DATA_PAGE24_LOCK1_LOCK_BL_BITS _u(0x00000030) -#define OTP_DATA_PAGE24_LOCK1_LOCK_BL_MSB _u(5) -#define OTP_DATA_PAGE24_LOCK1_LOCK_BL_LSB _u(4) -#define OTP_DATA_PAGE24_LOCK1_LOCK_BL_ACCESS "RO" -#define OTP_DATA_PAGE24_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE24_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE24_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE24_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE24_LOCK1_LOCK_NS -// Description : Lock state for Non-secure accesses to this page. Thermometer- -// coded, so lock state can be advanced permanently from any state -// to any less-permissive state by programming OTP. Software can -// also advance the lock state temporarily (until next OTP reset) -// using the SW_LOCKx registers. -// -// Note that READ_WRITE and READ_ONLY are equivalent in hardware, -// as the SBPI programming interface is not accessible to Non- -// secure software. However, Secure software may check these bits -// to apply write permissions to a Non-secure OTP programming API. -// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. -// 0x1 -> Page can be read by Non-secure software -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. -// 0x3 -> Page can not be accessed by Non-secure software. -#define OTP_DATA_PAGE24_LOCK1_LOCK_NS_RESET "-" -#define OTP_DATA_PAGE24_LOCK1_LOCK_NS_BITS _u(0x0000000c) -#define OTP_DATA_PAGE24_LOCK1_LOCK_NS_MSB _u(3) -#define OTP_DATA_PAGE24_LOCK1_LOCK_NS_LSB _u(2) -#define OTP_DATA_PAGE24_LOCK1_LOCK_NS_ACCESS "RO" -#define OTP_DATA_PAGE24_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE24_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE24_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE24_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE24_LOCK1_LOCK_S -// Description : Lock state for Secure accesses to this page. Thermometer-coded, -// so lock state can be advanced permanently from any state to any -// less-permissive state by programming OTP. Software can also -// advance the lock state temporarily (until next OTP reset) using -// the SW_LOCKx registers. -// 0x0 -> Page is fully accessible by Secure software. -// 0x1 -> Page can be read by Secure software, but can not be written. -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. -// 0x3 -> Page can not be accessed by Secure software. -#define OTP_DATA_PAGE24_LOCK1_LOCK_S_RESET "-" -#define OTP_DATA_PAGE24_LOCK1_LOCK_S_BITS _u(0x00000003) -#define OTP_DATA_PAGE24_LOCK1_LOCK_S_MSB _u(1) -#define OTP_DATA_PAGE24_LOCK1_LOCK_S_LSB _u(0) -#define OTP_DATA_PAGE24_LOCK1_LOCK_S_ACCESS "RO" -#define OTP_DATA_PAGE24_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE24_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE24_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE24_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) -// ============================================================================= -// Register : OTP_DATA_PAGE25_LOCK0 -// Description : Lock configuration LSBs for page 25 (rows 0x640 through 0x67f). -// Locks are stored with 3-way majority vote encoding, so that -// bits can be set independently. -// -// This OTP location is always readable, and is write-protected by -// its own permissions. -#define OTP_DATA_PAGE25_LOCK0_ROW _u(0x00000fb2) -#define OTP_DATA_PAGE25_LOCK0_BITS _u(0x00ffff7f) -#define OTP_DATA_PAGE25_LOCK0_RESET _u(0x00000000) -#define OTP_DATA_PAGE25_LOCK0_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE25_LOCK0_R2 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE25_LOCK0_R2_RESET "-" -#define OTP_DATA_PAGE25_LOCK0_R2_BITS _u(0x00ff0000) -#define OTP_DATA_PAGE25_LOCK0_R2_MSB _u(23) -#define OTP_DATA_PAGE25_LOCK0_R2_LSB _u(16) -#define OTP_DATA_PAGE25_LOCK0_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE25_LOCK0_R1 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE25_LOCK0_R1_RESET "-" -#define OTP_DATA_PAGE25_LOCK0_R1_BITS _u(0x0000ff00) -#define OTP_DATA_PAGE25_LOCK0_R1_MSB _u(15) -#define OTP_DATA_PAGE25_LOCK0_R1_LSB _u(8) -#define OTP_DATA_PAGE25_LOCK0_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE25_LOCK0_NO_KEY_STATE -// Description : State when at least one key is registered for this page and no -// matching key has been entered. -// 0x0 -> read_only -// 0x1 -> inaccessible -#define OTP_DATA_PAGE25_LOCK0_NO_KEY_STATE_RESET "-" -#define OTP_DATA_PAGE25_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) -#define OTP_DATA_PAGE25_LOCK0_NO_KEY_STATE_MSB _u(6) -#define OTP_DATA_PAGE25_LOCK0_NO_KEY_STATE_LSB _u(6) -#define OTP_DATA_PAGE25_LOCK0_NO_KEY_STATE_ACCESS "RO" -#define OTP_DATA_PAGE25_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) -#define OTP_DATA_PAGE25_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE25_LOCK0_KEY_R -// Description : Index 1-6 of a hardware key which must be entered to grant read -// access, or 0 if no such key is required. -#define OTP_DATA_PAGE25_LOCK0_KEY_R_RESET "-" -#define OTP_DATA_PAGE25_LOCK0_KEY_R_BITS _u(0x00000038) -#define OTP_DATA_PAGE25_LOCK0_KEY_R_MSB _u(5) -#define OTP_DATA_PAGE25_LOCK0_KEY_R_LSB _u(3) -#define OTP_DATA_PAGE25_LOCK0_KEY_R_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE25_LOCK0_KEY_W -// Description : Index 1-6 of a hardware key which must be entered to grant -// write access, or 0 if no such key is required. -#define OTP_DATA_PAGE25_LOCK0_KEY_W_RESET "-" -#define OTP_DATA_PAGE25_LOCK0_KEY_W_BITS _u(0x00000007) -#define OTP_DATA_PAGE25_LOCK0_KEY_W_MSB _u(2) -#define OTP_DATA_PAGE25_LOCK0_KEY_W_LSB _u(0) -#define OTP_DATA_PAGE25_LOCK0_KEY_W_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_PAGE25_LOCK1 -// Description : Lock configuration MSBs for page 25 (rows 0x640 through 0x67f). -// Locks are stored with 3-way majority vote encoding, so that -// bits can be set independently. -// -// This OTP location is always readable, and is write-protected by -// its own permissions. -#define OTP_DATA_PAGE25_LOCK1_ROW _u(0x00000fb3) -#define OTP_DATA_PAGE25_LOCK1_BITS _u(0x00ffff3f) -#define OTP_DATA_PAGE25_LOCK1_RESET _u(0x00000000) -#define OTP_DATA_PAGE25_LOCK1_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE25_LOCK1_R2 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE25_LOCK1_R2_RESET "-" -#define OTP_DATA_PAGE25_LOCK1_R2_BITS _u(0x00ff0000) -#define OTP_DATA_PAGE25_LOCK1_R2_MSB _u(23) -#define OTP_DATA_PAGE25_LOCK1_R2_LSB _u(16) -#define OTP_DATA_PAGE25_LOCK1_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE25_LOCK1_R1 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE25_LOCK1_R1_RESET "-" -#define OTP_DATA_PAGE25_LOCK1_R1_BITS _u(0x0000ff00) -#define OTP_DATA_PAGE25_LOCK1_R1_MSB _u(15) -#define OTP_DATA_PAGE25_LOCK1_R1_LSB _u(8) -#define OTP_DATA_PAGE25_LOCK1_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE25_LOCK1_LOCK_BL -// Description : Dummy lock bits reserved for bootloaders (including the RP2350 -// USB bootloader) to store their own OTP access permissions. No -// hardware effect, and no corresponding SW_LOCKx registers. -// 0x0 -> Bootloader permits user reads and writes to this page -// 0x1 -> Bootloader permits user reads of this page -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE -// 0x3 -> Bootloader does not permit user access to this page -#define OTP_DATA_PAGE25_LOCK1_LOCK_BL_RESET "-" -#define OTP_DATA_PAGE25_LOCK1_LOCK_BL_BITS _u(0x00000030) -#define OTP_DATA_PAGE25_LOCK1_LOCK_BL_MSB _u(5) -#define OTP_DATA_PAGE25_LOCK1_LOCK_BL_LSB _u(4) -#define OTP_DATA_PAGE25_LOCK1_LOCK_BL_ACCESS "RO" -#define OTP_DATA_PAGE25_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE25_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE25_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE25_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE25_LOCK1_LOCK_NS -// Description : Lock state for Non-secure accesses to this page. Thermometer- -// coded, so lock state can be advanced permanently from any state -// to any less-permissive state by programming OTP. Software can -// also advance the lock state temporarily (until next OTP reset) -// using the SW_LOCKx registers. -// -// Note that READ_WRITE and READ_ONLY are equivalent in hardware, -// as the SBPI programming interface is not accessible to Non- -// secure software. However, Secure software may check these bits -// to apply write permissions to a Non-secure OTP programming API. -// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. -// 0x1 -> Page can be read by Non-secure software -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. -// 0x3 -> Page can not be accessed by Non-secure software. -#define OTP_DATA_PAGE25_LOCK1_LOCK_NS_RESET "-" -#define OTP_DATA_PAGE25_LOCK1_LOCK_NS_BITS _u(0x0000000c) -#define OTP_DATA_PAGE25_LOCK1_LOCK_NS_MSB _u(3) -#define OTP_DATA_PAGE25_LOCK1_LOCK_NS_LSB _u(2) -#define OTP_DATA_PAGE25_LOCK1_LOCK_NS_ACCESS "RO" -#define OTP_DATA_PAGE25_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE25_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE25_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE25_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE25_LOCK1_LOCK_S -// Description : Lock state for Secure accesses to this page. Thermometer-coded, -// so lock state can be advanced permanently from any state to any -// less-permissive state by programming OTP. Software can also -// advance the lock state temporarily (until next OTP reset) using -// the SW_LOCKx registers. -// 0x0 -> Page is fully accessible by Secure software. -// 0x1 -> Page can be read by Secure software, but can not be written. -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. -// 0x3 -> Page can not be accessed by Secure software. -#define OTP_DATA_PAGE25_LOCK1_LOCK_S_RESET "-" -#define OTP_DATA_PAGE25_LOCK1_LOCK_S_BITS _u(0x00000003) -#define OTP_DATA_PAGE25_LOCK1_LOCK_S_MSB _u(1) -#define OTP_DATA_PAGE25_LOCK1_LOCK_S_LSB _u(0) -#define OTP_DATA_PAGE25_LOCK1_LOCK_S_ACCESS "RO" -#define OTP_DATA_PAGE25_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE25_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE25_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE25_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) -// ============================================================================= -// Register : OTP_DATA_PAGE26_LOCK0 -// Description : Lock configuration LSBs for page 26 (rows 0x680 through 0x6bf). -// Locks are stored with 3-way majority vote encoding, so that -// bits can be set independently. -// -// This OTP location is always readable, and is write-protected by -// its own permissions. -#define OTP_DATA_PAGE26_LOCK0_ROW _u(0x00000fb4) -#define OTP_DATA_PAGE26_LOCK0_BITS _u(0x00ffff7f) -#define OTP_DATA_PAGE26_LOCK0_RESET _u(0x00000000) -#define OTP_DATA_PAGE26_LOCK0_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE26_LOCK0_R2 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE26_LOCK0_R2_RESET "-" -#define OTP_DATA_PAGE26_LOCK0_R2_BITS _u(0x00ff0000) -#define OTP_DATA_PAGE26_LOCK0_R2_MSB _u(23) -#define OTP_DATA_PAGE26_LOCK0_R2_LSB _u(16) -#define OTP_DATA_PAGE26_LOCK0_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE26_LOCK0_R1 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE26_LOCK0_R1_RESET "-" -#define OTP_DATA_PAGE26_LOCK0_R1_BITS _u(0x0000ff00) -#define OTP_DATA_PAGE26_LOCK0_R1_MSB _u(15) -#define OTP_DATA_PAGE26_LOCK0_R1_LSB _u(8) -#define OTP_DATA_PAGE26_LOCK0_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE26_LOCK0_NO_KEY_STATE -// Description : State when at least one key is registered for this page and no -// matching key has been entered. -// 0x0 -> read_only -// 0x1 -> inaccessible -#define OTP_DATA_PAGE26_LOCK0_NO_KEY_STATE_RESET "-" -#define OTP_DATA_PAGE26_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) -#define OTP_DATA_PAGE26_LOCK0_NO_KEY_STATE_MSB _u(6) -#define OTP_DATA_PAGE26_LOCK0_NO_KEY_STATE_LSB _u(6) -#define OTP_DATA_PAGE26_LOCK0_NO_KEY_STATE_ACCESS "RO" -#define OTP_DATA_PAGE26_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) -#define OTP_DATA_PAGE26_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE26_LOCK0_KEY_R -// Description : Index 1-6 of a hardware key which must be entered to grant read -// access, or 0 if no such key is required. -#define OTP_DATA_PAGE26_LOCK0_KEY_R_RESET "-" -#define OTP_DATA_PAGE26_LOCK0_KEY_R_BITS _u(0x00000038) -#define OTP_DATA_PAGE26_LOCK0_KEY_R_MSB _u(5) -#define OTP_DATA_PAGE26_LOCK0_KEY_R_LSB _u(3) -#define OTP_DATA_PAGE26_LOCK0_KEY_R_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE26_LOCK0_KEY_W -// Description : Index 1-6 of a hardware key which must be entered to grant -// write access, or 0 if no such key is required. -#define OTP_DATA_PAGE26_LOCK0_KEY_W_RESET "-" -#define OTP_DATA_PAGE26_LOCK0_KEY_W_BITS _u(0x00000007) -#define OTP_DATA_PAGE26_LOCK0_KEY_W_MSB _u(2) -#define OTP_DATA_PAGE26_LOCK0_KEY_W_LSB _u(0) -#define OTP_DATA_PAGE26_LOCK0_KEY_W_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_PAGE26_LOCK1 -// Description : Lock configuration MSBs for page 26 (rows 0x680 through 0x6bf). -// Locks are stored with 3-way majority vote encoding, so that -// bits can be set independently. -// -// This OTP location is always readable, and is write-protected by -// its own permissions. -#define OTP_DATA_PAGE26_LOCK1_ROW _u(0x00000fb5) -#define OTP_DATA_PAGE26_LOCK1_BITS _u(0x00ffff3f) -#define OTP_DATA_PAGE26_LOCK1_RESET _u(0x00000000) -#define OTP_DATA_PAGE26_LOCK1_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE26_LOCK1_R2 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE26_LOCK1_R2_RESET "-" -#define OTP_DATA_PAGE26_LOCK1_R2_BITS _u(0x00ff0000) -#define OTP_DATA_PAGE26_LOCK1_R2_MSB _u(23) -#define OTP_DATA_PAGE26_LOCK1_R2_LSB _u(16) -#define OTP_DATA_PAGE26_LOCK1_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE26_LOCK1_R1 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE26_LOCK1_R1_RESET "-" -#define OTP_DATA_PAGE26_LOCK1_R1_BITS _u(0x0000ff00) -#define OTP_DATA_PAGE26_LOCK1_R1_MSB _u(15) -#define OTP_DATA_PAGE26_LOCK1_R1_LSB _u(8) -#define OTP_DATA_PAGE26_LOCK1_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE26_LOCK1_LOCK_BL -// Description : Dummy lock bits reserved for bootloaders (including the RP2350 -// USB bootloader) to store their own OTP access permissions. No -// hardware effect, and no corresponding SW_LOCKx registers. -// 0x0 -> Bootloader permits user reads and writes to this page -// 0x1 -> Bootloader permits user reads of this page -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE -// 0x3 -> Bootloader does not permit user access to this page -#define OTP_DATA_PAGE26_LOCK1_LOCK_BL_RESET "-" -#define OTP_DATA_PAGE26_LOCK1_LOCK_BL_BITS _u(0x00000030) -#define OTP_DATA_PAGE26_LOCK1_LOCK_BL_MSB _u(5) -#define OTP_DATA_PAGE26_LOCK1_LOCK_BL_LSB _u(4) -#define OTP_DATA_PAGE26_LOCK1_LOCK_BL_ACCESS "RO" -#define OTP_DATA_PAGE26_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE26_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE26_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE26_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE26_LOCK1_LOCK_NS -// Description : Lock state for Non-secure accesses to this page. Thermometer- -// coded, so lock state can be advanced permanently from any state -// to any less-permissive state by programming OTP. Software can -// also advance the lock state temporarily (until next OTP reset) -// using the SW_LOCKx registers. -// -// Note that READ_WRITE and READ_ONLY are equivalent in hardware, -// as the SBPI programming interface is not accessible to Non- -// secure software. However, Secure software may check these bits -// to apply write permissions to a Non-secure OTP programming API. -// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. -// 0x1 -> Page can be read by Non-secure software -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. -// 0x3 -> Page can not be accessed by Non-secure software. -#define OTP_DATA_PAGE26_LOCK1_LOCK_NS_RESET "-" -#define OTP_DATA_PAGE26_LOCK1_LOCK_NS_BITS _u(0x0000000c) -#define OTP_DATA_PAGE26_LOCK1_LOCK_NS_MSB _u(3) -#define OTP_DATA_PAGE26_LOCK1_LOCK_NS_LSB _u(2) -#define OTP_DATA_PAGE26_LOCK1_LOCK_NS_ACCESS "RO" -#define OTP_DATA_PAGE26_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE26_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE26_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE26_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE26_LOCK1_LOCK_S -// Description : Lock state for Secure accesses to this page. Thermometer-coded, -// so lock state can be advanced permanently from any state to any -// less-permissive state by programming OTP. Software can also -// advance the lock state temporarily (until next OTP reset) using -// the SW_LOCKx registers. -// 0x0 -> Page is fully accessible by Secure software. -// 0x1 -> Page can be read by Secure software, but can not be written. -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. -// 0x3 -> Page can not be accessed by Secure software. -#define OTP_DATA_PAGE26_LOCK1_LOCK_S_RESET "-" -#define OTP_DATA_PAGE26_LOCK1_LOCK_S_BITS _u(0x00000003) -#define OTP_DATA_PAGE26_LOCK1_LOCK_S_MSB _u(1) -#define OTP_DATA_PAGE26_LOCK1_LOCK_S_LSB _u(0) -#define OTP_DATA_PAGE26_LOCK1_LOCK_S_ACCESS "RO" -#define OTP_DATA_PAGE26_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE26_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE26_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE26_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) -// ============================================================================= -// Register : OTP_DATA_PAGE27_LOCK0 -// Description : Lock configuration LSBs for page 27 (rows 0x6c0 through 0x6ff). -// Locks are stored with 3-way majority vote encoding, so that -// bits can be set independently. -// -// This OTP location is always readable, and is write-protected by -// its own permissions. -#define OTP_DATA_PAGE27_LOCK0_ROW _u(0x00000fb6) -#define OTP_DATA_PAGE27_LOCK0_BITS _u(0x00ffff7f) -#define OTP_DATA_PAGE27_LOCK0_RESET _u(0x00000000) -#define OTP_DATA_PAGE27_LOCK0_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE27_LOCK0_R2 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE27_LOCK0_R2_RESET "-" -#define OTP_DATA_PAGE27_LOCK0_R2_BITS _u(0x00ff0000) -#define OTP_DATA_PAGE27_LOCK0_R2_MSB _u(23) -#define OTP_DATA_PAGE27_LOCK0_R2_LSB _u(16) -#define OTP_DATA_PAGE27_LOCK0_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE27_LOCK0_R1 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE27_LOCK0_R1_RESET "-" -#define OTP_DATA_PAGE27_LOCK0_R1_BITS _u(0x0000ff00) -#define OTP_DATA_PAGE27_LOCK0_R1_MSB _u(15) -#define OTP_DATA_PAGE27_LOCK0_R1_LSB _u(8) -#define OTP_DATA_PAGE27_LOCK0_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE27_LOCK0_NO_KEY_STATE -// Description : State when at least one key is registered for this page and no -// matching key has been entered. -// 0x0 -> read_only -// 0x1 -> inaccessible -#define OTP_DATA_PAGE27_LOCK0_NO_KEY_STATE_RESET "-" -#define OTP_DATA_PAGE27_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) -#define OTP_DATA_PAGE27_LOCK0_NO_KEY_STATE_MSB _u(6) -#define OTP_DATA_PAGE27_LOCK0_NO_KEY_STATE_LSB _u(6) -#define OTP_DATA_PAGE27_LOCK0_NO_KEY_STATE_ACCESS "RO" -#define OTP_DATA_PAGE27_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) -#define OTP_DATA_PAGE27_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE27_LOCK0_KEY_R -// Description : Index 1-6 of a hardware key which must be entered to grant read -// access, or 0 if no such key is required. -#define OTP_DATA_PAGE27_LOCK0_KEY_R_RESET "-" -#define OTP_DATA_PAGE27_LOCK0_KEY_R_BITS _u(0x00000038) -#define OTP_DATA_PAGE27_LOCK0_KEY_R_MSB _u(5) -#define OTP_DATA_PAGE27_LOCK0_KEY_R_LSB _u(3) -#define OTP_DATA_PAGE27_LOCK0_KEY_R_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE27_LOCK0_KEY_W -// Description : Index 1-6 of a hardware key which must be entered to grant -// write access, or 0 if no such key is required. -#define OTP_DATA_PAGE27_LOCK0_KEY_W_RESET "-" -#define OTP_DATA_PAGE27_LOCK0_KEY_W_BITS _u(0x00000007) -#define OTP_DATA_PAGE27_LOCK0_KEY_W_MSB _u(2) -#define OTP_DATA_PAGE27_LOCK0_KEY_W_LSB _u(0) -#define OTP_DATA_PAGE27_LOCK0_KEY_W_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_PAGE27_LOCK1 -// Description : Lock configuration MSBs for page 27 (rows 0x6c0 through 0x6ff). -// Locks are stored with 3-way majority vote encoding, so that -// bits can be set independently. -// -// This OTP location is always readable, and is write-protected by -// its own permissions. -#define OTP_DATA_PAGE27_LOCK1_ROW _u(0x00000fb7) -#define OTP_DATA_PAGE27_LOCK1_BITS _u(0x00ffff3f) -#define OTP_DATA_PAGE27_LOCK1_RESET _u(0x00000000) -#define OTP_DATA_PAGE27_LOCK1_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE27_LOCK1_R2 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE27_LOCK1_R2_RESET "-" -#define OTP_DATA_PAGE27_LOCK1_R2_BITS _u(0x00ff0000) -#define OTP_DATA_PAGE27_LOCK1_R2_MSB _u(23) -#define OTP_DATA_PAGE27_LOCK1_R2_LSB _u(16) -#define OTP_DATA_PAGE27_LOCK1_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE27_LOCK1_R1 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE27_LOCK1_R1_RESET "-" -#define OTP_DATA_PAGE27_LOCK1_R1_BITS _u(0x0000ff00) -#define OTP_DATA_PAGE27_LOCK1_R1_MSB _u(15) -#define OTP_DATA_PAGE27_LOCK1_R1_LSB _u(8) -#define OTP_DATA_PAGE27_LOCK1_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE27_LOCK1_LOCK_BL -// Description : Dummy lock bits reserved for bootloaders (including the RP2350 -// USB bootloader) to store their own OTP access permissions. No -// hardware effect, and no corresponding SW_LOCKx registers. -// 0x0 -> Bootloader permits user reads and writes to this page -// 0x1 -> Bootloader permits user reads of this page -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE -// 0x3 -> Bootloader does not permit user access to this page -#define OTP_DATA_PAGE27_LOCK1_LOCK_BL_RESET "-" -#define OTP_DATA_PAGE27_LOCK1_LOCK_BL_BITS _u(0x00000030) -#define OTP_DATA_PAGE27_LOCK1_LOCK_BL_MSB _u(5) -#define OTP_DATA_PAGE27_LOCK1_LOCK_BL_LSB _u(4) -#define OTP_DATA_PAGE27_LOCK1_LOCK_BL_ACCESS "RO" -#define OTP_DATA_PAGE27_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE27_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE27_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE27_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE27_LOCK1_LOCK_NS -// Description : Lock state for Non-secure accesses to this page. Thermometer- -// coded, so lock state can be advanced permanently from any state -// to any less-permissive state by programming OTP. Software can -// also advance the lock state temporarily (until next OTP reset) -// using the SW_LOCKx registers. -// -// Note that READ_WRITE and READ_ONLY are equivalent in hardware, -// as the SBPI programming interface is not accessible to Non- -// secure software. However, Secure software may check these bits -// to apply write permissions to a Non-secure OTP programming API. -// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. -// 0x1 -> Page can be read by Non-secure software -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. -// 0x3 -> Page can not be accessed by Non-secure software. -#define OTP_DATA_PAGE27_LOCK1_LOCK_NS_RESET "-" -#define OTP_DATA_PAGE27_LOCK1_LOCK_NS_BITS _u(0x0000000c) -#define OTP_DATA_PAGE27_LOCK1_LOCK_NS_MSB _u(3) -#define OTP_DATA_PAGE27_LOCK1_LOCK_NS_LSB _u(2) -#define OTP_DATA_PAGE27_LOCK1_LOCK_NS_ACCESS "RO" -#define OTP_DATA_PAGE27_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE27_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE27_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE27_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE27_LOCK1_LOCK_S -// Description : Lock state for Secure accesses to this page. Thermometer-coded, -// so lock state can be advanced permanently from any state to any -// less-permissive state by programming OTP. Software can also -// advance the lock state temporarily (until next OTP reset) using -// the SW_LOCKx registers. -// 0x0 -> Page is fully accessible by Secure software. -// 0x1 -> Page can be read by Secure software, but can not be written. -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. -// 0x3 -> Page can not be accessed by Secure software. -#define OTP_DATA_PAGE27_LOCK1_LOCK_S_RESET "-" -#define OTP_DATA_PAGE27_LOCK1_LOCK_S_BITS _u(0x00000003) -#define OTP_DATA_PAGE27_LOCK1_LOCK_S_MSB _u(1) -#define OTP_DATA_PAGE27_LOCK1_LOCK_S_LSB _u(0) -#define OTP_DATA_PAGE27_LOCK1_LOCK_S_ACCESS "RO" -#define OTP_DATA_PAGE27_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE27_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE27_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE27_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) -// ============================================================================= -// Register : OTP_DATA_PAGE28_LOCK0 -// Description : Lock configuration LSBs for page 28 (rows 0x700 through 0x73f). -// Locks are stored with 3-way majority vote encoding, so that -// bits can be set independently. -// -// This OTP location is always readable, and is write-protected by -// its own permissions. -#define OTP_DATA_PAGE28_LOCK0_ROW _u(0x00000fb8) -#define OTP_DATA_PAGE28_LOCK0_BITS _u(0x00ffff7f) -#define OTP_DATA_PAGE28_LOCK0_RESET _u(0x00000000) -#define OTP_DATA_PAGE28_LOCK0_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE28_LOCK0_R2 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE28_LOCK0_R2_RESET "-" -#define OTP_DATA_PAGE28_LOCK0_R2_BITS _u(0x00ff0000) -#define OTP_DATA_PAGE28_LOCK0_R2_MSB _u(23) -#define OTP_DATA_PAGE28_LOCK0_R2_LSB _u(16) -#define OTP_DATA_PAGE28_LOCK0_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE28_LOCK0_R1 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE28_LOCK0_R1_RESET "-" -#define OTP_DATA_PAGE28_LOCK0_R1_BITS _u(0x0000ff00) -#define OTP_DATA_PAGE28_LOCK0_R1_MSB _u(15) -#define OTP_DATA_PAGE28_LOCK0_R1_LSB _u(8) -#define OTP_DATA_PAGE28_LOCK0_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE28_LOCK0_NO_KEY_STATE -// Description : State when at least one key is registered for this page and no -// matching key has been entered. -// 0x0 -> read_only -// 0x1 -> inaccessible -#define OTP_DATA_PAGE28_LOCK0_NO_KEY_STATE_RESET "-" -#define OTP_DATA_PAGE28_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) -#define OTP_DATA_PAGE28_LOCK0_NO_KEY_STATE_MSB _u(6) -#define OTP_DATA_PAGE28_LOCK0_NO_KEY_STATE_LSB _u(6) -#define OTP_DATA_PAGE28_LOCK0_NO_KEY_STATE_ACCESS "RO" -#define OTP_DATA_PAGE28_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) -#define OTP_DATA_PAGE28_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE28_LOCK0_KEY_R -// Description : Index 1-6 of a hardware key which must be entered to grant read -// access, or 0 if no such key is required. -#define OTP_DATA_PAGE28_LOCK0_KEY_R_RESET "-" -#define OTP_DATA_PAGE28_LOCK0_KEY_R_BITS _u(0x00000038) -#define OTP_DATA_PAGE28_LOCK0_KEY_R_MSB _u(5) -#define OTP_DATA_PAGE28_LOCK0_KEY_R_LSB _u(3) -#define OTP_DATA_PAGE28_LOCK0_KEY_R_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE28_LOCK0_KEY_W -// Description : Index 1-6 of a hardware key which must be entered to grant -// write access, or 0 if no such key is required. -#define OTP_DATA_PAGE28_LOCK0_KEY_W_RESET "-" -#define OTP_DATA_PAGE28_LOCK0_KEY_W_BITS _u(0x00000007) -#define OTP_DATA_PAGE28_LOCK0_KEY_W_MSB _u(2) -#define OTP_DATA_PAGE28_LOCK0_KEY_W_LSB _u(0) -#define OTP_DATA_PAGE28_LOCK0_KEY_W_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_PAGE28_LOCK1 -// Description : Lock configuration MSBs for page 28 (rows 0x700 through 0x73f). -// Locks are stored with 3-way majority vote encoding, so that -// bits can be set independently. -// -// This OTP location is always readable, and is write-protected by -// its own permissions. -#define OTP_DATA_PAGE28_LOCK1_ROW _u(0x00000fb9) -#define OTP_DATA_PAGE28_LOCK1_BITS _u(0x00ffff3f) -#define OTP_DATA_PAGE28_LOCK1_RESET _u(0x00000000) -#define OTP_DATA_PAGE28_LOCK1_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE28_LOCK1_R2 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE28_LOCK1_R2_RESET "-" -#define OTP_DATA_PAGE28_LOCK1_R2_BITS _u(0x00ff0000) -#define OTP_DATA_PAGE28_LOCK1_R2_MSB _u(23) -#define OTP_DATA_PAGE28_LOCK1_R2_LSB _u(16) -#define OTP_DATA_PAGE28_LOCK1_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE28_LOCK1_R1 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE28_LOCK1_R1_RESET "-" -#define OTP_DATA_PAGE28_LOCK1_R1_BITS _u(0x0000ff00) -#define OTP_DATA_PAGE28_LOCK1_R1_MSB _u(15) -#define OTP_DATA_PAGE28_LOCK1_R1_LSB _u(8) -#define OTP_DATA_PAGE28_LOCK1_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE28_LOCK1_LOCK_BL -// Description : Dummy lock bits reserved for bootloaders (including the RP2350 -// USB bootloader) to store their own OTP access permissions. No -// hardware effect, and no corresponding SW_LOCKx registers. -// 0x0 -> Bootloader permits user reads and writes to this page -// 0x1 -> Bootloader permits user reads of this page -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE -// 0x3 -> Bootloader does not permit user access to this page -#define OTP_DATA_PAGE28_LOCK1_LOCK_BL_RESET "-" -#define OTP_DATA_PAGE28_LOCK1_LOCK_BL_BITS _u(0x00000030) -#define OTP_DATA_PAGE28_LOCK1_LOCK_BL_MSB _u(5) -#define OTP_DATA_PAGE28_LOCK1_LOCK_BL_LSB _u(4) -#define OTP_DATA_PAGE28_LOCK1_LOCK_BL_ACCESS "RO" -#define OTP_DATA_PAGE28_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE28_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE28_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE28_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE28_LOCK1_LOCK_NS -// Description : Lock state for Non-secure accesses to this page. Thermometer- -// coded, so lock state can be advanced permanently from any state -// to any less-permissive state by programming OTP. Software can -// also advance the lock state temporarily (until next OTP reset) -// using the SW_LOCKx registers. -// -// Note that READ_WRITE and READ_ONLY are equivalent in hardware, -// as the SBPI programming interface is not accessible to Non- -// secure software. However, Secure software may check these bits -// to apply write permissions to a Non-secure OTP programming API. -// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. -// 0x1 -> Page can be read by Non-secure software -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. -// 0x3 -> Page can not be accessed by Non-secure software. -#define OTP_DATA_PAGE28_LOCK1_LOCK_NS_RESET "-" -#define OTP_DATA_PAGE28_LOCK1_LOCK_NS_BITS _u(0x0000000c) -#define OTP_DATA_PAGE28_LOCK1_LOCK_NS_MSB _u(3) -#define OTP_DATA_PAGE28_LOCK1_LOCK_NS_LSB _u(2) -#define OTP_DATA_PAGE28_LOCK1_LOCK_NS_ACCESS "RO" -#define OTP_DATA_PAGE28_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE28_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE28_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE28_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE28_LOCK1_LOCK_S -// Description : Lock state for Secure accesses to this page. Thermometer-coded, -// so lock state can be advanced permanently from any state to any -// less-permissive state by programming OTP. Software can also -// advance the lock state temporarily (until next OTP reset) using -// the SW_LOCKx registers. -// 0x0 -> Page is fully accessible by Secure software. -// 0x1 -> Page can be read by Secure software, but can not be written. -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. -// 0x3 -> Page can not be accessed by Secure software. -#define OTP_DATA_PAGE28_LOCK1_LOCK_S_RESET "-" -#define OTP_DATA_PAGE28_LOCK1_LOCK_S_BITS _u(0x00000003) -#define OTP_DATA_PAGE28_LOCK1_LOCK_S_MSB _u(1) -#define OTP_DATA_PAGE28_LOCK1_LOCK_S_LSB _u(0) -#define OTP_DATA_PAGE28_LOCK1_LOCK_S_ACCESS "RO" -#define OTP_DATA_PAGE28_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE28_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE28_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE28_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) -// ============================================================================= -// Register : OTP_DATA_PAGE29_LOCK0 -// Description : Lock configuration LSBs for page 29 (rows 0x740 through 0x77f). -// Locks are stored with 3-way majority vote encoding, so that -// bits can be set independently. -// -// This OTP location is always readable, and is write-protected by -// its own permissions. -#define OTP_DATA_PAGE29_LOCK0_ROW _u(0x00000fba) -#define OTP_DATA_PAGE29_LOCK0_BITS _u(0x00ffff7f) -#define OTP_DATA_PAGE29_LOCK0_RESET _u(0x00000000) -#define OTP_DATA_PAGE29_LOCK0_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE29_LOCK0_R2 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE29_LOCK0_R2_RESET "-" -#define OTP_DATA_PAGE29_LOCK0_R2_BITS _u(0x00ff0000) -#define OTP_DATA_PAGE29_LOCK0_R2_MSB _u(23) -#define OTP_DATA_PAGE29_LOCK0_R2_LSB _u(16) -#define OTP_DATA_PAGE29_LOCK0_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE29_LOCK0_R1 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE29_LOCK0_R1_RESET "-" -#define OTP_DATA_PAGE29_LOCK0_R1_BITS _u(0x0000ff00) -#define OTP_DATA_PAGE29_LOCK0_R1_MSB _u(15) -#define OTP_DATA_PAGE29_LOCK0_R1_LSB _u(8) -#define OTP_DATA_PAGE29_LOCK0_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE29_LOCK0_NO_KEY_STATE -// Description : State when at least one key is registered for this page and no -// matching key has been entered. -// 0x0 -> read_only -// 0x1 -> inaccessible -#define OTP_DATA_PAGE29_LOCK0_NO_KEY_STATE_RESET "-" -#define OTP_DATA_PAGE29_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) -#define OTP_DATA_PAGE29_LOCK0_NO_KEY_STATE_MSB _u(6) -#define OTP_DATA_PAGE29_LOCK0_NO_KEY_STATE_LSB _u(6) -#define OTP_DATA_PAGE29_LOCK0_NO_KEY_STATE_ACCESS "RO" -#define OTP_DATA_PAGE29_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) -#define OTP_DATA_PAGE29_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE29_LOCK0_KEY_R -// Description : Index 1-6 of a hardware key which must be entered to grant read -// access, or 0 if no such key is required. -#define OTP_DATA_PAGE29_LOCK0_KEY_R_RESET "-" -#define OTP_DATA_PAGE29_LOCK0_KEY_R_BITS _u(0x00000038) -#define OTP_DATA_PAGE29_LOCK0_KEY_R_MSB _u(5) -#define OTP_DATA_PAGE29_LOCK0_KEY_R_LSB _u(3) -#define OTP_DATA_PAGE29_LOCK0_KEY_R_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE29_LOCK0_KEY_W -// Description : Index 1-6 of a hardware key which must be entered to grant -// write access, or 0 if no such key is required. -#define OTP_DATA_PAGE29_LOCK0_KEY_W_RESET "-" -#define OTP_DATA_PAGE29_LOCK0_KEY_W_BITS _u(0x00000007) -#define OTP_DATA_PAGE29_LOCK0_KEY_W_MSB _u(2) -#define OTP_DATA_PAGE29_LOCK0_KEY_W_LSB _u(0) -#define OTP_DATA_PAGE29_LOCK0_KEY_W_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_PAGE29_LOCK1 -// Description : Lock configuration MSBs for page 29 (rows 0x740 through 0x77f). -// Locks are stored with 3-way majority vote encoding, so that -// bits can be set independently. -// -// This OTP location is always readable, and is write-protected by -// its own permissions. -#define OTP_DATA_PAGE29_LOCK1_ROW _u(0x00000fbb) -#define OTP_DATA_PAGE29_LOCK1_BITS _u(0x00ffff3f) -#define OTP_DATA_PAGE29_LOCK1_RESET _u(0x00000000) -#define OTP_DATA_PAGE29_LOCK1_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE29_LOCK1_R2 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE29_LOCK1_R2_RESET "-" -#define OTP_DATA_PAGE29_LOCK1_R2_BITS _u(0x00ff0000) -#define OTP_DATA_PAGE29_LOCK1_R2_MSB _u(23) -#define OTP_DATA_PAGE29_LOCK1_R2_LSB _u(16) -#define OTP_DATA_PAGE29_LOCK1_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE29_LOCK1_R1 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE29_LOCK1_R1_RESET "-" -#define OTP_DATA_PAGE29_LOCK1_R1_BITS _u(0x0000ff00) -#define OTP_DATA_PAGE29_LOCK1_R1_MSB _u(15) -#define OTP_DATA_PAGE29_LOCK1_R1_LSB _u(8) -#define OTP_DATA_PAGE29_LOCK1_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE29_LOCK1_LOCK_BL -// Description : Dummy lock bits reserved for bootloaders (including the RP2350 -// USB bootloader) to store their own OTP access permissions. No -// hardware effect, and no corresponding SW_LOCKx registers. -// 0x0 -> Bootloader permits user reads and writes to this page -// 0x1 -> Bootloader permits user reads of this page -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE -// 0x3 -> Bootloader does not permit user access to this page -#define OTP_DATA_PAGE29_LOCK1_LOCK_BL_RESET "-" -#define OTP_DATA_PAGE29_LOCK1_LOCK_BL_BITS _u(0x00000030) -#define OTP_DATA_PAGE29_LOCK1_LOCK_BL_MSB _u(5) -#define OTP_DATA_PAGE29_LOCK1_LOCK_BL_LSB _u(4) -#define OTP_DATA_PAGE29_LOCK1_LOCK_BL_ACCESS "RO" -#define OTP_DATA_PAGE29_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE29_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE29_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE29_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE29_LOCK1_LOCK_NS -// Description : Lock state for Non-secure accesses to this page. Thermometer- -// coded, so lock state can be advanced permanently from any state -// to any less-permissive state by programming OTP. Software can -// also advance the lock state temporarily (until next OTP reset) -// using the SW_LOCKx registers. -// -// Note that READ_WRITE and READ_ONLY are equivalent in hardware, -// as the SBPI programming interface is not accessible to Non- -// secure software. However, Secure software may check these bits -// to apply write permissions to a Non-secure OTP programming API. -// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. -// 0x1 -> Page can be read by Non-secure software -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. -// 0x3 -> Page can not be accessed by Non-secure software. -#define OTP_DATA_PAGE29_LOCK1_LOCK_NS_RESET "-" -#define OTP_DATA_PAGE29_LOCK1_LOCK_NS_BITS _u(0x0000000c) -#define OTP_DATA_PAGE29_LOCK1_LOCK_NS_MSB _u(3) -#define OTP_DATA_PAGE29_LOCK1_LOCK_NS_LSB _u(2) -#define OTP_DATA_PAGE29_LOCK1_LOCK_NS_ACCESS "RO" -#define OTP_DATA_PAGE29_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE29_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE29_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE29_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE29_LOCK1_LOCK_S -// Description : Lock state for Secure accesses to this page. Thermometer-coded, -// so lock state can be advanced permanently from any state to any -// less-permissive state by programming OTP. Software can also -// advance the lock state temporarily (until next OTP reset) using -// the SW_LOCKx registers. -// 0x0 -> Page is fully accessible by Secure software. -// 0x1 -> Page can be read by Secure software, but can not be written. -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. -// 0x3 -> Page can not be accessed by Secure software. -#define OTP_DATA_PAGE29_LOCK1_LOCK_S_RESET "-" -#define OTP_DATA_PAGE29_LOCK1_LOCK_S_BITS _u(0x00000003) -#define OTP_DATA_PAGE29_LOCK1_LOCK_S_MSB _u(1) -#define OTP_DATA_PAGE29_LOCK1_LOCK_S_LSB _u(0) -#define OTP_DATA_PAGE29_LOCK1_LOCK_S_ACCESS "RO" -#define OTP_DATA_PAGE29_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE29_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE29_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE29_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) -// ============================================================================= -// Register : OTP_DATA_PAGE30_LOCK0 -// Description : Lock configuration LSBs for page 30 (rows 0x780 through 0x7bf). -// Locks are stored with 3-way majority vote encoding, so that -// bits can be set independently. -// -// This OTP location is always readable, and is write-protected by -// its own permissions. -#define OTP_DATA_PAGE30_LOCK0_ROW _u(0x00000fbc) -#define OTP_DATA_PAGE30_LOCK0_BITS _u(0x00ffff7f) -#define OTP_DATA_PAGE30_LOCK0_RESET _u(0x00000000) -#define OTP_DATA_PAGE30_LOCK0_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE30_LOCK0_R2 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE30_LOCK0_R2_RESET "-" -#define OTP_DATA_PAGE30_LOCK0_R2_BITS _u(0x00ff0000) -#define OTP_DATA_PAGE30_LOCK0_R2_MSB _u(23) -#define OTP_DATA_PAGE30_LOCK0_R2_LSB _u(16) -#define OTP_DATA_PAGE30_LOCK0_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE30_LOCK0_R1 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE30_LOCK0_R1_RESET "-" -#define OTP_DATA_PAGE30_LOCK0_R1_BITS _u(0x0000ff00) -#define OTP_DATA_PAGE30_LOCK0_R1_MSB _u(15) -#define OTP_DATA_PAGE30_LOCK0_R1_LSB _u(8) -#define OTP_DATA_PAGE30_LOCK0_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE30_LOCK0_NO_KEY_STATE -// Description : State when at least one key is registered for this page and no -// matching key has been entered. -// 0x0 -> read_only -// 0x1 -> inaccessible -#define OTP_DATA_PAGE30_LOCK0_NO_KEY_STATE_RESET "-" -#define OTP_DATA_PAGE30_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) -#define OTP_DATA_PAGE30_LOCK0_NO_KEY_STATE_MSB _u(6) -#define OTP_DATA_PAGE30_LOCK0_NO_KEY_STATE_LSB _u(6) -#define OTP_DATA_PAGE30_LOCK0_NO_KEY_STATE_ACCESS "RO" -#define OTP_DATA_PAGE30_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) -#define OTP_DATA_PAGE30_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE30_LOCK0_KEY_R -// Description : Index 1-6 of a hardware key which must be entered to grant read -// access, or 0 if no such key is required. -#define OTP_DATA_PAGE30_LOCK0_KEY_R_RESET "-" -#define OTP_DATA_PAGE30_LOCK0_KEY_R_BITS _u(0x00000038) -#define OTP_DATA_PAGE30_LOCK0_KEY_R_MSB _u(5) -#define OTP_DATA_PAGE30_LOCK0_KEY_R_LSB _u(3) -#define OTP_DATA_PAGE30_LOCK0_KEY_R_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE30_LOCK0_KEY_W -// Description : Index 1-6 of a hardware key which must be entered to grant -// write access, or 0 if no such key is required. -#define OTP_DATA_PAGE30_LOCK0_KEY_W_RESET "-" -#define OTP_DATA_PAGE30_LOCK0_KEY_W_BITS _u(0x00000007) -#define OTP_DATA_PAGE30_LOCK0_KEY_W_MSB _u(2) -#define OTP_DATA_PAGE30_LOCK0_KEY_W_LSB _u(0) -#define OTP_DATA_PAGE30_LOCK0_KEY_W_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_PAGE30_LOCK1 -// Description : Lock configuration MSBs for page 30 (rows 0x780 through 0x7bf). -// Locks are stored with 3-way majority vote encoding, so that -// bits can be set independently. -// -// This OTP location is always readable, and is write-protected by -// its own permissions. -#define OTP_DATA_PAGE30_LOCK1_ROW _u(0x00000fbd) -#define OTP_DATA_PAGE30_LOCK1_BITS _u(0x00ffff3f) -#define OTP_DATA_PAGE30_LOCK1_RESET _u(0x00000000) -#define OTP_DATA_PAGE30_LOCK1_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE30_LOCK1_R2 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE30_LOCK1_R2_RESET "-" -#define OTP_DATA_PAGE30_LOCK1_R2_BITS _u(0x00ff0000) -#define OTP_DATA_PAGE30_LOCK1_R2_MSB _u(23) -#define OTP_DATA_PAGE30_LOCK1_R2_LSB _u(16) -#define OTP_DATA_PAGE30_LOCK1_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE30_LOCK1_R1 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE30_LOCK1_R1_RESET "-" -#define OTP_DATA_PAGE30_LOCK1_R1_BITS _u(0x0000ff00) -#define OTP_DATA_PAGE30_LOCK1_R1_MSB _u(15) -#define OTP_DATA_PAGE30_LOCK1_R1_LSB _u(8) -#define OTP_DATA_PAGE30_LOCK1_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE30_LOCK1_LOCK_BL -// Description : Dummy lock bits reserved for bootloaders (including the RP2350 -// USB bootloader) to store their own OTP access permissions. No -// hardware effect, and no corresponding SW_LOCKx registers. -// 0x0 -> Bootloader permits user reads and writes to this page -// 0x1 -> Bootloader permits user reads of this page -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE -// 0x3 -> Bootloader does not permit user access to this page -#define OTP_DATA_PAGE30_LOCK1_LOCK_BL_RESET "-" -#define OTP_DATA_PAGE30_LOCK1_LOCK_BL_BITS _u(0x00000030) -#define OTP_DATA_PAGE30_LOCK1_LOCK_BL_MSB _u(5) -#define OTP_DATA_PAGE30_LOCK1_LOCK_BL_LSB _u(4) -#define OTP_DATA_PAGE30_LOCK1_LOCK_BL_ACCESS "RO" -#define OTP_DATA_PAGE30_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE30_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE30_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE30_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE30_LOCK1_LOCK_NS -// Description : Lock state for Non-secure accesses to this page. Thermometer- -// coded, so lock state can be advanced permanently from any state -// to any less-permissive state by programming OTP. Software can -// also advance the lock state temporarily (until next OTP reset) -// using the SW_LOCKx registers. -// -// Note that READ_WRITE and READ_ONLY are equivalent in hardware, -// as the SBPI programming interface is not accessible to Non- -// secure software. However, Secure software may check these bits -// to apply write permissions to a Non-secure OTP programming API. -// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. -// 0x1 -> Page can be read by Non-secure software -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. -// 0x3 -> Page can not be accessed by Non-secure software. -#define OTP_DATA_PAGE30_LOCK1_LOCK_NS_RESET "-" -#define OTP_DATA_PAGE30_LOCK1_LOCK_NS_BITS _u(0x0000000c) -#define OTP_DATA_PAGE30_LOCK1_LOCK_NS_MSB _u(3) -#define OTP_DATA_PAGE30_LOCK1_LOCK_NS_LSB _u(2) -#define OTP_DATA_PAGE30_LOCK1_LOCK_NS_ACCESS "RO" -#define OTP_DATA_PAGE30_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE30_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE30_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE30_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE30_LOCK1_LOCK_S -// Description : Lock state for Secure accesses to this page. Thermometer-coded, -// so lock state can be advanced permanently from any state to any -// less-permissive state by programming OTP. Software can also -// advance the lock state temporarily (until next OTP reset) using -// the SW_LOCKx registers. -// 0x0 -> Page is fully accessible by Secure software. -// 0x1 -> Page can be read by Secure software, but can not be written. -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. -// 0x3 -> Page can not be accessed by Secure software. -#define OTP_DATA_PAGE30_LOCK1_LOCK_S_RESET "-" -#define OTP_DATA_PAGE30_LOCK1_LOCK_S_BITS _u(0x00000003) -#define OTP_DATA_PAGE30_LOCK1_LOCK_S_MSB _u(1) -#define OTP_DATA_PAGE30_LOCK1_LOCK_S_LSB _u(0) -#define OTP_DATA_PAGE30_LOCK1_LOCK_S_ACCESS "RO" -#define OTP_DATA_PAGE30_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE30_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE30_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE30_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) -// ============================================================================= -// Register : OTP_DATA_PAGE31_LOCK0 -// Description : Lock configuration LSBs for page 31 (rows 0x7c0 through 0x7ff). -// Locks are stored with 3-way majority vote encoding, so that -// bits can be set independently. -// -// This OTP location is always readable, and is write-protected by -// its own permissions. -#define OTP_DATA_PAGE31_LOCK0_ROW _u(0x00000fbe) -#define OTP_DATA_PAGE31_LOCK0_BITS _u(0x00ffff7f) -#define OTP_DATA_PAGE31_LOCK0_RESET _u(0x00000000) -#define OTP_DATA_PAGE31_LOCK0_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE31_LOCK0_R2 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE31_LOCK0_R2_RESET "-" -#define OTP_DATA_PAGE31_LOCK0_R2_BITS _u(0x00ff0000) -#define OTP_DATA_PAGE31_LOCK0_R2_MSB _u(23) -#define OTP_DATA_PAGE31_LOCK0_R2_LSB _u(16) -#define OTP_DATA_PAGE31_LOCK0_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE31_LOCK0_R1 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE31_LOCK0_R1_RESET "-" -#define OTP_DATA_PAGE31_LOCK0_R1_BITS _u(0x0000ff00) -#define OTP_DATA_PAGE31_LOCK0_R1_MSB _u(15) -#define OTP_DATA_PAGE31_LOCK0_R1_LSB _u(8) -#define OTP_DATA_PAGE31_LOCK0_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE31_LOCK0_NO_KEY_STATE -// Description : State when at least one key is registered for this page and no -// matching key has been entered. -// 0x0 -> read_only -// 0x1 -> inaccessible -#define OTP_DATA_PAGE31_LOCK0_NO_KEY_STATE_RESET "-" -#define OTP_DATA_PAGE31_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) -#define OTP_DATA_PAGE31_LOCK0_NO_KEY_STATE_MSB _u(6) -#define OTP_DATA_PAGE31_LOCK0_NO_KEY_STATE_LSB _u(6) -#define OTP_DATA_PAGE31_LOCK0_NO_KEY_STATE_ACCESS "RO" -#define OTP_DATA_PAGE31_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) -#define OTP_DATA_PAGE31_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE31_LOCK0_KEY_R -// Description : Index 1-6 of a hardware key which must be entered to grant read -// access, or 0 if no such key is required. -#define OTP_DATA_PAGE31_LOCK0_KEY_R_RESET "-" -#define OTP_DATA_PAGE31_LOCK0_KEY_R_BITS _u(0x00000038) -#define OTP_DATA_PAGE31_LOCK0_KEY_R_MSB _u(5) -#define OTP_DATA_PAGE31_LOCK0_KEY_R_LSB _u(3) -#define OTP_DATA_PAGE31_LOCK0_KEY_R_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE31_LOCK0_KEY_W -// Description : Index 1-6 of a hardware key which must be entered to grant -// write access, or 0 if no such key is required. -#define OTP_DATA_PAGE31_LOCK0_KEY_W_RESET "-" -#define OTP_DATA_PAGE31_LOCK0_KEY_W_BITS _u(0x00000007) -#define OTP_DATA_PAGE31_LOCK0_KEY_W_MSB _u(2) -#define OTP_DATA_PAGE31_LOCK0_KEY_W_LSB _u(0) -#define OTP_DATA_PAGE31_LOCK0_KEY_W_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_PAGE31_LOCK1 -// Description : Lock configuration MSBs for page 31 (rows 0x7c0 through 0x7ff). -// Locks are stored with 3-way majority vote encoding, so that -// bits can be set independently. -// -// This OTP location is always readable, and is write-protected by -// its own permissions. -#define OTP_DATA_PAGE31_LOCK1_ROW _u(0x00000fbf) -#define OTP_DATA_PAGE31_LOCK1_BITS _u(0x00ffff3f) -#define OTP_DATA_PAGE31_LOCK1_RESET _u(0x00000000) -#define OTP_DATA_PAGE31_LOCK1_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE31_LOCK1_R2 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE31_LOCK1_R2_RESET "-" -#define OTP_DATA_PAGE31_LOCK1_R2_BITS _u(0x00ff0000) -#define OTP_DATA_PAGE31_LOCK1_R2_MSB _u(23) -#define OTP_DATA_PAGE31_LOCK1_R2_LSB _u(16) -#define OTP_DATA_PAGE31_LOCK1_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE31_LOCK1_R1 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE31_LOCK1_R1_RESET "-" -#define OTP_DATA_PAGE31_LOCK1_R1_BITS _u(0x0000ff00) -#define OTP_DATA_PAGE31_LOCK1_R1_MSB _u(15) -#define OTP_DATA_PAGE31_LOCK1_R1_LSB _u(8) -#define OTP_DATA_PAGE31_LOCK1_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE31_LOCK1_LOCK_BL -// Description : Dummy lock bits reserved for bootloaders (including the RP2350 -// USB bootloader) to store their own OTP access permissions. No -// hardware effect, and no corresponding SW_LOCKx registers. -// 0x0 -> Bootloader permits user reads and writes to this page -// 0x1 -> Bootloader permits user reads of this page -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE -// 0x3 -> Bootloader does not permit user access to this page -#define OTP_DATA_PAGE31_LOCK1_LOCK_BL_RESET "-" -#define OTP_DATA_PAGE31_LOCK1_LOCK_BL_BITS _u(0x00000030) -#define OTP_DATA_PAGE31_LOCK1_LOCK_BL_MSB _u(5) -#define OTP_DATA_PAGE31_LOCK1_LOCK_BL_LSB _u(4) -#define OTP_DATA_PAGE31_LOCK1_LOCK_BL_ACCESS "RO" -#define OTP_DATA_PAGE31_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE31_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE31_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE31_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE31_LOCK1_LOCK_NS -// Description : Lock state for Non-secure accesses to this page. Thermometer- -// coded, so lock state can be advanced permanently from any state -// to any less-permissive state by programming OTP. Software can -// also advance the lock state temporarily (until next OTP reset) -// using the SW_LOCKx registers. -// -// Note that READ_WRITE and READ_ONLY are equivalent in hardware, -// as the SBPI programming interface is not accessible to Non- -// secure software. However, Secure software may check these bits -// to apply write permissions to a Non-secure OTP programming API. -// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. -// 0x1 -> Page can be read by Non-secure software -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. -// 0x3 -> Page can not be accessed by Non-secure software. -#define OTP_DATA_PAGE31_LOCK1_LOCK_NS_RESET "-" -#define OTP_DATA_PAGE31_LOCK1_LOCK_NS_BITS _u(0x0000000c) -#define OTP_DATA_PAGE31_LOCK1_LOCK_NS_MSB _u(3) -#define OTP_DATA_PAGE31_LOCK1_LOCK_NS_LSB _u(2) -#define OTP_DATA_PAGE31_LOCK1_LOCK_NS_ACCESS "RO" -#define OTP_DATA_PAGE31_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE31_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE31_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE31_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE31_LOCK1_LOCK_S -// Description : Lock state for Secure accesses to this page. Thermometer-coded, -// so lock state can be advanced permanently from any state to any -// less-permissive state by programming OTP. Software can also -// advance the lock state temporarily (until next OTP reset) using -// the SW_LOCKx registers. -// 0x0 -> Page is fully accessible by Secure software. -// 0x1 -> Page can be read by Secure software, but can not be written. -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. -// 0x3 -> Page can not be accessed by Secure software. -#define OTP_DATA_PAGE31_LOCK1_LOCK_S_RESET "-" -#define OTP_DATA_PAGE31_LOCK1_LOCK_S_BITS _u(0x00000003) -#define OTP_DATA_PAGE31_LOCK1_LOCK_S_MSB _u(1) -#define OTP_DATA_PAGE31_LOCK1_LOCK_S_LSB _u(0) -#define OTP_DATA_PAGE31_LOCK1_LOCK_S_ACCESS "RO" -#define OTP_DATA_PAGE31_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE31_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE31_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE31_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) -// ============================================================================= -// Register : OTP_DATA_PAGE32_LOCK0 -// Description : Lock configuration LSBs for page 32 (rows 0x800 through 0x83f). -// Locks are stored with 3-way majority vote encoding, so that -// bits can be set independently. -// -// This OTP location is always readable, and is write-protected by -// its own permissions. -#define OTP_DATA_PAGE32_LOCK0_ROW _u(0x00000fc0) -#define OTP_DATA_PAGE32_LOCK0_BITS _u(0x00ffff7f) -#define OTP_DATA_PAGE32_LOCK0_RESET _u(0x00000000) -#define OTP_DATA_PAGE32_LOCK0_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE32_LOCK0_R2 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE32_LOCK0_R2_RESET "-" -#define OTP_DATA_PAGE32_LOCK0_R2_BITS _u(0x00ff0000) -#define OTP_DATA_PAGE32_LOCK0_R2_MSB _u(23) -#define OTP_DATA_PAGE32_LOCK0_R2_LSB _u(16) -#define OTP_DATA_PAGE32_LOCK0_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE32_LOCK0_R1 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE32_LOCK0_R1_RESET "-" -#define OTP_DATA_PAGE32_LOCK0_R1_BITS _u(0x0000ff00) -#define OTP_DATA_PAGE32_LOCK0_R1_MSB _u(15) -#define OTP_DATA_PAGE32_LOCK0_R1_LSB _u(8) -#define OTP_DATA_PAGE32_LOCK0_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE32_LOCK0_NO_KEY_STATE -// Description : State when at least one key is registered for this page and no -// matching key has been entered. -// 0x0 -> read_only -// 0x1 -> inaccessible -#define OTP_DATA_PAGE32_LOCK0_NO_KEY_STATE_RESET "-" -#define OTP_DATA_PAGE32_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) -#define OTP_DATA_PAGE32_LOCK0_NO_KEY_STATE_MSB _u(6) -#define OTP_DATA_PAGE32_LOCK0_NO_KEY_STATE_LSB _u(6) -#define OTP_DATA_PAGE32_LOCK0_NO_KEY_STATE_ACCESS "RO" -#define OTP_DATA_PAGE32_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) -#define OTP_DATA_PAGE32_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE32_LOCK0_KEY_R -// Description : Index 1-6 of a hardware key which must be entered to grant read -// access, or 0 if no such key is required. -#define OTP_DATA_PAGE32_LOCK0_KEY_R_RESET "-" -#define OTP_DATA_PAGE32_LOCK0_KEY_R_BITS _u(0x00000038) -#define OTP_DATA_PAGE32_LOCK0_KEY_R_MSB _u(5) -#define OTP_DATA_PAGE32_LOCK0_KEY_R_LSB _u(3) -#define OTP_DATA_PAGE32_LOCK0_KEY_R_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE32_LOCK0_KEY_W -// Description : Index 1-6 of a hardware key which must be entered to grant -// write access, or 0 if no such key is required. -#define OTP_DATA_PAGE32_LOCK0_KEY_W_RESET "-" -#define OTP_DATA_PAGE32_LOCK0_KEY_W_BITS _u(0x00000007) -#define OTP_DATA_PAGE32_LOCK0_KEY_W_MSB _u(2) -#define OTP_DATA_PAGE32_LOCK0_KEY_W_LSB _u(0) -#define OTP_DATA_PAGE32_LOCK0_KEY_W_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_PAGE32_LOCK1 -// Description : Lock configuration MSBs for page 32 (rows 0x800 through 0x83f). -// Locks are stored with 3-way majority vote encoding, so that -// bits can be set independently. -// -// This OTP location is always readable, and is write-protected by -// its own permissions. -#define OTP_DATA_PAGE32_LOCK1_ROW _u(0x00000fc1) -#define OTP_DATA_PAGE32_LOCK1_BITS _u(0x00ffff3f) -#define OTP_DATA_PAGE32_LOCK1_RESET _u(0x00000000) -#define OTP_DATA_PAGE32_LOCK1_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE32_LOCK1_R2 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE32_LOCK1_R2_RESET "-" -#define OTP_DATA_PAGE32_LOCK1_R2_BITS _u(0x00ff0000) -#define OTP_DATA_PAGE32_LOCK1_R2_MSB _u(23) -#define OTP_DATA_PAGE32_LOCK1_R2_LSB _u(16) -#define OTP_DATA_PAGE32_LOCK1_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE32_LOCK1_R1 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE32_LOCK1_R1_RESET "-" -#define OTP_DATA_PAGE32_LOCK1_R1_BITS _u(0x0000ff00) -#define OTP_DATA_PAGE32_LOCK1_R1_MSB _u(15) -#define OTP_DATA_PAGE32_LOCK1_R1_LSB _u(8) -#define OTP_DATA_PAGE32_LOCK1_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE32_LOCK1_LOCK_BL -// Description : Dummy lock bits reserved for bootloaders (including the RP2350 -// USB bootloader) to store their own OTP access permissions. No -// hardware effect, and no corresponding SW_LOCKx registers. -// 0x0 -> Bootloader permits user reads and writes to this page -// 0x1 -> Bootloader permits user reads of this page -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE -// 0x3 -> Bootloader does not permit user access to this page -#define OTP_DATA_PAGE32_LOCK1_LOCK_BL_RESET "-" -#define OTP_DATA_PAGE32_LOCK1_LOCK_BL_BITS _u(0x00000030) -#define OTP_DATA_PAGE32_LOCK1_LOCK_BL_MSB _u(5) -#define OTP_DATA_PAGE32_LOCK1_LOCK_BL_LSB _u(4) -#define OTP_DATA_PAGE32_LOCK1_LOCK_BL_ACCESS "RO" -#define OTP_DATA_PAGE32_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE32_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE32_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE32_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE32_LOCK1_LOCK_NS -// Description : Lock state for Non-secure accesses to this page. Thermometer- -// coded, so lock state can be advanced permanently from any state -// to any less-permissive state by programming OTP. Software can -// also advance the lock state temporarily (until next OTP reset) -// using the SW_LOCKx registers. -// -// Note that READ_WRITE and READ_ONLY are equivalent in hardware, -// as the SBPI programming interface is not accessible to Non- -// secure software. However, Secure software may check these bits -// to apply write permissions to a Non-secure OTP programming API. -// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. -// 0x1 -> Page can be read by Non-secure software -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. -// 0x3 -> Page can not be accessed by Non-secure software. -#define OTP_DATA_PAGE32_LOCK1_LOCK_NS_RESET "-" -#define OTP_DATA_PAGE32_LOCK1_LOCK_NS_BITS _u(0x0000000c) -#define OTP_DATA_PAGE32_LOCK1_LOCK_NS_MSB _u(3) -#define OTP_DATA_PAGE32_LOCK1_LOCK_NS_LSB _u(2) -#define OTP_DATA_PAGE32_LOCK1_LOCK_NS_ACCESS "RO" -#define OTP_DATA_PAGE32_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE32_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE32_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE32_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE32_LOCK1_LOCK_S -// Description : Lock state for Secure accesses to this page. Thermometer-coded, -// so lock state can be advanced permanently from any state to any -// less-permissive state by programming OTP. Software can also -// advance the lock state temporarily (until next OTP reset) using -// the SW_LOCKx registers. -// 0x0 -> Page is fully accessible by Secure software. -// 0x1 -> Page can be read by Secure software, but can not be written. -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. -// 0x3 -> Page can not be accessed by Secure software. -#define OTP_DATA_PAGE32_LOCK1_LOCK_S_RESET "-" -#define OTP_DATA_PAGE32_LOCK1_LOCK_S_BITS _u(0x00000003) -#define OTP_DATA_PAGE32_LOCK1_LOCK_S_MSB _u(1) -#define OTP_DATA_PAGE32_LOCK1_LOCK_S_LSB _u(0) -#define OTP_DATA_PAGE32_LOCK1_LOCK_S_ACCESS "RO" -#define OTP_DATA_PAGE32_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE32_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE32_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE32_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) -// ============================================================================= -// Register : OTP_DATA_PAGE33_LOCK0 -// Description : Lock configuration LSBs for page 33 (rows 0x840 through 0x87f). -// Locks are stored with 3-way majority vote encoding, so that -// bits can be set independently. -// -// This OTP location is always readable, and is write-protected by -// its own permissions. -#define OTP_DATA_PAGE33_LOCK0_ROW _u(0x00000fc2) -#define OTP_DATA_PAGE33_LOCK0_BITS _u(0x00ffff7f) -#define OTP_DATA_PAGE33_LOCK0_RESET _u(0x00000000) -#define OTP_DATA_PAGE33_LOCK0_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE33_LOCK0_R2 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE33_LOCK0_R2_RESET "-" -#define OTP_DATA_PAGE33_LOCK0_R2_BITS _u(0x00ff0000) -#define OTP_DATA_PAGE33_LOCK0_R2_MSB _u(23) -#define OTP_DATA_PAGE33_LOCK0_R2_LSB _u(16) -#define OTP_DATA_PAGE33_LOCK0_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE33_LOCK0_R1 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE33_LOCK0_R1_RESET "-" -#define OTP_DATA_PAGE33_LOCK0_R1_BITS _u(0x0000ff00) -#define OTP_DATA_PAGE33_LOCK0_R1_MSB _u(15) -#define OTP_DATA_PAGE33_LOCK0_R1_LSB _u(8) -#define OTP_DATA_PAGE33_LOCK0_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE33_LOCK0_NO_KEY_STATE -// Description : State when at least one key is registered for this page and no -// matching key has been entered. -// 0x0 -> read_only -// 0x1 -> inaccessible -#define OTP_DATA_PAGE33_LOCK0_NO_KEY_STATE_RESET "-" -#define OTP_DATA_PAGE33_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) -#define OTP_DATA_PAGE33_LOCK0_NO_KEY_STATE_MSB _u(6) -#define OTP_DATA_PAGE33_LOCK0_NO_KEY_STATE_LSB _u(6) -#define OTP_DATA_PAGE33_LOCK0_NO_KEY_STATE_ACCESS "RO" -#define OTP_DATA_PAGE33_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) -#define OTP_DATA_PAGE33_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE33_LOCK0_KEY_R -// Description : Index 1-6 of a hardware key which must be entered to grant read -// access, or 0 if no such key is required. -#define OTP_DATA_PAGE33_LOCK0_KEY_R_RESET "-" -#define OTP_DATA_PAGE33_LOCK0_KEY_R_BITS _u(0x00000038) -#define OTP_DATA_PAGE33_LOCK0_KEY_R_MSB _u(5) -#define OTP_DATA_PAGE33_LOCK0_KEY_R_LSB _u(3) -#define OTP_DATA_PAGE33_LOCK0_KEY_R_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE33_LOCK0_KEY_W -// Description : Index 1-6 of a hardware key which must be entered to grant -// write access, or 0 if no such key is required. -#define OTP_DATA_PAGE33_LOCK0_KEY_W_RESET "-" -#define OTP_DATA_PAGE33_LOCK0_KEY_W_BITS _u(0x00000007) -#define OTP_DATA_PAGE33_LOCK0_KEY_W_MSB _u(2) -#define OTP_DATA_PAGE33_LOCK0_KEY_W_LSB _u(0) -#define OTP_DATA_PAGE33_LOCK0_KEY_W_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_PAGE33_LOCK1 -// Description : Lock configuration MSBs for page 33 (rows 0x840 through 0x87f). -// Locks are stored with 3-way majority vote encoding, so that -// bits can be set independently. -// -// This OTP location is always readable, and is write-protected by -// its own permissions. -#define OTP_DATA_PAGE33_LOCK1_ROW _u(0x00000fc3) -#define OTP_DATA_PAGE33_LOCK1_BITS _u(0x00ffff3f) -#define OTP_DATA_PAGE33_LOCK1_RESET _u(0x00000000) -#define OTP_DATA_PAGE33_LOCK1_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE33_LOCK1_R2 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE33_LOCK1_R2_RESET "-" -#define OTP_DATA_PAGE33_LOCK1_R2_BITS _u(0x00ff0000) -#define OTP_DATA_PAGE33_LOCK1_R2_MSB _u(23) -#define OTP_DATA_PAGE33_LOCK1_R2_LSB _u(16) -#define OTP_DATA_PAGE33_LOCK1_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE33_LOCK1_R1 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE33_LOCK1_R1_RESET "-" -#define OTP_DATA_PAGE33_LOCK1_R1_BITS _u(0x0000ff00) -#define OTP_DATA_PAGE33_LOCK1_R1_MSB _u(15) -#define OTP_DATA_PAGE33_LOCK1_R1_LSB _u(8) -#define OTP_DATA_PAGE33_LOCK1_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE33_LOCK1_LOCK_BL -// Description : Dummy lock bits reserved for bootloaders (including the RP2350 -// USB bootloader) to store their own OTP access permissions. No -// hardware effect, and no corresponding SW_LOCKx registers. -// 0x0 -> Bootloader permits user reads and writes to this page -// 0x1 -> Bootloader permits user reads of this page -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE -// 0x3 -> Bootloader does not permit user access to this page -#define OTP_DATA_PAGE33_LOCK1_LOCK_BL_RESET "-" -#define OTP_DATA_PAGE33_LOCK1_LOCK_BL_BITS _u(0x00000030) -#define OTP_DATA_PAGE33_LOCK1_LOCK_BL_MSB _u(5) -#define OTP_DATA_PAGE33_LOCK1_LOCK_BL_LSB _u(4) -#define OTP_DATA_PAGE33_LOCK1_LOCK_BL_ACCESS "RO" -#define OTP_DATA_PAGE33_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE33_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE33_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE33_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE33_LOCK1_LOCK_NS -// Description : Lock state for Non-secure accesses to this page. Thermometer- -// coded, so lock state can be advanced permanently from any state -// to any less-permissive state by programming OTP. Software can -// also advance the lock state temporarily (until next OTP reset) -// using the SW_LOCKx registers. -// -// Note that READ_WRITE and READ_ONLY are equivalent in hardware, -// as the SBPI programming interface is not accessible to Non- -// secure software. However, Secure software may check these bits -// to apply write permissions to a Non-secure OTP programming API. -// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. -// 0x1 -> Page can be read by Non-secure software -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. -// 0x3 -> Page can not be accessed by Non-secure software. -#define OTP_DATA_PAGE33_LOCK1_LOCK_NS_RESET "-" -#define OTP_DATA_PAGE33_LOCK1_LOCK_NS_BITS _u(0x0000000c) -#define OTP_DATA_PAGE33_LOCK1_LOCK_NS_MSB _u(3) -#define OTP_DATA_PAGE33_LOCK1_LOCK_NS_LSB _u(2) -#define OTP_DATA_PAGE33_LOCK1_LOCK_NS_ACCESS "RO" -#define OTP_DATA_PAGE33_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE33_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE33_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE33_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE33_LOCK1_LOCK_S -// Description : Lock state for Secure accesses to this page. Thermometer-coded, -// so lock state can be advanced permanently from any state to any -// less-permissive state by programming OTP. Software can also -// advance the lock state temporarily (until next OTP reset) using -// the SW_LOCKx registers. -// 0x0 -> Page is fully accessible by Secure software. -// 0x1 -> Page can be read by Secure software, but can not be written. -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. -// 0x3 -> Page can not be accessed by Secure software. -#define OTP_DATA_PAGE33_LOCK1_LOCK_S_RESET "-" -#define OTP_DATA_PAGE33_LOCK1_LOCK_S_BITS _u(0x00000003) -#define OTP_DATA_PAGE33_LOCK1_LOCK_S_MSB _u(1) -#define OTP_DATA_PAGE33_LOCK1_LOCK_S_LSB _u(0) -#define OTP_DATA_PAGE33_LOCK1_LOCK_S_ACCESS "RO" -#define OTP_DATA_PAGE33_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE33_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE33_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE33_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) -// ============================================================================= -// Register : OTP_DATA_PAGE34_LOCK0 -// Description : Lock configuration LSBs for page 34 (rows 0x880 through 0x8bf). -// Locks are stored with 3-way majority vote encoding, so that -// bits can be set independently. -// -// This OTP location is always readable, and is write-protected by -// its own permissions. -#define OTP_DATA_PAGE34_LOCK0_ROW _u(0x00000fc4) -#define OTP_DATA_PAGE34_LOCK0_BITS _u(0x00ffff7f) -#define OTP_DATA_PAGE34_LOCK0_RESET _u(0x00000000) -#define OTP_DATA_PAGE34_LOCK0_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE34_LOCK0_R2 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE34_LOCK0_R2_RESET "-" -#define OTP_DATA_PAGE34_LOCK0_R2_BITS _u(0x00ff0000) -#define OTP_DATA_PAGE34_LOCK0_R2_MSB _u(23) -#define OTP_DATA_PAGE34_LOCK0_R2_LSB _u(16) -#define OTP_DATA_PAGE34_LOCK0_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE34_LOCK0_R1 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE34_LOCK0_R1_RESET "-" -#define OTP_DATA_PAGE34_LOCK0_R1_BITS _u(0x0000ff00) -#define OTP_DATA_PAGE34_LOCK0_R1_MSB _u(15) -#define OTP_DATA_PAGE34_LOCK0_R1_LSB _u(8) -#define OTP_DATA_PAGE34_LOCK0_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE34_LOCK0_NO_KEY_STATE -// Description : State when at least one key is registered for this page and no -// matching key has been entered. -// 0x0 -> read_only -// 0x1 -> inaccessible -#define OTP_DATA_PAGE34_LOCK0_NO_KEY_STATE_RESET "-" -#define OTP_DATA_PAGE34_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) -#define OTP_DATA_PAGE34_LOCK0_NO_KEY_STATE_MSB _u(6) -#define OTP_DATA_PAGE34_LOCK0_NO_KEY_STATE_LSB _u(6) -#define OTP_DATA_PAGE34_LOCK0_NO_KEY_STATE_ACCESS "RO" -#define OTP_DATA_PAGE34_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) -#define OTP_DATA_PAGE34_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE34_LOCK0_KEY_R -// Description : Index 1-6 of a hardware key which must be entered to grant read -// access, or 0 if no such key is required. -#define OTP_DATA_PAGE34_LOCK0_KEY_R_RESET "-" -#define OTP_DATA_PAGE34_LOCK0_KEY_R_BITS _u(0x00000038) -#define OTP_DATA_PAGE34_LOCK0_KEY_R_MSB _u(5) -#define OTP_DATA_PAGE34_LOCK0_KEY_R_LSB _u(3) -#define OTP_DATA_PAGE34_LOCK0_KEY_R_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE34_LOCK0_KEY_W -// Description : Index 1-6 of a hardware key which must be entered to grant -// write access, or 0 if no such key is required. -#define OTP_DATA_PAGE34_LOCK0_KEY_W_RESET "-" -#define OTP_DATA_PAGE34_LOCK0_KEY_W_BITS _u(0x00000007) -#define OTP_DATA_PAGE34_LOCK0_KEY_W_MSB _u(2) -#define OTP_DATA_PAGE34_LOCK0_KEY_W_LSB _u(0) -#define OTP_DATA_PAGE34_LOCK0_KEY_W_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_PAGE34_LOCK1 -// Description : Lock configuration MSBs for page 34 (rows 0x880 through 0x8bf). -// Locks are stored with 3-way majority vote encoding, so that -// bits can be set independently. -// -// This OTP location is always readable, and is write-protected by -// its own permissions. -#define OTP_DATA_PAGE34_LOCK1_ROW _u(0x00000fc5) -#define OTP_DATA_PAGE34_LOCK1_BITS _u(0x00ffff3f) -#define OTP_DATA_PAGE34_LOCK1_RESET _u(0x00000000) -#define OTP_DATA_PAGE34_LOCK1_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE34_LOCK1_R2 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE34_LOCK1_R2_RESET "-" -#define OTP_DATA_PAGE34_LOCK1_R2_BITS _u(0x00ff0000) -#define OTP_DATA_PAGE34_LOCK1_R2_MSB _u(23) -#define OTP_DATA_PAGE34_LOCK1_R2_LSB _u(16) -#define OTP_DATA_PAGE34_LOCK1_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE34_LOCK1_R1 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE34_LOCK1_R1_RESET "-" -#define OTP_DATA_PAGE34_LOCK1_R1_BITS _u(0x0000ff00) -#define OTP_DATA_PAGE34_LOCK1_R1_MSB _u(15) -#define OTP_DATA_PAGE34_LOCK1_R1_LSB _u(8) -#define OTP_DATA_PAGE34_LOCK1_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE34_LOCK1_LOCK_BL -// Description : Dummy lock bits reserved for bootloaders (including the RP2350 -// USB bootloader) to store their own OTP access permissions. No -// hardware effect, and no corresponding SW_LOCKx registers. -// 0x0 -> Bootloader permits user reads and writes to this page -// 0x1 -> Bootloader permits user reads of this page -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE -// 0x3 -> Bootloader does not permit user access to this page -#define OTP_DATA_PAGE34_LOCK1_LOCK_BL_RESET "-" -#define OTP_DATA_PAGE34_LOCK1_LOCK_BL_BITS _u(0x00000030) -#define OTP_DATA_PAGE34_LOCK1_LOCK_BL_MSB _u(5) -#define OTP_DATA_PAGE34_LOCK1_LOCK_BL_LSB _u(4) -#define OTP_DATA_PAGE34_LOCK1_LOCK_BL_ACCESS "RO" -#define OTP_DATA_PAGE34_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE34_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE34_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE34_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE34_LOCK1_LOCK_NS -// Description : Lock state for Non-secure accesses to this page. Thermometer- -// coded, so lock state can be advanced permanently from any state -// to any less-permissive state by programming OTP. Software can -// also advance the lock state temporarily (until next OTP reset) -// using the SW_LOCKx registers. -// -// Note that READ_WRITE and READ_ONLY are equivalent in hardware, -// as the SBPI programming interface is not accessible to Non- -// secure software. However, Secure software may check these bits -// to apply write permissions to a Non-secure OTP programming API. -// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. -// 0x1 -> Page can be read by Non-secure software -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. -// 0x3 -> Page can not be accessed by Non-secure software. -#define OTP_DATA_PAGE34_LOCK1_LOCK_NS_RESET "-" -#define OTP_DATA_PAGE34_LOCK1_LOCK_NS_BITS _u(0x0000000c) -#define OTP_DATA_PAGE34_LOCK1_LOCK_NS_MSB _u(3) -#define OTP_DATA_PAGE34_LOCK1_LOCK_NS_LSB _u(2) -#define OTP_DATA_PAGE34_LOCK1_LOCK_NS_ACCESS "RO" -#define OTP_DATA_PAGE34_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE34_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE34_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE34_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE34_LOCK1_LOCK_S -// Description : Lock state for Secure accesses to this page. Thermometer-coded, -// so lock state can be advanced permanently from any state to any -// less-permissive state by programming OTP. Software can also -// advance the lock state temporarily (until next OTP reset) using -// the SW_LOCKx registers. -// 0x0 -> Page is fully accessible by Secure software. -// 0x1 -> Page can be read by Secure software, but can not be written. -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. -// 0x3 -> Page can not be accessed by Secure software. -#define OTP_DATA_PAGE34_LOCK1_LOCK_S_RESET "-" -#define OTP_DATA_PAGE34_LOCK1_LOCK_S_BITS _u(0x00000003) -#define OTP_DATA_PAGE34_LOCK1_LOCK_S_MSB _u(1) -#define OTP_DATA_PAGE34_LOCK1_LOCK_S_LSB _u(0) -#define OTP_DATA_PAGE34_LOCK1_LOCK_S_ACCESS "RO" -#define OTP_DATA_PAGE34_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE34_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE34_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE34_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) -// ============================================================================= -// Register : OTP_DATA_PAGE35_LOCK0 -// Description : Lock configuration LSBs for page 35 (rows 0x8c0 through 0x8ff). -// Locks are stored with 3-way majority vote encoding, so that -// bits can be set independently. -// -// This OTP location is always readable, and is write-protected by -// its own permissions. -#define OTP_DATA_PAGE35_LOCK0_ROW _u(0x00000fc6) -#define OTP_DATA_PAGE35_LOCK0_BITS _u(0x00ffff7f) -#define OTP_DATA_PAGE35_LOCK0_RESET _u(0x00000000) -#define OTP_DATA_PAGE35_LOCK0_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE35_LOCK0_R2 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE35_LOCK0_R2_RESET "-" -#define OTP_DATA_PAGE35_LOCK0_R2_BITS _u(0x00ff0000) -#define OTP_DATA_PAGE35_LOCK0_R2_MSB _u(23) -#define OTP_DATA_PAGE35_LOCK0_R2_LSB _u(16) -#define OTP_DATA_PAGE35_LOCK0_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE35_LOCK0_R1 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE35_LOCK0_R1_RESET "-" -#define OTP_DATA_PAGE35_LOCK0_R1_BITS _u(0x0000ff00) -#define OTP_DATA_PAGE35_LOCK0_R1_MSB _u(15) -#define OTP_DATA_PAGE35_LOCK0_R1_LSB _u(8) -#define OTP_DATA_PAGE35_LOCK0_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE35_LOCK0_NO_KEY_STATE -// Description : State when at least one key is registered for this page and no -// matching key has been entered. -// 0x0 -> read_only -// 0x1 -> inaccessible -#define OTP_DATA_PAGE35_LOCK0_NO_KEY_STATE_RESET "-" -#define OTP_DATA_PAGE35_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) -#define OTP_DATA_PAGE35_LOCK0_NO_KEY_STATE_MSB _u(6) -#define OTP_DATA_PAGE35_LOCK0_NO_KEY_STATE_LSB _u(6) -#define OTP_DATA_PAGE35_LOCK0_NO_KEY_STATE_ACCESS "RO" -#define OTP_DATA_PAGE35_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) -#define OTP_DATA_PAGE35_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE35_LOCK0_KEY_R -// Description : Index 1-6 of a hardware key which must be entered to grant read -// access, or 0 if no such key is required. -#define OTP_DATA_PAGE35_LOCK0_KEY_R_RESET "-" -#define OTP_DATA_PAGE35_LOCK0_KEY_R_BITS _u(0x00000038) -#define OTP_DATA_PAGE35_LOCK0_KEY_R_MSB _u(5) -#define OTP_DATA_PAGE35_LOCK0_KEY_R_LSB _u(3) -#define OTP_DATA_PAGE35_LOCK0_KEY_R_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE35_LOCK0_KEY_W -// Description : Index 1-6 of a hardware key which must be entered to grant -// write access, or 0 if no such key is required. -#define OTP_DATA_PAGE35_LOCK0_KEY_W_RESET "-" -#define OTP_DATA_PAGE35_LOCK0_KEY_W_BITS _u(0x00000007) -#define OTP_DATA_PAGE35_LOCK0_KEY_W_MSB _u(2) -#define OTP_DATA_PAGE35_LOCK0_KEY_W_LSB _u(0) -#define OTP_DATA_PAGE35_LOCK0_KEY_W_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_PAGE35_LOCK1 -// Description : Lock configuration MSBs for page 35 (rows 0x8c0 through 0x8ff). -// Locks are stored with 3-way majority vote encoding, so that -// bits can be set independently. -// -// This OTP location is always readable, and is write-protected by -// its own permissions. -#define OTP_DATA_PAGE35_LOCK1_ROW _u(0x00000fc7) -#define OTP_DATA_PAGE35_LOCK1_BITS _u(0x00ffff3f) -#define OTP_DATA_PAGE35_LOCK1_RESET _u(0x00000000) -#define OTP_DATA_PAGE35_LOCK1_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE35_LOCK1_R2 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE35_LOCK1_R2_RESET "-" -#define OTP_DATA_PAGE35_LOCK1_R2_BITS _u(0x00ff0000) -#define OTP_DATA_PAGE35_LOCK1_R2_MSB _u(23) -#define OTP_DATA_PAGE35_LOCK1_R2_LSB _u(16) -#define OTP_DATA_PAGE35_LOCK1_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE35_LOCK1_R1 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE35_LOCK1_R1_RESET "-" -#define OTP_DATA_PAGE35_LOCK1_R1_BITS _u(0x0000ff00) -#define OTP_DATA_PAGE35_LOCK1_R1_MSB _u(15) -#define OTP_DATA_PAGE35_LOCK1_R1_LSB _u(8) -#define OTP_DATA_PAGE35_LOCK1_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE35_LOCK1_LOCK_BL -// Description : Dummy lock bits reserved for bootloaders (including the RP2350 -// USB bootloader) to store their own OTP access permissions. No -// hardware effect, and no corresponding SW_LOCKx registers. -// 0x0 -> Bootloader permits user reads and writes to this page -// 0x1 -> Bootloader permits user reads of this page -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE -// 0x3 -> Bootloader does not permit user access to this page -#define OTP_DATA_PAGE35_LOCK1_LOCK_BL_RESET "-" -#define OTP_DATA_PAGE35_LOCK1_LOCK_BL_BITS _u(0x00000030) -#define OTP_DATA_PAGE35_LOCK1_LOCK_BL_MSB _u(5) -#define OTP_DATA_PAGE35_LOCK1_LOCK_BL_LSB _u(4) -#define OTP_DATA_PAGE35_LOCK1_LOCK_BL_ACCESS "RO" -#define OTP_DATA_PAGE35_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE35_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE35_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE35_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE35_LOCK1_LOCK_NS -// Description : Lock state for Non-secure accesses to this page. Thermometer- -// coded, so lock state can be advanced permanently from any state -// to any less-permissive state by programming OTP. Software can -// also advance the lock state temporarily (until next OTP reset) -// using the SW_LOCKx registers. -// -// Note that READ_WRITE and READ_ONLY are equivalent in hardware, -// as the SBPI programming interface is not accessible to Non- -// secure software. However, Secure software may check these bits -// to apply write permissions to a Non-secure OTP programming API. -// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. -// 0x1 -> Page can be read by Non-secure software -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. -// 0x3 -> Page can not be accessed by Non-secure software. -#define OTP_DATA_PAGE35_LOCK1_LOCK_NS_RESET "-" -#define OTP_DATA_PAGE35_LOCK1_LOCK_NS_BITS _u(0x0000000c) -#define OTP_DATA_PAGE35_LOCK1_LOCK_NS_MSB _u(3) -#define OTP_DATA_PAGE35_LOCK1_LOCK_NS_LSB _u(2) -#define OTP_DATA_PAGE35_LOCK1_LOCK_NS_ACCESS "RO" -#define OTP_DATA_PAGE35_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE35_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE35_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE35_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE35_LOCK1_LOCK_S -// Description : Lock state for Secure accesses to this page. Thermometer-coded, -// so lock state can be advanced permanently from any state to any -// less-permissive state by programming OTP. Software can also -// advance the lock state temporarily (until next OTP reset) using -// the SW_LOCKx registers. -// 0x0 -> Page is fully accessible by Secure software. -// 0x1 -> Page can be read by Secure software, but can not be written. -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. -// 0x3 -> Page can not be accessed by Secure software. -#define OTP_DATA_PAGE35_LOCK1_LOCK_S_RESET "-" -#define OTP_DATA_PAGE35_LOCK1_LOCK_S_BITS _u(0x00000003) -#define OTP_DATA_PAGE35_LOCK1_LOCK_S_MSB _u(1) -#define OTP_DATA_PAGE35_LOCK1_LOCK_S_LSB _u(0) -#define OTP_DATA_PAGE35_LOCK1_LOCK_S_ACCESS "RO" -#define OTP_DATA_PAGE35_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE35_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE35_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE35_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) -// ============================================================================= -// Register : OTP_DATA_PAGE36_LOCK0 -// Description : Lock configuration LSBs for page 36 (rows 0x900 through 0x93f). -// Locks are stored with 3-way majority vote encoding, so that -// bits can be set independently. -// -// This OTP location is always readable, and is write-protected by -// its own permissions. -#define OTP_DATA_PAGE36_LOCK0_ROW _u(0x00000fc8) -#define OTP_DATA_PAGE36_LOCK0_BITS _u(0x00ffff7f) -#define OTP_DATA_PAGE36_LOCK0_RESET _u(0x00000000) -#define OTP_DATA_PAGE36_LOCK0_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE36_LOCK0_R2 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE36_LOCK0_R2_RESET "-" -#define OTP_DATA_PAGE36_LOCK0_R2_BITS _u(0x00ff0000) -#define OTP_DATA_PAGE36_LOCK0_R2_MSB _u(23) -#define OTP_DATA_PAGE36_LOCK0_R2_LSB _u(16) -#define OTP_DATA_PAGE36_LOCK0_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE36_LOCK0_R1 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE36_LOCK0_R1_RESET "-" -#define OTP_DATA_PAGE36_LOCK0_R1_BITS _u(0x0000ff00) -#define OTP_DATA_PAGE36_LOCK0_R1_MSB _u(15) -#define OTP_DATA_PAGE36_LOCK0_R1_LSB _u(8) -#define OTP_DATA_PAGE36_LOCK0_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE36_LOCK0_NO_KEY_STATE -// Description : State when at least one key is registered for this page and no -// matching key has been entered. -// 0x0 -> read_only -// 0x1 -> inaccessible -#define OTP_DATA_PAGE36_LOCK0_NO_KEY_STATE_RESET "-" -#define OTP_DATA_PAGE36_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) -#define OTP_DATA_PAGE36_LOCK0_NO_KEY_STATE_MSB _u(6) -#define OTP_DATA_PAGE36_LOCK0_NO_KEY_STATE_LSB _u(6) -#define OTP_DATA_PAGE36_LOCK0_NO_KEY_STATE_ACCESS "RO" -#define OTP_DATA_PAGE36_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) -#define OTP_DATA_PAGE36_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE36_LOCK0_KEY_R -// Description : Index 1-6 of a hardware key which must be entered to grant read -// access, or 0 if no such key is required. -#define OTP_DATA_PAGE36_LOCK0_KEY_R_RESET "-" -#define OTP_DATA_PAGE36_LOCK0_KEY_R_BITS _u(0x00000038) -#define OTP_DATA_PAGE36_LOCK0_KEY_R_MSB _u(5) -#define OTP_DATA_PAGE36_LOCK0_KEY_R_LSB _u(3) -#define OTP_DATA_PAGE36_LOCK0_KEY_R_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE36_LOCK0_KEY_W -// Description : Index 1-6 of a hardware key which must be entered to grant -// write access, or 0 if no such key is required. -#define OTP_DATA_PAGE36_LOCK0_KEY_W_RESET "-" -#define OTP_DATA_PAGE36_LOCK0_KEY_W_BITS _u(0x00000007) -#define OTP_DATA_PAGE36_LOCK0_KEY_W_MSB _u(2) -#define OTP_DATA_PAGE36_LOCK0_KEY_W_LSB _u(0) -#define OTP_DATA_PAGE36_LOCK0_KEY_W_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_PAGE36_LOCK1 -// Description : Lock configuration MSBs for page 36 (rows 0x900 through 0x93f). -// Locks are stored with 3-way majority vote encoding, so that -// bits can be set independently. -// -// This OTP location is always readable, and is write-protected by -// its own permissions. -#define OTP_DATA_PAGE36_LOCK1_ROW _u(0x00000fc9) -#define OTP_DATA_PAGE36_LOCK1_BITS _u(0x00ffff3f) -#define OTP_DATA_PAGE36_LOCK1_RESET _u(0x00000000) -#define OTP_DATA_PAGE36_LOCK1_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE36_LOCK1_R2 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE36_LOCK1_R2_RESET "-" -#define OTP_DATA_PAGE36_LOCK1_R2_BITS _u(0x00ff0000) -#define OTP_DATA_PAGE36_LOCK1_R2_MSB _u(23) -#define OTP_DATA_PAGE36_LOCK1_R2_LSB _u(16) -#define OTP_DATA_PAGE36_LOCK1_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE36_LOCK1_R1 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE36_LOCK1_R1_RESET "-" -#define OTP_DATA_PAGE36_LOCK1_R1_BITS _u(0x0000ff00) -#define OTP_DATA_PAGE36_LOCK1_R1_MSB _u(15) -#define OTP_DATA_PAGE36_LOCK1_R1_LSB _u(8) -#define OTP_DATA_PAGE36_LOCK1_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE36_LOCK1_LOCK_BL -// Description : Dummy lock bits reserved for bootloaders (including the RP2350 -// USB bootloader) to store their own OTP access permissions. No -// hardware effect, and no corresponding SW_LOCKx registers. -// 0x0 -> Bootloader permits user reads and writes to this page -// 0x1 -> Bootloader permits user reads of this page -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE -// 0x3 -> Bootloader does not permit user access to this page -#define OTP_DATA_PAGE36_LOCK1_LOCK_BL_RESET "-" -#define OTP_DATA_PAGE36_LOCK1_LOCK_BL_BITS _u(0x00000030) -#define OTP_DATA_PAGE36_LOCK1_LOCK_BL_MSB _u(5) -#define OTP_DATA_PAGE36_LOCK1_LOCK_BL_LSB _u(4) -#define OTP_DATA_PAGE36_LOCK1_LOCK_BL_ACCESS "RO" -#define OTP_DATA_PAGE36_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE36_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE36_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE36_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE36_LOCK1_LOCK_NS -// Description : Lock state for Non-secure accesses to this page. Thermometer- -// coded, so lock state can be advanced permanently from any state -// to any less-permissive state by programming OTP. Software can -// also advance the lock state temporarily (until next OTP reset) -// using the SW_LOCKx registers. -// -// Note that READ_WRITE and READ_ONLY are equivalent in hardware, -// as the SBPI programming interface is not accessible to Non- -// secure software. However, Secure software may check these bits -// to apply write permissions to a Non-secure OTP programming API. -// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. -// 0x1 -> Page can be read by Non-secure software -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. -// 0x3 -> Page can not be accessed by Non-secure software. -#define OTP_DATA_PAGE36_LOCK1_LOCK_NS_RESET "-" -#define OTP_DATA_PAGE36_LOCK1_LOCK_NS_BITS _u(0x0000000c) -#define OTP_DATA_PAGE36_LOCK1_LOCK_NS_MSB _u(3) -#define OTP_DATA_PAGE36_LOCK1_LOCK_NS_LSB _u(2) -#define OTP_DATA_PAGE36_LOCK1_LOCK_NS_ACCESS "RO" -#define OTP_DATA_PAGE36_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE36_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE36_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE36_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE36_LOCK1_LOCK_S -// Description : Lock state for Secure accesses to this page. Thermometer-coded, -// so lock state can be advanced permanently from any state to any -// less-permissive state by programming OTP. Software can also -// advance the lock state temporarily (until next OTP reset) using -// the SW_LOCKx registers. -// 0x0 -> Page is fully accessible by Secure software. -// 0x1 -> Page can be read by Secure software, but can not be written. -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. -// 0x3 -> Page can not be accessed by Secure software. -#define OTP_DATA_PAGE36_LOCK1_LOCK_S_RESET "-" -#define OTP_DATA_PAGE36_LOCK1_LOCK_S_BITS _u(0x00000003) -#define OTP_DATA_PAGE36_LOCK1_LOCK_S_MSB _u(1) -#define OTP_DATA_PAGE36_LOCK1_LOCK_S_LSB _u(0) -#define OTP_DATA_PAGE36_LOCK1_LOCK_S_ACCESS "RO" -#define OTP_DATA_PAGE36_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE36_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE36_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE36_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) -// ============================================================================= -// Register : OTP_DATA_PAGE37_LOCK0 -// Description : Lock configuration LSBs for page 37 (rows 0x940 through 0x97f). -// Locks are stored with 3-way majority vote encoding, so that -// bits can be set independently. -// -// This OTP location is always readable, and is write-protected by -// its own permissions. -#define OTP_DATA_PAGE37_LOCK0_ROW _u(0x00000fca) -#define OTP_DATA_PAGE37_LOCK0_BITS _u(0x00ffff7f) -#define OTP_DATA_PAGE37_LOCK0_RESET _u(0x00000000) -#define OTP_DATA_PAGE37_LOCK0_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE37_LOCK0_R2 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE37_LOCK0_R2_RESET "-" -#define OTP_DATA_PAGE37_LOCK0_R2_BITS _u(0x00ff0000) -#define OTP_DATA_PAGE37_LOCK0_R2_MSB _u(23) -#define OTP_DATA_PAGE37_LOCK0_R2_LSB _u(16) -#define OTP_DATA_PAGE37_LOCK0_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE37_LOCK0_R1 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE37_LOCK0_R1_RESET "-" -#define OTP_DATA_PAGE37_LOCK0_R1_BITS _u(0x0000ff00) -#define OTP_DATA_PAGE37_LOCK0_R1_MSB _u(15) -#define OTP_DATA_PAGE37_LOCK0_R1_LSB _u(8) -#define OTP_DATA_PAGE37_LOCK0_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE37_LOCK0_NO_KEY_STATE -// Description : State when at least one key is registered for this page and no -// matching key has been entered. -// 0x0 -> read_only -// 0x1 -> inaccessible -#define OTP_DATA_PAGE37_LOCK0_NO_KEY_STATE_RESET "-" -#define OTP_DATA_PAGE37_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) -#define OTP_DATA_PAGE37_LOCK0_NO_KEY_STATE_MSB _u(6) -#define OTP_DATA_PAGE37_LOCK0_NO_KEY_STATE_LSB _u(6) -#define OTP_DATA_PAGE37_LOCK0_NO_KEY_STATE_ACCESS "RO" -#define OTP_DATA_PAGE37_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) -#define OTP_DATA_PAGE37_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE37_LOCK0_KEY_R -// Description : Index 1-6 of a hardware key which must be entered to grant read -// access, or 0 if no such key is required. -#define OTP_DATA_PAGE37_LOCK0_KEY_R_RESET "-" -#define OTP_DATA_PAGE37_LOCK0_KEY_R_BITS _u(0x00000038) -#define OTP_DATA_PAGE37_LOCK0_KEY_R_MSB _u(5) -#define OTP_DATA_PAGE37_LOCK0_KEY_R_LSB _u(3) -#define OTP_DATA_PAGE37_LOCK0_KEY_R_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE37_LOCK0_KEY_W -// Description : Index 1-6 of a hardware key which must be entered to grant -// write access, or 0 if no such key is required. -#define OTP_DATA_PAGE37_LOCK0_KEY_W_RESET "-" -#define OTP_DATA_PAGE37_LOCK0_KEY_W_BITS _u(0x00000007) -#define OTP_DATA_PAGE37_LOCK0_KEY_W_MSB _u(2) -#define OTP_DATA_PAGE37_LOCK0_KEY_W_LSB _u(0) -#define OTP_DATA_PAGE37_LOCK0_KEY_W_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_PAGE37_LOCK1 -// Description : Lock configuration MSBs for page 37 (rows 0x940 through 0x97f). -// Locks are stored with 3-way majority vote encoding, so that -// bits can be set independently. -// -// This OTP location is always readable, and is write-protected by -// its own permissions. -#define OTP_DATA_PAGE37_LOCK1_ROW _u(0x00000fcb) -#define OTP_DATA_PAGE37_LOCK1_BITS _u(0x00ffff3f) -#define OTP_DATA_PAGE37_LOCK1_RESET _u(0x00000000) -#define OTP_DATA_PAGE37_LOCK1_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE37_LOCK1_R2 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE37_LOCK1_R2_RESET "-" -#define OTP_DATA_PAGE37_LOCK1_R2_BITS _u(0x00ff0000) -#define OTP_DATA_PAGE37_LOCK1_R2_MSB _u(23) -#define OTP_DATA_PAGE37_LOCK1_R2_LSB _u(16) -#define OTP_DATA_PAGE37_LOCK1_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE37_LOCK1_R1 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE37_LOCK1_R1_RESET "-" -#define OTP_DATA_PAGE37_LOCK1_R1_BITS _u(0x0000ff00) -#define OTP_DATA_PAGE37_LOCK1_R1_MSB _u(15) -#define OTP_DATA_PAGE37_LOCK1_R1_LSB _u(8) -#define OTP_DATA_PAGE37_LOCK1_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE37_LOCK1_LOCK_BL -// Description : Dummy lock bits reserved for bootloaders (including the RP2350 -// USB bootloader) to store their own OTP access permissions. No -// hardware effect, and no corresponding SW_LOCKx registers. -// 0x0 -> Bootloader permits user reads and writes to this page -// 0x1 -> Bootloader permits user reads of this page -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE -// 0x3 -> Bootloader does not permit user access to this page -#define OTP_DATA_PAGE37_LOCK1_LOCK_BL_RESET "-" -#define OTP_DATA_PAGE37_LOCK1_LOCK_BL_BITS _u(0x00000030) -#define OTP_DATA_PAGE37_LOCK1_LOCK_BL_MSB _u(5) -#define OTP_DATA_PAGE37_LOCK1_LOCK_BL_LSB _u(4) -#define OTP_DATA_PAGE37_LOCK1_LOCK_BL_ACCESS "RO" -#define OTP_DATA_PAGE37_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE37_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE37_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE37_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE37_LOCK1_LOCK_NS -// Description : Lock state for Non-secure accesses to this page. Thermometer- -// coded, so lock state can be advanced permanently from any state -// to any less-permissive state by programming OTP. Software can -// also advance the lock state temporarily (until next OTP reset) -// using the SW_LOCKx registers. -// -// Note that READ_WRITE and READ_ONLY are equivalent in hardware, -// as the SBPI programming interface is not accessible to Non- -// secure software. However, Secure software may check these bits -// to apply write permissions to a Non-secure OTP programming API. -// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. -// 0x1 -> Page can be read by Non-secure software -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. -// 0x3 -> Page can not be accessed by Non-secure software. -#define OTP_DATA_PAGE37_LOCK1_LOCK_NS_RESET "-" -#define OTP_DATA_PAGE37_LOCK1_LOCK_NS_BITS _u(0x0000000c) -#define OTP_DATA_PAGE37_LOCK1_LOCK_NS_MSB _u(3) -#define OTP_DATA_PAGE37_LOCK1_LOCK_NS_LSB _u(2) -#define OTP_DATA_PAGE37_LOCK1_LOCK_NS_ACCESS "RO" -#define OTP_DATA_PAGE37_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE37_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE37_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE37_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE37_LOCK1_LOCK_S -// Description : Lock state for Secure accesses to this page. Thermometer-coded, -// so lock state can be advanced permanently from any state to any -// less-permissive state by programming OTP. Software can also -// advance the lock state temporarily (until next OTP reset) using -// the SW_LOCKx registers. -// 0x0 -> Page is fully accessible by Secure software. -// 0x1 -> Page can be read by Secure software, but can not be written. -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. -// 0x3 -> Page can not be accessed by Secure software. -#define OTP_DATA_PAGE37_LOCK1_LOCK_S_RESET "-" -#define OTP_DATA_PAGE37_LOCK1_LOCK_S_BITS _u(0x00000003) -#define OTP_DATA_PAGE37_LOCK1_LOCK_S_MSB _u(1) -#define OTP_DATA_PAGE37_LOCK1_LOCK_S_LSB _u(0) -#define OTP_DATA_PAGE37_LOCK1_LOCK_S_ACCESS "RO" -#define OTP_DATA_PAGE37_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE37_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE37_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE37_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) -// ============================================================================= -// Register : OTP_DATA_PAGE38_LOCK0 -// Description : Lock configuration LSBs for page 38 (rows 0x980 through 0x9bf). -// Locks are stored with 3-way majority vote encoding, so that -// bits can be set independently. -// -// This OTP location is always readable, and is write-protected by -// its own permissions. -#define OTP_DATA_PAGE38_LOCK0_ROW _u(0x00000fcc) -#define OTP_DATA_PAGE38_LOCK0_BITS _u(0x00ffff7f) -#define OTP_DATA_PAGE38_LOCK0_RESET _u(0x00000000) -#define OTP_DATA_PAGE38_LOCK0_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE38_LOCK0_R2 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE38_LOCK0_R2_RESET "-" -#define OTP_DATA_PAGE38_LOCK0_R2_BITS _u(0x00ff0000) -#define OTP_DATA_PAGE38_LOCK0_R2_MSB _u(23) -#define OTP_DATA_PAGE38_LOCK0_R2_LSB _u(16) -#define OTP_DATA_PAGE38_LOCK0_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE38_LOCK0_R1 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE38_LOCK0_R1_RESET "-" -#define OTP_DATA_PAGE38_LOCK0_R1_BITS _u(0x0000ff00) -#define OTP_DATA_PAGE38_LOCK0_R1_MSB _u(15) -#define OTP_DATA_PAGE38_LOCK0_R1_LSB _u(8) -#define OTP_DATA_PAGE38_LOCK0_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE38_LOCK0_NO_KEY_STATE -// Description : State when at least one key is registered for this page and no -// matching key has been entered. -// 0x0 -> read_only -// 0x1 -> inaccessible -#define OTP_DATA_PAGE38_LOCK0_NO_KEY_STATE_RESET "-" -#define OTP_DATA_PAGE38_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) -#define OTP_DATA_PAGE38_LOCK0_NO_KEY_STATE_MSB _u(6) -#define OTP_DATA_PAGE38_LOCK0_NO_KEY_STATE_LSB _u(6) -#define OTP_DATA_PAGE38_LOCK0_NO_KEY_STATE_ACCESS "RO" -#define OTP_DATA_PAGE38_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) -#define OTP_DATA_PAGE38_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE38_LOCK0_KEY_R -// Description : Index 1-6 of a hardware key which must be entered to grant read -// access, or 0 if no such key is required. -#define OTP_DATA_PAGE38_LOCK0_KEY_R_RESET "-" -#define OTP_DATA_PAGE38_LOCK0_KEY_R_BITS _u(0x00000038) -#define OTP_DATA_PAGE38_LOCK0_KEY_R_MSB _u(5) -#define OTP_DATA_PAGE38_LOCK0_KEY_R_LSB _u(3) -#define OTP_DATA_PAGE38_LOCK0_KEY_R_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE38_LOCK0_KEY_W -// Description : Index 1-6 of a hardware key which must be entered to grant -// write access, or 0 if no such key is required. -#define OTP_DATA_PAGE38_LOCK0_KEY_W_RESET "-" -#define OTP_DATA_PAGE38_LOCK0_KEY_W_BITS _u(0x00000007) -#define OTP_DATA_PAGE38_LOCK0_KEY_W_MSB _u(2) -#define OTP_DATA_PAGE38_LOCK0_KEY_W_LSB _u(0) -#define OTP_DATA_PAGE38_LOCK0_KEY_W_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_PAGE38_LOCK1 -// Description : Lock configuration MSBs for page 38 (rows 0x980 through 0x9bf). -// Locks are stored with 3-way majority vote encoding, so that -// bits can be set independently. -// -// This OTP location is always readable, and is write-protected by -// its own permissions. -#define OTP_DATA_PAGE38_LOCK1_ROW _u(0x00000fcd) -#define OTP_DATA_PAGE38_LOCK1_BITS _u(0x00ffff3f) -#define OTP_DATA_PAGE38_LOCK1_RESET _u(0x00000000) -#define OTP_DATA_PAGE38_LOCK1_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE38_LOCK1_R2 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE38_LOCK1_R2_RESET "-" -#define OTP_DATA_PAGE38_LOCK1_R2_BITS _u(0x00ff0000) -#define OTP_DATA_PAGE38_LOCK1_R2_MSB _u(23) -#define OTP_DATA_PAGE38_LOCK1_R2_LSB _u(16) -#define OTP_DATA_PAGE38_LOCK1_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE38_LOCK1_R1 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE38_LOCK1_R1_RESET "-" -#define OTP_DATA_PAGE38_LOCK1_R1_BITS _u(0x0000ff00) -#define OTP_DATA_PAGE38_LOCK1_R1_MSB _u(15) -#define OTP_DATA_PAGE38_LOCK1_R1_LSB _u(8) -#define OTP_DATA_PAGE38_LOCK1_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE38_LOCK1_LOCK_BL -// Description : Dummy lock bits reserved for bootloaders (including the RP2350 -// USB bootloader) to store their own OTP access permissions. No -// hardware effect, and no corresponding SW_LOCKx registers. -// 0x0 -> Bootloader permits user reads and writes to this page -// 0x1 -> Bootloader permits user reads of this page -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE -// 0x3 -> Bootloader does not permit user access to this page -#define OTP_DATA_PAGE38_LOCK1_LOCK_BL_RESET "-" -#define OTP_DATA_PAGE38_LOCK1_LOCK_BL_BITS _u(0x00000030) -#define OTP_DATA_PAGE38_LOCK1_LOCK_BL_MSB _u(5) -#define OTP_DATA_PAGE38_LOCK1_LOCK_BL_LSB _u(4) -#define OTP_DATA_PAGE38_LOCK1_LOCK_BL_ACCESS "RO" -#define OTP_DATA_PAGE38_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE38_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE38_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE38_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE38_LOCK1_LOCK_NS -// Description : Lock state for Non-secure accesses to this page. Thermometer- -// coded, so lock state can be advanced permanently from any state -// to any less-permissive state by programming OTP. Software can -// also advance the lock state temporarily (until next OTP reset) -// using the SW_LOCKx registers. -// -// Note that READ_WRITE and READ_ONLY are equivalent in hardware, -// as the SBPI programming interface is not accessible to Non- -// secure software. However, Secure software may check these bits -// to apply write permissions to a Non-secure OTP programming API. -// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. -// 0x1 -> Page can be read by Non-secure software -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. -// 0x3 -> Page can not be accessed by Non-secure software. -#define OTP_DATA_PAGE38_LOCK1_LOCK_NS_RESET "-" -#define OTP_DATA_PAGE38_LOCK1_LOCK_NS_BITS _u(0x0000000c) -#define OTP_DATA_PAGE38_LOCK1_LOCK_NS_MSB _u(3) -#define OTP_DATA_PAGE38_LOCK1_LOCK_NS_LSB _u(2) -#define OTP_DATA_PAGE38_LOCK1_LOCK_NS_ACCESS "RO" -#define OTP_DATA_PAGE38_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE38_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE38_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE38_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE38_LOCK1_LOCK_S -// Description : Lock state for Secure accesses to this page. Thermometer-coded, -// so lock state can be advanced permanently from any state to any -// less-permissive state by programming OTP. Software can also -// advance the lock state temporarily (until next OTP reset) using -// the SW_LOCKx registers. -// 0x0 -> Page is fully accessible by Secure software. -// 0x1 -> Page can be read by Secure software, but can not be written. -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. -// 0x3 -> Page can not be accessed by Secure software. -#define OTP_DATA_PAGE38_LOCK1_LOCK_S_RESET "-" -#define OTP_DATA_PAGE38_LOCK1_LOCK_S_BITS _u(0x00000003) -#define OTP_DATA_PAGE38_LOCK1_LOCK_S_MSB _u(1) -#define OTP_DATA_PAGE38_LOCK1_LOCK_S_LSB _u(0) -#define OTP_DATA_PAGE38_LOCK1_LOCK_S_ACCESS "RO" -#define OTP_DATA_PAGE38_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE38_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE38_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE38_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) -// ============================================================================= -// Register : OTP_DATA_PAGE39_LOCK0 -// Description : Lock configuration LSBs for page 39 (rows 0x9c0 through 0x9ff). -// Locks are stored with 3-way majority vote encoding, so that -// bits can be set independently. -// -// This OTP location is always readable, and is write-protected by -// its own permissions. -#define OTP_DATA_PAGE39_LOCK0_ROW _u(0x00000fce) -#define OTP_DATA_PAGE39_LOCK0_BITS _u(0x00ffff7f) -#define OTP_DATA_PAGE39_LOCK0_RESET _u(0x00000000) -#define OTP_DATA_PAGE39_LOCK0_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE39_LOCK0_R2 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE39_LOCK0_R2_RESET "-" -#define OTP_DATA_PAGE39_LOCK0_R2_BITS _u(0x00ff0000) -#define OTP_DATA_PAGE39_LOCK0_R2_MSB _u(23) -#define OTP_DATA_PAGE39_LOCK0_R2_LSB _u(16) -#define OTP_DATA_PAGE39_LOCK0_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE39_LOCK0_R1 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE39_LOCK0_R1_RESET "-" -#define OTP_DATA_PAGE39_LOCK0_R1_BITS _u(0x0000ff00) -#define OTP_DATA_PAGE39_LOCK0_R1_MSB _u(15) -#define OTP_DATA_PAGE39_LOCK0_R1_LSB _u(8) -#define OTP_DATA_PAGE39_LOCK0_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE39_LOCK0_NO_KEY_STATE -// Description : State when at least one key is registered for this page and no -// matching key has been entered. -// 0x0 -> read_only -// 0x1 -> inaccessible -#define OTP_DATA_PAGE39_LOCK0_NO_KEY_STATE_RESET "-" -#define OTP_DATA_PAGE39_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) -#define OTP_DATA_PAGE39_LOCK0_NO_KEY_STATE_MSB _u(6) -#define OTP_DATA_PAGE39_LOCK0_NO_KEY_STATE_LSB _u(6) -#define OTP_DATA_PAGE39_LOCK0_NO_KEY_STATE_ACCESS "RO" -#define OTP_DATA_PAGE39_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) -#define OTP_DATA_PAGE39_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE39_LOCK0_KEY_R -// Description : Index 1-6 of a hardware key which must be entered to grant read -// access, or 0 if no such key is required. -#define OTP_DATA_PAGE39_LOCK0_KEY_R_RESET "-" -#define OTP_DATA_PAGE39_LOCK0_KEY_R_BITS _u(0x00000038) -#define OTP_DATA_PAGE39_LOCK0_KEY_R_MSB _u(5) -#define OTP_DATA_PAGE39_LOCK0_KEY_R_LSB _u(3) -#define OTP_DATA_PAGE39_LOCK0_KEY_R_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE39_LOCK0_KEY_W -// Description : Index 1-6 of a hardware key which must be entered to grant -// write access, or 0 if no such key is required. -#define OTP_DATA_PAGE39_LOCK0_KEY_W_RESET "-" -#define OTP_DATA_PAGE39_LOCK0_KEY_W_BITS _u(0x00000007) -#define OTP_DATA_PAGE39_LOCK0_KEY_W_MSB _u(2) -#define OTP_DATA_PAGE39_LOCK0_KEY_W_LSB _u(0) -#define OTP_DATA_PAGE39_LOCK0_KEY_W_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_PAGE39_LOCK1 -// Description : Lock configuration MSBs for page 39 (rows 0x9c0 through 0x9ff). -// Locks are stored with 3-way majority vote encoding, so that -// bits can be set independently. -// -// This OTP location is always readable, and is write-protected by -// its own permissions. -#define OTP_DATA_PAGE39_LOCK1_ROW _u(0x00000fcf) -#define OTP_DATA_PAGE39_LOCK1_BITS _u(0x00ffff3f) -#define OTP_DATA_PAGE39_LOCK1_RESET _u(0x00000000) -#define OTP_DATA_PAGE39_LOCK1_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE39_LOCK1_R2 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE39_LOCK1_R2_RESET "-" -#define OTP_DATA_PAGE39_LOCK1_R2_BITS _u(0x00ff0000) -#define OTP_DATA_PAGE39_LOCK1_R2_MSB _u(23) -#define OTP_DATA_PAGE39_LOCK1_R2_LSB _u(16) -#define OTP_DATA_PAGE39_LOCK1_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE39_LOCK1_R1 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE39_LOCK1_R1_RESET "-" -#define OTP_DATA_PAGE39_LOCK1_R1_BITS _u(0x0000ff00) -#define OTP_DATA_PAGE39_LOCK1_R1_MSB _u(15) -#define OTP_DATA_PAGE39_LOCK1_R1_LSB _u(8) -#define OTP_DATA_PAGE39_LOCK1_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE39_LOCK1_LOCK_BL -// Description : Dummy lock bits reserved for bootloaders (including the RP2350 -// USB bootloader) to store their own OTP access permissions. No -// hardware effect, and no corresponding SW_LOCKx registers. -// 0x0 -> Bootloader permits user reads and writes to this page -// 0x1 -> Bootloader permits user reads of this page -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE -// 0x3 -> Bootloader does not permit user access to this page -#define OTP_DATA_PAGE39_LOCK1_LOCK_BL_RESET "-" -#define OTP_DATA_PAGE39_LOCK1_LOCK_BL_BITS _u(0x00000030) -#define OTP_DATA_PAGE39_LOCK1_LOCK_BL_MSB _u(5) -#define OTP_DATA_PAGE39_LOCK1_LOCK_BL_LSB _u(4) -#define OTP_DATA_PAGE39_LOCK1_LOCK_BL_ACCESS "RO" -#define OTP_DATA_PAGE39_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE39_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE39_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE39_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE39_LOCK1_LOCK_NS -// Description : Lock state for Non-secure accesses to this page. Thermometer- -// coded, so lock state can be advanced permanently from any state -// to any less-permissive state by programming OTP. Software can -// also advance the lock state temporarily (until next OTP reset) -// using the SW_LOCKx registers. -// -// Note that READ_WRITE and READ_ONLY are equivalent in hardware, -// as the SBPI programming interface is not accessible to Non- -// secure software. However, Secure software may check these bits -// to apply write permissions to a Non-secure OTP programming API. -// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. -// 0x1 -> Page can be read by Non-secure software -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. -// 0x3 -> Page can not be accessed by Non-secure software. -#define OTP_DATA_PAGE39_LOCK1_LOCK_NS_RESET "-" -#define OTP_DATA_PAGE39_LOCK1_LOCK_NS_BITS _u(0x0000000c) -#define OTP_DATA_PAGE39_LOCK1_LOCK_NS_MSB _u(3) -#define OTP_DATA_PAGE39_LOCK1_LOCK_NS_LSB _u(2) -#define OTP_DATA_PAGE39_LOCK1_LOCK_NS_ACCESS "RO" -#define OTP_DATA_PAGE39_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE39_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE39_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE39_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE39_LOCK1_LOCK_S -// Description : Lock state for Secure accesses to this page. Thermometer-coded, -// so lock state can be advanced permanently from any state to any -// less-permissive state by programming OTP. Software can also -// advance the lock state temporarily (until next OTP reset) using -// the SW_LOCKx registers. -// 0x0 -> Page is fully accessible by Secure software. -// 0x1 -> Page can be read by Secure software, but can not be written. -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. -// 0x3 -> Page can not be accessed by Secure software. -#define OTP_DATA_PAGE39_LOCK1_LOCK_S_RESET "-" -#define OTP_DATA_PAGE39_LOCK1_LOCK_S_BITS _u(0x00000003) -#define OTP_DATA_PAGE39_LOCK1_LOCK_S_MSB _u(1) -#define OTP_DATA_PAGE39_LOCK1_LOCK_S_LSB _u(0) -#define OTP_DATA_PAGE39_LOCK1_LOCK_S_ACCESS "RO" -#define OTP_DATA_PAGE39_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE39_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE39_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE39_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) -// ============================================================================= -// Register : OTP_DATA_PAGE40_LOCK0 -// Description : Lock configuration LSBs for page 40 (rows 0xa00 through 0xa3f). -// Locks are stored with 3-way majority vote encoding, so that -// bits can be set independently. -// -// This OTP location is always readable, and is write-protected by -// its own permissions. -#define OTP_DATA_PAGE40_LOCK0_ROW _u(0x00000fd0) -#define OTP_DATA_PAGE40_LOCK0_BITS _u(0x00ffff7f) -#define OTP_DATA_PAGE40_LOCK0_RESET _u(0x00000000) -#define OTP_DATA_PAGE40_LOCK0_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE40_LOCK0_R2 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE40_LOCK0_R2_RESET "-" -#define OTP_DATA_PAGE40_LOCK0_R2_BITS _u(0x00ff0000) -#define OTP_DATA_PAGE40_LOCK0_R2_MSB _u(23) -#define OTP_DATA_PAGE40_LOCK0_R2_LSB _u(16) -#define OTP_DATA_PAGE40_LOCK0_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE40_LOCK0_R1 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE40_LOCK0_R1_RESET "-" -#define OTP_DATA_PAGE40_LOCK0_R1_BITS _u(0x0000ff00) -#define OTP_DATA_PAGE40_LOCK0_R1_MSB _u(15) -#define OTP_DATA_PAGE40_LOCK0_R1_LSB _u(8) -#define OTP_DATA_PAGE40_LOCK0_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE40_LOCK0_NO_KEY_STATE -// Description : State when at least one key is registered for this page and no -// matching key has been entered. -// 0x0 -> read_only -// 0x1 -> inaccessible -#define OTP_DATA_PAGE40_LOCK0_NO_KEY_STATE_RESET "-" -#define OTP_DATA_PAGE40_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) -#define OTP_DATA_PAGE40_LOCK0_NO_KEY_STATE_MSB _u(6) -#define OTP_DATA_PAGE40_LOCK0_NO_KEY_STATE_LSB _u(6) -#define OTP_DATA_PAGE40_LOCK0_NO_KEY_STATE_ACCESS "RO" -#define OTP_DATA_PAGE40_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) -#define OTP_DATA_PAGE40_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE40_LOCK0_KEY_R -// Description : Index 1-6 of a hardware key which must be entered to grant read -// access, or 0 if no such key is required. -#define OTP_DATA_PAGE40_LOCK0_KEY_R_RESET "-" -#define OTP_DATA_PAGE40_LOCK0_KEY_R_BITS _u(0x00000038) -#define OTP_DATA_PAGE40_LOCK0_KEY_R_MSB _u(5) -#define OTP_DATA_PAGE40_LOCK0_KEY_R_LSB _u(3) -#define OTP_DATA_PAGE40_LOCK0_KEY_R_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE40_LOCK0_KEY_W -// Description : Index 1-6 of a hardware key which must be entered to grant -// write access, or 0 if no such key is required. -#define OTP_DATA_PAGE40_LOCK0_KEY_W_RESET "-" -#define OTP_DATA_PAGE40_LOCK0_KEY_W_BITS _u(0x00000007) -#define OTP_DATA_PAGE40_LOCK0_KEY_W_MSB _u(2) -#define OTP_DATA_PAGE40_LOCK0_KEY_W_LSB _u(0) -#define OTP_DATA_PAGE40_LOCK0_KEY_W_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_PAGE40_LOCK1 -// Description : Lock configuration MSBs for page 40 (rows 0xa00 through 0xa3f). -// Locks are stored with 3-way majority vote encoding, so that -// bits can be set independently. -// -// This OTP location is always readable, and is write-protected by -// its own permissions. -#define OTP_DATA_PAGE40_LOCK1_ROW _u(0x00000fd1) -#define OTP_DATA_PAGE40_LOCK1_BITS _u(0x00ffff3f) -#define OTP_DATA_PAGE40_LOCK1_RESET _u(0x00000000) -#define OTP_DATA_PAGE40_LOCK1_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE40_LOCK1_R2 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE40_LOCK1_R2_RESET "-" -#define OTP_DATA_PAGE40_LOCK1_R2_BITS _u(0x00ff0000) -#define OTP_DATA_PAGE40_LOCK1_R2_MSB _u(23) -#define OTP_DATA_PAGE40_LOCK1_R2_LSB _u(16) -#define OTP_DATA_PAGE40_LOCK1_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE40_LOCK1_R1 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE40_LOCK1_R1_RESET "-" -#define OTP_DATA_PAGE40_LOCK1_R1_BITS _u(0x0000ff00) -#define OTP_DATA_PAGE40_LOCK1_R1_MSB _u(15) -#define OTP_DATA_PAGE40_LOCK1_R1_LSB _u(8) -#define OTP_DATA_PAGE40_LOCK1_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE40_LOCK1_LOCK_BL -// Description : Dummy lock bits reserved for bootloaders (including the RP2350 -// USB bootloader) to store their own OTP access permissions. No -// hardware effect, and no corresponding SW_LOCKx registers. -// 0x0 -> Bootloader permits user reads and writes to this page -// 0x1 -> Bootloader permits user reads of this page -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE -// 0x3 -> Bootloader does not permit user access to this page -#define OTP_DATA_PAGE40_LOCK1_LOCK_BL_RESET "-" -#define OTP_DATA_PAGE40_LOCK1_LOCK_BL_BITS _u(0x00000030) -#define OTP_DATA_PAGE40_LOCK1_LOCK_BL_MSB _u(5) -#define OTP_DATA_PAGE40_LOCK1_LOCK_BL_LSB _u(4) -#define OTP_DATA_PAGE40_LOCK1_LOCK_BL_ACCESS "RO" -#define OTP_DATA_PAGE40_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE40_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE40_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE40_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE40_LOCK1_LOCK_NS -// Description : Lock state for Non-secure accesses to this page. Thermometer- -// coded, so lock state can be advanced permanently from any state -// to any less-permissive state by programming OTP. Software can -// also advance the lock state temporarily (until next OTP reset) -// using the SW_LOCKx registers. -// -// Note that READ_WRITE and READ_ONLY are equivalent in hardware, -// as the SBPI programming interface is not accessible to Non- -// secure software. However, Secure software may check these bits -// to apply write permissions to a Non-secure OTP programming API. -// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. -// 0x1 -> Page can be read by Non-secure software -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. -// 0x3 -> Page can not be accessed by Non-secure software. -#define OTP_DATA_PAGE40_LOCK1_LOCK_NS_RESET "-" -#define OTP_DATA_PAGE40_LOCK1_LOCK_NS_BITS _u(0x0000000c) -#define OTP_DATA_PAGE40_LOCK1_LOCK_NS_MSB _u(3) -#define OTP_DATA_PAGE40_LOCK1_LOCK_NS_LSB _u(2) -#define OTP_DATA_PAGE40_LOCK1_LOCK_NS_ACCESS "RO" -#define OTP_DATA_PAGE40_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE40_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE40_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE40_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE40_LOCK1_LOCK_S -// Description : Lock state for Secure accesses to this page. Thermometer-coded, -// so lock state can be advanced permanently from any state to any -// less-permissive state by programming OTP. Software can also -// advance the lock state temporarily (until next OTP reset) using -// the SW_LOCKx registers. -// 0x0 -> Page is fully accessible by Secure software. -// 0x1 -> Page can be read by Secure software, but can not be written. -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. -// 0x3 -> Page can not be accessed by Secure software. -#define OTP_DATA_PAGE40_LOCK1_LOCK_S_RESET "-" -#define OTP_DATA_PAGE40_LOCK1_LOCK_S_BITS _u(0x00000003) -#define OTP_DATA_PAGE40_LOCK1_LOCK_S_MSB _u(1) -#define OTP_DATA_PAGE40_LOCK1_LOCK_S_LSB _u(0) -#define OTP_DATA_PAGE40_LOCK1_LOCK_S_ACCESS "RO" -#define OTP_DATA_PAGE40_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE40_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE40_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE40_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) -// ============================================================================= -// Register : OTP_DATA_PAGE41_LOCK0 -// Description : Lock configuration LSBs for page 41 (rows 0xa40 through 0xa7f). -// Locks are stored with 3-way majority vote encoding, so that -// bits can be set independently. -// -// This OTP location is always readable, and is write-protected by -// its own permissions. -#define OTP_DATA_PAGE41_LOCK0_ROW _u(0x00000fd2) -#define OTP_DATA_PAGE41_LOCK0_BITS _u(0x00ffff7f) -#define OTP_DATA_PAGE41_LOCK0_RESET _u(0x00000000) -#define OTP_DATA_PAGE41_LOCK0_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE41_LOCK0_R2 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE41_LOCK0_R2_RESET "-" -#define OTP_DATA_PAGE41_LOCK0_R2_BITS _u(0x00ff0000) -#define OTP_DATA_PAGE41_LOCK0_R2_MSB _u(23) -#define OTP_DATA_PAGE41_LOCK0_R2_LSB _u(16) -#define OTP_DATA_PAGE41_LOCK0_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE41_LOCK0_R1 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE41_LOCK0_R1_RESET "-" -#define OTP_DATA_PAGE41_LOCK0_R1_BITS _u(0x0000ff00) -#define OTP_DATA_PAGE41_LOCK0_R1_MSB _u(15) -#define OTP_DATA_PAGE41_LOCK0_R1_LSB _u(8) -#define OTP_DATA_PAGE41_LOCK0_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE41_LOCK0_NO_KEY_STATE -// Description : State when at least one key is registered for this page and no -// matching key has been entered. -// 0x0 -> read_only -// 0x1 -> inaccessible -#define OTP_DATA_PAGE41_LOCK0_NO_KEY_STATE_RESET "-" -#define OTP_DATA_PAGE41_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) -#define OTP_DATA_PAGE41_LOCK0_NO_KEY_STATE_MSB _u(6) -#define OTP_DATA_PAGE41_LOCK0_NO_KEY_STATE_LSB _u(6) -#define OTP_DATA_PAGE41_LOCK0_NO_KEY_STATE_ACCESS "RO" -#define OTP_DATA_PAGE41_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) -#define OTP_DATA_PAGE41_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE41_LOCK0_KEY_R -// Description : Index 1-6 of a hardware key which must be entered to grant read -// access, or 0 if no such key is required. -#define OTP_DATA_PAGE41_LOCK0_KEY_R_RESET "-" -#define OTP_DATA_PAGE41_LOCK0_KEY_R_BITS _u(0x00000038) -#define OTP_DATA_PAGE41_LOCK0_KEY_R_MSB _u(5) -#define OTP_DATA_PAGE41_LOCK0_KEY_R_LSB _u(3) -#define OTP_DATA_PAGE41_LOCK0_KEY_R_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE41_LOCK0_KEY_W -// Description : Index 1-6 of a hardware key which must be entered to grant -// write access, or 0 if no such key is required. -#define OTP_DATA_PAGE41_LOCK0_KEY_W_RESET "-" -#define OTP_DATA_PAGE41_LOCK0_KEY_W_BITS _u(0x00000007) -#define OTP_DATA_PAGE41_LOCK0_KEY_W_MSB _u(2) -#define OTP_DATA_PAGE41_LOCK0_KEY_W_LSB _u(0) -#define OTP_DATA_PAGE41_LOCK0_KEY_W_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_PAGE41_LOCK1 -// Description : Lock configuration MSBs for page 41 (rows 0xa40 through 0xa7f). -// Locks are stored with 3-way majority vote encoding, so that -// bits can be set independently. -// -// This OTP location is always readable, and is write-protected by -// its own permissions. -#define OTP_DATA_PAGE41_LOCK1_ROW _u(0x00000fd3) -#define OTP_DATA_PAGE41_LOCK1_BITS _u(0x00ffff3f) -#define OTP_DATA_PAGE41_LOCK1_RESET _u(0x00000000) -#define OTP_DATA_PAGE41_LOCK1_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE41_LOCK1_R2 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE41_LOCK1_R2_RESET "-" -#define OTP_DATA_PAGE41_LOCK1_R2_BITS _u(0x00ff0000) -#define OTP_DATA_PAGE41_LOCK1_R2_MSB _u(23) -#define OTP_DATA_PAGE41_LOCK1_R2_LSB _u(16) -#define OTP_DATA_PAGE41_LOCK1_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE41_LOCK1_R1 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE41_LOCK1_R1_RESET "-" -#define OTP_DATA_PAGE41_LOCK1_R1_BITS _u(0x0000ff00) -#define OTP_DATA_PAGE41_LOCK1_R1_MSB _u(15) -#define OTP_DATA_PAGE41_LOCK1_R1_LSB _u(8) -#define OTP_DATA_PAGE41_LOCK1_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE41_LOCK1_LOCK_BL -// Description : Dummy lock bits reserved for bootloaders (including the RP2350 -// USB bootloader) to store their own OTP access permissions. No -// hardware effect, and no corresponding SW_LOCKx registers. -// 0x0 -> Bootloader permits user reads and writes to this page -// 0x1 -> Bootloader permits user reads of this page -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE -// 0x3 -> Bootloader does not permit user access to this page -#define OTP_DATA_PAGE41_LOCK1_LOCK_BL_RESET "-" -#define OTP_DATA_PAGE41_LOCK1_LOCK_BL_BITS _u(0x00000030) -#define OTP_DATA_PAGE41_LOCK1_LOCK_BL_MSB _u(5) -#define OTP_DATA_PAGE41_LOCK1_LOCK_BL_LSB _u(4) -#define OTP_DATA_PAGE41_LOCK1_LOCK_BL_ACCESS "RO" -#define OTP_DATA_PAGE41_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE41_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE41_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE41_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE41_LOCK1_LOCK_NS -// Description : Lock state for Non-secure accesses to this page. Thermometer- -// coded, so lock state can be advanced permanently from any state -// to any less-permissive state by programming OTP. Software can -// also advance the lock state temporarily (until next OTP reset) -// using the SW_LOCKx registers. -// -// Note that READ_WRITE and READ_ONLY are equivalent in hardware, -// as the SBPI programming interface is not accessible to Non- -// secure software. However, Secure software may check these bits -// to apply write permissions to a Non-secure OTP programming API. -// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. -// 0x1 -> Page can be read by Non-secure software -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. -// 0x3 -> Page can not be accessed by Non-secure software. -#define OTP_DATA_PAGE41_LOCK1_LOCK_NS_RESET "-" -#define OTP_DATA_PAGE41_LOCK1_LOCK_NS_BITS _u(0x0000000c) -#define OTP_DATA_PAGE41_LOCK1_LOCK_NS_MSB _u(3) -#define OTP_DATA_PAGE41_LOCK1_LOCK_NS_LSB _u(2) -#define OTP_DATA_PAGE41_LOCK1_LOCK_NS_ACCESS "RO" -#define OTP_DATA_PAGE41_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE41_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE41_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE41_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE41_LOCK1_LOCK_S -// Description : Lock state for Secure accesses to this page. Thermometer-coded, -// so lock state can be advanced permanently from any state to any -// less-permissive state by programming OTP. Software can also -// advance the lock state temporarily (until next OTP reset) using -// the SW_LOCKx registers. -// 0x0 -> Page is fully accessible by Secure software. -// 0x1 -> Page can be read by Secure software, but can not be written. -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. -// 0x3 -> Page can not be accessed by Secure software. -#define OTP_DATA_PAGE41_LOCK1_LOCK_S_RESET "-" -#define OTP_DATA_PAGE41_LOCK1_LOCK_S_BITS _u(0x00000003) -#define OTP_DATA_PAGE41_LOCK1_LOCK_S_MSB _u(1) -#define OTP_DATA_PAGE41_LOCK1_LOCK_S_LSB _u(0) -#define OTP_DATA_PAGE41_LOCK1_LOCK_S_ACCESS "RO" -#define OTP_DATA_PAGE41_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE41_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE41_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE41_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) -// ============================================================================= -// Register : OTP_DATA_PAGE42_LOCK0 -// Description : Lock configuration LSBs for page 42 (rows 0xa80 through 0xabf). -// Locks are stored with 3-way majority vote encoding, so that -// bits can be set independently. -// -// This OTP location is always readable, and is write-protected by -// its own permissions. -#define OTP_DATA_PAGE42_LOCK0_ROW _u(0x00000fd4) -#define OTP_DATA_PAGE42_LOCK0_BITS _u(0x00ffff7f) -#define OTP_DATA_PAGE42_LOCK0_RESET _u(0x00000000) -#define OTP_DATA_PAGE42_LOCK0_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE42_LOCK0_R2 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE42_LOCK0_R2_RESET "-" -#define OTP_DATA_PAGE42_LOCK0_R2_BITS _u(0x00ff0000) -#define OTP_DATA_PAGE42_LOCK0_R2_MSB _u(23) -#define OTP_DATA_PAGE42_LOCK0_R2_LSB _u(16) -#define OTP_DATA_PAGE42_LOCK0_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE42_LOCK0_R1 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE42_LOCK0_R1_RESET "-" -#define OTP_DATA_PAGE42_LOCK0_R1_BITS _u(0x0000ff00) -#define OTP_DATA_PAGE42_LOCK0_R1_MSB _u(15) -#define OTP_DATA_PAGE42_LOCK0_R1_LSB _u(8) -#define OTP_DATA_PAGE42_LOCK0_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE42_LOCK0_NO_KEY_STATE -// Description : State when at least one key is registered for this page and no -// matching key has been entered. -// 0x0 -> read_only -// 0x1 -> inaccessible -#define OTP_DATA_PAGE42_LOCK0_NO_KEY_STATE_RESET "-" -#define OTP_DATA_PAGE42_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) -#define OTP_DATA_PAGE42_LOCK0_NO_KEY_STATE_MSB _u(6) -#define OTP_DATA_PAGE42_LOCK0_NO_KEY_STATE_LSB _u(6) -#define OTP_DATA_PAGE42_LOCK0_NO_KEY_STATE_ACCESS "RO" -#define OTP_DATA_PAGE42_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) -#define OTP_DATA_PAGE42_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE42_LOCK0_KEY_R -// Description : Index 1-6 of a hardware key which must be entered to grant read -// access, or 0 if no such key is required. -#define OTP_DATA_PAGE42_LOCK0_KEY_R_RESET "-" -#define OTP_DATA_PAGE42_LOCK0_KEY_R_BITS _u(0x00000038) -#define OTP_DATA_PAGE42_LOCK0_KEY_R_MSB _u(5) -#define OTP_DATA_PAGE42_LOCK0_KEY_R_LSB _u(3) -#define OTP_DATA_PAGE42_LOCK0_KEY_R_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE42_LOCK0_KEY_W -// Description : Index 1-6 of a hardware key which must be entered to grant -// write access, or 0 if no such key is required. -#define OTP_DATA_PAGE42_LOCK0_KEY_W_RESET "-" -#define OTP_DATA_PAGE42_LOCK0_KEY_W_BITS _u(0x00000007) -#define OTP_DATA_PAGE42_LOCK0_KEY_W_MSB _u(2) -#define OTP_DATA_PAGE42_LOCK0_KEY_W_LSB _u(0) -#define OTP_DATA_PAGE42_LOCK0_KEY_W_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_PAGE42_LOCK1 -// Description : Lock configuration MSBs for page 42 (rows 0xa80 through 0xabf). -// Locks are stored with 3-way majority vote encoding, so that -// bits can be set independently. -// -// This OTP location is always readable, and is write-protected by -// its own permissions. -#define OTP_DATA_PAGE42_LOCK1_ROW _u(0x00000fd5) -#define OTP_DATA_PAGE42_LOCK1_BITS _u(0x00ffff3f) -#define OTP_DATA_PAGE42_LOCK1_RESET _u(0x00000000) -#define OTP_DATA_PAGE42_LOCK1_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE42_LOCK1_R2 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE42_LOCK1_R2_RESET "-" -#define OTP_DATA_PAGE42_LOCK1_R2_BITS _u(0x00ff0000) -#define OTP_DATA_PAGE42_LOCK1_R2_MSB _u(23) -#define OTP_DATA_PAGE42_LOCK1_R2_LSB _u(16) -#define OTP_DATA_PAGE42_LOCK1_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE42_LOCK1_R1 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE42_LOCK1_R1_RESET "-" -#define OTP_DATA_PAGE42_LOCK1_R1_BITS _u(0x0000ff00) -#define OTP_DATA_PAGE42_LOCK1_R1_MSB _u(15) -#define OTP_DATA_PAGE42_LOCK1_R1_LSB _u(8) -#define OTP_DATA_PAGE42_LOCK1_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE42_LOCK1_LOCK_BL -// Description : Dummy lock bits reserved for bootloaders (including the RP2350 -// USB bootloader) to store their own OTP access permissions. No -// hardware effect, and no corresponding SW_LOCKx registers. -// 0x0 -> Bootloader permits user reads and writes to this page -// 0x1 -> Bootloader permits user reads of this page -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE -// 0x3 -> Bootloader does not permit user access to this page -#define OTP_DATA_PAGE42_LOCK1_LOCK_BL_RESET "-" -#define OTP_DATA_PAGE42_LOCK1_LOCK_BL_BITS _u(0x00000030) -#define OTP_DATA_PAGE42_LOCK1_LOCK_BL_MSB _u(5) -#define OTP_DATA_PAGE42_LOCK1_LOCK_BL_LSB _u(4) -#define OTP_DATA_PAGE42_LOCK1_LOCK_BL_ACCESS "RO" -#define OTP_DATA_PAGE42_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE42_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE42_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE42_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE42_LOCK1_LOCK_NS -// Description : Lock state for Non-secure accesses to this page. Thermometer- -// coded, so lock state can be advanced permanently from any state -// to any less-permissive state by programming OTP. Software can -// also advance the lock state temporarily (until next OTP reset) -// using the SW_LOCKx registers. -// -// Note that READ_WRITE and READ_ONLY are equivalent in hardware, -// as the SBPI programming interface is not accessible to Non- -// secure software. However, Secure software may check these bits -// to apply write permissions to a Non-secure OTP programming API. -// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. -// 0x1 -> Page can be read by Non-secure software -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. -// 0x3 -> Page can not be accessed by Non-secure software. -#define OTP_DATA_PAGE42_LOCK1_LOCK_NS_RESET "-" -#define OTP_DATA_PAGE42_LOCK1_LOCK_NS_BITS _u(0x0000000c) -#define OTP_DATA_PAGE42_LOCK1_LOCK_NS_MSB _u(3) -#define OTP_DATA_PAGE42_LOCK1_LOCK_NS_LSB _u(2) -#define OTP_DATA_PAGE42_LOCK1_LOCK_NS_ACCESS "RO" -#define OTP_DATA_PAGE42_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE42_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE42_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE42_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE42_LOCK1_LOCK_S -// Description : Lock state for Secure accesses to this page. Thermometer-coded, -// so lock state can be advanced permanently from any state to any -// less-permissive state by programming OTP. Software can also -// advance the lock state temporarily (until next OTP reset) using -// the SW_LOCKx registers. -// 0x0 -> Page is fully accessible by Secure software. -// 0x1 -> Page can be read by Secure software, but can not be written. -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. -// 0x3 -> Page can not be accessed by Secure software. -#define OTP_DATA_PAGE42_LOCK1_LOCK_S_RESET "-" -#define OTP_DATA_PAGE42_LOCK1_LOCK_S_BITS _u(0x00000003) -#define OTP_DATA_PAGE42_LOCK1_LOCK_S_MSB _u(1) -#define OTP_DATA_PAGE42_LOCK1_LOCK_S_LSB _u(0) -#define OTP_DATA_PAGE42_LOCK1_LOCK_S_ACCESS "RO" -#define OTP_DATA_PAGE42_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE42_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE42_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE42_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) -// ============================================================================= -// Register : OTP_DATA_PAGE43_LOCK0 -// Description : Lock configuration LSBs for page 43 (rows 0xac0 through 0xaff). -// Locks are stored with 3-way majority vote encoding, so that -// bits can be set independently. -// -// This OTP location is always readable, and is write-protected by -// its own permissions. -#define OTP_DATA_PAGE43_LOCK0_ROW _u(0x00000fd6) -#define OTP_DATA_PAGE43_LOCK0_BITS _u(0x00ffff7f) -#define OTP_DATA_PAGE43_LOCK0_RESET _u(0x00000000) -#define OTP_DATA_PAGE43_LOCK0_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE43_LOCK0_R2 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE43_LOCK0_R2_RESET "-" -#define OTP_DATA_PAGE43_LOCK0_R2_BITS _u(0x00ff0000) -#define OTP_DATA_PAGE43_LOCK0_R2_MSB _u(23) -#define OTP_DATA_PAGE43_LOCK0_R2_LSB _u(16) -#define OTP_DATA_PAGE43_LOCK0_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE43_LOCK0_R1 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE43_LOCK0_R1_RESET "-" -#define OTP_DATA_PAGE43_LOCK0_R1_BITS _u(0x0000ff00) -#define OTP_DATA_PAGE43_LOCK0_R1_MSB _u(15) -#define OTP_DATA_PAGE43_LOCK0_R1_LSB _u(8) -#define OTP_DATA_PAGE43_LOCK0_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE43_LOCK0_NO_KEY_STATE -// Description : State when at least one key is registered for this page and no -// matching key has been entered. -// 0x0 -> read_only -// 0x1 -> inaccessible -#define OTP_DATA_PAGE43_LOCK0_NO_KEY_STATE_RESET "-" -#define OTP_DATA_PAGE43_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) -#define OTP_DATA_PAGE43_LOCK0_NO_KEY_STATE_MSB _u(6) -#define OTP_DATA_PAGE43_LOCK0_NO_KEY_STATE_LSB _u(6) -#define OTP_DATA_PAGE43_LOCK0_NO_KEY_STATE_ACCESS "RO" -#define OTP_DATA_PAGE43_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) -#define OTP_DATA_PAGE43_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE43_LOCK0_KEY_R -// Description : Index 1-6 of a hardware key which must be entered to grant read -// access, or 0 if no such key is required. -#define OTP_DATA_PAGE43_LOCK0_KEY_R_RESET "-" -#define OTP_DATA_PAGE43_LOCK0_KEY_R_BITS _u(0x00000038) -#define OTP_DATA_PAGE43_LOCK0_KEY_R_MSB _u(5) -#define OTP_DATA_PAGE43_LOCK0_KEY_R_LSB _u(3) -#define OTP_DATA_PAGE43_LOCK0_KEY_R_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE43_LOCK0_KEY_W -// Description : Index 1-6 of a hardware key which must be entered to grant -// write access, or 0 if no such key is required. -#define OTP_DATA_PAGE43_LOCK0_KEY_W_RESET "-" -#define OTP_DATA_PAGE43_LOCK0_KEY_W_BITS _u(0x00000007) -#define OTP_DATA_PAGE43_LOCK0_KEY_W_MSB _u(2) -#define OTP_DATA_PAGE43_LOCK0_KEY_W_LSB _u(0) -#define OTP_DATA_PAGE43_LOCK0_KEY_W_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_PAGE43_LOCK1 -// Description : Lock configuration MSBs for page 43 (rows 0xac0 through 0xaff). -// Locks are stored with 3-way majority vote encoding, so that -// bits can be set independently. -// -// This OTP location is always readable, and is write-protected by -// its own permissions. -#define OTP_DATA_PAGE43_LOCK1_ROW _u(0x00000fd7) -#define OTP_DATA_PAGE43_LOCK1_BITS _u(0x00ffff3f) -#define OTP_DATA_PAGE43_LOCK1_RESET _u(0x00000000) -#define OTP_DATA_PAGE43_LOCK1_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE43_LOCK1_R2 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE43_LOCK1_R2_RESET "-" -#define OTP_DATA_PAGE43_LOCK1_R2_BITS _u(0x00ff0000) -#define OTP_DATA_PAGE43_LOCK1_R2_MSB _u(23) -#define OTP_DATA_PAGE43_LOCK1_R2_LSB _u(16) -#define OTP_DATA_PAGE43_LOCK1_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE43_LOCK1_R1 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE43_LOCK1_R1_RESET "-" -#define OTP_DATA_PAGE43_LOCK1_R1_BITS _u(0x0000ff00) -#define OTP_DATA_PAGE43_LOCK1_R1_MSB _u(15) -#define OTP_DATA_PAGE43_LOCK1_R1_LSB _u(8) -#define OTP_DATA_PAGE43_LOCK1_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE43_LOCK1_LOCK_BL -// Description : Dummy lock bits reserved for bootloaders (including the RP2350 -// USB bootloader) to store their own OTP access permissions. No -// hardware effect, and no corresponding SW_LOCKx registers. -// 0x0 -> Bootloader permits user reads and writes to this page -// 0x1 -> Bootloader permits user reads of this page -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE -// 0x3 -> Bootloader does not permit user access to this page -#define OTP_DATA_PAGE43_LOCK1_LOCK_BL_RESET "-" -#define OTP_DATA_PAGE43_LOCK1_LOCK_BL_BITS _u(0x00000030) -#define OTP_DATA_PAGE43_LOCK1_LOCK_BL_MSB _u(5) -#define OTP_DATA_PAGE43_LOCK1_LOCK_BL_LSB _u(4) -#define OTP_DATA_PAGE43_LOCK1_LOCK_BL_ACCESS "RO" -#define OTP_DATA_PAGE43_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE43_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE43_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE43_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE43_LOCK1_LOCK_NS -// Description : Lock state for Non-secure accesses to this page. Thermometer- -// coded, so lock state can be advanced permanently from any state -// to any less-permissive state by programming OTP. Software can -// also advance the lock state temporarily (until next OTP reset) -// using the SW_LOCKx registers. -// -// Note that READ_WRITE and READ_ONLY are equivalent in hardware, -// as the SBPI programming interface is not accessible to Non- -// secure software. However, Secure software may check these bits -// to apply write permissions to a Non-secure OTP programming API. -// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. -// 0x1 -> Page can be read by Non-secure software -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. -// 0x3 -> Page can not be accessed by Non-secure software. -#define OTP_DATA_PAGE43_LOCK1_LOCK_NS_RESET "-" -#define OTP_DATA_PAGE43_LOCK1_LOCK_NS_BITS _u(0x0000000c) -#define OTP_DATA_PAGE43_LOCK1_LOCK_NS_MSB _u(3) -#define OTP_DATA_PAGE43_LOCK1_LOCK_NS_LSB _u(2) -#define OTP_DATA_PAGE43_LOCK1_LOCK_NS_ACCESS "RO" -#define OTP_DATA_PAGE43_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE43_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE43_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE43_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE43_LOCK1_LOCK_S -// Description : Lock state for Secure accesses to this page. Thermometer-coded, -// so lock state can be advanced permanently from any state to any -// less-permissive state by programming OTP. Software can also -// advance the lock state temporarily (until next OTP reset) using -// the SW_LOCKx registers. -// 0x0 -> Page is fully accessible by Secure software. -// 0x1 -> Page can be read by Secure software, but can not be written. -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. -// 0x3 -> Page can not be accessed by Secure software. -#define OTP_DATA_PAGE43_LOCK1_LOCK_S_RESET "-" -#define OTP_DATA_PAGE43_LOCK1_LOCK_S_BITS _u(0x00000003) -#define OTP_DATA_PAGE43_LOCK1_LOCK_S_MSB _u(1) -#define OTP_DATA_PAGE43_LOCK1_LOCK_S_LSB _u(0) -#define OTP_DATA_PAGE43_LOCK1_LOCK_S_ACCESS "RO" -#define OTP_DATA_PAGE43_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE43_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE43_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE43_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) -// ============================================================================= -// Register : OTP_DATA_PAGE44_LOCK0 -// Description : Lock configuration LSBs for page 44 (rows 0xb00 through 0xb3f). -// Locks are stored with 3-way majority vote encoding, so that -// bits can be set independently. -// -// This OTP location is always readable, and is write-protected by -// its own permissions. -#define OTP_DATA_PAGE44_LOCK0_ROW _u(0x00000fd8) -#define OTP_DATA_PAGE44_LOCK0_BITS _u(0x00ffff7f) -#define OTP_DATA_PAGE44_LOCK0_RESET _u(0x00000000) -#define OTP_DATA_PAGE44_LOCK0_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE44_LOCK0_R2 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE44_LOCK0_R2_RESET "-" -#define OTP_DATA_PAGE44_LOCK0_R2_BITS _u(0x00ff0000) -#define OTP_DATA_PAGE44_LOCK0_R2_MSB _u(23) -#define OTP_DATA_PAGE44_LOCK0_R2_LSB _u(16) -#define OTP_DATA_PAGE44_LOCK0_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE44_LOCK0_R1 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE44_LOCK0_R1_RESET "-" -#define OTP_DATA_PAGE44_LOCK0_R1_BITS _u(0x0000ff00) -#define OTP_DATA_PAGE44_LOCK0_R1_MSB _u(15) -#define OTP_DATA_PAGE44_LOCK0_R1_LSB _u(8) -#define OTP_DATA_PAGE44_LOCK0_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE44_LOCK0_NO_KEY_STATE -// Description : State when at least one key is registered for this page and no -// matching key has been entered. -// 0x0 -> read_only -// 0x1 -> inaccessible -#define OTP_DATA_PAGE44_LOCK0_NO_KEY_STATE_RESET "-" -#define OTP_DATA_PAGE44_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) -#define OTP_DATA_PAGE44_LOCK0_NO_KEY_STATE_MSB _u(6) -#define OTP_DATA_PAGE44_LOCK0_NO_KEY_STATE_LSB _u(6) -#define OTP_DATA_PAGE44_LOCK0_NO_KEY_STATE_ACCESS "RO" -#define OTP_DATA_PAGE44_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) -#define OTP_DATA_PAGE44_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE44_LOCK0_KEY_R -// Description : Index 1-6 of a hardware key which must be entered to grant read -// access, or 0 if no such key is required. -#define OTP_DATA_PAGE44_LOCK0_KEY_R_RESET "-" -#define OTP_DATA_PAGE44_LOCK0_KEY_R_BITS _u(0x00000038) -#define OTP_DATA_PAGE44_LOCK0_KEY_R_MSB _u(5) -#define OTP_DATA_PAGE44_LOCK0_KEY_R_LSB _u(3) -#define OTP_DATA_PAGE44_LOCK0_KEY_R_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE44_LOCK0_KEY_W -// Description : Index 1-6 of a hardware key which must be entered to grant -// write access, or 0 if no such key is required. -#define OTP_DATA_PAGE44_LOCK0_KEY_W_RESET "-" -#define OTP_DATA_PAGE44_LOCK0_KEY_W_BITS _u(0x00000007) -#define OTP_DATA_PAGE44_LOCK0_KEY_W_MSB _u(2) -#define OTP_DATA_PAGE44_LOCK0_KEY_W_LSB _u(0) -#define OTP_DATA_PAGE44_LOCK0_KEY_W_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_PAGE44_LOCK1 -// Description : Lock configuration MSBs for page 44 (rows 0xb00 through 0xb3f). -// Locks are stored with 3-way majority vote encoding, so that -// bits can be set independently. -// -// This OTP location is always readable, and is write-protected by -// its own permissions. -#define OTP_DATA_PAGE44_LOCK1_ROW _u(0x00000fd9) -#define OTP_DATA_PAGE44_LOCK1_BITS _u(0x00ffff3f) -#define OTP_DATA_PAGE44_LOCK1_RESET _u(0x00000000) -#define OTP_DATA_PAGE44_LOCK1_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE44_LOCK1_R2 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE44_LOCK1_R2_RESET "-" -#define OTP_DATA_PAGE44_LOCK1_R2_BITS _u(0x00ff0000) -#define OTP_DATA_PAGE44_LOCK1_R2_MSB _u(23) -#define OTP_DATA_PAGE44_LOCK1_R2_LSB _u(16) -#define OTP_DATA_PAGE44_LOCK1_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE44_LOCK1_R1 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE44_LOCK1_R1_RESET "-" -#define OTP_DATA_PAGE44_LOCK1_R1_BITS _u(0x0000ff00) -#define OTP_DATA_PAGE44_LOCK1_R1_MSB _u(15) -#define OTP_DATA_PAGE44_LOCK1_R1_LSB _u(8) -#define OTP_DATA_PAGE44_LOCK1_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE44_LOCK1_LOCK_BL -// Description : Dummy lock bits reserved for bootloaders (including the RP2350 -// USB bootloader) to store their own OTP access permissions. No -// hardware effect, and no corresponding SW_LOCKx registers. -// 0x0 -> Bootloader permits user reads and writes to this page -// 0x1 -> Bootloader permits user reads of this page -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE -// 0x3 -> Bootloader does not permit user access to this page -#define OTP_DATA_PAGE44_LOCK1_LOCK_BL_RESET "-" -#define OTP_DATA_PAGE44_LOCK1_LOCK_BL_BITS _u(0x00000030) -#define OTP_DATA_PAGE44_LOCK1_LOCK_BL_MSB _u(5) -#define OTP_DATA_PAGE44_LOCK1_LOCK_BL_LSB _u(4) -#define OTP_DATA_PAGE44_LOCK1_LOCK_BL_ACCESS "RO" -#define OTP_DATA_PAGE44_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE44_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE44_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE44_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE44_LOCK1_LOCK_NS -// Description : Lock state for Non-secure accesses to this page. Thermometer- -// coded, so lock state can be advanced permanently from any state -// to any less-permissive state by programming OTP. Software can -// also advance the lock state temporarily (until next OTP reset) -// using the SW_LOCKx registers. -// -// Note that READ_WRITE and READ_ONLY are equivalent in hardware, -// as the SBPI programming interface is not accessible to Non- -// secure software. However, Secure software may check these bits -// to apply write permissions to a Non-secure OTP programming API. -// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. -// 0x1 -> Page can be read by Non-secure software -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. -// 0x3 -> Page can not be accessed by Non-secure software. -#define OTP_DATA_PAGE44_LOCK1_LOCK_NS_RESET "-" -#define OTP_DATA_PAGE44_LOCK1_LOCK_NS_BITS _u(0x0000000c) -#define OTP_DATA_PAGE44_LOCK1_LOCK_NS_MSB _u(3) -#define OTP_DATA_PAGE44_LOCK1_LOCK_NS_LSB _u(2) -#define OTP_DATA_PAGE44_LOCK1_LOCK_NS_ACCESS "RO" -#define OTP_DATA_PAGE44_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE44_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE44_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE44_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE44_LOCK1_LOCK_S -// Description : Lock state for Secure accesses to this page. Thermometer-coded, -// so lock state can be advanced permanently from any state to any -// less-permissive state by programming OTP. Software can also -// advance the lock state temporarily (until next OTP reset) using -// the SW_LOCKx registers. -// 0x0 -> Page is fully accessible by Secure software. -// 0x1 -> Page can be read by Secure software, but can not be written. -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. -// 0x3 -> Page can not be accessed by Secure software. -#define OTP_DATA_PAGE44_LOCK1_LOCK_S_RESET "-" -#define OTP_DATA_PAGE44_LOCK1_LOCK_S_BITS _u(0x00000003) -#define OTP_DATA_PAGE44_LOCK1_LOCK_S_MSB _u(1) -#define OTP_DATA_PAGE44_LOCK1_LOCK_S_LSB _u(0) -#define OTP_DATA_PAGE44_LOCK1_LOCK_S_ACCESS "RO" -#define OTP_DATA_PAGE44_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE44_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE44_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE44_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) -// ============================================================================= -// Register : OTP_DATA_PAGE45_LOCK0 -// Description : Lock configuration LSBs for page 45 (rows 0xb40 through 0xb7f). -// Locks are stored with 3-way majority vote encoding, so that -// bits can be set independently. -// -// This OTP location is always readable, and is write-protected by -// its own permissions. -#define OTP_DATA_PAGE45_LOCK0_ROW _u(0x00000fda) -#define OTP_DATA_PAGE45_LOCK0_BITS _u(0x00ffff7f) -#define OTP_DATA_PAGE45_LOCK0_RESET _u(0x00000000) -#define OTP_DATA_PAGE45_LOCK0_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE45_LOCK0_R2 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE45_LOCK0_R2_RESET "-" -#define OTP_DATA_PAGE45_LOCK0_R2_BITS _u(0x00ff0000) -#define OTP_DATA_PAGE45_LOCK0_R2_MSB _u(23) -#define OTP_DATA_PAGE45_LOCK0_R2_LSB _u(16) -#define OTP_DATA_PAGE45_LOCK0_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE45_LOCK0_R1 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE45_LOCK0_R1_RESET "-" -#define OTP_DATA_PAGE45_LOCK0_R1_BITS _u(0x0000ff00) -#define OTP_DATA_PAGE45_LOCK0_R1_MSB _u(15) -#define OTP_DATA_PAGE45_LOCK0_R1_LSB _u(8) -#define OTP_DATA_PAGE45_LOCK0_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE45_LOCK0_NO_KEY_STATE -// Description : State when at least one key is registered for this page and no -// matching key has been entered. -// 0x0 -> read_only -// 0x1 -> inaccessible -#define OTP_DATA_PAGE45_LOCK0_NO_KEY_STATE_RESET "-" -#define OTP_DATA_PAGE45_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) -#define OTP_DATA_PAGE45_LOCK0_NO_KEY_STATE_MSB _u(6) -#define OTP_DATA_PAGE45_LOCK0_NO_KEY_STATE_LSB _u(6) -#define OTP_DATA_PAGE45_LOCK0_NO_KEY_STATE_ACCESS "RO" -#define OTP_DATA_PAGE45_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) -#define OTP_DATA_PAGE45_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE45_LOCK0_KEY_R -// Description : Index 1-6 of a hardware key which must be entered to grant read -// access, or 0 if no such key is required. -#define OTP_DATA_PAGE45_LOCK0_KEY_R_RESET "-" -#define OTP_DATA_PAGE45_LOCK0_KEY_R_BITS _u(0x00000038) -#define OTP_DATA_PAGE45_LOCK0_KEY_R_MSB _u(5) -#define OTP_DATA_PAGE45_LOCK0_KEY_R_LSB _u(3) -#define OTP_DATA_PAGE45_LOCK0_KEY_R_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE45_LOCK0_KEY_W -// Description : Index 1-6 of a hardware key which must be entered to grant -// write access, or 0 if no such key is required. -#define OTP_DATA_PAGE45_LOCK0_KEY_W_RESET "-" -#define OTP_DATA_PAGE45_LOCK0_KEY_W_BITS _u(0x00000007) -#define OTP_DATA_PAGE45_LOCK0_KEY_W_MSB _u(2) -#define OTP_DATA_PAGE45_LOCK0_KEY_W_LSB _u(0) -#define OTP_DATA_PAGE45_LOCK0_KEY_W_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_PAGE45_LOCK1 -// Description : Lock configuration MSBs for page 45 (rows 0xb40 through 0xb7f). -// Locks are stored with 3-way majority vote encoding, so that -// bits can be set independently. -// -// This OTP location is always readable, and is write-protected by -// its own permissions. -#define OTP_DATA_PAGE45_LOCK1_ROW _u(0x00000fdb) -#define OTP_DATA_PAGE45_LOCK1_BITS _u(0x00ffff3f) -#define OTP_DATA_PAGE45_LOCK1_RESET _u(0x00000000) -#define OTP_DATA_PAGE45_LOCK1_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE45_LOCK1_R2 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE45_LOCK1_R2_RESET "-" -#define OTP_DATA_PAGE45_LOCK1_R2_BITS _u(0x00ff0000) -#define OTP_DATA_PAGE45_LOCK1_R2_MSB _u(23) -#define OTP_DATA_PAGE45_LOCK1_R2_LSB _u(16) -#define OTP_DATA_PAGE45_LOCK1_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE45_LOCK1_R1 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE45_LOCK1_R1_RESET "-" -#define OTP_DATA_PAGE45_LOCK1_R1_BITS _u(0x0000ff00) -#define OTP_DATA_PAGE45_LOCK1_R1_MSB _u(15) -#define OTP_DATA_PAGE45_LOCK1_R1_LSB _u(8) -#define OTP_DATA_PAGE45_LOCK1_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE45_LOCK1_LOCK_BL -// Description : Dummy lock bits reserved for bootloaders (including the RP2350 -// USB bootloader) to store their own OTP access permissions. No -// hardware effect, and no corresponding SW_LOCKx registers. -// 0x0 -> Bootloader permits user reads and writes to this page -// 0x1 -> Bootloader permits user reads of this page -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE -// 0x3 -> Bootloader does not permit user access to this page -#define OTP_DATA_PAGE45_LOCK1_LOCK_BL_RESET "-" -#define OTP_DATA_PAGE45_LOCK1_LOCK_BL_BITS _u(0x00000030) -#define OTP_DATA_PAGE45_LOCK1_LOCK_BL_MSB _u(5) -#define OTP_DATA_PAGE45_LOCK1_LOCK_BL_LSB _u(4) -#define OTP_DATA_PAGE45_LOCK1_LOCK_BL_ACCESS "RO" -#define OTP_DATA_PAGE45_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE45_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE45_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE45_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE45_LOCK1_LOCK_NS -// Description : Lock state for Non-secure accesses to this page. Thermometer- -// coded, so lock state can be advanced permanently from any state -// to any less-permissive state by programming OTP. Software can -// also advance the lock state temporarily (until next OTP reset) -// using the SW_LOCKx registers. -// -// Note that READ_WRITE and READ_ONLY are equivalent in hardware, -// as the SBPI programming interface is not accessible to Non- -// secure software. However, Secure software may check these bits -// to apply write permissions to a Non-secure OTP programming API. -// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. -// 0x1 -> Page can be read by Non-secure software -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. -// 0x3 -> Page can not be accessed by Non-secure software. -#define OTP_DATA_PAGE45_LOCK1_LOCK_NS_RESET "-" -#define OTP_DATA_PAGE45_LOCK1_LOCK_NS_BITS _u(0x0000000c) -#define OTP_DATA_PAGE45_LOCK1_LOCK_NS_MSB _u(3) -#define OTP_DATA_PAGE45_LOCK1_LOCK_NS_LSB _u(2) -#define OTP_DATA_PAGE45_LOCK1_LOCK_NS_ACCESS "RO" -#define OTP_DATA_PAGE45_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE45_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE45_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE45_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE45_LOCK1_LOCK_S -// Description : Lock state for Secure accesses to this page. Thermometer-coded, -// so lock state can be advanced permanently from any state to any -// less-permissive state by programming OTP. Software can also -// advance the lock state temporarily (until next OTP reset) using -// the SW_LOCKx registers. -// 0x0 -> Page is fully accessible by Secure software. -// 0x1 -> Page can be read by Secure software, but can not be written. -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. -// 0x3 -> Page can not be accessed by Secure software. -#define OTP_DATA_PAGE45_LOCK1_LOCK_S_RESET "-" -#define OTP_DATA_PAGE45_LOCK1_LOCK_S_BITS _u(0x00000003) -#define OTP_DATA_PAGE45_LOCK1_LOCK_S_MSB _u(1) -#define OTP_DATA_PAGE45_LOCK1_LOCK_S_LSB _u(0) -#define OTP_DATA_PAGE45_LOCK1_LOCK_S_ACCESS "RO" -#define OTP_DATA_PAGE45_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE45_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE45_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE45_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) -// ============================================================================= -// Register : OTP_DATA_PAGE46_LOCK0 -// Description : Lock configuration LSBs for page 46 (rows 0xb80 through 0xbbf). -// Locks are stored with 3-way majority vote encoding, so that -// bits can be set independently. -// -// This OTP location is always readable, and is write-protected by -// its own permissions. -#define OTP_DATA_PAGE46_LOCK0_ROW _u(0x00000fdc) -#define OTP_DATA_PAGE46_LOCK0_BITS _u(0x00ffff7f) -#define OTP_DATA_PAGE46_LOCK0_RESET _u(0x00000000) -#define OTP_DATA_PAGE46_LOCK0_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE46_LOCK0_R2 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE46_LOCK0_R2_RESET "-" -#define OTP_DATA_PAGE46_LOCK0_R2_BITS _u(0x00ff0000) -#define OTP_DATA_PAGE46_LOCK0_R2_MSB _u(23) -#define OTP_DATA_PAGE46_LOCK0_R2_LSB _u(16) -#define OTP_DATA_PAGE46_LOCK0_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE46_LOCK0_R1 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE46_LOCK0_R1_RESET "-" -#define OTP_DATA_PAGE46_LOCK0_R1_BITS _u(0x0000ff00) -#define OTP_DATA_PAGE46_LOCK0_R1_MSB _u(15) -#define OTP_DATA_PAGE46_LOCK0_R1_LSB _u(8) -#define OTP_DATA_PAGE46_LOCK0_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE46_LOCK0_NO_KEY_STATE -// Description : State when at least one key is registered for this page and no -// matching key has been entered. -// 0x0 -> read_only -// 0x1 -> inaccessible -#define OTP_DATA_PAGE46_LOCK0_NO_KEY_STATE_RESET "-" -#define OTP_DATA_PAGE46_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) -#define OTP_DATA_PAGE46_LOCK0_NO_KEY_STATE_MSB _u(6) -#define OTP_DATA_PAGE46_LOCK0_NO_KEY_STATE_LSB _u(6) -#define OTP_DATA_PAGE46_LOCK0_NO_KEY_STATE_ACCESS "RO" -#define OTP_DATA_PAGE46_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) -#define OTP_DATA_PAGE46_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE46_LOCK0_KEY_R -// Description : Index 1-6 of a hardware key which must be entered to grant read -// access, or 0 if no such key is required. -#define OTP_DATA_PAGE46_LOCK0_KEY_R_RESET "-" -#define OTP_DATA_PAGE46_LOCK0_KEY_R_BITS _u(0x00000038) -#define OTP_DATA_PAGE46_LOCK0_KEY_R_MSB _u(5) -#define OTP_DATA_PAGE46_LOCK0_KEY_R_LSB _u(3) -#define OTP_DATA_PAGE46_LOCK0_KEY_R_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE46_LOCK0_KEY_W -// Description : Index 1-6 of a hardware key which must be entered to grant -// write access, or 0 if no such key is required. -#define OTP_DATA_PAGE46_LOCK0_KEY_W_RESET "-" -#define OTP_DATA_PAGE46_LOCK0_KEY_W_BITS _u(0x00000007) -#define OTP_DATA_PAGE46_LOCK0_KEY_W_MSB _u(2) -#define OTP_DATA_PAGE46_LOCK0_KEY_W_LSB _u(0) -#define OTP_DATA_PAGE46_LOCK0_KEY_W_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_PAGE46_LOCK1 -// Description : Lock configuration MSBs for page 46 (rows 0xb80 through 0xbbf). -// Locks are stored with 3-way majority vote encoding, so that -// bits can be set independently. -// -// This OTP location is always readable, and is write-protected by -// its own permissions. -#define OTP_DATA_PAGE46_LOCK1_ROW _u(0x00000fdd) -#define OTP_DATA_PAGE46_LOCK1_BITS _u(0x00ffff3f) -#define OTP_DATA_PAGE46_LOCK1_RESET _u(0x00000000) -#define OTP_DATA_PAGE46_LOCK1_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE46_LOCK1_R2 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE46_LOCK1_R2_RESET "-" -#define OTP_DATA_PAGE46_LOCK1_R2_BITS _u(0x00ff0000) -#define OTP_DATA_PAGE46_LOCK1_R2_MSB _u(23) -#define OTP_DATA_PAGE46_LOCK1_R2_LSB _u(16) -#define OTP_DATA_PAGE46_LOCK1_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE46_LOCK1_R1 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE46_LOCK1_R1_RESET "-" -#define OTP_DATA_PAGE46_LOCK1_R1_BITS _u(0x0000ff00) -#define OTP_DATA_PAGE46_LOCK1_R1_MSB _u(15) -#define OTP_DATA_PAGE46_LOCK1_R1_LSB _u(8) -#define OTP_DATA_PAGE46_LOCK1_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE46_LOCK1_LOCK_BL -// Description : Dummy lock bits reserved for bootloaders (including the RP2350 -// USB bootloader) to store their own OTP access permissions. No -// hardware effect, and no corresponding SW_LOCKx registers. -// 0x0 -> Bootloader permits user reads and writes to this page -// 0x1 -> Bootloader permits user reads of this page -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE -// 0x3 -> Bootloader does not permit user access to this page -#define OTP_DATA_PAGE46_LOCK1_LOCK_BL_RESET "-" -#define OTP_DATA_PAGE46_LOCK1_LOCK_BL_BITS _u(0x00000030) -#define OTP_DATA_PAGE46_LOCK1_LOCK_BL_MSB _u(5) -#define OTP_DATA_PAGE46_LOCK1_LOCK_BL_LSB _u(4) -#define OTP_DATA_PAGE46_LOCK1_LOCK_BL_ACCESS "RO" -#define OTP_DATA_PAGE46_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE46_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE46_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE46_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE46_LOCK1_LOCK_NS -// Description : Lock state for Non-secure accesses to this page. Thermometer- -// coded, so lock state can be advanced permanently from any state -// to any less-permissive state by programming OTP. Software can -// also advance the lock state temporarily (until next OTP reset) -// using the SW_LOCKx registers. -// -// Note that READ_WRITE and READ_ONLY are equivalent in hardware, -// as the SBPI programming interface is not accessible to Non- -// secure software. However, Secure software may check these bits -// to apply write permissions to a Non-secure OTP programming API. -// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. -// 0x1 -> Page can be read by Non-secure software -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. -// 0x3 -> Page can not be accessed by Non-secure software. -#define OTP_DATA_PAGE46_LOCK1_LOCK_NS_RESET "-" -#define OTP_DATA_PAGE46_LOCK1_LOCK_NS_BITS _u(0x0000000c) -#define OTP_DATA_PAGE46_LOCK1_LOCK_NS_MSB _u(3) -#define OTP_DATA_PAGE46_LOCK1_LOCK_NS_LSB _u(2) -#define OTP_DATA_PAGE46_LOCK1_LOCK_NS_ACCESS "RO" -#define OTP_DATA_PAGE46_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE46_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE46_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE46_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE46_LOCK1_LOCK_S -// Description : Lock state for Secure accesses to this page. Thermometer-coded, -// so lock state can be advanced permanently from any state to any -// less-permissive state by programming OTP. Software can also -// advance the lock state temporarily (until next OTP reset) using -// the SW_LOCKx registers. -// 0x0 -> Page is fully accessible by Secure software. -// 0x1 -> Page can be read by Secure software, but can not be written. -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. -// 0x3 -> Page can not be accessed by Secure software. -#define OTP_DATA_PAGE46_LOCK1_LOCK_S_RESET "-" -#define OTP_DATA_PAGE46_LOCK1_LOCK_S_BITS _u(0x00000003) -#define OTP_DATA_PAGE46_LOCK1_LOCK_S_MSB _u(1) -#define OTP_DATA_PAGE46_LOCK1_LOCK_S_LSB _u(0) -#define OTP_DATA_PAGE46_LOCK1_LOCK_S_ACCESS "RO" -#define OTP_DATA_PAGE46_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE46_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE46_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE46_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) -// ============================================================================= -// Register : OTP_DATA_PAGE47_LOCK0 -// Description : Lock configuration LSBs for page 47 (rows 0xbc0 through 0xbff). -// Locks are stored with 3-way majority vote encoding, so that -// bits can be set independently. -// -// This OTP location is always readable, and is write-protected by -// its own permissions. -#define OTP_DATA_PAGE47_LOCK0_ROW _u(0x00000fde) -#define OTP_DATA_PAGE47_LOCK0_BITS _u(0x00ffff7f) -#define OTP_DATA_PAGE47_LOCK0_RESET _u(0x00000000) -#define OTP_DATA_PAGE47_LOCK0_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE47_LOCK0_R2 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE47_LOCK0_R2_RESET "-" -#define OTP_DATA_PAGE47_LOCK0_R2_BITS _u(0x00ff0000) -#define OTP_DATA_PAGE47_LOCK0_R2_MSB _u(23) -#define OTP_DATA_PAGE47_LOCK0_R2_LSB _u(16) -#define OTP_DATA_PAGE47_LOCK0_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE47_LOCK0_R1 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE47_LOCK0_R1_RESET "-" -#define OTP_DATA_PAGE47_LOCK0_R1_BITS _u(0x0000ff00) -#define OTP_DATA_PAGE47_LOCK0_R1_MSB _u(15) -#define OTP_DATA_PAGE47_LOCK0_R1_LSB _u(8) -#define OTP_DATA_PAGE47_LOCK0_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE47_LOCK0_NO_KEY_STATE -// Description : State when at least one key is registered for this page and no -// matching key has been entered. -// 0x0 -> read_only -// 0x1 -> inaccessible -#define OTP_DATA_PAGE47_LOCK0_NO_KEY_STATE_RESET "-" -#define OTP_DATA_PAGE47_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) -#define OTP_DATA_PAGE47_LOCK0_NO_KEY_STATE_MSB _u(6) -#define OTP_DATA_PAGE47_LOCK0_NO_KEY_STATE_LSB _u(6) -#define OTP_DATA_PAGE47_LOCK0_NO_KEY_STATE_ACCESS "RO" -#define OTP_DATA_PAGE47_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) -#define OTP_DATA_PAGE47_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE47_LOCK0_KEY_R -// Description : Index 1-6 of a hardware key which must be entered to grant read -// access, or 0 if no such key is required. -#define OTP_DATA_PAGE47_LOCK0_KEY_R_RESET "-" -#define OTP_DATA_PAGE47_LOCK0_KEY_R_BITS _u(0x00000038) -#define OTP_DATA_PAGE47_LOCK0_KEY_R_MSB _u(5) -#define OTP_DATA_PAGE47_LOCK0_KEY_R_LSB _u(3) -#define OTP_DATA_PAGE47_LOCK0_KEY_R_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE47_LOCK0_KEY_W -// Description : Index 1-6 of a hardware key which must be entered to grant -// write access, or 0 if no such key is required. -#define OTP_DATA_PAGE47_LOCK0_KEY_W_RESET "-" -#define OTP_DATA_PAGE47_LOCK0_KEY_W_BITS _u(0x00000007) -#define OTP_DATA_PAGE47_LOCK0_KEY_W_MSB _u(2) -#define OTP_DATA_PAGE47_LOCK0_KEY_W_LSB _u(0) -#define OTP_DATA_PAGE47_LOCK0_KEY_W_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_PAGE47_LOCK1 -// Description : Lock configuration MSBs for page 47 (rows 0xbc0 through 0xbff). -// Locks are stored with 3-way majority vote encoding, so that -// bits can be set independently. -// -// This OTP location is always readable, and is write-protected by -// its own permissions. -#define OTP_DATA_PAGE47_LOCK1_ROW _u(0x00000fdf) -#define OTP_DATA_PAGE47_LOCK1_BITS _u(0x00ffff3f) -#define OTP_DATA_PAGE47_LOCK1_RESET _u(0x00000000) -#define OTP_DATA_PAGE47_LOCK1_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE47_LOCK1_R2 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE47_LOCK1_R2_RESET "-" -#define OTP_DATA_PAGE47_LOCK1_R2_BITS _u(0x00ff0000) -#define OTP_DATA_PAGE47_LOCK1_R2_MSB _u(23) -#define OTP_DATA_PAGE47_LOCK1_R2_LSB _u(16) -#define OTP_DATA_PAGE47_LOCK1_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE47_LOCK1_R1 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE47_LOCK1_R1_RESET "-" -#define OTP_DATA_PAGE47_LOCK1_R1_BITS _u(0x0000ff00) -#define OTP_DATA_PAGE47_LOCK1_R1_MSB _u(15) -#define OTP_DATA_PAGE47_LOCK1_R1_LSB _u(8) -#define OTP_DATA_PAGE47_LOCK1_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE47_LOCK1_LOCK_BL -// Description : Dummy lock bits reserved for bootloaders (including the RP2350 -// USB bootloader) to store their own OTP access permissions. No -// hardware effect, and no corresponding SW_LOCKx registers. -// 0x0 -> Bootloader permits user reads and writes to this page -// 0x1 -> Bootloader permits user reads of this page -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE -// 0x3 -> Bootloader does not permit user access to this page -#define OTP_DATA_PAGE47_LOCK1_LOCK_BL_RESET "-" -#define OTP_DATA_PAGE47_LOCK1_LOCK_BL_BITS _u(0x00000030) -#define OTP_DATA_PAGE47_LOCK1_LOCK_BL_MSB _u(5) -#define OTP_DATA_PAGE47_LOCK1_LOCK_BL_LSB _u(4) -#define OTP_DATA_PAGE47_LOCK1_LOCK_BL_ACCESS "RO" -#define OTP_DATA_PAGE47_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE47_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE47_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE47_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE47_LOCK1_LOCK_NS -// Description : Lock state for Non-secure accesses to this page. Thermometer- -// coded, so lock state can be advanced permanently from any state -// to any less-permissive state by programming OTP. Software can -// also advance the lock state temporarily (until next OTP reset) -// using the SW_LOCKx registers. -// -// Note that READ_WRITE and READ_ONLY are equivalent in hardware, -// as the SBPI programming interface is not accessible to Non- -// secure software. However, Secure software may check these bits -// to apply write permissions to a Non-secure OTP programming API. -// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. -// 0x1 -> Page can be read by Non-secure software -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. -// 0x3 -> Page can not be accessed by Non-secure software. -#define OTP_DATA_PAGE47_LOCK1_LOCK_NS_RESET "-" -#define OTP_DATA_PAGE47_LOCK1_LOCK_NS_BITS _u(0x0000000c) -#define OTP_DATA_PAGE47_LOCK1_LOCK_NS_MSB _u(3) -#define OTP_DATA_PAGE47_LOCK1_LOCK_NS_LSB _u(2) -#define OTP_DATA_PAGE47_LOCK1_LOCK_NS_ACCESS "RO" -#define OTP_DATA_PAGE47_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE47_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE47_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE47_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE47_LOCK1_LOCK_S -// Description : Lock state for Secure accesses to this page. Thermometer-coded, -// so lock state can be advanced permanently from any state to any -// less-permissive state by programming OTP. Software can also -// advance the lock state temporarily (until next OTP reset) using -// the SW_LOCKx registers. -// 0x0 -> Page is fully accessible by Secure software. -// 0x1 -> Page can be read by Secure software, but can not be written. -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. -// 0x3 -> Page can not be accessed by Secure software. -#define OTP_DATA_PAGE47_LOCK1_LOCK_S_RESET "-" -#define OTP_DATA_PAGE47_LOCK1_LOCK_S_BITS _u(0x00000003) -#define OTP_DATA_PAGE47_LOCK1_LOCK_S_MSB _u(1) -#define OTP_DATA_PAGE47_LOCK1_LOCK_S_LSB _u(0) -#define OTP_DATA_PAGE47_LOCK1_LOCK_S_ACCESS "RO" -#define OTP_DATA_PAGE47_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE47_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE47_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE47_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) -// ============================================================================= -// Register : OTP_DATA_PAGE48_LOCK0 -// Description : Lock configuration LSBs for page 48 (rows 0xc00 through 0xc3f). -// Locks are stored with 3-way majority vote encoding, so that -// bits can be set independently. -// -// This OTP location is always readable, and is write-protected by -// its own permissions. -#define OTP_DATA_PAGE48_LOCK0_ROW _u(0x00000fe0) -#define OTP_DATA_PAGE48_LOCK0_BITS _u(0x00ffff7f) -#define OTP_DATA_PAGE48_LOCK0_RESET _u(0x00000000) -#define OTP_DATA_PAGE48_LOCK0_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE48_LOCK0_R2 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE48_LOCK0_R2_RESET "-" -#define OTP_DATA_PAGE48_LOCK0_R2_BITS _u(0x00ff0000) -#define OTP_DATA_PAGE48_LOCK0_R2_MSB _u(23) -#define OTP_DATA_PAGE48_LOCK0_R2_LSB _u(16) -#define OTP_DATA_PAGE48_LOCK0_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE48_LOCK0_R1 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE48_LOCK0_R1_RESET "-" -#define OTP_DATA_PAGE48_LOCK0_R1_BITS _u(0x0000ff00) -#define OTP_DATA_PAGE48_LOCK0_R1_MSB _u(15) -#define OTP_DATA_PAGE48_LOCK0_R1_LSB _u(8) -#define OTP_DATA_PAGE48_LOCK0_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE48_LOCK0_NO_KEY_STATE -// Description : State when at least one key is registered for this page and no -// matching key has been entered. -// 0x0 -> read_only -// 0x1 -> inaccessible -#define OTP_DATA_PAGE48_LOCK0_NO_KEY_STATE_RESET "-" -#define OTP_DATA_PAGE48_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) -#define OTP_DATA_PAGE48_LOCK0_NO_KEY_STATE_MSB _u(6) -#define OTP_DATA_PAGE48_LOCK0_NO_KEY_STATE_LSB _u(6) -#define OTP_DATA_PAGE48_LOCK0_NO_KEY_STATE_ACCESS "RO" -#define OTP_DATA_PAGE48_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) -#define OTP_DATA_PAGE48_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE48_LOCK0_KEY_R -// Description : Index 1-6 of a hardware key which must be entered to grant read -// access, or 0 if no such key is required. -#define OTP_DATA_PAGE48_LOCK0_KEY_R_RESET "-" -#define OTP_DATA_PAGE48_LOCK0_KEY_R_BITS _u(0x00000038) -#define OTP_DATA_PAGE48_LOCK0_KEY_R_MSB _u(5) -#define OTP_DATA_PAGE48_LOCK0_KEY_R_LSB _u(3) -#define OTP_DATA_PAGE48_LOCK0_KEY_R_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE48_LOCK0_KEY_W -// Description : Index 1-6 of a hardware key which must be entered to grant -// write access, or 0 if no such key is required. -#define OTP_DATA_PAGE48_LOCK0_KEY_W_RESET "-" -#define OTP_DATA_PAGE48_LOCK0_KEY_W_BITS _u(0x00000007) -#define OTP_DATA_PAGE48_LOCK0_KEY_W_MSB _u(2) -#define OTP_DATA_PAGE48_LOCK0_KEY_W_LSB _u(0) -#define OTP_DATA_PAGE48_LOCK0_KEY_W_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_PAGE48_LOCK1 -// Description : Lock configuration MSBs for page 48 (rows 0xc00 through 0xc3f). -// Locks are stored with 3-way majority vote encoding, so that -// bits can be set independently. -// -// This OTP location is always readable, and is write-protected by -// its own permissions. -#define OTP_DATA_PAGE48_LOCK1_ROW _u(0x00000fe1) -#define OTP_DATA_PAGE48_LOCK1_BITS _u(0x00ffff3f) -#define OTP_DATA_PAGE48_LOCK1_RESET _u(0x00000000) -#define OTP_DATA_PAGE48_LOCK1_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE48_LOCK1_R2 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE48_LOCK1_R2_RESET "-" -#define OTP_DATA_PAGE48_LOCK1_R2_BITS _u(0x00ff0000) -#define OTP_DATA_PAGE48_LOCK1_R2_MSB _u(23) -#define OTP_DATA_PAGE48_LOCK1_R2_LSB _u(16) -#define OTP_DATA_PAGE48_LOCK1_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE48_LOCK1_R1 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE48_LOCK1_R1_RESET "-" -#define OTP_DATA_PAGE48_LOCK1_R1_BITS _u(0x0000ff00) -#define OTP_DATA_PAGE48_LOCK1_R1_MSB _u(15) -#define OTP_DATA_PAGE48_LOCK1_R1_LSB _u(8) -#define OTP_DATA_PAGE48_LOCK1_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE48_LOCK1_LOCK_BL -// Description : Dummy lock bits reserved for bootloaders (including the RP2350 -// USB bootloader) to store their own OTP access permissions. No -// hardware effect, and no corresponding SW_LOCKx registers. -// 0x0 -> Bootloader permits user reads and writes to this page -// 0x1 -> Bootloader permits user reads of this page -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE -// 0x3 -> Bootloader does not permit user access to this page -#define OTP_DATA_PAGE48_LOCK1_LOCK_BL_RESET "-" -#define OTP_DATA_PAGE48_LOCK1_LOCK_BL_BITS _u(0x00000030) -#define OTP_DATA_PAGE48_LOCK1_LOCK_BL_MSB _u(5) -#define OTP_DATA_PAGE48_LOCK1_LOCK_BL_LSB _u(4) -#define OTP_DATA_PAGE48_LOCK1_LOCK_BL_ACCESS "RO" -#define OTP_DATA_PAGE48_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE48_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE48_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE48_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE48_LOCK1_LOCK_NS -// Description : Lock state for Non-secure accesses to this page. Thermometer- -// coded, so lock state can be advanced permanently from any state -// to any less-permissive state by programming OTP. Software can -// also advance the lock state temporarily (until next OTP reset) -// using the SW_LOCKx registers. -// -// Note that READ_WRITE and READ_ONLY are equivalent in hardware, -// as the SBPI programming interface is not accessible to Non- -// secure software. However, Secure software may check these bits -// to apply write permissions to a Non-secure OTP programming API. -// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. -// 0x1 -> Page can be read by Non-secure software -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. -// 0x3 -> Page can not be accessed by Non-secure software. -#define OTP_DATA_PAGE48_LOCK1_LOCK_NS_RESET "-" -#define OTP_DATA_PAGE48_LOCK1_LOCK_NS_BITS _u(0x0000000c) -#define OTP_DATA_PAGE48_LOCK1_LOCK_NS_MSB _u(3) -#define OTP_DATA_PAGE48_LOCK1_LOCK_NS_LSB _u(2) -#define OTP_DATA_PAGE48_LOCK1_LOCK_NS_ACCESS "RO" -#define OTP_DATA_PAGE48_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE48_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE48_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE48_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE48_LOCK1_LOCK_S -// Description : Lock state for Secure accesses to this page. Thermometer-coded, -// so lock state can be advanced permanently from any state to any -// less-permissive state by programming OTP. Software can also -// advance the lock state temporarily (until next OTP reset) using -// the SW_LOCKx registers. -// 0x0 -> Page is fully accessible by Secure software. -// 0x1 -> Page can be read by Secure software, but can not be written. -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. -// 0x3 -> Page can not be accessed by Secure software. -#define OTP_DATA_PAGE48_LOCK1_LOCK_S_RESET "-" -#define OTP_DATA_PAGE48_LOCK1_LOCK_S_BITS _u(0x00000003) -#define OTP_DATA_PAGE48_LOCK1_LOCK_S_MSB _u(1) -#define OTP_DATA_PAGE48_LOCK1_LOCK_S_LSB _u(0) -#define OTP_DATA_PAGE48_LOCK1_LOCK_S_ACCESS "RO" -#define OTP_DATA_PAGE48_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE48_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE48_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE48_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) -// ============================================================================= -// Register : OTP_DATA_PAGE49_LOCK0 -// Description : Lock configuration LSBs for page 49 (rows 0xc40 through 0xc7f). -// Locks are stored with 3-way majority vote encoding, so that -// bits can be set independently. -// -// This OTP location is always readable, and is write-protected by -// its own permissions. -#define OTP_DATA_PAGE49_LOCK0_ROW _u(0x00000fe2) -#define OTP_DATA_PAGE49_LOCK0_BITS _u(0x00ffff7f) -#define OTP_DATA_PAGE49_LOCK0_RESET _u(0x00000000) -#define OTP_DATA_PAGE49_LOCK0_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE49_LOCK0_R2 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE49_LOCK0_R2_RESET "-" -#define OTP_DATA_PAGE49_LOCK0_R2_BITS _u(0x00ff0000) -#define OTP_DATA_PAGE49_LOCK0_R2_MSB _u(23) -#define OTP_DATA_PAGE49_LOCK0_R2_LSB _u(16) -#define OTP_DATA_PAGE49_LOCK0_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE49_LOCK0_R1 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE49_LOCK0_R1_RESET "-" -#define OTP_DATA_PAGE49_LOCK0_R1_BITS _u(0x0000ff00) -#define OTP_DATA_PAGE49_LOCK0_R1_MSB _u(15) -#define OTP_DATA_PAGE49_LOCK0_R1_LSB _u(8) -#define OTP_DATA_PAGE49_LOCK0_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE49_LOCK0_NO_KEY_STATE -// Description : State when at least one key is registered for this page and no -// matching key has been entered. -// 0x0 -> read_only -// 0x1 -> inaccessible -#define OTP_DATA_PAGE49_LOCK0_NO_KEY_STATE_RESET "-" -#define OTP_DATA_PAGE49_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) -#define OTP_DATA_PAGE49_LOCK0_NO_KEY_STATE_MSB _u(6) -#define OTP_DATA_PAGE49_LOCK0_NO_KEY_STATE_LSB _u(6) -#define OTP_DATA_PAGE49_LOCK0_NO_KEY_STATE_ACCESS "RO" -#define OTP_DATA_PAGE49_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) -#define OTP_DATA_PAGE49_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE49_LOCK0_KEY_R -// Description : Index 1-6 of a hardware key which must be entered to grant read -// access, or 0 if no such key is required. -#define OTP_DATA_PAGE49_LOCK0_KEY_R_RESET "-" -#define OTP_DATA_PAGE49_LOCK0_KEY_R_BITS _u(0x00000038) -#define OTP_DATA_PAGE49_LOCK0_KEY_R_MSB _u(5) -#define OTP_DATA_PAGE49_LOCK0_KEY_R_LSB _u(3) -#define OTP_DATA_PAGE49_LOCK0_KEY_R_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE49_LOCK0_KEY_W -// Description : Index 1-6 of a hardware key which must be entered to grant -// write access, or 0 if no such key is required. -#define OTP_DATA_PAGE49_LOCK0_KEY_W_RESET "-" -#define OTP_DATA_PAGE49_LOCK0_KEY_W_BITS _u(0x00000007) -#define OTP_DATA_PAGE49_LOCK0_KEY_W_MSB _u(2) -#define OTP_DATA_PAGE49_LOCK0_KEY_W_LSB _u(0) -#define OTP_DATA_PAGE49_LOCK0_KEY_W_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_PAGE49_LOCK1 -// Description : Lock configuration MSBs for page 49 (rows 0xc40 through 0xc7f). -// Locks are stored with 3-way majority vote encoding, so that -// bits can be set independently. -// -// This OTP location is always readable, and is write-protected by -// its own permissions. -#define OTP_DATA_PAGE49_LOCK1_ROW _u(0x00000fe3) -#define OTP_DATA_PAGE49_LOCK1_BITS _u(0x00ffff3f) -#define OTP_DATA_PAGE49_LOCK1_RESET _u(0x00000000) -#define OTP_DATA_PAGE49_LOCK1_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE49_LOCK1_R2 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE49_LOCK1_R2_RESET "-" -#define OTP_DATA_PAGE49_LOCK1_R2_BITS _u(0x00ff0000) -#define OTP_DATA_PAGE49_LOCK1_R2_MSB _u(23) -#define OTP_DATA_PAGE49_LOCK1_R2_LSB _u(16) -#define OTP_DATA_PAGE49_LOCK1_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE49_LOCK1_R1 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE49_LOCK1_R1_RESET "-" -#define OTP_DATA_PAGE49_LOCK1_R1_BITS _u(0x0000ff00) -#define OTP_DATA_PAGE49_LOCK1_R1_MSB _u(15) -#define OTP_DATA_PAGE49_LOCK1_R1_LSB _u(8) -#define OTP_DATA_PAGE49_LOCK1_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE49_LOCK1_LOCK_BL -// Description : Dummy lock bits reserved for bootloaders (including the RP2350 -// USB bootloader) to store their own OTP access permissions. No -// hardware effect, and no corresponding SW_LOCKx registers. -// 0x0 -> Bootloader permits user reads and writes to this page -// 0x1 -> Bootloader permits user reads of this page -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE -// 0x3 -> Bootloader does not permit user access to this page -#define OTP_DATA_PAGE49_LOCK1_LOCK_BL_RESET "-" -#define OTP_DATA_PAGE49_LOCK1_LOCK_BL_BITS _u(0x00000030) -#define OTP_DATA_PAGE49_LOCK1_LOCK_BL_MSB _u(5) -#define OTP_DATA_PAGE49_LOCK1_LOCK_BL_LSB _u(4) -#define OTP_DATA_PAGE49_LOCK1_LOCK_BL_ACCESS "RO" -#define OTP_DATA_PAGE49_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE49_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE49_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE49_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE49_LOCK1_LOCK_NS -// Description : Lock state for Non-secure accesses to this page. Thermometer- -// coded, so lock state can be advanced permanently from any state -// to any less-permissive state by programming OTP. Software can -// also advance the lock state temporarily (until next OTP reset) -// using the SW_LOCKx registers. -// -// Note that READ_WRITE and READ_ONLY are equivalent in hardware, -// as the SBPI programming interface is not accessible to Non- -// secure software. However, Secure software may check these bits -// to apply write permissions to a Non-secure OTP programming API. -// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. -// 0x1 -> Page can be read by Non-secure software -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. -// 0x3 -> Page can not be accessed by Non-secure software. -#define OTP_DATA_PAGE49_LOCK1_LOCK_NS_RESET "-" -#define OTP_DATA_PAGE49_LOCK1_LOCK_NS_BITS _u(0x0000000c) -#define OTP_DATA_PAGE49_LOCK1_LOCK_NS_MSB _u(3) -#define OTP_DATA_PAGE49_LOCK1_LOCK_NS_LSB _u(2) -#define OTP_DATA_PAGE49_LOCK1_LOCK_NS_ACCESS "RO" -#define OTP_DATA_PAGE49_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE49_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE49_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE49_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE49_LOCK1_LOCK_S -// Description : Lock state for Secure accesses to this page. Thermometer-coded, -// so lock state can be advanced permanently from any state to any -// less-permissive state by programming OTP. Software can also -// advance the lock state temporarily (until next OTP reset) using -// the SW_LOCKx registers. -// 0x0 -> Page is fully accessible by Secure software. -// 0x1 -> Page can be read by Secure software, but can not be written. -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. -// 0x3 -> Page can not be accessed by Secure software. -#define OTP_DATA_PAGE49_LOCK1_LOCK_S_RESET "-" -#define OTP_DATA_PAGE49_LOCK1_LOCK_S_BITS _u(0x00000003) -#define OTP_DATA_PAGE49_LOCK1_LOCK_S_MSB _u(1) -#define OTP_DATA_PAGE49_LOCK1_LOCK_S_LSB _u(0) -#define OTP_DATA_PAGE49_LOCK1_LOCK_S_ACCESS "RO" -#define OTP_DATA_PAGE49_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE49_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE49_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE49_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) -// ============================================================================= -// Register : OTP_DATA_PAGE50_LOCK0 -// Description : Lock configuration LSBs for page 50 (rows 0xc80 through 0xcbf). -// Locks are stored with 3-way majority vote encoding, so that -// bits can be set independently. -// -// This OTP location is always readable, and is write-protected by -// its own permissions. -#define OTP_DATA_PAGE50_LOCK0_ROW _u(0x00000fe4) -#define OTP_DATA_PAGE50_LOCK0_BITS _u(0x00ffff7f) -#define OTP_DATA_PAGE50_LOCK0_RESET _u(0x00000000) -#define OTP_DATA_PAGE50_LOCK0_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE50_LOCK0_R2 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE50_LOCK0_R2_RESET "-" -#define OTP_DATA_PAGE50_LOCK0_R2_BITS _u(0x00ff0000) -#define OTP_DATA_PAGE50_LOCK0_R2_MSB _u(23) -#define OTP_DATA_PAGE50_LOCK0_R2_LSB _u(16) -#define OTP_DATA_PAGE50_LOCK0_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE50_LOCK0_R1 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE50_LOCK0_R1_RESET "-" -#define OTP_DATA_PAGE50_LOCK0_R1_BITS _u(0x0000ff00) -#define OTP_DATA_PAGE50_LOCK0_R1_MSB _u(15) -#define OTP_DATA_PAGE50_LOCK0_R1_LSB _u(8) -#define OTP_DATA_PAGE50_LOCK0_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE50_LOCK0_NO_KEY_STATE -// Description : State when at least one key is registered for this page and no -// matching key has been entered. -// 0x0 -> read_only -// 0x1 -> inaccessible -#define OTP_DATA_PAGE50_LOCK0_NO_KEY_STATE_RESET "-" -#define OTP_DATA_PAGE50_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) -#define OTP_DATA_PAGE50_LOCK0_NO_KEY_STATE_MSB _u(6) -#define OTP_DATA_PAGE50_LOCK0_NO_KEY_STATE_LSB _u(6) -#define OTP_DATA_PAGE50_LOCK0_NO_KEY_STATE_ACCESS "RO" -#define OTP_DATA_PAGE50_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) -#define OTP_DATA_PAGE50_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE50_LOCK0_KEY_R -// Description : Index 1-6 of a hardware key which must be entered to grant read -// access, or 0 if no such key is required. -#define OTP_DATA_PAGE50_LOCK0_KEY_R_RESET "-" -#define OTP_DATA_PAGE50_LOCK0_KEY_R_BITS _u(0x00000038) -#define OTP_DATA_PAGE50_LOCK0_KEY_R_MSB _u(5) -#define OTP_DATA_PAGE50_LOCK0_KEY_R_LSB _u(3) -#define OTP_DATA_PAGE50_LOCK0_KEY_R_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE50_LOCK0_KEY_W -// Description : Index 1-6 of a hardware key which must be entered to grant -// write access, or 0 if no such key is required. -#define OTP_DATA_PAGE50_LOCK0_KEY_W_RESET "-" -#define OTP_DATA_PAGE50_LOCK0_KEY_W_BITS _u(0x00000007) -#define OTP_DATA_PAGE50_LOCK0_KEY_W_MSB _u(2) -#define OTP_DATA_PAGE50_LOCK0_KEY_W_LSB _u(0) -#define OTP_DATA_PAGE50_LOCK0_KEY_W_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_PAGE50_LOCK1 -// Description : Lock configuration MSBs for page 50 (rows 0xc80 through 0xcbf). -// Locks are stored with 3-way majority vote encoding, so that -// bits can be set independently. -// -// This OTP location is always readable, and is write-protected by -// its own permissions. -#define OTP_DATA_PAGE50_LOCK1_ROW _u(0x00000fe5) -#define OTP_DATA_PAGE50_LOCK1_BITS _u(0x00ffff3f) -#define OTP_DATA_PAGE50_LOCK1_RESET _u(0x00000000) -#define OTP_DATA_PAGE50_LOCK1_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE50_LOCK1_R2 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE50_LOCK1_R2_RESET "-" -#define OTP_DATA_PAGE50_LOCK1_R2_BITS _u(0x00ff0000) -#define OTP_DATA_PAGE50_LOCK1_R2_MSB _u(23) -#define OTP_DATA_PAGE50_LOCK1_R2_LSB _u(16) -#define OTP_DATA_PAGE50_LOCK1_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE50_LOCK1_R1 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE50_LOCK1_R1_RESET "-" -#define OTP_DATA_PAGE50_LOCK1_R1_BITS _u(0x0000ff00) -#define OTP_DATA_PAGE50_LOCK1_R1_MSB _u(15) -#define OTP_DATA_PAGE50_LOCK1_R1_LSB _u(8) -#define OTP_DATA_PAGE50_LOCK1_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE50_LOCK1_LOCK_BL -// Description : Dummy lock bits reserved for bootloaders (including the RP2350 -// USB bootloader) to store their own OTP access permissions. No -// hardware effect, and no corresponding SW_LOCKx registers. -// 0x0 -> Bootloader permits user reads and writes to this page -// 0x1 -> Bootloader permits user reads of this page -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE -// 0x3 -> Bootloader does not permit user access to this page -#define OTP_DATA_PAGE50_LOCK1_LOCK_BL_RESET "-" -#define OTP_DATA_PAGE50_LOCK1_LOCK_BL_BITS _u(0x00000030) -#define OTP_DATA_PAGE50_LOCK1_LOCK_BL_MSB _u(5) -#define OTP_DATA_PAGE50_LOCK1_LOCK_BL_LSB _u(4) -#define OTP_DATA_PAGE50_LOCK1_LOCK_BL_ACCESS "RO" -#define OTP_DATA_PAGE50_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE50_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE50_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE50_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE50_LOCK1_LOCK_NS -// Description : Lock state for Non-secure accesses to this page. Thermometer- -// coded, so lock state can be advanced permanently from any state -// to any less-permissive state by programming OTP. Software can -// also advance the lock state temporarily (until next OTP reset) -// using the SW_LOCKx registers. -// -// Note that READ_WRITE and READ_ONLY are equivalent in hardware, -// as the SBPI programming interface is not accessible to Non- -// secure software. However, Secure software may check these bits -// to apply write permissions to a Non-secure OTP programming API. -// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. -// 0x1 -> Page can be read by Non-secure software -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. -// 0x3 -> Page can not be accessed by Non-secure software. -#define OTP_DATA_PAGE50_LOCK1_LOCK_NS_RESET "-" -#define OTP_DATA_PAGE50_LOCK1_LOCK_NS_BITS _u(0x0000000c) -#define OTP_DATA_PAGE50_LOCK1_LOCK_NS_MSB _u(3) -#define OTP_DATA_PAGE50_LOCK1_LOCK_NS_LSB _u(2) -#define OTP_DATA_PAGE50_LOCK1_LOCK_NS_ACCESS "RO" -#define OTP_DATA_PAGE50_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE50_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE50_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE50_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE50_LOCK1_LOCK_S -// Description : Lock state for Secure accesses to this page. Thermometer-coded, -// so lock state can be advanced permanently from any state to any -// less-permissive state by programming OTP. Software can also -// advance the lock state temporarily (until next OTP reset) using -// the SW_LOCKx registers. -// 0x0 -> Page is fully accessible by Secure software. -// 0x1 -> Page can be read by Secure software, but can not be written. -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. -// 0x3 -> Page can not be accessed by Secure software. -#define OTP_DATA_PAGE50_LOCK1_LOCK_S_RESET "-" -#define OTP_DATA_PAGE50_LOCK1_LOCK_S_BITS _u(0x00000003) -#define OTP_DATA_PAGE50_LOCK1_LOCK_S_MSB _u(1) -#define OTP_DATA_PAGE50_LOCK1_LOCK_S_LSB _u(0) -#define OTP_DATA_PAGE50_LOCK1_LOCK_S_ACCESS "RO" -#define OTP_DATA_PAGE50_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE50_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE50_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE50_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) -// ============================================================================= -// Register : OTP_DATA_PAGE51_LOCK0 -// Description : Lock configuration LSBs for page 51 (rows 0xcc0 through 0xcff). -// Locks are stored with 3-way majority vote encoding, so that -// bits can be set independently. -// -// This OTP location is always readable, and is write-protected by -// its own permissions. -#define OTP_DATA_PAGE51_LOCK0_ROW _u(0x00000fe6) -#define OTP_DATA_PAGE51_LOCK0_BITS _u(0x00ffff7f) -#define OTP_DATA_PAGE51_LOCK0_RESET _u(0x00000000) -#define OTP_DATA_PAGE51_LOCK0_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE51_LOCK0_R2 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE51_LOCK0_R2_RESET "-" -#define OTP_DATA_PAGE51_LOCK0_R2_BITS _u(0x00ff0000) -#define OTP_DATA_PAGE51_LOCK0_R2_MSB _u(23) -#define OTP_DATA_PAGE51_LOCK0_R2_LSB _u(16) -#define OTP_DATA_PAGE51_LOCK0_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE51_LOCK0_R1 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE51_LOCK0_R1_RESET "-" -#define OTP_DATA_PAGE51_LOCK0_R1_BITS _u(0x0000ff00) -#define OTP_DATA_PAGE51_LOCK0_R1_MSB _u(15) -#define OTP_DATA_PAGE51_LOCK0_R1_LSB _u(8) -#define OTP_DATA_PAGE51_LOCK0_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE51_LOCK0_NO_KEY_STATE -// Description : State when at least one key is registered for this page and no -// matching key has been entered. -// 0x0 -> read_only -// 0x1 -> inaccessible -#define OTP_DATA_PAGE51_LOCK0_NO_KEY_STATE_RESET "-" -#define OTP_DATA_PAGE51_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) -#define OTP_DATA_PAGE51_LOCK0_NO_KEY_STATE_MSB _u(6) -#define OTP_DATA_PAGE51_LOCK0_NO_KEY_STATE_LSB _u(6) -#define OTP_DATA_PAGE51_LOCK0_NO_KEY_STATE_ACCESS "RO" -#define OTP_DATA_PAGE51_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) -#define OTP_DATA_PAGE51_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE51_LOCK0_KEY_R -// Description : Index 1-6 of a hardware key which must be entered to grant read -// access, or 0 if no such key is required. -#define OTP_DATA_PAGE51_LOCK0_KEY_R_RESET "-" -#define OTP_DATA_PAGE51_LOCK0_KEY_R_BITS _u(0x00000038) -#define OTP_DATA_PAGE51_LOCK0_KEY_R_MSB _u(5) -#define OTP_DATA_PAGE51_LOCK0_KEY_R_LSB _u(3) -#define OTP_DATA_PAGE51_LOCK0_KEY_R_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE51_LOCK0_KEY_W -// Description : Index 1-6 of a hardware key which must be entered to grant -// write access, or 0 if no such key is required. -#define OTP_DATA_PAGE51_LOCK0_KEY_W_RESET "-" -#define OTP_DATA_PAGE51_LOCK0_KEY_W_BITS _u(0x00000007) -#define OTP_DATA_PAGE51_LOCK0_KEY_W_MSB _u(2) -#define OTP_DATA_PAGE51_LOCK0_KEY_W_LSB _u(0) -#define OTP_DATA_PAGE51_LOCK0_KEY_W_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_PAGE51_LOCK1 -// Description : Lock configuration MSBs for page 51 (rows 0xcc0 through 0xcff). -// Locks are stored with 3-way majority vote encoding, so that -// bits can be set independently. -// -// This OTP location is always readable, and is write-protected by -// its own permissions. -#define OTP_DATA_PAGE51_LOCK1_ROW _u(0x00000fe7) -#define OTP_DATA_PAGE51_LOCK1_BITS _u(0x00ffff3f) -#define OTP_DATA_PAGE51_LOCK1_RESET _u(0x00000000) -#define OTP_DATA_PAGE51_LOCK1_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE51_LOCK1_R2 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE51_LOCK1_R2_RESET "-" -#define OTP_DATA_PAGE51_LOCK1_R2_BITS _u(0x00ff0000) -#define OTP_DATA_PAGE51_LOCK1_R2_MSB _u(23) -#define OTP_DATA_PAGE51_LOCK1_R2_LSB _u(16) -#define OTP_DATA_PAGE51_LOCK1_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE51_LOCK1_R1 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE51_LOCK1_R1_RESET "-" -#define OTP_DATA_PAGE51_LOCK1_R1_BITS _u(0x0000ff00) -#define OTP_DATA_PAGE51_LOCK1_R1_MSB _u(15) -#define OTP_DATA_PAGE51_LOCK1_R1_LSB _u(8) -#define OTP_DATA_PAGE51_LOCK1_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE51_LOCK1_LOCK_BL -// Description : Dummy lock bits reserved for bootloaders (including the RP2350 -// USB bootloader) to store their own OTP access permissions. No -// hardware effect, and no corresponding SW_LOCKx registers. -// 0x0 -> Bootloader permits user reads and writes to this page -// 0x1 -> Bootloader permits user reads of this page -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE -// 0x3 -> Bootloader does not permit user access to this page -#define OTP_DATA_PAGE51_LOCK1_LOCK_BL_RESET "-" -#define OTP_DATA_PAGE51_LOCK1_LOCK_BL_BITS _u(0x00000030) -#define OTP_DATA_PAGE51_LOCK1_LOCK_BL_MSB _u(5) -#define OTP_DATA_PAGE51_LOCK1_LOCK_BL_LSB _u(4) -#define OTP_DATA_PAGE51_LOCK1_LOCK_BL_ACCESS "RO" -#define OTP_DATA_PAGE51_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE51_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE51_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE51_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE51_LOCK1_LOCK_NS -// Description : Lock state for Non-secure accesses to this page. Thermometer- -// coded, so lock state can be advanced permanently from any state -// to any less-permissive state by programming OTP. Software can -// also advance the lock state temporarily (until next OTP reset) -// using the SW_LOCKx registers. -// -// Note that READ_WRITE and READ_ONLY are equivalent in hardware, -// as the SBPI programming interface is not accessible to Non- -// secure software. However, Secure software may check these bits -// to apply write permissions to a Non-secure OTP programming API. -// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. -// 0x1 -> Page can be read by Non-secure software -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. -// 0x3 -> Page can not be accessed by Non-secure software. -#define OTP_DATA_PAGE51_LOCK1_LOCK_NS_RESET "-" -#define OTP_DATA_PAGE51_LOCK1_LOCK_NS_BITS _u(0x0000000c) -#define OTP_DATA_PAGE51_LOCK1_LOCK_NS_MSB _u(3) -#define OTP_DATA_PAGE51_LOCK1_LOCK_NS_LSB _u(2) -#define OTP_DATA_PAGE51_LOCK1_LOCK_NS_ACCESS "RO" -#define OTP_DATA_PAGE51_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE51_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE51_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE51_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE51_LOCK1_LOCK_S -// Description : Lock state for Secure accesses to this page. Thermometer-coded, -// so lock state can be advanced permanently from any state to any -// less-permissive state by programming OTP. Software can also -// advance the lock state temporarily (until next OTP reset) using -// the SW_LOCKx registers. -// 0x0 -> Page is fully accessible by Secure software. -// 0x1 -> Page can be read by Secure software, but can not be written. -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. -// 0x3 -> Page can not be accessed by Secure software. -#define OTP_DATA_PAGE51_LOCK1_LOCK_S_RESET "-" -#define OTP_DATA_PAGE51_LOCK1_LOCK_S_BITS _u(0x00000003) -#define OTP_DATA_PAGE51_LOCK1_LOCK_S_MSB _u(1) -#define OTP_DATA_PAGE51_LOCK1_LOCK_S_LSB _u(0) -#define OTP_DATA_PAGE51_LOCK1_LOCK_S_ACCESS "RO" -#define OTP_DATA_PAGE51_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE51_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE51_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE51_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) -// ============================================================================= -// Register : OTP_DATA_PAGE52_LOCK0 -// Description : Lock configuration LSBs for page 52 (rows 0xd00 through 0xd3f). -// Locks are stored with 3-way majority vote encoding, so that -// bits can be set independently. -// -// This OTP location is always readable, and is write-protected by -// its own permissions. -#define OTP_DATA_PAGE52_LOCK0_ROW _u(0x00000fe8) -#define OTP_DATA_PAGE52_LOCK0_BITS _u(0x00ffff7f) -#define OTP_DATA_PAGE52_LOCK0_RESET _u(0x00000000) -#define OTP_DATA_PAGE52_LOCK0_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE52_LOCK0_R2 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE52_LOCK0_R2_RESET "-" -#define OTP_DATA_PAGE52_LOCK0_R2_BITS _u(0x00ff0000) -#define OTP_DATA_PAGE52_LOCK0_R2_MSB _u(23) -#define OTP_DATA_PAGE52_LOCK0_R2_LSB _u(16) -#define OTP_DATA_PAGE52_LOCK0_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE52_LOCK0_R1 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE52_LOCK0_R1_RESET "-" -#define OTP_DATA_PAGE52_LOCK0_R1_BITS _u(0x0000ff00) -#define OTP_DATA_PAGE52_LOCK0_R1_MSB _u(15) -#define OTP_DATA_PAGE52_LOCK0_R1_LSB _u(8) -#define OTP_DATA_PAGE52_LOCK0_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE52_LOCK0_NO_KEY_STATE -// Description : State when at least one key is registered for this page and no -// matching key has been entered. -// 0x0 -> read_only -// 0x1 -> inaccessible -#define OTP_DATA_PAGE52_LOCK0_NO_KEY_STATE_RESET "-" -#define OTP_DATA_PAGE52_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) -#define OTP_DATA_PAGE52_LOCK0_NO_KEY_STATE_MSB _u(6) -#define OTP_DATA_PAGE52_LOCK0_NO_KEY_STATE_LSB _u(6) -#define OTP_DATA_PAGE52_LOCK0_NO_KEY_STATE_ACCESS "RO" -#define OTP_DATA_PAGE52_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) -#define OTP_DATA_PAGE52_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE52_LOCK0_KEY_R -// Description : Index 1-6 of a hardware key which must be entered to grant read -// access, or 0 if no such key is required. -#define OTP_DATA_PAGE52_LOCK0_KEY_R_RESET "-" -#define OTP_DATA_PAGE52_LOCK0_KEY_R_BITS _u(0x00000038) -#define OTP_DATA_PAGE52_LOCK0_KEY_R_MSB _u(5) -#define OTP_DATA_PAGE52_LOCK0_KEY_R_LSB _u(3) -#define OTP_DATA_PAGE52_LOCK0_KEY_R_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE52_LOCK0_KEY_W -// Description : Index 1-6 of a hardware key which must be entered to grant -// write access, or 0 if no such key is required. -#define OTP_DATA_PAGE52_LOCK0_KEY_W_RESET "-" -#define OTP_DATA_PAGE52_LOCK0_KEY_W_BITS _u(0x00000007) -#define OTP_DATA_PAGE52_LOCK0_KEY_W_MSB _u(2) -#define OTP_DATA_PAGE52_LOCK0_KEY_W_LSB _u(0) -#define OTP_DATA_PAGE52_LOCK0_KEY_W_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_PAGE52_LOCK1 -// Description : Lock configuration MSBs for page 52 (rows 0xd00 through 0xd3f). -// Locks are stored with 3-way majority vote encoding, so that -// bits can be set independently. -// -// This OTP location is always readable, and is write-protected by -// its own permissions. -#define OTP_DATA_PAGE52_LOCK1_ROW _u(0x00000fe9) -#define OTP_DATA_PAGE52_LOCK1_BITS _u(0x00ffff3f) -#define OTP_DATA_PAGE52_LOCK1_RESET _u(0x00000000) -#define OTP_DATA_PAGE52_LOCK1_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE52_LOCK1_R2 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE52_LOCK1_R2_RESET "-" -#define OTP_DATA_PAGE52_LOCK1_R2_BITS _u(0x00ff0000) -#define OTP_DATA_PAGE52_LOCK1_R2_MSB _u(23) -#define OTP_DATA_PAGE52_LOCK1_R2_LSB _u(16) -#define OTP_DATA_PAGE52_LOCK1_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE52_LOCK1_R1 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE52_LOCK1_R1_RESET "-" -#define OTP_DATA_PAGE52_LOCK1_R1_BITS _u(0x0000ff00) -#define OTP_DATA_PAGE52_LOCK1_R1_MSB _u(15) -#define OTP_DATA_PAGE52_LOCK1_R1_LSB _u(8) -#define OTP_DATA_PAGE52_LOCK1_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE52_LOCK1_LOCK_BL -// Description : Dummy lock bits reserved for bootloaders (including the RP2350 -// USB bootloader) to store their own OTP access permissions. No -// hardware effect, and no corresponding SW_LOCKx registers. -// 0x0 -> Bootloader permits user reads and writes to this page -// 0x1 -> Bootloader permits user reads of this page -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE -// 0x3 -> Bootloader does not permit user access to this page -#define OTP_DATA_PAGE52_LOCK1_LOCK_BL_RESET "-" -#define OTP_DATA_PAGE52_LOCK1_LOCK_BL_BITS _u(0x00000030) -#define OTP_DATA_PAGE52_LOCK1_LOCK_BL_MSB _u(5) -#define OTP_DATA_PAGE52_LOCK1_LOCK_BL_LSB _u(4) -#define OTP_DATA_PAGE52_LOCK1_LOCK_BL_ACCESS "RO" -#define OTP_DATA_PAGE52_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE52_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE52_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE52_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE52_LOCK1_LOCK_NS -// Description : Lock state for Non-secure accesses to this page. Thermometer- -// coded, so lock state can be advanced permanently from any state -// to any less-permissive state by programming OTP. Software can -// also advance the lock state temporarily (until next OTP reset) -// using the SW_LOCKx registers. -// -// Note that READ_WRITE and READ_ONLY are equivalent in hardware, -// as the SBPI programming interface is not accessible to Non- -// secure software. However, Secure software may check these bits -// to apply write permissions to a Non-secure OTP programming API. -// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. -// 0x1 -> Page can be read by Non-secure software -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. -// 0x3 -> Page can not be accessed by Non-secure software. -#define OTP_DATA_PAGE52_LOCK1_LOCK_NS_RESET "-" -#define OTP_DATA_PAGE52_LOCK1_LOCK_NS_BITS _u(0x0000000c) -#define OTP_DATA_PAGE52_LOCK1_LOCK_NS_MSB _u(3) -#define OTP_DATA_PAGE52_LOCK1_LOCK_NS_LSB _u(2) -#define OTP_DATA_PAGE52_LOCK1_LOCK_NS_ACCESS "RO" -#define OTP_DATA_PAGE52_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE52_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE52_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE52_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE52_LOCK1_LOCK_S -// Description : Lock state for Secure accesses to this page. Thermometer-coded, -// so lock state can be advanced permanently from any state to any -// less-permissive state by programming OTP. Software can also -// advance the lock state temporarily (until next OTP reset) using -// the SW_LOCKx registers. -// 0x0 -> Page is fully accessible by Secure software. -// 0x1 -> Page can be read by Secure software, but can not be written. -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. -// 0x3 -> Page can not be accessed by Secure software. -#define OTP_DATA_PAGE52_LOCK1_LOCK_S_RESET "-" -#define OTP_DATA_PAGE52_LOCK1_LOCK_S_BITS _u(0x00000003) -#define OTP_DATA_PAGE52_LOCK1_LOCK_S_MSB _u(1) -#define OTP_DATA_PAGE52_LOCK1_LOCK_S_LSB _u(0) -#define OTP_DATA_PAGE52_LOCK1_LOCK_S_ACCESS "RO" -#define OTP_DATA_PAGE52_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE52_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE52_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE52_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) -// ============================================================================= -// Register : OTP_DATA_PAGE53_LOCK0 -// Description : Lock configuration LSBs for page 53 (rows 0xd40 through 0xd7f). -// Locks are stored with 3-way majority vote encoding, so that -// bits can be set independently. -// -// This OTP location is always readable, and is write-protected by -// its own permissions. -#define OTP_DATA_PAGE53_LOCK0_ROW _u(0x00000fea) -#define OTP_DATA_PAGE53_LOCK0_BITS _u(0x00ffff7f) -#define OTP_DATA_PAGE53_LOCK0_RESET _u(0x00000000) -#define OTP_DATA_PAGE53_LOCK0_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE53_LOCK0_R2 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE53_LOCK0_R2_RESET "-" -#define OTP_DATA_PAGE53_LOCK0_R2_BITS _u(0x00ff0000) -#define OTP_DATA_PAGE53_LOCK0_R2_MSB _u(23) -#define OTP_DATA_PAGE53_LOCK0_R2_LSB _u(16) -#define OTP_DATA_PAGE53_LOCK0_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE53_LOCK0_R1 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE53_LOCK0_R1_RESET "-" -#define OTP_DATA_PAGE53_LOCK0_R1_BITS _u(0x0000ff00) -#define OTP_DATA_PAGE53_LOCK0_R1_MSB _u(15) -#define OTP_DATA_PAGE53_LOCK0_R1_LSB _u(8) -#define OTP_DATA_PAGE53_LOCK0_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE53_LOCK0_NO_KEY_STATE -// Description : State when at least one key is registered for this page and no -// matching key has been entered. -// 0x0 -> read_only -// 0x1 -> inaccessible -#define OTP_DATA_PAGE53_LOCK0_NO_KEY_STATE_RESET "-" -#define OTP_DATA_PAGE53_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) -#define OTP_DATA_PAGE53_LOCK0_NO_KEY_STATE_MSB _u(6) -#define OTP_DATA_PAGE53_LOCK0_NO_KEY_STATE_LSB _u(6) -#define OTP_DATA_PAGE53_LOCK0_NO_KEY_STATE_ACCESS "RO" -#define OTP_DATA_PAGE53_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) -#define OTP_DATA_PAGE53_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE53_LOCK0_KEY_R -// Description : Index 1-6 of a hardware key which must be entered to grant read -// access, or 0 if no such key is required. -#define OTP_DATA_PAGE53_LOCK0_KEY_R_RESET "-" -#define OTP_DATA_PAGE53_LOCK0_KEY_R_BITS _u(0x00000038) -#define OTP_DATA_PAGE53_LOCK0_KEY_R_MSB _u(5) -#define OTP_DATA_PAGE53_LOCK0_KEY_R_LSB _u(3) -#define OTP_DATA_PAGE53_LOCK0_KEY_R_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE53_LOCK0_KEY_W -// Description : Index 1-6 of a hardware key which must be entered to grant -// write access, or 0 if no such key is required. -#define OTP_DATA_PAGE53_LOCK0_KEY_W_RESET "-" -#define OTP_DATA_PAGE53_LOCK0_KEY_W_BITS _u(0x00000007) -#define OTP_DATA_PAGE53_LOCK0_KEY_W_MSB _u(2) -#define OTP_DATA_PAGE53_LOCK0_KEY_W_LSB _u(0) -#define OTP_DATA_PAGE53_LOCK0_KEY_W_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_PAGE53_LOCK1 -// Description : Lock configuration MSBs for page 53 (rows 0xd40 through 0xd7f). -// Locks are stored with 3-way majority vote encoding, so that -// bits can be set independently. -// -// This OTP location is always readable, and is write-protected by -// its own permissions. -#define OTP_DATA_PAGE53_LOCK1_ROW _u(0x00000feb) -#define OTP_DATA_PAGE53_LOCK1_BITS _u(0x00ffff3f) -#define OTP_DATA_PAGE53_LOCK1_RESET _u(0x00000000) -#define OTP_DATA_PAGE53_LOCK1_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE53_LOCK1_R2 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE53_LOCK1_R2_RESET "-" -#define OTP_DATA_PAGE53_LOCK1_R2_BITS _u(0x00ff0000) -#define OTP_DATA_PAGE53_LOCK1_R2_MSB _u(23) -#define OTP_DATA_PAGE53_LOCK1_R2_LSB _u(16) -#define OTP_DATA_PAGE53_LOCK1_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE53_LOCK1_R1 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE53_LOCK1_R1_RESET "-" -#define OTP_DATA_PAGE53_LOCK1_R1_BITS _u(0x0000ff00) -#define OTP_DATA_PAGE53_LOCK1_R1_MSB _u(15) -#define OTP_DATA_PAGE53_LOCK1_R1_LSB _u(8) -#define OTP_DATA_PAGE53_LOCK1_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE53_LOCK1_LOCK_BL -// Description : Dummy lock bits reserved for bootloaders (including the RP2350 -// USB bootloader) to store their own OTP access permissions. No -// hardware effect, and no corresponding SW_LOCKx registers. -// 0x0 -> Bootloader permits user reads and writes to this page -// 0x1 -> Bootloader permits user reads of this page -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE -// 0x3 -> Bootloader does not permit user access to this page -#define OTP_DATA_PAGE53_LOCK1_LOCK_BL_RESET "-" -#define OTP_DATA_PAGE53_LOCK1_LOCK_BL_BITS _u(0x00000030) -#define OTP_DATA_PAGE53_LOCK1_LOCK_BL_MSB _u(5) -#define OTP_DATA_PAGE53_LOCK1_LOCK_BL_LSB _u(4) -#define OTP_DATA_PAGE53_LOCK1_LOCK_BL_ACCESS "RO" -#define OTP_DATA_PAGE53_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE53_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE53_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE53_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE53_LOCK1_LOCK_NS -// Description : Lock state for Non-secure accesses to this page. Thermometer- -// coded, so lock state can be advanced permanently from any state -// to any less-permissive state by programming OTP. Software can -// also advance the lock state temporarily (until next OTP reset) -// using the SW_LOCKx registers. -// -// Note that READ_WRITE and READ_ONLY are equivalent in hardware, -// as the SBPI programming interface is not accessible to Non- -// secure software. However, Secure software may check these bits -// to apply write permissions to a Non-secure OTP programming API. -// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. -// 0x1 -> Page can be read by Non-secure software -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. -// 0x3 -> Page can not be accessed by Non-secure software. -#define OTP_DATA_PAGE53_LOCK1_LOCK_NS_RESET "-" -#define OTP_DATA_PAGE53_LOCK1_LOCK_NS_BITS _u(0x0000000c) -#define OTP_DATA_PAGE53_LOCK1_LOCK_NS_MSB _u(3) -#define OTP_DATA_PAGE53_LOCK1_LOCK_NS_LSB _u(2) -#define OTP_DATA_PAGE53_LOCK1_LOCK_NS_ACCESS "RO" -#define OTP_DATA_PAGE53_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE53_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE53_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE53_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE53_LOCK1_LOCK_S -// Description : Lock state for Secure accesses to this page. Thermometer-coded, -// so lock state can be advanced permanently from any state to any -// less-permissive state by programming OTP. Software can also -// advance the lock state temporarily (until next OTP reset) using -// the SW_LOCKx registers. -// 0x0 -> Page is fully accessible by Secure software. -// 0x1 -> Page can be read by Secure software, but can not be written. -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. -// 0x3 -> Page can not be accessed by Secure software. -#define OTP_DATA_PAGE53_LOCK1_LOCK_S_RESET "-" -#define OTP_DATA_PAGE53_LOCK1_LOCK_S_BITS _u(0x00000003) -#define OTP_DATA_PAGE53_LOCK1_LOCK_S_MSB _u(1) -#define OTP_DATA_PAGE53_LOCK1_LOCK_S_LSB _u(0) -#define OTP_DATA_PAGE53_LOCK1_LOCK_S_ACCESS "RO" -#define OTP_DATA_PAGE53_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE53_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE53_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE53_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) -// ============================================================================= -// Register : OTP_DATA_PAGE54_LOCK0 -// Description : Lock configuration LSBs for page 54 (rows 0xd80 through 0xdbf). -// Locks are stored with 3-way majority vote encoding, so that -// bits can be set independently. -// -// This OTP location is always readable, and is write-protected by -// its own permissions. -#define OTP_DATA_PAGE54_LOCK0_ROW _u(0x00000fec) -#define OTP_DATA_PAGE54_LOCK0_BITS _u(0x00ffff7f) -#define OTP_DATA_PAGE54_LOCK0_RESET _u(0x00000000) -#define OTP_DATA_PAGE54_LOCK0_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE54_LOCK0_R2 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE54_LOCK0_R2_RESET "-" -#define OTP_DATA_PAGE54_LOCK0_R2_BITS _u(0x00ff0000) -#define OTP_DATA_PAGE54_LOCK0_R2_MSB _u(23) -#define OTP_DATA_PAGE54_LOCK0_R2_LSB _u(16) -#define OTP_DATA_PAGE54_LOCK0_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE54_LOCK0_R1 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE54_LOCK0_R1_RESET "-" -#define OTP_DATA_PAGE54_LOCK0_R1_BITS _u(0x0000ff00) -#define OTP_DATA_PAGE54_LOCK0_R1_MSB _u(15) -#define OTP_DATA_PAGE54_LOCK0_R1_LSB _u(8) -#define OTP_DATA_PAGE54_LOCK0_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE54_LOCK0_NO_KEY_STATE -// Description : State when at least one key is registered for this page and no -// matching key has been entered. -// 0x0 -> read_only -// 0x1 -> inaccessible -#define OTP_DATA_PAGE54_LOCK0_NO_KEY_STATE_RESET "-" -#define OTP_DATA_PAGE54_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) -#define OTP_DATA_PAGE54_LOCK0_NO_KEY_STATE_MSB _u(6) -#define OTP_DATA_PAGE54_LOCK0_NO_KEY_STATE_LSB _u(6) -#define OTP_DATA_PAGE54_LOCK0_NO_KEY_STATE_ACCESS "RO" -#define OTP_DATA_PAGE54_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) -#define OTP_DATA_PAGE54_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE54_LOCK0_KEY_R -// Description : Index 1-6 of a hardware key which must be entered to grant read -// access, or 0 if no such key is required. -#define OTP_DATA_PAGE54_LOCK0_KEY_R_RESET "-" -#define OTP_DATA_PAGE54_LOCK0_KEY_R_BITS _u(0x00000038) -#define OTP_DATA_PAGE54_LOCK0_KEY_R_MSB _u(5) -#define OTP_DATA_PAGE54_LOCK0_KEY_R_LSB _u(3) -#define OTP_DATA_PAGE54_LOCK0_KEY_R_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE54_LOCK0_KEY_W -// Description : Index 1-6 of a hardware key which must be entered to grant -// write access, or 0 if no such key is required. -#define OTP_DATA_PAGE54_LOCK0_KEY_W_RESET "-" -#define OTP_DATA_PAGE54_LOCK0_KEY_W_BITS _u(0x00000007) -#define OTP_DATA_PAGE54_LOCK0_KEY_W_MSB _u(2) -#define OTP_DATA_PAGE54_LOCK0_KEY_W_LSB _u(0) -#define OTP_DATA_PAGE54_LOCK0_KEY_W_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_PAGE54_LOCK1 -// Description : Lock configuration MSBs for page 54 (rows 0xd80 through 0xdbf). -// Locks are stored with 3-way majority vote encoding, so that -// bits can be set independently. -// -// This OTP location is always readable, and is write-protected by -// its own permissions. -#define OTP_DATA_PAGE54_LOCK1_ROW _u(0x00000fed) -#define OTP_DATA_PAGE54_LOCK1_BITS _u(0x00ffff3f) -#define OTP_DATA_PAGE54_LOCK1_RESET _u(0x00000000) -#define OTP_DATA_PAGE54_LOCK1_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE54_LOCK1_R2 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE54_LOCK1_R2_RESET "-" -#define OTP_DATA_PAGE54_LOCK1_R2_BITS _u(0x00ff0000) -#define OTP_DATA_PAGE54_LOCK1_R2_MSB _u(23) -#define OTP_DATA_PAGE54_LOCK1_R2_LSB _u(16) -#define OTP_DATA_PAGE54_LOCK1_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE54_LOCK1_R1 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE54_LOCK1_R1_RESET "-" -#define OTP_DATA_PAGE54_LOCK1_R1_BITS _u(0x0000ff00) -#define OTP_DATA_PAGE54_LOCK1_R1_MSB _u(15) -#define OTP_DATA_PAGE54_LOCK1_R1_LSB _u(8) -#define OTP_DATA_PAGE54_LOCK1_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE54_LOCK1_LOCK_BL -// Description : Dummy lock bits reserved for bootloaders (including the RP2350 -// USB bootloader) to store their own OTP access permissions. No -// hardware effect, and no corresponding SW_LOCKx registers. -// 0x0 -> Bootloader permits user reads and writes to this page -// 0x1 -> Bootloader permits user reads of this page -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE -// 0x3 -> Bootloader does not permit user access to this page -#define OTP_DATA_PAGE54_LOCK1_LOCK_BL_RESET "-" -#define OTP_DATA_PAGE54_LOCK1_LOCK_BL_BITS _u(0x00000030) -#define OTP_DATA_PAGE54_LOCK1_LOCK_BL_MSB _u(5) -#define OTP_DATA_PAGE54_LOCK1_LOCK_BL_LSB _u(4) -#define OTP_DATA_PAGE54_LOCK1_LOCK_BL_ACCESS "RO" -#define OTP_DATA_PAGE54_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE54_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE54_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE54_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE54_LOCK1_LOCK_NS -// Description : Lock state for Non-secure accesses to this page. Thermometer- -// coded, so lock state can be advanced permanently from any state -// to any less-permissive state by programming OTP. Software can -// also advance the lock state temporarily (until next OTP reset) -// using the SW_LOCKx registers. -// -// Note that READ_WRITE and READ_ONLY are equivalent in hardware, -// as the SBPI programming interface is not accessible to Non- -// secure software. However, Secure software may check these bits -// to apply write permissions to a Non-secure OTP programming API. -// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. -// 0x1 -> Page can be read by Non-secure software -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. -// 0x3 -> Page can not be accessed by Non-secure software. -#define OTP_DATA_PAGE54_LOCK1_LOCK_NS_RESET "-" -#define OTP_DATA_PAGE54_LOCK1_LOCK_NS_BITS _u(0x0000000c) -#define OTP_DATA_PAGE54_LOCK1_LOCK_NS_MSB _u(3) -#define OTP_DATA_PAGE54_LOCK1_LOCK_NS_LSB _u(2) -#define OTP_DATA_PAGE54_LOCK1_LOCK_NS_ACCESS "RO" -#define OTP_DATA_PAGE54_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE54_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE54_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE54_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE54_LOCK1_LOCK_S -// Description : Lock state for Secure accesses to this page. Thermometer-coded, -// so lock state can be advanced permanently from any state to any -// less-permissive state by programming OTP. Software can also -// advance the lock state temporarily (until next OTP reset) using -// the SW_LOCKx registers. -// 0x0 -> Page is fully accessible by Secure software. -// 0x1 -> Page can be read by Secure software, but can not be written. -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. -// 0x3 -> Page can not be accessed by Secure software. -#define OTP_DATA_PAGE54_LOCK1_LOCK_S_RESET "-" -#define OTP_DATA_PAGE54_LOCK1_LOCK_S_BITS _u(0x00000003) -#define OTP_DATA_PAGE54_LOCK1_LOCK_S_MSB _u(1) -#define OTP_DATA_PAGE54_LOCK1_LOCK_S_LSB _u(0) -#define OTP_DATA_PAGE54_LOCK1_LOCK_S_ACCESS "RO" -#define OTP_DATA_PAGE54_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE54_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE54_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE54_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) -// ============================================================================= -// Register : OTP_DATA_PAGE55_LOCK0 -// Description : Lock configuration LSBs for page 55 (rows 0xdc0 through 0xdff). -// Locks are stored with 3-way majority vote encoding, so that -// bits can be set independently. -// -// This OTP location is always readable, and is write-protected by -// its own permissions. -#define OTP_DATA_PAGE55_LOCK0_ROW _u(0x00000fee) -#define OTP_DATA_PAGE55_LOCK0_BITS _u(0x00ffff7f) -#define OTP_DATA_PAGE55_LOCK0_RESET _u(0x00000000) -#define OTP_DATA_PAGE55_LOCK0_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE55_LOCK0_R2 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE55_LOCK0_R2_RESET "-" -#define OTP_DATA_PAGE55_LOCK0_R2_BITS _u(0x00ff0000) -#define OTP_DATA_PAGE55_LOCK0_R2_MSB _u(23) -#define OTP_DATA_PAGE55_LOCK0_R2_LSB _u(16) -#define OTP_DATA_PAGE55_LOCK0_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE55_LOCK0_R1 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE55_LOCK0_R1_RESET "-" -#define OTP_DATA_PAGE55_LOCK0_R1_BITS _u(0x0000ff00) -#define OTP_DATA_PAGE55_LOCK0_R1_MSB _u(15) -#define OTP_DATA_PAGE55_LOCK0_R1_LSB _u(8) -#define OTP_DATA_PAGE55_LOCK0_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE55_LOCK0_NO_KEY_STATE -// Description : State when at least one key is registered for this page and no -// matching key has been entered. -// 0x0 -> read_only -// 0x1 -> inaccessible -#define OTP_DATA_PAGE55_LOCK0_NO_KEY_STATE_RESET "-" -#define OTP_DATA_PAGE55_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) -#define OTP_DATA_PAGE55_LOCK0_NO_KEY_STATE_MSB _u(6) -#define OTP_DATA_PAGE55_LOCK0_NO_KEY_STATE_LSB _u(6) -#define OTP_DATA_PAGE55_LOCK0_NO_KEY_STATE_ACCESS "RO" -#define OTP_DATA_PAGE55_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) -#define OTP_DATA_PAGE55_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE55_LOCK0_KEY_R -// Description : Index 1-6 of a hardware key which must be entered to grant read -// access, or 0 if no such key is required. -#define OTP_DATA_PAGE55_LOCK0_KEY_R_RESET "-" -#define OTP_DATA_PAGE55_LOCK0_KEY_R_BITS _u(0x00000038) -#define OTP_DATA_PAGE55_LOCK0_KEY_R_MSB _u(5) -#define OTP_DATA_PAGE55_LOCK0_KEY_R_LSB _u(3) -#define OTP_DATA_PAGE55_LOCK0_KEY_R_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE55_LOCK0_KEY_W -// Description : Index 1-6 of a hardware key which must be entered to grant -// write access, or 0 if no such key is required. -#define OTP_DATA_PAGE55_LOCK0_KEY_W_RESET "-" -#define OTP_DATA_PAGE55_LOCK0_KEY_W_BITS _u(0x00000007) -#define OTP_DATA_PAGE55_LOCK0_KEY_W_MSB _u(2) -#define OTP_DATA_PAGE55_LOCK0_KEY_W_LSB _u(0) -#define OTP_DATA_PAGE55_LOCK0_KEY_W_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_PAGE55_LOCK1 -// Description : Lock configuration MSBs for page 55 (rows 0xdc0 through 0xdff). -// Locks are stored with 3-way majority vote encoding, so that -// bits can be set independently. -// -// This OTP location is always readable, and is write-protected by -// its own permissions. -#define OTP_DATA_PAGE55_LOCK1_ROW _u(0x00000fef) -#define OTP_DATA_PAGE55_LOCK1_BITS _u(0x00ffff3f) -#define OTP_DATA_PAGE55_LOCK1_RESET _u(0x00000000) -#define OTP_DATA_PAGE55_LOCK1_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE55_LOCK1_R2 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE55_LOCK1_R2_RESET "-" -#define OTP_DATA_PAGE55_LOCK1_R2_BITS _u(0x00ff0000) -#define OTP_DATA_PAGE55_LOCK1_R2_MSB _u(23) -#define OTP_DATA_PAGE55_LOCK1_R2_LSB _u(16) -#define OTP_DATA_PAGE55_LOCK1_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE55_LOCK1_R1 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE55_LOCK1_R1_RESET "-" -#define OTP_DATA_PAGE55_LOCK1_R1_BITS _u(0x0000ff00) -#define OTP_DATA_PAGE55_LOCK1_R1_MSB _u(15) -#define OTP_DATA_PAGE55_LOCK1_R1_LSB _u(8) -#define OTP_DATA_PAGE55_LOCK1_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE55_LOCK1_LOCK_BL -// Description : Dummy lock bits reserved for bootloaders (including the RP2350 -// USB bootloader) to store their own OTP access permissions. No -// hardware effect, and no corresponding SW_LOCKx registers. -// 0x0 -> Bootloader permits user reads and writes to this page -// 0x1 -> Bootloader permits user reads of this page -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE -// 0x3 -> Bootloader does not permit user access to this page -#define OTP_DATA_PAGE55_LOCK1_LOCK_BL_RESET "-" -#define OTP_DATA_PAGE55_LOCK1_LOCK_BL_BITS _u(0x00000030) -#define OTP_DATA_PAGE55_LOCK1_LOCK_BL_MSB _u(5) -#define OTP_DATA_PAGE55_LOCK1_LOCK_BL_LSB _u(4) -#define OTP_DATA_PAGE55_LOCK1_LOCK_BL_ACCESS "RO" -#define OTP_DATA_PAGE55_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE55_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE55_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE55_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE55_LOCK1_LOCK_NS -// Description : Lock state for Non-secure accesses to this page. Thermometer- -// coded, so lock state can be advanced permanently from any state -// to any less-permissive state by programming OTP. Software can -// also advance the lock state temporarily (until next OTP reset) -// using the SW_LOCKx registers. -// -// Note that READ_WRITE and READ_ONLY are equivalent in hardware, -// as the SBPI programming interface is not accessible to Non- -// secure software. However, Secure software may check these bits -// to apply write permissions to a Non-secure OTP programming API. -// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. -// 0x1 -> Page can be read by Non-secure software -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. -// 0x3 -> Page can not be accessed by Non-secure software. -#define OTP_DATA_PAGE55_LOCK1_LOCK_NS_RESET "-" -#define OTP_DATA_PAGE55_LOCK1_LOCK_NS_BITS _u(0x0000000c) -#define OTP_DATA_PAGE55_LOCK1_LOCK_NS_MSB _u(3) -#define OTP_DATA_PAGE55_LOCK1_LOCK_NS_LSB _u(2) -#define OTP_DATA_PAGE55_LOCK1_LOCK_NS_ACCESS "RO" -#define OTP_DATA_PAGE55_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE55_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE55_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE55_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE55_LOCK1_LOCK_S -// Description : Lock state for Secure accesses to this page. Thermometer-coded, -// so lock state can be advanced permanently from any state to any -// less-permissive state by programming OTP. Software can also -// advance the lock state temporarily (until next OTP reset) using -// the SW_LOCKx registers. -// 0x0 -> Page is fully accessible by Secure software. -// 0x1 -> Page can be read by Secure software, but can not be written. -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. -// 0x3 -> Page can not be accessed by Secure software. -#define OTP_DATA_PAGE55_LOCK1_LOCK_S_RESET "-" -#define OTP_DATA_PAGE55_LOCK1_LOCK_S_BITS _u(0x00000003) -#define OTP_DATA_PAGE55_LOCK1_LOCK_S_MSB _u(1) -#define OTP_DATA_PAGE55_LOCK1_LOCK_S_LSB _u(0) -#define OTP_DATA_PAGE55_LOCK1_LOCK_S_ACCESS "RO" -#define OTP_DATA_PAGE55_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE55_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE55_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE55_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) -// ============================================================================= -// Register : OTP_DATA_PAGE56_LOCK0 -// Description : Lock configuration LSBs for page 56 (rows 0xe00 through 0xe3f). -// Locks are stored with 3-way majority vote encoding, so that -// bits can be set independently. -// -// This OTP location is always readable, and is write-protected by -// its own permissions. -#define OTP_DATA_PAGE56_LOCK0_ROW _u(0x00000ff0) -#define OTP_DATA_PAGE56_LOCK0_BITS _u(0x00ffff7f) -#define OTP_DATA_PAGE56_LOCK0_RESET _u(0x00000000) -#define OTP_DATA_PAGE56_LOCK0_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE56_LOCK0_R2 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE56_LOCK0_R2_RESET "-" -#define OTP_DATA_PAGE56_LOCK0_R2_BITS _u(0x00ff0000) -#define OTP_DATA_PAGE56_LOCK0_R2_MSB _u(23) -#define OTP_DATA_PAGE56_LOCK0_R2_LSB _u(16) -#define OTP_DATA_PAGE56_LOCK0_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE56_LOCK0_R1 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE56_LOCK0_R1_RESET "-" -#define OTP_DATA_PAGE56_LOCK0_R1_BITS _u(0x0000ff00) -#define OTP_DATA_PAGE56_LOCK0_R1_MSB _u(15) -#define OTP_DATA_PAGE56_LOCK0_R1_LSB _u(8) -#define OTP_DATA_PAGE56_LOCK0_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE56_LOCK0_NO_KEY_STATE -// Description : State when at least one key is registered for this page and no -// matching key has been entered. -// 0x0 -> read_only -// 0x1 -> inaccessible -#define OTP_DATA_PAGE56_LOCK0_NO_KEY_STATE_RESET "-" -#define OTP_DATA_PAGE56_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) -#define OTP_DATA_PAGE56_LOCK0_NO_KEY_STATE_MSB _u(6) -#define OTP_DATA_PAGE56_LOCK0_NO_KEY_STATE_LSB _u(6) -#define OTP_DATA_PAGE56_LOCK0_NO_KEY_STATE_ACCESS "RO" -#define OTP_DATA_PAGE56_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) -#define OTP_DATA_PAGE56_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE56_LOCK0_KEY_R -// Description : Index 1-6 of a hardware key which must be entered to grant read -// access, or 0 if no such key is required. -#define OTP_DATA_PAGE56_LOCK0_KEY_R_RESET "-" -#define OTP_DATA_PAGE56_LOCK0_KEY_R_BITS _u(0x00000038) -#define OTP_DATA_PAGE56_LOCK0_KEY_R_MSB _u(5) -#define OTP_DATA_PAGE56_LOCK0_KEY_R_LSB _u(3) -#define OTP_DATA_PAGE56_LOCK0_KEY_R_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE56_LOCK0_KEY_W -// Description : Index 1-6 of a hardware key which must be entered to grant -// write access, or 0 if no such key is required. -#define OTP_DATA_PAGE56_LOCK0_KEY_W_RESET "-" -#define OTP_DATA_PAGE56_LOCK0_KEY_W_BITS _u(0x00000007) -#define OTP_DATA_PAGE56_LOCK0_KEY_W_MSB _u(2) -#define OTP_DATA_PAGE56_LOCK0_KEY_W_LSB _u(0) -#define OTP_DATA_PAGE56_LOCK0_KEY_W_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_PAGE56_LOCK1 -// Description : Lock configuration MSBs for page 56 (rows 0xe00 through 0xe3f). -// Locks are stored with 3-way majority vote encoding, so that -// bits can be set independently. -// -// This OTP location is always readable, and is write-protected by -// its own permissions. -#define OTP_DATA_PAGE56_LOCK1_ROW _u(0x00000ff1) -#define OTP_DATA_PAGE56_LOCK1_BITS _u(0x00ffff3f) -#define OTP_DATA_PAGE56_LOCK1_RESET _u(0x00000000) -#define OTP_DATA_PAGE56_LOCK1_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE56_LOCK1_R2 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE56_LOCK1_R2_RESET "-" -#define OTP_DATA_PAGE56_LOCK1_R2_BITS _u(0x00ff0000) -#define OTP_DATA_PAGE56_LOCK1_R2_MSB _u(23) -#define OTP_DATA_PAGE56_LOCK1_R2_LSB _u(16) -#define OTP_DATA_PAGE56_LOCK1_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE56_LOCK1_R1 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE56_LOCK1_R1_RESET "-" -#define OTP_DATA_PAGE56_LOCK1_R1_BITS _u(0x0000ff00) -#define OTP_DATA_PAGE56_LOCK1_R1_MSB _u(15) -#define OTP_DATA_PAGE56_LOCK1_R1_LSB _u(8) -#define OTP_DATA_PAGE56_LOCK1_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE56_LOCK1_LOCK_BL -// Description : Dummy lock bits reserved for bootloaders (including the RP2350 -// USB bootloader) to store their own OTP access permissions. No -// hardware effect, and no corresponding SW_LOCKx registers. -// 0x0 -> Bootloader permits user reads and writes to this page -// 0x1 -> Bootloader permits user reads of this page -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE -// 0x3 -> Bootloader does not permit user access to this page -#define OTP_DATA_PAGE56_LOCK1_LOCK_BL_RESET "-" -#define OTP_DATA_PAGE56_LOCK1_LOCK_BL_BITS _u(0x00000030) -#define OTP_DATA_PAGE56_LOCK1_LOCK_BL_MSB _u(5) -#define OTP_DATA_PAGE56_LOCK1_LOCK_BL_LSB _u(4) -#define OTP_DATA_PAGE56_LOCK1_LOCK_BL_ACCESS "RO" -#define OTP_DATA_PAGE56_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE56_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE56_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE56_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE56_LOCK1_LOCK_NS -// Description : Lock state for Non-secure accesses to this page. Thermometer- -// coded, so lock state can be advanced permanently from any state -// to any less-permissive state by programming OTP. Software can -// also advance the lock state temporarily (until next OTP reset) -// using the SW_LOCKx registers. -// -// Note that READ_WRITE and READ_ONLY are equivalent in hardware, -// as the SBPI programming interface is not accessible to Non- -// secure software. However, Secure software may check these bits -// to apply write permissions to a Non-secure OTP programming API. -// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. -// 0x1 -> Page can be read by Non-secure software -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. -// 0x3 -> Page can not be accessed by Non-secure software. -#define OTP_DATA_PAGE56_LOCK1_LOCK_NS_RESET "-" -#define OTP_DATA_PAGE56_LOCK1_LOCK_NS_BITS _u(0x0000000c) -#define OTP_DATA_PAGE56_LOCK1_LOCK_NS_MSB _u(3) -#define OTP_DATA_PAGE56_LOCK1_LOCK_NS_LSB _u(2) -#define OTP_DATA_PAGE56_LOCK1_LOCK_NS_ACCESS "RO" -#define OTP_DATA_PAGE56_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE56_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE56_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE56_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE56_LOCK1_LOCK_S -// Description : Lock state for Secure accesses to this page. Thermometer-coded, -// so lock state can be advanced permanently from any state to any -// less-permissive state by programming OTP. Software can also -// advance the lock state temporarily (until next OTP reset) using -// the SW_LOCKx registers. -// 0x0 -> Page is fully accessible by Secure software. -// 0x1 -> Page can be read by Secure software, but can not be written. -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. -// 0x3 -> Page can not be accessed by Secure software. -#define OTP_DATA_PAGE56_LOCK1_LOCK_S_RESET "-" -#define OTP_DATA_PAGE56_LOCK1_LOCK_S_BITS _u(0x00000003) -#define OTP_DATA_PAGE56_LOCK1_LOCK_S_MSB _u(1) -#define OTP_DATA_PAGE56_LOCK1_LOCK_S_LSB _u(0) -#define OTP_DATA_PAGE56_LOCK1_LOCK_S_ACCESS "RO" -#define OTP_DATA_PAGE56_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE56_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE56_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE56_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) -// ============================================================================= -// Register : OTP_DATA_PAGE57_LOCK0 -// Description : Lock configuration LSBs for page 57 (rows 0xe40 through 0xe7f). -// Locks are stored with 3-way majority vote encoding, so that -// bits can be set independently. -// -// This OTP location is always readable, and is write-protected by -// its own permissions. -#define OTP_DATA_PAGE57_LOCK0_ROW _u(0x00000ff2) -#define OTP_DATA_PAGE57_LOCK0_BITS _u(0x00ffff7f) -#define OTP_DATA_PAGE57_LOCK0_RESET _u(0x00000000) -#define OTP_DATA_PAGE57_LOCK0_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE57_LOCK0_R2 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE57_LOCK0_R2_RESET "-" -#define OTP_DATA_PAGE57_LOCK0_R2_BITS _u(0x00ff0000) -#define OTP_DATA_PAGE57_LOCK0_R2_MSB _u(23) -#define OTP_DATA_PAGE57_LOCK0_R2_LSB _u(16) -#define OTP_DATA_PAGE57_LOCK0_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE57_LOCK0_R1 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE57_LOCK0_R1_RESET "-" -#define OTP_DATA_PAGE57_LOCK0_R1_BITS _u(0x0000ff00) -#define OTP_DATA_PAGE57_LOCK0_R1_MSB _u(15) -#define OTP_DATA_PAGE57_LOCK0_R1_LSB _u(8) -#define OTP_DATA_PAGE57_LOCK0_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE57_LOCK0_NO_KEY_STATE -// Description : State when at least one key is registered for this page and no -// matching key has been entered. -// 0x0 -> read_only -// 0x1 -> inaccessible -#define OTP_DATA_PAGE57_LOCK0_NO_KEY_STATE_RESET "-" -#define OTP_DATA_PAGE57_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) -#define OTP_DATA_PAGE57_LOCK0_NO_KEY_STATE_MSB _u(6) -#define OTP_DATA_PAGE57_LOCK0_NO_KEY_STATE_LSB _u(6) -#define OTP_DATA_PAGE57_LOCK0_NO_KEY_STATE_ACCESS "RO" -#define OTP_DATA_PAGE57_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) -#define OTP_DATA_PAGE57_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE57_LOCK0_KEY_R -// Description : Index 1-6 of a hardware key which must be entered to grant read -// access, or 0 if no such key is required. -#define OTP_DATA_PAGE57_LOCK0_KEY_R_RESET "-" -#define OTP_DATA_PAGE57_LOCK0_KEY_R_BITS _u(0x00000038) -#define OTP_DATA_PAGE57_LOCK0_KEY_R_MSB _u(5) -#define OTP_DATA_PAGE57_LOCK0_KEY_R_LSB _u(3) -#define OTP_DATA_PAGE57_LOCK0_KEY_R_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE57_LOCK0_KEY_W -// Description : Index 1-6 of a hardware key which must be entered to grant -// write access, or 0 if no such key is required. -#define OTP_DATA_PAGE57_LOCK0_KEY_W_RESET "-" -#define OTP_DATA_PAGE57_LOCK0_KEY_W_BITS _u(0x00000007) -#define OTP_DATA_PAGE57_LOCK0_KEY_W_MSB _u(2) -#define OTP_DATA_PAGE57_LOCK0_KEY_W_LSB _u(0) -#define OTP_DATA_PAGE57_LOCK0_KEY_W_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_PAGE57_LOCK1 -// Description : Lock configuration MSBs for page 57 (rows 0xe40 through 0xe7f). -// Locks are stored with 3-way majority vote encoding, so that -// bits can be set independently. -// -// This OTP location is always readable, and is write-protected by -// its own permissions. -#define OTP_DATA_PAGE57_LOCK1_ROW _u(0x00000ff3) -#define OTP_DATA_PAGE57_LOCK1_BITS _u(0x00ffff3f) -#define OTP_DATA_PAGE57_LOCK1_RESET _u(0x00000000) -#define OTP_DATA_PAGE57_LOCK1_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE57_LOCK1_R2 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE57_LOCK1_R2_RESET "-" -#define OTP_DATA_PAGE57_LOCK1_R2_BITS _u(0x00ff0000) -#define OTP_DATA_PAGE57_LOCK1_R2_MSB _u(23) -#define OTP_DATA_PAGE57_LOCK1_R2_LSB _u(16) -#define OTP_DATA_PAGE57_LOCK1_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE57_LOCK1_R1 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE57_LOCK1_R1_RESET "-" -#define OTP_DATA_PAGE57_LOCK1_R1_BITS _u(0x0000ff00) -#define OTP_DATA_PAGE57_LOCK1_R1_MSB _u(15) -#define OTP_DATA_PAGE57_LOCK1_R1_LSB _u(8) -#define OTP_DATA_PAGE57_LOCK1_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE57_LOCK1_LOCK_BL -// Description : Dummy lock bits reserved for bootloaders (including the RP2350 -// USB bootloader) to store their own OTP access permissions. No -// hardware effect, and no corresponding SW_LOCKx registers. -// 0x0 -> Bootloader permits user reads and writes to this page -// 0x1 -> Bootloader permits user reads of this page -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE -// 0x3 -> Bootloader does not permit user access to this page -#define OTP_DATA_PAGE57_LOCK1_LOCK_BL_RESET "-" -#define OTP_DATA_PAGE57_LOCK1_LOCK_BL_BITS _u(0x00000030) -#define OTP_DATA_PAGE57_LOCK1_LOCK_BL_MSB _u(5) -#define OTP_DATA_PAGE57_LOCK1_LOCK_BL_LSB _u(4) -#define OTP_DATA_PAGE57_LOCK1_LOCK_BL_ACCESS "RO" -#define OTP_DATA_PAGE57_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE57_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE57_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE57_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE57_LOCK1_LOCK_NS -// Description : Lock state for Non-secure accesses to this page. Thermometer- -// coded, so lock state can be advanced permanently from any state -// to any less-permissive state by programming OTP. Software can -// also advance the lock state temporarily (until next OTP reset) -// using the SW_LOCKx registers. -// -// Note that READ_WRITE and READ_ONLY are equivalent in hardware, -// as the SBPI programming interface is not accessible to Non- -// secure software. However, Secure software may check these bits -// to apply write permissions to a Non-secure OTP programming API. -// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. -// 0x1 -> Page can be read by Non-secure software -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. -// 0x3 -> Page can not be accessed by Non-secure software. -#define OTP_DATA_PAGE57_LOCK1_LOCK_NS_RESET "-" -#define OTP_DATA_PAGE57_LOCK1_LOCK_NS_BITS _u(0x0000000c) -#define OTP_DATA_PAGE57_LOCK1_LOCK_NS_MSB _u(3) -#define OTP_DATA_PAGE57_LOCK1_LOCK_NS_LSB _u(2) -#define OTP_DATA_PAGE57_LOCK1_LOCK_NS_ACCESS "RO" -#define OTP_DATA_PAGE57_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE57_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE57_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE57_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE57_LOCK1_LOCK_S -// Description : Lock state for Secure accesses to this page. Thermometer-coded, -// so lock state can be advanced permanently from any state to any -// less-permissive state by programming OTP. Software can also -// advance the lock state temporarily (until next OTP reset) using -// the SW_LOCKx registers. -// 0x0 -> Page is fully accessible by Secure software. -// 0x1 -> Page can be read by Secure software, but can not be written. -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. -// 0x3 -> Page can not be accessed by Secure software. -#define OTP_DATA_PAGE57_LOCK1_LOCK_S_RESET "-" -#define OTP_DATA_PAGE57_LOCK1_LOCK_S_BITS _u(0x00000003) -#define OTP_DATA_PAGE57_LOCK1_LOCK_S_MSB _u(1) -#define OTP_DATA_PAGE57_LOCK1_LOCK_S_LSB _u(0) -#define OTP_DATA_PAGE57_LOCK1_LOCK_S_ACCESS "RO" -#define OTP_DATA_PAGE57_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE57_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE57_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE57_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) -// ============================================================================= -// Register : OTP_DATA_PAGE58_LOCK0 -// Description : Lock configuration LSBs for page 58 (rows 0xe80 through 0xebf). -// Locks are stored with 3-way majority vote encoding, so that -// bits can be set independently. -// -// This OTP location is always readable, and is write-protected by -// its own permissions. -#define OTP_DATA_PAGE58_LOCK0_ROW _u(0x00000ff4) -#define OTP_DATA_PAGE58_LOCK0_BITS _u(0x00ffff7f) -#define OTP_DATA_PAGE58_LOCK0_RESET _u(0x00000000) -#define OTP_DATA_PAGE58_LOCK0_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE58_LOCK0_R2 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE58_LOCK0_R2_RESET "-" -#define OTP_DATA_PAGE58_LOCK0_R2_BITS _u(0x00ff0000) -#define OTP_DATA_PAGE58_LOCK0_R2_MSB _u(23) -#define OTP_DATA_PAGE58_LOCK0_R2_LSB _u(16) -#define OTP_DATA_PAGE58_LOCK0_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE58_LOCK0_R1 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE58_LOCK0_R1_RESET "-" -#define OTP_DATA_PAGE58_LOCK0_R1_BITS _u(0x0000ff00) -#define OTP_DATA_PAGE58_LOCK0_R1_MSB _u(15) -#define OTP_DATA_PAGE58_LOCK0_R1_LSB _u(8) -#define OTP_DATA_PAGE58_LOCK0_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE58_LOCK0_NO_KEY_STATE -// Description : State when at least one key is registered for this page and no -// matching key has been entered. -// 0x0 -> read_only -// 0x1 -> inaccessible -#define OTP_DATA_PAGE58_LOCK0_NO_KEY_STATE_RESET "-" -#define OTP_DATA_PAGE58_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) -#define OTP_DATA_PAGE58_LOCK0_NO_KEY_STATE_MSB _u(6) -#define OTP_DATA_PAGE58_LOCK0_NO_KEY_STATE_LSB _u(6) -#define OTP_DATA_PAGE58_LOCK0_NO_KEY_STATE_ACCESS "RO" -#define OTP_DATA_PAGE58_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) -#define OTP_DATA_PAGE58_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE58_LOCK0_KEY_R -// Description : Index 1-6 of a hardware key which must be entered to grant read -// access, or 0 if no such key is required. -#define OTP_DATA_PAGE58_LOCK0_KEY_R_RESET "-" -#define OTP_DATA_PAGE58_LOCK0_KEY_R_BITS _u(0x00000038) -#define OTP_DATA_PAGE58_LOCK0_KEY_R_MSB _u(5) -#define OTP_DATA_PAGE58_LOCK0_KEY_R_LSB _u(3) -#define OTP_DATA_PAGE58_LOCK0_KEY_R_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE58_LOCK0_KEY_W -// Description : Index 1-6 of a hardware key which must be entered to grant -// write access, or 0 if no such key is required. -#define OTP_DATA_PAGE58_LOCK0_KEY_W_RESET "-" -#define OTP_DATA_PAGE58_LOCK0_KEY_W_BITS _u(0x00000007) -#define OTP_DATA_PAGE58_LOCK0_KEY_W_MSB _u(2) -#define OTP_DATA_PAGE58_LOCK0_KEY_W_LSB _u(0) -#define OTP_DATA_PAGE58_LOCK0_KEY_W_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_PAGE58_LOCK1 -// Description : Lock configuration MSBs for page 58 (rows 0xe80 through 0xebf). -// Locks are stored with 3-way majority vote encoding, so that -// bits can be set independently. -// -// This OTP location is always readable, and is write-protected by -// its own permissions. -#define OTP_DATA_PAGE58_LOCK1_ROW _u(0x00000ff5) -#define OTP_DATA_PAGE58_LOCK1_BITS _u(0x00ffff3f) -#define OTP_DATA_PAGE58_LOCK1_RESET _u(0x00000000) -#define OTP_DATA_PAGE58_LOCK1_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE58_LOCK1_R2 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE58_LOCK1_R2_RESET "-" -#define OTP_DATA_PAGE58_LOCK1_R2_BITS _u(0x00ff0000) -#define OTP_DATA_PAGE58_LOCK1_R2_MSB _u(23) -#define OTP_DATA_PAGE58_LOCK1_R2_LSB _u(16) -#define OTP_DATA_PAGE58_LOCK1_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE58_LOCK1_R1 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE58_LOCK1_R1_RESET "-" -#define OTP_DATA_PAGE58_LOCK1_R1_BITS _u(0x0000ff00) -#define OTP_DATA_PAGE58_LOCK1_R1_MSB _u(15) -#define OTP_DATA_PAGE58_LOCK1_R1_LSB _u(8) -#define OTP_DATA_PAGE58_LOCK1_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE58_LOCK1_LOCK_BL -// Description : Dummy lock bits reserved for bootloaders (including the RP2350 -// USB bootloader) to store their own OTP access permissions. No -// hardware effect, and no corresponding SW_LOCKx registers. -// 0x0 -> Bootloader permits user reads and writes to this page -// 0x1 -> Bootloader permits user reads of this page -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE -// 0x3 -> Bootloader does not permit user access to this page -#define OTP_DATA_PAGE58_LOCK1_LOCK_BL_RESET "-" -#define OTP_DATA_PAGE58_LOCK1_LOCK_BL_BITS _u(0x00000030) -#define OTP_DATA_PAGE58_LOCK1_LOCK_BL_MSB _u(5) -#define OTP_DATA_PAGE58_LOCK1_LOCK_BL_LSB _u(4) -#define OTP_DATA_PAGE58_LOCK1_LOCK_BL_ACCESS "RO" -#define OTP_DATA_PAGE58_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE58_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE58_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE58_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE58_LOCK1_LOCK_NS -// Description : Lock state for Non-secure accesses to this page. Thermometer- -// coded, so lock state can be advanced permanently from any state -// to any less-permissive state by programming OTP. Software can -// also advance the lock state temporarily (until next OTP reset) -// using the SW_LOCKx registers. -// -// Note that READ_WRITE and READ_ONLY are equivalent in hardware, -// as the SBPI programming interface is not accessible to Non- -// secure software. However, Secure software may check these bits -// to apply write permissions to a Non-secure OTP programming API. -// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. -// 0x1 -> Page can be read by Non-secure software -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. -// 0x3 -> Page can not be accessed by Non-secure software. -#define OTP_DATA_PAGE58_LOCK1_LOCK_NS_RESET "-" -#define OTP_DATA_PAGE58_LOCK1_LOCK_NS_BITS _u(0x0000000c) -#define OTP_DATA_PAGE58_LOCK1_LOCK_NS_MSB _u(3) -#define OTP_DATA_PAGE58_LOCK1_LOCK_NS_LSB _u(2) -#define OTP_DATA_PAGE58_LOCK1_LOCK_NS_ACCESS "RO" -#define OTP_DATA_PAGE58_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE58_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE58_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE58_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE58_LOCK1_LOCK_S -// Description : Lock state for Secure accesses to this page. Thermometer-coded, -// so lock state can be advanced permanently from any state to any -// less-permissive state by programming OTP. Software can also -// advance the lock state temporarily (until next OTP reset) using -// the SW_LOCKx registers. -// 0x0 -> Page is fully accessible by Secure software. -// 0x1 -> Page can be read by Secure software, but can not be written. -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. -// 0x3 -> Page can not be accessed by Secure software. -#define OTP_DATA_PAGE58_LOCK1_LOCK_S_RESET "-" -#define OTP_DATA_PAGE58_LOCK1_LOCK_S_BITS _u(0x00000003) -#define OTP_DATA_PAGE58_LOCK1_LOCK_S_MSB _u(1) -#define OTP_DATA_PAGE58_LOCK1_LOCK_S_LSB _u(0) -#define OTP_DATA_PAGE58_LOCK1_LOCK_S_ACCESS "RO" -#define OTP_DATA_PAGE58_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE58_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE58_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE58_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) -// ============================================================================= -// Register : OTP_DATA_PAGE59_LOCK0 -// Description : Lock configuration LSBs for page 59 (rows 0xec0 through 0xeff). -// Locks are stored with 3-way majority vote encoding, so that -// bits can be set independently. -// -// This OTP location is always readable, and is write-protected by -// its own permissions. -#define OTP_DATA_PAGE59_LOCK0_ROW _u(0x00000ff6) -#define OTP_DATA_PAGE59_LOCK0_BITS _u(0x00ffff7f) -#define OTP_DATA_PAGE59_LOCK0_RESET _u(0x00000000) -#define OTP_DATA_PAGE59_LOCK0_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE59_LOCK0_R2 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE59_LOCK0_R2_RESET "-" -#define OTP_DATA_PAGE59_LOCK0_R2_BITS _u(0x00ff0000) -#define OTP_DATA_PAGE59_LOCK0_R2_MSB _u(23) -#define OTP_DATA_PAGE59_LOCK0_R2_LSB _u(16) -#define OTP_DATA_PAGE59_LOCK0_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE59_LOCK0_R1 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE59_LOCK0_R1_RESET "-" -#define OTP_DATA_PAGE59_LOCK0_R1_BITS _u(0x0000ff00) -#define OTP_DATA_PAGE59_LOCK0_R1_MSB _u(15) -#define OTP_DATA_PAGE59_LOCK0_R1_LSB _u(8) -#define OTP_DATA_PAGE59_LOCK0_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE59_LOCK0_NO_KEY_STATE -// Description : State when at least one key is registered for this page and no -// matching key has been entered. -// 0x0 -> read_only -// 0x1 -> inaccessible -#define OTP_DATA_PAGE59_LOCK0_NO_KEY_STATE_RESET "-" -#define OTP_DATA_PAGE59_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) -#define OTP_DATA_PAGE59_LOCK0_NO_KEY_STATE_MSB _u(6) -#define OTP_DATA_PAGE59_LOCK0_NO_KEY_STATE_LSB _u(6) -#define OTP_DATA_PAGE59_LOCK0_NO_KEY_STATE_ACCESS "RO" -#define OTP_DATA_PAGE59_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) -#define OTP_DATA_PAGE59_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE59_LOCK0_KEY_R -// Description : Index 1-6 of a hardware key which must be entered to grant read -// access, or 0 if no such key is required. -#define OTP_DATA_PAGE59_LOCK0_KEY_R_RESET "-" -#define OTP_DATA_PAGE59_LOCK0_KEY_R_BITS _u(0x00000038) -#define OTP_DATA_PAGE59_LOCK0_KEY_R_MSB _u(5) -#define OTP_DATA_PAGE59_LOCK0_KEY_R_LSB _u(3) -#define OTP_DATA_PAGE59_LOCK0_KEY_R_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE59_LOCK0_KEY_W -// Description : Index 1-6 of a hardware key which must be entered to grant -// write access, or 0 if no such key is required. -#define OTP_DATA_PAGE59_LOCK0_KEY_W_RESET "-" -#define OTP_DATA_PAGE59_LOCK0_KEY_W_BITS _u(0x00000007) -#define OTP_DATA_PAGE59_LOCK0_KEY_W_MSB _u(2) -#define OTP_DATA_PAGE59_LOCK0_KEY_W_LSB _u(0) -#define OTP_DATA_PAGE59_LOCK0_KEY_W_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_PAGE59_LOCK1 -// Description : Lock configuration MSBs for page 59 (rows 0xec0 through 0xeff). -// Locks are stored with 3-way majority vote encoding, so that -// bits can be set independently. -// -// This OTP location is always readable, and is write-protected by -// its own permissions. -#define OTP_DATA_PAGE59_LOCK1_ROW _u(0x00000ff7) -#define OTP_DATA_PAGE59_LOCK1_BITS _u(0x00ffff3f) -#define OTP_DATA_PAGE59_LOCK1_RESET _u(0x00000000) -#define OTP_DATA_PAGE59_LOCK1_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE59_LOCK1_R2 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE59_LOCK1_R2_RESET "-" -#define OTP_DATA_PAGE59_LOCK1_R2_BITS _u(0x00ff0000) -#define OTP_DATA_PAGE59_LOCK1_R2_MSB _u(23) -#define OTP_DATA_PAGE59_LOCK1_R2_LSB _u(16) -#define OTP_DATA_PAGE59_LOCK1_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE59_LOCK1_R1 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE59_LOCK1_R1_RESET "-" -#define OTP_DATA_PAGE59_LOCK1_R1_BITS _u(0x0000ff00) -#define OTP_DATA_PAGE59_LOCK1_R1_MSB _u(15) -#define OTP_DATA_PAGE59_LOCK1_R1_LSB _u(8) -#define OTP_DATA_PAGE59_LOCK1_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE59_LOCK1_LOCK_BL -// Description : Dummy lock bits reserved for bootloaders (including the RP2350 -// USB bootloader) to store their own OTP access permissions. No -// hardware effect, and no corresponding SW_LOCKx registers. -// 0x0 -> Bootloader permits user reads and writes to this page -// 0x1 -> Bootloader permits user reads of this page -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE -// 0x3 -> Bootloader does not permit user access to this page -#define OTP_DATA_PAGE59_LOCK1_LOCK_BL_RESET "-" -#define OTP_DATA_PAGE59_LOCK1_LOCK_BL_BITS _u(0x00000030) -#define OTP_DATA_PAGE59_LOCK1_LOCK_BL_MSB _u(5) -#define OTP_DATA_PAGE59_LOCK1_LOCK_BL_LSB _u(4) -#define OTP_DATA_PAGE59_LOCK1_LOCK_BL_ACCESS "RO" -#define OTP_DATA_PAGE59_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE59_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE59_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE59_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE59_LOCK1_LOCK_NS -// Description : Lock state for Non-secure accesses to this page. Thermometer- -// coded, so lock state can be advanced permanently from any state -// to any less-permissive state by programming OTP. Software can -// also advance the lock state temporarily (until next OTP reset) -// using the SW_LOCKx registers. -// -// Note that READ_WRITE and READ_ONLY are equivalent in hardware, -// as the SBPI programming interface is not accessible to Non- -// secure software. However, Secure software may check these bits -// to apply write permissions to a Non-secure OTP programming API. -// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. -// 0x1 -> Page can be read by Non-secure software -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. -// 0x3 -> Page can not be accessed by Non-secure software. -#define OTP_DATA_PAGE59_LOCK1_LOCK_NS_RESET "-" -#define OTP_DATA_PAGE59_LOCK1_LOCK_NS_BITS _u(0x0000000c) -#define OTP_DATA_PAGE59_LOCK1_LOCK_NS_MSB _u(3) -#define OTP_DATA_PAGE59_LOCK1_LOCK_NS_LSB _u(2) -#define OTP_DATA_PAGE59_LOCK1_LOCK_NS_ACCESS "RO" -#define OTP_DATA_PAGE59_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE59_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE59_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE59_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE59_LOCK1_LOCK_S -// Description : Lock state for Secure accesses to this page. Thermometer-coded, -// so lock state can be advanced permanently from any state to any -// less-permissive state by programming OTP. Software can also -// advance the lock state temporarily (until next OTP reset) using -// the SW_LOCKx registers. -// 0x0 -> Page is fully accessible by Secure software. -// 0x1 -> Page can be read by Secure software, but can not be written. -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. -// 0x3 -> Page can not be accessed by Secure software. -#define OTP_DATA_PAGE59_LOCK1_LOCK_S_RESET "-" -#define OTP_DATA_PAGE59_LOCK1_LOCK_S_BITS _u(0x00000003) -#define OTP_DATA_PAGE59_LOCK1_LOCK_S_MSB _u(1) -#define OTP_DATA_PAGE59_LOCK1_LOCK_S_LSB _u(0) -#define OTP_DATA_PAGE59_LOCK1_LOCK_S_ACCESS "RO" -#define OTP_DATA_PAGE59_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE59_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE59_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE59_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) -// ============================================================================= -// Register : OTP_DATA_PAGE60_LOCK0 -// Description : Lock configuration LSBs for page 60 (rows 0xf00 through 0xf3f). -// Locks are stored with 3-way majority vote encoding, so that -// bits can be set independently. -// -// This OTP location is always readable, and is write-protected by -// its own permissions. -#define OTP_DATA_PAGE60_LOCK0_ROW _u(0x00000ff8) -#define OTP_DATA_PAGE60_LOCK0_BITS _u(0x00ffff7f) -#define OTP_DATA_PAGE60_LOCK0_RESET _u(0x00000000) -#define OTP_DATA_PAGE60_LOCK0_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE60_LOCK0_R2 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE60_LOCK0_R2_RESET "-" -#define OTP_DATA_PAGE60_LOCK0_R2_BITS _u(0x00ff0000) -#define OTP_DATA_PAGE60_LOCK0_R2_MSB _u(23) -#define OTP_DATA_PAGE60_LOCK0_R2_LSB _u(16) -#define OTP_DATA_PAGE60_LOCK0_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE60_LOCK0_R1 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE60_LOCK0_R1_RESET "-" -#define OTP_DATA_PAGE60_LOCK0_R1_BITS _u(0x0000ff00) -#define OTP_DATA_PAGE60_LOCK0_R1_MSB _u(15) -#define OTP_DATA_PAGE60_LOCK0_R1_LSB _u(8) -#define OTP_DATA_PAGE60_LOCK0_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE60_LOCK0_NO_KEY_STATE -// Description : State when at least one key is registered for this page and no -// matching key has been entered. -// 0x0 -> read_only -// 0x1 -> inaccessible -#define OTP_DATA_PAGE60_LOCK0_NO_KEY_STATE_RESET "-" -#define OTP_DATA_PAGE60_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) -#define OTP_DATA_PAGE60_LOCK0_NO_KEY_STATE_MSB _u(6) -#define OTP_DATA_PAGE60_LOCK0_NO_KEY_STATE_LSB _u(6) -#define OTP_DATA_PAGE60_LOCK0_NO_KEY_STATE_ACCESS "RO" -#define OTP_DATA_PAGE60_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) -#define OTP_DATA_PAGE60_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE60_LOCK0_KEY_R -// Description : Index 1-6 of a hardware key which must be entered to grant read -// access, or 0 if no such key is required. -#define OTP_DATA_PAGE60_LOCK0_KEY_R_RESET "-" -#define OTP_DATA_PAGE60_LOCK0_KEY_R_BITS _u(0x00000038) -#define OTP_DATA_PAGE60_LOCK0_KEY_R_MSB _u(5) -#define OTP_DATA_PAGE60_LOCK0_KEY_R_LSB _u(3) -#define OTP_DATA_PAGE60_LOCK0_KEY_R_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE60_LOCK0_KEY_W -// Description : Index 1-6 of a hardware key which must be entered to grant -// write access, or 0 if no such key is required. -#define OTP_DATA_PAGE60_LOCK0_KEY_W_RESET "-" -#define OTP_DATA_PAGE60_LOCK0_KEY_W_BITS _u(0x00000007) -#define OTP_DATA_PAGE60_LOCK0_KEY_W_MSB _u(2) -#define OTP_DATA_PAGE60_LOCK0_KEY_W_LSB _u(0) -#define OTP_DATA_PAGE60_LOCK0_KEY_W_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_PAGE60_LOCK1 -// Description : Lock configuration MSBs for page 60 (rows 0xf00 through 0xf3f). -// Locks are stored with 3-way majority vote encoding, so that -// bits can be set independently. -// -// This OTP location is always readable, and is write-protected by -// its own permissions. -#define OTP_DATA_PAGE60_LOCK1_ROW _u(0x00000ff9) -#define OTP_DATA_PAGE60_LOCK1_BITS _u(0x00ffff3f) -#define OTP_DATA_PAGE60_LOCK1_RESET _u(0x00000000) -#define OTP_DATA_PAGE60_LOCK1_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE60_LOCK1_R2 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE60_LOCK1_R2_RESET "-" -#define OTP_DATA_PAGE60_LOCK1_R2_BITS _u(0x00ff0000) -#define OTP_DATA_PAGE60_LOCK1_R2_MSB _u(23) -#define OTP_DATA_PAGE60_LOCK1_R2_LSB _u(16) -#define OTP_DATA_PAGE60_LOCK1_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE60_LOCK1_R1 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE60_LOCK1_R1_RESET "-" -#define OTP_DATA_PAGE60_LOCK1_R1_BITS _u(0x0000ff00) -#define OTP_DATA_PAGE60_LOCK1_R1_MSB _u(15) -#define OTP_DATA_PAGE60_LOCK1_R1_LSB _u(8) -#define OTP_DATA_PAGE60_LOCK1_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE60_LOCK1_LOCK_BL -// Description : Dummy lock bits reserved for bootloaders (including the RP2350 -// USB bootloader) to store their own OTP access permissions. No -// hardware effect, and no corresponding SW_LOCKx registers. -// 0x0 -> Bootloader permits user reads and writes to this page -// 0x1 -> Bootloader permits user reads of this page -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE -// 0x3 -> Bootloader does not permit user access to this page -#define OTP_DATA_PAGE60_LOCK1_LOCK_BL_RESET "-" -#define OTP_DATA_PAGE60_LOCK1_LOCK_BL_BITS _u(0x00000030) -#define OTP_DATA_PAGE60_LOCK1_LOCK_BL_MSB _u(5) -#define OTP_DATA_PAGE60_LOCK1_LOCK_BL_LSB _u(4) -#define OTP_DATA_PAGE60_LOCK1_LOCK_BL_ACCESS "RO" -#define OTP_DATA_PAGE60_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE60_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE60_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE60_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE60_LOCK1_LOCK_NS -// Description : Lock state for Non-secure accesses to this page. Thermometer- -// coded, so lock state can be advanced permanently from any state -// to any less-permissive state by programming OTP. Software can -// also advance the lock state temporarily (until next OTP reset) -// using the SW_LOCKx registers. -// -// Note that READ_WRITE and READ_ONLY are equivalent in hardware, -// as the SBPI programming interface is not accessible to Non- -// secure software. However, Secure software may check these bits -// to apply write permissions to a Non-secure OTP programming API. -// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. -// 0x1 -> Page can be read by Non-secure software -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. -// 0x3 -> Page can not be accessed by Non-secure software. -#define OTP_DATA_PAGE60_LOCK1_LOCK_NS_RESET "-" -#define OTP_DATA_PAGE60_LOCK1_LOCK_NS_BITS _u(0x0000000c) -#define OTP_DATA_PAGE60_LOCK1_LOCK_NS_MSB _u(3) -#define OTP_DATA_PAGE60_LOCK1_LOCK_NS_LSB _u(2) -#define OTP_DATA_PAGE60_LOCK1_LOCK_NS_ACCESS "RO" -#define OTP_DATA_PAGE60_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE60_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE60_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE60_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE60_LOCK1_LOCK_S -// Description : Lock state for Secure accesses to this page. Thermometer-coded, -// so lock state can be advanced permanently from any state to any -// less-permissive state by programming OTP. Software can also -// advance the lock state temporarily (until next OTP reset) using -// the SW_LOCKx registers. -// 0x0 -> Page is fully accessible by Secure software. -// 0x1 -> Page can be read by Secure software, but can not be written. -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. -// 0x3 -> Page can not be accessed by Secure software. -#define OTP_DATA_PAGE60_LOCK1_LOCK_S_RESET "-" -#define OTP_DATA_PAGE60_LOCK1_LOCK_S_BITS _u(0x00000003) -#define OTP_DATA_PAGE60_LOCK1_LOCK_S_MSB _u(1) -#define OTP_DATA_PAGE60_LOCK1_LOCK_S_LSB _u(0) -#define OTP_DATA_PAGE60_LOCK1_LOCK_S_ACCESS "RO" -#define OTP_DATA_PAGE60_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE60_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE60_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE60_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) -// ============================================================================= -// Register : OTP_DATA_PAGE61_LOCK0 -// Description : Lock configuration LSBs for page 61 (rows 0xf40 through 0xf7f). -// Locks are stored with 3-way majority vote encoding, so that -// bits can be set independently. -// -// This OTP location is always readable, and is write-protected by -// its own permissions. -#define OTP_DATA_PAGE61_LOCK0_ROW _u(0x00000ffa) -#define OTP_DATA_PAGE61_LOCK0_BITS _u(0x00ffff7f) -#define OTP_DATA_PAGE61_LOCK0_RESET _u(0x00000000) -#define OTP_DATA_PAGE61_LOCK0_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE61_LOCK0_R2 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE61_LOCK0_R2_RESET "-" -#define OTP_DATA_PAGE61_LOCK0_R2_BITS _u(0x00ff0000) -#define OTP_DATA_PAGE61_LOCK0_R2_MSB _u(23) -#define OTP_DATA_PAGE61_LOCK0_R2_LSB _u(16) -#define OTP_DATA_PAGE61_LOCK0_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE61_LOCK0_R1 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE61_LOCK0_R1_RESET "-" -#define OTP_DATA_PAGE61_LOCK0_R1_BITS _u(0x0000ff00) -#define OTP_DATA_PAGE61_LOCK0_R1_MSB _u(15) -#define OTP_DATA_PAGE61_LOCK0_R1_LSB _u(8) -#define OTP_DATA_PAGE61_LOCK0_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE61_LOCK0_NO_KEY_STATE -// Description : State when at least one key is registered for this page and no -// matching key has been entered. -// 0x0 -> read_only -// 0x1 -> inaccessible -#define OTP_DATA_PAGE61_LOCK0_NO_KEY_STATE_RESET "-" -#define OTP_DATA_PAGE61_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) -#define OTP_DATA_PAGE61_LOCK0_NO_KEY_STATE_MSB _u(6) -#define OTP_DATA_PAGE61_LOCK0_NO_KEY_STATE_LSB _u(6) -#define OTP_DATA_PAGE61_LOCK0_NO_KEY_STATE_ACCESS "RO" -#define OTP_DATA_PAGE61_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) -#define OTP_DATA_PAGE61_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE61_LOCK0_KEY_R -// Description : Index 1-6 of a hardware key which must be entered to grant read -// access, or 0 if no such key is required. -#define OTP_DATA_PAGE61_LOCK0_KEY_R_RESET "-" -#define OTP_DATA_PAGE61_LOCK0_KEY_R_BITS _u(0x00000038) -#define OTP_DATA_PAGE61_LOCK0_KEY_R_MSB _u(5) -#define OTP_DATA_PAGE61_LOCK0_KEY_R_LSB _u(3) -#define OTP_DATA_PAGE61_LOCK0_KEY_R_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE61_LOCK0_KEY_W -// Description : Index 1-6 of a hardware key which must be entered to grant -// write access, or 0 if no such key is required. -#define OTP_DATA_PAGE61_LOCK0_KEY_W_RESET "-" -#define OTP_DATA_PAGE61_LOCK0_KEY_W_BITS _u(0x00000007) -#define OTP_DATA_PAGE61_LOCK0_KEY_W_MSB _u(2) -#define OTP_DATA_PAGE61_LOCK0_KEY_W_LSB _u(0) -#define OTP_DATA_PAGE61_LOCK0_KEY_W_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_PAGE61_LOCK1 -// Description : Lock configuration MSBs for page 61 (rows 0xf40 through 0xf7f). -// Locks are stored with 3-way majority vote encoding, so that -// bits can be set independently. -// -// This OTP location is always readable, and is write-protected by -// its own permissions. -#define OTP_DATA_PAGE61_LOCK1_ROW _u(0x00000ffb) -#define OTP_DATA_PAGE61_LOCK1_BITS _u(0x00ffff3f) -#define OTP_DATA_PAGE61_LOCK1_RESET _u(0x00000000) -#define OTP_DATA_PAGE61_LOCK1_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE61_LOCK1_R2 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE61_LOCK1_R2_RESET "-" -#define OTP_DATA_PAGE61_LOCK1_R2_BITS _u(0x00ff0000) -#define OTP_DATA_PAGE61_LOCK1_R2_MSB _u(23) -#define OTP_DATA_PAGE61_LOCK1_R2_LSB _u(16) -#define OTP_DATA_PAGE61_LOCK1_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE61_LOCK1_R1 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE61_LOCK1_R1_RESET "-" -#define OTP_DATA_PAGE61_LOCK1_R1_BITS _u(0x0000ff00) -#define OTP_DATA_PAGE61_LOCK1_R1_MSB _u(15) -#define OTP_DATA_PAGE61_LOCK1_R1_LSB _u(8) -#define OTP_DATA_PAGE61_LOCK1_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE61_LOCK1_LOCK_BL -// Description : Dummy lock bits reserved for bootloaders (including the RP2350 -// USB bootloader) to store their own OTP access permissions. No -// hardware effect, and no corresponding SW_LOCKx registers. -// 0x0 -> Bootloader permits user reads and writes to this page -// 0x1 -> Bootloader permits user reads of this page -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE -// 0x3 -> Bootloader does not permit user access to this page -#define OTP_DATA_PAGE61_LOCK1_LOCK_BL_RESET "-" -#define OTP_DATA_PAGE61_LOCK1_LOCK_BL_BITS _u(0x00000030) -#define OTP_DATA_PAGE61_LOCK1_LOCK_BL_MSB _u(5) -#define OTP_DATA_PAGE61_LOCK1_LOCK_BL_LSB _u(4) -#define OTP_DATA_PAGE61_LOCK1_LOCK_BL_ACCESS "RO" -#define OTP_DATA_PAGE61_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE61_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE61_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE61_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE61_LOCK1_LOCK_NS -// Description : Lock state for Non-secure accesses to this page. Thermometer- -// coded, so lock state can be advanced permanently from any state -// to any less-permissive state by programming OTP. Software can -// also advance the lock state temporarily (until next OTP reset) -// using the SW_LOCKx registers. -// -// Note that READ_WRITE and READ_ONLY are equivalent in hardware, -// as the SBPI programming interface is not accessible to Non- -// secure software. However, Secure software may check these bits -// to apply write permissions to a Non-secure OTP programming API. -// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. -// 0x1 -> Page can be read by Non-secure software -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. -// 0x3 -> Page can not be accessed by Non-secure software. -#define OTP_DATA_PAGE61_LOCK1_LOCK_NS_RESET "-" -#define OTP_DATA_PAGE61_LOCK1_LOCK_NS_BITS _u(0x0000000c) -#define OTP_DATA_PAGE61_LOCK1_LOCK_NS_MSB _u(3) -#define OTP_DATA_PAGE61_LOCK1_LOCK_NS_LSB _u(2) -#define OTP_DATA_PAGE61_LOCK1_LOCK_NS_ACCESS "RO" -#define OTP_DATA_PAGE61_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE61_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE61_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE61_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE61_LOCK1_LOCK_S -// Description : Lock state for Secure accesses to this page. Thermometer-coded, -// so lock state can be advanced permanently from any state to any -// less-permissive state by programming OTP. Software can also -// advance the lock state temporarily (until next OTP reset) using -// the SW_LOCKx registers. -// 0x0 -> Page is fully accessible by Secure software. -// 0x1 -> Page can be read by Secure software, but can not be written. -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. -// 0x3 -> Page can not be accessed by Secure software. -#define OTP_DATA_PAGE61_LOCK1_LOCK_S_RESET "-" -#define OTP_DATA_PAGE61_LOCK1_LOCK_S_BITS _u(0x00000003) -#define OTP_DATA_PAGE61_LOCK1_LOCK_S_MSB _u(1) -#define OTP_DATA_PAGE61_LOCK1_LOCK_S_LSB _u(0) -#define OTP_DATA_PAGE61_LOCK1_LOCK_S_ACCESS "RO" -#define OTP_DATA_PAGE61_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE61_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE61_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE61_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) -// ============================================================================= -// Register : OTP_DATA_PAGE62_LOCK0 -// Description : Lock configuration LSBs for page 62 (rows 0xf80 through 0xfbf). -// Locks are stored with 3-way majority vote encoding, so that -// bits can be set independently. -// -// This OTP location is always readable, and is write-protected by -// its own permissions. -#define OTP_DATA_PAGE62_LOCK0_ROW _u(0x00000ffc) -#define OTP_DATA_PAGE62_LOCK0_BITS _u(0x00ffff7f) -#define OTP_DATA_PAGE62_LOCK0_RESET _u(0x00000000) -#define OTP_DATA_PAGE62_LOCK0_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE62_LOCK0_R2 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE62_LOCK0_R2_RESET "-" -#define OTP_DATA_PAGE62_LOCK0_R2_BITS _u(0x00ff0000) -#define OTP_DATA_PAGE62_LOCK0_R2_MSB _u(23) -#define OTP_DATA_PAGE62_LOCK0_R2_LSB _u(16) -#define OTP_DATA_PAGE62_LOCK0_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE62_LOCK0_R1 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE62_LOCK0_R1_RESET "-" -#define OTP_DATA_PAGE62_LOCK0_R1_BITS _u(0x0000ff00) -#define OTP_DATA_PAGE62_LOCK0_R1_MSB _u(15) -#define OTP_DATA_PAGE62_LOCK0_R1_LSB _u(8) -#define OTP_DATA_PAGE62_LOCK0_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE62_LOCK0_NO_KEY_STATE -// Description : State when at least one key is registered for this page and no -// matching key has been entered. -// 0x0 -> read_only -// 0x1 -> inaccessible -#define OTP_DATA_PAGE62_LOCK0_NO_KEY_STATE_RESET "-" -#define OTP_DATA_PAGE62_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) -#define OTP_DATA_PAGE62_LOCK0_NO_KEY_STATE_MSB _u(6) -#define OTP_DATA_PAGE62_LOCK0_NO_KEY_STATE_LSB _u(6) -#define OTP_DATA_PAGE62_LOCK0_NO_KEY_STATE_ACCESS "RO" -#define OTP_DATA_PAGE62_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) -#define OTP_DATA_PAGE62_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE62_LOCK0_KEY_R -// Description : Index 1-6 of a hardware key which must be entered to grant read -// access, or 0 if no such key is required. -#define OTP_DATA_PAGE62_LOCK0_KEY_R_RESET "-" -#define OTP_DATA_PAGE62_LOCK0_KEY_R_BITS _u(0x00000038) -#define OTP_DATA_PAGE62_LOCK0_KEY_R_MSB _u(5) -#define OTP_DATA_PAGE62_LOCK0_KEY_R_LSB _u(3) -#define OTP_DATA_PAGE62_LOCK0_KEY_R_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE62_LOCK0_KEY_W -// Description : Index 1-6 of a hardware key which must be entered to grant -// write access, or 0 if no such key is required. -#define OTP_DATA_PAGE62_LOCK0_KEY_W_RESET "-" -#define OTP_DATA_PAGE62_LOCK0_KEY_W_BITS _u(0x00000007) -#define OTP_DATA_PAGE62_LOCK0_KEY_W_MSB _u(2) -#define OTP_DATA_PAGE62_LOCK0_KEY_W_LSB _u(0) -#define OTP_DATA_PAGE62_LOCK0_KEY_W_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_PAGE62_LOCK1 -// Description : Lock configuration MSBs for page 62 (rows 0xf80 through 0xfbf). -// Locks are stored with 3-way majority vote encoding, so that -// bits can be set independently. -// -// This OTP location is always readable, and is write-protected by -// its own permissions. -#define OTP_DATA_PAGE62_LOCK1_ROW _u(0x00000ffd) -#define OTP_DATA_PAGE62_LOCK1_BITS _u(0x00ffff3f) -#define OTP_DATA_PAGE62_LOCK1_RESET _u(0x00000000) -#define OTP_DATA_PAGE62_LOCK1_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE62_LOCK1_R2 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE62_LOCK1_R2_RESET "-" -#define OTP_DATA_PAGE62_LOCK1_R2_BITS _u(0x00ff0000) -#define OTP_DATA_PAGE62_LOCK1_R2_MSB _u(23) -#define OTP_DATA_PAGE62_LOCK1_R2_LSB _u(16) -#define OTP_DATA_PAGE62_LOCK1_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE62_LOCK1_R1 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE62_LOCK1_R1_RESET "-" -#define OTP_DATA_PAGE62_LOCK1_R1_BITS _u(0x0000ff00) -#define OTP_DATA_PAGE62_LOCK1_R1_MSB _u(15) -#define OTP_DATA_PAGE62_LOCK1_R1_LSB _u(8) -#define OTP_DATA_PAGE62_LOCK1_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE62_LOCK1_LOCK_BL -// Description : Dummy lock bits reserved for bootloaders (including the RP2350 -// USB bootloader) to store their own OTP access permissions. No -// hardware effect, and no corresponding SW_LOCKx registers. -// 0x0 -> Bootloader permits user reads and writes to this page -// 0x1 -> Bootloader permits user reads of this page -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE -// 0x3 -> Bootloader does not permit user access to this page -#define OTP_DATA_PAGE62_LOCK1_LOCK_BL_RESET "-" -#define OTP_DATA_PAGE62_LOCK1_LOCK_BL_BITS _u(0x00000030) -#define OTP_DATA_PAGE62_LOCK1_LOCK_BL_MSB _u(5) -#define OTP_DATA_PAGE62_LOCK1_LOCK_BL_LSB _u(4) -#define OTP_DATA_PAGE62_LOCK1_LOCK_BL_ACCESS "RO" -#define OTP_DATA_PAGE62_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE62_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE62_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE62_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE62_LOCK1_LOCK_NS -// Description : Lock state for Non-secure accesses to this page. Thermometer- -// coded, so lock state can be advanced permanently from any state -// to any less-permissive state by programming OTP. Software can -// also advance the lock state temporarily (until next OTP reset) -// using the SW_LOCKx registers. -// -// Note that READ_WRITE and READ_ONLY are equivalent in hardware, -// as the SBPI programming interface is not accessible to Non- -// secure software. However, Secure software may check these bits -// to apply write permissions to a Non-secure OTP programming API. -// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. -// 0x1 -> Page can be read by Non-secure software -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. -// 0x3 -> Page can not be accessed by Non-secure software. -#define OTP_DATA_PAGE62_LOCK1_LOCK_NS_RESET "-" -#define OTP_DATA_PAGE62_LOCK1_LOCK_NS_BITS _u(0x0000000c) -#define OTP_DATA_PAGE62_LOCK1_LOCK_NS_MSB _u(3) -#define OTP_DATA_PAGE62_LOCK1_LOCK_NS_LSB _u(2) -#define OTP_DATA_PAGE62_LOCK1_LOCK_NS_ACCESS "RO" -#define OTP_DATA_PAGE62_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE62_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE62_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE62_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE62_LOCK1_LOCK_S -// Description : Lock state for Secure accesses to this page. Thermometer-coded, -// so lock state can be advanced permanently from any state to any -// less-permissive state by programming OTP. Software can also -// advance the lock state temporarily (until next OTP reset) using -// the SW_LOCKx registers. -// 0x0 -> Page is fully accessible by Secure software. -// 0x1 -> Page can be read by Secure software, but can not be written. -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. -// 0x3 -> Page can not be accessed by Secure software. -#define OTP_DATA_PAGE62_LOCK1_LOCK_S_RESET "-" -#define OTP_DATA_PAGE62_LOCK1_LOCK_S_BITS _u(0x00000003) -#define OTP_DATA_PAGE62_LOCK1_LOCK_S_MSB _u(1) -#define OTP_DATA_PAGE62_LOCK1_LOCK_S_LSB _u(0) -#define OTP_DATA_PAGE62_LOCK1_LOCK_S_ACCESS "RO" -#define OTP_DATA_PAGE62_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE62_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE62_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE62_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) -// ============================================================================= -// Register : OTP_DATA_PAGE63_LOCK0 -// Description : Lock configuration LSBs for page 63 (rows 0xfc0 through 0xfff). -// Locks are stored with 3-way majority vote encoding, so that -// bits can be set independently. -// -// This OTP location is always readable, and is write-protected by -// its own permissions. -#define OTP_DATA_PAGE63_LOCK0_ROW _u(0x00000ffe) -#define OTP_DATA_PAGE63_LOCK0_BITS _u(0x00ffffff) -#define OTP_DATA_PAGE63_LOCK0_RESET _u(0x00000000) -#define OTP_DATA_PAGE63_LOCK0_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE63_LOCK0_R2 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE63_LOCK0_R2_RESET "-" -#define OTP_DATA_PAGE63_LOCK0_R2_BITS _u(0x00ff0000) -#define OTP_DATA_PAGE63_LOCK0_R2_MSB _u(23) -#define OTP_DATA_PAGE63_LOCK0_R2_LSB _u(16) -#define OTP_DATA_PAGE63_LOCK0_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE63_LOCK0_R1 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE63_LOCK0_R1_RESET "-" -#define OTP_DATA_PAGE63_LOCK0_R1_BITS _u(0x0000ff00) -#define OTP_DATA_PAGE63_LOCK0_R1_MSB _u(15) -#define OTP_DATA_PAGE63_LOCK0_R1_LSB _u(8) -#define OTP_DATA_PAGE63_LOCK0_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE63_LOCK0_RMA -// Description : Decommission for RMA of a suspected faulty device. This re- -// enables the factory test JTAG interface, and makes pages 3 -// through 61 of the OTP permanently inaccessible. -#define OTP_DATA_PAGE63_LOCK0_RMA_RESET "-" -#define OTP_DATA_PAGE63_LOCK0_RMA_BITS _u(0x00000080) -#define OTP_DATA_PAGE63_LOCK0_RMA_MSB _u(7) -#define OTP_DATA_PAGE63_LOCK0_RMA_LSB _u(7) -#define OTP_DATA_PAGE63_LOCK0_RMA_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE63_LOCK0_NO_KEY_STATE -// Description : State when at least one key is registered for this page and no -// matching key has been entered. -// 0x0 -> read_only -// 0x1 -> inaccessible -#define OTP_DATA_PAGE63_LOCK0_NO_KEY_STATE_RESET "-" -#define OTP_DATA_PAGE63_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) -#define OTP_DATA_PAGE63_LOCK0_NO_KEY_STATE_MSB _u(6) -#define OTP_DATA_PAGE63_LOCK0_NO_KEY_STATE_LSB _u(6) -#define OTP_DATA_PAGE63_LOCK0_NO_KEY_STATE_ACCESS "RO" -#define OTP_DATA_PAGE63_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) -#define OTP_DATA_PAGE63_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE63_LOCK0_KEY_R -// Description : Index 1-6 of a hardware key which must be entered to grant read -// access, or 0 if no such key is required. -#define OTP_DATA_PAGE63_LOCK0_KEY_R_RESET "-" -#define OTP_DATA_PAGE63_LOCK0_KEY_R_BITS _u(0x00000038) -#define OTP_DATA_PAGE63_LOCK0_KEY_R_MSB _u(5) -#define OTP_DATA_PAGE63_LOCK0_KEY_R_LSB _u(3) -#define OTP_DATA_PAGE63_LOCK0_KEY_R_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE63_LOCK0_KEY_W -// Description : Index 1-6 of a hardware key which must be entered to grant -// write access, or 0 if no such key is required. -#define OTP_DATA_PAGE63_LOCK0_KEY_W_RESET "-" -#define OTP_DATA_PAGE63_LOCK0_KEY_W_BITS _u(0x00000007) -#define OTP_DATA_PAGE63_LOCK0_KEY_W_MSB _u(2) -#define OTP_DATA_PAGE63_LOCK0_KEY_W_LSB _u(0) -#define OTP_DATA_PAGE63_LOCK0_KEY_W_ACCESS "RO" -// ============================================================================= -// Register : OTP_DATA_PAGE63_LOCK1 -// Description : Lock configuration MSBs for page 63 (rows 0xfc0 through 0xfff). -// Locks are stored with 3-way majority vote encoding, so that -// bits can be set independently. -// -// This OTP location is always readable, and is write-protected by -// its own permissions. -#define OTP_DATA_PAGE63_LOCK1_ROW _u(0x00000fff) -#define OTP_DATA_PAGE63_LOCK1_BITS _u(0x00ffff3f) -#define OTP_DATA_PAGE63_LOCK1_RESET _u(0x00000000) -#define OTP_DATA_PAGE63_LOCK1_WIDTH _u(24) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE63_LOCK1_R2 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE63_LOCK1_R2_RESET "-" -#define OTP_DATA_PAGE63_LOCK1_R2_BITS _u(0x00ff0000) -#define OTP_DATA_PAGE63_LOCK1_R2_MSB _u(23) -#define OTP_DATA_PAGE63_LOCK1_R2_LSB _u(16) -#define OTP_DATA_PAGE63_LOCK1_R2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE63_LOCK1_R1 -// Description : Redundant copy of bits 7:0 -#define OTP_DATA_PAGE63_LOCK1_R1_RESET "-" -#define OTP_DATA_PAGE63_LOCK1_R1_BITS _u(0x0000ff00) -#define OTP_DATA_PAGE63_LOCK1_R1_MSB _u(15) -#define OTP_DATA_PAGE63_LOCK1_R1_LSB _u(8) -#define OTP_DATA_PAGE63_LOCK1_R1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE63_LOCK1_LOCK_BL -// Description : Dummy lock bits reserved for bootloaders (including the RP2350 -// USB bootloader) to store their own OTP access permissions. No -// hardware effect, and no corresponding SW_LOCKx registers. -// 0x0 -> Bootloader permits user reads and writes to this page -// 0x1 -> Bootloader permits user reads of this page -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE -// 0x3 -> Bootloader does not permit user access to this page -#define OTP_DATA_PAGE63_LOCK1_LOCK_BL_RESET "-" -#define OTP_DATA_PAGE63_LOCK1_LOCK_BL_BITS _u(0x00000030) -#define OTP_DATA_PAGE63_LOCK1_LOCK_BL_MSB _u(5) -#define OTP_DATA_PAGE63_LOCK1_LOCK_BL_LSB _u(4) -#define OTP_DATA_PAGE63_LOCK1_LOCK_BL_ACCESS "RO" -#define OTP_DATA_PAGE63_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE63_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE63_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE63_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE63_LOCK1_LOCK_NS -// Description : Lock state for Non-secure accesses to this page. Thermometer- -// coded, so lock state can be advanced permanently from any state -// to any less-permissive state by programming OTP. Software can -// also advance the lock state temporarily (until next OTP reset) -// using the SW_LOCKx registers. -// -// Note that READ_WRITE and READ_ONLY are equivalent in hardware, -// as the SBPI programming interface is not accessible to Non- -// secure software. However, Secure software may check these bits -// to apply write permissions to a Non-secure OTP programming API. -// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. -// 0x1 -> Page can be read by Non-secure software -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. -// 0x3 -> Page can not be accessed by Non-secure software. -#define OTP_DATA_PAGE63_LOCK1_LOCK_NS_RESET "-" -#define OTP_DATA_PAGE63_LOCK1_LOCK_NS_BITS _u(0x0000000c) -#define OTP_DATA_PAGE63_LOCK1_LOCK_NS_MSB _u(3) -#define OTP_DATA_PAGE63_LOCK1_LOCK_NS_LSB _u(2) -#define OTP_DATA_PAGE63_LOCK1_LOCK_NS_ACCESS "RO" -#define OTP_DATA_PAGE63_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE63_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE63_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE63_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) -// ----------------------------------------------------------------------------- -// Field : OTP_DATA_PAGE63_LOCK1_LOCK_S -// Description : Lock state for Secure accesses to this page. Thermometer-coded, -// so lock state can be advanced permanently from any state to any -// less-permissive state by programming OTP. Software can also -// advance the lock state temporarily (until next OTP reset) using -// the SW_LOCKx registers. -// 0x0 -> Page is fully accessible by Secure software. -// 0x1 -> Page can be read by Secure software, but can not be written. -// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. -// 0x3 -> Page can not be accessed by Secure software. -#define OTP_DATA_PAGE63_LOCK1_LOCK_S_RESET "-" -#define OTP_DATA_PAGE63_LOCK1_LOCK_S_BITS _u(0x00000003) -#define OTP_DATA_PAGE63_LOCK1_LOCK_S_MSB _u(1) -#define OTP_DATA_PAGE63_LOCK1_LOCK_S_LSB _u(0) -#define OTP_DATA_PAGE63_LOCK1_LOCK_S_ACCESS "RO" -#define OTP_DATA_PAGE63_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) -#define OTP_DATA_PAGE63_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) -#define OTP_DATA_PAGE63_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) -#define OTP_DATA_PAGE63_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) -// ============================================================================= -#endif // _HARDWARE_REGS_OTP_DATA_H - diff --git a/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/pads_bank0.h b/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/pads_bank0.h deleted file mode 100644 index cf262054f3..0000000000 --- a/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/pads_bank0.h +++ /dev/null @@ -1,3980 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -// ============================================================================= -// Register block : PADS_BANK0 -// Version : 1 -// Bus type : apb -// ============================================================================= -#ifndef _HARDWARE_REGS_PADS_BANK0_H -#define _HARDWARE_REGS_PADS_BANK0_H -// ============================================================================= -// Register : PADS_BANK0_VOLTAGE_SELECT -// Description : Voltage select. Per bank control -// 0x0 -> Set voltage to 3.3V (DVDD >= 2V5) -// 0x1 -> Set voltage to 1.8V (DVDD <= 1V8) -#define PADS_BANK0_VOLTAGE_SELECT_OFFSET _u(0x00000000) -#define PADS_BANK0_VOLTAGE_SELECT_BITS _u(0x00000001) -#define PADS_BANK0_VOLTAGE_SELECT_RESET _u(0x00000000) -#define PADS_BANK0_VOLTAGE_SELECT_MSB _u(0) -#define PADS_BANK0_VOLTAGE_SELECT_LSB _u(0) -#define PADS_BANK0_VOLTAGE_SELECT_ACCESS "RW" -#define PADS_BANK0_VOLTAGE_SELECT_VALUE_3V3 _u(0x0) -#define PADS_BANK0_VOLTAGE_SELECT_VALUE_1V8 _u(0x1) -// ============================================================================= -// Register : PADS_BANK0_GPIO0 -#define PADS_BANK0_GPIO0_OFFSET _u(0x00000004) -#define PADS_BANK0_GPIO0_BITS _u(0x000001ff) -#define PADS_BANK0_GPIO0_RESET _u(0x00000116) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO0_ISO -// Description : Pad isolation control. Remove this once the pad is configured -// by software. -#define PADS_BANK0_GPIO0_ISO_RESET _u(0x1) -#define PADS_BANK0_GPIO0_ISO_BITS _u(0x00000100) -#define PADS_BANK0_GPIO0_ISO_MSB _u(8) -#define PADS_BANK0_GPIO0_ISO_LSB _u(8) -#define PADS_BANK0_GPIO0_ISO_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO0_OD -// Description : Output disable. Has priority over output enable from -// peripherals -#define PADS_BANK0_GPIO0_OD_RESET _u(0x0) -#define PADS_BANK0_GPIO0_OD_BITS _u(0x00000080) -#define PADS_BANK0_GPIO0_OD_MSB _u(7) -#define PADS_BANK0_GPIO0_OD_LSB _u(7) -#define PADS_BANK0_GPIO0_OD_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO0_IE -// Description : Input enable -#define PADS_BANK0_GPIO0_IE_RESET _u(0x0) -#define PADS_BANK0_GPIO0_IE_BITS _u(0x00000040) -#define PADS_BANK0_GPIO0_IE_MSB _u(6) -#define PADS_BANK0_GPIO0_IE_LSB _u(6) -#define PADS_BANK0_GPIO0_IE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO0_DRIVE -// Description : Drive strength. -// 0x0 -> 2mA -// 0x1 -> 4mA -// 0x2 -> 8mA -// 0x3 -> 12mA -#define PADS_BANK0_GPIO0_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO0_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO0_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO0_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO0_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO0_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO0_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO0_DRIVE_VALUE_8MA _u(0x2) -#define PADS_BANK0_GPIO0_DRIVE_VALUE_12MA _u(0x3) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO0_PUE -// Description : Pull up enable -#define PADS_BANK0_GPIO0_PUE_RESET _u(0x0) -#define PADS_BANK0_GPIO0_PUE_BITS _u(0x00000008) -#define PADS_BANK0_GPIO0_PUE_MSB _u(3) -#define PADS_BANK0_GPIO0_PUE_LSB _u(3) -#define PADS_BANK0_GPIO0_PUE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO0_PDE -// Description : Pull down enable -#define PADS_BANK0_GPIO0_PDE_RESET _u(0x1) -#define PADS_BANK0_GPIO0_PDE_BITS _u(0x00000004) -#define PADS_BANK0_GPIO0_PDE_MSB _u(2) -#define PADS_BANK0_GPIO0_PDE_LSB _u(2) -#define PADS_BANK0_GPIO0_PDE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO0_SCHMITT -// Description : Enable schmitt trigger -#define PADS_BANK0_GPIO0_SCHMITT_RESET _u(0x1) -#define PADS_BANK0_GPIO0_SCHMITT_BITS _u(0x00000002) -#define PADS_BANK0_GPIO0_SCHMITT_MSB _u(1) -#define PADS_BANK0_GPIO0_SCHMITT_LSB _u(1) -#define PADS_BANK0_GPIO0_SCHMITT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO0_SLEWFAST -// Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO0_SLEWFAST_RESET _u(0x0) -#define PADS_BANK0_GPIO0_SLEWFAST_BITS _u(0x00000001) -#define PADS_BANK0_GPIO0_SLEWFAST_MSB _u(0) -#define PADS_BANK0_GPIO0_SLEWFAST_LSB _u(0) -#define PADS_BANK0_GPIO0_SLEWFAST_ACCESS "RW" -// ============================================================================= -// Register : PADS_BANK0_GPIO1 -#define PADS_BANK0_GPIO1_OFFSET _u(0x00000008) -#define PADS_BANK0_GPIO1_BITS _u(0x000001ff) -#define PADS_BANK0_GPIO1_RESET _u(0x00000116) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO1_ISO -// Description : Pad isolation control. Remove this once the pad is configured -// by software. -#define PADS_BANK0_GPIO1_ISO_RESET _u(0x1) -#define PADS_BANK0_GPIO1_ISO_BITS _u(0x00000100) -#define PADS_BANK0_GPIO1_ISO_MSB _u(8) -#define PADS_BANK0_GPIO1_ISO_LSB _u(8) -#define PADS_BANK0_GPIO1_ISO_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO1_OD -// Description : Output disable. Has priority over output enable from -// peripherals -#define PADS_BANK0_GPIO1_OD_RESET _u(0x0) -#define PADS_BANK0_GPIO1_OD_BITS _u(0x00000080) -#define PADS_BANK0_GPIO1_OD_MSB _u(7) -#define PADS_BANK0_GPIO1_OD_LSB _u(7) -#define PADS_BANK0_GPIO1_OD_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO1_IE -// Description : Input enable -#define PADS_BANK0_GPIO1_IE_RESET _u(0x0) -#define PADS_BANK0_GPIO1_IE_BITS _u(0x00000040) -#define PADS_BANK0_GPIO1_IE_MSB _u(6) -#define PADS_BANK0_GPIO1_IE_LSB _u(6) -#define PADS_BANK0_GPIO1_IE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO1_DRIVE -// Description : Drive strength. -// 0x0 -> 2mA -// 0x1 -> 4mA -// 0x2 -> 8mA -// 0x3 -> 12mA -#define PADS_BANK0_GPIO1_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO1_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO1_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO1_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO1_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO1_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO1_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO1_DRIVE_VALUE_8MA _u(0x2) -#define PADS_BANK0_GPIO1_DRIVE_VALUE_12MA _u(0x3) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO1_PUE -// Description : Pull up enable -#define PADS_BANK0_GPIO1_PUE_RESET _u(0x0) -#define PADS_BANK0_GPIO1_PUE_BITS _u(0x00000008) -#define PADS_BANK0_GPIO1_PUE_MSB _u(3) -#define PADS_BANK0_GPIO1_PUE_LSB _u(3) -#define PADS_BANK0_GPIO1_PUE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO1_PDE -// Description : Pull down enable -#define PADS_BANK0_GPIO1_PDE_RESET _u(0x1) -#define PADS_BANK0_GPIO1_PDE_BITS _u(0x00000004) -#define PADS_BANK0_GPIO1_PDE_MSB _u(2) -#define PADS_BANK0_GPIO1_PDE_LSB _u(2) -#define PADS_BANK0_GPIO1_PDE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO1_SCHMITT -// Description : Enable schmitt trigger -#define PADS_BANK0_GPIO1_SCHMITT_RESET _u(0x1) -#define PADS_BANK0_GPIO1_SCHMITT_BITS _u(0x00000002) -#define PADS_BANK0_GPIO1_SCHMITT_MSB _u(1) -#define PADS_BANK0_GPIO1_SCHMITT_LSB _u(1) -#define PADS_BANK0_GPIO1_SCHMITT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO1_SLEWFAST -// Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO1_SLEWFAST_RESET _u(0x0) -#define PADS_BANK0_GPIO1_SLEWFAST_BITS _u(0x00000001) -#define PADS_BANK0_GPIO1_SLEWFAST_MSB _u(0) -#define PADS_BANK0_GPIO1_SLEWFAST_LSB _u(0) -#define PADS_BANK0_GPIO1_SLEWFAST_ACCESS "RW" -// ============================================================================= -// Register : PADS_BANK0_GPIO2 -#define PADS_BANK0_GPIO2_OFFSET _u(0x0000000c) -#define PADS_BANK0_GPIO2_BITS _u(0x000001ff) -#define PADS_BANK0_GPIO2_RESET _u(0x00000116) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO2_ISO -// Description : Pad isolation control. Remove this once the pad is configured -// by software. -#define PADS_BANK0_GPIO2_ISO_RESET _u(0x1) -#define PADS_BANK0_GPIO2_ISO_BITS _u(0x00000100) -#define PADS_BANK0_GPIO2_ISO_MSB _u(8) -#define PADS_BANK0_GPIO2_ISO_LSB _u(8) -#define PADS_BANK0_GPIO2_ISO_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO2_OD -// Description : Output disable. Has priority over output enable from -// peripherals -#define PADS_BANK0_GPIO2_OD_RESET _u(0x0) -#define PADS_BANK0_GPIO2_OD_BITS _u(0x00000080) -#define PADS_BANK0_GPIO2_OD_MSB _u(7) -#define PADS_BANK0_GPIO2_OD_LSB _u(7) -#define PADS_BANK0_GPIO2_OD_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO2_IE -// Description : Input enable -#define PADS_BANK0_GPIO2_IE_RESET _u(0x0) -#define PADS_BANK0_GPIO2_IE_BITS _u(0x00000040) -#define PADS_BANK0_GPIO2_IE_MSB _u(6) -#define PADS_BANK0_GPIO2_IE_LSB _u(6) -#define PADS_BANK0_GPIO2_IE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO2_DRIVE -// Description : Drive strength. -// 0x0 -> 2mA -// 0x1 -> 4mA -// 0x2 -> 8mA -// 0x3 -> 12mA -#define PADS_BANK0_GPIO2_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO2_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO2_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO2_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO2_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO2_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO2_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO2_DRIVE_VALUE_8MA _u(0x2) -#define PADS_BANK0_GPIO2_DRIVE_VALUE_12MA _u(0x3) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO2_PUE -// Description : Pull up enable -#define PADS_BANK0_GPIO2_PUE_RESET _u(0x0) -#define PADS_BANK0_GPIO2_PUE_BITS _u(0x00000008) -#define PADS_BANK0_GPIO2_PUE_MSB _u(3) -#define PADS_BANK0_GPIO2_PUE_LSB _u(3) -#define PADS_BANK0_GPIO2_PUE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO2_PDE -// Description : Pull down enable -#define PADS_BANK0_GPIO2_PDE_RESET _u(0x1) -#define PADS_BANK0_GPIO2_PDE_BITS _u(0x00000004) -#define PADS_BANK0_GPIO2_PDE_MSB _u(2) -#define PADS_BANK0_GPIO2_PDE_LSB _u(2) -#define PADS_BANK0_GPIO2_PDE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO2_SCHMITT -// Description : Enable schmitt trigger -#define PADS_BANK0_GPIO2_SCHMITT_RESET _u(0x1) -#define PADS_BANK0_GPIO2_SCHMITT_BITS _u(0x00000002) -#define PADS_BANK0_GPIO2_SCHMITT_MSB _u(1) -#define PADS_BANK0_GPIO2_SCHMITT_LSB _u(1) -#define PADS_BANK0_GPIO2_SCHMITT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO2_SLEWFAST -// Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO2_SLEWFAST_RESET _u(0x0) -#define PADS_BANK0_GPIO2_SLEWFAST_BITS _u(0x00000001) -#define PADS_BANK0_GPIO2_SLEWFAST_MSB _u(0) -#define PADS_BANK0_GPIO2_SLEWFAST_LSB _u(0) -#define PADS_BANK0_GPIO2_SLEWFAST_ACCESS "RW" -// ============================================================================= -// Register : PADS_BANK0_GPIO3 -#define PADS_BANK0_GPIO3_OFFSET _u(0x00000010) -#define PADS_BANK0_GPIO3_BITS _u(0x000001ff) -#define PADS_BANK0_GPIO3_RESET _u(0x00000116) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO3_ISO -// Description : Pad isolation control. Remove this once the pad is configured -// by software. -#define PADS_BANK0_GPIO3_ISO_RESET _u(0x1) -#define PADS_BANK0_GPIO3_ISO_BITS _u(0x00000100) -#define PADS_BANK0_GPIO3_ISO_MSB _u(8) -#define PADS_BANK0_GPIO3_ISO_LSB _u(8) -#define PADS_BANK0_GPIO3_ISO_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO3_OD -// Description : Output disable. Has priority over output enable from -// peripherals -#define PADS_BANK0_GPIO3_OD_RESET _u(0x0) -#define PADS_BANK0_GPIO3_OD_BITS _u(0x00000080) -#define PADS_BANK0_GPIO3_OD_MSB _u(7) -#define PADS_BANK0_GPIO3_OD_LSB _u(7) -#define PADS_BANK0_GPIO3_OD_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO3_IE -// Description : Input enable -#define PADS_BANK0_GPIO3_IE_RESET _u(0x0) -#define PADS_BANK0_GPIO3_IE_BITS _u(0x00000040) -#define PADS_BANK0_GPIO3_IE_MSB _u(6) -#define PADS_BANK0_GPIO3_IE_LSB _u(6) -#define PADS_BANK0_GPIO3_IE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO3_DRIVE -// Description : Drive strength. -// 0x0 -> 2mA -// 0x1 -> 4mA -// 0x2 -> 8mA -// 0x3 -> 12mA -#define PADS_BANK0_GPIO3_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO3_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO3_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO3_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO3_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO3_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO3_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO3_DRIVE_VALUE_8MA _u(0x2) -#define PADS_BANK0_GPIO3_DRIVE_VALUE_12MA _u(0x3) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO3_PUE -// Description : Pull up enable -#define PADS_BANK0_GPIO3_PUE_RESET _u(0x0) -#define PADS_BANK0_GPIO3_PUE_BITS _u(0x00000008) -#define PADS_BANK0_GPIO3_PUE_MSB _u(3) -#define PADS_BANK0_GPIO3_PUE_LSB _u(3) -#define PADS_BANK0_GPIO3_PUE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO3_PDE -// Description : Pull down enable -#define PADS_BANK0_GPIO3_PDE_RESET _u(0x1) -#define PADS_BANK0_GPIO3_PDE_BITS _u(0x00000004) -#define PADS_BANK0_GPIO3_PDE_MSB _u(2) -#define PADS_BANK0_GPIO3_PDE_LSB _u(2) -#define PADS_BANK0_GPIO3_PDE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO3_SCHMITT -// Description : Enable schmitt trigger -#define PADS_BANK0_GPIO3_SCHMITT_RESET _u(0x1) -#define PADS_BANK0_GPIO3_SCHMITT_BITS _u(0x00000002) -#define PADS_BANK0_GPIO3_SCHMITT_MSB _u(1) -#define PADS_BANK0_GPIO3_SCHMITT_LSB _u(1) -#define PADS_BANK0_GPIO3_SCHMITT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO3_SLEWFAST -// Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO3_SLEWFAST_RESET _u(0x0) -#define PADS_BANK0_GPIO3_SLEWFAST_BITS _u(0x00000001) -#define PADS_BANK0_GPIO3_SLEWFAST_MSB _u(0) -#define PADS_BANK0_GPIO3_SLEWFAST_LSB _u(0) -#define PADS_BANK0_GPIO3_SLEWFAST_ACCESS "RW" -// ============================================================================= -// Register : PADS_BANK0_GPIO4 -#define PADS_BANK0_GPIO4_OFFSET _u(0x00000014) -#define PADS_BANK0_GPIO4_BITS _u(0x000001ff) -#define PADS_BANK0_GPIO4_RESET _u(0x00000116) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO4_ISO -// Description : Pad isolation control. Remove this once the pad is configured -// by software. -#define PADS_BANK0_GPIO4_ISO_RESET _u(0x1) -#define PADS_BANK0_GPIO4_ISO_BITS _u(0x00000100) -#define PADS_BANK0_GPIO4_ISO_MSB _u(8) -#define PADS_BANK0_GPIO4_ISO_LSB _u(8) -#define PADS_BANK0_GPIO4_ISO_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO4_OD -// Description : Output disable. Has priority over output enable from -// peripherals -#define PADS_BANK0_GPIO4_OD_RESET _u(0x0) -#define PADS_BANK0_GPIO4_OD_BITS _u(0x00000080) -#define PADS_BANK0_GPIO4_OD_MSB _u(7) -#define PADS_BANK0_GPIO4_OD_LSB _u(7) -#define PADS_BANK0_GPIO4_OD_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO4_IE -// Description : Input enable -#define PADS_BANK0_GPIO4_IE_RESET _u(0x0) -#define PADS_BANK0_GPIO4_IE_BITS _u(0x00000040) -#define PADS_BANK0_GPIO4_IE_MSB _u(6) -#define PADS_BANK0_GPIO4_IE_LSB _u(6) -#define PADS_BANK0_GPIO4_IE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO4_DRIVE -// Description : Drive strength. -// 0x0 -> 2mA -// 0x1 -> 4mA -// 0x2 -> 8mA -// 0x3 -> 12mA -#define PADS_BANK0_GPIO4_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO4_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO4_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO4_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO4_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO4_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO4_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO4_DRIVE_VALUE_8MA _u(0x2) -#define PADS_BANK0_GPIO4_DRIVE_VALUE_12MA _u(0x3) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO4_PUE -// Description : Pull up enable -#define PADS_BANK0_GPIO4_PUE_RESET _u(0x0) -#define PADS_BANK0_GPIO4_PUE_BITS _u(0x00000008) -#define PADS_BANK0_GPIO4_PUE_MSB _u(3) -#define PADS_BANK0_GPIO4_PUE_LSB _u(3) -#define PADS_BANK0_GPIO4_PUE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO4_PDE -// Description : Pull down enable -#define PADS_BANK0_GPIO4_PDE_RESET _u(0x1) -#define PADS_BANK0_GPIO4_PDE_BITS _u(0x00000004) -#define PADS_BANK0_GPIO4_PDE_MSB _u(2) -#define PADS_BANK0_GPIO4_PDE_LSB _u(2) -#define PADS_BANK0_GPIO4_PDE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO4_SCHMITT -// Description : Enable schmitt trigger -#define PADS_BANK0_GPIO4_SCHMITT_RESET _u(0x1) -#define PADS_BANK0_GPIO4_SCHMITT_BITS _u(0x00000002) -#define PADS_BANK0_GPIO4_SCHMITT_MSB _u(1) -#define PADS_BANK0_GPIO4_SCHMITT_LSB _u(1) -#define PADS_BANK0_GPIO4_SCHMITT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO4_SLEWFAST -// Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO4_SLEWFAST_RESET _u(0x0) -#define PADS_BANK0_GPIO4_SLEWFAST_BITS _u(0x00000001) -#define PADS_BANK0_GPIO4_SLEWFAST_MSB _u(0) -#define PADS_BANK0_GPIO4_SLEWFAST_LSB _u(0) -#define PADS_BANK0_GPIO4_SLEWFAST_ACCESS "RW" -// ============================================================================= -// Register : PADS_BANK0_GPIO5 -#define PADS_BANK0_GPIO5_OFFSET _u(0x00000018) -#define PADS_BANK0_GPIO5_BITS _u(0x000001ff) -#define PADS_BANK0_GPIO5_RESET _u(0x00000116) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO5_ISO -// Description : Pad isolation control. Remove this once the pad is configured -// by software. -#define PADS_BANK0_GPIO5_ISO_RESET _u(0x1) -#define PADS_BANK0_GPIO5_ISO_BITS _u(0x00000100) -#define PADS_BANK0_GPIO5_ISO_MSB _u(8) -#define PADS_BANK0_GPIO5_ISO_LSB _u(8) -#define PADS_BANK0_GPIO5_ISO_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO5_OD -// Description : Output disable. Has priority over output enable from -// peripherals -#define PADS_BANK0_GPIO5_OD_RESET _u(0x0) -#define PADS_BANK0_GPIO5_OD_BITS _u(0x00000080) -#define PADS_BANK0_GPIO5_OD_MSB _u(7) -#define PADS_BANK0_GPIO5_OD_LSB _u(7) -#define PADS_BANK0_GPIO5_OD_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO5_IE -// Description : Input enable -#define PADS_BANK0_GPIO5_IE_RESET _u(0x0) -#define PADS_BANK0_GPIO5_IE_BITS _u(0x00000040) -#define PADS_BANK0_GPIO5_IE_MSB _u(6) -#define PADS_BANK0_GPIO5_IE_LSB _u(6) -#define PADS_BANK0_GPIO5_IE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO5_DRIVE -// Description : Drive strength. -// 0x0 -> 2mA -// 0x1 -> 4mA -// 0x2 -> 8mA -// 0x3 -> 12mA -#define PADS_BANK0_GPIO5_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO5_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO5_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO5_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO5_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO5_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO5_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO5_DRIVE_VALUE_8MA _u(0x2) -#define PADS_BANK0_GPIO5_DRIVE_VALUE_12MA _u(0x3) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO5_PUE -// Description : Pull up enable -#define PADS_BANK0_GPIO5_PUE_RESET _u(0x0) -#define PADS_BANK0_GPIO5_PUE_BITS _u(0x00000008) -#define PADS_BANK0_GPIO5_PUE_MSB _u(3) -#define PADS_BANK0_GPIO5_PUE_LSB _u(3) -#define PADS_BANK0_GPIO5_PUE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO5_PDE -// Description : Pull down enable -#define PADS_BANK0_GPIO5_PDE_RESET _u(0x1) -#define PADS_BANK0_GPIO5_PDE_BITS _u(0x00000004) -#define PADS_BANK0_GPIO5_PDE_MSB _u(2) -#define PADS_BANK0_GPIO5_PDE_LSB _u(2) -#define PADS_BANK0_GPIO5_PDE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO5_SCHMITT -// Description : Enable schmitt trigger -#define PADS_BANK0_GPIO5_SCHMITT_RESET _u(0x1) -#define PADS_BANK0_GPIO5_SCHMITT_BITS _u(0x00000002) -#define PADS_BANK0_GPIO5_SCHMITT_MSB _u(1) -#define PADS_BANK0_GPIO5_SCHMITT_LSB _u(1) -#define PADS_BANK0_GPIO5_SCHMITT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO5_SLEWFAST -// Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO5_SLEWFAST_RESET _u(0x0) -#define PADS_BANK0_GPIO5_SLEWFAST_BITS _u(0x00000001) -#define PADS_BANK0_GPIO5_SLEWFAST_MSB _u(0) -#define PADS_BANK0_GPIO5_SLEWFAST_LSB _u(0) -#define PADS_BANK0_GPIO5_SLEWFAST_ACCESS "RW" -// ============================================================================= -// Register : PADS_BANK0_GPIO6 -#define PADS_BANK0_GPIO6_OFFSET _u(0x0000001c) -#define PADS_BANK0_GPIO6_BITS _u(0x000001ff) -#define PADS_BANK0_GPIO6_RESET _u(0x00000116) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO6_ISO -// Description : Pad isolation control. Remove this once the pad is configured -// by software. -#define PADS_BANK0_GPIO6_ISO_RESET _u(0x1) -#define PADS_BANK0_GPIO6_ISO_BITS _u(0x00000100) -#define PADS_BANK0_GPIO6_ISO_MSB _u(8) -#define PADS_BANK0_GPIO6_ISO_LSB _u(8) -#define PADS_BANK0_GPIO6_ISO_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO6_OD -// Description : Output disable. Has priority over output enable from -// peripherals -#define PADS_BANK0_GPIO6_OD_RESET _u(0x0) -#define PADS_BANK0_GPIO6_OD_BITS _u(0x00000080) -#define PADS_BANK0_GPIO6_OD_MSB _u(7) -#define PADS_BANK0_GPIO6_OD_LSB _u(7) -#define PADS_BANK0_GPIO6_OD_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO6_IE -// Description : Input enable -#define PADS_BANK0_GPIO6_IE_RESET _u(0x0) -#define PADS_BANK0_GPIO6_IE_BITS _u(0x00000040) -#define PADS_BANK0_GPIO6_IE_MSB _u(6) -#define PADS_BANK0_GPIO6_IE_LSB _u(6) -#define PADS_BANK0_GPIO6_IE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO6_DRIVE -// Description : Drive strength. -// 0x0 -> 2mA -// 0x1 -> 4mA -// 0x2 -> 8mA -// 0x3 -> 12mA -#define PADS_BANK0_GPIO6_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO6_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO6_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO6_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO6_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO6_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO6_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO6_DRIVE_VALUE_8MA _u(0x2) -#define PADS_BANK0_GPIO6_DRIVE_VALUE_12MA _u(0x3) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO6_PUE -// Description : Pull up enable -#define PADS_BANK0_GPIO6_PUE_RESET _u(0x0) -#define PADS_BANK0_GPIO6_PUE_BITS _u(0x00000008) -#define PADS_BANK0_GPIO6_PUE_MSB _u(3) -#define PADS_BANK0_GPIO6_PUE_LSB _u(3) -#define PADS_BANK0_GPIO6_PUE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO6_PDE -// Description : Pull down enable -#define PADS_BANK0_GPIO6_PDE_RESET _u(0x1) -#define PADS_BANK0_GPIO6_PDE_BITS _u(0x00000004) -#define PADS_BANK0_GPIO6_PDE_MSB _u(2) -#define PADS_BANK0_GPIO6_PDE_LSB _u(2) -#define PADS_BANK0_GPIO6_PDE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO6_SCHMITT -// Description : Enable schmitt trigger -#define PADS_BANK0_GPIO6_SCHMITT_RESET _u(0x1) -#define PADS_BANK0_GPIO6_SCHMITT_BITS _u(0x00000002) -#define PADS_BANK0_GPIO6_SCHMITT_MSB _u(1) -#define PADS_BANK0_GPIO6_SCHMITT_LSB _u(1) -#define PADS_BANK0_GPIO6_SCHMITT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO6_SLEWFAST -// Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO6_SLEWFAST_RESET _u(0x0) -#define PADS_BANK0_GPIO6_SLEWFAST_BITS _u(0x00000001) -#define PADS_BANK0_GPIO6_SLEWFAST_MSB _u(0) -#define PADS_BANK0_GPIO6_SLEWFAST_LSB _u(0) -#define PADS_BANK0_GPIO6_SLEWFAST_ACCESS "RW" -// ============================================================================= -// Register : PADS_BANK0_GPIO7 -#define PADS_BANK0_GPIO7_OFFSET _u(0x00000020) -#define PADS_BANK0_GPIO7_BITS _u(0x000001ff) -#define PADS_BANK0_GPIO7_RESET _u(0x00000116) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO7_ISO -// Description : Pad isolation control. Remove this once the pad is configured -// by software. -#define PADS_BANK0_GPIO7_ISO_RESET _u(0x1) -#define PADS_BANK0_GPIO7_ISO_BITS _u(0x00000100) -#define PADS_BANK0_GPIO7_ISO_MSB _u(8) -#define PADS_BANK0_GPIO7_ISO_LSB _u(8) -#define PADS_BANK0_GPIO7_ISO_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO7_OD -// Description : Output disable. Has priority over output enable from -// peripherals -#define PADS_BANK0_GPIO7_OD_RESET _u(0x0) -#define PADS_BANK0_GPIO7_OD_BITS _u(0x00000080) -#define PADS_BANK0_GPIO7_OD_MSB _u(7) -#define PADS_BANK0_GPIO7_OD_LSB _u(7) -#define PADS_BANK0_GPIO7_OD_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO7_IE -// Description : Input enable -#define PADS_BANK0_GPIO7_IE_RESET _u(0x0) -#define PADS_BANK0_GPIO7_IE_BITS _u(0x00000040) -#define PADS_BANK0_GPIO7_IE_MSB _u(6) -#define PADS_BANK0_GPIO7_IE_LSB _u(6) -#define PADS_BANK0_GPIO7_IE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO7_DRIVE -// Description : Drive strength. -// 0x0 -> 2mA -// 0x1 -> 4mA -// 0x2 -> 8mA -// 0x3 -> 12mA -#define PADS_BANK0_GPIO7_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO7_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO7_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO7_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO7_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO7_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO7_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO7_DRIVE_VALUE_8MA _u(0x2) -#define PADS_BANK0_GPIO7_DRIVE_VALUE_12MA _u(0x3) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO7_PUE -// Description : Pull up enable -#define PADS_BANK0_GPIO7_PUE_RESET _u(0x0) -#define PADS_BANK0_GPIO7_PUE_BITS _u(0x00000008) -#define PADS_BANK0_GPIO7_PUE_MSB _u(3) -#define PADS_BANK0_GPIO7_PUE_LSB _u(3) -#define PADS_BANK0_GPIO7_PUE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO7_PDE -// Description : Pull down enable -#define PADS_BANK0_GPIO7_PDE_RESET _u(0x1) -#define PADS_BANK0_GPIO7_PDE_BITS _u(0x00000004) -#define PADS_BANK0_GPIO7_PDE_MSB _u(2) -#define PADS_BANK0_GPIO7_PDE_LSB _u(2) -#define PADS_BANK0_GPIO7_PDE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO7_SCHMITT -// Description : Enable schmitt trigger -#define PADS_BANK0_GPIO7_SCHMITT_RESET _u(0x1) -#define PADS_BANK0_GPIO7_SCHMITT_BITS _u(0x00000002) -#define PADS_BANK0_GPIO7_SCHMITT_MSB _u(1) -#define PADS_BANK0_GPIO7_SCHMITT_LSB _u(1) -#define PADS_BANK0_GPIO7_SCHMITT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO7_SLEWFAST -// Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO7_SLEWFAST_RESET _u(0x0) -#define PADS_BANK0_GPIO7_SLEWFAST_BITS _u(0x00000001) -#define PADS_BANK0_GPIO7_SLEWFAST_MSB _u(0) -#define PADS_BANK0_GPIO7_SLEWFAST_LSB _u(0) -#define PADS_BANK0_GPIO7_SLEWFAST_ACCESS "RW" -// ============================================================================= -// Register : PADS_BANK0_GPIO8 -#define PADS_BANK0_GPIO8_OFFSET _u(0x00000024) -#define PADS_BANK0_GPIO8_BITS _u(0x000001ff) -#define PADS_BANK0_GPIO8_RESET _u(0x00000116) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO8_ISO -// Description : Pad isolation control. Remove this once the pad is configured -// by software. -#define PADS_BANK0_GPIO8_ISO_RESET _u(0x1) -#define PADS_BANK0_GPIO8_ISO_BITS _u(0x00000100) -#define PADS_BANK0_GPIO8_ISO_MSB _u(8) -#define PADS_BANK0_GPIO8_ISO_LSB _u(8) -#define PADS_BANK0_GPIO8_ISO_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO8_OD -// Description : Output disable. Has priority over output enable from -// peripherals -#define PADS_BANK0_GPIO8_OD_RESET _u(0x0) -#define PADS_BANK0_GPIO8_OD_BITS _u(0x00000080) -#define PADS_BANK0_GPIO8_OD_MSB _u(7) -#define PADS_BANK0_GPIO8_OD_LSB _u(7) -#define PADS_BANK0_GPIO8_OD_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO8_IE -// Description : Input enable -#define PADS_BANK0_GPIO8_IE_RESET _u(0x0) -#define PADS_BANK0_GPIO8_IE_BITS _u(0x00000040) -#define PADS_BANK0_GPIO8_IE_MSB _u(6) -#define PADS_BANK0_GPIO8_IE_LSB _u(6) -#define PADS_BANK0_GPIO8_IE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO8_DRIVE -// Description : Drive strength. -// 0x0 -> 2mA -// 0x1 -> 4mA -// 0x2 -> 8mA -// 0x3 -> 12mA -#define PADS_BANK0_GPIO8_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO8_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO8_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO8_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO8_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO8_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO8_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO8_DRIVE_VALUE_8MA _u(0x2) -#define PADS_BANK0_GPIO8_DRIVE_VALUE_12MA _u(0x3) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO8_PUE -// Description : Pull up enable -#define PADS_BANK0_GPIO8_PUE_RESET _u(0x0) -#define PADS_BANK0_GPIO8_PUE_BITS _u(0x00000008) -#define PADS_BANK0_GPIO8_PUE_MSB _u(3) -#define PADS_BANK0_GPIO8_PUE_LSB _u(3) -#define PADS_BANK0_GPIO8_PUE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO8_PDE -// Description : Pull down enable -#define PADS_BANK0_GPIO8_PDE_RESET _u(0x1) -#define PADS_BANK0_GPIO8_PDE_BITS _u(0x00000004) -#define PADS_BANK0_GPIO8_PDE_MSB _u(2) -#define PADS_BANK0_GPIO8_PDE_LSB _u(2) -#define PADS_BANK0_GPIO8_PDE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO8_SCHMITT -// Description : Enable schmitt trigger -#define PADS_BANK0_GPIO8_SCHMITT_RESET _u(0x1) -#define PADS_BANK0_GPIO8_SCHMITT_BITS _u(0x00000002) -#define PADS_BANK0_GPIO8_SCHMITT_MSB _u(1) -#define PADS_BANK0_GPIO8_SCHMITT_LSB _u(1) -#define PADS_BANK0_GPIO8_SCHMITT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO8_SLEWFAST -// Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO8_SLEWFAST_RESET _u(0x0) -#define PADS_BANK0_GPIO8_SLEWFAST_BITS _u(0x00000001) -#define PADS_BANK0_GPIO8_SLEWFAST_MSB _u(0) -#define PADS_BANK0_GPIO8_SLEWFAST_LSB _u(0) -#define PADS_BANK0_GPIO8_SLEWFAST_ACCESS "RW" -// ============================================================================= -// Register : PADS_BANK0_GPIO9 -#define PADS_BANK0_GPIO9_OFFSET _u(0x00000028) -#define PADS_BANK0_GPIO9_BITS _u(0x000001ff) -#define PADS_BANK0_GPIO9_RESET _u(0x00000116) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO9_ISO -// Description : Pad isolation control. Remove this once the pad is configured -// by software. -#define PADS_BANK0_GPIO9_ISO_RESET _u(0x1) -#define PADS_BANK0_GPIO9_ISO_BITS _u(0x00000100) -#define PADS_BANK0_GPIO9_ISO_MSB _u(8) -#define PADS_BANK0_GPIO9_ISO_LSB _u(8) -#define PADS_BANK0_GPIO9_ISO_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO9_OD -// Description : Output disable. Has priority over output enable from -// peripherals -#define PADS_BANK0_GPIO9_OD_RESET _u(0x0) -#define PADS_BANK0_GPIO9_OD_BITS _u(0x00000080) -#define PADS_BANK0_GPIO9_OD_MSB _u(7) -#define PADS_BANK0_GPIO9_OD_LSB _u(7) -#define PADS_BANK0_GPIO9_OD_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO9_IE -// Description : Input enable -#define PADS_BANK0_GPIO9_IE_RESET _u(0x0) -#define PADS_BANK0_GPIO9_IE_BITS _u(0x00000040) -#define PADS_BANK0_GPIO9_IE_MSB _u(6) -#define PADS_BANK0_GPIO9_IE_LSB _u(6) -#define PADS_BANK0_GPIO9_IE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO9_DRIVE -// Description : Drive strength. -// 0x0 -> 2mA -// 0x1 -> 4mA -// 0x2 -> 8mA -// 0x3 -> 12mA -#define PADS_BANK0_GPIO9_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO9_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO9_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO9_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO9_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO9_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO9_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO9_DRIVE_VALUE_8MA _u(0x2) -#define PADS_BANK0_GPIO9_DRIVE_VALUE_12MA _u(0x3) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO9_PUE -// Description : Pull up enable -#define PADS_BANK0_GPIO9_PUE_RESET _u(0x0) -#define PADS_BANK0_GPIO9_PUE_BITS _u(0x00000008) -#define PADS_BANK0_GPIO9_PUE_MSB _u(3) -#define PADS_BANK0_GPIO9_PUE_LSB _u(3) -#define PADS_BANK0_GPIO9_PUE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO9_PDE -// Description : Pull down enable -#define PADS_BANK0_GPIO9_PDE_RESET _u(0x1) -#define PADS_BANK0_GPIO9_PDE_BITS _u(0x00000004) -#define PADS_BANK0_GPIO9_PDE_MSB _u(2) -#define PADS_BANK0_GPIO9_PDE_LSB _u(2) -#define PADS_BANK0_GPIO9_PDE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO9_SCHMITT -// Description : Enable schmitt trigger -#define PADS_BANK0_GPIO9_SCHMITT_RESET _u(0x1) -#define PADS_BANK0_GPIO9_SCHMITT_BITS _u(0x00000002) -#define PADS_BANK0_GPIO9_SCHMITT_MSB _u(1) -#define PADS_BANK0_GPIO9_SCHMITT_LSB _u(1) -#define PADS_BANK0_GPIO9_SCHMITT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO9_SLEWFAST -// Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO9_SLEWFAST_RESET _u(0x0) -#define PADS_BANK0_GPIO9_SLEWFAST_BITS _u(0x00000001) -#define PADS_BANK0_GPIO9_SLEWFAST_MSB _u(0) -#define PADS_BANK0_GPIO9_SLEWFAST_LSB _u(0) -#define PADS_BANK0_GPIO9_SLEWFAST_ACCESS "RW" -// ============================================================================= -// Register : PADS_BANK0_GPIO10 -#define PADS_BANK0_GPIO10_OFFSET _u(0x0000002c) -#define PADS_BANK0_GPIO10_BITS _u(0x000001ff) -#define PADS_BANK0_GPIO10_RESET _u(0x00000116) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO10_ISO -// Description : Pad isolation control. Remove this once the pad is configured -// by software. -#define PADS_BANK0_GPIO10_ISO_RESET _u(0x1) -#define PADS_BANK0_GPIO10_ISO_BITS _u(0x00000100) -#define PADS_BANK0_GPIO10_ISO_MSB _u(8) -#define PADS_BANK0_GPIO10_ISO_LSB _u(8) -#define PADS_BANK0_GPIO10_ISO_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO10_OD -// Description : Output disable. Has priority over output enable from -// peripherals -#define PADS_BANK0_GPIO10_OD_RESET _u(0x0) -#define PADS_BANK0_GPIO10_OD_BITS _u(0x00000080) -#define PADS_BANK0_GPIO10_OD_MSB _u(7) -#define PADS_BANK0_GPIO10_OD_LSB _u(7) -#define PADS_BANK0_GPIO10_OD_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO10_IE -// Description : Input enable -#define PADS_BANK0_GPIO10_IE_RESET _u(0x0) -#define PADS_BANK0_GPIO10_IE_BITS _u(0x00000040) -#define PADS_BANK0_GPIO10_IE_MSB _u(6) -#define PADS_BANK0_GPIO10_IE_LSB _u(6) -#define PADS_BANK0_GPIO10_IE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO10_DRIVE -// Description : Drive strength. -// 0x0 -> 2mA -// 0x1 -> 4mA -// 0x2 -> 8mA -// 0x3 -> 12mA -#define PADS_BANK0_GPIO10_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO10_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO10_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO10_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO10_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO10_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO10_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO10_DRIVE_VALUE_8MA _u(0x2) -#define PADS_BANK0_GPIO10_DRIVE_VALUE_12MA _u(0x3) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO10_PUE -// Description : Pull up enable -#define PADS_BANK0_GPIO10_PUE_RESET _u(0x0) -#define PADS_BANK0_GPIO10_PUE_BITS _u(0x00000008) -#define PADS_BANK0_GPIO10_PUE_MSB _u(3) -#define PADS_BANK0_GPIO10_PUE_LSB _u(3) -#define PADS_BANK0_GPIO10_PUE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO10_PDE -// Description : Pull down enable -#define PADS_BANK0_GPIO10_PDE_RESET _u(0x1) -#define PADS_BANK0_GPIO10_PDE_BITS _u(0x00000004) -#define PADS_BANK0_GPIO10_PDE_MSB _u(2) -#define PADS_BANK0_GPIO10_PDE_LSB _u(2) -#define PADS_BANK0_GPIO10_PDE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO10_SCHMITT -// Description : Enable schmitt trigger -#define PADS_BANK0_GPIO10_SCHMITT_RESET _u(0x1) -#define PADS_BANK0_GPIO10_SCHMITT_BITS _u(0x00000002) -#define PADS_BANK0_GPIO10_SCHMITT_MSB _u(1) -#define PADS_BANK0_GPIO10_SCHMITT_LSB _u(1) -#define PADS_BANK0_GPIO10_SCHMITT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO10_SLEWFAST -// Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO10_SLEWFAST_RESET _u(0x0) -#define PADS_BANK0_GPIO10_SLEWFAST_BITS _u(0x00000001) -#define PADS_BANK0_GPIO10_SLEWFAST_MSB _u(0) -#define PADS_BANK0_GPIO10_SLEWFAST_LSB _u(0) -#define PADS_BANK0_GPIO10_SLEWFAST_ACCESS "RW" -// ============================================================================= -// Register : PADS_BANK0_GPIO11 -#define PADS_BANK0_GPIO11_OFFSET _u(0x00000030) -#define PADS_BANK0_GPIO11_BITS _u(0x000001ff) -#define PADS_BANK0_GPIO11_RESET _u(0x00000116) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO11_ISO -// Description : Pad isolation control. Remove this once the pad is configured -// by software. -#define PADS_BANK0_GPIO11_ISO_RESET _u(0x1) -#define PADS_BANK0_GPIO11_ISO_BITS _u(0x00000100) -#define PADS_BANK0_GPIO11_ISO_MSB _u(8) -#define PADS_BANK0_GPIO11_ISO_LSB _u(8) -#define PADS_BANK0_GPIO11_ISO_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO11_OD -// Description : Output disable. Has priority over output enable from -// peripherals -#define PADS_BANK0_GPIO11_OD_RESET _u(0x0) -#define PADS_BANK0_GPIO11_OD_BITS _u(0x00000080) -#define PADS_BANK0_GPIO11_OD_MSB _u(7) -#define PADS_BANK0_GPIO11_OD_LSB _u(7) -#define PADS_BANK0_GPIO11_OD_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO11_IE -// Description : Input enable -#define PADS_BANK0_GPIO11_IE_RESET _u(0x0) -#define PADS_BANK0_GPIO11_IE_BITS _u(0x00000040) -#define PADS_BANK0_GPIO11_IE_MSB _u(6) -#define PADS_BANK0_GPIO11_IE_LSB _u(6) -#define PADS_BANK0_GPIO11_IE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO11_DRIVE -// Description : Drive strength. -// 0x0 -> 2mA -// 0x1 -> 4mA -// 0x2 -> 8mA -// 0x3 -> 12mA -#define PADS_BANK0_GPIO11_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO11_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO11_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO11_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO11_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO11_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO11_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO11_DRIVE_VALUE_8MA _u(0x2) -#define PADS_BANK0_GPIO11_DRIVE_VALUE_12MA _u(0x3) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO11_PUE -// Description : Pull up enable -#define PADS_BANK0_GPIO11_PUE_RESET _u(0x0) -#define PADS_BANK0_GPIO11_PUE_BITS _u(0x00000008) -#define PADS_BANK0_GPIO11_PUE_MSB _u(3) -#define PADS_BANK0_GPIO11_PUE_LSB _u(3) -#define PADS_BANK0_GPIO11_PUE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO11_PDE -// Description : Pull down enable -#define PADS_BANK0_GPIO11_PDE_RESET _u(0x1) -#define PADS_BANK0_GPIO11_PDE_BITS _u(0x00000004) -#define PADS_BANK0_GPIO11_PDE_MSB _u(2) -#define PADS_BANK0_GPIO11_PDE_LSB _u(2) -#define PADS_BANK0_GPIO11_PDE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO11_SCHMITT -// Description : Enable schmitt trigger -#define PADS_BANK0_GPIO11_SCHMITT_RESET _u(0x1) -#define PADS_BANK0_GPIO11_SCHMITT_BITS _u(0x00000002) -#define PADS_BANK0_GPIO11_SCHMITT_MSB _u(1) -#define PADS_BANK0_GPIO11_SCHMITT_LSB _u(1) -#define PADS_BANK0_GPIO11_SCHMITT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO11_SLEWFAST -// Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO11_SLEWFAST_RESET _u(0x0) -#define PADS_BANK0_GPIO11_SLEWFAST_BITS _u(0x00000001) -#define PADS_BANK0_GPIO11_SLEWFAST_MSB _u(0) -#define PADS_BANK0_GPIO11_SLEWFAST_LSB _u(0) -#define PADS_BANK0_GPIO11_SLEWFAST_ACCESS "RW" -// ============================================================================= -// Register : PADS_BANK0_GPIO12 -#define PADS_BANK0_GPIO12_OFFSET _u(0x00000034) -#define PADS_BANK0_GPIO12_BITS _u(0x000001ff) -#define PADS_BANK0_GPIO12_RESET _u(0x00000116) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO12_ISO -// Description : Pad isolation control. Remove this once the pad is configured -// by software. -#define PADS_BANK0_GPIO12_ISO_RESET _u(0x1) -#define PADS_BANK0_GPIO12_ISO_BITS _u(0x00000100) -#define PADS_BANK0_GPIO12_ISO_MSB _u(8) -#define PADS_BANK0_GPIO12_ISO_LSB _u(8) -#define PADS_BANK0_GPIO12_ISO_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO12_OD -// Description : Output disable. Has priority over output enable from -// peripherals -#define PADS_BANK0_GPIO12_OD_RESET _u(0x0) -#define PADS_BANK0_GPIO12_OD_BITS _u(0x00000080) -#define PADS_BANK0_GPIO12_OD_MSB _u(7) -#define PADS_BANK0_GPIO12_OD_LSB _u(7) -#define PADS_BANK0_GPIO12_OD_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO12_IE -// Description : Input enable -#define PADS_BANK0_GPIO12_IE_RESET _u(0x0) -#define PADS_BANK0_GPIO12_IE_BITS _u(0x00000040) -#define PADS_BANK0_GPIO12_IE_MSB _u(6) -#define PADS_BANK0_GPIO12_IE_LSB _u(6) -#define PADS_BANK0_GPIO12_IE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO12_DRIVE -// Description : Drive strength. -// 0x0 -> 2mA -// 0x1 -> 4mA -// 0x2 -> 8mA -// 0x3 -> 12mA -#define PADS_BANK0_GPIO12_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO12_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO12_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO12_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO12_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO12_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO12_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO12_DRIVE_VALUE_8MA _u(0x2) -#define PADS_BANK0_GPIO12_DRIVE_VALUE_12MA _u(0x3) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO12_PUE -// Description : Pull up enable -#define PADS_BANK0_GPIO12_PUE_RESET _u(0x0) -#define PADS_BANK0_GPIO12_PUE_BITS _u(0x00000008) -#define PADS_BANK0_GPIO12_PUE_MSB _u(3) -#define PADS_BANK0_GPIO12_PUE_LSB _u(3) -#define PADS_BANK0_GPIO12_PUE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO12_PDE -// Description : Pull down enable -#define PADS_BANK0_GPIO12_PDE_RESET _u(0x1) -#define PADS_BANK0_GPIO12_PDE_BITS _u(0x00000004) -#define PADS_BANK0_GPIO12_PDE_MSB _u(2) -#define PADS_BANK0_GPIO12_PDE_LSB _u(2) -#define PADS_BANK0_GPIO12_PDE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO12_SCHMITT -// Description : Enable schmitt trigger -#define PADS_BANK0_GPIO12_SCHMITT_RESET _u(0x1) -#define PADS_BANK0_GPIO12_SCHMITT_BITS _u(0x00000002) -#define PADS_BANK0_GPIO12_SCHMITT_MSB _u(1) -#define PADS_BANK0_GPIO12_SCHMITT_LSB _u(1) -#define PADS_BANK0_GPIO12_SCHMITT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO12_SLEWFAST -// Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO12_SLEWFAST_RESET _u(0x0) -#define PADS_BANK0_GPIO12_SLEWFAST_BITS _u(0x00000001) -#define PADS_BANK0_GPIO12_SLEWFAST_MSB _u(0) -#define PADS_BANK0_GPIO12_SLEWFAST_LSB _u(0) -#define PADS_BANK0_GPIO12_SLEWFAST_ACCESS "RW" -// ============================================================================= -// Register : PADS_BANK0_GPIO13 -#define PADS_BANK0_GPIO13_OFFSET _u(0x00000038) -#define PADS_BANK0_GPIO13_BITS _u(0x000001ff) -#define PADS_BANK0_GPIO13_RESET _u(0x00000116) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO13_ISO -// Description : Pad isolation control. Remove this once the pad is configured -// by software. -#define PADS_BANK0_GPIO13_ISO_RESET _u(0x1) -#define PADS_BANK0_GPIO13_ISO_BITS _u(0x00000100) -#define PADS_BANK0_GPIO13_ISO_MSB _u(8) -#define PADS_BANK0_GPIO13_ISO_LSB _u(8) -#define PADS_BANK0_GPIO13_ISO_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO13_OD -// Description : Output disable. Has priority over output enable from -// peripherals -#define PADS_BANK0_GPIO13_OD_RESET _u(0x0) -#define PADS_BANK0_GPIO13_OD_BITS _u(0x00000080) -#define PADS_BANK0_GPIO13_OD_MSB _u(7) -#define PADS_BANK0_GPIO13_OD_LSB _u(7) -#define PADS_BANK0_GPIO13_OD_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO13_IE -// Description : Input enable -#define PADS_BANK0_GPIO13_IE_RESET _u(0x0) -#define PADS_BANK0_GPIO13_IE_BITS _u(0x00000040) -#define PADS_BANK0_GPIO13_IE_MSB _u(6) -#define PADS_BANK0_GPIO13_IE_LSB _u(6) -#define PADS_BANK0_GPIO13_IE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO13_DRIVE -// Description : Drive strength. -// 0x0 -> 2mA -// 0x1 -> 4mA -// 0x2 -> 8mA -// 0x3 -> 12mA -#define PADS_BANK0_GPIO13_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO13_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO13_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO13_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO13_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO13_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO13_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO13_DRIVE_VALUE_8MA _u(0x2) -#define PADS_BANK0_GPIO13_DRIVE_VALUE_12MA _u(0x3) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO13_PUE -// Description : Pull up enable -#define PADS_BANK0_GPIO13_PUE_RESET _u(0x0) -#define PADS_BANK0_GPIO13_PUE_BITS _u(0x00000008) -#define PADS_BANK0_GPIO13_PUE_MSB _u(3) -#define PADS_BANK0_GPIO13_PUE_LSB _u(3) -#define PADS_BANK0_GPIO13_PUE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO13_PDE -// Description : Pull down enable -#define PADS_BANK0_GPIO13_PDE_RESET _u(0x1) -#define PADS_BANK0_GPIO13_PDE_BITS _u(0x00000004) -#define PADS_BANK0_GPIO13_PDE_MSB _u(2) -#define PADS_BANK0_GPIO13_PDE_LSB _u(2) -#define PADS_BANK0_GPIO13_PDE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO13_SCHMITT -// Description : Enable schmitt trigger -#define PADS_BANK0_GPIO13_SCHMITT_RESET _u(0x1) -#define PADS_BANK0_GPIO13_SCHMITT_BITS _u(0x00000002) -#define PADS_BANK0_GPIO13_SCHMITT_MSB _u(1) -#define PADS_BANK0_GPIO13_SCHMITT_LSB _u(1) -#define PADS_BANK0_GPIO13_SCHMITT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO13_SLEWFAST -// Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO13_SLEWFAST_RESET _u(0x0) -#define PADS_BANK0_GPIO13_SLEWFAST_BITS _u(0x00000001) -#define PADS_BANK0_GPIO13_SLEWFAST_MSB _u(0) -#define PADS_BANK0_GPIO13_SLEWFAST_LSB _u(0) -#define PADS_BANK0_GPIO13_SLEWFAST_ACCESS "RW" -// ============================================================================= -// Register : PADS_BANK0_GPIO14 -#define PADS_BANK0_GPIO14_OFFSET _u(0x0000003c) -#define PADS_BANK0_GPIO14_BITS _u(0x000001ff) -#define PADS_BANK0_GPIO14_RESET _u(0x00000116) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO14_ISO -// Description : Pad isolation control. Remove this once the pad is configured -// by software. -#define PADS_BANK0_GPIO14_ISO_RESET _u(0x1) -#define PADS_BANK0_GPIO14_ISO_BITS _u(0x00000100) -#define PADS_BANK0_GPIO14_ISO_MSB _u(8) -#define PADS_BANK0_GPIO14_ISO_LSB _u(8) -#define PADS_BANK0_GPIO14_ISO_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO14_OD -// Description : Output disable. Has priority over output enable from -// peripherals -#define PADS_BANK0_GPIO14_OD_RESET _u(0x0) -#define PADS_BANK0_GPIO14_OD_BITS _u(0x00000080) -#define PADS_BANK0_GPIO14_OD_MSB _u(7) -#define PADS_BANK0_GPIO14_OD_LSB _u(7) -#define PADS_BANK0_GPIO14_OD_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO14_IE -// Description : Input enable -#define PADS_BANK0_GPIO14_IE_RESET _u(0x0) -#define PADS_BANK0_GPIO14_IE_BITS _u(0x00000040) -#define PADS_BANK0_GPIO14_IE_MSB _u(6) -#define PADS_BANK0_GPIO14_IE_LSB _u(6) -#define PADS_BANK0_GPIO14_IE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO14_DRIVE -// Description : Drive strength. -// 0x0 -> 2mA -// 0x1 -> 4mA -// 0x2 -> 8mA -// 0x3 -> 12mA -#define PADS_BANK0_GPIO14_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO14_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO14_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO14_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO14_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO14_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO14_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO14_DRIVE_VALUE_8MA _u(0x2) -#define PADS_BANK0_GPIO14_DRIVE_VALUE_12MA _u(0x3) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO14_PUE -// Description : Pull up enable -#define PADS_BANK0_GPIO14_PUE_RESET _u(0x0) -#define PADS_BANK0_GPIO14_PUE_BITS _u(0x00000008) -#define PADS_BANK0_GPIO14_PUE_MSB _u(3) -#define PADS_BANK0_GPIO14_PUE_LSB _u(3) -#define PADS_BANK0_GPIO14_PUE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO14_PDE -// Description : Pull down enable -#define PADS_BANK0_GPIO14_PDE_RESET _u(0x1) -#define PADS_BANK0_GPIO14_PDE_BITS _u(0x00000004) -#define PADS_BANK0_GPIO14_PDE_MSB _u(2) -#define PADS_BANK0_GPIO14_PDE_LSB _u(2) -#define PADS_BANK0_GPIO14_PDE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO14_SCHMITT -// Description : Enable schmitt trigger -#define PADS_BANK0_GPIO14_SCHMITT_RESET _u(0x1) -#define PADS_BANK0_GPIO14_SCHMITT_BITS _u(0x00000002) -#define PADS_BANK0_GPIO14_SCHMITT_MSB _u(1) -#define PADS_BANK0_GPIO14_SCHMITT_LSB _u(1) -#define PADS_BANK0_GPIO14_SCHMITT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO14_SLEWFAST -// Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO14_SLEWFAST_RESET _u(0x0) -#define PADS_BANK0_GPIO14_SLEWFAST_BITS _u(0x00000001) -#define PADS_BANK0_GPIO14_SLEWFAST_MSB _u(0) -#define PADS_BANK0_GPIO14_SLEWFAST_LSB _u(0) -#define PADS_BANK0_GPIO14_SLEWFAST_ACCESS "RW" -// ============================================================================= -// Register : PADS_BANK0_GPIO15 -#define PADS_BANK0_GPIO15_OFFSET _u(0x00000040) -#define PADS_BANK0_GPIO15_BITS _u(0x000001ff) -#define PADS_BANK0_GPIO15_RESET _u(0x00000116) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO15_ISO -// Description : Pad isolation control. Remove this once the pad is configured -// by software. -#define PADS_BANK0_GPIO15_ISO_RESET _u(0x1) -#define PADS_BANK0_GPIO15_ISO_BITS _u(0x00000100) -#define PADS_BANK0_GPIO15_ISO_MSB _u(8) -#define PADS_BANK0_GPIO15_ISO_LSB _u(8) -#define PADS_BANK0_GPIO15_ISO_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO15_OD -// Description : Output disable. Has priority over output enable from -// peripherals -#define PADS_BANK0_GPIO15_OD_RESET _u(0x0) -#define PADS_BANK0_GPIO15_OD_BITS _u(0x00000080) -#define PADS_BANK0_GPIO15_OD_MSB _u(7) -#define PADS_BANK0_GPIO15_OD_LSB _u(7) -#define PADS_BANK0_GPIO15_OD_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO15_IE -// Description : Input enable -#define PADS_BANK0_GPIO15_IE_RESET _u(0x0) -#define PADS_BANK0_GPIO15_IE_BITS _u(0x00000040) -#define PADS_BANK0_GPIO15_IE_MSB _u(6) -#define PADS_BANK0_GPIO15_IE_LSB _u(6) -#define PADS_BANK0_GPIO15_IE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO15_DRIVE -// Description : Drive strength. -// 0x0 -> 2mA -// 0x1 -> 4mA -// 0x2 -> 8mA -// 0x3 -> 12mA -#define PADS_BANK0_GPIO15_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO15_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO15_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO15_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO15_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO15_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO15_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO15_DRIVE_VALUE_8MA _u(0x2) -#define PADS_BANK0_GPIO15_DRIVE_VALUE_12MA _u(0x3) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO15_PUE -// Description : Pull up enable -#define PADS_BANK0_GPIO15_PUE_RESET _u(0x0) -#define PADS_BANK0_GPIO15_PUE_BITS _u(0x00000008) -#define PADS_BANK0_GPIO15_PUE_MSB _u(3) -#define PADS_BANK0_GPIO15_PUE_LSB _u(3) -#define PADS_BANK0_GPIO15_PUE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO15_PDE -// Description : Pull down enable -#define PADS_BANK0_GPIO15_PDE_RESET _u(0x1) -#define PADS_BANK0_GPIO15_PDE_BITS _u(0x00000004) -#define PADS_BANK0_GPIO15_PDE_MSB _u(2) -#define PADS_BANK0_GPIO15_PDE_LSB _u(2) -#define PADS_BANK0_GPIO15_PDE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO15_SCHMITT -// Description : Enable schmitt trigger -#define PADS_BANK0_GPIO15_SCHMITT_RESET _u(0x1) -#define PADS_BANK0_GPIO15_SCHMITT_BITS _u(0x00000002) -#define PADS_BANK0_GPIO15_SCHMITT_MSB _u(1) -#define PADS_BANK0_GPIO15_SCHMITT_LSB _u(1) -#define PADS_BANK0_GPIO15_SCHMITT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO15_SLEWFAST -// Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO15_SLEWFAST_RESET _u(0x0) -#define PADS_BANK0_GPIO15_SLEWFAST_BITS _u(0x00000001) -#define PADS_BANK0_GPIO15_SLEWFAST_MSB _u(0) -#define PADS_BANK0_GPIO15_SLEWFAST_LSB _u(0) -#define PADS_BANK0_GPIO15_SLEWFAST_ACCESS "RW" -// ============================================================================= -// Register : PADS_BANK0_GPIO16 -#define PADS_BANK0_GPIO16_OFFSET _u(0x00000044) -#define PADS_BANK0_GPIO16_BITS _u(0x000001ff) -#define PADS_BANK0_GPIO16_RESET _u(0x00000116) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO16_ISO -// Description : Pad isolation control. Remove this once the pad is configured -// by software. -#define PADS_BANK0_GPIO16_ISO_RESET _u(0x1) -#define PADS_BANK0_GPIO16_ISO_BITS _u(0x00000100) -#define PADS_BANK0_GPIO16_ISO_MSB _u(8) -#define PADS_BANK0_GPIO16_ISO_LSB _u(8) -#define PADS_BANK0_GPIO16_ISO_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO16_OD -// Description : Output disable. Has priority over output enable from -// peripherals -#define PADS_BANK0_GPIO16_OD_RESET _u(0x0) -#define PADS_BANK0_GPIO16_OD_BITS _u(0x00000080) -#define PADS_BANK0_GPIO16_OD_MSB _u(7) -#define PADS_BANK0_GPIO16_OD_LSB _u(7) -#define PADS_BANK0_GPIO16_OD_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO16_IE -// Description : Input enable -#define PADS_BANK0_GPIO16_IE_RESET _u(0x0) -#define PADS_BANK0_GPIO16_IE_BITS _u(0x00000040) -#define PADS_BANK0_GPIO16_IE_MSB _u(6) -#define PADS_BANK0_GPIO16_IE_LSB _u(6) -#define PADS_BANK0_GPIO16_IE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO16_DRIVE -// Description : Drive strength. -// 0x0 -> 2mA -// 0x1 -> 4mA -// 0x2 -> 8mA -// 0x3 -> 12mA -#define PADS_BANK0_GPIO16_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO16_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO16_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO16_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO16_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO16_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO16_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO16_DRIVE_VALUE_8MA _u(0x2) -#define PADS_BANK0_GPIO16_DRIVE_VALUE_12MA _u(0x3) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO16_PUE -// Description : Pull up enable -#define PADS_BANK0_GPIO16_PUE_RESET _u(0x0) -#define PADS_BANK0_GPIO16_PUE_BITS _u(0x00000008) -#define PADS_BANK0_GPIO16_PUE_MSB _u(3) -#define PADS_BANK0_GPIO16_PUE_LSB _u(3) -#define PADS_BANK0_GPIO16_PUE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO16_PDE -// Description : Pull down enable -#define PADS_BANK0_GPIO16_PDE_RESET _u(0x1) -#define PADS_BANK0_GPIO16_PDE_BITS _u(0x00000004) -#define PADS_BANK0_GPIO16_PDE_MSB _u(2) -#define PADS_BANK0_GPIO16_PDE_LSB _u(2) -#define PADS_BANK0_GPIO16_PDE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO16_SCHMITT -// Description : Enable schmitt trigger -#define PADS_BANK0_GPIO16_SCHMITT_RESET _u(0x1) -#define PADS_BANK0_GPIO16_SCHMITT_BITS _u(0x00000002) -#define PADS_BANK0_GPIO16_SCHMITT_MSB _u(1) -#define PADS_BANK0_GPIO16_SCHMITT_LSB _u(1) -#define PADS_BANK0_GPIO16_SCHMITT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO16_SLEWFAST -// Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO16_SLEWFAST_RESET _u(0x0) -#define PADS_BANK0_GPIO16_SLEWFAST_BITS _u(0x00000001) -#define PADS_BANK0_GPIO16_SLEWFAST_MSB _u(0) -#define PADS_BANK0_GPIO16_SLEWFAST_LSB _u(0) -#define PADS_BANK0_GPIO16_SLEWFAST_ACCESS "RW" -// ============================================================================= -// Register : PADS_BANK0_GPIO17 -#define PADS_BANK0_GPIO17_OFFSET _u(0x00000048) -#define PADS_BANK0_GPIO17_BITS _u(0x000001ff) -#define PADS_BANK0_GPIO17_RESET _u(0x00000116) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO17_ISO -// Description : Pad isolation control. Remove this once the pad is configured -// by software. -#define PADS_BANK0_GPIO17_ISO_RESET _u(0x1) -#define PADS_BANK0_GPIO17_ISO_BITS _u(0x00000100) -#define PADS_BANK0_GPIO17_ISO_MSB _u(8) -#define PADS_BANK0_GPIO17_ISO_LSB _u(8) -#define PADS_BANK0_GPIO17_ISO_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO17_OD -// Description : Output disable. Has priority over output enable from -// peripherals -#define PADS_BANK0_GPIO17_OD_RESET _u(0x0) -#define PADS_BANK0_GPIO17_OD_BITS _u(0x00000080) -#define PADS_BANK0_GPIO17_OD_MSB _u(7) -#define PADS_BANK0_GPIO17_OD_LSB _u(7) -#define PADS_BANK0_GPIO17_OD_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO17_IE -// Description : Input enable -#define PADS_BANK0_GPIO17_IE_RESET _u(0x0) -#define PADS_BANK0_GPIO17_IE_BITS _u(0x00000040) -#define PADS_BANK0_GPIO17_IE_MSB _u(6) -#define PADS_BANK0_GPIO17_IE_LSB _u(6) -#define PADS_BANK0_GPIO17_IE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO17_DRIVE -// Description : Drive strength. -// 0x0 -> 2mA -// 0x1 -> 4mA -// 0x2 -> 8mA -// 0x3 -> 12mA -#define PADS_BANK0_GPIO17_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO17_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO17_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO17_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO17_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO17_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO17_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO17_DRIVE_VALUE_8MA _u(0x2) -#define PADS_BANK0_GPIO17_DRIVE_VALUE_12MA _u(0x3) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO17_PUE -// Description : Pull up enable -#define PADS_BANK0_GPIO17_PUE_RESET _u(0x0) -#define PADS_BANK0_GPIO17_PUE_BITS _u(0x00000008) -#define PADS_BANK0_GPIO17_PUE_MSB _u(3) -#define PADS_BANK0_GPIO17_PUE_LSB _u(3) -#define PADS_BANK0_GPIO17_PUE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO17_PDE -// Description : Pull down enable -#define PADS_BANK0_GPIO17_PDE_RESET _u(0x1) -#define PADS_BANK0_GPIO17_PDE_BITS _u(0x00000004) -#define PADS_BANK0_GPIO17_PDE_MSB _u(2) -#define PADS_BANK0_GPIO17_PDE_LSB _u(2) -#define PADS_BANK0_GPIO17_PDE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO17_SCHMITT -// Description : Enable schmitt trigger -#define PADS_BANK0_GPIO17_SCHMITT_RESET _u(0x1) -#define PADS_BANK0_GPIO17_SCHMITT_BITS _u(0x00000002) -#define PADS_BANK0_GPIO17_SCHMITT_MSB _u(1) -#define PADS_BANK0_GPIO17_SCHMITT_LSB _u(1) -#define PADS_BANK0_GPIO17_SCHMITT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO17_SLEWFAST -// Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO17_SLEWFAST_RESET _u(0x0) -#define PADS_BANK0_GPIO17_SLEWFAST_BITS _u(0x00000001) -#define PADS_BANK0_GPIO17_SLEWFAST_MSB _u(0) -#define PADS_BANK0_GPIO17_SLEWFAST_LSB _u(0) -#define PADS_BANK0_GPIO17_SLEWFAST_ACCESS "RW" -// ============================================================================= -// Register : PADS_BANK0_GPIO18 -#define PADS_BANK0_GPIO18_OFFSET _u(0x0000004c) -#define PADS_BANK0_GPIO18_BITS _u(0x000001ff) -#define PADS_BANK0_GPIO18_RESET _u(0x00000116) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO18_ISO -// Description : Pad isolation control. Remove this once the pad is configured -// by software. -#define PADS_BANK0_GPIO18_ISO_RESET _u(0x1) -#define PADS_BANK0_GPIO18_ISO_BITS _u(0x00000100) -#define PADS_BANK0_GPIO18_ISO_MSB _u(8) -#define PADS_BANK0_GPIO18_ISO_LSB _u(8) -#define PADS_BANK0_GPIO18_ISO_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO18_OD -// Description : Output disable. Has priority over output enable from -// peripherals -#define PADS_BANK0_GPIO18_OD_RESET _u(0x0) -#define PADS_BANK0_GPIO18_OD_BITS _u(0x00000080) -#define PADS_BANK0_GPIO18_OD_MSB _u(7) -#define PADS_BANK0_GPIO18_OD_LSB _u(7) -#define PADS_BANK0_GPIO18_OD_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO18_IE -// Description : Input enable -#define PADS_BANK0_GPIO18_IE_RESET _u(0x0) -#define PADS_BANK0_GPIO18_IE_BITS _u(0x00000040) -#define PADS_BANK0_GPIO18_IE_MSB _u(6) -#define PADS_BANK0_GPIO18_IE_LSB _u(6) -#define PADS_BANK0_GPIO18_IE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO18_DRIVE -// Description : Drive strength. -// 0x0 -> 2mA -// 0x1 -> 4mA -// 0x2 -> 8mA -// 0x3 -> 12mA -#define PADS_BANK0_GPIO18_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO18_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO18_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO18_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO18_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO18_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO18_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO18_DRIVE_VALUE_8MA _u(0x2) -#define PADS_BANK0_GPIO18_DRIVE_VALUE_12MA _u(0x3) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO18_PUE -// Description : Pull up enable -#define PADS_BANK0_GPIO18_PUE_RESET _u(0x0) -#define PADS_BANK0_GPIO18_PUE_BITS _u(0x00000008) -#define PADS_BANK0_GPIO18_PUE_MSB _u(3) -#define PADS_BANK0_GPIO18_PUE_LSB _u(3) -#define PADS_BANK0_GPIO18_PUE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO18_PDE -// Description : Pull down enable -#define PADS_BANK0_GPIO18_PDE_RESET _u(0x1) -#define PADS_BANK0_GPIO18_PDE_BITS _u(0x00000004) -#define PADS_BANK0_GPIO18_PDE_MSB _u(2) -#define PADS_BANK0_GPIO18_PDE_LSB _u(2) -#define PADS_BANK0_GPIO18_PDE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO18_SCHMITT -// Description : Enable schmitt trigger -#define PADS_BANK0_GPIO18_SCHMITT_RESET _u(0x1) -#define PADS_BANK0_GPIO18_SCHMITT_BITS _u(0x00000002) -#define PADS_BANK0_GPIO18_SCHMITT_MSB _u(1) -#define PADS_BANK0_GPIO18_SCHMITT_LSB _u(1) -#define PADS_BANK0_GPIO18_SCHMITT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO18_SLEWFAST -// Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO18_SLEWFAST_RESET _u(0x0) -#define PADS_BANK0_GPIO18_SLEWFAST_BITS _u(0x00000001) -#define PADS_BANK0_GPIO18_SLEWFAST_MSB _u(0) -#define PADS_BANK0_GPIO18_SLEWFAST_LSB _u(0) -#define PADS_BANK0_GPIO18_SLEWFAST_ACCESS "RW" -// ============================================================================= -// Register : PADS_BANK0_GPIO19 -#define PADS_BANK0_GPIO19_OFFSET _u(0x00000050) -#define PADS_BANK0_GPIO19_BITS _u(0x000001ff) -#define PADS_BANK0_GPIO19_RESET _u(0x00000116) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO19_ISO -// Description : Pad isolation control. Remove this once the pad is configured -// by software. -#define PADS_BANK0_GPIO19_ISO_RESET _u(0x1) -#define PADS_BANK0_GPIO19_ISO_BITS _u(0x00000100) -#define PADS_BANK0_GPIO19_ISO_MSB _u(8) -#define PADS_BANK0_GPIO19_ISO_LSB _u(8) -#define PADS_BANK0_GPIO19_ISO_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO19_OD -// Description : Output disable. Has priority over output enable from -// peripherals -#define PADS_BANK0_GPIO19_OD_RESET _u(0x0) -#define PADS_BANK0_GPIO19_OD_BITS _u(0x00000080) -#define PADS_BANK0_GPIO19_OD_MSB _u(7) -#define PADS_BANK0_GPIO19_OD_LSB _u(7) -#define PADS_BANK0_GPIO19_OD_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO19_IE -// Description : Input enable -#define PADS_BANK0_GPIO19_IE_RESET _u(0x0) -#define PADS_BANK0_GPIO19_IE_BITS _u(0x00000040) -#define PADS_BANK0_GPIO19_IE_MSB _u(6) -#define PADS_BANK0_GPIO19_IE_LSB _u(6) -#define PADS_BANK0_GPIO19_IE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO19_DRIVE -// Description : Drive strength. -// 0x0 -> 2mA -// 0x1 -> 4mA -// 0x2 -> 8mA -// 0x3 -> 12mA -#define PADS_BANK0_GPIO19_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO19_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO19_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO19_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO19_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO19_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO19_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO19_DRIVE_VALUE_8MA _u(0x2) -#define PADS_BANK0_GPIO19_DRIVE_VALUE_12MA _u(0x3) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO19_PUE -// Description : Pull up enable -#define PADS_BANK0_GPIO19_PUE_RESET _u(0x0) -#define PADS_BANK0_GPIO19_PUE_BITS _u(0x00000008) -#define PADS_BANK0_GPIO19_PUE_MSB _u(3) -#define PADS_BANK0_GPIO19_PUE_LSB _u(3) -#define PADS_BANK0_GPIO19_PUE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO19_PDE -// Description : Pull down enable -#define PADS_BANK0_GPIO19_PDE_RESET _u(0x1) -#define PADS_BANK0_GPIO19_PDE_BITS _u(0x00000004) -#define PADS_BANK0_GPIO19_PDE_MSB _u(2) -#define PADS_BANK0_GPIO19_PDE_LSB _u(2) -#define PADS_BANK0_GPIO19_PDE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO19_SCHMITT -// Description : Enable schmitt trigger -#define PADS_BANK0_GPIO19_SCHMITT_RESET _u(0x1) -#define PADS_BANK0_GPIO19_SCHMITT_BITS _u(0x00000002) -#define PADS_BANK0_GPIO19_SCHMITT_MSB _u(1) -#define PADS_BANK0_GPIO19_SCHMITT_LSB _u(1) -#define PADS_BANK0_GPIO19_SCHMITT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO19_SLEWFAST -// Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO19_SLEWFAST_RESET _u(0x0) -#define PADS_BANK0_GPIO19_SLEWFAST_BITS _u(0x00000001) -#define PADS_BANK0_GPIO19_SLEWFAST_MSB _u(0) -#define PADS_BANK0_GPIO19_SLEWFAST_LSB _u(0) -#define PADS_BANK0_GPIO19_SLEWFAST_ACCESS "RW" -// ============================================================================= -// Register : PADS_BANK0_GPIO20 -#define PADS_BANK0_GPIO20_OFFSET _u(0x00000054) -#define PADS_BANK0_GPIO20_BITS _u(0x000001ff) -#define PADS_BANK0_GPIO20_RESET _u(0x00000116) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO20_ISO -// Description : Pad isolation control. Remove this once the pad is configured -// by software. -#define PADS_BANK0_GPIO20_ISO_RESET _u(0x1) -#define PADS_BANK0_GPIO20_ISO_BITS _u(0x00000100) -#define PADS_BANK0_GPIO20_ISO_MSB _u(8) -#define PADS_BANK0_GPIO20_ISO_LSB _u(8) -#define PADS_BANK0_GPIO20_ISO_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO20_OD -// Description : Output disable. Has priority over output enable from -// peripherals -#define PADS_BANK0_GPIO20_OD_RESET _u(0x0) -#define PADS_BANK0_GPIO20_OD_BITS _u(0x00000080) -#define PADS_BANK0_GPIO20_OD_MSB _u(7) -#define PADS_BANK0_GPIO20_OD_LSB _u(7) -#define PADS_BANK0_GPIO20_OD_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO20_IE -// Description : Input enable -#define PADS_BANK0_GPIO20_IE_RESET _u(0x0) -#define PADS_BANK0_GPIO20_IE_BITS _u(0x00000040) -#define PADS_BANK0_GPIO20_IE_MSB _u(6) -#define PADS_BANK0_GPIO20_IE_LSB _u(6) -#define PADS_BANK0_GPIO20_IE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO20_DRIVE -// Description : Drive strength. -// 0x0 -> 2mA -// 0x1 -> 4mA -// 0x2 -> 8mA -// 0x3 -> 12mA -#define PADS_BANK0_GPIO20_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO20_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO20_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO20_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO20_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO20_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO20_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO20_DRIVE_VALUE_8MA _u(0x2) -#define PADS_BANK0_GPIO20_DRIVE_VALUE_12MA _u(0x3) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO20_PUE -// Description : Pull up enable -#define PADS_BANK0_GPIO20_PUE_RESET _u(0x0) -#define PADS_BANK0_GPIO20_PUE_BITS _u(0x00000008) -#define PADS_BANK0_GPIO20_PUE_MSB _u(3) -#define PADS_BANK0_GPIO20_PUE_LSB _u(3) -#define PADS_BANK0_GPIO20_PUE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO20_PDE -// Description : Pull down enable -#define PADS_BANK0_GPIO20_PDE_RESET _u(0x1) -#define PADS_BANK0_GPIO20_PDE_BITS _u(0x00000004) -#define PADS_BANK0_GPIO20_PDE_MSB _u(2) -#define PADS_BANK0_GPIO20_PDE_LSB _u(2) -#define PADS_BANK0_GPIO20_PDE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO20_SCHMITT -// Description : Enable schmitt trigger -#define PADS_BANK0_GPIO20_SCHMITT_RESET _u(0x1) -#define PADS_BANK0_GPIO20_SCHMITT_BITS _u(0x00000002) -#define PADS_BANK0_GPIO20_SCHMITT_MSB _u(1) -#define PADS_BANK0_GPIO20_SCHMITT_LSB _u(1) -#define PADS_BANK0_GPIO20_SCHMITT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO20_SLEWFAST -// Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO20_SLEWFAST_RESET _u(0x0) -#define PADS_BANK0_GPIO20_SLEWFAST_BITS _u(0x00000001) -#define PADS_BANK0_GPIO20_SLEWFAST_MSB _u(0) -#define PADS_BANK0_GPIO20_SLEWFAST_LSB _u(0) -#define PADS_BANK0_GPIO20_SLEWFAST_ACCESS "RW" -// ============================================================================= -// Register : PADS_BANK0_GPIO21 -#define PADS_BANK0_GPIO21_OFFSET _u(0x00000058) -#define PADS_BANK0_GPIO21_BITS _u(0x000001ff) -#define PADS_BANK0_GPIO21_RESET _u(0x00000116) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO21_ISO -// Description : Pad isolation control. Remove this once the pad is configured -// by software. -#define PADS_BANK0_GPIO21_ISO_RESET _u(0x1) -#define PADS_BANK0_GPIO21_ISO_BITS _u(0x00000100) -#define PADS_BANK0_GPIO21_ISO_MSB _u(8) -#define PADS_BANK0_GPIO21_ISO_LSB _u(8) -#define PADS_BANK0_GPIO21_ISO_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO21_OD -// Description : Output disable. Has priority over output enable from -// peripherals -#define PADS_BANK0_GPIO21_OD_RESET _u(0x0) -#define PADS_BANK0_GPIO21_OD_BITS _u(0x00000080) -#define PADS_BANK0_GPIO21_OD_MSB _u(7) -#define PADS_BANK0_GPIO21_OD_LSB _u(7) -#define PADS_BANK0_GPIO21_OD_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO21_IE -// Description : Input enable -#define PADS_BANK0_GPIO21_IE_RESET _u(0x0) -#define PADS_BANK0_GPIO21_IE_BITS _u(0x00000040) -#define PADS_BANK0_GPIO21_IE_MSB _u(6) -#define PADS_BANK0_GPIO21_IE_LSB _u(6) -#define PADS_BANK0_GPIO21_IE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO21_DRIVE -// Description : Drive strength. -// 0x0 -> 2mA -// 0x1 -> 4mA -// 0x2 -> 8mA -// 0x3 -> 12mA -#define PADS_BANK0_GPIO21_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO21_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO21_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO21_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO21_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO21_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO21_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO21_DRIVE_VALUE_8MA _u(0x2) -#define PADS_BANK0_GPIO21_DRIVE_VALUE_12MA _u(0x3) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO21_PUE -// Description : Pull up enable -#define PADS_BANK0_GPIO21_PUE_RESET _u(0x0) -#define PADS_BANK0_GPIO21_PUE_BITS _u(0x00000008) -#define PADS_BANK0_GPIO21_PUE_MSB _u(3) -#define PADS_BANK0_GPIO21_PUE_LSB _u(3) -#define PADS_BANK0_GPIO21_PUE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO21_PDE -// Description : Pull down enable -#define PADS_BANK0_GPIO21_PDE_RESET _u(0x1) -#define PADS_BANK0_GPIO21_PDE_BITS _u(0x00000004) -#define PADS_BANK0_GPIO21_PDE_MSB _u(2) -#define PADS_BANK0_GPIO21_PDE_LSB _u(2) -#define PADS_BANK0_GPIO21_PDE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO21_SCHMITT -// Description : Enable schmitt trigger -#define PADS_BANK0_GPIO21_SCHMITT_RESET _u(0x1) -#define PADS_BANK0_GPIO21_SCHMITT_BITS _u(0x00000002) -#define PADS_BANK0_GPIO21_SCHMITT_MSB _u(1) -#define PADS_BANK0_GPIO21_SCHMITT_LSB _u(1) -#define PADS_BANK0_GPIO21_SCHMITT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO21_SLEWFAST -// Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO21_SLEWFAST_RESET _u(0x0) -#define PADS_BANK0_GPIO21_SLEWFAST_BITS _u(0x00000001) -#define PADS_BANK0_GPIO21_SLEWFAST_MSB _u(0) -#define PADS_BANK0_GPIO21_SLEWFAST_LSB _u(0) -#define PADS_BANK0_GPIO21_SLEWFAST_ACCESS "RW" -// ============================================================================= -// Register : PADS_BANK0_GPIO22 -#define PADS_BANK0_GPIO22_OFFSET _u(0x0000005c) -#define PADS_BANK0_GPIO22_BITS _u(0x000001ff) -#define PADS_BANK0_GPIO22_RESET _u(0x00000116) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO22_ISO -// Description : Pad isolation control. Remove this once the pad is configured -// by software. -#define PADS_BANK0_GPIO22_ISO_RESET _u(0x1) -#define PADS_BANK0_GPIO22_ISO_BITS _u(0x00000100) -#define PADS_BANK0_GPIO22_ISO_MSB _u(8) -#define PADS_BANK0_GPIO22_ISO_LSB _u(8) -#define PADS_BANK0_GPIO22_ISO_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO22_OD -// Description : Output disable. Has priority over output enable from -// peripherals -#define PADS_BANK0_GPIO22_OD_RESET _u(0x0) -#define PADS_BANK0_GPIO22_OD_BITS _u(0x00000080) -#define PADS_BANK0_GPIO22_OD_MSB _u(7) -#define PADS_BANK0_GPIO22_OD_LSB _u(7) -#define PADS_BANK0_GPIO22_OD_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO22_IE -// Description : Input enable -#define PADS_BANK0_GPIO22_IE_RESET _u(0x0) -#define PADS_BANK0_GPIO22_IE_BITS _u(0x00000040) -#define PADS_BANK0_GPIO22_IE_MSB _u(6) -#define PADS_BANK0_GPIO22_IE_LSB _u(6) -#define PADS_BANK0_GPIO22_IE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO22_DRIVE -// Description : Drive strength. -// 0x0 -> 2mA -// 0x1 -> 4mA -// 0x2 -> 8mA -// 0x3 -> 12mA -#define PADS_BANK0_GPIO22_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO22_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO22_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO22_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO22_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO22_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO22_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO22_DRIVE_VALUE_8MA _u(0x2) -#define PADS_BANK0_GPIO22_DRIVE_VALUE_12MA _u(0x3) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO22_PUE -// Description : Pull up enable -#define PADS_BANK0_GPIO22_PUE_RESET _u(0x0) -#define PADS_BANK0_GPIO22_PUE_BITS _u(0x00000008) -#define PADS_BANK0_GPIO22_PUE_MSB _u(3) -#define PADS_BANK0_GPIO22_PUE_LSB _u(3) -#define PADS_BANK0_GPIO22_PUE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO22_PDE -// Description : Pull down enable -#define PADS_BANK0_GPIO22_PDE_RESET _u(0x1) -#define PADS_BANK0_GPIO22_PDE_BITS _u(0x00000004) -#define PADS_BANK0_GPIO22_PDE_MSB _u(2) -#define PADS_BANK0_GPIO22_PDE_LSB _u(2) -#define PADS_BANK0_GPIO22_PDE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO22_SCHMITT -// Description : Enable schmitt trigger -#define PADS_BANK0_GPIO22_SCHMITT_RESET _u(0x1) -#define PADS_BANK0_GPIO22_SCHMITT_BITS _u(0x00000002) -#define PADS_BANK0_GPIO22_SCHMITT_MSB _u(1) -#define PADS_BANK0_GPIO22_SCHMITT_LSB _u(1) -#define PADS_BANK0_GPIO22_SCHMITT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO22_SLEWFAST -// Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO22_SLEWFAST_RESET _u(0x0) -#define PADS_BANK0_GPIO22_SLEWFAST_BITS _u(0x00000001) -#define PADS_BANK0_GPIO22_SLEWFAST_MSB _u(0) -#define PADS_BANK0_GPIO22_SLEWFAST_LSB _u(0) -#define PADS_BANK0_GPIO22_SLEWFAST_ACCESS "RW" -// ============================================================================= -// Register : PADS_BANK0_GPIO23 -#define PADS_BANK0_GPIO23_OFFSET _u(0x00000060) -#define PADS_BANK0_GPIO23_BITS _u(0x000001ff) -#define PADS_BANK0_GPIO23_RESET _u(0x00000116) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO23_ISO -// Description : Pad isolation control. Remove this once the pad is configured -// by software. -#define PADS_BANK0_GPIO23_ISO_RESET _u(0x1) -#define PADS_BANK0_GPIO23_ISO_BITS _u(0x00000100) -#define PADS_BANK0_GPIO23_ISO_MSB _u(8) -#define PADS_BANK0_GPIO23_ISO_LSB _u(8) -#define PADS_BANK0_GPIO23_ISO_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO23_OD -// Description : Output disable. Has priority over output enable from -// peripherals -#define PADS_BANK0_GPIO23_OD_RESET _u(0x0) -#define PADS_BANK0_GPIO23_OD_BITS _u(0x00000080) -#define PADS_BANK0_GPIO23_OD_MSB _u(7) -#define PADS_BANK0_GPIO23_OD_LSB _u(7) -#define PADS_BANK0_GPIO23_OD_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO23_IE -// Description : Input enable -#define PADS_BANK0_GPIO23_IE_RESET _u(0x0) -#define PADS_BANK0_GPIO23_IE_BITS _u(0x00000040) -#define PADS_BANK0_GPIO23_IE_MSB _u(6) -#define PADS_BANK0_GPIO23_IE_LSB _u(6) -#define PADS_BANK0_GPIO23_IE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO23_DRIVE -// Description : Drive strength. -// 0x0 -> 2mA -// 0x1 -> 4mA -// 0x2 -> 8mA -// 0x3 -> 12mA -#define PADS_BANK0_GPIO23_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO23_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO23_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO23_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO23_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO23_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO23_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO23_DRIVE_VALUE_8MA _u(0x2) -#define PADS_BANK0_GPIO23_DRIVE_VALUE_12MA _u(0x3) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO23_PUE -// Description : Pull up enable -#define PADS_BANK0_GPIO23_PUE_RESET _u(0x0) -#define PADS_BANK0_GPIO23_PUE_BITS _u(0x00000008) -#define PADS_BANK0_GPIO23_PUE_MSB _u(3) -#define PADS_BANK0_GPIO23_PUE_LSB _u(3) -#define PADS_BANK0_GPIO23_PUE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO23_PDE -// Description : Pull down enable -#define PADS_BANK0_GPIO23_PDE_RESET _u(0x1) -#define PADS_BANK0_GPIO23_PDE_BITS _u(0x00000004) -#define PADS_BANK0_GPIO23_PDE_MSB _u(2) -#define PADS_BANK0_GPIO23_PDE_LSB _u(2) -#define PADS_BANK0_GPIO23_PDE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO23_SCHMITT -// Description : Enable schmitt trigger -#define PADS_BANK0_GPIO23_SCHMITT_RESET _u(0x1) -#define PADS_BANK0_GPIO23_SCHMITT_BITS _u(0x00000002) -#define PADS_BANK0_GPIO23_SCHMITT_MSB _u(1) -#define PADS_BANK0_GPIO23_SCHMITT_LSB _u(1) -#define PADS_BANK0_GPIO23_SCHMITT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO23_SLEWFAST -// Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO23_SLEWFAST_RESET _u(0x0) -#define PADS_BANK0_GPIO23_SLEWFAST_BITS _u(0x00000001) -#define PADS_BANK0_GPIO23_SLEWFAST_MSB _u(0) -#define PADS_BANK0_GPIO23_SLEWFAST_LSB _u(0) -#define PADS_BANK0_GPIO23_SLEWFAST_ACCESS "RW" -// ============================================================================= -// Register : PADS_BANK0_GPIO24 -#define PADS_BANK0_GPIO24_OFFSET _u(0x00000064) -#define PADS_BANK0_GPIO24_BITS _u(0x000001ff) -#define PADS_BANK0_GPIO24_RESET _u(0x00000116) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO24_ISO -// Description : Pad isolation control. Remove this once the pad is configured -// by software. -#define PADS_BANK0_GPIO24_ISO_RESET _u(0x1) -#define PADS_BANK0_GPIO24_ISO_BITS _u(0x00000100) -#define PADS_BANK0_GPIO24_ISO_MSB _u(8) -#define PADS_BANK0_GPIO24_ISO_LSB _u(8) -#define PADS_BANK0_GPIO24_ISO_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO24_OD -// Description : Output disable. Has priority over output enable from -// peripherals -#define PADS_BANK0_GPIO24_OD_RESET _u(0x0) -#define PADS_BANK0_GPIO24_OD_BITS _u(0x00000080) -#define PADS_BANK0_GPIO24_OD_MSB _u(7) -#define PADS_BANK0_GPIO24_OD_LSB _u(7) -#define PADS_BANK0_GPIO24_OD_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO24_IE -// Description : Input enable -#define PADS_BANK0_GPIO24_IE_RESET _u(0x0) -#define PADS_BANK0_GPIO24_IE_BITS _u(0x00000040) -#define PADS_BANK0_GPIO24_IE_MSB _u(6) -#define PADS_BANK0_GPIO24_IE_LSB _u(6) -#define PADS_BANK0_GPIO24_IE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO24_DRIVE -// Description : Drive strength. -// 0x0 -> 2mA -// 0x1 -> 4mA -// 0x2 -> 8mA -// 0x3 -> 12mA -#define PADS_BANK0_GPIO24_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO24_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO24_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO24_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO24_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO24_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO24_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO24_DRIVE_VALUE_8MA _u(0x2) -#define PADS_BANK0_GPIO24_DRIVE_VALUE_12MA _u(0x3) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO24_PUE -// Description : Pull up enable -#define PADS_BANK0_GPIO24_PUE_RESET _u(0x0) -#define PADS_BANK0_GPIO24_PUE_BITS _u(0x00000008) -#define PADS_BANK0_GPIO24_PUE_MSB _u(3) -#define PADS_BANK0_GPIO24_PUE_LSB _u(3) -#define PADS_BANK0_GPIO24_PUE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO24_PDE -// Description : Pull down enable -#define PADS_BANK0_GPIO24_PDE_RESET _u(0x1) -#define PADS_BANK0_GPIO24_PDE_BITS _u(0x00000004) -#define PADS_BANK0_GPIO24_PDE_MSB _u(2) -#define PADS_BANK0_GPIO24_PDE_LSB _u(2) -#define PADS_BANK0_GPIO24_PDE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO24_SCHMITT -// Description : Enable schmitt trigger -#define PADS_BANK0_GPIO24_SCHMITT_RESET _u(0x1) -#define PADS_BANK0_GPIO24_SCHMITT_BITS _u(0x00000002) -#define PADS_BANK0_GPIO24_SCHMITT_MSB _u(1) -#define PADS_BANK0_GPIO24_SCHMITT_LSB _u(1) -#define PADS_BANK0_GPIO24_SCHMITT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO24_SLEWFAST -// Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO24_SLEWFAST_RESET _u(0x0) -#define PADS_BANK0_GPIO24_SLEWFAST_BITS _u(0x00000001) -#define PADS_BANK0_GPIO24_SLEWFAST_MSB _u(0) -#define PADS_BANK0_GPIO24_SLEWFAST_LSB _u(0) -#define PADS_BANK0_GPIO24_SLEWFAST_ACCESS "RW" -// ============================================================================= -// Register : PADS_BANK0_GPIO25 -#define PADS_BANK0_GPIO25_OFFSET _u(0x00000068) -#define PADS_BANK0_GPIO25_BITS _u(0x000001ff) -#define PADS_BANK0_GPIO25_RESET _u(0x00000116) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO25_ISO -// Description : Pad isolation control. Remove this once the pad is configured -// by software. -#define PADS_BANK0_GPIO25_ISO_RESET _u(0x1) -#define PADS_BANK0_GPIO25_ISO_BITS _u(0x00000100) -#define PADS_BANK0_GPIO25_ISO_MSB _u(8) -#define PADS_BANK0_GPIO25_ISO_LSB _u(8) -#define PADS_BANK0_GPIO25_ISO_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO25_OD -// Description : Output disable. Has priority over output enable from -// peripherals -#define PADS_BANK0_GPIO25_OD_RESET _u(0x0) -#define PADS_BANK0_GPIO25_OD_BITS _u(0x00000080) -#define PADS_BANK0_GPIO25_OD_MSB _u(7) -#define PADS_BANK0_GPIO25_OD_LSB _u(7) -#define PADS_BANK0_GPIO25_OD_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO25_IE -// Description : Input enable -#define PADS_BANK0_GPIO25_IE_RESET _u(0x0) -#define PADS_BANK0_GPIO25_IE_BITS _u(0x00000040) -#define PADS_BANK0_GPIO25_IE_MSB _u(6) -#define PADS_BANK0_GPIO25_IE_LSB _u(6) -#define PADS_BANK0_GPIO25_IE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO25_DRIVE -// Description : Drive strength. -// 0x0 -> 2mA -// 0x1 -> 4mA -// 0x2 -> 8mA -// 0x3 -> 12mA -#define PADS_BANK0_GPIO25_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO25_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO25_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO25_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO25_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO25_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO25_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO25_DRIVE_VALUE_8MA _u(0x2) -#define PADS_BANK0_GPIO25_DRIVE_VALUE_12MA _u(0x3) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO25_PUE -// Description : Pull up enable -#define PADS_BANK0_GPIO25_PUE_RESET _u(0x0) -#define PADS_BANK0_GPIO25_PUE_BITS _u(0x00000008) -#define PADS_BANK0_GPIO25_PUE_MSB _u(3) -#define PADS_BANK0_GPIO25_PUE_LSB _u(3) -#define PADS_BANK0_GPIO25_PUE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO25_PDE -// Description : Pull down enable -#define PADS_BANK0_GPIO25_PDE_RESET _u(0x1) -#define PADS_BANK0_GPIO25_PDE_BITS _u(0x00000004) -#define PADS_BANK0_GPIO25_PDE_MSB _u(2) -#define PADS_BANK0_GPIO25_PDE_LSB _u(2) -#define PADS_BANK0_GPIO25_PDE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO25_SCHMITT -// Description : Enable schmitt trigger -#define PADS_BANK0_GPIO25_SCHMITT_RESET _u(0x1) -#define PADS_BANK0_GPIO25_SCHMITT_BITS _u(0x00000002) -#define PADS_BANK0_GPIO25_SCHMITT_MSB _u(1) -#define PADS_BANK0_GPIO25_SCHMITT_LSB _u(1) -#define PADS_BANK0_GPIO25_SCHMITT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO25_SLEWFAST -// Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO25_SLEWFAST_RESET _u(0x0) -#define PADS_BANK0_GPIO25_SLEWFAST_BITS _u(0x00000001) -#define PADS_BANK0_GPIO25_SLEWFAST_MSB _u(0) -#define PADS_BANK0_GPIO25_SLEWFAST_LSB _u(0) -#define PADS_BANK0_GPIO25_SLEWFAST_ACCESS "RW" -// ============================================================================= -// Register : PADS_BANK0_GPIO26 -#define PADS_BANK0_GPIO26_OFFSET _u(0x0000006c) -#define PADS_BANK0_GPIO26_BITS _u(0x000001ff) -#define PADS_BANK0_GPIO26_RESET _u(0x00000116) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO26_ISO -// Description : Pad isolation control. Remove this once the pad is configured -// by software. -#define PADS_BANK0_GPIO26_ISO_RESET _u(0x1) -#define PADS_BANK0_GPIO26_ISO_BITS _u(0x00000100) -#define PADS_BANK0_GPIO26_ISO_MSB _u(8) -#define PADS_BANK0_GPIO26_ISO_LSB _u(8) -#define PADS_BANK0_GPIO26_ISO_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO26_OD -// Description : Output disable. Has priority over output enable from -// peripherals -#define PADS_BANK0_GPIO26_OD_RESET _u(0x0) -#define PADS_BANK0_GPIO26_OD_BITS _u(0x00000080) -#define PADS_BANK0_GPIO26_OD_MSB _u(7) -#define PADS_BANK0_GPIO26_OD_LSB _u(7) -#define PADS_BANK0_GPIO26_OD_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO26_IE -// Description : Input enable -#define PADS_BANK0_GPIO26_IE_RESET _u(0x0) -#define PADS_BANK0_GPIO26_IE_BITS _u(0x00000040) -#define PADS_BANK0_GPIO26_IE_MSB _u(6) -#define PADS_BANK0_GPIO26_IE_LSB _u(6) -#define PADS_BANK0_GPIO26_IE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO26_DRIVE -// Description : Drive strength. -// 0x0 -> 2mA -// 0x1 -> 4mA -// 0x2 -> 8mA -// 0x3 -> 12mA -#define PADS_BANK0_GPIO26_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO26_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO26_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO26_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO26_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO26_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO26_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO26_DRIVE_VALUE_8MA _u(0x2) -#define PADS_BANK0_GPIO26_DRIVE_VALUE_12MA _u(0x3) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO26_PUE -// Description : Pull up enable -#define PADS_BANK0_GPIO26_PUE_RESET _u(0x0) -#define PADS_BANK0_GPIO26_PUE_BITS _u(0x00000008) -#define PADS_BANK0_GPIO26_PUE_MSB _u(3) -#define PADS_BANK0_GPIO26_PUE_LSB _u(3) -#define PADS_BANK0_GPIO26_PUE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO26_PDE -// Description : Pull down enable -#define PADS_BANK0_GPIO26_PDE_RESET _u(0x1) -#define PADS_BANK0_GPIO26_PDE_BITS _u(0x00000004) -#define PADS_BANK0_GPIO26_PDE_MSB _u(2) -#define PADS_BANK0_GPIO26_PDE_LSB _u(2) -#define PADS_BANK0_GPIO26_PDE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO26_SCHMITT -// Description : Enable schmitt trigger -#define PADS_BANK0_GPIO26_SCHMITT_RESET _u(0x1) -#define PADS_BANK0_GPIO26_SCHMITT_BITS _u(0x00000002) -#define PADS_BANK0_GPIO26_SCHMITT_MSB _u(1) -#define PADS_BANK0_GPIO26_SCHMITT_LSB _u(1) -#define PADS_BANK0_GPIO26_SCHMITT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO26_SLEWFAST -// Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO26_SLEWFAST_RESET _u(0x0) -#define PADS_BANK0_GPIO26_SLEWFAST_BITS _u(0x00000001) -#define PADS_BANK0_GPIO26_SLEWFAST_MSB _u(0) -#define PADS_BANK0_GPIO26_SLEWFAST_LSB _u(0) -#define PADS_BANK0_GPIO26_SLEWFAST_ACCESS "RW" -// ============================================================================= -// Register : PADS_BANK0_GPIO27 -#define PADS_BANK0_GPIO27_OFFSET _u(0x00000070) -#define PADS_BANK0_GPIO27_BITS _u(0x000001ff) -#define PADS_BANK0_GPIO27_RESET _u(0x00000116) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO27_ISO -// Description : Pad isolation control. Remove this once the pad is configured -// by software. -#define PADS_BANK0_GPIO27_ISO_RESET _u(0x1) -#define PADS_BANK0_GPIO27_ISO_BITS _u(0x00000100) -#define PADS_BANK0_GPIO27_ISO_MSB _u(8) -#define PADS_BANK0_GPIO27_ISO_LSB _u(8) -#define PADS_BANK0_GPIO27_ISO_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO27_OD -// Description : Output disable. Has priority over output enable from -// peripherals -#define PADS_BANK0_GPIO27_OD_RESET _u(0x0) -#define PADS_BANK0_GPIO27_OD_BITS _u(0x00000080) -#define PADS_BANK0_GPIO27_OD_MSB _u(7) -#define PADS_BANK0_GPIO27_OD_LSB _u(7) -#define PADS_BANK0_GPIO27_OD_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO27_IE -// Description : Input enable -#define PADS_BANK0_GPIO27_IE_RESET _u(0x0) -#define PADS_BANK0_GPIO27_IE_BITS _u(0x00000040) -#define PADS_BANK0_GPIO27_IE_MSB _u(6) -#define PADS_BANK0_GPIO27_IE_LSB _u(6) -#define PADS_BANK0_GPIO27_IE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO27_DRIVE -// Description : Drive strength. -// 0x0 -> 2mA -// 0x1 -> 4mA -// 0x2 -> 8mA -// 0x3 -> 12mA -#define PADS_BANK0_GPIO27_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO27_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO27_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO27_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO27_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO27_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO27_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO27_DRIVE_VALUE_8MA _u(0x2) -#define PADS_BANK0_GPIO27_DRIVE_VALUE_12MA _u(0x3) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO27_PUE -// Description : Pull up enable -#define PADS_BANK0_GPIO27_PUE_RESET _u(0x0) -#define PADS_BANK0_GPIO27_PUE_BITS _u(0x00000008) -#define PADS_BANK0_GPIO27_PUE_MSB _u(3) -#define PADS_BANK0_GPIO27_PUE_LSB _u(3) -#define PADS_BANK0_GPIO27_PUE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO27_PDE -// Description : Pull down enable -#define PADS_BANK0_GPIO27_PDE_RESET _u(0x1) -#define PADS_BANK0_GPIO27_PDE_BITS _u(0x00000004) -#define PADS_BANK0_GPIO27_PDE_MSB _u(2) -#define PADS_BANK0_GPIO27_PDE_LSB _u(2) -#define PADS_BANK0_GPIO27_PDE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO27_SCHMITT -// Description : Enable schmitt trigger -#define PADS_BANK0_GPIO27_SCHMITT_RESET _u(0x1) -#define PADS_BANK0_GPIO27_SCHMITT_BITS _u(0x00000002) -#define PADS_BANK0_GPIO27_SCHMITT_MSB _u(1) -#define PADS_BANK0_GPIO27_SCHMITT_LSB _u(1) -#define PADS_BANK0_GPIO27_SCHMITT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO27_SLEWFAST -// Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO27_SLEWFAST_RESET _u(0x0) -#define PADS_BANK0_GPIO27_SLEWFAST_BITS _u(0x00000001) -#define PADS_BANK0_GPIO27_SLEWFAST_MSB _u(0) -#define PADS_BANK0_GPIO27_SLEWFAST_LSB _u(0) -#define PADS_BANK0_GPIO27_SLEWFAST_ACCESS "RW" -// ============================================================================= -// Register : PADS_BANK0_GPIO28 -#define PADS_BANK0_GPIO28_OFFSET _u(0x00000074) -#define PADS_BANK0_GPIO28_BITS _u(0x000001ff) -#define PADS_BANK0_GPIO28_RESET _u(0x00000116) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO28_ISO -// Description : Pad isolation control. Remove this once the pad is configured -// by software. -#define PADS_BANK0_GPIO28_ISO_RESET _u(0x1) -#define PADS_BANK0_GPIO28_ISO_BITS _u(0x00000100) -#define PADS_BANK0_GPIO28_ISO_MSB _u(8) -#define PADS_BANK0_GPIO28_ISO_LSB _u(8) -#define PADS_BANK0_GPIO28_ISO_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO28_OD -// Description : Output disable. Has priority over output enable from -// peripherals -#define PADS_BANK0_GPIO28_OD_RESET _u(0x0) -#define PADS_BANK0_GPIO28_OD_BITS _u(0x00000080) -#define PADS_BANK0_GPIO28_OD_MSB _u(7) -#define PADS_BANK0_GPIO28_OD_LSB _u(7) -#define PADS_BANK0_GPIO28_OD_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO28_IE -// Description : Input enable -#define PADS_BANK0_GPIO28_IE_RESET _u(0x0) -#define PADS_BANK0_GPIO28_IE_BITS _u(0x00000040) -#define PADS_BANK0_GPIO28_IE_MSB _u(6) -#define PADS_BANK0_GPIO28_IE_LSB _u(6) -#define PADS_BANK0_GPIO28_IE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO28_DRIVE -// Description : Drive strength. -// 0x0 -> 2mA -// 0x1 -> 4mA -// 0x2 -> 8mA -// 0x3 -> 12mA -#define PADS_BANK0_GPIO28_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO28_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO28_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO28_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO28_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO28_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO28_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO28_DRIVE_VALUE_8MA _u(0x2) -#define PADS_BANK0_GPIO28_DRIVE_VALUE_12MA _u(0x3) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO28_PUE -// Description : Pull up enable -#define PADS_BANK0_GPIO28_PUE_RESET _u(0x0) -#define PADS_BANK0_GPIO28_PUE_BITS _u(0x00000008) -#define PADS_BANK0_GPIO28_PUE_MSB _u(3) -#define PADS_BANK0_GPIO28_PUE_LSB _u(3) -#define PADS_BANK0_GPIO28_PUE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO28_PDE -// Description : Pull down enable -#define PADS_BANK0_GPIO28_PDE_RESET _u(0x1) -#define PADS_BANK0_GPIO28_PDE_BITS _u(0x00000004) -#define PADS_BANK0_GPIO28_PDE_MSB _u(2) -#define PADS_BANK0_GPIO28_PDE_LSB _u(2) -#define PADS_BANK0_GPIO28_PDE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO28_SCHMITT -// Description : Enable schmitt trigger -#define PADS_BANK0_GPIO28_SCHMITT_RESET _u(0x1) -#define PADS_BANK0_GPIO28_SCHMITT_BITS _u(0x00000002) -#define PADS_BANK0_GPIO28_SCHMITT_MSB _u(1) -#define PADS_BANK0_GPIO28_SCHMITT_LSB _u(1) -#define PADS_BANK0_GPIO28_SCHMITT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO28_SLEWFAST -// Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO28_SLEWFAST_RESET _u(0x0) -#define PADS_BANK0_GPIO28_SLEWFAST_BITS _u(0x00000001) -#define PADS_BANK0_GPIO28_SLEWFAST_MSB _u(0) -#define PADS_BANK0_GPIO28_SLEWFAST_LSB _u(0) -#define PADS_BANK0_GPIO28_SLEWFAST_ACCESS "RW" -// ============================================================================= -// Register : PADS_BANK0_GPIO29 -#define PADS_BANK0_GPIO29_OFFSET _u(0x00000078) -#define PADS_BANK0_GPIO29_BITS _u(0x000001ff) -#define PADS_BANK0_GPIO29_RESET _u(0x00000116) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO29_ISO -// Description : Pad isolation control. Remove this once the pad is configured -// by software. -#define PADS_BANK0_GPIO29_ISO_RESET _u(0x1) -#define PADS_BANK0_GPIO29_ISO_BITS _u(0x00000100) -#define PADS_BANK0_GPIO29_ISO_MSB _u(8) -#define PADS_BANK0_GPIO29_ISO_LSB _u(8) -#define PADS_BANK0_GPIO29_ISO_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO29_OD -// Description : Output disable. Has priority over output enable from -// peripherals -#define PADS_BANK0_GPIO29_OD_RESET _u(0x0) -#define PADS_BANK0_GPIO29_OD_BITS _u(0x00000080) -#define PADS_BANK0_GPIO29_OD_MSB _u(7) -#define PADS_BANK0_GPIO29_OD_LSB _u(7) -#define PADS_BANK0_GPIO29_OD_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO29_IE -// Description : Input enable -#define PADS_BANK0_GPIO29_IE_RESET _u(0x0) -#define PADS_BANK0_GPIO29_IE_BITS _u(0x00000040) -#define PADS_BANK0_GPIO29_IE_MSB _u(6) -#define PADS_BANK0_GPIO29_IE_LSB _u(6) -#define PADS_BANK0_GPIO29_IE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO29_DRIVE -// Description : Drive strength. -// 0x0 -> 2mA -// 0x1 -> 4mA -// 0x2 -> 8mA -// 0x3 -> 12mA -#define PADS_BANK0_GPIO29_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO29_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO29_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO29_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO29_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO29_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO29_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO29_DRIVE_VALUE_8MA _u(0x2) -#define PADS_BANK0_GPIO29_DRIVE_VALUE_12MA _u(0x3) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO29_PUE -// Description : Pull up enable -#define PADS_BANK0_GPIO29_PUE_RESET _u(0x0) -#define PADS_BANK0_GPIO29_PUE_BITS _u(0x00000008) -#define PADS_BANK0_GPIO29_PUE_MSB _u(3) -#define PADS_BANK0_GPIO29_PUE_LSB _u(3) -#define PADS_BANK0_GPIO29_PUE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO29_PDE -// Description : Pull down enable -#define PADS_BANK0_GPIO29_PDE_RESET _u(0x1) -#define PADS_BANK0_GPIO29_PDE_BITS _u(0x00000004) -#define PADS_BANK0_GPIO29_PDE_MSB _u(2) -#define PADS_BANK0_GPIO29_PDE_LSB _u(2) -#define PADS_BANK0_GPIO29_PDE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO29_SCHMITT -// Description : Enable schmitt trigger -#define PADS_BANK0_GPIO29_SCHMITT_RESET _u(0x1) -#define PADS_BANK0_GPIO29_SCHMITT_BITS _u(0x00000002) -#define PADS_BANK0_GPIO29_SCHMITT_MSB _u(1) -#define PADS_BANK0_GPIO29_SCHMITT_LSB _u(1) -#define PADS_BANK0_GPIO29_SCHMITT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO29_SLEWFAST -// Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO29_SLEWFAST_RESET _u(0x0) -#define PADS_BANK0_GPIO29_SLEWFAST_BITS _u(0x00000001) -#define PADS_BANK0_GPIO29_SLEWFAST_MSB _u(0) -#define PADS_BANK0_GPIO29_SLEWFAST_LSB _u(0) -#define PADS_BANK0_GPIO29_SLEWFAST_ACCESS "RW" -// ============================================================================= -// Register : PADS_BANK0_GPIO30 -#define PADS_BANK0_GPIO30_OFFSET _u(0x0000007c) -#define PADS_BANK0_GPIO30_BITS _u(0x000001ff) -#define PADS_BANK0_GPIO30_RESET _u(0x00000116) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO30_ISO -// Description : Pad isolation control. Remove this once the pad is configured -// by software. -#define PADS_BANK0_GPIO30_ISO_RESET _u(0x1) -#define PADS_BANK0_GPIO30_ISO_BITS _u(0x00000100) -#define PADS_BANK0_GPIO30_ISO_MSB _u(8) -#define PADS_BANK0_GPIO30_ISO_LSB _u(8) -#define PADS_BANK0_GPIO30_ISO_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO30_OD -// Description : Output disable. Has priority over output enable from -// peripherals -#define PADS_BANK0_GPIO30_OD_RESET _u(0x0) -#define PADS_BANK0_GPIO30_OD_BITS _u(0x00000080) -#define PADS_BANK0_GPIO30_OD_MSB _u(7) -#define PADS_BANK0_GPIO30_OD_LSB _u(7) -#define PADS_BANK0_GPIO30_OD_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO30_IE -// Description : Input enable -#define PADS_BANK0_GPIO30_IE_RESET _u(0x0) -#define PADS_BANK0_GPIO30_IE_BITS _u(0x00000040) -#define PADS_BANK0_GPIO30_IE_MSB _u(6) -#define PADS_BANK0_GPIO30_IE_LSB _u(6) -#define PADS_BANK0_GPIO30_IE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO30_DRIVE -// Description : Drive strength. -// 0x0 -> 2mA -// 0x1 -> 4mA -// 0x2 -> 8mA -// 0x3 -> 12mA -#define PADS_BANK0_GPIO30_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO30_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO30_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO30_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO30_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO30_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO30_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO30_DRIVE_VALUE_8MA _u(0x2) -#define PADS_BANK0_GPIO30_DRIVE_VALUE_12MA _u(0x3) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO30_PUE -// Description : Pull up enable -#define PADS_BANK0_GPIO30_PUE_RESET _u(0x0) -#define PADS_BANK0_GPIO30_PUE_BITS _u(0x00000008) -#define PADS_BANK0_GPIO30_PUE_MSB _u(3) -#define PADS_BANK0_GPIO30_PUE_LSB _u(3) -#define PADS_BANK0_GPIO30_PUE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO30_PDE -// Description : Pull down enable -#define PADS_BANK0_GPIO30_PDE_RESET _u(0x1) -#define PADS_BANK0_GPIO30_PDE_BITS _u(0x00000004) -#define PADS_BANK0_GPIO30_PDE_MSB _u(2) -#define PADS_BANK0_GPIO30_PDE_LSB _u(2) -#define PADS_BANK0_GPIO30_PDE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO30_SCHMITT -// Description : Enable schmitt trigger -#define PADS_BANK0_GPIO30_SCHMITT_RESET _u(0x1) -#define PADS_BANK0_GPIO30_SCHMITT_BITS _u(0x00000002) -#define PADS_BANK0_GPIO30_SCHMITT_MSB _u(1) -#define PADS_BANK0_GPIO30_SCHMITT_LSB _u(1) -#define PADS_BANK0_GPIO30_SCHMITT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO30_SLEWFAST -// Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO30_SLEWFAST_RESET _u(0x0) -#define PADS_BANK0_GPIO30_SLEWFAST_BITS _u(0x00000001) -#define PADS_BANK0_GPIO30_SLEWFAST_MSB _u(0) -#define PADS_BANK0_GPIO30_SLEWFAST_LSB _u(0) -#define PADS_BANK0_GPIO30_SLEWFAST_ACCESS "RW" -// ============================================================================= -// Register : PADS_BANK0_GPIO31 -#define PADS_BANK0_GPIO31_OFFSET _u(0x00000080) -#define PADS_BANK0_GPIO31_BITS _u(0x000001ff) -#define PADS_BANK0_GPIO31_RESET _u(0x00000116) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO31_ISO -// Description : Pad isolation control. Remove this once the pad is configured -// by software. -#define PADS_BANK0_GPIO31_ISO_RESET _u(0x1) -#define PADS_BANK0_GPIO31_ISO_BITS _u(0x00000100) -#define PADS_BANK0_GPIO31_ISO_MSB _u(8) -#define PADS_BANK0_GPIO31_ISO_LSB _u(8) -#define PADS_BANK0_GPIO31_ISO_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO31_OD -// Description : Output disable. Has priority over output enable from -// peripherals -#define PADS_BANK0_GPIO31_OD_RESET _u(0x0) -#define PADS_BANK0_GPIO31_OD_BITS _u(0x00000080) -#define PADS_BANK0_GPIO31_OD_MSB _u(7) -#define PADS_BANK0_GPIO31_OD_LSB _u(7) -#define PADS_BANK0_GPIO31_OD_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO31_IE -// Description : Input enable -#define PADS_BANK0_GPIO31_IE_RESET _u(0x0) -#define PADS_BANK0_GPIO31_IE_BITS _u(0x00000040) -#define PADS_BANK0_GPIO31_IE_MSB _u(6) -#define PADS_BANK0_GPIO31_IE_LSB _u(6) -#define PADS_BANK0_GPIO31_IE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO31_DRIVE -// Description : Drive strength. -// 0x0 -> 2mA -// 0x1 -> 4mA -// 0x2 -> 8mA -// 0x3 -> 12mA -#define PADS_BANK0_GPIO31_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO31_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO31_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO31_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO31_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO31_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO31_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO31_DRIVE_VALUE_8MA _u(0x2) -#define PADS_BANK0_GPIO31_DRIVE_VALUE_12MA _u(0x3) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO31_PUE -// Description : Pull up enable -#define PADS_BANK0_GPIO31_PUE_RESET _u(0x0) -#define PADS_BANK0_GPIO31_PUE_BITS _u(0x00000008) -#define PADS_BANK0_GPIO31_PUE_MSB _u(3) -#define PADS_BANK0_GPIO31_PUE_LSB _u(3) -#define PADS_BANK0_GPIO31_PUE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO31_PDE -// Description : Pull down enable -#define PADS_BANK0_GPIO31_PDE_RESET _u(0x1) -#define PADS_BANK0_GPIO31_PDE_BITS _u(0x00000004) -#define PADS_BANK0_GPIO31_PDE_MSB _u(2) -#define PADS_BANK0_GPIO31_PDE_LSB _u(2) -#define PADS_BANK0_GPIO31_PDE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO31_SCHMITT -// Description : Enable schmitt trigger -#define PADS_BANK0_GPIO31_SCHMITT_RESET _u(0x1) -#define PADS_BANK0_GPIO31_SCHMITT_BITS _u(0x00000002) -#define PADS_BANK0_GPIO31_SCHMITT_MSB _u(1) -#define PADS_BANK0_GPIO31_SCHMITT_LSB _u(1) -#define PADS_BANK0_GPIO31_SCHMITT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO31_SLEWFAST -// Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO31_SLEWFAST_RESET _u(0x0) -#define PADS_BANK0_GPIO31_SLEWFAST_BITS _u(0x00000001) -#define PADS_BANK0_GPIO31_SLEWFAST_MSB _u(0) -#define PADS_BANK0_GPIO31_SLEWFAST_LSB _u(0) -#define PADS_BANK0_GPIO31_SLEWFAST_ACCESS "RW" -// ============================================================================= -// Register : PADS_BANK0_GPIO32 -#define PADS_BANK0_GPIO32_OFFSET _u(0x00000084) -#define PADS_BANK0_GPIO32_BITS _u(0x000001ff) -#define PADS_BANK0_GPIO32_RESET _u(0x00000116) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO32_ISO -// Description : Pad isolation control. Remove this once the pad is configured -// by software. -#define PADS_BANK0_GPIO32_ISO_RESET _u(0x1) -#define PADS_BANK0_GPIO32_ISO_BITS _u(0x00000100) -#define PADS_BANK0_GPIO32_ISO_MSB _u(8) -#define PADS_BANK0_GPIO32_ISO_LSB _u(8) -#define PADS_BANK0_GPIO32_ISO_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO32_OD -// Description : Output disable. Has priority over output enable from -// peripherals -#define PADS_BANK0_GPIO32_OD_RESET _u(0x0) -#define PADS_BANK0_GPIO32_OD_BITS _u(0x00000080) -#define PADS_BANK0_GPIO32_OD_MSB _u(7) -#define PADS_BANK0_GPIO32_OD_LSB _u(7) -#define PADS_BANK0_GPIO32_OD_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO32_IE -// Description : Input enable -#define PADS_BANK0_GPIO32_IE_RESET _u(0x0) -#define PADS_BANK0_GPIO32_IE_BITS _u(0x00000040) -#define PADS_BANK0_GPIO32_IE_MSB _u(6) -#define PADS_BANK0_GPIO32_IE_LSB _u(6) -#define PADS_BANK0_GPIO32_IE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO32_DRIVE -// Description : Drive strength. -// 0x0 -> 2mA -// 0x1 -> 4mA -// 0x2 -> 8mA -// 0x3 -> 12mA -#define PADS_BANK0_GPIO32_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO32_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO32_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO32_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO32_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO32_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO32_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO32_DRIVE_VALUE_8MA _u(0x2) -#define PADS_BANK0_GPIO32_DRIVE_VALUE_12MA _u(0x3) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO32_PUE -// Description : Pull up enable -#define PADS_BANK0_GPIO32_PUE_RESET _u(0x0) -#define PADS_BANK0_GPIO32_PUE_BITS _u(0x00000008) -#define PADS_BANK0_GPIO32_PUE_MSB _u(3) -#define PADS_BANK0_GPIO32_PUE_LSB _u(3) -#define PADS_BANK0_GPIO32_PUE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO32_PDE -// Description : Pull down enable -#define PADS_BANK0_GPIO32_PDE_RESET _u(0x1) -#define PADS_BANK0_GPIO32_PDE_BITS _u(0x00000004) -#define PADS_BANK0_GPIO32_PDE_MSB _u(2) -#define PADS_BANK0_GPIO32_PDE_LSB _u(2) -#define PADS_BANK0_GPIO32_PDE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO32_SCHMITT -// Description : Enable schmitt trigger -#define PADS_BANK0_GPIO32_SCHMITT_RESET _u(0x1) -#define PADS_BANK0_GPIO32_SCHMITT_BITS _u(0x00000002) -#define PADS_BANK0_GPIO32_SCHMITT_MSB _u(1) -#define PADS_BANK0_GPIO32_SCHMITT_LSB _u(1) -#define PADS_BANK0_GPIO32_SCHMITT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO32_SLEWFAST -// Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO32_SLEWFAST_RESET _u(0x0) -#define PADS_BANK0_GPIO32_SLEWFAST_BITS _u(0x00000001) -#define PADS_BANK0_GPIO32_SLEWFAST_MSB _u(0) -#define PADS_BANK0_GPIO32_SLEWFAST_LSB _u(0) -#define PADS_BANK0_GPIO32_SLEWFAST_ACCESS "RW" -// ============================================================================= -// Register : PADS_BANK0_GPIO33 -#define PADS_BANK0_GPIO33_OFFSET _u(0x00000088) -#define PADS_BANK0_GPIO33_BITS _u(0x000001ff) -#define PADS_BANK0_GPIO33_RESET _u(0x00000116) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO33_ISO -// Description : Pad isolation control. Remove this once the pad is configured -// by software. -#define PADS_BANK0_GPIO33_ISO_RESET _u(0x1) -#define PADS_BANK0_GPIO33_ISO_BITS _u(0x00000100) -#define PADS_BANK0_GPIO33_ISO_MSB _u(8) -#define PADS_BANK0_GPIO33_ISO_LSB _u(8) -#define PADS_BANK0_GPIO33_ISO_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO33_OD -// Description : Output disable. Has priority over output enable from -// peripherals -#define PADS_BANK0_GPIO33_OD_RESET _u(0x0) -#define PADS_BANK0_GPIO33_OD_BITS _u(0x00000080) -#define PADS_BANK0_GPIO33_OD_MSB _u(7) -#define PADS_BANK0_GPIO33_OD_LSB _u(7) -#define PADS_BANK0_GPIO33_OD_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO33_IE -// Description : Input enable -#define PADS_BANK0_GPIO33_IE_RESET _u(0x0) -#define PADS_BANK0_GPIO33_IE_BITS _u(0x00000040) -#define PADS_BANK0_GPIO33_IE_MSB _u(6) -#define PADS_BANK0_GPIO33_IE_LSB _u(6) -#define PADS_BANK0_GPIO33_IE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO33_DRIVE -// Description : Drive strength. -// 0x0 -> 2mA -// 0x1 -> 4mA -// 0x2 -> 8mA -// 0x3 -> 12mA -#define PADS_BANK0_GPIO33_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO33_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO33_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO33_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO33_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO33_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO33_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO33_DRIVE_VALUE_8MA _u(0x2) -#define PADS_BANK0_GPIO33_DRIVE_VALUE_12MA _u(0x3) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO33_PUE -// Description : Pull up enable -#define PADS_BANK0_GPIO33_PUE_RESET _u(0x0) -#define PADS_BANK0_GPIO33_PUE_BITS _u(0x00000008) -#define PADS_BANK0_GPIO33_PUE_MSB _u(3) -#define PADS_BANK0_GPIO33_PUE_LSB _u(3) -#define PADS_BANK0_GPIO33_PUE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO33_PDE -// Description : Pull down enable -#define PADS_BANK0_GPIO33_PDE_RESET _u(0x1) -#define PADS_BANK0_GPIO33_PDE_BITS _u(0x00000004) -#define PADS_BANK0_GPIO33_PDE_MSB _u(2) -#define PADS_BANK0_GPIO33_PDE_LSB _u(2) -#define PADS_BANK0_GPIO33_PDE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO33_SCHMITT -// Description : Enable schmitt trigger -#define PADS_BANK0_GPIO33_SCHMITT_RESET _u(0x1) -#define PADS_BANK0_GPIO33_SCHMITT_BITS _u(0x00000002) -#define PADS_BANK0_GPIO33_SCHMITT_MSB _u(1) -#define PADS_BANK0_GPIO33_SCHMITT_LSB _u(1) -#define PADS_BANK0_GPIO33_SCHMITT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO33_SLEWFAST -// Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO33_SLEWFAST_RESET _u(0x0) -#define PADS_BANK0_GPIO33_SLEWFAST_BITS _u(0x00000001) -#define PADS_BANK0_GPIO33_SLEWFAST_MSB _u(0) -#define PADS_BANK0_GPIO33_SLEWFAST_LSB _u(0) -#define PADS_BANK0_GPIO33_SLEWFAST_ACCESS "RW" -// ============================================================================= -// Register : PADS_BANK0_GPIO34 -#define PADS_BANK0_GPIO34_OFFSET _u(0x0000008c) -#define PADS_BANK0_GPIO34_BITS _u(0x000001ff) -#define PADS_BANK0_GPIO34_RESET _u(0x00000116) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO34_ISO -// Description : Pad isolation control. Remove this once the pad is configured -// by software. -#define PADS_BANK0_GPIO34_ISO_RESET _u(0x1) -#define PADS_BANK0_GPIO34_ISO_BITS _u(0x00000100) -#define PADS_BANK0_GPIO34_ISO_MSB _u(8) -#define PADS_BANK0_GPIO34_ISO_LSB _u(8) -#define PADS_BANK0_GPIO34_ISO_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO34_OD -// Description : Output disable. Has priority over output enable from -// peripherals -#define PADS_BANK0_GPIO34_OD_RESET _u(0x0) -#define PADS_BANK0_GPIO34_OD_BITS _u(0x00000080) -#define PADS_BANK0_GPIO34_OD_MSB _u(7) -#define PADS_BANK0_GPIO34_OD_LSB _u(7) -#define PADS_BANK0_GPIO34_OD_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO34_IE -// Description : Input enable -#define PADS_BANK0_GPIO34_IE_RESET _u(0x0) -#define PADS_BANK0_GPIO34_IE_BITS _u(0x00000040) -#define PADS_BANK0_GPIO34_IE_MSB _u(6) -#define PADS_BANK0_GPIO34_IE_LSB _u(6) -#define PADS_BANK0_GPIO34_IE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO34_DRIVE -// Description : Drive strength. -// 0x0 -> 2mA -// 0x1 -> 4mA -// 0x2 -> 8mA -// 0x3 -> 12mA -#define PADS_BANK0_GPIO34_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO34_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO34_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO34_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO34_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO34_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO34_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO34_DRIVE_VALUE_8MA _u(0x2) -#define PADS_BANK0_GPIO34_DRIVE_VALUE_12MA _u(0x3) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO34_PUE -// Description : Pull up enable -#define PADS_BANK0_GPIO34_PUE_RESET _u(0x0) -#define PADS_BANK0_GPIO34_PUE_BITS _u(0x00000008) -#define PADS_BANK0_GPIO34_PUE_MSB _u(3) -#define PADS_BANK0_GPIO34_PUE_LSB _u(3) -#define PADS_BANK0_GPIO34_PUE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO34_PDE -// Description : Pull down enable -#define PADS_BANK0_GPIO34_PDE_RESET _u(0x1) -#define PADS_BANK0_GPIO34_PDE_BITS _u(0x00000004) -#define PADS_BANK0_GPIO34_PDE_MSB _u(2) -#define PADS_BANK0_GPIO34_PDE_LSB _u(2) -#define PADS_BANK0_GPIO34_PDE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO34_SCHMITT -// Description : Enable schmitt trigger -#define PADS_BANK0_GPIO34_SCHMITT_RESET _u(0x1) -#define PADS_BANK0_GPIO34_SCHMITT_BITS _u(0x00000002) -#define PADS_BANK0_GPIO34_SCHMITT_MSB _u(1) -#define PADS_BANK0_GPIO34_SCHMITT_LSB _u(1) -#define PADS_BANK0_GPIO34_SCHMITT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO34_SLEWFAST -// Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO34_SLEWFAST_RESET _u(0x0) -#define PADS_BANK0_GPIO34_SLEWFAST_BITS _u(0x00000001) -#define PADS_BANK0_GPIO34_SLEWFAST_MSB _u(0) -#define PADS_BANK0_GPIO34_SLEWFAST_LSB _u(0) -#define PADS_BANK0_GPIO34_SLEWFAST_ACCESS "RW" -// ============================================================================= -// Register : PADS_BANK0_GPIO35 -#define PADS_BANK0_GPIO35_OFFSET _u(0x00000090) -#define PADS_BANK0_GPIO35_BITS _u(0x000001ff) -#define PADS_BANK0_GPIO35_RESET _u(0x00000116) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO35_ISO -// Description : Pad isolation control. Remove this once the pad is configured -// by software. -#define PADS_BANK0_GPIO35_ISO_RESET _u(0x1) -#define PADS_BANK0_GPIO35_ISO_BITS _u(0x00000100) -#define PADS_BANK0_GPIO35_ISO_MSB _u(8) -#define PADS_BANK0_GPIO35_ISO_LSB _u(8) -#define PADS_BANK0_GPIO35_ISO_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO35_OD -// Description : Output disable. Has priority over output enable from -// peripherals -#define PADS_BANK0_GPIO35_OD_RESET _u(0x0) -#define PADS_BANK0_GPIO35_OD_BITS _u(0x00000080) -#define PADS_BANK0_GPIO35_OD_MSB _u(7) -#define PADS_BANK0_GPIO35_OD_LSB _u(7) -#define PADS_BANK0_GPIO35_OD_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO35_IE -// Description : Input enable -#define PADS_BANK0_GPIO35_IE_RESET _u(0x0) -#define PADS_BANK0_GPIO35_IE_BITS _u(0x00000040) -#define PADS_BANK0_GPIO35_IE_MSB _u(6) -#define PADS_BANK0_GPIO35_IE_LSB _u(6) -#define PADS_BANK0_GPIO35_IE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO35_DRIVE -// Description : Drive strength. -// 0x0 -> 2mA -// 0x1 -> 4mA -// 0x2 -> 8mA -// 0x3 -> 12mA -#define PADS_BANK0_GPIO35_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO35_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO35_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO35_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO35_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO35_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO35_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO35_DRIVE_VALUE_8MA _u(0x2) -#define PADS_BANK0_GPIO35_DRIVE_VALUE_12MA _u(0x3) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO35_PUE -// Description : Pull up enable -#define PADS_BANK0_GPIO35_PUE_RESET _u(0x0) -#define PADS_BANK0_GPIO35_PUE_BITS _u(0x00000008) -#define PADS_BANK0_GPIO35_PUE_MSB _u(3) -#define PADS_BANK0_GPIO35_PUE_LSB _u(3) -#define PADS_BANK0_GPIO35_PUE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO35_PDE -// Description : Pull down enable -#define PADS_BANK0_GPIO35_PDE_RESET _u(0x1) -#define PADS_BANK0_GPIO35_PDE_BITS _u(0x00000004) -#define PADS_BANK0_GPIO35_PDE_MSB _u(2) -#define PADS_BANK0_GPIO35_PDE_LSB _u(2) -#define PADS_BANK0_GPIO35_PDE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO35_SCHMITT -// Description : Enable schmitt trigger -#define PADS_BANK0_GPIO35_SCHMITT_RESET _u(0x1) -#define PADS_BANK0_GPIO35_SCHMITT_BITS _u(0x00000002) -#define PADS_BANK0_GPIO35_SCHMITT_MSB _u(1) -#define PADS_BANK0_GPIO35_SCHMITT_LSB _u(1) -#define PADS_BANK0_GPIO35_SCHMITT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO35_SLEWFAST -// Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO35_SLEWFAST_RESET _u(0x0) -#define PADS_BANK0_GPIO35_SLEWFAST_BITS _u(0x00000001) -#define PADS_BANK0_GPIO35_SLEWFAST_MSB _u(0) -#define PADS_BANK0_GPIO35_SLEWFAST_LSB _u(0) -#define PADS_BANK0_GPIO35_SLEWFAST_ACCESS "RW" -// ============================================================================= -// Register : PADS_BANK0_GPIO36 -#define PADS_BANK0_GPIO36_OFFSET _u(0x00000094) -#define PADS_BANK0_GPIO36_BITS _u(0x000001ff) -#define PADS_BANK0_GPIO36_RESET _u(0x00000116) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO36_ISO -// Description : Pad isolation control. Remove this once the pad is configured -// by software. -#define PADS_BANK0_GPIO36_ISO_RESET _u(0x1) -#define PADS_BANK0_GPIO36_ISO_BITS _u(0x00000100) -#define PADS_BANK0_GPIO36_ISO_MSB _u(8) -#define PADS_BANK0_GPIO36_ISO_LSB _u(8) -#define PADS_BANK0_GPIO36_ISO_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO36_OD -// Description : Output disable. Has priority over output enable from -// peripherals -#define PADS_BANK0_GPIO36_OD_RESET _u(0x0) -#define PADS_BANK0_GPIO36_OD_BITS _u(0x00000080) -#define PADS_BANK0_GPIO36_OD_MSB _u(7) -#define PADS_BANK0_GPIO36_OD_LSB _u(7) -#define PADS_BANK0_GPIO36_OD_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO36_IE -// Description : Input enable -#define PADS_BANK0_GPIO36_IE_RESET _u(0x0) -#define PADS_BANK0_GPIO36_IE_BITS _u(0x00000040) -#define PADS_BANK0_GPIO36_IE_MSB _u(6) -#define PADS_BANK0_GPIO36_IE_LSB _u(6) -#define PADS_BANK0_GPIO36_IE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO36_DRIVE -// Description : Drive strength. -// 0x0 -> 2mA -// 0x1 -> 4mA -// 0x2 -> 8mA -// 0x3 -> 12mA -#define PADS_BANK0_GPIO36_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO36_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO36_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO36_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO36_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO36_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO36_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO36_DRIVE_VALUE_8MA _u(0x2) -#define PADS_BANK0_GPIO36_DRIVE_VALUE_12MA _u(0x3) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO36_PUE -// Description : Pull up enable -#define PADS_BANK0_GPIO36_PUE_RESET _u(0x0) -#define PADS_BANK0_GPIO36_PUE_BITS _u(0x00000008) -#define PADS_BANK0_GPIO36_PUE_MSB _u(3) -#define PADS_BANK0_GPIO36_PUE_LSB _u(3) -#define PADS_BANK0_GPIO36_PUE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO36_PDE -// Description : Pull down enable -#define PADS_BANK0_GPIO36_PDE_RESET _u(0x1) -#define PADS_BANK0_GPIO36_PDE_BITS _u(0x00000004) -#define PADS_BANK0_GPIO36_PDE_MSB _u(2) -#define PADS_BANK0_GPIO36_PDE_LSB _u(2) -#define PADS_BANK0_GPIO36_PDE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO36_SCHMITT -// Description : Enable schmitt trigger -#define PADS_BANK0_GPIO36_SCHMITT_RESET _u(0x1) -#define PADS_BANK0_GPIO36_SCHMITT_BITS _u(0x00000002) -#define PADS_BANK0_GPIO36_SCHMITT_MSB _u(1) -#define PADS_BANK0_GPIO36_SCHMITT_LSB _u(1) -#define PADS_BANK0_GPIO36_SCHMITT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO36_SLEWFAST -// Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO36_SLEWFAST_RESET _u(0x0) -#define PADS_BANK0_GPIO36_SLEWFAST_BITS _u(0x00000001) -#define PADS_BANK0_GPIO36_SLEWFAST_MSB _u(0) -#define PADS_BANK0_GPIO36_SLEWFAST_LSB _u(0) -#define PADS_BANK0_GPIO36_SLEWFAST_ACCESS "RW" -// ============================================================================= -// Register : PADS_BANK0_GPIO37 -#define PADS_BANK0_GPIO37_OFFSET _u(0x00000098) -#define PADS_BANK0_GPIO37_BITS _u(0x000001ff) -#define PADS_BANK0_GPIO37_RESET _u(0x00000116) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO37_ISO -// Description : Pad isolation control. Remove this once the pad is configured -// by software. -#define PADS_BANK0_GPIO37_ISO_RESET _u(0x1) -#define PADS_BANK0_GPIO37_ISO_BITS _u(0x00000100) -#define PADS_BANK0_GPIO37_ISO_MSB _u(8) -#define PADS_BANK0_GPIO37_ISO_LSB _u(8) -#define PADS_BANK0_GPIO37_ISO_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO37_OD -// Description : Output disable. Has priority over output enable from -// peripherals -#define PADS_BANK0_GPIO37_OD_RESET _u(0x0) -#define PADS_BANK0_GPIO37_OD_BITS _u(0x00000080) -#define PADS_BANK0_GPIO37_OD_MSB _u(7) -#define PADS_BANK0_GPIO37_OD_LSB _u(7) -#define PADS_BANK0_GPIO37_OD_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO37_IE -// Description : Input enable -#define PADS_BANK0_GPIO37_IE_RESET _u(0x0) -#define PADS_BANK0_GPIO37_IE_BITS _u(0x00000040) -#define PADS_BANK0_GPIO37_IE_MSB _u(6) -#define PADS_BANK0_GPIO37_IE_LSB _u(6) -#define PADS_BANK0_GPIO37_IE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO37_DRIVE -// Description : Drive strength. -// 0x0 -> 2mA -// 0x1 -> 4mA -// 0x2 -> 8mA -// 0x3 -> 12mA -#define PADS_BANK0_GPIO37_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO37_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO37_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO37_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO37_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO37_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO37_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO37_DRIVE_VALUE_8MA _u(0x2) -#define PADS_BANK0_GPIO37_DRIVE_VALUE_12MA _u(0x3) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO37_PUE -// Description : Pull up enable -#define PADS_BANK0_GPIO37_PUE_RESET _u(0x0) -#define PADS_BANK0_GPIO37_PUE_BITS _u(0x00000008) -#define PADS_BANK0_GPIO37_PUE_MSB _u(3) -#define PADS_BANK0_GPIO37_PUE_LSB _u(3) -#define PADS_BANK0_GPIO37_PUE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO37_PDE -// Description : Pull down enable -#define PADS_BANK0_GPIO37_PDE_RESET _u(0x1) -#define PADS_BANK0_GPIO37_PDE_BITS _u(0x00000004) -#define PADS_BANK0_GPIO37_PDE_MSB _u(2) -#define PADS_BANK0_GPIO37_PDE_LSB _u(2) -#define PADS_BANK0_GPIO37_PDE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO37_SCHMITT -// Description : Enable schmitt trigger -#define PADS_BANK0_GPIO37_SCHMITT_RESET _u(0x1) -#define PADS_BANK0_GPIO37_SCHMITT_BITS _u(0x00000002) -#define PADS_BANK0_GPIO37_SCHMITT_MSB _u(1) -#define PADS_BANK0_GPIO37_SCHMITT_LSB _u(1) -#define PADS_BANK0_GPIO37_SCHMITT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO37_SLEWFAST -// Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO37_SLEWFAST_RESET _u(0x0) -#define PADS_BANK0_GPIO37_SLEWFAST_BITS _u(0x00000001) -#define PADS_BANK0_GPIO37_SLEWFAST_MSB _u(0) -#define PADS_BANK0_GPIO37_SLEWFAST_LSB _u(0) -#define PADS_BANK0_GPIO37_SLEWFAST_ACCESS "RW" -// ============================================================================= -// Register : PADS_BANK0_GPIO38 -#define PADS_BANK0_GPIO38_OFFSET _u(0x0000009c) -#define PADS_BANK0_GPIO38_BITS _u(0x000001ff) -#define PADS_BANK0_GPIO38_RESET _u(0x00000116) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO38_ISO -// Description : Pad isolation control. Remove this once the pad is configured -// by software. -#define PADS_BANK0_GPIO38_ISO_RESET _u(0x1) -#define PADS_BANK0_GPIO38_ISO_BITS _u(0x00000100) -#define PADS_BANK0_GPIO38_ISO_MSB _u(8) -#define PADS_BANK0_GPIO38_ISO_LSB _u(8) -#define PADS_BANK0_GPIO38_ISO_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO38_OD -// Description : Output disable. Has priority over output enable from -// peripherals -#define PADS_BANK0_GPIO38_OD_RESET _u(0x0) -#define PADS_BANK0_GPIO38_OD_BITS _u(0x00000080) -#define PADS_BANK0_GPIO38_OD_MSB _u(7) -#define PADS_BANK0_GPIO38_OD_LSB _u(7) -#define PADS_BANK0_GPIO38_OD_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO38_IE -// Description : Input enable -#define PADS_BANK0_GPIO38_IE_RESET _u(0x0) -#define PADS_BANK0_GPIO38_IE_BITS _u(0x00000040) -#define PADS_BANK0_GPIO38_IE_MSB _u(6) -#define PADS_BANK0_GPIO38_IE_LSB _u(6) -#define PADS_BANK0_GPIO38_IE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO38_DRIVE -// Description : Drive strength. -// 0x0 -> 2mA -// 0x1 -> 4mA -// 0x2 -> 8mA -// 0x3 -> 12mA -#define PADS_BANK0_GPIO38_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO38_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO38_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO38_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO38_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO38_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO38_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO38_DRIVE_VALUE_8MA _u(0x2) -#define PADS_BANK0_GPIO38_DRIVE_VALUE_12MA _u(0x3) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO38_PUE -// Description : Pull up enable -#define PADS_BANK0_GPIO38_PUE_RESET _u(0x0) -#define PADS_BANK0_GPIO38_PUE_BITS _u(0x00000008) -#define PADS_BANK0_GPIO38_PUE_MSB _u(3) -#define PADS_BANK0_GPIO38_PUE_LSB _u(3) -#define PADS_BANK0_GPIO38_PUE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO38_PDE -// Description : Pull down enable -#define PADS_BANK0_GPIO38_PDE_RESET _u(0x1) -#define PADS_BANK0_GPIO38_PDE_BITS _u(0x00000004) -#define PADS_BANK0_GPIO38_PDE_MSB _u(2) -#define PADS_BANK0_GPIO38_PDE_LSB _u(2) -#define PADS_BANK0_GPIO38_PDE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO38_SCHMITT -// Description : Enable schmitt trigger -#define PADS_BANK0_GPIO38_SCHMITT_RESET _u(0x1) -#define PADS_BANK0_GPIO38_SCHMITT_BITS _u(0x00000002) -#define PADS_BANK0_GPIO38_SCHMITT_MSB _u(1) -#define PADS_BANK0_GPIO38_SCHMITT_LSB _u(1) -#define PADS_BANK0_GPIO38_SCHMITT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO38_SLEWFAST -// Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO38_SLEWFAST_RESET _u(0x0) -#define PADS_BANK0_GPIO38_SLEWFAST_BITS _u(0x00000001) -#define PADS_BANK0_GPIO38_SLEWFAST_MSB _u(0) -#define PADS_BANK0_GPIO38_SLEWFAST_LSB _u(0) -#define PADS_BANK0_GPIO38_SLEWFAST_ACCESS "RW" -// ============================================================================= -// Register : PADS_BANK0_GPIO39 -#define PADS_BANK0_GPIO39_OFFSET _u(0x000000a0) -#define PADS_BANK0_GPIO39_BITS _u(0x000001ff) -#define PADS_BANK0_GPIO39_RESET _u(0x00000116) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO39_ISO -// Description : Pad isolation control. Remove this once the pad is configured -// by software. -#define PADS_BANK0_GPIO39_ISO_RESET _u(0x1) -#define PADS_BANK0_GPIO39_ISO_BITS _u(0x00000100) -#define PADS_BANK0_GPIO39_ISO_MSB _u(8) -#define PADS_BANK0_GPIO39_ISO_LSB _u(8) -#define PADS_BANK0_GPIO39_ISO_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO39_OD -// Description : Output disable. Has priority over output enable from -// peripherals -#define PADS_BANK0_GPIO39_OD_RESET _u(0x0) -#define PADS_BANK0_GPIO39_OD_BITS _u(0x00000080) -#define PADS_BANK0_GPIO39_OD_MSB _u(7) -#define PADS_BANK0_GPIO39_OD_LSB _u(7) -#define PADS_BANK0_GPIO39_OD_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO39_IE -// Description : Input enable -#define PADS_BANK0_GPIO39_IE_RESET _u(0x0) -#define PADS_BANK0_GPIO39_IE_BITS _u(0x00000040) -#define PADS_BANK0_GPIO39_IE_MSB _u(6) -#define PADS_BANK0_GPIO39_IE_LSB _u(6) -#define PADS_BANK0_GPIO39_IE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO39_DRIVE -// Description : Drive strength. -// 0x0 -> 2mA -// 0x1 -> 4mA -// 0x2 -> 8mA -// 0x3 -> 12mA -#define PADS_BANK0_GPIO39_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO39_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO39_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO39_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO39_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO39_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO39_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO39_DRIVE_VALUE_8MA _u(0x2) -#define PADS_BANK0_GPIO39_DRIVE_VALUE_12MA _u(0x3) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO39_PUE -// Description : Pull up enable -#define PADS_BANK0_GPIO39_PUE_RESET _u(0x0) -#define PADS_BANK0_GPIO39_PUE_BITS _u(0x00000008) -#define PADS_BANK0_GPIO39_PUE_MSB _u(3) -#define PADS_BANK0_GPIO39_PUE_LSB _u(3) -#define PADS_BANK0_GPIO39_PUE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO39_PDE -// Description : Pull down enable -#define PADS_BANK0_GPIO39_PDE_RESET _u(0x1) -#define PADS_BANK0_GPIO39_PDE_BITS _u(0x00000004) -#define PADS_BANK0_GPIO39_PDE_MSB _u(2) -#define PADS_BANK0_GPIO39_PDE_LSB _u(2) -#define PADS_BANK0_GPIO39_PDE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO39_SCHMITT -// Description : Enable schmitt trigger -#define PADS_BANK0_GPIO39_SCHMITT_RESET _u(0x1) -#define PADS_BANK0_GPIO39_SCHMITT_BITS _u(0x00000002) -#define PADS_BANK0_GPIO39_SCHMITT_MSB _u(1) -#define PADS_BANK0_GPIO39_SCHMITT_LSB _u(1) -#define PADS_BANK0_GPIO39_SCHMITT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO39_SLEWFAST -// Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO39_SLEWFAST_RESET _u(0x0) -#define PADS_BANK0_GPIO39_SLEWFAST_BITS _u(0x00000001) -#define PADS_BANK0_GPIO39_SLEWFAST_MSB _u(0) -#define PADS_BANK0_GPIO39_SLEWFAST_LSB _u(0) -#define PADS_BANK0_GPIO39_SLEWFAST_ACCESS "RW" -// ============================================================================= -// Register : PADS_BANK0_GPIO40 -#define PADS_BANK0_GPIO40_OFFSET _u(0x000000a4) -#define PADS_BANK0_GPIO40_BITS _u(0x000001ff) -#define PADS_BANK0_GPIO40_RESET _u(0x00000116) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO40_ISO -// Description : Pad isolation control. Remove this once the pad is configured -// by software. -#define PADS_BANK0_GPIO40_ISO_RESET _u(0x1) -#define PADS_BANK0_GPIO40_ISO_BITS _u(0x00000100) -#define PADS_BANK0_GPIO40_ISO_MSB _u(8) -#define PADS_BANK0_GPIO40_ISO_LSB _u(8) -#define PADS_BANK0_GPIO40_ISO_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO40_OD -// Description : Output disable. Has priority over output enable from -// peripherals -#define PADS_BANK0_GPIO40_OD_RESET _u(0x0) -#define PADS_BANK0_GPIO40_OD_BITS _u(0x00000080) -#define PADS_BANK0_GPIO40_OD_MSB _u(7) -#define PADS_BANK0_GPIO40_OD_LSB _u(7) -#define PADS_BANK0_GPIO40_OD_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO40_IE -// Description : Input enable -#define PADS_BANK0_GPIO40_IE_RESET _u(0x0) -#define PADS_BANK0_GPIO40_IE_BITS _u(0x00000040) -#define PADS_BANK0_GPIO40_IE_MSB _u(6) -#define PADS_BANK0_GPIO40_IE_LSB _u(6) -#define PADS_BANK0_GPIO40_IE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO40_DRIVE -// Description : Drive strength. -// 0x0 -> 2mA -// 0x1 -> 4mA -// 0x2 -> 8mA -// 0x3 -> 12mA -#define PADS_BANK0_GPIO40_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO40_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO40_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO40_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO40_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO40_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO40_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO40_DRIVE_VALUE_8MA _u(0x2) -#define PADS_BANK0_GPIO40_DRIVE_VALUE_12MA _u(0x3) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO40_PUE -// Description : Pull up enable -#define PADS_BANK0_GPIO40_PUE_RESET _u(0x0) -#define PADS_BANK0_GPIO40_PUE_BITS _u(0x00000008) -#define PADS_BANK0_GPIO40_PUE_MSB _u(3) -#define PADS_BANK0_GPIO40_PUE_LSB _u(3) -#define PADS_BANK0_GPIO40_PUE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO40_PDE -// Description : Pull down enable -#define PADS_BANK0_GPIO40_PDE_RESET _u(0x1) -#define PADS_BANK0_GPIO40_PDE_BITS _u(0x00000004) -#define PADS_BANK0_GPIO40_PDE_MSB _u(2) -#define PADS_BANK0_GPIO40_PDE_LSB _u(2) -#define PADS_BANK0_GPIO40_PDE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO40_SCHMITT -// Description : Enable schmitt trigger -#define PADS_BANK0_GPIO40_SCHMITT_RESET _u(0x1) -#define PADS_BANK0_GPIO40_SCHMITT_BITS _u(0x00000002) -#define PADS_BANK0_GPIO40_SCHMITT_MSB _u(1) -#define PADS_BANK0_GPIO40_SCHMITT_LSB _u(1) -#define PADS_BANK0_GPIO40_SCHMITT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO40_SLEWFAST -// Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO40_SLEWFAST_RESET _u(0x0) -#define PADS_BANK0_GPIO40_SLEWFAST_BITS _u(0x00000001) -#define PADS_BANK0_GPIO40_SLEWFAST_MSB _u(0) -#define PADS_BANK0_GPIO40_SLEWFAST_LSB _u(0) -#define PADS_BANK0_GPIO40_SLEWFAST_ACCESS "RW" -// ============================================================================= -// Register : PADS_BANK0_GPIO41 -#define PADS_BANK0_GPIO41_OFFSET _u(0x000000a8) -#define PADS_BANK0_GPIO41_BITS _u(0x000001ff) -#define PADS_BANK0_GPIO41_RESET _u(0x00000116) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO41_ISO -// Description : Pad isolation control. Remove this once the pad is configured -// by software. -#define PADS_BANK0_GPIO41_ISO_RESET _u(0x1) -#define PADS_BANK0_GPIO41_ISO_BITS _u(0x00000100) -#define PADS_BANK0_GPIO41_ISO_MSB _u(8) -#define PADS_BANK0_GPIO41_ISO_LSB _u(8) -#define PADS_BANK0_GPIO41_ISO_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO41_OD -// Description : Output disable. Has priority over output enable from -// peripherals -#define PADS_BANK0_GPIO41_OD_RESET _u(0x0) -#define PADS_BANK0_GPIO41_OD_BITS _u(0x00000080) -#define PADS_BANK0_GPIO41_OD_MSB _u(7) -#define PADS_BANK0_GPIO41_OD_LSB _u(7) -#define PADS_BANK0_GPIO41_OD_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO41_IE -// Description : Input enable -#define PADS_BANK0_GPIO41_IE_RESET _u(0x0) -#define PADS_BANK0_GPIO41_IE_BITS _u(0x00000040) -#define PADS_BANK0_GPIO41_IE_MSB _u(6) -#define PADS_BANK0_GPIO41_IE_LSB _u(6) -#define PADS_BANK0_GPIO41_IE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO41_DRIVE -// Description : Drive strength. -// 0x0 -> 2mA -// 0x1 -> 4mA -// 0x2 -> 8mA -// 0x3 -> 12mA -#define PADS_BANK0_GPIO41_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO41_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO41_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO41_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO41_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO41_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO41_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO41_DRIVE_VALUE_8MA _u(0x2) -#define PADS_BANK0_GPIO41_DRIVE_VALUE_12MA _u(0x3) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO41_PUE -// Description : Pull up enable -#define PADS_BANK0_GPIO41_PUE_RESET _u(0x0) -#define PADS_BANK0_GPIO41_PUE_BITS _u(0x00000008) -#define PADS_BANK0_GPIO41_PUE_MSB _u(3) -#define PADS_BANK0_GPIO41_PUE_LSB _u(3) -#define PADS_BANK0_GPIO41_PUE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO41_PDE -// Description : Pull down enable -#define PADS_BANK0_GPIO41_PDE_RESET _u(0x1) -#define PADS_BANK0_GPIO41_PDE_BITS _u(0x00000004) -#define PADS_BANK0_GPIO41_PDE_MSB _u(2) -#define PADS_BANK0_GPIO41_PDE_LSB _u(2) -#define PADS_BANK0_GPIO41_PDE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO41_SCHMITT -// Description : Enable schmitt trigger -#define PADS_BANK0_GPIO41_SCHMITT_RESET _u(0x1) -#define PADS_BANK0_GPIO41_SCHMITT_BITS _u(0x00000002) -#define PADS_BANK0_GPIO41_SCHMITT_MSB _u(1) -#define PADS_BANK0_GPIO41_SCHMITT_LSB _u(1) -#define PADS_BANK0_GPIO41_SCHMITT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO41_SLEWFAST -// Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO41_SLEWFAST_RESET _u(0x0) -#define PADS_BANK0_GPIO41_SLEWFAST_BITS _u(0x00000001) -#define PADS_BANK0_GPIO41_SLEWFAST_MSB _u(0) -#define PADS_BANK0_GPIO41_SLEWFAST_LSB _u(0) -#define PADS_BANK0_GPIO41_SLEWFAST_ACCESS "RW" -// ============================================================================= -// Register : PADS_BANK0_GPIO42 -#define PADS_BANK0_GPIO42_OFFSET _u(0x000000ac) -#define PADS_BANK0_GPIO42_BITS _u(0x000001ff) -#define PADS_BANK0_GPIO42_RESET _u(0x00000116) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO42_ISO -// Description : Pad isolation control. Remove this once the pad is configured -// by software. -#define PADS_BANK0_GPIO42_ISO_RESET _u(0x1) -#define PADS_BANK0_GPIO42_ISO_BITS _u(0x00000100) -#define PADS_BANK0_GPIO42_ISO_MSB _u(8) -#define PADS_BANK0_GPIO42_ISO_LSB _u(8) -#define PADS_BANK0_GPIO42_ISO_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO42_OD -// Description : Output disable. Has priority over output enable from -// peripherals -#define PADS_BANK0_GPIO42_OD_RESET _u(0x0) -#define PADS_BANK0_GPIO42_OD_BITS _u(0x00000080) -#define PADS_BANK0_GPIO42_OD_MSB _u(7) -#define PADS_BANK0_GPIO42_OD_LSB _u(7) -#define PADS_BANK0_GPIO42_OD_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO42_IE -// Description : Input enable -#define PADS_BANK0_GPIO42_IE_RESET _u(0x0) -#define PADS_BANK0_GPIO42_IE_BITS _u(0x00000040) -#define PADS_BANK0_GPIO42_IE_MSB _u(6) -#define PADS_BANK0_GPIO42_IE_LSB _u(6) -#define PADS_BANK0_GPIO42_IE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO42_DRIVE -// Description : Drive strength. -// 0x0 -> 2mA -// 0x1 -> 4mA -// 0x2 -> 8mA -// 0x3 -> 12mA -#define PADS_BANK0_GPIO42_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO42_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO42_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO42_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO42_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO42_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO42_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO42_DRIVE_VALUE_8MA _u(0x2) -#define PADS_BANK0_GPIO42_DRIVE_VALUE_12MA _u(0x3) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO42_PUE -// Description : Pull up enable -#define PADS_BANK0_GPIO42_PUE_RESET _u(0x0) -#define PADS_BANK0_GPIO42_PUE_BITS _u(0x00000008) -#define PADS_BANK0_GPIO42_PUE_MSB _u(3) -#define PADS_BANK0_GPIO42_PUE_LSB _u(3) -#define PADS_BANK0_GPIO42_PUE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO42_PDE -// Description : Pull down enable -#define PADS_BANK0_GPIO42_PDE_RESET _u(0x1) -#define PADS_BANK0_GPIO42_PDE_BITS _u(0x00000004) -#define PADS_BANK0_GPIO42_PDE_MSB _u(2) -#define PADS_BANK0_GPIO42_PDE_LSB _u(2) -#define PADS_BANK0_GPIO42_PDE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO42_SCHMITT -// Description : Enable schmitt trigger -#define PADS_BANK0_GPIO42_SCHMITT_RESET _u(0x1) -#define PADS_BANK0_GPIO42_SCHMITT_BITS _u(0x00000002) -#define PADS_BANK0_GPIO42_SCHMITT_MSB _u(1) -#define PADS_BANK0_GPIO42_SCHMITT_LSB _u(1) -#define PADS_BANK0_GPIO42_SCHMITT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO42_SLEWFAST -// Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO42_SLEWFAST_RESET _u(0x0) -#define PADS_BANK0_GPIO42_SLEWFAST_BITS _u(0x00000001) -#define PADS_BANK0_GPIO42_SLEWFAST_MSB _u(0) -#define PADS_BANK0_GPIO42_SLEWFAST_LSB _u(0) -#define PADS_BANK0_GPIO42_SLEWFAST_ACCESS "RW" -// ============================================================================= -// Register : PADS_BANK0_GPIO43 -#define PADS_BANK0_GPIO43_OFFSET _u(0x000000b0) -#define PADS_BANK0_GPIO43_BITS _u(0x000001ff) -#define PADS_BANK0_GPIO43_RESET _u(0x00000116) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO43_ISO -// Description : Pad isolation control. Remove this once the pad is configured -// by software. -#define PADS_BANK0_GPIO43_ISO_RESET _u(0x1) -#define PADS_BANK0_GPIO43_ISO_BITS _u(0x00000100) -#define PADS_BANK0_GPIO43_ISO_MSB _u(8) -#define PADS_BANK0_GPIO43_ISO_LSB _u(8) -#define PADS_BANK0_GPIO43_ISO_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO43_OD -// Description : Output disable. Has priority over output enable from -// peripherals -#define PADS_BANK0_GPIO43_OD_RESET _u(0x0) -#define PADS_BANK0_GPIO43_OD_BITS _u(0x00000080) -#define PADS_BANK0_GPIO43_OD_MSB _u(7) -#define PADS_BANK0_GPIO43_OD_LSB _u(7) -#define PADS_BANK0_GPIO43_OD_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO43_IE -// Description : Input enable -#define PADS_BANK0_GPIO43_IE_RESET _u(0x0) -#define PADS_BANK0_GPIO43_IE_BITS _u(0x00000040) -#define PADS_BANK0_GPIO43_IE_MSB _u(6) -#define PADS_BANK0_GPIO43_IE_LSB _u(6) -#define PADS_BANK0_GPIO43_IE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO43_DRIVE -// Description : Drive strength. -// 0x0 -> 2mA -// 0x1 -> 4mA -// 0x2 -> 8mA -// 0x3 -> 12mA -#define PADS_BANK0_GPIO43_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO43_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO43_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO43_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO43_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO43_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO43_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO43_DRIVE_VALUE_8MA _u(0x2) -#define PADS_BANK0_GPIO43_DRIVE_VALUE_12MA _u(0x3) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO43_PUE -// Description : Pull up enable -#define PADS_BANK0_GPIO43_PUE_RESET _u(0x0) -#define PADS_BANK0_GPIO43_PUE_BITS _u(0x00000008) -#define PADS_BANK0_GPIO43_PUE_MSB _u(3) -#define PADS_BANK0_GPIO43_PUE_LSB _u(3) -#define PADS_BANK0_GPIO43_PUE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO43_PDE -// Description : Pull down enable -#define PADS_BANK0_GPIO43_PDE_RESET _u(0x1) -#define PADS_BANK0_GPIO43_PDE_BITS _u(0x00000004) -#define PADS_BANK0_GPIO43_PDE_MSB _u(2) -#define PADS_BANK0_GPIO43_PDE_LSB _u(2) -#define PADS_BANK0_GPIO43_PDE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO43_SCHMITT -// Description : Enable schmitt trigger -#define PADS_BANK0_GPIO43_SCHMITT_RESET _u(0x1) -#define PADS_BANK0_GPIO43_SCHMITT_BITS _u(0x00000002) -#define PADS_BANK0_GPIO43_SCHMITT_MSB _u(1) -#define PADS_BANK0_GPIO43_SCHMITT_LSB _u(1) -#define PADS_BANK0_GPIO43_SCHMITT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO43_SLEWFAST -// Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO43_SLEWFAST_RESET _u(0x0) -#define PADS_BANK0_GPIO43_SLEWFAST_BITS _u(0x00000001) -#define PADS_BANK0_GPIO43_SLEWFAST_MSB _u(0) -#define PADS_BANK0_GPIO43_SLEWFAST_LSB _u(0) -#define PADS_BANK0_GPIO43_SLEWFAST_ACCESS "RW" -// ============================================================================= -// Register : PADS_BANK0_GPIO44 -#define PADS_BANK0_GPIO44_OFFSET _u(0x000000b4) -#define PADS_BANK0_GPIO44_BITS _u(0x000001ff) -#define PADS_BANK0_GPIO44_RESET _u(0x00000116) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO44_ISO -// Description : Pad isolation control. Remove this once the pad is configured -// by software. -#define PADS_BANK0_GPIO44_ISO_RESET _u(0x1) -#define PADS_BANK0_GPIO44_ISO_BITS _u(0x00000100) -#define PADS_BANK0_GPIO44_ISO_MSB _u(8) -#define PADS_BANK0_GPIO44_ISO_LSB _u(8) -#define PADS_BANK0_GPIO44_ISO_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO44_OD -// Description : Output disable. Has priority over output enable from -// peripherals -#define PADS_BANK0_GPIO44_OD_RESET _u(0x0) -#define PADS_BANK0_GPIO44_OD_BITS _u(0x00000080) -#define PADS_BANK0_GPIO44_OD_MSB _u(7) -#define PADS_BANK0_GPIO44_OD_LSB _u(7) -#define PADS_BANK0_GPIO44_OD_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO44_IE -// Description : Input enable -#define PADS_BANK0_GPIO44_IE_RESET _u(0x0) -#define PADS_BANK0_GPIO44_IE_BITS _u(0x00000040) -#define PADS_BANK0_GPIO44_IE_MSB _u(6) -#define PADS_BANK0_GPIO44_IE_LSB _u(6) -#define PADS_BANK0_GPIO44_IE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO44_DRIVE -// Description : Drive strength. -// 0x0 -> 2mA -// 0x1 -> 4mA -// 0x2 -> 8mA -// 0x3 -> 12mA -#define PADS_BANK0_GPIO44_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO44_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO44_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO44_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO44_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO44_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO44_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO44_DRIVE_VALUE_8MA _u(0x2) -#define PADS_BANK0_GPIO44_DRIVE_VALUE_12MA _u(0x3) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO44_PUE -// Description : Pull up enable -#define PADS_BANK0_GPIO44_PUE_RESET _u(0x0) -#define PADS_BANK0_GPIO44_PUE_BITS _u(0x00000008) -#define PADS_BANK0_GPIO44_PUE_MSB _u(3) -#define PADS_BANK0_GPIO44_PUE_LSB _u(3) -#define PADS_BANK0_GPIO44_PUE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO44_PDE -// Description : Pull down enable -#define PADS_BANK0_GPIO44_PDE_RESET _u(0x1) -#define PADS_BANK0_GPIO44_PDE_BITS _u(0x00000004) -#define PADS_BANK0_GPIO44_PDE_MSB _u(2) -#define PADS_BANK0_GPIO44_PDE_LSB _u(2) -#define PADS_BANK0_GPIO44_PDE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO44_SCHMITT -// Description : Enable schmitt trigger -#define PADS_BANK0_GPIO44_SCHMITT_RESET _u(0x1) -#define PADS_BANK0_GPIO44_SCHMITT_BITS _u(0x00000002) -#define PADS_BANK0_GPIO44_SCHMITT_MSB _u(1) -#define PADS_BANK0_GPIO44_SCHMITT_LSB _u(1) -#define PADS_BANK0_GPIO44_SCHMITT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO44_SLEWFAST -// Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO44_SLEWFAST_RESET _u(0x0) -#define PADS_BANK0_GPIO44_SLEWFAST_BITS _u(0x00000001) -#define PADS_BANK0_GPIO44_SLEWFAST_MSB _u(0) -#define PADS_BANK0_GPIO44_SLEWFAST_LSB _u(0) -#define PADS_BANK0_GPIO44_SLEWFAST_ACCESS "RW" -// ============================================================================= -// Register : PADS_BANK0_GPIO45 -#define PADS_BANK0_GPIO45_OFFSET _u(0x000000b8) -#define PADS_BANK0_GPIO45_BITS _u(0x000001ff) -#define PADS_BANK0_GPIO45_RESET _u(0x00000116) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO45_ISO -// Description : Pad isolation control. Remove this once the pad is configured -// by software. -#define PADS_BANK0_GPIO45_ISO_RESET _u(0x1) -#define PADS_BANK0_GPIO45_ISO_BITS _u(0x00000100) -#define PADS_BANK0_GPIO45_ISO_MSB _u(8) -#define PADS_BANK0_GPIO45_ISO_LSB _u(8) -#define PADS_BANK0_GPIO45_ISO_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO45_OD -// Description : Output disable. Has priority over output enable from -// peripherals -#define PADS_BANK0_GPIO45_OD_RESET _u(0x0) -#define PADS_BANK0_GPIO45_OD_BITS _u(0x00000080) -#define PADS_BANK0_GPIO45_OD_MSB _u(7) -#define PADS_BANK0_GPIO45_OD_LSB _u(7) -#define PADS_BANK0_GPIO45_OD_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO45_IE -// Description : Input enable -#define PADS_BANK0_GPIO45_IE_RESET _u(0x0) -#define PADS_BANK0_GPIO45_IE_BITS _u(0x00000040) -#define PADS_BANK0_GPIO45_IE_MSB _u(6) -#define PADS_BANK0_GPIO45_IE_LSB _u(6) -#define PADS_BANK0_GPIO45_IE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO45_DRIVE -// Description : Drive strength. -// 0x0 -> 2mA -// 0x1 -> 4mA -// 0x2 -> 8mA -// 0x3 -> 12mA -#define PADS_BANK0_GPIO45_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO45_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO45_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO45_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO45_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO45_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO45_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO45_DRIVE_VALUE_8MA _u(0x2) -#define PADS_BANK0_GPIO45_DRIVE_VALUE_12MA _u(0x3) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO45_PUE -// Description : Pull up enable -#define PADS_BANK0_GPIO45_PUE_RESET _u(0x0) -#define PADS_BANK0_GPIO45_PUE_BITS _u(0x00000008) -#define PADS_BANK0_GPIO45_PUE_MSB _u(3) -#define PADS_BANK0_GPIO45_PUE_LSB _u(3) -#define PADS_BANK0_GPIO45_PUE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO45_PDE -// Description : Pull down enable -#define PADS_BANK0_GPIO45_PDE_RESET _u(0x1) -#define PADS_BANK0_GPIO45_PDE_BITS _u(0x00000004) -#define PADS_BANK0_GPIO45_PDE_MSB _u(2) -#define PADS_BANK0_GPIO45_PDE_LSB _u(2) -#define PADS_BANK0_GPIO45_PDE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO45_SCHMITT -// Description : Enable schmitt trigger -#define PADS_BANK0_GPIO45_SCHMITT_RESET _u(0x1) -#define PADS_BANK0_GPIO45_SCHMITT_BITS _u(0x00000002) -#define PADS_BANK0_GPIO45_SCHMITT_MSB _u(1) -#define PADS_BANK0_GPIO45_SCHMITT_LSB _u(1) -#define PADS_BANK0_GPIO45_SCHMITT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO45_SLEWFAST -// Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO45_SLEWFAST_RESET _u(0x0) -#define PADS_BANK0_GPIO45_SLEWFAST_BITS _u(0x00000001) -#define PADS_BANK0_GPIO45_SLEWFAST_MSB _u(0) -#define PADS_BANK0_GPIO45_SLEWFAST_LSB _u(0) -#define PADS_BANK0_GPIO45_SLEWFAST_ACCESS "RW" -// ============================================================================= -// Register : PADS_BANK0_GPIO46 -#define PADS_BANK0_GPIO46_OFFSET _u(0x000000bc) -#define PADS_BANK0_GPIO46_BITS _u(0x000001ff) -#define PADS_BANK0_GPIO46_RESET _u(0x00000116) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO46_ISO -// Description : Pad isolation control. Remove this once the pad is configured -// by software. -#define PADS_BANK0_GPIO46_ISO_RESET _u(0x1) -#define PADS_BANK0_GPIO46_ISO_BITS _u(0x00000100) -#define PADS_BANK0_GPIO46_ISO_MSB _u(8) -#define PADS_BANK0_GPIO46_ISO_LSB _u(8) -#define PADS_BANK0_GPIO46_ISO_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO46_OD -// Description : Output disable. Has priority over output enable from -// peripherals -#define PADS_BANK0_GPIO46_OD_RESET _u(0x0) -#define PADS_BANK0_GPIO46_OD_BITS _u(0x00000080) -#define PADS_BANK0_GPIO46_OD_MSB _u(7) -#define PADS_BANK0_GPIO46_OD_LSB _u(7) -#define PADS_BANK0_GPIO46_OD_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO46_IE -// Description : Input enable -#define PADS_BANK0_GPIO46_IE_RESET _u(0x0) -#define PADS_BANK0_GPIO46_IE_BITS _u(0x00000040) -#define PADS_BANK0_GPIO46_IE_MSB _u(6) -#define PADS_BANK0_GPIO46_IE_LSB _u(6) -#define PADS_BANK0_GPIO46_IE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO46_DRIVE -// Description : Drive strength. -// 0x0 -> 2mA -// 0x1 -> 4mA -// 0x2 -> 8mA -// 0x3 -> 12mA -#define PADS_BANK0_GPIO46_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO46_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO46_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO46_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO46_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO46_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO46_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO46_DRIVE_VALUE_8MA _u(0x2) -#define PADS_BANK0_GPIO46_DRIVE_VALUE_12MA _u(0x3) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO46_PUE -// Description : Pull up enable -#define PADS_BANK0_GPIO46_PUE_RESET _u(0x0) -#define PADS_BANK0_GPIO46_PUE_BITS _u(0x00000008) -#define PADS_BANK0_GPIO46_PUE_MSB _u(3) -#define PADS_BANK0_GPIO46_PUE_LSB _u(3) -#define PADS_BANK0_GPIO46_PUE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO46_PDE -// Description : Pull down enable -#define PADS_BANK0_GPIO46_PDE_RESET _u(0x1) -#define PADS_BANK0_GPIO46_PDE_BITS _u(0x00000004) -#define PADS_BANK0_GPIO46_PDE_MSB _u(2) -#define PADS_BANK0_GPIO46_PDE_LSB _u(2) -#define PADS_BANK0_GPIO46_PDE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO46_SCHMITT -// Description : Enable schmitt trigger -#define PADS_BANK0_GPIO46_SCHMITT_RESET _u(0x1) -#define PADS_BANK0_GPIO46_SCHMITT_BITS _u(0x00000002) -#define PADS_BANK0_GPIO46_SCHMITT_MSB _u(1) -#define PADS_BANK0_GPIO46_SCHMITT_LSB _u(1) -#define PADS_BANK0_GPIO46_SCHMITT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO46_SLEWFAST -// Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO46_SLEWFAST_RESET _u(0x0) -#define PADS_BANK0_GPIO46_SLEWFAST_BITS _u(0x00000001) -#define PADS_BANK0_GPIO46_SLEWFAST_MSB _u(0) -#define PADS_BANK0_GPIO46_SLEWFAST_LSB _u(0) -#define PADS_BANK0_GPIO46_SLEWFAST_ACCESS "RW" -// ============================================================================= -// Register : PADS_BANK0_GPIO47 -#define PADS_BANK0_GPIO47_OFFSET _u(0x000000c0) -#define PADS_BANK0_GPIO47_BITS _u(0x000001ff) -#define PADS_BANK0_GPIO47_RESET _u(0x00000116) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO47_ISO -// Description : Pad isolation control. Remove this once the pad is configured -// by software. -#define PADS_BANK0_GPIO47_ISO_RESET _u(0x1) -#define PADS_BANK0_GPIO47_ISO_BITS _u(0x00000100) -#define PADS_BANK0_GPIO47_ISO_MSB _u(8) -#define PADS_BANK0_GPIO47_ISO_LSB _u(8) -#define PADS_BANK0_GPIO47_ISO_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO47_OD -// Description : Output disable. Has priority over output enable from -// peripherals -#define PADS_BANK0_GPIO47_OD_RESET _u(0x0) -#define PADS_BANK0_GPIO47_OD_BITS _u(0x00000080) -#define PADS_BANK0_GPIO47_OD_MSB _u(7) -#define PADS_BANK0_GPIO47_OD_LSB _u(7) -#define PADS_BANK0_GPIO47_OD_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO47_IE -// Description : Input enable -#define PADS_BANK0_GPIO47_IE_RESET _u(0x0) -#define PADS_BANK0_GPIO47_IE_BITS _u(0x00000040) -#define PADS_BANK0_GPIO47_IE_MSB _u(6) -#define PADS_BANK0_GPIO47_IE_LSB _u(6) -#define PADS_BANK0_GPIO47_IE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO47_DRIVE -// Description : Drive strength. -// 0x0 -> 2mA -// 0x1 -> 4mA -// 0x2 -> 8mA -// 0x3 -> 12mA -#define PADS_BANK0_GPIO47_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO47_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO47_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO47_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO47_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO47_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO47_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO47_DRIVE_VALUE_8MA _u(0x2) -#define PADS_BANK0_GPIO47_DRIVE_VALUE_12MA _u(0x3) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO47_PUE -// Description : Pull up enable -#define PADS_BANK0_GPIO47_PUE_RESET _u(0x0) -#define PADS_BANK0_GPIO47_PUE_BITS _u(0x00000008) -#define PADS_BANK0_GPIO47_PUE_MSB _u(3) -#define PADS_BANK0_GPIO47_PUE_LSB _u(3) -#define PADS_BANK0_GPIO47_PUE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO47_PDE -// Description : Pull down enable -#define PADS_BANK0_GPIO47_PDE_RESET _u(0x1) -#define PADS_BANK0_GPIO47_PDE_BITS _u(0x00000004) -#define PADS_BANK0_GPIO47_PDE_MSB _u(2) -#define PADS_BANK0_GPIO47_PDE_LSB _u(2) -#define PADS_BANK0_GPIO47_PDE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO47_SCHMITT -// Description : Enable schmitt trigger -#define PADS_BANK0_GPIO47_SCHMITT_RESET _u(0x1) -#define PADS_BANK0_GPIO47_SCHMITT_BITS _u(0x00000002) -#define PADS_BANK0_GPIO47_SCHMITT_MSB _u(1) -#define PADS_BANK0_GPIO47_SCHMITT_LSB _u(1) -#define PADS_BANK0_GPIO47_SCHMITT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_GPIO47_SLEWFAST -// Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO47_SLEWFAST_RESET _u(0x0) -#define PADS_BANK0_GPIO47_SLEWFAST_BITS _u(0x00000001) -#define PADS_BANK0_GPIO47_SLEWFAST_MSB _u(0) -#define PADS_BANK0_GPIO47_SLEWFAST_LSB _u(0) -#define PADS_BANK0_GPIO47_SLEWFAST_ACCESS "RW" -// ============================================================================= -// Register : PADS_BANK0_SWCLK -#define PADS_BANK0_SWCLK_OFFSET _u(0x000000c4) -#define PADS_BANK0_SWCLK_BITS _u(0x000001ff) -#define PADS_BANK0_SWCLK_RESET _u(0x0000005a) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_SWCLK_ISO -// Description : Pad isolation control. Remove this once the pad is configured -// by software. -#define PADS_BANK0_SWCLK_ISO_RESET _u(0x0) -#define PADS_BANK0_SWCLK_ISO_BITS _u(0x00000100) -#define PADS_BANK0_SWCLK_ISO_MSB _u(8) -#define PADS_BANK0_SWCLK_ISO_LSB _u(8) -#define PADS_BANK0_SWCLK_ISO_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_SWCLK_OD -// Description : Output disable. Has priority over output enable from -// peripherals -#define PADS_BANK0_SWCLK_OD_RESET _u(0x0) -#define PADS_BANK0_SWCLK_OD_BITS _u(0x00000080) -#define PADS_BANK0_SWCLK_OD_MSB _u(7) -#define PADS_BANK0_SWCLK_OD_LSB _u(7) -#define PADS_BANK0_SWCLK_OD_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_SWCLK_IE -// Description : Input enable -#define PADS_BANK0_SWCLK_IE_RESET _u(0x1) -#define PADS_BANK0_SWCLK_IE_BITS _u(0x00000040) -#define PADS_BANK0_SWCLK_IE_MSB _u(6) -#define PADS_BANK0_SWCLK_IE_LSB _u(6) -#define PADS_BANK0_SWCLK_IE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_SWCLK_DRIVE -// Description : Drive strength. -// 0x0 -> 2mA -// 0x1 -> 4mA -// 0x2 -> 8mA -// 0x3 -> 12mA -#define PADS_BANK0_SWCLK_DRIVE_RESET _u(0x1) -#define PADS_BANK0_SWCLK_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_SWCLK_DRIVE_MSB _u(5) -#define PADS_BANK0_SWCLK_DRIVE_LSB _u(4) -#define PADS_BANK0_SWCLK_DRIVE_ACCESS "RW" -#define PADS_BANK0_SWCLK_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_SWCLK_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_SWCLK_DRIVE_VALUE_8MA _u(0x2) -#define PADS_BANK0_SWCLK_DRIVE_VALUE_12MA _u(0x3) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_SWCLK_PUE -// Description : Pull up enable -#define PADS_BANK0_SWCLK_PUE_RESET _u(0x1) -#define PADS_BANK0_SWCLK_PUE_BITS _u(0x00000008) -#define PADS_BANK0_SWCLK_PUE_MSB _u(3) -#define PADS_BANK0_SWCLK_PUE_LSB _u(3) -#define PADS_BANK0_SWCLK_PUE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_SWCLK_PDE -// Description : Pull down enable -#define PADS_BANK0_SWCLK_PDE_RESET _u(0x0) -#define PADS_BANK0_SWCLK_PDE_BITS _u(0x00000004) -#define PADS_BANK0_SWCLK_PDE_MSB _u(2) -#define PADS_BANK0_SWCLK_PDE_LSB _u(2) -#define PADS_BANK0_SWCLK_PDE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_SWCLK_SCHMITT -// Description : Enable schmitt trigger -#define PADS_BANK0_SWCLK_SCHMITT_RESET _u(0x1) -#define PADS_BANK0_SWCLK_SCHMITT_BITS _u(0x00000002) -#define PADS_BANK0_SWCLK_SCHMITT_MSB _u(1) -#define PADS_BANK0_SWCLK_SCHMITT_LSB _u(1) -#define PADS_BANK0_SWCLK_SCHMITT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_SWCLK_SLEWFAST -// Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_SWCLK_SLEWFAST_RESET _u(0x0) -#define PADS_BANK0_SWCLK_SLEWFAST_BITS _u(0x00000001) -#define PADS_BANK0_SWCLK_SLEWFAST_MSB _u(0) -#define PADS_BANK0_SWCLK_SLEWFAST_LSB _u(0) -#define PADS_BANK0_SWCLK_SLEWFAST_ACCESS "RW" -// ============================================================================= -// Register : PADS_BANK0_SWD -#define PADS_BANK0_SWD_OFFSET _u(0x000000c8) -#define PADS_BANK0_SWD_BITS _u(0x000001ff) -#define PADS_BANK0_SWD_RESET _u(0x0000005a) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_SWD_ISO -// Description : Pad isolation control. Remove this once the pad is configured -// by software. -#define PADS_BANK0_SWD_ISO_RESET _u(0x0) -#define PADS_BANK0_SWD_ISO_BITS _u(0x00000100) -#define PADS_BANK0_SWD_ISO_MSB _u(8) -#define PADS_BANK0_SWD_ISO_LSB _u(8) -#define PADS_BANK0_SWD_ISO_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_SWD_OD -// Description : Output disable. Has priority over output enable from -// peripherals -#define PADS_BANK0_SWD_OD_RESET _u(0x0) -#define PADS_BANK0_SWD_OD_BITS _u(0x00000080) -#define PADS_BANK0_SWD_OD_MSB _u(7) -#define PADS_BANK0_SWD_OD_LSB _u(7) -#define PADS_BANK0_SWD_OD_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_SWD_IE -// Description : Input enable -#define PADS_BANK0_SWD_IE_RESET _u(0x1) -#define PADS_BANK0_SWD_IE_BITS _u(0x00000040) -#define PADS_BANK0_SWD_IE_MSB _u(6) -#define PADS_BANK0_SWD_IE_LSB _u(6) -#define PADS_BANK0_SWD_IE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_SWD_DRIVE -// Description : Drive strength. -// 0x0 -> 2mA -// 0x1 -> 4mA -// 0x2 -> 8mA -// 0x3 -> 12mA -#define PADS_BANK0_SWD_DRIVE_RESET _u(0x1) -#define PADS_BANK0_SWD_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_SWD_DRIVE_MSB _u(5) -#define PADS_BANK0_SWD_DRIVE_LSB _u(4) -#define PADS_BANK0_SWD_DRIVE_ACCESS "RW" -#define PADS_BANK0_SWD_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_SWD_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_SWD_DRIVE_VALUE_8MA _u(0x2) -#define PADS_BANK0_SWD_DRIVE_VALUE_12MA _u(0x3) -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_SWD_PUE -// Description : Pull up enable -#define PADS_BANK0_SWD_PUE_RESET _u(0x1) -#define PADS_BANK0_SWD_PUE_BITS _u(0x00000008) -#define PADS_BANK0_SWD_PUE_MSB _u(3) -#define PADS_BANK0_SWD_PUE_LSB _u(3) -#define PADS_BANK0_SWD_PUE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_SWD_PDE -// Description : Pull down enable -#define PADS_BANK0_SWD_PDE_RESET _u(0x0) -#define PADS_BANK0_SWD_PDE_BITS _u(0x00000004) -#define PADS_BANK0_SWD_PDE_MSB _u(2) -#define PADS_BANK0_SWD_PDE_LSB _u(2) -#define PADS_BANK0_SWD_PDE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_SWD_SCHMITT -// Description : Enable schmitt trigger -#define PADS_BANK0_SWD_SCHMITT_RESET _u(0x1) -#define PADS_BANK0_SWD_SCHMITT_BITS _u(0x00000002) -#define PADS_BANK0_SWD_SCHMITT_MSB _u(1) -#define PADS_BANK0_SWD_SCHMITT_LSB _u(1) -#define PADS_BANK0_SWD_SCHMITT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_BANK0_SWD_SLEWFAST -// Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_SWD_SLEWFAST_RESET _u(0x0) -#define PADS_BANK0_SWD_SLEWFAST_BITS _u(0x00000001) -#define PADS_BANK0_SWD_SLEWFAST_MSB _u(0) -#define PADS_BANK0_SWD_SLEWFAST_LSB _u(0) -#define PADS_BANK0_SWD_SLEWFAST_ACCESS "RW" -// ============================================================================= -#endif // _HARDWARE_REGS_PADS_BANK0_H - diff --git a/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/pads_qspi.h b/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/pads_qspi.h deleted file mode 100644 index 5e31fd0421..0000000000 --- a/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/pads_qspi.h +++ /dev/null @@ -1,504 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -// ============================================================================= -// Register block : PADS_QSPI -// Version : 1 -// Bus type : apb -// ============================================================================= -#ifndef _HARDWARE_REGS_PADS_QSPI_H -#define _HARDWARE_REGS_PADS_QSPI_H -// ============================================================================= -// Register : PADS_QSPI_VOLTAGE_SELECT -// Description : Voltage select. Per bank control -// 0x0 -> Set voltage to 3.3V (DVDD >= 2V5) -// 0x1 -> Set voltage to 1.8V (DVDD <= 1V8) -#define PADS_QSPI_VOLTAGE_SELECT_OFFSET _u(0x00000000) -#define PADS_QSPI_VOLTAGE_SELECT_BITS _u(0x00000001) -#define PADS_QSPI_VOLTAGE_SELECT_RESET _u(0x00000000) -#define PADS_QSPI_VOLTAGE_SELECT_MSB _u(0) -#define PADS_QSPI_VOLTAGE_SELECT_LSB _u(0) -#define PADS_QSPI_VOLTAGE_SELECT_ACCESS "RW" -#define PADS_QSPI_VOLTAGE_SELECT_VALUE_3V3 _u(0x0) -#define PADS_QSPI_VOLTAGE_SELECT_VALUE_1V8 _u(0x1) -// ============================================================================= -// Register : PADS_QSPI_GPIO_QSPI_SCLK -#define PADS_QSPI_GPIO_QSPI_SCLK_OFFSET _u(0x00000004) -#define PADS_QSPI_GPIO_QSPI_SCLK_BITS _u(0x000001ff) -#define PADS_QSPI_GPIO_QSPI_SCLK_RESET _u(0x00000156) -// ----------------------------------------------------------------------------- -// Field : PADS_QSPI_GPIO_QSPI_SCLK_ISO -// Description : Pad isolation control. Remove this once the pad is configured -// by software. -#define PADS_QSPI_GPIO_QSPI_SCLK_ISO_RESET _u(0x1) -#define PADS_QSPI_GPIO_QSPI_SCLK_ISO_BITS _u(0x00000100) -#define PADS_QSPI_GPIO_QSPI_SCLK_ISO_MSB _u(8) -#define PADS_QSPI_GPIO_QSPI_SCLK_ISO_LSB _u(8) -#define PADS_QSPI_GPIO_QSPI_SCLK_ISO_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_QSPI_GPIO_QSPI_SCLK_OD -// Description : Output disable. Has priority over output enable from -// peripherals -#define PADS_QSPI_GPIO_QSPI_SCLK_OD_RESET _u(0x0) -#define PADS_QSPI_GPIO_QSPI_SCLK_OD_BITS _u(0x00000080) -#define PADS_QSPI_GPIO_QSPI_SCLK_OD_MSB _u(7) -#define PADS_QSPI_GPIO_QSPI_SCLK_OD_LSB _u(7) -#define PADS_QSPI_GPIO_QSPI_SCLK_OD_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_QSPI_GPIO_QSPI_SCLK_IE -// Description : Input enable -#define PADS_QSPI_GPIO_QSPI_SCLK_IE_RESET _u(0x1) -#define PADS_QSPI_GPIO_QSPI_SCLK_IE_BITS _u(0x00000040) -#define PADS_QSPI_GPIO_QSPI_SCLK_IE_MSB _u(6) -#define PADS_QSPI_GPIO_QSPI_SCLK_IE_LSB _u(6) -#define PADS_QSPI_GPIO_QSPI_SCLK_IE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_QSPI_GPIO_QSPI_SCLK_DRIVE -// Description : Drive strength. -// 0x0 -> 2mA -// 0x1 -> 4mA -// 0x2 -> 8mA -// 0x3 -> 12mA -#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_RESET _u(0x1) -#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_BITS _u(0x00000030) -#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_MSB _u(5) -#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_LSB _u(4) -#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_ACCESS "RW" -#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_VALUE_2MA _u(0x0) -#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_VALUE_4MA _u(0x1) -#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_VALUE_8MA _u(0x2) -#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_VALUE_12MA _u(0x3) -// ----------------------------------------------------------------------------- -// Field : PADS_QSPI_GPIO_QSPI_SCLK_PUE -// Description : Pull up enable -#define PADS_QSPI_GPIO_QSPI_SCLK_PUE_RESET _u(0x0) -#define PADS_QSPI_GPIO_QSPI_SCLK_PUE_BITS _u(0x00000008) -#define PADS_QSPI_GPIO_QSPI_SCLK_PUE_MSB _u(3) -#define PADS_QSPI_GPIO_QSPI_SCLK_PUE_LSB _u(3) -#define PADS_QSPI_GPIO_QSPI_SCLK_PUE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_QSPI_GPIO_QSPI_SCLK_PDE -// Description : Pull down enable -#define PADS_QSPI_GPIO_QSPI_SCLK_PDE_RESET _u(0x1) -#define PADS_QSPI_GPIO_QSPI_SCLK_PDE_BITS _u(0x00000004) -#define PADS_QSPI_GPIO_QSPI_SCLK_PDE_MSB _u(2) -#define PADS_QSPI_GPIO_QSPI_SCLK_PDE_LSB _u(2) -#define PADS_QSPI_GPIO_QSPI_SCLK_PDE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT -// Description : Enable schmitt trigger -#define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_RESET _u(0x1) -#define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_BITS _u(0x00000002) -#define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_MSB _u(1) -#define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_LSB _u(1) -#define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST -// Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_RESET _u(0x0) -#define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_BITS _u(0x00000001) -#define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_MSB _u(0) -#define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_LSB _u(0) -#define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_ACCESS "RW" -// ============================================================================= -// Register : PADS_QSPI_GPIO_QSPI_SD0 -#define PADS_QSPI_GPIO_QSPI_SD0_OFFSET _u(0x00000008) -#define PADS_QSPI_GPIO_QSPI_SD0_BITS _u(0x000001ff) -#define PADS_QSPI_GPIO_QSPI_SD0_RESET _u(0x00000156) -// ----------------------------------------------------------------------------- -// Field : PADS_QSPI_GPIO_QSPI_SD0_ISO -// Description : Pad isolation control. Remove this once the pad is configured -// by software. -#define PADS_QSPI_GPIO_QSPI_SD0_ISO_RESET _u(0x1) -#define PADS_QSPI_GPIO_QSPI_SD0_ISO_BITS _u(0x00000100) -#define PADS_QSPI_GPIO_QSPI_SD0_ISO_MSB _u(8) -#define PADS_QSPI_GPIO_QSPI_SD0_ISO_LSB _u(8) -#define PADS_QSPI_GPIO_QSPI_SD0_ISO_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_QSPI_GPIO_QSPI_SD0_OD -// Description : Output disable. Has priority over output enable from -// peripherals -#define PADS_QSPI_GPIO_QSPI_SD0_OD_RESET _u(0x0) -#define PADS_QSPI_GPIO_QSPI_SD0_OD_BITS _u(0x00000080) -#define PADS_QSPI_GPIO_QSPI_SD0_OD_MSB _u(7) -#define PADS_QSPI_GPIO_QSPI_SD0_OD_LSB _u(7) -#define PADS_QSPI_GPIO_QSPI_SD0_OD_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_QSPI_GPIO_QSPI_SD0_IE -// Description : Input enable -#define PADS_QSPI_GPIO_QSPI_SD0_IE_RESET _u(0x1) -#define PADS_QSPI_GPIO_QSPI_SD0_IE_BITS _u(0x00000040) -#define PADS_QSPI_GPIO_QSPI_SD0_IE_MSB _u(6) -#define PADS_QSPI_GPIO_QSPI_SD0_IE_LSB _u(6) -#define PADS_QSPI_GPIO_QSPI_SD0_IE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_QSPI_GPIO_QSPI_SD0_DRIVE -// Description : Drive strength. -// 0x0 -> 2mA -// 0x1 -> 4mA -// 0x2 -> 8mA -// 0x3 -> 12mA -#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_RESET _u(0x1) -#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_BITS _u(0x00000030) -#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_MSB _u(5) -#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_LSB _u(4) -#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_ACCESS "RW" -#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_VALUE_2MA _u(0x0) -#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_VALUE_4MA _u(0x1) -#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_VALUE_8MA _u(0x2) -#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_VALUE_12MA _u(0x3) -// ----------------------------------------------------------------------------- -// Field : PADS_QSPI_GPIO_QSPI_SD0_PUE -// Description : Pull up enable -#define PADS_QSPI_GPIO_QSPI_SD0_PUE_RESET _u(0x0) -#define PADS_QSPI_GPIO_QSPI_SD0_PUE_BITS _u(0x00000008) -#define PADS_QSPI_GPIO_QSPI_SD0_PUE_MSB _u(3) -#define PADS_QSPI_GPIO_QSPI_SD0_PUE_LSB _u(3) -#define PADS_QSPI_GPIO_QSPI_SD0_PUE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_QSPI_GPIO_QSPI_SD0_PDE -// Description : Pull down enable -#define PADS_QSPI_GPIO_QSPI_SD0_PDE_RESET _u(0x1) -#define PADS_QSPI_GPIO_QSPI_SD0_PDE_BITS _u(0x00000004) -#define PADS_QSPI_GPIO_QSPI_SD0_PDE_MSB _u(2) -#define PADS_QSPI_GPIO_QSPI_SD0_PDE_LSB _u(2) -#define PADS_QSPI_GPIO_QSPI_SD0_PDE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_QSPI_GPIO_QSPI_SD0_SCHMITT -// Description : Enable schmitt trigger -#define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_RESET _u(0x1) -#define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_BITS _u(0x00000002) -#define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_MSB _u(1) -#define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_LSB _u(1) -#define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST -// Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_RESET _u(0x0) -#define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_BITS _u(0x00000001) -#define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_MSB _u(0) -#define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_LSB _u(0) -#define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_ACCESS "RW" -// ============================================================================= -// Register : PADS_QSPI_GPIO_QSPI_SD1 -#define PADS_QSPI_GPIO_QSPI_SD1_OFFSET _u(0x0000000c) -#define PADS_QSPI_GPIO_QSPI_SD1_BITS _u(0x000001ff) -#define PADS_QSPI_GPIO_QSPI_SD1_RESET _u(0x00000156) -// ----------------------------------------------------------------------------- -// Field : PADS_QSPI_GPIO_QSPI_SD1_ISO -// Description : Pad isolation control. Remove this once the pad is configured -// by software. -#define PADS_QSPI_GPIO_QSPI_SD1_ISO_RESET _u(0x1) -#define PADS_QSPI_GPIO_QSPI_SD1_ISO_BITS _u(0x00000100) -#define PADS_QSPI_GPIO_QSPI_SD1_ISO_MSB _u(8) -#define PADS_QSPI_GPIO_QSPI_SD1_ISO_LSB _u(8) -#define PADS_QSPI_GPIO_QSPI_SD1_ISO_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_QSPI_GPIO_QSPI_SD1_OD -// Description : Output disable. Has priority over output enable from -// peripherals -#define PADS_QSPI_GPIO_QSPI_SD1_OD_RESET _u(0x0) -#define PADS_QSPI_GPIO_QSPI_SD1_OD_BITS _u(0x00000080) -#define PADS_QSPI_GPIO_QSPI_SD1_OD_MSB _u(7) -#define PADS_QSPI_GPIO_QSPI_SD1_OD_LSB _u(7) -#define PADS_QSPI_GPIO_QSPI_SD1_OD_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_QSPI_GPIO_QSPI_SD1_IE -// Description : Input enable -#define PADS_QSPI_GPIO_QSPI_SD1_IE_RESET _u(0x1) -#define PADS_QSPI_GPIO_QSPI_SD1_IE_BITS _u(0x00000040) -#define PADS_QSPI_GPIO_QSPI_SD1_IE_MSB _u(6) -#define PADS_QSPI_GPIO_QSPI_SD1_IE_LSB _u(6) -#define PADS_QSPI_GPIO_QSPI_SD1_IE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_QSPI_GPIO_QSPI_SD1_DRIVE -// Description : Drive strength. -// 0x0 -> 2mA -// 0x1 -> 4mA -// 0x2 -> 8mA -// 0x3 -> 12mA -#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_RESET _u(0x1) -#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_BITS _u(0x00000030) -#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_MSB _u(5) -#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_LSB _u(4) -#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_ACCESS "RW" -#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_VALUE_2MA _u(0x0) -#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_VALUE_4MA _u(0x1) -#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_VALUE_8MA _u(0x2) -#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_VALUE_12MA _u(0x3) -// ----------------------------------------------------------------------------- -// Field : PADS_QSPI_GPIO_QSPI_SD1_PUE -// Description : Pull up enable -#define PADS_QSPI_GPIO_QSPI_SD1_PUE_RESET _u(0x0) -#define PADS_QSPI_GPIO_QSPI_SD1_PUE_BITS _u(0x00000008) -#define PADS_QSPI_GPIO_QSPI_SD1_PUE_MSB _u(3) -#define PADS_QSPI_GPIO_QSPI_SD1_PUE_LSB _u(3) -#define PADS_QSPI_GPIO_QSPI_SD1_PUE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_QSPI_GPIO_QSPI_SD1_PDE -// Description : Pull down enable -#define PADS_QSPI_GPIO_QSPI_SD1_PDE_RESET _u(0x1) -#define PADS_QSPI_GPIO_QSPI_SD1_PDE_BITS _u(0x00000004) -#define PADS_QSPI_GPIO_QSPI_SD1_PDE_MSB _u(2) -#define PADS_QSPI_GPIO_QSPI_SD1_PDE_LSB _u(2) -#define PADS_QSPI_GPIO_QSPI_SD1_PDE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_QSPI_GPIO_QSPI_SD1_SCHMITT -// Description : Enable schmitt trigger -#define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_RESET _u(0x1) -#define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_BITS _u(0x00000002) -#define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_MSB _u(1) -#define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_LSB _u(1) -#define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST -// Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_RESET _u(0x0) -#define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_BITS _u(0x00000001) -#define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_MSB _u(0) -#define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_LSB _u(0) -#define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_ACCESS "RW" -// ============================================================================= -// Register : PADS_QSPI_GPIO_QSPI_SD2 -#define PADS_QSPI_GPIO_QSPI_SD2_OFFSET _u(0x00000010) -#define PADS_QSPI_GPIO_QSPI_SD2_BITS _u(0x000001ff) -#define PADS_QSPI_GPIO_QSPI_SD2_RESET _u(0x0000015a) -// ----------------------------------------------------------------------------- -// Field : PADS_QSPI_GPIO_QSPI_SD2_ISO -// Description : Pad isolation control. Remove this once the pad is configured -// by software. -#define PADS_QSPI_GPIO_QSPI_SD2_ISO_RESET _u(0x1) -#define PADS_QSPI_GPIO_QSPI_SD2_ISO_BITS _u(0x00000100) -#define PADS_QSPI_GPIO_QSPI_SD2_ISO_MSB _u(8) -#define PADS_QSPI_GPIO_QSPI_SD2_ISO_LSB _u(8) -#define PADS_QSPI_GPIO_QSPI_SD2_ISO_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_QSPI_GPIO_QSPI_SD2_OD -// Description : Output disable. Has priority over output enable from -// peripherals -#define PADS_QSPI_GPIO_QSPI_SD2_OD_RESET _u(0x0) -#define PADS_QSPI_GPIO_QSPI_SD2_OD_BITS _u(0x00000080) -#define PADS_QSPI_GPIO_QSPI_SD2_OD_MSB _u(7) -#define PADS_QSPI_GPIO_QSPI_SD2_OD_LSB _u(7) -#define PADS_QSPI_GPIO_QSPI_SD2_OD_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_QSPI_GPIO_QSPI_SD2_IE -// Description : Input enable -#define PADS_QSPI_GPIO_QSPI_SD2_IE_RESET _u(0x1) -#define PADS_QSPI_GPIO_QSPI_SD2_IE_BITS _u(0x00000040) -#define PADS_QSPI_GPIO_QSPI_SD2_IE_MSB _u(6) -#define PADS_QSPI_GPIO_QSPI_SD2_IE_LSB _u(6) -#define PADS_QSPI_GPIO_QSPI_SD2_IE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_QSPI_GPIO_QSPI_SD2_DRIVE -// Description : Drive strength. -// 0x0 -> 2mA -// 0x1 -> 4mA -// 0x2 -> 8mA -// 0x3 -> 12mA -#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_RESET _u(0x1) -#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_BITS _u(0x00000030) -#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_MSB _u(5) -#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_LSB _u(4) -#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_ACCESS "RW" -#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_VALUE_2MA _u(0x0) -#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_VALUE_4MA _u(0x1) -#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_VALUE_8MA _u(0x2) -#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_VALUE_12MA _u(0x3) -// ----------------------------------------------------------------------------- -// Field : PADS_QSPI_GPIO_QSPI_SD2_PUE -// Description : Pull up enable -#define PADS_QSPI_GPIO_QSPI_SD2_PUE_RESET _u(0x1) -#define PADS_QSPI_GPIO_QSPI_SD2_PUE_BITS _u(0x00000008) -#define PADS_QSPI_GPIO_QSPI_SD2_PUE_MSB _u(3) -#define PADS_QSPI_GPIO_QSPI_SD2_PUE_LSB _u(3) -#define PADS_QSPI_GPIO_QSPI_SD2_PUE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_QSPI_GPIO_QSPI_SD2_PDE -// Description : Pull down enable -#define PADS_QSPI_GPIO_QSPI_SD2_PDE_RESET _u(0x0) -#define PADS_QSPI_GPIO_QSPI_SD2_PDE_BITS _u(0x00000004) -#define PADS_QSPI_GPIO_QSPI_SD2_PDE_MSB _u(2) -#define PADS_QSPI_GPIO_QSPI_SD2_PDE_LSB _u(2) -#define PADS_QSPI_GPIO_QSPI_SD2_PDE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_QSPI_GPIO_QSPI_SD2_SCHMITT -// Description : Enable schmitt trigger -#define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_RESET _u(0x1) -#define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_BITS _u(0x00000002) -#define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_MSB _u(1) -#define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_LSB _u(1) -#define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST -// Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_RESET _u(0x0) -#define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_BITS _u(0x00000001) -#define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_MSB _u(0) -#define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_LSB _u(0) -#define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_ACCESS "RW" -// ============================================================================= -// Register : PADS_QSPI_GPIO_QSPI_SD3 -#define PADS_QSPI_GPIO_QSPI_SD3_OFFSET _u(0x00000014) -#define PADS_QSPI_GPIO_QSPI_SD3_BITS _u(0x000001ff) -#define PADS_QSPI_GPIO_QSPI_SD3_RESET _u(0x0000015a) -// ----------------------------------------------------------------------------- -// Field : PADS_QSPI_GPIO_QSPI_SD3_ISO -// Description : Pad isolation control. Remove this once the pad is configured -// by software. -#define PADS_QSPI_GPIO_QSPI_SD3_ISO_RESET _u(0x1) -#define PADS_QSPI_GPIO_QSPI_SD3_ISO_BITS _u(0x00000100) -#define PADS_QSPI_GPIO_QSPI_SD3_ISO_MSB _u(8) -#define PADS_QSPI_GPIO_QSPI_SD3_ISO_LSB _u(8) -#define PADS_QSPI_GPIO_QSPI_SD3_ISO_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_QSPI_GPIO_QSPI_SD3_OD -// Description : Output disable. Has priority over output enable from -// peripherals -#define PADS_QSPI_GPIO_QSPI_SD3_OD_RESET _u(0x0) -#define PADS_QSPI_GPIO_QSPI_SD3_OD_BITS _u(0x00000080) -#define PADS_QSPI_GPIO_QSPI_SD3_OD_MSB _u(7) -#define PADS_QSPI_GPIO_QSPI_SD3_OD_LSB _u(7) -#define PADS_QSPI_GPIO_QSPI_SD3_OD_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_QSPI_GPIO_QSPI_SD3_IE -// Description : Input enable -#define PADS_QSPI_GPIO_QSPI_SD3_IE_RESET _u(0x1) -#define PADS_QSPI_GPIO_QSPI_SD3_IE_BITS _u(0x00000040) -#define PADS_QSPI_GPIO_QSPI_SD3_IE_MSB _u(6) -#define PADS_QSPI_GPIO_QSPI_SD3_IE_LSB _u(6) -#define PADS_QSPI_GPIO_QSPI_SD3_IE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_QSPI_GPIO_QSPI_SD3_DRIVE -// Description : Drive strength. -// 0x0 -> 2mA -// 0x1 -> 4mA -// 0x2 -> 8mA -// 0x3 -> 12mA -#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_RESET _u(0x1) -#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_BITS _u(0x00000030) -#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_MSB _u(5) -#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_LSB _u(4) -#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_ACCESS "RW" -#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_VALUE_2MA _u(0x0) -#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_VALUE_4MA _u(0x1) -#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_VALUE_8MA _u(0x2) -#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_VALUE_12MA _u(0x3) -// ----------------------------------------------------------------------------- -// Field : PADS_QSPI_GPIO_QSPI_SD3_PUE -// Description : Pull up enable -#define PADS_QSPI_GPIO_QSPI_SD3_PUE_RESET _u(0x1) -#define PADS_QSPI_GPIO_QSPI_SD3_PUE_BITS _u(0x00000008) -#define PADS_QSPI_GPIO_QSPI_SD3_PUE_MSB _u(3) -#define PADS_QSPI_GPIO_QSPI_SD3_PUE_LSB _u(3) -#define PADS_QSPI_GPIO_QSPI_SD3_PUE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_QSPI_GPIO_QSPI_SD3_PDE -// Description : Pull down enable -#define PADS_QSPI_GPIO_QSPI_SD3_PDE_RESET _u(0x0) -#define PADS_QSPI_GPIO_QSPI_SD3_PDE_BITS _u(0x00000004) -#define PADS_QSPI_GPIO_QSPI_SD3_PDE_MSB _u(2) -#define PADS_QSPI_GPIO_QSPI_SD3_PDE_LSB _u(2) -#define PADS_QSPI_GPIO_QSPI_SD3_PDE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_QSPI_GPIO_QSPI_SD3_SCHMITT -// Description : Enable schmitt trigger -#define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_RESET _u(0x1) -#define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_BITS _u(0x00000002) -#define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_MSB _u(1) -#define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_LSB _u(1) -#define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST -// Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_RESET _u(0x0) -#define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_BITS _u(0x00000001) -#define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_MSB _u(0) -#define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_LSB _u(0) -#define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_ACCESS "RW" -// ============================================================================= -// Register : PADS_QSPI_GPIO_QSPI_SS -#define PADS_QSPI_GPIO_QSPI_SS_OFFSET _u(0x00000018) -#define PADS_QSPI_GPIO_QSPI_SS_BITS _u(0x000001ff) -#define PADS_QSPI_GPIO_QSPI_SS_RESET _u(0x0000015a) -// ----------------------------------------------------------------------------- -// Field : PADS_QSPI_GPIO_QSPI_SS_ISO -// Description : Pad isolation control. Remove this once the pad is configured -// by software. -#define PADS_QSPI_GPIO_QSPI_SS_ISO_RESET _u(0x1) -#define PADS_QSPI_GPIO_QSPI_SS_ISO_BITS _u(0x00000100) -#define PADS_QSPI_GPIO_QSPI_SS_ISO_MSB _u(8) -#define PADS_QSPI_GPIO_QSPI_SS_ISO_LSB _u(8) -#define PADS_QSPI_GPIO_QSPI_SS_ISO_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_QSPI_GPIO_QSPI_SS_OD -// Description : Output disable. Has priority over output enable from -// peripherals -#define PADS_QSPI_GPIO_QSPI_SS_OD_RESET _u(0x0) -#define PADS_QSPI_GPIO_QSPI_SS_OD_BITS _u(0x00000080) -#define PADS_QSPI_GPIO_QSPI_SS_OD_MSB _u(7) -#define PADS_QSPI_GPIO_QSPI_SS_OD_LSB _u(7) -#define PADS_QSPI_GPIO_QSPI_SS_OD_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_QSPI_GPIO_QSPI_SS_IE -// Description : Input enable -#define PADS_QSPI_GPIO_QSPI_SS_IE_RESET _u(0x1) -#define PADS_QSPI_GPIO_QSPI_SS_IE_BITS _u(0x00000040) -#define PADS_QSPI_GPIO_QSPI_SS_IE_MSB _u(6) -#define PADS_QSPI_GPIO_QSPI_SS_IE_LSB _u(6) -#define PADS_QSPI_GPIO_QSPI_SS_IE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_QSPI_GPIO_QSPI_SS_DRIVE -// Description : Drive strength. -// 0x0 -> 2mA -// 0x1 -> 4mA -// 0x2 -> 8mA -// 0x3 -> 12mA -#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_RESET _u(0x1) -#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_BITS _u(0x00000030) -#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_MSB _u(5) -#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_LSB _u(4) -#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_ACCESS "RW" -#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_VALUE_2MA _u(0x0) -#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_VALUE_4MA _u(0x1) -#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_VALUE_8MA _u(0x2) -#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_VALUE_12MA _u(0x3) -// ----------------------------------------------------------------------------- -// Field : PADS_QSPI_GPIO_QSPI_SS_PUE -// Description : Pull up enable -#define PADS_QSPI_GPIO_QSPI_SS_PUE_RESET _u(0x1) -#define PADS_QSPI_GPIO_QSPI_SS_PUE_BITS _u(0x00000008) -#define PADS_QSPI_GPIO_QSPI_SS_PUE_MSB _u(3) -#define PADS_QSPI_GPIO_QSPI_SS_PUE_LSB _u(3) -#define PADS_QSPI_GPIO_QSPI_SS_PUE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_QSPI_GPIO_QSPI_SS_PDE -// Description : Pull down enable -#define PADS_QSPI_GPIO_QSPI_SS_PDE_RESET _u(0x0) -#define PADS_QSPI_GPIO_QSPI_SS_PDE_BITS _u(0x00000004) -#define PADS_QSPI_GPIO_QSPI_SS_PDE_MSB _u(2) -#define PADS_QSPI_GPIO_QSPI_SS_PDE_LSB _u(2) -#define PADS_QSPI_GPIO_QSPI_SS_PDE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_QSPI_GPIO_QSPI_SS_SCHMITT -// Description : Enable schmitt trigger -#define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_RESET _u(0x1) -#define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_BITS _u(0x00000002) -#define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_MSB _u(1) -#define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_LSB _u(1) -#define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PADS_QSPI_GPIO_QSPI_SS_SLEWFAST -// Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_RESET _u(0x0) -#define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_BITS _u(0x00000001) -#define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_MSB _u(0) -#define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_LSB _u(0) -#define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_ACCESS "RW" -// ============================================================================= -#endif // _HARDWARE_REGS_PADS_QSPI_H - diff --git a/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/pio.h b/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/pio.h deleted file mode 100644 index 4a18b5c6fd..0000000000 --- a/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/pio.h +++ /dev/null @@ -1,3417 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -// ============================================================================= -// Register block : PIO -// Version : 1 -// Bus type : ahbl -// Description : Programmable IO block -// ============================================================================= -#ifndef _HARDWARE_REGS_PIO_H -#define _HARDWARE_REGS_PIO_H -// ============================================================================= -// Register : PIO_CTRL -// Description : PIO control register -#define PIO_CTRL_OFFSET _u(0x00000000) -#define PIO_CTRL_BITS _u(0x07ff0fff) -#define PIO_CTRL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : PIO_CTRL_NEXTPREV_CLKDIV_RESTART -// Description : Write 1 to restart the clock dividers of state machines in -// neighbouring PIO blocks, as specified by NEXT_PIO_MASK and -// PREV_PIO_MASK in the same write. -// -// This is equivalent to writing 1 to the corresponding -// CLKDIV_RESTART bits in those PIOs' CTRL registers. -#define PIO_CTRL_NEXTPREV_CLKDIV_RESTART_RESET _u(0x0) -#define PIO_CTRL_NEXTPREV_CLKDIV_RESTART_BITS _u(0x04000000) -#define PIO_CTRL_NEXTPREV_CLKDIV_RESTART_MSB _u(26) -#define PIO_CTRL_NEXTPREV_CLKDIV_RESTART_LSB _u(26) -#define PIO_CTRL_NEXTPREV_CLKDIV_RESTART_ACCESS "SC" -// ----------------------------------------------------------------------------- -// Field : PIO_CTRL_NEXTPREV_SM_DISABLE -// Description : Write 1 to disable state machines in neighbouring PIO blocks, -// as specified by NEXT_PIO_MASK and PREV_PIO_MASK in the same -// write. -// -// This is equivalent to clearing the corresponding SM_ENABLE bits -// in those PIOs' CTRL registers. -#define PIO_CTRL_NEXTPREV_SM_DISABLE_RESET _u(0x0) -#define PIO_CTRL_NEXTPREV_SM_DISABLE_BITS _u(0x02000000) -#define PIO_CTRL_NEXTPREV_SM_DISABLE_MSB _u(25) -#define PIO_CTRL_NEXTPREV_SM_DISABLE_LSB _u(25) -#define PIO_CTRL_NEXTPREV_SM_DISABLE_ACCESS "SC" -// ----------------------------------------------------------------------------- -// Field : PIO_CTRL_NEXTPREV_SM_ENABLE -// Description : Write 1 to enable state machines in neighbouring PIO blocks, as -// specified by NEXT_PIO_MASK and PREV_PIO_MASK in the same write. -// -// This is equivalent to setting the corresponding SM_ENABLE bits -// in those PIOs' CTRL registers. -// -// If both OTHERS_SM_ENABLE and OTHERS_SM_DISABLE are set, the -// disable takes precedence. -#define PIO_CTRL_NEXTPREV_SM_ENABLE_RESET _u(0x0) -#define PIO_CTRL_NEXTPREV_SM_ENABLE_BITS _u(0x01000000) -#define PIO_CTRL_NEXTPREV_SM_ENABLE_MSB _u(24) -#define PIO_CTRL_NEXTPREV_SM_ENABLE_LSB _u(24) -#define PIO_CTRL_NEXTPREV_SM_ENABLE_ACCESS "SC" -// ----------------------------------------------------------------------------- -// Field : PIO_CTRL_NEXT_PIO_MASK -// Description : A mask of state machines in the neighbouring higher-numbered -// PIO block in the system (or PIO block 0 if this is the highest- -// numbered PIO block) to which to apply the operations specified -// by NEXTPREV_CLKDIV_RESTART, NEXTPREV_SM_ENABLE, and -// NEXTPREV_SM_DISABLE in the same write. -// -// This allows state machines in a neighbouring PIO block to be -// started/stopped/clock-synced exactly simultaneously with a -// write to this PIO block's CTRL register. -// -// Note that in a system with two PIOs, NEXT_PIO_MASK and -// PREV_PIO_MASK actually indicate the same PIO block. In this -// case the effects are applied cumulatively (as though the masks -// were OR'd together). -// -// Neighbouring PIO blocks are disconnected (status signals tied -// to 0 and control signals ignored) if one block is accessible to -// NonSecure code, and one is not. -#define PIO_CTRL_NEXT_PIO_MASK_RESET _u(0x0) -#define PIO_CTRL_NEXT_PIO_MASK_BITS _u(0x00f00000) -#define PIO_CTRL_NEXT_PIO_MASK_MSB _u(23) -#define PIO_CTRL_NEXT_PIO_MASK_LSB _u(20) -#define PIO_CTRL_NEXT_PIO_MASK_ACCESS "SC" -// ----------------------------------------------------------------------------- -// Field : PIO_CTRL_PREV_PIO_MASK -// Description : A mask of state machines in the neighbouring lower-numbered PIO -// block in the system (or the highest-numbered PIO block if this -// is PIO block 0) to which to apply the operations specified by -// OP_CLKDIV_RESTART, OP_ENABLE, OP_DISABLE in the same write. -// -// This allows state machines in a neighbouring PIO block to be -// started/stopped/clock-synced exactly simultaneously with a -// write to this PIO block's CTRL register. -// -// Neighbouring PIO blocks are disconnected (status signals tied -// to 0 and control signals ignored) if one block is accessible to -// NonSecure code, and one is not. -#define PIO_CTRL_PREV_PIO_MASK_RESET _u(0x0) -#define PIO_CTRL_PREV_PIO_MASK_BITS _u(0x000f0000) -#define PIO_CTRL_PREV_PIO_MASK_MSB _u(19) -#define PIO_CTRL_PREV_PIO_MASK_LSB _u(16) -#define PIO_CTRL_PREV_PIO_MASK_ACCESS "SC" -// ----------------------------------------------------------------------------- -// Field : PIO_CTRL_CLKDIV_RESTART -// Description : Restart a state machine's clock divider from an initial phase -// of 0. Clock dividers are free-running, so once started, their -// output (including fractional jitter) is completely determined -// by the integer/fractional divisor configured in SMx_CLKDIV. -// This means that, if multiple clock dividers with the same -// divisor are restarted simultaneously, by writing multiple 1 -// bits to this field, the execution clocks of those state -// machines will run in precise lockstep. -// -// Note that setting/clearing SM_ENABLE does not stop the clock -// divider from running, so once multiple state machines' clocks -// are synchronised, it is safe to disable/reenable a state -// machine, whilst keeping the clock dividers in sync. -// -// Note also that CLKDIV_RESTART can be written to whilst the -// state machine is running, and this is useful to resynchronise -// clock dividers after the divisors (SMx_CLKDIV) have been -// changed on-the-fly. -#define PIO_CTRL_CLKDIV_RESTART_RESET _u(0x0) -#define PIO_CTRL_CLKDIV_RESTART_BITS _u(0x00000f00) -#define PIO_CTRL_CLKDIV_RESTART_MSB _u(11) -#define PIO_CTRL_CLKDIV_RESTART_LSB _u(8) -#define PIO_CTRL_CLKDIV_RESTART_ACCESS "SC" -// ----------------------------------------------------------------------------- -// Field : PIO_CTRL_SM_RESTART -// Description : Write 1 to instantly clear internal SM state which may be -// otherwise difficult to access and will affect future execution. -// -// Specifically, the following are cleared: input and output shift -// counters; the contents of the input shift register; the delay -// counter; the waiting-on-IRQ state; any stalled instruction -// written to SMx_INSTR or run by OUT/MOV EXEC; any pin write left -// asserted due to OUT_STICKY. -// -// The contents of the output shift register and the X/Y scratch -// registers are not affected. -#define PIO_CTRL_SM_RESTART_RESET _u(0x0) -#define PIO_CTRL_SM_RESTART_BITS _u(0x000000f0) -#define PIO_CTRL_SM_RESTART_MSB _u(7) -#define PIO_CTRL_SM_RESTART_LSB _u(4) -#define PIO_CTRL_SM_RESTART_ACCESS "SC" -// ----------------------------------------------------------------------------- -// Field : PIO_CTRL_SM_ENABLE -// Description : Enable/disable each of the four state machines by writing 1/0 -// to each of these four bits. When disabled, a state machine will -// cease executing instructions, except those written directly to -// SMx_INSTR by the system. Multiple bits can be set/cleared at -// once to run/halt multiple state machines simultaneously. -#define PIO_CTRL_SM_ENABLE_RESET _u(0x0) -#define PIO_CTRL_SM_ENABLE_BITS _u(0x0000000f) -#define PIO_CTRL_SM_ENABLE_MSB _u(3) -#define PIO_CTRL_SM_ENABLE_LSB _u(0) -#define PIO_CTRL_SM_ENABLE_ACCESS "RW" -// ============================================================================= -// Register : PIO_FSTAT -// Description : FIFO status register -#define PIO_FSTAT_OFFSET _u(0x00000004) -#define PIO_FSTAT_BITS _u(0x0f0f0f0f) -#define PIO_FSTAT_RESET _u(0x0f000f00) -// ----------------------------------------------------------------------------- -// Field : PIO_FSTAT_TXEMPTY -// Description : State machine TX FIFO is empty -#define PIO_FSTAT_TXEMPTY_RESET _u(0xf) -#define PIO_FSTAT_TXEMPTY_BITS _u(0x0f000000) -#define PIO_FSTAT_TXEMPTY_MSB _u(27) -#define PIO_FSTAT_TXEMPTY_LSB _u(24) -#define PIO_FSTAT_TXEMPTY_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PIO_FSTAT_TXFULL -// Description : State machine TX FIFO is full -#define PIO_FSTAT_TXFULL_RESET _u(0x0) -#define PIO_FSTAT_TXFULL_BITS _u(0x000f0000) -#define PIO_FSTAT_TXFULL_MSB _u(19) -#define PIO_FSTAT_TXFULL_LSB _u(16) -#define PIO_FSTAT_TXFULL_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PIO_FSTAT_RXEMPTY -// Description : State machine RX FIFO is empty -#define PIO_FSTAT_RXEMPTY_RESET _u(0xf) -#define PIO_FSTAT_RXEMPTY_BITS _u(0x00000f00) -#define PIO_FSTAT_RXEMPTY_MSB _u(11) -#define PIO_FSTAT_RXEMPTY_LSB _u(8) -#define PIO_FSTAT_RXEMPTY_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PIO_FSTAT_RXFULL -// Description : State machine RX FIFO is full -#define PIO_FSTAT_RXFULL_RESET _u(0x0) -#define PIO_FSTAT_RXFULL_BITS _u(0x0000000f) -#define PIO_FSTAT_RXFULL_MSB _u(3) -#define PIO_FSTAT_RXFULL_LSB _u(0) -#define PIO_FSTAT_RXFULL_ACCESS "RO" -// ============================================================================= -// Register : PIO_FDEBUG -// Description : FIFO debug register -#define PIO_FDEBUG_OFFSET _u(0x00000008) -#define PIO_FDEBUG_BITS _u(0x0f0f0f0f) -#define PIO_FDEBUG_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : PIO_FDEBUG_TXSTALL -// Description : State machine has stalled on empty TX FIFO during a blocking -// PULL, or an OUT with autopull enabled. Write 1 to clear. -#define PIO_FDEBUG_TXSTALL_RESET _u(0x0) -#define PIO_FDEBUG_TXSTALL_BITS _u(0x0f000000) -#define PIO_FDEBUG_TXSTALL_MSB _u(27) -#define PIO_FDEBUG_TXSTALL_LSB _u(24) -#define PIO_FDEBUG_TXSTALL_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : PIO_FDEBUG_TXOVER -// Description : TX FIFO overflow (i.e. write-on-full by the system) has -// occurred. Write 1 to clear. Note that write-on-full does not -// alter the state or contents of the FIFO in any way, but the -// data that the system attempted to write is dropped, so if this -// flag is set, your software has quite likely dropped some data -// on the floor. -#define PIO_FDEBUG_TXOVER_RESET _u(0x0) -#define PIO_FDEBUG_TXOVER_BITS _u(0x000f0000) -#define PIO_FDEBUG_TXOVER_MSB _u(19) -#define PIO_FDEBUG_TXOVER_LSB _u(16) -#define PIO_FDEBUG_TXOVER_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : PIO_FDEBUG_RXUNDER -// Description : RX FIFO underflow (i.e. read-on-empty by the system) has -// occurred. Write 1 to clear. Note that read-on-empty does not -// perturb the state of the FIFO in any way, but the data returned -// by reading from an empty FIFO is undefined, so this flag -// generally only becomes set due to some kind of software error. -#define PIO_FDEBUG_RXUNDER_RESET _u(0x0) -#define PIO_FDEBUG_RXUNDER_BITS _u(0x00000f00) -#define PIO_FDEBUG_RXUNDER_MSB _u(11) -#define PIO_FDEBUG_RXUNDER_LSB _u(8) -#define PIO_FDEBUG_RXUNDER_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : PIO_FDEBUG_RXSTALL -// Description : State machine has stalled on full RX FIFO during a blocking -// PUSH, or an IN with autopush enabled. This flag is also set -// when a nonblocking PUSH to a full FIFO took place, in which -// case the state machine has dropped data. Write 1 to clear. -#define PIO_FDEBUG_RXSTALL_RESET _u(0x0) -#define PIO_FDEBUG_RXSTALL_BITS _u(0x0000000f) -#define PIO_FDEBUG_RXSTALL_MSB _u(3) -#define PIO_FDEBUG_RXSTALL_LSB _u(0) -#define PIO_FDEBUG_RXSTALL_ACCESS "WC" -// ============================================================================= -// Register : PIO_FLEVEL -// Description : FIFO levels -#define PIO_FLEVEL_OFFSET _u(0x0000000c) -#define PIO_FLEVEL_BITS _u(0xffffffff) -#define PIO_FLEVEL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : PIO_FLEVEL_RX3 -#define PIO_FLEVEL_RX3_RESET _u(0x0) -#define PIO_FLEVEL_RX3_BITS _u(0xf0000000) -#define PIO_FLEVEL_RX3_MSB _u(31) -#define PIO_FLEVEL_RX3_LSB _u(28) -#define PIO_FLEVEL_RX3_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PIO_FLEVEL_TX3 -#define PIO_FLEVEL_TX3_RESET _u(0x0) -#define PIO_FLEVEL_TX3_BITS _u(0x0f000000) -#define PIO_FLEVEL_TX3_MSB _u(27) -#define PIO_FLEVEL_TX3_LSB _u(24) -#define PIO_FLEVEL_TX3_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PIO_FLEVEL_RX2 -#define PIO_FLEVEL_RX2_RESET _u(0x0) -#define PIO_FLEVEL_RX2_BITS _u(0x00f00000) -#define PIO_FLEVEL_RX2_MSB _u(23) -#define PIO_FLEVEL_RX2_LSB _u(20) -#define PIO_FLEVEL_RX2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PIO_FLEVEL_TX2 -#define PIO_FLEVEL_TX2_RESET _u(0x0) -#define PIO_FLEVEL_TX2_BITS _u(0x000f0000) -#define PIO_FLEVEL_TX2_MSB _u(19) -#define PIO_FLEVEL_TX2_LSB _u(16) -#define PIO_FLEVEL_TX2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PIO_FLEVEL_RX1 -#define PIO_FLEVEL_RX1_RESET _u(0x0) -#define PIO_FLEVEL_RX1_BITS _u(0x0000f000) -#define PIO_FLEVEL_RX1_MSB _u(15) -#define PIO_FLEVEL_RX1_LSB _u(12) -#define PIO_FLEVEL_RX1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PIO_FLEVEL_TX1 -#define PIO_FLEVEL_TX1_RESET _u(0x0) -#define PIO_FLEVEL_TX1_BITS _u(0x00000f00) -#define PIO_FLEVEL_TX1_MSB _u(11) -#define PIO_FLEVEL_TX1_LSB _u(8) -#define PIO_FLEVEL_TX1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PIO_FLEVEL_RX0 -#define PIO_FLEVEL_RX0_RESET _u(0x0) -#define PIO_FLEVEL_RX0_BITS _u(0x000000f0) -#define PIO_FLEVEL_RX0_MSB _u(7) -#define PIO_FLEVEL_RX0_LSB _u(4) -#define PIO_FLEVEL_RX0_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PIO_FLEVEL_TX0 -#define PIO_FLEVEL_TX0_RESET _u(0x0) -#define PIO_FLEVEL_TX0_BITS _u(0x0000000f) -#define PIO_FLEVEL_TX0_MSB _u(3) -#define PIO_FLEVEL_TX0_LSB _u(0) -#define PIO_FLEVEL_TX0_ACCESS "RO" -// ============================================================================= -// Register : PIO_TXF0 -// Description : Direct write access to the TX FIFO for this state machine. Each -// write pushes one word to the FIFO. Attempting to write to a -// full FIFO has no effect on the FIFO state or contents, and sets -// the sticky FDEBUG_TXOVER error flag for this FIFO. -#define PIO_TXF0_OFFSET _u(0x00000010) -#define PIO_TXF0_BITS _u(0xffffffff) -#define PIO_TXF0_RESET _u(0x00000000) -#define PIO_TXF0_MSB _u(31) -#define PIO_TXF0_LSB _u(0) -#define PIO_TXF0_ACCESS "WF" -// ============================================================================= -// Register : PIO_TXF1 -// Description : Direct write access to the TX FIFO for this state machine. Each -// write pushes one word to the FIFO. Attempting to write to a -// full FIFO has no effect on the FIFO state or contents, and sets -// the sticky FDEBUG_TXOVER error flag for this FIFO. -#define PIO_TXF1_OFFSET _u(0x00000014) -#define PIO_TXF1_BITS _u(0xffffffff) -#define PIO_TXF1_RESET _u(0x00000000) -#define PIO_TXF1_MSB _u(31) -#define PIO_TXF1_LSB _u(0) -#define PIO_TXF1_ACCESS "WF" -// ============================================================================= -// Register : PIO_TXF2 -// Description : Direct write access to the TX FIFO for this state machine. Each -// write pushes one word to the FIFO. Attempting to write to a -// full FIFO has no effect on the FIFO state or contents, and sets -// the sticky FDEBUG_TXOVER error flag for this FIFO. -#define PIO_TXF2_OFFSET _u(0x00000018) -#define PIO_TXF2_BITS _u(0xffffffff) -#define PIO_TXF2_RESET _u(0x00000000) -#define PIO_TXF2_MSB _u(31) -#define PIO_TXF2_LSB _u(0) -#define PIO_TXF2_ACCESS "WF" -// ============================================================================= -// Register : PIO_TXF3 -// Description : Direct write access to the TX FIFO for this state machine. Each -// write pushes one word to the FIFO. Attempting to write to a -// full FIFO has no effect on the FIFO state or contents, and sets -// the sticky FDEBUG_TXOVER error flag for this FIFO. -#define PIO_TXF3_OFFSET _u(0x0000001c) -#define PIO_TXF3_BITS _u(0xffffffff) -#define PIO_TXF3_RESET _u(0x00000000) -#define PIO_TXF3_MSB _u(31) -#define PIO_TXF3_LSB _u(0) -#define PIO_TXF3_ACCESS "WF" -// ============================================================================= -// Register : PIO_RXF0 -// Description : Direct read access to the RX FIFO for this state machine. Each -// read pops one word from the FIFO. Attempting to read from an -// empty FIFO has no effect on the FIFO state, and sets the sticky -// FDEBUG_RXUNDER error flag for this FIFO. The data returned to -// the system on a read from an empty FIFO is undefined. -#define PIO_RXF0_OFFSET _u(0x00000020) -#define PIO_RXF0_BITS _u(0xffffffff) -#define PIO_RXF0_RESET "-" -#define PIO_RXF0_MSB _u(31) -#define PIO_RXF0_LSB _u(0) -#define PIO_RXF0_ACCESS "RF" -// ============================================================================= -// Register : PIO_RXF1 -// Description : Direct read access to the RX FIFO for this state machine. Each -// read pops one word from the FIFO. Attempting to read from an -// empty FIFO has no effect on the FIFO state, and sets the sticky -// FDEBUG_RXUNDER error flag for this FIFO. The data returned to -// the system on a read from an empty FIFO is undefined. -#define PIO_RXF1_OFFSET _u(0x00000024) -#define PIO_RXF1_BITS _u(0xffffffff) -#define PIO_RXF1_RESET "-" -#define PIO_RXF1_MSB _u(31) -#define PIO_RXF1_LSB _u(0) -#define PIO_RXF1_ACCESS "RF" -// ============================================================================= -// Register : PIO_RXF2 -// Description : Direct read access to the RX FIFO for this state machine. Each -// read pops one word from the FIFO. Attempting to read from an -// empty FIFO has no effect on the FIFO state, and sets the sticky -// FDEBUG_RXUNDER error flag for this FIFO. The data returned to -// the system on a read from an empty FIFO is undefined. -#define PIO_RXF2_OFFSET _u(0x00000028) -#define PIO_RXF2_BITS _u(0xffffffff) -#define PIO_RXF2_RESET "-" -#define PIO_RXF2_MSB _u(31) -#define PIO_RXF2_LSB _u(0) -#define PIO_RXF2_ACCESS "RF" -// ============================================================================= -// Register : PIO_RXF3 -// Description : Direct read access to the RX FIFO for this state machine. Each -// read pops one word from the FIFO. Attempting to read from an -// empty FIFO has no effect on the FIFO state, and sets the sticky -// FDEBUG_RXUNDER error flag for this FIFO. The data returned to -// the system on a read from an empty FIFO is undefined. -#define PIO_RXF3_OFFSET _u(0x0000002c) -#define PIO_RXF3_BITS _u(0xffffffff) -#define PIO_RXF3_RESET "-" -#define PIO_RXF3_MSB _u(31) -#define PIO_RXF3_LSB _u(0) -#define PIO_RXF3_ACCESS "RF" -// ============================================================================= -// Register : PIO_IRQ -// Description : State machine IRQ flags register. Write 1 to clear. There are -// eight state machine IRQ flags, which can be set, cleared, and -// waited on by the state machines. There's no fixed association -// between flags and state machines -- any state machine can use -// any flag. -// -// Any of the eight flags can be used for timing synchronisation -// between state machines, using IRQ and WAIT instructions. Any -// combination of the eight flags can also routed out to either of -// the two system-level interrupt requests, alongside FIFO status -// interrupts -- see e.g. IRQ0_INTE. -#define PIO_IRQ_OFFSET _u(0x00000030) -#define PIO_IRQ_BITS _u(0x000000ff) -#define PIO_IRQ_RESET _u(0x00000000) -#define PIO_IRQ_MSB _u(7) -#define PIO_IRQ_LSB _u(0) -#define PIO_IRQ_ACCESS "WC" -// ============================================================================= -// Register : PIO_IRQ_FORCE -// Description : Writing a 1 to each of these bits will forcibly assert the -// corresponding IRQ. Note this is different to the INTF register: -// writing here affects PIO internal state. INTF just asserts the -// processor-facing IRQ signal for testing ISRs, and is not -// visible to the state machines. -#define PIO_IRQ_FORCE_OFFSET _u(0x00000034) -#define PIO_IRQ_FORCE_BITS _u(0x000000ff) -#define PIO_IRQ_FORCE_RESET _u(0x00000000) -#define PIO_IRQ_FORCE_MSB _u(7) -#define PIO_IRQ_FORCE_LSB _u(0) -#define PIO_IRQ_FORCE_ACCESS "WF" -// ============================================================================= -// Register : PIO_INPUT_SYNC_BYPASS -// Description : There is a 2-flipflop synchronizer on each GPIO input, which -// protects PIO logic from metastabilities. This increases input -// delay, and for fast synchronous IO (e.g. SPI) these -// synchronizers may need to be bypassed. Each bit in this -// register corresponds to one GPIO. -// 0 -> input is synchronized (default) -// 1 -> synchronizer is bypassed -// If in doubt, leave this register as all zeroes. -#define PIO_INPUT_SYNC_BYPASS_OFFSET _u(0x00000038) -#define PIO_INPUT_SYNC_BYPASS_BITS _u(0xffffffff) -#define PIO_INPUT_SYNC_BYPASS_RESET _u(0x00000000) -#define PIO_INPUT_SYNC_BYPASS_MSB _u(31) -#define PIO_INPUT_SYNC_BYPASS_LSB _u(0) -#define PIO_INPUT_SYNC_BYPASS_ACCESS "RW" -// ============================================================================= -// Register : PIO_DBG_PADOUT -// Description : Read to sample the pad output values PIO is currently driving -// to the GPIOs. On RP2040 there are 30 GPIOs, so the two most -// significant bits are hardwired to 0. -#define PIO_DBG_PADOUT_OFFSET _u(0x0000003c) -#define PIO_DBG_PADOUT_BITS _u(0xffffffff) -#define PIO_DBG_PADOUT_RESET _u(0x00000000) -#define PIO_DBG_PADOUT_MSB _u(31) -#define PIO_DBG_PADOUT_LSB _u(0) -#define PIO_DBG_PADOUT_ACCESS "RO" -// ============================================================================= -// Register : PIO_DBG_PADOE -// Description : Read to sample the pad output enables (direction) PIO is -// currently driving to the GPIOs. On RP2040 there are 30 GPIOs, -// so the two most significant bits are hardwired to 0. -#define PIO_DBG_PADOE_OFFSET _u(0x00000040) -#define PIO_DBG_PADOE_BITS _u(0xffffffff) -#define PIO_DBG_PADOE_RESET _u(0x00000000) -#define PIO_DBG_PADOE_MSB _u(31) -#define PIO_DBG_PADOE_LSB _u(0) -#define PIO_DBG_PADOE_ACCESS "RO" -// ============================================================================= -// Register : PIO_DBG_CFGINFO -// Description : The PIO hardware has some free parameters that may vary between -// chip products. -// These should be provided in the chip datasheet, but are also -// exposed here. -#define PIO_DBG_CFGINFO_OFFSET _u(0x00000044) -#define PIO_DBG_CFGINFO_BITS _u(0xf03f0f3f) -#define PIO_DBG_CFGINFO_RESET _u(0x10000000) -// ----------------------------------------------------------------------------- -// Field : PIO_DBG_CFGINFO_VERSION -// Description : Version of the core PIO hardware. -// 0x0 -> Version 0 (RP2040) -// 0x1 -> Version 1 (RP2350) -#define PIO_DBG_CFGINFO_VERSION_RESET _u(0x1) -#define PIO_DBG_CFGINFO_VERSION_BITS _u(0xf0000000) -#define PIO_DBG_CFGINFO_VERSION_MSB _u(31) -#define PIO_DBG_CFGINFO_VERSION_LSB _u(28) -#define PIO_DBG_CFGINFO_VERSION_ACCESS "RO" -#define PIO_DBG_CFGINFO_VERSION_VALUE_V0 _u(0x0) -#define PIO_DBG_CFGINFO_VERSION_VALUE_V1 _u(0x1) -// ----------------------------------------------------------------------------- -// Field : PIO_DBG_CFGINFO_IMEM_SIZE -// Description : The size of the instruction memory, measured in units of one -// instruction -#define PIO_DBG_CFGINFO_IMEM_SIZE_RESET "-" -#define PIO_DBG_CFGINFO_IMEM_SIZE_BITS _u(0x003f0000) -#define PIO_DBG_CFGINFO_IMEM_SIZE_MSB _u(21) -#define PIO_DBG_CFGINFO_IMEM_SIZE_LSB _u(16) -#define PIO_DBG_CFGINFO_IMEM_SIZE_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PIO_DBG_CFGINFO_SM_COUNT -// Description : The number of state machines this PIO instance is equipped -// with. -#define PIO_DBG_CFGINFO_SM_COUNT_RESET "-" -#define PIO_DBG_CFGINFO_SM_COUNT_BITS _u(0x00000f00) -#define PIO_DBG_CFGINFO_SM_COUNT_MSB _u(11) -#define PIO_DBG_CFGINFO_SM_COUNT_LSB _u(8) -#define PIO_DBG_CFGINFO_SM_COUNT_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PIO_DBG_CFGINFO_FIFO_DEPTH -// Description : The depth of the state machine TX/RX FIFOs, measured in words. -// Joining fifos via SHIFTCTRL_FJOIN gives one FIFO with double -// this depth. -#define PIO_DBG_CFGINFO_FIFO_DEPTH_RESET "-" -#define PIO_DBG_CFGINFO_FIFO_DEPTH_BITS _u(0x0000003f) -#define PIO_DBG_CFGINFO_FIFO_DEPTH_MSB _u(5) -#define PIO_DBG_CFGINFO_FIFO_DEPTH_LSB _u(0) -#define PIO_DBG_CFGINFO_FIFO_DEPTH_ACCESS "RO" -// ============================================================================= -// Register : PIO_INSTR_MEM0 -// Description : Write-only access to instruction memory location 0 -#define PIO_INSTR_MEM0_OFFSET _u(0x00000048) -#define PIO_INSTR_MEM0_BITS _u(0x0000ffff) -#define PIO_INSTR_MEM0_RESET _u(0x00000000) -#define PIO_INSTR_MEM0_MSB _u(15) -#define PIO_INSTR_MEM0_LSB _u(0) -#define PIO_INSTR_MEM0_ACCESS "WO" -// ============================================================================= -// Register : PIO_INSTR_MEM1 -// Description : Write-only access to instruction memory location 1 -#define PIO_INSTR_MEM1_OFFSET _u(0x0000004c) -#define PIO_INSTR_MEM1_BITS _u(0x0000ffff) -#define PIO_INSTR_MEM1_RESET _u(0x00000000) -#define PIO_INSTR_MEM1_MSB _u(15) -#define PIO_INSTR_MEM1_LSB _u(0) -#define PIO_INSTR_MEM1_ACCESS "WO" -// ============================================================================= -// Register : PIO_INSTR_MEM2 -// Description : Write-only access to instruction memory location 2 -#define PIO_INSTR_MEM2_OFFSET _u(0x00000050) -#define PIO_INSTR_MEM2_BITS _u(0x0000ffff) -#define PIO_INSTR_MEM2_RESET _u(0x00000000) -#define PIO_INSTR_MEM2_MSB _u(15) -#define PIO_INSTR_MEM2_LSB _u(0) -#define PIO_INSTR_MEM2_ACCESS "WO" -// ============================================================================= -// Register : PIO_INSTR_MEM3 -// Description : Write-only access to instruction memory location 3 -#define PIO_INSTR_MEM3_OFFSET _u(0x00000054) -#define PIO_INSTR_MEM3_BITS _u(0x0000ffff) -#define PIO_INSTR_MEM3_RESET _u(0x00000000) -#define PIO_INSTR_MEM3_MSB _u(15) -#define PIO_INSTR_MEM3_LSB _u(0) -#define PIO_INSTR_MEM3_ACCESS "WO" -// ============================================================================= -// Register : PIO_INSTR_MEM4 -// Description : Write-only access to instruction memory location 4 -#define PIO_INSTR_MEM4_OFFSET _u(0x00000058) -#define PIO_INSTR_MEM4_BITS _u(0x0000ffff) -#define PIO_INSTR_MEM4_RESET _u(0x00000000) -#define PIO_INSTR_MEM4_MSB _u(15) -#define PIO_INSTR_MEM4_LSB _u(0) -#define PIO_INSTR_MEM4_ACCESS "WO" -// ============================================================================= -// Register : PIO_INSTR_MEM5 -// Description : Write-only access to instruction memory location 5 -#define PIO_INSTR_MEM5_OFFSET _u(0x0000005c) -#define PIO_INSTR_MEM5_BITS _u(0x0000ffff) -#define PIO_INSTR_MEM5_RESET _u(0x00000000) -#define PIO_INSTR_MEM5_MSB _u(15) -#define PIO_INSTR_MEM5_LSB _u(0) -#define PIO_INSTR_MEM5_ACCESS "WO" -// ============================================================================= -// Register : PIO_INSTR_MEM6 -// Description : Write-only access to instruction memory location 6 -#define PIO_INSTR_MEM6_OFFSET _u(0x00000060) -#define PIO_INSTR_MEM6_BITS _u(0x0000ffff) -#define PIO_INSTR_MEM6_RESET _u(0x00000000) -#define PIO_INSTR_MEM6_MSB _u(15) -#define PIO_INSTR_MEM6_LSB _u(0) -#define PIO_INSTR_MEM6_ACCESS "WO" -// ============================================================================= -// Register : PIO_INSTR_MEM7 -// Description : Write-only access to instruction memory location 7 -#define PIO_INSTR_MEM7_OFFSET _u(0x00000064) -#define PIO_INSTR_MEM7_BITS _u(0x0000ffff) -#define PIO_INSTR_MEM7_RESET _u(0x00000000) -#define PIO_INSTR_MEM7_MSB _u(15) -#define PIO_INSTR_MEM7_LSB _u(0) -#define PIO_INSTR_MEM7_ACCESS "WO" -// ============================================================================= -// Register : PIO_INSTR_MEM8 -// Description : Write-only access to instruction memory location 8 -#define PIO_INSTR_MEM8_OFFSET _u(0x00000068) -#define PIO_INSTR_MEM8_BITS _u(0x0000ffff) -#define PIO_INSTR_MEM8_RESET _u(0x00000000) -#define PIO_INSTR_MEM8_MSB _u(15) -#define PIO_INSTR_MEM8_LSB _u(0) -#define PIO_INSTR_MEM8_ACCESS "WO" -// ============================================================================= -// Register : PIO_INSTR_MEM9 -// Description : Write-only access to instruction memory location 9 -#define PIO_INSTR_MEM9_OFFSET _u(0x0000006c) -#define PIO_INSTR_MEM9_BITS _u(0x0000ffff) -#define PIO_INSTR_MEM9_RESET _u(0x00000000) -#define PIO_INSTR_MEM9_MSB _u(15) -#define PIO_INSTR_MEM9_LSB _u(0) -#define PIO_INSTR_MEM9_ACCESS "WO" -// ============================================================================= -// Register : PIO_INSTR_MEM10 -// Description : Write-only access to instruction memory location 10 -#define PIO_INSTR_MEM10_OFFSET _u(0x00000070) -#define PIO_INSTR_MEM10_BITS _u(0x0000ffff) -#define PIO_INSTR_MEM10_RESET _u(0x00000000) -#define PIO_INSTR_MEM10_MSB _u(15) -#define PIO_INSTR_MEM10_LSB _u(0) -#define PIO_INSTR_MEM10_ACCESS "WO" -// ============================================================================= -// Register : PIO_INSTR_MEM11 -// Description : Write-only access to instruction memory location 11 -#define PIO_INSTR_MEM11_OFFSET _u(0x00000074) -#define PIO_INSTR_MEM11_BITS _u(0x0000ffff) -#define PIO_INSTR_MEM11_RESET _u(0x00000000) -#define PIO_INSTR_MEM11_MSB _u(15) -#define PIO_INSTR_MEM11_LSB _u(0) -#define PIO_INSTR_MEM11_ACCESS "WO" -// ============================================================================= -// Register : PIO_INSTR_MEM12 -// Description : Write-only access to instruction memory location 12 -#define PIO_INSTR_MEM12_OFFSET _u(0x00000078) -#define PIO_INSTR_MEM12_BITS _u(0x0000ffff) -#define PIO_INSTR_MEM12_RESET _u(0x00000000) -#define PIO_INSTR_MEM12_MSB _u(15) -#define PIO_INSTR_MEM12_LSB _u(0) -#define PIO_INSTR_MEM12_ACCESS "WO" -// ============================================================================= -// Register : PIO_INSTR_MEM13 -// Description : Write-only access to instruction memory location 13 -#define PIO_INSTR_MEM13_OFFSET _u(0x0000007c) -#define PIO_INSTR_MEM13_BITS _u(0x0000ffff) -#define PIO_INSTR_MEM13_RESET _u(0x00000000) -#define PIO_INSTR_MEM13_MSB _u(15) -#define PIO_INSTR_MEM13_LSB _u(0) -#define PIO_INSTR_MEM13_ACCESS "WO" -// ============================================================================= -// Register : PIO_INSTR_MEM14 -// Description : Write-only access to instruction memory location 14 -#define PIO_INSTR_MEM14_OFFSET _u(0x00000080) -#define PIO_INSTR_MEM14_BITS _u(0x0000ffff) -#define PIO_INSTR_MEM14_RESET _u(0x00000000) -#define PIO_INSTR_MEM14_MSB _u(15) -#define PIO_INSTR_MEM14_LSB _u(0) -#define PIO_INSTR_MEM14_ACCESS "WO" -// ============================================================================= -// Register : PIO_INSTR_MEM15 -// Description : Write-only access to instruction memory location 15 -#define PIO_INSTR_MEM15_OFFSET _u(0x00000084) -#define PIO_INSTR_MEM15_BITS _u(0x0000ffff) -#define PIO_INSTR_MEM15_RESET _u(0x00000000) -#define PIO_INSTR_MEM15_MSB _u(15) -#define PIO_INSTR_MEM15_LSB _u(0) -#define PIO_INSTR_MEM15_ACCESS "WO" -// ============================================================================= -// Register : PIO_INSTR_MEM16 -// Description : Write-only access to instruction memory location 16 -#define PIO_INSTR_MEM16_OFFSET _u(0x00000088) -#define PIO_INSTR_MEM16_BITS _u(0x0000ffff) -#define PIO_INSTR_MEM16_RESET _u(0x00000000) -#define PIO_INSTR_MEM16_MSB _u(15) -#define PIO_INSTR_MEM16_LSB _u(0) -#define PIO_INSTR_MEM16_ACCESS "WO" -// ============================================================================= -// Register : PIO_INSTR_MEM17 -// Description : Write-only access to instruction memory location 17 -#define PIO_INSTR_MEM17_OFFSET _u(0x0000008c) -#define PIO_INSTR_MEM17_BITS _u(0x0000ffff) -#define PIO_INSTR_MEM17_RESET _u(0x00000000) -#define PIO_INSTR_MEM17_MSB _u(15) -#define PIO_INSTR_MEM17_LSB _u(0) -#define PIO_INSTR_MEM17_ACCESS "WO" -// ============================================================================= -// Register : PIO_INSTR_MEM18 -// Description : Write-only access to instruction memory location 18 -#define PIO_INSTR_MEM18_OFFSET _u(0x00000090) -#define PIO_INSTR_MEM18_BITS _u(0x0000ffff) -#define PIO_INSTR_MEM18_RESET _u(0x00000000) -#define PIO_INSTR_MEM18_MSB _u(15) -#define PIO_INSTR_MEM18_LSB _u(0) -#define PIO_INSTR_MEM18_ACCESS "WO" -// ============================================================================= -// Register : PIO_INSTR_MEM19 -// Description : Write-only access to instruction memory location 19 -#define PIO_INSTR_MEM19_OFFSET _u(0x00000094) -#define PIO_INSTR_MEM19_BITS _u(0x0000ffff) -#define PIO_INSTR_MEM19_RESET _u(0x00000000) -#define PIO_INSTR_MEM19_MSB _u(15) -#define PIO_INSTR_MEM19_LSB _u(0) -#define PIO_INSTR_MEM19_ACCESS "WO" -// ============================================================================= -// Register : PIO_INSTR_MEM20 -// Description : Write-only access to instruction memory location 20 -#define PIO_INSTR_MEM20_OFFSET _u(0x00000098) -#define PIO_INSTR_MEM20_BITS _u(0x0000ffff) -#define PIO_INSTR_MEM20_RESET _u(0x00000000) -#define PIO_INSTR_MEM20_MSB _u(15) -#define PIO_INSTR_MEM20_LSB _u(0) -#define PIO_INSTR_MEM20_ACCESS "WO" -// ============================================================================= -// Register : PIO_INSTR_MEM21 -// Description : Write-only access to instruction memory location 21 -#define PIO_INSTR_MEM21_OFFSET _u(0x0000009c) -#define PIO_INSTR_MEM21_BITS _u(0x0000ffff) -#define PIO_INSTR_MEM21_RESET _u(0x00000000) -#define PIO_INSTR_MEM21_MSB _u(15) -#define PIO_INSTR_MEM21_LSB _u(0) -#define PIO_INSTR_MEM21_ACCESS "WO" -// ============================================================================= -// Register : PIO_INSTR_MEM22 -// Description : Write-only access to instruction memory location 22 -#define PIO_INSTR_MEM22_OFFSET _u(0x000000a0) -#define PIO_INSTR_MEM22_BITS _u(0x0000ffff) -#define PIO_INSTR_MEM22_RESET _u(0x00000000) -#define PIO_INSTR_MEM22_MSB _u(15) -#define PIO_INSTR_MEM22_LSB _u(0) -#define PIO_INSTR_MEM22_ACCESS "WO" -// ============================================================================= -// Register : PIO_INSTR_MEM23 -// Description : Write-only access to instruction memory location 23 -#define PIO_INSTR_MEM23_OFFSET _u(0x000000a4) -#define PIO_INSTR_MEM23_BITS _u(0x0000ffff) -#define PIO_INSTR_MEM23_RESET _u(0x00000000) -#define PIO_INSTR_MEM23_MSB _u(15) -#define PIO_INSTR_MEM23_LSB _u(0) -#define PIO_INSTR_MEM23_ACCESS "WO" -// ============================================================================= -// Register : PIO_INSTR_MEM24 -// Description : Write-only access to instruction memory location 24 -#define PIO_INSTR_MEM24_OFFSET _u(0x000000a8) -#define PIO_INSTR_MEM24_BITS _u(0x0000ffff) -#define PIO_INSTR_MEM24_RESET _u(0x00000000) -#define PIO_INSTR_MEM24_MSB _u(15) -#define PIO_INSTR_MEM24_LSB _u(0) -#define PIO_INSTR_MEM24_ACCESS "WO" -// ============================================================================= -// Register : PIO_INSTR_MEM25 -// Description : Write-only access to instruction memory location 25 -#define PIO_INSTR_MEM25_OFFSET _u(0x000000ac) -#define PIO_INSTR_MEM25_BITS _u(0x0000ffff) -#define PIO_INSTR_MEM25_RESET _u(0x00000000) -#define PIO_INSTR_MEM25_MSB _u(15) -#define PIO_INSTR_MEM25_LSB _u(0) -#define PIO_INSTR_MEM25_ACCESS "WO" -// ============================================================================= -// Register : PIO_INSTR_MEM26 -// Description : Write-only access to instruction memory location 26 -#define PIO_INSTR_MEM26_OFFSET _u(0x000000b0) -#define PIO_INSTR_MEM26_BITS _u(0x0000ffff) -#define PIO_INSTR_MEM26_RESET _u(0x00000000) -#define PIO_INSTR_MEM26_MSB _u(15) -#define PIO_INSTR_MEM26_LSB _u(0) -#define PIO_INSTR_MEM26_ACCESS "WO" -// ============================================================================= -// Register : PIO_INSTR_MEM27 -// Description : Write-only access to instruction memory location 27 -#define PIO_INSTR_MEM27_OFFSET _u(0x000000b4) -#define PIO_INSTR_MEM27_BITS _u(0x0000ffff) -#define PIO_INSTR_MEM27_RESET _u(0x00000000) -#define PIO_INSTR_MEM27_MSB _u(15) -#define PIO_INSTR_MEM27_LSB _u(0) -#define PIO_INSTR_MEM27_ACCESS "WO" -// ============================================================================= -// Register : PIO_INSTR_MEM28 -// Description : Write-only access to instruction memory location 28 -#define PIO_INSTR_MEM28_OFFSET _u(0x000000b8) -#define PIO_INSTR_MEM28_BITS _u(0x0000ffff) -#define PIO_INSTR_MEM28_RESET _u(0x00000000) -#define PIO_INSTR_MEM28_MSB _u(15) -#define PIO_INSTR_MEM28_LSB _u(0) -#define PIO_INSTR_MEM28_ACCESS "WO" -// ============================================================================= -// Register : PIO_INSTR_MEM29 -// Description : Write-only access to instruction memory location 29 -#define PIO_INSTR_MEM29_OFFSET _u(0x000000bc) -#define PIO_INSTR_MEM29_BITS _u(0x0000ffff) -#define PIO_INSTR_MEM29_RESET _u(0x00000000) -#define PIO_INSTR_MEM29_MSB _u(15) -#define PIO_INSTR_MEM29_LSB _u(0) -#define PIO_INSTR_MEM29_ACCESS "WO" -// ============================================================================= -// Register : PIO_INSTR_MEM30 -// Description : Write-only access to instruction memory location 30 -#define PIO_INSTR_MEM30_OFFSET _u(0x000000c0) -#define PIO_INSTR_MEM30_BITS _u(0x0000ffff) -#define PIO_INSTR_MEM30_RESET _u(0x00000000) -#define PIO_INSTR_MEM30_MSB _u(15) -#define PIO_INSTR_MEM30_LSB _u(0) -#define PIO_INSTR_MEM30_ACCESS "WO" -// ============================================================================= -// Register : PIO_INSTR_MEM31 -// Description : Write-only access to instruction memory location 31 -#define PIO_INSTR_MEM31_OFFSET _u(0x000000c4) -#define PIO_INSTR_MEM31_BITS _u(0x0000ffff) -#define PIO_INSTR_MEM31_RESET _u(0x00000000) -#define PIO_INSTR_MEM31_MSB _u(15) -#define PIO_INSTR_MEM31_LSB _u(0) -#define PIO_INSTR_MEM31_ACCESS "WO" -// ============================================================================= -// Register : PIO_SM0_CLKDIV -// Description : Clock divisor register for state machine 0 -// Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) -#define PIO_SM0_CLKDIV_OFFSET _u(0x000000c8) -#define PIO_SM0_CLKDIV_BITS _u(0xffffff00) -#define PIO_SM0_CLKDIV_RESET _u(0x00010000) -// ----------------------------------------------------------------------------- -// Field : PIO_SM0_CLKDIV_INT -// Description : Effective frequency is sysclk/(int + frac/256). -// Value of 0 is interpreted as 65536. If INT is 0, FRAC must also -// be 0. -#define PIO_SM0_CLKDIV_INT_RESET _u(0x0001) -#define PIO_SM0_CLKDIV_INT_BITS _u(0xffff0000) -#define PIO_SM0_CLKDIV_INT_MSB _u(31) -#define PIO_SM0_CLKDIV_INT_LSB _u(16) -#define PIO_SM0_CLKDIV_INT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM0_CLKDIV_FRAC -// Description : Fractional part of clock divisor -#define PIO_SM0_CLKDIV_FRAC_RESET _u(0x00) -#define PIO_SM0_CLKDIV_FRAC_BITS _u(0x0000ff00) -#define PIO_SM0_CLKDIV_FRAC_MSB _u(15) -#define PIO_SM0_CLKDIV_FRAC_LSB _u(8) -#define PIO_SM0_CLKDIV_FRAC_ACCESS "RW" -// ============================================================================= -// Register : PIO_SM0_EXECCTRL -// Description : Execution/behavioural settings for state machine 0 -#define PIO_SM0_EXECCTRL_OFFSET _u(0x000000cc) -#define PIO_SM0_EXECCTRL_BITS _u(0xffffffff) -#define PIO_SM0_EXECCTRL_RESET _u(0x0001f000) -// ----------------------------------------------------------------------------- -// Field : PIO_SM0_EXECCTRL_EXEC_STALLED -// Description : If 1, an instruction written to SMx_INSTR is stalled, and -// latched by the state machine. Will clear to 0 once this -// instruction completes. -#define PIO_SM0_EXECCTRL_EXEC_STALLED_RESET _u(0x0) -#define PIO_SM0_EXECCTRL_EXEC_STALLED_BITS _u(0x80000000) -#define PIO_SM0_EXECCTRL_EXEC_STALLED_MSB _u(31) -#define PIO_SM0_EXECCTRL_EXEC_STALLED_LSB _u(31) -#define PIO_SM0_EXECCTRL_EXEC_STALLED_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PIO_SM0_EXECCTRL_SIDE_EN -// Description : If 1, the MSB of the Delay/Side-set instruction field is used -// as side-set enable, rather than a side-set data bit. This -// allows instructions to perform side-set optionally, rather than -// on every instruction, but the maximum possible side-set width -// is reduced from 5 to 4. Note that the value of -// PINCTRL_SIDESET_COUNT is inclusive of this enable bit. -#define PIO_SM0_EXECCTRL_SIDE_EN_RESET _u(0x0) -#define PIO_SM0_EXECCTRL_SIDE_EN_BITS _u(0x40000000) -#define PIO_SM0_EXECCTRL_SIDE_EN_MSB _u(30) -#define PIO_SM0_EXECCTRL_SIDE_EN_LSB _u(30) -#define PIO_SM0_EXECCTRL_SIDE_EN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM0_EXECCTRL_SIDE_PINDIR -// Description : If 1, side-set data is asserted to pin directions, instead of -// pin values -#define PIO_SM0_EXECCTRL_SIDE_PINDIR_RESET _u(0x0) -#define PIO_SM0_EXECCTRL_SIDE_PINDIR_BITS _u(0x20000000) -#define PIO_SM0_EXECCTRL_SIDE_PINDIR_MSB _u(29) -#define PIO_SM0_EXECCTRL_SIDE_PINDIR_LSB _u(29) -#define PIO_SM0_EXECCTRL_SIDE_PINDIR_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM0_EXECCTRL_JMP_PIN -// Description : The GPIO number to use as condition for JMP PIN. Unaffected by -// input mapping. -#define PIO_SM0_EXECCTRL_JMP_PIN_RESET _u(0x00) -#define PIO_SM0_EXECCTRL_JMP_PIN_BITS _u(0x1f000000) -#define PIO_SM0_EXECCTRL_JMP_PIN_MSB _u(28) -#define PIO_SM0_EXECCTRL_JMP_PIN_LSB _u(24) -#define PIO_SM0_EXECCTRL_JMP_PIN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM0_EXECCTRL_OUT_EN_SEL -// Description : Which data bit to use for inline OUT enable -#define PIO_SM0_EXECCTRL_OUT_EN_SEL_RESET _u(0x00) -#define PIO_SM0_EXECCTRL_OUT_EN_SEL_BITS _u(0x00f80000) -#define PIO_SM0_EXECCTRL_OUT_EN_SEL_MSB _u(23) -#define PIO_SM0_EXECCTRL_OUT_EN_SEL_LSB _u(19) -#define PIO_SM0_EXECCTRL_OUT_EN_SEL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM0_EXECCTRL_INLINE_OUT_EN -// Description : If 1, use a bit of OUT data as an auxiliary write enable -// When used in conjunction with OUT_STICKY, writes with an enable -// of 0 will -// deassert the latest pin write. This can create useful -// masking/override behaviour -// due to the priority ordering of state machine pin writes (SM0 < -// SM1 < ...) -#define PIO_SM0_EXECCTRL_INLINE_OUT_EN_RESET _u(0x0) -#define PIO_SM0_EXECCTRL_INLINE_OUT_EN_BITS _u(0x00040000) -#define PIO_SM0_EXECCTRL_INLINE_OUT_EN_MSB _u(18) -#define PIO_SM0_EXECCTRL_INLINE_OUT_EN_LSB _u(18) -#define PIO_SM0_EXECCTRL_INLINE_OUT_EN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM0_EXECCTRL_OUT_STICKY -// Description : Continuously assert the most recent OUT/SET to the pins -#define PIO_SM0_EXECCTRL_OUT_STICKY_RESET _u(0x0) -#define PIO_SM0_EXECCTRL_OUT_STICKY_BITS _u(0x00020000) -#define PIO_SM0_EXECCTRL_OUT_STICKY_MSB _u(17) -#define PIO_SM0_EXECCTRL_OUT_STICKY_LSB _u(17) -#define PIO_SM0_EXECCTRL_OUT_STICKY_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM0_EXECCTRL_WRAP_TOP -// Description : After reaching this address, execution is wrapped to -// wrap_bottom. -// If the instruction is a jump, and the jump condition is true, -// the jump takes priority. -#define PIO_SM0_EXECCTRL_WRAP_TOP_RESET _u(0x1f) -#define PIO_SM0_EXECCTRL_WRAP_TOP_BITS _u(0x0001f000) -#define PIO_SM0_EXECCTRL_WRAP_TOP_MSB _u(16) -#define PIO_SM0_EXECCTRL_WRAP_TOP_LSB _u(12) -#define PIO_SM0_EXECCTRL_WRAP_TOP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM0_EXECCTRL_WRAP_BOTTOM -// Description : After reaching wrap_top, execution is wrapped to this address. -#define PIO_SM0_EXECCTRL_WRAP_BOTTOM_RESET _u(0x00) -#define PIO_SM0_EXECCTRL_WRAP_BOTTOM_BITS _u(0x00000f80) -#define PIO_SM0_EXECCTRL_WRAP_BOTTOM_MSB _u(11) -#define PIO_SM0_EXECCTRL_WRAP_BOTTOM_LSB _u(7) -#define PIO_SM0_EXECCTRL_WRAP_BOTTOM_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM0_EXECCTRL_STATUS_SEL -// Description : Comparison used for the MOV x, STATUS instruction. -// 0x0 -> All-ones if TX FIFO level < N, otherwise all-zeroes -// 0x1 -> All-ones if RX FIFO level < N, otherwise all-zeroes -// 0x2 -> All-ones if the indexed IRQ flag is raised, otherwise all-zeroes -#define PIO_SM0_EXECCTRL_STATUS_SEL_RESET _u(0x0) -#define PIO_SM0_EXECCTRL_STATUS_SEL_BITS _u(0x00000060) -#define PIO_SM0_EXECCTRL_STATUS_SEL_MSB _u(6) -#define PIO_SM0_EXECCTRL_STATUS_SEL_LSB _u(5) -#define PIO_SM0_EXECCTRL_STATUS_SEL_ACCESS "RW" -#define PIO_SM0_EXECCTRL_STATUS_SEL_VALUE_TXLEVEL _u(0x0) -#define PIO_SM0_EXECCTRL_STATUS_SEL_VALUE_RXLEVEL _u(0x1) -#define PIO_SM0_EXECCTRL_STATUS_SEL_VALUE_IRQ _u(0x2) -// ----------------------------------------------------------------------------- -// Field : PIO_SM0_EXECCTRL_STATUS_N -// Description : Comparison level or IRQ index for the MOV x, STATUS -// instruction. -// -// If STATUS_SEL is TXLEVEL or RXLEVEL, then values of STATUS_N -// greater than the current FIFO depth are reserved, and have -// undefined behaviour. -// 0x00 -> Index 0-7 of an IRQ flag in this PIO block -// 0x08 -> Index 0-7 of an IRQ flag in the next lower-numbered PIO block -// 0x10 -> Index 0-7 of an IRQ flag in the next higher-numbered PIO block -#define PIO_SM0_EXECCTRL_STATUS_N_RESET _u(0x00) -#define PIO_SM0_EXECCTRL_STATUS_N_BITS _u(0x0000001f) -#define PIO_SM0_EXECCTRL_STATUS_N_MSB _u(4) -#define PIO_SM0_EXECCTRL_STATUS_N_LSB _u(0) -#define PIO_SM0_EXECCTRL_STATUS_N_ACCESS "RW" -#define PIO_SM0_EXECCTRL_STATUS_N_VALUE_IRQ _u(0x00) -#define PIO_SM0_EXECCTRL_STATUS_N_VALUE_IRQ_PREVPIO _u(0x08) -#define PIO_SM0_EXECCTRL_STATUS_N_VALUE_IRQ_NEXTPIO _u(0x10) -// ============================================================================= -// Register : PIO_SM0_SHIFTCTRL -// Description : Control behaviour of the input/output shift registers for state -// machine 0 -#define PIO_SM0_SHIFTCTRL_OFFSET _u(0x000000d0) -#define PIO_SM0_SHIFTCTRL_BITS _u(0xffffc01f) -#define PIO_SM0_SHIFTCTRL_RESET _u(0x000c0000) -// ----------------------------------------------------------------------------- -// Field : PIO_SM0_SHIFTCTRL_FJOIN_RX -// Description : When 1, RX FIFO steals the TX FIFO's storage, and becomes twice -// as deep. -// TX FIFO is disabled as a result (always reads as both full and -// empty). -// FIFOs are flushed when this bit is changed. -#define PIO_SM0_SHIFTCTRL_FJOIN_RX_RESET _u(0x0) -#define PIO_SM0_SHIFTCTRL_FJOIN_RX_BITS _u(0x80000000) -#define PIO_SM0_SHIFTCTRL_FJOIN_RX_MSB _u(31) -#define PIO_SM0_SHIFTCTRL_FJOIN_RX_LSB _u(31) -#define PIO_SM0_SHIFTCTRL_FJOIN_RX_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM0_SHIFTCTRL_FJOIN_TX -// Description : When 1, TX FIFO steals the RX FIFO's storage, and becomes twice -// as deep. -// RX FIFO is disabled as a result (always reads as both full and -// empty). -// FIFOs are flushed when this bit is changed. -#define PIO_SM0_SHIFTCTRL_FJOIN_TX_RESET _u(0x0) -#define PIO_SM0_SHIFTCTRL_FJOIN_TX_BITS _u(0x40000000) -#define PIO_SM0_SHIFTCTRL_FJOIN_TX_MSB _u(30) -#define PIO_SM0_SHIFTCTRL_FJOIN_TX_LSB _u(30) -#define PIO_SM0_SHIFTCTRL_FJOIN_TX_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM0_SHIFTCTRL_PULL_THRESH -// Description : Number of bits shifted out of OSR before autopull, or -// conditional pull (PULL IFEMPTY), will take place. -// Write 0 for value of 32. -#define PIO_SM0_SHIFTCTRL_PULL_THRESH_RESET _u(0x00) -#define PIO_SM0_SHIFTCTRL_PULL_THRESH_BITS _u(0x3e000000) -#define PIO_SM0_SHIFTCTRL_PULL_THRESH_MSB _u(29) -#define PIO_SM0_SHIFTCTRL_PULL_THRESH_LSB _u(25) -#define PIO_SM0_SHIFTCTRL_PULL_THRESH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM0_SHIFTCTRL_PUSH_THRESH -// Description : Number of bits shifted into ISR before autopush, or conditional -// push (PUSH IFFULL), will take place. -// Write 0 for value of 32. -#define PIO_SM0_SHIFTCTRL_PUSH_THRESH_RESET _u(0x00) -#define PIO_SM0_SHIFTCTRL_PUSH_THRESH_BITS _u(0x01f00000) -#define PIO_SM0_SHIFTCTRL_PUSH_THRESH_MSB _u(24) -#define PIO_SM0_SHIFTCTRL_PUSH_THRESH_LSB _u(20) -#define PIO_SM0_SHIFTCTRL_PUSH_THRESH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR -// Description : 1 = shift out of output shift register to right. 0 = to left. -#define PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR_RESET _u(0x1) -#define PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR_BITS _u(0x00080000) -#define PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR_MSB _u(19) -#define PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR_LSB _u(19) -#define PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM0_SHIFTCTRL_IN_SHIFTDIR -// Description : 1 = shift input shift register to right (data enters from -// left). 0 = to left. -#define PIO_SM0_SHIFTCTRL_IN_SHIFTDIR_RESET _u(0x1) -#define PIO_SM0_SHIFTCTRL_IN_SHIFTDIR_BITS _u(0x00040000) -#define PIO_SM0_SHIFTCTRL_IN_SHIFTDIR_MSB _u(18) -#define PIO_SM0_SHIFTCTRL_IN_SHIFTDIR_LSB _u(18) -#define PIO_SM0_SHIFTCTRL_IN_SHIFTDIR_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM0_SHIFTCTRL_AUTOPULL -// Description : Pull automatically when the output shift register is emptied, -// i.e. on or following an OUT instruction which causes the output -// shift counter to reach or exceed PULL_THRESH. -#define PIO_SM0_SHIFTCTRL_AUTOPULL_RESET _u(0x0) -#define PIO_SM0_SHIFTCTRL_AUTOPULL_BITS _u(0x00020000) -#define PIO_SM0_SHIFTCTRL_AUTOPULL_MSB _u(17) -#define PIO_SM0_SHIFTCTRL_AUTOPULL_LSB _u(17) -#define PIO_SM0_SHIFTCTRL_AUTOPULL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM0_SHIFTCTRL_AUTOPUSH -// Description : Push automatically when the input shift register is filled, -// i.e. on an IN instruction which causes the input shift counter -// to reach or exceed PUSH_THRESH. -#define PIO_SM0_SHIFTCTRL_AUTOPUSH_RESET _u(0x0) -#define PIO_SM0_SHIFTCTRL_AUTOPUSH_BITS _u(0x00010000) -#define PIO_SM0_SHIFTCTRL_AUTOPUSH_MSB _u(16) -#define PIO_SM0_SHIFTCTRL_AUTOPUSH_LSB _u(16) -#define PIO_SM0_SHIFTCTRL_AUTOPUSH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM0_SHIFTCTRL_FJOIN_RX_PUT -// Description : If 1, disable this state machine's RX FIFO, make its storage -// available for random write access by the state machine (using -// the `put` instruction) and, unless FJOIN_RX_GET is also set, -// random read access by the processor (through the RXFx_PUTGETy -// registers). -// -// If FJOIN_RX_PUT and FJOIN_RX_GET are both set, then the RX -// FIFO's registers can be randomly read/written by the state -// machine, but are completely inaccessible to the processor. -// -// Setting this bit will clear the FJOIN_TX and FJOIN_RX bits. -#define PIO_SM0_SHIFTCTRL_FJOIN_RX_PUT_RESET _u(0x0) -#define PIO_SM0_SHIFTCTRL_FJOIN_RX_PUT_BITS _u(0x00008000) -#define PIO_SM0_SHIFTCTRL_FJOIN_RX_PUT_MSB _u(15) -#define PIO_SM0_SHIFTCTRL_FJOIN_RX_PUT_LSB _u(15) -#define PIO_SM0_SHIFTCTRL_FJOIN_RX_PUT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM0_SHIFTCTRL_FJOIN_RX_GET -// Description : If 1, disable this state machine's RX FIFO, make its storage -// available for random read access by the state machine (using -// the `get` instruction) and, unless FJOIN_RX_PUT is also set, -// random write access by the processor (through the RXFx_PUTGETy -// registers). -// -// If FJOIN_RX_PUT and FJOIN_RX_GET are both set, then the RX -// FIFO's registers can be randomly read/written by the state -// machine, but are completely inaccessible to the processor. -// -// Setting this bit will clear the FJOIN_TX and FJOIN_RX bits. -#define PIO_SM0_SHIFTCTRL_FJOIN_RX_GET_RESET _u(0x0) -#define PIO_SM0_SHIFTCTRL_FJOIN_RX_GET_BITS _u(0x00004000) -#define PIO_SM0_SHIFTCTRL_FJOIN_RX_GET_MSB _u(14) -#define PIO_SM0_SHIFTCTRL_FJOIN_RX_GET_LSB _u(14) -#define PIO_SM0_SHIFTCTRL_FJOIN_RX_GET_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM0_SHIFTCTRL_IN_COUNT -// Description : Set the number of pins which are not masked to 0 when read by -// an IN PINS, WAIT PIN or MOV x, PINS instruction. -// -// For example, an IN_COUNT of 5 means that the 5 LSBs of the IN -// pin group are visible (bits 4:0), but the remaining 27 MSBs are -// masked to 0. A count of 32 is encoded with a field value of 0, -// so the default behaviour is to not perform any masking. -// -// Note this masking is applied in addition to the masking usually -// performed by the IN instruction. This is mainly useful for the -// MOV x, PINS instruction, which otherwise has no way of masking -// pins. -#define PIO_SM0_SHIFTCTRL_IN_COUNT_RESET _u(0x00) -#define PIO_SM0_SHIFTCTRL_IN_COUNT_BITS _u(0x0000001f) -#define PIO_SM0_SHIFTCTRL_IN_COUNT_MSB _u(4) -#define PIO_SM0_SHIFTCTRL_IN_COUNT_LSB _u(0) -#define PIO_SM0_SHIFTCTRL_IN_COUNT_ACCESS "RW" -// ============================================================================= -// Register : PIO_SM0_ADDR -// Description : Current instruction address of state machine 0 -#define PIO_SM0_ADDR_OFFSET _u(0x000000d4) -#define PIO_SM0_ADDR_BITS _u(0x0000001f) -#define PIO_SM0_ADDR_RESET _u(0x00000000) -#define PIO_SM0_ADDR_MSB _u(4) -#define PIO_SM0_ADDR_LSB _u(0) -#define PIO_SM0_ADDR_ACCESS "RO" -// ============================================================================= -// Register : PIO_SM0_INSTR -// Description : Read to see the instruction currently addressed by state -// machine 0's program counter -// Write to execute an instruction immediately (including jumps) -// and then resume execution. -#define PIO_SM0_INSTR_OFFSET _u(0x000000d8) -#define PIO_SM0_INSTR_BITS _u(0x0000ffff) -#define PIO_SM0_INSTR_RESET "-" -#define PIO_SM0_INSTR_MSB _u(15) -#define PIO_SM0_INSTR_LSB _u(0) -#define PIO_SM0_INSTR_ACCESS "RW" -// ============================================================================= -// Register : PIO_SM0_PINCTRL -// Description : State machine pin control -#define PIO_SM0_PINCTRL_OFFSET _u(0x000000dc) -#define PIO_SM0_PINCTRL_BITS _u(0xffffffff) -#define PIO_SM0_PINCTRL_RESET _u(0x14000000) -// ----------------------------------------------------------------------------- -// Field : PIO_SM0_PINCTRL_SIDESET_COUNT -// Description : The number of MSBs of the Delay/Side-set instruction field -// which are used for side-set. Inclusive of the enable bit, if -// present. Minimum of 0 (all delay bits, no side-set) and maximum -// of 5 (all side-set, no delay). -#define PIO_SM0_PINCTRL_SIDESET_COUNT_RESET _u(0x0) -#define PIO_SM0_PINCTRL_SIDESET_COUNT_BITS _u(0xe0000000) -#define PIO_SM0_PINCTRL_SIDESET_COUNT_MSB _u(31) -#define PIO_SM0_PINCTRL_SIDESET_COUNT_LSB _u(29) -#define PIO_SM0_PINCTRL_SIDESET_COUNT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM0_PINCTRL_SET_COUNT -// Description : The number of pins asserted by a SET. In the range 0 to 5 -// inclusive. -#define PIO_SM0_PINCTRL_SET_COUNT_RESET _u(0x5) -#define PIO_SM0_PINCTRL_SET_COUNT_BITS _u(0x1c000000) -#define PIO_SM0_PINCTRL_SET_COUNT_MSB _u(28) -#define PIO_SM0_PINCTRL_SET_COUNT_LSB _u(26) -#define PIO_SM0_PINCTRL_SET_COUNT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM0_PINCTRL_OUT_COUNT -// Description : The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV -// PINS instruction. In the range 0 to 32 inclusive. -#define PIO_SM0_PINCTRL_OUT_COUNT_RESET _u(0x00) -#define PIO_SM0_PINCTRL_OUT_COUNT_BITS _u(0x03f00000) -#define PIO_SM0_PINCTRL_OUT_COUNT_MSB _u(25) -#define PIO_SM0_PINCTRL_OUT_COUNT_LSB _u(20) -#define PIO_SM0_PINCTRL_OUT_COUNT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM0_PINCTRL_IN_BASE -// Description : The pin which is mapped to the least-significant bit of a state -// machine's IN data bus. Higher-numbered pins are mapped to -// consecutively more-significant data bits, with a modulo of 32 -// applied to pin number. -#define PIO_SM0_PINCTRL_IN_BASE_RESET _u(0x00) -#define PIO_SM0_PINCTRL_IN_BASE_BITS _u(0x000f8000) -#define PIO_SM0_PINCTRL_IN_BASE_MSB _u(19) -#define PIO_SM0_PINCTRL_IN_BASE_LSB _u(15) -#define PIO_SM0_PINCTRL_IN_BASE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM0_PINCTRL_SIDESET_BASE -// Description : The lowest-numbered pin that will be affected by a side-set -// operation. The MSBs of an instruction's side-set/delay field -// (up to 5, determined by SIDESET_COUNT) are used for side-set -// data, with the remaining LSBs used for delay. The least- -// significant bit of the side-set portion is the bit written to -// this pin, with more-significant bits written to higher-numbered -// pins. -#define PIO_SM0_PINCTRL_SIDESET_BASE_RESET _u(0x00) -#define PIO_SM0_PINCTRL_SIDESET_BASE_BITS _u(0x00007c00) -#define PIO_SM0_PINCTRL_SIDESET_BASE_MSB _u(14) -#define PIO_SM0_PINCTRL_SIDESET_BASE_LSB _u(10) -#define PIO_SM0_PINCTRL_SIDESET_BASE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM0_PINCTRL_SET_BASE -// Description : The lowest-numbered pin that will be affected by a SET PINS or -// SET PINDIRS instruction. The data written to this pin is the -// least-significant bit of the SET data. -#define PIO_SM0_PINCTRL_SET_BASE_RESET _u(0x00) -#define PIO_SM0_PINCTRL_SET_BASE_BITS _u(0x000003e0) -#define PIO_SM0_PINCTRL_SET_BASE_MSB _u(9) -#define PIO_SM0_PINCTRL_SET_BASE_LSB _u(5) -#define PIO_SM0_PINCTRL_SET_BASE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM0_PINCTRL_OUT_BASE -// Description : The lowest-numbered pin that will be affected by an OUT PINS, -// OUT PINDIRS or MOV PINS instruction. The data written to this -// pin will always be the least-significant bit of the OUT or MOV -// data. -#define PIO_SM0_PINCTRL_OUT_BASE_RESET _u(0x00) -#define PIO_SM0_PINCTRL_OUT_BASE_BITS _u(0x0000001f) -#define PIO_SM0_PINCTRL_OUT_BASE_MSB _u(4) -#define PIO_SM0_PINCTRL_OUT_BASE_LSB _u(0) -#define PIO_SM0_PINCTRL_OUT_BASE_ACCESS "RW" -// ============================================================================= -// Register : PIO_SM1_CLKDIV -// Description : Clock divisor register for state machine 1 -// Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) -#define PIO_SM1_CLKDIV_OFFSET _u(0x000000e0) -#define PIO_SM1_CLKDIV_BITS _u(0xffffff00) -#define PIO_SM1_CLKDIV_RESET _u(0x00010000) -// ----------------------------------------------------------------------------- -// Field : PIO_SM1_CLKDIV_INT -// Description : Effective frequency is sysclk/(int + frac/256). -// Value of 0 is interpreted as 65536. If INT is 0, FRAC must also -// be 0. -#define PIO_SM1_CLKDIV_INT_RESET _u(0x0001) -#define PIO_SM1_CLKDIV_INT_BITS _u(0xffff0000) -#define PIO_SM1_CLKDIV_INT_MSB _u(31) -#define PIO_SM1_CLKDIV_INT_LSB _u(16) -#define PIO_SM1_CLKDIV_INT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM1_CLKDIV_FRAC -// Description : Fractional part of clock divisor -#define PIO_SM1_CLKDIV_FRAC_RESET _u(0x00) -#define PIO_SM1_CLKDIV_FRAC_BITS _u(0x0000ff00) -#define PIO_SM1_CLKDIV_FRAC_MSB _u(15) -#define PIO_SM1_CLKDIV_FRAC_LSB _u(8) -#define PIO_SM1_CLKDIV_FRAC_ACCESS "RW" -// ============================================================================= -// Register : PIO_SM1_EXECCTRL -// Description : Execution/behavioural settings for state machine 1 -#define PIO_SM1_EXECCTRL_OFFSET _u(0x000000e4) -#define PIO_SM1_EXECCTRL_BITS _u(0xffffffff) -#define PIO_SM1_EXECCTRL_RESET _u(0x0001f000) -// ----------------------------------------------------------------------------- -// Field : PIO_SM1_EXECCTRL_EXEC_STALLED -// Description : If 1, an instruction written to SMx_INSTR is stalled, and -// latched by the state machine. Will clear to 0 once this -// instruction completes. -#define PIO_SM1_EXECCTRL_EXEC_STALLED_RESET _u(0x0) -#define PIO_SM1_EXECCTRL_EXEC_STALLED_BITS _u(0x80000000) -#define PIO_SM1_EXECCTRL_EXEC_STALLED_MSB _u(31) -#define PIO_SM1_EXECCTRL_EXEC_STALLED_LSB _u(31) -#define PIO_SM1_EXECCTRL_EXEC_STALLED_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PIO_SM1_EXECCTRL_SIDE_EN -// Description : If 1, the MSB of the Delay/Side-set instruction field is used -// as side-set enable, rather than a side-set data bit. This -// allows instructions to perform side-set optionally, rather than -// on every instruction, but the maximum possible side-set width -// is reduced from 5 to 4. Note that the value of -// PINCTRL_SIDESET_COUNT is inclusive of this enable bit. -#define PIO_SM1_EXECCTRL_SIDE_EN_RESET _u(0x0) -#define PIO_SM1_EXECCTRL_SIDE_EN_BITS _u(0x40000000) -#define PIO_SM1_EXECCTRL_SIDE_EN_MSB _u(30) -#define PIO_SM1_EXECCTRL_SIDE_EN_LSB _u(30) -#define PIO_SM1_EXECCTRL_SIDE_EN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM1_EXECCTRL_SIDE_PINDIR -// Description : If 1, side-set data is asserted to pin directions, instead of -// pin values -#define PIO_SM1_EXECCTRL_SIDE_PINDIR_RESET _u(0x0) -#define PIO_SM1_EXECCTRL_SIDE_PINDIR_BITS _u(0x20000000) -#define PIO_SM1_EXECCTRL_SIDE_PINDIR_MSB _u(29) -#define PIO_SM1_EXECCTRL_SIDE_PINDIR_LSB _u(29) -#define PIO_SM1_EXECCTRL_SIDE_PINDIR_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM1_EXECCTRL_JMP_PIN -// Description : The GPIO number to use as condition for JMP PIN. Unaffected by -// input mapping. -#define PIO_SM1_EXECCTRL_JMP_PIN_RESET _u(0x00) -#define PIO_SM1_EXECCTRL_JMP_PIN_BITS _u(0x1f000000) -#define PIO_SM1_EXECCTRL_JMP_PIN_MSB _u(28) -#define PIO_SM1_EXECCTRL_JMP_PIN_LSB _u(24) -#define PIO_SM1_EXECCTRL_JMP_PIN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM1_EXECCTRL_OUT_EN_SEL -// Description : Which data bit to use for inline OUT enable -#define PIO_SM1_EXECCTRL_OUT_EN_SEL_RESET _u(0x00) -#define PIO_SM1_EXECCTRL_OUT_EN_SEL_BITS _u(0x00f80000) -#define PIO_SM1_EXECCTRL_OUT_EN_SEL_MSB _u(23) -#define PIO_SM1_EXECCTRL_OUT_EN_SEL_LSB _u(19) -#define PIO_SM1_EXECCTRL_OUT_EN_SEL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM1_EXECCTRL_INLINE_OUT_EN -// Description : If 1, use a bit of OUT data as an auxiliary write enable -// When used in conjunction with OUT_STICKY, writes with an enable -// of 0 will -// deassert the latest pin write. This can create useful -// masking/override behaviour -// due to the priority ordering of state machine pin writes (SM0 < -// SM1 < ...) -#define PIO_SM1_EXECCTRL_INLINE_OUT_EN_RESET _u(0x0) -#define PIO_SM1_EXECCTRL_INLINE_OUT_EN_BITS _u(0x00040000) -#define PIO_SM1_EXECCTRL_INLINE_OUT_EN_MSB _u(18) -#define PIO_SM1_EXECCTRL_INLINE_OUT_EN_LSB _u(18) -#define PIO_SM1_EXECCTRL_INLINE_OUT_EN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM1_EXECCTRL_OUT_STICKY -// Description : Continuously assert the most recent OUT/SET to the pins -#define PIO_SM1_EXECCTRL_OUT_STICKY_RESET _u(0x0) -#define PIO_SM1_EXECCTRL_OUT_STICKY_BITS _u(0x00020000) -#define PIO_SM1_EXECCTRL_OUT_STICKY_MSB _u(17) -#define PIO_SM1_EXECCTRL_OUT_STICKY_LSB _u(17) -#define PIO_SM1_EXECCTRL_OUT_STICKY_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM1_EXECCTRL_WRAP_TOP -// Description : After reaching this address, execution is wrapped to -// wrap_bottom. -// If the instruction is a jump, and the jump condition is true, -// the jump takes priority. -#define PIO_SM1_EXECCTRL_WRAP_TOP_RESET _u(0x1f) -#define PIO_SM1_EXECCTRL_WRAP_TOP_BITS _u(0x0001f000) -#define PIO_SM1_EXECCTRL_WRAP_TOP_MSB _u(16) -#define PIO_SM1_EXECCTRL_WRAP_TOP_LSB _u(12) -#define PIO_SM1_EXECCTRL_WRAP_TOP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM1_EXECCTRL_WRAP_BOTTOM -// Description : After reaching wrap_top, execution is wrapped to this address. -#define PIO_SM1_EXECCTRL_WRAP_BOTTOM_RESET _u(0x00) -#define PIO_SM1_EXECCTRL_WRAP_BOTTOM_BITS _u(0x00000f80) -#define PIO_SM1_EXECCTRL_WRAP_BOTTOM_MSB _u(11) -#define PIO_SM1_EXECCTRL_WRAP_BOTTOM_LSB _u(7) -#define PIO_SM1_EXECCTRL_WRAP_BOTTOM_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM1_EXECCTRL_STATUS_SEL -// Description : Comparison used for the MOV x, STATUS instruction. -// 0x0 -> All-ones if TX FIFO level < N, otherwise all-zeroes -// 0x1 -> All-ones if RX FIFO level < N, otherwise all-zeroes -// 0x2 -> All-ones if the indexed IRQ flag is raised, otherwise all-zeroes -#define PIO_SM1_EXECCTRL_STATUS_SEL_RESET _u(0x0) -#define PIO_SM1_EXECCTRL_STATUS_SEL_BITS _u(0x00000060) -#define PIO_SM1_EXECCTRL_STATUS_SEL_MSB _u(6) -#define PIO_SM1_EXECCTRL_STATUS_SEL_LSB _u(5) -#define PIO_SM1_EXECCTRL_STATUS_SEL_ACCESS "RW" -#define PIO_SM1_EXECCTRL_STATUS_SEL_VALUE_TXLEVEL _u(0x0) -#define PIO_SM1_EXECCTRL_STATUS_SEL_VALUE_RXLEVEL _u(0x1) -#define PIO_SM1_EXECCTRL_STATUS_SEL_VALUE_IRQ _u(0x2) -// ----------------------------------------------------------------------------- -// Field : PIO_SM1_EXECCTRL_STATUS_N -// Description : Comparison level or IRQ index for the MOV x, STATUS -// instruction. -// -// If STATUS_SEL is TXLEVEL or RXLEVEL, then values of STATUS_N -// greater than the current FIFO depth are reserved, and have -// undefined behaviour. -// 0x00 -> Index 0-7 of an IRQ flag in this PIO block -// 0x08 -> Index 0-7 of an IRQ flag in the next lower-numbered PIO block -// 0x10 -> Index 0-7 of an IRQ flag in the next higher-numbered PIO block -#define PIO_SM1_EXECCTRL_STATUS_N_RESET _u(0x00) -#define PIO_SM1_EXECCTRL_STATUS_N_BITS _u(0x0000001f) -#define PIO_SM1_EXECCTRL_STATUS_N_MSB _u(4) -#define PIO_SM1_EXECCTRL_STATUS_N_LSB _u(0) -#define PIO_SM1_EXECCTRL_STATUS_N_ACCESS "RW" -#define PIO_SM1_EXECCTRL_STATUS_N_VALUE_IRQ _u(0x00) -#define PIO_SM1_EXECCTRL_STATUS_N_VALUE_IRQ_PREVPIO _u(0x08) -#define PIO_SM1_EXECCTRL_STATUS_N_VALUE_IRQ_NEXTPIO _u(0x10) -// ============================================================================= -// Register : PIO_SM1_SHIFTCTRL -// Description : Control behaviour of the input/output shift registers for state -// machine 1 -#define PIO_SM1_SHIFTCTRL_OFFSET _u(0x000000e8) -#define PIO_SM1_SHIFTCTRL_BITS _u(0xffffc01f) -#define PIO_SM1_SHIFTCTRL_RESET _u(0x000c0000) -// ----------------------------------------------------------------------------- -// Field : PIO_SM1_SHIFTCTRL_FJOIN_RX -// Description : When 1, RX FIFO steals the TX FIFO's storage, and becomes twice -// as deep. -// TX FIFO is disabled as a result (always reads as both full and -// empty). -// FIFOs are flushed when this bit is changed. -#define PIO_SM1_SHIFTCTRL_FJOIN_RX_RESET _u(0x0) -#define PIO_SM1_SHIFTCTRL_FJOIN_RX_BITS _u(0x80000000) -#define PIO_SM1_SHIFTCTRL_FJOIN_RX_MSB _u(31) -#define PIO_SM1_SHIFTCTRL_FJOIN_RX_LSB _u(31) -#define PIO_SM1_SHIFTCTRL_FJOIN_RX_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM1_SHIFTCTRL_FJOIN_TX -// Description : When 1, TX FIFO steals the RX FIFO's storage, and becomes twice -// as deep. -// RX FIFO is disabled as a result (always reads as both full and -// empty). -// FIFOs are flushed when this bit is changed. -#define PIO_SM1_SHIFTCTRL_FJOIN_TX_RESET _u(0x0) -#define PIO_SM1_SHIFTCTRL_FJOIN_TX_BITS _u(0x40000000) -#define PIO_SM1_SHIFTCTRL_FJOIN_TX_MSB _u(30) -#define PIO_SM1_SHIFTCTRL_FJOIN_TX_LSB _u(30) -#define PIO_SM1_SHIFTCTRL_FJOIN_TX_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM1_SHIFTCTRL_PULL_THRESH -// Description : Number of bits shifted out of OSR before autopull, or -// conditional pull (PULL IFEMPTY), will take place. -// Write 0 for value of 32. -#define PIO_SM1_SHIFTCTRL_PULL_THRESH_RESET _u(0x00) -#define PIO_SM1_SHIFTCTRL_PULL_THRESH_BITS _u(0x3e000000) -#define PIO_SM1_SHIFTCTRL_PULL_THRESH_MSB _u(29) -#define PIO_SM1_SHIFTCTRL_PULL_THRESH_LSB _u(25) -#define PIO_SM1_SHIFTCTRL_PULL_THRESH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM1_SHIFTCTRL_PUSH_THRESH -// Description : Number of bits shifted into ISR before autopush, or conditional -// push (PUSH IFFULL), will take place. -// Write 0 for value of 32. -#define PIO_SM1_SHIFTCTRL_PUSH_THRESH_RESET _u(0x00) -#define PIO_SM1_SHIFTCTRL_PUSH_THRESH_BITS _u(0x01f00000) -#define PIO_SM1_SHIFTCTRL_PUSH_THRESH_MSB _u(24) -#define PIO_SM1_SHIFTCTRL_PUSH_THRESH_LSB _u(20) -#define PIO_SM1_SHIFTCTRL_PUSH_THRESH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM1_SHIFTCTRL_OUT_SHIFTDIR -// Description : 1 = shift out of output shift register to right. 0 = to left. -#define PIO_SM1_SHIFTCTRL_OUT_SHIFTDIR_RESET _u(0x1) -#define PIO_SM1_SHIFTCTRL_OUT_SHIFTDIR_BITS _u(0x00080000) -#define PIO_SM1_SHIFTCTRL_OUT_SHIFTDIR_MSB _u(19) -#define PIO_SM1_SHIFTCTRL_OUT_SHIFTDIR_LSB _u(19) -#define PIO_SM1_SHIFTCTRL_OUT_SHIFTDIR_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM1_SHIFTCTRL_IN_SHIFTDIR -// Description : 1 = shift input shift register to right (data enters from -// left). 0 = to left. -#define PIO_SM1_SHIFTCTRL_IN_SHIFTDIR_RESET _u(0x1) -#define PIO_SM1_SHIFTCTRL_IN_SHIFTDIR_BITS _u(0x00040000) -#define PIO_SM1_SHIFTCTRL_IN_SHIFTDIR_MSB _u(18) -#define PIO_SM1_SHIFTCTRL_IN_SHIFTDIR_LSB _u(18) -#define PIO_SM1_SHIFTCTRL_IN_SHIFTDIR_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM1_SHIFTCTRL_AUTOPULL -// Description : Pull automatically when the output shift register is emptied, -// i.e. on or following an OUT instruction which causes the output -// shift counter to reach or exceed PULL_THRESH. -#define PIO_SM1_SHIFTCTRL_AUTOPULL_RESET _u(0x0) -#define PIO_SM1_SHIFTCTRL_AUTOPULL_BITS _u(0x00020000) -#define PIO_SM1_SHIFTCTRL_AUTOPULL_MSB _u(17) -#define PIO_SM1_SHIFTCTRL_AUTOPULL_LSB _u(17) -#define PIO_SM1_SHIFTCTRL_AUTOPULL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM1_SHIFTCTRL_AUTOPUSH -// Description : Push automatically when the input shift register is filled, -// i.e. on an IN instruction which causes the input shift counter -// to reach or exceed PUSH_THRESH. -#define PIO_SM1_SHIFTCTRL_AUTOPUSH_RESET _u(0x0) -#define PIO_SM1_SHIFTCTRL_AUTOPUSH_BITS _u(0x00010000) -#define PIO_SM1_SHIFTCTRL_AUTOPUSH_MSB _u(16) -#define PIO_SM1_SHIFTCTRL_AUTOPUSH_LSB _u(16) -#define PIO_SM1_SHIFTCTRL_AUTOPUSH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM1_SHIFTCTRL_FJOIN_RX_PUT -// Description : If 1, disable this state machine's RX FIFO, make its storage -// available for random write access by the state machine (using -// the `put` instruction) and, unless FJOIN_RX_GET is also set, -// random read access by the processor (through the RXFx_PUTGETy -// registers). -// -// If FJOIN_RX_PUT and FJOIN_RX_GET are both set, then the RX -// FIFO's registers can be randomly read/written by the state -// machine, but are completely inaccessible to the processor. -// -// Setting this bit will clear the FJOIN_TX and FJOIN_RX bits. -#define PIO_SM1_SHIFTCTRL_FJOIN_RX_PUT_RESET _u(0x0) -#define PIO_SM1_SHIFTCTRL_FJOIN_RX_PUT_BITS _u(0x00008000) -#define PIO_SM1_SHIFTCTRL_FJOIN_RX_PUT_MSB _u(15) -#define PIO_SM1_SHIFTCTRL_FJOIN_RX_PUT_LSB _u(15) -#define PIO_SM1_SHIFTCTRL_FJOIN_RX_PUT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM1_SHIFTCTRL_FJOIN_RX_GET -// Description : If 1, disable this state machine's RX FIFO, make its storage -// available for random read access by the state machine (using -// the `get` instruction) and, unless FJOIN_RX_PUT is also set, -// random write access by the processor (through the RXFx_PUTGETy -// registers). -// -// If FJOIN_RX_PUT and FJOIN_RX_GET are both set, then the RX -// FIFO's registers can be randomly read/written by the state -// machine, but are completely inaccessible to the processor. -// -// Setting this bit will clear the FJOIN_TX and FJOIN_RX bits. -#define PIO_SM1_SHIFTCTRL_FJOIN_RX_GET_RESET _u(0x0) -#define PIO_SM1_SHIFTCTRL_FJOIN_RX_GET_BITS _u(0x00004000) -#define PIO_SM1_SHIFTCTRL_FJOIN_RX_GET_MSB _u(14) -#define PIO_SM1_SHIFTCTRL_FJOIN_RX_GET_LSB _u(14) -#define PIO_SM1_SHIFTCTRL_FJOIN_RX_GET_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM1_SHIFTCTRL_IN_COUNT -// Description : Set the number of pins which are not masked to 0 when read by -// an IN PINS, WAIT PIN or MOV x, PINS instruction. -// -// For example, an IN_COUNT of 5 means that the 5 LSBs of the IN -// pin group are visible (bits 4:0), but the remaining 27 MSBs are -// masked to 0. A count of 32 is encoded with a field value of 0, -// so the default behaviour is to not perform any masking. -// -// Note this masking is applied in addition to the masking usually -// performed by the IN instruction. This is mainly useful for the -// MOV x, PINS instruction, which otherwise has no way of masking -// pins. -#define PIO_SM1_SHIFTCTRL_IN_COUNT_RESET _u(0x00) -#define PIO_SM1_SHIFTCTRL_IN_COUNT_BITS _u(0x0000001f) -#define PIO_SM1_SHIFTCTRL_IN_COUNT_MSB _u(4) -#define PIO_SM1_SHIFTCTRL_IN_COUNT_LSB _u(0) -#define PIO_SM1_SHIFTCTRL_IN_COUNT_ACCESS "RW" -// ============================================================================= -// Register : PIO_SM1_ADDR -// Description : Current instruction address of state machine 1 -#define PIO_SM1_ADDR_OFFSET _u(0x000000ec) -#define PIO_SM1_ADDR_BITS _u(0x0000001f) -#define PIO_SM1_ADDR_RESET _u(0x00000000) -#define PIO_SM1_ADDR_MSB _u(4) -#define PIO_SM1_ADDR_LSB _u(0) -#define PIO_SM1_ADDR_ACCESS "RO" -// ============================================================================= -// Register : PIO_SM1_INSTR -// Description : Read to see the instruction currently addressed by state -// machine 1's program counter -// Write to execute an instruction immediately (including jumps) -// and then resume execution. -#define PIO_SM1_INSTR_OFFSET _u(0x000000f0) -#define PIO_SM1_INSTR_BITS _u(0x0000ffff) -#define PIO_SM1_INSTR_RESET "-" -#define PIO_SM1_INSTR_MSB _u(15) -#define PIO_SM1_INSTR_LSB _u(0) -#define PIO_SM1_INSTR_ACCESS "RW" -// ============================================================================= -// Register : PIO_SM1_PINCTRL -// Description : State machine pin control -#define PIO_SM1_PINCTRL_OFFSET _u(0x000000f4) -#define PIO_SM1_PINCTRL_BITS _u(0xffffffff) -#define PIO_SM1_PINCTRL_RESET _u(0x14000000) -// ----------------------------------------------------------------------------- -// Field : PIO_SM1_PINCTRL_SIDESET_COUNT -// Description : The number of MSBs of the Delay/Side-set instruction field -// which are used for side-set. Inclusive of the enable bit, if -// present. Minimum of 0 (all delay bits, no side-set) and maximum -// of 5 (all side-set, no delay). -#define PIO_SM1_PINCTRL_SIDESET_COUNT_RESET _u(0x0) -#define PIO_SM1_PINCTRL_SIDESET_COUNT_BITS _u(0xe0000000) -#define PIO_SM1_PINCTRL_SIDESET_COUNT_MSB _u(31) -#define PIO_SM1_PINCTRL_SIDESET_COUNT_LSB _u(29) -#define PIO_SM1_PINCTRL_SIDESET_COUNT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM1_PINCTRL_SET_COUNT -// Description : The number of pins asserted by a SET. In the range 0 to 5 -// inclusive. -#define PIO_SM1_PINCTRL_SET_COUNT_RESET _u(0x5) -#define PIO_SM1_PINCTRL_SET_COUNT_BITS _u(0x1c000000) -#define PIO_SM1_PINCTRL_SET_COUNT_MSB _u(28) -#define PIO_SM1_PINCTRL_SET_COUNT_LSB _u(26) -#define PIO_SM1_PINCTRL_SET_COUNT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM1_PINCTRL_OUT_COUNT -// Description : The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV -// PINS instruction. In the range 0 to 32 inclusive. -#define PIO_SM1_PINCTRL_OUT_COUNT_RESET _u(0x00) -#define PIO_SM1_PINCTRL_OUT_COUNT_BITS _u(0x03f00000) -#define PIO_SM1_PINCTRL_OUT_COUNT_MSB _u(25) -#define PIO_SM1_PINCTRL_OUT_COUNT_LSB _u(20) -#define PIO_SM1_PINCTRL_OUT_COUNT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM1_PINCTRL_IN_BASE -// Description : The pin which is mapped to the least-significant bit of a state -// machine's IN data bus. Higher-numbered pins are mapped to -// consecutively more-significant data bits, with a modulo of 32 -// applied to pin number. -#define PIO_SM1_PINCTRL_IN_BASE_RESET _u(0x00) -#define PIO_SM1_PINCTRL_IN_BASE_BITS _u(0x000f8000) -#define PIO_SM1_PINCTRL_IN_BASE_MSB _u(19) -#define PIO_SM1_PINCTRL_IN_BASE_LSB _u(15) -#define PIO_SM1_PINCTRL_IN_BASE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM1_PINCTRL_SIDESET_BASE -// Description : The lowest-numbered pin that will be affected by a side-set -// operation. The MSBs of an instruction's side-set/delay field -// (up to 5, determined by SIDESET_COUNT) are used for side-set -// data, with the remaining LSBs used for delay. The least- -// significant bit of the side-set portion is the bit written to -// this pin, with more-significant bits written to higher-numbered -// pins. -#define PIO_SM1_PINCTRL_SIDESET_BASE_RESET _u(0x00) -#define PIO_SM1_PINCTRL_SIDESET_BASE_BITS _u(0x00007c00) -#define PIO_SM1_PINCTRL_SIDESET_BASE_MSB _u(14) -#define PIO_SM1_PINCTRL_SIDESET_BASE_LSB _u(10) -#define PIO_SM1_PINCTRL_SIDESET_BASE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM1_PINCTRL_SET_BASE -// Description : The lowest-numbered pin that will be affected by a SET PINS or -// SET PINDIRS instruction. The data written to this pin is the -// least-significant bit of the SET data. -#define PIO_SM1_PINCTRL_SET_BASE_RESET _u(0x00) -#define PIO_SM1_PINCTRL_SET_BASE_BITS _u(0x000003e0) -#define PIO_SM1_PINCTRL_SET_BASE_MSB _u(9) -#define PIO_SM1_PINCTRL_SET_BASE_LSB _u(5) -#define PIO_SM1_PINCTRL_SET_BASE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM1_PINCTRL_OUT_BASE -// Description : The lowest-numbered pin that will be affected by an OUT PINS, -// OUT PINDIRS or MOV PINS instruction. The data written to this -// pin will always be the least-significant bit of the OUT or MOV -// data. -#define PIO_SM1_PINCTRL_OUT_BASE_RESET _u(0x00) -#define PIO_SM1_PINCTRL_OUT_BASE_BITS _u(0x0000001f) -#define PIO_SM1_PINCTRL_OUT_BASE_MSB _u(4) -#define PIO_SM1_PINCTRL_OUT_BASE_LSB _u(0) -#define PIO_SM1_PINCTRL_OUT_BASE_ACCESS "RW" -// ============================================================================= -// Register : PIO_SM2_CLKDIV -// Description : Clock divisor register for state machine 2 -// Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) -#define PIO_SM2_CLKDIV_OFFSET _u(0x000000f8) -#define PIO_SM2_CLKDIV_BITS _u(0xffffff00) -#define PIO_SM2_CLKDIV_RESET _u(0x00010000) -// ----------------------------------------------------------------------------- -// Field : PIO_SM2_CLKDIV_INT -// Description : Effective frequency is sysclk/(int + frac/256). -// Value of 0 is interpreted as 65536. If INT is 0, FRAC must also -// be 0. -#define PIO_SM2_CLKDIV_INT_RESET _u(0x0001) -#define PIO_SM2_CLKDIV_INT_BITS _u(0xffff0000) -#define PIO_SM2_CLKDIV_INT_MSB _u(31) -#define PIO_SM2_CLKDIV_INT_LSB _u(16) -#define PIO_SM2_CLKDIV_INT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM2_CLKDIV_FRAC -// Description : Fractional part of clock divisor -#define PIO_SM2_CLKDIV_FRAC_RESET _u(0x00) -#define PIO_SM2_CLKDIV_FRAC_BITS _u(0x0000ff00) -#define PIO_SM2_CLKDIV_FRAC_MSB _u(15) -#define PIO_SM2_CLKDIV_FRAC_LSB _u(8) -#define PIO_SM2_CLKDIV_FRAC_ACCESS "RW" -// ============================================================================= -// Register : PIO_SM2_EXECCTRL -// Description : Execution/behavioural settings for state machine 2 -#define PIO_SM2_EXECCTRL_OFFSET _u(0x000000fc) -#define PIO_SM2_EXECCTRL_BITS _u(0xffffffff) -#define PIO_SM2_EXECCTRL_RESET _u(0x0001f000) -// ----------------------------------------------------------------------------- -// Field : PIO_SM2_EXECCTRL_EXEC_STALLED -// Description : If 1, an instruction written to SMx_INSTR is stalled, and -// latched by the state machine. Will clear to 0 once this -// instruction completes. -#define PIO_SM2_EXECCTRL_EXEC_STALLED_RESET _u(0x0) -#define PIO_SM2_EXECCTRL_EXEC_STALLED_BITS _u(0x80000000) -#define PIO_SM2_EXECCTRL_EXEC_STALLED_MSB _u(31) -#define PIO_SM2_EXECCTRL_EXEC_STALLED_LSB _u(31) -#define PIO_SM2_EXECCTRL_EXEC_STALLED_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PIO_SM2_EXECCTRL_SIDE_EN -// Description : If 1, the MSB of the Delay/Side-set instruction field is used -// as side-set enable, rather than a side-set data bit. This -// allows instructions to perform side-set optionally, rather than -// on every instruction, but the maximum possible side-set width -// is reduced from 5 to 4. Note that the value of -// PINCTRL_SIDESET_COUNT is inclusive of this enable bit. -#define PIO_SM2_EXECCTRL_SIDE_EN_RESET _u(0x0) -#define PIO_SM2_EXECCTRL_SIDE_EN_BITS _u(0x40000000) -#define PIO_SM2_EXECCTRL_SIDE_EN_MSB _u(30) -#define PIO_SM2_EXECCTRL_SIDE_EN_LSB _u(30) -#define PIO_SM2_EXECCTRL_SIDE_EN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM2_EXECCTRL_SIDE_PINDIR -// Description : If 1, side-set data is asserted to pin directions, instead of -// pin values -#define PIO_SM2_EXECCTRL_SIDE_PINDIR_RESET _u(0x0) -#define PIO_SM2_EXECCTRL_SIDE_PINDIR_BITS _u(0x20000000) -#define PIO_SM2_EXECCTRL_SIDE_PINDIR_MSB _u(29) -#define PIO_SM2_EXECCTRL_SIDE_PINDIR_LSB _u(29) -#define PIO_SM2_EXECCTRL_SIDE_PINDIR_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM2_EXECCTRL_JMP_PIN -// Description : The GPIO number to use as condition for JMP PIN. Unaffected by -// input mapping. -#define PIO_SM2_EXECCTRL_JMP_PIN_RESET _u(0x00) -#define PIO_SM2_EXECCTRL_JMP_PIN_BITS _u(0x1f000000) -#define PIO_SM2_EXECCTRL_JMP_PIN_MSB _u(28) -#define PIO_SM2_EXECCTRL_JMP_PIN_LSB _u(24) -#define PIO_SM2_EXECCTRL_JMP_PIN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM2_EXECCTRL_OUT_EN_SEL -// Description : Which data bit to use for inline OUT enable -#define PIO_SM2_EXECCTRL_OUT_EN_SEL_RESET _u(0x00) -#define PIO_SM2_EXECCTRL_OUT_EN_SEL_BITS _u(0x00f80000) -#define PIO_SM2_EXECCTRL_OUT_EN_SEL_MSB _u(23) -#define PIO_SM2_EXECCTRL_OUT_EN_SEL_LSB _u(19) -#define PIO_SM2_EXECCTRL_OUT_EN_SEL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM2_EXECCTRL_INLINE_OUT_EN -// Description : If 1, use a bit of OUT data as an auxiliary write enable -// When used in conjunction with OUT_STICKY, writes with an enable -// of 0 will -// deassert the latest pin write. This can create useful -// masking/override behaviour -// due to the priority ordering of state machine pin writes (SM0 < -// SM1 < ...) -#define PIO_SM2_EXECCTRL_INLINE_OUT_EN_RESET _u(0x0) -#define PIO_SM2_EXECCTRL_INLINE_OUT_EN_BITS _u(0x00040000) -#define PIO_SM2_EXECCTRL_INLINE_OUT_EN_MSB _u(18) -#define PIO_SM2_EXECCTRL_INLINE_OUT_EN_LSB _u(18) -#define PIO_SM2_EXECCTRL_INLINE_OUT_EN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM2_EXECCTRL_OUT_STICKY -// Description : Continuously assert the most recent OUT/SET to the pins -#define PIO_SM2_EXECCTRL_OUT_STICKY_RESET _u(0x0) -#define PIO_SM2_EXECCTRL_OUT_STICKY_BITS _u(0x00020000) -#define PIO_SM2_EXECCTRL_OUT_STICKY_MSB _u(17) -#define PIO_SM2_EXECCTRL_OUT_STICKY_LSB _u(17) -#define PIO_SM2_EXECCTRL_OUT_STICKY_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM2_EXECCTRL_WRAP_TOP -// Description : After reaching this address, execution is wrapped to -// wrap_bottom. -// If the instruction is a jump, and the jump condition is true, -// the jump takes priority. -#define PIO_SM2_EXECCTRL_WRAP_TOP_RESET _u(0x1f) -#define PIO_SM2_EXECCTRL_WRAP_TOP_BITS _u(0x0001f000) -#define PIO_SM2_EXECCTRL_WRAP_TOP_MSB _u(16) -#define PIO_SM2_EXECCTRL_WRAP_TOP_LSB _u(12) -#define PIO_SM2_EXECCTRL_WRAP_TOP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM2_EXECCTRL_WRAP_BOTTOM -// Description : After reaching wrap_top, execution is wrapped to this address. -#define PIO_SM2_EXECCTRL_WRAP_BOTTOM_RESET _u(0x00) -#define PIO_SM2_EXECCTRL_WRAP_BOTTOM_BITS _u(0x00000f80) -#define PIO_SM2_EXECCTRL_WRAP_BOTTOM_MSB _u(11) -#define PIO_SM2_EXECCTRL_WRAP_BOTTOM_LSB _u(7) -#define PIO_SM2_EXECCTRL_WRAP_BOTTOM_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM2_EXECCTRL_STATUS_SEL -// Description : Comparison used for the MOV x, STATUS instruction. -// 0x0 -> All-ones if TX FIFO level < N, otherwise all-zeroes -// 0x1 -> All-ones if RX FIFO level < N, otherwise all-zeroes -// 0x2 -> All-ones if the indexed IRQ flag is raised, otherwise all-zeroes -#define PIO_SM2_EXECCTRL_STATUS_SEL_RESET _u(0x0) -#define PIO_SM2_EXECCTRL_STATUS_SEL_BITS _u(0x00000060) -#define PIO_SM2_EXECCTRL_STATUS_SEL_MSB _u(6) -#define PIO_SM2_EXECCTRL_STATUS_SEL_LSB _u(5) -#define PIO_SM2_EXECCTRL_STATUS_SEL_ACCESS "RW" -#define PIO_SM2_EXECCTRL_STATUS_SEL_VALUE_TXLEVEL _u(0x0) -#define PIO_SM2_EXECCTRL_STATUS_SEL_VALUE_RXLEVEL _u(0x1) -#define PIO_SM2_EXECCTRL_STATUS_SEL_VALUE_IRQ _u(0x2) -// ----------------------------------------------------------------------------- -// Field : PIO_SM2_EXECCTRL_STATUS_N -// Description : Comparison level or IRQ index for the MOV x, STATUS -// instruction. -// -// If STATUS_SEL is TXLEVEL or RXLEVEL, then values of STATUS_N -// greater than the current FIFO depth are reserved, and have -// undefined behaviour. -// 0x00 -> Index 0-7 of an IRQ flag in this PIO block -// 0x08 -> Index 0-7 of an IRQ flag in the next lower-numbered PIO block -// 0x10 -> Index 0-7 of an IRQ flag in the next higher-numbered PIO block -#define PIO_SM2_EXECCTRL_STATUS_N_RESET _u(0x00) -#define PIO_SM2_EXECCTRL_STATUS_N_BITS _u(0x0000001f) -#define PIO_SM2_EXECCTRL_STATUS_N_MSB _u(4) -#define PIO_SM2_EXECCTRL_STATUS_N_LSB _u(0) -#define PIO_SM2_EXECCTRL_STATUS_N_ACCESS "RW" -#define PIO_SM2_EXECCTRL_STATUS_N_VALUE_IRQ _u(0x00) -#define PIO_SM2_EXECCTRL_STATUS_N_VALUE_IRQ_PREVPIO _u(0x08) -#define PIO_SM2_EXECCTRL_STATUS_N_VALUE_IRQ_NEXTPIO _u(0x10) -// ============================================================================= -// Register : PIO_SM2_SHIFTCTRL -// Description : Control behaviour of the input/output shift registers for state -// machine 2 -#define PIO_SM2_SHIFTCTRL_OFFSET _u(0x00000100) -#define PIO_SM2_SHIFTCTRL_BITS _u(0xffffc01f) -#define PIO_SM2_SHIFTCTRL_RESET _u(0x000c0000) -// ----------------------------------------------------------------------------- -// Field : PIO_SM2_SHIFTCTRL_FJOIN_RX -// Description : When 1, RX FIFO steals the TX FIFO's storage, and becomes twice -// as deep. -// TX FIFO is disabled as a result (always reads as both full and -// empty). -// FIFOs are flushed when this bit is changed. -#define PIO_SM2_SHIFTCTRL_FJOIN_RX_RESET _u(0x0) -#define PIO_SM2_SHIFTCTRL_FJOIN_RX_BITS _u(0x80000000) -#define PIO_SM2_SHIFTCTRL_FJOIN_RX_MSB _u(31) -#define PIO_SM2_SHIFTCTRL_FJOIN_RX_LSB _u(31) -#define PIO_SM2_SHIFTCTRL_FJOIN_RX_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM2_SHIFTCTRL_FJOIN_TX -// Description : When 1, TX FIFO steals the RX FIFO's storage, and becomes twice -// as deep. -// RX FIFO is disabled as a result (always reads as both full and -// empty). -// FIFOs are flushed when this bit is changed. -#define PIO_SM2_SHIFTCTRL_FJOIN_TX_RESET _u(0x0) -#define PIO_SM2_SHIFTCTRL_FJOIN_TX_BITS _u(0x40000000) -#define PIO_SM2_SHIFTCTRL_FJOIN_TX_MSB _u(30) -#define PIO_SM2_SHIFTCTRL_FJOIN_TX_LSB _u(30) -#define PIO_SM2_SHIFTCTRL_FJOIN_TX_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM2_SHIFTCTRL_PULL_THRESH -// Description : Number of bits shifted out of OSR before autopull, or -// conditional pull (PULL IFEMPTY), will take place. -// Write 0 for value of 32. -#define PIO_SM2_SHIFTCTRL_PULL_THRESH_RESET _u(0x00) -#define PIO_SM2_SHIFTCTRL_PULL_THRESH_BITS _u(0x3e000000) -#define PIO_SM2_SHIFTCTRL_PULL_THRESH_MSB _u(29) -#define PIO_SM2_SHIFTCTRL_PULL_THRESH_LSB _u(25) -#define PIO_SM2_SHIFTCTRL_PULL_THRESH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM2_SHIFTCTRL_PUSH_THRESH -// Description : Number of bits shifted into ISR before autopush, or conditional -// push (PUSH IFFULL), will take place. -// Write 0 for value of 32. -#define PIO_SM2_SHIFTCTRL_PUSH_THRESH_RESET _u(0x00) -#define PIO_SM2_SHIFTCTRL_PUSH_THRESH_BITS _u(0x01f00000) -#define PIO_SM2_SHIFTCTRL_PUSH_THRESH_MSB _u(24) -#define PIO_SM2_SHIFTCTRL_PUSH_THRESH_LSB _u(20) -#define PIO_SM2_SHIFTCTRL_PUSH_THRESH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM2_SHIFTCTRL_OUT_SHIFTDIR -// Description : 1 = shift out of output shift register to right. 0 = to left. -#define PIO_SM2_SHIFTCTRL_OUT_SHIFTDIR_RESET _u(0x1) -#define PIO_SM2_SHIFTCTRL_OUT_SHIFTDIR_BITS _u(0x00080000) -#define PIO_SM2_SHIFTCTRL_OUT_SHIFTDIR_MSB _u(19) -#define PIO_SM2_SHIFTCTRL_OUT_SHIFTDIR_LSB _u(19) -#define PIO_SM2_SHIFTCTRL_OUT_SHIFTDIR_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM2_SHIFTCTRL_IN_SHIFTDIR -// Description : 1 = shift input shift register to right (data enters from -// left). 0 = to left. -#define PIO_SM2_SHIFTCTRL_IN_SHIFTDIR_RESET _u(0x1) -#define PIO_SM2_SHIFTCTRL_IN_SHIFTDIR_BITS _u(0x00040000) -#define PIO_SM2_SHIFTCTRL_IN_SHIFTDIR_MSB _u(18) -#define PIO_SM2_SHIFTCTRL_IN_SHIFTDIR_LSB _u(18) -#define PIO_SM2_SHIFTCTRL_IN_SHIFTDIR_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM2_SHIFTCTRL_AUTOPULL -// Description : Pull automatically when the output shift register is emptied, -// i.e. on or following an OUT instruction which causes the output -// shift counter to reach or exceed PULL_THRESH. -#define PIO_SM2_SHIFTCTRL_AUTOPULL_RESET _u(0x0) -#define PIO_SM2_SHIFTCTRL_AUTOPULL_BITS _u(0x00020000) -#define PIO_SM2_SHIFTCTRL_AUTOPULL_MSB _u(17) -#define PIO_SM2_SHIFTCTRL_AUTOPULL_LSB _u(17) -#define PIO_SM2_SHIFTCTRL_AUTOPULL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM2_SHIFTCTRL_AUTOPUSH -// Description : Push automatically when the input shift register is filled, -// i.e. on an IN instruction which causes the input shift counter -// to reach or exceed PUSH_THRESH. -#define PIO_SM2_SHIFTCTRL_AUTOPUSH_RESET _u(0x0) -#define PIO_SM2_SHIFTCTRL_AUTOPUSH_BITS _u(0x00010000) -#define PIO_SM2_SHIFTCTRL_AUTOPUSH_MSB _u(16) -#define PIO_SM2_SHIFTCTRL_AUTOPUSH_LSB _u(16) -#define PIO_SM2_SHIFTCTRL_AUTOPUSH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM2_SHIFTCTRL_FJOIN_RX_PUT -// Description : If 1, disable this state machine's RX FIFO, make its storage -// available for random write access by the state machine (using -// the `put` instruction) and, unless FJOIN_RX_GET is also set, -// random read access by the processor (through the RXFx_PUTGETy -// registers). -// -// If FJOIN_RX_PUT and FJOIN_RX_GET are both set, then the RX -// FIFO's registers can be randomly read/written by the state -// machine, but are completely inaccessible to the processor. -// -// Setting this bit will clear the FJOIN_TX and FJOIN_RX bits. -#define PIO_SM2_SHIFTCTRL_FJOIN_RX_PUT_RESET _u(0x0) -#define PIO_SM2_SHIFTCTRL_FJOIN_RX_PUT_BITS _u(0x00008000) -#define PIO_SM2_SHIFTCTRL_FJOIN_RX_PUT_MSB _u(15) -#define PIO_SM2_SHIFTCTRL_FJOIN_RX_PUT_LSB _u(15) -#define PIO_SM2_SHIFTCTRL_FJOIN_RX_PUT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM2_SHIFTCTRL_FJOIN_RX_GET -// Description : If 1, disable this state machine's RX FIFO, make its storage -// available for random read access by the state machine (using -// the `get` instruction) and, unless FJOIN_RX_PUT is also set, -// random write access by the processor (through the RXFx_PUTGETy -// registers). -// -// If FJOIN_RX_PUT and FJOIN_RX_GET are both set, then the RX -// FIFO's registers can be randomly read/written by the state -// machine, but are completely inaccessible to the processor. -// -// Setting this bit will clear the FJOIN_TX and FJOIN_RX bits. -#define PIO_SM2_SHIFTCTRL_FJOIN_RX_GET_RESET _u(0x0) -#define PIO_SM2_SHIFTCTRL_FJOIN_RX_GET_BITS _u(0x00004000) -#define PIO_SM2_SHIFTCTRL_FJOIN_RX_GET_MSB _u(14) -#define PIO_SM2_SHIFTCTRL_FJOIN_RX_GET_LSB _u(14) -#define PIO_SM2_SHIFTCTRL_FJOIN_RX_GET_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM2_SHIFTCTRL_IN_COUNT -// Description : Set the number of pins which are not masked to 0 when read by -// an IN PINS, WAIT PIN or MOV x, PINS instruction. -// -// For example, an IN_COUNT of 5 means that the 5 LSBs of the IN -// pin group are visible (bits 4:0), but the remaining 27 MSBs are -// masked to 0. A count of 32 is encoded with a field value of 0, -// so the default behaviour is to not perform any masking. -// -// Note this masking is applied in addition to the masking usually -// performed by the IN instruction. This is mainly useful for the -// MOV x, PINS instruction, which otherwise has no way of masking -// pins. -#define PIO_SM2_SHIFTCTRL_IN_COUNT_RESET _u(0x00) -#define PIO_SM2_SHIFTCTRL_IN_COUNT_BITS _u(0x0000001f) -#define PIO_SM2_SHIFTCTRL_IN_COUNT_MSB _u(4) -#define PIO_SM2_SHIFTCTRL_IN_COUNT_LSB _u(0) -#define PIO_SM2_SHIFTCTRL_IN_COUNT_ACCESS "RW" -// ============================================================================= -// Register : PIO_SM2_ADDR -// Description : Current instruction address of state machine 2 -#define PIO_SM2_ADDR_OFFSET _u(0x00000104) -#define PIO_SM2_ADDR_BITS _u(0x0000001f) -#define PIO_SM2_ADDR_RESET _u(0x00000000) -#define PIO_SM2_ADDR_MSB _u(4) -#define PIO_SM2_ADDR_LSB _u(0) -#define PIO_SM2_ADDR_ACCESS "RO" -// ============================================================================= -// Register : PIO_SM2_INSTR -// Description : Read to see the instruction currently addressed by state -// machine 2's program counter -// Write to execute an instruction immediately (including jumps) -// and then resume execution. -#define PIO_SM2_INSTR_OFFSET _u(0x00000108) -#define PIO_SM2_INSTR_BITS _u(0x0000ffff) -#define PIO_SM2_INSTR_RESET "-" -#define PIO_SM2_INSTR_MSB _u(15) -#define PIO_SM2_INSTR_LSB _u(0) -#define PIO_SM2_INSTR_ACCESS "RW" -// ============================================================================= -// Register : PIO_SM2_PINCTRL -// Description : State machine pin control -#define PIO_SM2_PINCTRL_OFFSET _u(0x0000010c) -#define PIO_SM2_PINCTRL_BITS _u(0xffffffff) -#define PIO_SM2_PINCTRL_RESET _u(0x14000000) -// ----------------------------------------------------------------------------- -// Field : PIO_SM2_PINCTRL_SIDESET_COUNT -// Description : The number of MSBs of the Delay/Side-set instruction field -// which are used for side-set. Inclusive of the enable bit, if -// present. Minimum of 0 (all delay bits, no side-set) and maximum -// of 5 (all side-set, no delay). -#define PIO_SM2_PINCTRL_SIDESET_COUNT_RESET _u(0x0) -#define PIO_SM2_PINCTRL_SIDESET_COUNT_BITS _u(0xe0000000) -#define PIO_SM2_PINCTRL_SIDESET_COUNT_MSB _u(31) -#define PIO_SM2_PINCTRL_SIDESET_COUNT_LSB _u(29) -#define PIO_SM2_PINCTRL_SIDESET_COUNT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM2_PINCTRL_SET_COUNT -// Description : The number of pins asserted by a SET. In the range 0 to 5 -// inclusive. -#define PIO_SM2_PINCTRL_SET_COUNT_RESET _u(0x5) -#define PIO_SM2_PINCTRL_SET_COUNT_BITS _u(0x1c000000) -#define PIO_SM2_PINCTRL_SET_COUNT_MSB _u(28) -#define PIO_SM2_PINCTRL_SET_COUNT_LSB _u(26) -#define PIO_SM2_PINCTRL_SET_COUNT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM2_PINCTRL_OUT_COUNT -// Description : The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV -// PINS instruction. In the range 0 to 32 inclusive. -#define PIO_SM2_PINCTRL_OUT_COUNT_RESET _u(0x00) -#define PIO_SM2_PINCTRL_OUT_COUNT_BITS _u(0x03f00000) -#define PIO_SM2_PINCTRL_OUT_COUNT_MSB _u(25) -#define PIO_SM2_PINCTRL_OUT_COUNT_LSB _u(20) -#define PIO_SM2_PINCTRL_OUT_COUNT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM2_PINCTRL_IN_BASE -// Description : The pin which is mapped to the least-significant bit of a state -// machine's IN data bus. Higher-numbered pins are mapped to -// consecutively more-significant data bits, with a modulo of 32 -// applied to pin number. -#define PIO_SM2_PINCTRL_IN_BASE_RESET _u(0x00) -#define PIO_SM2_PINCTRL_IN_BASE_BITS _u(0x000f8000) -#define PIO_SM2_PINCTRL_IN_BASE_MSB _u(19) -#define PIO_SM2_PINCTRL_IN_BASE_LSB _u(15) -#define PIO_SM2_PINCTRL_IN_BASE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM2_PINCTRL_SIDESET_BASE -// Description : The lowest-numbered pin that will be affected by a side-set -// operation. The MSBs of an instruction's side-set/delay field -// (up to 5, determined by SIDESET_COUNT) are used for side-set -// data, with the remaining LSBs used for delay. The least- -// significant bit of the side-set portion is the bit written to -// this pin, with more-significant bits written to higher-numbered -// pins. -#define PIO_SM2_PINCTRL_SIDESET_BASE_RESET _u(0x00) -#define PIO_SM2_PINCTRL_SIDESET_BASE_BITS _u(0x00007c00) -#define PIO_SM2_PINCTRL_SIDESET_BASE_MSB _u(14) -#define PIO_SM2_PINCTRL_SIDESET_BASE_LSB _u(10) -#define PIO_SM2_PINCTRL_SIDESET_BASE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM2_PINCTRL_SET_BASE -// Description : The lowest-numbered pin that will be affected by a SET PINS or -// SET PINDIRS instruction. The data written to this pin is the -// least-significant bit of the SET data. -#define PIO_SM2_PINCTRL_SET_BASE_RESET _u(0x00) -#define PIO_SM2_PINCTRL_SET_BASE_BITS _u(0x000003e0) -#define PIO_SM2_PINCTRL_SET_BASE_MSB _u(9) -#define PIO_SM2_PINCTRL_SET_BASE_LSB _u(5) -#define PIO_SM2_PINCTRL_SET_BASE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM2_PINCTRL_OUT_BASE -// Description : The lowest-numbered pin that will be affected by an OUT PINS, -// OUT PINDIRS or MOV PINS instruction. The data written to this -// pin will always be the least-significant bit of the OUT or MOV -// data. -#define PIO_SM2_PINCTRL_OUT_BASE_RESET _u(0x00) -#define PIO_SM2_PINCTRL_OUT_BASE_BITS _u(0x0000001f) -#define PIO_SM2_PINCTRL_OUT_BASE_MSB _u(4) -#define PIO_SM2_PINCTRL_OUT_BASE_LSB _u(0) -#define PIO_SM2_PINCTRL_OUT_BASE_ACCESS "RW" -// ============================================================================= -// Register : PIO_SM3_CLKDIV -// Description : Clock divisor register for state machine 3 -// Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) -#define PIO_SM3_CLKDIV_OFFSET _u(0x00000110) -#define PIO_SM3_CLKDIV_BITS _u(0xffffff00) -#define PIO_SM3_CLKDIV_RESET _u(0x00010000) -// ----------------------------------------------------------------------------- -// Field : PIO_SM3_CLKDIV_INT -// Description : Effective frequency is sysclk/(int + frac/256). -// Value of 0 is interpreted as 65536. If INT is 0, FRAC must also -// be 0. -#define PIO_SM3_CLKDIV_INT_RESET _u(0x0001) -#define PIO_SM3_CLKDIV_INT_BITS _u(0xffff0000) -#define PIO_SM3_CLKDIV_INT_MSB _u(31) -#define PIO_SM3_CLKDIV_INT_LSB _u(16) -#define PIO_SM3_CLKDIV_INT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM3_CLKDIV_FRAC -// Description : Fractional part of clock divisor -#define PIO_SM3_CLKDIV_FRAC_RESET _u(0x00) -#define PIO_SM3_CLKDIV_FRAC_BITS _u(0x0000ff00) -#define PIO_SM3_CLKDIV_FRAC_MSB _u(15) -#define PIO_SM3_CLKDIV_FRAC_LSB _u(8) -#define PIO_SM3_CLKDIV_FRAC_ACCESS "RW" -// ============================================================================= -// Register : PIO_SM3_EXECCTRL -// Description : Execution/behavioural settings for state machine 3 -#define PIO_SM3_EXECCTRL_OFFSET _u(0x00000114) -#define PIO_SM3_EXECCTRL_BITS _u(0xffffffff) -#define PIO_SM3_EXECCTRL_RESET _u(0x0001f000) -// ----------------------------------------------------------------------------- -// Field : PIO_SM3_EXECCTRL_EXEC_STALLED -// Description : If 1, an instruction written to SMx_INSTR is stalled, and -// latched by the state machine. Will clear to 0 once this -// instruction completes. -#define PIO_SM3_EXECCTRL_EXEC_STALLED_RESET _u(0x0) -#define PIO_SM3_EXECCTRL_EXEC_STALLED_BITS _u(0x80000000) -#define PIO_SM3_EXECCTRL_EXEC_STALLED_MSB _u(31) -#define PIO_SM3_EXECCTRL_EXEC_STALLED_LSB _u(31) -#define PIO_SM3_EXECCTRL_EXEC_STALLED_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PIO_SM3_EXECCTRL_SIDE_EN -// Description : If 1, the MSB of the Delay/Side-set instruction field is used -// as side-set enable, rather than a side-set data bit. This -// allows instructions to perform side-set optionally, rather than -// on every instruction, but the maximum possible side-set width -// is reduced from 5 to 4. Note that the value of -// PINCTRL_SIDESET_COUNT is inclusive of this enable bit. -#define PIO_SM3_EXECCTRL_SIDE_EN_RESET _u(0x0) -#define PIO_SM3_EXECCTRL_SIDE_EN_BITS _u(0x40000000) -#define PIO_SM3_EXECCTRL_SIDE_EN_MSB _u(30) -#define PIO_SM3_EXECCTRL_SIDE_EN_LSB _u(30) -#define PIO_SM3_EXECCTRL_SIDE_EN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM3_EXECCTRL_SIDE_PINDIR -// Description : If 1, side-set data is asserted to pin directions, instead of -// pin values -#define PIO_SM3_EXECCTRL_SIDE_PINDIR_RESET _u(0x0) -#define PIO_SM3_EXECCTRL_SIDE_PINDIR_BITS _u(0x20000000) -#define PIO_SM3_EXECCTRL_SIDE_PINDIR_MSB _u(29) -#define PIO_SM3_EXECCTRL_SIDE_PINDIR_LSB _u(29) -#define PIO_SM3_EXECCTRL_SIDE_PINDIR_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM3_EXECCTRL_JMP_PIN -// Description : The GPIO number to use as condition for JMP PIN. Unaffected by -// input mapping. -#define PIO_SM3_EXECCTRL_JMP_PIN_RESET _u(0x00) -#define PIO_SM3_EXECCTRL_JMP_PIN_BITS _u(0x1f000000) -#define PIO_SM3_EXECCTRL_JMP_PIN_MSB _u(28) -#define PIO_SM3_EXECCTRL_JMP_PIN_LSB _u(24) -#define PIO_SM3_EXECCTRL_JMP_PIN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM3_EXECCTRL_OUT_EN_SEL -// Description : Which data bit to use for inline OUT enable -#define PIO_SM3_EXECCTRL_OUT_EN_SEL_RESET _u(0x00) -#define PIO_SM3_EXECCTRL_OUT_EN_SEL_BITS _u(0x00f80000) -#define PIO_SM3_EXECCTRL_OUT_EN_SEL_MSB _u(23) -#define PIO_SM3_EXECCTRL_OUT_EN_SEL_LSB _u(19) -#define PIO_SM3_EXECCTRL_OUT_EN_SEL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM3_EXECCTRL_INLINE_OUT_EN -// Description : If 1, use a bit of OUT data as an auxiliary write enable -// When used in conjunction with OUT_STICKY, writes with an enable -// of 0 will -// deassert the latest pin write. This can create useful -// masking/override behaviour -// due to the priority ordering of state machine pin writes (SM0 < -// SM1 < ...) -#define PIO_SM3_EXECCTRL_INLINE_OUT_EN_RESET _u(0x0) -#define PIO_SM3_EXECCTRL_INLINE_OUT_EN_BITS _u(0x00040000) -#define PIO_SM3_EXECCTRL_INLINE_OUT_EN_MSB _u(18) -#define PIO_SM3_EXECCTRL_INLINE_OUT_EN_LSB _u(18) -#define PIO_SM3_EXECCTRL_INLINE_OUT_EN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM3_EXECCTRL_OUT_STICKY -// Description : Continuously assert the most recent OUT/SET to the pins -#define PIO_SM3_EXECCTRL_OUT_STICKY_RESET _u(0x0) -#define PIO_SM3_EXECCTRL_OUT_STICKY_BITS _u(0x00020000) -#define PIO_SM3_EXECCTRL_OUT_STICKY_MSB _u(17) -#define PIO_SM3_EXECCTRL_OUT_STICKY_LSB _u(17) -#define PIO_SM3_EXECCTRL_OUT_STICKY_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM3_EXECCTRL_WRAP_TOP -// Description : After reaching this address, execution is wrapped to -// wrap_bottom. -// If the instruction is a jump, and the jump condition is true, -// the jump takes priority. -#define PIO_SM3_EXECCTRL_WRAP_TOP_RESET _u(0x1f) -#define PIO_SM3_EXECCTRL_WRAP_TOP_BITS _u(0x0001f000) -#define PIO_SM3_EXECCTRL_WRAP_TOP_MSB _u(16) -#define PIO_SM3_EXECCTRL_WRAP_TOP_LSB _u(12) -#define PIO_SM3_EXECCTRL_WRAP_TOP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM3_EXECCTRL_WRAP_BOTTOM -// Description : After reaching wrap_top, execution is wrapped to this address. -#define PIO_SM3_EXECCTRL_WRAP_BOTTOM_RESET _u(0x00) -#define PIO_SM3_EXECCTRL_WRAP_BOTTOM_BITS _u(0x00000f80) -#define PIO_SM3_EXECCTRL_WRAP_BOTTOM_MSB _u(11) -#define PIO_SM3_EXECCTRL_WRAP_BOTTOM_LSB _u(7) -#define PIO_SM3_EXECCTRL_WRAP_BOTTOM_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM3_EXECCTRL_STATUS_SEL -// Description : Comparison used for the MOV x, STATUS instruction. -// 0x0 -> All-ones if TX FIFO level < N, otherwise all-zeroes -// 0x1 -> All-ones if RX FIFO level < N, otherwise all-zeroes -// 0x2 -> All-ones if the indexed IRQ flag is raised, otherwise all-zeroes -#define PIO_SM3_EXECCTRL_STATUS_SEL_RESET _u(0x0) -#define PIO_SM3_EXECCTRL_STATUS_SEL_BITS _u(0x00000060) -#define PIO_SM3_EXECCTRL_STATUS_SEL_MSB _u(6) -#define PIO_SM3_EXECCTRL_STATUS_SEL_LSB _u(5) -#define PIO_SM3_EXECCTRL_STATUS_SEL_ACCESS "RW" -#define PIO_SM3_EXECCTRL_STATUS_SEL_VALUE_TXLEVEL _u(0x0) -#define PIO_SM3_EXECCTRL_STATUS_SEL_VALUE_RXLEVEL _u(0x1) -#define PIO_SM3_EXECCTRL_STATUS_SEL_VALUE_IRQ _u(0x2) -// ----------------------------------------------------------------------------- -// Field : PIO_SM3_EXECCTRL_STATUS_N -// Description : Comparison level or IRQ index for the MOV x, STATUS -// instruction. -// -// If STATUS_SEL is TXLEVEL or RXLEVEL, then values of STATUS_N -// greater than the current FIFO depth are reserved, and have -// undefined behaviour. -// 0x00 -> Index 0-7 of an IRQ flag in this PIO block -// 0x08 -> Index 0-7 of an IRQ flag in the next lower-numbered PIO block -// 0x10 -> Index 0-7 of an IRQ flag in the next higher-numbered PIO block -#define PIO_SM3_EXECCTRL_STATUS_N_RESET _u(0x00) -#define PIO_SM3_EXECCTRL_STATUS_N_BITS _u(0x0000001f) -#define PIO_SM3_EXECCTRL_STATUS_N_MSB _u(4) -#define PIO_SM3_EXECCTRL_STATUS_N_LSB _u(0) -#define PIO_SM3_EXECCTRL_STATUS_N_ACCESS "RW" -#define PIO_SM3_EXECCTRL_STATUS_N_VALUE_IRQ _u(0x00) -#define PIO_SM3_EXECCTRL_STATUS_N_VALUE_IRQ_PREVPIO _u(0x08) -#define PIO_SM3_EXECCTRL_STATUS_N_VALUE_IRQ_NEXTPIO _u(0x10) -// ============================================================================= -// Register : PIO_SM3_SHIFTCTRL -// Description : Control behaviour of the input/output shift registers for state -// machine 3 -#define PIO_SM3_SHIFTCTRL_OFFSET _u(0x00000118) -#define PIO_SM3_SHIFTCTRL_BITS _u(0xffffc01f) -#define PIO_SM3_SHIFTCTRL_RESET _u(0x000c0000) -// ----------------------------------------------------------------------------- -// Field : PIO_SM3_SHIFTCTRL_FJOIN_RX -// Description : When 1, RX FIFO steals the TX FIFO's storage, and becomes twice -// as deep. -// TX FIFO is disabled as a result (always reads as both full and -// empty). -// FIFOs are flushed when this bit is changed. -#define PIO_SM3_SHIFTCTRL_FJOIN_RX_RESET _u(0x0) -#define PIO_SM3_SHIFTCTRL_FJOIN_RX_BITS _u(0x80000000) -#define PIO_SM3_SHIFTCTRL_FJOIN_RX_MSB _u(31) -#define PIO_SM3_SHIFTCTRL_FJOIN_RX_LSB _u(31) -#define PIO_SM3_SHIFTCTRL_FJOIN_RX_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM3_SHIFTCTRL_FJOIN_TX -// Description : When 1, TX FIFO steals the RX FIFO's storage, and becomes twice -// as deep. -// RX FIFO is disabled as a result (always reads as both full and -// empty). -// FIFOs are flushed when this bit is changed. -#define PIO_SM3_SHIFTCTRL_FJOIN_TX_RESET _u(0x0) -#define PIO_SM3_SHIFTCTRL_FJOIN_TX_BITS _u(0x40000000) -#define PIO_SM3_SHIFTCTRL_FJOIN_TX_MSB _u(30) -#define PIO_SM3_SHIFTCTRL_FJOIN_TX_LSB _u(30) -#define PIO_SM3_SHIFTCTRL_FJOIN_TX_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM3_SHIFTCTRL_PULL_THRESH -// Description : Number of bits shifted out of OSR before autopull, or -// conditional pull (PULL IFEMPTY), will take place. -// Write 0 for value of 32. -#define PIO_SM3_SHIFTCTRL_PULL_THRESH_RESET _u(0x00) -#define PIO_SM3_SHIFTCTRL_PULL_THRESH_BITS _u(0x3e000000) -#define PIO_SM3_SHIFTCTRL_PULL_THRESH_MSB _u(29) -#define PIO_SM3_SHIFTCTRL_PULL_THRESH_LSB _u(25) -#define PIO_SM3_SHIFTCTRL_PULL_THRESH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM3_SHIFTCTRL_PUSH_THRESH -// Description : Number of bits shifted into ISR before autopush, or conditional -// push (PUSH IFFULL), will take place. -// Write 0 for value of 32. -#define PIO_SM3_SHIFTCTRL_PUSH_THRESH_RESET _u(0x00) -#define PIO_SM3_SHIFTCTRL_PUSH_THRESH_BITS _u(0x01f00000) -#define PIO_SM3_SHIFTCTRL_PUSH_THRESH_MSB _u(24) -#define PIO_SM3_SHIFTCTRL_PUSH_THRESH_LSB _u(20) -#define PIO_SM3_SHIFTCTRL_PUSH_THRESH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM3_SHIFTCTRL_OUT_SHIFTDIR -// Description : 1 = shift out of output shift register to right. 0 = to left. -#define PIO_SM3_SHIFTCTRL_OUT_SHIFTDIR_RESET _u(0x1) -#define PIO_SM3_SHIFTCTRL_OUT_SHIFTDIR_BITS _u(0x00080000) -#define PIO_SM3_SHIFTCTRL_OUT_SHIFTDIR_MSB _u(19) -#define PIO_SM3_SHIFTCTRL_OUT_SHIFTDIR_LSB _u(19) -#define PIO_SM3_SHIFTCTRL_OUT_SHIFTDIR_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM3_SHIFTCTRL_IN_SHIFTDIR -// Description : 1 = shift input shift register to right (data enters from -// left). 0 = to left. -#define PIO_SM3_SHIFTCTRL_IN_SHIFTDIR_RESET _u(0x1) -#define PIO_SM3_SHIFTCTRL_IN_SHIFTDIR_BITS _u(0x00040000) -#define PIO_SM3_SHIFTCTRL_IN_SHIFTDIR_MSB _u(18) -#define PIO_SM3_SHIFTCTRL_IN_SHIFTDIR_LSB _u(18) -#define PIO_SM3_SHIFTCTRL_IN_SHIFTDIR_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM3_SHIFTCTRL_AUTOPULL -// Description : Pull automatically when the output shift register is emptied, -// i.e. on or following an OUT instruction which causes the output -// shift counter to reach or exceed PULL_THRESH. -#define PIO_SM3_SHIFTCTRL_AUTOPULL_RESET _u(0x0) -#define PIO_SM3_SHIFTCTRL_AUTOPULL_BITS _u(0x00020000) -#define PIO_SM3_SHIFTCTRL_AUTOPULL_MSB _u(17) -#define PIO_SM3_SHIFTCTRL_AUTOPULL_LSB _u(17) -#define PIO_SM3_SHIFTCTRL_AUTOPULL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM3_SHIFTCTRL_AUTOPUSH -// Description : Push automatically when the input shift register is filled, -// i.e. on an IN instruction which causes the input shift counter -// to reach or exceed PUSH_THRESH. -#define PIO_SM3_SHIFTCTRL_AUTOPUSH_RESET _u(0x0) -#define PIO_SM3_SHIFTCTRL_AUTOPUSH_BITS _u(0x00010000) -#define PIO_SM3_SHIFTCTRL_AUTOPUSH_MSB _u(16) -#define PIO_SM3_SHIFTCTRL_AUTOPUSH_LSB _u(16) -#define PIO_SM3_SHIFTCTRL_AUTOPUSH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM3_SHIFTCTRL_FJOIN_RX_PUT -// Description : If 1, disable this state machine's RX FIFO, make its storage -// available for random write access by the state machine (using -// the `put` instruction) and, unless FJOIN_RX_GET is also set, -// random read access by the processor (through the RXFx_PUTGETy -// registers). -// -// If FJOIN_RX_PUT and FJOIN_RX_GET are both set, then the RX -// FIFO's registers can be randomly read/written by the state -// machine, but are completely inaccessible to the processor. -// -// Setting this bit will clear the FJOIN_TX and FJOIN_RX bits. -#define PIO_SM3_SHIFTCTRL_FJOIN_RX_PUT_RESET _u(0x0) -#define PIO_SM3_SHIFTCTRL_FJOIN_RX_PUT_BITS _u(0x00008000) -#define PIO_SM3_SHIFTCTRL_FJOIN_RX_PUT_MSB _u(15) -#define PIO_SM3_SHIFTCTRL_FJOIN_RX_PUT_LSB _u(15) -#define PIO_SM3_SHIFTCTRL_FJOIN_RX_PUT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM3_SHIFTCTRL_FJOIN_RX_GET -// Description : If 1, disable this state machine's RX FIFO, make its storage -// available for random read access by the state machine (using -// the `get` instruction) and, unless FJOIN_RX_PUT is also set, -// random write access by the processor (through the RXFx_PUTGETy -// registers). -// -// If FJOIN_RX_PUT and FJOIN_RX_GET are both set, then the RX -// FIFO's registers can be randomly read/written by the state -// machine, but are completely inaccessible to the processor. -// -// Setting this bit will clear the FJOIN_TX and FJOIN_RX bits. -#define PIO_SM3_SHIFTCTRL_FJOIN_RX_GET_RESET _u(0x0) -#define PIO_SM3_SHIFTCTRL_FJOIN_RX_GET_BITS _u(0x00004000) -#define PIO_SM3_SHIFTCTRL_FJOIN_RX_GET_MSB _u(14) -#define PIO_SM3_SHIFTCTRL_FJOIN_RX_GET_LSB _u(14) -#define PIO_SM3_SHIFTCTRL_FJOIN_RX_GET_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM3_SHIFTCTRL_IN_COUNT -// Description : Set the number of pins which are not masked to 0 when read by -// an IN PINS, WAIT PIN or MOV x, PINS instruction. -// -// For example, an IN_COUNT of 5 means that the 5 LSBs of the IN -// pin group are visible (bits 4:0), but the remaining 27 MSBs are -// masked to 0. A count of 32 is encoded with a field value of 0, -// so the default behaviour is to not perform any masking. -// -// Note this masking is applied in addition to the masking usually -// performed by the IN instruction. This is mainly useful for the -// MOV x, PINS instruction, which otherwise has no way of masking -// pins. -#define PIO_SM3_SHIFTCTRL_IN_COUNT_RESET _u(0x00) -#define PIO_SM3_SHIFTCTRL_IN_COUNT_BITS _u(0x0000001f) -#define PIO_SM3_SHIFTCTRL_IN_COUNT_MSB _u(4) -#define PIO_SM3_SHIFTCTRL_IN_COUNT_LSB _u(0) -#define PIO_SM3_SHIFTCTRL_IN_COUNT_ACCESS "RW" -// ============================================================================= -// Register : PIO_SM3_ADDR -// Description : Current instruction address of state machine 3 -#define PIO_SM3_ADDR_OFFSET _u(0x0000011c) -#define PIO_SM3_ADDR_BITS _u(0x0000001f) -#define PIO_SM3_ADDR_RESET _u(0x00000000) -#define PIO_SM3_ADDR_MSB _u(4) -#define PIO_SM3_ADDR_LSB _u(0) -#define PIO_SM3_ADDR_ACCESS "RO" -// ============================================================================= -// Register : PIO_SM3_INSTR -// Description : Read to see the instruction currently addressed by state -// machine 3's program counter -// Write to execute an instruction immediately (including jumps) -// and then resume execution. -#define PIO_SM3_INSTR_OFFSET _u(0x00000120) -#define PIO_SM3_INSTR_BITS _u(0x0000ffff) -#define PIO_SM3_INSTR_RESET "-" -#define PIO_SM3_INSTR_MSB _u(15) -#define PIO_SM3_INSTR_LSB _u(0) -#define PIO_SM3_INSTR_ACCESS "RW" -// ============================================================================= -// Register : PIO_SM3_PINCTRL -// Description : State machine pin control -#define PIO_SM3_PINCTRL_OFFSET _u(0x00000124) -#define PIO_SM3_PINCTRL_BITS _u(0xffffffff) -#define PIO_SM3_PINCTRL_RESET _u(0x14000000) -// ----------------------------------------------------------------------------- -// Field : PIO_SM3_PINCTRL_SIDESET_COUNT -// Description : The number of MSBs of the Delay/Side-set instruction field -// which are used for side-set. Inclusive of the enable bit, if -// present. Minimum of 0 (all delay bits, no side-set) and maximum -// of 5 (all side-set, no delay). -#define PIO_SM3_PINCTRL_SIDESET_COUNT_RESET _u(0x0) -#define PIO_SM3_PINCTRL_SIDESET_COUNT_BITS _u(0xe0000000) -#define PIO_SM3_PINCTRL_SIDESET_COUNT_MSB _u(31) -#define PIO_SM3_PINCTRL_SIDESET_COUNT_LSB _u(29) -#define PIO_SM3_PINCTRL_SIDESET_COUNT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM3_PINCTRL_SET_COUNT -// Description : The number of pins asserted by a SET. In the range 0 to 5 -// inclusive. -#define PIO_SM3_PINCTRL_SET_COUNT_RESET _u(0x5) -#define PIO_SM3_PINCTRL_SET_COUNT_BITS _u(0x1c000000) -#define PIO_SM3_PINCTRL_SET_COUNT_MSB _u(28) -#define PIO_SM3_PINCTRL_SET_COUNT_LSB _u(26) -#define PIO_SM3_PINCTRL_SET_COUNT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM3_PINCTRL_OUT_COUNT -// Description : The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV -// PINS instruction. In the range 0 to 32 inclusive. -#define PIO_SM3_PINCTRL_OUT_COUNT_RESET _u(0x00) -#define PIO_SM3_PINCTRL_OUT_COUNT_BITS _u(0x03f00000) -#define PIO_SM3_PINCTRL_OUT_COUNT_MSB _u(25) -#define PIO_SM3_PINCTRL_OUT_COUNT_LSB _u(20) -#define PIO_SM3_PINCTRL_OUT_COUNT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM3_PINCTRL_IN_BASE -// Description : The pin which is mapped to the least-significant bit of a state -// machine's IN data bus. Higher-numbered pins are mapped to -// consecutively more-significant data bits, with a modulo of 32 -// applied to pin number. -#define PIO_SM3_PINCTRL_IN_BASE_RESET _u(0x00) -#define PIO_SM3_PINCTRL_IN_BASE_BITS _u(0x000f8000) -#define PIO_SM3_PINCTRL_IN_BASE_MSB _u(19) -#define PIO_SM3_PINCTRL_IN_BASE_LSB _u(15) -#define PIO_SM3_PINCTRL_IN_BASE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM3_PINCTRL_SIDESET_BASE -// Description : The lowest-numbered pin that will be affected by a side-set -// operation. The MSBs of an instruction's side-set/delay field -// (up to 5, determined by SIDESET_COUNT) are used for side-set -// data, with the remaining LSBs used for delay. The least- -// significant bit of the side-set portion is the bit written to -// this pin, with more-significant bits written to higher-numbered -// pins. -#define PIO_SM3_PINCTRL_SIDESET_BASE_RESET _u(0x00) -#define PIO_SM3_PINCTRL_SIDESET_BASE_BITS _u(0x00007c00) -#define PIO_SM3_PINCTRL_SIDESET_BASE_MSB _u(14) -#define PIO_SM3_PINCTRL_SIDESET_BASE_LSB _u(10) -#define PIO_SM3_PINCTRL_SIDESET_BASE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM3_PINCTRL_SET_BASE -// Description : The lowest-numbered pin that will be affected by a SET PINS or -// SET PINDIRS instruction. The data written to this pin is the -// least-significant bit of the SET data. -#define PIO_SM3_PINCTRL_SET_BASE_RESET _u(0x00) -#define PIO_SM3_PINCTRL_SET_BASE_BITS _u(0x000003e0) -#define PIO_SM3_PINCTRL_SET_BASE_MSB _u(9) -#define PIO_SM3_PINCTRL_SET_BASE_LSB _u(5) -#define PIO_SM3_PINCTRL_SET_BASE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_SM3_PINCTRL_OUT_BASE -// Description : The lowest-numbered pin that will be affected by an OUT PINS, -// OUT PINDIRS or MOV PINS instruction. The data written to this -// pin will always be the least-significant bit of the OUT or MOV -// data. -#define PIO_SM3_PINCTRL_OUT_BASE_RESET _u(0x00) -#define PIO_SM3_PINCTRL_OUT_BASE_BITS _u(0x0000001f) -#define PIO_SM3_PINCTRL_OUT_BASE_MSB _u(4) -#define PIO_SM3_PINCTRL_OUT_BASE_LSB _u(0) -#define PIO_SM3_PINCTRL_OUT_BASE_ACCESS "RW" -// ============================================================================= -// Register : PIO_RXF0_PUTGET0 -// Description : Direct read/write access to entry 0 of SM0's RX FIFO, if -// SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. -#define PIO_RXF0_PUTGET0_OFFSET _u(0x00000128) -#define PIO_RXF0_PUTGET0_BITS _u(0xffffffff) -#define PIO_RXF0_PUTGET0_RESET _u(0x00000000) -#define PIO_RXF0_PUTGET0_MSB _u(31) -#define PIO_RXF0_PUTGET0_LSB _u(0) -#define PIO_RXF0_PUTGET0_ACCESS "RW" -// ============================================================================= -// Register : PIO_RXF0_PUTGET1 -// Description : Direct read/write access to entry 1 of SM0's RX FIFO, if -// SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. -#define PIO_RXF0_PUTGET1_OFFSET _u(0x0000012c) -#define PIO_RXF0_PUTGET1_BITS _u(0xffffffff) -#define PIO_RXF0_PUTGET1_RESET _u(0x00000000) -#define PIO_RXF0_PUTGET1_MSB _u(31) -#define PIO_RXF0_PUTGET1_LSB _u(0) -#define PIO_RXF0_PUTGET1_ACCESS "RW" -// ============================================================================= -// Register : PIO_RXF0_PUTGET2 -// Description : Direct read/write access to entry 2 of SM0's RX FIFO, if -// SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. -#define PIO_RXF0_PUTGET2_OFFSET _u(0x00000130) -#define PIO_RXF0_PUTGET2_BITS _u(0xffffffff) -#define PIO_RXF0_PUTGET2_RESET _u(0x00000000) -#define PIO_RXF0_PUTGET2_MSB _u(31) -#define PIO_RXF0_PUTGET2_LSB _u(0) -#define PIO_RXF0_PUTGET2_ACCESS "RW" -// ============================================================================= -// Register : PIO_RXF0_PUTGET3 -// Description : Direct read/write access to entry 3 of SM0's RX FIFO, if -// SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. -#define PIO_RXF0_PUTGET3_OFFSET _u(0x00000134) -#define PIO_RXF0_PUTGET3_BITS _u(0xffffffff) -#define PIO_RXF0_PUTGET3_RESET _u(0x00000000) -#define PIO_RXF0_PUTGET3_MSB _u(31) -#define PIO_RXF0_PUTGET3_LSB _u(0) -#define PIO_RXF0_PUTGET3_ACCESS "RW" -// ============================================================================= -// Register : PIO_RXF1_PUTGET0 -// Description : Direct read/write access to entry 0 of SM1's RX FIFO, if -// SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. -#define PIO_RXF1_PUTGET0_OFFSET _u(0x00000138) -#define PIO_RXF1_PUTGET0_BITS _u(0xffffffff) -#define PIO_RXF1_PUTGET0_RESET _u(0x00000000) -#define PIO_RXF1_PUTGET0_MSB _u(31) -#define PIO_RXF1_PUTGET0_LSB _u(0) -#define PIO_RXF1_PUTGET0_ACCESS "RW" -// ============================================================================= -// Register : PIO_RXF1_PUTGET1 -// Description : Direct read/write access to entry 1 of SM1's RX FIFO, if -// SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. -#define PIO_RXF1_PUTGET1_OFFSET _u(0x0000013c) -#define PIO_RXF1_PUTGET1_BITS _u(0xffffffff) -#define PIO_RXF1_PUTGET1_RESET _u(0x00000000) -#define PIO_RXF1_PUTGET1_MSB _u(31) -#define PIO_RXF1_PUTGET1_LSB _u(0) -#define PIO_RXF1_PUTGET1_ACCESS "RW" -// ============================================================================= -// Register : PIO_RXF1_PUTGET2 -// Description : Direct read/write access to entry 2 of SM1's RX FIFO, if -// SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. -#define PIO_RXF1_PUTGET2_OFFSET _u(0x00000140) -#define PIO_RXF1_PUTGET2_BITS _u(0xffffffff) -#define PIO_RXF1_PUTGET2_RESET _u(0x00000000) -#define PIO_RXF1_PUTGET2_MSB _u(31) -#define PIO_RXF1_PUTGET2_LSB _u(0) -#define PIO_RXF1_PUTGET2_ACCESS "RW" -// ============================================================================= -// Register : PIO_RXF1_PUTGET3 -// Description : Direct read/write access to entry 3 of SM1's RX FIFO, if -// SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. -#define PIO_RXF1_PUTGET3_OFFSET _u(0x00000144) -#define PIO_RXF1_PUTGET3_BITS _u(0xffffffff) -#define PIO_RXF1_PUTGET3_RESET _u(0x00000000) -#define PIO_RXF1_PUTGET3_MSB _u(31) -#define PIO_RXF1_PUTGET3_LSB _u(0) -#define PIO_RXF1_PUTGET3_ACCESS "RW" -// ============================================================================= -// Register : PIO_RXF2_PUTGET0 -// Description : Direct read/write access to entry 0 of SM2's RX FIFO, if -// SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. -#define PIO_RXF2_PUTGET0_OFFSET _u(0x00000148) -#define PIO_RXF2_PUTGET0_BITS _u(0xffffffff) -#define PIO_RXF2_PUTGET0_RESET _u(0x00000000) -#define PIO_RXF2_PUTGET0_MSB _u(31) -#define PIO_RXF2_PUTGET0_LSB _u(0) -#define PIO_RXF2_PUTGET0_ACCESS "RW" -// ============================================================================= -// Register : PIO_RXF2_PUTGET1 -// Description : Direct read/write access to entry 1 of SM2's RX FIFO, if -// SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. -#define PIO_RXF2_PUTGET1_OFFSET _u(0x0000014c) -#define PIO_RXF2_PUTGET1_BITS _u(0xffffffff) -#define PIO_RXF2_PUTGET1_RESET _u(0x00000000) -#define PIO_RXF2_PUTGET1_MSB _u(31) -#define PIO_RXF2_PUTGET1_LSB _u(0) -#define PIO_RXF2_PUTGET1_ACCESS "RW" -// ============================================================================= -// Register : PIO_RXF2_PUTGET2 -// Description : Direct read/write access to entry 2 of SM2's RX FIFO, if -// SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. -#define PIO_RXF2_PUTGET2_OFFSET _u(0x00000150) -#define PIO_RXF2_PUTGET2_BITS _u(0xffffffff) -#define PIO_RXF2_PUTGET2_RESET _u(0x00000000) -#define PIO_RXF2_PUTGET2_MSB _u(31) -#define PIO_RXF2_PUTGET2_LSB _u(0) -#define PIO_RXF2_PUTGET2_ACCESS "RW" -// ============================================================================= -// Register : PIO_RXF2_PUTGET3 -// Description : Direct read/write access to entry 3 of SM2's RX FIFO, if -// SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. -#define PIO_RXF2_PUTGET3_OFFSET _u(0x00000154) -#define PIO_RXF2_PUTGET3_BITS _u(0xffffffff) -#define PIO_RXF2_PUTGET3_RESET _u(0x00000000) -#define PIO_RXF2_PUTGET3_MSB _u(31) -#define PIO_RXF2_PUTGET3_LSB _u(0) -#define PIO_RXF2_PUTGET3_ACCESS "RW" -// ============================================================================= -// Register : PIO_RXF3_PUTGET0 -// Description : Direct read/write access to entry 0 of SM3's RX FIFO, if -// SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. -#define PIO_RXF3_PUTGET0_OFFSET _u(0x00000158) -#define PIO_RXF3_PUTGET0_BITS _u(0xffffffff) -#define PIO_RXF3_PUTGET0_RESET _u(0x00000000) -#define PIO_RXF3_PUTGET0_MSB _u(31) -#define PIO_RXF3_PUTGET0_LSB _u(0) -#define PIO_RXF3_PUTGET0_ACCESS "RW" -// ============================================================================= -// Register : PIO_RXF3_PUTGET1 -// Description : Direct read/write access to entry 1 of SM3's RX FIFO, if -// SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. -#define PIO_RXF3_PUTGET1_OFFSET _u(0x0000015c) -#define PIO_RXF3_PUTGET1_BITS _u(0xffffffff) -#define PIO_RXF3_PUTGET1_RESET _u(0x00000000) -#define PIO_RXF3_PUTGET1_MSB _u(31) -#define PIO_RXF3_PUTGET1_LSB _u(0) -#define PIO_RXF3_PUTGET1_ACCESS "RW" -// ============================================================================= -// Register : PIO_RXF3_PUTGET2 -// Description : Direct read/write access to entry 2 of SM3's RX FIFO, if -// SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. -#define PIO_RXF3_PUTGET2_OFFSET _u(0x00000160) -#define PIO_RXF3_PUTGET2_BITS _u(0xffffffff) -#define PIO_RXF3_PUTGET2_RESET _u(0x00000000) -#define PIO_RXF3_PUTGET2_MSB _u(31) -#define PIO_RXF3_PUTGET2_LSB _u(0) -#define PIO_RXF3_PUTGET2_ACCESS "RW" -// ============================================================================= -// Register : PIO_RXF3_PUTGET3 -// Description : Direct read/write access to entry 3 of SM3's RX FIFO, if -// SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. -#define PIO_RXF3_PUTGET3_OFFSET _u(0x00000164) -#define PIO_RXF3_PUTGET3_BITS _u(0xffffffff) -#define PIO_RXF3_PUTGET3_RESET _u(0x00000000) -#define PIO_RXF3_PUTGET3_MSB _u(31) -#define PIO_RXF3_PUTGET3_LSB _u(0) -#define PIO_RXF3_PUTGET3_ACCESS "RW" -// ============================================================================= -// Register : PIO_GPIOBASE -// Description : Relocate GPIO 0 (from PIO's point of view) in the system GPIO -// numbering, to access more than 32 GPIOs from PIO. -// -// Only the values 0 and 16 are supported (only bit 4 is -// writable). -#define PIO_GPIOBASE_OFFSET _u(0x00000168) -#define PIO_GPIOBASE_BITS _u(0x00000010) -#define PIO_GPIOBASE_RESET _u(0x00000000) -#define PIO_GPIOBASE_MSB _u(4) -#define PIO_GPIOBASE_LSB _u(4) -#define PIO_GPIOBASE_ACCESS "RW" -// ============================================================================= -// Register : PIO_INTR -// Description : Raw Interrupts -#define PIO_INTR_OFFSET _u(0x0000016c) -#define PIO_INTR_BITS _u(0x0000ffff) -#define PIO_INTR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : PIO_INTR_SM7 -#define PIO_INTR_SM7_RESET _u(0x0) -#define PIO_INTR_SM7_BITS _u(0x00008000) -#define PIO_INTR_SM7_MSB _u(15) -#define PIO_INTR_SM7_LSB _u(15) -#define PIO_INTR_SM7_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PIO_INTR_SM6 -#define PIO_INTR_SM6_RESET _u(0x0) -#define PIO_INTR_SM6_BITS _u(0x00004000) -#define PIO_INTR_SM6_MSB _u(14) -#define PIO_INTR_SM6_LSB _u(14) -#define PIO_INTR_SM6_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PIO_INTR_SM5 -#define PIO_INTR_SM5_RESET _u(0x0) -#define PIO_INTR_SM5_BITS _u(0x00002000) -#define PIO_INTR_SM5_MSB _u(13) -#define PIO_INTR_SM5_LSB _u(13) -#define PIO_INTR_SM5_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PIO_INTR_SM4 -#define PIO_INTR_SM4_RESET _u(0x0) -#define PIO_INTR_SM4_BITS _u(0x00001000) -#define PIO_INTR_SM4_MSB _u(12) -#define PIO_INTR_SM4_LSB _u(12) -#define PIO_INTR_SM4_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PIO_INTR_SM3 -#define PIO_INTR_SM3_RESET _u(0x0) -#define PIO_INTR_SM3_BITS _u(0x00000800) -#define PIO_INTR_SM3_MSB _u(11) -#define PIO_INTR_SM3_LSB _u(11) -#define PIO_INTR_SM3_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PIO_INTR_SM2 -#define PIO_INTR_SM2_RESET _u(0x0) -#define PIO_INTR_SM2_BITS _u(0x00000400) -#define PIO_INTR_SM2_MSB _u(10) -#define PIO_INTR_SM2_LSB _u(10) -#define PIO_INTR_SM2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PIO_INTR_SM1 -#define PIO_INTR_SM1_RESET _u(0x0) -#define PIO_INTR_SM1_BITS _u(0x00000200) -#define PIO_INTR_SM1_MSB _u(9) -#define PIO_INTR_SM1_LSB _u(9) -#define PIO_INTR_SM1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PIO_INTR_SM0 -#define PIO_INTR_SM0_RESET _u(0x0) -#define PIO_INTR_SM0_BITS _u(0x00000100) -#define PIO_INTR_SM0_MSB _u(8) -#define PIO_INTR_SM0_LSB _u(8) -#define PIO_INTR_SM0_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PIO_INTR_SM3_TXNFULL -#define PIO_INTR_SM3_TXNFULL_RESET _u(0x0) -#define PIO_INTR_SM3_TXNFULL_BITS _u(0x00000080) -#define PIO_INTR_SM3_TXNFULL_MSB _u(7) -#define PIO_INTR_SM3_TXNFULL_LSB _u(7) -#define PIO_INTR_SM3_TXNFULL_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PIO_INTR_SM2_TXNFULL -#define PIO_INTR_SM2_TXNFULL_RESET _u(0x0) -#define PIO_INTR_SM2_TXNFULL_BITS _u(0x00000040) -#define PIO_INTR_SM2_TXNFULL_MSB _u(6) -#define PIO_INTR_SM2_TXNFULL_LSB _u(6) -#define PIO_INTR_SM2_TXNFULL_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PIO_INTR_SM1_TXNFULL -#define PIO_INTR_SM1_TXNFULL_RESET _u(0x0) -#define PIO_INTR_SM1_TXNFULL_BITS _u(0x00000020) -#define PIO_INTR_SM1_TXNFULL_MSB _u(5) -#define PIO_INTR_SM1_TXNFULL_LSB _u(5) -#define PIO_INTR_SM1_TXNFULL_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PIO_INTR_SM0_TXNFULL -#define PIO_INTR_SM0_TXNFULL_RESET _u(0x0) -#define PIO_INTR_SM0_TXNFULL_BITS _u(0x00000010) -#define PIO_INTR_SM0_TXNFULL_MSB _u(4) -#define PIO_INTR_SM0_TXNFULL_LSB _u(4) -#define PIO_INTR_SM0_TXNFULL_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PIO_INTR_SM3_RXNEMPTY -#define PIO_INTR_SM3_RXNEMPTY_RESET _u(0x0) -#define PIO_INTR_SM3_RXNEMPTY_BITS _u(0x00000008) -#define PIO_INTR_SM3_RXNEMPTY_MSB _u(3) -#define PIO_INTR_SM3_RXNEMPTY_LSB _u(3) -#define PIO_INTR_SM3_RXNEMPTY_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PIO_INTR_SM2_RXNEMPTY -#define PIO_INTR_SM2_RXNEMPTY_RESET _u(0x0) -#define PIO_INTR_SM2_RXNEMPTY_BITS _u(0x00000004) -#define PIO_INTR_SM2_RXNEMPTY_MSB _u(2) -#define PIO_INTR_SM2_RXNEMPTY_LSB _u(2) -#define PIO_INTR_SM2_RXNEMPTY_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PIO_INTR_SM1_RXNEMPTY -#define PIO_INTR_SM1_RXNEMPTY_RESET _u(0x0) -#define PIO_INTR_SM1_RXNEMPTY_BITS _u(0x00000002) -#define PIO_INTR_SM1_RXNEMPTY_MSB _u(1) -#define PIO_INTR_SM1_RXNEMPTY_LSB _u(1) -#define PIO_INTR_SM1_RXNEMPTY_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PIO_INTR_SM0_RXNEMPTY -#define PIO_INTR_SM0_RXNEMPTY_RESET _u(0x0) -#define PIO_INTR_SM0_RXNEMPTY_BITS _u(0x00000001) -#define PIO_INTR_SM0_RXNEMPTY_MSB _u(0) -#define PIO_INTR_SM0_RXNEMPTY_LSB _u(0) -#define PIO_INTR_SM0_RXNEMPTY_ACCESS "RO" -// ============================================================================= -// Register : PIO_IRQ0_INTE -// Description : Interrupt Enable for irq0 -#define PIO_IRQ0_INTE_OFFSET _u(0x00000170) -#define PIO_IRQ0_INTE_BITS _u(0x0000ffff) -#define PIO_IRQ0_INTE_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ0_INTE_SM7 -#define PIO_IRQ0_INTE_SM7_RESET _u(0x0) -#define PIO_IRQ0_INTE_SM7_BITS _u(0x00008000) -#define PIO_IRQ0_INTE_SM7_MSB _u(15) -#define PIO_IRQ0_INTE_SM7_LSB _u(15) -#define PIO_IRQ0_INTE_SM7_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ0_INTE_SM6 -#define PIO_IRQ0_INTE_SM6_RESET _u(0x0) -#define PIO_IRQ0_INTE_SM6_BITS _u(0x00004000) -#define PIO_IRQ0_INTE_SM6_MSB _u(14) -#define PIO_IRQ0_INTE_SM6_LSB _u(14) -#define PIO_IRQ0_INTE_SM6_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ0_INTE_SM5 -#define PIO_IRQ0_INTE_SM5_RESET _u(0x0) -#define PIO_IRQ0_INTE_SM5_BITS _u(0x00002000) -#define PIO_IRQ0_INTE_SM5_MSB _u(13) -#define PIO_IRQ0_INTE_SM5_LSB _u(13) -#define PIO_IRQ0_INTE_SM5_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ0_INTE_SM4 -#define PIO_IRQ0_INTE_SM4_RESET _u(0x0) -#define PIO_IRQ0_INTE_SM4_BITS _u(0x00001000) -#define PIO_IRQ0_INTE_SM4_MSB _u(12) -#define PIO_IRQ0_INTE_SM4_LSB _u(12) -#define PIO_IRQ0_INTE_SM4_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ0_INTE_SM3 -#define PIO_IRQ0_INTE_SM3_RESET _u(0x0) -#define PIO_IRQ0_INTE_SM3_BITS _u(0x00000800) -#define PIO_IRQ0_INTE_SM3_MSB _u(11) -#define PIO_IRQ0_INTE_SM3_LSB _u(11) -#define PIO_IRQ0_INTE_SM3_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ0_INTE_SM2 -#define PIO_IRQ0_INTE_SM2_RESET _u(0x0) -#define PIO_IRQ0_INTE_SM2_BITS _u(0x00000400) -#define PIO_IRQ0_INTE_SM2_MSB _u(10) -#define PIO_IRQ0_INTE_SM2_LSB _u(10) -#define PIO_IRQ0_INTE_SM2_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ0_INTE_SM1 -#define PIO_IRQ0_INTE_SM1_RESET _u(0x0) -#define PIO_IRQ0_INTE_SM1_BITS _u(0x00000200) -#define PIO_IRQ0_INTE_SM1_MSB _u(9) -#define PIO_IRQ0_INTE_SM1_LSB _u(9) -#define PIO_IRQ0_INTE_SM1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ0_INTE_SM0 -#define PIO_IRQ0_INTE_SM0_RESET _u(0x0) -#define PIO_IRQ0_INTE_SM0_BITS _u(0x00000100) -#define PIO_IRQ0_INTE_SM0_MSB _u(8) -#define PIO_IRQ0_INTE_SM0_LSB _u(8) -#define PIO_IRQ0_INTE_SM0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ0_INTE_SM3_TXNFULL -#define PIO_IRQ0_INTE_SM3_TXNFULL_RESET _u(0x0) -#define PIO_IRQ0_INTE_SM3_TXNFULL_BITS _u(0x00000080) -#define PIO_IRQ0_INTE_SM3_TXNFULL_MSB _u(7) -#define PIO_IRQ0_INTE_SM3_TXNFULL_LSB _u(7) -#define PIO_IRQ0_INTE_SM3_TXNFULL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ0_INTE_SM2_TXNFULL -#define PIO_IRQ0_INTE_SM2_TXNFULL_RESET _u(0x0) -#define PIO_IRQ0_INTE_SM2_TXNFULL_BITS _u(0x00000040) -#define PIO_IRQ0_INTE_SM2_TXNFULL_MSB _u(6) -#define PIO_IRQ0_INTE_SM2_TXNFULL_LSB _u(6) -#define PIO_IRQ0_INTE_SM2_TXNFULL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ0_INTE_SM1_TXNFULL -#define PIO_IRQ0_INTE_SM1_TXNFULL_RESET _u(0x0) -#define PIO_IRQ0_INTE_SM1_TXNFULL_BITS _u(0x00000020) -#define PIO_IRQ0_INTE_SM1_TXNFULL_MSB _u(5) -#define PIO_IRQ0_INTE_SM1_TXNFULL_LSB _u(5) -#define PIO_IRQ0_INTE_SM1_TXNFULL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ0_INTE_SM0_TXNFULL -#define PIO_IRQ0_INTE_SM0_TXNFULL_RESET _u(0x0) -#define PIO_IRQ0_INTE_SM0_TXNFULL_BITS _u(0x00000010) -#define PIO_IRQ0_INTE_SM0_TXNFULL_MSB _u(4) -#define PIO_IRQ0_INTE_SM0_TXNFULL_LSB _u(4) -#define PIO_IRQ0_INTE_SM0_TXNFULL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ0_INTE_SM3_RXNEMPTY -#define PIO_IRQ0_INTE_SM3_RXNEMPTY_RESET _u(0x0) -#define PIO_IRQ0_INTE_SM3_RXNEMPTY_BITS _u(0x00000008) -#define PIO_IRQ0_INTE_SM3_RXNEMPTY_MSB _u(3) -#define PIO_IRQ0_INTE_SM3_RXNEMPTY_LSB _u(3) -#define PIO_IRQ0_INTE_SM3_RXNEMPTY_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ0_INTE_SM2_RXNEMPTY -#define PIO_IRQ0_INTE_SM2_RXNEMPTY_RESET _u(0x0) -#define PIO_IRQ0_INTE_SM2_RXNEMPTY_BITS _u(0x00000004) -#define PIO_IRQ0_INTE_SM2_RXNEMPTY_MSB _u(2) -#define PIO_IRQ0_INTE_SM2_RXNEMPTY_LSB _u(2) -#define PIO_IRQ0_INTE_SM2_RXNEMPTY_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ0_INTE_SM1_RXNEMPTY -#define PIO_IRQ0_INTE_SM1_RXNEMPTY_RESET _u(0x0) -#define PIO_IRQ0_INTE_SM1_RXNEMPTY_BITS _u(0x00000002) -#define PIO_IRQ0_INTE_SM1_RXNEMPTY_MSB _u(1) -#define PIO_IRQ0_INTE_SM1_RXNEMPTY_LSB _u(1) -#define PIO_IRQ0_INTE_SM1_RXNEMPTY_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ0_INTE_SM0_RXNEMPTY -#define PIO_IRQ0_INTE_SM0_RXNEMPTY_RESET _u(0x0) -#define PIO_IRQ0_INTE_SM0_RXNEMPTY_BITS _u(0x00000001) -#define PIO_IRQ0_INTE_SM0_RXNEMPTY_MSB _u(0) -#define PIO_IRQ0_INTE_SM0_RXNEMPTY_LSB _u(0) -#define PIO_IRQ0_INTE_SM0_RXNEMPTY_ACCESS "RW" -// ============================================================================= -// Register : PIO_IRQ0_INTF -// Description : Interrupt Force for irq0 -#define PIO_IRQ0_INTF_OFFSET _u(0x00000174) -#define PIO_IRQ0_INTF_BITS _u(0x0000ffff) -#define PIO_IRQ0_INTF_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ0_INTF_SM7 -#define PIO_IRQ0_INTF_SM7_RESET _u(0x0) -#define PIO_IRQ0_INTF_SM7_BITS _u(0x00008000) -#define PIO_IRQ0_INTF_SM7_MSB _u(15) -#define PIO_IRQ0_INTF_SM7_LSB _u(15) -#define PIO_IRQ0_INTF_SM7_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ0_INTF_SM6 -#define PIO_IRQ0_INTF_SM6_RESET _u(0x0) -#define PIO_IRQ0_INTF_SM6_BITS _u(0x00004000) -#define PIO_IRQ0_INTF_SM6_MSB _u(14) -#define PIO_IRQ0_INTF_SM6_LSB _u(14) -#define PIO_IRQ0_INTF_SM6_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ0_INTF_SM5 -#define PIO_IRQ0_INTF_SM5_RESET _u(0x0) -#define PIO_IRQ0_INTF_SM5_BITS _u(0x00002000) -#define PIO_IRQ0_INTF_SM5_MSB _u(13) -#define PIO_IRQ0_INTF_SM5_LSB _u(13) -#define PIO_IRQ0_INTF_SM5_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ0_INTF_SM4 -#define PIO_IRQ0_INTF_SM4_RESET _u(0x0) -#define PIO_IRQ0_INTF_SM4_BITS _u(0x00001000) -#define PIO_IRQ0_INTF_SM4_MSB _u(12) -#define PIO_IRQ0_INTF_SM4_LSB _u(12) -#define PIO_IRQ0_INTF_SM4_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ0_INTF_SM3 -#define PIO_IRQ0_INTF_SM3_RESET _u(0x0) -#define PIO_IRQ0_INTF_SM3_BITS _u(0x00000800) -#define PIO_IRQ0_INTF_SM3_MSB _u(11) -#define PIO_IRQ0_INTF_SM3_LSB _u(11) -#define PIO_IRQ0_INTF_SM3_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ0_INTF_SM2 -#define PIO_IRQ0_INTF_SM2_RESET _u(0x0) -#define PIO_IRQ0_INTF_SM2_BITS _u(0x00000400) -#define PIO_IRQ0_INTF_SM2_MSB _u(10) -#define PIO_IRQ0_INTF_SM2_LSB _u(10) -#define PIO_IRQ0_INTF_SM2_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ0_INTF_SM1 -#define PIO_IRQ0_INTF_SM1_RESET _u(0x0) -#define PIO_IRQ0_INTF_SM1_BITS _u(0x00000200) -#define PIO_IRQ0_INTF_SM1_MSB _u(9) -#define PIO_IRQ0_INTF_SM1_LSB _u(9) -#define PIO_IRQ0_INTF_SM1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ0_INTF_SM0 -#define PIO_IRQ0_INTF_SM0_RESET _u(0x0) -#define PIO_IRQ0_INTF_SM0_BITS _u(0x00000100) -#define PIO_IRQ0_INTF_SM0_MSB _u(8) -#define PIO_IRQ0_INTF_SM0_LSB _u(8) -#define PIO_IRQ0_INTF_SM0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ0_INTF_SM3_TXNFULL -#define PIO_IRQ0_INTF_SM3_TXNFULL_RESET _u(0x0) -#define PIO_IRQ0_INTF_SM3_TXNFULL_BITS _u(0x00000080) -#define PIO_IRQ0_INTF_SM3_TXNFULL_MSB _u(7) -#define PIO_IRQ0_INTF_SM3_TXNFULL_LSB _u(7) -#define PIO_IRQ0_INTF_SM3_TXNFULL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ0_INTF_SM2_TXNFULL -#define PIO_IRQ0_INTF_SM2_TXNFULL_RESET _u(0x0) -#define PIO_IRQ0_INTF_SM2_TXNFULL_BITS _u(0x00000040) -#define PIO_IRQ0_INTF_SM2_TXNFULL_MSB _u(6) -#define PIO_IRQ0_INTF_SM2_TXNFULL_LSB _u(6) -#define PIO_IRQ0_INTF_SM2_TXNFULL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ0_INTF_SM1_TXNFULL -#define PIO_IRQ0_INTF_SM1_TXNFULL_RESET _u(0x0) -#define PIO_IRQ0_INTF_SM1_TXNFULL_BITS _u(0x00000020) -#define PIO_IRQ0_INTF_SM1_TXNFULL_MSB _u(5) -#define PIO_IRQ0_INTF_SM1_TXNFULL_LSB _u(5) -#define PIO_IRQ0_INTF_SM1_TXNFULL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ0_INTF_SM0_TXNFULL -#define PIO_IRQ0_INTF_SM0_TXNFULL_RESET _u(0x0) -#define PIO_IRQ0_INTF_SM0_TXNFULL_BITS _u(0x00000010) -#define PIO_IRQ0_INTF_SM0_TXNFULL_MSB _u(4) -#define PIO_IRQ0_INTF_SM0_TXNFULL_LSB _u(4) -#define PIO_IRQ0_INTF_SM0_TXNFULL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ0_INTF_SM3_RXNEMPTY -#define PIO_IRQ0_INTF_SM3_RXNEMPTY_RESET _u(0x0) -#define PIO_IRQ0_INTF_SM3_RXNEMPTY_BITS _u(0x00000008) -#define PIO_IRQ0_INTF_SM3_RXNEMPTY_MSB _u(3) -#define PIO_IRQ0_INTF_SM3_RXNEMPTY_LSB _u(3) -#define PIO_IRQ0_INTF_SM3_RXNEMPTY_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ0_INTF_SM2_RXNEMPTY -#define PIO_IRQ0_INTF_SM2_RXNEMPTY_RESET _u(0x0) -#define PIO_IRQ0_INTF_SM2_RXNEMPTY_BITS _u(0x00000004) -#define PIO_IRQ0_INTF_SM2_RXNEMPTY_MSB _u(2) -#define PIO_IRQ0_INTF_SM2_RXNEMPTY_LSB _u(2) -#define PIO_IRQ0_INTF_SM2_RXNEMPTY_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ0_INTF_SM1_RXNEMPTY -#define PIO_IRQ0_INTF_SM1_RXNEMPTY_RESET _u(0x0) -#define PIO_IRQ0_INTF_SM1_RXNEMPTY_BITS _u(0x00000002) -#define PIO_IRQ0_INTF_SM1_RXNEMPTY_MSB _u(1) -#define PIO_IRQ0_INTF_SM1_RXNEMPTY_LSB _u(1) -#define PIO_IRQ0_INTF_SM1_RXNEMPTY_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ0_INTF_SM0_RXNEMPTY -#define PIO_IRQ0_INTF_SM0_RXNEMPTY_RESET _u(0x0) -#define PIO_IRQ0_INTF_SM0_RXNEMPTY_BITS _u(0x00000001) -#define PIO_IRQ0_INTF_SM0_RXNEMPTY_MSB _u(0) -#define PIO_IRQ0_INTF_SM0_RXNEMPTY_LSB _u(0) -#define PIO_IRQ0_INTF_SM0_RXNEMPTY_ACCESS "RW" -// ============================================================================= -// Register : PIO_IRQ0_INTS -// Description : Interrupt status after masking & forcing for irq0 -#define PIO_IRQ0_INTS_OFFSET _u(0x00000178) -#define PIO_IRQ0_INTS_BITS _u(0x0000ffff) -#define PIO_IRQ0_INTS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ0_INTS_SM7 -#define PIO_IRQ0_INTS_SM7_RESET _u(0x0) -#define PIO_IRQ0_INTS_SM7_BITS _u(0x00008000) -#define PIO_IRQ0_INTS_SM7_MSB _u(15) -#define PIO_IRQ0_INTS_SM7_LSB _u(15) -#define PIO_IRQ0_INTS_SM7_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ0_INTS_SM6 -#define PIO_IRQ0_INTS_SM6_RESET _u(0x0) -#define PIO_IRQ0_INTS_SM6_BITS _u(0x00004000) -#define PIO_IRQ0_INTS_SM6_MSB _u(14) -#define PIO_IRQ0_INTS_SM6_LSB _u(14) -#define PIO_IRQ0_INTS_SM6_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ0_INTS_SM5 -#define PIO_IRQ0_INTS_SM5_RESET _u(0x0) -#define PIO_IRQ0_INTS_SM5_BITS _u(0x00002000) -#define PIO_IRQ0_INTS_SM5_MSB _u(13) -#define PIO_IRQ0_INTS_SM5_LSB _u(13) -#define PIO_IRQ0_INTS_SM5_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ0_INTS_SM4 -#define PIO_IRQ0_INTS_SM4_RESET _u(0x0) -#define PIO_IRQ0_INTS_SM4_BITS _u(0x00001000) -#define PIO_IRQ0_INTS_SM4_MSB _u(12) -#define PIO_IRQ0_INTS_SM4_LSB _u(12) -#define PIO_IRQ0_INTS_SM4_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ0_INTS_SM3 -#define PIO_IRQ0_INTS_SM3_RESET _u(0x0) -#define PIO_IRQ0_INTS_SM3_BITS _u(0x00000800) -#define PIO_IRQ0_INTS_SM3_MSB _u(11) -#define PIO_IRQ0_INTS_SM3_LSB _u(11) -#define PIO_IRQ0_INTS_SM3_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ0_INTS_SM2 -#define PIO_IRQ0_INTS_SM2_RESET _u(0x0) -#define PIO_IRQ0_INTS_SM2_BITS _u(0x00000400) -#define PIO_IRQ0_INTS_SM2_MSB _u(10) -#define PIO_IRQ0_INTS_SM2_LSB _u(10) -#define PIO_IRQ0_INTS_SM2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ0_INTS_SM1 -#define PIO_IRQ0_INTS_SM1_RESET _u(0x0) -#define PIO_IRQ0_INTS_SM1_BITS _u(0x00000200) -#define PIO_IRQ0_INTS_SM1_MSB _u(9) -#define PIO_IRQ0_INTS_SM1_LSB _u(9) -#define PIO_IRQ0_INTS_SM1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ0_INTS_SM0 -#define PIO_IRQ0_INTS_SM0_RESET _u(0x0) -#define PIO_IRQ0_INTS_SM0_BITS _u(0x00000100) -#define PIO_IRQ0_INTS_SM0_MSB _u(8) -#define PIO_IRQ0_INTS_SM0_LSB _u(8) -#define PIO_IRQ0_INTS_SM0_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ0_INTS_SM3_TXNFULL -#define PIO_IRQ0_INTS_SM3_TXNFULL_RESET _u(0x0) -#define PIO_IRQ0_INTS_SM3_TXNFULL_BITS _u(0x00000080) -#define PIO_IRQ0_INTS_SM3_TXNFULL_MSB _u(7) -#define PIO_IRQ0_INTS_SM3_TXNFULL_LSB _u(7) -#define PIO_IRQ0_INTS_SM3_TXNFULL_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ0_INTS_SM2_TXNFULL -#define PIO_IRQ0_INTS_SM2_TXNFULL_RESET _u(0x0) -#define PIO_IRQ0_INTS_SM2_TXNFULL_BITS _u(0x00000040) -#define PIO_IRQ0_INTS_SM2_TXNFULL_MSB _u(6) -#define PIO_IRQ0_INTS_SM2_TXNFULL_LSB _u(6) -#define PIO_IRQ0_INTS_SM2_TXNFULL_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ0_INTS_SM1_TXNFULL -#define PIO_IRQ0_INTS_SM1_TXNFULL_RESET _u(0x0) -#define PIO_IRQ0_INTS_SM1_TXNFULL_BITS _u(0x00000020) -#define PIO_IRQ0_INTS_SM1_TXNFULL_MSB _u(5) -#define PIO_IRQ0_INTS_SM1_TXNFULL_LSB _u(5) -#define PIO_IRQ0_INTS_SM1_TXNFULL_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ0_INTS_SM0_TXNFULL -#define PIO_IRQ0_INTS_SM0_TXNFULL_RESET _u(0x0) -#define PIO_IRQ0_INTS_SM0_TXNFULL_BITS _u(0x00000010) -#define PIO_IRQ0_INTS_SM0_TXNFULL_MSB _u(4) -#define PIO_IRQ0_INTS_SM0_TXNFULL_LSB _u(4) -#define PIO_IRQ0_INTS_SM0_TXNFULL_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ0_INTS_SM3_RXNEMPTY -#define PIO_IRQ0_INTS_SM3_RXNEMPTY_RESET _u(0x0) -#define PIO_IRQ0_INTS_SM3_RXNEMPTY_BITS _u(0x00000008) -#define PIO_IRQ0_INTS_SM3_RXNEMPTY_MSB _u(3) -#define PIO_IRQ0_INTS_SM3_RXNEMPTY_LSB _u(3) -#define PIO_IRQ0_INTS_SM3_RXNEMPTY_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ0_INTS_SM2_RXNEMPTY -#define PIO_IRQ0_INTS_SM2_RXNEMPTY_RESET _u(0x0) -#define PIO_IRQ0_INTS_SM2_RXNEMPTY_BITS _u(0x00000004) -#define PIO_IRQ0_INTS_SM2_RXNEMPTY_MSB _u(2) -#define PIO_IRQ0_INTS_SM2_RXNEMPTY_LSB _u(2) -#define PIO_IRQ0_INTS_SM2_RXNEMPTY_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ0_INTS_SM1_RXNEMPTY -#define PIO_IRQ0_INTS_SM1_RXNEMPTY_RESET _u(0x0) -#define PIO_IRQ0_INTS_SM1_RXNEMPTY_BITS _u(0x00000002) -#define PIO_IRQ0_INTS_SM1_RXNEMPTY_MSB _u(1) -#define PIO_IRQ0_INTS_SM1_RXNEMPTY_LSB _u(1) -#define PIO_IRQ0_INTS_SM1_RXNEMPTY_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ0_INTS_SM0_RXNEMPTY -#define PIO_IRQ0_INTS_SM0_RXNEMPTY_RESET _u(0x0) -#define PIO_IRQ0_INTS_SM0_RXNEMPTY_BITS _u(0x00000001) -#define PIO_IRQ0_INTS_SM0_RXNEMPTY_MSB _u(0) -#define PIO_IRQ0_INTS_SM0_RXNEMPTY_LSB _u(0) -#define PIO_IRQ0_INTS_SM0_RXNEMPTY_ACCESS "RO" -// ============================================================================= -// Register : PIO_IRQ1_INTE -// Description : Interrupt Enable for irq1 -#define PIO_IRQ1_INTE_OFFSET _u(0x0000017c) -#define PIO_IRQ1_INTE_BITS _u(0x0000ffff) -#define PIO_IRQ1_INTE_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ1_INTE_SM7 -#define PIO_IRQ1_INTE_SM7_RESET _u(0x0) -#define PIO_IRQ1_INTE_SM7_BITS _u(0x00008000) -#define PIO_IRQ1_INTE_SM7_MSB _u(15) -#define PIO_IRQ1_INTE_SM7_LSB _u(15) -#define PIO_IRQ1_INTE_SM7_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ1_INTE_SM6 -#define PIO_IRQ1_INTE_SM6_RESET _u(0x0) -#define PIO_IRQ1_INTE_SM6_BITS _u(0x00004000) -#define PIO_IRQ1_INTE_SM6_MSB _u(14) -#define PIO_IRQ1_INTE_SM6_LSB _u(14) -#define PIO_IRQ1_INTE_SM6_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ1_INTE_SM5 -#define PIO_IRQ1_INTE_SM5_RESET _u(0x0) -#define PIO_IRQ1_INTE_SM5_BITS _u(0x00002000) -#define PIO_IRQ1_INTE_SM5_MSB _u(13) -#define PIO_IRQ1_INTE_SM5_LSB _u(13) -#define PIO_IRQ1_INTE_SM5_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ1_INTE_SM4 -#define PIO_IRQ1_INTE_SM4_RESET _u(0x0) -#define PIO_IRQ1_INTE_SM4_BITS _u(0x00001000) -#define PIO_IRQ1_INTE_SM4_MSB _u(12) -#define PIO_IRQ1_INTE_SM4_LSB _u(12) -#define PIO_IRQ1_INTE_SM4_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ1_INTE_SM3 -#define PIO_IRQ1_INTE_SM3_RESET _u(0x0) -#define PIO_IRQ1_INTE_SM3_BITS _u(0x00000800) -#define PIO_IRQ1_INTE_SM3_MSB _u(11) -#define PIO_IRQ1_INTE_SM3_LSB _u(11) -#define PIO_IRQ1_INTE_SM3_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ1_INTE_SM2 -#define PIO_IRQ1_INTE_SM2_RESET _u(0x0) -#define PIO_IRQ1_INTE_SM2_BITS _u(0x00000400) -#define PIO_IRQ1_INTE_SM2_MSB _u(10) -#define PIO_IRQ1_INTE_SM2_LSB _u(10) -#define PIO_IRQ1_INTE_SM2_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ1_INTE_SM1 -#define PIO_IRQ1_INTE_SM1_RESET _u(0x0) -#define PIO_IRQ1_INTE_SM1_BITS _u(0x00000200) -#define PIO_IRQ1_INTE_SM1_MSB _u(9) -#define PIO_IRQ1_INTE_SM1_LSB _u(9) -#define PIO_IRQ1_INTE_SM1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ1_INTE_SM0 -#define PIO_IRQ1_INTE_SM0_RESET _u(0x0) -#define PIO_IRQ1_INTE_SM0_BITS _u(0x00000100) -#define PIO_IRQ1_INTE_SM0_MSB _u(8) -#define PIO_IRQ1_INTE_SM0_LSB _u(8) -#define PIO_IRQ1_INTE_SM0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ1_INTE_SM3_TXNFULL -#define PIO_IRQ1_INTE_SM3_TXNFULL_RESET _u(0x0) -#define PIO_IRQ1_INTE_SM3_TXNFULL_BITS _u(0x00000080) -#define PIO_IRQ1_INTE_SM3_TXNFULL_MSB _u(7) -#define PIO_IRQ1_INTE_SM3_TXNFULL_LSB _u(7) -#define PIO_IRQ1_INTE_SM3_TXNFULL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ1_INTE_SM2_TXNFULL -#define PIO_IRQ1_INTE_SM2_TXNFULL_RESET _u(0x0) -#define PIO_IRQ1_INTE_SM2_TXNFULL_BITS _u(0x00000040) -#define PIO_IRQ1_INTE_SM2_TXNFULL_MSB _u(6) -#define PIO_IRQ1_INTE_SM2_TXNFULL_LSB _u(6) -#define PIO_IRQ1_INTE_SM2_TXNFULL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ1_INTE_SM1_TXNFULL -#define PIO_IRQ1_INTE_SM1_TXNFULL_RESET _u(0x0) -#define PIO_IRQ1_INTE_SM1_TXNFULL_BITS _u(0x00000020) -#define PIO_IRQ1_INTE_SM1_TXNFULL_MSB _u(5) -#define PIO_IRQ1_INTE_SM1_TXNFULL_LSB _u(5) -#define PIO_IRQ1_INTE_SM1_TXNFULL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ1_INTE_SM0_TXNFULL -#define PIO_IRQ1_INTE_SM0_TXNFULL_RESET _u(0x0) -#define PIO_IRQ1_INTE_SM0_TXNFULL_BITS _u(0x00000010) -#define PIO_IRQ1_INTE_SM0_TXNFULL_MSB _u(4) -#define PIO_IRQ1_INTE_SM0_TXNFULL_LSB _u(4) -#define PIO_IRQ1_INTE_SM0_TXNFULL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ1_INTE_SM3_RXNEMPTY -#define PIO_IRQ1_INTE_SM3_RXNEMPTY_RESET _u(0x0) -#define PIO_IRQ1_INTE_SM3_RXNEMPTY_BITS _u(0x00000008) -#define PIO_IRQ1_INTE_SM3_RXNEMPTY_MSB _u(3) -#define PIO_IRQ1_INTE_SM3_RXNEMPTY_LSB _u(3) -#define PIO_IRQ1_INTE_SM3_RXNEMPTY_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ1_INTE_SM2_RXNEMPTY -#define PIO_IRQ1_INTE_SM2_RXNEMPTY_RESET _u(0x0) -#define PIO_IRQ1_INTE_SM2_RXNEMPTY_BITS _u(0x00000004) -#define PIO_IRQ1_INTE_SM2_RXNEMPTY_MSB _u(2) -#define PIO_IRQ1_INTE_SM2_RXNEMPTY_LSB _u(2) -#define PIO_IRQ1_INTE_SM2_RXNEMPTY_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ1_INTE_SM1_RXNEMPTY -#define PIO_IRQ1_INTE_SM1_RXNEMPTY_RESET _u(0x0) -#define PIO_IRQ1_INTE_SM1_RXNEMPTY_BITS _u(0x00000002) -#define PIO_IRQ1_INTE_SM1_RXNEMPTY_MSB _u(1) -#define PIO_IRQ1_INTE_SM1_RXNEMPTY_LSB _u(1) -#define PIO_IRQ1_INTE_SM1_RXNEMPTY_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ1_INTE_SM0_RXNEMPTY -#define PIO_IRQ1_INTE_SM0_RXNEMPTY_RESET _u(0x0) -#define PIO_IRQ1_INTE_SM0_RXNEMPTY_BITS _u(0x00000001) -#define PIO_IRQ1_INTE_SM0_RXNEMPTY_MSB _u(0) -#define PIO_IRQ1_INTE_SM0_RXNEMPTY_LSB _u(0) -#define PIO_IRQ1_INTE_SM0_RXNEMPTY_ACCESS "RW" -// ============================================================================= -// Register : PIO_IRQ1_INTF -// Description : Interrupt Force for irq1 -#define PIO_IRQ1_INTF_OFFSET _u(0x00000180) -#define PIO_IRQ1_INTF_BITS _u(0x0000ffff) -#define PIO_IRQ1_INTF_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ1_INTF_SM7 -#define PIO_IRQ1_INTF_SM7_RESET _u(0x0) -#define PIO_IRQ1_INTF_SM7_BITS _u(0x00008000) -#define PIO_IRQ1_INTF_SM7_MSB _u(15) -#define PIO_IRQ1_INTF_SM7_LSB _u(15) -#define PIO_IRQ1_INTF_SM7_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ1_INTF_SM6 -#define PIO_IRQ1_INTF_SM6_RESET _u(0x0) -#define PIO_IRQ1_INTF_SM6_BITS _u(0x00004000) -#define PIO_IRQ1_INTF_SM6_MSB _u(14) -#define PIO_IRQ1_INTF_SM6_LSB _u(14) -#define PIO_IRQ1_INTF_SM6_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ1_INTF_SM5 -#define PIO_IRQ1_INTF_SM5_RESET _u(0x0) -#define PIO_IRQ1_INTF_SM5_BITS _u(0x00002000) -#define PIO_IRQ1_INTF_SM5_MSB _u(13) -#define PIO_IRQ1_INTF_SM5_LSB _u(13) -#define PIO_IRQ1_INTF_SM5_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ1_INTF_SM4 -#define PIO_IRQ1_INTF_SM4_RESET _u(0x0) -#define PIO_IRQ1_INTF_SM4_BITS _u(0x00001000) -#define PIO_IRQ1_INTF_SM4_MSB _u(12) -#define PIO_IRQ1_INTF_SM4_LSB _u(12) -#define PIO_IRQ1_INTF_SM4_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ1_INTF_SM3 -#define PIO_IRQ1_INTF_SM3_RESET _u(0x0) -#define PIO_IRQ1_INTF_SM3_BITS _u(0x00000800) -#define PIO_IRQ1_INTF_SM3_MSB _u(11) -#define PIO_IRQ1_INTF_SM3_LSB _u(11) -#define PIO_IRQ1_INTF_SM3_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ1_INTF_SM2 -#define PIO_IRQ1_INTF_SM2_RESET _u(0x0) -#define PIO_IRQ1_INTF_SM2_BITS _u(0x00000400) -#define PIO_IRQ1_INTF_SM2_MSB _u(10) -#define PIO_IRQ1_INTF_SM2_LSB _u(10) -#define PIO_IRQ1_INTF_SM2_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ1_INTF_SM1 -#define PIO_IRQ1_INTF_SM1_RESET _u(0x0) -#define PIO_IRQ1_INTF_SM1_BITS _u(0x00000200) -#define PIO_IRQ1_INTF_SM1_MSB _u(9) -#define PIO_IRQ1_INTF_SM1_LSB _u(9) -#define PIO_IRQ1_INTF_SM1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ1_INTF_SM0 -#define PIO_IRQ1_INTF_SM0_RESET _u(0x0) -#define PIO_IRQ1_INTF_SM0_BITS _u(0x00000100) -#define PIO_IRQ1_INTF_SM0_MSB _u(8) -#define PIO_IRQ1_INTF_SM0_LSB _u(8) -#define PIO_IRQ1_INTF_SM0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ1_INTF_SM3_TXNFULL -#define PIO_IRQ1_INTF_SM3_TXNFULL_RESET _u(0x0) -#define PIO_IRQ1_INTF_SM3_TXNFULL_BITS _u(0x00000080) -#define PIO_IRQ1_INTF_SM3_TXNFULL_MSB _u(7) -#define PIO_IRQ1_INTF_SM3_TXNFULL_LSB _u(7) -#define PIO_IRQ1_INTF_SM3_TXNFULL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ1_INTF_SM2_TXNFULL -#define PIO_IRQ1_INTF_SM2_TXNFULL_RESET _u(0x0) -#define PIO_IRQ1_INTF_SM2_TXNFULL_BITS _u(0x00000040) -#define PIO_IRQ1_INTF_SM2_TXNFULL_MSB _u(6) -#define PIO_IRQ1_INTF_SM2_TXNFULL_LSB _u(6) -#define PIO_IRQ1_INTF_SM2_TXNFULL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ1_INTF_SM1_TXNFULL -#define PIO_IRQ1_INTF_SM1_TXNFULL_RESET _u(0x0) -#define PIO_IRQ1_INTF_SM1_TXNFULL_BITS _u(0x00000020) -#define PIO_IRQ1_INTF_SM1_TXNFULL_MSB _u(5) -#define PIO_IRQ1_INTF_SM1_TXNFULL_LSB _u(5) -#define PIO_IRQ1_INTF_SM1_TXNFULL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ1_INTF_SM0_TXNFULL -#define PIO_IRQ1_INTF_SM0_TXNFULL_RESET _u(0x0) -#define PIO_IRQ1_INTF_SM0_TXNFULL_BITS _u(0x00000010) -#define PIO_IRQ1_INTF_SM0_TXNFULL_MSB _u(4) -#define PIO_IRQ1_INTF_SM0_TXNFULL_LSB _u(4) -#define PIO_IRQ1_INTF_SM0_TXNFULL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ1_INTF_SM3_RXNEMPTY -#define PIO_IRQ1_INTF_SM3_RXNEMPTY_RESET _u(0x0) -#define PIO_IRQ1_INTF_SM3_RXNEMPTY_BITS _u(0x00000008) -#define PIO_IRQ1_INTF_SM3_RXNEMPTY_MSB _u(3) -#define PIO_IRQ1_INTF_SM3_RXNEMPTY_LSB _u(3) -#define PIO_IRQ1_INTF_SM3_RXNEMPTY_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ1_INTF_SM2_RXNEMPTY -#define PIO_IRQ1_INTF_SM2_RXNEMPTY_RESET _u(0x0) -#define PIO_IRQ1_INTF_SM2_RXNEMPTY_BITS _u(0x00000004) -#define PIO_IRQ1_INTF_SM2_RXNEMPTY_MSB _u(2) -#define PIO_IRQ1_INTF_SM2_RXNEMPTY_LSB _u(2) -#define PIO_IRQ1_INTF_SM2_RXNEMPTY_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ1_INTF_SM1_RXNEMPTY -#define PIO_IRQ1_INTF_SM1_RXNEMPTY_RESET _u(0x0) -#define PIO_IRQ1_INTF_SM1_RXNEMPTY_BITS _u(0x00000002) -#define PIO_IRQ1_INTF_SM1_RXNEMPTY_MSB _u(1) -#define PIO_IRQ1_INTF_SM1_RXNEMPTY_LSB _u(1) -#define PIO_IRQ1_INTF_SM1_RXNEMPTY_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ1_INTF_SM0_RXNEMPTY -#define PIO_IRQ1_INTF_SM0_RXNEMPTY_RESET _u(0x0) -#define PIO_IRQ1_INTF_SM0_RXNEMPTY_BITS _u(0x00000001) -#define PIO_IRQ1_INTF_SM0_RXNEMPTY_MSB _u(0) -#define PIO_IRQ1_INTF_SM0_RXNEMPTY_LSB _u(0) -#define PIO_IRQ1_INTF_SM0_RXNEMPTY_ACCESS "RW" -// ============================================================================= -// Register : PIO_IRQ1_INTS -// Description : Interrupt status after masking & forcing for irq1 -#define PIO_IRQ1_INTS_OFFSET _u(0x00000184) -#define PIO_IRQ1_INTS_BITS _u(0x0000ffff) -#define PIO_IRQ1_INTS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ1_INTS_SM7 -#define PIO_IRQ1_INTS_SM7_RESET _u(0x0) -#define PIO_IRQ1_INTS_SM7_BITS _u(0x00008000) -#define PIO_IRQ1_INTS_SM7_MSB _u(15) -#define PIO_IRQ1_INTS_SM7_LSB _u(15) -#define PIO_IRQ1_INTS_SM7_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ1_INTS_SM6 -#define PIO_IRQ1_INTS_SM6_RESET _u(0x0) -#define PIO_IRQ1_INTS_SM6_BITS _u(0x00004000) -#define PIO_IRQ1_INTS_SM6_MSB _u(14) -#define PIO_IRQ1_INTS_SM6_LSB _u(14) -#define PIO_IRQ1_INTS_SM6_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ1_INTS_SM5 -#define PIO_IRQ1_INTS_SM5_RESET _u(0x0) -#define PIO_IRQ1_INTS_SM5_BITS _u(0x00002000) -#define PIO_IRQ1_INTS_SM5_MSB _u(13) -#define PIO_IRQ1_INTS_SM5_LSB _u(13) -#define PIO_IRQ1_INTS_SM5_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ1_INTS_SM4 -#define PIO_IRQ1_INTS_SM4_RESET _u(0x0) -#define PIO_IRQ1_INTS_SM4_BITS _u(0x00001000) -#define PIO_IRQ1_INTS_SM4_MSB _u(12) -#define PIO_IRQ1_INTS_SM4_LSB _u(12) -#define PIO_IRQ1_INTS_SM4_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ1_INTS_SM3 -#define PIO_IRQ1_INTS_SM3_RESET _u(0x0) -#define PIO_IRQ1_INTS_SM3_BITS _u(0x00000800) -#define PIO_IRQ1_INTS_SM3_MSB _u(11) -#define PIO_IRQ1_INTS_SM3_LSB _u(11) -#define PIO_IRQ1_INTS_SM3_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ1_INTS_SM2 -#define PIO_IRQ1_INTS_SM2_RESET _u(0x0) -#define PIO_IRQ1_INTS_SM2_BITS _u(0x00000400) -#define PIO_IRQ1_INTS_SM2_MSB _u(10) -#define PIO_IRQ1_INTS_SM2_LSB _u(10) -#define PIO_IRQ1_INTS_SM2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ1_INTS_SM1 -#define PIO_IRQ1_INTS_SM1_RESET _u(0x0) -#define PIO_IRQ1_INTS_SM1_BITS _u(0x00000200) -#define PIO_IRQ1_INTS_SM1_MSB _u(9) -#define PIO_IRQ1_INTS_SM1_LSB _u(9) -#define PIO_IRQ1_INTS_SM1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ1_INTS_SM0 -#define PIO_IRQ1_INTS_SM0_RESET _u(0x0) -#define PIO_IRQ1_INTS_SM0_BITS _u(0x00000100) -#define PIO_IRQ1_INTS_SM0_MSB _u(8) -#define PIO_IRQ1_INTS_SM0_LSB _u(8) -#define PIO_IRQ1_INTS_SM0_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ1_INTS_SM3_TXNFULL -#define PIO_IRQ1_INTS_SM3_TXNFULL_RESET _u(0x0) -#define PIO_IRQ1_INTS_SM3_TXNFULL_BITS _u(0x00000080) -#define PIO_IRQ1_INTS_SM3_TXNFULL_MSB _u(7) -#define PIO_IRQ1_INTS_SM3_TXNFULL_LSB _u(7) -#define PIO_IRQ1_INTS_SM3_TXNFULL_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ1_INTS_SM2_TXNFULL -#define PIO_IRQ1_INTS_SM2_TXNFULL_RESET _u(0x0) -#define PIO_IRQ1_INTS_SM2_TXNFULL_BITS _u(0x00000040) -#define PIO_IRQ1_INTS_SM2_TXNFULL_MSB _u(6) -#define PIO_IRQ1_INTS_SM2_TXNFULL_LSB _u(6) -#define PIO_IRQ1_INTS_SM2_TXNFULL_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ1_INTS_SM1_TXNFULL -#define PIO_IRQ1_INTS_SM1_TXNFULL_RESET _u(0x0) -#define PIO_IRQ1_INTS_SM1_TXNFULL_BITS _u(0x00000020) -#define PIO_IRQ1_INTS_SM1_TXNFULL_MSB _u(5) -#define PIO_IRQ1_INTS_SM1_TXNFULL_LSB _u(5) -#define PIO_IRQ1_INTS_SM1_TXNFULL_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ1_INTS_SM0_TXNFULL -#define PIO_IRQ1_INTS_SM0_TXNFULL_RESET _u(0x0) -#define PIO_IRQ1_INTS_SM0_TXNFULL_BITS _u(0x00000010) -#define PIO_IRQ1_INTS_SM0_TXNFULL_MSB _u(4) -#define PIO_IRQ1_INTS_SM0_TXNFULL_LSB _u(4) -#define PIO_IRQ1_INTS_SM0_TXNFULL_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ1_INTS_SM3_RXNEMPTY -#define PIO_IRQ1_INTS_SM3_RXNEMPTY_RESET _u(0x0) -#define PIO_IRQ1_INTS_SM3_RXNEMPTY_BITS _u(0x00000008) -#define PIO_IRQ1_INTS_SM3_RXNEMPTY_MSB _u(3) -#define PIO_IRQ1_INTS_SM3_RXNEMPTY_LSB _u(3) -#define PIO_IRQ1_INTS_SM3_RXNEMPTY_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ1_INTS_SM2_RXNEMPTY -#define PIO_IRQ1_INTS_SM2_RXNEMPTY_RESET _u(0x0) -#define PIO_IRQ1_INTS_SM2_RXNEMPTY_BITS _u(0x00000004) -#define PIO_IRQ1_INTS_SM2_RXNEMPTY_MSB _u(2) -#define PIO_IRQ1_INTS_SM2_RXNEMPTY_LSB _u(2) -#define PIO_IRQ1_INTS_SM2_RXNEMPTY_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ1_INTS_SM1_RXNEMPTY -#define PIO_IRQ1_INTS_SM1_RXNEMPTY_RESET _u(0x0) -#define PIO_IRQ1_INTS_SM1_RXNEMPTY_BITS _u(0x00000002) -#define PIO_IRQ1_INTS_SM1_RXNEMPTY_MSB _u(1) -#define PIO_IRQ1_INTS_SM1_RXNEMPTY_LSB _u(1) -#define PIO_IRQ1_INTS_SM1_RXNEMPTY_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PIO_IRQ1_INTS_SM0_RXNEMPTY -#define PIO_IRQ1_INTS_SM0_RXNEMPTY_RESET _u(0x0) -#define PIO_IRQ1_INTS_SM0_RXNEMPTY_BITS _u(0x00000001) -#define PIO_IRQ1_INTS_SM0_RXNEMPTY_MSB _u(0) -#define PIO_IRQ1_INTS_SM0_RXNEMPTY_LSB _u(0) -#define PIO_IRQ1_INTS_SM0_RXNEMPTY_ACCESS "RO" -// ============================================================================= -#endif // _HARDWARE_REGS_PIO_H - diff --git a/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/pll.h b/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/pll.h deleted file mode 100644 index fdf254d15f..0000000000 --- a/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/pll.h +++ /dev/null @@ -1,199 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -// ============================================================================= -// Register block : PLL -// Version : 1 -// Bus type : apb -// ============================================================================= -#ifndef _HARDWARE_REGS_PLL_H -#define _HARDWARE_REGS_PLL_H -// ============================================================================= -// Register : PLL_CS -// Description : Control and Status -// GENERAL CONSTRAINTS: -// Reference clock frequency min=5MHz, max=800MHz -// Feedback divider min=16, max=320 -// VCO frequency min=750MHz, max=1600MHz -#define PLL_CS_OFFSET _u(0x00000000) -#define PLL_CS_BITS _u(0xc000013f) -#define PLL_CS_RESET _u(0x00000001) -// ----------------------------------------------------------------------------- -// Field : PLL_CS_LOCK -// Description : PLL is locked -#define PLL_CS_LOCK_RESET _u(0x0) -#define PLL_CS_LOCK_BITS _u(0x80000000) -#define PLL_CS_LOCK_MSB _u(31) -#define PLL_CS_LOCK_LSB _u(31) -#define PLL_CS_LOCK_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PLL_CS_LOCK_N -// Description : PLL is not locked -// Ideally this is cleared when PLL lock is seen and this should -// never normally be set -#define PLL_CS_LOCK_N_RESET _u(0x0) -#define PLL_CS_LOCK_N_BITS _u(0x40000000) -#define PLL_CS_LOCK_N_MSB _u(30) -#define PLL_CS_LOCK_N_LSB _u(30) -#define PLL_CS_LOCK_N_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : PLL_CS_BYPASS -// Description : Passes the reference clock to the output instead of the divided -// VCO. The VCO continues to run so the user can switch between -// the reference clock and the divided VCO but the output will -// glitch when doing so. -#define PLL_CS_BYPASS_RESET _u(0x0) -#define PLL_CS_BYPASS_BITS _u(0x00000100) -#define PLL_CS_BYPASS_MSB _u(8) -#define PLL_CS_BYPASS_LSB _u(8) -#define PLL_CS_BYPASS_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PLL_CS_REFDIV -// Description : Divides the PLL input reference clock. -// Behaviour is undefined for div=0. -// PLL output will be unpredictable during refdiv changes, wait -// for lock=1 before using it. -#define PLL_CS_REFDIV_RESET _u(0x01) -#define PLL_CS_REFDIV_BITS _u(0x0000003f) -#define PLL_CS_REFDIV_MSB _u(5) -#define PLL_CS_REFDIV_LSB _u(0) -#define PLL_CS_REFDIV_ACCESS "RW" -// ============================================================================= -// Register : PLL_PWR -// Description : Controls the PLL power modes. -#define PLL_PWR_OFFSET _u(0x00000004) -#define PLL_PWR_BITS _u(0x0000002d) -#define PLL_PWR_RESET _u(0x0000002d) -// ----------------------------------------------------------------------------- -// Field : PLL_PWR_VCOPD -// Description : PLL VCO powerdown -// To save power set high when PLL output not required or -// bypass=1. -#define PLL_PWR_VCOPD_RESET _u(0x1) -#define PLL_PWR_VCOPD_BITS _u(0x00000020) -#define PLL_PWR_VCOPD_MSB _u(5) -#define PLL_PWR_VCOPD_LSB _u(5) -#define PLL_PWR_VCOPD_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PLL_PWR_POSTDIVPD -// Description : PLL post divider powerdown -// To save power set high when PLL output not required or -// bypass=1. -#define PLL_PWR_POSTDIVPD_RESET _u(0x1) -#define PLL_PWR_POSTDIVPD_BITS _u(0x00000008) -#define PLL_PWR_POSTDIVPD_MSB _u(3) -#define PLL_PWR_POSTDIVPD_LSB _u(3) -#define PLL_PWR_POSTDIVPD_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PLL_PWR_DSMPD -// Description : PLL DSM powerdown -// Nothing is achieved by setting this low. -#define PLL_PWR_DSMPD_RESET _u(0x1) -#define PLL_PWR_DSMPD_BITS _u(0x00000004) -#define PLL_PWR_DSMPD_MSB _u(2) -#define PLL_PWR_DSMPD_LSB _u(2) -#define PLL_PWR_DSMPD_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PLL_PWR_PD -// Description : PLL powerdown -// To save power set high when PLL output not required. -#define PLL_PWR_PD_RESET _u(0x1) -#define PLL_PWR_PD_BITS _u(0x00000001) -#define PLL_PWR_PD_MSB _u(0) -#define PLL_PWR_PD_LSB _u(0) -#define PLL_PWR_PD_ACCESS "RW" -// ============================================================================= -// Register : PLL_FBDIV_INT -// Description : Feedback divisor -// (note: this PLL does not support fractional division) -// see ctrl reg description for constraints -#define PLL_FBDIV_INT_OFFSET _u(0x00000008) -#define PLL_FBDIV_INT_BITS _u(0x00000fff) -#define PLL_FBDIV_INT_RESET _u(0x00000000) -#define PLL_FBDIV_INT_MSB _u(11) -#define PLL_FBDIV_INT_LSB _u(0) -#define PLL_FBDIV_INT_ACCESS "RW" -// ============================================================================= -// Register : PLL_PRIM -// Description : Controls the PLL post dividers for the primary output -// (note: this PLL does not have a secondary output) -// the primary output is driven from VCO divided by -// postdiv1*postdiv2 -#define PLL_PRIM_OFFSET _u(0x0000000c) -#define PLL_PRIM_BITS _u(0x00077000) -#define PLL_PRIM_RESET _u(0x00077000) -// ----------------------------------------------------------------------------- -// Field : PLL_PRIM_POSTDIV1 -// Description : divide by 1-7 -#define PLL_PRIM_POSTDIV1_RESET _u(0x7) -#define PLL_PRIM_POSTDIV1_BITS _u(0x00070000) -#define PLL_PRIM_POSTDIV1_MSB _u(18) -#define PLL_PRIM_POSTDIV1_LSB _u(16) -#define PLL_PRIM_POSTDIV1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PLL_PRIM_POSTDIV2 -// Description : divide by 1-7 -#define PLL_PRIM_POSTDIV2_RESET _u(0x7) -#define PLL_PRIM_POSTDIV2_BITS _u(0x00007000) -#define PLL_PRIM_POSTDIV2_MSB _u(14) -#define PLL_PRIM_POSTDIV2_LSB _u(12) -#define PLL_PRIM_POSTDIV2_ACCESS "RW" -// ============================================================================= -// Register : PLL_INTR -// Description : Raw Interrupts -#define PLL_INTR_OFFSET _u(0x00000010) -#define PLL_INTR_BITS _u(0x00000001) -#define PLL_INTR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : PLL_INTR_LOCK_N_STICKY -#define PLL_INTR_LOCK_N_STICKY_RESET _u(0x0) -#define PLL_INTR_LOCK_N_STICKY_BITS _u(0x00000001) -#define PLL_INTR_LOCK_N_STICKY_MSB _u(0) -#define PLL_INTR_LOCK_N_STICKY_LSB _u(0) -#define PLL_INTR_LOCK_N_STICKY_ACCESS "WC" -// ============================================================================= -// Register : PLL_INTE -// Description : Interrupt Enable -#define PLL_INTE_OFFSET _u(0x00000014) -#define PLL_INTE_BITS _u(0x00000001) -#define PLL_INTE_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : PLL_INTE_LOCK_N_STICKY -#define PLL_INTE_LOCK_N_STICKY_RESET _u(0x0) -#define PLL_INTE_LOCK_N_STICKY_BITS _u(0x00000001) -#define PLL_INTE_LOCK_N_STICKY_MSB _u(0) -#define PLL_INTE_LOCK_N_STICKY_LSB _u(0) -#define PLL_INTE_LOCK_N_STICKY_ACCESS "RW" -// ============================================================================= -// Register : PLL_INTF -// Description : Interrupt Force -#define PLL_INTF_OFFSET _u(0x00000018) -#define PLL_INTF_BITS _u(0x00000001) -#define PLL_INTF_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : PLL_INTF_LOCK_N_STICKY -#define PLL_INTF_LOCK_N_STICKY_RESET _u(0x0) -#define PLL_INTF_LOCK_N_STICKY_BITS _u(0x00000001) -#define PLL_INTF_LOCK_N_STICKY_MSB _u(0) -#define PLL_INTF_LOCK_N_STICKY_LSB _u(0) -#define PLL_INTF_LOCK_N_STICKY_ACCESS "RW" -// ============================================================================= -// Register : PLL_INTS -// Description : Interrupt status after masking & forcing -#define PLL_INTS_OFFSET _u(0x0000001c) -#define PLL_INTS_BITS _u(0x00000001) -#define PLL_INTS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : PLL_INTS_LOCK_N_STICKY -#define PLL_INTS_LOCK_N_STICKY_RESET _u(0x0) -#define PLL_INTS_LOCK_N_STICKY_BITS _u(0x00000001) -#define PLL_INTS_LOCK_N_STICKY_MSB _u(0) -#define PLL_INTS_LOCK_N_STICKY_LSB _u(0) -#define PLL_INTS_LOCK_N_STICKY_ACCESS "RO" -// ============================================================================= -#endif // _HARDWARE_REGS_PLL_H - diff --git a/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/powman.h b/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/powman.h deleted file mode 100644 index edfbabbcc1..0000000000 --- a/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/powman.h +++ /dev/null @@ -1,2194 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -// ============================================================================= -// Register block : POWMAN -// Version : 1 -// Bus type : apb -// Description : Controls vreg, bor, lposc, chip resets & xosc startup, -// powman and provides scratch register for general use and for -// bootcode use -// ============================================================================= -#ifndef _HARDWARE_REGS_POWMAN_H -#define _HARDWARE_REGS_POWMAN_H -// ============================================================================= -// Register : POWMAN_BADPASSWD -// Description : Indicates a bad password has been used -#define POWMAN_BADPASSWD_OFFSET _u(0x00000000) -#define POWMAN_BADPASSWD_BITS _u(0x00000001) -#define POWMAN_BADPASSWD_RESET _u(0x00000000) -#define POWMAN_BADPASSWD_MSB _u(0) -#define POWMAN_BADPASSWD_LSB _u(0) -#define POWMAN_BADPASSWD_ACCESS "WC" -// ============================================================================= -// Register : POWMAN_VREG_CTRL -// Description : Voltage Regulator Control -#define POWMAN_VREG_CTRL_OFFSET _u(0x00000004) -#define POWMAN_VREG_CTRL_BITS _u(0x0000b170) -#define POWMAN_VREG_CTRL_RESET _u(0x00008050) -// ----------------------------------------------------------------------------- -// Field : POWMAN_VREG_CTRL_RST_N -// Description : returns the regulator to its startup settings -// 0 - reset -// 1 - not reset (default) -#define POWMAN_VREG_CTRL_RST_N_RESET _u(0x1) -#define POWMAN_VREG_CTRL_RST_N_BITS _u(0x00008000) -#define POWMAN_VREG_CTRL_RST_N_MSB _u(15) -#define POWMAN_VREG_CTRL_RST_N_LSB _u(15) -#define POWMAN_VREG_CTRL_RST_N_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : POWMAN_VREG_CTRL_UNLOCK -// Description : unlocks the VREG control interface after power up -// 0 - Locked (default) -// 1 - Unlocked -// It cannot be relocked when it is unlocked. -#define POWMAN_VREG_CTRL_UNLOCK_RESET _u(0x0) -#define POWMAN_VREG_CTRL_UNLOCK_BITS _u(0x00002000) -#define POWMAN_VREG_CTRL_UNLOCK_MSB _u(13) -#define POWMAN_VREG_CTRL_UNLOCK_LSB _u(13) -#define POWMAN_VREG_CTRL_UNLOCK_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : POWMAN_VREG_CTRL_ISOLATE -// Description : isolates the VREG control interface -// 0 - not isolated (default) -// 1 - isolated -#define POWMAN_VREG_CTRL_ISOLATE_RESET _u(0x0) -#define POWMAN_VREG_CTRL_ISOLATE_BITS _u(0x00001000) -#define POWMAN_VREG_CTRL_ISOLATE_MSB _u(12) -#define POWMAN_VREG_CTRL_ISOLATE_LSB _u(12) -#define POWMAN_VREG_CTRL_ISOLATE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : POWMAN_VREG_CTRL_DISABLE_VOLTAGE_LIMIT -// Description : 0=not disabled, 1=enabled -#define POWMAN_VREG_CTRL_DISABLE_VOLTAGE_LIMIT_RESET _u(0x0) -#define POWMAN_VREG_CTRL_DISABLE_VOLTAGE_LIMIT_BITS _u(0x00000100) -#define POWMAN_VREG_CTRL_DISABLE_VOLTAGE_LIMIT_MSB _u(8) -#define POWMAN_VREG_CTRL_DISABLE_VOLTAGE_LIMIT_LSB _u(8) -#define POWMAN_VREG_CTRL_DISABLE_VOLTAGE_LIMIT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : POWMAN_VREG_CTRL_HT_TH -// Description : high temperature protection threshold -// regulator power transistors are disabled when junction -// temperature exceeds threshold -// 000 - 100C -// 001 - 105C -// 010 - 110C -// 011 - 115C -// 100 - 120C -// 101 - 125C -// 110 - 135C -// 111 - 150C -#define POWMAN_VREG_CTRL_HT_TH_RESET _u(0x5) -#define POWMAN_VREG_CTRL_HT_TH_BITS _u(0x00000070) -#define POWMAN_VREG_CTRL_HT_TH_MSB _u(6) -#define POWMAN_VREG_CTRL_HT_TH_LSB _u(4) -#define POWMAN_VREG_CTRL_HT_TH_ACCESS "RW" -// ============================================================================= -// Register : POWMAN_VREG_STS -// Description : Voltage Regulator Status -#define POWMAN_VREG_STS_OFFSET _u(0x00000008) -#define POWMAN_VREG_STS_BITS _u(0x00000011) -#define POWMAN_VREG_STS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : POWMAN_VREG_STS_VOUT_OK -// Description : output regulation status -// 0=not in regulation, 1=in regulation -#define POWMAN_VREG_STS_VOUT_OK_RESET _u(0x0) -#define POWMAN_VREG_STS_VOUT_OK_BITS _u(0x00000010) -#define POWMAN_VREG_STS_VOUT_OK_MSB _u(4) -#define POWMAN_VREG_STS_VOUT_OK_LSB _u(4) -#define POWMAN_VREG_STS_VOUT_OK_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : POWMAN_VREG_STS_STARTUP -// Description : startup status -// 0=startup complete, 1=starting up -#define POWMAN_VREG_STS_STARTUP_RESET _u(0x0) -#define POWMAN_VREG_STS_STARTUP_BITS _u(0x00000001) -#define POWMAN_VREG_STS_STARTUP_MSB _u(0) -#define POWMAN_VREG_STS_STARTUP_LSB _u(0) -#define POWMAN_VREG_STS_STARTUP_ACCESS "RO" -// ============================================================================= -// Register : POWMAN_VREG -// Description : Voltage Regulator Settings -#define POWMAN_VREG_OFFSET _u(0x0000000c) -#define POWMAN_VREG_BITS _u(0x000081f2) -#define POWMAN_VREG_RESET _u(0x000000b0) -// ----------------------------------------------------------------------------- -// Field : POWMAN_VREG_UPDATE_IN_PROGRESS -// Description : regulator state is being updated -// writes to the vreg register will be ignored when this field is -// set -#define POWMAN_VREG_UPDATE_IN_PROGRESS_RESET _u(0x0) -#define POWMAN_VREG_UPDATE_IN_PROGRESS_BITS _u(0x00008000) -#define POWMAN_VREG_UPDATE_IN_PROGRESS_MSB _u(15) -#define POWMAN_VREG_UPDATE_IN_PROGRESS_LSB _u(15) -#define POWMAN_VREG_UPDATE_IN_PROGRESS_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : POWMAN_VREG_VSEL -// Description : output voltage select -// the regulator output voltage is limited to 1.3V unless the -// voltage limit -// is disabled using the disable_voltage_limit field in the -// vreg_ctrl register -// 00000 - 0.55V -// 00001 - 0.60V -// 00010 - 0.65V -// 00011 - 0.70V -// 00100 - 0.75V -// 00101 - 0.80V -// 00110 - 0.85V -// 00111 - 0.90V -// 01000 - 0.95V -// 01001 - 1.00V -// 01010 - 1.05V -// 01011 - 1.10V (default) -// 01100 - 1.15V -// 01101 - 1.20V -// 01110 - 1.25V -// 01111 - 1.30V -// 10000 - 1.35V -// 10001 - 1.40V -// 10010 - 1.50V -// 10011 - 1.60V -// 10100 - 1.65V -// 10101 - 1.70V -// 10110 - 1.80V -// 10111 - 1.90V -// 11000 - 2.00V -// 11001 - 2.35V -// 11010 - 2.50V -// 11011 - 2.65V -// 11100 - 2.80V -// 11101 - 3.00V -// 11110 - 3.15V -// 11111 - 3.30V -#define POWMAN_VREG_VSEL_RESET _u(0x0b) -#define POWMAN_VREG_VSEL_BITS _u(0x000001f0) -#define POWMAN_VREG_VSEL_MSB _u(8) -#define POWMAN_VREG_VSEL_LSB _u(4) -#define POWMAN_VREG_VSEL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : POWMAN_VREG_HIZ -// Description : high impedance mode select -// 0=not in high impedance mode, 1=in high impedance mode -#define POWMAN_VREG_HIZ_RESET _u(0x0) -#define POWMAN_VREG_HIZ_BITS _u(0x00000002) -#define POWMAN_VREG_HIZ_MSB _u(1) -#define POWMAN_VREG_HIZ_LSB _u(1) -#define POWMAN_VREG_HIZ_ACCESS "RW" -// ============================================================================= -// Register : POWMAN_VREG_LP_ENTRY -// Description : Voltage Regulator Low Power Entry Settings -#define POWMAN_VREG_LP_ENTRY_OFFSET _u(0x00000010) -#define POWMAN_VREG_LP_ENTRY_BITS _u(0x000001f6) -#define POWMAN_VREG_LP_ENTRY_RESET _u(0x000000b4) -// ----------------------------------------------------------------------------- -// Field : POWMAN_VREG_LP_ENTRY_VSEL -// Description : output voltage select -// the regulator output voltage is limited to 1.3V unless the -// voltage limit -// is disabled using the disable_voltage_limit field in the -// vreg_ctrl register -// 00000 - 0.55V -// 00001 - 0.60V -// 00010 - 0.65V -// 00011 - 0.70V -// 00100 - 0.75V -// 00101 - 0.80V -// 00110 - 0.85V -// 00111 - 0.90V -// 01000 - 0.95V -// 01001 - 1.00V -// 01010 - 1.05V -// 01011 - 1.10V (default) -// 01100 - 1.15V -// 01101 - 1.20V -// 01110 - 1.25V -// 01111 - 1.30V -// 10000 - 1.35V -// 10001 - 1.40V -// 10010 - 1.50V -// 10011 - 1.60V -// 10100 - 1.65V -// 10101 - 1.70V -// 10110 - 1.80V -// 10111 - 1.90V -// 11000 - 2.00V -// 11001 - 2.35V -// 11010 - 2.50V -// 11011 - 2.65V -// 11100 - 2.80V -// 11101 - 3.00V -// 11110 - 3.15V -// 11111 - 3.30V -#define POWMAN_VREG_LP_ENTRY_VSEL_RESET _u(0x0b) -#define POWMAN_VREG_LP_ENTRY_VSEL_BITS _u(0x000001f0) -#define POWMAN_VREG_LP_ENTRY_VSEL_MSB _u(8) -#define POWMAN_VREG_LP_ENTRY_VSEL_LSB _u(4) -#define POWMAN_VREG_LP_ENTRY_VSEL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : POWMAN_VREG_LP_ENTRY_MODE -// Description : selects either normal (switching) mode or low power (linear) -// mode -// low power mode can only be selected for output voltages up to -// 1.3V -// 0 = normal mode (switching) -// 1 = low power mode (linear) -#define POWMAN_VREG_LP_ENTRY_MODE_RESET _u(0x1) -#define POWMAN_VREG_LP_ENTRY_MODE_BITS _u(0x00000004) -#define POWMAN_VREG_LP_ENTRY_MODE_MSB _u(2) -#define POWMAN_VREG_LP_ENTRY_MODE_LSB _u(2) -#define POWMAN_VREG_LP_ENTRY_MODE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : POWMAN_VREG_LP_ENTRY_HIZ -// Description : high impedance mode select -// 0=not in high impedance mode, 1=in high impedance mode -#define POWMAN_VREG_LP_ENTRY_HIZ_RESET _u(0x0) -#define POWMAN_VREG_LP_ENTRY_HIZ_BITS _u(0x00000002) -#define POWMAN_VREG_LP_ENTRY_HIZ_MSB _u(1) -#define POWMAN_VREG_LP_ENTRY_HIZ_LSB _u(1) -#define POWMAN_VREG_LP_ENTRY_HIZ_ACCESS "RW" -// ============================================================================= -// Register : POWMAN_VREG_LP_EXIT -// Description : Voltage Regulator Low Power Exit Settings -#define POWMAN_VREG_LP_EXIT_OFFSET _u(0x00000014) -#define POWMAN_VREG_LP_EXIT_BITS _u(0x000001f6) -#define POWMAN_VREG_LP_EXIT_RESET _u(0x000000b0) -// ----------------------------------------------------------------------------- -// Field : POWMAN_VREG_LP_EXIT_VSEL -// Description : output voltage select -// the regulator output voltage is limited to 1.3V unless the -// voltage limit -// is disabled using the disable_voltage_limit field in the -// vreg_ctrl register -// 00000 - 0.55V -// 00001 - 0.60V -// 00010 - 0.65V -// 00011 - 0.70V -// 00100 - 0.75V -// 00101 - 0.80V -// 00110 - 0.85V -// 00111 - 0.90V -// 01000 - 0.95V -// 01001 - 1.00V -// 01010 - 1.05V -// 01011 - 1.10V (default) -// 01100 - 1.15V -// 01101 - 1.20V -// 01110 - 1.25V -// 01111 - 1.30V -// 10000 - 1.35V -// 10001 - 1.40V -// 10010 - 1.50V -// 10011 - 1.60V -// 10100 - 1.65V -// 10101 - 1.70V -// 10110 - 1.80V -// 10111 - 1.90V -// 11000 - 2.00V -// 11001 - 2.35V -// 11010 - 2.50V -// 11011 - 2.65V -// 11100 - 2.80V -// 11101 - 3.00V -// 11110 - 3.15V -// 11111 - 3.30V -#define POWMAN_VREG_LP_EXIT_VSEL_RESET _u(0x0b) -#define POWMAN_VREG_LP_EXIT_VSEL_BITS _u(0x000001f0) -#define POWMAN_VREG_LP_EXIT_VSEL_MSB _u(8) -#define POWMAN_VREG_LP_EXIT_VSEL_LSB _u(4) -#define POWMAN_VREG_LP_EXIT_VSEL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : POWMAN_VREG_LP_EXIT_MODE -// Description : selects either normal (switching) mode or low power (linear) -// mode -// low power mode can only be selected for output voltages up to -// 1.3V -// 0 = normal mode (switching) -// 1 = low power mode (linear) -#define POWMAN_VREG_LP_EXIT_MODE_RESET _u(0x0) -#define POWMAN_VREG_LP_EXIT_MODE_BITS _u(0x00000004) -#define POWMAN_VREG_LP_EXIT_MODE_MSB _u(2) -#define POWMAN_VREG_LP_EXIT_MODE_LSB _u(2) -#define POWMAN_VREG_LP_EXIT_MODE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : POWMAN_VREG_LP_EXIT_HIZ -// Description : high impedance mode select -// 0=not in high impedance mode, 1=in high impedance mode -#define POWMAN_VREG_LP_EXIT_HIZ_RESET _u(0x0) -#define POWMAN_VREG_LP_EXIT_HIZ_BITS _u(0x00000002) -#define POWMAN_VREG_LP_EXIT_HIZ_MSB _u(1) -#define POWMAN_VREG_LP_EXIT_HIZ_LSB _u(1) -#define POWMAN_VREG_LP_EXIT_HIZ_ACCESS "RW" -// ============================================================================= -// Register : POWMAN_BOD_CTRL -// Description : Brown-out Detection Control -#define POWMAN_BOD_CTRL_OFFSET _u(0x00000018) -#define POWMAN_BOD_CTRL_BITS _u(0x00001000) -#define POWMAN_BOD_CTRL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : POWMAN_BOD_CTRL_ISOLATE -// Description : isolates the brown-out detection control interface -// 0 - not isolated (default) -// 1 - isolated -#define POWMAN_BOD_CTRL_ISOLATE_RESET _u(0x0) -#define POWMAN_BOD_CTRL_ISOLATE_BITS _u(0x00001000) -#define POWMAN_BOD_CTRL_ISOLATE_MSB _u(12) -#define POWMAN_BOD_CTRL_ISOLATE_LSB _u(12) -#define POWMAN_BOD_CTRL_ISOLATE_ACCESS "RW" -// ============================================================================= -// Register : POWMAN_BOD -// Description : Brown-out Detection Settings -#define POWMAN_BOD_OFFSET _u(0x0000001c) -#define POWMAN_BOD_BITS _u(0x000001f1) -#define POWMAN_BOD_RESET _u(0x000000b1) -// ----------------------------------------------------------------------------- -// Field : POWMAN_BOD_VSEL -// Description : threshold select -// 00000 - 0.473V -// 00001 - 0.516V -// 00010 - 0.559V -// 00011 - 0.602V -// 00100 - 0.645VS -// 00101 - 0.688V -// 00110 - 0.731V -// 00111 - 0.774V -// 01000 - 0.817V -// 01001 - 0.860V (default) -// 01010 - 0.903V -// 01011 - 0.946V -// 01100 - 0.989V -// 01101 - 1.032V -// 01110 - 1.075V -// 01111 - 1.118V -// 10000 - 1.161 -// 10001 - 1.204V -#define POWMAN_BOD_VSEL_RESET _u(0x0b) -#define POWMAN_BOD_VSEL_BITS _u(0x000001f0) -#define POWMAN_BOD_VSEL_MSB _u(8) -#define POWMAN_BOD_VSEL_LSB _u(4) -#define POWMAN_BOD_VSEL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : POWMAN_BOD_EN -// Description : enable brown-out detection -// 0=not enabled, 1=enabled -#define POWMAN_BOD_EN_RESET _u(0x1) -#define POWMAN_BOD_EN_BITS _u(0x00000001) -#define POWMAN_BOD_EN_MSB _u(0) -#define POWMAN_BOD_EN_LSB _u(0) -#define POWMAN_BOD_EN_ACCESS "RW" -// ============================================================================= -// Register : POWMAN_BOD_LP_ENTRY -// Description : Brown-out Detection Low Power Entry Settings -#define POWMAN_BOD_LP_ENTRY_OFFSET _u(0x00000020) -#define POWMAN_BOD_LP_ENTRY_BITS _u(0x000001f1) -#define POWMAN_BOD_LP_ENTRY_RESET _u(0x000000b0) -// ----------------------------------------------------------------------------- -// Field : POWMAN_BOD_LP_ENTRY_VSEL -// Description : threshold select -// 00000 - 0.473V -// 00001 - 0.516V -// 00010 - 0.559V -// 00011 - 0.602V -// 00100 - 0.645VS -// 00101 - 0.688V -// 00110 - 0.731V -// 00111 - 0.774V -// 01000 - 0.817V -// 01001 - 0.860V (default) -// 01010 - 0.903V -// 01011 - 0.946V -// 01100 - 0.989V -// 01101 - 1.032V -// 01110 - 1.075V -// 01111 - 1.118V -// 10000 - 1.161 -// 10001 - 1.204V -#define POWMAN_BOD_LP_ENTRY_VSEL_RESET _u(0x0b) -#define POWMAN_BOD_LP_ENTRY_VSEL_BITS _u(0x000001f0) -#define POWMAN_BOD_LP_ENTRY_VSEL_MSB _u(8) -#define POWMAN_BOD_LP_ENTRY_VSEL_LSB _u(4) -#define POWMAN_BOD_LP_ENTRY_VSEL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : POWMAN_BOD_LP_ENTRY_EN -// Description : enable brown-out detection -// 0=not enabled, 1=enabled -#define POWMAN_BOD_LP_ENTRY_EN_RESET _u(0x0) -#define POWMAN_BOD_LP_ENTRY_EN_BITS _u(0x00000001) -#define POWMAN_BOD_LP_ENTRY_EN_MSB _u(0) -#define POWMAN_BOD_LP_ENTRY_EN_LSB _u(0) -#define POWMAN_BOD_LP_ENTRY_EN_ACCESS "RW" -// ============================================================================= -// Register : POWMAN_BOD_LP_EXIT -// Description : Brown-out Detection Low Power Exit Settings -#define POWMAN_BOD_LP_EXIT_OFFSET _u(0x00000024) -#define POWMAN_BOD_LP_EXIT_BITS _u(0x000001f1) -#define POWMAN_BOD_LP_EXIT_RESET _u(0x000000b1) -// ----------------------------------------------------------------------------- -// Field : POWMAN_BOD_LP_EXIT_VSEL -// Description : threshold select -// 00000 - 0.473V -// 00001 - 0.516V -// 00010 - 0.559V -// 00011 - 0.602V -// 00100 - 0.645VS -// 00101 - 0.688V -// 00110 - 0.731V -// 00111 - 0.774V -// 01000 - 0.817V -// 01001 - 0.860V (default) -// 01010 - 0.903V -// 01011 - 0.946V -// 01100 - 0.989V -// 01101 - 1.032V -// 01110 - 1.075V -// 01111 - 1.118V -// 10000 - 1.161 -// 10001 - 1.204V -#define POWMAN_BOD_LP_EXIT_VSEL_RESET _u(0x0b) -#define POWMAN_BOD_LP_EXIT_VSEL_BITS _u(0x000001f0) -#define POWMAN_BOD_LP_EXIT_VSEL_MSB _u(8) -#define POWMAN_BOD_LP_EXIT_VSEL_LSB _u(4) -#define POWMAN_BOD_LP_EXIT_VSEL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : POWMAN_BOD_LP_EXIT_EN -// Description : enable brown-out detection -// 0=not enabled, 1=enabled -#define POWMAN_BOD_LP_EXIT_EN_RESET _u(0x1) -#define POWMAN_BOD_LP_EXIT_EN_BITS _u(0x00000001) -#define POWMAN_BOD_LP_EXIT_EN_MSB _u(0) -#define POWMAN_BOD_LP_EXIT_EN_LSB _u(0) -#define POWMAN_BOD_LP_EXIT_EN_ACCESS "RW" -// ============================================================================= -// Register : POWMAN_LPOSC -// Description : Low power oscillator control register. -#define POWMAN_LPOSC_OFFSET _u(0x00000028) -#define POWMAN_LPOSC_BITS _u(0x000003f3) -#define POWMAN_LPOSC_RESET _u(0x00000203) -// ----------------------------------------------------------------------------- -// Field : POWMAN_LPOSC_TRIM -// Description : Frequency trim - the trim step is typically 1% of the reset -// frequency, but can be up to 3% -#define POWMAN_LPOSC_TRIM_RESET _u(0x20) -#define POWMAN_LPOSC_TRIM_BITS _u(0x000003f0) -#define POWMAN_LPOSC_TRIM_MSB _u(9) -#define POWMAN_LPOSC_TRIM_LSB _u(4) -#define POWMAN_LPOSC_TRIM_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : POWMAN_LPOSC_MODE -// Description : This feature has been removed -#define POWMAN_LPOSC_MODE_RESET _u(0x3) -#define POWMAN_LPOSC_MODE_BITS _u(0x00000003) -#define POWMAN_LPOSC_MODE_MSB _u(1) -#define POWMAN_LPOSC_MODE_LSB _u(0) -#define POWMAN_LPOSC_MODE_ACCESS "RW" -// ============================================================================= -// Register : POWMAN_CHIP_RESET -// Description : Chip reset control and status -#define POWMAN_CHIP_RESET_OFFSET _u(0x0000002c) -#define POWMAN_CHIP_RESET_BITS _u(0x1fef0011) -#define POWMAN_CHIP_RESET_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_RSM -// Description : Last reset was a watchdog timeout which was configured to reset -// the power-on state machine -// This resets: -// double_tap flag no -// DP no -// RPAP no -// rescue_flag no -// timer no -// powman no -// swcore no -// psm yes -// and does not change the power state -#define POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_RSM_RESET _u(0x0) -#define POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_RSM_BITS _u(0x10000000) -#define POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_RSM_MSB _u(28) -#define POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_RSM_LSB _u(28) -#define POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_RSM_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : POWMAN_CHIP_RESET_HAD_HZD_SYS_RESET_REQ -// Description : Last reset was a system reset from the hazard debugger -// This resets: -// double_tap flag no -// DP no -// RPAP no -// rescue_flag no -// timer no -// powman no -// swcore no -// psm yes -// and does not change the power state -#define POWMAN_CHIP_RESET_HAD_HZD_SYS_RESET_REQ_RESET _u(0x0) -#define POWMAN_CHIP_RESET_HAD_HZD_SYS_RESET_REQ_BITS _u(0x08000000) -#define POWMAN_CHIP_RESET_HAD_HZD_SYS_RESET_REQ_MSB _u(27) -#define POWMAN_CHIP_RESET_HAD_HZD_SYS_RESET_REQ_LSB _u(27) -#define POWMAN_CHIP_RESET_HAD_HZD_SYS_RESET_REQ_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : POWMAN_CHIP_RESET_HAD_GLITCH_DETECT -// Description : Last reset was due to a power supply glitch -// This resets: -// double_tap flag no -// DP no -// RPAP no -// rescue_flag no -// timer no -// powman no -// swcore no -// psm yes -// and does not change the power state -#define POWMAN_CHIP_RESET_HAD_GLITCH_DETECT_RESET _u(0x0) -#define POWMAN_CHIP_RESET_HAD_GLITCH_DETECT_BITS _u(0x04000000) -#define POWMAN_CHIP_RESET_HAD_GLITCH_DETECT_MSB _u(26) -#define POWMAN_CHIP_RESET_HAD_GLITCH_DETECT_LSB _u(26) -#define POWMAN_CHIP_RESET_HAD_GLITCH_DETECT_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : POWMAN_CHIP_RESET_HAD_SWCORE_PD -// Description : Last reset was a switched core powerdown -// This resets: -// double_tap flag no -// DP no -// RPAP no -// rescue_flag no -// timer no -// powman no -// swcore yes -// psm yes -// then starts the power sequencer -#define POWMAN_CHIP_RESET_HAD_SWCORE_PD_RESET _u(0x0) -#define POWMAN_CHIP_RESET_HAD_SWCORE_PD_BITS _u(0x02000000) -#define POWMAN_CHIP_RESET_HAD_SWCORE_PD_MSB _u(25) -#define POWMAN_CHIP_RESET_HAD_SWCORE_PD_LSB _u(25) -#define POWMAN_CHIP_RESET_HAD_SWCORE_PD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_SWCORE -// Description : Last reset was a watchdog timeout which was configured to reset -// the switched-core -// This resets: -// double_tap flag no -// DP no -// RPAP no -// rescue_flag no -// timer no -// powman no -// swcore yes -// psm yes -// then starts the power sequencer -#define POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_SWCORE_RESET _u(0x0) -#define POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_SWCORE_BITS _u(0x01000000) -#define POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_SWCORE_MSB _u(24) -#define POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_SWCORE_LSB _u(24) -#define POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_SWCORE_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_POWMAN -// Description : Last reset was a watchdog timeout which was configured to reset -// the power manager -// This resets: -// double_tap flag no -// DP no -// RPAP no -// rescue_flag no -// timer yes -// powman yes -// swcore yes -// psm yes -// then starts the power sequencer -#define POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_POWMAN_RESET _u(0x0) -#define POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_POWMAN_BITS _u(0x00800000) -#define POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_POWMAN_MSB _u(23) -#define POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_POWMAN_LSB _u(23) -#define POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_POWMAN_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_POWMAN_ASYNC -// Description : Last reset was a watchdog timeout which was configured to reset -// the power manager asynchronously -// This resets: -// double_tap flag no -// DP no -// RPAP no -// rescue_flag no -// timer yes -// powman yes -// swcore yes -// psm yes -// then starts the power sequencer -#define POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_POWMAN_ASYNC_RESET _u(0x0) -#define POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_POWMAN_ASYNC_BITS _u(0x00400000) -#define POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_POWMAN_ASYNC_MSB _u(22) -#define POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_POWMAN_ASYNC_LSB _u(22) -#define POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_POWMAN_ASYNC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : POWMAN_CHIP_RESET_HAD_RESCUE -// Description : Last reset was a rescue reset from the debugger -// This resets: -// double_tap flag no -// DP no -// RPAP no -// rescue_flag no, it sets this flag -// timer yes -// powman yes -// swcore yes -// psm yes -// then starts the power sequencer -#define POWMAN_CHIP_RESET_HAD_RESCUE_RESET _u(0x0) -#define POWMAN_CHIP_RESET_HAD_RESCUE_BITS _u(0x00200000) -#define POWMAN_CHIP_RESET_HAD_RESCUE_MSB _u(21) -#define POWMAN_CHIP_RESET_HAD_RESCUE_LSB _u(21) -#define POWMAN_CHIP_RESET_HAD_RESCUE_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : POWMAN_CHIP_RESET_HAD_DP_RESET_REQ -// Description : Last reset was an reset request from the arm debugger -// This resets: -// double_tap flag no -// DP no -// RPAP no -// rescue_flag yes -// timer yes -// powman yes -// swcore yes -// psm yes -// then starts the power sequencer -#define POWMAN_CHIP_RESET_HAD_DP_RESET_REQ_RESET _u(0x0) -#define POWMAN_CHIP_RESET_HAD_DP_RESET_REQ_BITS _u(0x00080000) -#define POWMAN_CHIP_RESET_HAD_DP_RESET_REQ_MSB _u(19) -#define POWMAN_CHIP_RESET_HAD_DP_RESET_REQ_LSB _u(19) -#define POWMAN_CHIP_RESET_HAD_DP_RESET_REQ_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : POWMAN_CHIP_RESET_HAD_RUN_LOW -// Description : Last reset was from the RUN pin -// This resets: -// double_tap flag no -// DP yes -// RPAP yes -// rescue_flag yes -// timer yes -// powman yes -// swcore yes -// psm yes -// then starts the power sequencer -#define POWMAN_CHIP_RESET_HAD_RUN_LOW_RESET _u(0x0) -#define POWMAN_CHIP_RESET_HAD_RUN_LOW_BITS _u(0x00040000) -#define POWMAN_CHIP_RESET_HAD_RUN_LOW_MSB _u(18) -#define POWMAN_CHIP_RESET_HAD_RUN_LOW_LSB _u(18) -#define POWMAN_CHIP_RESET_HAD_RUN_LOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : POWMAN_CHIP_RESET_HAD_BOR -// Description : Last reset was from the brown-out detection block -// This resets: -// double_tap flag yes -// DP yes -// RPAP yes -// rescue_flag yes -// timer yes -// powman yes -// swcore yes -// psm yes -// then starts the power sequencer -#define POWMAN_CHIP_RESET_HAD_BOR_RESET _u(0x0) -#define POWMAN_CHIP_RESET_HAD_BOR_BITS _u(0x00020000) -#define POWMAN_CHIP_RESET_HAD_BOR_MSB _u(17) -#define POWMAN_CHIP_RESET_HAD_BOR_LSB _u(17) -#define POWMAN_CHIP_RESET_HAD_BOR_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : POWMAN_CHIP_RESET_HAD_POR -// Description : Last reset was from the power-on reset -// This resets: -// double_tap flag yes -// DP yes -// RPAP yes -// rescue_flag yes -// timer yes -// powman yes -// swcore yes -// psm yes -// then starts the power sequencer -#define POWMAN_CHIP_RESET_HAD_POR_RESET _u(0x0) -#define POWMAN_CHIP_RESET_HAD_POR_BITS _u(0x00010000) -#define POWMAN_CHIP_RESET_HAD_POR_MSB _u(16) -#define POWMAN_CHIP_RESET_HAD_POR_LSB _u(16) -#define POWMAN_CHIP_RESET_HAD_POR_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : POWMAN_CHIP_RESET_RESCUE_FLAG -// Description : This is set by a rescue reset from the RP-AP. -// Its purpose is to halt before the bootrom before booting from -// flash in order to recover from a boot lock-up. -// The debugger can then attach once the bootrom has been halted -// and flash some working code that does not lock up. -#define POWMAN_CHIP_RESET_RESCUE_FLAG_RESET _u(0x0) -#define POWMAN_CHIP_RESET_RESCUE_FLAG_BITS _u(0x00000010) -#define POWMAN_CHIP_RESET_RESCUE_FLAG_MSB _u(4) -#define POWMAN_CHIP_RESET_RESCUE_FLAG_LSB _u(4) -#define POWMAN_CHIP_RESET_RESCUE_FLAG_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : POWMAN_CHIP_RESET_DOUBLE_TAP -// Description : This flag is set by double-tapping RUN. It tells bootcode to go -// into the bootloader. -#define POWMAN_CHIP_RESET_DOUBLE_TAP_RESET _u(0x0) -#define POWMAN_CHIP_RESET_DOUBLE_TAP_BITS _u(0x00000001) -#define POWMAN_CHIP_RESET_DOUBLE_TAP_MSB _u(0) -#define POWMAN_CHIP_RESET_DOUBLE_TAP_LSB _u(0) -#define POWMAN_CHIP_RESET_DOUBLE_TAP_ACCESS "RW" -// ============================================================================= -// Register : POWMAN_WDSEL -// Description : Allows a watchdog reset to reset the internal state of powman -// in addition to the power-on state machine (PSM). -// Note that powman ignores watchdog resets that do not select at -// least the CLOCKS stage or earlier stages in the PSM. If using -// these bits, it's recommended to set PSM_WDSEL to all-ones in -// addition to the desired bits in this register. Failing to -// select CLOCKS or earlier will result in the POWMAN_WDSEL -// register having no effect. -#define POWMAN_WDSEL_OFFSET _u(0x00000030) -#define POWMAN_WDSEL_BITS _u(0x00001111) -#define POWMAN_WDSEL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : POWMAN_WDSEL_RESET_RSM -// Description : If set to 1, a watchdog reset will run the full power-on state -// machine (PSM) sequence -// From a user perspective it is the same as setting -// RSM_WDSEL_PROC_COLD -// From a hardware debug perspective it has the same effect as a -// reset from a glitch detector -#define POWMAN_WDSEL_RESET_RSM_RESET _u(0x0) -#define POWMAN_WDSEL_RESET_RSM_BITS _u(0x00001000) -#define POWMAN_WDSEL_RESET_RSM_MSB _u(12) -#define POWMAN_WDSEL_RESET_RSM_LSB _u(12) -#define POWMAN_WDSEL_RESET_RSM_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : POWMAN_WDSEL_RESET_SWCORE -// Description : If set to 1, a watchdog reset will reset the switched core -// power domain and run the full power-on state machine (PSM) -// sequence -// From a user perspective it is the same as setting -// RSM_WDSEL_PROC_COLD -// From a hardware debug perspective it has the same effect as a -// power-on reset for the switched core power domain -#define POWMAN_WDSEL_RESET_SWCORE_RESET _u(0x0) -#define POWMAN_WDSEL_RESET_SWCORE_BITS _u(0x00000100) -#define POWMAN_WDSEL_RESET_SWCORE_MSB _u(8) -#define POWMAN_WDSEL_RESET_SWCORE_LSB _u(8) -#define POWMAN_WDSEL_RESET_SWCORE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : POWMAN_WDSEL_RESET_POWMAN -// Description : If set to 1, a watchdog reset will restore powman defaults, -// reset the timer, reset the switched core power domain -// and run the full power-on state machine (PSM) sequence -// This relies on clk_ref running. Use reset_powman_async if that -// may not be true -#define POWMAN_WDSEL_RESET_POWMAN_RESET _u(0x0) -#define POWMAN_WDSEL_RESET_POWMAN_BITS _u(0x00000010) -#define POWMAN_WDSEL_RESET_POWMAN_MSB _u(4) -#define POWMAN_WDSEL_RESET_POWMAN_LSB _u(4) -#define POWMAN_WDSEL_RESET_POWMAN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : POWMAN_WDSEL_RESET_POWMAN_ASYNC -// Description : If set to 1, a watchdog reset will restore powman defaults, -// reset the timer, -// reset the switched core domain and run the full power-on state -// machine (PSM) sequence -// This does not rely on clk_ref running -#define POWMAN_WDSEL_RESET_POWMAN_ASYNC_RESET _u(0x0) -#define POWMAN_WDSEL_RESET_POWMAN_ASYNC_BITS _u(0x00000001) -#define POWMAN_WDSEL_RESET_POWMAN_ASYNC_MSB _u(0) -#define POWMAN_WDSEL_RESET_POWMAN_ASYNC_LSB _u(0) -#define POWMAN_WDSEL_RESET_POWMAN_ASYNC_ACCESS "RW" -// ============================================================================= -// Register : POWMAN_SEQ_CFG -// Description : For configuration of the power sequencer -// Writes are ignored while POWMAN_STATE_CHANGING=1 -#define POWMAN_SEQ_CFG_OFFSET _u(0x00000034) -#define POWMAN_SEQ_CFG_BITS _u(0x001311f3) -#define POWMAN_SEQ_CFG_RESET _u(0x001011f0) -// ----------------------------------------------------------------------------- -// Field : POWMAN_SEQ_CFG_USING_FAST_POWCK -// Description : 0 indicates the POWMAN clock is running from the low power -// oscillator (32kHz) -// 1 indicates the POWMAN clock is running from the reference -// clock (2-50MHz) -#define POWMAN_SEQ_CFG_USING_FAST_POWCK_RESET _u(0x1) -#define POWMAN_SEQ_CFG_USING_FAST_POWCK_BITS _u(0x00100000) -#define POWMAN_SEQ_CFG_USING_FAST_POWCK_MSB _u(20) -#define POWMAN_SEQ_CFG_USING_FAST_POWCK_LSB _u(20) -#define POWMAN_SEQ_CFG_USING_FAST_POWCK_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : POWMAN_SEQ_CFG_USING_BOD_LP -// Description : Indicates the brown-out detector (BOD) mode -// 0 = BOD high power mode which is the default -// 1 = BOD low power mode -#define POWMAN_SEQ_CFG_USING_BOD_LP_RESET _u(0x0) -#define POWMAN_SEQ_CFG_USING_BOD_LP_BITS _u(0x00020000) -#define POWMAN_SEQ_CFG_USING_BOD_LP_MSB _u(17) -#define POWMAN_SEQ_CFG_USING_BOD_LP_LSB _u(17) -#define POWMAN_SEQ_CFG_USING_BOD_LP_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : POWMAN_SEQ_CFG_USING_VREG_LP -// Description : Indicates the voltage regulator (VREG) mode -// 0 = VREG high power mode which is the default -// 1 = VREG low power mode -#define POWMAN_SEQ_CFG_USING_VREG_LP_RESET _u(0x0) -#define POWMAN_SEQ_CFG_USING_VREG_LP_BITS _u(0x00010000) -#define POWMAN_SEQ_CFG_USING_VREG_LP_MSB _u(16) -#define POWMAN_SEQ_CFG_USING_VREG_LP_LSB _u(16) -#define POWMAN_SEQ_CFG_USING_VREG_LP_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : POWMAN_SEQ_CFG_USE_FAST_POWCK -// Description : selects the reference clock (clk_ref) as the source of the -// POWMAN clock when switched-core is powered. The POWMAN clock -// always switches to the slow clock (lposc) when switched-core is -// powered down because the fast clock stops running. -// 0 always run the POWMAN clock from the slow clock (lposc) -// 1 run the POWMAN clock from the fast clock when available -// This setting takes effect when a power up sequence is next run -#define POWMAN_SEQ_CFG_USE_FAST_POWCK_RESET _u(0x1) -#define POWMAN_SEQ_CFG_USE_FAST_POWCK_BITS _u(0x00001000) -#define POWMAN_SEQ_CFG_USE_FAST_POWCK_MSB _u(12) -#define POWMAN_SEQ_CFG_USE_FAST_POWCK_LSB _u(12) -#define POWMAN_SEQ_CFG_USE_FAST_POWCK_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : POWMAN_SEQ_CFG_RUN_LPOSC_IN_LP -// Description : Set to 0 to stop the low power osc when the switched-core is -// powered down, which is unwise if using it to clock the timer -// This setting takes effect when the swcore is next powered down -#define POWMAN_SEQ_CFG_RUN_LPOSC_IN_LP_RESET _u(0x1) -#define POWMAN_SEQ_CFG_RUN_LPOSC_IN_LP_BITS _u(0x00000100) -#define POWMAN_SEQ_CFG_RUN_LPOSC_IN_LP_MSB _u(8) -#define POWMAN_SEQ_CFG_RUN_LPOSC_IN_LP_LSB _u(8) -#define POWMAN_SEQ_CFG_RUN_LPOSC_IN_LP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : POWMAN_SEQ_CFG_USE_BOD_HP -// Description : Set to 0 to prevent automatic switching to bod high power mode -// when switched-core is powered up -// This setting takes effect when the swcore is next powered up -#define POWMAN_SEQ_CFG_USE_BOD_HP_RESET _u(0x1) -#define POWMAN_SEQ_CFG_USE_BOD_HP_BITS _u(0x00000080) -#define POWMAN_SEQ_CFG_USE_BOD_HP_MSB _u(7) -#define POWMAN_SEQ_CFG_USE_BOD_HP_LSB _u(7) -#define POWMAN_SEQ_CFG_USE_BOD_HP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : POWMAN_SEQ_CFG_USE_BOD_LP -// Description : Set to 0 to prevent automatic switching to bod low power mode -// when switched-core is powered down -// This setting takes effect when the swcore is next powered down -#define POWMAN_SEQ_CFG_USE_BOD_LP_RESET _u(0x1) -#define POWMAN_SEQ_CFG_USE_BOD_LP_BITS _u(0x00000040) -#define POWMAN_SEQ_CFG_USE_BOD_LP_MSB _u(6) -#define POWMAN_SEQ_CFG_USE_BOD_LP_LSB _u(6) -#define POWMAN_SEQ_CFG_USE_BOD_LP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : POWMAN_SEQ_CFG_USE_VREG_HP -// Description : Set to 0 to prevent automatic switching to vreg high power mode -// when switched-core is powered up -// This setting takes effect when the swcore is next powered up -#define POWMAN_SEQ_CFG_USE_VREG_HP_RESET _u(0x1) -#define POWMAN_SEQ_CFG_USE_VREG_HP_BITS _u(0x00000020) -#define POWMAN_SEQ_CFG_USE_VREG_HP_MSB _u(5) -#define POWMAN_SEQ_CFG_USE_VREG_HP_LSB _u(5) -#define POWMAN_SEQ_CFG_USE_VREG_HP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : POWMAN_SEQ_CFG_USE_VREG_LP -// Description : Set to 0 to prevent automatic switching to vreg low power mode -// when switched-core is powered down -// This setting takes effect when the swcore is next powered down -#define POWMAN_SEQ_CFG_USE_VREG_LP_RESET _u(0x1) -#define POWMAN_SEQ_CFG_USE_VREG_LP_BITS _u(0x00000010) -#define POWMAN_SEQ_CFG_USE_VREG_LP_MSB _u(4) -#define POWMAN_SEQ_CFG_USE_VREG_LP_LSB _u(4) -#define POWMAN_SEQ_CFG_USE_VREG_LP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : POWMAN_SEQ_CFG_HW_PWRUP_SRAM0 -// Description : Specifies the power state of SRAM0 when powering up swcore from -// a low power state (P1.xxx) to a high power state (P0.0xx). -// 0=power-up -// 1=no change -#define POWMAN_SEQ_CFG_HW_PWRUP_SRAM0_RESET _u(0x0) -#define POWMAN_SEQ_CFG_HW_PWRUP_SRAM0_BITS _u(0x00000002) -#define POWMAN_SEQ_CFG_HW_PWRUP_SRAM0_MSB _u(1) -#define POWMAN_SEQ_CFG_HW_PWRUP_SRAM0_LSB _u(1) -#define POWMAN_SEQ_CFG_HW_PWRUP_SRAM0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : POWMAN_SEQ_CFG_HW_PWRUP_SRAM1 -// Description : Specifies the power state of SRAM1 when powering up swcore from -// a low power state (P1.xxx) to a high power state (P0.0xx). -// 0=power-up -// 1=no change -#define POWMAN_SEQ_CFG_HW_PWRUP_SRAM1_RESET _u(0x0) -#define POWMAN_SEQ_CFG_HW_PWRUP_SRAM1_BITS _u(0x00000001) -#define POWMAN_SEQ_CFG_HW_PWRUP_SRAM1_MSB _u(0) -#define POWMAN_SEQ_CFG_HW_PWRUP_SRAM1_LSB _u(0) -#define POWMAN_SEQ_CFG_HW_PWRUP_SRAM1_ACCESS "RW" -// ============================================================================= -// Register : POWMAN_STATE -// Description : This register controls the power state of the 4 power domains. -// The current power state is indicated in POWMAN_STATE_CURRENT -// which is read-only. -// To change the state, write to POWMAN_STATE_REQ. -// The coding of POWMAN_STATE_CURRENT & POWMAN_STATE_REQ -// corresponds to the power states -// defined in the datasheet: -// bit 3 = SWCORE -// bit 2 = XIP cache -// bit 1 = SRAM0 -// bit 0 = SRAM1 -// 0 = powered up -// 1 = powered down -// When POWMAN_STATE_REQ is written, the POWMAN_STATE_WAITING flag -// is set while the Power Manager determines what is required. If -// an invalid transition is requested the Power Manager will still -// register the request in POWMAN_STATE_REQ but will also set the -// POWMAN_BAD_REQ flag. It will then implement the power-up -// requests and ignore the power down requests. To do nothing -// would risk entering an unrecoverable lock-up state. Invalid -// requests are: any combination of power up and power down -// requests any request that results in swcore boing powered and -// xip unpowered If the request is to power down the switched-core -// domain then POWMAN_STATE_WAITING stays active until the -// processors halt. During this time the POWMAN_STATE_REQ field -// can be re-written to change or cancel the request. When the -// power state transition begins the POWMAN_STATE_WAITING_flag is -// cleared, the POWMAN_STATE_CHANGING flag is set and POWMAN -// register writes are ignored until the transition completes. -#define POWMAN_STATE_OFFSET _u(0x00000038) -#define POWMAN_STATE_BITS _u(0x00003fff) -#define POWMAN_STATE_RESET _u(0x0000000f) -// ----------------------------------------------------------------------------- -// Field : POWMAN_STATE_CHANGING -#define POWMAN_STATE_CHANGING_RESET _u(0x0) -#define POWMAN_STATE_CHANGING_BITS _u(0x00002000) -#define POWMAN_STATE_CHANGING_MSB _u(13) -#define POWMAN_STATE_CHANGING_LSB _u(13) -#define POWMAN_STATE_CHANGING_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : POWMAN_STATE_WAITING -#define POWMAN_STATE_WAITING_RESET _u(0x0) -#define POWMAN_STATE_WAITING_BITS _u(0x00001000) -#define POWMAN_STATE_WAITING_MSB _u(12) -#define POWMAN_STATE_WAITING_LSB _u(12) -#define POWMAN_STATE_WAITING_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : POWMAN_STATE_BAD_HW_REQ -// Description : Bad hardware initiated state request. Went back to state 0 -// (i.e. everything powered up) -#define POWMAN_STATE_BAD_HW_REQ_RESET _u(0x0) -#define POWMAN_STATE_BAD_HW_REQ_BITS _u(0x00000800) -#define POWMAN_STATE_BAD_HW_REQ_MSB _u(11) -#define POWMAN_STATE_BAD_HW_REQ_LSB _u(11) -#define POWMAN_STATE_BAD_HW_REQ_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : POWMAN_STATE_BAD_SW_REQ -// Description : Bad software initiated state request. No action taken. -#define POWMAN_STATE_BAD_SW_REQ_RESET _u(0x0) -#define POWMAN_STATE_BAD_SW_REQ_BITS _u(0x00000400) -#define POWMAN_STATE_BAD_SW_REQ_MSB _u(10) -#define POWMAN_STATE_BAD_SW_REQ_LSB _u(10) -#define POWMAN_STATE_BAD_SW_REQ_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : POWMAN_STATE_PWRUP_WHILE_WAITING -// Description : Request ignored because of a pending pwrup request. See -// current_pwrup_req. Note this blocks powering up AND powering -// down. -#define POWMAN_STATE_PWRUP_WHILE_WAITING_RESET _u(0x0) -#define POWMAN_STATE_PWRUP_WHILE_WAITING_BITS _u(0x00000200) -#define POWMAN_STATE_PWRUP_WHILE_WAITING_MSB _u(9) -#define POWMAN_STATE_PWRUP_WHILE_WAITING_LSB _u(9) -#define POWMAN_STATE_PWRUP_WHILE_WAITING_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : POWMAN_STATE_REQ_IGNORED -#define POWMAN_STATE_REQ_IGNORED_RESET _u(0x0) -#define POWMAN_STATE_REQ_IGNORED_BITS _u(0x00000100) -#define POWMAN_STATE_REQ_IGNORED_MSB _u(8) -#define POWMAN_STATE_REQ_IGNORED_LSB _u(8) -#define POWMAN_STATE_REQ_IGNORED_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : POWMAN_STATE_REQ -#define POWMAN_STATE_REQ_RESET _u(0x0) -#define POWMAN_STATE_REQ_BITS _u(0x000000f0) -#define POWMAN_STATE_REQ_MSB _u(7) -#define POWMAN_STATE_REQ_LSB _u(4) -#define POWMAN_STATE_REQ_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : POWMAN_STATE_CURRENT -#define POWMAN_STATE_CURRENT_RESET _u(0xf) -#define POWMAN_STATE_CURRENT_BITS _u(0x0000000f) -#define POWMAN_STATE_CURRENT_MSB _u(3) -#define POWMAN_STATE_CURRENT_LSB _u(0) -#define POWMAN_STATE_CURRENT_ACCESS "RO" -// ============================================================================= -// Register : POWMAN_POW_FASTDIV -// Description : None -// divides the POWMAN clock to provide a tick for the delay module -// and state machines -// when clk_pow is running from the slow clock it is not divided -// when clk_pow is running from the fast clock it is divided by -// tick_div -#define POWMAN_POW_FASTDIV_OFFSET _u(0x0000003c) -#define POWMAN_POW_FASTDIV_BITS _u(0x000007ff) -#define POWMAN_POW_FASTDIV_RESET _u(0x00000040) -#define POWMAN_POW_FASTDIV_MSB _u(10) -#define POWMAN_POW_FASTDIV_LSB _u(0) -#define POWMAN_POW_FASTDIV_ACCESS "RW" -// ============================================================================= -// Register : POWMAN_POW_DELAY -// Description : power state machine delays -#define POWMAN_POW_DELAY_OFFSET _u(0x00000040) -#define POWMAN_POW_DELAY_BITS _u(0x0000ffff) -#define POWMAN_POW_DELAY_RESET _u(0x00002011) -// ----------------------------------------------------------------------------- -// Field : POWMAN_POW_DELAY_SRAM_STEP -// Description : timing between the sram0 and sram1 power state machine steps -// measured in units of the powman tick period (>=1us), 0 gives a -// delay of 1 unit -#define POWMAN_POW_DELAY_SRAM_STEP_RESET _u(0x20) -#define POWMAN_POW_DELAY_SRAM_STEP_BITS _u(0x0000ff00) -#define POWMAN_POW_DELAY_SRAM_STEP_MSB _u(15) -#define POWMAN_POW_DELAY_SRAM_STEP_LSB _u(8) -#define POWMAN_POW_DELAY_SRAM_STEP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : POWMAN_POW_DELAY_XIP_STEP -// Description : timing between the xip power state machine steps -// measured in units of the lposc period, 0 gives a delay of 1 -// unit -#define POWMAN_POW_DELAY_XIP_STEP_RESET _u(0x1) -#define POWMAN_POW_DELAY_XIP_STEP_BITS _u(0x000000f0) -#define POWMAN_POW_DELAY_XIP_STEP_MSB _u(7) -#define POWMAN_POW_DELAY_XIP_STEP_LSB _u(4) -#define POWMAN_POW_DELAY_XIP_STEP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : POWMAN_POW_DELAY_SWCORE_STEP -// Description : timing between the swcore power state machine steps -// measured in units of the lposc period, 0 gives a delay of 1 -// unit -#define POWMAN_POW_DELAY_SWCORE_STEP_RESET _u(0x1) -#define POWMAN_POW_DELAY_SWCORE_STEP_BITS _u(0x0000000f) -#define POWMAN_POW_DELAY_SWCORE_STEP_MSB _u(3) -#define POWMAN_POW_DELAY_SWCORE_STEP_LSB _u(0) -#define POWMAN_POW_DELAY_SWCORE_STEP_ACCESS "RW" -// ============================================================================= -// Register : POWMAN_EXT_CTRL0 -// Description : Configures a gpio as a power mode aware control output -#define POWMAN_EXT_CTRL0_OFFSET _u(0x00000044) -#define POWMAN_EXT_CTRL0_BITS _u(0x0000713f) -#define POWMAN_EXT_CTRL0_RESET _u(0x0000003f) -// ----------------------------------------------------------------------------- -// Field : POWMAN_EXT_CTRL0_LP_EXIT_STATE -// Description : output level when exiting the low power state -#define POWMAN_EXT_CTRL0_LP_EXIT_STATE_RESET _u(0x0) -#define POWMAN_EXT_CTRL0_LP_EXIT_STATE_BITS _u(0x00004000) -#define POWMAN_EXT_CTRL0_LP_EXIT_STATE_MSB _u(14) -#define POWMAN_EXT_CTRL0_LP_EXIT_STATE_LSB _u(14) -#define POWMAN_EXT_CTRL0_LP_EXIT_STATE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : POWMAN_EXT_CTRL0_LP_ENTRY_STATE -// Description : output level when entering the low power state -#define POWMAN_EXT_CTRL0_LP_ENTRY_STATE_RESET _u(0x0) -#define POWMAN_EXT_CTRL0_LP_ENTRY_STATE_BITS _u(0x00002000) -#define POWMAN_EXT_CTRL0_LP_ENTRY_STATE_MSB _u(13) -#define POWMAN_EXT_CTRL0_LP_ENTRY_STATE_LSB _u(13) -#define POWMAN_EXT_CTRL0_LP_ENTRY_STATE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : POWMAN_EXT_CTRL0_INIT_STATE -#define POWMAN_EXT_CTRL0_INIT_STATE_RESET _u(0x0) -#define POWMAN_EXT_CTRL0_INIT_STATE_BITS _u(0x00001000) -#define POWMAN_EXT_CTRL0_INIT_STATE_MSB _u(12) -#define POWMAN_EXT_CTRL0_INIT_STATE_LSB _u(12) -#define POWMAN_EXT_CTRL0_INIT_STATE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : POWMAN_EXT_CTRL0_INIT -#define POWMAN_EXT_CTRL0_INIT_RESET _u(0x0) -#define POWMAN_EXT_CTRL0_INIT_BITS _u(0x00000100) -#define POWMAN_EXT_CTRL0_INIT_MSB _u(8) -#define POWMAN_EXT_CTRL0_INIT_LSB _u(8) -#define POWMAN_EXT_CTRL0_INIT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : POWMAN_EXT_CTRL0_GPIO_SELECT -// Description : selects from gpio 0->30 -// set to 31 to disable this feature -#define POWMAN_EXT_CTRL0_GPIO_SELECT_RESET _u(0x3f) -#define POWMAN_EXT_CTRL0_GPIO_SELECT_BITS _u(0x0000003f) -#define POWMAN_EXT_CTRL0_GPIO_SELECT_MSB _u(5) -#define POWMAN_EXT_CTRL0_GPIO_SELECT_LSB _u(0) -#define POWMAN_EXT_CTRL0_GPIO_SELECT_ACCESS "RW" -// ============================================================================= -// Register : POWMAN_EXT_CTRL1 -// Description : Configures a gpio as a power mode aware control output -#define POWMAN_EXT_CTRL1_OFFSET _u(0x00000048) -#define POWMAN_EXT_CTRL1_BITS _u(0x0000713f) -#define POWMAN_EXT_CTRL1_RESET _u(0x0000003f) -// ----------------------------------------------------------------------------- -// Field : POWMAN_EXT_CTRL1_LP_EXIT_STATE -// Description : output level when exiting the low power state -#define POWMAN_EXT_CTRL1_LP_EXIT_STATE_RESET _u(0x0) -#define POWMAN_EXT_CTRL1_LP_EXIT_STATE_BITS _u(0x00004000) -#define POWMAN_EXT_CTRL1_LP_EXIT_STATE_MSB _u(14) -#define POWMAN_EXT_CTRL1_LP_EXIT_STATE_LSB _u(14) -#define POWMAN_EXT_CTRL1_LP_EXIT_STATE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : POWMAN_EXT_CTRL1_LP_ENTRY_STATE -// Description : output level when entering the low power state -#define POWMAN_EXT_CTRL1_LP_ENTRY_STATE_RESET _u(0x0) -#define POWMAN_EXT_CTRL1_LP_ENTRY_STATE_BITS _u(0x00002000) -#define POWMAN_EXT_CTRL1_LP_ENTRY_STATE_MSB _u(13) -#define POWMAN_EXT_CTRL1_LP_ENTRY_STATE_LSB _u(13) -#define POWMAN_EXT_CTRL1_LP_ENTRY_STATE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : POWMAN_EXT_CTRL1_INIT_STATE -#define POWMAN_EXT_CTRL1_INIT_STATE_RESET _u(0x0) -#define POWMAN_EXT_CTRL1_INIT_STATE_BITS _u(0x00001000) -#define POWMAN_EXT_CTRL1_INIT_STATE_MSB _u(12) -#define POWMAN_EXT_CTRL1_INIT_STATE_LSB _u(12) -#define POWMAN_EXT_CTRL1_INIT_STATE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : POWMAN_EXT_CTRL1_INIT -#define POWMAN_EXT_CTRL1_INIT_RESET _u(0x0) -#define POWMAN_EXT_CTRL1_INIT_BITS _u(0x00000100) -#define POWMAN_EXT_CTRL1_INIT_MSB _u(8) -#define POWMAN_EXT_CTRL1_INIT_LSB _u(8) -#define POWMAN_EXT_CTRL1_INIT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : POWMAN_EXT_CTRL1_GPIO_SELECT -// Description : selects from gpio 0->30 -// set to 31 to disable this feature -#define POWMAN_EXT_CTRL1_GPIO_SELECT_RESET _u(0x3f) -#define POWMAN_EXT_CTRL1_GPIO_SELECT_BITS _u(0x0000003f) -#define POWMAN_EXT_CTRL1_GPIO_SELECT_MSB _u(5) -#define POWMAN_EXT_CTRL1_GPIO_SELECT_LSB _u(0) -#define POWMAN_EXT_CTRL1_GPIO_SELECT_ACCESS "RW" -// ============================================================================= -// Register : POWMAN_EXT_TIME_REF -// Description : Select a GPIO to use as a time reference, the source can be -// used to drive the low power clock at 32kHz, or to provide a 1ms -// tick to the timer, or provide a 1Hz tick to the timer. The tick -// selection is controlled by the POWMAN_TIMER register. -#define POWMAN_EXT_TIME_REF_OFFSET _u(0x0000004c) -#define POWMAN_EXT_TIME_REF_BITS _u(0x00000013) -#define POWMAN_EXT_TIME_REF_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : POWMAN_EXT_TIME_REF_DRIVE_LPCK -// Description : Use the selected GPIO to drive the 32kHz low power clock, in -// place of LPOSC. This field must only be written when -// POWMAN_TIMER_RUN=0 -#define POWMAN_EXT_TIME_REF_DRIVE_LPCK_RESET _u(0x0) -#define POWMAN_EXT_TIME_REF_DRIVE_LPCK_BITS _u(0x00000010) -#define POWMAN_EXT_TIME_REF_DRIVE_LPCK_MSB _u(4) -#define POWMAN_EXT_TIME_REF_DRIVE_LPCK_LSB _u(4) -#define POWMAN_EXT_TIME_REF_DRIVE_LPCK_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : POWMAN_EXT_TIME_REF_SOURCE_SEL -// Description : 0 -> gpio12 -// 1 -> gpio20 -// 2 -> gpio14 -// 3 -> gpio22 -#define POWMAN_EXT_TIME_REF_SOURCE_SEL_RESET _u(0x0) -#define POWMAN_EXT_TIME_REF_SOURCE_SEL_BITS _u(0x00000003) -#define POWMAN_EXT_TIME_REF_SOURCE_SEL_MSB _u(1) -#define POWMAN_EXT_TIME_REF_SOURCE_SEL_LSB _u(0) -#define POWMAN_EXT_TIME_REF_SOURCE_SEL_ACCESS "RW" -// ============================================================================= -// Register : POWMAN_LPOSC_FREQ_KHZ_INT -// Description : Informs the AON Timer of the integer component of the clock -// frequency when running off the LPOSC. -// Integer component of the LPOSC or GPIO clock source frequency -// in kHz. Default = 32 This field must only be written when -// POWMAN_TIMER_RUN=0 or POWMAN_TIMER_USING_XOSC=1 -#define POWMAN_LPOSC_FREQ_KHZ_INT_OFFSET _u(0x00000050) -#define POWMAN_LPOSC_FREQ_KHZ_INT_BITS _u(0x0000003f) -#define POWMAN_LPOSC_FREQ_KHZ_INT_RESET _u(0x00000020) -#define POWMAN_LPOSC_FREQ_KHZ_INT_MSB _u(5) -#define POWMAN_LPOSC_FREQ_KHZ_INT_LSB _u(0) -#define POWMAN_LPOSC_FREQ_KHZ_INT_ACCESS "RW" -// ============================================================================= -// Register : POWMAN_LPOSC_FREQ_KHZ_FRAC -// Description : Informs the AON Timer of the fractional component of the clock -// frequency when running off the LPOSC. -// Fractional component of the LPOSC or GPIO clock source -// frequency in kHz. Default = 0.768 This field must only be -// written when POWMAN_TIMER_RUN=0 or POWMAN_TIMER_USING_XOSC=1 -#define POWMAN_LPOSC_FREQ_KHZ_FRAC_OFFSET _u(0x00000054) -#define POWMAN_LPOSC_FREQ_KHZ_FRAC_BITS _u(0x0000ffff) -#define POWMAN_LPOSC_FREQ_KHZ_FRAC_RESET _u(0x0000c49c) -#define POWMAN_LPOSC_FREQ_KHZ_FRAC_MSB _u(15) -#define POWMAN_LPOSC_FREQ_KHZ_FRAC_LSB _u(0) -#define POWMAN_LPOSC_FREQ_KHZ_FRAC_ACCESS "RW" -// ============================================================================= -// Register : POWMAN_XOSC_FREQ_KHZ_INT -// Description : Informs the AON Timer of the integer component of the clock -// frequency when running off the XOSC. -// Integer component of the XOSC frequency in kHz. Default = 12000 -// Must be >1 This field must only be written when -// POWMAN_TIMER_RUN=0 or POWMAN_TIMER_USING_XOSC=0 -#define POWMAN_XOSC_FREQ_KHZ_INT_OFFSET _u(0x00000058) -#define POWMAN_XOSC_FREQ_KHZ_INT_BITS _u(0x0000ffff) -#define POWMAN_XOSC_FREQ_KHZ_INT_RESET _u(0x00002ee0) -#define POWMAN_XOSC_FREQ_KHZ_INT_MSB _u(15) -#define POWMAN_XOSC_FREQ_KHZ_INT_LSB _u(0) -#define POWMAN_XOSC_FREQ_KHZ_INT_ACCESS "RW" -// ============================================================================= -// Register : POWMAN_XOSC_FREQ_KHZ_FRAC -// Description : Informs the AON Timer of the fractional component of the clock -// frequency when running off the XOSC. -// Fractional component of the XOSC frequency in kHz. This field -// must only be written when POWMAN_TIMER_RUN=0 or -// POWMAN_TIMER_USING_XOSC=0 -#define POWMAN_XOSC_FREQ_KHZ_FRAC_OFFSET _u(0x0000005c) -#define POWMAN_XOSC_FREQ_KHZ_FRAC_BITS _u(0x0000ffff) -#define POWMAN_XOSC_FREQ_KHZ_FRAC_RESET _u(0x00000000) -#define POWMAN_XOSC_FREQ_KHZ_FRAC_MSB _u(15) -#define POWMAN_XOSC_FREQ_KHZ_FRAC_LSB _u(0) -#define POWMAN_XOSC_FREQ_KHZ_FRAC_ACCESS "RW" -// ============================================================================= -// Register : POWMAN_SET_TIME_63TO48 -// Description : None -// For setting the time, do not use for reading the time, use -// POWMAN_READ_TIME_UPPER and POWMAN_READ_TIME_LOWER. This field -// must only be written when POWMAN_TIMER_RUN=0 -#define POWMAN_SET_TIME_63TO48_OFFSET _u(0x00000060) -#define POWMAN_SET_TIME_63TO48_BITS _u(0x0000ffff) -#define POWMAN_SET_TIME_63TO48_RESET _u(0x00000000) -#define POWMAN_SET_TIME_63TO48_MSB _u(15) -#define POWMAN_SET_TIME_63TO48_LSB _u(0) -#define POWMAN_SET_TIME_63TO48_ACCESS "RW" -// ============================================================================= -// Register : POWMAN_SET_TIME_47TO32 -// Description : None -// For setting the time, do not use for reading the time, use -// POWMAN_READ_TIME_UPPER and POWMAN_READ_TIME_LOWER. This field -// must only be written when POWMAN_TIMER_RUN=0 -#define POWMAN_SET_TIME_47TO32_OFFSET _u(0x00000064) -#define POWMAN_SET_TIME_47TO32_BITS _u(0x0000ffff) -#define POWMAN_SET_TIME_47TO32_RESET _u(0x00000000) -#define POWMAN_SET_TIME_47TO32_MSB _u(15) -#define POWMAN_SET_TIME_47TO32_LSB _u(0) -#define POWMAN_SET_TIME_47TO32_ACCESS "RW" -// ============================================================================= -// Register : POWMAN_SET_TIME_31TO16 -// Description : None -// For setting the time, do not use for reading the time, use -// POWMAN_READ_TIME_UPPER and POWMAN_READ_TIME_LOWER. This field -// must only be written when POWMAN_TIMER_RUN=0 -#define POWMAN_SET_TIME_31TO16_OFFSET _u(0x00000068) -#define POWMAN_SET_TIME_31TO16_BITS _u(0x0000ffff) -#define POWMAN_SET_TIME_31TO16_RESET _u(0x00000000) -#define POWMAN_SET_TIME_31TO16_MSB _u(15) -#define POWMAN_SET_TIME_31TO16_LSB _u(0) -#define POWMAN_SET_TIME_31TO16_ACCESS "RW" -// ============================================================================= -// Register : POWMAN_SET_TIME_15TO0 -// Description : None -// For setting the time, do not use for reading the time, use -// POWMAN_READ_TIME_UPPER and POWMAN_READ_TIME_LOWER. This field -// must only be written when POWMAN_TIMER_RUN=0 -#define POWMAN_SET_TIME_15TO0_OFFSET _u(0x0000006c) -#define POWMAN_SET_TIME_15TO0_BITS _u(0x0000ffff) -#define POWMAN_SET_TIME_15TO0_RESET _u(0x00000000) -#define POWMAN_SET_TIME_15TO0_MSB _u(15) -#define POWMAN_SET_TIME_15TO0_LSB _u(0) -#define POWMAN_SET_TIME_15TO0_ACCESS "RW" -// ============================================================================= -// Register : POWMAN_READ_TIME_UPPER -// Description : None -// For reading bits 63:32 of the timer. When reading all 64 bits -// it is possible for the LOWER count to rollover during the read. -// It is recommended to read UPPER, then LOWER, then re-read UPPER -// and, if it has changed, re-read LOWER. -#define POWMAN_READ_TIME_UPPER_OFFSET _u(0x00000070) -#define POWMAN_READ_TIME_UPPER_BITS _u(0xffffffff) -#define POWMAN_READ_TIME_UPPER_RESET _u(0x00000000) -#define POWMAN_READ_TIME_UPPER_MSB _u(31) -#define POWMAN_READ_TIME_UPPER_LSB _u(0) -#define POWMAN_READ_TIME_UPPER_ACCESS "RO" -// ============================================================================= -// Register : POWMAN_READ_TIME_LOWER -// Description : None -// For reading bits 31:0 of the timer. -#define POWMAN_READ_TIME_LOWER_OFFSET _u(0x00000074) -#define POWMAN_READ_TIME_LOWER_BITS _u(0xffffffff) -#define POWMAN_READ_TIME_LOWER_RESET _u(0x00000000) -#define POWMAN_READ_TIME_LOWER_MSB _u(31) -#define POWMAN_READ_TIME_LOWER_LSB _u(0) -#define POWMAN_READ_TIME_LOWER_ACCESS "RO" -// ============================================================================= -// Register : POWMAN_ALARM_TIME_63TO48 -// Description : None -// This field must only be written when POWMAN_ALARM_ENAB=0 -#define POWMAN_ALARM_TIME_63TO48_OFFSET _u(0x00000078) -#define POWMAN_ALARM_TIME_63TO48_BITS _u(0x0000ffff) -#define POWMAN_ALARM_TIME_63TO48_RESET _u(0x00000000) -#define POWMAN_ALARM_TIME_63TO48_MSB _u(15) -#define POWMAN_ALARM_TIME_63TO48_LSB _u(0) -#define POWMAN_ALARM_TIME_63TO48_ACCESS "RW" -// ============================================================================= -// Register : POWMAN_ALARM_TIME_47TO32 -// Description : None -// This field must only be written when POWMAN_ALARM_ENAB=0 -#define POWMAN_ALARM_TIME_47TO32_OFFSET _u(0x0000007c) -#define POWMAN_ALARM_TIME_47TO32_BITS _u(0x0000ffff) -#define POWMAN_ALARM_TIME_47TO32_RESET _u(0x00000000) -#define POWMAN_ALARM_TIME_47TO32_MSB _u(15) -#define POWMAN_ALARM_TIME_47TO32_LSB _u(0) -#define POWMAN_ALARM_TIME_47TO32_ACCESS "RW" -// ============================================================================= -// Register : POWMAN_ALARM_TIME_31TO16 -// Description : None -// This field must only be written when POWMAN_ALARM_ENAB=0 -#define POWMAN_ALARM_TIME_31TO16_OFFSET _u(0x00000080) -#define POWMAN_ALARM_TIME_31TO16_BITS _u(0x0000ffff) -#define POWMAN_ALARM_TIME_31TO16_RESET _u(0x00000000) -#define POWMAN_ALARM_TIME_31TO16_MSB _u(15) -#define POWMAN_ALARM_TIME_31TO16_LSB _u(0) -#define POWMAN_ALARM_TIME_31TO16_ACCESS "RW" -// ============================================================================= -// Register : POWMAN_ALARM_TIME_15TO0 -// Description : None -// This field must only be written when POWMAN_ALARM_ENAB=0 -#define POWMAN_ALARM_TIME_15TO0_OFFSET _u(0x00000084) -#define POWMAN_ALARM_TIME_15TO0_BITS _u(0x0000ffff) -#define POWMAN_ALARM_TIME_15TO0_RESET _u(0x00000000) -#define POWMAN_ALARM_TIME_15TO0_MSB _u(15) -#define POWMAN_ALARM_TIME_15TO0_LSB _u(0) -#define POWMAN_ALARM_TIME_15TO0_ACCESS "RW" -// ============================================================================= -// Register : POWMAN_TIMER -#define POWMAN_TIMER_OFFSET _u(0x00000088) -#define POWMAN_TIMER_BITS _u(0x000f2777) -#define POWMAN_TIMER_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : POWMAN_TIMER_USING_GPIO_1HZ -// Description : Timer is synchronised to a 1hz gpio source -#define POWMAN_TIMER_USING_GPIO_1HZ_RESET _u(0x0) -#define POWMAN_TIMER_USING_GPIO_1HZ_BITS _u(0x00080000) -#define POWMAN_TIMER_USING_GPIO_1HZ_MSB _u(19) -#define POWMAN_TIMER_USING_GPIO_1HZ_LSB _u(19) -#define POWMAN_TIMER_USING_GPIO_1HZ_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : POWMAN_TIMER_USING_GPIO_1KHZ -// Description : Timer is running from a 1khz gpio source -#define POWMAN_TIMER_USING_GPIO_1KHZ_RESET _u(0x0) -#define POWMAN_TIMER_USING_GPIO_1KHZ_BITS _u(0x00040000) -#define POWMAN_TIMER_USING_GPIO_1KHZ_MSB _u(18) -#define POWMAN_TIMER_USING_GPIO_1KHZ_LSB _u(18) -#define POWMAN_TIMER_USING_GPIO_1KHZ_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : POWMAN_TIMER_USING_LPOSC -// Description : Timer is running from lposc -#define POWMAN_TIMER_USING_LPOSC_RESET _u(0x0) -#define POWMAN_TIMER_USING_LPOSC_BITS _u(0x00020000) -#define POWMAN_TIMER_USING_LPOSC_MSB _u(17) -#define POWMAN_TIMER_USING_LPOSC_LSB _u(17) -#define POWMAN_TIMER_USING_LPOSC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : POWMAN_TIMER_USING_XOSC -// Description : Timer is running from xosc -#define POWMAN_TIMER_USING_XOSC_RESET _u(0x0) -#define POWMAN_TIMER_USING_XOSC_BITS _u(0x00010000) -#define POWMAN_TIMER_USING_XOSC_MSB _u(16) -#define POWMAN_TIMER_USING_XOSC_LSB _u(16) -#define POWMAN_TIMER_USING_XOSC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : POWMAN_TIMER_USE_GPIO_1HZ -// Description : Selects the gpio source as the reference for the sec counter. -// The msec counter will continue to use the lposc or xosc -// reference. -#define POWMAN_TIMER_USE_GPIO_1HZ_RESET _u(0x0) -#define POWMAN_TIMER_USE_GPIO_1HZ_BITS _u(0x00002000) -#define POWMAN_TIMER_USE_GPIO_1HZ_MSB _u(13) -#define POWMAN_TIMER_USE_GPIO_1HZ_LSB _u(13) -#define POWMAN_TIMER_USE_GPIO_1HZ_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : POWMAN_TIMER_USE_GPIO_1KHZ -// Description : switch to gpio as the source of the 1kHz timer tick -#define POWMAN_TIMER_USE_GPIO_1KHZ_RESET _u(0x0) -#define POWMAN_TIMER_USE_GPIO_1KHZ_BITS _u(0x00000400) -#define POWMAN_TIMER_USE_GPIO_1KHZ_MSB _u(10) -#define POWMAN_TIMER_USE_GPIO_1KHZ_LSB _u(10) -#define POWMAN_TIMER_USE_GPIO_1KHZ_ACCESS "SC" -// ----------------------------------------------------------------------------- -// Field : POWMAN_TIMER_USE_XOSC -// Description : switch to xosc as the source of the 1kHz timer tick -#define POWMAN_TIMER_USE_XOSC_RESET _u(0x0) -#define POWMAN_TIMER_USE_XOSC_BITS _u(0x00000200) -#define POWMAN_TIMER_USE_XOSC_MSB _u(9) -#define POWMAN_TIMER_USE_XOSC_LSB _u(9) -#define POWMAN_TIMER_USE_XOSC_ACCESS "SC" -// ----------------------------------------------------------------------------- -// Field : POWMAN_TIMER_USE_LPOSC -// Description : Switch to lposc as the source of the 1kHz timer tick -#define POWMAN_TIMER_USE_LPOSC_RESET _u(0x0) -#define POWMAN_TIMER_USE_LPOSC_BITS _u(0x00000100) -#define POWMAN_TIMER_USE_LPOSC_MSB _u(8) -#define POWMAN_TIMER_USE_LPOSC_LSB _u(8) -#define POWMAN_TIMER_USE_LPOSC_ACCESS "SC" -// ----------------------------------------------------------------------------- -// Field : POWMAN_TIMER_ALARM -// Description : Alarm has fired. Write to 1 to clear the alarm. -#define POWMAN_TIMER_ALARM_RESET _u(0x0) -#define POWMAN_TIMER_ALARM_BITS _u(0x00000040) -#define POWMAN_TIMER_ALARM_MSB _u(6) -#define POWMAN_TIMER_ALARM_LSB _u(6) -#define POWMAN_TIMER_ALARM_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : POWMAN_TIMER_PWRUP_ON_ALARM -// Description : Alarm wakes the chip from low power mode -#define POWMAN_TIMER_PWRUP_ON_ALARM_RESET _u(0x0) -#define POWMAN_TIMER_PWRUP_ON_ALARM_BITS _u(0x00000020) -#define POWMAN_TIMER_PWRUP_ON_ALARM_MSB _u(5) -#define POWMAN_TIMER_PWRUP_ON_ALARM_LSB _u(5) -#define POWMAN_TIMER_PWRUP_ON_ALARM_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : POWMAN_TIMER_ALARM_ENAB -// Description : Enables the alarm. The alarm must be disabled while writing the -// alarm time. -#define POWMAN_TIMER_ALARM_ENAB_RESET _u(0x0) -#define POWMAN_TIMER_ALARM_ENAB_BITS _u(0x00000010) -#define POWMAN_TIMER_ALARM_ENAB_MSB _u(4) -#define POWMAN_TIMER_ALARM_ENAB_LSB _u(4) -#define POWMAN_TIMER_ALARM_ENAB_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : POWMAN_TIMER_CLEAR -// Description : Clears the timer, does not disable the timer and does not -// affect the alarm. This control can be written at any time. -#define POWMAN_TIMER_CLEAR_RESET _u(0x0) -#define POWMAN_TIMER_CLEAR_BITS _u(0x00000004) -#define POWMAN_TIMER_CLEAR_MSB _u(2) -#define POWMAN_TIMER_CLEAR_LSB _u(2) -#define POWMAN_TIMER_CLEAR_ACCESS "SC" -// ----------------------------------------------------------------------------- -// Field : POWMAN_TIMER_RUN -// Description : Timer enable. Setting this bit causes the timer to begin -// counting up from its current value. Clearing this bit stops the -// timer from counting. -// -// Before enabling the timer, set the POWMAN_LPOSC_FREQ* and -// POWMAN_XOSC_FREQ* registers to configure the count rate, and -// initialise the current time by writing to SET_TIME_63TO48 -// through SET_TIME_15TO0. You must not write to the SET_TIME_x -// registers when the timer is running. -// -// Once configured, start the timer by setting POWMAN_TIMER_RUN=1. -// This will start the timer running from the LPOSC. When the XOSC -// is available switch the reference clock to XOSC then select it -// as the timer clock by setting POWMAN_TIMER_USE_XOSC=1 -#define POWMAN_TIMER_RUN_RESET _u(0x0) -#define POWMAN_TIMER_RUN_BITS _u(0x00000002) -#define POWMAN_TIMER_RUN_MSB _u(1) -#define POWMAN_TIMER_RUN_LSB _u(1) -#define POWMAN_TIMER_RUN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : POWMAN_TIMER_NONSEC_WRITE -// Description : Control whether Non-secure software can write to the timer -// registers. All other registers are hardwired to be inaccessible -// to Non-secure. -#define POWMAN_TIMER_NONSEC_WRITE_RESET _u(0x0) -#define POWMAN_TIMER_NONSEC_WRITE_BITS _u(0x00000001) -#define POWMAN_TIMER_NONSEC_WRITE_MSB _u(0) -#define POWMAN_TIMER_NONSEC_WRITE_LSB _u(0) -#define POWMAN_TIMER_NONSEC_WRITE_ACCESS "RW" -// ============================================================================= -// Register : POWMAN_PWRUP0 -// Description : 4 GPIO powerup events can be configured to wake the chip up -// from a low power state. -// The pwrups are level/edge sensitive and can be set to trigger -// on a high/rising or low/falling event -// The number of gpios available depends on the package option. An -// invalid selection will be ignored -// source = 0 selects gpio0 -// . -// . -// source = 47 selects gpio47 -// source = 48 selects qspi_ss -// source = 49 selects qspi_sd0 -// source = 50 selects qspi_sd1 -// source = 51 selects qspi_sd2 -// source = 52 selects qspi_sd3 -// source = 53 selects qspi_sclk -// level = 0 triggers the pwrup when the source is low -// level = 1 triggers the pwrup when the source is high -#define POWMAN_PWRUP0_OFFSET _u(0x0000008c) -#define POWMAN_PWRUP0_BITS _u(0x000007ff) -#define POWMAN_PWRUP0_RESET _u(0x0000003f) -// ----------------------------------------------------------------------------- -// Field : POWMAN_PWRUP0_RAW_STATUS -// Description : Value of selected gpio pin (only if enable == 1) -#define POWMAN_PWRUP0_RAW_STATUS_RESET _u(0x0) -#define POWMAN_PWRUP0_RAW_STATUS_BITS _u(0x00000400) -#define POWMAN_PWRUP0_RAW_STATUS_MSB _u(10) -#define POWMAN_PWRUP0_RAW_STATUS_LSB _u(10) -#define POWMAN_PWRUP0_RAW_STATUS_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : POWMAN_PWRUP0_STATUS -// Description : Status of gpio wakeup. Write to 1 to clear a latched edge -// detect. -#define POWMAN_PWRUP0_STATUS_RESET _u(0x0) -#define POWMAN_PWRUP0_STATUS_BITS _u(0x00000200) -#define POWMAN_PWRUP0_STATUS_MSB _u(9) -#define POWMAN_PWRUP0_STATUS_LSB _u(9) -#define POWMAN_PWRUP0_STATUS_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : POWMAN_PWRUP0_MODE -// Description : Edge or level detect. Edge will detect a 0 to 1 transition (or -// 1 to 0 transition). Level will detect a 1 or 0. Both types of -// event get latched into the current_pwrup_req register. -// 0x0 -> level -// 0x1 -> edge -#define POWMAN_PWRUP0_MODE_RESET _u(0x0) -#define POWMAN_PWRUP0_MODE_BITS _u(0x00000100) -#define POWMAN_PWRUP0_MODE_MSB _u(8) -#define POWMAN_PWRUP0_MODE_LSB _u(8) -#define POWMAN_PWRUP0_MODE_ACCESS "RW" -#define POWMAN_PWRUP0_MODE_VALUE_LEVEL _u(0x0) -#define POWMAN_PWRUP0_MODE_VALUE_EDGE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : POWMAN_PWRUP0_DIRECTION -// 0x0 -> low_falling -// 0x1 -> high_rising -#define POWMAN_PWRUP0_DIRECTION_RESET _u(0x0) -#define POWMAN_PWRUP0_DIRECTION_BITS _u(0x00000080) -#define POWMAN_PWRUP0_DIRECTION_MSB _u(7) -#define POWMAN_PWRUP0_DIRECTION_LSB _u(7) -#define POWMAN_PWRUP0_DIRECTION_ACCESS "RW" -#define POWMAN_PWRUP0_DIRECTION_VALUE_LOW_FALLING _u(0x0) -#define POWMAN_PWRUP0_DIRECTION_VALUE_HIGH_RISING _u(0x1) -// ----------------------------------------------------------------------------- -// Field : POWMAN_PWRUP0_ENABLE -// Description : Set to 1 to enable the wakeup source. Set to 0 to disable the -// wakeup source and clear a pending wakeup event. -// If using edge detect a latched edge needs to be cleared by -// writing 1 to the status register also. -#define POWMAN_PWRUP0_ENABLE_RESET _u(0x0) -#define POWMAN_PWRUP0_ENABLE_BITS _u(0x00000040) -#define POWMAN_PWRUP0_ENABLE_MSB _u(6) -#define POWMAN_PWRUP0_ENABLE_LSB _u(6) -#define POWMAN_PWRUP0_ENABLE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : POWMAN_PWRUP0_SOURCE -#define POWMAN_PWRUP0_SOURCE_RESET _u(0x3f) -#define POWMAN_PWRUP0_SOURCE_BITS _u(0x0000003f) -#define POWMAN_PWRUP0_SOURCE_MSB _u(5) -#define POWMAN_PWRUP0_SOURCE_LSB _u(0) -#define POWMAN_PWRUP0_SOURCE_ACCESS "RW" -// ============================================================================= -// Register : POWMAN_PWRUP1 -// Description : 4 GPIO powerup events can be configured to wake the chip up -// from a low power state. -// The pwrups are level/edge sensitive and can be set to trigger -// on a high/rising or low/falling event -// The number of gpios available depends on the package option. An -// invalid selection will be ignored -// source = 0 selects gpio0 -// . -// . -// source = 47 selects gpio47 -// source = 48 selects qspi_ss -// source = 49 selects qspi_sd0 -// source = 50 selects qspi_sd1 -// source = 51 selects qspi_sd2 -// source = 52 selects qspi_sd3 -// source = 53 selects qspi_sclk -// level = 0 triggers the pwrup when the source is low -// level = 1 triggers the pwrup when the source is high -#define POWMAN_PWRUP1_OFFSET _u(0x00000090) -#define POWMAN_PWRUP1_BITS _u(0x000007ff) -#define POWMAN_PWRUP1_RESET _u(0x0000003f) -// ----------------------------------------------------------------------------- -// Field : POWMAN_PWRUP1_RAW_STATUS -// Description : Value of selected gpio pin (only if enable == 1) -#define POWMAN_PWRUP1_RAW_STATUS_RESET _u(0x0) -#define POWMAN_PWRUP1_RAW_STATUS_BITS _u(0x00000400) -#define POWMAN_PWRUP1_RAW_STATUS_MSB _u(10) -#define POWMAN_PWRUP1_RAW_STATUS_LSB _u(10) -#define POWMAN_PWRUP1_RAW_STATUS_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : POWMAN_PWRUP1_STATUS -// Description : Status of gpio wakeup. Write to 1 to clear a latched edge -// detect. -#define POWMAN_PWRUP1_STATUS_RESET _u(0x0) -#define POWMAN_PWRUP1_STATUS_BITS _u(0x00000200) -#define POWMAN_PWRUP1_STATUS_MSB _u(9) -#define POWMAN_PWRUP1_STATUS_LSB _u(9) -#define POWMAN_PWRUP1_STATUS_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : POWMAN_PWRUP1_MODE -// Description : Edge or level detect. Edge will detect a 0 to 1 transition (or -// 1 to 0 transition). Level will detect a 1 or 0. Both types of -// event get latched into the current_pwrup_req register. -// 0x0 -> level -// 0x1 -> edge -#define POWMAN_PWRUP1_MODE_RESET _u(0x0) -#define POWMAN_PWRUP1_MODE_BITS _u(0x00000100) -#define POWMAN_PWRUP1_MODE_MSB _u(8) -#define POWMAN_PWRUP1_MODE_LSB _u(8) -#define POWMAN_PWRUP1_MODE_ACCESS "RW" -#define POWMAN_PWRUP1_MODE_VALUE_LEVEL _u(0x0) -#define POWMAN_PWRUP1_MODE_VALUE_EDGE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : POWMAN_PWRUP1_DIRECTION -// 0x0 -> low_falling -// 0x1 -> high_rising -#define POWMAN_PWRUP1_DIRECTION_RESET _u(0x0) -#define POWMAN_PWRUP1_DIRECTION_BITS _u(0x00000080) -#define POWMAN_PWRUP1_DIRECTION_MSB _u(7) -#define POWMAN_PWRUP1_DIRECTION_LSB _u(7) -#define POWMAN_PWRUP1_DIRECTION_ACCESS "RW" -#define POWMAN_PWRUP1_DIRECTION_VALUE_LOW_FALLING _u(0x0) -#define POWMAN_PWRUP1_DIRECTION_VALUE_HIGH_RISING _u(0x1) -// ----------------------------------------------------------------------------- -// Field : POWMAN_PWRUP1_ENABLE -// Description : Set to 1 to enable the wakeup source. Set to 0 to disable the -// wakeup source and clear a pending wakeup event. -// If using edge detect a latched edge needs to be cleared by -// writing 1 to the status register also. -#define POWMAN_PWRUP1_ENABLE_RESET _u(0x0) -#define POWMAN_PWRUP1_ENABLE_BITS _u(0x00000040) -#define POWMAN_PWRUP1_ENABLE_MSB _u(6) -#define POWMAN_PWRUP1_ENABLE_LSB _u(6) -#define POWMAN_PWRUP1_ENABLE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : POWMAN_PWRUP1_SOURCE -#define POWMAN_PWRUP1_SOURCE_RESET _u(0x3f) -#define POWMAN_PWRUP1_SOURCE_BITS _u(0x0000003f) -#define POWMAN_PWRUP1_SOURCE_MSB _u(5) -#define POWMAN_PWRUP1_SOURCE_LSB _u(0) -#define POWMAN_PWRUP1_SOURCE_ACCESS "RW" -// ============================================================================= -// Register : POWMAN_PWRUP2 -// Description : 4 GPIO powerup events can be configured to wake the chip up -// from a low power state. -// The pwrups are level/edge sensitive and can be set to trigger -// on a high/rising or low/falling event -// The number of gpios available depends on the package option. An -// invalid selection will be ignored -// source = 0 selects gpio0 -// . -// . -// source = 47 selects gpio47 -// source = 48 selects qspi_ss -// source = 49 selects qspi_sd0 -// source = 50 selects qspi_sd1 -// source = 51 selects qspi_sd2 -// source = 52 selects qspi_sd3 -// source = 53 selects qspi_sclk -// level = 0 triggers the pwrup when the source is low -// level = 1 triggers the pwrup when the source is high -#define POWMAN_PWRUP2_OFFSET _u(0x00000094) -#define POWMAN_PWRUP2_BITS _u(0x000007ff) -#define POWMAN_PWRUP2_RESET _u(0x0000003f) -// ----------------------------------------------------------------------------- -// Field : POWMAN_PWRUP2_RAW_STATUS -// Description : Value of selected gpio pin (only if enable == 1) -#define POWMAN_PWRUP2_RAW_STATUS_RESET _u(0x0) -#define POWMAN_PWRUP2_RAW_STATUS_BITS _u(0x00000400) -#define POWMAN_PWRUP2_RAW_STATUS_MSB _u(10) -#define POWMAN_PWRUP2_RAW_STATUS_LSB _u(10) -#define POWMAN_PWRUP2_RAW_STATUS_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : POWMAN_PWRUP2_STATUS -// Description : Status of gpio wakeup. Write to 1 to clear a latched edge -// detect. -#define POWMAN_PWRUP2_STATUS_RESET _u(0x0) -#define POWMAN_PWRUP2_STATUS_BITS _u(0x00000200) -#define POWMAN_PWRUP2_STATUS_MSB _u(9) -#define POWMAN_PWRUP2_STATUS_LSB _u(9) -#define POWMAN_PWRUP2_STATUS_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : POWMAN_PWRUP2_MODE -// Description : Edge or level detect. Edge will detect a 0 to 1 transition (or -// 1 to 0 transition). Level will detect a 1 or 0. Both types of -// event get latched into the current_pwrup_req register. -// 0x0 -> level -// 0x1 -> edge -#define POWMAN_PWRUP2_MODE_RESET _u(0x0) -#define POWMAN_PWRUP2_MODE_BITS _u(0x00000100) -#define POWMAN_PWRUP2_MODE_MSB _u(8) -#define POWMAN_PWRUP2_MODE_LSB _u(8) -#define POWMAN_PWRUP2_MODE_ACCESS "RW" -#define POWMAN_PWRUP2_MODE_VALUE_LEVEL _u(0x0) -#define POWMAN_PWRUP2_MODE_VALUE_EDGE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : POWMAN_PWRUP2_DIRECTION -// 0x0 -> low_falling -// 0x1 -> high_rising -#define POWMAN_PWRUP2_DIRECTION_RESET _u(0x0) -#define POWMAN_PWRUP2_DIRECTION_BITS _u(0x00000080) -#define POWMAN_PWRUP2_DIRECTION_MSB _u(7) -#define POWMAN_PWRUP2_DIRECTION_LSB _u(7) -#define POWMAN_PWRUP2_DIRECTION_ACCESS "RW" -#define POWMAN_PWRUP2_DIRECTION_VALUE_LOW_FALLING _u(0x0) -#define POWMAN_PWRUP2_DIRECTION_VALUE_HIGH_RISING _u(0x1) -// ----------------------------------------------------------------------------- -// Field : POWMAN_PWRUP2_ENABLE -// Description : Set to 1 to enable the wakeup source. Set to 0 to disable the -// wakeup source and clear a pending wakeup event. -// If using edge detect a latched edge needs to be cleared by -// writing 1 to the status register also. -#define POWMAN_PWRUP2_ENABLE_RESET _u(0x0) -#define POWMAN_PWRUP2_ENABLE_BITS _u(0x00000040) -#define POWMAN_PWRUP2_ENABLE_MSB _u(6) -#define POWMAN_PWRUP2_ENABLE_LSB _u(6) -#define POWMAN_PWRUP2_ENABLE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : POWMAN_PWRUP2_SOURCE -#define POWMAN_PWRUP2_SOURCE_RESET _u(0x3f) -#define POWMAN_PWRUP2_SOURCE_BITS _u(0x0000003f) -#define POWMAN_PWRUP2_SOURCE_MSB _u(5) -#define POWMAN_PWRUP2_SOURCE_LSB _u(0) -#define POWMAN_PWRUP2_SOURCE_ACCESS "RW" -// ============================================================================= -// Register : POWMAN_PWRUP3 -// Description : 4 GPIO powerup events can be configured to wake the chip up -// from a low power state. -// The pwrups are level/edge sensitive and can be set to trigger -// on a high/rising or low/falling event -// The number of gpios available depends on the package option. An -// invalid selection will be ignored -// source = 0 selects gpio0 -// . -// . -// source = 47 selects gpio47 -// source = 48 selects qspi_ss -// source = 49 selects qspi_sd0 -// source = 50 selects qspi_sd1 -// source = 51 selects qspi_sd2 -// source = 52 selects qspi_sd3 -// source = 53 selects qspi_sclk -// level = 0 triggers the pwrup when the source is low -// level = 1 triggers the pwrup when the source is high -#define POWMAN_PWRUP3_OFFSET _u(0x00000098) -#define POWMAN_PWRUP3_BITS _u(0x000007ff) -#define POWMAN_PWRUP3_RESET _u(0x0000003f) -// ----------------------------------------------------------------------------- -// Field : POWMAN_PWRUP3_RAW_STATUS -// Description : Value of selected gpio pin (only if enable == 1) -#define POWMAN_PWRUP3_RAW_STATUS_RESET _u(0x0) -#define POWMAN_PWRUP3_RAW_STATUS_BITS _u(0x00000400) -#define POWMAN_PWRUP3_RAW_STATUS_MSB _u(10) -#define POWMAN_PWRUP3_RAW_STATUS_LSB _u(10) -#define POWMAN_PWRUP3_RAW_STATUS_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : POWMAN_PWRUP3_STATUS -// Description : Status of gpio wakeup. Write to 1 to clear a latched edge -// detect. -#define POWMAN_PWRUP3_STATUS_RESET _u(0x0) -#define POWMAN_PWRUP3_STATUS_BITS _u(0x00000200) -#define POWMAN_PWRUP3_STATUS_MSB _u(9) -#define POWMAN_PWRUP3_STATUS_LSB _u(9) -#define POWMAN_PWRUP3_STATUS_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : POWMAN_PWRUP3_MODE -// Description : Edge or level detect. Edge will detect a 0 to 1 transition (or -// 1 to 0 transition). Level will detect a 1 or 0. Both types of -// event get latched into the current_pwrup_req register. -// 0x0 -> level -// 0x1 -> edge -#define POWMAN_PWRUP3_MODE_RESET _u(0x0) -#define POWMAN_PWRUP3_MODE_BITS _u(0x00000100) -#define POWMAN_PWRUP3_MODE_MSB _u(8) -#define POWMAN_PWRUP3_MODE_LSB _u(8) -#define POWMAN_PWRUP3_MODE_ACCESS "RW" -#define POWMAN_PWRUP3_MODE_VALUE_LEVEL _u(0x0) -#define POWMAN_PWRUP3_MODE_VALUE_EDGE _u(0x1) -// ----------------------------------------------------------------------------- -// Field : POWMAN_PWRUP3_DIRECTION -// 0x0 -> low_falling -// 0x1 -> high_rising -#define POWMAN_PWRUP3_DIRECTION_RESET _u(0x0) -#define POWMAN_PWRUP3_DIRECTION_BITS _u(0x00000080) -#define POWMAN_PWRUP3_DIRECTION_MSB _u(7) -#define POWMAN_PWRUP3_DIRECTION_LSB _u(7) -#define POWMAN_PWRUP3_DIRECTION_ACCESS "RW" -#define POWMAN_PWRUP3_DIRECTION_VALUE_LOW_FALLING _u(0x0) -#define POWMAN_PWRUP3_DIRECTION_VALUE_HIGH_RISING _u(0x1) -// ----------------------------------------------------------------------------- -// Field : POWMAN_PWRUP3_ENABLE -// Description : Set to 1 to enable the wakeup source. Set to 0 to disable the -// wakeup source and clear a pending wakeup event. -// If using edge detect a latched edge needs to be cleared by -// writing 1 to the status register also. -#define POWMAN_PWRUP3_ENABLE_RESET _u(0x0) -#define POWMAN_PWRUP3_ENABLE_BITS _u(0x00000040) -#define POWMAN_PWRUP3_ENABLE_MSB _u(6) -#define POWMAN_PWRUP3_ENABLE_LSB _u(6) -#define POWMAN_PWRUP3_ENABLE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : POWMAN_PWRUP3_SOURCE -#define POWMAN_PWRUP3_SOURCE_RESET _u(0x3f) -#define POWMAN_PWRUP3_SOURCE_BITS _u(0x0000003f) -#define POWMAN_PWRUP3_SOURCE_MSB _u(5) -#define POWMAN_PWRUP3_SOURCE_LSB _u(0) -#define POWMAN_PWRUP3_SOURCE_ACCESS "RW" -// ============================================================================= -// Register : POWMAN_CURRENT_PWRUP_REQ -// Description : Indicates current powerup request state -// pwrup events can be cleared by removing the enable from the -// pwrup register. The alarm pwrup req can be cleared by clearing -// timer.alarm_enab -// 0 = chip reset, for the source of the last reset see -// POWMAN_CHIP_RESET -// 1 = pwrup0 -// 2 = pwrup1 -// 3 = pwrup2 -// 4 = pwrup3 -// 5 = coresight_pwrup -// 6 = alarm_pwrup -#define POWMAN_CURRENT_PWRUP_REQ_OFFSET _u(0x0000009c) -#define POWMAN_CURRENT_PWRUP_REQ_BITS _u(0x0000007f) -#define POWMAN_CURRENT_PWRUP_REQ_RESET _u(0x00000000) -#define POWMAN_CURRENT_PWRUP_REQ_MSB _u(6) -#define POWMAN_CURRENT_PWRUP_REQ_LSB _u(0) -#define POWMAN_CURRENT_PWRUP_REQ_ACCESS "RO" -// ============================================================================= -// Register : POWMAN_LAST_SWCORE_PWRUP -// Description : Indicates which pwrup source triggered the last switched-core -// power up -// 0 = chip reset, for the source of the last reset see -// POWMAN_CHIP_RESET -// 1 = pwrup0 -// 2 = pwrup1 -// 3 = pwrup2 -// 4 = pwrup3 -// 5 = coresight_pwrup -// 6 = alarm_pwrup -#define POWMAN_LAST_SWCORE_PWRUP_OFFSET _u(0x000000a0) -#define POWMAN_LAST_SWCORE_PWRUP_BITS _u(0x0000007f) -#define POWMAN_LAST_SWCORE_PWRUP_RESET _u(0x00000000) -#define POWMAN_LAST_SWCORE_PWRUP_MSB _u(6) -#define POWMAN_LAST_SWCORE_PWRUP_LSB _u(0) -#define POWMAN_LAST_SWCORE_PWRUP_ACCESS "RO" -// ============================================================================= -// Register : POWMAN_DBG_PWRCFG -#define POWMAN_DBG_PWRCFG_OFFSET _u(0x000000a4) -#define POWMAN_DBG_PWRCFG_BITS _u(0x00000001) -#define POWMAN_DBG_PWRCFG_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : POWMAN_DBG_PWRCFG_IGNORE -// Description : Ignore pwrup req from debugger. If pwrup req is asserted then -// this will prevent power down and set powerdown blocked. Set -// ignore to stop paying attention to pwrup_req -#define POWMAN_DBG_PWRCFG_IGNORE_RESET _u(0x0) -#define POWMAN_DBG_PWRCFG_IGNORE_BITS _u(0x00000001) -#define POWMAN_DBG_PWRCFG_IGNORE_MSB _u(0) -#define POWMAN_DBG_PWRCFG_IGNORE_LSB _u(0) -#define POWMAN_DBG_PWRCFG_IGNORE_ACCESS "RW" -// ============================================================================= -// Register : POWMAN_BOOTDIS -// Description : Tell the bootrom to ignore the BOOT0..3 registers following the -// next RSM reset (e.g. the next core power down/up). -// -// If an early boot stage has soft-locked some OTP pages in order -// to protect their contents from later stages, there is a risk -// that Secure code running at a later stage can unlock the pages -// by powering the core up and down. -// -// This register can be used to ensure that the bootloader runs as -// normal on the next power up, preventing Secure code at a later -// stage from accessing OTP in its unlocked state. -// -// Should be used in conjunction with the OTP BOOTDIS register. -#define POWMAN_BOOTDIS_OFFSET _u(0x000000a8) -#define POWMAN_BOOTDIS_BITS _u(0x00000003) -#define POWMAN_BOOTDIS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : POWMAN_BOOTDIS_NEXT -// Description : This flag always ORs writes into its current contents. It can -// be set but not cleared by software. -// -// The BOOTDIS_NEXT bit is OR'd into the BOOTDIS_NOW bit when the -// core is powered down. Simultaneously, the BOOTDIS_NEXT bit is -// cleared. Setting this bit means that the BOOT0..3 registers -// will be ignored following the next reset of the RSM by powman. -// -// This flag should be set by an early boot stage that has soft- -// locked OTP pages, to prevent later stages from unlocking it by -// power cycling. -#define POWMAN_BOOTDIS_NEXT_RESET _u(0x0) -#define POWMAN_BOOTDIS_NEXT_BITS _u(0x00000002) -#define POWMAN_BOOTDIS_NEXT_MSB _u(1) -#define POWMAN_BOOTDIS_NEXT_LSB _u(1) -#define POWMAN_BOOTDIS_NEXT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : POWMAN_BOOTDIS_NOW -// Description : When powman resets the RSM, the current value of BOOTDIS_NEXT -// is OR'd into BOOTDIS_NOW, and BOOTDIS_NEXT is cleared. -// -// The bootrom checks this flag before reading the BOOT0..3 -// registers. If it is set, the bootrom clears it, and ignores the -// BOOT registers. This prevents Secure software from diverting -// the boot path before a bootloader has had the chance to soft -// lock OTP pages containing sensitive data. -#define POWMAN_BOOTDIS_NOW_RESET _u(0x0) -#define POWMAN_BOOTDIS_NOW_BITS _u(0x00000001) -#define POWMAN_BOOTDIS_NOW_MSB _u(0) -#define POWMAN_BOOTDIS_NOW_LSB _u(0) -#define POWMAN_BOOTDIS_NOW_ACCESS "WC" -// ============================================================================= -// Register : POWMAN_DBGCONFIG -#define POWMAN_DBGCONFIG_OFFSET _u(0x000000ac) -#define POWMAN_DBGCONFIG_BITS _u(0x0000000f) -#define POWMAN_DBGCONFIG_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : POWMAN_DBGCONFIG_DP_INSTID -// Description : Configure DP instance ID for SWD multidrop selection. -// Recommend that this is NOT changed until you require debug -// access in multi-chip environment -#define POWMAN_DBGCONFIG_DP_INSTID_RESET _u(0x0) -#define POWMAN_DBGCONFIG_DP_INSTID_BITS _u(0x0000000f) -#define POWMAN_DBGCONFIG_DP_INSTID_MSB _u(3) -#define POWMAN_DBGCONFIG_DP_INSTID_LSB _u(0) -#define POWMAN_DBGCONFIG_DP_INSTID_ACCESS "RW" -// ============================================================================= -// Register : POWMAN_SCRATCH0 -// Description : Scratch register. Information persists in low power mode -#define POWMAN_SCRATCH0_OFFSET _u(0x000000b0) -#define POWMAN_SCRATCH0_BITS _u(0xffffffff) -#define POWMAN_SCRATCH0_RESET _u(0x00000000) -#define POWMAN_SCRATCH0_MSB _u(31) -#define POWMAN_SCRATCH0_LSB _u(0) -#define POWMAN_SCRATCH0_ACCESS "RW" -// ============================================================================= -// Register : POWMAN_SCRATCH1 -// Description : Scratch register. Information persists in low power mode -#define POWMAN_SCRATCH1_OFFSET _u(0x000000b4) -#define POWMAN_SCRATCH1_BITS _u(0xffffffff) -#define POWMAN_SCRATCH1_RESET _u(0x00000000) -#define POWMAN_SCRATCH1_MSB _u(31) -#define POWMAN_SCRATCH1_LSB _u(0) -#define POWMAN_SCRATCH1_ACCESS "RW" -// ============================================================================= -// Register : POWMAN_SCRATCH2 -// Description : Scratch register. Information persists in low power mode -#define POWMAN_SCRATCH2_OFFSET _u(0x000000b8) -#define POWMAN_SCRATCH2_BITS _u(0xffffffff) -#define POWMAN_SCRATCH2_RESET _u(0x00000000) -#define POWMAN_SCRATCH2_MSB _u(31) -#define POWMAN_SCRATCH2_LSB _u(0) -#define POWMAN_SCRATCH2_ACCESS "RW" -// ============================================================================= -// Register : POWMAN_SCRATCH3 -// Description : Scratch register. Information persists in low power mode -#define POWMAN_SCRATCH3_OFFSET _u(0x000000bc) -#define POWMAN_SCRATCH3_BITS _u(0xffffffff) -#define POWMAN_SCRATCH3_RESET _u(0x00000000) -#define POWMAN_SCRATCH3_MSB _u(31) -#define POWMAN_SCRATCH3_LSB _u(0) -#define POWMAN_SCRATCH3_ACCESS "RW" -// ============================================================================= -// Register : POWMAN_SCRATCH4 -// Description : Scratch register. Information persists in low power mode -#define POWMAN_SCRATCH4_OFFSET _u(0x000000c0) -#define POWMAN_SCRATCH4_BITS _u(0xffffffff) -#define POWMAN_SCRATCH4_RESET _u(0x00000000) -#define POWMAN_SCRATCH4_MSB _u(31) -#define POWMAN_SCRATCH4_LSB _u(0) -#define POWMAN_SCRATCH4_ACCESS "RW" -// ============================================================================= -// Register : POWMAN_SCRATCH5 -// Description : Scratch register. Information persists in low power mode -#define POWMAN_SCRATCH5_OFFSET _u(0x000000c4) -#define POWMAN_SCRATCH5_BITS _u(0xffffffff) -#define POWMAN_SCRATCH5_RESET _u(0x00000000) -#define POWMAN_SCRATCH5_MSB _u(31) -#define POWMAN_SCRATCH5_LSB _u(0) -#define POWMAN_SCRATCH5_ACCESS "RW" -// ============================================================================= -// Register : POWMAN_SCRATCH6 -// Description : Scratch register. Information persists in low power mode -#define POWMAN_SCRATCH6_OFFSET _u(0x000000c8) -#define POWMAN_SCRATCH6_BITS _u(0xffffffff) -#define POWMAN_SCRATCH6_RESET _u(0x00000000) -#define POWMAN_SCRATCH6_MSB _u(31) -#define POWMAN_SCRATCH6_LSB _u(0) -#define POWMAN_SCRATCH6_ACCESS "RW" -// ============================================================================= -// Register : POWMAN_SCRATCH7 -// Description : Scratch register. Information persists in low power mode -#define POWMAN_SCRATCH7_OFFSET _u(0x000000cc) -#define POWMAN_SCRATCH7_BITS _u(0xffffffff) -#define POWMAN_SCRATCH7_RESET _u(0x00000000) -#define POWMAN_SCRATCH7_MSB _u(31) -#define POWMAN_SCRATCH7_LSB _u(0) -#define POWMAN_SCRATCH7_ACCESS "RW" -// ============================================================================= -// Register : POWMAN_BOOT0 -// Description : Scratch register. Information persists in low power mode -#define POWMAN_BOOT0_OFFSET _u(0x000000d0) -#define POWMAN_BOOT0_BITS _u(0xffffffff) -#define POWMAN_BOOT0_RESET _u(0x00000000) -#define POWMAN_BOOT0_MSB _u(31) -#define POWMAN_BOOT0_LSB _u(0) -#define POWMAN_BOOT0_ACCESS "RW" -// ============================================================================= -// Register : POWMAN_BOOT1 -// Description : Scratch register. Information persists in low power mode -#define POWMAN_BOOT1_OFFSET _u(0x000000d4) -#define POWMAN_BOOT1_BITS _u(0xffffffff) -#define POWMAN_BOOT1_RESET _u(0x00000000) -#define POWMAN_BOOT1_MSB _u(31) -#define POWMAN_BOOT1_LSB _u(0) -#define POWMAN_BOOT1_ACCESS "RW" -// ============================================================================= -// Register : POWMAN_BOOT2 -// Description : Scratch register. Information persists in low power mode -#define POWMAN_BOOT2_OFFSET _u(0x000000d8) -#define POWMAN_BOOT2_BITS _u(0xffffffff) -#define POWMAN_BOOT2_RESET _u(0x00000000) -#define POWMAN_BOOT2_MSB _u(31) -#define POWMAN_BOOT2_LSB _u(0) -#define POWMAN_BOOT2_ACCESS "RW" -// ============================================================================= -// Register : POWMAN_BOOT3 -// Description : Scratch register. Information persists in low power mode -#define POWMAN_BOOT3_OFFSET _u(0x000000dc) -#define POWMAN_BOOT3_BITS _u(0xffffffff) -#define POWMAN_BOOT3_RESET _u(0x00000000) -#define POWMAN_BOOT3_MSB _u(31) -#define POWMAN_BOOT3_LSB _u(0) -#define POWMAN_BOOT3_ACCESS "RW" -// ============================================================================= -// Register : POWMAN_INTR -// Description : Raw Interrupts -#define POWMAN_INTR_OFFSET _u(0x000000e0) -#define POWMAN_INTR_BITS _u(0x0000000f) -#define POWMAN_INTR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : POWMAN_INTR_PWRUP_WHILE_WAITING -// Description : Source is state.pwrup_while_waiting -#define POWMAN_INTR_PWRUP_WHILE_WAITING_RESET _u(0x0) -#define POWMAN_INTR_PWRUP_WHILE_WAITING_BITS _u(0x00000008) -#define POWMAN_INTR_PWRUP_WHILE_WAITING_MSB _u(3) -#define POWMAN_INTR_PWRUP_WHILE_WAITING_LSB _u(3) -#define POWMAN_INTR_PWRUP_WHILE_WAITING_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : POWMAN_INTR_STATE_REQ_IGNORED -// Description : Source is state.req_ignored -#define POWMAN_INTR_STATE_REQ_IGNORED_RESET _u(0x0) -#define POWMAN_INTR_STATE_REQ_IGNORED_BITS _u(0x00000004) -#define POWMAN_INTR_STATE_REQ_IGNORED_MSB _u(2) -#define POWMAN_INTR_STATE_REQ_IGNORED_LSB _u(2) -#define POWMAN_INTR_STATE_REQ_IGNORED_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : POWMAN_INTR_TIMER -#define POWMAN_INTR_TIMER_RESET _u(0x0) -#define POWMAN_INTR_TIMER_BITS _u(0x00000002) -#define POWMAN_INTR_TIMER_MSB _u(1) -#define POWMAN_INTR_TIMER_LSB _u(1) -#define POWMAN_INTR_TIMER_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : POWMAN_INTR_VREG_OUTPUT_LOW -#define POWMAN_INTR_VREG_OUTPUT_LOW_RESET _u(0x0) -#define POWMAN_INTR_VREG_OUTPUT_LOW_BITS _u(0x00000001) -#define POWMAN_INTR_VREG_OUTPUT_LOW_MSB _u(0) -#define POWMAN_INTR_VREG_OUTPUT_LOW_LSB _u(0) -#define POWMAN_INTR_VREG_OUTPUT_LOW_ACCESS "WC" -// ============================================================================= -// Register : POWMAN_INTE -// Description : Interrupt Enable -#define POWMAN_INTE_OFFSET _u(0x000000e4) -#define POWMAN_INTE_BITS _u(0x0000000f) -#define POWMAN_INTE_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : POWMAN_INTE_PWRUP_WHILE_WAITING -// Description : Source is state.pwrup_while_waiting -#define POWMAN_INTE_PWRUP_WHILE_WAITING_RESET _u(0x0) -#define POWMAN_INTE_PWRUP_WHILE_WAITING_BITS _u(0x00000008) -#define POWMAN_INTE_PWRUP_WHILE_WAITING_MSB _u(3) -#define POWMAN_INTE_PWRUP_WHILE_WAITING_LSB _u(3) -#define POWMAN_INTE_PWRUP_WHILE_WAITING_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : POWMAN_INTE_STATE_REQ_IGNORED -// Description : Source is state.req_ignored -#define POWMAN_INTE_STATE_REQ_IGNORED_RESET _u(0x0) -#define POWMAN_INTE_STATE_REQ_IGNORED_BITS _u(0x00000004) -#define POWMAN_INTE_STATE_REQ_IGNORED_MSB _u(2) -#define POWMAN_INTE_STATE_REQ_IGNORED_LSB _u(2) -#define POWMAN_INTE_STATE_REQ_IGNORED_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : POWMAN_INTE_TIMER -#define POWMAN_INTE_TIMER_RESET _u(0x0) -#define POWMAN_INTE_TIMER_BITS _u(0x00000002) -#define POWMAN_INTE_TIMER_MSB _u(1) -#define POWMAN_INTE_TIMER_LSB _u(1) -#define POWMAN_INTE_TIMER_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : POWMAN_INTE_VREG_OUTPUT_LOW -#define POWMAN_INTE_VREG_OUTPUT_LOW_RESET _u(0x0) -#define POWMAN_INTE_VREG_OUTPUT_LOW_BITS _u(0x00000001) -#define POWMAN_INTE_VREG_OUTPUT_LOW_MSB _u(0) -#define POWMAN_INTE_VREG_OUTPUT_LOW_LSB _u(0) -#define POWMAN_INTE_VREG_OUTPUT_LOW_ACCESS "RW" -// ============================================================================= -// Register : POWMAN_INTF -// Description : Interrupt Force -#define POWMAN_INTF_OFFSET _u(0x000000e8) -#define POWMAN_INTF_BITS _u(0x0000000f) -#define POWMAN_INTF_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : POWMAN_INTF_PWRUP_WHILE_WAITING -// Description : Source is state.pwrup_while_waiting -#define POWMAN_INTF_PWRUP_WHILE_WAITING_RESET _u(0x0) -#define POWMAN_INTF_PWRUP_WHILE_WAITING_BITS _u(0x00000008) -#define POWMAN_INTF_PWRUP_WHILE_WAITING_MSB _u(3) -#define POWMAN_INTF_PWRUP_WHILE_WAITING_LSB _u(3) -#define POWMAN_INTF_PWRUP_WHILE_WAITING_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : POWMAN_INTF_STATE_REQ_IGNORED -// Description : Source is state.req_ignored -#define POWMAN_INTF_STATE_REQ_IGNORED_RESET _u(0x0) -#define POWMAN_INTF_STATE_REQ_IGNORED_BITS _u(0x00000004) -#define POWMAN_INTF_STATE_REQ_IGNORED_MSB _u(2) -#define POWMAN_INTF_STATE_REQ_IGNORED_LSB _u(2) -#define POWMAN_INTF_STATE_REQ_IGNORED_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : POWMAN_INTF_TIMER -#define POWMAN_INTF_TIMER_RESET _u(0x0) -#define POWMAN_INTF_TIMER_BITS _u(0x00000002) -#define POWMAN_INTF_TIMER_MSB _u(1) -#define POWMAN_INTF_TIMER_LSB _u(1) -#define POWMAN_INTF_TIMER_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : POWMAN_INTF_VREG_OUTPUT_LOW -#define POWMAN_INTF_VREG_OUTPUT_LOW_RESET _u(0x0) -#define POWMAN_INTF_VREG_OUTPUT_LOW_BITS _u(0x00000001) -#define POWMAN_INTF_VREG_OUTPUT_LOW_MSB _u(0) -#define POWMAN_INTF_VREG_OUTPUT_LOW_LSB _u(0) -#define POWMAN_INTF_VREG_OUTPUT_LOW_ACCESS "RW" -// ============================================================================= -// Register : POWMAN_INTS -// Description : Interrupt status after masking & forcing -#define POWMAN_INTS_OFFSET _u(0x000000ec) -#define POWMAN_INTS_BITS _u(0x0000000f) -#define POWMAN_INTS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : POWMAN_INTS_PWRUP_WHILE_WAITING -// Description : Source is state.pwrup_while_waiting -#define POWMAN_INTS_PWRUP_WHILE_WAITING_RESET _u(0x0) -#define POWMAN_INTS_PWRUP_WHILE_WAITING_BITS _u(0x00000008) -#define POWMAN_INTS_PWRUP_WHILE_WAITING_MSB _u(3) -#define POWMAN_INTS_PWRUP_WHILE_WAITING_LSB _u(3) -#define POWMAN_INTS_PWRUP_WHILE_WAITING_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : POWMAN_INTS_STATE_REQ_IGNORED -// Description : Source is state.req_ignored -#define POWMAN_INTS_STATE_REQ_IGNORED_RESET _u(0x0) -#define POWMAN_INTS_STATE_REQ_IGNORED_BITS _u(0x00000004) -#define POWMAN_INTS_STATE_REQ_IGNORED_MSB _u(2) -#define POWMAN_INTS_STATE_REQ_IGNORED_LSB _u(2) -#define POWMAN_INTS_STATE_REQ_IGNORED_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : POWMAN_INTS_TIMER -#define POWMAN_INTS_TIMER_RESET _u(0x0) -#define POWMAN_INTS_TIMER_BITS _u(0x00000002) -#define POWMAN_INTS_TIMER_MSB _u(1) -#define POWMAN_INTS_TIMER_LSB _u(1) -#define POWMAN_INTS_TIMER_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : POWMAN_INTS_VREG_OUTPUT_LOW -#define POWMAN_INTS_VREG_OUTPUT_LOW_RESET _u(0x0) -#define POWMAN_INTS_VREG_OUTPUT_LOW_BITS _u(0x00000001) -#define POWMAN_INTS_VREG_OUTPUT_LOW_MSB _u(0) -#define POWMAN_INTS_VREG_OUTPUT_LOW_LSB _u(0) -#define POWMAN_INTS_VREG_OUTPUT_LOW_ACCESS "RO" -// ============================================================================= -#endif // _HARDWARE_REGS_POWMAN_H - diff --git a/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/psm.h b/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/psm.h deleted file mode 100644 index cad268a36e..0000000000 --- a/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/psm.h +++ /dev/null @@ -1,741 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -// ============================================================================= -// Register block : PSM -// Version : 1 -// Bus type : apb -// ============================================================================= -#ifndef _HARDWARE_REGS_PSM_H -#define _HARDWARE_REGS_PSM_H -// ============================================================================= -// Register : PSM_FRCE_ON -// Description : Force block out of reset (i.e. power it on) -#define PSM_FRCE_ON_OFFSET _u(0x00000000) -#define PSM_FRCE_ON_BITS _u(0x01ffffff) -#define PSM_FRCE_ON_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : PSM_FRCE_ON_PROC1 -#define PSM_FRCE_ON_PROC1_RESET _u(0x0) -#define PSM_FRCE_ON_PROC1_BITS _u(0x01000000) -#define PSM_FRCE_ON_PROC1_MSB _u(24) -#define PSM_FRCE_ON_PROC1_LSB _u(24) -#define PSM_FRCE_ON_PROC1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PSM_FRCE_ON_PROC0 -#define PSM_FRCE_ON_PROC0_RESET _u(0x0) -#define PSM_FRCE_ON_PROC0_BITS _u(0x00800000) -#define PSM_FRCE_ON_PROC0_MSB _u(23) -#define PSM_FRCE_ON_PROC0_LSB _u(23) -#define PSM_FRCE_ON_PROC0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PSM_FRCE_ON_ACCESSCTRL -#define PSM_FRCE_ON_ACCESSCTRL_RESET _u(0x0) -#define PSM_FRCE_ON_ACCESSCTRL_BITS _u(0x00400000) -#define PSM_FRCE_ON_ACCESSCTRL_MSB _u(22) -#define PSM_FRCE_ON_ACCESSCTRL_LSB _u(22) -#define PSM_FRCE_ON_ACCESSCTRL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PSM_FRCE_ON_SIO -#define PSM_FRCE_ON_SIO_RESET _u(0x0) -#define PSM_FRCE_ON_SIO_BITS _u(0x00200000) -#define PSM_FRCE_ON_SIO_MSB _u(21) -#define PSM_FRCE_ON_SIO_LSB _u(21) -#define PSM_FRCE_ON_SIO_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PSM_FRCE_ON_XIP -#define PSM_FRCE_ON_XIP_RESET _u(0x0) -#define PSM_FRCE_ON_XIP_BITS _u(0x00100000) -#define PSM_FRCE_ON_XIP_MSB _u(20) -#define PSM_FRCE_ON_XIP_LSB _u(20) -#define PSM_FRCE_ON_XIP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PSM_FRCE_ON_SRAM9 -#define PSM_FRCE_ON_SRAM9_RESET _u(0x0) -#define PSM_FRCE_ON_SRAM9_BITS _u(0x00080000) -#define PSM_FRCE_ON_SRAM9_MSB _u(19) -#define PSM_FRCE_ON_SRAM9_LSB _u(19) -#define PSM_FRCE_ON_SRAM9_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PSM_FRCE_ON_SRAM8 -#define PSM_FRCE_ON_SRAM8_RESET _u(0x0) -#define PSM_FRCE_ON_SRAM8_BITS _u(0x00040000) -#define PSM_FRCE_ON_SRAM8_MSB _u(18) -#define PSM_FRCE_ON_SRAM8_LSB _u(18) -#define PSM_FRCE_ON_SRAM8_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PSM_FRCE_ON_SRAM7 -#define PSM_FRCE_ON_SRAM7_RESET _u(0x0) -#define PSM_FRCE_ON_SRAM7_BITS _u(0x00020000) -#define PSM_FRCE_ON_SRAM7_MSB _u(17) -#define PSM_FRCE_ON_SRAM7_LSB _u(17) -#define PSM_FRCE_ON_SRAM7_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PSM_FRCE_ON_SRAM6 -#define PSM_FRCE_ON_SRAM6_RESET _u(0x0) -#define PSM_FRCE_ON_SRAM6_BITS _u(0x00010000) -#define PSM_FRCE_ON_SRAM6_MSB _u(16) -#define PSM_FRCE_ON_SRAM6_LSB _u(16) -#define PSM_FRCE_ON_SRAM6_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PSM_FRCE_ON_SRAM5 -#define PSM_FRCE_ON_SRAM5_RESET _u(0x0) -#define PSM_FRCE_ON_SRAM5_BITS _u(0x00008000) -#define PSM_FRCE_ON_SRAM5_MSB _u(15) -#define PSM_FRCE_ON_SRAM5_LSB _u(15) -#define PSM_FRCE_ON_SRAM5_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PSM_FRCE_ON_SRAM4 -#define PSM_FRCE_ON_SRAM4_RESET _u(0x0) -#define PSM_FRCE_ON_SRAM4_BITS _u(0x00004000) -#define PSM_FRCE_ON_SRAM4_MSB _u(14) -#define PSM_FRCE_ON_SRAM4_LSB _u(14) -#define PSM_FRCE_ON_SRAM4_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PSM_FRCE_ON_SRAM3 -#define PSM_FRCE_ON_SRAM3_RESET _u(0x0) -#define PSM_FRCE_ON_SRAM3_BITS _u(0x00002000) -#define PSM_FRCE_ON_SRAM3_MSB _u(13) -#define PSM_FRCE_ON_SRAM3_LSB _u(13) -#define PSM_FRCE_ON_SRAM3_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PSM_FRCE_ON_SRAM2 -#define PSM_FRCE_ON_SRAM2_RESET _u(0x0) -#define PSM_FRCE_ON_SRAM2_BITS _u(0x00001000) -#define PSM_FRCE_ON_SRAM2_MSB _u(12) -#define PSM_FRCE_ON_SRAM2_LSB _u(12) -#define PSM_FRCE_ON_SRAM2_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PSM_FRCE_ON_SRAM1 -#define PSM_FRCE_ON_SRAM1_RESET _u(0x0) -#define PSM_FRCE_ON_SRAM1_BITS _u(0x00000800) -#define PSM_FRCE_ON_SRAM1_MSB _u(11) -#define PSM_FRCE_ON_SRAM1_LSB _u(11) -#define PSM_FRCE_ON_SRAM1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PSM_FRCE_ON_SRAM0 -#define PSM_FRCE_ON_SRAM0_RESET _u(0x0) -#define PSM_FRCE_ON_SRAM0_BITS _u(0x00000400) -#define PSM_FRCE_ON_SRAM0_MSB _u(10) -#define PSM_FRCE_ON_SRAM0_LSB _u(10) -#define PSM_FRCE_ON_SRAM0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PSM_FRCE_ON_BOOTRAM -#define PSM_FRCE_ON_BOOTRAM_RESET _u(0x0) -#define PSM_FRCE_ON_BOOTRAM_BITS _u(0x00000200) -#define PSM_FRCE_ON_BOOTRAM_MSB _u(9) -#define PSM_FRCE_ON_BOOTRAM_LSB _u(9) -#define PSM_FRCE_ON_BOOTRAM_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PSM_FRCE_ON_ROM -#define PSM_FRCE_ON_ROM_RESET _u(0x0) -#define PSM_FRCE_ON_ROM_BITS _u(0x00000100) -#define PSM_FRCE_ON_ROM_MSB _u(8) -#define PSM_FRCE_ON_ROM_LSB _u(8) -#define PSM_FRCE_ON_ROM_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PSM_FRCE_ON_BUSFABRIC -#define PSM_FRCE_ON_BUSFABRIC_RESET _u(0x0) -#define PSM_FRCE_ON_BUSFABRIC_BITS _u(0x00000080) -#define PSM_FRCE_ON_BUSFABRIC_MSB _u(7) -#define PSM_FRCE_ON_BUSFABRIC_LSB _u(7) -#define PSM_FRCE_ON_BUSFABRIC_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PSM_FRCE_ON_PSM_READY -#define PSM_FRCE_ON_PSM_READY_RESET _u(0x0) -#define PSM_FRCE_ON_PSM_READY_BITS _u(0x00000040) -#define PSM_FRCE_ON_PSM_READY_MSB _u(6) -#define PSM_FRCE_ON_PSM_READY_LSB _u(6) -#define PSM_FRCE_ON_PSM_READY_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PSM_FRCE_ON_CLOCKS -#define PSM_FRCE_ON_CLOCKS_RESET _u(0x0) -#define PSM_FRCE_ON_CLOCKS_BITS _u(0x00000020) -#define PSM_FRCE_ON_CLOCKS_MSB _u(5) -#define PSM_FRCE_ON_CLOCKS_LSB _u(5) -#define PSM_FRCE_ON_CLOCKS_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PSM_FRCE_ON_RESETS -#define PSM_FRCE_ON_RESETS_RESET _u(0x0) -#define PSM_FRCE_ON_RESETS_BITS _u(0x00000010) -#define PSM_FRCE_ON_RESETS_MSB _u(4) -#define PSM_FRCE_ON_RESETS_LSB _u(4) -#define PSM_FRCE_ON_RESETS_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PSM_FRCE_ON_XOSC -#define PSM_FRCE_ON_XOSC_RESET _u(0x0) -#define PSM_FRCE_ON_XOSC_BITS _u(0x00000008) -#define PSM_FRCE_ON_XOSC_MSB _u(3) -#define PSM_FRCE_ON_XOSC_LSB _u(3) -#define PSM_FRCE_ON_XOSC_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PSM_FRCE_ON_ROSC -#define PSM_FRCE_ON_ROSC_RESET _u(0x0) -#define PSM_FRCE_ON_ROSC_BITS _u(0x00000004) -#define PSM_FRCE_ON_ROSC_MSB _u(2) -#define PSM_FRCE_ON_ROSC_LSB _u(2) -#define PSM_FRCE_ON_ROSC_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PSM_FRCE_ON_OTP -#define PSM_FRCE_ON_OTP_RESET _u(0x0) -#define PSM_FRCE_ON_OTP_BITS _u(0x00000002) -#define PSM_FRCE_ON_OTP_MSB _u(1) -#define PSM_FRCE_ON_OTP_LSB _u(1) -#define PSM_FRCE_ON_OTP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PSM_FRCE_ON_PROC_COLD -#define PSM_FRCE_ON_PROC_COLD_RESET _u(0x0) -#define PSM_FRCE_ON_PROC_COLD_BITS _u(0x00000001) -#define PSM_FRCE_ON_PROC_COLD_MSB _u(0) -#define PSM_FRCE_ON_PROC_COLD_LSB _u(0) -#define PSM_FRCE_ON_PROC_COLD_ACCESS "RW" -// ============================================================================= -// Register : PSM_FRCE_OFF -// Description : Force into reset (i.e. power it off) -#define PSM_FRCE_OFF_OFFSET _u(0x00000004) -#define PSM_FRCE_OFF_BITS _u(0x01ffffff) -#define PSM_FRCE_OFF_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : PSM_FRCE_OFF_PROC1 -#define PSM_FRCE_OFF_PROC1_RESET _u(0x0) -#define PSM_FRCE_OFF_PROC1_BITS _u(0x01000000) -#define PSM_FRCE_OFF_PROC1_MSB _u(24) -#define PSM_FRCE_OFF_PROC1_LSB _u(24) -#define PSM_FRCE_OFF_PROC1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PSM_FRCE_OFF_PROC0 -#define PSM_FRCE_OFF_PROC0_RESET _u(0x0) -#define PSM_FRCE_OFF_PROC0_BITS _u(0x00800000) -#define PSM_FRCE_OFF_PROC0_MSB _u(23) -#define PSM_FRCE_OFF_PROC0_LSB _u(23) -#define PSM_FRCE_OFF_PROC0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PSM_FRCE_OFF_ACCESSCTRL -#define PSM_FRCE_OFF_ACCESSCTRL_RESET _u(0x0) -#define PSM_FRCE_OFF_ACCESSCTRL_BITS _u(0x00400000) -#define PSM_FRCE_OFF_ACCESSCTRL_MSB _u(22) -#define PSM_FRCE_OFF_ACCESSCTRL_LSB _u(22) -#define PSM_FRCE_OFF_ACCESSCTRL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PSM_FRCE_OFF_SIO -#define PSM_FRCE_OFF_SIO_RESET _u(0x0) -#define PSM_FRCE_OFF_SIO_BITS _u(0x00200000) -#define PSM_FRCE_OFF_SIO_MSB _u(21) -#define PSM_FRCE_OFF_SIO_LSB _u(21) -#define PSM_FRCE_OFF_SIO_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PSM_FRCE_OFF_XIP -#define PSM_FRCE_OFF_XIP_RESET _u(0x0) -#define PSM_FRCE_OFF_XIP_BITS _u(0x00100000) -#define PSM_FRCE_OFF_XIP_MSB _u(20) -#define PSM_FRCE_OFF_XIP_LSB _u(20) -#define PSM_FRCE_OFF_XIP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PSM_FRCE_OFF_SRAM9 -#define PSM_FRCE_OFF_SRAM9_RESET _u(0x0) -#define PSM_FRCE_OFF_SRAM9_BITS _u(0x00080000) -#define PSM_FRCE_OFF_SRAM9_MSB _u(19) -#define PSM_FRCE_OFF_SRAM9_LSB _u(19) -#define PSM_FRCE_OFF_SRAM9_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PSM_FRCE_OFF_SRAM8 -#define PSM_FRCE_OFF_SRAM8_RESET _u(0x0) -#define PSM_FRCE_OFF_SRAM8_BITS _u(0x00040000) -#define PSM_FRCE_OFF_SRAM8_MSB _u(18) -#define PSM_FRCE_OFF_SRAM8_LSB _u(18) -#define PSM_FRCE_OFF_SRAM8_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PSM_FRCE_OFF_SRAM7 -#define PSM_FRCE_OFF_SRAM7_RESET _u(0x0) -#define PSM_FRCE_OFF_SRAM7_BITS _u(0x00020000) -#define PSM_FRCE_OFF_SRAM7_MSB _u(17) -#define PSM_FRCE_OFF_SRAM7_LSB _u(17) -#define PSM_FRCE_OFF_SRAM7_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PSM_FRCE_OFF_SRAM6 -#define PSM_FRCE_OFF_SRAM6_RESET _u(0x0) -#define PSM_FRCE_OFF_SRAM6_BITS _u(0x00010000) -#define PSM_FRCE_OFF_SRAM6_MSB _u(16) -#define PSM_FRCE_OFF_SRAM6_LSB _u(16) -#define PSM_FRCE_OFF_SRAM6_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PSM_FRCE_OFF_SRAM5 -#define PSM_FRCE_OFF_SRAM5_RESET _u(0x0) -#define PSM_FRCE_OFF_SRAM5_BITS _u(0x00008000) -#define PSM_FRCE_OFF_SRAM5_MSB _u(15) -#define PSM_FRCE_OFF_SRAM5_LSB _u(15) -#define PSM_FRCE_OFF_SRAM5_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PSM_FRCE_OFF_SRAM4 -#define PSM_FRCE_OFF_SRAM4_RESET _u(0x0) -#define PSM_FRCE_OFF_SRAM4_BITS _u(0x00004000) -#define PSM_FRCE_OFF_SRAM4_MSB _u(14) -#define PSM_FRCE_OFF_SRAM4_LSB _u(14) -#define PSM_FRCE_OFF_SRAM4_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PSM_FRCE_OFF_SRAM3 -#define PSM_FRCE_OFF_SRAM3_RESET _u(0x0) -#define PSM_FRCE_OFF_SRAM3_BITS _u(0x00002000) -#define PSM_FRCE_OFF_SRAM3_MSB _u(13) -#define PSM_FRCE_OFF_SRAM3_LSB _u(13) -#define PSM_FRCE_OFF_SRAM3_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PSM_FRCE_OFF_SRAM2 -#define PSM_FRCE_OFF_SRAM2_RESET _u(0x0) -#define PSM_FRCE_OFF_SRAM2_BITS _u(0x00001000) -#define PSM_FRCE_OFF_SRAM2_MSB _u(12) -#define PSM_FRCE_OFF_SRAM2_LSB _u(12) -#define PSM_FRCE_OFF_SRAM2_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PSM_FRCE_OFF_SRAM1 -#define PSM_FRCE_OFF_SRAM1_RESET _u(0x0) -#define PSM_FRCE_OFF_SRAM1_BITS _u(0x00000800) -#define PSM_FRCE_OFF_SRAM1_MSB _u(11) -#define PSM_FRCE_OFF_SRAM1_LSB _u(11) -#define PSM_FRCE_OFF_SRAM1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PSM_FRCE_OFF_SRAM0 -#define PSM_FRCE_OFF_SRAM0_RESET _u(0x0) -#define PSM_FRCE_OFF_SRAM0_BITS _u(0x00000400) -#define PSM_FRCE_OFF_SRAM0_MSB _u(10) -#define PSM_FRCE_OFF_SRAM0_LSB _u(10) -#define PSM_FRCE_OFF_SRAM0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PSM_FRCE_OFF_BOOTRAM -#define PSM_FRCE_OFF_BOOTRAM_RESET _u(0x0) -#define PSM_FRCE_OFF_BOOTRAM_BITS _u(0x00000200) -#define PSM_FRCE_OFF_BOOTRAM_MSB _u(9) -#define PSM_FRCE_OFF_BOOTRAM_LSB _u(9) -#define PSM_FRCE_OFF_BOOTRAM_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PSM_FRCE_OFF_ROM -#define PSM_FRCE_OFF_ROM_RESET _u(0x0) -#define PSM_FRCE_OFF_ROM_BITS _u(0x00000100) -#define PSM_FRCE_OFF_ROM_MSB _u(8) -#define PSM_FRCE_OFF_ROM_LSB _u(8) -#define PSM_FRCE_OFF_ROM_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PSM_FRCE_OFF_BUSFABRIC -#define PSM_FRCE_OFF_BUSFABRIC_RESET _u(0x0) -#define PSM_FRCE_OFF_BUSFABRIC_BITS _u(0x00000080) -#define PSM_FRCE_OFF_BUSFABRIC_MSB _u(7) -#define PSM_FRCE_OFF_BUSFABRIC_LSB _u(7) -#define PSM_FRCE_OFF_BUSFABRIC_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PSM_FRCE_OFF_PSM_READY -#define PSM_FRCE_OFF_PSM_READY_RESET _u(0x0) -#define PSM_FRCE_OFF_PSM_READY_BITS _u(0x00000040) -#define PSM_FRCE_OFF_PSM_READY_MSB _u(6) -#define PSM_FRCE_OFF_PSM_READY_LSB _u(6) -#define PSM_FRCE_OFF_PSM_READY_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PSM_FRCE_OFF_CLOCKS -#define PSM_FRCE_OFF_CLOCKS_RESET _u(0x0) -#define PSM_FRCE_OFF_CLOCKS_BITS _u(0x00000020) -#define PSM_FRCE_OFF_CLOCKS_MSB _u(5) -#define PSM_FRCE_OFF_CLOCKS_LSB _u(5) -#define PSM_FRCE_OFF_CLOCKS_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PSM_FRCE_OFF_RESETS -#define PSM_FRCE_OFF_RESETS_RESET _u(0x0) -#define PSM_FRCE_OFF_RESETS_BITS _u(0x00000010) -#define PSM_FRCE_OFF_RESETS_MSB _u(4) -#define PSM_FRCE_OFF_RESETS_LSB _u(4) -#define PSM_FRCE_OFF_RESETS_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PSM_FRCE_OFF_XOSC -#define PSM_FRCE_OFF_XOSC_RESET _u(0x0) -#define PSM_FRCE_OFF_XOSC_BITS _u(0x00000008) -#define PSM_FRCE_OFF_XOSC_MSB _u(3) -#define PSM_FRCE_OFF_XOSC_LSB _u(3) -#define PSM_FRCE_OFF_XOSC_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PSM_FRCE_OFF_ROSC -#define PSM_FRCE_OFF_ROSC_RESET _u(0x0) -#define PSM_FRCE_OFF_ROSC_BITS _u(0x00000004) -#define PSM_FRCE_OFF_ROSC_MSB _u(2) -#define PSM_FRCE_OFF_ROSC_LSB _u(2) -#define PSM_FRCE_OFF_ROSC_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PSM_FRCE_OFF_OTP -#define PSM_FRCE_OFF_OTP_RESET _u(0x0) -#define PSM_FRCE_OFF_OTP_BITS _u(0x00000002) -#define PSM_FRCE_OFF_OTP_MSB _u(1) -#define PSM_FRCE_OFF_OTP_LSB _u(1) -#define PSM_FRCE_OFF_OTP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PSM_FRCE_OFF_PROC_COLD -#define PSM_FRCE_OFF_PROC_COLD_RESET _u(0x0) -#define PSM_FRCE_OFF_PROC_COLD_BITS _u(0x00000001) -#define PSM_FRCE_OFF_PROC_COLD_MSB _u(0) -#define PSM_FRCE_OFF_PROC_COLD_LSB _u(0) -#define PSM_FRCE_OFF_PROC_COLD_ACCESS "RW" -// ============================================================================= -// Register : PSM_WDSEL -// Description : Set to 1 if the watchdog should reset this -#define PSM_WDSEL_OFFSET _u(0x00000008) -#define PSM_WDSEL_BITS _u(0x01ffffff) -#define PSM_WDSEL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : PSM_WDSEL_PROC1 -#define PSM_WDSEL_PROC1_RESET _u(0x0) -#define PSM_WDSEL_PROC1_BITS _u(0x01000000) -#define PSM_WDSEL_PROC1_MSB _u(24) -#define PSM_WDSEL_PROC1_LSB _u(24) -#define PSM_WDSEL_PROC1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PSM_WDSEL_PROC0 -#define PSM_WDSEL_PROC0_RESET _u(0x0) -#define PSM_WDSEL_PROC0_BITS _u(0x00800000) -#define PSM_WDSEL_PROC0_MSB _u(23) -#define PSM_WDSEL_PROC0_LSB _u(23) -#define PSM_WDSEL_PROC0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PSM_WDSEL_ACCESSCTRL -#define PSM_WDSEL_ACCESSCTRL_RESET _u(0x0) -#define PSM_WDSEL_ACCESSCTRL_BITS _u(0x00400000) -#define PSM_WDSEL_ACCESSCTRL_MSB _u(22) -#define PSM_WDSEL_ACCESSCTRL_LSB _u(22) -#define PSM_WDSEL_ACCESSCTRL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PSM_WDSEL_SIO -#define PSM_WDSEL_SIO_RESET _u(0x0) -#define PSM_WDSEL_SIO_BITS _u(0x00200000) -#define PSM_WDSEL_SIO_MSB _u(21) -#define PSM_WDSEL_SIO_LSB _u(21) -#define PSM_WDSEL_SIO_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PSM_WDSEL_XIP -#define PSM_WDSEL_XIP_RESET _u(0x0) -#define PSM_WDSEL_XIP_BITS _u(0x00100000) -#define PSM_WDSEL_XIP_MSB _u(20) -#define PSM_WDSEL_XIP_LSB _u(20) -#define PSM_WDSEL_XIP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PSM_WDSEL_SRAM9 -#define PSM_WDSEL_SRAM9_RESET _u(0x0) -#define PSM_WDSEL_SRAM9_BITS _u(0x00080000) -#define PSM_WDSEL_SRAM9_MSB _u(19) -#define PSM_WDSEL_SRAM9_LSB _u(19) -#define PSM_WDSEL_SRAM9_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PSM_WDSEL_SRAM8 -#define PSM_WDSEL_SRAM8_RESET _u(0x0) -#define PSM_WDSEL_SRAM8_BITS _u(0x00040000) -#define PSM_WDSEL_SRAM8_MSB _u(18) -#define PSM_WDSEL_SRAM8_LSB _u(18) -#define PSM_WDSEL_SRAM8_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PSM_WDSEL_SRAM7 -#define PSM_WDSEL_SRAM7_RESET _u(0x0) -#define PSM_WDSEL_SRAM7_BITS _u(0x00020000) -#define PSM_WDSEL_SRAM7_MSB _u(17) -#define PSM_WDSEL_SRAM7_LSB _u(17) -#define PSM_WDSEL_SRAM7_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PSM_WDSEL_SRAM6 -#define PSM_WDSEL_SRAM6_RESET _u(0x0) -#define PSM_WDSEL_SRAM6_BITS _u(0x00010000) -#define PSM_WDSEL_SRAM6_MSB _u(16) -#define PSM_WDSEL_SRAM6_LSB _u(16) -#define PSM_WDSEL_SRAM6_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PSM_WDSEL_SRAM5 -#define PSM_WDSEL_SRAM5_RESET _u(0x0) -#define PSM_WDSEL_SRAM5_BITS _u(0x00008000) -#define PSM_WDSEL_SRAM5_MSB _u(15) -#define PSM_WDSEL_SRAM5_LSB _u(15) -#define PSM_WDSEL_SRAM5_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PSM_WDSEL_SRAM4 -#define PSM_WDSEL_SRAM4_RESET _u(0x0) -#define PSM_WDSEL_SRAM4_BITS _u(0x00004000) -#define PSM_WDSEL_SRAM4_MSB _u(14) -#define PSM_WDSEL_SRAM4_LSB _u(14) -#define PSM_WDSEL_SRAM4_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PSM_WDSEL_SRAM3 -#define PSM_WDSEL_SRAM3_RESET _u(0x0) -#define PSM_WDSEL_SRAM3_BITS _u(0x00002000) -#define PSM_WDSEL_SRAM3_MSB _u(13) -#define PSM_WDSEL_SRAM3_LSB _u(13) -#define PSM_WDSEL_SRAM3_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PSM_WDSEL_SRAM2 -#define PSM_WDSEL_SRAM2_RESET _u(0x0) -#define PSM_WDSEL_SRAM2_BITS _u(0x00001000) -#define PSM_WDSEL_SRAM2_MSB _u(12) -#define PSM_WDSEL_SRAM2_LSB _u(12) -#define PSM_WDSEL_SRAM2_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PSM_WDSEL_SRAM1 -#define PSM_WDSEL_SRAM1_RESET _u(0x0) -#define PSM_WDSEL_SRAM1_BITS _u(0x00000800) -#define PSM_WDSEL_SRAM1_MSB _u(11) -#define PSM_WDSEL_SRAM1_LSB _u(11) -#define PSM_WDSEL_SRAM1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PSM_WDSEL_SRAM0 -#define PSM_WDSEL_SRAM0_RESET _u(0x0) -#define PSM_WDSEL_SRAM0_BITS _u(0x00000400) -#define PSM_WDSEL_SRAM0_MSB _u(10) -#define PSM_WDSEL_SRAM0_LSB _u(10) -#define PSM_WDSEL_SRAM0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PSM_WDSEL_BOOTRAM -#define PSM_WDSEL_BOOTRAM_RESET _u(0x0) -#define PSM_WDSEL_BOOTRAM_BITS _u(0x00000200) -#define PSM_WDSEL_BOOTRAM_MSB _u(9) -#define PSM_WDSEL_BOOTRAM_LSB _u(9) -#define PSM_WDSEL_BOOTRAM_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PSM_WDSEL_ROM -#define PSM_WDSEL_ROM_RESET _u(0x0) -#define PSM_WDSEL_ROM_BITS _u(0x00000100) -#define PSM_WDSEL_ROM_MSB _u(8) -#define PSM_WDSEL_ROM_LSB _u(8) -#define PSM_WDSEL_ROM_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PSM_WDSEL_BUSFABRIC -#define PSM_WDSEL_BUSFABRIC_RESET _u(0x0) -#define PSM_WDSEL_BUSFABRIC_BITS _u(0x00000080) -#define PSM_WDSEL_BUSFABRIC_MSB _u(7) -#define PSM_WDSEL_BUSFABRIC_LSB _u(7) -#define PSM_WDSEL_BUSFABRIC_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PSM_WDSEL_PSM_READY -#define PSM_WDSEL_PSM_READY_RESET _u(0x0) -#define PSM_WDSEL_PSM_READY_BITS _u(0x00000040) -#define PSM_WDSEL_PSM_READY_MSB _u(6) -#define PSM_WDSEL_PSM_READY_LSB _u(6) -#define PSM_WDSEL_PSM_READY_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PSM_WDSEL_CLOCKS -#define PSM_WDSEL_CLOCKS_RESET _u(0x0) -#define PSM_WDSEL_CLOCKS_BITS _u(0x00000020) -#define PSM_WDSEL_CLOCKS_MSB _u(5) -#define PSM_WDSEL_CLOCKS_LSB _u(5) -#define PSM_WDSEL_CLOCKS_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PSM_WDSEL_RESETS -#define PSM_WDSEL_RESETS_RESET _u(0x0) -#define PSM_WDSEL_RESETS_BITS _u(0x00000010) -#define PSM_WDSEL_RESETS_MSB _u(4) -#define PSM_WDSEL_RESETS_LSB _u(4) -#define PSM_WDSEL_RESETS_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PSM_WDSEL_XOSC -#define PSM_WDSEL_XOSC_RESET _u(0x0) -#define PSM_WDSEL_XOSC_BITS _u(0x00000008) -#define PSM_WDSEL_XOSC_MSB _u(3) -#define PSM_WDSEL_XOSC_LSB _u(3) -#define PSM_WDSEL_XOSC_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PSM_WDSEL_ROSC -#define PSM_WDSEL_ROSC_RESET _u(0x0) -#define PSM_WDSEL_ROSC_BITS _u(0x00000004) -#define PSM_WDSEL_ROSC_MSB _u(2) -#define PSM_WDSEL_ROSC_LSB _u(2) -#define PSM_WDSEL_ROSC_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PSM_WDSEL_OTP -#define PSM_WDSEL_OTP_RESET _u(0x0) -#define PSM_WDSEL_OTP_BITS _u(0x00000002) -#define PSM_WDSEL_OTP_MSB _u(1) -#define PSM_WDSEL_OTP_LSB _u(1) -#define PSM_WDSEL_OTP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PSM_WDSEL_PROC_COLD -#define PSM_WDSEL_PROC_COLD_RESET _u(0x0) -#define PSM_WDSEL_PROC_COLD_BITS _u(0x00000001) -#define PSM_WDSEL_PROC_COLD_MSB _u(0) -#define PSM_WDSEL_PROC_COLD_LSB _u(0) -#define PSM_WDSEL_PROC_COLD_ACCESS "RW" -// ============================================================================= -// Register : PSM_DONE -// Description : Is the subsystem ready? -#define PSM_DONE_OFFSET _u(0x0000000c) -#define PSM_DONE_BITS _u(0x01ffffff) -#define PSM_DONE_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : PSM_DONE_PROC1 -#define PSM_DONE_PROC1_RESET _u(0x0) -#define PSM_DONE_PROC1_BITS _u(0x01000000) -#define PSM_DONE_PROC1_MSB _u(24) -#define PSM_DONE_PROC1_LSB _u(24) -#define PSM_DONE_PROC1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PSM_DONE_PROC0 -#define PSM_DONE_PROC0_RESET _u(0x0) -#define PSM_DONE_PROC0_BITS _u(0x00800000) -#define PSM_DONE_PROC0_MSB _u(23) -#define PSM_DONE_PROC0_LSB _u(23) -#define PSM_DONE_PROC0_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PSM_DONE_ACCESSCTRL -#define PSM_DONE_ACCESSCTRL_RESET _u(0x0) -#define PSM_DONE_ACCESSCTRL_BITS _u(0x00400000) -#define PSM_DONE_ACCESSCTRL_MSB _u(22) -#define PSM_DONE_ACCESSCTRL_LSB _u(22) -#define PSM_DONE_ACCESSCTRL_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PSM_DONE_SIO -#define PSM_DONE_SIO_RESET _u(0x0) -#define PSM_DONE_SIO_BITS _u(0x00200000) -#define PSM_DONE_SIO_MSB _u(21) -#define PSM_DONE_SIO_LSB _u(21) -#define PSM_DONE_SIO_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PSM_DONE_XIP -#define PSM_DONE_XIP_RESET _u(0x0) -#define PSM_DONE_XIP_BITS _u(0x00100000) -#define PSM_DONE_XIP_MSB _u(20) -#define PSM_DONE_XIP_LSB _u(20) -#define PSM_DONE_XIP_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PSM_DONE_SRAM9 -#define PSM_DONE_SRAM9_RESET _u(0x0) -#define PSM_DONE_SRAM9_BITS _u(0x00080000) -#define PSM_DONE_SRAM9_MSB _u(19) -#define PSM_DONE_SRAM9_LSB _u(19) -#define PSM_DONE_SRAM9_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PSM_DONE_SRAM8 -#define PSM_DONE_SRAM8_RESET _u(0x0) -#define PSM_DONE_SRAM8_BITS _u(0x00040000) -#define PSM_DONE_SRAM8_MSB _u(18) -#define PSM_DONE_SRAM8_LSB _u(18) -#define PSM_DONE_SRAM8_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PSM_DONE_SRAM7 -#define PSM_DONE_SRAM7_RESET _u(0x0) -#define PSM_DONE_SRAM7_BITS _u(0x00020000) -#define PSM_DONE_SRAM7_MSB _u(17) -#define PSM_DONE_SRAM7_LSB _u(17) -#define PSM_DONE_SRAM7_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PSM_DONE_SRAM6 -#define PSM_DONE_SRAM6_RESET _u(0x0) -#define PSM_DONE_SRAM6_BITS _u(0x00010000) -#define PSM_DONE_SRAM6_MSB _u(16) -#define PSM_DONE_SRAM6_LSB _u(16) -#define PSM_DONE_SRAM6_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PSM_DONE_SRAM5 -#define PSM_DONE_SRAM5_RESET _u(0x0) -#define PSM_DONE_SRAM5_BITS _u(0x00008000) -#define PSM_DONE_SRAM5_MSB _u(15) -#define PSM_DONE_SRAM5_LSB _u(15) -#define PSM_DONE_SRAM5_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PSM_DONE_SRAM4 -#define PSM_DONE_SRAM4_RESET _u(0x0) -#define PSM_DONE_SRAM4_BITS _u(0x00004000) -#define PSM_DONE_SRAM4_MSB _u(14) -#define PSM_DONE_SRAM4_LSB _u(14) -#define PSM_DONE_SRAM4_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PSM_DONE_SRAM3 -#define PSM_DONE_SRAM3_RESET _u(0x0) -#define PSM_DONE_SRAM3_BITS _u(0x00002000) -#define PSM_DONE_SRAM3_MSB _u(13) -#define PSM_DONE_SRAM3_LSB _u(13) -#define PSM_DONE_SRAM3_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PSM_DONE_SRAM2 -#define PSM_DONE_SRAM2_RESET _u(0x0) -#define PSM_DONE_SRAM2_BITS _u(0x00001000) -#define PSM_DONE_SRAM2_MSB _u(12) -#define PSM_DONE_SRAM2_LSB _u(12) -#define PSM_DONE_SRAM2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PSM_DONE_SRAM1 -#define PSM_DONE_SRAM1_RESET _u(0x0) -#define PSM_DONE_SRAM1_BITS _u(0x00000800) -#define PSM_DONE_SRAM1_MSB _u(11) -#define PSM_DONE_SRAM1_LSB _u(11) -#define PSM_DONE_SRAM1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PSM_DONE_SRAM0 -#define PSM_DONE_SRAM0_RESET _u(0x0) -#define PSM_DONE_SRAM0_BITS _u(0x00000400) -#define PSM_DONE_SRAM0_MSB _u(10) -#define PSM_DONE_SRAM0_LSB _u(10) -#define PSM_DONE_SRAM0_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PSM_DONE_BOOTRAM -#define PSM_DONE_BOOTRAM_RESET _u(0x0) -#define PSM_DONE_BOOTRAM_BITS _u(0x00000200) -#define PSM_DONE_BOOTRAM_MSB _u(9) -#define PSM_DONE_BOOTRAM_LSB _u(9) -#define PSM_DONE_BOOTRAM_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PSM_DONE_ROM -#define PSM_DONE_ROM_RESET _u(0x0) -#define PSM_DONE_ROM_BITS _u(0x00000100) -#define PSM_DONE_ROM_MSB _u(8) -#define PSM_DONE_ROM_LSB _u(8) -#define PSM_DONE_ROM_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PSM_DONE_BUSFABRIC -#define PSM_DONE_BUSFABRIC_RESET _u(0x0) -#define PSM_DONE_BUSFABRIC_BITS _u(0x00000080) -#define PSM_DONE_BUSFABRIC_MSB _u(7) -#define PSM_DONE_BUSFABRIC_LSB _u(7) -#define PSM_DONE_BUSFABRIC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PSM_DONE_PSM_READY -#define PSM_DONE_PSM_READY_RESET _u(0x0) -#define PSM_DONE_PSM_READY_BITS _u(0x00000040) -#define PSM_DONE_PSM_READY_MSB _u(6) -#define PSM_DONE_PSM_READY_LSB _u(6) -#define PSM_DONE_PSM_READY_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PSM_DONE_CLOCKS -#define PSM_DONE_CLOCKS_RESET _u(0x0) -#define PSM_DONE_CLOCKS_BITS _u(0x00000020) -#define PSM_DONE_CLOCKS_MSB _u(5) -#define PSM_DONE_CLOCKS_LSB _u(5) -#define PSM_DONE_CLOCKS_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PSM_DONE_RESETS -#define PSM_DONE_RESETS_RESET _u(0x0) -#define PSM_DONE_RESETS_BITS _u(0x00000010) -#define PSM_DONE_RESETS_MSB _u(4) -#define PSM_DONE_RESETS_LSB _u(4) -#define PSM_DONE_RESETS_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PSM_DONE_XOSC -#define PSM_DONE_XOSC_RESET _u(0x0) -#define PSM_DONE_XOSC_BITS _u(0x00000008) -#define PSM_DONE_XOSC_MSB _u(3) -#define PSM_DONE_XOSC_LSB _u(3) -#define PSM_DONE_XOSC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PSM_DONE_ROSC -#define PSM_DONE_ROSC_RESET _u(0x0) -#define PSM_DONE_ROSC_BITS _u(0x00000004) -#define PSM_DONE_ROSC_MSB _u(2) -#define PSM_DONE_ROSC_LSB _u(2) -#define PSM_DONE_ROSC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PSM_DONE_OTP -#define PSM_DONE_OTP_RESET _u(0x0) -#define PSM_DONE_OTP_BITS _u(0x00000002) -#define PSM_DONE_OTP_MSB _u(1) -#define PSM_DONE_OTP_LSB _u(1) -#define PSM_DONE_OTP_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PSM_DONE_PROC_COLD -#define PSM_DONE_PROC_COLD_RESET _u(0x0) -#define PSM_DONE_PROC_COLD_BITS _u(0x00000001) -#define PSM_DONE_PROC_COLD_MSB _u(0) -#define PSM_DONE_PROC_COLD_LSB _u(0) -#define PSM_DONE_PROC_COLD_ACCESS "RO" -// ============================================================================= -#endif // _HARDWARE_REGS_PSM_H - diff --git a/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/pwm.h b/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/pwm.h deleted file mode 100644 index 629ee8a655..0000000000 --- a/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/pwm.h +++ /dev/null @@ -1,2374 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -// ============================================================================= -// Register block : PWM -// Version : 1 -// Bus type : apb -// Description : Simple PWM -// ============================================================================= -#ifndef _HARDWARE_REGS_PWM_H -#define _HARDWARE_REGS_PWM_H -// ============================================================================= -// Register : PWM_CH0_CSR -// Description : Control and status register -#define PWM_CH0_CSR_OFFSET _u(0x00000000) -#define PWM_CH0_CSR_BITS _u(0x000000ff) -#define PWM_CH0_CSR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : PWM_CH0_CSR_PH_ADV -// Description : Advance the phase of the counter by 1 count, while it is -// running. -// Self-clearing. Write a 1, and poll until low. Counter must be -// running -// at less than full speed (div_int + div_frac / 16 > 1) -#define PWM_CH0_CSR_PH_ADV_RESET _u(0x0) -#define PWM_CH0_CSR_PH_ADV_BITS _u(0x00000080) -#define PWM_CH0_CSR_PH_ADV_MSB _u(7) -#define PWM_CH0_CSR_PH_ADV_LSB _u(7) -#define PWM_CH0_CSR_PH_ADV_ACCESS "SC" -// ----------------------------------------------------------------------------- -// Field : PWM_CH0_CSR_PH_RET -// Description : Retard the phase of the counter by 1 count, while it is -// running. -// Self-clearing. Write a 1, and poll until low. Counter must be -// running. -#define PWM_CH0_CSR_PH_RET_RESET _u(0x0) -#define PWM_CH0_CSR_PH_RET_BITS _u(0x00000040) -#define PWM_CH0_CSR_PH_RET_MSB _u(6) -#define PWM_CH0_CSR_PH_RET_LSB _u(6) -#define PWM_CH0_CSR_PH_RET_ACCESS "SC" -// ----------------------------------------------------------------------------- -// Field : PWM_CH0_CSR_DIVMODE -// 0x0 -> Free-running counting at rate dictated by fractional divider -// 0x1 -> Fractional divider operation is gated by the PWM B pin. -// 0x2 -> Counter advances with each rising edge of the PWM B pin. -// 0x3 -> Counter advances with each falling edge of the PWM B pin. -#define PWM_CH0_CSR_DIVMODE_RESET _u(0x0) -#define PWM_CH0_CSR_DIVMODE_BITS _u(0x00000030) -#define PWM_CH0_CSR_DIVMODE_MSB _u(5) -#define PWM_CH0_CSR_DIVMODE_LSB _u(4) -#define PWM_CH0_CSR_DIVMODE_ACCESS "RW" -#define PWM_CH0_CSR_DIVMODE_VALUE_DIV _u(0x0) -#define PWM_CH0_CSR_DIVMODE_VALUE_LEVEL _u(0x1) -#define PWM_CH0_CSR_DIVMODE_VALUE_RISE _u(0x2) -#define PWM_CH0_CSR_DIVMODE_VALUE_FALL _u(0x3) -// ----------------------------------------------------------------------------- -// Field : PWM_CH0_CSR_B_INV -// Description : Invert output B -#define PWM_CH0_CSR_B_INV_RESET _u(0x0) -#define PWM_CH0_CSR_B_INV_BITS _u(0x00000008) -#define PWM_CH0_CSR_B_INV_MSB _u(3) -#define PWM_CH0_CSR_B_INV_LSB _u(3) -#define PWM_CH0_CSR_B_INV_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_CH0_CSR_A_INV -// Description : Invert output A -#define PWM_CH0_CSR_A_INV_RESET _u(0x0) -#define PWM_CH0_CSR_A_INV_BITS _u(0x00000004) -#define PWM_CH0_CSR_A_INV_MSB _u(2) -#define PWM_CH0_CSR_A_INV_LSB _u(2) -#define PWM_CH0_CSR_A_INV_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_CH0_CSR_PH_CORRECT -// Description : 1: Enable phase-correct modulation. 0: Trailing-edge -#define PWM_CH0_CSR_PH_CORRECT_RESET _u(0x0) -#define PWM_CH0_CSR_PH_CORRECT_BITS _u(0x00000002) -#define PWM_CH0_CSR_PH_CORRECT_MSB _u(1) -#define PWM_CH0_CSR_PH_CORRECT_LSB _u(1) -#define PWM_CH0_CSR_PH_CORRECT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_CH0_CSR_EN -// Description : Enable the PWM channel. -#define PWM_CH0_CSR_EN_RESET _u(0x0) -#define PWM_CH0_CSR_EN_BITS _u(0x00000001) -#define PWM_CH0_CSR_EN_MSB _u(0) -#define PWM_CH0_CSR_EN_LSB _u(0) -#define PWM_CH0_CSR_EN_ACCESS "RW" -// ============================================================================= -// Register : PWM_CH0_DIV -// Description : INT and FRAC form a fixed-point fractional number. -// Counting rate is system clock frequency divided by this number. -// Fractional division uses simple 1st-order sigma-delta. -#define PWM_CH0_DIV_OFFSET _u(0x00000004) -#define PWM_CH0_DIV_BITS _u(0x00000fff) -#define PWM_CH0_DIV_RESET _u(0x00000010) -// ----------------------------------------------------------------------------- -// Field : PWM_CH0_DIV_INT -#define PWM_CH0_DIV_INT_RESET _u(0x01) -#define PWM_CH0_DIV_INT_BITS _u(0x00000ff0) -#define PWM_CH0_DIV_INT_MSB _u(11) -#define PWM_CH0_DIV_INT_LSB _u(4) -#define PWM_CH0_DIV_INT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_CH0_DIV_FRAC -#define PWM_CH0_DIV_FRAC_RESET _u(0x0) -#define PWM_CH0_DIV_FRAC_BITS _u(0x0000000f) -#define PWM_CH0_DIV_FRAC_MSB _u(3) -#define PWM_CH0_DIV_FRAC_LSB _u(0) -#define PWM_CH0_DIV_FRAC_ACCESS "RW" -// ============================================================================= -// Register : PWM_CH0_CTR -// Description : Direct access to the PWM counter -#define PWM_CH0_CTR_OFFSET _u(0x00000008) -#define PWM_CH0_CTR_BITS _u(0x0000ffff) -#define PWM_CH0_CTR_RESET _u(0x00000000) -#define PWM_CH0_CTR_MSB _u(15) -#define PWM_CH0_CTR_LSB _u(0) -#define PWM_CH0_CTR_ACCESS "RW" -// ============================================================================= -// Register : PWM_CH0_CC -// Description : Counter compare values -#define PWM_CH0_CC_OFFSET _u(0x0000000c) -#define PWM_CH0_CC_BITS _u(0xffffffff) -#define PWM_CH0_CC_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : PWM_CH0_CC_B -#define PWM_CH0_CC_B_RESET _u(0x0000) -#define PWM_CH0_CC_B_BITS _u(0xffff0000) -#define PWM_CH0_CC_B_MSB _u(31) -#define PWM_CH0_CC_B_LSB _u(16) -#define PWM_CH0_CC_B_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_CH0_CC_A -#define PWM_CH0_CC_A_RESET _u(0x0000) -#define PWM_CH0_CC_A_BITS _u(0x0000ffff) -#define PWM_CH0_CC_A_MSB _u(15) -#define PWM_CH0_CC_A_LSB _u(0) -#define PWM_CH0_CC_A_ACCESS "RW" -// ============================================================================= -// Register : PWM_CH0_TOP -// Description : Counter wrap value -#define PWM_CH0_TOP_OFFSET _u(0x00000010) -#define PWM_CH0_TOP_BITS _u(0x0000ffff) -#define PWM_CH0_TOP_RESET _u(0x0000ffff) -#define PWM_CH0_TOP_MSB _u(15) -#define PWM_CH0_TOP_LSB _u(0) -#define PWM_CH0_TOP_ACCESS "RW" -// ============================================================================= -// Register : PWM_CH1_CSR -// Description : Control and status register -#define PWM_CH1_CSR_OFFSET _u(0x00000014) -#define PWM_CH1_CSR_BITS _u(0x000000ff) -#define PWM_CH1_CSR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : PWM_CH1_CSR_PH_ADV -// Description : Advance the phase of the counter by 1 count, while it is -// running. -// Self-clearing. Write a 1, and poll until low. Counter must be -// running -// at less than full speed (div_int + div_frac / 16 > 1) -#define PWM_CH1_CSR_PH_ADV_RESET _u(0x0) -#define PWM_CH1_CSR_PH_ADV_BITS _u(0x00000080) -#define PWM_CH1_CSR_PH_ADV_MSB _u(7) -#define PWM_CH1_CSR_PH_ADV_LSB _u(7) -#define PWM_CH1_CSR_PH_ADV_ACCESS "SC" -// ----------------------------------------------------------------------------- -// Field : PWM_CH1_CSR_PH_RET -// Description : Retard the phase of the counter by 1 count, while it is -// running. -// Self-clearing. Write a 1, and poll until low. Counter must be -// running. -#define PWM_CH1_CSR_PH_RET_RESET _u(0x0) -#define PWM_CH1_CSR_PH_RET_BITS _u(0x00000040) -#define PWM_CH1_CSR_PH_RET_MSB _u(6) -#define PWM_CH1_CSR_PH_RET_LSB _u(6) -#define PWM_CH1_CSR_PH_RET_ACCESS "SC" -// ----------------------------------------------------------------------------- -// Field : PWM_CH1_CSR_DIVMODE -// 0x0 -> Free-running counting at rate dictated by fractional divider -// 0x1 -> Fractional divider operation is gated by the PWM B pin. -// 0x2 -> Counter advances with each rising edge of the PWM B pin. -// 0x3 -> Counter advances with each falling edge of the PWM B pin. -#define PWM_CH1_CSR_DIVMODE_RESET _u(0x0) -#define PWM_CH1_CSR_DIVMODE_BITS _u(0x00000030) -#define PWM_CH1_CSR_DIVMODE_MSB _u(5) -#define PWM_CH1_CSR_DIVMODE_LSB _u(4) -#define PWM_CH1_CSR_DIVMODE_ACCESS "RW" -#define PWM_CH1_CSR_DIVMODE_VALUE_DIV _u(0x0) -#define PWM_CH1_CSR_DIVMODE_VALUE_LEVEL _u(0x1) -#define PWM_CH1_CSR_DIVMODE_VALUE_RISE _u(0x2) -#define PWM_CH1_CSR_DIVMODE_VALUE_FALL _u(0x3) -// ----------------------------------------------------------------------------- -// Field : PWM_CH1_CSR_B_INV -// Description : Invert output B -#define PWM_CH1_CSR_B_INV_RESET _u(0x0) -#define PWM_CH1_CSR_B_INV_BITS _u(0x00000008) -#define PWM_CH1_CSR_B_INV_MSB _u(3) -#define PWM_CH1_CSR_B_INV_LSB _u(3) -#define PWM_CH1_CSR_B_INV_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_CH1_CSR_A_INV -// Description : Invert output A -#define PWM_CH1_CSR_A_INV_RESET _u(0x0) -#define PWM_CH1_CSR_A_INV_BITS _u(0x00000004) -#define PWM_CH1_CSR_A_INV_MSB _u(2) -#define PWM_CH1_CSR_A_INV_LSB _u(2) -#define PWM_CH1_CSR_A_INV_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_CH1_CSR_PH_CORRECT -// Description : 1: Enable phase-correct modulation. 0: Trailing-edge -#define PWM_CH1_CSR_PH_CORRECT_RESET _u(0x0) -#define PWM_CH1_CSR_PH_CORRECT_BITS _u(0x00000002) -#define PWM_CH1_CSR_PH_CORRECT_MSB _u(1) -#define PWM_CH1_CSR_PH_CORRECT_LSB _u(1) -#define PWM_CH1_CSR_PH_CORRECT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_CH1_CSR_EN -// Description : Enable the PWM channel. -#define PWM_CH1_CSR_EN_RESET _u(0x0) -#define PWM_CH1_CSR_EN_BITS _u(0x00000001) -#define PWM_CH1_CSR_EN_MSB _u(0) -#define PWM_CH1_CSR_EN_LSB _u(0) -#define PWM_CH1_CSR_EN_ACCESS "RW" -// ============================================================================= -// Register : PWM_CH1_DIV -// Description : INT and FRAC form a fixed-point fractional number. -// Counting rate is system clock frequency divided by this number. -// Fractional division uses simple 1st-order sigma-delta. -#define PWM_CH1_DIV_OFFSET _u(0x00000018) -#define PWM_CH1_DIV_BITS _u(0x00000fff) -#define PWM_CH1_DIV_RESET _u(0x00000010) -// ----------------------------------------------------------------------------- -// Field : PWM_CH1_DIV_INT -#define PWM_CH1_DIV_INT_RESET _u(0x01) -#define PWM_CH1_DIV_INT_BITS _u(0x00000ff0) -#define PWM_CH1_DIV_INT_MSB _u(11) -#define PWM_CH1_DIV_INT_LSB _u(4) -#define PWM_CH1_DIV_INT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_CH1_DIV_FRAC -#define PWM_CH1_DIV_FRAC_RESET _u(0x0) -#define PWM_CH1_DIV_FRAC_BITS _u(0x0000000f) -#define PWM_CH1_DIV_FRAC_MSB _u(3) -#define PWM_CH1_DIV_FRAC_LSB _u(0) -#define PWM_CH1_DIV_FRAC_ACCESS "RW" -// ============================================================================= -// Register : PWM_CH1_CTR -// Description : Direct access to the PWM counter -#define PWM_CH1_CTR_OFFSET _u(0x0000001c) -#define PWM_CH1_CTR_BITS _u(0x0000ffff) -#define PWM_CH1_CTR_RESET _u(0x00000000) -#define PWM_CH1_CTR_MSB _u(15) -#define PWM_CH1_CTR_LSB _u(0) -#define PWM_CH1_CTR_ACCESS "RW" -// ============================================================================= -// Register : PWM_CH1_CC -// Description : Counter compare values -#define PWM_CH1_CC_OFFSET _u(0x00000020) -#define PWM_CH1_CC_BITS _u(0xffffffff) -#define PWM_CH1_CC_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : PWM_CH1_CC_B -#define PWM_CH1_CC_B_RESET _u(0x0000) -#define PWM_CH1_CC_B_BITS _u(0xffff0000) -#define PWM_CH1_CC_B_MSB _u(31) -#define PWM_CH1_CC_B_LSB _u(16) -#define PWM_CH1_CC_B_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_CH1_CC_A -#define PWM_CH1_CC_A_RESET _u(0x0000) -#define PWM_CH1_CC_A_BITS _u(0x0000ffff) -#define PWM_CH1_CC_A_MSB _u(15) -#define PWM_CH1_CC_A_LSB _u(0) -#define PWM_CH1_CC_A_ACCESS "RW" -// ============================================================================= -// Register : PWM_CH1_TOP -// Description : Counter wrap value -#define PWM_CH1_TOP_OFFSET _u(0x00000024) -#define PWM_CH1_TOP_BITS _u(0x0000ffff) -#define PWM_CH1_TOP_RESET _u(0x0000ffff) -#define PWM_CH1_TOP_MSB _u(15) -#define PWM_CH1_TOP_LSB _u(0) -#define PWM_CH1_TOP_ACCESS "RW" -// ============================================================================= -// Register : PWM_CH2_CSR -// Description : Control and status register -#define PWM_CH2_CSR_OFFSET _u(0x00000028) -#define PWM_CH2_CSR_BITS _u(0x000000ff) -#define PWM_CH2_CSR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : PWM_CH2_CSR_PH_ADV -// Description : Advance the phase of the counter by 1 count, while it is -// running. -// Self-clearing. Write a 1, and poll until low. Counter must be -// running -// at less than full speed (div_int + div_frac / 16 > 1) -#define PWM_CH2_CSR_PH_ADV_RESET _u(0x0) -#define PWM_CH2_CSR_PH_ADV_BITS _u(0x00000080) -#define PWM_CH2_CSR_PH_ADV_MSB _u(7) -#define PWM_CH2_CSR_PH_ADV_LSB _u(7) -#define PWM_CH2_CSR_PH_ADV_ACCESS "SC" -// ----------------------------------------------------------------------------- -// Field : PWM_CH2_CSR_PH_RET -// Description : Retard the phase of the counter by 1 count, while it is -// running. -// Self-clearing. Write a 1, and poll until low. Counter must be -// running. -#define PWM_CH2_CSR_PH_RET_RESET _u(0x0) -#define PWM_CH2_CSR_PH_RET_BITS _u(0x00000040) -#define PWM_CH2_CSR_PH_RET_MSB _u(6) -#define PWM_CH2_CSR_PH_RET_LSB _u(6) -#define PWM_CH2_CSR_PH_RET_ACCESS "SC" -// ----------------------------------------------------------------------------- -// Field : PWM_CH2_CSR_DIVMODE -// 0x0 -> Free-running counting at rate dictated by fractional divider -// 0x1 -> Fractional divider operation is gated by the PWM B pin. -// 0x2 -> Counter advances with each rising edge of the PWM B pin. -// 0x3 -> Counter advances with each falling edge of the PWM B pin. -#define PWM_CH2_CSR_DIVMODE_RESET _u(0x0) -#define PWM_CH2_CSR_DIVMODE_BITS _u(0x00000030) -#define PWM_CH2_CSR_DIVMODE_MSB _u(5) -#define PWM_CH2_CSR_DIVMODE_LSB _u(4) -#define PWM_CH2_CSR_DIVMODE_ACCESS "RW" -#define PWM_CH2_CSR_DIVMODE_VALUE_DIV _u(0x0) -#define PWM_CH2_CSR_DIVMODE_VALUE_LEVEL _u(0x1) -#define PWM_CH2_CSR_DIVMODE_VALUE_RISE _u(0x2) -#define PWM_CH2_CSR_DIVMODE_VALUE_FALL _u(0x3) -// ----------------------------------------------------------------------------- -// Field : PWM_CH2_CSR_B_INV -// Description : Invert output B -#define PWM_CH2_CSR_B_INV_RESET _u(0x0) -#define PWM_CH2_CSR_B_INV_BITS _u(0x00000008) -#define PWM_CH2_CSR_B_INV_MSB _u(3) -#define PWM_CH2_CSR_B_INV_LSB _u(3) -#define PWM_CH2_CSR_B_INV_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_CH2_CSR_A_INV -// Description : Invert output A -#define PWM_CH2_CSR_A_INV_RESET _u(0x0) -#define PWM_CH2_CSR_A_INV_BITS _u(0x00000004) -#define PWM_CH2_CSR_A_INV_MSB _u(2) -#define PWM_CH2_CSR_A_INV_LSB _u(2) -#define PWM_CH2_CSR_A_INV_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_CH2_CSR_PH_CORRECT -// Description : 1: Enable phase-correct modulation. 0: Trailing-edge -#define PWM_CH2_CSR_PH_CORRECT_RESET _u(0x0) -#define PWM_CH2_CSR_PH_CORRECT_BITS _u(0x00000002) -#define PWM_CH2_CSR_PH_CORRECT_MSB _u(1) -#define PWM_CH2_CSR_PH_CORRECT_LSB _u(1) -#define PWM_CH2_CSR_PH_CORRECT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_CH2_CSR_EN -// Description : Enable the PWM channel. -#define PWM_CH2_CSR_EN_RESET _u(0x0) -#define PWM_CH2_CSR_EN_BITS _u(0x00000001) -#define PWM_CH2_CSR_EN_MSB _u(0) -#define PWM_CH2_CSR_EN_LSB _u(0) -#define PWM_CH2_CSR_EN_ACCESS "RW" -// ============================================================================= -// Register : PWM_CH2_DIV -// Description : INT and FRAC form a fixed-point fractional number. -// Counting rate is system clock frequency divided by this number. -// Fractional division uses simple 1st-order sigma-delta. -#define PWM_CH2_DIV_OFFSET _u(0x0000002c) -#define PWM_CH2_DIV_BITS _u(0x00000fff) -#define PWM_CH2_DIV_RESET _u(0x00000010) -// ----------------------------------------------------------------------------- -// Field : PWM_CH2_DIV_INT -#define PWM_CH2_DIV_INT_RESET _u(0x01) -#define PWM_CH2_DIV_INT_BITS _u(0x00000ff0) -#define PWM_CH2_DIV_INT_MSB _u(11) -#define PWM_CH2_DIV_INT_LSB _u(4) -#define PWM_CH2_DIV_INT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_CH2_DIV_FRAC -#define PWM_CH2_DIV_FRAC_RESET _u(0x0) -#define PWM_CH2_DIV_FRAC_BITS _u(0x0000000f) -#define PWM_CH2_DIV_FRAC_MSB _u(3) -#define PWM_CH2_DIV_FRAC_LSB _u(0) -#define PWM_CH2_DIV_FRAC_ACCESS "RW" -// ============================================================================= -// Register : PWM_CH2_CTR -// Description : Direct access to the PWM counter -#define PWM_CH2_CTR_OFFSET _u(0x00000030) -#define PWM_CH2_CTR_BITS _u(0x0000ffff) -#define PWM_CH2_CTR_RESET _u(0x00000000) -#define PWM_CH2_CTR_MSB _u(15) -#define PWM_CH2_CTR_LSB _u(0) -#define PWM_CH2_CTR_ACCESS "RW" -// ============================================================================= -// Register : PWM_CH2_CC -// Description : Counter compare values -#define PWM_CH2_CC_OFFSET _u(0x00000034) -#define PWM_CH2_CC_BITS _u(0xffffffff) -#define PWM_CH2_CC_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : PWM_CH2_CC_B -#define PWM_CH2_CC_B_RESET _u(0x0000) -#define PWM_CH2_CC_B_BITS _u(0xffff0000) -#define PWM_CH2_CC_B_MSB _u(31) -#define PWM_CH2_CC_B_LSB _u(16) -#define PWM_CH2_CC_B_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_CH2_CC_A -#define PWM_CH2_CC_A_RESET _u(0x0000) -#define PWM_CH2_CC_A_BITS _u(0x0000ffff) -#define PWM_CH2_CC_A_MSB _u(15) -#define PWM_CH2_CC_A_LSB _u(0) -#define PWM_CH2_CC_A_ACCESS "RW" -// ============================================================================= -// Register : PWM_CH2_TOP -// Description : Counter wrap value -#define PWM_CH2_TOP_OFFSET _u(0x00000038) -#define PWM_CH2_TOP_BITS _u(0x0000ffff) -#define PWM_CH2_TOP_RESET _u(0x0000ffff) -#define PWM_CH2_TOP_MSB _u(15) -#define PWM_CH2_TOP_LSB _u(0) -#define PWM_CH2_TOP_ACCESS "RW" -// ============================================================================= -// Register : PWM_CH3_CSR -// Description : Control and status register -#define PWM_CH3_CSR_OFFSET _u(0x0000003c) -#define PWM_CH3_CSR_BITS _u(0x000000ff) -#define PWM_CH3_CSR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : PWM_CH3_CSR_PH_ADV -// Description : Advance the phase of the counter by 1 count, while it is -// running. -// Self-clearing. Write a 1, and poll until low. Counter must be -// running -// at less than full speed (div_int + div_frac / 16 > 1) -#define PWM_CH3_CSR_PH_ADV_RESET _u(0x0) -#define PWM_CH3_CSR_PH_ADV_BITS _u(0x00000080) -#define PWM_CH3_CSR_PH_ADV_MSB _u(7) -#define PWM_CH3_CSR_PH_ADV_LSB _u(7) -#define PWM_CH3_CSR_PH_ADV_ACCESS "SC" -// ----------------------------------------------------------------------------- -// Field : PWM_CH3_CSR_PH_RET -// Description : Retard the phase of the counter by 1 count, while it is -// running. -// Self-clearing. Write a 1, and poll until low. Counter must be -// running. -#define PWM_CH3_CSR_PH_RET_RESET _u(0x0) -#define PWM_CH3_CSR_PH_RET_BITS _u(0x00000040) -#define PWM_CH3_CSR_PH_RET_MSB _u(6) -#define PWM_CH3_CSR_PH_RET_LSB _u(6) -#define PWM_CH3_CSR_PH_RET_ACCESS "SC" -// ----------------------------------------------------------------------------- -// Field : PWM_CH3_CSR_DIVMODE -// 0x0 -> Free-running counting at rate dictated by fractional divider -// 0x1 -> Fractional divider operation is gated by the PWM B pin. -// 0x2 -> Counter advances with each rising edge of the PWM B pin. -// 0x3 -> Counter advances with each falling edge of the PWM B pin. -#define PWM_CH3_CSR_DIVMODE_RESET _u(0x0) -#define PWM_CH3_CSR_DIVMODE_BITS _u(0x00000030) -#define PWM_CH3_CSR_DIVMODE_MSB _u(5) -#define PWM_CH3_CSR_DIVMODE_LSB _u(4) -#define PWM_CH3_CSR_DIVMODE_ACCESS "RW" -#define PWM_CH3_CSR_DIVMODE_VALUE_DIV _u(0x0) -#define PWM_CH3_CSR_DIVMODE_VALUE_LEVEL _u(0x1) -#define PWM_CH3_CSR_DIVMODE_VALUE_RISE _u(0x2) -#define PWM_CH3_CSR_DIVMODE_VALUE_FALL _u(0x3) -// ----------------------------------------------------------------------------- -// Field : PWM_CH3_CSR_B_INV -// Description : Invert output B -#define PWM_CH3_CSR_B_INV_RESET _u(0x0) -#define PWM_CH3_CSR_B_INV_BITS _u(0x00000008) -#define PWM_CH3_CSR_B_INV_MSB _u(3) -#define PWM_CH3_CSR_B_INV_LSB _u(3) -#define PWM_CH3_CSR_B_INV_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_CH3_CSR_A_INV -// Description : Invert output A -#define PWM_CH3_CSR_A_INV_RESET _u(0x0) -#define PWM_CH3_CSR_A_INV_BITS _u(0x00000004) -#define PWM_CH3_CSR_A_INV_MSB _u(2) -#define PWM_CH3_CSR_A_INV_LSB _u(2) -#define PWM_CH3_CSR_A_INV_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_CH3_CSR_PH_CORRECT -// Description : 1: Enable phase-correct modulation. 0: Trailing-edge -#define PWM_CH3_CSR_PH_CORRECT_RESET _u(0x0) -#define PWM_CH3_CSR_PH_CORRECT_BITS _u(0x00000002) -#define PWM_CH3_CSR_PH_CORRECT_MSB _u(1) -#define PWM_CH3_CSR_PH_CORRECT_LSB _u(1) -#define PWM_CH3_CSR_PH_CORRECT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_CH3_CSR_EN -// Description : Enable the PWM channel. -#define PWM_CH3_CSR_EN_RESET _u(0x0) -#define PWM_CH3_CSR_EN_BITS _u(0x00000001) -#define PWM_CH3_CSR_EN_MSB _u(0) -#define PWM_CH3_CSR_EN_LSB _u(0) -#define PWM_CH3_CSR_EN_ACCESS "RW" -// ============================================================================= -// Register : PWM_CH3_DIV -// Description : INT and FRAC form a fixed-point fractional number. -// Counting rate is system clock frequency divided by this number. -// Fractional division uses simple 1st-order sigma-delta. -#define PWM_CH3_DIV_OFFSET _u(0x00000040) -#define PWM_CH3_DIV_BITS _u(0x00000fff) -#define PWM_CH3_DIV_RESET _u(0x00000010) -// ----------------------------------------------------------------------------- -// Field : PWM_CH3_DIV_INT -#define PWM_CH3_DIV_INT_RESET _u(0x01) -#define PWM_CH3_DIV_INT_BITS _u(0x00000ff0) -#define PWM_CH3_DIV_INT_MSB _u(11) -#define PWM_CH3_DIV_INT_LSB _u(4) -#define PWM_CH3_DIV_INT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_CH3_DIV_FRAC -#define PWM_CH3_DIV_FRAC_RESET _u(0x0) -#define PWM_CH3_DIV_FRAC_BITS _u(0x0000000f) -#define PWM_CH3_DIV_FRAC_MSB _u(3) -#define PWM_CH3_DIV_FRAC_LSB _u(0) -#define PWM_CH3_DIV_FRAC_ACCESS "RW" -// ============================================================================= -// Register : PWM_CH3_CTR -// Description : Direct access to the PWM counter -#define PWM_CH3_CTR_OFFSET _u(0x00000044) -#define PWM_CH3_CTR_BITS _u(0x0000ffff) -#define PWM_CH3_CTR_RESET _u(0x00000000) -#define PWM_CH3_CTR_MSB _u(15) -#define PWM_CH3_CTR_LSB _u(0) -#define PWM_CH3_CTR_ACCESS "RW" -// ============================================================================= -// Register : PWM_CH3_CC -// Description : Counter compare values -#define PWM_CH3_CC_OFFSET _u(0x00000048) -#define PWM_CH3_CC_BITS _u(0xffffffff) -#define PWM_CH3_CC_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : PWM_CH3_CC_B -#define PWM_CH3_CC_B_RESET _u(0x0000) -#define PWM_CH3_CC_B_BITS _u(0xffff0000) -#define PWM_CH3_CC_B_MSB _u(31) -#define PWM_CH3_CC_B_LSB _u(16) -#define PWM_CH3_CC_B_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_CH3_CC_A -#define PWM_CH3_CC_A_RESET _u(0x0000) -#define PWM_CH3_CC_A_BITS _u(0x0000ffff) -#define PWM_CH3_CC_A_MSB _u(15) -#define PWM_CH3_CC_A_LSB _u(0) -#define PWM_CH3_CC_A_ACCESS "RW" -// ============================================================================= -// Register : PWM_CH3_TOP -// Description : Counter wrap value -#define PWM_CH3_TOP_OFFSET _u(0x0000004c) -#define PWM_CH3_TOP_BITS _u(0x0000ffff) -#define PWM_CH3_TOP_RESET _u(0x0000ffff) -#define PWM_CH3_TOP_MSB _u(15) -#define PWM_CH3_TOP_LSB _u(0) -#define PWM_CH3_TOP_ACCESS "RW" -// ============================================================================= -// Register : PWM_CH4_CSR -// Description : Control and status register -#define PWM_CH4_CSR_OFFSET _u(0x00000050) -#define PWM_CH4_CSR_BITS _u(0x000000ff) -#define PWM_CH4_CSR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : PWM_CH4_CSR_PH_ADV -// Description : Advance the phase of the counter by 1 count, while it is -// running. -// Self-clearing. Write a 1, and poll until low. Counter must be -// running -// at less than full speed (div_int + div_frac / 16 > 1) -#define PWM_CH4_CSR_PH_ADV_RESET _u(0x0) -#define PWM_CH4_CSR_PH_ADV_BITS _u(0x00000080) -#define PWM_CH4_CSR_PH_ADV_MSB _u(7) -#define PWM_CH4_CSR_PH_ADV_LSB _u(7) -#define PWM_CH4_CSR_PH_ADV_ACCESS "SC" -// ----------------------------------------------------------------------------- -// Field : PWM_CH4_CSR_PH_RET -// Description : Retard the phase of the counter by 1 count, while it is -// running. -// Self-clearing. Write a 1, and poll until low. Counter must be -// running. -#define PWM_CH4_CSR_PH_RET_RESET _u(0x0) -#define PWM_CH4_CSR_PH_RET_BITS _u(0x00000040) -#define PWM_CH4_CSR_PH_RET_MSB _u(6) -#define PWM_CH4_CSR_PH_RET_LSB _u(6) -#define PWM_CH4_CSR_PH_RET_ACCESS "SC" -// ----------------------------------------------------------------------------- -// Field : PWM_CH4_CSR_DIVMODE -// 0x0 -> Free-running counting at rate dictated by fractional divider -// 0x1 -> Fractional divider operation is gated by the PWM B pin. -// 0x2 -> Counter advances with each rising edge of the PWM B pin. -// 0x3 -> Counter advances with each falling edge of the PWM B pin. -#define PWM_CH4_CSR_DIVMODE_RESET _u(0x0) -#define PWM_CH4_CSR_DIVMODE_BITS _u(0x00000030) -#define PWM_CH4_CSR_DIVMODE_MSB _u(5) -#define PWM_CH4_CSR_DIVMODE_LSB _u(4) -#define PWM_CH4_CSR_DIVMODE_ACCESS "RW" -#define PWM_CH4_CSR_DIVMODE_VALUE_DIV _u(0x0) -#define PWM_CH4_CSR_DIVMODE_VALUE_LEVEL _u(0x1) -#define PWM_CH4_CSR_DIVMODE_VALUE_RISE _u(0x2) -#define PWM_CH4_CSR_DIVMODE_VALUE_FALL _u(0x3) -// ----------------------------------------------------------------------------- -// Field : PWM_CH4_CSR_B_INV -// Description : Invert output B -#define PWM_CH4_CSR_B_INV_RESET _u(0x0) -#define PWM_CH4_CSR_B_INV_BITS _u(0x00000008) -#define PWM_CH4_CSR_B_INV_MSB _u(3) -#define PWM_CH4_CSR_B_INV_LSB _u(3) -#define PWM_CH4_CSR_B_INV_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_CH4_CSR_A_INV -// Description : Invert output A -#define PWM_CH4_CSR_A_INV_RESET _u(0x0) -#define PWM_CH4_CSR_A_INV_BITS _u(0x00000004) -#define PWM_CH4_CSR_A_INV_MSB _u(2) -#define PWM_CH4_CSR_A_INV_LSB _u(2) -#define PWM_CH4_CSR_A_INV_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_CH4_CSR_PH_CORRECT -// Description : 1: Enable phase-correct modulation. 0: Trailing-edge -#define PWM_CH4_CSR_PH_CORRECT_RESET _u(0x0) -#define PWM_CH4_CSR_PH_CORRECT_BITS _u(0x00000002) -#define PWM_CH4_CSR_PH_CORRECT_MSB _u(1) -#define PWM_CH4_CSR_PH_CORRECT_LSB _u(1) -#define PWM_CH4_CSR_PH_CORRECT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_CH4_CSR_EN -// Description : Enable the PWM channel. -#define PWM_CH4_CSR_EN_RESET _u(0x0) -#define PWM_CH4_CSR_EN_BITS _u(0x00000001) -#define PWM_CH4_CSR_EN_MSB _u(0) -#define PWM_CH4_CSR_EN_LSB _u(0) -#define PWM_CH4_CSR_EN_ACCESS "RW" -// ============================================================================= -// Register : PWM_CH4_DIV -// Description : INT and FRAC form a fixed-point fractional number. -// Counting rate is system clock frequency divided by this number. -// Fractional division uses simple 1st-order sigma-delta. -#define PWM_CH4_DIV_OFFSET _u(0x00000054) -#define PWM_CH4_DIV_BITS _u(0x00000fff) -#define PWM_CH4_DIV_RESET _u(0x00000010) -// ----------------------------------------------------------------------------- -// Field : PWM_CH4_DIV_INT -#define PWM_CH4_DIV_INT_RESET _u(0x01) -#define PWM_CH4_DIV_INT_BITS _u(0x00000ff0) -#define PWM_CH4_DIV_INT_MSB _u(11) -#define PWM_CH4_DIV_INT_LSB _u(4) -#define PWM_CH4_DIV_INT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_CH4_DIV_FRAC -#define PWM_CH4_DIV_FRAC_RESET _u(0x0) -#define PWM_CH4_DIV_FRAC_BITS _u(0x0000000f) -#define PWM_CH4_DIV_FRAC_MSB _u(3) -#define PWM_CH4_DIV_FRAC_LSB _u(0) -#define PWM_CH4_DIV_FRAC_ACCESS "RW" -// ============================================================================= -// Register : PWM_CH4_CTR -// Description : Direct access to the PWM counter -#define PWM_CH4_CTR_OFFSET _u(0x00000058) -#define PWM_CH4_CTR_BITS _u(0x0000ffff) -#define PWM_CH4_CTR_RESET _u(0x00000000) -#define PWM_CH4_CTR_MSB _u(15) -#define PWM_CH4_CTR_LSB _u(0) -#define PWM_CH4_CTR_ACCESS "RW" -// ============================================================================= -// Register : PWM_CH4_CC -// Description : Counter compare values -#define PWM_CH4_CC_OFFSET _u(0x0000005c) -#define PWM_CH4_CC_BITS _u(0xffffffff) -#define PWM_CH4_CC_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : PWM_CH4_CC_B -#define PWM_CH4_CC_B_RESET _u(0x0000) -#define PWM_CH4_CC_B_BITS _u(0xffff0000) -#define PWM_CH4_CC_B_MSB _u(31) -#define PWM_CH4_CC_B_LSB _u(16) -#define PWM_CH4_CC_B_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_CH4_CC_A -#define PWM_CH4_CC_A_RESET _u(0x0000) -#define PWM_CH4_CC_A_BITS _u(0x0000ffff) -#define PWM_CH4_CC_A_MSB _u(15) -#define PWM_CH4_CC_A_LSB _u(0) -#define PWM_CH4_CC_A_ACCESS "RW" -// ============================================================================= -// Register : PWM_CH4_TOP -// Description : Counter wrap value -#define PWM_CH4_TOP_OFFSET _u(0x00000060) -#define PWM_CH4_TOP_BITS _u(0x0000ffff) -#define PWM_CH4_TOP_RESET _u(0x0000ffff) -#define PWM_CH4_TOP_MSB _u(15) -#define PWM_CH4_TOP_LSB _u(0) -#define PWM_CH4_TOP_ACCESS "RW" -// ============================================================================= -// Register : PWM_CH5_CSR -// Description : Control and status register -#define PWM_CH5_CSR_OFFSET _u(0x00000064) -#define PWM_CH5_CSR_BITS _u(0x000000ff) -#define PWM_CH5_CSR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : PWM_CH5_CSR_PH_ADV -// Description : Advance the phase of the counter by 1 count, while it is -// running. -// Self-clearing. Write a 1, and poll until low. Counter must be -// running -// at less than full speed (div_int + div_frac / 16 > 1) -#define PWM_CH5_CSR_PH_ADV_RESET _u(0x0) -#define PWM_CH5_CSR_PH_ADV_BITS _u(0x00000080) -#define PWM_CH5_CSR_PH_ADV_MSB _u(7) -#define PWM_CH5_CSR_PH_ADV_LSB _u(7) -#define PWM_CH5_CSR_PH_ADV_ACCESS "SC" -// ----------------------------------------------------------------------------- -// Field : PWM_CH5_CSR_PH_RET -// Description : Retard the phase of the counter by 1 count, while it is -// running. -// Self-clearing. Write a 1, and poll until low. Counter must be -// running. -#define PWM_CH5_CSR_PH_RET_RESET _u(0x0) -#define PWM_CH5_CSR_PH_RET_BITS _u(0x00000040) -#define PWM_CH5_CSR_PH_RET_MSB _u(6) -#define PWM_CH5_CSR_PH_RET_LSB _u(6) -#define PWM_CH5_CSR_PH_RET_ACCESS "SC" -// ----------------------------------------------------------------------------- -// Field : PWM_CH5_CSR_DIVMODE -// 0x0 -> Free-running counting at rate dictated by fractional divider -// 0x1 -> Fractional divider operation is gated by the PWM B pin. -// 0x2 -> Counter advances with each rising edge of the PWM B pin. -// 0x3 -> Counter advances with each falling edge of the PWM B pin. -#define PWM_CH5_CSR_DIVMODE_RESET _u(0x0) -#define PWM_CH5_CSR_DIVMODE_BITS _u(0x00000030) -#define PWM_CH5_CSR_DIVMODE_MSB _u(5) -#define PWM_CH5_CSR_DIVMODE_LSB _u(4) -#define PWM_CH5_CSR_DIVMODE_ACCESS "RW" -#define PWM_CH5_CSR_DIVMODE_VALUE_DIV _u(0x0) -#define PWM_CH5_CSR_DIVMODE_VALUE_LEVEL _u(0x1) -#define PWM_CH5_CSR_DIVMODE_VALUE_RISE _u(0x2) -#define PWM_CH5_CSR_DIVMODE_VALUE_FALL _u(0x3) -// ----------------------------------------------------------------------------- -// Field : PWM_CH5_CSR_B_INV -// Description : Invert output B -#define PWM_CH5_CSR_B_INV_RESET _u(0x0) -#define PWM_CH5_CSR_B_INV_BITS _u(0x00000008) -#define PWM_CH5_CSR_B_INV_MSB _u(3) -#define PWM_CH5_CSR_B_INV_LSB _u(3) -#define PWM_CH5_CSR_B_INV_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_CH5_CSR_A_INV -// Description : Invert output A -#define PWM_CH5_CSR_A_INV_RESET _u(0x0) -#define PWM_CH5_CSR_A_INV_BITS _u(0x00000004) -#define PWM_CH5_CSR_A_INV_MSB _u(2) -#define PWM_CH5_CSR_A_INV_LSB _u(2) -#define PWM_CH5_CSR_A_INV_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_CH5_CSR_PH_CORRECT -// Description : 1: Enable phase-correct modulation. 0: Trailing-edge -#define PWM_CH5_CSR_PH_CORRECT_RESET _u(0x0) -#define PWM_CH5_CSR_PH_CORRECT_BITS _u(0x00000002) -#define PWM_CH5_CSR_PH_CORRECT_MSB _u(1) -#define PWM_CH5_CSR_PH_CORRECT_LSB _u(1) -#define PWM_CH5_CSR_PH_CORRECT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_CH5_CSR_EN -// Description : Enable the PWM channel. -#define PWM_CH5_CSR_EN_RESET _u(0x0) -#define PWM_CH5_CSR_EN_BITS _u(0x00000001) -#define PWM_CH5_CSR_EN_MSB _u(0) -#define PWM_CH5_CSR_EN_LSB _u(0) -#define PWM_CH5_CSR_EN_ACCESS "RW" -// ============================================================================= -// Register : PWM_CH5_DIV -// Description : INT and FRAC form a fixed-point fractional number. -// Counting rate is system clock frequency divided by this number. -// Fractional division uses simple 1st-order sigma-delta. -#define PWM_CH5_DIV_OFFSET _u(0x00000068) -#define PWM_CH5_DIV_BITS _u(0x00000fff) -#define PWM_CH5_DIV_RESET _u(0x00000010) -// ----------------------------------------------------------------------------- -// Field : PWM_CH5_DIV_INT -#define PWM_CH5_DIV_INT_RESET _u(0x01) -#define PWM_CH5_DIV_INT_BITS _u(0x00000ff0) -#define PWM_CH5_DIV_INT_MSB _u(11) -#define PWM_CH5_DIV_INT_LSB _u(4) -#define PWM_CH5_DIV_INT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_CH5_DIV_FRAC -#define PWM_CH5_DIV_FRAC_RESET _u(0x0) -#define PWM_CH5_DIV_FRAC_BITS _u(0x0000000f) -#define PWM_CH5_DIV_FRAC_MSB _u(3) -#define PWM_CH5_DIV_FRAC_LSB _u(0) -#define PWM_CH5_DIV_FRAC_ACCESS "RW" -// ============================================================================= -// Register : PWM_CH5_CTR -// Description : Direct access to the PWM counter -#define PWM_CH5_CTR_OFFSET _u(0x0000006c) -#define PWM_CH5_CTR_BITS _u(0x0000ffff) -#define PWM_CH5_CTR_RESET _u(0x00000000) -#define PWM_CH5_CTR_MSB _u(15) -#define PWM_CH5_CTR_LSB _u(0) -#define PWM_CH5_CTR_ACCESS "RW" -// ============================================================================= -// Register : PWM_CH5_CC -// Description : Counter compare values -#define PWM_CH5_CC_OFFSET _u(0x00000070) -#define PWM_CH5_CC_BITS _u(0xffffffff) -#define PWM_CH5_CC_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : PWM_CH5_CC_B -#define PWM_CH5_CC_B_RESET _u(0x0000) -#define PWM_CH5_CC_B_BITS _u(0xffff0000) -#define PWM_CH5_CC_B_MSB _u(31) -#define PWM_CH5_CC_B_LSB _u(16) -#define PWM_CH5_CC_B_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_CH5_CC_A -#define PWM_CH5_CC_A_RESET _u(0x0000) -#define PWM_CH5_CC_A_BITS _u(0x0000ffff) -#define PWM_CH5_CC_A_MSB _u(15) -#define PWM_CH5_CC_A_LSB _u(0) -#define PWM_CH5_CC_A_ACCESS "RW" -// ============================================================================= -// Register : PWM_CH5_TOP -// Description : Counter wrap value -#define PWM_CH5_TOP_OFFSET _u(0x00000074) -#define PWM_CH5_TOP_BITS _u(0x0000ffff) -#define PWM_CH5_TOP_RESET _u(0x0000ffff) -#define PWM_CH5_TOP_MSB _u(15) -#define PWM_CH5_TOP_LSB _u(0) -#define PWM_CH5_TOP_ACCESS "RW" -// ============================================================================= -// Register : PWM_CH6_CSR -// Description : Control and status register -#define PWM_CH6_CSR_OFFSET _u(0x00000078) -#define PWM_CH6_CSR_BITS _u(0x000000ff) -#define PWM_CH6_CSR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : PWM_CH6_CSR_PH_ADV -// Description : Advance the phase of the counter by 1 count, while it is -// running. -// Self-clearing. Write a 1, and poll until low. Counter must be -// running -// at less than full speed (div_int + div_frac / 16 > 1) -#define PWM_CH6_CSR_PH_ADV_RESET _u(0x0) -#define PWM_CH6_CSR_PH_ADV_BITS _u(0x00000080) -#define PWM_CH6_CSR_PH_ADV_MSB _u(7) -#define PWM_CH6_CSR_PH_ADV_LSB _u(7) -#define PWM_CH6_CSR_PH_ADV_ACCESS "SC" -// ----------------------------------------------------------------------------- -// Field : PWM_CH6_CSR_PH_RET -// Description : Retard the phase of the counter by 1 count, while it is -// running. -// Self-clearing. Write a 1, and poll until low. Counter must be -// running. -#define PWM_CH6_CSR_PH_RET_RESET _u(0x0) -#define PWM_CH6_CSR_PH_RET_BITS _u(0x00000040) -#define PWM_CH6_CSR_PH_RET_MSB _u(6) -#define PWM_CH6_CSR_PH_RET_LSB _u(6) -#define PWM_CH6_CSR_PH_RET_ACCESS "SC" -// ----------------------------------------------------------------------------- -// Field : PWM_CH6_CSR_DIVMODE -// 0x0 -> Free-running counting at rate dictated by fractional divider -// 0x1 -> Fractional divider operation is gated by the PWM B pin. -// 0x2 -> Counter advances with each rising edge of the PWM B pin. -// 0x3 -> Counter advances with each falling edge of the PWM B pin. -#define PWM_CH6_CSR_DIVMODE_RESET _u(0x0) -#define PWM_CH6_CSR_DIVMODE_BITS _u(0x00000030) -#define PWM_CH6_CSR_DIVMODE_MSB _u(5) -#define PWM_CH6_CSR_DIVMODE_LSB _u(4) -#define PWM_CH6_CSR_DIVMODE_ACCESS "RW" -#define PWM_CH6_CSR_DIVMODE_VALUE_DIV _u(0x0) -#define PWM_CH6_CSR_DIVMODE_VALUE_LEVEL _u(0x1) -#define PWM_CH6_CSR_DIVMODE_VALUE_RISE _u(0x2) -#define PWM_CH6_CSR_DIVMODE_VALUE_FALL _u(0x3) -// ----------------------------------------------------------------------------- -// Field : PWM_CH6_CSR_B_INV -// Description : Invert output B -#define PWM_CH6_CSR_B_INV_RESET _u(0x0) -#define PWM_CH6_CSR_B_INV_BITS _u(0x00000008) -#define PWM_CH6_CSR_B_INV_MSB _u(3) -#define PWM_CH6_CSR_B_INV_LSB _u(3) -#define PWM_CH6_CSR_B_INV_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_CH6_CSR_A_INV -// Description : Invert output A -#define PWM_CH6_CSR_A_INV_RESET _u(0x0) -#define PWM_CH6_CSR_A_INV_BITS _u(0x00000004) -#define PWM_CH6_CSR_A_INV_MSB _u(2) -#define PWM_CH6_CSR_A_INV_LSB _u(2) -#define PWM_CH6_CSR_A_INV_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_CH6_CSR_PH_CORRECT -// Description : 1: Enable phase-correct modulation. 0: Trailing-edge -#define PWM_CH6_CSR_PH_CORRECT_RESET _u(0x0) -#define PWM_CH6_CSR_PH_CORRECT_BITS _u(0x00000002) -#define PWM_CH6_CSR_PH_CORRECT_MSB _u(1) -#define PWM_CH6_CSR_PH_CORRECT_LSB _u(1) -#define PWM_CH6_CSR_PH_CORRECT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_CH6_CSR_EN -// Description : Enable the PWM channel. -#define PWM_CH6_CSR_EN_RESET _u(0x0) -#define PWM_CH6_CSR_EN_BITS _u(0x00000001) -#define PWM_CH6_CSR_EN_MSB _u(0) -#define PWM_CH6_CSR_EN_LSB _u(0) -#define PWM_CH6_CSR_EN_ACCESS "RW" -// ============================================================================= -// Register : PWM_CH6_DIV -// Description : INT and FRAC form a fixed-point fractional number. -// Counting rate is system clock frequency divided by this number. -// Fractional division uses simple 1st-order sigma-delta. -#define PWM_CH6_DIV_OFFSET _u(0x0000007c) -#define PWM_CH6_DIV_BITS _u(0x00000fff) -#define PWM_CH6_DIV_RESET _u(0x00000010) -// ----------------------------------------------------------------------------- -// Field : PWM_CH6_DIV_INT -#define PWM_CH6_DIV_INT_RESET _u(0x01) -#define PWM_CH6_DIV_INT_BITS _u(0x00000ff0) -#define PWM_CH6_DIV_INT_MSB _u(11) -#define PWM_CH6_DIV_INT_LSB _u(4) -#define PWM_CH6_DIV_INT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_CH6_DIV_FRAC -#define PWM_CH6_DIV_FRAC_RESET _u(0x0) -#define PWM_CH6_DIV_FRAC_BITS _u(0x0000000f) -#define PWM_CH6_DIV_FRAC_MSB _u(3) -#define PWM_CH6_DIV_FRAC_LSB _u(0) -#define PWM_CH6_DIV_FRAC_ACCESS "RW" -// ============================================================================= -// Register : PWM_CH6_CTR -// Description : Direct access to the PWM counter -#define PWM_CH6_CTR_OFFSET _u(0x00000080) -#define PWM_CH6_CTR_BITS _u(0x0000ffff) -#define PWM_CH6_CTR_RESET _u(0x00000000) -#define PWM_CH6_CTR_MSB _u(15) -#define PWM_CH6_CTR_LSB _u(0) -#define PWM_CH6_CTR_ACCESS "RW" -// ============================================================================= -// Register : PWM_CH6_CC -// Description : Counter compare values -#define PWM_CH6_CC_OFFSET _u(0x00000084) -#define PWM_CH6_CC_BITS _u(0xffffffff) -#define PWM_CH6_CC_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : PWM_CH6_CC_B -#define PWM_CH6_CC_B_RESET _u(0x0000) -#define PWM_CH6_CC_B_BITS _u(0xffff0000) -#define PWM_CH6_CC_B_MSB _u(31) -#define PWM_CH6_CC_B_LSB _u(16) -#define PWM_CH6_CC_B_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_CH6_CC_A -#define PWM_CH6_CC_A_RESET _u(0x0000) -#define PWM_CH6_CC_A_BITS _u(0x0000ffff) -#define PWM_CH6_CC_A_MSB _u(15) -#define PWM_CH6_CC_A_LSB _u(0) -#define PWM_CH6_CC_A_ACCESS "RW" -// ============================================================================= -// Register : PWM_CH6_TOP -// Description : Counter wrap value -#define PWM_CH6_TOP_OFFSET _u(0x00000088) -#define PWM_CH6_TOP_BITS _u(0x0000ffff) -#define PWM_CH6_TOP_RESET _u(0x0000ffff) -#define PWM_CH6_TOP_MSB _u(15) -#define PWM_CH6_TOP_LSB _u(0) -#define PWM_CH6_TOP_ACCESS "RW" -// ============================================================================= -// Register : PWM_CH7_CSR -// Description : Control and status register -#define PWM_CH7_CSR_OFFSET _u(0x0000008c) -#define PWM_CH7_CSR_BITS _u(0x000000ff) -#define PWM_CH7_CSR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : PWM_CH7_CSR_PH_ADV -// Description : Advance the phase of the counter by 1 count, while it is -// running. -// Self-clearing. Write a 1, and poll until low. Counter must be -// running -// at less than full speed (div_int + div_frac / 16 > 1) -#define PWM_CH7_CSR_PH_ADV_RESET _u(0x0) -#define PWM_CH7_CSR_PH_ADV_BITS _u(0x00000080) -#define PWM_CH7_CSR_PH_ADV_MSB _u(7) -#define PWM_CH7_CSR_PH_ADV_LSB _u(7) -#define PWM_CH7_CSR_PH_ADV_ACCESS "SC" -// ----------------------------------------------------------------------------- -// Field : PWM_CH7_CSR_PH_RET -// Description : Retard the phase of the counter by 1 count, while it is -// running. -// Self-clearing. Write a 1, and poll until low. Counter must be -// running. -#define PWM_CH7_CSR_PH_RET_RESET _u(0x0) -#define PWM_CH7_CSR_PH_RET_BITS _u(0x00000040) -#define PWM_CH7_CSR_PH_RET_MSB _u(6) -#define PWM_CH7_CSR_PH_RET_LSB _u(6) -#define PWM_CH7_CSR_PH_RET_ACCESS "SC" -// ----------------------------------------------------------------------------- -// Field : PWM_CH7_CSR_DIVMODE -// 0x0 -> Free-running counting at rate dictated by fractional divider -// 0x1 -> Fractional divider operation is gated by the PWM B pin. -// 0x2 -> Counter advances with each rising edge of the PWM B pin. -// 0x3 -> Counter advances with each falling edge of the PWM B pin. -#define PWM_CH7_CSR_DIVMODE_RESET _u(0x0) -#define PWM_CH7_CSR_DIVMODE_BITS _u(0x00000030) -#define PWM_CH7_CSR_DIVMODE_MSB _u(5) -#define PWM_CH7_CSR_DIVMODE_LSB _u(4) -#define PWM_CH7_CSR_DIVMODE_ACCESS "RW" -#define PWM_CH7_CSR_DIVMODE_VALUE_DIV _u(0x0) -#define PWM_CH7_CSR_DIVMODE_VALUE_LEVEL _u(0x1) -#define PWM_CH7_CSR_DIVMODE_VALUE_RISE _u(0x2) -#define PWM_CH7_CSR_DIVMODE_VALUE_FALL _u(0x3) -// ----------------------------------------------------------------------------- -// Field : PWM_CH7_CSR_B_INV -// Description : Invert output B -#define PWM_CH7_CSR_B_INV_RESET _u(0x0) -#define PWM_CH7_CSR_B_INV_BITS _u(0x00000008) -#define PWM_CH7_CSR_B_INV_MSB _u(3) -#define PWM_CH7_CSR_B_INV_LSB _u(3) -#define PWM_CH7_CSR_B_INV_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_CH7_CSR_A_INV -// Description : Invert output A -#define PWM_CH7_CSR_A_INV_RESET _u(0x0) -#define PWM_CH7_CSR_A_INV_BITS _u(0x00000004) -#define PWM_CH7_CSR_A_INV_MSB _u(2) -#define PWM_CH7_CSR_A_INV_LSB _u(2) -#define PWM_CH7_CSR_A_INV_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_CH7_CSR_PH_CORRECT -// Description : 1: Enable phase-correct modulation. 0: Trailing-edge -#define PWM_CH7_CSR_PH_CORRECT_RESET _u(0x0) -#define PWM_CH7_CSR_PH_CORRECT_BITS _u(0x00000002) -#define PWM_CH7_CSR_PH_CORRECT_MSB _u(1) -#define PWM_CH7_CSR_PH_CORRECT_LSB _u(1) -#define PWM_CH7_CSR_PH_CORRECT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_CH7_CSR_EN -// Description : Enable the PWM channel. -#define PWM_CH7_CSR_EN_RESET _u(0x0) -#define PWM_CH7_CSR_EN_BITS _u(0x00000001) -#define PWM_CH7_CSR_EN_MSB _u(0) -#define PWM_CH7_CSR_EN_LSB _u(0) -#define PWM_CH7_CSR_EN_ACCESS "RW" -// ============================================================================= -// Register : PWM_CH7_DIV -// Description : INT and FRAC form a fixed-point fractional number. -// Counting rate is system clock frequency divided by this number. -// Fractional division uses simple 1st-order sigma-delta. -#define PWM_CH7_DIV_OFFSET _u(0x00000090) -#define PWM_CH7_DIV_BITS _u(0x00000fff) -#define PWM_CH7_DIV_RESET _u(0x00000010) -// ----------------------------------------------------------------------------- -// Field : PWM_CH7_DIV_INT -#define PWM_CH7_DIV_INT_RESET _u(0x01) -#define PWM_CH7_DIV_INT_BITS _u(0x00000ff0) -#define PWM_CH7_DIV_INT_MSB _u(11) -#define PWM_CH7_DIV_INT_LSB _u(4) -#define PWM_CH7_DIV_INT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_CH7_DIV_FRAC -#define PWM_CH7_DIV_FRAC_RESET _u(0x0) -#define PWM_CH7_DIV_FRAC_BITS _u(0x0000000f) -#define PWM_CH7_DIV_FRAC_MSB _u(3) -#define PWM_CH7_DIV_FRAC_LSB _u(0) -#define PWM_CH7_DIV_FRAC_ACCESS "RW" -// ============================================================================= -// Register : PWM_CH7_CTR -// Description : Direct access to the PWM counter -#define PWM_CH7_CTR_OFFSET _u(0x00000094) -#define PWM_CH7_CTR_BITS _u(0x0000ffff) -#define PWM_CH7_CTR_RESET _u(0x00000000) -#define PWM_CH7_CTR_MSB _u(15) -#define PWM_CH7_CTR_LSB _u(0) -#define PWM_CH7_CTR_ACCESS "RW" -// ============================================================================= -// Register : PWM_CH7_CC -// Description : Counter compare values -#define PWM_CH7_CC_OFFSET _u(0x00000098) -#define PWM_CH7_CC_BITS _u(0xffffffff) -#define PWM_CH7_CC_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : PWM_CH7_CC_B -#define PWM_CH7_CC_B_RESET _u(0x0000) -#define PWM_CH7_CC_B_BITS _u(0xffff0000) -#define PWM_CH7_CC_B_MSB _u(31) -#define PWM_CH7_CC_B_LSB _u(16) -#define PWM_CH7_CC_B_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_CH7_CC_A -#define PWM_CH7_CC_A_RESET _u(0x0000) -#define PWM_CH7_CC_A_BITS _u(0x0000ffff) -#define PWM_CH7_CC_A_MSB _u(15) -#define PWM_CH7_CC_A_LSB _u(0) -#define PWM_CH7_CC_A_ACCESS "RW" -// ============================================================================= -// Register : PWM_CH7_TOP -// Description : Counter wrap value -#define PWM_CH7_TOP_OFFSET _u(0x0000009c) -#define PWM_CH7_TOP_BITS _u(0x0000ffff) -#define PWM_CH7_TOP_RESET _u(0x0000ffff) -#define PWM_CH7_TOP_MSB _u(15) -#define PWM_CH7_TOP_LSB _u(0) -#define PWM_CH7_TOP_ACCESS "RW" -// ============================================================================= -// Register : PWM_CH8_CSR -// Description : Control and status register -#define PWM_CH8_CSR_OFFSET _u(0x000000a0) -#define PWM_CH8_CSR_BITS _u(0x000000ff) -#define PWM_CH8_CSR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : PWM_CH8_CSR_PH_ADV -// Description : Advance the phase of the counter by 1 count, while it is -// running. -// Self-clearing. Write a 1, and poll until low. Counter must be -// running -// at less than full speed (div_int + div_frac / 16 > 1) -#define PWM_CH8_CSR_PH_ADV_RESET _u(0x0) -#define PWM_CH8_CSR_PH_ADV_BITS _u(0x00000080) -#define PWM_CH8_CSR_PH_ADV_MSB _u(7) -#define PWM_CH8_CSR_PH_ADV_LSB _u(7) -#define PWM_CH8_CSR_PH_ADV_ACCESS "SC" -// ----------------------------------------------------------------------------- -// Field : PWM_CH8_CSR_PH_RET -// Description : Retard the phase of the counter by 1 count, while it is -// running. -// Self-clearing. Write a 1, and poll until low. Counter must be -// running. -#define PWM_CH8_CSR_PH_RET_RESET _u(0x0) -#define PWM_CH8_CSR_PH_RET_BITS _u(0x00000040) -#define PWM_CH8_CSR_PH_RET_MSB _u(6) -#define PWM_CH8_CSR_PH_RET_LSB _u(6) -#define PWM_CH8_CSR_PH_RET_ACCESS "SC" -// ----------------------------------------------------------------------------- -// Field : PWM_CH8_CSR_DIVMODE -// 0x0 -> Free-running counting at rate dictated by fractional divider -// 0x1 -> Fractional divider operation is gated by the PWM B pin. -// 0x2 -> Counter advances with each rising edge of the PWM B pin. -// 0x3 -> Counter advances with each falling edge of the PWM B pin. -#define PWM_CH8_CSR_DIVMODE_RESET _u(0x0) -#define PWM_CH8_CSR_DIVMODE_BITS _u(0x00000030) -#define PWM_CH8_CSR_DIVMODE_MSB _u(5) -#define PWM_CH8_CSR_DIVMODE_LSB _u(4) -#define PWM_CH8_CSR_DIVMODE_ACCESS "RW" -#define PWM_CH8_CSR_DIVMODE_VALUE_DIV _u(0x0) -#define PWM_CH8_CSR_DIVMODE_VALUE_LEVEL _u(0x1) -#define PWM_CH8_CSR_DIVMODE_VALUE_RISE _u(0x2) -#define PWM_CH8_CSR_DIVMODE_VALUE_FALL _u(0x3) -// ----------------------------------------------------------------------------- -// Field : PWM_CH8_CSR_B_INV -// Description : Invert output B -#define PWM_CH8_CSR_B_INV_RESET _u(0x0) -#define PWM_CH8_CSR_B_INV_BITS _u(0x00000008) -#define PWM_CH8_CSR_B_INV_MSB _u(3) -#define PWM_CH8_CSR_B_INV_LSB _u(3) -#define PWM_CH8_CSR_B_INV_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_CH8_CSR_A_INV -// Description : Invert output A -#define PWM_CH8_CSR_A_INV_RESET _u(0x0) -#define PWM_CH8_CSR_A_INV_BITS _u(0x00000004) -#define PWM_CH8_CSR_A_INV_MSB _u(2) -#define PWM_CH8_CSR_A_INV_LSB _u(2) -#define PWM_CH8_CSR_A_INV_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_CH8_CSR_PH_CORRECT -// Description : 1: Enable phase-correct modulation. 0: Trailing-edge -#define PWM_CH8_CSR_PH_CORRECT_RESET _u(0x0) -#define PWM_CH8_CSR_PH_CORRECT_BITS _u(0x00000002) -#define PWM_CH8_CSR_PH_CORRECT_MSB _u(1) -#define PWM_CH8_CSR_PH_CORRECT_LSB _u(1) -#define PWM_CH8_CSR_PH_CORRECT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_CH8_CSR_EN -// Description : Enable the PWM channel. -#define PWM_CH8_CSR_EN_RESET _u(0x0) -#define PWM_CH8_CSR_EN_BITS _u(0x00000001) -#define PWM_CH8_CSR_EN_MSB _u(0) -#define PWM_CH8_CSR_EN_LSB _u(0) -#define PWM_CH8_CSR_EN_ACCESS "RW" -// ============================================================================= -// Register : PWM_CH8_DIV -// Description : INT and FRAC form a fixed-point fractional number. -// Counting rate is system clock frequency divided by this number. -// Fractional division uses simple 1st-order sigma-delta. -#define PWM_CH8_DIV_OFFSET _u(0x000000a4) -#define PWM_CH8_DIV_BITS _u(0x00000fff) -#define PWM_CH8_DIV_RESET _u(0x00000010) -// ----------------------------------------------------------------------------- -// Field : PWM_CH8_DIV_INT -#define PWM_CH8_DIV_INT_RESET _u(0x01) -#define PWM_CH8_DIV_INT_BITS _u(0x00000ff0) -#define PWM_CH8_DIV_INT_MSB _u(11) -#define PWM_CH8_DIV_INT_LSB _u(4) -#define PWM_CH8_DIV_INT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_CH8_DIV_FRAC -#define PWM_CH8_DIV_FRAC_RESET _u(0x0) -#define PWM_CH8_DIV_FRAC_BITS _u(0x0000000f) -#define PWM_CH8_DIV_FRAC_MSB _u(3) -#define PWM_CH8_DIV_FRAC_LSB _u(0) -#define PWM_CH8_DIV_FRAC_ACCESS "RW" -// ============================================================================= -// Register : PWM_CH8_CTR -// Description : Direct access to the PWM counter -#define PWM_CH8_CTR_OFFSET _u(0x000000a8) -#define PWM_CH8_CTR_BITS _u(0x0000ffff) -#define PWM_CH8_CTR_RESET _u(0x00000000) -#define PWM_CH8_CTR_MSB _u(15) -#define PWM_CH8_CTR_LSB _u(0) -#define PWM_CH8_CTR_ACCESS "RW" -// ============================================================================= -// Register : PWM_CH8_CC -// Description : Counter compare values -#define PWM_CH8_CC_OFFSET _u(0x000000ac) -#define PWM_CH8_CC_BITS _u(0xffffffff) -#define PWM_CH8_CC_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : PWM_CH8_CC_B -#define PWM_CH8_CC_B_RESET _u(0x0000) -#define PWM_CH8_CC_B_BITS _u(0xffff0000) -#define PWM_CH8_CC_B_MSB _u(31) -#define PWM_CH8_CC_B_LSB _u(16) -#define PWM_CH8_CC_B_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_CH8_CC_A -#define PWM_CH8_CC_A_RESET _u(0x0000) -#define PWM_CH8_CC_A_BITS _u(0x0000ffff) -#define PWM_CH8_CC_A_MSB _u(15) -#define PWM_CH8_CC_A_LSB _u(0) -#define PWM_CH8_CC_A_ACCESS "RW" -// ============================================================================= -// Register : PWM_CH8_TOP -// Description : Counter wrap value -#define PWM_CH8_TOP_OFFSET _u(0x000000b0) -#define PWM_CH8_TOP_BITS _u(0x0000ffff) -#define PWM_CH8_TOP_RESET _u(0x0000ffff) -#define PWM_CH8_TOP_MSB _u(15) -#define PWM_CH8_TOP_LSB _u(0) -#define PWM_CH8_TOP_ACCESS "RW" -// ============================================================================= -// Register : PWM_CH9_CSR -// Description : Control and status register -#define PWM_CH9_CSR_OFFSET _u(0x000000b4) -#define PWM_CH9_CSR_BITS _u(0x000000ff) -#define PWM_CH9_CSR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : PWM_CH9_CSR_PH_ADV -// Description : Advance the phase of the counter by 1 count, while it is -// running. -// Self-clearing. Write a 1, and poll until low. Counter must be -// running -// at less than full speed (div_int + div_frac / 16 > 1) -#define PWM_CH9_CSR_PH_ADV_RESET _u(0x0) -#define PWM_CH9_CSR_PH_ADV_BITS _u(0x00000080) -#define PWM_CH9_CSR_PH_ADV_MSB _u(7) -#define PWM_CH9_CSR_PH_ADV_LSB _u(7) -#define PWM_CH9_CSR_PH_ADV_ACCESS "SC" -// ----------------------------------------------------------------------------- -// Field : PWM_CH9_CSR_PH_RET -// Description : Retard the phase of the counter by 1 count, while it is -// running. -// Self-clearing. Write a 1, and poll until low. Counter must be -// running. -#define PWM_CH9_CSR_PH_RET_RESET _u(0x0) -#define PWM_CH9_CSR_PH_RET_BITS _u(0x00000040) -#define PWM_CH9_CSR_PH_RET_MSB _u(6) -#define PWM_CH9_CSR_PH_RET_LSB _u(6) -#define PWM_CH9_CSR_PH_RET_ACCESS "SC" -// ----------------------------------------------------------------------------- -// Field : PWM_CH9_CSR_DIVMODE -// 0x0 -> Free-running counting at rate dictated by fractional divider -// 0x1 -> Fractional divider operation is gated by the PWM B pin. -// 0x2 -> Counter advances with each rising edge of the PWM B pin. -// 0x3 -> Counter advances with each falling edge of the PWM B pin. -#define PWM_CH9_CSR_DIVMODE_RESET _u(0x0) -#define PWM_CH9_CSR_DIVMODE_BITS _u(0x00000030) -#define PWM_CH9_CSR_DIVMODE_MSB _u(5) -#define PWM_CH9_CSR_DIVMODE_LSB _u(4) -#define PWM_CH9_CSR_DIVMODE_ACCESS "RW" -#define PWM_CH9_CSR_DIVMODE_VALUE_DIV _u(0x0) -#define PWM_CH9_CSR_DIVMODE_VALUE_LEVEL _u(0x1) -#define PWM_CH9_CSR_DIVMODE_VALUE_RISE _u(0x2) -#define PWM_CH9_CSR_DIVMODE_VALUE_FALL _u(0x3) -// ----------------------------------------------------------------------------- -// Field : PWM_CH9_CSR_B_INV -// Description : Invert output B -#define PWM_CH9_CSR_B_INV_RESET _u(0x0) -#define PWM_CH9_CSR_B_INV_BITS _u(0x00000008) -#define PWM_CH9_CSR_B_INV_MSB _u(3) -#define PWM_CH9_CSR_B_INV_LSB _u(3) -#define PWM_CH9_CSR_B_INV_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_CH9_CSR_A_INV -// Description : Invert output A -#define PWM_CH9_CSR_A_INV_RESET _u(0x0) -#define PWM_CH9_CSR_A_INV_BITS _u(0x00000004) -#define PWM_CH9_CSR_A_INV_MSB _u(2) -#define PWM_CH9_CSR_A_INV_LSB _u(2) -#define PWM_CH9_CSR_A_INV_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_CH9_CSR_PH_CORRECT -// Description : 1: Enable phase-correct modulation. 0: Trailing-edge -#define PWM_CH9_CSR_PH_CORRECT_RESET _u(0x0) -#define PWM_CH9_CSR_PH_CORRECT_BITS _u(0x00000002) -#define PWM_CH9_CSR_PH_CORRECT_MSB _u(1) -#define PWM_CH9_CSR_PH_CORRECT_LSB _u(1) -#define PWM_CH9_CSR_PH_CORRECT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_CH9_CSR_EN -// Description : Enable the PWM channel. -#define PWM_CH9_CSR_EN_RESET _u(0x0) -#define PWM_CH9_CSR_EN_BITS _u(0x00000001) -#define PWM_CH9_CSR_EN_MSB _u(0) -#define PWM_CH9_CSR_EN_LSB _u(0) -#define PWM_CH9_CSR_EN_ACCESS "RW" -// ============================================================================= -// Register : PWM_CH9_DIV -// Description : INT and FRAC form a fixed-point fractional number. -// Counting rate is system clock frequency divided by this number. -// Fractional division uses simple 1st-order sigma-delta. -#define PWM_CH9_DIV_OFFSET _u(0x000000b8) -#define PWM_CH9_DIV_BITS _u(0x00000fff) -#define PWM_CH9_DIV_RESET _u(0x00000010) -// ----------------------------------------------------------------------------- -// Field : PWM_CH9_DIV_INT -#define PWM_CH9_DIV_INT_RESET _u(0x01) -#define PWM_CH9_DIV_INT_BITS _u(0x00000ff0) -#define PWM_CH9_DIV_INT_MSB _u(11) -#define PWM_CH9_DIV_INT_LSB _u(4) -#define PWM_CH9_DIV_INT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_CH9_DIV_FRAC -#define PWM_CH9_DIV_FRAC_RESET _u(0x0) -#define PWM_CH9_DIV_FRAC_BITS _u(0x0000000f) -#define PWM_CH9_DIV_FRAC_MSB _u(3) -#define PWM_CH9_DIV_FRAC_LSB _u(0) -#define PWM_CH9_DIV_FRAC_ACCESS "RW" -// ============================================================================= -// Register : PWM_CH9_CTR -// Description : Direct access to the PWM counter -#define PWM_CH9_CTR_OFFSET _u(0x000000bc) -#define PWM_CH9_CTR_BITS _u(0x0000ffff) -#define PWM_CH9_CTR_RESET _u(0x00000000) -#define PWM_CH9_CTR_MSB _u(15) -#define PWM_CH9_CTR_LSB _u(0) -#define PWM_CH9_CTR_ACCESS "RW" -// ============================================================================= -// Register : PWM_CH9_CC -// Description : Counter compare values -#define PWM_CH9_CC_OFFSET _u(0x000000c0) -#define PWM_CH9_CC_BITS _u(0xffffffff) -#define PWM_CH9_CC_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : PWM_CH9_CC_B -#define PWM_CH9_CC_B_RESET _u(0x0000) -#define PWM_CH9_CC_B_BITS _u(0xffff0000) -#define PWM_CH9_CC_B_MSB _u(31) -#define PWM_CH9_CC_B_LSB _u(16) -#define PWM_CH9_CC_B_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_CH9_CC_A -#define PWM_CH9_CC_A_RESET _u(0x0000) -#define PWM_CH9_CC_A_BITS _u(0x0000ffff) -#define PWM_CH9_CC_A_MSB _u(15) -#define PWM_CH9_CC_A_LSB _u(0) -#define PWM_CH9_CC_A_ACCESS "RW" -// ============================================================================= -// Register : PWM_CH9_TOP -// Description : Counter wrap value -#define PWM_CH9_TOP_OFFSET _u(0x000000c4) -#define PWM_CH9_TOP_BITS _u(0x0000ffff) -#define PWM_CH9_TOP_RESET _u(0x0000ffff) -#define PWM_CH9_TOP_MSB _u(15) -#define PWM_CH9_TOP_LSB _u(0) -#define PWM_CH9_TOP_ACCESS "RW" -// ============================================================================= -// Register : PWM_CH10_CSR -// Description : Control and status register -#define PWM_CH10_CSR_OFFSET _u(0x000000c8) -#define PWM_CH10_CSR_BITS _u(0x000000ff) -#define PWM_CH10_CSR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : PWM_CH10_CSR_PH_ADV -// Description : Advance the phase of the counter by 1 count, while it is -// running. -// Self-clearing. Write a 1, and poll until low. Counter must be -// running -// at less than full speed (div_int + div_frac / 16 > 1) -#define PWM_CH10_CSR_PH_ADV_RESET _u(0x0) -#define PWM_CH10_CSR_PH_ADV_BITS _u(0x00000080) -#define PWM_CH10_CSR_PH_ADV_MSB _u(7) -#define PWM_CH10_CSR_PH_ADV_LSB _u(7) -#define PWM_CH10_CSR_PH_ADV_ACCESS "SC" -// ----------------------------------------------------------------------------- -// Field : PWM_CH10_CSR_PH_RET -// Description : Retard the phase of the counter by 1 count, while it is -// running. -// Self-clearing. Write a 1, and poll until low. Counter must be -// running. -#define PWM_CH10_CSR_PH_RET_RESET _u(0x0) -#define PWM_CH10_CSR_PH_RET_BITS _u(0x00000040) -#define PWM_CH10_CSR_PH_RET_MSB _u(6) -#define PWM_CH10_CSR_PH_RET_LSB _u(6) -#define PWM_CH10_CSR_PH_RET_ACCESS "SC" -// ----------------------------------------------------------------------------- -// Field : PWM_CH10_CSR_DIVMODE -// 0x0 -> Free-running counting at rate dictated by fractional divider -// 0x1 -> Fractional divider operation is gated by the PWM B pin. -// 0x2 -> Counter advances with each rising edge of the PWM B pin. -// 0x3 -> Counter advances with each falling edge of the PWM B pin. -#define PWM_CH10_CSR_DIVMODE_RESET _u(0x0) -#define PWM_CH10_CSR_DIVMODE_BITS _u(0x00000030) -#define PWM_CH10_CSR_DIVMODE_MSB _u(5) -#define PWM_CH10_CSR_DIVMODE_LSB _u(4) -#define PWM_CH10_CSR_DIVMODE_ACCESS "RW" -#define PWM_CH10_CSR_DIVMODE_VALUE_DIV _u(0x0) -#define PWM_CH10_CSR_DIVMODE_VALUE_LEVEL _u(0x1) -#define PWM_CH10_CSR_DIVMODE_VALUE_RISE _u(0x2) -#define PWM_CH10_CSR_DIVMODE_VALUE_FALL _u(0x3) -// ----------------------------------------------------------------------------- -// Field : PWM_CH10_CSR_B_INV -// Description : Invert output B -#define PWM_CH10_CSR_B_INV_RESET _u(0x0) -#define PWM_CH10_CSR_B_INV_BITS _u(0x00000008) -#define PWM_CH10_CSR_B_INV_MSB _u(3) -#define PWM_CH10_CSR_B_INV_LSB _u(3) -#define PWM_CH10_CSR_B_INV_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_CH10_CSR_A_INV -// Description : Invert output A -#define PWM_CH10_CSR_A_INV_RESET _u(0x0) -#define PWM_CH10_CSR_A_INV_BITS _u(0x00000004) -#define PWM_CH10_CSR_A_INV_MSB _u(2) -#define PWM_CH10_CSR_A_INV_LSB _u(2) -#define PWM_CH10_CSR_A_INV_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_CH10_CSR_PH_CORRECT -// Description : 1: Enable phase-correct modulation. 0: Trailing-edge -#define PWM_CH10_CSR_PH_CORRECT_RESET _u(0x0) -#define PWM_CH10_CSR_PH_CORRECT_BITS _u(0x00000002) -#define PWM_CH10_CSR_PH_CORRECT_MSB _u(1) -#define PWM_CH10_CSR_PH_CORRECT_LSB _u(1) -#define PWM_CH10_CSR_PH_CORRECT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_CH10_CSR_EN -// Description : Enable the PWM channel. -#define PWM_CH10_CSR_EN_RESET _u(0x0) -#define PWM_CH10_CSR_EN_BITS _u(0x00000001) -#define PWM_CH10_CSR_EN_MSB _u(0) -#define PWM_CH10_CSR_EN_LSB _u(0) -#define PWM_CH10_CSR_EN_ACCESS "RW" -// ============================================================================= -// Register : PWM_CH10_DIV -// Description : INT and FRAC form a fixed-point fractional number. -// Counting rate is system clock frequency divided by this number. -// Fractional division uses simple 1st-order sigma-delta. -#define PWM_CH10_DIV_OFFSET _u(0x000000cc) -#define PWM_CH10_DIV_BITS _u(0x00000fff) -#define PWM_CH10_DIV_RESET _u(0x00000010) -// ----------------------------------------------------------------------------- -// Field : PWM_CH10_DIV_INT -#define PWM_CH10_DIV_INT_RESET _u(0x01) -#define PWM_CH10_DIV_INT_BITS _u(0x00000ff0) -#define PWM_CH10_DIV_INT_MSB _u(11) -#define PWM_CH10_DIV_INT_LSB _u(4) -#define PWM_CH10_DIV_INT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_CH10_DIV_FRAC -#define PWM_CH10_DIV_FRAC_RESET _u(0x0) -#define PWM_CH10_DIV_FRAC_BITS _u(0x0000000f) -#define PWM_CH10_DIV_FRAC_MSB _u(3) -#define PWM_CH10_DIV_FRAC_LSB _u(0) -#define PWM_CH10_DIV_FRAC_ACCESS "RW" -// ============================================================================= -// Register : PWM_CH10_CTR -// Description : Direct access to the PWM counter -#define PWM_CH10_CTR_OFFSET _u(0x000000d0) -#define PWM_CH10_CTR_BITS _u(0x0000ffff) -#define PWM_CH10_CTR_RESET _u(0x00000000) -#define PWM_CH10_CTR_MSB _u(15) -#define PWM_CH10_CTR_LSB _u(0) -#define PWM_CH10_CTR_ACCESS "RW" -// ============================================================================= -// Register : PWM_CH10_CC -// Description : Counter compare values -#define PWM_CH10_CC_OFFSET _u(0x000000d4) -#define PWM_CH10_CC_BITS _u(0xffffffff) -#define PWM_CH10_CC_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : PWM_CH10_CC_B -#define PWM_CH10_CC_B_RESET _u(0x0000) -#define PWM_CH10_CC_B_BITS _u(0xffff0000) -#define PWM_CH10_CC_B_MSB _u(31) -#define PWM_CH10_CC_B_LSB _u(16) -#define PWM_CH10_CC_B_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_CH10_CC_A -#define PWM_CH10_CC_A_RESET _u(0x0000) -#define PWM_CH10_CC_A_BITS _u(0x0000ffff) -#define PWM_CH10_CC_A_MSB _u(15) -#define PWM_CH10_CC_A_LSB _u(0) -#define PWM_CH10_CC_A_ACCESS "RW" -// ============================================================================= -// Register : PWM_CH10_TOP -// Description : Counter wrap value -#define PWM_CH10_TOP_OFFSET _u(0x000000d8) -#define PWM_CH10_TOP_BITS _u(0x0000ffff) -#define PWM_CH10_TOP_RESET _u(0x0000ffff) -#define PWM_CH10_TOP_MSB _u(15) -#define PWM_CH10_TOP_LSB _u(0) -#define PWM_CH10_TOP_ACCESS "RW" -// ============================================================================= -// Register : PWM_CH11_CSR -// Description : Control and status register -#define PWM_CH11_CSR_OFFSET _u(0x000000dc) -#define PWM_CH11_CSR_BITS _u(0x000000ff) -#define PWM_CH11_CSR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : PWM_CH11_CSR_PH_ADV -// Description : Advance the phase of the counter by 1 count, while it is -// running. -// Self-clearing. Write a 1, and poll until low. Counter must be -// running -// at less than full speed (div_int + div_frac / 16 > 1) -#define PWM_CH11_CSR_PH_ADV_RESET _u(0x0) -#define PWM_CH11_CSR_PH_ADV_BITS _u(0x00000080) -#define PWM_CH11_CSR_PH_ADV_MSB _u(7) -#define PWM_CH11_CSR_PH_ADV_LSB _u(7) -#define PWM_CH11_CSR_PH_ADV_ACCESS "SC" -// ----------------------------------------------------------------------------- -// Field : PWM_CH11_CSR_PH_RET -// Description : Retard the phase of the counter by 1 count, while it is -// running. -// Self-clearing. Write a 1, and poll until low. Counter must be -// running. -#define PWM_CH11_CSR_PH_RET_RESET _u(0x0) -#define PWM_CH11_CSR_PH_RET_BITS _u(0x00000040) -#define PWM_CH11_CSR_PH_RET_MSB _u(6) -#define PWM_CH11_CSR_PH_RET_LSB _u(6) -#define PWM_CH11_CSR_PH_RET_ACCESS "SC" -// ----------------------------------------------------------------------------- -// Field : PWM_CH11_CSR_DIVMODE -// 0x0 -> Free-running counting at rate dictated by fractional divider -// 0x1 -> Fractional divider operation is gated by the PWM B pin. -// 0x2 -> Counter advances with each rising edge of the PWM B pin. -// 0x3 -> Counter advances with each falling edge of the PWM B pin. -#define PWM_CH11_CSR_DIVMODE_RESET _u(0x0) -#define PWM_CH11_CSR_DIVMODE_BITS _u(0x00000030) -#define PWM_CH11_CSR_DIVMODE_MSB _u(5) -#define PWM_CH11_CSR_DIVMODE_LSB _u(4) -#define PWM_CH11_CSR_DIVMODE_ACCESS "RW" -#define PWM_CH11_CSR_DIVMODE_VALUE_DIV _u(0x0) -#define PWM_CH11_CSR_DIVMODE_VALUE_LEVEL _u(0x1) -#define PWM_CH11_CSR_DIVMODE_VALUE_RISE _u(0x2) -#define PWM_CH11_CSR_DIVMODE_VALUE_FALL _u(0x3) -// ----------------------------------------------------------------------------- -// Field : PWM_CH11_CSR_B_INV -// Description : Invert output B -#define PWM_CH11_CSR_B_INV_RESET _u(0x0) -#define PWM_CH11_CSR_B_INV_BITS _u(0x00000008) -#define PWM_CH11_CSR_B_INV_MSB _u(3) -#define PWM_CH11_CSR_B_INV_LSB _u(3) -#define PWM_CH11_CSR_B_INV_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_CH11_CSR_A_INV -// Description : Invert output A -#define PWM_CH11_CSR_A_INV_RESET _u(0x0) -#define PWM_CH11_CSR_A_INV_BITS _u(0x00000004) -#define PWM_CH11_CSR_A_INV_MSB _u(2) -#define PWM_CH11_CSR_A_INV_LSB _u(2) -#define PWM_CH11_CSR_A_INV_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_CH11_CSR_PH_CORRECT -// Description : 1: Enable phase-correct modulation. 0: Trailing-edge -#define PWM_CH11_CSR_PH_CORRECT_RESET _u(0x0) -#define PWM_CH11_CSR_PH_CORRECT_BITS _u(0x00000002) -#define PWM_CH11_CSR_PH_CORRECT_MSB _u(1) -#define PWM_CH11_CSR_PH_CORRECT_LSB _u(1) -#define PWM_CH11_CSR_PH_CORRECT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_CH11_CSR_EN -// Description : Enable the PWM channel. -#define PWM_CH11_CSR_EN_RESET _u(0x0) -#define PWM_CH11_CSR_EN_BITS _u(0x00000001) -#define PWM_CH11_CSR_EN_MSB _u(0) -#define PWM_CH11_CSR_EN_LSB _u(0) -#define PWM_CH11_CSR_EN_ACCESS "RW" -// ============================================================================= -// Register : PWM_CH11_DIV -// Description : INT and FRAC form a fixed-point fractional number. -// Counting rate is system clock frequency divided by this number. -// Fractional division uses simple 1st-order sigma-delta. -#define PWM_CH11_DIV_OFFSET _u(0x000000e0) -#define PWM_CH11_DIV_BITS _u(0x00000fff) -#define PWM_CH11_DIV_RESET _u(0x00000010) -// ----------------------------------------------------------------------------- -// Field : PWM_CH11_DIV_INT -#define PWM_CH11_DIV_INT_RESET _u(0x01) -#define PWM_CH11_DIV_INT_BITS _u(0x00000ff0) -#define PWM_CH11_DIV_INT_MSB _u(11) -#define PWM_CH11_DIV_INT_LSB _u(4) -#define PWM_CH11_DIV_INT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_CH11_DIV_FRAC -#define PWM_CH11_DIV_FRAC_RESET _u(0x0) -#define PWM_CH11_DIV_FRAC_BITS _u(0x0000000f) -#define PWM_CH11_DIV_FRAC_MSB _u(3) -#define PWM_CH11_DIV_FRAC_LSB _u(0) -#define PWM_CH11_DIV_FRAC_ACCESS "RW" -// ============================================================================= -// Register : PWM_CH11_CTR -// Description : Direct access to the PWM counter -#define PWM_CH11_CTR_OFFSET _u(0x000000e4) -#define PWM_CH11_CTR_BITS _u(0x0000ffff) -#define PWM_CH11_CTR_RESET _u(0x00000000) -#define PWM_CH11_CTR_MSB _u(15) -#define PWM_CH11_CTR_LSB _u(0) -#define PWM_CH11_CTR_ACCESS "RW" -// ============================================================================= -// Register : PWM_CH11_CC -// Description : Counter compare values -#define PWM_CH11_CC_OFFSET _u(0x000000e8) -#define PWM_CH11_CC_BITS _u(0xffffffff) -#define PWM_CH11_CC_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : PWM_CH11_CC_B -#define PWM_CH11_CC_B_RESET _u(0x0000) -#define PWM_CH11_CC_B_BITS _u(0xffff0000) -#define PWM_CH11_CC_B_MSB _u(31) -#define PWM_CH11_CC_B_LSB _u(16) -#define PWM_CH11_CC_B_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_CH11_CC_A -#define PWM_CH11_CC_A_RESET _u(0x0000) -#define PWM_CH11_CC_A_BITS _u(0x0000ffff) -#define PWM_CH11_CC_A_MSB _u(15) -#define PWM_CH11_CC_A_LSB _u(0) -#define PWM_CH11_CC_A_ACCESS "RW" -// ============================================================================= -// Register : PWM_CH11_TOP -// Description : Counter wrap value -#define PWM_CH11_TOP_OFFSET _u(0x000000ec) -#define PWM_CH11_TOP_BITS _u(0x0000ffff) -#define PWM_CH11_TOP_RESET _u(0x0000ffff) -#define PWM_CH11_TOP_MSB _u(15) -#define PWM_CH11_TOP_LSB _u(0) -#define PWM_CH11_TOP_ACCESS "RW" -// ============================================================================= -// Register : PWM_EN -// Description : This register aliases the CSR_EN bits for all channels. -// Writing to this register allows multiple channels to be enabled -// or disabled simultaneously, so they can run in perfect sync. -// For each channel, there is only one physical EN register bit, -// which can be accessed through here or CHx_CSR. -#define PWM_EN_OFFSET _u(0x000000f0) -#define PWM_EN_BITS _u(0x00000fff) -#define PWM_EN_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : PWM_EN_CH11 -#define PWM_EN_CH11_RESET _u(0x0) -#define PWM_EN_CH11_BITS _u(0x00000800) -#define PWM_EN_CH11_MSB _u(11) -#define PWM_EN_CH11_LSB _u(11) -#define PWM_EN_CH11_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_EN_CH10 -#define PWM_EN_CH10_RESET _u(0x0) -#define PWM_EN_CH10_BITS _u(0x00000400) -#define PWM_EN_CH10_MSB _u(10) -#define PWM_EN_CH10_LSB _u(10) -#define PWM_EN_CH10_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_EN_CH9 -#define PWM_EN_CH9_RESET _u(0x0) -#define PWM_EN_CH9_BITS _u(0x00000200) -#define PWM_EN_CH9_MSB _u(9) -#define PWM_EN_CH9_LSB _u(9) -#define PWM_EN_CH9_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_EN_CH8 -#define PWM_EN_CH8_RESET _u(0x0) -#define PWM_EN_CH8_BITS _u(0x00000100) -#define PWM_EN_CH8_MSB _u(8) -#define PWM_EN_CH8_LSB _u(8) -#define PWM_EN_CH8_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_EN_CH7 -#define PWM_EN_CH7_RESET _u(0x0) -#define PWM_EN_CH7_BITS _u(0x00000080) -#define PWM_EN_CH7_MSB _u(7) -#define PWM_EN_CH7_LSB _u(7) -#define PWM_EN_CH7_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_EN_CH6 -#define PWM_EN_CH6_RESET _u(0x0) -#define PWM_EN_CH6_BITS _u(0x00000040) -#define PWM_EN_CH6_MSB _u(6) -#define PWM_EN_CH6_LSB _u(6) -#define PWM_EN_CH6_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_EN_CH5 -#define PWM_EN_CH5_RESET _u(0x0) -#define PWM_EN_CH5_BITS _u(0x00000020) -#define PWM_EN_CH5_MSB _u(5) -#define PWM_EN_CH5_LSB _u(5) -#define PWM_EN_CH5_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_EN_CH4 -#define PWM_EN_CH4_RESET _u(0x0) -#define PWM_EN_CH4_BITS _u(0x00000010) -#define PWM_EN_CH4_MSB _u(4) -#define PWM_EN_CH4_LSB _u(4) -#define PWM_EN_CH4_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_EN_CH3 -#define PWM_EN_CH3_RESET _u(0x0) -#define PWM_EN_CH3_BITS _u(0x00000008) -#define PWM_EN_CH3_MSB _u(3) -#define PWM_EN_CH3_LSB _u(3) -#define PWM_EN_CH3_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_EN_CH2 -#define PWM_EN_CH2_RESET _u(0x0) -#define PWM_EN_CH2_BITS _u(0x00000004) -#define PWM_EN_CH2_MSB _u(2) -#define PWM_EN_CH2_LSB _u(2) -#define PWM_EN_CH2_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_EN_CH1 -#define PWM_EN_CH1_RESET _u(0x0) -#define PWM_EN_CH1_BITS _u(0x00000002) -#define PWM_EN_CH1_MSB _u(1) -#define PWM_EN_CH1_LSB _u(1) -#define PWM_EN_CH1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_EN_CH0 -#define PWM_EN_CH0_RESET _u(0x0) -#define PWM_EN_CH0_BITS _u(0x00000001) -#define PWM_EN_CH0_MSB _u(0) -#define PWM_EN_CH0_LSB _u(0) -#define PWM_EN_CH0_ACCESS "RW" -// ============================================================================= -// Register : PWM_INTR -// Description : Raw Interrupts -#define PWM_INTR_OFFSET _u(0x000000f4) -#define PWM_INTR_BITS _u(0x00000fff) -#define PWM_INTR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : PWM_INTR_CH11 -#define PWM_INTR_CH11_RESET _u(0x0) -#define PWM_INTR_CH11_BITS _u(0x00000800) -#define PWM_INTR_CH11_MSB _u(11) -#define PWM_INTR_CH11_LSB _u(11) -#define PWM_INTR_CH11_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : PWM_INTR_CH10 -#define PWM_INTR_CH10_RESET _u(0x0) -#define PWM_INTR_CH10_BITS _u(0x00000400) -#define PWM_INTR_CH10_MSB _u(10) -#define PWM_INTR_CH10_LSB _u(10) -#define PWM_INTR_CH10_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : PWM_INTR_CH9 -#define PWM_INTR_CH9_RESET _u(0x0) -#define PWM_INTR_CH9_BITS _u(0x00000200) -#define PWM_INTR_CH9_MSB _u(9) -#define PWM_INTR_CH9_LSB _u(9) -#define PWM_INTR_CH9_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : PWM_INTR_CH8 -#define PWM_INTR_CH8_RESET _u(0x0) -#define PWM_INTR_CH8_BITS _u(0x00000100) -#define PWM_INTR_CH8_MSB _u(8) -#define PWM_INTR_CH8_LSB _u(8) -#define PWM_INTR_CH8_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : PWM_INTR_CH7 -#define PWM_INTR_CH7_RESET _u(0x0) -#define PWM_INTR_CH7_BITS _u(0x00000080) -#define PWM_INTR_CH7_MSB _u(7) -#define PWM_INTR_CH7_LSB _u(7) -#define PWM_INTR_CH7_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : PWM_INTR_CH6 -#define PWM_INTR_CH6_RESET _u(0x0) -#define PWM_INTR_CH6_BITS _u(0x00000040) -#define PWM_INTR_CH6_MSB _u(6) -#define PWM_INTR_CH6_LSB _u(6) -#define PWM_INTR_CH6_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : PWM_INTR_CH5 -#define PWM_INTR_CH5_RESET _u(0x0) -#define PWM_INTR_CH5_BITS _u(0x00000020) -#define PWM_INTR_CH5_MSB _u(5) -#define PWM_INTR_CH5_LSB _u(5) -#define PWM_INTR_CH5_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : PWM_INTR_CH4 -#define PWM_INTR_CH4_RESET _u(0x0) -#define PWM_INTR_CH4_BITS _u(0x00000010) -#define PWM_INTR_CH4_MSB _u(4) -#define PWM_INTR_CH4_LSB _u(4) -#define PWM_INTR_CH4_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : PWM_INTR_CH3 -#define PWM_INTR_CH3_RESET _u(0x0) -#define PWM_INTR_CH3_BITS _u(0x00000008) -#define PWM_INTR_CH3_MSB _u(3) -#define PWM_INTR_CH3_LSB _u(3) -#define PWM_INTR_CH3_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : PWM_INTR_CH2 -#define PWM_INTR_CH2_RESET _u(0x0) -#define PWM_INTR_CH2_BITS _u(0x00000004) -#define PWM_INTR_CH2_MSB _u(2) -#define PWM_INTR_CH2_LSB _u(2) -#define PWM_INTR_CH2_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : PWM_INTR_CH1 -#define PWM_INTR_CH1_RESET _u(0x0) -#define PWM_INTR_CH1_BITS _u(0x00000002) -#define PWM_INTR_CH1_MSB _u(1) -#define PWM_INTR_CH1_LSB _u(1) -#define PWM_INTR_CH1_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : PWM_INTR_CH0 -#define PWM_INTR_CH0_RESET _u(0x0) -#define PWM_INTR_CH0_BITS _u(0x00000001) -#define PWM_INTR_CH0_MSB _u(0) -#define PWM_INTR_CH0_LSB _u(0) -#define PWM_INTR_CH0_ACCESS "WC" -// ============================================================================= -// Register : PWM_IRQ0_INTE -// Description : Interrupt Enable for irq0 -#define PWM_IRQ0_INTE_OFFSET _u(0x000000f8) -#define PWM_IRQ0_INTE_BITS _u(0x00000fff) -#define PWM_IRQ0_INTE_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : PWM_IRQ0_INTE_CH11 -#define PWM_IRQ0_INTE_CH11_RESET _u(0x0) -#define PWM_IRQ0_INTE_CH11_BITS _u(0x00000800) -#define PWM_IRQ0_INTE_CH11_MSB _u(11) -#define PWM_IRQ0_INTE_CH11_LSB _u(11) -#define PWM_IRQ0_INTE_CH11_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_IRQ0_INTE_CH10 -#define PWM_IRQ0_INTE_CH10_RESET _u(0x0) -#define PWM_IRQ0_INTE_CH10_BITS _u(0x00000400) -#define PWM_IRQ0_INTE_CH10_MSB _u(10) -#define PWM_IRQ0_INTE_CH10_LSB _u(10) -#define PWM_IRQ0_INTE_CH10_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_IRQ0_INTE_CH9 -#define PWM_IRQ0_INTE_CH9_RESET _u(0x0) -#define PWM_IRQ0_INTE_CH9_BITS _u(0x00000200) -#define PWM_IRQ0_INTE_CH9_MSB _u(9) -#define PWM_IRQ0_INTE_CH9_LSB _u(9) -#define PWM_IRQ0_INTE_CH9_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_IRQ0_INTE_CH8 -#define PWM_IRQ0_INTE_CH8_RESET _u(0x0) -#define PWM_IRQ0_INTE_CH8_BITS _u(0x00000100) -#define PWM_IRQ0_INTE_CH8_MSB _u(8) -#define PWM_IRQ0_INTE_CH8_LSB _u(8) -#define PWM_IRQ0_INTE_CH8_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_IRQ0_INTE_CH7 -#define PWM_IRQ0_INTE_CH7_RESET _u(0x0) -#define PWM_IRQ0_INTE_CH7_BITS _u(0x00000080) -#define PWM_IRQ0_INTE_CH7_MSB _u(7) -#define PWM_IRQ0_INTE_CH7_LSB _u(7) -#define PWM_IRQ0_INTE_CH7_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_IRQ0_INTE_CH6 -#define PWM_IRQ0_INTE_CH6_RESET _u(0x0) -#define PWM_IRQ0_INTE_CH6_BITS _u(0x00000040) -#define PWM_IRQ0_INTE_CH6_MSB _u(6) -#define PWM_IRQ0_INTE_CH6_LSB _u(6) -#define PWM_IRQ0_INTE_CH6_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_IRQ0_INTE_CH5 -#define PWM_IRQ0_INTE_CH5_RESET _u(0x0) -#define PWM_IRQ0_INTE_CH5_BITS _u(0x00000020) -#define PWM_IRQ0_INTE_CH5_MSB _u(5) -#define PWM_IRQ0_INTE_CH5_LSB _u(5) -#define PWM_IRQ0_INTE_CH5_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_IRQ0_INTE_CH4 -#define PWM_IRQ0_INTE_CH4_RESET _u(0x0) -#define PWM_IRQ0_INTE_CH4_BITS _u(0x00000010) -#define PWM_IRQ0_INTE_CH4_MSB _u(4) -#define PWM_IRQ0_INTE_CH4_LSB _u(4) -#define PWM_IRQ0_INTE_CH4_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_IRQ0_INTE_CH3 -#define PWM_IRQ0_INTE_CH3_RESET _u(0x0) -#define PWM_IRQ0_INTE_CH3_BITS _u(0x00000008) -#define PWM_IRQ0_INTE_CH3_MSB _u(3) -#define PWM_IRQ0_INTE_CH3_LSB _u(3) -#define PWM_IRQ0_INTE_CH3_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_IRQ0_INTE_CH2 -#define PWM_IRQ0_INTE_CH2_RESET _u(0x0) -#define PWM_IRQ0_INTE_CH2_BITS _u(0x00000004) -#define PWM_IRQ0_INTE_CH2_MSB _u(2) -#define PWM_IRQ0_INTE_CH2_LSB _u(2) -#define PWM_IRQ0_INTE_CH2_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_IRQ0_INTE_CH1 -#define PWM_IRQ0_INTE_CH1_RESET _u(0x0) -#define PWM_IRQ0_INTE_CH1_BITS _u(0x00000002) -#define PWM_IRQ0_INTE_CH1_MSB _u(1) -#define PWM_IRQ0_INTE_CH1_LSB _u(1) -#define PWM_IRQ0_INTE_CH1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_IRQ0_INTE_CH0 -#define PWM_IRQ0_INTE_CH0_RESET _u(0x0) -#define PWM_IRQ0_INTE_CH0_BITS _u(0x00000001) -#define PWM_IRQ0_INTE_CH0_MSB _u(0) -#define PWM_IRQ0_INTE_CH0_LSB _u(0) -#define PWM_IRQ0_INTE_CH0_ACCESS "RW" -// ============================================================================= -// Register : PWM_IRQ0_INTF -// Description : Interrupt Force for irq0 -#define PWM_IRQ0_INTF_OFFSET _u(0x000000fc) -#define PWM_IRQ0_INTF_BITS _u(0x00000fff) -#define PWM_IRQ0_INTF_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : PWM_IRQ0_INTF_CH11 -#define PWM_IRQ0_INTF_CH11_RESET _u(0x0) -#define PWM_IRQ0_INTF_CH11_BITS _u(0x00000800) -#define PWM_IRQ0_INTF_CH11_MSB _u(11) -#define PWM_IRQ0_INTF_CH11_LSB _u(11) -#define PWM_IRQ0_INTF_CH11_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_IRQ0_INTF_CH10 -#define PWM_IRQ0_INTF_CH10_RESET _u(0x0) -#define PWM_IRQ0_INTF_CH10_BITS _u(0x00000400) -#define PWM_IRQ0_INTF_CH10_MSB _u(10) -#define PWM_IRQ0_INTF_CH10_LSB _u(10) -#define PWM_IRQ0_INTF_CH10_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_IRQ0_INTF_CH9 -#define PWM_IRQ0_INTF_CH9_RESET _u(0x0) -#define PWM_IRQ0_INTF_CH9_BITS _u(0x00000200) -#define PWM_IRQ0_INTF_CH9_MSB _u(9) -#define PWM_IRQ0_INTF_CH9_LSB _u(9) -#define PWM_IRQ0_INTF_CH9_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_IRQ0_INTF_CH8 -#define PWM_IRQ0_INTF_CH8_RESET _u(0x0) -#define PWM_IRQ0_INTF_CH8_BITS _u(0x00000100) -#define PWM_IRQ0_INTF_CH8_MSB _u(8) -#define PWM_IRQ0_INTF_CH8_LSB _u(8) -#define PWM_IRQ0_INTF_CH8_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_IRQ0_INTF_CH7 -#define PWM_IRQ0_INTF_CH7_RESET _u(0x0) -#define PWM_IRQ0_INTF_CH7_BITS _u(0x00000080) -#define PWM_IRQ0_INTF_CH7_MSB _u(7) -#define PWM_IRQ0_INTF_CH7_LSB _u(7) -#define PWM_IRQ0_INTF_CH7_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_IRQ0_INTF_CH6 -#define PWM_IRQ0_INTF_CH6_RESET _u(0x0) -#define PWM_IRQ0_INTF_CH6_BITS _u(0x00000040) -#define PWM_IRQ0_INTF_CH6_MSB _u(6) -#define PWM_IRQ0_INTF_CH6_LSB _u(6) -#define PWM_IRQ0_INTF_CH6_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_IRQ0_INTF_CH5 -#define PWM_IRQ0_INTF_CH5_RESET _u(0x0) -#define PWM_IRQ0_INTF_CH5_BITS _u(0x00000020) -#define PWM_IRQ0_INTF_CH5_MSB _u(5) -#define PWM_IRQ0_INTF_CH5_LSB _u(5) -#define PWM_IRQ0_INTF_CH5_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_IRQ0_INTF_CH4 -#define PWM_IRQ0_INTF_CH4_RESET _u(0x0) -#define PWM_IRQ0_INTF_CH4_BITS _u(0x00000010) -#define PWM_IRQ0_INTF_CH4_MSB _u(4) -#define PWM_IRQ0_INTF_CH4_LSB _u(4) -#define PWM_IRQ0_INTF_CH4_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_IRQ0_INTF_CH3 -#define PWM_IRQ0_INTF_CH3_RESET _u(0x0) -#define PWM_IRQ0_INTF_CH3_BITS _u(0x00000008) -#define PWM_IRQ0_INTF_CH3_MSB _u(3) -#define PWM_IRQ0_INTF_CH3_LSB _u(3) -#define PWM_IRQ0_INTF_CH3_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_IRQ0_INTF_CH2 -#define PWM_IRQ0_INTF_CH2_RESET _u(0x0) -#define PWM_IRQ0_INTF_CH2_BITS _u(0x00000004) -#define PWM_IRQ0_INTF_CH2_MSB _u(2) -#define PWM_IRQ0_INTF_CH2_LSB _u(2) -#define PWM_IRQ0_INTF_CH2_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_IRQ0_INTF_CH1 -#define PWM_IRQ0_INTF_CH1_RESET _u(0x0) -#define PWM_IRQ0_INTF_CH1_BITS _u(0x00000002) -#define PWM_IRQ0_INTF_CH1_MSB _u(1) -#define PWM_IRQ0_INTF_CH1_LSB _u(1) -#define PWM_IRQ0_INTF_CH1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_IRQ0_INTF_CH0 -#define PWM_IRQ0_INTF_CH0_RESET _u(0x0) -#define PWM_IRQ0_INTF_CH0_BITS _u(0x00000001) -#define PWM_IRQ0_INTF_CH0_MSB _u(0) -#define PWM_IRQ0_INTF_CH0_LSB _u(0) -#define PWM_IRQ0_INTF_CH0_ACCESS "RW" -// ============================================================================= -// Register : PWM_IRQ0_INTS -// Description : Interrupt status after masking & forcing for irq0 -#define PWM_IRQ0_INTS_OFFSET _u(0x00000100) -#define PWM_IRQ0_INTS_BITS _u(0x00000fff) -#define PWM_IRQ0_INTS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : PWM_IRQ0_INTS_CH11 -#define PWM_IRQ0_INTS_CH11_RESET _u(0x0) -#define PWM_IRQ0_INTS_CH11_BITS _u(0x00000800) -#define PWM_IRQ0_INTS_CH11_MSB _u(11) -#define PWM_IRQ0_INTS_CH11_LSB _u(11) -#define PWM_IRQ0_INTS_CH11_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PWM_IRQ0_INTS_CH10 -#define PWM_IRQ0_INTS_CH10_RESET _u(0x0) -#define PWM_IRQ0_INTS_CH10_BITS _u(0x00000400) -#define PWM_IRQ0_INTS_CH10_MSB _u(10) -#define PWM_IRQ0_INTS_CH10_LSB _u(10) -#define PWM_IRQ0_INTS_CH10_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PWM_IRQ0_INTS_CH9 -#define PWM_IRQ0_INTS_CH9_RESET _u(0x0) -#define PWM_IRQ0_INTS_CH9_BITS _u(0x00000200) -#define PWM_IRQ0_INTS_CH9_MSB _u(9) -#define PWM_IRQ0_INTS_CH9_LSB _u(9) -#define PWM_IRQ0_INTS_CH9_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PWM_IRQ0_INTS_CH8 -#define PWM_IRQ0_INTS_CH8_RESET _u(0x0) -#define PWM_IRQ0_INTS_CH8_BITS _u(0x00000100) -#define PWM_IRQ0_INTS_CH8_MSB _u(8) -#define PWM_IRQ0_INTS_CH8_LSB _u(8) -#define PWM_IRQ0_INTS_CH8_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PWM_IRQ0_INTS_CH7 -#define PWM_IRQ0_INTS_CH7_RESET _u(0x0) -#define PWM_IRQ0_INTS_CH7_BITS _u(0x00000080) -#define PWM_IRQ0_INTS_CH7_MSB _u(7) -#define PWM_IRQ0_INTS_CH7_LSB _u(7) -#define PWM_IRQ0_INTS_CH7_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PWM_IRQ0_INTS_CH6 -#define PWM_IRQ0_INTS_CH6_RESET _u(0x0) -#define PWM_IRQ0_INTS_CH6_BITS _u(0x00000040) -#define PWM_IRQ0_INTS_CH6_MSB _u(6) -#define PWM_IRQ0_INTS_CH6_LSB _u(6) -#define PWM_IRQ0_INTS_CH6_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PWM_IRQ0_INTS_CH5 -#define PWM_IRQ0_INTS_CH5_RESET _u(0x0) -#define PWM_IRQ0_INTS_CH5_BITS _u(0x00000020) -#define PWM_IRQ0_INTS_CH5_MSB _u(5) -#define PWM_IRQ0_INTS_CH5_LSB _u(5) -#define PWM_IRQ0_INTS_CH5_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PWM_IRQ0_INTS_CH4 -#define PWM_IRQ0_INTS_CH4_RESET _u(0x0) -#define PWM_IRQ0_INTS_CH4_BITS _u(0x00000010) -#define PWM_IRQ0_INTS_CH4_MSB _u(4) -#define PWM_IRQ0_INTS_CH4_LSB _u(4) -#define PWM_IRQ0_INTS_CH4_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PWM_IRQ0_INTS_CH3 -#define PWM_IRQ0_INTS_CH3_RESET _u(0x0) -#define PWM_IRQ0_INTS_CH3_BITS _u(0x00000008) -#define PWM_IRQ0_INTS_CH3_MSB _u(3) -#define PWM_IRQ0_INTS_CH3_LSB _u(3) -#define PWM_IRQ0_INTS_CH3_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PWM_IRQ0_INTS_CH2 -#define PWM_IRQ0_INTS_CH2_RESET _u(0x0) -#define PWM_IRQ0_INTS_CH2_BITS _u(0x00000004) -#define PWM_IRQ0_INTS_CH2_MSB _u(2) -#define PWM_IRQ0_INTS_CH2_LSB _u(2) -#define PWM_IRQ0_INTS_CH2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PWM_IRQ0_INTS_CH1 -#define PWM_IRQ0_INTS_CH1_RESET _u(0x0) -#define PWM_IRQ0_INTS_CH1_BITS _u(0x00000002) -#define PWM_IRQ0_INTS_CH1_MSB _u(1) -#define PWM_IRQ0_INTS_CH1_LSB _u(1) -#define PWM_IRQ0_INTS_CH1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PWM_IRQ0_INTS_CH0 -#define PWM_IRQ0_INTS_CH0_RESET _u(0x0) -#define PWM_IRQ0_INTS_CH0_BITS _u(0x00000001) -#define PWM_IRQ0_INTS_CH0_MSB _u(0) -#define PWM_IRQ0_INTS_CH0_LSB _u(0) -#define PWM_IRQ0_INTS_CH0_ACCESS "RO" -// ============================================================================= -// Register : PWM_IRQ1_INTE -// Description : Interrupt Enable for irq1 -#define PWM_IRQ1_INTE_OFFSET _u(0x00000104) -#define PWM_IRQ1_INTE_BITS _u(0x00000fff) -#define PWM_IRQ1_INTE_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : PWM_IRQ1_INTE_CH11 -#define PWM_IRQ1_INTE_CH11_RESET _u(0x0) -#define PWM_IRQ1_INTE_CH11_BITS _u(0x00000800) -#define PWM_IRQ1_INTE_CH11_MSB _u(11) -#define PWM_IRQ1_INTE_CH11_LSB _u(11) -#define PWM_IRQ1_INTE_CH11_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_IRQ1_INTE_CH10 -#define PWM_IRQ1_INTE_CH10_RESET _u(0x0) -#define PWM_IRQ1_INTE_CH10_BITS _u(0x00000400) -#define PWM_IRQ1_INTE_CH10_MSB _u(10) -#define PWM_IRQ1_INTE_CH10_LSB _u(10) -#define PWM_IRQ1_INTE_CH10_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_IRQ1_INTE_CH9 -#define PWM_IRQ1_INTE_CH9_RESET _u(0x0) -#define PWM_IRQ1_INTE_CH9_BITS _u(0x00000200) -#define PWM_IRQ1_INTE_CH9_MSB _u(9) -#define PWM_IRQ1_INTE_CH9_LSB _u(9) -#define PWM_IRQ1_INTE_CH9_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_IRQ1_INTE_CH8 -#define PWM_IRQ1_INTE_CH8_RESET _u(0x0) -#define PWM_IRQ1_INTE_CH8_BITS _u(0x00000100) -#define PWM_IRQ1_INTE_CH8_MSB _u(8) -#define PWM_IRQ1_INTE_CH8_LSB _u(8) -#define PWM_IRQ1_INTE_CH8_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_IRQ1_INTE_CH7 -#define PWM_IRQ1_INTE_CH7_RESET _u(0x0) -#define PWM_IRQ1_INTE_CH7_BITS _u(0x00000080) -#define PWM_IRQ1_INTE_CH7_MSB _u(7) -#define PWM_IRQ1_INTE_CH7_LSB _u(7) -#define PWM_IRQ1_INTE_CH7_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_IRQ1_INTE_CH6 -#define PWM_IRQ1_INTE_CH6_RESET _u(0x0) -#define PWM_IRQ1_INTE_CH6_BITS _u(0x00000040) -#define PWM_IRQ1_INTE_CH6_MSB _u(6) -#define PWM_IRQ1_INTE_CH6_LSB _u(6) -#define PWM_IRQ1_INTE_CH6_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_IRQ1_INTE_CH5 -#define PWM_IRQ1_INTE_CH5_RESET _u(0x0) -#define PWM_IRQ1_INTE_CH5_BITS _u(0x00000020) -#define PWM_IRQ1_INTE_CH5_MSB _u(5) -#define PWM_IRQ1_INTE_CH5_LSB _u(5) -#define PWM_IRQ1_INTE_CH5_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_IRQ1_INTE_CH4 -#define PWM_IRQ1_INTE_CH4_RESET _u(0x0) -#define PWM_IRQ1_INTE_CH4_BITS _u(0x00000010) -#define PWM_IRQ1_INTE_CH4_MSB _u(4) -#define PWM_IRQ1_INTE_CH4_LSB _u(4) -#define PWM_IRQ1_INTE_CH4_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_IRQ1_INTE_CH3 -#define PWM_IRQ1_INTE_CH3_RESET _u(0x0) -#define PWM_IRQ1_INTE_CH3_BITS _u(0x00000008) -#define PWM_IRQ1_INTE_CH3_MSB _u(3) -#define PWM_IRQ1_INTE_CH3_LSB _u(3) -#define PWM_IRQ1_INTE_CH3_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_IRQ1_INTE_CH2 -#define PWM_IRQ1_INTE_CH2_RESET _u(0x0) -#define PWM_IRQ1_INTE_CH2_BITS _u(0x00000004) -#define PWM_IRQ1_INTE_CH2_MSB _u(2) -#define PWM_IRQ1_INTE_CH2_LSB _u(2) -#define PWM_IRQ1_INTE_CH2_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_IRQ1_INTE_CH1 -#define PWM_IRQ1_INTE_CH1_RESET _u(0x0) -#define PWM_IRQ1_INTE_CH1_BITS _u(0x00000002) -#define PWM_IRQ1_INTE_CH1_MSB _u(1) -#define PWM_IRQ1_INTE_CH1_LSB _u(1) -#define PWM_IRQ1_INTE_CH1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_IRQ1_INTE_CH0 -#define PWM_IRQ1_INTE_CH0_RESET _u(0x0) -#define PWM_IRQ1_INTE_CH0_BITS _u(0x00000001) -#define PWM_IRQ1_INTE_CH0_MSB _u(0) -#define PWM_IRQ1_INTE_CH0_LSB _u(0) -#define PWM_IRQ1_INTE_CH0_ACCESS "RW" -// ============================================================================= -// Register : PWM_IRQ1_INTF -// Description : Interrupt Force for irq1 -#define PWM_IRQ1_INTF_OFFSET _u(0x00000108) -#define PWM_IRQ1_INTF_BITS _u(0x00000fff) -#define PWM_IRQ1_INTF_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : PWM_IRQ1_INTF_CH11 -#define PWM_IRQ1_INTF_CH11_RESET _u(0x0) -#define PWM_IRQ1_INTF_CH11_BITS _u(0x00000800) -#define PWM_IRQ1_INTF_CH11_MSB _u(11) -#define PWM_IRQ1_INTF_CH11_LSB _u(11) -#define PWM_IRQ1_INTF_CH11_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_IRQ1_INTF_CH10 -#define PWM_IRQ1_INTF_CH10_RESET _u(0x0) -#define PWM_IRQ1_INTF_CH10_BITS _u(0x00000400) -#define PWM_IRQ1_INTF_CH10_MSB _u(10) -#define PWM_IRQ1_INTF_CH10_LSB _u(10) -#define PWM_IRQ1_INTF_CH10_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_IRQ1_INTF_CH9 -#define PWM_IRQ1_INTF_CH9_RESET _u(0x0) -#define PWM_IRQ1_INTF_CH9_BITS _u(0x00000200) -#define PWM_IRQ1_INTF_CH9_MSB _u(9) -#define PWM_IRQ1_INTF_CH9_LSB _u(9) -#define PWM_IRQ1_INTF_CH9_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_IRQ1_INTF_CH8 -#define PWM_IRQ1_INTF_CH8_RESET _u(0x0) -#define PWM_IRQ1_INTF_CH8_BITS _u(0x00000100) -#define PWM_IRQ1_INTF_CH8_MSB _u(8) -#define PWM_IRQ1_INTF_CH8_LSB _u(8) -#define PWM_IRQ1_INTF_CH8_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_IRQ1_INTF_CH7 -#define PWM_IRQ1_INTF_CH7_RESET _u(0x0) -#define PWM_IRQ1_INTF_CH7_BITS _u(0x00000080) -#define PWM_IRQ1_INTF_CH7_MSB _u(7) -#define PWM_IRQ1_INTF_CH7_LSB _u(7) -#define PWM_IRQ1_INTF_CH7_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_IRQ1_INTF_CH6 -#define PWM_IRQ1_INTF_CH6_RESET _u(0x0) -#define PWM_IRQ1_INTF_CH6_BITS _u(0x00000040) -#define PWM_IRQ1_INTF_CH6_MSB _u(6) -#define PWM_IRQ1_INTF_CH6_LSB _u(6) -#define PWM_IRQ1_INTF_CH6_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_IRQ1_INTF_CH5 -#define PWM_IRQ1_INTF_CH5_RESET _u(0x0) -#define PWM_IRQ1_INTF_CH5_BITS _u(0x00000020) -#define PWM_IRQ1_INTF_CH5_MSB _u(5) -#define PWM_IRQ1_INTF_CH5_LSB _u(5) -#define PWM_IRQ1_INTF_CH5_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_IRQ1_INTF_CH4 -#define PWM_IRQ1_INTF_CH4_RESET _u(0x0) -#define PWM_IRQ1_INTF_CH4_BITS _u(0x00000010) -#define PWM_IRQ1_INTF_CH4_MSB _u(4) -#define PWM_IRQ1_INTF_CH4_LSB _u(4) -#define PWM_IRQ1_INTF_CH4_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_IRQ1_INTF_CH3 -#define PWM_IRQ1_INTF_CH3_RESET _u(0x0) -#define PWM_IRQ1_INTF_CH3_BITS _u(0x00000008) -#define PWM_IRQ1_INTF_CH3_MSB _u(3) -#define PWM_IRQ1_INTF_CH3_LSB _u(3) -#define PWM_IRQ1_INTF_CH3_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_IRQ1_INTF_CH2 -#define PWM_IRQ1_INTF_CH2_RESET _u(0x0) -#define PWM_IRQ1_INTF_CH2_BITS _u(0x00000004) -#define PWM_IRQ1_INTF_CH2_MSB _u(2) -#define PWM_IRQ1_INTF_CH2_LSB _u(2) -#define PWM_IRQ1_INTF_CH2_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_IRQ1_INTF_CH1 -#define PWM_IRQ1_INTF_CH1_RESET _u(0x0) -#define PWM_IRQ1_INTF_CH1_BITS _u(0x00000002) -#define PWM_IRQ1_INTF_CH1_MSB _u(1) -#define PWM_IRQ1_INTF_CH1_LSB _u(1) -#define PWM_IRQ1_INTF_CH1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : PWM_IRQ1_INTF_CH0 -#define PWM_IRQ1_INTF_CH0_RESET _u(0x0) -#define PWM_IRQ1_INTF_CH0_BITS _u(0x00000001) -#define PWM_IRQ1_INTF_CH0_MSB _u(0) -#define PWM_IRQ1_INTF_CH0_LSB _u(0) -#define PWM_IRQ1_INTF_CH0_ACCESS "RW" -// ============================================================================= -// Register : PWM_IRQ1_INTS -// Description : Interrupt status after masking & forcing for irq1 -#define PWM_IRQ1_INTS_OFFSET _u(0x0000010c) -#define PWM_IRQ1_INTS_BITS _u(0x00000fff) -#define PWM_IRQ1_INTS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : PWM_IRQ1_INTS_CH11 -#define PWM_IRQ1_INTS_CH11_RESET _u(0x0) -#define PWM_IRQ1_INTS_CH11_BITS _u(0x00000800) -#define PWM_IRQ1_INTS_CH11_MSB _u(11) -#define PWM_IRQ1_INTS_CH11_LSB _u(11) -#define PWM_IRQ1_INTS_CH11_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PWM_IRQ1_INTS_CH10 -#define PWM_IRQ1_INTS_CH10_RESET _u(0x0) -#define PWM_IRQ1_INTS_CH10_BITS _u(0x00000400) -#define PWM_IRQ1_INTS_CH10_MSB _u(10) -#define PWM_IRQ1_INTS_CH10_LSB _u(10) -#define PWM_IRQ1_INTS_CH10_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PWM_IRQ1_INTS_CH9 -#define PWM_IRQ1_INTS_CH9_RESET _u(0x0) -#define PWM_IRQ1_INTS_CH9_BITS _u(0x00000200) -#define PWM_IRQ1_INTS_CH9_MSB _u(9) -#define PWM_IRQ1_INTS_CH9_LSB _u(9) -#define PWM_IRQ1_INTS_CH9_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PWM_IRQ1_INTS_CH8 -#define PWM_IRQ1_INTS_CH8_RESET _u(0x0) -#define PWM_IRQ1_INTS_CH8_BITS _u(0x00000100) -#define PWM_IRQ1_INTS_CH8_MSB _u(8) -#define PWM_IRQ1_INTS_CH8_LSB _u(8) -#define PWM_IRQ1_INTS_CH8_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PWM_IRQ1_INTS_CH7 -#define PWM_IRQ1_INTS_CH7_RESET _u(0x0) -#define PWM_IRQ1_INTS_CH7_BITS _u(0x00000080) -#define PWM_IRQ1_INTS_CH7_MSB _u(7) -#define PWM_IRQ1_INTS_CH7_LSB _u(7) -#define PWM_IRQ1_INTS_CH7_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PWM_IRQ1_INTS_CH6 -#define PWM_IRQ1_INTS_CH6_RESET _u(0x0) -#define PWM_IRQ1_INTS_CH6_BITS _u(0x00000040) -#define PWM_IRQ1_INTS_CH6_MSB _u(6) -#define PWM_IRQ1_INTS_CH6_LSB _u(6) -#define PWM_IRQ1_INTS_CH6_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PWM_IRQ1_INTS_CH5 -#define PWM_IRQ1_INTS_CH5_RESET _u(0x0) -#define PWM_IRQ1_INTS_CH5_BITS _u(0x00000020) -#define PWM_IRQ1_INTS_CH5_MSB _u(5) -#define PWM_IRQ1_INTS_CH5_LSB _u(5) -#define PWM_IRQ1_INTS_CH5_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PWM_IRQ1_INTS_CH4 -#define PWM_IRQ1_INTS_CH4_RESET _u(0x0) -#define PWM_IRQ1_INTS_CH4_BITS _u(0x00000010) -#define PWM_IRQ1_INTS_CH4_MSB _u(4) -#define PWM_IRQ1_INTS_CH4_LSB _u(4) -#define PWM_IRQ1_INTS_CH4_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PWM_IRQ1_INTS_CH3 -#define PWM_IRQ1_INTS_CH3_RESET _u(0x0) -#define PWM_IRQ1_INTS_CH3_BITS _u(0x00000008) -#define PWM_IRQ1_INTS_CH3_MSB _u(3) -#define PWM_IRQ1_INTS_CH3_LSB _u(3) -#define PWM_IRQ1_INTS_CH3_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PWM_IRQ1_INTS_CH2 -#define PWM_IRQ1_INTS_CH2_RESET _u(0x0) -#define PWM_IRQ1_INTS_CH2_BITS _u(0x00000004) -#define PWM_IRQ1_INTS_CH2_MSB _u(2) -#define PWM_IRQ1_INTS_CH2_LSB _u(2) -#define PWM_IRQ1_INTS_CH2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PWM_IRQ1_INTS_CH1 -#define PWM_IRQ1_INTS_CH1_RESET _u(0x0) -#define PWM_IRQ1_INTS_CH1_BITS _u(0x00000002) -#define PWM_IRQ1_INTS_CH1_MSB _u(1) -#define PWM_IRQ1_INTS_CH1_LSB _u(1) -#define PWM_IRQ1_INTS_CH1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : PWM_IRQ1_INTS_CH0 -#define PWM_IRQ1_INTS_CH0_RESET _u(0x0) -#define PWM_IRQ1_INTS_CH0_BITS _u(0x00000001) -#define PWM_IRQ1_INTS_CH0_MSB _u(0) -#define PWM_IRQ1_INTS_CH0_LSB _u(0) -#define PWM_IRQ1_INTS_CH0_ACCESS "RO" -// ============================================================================= -#endif // _HARDWARE_REGS_PWM_H - diff --git a/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/qmi.h b/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/qmi.h deleted file mode 100644 index 3efebc13f3..0000000000 --- a/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/qmi.h +++ /dev/null @@ -1,1781 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -// ============================================================================= -// Register block : QMI -// Version : 1 -// Bus type : apb -// Description : QSPI Memory Interface. -// -// Provides a memory-mapped interface to up to two -// SPI/DSPI/QSPI flash or PSRAM devices. Also provides a serial -// interface for programming and configuration of the external -// device. -// ============================================================================= -#ifndef _HARDWARE_REGS_QMI_H -#define _HARDWARE_REGS_QMI_H -// ============================================================================= -// Register : QMI_DIRECT_CSR -// Description : Control and status for direct serial mode -// -// Direct serial mode allows the processor to send and receive raw -// serial frames, for programming, configuration and control of -// the external memory devices. Only SPI mode 0 (CPOL=0 CPHA=0) is -// supported. -#define QMI_DIRECT_CSR_OFFSET _u(0x00000000) -#define QMI_DIRECT_CSR_BITS _u(0xffdf7ccf) -#define QMI_DIRECT_CSR_RESET _u(0x01800000) -// ----------------------------------------------------------------------------- -// Field : QMI_DIRECT_CSR_RXDELAY -// Description : Delay the read data sample timing, in units of one half of a -// system clock cycle. (Not necessarily half of an SCK cycle.) -#define QMI_DIRECT_CSR_RXDELAY_RESET _u(0x0) -#define QMI_DIRECT_CSR_RXDELAY_BITS _u(0xc0000000) -#define QMI_DIRECT_CSR_RXDELAY_MSB _u(31) -#define QMI_DIRECT_CSR_RXDELAY_LSB _u(30) -#define QMI_DIRECT_CSR_RXDELAY_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : QMI_DIRECT_CSR_CLKDIV -// Description : Clock divisor for direct serial mode. Divisors of 1..255 are -// encoded directly, and the maximum divisor of 256 is encoded by -// a value of CLKDIV=0. -// -// The clock divisor can be changed on-the-fly by software, -// without halting or otherwise coordinating with the serial -// interface. The serial interface will sample the latest clock -// divisor each time it begins the transmission of a new byte. -#define QMI_DIRECT_CSR_CLKDIV_RESET _u(0x06) -#define QMI_DIRECT_CSR_CLKDIV_BITS _u(0x3fc00000) -#define QMI_DIRECT_CSR_CLKDIV_MSB _u(29) -#define QMI_DIRECT_CSR_CLKDIV_LSB _u(22) -#define QMI_DIRECT_CSR_CLKDIV_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : QMI_DIRECT_CSR_RXLEVEL -// Description : Current level of DIRECT_RX FIFO -#define QMI_DIRECT_CSR_RXLEVEL_RESET _u(0x0) -#define QMI_DIRECT_CSR_RXLEVEL_BITS _u(0x001c0000) -#define QMI_DIRECT_CSR_RXLEVEL_MSB _u(20) -#define QMI_DIRECT_CSR_RXLEVEL_LSB _u(18) -#define QMI_DIRECT_CSR_RXLEVEL_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : QMI_DIRECT_CSR_RXFULL -// Description : When 1, the DIRECT_RX FIFO is currently full. The serial -// interface will be stalled until data is popped; the interface -// will not begin a new serial frame when the DIRECT_TX FIFO is -// empty or the DIRECT_RX FIFO is full. -#define QMI_DIRECT_CSR_RXFULL_RESET _u(0x0) -#define QMI_DIRECT_CSR_RXFULL_BITS _u(0x00020000) -#define QMI_DIRECT_CSR_RXFULL_MSB _u(17) -#define QMI_DIRECT_CSR_RXFULL_LSB _u(17) -#define QMI_DIRECT_CSR_RXFULL_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : QMI_DIRECT_CSR_RXEMPTY -// Description : When 1, the DIRECT_RX FIFO is currently empty. If the processor -// attempts to read more data, the FIFO state is not affected, but -// the value returned to the processor is undefined. -#define QMI_DIRECT_CSR_RXEMPTY_RESET _u(0x0) -#define QMI_DIRECT_CSR_RXEMPTY_BITS _u(0x00010000) -#define QMI_DIRECT_CSR_RXEMPTY_MSB _u(16) -#define QMI_DIRECT_CSR_RXEMPTY_LSB _u(16) -#define QMI_DIRECT_CSR_RXEMPTY_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : QMI_DIRECT_CSR_TXLEVEL -// Description : Current level of DIRECT_TX FIFO -#define QMI_DIRECT_CSR_TXLEVEL_RESET _u(0x0) -#define QMI_DIRECT_CSR_TXLEVEL_BITS _u(0x00007000) -#define QMI_DIRECT_CSR_TXLEVEL_MSB _u(14) -#define QMI_DIRECT_CSR_TXLEVEL_LSB _u(12) -#define QMI_DIRECT_CSR_TXLEVEL_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : QMI_DIRECT_CSR_TXEMPTY -// Description : When 1, the DIRECT_TX FIFO is currently empty. Unless the -// processor pushes more data, transmission will stop and BUSY -// will go low once the current 8-bit serial frame completes. -#define QMI_DIRECT_CSR_TXEMPTY_RESET _u(0x0) -#define QMI_DIRECT_CSR_TXEMPTY_BITS _u(0x00000800) -#define QMI_DIRECT_CSR_TXEMPTY_MSB _u(11) -#define QMI_DIRECT_CSR_TXEMPTY_LSB _u(11) -#define QMI_DIRECT_CSR_TXEMPTY_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : QMI_DIRECT_CSR_TXFULL -// Description : When 1, the DIRECT_TX FIFO is currently full. If the processor -// tries to write more data, that data will be ignored. -#define QMI_DIRECT_CSR_TXFULL_RESET _u(0x0) -#define QMI_DIRECT_CSR_TXFULL_BITS _u(0x00000400) -#define QMI_DIRECT_CSR_TXFULL_MSB _u(10) -#define QMI_DIRECT_CSR_TXFULL_LSB _u(10) -#define QMI_DIRECT_CSR_TXFULL_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : QMI_DIRECT_CSR_AUTO_CS1N -// Description : When 1, automatically assert the CS1n chip select line whenever -// the BUSY flag is set. -#define QMI_DIRECT_CSR_AUTO_CS1N_RESET _u(0x0) -#define QMI_DIRECT_CSR_AUTO_CS1N_BITS _u(0x00000080) -#define QMI_DIRECT_CSR_AUTO_CS1N_MSB _u(7) -#define QMI_DIRECT_CSR_AUTO_CS1N_LSB _u(7) -#define QMI_DIRECT_CSR_AUTO_CS1N_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : QMI_DIRECT_CSR_AUTO_CS0N -// Description : When 1, automatically assert the CS0n chip select line whenever -// the BUSY flag is set. -#define QMI_DIRECT_CSR_AUTO_CS0N_RESET _u(0x0) -#define QMI_DIRECT_CSR_AUTO_CS0N_BITS _u(0x00000040) -#define QMI_DIRECT_CSR_AUTO_CS0N_MSB _u(6) -#define QMI_DIRECT_CSR_AUTO_CS0N_LSB _u(6) -#define QMI_DIRECT_CSR_AUTO_CS0N_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : QMI_DIRECT_CSR_ASSERT_CS1N -// Description : When 1, assert (i.e. drive low) the CS1n chip select line. -// -// Note that this applies even when DIRECT_CSR_EN is 0. -#define QMI_DIRECT_CSR_ASSERT_CS1N_RESET _u(0x0) -#define QMI_DIRECT_CSR_ASSERT_CS1N_BITS _u(0x00000008) -#define QMI_DIRECT_CSR_ASSERT_CS1N_MSB _u(3) -#define QMI_DIRECT_CSR_ASSERT_CS1N_LSB _u(3) -#define QMI_DIRECT_CSR_ASSERT_CS1N_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : QMI_DIRECT_CSR_ASSERT_CS0N -// Description : When 1, assert (i.e. drive low) the CS0n chip select line. -// -// Note that this applies even when DIRECT_CSR_EN is 0. -#define QMI_DIRECT_CSR_ASSERT_CS0N_RESET _u(0x0) -#define QMI_DIRECT_CSR_ASSERT_CS0N_BITS _u(0x00000004) -#define QMI_DIRECT_CSR_ASSERT_CS0N_MSB _u(2) -#define QMI_DIRECT_CSR_ASSERT_CS0N_LSB _u(2) -#define QMI_DIRECT_CSR_ASSERT_CS0N_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : QMI_DIRECT_CSR_BUSY -// Description : Direct mode busy flag. If 1, data is currently being shifted -// in/out (or would be if the interface were not stalled on the RX -// FIFO), and the chip select must not yet be deasserted. -// -// The busy flag will also be set to 1 if a memory-mapped transfer -// is still in progress when direct mode is enabled. Direct mode -// blocks new memory-mapped transfers, but can't halt a transfer -// that is already in progress. If there is a chance that memory- -// mapped transfers may be in progress, the busy flag should be -// polled for 0 before asserting the chip select. -// -// (In practice you will usually discover this timing condition -// through other means, because any subsequent memory-mapped -// transfers when direct mode is enabled will return bus errors, -// which are difficult to ignore.) -#define QMI_DIRECT_CSR_BUSY_RESET _u(0x0) -#define QMI_DIRECT_CSR_BUSY_BITS _u(0x00000002) -#define QMI_DIRECT_CSR_BUSY_MSB _u(1) -#define QMI_DIRECT_CSR_BUSY_LSB _u(1) -#define QMI_DIRECT_CSR_BUSY_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : QMI_DIRECT_CSR_EN -// Description : Enable direct mode. -// -// In direct mode, software controls the chip select lines, and -// can perform direct SPI transfers by pushing data to the -// DIRECT_TX FIFO, and popping the same amount of data from the -// DIRECT_RX FIFO. -// -// Memory-mapped accesses will generate bus errors when direct -// serial mode is enabled. -#define QMI_DIRECT_CSR_EN_RESET _u(0x0) -#define QMI_DIRECT_CSR_EN_BITS _u(0x00000001) -#define QMI_DIRECT_CSR_EN_MSB _u(0) -#define QMI_DIRECT_CSR_EN_LSB _u(0) -#define QMI_DIRECT_CSR_EN_ACCESS "RW" -// ============================================================================= -// Register : QMI_DIRECT_TX -// Description : Transmit FIFO for direct mode -#define QMI_DIRECT_TX_OFFSET _u(0x00000004) -#define QMI_DIRECT_TX_BITS _u(0x001fffff) -#define QMI_DIRECT_TX_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : QMI_DIRECT_TX_NOPUSH -// Description : Inhibit the RX FIFO push that would correspond to this TX FIFO -// entry. -// -// Useful to avoid garbage appearing in the RX FIFO when pushing -// the command at the beginning of a SPI transfer. -#define QMI_DIRECT_TX_NOPUSH_RESET _u(0x0) -#define QMI_DIRECT_TX_NOPUSH_BITS _u(0x00100000) -#define QMI_DIRECT_TX_NOPUSH_MSB _u(20) -#define QMI_DIRECT_TX_NOPUSH_LSB _u(20) -#define QMI_DIRECT_TX_NOPUSH_ACCESS "WF" -// ----------------------------------------------------------------------------- -// Field : QMI_DIRECT_TX_OE -// Description : Output enable (active-high). For single width (SPI), this field -// is ignored, and SD0 is always set to output, with SD1 always -// set to input. -// -// For dual and quad width (DSPI/QSPI), this sets whether the -// relevant SDx pads are set to output whilst transferring this -// FIFO record. In this case the command/address should have OE -// set, and the data transfer should have OE set or clear -// depending on the direction of the transfer. -#define QMI_DIRECT_TX_OE_RESET _u(0x0) -#define QMI_DIRECT_TX_OE_BITS _u(0x00080000) -#define QMI_DIRECT_TX_OE_MSB _u(19) -#define QMI_DIRECT_TX_OE_LSB _u(19) -#define QMI_DIRECT_TX_OE_ACCESS "WF" -// ----------------------------------------------------------------------------- -// Field : QMI_DIRECT_TX_DWIDTH -// Description : Data width. If 0, hardware will transmit the 8 LSBs of the -// DIRECT_TX DATA field, and return an 8-bit value in the 8 LSBs -// of DIRECT_RX. If 1, the full 16-bit width is used. 8-bit and -// 16-bit transfers can be mixed freely. -#define QMI_DIRECT_TX_DWIDTH_RESET _u(0x0) -#define QMI_DIRECT_TX_DWIDTH_BITS _u(0x00040000) -#define QMI_DIRECT_TX_DWIDTH_MSB _u(18) -#define QMI_DIRECT_TX_DWIDTH_LSB _u(18) -#define QMI_DIRECT_TX_DWIDTH_ACCESS "WF" -// ----------------------------------------------------------------------------- -// Field : QMI_DIRECT_TX_IWIDTH -// Description : Configure whether this FIFO record is transferred with -// single/dual/quad interface width (0/1/2). Different widths can -// be mixed freely. -// 0x0 -> Single width -// 0x1 -> Dual width -// 0x2 -> Quad width -#define QMI_DIRECT_TX_IWIDTH_RESET _u(0x0) -#define QMI_DIRECT_TX_IWIDTH_BITS _u(0x00030000) -#define QMI_DIRECT_TX_IWIDTH_MSB _u(17) -#define QMI_DIRECT_TX_IWIDTH_LSB _u(16) -#define QMI_DIRECT_TX_IWIDTH_ACCESS "WF" -#define QMI_DIRECT_TX_IWIDTH_VALUE_S _u(0x0) -#define QMI_DIRECT_TX_IWIDTH_VALUE_D _u(0x1) -#define QMI_DIRECT_TX_IWIDTH_VALUE_Q _u(0x2) -// ----------------------------------------------------------------------------- -// Field : QMI_DIRECT_TX_DATA -// Description : Data pushed here will be clocked out falling edges of SCK (or -// before the very first rising edge of SCK, if this is the first -// pulse). For each byte clocked out, the interface will -// simultaneously sample one byte, on rising edges of SCK, and -// push this to the DIRECT_RX FIFO. -// -// For 16-bit data, the least-significant byte is transmitted -// first. -#define QMI_DIRECT_TX_DATA_RESET _u(0x0000) -#define QMI_DIRECT_TX_DATA_BITS _u(0x0000ffff) -#define QMI_DIRECT_TX_DATA_MSB _u(15) -#define QMI_DIRECT_TX_DATA_LSB _u(0) -#define QMI_DIRECT_TX_DATA_ACCESS "WF" -// ============================================================================= -// Register : QMI_DIRECT_RX -// Description : Receive FIFO for direct mode -// With each byte clocked out on the serial interface, one byte -// will simultaneously be clocked in, and will appear in this -// FIFO. The serial interface will stall when this FIFO is full, -// to avoid dropping data. -// -// When 16-bit data is pushed into the TX FIFO, the corresponding -// RX FIFO push will also contain 16 bits of data. The least- -// significant byte is the first one received. -#define QMI_DIRECT_RX_OFFSET _u(0x00000008) -#define QMI_DIRECT_RX_BITS _u(0x0000ffff) -#define QMI_DIRECT_RX_RESET _u(0x00000000) -#define QMI_DIRECT_RX_MSB _u(15) -#define QMI_DIRECT_RX_LSB _u(0) -#define QMI_DIRECT_RX_ACCESS "RF" -// ============================================================================= -// Register : QMI_M0_TIMING -// Description : Timing configuration register for memory address window 0. -#define QMI_M0_TIMING_OFFSET _u(0x0000000c) -#define QMI_M0_TIMING_BITS _u(0xf3fff7ff) -#define QMI_M0_TIMING_RESET _u(0x40000004) -// ----------------------------------------------------------------------------- -// Field : QMI_M0_TIMING_COOLDOWN -// Description : Chip select cooldown period. When a memory transfer finishes, -// the chip select remains asserted for 64 x COOLDOWN system clock -// cycles, plus half an SCK clock period (rounded up for odd SCK -// divisors). After this cooldown expires, the chip select is -// always deasserted to save power. -// -// If the next memory access arrives within the cooldown period, -// the QMI may be able to append more SCK cycles to the currently -// ongoing SPI transfer, rather than starting a new transfer. This -// reduces access latency and increases bus throughput. -// -// Specifically, the next access must be in the same direction -// (read/write), access the same memory window (chip select 0/1), -// and follow sequentially the address of the last transfer. If -// any of these are false, the new access will first deassert the -// chip select, then begin a new transfer. -// -// If COOLDOWN is 0, the address alignment configured by PAGEBREAK -// has been reached, or the total chip select assertion limit -// MAX_SELECT has been reached, the cooldown period is skipped, -// and the chip select will always be deasserted one half SCK -// period after the transfer finishes. -#define QMI_M0_TIMING_COOLDOWN_RESET _u(0x1) -#define QMI_M0_TIMING_COOLDOWN_BITS _u(0xc0000000) -#define QMI_M0_TIMING_COOLDOWN_MSB _u(31) -#define QMI_M0_TIMING_COOLDOWN_LSB _u(30) -#define QMI_M0_TIMING_COOLDOWN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : QMI_M0_TIMING_PAGEBREAK -// Description : When page break is enabled, chip select will automatically -// deassert when crossing certain power-of-2-aligned address -// boundaries. The next access will always begin a new read/write -// SPI burst, even if the address of the next access follows in -// sequence with the last access before the page boundary. -// -// Some flash and PSRAM devices forbid crossing page boundaries -// with a single read/write transfer, or restrict the operating -// frequency for transfers that do cross page a boundary. This -// option allows the QMI to safely support those devices. -// -// This field has no effect when COOLDOWN is disabled. -// 0x0 -> No page boundary is enforced -// 0x1 -> Break bursts crossing a 256-byte page boundary -// 0x2 -> Break bursts crossing a 1024-byte quad-page boundary -// 0x3 -> Break bursts crossing a 4096-byte sector boundary -#define QMI_M0_TIMING_PAGEBREAK_RESET _u(0x0) -#define QMI_M0_TIMING_PAGEBREAK_BITS _u(0x30000000) -#define QMI_M0_TIMING_PAGEBREAK_MSB _u(29) -#define QMI_M0_TIMING_PAGEBREAK_LSB _u(28) -#define QMI_M0_TIMING_PAGEBREAK_ACCESS "RW" -#define QMI_M0_TIMING_PAGEBREAK_VALUE_NONE _u(0x0) -#define QMI_M0_TIMING_PAGEBREAK_VALUE_256 _u(0x1) -#define QMI_M0_TIMING_PAGEBREAK_VALUE_1024 _u(0x2) -#define QMI_M0_TIMING_PAGEBREAK_VALUE_4096 _u(0x3) -// ----------------------------------------------------------------------------- -// Field : QMI_M0_TIMING_SELECT_SETUP -// Description : Add up to one additional system clock cycle of setup between -// chip select assertion and the first rising edge of SCK. -// -// The default setup time is one half SCK period, which is usually -// sufficient except for very high SCK frequencies with some flash -// devices. -#define QMI_M0_TIMING_SELECT_SETUP_RESET _u(0x0) -#define QMI_M0_TIMING_SELECT_SETUP_BITS _u(0x02000000) -#define QMI_M0_TIMING_SELECT_SETUP_MSB _u(25) -#define QMI_M0_TIMING_SELECT_SETUP_LSB _u(25) -#define QMI_M0_TIMING_SELECT_SETUP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : QMI_M0_TIMING_SELECT_HOLD -// Description : Add up to three additional system clock cycles of active hold -// between the last falling edge of SCK and the deassertion of -// this window's chip select. -// -// The default hold time is one system clock cycle. Note that -// flash datasheets usually give chip select active hold time from -// the last *rising* edge of SCK, and so even zero hold from the -// last falling edge would be safe. -// -// Note that this is a minimum hold time guaranteed by the QMI: -// the actual chip select active hold may be slightly longer for -// read transfers with low clock divisors and/or high sample -// delays. Specifically, if the point two cycles after the last RX -// data sample is later than the last SCK falling edge, then the -// hold time is measured from *this* point. -// -// Note also that, in case the final SCK pulse is masked to save -// energy (true for non-DTR reads when COOLDOWN is disabled or -// PAGE_BREAK is reached), all of QMI's timing logic behaves as -// though the clock pulse were still present. The SELECT_HOLD time -// is applied from the point where the last SCK falling edge would -// be if the clock pulse were not masked. -#define QMI_M0_TIMING_SELECT_HOLD_RESET _u(0x0) -#define QMI_M0_TIMING_SELECT_HOLD_BITS _u(0x01800000) -#define QMI_M0_TIMING_SELECT_HOLD_MSB _u(24) -#define QMI_M0_TIMING_SELECT_HOLD_LSB _u(23) -#define QMI_M0_TIMING_SELECT_HOLD_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : QMI_M0_TIMING_MAX_SELECT -// Description : Enforce a maximum assertion duration for this window's chip -// select, in units of 64 system clock cycles. If 0, the QMI is -// permitted to keep the chip select asserted indefinitely when -// servicing sequential memory accesses (see COOLDOWN). -// -// This feature is required to meet timing constraints of PSRAM -// devices, which specify a maximum chip select assertion so they -// can perform DRAM refresh cycles. See also MIN_DESELECT, which -// can enforce a minimum deselect time. -// -// If a memory access is in progress at the time MAX_SELECT is -// reached, the QMI will wait for the access to complete before -// deasserting the chip select. This additional time must be -// accounted for to calculate a safe MAX_SELECT value. In the -// worst case, this may be a fully-formed serial transfer, -// including command prefix and address, with a data payload as -// large as one cache line. -#define QMI_M0_TIMING_MAX_SELECT_RESET _u(0x00) -#define QMI_M0_TIMING_MAX_SELECT_BITS _u(0x007e0000) -#define QMI_M0_TIMING_MAX_SELECT_MSB _u(22) -#define QMI_M0_TIMING_MAX_SELECT_LSB _u(17) -#define QMI_M0_TIMING_MAX_SELECT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : QMI_M0_TIMING_MIN_DESELECT -// Description : After this window's chip select is deasserted, it remains -// deasserted for half an SCK cycle (rounded up to an integer -// number of system clock cycles), plus MIN_DESELECT additional -// system clock cycles, before the QMI reasserts either chip -// select pin. -// -// Nonzero values may be required for PSRAM devices which enforce -// a longer minimum CS deselect time, so that they can perform -// internal DRAM refresh cycles whilst deselected. -#define QMI_M0_TIMING_MIN_DESELECT_RESET _u(0x00) -#define QMI_M0_TIMING_MIN_DESELECT_BITS _u(0x0001f000) -#define QMI_M0_TIMING_MIN_DESELECT_MSB _u(16) -#define QMI_M0_TIMING_MIN_DESELECT_LSB _u(12) -#define QMI_M0_TIMING_MIN_DESELECT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : QMI_M0_TIMING_RXDELAY -// Description : Delay the read data sample timing, in units of one half of a -// system clock cycle. (Not necessarily half of an SCK cycle.) An -// RXDELAY of 0 means the sample is captured at the SDI input -// registers simultaneously with the rising edge of SCK launched -// from the SCK output register. -// -// At higher SCK frequencies, RXDELAY may need to be increased to -// account for the round trip delay of the pads, and the clock- -// to-Q delay of the QSPI memory device. -#define QMI_M0_TIMING_RXDELAY_RESET _u(0x0) -#define QMI_M0_TIMING_RXDELAY_BITS _u(0x00000700) -#define QMI_M0_TIMING_RXDELAY_MSB _u(10) -#define QMI_M0_TIMING_RXDELAY_LSB _u(8) -#define QMI_M0_TIMING_RXDELAY_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : QMI_M0_TIMING_CLKDIV -// Description : Clock divisor. Odd and even divisors are supported. Defines the -// SCK clock period in units of 1 system clock cycle. Divisors -// 1..255 are encoded directly, and a divisor of 256 is encoded -// with a value of CLKDIV=0. -// -// The clock divisor can be changed on-the-fly, even when the QMI -// is currently accessing memory in this address window. All other -// parameters must only be changed when the QMI is idle. -// -// If software is increasing CLKDIV in anticipation of an increase -// in the system clock frequency, a dummy access to either memory -// window (and appropriate processor barriers/fences) must be -// inserted after the Mx_TIMING write to ensure the SCK divisor -// change is in effect _before_ the system clock is changed. -#define QMI_M0_TIMING_CLKDIV_RESET _u(0x04) -#define QMI_M0_TIMING_CLKDIV_BITS _u(0x000000ff) -#define QMI_M0_TIMING_CLKDIV_MSB _u(7) -#define QMI_M0_TIMING_CLKDIV_LSB _u(0) -#define QMI_M0_TIMING_CLKDIV_ACCESS "RW" -// ============================================================================= -// Register : QMI_M0_RFMT -// Description : Read transfer format configuration for memory address window 0. -// -// Configure the bus width of each transfer phase individually, -// and configure the length or presence of the command prefix, -// command suffix and dummy/turnaround transfer phases. Only -// 24-bit addresses are supported. -// -// The reset value of the M0_RFMT register is configured to -// support a basic 03h serial read transfer with no additional -// configuration. -#define QMI_M0_RFMT_OFFSET _u(0x00000010) -#define QMI_M0_RFMT_BITS _u(0x1007d3ff) -#define QMI_M0_RFMT_RESET _u(0x00001000) -// ----------------------------------------------------------------------------- -// Field : QMI_M0_RFMT_DTR -// Description : Enable double transfer rate (DTR) for read commands: address, -// suffix and read data phases are active on both edges of SCK. -// SDO data is launched centre-aligned on each SCK edge, and SDI -// data is captured on the SCK edge that follows its launch. -// -// DTR is implemented by halving the clock rate; SCK has a period -// of 2 x CLK_DIV throughout the transfer. The prefix and dummy -// phases are still single transfer rate. -// -// If the suffix is quad-width, it must be 0 or 8 bits in length, -// to ensure an even number of SCK edges. -#define QMI_M0_RFMT_DTR_RESET _u(0x0) -#define QMI_M0_RFMT_DTR_BITS _u(0x10000000) -#define QMI_M0_RFMT_DTR_MSB _u(28) -#define QMI_M0_RFMT_DTR_LSB _u(28) -#define QMI_M0_RFMT_DTR_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : QMI_M0_RFMT_DUMMY_LEN -// Description : Length of dummy phase between command suffix and data phase, in -// units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 -// for single) -// 0x0 -> No dummy phase -// 0x1 -> 4 dummy bits -// 0x2 -> 8 dummy bits -// 0x3 -> 12 dummy bits -// 0x4 -> 16 dummy bits -// 0x5 -> 20 dummy bits -// 0x6 -> 24 dummy bits -// 0x7 -> 28 dummy bits -#define QMI_M0_RFMT_DUMMY_LEN_RESET _u(0x0) -#define QMI_M0_RFMT_DUMMY_LEN_BITS _u(0x00070000) -#define QMI_M0_RFMT_DUMMY_LEN_MSB _u(18) -#define QMI_M0_RFMT_DUMMY_LEN_LSB _u(16) -#define QMI_M0_RFMT_DUMMY_LEN_ACCESS "RW" -#define QMI_M0_RFMT_DUMMY_LEN_VALUE_NONE _u(0x0) -#define QMI_M0_RFMT_DUMMY_LEN_VALUE_4 _u(0x1) -#define QMI_M0_RFMT_DUMMY_LEN_VALUE_8 _u(0x2) -#define QMI_M0_RFMT_DUMMY_LEN_VALUE_12 _u(0x3) -#define QMI_M0_RFMT_DUMMY_LEN_VALUE_16 _u(0x4) -#define QMI_M0_RFMT_DUMMY_LEN_VALUE_20 _u(0x5) -#define QMI_M0_RFMT_DUMMY_LEN_VALUE_24 _u(0x6) -#define QMI_M0_RFMT_DUMMY_LEN_VALUE_28 _u(0x7) -// ----------------------------------------------------------------------------- -// Field : QMI_M0_RFMT_SUFFIX_LEN -// Description : Length of post-address command suffix, in units of 4 bits. -// (i.e. 1 cycle for quad width, 2 for dual, 4 for single) -// -// Only values of 0 and 8 bits are supported. -// 0x0 -> No suffix -// 0x2 -> 8-bit suffix -#define QMI_M0_RFMT_SUFFIX_LEN_RESET _u(0x0) -#define QMI_M0_RFMT_SUFFIX_LEN_BITS _u(0x0000c000) -#define QMI_M0_RFMT_SUFFIX_LEN_MSB _u(15) -#define QMI_M0_RFMT_SUFFIX_LEN_LSB _u(14) -#define QMI_M0_RFMT_SUFFIX_LEN_ACCESS "RW" -#define QMI_M0_RFMT_SUFFIX_LEN_VALUE_NONE _u(0x0) -#define QMI_M0_RFMT_SUFFIX_LEN_VALUE_8 _u(0x2) -// ----------------------------------------------------------------------------- -// Field : QMI_M0_RFMT_PREFIX_LEN -// Description : Length of command prefix, in units of 8 bits. (i.e. 2 cycles -// for quad width, 4 for dual, 8 for single) -// 0x0 -> No prefix -// 0x1 -> 8-bit prefix -#define QMI_M0_RFMT_PREFIX_LEN_RESET _u(0x1) -#define QMI_M0_RFMT_PREFIX_LEN_BITS _u(0x00001000) -#define QMI_M0_RFMT_PREFIX_LEN_MSB _u(12) -#define QMI_M0_RFMT_PREFIX_LEN_LSB _u(12) -#define QMI_M0_RFMT_PREFIX_LEN_ACCESS "RW" -#define QMI_M0_RFMT_PREFIX_LEN_VALUE_NONE _u(0x0) -#define QMI_M0_RFMT_PREFIX_LEN_VALUE_8 _u(0x1) -// ----------------------------------------------------------------------------- -// Field : QMI_M0_RFMT_DATA_WIDTH -// Description : The width used for the data transfer -// 0x0 -> Single width -// 0x1 -> Dual width -// 0x2 -> Quad width -#define QMI_M0_RFMT_DATA_WIDTH_RESET _u(0x0) -#define QMI_M0_RFMT_DATA_WIDTH_BITS _u(0x00000300) -#define QMI_M0_RFMT_DATA_WIDTH_MSB _u(9) -#define QMI_M0_RFMT_DATA_WIDTH_LSB _u(8) -#define QMI_M0_RFMT_DATA_WIDTH_ACCESS "RW" -#define QMI_M0_RFMT_DATA_WIDTH_VALUE_S _u(0x0) -#define QMI_M0_RFMT_DATA_WIDTH_VALUE_D _u(0x1) -#define QMI_M0_RFMT_DATA_WIDTH_VALUE_Q _u(0x2) -// ----------------------------------------------------------------------------- -// Field : QMI_M0_RFMT_DUMMY_WIDTH -// Description : The width used for the dummy phase, if any. -// -// If width is single, SD0/MOSI is held asserted low during the -// dummy phase, and SD1...SD3 are tristated. If width is -// dual/quad, all IOs are tristated during the dummy phase. -// 0x0 -> Single width -// 0x1 -> Dual width -// 0x2 -> Quad width -#define QMI_M0_RFMT_DUMMY_WIDTH_RESET _u(0x0) -#define QMI_M0_RFMT_DUMMY_WIDTH_BITS _u(0x000000c0) -#define QMI_M0_RFMT_DUMMY_WIDTH_MSB _u(7) -#define QMI_M0_RFMT_DUMMY_WIDTH_LSB _u(6) -#define QMI_M0_RFMT_DUMMY_WIDTH_ACCESS "RW" -#define QMI_M0_RFMT_DUMMY_WIDTH_VALUE_S _u(0x0) -#define QMI_M0_RFMT_DUMMY_WIDTH_VALUE_D _u(0x1) -#define QMI_M0_RFMT_DUMMY_WIDTH_VALUE_Q _u(0x2) -// ----------------------------------------------------------------------------- -// Field : QMI_M0_RFMT_SUFFIX_WIDTH -// Description : The width used for the post-address command suffix, if any -// 0x0 -> Single width -// 0x1 -> Dual width -// 0x2 -> Quad width -#define QMI_M0_RFMT_SUFFIX_WIDTH_RESET _u(0x0) -#define QMI_M0_RFMT_SUFFIX_WIDTH_BITS _u(0x00000030) -#define QMI_M0_RFMT_SUFFIX_WIDTH_MSB _u(5) -#define QMI_M0_RFMT_SUFFIX_WIDTH_LSB _u(4) -#define QMI_M0_RFMT_SUFFIX_WIDTH_ACCESS "RW" -#define QMI_M0_RFMT_SUFFIX_WIDTH_VALUE_S _u(0x0) -#define QMI_M0_RFMT_SUFFIX_WIDTH_VALUE_D _u(0x1) -#define QMI_M0_RFMT_SUFFIX_WIDTH_VALUE_Q _u(0x2) -// ----------------------------------------------------------------------------- -// Field : QMI_M0_RFMT_ADDR_WIDTH -// Description : The transfer width used for the address. The address phase -// always transfers 24 bits in total. -// 0x0 -> Single width -// 0x1 -> Dual width -// 0x2 -> Quad width -#define QMI_M0_RFMT_ADDR_WIDTH_RESET _u(0x0) -#define QMI_M0_RFMT_ADDR_WIDTH_BITS _u(0x0000000c) -#define QMI_M0_RFMT_ADDR_WIDTH_MSB _u(3) -#define QMI_M0_RFMT_ADDR_WIDTH_LSB _u(2) -#define QMI_M0_RFMT_ADDR_WIDTH_ACCESS "RW" -#define QMI_M0_RFMT_ADDR_WIDTH_VALUE_S _u(0x0) -#define QMI_M0_RFMT_ADDR_WIDTH_VALUE_D _u(0x1) -#define QMI_M0_RFMT_ADDR_WIDTH_VALUE_Q _u(0x2) -// ----------------------------------------------------------------------------- -// Field : QMI_M0_RFMT_PREFIX_WIDTH -// Description : The transfer width used for the command prefix, if any -// 0x0 -> Single width -// 0x1 -> Dual width -// 0x2 -> Quad width -#define QMI_M0_RFMT_PREFIX_WIDTH_RESET _u(0x0) -#define QMI_M0_RFMT_PREFIX_WIDTH_BITS _u(0x00000003) -#define QMI_M0_RFMT_PREFIX_WIDTH_MSB _u(1) -#define QMI_M0_RFMT_PREFIX_WIDTH_LSB _u(0) -#define QMI_M0_RFMT_PREFIX_WIDTH_ACCESS "RW" -#define QMI_M0_RFMT_PREFIX_WIDTH_VALUE_S _u(0x0) -#define QMI_M0_RFMT_PREFIX_WIDTH_VALUE_D _u(0x1) -#define QMI_M0_RFMT_PREFIX_WIDTH_VALUE_Q _u(0x2) -// ============================================================================= -// Register : QMI_M0_RCMD -// Description : Command constants used for reads from memory address window 0. -// -// The reset value of the M0_RCMD register is configured to -// support a basic 03h serial read transfer with no additional -// configuration. -#define QMI_M0_RCMD_OFFSET _u(0x00000014) -#define QMI_M0_RCMD_BITS _u(0x0000ffff) -#define QMI_M0_RCMD_RESET _u(0x0000a003) -// ----------------------------------------------------------------------------- -// Field : QMI_M0_RCMD_SUFFIX -// Description : The command suffix bits following the address, if -// Mx_RFMT_SUFFIX_LEN is nonzero. -#define QMI_M0_RCMD_SUFFIX_RESET _u(0xa0) -#define QMI_M0_RCMD_SUFFIX_BITS _u(0x0000ff00) -#define QMI_M0_RCMD_SUFFIX_MSB _u(15) -#define QMI_M0_RCMD_SUFFIX_LSB _u(8) -#define QMI_M0_RCMD_SUFFIX_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : QMI_M0_RCMD_PREFIX -// Description : The command prefix bits to prepend on each new transfer, if -// Mx_RFMT_PREFIX_LEN is nonzero. -#define QMI_M0_RCMD_PREFIX_RESET _u(0x03) -#define QMI_M0_RCMD_PREFIX_BITS _u(0x000000ff) -#define QMI_M0_RCMD_PREFIX_MSB _u(7) -#define QMI_M0_RCMD_PREFIX_LSB _u(0) -#define QMI_M0_RCMD_PREFIX_ACCESS "RW" -// ============================================================================= -// Register : QMI_M0_WFMT -// Description : Write transfer format configuration for memory address window -// 0. -// -// Configure the bus width of each transfer phase individually, -// and configure the length or presence of the command prefix, -// command suffix and dummy/turnaround transfer phases. Only -// 24-bit addresses are supported. -// -// The reset value of the M0_WFMT register is configured to -// support a basic 02h serial write transfer. However, writes to -// this window must first be enabled via the XIP_CTRL_WRITABLE_M0 -// bit, as XIP memory is read-only by default. -#define QMI_M0_WFMT_OFFSET _u(0x00000018) -#define QMI_M0_WFMT_BITS _u(0x1007d3ff) -#define QMI_M0_WFMT_RESET _u(0x00001000) -// ----------------------------------------------------------------------------- -// Field : QMI_M0_WFMT_DTR -// Description : Enable double transfer rate (DTR) for write commands: address, -// suffix and write data phases are active on both edges of SCK. -// SDO data is launched centre-aligned on each SCK edge, and SDI -// data is captured on the SCK edge that follows its launch. -// -// DTR is implemented by halving the clock rate; SCK has a period -// of 2 x CLK_DIV throughout the transfer. The prefix and dummy -// phases are still single transfer rate. -// -// If the suffix is quad-width, it must be 0 or 8 bits in length, -// to ensure an even number of SCK edges. -#define QMI_M0_WFMT_DTR_RESET _u(0x0) -#define QMI_M0_WFMT_DTR_BITS _u(0x10000000) -#define QMI_M0_WFMT_DTR_MSB _u(28) -#define QMI_M0_WFMT_DTR_LSB _u(28) -#define QMI_M0_WFMT_DTR_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : QMI_M0_WFMT_DUMMY_LEN -// Description : Length of dummy phase between command suffix and data phase, in -// units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 -// for single) -// 0x0 -> No dummy phase -// 0x1 -> 4 dummy bits -// 0x2 -> 8 dummy bits -// 0x3 -> 12 dummy bits -// 0x4 -> 16 dummy bits -// 0x5 -> 20 dummy bits -// 0x6 -> 24 dummy bits -// 0x7 -> 28 dummy bits -#define QMI_M0_WFMT_DUMMY_LEN_RESET _u(0x0) -#define QMI_M0_WFMT_DUMMY_LEN_BITS _u(0x00070000) -#define QMI_M0_WFMT_DUMMY_LEN_MSB _u(18) -#define QMI_M0_WFMT_DUMMY_LEN_LSB _u(16) -#define QMI_M0_WFMT_DUMMY_LEN_ACCESS "RW" -#define QMI_M0_WFMT_DUMMY_LEN_VALUE_NONE _u(0x0) -#define QMI_M0_WFMT_DUMMY_LEN_VALUE_4 _u(0x1) -#define QMI_M0_WFMT_DUMMY_LEN_VALUE_8 _u(0x2) -#define QMI_M0_WFMT_DUMMY_LEN_VALUE_12 _u(0x3) -#define QMI_M0_WFMT_DUMMY_LEN_VALUE_16 _u(0x4) -#define QMI_M0_WFMT_DUMMY_LEN_VALUE_20 _u(0x5) -#define QMI_M0_WFMT_DUMMY_LEN_VALUE_24 _u(0x6) -#define QMI_M0_WFMT_DUMMY_LEN_VALUE_28 _u(0x7) -// ----------------------------------------------------------------------------- -// Field : QMI_M0_WFMT_SUFFIX_LEN -// Description : Length of post-address command suffix, in units of 4 bits. -// (i.e. 1 cycle for quad width, 2 for dual, 4 for single) -// -// Only values of 0 and 8 bits are supported. -// 0x0 -> No suffix -// 0x2 -> 8-bit suffix -#define QMI_M0_WFMT_SUFFIX_LEN_RESET _u(0x0) -#define QMI_M0_WFMT_SUFFIX_LEN_BITS _u(0x0000c000) -#define QMI_M0_WFMT_SUFFIX_LEN_MSB _u(15) -#define QMI_M0_WFMT_SUFFIX_LEN_LSB _u(14) -#define QMI_M0_WFMT_SUFFIX_LEN_ACCESS "RW" -#define QMI_M0_WFMT_SUFFIX_LEN_VALUE_NONE _u(0x0) -#define QMI_M0_WFMT_SUFFIX_LEN_VALUE_8 _u(0x2) -// ----------------------------------------------------------------------------- -// Field : QMI_M0_WFMT_PREFIX_LEN -// Description : Length of command prefix, in units of 8 bits. (i.e. 2 cycles -// for quad width, 4 for dual, 8 for single) -// 0x0 -> No prefix -// 0x1 -> 8-bit prefix -#define QMI_M0_WFMT_PREFIX_LEN_RESET _u(0x1) -#define QMI_M0_WFMT_PREFIX_LEN_BITS _u(0x00001000) -#define QMI_M0_WFMT_PREFIX_LEN_MSB _u(12) -#define QMI_M0_WFMT_PREFIX_LEN_LSB _u(12) -#define QMI_M0_WFMT_PREFIX_LEN_ACCESS "RW" -#define QMI_M0_WFMT_PREFIX_LEN_VALUE_NONE _u(0x0) -#define QMI_M0_WFMT_PREFIX_LEN_VALUE_8 _u(0x1) -// ----------------------------------------------------------------------------- -// Field : QMI_M0_WFMT_DATA_WIDTH -// Description : The width used for the data transfer -// 0x0 -> Single width -// 0x1 -> Dual width -// 0x2 -> Quad width -#define QMI_M0_WFMT_DATA_WIDTH_RESET _u(0x0) -#define QMI_M0_WFMT_DATA_WIDTH_BITS _u(0x00000300) -#define QMI_M0_WFMT_DATA_WIDTH_MSB _u(9) -#define QMI_M0_WFMT_DATA_WIDTH_LSB _u(8) -#define QMI_M0_WFMT_DATA_WIDTH_ACCESS "RW" -#define QMI_M0_WFMT_DATA_WIDTH_VALUE_S _u(0x0) -#define QMI_M0_WFMT_DATA_WIDTH_VALUE_D _u(0x1) -#define QMI_M0_WFMT_DATA_WIDTH_VALUE_Q _u(0x2) -// ----------------------------------------------------------------------------- -// Field : QMI_M0_WFMT_DUMMY_WIDTH -// Description : The width used for the dummy phase, if any. -// -// If width is single, SD0/MOSI is held asserted low during the -// dummy phase, and SD1...SD3 are tristated. If width is -// dual/quad, all IOs are tristated during the dummy phase. -// 0x0 -> Single width -// 0x1 -> Dual width -// 0x2 -> Quad width -#define QMI_M0_WFMT_DUMMY_WIDTH_RESET _u(0x0) -#define QMI_M0_WFMT_DUMMY_WIDTH_BITS _u(0x000000c0) -#define QMI_M0_WFMT_DUMMY_WIDTH_MSB _u(7) -#define QMI_M0_WFMT_DUMMY_WIDTH_LSB _u(6) -#define QMI_M0_WFMT_DUMMY_WIDTH_ACCESS "RW" -#define QMI_M0_WFMT_DUMMY_WIDTH_VALUE_S _u(0x0) -#define QMI_M0_WFMT_DUMMY_WIDTH_VALUE_D _u(0x1) -#define QMI_M0_WFMT_DUMMY_WIDTH_VALUE_Q _u(0x2) -// ----------------------------------------------------------------------------- -// Field : QMI_M0_WFMT_SUFFIX_WIDTH -// Description : The width used for the post-address command suffix, if any -// 0x0 -> Single width -// 0x1 -> Dual width -// 0x2 -> Quad width -#define QMI_M0_WFMT_SUFFIX_WIDTH_RESET _u(0x0) -#define QMI_M0_WFMT_SUFFIX_WIDTH_BITS _u(0x00000030) -#define QMI_M0_WFMT_SUFFIX_WIDTH_MSB _u(5) -#define QMI_M0_WFMT_SUFFIX_WIDTH_LSB _u(4) -#define QMI_M0_WFMT_SUFFIX_WIDTH_ACCESS "RW" -#define QMI_M0_WFMT_SUFFIX_WIDTH_VALUE_S _u(0x0) -#define QMI_M0_WFMT_SUFFIX_WIDTH_VALUE_D _u(0x1) -#define QMI_M0_WFMT_SUFFIX_WIDTH_VALUE_Q _u(0x2) -// ----------------------------------------------------------------------------- -// Field : QMI_M0_WFMT_ADDR_WIDTH -// Description : The transfer width used for the address. The address phase -// always transfers 24 bits in total. -// 0x0 -> Single width -// 0x1 -> Dual width -// 0x2 -> Quad width -#define QMI_M0_WFMT_ADDR_WIDTH_RESET _u(0x0) -#define QMI_M0_WFMT_ADDR_WIDTH_BITS _u(0x0000000c) -#define QMI_M0_WFMT_ADDR_WIDTH_MSB _u(3) -#define QMI_M0_WFMT_ADDR_WIDTH_LSB _u(2) -#define QMI_M0_WFMT_ADDR_WIDTH_ACCESS "RW" -#define QMI_M0_WFMT_ADDR_WIDTH_VALUE_S _u(0x0) -#define QMI_M0_WFMT_ADDR_WIDTH_VALUE_D _u(0x1) -#define QMI_M0_WFMT_ADDR_WIDTH_VALUE_Q _u(0x2) -// ----------------------------------------------------------------------------- -// Field : QMI_M0_WFMT_PREFIX_WIDTH -// Description : The transfer width used for the command prefix, if any -// 0x0 -> Single width -// 0x1 -> Dual width -// 0x2 -> Quad width -#define QMI_M0_WFMT_PREFIX_WIDTH_RESET _u(0x0) -#define QMI_M0_WFMT_PREFIX_WIDTH_BITS _u(0x00000003) -#define QMI_M0_WFMT_PREFIX_WIDTH_MSB _u(1) -#define QMI_M0_WFMT_PREFIX_WIDTH_LSB _u(0) -#define QMI_M0_WFMT_PREFIX_WIDTH_ACCESS "RW" -#define QMI_M0_WFMT_PREFIX_WIDTH_VALUE_S _u(0x0) -#define QMI_M0_WFMT_PREFIX_WIDTH_VALUE_D _u(0x1) -#define QMI_M0_WFMT_PREFIX_WIDTH_VALUE_Q _u(0x2) -// ============================================================================= -// Register : QMI_M0_WCMD -// Description : Command constants used for writes to memory address window 0. -// -// The reset value of the M0_WCMD register is configured to -// support a basic 02h serial write transfer with no additional -// configuration. -#define QMI_M0_WCMD_OFFSET _u(0x0000001c) -#define QMI_M0_WCMD_BITS _u(0x0000ffff) -#define QMI_M0_WCMD_RESET _u(0x0000a002) -// ----------------------------------------------------------------------------- -// Field : QMI_M0_WCMD_SUFFIX -// Description : The command suffix bits following the address, if -// Mx_WFMT_SUFFIX_LEN is nonzero. -#define QMI_M0_WCMD_SUFFIX_RESET _u(0xa0) -#define QMI_M0_WCMD_SUFFIX_BITS _u(0x0000ff00) -#define QMI_M0_WCMD_SUFFIX_MSB _u(15) -#define QMI_M0_WCMD_SUFFIX_LSB _u(8) -#define QMI_M0_WCMD_SUFFIX_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : QMI_M0_WCMD_PREFIX -// Description : The command prefix bits to prepend on each new transfer, if -// Mx_WFMT_PREFIX_LEN is nonzero. -#define QMI_M0_WCMD_PREFIX_RESET _u(0x02) -#define QMI_M0_WCMD_PREFIX_BITS _u(0x000000ff) -#define QMI_M0_WCMD_PREFIX_MSB _u(7) -#define QMI_M0_WCMD_PREFIX_LSB _u(0) -#define QMI_M0_WCMD_PREFIX_ACCESS "RW" -// ============================================================================= -// Register : QMI_M1_TIMING -// Description : Timing configuration register for memory address window 1. -#define QMI_M1_TIMING_OFFSET _u(0x00000020) -#define QMI_M1_TIMING_BITS _u(0xf3fff7ff) -#define QMI_M1_TIMING_RESET _u(0x40000004) -// ----------------------------------------------------------------------------- -// Field : QMI_M1_TIMING_COOLDOWN -// Description : Chip select cooldown period. When a memory transfer finishes, -// the chip select remains asserted for 64 x COOLDOWN system clock -// cycles, plus half an SCK clock period (rounded up for odd SCK -// divisors). After this cooldown expires, the chip select is -// always deasserted to save power. -// -// If the next memory access arrives within the cooldown period, -// the QMI may be able to append more SCK cycles to the currently -// ongoing SPI transfer, rather than starting a new transfer. This -// reduces access latency and increases bus throughput. -// -// Specifically, the next access must be in the same direction -// (read/write), access the same memory window (chip select 0/1), -// and follow sequentially the address of the last transfer. If -// any of these are false, the new access will first deassert the -// chip select, then begin a new transfer. -// -// If COOLDOWN is 0, the address alignment configured by PAGEBREAK -// has been reached, or the total chip select assertion limit -// MAX_SELECT has been reached, the cooldown period is skipped, -// and the chip select will always be deasserted one half SCK -// period after the transfer finishes. -#define QMI_M1_TIMING_COOLDOWN_RESET _u(0x1) -#define QMI_M1_TIMING_COOLDOWN_BITS _u(0xc0000000) -#define QMI_M1_TIMING_COOLDOWN_MSB _u(31) -#define QMI_M1_TIMING_COOLDOWN_LSB _u(30) -#define QMI_M1_TIMING_COOLDOWN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : QMI_M1_TIMING_PAGEBREAK -// Description : When page break is enabled, chip select will automatically -// deassert when crossing certain power-of-2-aligned address -// boundaries. The next access will always begin a new read/write -// SPI burst, even if the address of the next access follows in -// sequence with the last access before the page boundary. -// -// Some flash and PSRAM devices forbid crossing page boundaries -// with a single read/write transfer, or restrict the operating -// frequency for transfers that do cross page a boundary. This -// option allows the QMI to safely support those devices. -// -// This field has no effect when COOLDOWN is disabled. -// 0x0 -> No page boundary is enforced -// 0x1 -> Break bursts crossing a 256-byte page boundary -// 0x2 -> Break bursts crossing a 1024-byte quad-page boundary -// 0x3 -> Break bursts crossing a 4096-byte sector boundary -#define QMI_M1_TIMING_PAGEBREAK_RESET _u(0x0) -#define QMI_M1_TIMING_PAGEBREAK_BITS _u(0x30000000) -#define QMI_M1_TIMING_PAGEBREAK_MSB _u(29) -#define QMI_M1_TIMING_PAGEBREAK_LSB _u(28) -#define QMI_M1_TIMING_PAGEBREAK_ACCESS "RW" -#define QMI_M1_TIMING_PAGEBREAK_VALUE_NONE _u(0x0) -#define QMI_M1_TIMING_PAGEBREAK_VALUE_256 _u(0x1) -#define QMI_M1_TIMING_PAGEBREAK_VALUE_1024 _u(0x2) -#define QMI_M1_TIMING_PAGEBREAK_VALUE_4096 _u(0x3) -// ----------------------------------------------------------------------------- -// Field : QMI_M1_TIMING_SELECT_SETUP -// Description : Add up to one additional system clock cycle of setup between -// chip select assertion and the first rising edge of SCK. -// -// The default setup time is one half SCK period, which is usually -// sufficient except for very high SCK frequencies with some flash -// devices. -#define QMI_M1_TIMING_SELECT_SETUP_RESET _u(0x0) -#define QMI_M1_TIMING_SELECT_SETUP_BITS _u(0x02000000) -#define QMI_M1_TIMING_SELECT_SETUP_MSB _u(25) -#define QMI_M1_TIMING_SELECT_SETUP_LSB _u(25) -#define QMI_M1_TIMING_SELECT_SETUP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : QMI_M1_TIMING_SELECT_HOLD -// Description : Add up to three additional system clock cycles of active hold -// between the last falling edge of SCK and the deassertion of -// this window's chip select. -// -// The default hold time is one system clock cycle. Note that -// flash datasheets usually give chip select active hold time from -// the last *rising* edge of SCK, and so even zero hold from the -// last falling edge would be safe. -// -// Note that this is a minimum hold time guaranteed by the QMI: -// the actual chip select active hold may be slightly longer for -// read transfers with low clock divisors and/or high sample -// delays. Specifically, if the point two cycles after the last RX -// data sample is later than the last SCK falling edge, then the -// hold time is measured from *this* point. -// -// Note also that, in case the final SCK pulse is masked to save -// energy (true for non-DTR reads when COOLDOWN is disabled or -// PAGE_BREAK is reached), all of QMI's timing logic behaves as -// though the clock pulse were still present. The SELECT_HOLD time -// is applied from the point where the last SCK falling edge would -// be if the clock pulse were not masked. -#define QMI_M1_TIMING_SELECT_HOLD_RESET _u(0x0) -#define QMI_M1_TIMING_SELECT_HOLD_BITS _u(0x01800000) -#define QMI_M1_TIMING_SELECT_HOLD_MSB _u(24) -#define QMI_M1_TIMING_SELECT_HOLD_LSB _u(23) -#define QMI_M1_TIMING_SELECT_HOLD_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : QMI_M1_TIMING_MAX_SELECT -// Description : Enforce a maximum assertion duration for this window's chip -// select, in units of 64 system clock cycles. If 0, the QMI is -// permitted to keep the chip select asserted indefinitely when -// servicing sequential memory accesses (see COOLDOWN). -// -// This feature is required to meet timing constraints of PSRAM -// devices, which specify a maximum chip select assertion so they -// can perform DRAM refresh cycles. See also MIN_DESELECT, which -// can enforce a minimum deselect time. -// -// If a memory access is in progress at the time MAX_SELECT is -// reached, the QMI will wait for the access to complete before -// deasserting the chip select. This additional time must be -// accounted for to calculate a safe MAX_SELECT value. In the -// worst case, this may be a fully-formed serial transfer, -// including command prefix and address, with a data payload as -// large as one cache line. -#define QMI_M1_TIMING_MAX_SELECT_RESET _u(0x00) -#define QMI_M1_TIMING_MAX_SELECT_BITS _u(0x007e0000) -#define QMI_M1_TIMING_MAX_SELECT_MSB _u(22) -#define QMI_M1_TIMING_MAX_SELECT_LSB _u(17) -#define QMI_M1_TIMING_MAX_SELECT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : QMI_M1_TIMING_MIN_DESELECT -// Description : After this window's chip select is deasserted, it remains -// deasserted for half an SCK cycle (rounded up to an integer -// number of system clock cycles), plus MIN_DESELECT additional -// system clock cycles, before the QMI reasserts either chip -// select pin. -// -// Nonzero values may be required for PSRAM devices which enforce -// a longer minimum CS deselect time, so that they can perform -// internal DRAM refresh cycles whilst deselected. -#define QMI_M1_TIMING_MIN_DESELECT_RESET _u(0x00) -#define QMI_M1_TIMING_MIN_DESELECT_BITS _u(0x0001f000) -#define QMI_M1_TIMING_MIN_DESELECT_MSB _u(16) -#define QMI_M1_TIMING_MIN_DESELECT_LSB _u(12) -#define QMI_M1_TIMING_MIN_DESELECT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : QMI_M1_TIMING_RXDELAY -// Description : Delay the read data sample timing, in units of one half of a -// system clock cycle. (Not necessarily half of an SCK cycle.) An -// RXDELAY of 0 means the sample is captured at the SDI input -// registers simultaneously with the rising edge of SCK launched -// from the SCK output register. -// -// At higher SCK frequencies, RXDELAY may need to be increased to -// account for the round trip delay of the pads, and the clock- -// to-Q delay of the QSPI memory device. -#define QMI_M1_TIMING_RXDELAY_RESET _u(0x0) -#define QMI_M1_TIMING_RXDELAY_BITS _u(0x00000700) -#define QMI_M1_TIMING_RXDELAY_MSB _u(10) -#define QMI_M1_TIMING_RXDELAY_LSB _u(8) -#define QMI_M1_TIMING_RXDELAY_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : QMI_M1_TIMING_CLKDIV -// Description : Clock divisor. Odd and even divisors are supported. Defines the -// SCK clock period in units of 1 system clock cycle. Divisors -// 1..255 are encoded directly, and a divisor of 256 is encoded -// with a value of CLKDIV=0. -// -// The clock divisor can be changed on-the-fly, even when the QMI -// is currently accessing memory in this address window. All other -// parameters must only be changed when the QMI is idle. -// -// If software is increasing CLKDIV in anticipation of an increase -// in the system clock frequency, a dummy access to either memory -// window (and appropriate processor barriers/fences) must be -// inserted after the Mx_TIMING write to ensure the SCK divisor -// change is in effect _before_ the system clock is changed. -#define QMI_M1_TIMING_CLKDIV_RESET _u(0x04) -#define QMI_M1_TIMING_CLKDIV_BITS _u(0x000000ff) -#define QMI_M1_TIMING_CLKDIV_MSB _u(7) -#define QMI_M1_TIMING_CLKDIV_LSB _u(0) -#define QMI_M1_TIMING_CLKDIV_ACCESS "RW" -// ============================================================================= -// Register : QMI_M1_RFMT -// Description : Read transfer format configuration for memory address window 1. -// -// Configure the bus width of each transfer phase individually, -// and configure the length or presence of the command prefix, -// command suffix and dummy/turnaround transfer phases. Only -// 24-bit addresses are supported. -// -// The reset value of the M1_RFMT register is configured to -// support a basic 03h serial read transfer with no additional -// configuration. -#define QMI_M1_RFMT_OFFSET _u(0x00000024) -#define QMI_M1_RFMT_BITS _u(0x1007d3ff) -#define QMI_M1_RFMT_RESET _u(0x00001000) -// ----------------------------------------------------------------------------- -// Field : QMI_M1_RFMT_DTR -// Description : Enable double transfer rate (DTR) for read commands: address, -// suffix and read data phases are active on both edges of SCK. -// SDO data is launched centre-aligned on each SCK edge, and SDI -// data is captured on the SCK edge that follows its launch. -// -// DTR is implemented by halving the clock rate; SCK has a period -// of 2 x CLK_DIV throughout the transfer. The prefix and dummy -// phases are still single transfer rate. -// -// If the suffix is quad-width, it must be 0 or 8 bits in length, -// to ensure an even number of SCK edges. -#define QMI_M1_RFMT_DTR_RESET _u(0x0) -#define QMI_M1_RFMT_DTR_BITS _u(0x10000000) -#define QMI_M1_RFMT_DTR_MSB _u(28) -#define QMI_M1_RFMT_DTR_LSB _u(28) -#define QMI_M1_RFMT_DTR_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : QMI_M1_RFMT_DUMMY_LEN -// Description : Length of dummy phase between command suffix and data phase, in -// units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 -// for single) -// 0x0 -> No dummy phase -// 0x1 -> 4 dummy bits -// 0x2 -> 8 dummy bits -// 0x3 -> 12 dummy bits -// 0x4 -> 16 dummy bits -// 0x5 -> 20 dummy bits -// 0x6 -> 24 dummy bits -// 0x7 -> 28 dummy bits -#define QMI_M1_RFMT_DUMMY_LEN_RESET _u(0x0) -#define QMI_M1_RFMT_DUMMY_LEN_BITS _u(0x00070000) -#define QMI_M1_RFMT_DUMMY_LEN_MSB _u(18) -#define QMI_M1_RFMT_DUMMY_LEN_LSB _u(16) -#define QMI_M1_RFMT_DUMMY_LEN_ACCESS "RW" -#define QMI_M1_RFMT_DUMMY_LEN_VALUE_NONE _u(0x0) -#define QMI_M1_RFMT_DUMMY_LEN_VALUE_4 _u(0x1) -#define QMI_M1_RFMT_DUMMY_LEN_VALUE_8 _u(0x2) -#define QMI_M1_RFMT_DUMMY_LEN_VALUE_12 _u(0x3) -#define QMI_M1_RFMT_DUMMY_LEN_VALUE_16 _u(0x4) -#define QMI_M1_RFMT_DUMMY_LEN_VALUE_20 _u(0x5) -#define QMI_M1_RFMT_DUMMY_LEN_VALUE_24 _u(0x6) -#define QMI_M1_RFMT_DUMMY_LEN_VALUE_28 _u(0x7) -// ----------------------------------------------------------------------------- -// Field : QMI_M1_RFMT_SUFFIX_LEN -// Description : Length of post-address command suffix, in units of 4 bits. -// (i.e. 1 cycle for quad width, 2 for dual, 4 for single) -// -// Only values of 0 and 8 bits are supported. -// 0x0 -> No suffix -// 0x2 -> 8-bit suffix -#define QMI_M1_RFMT_SUFFIX_LEN_RESET _u(0x0) -#define QMI_M1_RFMT_SUFFIX_LEN_BITS _u(0x0000c000) -#define QMI_M1_RFMT_SUFFIX_LEN_MSB _u(15) -#define QMI_M1_RFMT_SUFFIX_LEN_LSB _u(14) -#define QMI_M1_RFMT_SUFFIX_LEN_ACCESS "RW" -#define QMI_M1_RFMT_SUFFIX_LEN_VALUE_NONE _u(0x0) -#define QMI_M1_RFMT_SUFFIX_LEN_VALUE_8 _u(0x2) -// ----------------------------------------------------------------------------- -// Field : QMI_M1_RFMT_PREFIX_LEN -// Description : Length of command prefix, in units of 8 bits. (i.e. 2 cycles -// for quad width, 4 for dual, 8 for single) -// 0x0 -> No prefix -// 0x1 -> 8-bit prefix -#define QMI_M1_RFMT_PREFIX_LEN_RESET _u(0x1) -#define QMI_M1_RFMT_PREFIX_LEN_BITS _u(0x00001000) -#define QMI_M1_RFMT_PREFIX_LEN_MSB _u(12) -#define QMI_M1_RFMT_PREFIX_LEN_LSB _u(12) -#define QMI_M1_RFMT_PREFIX_LEN_ACCESS "RW" -#define QMI_M1_RFMT_PREFIX_LEN_VALUE_NONE _u(0x0) -#define QMI_M1_RFMT_PREFIX_LEN_VALUE_8 _u(0x1) -// ----------------------------------------------------------------------------- -// Field : QMI_M1_RFMT_DATA_WIDTH -// Description : The width used for the data transfer -// 0x0 -> Single width -// 0x1 -> Dual width -// 0x2 -> Quad width -#define QMI_M1_RFMT_DATA_WIDTH_RESET _u(0x0) -#define QMI_M1_RFMT_DATA_WIDTH_BITS _u(0x00000300) -#define QMI_M1_RFMT_DATA_WIDTH_MSB _u(9) -#define QMI_M1_RFMT_DATA_WIDTH_LSB _u(8) -#define QMI_M1_RFMT_DATA_WIDTH_ACCESS "RW" -#define QMI_M1_RFMT_DATA_WIDTH_VALUE_S _u(0x0) -#define QMI_M1_RFMT_DATA_WIDTH_VALUE_D _u(0x1) -#define QMI_M1_RFMT_DATA_WIDTH_VALUE_Q _u(0x2) -// ----------------------------------------------------------------------------- -// Field : QMI_M1_RFMT_DUMMY_WIDTH -// Description : The width used for the dummy phase, if any. -// -// If width is single, SD0/MOSI is held asserted low during the -// dummy phase, and SD1...SD3 are tristated. If width is -// dual/quad, all IOs are tristated during the dummy phase. -// 0x0 -> Single width -// 0x1 -> Dual width -// 0x2 -> Quad width -#define QMI_M1_RFMT_DUMMY_WIDTH_RESET _u(0x0) -#define QMI_M1_RFMT_DUMMY_WIDTH_BITS _u(0x000000c0) -#define QMI_M1_RFMT_DUMMY_WIDTH_MSB _u(7) -#define QMI_M1_RFMT_DUMMY_WIDTH_LSB _u(6) -#define QMI_M1_RFMT_DUMMY_WIDTH_ACCESS "RW" -#define QMI_M1_RFMT_DUMMY_WIDTH_VALUE_S _u(0x0) -#define QMI_M1_RFMT_DUMMY_WIDTH_VALUE_D _u(0x1) -#define QMI_M1_RFMT_DUMMY_WIDTH_VALUE_Q _u(0x2) -// ----------------------------------------------------------------------------- -// Field : QMI_M1_RFMT_SUFFIX_WIDTH -// Description : The width used for the post-address command suffix, if any -// 0x0 -> Single width -// 0x1 -> Dual width -// 0x2 -> Quad width -#define QMI_M1_RFMT_SUFFIX_WIDTH_RESET _u(0x0) -#define QMI_M1_RFMT_SUFFIX_WIDTH_BITS _u(0x00000030) -#define QMI_M1_RFMT_SUFFIX_WIDTH_MSB _u(5) -#define QMI_M1_RFMT_SUFFIX_WIDTH_LSB _u(4) -#define QMI_M1_RFMT_SUFFIX_WIDTH_ACCESS "RW" -#define QMI_M1_RFMT_SUFFIX_WIDTH_VALUE_S _u(0x0) -#define QMI_M1_RFMT_SUFFIX_WIDTH_VALUE_D _u(0x1) -#define QMI_M1_RFMT_SUFFIX_WIDTH_VALUE_Q _u(0x2) -// ----------------------------------------------------------------------------- -// Field : QMI_M1_RFMT_ADDR_WIDTH -// Description : The transfer width used for the address. The address phase -// always transfers 24 bits in total. -// 0x0 -> Single width -// 0x1 -> Dual width -// 0x2 -> Quad width -#define QMI_M1_RFMT_ADDR_WIDTH_RESET _u(0x0) -#define QMI_M1_RFMT_ADDR_WIDTH_BITS _u(0x0000000c) -#define QMI_M1_RFMT_ADDR_WIDTH_MSB _u(3) -#define QMI_M1_RFMT_ADDR_WIDTH_LSB _u(2) -#define QMI_M1_RFMT_ADDR_WIDTH_ACCESS "RW" -#define QMI_M1_RFMT_ADDR_WIDTH_VALUE_S _u(0x0) -#define QMI_M1_RFMT_ADDR_WIDTH_VALUE_D _u(0x1) -#define QMI_M1_RFMT_ADDR_WIDTH_VALUE_Q _u(0x2) -// ----------------------------------------------------------------------------- -// Field : QMI_M1_RFMT_PREFIX_WIDTH -// Description : The transfer width used for the command prefix, if any -// 0x0 -> Single width -// 0x1 -> Dual width -// 0x2 -> Quad width -#define QMI_M1_RFMT_PREFIX_WIDTH_RESET _u(0x0) -#define QMI_M1_RFMT_PREFIX_WIDTH_BITS _u(0x00000003) -#define QMI_M1_RFMT_PREFIX_WIDTH_MSB _u(1) -#define QMI_M1_RFMT_PREFIX_WIDTH_LSB _u(0) -#define QMI_M1_RFMT_PREFIX_WIDTH_ACCESS "RW" -#define QMI_M1_RFMT_PREFIX_WIDTH_VALUE_S _u(0x0) -#define QMI_M1_RFMT_PREFIX_WIDTH_VALUE_D _u(0x1) -#define QMI_M1_RFMT_PREFIX_WIDTH_VALUE_Q _u(0x2) -// ============================================================================= -// Register : QMI_M1_RCMD -// Description : Command constants used for reads from memory address window 1. -// -// The reset value of the M1_RCMD register is configured to -// support a basic 03h serial read transfer with no additional -// configuration. -#define QMI_M1_RCMD_OFFSET _u(0x00000028) -#define QMI_M1_RCMD_BITS _u(0x0000ffff) -#define QMI_M1_RCMD_RESET _u(0x0000a003) -// ----------------------------------------------------------------------------- -// Field : QMI_M1_RCMD_SUFFIX -// Description : The command suffix bits following the address, if -// Mx_RFMT_SUFFIX_LEN is nonzero. -#define QMI_M1_RCMD_SUFFIX_RESET _u(0xa0) -#define QMI_M1_RCMD_SUFFIX_BITS _u(0x0000ff00) -#define QMI_M1_RCMD_SUFFIX_MSB _u(15) -#define QMI_M1_RCMD_SUFFIX_LSB _u(8) -#define QMI_M1_RCMD_SUFFIX_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : QMI_M1_RCMD_PREFIX -// Description : The command prefix bits to prepend on each new transfer, if -// Mx_RFMT_PREFIX_LEN is nonzero. -#define QMI_M1_RCMD_PREFIX_RESET _u(0x03) -#define QMI_M1_RCMD_PREFIX_BITS _u(0x000000ff) -#define QMI_M1_RCMD_PREFIX_MSB _u(7) -#define QMI_M1_RCMD_PREFIX_LSB _u(0) -#define QMI_M1_RCMD_PREFIX_ACCESS "RW" -// ============================================================================= -// Register : QMI_M1_WFMT -// Description : Write transfer format configuration for memory address window -// 1. -// -// Configure the bus width of each transfer phase individually, -// and configure the length or presence of the command prefix, -// command suffix and dummy/turnaround transfer phases. Only -// 24-bit addresses are supported. -// -// The reset value of the M1_WFMT register is configured to -// support a basic 02h serial write transfer. However, writes to -// this window must first be enabled via the XIP_CTRL_WRITABLE_M1 -// bit, as XIP memory is read-only by default. -#define QMI_M1_WFMT_OFFSET _u(0x0000002c) -#define QMI_M1_WFMT_BITS _u(0x1007d3ff) -#define QMI_M1_WFMT_RESET _u(0x00001000) -// ----------------------------------------------------------------------------- -// Field : QMI_M1_WFMT_DTR -// Description : Enable double transfer rate (DTR) for write commands: address, -// suffix and write data phases are active on both edges of SCK. -// SDO data is launched centre-aligned on each SCK edge, and SDI -// data is captured on the SCK edge that follows its launch. -// -// DTR is implemented by halving the clock rate; SCK has a period -// of 2 x CLK_DIV throughout the transfer. The prefix and dummy -// phases are still single transfer rate. -// -// If the suffix is quad-width, it must be 0 or 8 bits in length, -// to ensure an even number of SCK edges. -#define QMI_M1_WFMT_DTR_RESET _u(0x0) -#define QMI_M1_WFMT_DTR_BITS _u(0x10000000) -#define QMI_M1_WFMT_DTR_MSB _u(28) -#define QMI_M1_WFMT_DTR_LSB _u(28) -#define QMI_M1_WFMT_DTR_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : QMI_M1_WFMT_DUMMY_LEN -// Description : Length of dummy phase between command suffix and data phase, in -// units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 -// for single) -// 0x0 -> No dummy phase -// 0x1 -> 4 dummy bits -// 0x2 -> 8 dummy bits -// 0x3 -> 12 dummy bits -// 0x4 -> 16 dummy bits -// 0x5 -> 20 dummy bits -// 0x6 -> 24 dummy bits -// 0x7 -> 28 dummy bits -#define QMI_M1_WFMT_DUMMY_LEN_RESET _u(0x0) -#define QMI_M1_WFMT_DUMMY_LEN_BITS _u(0x00070000) -#define QMI_M1_WFMT_DUMMY_LEN_MSB _u(18) -#define QMI_M1_WFMT_DUMMY_LEN_LSB _u(16) -#define QMI_M1_WFMT_DUMMY_LEN_ACCESS "RW" -#define QMI_M1_WFMT_DUMMY_LEN_VALUE_NONE _u(0x0) -#define QMI_M1_WFMT_DUMMY_LEN_VALUE_4 _u(0x1) -#define QMI_M1_WFMT_DUMMY_LEN_VALUE_8 _u(0x2) -#define QMI_M1_WFMT_DUMMY_LEN_VALUE_12 _u(0x3) -#define QMI_M1_WFMT_DUMMY_LEN_VALUE_16 _u(0x4) -#define QMI_M1_WFMT_DUMMY_LEN_VALUE_20 _u(0x5) -#define QMI_M1_WFMT_DUMMY_LEN_VALUE_24 _u(0x6) -#define QMI_M1_WFMT_DUMMY_LEN_VALUE_28 _u(0x7) -// ----------------------------------------------------------------------------- -// Field : QMI_M1_WFMT_SUFFIX_LEN -// Description : Length of post-address command suffix, in units of 4 bits. -// (i.e. 1 cycle for quad width, 2 for dual, 4 for single) -// -// Only values of 0 and 8 bits are supported. -// 0x0 -> No suffix -// 0x2 -> 8-bit suffix -#define QMI_M1_WFMT_SUFFIX_LEN_RESET _u(0x0) -#define QMI_M1_WFMT_SUFFIX_LEN_BITS _u(0x0000c000) -#define QMI_M1_WFMT_SUFFIX_LEN_MSB _u(15) -#define QMI_M1_WFMT_SUFFIX_LEN_LSB _u(14) -#define QMI_M1_WFMT_SUFFIX_LEN_ACCESS "RW" -#define QMI_M1_WFMT_SUFFIX_LEN_VALUE_NONE _u(0x0) -#define QMI_M1_WFMT_SUFFIX_LEN_VALUE_8 _u(0x2) -// ----------------------------------------------------------------------------- -// Field : QMI_M1_WFMT_PREFIX_LEN -// Description : Length of command prefix, in units of 8 bits. (i.e. 2 cycles -// for quad width, 4 for dual, 8 for single) -// 0x0 -> No prefix -// 0x1 -> 8-bit prefix -#define QMI_M1_WFMT_PREFIX_LEN_RESET _u(0x1) -#define QMI_M1_WFMT_PREFIX_LEN_BITS _u(0x00001000) -#define QMI_M1_WFMT_PREFIX_LEN_MSB _u(12) -#define QMI_M1_WFMT_PREFIX_LEN_LSB _u(12) -#define QMI_M1_WFMT_PREFIX_LEN_ACCESS "RW" -#define QMI_M1_WFMT_PREFIX_LEN_VALUE_NONE _u(0x0) -#define QMI_M1_WFMT_PREFIX_LEN_VALUE_8 _u(0x1) -// ----------------------------------------------------------------------------- -// Field : QMI_M1_WFMT_DATA_WIDTH -// Description : The width used for the data transfer -// 0x0 -> Single width -// 0x1 -> Dual width -// 0x2 -> Quad width -#define QMI_M1_WFMT_DATA_WIDTH_RESET _u(0x0) -#define QMI_M1_WFMT_DATA_WIDTH_BITS _u(0x00000300) -#define QMI_M1_WFMT_DATA_WIDTH_MSB _u(9) -#define QMI_M1_WFMT_DATA_WIDTH_LSB _u(8) -#define QMI_M1_WFMT_DATA_WIDTH_ACCESS "RW" -#define QMI_M1_WFMT_DATA_WIDTH_VALUE_S _u(0x0) -#define QMI_M1_WFMT_DATA_WIDTH_VALUE_D _u(0x1) -#define QMI_M1_WFMT_DATA_WIDTH_VALUE_Q _u(0x2) -// ----------------------------------------------------------------------------- -// Field : QMI_M1_WFMT_DUMMY_WIDTH -// Description : The width used for the dummy phase, if any. -// -// If width is single, SD0/MOSI is held asserted low during the -// dummy phase, and SD1...SD3 are tristated. If width is -// dual/quad, all IOs are tristated during the dummy phase. -// 0x0 -> Single width -// 0x1 -> Dual width -// 0x2 -> Quad width -#define QMI_M1_WFMT_DUMMY_WIDTH_RESET _u(0x0) -#define QMI_M1_WFMT_DUMMY_WIDTH_BITS _u(0x000000c0) -#define QMI_M1_WFMT_DUMMY_WIDTH_MSB _u(7) -#define QMI_M1_WFMT_DUMMY_WIDTH_LSB _u(6) -#define QMI_M1_WFMT_DUMMY_WIDTH_ACCESS "RW" -#define QMI_M1_WFMT_DUMMY_WIDTH_VALUE_S _u(0x0) -#define QMI_M1_WFMT_DUMMY_WIDTH_VALUE_D _u(0x1) -#define QMI_M1_WFMT_DUMMY_WIDTH_VALUE_Q _u(0x2) -// ----------------------------------------------------------------------------- -// Field : QMI_M1_WFMT_SUFFIX_WIDTH -// Description : The width used for the post-address command suffix, if any -// 0x0 -> Single width -// 0x1 -> Dual width -// 0x2 -> Quad width -#define QMI_M1_WFMT_SUFFIX_WIDTH_RESET _u(0x0) -#define QMI_M1_WFMT_SUFFIX_WIDTH_BITS _u(0x00000030) -#define QMI_M1_WFMT_SUFFIX_WIDTH_MSB _u(5) -#define QMI_M1_WFMT_SUFFIX_WIDTH_LSB _u(4) -#define QMI_M1_WFMT_SUFFIX_WIDTH_ACCESS "RW" -#define QMI_M1_WFMT_SUFFIX_WIDTH_VALUE_S _u(0x0) -#define QMI_M1_WFMT_SUFFIX_WIDTH_VALUE_D _u(0x1) -#define QMI_M1_WFMT_SUFFIX_WIDTH_VALUE_Q _u(0x2) -// ----------------------------------------------------------------------------- -// Field : QMI_M1_WFMT_ADDR_WIDTH -// Description : The transfer width used for the address. The address phase -// always transfers 24 bits in total. -// 0x0 -> Single width -// 0x1 -> Dual width -// 0x2 -> Quad width -#define QMI_M1_WFMT_ADDR_WIDTH_RESET _u(0x0) -#define QMI_M1_WFMT_ADDR_WIDTH_BITS _u(0x0000000c) -#define QMI_M1_WFMT_ADDR_WIDTH_MSB _u(3) -#define QMI_M1_WFMT_ADDR_WIDTH_LSB _u(2) -#define QMI_M1_WFMT_ADDR_WIDTH_ACCESS "RW" -#define QMI_M1_WFMT_ADDR_WIDTH_VALUE_S _u(0x0) -#define QMI_M1_WFMT_ADDR_WIDTH_VALUE_D _u(0x1) -#define QMI_M1_WFMT_ADDR_WIDTH_VALUE_Q _u(0x2) -// ----------------------------------------------------------------------------- -// Field : QMI_M1_WFMT_PREFIX_WIDTH -// Description : The transfer width used for the command prefix, if any -// 0x0 -> Single width -// 0x1 -> Dual width -// 0x2 -> Quad width -#define QMI_M1_WFMT_PREFIX_WIDTH_RESET _u(0x0) -#define QMI_M1_WFMT_PREFIX_WIDTH_BITS _u(0x00000003) -#define QMI_M1_WFMT_PREFIX_WIDTH_MSB _u(1) -#define QMI_M1_WFMT_PREFIX_WIDTH_LSB _u(0) -#define QMI_M1_WFMT_PREFIX_WIDTH_ACCESS "RW" -#define QMI_M1_WFMT_PREFIX_WIDTH_VALUE_S _u(0x0) -#define QMI_M1_WFMT_PREFIX_WIDTH_VALUE_D _u(0x1) -#define QMI_M1_WFMT_PREFIX_WIDTH_VALUE_Q _u(0x2) -// ============================================================================= -// Register : QMI_M1_WCMD -// Description : Command constants used for writes to memory address window 1. -// -// The reset value of the M1_WCMD register is configured to -// support a basic 02h serial write transfer with no additional -// configuration. -#define QMI_M1_WCMD_OFFSET _u(0x00000030) -#define QMI_M1_WCMD_BITS _u(0x0000ffff) -#define QMI_M1_WCMD_RESET _u(0x0000a002) -// ----------------------------------------------------------------------------- -// Field : QMI_M1_WCMD_SUFFIX -// Description : The command suffix bits following the address, if -// Mx_WFMT_SUFFIX_LEN is nonzero. -#define QMI_M1_WCMD_SUFFIX_RESET _u(0xa0) -#define QMI_M1_WCMD_SUFFIX_BITS _u(0x0000ff00) -#define QMI_M1_WCMD_SUFFIX_MSB _u(15) -#define QMI_M1_WCMD_SUFFIX_LSB _u(8) -#define QMI_M1_WCMD_SUFFIX_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : QMI_M1_WCMD_PREFIX -// Description : The command prefix bits to prepend on each new transfer, if -// Mx_WFMT_PREFIX_LEN is nonzero. -#define QMI_M1_WCMD_PREFIX_RESET _u(0x02) -#define QMI_M1_WCMD_PREFIX_BITS _u(0x000000ff) -#define QMI_M1_WCMD_PREFIX_MSB _u(7) -#define QMI_M1_WCMD_PREFIX_LSB _u(0) -#define QMI_M1_WCMD_PREFIX_ACCESS "RW" -// ============================================================================= -// Register : QMI_ATRANS0 -// Description : Configure address translation for XIP virtual addresses -// 0x000000 through 0x3fffff (a 4 MiB window starting at +0 MiB). -// -// Address translation allows a program image to be executed in -// place at multiple physical flash addresses (for example, a -// double-buffered flash image for over-the-air updates), without -// the overhead of position-independent code. -// -// At reset, the address translation registers are initialised to -// an identity mapping, so that they can be ignored if address -// translation is not required. -// -// Note that the XIP cache is fully virtually addressed, so a -// cache flush is required after changing the address translation. -#define QMI_ATRANS0_OFFSET _u(0x00000034) -#define QMI_ATRANS0_BITS _u(0x07ff0fff) -#define QMI_ATRANS0_RESET _u(0x04000000) -// ----------------------------------------------------------------------------- -// Field : QMI_ATRANS0_SIZE -// Description : Translation aperture size for this virtual address range, in -// units of 4 kiB (one flash sector). -// -// Bits 21:12 of the virtual address are compared to SIZE. Offsets -// greater than SIZE return a bus error, and do not cause a QSPI -// access. -#define QMI_ATRANS0_SIZE_RESET _u(0x400) -#define QMI_ATRANS0_SIZE_BITS _u(0x07ff0000) -#define QMI_ATRANS0_SIZE_MSB _u(26) -#define QMI_ATRANS0_SIZE_LSB _u(16) -#define QMI_ATRANS0_SIZE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : QMI_ATRANS0_BASE -// Description : Physical address base for this virtual address range, in units -// of 4 kiB (one flash sector). -// -// Taking a 24-bit virtual address, firstly bits 23:22 (the two -// MSBs) are masked to zero, and then BASE is added to bits 23:12 -// (the upper 12 bits) to form the physical address. Translation -// wraps on a 16 MiB boundary. -#define QMI_ATRANS0_BASE_RESET _u(0x000) -#define QMI_ATRANS0_BASE_BITS _u(0x00000fff) -#define QMI_ATRANS0_BASE_MSB _u(11) -#define QMI_ATRANS0_BASE_LSB _u(0) -#define QMI_ATRANS0_BASE_ACCESS "RW" -// ============================================================================= -// Register : QMI_ATRANS1 -// Description : Configure address translation for XIP virtual addresses -// 0x400000 through 0x7fffff (a 4 MiB window starting at +4 MiB). -// -// Address translation allows a program image to be executed in -// place at multiple physical flash addresses (for example, a -// double-buffered flash image for over-the-air updates), without -// the overhead of position-independent code. -// -// At reset, the address translation registers are initialised to -// an identity mapping, so that they can be ignored if address -// translation is not required. -// -// Note that the XIP cache is fully virtually addressed, so a -// cache flush is required after changing the address translation. -#define QMI_ATRANS1_OFFSET _u(0x00000038) -#define QMI_ATRANS1_BITS _u(0x07ff0fff) -#define QMI_ATRANS1_RESET _u(0x04000400) -// ----------------------------------------------------------------------------- -// Field : QMI_ATRANS1_SIZE -// Description : Translation aperture size for this virtual address range, in -// units of 4 kiB (one flash sector). -// -// Bits 21:12 of the virtual address are compared to SIZE. Offsets -// greater than SIZE return a bus error, and do not cause a QSPI -// access. -#define QMI_ATRANS1_SIZE_RESET _u(0x400) -#define QMI_ATRANS1_SIZE_BITS _u(0x07ff0000) -#define QMI_ATRANS1_SIZE_MSB _u(26) -#define QMI_ATRANS1_SIZE_LSB _u(16) -#define QMI_ATRANS1_SIZE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : QMI_ATRANS1_BASE -// Description : Physical address base for this virtual address range, in units -// of 4 kiB (one flash sector). -// -// Taking a 24-bit virtual address, firstly bits 23:22 (the two -// MSBs) are masked to zero, and then BASE is added to bits 23:12 -// (the upper 12 bits) to form the physical address. Translation -// wraps on a 16 MiB boundary. -#define QMI_ATRANS1_BASE_RESET _u(0x400) -#define QMI_ATRANS1_BASE_BITS _u(0x00000fff) -#define QMI_ATRANS1_BASE_MSB _u(11) -#define QMI_ATRANS1_BASE_LSB _u(0) -#define QMI_ATRANS1_BASE_ACCESS "RW" -// ============================================================================= -// Register : QMI_ATRANS2 -// Description : Configure address translation for XIP virtual addresses -// 0x800000 through 0xbfffff (a 4 MiB window starting at +8 MiB). -// -// Address translation allows a program image to be executed in -// place at multiple physical flash addresses (for example, a -// double-buffered flash image for over-the-air updates), without -// the overhead of position-independent code. -// -// At reset, the address translation registers are initialised to -// an identity mapping, so that they can be ignored if address -// translation is not required. -// -// Note that the XIP cache is fully virtually addressed, so a -// cache flush is required after changing the address translation. -#define QMI_ATRANS2_OFFSET _u(0x0000003c) -#define QMI_ATRANS2_BITS _u(0x07ff0fff) -#define QMI_ATRANS2_RESET _u(0x04000800) -// ----------------------------------------------------------------------------- -// Field : QMI_ATRANS2_SIZE -// Description : Translation aperture size for this virtual address range, in -// units of 4 kiB (one flash sector). -// -// Bits 21:12 of the virtual address are compared to SIZE. Offsets -// greater than SIZE return a bus error, and do not cause a QSPI -// access. -#define QMI_ATRANS2_SIZE_RESET _u(0x400) -#define QMI_ATRANS2_SIZE_BITS _u(0x07ff0000) -#define QMI_ATRANS2_SIZE_MSB _u(26) -#define QMI_ATRANS2_SIZE_LSB _u(16) -#define QMI_ATRANS2_SIZE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : QMI_ATRANS2_BASE -// Description : Physical address base for this virtual address range, in units -// of 4 kiB (one flash sector). -// -// Taking a 24-bit virtual address, firstly bits 23:22 (the two -// MSBs) are masked to zero, and then BASE is added to bits 23:12 -// (the upper 12 bits) to form the physical address. Translation -// wraps on a 16 MiB boundary. -#define QMI_ATRANS2_BASE_RESET _u(0x800) -#define QMI_ATRANS2_BASE_BITS _u(0x00000fff) -#define QMI_ATRANS2_BASE_MSB _u(11) -#define QMI_ATRANS2_BASE_LSB _u(0) -#define QMI_ATRANS2_BASE_ACCESS "RW" -// ============================================================================= -// Register : QMI_ATRANS3 -// Description : Configure address translation for XIP virtual addresses -// 0xc00000 through 0xffffff (a 4 MiB window starting at +12 MiB). -// -// Address translation allows a program image to be executed in -// place at multiple physical flash addresses (for example, a -// double-buffered flash image for over-the-air updates), without -// the overhead of position-independent code. -// -// At reset, the address translation registers are initialised to -// an identity mapping, so that they can be ignored if address -// translation is not required. -// -// Note that the XIP cache is fully virtually addressed, so a -// cache flush is required after changing the address translation. -#define QMI_ATRANS3_OFFSET _u(0x00000040) -#define QMI_ATRANS3_BITS _u(0x07ff0fff) -#define QMI_ATRANS3_RESET _u(0x04000c00) -// ----------------------------------------------------------------------------- -// Field : QMI_ATRANS3_SIZE -// Description : Translation aperture size for this virtual address range, in -// units of 4 kiB (one flash sector). -// -// Bits 21:12 of the virtual address are compared to SIZE. Offsets -// greater than SIZE return a bus error, and do not cause a QSPI -// access. -#define QMI_ATRANS3_SIZE_RESET _u(0x400) -#define QMI_ATRANS3_SIZE_BITS _u(0x07ff0000) -#define QMI_ATRANS3_SIZE_MSB _u(26) -#define QMI_ATRANS3_SIZE_LSB _u(16) -#define QMI_ATRANS3_SIZE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : QMI_ATRANS3_BASE -// Description : Physical address base for this virtual address range, in units -// of 4 kiB (one flash sector). -// -// Taking a 24-bit virtual address, firstly bits 23:22 (the two -// MSBs) are masked to zero, and then BASE is added to bits 23:12 -// (the upper 12 bits) to form the physical address. Translation -// wraps on a 16 MiB boundary. -#define QMI_ATRANS3_BASE_RESET _u(0xc00) -#define QMI_ATRANS3_BASE_BITS _u(0x00000fff) -#define QMI_ATRANS3_BASE_MSB _u(11) -#define QMI_ATRANS3_BASE_LSB _u(0) -#define QMI_ATRANS3_BASE_ACCESS "RW" -// ============================================================================= -// Register : QMI_ATRANS4 -// Description : Configure address translation for XIP virtual addresses -// 0x1000000 through 0x13fffff (a 4 MiB window starting at +16 -// MiB). -// -// Address translation allows a program image to be executed in -// place at multiple physical flash addresses (for example, a -// double-buffered flash image for over-the-air updates), without -// the overhead of position-independent code. -// -// At reset, the address translation registers are initialised to -// an identity mapping, so that they can be ignored if address -// translation is not required. -// -// Note that the XIP cache is fully virtually addressed, so a -// cache flush is required after changing the address translation. -#define QMI_ATRANS4_OFFSET _u(0x00000044) -#define QMI_ATRANS4_BITS _u(0x07ff0fff) -#define QMI_ATRANS4_RESET _u(0x04000000) -// ----------------------------------------------------------------------------- -// Field : QMI_ATRANS4_SIZE -// Description : Translation aperture size for this virtual address range, in -// units of 4 kiB (one flash sector). -// -// Bits 21:12 of the virtual address are compared to SIZE. Offsets -// greater than SIZE return a bus error, and do not cause a QSPI -// access. -#define QMI_ATRANS4_SIZE_RESET _u(0x400) -#define QMI_ATRANS4_SIZE_BITS _u(0x07ff0000) -#define QMI_ATRANS4_SIZE_MSB _u(26) -#define QMI_ATRANS4_SIZE_LSB _u(16) -#define QMI_ATRANS4_SIZE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : QMI_ATRANS4_BASE -// Description : Physical address base for this virtual address range, in units -// of 4 kiB (one flash sector). -// -// Taking a 24-bit virtual address, firstly bits 23:22 (the two -// MSBs) are masked to zero, and then BASE is added to bits 23:12 -// (the upper 12 bits) to form the physical address. Translation -// wraps on a 16 MiB boundary. -#define QMI_ATRANS4_BASE_RESET _u(0x000) -#define QMI_ATRANS4_BASE_BITS _u(0x00000fff) -#define QMI_ATRANS4_BASE_MSB _u(11) -#define QMI_ATRANS4_BASE_LSB _u(0) -#define QMI_ATRANS4_BASE_ACCESS "RW" -// ============================================================================= -// Register : QMI_ATRANS5 -// Description : Configure address translation for XIP virtual addresses -// 0x1400000 through 0x17fffff (a 4 MiB window starting at +20 -// MiB). -// -// Address translation allows a program image to be executed in -// place at multiple physical flash addresses (for example, a -// double-buffered flash image for over-the-air updates), without -// the overhead of position-independent code. -// -// At reset, the address translation registers are initialised to -// an identity mapping, so that they can be ignored if address -// translation is not required. -// -// Note that the XIP cache is fully virtually addressed, so a -// cache flush is required after changing the address translation. -#define QMI_ATRANS5_OFFSET _u(0x00000048) -#define QMI_ATRANS5_BITS _u(0x07ff0fff) -#define QMI_ATRANS5_RESET _u(0x04000400) -// ----------------------------------------------------------------------------- -// Field : QMI_ATRANS5_SIZE -// Description : Translation aperture size for this virtual address range, in -// units of 4 kiB (one flash sector). -// -// Bits 21:12 of the virtual address are compared to SIZE. Offsets -// greater than SIZE return a bus error, and do not cause a QSPI -// access. -#define QMI_ATRANS5_SIZE_RESET _u(0x400) -#define QMI_ATRANS5_SIZE_BITS _u(0x07ff0000) -#define QMI_ATRANS5_SIZE_MSB _u(26) -#define QMI_ATRANS5_SIZE_LSB _u(16) -#define QMI_ATRANS5_SIZE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : QMI_ATRANS5_BASE -// Description : Physical address base for this virtual address range, in units -// of 4 kiB (one flash sector). -// -// Taking a 24-bit virtual address, firstly bits 23:22 (the two -// MSBs) are masked to zero, and then BASE is added to bits 23:12 -// (the upper 12 bits) to form the physical address. Translation -// wraps on a 16 MiB boundary. -#define QMI_ATRANS5_BASE_RESET _u(0x400) -#define QMI_ATRANS5_BASE_BITS _u(0x00000fff) -#define QMI_ATRANS5_BASE_MSB _u(11) -#define QMI_ATRANS5_BASE_LSB _u(0) -#define QMI_ATRANS5_BASE_ACCESS "RW" -// ============================================================================= -// Register : QMI_ATRANS6 -// Description : Configure address translation for XIP virtual addresses -// 0x1800000 through 0x1bfffff (a 4 MiB window starting at +24 -// MiB). -// -// Address translation allows a program image to be executed in -// place at multiple physical flash addresses (for example, a -// double-buffered flash image for over-the-air updates), without -// the overhead of position-independent code. -// -// At reset, the address translation registers are initialised to -// an identity mapping, so that they can be ignored if address -// translation is not required. -// -// Note that the XIP cache is fully virtually addressed, so a -// cache flush is required after changing the address translation. -#define QMI_ATRANS6_OFFSET _u(0x0000004c) -#define QMI_ATRANS6_BITS _u(0x07ff0fff) -#define QMI_ATRANS6_RESET _u(0x04000800) -// ----------------------------------------------------------------------------- -// Field : QMI_ATRANS6_SIZE -// Description : Translation aperture size for this virtual address range, in -// units of 4 kiB (one flash sector). -// -// Bits 21:12 of the virtual address are compared to SIZE. Offsets -// greater than SIZE return a bus error, and do not cause a QSPI -// access. -#define QMI_ATRANS6_SIZE_RESET _u(0x400) -#define QMI_ATRANS6_SIZE_BITS _u(0x07ff0000) -#define QMI_ATRANS6_SIZE_MSB _u(26) -#define QMI_ATRANS6_SIZE_LSB _u(16) -#define QMI_ATRANS6_SIZE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : QMI_ATRANS6_BASE -// Description : Physical address base for this virtual address range, in units -// of 4 kiB (one flash sector). -// -// Taking a 24-bit virtual address, firstly bits 23:22 (the two -// MSBs) are masked to zero, and then BASE is added to bits 23:12 -// (the upper 12 bits) to form the physical address. Translation -// wraps on a 16 MiB boundary. -#define QMI_ATRANS6_BASE_RESET _u(0x800) -#define QMI_ATRANS6_BASE_BITS _u(0x00000fff) -#define QMI_ATRANS6_BASE_MSB _u(11) -#define QMI_ATRANS6_BASE_LSB _u(0) -#define QMI_ATRANS6_BASE_ACCESS "RW" -// ============================================================================= -// Register : QMI_ATRANS7 -// Description : Configure address translation for XIP virtual addresses -// 0x1c00000 through 0x1ffffff (a 4 MiB window starting at +28 -// MiB). -// -// Address translation allows a program image to be executed in -// place at multiple physical flash addresses (for example, a -// double-buffered flash image for over-the-air updates), without -// the overhead of position-independent code. -// -// At reset, the address translation registers are initialised to -// an identity mapping, so that they can be ignored if address -// translation is not required. -// -// Note that the XIP cache is fully virtually addressed, so a -// cache flush is required after changing the address translation. -#define QMI_ATRANS7_OFFSET _u(0x00000050) -#define QMI_ATRANS7_BITS _u(0x07ff0fff) -#define QMI_ATRANS7_RESET _u(0x04000c00) -// ----------------------------------------------------------------------------- -// Field : QMI_ATRANS7_SIZE -// Description : Translation aperture size for this virtual address range, in -// units of 4 kiB (one flash sector). -// -// Bits 21:12 of the virtual address are compared to SIZE. Offsets -// greater than SIZE return a bus error, and do not cause a QSPI -// access. -#define QMI_ATRANS7_SIZE_RESET _u(0x400) -#define QMI_ATRANS7_SIZE_BITS _u(0x07ff0000) -#define QMI_ATRANS7_SIZE_MSB _u(26) -#define QMI_ATRANS7_SIZE_LSB _u(16) -#define QMI_ATRANS7_SIZE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : QMI_ATRANS7_BASE -// Description : Physical address base for this virtual address range, in units -// of 4 kiB (one flash sector). -// -// Taking a 24-bit virtual address, firstly bits 23:22 (the two -// MSBs) are masked to zero, and then BASE is added to bits 23:12 -// (the upper 12 bits) to form the physical address. Translation -// wraps on a 16 MiB boundary. -#define QMI_ATRANS7_BASE_RESET _u(0xc00) -#define QMI_ATRANS7_BASE_BITS _u(0x00000fff) -#define QMI_ATRANS7_BASE_MSB _u(11) -#define QMI_ATRANS7_BASE_LSB _u(0) -#define QMI_ATRANS7_BASE_ACCESS "RW" -// ============================================================================= -#endif // _HARDWARE_REGS_QMI_H - diff --git a/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/resets.h b/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/resets.h deleted file mode 100644 index 459f24e9ea..0000000000 --- a/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/resets.h +++ /dev/null @@ -1,641 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -// ============================================================================= -// Register block : RESETS -// Version : 1 -// Bus type : apb -// ============================================================================= -#ifndef _HARDWARE_REGS_RESETS_H -#define _HARDWARE_REGS_RESETS_H -// ============================================================================= -// Register : RESETS_RESET -#define RESETS_RESET_OFFSET _u(0x00000000) -#define RESETS_RESET_BITS _u(0x1fffffff) -#define RESETS_RESET_RESET _u(0x1fffffff) -// ----------------------------------------------------------------------------- -// Field : RESETS_RESET_USBCTRL -#define RESETS_RESET_USBCTRL_RESET _u(0x1) -#define RESETS_RESET_USBCTRL_BITS _u(0x10000000) -#define RESETS_RESET_USBCTRL_MSB _u(28) -#define RESETS_RESET_USBCTRL_LSB _u(28) -#define RESETS_RESET_USBCTRL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RESETS_RESET_UART1 -#define RESETS_RESET_UART1_RESET _u(0x1) -#define RESETS_RESET_UART1_BITS _u(0x08000000) -#define RESETS_RESET_UART1_MSB _u(27) -#define RESETS_RESET_UART1_LSB _u(27) -#define RESETS_RESET_UART1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RESETS_RESET_UART0 -#define RESETS_RESET_UART0_RESET _u(0x1) -#define RESETS_RESET_UART0_BITS _u(0x04000000) -#define RESETS_RESET_UART0_MSB _u(26) -#define RESETS_RESET_UART0_LSB _u(26) -#define RESETS_RESET_UART0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RESETS_RESET_TRNG -#define RESETS_RESET_TRNG_RESET _u(0x1) -#define RESETS_RESET_TRNG_BITS _u(0x02000000) -#define RESETS_RESET_TRNG_MSB _u(25) -#define RESETS_RESET_TRNG_LSB _u(25) -#define RESETS_RESET_TRNG_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RESETS_RESET_TIMER1 -#define RESETS_RESET_TIMER1_RESET _u(0x1) -#define RESETS_RESET_TIMER1_BITS _u(0x01000000) -#define RESETS_RESET_TIMER1_MSB _u(24) -#define RESETS_RESET_TIMER1_LSB _u(24) -#define RESETS_RESET_TIMER1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RESETS_RESET_TIMER0 -#define RESETS_RESET_TIMER0_RESET _u(0x1) -#define RESETS_RESET_TIMER0_BITS _u(0x00800000) -#define RESETS_RESET_TIMER0_MSB _u(23) -#define RESETS_RESET_TIMER0_LSB _u(23) -#define RESETS_RESET_TIMER0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RESETS_RESET_TBMAN -#define RESETS_RESET_TBMAN_RESET _u(0x1) -#define RESETS_RESET_TBMAN_BITS _u(0x00400000) -#define RESETS_RESET_TBMAN_MSB _u(22) -#define RESETS_RESET_TBMAN_LSB _u(22) -#define RESETS_RESET_TBMAN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RESETS_RESET_SYSINFO -#define RESETS_RESET_SYSINFO_RESET _u(0x1) -#define RESETS_RESET_SYSINFO_BITS _u(0x00200000) -#define RESETS_RESET_SYSINFO_MSB _u(21) -#define RESETS_RESET_SYSINFO_LSB _u(21) -#define RESETS_RESET_SYSINFO_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RESETS_RESET_SYSCFG -#define RESETS_RESET_SYSCFG_RESET _u(0x1) -#define RESETS_RESET_SYSCFG_BITS _u(0x00100000) -#define RESETS_RESET_SYSCFG_MSB _u(20) -#define RESETS_RESET_SYSCFG_LSB _u(20) -#define RESETS_RESET_SYSCFG_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RESETS_RESET_SPI1 -#define RESETS_RESET_SPI1_RESET _u(0x1) -#define RESETS_RESET_SPI1_BITS _u(0x00080000) -#define RESETS_RESET_SPI1_MSB _u(19) -#define RESETS_RESET_SPI1_LSB _u(19) -#define RESETS_RESET_SPI1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RESETS_RESET_SPI0 -#define RESETS_RESET_SPI0_RESET _u(0x1) -#define RESETS_RESET_SPI0_BITS _u(0x00040000) -#define RESETS_RESET_SPI0_MSB _u(18) -#define RESETS_RESET_SPI0_LSB _u(18) -#define RESETS_RESET_SPI0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RESETS_RESET_SHA256 -#define RESETS_RESET_SHA256_RESET _u(0x1) -#define RESETS_RESET_SHA256_BITS _u(0x00020000) -#define RESETS_RESET_SHA256_MSB _u(17) -#define RESETS_RESET_SHA256_LSB _u(17) -#define RESETS_RESET_SHA256_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RESETS_RESET_PWM -#define RESETS_RESET_PWM_RESET _u(0x1) -#define RESETS_RESET_PWM_BITS _u(0x00010000) -#define RESETS_RESET_PWM_MSB _u(16) -#define RESETS_RESET_PWM_LSB _u(16) -#define RESETS_RESET_PWM_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RESETS_RESET_PLL_USB -#define RESETS_RESET_PLL_USB_RESET _u(0x1) -#define RESETS_RESET_PLL_USB_BITS _u(0x00008000) -#define RESETS_RESET_PLL_USB_MSB _u(15) -#define RESETS_RESET_PLL_USB_LSB _u(15) -#define RESETS_RESET_PLL_USB_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RESETS_RESET_PLL_SYS -#define RESETS_RESET_PLL_SYS_RESET _u(0x1) -#define RESETS_RESET_PLL_SYS_BITS _u(0x00004000) -#define RESETS_RESET_PLL_SYS_MSB _u(14) -#define RESETS_RESET_PLL_SYS_LSB _u(14) -#define RESETS_RESET_PLL_SYS_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RESETS_RESET_PIO2 -#define RESETS_RESET_PIO2_RESET _u(0x1) -#define RESETS_RESET_PIO2_BITS _u(0x00002000) -#define RESETS_RESET_PIO2_MSB _u(13) -#define RESETS_RESET_PIO2_LSB _u(13) -#define RESETS_RESET_PIO2_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RESETS_RESET_PIO1 -#define RESETS_RESET_PIO1_RESET _u(0x1) -#define RESETS_RESET_PIO1_BITS _u(0x00001000) -#define RESETS_RESET_PIO1_MSB _u(12) -#define RESETS_RESET_PIO1_LSB _u(12) -#define RESETS_RESET_PIO1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RESETS_RESET_PIO0 -#define RESETS_RESET_PIO0_RESET _u(0x1) -#define RESETS_RESET_PIO0_BITS _u(0x00000800) -#define RESETS_RESET_PIO0_MSB _u(11) -#define RESETS_RESET_PIO0_LSB _u(11) -#define RESETS_RESET_PIO0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RESETS_RESET_PADS_QSPI -#define RESETS_RESET_PADS_QSPI_RESET _u(0x1) -#define RESETS_RESET_PADS_QSPI_BITS _u(0x00000400) -#define RESETS_RESET_PADS_QSPI_MSB _u(10) -#define RESETS_RESET_PADS_QSPI_LSB _u(10) -#define RESETS_RESET_PADS_QSPI_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RESETS_RESET_PADS_BANK0 -#define RESETS_RESET_PADS_BANK0_RESET _u(0x1) -#define RESETS_RESET_PADS_BANK0_BITS _u(0x00000200) -#define RESETS_RESET_PADS_BANK0_MSB _u(9) -#define RESETS_RESET_PADS_BANK0_LSB _u(9) -#define RESETS_RESET_PADS_BANK0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RESETS_RESET_JTAG -#define RESETS_RESET_JTAG_RESET _u(0x1) -#define RESETS_RESET_JTAG_BITS _u(0x00000100) -#define RESETS_RESET_JTAG_MSB _u(8) -#define RESETS_RESET_JTAG_LSB _u(8) -#define RESETS_RESET_JTAG_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RESETS_RESET_IO_QSPI -#define RESETS_RESET_IO_QSPI_RESET _u(0x1) -#define RESETS_RESET_IO_QSPI_BITS _u(0x00000080) -#define RESETS_RESET_IO_QSPI_MSB _u(7) -#define RESETS_RESET_IO_QSPI_LSB _u(7) -#define RESETS_RESET_IO_QSPI_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RESETS_RESET_IO_BANK0 -#define RESETS_RESET_IO_BANK0_RESET _u(0x1) -#define RESETS_RESET_IO_BANK0_BITS _u(0x00000040) -#define RESETS_RESET_IO_BANK0_MSB _u(6) -#define RESETS_RESET_IO_BANK0_LSB _u(6) -#define RESETS_RESET_IO_BANK0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RESETS_RESET_I2C1 -#define RESETS_RESET_I2C1_RESET _u(0x1) -#define RESETS_RESET_I2C1_BITS _u(0x00000020) -#define RESETS_RESET_I2C1_MSB _u(5) -#define RESETS_RESET_I2C1_LSB _u(5) -#define RESETS_RESET_I2C1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RESETS_RESET_I2C0 -#define RESETS_RESET_I2C0_RESET _u(0x1) -#define RESETS_RESET_I2C0_BITS _u(0x00000010) -#define RESETS_RESET_I2C0_MSB _u(4) -#define RESETS_RESET_I2C0_LSB _u(4) -#define RESETS_RESET_I2C0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RESETS_RESET_HSTX -#define RESETS_RESET_HSTX_RESET _u(0x1) -#define RESETS_RESET_HSTX_BITS _u(0x00000008) -#define RESETS_RESET_HSTX_MSB _u(3) -#define RESETS_RESET_HSTX_LSB _u(3) -#define RESETS_RESET_HSTX_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RESETS_RESET_DMA -#define RESETS_RESET_DMA_RESET _u(0x1) -#define RESETS_RESET_DMA_BITS _u(0x00000004) -#define RESETS_RESET_DMA_MSB _u(2) -#define RESETS_RESET_DMA_LSB _u(2) -#define RESETS_RESET_DMA_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RESETS_RESET_BUSCTRL -#define RESETS_RESET_BUSCTRL_RESET _u(0x1) -#define RESETS_RESET_BUSCTRL_BITS _u(0x00000002) -#define RESETS_RESET_BUSCTRL_MSB _u(1) -#define RESETS_RESET_BUSCTRL_LSB _u(1) -#define RESETS_RESET_BUSCTRL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RESETS_RESET_ADC -#define RESETS_RESET_ADC_RESET _u(0x1) -#define RESETS_RESET_ADC_BITS _u(0x00000001) -#define RESETS_RESET_ADC_MSB _u(0) -#define RESETS_RESET_ADC_LSB _u(0) -#define RESETS_RESET_ADC_ACCESS "RW" -// ============================================================================= -// Register : RESETS_WDSEL -#define RESETS_WDSEL_OFFSET _u(0x00000004) -#define RESETS_WDSEL_BITS _u(0x1fffffff) -#define RESETS_WDSEL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : RESETS_WDSEL_USBCTRL -#define RESETS_WDSEL_USBCTRL_RESET _u(0x0) -#define RESETS_WDSEL_USBCTRL_BITS _u(0x10000000) -#define RESETS_WDSEL_USBCTRL_MSB _u(28) -#define RESETS_WDSEL_USBCTRL_LSB _u(28) -#define RESETS_WDSEL_USBCTRL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RESETS_WDSEL_UART1 -#define RESETS_WDSEL_UART1_RESET _u(0x0) -#define RESETS_WDSEL_UART1_BITS _u(0x08000000) -#define RESETS_WDSEL_UART1_MSB _u(27) -#define RESETS_WDSEL_UART1_LSB _u(27) -#define RESETS_WDSEL_UART1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RESETS_WDSEL_UART0 -#define RESETS_WDSEL_UART0_RESET _u(0x0) -#define RESETS_WDSEL_UART0_BITS _u(0x04000000) -#define RESETS_WDSEL_UART0_MSB _u(26) -#define RESETS_WDSEL_UART0_LSB _u(26) -#define RESETS_WDSEL_UART0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RESETS_WDSEL_TRNG -#define RESETS_WDSEL_TRNG_RESET _u(0x0) -#define RESETS_WDSEL_TRNG_BITS _u(0x02000000) -#define RESETS_WDSEL_TRNG_MSB _u(25) -#define RESETS_WDSEL_TRNG_LSB _u(25) -#define RESETS_WDSEL_TRNG_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RESETS_WDSEL_TIMER1 -#define RESETS_WDSEL_TIMER1_RESET _u(0x0) -#define RESETS_WDSEL_TIMER1_BITS _u(0x01000000) -#define RESETS_WDSEL_TIMER1_MSB _u(24) -#define RESETS_WDSEL_TIMER1_LSB _u(24) -#define RESETS_WDSEL_TIMER1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RESETS_WDSEL_TIMER0 -#define RESETS_WDSEL_TIMER0_RESET _u(0x0) -#define RESETS_WDSEL_TIMER0_BITS _u(0x00800000) -#define RESETS_WDSEL_TIMER0_MSB _u(23) -#define RESETS_WDSEL_TIMER0_LSB _u(23) -#define RESETS_WDSEL_TIMER0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RESETS_WDSEL_TBMAN -#define RESETS_WDSEL_TBMAN_RESET _u(0x0) -#define RESETS_WDSEL_TBMAN_BITS _u(0x00400000) -#define RESETS_WDSEL_TBMAN_MSB _u(22) -#define RESETS_WDSEL_TBMAN_LSB _u(22) -#define RESETS_WDSEL_TBMAN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RESETS_WDSEL_SYSINFO -#define RESETS_WDSEL_SYSINFO_RESET _u(0x0) -#define RESETS_WDSEL_SYSINFO_BITS _u(0x00200000) -#define RESETS_WDSEL_SYSINFO_MSB _u(21) -#define RESETS_WDSEL_SYSINFO_LSB _u(21) -#define RESETS_WDSEL_SYSINFO_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RESETS_WDSEL_SYSCFG -#define RESETS_WDSEL_SYSCFG_RESET _u(0x0) -#define RESETS_WDSEL_SYSCFG_BITS _u(0x00100000) -#define RESETS_WDSEL_SYSCFG_MSB _u(20) -#define RESETS_WDSEL_SYSCFG_LSB _u(20) -#define RESETS_WDSEL_SYSCFG_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RESETS_WDSEL_SPI1 -#define RESETS_WDSEL_SPI1_RESET _u(0x0) -#define RESETS_WDSEL_SPI1_BITS _u(0x00080000) -#define RESETS_WDSEL_SPI1_MSB _u(19) -#define RESETS_WDSEL_SPI1_LSB _u(19) -#define RESETS_WDSEL_SPI1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RESETS_WDSEL_SPI0 -#define RESETS_WDSEL_SPI0_RESET _u(0x0) -#define RESETS_WDSEL_SPI0_BITS _u(0x00040000) -#define RESETS_WDSEL_SPI0_MSB _u(18) -#define RESETS_WDSEL_SPI0_LSB _u(18) -#define RESETS_WDSEL_SPI0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RESETS_WDSEL_SHA256 -#define RESETS_WDSEL_SHA256_RESET _u(0x0) -#define RESETS_WDSEL_SHA256_BITS _u(0x00020000) -#define RESETS_WDSEL_SHA256_MSB _u(17) -#define RESETS_WDSEL_SHA256_LSB _u(17) -#define RESETS_WDSEL_SHA256_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RESETS_WDSEL_PWM -#define RESETS_WDSEL_PWM_RESET _u(0x0) -#define RESETS_WDSEL_PWM_BITS _u(0x00010000) -#define RESETS_WDSEL_PWM_MSB _u(16) -#define RESETS_WDSEL_PWM_LSB _u(16) -#define RESETS_WDSEL_PWM_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RESETS_WDSEL_PLL_USB -#define RESETS_WDSEL_PLL_USB_RESET _u(0x0) -#define RESETS_WDSEL_PLL_USB_BITS _u(0x00008000) -#define RESETS_WDSEL_PLL_USB_MSB _u(15) -#define RESETS_WDSEL_PLL_USB_LSB _u(15) -#define RESETS_WDSEL_PLL_USB_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RESETS_WDSEL_PLL_SYS -#define RESETS_WDSEL_PLL_SYS_RESET _u(0x0) -#define RESETS_WDSEL_PLL_SYS_BITS _u(0x00004000) -#define RESETS_WDSEL_PLL_SYS_MSB _u(14) -#define RESETS_WDSEL_PLL_SYS_LSB _u(14) -#define RESETS_WDSEL_PLL_SYS_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RESETS_WDSEL_PIO2 -#define RESETS_WDSEL_PIO2_RESET _u(0x0) -#define RESETS_WDSEL_PIO2_BITS _u(0x00002000) -#define RESETS_WDSEL_PIO2_MSB _u(13) -#define RESETS_WDSEL_PIO2_LSB _u(13) -#define RESETS_WDSEL_PIO2_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RESETS_WDSEL_PIO1 -#define RESETS_WDSEL_PIO1_RESET _u(0x0) -#define RESETS_WDSEL_PIO1_BITS _u(0x00001000) -#define RESETS_WDSEL_PIO1_MSB _u(12) -#define RESETS_WDSEL_PIO1_LSB _u(12) -#define RESETS_WDSEL_PIO1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RESETS_WDSEL_PIO0 -#define RESETS_WDSEL_PIO0_RESET _u(0x0) -#define RESETS_WDSEL_PIO0_BITS _u(0x00000800) -#define RESETS_WDSEL_PIO0_MSB _u(11) -#define RESETS_WDSEL_PIO0_LSB _u(11) -#define RESETS_WDSEL_PIO0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RESETS_WDSEL_PADS_QSPI -#define RESETS_WDSEL_PADS_QSPI_RESET _u(0x0) -#define RESETS_WDSEL_PADS_QSPI_BITS _u(0x00000400) -#define RESETS_WDSEL_PADS_QSPI_MSB _u(10) -#define RESETS_WDSEL_PADS_QSPI_LSB _u(10) -#define RESETS_WDSEL_PADS_QSPI_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RESETS_WDSEL_PADS_BANK0 -#define RESETS_WDSEL_PADS_BANK0_RESET _u(0x0) -#define RESETS_WDSEL_PADS_BANK0_BITS _u(0x00000200) -#define RESETS_WDSEL_PADS_BANK0_MSB _u(9) -#define RESETS_WDSEL_PADS_BANK0_LSB _u(9) -#define RESETS_WDSEL_PADS_BANK0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RESETS_WDSEL_JTAG -#define RESETS_WDSEL_JTAG_RESET _u(0x0) -#define RESETS_WDSEL_JTAG_BITS _u(0x00000100) -#define RESETS_WDSEL_JTAG_MSB _u(8) -#define RESETS_WDSEL_JTAG_LSB _u(8) -#define RESETS_WDSEL_JTAG_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RESETS_WDSEL_IO_QSPI -#define RESETS_WDSEL_IO_QSPI_RESET _u(0x0) -#define RESETS_WDSEL_IO_QSPI_BITS _u(0x00000080) -#define RESETS_WDSEL_IO_QSPI_MSB _u(7) -#define RESETS_WDSEL_IO_QSPI_LSB _u(7) -#define RESETS_WDSEL_IO_QSPI_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RESETS_WDSEL_IO_BANK0 -#define RESETS_WDSEL_IO_BANK0_RESET _u(0x0) -#define RESETS_WDSEL_IO_BANK0_BITS _u(0x00000040) -#define RESETS_WDSEL_IO_BANK0_MSB _u(6) -#define RESETS_WDSEL_IO_BANK0_LSB _u(6) -#define RESETS_WDSEL_IO_BANK0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RESETS_WDSEL_I2C1 -#define RESETS_WDSEL_I2C1_RESET _u(0x0) -#define RESETS_WDSEL_I2C1_BITS _u(0x00000020) -#define RESETS_WDSEL_I2C1_MSB _u(5) -#define RESETS_WDSEL_I2C1_LSB _u(5) -#define RESETS_WDSEL_I2C1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RESETS_WDSEL_I2C0 -#define RESETS_WDSEL_I2C0_RESET _u(0x0) -#define RESETS_WDSEL_I2C0_BITS _u(0x00000010) -#define RESETS_WDSEL_I2C0_MSB _u(4) -#define RESETS_WDSEL_I2C0_LSB _u(4) -#define RESETS_WDSEL_I2C0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RESETS_WDSEL_HSTX -#define RESETS_WDSEL_HSTX_RESET _u(0x0) -#define RESETS_WDSEL_HSTX_BITS _u(0x00000008) -#define RESETS_WDSEL_HSTX_MSB _u(3) -#define RESETS_WDSEL_HSTX_LSB _u(3) -#define RESETS_WDSEL_HSTX_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RESETS_WDSEL_DMA -#define RESETS_WDSEL_DMA_RESET _u(0x0) -#define RESETS_WDSEL_DMA_BITS _u(0x00000004) -#define RESETS_WDSEL_DMA_MSB _u(2) -#define RESETS_WDSEL_DMA_LSB _u(2) -#define RESETS_WDSEL_DMA_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RESETS_WDSEL_BUSCTRL -#define RESETS_WDSEL_BUSCTRL_RESET _u(0x0) -#define RESETS_WDSEL_BUSCTRL_BITS _u(0x00000002) -#define RESETS_WDSEL_BUSCTRL_MSB _u(1) -#define RESETS_WDSEL_BUSCTRL_LSB _u(1) -#define RESETS_WDSEL_BUSCTRL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RESETS_WDSEL_ADC -#define RESETS_WDSEL_ADC_RESET _u(0x0) -#define RESETS_WDSEL_ADC_BITS _u(0x00000001) -#define RESETS_WDSEL_ADC_MSB _u(0) -#define RESETS_WDSEL_ADC_LSB _u(0) -#define RESETS_WDSEL_ADC_ACCESS "RW" -// ============================================================================= -// Register : RESETS_RESET_DONE -#define RESETS_RESET_DONE_OFFSET _u(0x00000008) -#define RESETS_RESET_DONE_BITS _u(0x1fffffff) -#define RESETS_RESET_DONE_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : RESETS_RESET_DONE_USBCTRL -#define RESETS_RESET_DONE_USBCTRL_RESET _u(0x0) -#define RESETS_RESET_DONE_USBCTRL_BITS _u(0x10000000) -#define RESETS_RESET_DONE_USBCTRL_MSB _u(28) -#define RESETS_RESET_DONE_USBCTRL_LSB _u(28) -#define RESETS_RESET_DONE_USBCTRL_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RESETS_RESET_DONE_UART1 -#define RESETS_RESET_DONE_UART1_RESET _u(0x0) -#define RESETS_RESET_DONE_UART1_BITS _u(0x08000000) -#define RESETS_RESET_DONE_UART1_MSB _u(27) -#define RESETS_RESET_DONE_UART1_LSB _u(27) -#define RESETS_RESET_DONE_UART1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RESETS_RESET_DONE_UART0 -#define RESETS_RESET_DONE_UART0_RESET _u(0x0) -#define RESETS_RESET_DONE_UART0_BITS _u(0x04000000) -#define RESETS_RESET_DONE_UART0_MSB _u(26) -#define RESETS_RESET_DONE_UART0_LSB _u(26) -#define RESETS_RESET_DONE_UART0_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RESETS_RESET_DONE_TRNG -#define RESETS_RESET_DONE_TRNG_RESET _u(0x0) -#define RESETS_RESET_DONE_TRNG_BITS _u(0x02000000) -#define RESETS_RESET_DONE_TRNG_MSB _u(25) -#define RESETS_RESET_DONE_TRNG_LSB _u(25) -#define RESETS_RESET_DONE_TRNG_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RESETS_RESET_DONE_TIMER1 -#define RESETS_RESET_DONE_TIMER1_RESET _u(0x0) -#define RESETS_RESET_DONE_TIMER1_BITS _u(0x01000000) -#define RESETS_RESET_DONE_TIMER1_MSB _u(24) -#define RESETS_RESET_DONE_TIMER1_LSB _u(24) -#define RESETS_RESET_DONE_TIMER1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RESETS_RESET_DONE_TIMER0 -#define RESETS_RESET_DONE_TIMER0_RESET _u(0x0) -#define RESETS_RESET_DONE_TIMER0_BITS _u(0x00800000) -#define RESETS_RESET_DONE_TIMER0_MSB _u(23) -#define RESETS_RESET_DONE_TIMER0_LSB _u(23) -#define RESETS_RESET_DONE_TIMER0_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RESETS_RESET_DONE_TBMAN -#define RESETS_RESET_DONE_TBMAN_RESET _u(0x0) -#define RESETS_RESET_DONE_TBMAN_BITS _u(0x00400000) -#define RESETS_RESET_DONE_TBMAN_MSB _u(22) -#define RESETS_RESET_DONE_TBMAN_LSB _u(22) -#define RESETS_RESET_DONE_TBMAN_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RESETS_RESET_DONE_SYSINFO -#define RESETS_RESET_DONE_SYSINFO_RESET _u(0x0) -#define RESETS_RESET_DONE_SYSINFO_BITS _u(0x00200000) -#define RESETS_RESET_DONE_SYSINFO_MSB _u(21) -#define RESETS_RESET_DONE_SYSINFO_LSB _u(21) -#define RESETS_RESET_DONE_SYSINFO_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RESETS_RESET_DONE_SYSCFG -#define RESETS_RESET_DONE_SYSCFG_RESET _u(0x0) -#define RESETS_RESET_DONE_SYSCFG_BITS _u(0x00100000) -#define RESETS_RESET_DONE_SYSCFG_MSB _u(20) -#define RESETS_RESET_DONE_SYSCFG_LSB _u(20) -#define RESETS_RESET_DONE_SYSCFG_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RESETS_RESET_DONE_SPI1 -#define RESETS_RESET_DONE_SPI1_RESET _u(0x0) -#define RESETS_RESET_DONE_SPI1_BITS _u(0x00080000) -#define RESETS_RESET_DONE_SPI1_MSB _u(19) -#define RESETS_RESET_DONE_SPI1_LSB _u(19) -#define RESETS_RESET_DONE_SPI1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RESETS_RESET_DONE_SPI0 -#define RESETS_RESET_DONE_SPI0_RESET _u(0x0) -#define RESETS_RESET_DONE_SPI0_BITS _u(0x00040000) -#define RESETS_RESET_DONE_SPI0_MSB _u(18) -#define RESETS_RESET_DONE_SPI0_LSB _u(18) -#define RESETS_RESET_DONE_SPI0_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RESETS_RESET_DONE_SHA256 -#define RESETS_RESET_DONE_SHA256_RESET _u(0x0) -#define RESETS_RESET_DONE_SHA256_BITS _u(0x00020000) -#define RESETS_RESET_DONE_SHA256_MSB _u(17) -#define RESETS_RESET_DONE_SHA256_LSB _u(17) -#define RESETS_RESET_DONE_SHA256_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RESETS_RESET_DONE_PWM -#define RESETS_RESET_DONE_PWM_RESET _u(0x0) -#define RESETS_RESET_DONE_PWM_BITS _u(0x00010000) -#define RESETS_RESET_DONE_PWM_MSB _u(16) -#define RESETS_RESET_DONE_PWM_LSB _u(16) -#define RESETS_RESET_DONE_PWM_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RESETS_RESET_DONE_PLL_USB -#define RESETS_RESET_DONE_PLL_USB_RESET _u(0x0) -#define RESETS_RESET_DONE_PLL_USB_BITS _u(0x00008000) -#define RESETS_RESET_DONE_PLL_USB_MSB _u(15) -#define RESETS_RESET_DONE_PLL_USB_LSB _u(15) -#define RESETS_RESET_DONE_PLL_USB_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RESETS_RESET_DONE_PLL_SYS -#define RESETS_RESET_DONE_PLL_SYS_RESET _u(0x0) -#define RESETS_RESET_DONE_PLL_SYS_BITS _u(0x00004000) -#define RESETS_RESET_DONE_PLL_SYS_MSB _u(14) -#define RESETS_RESET_DONE_PLL_SYS_LSB _u(14) -#define RESETS_RESET_DONE_PLL_SYS_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RESETS_RESET_DONE_PIO2 -#define RESETS_RESET_DONE_PIO2_RESET _u(0x0) -#define RESETS_RESET_DONE_PIO2_BITS _u(0x00002000) -#define RESETS_RESET_DONE_PIO2_MSB _u(13) -#define RESETS_RESET_DONE_PIO2_LSB _u(13) -#define RESETS_RESET_DONE_PIO2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RESETS_RESET_DONE_PIO1 -#define RESETS_RESET_DONE_PIO1_RESET _u(0x0) -#define RESETS_RESET_DONE_PIO1_BITS _u(0x00001000) -#define RESETS_RESET_DONE_PIO1_MSB _u(12) -#define RESETS_RESET_DONE_PIO1_LSB _u(12) -#define RESETS_RESET_DONE_PIO1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RESETS_RESET_DONE_PIO0 -#define RESETS_RESET_DONE_PIO0_RESET _u(0x0) -#define RESETS_RESET_DONE_PIO0_BITS _u(0x00000800) -#define RESETS_RESET_DONE_PIO0_MSB _u(11) -#define RESETS_RESET_DONE_PIO0_LSB _u(11) -#define RESETS_RESET_DONE_PIO0_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RESETS_RESET_DONE_PADS_QSPI -#define RESETS_RESET_DONE_PADS_QSPI_RESET _u(0x0) -#define RESETS_RESET_DONE_PADS_QSPI_BITS _u(0x00000400) -#define RESETS_RESET_DONE_PADS_QSPI_MSB _u(10) -#define RESETS_RESET_DONE_PADS_QSPI_LSB _u(10) -#define RESETS_RESET_DONE_PADS_QSPI_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RESETS_RESET_DONE_PADS_BANK0 -#define RESETS_RESET_DONE_PADS_BANK0_RESET _u(0x0) -#define RESETS_RESET_DONE_PADS_BANK0_BITS _u(0x00000200) -#define RESETS_RESET_DONE_PADS_BANK0_MSB _u(9) -#define RESETS_RESET_DONE_PADS_BANK0_LSB _u(9) -#define RESETS_RESET_DONE_PADS_BANK0_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RESETS_RESET_DONE_JTAG -#define RESETS_RESET_DONE_JTAG_RESET _u(0x0) -#define RESETS_RESET_DONE_JTAG_BITS _u(0x00000100) -#define RESETS_RESET_DONE_JTAG_MSB _u(8) -#define RESETS_RESET_DONE_JTAG_LSB _u(8) -#define RESETS_RESET_DONE_JTAG_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RESETS_RESET_DONE_IO_QSPI -#define RESETS_RESET_DONE_IO_QSPI_RESET _u(0x0) -#define RESETS_RESET_DONE_IO_QSPI_BITS _u(0x00000080) -#define RESETS_RESET_DONE_IO_QSPI_MSB _u(7) -#define RESETS_RESET_DONE_IO_QSPI_LSB _u(7) -#define RESETS_RESET_DONE_IO_QSPI_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RESETS_RESET_DONE_IO_BANK0 -#define RESETS_RESET_DONE_IO_BANK0_RESET _u(0x0) -#define RESETS_RESET_DONE_IO_BANK0_BITS _u(0x00000040) -#define RESETS_RESET_DONE_IO_BANK0_MSB _u(6) -#define RESETS_RESET_DONE_IO_BANK0_LSB _u(6) -#define RESETS_RESET_DONE_IO_BANK0_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RESETS_RESET_DONE_I2C1 -#define RESETS_RESET_DONE_I2C1_RESET _u(0x0) -#define RESETS_RESET_DONE_I2C1_BITS _u(0x00000020) -#define RESETS_RESET_DONE_I2C1_MSB _u(5) -#define RESETS_RESET_DONE_I2C1_LSB _u(5) -#define RESETS_RESET_DONE_I2C1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RESETS_RESET_DONE_I2C0 -#define RESETS_RESET_DONE_I2C0_RESET _u(0x0) -#define RESETS_RESET_DONE_I2C0_BITS _u(0x00000010) -#define RESETS_RESET_DONE_I2C0_MSB _u(4) -#define RESETS_RESET_DONE_I2C0_LSB _u(4) -#define RESETS_RESET_DONE_I2C0_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RESETS_RESET_DONE_HSTX -#define RESETS_RESET_DONE_HSTX_RESET _u(0x0) -#define RESETS_RESET_DONE_HSTX_BITS _u(0x00000008) -#define RESETS_RESET_DONE_HSTX_MSB _u(3) -#define RESETS_RESET_DONE_HSTX_LSB _u(3) -#define RESETS_RESET_DONE_HSTX_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RESETS_RESET_DONE_DMA -#define RESETS_RESET_DONE_DMA_RESET _u(0x0) -#define RESETS_RESET_DONE_DMA_BITS _u(0x00000004) -#define RESETS_RESET_DONE_DMA_MSB _u(2) -#define RESETS_RESET_DONE_DMA_LSB _u(2) -#define RESETS_RESET_DONE_DMA_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RESETS_RESET_DONE_BUSCTRL -#define RESETS_RESET_DONE_BUSCTRL_RESET _u(0x0) -#define RESETS_RESET_DONE_BUSCTRL_BITS _u(0x00000002) -#define RESETS_RESET_DONE_BUSCTRL_MSB _u(1) -#define RESETS_RESET_DONE_BUSCTRL_LSB _u(1) -#define RESETS_RESET_DONE_BUSCTRL_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RESETS_RESET_DONE_ADC -#define RESETS_RESET_DONE_ADC_RESET _u(0x0) -#define RESETS_RESET_DONE_ADC_BITS _u(0x00000001) -#define RESETS_RESET_DONE_ADC_MSB _u(0) -#define RESETS_RESET_DONE_ADC_LSB _u(0) -#define RESETS_RESET_DONE_ADC_ACCESS "RO" -// ============================================================================= -#endif // _HARDWARE_REGS_RESETS_H - diff --git a/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/riscv_dm.h b/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/riscv_dm.h deleted file mode 100644 index bbf64a2963..0000000000 --- a/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/riscv_dm.h +++ /dev/null @@ -1,1025 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -// ============================================================================= -// Register block : RISCV_DM -// Version : 1 -// Bus type : apb -// Description : RISC-V Debug module registers (Hazard3 subset only). Read- -// only information fields (such as dmstatus.version) are -// listed here with the values they have on the RP2350 -// instantiation of Hazard3. -// ============================================================================= -#ifndef _HARDWARE_REGS_RISCV_DM_H -#define _HARDWARE_REGS_RISCV_DM_H -// ============================================================================= -// Register : RISCV_DM_DATA0 -// Description : data0 through data11 are basic read/write registers that may be -// read or changed by abstract commands. abstractcs.datacount -// indicates how many of them are implemented, starting at data0, -// counting up. -// -// Accessing these registers while an abstract command is -// executing causes abstractcs.cmderr to be set to 1 (busy) if it -// is 0. -// -// Attempts to write them while abstractcs.busy is set does not -// change their value. -// -// The values in these registers may not be preserved after an -// abstract command is executed. The only guarantees on their -// contents are the ones offered by the command in question. If -// the command fails, no assumptions can be made about the -// contents of these registers. -// -// (Note: Hazard3 implements data0 only.) -#define RISCV_DM_DATA0_OFFSET _u(0x00000010) -#define RISCV_DM_DATA0_BITS _u(0xffffffff) -#define RISCV_DM_DATA0_RESET _u(0x00000000) -#define RISCV_DM_DATA0_MSB _u(31) -#define RISCV_DM_DATA0_LSB _u(0) -#define RISCV_DM_DATA0_ACCESS "RW" -// ============================================================================= -// Register : RISCV_DM_DMCONTROL -// Description : This register controls the overall Debug Module as well as the -// currently selected harts, as defined in hasel. -#define RISCV_DM_DMCONTROL_OFFSET _u(0x00000040) -#define RISCV_DM_DMCONTROL_BITS _u(0xf7ffffcf) -#define RISCV_DM_DMCONTROL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : RISCV_DM_DMCONTROL_HALTREQ -// Description : Writing 0 clears the halt request bit for all currently -// selected harts. This may cancel outstanding halt requests for -// those harts. -// -// Writing 1 sets the halt request bit for all currently selected -// harts. Running harts will halt whenever their halt request bit -// is set. -// -// Writes apply to the new value of hartsel and hasel. -#define RISCV_DM_DMCONTROL_HALTREQ_RESET _u(0x0) -#define RISCV_DM_DMCONTROL_HALTREQ_BITS _u(0x80000000) -#define RISCV_DM_DMCONTROL_HALTREQ_MSB _u(31) -#define RISCV_DM_DMCONTROL_HALTREQ_LSB _u(31) -#define RISCV_DM_DMCONTROL_HALTREQ_ACCESS "WO" -// ----------------------------------------------------------------------------- -// Field : RISCV_DM_DMCONTROL_RESUMEREQ -// Description : Writing 1 causes the currently selected harts to resume once, -// if they are halted when the write occurs. It also clears the -// resume ack bit for those harts. -// -// resumereq is ignored if haltreq is set. -// -// Writes apply to the new value of hartsel and hasel. -#define RISCV_DM_DMCONTROL_RESUMEREQ_RESET _u(0x0) -#define RISCV_DM_DMCONTROL_RESUMEREQ_BITS _u(0x40000000) -#define RISCV_DM_DMCONTROL_RESUMEREQ_MSB _u(30) -#define RISCV_DM_DMCONTROL_RESUMEREQ_LSB _u(30) -#define RISCV_DM_DMCONTROL_RESUMEREQ_ACCESS "SC" -// ----------------------------------------------------------------------------- -// Field : RISCV_DM_DMCONTROL_HARTRESET -// Description : This optional field writes the reset bit for all the currently -// selected harts. To perform a reset the debugger writes 1, and -// then writes 0 to deassert the reset signal. -// -// While this bit is 1, the debugger must not change which harts -// are selected. -// -// Writes apply to the new value of hartsel and hasel. -// -// (The exact behaviour of this field is implementation-defined: -// on RP2350 it (triggers a local reset of the selected core(s) -// only.) -#define RISCV_DM_DMCONTROL_HARTRESET_RESET _u(0x0) -#define RISCV_DM_DMCONTROL_HARTRESET_BITS _u(0x20000000) -#define RISCV_DM_DMCONTROL_HARTRESET_MSB _u(29) -#define RISCV_DM_DMCONTROL_HARTRESET_LSB _u(29) -#define RISCV_DM_DMCONTROL_HARTRESET_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RISCV_DM_DMCONTROL_ACKHAVERESET -// Description : 0: No effect. -// -// 1: Clears havereset for any selected harts. -// -// Writes apply to the new value of hartsel and hasel. -#define RISCV_DM_DMCONTROL_ACKHAVERESET_RESET _u(0x0) -#define RISCV_DM_DMCONTROL_ACKHAVERESET_BITS _u(0x10000000) -#define RISCV_DM_DMCONTROL_ACKHAVERESET_MSB _u(28) -#define RISCV_DM_DMCONTROL_ACKHAVERESET_LSB _u(28) -#define RISCV_DM_DMCONTROL_ACKHAVERESET_ACCESS "SC" -// ----------------------------------------------------------------------------- -// Field : RISCV_DM_DMCONTROL_HASEL -// Description : Selects the definition of currently selected harts. -// -// 0: There is a single currently selected hart, that is selected -// by hartsel. -// -// 1: There may be multiple currently selected harts – the hart -// selected by hartsel, plus those selected by the hart array mask -// register. -// -// Hazard3 does support the hart array mask. -#define RISCV_DM_DMCONTROL_HASEL_RESET _u(0x0) -#define RISCV_DM_DMCONTROL_HASEL_BITS _u(0x04000000) -#define RISCV_DM_DMCONTROL_HASEL_MSB _u(26) -#define RISCV_DM_DMCONTROL_HASEL_LSB _u(26) -#define RISCV_DM_DMCONTROL_HASEL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RISCV_DM_DMCONTROL_HARTSELLO -// Description : The low 10 bits of hartsel: the DM-specific index of the hart -// to select. This hart is always part of the currently selected -// harts. -// -// On RP2350, since there are only two cores (with one hart each), -// only the least-significant bit is writable. The others are tied -// to 0. -#define RISCV_DM_DMCONTROL_HARTSELLO_RESET _u(0x000) -#define RISCV_DM_DMCONTROL_HARTSELLO_BITS _u(0x03ff0000) -#define RISCV_DM_DMCONTROL_HARTSELLO_MSB _u(25) -#define RISCV_DM_DMCONTROL_HARTSELLO_LSB _u(16) -#define RISCV_DM_DMCONTROL_HARTSELLO_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RISCV_DM_DMCONTROL_HARTSELHI -// Description : The high 10 bits of hartsel: the DM-specific index of the hart -// to select. This hart is always part of the currently selected -// harts. -// -// On Hazard3 this field is always tied to all-zeroes. -#define RISCV_DM_DMCONTROL_HARTSELHI_RESET _u(0x000) -#define RISCV_DM_DMCONTROL_HARTSELHI_BITS _u(0x0000ffc0) -#define RISCV_DM_DMCONTROL_HARTSELHI_MSB _u(15) -#define RISCV_DM_DMCONTROL_HARTSELHI_LSB _u(6) -#define RISCV_DM_DMCONTROL_HARTSELHI_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RISCV_DM_DMCONTROL_SETRESETHALTREQ -// Description : This optional field writes the halt-on-reset request bit for -// all currently selected harts, unless clrresethaltreq is -// simultaneously set to 1. -// -// When set to 1, each selected hart will halt upon the next -// deassertion of its reset. The halt-on-reset request bit is not -// automatically cleared. The debugger must write to -// clrresethaltreq to clear it. -// -// Writes apply to the new value of hartsel and hasel. -#define RISCV_DM_DMCONTROL_SETRESETHALTREQ_RESET _u(0x0) -#define RISCV_DM_DMCONTROL_SETRESETHALTREQ_BITS _u(0x00000008) -#define RISCV_DM_DMCONTROL_SETRESETHALTREQ_MSB _u(3) -#define RISCV_DM_DMCONTROL_SETRESETHALTREQ_LSB _u(3) -#define RISCV_DM_DMCONTROL_SETRESETHALTREQ_ACCESS "SC" -// ----------------------------------------------------------------------------- -// Field : RISCV_DM_DMCONTROL_CLRRESETHALTREQ -// Description : This optional field clears the halt-on-reset request bit for -// all currently selected harts. -// -// Writes apply to the new value of hartsel and hasel. -#define RISCV_DM_DMCONTROL_CLRRESETHALTREQ_RESET _u(0x0) -#define RISCV_DM_DMCONTROL_CLRRESETHALTREQ_BITS _u(0x00000004) -#define RISCV_DM_DMCONTROL_CLRRESETHALTREQ_MSB _u(2) -#define RISCV_DM_DMCONTROL_CLRRESETHALTREQ_LSB _u(2) -#define RISCV_DM_DMCONTROL_CLRRESETHALTREQ_ACCESS "SC" -// ----------------------------------------------------------------------------- -// Field : RISCV_DM_DMCONTROL_NDMRESET -// Description : This bit controls the reset signal from the DM to the rest of -// the system. The signal should reset every part of the system, -// including every hart, except for the DM and any logic required -// to access the DM. To perform a system reset the debugger writes -// 1, and then writes 0 to deassert the reset. -// -// On RP2350 this performs a cold reset, the equivalent of a -// watchdog reset with all WDSEL bits set. This includes both -// cores and all peripherals. -#define RISCV_DM_DMCONTROL_NDMRESET_RESET _u(0x0) -#define RISCV_DM_DMCONTROL_NDMRESET_BITS _u(0x00000002) -#define RISCV_DM_DMCONTROL_NDMRESET_MSB _u(1) -#define RISCV_DM_DMCONTROL_NDMRESET_LSB _u(1) -#define RISCV_DM_DMCONTROL_NDMRESET_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RISCV_DM_DMCONTROL_DMACTIVE -// Description : This bit serves as a reset signal for the Debug Module itself. -// -// 0: The module’s state, including authentication mechanism, -// takes its reset values (the dmactive bit is the only bit which -// can be written to something other than its reset value). -// -// 1: The module functions normally. -// -// No other mechanism should exist that may result in resetting -// the Debug Module after power up, with the possible (but not -// recommended) exception of a global reset signal that resets the -// entire platform. -// -// (On RP2350, the Debug Module is reset by a power-on reset, a -// brownout reset, the RUN pin, and a rescue reset.) -// -// A debugger may pulse this bit low to get the Debug Module into -// a known state. -#define RISCV_DM_DMCONTROL_DMACTIVE_RESET _u(0x0) -#define RISCV_DM_DMCONTROL_DMACTIVE_BITS _u(0x00000001) -#define RISCV_DM_DMCONTROL_DMACTIVE_MSB _u(0) -#define RISCV_DM_DMCONTROL_DMACTIVE_LSB _u(0) -#define RISCV_DM_DMCONTROL_DMACTIVE_ACCESS "RW" -// ============================================================================= -// Register : RISCV_DM_DMSTATUS -// Description : This register reports status for the overall Debug Module as -// well as the currently selected harts, as defined in hasel. Its -// address will not change in the future, because it contains -// version. -// -// This entire register is read-only. -#define RISCV_DM_DMSTATUS_OFFSET _u(0x00000044) -#define RISCV_DM_DMSTATUS_BITS _u(0x004fffff) -#define RISCV_DM_DMSTATUS_RESET _u(0x004000a2) -// ----------------------------------------------------------------------------- -// Field : RISCV_DM_DMSTATUS_IMPEBREAK -// Description : If 1, then there is an implicit ebreak instruction at the non- -// existent word immediately after the Program Buffer. This saves -// the debugger from having to write the ebreak itself, and allows -// the Program Buffer to be one word smaller. -#define RISCV_DM_DMSTATUS_IMPEBREAK_RESET _u(0x1) -#define RISCV_DM_DMSTATUS_IMPEBREAK_BITS _u(0x00400000) -#define RISCV_DM_DMSTATUS_IMPEBREAK_MSB _u(22) -#define RISCV_DM_DMSTATUS_IMPEBREAK_LSB _u(22) -#define RISCV_DM_DMSTATUS_IMPEBREAK_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RISCV_DM_DMSTATUS_ALLHAVERESET -// Description : This field is 1 when all currently selected harts have been -// reset and reset has not been acknowledged for any of them. -#define RISCV_DM_DMSTATUS_ALLHAVERESET_RESET _u(0x0) -#define RISCV_DM_DMSTATUS_ALLHAVERESET_BITS _u(0x00080000) -#define RISCV_DM_DMSTATUS_ALLHAVERESET_MSB _u(19) -#define RISCV_DM_DMSTATUS_ALLHAVERESET_LSB _u(19) -#define RISCV_DM_DMSTATUS_ALLHAVERESET_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RISCV_DM_DMSTATUS_ANYHAVERESET -// Description : This field is 1 when at least one currently selected hart has -// been reset and reset has not been acknowledged for that hart. -#define RISCV_DM_DMSTATUS_ANYHAVERESET_RESET _u(0x0) -#define RISCV_DM_DMSTATUS_ANYHAVERESET_BITS _u(0x00040000) -#define RISCV_DM_DMSTATUS_ANYHAVERESET_MSB _u(18) -#define RISCV_DM_DMSTATUS_ANYHAVERESET_LSB _u(18) -#define RISCV_DM_DMSTATUS_ANYHAVERESET_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RISCV_DM_DMSTATUS_ALLRESUMEACK -// Description : This field is 1 when all currently selected harts have -// acknowledged their last resume request. -#define RISCV_DM_DMSTATUS_ALLRESUMEACK_RESET _u(0x0) -#define RISCV_DM_DMSTATUS_ALLRESUMEACK_BITS _u(0x00020000) -#define RISCV_DM_DMSTATUS_ALLRESUMEACK_MSB _u(17) -#define RISCV_DM_DMSTATUS_ALLRESUMEACK_LSB _u(17) -#define RISCV_DM_DMSTATUS_ALLRESUMEACK_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RISCV_DM_DMSTATUS_ANYRESUMEACK -// Description : This field is 1 when any currently selected hart has -// acknowledged its last resume request. -#define RISCV_DM_DMSTATUS_ANYRESUMEACK_RESET _u(0x0) -#define RISCV_DM_DMSTATUS_ANYRESUMEACK_BITS _u(0x00010000) -#define RISCV_DM_DMSTATUS_ANYRESUMEACK_MSB _u(16) -#define RISCV_DM_DMSTATUS_ANYRESUMEACK_LSB _u(16) -#define RISCV_DM_DMSTATUS_ANYRESUMEACK_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RISCV_DM_DMSTATUS_ALLNONEXISTENT -// Description : This field is 1 when all currently selected harts do not exist -// on this platform. -#define RISCV_DM_DMSTATUS_ALLNONEXISTENT_RESET "-" -#define RISCV_DM_DMSTATUS_ALLNONEXISTENT_BITS _u(0x00008000) -#define RISCV_DM_DMSTATUS_ALLNONEXISTENT_MSB _u(15) -#define RISCV_DM_DMSTATUS_ALLNONEXISTENT_LSB _u(15) -#define RISCV_DM_DMSTATUS_ALLNONEXISTENT_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RISCV_DM_DMSTATUS_ANYNONEXISTENT -// Description : This field is 1 when any currently selected hart does not exist -// in this platform. -#define RISCV_DM_DMSTATUS_ANYNONEXISTENT_RESET "-" -#define RISCV_DM_DMSTATUS_ANYNONEXISTENT_BITS _u(0x00004000) -#define RISCV_DM_DMSTATUS_ANYNONEXISTENT_MSB _u(14) -#define RISCV_DM_DMSTATUS_ANYNONEXISTENT_LSB _u(14) -#define RISCV_DM_DMSTATUS_ANYNONEXISTENT_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RISCV_DM_DMSTATUS_ALLUNAVAIL -// Description : This field is 1 when all currently selected harts are -// unavailable. -#define RISCV_DM_DMSTATUS_ALLUNAVAIL_RESET "-" -#define RISCV_DM_DMSTATUS_ALLUNAVAIL_BITS _u(0x00002000) -#define RISCV_DM_DMSTATUS_ALLUNAVAIL_MSB _u(13) -#define RISCV_DM_DMSTATUS_ALLUNAVAIL_LSB _u(13) -#define RISCV_DM_DMSTATUS_ALLUNAVAIL_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RISCV_DM_DMSTATUS_ANYUNAVAIL -// Description : This field is 1 when any currently selected hart is -// unavailable. -#define RISCV_DM_DMSTATUS_ANYUNAVAIL_RESET "-" -#define RISCV_DM_DMSTATUS_ANYUNAVAIL_BITS _u(0x00001000) -#define RISCV_DM_DMSTATUS_ANYUNAVAIL_MSB _u(12) -#define RISCV_DM_DMSTATUS_ANYUNAVAIL_LSB _u(12) -#define RISCV_DM_DMSTATUS_ANYUNAVAIL_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RISCV_DM_DMSTATUS_ALLRUNNING -// Description : This field is 1 when all currently selected harts are running. -#define RISCV_DM_DMSTATUS_ALLRUNNING_RESET _u(0x0) -#define RISCV_DM_DMSTATUS_ALLRUNNING_BITS _u(0x00000800) -#define RISCV_DM_DMSTATUS_ALLRUNNING_MSB _u(11) -#define RISCV_DM_DMSTATUS_ALLRUNNING_LSB _u(11) -#define RISCV_DM_DMSTATUS_ALLRUNNING_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RISCV_DM_DMSTATUS_ANYRUNNING -// Description : This field is 1 when any currently selected hart is running. -#define RISCV_DM_DMSTATUS_ANYRUNNING_RESET _u(0x0) -#define RISCV_DM_DMSTATUS_ANYRUNNING_BITS _u(0x00000400) -#define RISCV_DM_DMSTATUS_ANYRUNNING_MSB _u(10) -#define RISCV_DM_DMSTATUS_ANYRUNNING_LSB _u(10) -#define RISCV_DM_DMSTATUS_ANYRUNNING_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RISCV_DM_DMSTATUS_ALLHALTED -// Description : This field is 1 when all currently selected harts are halted. -#define RISCV_DM_DMSTATUS_ALLHALTED_RESET _u(0x0) -#define RISCV_DM_DMSTATUS_ALLHALTED_BITS _u(0x00000200) -#define RISCV_DM_DMSTATUS_ALLHALTED_MSB _u(9) -#define RISCV_DM_DMSTATUS_ALLHALTED_LSB _u(9) -#define RISCV_DM_DMSTATUS_ALLHALTED_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RISCV_DM_DMSTATUS_ANYHALTED -// Description : This field is 1 when any currently selected hart is halted. -#define RISCV_DM_DMSTATUS_ANYHALTED_RESET _u(0x0) -#define RISCV_DM_DMSTATUS_ANYHALTED_BITS _u(0x00000100) -#define RISCV_DM_DMSTATUS_ANYHALTED_MSB _u(8) -#define RISCV_DM_DMSTATUS_ANYHALTED_LSB _u(8) -#define RISCV_DM_DMSTATUS_ANYHALTED_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RISCV_DM_DMSTATUS_AUTHENTICATED -// Description : 0: Authentication is required before using the DM. -// -// 1: The authentication check has passed. -// -// On components that don’t implement authentication, this bit -// must be preset as 1. (Note: the version of Hazard3 on RP2350 -// does not implement authentication.) -#define RISCV_DM_DMSTATUS_AUTHENTICATED_RESET _u(0x1) -#define RISCV_DM_DMSTATUS_AUTHENTICATED_BITS _u(0x00000080) -#define RISCV_DM_DMSTATUS_AUTHENTICATED_MSB _u(7) -#define RISCV_DM_DMSTATUS_AUTHENTICATED_LSB _u(7) -#define RISCV_DM_DMSTATUS_AUTHENTICATED_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RISCV_DM_DMSTATUS_AUTHBUSY -// Description : 0: The authentication module is ready to process the next -// read/write to authdata. -// -// 1: The authentication module is busy. Accessing authdata -// results in unspecified behavior. authbusy only becomes set in -// immediate response to an access to authdata. -#define RISCV_DM_DMSTATUS_AUTHBUSY_RESET _u(0x0) -#define RISCV_DM_DMSTATUS_AUTHBUSY_BITS _u(0x00000040) -#define RISCV_DM_DMSTATUS_AUTHBUSY_MSB _u(6) -#define RISCV_DM_DMSTATUS_AUTHBUSY_LSB _u(6) -#define RISCV_DM_DMSTATUS_AUTHBUSY_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RISCV_DM_DMSTATUS_HASRESETHALTREQ -// Description : 1 if this Debug Module supports halt-on-reset functionality -// controllable by the setresethaltreq and clrresethaltreq bits. 0 -// otherwise. -#define RISCV_DM_DMSTATUS_HASRESETHALTREQ_RESET _u(0x1) -#define RISCV_DM_DMSTATUS_HASRESETHALTREQ_BITS _u(0x00000020) -#define RISCV_DM_DMSTATUS_HASRESETHALTREQ_MSB _u(5) -#define RISCV_DM_DMSTATUS_HASRESETHALTREQ_LSB _u(5) -#define RISCV_DM_DMSTATUS_HASRESETHALTREQ_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RISCV_DM_DMSTATUS_CONFSTPTRVALID -// Description : 0: confstrptr0–confstrptr3 hold information which is not -// relevant to the configuration string. -// -// 1: confstrptr0–confstrptr3 hold the address of the -// configuration string. -#define RISCV_DM_DMSTATUS_CONFSTPTRVALID_RESET _u(0x0) -#define RISCV_DM_DMSTATUS_CONFSTPTRVALID_BITS _u(0x00000010) -#define RISCV_DM_DMSTATUS_CONFSTPTRVALID_MSB _u(4) -#define RISCV_DM_DMSTATUS_CONFSTPTRVALID_LSB _u(4) -#define RISCV_DM_DMSTATUS_CONFSTPTRVALID_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RISCV_DM_DMSTATUS_VERSION -// Description : 0: There is no Debug Module present. 1: There is a Debug Module -// and it conforms to version 0.11 of the RISC-V debug -// specification. -// -// 2: There is a Debug Module and it conforms to version 0.13 of -// the RISC-V debug specification. -// -// 15: There is a Debug Module but it does not con- form to any -// available version of the RISC-V debug spec. -#define RISCV_DM_DMSTATUS_VERSION_RESET _u(0x2) -#define RISCV_DM_DMSTATUS_VERSION_BITS _u(0x0000000f) -#define RISCV_DM_DMSTATUS_VERSION_MSB _u(3) -#define RISCV_DM_DMSTATUS_VERSION_LSB _u(0) -#define RISCV_DM_DMSTATUS_VERSION_ACCESS "RO" -// ============================================================================= -// Register : RISCV_DM_HARTINFO -// Description : This register gives information about the hart currently -// selected by hartsel. -// -// This entire register is read-only. -#define RISCV_DM_HARTINFO_OFFSET _u(0x00000048) -#define RISCV_DM_HARTINFO_BITS _u(0x00f1ffff) -#define RISCV_DM_HARTINFO_RESET _u(0x00001bff) -// ----------------------------------------------------------------------------- -// Field : RISCV_DM_HARTINFO_NSCRATCH -// Description : Number of dscratch registers available for the debugger to use -// during program buffer execution, starting from dscratch0. The -// debugger can make no assumptions about the contents of these -// registers between commands. -#define RISCV_DM_HARTINFO_NSCRATCH_RESET _u(0x0) -#define RISCV_DM_HARTINFO_NSCRATCH_BITS _u(0x00f00000) -#define RISCV_DM_HARTINFO_NSCRATCH_MSB _u(23) -#define RISCV_DM_HARTINFO_NSCRATCH_LSB _u(20) -#define RISCV_DM_HARTINFO_NSCRATCH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RISCV_DM_HARTINFO_DATAACCESS -// Description : 0: The data registers are shadowed in the hart by CSRs. Each -// CSR is DXLEN bits in size, and corresponds to a single -// argument. -// -// 1: The data registers are shadowed in the hart’s memory map. -// Each register takes up 4 bytes in the memory map. -#define RISCV_DM_HARTINFO_DATAACCESS_RESET _u(0x0) -#define RISCV_DM_HARTINFO_DATAACCESS_BITS _u(0x00010000) -#define RISCV_DM_HARTINFO_DATAACCESS_MSB _u(16) -#define RISCV_DM_HARTINFO_DATAACCESS_LSB _u(16) -#define RISCV_DM_HARTINFO_DATAACCESS_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RISCV_DM_HARTINFO_DATASIZE -// Description : If dataaccess is 0: Number of CSRs dedicated to shadowing the -// data registers. -// -// If dataaccess is 1: Number of 32-bit words in the memory map -// dedicated to shadowing the data registers. -#define RISCV_DM_HARTINFO_DATASIZE_RESET _u(0x1) -#define RISCV_DM_HARTINFO_DATASIZE_BITS _u(0x0000f000) -#define RISCV_DM_HARTINFO_DATASIZE_MSB _u(15) -#define RISCV_DM_HARTINFO_DATASIZE_LSB _u(12) -#define RISCV_DM_HARTINFO_DATASIZE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RISCV_DM_HARTINFO_DATAADDR -// Description : If dataaccess is 0: The number of the first CSR dedicated to -// shadowing the data registers. -// -// If dataaccess is 1: Signed address of RAM where the data -// registers are shadowed, to be used to access relative to zero -// -// On Hazard3 this indicates the single data register mapped as -// dmdata0. There is actually only a single shared register, -// internal to the Debug Module, and mirrored in each core's CSR -// space. -#define RISCV_DM_HARTINFO_DATAADDR_RESET _u(0xbff) -#define RISCV_DM_HARTINFO_DATAADDR_BITS _u(0x00000fff) -#define RISCV_DM_HARTINFO_DATAADDR_MSB _u(11) -#define RISCV_DM_HARTINFO_DATAADDR_LSB _u(0) -#define RISCV_DM_HARTINFO_DATAADDR_ACCESS "RW" -// ============================================================================= -// Register : RISCV_DM_HALTSUM1 -// Description : Each bit in this read-only register indicates whether any of a -// group of harts is halted or not. Unavailable/nonexistent harts -// are not considered to be halted. -// -// Each bit in haltsum1 is an OR reduction of 32 bits' worth of -// haltsum0. On RP2350, only the LSB is implemented. -#define RISCV_DM_HALTSUM1_OFFSET _u(0x0000004c) -#define RISCV_DM_HALTSUM1_BITS _u(0x00000001) -#define RISCV_DM_HALTSUM1_RESET _u(0x00000000) -#define RISCV_DM_HALTSUM1_MSB _u(0) -#define RISCV_DM_HALTSUM1_LSB _u(0) -#define RISCV_DM_HALTSUM1_ACCESS "RO" -// ============================================================================= -// Register : RISCV_DM_HAWINDOWSEL -// Description : This register selects which of the 32-bit portion of the hart -// array mask register is accessible in hawindow. -#define RISCV_DM_HAWINDOWSEL_OFFSET _u(0x00000050) -#define RISCV_DM_HAWINDOWSEL_BITS _u(0x00007fff) -#define RISCV_DM_HAWINDOWSEL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : RISCV_DM_HAWINDOWSEL_HAWINDOWSEL -// Description : On Hazard3 this register is entirely hardwired to 0. -#define RISCV_DM_HAWINDOWSEL_HAWINDOWSEL_RESET _u(0x0000) -#define RISCV_DM_HAWINDOWSEL_HAWINDOWSEL_BITS _u(0x00007fff) -#define RISCV_DM_HAWINDOWSEL_HAWINDOWSEL_MSB _u(14) -#define RISCV_DM_HAWINDOWSEL_HAWINDOWSEL_LSB _u(0) -#define RISCV_DM_HAWINDOWSEL_HAWINDOWSEL_ACCESS "RW" -// ============================================================================= -// Register : RISCV_DM_HAWINDOW -// Description : This register provides R/W access to a 32-bit portion of the -// hart array mask register. The position of the window is -// determined by hawindowsel. I.e. bit 0 refers to hart -// hawindowsel ∗ 32, while bit 31 refers to hart hawindowsel ∗ 32 -// + 31. -// -// On RP2350 only the two least-significant bits of this register -// are implemented, since there are only two cores. This is still -// useful to run/halt/reset both cores exactly simultaneously. -#define RISCV_DM_HAWINDOW_OFFSET _u(0x00000054) -#define RISCV_DM_HAWINDOW_BITS _u(0x00000003) -#define RISCV_DM_HAWINDOW_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : RISCV_DM_HAWINDOW_MASKDATA -#define RISCV_DM_HAWINDOW_MASKDATA_RESET _u(0x0) -#define RISCV_DM_HAWINDOW_MASKDATA_BITS _u(0x00000003) -#define RISCV_DM_HAWINDOW_MASKDATA_MSB _u(1) -#define RISCV_DM_HAWINDOW_MASKDATA_LSB _u(0) -#define RISCV_DM_HAWINDOW_MASKDATA_ACCESS "RW" -// ============================================================================= -// Register : RISCV_DM_ABSTRACTS -// Description : Abstract Control and Status. Writing this register while an -// abstract command is executing causes cmderr to be set to 1 -// (busy) if it is 0. -#define RISCV_DM_ABSTRACTS_OFFSET _u(0x00000058) -#define RISCV_DM_ABSTRACTS_BITS _u(0x1f00170f) -#define RISCV_DM_ABSTRACTS_RESET _u(0x02000001) -// ----------------------------------------------------------------------------- -// Field : RISCV_DM_ABSTRACTS_PROGBUFSIZE -// Description : Size of the Program Buffer, in 32-bit words. -#define RISCV_DM_ABSTRACTS_PROGBUFSIZE_RESET _u(0x02) -#define RISCV_DM_ABSTRACTS_PROGBUFSIZE_BITS _u(0x1f000000) -#define RISCV_DM_ABSTRACTS_PROGBUFSIZE_MSB _u(28) -#define RISCV_DM_ABSTRACTS_PROGBUFSIZE_LSB _u(24) -#define RISCV_DM_ABSTRACTS_PROGBUFSIZE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RISCV_DM_ABSTRACTS_BUSY -// Description : 1: An abstract command is currently being executed. -// -// This bit is set as soon as command is written, and is not -// cleared until that command has completed. -#define RISCV_DM_ABSTRACTS_BUSY_RESET _u(0x0) -#define RISCV_DM_ABSTRACTS_BUSY_BITS _u(0x00001000) -#define RISCV_DM_ABSTRACTS_BUSY_MSB _u(12) -#define RISCV_DM_ABSTRACTS_BUSY_LSB _u(12) -#define RISCV_DM_ABSTRACTS_BUSY_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RISCV_DM_ABSTRACTS_CMDERR -// Description : Gets set if an abstract command fails. The bits in this field -// remain set until they are cleared by writing 1 to them. No -// abstract command is started until the value is reset to 0. -// -// This field only contains a valid value if busy is 0. -// -// 0 (none): No error. -// -// 1 (busy): An abstract command was executing while command, -// abstractcs, or abstractauto was written, or when one of the -// data or progbuf registers was read or written. This status is -// only written if cmderr contains 0. -// -// 2 (not supported): The requested command is not supported, -// regardless of whether the hart is running or not. -// -// 3 (exception): An exception occurred while executing the -// command (e.g. while executing the Program Buffer). -// -// 4 (halt/resume): The abstract command couldn’t execute because -// the hart wasn’t in the required state (running/halted), or -// unavailable. -// -// 5 (bus): The abstract command failed due to a bus error (e.g. -// alignment, access size, or timeout). -// -// 7 (other): The command failed for another reason. -// -// Note: Hazard3 does not set values 5 or 7. Load/store -// instructions in the program buffer raise an exception when they -// encounter a bus fault, setting cmderr=3. -#define RISCV_DM_ABSTRACTS_CMDERR_RESET _u(0x0) -#define RISCV_DM_ABSTRACTS_CMDERR_BITS _u(0x00000700) -#define RISCV_DM_ABSTRACTS_CMDERR_MSB _u(10) -#define RISCV_DM_ABSTRACTS_CMDERR_LSB _u(8) -#define RISCV_DM_ABSTRACTS_CMDERR_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : RISCV_DM_ABSTRACTS_DATACOUNT -// Description : Number of data registers that are implemented as part of the -// abstract command interface. -#define RISCV_DM_ABSTRACTS_DATACOUNT_RESET _u(0x1) -#define RISCV_DM_ABSTRACTS_DATACOUNT_BITS _u(0x0000000f) -#define RISCV_DM_ABSTRACTS_DATACOUNT_MSB _u(3) -#define RISCV_DM_ABSTRACTS_DATACOUNT_LSB _u(0) -#define RISCV_DM_ABSTRACTS_DATACOUNT_ACCESS "RO" -// ============================================================================= -// Register : RISCV_DM_COMMAND -// Description : Writes to this register cause the corresponding abstract -// command to be executed. -// -// Writing this register while an abstract command is executing -// causes cmderr to be set to 1 (busy) if it is 0. -// -// If cmderr is non-zero, writes to this register are ignored. -#define RISCV_DM_COMMAND_OFFSET _u(0x0000005c) -#define RISCV_DM_COMMAND_BITS _u(0xff7fffff) -#define RISCV_DM_COMMAND_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : RISCV_DM_COMMAND_CMDTYPE -// Description : On Hazard3 this field must be 0 (Access Register) -#define RISCV_DM_COMMAND_CMDTYPE_RESET _u(0x00) -#define RISCV_DM_COMMAND_CMDTYPE_BITS _u(0xff000000) -#define RISCV_DM_COMMAND_CMDTYPE_MSB _u(31) -#define RISCV_DM_COMMAND_CMDTYPE_LSB _u(24) -#define RISCV_DM_COMMAND_CMDTYPE_ACCESS "WO" -// ----------------------------------------------------------------------------- -// Field : RISCV_DM_COMMAND_AARSIZE -// Description : On Hazard3 this field must be 2 (32-bit register access) -#define RISCV_DM_COMMAND_AARSIZE_RESET _u(0x0) -#define RISCV_DM_COMMAND_AARSIZE_BITS _u(0x00700000) -#define RISCV_DM_COMMAND_AARSIZE_MSB _u(22) -#define RISCV_DM_COMMAND_AARSIZE_LSB _u(20) -#define RISCV_DM_COMMAND_AARSIZE_ACCESS "WO" -// ----------------------------------------------------------------------------- -// Field : RISCV_DM_COMMAND_AARPOSTINCREMENT -// Description : On Hazard3 this field must be 0 (no post-increment of regno) -#define RISCV_DM_COMMAND_AARPOSTINCREMENT_RESET _u(0x0) -#define RISCV_DM_COMMAND_AARPOSTINCREMENT_BITS _u(0x00080000) -#define RISCV_DM_COMMAND_AARPOSTINCREMENT_MSB _u(19) -#define RISCV_DM_COMMAND_AARPOSTINCREMENT_LSB _u(19) -#define RISCV_DM_COMMAND_AARPOSTINCREMENT_ACCESS "WO" -// ----------------------------------------------------------------------------- -// Field : RISCV_DM_COMMAND_POSTEXEC -// Description : 0: No effect. -// -// 1: Execute the program in the Program Buffer exactly once after -// performing the transfer, if any. -#define RISCV_DM_COMMAND_POSTEXEC_RESET _u(0x0) -#define RISCV_DM_COMMAND_POSTEXEC_BITS _u(0x00040000) -#define RISCV_DM_COMMAND_POSTEXEC_MSB _u(18) -#define RISCV_DM_COMMAND_POSTEXEC_LSB _u(18) -#define RISCV_DM_COMMAND_POSTEXEC_ACCESS "WO" -// ----------------------------------------------------------------------------- -// Field : RISCV_DM_COMMAND_TRANSFER -// Description : 0: Don’t do the operation specified by write. -// -// 1: Do the operation specified by write. -// -// This bit can be used to just execute the Program Buffer without -// having to worry about placing valid values into aarsize or -// regno. -#define RISCV_DM_COMMAND_TRANSFER_RESET _u(0x0) -#define RISCV_DM_COMMAND_TRANSFER_BITS _u(0x00020000) -#define RISCV_DM_COMMAND_TRANSFER_MSB _u(17) -#define RISCV_DM_COMMAND_TRANSFER_LSB _u(17) -#define RISCV_DM_COMMAND_TRANSFER_ACCESS "WO" -// ----------------------------------------------------------------------------- -// Field : RISCV_DM_COMMAND_WRITE -// Description : When transfer is set: -// -// 0: Copy data from the specified register into data0. -// -// 1: Copy data from data0 into the specified register. -#define RISCV_DM_COMMAND_WRITE_RESET _u(0x0) -#define RISCV_DM_COMMAND_WRITE_BITS _u(0x00010000) -#define RISCV_DM_COMMAND_WRITE_MSB _u(16) -#define RISCV_DM_COMMAND_WRITE_LSB _u(16) -#define RISCV_DM_COMMAND_WRITE_ACCESS "WO" -// ----------------------------------------------------------------------------- -// Field : RISCV_DM_COMMAND_REGNO -// Description : Number of the register to access. -// -// On Hazard3 this must be in the range 0x1000 through 0x101f -// inclusive, referring to GPRs x0 through x31. -#define RISCV_DM_COMMAND_REGNO_RESET _u(0x0000) -#define RISCV_DM_COMMAND_REGNO_BITS _u(0x0000ffff) -#define RISCV_DM_COMMAND_REGNO_MSB _u(15) -#define RISCV_DM_COMMAND_REGNO_LSB _u(0) -#define RISCV_DM_COMMAND_REGNO_ACCESS "WO" -// ============================================================================= -// Register : RISCV_DM_ABSTRACTAUTO -// Description : Abstract Command Autoexec. Writing this register while an -// abstract command is executing causes cmderr to be set to 1 -// (busy) if it is 0. -#define RISCV_DM_ABSTRACTAUTO_OFFSET _u(0x00000060) -#define RISCV_DM_ABSTRACTAUTO_BITS _u(0xffff8fff) -#define RISCV_DM_ABSTRACTAUTO_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : RISCV_DM_ABSTRACTAUTO_AUTOEXECPROGBUF -// Description : When a bit in this field is 1, read or write accesses to the -// corresponding progbuf word cause the command in command to be -// executed again. -// -// Hazard3 implements only the two least-significant bits of this -// field (for the two-entry progbuf) -#define RISCV_DM_ABSTRACTAUTO_AUTOEXECPROGBUF_RESET _u(0x00000) -#define RISCV_DM_ABSTRACTAUTO_AUTOEXECPROGBUF_BITS _u(0xffff8000) -#define RISCV_DM_ABSTRACTAUTO_AUTOEXECPROGBUF_MSB _u(31) -#define RISCV_DM_ABSTRACTAUTO_AUTOEXECPROGBUF_LSB _u(15) -#define RISCV_DM_ABSTRACTAUTO_AUTOEXECPROGBUF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RISCV_DM_ABSTRACTAUTO_AUTOEXEDDATA -// Description : When a bit in this field is 1, read or write accesses to the -// corresponding data word cause the command in command to be -// executed again. -// -// Hazard3 implements only the least-significant bit of this -// field. -#define RISCV_DM_ABSTRACTAUTO_AUTOEXEDDATA_RESET _u(0x000) -#define RISCV_DM_ABSTRACTAUTO_AUTOEXEDDATA_BITS _u(0x00000fff) -#define RISCV_DM_ABSTRACTAUTO_AUTOEXEDDATA_MSB _u(11) -#define RISCV_DM_ABSTRACTAUTO_AUTOEXEDDATA_LSB _u(0) -#define RISCV_DM_ABSTRACTAUTO_AUTOEXEDDATA_ACCESS "RW" -// ============================================================================= -// Register : RISCV_DM_NEXTDM -// Description : If there is more than one DM accessible on this DMI, this -// register contains the base address of thenext one in the chain, -// or 0 if this is the last one in the chain. -#define RISCV_DM_NEXTDM_OFFSET _u(0x00000074) -#define RISCV_DM_NEXTDM_BITS _u(0xffffffff) -#define RISCV_DM_NEXTDM_RESET _u(0x00000000) -#define RISCV_DM_NEXTDM_MSB _u(31) -#define RISCV_DM_NEXTDM_LSB _u(0) -#define RISCV_DM_NEXTDM_ACCESS "RO" -// ============================================================================= -// Register : RISCV_DM_PROGBUF0 -// Description : progbuf0 through progbuf15 provide read/write access to the -// program buffer. abstractcs.progbufsize indicates how many of -// them are implemented starting at progbuf0, counting up. -// -// (Hazard3 implements a 2-word program buffer.) -#define RISCV_DM_PROGBUF0_OFFSET _u(0x00000080) -#define RISCV_DM_PROGBUF0_BITS _u(0xffffffff) -#define RISCV_DM_PROGBUF0_RESET _u(0x00000000) -#define RISCV_DM_PROGBUF0_MSB _u(31) -#define RISCV_DM_PROGBUF0_LSB _u(0) -#define RISCV_DM_PROGBUF0_ACCESS "RW" -// ============================================================================= -// Register : RISCV_DM_PROGBUF1 -// Description : progbuf0 through progbuf15 provide read/write access to the -// program buffer. abstractcs.progbufsize indicates how many of -// them are implemented starting at progbuf0, counting up. -// -// (Hazard3 implements a 2-word program buffer.) -#define RISCV_DM_PROGBUF1_OFFSET _u(0x00000084) -#define RISCV_DM_PROGBUF1_BITS _u(0xffffffff) -#define RISCV_DM_PROGBUF1_RESET _u(0x00000000) -#define RISCV_DM_PROGBUF1_MSB _u(31) -#define RISCV_DM_PROGBUF1_LSB _u(0) -#define RISCV_DM_PROGBUF1_ACCESS "RW" -// ============================================================================= -// Register : RISCV_DM_SBCS -// Description : System Bus Access Control and Status -#define RISCV_DM_SBCS_OFFSET _u(0x000000e0) -#define RISCV_DM_SBCS_BITS _u(0xe07fffff) -#define RISCV_DM_SBCS_RESET _u(0x20000407) -// ----------------------------------------------------------------------------- -// Field : RISCV_DM_SBCS_SBVERSION -// Description : 1: The System Bus interface conforms to version 0.13.2 of the -// RISC-V debug spec. -#define RISCV_DM_SBCS_SBVERSION_RESET _u(0x1) -#define RISCV_DM_SBCS_SBVERSION_BITS _u(0xe0000000) -#define RISCV_DM_SBCS_SBVERSION_MSB _u(31) -#define RISCV_DM_SBCS_SBVERSION_LSB _u(29) -#define RISCV_DM_SBCS_SBVERSION_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RISCV_DM_SBCS_SBBUSYERROR -// Description : Set when the debugger attempts to read data while a read is in -// progress, or when the debugger initiates a new access while one -// is already in progress (while sbbusy is set). It remains set -// until it’s explicitly cleared by the debugger. -// -// While this field is set, no more system bus accesses can be -// initiated by the Debug Module. -#define RISCV_DM_SBCS_SBBUSYERROR_RESET _u(0x0) -#define RISCV_DM_SBCS_SBBUSYERROR_BITS _u(0x00400000) -#define RISCV_DM_SBCS_SBBUSYERROR_MSB _u(22) -#define RISCV_DM_SBCS_SBBUSYERROR_LSB _u(22) -#define RISCV_DM_SBCS_SBBUSYERROR_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : RISCV_DM_SBCS_SBBUSY -// Description : When 1, indicates the system bus master is busy. (Whether the -// system bus itself is busy is related, but not the same thing.) -// This bit goes high immediately when a read or write is -// requested for any reason, and does not go low until the access -// is fully completed. -// -// Writes to sbcs while sbbusy is high result in undefined -// behavior. A debugger must not write to sbcs until it reads -// sbbusy as 0. -#define RISCV_DM_SBCS_SBBUSY_RESET _u(0x0) -#define RISCV_DM_SBCS_SBBUSY_BITS _u(0x00200000) -#define RISCV_DM_SBCS_SBBUSY_MSB _u(21) -#define RISCV_DM_SBCS_SBBUSY_LSB _u(21) -#define RISCV_DM_SBCS_SBBUSY_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RISCV_DM_SBCS_SBREADONADDR -// Description : When 1, every write to sbaddress0 automatically triggers a -// system bus read at the new address. -#define RISCV_DM_SBCS_SBREADONADDR_RESET _u(0x0) -#define RISCV_DM_SBCS_SBREADONADDR_BITS _u(0x00100000) -#define RISCV_DM_SBCS_SBREADONADDR_MSB _u(20) -#define RISCV_DM_SBCS_SBREADONADDR_LSB _u(20) -#define RISCV_DM_SBCS_SBREADONADDR_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RISCV_DM_SBCS_SBACCESS -// Description : Select the access size to use for system bus accesses. -// -// 0: 8-bit -// -// 1: 16-bit -// -// 2: 32-bit -// -// 3: 64-bit -// -// 4: 128-bit -// -// If sbaccess has an unsupported value when the DM starts a bus -// access, the access is not per formed and sberror is set to 4. -// (On Hazard3 the supported values are 8-bit, 16-bit and 32-bit.) -#define RISCV_DM_SBCS_SBACCESS_RESET _u(0x0) -#define RISCV_DM_SBCS_SBACCESS_BITS _u(0x000e0000) -#define RISCV_DM_SBCS_SBACCESS_MSB _u(19) -#define RISCV_DM_SBCS_SBACCESS_LSB _u(17) -#define RISCV_DM_SBCS_SBACCESS_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RISCV_DM_SBCS_SBAUTOINCREMENT -// Description : When 1, sbaddress is incremented by the access size (in bytes) -// selected in sbaccess after every system bus access. -#define RISCV_DM_SBCS_SBAUTOINCREMENT_RESET _u(0x0) -#define RISCV_DM_SBCS_SBAUTOINCREMENT_BITS _u(0x00010000) -#define RISCV_DM_SBCS_SBAUTOINCREMENT_MSB _u(16) -#define RISCV_DM_SBCS_SBAUTOINCREMENT_LSB _u(16) -#define RISCV_DM_SBCS_SBAUTOINCREMENT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RISCV_DM_SBCS_SBREADONDATA -// Description : When 1, every read from sbdata0 automatically triggers a system -// bus read at the (possibly auto- incremented) address. -#define RISCV_DM_SBCS_SBREADONDATA_RESET _u(0x0) -#define RISCV_DM_SBCS_SBREADONDATA_BITS _u(0x00008000) -#define RISCV_DM_SBCS_SBREADONDATA_MSB _u(15) -#define RISCV_DM_SBCS_SBREADONDATA_LSB _u(15) -#define RISCV_DM_SBCS_SBREADONDATA_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RISCV_DM_SBCS_SBERROR -// Description : When the Debug Module’s system bus master encounters an error, -// this field gets set. The bits in this field remain set until -// they are cleared by writing 1 to them. While this field is non- -// zero, no more system bus accesses can be initiated by the Debug -// Module. -// -// An implementation may report “Other” (7) for any error -// condition. (Hazard3 does not use this value for any errors.) -// -// 0: There was no bus error. -// -// 1: There was a timeout. -// -// 2: A bad address was accessed. -// -// 3: There was an alignment error. -// -// 4: An access of unsupported size was requested. -// -// 7: Other. -// -// Hazard3 raises an alignment error for any non-naturally-aligned -// bus transfer which would otherwise be a valid transfer. -#define RISCV_DM_SBCS_SBERROR_RESET _u(0x0) -#define RISCV_DM_SBCS_SBERROR_BITS _u(0x00007000) -#define RISCV_DM_SBCS_SBERROR_MSB _u(14) -#define RISCV_DM_SBCS_SBERROR_LSB _u(12) -#define RISCV_DM_SBCS_SBERROR_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : RISCV_DM_SBCS_SBASIZE -// Description : Width of system bus addresses in bits. (0 indicates there is no -// bus access support.) -#define RISCV_DM_SBCS_SBASIZE_RESET _u(0x20) -#define RISCV_DM_SBCS_SBASIZE_BITS _u(0x00000fe0) -#define RISCV_DM_SBCS_SBASIZE_MSB _u(11) -#define RISCV_DM_SBCS_SBASIZE_LSB _u(5) -#define RISCV_DM_SBCS_SBASIZE_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RISCV_DM_SBCS_SBACCESS128 -// Description : 1 when 128-bit system bus accesses are supported. -#define RISCV_DM_SBCS_SBACCESS128_RESET _u(0x0) -#define RISCV_DM_SBCS_SBACCESS128_BITS _u(0x00000010) -#define RISCV_DM_SBCS_SBACCESS128_MSB _u(4) -#define RISCV_DM_SBCS_SBACCESS128_LSB _u(4) -#define RISCV_DM_SBCS_SBACCESS128_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RISCV_DM_SBCS_SBACCESS64 -// Description : 1 when 64-bit system bus accesses are supported. -#define RISCV_DM_SBCS_SBACCESS64_RESET _u(0x0) -#define RISCV_DM_SBCS_SBACCESS64_BITS _u(0x00000008) -#define RISCV_DM_SBCS_SBACCESS64_MSB _u(3) -#define RISCV_DM_SBCS_SBACCESS64_LSB _u(3) -#define RISCV_DM_SBCS_SBACCESS64_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RISCV_DM_SBCS_SBACCESS32 -// Description : 1 when 32-bit system bus accesses are supported. -#define RISCV_DM_SBCS_SBACCESS32_RESET _u(0x1) -#define RISCV_DM_SBCS_SBACCESS32_BITS _u(0x00000004) -#define RISCV_DM_SBCS_SBACCESS32_MSB _u(2) -#define RISCV_DM_SBCS_SBACCESS32_LSB _u(2) -#define RISCV_DM_SBCS_SBACCESS32_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RISCV_DM_SBCS_SBACCESS16 -// Description : 1 when 16-bit system bus accesses are supported. -#define RISCV_DM_SBCS_SBACCESS16_RESET _u(0x1) -#define RISCV_DM_SBCS_SBACCESS16_BITS _u(0x00000002) -#define RISCV_DM_SBCS_SBACCESS16_MSB _u(1) -#define RISCV_DM_SBCS_SBACCESS16_LSB _u(1) -#define RISCV_DM_SBCS_SBACCESS16_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RISCV_DM_SBCS_SBACCESS8 -// Description : 1 when 8-bit system bus accesses are supported. -#define RISCV_DM_SBCS_SBACCESS8_RESET _u(0x1) -#define RISCV_DM_SBCS_SBACCESS8_BITS _u(0x00000001) -#define RISCV_DM_SBCS_SBACCESS8_MSB _u(0) -#define RISCV_DM_SBCS_SBACCESS8_LSB _u(0) -#define RISCV_DM_SBCS_SBACCESS8_ACCESS "RO" -// ============================================================================= -// Register : RISCV_DM_SBADDRESS0 -// Description : System Bus Address 31:0 -// -// When the system bus master is busy, writes to this register -// will set sbbusyerror and don’t do anything else. -// -// If sberror is 0, sbbusyerror is 0, and sbreadonaddr is set then -// writes to this register start the following: -// -// 1. Set sbbusy. -// -// 2. Perform a bus read from the new value of sbaddress. -// -// 3. If the read succeeded and sbautoincrement is set, increment -// sbaddress. -// -// 4. Clear sbbusy. -#define RISCV_DM_SBADDRESS0_OFFSET _u(0x000000e4) -#define RISCV_DM_SBADDRESS0_BITS _u(0xffffffff) -#define RISCV_DM_SBADDRESS0_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : RISCV_DM_SBADDRESS0_ADDRESS -// Description : Accesses bits 31:0 of the physical address in sbaddress. -#define RISCV_DM_SBADDRESS0_ADDRESS_RESET _u(0x00000000) -#define RISCV_DM_SBADDRESS0_ADDRESS_BITS _u(0xffffffff) -#define RISCV_DM_SBADDRESS0_ADDRESS_MSB _u(31) -#define RISCV_DM_SBADDRESS0_ADDRESS_LSB _u(0) -#define RISCV_DM_SBADDRESS0_ADDRESS_ACCESS "RW" -// ============================================================================= -// Register : RISCV_DM_SBDATA0 -// Description : System Bus Data 31:0 -// -// Any successful system bus read updates sbdata. If the width of -// the read access is less than the width of sbdata, the contents -// of the remaining high bits may take on any value. -// -// If sberror or sbbusyerror both aren’t 0 then accesses do -// nothing. -// -// If the bus master is busy then accesses set sbbusyerror, and -// don’t do anything else. Writes to this register start the -// following: -// -// 1. Set sbbusy. -// -// 2. Perform a bus write of the new value of sbdata to sbaddress. -// -// 3. If the write succeeded and sbautoincrement is set, increment -// sbaddress. -// -// 4. Clear sbbusy. -// -// Reads from this register start the following: -// -// 1. “Return” the data. -// -// 2. Set sbbusy. -// -// 3. If sbreadondata is set, perform a system bus read from the -// address contained in sbaddress, placing the result in sbdata. -// -// 4. If the read was successful, and sbautoincrement is set, -// increment sbaddress. -// -// 5. Clear sbbusy. -#define RISCV_DM_SBDATA0_OFFSET _u(0x000000f0) -#define RISCV_DM_SBDATA0_BITS _u(0xffffffff) -#define RISCV_DM_SBDATA0_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : RISCV_DM_SBDATA0_DATA -#define RISCV_DM_SBDATA0_DATA_RESET _u(0x00000000) -#define RISCV_DM_SBDATA0_DATA_BITS _u(0xffffffff) -#define RISCV_DM_SBDATA0_DATA_MSB _u(31) -#define RISCV_DM_SBDATA0_DATA_LSB _u(0) -#define RISCV_DM_SBDATA0_DATA_ACCESS "RW" -// ============================================================================= -// Register : RISCV_DM_HALTSUM0 -// Description : Each bit in this read-only register indicates whether one -// specific hart is halted or not. Unavailable/nonexistent harts -// are not considered to be halted. -// -// On RP2350, only the two LSBs of this register are implemented, -// one for each core/hart. -// -// This entire register is read-only. -#define RISCV_DM_HALTSUM0_OFFSET _u(0x00000100) -#define RISCV_DM_HALTSUM0_BITS _u(0xffffffff) -#define RISCV_DM_HALTSUM0_RESET _u(0x00000000) -#define RISCV_DM_HALTSUM0_MSB _u(31) -#define RISCV_DM_HALTSUM0_LSB _u(0) -#define RISCV_DM_HALTSUM0_ACCESS "RO" -// ============================================================================= -#endif // _HARDWARE_REGS_RISCV_DM_H - diff --git a/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/rosc.h b/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/rosc.h deleted file mode 100644 index 4865c2ee31..0000000000 --- a/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/rosc.h +++ /dev/null @@ -1,345 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -// ============================================================================= -// Register block : ROSC -// Version : 1 -// Bus type : apb -// ============================================================================= -#ifndef _HARDWARE_REGS_ROSC_H -#define _HARDWARE_REGS_ROSC_H -// ============================================================================= -// Register : ROSC_CTRL -// Description : Ring Oscillator control -#define ROSC_CTRL_OFFSET _u(0x00000000) -#define ROSC_CTRL_BITS _u(0x00ffffff) -#define ROSC_CTRL_RESET _u(0x00000aa0) -// ----------------------------------------------------------------------------- -// Field : ROSC_CTRL_ENABLE -// Description : On power-up this field is initialised to ENABLE -// The system clock must be switched to another source before -// setting this field to DISABLE otherwise the chip will lock up -// The 12-bit code is intended to give some protection against -// accidental writes. An invalid setting will enable the -// oscillator. -// 0xd1e -> DISABLE -// 0xfab -> ENABLE -#define ROSC_CTRL_ENABLE_RESET "-" -#define ROSC_CTRL_ENABLE_BITS _u(0x00fff000) -#define ROSC_CTRL_ENABLE_MSB _u(23) -#define ROSC_CTRL_ENABLE_LSB _u(12) -#define ROSC_CTRL_ENABLE_ACCESS "RW" -#define ROSC_CTRL_ENABLE_VALUE_DISABLE _u(0xd1e) -#define ROSC_CTRL_ENABLE_VALUE_ENABLE _u(0xfab) -// ----------------------------------------------------------------------------- -// Field : ROSC_CTRL_FREQ_RANGE -// Description : Controls the number of delay stages in the ROSC ring -// LOW uses stages 0 to 7 -// MEDIUM uses stages 2 to 7 -// HIGH uses stages 4 to 7 -// TOOHIGH uses stages 6 to 7 and should not be used because its -// frequency exceeds design specifications -// The clock output will not glitch when changing the range up one -// step at a time -// The clock output will glitch when changing the range down -// Note: the values here are gray coded which is why HIGH comes -// before TOOHIGH -// 0xfa4 -> LOW -// 0xfa5 -> MEDIUM -// 0xfa7 -> HIGH -// 0xfa6 -> TOOHIGH -#define ROSC_CTRL_FREQ_RANGE_RESET _u(0xaa0) -#define ROSC_CTRL_FREQ_RANGE_BITS _u(0x00000fff) -#define ROSC_CTRL_FREQ_RANGE_MSB _u(11) -#define ROSC_CTRL_FREQ_RANGE_LSB _u(0) -#define ROSC_CTRL_FREQ_RANGE_ACCESS "RW" -#define ROSC_CTRL_FREQ_RANGE_VALUE_LOW _u(0xfa4) -#define ROSC_CTRL_FREQ_RANGE_VALUE_MEDIUM _u(0xfa5) -#define ROSC_CTRL_FREQ_RANGE_VALUE_HIGH _u(0xfa7) -#define ROSC_CTRL_FREQ_RANGE_VALUE_TOOHIGH _u(0xfa6) -// ============================================================================= -// Register : ROSC_FREQA -// Description : The FREQA & FREQB registers control the frequency by -// controlling the drive strength of each stage -// The drive strength has 4 levels determined by the number of -// bits set -// Increasing the number of bits set increases the drive strength -// and increases the oscillation frequency -// 0 bits set is the default drive strength -// 1 bit set doubles the drive strength -// 2 bits set triples drive strength -// 3 bits set quadruples drive strength -// For frequency randomisation set both DS0_RANDOM=1 & -// DS1_RANDOM=1 -#define ROSC_FREQA_OFFSET _u(0x00000004) -#define ROSC_FREQA_BITS _u(0xffff77ff) -#define ROSC_FREQA_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : ROSC_FREQA_PASSWD -// Description : Set to 0x9696 to apply the settings -// Any other value in this field will set all drive strengths to 0 -// 0x9696 -> PASS -#define ROSC_FREQA_PASSWD_RESET _u(0x0000) -#define ROSC_FREQA_PASSWD_BITS _u(0xffff0000) -#define ROSC_FREQA_PASSWD_MSB _u(31) -#define ROSC_FREQA_PASSWD_LSB _u(16) -#define ROSC_FREQA_PASSWD_ACCESS "RW" -#define ROSC_FREQA_PASSWD_VALUE_PASS _u(0x9696) -// ----------------------------------------------------------------------------- -// Field : ROSC_FREQA_DS3 -// Description : Stage 3 drive strength -#define ROSC_FREQA_DS3_RESET _u(0x0) -#define ROSC_FREQA_DS3_BITS _u(0x00007000) -#define ROSC_FREQA_DS3_MSB _u(14) -#define ROSC_FREQA_DS3_LSB _u(12) -#define ROSC_FREQA_DS3_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ROSC_FREQA_DS2 -// Description : Stage 2 drive strength -#define ROSC_FREQA_DS2_RESET _u(0x0) -#define ROSC_FREQA_DS2_BITS _u(0x00000700) -#define ROSC_FREQA_DS2_MSB _u(10) -#define ROSC_FREQA_DS2_LSB _u(8) -#define ROSC_FREQA_DS2_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ROSC_FREQA_DS1_RANDOM -// Description : Randomises the stage 1 drive strength -#define ROSC_FREQA_DS1_RANDOM_RESET _u(0x0) -#define ROSC_FREQA_DS1_RANDOM_BITS _u(0x00000080) -#define ROSC_FREQA_DS1_RANDOM_MSB _u(7) -#define ROSC_FREQA_DS1_RANDOM_LSB _u(7) -#define ROSC_FREQA_DS1_RANDOM_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ROSC_FREQA_DS1 -// Description : Stage 1 drive strength -#define ROSC_FREQA_DS1_RESET _u(0x0) -#define ROSC_FREQA_DS1_BITS _u(0x00000070) -#define ROSC_FREQA_DS1_MSB _u(6) -#define ROSC_FREQA_DS1_LSB _u(4) -#define ROSC_FREQA_DS1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ROSC_FREQA_DS0_RANDOM -// Description : Randomises the stage 0 drive strength -#define ROSC_FREQA_DS0_RANDOM_RESET _u(0x0) -#define ROSC_FREQA_DS0_RANDOM_BITS _u(0x00000008) -#define ROSC_FREQA_DS0_RANDOM_MSB _u(3) -#define ROSC_FREQA_DS0_RANDOM_LSB _u(3) -#define ROSC_FREQA_DS0_RANDOM_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ROSC_FREQA_DS0 -// Description : Stage 0 drive strength -#define ROSC_FREQA_DS0_RESET _u(0x0) -#define ROSC_FREQA_DS0_BITS _u(0x00000007) -#define ROSC_FREQA_DS0_MSB _u(2) -#define ROSC_FREQA_DS0_LSB _u(0) -#define ROSC_FREQA_DS0_ACCESS "RW" -// ============================================================================= -// Register : ROSC_FREQB -// Description : For a detailed description see freqa register -#define ROSC_FREQB_OFFSET _u(0x00000008) -#define ROSC_FREQB_BITS _u(0xffff7777) -#define ROSC_FREQB_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : ROSC_FREQB_PASSWD -// Description : Set to 0x9696 to apply the settings -// Any other value in this field will set all drive strengths to 0 -// 0x9696 -> PASS -#define ROSC_FREQB_PASSWD_RESET _u(0x0000) -#define ROSC_FREQB_PASSWD_BITS _u(0xffff0000) -#define ROSC_FREQB_PASSWD_MSB _u(31) -#define ROSC_FREQB_PASSWD_LSB _u(16) -#define ROSC_FREQB_PASSWD_ACCESS "RW" -#define ROSC_FREQB_PASSWD_VALUE_PASS _u(0x9696) -// ----------------------------------------------------------------------------- -// Field : ROSC_FREQB_DS7 -// Description : Stage 7 drive strength -#define ROSC_FREQB_DS7_RESET _u(0x0) -#define ROSC_FREQB_DS7_BITS _u(0x00007000) -#define ROSC_FREQB_DS7_MSB _u(14) -#define ROSC_FREQB_DS7_LSB _u(12) -#define ROSC_FREQB_DS7_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ROSC_FREQB_DS6 -// Description : Stage 6 drive strength -#define ROSC_FREQB_DS6_RESET _u(0x0) -#define ROSC_FREQB_DS6_BITS _u(0x00000700) -#define ROSC_FREQB_DS6_MSB _u(10) -#define ROSC_FREQB_DS6_LSB _u(8) -#define ROSC_FREQB_DS6_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ROSC_FREQB_DS5 -// Description : Stage 5 drive strength -#define ROSC_FREQB_DS5_RESET _u(0x0) -#define ROSC_FREQB_DS5_BITS _u(0x00000070) -#define ROSC_FREQB_DS5_MSB _u(6) -#define ROSC_FREQB_DS5_LSB _u(4) -#define ROSC_FREQB_DS5_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ROSC_FREQB_DS4 -// Description : Stage 4 drive strength -#define ROSC_FREQB_DS4_RESET _u(0x0) -#define ROSC_FREQB_DS4_BITS _u(0x00000007) -#define ROSC_FREQB_DS4_MSB _u(2) -#define ROSC_FREQB_DS4_LSB _u(0) -#define ROSC_FREQB_DS4_ACCESS "RW" -// ============================================================================= -// Register : ROSC_RANDOM -// Description : Loads a value to the LFSR randomiser -#define ROSC_RANDOM_OFFSET _u(0x0000000c) -#define ROSC_RANDOM_BITS _u(0xffffffff) -#define ROSC_RANDOM_RESET _u(0x3f04b16d) -// ----------------------------------------------------------------------------- -// Field : ROSC_RANDOM_SEED -#define ROSC_RANDOM_SEED_RESET _u(0x3f04b16d) -#define ROSC_RANDOM_SEED_BITS _u(0xffffffff) -#define ROSC_RANDOM_SEED_MSB _u(31) -#define ROSC_RANDOM_SEED_LSB _u(0) -#define ROSC_RANDOM_SEED_ACCESS "RW" -// ============================================================================= -// Register : ROSC_DORMANT -// Description : Ring Oscillator pause control -// This is used to save power by pausing the ROSC -// On power-up this field is initialised to WAKE -// An invalid write will also select WAKE -// Warning: setup the irq before selecting dormant mode -// 0x636f6d61 -> dormant -// 0x77616b65 -> WAKE -#define ROSC_DORMANT_OFFSET _u(0x00000010) -#define ROSC_DORMANT_BITS _u(0xffffffff) -#define ROSC_DORMANT_RESET "-" -#define ROSC_DORMANT_MSB _u(31) -#define ROSC_DORMANT_LSB _u(0) -#define ROSC_DORMANT_ACCESS "RW" -#define ROSC_DORMANT_VALUE_DORMANT _u(0x636f6d61) -#define ROSC_DORMANT_VALUE_WAKE _u(0x77616b65) -// ============================================================================= -// Register : ROSC_DIV -// Description : Controls the output divider -// set to 0xaa00 + div where -// div = 0 divides by 128 -// div = 1-127 divides by div -// any other value sets div=128 -// this register resets to div=32 -// 0xaa00 -> PASS -#define ROSC_DIV_OFFSET _u(0x00000014) -#define ROSC_DIV_BITS _u(0x0000ffff) -#define ROSC_DIV_RESET "-" -#define ROSC_DIV_MSB _u(15) -#define ROSC_DIV_LSB _u(0) -#define ROSC_DIV_ACCESS "RW" -#define ROSC_DIV_VALUE_PASS _u(0xaa00) -// ============================================================================= -// Register : ROSC_PHASE -// Description : Controls the phase shifted output -#define ROSC_PHASE_OFFSET _u(0x00000018) -#define ROSC_PHASE_BITS _u(0x00000fff) -#define ROSC_PHASE_RESET _u(0x00000008) -// ----------------------------------------------------------------------------- -// Field : ROSC_PHASE_PASSWD -// Description : set to 0xaa -// any other value enables the output with shift=0 -#define ROSC_PHASE_PASSWD_RESET _u(0x00) -#define ROSC_PHASE_PASSWD_BITS _u(0x00000ff0) -#define ROSC_PHASE_PASSWD_MSB _u(11) -#define ROSC_PHASE_PASSWD_LSB _u(4) -#define ROSC_PHASE_PASSWD_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ROSC_PHASE_ENABLE -// Description : enable the phase-shifted output -// this can be changed on-the-fly -#define ROSC_PHASE_ENABLE_RESET _u(0x1) -#define ROSC_PHASE_ENABLE_BITS _u(0x00000008) -#define ROSC_PHASE_ENABLE_MSB _u(3) -#define ROSC_PHASE_ENABLE_LSB _u(3) -#define ROSC_PHASE_ENABLE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ROSC_PHASE_FLIP -// Description : invert the phase-shifted output -// this is ignored when div=1 -#define ROSC_PHASE_FLIP_RESET _u(0x0) -#define ROSC_PHASE_FLIP_BITS _u(0x00000004) -#define ROSC_PHASE_FLIP_MSB _u(2) -#define ROSC_PHASE_FLIP_LSB _u(2) -#define ROSC_PHASE_FLIP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : ROSC_PHASE_SHIFT -// Description : phase shift the phase-shifted output by SHIFT input clocks -// this can be changed on-the-fly -// must be set to 0 before setting div=1 -#define ROSC_PHASE_SHIFT_RESET _u(0x0) -#define ROSC_PHASE_SHIFT_BITS _u(0x00000003) -#define ROSC_PHASE_SHIFT_MSB _u(1) -#define ROSC_PHASE_SHIFT_LSB _u(0) -#define ROSC_PHASE_SHIFT_ACCESS "RW" -// ============================================================================= -// Register : ROSC_STATUS -// Description : Ring Oscillator Status -#define ROSC_STATUS_OFFSET _u(0x0000001c) -#define ROSC_STATUS_BITS _u(0x81011000) -#define ROSC_STATUS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : ROSC_STATUS_STABLE -// Description : Oscillator is running and stable -#define ROSC_STATUS_STABLE_RESET _u(0x0) -#define ROSC_STATUS_STABLE_BITS _u(0x80000000) -#define ROSC_STATUS_STABLE_MSB _u(31) -#define ROSC_STATUS_STABLE_LSB _u(31) -#define ROSC_STATUS_STABLE_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : ROSC_STATUS_BADWRITE -// Description : An invalid value has been written to CTRL_ENABLE or -// CTRL_FREQ_RANGE or FREQA or FREQB or DIV or PHASE or DORMANT -#define ROSC_STATUS_BADWRITE_RESET _u(0x0) -#define ROSC_STATUS_BADWRITE_BITS _u(0x01000000) -#define ROSC_STATUS_BADWRITE_MSB _u(24) -#define ROSC_STATUS_BADWRITE_LSB _u(24) -#define ROSC_STATUS_BADWRITE_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : ROSC_STATUS_DIV_RUNNING -// Description : post-divider is running -// this resets to 0 but transitions to 1 during chip startup -#define ROSC_STATUS_DIV_RUNNING_RESET "-" -#define ROSC_STATUS_DIV_RUNNING_BITS _u(0x00010000) -#define ROSC_STATUS_DIV_RUNNING_MSB _u(16) -#define ROSC_STATUS_DIV_RUNNING_LSB _u(16) -#define ROSC_STATUS_DIV_RUNNING_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : ROSC_STATUS_ENABLED -// Description : Oscillator is enabled but not necessarily running and stable -// this resets to 0 but transitions to 1 during chip startup -#define ROSC_STATUS_ENABLED_RESET "-" -#define ROSC_STATUS_ENABLED_BITS _u(0x00001000) -#define ROSC_STATUS_ENABLED_MSB _u(12) -#define ROSC_STATUS_ENABLED_LSB _u(12) -#define ROSC_STATUS_ENABLED_ACCESS "RO" -// ============================================================================= -// Register : ROSC_RANDOMBIT -// Description : This just reads the state of the oscillator output so -// randomness is compromised if the ring oscillator is stopped or -// run at a harmonic of the bus frequency -#define ROSC_RANDOMBIT_OFFSET _u(0x00000020) -#define ROSC_RANDOMBIT_BITS _u(0x00000001) -#define ROSC_RANDOMBIT_RESET _u(0x00000001) -#define ROSC_RANDOMBIT_MSB _u(0) -#define ROSC_RANDOMBIT_LSB _u(0) -#define ROSC_RANDOMBIT_ACCESS "RO" -// ============================================================================= -// Register : ROSC_COUNT -// Description : A down counter running at the ROSC frequency which counts to -// zero and stops. -// To start the counter write a non-zero value. -// Can be used for short software pauses when setting up time -// sensitive hardware. -#define ROSC_COUNT_OFFSET _u(0x00000024) -#define ROSC_COUNT_BITS _u(0x0000ffff) -#define ROSC_COUNT_RESET _u(0x00000000) -#define ROSC_COUNT_MSB _u(15) -#define ROSC_COUNT_LSB _u(0) -#define ROSC_COUNT_ACCESS "RW" -// ============================================================================= -#endif // _HARDWARE_REGS_ROSC_H - diff --git a/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/rp_ap.h b/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/rp_ap.h deleted file mode 100644 index ff45438c1f..0000000000 --- a/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/rp_ap.h +++ /dev/null @@ -1,729 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -// ============================================================================= -// Register block : RP_AP -// Version : 1 -// Bus type : apb -// ============================================================================= -#ifndef _HARDWARE_REGS_RP_AP_H -#define _HARDWARE_REGS_RP_AP_H -// ============================================================================= -// Register : RP_AP_CTRL -// Description : This register is primarily used for DFT but can also be used to -// overcome some power up problems. However, it should not be used -// to force power up of domains. Use DBG_POW_OVRD for that. -#define RP_AP_CTRL_OFFSET _u(0x00000000) -#define RP_AP_CTRL_BITS _u(0xc000007f) -#define RP_AP_CTRL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : RP_AP_CTRL_RESCUE_RESTART -// Description : Allows debug of boot problems by restarting the chip with -// minimal boot code execution. Write to 1 to put the chip in -// reset then write to 0 to restart the chip with the rescue flag -// set. The rescue flag is in the POWMAN_CHIP_RESET register and -// is read by boot code. The rescue flag is cleared by writing 0 -// to POWMAN_CHIP_RESET_RESCUE_FLAG or by resetting the chip by -// any means other than RESCUE_RESTART. -#define RP_AP_CTRL_RESCUE_RESTART_RESET _u(0x0) -#define RP_AP_CTRL_RESCUE_RESTART_BITS _u(0x80000000) -#define RP_AP_CTRL_RESCUE_RESTART_MSB _u(31) -#define RP_AP_CTRL_RESCUE_RESTART_LSB _u(31) -#define RP_AP_CTRL_RESCUE_RESTART_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RP_AP_CTRL_SPARE -// Description : Unused -#define RP_AP_CTRL_SPARE_RESET _u(0x0) -#define RP_AP_CTRL_SPARE_BITS _u(0x40000000) -#define RP_AP_CTRL_SPARE_MSB _u(30) -#define RP_AP_CTRL_SPARE_LSB _u(30) -#define RP_AP_CTRL_SPARE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RP_AP_CTRL_DBG_FRCE_GPIO_LPCK -// Description : Allows chip start-up when the Low Power Oscillator (LPOSC) is -// inoperative or malfunctioning and also allows the initial power -// sequencing rate to be adjusted. Write to 1 to force the LPOSC -// output to be driven from a GPIO (gpio20 on 80-pin package, -// gpio34 on the 60-pin package). If the LPOSC is inoperative or -// malfunctioning it may also be necessary to set the -// LPOSC_STABLE_FRCE bit in this register. The user must provide a -// clock on the GPIO. For normal operation use a clock running at -// around 32kHz. Adjusting the frequency will speed up or slow -// down the initial power-up sequence. -#define RP_AP_CTRL_DBG_FRCE_GPIO_LPCK_RESET _u(0x0) -#define RP_AP_CTRL_DBG_FRCE_GPIO_LPCK_BITS _u(0x00000040) -#define RP_AP_CTRL_DBG_FRCE_GPIO_LPCK_MSB _u(6) -#define RP_AP_CTRL_DBG_FRCE_GPIO_LPCK_LSB _u(6) -#define RP_AP_CTRL_DBG_FRCE_GPIO_LPCK_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RP_AP_CTRL_LPOSC_STABLE_FRCE -// Description : Allows the chip to start-up even though the Low Power -// Oscillator (LPOSC) is failing to set its stable flag. Initial -// power sequencing is clocked by LPOSC at around 32kHz but does -// not start until the LPOSC declares itself to be stable. If the -// LPOSC is otherwise working correctly the chip will boot when -// this bit is set. If the LPOSC is not working then -// DBG_FRCE_GPIO_LPCK must be set and an external clock provided. -#define RP_AP_CTRL_LPOSC_STABLE_FRCE_RESET _u(0x0) -#define RP_AP_CTRL_LPOSC_STABLE_FRCE_BITS _u(0x00000020) -#define RP_AP_CTRL_LPOSC_STABLE_FRCE_MSB _u(5) -#define RP_AP_CTRL_LPOSC_STABLE_FRCE_LSB _u(5) -#define RP_AP_CTRL_LPOSC_STABLE_FRCE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RP_AP_CTRL_POWMAN_DFT_ISO_OFF -// Description : Holds the isolation gates between power domains in the open -// state. This is intended to hold the gates open for DFT and -// power manager debug. It is not intended to force the isolation -// gates open. Use the overrides in DBG_POW_OVRD to force the -// isolation gates open or closed. -#define RP_AP_CTRL_POWMAN_DFT_ISO_OFF_RESET _u(0x0) -#define RP_AP_CTRL_POWMAN_DFT_ISO_OFF_BITS _u(0x00000010) -#define RP_AP_CTRL_POWMAN_DFT_ISO_OFF_MSB _u(4) -#define RP_AP_CTRL_POWMAN_DFT_ISO_OFF_LSB _u(4) -#define RP_AP_CTRL_POWMAN_DFT_ISO_OFF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RP_AP_CTRL_POWMAN_DFT_PWRON -// Description : Holds the power switches on for all domains. This is intended -// to keep the power on for DFT and debug, rather than for -// switching the power on. The power switches are not sequenced -// and the sudden demand for current could cause the always-on -// power domain to brown out. This register is in the always-on -// domain therefore chaos could ensue. It is recommended to use -// the DBG_POW_OVRD controls instead. -#define RP_AP_CTRL_POWMAN_DFT_PWRON_RESET _u(0x0) -#define RP_AP_CTRL_POWMAN_DFT_PWRON_BITS _u(0x00000008) -#define RP_AP_CTRL_POWMAN_DFT_PWRON_MSB _u(3) -#define RP_AP_CTRL_POWMAN_DFT_PWRON_LSB _u(3) -#define RP_AP_CTRL_POWMAN_DFT_PWRON_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RP_AP_CTRL_POWMAN_DBGMODE -// Description : This prevents the power manager from powering down and -// resetting the switched-core power domain. It is intended for -// DFT and for debugging the power manager after the chip has -// booted. It cannot be used to force initial power on because it -// simultaneously deasserts the reset. -#define RP_AP_CTRL_POWMAN_DBGMODE_RESET _u(0x0) -#define RP_AP_CTRL_POWMAN_DBGMODE_BITS _u(0x00000004) -#define RP_AP_CTRL_POWMAN_DBGMODE_MSB _u(2) -#define RP_AP_CTRL_POWMAN_DBGMODE_LSB _u(2) -#define RP_AP_CTRL_POWMAN_DBGMODE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RP_AP_CTRL_JTAG_FUNCSEL -// Description : Multiplexes the JTAG ports onto GPIO0-3 -#define RP_AP_CTRL_JTAG_FUNCSEL_RESET _u(0x0) -#define RP_AP_CTRL_JTAG_FUNCSEL_BITS _u(0x00000002) -#define RP_AP_CTRL_JTAG_FUNCSEL_MSB _u(1) -#define RP_AP_CTRL_JTAG_FUNCSEL_LSB _u(1) -#define RP_AP_CTRL_JTAG_FUNCSEL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RP_AP_CTRL_JTAG_TRSTN -// Description : Resets the JTAG module. Active low. -#define RP_AP_CTRL_JTAG_TRSTN_RESET _u(0x0) -#define RP_AP_CTRL_JTAG_TRSTN_BITS _u(0x00000001) -#define RP_AP_CTRL_JTAG_TRSTN_MSB _u(0) -#define RP_AP_CTRL_JTAG_TRSTN_LSB _u(0) -#define RP_AP_CTRL_JTAG_TRSTN_ACCESS "RW" -// ============================================================================= -// Register : RP_AP_DBGKEY -// Description : Serial key load interface (write-only) -#define RP_AP_DBGKEY_OFFSET _u(0x00000004) -#define RP_AP_DBGKEY_BITS _u(0x00000007) -#define RP_AP_DBGKEY_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : RP_AP_DBGKEY_RESET -// Description : Reset (before sending a new key) -#define RP_AP_DBGKEY_RESET_RESET _u(0x0) -#define RP_AP_DBGKEY_RESET_BITS _u(0x00000004) -#define RP_AP_DBGKEY_RESET_MSB _u(2) -#define RP_AP_DBGKEY_RESET_LSB _u(2) -#define RP_AP_DBGKEY_RESET_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RP_AP_DBGKEY_PUSH -#define RP_AP_DBGKEY_PUSH_RESET _u(0x0) -#define RP_AP_DBGKEY_PUSH_BITS _u(0x00000002) -#define RP_AP_DBGKEY_PUSH_MSB _u(1) -#define RP_AP_DBGKEY_PUSH_LSB _u(1) -#define RP_AP_DBGKEY_PUSH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RP_AP_DBGKEY_DATA -#define RP_AP_DBGKEY_DATA_RESET _u(0x0) -#define RP_AP_DBGKEY_DATA_BITS _u(0x00000001) -#define RP_AP_DBGKEY_DATA_MSB _u(0) -#define RP_AP_DBGKEY_DATA_LSB _u(0) -#define RP_AP_DBGKEY_DATA_ACCESS "RW" -// ============================================================================= -// Register : RP_AP_DBG_POW_STATE_SWCORE -// Description : This register indicates the state of the power sequencer for -// the switched-core domain. -// The sequencer timing is managed by the POWMAN_SEQ_* registers. -// See the header file for those registers for more information on -// the timing. -// Power up of the domain commences by clearing bit 0 (IS_PD) then -// bits 1-8 are set in sequence. Bit 8 (IS_PU) indicates the -// sequence is complete. -// Power down of the domain commences by clearing bit 8 (IS_PU) -// then bits 7-1 are cleared in sequence. Bit 0 (IS_PU) is then -// set to indicate the sequence is complete. -// Bits 9-11 describe the states of the power manager clocks which -// change as clock generators in the switched-core become -// available following switched-core power up. -// This bus can be sent to GPIO for debug. See -// DBG_POW_OUTPUT_TO_GPIO in the DBG_POW_OVRD register. -#define RP_AP_DBG_POW_STATE_SWCORE_OFFSET _u(0x00000008) -#define RP_AP_DBG_POW_STATE_SWCORE_BITS _u(0x00000fff) -#define RP_AP_DBG_POW_STATE_SWCORE_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : RP_AP_DBG_POW_STATE_SWCORE_USING_FAST_POWCK -// Description : Indicates the source of the power manager clock. On switched- -// core power up the clock switches from the LPOSC to clk_ref and -// this flag will be set. clk_ref will be running from the ROSC -// initially but will switch to XOSC when it comes available. On -// switched-core power down the clock switches to LPOSC and this -// flag will be cleared. -#define RP_AP_DBG_POW_STATE_SWCORE_USING_FAST_POWCK_RESET _u(0x0) -#define RP_AP_DBG_POW_STATE_SWCORE_USING_FAST_POWCK_BITS _u(0x00000800) -#define RP_AP_DBG_POW_STATE_SWCORE_USING_FAST_POWCK_MSB _u(11) -#define RP_AP_DBG_POW_STATE_SWCORE_USING_FAST_POWCK_LSB _u(11) -#define RP_AP_DBG_POW_STATE_SWCORE_USING_FAST_POWCK_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RP_AP_DBG_POW_STATE_SWCORE_WAITING_POWCK -// Description : Indicates the switched-core power sequencer is waiting for the -// power manager clock to update. On switched-core power up the -// clock switches from the LPOSC to clk_ref. clk_ref will be -// running from the ROSC initially but will switch to XOSC when it -// comes available. On switched-core power down the clock switches -// to LPOSC. -// If the switched-core power up sequence stalls with this flag -// active then it means clk_ref is not running which indicates a -// problem with the ROSC. If that happens then set -// DBG_POW_RESTART_FROM_XOSC in the DBG_POW_OVRD register to avoid -// using the ROSC. -// If the switched-core power down sequence stalls with this flag -// active then it means LPOSC is not running. The solution is to -// not stop LPOSC when the switched-core power domain is powered. -#define RP_AP_DBG_POW_STATE_SWCORE_WAITING_POWCK_RESET _u(0x0) -#define RP_AP_DBG_POW_STATE_SWCORE_WAITING_POWCK_BITS _u(0x00000400) -#define RP_AP_DBG_POW_STATE_SWCORE_WAITING_POWCK_MSB _u(10) -#define RP_AP_DBG_POW_STATE_SWCORE_WAITING_POWCK_LSB _u(10) -#define RP_AP_DBG_POW_STATE_SWCORE_WAITING_POWCK_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RP_AP_DBG_POW_STATE_SWCORE_WAITING_TIMCK -// Description : Indicates that the switched-core power sequencer is waiting for -// the AON-Timer to update. On switched-core power-up there is -// nothing to be done. The AON-Timer continues to run from the -// LPOSC so this flag will not be set. Software decides whether to -// switch the AON-Timer clock to XOSC (via clk_ref). On switched- -// core power-down the sequencer will switch the AON-Timer back to -// LPOSC if software switched it to XOSC. During the switchover -// the WAITING_TIMCK flag will be set. If the switched-core power -// down sequence stalls with this flag active then the only -// recourse is to reset the chip and change software to not select -// XOSC as the AON-Timer source. -#define RP_AP_DBG_POW_STATE_SWCORE_WAITING_TIMCK_RESET _u(0x0) -#define RP_AP_DBG_POW_STATE_SWCORE_WAITING_TIMCK_BITS _u(0x00000200) -#define RP_AP_DBG_POW_STATE_SWCORE_WAITING_TIMCK_MSB _u(9) -#define RP_AP_DBG_POW_STATE_SWCORE_WAITING_TIMCK_LSB _u(9) -#define RP_AP_DBG_POW_STATE_SWCORE_WAITING_TIMCK_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RP_AP_DBG_POW_STATE_SWCORE_IS_PU -// Description : Indicates the power somain is fully powered up. -#define RP_AP_DBG_POW_STATE_SWCORE_IS_PU_RESET _u(0x0) -#define RP_AP_DBG_POW_STATE_SWCORE_IS_PU_BITS _u(0x00000100) -#define RP_AP_DBG_POW_STATE_SWCORE_IS_PU_MSB _u(8) -#define RP_AP_DBG_POW_STATE_SWCORE_IS_PU_LSB _u(8) -#define RP_AP_DBG_POW_STATE_SWCORE_IS_PU_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RP_AP_DBG_POW_STATE_SWCORE_RESET_FROM_SEQ -// Description : Indicates the state of the reset to the power domain. -#define RP_AP_DBG_POW_STATE_SWCORE_RESET_FROM_SEQ_RESET _u(0x0) -#define RP_AP_DBG_POW_STATE_SWCORE_RESET_FROM_SEQ_BITS _u(0x00000080) -#define RP_AP_DBG_POW_STATE_SWCORE_RESET_FROM_SEQ_MSB _u(7) -#define RP_AP_DBG_POW_STATE_SWCORE_RESET_FROM_SEQ_LSB _u(7) -#define RP_AP_DBG_POW_STATE_SWCORE_RESET_FROM_SEQ_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RP_AP_DBG_POW_STATE_SWCORE_ENAB_ACK -// Description : Indicates the state of the enable to the power domain. -#define RP_AP_DBG_POW_STATE_SWCORE_ENAB_ACK_RESET _u(0x0) -#define RP_AP_DBG_POW_STATE_SWCORE_ENAB_ACK_BITS _u(0x00000040) -#define RP_AP_DBG_POW_STATE_SWCORE_ENAB_ACK_MSB _u(6) -#define RP_AP_DBG_POW_STATE_SWCORE_ENAB_ACK_LSB _u(6) -#define RP_AP_DBG_POW_STATE_SWCORE_ENAB_ACK_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RP_AP_DBG_POW_STATE_SWCORE_ISOLATE_FROM_SEQ -// Description : Indicates the state of the isolation control to the power -// domain. -#define RP_AP_DBG_POW_STATE_SWCORE_ISOLATE_FROM_SEQ_RESET _u(0x0) -#define RP_AP_DBG_POW_STATE_SWCORE_ISOLATE_FROM_SEQ_BITS _u(0x00000020) -#define RP_AP_DBG_POW_STATE_SWCORE_ISOLATE_FROM_SEQ_MSB _u(5) -#define RP_AP_DBG_POW_STATE_SWCORE_ISOLATE_FROM_SEQ_LSB _u(5) -#define RP_AP_DBG_POW_STATE_SWCORE_ISOLATE_FROM_SEQ_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RP_AP_DBG_POW_STATE_SWCORE_LARGE_ACK -// Description : Indicates the state of the large power switches for the power -// domain. -#define RP_AP_DBG_POW_STATE_SWCORE_LARGE_ACK_RESET _u(0x0) -#define RP_AP_DBG_POW_STATE_SWCORE_LARGE_ACK_BITS _u(0x00000010) -#define RP_AP_DBG_POW_STATE_SWCORE_LARGE_ACK_MSB _u(4) -#define RP_AP_DBG_POW_STATE_SWCORE_LARGE_ACK_LSB _u(4) -#define RP_AP_DBG_POW_STATE_SWCORE_LARGE_ACK_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK2 -// Description : The small switches are split into 3 chains. In the power up -// sequence they are switched on separately to allow management of -// the VDD rise time. In the power down sequence they switch off -// simultaneously with the large power switches. -// This bit indicates the state of the last element in small power -// switch chain 2. -#define RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK2_RESET _u(0x0) -#define RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK2_BITS _u(0x00000008) -#define RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK2_MSB _u(3) -#define RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK2_LSB _u(3) -#define RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK1 -// Description : This bit indicates the state of the last element in small power -// switch chain 1. -#define RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK1_RESET _u(0x0) -#define RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK1_BITS _u(0x00000004) -#define RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK1_MSB _u(2) -#define RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK1_LSB _u(2) -#define RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK0 -// Description : This bit indicates the state of the last element in small power -// switch chain 0. -#define RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK0_RESET _u(0x0) -#define RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK0_BITS _u(0x00000002) -#define RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK0_MSB _u(1) -#define RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK0_LSB _u(1) -#define RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK0_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RP_AP_DBG_POW_STATE_SWCORE_IS_PD -// Description : Indicates the power somain is fully powered down. -#define RP_AP_DBG_POW_STATE_SWCORE_IS_PD_RESET _u(0x0) -#define RP_AP_DBG_POW_STATE_SWCORE_IS_PD_BITS _u(0x00000001) -#define RP_AP_DBG_POW_STATE_SWCORE_IS_PD_MSB _u(0) -#define RP_AP_DBG_POW_STATE_SWCORE_IS_PD_LSB _u(0) -#define RP_AP_DBG_POW_STATE_SWCORE_IS_PD_ACCESS "RO" -// ============================================================================= -// Register : RP_AP_DBG_POW_STATE_XIP -// Description : This register indicates the state of the power sequencer for -// the XIP domain. -// The sequencer timing is managed by the POWMAN_SEQ_* registers. -// See the header file for those registers for more information on -// the timing. -// Power up of the domain commences by clearing bit 0 (IS_PD) then -// bits 1-8 are set in sequence. Bit 8 (IS_PU) indicates the -// sequence is complete. -// Power down of the domain commences by clearing bit 8 (IS_PU) -// then bits 7-1 are cleared in sequence. Bit 0 (IS_PU) is then -// set to indicate the sequence is complete. -#define RP_AP_DBG_POW_STATE_XIP_OFFSET _u(0x0000000c) -#define RP_AP_DBG_POW_STATE_XIP_BITS _u(0x000001ff) -#define RP_AP_DBG_POW_STATE_XIP_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : RP_AP_DBG_POW_STATE_XIP_IS_PU -// Description : Indicates the power somain is fully powered up. -#define RP_AP_DBG_POW_STATE_XIP_IS_PU_RESET _u(0x0) -#define RP_AP_DBG_POW_STATE_XIP_IS_PU_BITS _u(0x00000100) -#define RP_AP_DBG_POW_STATE_XIP_IS_PU_MSB _u(8) -#define RP_AP_DBG_POW_STATE_XIP_IS_PU_LSB _u(8) -#define RP_AP_DBG_POW_STATE_XIP_IS_PU_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RP_AP_DBG_POW_STATE_XIP_RESET_FROM_SEQ -// Description : Indicates the state of the reset to the power domain. -#define RP_AP_DBG_POW_STATE_XIP_RESET_FROM_SEQ_RESET _u(0x0) -#define RP_AP_DBG_POW_STATE_XIP_RESET_FROM_SEQ_BITS _u(0x00000080) -#define RP_AP_DBG_POW_STATE_XIP_RESET_FROM_SEQ_MSB _u(7) -#define RP_AP_DBG_POW_STATE_XIP_RESET_FROM_SEQ_LSB _u(7) -#define RP_AP_DBG_POW_STATE_XIP_RESET_FROM_SEQ_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RP_AP_DBG_POW_STATE_XIP_ENAB_ACK -// Description : Indicates the state of the enable to the power domain. -#define RP_AP_DBG_POW_STATE_XIP_ENAB_ACK_RESET _u(0x0) -#define RP_AP_DBG_POW_STATE_XIP_ENAB_ACK_BITS _u(0x00000040) -#define RP_AP_DBG_POW_STATE_XIP_ENAB_ACK_MSB _u(6) -#define RP_AP_DBG_POW_STATE_XIP_ENAB_ACK_LSB _u(6) -#define RP_AP_DBG_POW_STATE_XIP_ENAB_ACK_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RP_AP_DBG_POW_STATE_XIP_ISOLATE_FROM_SEQ -// Description : Indicates the state of the isolation control to the power -// domain. -#define RP_AP_DBG_POW_STATE_XIP_ISOLATE_FROM_SEQ_RESET _u(0x0) -#define RP_AP_DBG_POW_STATE_XIP_ISOLATE_FROM_SEQ_BITS _u(0x00000020) -#define RP_AP_DBG_POW_STATE_XIP_ISOLATE_FROM_SEQ_MSB _u(5) -#define RP_AP_DBG_POW_STATE_XIP_ISOLATE_FROM_SEQ_LSB _u(5) -#define RP_AP_DBG_POW_STATE_XIP_ISOLATE_FROM_SEQ_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RP_AP_DBG_POW_STATE_XIP_LARGE_ACK -// Description : Indicates the state of the large power switches for the power -// domain. -#define RP_AP_DBG_POW_STATE_XIP_LARGE_ACK_RESET _u(0x0) -#define RP_AP_DBG_POW_STATE_XIP_LARGE_ACK_BITS _u(0x00000010) -#define RP_AP_DBG_POW_STATE_XIP_LARGE_ACK_MSB _u(4) -#define RP_AP_DBG_POW_STATE_XIP_LARGE_ACK_LSB _u(4) -#define RP_AP_DBG_POW_STATE_XIP_LARGE_ACK_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RP_AP_DBG_POW_STATE_XIP_SMALL_ACK2 -// Description : The small switches are split into 3 chains. In the power up -// sequence they are switched on separately to allow management of -// the VDD rise time. In the power down sequence they switch off -// simultaneously with the large power switches. -// This bit indicates the state of the last element in small power -// switch chain 2. -#define RP_AP_DBG_POW_STATE_XIP_SMALL_ACK2_RESET _u(0x0) -#define RP_AP_DBG_POW_STATE_XIP_SMALL_ACK2_BITS _u(0x00000008) -#define RP_AP_DBG_POW_STATE_XIP_SMALL_ACK2_MSB _u(3) -#define RP_AP_DBG_POW_STATE_XIP_SMALL_ACK2_LSB _u(3) -#define RP_AP_DBG_POW_STATE_XIP_SMALL_ACK2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RP_AP_DBG_POW_STATE_XIP_SMALL_ACK1 -// Description : This bit indicates the state of the last element in small power -// switch chain 1. -#define RP_AP_DBG_POW_STATE_XIP_SMALL_ACK1_RESET _u(0x0) -#define RP_AP_DBG_POW_STATE_XIP_SMALL_ACK1_BITS _u(0x00000004) -#define RP_AP_DBG_POW_STATE_XIP_SMALL_ACK1_MSB _u(2) -#define RP_AP_DBG_POW_STATE_XIP_SMALL_ACK1_LSB _u(2) -#define RP_AP_DBG_POW_STATE_XIP_SMALL_ACK1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RP_AP_DBG_POW_STATE_XIP_SMALL_ACK0 -// Description : This bit indicates the state of the last element in small power -// switch chain 0. -#define RP_AP_DBG_POW_STATE_XIP_SMALL_ACK0_RESET _u(0x0) -#define RP_AP_DBG_POW_STATE_XIP_SMALL_ACK0_BITS _u(0x00000002) -#define RP_AP_DBG_POW_STATE_XIP_SMALL_ACK0_MSB _u(1) -#define RP_AP_DBG_POW_STATE_XIP_SMALL_ACK0_LSB _u(1) -#define RP_AP_DBG_POW_STATE_XIP_SMALL_ACK0_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RP_AP_DBG_POW_STATE_XIP_IS_PD -// Description : Indicates the power somain is fully powered down. -#define RP_AP_DBG_POW_STATE_XIP_IS_PD_RESET _u(0x0) -#define RP_AP_DBG_POW_STATE_XIP_IS_PD_BITS _u(0x00000001) -#define RP_AP_DBG_POW_STATE_XIP_IS_PD_MSB _u(0) -#define RP_AP_DBG_POW_STATE_XIP_IS_PD_LSB _u(0) -#define RP_AP_DBG_POW_STATE_XIP_IS_PD_ACCESS "RO" -// ============================================================================= -// Register : RP_AP_DBG_POW_STATE_SRAM0 -// Description : This register indicates the state of the power sequencer for -// the SRAM0 domain. -// The sequencer timing is managed by the POWMAN_SEQ_* registers. -// See the header file for those registers for more information on -// the timing. -// Power up of the domain commences by clearing bit 0 (IS_PD) then -// bits 1-8 are set in sequence. Bit 8 (IS_PU) indicates the -// sequence is complete. -// Power down of the domain commences by clearing bit 8 (IS_PU) -// then bits 7-1 are cleared in sequence. Bit 0 (IS_PU) is then -// set to indicate the sequence is complete. -#define RP_AP_DBG_POW_STATE_SRAM0_OFFSET _u(0x00000010) -#define RP_AP_DBG_POW_STATE_SRAM0_BITS _u(0x000001ff) -#define RP_AP_DBG_POW_STATE_SRAM0_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : RP_AP_DBG_POW_STATE_SRAM0_IS_PU -// Description : Indicates the power somain is fully powered up. -#define RP_AP_DBG_POW_STATE_SRAM0_IS_PU_RESET _u(0x0) -#define RP_AP_DBG_POW_STATE_SRAM0_IS_PU_BITS _u(0x00000100) -#define RP_AP_DBG_POW_STATE_SRAM0_IS_PU_MSB _u(8) -#define RP_AP_DBG_POW_STATE_SRAM0_IS_PU_LSB _u(8) -#define RP_AP_DBG_POW_STATE_SRAM0_IS_PU_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RP_AP_DBG_POW_STATE_SRAM0_RESET_FROM_SEQ -// Description : Indicates the state of the reset to the power domain. -#define RP_AP_DBG_POW_STATE_SRAM0_RESET_FROM_SEQ_RESET _u(0x0) -#define RP_AP_DBG_POW_STATE_SRAM0_RESET_FROM_SEQ_BITS _u(0x00000080) -#define RP_AP_DBG_POW_STATE_SRAM0_RESET_FROM_SEQ_MSB _u(7) -#define RP_AP_DBG_POW_STATE_SRAM0_RESET_FROM_SEQ_LSB _u(7) -#define RP_AP_DBG_POW_STATE_SRAM0_RESET_FROM_SEQ_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RP_AP_DBG_POW_STATE_SRAM0_ENAB_ACK -// Description : Indicates the state of the enable to the power domain. -#define RP_AP_DBG_POW_STATE_SRAM0_ENAB_ACK_RESET _u(0x0) -#define RP_AP_DBG_POW_STATE_SRAM0_ENAB_ACK_BITS _u(0x00000040) -#define RP_AP_DBG_POW_STATE_SRAM0_ENAB_ACK_MSB _u(6) -#define RP_AP_DBG_POW_STATE_SRAM0_ENAB_ACK_LSB _u(6) -#define RP_AP_DBG_POW_STATE_SRAM0_ENAB_ACK_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RP_AP_DBG_POW_STATE_SRAM0_ISOLATE_FROM_SEQ -// Description : Indicates the state of the isolation control to the power -// domain. -#define RP_AP_DBG_POW_STATE_SRAM0_ISOLATE_FROM_SEQ_RESET _u(0x0) -#define RP_AP_DBG_POW_STATE_SRAM0_ISOLATE_FROM_SEQ_BITS _u(0x00000020) -#define RP_AP_DBG_POW_STATE_SRAM0_ISOLATE_FROM_SEQ_MSB _u(5) -#define RP_AP_DBG_POW_STATE_SRAM0_ISOLATE_FROM_SEQ_LSB _u(5) -#define RP_AP_DBG_POW_STATE_SRAM0_ISOLATE_FROM_SEQ_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RP_AP_DBG_POW_STATE_SRAM0_LARGE_ACK -// Description : Indicates the state of the large power switches for the power -// domain. -#define RP_AP_DBG_POW_STATE_SRAM0_LARGE_ACK_RESET _u(0x0) -#define RP_AP_DBG_POW_STATE_SRAM0_LARGE_ACK_BITS _u(0x00000010) -#define RP_AP_DBG_POW_STATE_SRAM0_LARGE_ACK_MSB _u(4) -#define RP_AP_DBG_POW_STATE_SRAM0_LARGE_ACK_LSB _u(4) -#define RP_AP_DBG_POW_STATE_SRAM0_LARGE_ACK_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK2 -// Description : The small switches are split into 3 chains. In the power up -// sequence they are switched on separately to allow management of -// the VDD rise time. In the power down sequence they switch off -// simultaneously with the large power switches. -// This bit indicates the state of the last element in small power -// switch chain 2. -#define RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK2_RESET _u(0x0) -#define RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK2_BITS _u(0x00000008) -#define RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK2_MSB _u(3) -#define RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK2_LSB _u(3) -#define RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK1 -// Description : This bit indicates the state of the last element in small power -// switch chain 1. -#define RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK1_RESET _u(0x0) -#define RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK1_BITS _u(0x00000004) -#define RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK1_MSB _u(2) -#define RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK1_LSB _u(2) -#define RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK0 -// Description : This bit indicates the state of the last element in small power -// switch chain 0. -#define RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK0_RESET _u(0x0) -#define RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK0_BITS _u(0x00000002) -#define RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK0_MSB _u(1) -#define RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK0_LSB _u(1) -#define RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK0_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RP_AP_DBG_POW_STATE_SRAM0_IS_PD -// Description : Indicates the power somain is fully powered down. -#define RP_AP_DBG_POW_STATE_SRAM0_IS_PD_RESET _u(0x0) -#define RP_AP_DBG_POW_STATE_SRAM0_IS_PD_BITS _u(0x00000001) -#define RP_AP_DBG_POW_STATE_SRAM0_IS_PD_MSB _u(0) -#define RP_AP_DBG_POW_STATE_SRAM0_IS_PD_LSB _u(0) -#define RP_AP_DBG_POW_STATE_SRAM0_IS_PD_ACCESS "RO" -// ============================================================================= -// Register : RP_AP_DBG_POW_STATE_SRAM1 -// Description : This register indicates the state of the power sequencer for -// the SRAM1 domain. -// The sequencer timing is managed by the POWMAN_SEQ_* registers. -// See the header file for those registers for more information on -// the timing. -// Power up of the domain commences by clearing bit 0 (IS_PD) then -// bits 1-8 are set in sequence. Bit 8 (IS_PU) indicates the -// sequence is complete. -// Power down of the domain commences by clearing bit 8 (IS_PU) -// then bits 7-1 are cleared in sequence. Bit 0 (IS_PU) is then -// set to indicate the sequence is complete. -#define RP_AP_DBG_POW_STATE_SRAM1_OFFSET _u(0x00000014) -#define RP_AP_DBG_POW_STATE_SRAM1_BITS _u(0x000001ff) -#define RP_AP_DBG_POW_STATE_SRAM1_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : RP_AP_DBG_POW_STATE_SRAM1_IS_PU -// Description : Indicates the power somain is fully powered up. -#define RP_AP_DBG_POW_STATE_SRAM1_IS_PU_RESET _u(0x0) -#define RP_AP_DBG_POW_STATE_SRAM1_IS_PU_BITS _u(0x00000100) -#define RP_AP_DBG_POW_STATE_SRAM1_IS_PU_MSB _u(8) -#define RP_AP_DBG_POW_STATE_SRAM1_IS_PU_LSB _u(8) -#define RP_AP_DBG_POW_STATE_SRAM1_IS_PU_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RP_AP_DBG_POW_STATE_SRAM1_RESET_FROM_SEQ -// Description : Indicates the state of the reset to the power domain. -#define RP_AP_DBG_POW_STATE_SRAM1_RESET_FROM_SEQ_RESET _u(0x0) -#define RP_AP_DBG_POW_STATE_SRAM1_RESET_FROM_SEQ_BITS _u(0x00000080) -#define RP_AP_DBG_POW_STATE_SRAM1_RESET_FROM_SEQ_MSB _u(7) -#define RP_AP_DBG_POW_STATE_SRAM1_RESET_FROM_SEQ_LSB _u(7) -#define RP_AP_DBG_POW_STATE_SRAM1_RESET_FROM_SEQ_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RP_AP_DBG_POW_STATE_SRAM1_ENAB_ACK -// Description : Indicates the state of the enable to the power domain. -#define RP_AP_DBG_POW_STATE_SRAM1_ENAB_ACK_RESET _u(0x0) -#define RP_AP_DBG_POW_STATE_SRAM1_ENAB_ACK_BITS _u(0x00000040) -#define RP_AP_DBG_POW_STATE_SRAM1_ENAB_ACK_MSB _u(6) -#define RP_AP_DBG_POW_STATE_SRAM1_ENAB_ACK_LSB _u(6) -#define RP_AP_DBG_POW_STATE_SRAM1_ENAB_ACK_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RP_AP_DBG_POW_STATE_SRAM1_ISOLATE_FROM_SEQ -// Description : Indicates the state of the isolation control to the power -// domain. -#define RP_AP_DBG_POW_STATE_SRAM1_ISOLATE_FROM_SEQ_RESET _u(0x0) -#define RP_AP_DBG_POW_STATE_SRAM1_ISOLATE_FROM_SEQ_BITS _u(0x00000020) -#define RP_AP_DBG_POW_STATE_SRAM1_ISOLATE_FROM_SEQ_MSB _u(5) -#define RP_AP_DBG_POW_STATE_SRAM1_ISOLATE_FROM_SEQ_LSB _u(5) -#define RP_AP_DBG_POW_STATE_SRAM1_ISOLATE_FROM_SEQ_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RP_AP_DBG_POW_STATE_SRAM1_LARGE_ACK -// Description : Indicates the state of the large power switches for the power -// domain. -#define RP_AP_DBG_POW_STATE_SRAM1_LARGE_ACK_RESET _u(0x0) -#define RP_AP_DBG_POW_STATE_SRAM1_LARGE_ACK_BITS _u(0x00000010) -#define RP_AP_DBG_POW_STATE_SRAM1_LARGE_ACK_MSB _u(4) -#define RP_AP_DBG_POW_STATE_SRAM1_LARGE_ACK_LSB _u(4) -#define RP_AP_DBG_POW_STATE_SRAM1_LARGE_ACK_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK2 -// Description : The small switches are split into 3 chains. In the power up -// sequence they are switched on separately to allow management of -// the VDD rise time. In the power down sequence they switch off -// simultaneously with the large power switches. -// This bit indicates the state of the last element in small power -// switch chain 2. -#define RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK2_RESET _u(0x0) -#define RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK2_BITS _u(0x00000008) -#define RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK2_MSB _u(3) -#define RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK2_LSB _u(3) -#define RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK1 -// Description : This bit indicates the state of the last element in small power -// switch chain 1. -#define RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK1_RESET _u(0x0) -#define RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK1_BITS _u(0x00000004) -#define RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK1_MSB _u(2) -#define RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK1_LSB _u(2) -#define RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK0 -// Description : This bit indicates the state of the last element in small power -// switch chain 0. -#define RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK0_RESET _u(0x0) -#define RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK0_BITS _u(0x00000002) -#define RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK0_MSB _u(1) -#define RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK0_LSB _u(1) -#define RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK0_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RP_AP_DBG_POW_STATE_SRAM1_IS_PD -// Description : Indicates the power somain is fully powered down. -#define RP_AP_DBG_POW_STATE_SRAM1_IS_PD_RESET _u(0x0) -#define RP_AP_DBG_POW_STATE_SRAM1_IS_PD_BITS _u(0x00000001) -#define RP_AP_DBG_POW_STATE_SRAM1_IS_PD_MSB _u(0) -#define RP_AP_DBG_POW_STATE_SRAM1_IS_PD_LSB _u(0) -#define RP_AP_DBG_POW_STATE_SRAM1_IS_PD_ACCESS "RO" -// ============================================================================= -// Register : RP_AP_DBG_POW_OVRD -// Description : This register allows external control of the power sequencer -// outputs for all the switched power domains. If any of the power -// sequencers stall at any stage then force power up operation of -// all domains by running this sequence: -// - set DBG_POW_OVRD = 0x3b to force small power switches on, -// large power switches off, resets on and isolation on -// - allow time for the domain power supplies to reach full rail -// - set DBG_POW_OVRD = 0x3b to force large power switches on -// - set DBG_POW_OVRD = 0x37 to remove isolation -// - set DBG_POW_OVRD = 0x17 to remove resets -#define RP_AP_DBG_POW_OVRD_OFFSET _u(0x00000018) -#define RP_AP_DBG_POW_OVRD_BITS _u(0x0000007f) -#define RP_AP_DBG_POW_OVRD_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : RP_AP_DBG_POW_OVRD_DBG_POW_RESTART_FROM_XOSC -// Description : By default the system begins boot as soon as a clock is -// available from the ROSC, then it switches to the XOSC when it -// is available. This is done because the XOSC takes several ms to -// start up. If there is a problem with the ROSC then the default -// behaviour can be changed to not use the ROSC and wait for XOSC. -// However, this requires a mask change to modify the reset value -// of the Power Manager START_FROM_XOSC register. To allow -// experimentation the default can be temporarily changed by -// setting this register bit to 1. After setting this bit the core -// must be reset by a Coresight dprst or a rescue reset (see -// RESCUE_RESTART in the RP_AP_CTRL register above). A power-on -// reset, brown-out reset or RUN pin reset will reset this control -// and revert to the default behaviour. -#define RP_AP_DBG_POW_OVRD_DBG_POW_RESTART_FROM_XOSC_RESET _u(0x0) -#define RP_AP_DBG_POW_OVRD_DBG_POW_RESTART_FROM_XOSC_BITS _u(0x00000040) -#define RP_AP_DBG_POW_OVRD_DBG_POW_RESTART_FROM_XOSC_MSB _u(6) -#define RP_AP_DBG_POW_OVRD_DBG_POW_RESTART_FROM_XOSC_LSB _u(6) -#define RP_AP_DBG_POW_OVRD_DBG_POW_RESTART_FROM_XOSC_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RP_AP_DBG_POW_OVRD_DBG_POW_RESET -// Description : When DBG_POW_OVRD_RESET=1 this register bit controls the resets -// for all domains. 1 = reset. 0 = not reset. -#define RP_AP_DBG_POW_OVRD_DBG_POW_RESET_RESET _u(0x0) -#define RP_AP_DBG_POW_OVRD_DBG_POW_RESET_BITS _u(0x00000020) -#define RP_AP_DBG_POW_OVRD_DBG_POW_RESET_MSB _u(5) -#define RP_AP_DBG_POW_OVRD_DBG_POW_RESET_LSB _u(5) -#define RP_AP_DBG_POW_OVRD_DBG_POW_RESET_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_RESET -// Description : Enables DBG_POW_RESET to control the resets for the power -// manager and the switched-core. Essentially that is everythjing -// except the Coresight 2-wire interface and the RP_AP registers. -#define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_RESET_RESET _u(0x0) -#define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_RESET_BITS _u(0x00000010) -#define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_RESET_MSB _u(4) -#define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_RESET_LSB _u(4) -#define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_RESET_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RP_AP_DBG_POW_OVRD_DBG_POW_ISO -// Description : When DBG_POW_OVRD_ISO=1 this register bit controls the -// isolation gates for all domains. 1 = isolated. 0 = not -// isolated. -#define RP_AP_DBG_POW_OVRD_DBG_POW_ISO_RESET _u(0x0) -#define RP_AP_DBG_POW_OVRD_DBG_POW_ISO_BITS _u(0x00000008) -#define RP_AP_DBG_POW_OVRD_DBG_POW_ISO_MSB _u(3) -#define RP_AP_DBG_POW_OVRD_DBG_POW_ISO_LSB _u(3) -#define RP_AP_DBG_POW_OVRD_DBG_POW_ISO_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_ISO -// Description : Enables DBG_POW_ISO to control the isolation gates between -// domains. -#define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_ISO_RESET _u(0x0) -#define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_ISO_BITS _u(0x00000004) -#define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_ISO_MSB _u(2) -#define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_ISO_LSB _u(2) -#define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_ISO_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_LARGE_REQ -// Description : Turn on the large power switches for all domains. This should -// not be done until sufficient time has been allowed for the -// small switches to bring the supplies up. Switching the large -// switches on too soon risks browning out the always-on domain -// and corrupting these very registers. -#define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_LARGE_REQ_RESET _u(0x0) -#define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_LARGE_REQ_BITS _u(0x00000002) -#define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_LARGE_REQ_MSB _u(1) -#define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_LARGE_REQ_LSB _u(1) -#define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_LARGE_REQ_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_SMALL_REQ -// Description : Turn on the small power switches for all domains. This switches -// on chain 0 for each domain and switches off chains 2 & 3 and -// the large power switch chain. This will bring the power up for -// all domains without browning out the always-on power domain. -#define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_SMALL_REQ_RESET _u(0x0) -#define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_SMALL_REQ_BITS _u(0x00000001) -#define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_SMALL_REQ_MSB _u(0) -#define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_SMALL_REQ_LSB _u(0) -#define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_SMALL_REQ_ACCESS "RW" -// ============================================================================= -// Register : RP_AP_DBG_POW_OUTPUT_TO_GPIO -// Description : Send some, or all, bits of DBG_POW_STATE_SWCORE to gpios. -// Bit 0 sends bit 0 of DBG_POW_STATE_SWCORE to GPIO 34 -// Bit 1 sends bit 1 of DBG_POW_STATE_SWCORE to GPIO 35 -// Bit 2 sends bit 2 of DBG_POW_STATE_SWCORE to GPIO 36 -// . -// . -// Bit 11 sends bit 11 of DBG_POW_STATE_SWCORE to GPIO 45 -#define RP_AP_DBG_POW_OUTPUT_TO_GPIO_OFFSET _u(0x0000001c) -#define RP_AP_DBG_POW_OUTPUT_TO_GPIO_BITS _u(0x00000fff) -#define RP_AP_DBG_POW_OUTPUT_TO_GPIO_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : RP_AP_DBG_POW_OUTPUT_TO_GPIO_ENABLE -#define RP_AP_DBG_POW_OUTPUT_TO_GPIO_ENABLE_RESET _u(0x000) -#define RP_AP_DBG_POW_OUTPUT_TO_GPIO_ENABLE_BITS _u(0x00000fff) -#define RP_AP_DBG_POW_OUTPUT_TO_GPIO_ENABLE_MSB _u(11) -#define RP_AP_DBG_POW_OUTPUT_TO_GPIO_ENABLE_LSB _u(0) -#define RP_AP_DBG_POW_OUTPUT_TO_GPIO_ENABLE_ACCESS "RW" -// ============================================================================= -// Register : RP_AP_IDR -// Description : Standard Coresight ID Register -#define RP_AP_IDR_OFFSET _u(0x00000dfc) -#define RP_AP_IDR_BITS _u(0xffffffff) -#define RP_AP_IDR_RESET "-" -#define RP_AP_IDR_MSB _u(31) -#define RP_AP_IDR_LSB _u(0) -#define RP_AP_IDR_ACCESS "RO" -// ============================================================================= -#endif // _HARDWARE_REGS_RP_AP_H - diff --git a/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/rvcsr.h b/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/rvcsr.h deleted file mode 100644 index f5ff378ab7..0000000000 --- a/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/rvcsr.h +++ /dev/null @@ -1,3154 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -// ============================================================================= -// Register block : RVCSR -// Version : 1 -// Bus type : apb -// Description : CSR listing for Hazard3 -// ============================================================================= -#ifndef _HARDWARE_REGS_RVCSR_H -#define _HARDWARE_REGS_RVCSR_H -// ============================================================================= -// Register : RVCSR_MSTATUS -// Description : Machine status register -#define RVCSR_MSTATUS_OFFSET _u(0x00000300) -#define RVCSR_MSTATUS_BITS _u(0x00221888) -#define RVCSR_MSTATUS_RESET _u(0x00001800) -// ----------------------------------------------------------------------------- -// Field : RVCSR_MSTATUS_TW -// Description : Timeout wait. When 1, attempting to execute a WFI instruction -// in U-mode will instantly cause an illegal instruction -// exception. -#define RVCSR_MSTATUS_TW_RESET _u(0x0) -#define RVCSR_MSTATUS_TW_BITS _u(0x00200000) -#define RVCSR_MSTATUS_TW_MSB _u(21) -#define RVCSR_MSTATUS_TW_LSB _u(21) -#define RVCSR_MSTATUS_TW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RVCSR_MSTATUS_MPRV -// Description : Modify privilege. If 1, loads and stores behave as though the -// current privilege level were `mpp`. This includes physical -// memory protection checks, and the privilege level asserted on -// the system bus alongside the load/store address. -#define RVCSR_MSTATUS_MPRV_RESET _u(0x0) -#define RVCSR_MSTATUS_MPRV_BITS _u(0x00020000) -#define RVCSR_MSTATUS_MPRV_MSB _u(17) -#define RVCSR_MSTATUS_MPRV_LSB _u(17) -#define RVCSR_MSTATUS_MPRV_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RVCSR_MSTATUS_MPP -// Description : Previous privilege level. Can store the values 3 (M-mode) or 0 -// (U-mode). If another value is written, hardware rounds to the -// nearest supported mode. -#define RVCSR_MSTATUS_MPP_RESET _u(0x3) -#define RVCSR_MSTATUS_MPP_BITS _u(0x00001800) -#define RVCSR_MSTATUS_MPP_MSB _u(12) -#define RVCSR_MSTATUS_MPP_LSB _u(11) -#define RVCSR_MSTATUS_MPP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RVCSR_MSTATUS_MPIE -// Description : Previous interrupt enable. Readable and writable. Is set to the -// current value of `mstatus.mie` on trap entry. Is set to 1 on -// trap return. -#define RVCSR_MSTATUS_MPIE_RESET _u(0x0) -#define RVCSR_MSTATUS_MPIE_BITS _u(0x00000080) -#define RVCSR_MSTATUS_MPIE_MSB _u(7) -#define RVCSR_MSTATUS_MPIE_LSB _u(7) -#define RVCSR_MSTATUS_MPIE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RVCSR_MSTATUS_MIE -// Description : Interrupt enable. Readable and writable. Is set to 0 on trap -// entry. Is set to the current value of `mstatus.mpie` on trap -// return. -#define RVCSR_MSTATUS_MIE_RESET _u(0x0) -#define RVCSR_MSTATUS_MIE_BITS _u(0x00000008) -#define RVCSR_MSTATUS_MIE_MSB _u(3) -#define RVCSR_MSTATUS_MIE_LSB _u(3) -#define RVCSR_MSTATUS_MIE_ACCESS "RW" -// ============================================================================= -// Register : RVCSR_MISA -// Description : Summary of ISA extension support -// -// On RP2350, Hazard3's full `-march` string is: -// `rv32ima_zicsr_zifencei_zba_zbb_zbs_zbkb_zca_zcb_zcmp` -// -// Note Zca is equivalent to the C extension in this case; all -// instructions from the RISC-V C extension relevant to a 32-bit -// non-floating-point processor are supported. On older toolchains -// which do not support the Zc extensions, the appropriate -// `-march` string is: `rv32imac_zicsr_zifencei_zba_zbb_zbs_zbkb` -// -// In addition the following custom extensions are configured: -// Xh3bm, Xh3power, Xh3irq, Xh3pmpm -#define RVCSR_MISA_OFFSET _u(0x00000301) -#define RVCSR_MISA_BITS _u(0xc0901107) -#define RVCSR_MISA_RESET _u(0x40901105) -// ----------------------------------------------------------------------------- -// Field : RVCSR_MISA_MXL -// Description : Value of 0x1 indicates this is a 32-bit processor. -#define RVCSR_MISA_MXL_RESET _u(0x1) -#define RVCSR_MISA_MXL_BITS _u(0xc0000000) -#define RVCSR_MISA_MXL_MSB _u(31) -#define RVCSR_MISA_MXL_LSB _u(30) -#define RVCSR_MISA_MXL_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RVCSR_MISA_X -// Description : Value of 1 indicates nonstandard extensions are present. (Xh3b -// bit manipulation, and custom sleep and interrupt control CSRs) -#define RVCSR_MISA_X_RESET _u(0x1) -#define RVCSR_MISA_X_BITS _u(0x00800000) -#define RVCSR_MISA_X_MSB _u(23) -#define RVCSR_MISA_X_LSB _u(23) -#define RVCSR_MISA_X_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RVCSR_MISA_U -// Description : Value of 1 indicates U-mode is implemented. -#define RVCSR_MISA_U_RESET _u(0x1) -#define RVCSR_MISA_U_BITS _u(0x00100000) -#define RVCSR_MISA_U_MSB _u(20) -#define RVCSR_MISA_U_LSB _u(20) -#define RVCSR_MISA_U_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RVCSR_MISA_M -// Description : Value of 1 indicates the M extension (integer multiply/divide) -// is implemented. -#define RVCSR_MISA_M_RESET _u(0x1) -#define RVCSR_MISA_M_BITS _u(0x00001000) -#define RVCSR_MISA_M_MSB _u(12) -#define RVCSR_MISA_M_LSB _u(12) -#define RVCSR_MISA_M_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RVCSR_MISA_I -// Description : Value of 1 indicates the RVI base ISA is implemented (as -// opposed to RVE) -#define RVCSR_MISA_I_RESET _u(0x1) -#define RVCSR_MISA_I_BITS _u(0x00000100) -#define RVCSR_MISA_I_MSB _u(8) -#define RVCSR_MISA_I_LSB _u(8) -#define RVCSR_MISA_I_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RVCSR_MISA_C -// Description : Value of 1 indicates the C extension (compressed instructions) -// is implemented. -#define RVCSR_MISA_C_RESET _u(0x1) -#define RVCSR_MISA_C_BITS _u(0x00000004) -#define RVCSR_MISA_C_MSB _u(2) -#define RVCSR_MISA_C_LSB _u(2) -#define RVCSR_MISA_C_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RVCSR_MISA_B -// Description : Value of 1 indicates the B extension (bit manipulation) is -// implemented. B is the combination of Zba, Zbb and Zbs. -// -// Hazard3 implements all of these extensions, but the definition -// of B as ZbaZbbZbs did not exist at the point this version of -// Hazard3 was taped out. This bit was reserved-0 at that point. -// Therefore this bit reads as 0. -#define RVCSR_MISA_B_RESET _u(0x0) -#define RVCSR_MISA_B_BITS _u(0x00000002) -#define RVCSR_MISA_B_MSB _u(1) -#define RVCSR_MISA_B_LSB _u(1) -#define RVCSR_MISA_B_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RVCSR_MISA_A -// Description : Value of 1 indicates the A extension (atomics) is implemented. -#define RVCSR_MISA_A_RESET _u(0x1) -#define RVCSR_MISA_A_BITS _u(0x00000001) -#define RVCSR_MISA_A_MSB _u(0) -#define RVCSR_MISA_A_LSB _u(0) -#define RVCSR_MISA_A_ACCESS "RO" -// ============================================================================= -// Register : RVCSR_MEDELEG -// Description : Machine exception delegation register. Not implemented, as no -// S-mode support. -#define RVCSR_MEDELEG_OFFSET _u(0x00000302) -#define RVCSR_MEDELEG_BITS _u(0xffffffff) -#define RVCSR_MEDELEG_RESET "-" -#define RVCSR_MEDELEG_MSB _u(31) -#define RVCSR_MEDELEG_LSB _u(0) -#define RVCSR_MEDELEG_ACCESS "RW" -// ============================================================================= -// Register : RVCSR_MIDELEG -// Description : Machine interrupt delegation register. Not implemented, as no -// S-mode support. -#define RVCSR_MIDELEG_OFFSET _u(0x00000303) -#define RVCSR_MIDELEG_BITS _u(0xffffffff) -#define RVCSR_MIDELEG_RESET "-" -#define RVCSR_MIDELEG_MSB _u(31) -#define RVCSR_MIDELEG_LSB _u(0) -#define RVCSR_MIDELEG_ACCESS "RW" -// ============================================================================= -// Register : RVCSR_MIE -// Description : Machine interrupt enable register -#define RVCSR_MIE_OFFSET _u(0x00000304) -#define RVCSR_MIE_BITS _u(0x00000888) -#define RVCSR_MIE_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : RVCSR_MIE_MEIE -// Description : External interrupt enable. The processor transfers to the -// external interrupt vector when `mie.meie`, `mip.meip` and -// `mstatus.mie` are all 1. -// -// Hazard3 has internal registers to individually filter external -// interrupts (see `meiea`), but this standard control can be used -// to mask all external interrupts at once. -#define RVCSR_MIE_MEIE_RESET _u(0x0) -#define RVCSR_MIE_MEIE_BITS _u(0x00000800) -#define RVCSR_MIE_MEIE_MSB _u(11) -#define RVCSR_MIE_MEIE_LSB _u(11) -#define RVCSR_MIE_MEIE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RVCSR_MIE_MTIE -// Description : Timer interrupt enable. The processor transfers to the timer -// interrupt vector when `mie.mtie`, `mip.mtip` and `mstatus.mie` -// are all 1, unless a software or external interrupt request is -// also valid at this time. -#define RVCSR_MIE_MTIE_RESET _u(0x0) -#define RVCSR_MIE_MTIE_BITS _u(0x00000080) -#define RVCSR_MIE_MTIE_MSB _u(7) -#define RVCSR_MIE_MTIE_LSB _u(7) -#define RVCSR_MIE_MTIE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RVCSR_MIE_MSIE -// Description : Software interrupt enable. The processor transfers to the -// software interrupt vector `mie.msie`, `mip.msip` and -// `mstatus.mie` are all 1, unless an external interrupt request -// is also valid at this time. -#define RVCSR_MIE_MSIE_RESET _u(0x0) -#define RVCSR_MIE_MSIE_BITS _u(0x00000008) -#define RVCSR_MIE_MSIE_MSB _u(3) -#define RVCSR_MIE_MSIE_LSB _u(3) -#define RVCSR_MIE_MSIE_ACCESS "RW" -// ============================================================================= -// Register : RVCSR_MTVEC -// Description : Machine trap handler base address. -#define RVCSR_MTVEC_OFFSET _u(0x00000305) -#define RVCSR_MTVEC_BITS _u(0xffffffff) -#define RVCSR_MTVEC_RESET _u(0x00007ffc) -// ----------------------------------------------------------------------------- -// Field : RVCSR_MTVEC_BASE -// Description : The upper 30 bits of the trap vector address (2 LSBs are -// implicitly 0). Must be 64-byte-aligned if vectoring is enabled. -// Otherwise, must be 4-byte-aligned. -#define RVCSR_MTVEC_BASE_RESET _u(0x00001fff) -#define RVCSR_MTVEC_BASE_BITS _u(0xfffffffc) -#define RVCSR_MTVEC_BASE_MSB _u(31) -#define RVCSR_MTVEC_BASE_LSB _u(2) -#define RVCSR_MTVEC_BASE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RVCSR_MTVEC_MODE -// Description : If 0 (direct mode), all traps set pc to the trap vector base. -// If 1 (vectored), exceptions set pc to the trap vector base, and -// interrupts set pc to 4 times the interrupt cause (3=soft IRQ, -// 7=timer IRQ, 11=external IRQ). -// -// The upper bit is hardwired to zero, so attempting to set mode -// to 2 or 3 will result in a value of 0 or 1 respectively. -// 0x0 -> Direct entry to mtvec -// 0x1 -> Vectored entry to a 16-entry jump table starting at mtvec -#define RVCSR_MTVEC_MODE_RESET _u(0x0) -#define RVCSR_MTVEC_MODE_BITS _u(0x00000003) -#define RVCSR_MTVEC_MODE_MSB _u(1) -#define RVCSR_MTVEC_MODE_LSB _u(0) -#define RVCSR_MTVEC_MODE_ACCESS "RW" -#define RVCSR_MTVEC_MODE_VALUE_DIRECT _u(0x0) -#define RVCSR_MTVEC_MODE_VALUE_VECTORED _u(0x1) -// ============================================================================= -// Register : RVCSR_MCOUNTEREN -// Description : Counter enable. Control access to counters from U-mode. Not to -// be confused with mcountinhibit. -#define RVCSR_MCOUNTEREN_OFFSET _u(0x00000306) -#define RVCSR_MCOUNTEREN_BITS _u(0x00000007) -#define RVCSR_MCOUNTEREN_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : RVCSR_MCOUNTEREN_IR -// Description : If 1, U-mode is permitted to access the `instret`/`instreth` -// instruction retire counter CSRs. Otherwise, U-mode accesses to -// these CSRs will trap. -#define RVCSR_MCOUNTEREN_IR_RESET _u(0x0) -#define RVCSR_MCOUNTEREN_IR_BITS _u(0x00000004) -#define RVCSR_MCOUNTEREN_IR_MSB _u(2) -#define RVCSR_MCOUNTEREN_IR_LSB _u(2) -#define RVCSR_MCOUNTEREN_IR_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RVCSR_MCOUNTEREN_TM -// Description : No hardware effect, as the `time`/`timeh` CSRs are not -// implemented. However, this field still exists, as M-mode -// software can use it to track whether it should emulate U-mode -// attempts to access those CSRs. -#define RVCSR_MCOUNTEREN_TM_RESET _u(0x0) -#define RVCSR_MCOUNTEREN_TM_BITS _u(0x00000002) -#define RVCSR_MCOUNTEREN_TM_MSB _u(1) -#define RVCSR_MCOUNTEREN_TM_LSB _u(1) -#define RVCSR_MCOUNTEREN_TM_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RVCSR_MCOUNTEREN_CY -// Description : If 1, U-mode is permitted to access the `cycle`/`cycleh` cycle -// counter CSRs. Otherwise, U-mode accesses to these CSRs will -// trap. -#define RVCSR_MCOUNTEREN_CY_RESET _u(0x0) -#define RVCSR_MCOUNTEREN_CY_BITS _u(0x00000001) -#define RVCSR_MCOUNTEREN_CY_MSB _u(0) -#define RVCSR_MCOUNTEREN_CY_LSB _u(0) -#define RVCSR_MCOUNTEREN_CY_ACCESS "RW" -// ============================================================================= -// Register : RVCSR_MENVCFG -// Description : Machine environment configuration register, low half -#define RVCSR_MENVCFG_OFFSET _u(0x0000030a) -#define RVCSR_MENVCFG_BITS _u(0x00000001) -#define RVCSR_MENVCFG_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : RVCSR_MENVCFG_FIOM -// Description : When set, fence instructions in modes less privileged than -// M-mode which specify that IO memory accesses are ordered will -// also cause ordering of main memory accesses. -// -// FIOM is hardwired to zero on Hazard3, because S-mode is not -// supported, and because fence instructions execute as NOPs (with -// the exception of `fence.i`) -#define RVCSR_MENVCFG_FIOM_RESET _u(0x0) -#define RVCSR_MENVCFG_FIOM_BITS _u(0x00000001) -#define RVCSR_MENVCFG_FIOM_MSB _u(0) -#define RVCSR_MENVCFG_FIOM_LSB _u(0) -#define RVCSR_MENVCFG_FIOM_ACCESS "RO" -// ============================================================================= -// Register : RVCSR_MSTATUSH -// Description : High half of mstatus, hardwired to 0. -#define RVCSR_MSTATUSH_OFFSET _u(0x00000310) -#define RVCSR_MSTATUSH_BITS _u(0xffffffff) -#define RVCSR_MSTATUSH_RESET _u(0x00000000) -#define RVCSR_MSTATUSH_MSB _u(31) -#define RVCSR_MSTATUSH_LSB _u(0) -#define RVCSR_MSTATUSH_ACCESS "RO" -// ============================================================================= -// Register : RVCSR_MENVCFGH -// Description : Machine environment configuration register, high half -// -// This register is fully reserved, as Hazard3 does not implement -// the relevant extensions. It is implemented as hardwired-0. -#define RVCSR_MENVCFGH_OFFSET _u(0x0000031a) -#define RVCSR_MENVCFGH_BITS _u(0x00000000) -#define RVCSR_MENVCFGH_RESET _u(0x00000000) -#define RVCSR_MENVCFGH_MSB _u(31) -#define RVCSR_MENVCFGH_LSB _u(0) -#define RVCSR_MENVCFGH_ACCESS "RW" -// ============================================================================= -// Register : RVCSR_MCOUNTINHIBIT -// Description : Count inhibit register for `mcycle`/`minstret` -#define RVCSR_MCOUNTINHIBIT_OFFSET _u(0x00000320) -#define RVCSR_MCOUNTINHIBIT_BITS _u(0x00000005) -#define RVCSR_MCOUNTINHIBIT_RESET _u(0x00000005) -// ----------------------------------------------------------------------------- -// Field : RVCSR_MCOUNTINHIBIT_IR -// Description : Inhibit counting of the `minstret` and `minstreth` registers. -// Set by default to save power. -#define RVCSR_MCOUNTINHIBIT_IR_RESET _u(0x1) -#define RVCSR_MCOUNTINHIBIT_IR_BITS _u(0x00000004) -#define RVCSR_MCOUNTINHIBIT_IR_MSB _u(2) -#define RVCSR_MCOUNTINHIBIT_IR_LSB _u(2) -#define RVCSR_MCOUNTINHIBIT_IR_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RVCSR_MCOUNTINHIBIT_CY -// Description : Inhibit counting of the `mcycle` and `mcycleh` registers. Set -// by default to save power. -#define RVCSR_MCOUNTINHIBIT_CY_RESET _u(0x1) -#define RVCSR_MCOUNTINHIBIT_CY_BITS _u(0x00000001) -#define RVCSR_MCOUNTINHIBIT_CY_MSB _u(0) -#define RVCSR_MCOUNTINHIBIT_CY_LSB _u(0) -#define RVCSR_MCOUNTINHIBIT_CY_ACCESS "RW" -// ============================================================================= -// Register : RVCSR_MHPMEVENT3 -// Description : Extended performance event selector, hardwired to 0. -#define RVCSR_MHPMEVENT3_OFFSET _u(0x00000323) -#define RVCSR_MHPMEVENT3_BITS _u(0xffffffff) -#define RVCSR_MHPMEVENT3_RESET _u(0x00000000) -#define RVCSR_MHPMEVENT3_MSB _u(31) -#define RVCSR_MHPMEVENT3_LSB _u(0) -#define RVCSR_MHPMEVENT3_ACCESS "RO" -// ============================================================================= -// Register : RVCSR_MHPMEVENT4 -// Description : Extended performance event selector, hardwired to 0. -#define RVCSR_MHPMEVENT4_OFFSET _u(0x00000324) -#define RVCSR_MHPMEVENT4_BITS _u(0xffffffff) -#define RVCSR_MHPMEVENT4_RESET _u(0x00000000) -#define RVCSR_MHPMEVENT4_MSB _u(31) -#define RVCSR_MHPMEVENT4_LSB _u(0) -#define RVCSR_MHPMEVENT4_ACCESS "RO" -// ============================================================================= -// Register : RVCSR_MHPMEVENT5 -// Description : Extended performance event selector, hardwired to 0. -#define RVCSR_MHPMEVENT5_OFFSET _u(0x00000325) -#define RVCSR_MHPMEVENT5_BITS _u(0xffffffff) -#define RVCSR_MHPMEVENT5_RESET _u(0x00000000) -#define RVCSR_MHPMEVENT5_MSB _u(31) -#define RVCSR_MHPMEVENT5_LSB _u(0) -#define RVCSR_MHPMEVENT5_ACCESS "RO" -// ============================================================================= -// Register : RVCSR_MHPMEVENT6 -// Description : Extended performance event selector, hardwired to 0. -#define RVCSR_MHPMEVENT6_OFFSET _u(0x00000326) -#define RVCSR_MHPMEVENT6_BITS _u(0xffffffff) -#define RVCSR_MHPMEVENT6_RESET _u(0x00000000) -#define RVCSR_MHPMEVENT6_MSB _u(31) -#define RVCSR_MHPMEVENT6_LSB _u(0) -#define RVCSR_MHPMEVENT6_ACCESS "RO" -// ============================================================================= -// Register : RVCSR_MHPMEVENT7 -// Description : Extended performance event selector, hardwired to 0. -#define RVCSR_MHPMEVENT7_OFFSET _u(0x00000327) -#define RVCSR_MHPMEVENT7_BITS _u(0xffffffff) -#define RVCSR_MHPMEVENT7_RESET _u(0x00000000) -#define RVCSR_MHPMEVENT7_MSB _u(31) -#define RVCSR_MHPMEVENT7_LSB _u(0) -#define RVCSR_MHPMEVENT7_ACCESS "RO" -// ============================================================================= -// Register : RVCSR_MHPMEVENT8 -// Description : Extended performance event selector, hardwired to 0. -#define RVCSR_MHPMEVENT8_OFFSET _u(0x00000328) -#define RVCSR_MHPMEVENT8_BITS _u(0xffffffff) -#define RVCSR_MHPMEVENT8_RESET _u(0x00000000) -#define RVCSR_MHPMEVENT8_MSB _u(31) -#define RVCSR_MHPMEVENT8_LSB _u(0) -#define RVCSR_MHPMEVENT8_ACCESS "RO" -// ============================================================================= -// Register : RVCSR_MHPMEVENT9 -// Description : Extended performance event selector, hardwired to 0. -#define RVCSR_MHPMEVENT9_OFFSET _u(0x00000329) -#define RVCSR_MHPMEVENT9_BITS _u(0xffffffff) -#define RVCSR_MHPMEVENT9_RESET _u(0x00000000) -#define RVCSR_MHPMEVENT9_MSB _u(31) -#define RVCSR_MHPMEVENT9_LSB _u(0) -#define RVCSR_MHPMEVENT9_ACCESS "RO" -// ============================================================================= -// Register : RVCSR_MHPMEVENT10 -// Description : Extended performance event selector, hardwired to 0. -#define RVCSR_MHPMEVENT10_OFFSET _u(0x0000032a) -#define RVCSR_MHPMEVENT10_BITS _u(0xffffffff) -#define RVCSR_MHPMEVENT10_RESET _u(0x00000000) -#define RVCSR_MHPMEVENT10_MSB _u(31) -#define RVCSR_MHPMEVENT10_LSB _u(0) -#define RVCSR_MHPMEVENT10_ACCESS "RO" -// ============================================================================= -// Register : RVCSR_MHPMEVENT11 -// Description : Extended performance event selector, hardwired to 0. -#define RVCSR_MHPMEVENT11_OFFSET _u(0x0000032b) -#define RVCSR_MHPMEVENT11_BITS _u(0xffffffff) -#define RVCSR_MHPMEVENT11_RESET _u(0x00000000) -#define RVCSR_MHPMEVENT11_MSB _u(31) -#define RVCSR_MHPMEVENT11_LSB _u(0) -#define RVCSR_MHPMEVENT11_ACCESS "RO" -// ============================================================================= -// Register : RVCSR_MHPMEVENT12 -// Description : Extended performance event selector, hardwired to 0. -#define RVCSR_MHPMEVENT12_OFFSET _u(0x0000032c) -#define RVCSR_MHPMEVENT12_BITS _u(0xffffffff) -#define RVCSR_MHPMEVENT12_RESET _u(0x00000000) -#define RVCSR_MHPMEVENT12_MSB _u(31) -#define RVCSR_MHPMEVENT12_LSB _u(0) -#define RVCSR_MHPMEVENT12_ACCESS "RO" -// ============================================================================= -// Register : RVCSR_MHPMEVENT13 -// Description : Extended performance event selector, hardwired to 0. -#define RVCSR_MHPMEVENT13_OFFSET _u(0x0000032d) -#define RVCSR_MHPMEVENT13_BITS _u(0xffffffff) -#define RVCSR_MHPMEVENT13_RESET _u(0x00000000) -#define RVCSR_MHPMEVENT13_MSB _u(31) -#define RVCSR_MHPMEVENT13_LSB _u(0) -#define RVCSR_MHPMEVENT13_ACCESS "RO" -// ============================================================================= -// Register : RVCSR_MHPMEVENT14 -// Description : Extended performance event selector, hardwired to 0. -#define RVCSR_MHPMEVENT14_OFFSET _u(0x0000032e) -#define RVCSR_MHPMEVENT14_BITS _u(0xffffffff) -#define RVCSR_MHPMEVENT14_RESET _u(0x00000000) -#define RVCSR_MHPMEVENT14_MSB _u(31) -#define RVCSR_MHPMEVENT14_LSB _u(0) -#define RVCSR_MHPMEVENT14_ACCESS "RO" -// ============================================================================= -// Register : RVCSR_MHPMEVENT15 -// Description : Extended performance event selector, hardwired to 0. -#define RVCSR_MHPMEVENT15_OFFSET _u(0x0000032f) -#define RVCSR_MHPMEVENT15_BITS _u(0xffffffff) -#define RVCSR_MHPMEVENT15_RESET _u(0x00000000) -#define RVCSR_MHPMEVENT15_MSB _u(31) -#define RVCSR_MHPMEVENT15_LSB _u(0) -#define RVCSR_MHPMEVENT15_ACCESS "RO" -// ============================================================================= -// Register : RVCSR_MHPMEVENT16 -// Description : Extended performance event selector, hardwired to 0. -#define RVCSR_MHPMEVENT16_OFFSET _u(0x00000330) -#define RVCSR_MHPMEVENT16_BITS _u(0xffffffff) -#define RVCSR_MHPMEVENT16_RESET _u(0x00000000) -#define RVCSR_MHPMEVENT16_MSB _u(31) -#define RVCSR_MHPMEVENT16_LSB _u(0) -#define RVCSR_MHPMEVENT16_ACCESS "RO" -// ============================================================================= -// Register : RVCSR_MHPMEVENT17 -// Description : Extended performance event selector, hardwired to 0. -#define RVCSR_MHPMEVENT17_OFFSET _u(0x00000331) -#define RVCSR_MHPMEVENT17_BITS _u(0xffffffff) -#define RVCSR_MHPMEVENT17_RESET _u(0x00000000) -#define RVCSR_MHPMEVENT17_MSB _u(31) -#define RVCSR_MHPMEVENT17_LSB _u(0) -#define RVCSR_MHPMEVENT17_ACCESS "RO" -// ============================================================================= -// Register : RVCSR_MHPMEVENT18 -// Description : Extended performance event selector, hardwired to 0. -#define RVCSR_MHPMEVENT18_OFFSET _u(0x00000332) -#define RVCSR_MHPMEVENT18_BITS _u(0xffffffff) -#define RVCSR_MHPMEVENT18_RESET _u(0x00000000) -#define RVCSR_MHPMEVENT18_MSB _u(31) -#define RVCSR_MHPMEVENT18_LSB _u(0) -#define RVCSR_MHPMEVENT18_ACCESS "RO" -// ============================================================================= -// Register : RVCSR_MHPMEVENT19 -// Description : Extended performance event selector, hardwired to 0. -#define RVCSR_MHPMEVENT19_OFFSET _u(0x00000333) -#define RVCSR_MHPMEVENT19_BITS _u(0xffffffff) -#define RVCSR_MHPMEVENT19_RESET _u(0x00000000) -#define RVCSR_MHPMEVENT19_MSB _u(31) -#define RVCSR_MHPMEVENT19_LSB _u(0) -#define RVCSR_MHPMEVENT19_ACCESS "RO" -// ============================================================================= -// Register : RVCSR_MHPMEVENT20 -// Description : Extended performance event selector, hardwired to 0. -#define RVCSR_MHPMEVENT20_OFFSET _u(0x00000334) -#define RVCSR_MHPMEVENT20_BITS _u(0xffffffff) -#define RVCSR_MHPMEVENT20_RESET _u(0x00000000) -#define RVCSR_MHPMEVENT20_MSB _u(31) -#define RVCSR_MHPMEVENT20_LSB _u(0) -#define RVCSR_MHPMEVENT20_ACCESS "RO" -// ============================================================================= -// Register : RVCSR_MHPMEVENT21 -// Description : Extended performance event selector, hardwired to 0. -#define RVCSR_MHPMEVENT21_OFFSET _u(0x00000335) -#define RVCSR_MHPMEVENT21_BITS _u(0xffffffff) -#define RVCSR_MHPMEVENT21_RESET _u(0x00000000) -#define RVCSR_MHPMEVENT21_MSB _u(31) -#define RVCSR_MHPMEVENT21_LSB _u(0) -#define RVCSR_MHPMEVENT21_ACCESS "RO" -// ============================================================================= -// Register : RVCSR_MHPMEVENT22 -// Description : Extended performance event selector, hardwired to 0. -#define RVCSR_MHPMEVENT22_OFFSET _u(0x00000336) -#define RVCSR_MHPMEVENT22_BITS _u(0xffffffff) -#define RVCSR_MHPMEVENT22_RESET _u(0x00000000) -#define RVCSR_MHPMEVENT22_MSB _u(31) -#define RVCSR_MHPMEVENT22_LSB _u(0) -#define RVCSR_MHPMEVENT22_ACCESS "RO" -// ============================================================================= -// Register : RVCSR_MHPMEVENT23 -// Description : Extended performance event selector, hardwired to 0. -#define RVCSR_MHPMEVENT23_OFFSET _u(0x00000337) -#define RVCSR_MHPMEVENT23_BITS _u(0xffffffff) -#define RVCSR_MHPMEVENT23_RESET _u(0x00000000) -#define RVCSR_MHPMEVENT23_MSB _u(31) -#define RVCSR_MHPMEVENT23_LSB _u(0) -#define RVCSR_MHPMEVENT23_ACCESS "RO" -// ============================================================================= -// Register : RVCSR_MHPMEVENT24 -// Description : Extended performance event selector, hardwired to 0. -#define RVCSR_MHPMEVENT24_OFFSET _u(0x00000338) -#define RVCSR_MHPMEVENT24_BITS _u(0xffffffff) -#define RVCSR_MHPMEVENT24_RESET _u(0x00000000) -#define RVCSR_MHPMEVENT24_MSB _u(31) -#define RVCSR_MHPMEVENT24_LSB _u(0) -#define RVCSR_MHPMEVENT24_ACCESS "RO" -// ============================================================================= -// Register : RVCSR_MHPMEVENT25 -// Description : Extended performance event selector, hardwired to 0. -#define RVCSR_MHPMEVENT25_OFFSET _u(0x00000339) -#define RVCSR_MHPMEVENT25_BITS _u(0xffffffff) -#define RVCSR_MHPMEVENT25_RESET _u(0x00000000) -#define RVCSR_MHPMEVENT25_MSB _u(31) -#define RVCSR_MHPMEVENT25_LSB _u(0) -#define RVCSR_MHPMEVENT25_ACCESS "RO" -// ============================================================================= -// Register : RVCSR_MHPMEVENT26 -// Description : Extended performance event selector, hardwired to 0. -#define RVCSR_MHPMEVENT26_OFFSET _u(0x0000033a) -#define RVCSR_MHPMEVENT26_BITS _u(0xffffffff) -#define RVCSR_MHPMEVENT26_RESET _u(0x00000000) -#define RVCSR_MHPMEVENT26_MSB _u(31) -#define RVCSR_MHPMEVENT26_LSB _u(0) -#define RVCSR_MHPMEVENT26_ACCESS "RO" -// ============================================================================= -// Register : RVCSR_MHPMEVENT27 -// Description : Extended performance event selector, hardwired to 0. -#define RVCSR_MHPMEVENT27_OFFSET _u(0x0000033b) -#define RVCSR_MHPMEVENT27_BITS _u(0xffffffff) -#define RVCSR_MHPMEVENT27_RESET _u(0x00000000) -#define RVCSR_MHPMEVENT27_MSB _u(31) -#define RVCSR_MHPMEVENT27_LSB _u(0) -#define RVCSR_MHPMEVENT27_ACCESS "RO" -// ============================================================================= -// Register : RVCSR_MHPMEVENT28 -// Description : Extended performance event selector, hardwired to 0. -#define RVCSR_MHPMEVENT28_OFFSET _u(0x0000033c) -#define RVCSR_MHPMEVENT28_BITS _u(0xffffffff) -#define RVCSR_MHPMEVENT28_RESET _u(0x00000000) -#define RVCSR_MHPMEVENT28_MSB _u(31) -#define RVCSR_MHPMEVENT28_LSB _u(0) -#define RVCSR_MHPMEVENT28_ACCESS "RO" -// ============================================================================= -// Register : RVCSR_MHPMEVENT29 -// Description : Extended performance event selector, hardwired to 0. -#define RVCSR_MHPMEVENT29_OFFSET _u(0x0000033d) -#define RVCSR_MHPMEVENT29_BITS _u(0xffffffff) -#define RVCSR_MHPMEVENT29_RESET _u(0x00000000) -#define RVCSR_MHPMEVENT29_MSB _u(31) -#define RVCSR_MHPMEVENT29_LSB _u(0) -#define RVCSR_MHPMEVENT29_ACCESS "RO" -// ============================================================================= -// Register : RVCSR_MHPMEVENT30 -// Description : Extended performance event selector, hardwired to 0. -#define RVCSR_MHPMEVENT30_OFFSET _u(0x0000033e) -#define RVCSR_MHPMEVENT30_BITS _u(0xffffffff) -#define RVCSR_MHPMEVENT30_RESET _u(0x00000000) -#define RVCSR_MHPMEVENT30_MSB _u(31) -#define RVCSR_MHPMEVENT30_LSB _u(0) -#define RVCSR_MHPMEVENT30_ACCESS "RO" -// ============================================================================= -// Register : RVCSR_MHPMEVENT31 -// Description : Extended performance event selector, hardwired to 0. -#define RVCSR_MHPMEVENT31_OFFSET _u(0x0000033f) -#define RVCSR_MHPMEVENT31_BITS _u(0xffffffff) -#define RVCSR_MHPMEVENT31_RESET _u(0x00000000) -#define RVCSR_MHPMEVENT31_MSB _u(31) -#define RVCSR_MHPMEVENT31_LSB _u(0) -#define RVCSR_MHPMEVENT31_ACCESS "RO" -// ============================================================================= -// Register : RVCSR_MSCRATCH -// Description : Scratch register for machine trap handlers. -// -// 32-bit read/write register with no specific hardware function. -// Software may use this to do a fast save/restore of a core -// register in a trap handler. -#define RVCSR_MSCRATCH_OFFSET _u(0x00000340) -#define RVCSR_MSCRATCH_BITS _u(0xffffffff) -#define RVCSR_MSCRATCH_RESET _u(0x00000000) -#define RVCSR_MSCRATCH_MSB _u(31) -#define RVCSR_MSCRATCH_LSB _u(0) -#define RVCSR_MSCRATCH_ACCESS "RW" -// ============================================================================= -// Register : RVCSR_MEPC -// Description : Machine exception program counter. -// -// When entering a trap, the current value of the program counter -// is recorded here. When executing an `mret`, the processor jumps -// to `mepc`. Can also be read and written by software. -#define RVCSR_MEPC_OFFSET _u(0x00000341) -#define RVCSR_MEPC_BITS _u(0xfffffffc) -#define RVCSR_MEPC_RESET _u(0x00000000) -#define RVCSR_MEPC_MSB _u(31) -#define RVCSR_MEPC_LSB _u(2) -#define RVCSR_MEPC_ACCESS "RW" -// ============================================================================= -// Register : RVCSR_MCAUSE -// Description : Machine trap cause. Set when entering a trap to indicate the -// reason for the trap. Readable and writable by software. -#define RVCSR_MCAUSE_OFFSET _u(0x00000342) -#define RVCSR_MCAUSE_BITS _u(0x8000000f) -#define RVCSR_MCAUSE_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : RVCSR_MCAUSE_INTERRUPT -// Description : If 1, the trap was caused by an interrupt. If 0, it was caused -// by an exception. -#define RVCSR_MCAUSE_INTERRUPT_RESET _u(0x0) -#define RVCSR_MCAUSE_INTERRUPT_BITS _u(0x80000000) -#define RVCSR_MCAUSE_INTERRUPT_MSB _u(31) -#define RVCSR_MCAUSE_INTERRUPT_LSB _u(31) -#define RVCSR_MCAUSE_INTERRUPT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RVCSR_MCAUSE_CODE -// Description : If `interrupt` is set, `code` indicates the index of the bit in -// mip that caused the trap (3=soft IRQ, 7=timer IRQ, 11=external -// IRQ). Otherwise, `code` is set according to the cause of the -// exception. -// 0x0 -> Instruction fetch was misaligned. Will never fire on RP2350, since the C extension is enabled. -// 0x1 -> Instruction access fault. Instruction fetch failed a PMP check, or encountered a downstream bus fault, and then passed the point of no speculation. -// 0x2 -> Illegal instruction was executed (including illegal CSR accesses) -// 0x3 -> Breakpoint. An ebreak instruction was executed when the relevant dcsr.ebreak bit was clear. -// 0x4 -> Load address misaligned. Hazard3 requires natural alignment of all accesses. -// 0x5 -> Load access fault. A load failed a PMP check, or encountered a downstream bus error. -// 0x6 -> Store/AMO address misaligned. Hazard3 requires natural alignment of all accesses. -// 0x7 -> Store/AMO access fault. A store/AMO failed a PMP check, or encountered a downstream bus error. Also set if an AMO is attempted on a region that does not support atomics (on RP2350, anything but SRAM). -// 0x8 -> Environment call from U-mode. -// 0xb -> Environment call from M-mode. -#define RVCSR_MCAUSE_CODE_RESET _u(0x0) -#define RVCSR_MCAUSE_CODE_BITS _u(0x0000000f) -#define RVCSR_MCAUSE_CODE_MSB _u(3) -#define RVCSR_MCAUSE_CODE_LSB _u(0) -#define RVCSR_MCAUSE_CODE_ACCESS "RW" -#define RVCSR_MCAUSE_CODE_VALUE_INSTR_ALIGN _u(0x0) -#define RVCSR_MCAUSE_CODE_VALUE_INSTR_FAULT _u(0x1) -#define RVCSR_MCAUSE_CODE_VALUE_ILLEGAL_INSTR _u(0x2) -#define RVCSR_MCAUSE_CODE_VALUE_BREAKPOINT _u(0x3) -#define RVCSR_MCAUSE_CODE_VALUE_LOAD_ALIGN _u(0x4) -#define RVCSR_MCAUSE_CODE_VALUE_LOAD_FAULT _u(0x5) -#define RVCSR_MCAUSE_CODE_VALUE_STORE_ALIGN _u(0x6) -#define RVCSR_MCAUSE_CODE_VALUE_STORE_FAULT _u(0x7) -#define RVCSR_MCAUSE_CODE_VALUE_U_ECALL _u(0x8) -#define RVCSR_MCAUSE_CODE_VALUE_M_ECALL _u(0xb) -// ============================================================================= -// Register : RVCSR_MTVAL -// Description : Machine bad address or instruction. Hardwired to zero. -#define RVCSR_MTVAL_OFFSET _u(0x00000343) -#define RVCSR_MTVAL_BITS _u(0xffffffff) -#define RVCSR_MTVAL_RESET _u(0x00000000) -#define RVCSR_MTVAL_MSB _u(31) -#define RVCSR_MTVAL_LSB _u(0) -#define RVCSR_MTVAL_ACCESS "RO" -// ============================================================================= -// Register : RVCSR_MIP -// Description : Machine interrupt pending -#define RVCSR_MIP_OFFSET _u(0x00000344) -#define RVCSR_MIP_BITS _u(0x00000888) -#define RVCSR_MIP_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : RVCSR_MIP_MEIP -// Description : External interrupt pending. The processor transfers to the -// external interrupt vector when `mie.meie`, `mip.meip` and -// `mstatus.mie` are all 1. -// -// Hazard3 has internal registers to individually filter which -// external IRQs appear in `meip`. When `meip` is 1, this -// indicates there is at least one external interrupt which is -// asserted (hence pending in `mieipa`), enabled in `meiea`, and -// of priority greater than or equal to the current preemption -// level in `meicontext.preempt`. -#define RVCSR_MIP_MEIP_RESET _u(0x0) -#define RVCSR_MIP_MEIP_BITS _u(0x00000800) -#define RVCSR_MIP_MEIP_MSB _u(11) -#define RVCSR_MIP_MEIP_LSB _u(11) -#define RVCSR_MIP_MEIP_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RVCSR_MIP_MTIP -// Description : Timer interrupt pending. The processor transfers to the timer -// interrupt vector when `mie.mtie`, `mip.mtip` and `mstatus.mie` -// are all 1, unless a software or external interrupt request is -// also valid at this time. -#define RVCSR_MIP_MTIP_RESET _u(0x0) -#define RVCSR_MIP_MTIP_BITS _u(0x00000080) -#define RVCSR_MIP_MTIP_MSB _u(7) -#define RVCSR_MIP_MTIP_LSB _u(7) -#define RVCSR_MIP_MTIP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RVCSR_MIP_MSIP -// Description : Software interrupt pending. The processor transfers to the -// software interrupt vector `mie.msie`, `mip.msip` and -// `mstatus.mie` are all 1, unless an external interrupt request -// is also valid at this time. -#define RVCSR_MIP_MSIP_RESET _u(0x0) -#define RVCSR_MIP_MSIP_BITS _u(0x00000008) -#define RVCSR_MIP_MSIP_MSB _u(3) -#define RVCSR_MIP_MSIP_LSB _u(3) -#define RVCSR_MIP_MSIP_ACCESS "RW" -// ============================================================================= -// Register : RVCSR_PMPCFG0 -// Description : Physical memory protection configuration for regions 0 through -// 3 -#define RVCSR_PMPCFG0_OFFSET _u(0x000003a0) -#define RVCSR_PMPCFG0_BITS _u(0x9f9f9f9f) -#define RVCSR_PMPCFG0_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : RVCSR_PMPCFG0_R3_L -// Description : Lock region 3, and apply it to M-mode as well as U-mode. -#define RVCSR_PMPCFG0_R3_L_RESET _u(0x0) -#define RVCSR_PMPCFG0_R3_L_BITS _u(0x80000000) -#define RVCSR_PMPCFG0_R3_L_MSB _u(31) -#define RVCSR_PMPCFG0_R3_L_LSB _u(31) -#define RVCSR_PMPCFG0_R3_L_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RVCSR_PMPCFG0_R3_A -// Description : Address matching type for region 3. Writing an unsupported -// value (TOR) will set the region to OFF. -// 0x0 -> Disable region -// 0x2 -> Naturally aligned 4-byte -// 0x3 -> Naturally aligned power-of-two (8 bytes to 4 GiB) -#define RVCSR_PMPCFG0_R3_A_RESET _u(0x0) -#define RVCSR_PMPCFG0_R3_A_BITS _u(0x18000000) -#define RVCSR_PMPCFG0_R3_A_MSB _u(28) -#define RVCSR_PMPCFG0_R3_A_LSB _u(27) -#define RVCSR_PMPCFG0_R3_A_ACCESS "RW" -#define RVCSR_PMPCFG0_R3_A_VALUE_OFF _u(0x0) -#define RVCSR_PMPCFG0_R3_A_VALUE_NA4 _u(0x2) -#define RVCSR_PMPCFG0_R3_A_VALUE_NAPOT _u(0x3) -// ----------------------------------------------------------------------------- -// Field : RVCSR_PMPCFG0_R3_R -// Description : Read permission for region 3. Note R and X are transposed from -// the standard bit order due to erratum RP2350-E6. -#define RVCSR_PMPCFG0_R3_R_RESET _u(0x0) -#define RVCSR_PMPCFG0_R3_R_BITS _u(0x04000000) -#define RVCSR_PMPCFG0_R3_R_MSB _u(26) -#define RVCSR_PMPCFG0_R3_R_LSB _u(26) -#define RVCSR_PMPCFG0_R3_R_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RVCSR_PMPCFG0_R3_W -// Description : Write permission for region 3 -#define RVCSR_PMPCFG0_R3_W_RESET _u(0x0) -#define RVCSR_PMPCFG0_R3_W_BITS _u(0x02000000) -#define RVCSR_PMPCFG0_R3_W_MSB _u(25) -#define RVCSR_PMPCFG0_R3_W_LSB _u(25) -#define RVCSR_PMPCFG0_R3_W_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RVCSR_PMPCFG0_R3_X -// Description : Execute permission for region 3. Note R and X are transposed -// from the standard bit order due to erratum RP2350-E6. -#define RVCSR_PMPCFG0_R3_X_RESET _u(0x0) -#define RVCSR_PMPCFG0_R3_X_BITS _u(0x01000000) -#define RVCSR_PMPCFG0_R3_X_MSB _u(24) -#define RVCSR_PMPCFG0_R3_X_LSB _u(24) -#define RVCSR_PMPCFG0_R3_X_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RVCSR_PMPCFG0_R2_L -// Description : Lock region 2, and apply it to M-mode as well as U-mode. -#define RVCSR_PMPCFG0_R2_L_RESET _u(0x0) -#define RVCSR_PMPCFG0_R2_L_BITS _u(0x00800000) -#define RVCSR_PMPCFG0_R2_L_MSB _u(23) -#define RVCSR_PMPCFG0_R2_L_LSB _u(23) -#define RVCSR_PMPCFG0_R2_L_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RVCSR_PMPCFG0_R2_A -// Description : Address matching type for region 2. Writing an unsupported -// value (TOR) will set the region to OFF. -// 0x0 -> Disable region -// 0x2 -> Naturally aligned 4-byte -// 0x3 -> Naturally aligned power-of-two (8 bytes to 4 GiB) -#define RVCSR_PMPCFG0_R2_A_RESET _u(0x0) -#define RVCSR_PMPCFG0_R2_A_BITS _u(0x00180000) -#define RVCSR_PMPCFG0_R2_A_MSB _u(20) -#define RVCSR_PMPCFG0_R2_A_LSB _u(19) -#define RVCSR_PMPCFG0_R2_A_ACCESS "RW" -#define RVCSR_PMPCFG0_R2_A_VALUE_OFF _u(0x0) -#define RVCSR_PMPCFG0_R2_A_VALUE_NA4 _u(0x2) -#define RVCSR_PMPCFG0_R2_A_VALUE_NAPOT _u(0x3) -// ----------------------------------------------------------------------------- -// Field : RVCSR_PMPCFG0_R2_R -// Description : Read permission for region 2. Note R and X are transposed from -// the standard bit order due to erratum RP2350-E6. -#define RVCSR_PMPCFG0_R2_R_RESET _u(0x0) -#define RVCSR_PMPCFG0_R2_R_BITS _u(0x00040000) -#define RVCSR_PMPCFG0_R2_R_MSB _u(18) -#define RVCSR_PMPCFG0_R2_R_LSB _u(18) -#define RVCSR_PMPCFG0_R2_R_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RVCSR_PMPCFG0_R2_W -// Description : Write permission for region 2 -#define RVCSR_PMPCFG0_R2_W_RESET _u(0x0) -#define RVCSR_PMPCFG0_R2_W_BITS _u(0x00020000) -#define RVCSR_PMPCFG0_R2_W_MSB _u(17) -#define RVCSR_PMPCFG0_R2_W_LSB _u(17) -#define RVCSR_PMPCFG0_R2_W_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RVCSR_PMPCFG0_R2_X -// Description : Execute permission for region 2. Note R and X are transposed -// from the standard bit order due to erratum RP2350-E6. -#define RVCSR_PMPCFG0_R2_X_RESET _u(0x0) -#define RVCSR_PMPCFG0_R2_X_BITS _u(0x00010000) -#define RVCSR_PMPCFG0_R2_X_MSB _u(16) -#define RVCSR_PMPCFG0_R2_X_LSB _u(16) -#define RVCSR_PMPCFG0_R2_X_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RVCSR_PMPCFG0_R1_L -// Description : Lock region 1, and apply it to M-mode as well as U-mode. -#define RVCSR_PMPCFG0_R1_L_RESET _u(0x0) -#define RVCSR_PMPCFG0_R1_L_BITS _u(0x00008000) -#define RVCSR_PMPCFG0_R1_L_MSB _u(15) -#define RVCSR_PMPCFG0_R1_L_LSB _u(15) -#define RVCSR_PMPCFG0_R1_L_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RVCSR_PMPCFG0_R1_A -// Description : Address matching type for region 1. Writing an unsupported -// value (TOR) will set the region to OFF. -// 0x0 -> Disable region -// 0x2 -> Naturally aligned 4-byte -// 0x3 -> Naturally aligned power-of-two (8 bytes to 4 GiB) -#define RVCSR_PMPCFG0_R1_A_RESET _u(0x0) -#define RVCSR_PMPCFG0_R1_A_BITS _u(0x00001800) -#define RVCSR_PMPCFG0_R1_A_MSB _u(12) -#define RVCSR_PMPCFG0_R1_A_LSB _u(11) -#define RVCSR_PMPCFG0_R1_A_ACCESS "RW" -#define RVCSR_PMPCFG0_R1_A_VALUE_OFF _u(0x0) -#define RVCSR_PMPCFG0_R1_A_VALUE_NA4 _u(0x2) -#define RVCSR_PMPCFG0_R1_A_VALUE_NAPOT _u(0x3) -// ----------------------------------------------------------------------------- -// Field : RVCSR_PMPCFG0_R1_R -// Description : Read permission for region 1. Note R and X are transposed from -// the standard bit order due to erratum RP2350-E6. -#define RVCSR_PMPCFG0_R1_R_RESET _u(0x0) -#define RVCSR_PMPCFG0_R1_R_BITS _u(0x00000400) -#define RVCSR_PMPCFG0_R1_R_MSB _u(10) -#define RVCSR_PMPCFG0_R1_R_LSB _u(10) -#define RVCSR_PMPCFG0_R1_R_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RVCSR_PMPCFG0_R1_W -// Description : Write permission for region 1 -#define RVCSR_PMPCFG0_R1_W_RESET _u(0x0) -#define RVCSR_PMPCFG0_R1_W_BITS _u(0x00000200) -#define RVCSR_PMPCFG0_R1_W_MSB _u(9) -#define RVCSR_PMPCFG0_R1_W_LSB _u(9) -#define RVCSR_PMPCFG0_R1_W_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RVCSR_PMPCFG0_R1_X -// Description : Execute permission for region 1. Note R and X are transposed -// from the standard bit order due to erratum RP2350-E6. -#define RVCSR_PMPCFG0_R1_X_RESET _u(0x0) -#define RVCSR_PMPCFG0_R1_X_BITS _u(0x00000100) -#define RVCSR_PMPCFG0_R1_X_MSB _u(8) -#define RVCSR_PMPCFG0_R1_X_LSB _u(8) -#define RVCSR_PMPCFG0_R1_X_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RVCSR_PMPCFG0_R0_L -// Description : Lock region 0, and apply it to M-mode as well as U-mode. -#define RVCSR_PMPCFG0_R0_L_RESET _u(0x0) -#define RVCSR_PMPCFG0_R0_L_BITS _u(0x00000080) -#define RVCSR_PMPCFG0_R0_L_MSB _u(7) -#define RVCSR_PMPCFG0_R0_L_LSB _u(7) -#define RVCSR_PMPCFG0_R0_L_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RVCSR_PMPCFG0_R0_A -// Description : Address matching type for region 0. Writing an unsupported -// value (TOR) will set the region to OFF. -// 0x0 -> Disable region -// 0x2 -> Naturally aligned 4-byte -// 0x3 -> Naturally aligned power-of-two (8 bytes to 4 GiB) -#define RVCSR_PMPCFG0_R0_A_RESET _u(0x0) -#define RVCSR_PMPCFG0_R0_A_BITS _u(0x00000018) -#define RVCSR_PMPCFG0_R0_A_MSB _u(4) -#define RVCSR_PMPCFG0_R0_A_LSB _u(3) -#define RVCSR_PMPCFG0_R0_A_ACCESS "RW" -#define RVCSR_PMPCFG0_R0_A_VALUE_OFF _u(0x0) -#define RVCSR_PMPCFG0_R0_A_VALUE_NA4 _u(0x2) -#define RVCSR_PMPCFG0_R0_A_VALUE_NAPOT _u(0x3) -// ----------------------------------------------------------------------------- -// Field : RVCSR_PMPCFG0_R0_R -// Description : Read permission for region 0. Note R and X are transposed from -// the standard bit order due to erratum RP2350-E6. -#define RVCSR_PMPCFG0_R0_R_RESET _u(0x0) -#define RVCSR_PMPCFG0_R0_R_BITS _u(0x00000004) -#define RVCSR_PMPCFG0_R0_R_MSB _u(2) -#define RVCSR_PMPCFG0_R0_R_LSB _u(2) -#define RVCSR_PMPCFG0_R0_R_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RVCSR_PMPCFG0_R0_W -// Description : Write permission for region 0 -#define RVCSR_PMPCFG0_R0_W_RESET _u(0x0) -#define RVCSR_PMPCFG0_R0_W_BITS _u(0x00000002) -#define RVCSR_PMPCFG0_R0_W_MSB _u(1) -#define RVCSR_PMPCFG0_R0_W_LSB _u(1) -#define RVCSR_PMPCFG0_R0_W_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RVCSR_PMPCFG0_R0_X -// Description : Execute permission for region 0. Note R and X are transposed -// from the standard bit order due to erratum RP2350-E6. -#define RVCSR_PMPCFG0_R0_X_RESET _u(0x0) -#define RVCSR_PMPCFG0_R0_X_BITS _u(0x00000001) -#define RVCSR_PMPCFG0_R0_X_MSB _u(0) -#define RVCSR_PMPCFG0_R0_X_LSB _u(0) -#define RVCSR_PMPCFG0_R0_X_ACCESS "RW" -// ============================================================================= -// Register : RVCSR_PMPCFG1 -// Description : Physical memory protection configuration for regions 4 through -// 7 -#define RVCSR_PMPCFG1_OFFSET _u(0x000003a1) -#define RVCSR_PMPCFG1_BITS _u(0x9f9f9f9f) -#define RVCSR_PMPCFG1_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : RVCSR_PMPCFG1_R7_L -// Description : Lock region 7, and apply it to M-mode as well as U-mode. -#define RVCSR_PMPCFG1_R7_L_RESET _u(0x0) -#define RVCSR_PMPCFG1_R7_L_BITS _u(0x80000000) -#define RVCSR_PMPCFG1_R7_L_MSB _u(31) -#define RVCSR_PMPCFG1_R7_L_LSB _u(31) -#define RVCSR_PMPCFG1_R7_L_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RVCSR_PMPCFG1_R7_A -// Description : Address matching type for region 7. Writing an unsupported -// value (TOR) will set the region to OFF. -// 0x0 -> Disable region -// 0x2 -> Naturally aligned 4-byte -// 0x3 -> Naturally aligned power-of-two (8 bytes to 4 GiB) -#define RVCSR_PMPCFG1_R7_A_RESET _u(0x0) -#define RVCSR_PMPCFG1_R7_A_BITS _u(0x18000000) -#define RVCSR_PMPCFG1_R7_A_MSB _u(28) -#define RVCSR_PMPCFG1_R7_A_LSB _u(27) -#define RVCSR_PMPCFG1_R7_A_ACCESS "RW" -#define RVCSR_PMPCFG1_R7_A_VALUE_OFF _u(0x0) -#define RVCSR_PMPCFG1_R7_A_VALUE_NA4 _u(0x2) -#define RVCSR_PMPCFG1_R7_A_VALUE_NAPOT _u(0x3) -// ----------------------------------------------------------------------------- -// Field : RVCSR_PMPCFG1_R7_R -// Description : Read permission for region 7. Note R and X are transposed from -// the standard bit order due to erratum RP2350-E6. -#define RVCSR_PMPCFG1_R7_R_RESET _u(0x0) -#define RVCSR_PMPCFG1_R7_R_BITS _u(0x04000000) -#define RVCSR_PMPCFG1_R7_R_MSB _u(26) -#define RVCSR_PMPCFG1_R7_R_LSB _u(26) -#define RVCSR_PMPCFG1_R7_R_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RVCSR_PMPCFG1_R7_W -// Description : Write permission for region 7 -#define RVCSR_PMPCFG1_R7_W_RESET _u(0x0) -#define RVCSR_PMPCFG1_R7_W_BITS _u(0x02000000) -#define RVCSR_PMPCFG1_R7_W_MSB _u(25) -#define RVCSR_PMPCFG1_R7_W_LSB _u(25) -#define RVCSR_PMPCFG1_R7_W_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RVCSR_PMPCFG1_R7_X -// Description : Execute permission for region 7. Note R and X are transposed -// from the standard bit order due to erratum RP2350-E6. -#define RVCSR_PMPCFG1_R7_X_RESET _u(0x0) -#define RVCSR_PMPCFG1_R7_X_BITS _u(0x01000000) -#define RVCSR_PMPCFG1_R7_X_MSB _u(24) -#define RVCSR_PMPCFG1_R7_X_LSB _u(24) -#define RVCSR_PMPCFG1_R7_X_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RVCSR_PMPCFG1_R6_L -// Description : Lock region 6, and apply it to M-mode as well as U-mode. -#define RVCSR_PMPCFG1_R6_L_RESET _u(0x0) -#define RVCSR_PMPCFG1_R6_L_BITS _u(0x00800000) -#define RVCSR_PMPCFG1_R6_L_MSB _u(23) -#define RVCSR_PMPCFG1_R6_L_LSB _u(23) -#define RVCSR_PMPCFG1_R6_L_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RVCSR_PMPCFG1_R6_A -// Description : Address matching type for region 6. Writing an unsupported -// value (TOR) will set the region to OFF. -// 0x0 -> Disable region -// 0x2 -> Naturally aligned 4-byte -// 0x3 -> Naturally aligned power-of-two (8 bytes to 4 GiB) -#define RVCSR_PMPCFG1_R6_A_RESET _u(0x0) -#define RVCSR_PMPCFG1_R6_A_BITS _u(0x00180000) -#define RVCSR_PMPCFG1_R6_A_MSB _u(20) -#define RVCSR_PMPCFG1_R6_A_LSB _u(19) -#define RVCSR_PMPCFG1_R6_A_ACCESS "RW" -#define RVCSR_PMPCFG1_R6_A_VALUE_OFF _u(0x0) -#define RVCSR_PMPCFG1_R6_A_VALUE_NA4 _u(0x2) -#define RVCSR_PMPCFG1_R6_A_VALUE_NAPOT _u(0x3) -// ----------------------------------------------------------------------------- -// Field : RVCSR_PMPCFG1_R6_R -// Description : Read permission for region 6. Note R and X are transposed from -// the standard bit order due to erratum RP2350-E6. -#define RVCSR_PMPCFG1_R6_R_RESET _u(0x0) -#define RVCSR_PMPCFG1_R6_R_BITS _u(0x00040000) -#define RVCSR_PMPCFG1_R6_R_MSB _u(18) -#define RVCSR_PMPCFG1_R6_R_LSB _u(18) -#define RVCSR_PMPCFG1_R6_R_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RVCSR_PMPCFG1_R6_W -// Description : Write permission for region 6 -#define RVCSR_PMPCFG1_R6_W_RESET _u(0x0) -#define RVCSR_PMPCFG1_R6_W_BITS _u(0x00020000) -#define RVCSR_PMPCFG1_R6_W_MSB _u(17) -#define RVCSR_PMPCFG1_R6_W_LSB _u(17) -#define RVCSR_PMPCFG1_R6_W_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RVCSR_PMPCFG1_R6_X -// Description : Execute permission for region 6. Note R and X are transposed -// from the standard bit order due to erratum RP2350-E6. -#define RVCSR_PMPCFG1_R6_X_RESET _u(0x0) -#define RVCSR_PMPCFG1_R6_X_BITS _u(0x00010000) -#define RVCSR_PMPCFG1_R6_X_MSB _u(16) -#define RVCSR_PMPCFG1_R6_X_LSB _u(16) -#define RVCSR_PMPCFG1_R6_X_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RVCSR_PMPCFG1_R5_L -// Description : Lock region 5, and apply it to M-mode as well as U-mode. -#define RVCSR_PMPCFG1_R5_L_RESET _u(0x0) -#define RVCSR_PMPCFG1_R5_L_BITS _u(0x00008000) -#define RVCSR_PMPCFG1_R5_L_MSB _u(15) -#define RVCSR_PMPCFG1_R5_L_LSB _u(15) -#define RVCSR_PMPCFG1_R5_L_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RVCSR_PMPCFG1_R5_A -// Description : Address matching type for region 5. Writing an unsupported -// value (TOR) will set the region to OFF. -// 0x0 -> Disable region -// 0x2 -> Naturally aligned 4-byte -// 0x3 -> Naturally aligned power-of-two (8 bytes to 4 GiB) -#define RVCSR_PMPCFG1_R5_A_RESET _u(0x0) -#define RVCSR_PMPCFG1_R5_A_BITS _u(0x00001800) -#define RVCSR_PMPCFG1_R5_A_MSB _u(12) -#define RVCSR_PMPCFG1_R5_A_LSB _u(11) -#define RVCSR_PMPCFG1_R5_A_ACCESS "RW" -#define RVCSR_PMPCFG1_R5_A_VALUE_OFF _u(0x0) -#define RVCSR_PMPCFG1_R5_A_VALUE_NA4 _u(0x2) -#define RVCSR_PMPCFG1_R5_A_VALUE_NAPOT _u(0x3) -// ----------------------------------------------------------------------------- -// Field : RVCSR_PMPCFG1_R5_R -// Description : Read permission for region 5. Note R and X are transposed from -// the standard bit order due to erratum RP2350-E6. -#define RVCSR_PMPCFG1_R5_R_RESET _u(0x0) -#define RVCSR_PMPCFG1_R5_R_BITS _u(0x00000400) -#define RVCSR_PMPCFG1_R5_R_MSB _u(10) -#define RVCSR_PMPCFG1_R5_R_LSB _u(10) -#define RVCSR_PMPCFG1_R5_R_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RVCSR_PMPCFG1_R5_W -// Description : Write permission for region 5 -#define RVCSR_PMPCFG1_R5_W_RESET _u(0x0) -#define RVCSR_PMPCFG1_R5_W_BITS _u(0x00000200) -#define RVCSR_PMPCFG1_R5_W_MSB _u(9) -#define RVCSR_PMPCFG1_R5_W_LSB _u(9) -#define RVCSR_PMPCFG1_R5_W_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RVCSR_PMPCFG1_R5_X -// Description : Execute permission for region 5. Note R and X are transposed -// from the standard bit order due to erratum RP2350-E6. -#define RVCSR_PMPCFG1_R5_X_RESET _u(0x0) -#define RVCSR_PMPCFG1_R5_X_BITS _u(0x00000100) -#define RVCSR_PMPCFG1_R5_X_MSB _u(8) -#define RVCSR_PMPCFG1_R5_X_LSB _u(8) -#define RVCSR_PMPCFG1_R5_X_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RVCSR_PMPCFG1_R4_L -// Description : Lock region 4, and apply it to M-mode as well as U-mode. -#define RVCSR_PMPCFG1_R4_L_RESET _u(0x0) -#define RVCSR_PMPCFG1_R4_L_BITS _u(0x00000080) -#define RVCSR_PMPCFG1_R4_L_MSB _u(7) -#define RVCSR_PMPCFG1_R4_L_LSB _u(7) -#define RVCSR_PMPCFG1_R4_L_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RVCSR_PMPCFG1_R4_A -// Description : Address matching type for region 4. Writing an unsupported -// value (TOR) will set the region to OFF. -// 0x0 -> Disable region -// 0x2 -> Naturally aligned 4-byte -// 0x3 -> Naturally aligned power-of-two (8 bytes to 4 GiB) -#define RVCSR_PMPCFG1_R4_A_RESET _u(0x0) -#define RVCSR_PMPCFG1_R4_A_BITS _u(0x00000018) -#define RVCSR_PMPCFG1_R4_A_MSB _u(4) -#define RVCSR_PMPCFG1_R4_A_LSB _u(3) -#define RVCSR_PMPCFG1_R4_A_ACCESS "RW" -#define RVCSR_PMPCFG1_R4_A_VALUE_OFF _u(0x0) -#define RVCSR_PMPCFG1_R4_A_VALUE_NA4 _u(0x2) -#define RVCSR_PMPCFG1_R4_A_VALUE_NAPOT _u(0x3) -// ----------------------------------------------------------------------------- -// Field : RVCSR_PMPCFG1_R4_R -// Description : Read permission for region 4. Note R and X are transposed from -// the standard bit order due to erratum RP2350-E6. -#define RVCSR_PMPCFG1_R4_R_RESET _u(0x0) -#define RVCSR_PMPCFG1_R4_R_BITS _u(0x00000004) -#define RVCSR_PMPCFG1_R4_R_MSB _u(2) -#define RVCSR_PMPCFG1_R4_R_LSB _u(2) -#define RVCSR_PMPCFG1_R4_R_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RVCSR_PMPCFG1_R4_W -// Description : Write permission for region 4 -#define RVCSR_PMPCFG1_R4_W_RESET _u(0x0) -#define RVCSR_PMPCFG1_R4_W_BITS _u(0x00000002) -#define RVCSR_PMPCFG1_R4_W_MSB _u(1) -#define RVCSR_PMPCFG1_R4_W_LSB _u(1) -#define RVCSR_PMPCFG1_R4_W_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RVCSR_PMPCFG1_R4_X -// Description : Execute permission for region 4. Note R and X are transposed -// from the standard bit order due to erratum RP2350-E6. -#define RVCSR_PMPCFG1_R4_X_RESET _u(0x0) -#define RVCSR_PMPCFG1_R4_X_BITS _u(0x00000001) -#define RVCSR_PMPCFG1_R4_X_MSB _u(0) -#define RVCSR_PMPCFG1_R4_X_LSB _u(0) -#define RVCSR_PMPCFG1_R4_X_ACCESS "RW" -// ============================================================================= -// Register : RVCSR_PMPCFG2 -// Description : Physical memory protection configuration for regions 8 through -// 11 -#define RVCSR_PMPCFG2_OFFSET _u(0x000003a2) -#define RVCSR_PMPCFG2_BITS _u(0x9f9f9f9f) -#define RVCSR_PMPCFG2_RESET _u(0x001f1f1f) -// ----------------------------------------------------------------------------- -// Field : RVCSR_PMPCFG2_R11_L -// Description : Lock region 11, and apply it to M-mode as well as U-mode. -#define RVCSR_PMPCFG2_R11_L_RESET _u(0x0) -#define RVCSR_PMPCFG2_R11_L_BITS _u(0x80000000) -#define RVCSR_PMPCFG2_R11_L_MSB _u(31) -#define RVCSR_PMPCFG2_R11_L_LSB _u(31) -#define RVCSR_PMPCFG2_R11_L_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RVCSR_PMPCFG2_R11_A -// Description : Address matching type for region 11. Writing an unsupported -// value (TOR) will set the region to OFF. -// 0x0 -> Disable region -// 0x2 -> Naturally aligned 4-byte -// 0x3 -> Naturally aligned power-of-two (8 bytes to 4 GiB) -#define RVCSR_PMPCFG2_R11_A_RESET _u(0x0) -#define RVCSR_PMPCFG2_R11_A_BITS _u(0x18000000) -#define RVCSR_PMPCFG2_R11_A_MSB _u(28) -#define RVCSR_PMPCFG2_R11_A_LSB _u(27) -#define RVCSR_PMPCFG2_R11_A_ACCESS "RO" -#define RVCSR_PMPCFG2_R11_A_VALUE_OFF _u(0x0) -#define RVCSR_PMPCFG2_R11_A_VALUE_NA4 _u(0x2) -#define RVCSR_PMPCFG2_R11_A_VALUE_NAPOT _u(0x3) -// ----------------------------------------------------------------------------- -// Field : RVCSR_PMPCFG2_R11_R -// Description : Read permission for region 11. Note R and X are transposed from -// the standard bit order due to erratum RP2350-E6. -#define RVCSR_PMPCFG2_R11_R_RESET _u(0x0) -#define RVCSR_PMPCFG2_R11_R_BITS _u(0x04000000) -#define RVCSR_PMPCFG2_R11_R_MSB _u(26) -#define RVCSR_PMPCFG2_R11_R_LSB _u(26) -#define RVCSR_PMPCFG2_R11_R_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RVCSR_PMPCFG2_R11_W -// Description : Write permission for region 11 -#define RVCSR_PMPCFG2_R11_W_RESET _u(0x0) -#define RVCSR_PMPCFG2_R11_W_BITS _u(0x02000000) -#define RVCSR_PMPCFG2_R11_W_MSB _u(25) -#define RVCSR_PMPCFG2_R11_W_LSB _u(25) -#define RVCSR_PMPCFG2_R11_W_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RVCSR_PMPCFG2_R11_X -// Description : Execute permission for region 11. Note R and X are transposed -// from the standard bit order due to erratum RP2350-E6. -#define RVCSR_PMPCFG2_R11_X_RESET _u(0x0) -#define RVCSR_PMPCFG2_R11_X_BITS _u(0x01000000) -#define RVCSR_PMPCFG2_R11_X_MSB _u(24) -#define RVCSR_PMPCFG2_R11_X_LSB _u(24) -#define RVCSR_PMPCFG2_R11_X_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RVCSR_PMPCFG2_R10_L -// Description : Lock region 10, and apply it to M-mode as well as U-mode. -#define RVCSR_PMPCFG2_R10_L_RESET _u(0x0) -#define RVCSR_PMPCFG2_R10_L_BITS _u(0x00800000) -#define RVCSR_PMPCFG2_R10_L_MSB _u(23) -#define RVCSR_PMPCFG2_R10_L_LSB _u(23) -#define RVCSR_PMPCFG2_R10_L_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RVCSR_PMPCFG2_R10_A -// Description : Address matching type for region 10. Writing an unsupported -// value (TOR) will set the region to OFF. -// 0x0 -> Disable region -// 0x2 -> Naturally aligned 4-byte -// 0x3 -> Naturally aligned power-of-two (8 bytes to 4 GiB) -#define RVCSR_PMPCFG2_R10_A_RESET _u(0x3) -#define RVCSR_PMPCFG2_R10_A_BITS _u(0x00180000) -#define RVCSR_PMPCFG2_R10_A_MSB _u(20) -#define RVCSR_PMPCFG2_R10_A_LSB _u(19) -#define RVCSR_PMPCFG2_R10_A_ACCESS "RO" -#define RVCSR_PMPCFG2_R10_A_VALUE_OFF _u(0x0) -#define RVCSR_PMPCFG2_R10_A_VALUE_NA4 _u(0x2) -#define RVCSR_PMPCFG2_R10_A_VALUE_NAPOT _u(0x3) -// ----------------------------------------------------------------------------- -// Field : RVCSR_PMPCFG2_R10_R -// Description : Read permission for region 10. Note R and X are transposed from -// the standard bit order due to erratum RP2350-E6. -#define RVCSR_PMPCFG2_R10_R_RESET _u(0x1) -#define RVCSR_PMPCFG2_R10_R_BITS _u(0x00040000) -#define RVCSR_PMPCFG2_R10_R_MSB _u(18) -#define RVCSR_PMPCFG2_R10_R_LSB _u(18) -#define RVCSR_PMPCFG2_R10_R_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RVCSR_PMPCFG2_R10_W -// Description : Write permission for region 10 -#define RVCSR_PMPCFG2_R10_W_RESET _u(0x1) -#define RVCSR_PMPCFG2_R10_W_BITS _u(0x00020000) -#define RVCSR_PMPCFG2_R10_W_MSB _u(17) -#define RVCSR_PMPCFG2_R10_W_LSB _u(17) -#define RVCSR_PMPCFG2_R10_W_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RVCSR_PMPCFG2_R10_X -// Description : Execute permission for region 10. Note R and X are transposed -// from the standard bit order due to erratum RP2350-E6. -#define RVCSR_PMPCFG2_R10_X_RESET _u(0x1) -#define RVCSR_PMPCFG2_R10_X_BITS _u(0x00010000) -#define RVCSR_PMPCFG2_R10_X_MSB _u(16) -#define RVCSR_PMPCFG2_R10_X_LSB _u(16) -#define RVCSR_PMPCFG2_R10_X_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RVCSR_PMPCFG2_R9_L -// Description : Lock region 9, and apply it to M-mode as well as U-mode. -#define RVCSR_PMPCFG2_R9_L_RESET _u(0x0) -#define RVCSR_PMPCFG2_R9_L_BITS _u(0x00008000) -#define RVCSR_PMPCFG2_R9_L_MSB _u(15) -#define RVCSR_PMPCFG2_R9_L_LSB _u(15) -#define RVCSR_PMPCFG2_R9_L_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RVCSR_PMPCFG2_R9_A -// Description : Address matching type for region 9. Writing an unsupported -// value (TOR) will set the region to OFF. -// 0x0 -> Disable region -// 0x2 -> Naturally aligned 4-byte -// 0x3 -> Naturally aligned power-of-two (8 bytes to 4 GiB) -#define RVCSR_PMPCFG2_R9_A_RESET _u(0x3) -#define RVCSR_PMPCFG2_R9_A_BITS _u(0x00001800) -#define RVCSR_PMPCFG2_R9_A_MSB _u(12) -#define RVCSR_PMPCFG2_R9_A_LSB _u(11) -#define RVCSR_PMPCFG2_R9_A_ACCESS "RO" -#define RVCSR_PMPCFG2_R9_A_VALUE_OFF _u(0x0) -#define RVCSR_PMPCFG2_R9_A_VALUE_NA4 _u(0x2) -#define RVCSR_PMPCFG2_R9_A_VALUE_NAPOT _u(0x3) -// ----------------------------------------------------------------------------- -// Field : RVCSR_PMPCFG2_R9_R -// Description : Read permission for region 9. Note R and X are transposed from -// the standard bit order due to erratum RP2350-E6. -#define RVCSR_PMPCFG2_R9_R_RESET _u(0x1) -#define RVCSR_PMPCFG2_R9_R_BITS _u(0x00000400) -#define RVCSR_PMPCFG2_R9_R_MSB _u(10) -#define RVCSR_PMPCFG2_R9_R_LSB _u(10) -#define RVCSR_PMPCFG2_R9_R_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RVCSR_PMPCFG2_R9_W -// Description : Write permission for region 9 -#define RVCSR_PMPCFG2_R9_W_RESET _u(0x1) -#define RVCSR_PMPCFG2_R9_W_BITS _u(0x00000200) -#define RVCSR_PMPCFG2_R9_W_MSB _u(9) -#define RVCSR_PMPCFG2_R9_W_LSB _u(9) -#define RVCSR_PMPCFG2_R9_W_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RVCSR_PMPCFG2_R9_X -// Description : Execute permission for region 9. Note R and X are transposed -// from the standard bit order due to erratum RP2350-E6. -#define RVCSR_PMPCFG2_R9_X_RESET _u(0x1) -#define RVCSR_PMPCFG2_R9_X_BITS _u(0x00000100) -#define RVCSR_PMPCFG2_R9_X_MSB _u(8) -#define RVCSR_PMPCFG2_R9_X_LSB _u(8) -#define RVCSR_PMPCFG2_R9_X_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RVCSR_PMPCFG2_R8_L -// Description : Lock region 8, and apply it to M-mode as well as U-mode. -#define RVCSR_PMPCFG2_R8_L_RESET _u(0x0) -#define RVCSR_PMPCFG2_R8_L_BITS _u(0x00000080) -#define RVCSR_PMPCFG2_R8_L_MSB _u(7) -#define RVCSR_PMPCFG2_R8_L_LSB _u(7) -#define RVCSR_PMPCFG2_R8_L_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RVCSR_PMPCFG2_R8_A -// Description : Address matching type for region 8. Writing an unsupported -// value (TOR) will set the region to OFF. -// 0x0 -> Disable region -// 0x2 -> Naturally aligned 4-byte -// 0x3 -> Naturally aligned power-of-two (8 bytes to 4 GiB) -#define RVCSR_PMPCFG2_R8_A_RESET _u(0x3) -#define RVCSR_PMPCFG2_R8_A_BITS _u(0x00000018) -#define RVCSR_PMPCFG2_R8_A_MSB _u(4) -#define RVCSR_PMPCFG2_R8_A_LSB _u(3) -#define RVCSR_PMPCFG2_R8_A_ACCESS "RO" -#define RVCSR_PMPCFG2_R8_A_VALUE_OFF _u(0x0) -#define RVCSR_PMPCFG2_R8_A_VALUE_NA4 _u(0x2) -#define RVCSR_PMPCFG2_R8_A_VALUE_NAPOT _u(0x3) -// ----------------------------------------------------------------------------- -// Field : RVCSR_PMPCFG2_R8_R -// Description : Read permission for region 8. Note R and X are transposed from -// the standard bit order due to erratum RP2350-E6. -#define RVCSR_PMPCFG2_R8_R_RESET _u(0x1) -#define RVCSR_PMPCFG2_R8_R_BITS _u(0x00000004) -#define RVCSR_PMPCFG2_R8_R_MSB _u(2) -#define RVCSR_PMPCFG2_R8_R_LSB _u(2) -#define RVCSR_PMPCFG2_R8_R_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RVCSR_PMPCFG2_R8_W -// Description : Write permission for region 8 -#define RVCSR_PMPCFG2_R8_W_RESET _u(0x1) -#define RVCSR_PMPCFG2_R8_W_BITS _u(0x00000002) -#define RVCSR_PMPCFG2_R8_W_MSB _u(1) -#define RVCSR_PMPCFG2_R8_W_LSB _u(1) -#define RVCSR_PMPCFG2_R8_W_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RVCSR_PMPCFG2_R8_X -// Description : Execute permission for region 8. Note R and X are transposed -// from the standard bit order due to erratum RP2350-E6. -#define RVCSR_PMPCFG2_R8_X_RESET _u(0x1) -#define RVCSR_PMPCFG2_R8_X_BITS _u(0x00000001) -#define RVCSR_PMPCFG2_R8_X_MSB _u(0) -#define RVCSR_PMPCFG2_R8_X_LSB _u(0) -#define RVCSR_PMPCFG2_R8_X_ACCESS "RO" -// ============================================================================= -// Register : RVCSR_PMPCFG3 -// Description : Physical memory protection configuration for regions 12 through -// 15 -#define RVCSR_PMPCFG3_OFFSET _u(0x000003a3) -#define RVCSR_PMPCFG3_BITS _u(0x9f9f9f9f) -#define RVCSR_PMPCFG3_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : RVCSR_PMPCFG3_R15_L -// Description : Lock region 15, and apply it to M-mode as well as U-mode. -#define RVCSR_PMPCFG3_R15_L_RESET _u(0x0) -#define RVCSR_PMPCFG3_R15_L_BITS _u(0x80000000) -#define RVCSR_PMPCFG3_R15_L_MSB _u(31) -#define RVCSR_PMPCFG3_R15_L_LSB _u(31) -#define RVCSR_PMPCFG3_R15_L_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RVCSR_PMPCFG3_R15_A -// Description : Address matching type for region 15. Writing an unsupported -// value (TOR) will set the region to OFF. -// 0x0 -> Disable region -// 0x2 -> Naturally aligned 4-byte -// 0x3 -> Naturally aligned power-of-two (8 bytes to 4 GiB) -#define RVCSR_PMPCFG3_R15_A_RESET _u(0x0) -#define RVCSR_PMPCFG3_R15_A_BITS _u(0x18000000) -#define RVCSR_PMPCFG3_R15_A_MSB _u(28) -#define RVCSR_PMPCFG3_R15_A_LSB _u(27) -#define RVCSR_PMPCFG3_R15_A_ACCESS "RO" -#define RVCSR_PMPCFG3_R15_A_VALUE_OFF _u(0x0) -#define RVCSR_PMPCFG3_R15_A_VALUE_NA4 _u(0x2) -#define RVCSR_PMPCFG3_R15_A_VALUE_NAPOT _u(0x3) -// ----------------------------------------------------------------------------- -// Field : RVCSR_PMPCFG3_R15_R -// Description : Read permission for region 15. Note R and X are transposed from -// the standard bit order due to erratum RP2350-E6. -#define RVCSR_PMPCFG3_R15_R_RESET _u(0x0) -#define RVCSR_PMPCFG3_R15_R_BITS _u(0x04000000) -#define RVCSR_PMPCFG3_R15_R_MSB _u(26) -#define RVCSR_PMPCFG3_R15_R_LSB _u(26) -#define RVCSR_PMPCFG3_R15_R_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RVCSR_PMPCFG3_R15_W -// Description : Write permission for region 15 -#define RVCSR_PMPCFG3_R15_W_RESET _u(0x0) -#define RVCSR_PMPCFG3_R15_W_BITS _u(0x02000000) -#define RVCSR_PMPCFG3_R15_W_MSB _u(25) -#define RVCSR_PMPCFG3_R15_W_LSB _u(25) -#define RVCSR_PMPCFG3_R15_W_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RVCSR_PMPCFG3_R15_X -// Description : Execute permission for region 15. Note R and X are transposed -// from the standard bit order due to erratum RP2350-E6. -#define RVCSR_PMPCFG3_R15_X_RESET _u(0x0) -#define RVCSR_PMPCFG3_R15_X_BITS _u(0x01000000) -#define RVCSR_PMPCFG3_R15_X_MSB _u(24) -#define RVCSR_PMPCFG3_R15_X_LSB _u(24) -#define RVCSR_PMPCFG3_R15_X_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RVCSR_PMPCFG3_R14_L -// Description : Lock region 14, and apply it to M-mode as well as U-mode. -#define RVCSR_PMPCFG3_R14_L_RESET _u(0x0) -#define RVCSR_PMPCFG3_R14_L_BITS _u(0x00800000) -#define RVCSR_PMPCFG3_R14_L_MSB _u(23) -#define RVCSR_PMPCFG3_R14_L_LSB _u(23) -#define RVCSR_PMPCFG3_R14_L_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RVCSR_PMPCFG3_R14_A -// Description : Address matching type for region 14. Writing an unsupported -// value (TOR) will set the region to OFF. -// 0x0 -> Disable region -// 0x2 -> Naturally aligned 4-byte -// 0x3 -> Naturally aligned power-of-two (8 bytes to 4 GiB) -#define RVCSR_PMPCFG3_R14_A_RESET _u(0x0) -#define RVCSR_PMPCFG3_R14_A_BITS _u(0x00180000) -#define RVCSR_PMPCFG3_R14_A_MSB _u(20) -#define RVCSR_PMPCFG3_R14_A_LSB _u(19) -#define RVCSR_PMPCFG3_R14_A_ACCESS "RO" -#define RVCSR_PMPCFG3_R14_A_VALUE_OFF _u(0x0) -#define RVCSR_PMPCFG3_R14_A_VALUE_NA4 _u(0x2) -#define RVCSR_PMPCFG3_R14_A_VALUE_NAPOT _u(0x3) -// ----------------------------------------------------------------------------- -// Field : RVCSR_PMPCFG3_R14_R -// Description : Read permission for region 14. Note R and X are transposed from -// the standard bit order due to erratum RP2350-E6. -#define RVCSR_PMPCFG3_R14_R_RESET _u(0x0) -#define RVCSR_PMPCFG3_R14_R_BITS _u(0x00040000) -#define RVCSR_PMPCFG3_R14_R_MSB _u(18) -#define RVCSR_PMPCFG3_R14_R_LSB _u(18) -#define RVCSR_PMPCFG3_R14_R_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RVCSR_PMPCFG3_R14_W -// Description : Write permission for region 14 -#define RVCSR_PMPCFG3_R14_W_RESET _u(0x0) -#define RVCSR_PMPCFG3_R14_W_BITS _u(0x00020000) -#define RVCSR_PMPCFG3_R14_W_MSB _u(17) -#define RVCSR_PMPCFG3_R14_W_LSB _u(17) -#define RVCSR_PMPCFG3_R14_W_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RVCSR_PMPCFG3_R14_X -// Description : Execute permission for region 14. Note R and X are transposed -// from the standard bit order due to erratum RP2350-E6. -#define RVCSR_PMPCFG3_R14_X_RESET _u(0x0) -#define RVCSR_PMPCFG3_R14_X_BITS _u(0x00010000) -#define RVCSR_PMPCFG3_R14_X_MSB _u(16) -#define RVCSR_PMPCFG3_R14_X_LSB _u(16) -#define RVCSR_PMPCFG3_R14_X_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RVCSR_PMPCFG3_R13_L -// Description : Lock region 13, and apply it to M-mode as well as U-mode. -#define RVCSR_PMPCFG3_R13_L_RESET _u(0x0) -#define RVCSR_PMPCFG3_R13_L_BITS _u(0x00008000) -#define RVCSR_PMPCFG3_R13_L_MSB _u(15) -#define RVCSR_PMPCFG3_R13_L_LSB _u(15) -#define RVCSR_PMPCFG3_R13_L_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RVCSR_PMPCFG3_R13_A -// Description : Address matching type for region 13. Writing an unsupported -// value (TOR) will set the region to OFF. -// 0x0 -> Disable region -// 0x2 -> Naturally aligned 4-byte -// 0x3 -> Naturally aligned power-of-two (8 bytes to 4 GiB) -#define RVCSR_PMPCFG3_R13_A_RESET _u(0x0) -#define RVCSR_PMPCFG3_R13_A_BITS _u(0x00001800) -#define RVCSR_PMPCFG3_R13_A_MSB _u(12) -#define RVCSR_PMPCFG3_R13_A_LSB _u(11) -#define RVCSR_PMPCFG3_R13_A_ACCESS "RO" -#define RVCSR_PMPCFG3_R13_A_VALUE_OFF _u(0x0) -#define RVCSR_PMPCFG3_R13_A_VALUE_NA4 _u(0x2) -#define RVCSR_PMPCFG3_R13_A_VALUE_NAPOT _u(0x3) -// ----------------------------------------------------------------------------- -// Field : RVCSR_PMPCFG3_R13_R -// Description : Read permission for region 13. Note R and X are transposed from -// the standard bit order due to erratum RP2350-E6. -#define RVCSR_PMPCFG3_R13_R_RESET _u(0x0) -#define RVCSR_PMPCFG3_R13_R_BITS _u(0x00000400) -#define RVCSR_PMPCFG3_R13_R_MSB _u(10) -#define RVCSR_PMPCFG3_R13_R_LSB _u(10) -#define RVCSR_PMPCFG3_R13_R_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RVCSR_PMPCFG3_R13_W -// Description : Write permission for region 13 -#define RVCSR_PMPCFG3_R13_W_RESET _u(0x0) -#define RVCSR_PMPCFG3_R13_W_BITS _u(0x00000200) -#define RVCSR_PMPCFG3_R13_W_MSB _u(9) -#define RVCSR_PMPCFG3_R13_W_LSB _u(9) -#define RVCSR_PMPCFG3_R13_W_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RVCSR_PMPCFG3_R13_X -// Description : Execute permission for region 13. Note R and X are transposed -// from the standard bit order due to erratum RP2350-E6. -#define RVCSR_PMPCFG3_R13_X_RESET _u(0x0) -#define RVCSR_PMPCFG3_R13_X_BITS _u(0x00000100) -#define RVCSR_PMPCFG3_R13_X_MSB _u(8) -#define RVCSR_PMPCFG3_R13_X_LSB _u(8) -#define RVCSR_PMPCFG3_R13_X_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RVCSR_PMPCFG3_R12_L -// Description : Lock region 12, and apply it to M-mode as well as U-mode. -#define RVCSR_PMPCFG3_R12_L_RESET _u(0x0) -#define RVCSR_PMPCFG3_R12_L_BITS _u(0x00000080) -#define RVCSR_PMPCFG3_R12_L_MSB _u(7) -#define RVCSR_PMPCFG3_R12_L_LSB _u(7) -#define RVCSR_PMPCFG3_R12_L_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RVCSR_PMPCFG3_R12_A -// Description : Address matching type for region 12. Writing an unsupported -// value (TOR) will set the region to OFF. -// 0x0 -> Disable region -// 0x2 -> Naturally aligned 4-byte -// 0x3 -> Naturally aligned power-of-two (8 bytes to 4 GiB) -#define RVCSR_PMPCFG3_R12_A_RESET _u(0x0) -#define RVCSR_PMPCFG3_R12_A_BITS _u(0x00000018) -#define RVCSR_PMPCFG3_R12_A_MSB _u(4) -#define RVCSR_PMPCFG3_R12_A_LSB _u(3) -#define RVCSR_PMPCFG3_R12_A_ACCESS "RO" -#define RVCSR_PMPCFG3_R12_A_VALUE_OFF _u(0x0) -#define RVCSR_PMPCFG3_R12_A_VALUE_NA4 _u(0x2) -#define RVCSR_PMPCFG3_R12_A_VALUE_NAPOT _u(0x3) -// ----------------------------------------------------------------------------- -// Field : RVCSR_PMPCFG3_R12_R -// Description : Read permission for region 12. Note R and X are transposed from -// the standard bit order due to erratum RP2350-E6. -#define RVCSR_PMPCFG3_R12_R_RESET _u(0x0) -#define RVCSR_PMPCFG3_R12_R_BITS _u(0x00000004) -#define RVCSR_PMPCFG3_R12_R_MSB _u(2) -#define RVCSR_PMPCFG3_R12_R_LSB _u(2) -#define RVCSR_PMPCFG3_R12_R_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RVCSR_PMPCFG3_R12_W -// Description : Write permission for region 12 -#define RVCSR_PMPCFG3_R12_W_RESET _u(0x0) -#define RVCSR_PMPCFG3_R12_W_BITS _u(0x00000002) -#define RVCSR_PMPCFG3_R12_W_MSB _u(1) -#define RVCSR_PMPCFG3_R12_W_LSB _u(1) -#define RVCSR_PMPCFG3_R12_W_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RVCSR_PMPCFG3_R12_X -// Description : Execute permission for region 12. Note R and X are transposed -// from the standard bit order due to erratum RP2350-E6. -#define RVCSR_PMPCFG3_R12_X_RESET _u(0x0) -#define RVCSR_PMPCFG3_R12_X_BITS _u(0x00000001) -#define RVCSR_PMPCFG3_R12_X_MSB _u(0) -#define RVCSR_PMPCFG3_R12_X_LSB _u(0) -#define RVCSR_PMPCFG3_R12_X_ACCESS "RO" -// ============================================================================= -// Register : RVCSR_PMPADDR0 -// Description : Physical memory protection address for region 0. Note all PMP -// addresses are in units of four bytes. -#define RVCSR_PMPADDR0_OFFSET _u(0x000003b0) -#define RVCSR_PMPADDR0_BITS _u(0x3fffffff) -#define RVCSR_PMPADDR0_RESET _u(0x00000000) -#define RVCSR_PMPADDR0_MSB _u(29) -#define RVCSR_PMPADDR0_LSB _u(0) -#define RVCSR_PMPADDR0_ACCESS "RW" -// ============================================================================= -// Register : RVCSR_PMPADDR1 -// Description : Physical memory protection address for region 1. Note all PMP -// addresses are in units of four bytes. -#define RVCSR_PMPADDR1_OFFSET _u(0x000003b1) -#define RVCSR_PMPADDR1_BITS _u(0x3fffffff) -#define RVCSR_PMPADDR1_RESET _u(0x00000000) -#define RVCSR_PMPADDR1_MSB _u(29) -#define RVCSR_PMPADDR1_LSB _u(0) -#define RVCSR_PMPADDR1_ACCESS "RW" -// ============================================================================= -// Register : RVCSR_PMPADDR2 -// Description : Physical memory protection address for region 2. Note all PMP -// addresses are in units of four bytes. -#define RVCSR_PMPADDR2_OFFSET _u(0x000003b2) -#define RVCSR_PMPADDR2_BITS _u(0x3fffffff) -#define RVCSR_PMPADDR2_RESET _u(0x00000000) -#define RVCSR_PMPADDR2_MSB _u(29) -#define RVCSR_PMPADDR2_LSB _u(0) -#define RVCSR_PMPADDR2_ACCESS "RW" -// ============================================================================= -// Register : RVCSR_PMPADDR3 -// Description : Physical memory protection address for region 3. Note all PMP -// addresses are in units of four bytes. -#define RVCSR_PMPADDR3_OFFSET _u(0x000003b3) -#define RVCSR_PMPADDR3_BITS _u(0x3fffffff) -#define RVCSR_PMPADDR3_RESET _u(0x00000000) -#define RVCSR_PMPADDR3_MSB _u(29) -#define RVCSR_PMPADDR3_LSB _u(0) -#define RVCSR_PMPADDR3_ACCESS "RW" -// ============================================================================= -// Register : RVCSR_PMPADDR4 -// Description : Physical memory protection address for region 4. Note all PMP -// addresses are in units of four bytes. -#define RVCSR_PMPADDR4_OFFSET _u(0x000003b4) -#define RVCSR_PMPADDR4_BITS _u(0x3fffffff) -#define RVCSR_PMPADDR4_RESET _u(0x00000000) -#define RVCSR_PMPADDR4_MSB _u(29) -#define RVCSR_PMPADDR4_LSB _u(0) -#define RVCSR_PMPADDR4_ACCESS "RW" -// ============================================================================= -// Register : RVCSR_PMPADDR5 -// Description : Physical memory protection address for region 5. Note all PMP -// addresses are in units of four bytes. -#define RVCSR_PMPADDR5_OFFSET _u(0x000003b5) -#define RVCSR_PMPADDR5_BITS _u(0x3fffffff) -#define RVCSR_PMPADDR5_RESET _u(0x00000000) -#define RVCSR_PMPADDR5_MSB _u(29) -#define RVCSR_PMPADDR5_LSB _u(0) -#define RVCSR_PMPADDR5_ACCESS "RW" -// ============================================================================= -// Register : RVCSR_PMPADDR6 -// Description : Physical memory protection address for region 6. Note all PMP -// addresses are in units of four bytes. -#define RVCSR_PMPADDR6_OFFSET _u(0x000003b6) -#define RVCSR_PMPADDR6_BITS _u(0x3fffffff) -#define RVCSR_PMPADDR6_RESET _u(0x00000000) -#define RVCSR_PMPADDR6_MSB _u(29) -#define RVCSR_PMPADDR6_LSB _u(0) -#define RVCSR_PMPADDR6_ACCESS "RW" -// ============================================================================= -// Register : RVCSR_PMPADDR7 -// Description : Physical memory protection address for region 7. Note all PMP -// addresses are in units of four bytes. -#define RVCSR_PMPADDR7_OFFSET _u(0x000003b7) -#define RVCSR_PMPADDR7_BITS _u(0x3fffffff) -#define RVCSR_PMPADDR7_RESET _u(0x00000000) -#define RVCSR_PMPADDR7_MSB _u(29) -#define RVCSR_PMPADDR7_LSB _u(0) -#define RVCSR_PMPADDR7_ACCESS "RW" -// ============================================================================= -// Register : RVCSR_PMPADDR8 -// Description : Physical memory protection address for region 8. Note all PMP -// addresses are in units of four bytes. -// -// Hardwired to the address range `0x00000000` through -// `0x0fffffff`, which contains the boot ROM. This range is made -// accessible to User mode by default. User mode access to this -// range can be disabled using one of the dynamically configurable -// PMP regions, or using the permission registers in ACCESSCTRL. -#define RVCSR_PMPADDR8_OFFSET _u(0x000003b8) -#define RVCSR_PMPADDR8_BITS _u(0x3fffffff) -#define RVCSR_PMPADDR8_RESET _u(0x01ffffff) -#define RVCSR_PMPADDR8_MSB _u(29) -#define RVCSR_PMPADDR8_LSB _u(0) -#define RVCSR_PMPADDR8_ACCESS "RO" -// ============================================================================= -// Register : RVCSR_PMPADDR9 -// Description : Physical memory protection address for region 9. Note all PMP -// addresses are in units of four bytes. -// -// Hardwired to the address range `0x40000000` through -// `0x5fffffff`, which contains the system peripherals. This range -// is made accessible to User mode by default. User mode access to -// this range can be disabled using one of the dynamically -// configurable PMP regions, or using the permission registers in -// ACCESSCTRL. -#define RVCSR_PMPADDR9_OFFSET _u(0x000003b9) -#define RVCSR_PMPADDR9_BITS _u(0x3fffffff) -#define RVCSR_PMPADDR9_RESET _u(0x13ffffff) -#define RVCSR_PMPADDR9_MSB _u(29) -#define RVCSR_PMPADDR9_LSB _u(0) -#define RVCSR_PMPADDR9_ACCESS "RO" -// ============================================================================= -// Register : RVCSR_PMPADDR10 -// Description : Physical memory protection address for region 10. Note all PMP -// addresses are in units of four bytes. -// -// Hardwired to the address range `0xd0000000` through -// `0xdfffffff`, which contains the core-local peripherals (SIO). -// This range is made accessible to User mode by default. User -// mode access to this range can be disabled using one of the -// dynamically configurable PMP regions, or using the permission -// registers in ACCESSCTRL. -#define RVCSR_PMPADDR10_OFFSET _u(0x000003ba) -#define RVCSR_PMPADDR10_BITS _u(0x3fffffff) -#define RVCSR_PMPADDR10_RESET _u(0x35ffffff) -#define RVCSR_PMPADDR10_MSB _u(29) -#define RVCSR_PMPADDR10_LSB _u(0) -#define RVCSR_PMPADDR10_ACCESS "RO" -// ============================================================================= -// Register : RVCSR_PMPADDR11 -// Description : Physical memory protection address for region 11. Note all PMP -// addresses are in units of four bytes. -// -// Hardwired to all-zeroes. This region is not implemented. -#define RVCSR_PMPADDR11_OFFSET _u(0x000003bb) -#define RVCSR_PMPADDR11_BITS _u(0x3fffffff) -#define RVCSR_PMPADDR11_RESET _u(0x00000000) -#define RVCSR_PMPADDR11_MSB _u(29) -#define RVCSR_PMPADDR11_LSB _u(0) -#define RVCSR_PMPADDR11_ACCESS "RO" -// ============================================================================= -// Register : RVCSR_PMPADDR12 -// Description : Physical memory protection address for region 12. Note all PMP -// addresses are in units of four bytes. -// -// Hardwired to all-zeroes. This region is not implemented. -#define RVCSR_PMPADDR12_OFFSET _u(0x000003bc) -#define RVCSR_PMPADDR12_BITS _u(0x3fffffff) -#define RVCSR_PMPADDR12_RESET _u(0x00000000) -#define RVCSR_PMPADDR12_MSB _u(29) -#define RVCSR_PMPADDR12_LSB _u(0) -#define RVCSR_PMPADDR12_ACCESS "RO" -// ============================================================================= -// Register : RVCSR_PMPADDR13 -// Description : Physical memory protection address for region 13. Note all PMP -// addresses are in units of four bytes. -// -// Hardwired to all-zeroes. This region is not implemented. -#define RVCSR_PMPADDR13_OFFSET _u(0x000003bd) -#define RVCSR_PMPADDR13_BITS _u(0x3fffffff) -#define RVCSR_PMPADDR13_RESET _u(0x00000000) -#define RVCSR_PMPADDR13_MSB _u(29) -#define RVCSR_PMPADDR13_LSB _u(0) -#define RVCSR_PMPADDR13_ACCESS "RO" -// ============================================================================= -// Register : RVCSR_PMPADDR14 -// Description : Physical memory protection address for region 14. Note all PMP -// addresses are in units of four bytes. -// -// Hardwired to all-zeroes. This region is not implemented. -#define RVCSR_PMPADDR14_OFFSET _u(0x000003be) -#define RVCSR_PMPADDR14_BITS _u(0x3fffffff) -#define RVCSR_PMPADDR14_RESET _u(0x00000000) -#define RVCSR_PMPADDR14_MSB _u(29) -#define RVCSR_PMPADDR14_LSB _u(0) -#define RVCSR_PMPADDR14_ACCESS "RO" -// ============================================================================= -// Register : RVCSR_PMPADDR15 -// Description : Physical memory protection address for region 15. Note all PMP -// addresses are in units of four bytes. -// -// Hardwired to all-zeroes. This region is not implemented. -#define RVCSR_PMPADDR15_OFFSET _u(0x000003bf) -#define RVCSR_PMPADDR15_BITS _u(0x3fffffff) -#define RVCSR_PMPADDR15_RESET _u(0x00000000) -#define RVCSR_PMPADDR15_MSB _u(29) -#define RVCSR_PMPADDR15_LSB _u(0) -#define RVCSR_PMPADDR15_ACCESS "RO" -// ============================================================================= -// Register : RVCSR_TSELECT -// Description : Select trigger to be configured via `tdata1`/`tdata2` -// -// On RP2350, four instruction address triggers are implemented, -// so only the two LSBs of this register are writable. -#define RVCSR_TSELECT_OFFSET _u(0x000007a0) -#define RVCSR_TSELECT_BITS _u(0x00000003) -#define RVCSR_TSELECT_RESET _u(0x00000000) -#define RVCSR_TSELECT_MSB _u(1) -#define RVCSR_TSELECT_LSB _u(0) -#define RVCSR_TSELECT_ACCESS "RW" -// ============================================================================= -// Register : RVCSR_TDATA1 -// Description : Trigger configuration data 1 -// -// Hazard 3 only supports address/data match triggers (type=2) so -// this register description includes the `mcontrol` fields for -// this type. -// -// More precisely, Hazard3 only supports exact instruction address -// match triggers (hardware breakpoints) so many of this -// register's fields are hardwired. -#define RVCSR_TDATA1_OFFSET _u(0x000007a1) -#define RVCSR_TDATA1_BITS _u(0xffffffcf) -#define RVCSR_TDATA1_RESET _u(0x20000000) -// ----------------------------------------------------------------------------- -// Field : RVCSR_TDATA1_TYPE -// Description : Trigger type. Hardwired to type=2, meaning an address/data -// match trigger -#define RVCSR_TDATA1_TYPE_RESET _u(0x2) -#define RVCSR_TDATA1_TYPE_BITS _u(0xf0000000) -#define RVCSR_TDATA1_TYPE_MSB _u(31) -#define RVCSR_TDATA1_TYPE_LSB _u(28) -#define RVCSR_TDATA1_TYPE_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RVCSR_TDATA1_DMODE -// Description : If 0, both Debug and M-mode can write the `tdata` registers at -// the selected `tselect`. -// -// If 1, only Debug Mode can write the `tdata` registers at the -// selected `tselect`. Writes from other modes are ignored. -// -// This bit is only writable from Debug Mode -#define RVCSR_TDATA1_DMODE_RESET _u(0x0) -#define RVCSR_TDATA1_DMODE_BITS _u(0x08000000) -#define RVCSR_TDATA1_DMODE_MSB _u(27) -#define RVCSR_TDATA1_DMODE_LSB _u(27) -#define RVCSR_TDATA1_DMODE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RVCSR_TDATA1_MASKMAX -// Description : Value of 0 indicates only exact address matches are supported -#define RVCSR_TDATA1_MASKMAX_RESET _u(0x00) -#define RVCSR_TDATA1_MASKMAX_BITS _u(0x07e00000) -#define RVCSR_TDATA1_MASKMAX_MSB _u(26) -#define RVCSR_TDATA1_MASKMAX_LSB _u(21) -#define RVCSR_TDATA1_MASKMAX_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RVCSR_TDATA1_HIT -// Description : Trigger hit flag. Not implemented, hardwired to 0. -#define RVCSR_TDATA1_HIT_RESET _u(0x0) -#define RVCSR_TDATA1_HIT_BITS _u(0x00100000) -#define RVCSR_TDATA1_HIT_MSB _u(20) -#define RVCSR_TDATA1_HIT_LSB _u(20) -#define RVCSR_TDATA1_HIT_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RVCSR_TDATA1_SELECT -// Description : Hardwired value of 0 indicates that only address matches are -// supported, not data matches -#define RVCSR_TDATA1_SELECT_RESET _u(0x0) -#define RVCSR_TDATA1_SELECT_BITS _u(0x00080000) -#define RVCSR_TDATA1_SELECT_MSB _u(19) -#define RVCSR_TDATA1_SELECT_LSB _u(19) -#define RVCSR_TDATA1_SELECT_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RVCSR_TDATA1_TIMING -// Description : Hardwired value of 0 indicates that trigger fires before the -// triggering instruction executes, not afterward -#define RVCSR_TDATA1_TIMING_RESET _u(0x0) -#define RVCSR_TDATA1_TIMING_BITS _u(0x00040000) -#define RVCSR_TDATA1_TIMING_MSB _u(18) -#define RVCSR_TDATA1_TIMING_LSB _u(18) -#define RVCSR_TDATA1_TIMING_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RVCSR_TDATA1_SIZELO -// Description : Hardwired value of 0 indicates that access size matching is not -// supported -#define RVCSR_TDATA1_SIZELO_RESET _u(0x0) -#define RVCSR_TDATA1_SIZELO_BITS _u(0x00030000) -#define RVCSR_TDATA1_SIZELO_MSB _u(17) -#define RVCSR_TDATA1_SIZELO_LSB _u(16) -#define RVCSR_TDATA1_SIZELO_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RVCSR_TDATA1_ACTION -// Description : Select action to be taken when the trigger fires. -// 0x0 -> Raise a breakpoint exception, which can be handled by the M-mode exception handler -// 0x1 -> Enter debug mode. This action is only selectable when `tdata1.dmode` is 1. -#define RVCSR_TDATA1_ACTION_RESET _u(0x0) -#define RVCSR_TDATA1_ACTION_BITS _u(0x0000f000) -#define RVCSR_TDATA1_ACTION_MSB _u(15) -#define RVCSR_TDATA1_ACTION_LSB _u(12) -#define RVCSR_TDATA1_ACTION_ACCESS "RW" -#define RVCSR_TDATA1_ACTION_VALUE_EBREAK _u(0x0) -#define RVCSR_TDATA1_ACTION_VALUE_DEBUG _u(0x1) -// ----------------------------------------------------------------------------- -// Field : RVCSR_TDATA1_CHAIN -// Description : Hardwired to 0 to indicate trigger chaining is not supported. -#define RVCSR_TDATA1_CHAIN_RESET _u(0x0) -#define RVCSR_TDATA1_CHAIN_BITS _u(0x00000800) -#define RVCSR_TDATA1_CHAIN_MSB _u(11) -#define RVCSR_TDATA1_CHAIN_LSB _u(11) -#define RVCSR_TDATA1_CHAIN_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RVCSR_TDATA1_MATCH -// Description : Hardwired to 0 to indicate match is always on the full address -// specified by `tdata2` -#define RVCSR_TDATA1_MATCH_RESET _u(0x0) -#define RVCSR_TDATA1_MATCH_BITS _u(0x00000780) -#define RVCSR_TDATA1_MATCH_MSB _u(10) -#define RVCSR_TDATA1_MATCH_LSB _u(7) -#define RVCSR_TDATA1_MATCH_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RVCSR_TDATA1_M -// Description : When set, enable this trigger in M-mode -#define RVCSR_TDATA1_M_RESET _u(0x0) -#define RVCSR_TDATA1_M_BITS _u(0x00000040) -#define RVCSR_TDATA1_M_MSB _u(6) -#define RVCSR_TDATA1_M_LSB _u(6) -#define RVCSR_TDATA1_M_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RVCSR_TDATA1_U -// Description : When set, enable this trigger in U-mode -#define RVCSR_TDATA1_U_RESET _u(0x0) -#define RVCSR_TDATA1_U_BITS _u(0x00000008) -#define RVCSR_TDATA1_U_MSB _u(3) -#define RVCSR_TDATA1_U_LSB _u(3) -#define RVCSR_TDATA1_U_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RVCSR_TDATA1_EXECUTE -// Description : When set, the trigger fires on the address of an instruction -// that is executed. -#define RVCSR_TDATA1_EXECUTE_RESET _u(0x0) -#define RVCSR_TDATA1_EXECUTE_BITS _u(0x00000004) -#define RVCSR_TDATA1_EXECUTE_MSB _u(2) -#define RVCSR_TDATA1_EXECUTE_LSB _u(2) -#define RVCSR_TDATA1_EXECUTE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RVCSR_TDATA1_STORE -// Description : Hardwired to 0 to indicate store address/data triggers are not -// supported -#define RVCSR_TDATA1_STORE_RESET _u(0x0) -#define RVCSR_TDATA1_STORE_BITS _u(0x00000002) -#define RVCSR_TDATA1_STORE_MSB _u(1) -#define RVCSR_TDATA1_STORE_LSB _u(1) -#define RVCSR_TDATA1_STORE_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RVCSR_TDATA1_LOAD -// Description : Hardwired to 0 to indicate load address/data triggers are not -// supported -#define RVCSR_TDATA1_LOAD_RESET _u(0x0) -#define RVCSR_TDATA1_LOAD_BITS _u(0x00000001) -#define RVCSR_TDATA1_LOAD_MSB _u(0) -#define RVCSR_TDATA1_LOAD_LSB _u(0) -#define RVCSR_TDATA1_LOAD_ACCESS "RO" -// ============================================================================= -// Register : RVCSR_TDATA2 -// Description : Trigger configuration data 2 -// -// Contains the address for instruction address triggers (hardware -// breakpoints) -#define RVCSR_TDATA2_OFFSET _u(0x000007a2) -#define RVCSR_TDATA2_BITS _u(0xffffffff) -#define RVCSR_TDATA2_RESET _u(0x00000000) -#define RVCSR_TDATA2_MSB _u(31) -#define RVCSR_TDATA2_LSB _u(0) -#define RVCSR_TDATA2_ACCESS "RW" -// ============================================================================= -// Register : RVCSR_DCSR -// Description : Debug control and status register. Access outside of Debug Mode -// will cause an illegal instruction exception. -#define RVCSR_DCSR_OFFSET _u(0x000007b0) -#define RVCSR_DCSR_BITS _u(0xf0009fc7) -#define RVCSR_DCSR_RESET _u(0x40000603) -// ----------------------------------------------------------------------------- -// Field : RVCSR_DCSR_XDEBUGVER -// Description : Hardwired to 4: external debug support as per RISC-V 0.13.2 -// debug specification. -#define RVCSR_DCSR_XDEBUGVER_RESET _u(0x4) -#define RVCSR_DCSR_XDEBUGVER_BITS _u(0xf0000000) -#define RVCSR_DCSR_XDEBUGVER_MSB _u(31) -#define RVCSR_DCSR_XDEBUGVER_LSB _u(28) -#define RVCSR_DCSR_XDEBUGVER_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RVCSR_DCSR_EBREAKM -// Description : When 1, `ebreak` instructions executed in M-mode will break to -// Debug Mode instead of trapping -#define RVCSR_DCSR_EBREAKM_RESET _u(0x0) -#define RVCSR_DCSR_EBREAKM_BITS _u(0x00008000) -#define RVCSR_DCSR_EBREAKM_MSB _u(15) -#define RVCSR_DCSR_EBREAKM_LSB _u(15) -#define RVCSR_DCSR_EBREAKM_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RVCSR_DCSR_EBREAKU -// Description : When 1, `ebreak` instructions executed in U-mode will break to -// Debug Mode instead of trapping. -#define RVCSR_DCSR_EBREAKU_RESET _u(0x0) -#define RVCSR_DCSR_EBREAKU_BITS _u(0x00001000) -#define RVCSR_DCSR_EBREAKU_MSB _u(12) -#define RVCSR_DCSR_EBREAKU_LSB _u(12) -#define RVCSR_DCSR_EBREAKU_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RVCSR_DCSR_STEPIE -// Description : Hardwired to 0: no interrupts are taken during hardware single- -// stepping. -#define RVCSR_DCSR_STEPIE_RESET _u(0x0) -#define RVCSR_DCSR_STEPIE_BITS _u(0x00000800) -#define RVCSR_DCSR_STEPIE_MSB _u(11) -#define RVCSR_DCSR_STEPIE_LSB _u(11) -#define RVCSR_DCSR_STEPIE_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RVCSR_DCSR_STOPCOUNT -// Description : Hardwired to 1: `mcycle`/`mcycleh` and `minstret`/`minstreth` -// do not increment in Debug Mode. -#define RVCSR_DCSR_STOPCOUNT_RESET _u(0x1) -#define RVCSR_DCSR_STOPCOUNT_BITS _u(0x00000400) -#define RVCSR_DCSR_STOPCOUNT_MSB _u(10) -#define RVCSR_DCSR_STOPCOUNT_LSB _u(10) -#define RVCSR_DCSR_STOPCOUNT_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RVCSR_DCSR_STOPTIME -// Description : Hardwired to 1: core-local timers don't increment in debug -// mode. External timers (e.g. hart-shared) may be configured to -// ignore this. -#define RVCSR_DCSR_STOPTIME_RESET _u(0x1) -#define RVCSR_DCSR_STOPTIME_BITS _u(0x00000200) -#define RVCSR_DCSR_STOPTIME_MSB _u(9) -#define RVCSR_DCSR_STOPTIME_LSB _u(9) -#define RVCSR_DCSR_STOPTIME_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RVCSR_DCSR_CAUSE -// Description : Set by hardware when entering debug mode. -// 0x1 -> An ebreak instruction was executed when the relevant `dcsr.ebreakx` bit was set. -// 0x2 -> The trigger module caused a breakpoint exception. -// 0x3 -> Processor entered Debug Mode due to a halt request, or a reset-halt request present when the core reset was released. -// 0x4 -> Processor entered Debug Mode after executing one instruction with single-stepping enabled. -#define RVCSR_DCSR_CAUSE_RESET _u(0x0) -#define RVCSR_DCSR_CAUSE_BITS _u(0x000001c0) -#define RVCSR_DCSR_CAUSE_MSB _u(8) -#define RVCSR_DCSR_CAUSE_LSB _u(6) -#define RVCSR_DCSR_CAUSE_ACCESS "RO" -#define RVCSR_DCSR_CAUSE_VALUE_EBREAK _u(0x1) -#define RVCSR_DCSR_CAUSE_VALUE_TRIGGER _u(0x2) -#define RVCSR_DCSR_CAUSE_VALUE_HALTREQ _u(0x3) -#define RVCSR_DCSR_CAUSE_VALUE_STEP _u(0x4) -// ----------------------------------------------------------------------------- -// Field : RVCSR_DCSR_STEP -// Description : When 1, re-enter Debug Mode after each instruction executed in -// M-mode or U-mode. -#define RVCSR_DCSR_STEP_RESET _u(0x0) -#define RVCSR_DCSR_STEP_BITS _u(0x00000004) -#define RVCSR_DCSR_STEP_MSB _u(2) -#define RVCSR_DCSR_STEP_LSB _u(2) -#define RVCSR_DCSR_STEP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RVCSR_DCSR_PRV -// Description : Read the privilege mode the core was in when entering Debug -// Mode, and set the privilege mode the core will execute in when -// returning from Debug Mode. -#define RVCSR_DCSR_PRV_RESET _u(0x3) -#define RVCSR_DCSR_PRV_BITS _u(0x00000003) -#define RVCSR_DCSR_PRV_MSB _u(1) -#define RVCSR_DCSR_PRV_LSB _u(0) -#define RVCSR_DCSR_PRV_ACCESS "RW" -// ============================================================================= -// Register : RVCSR_DPC -// Description : Debug program counter. When entering Debug Mode, `dpc` samples -// the current program counter, e.g. the address of an `ebreak` -// which caused Debug Mode entry. When leaving debug mode, the -// processor jumps to `dpc`. The host may read/write this register -// whilst in Debug Mode. -#define RVCSR_DPC_OFFSET _u(0x000007b1) -#define RVCSR_DPC_BITS _u(0xfffffffe) -#define RVCSR_DPC_RESET _u(0x00000000) -#define RVCSR_DPC_MSB _u(31) -#define RVCSR_DPC_LSB _u(1) -#define RVCSR_DPC_ACCESS "RW" -// ============================================================================= -// Register : RVCSR_MCYCLE -// Description : Machine-mode cycle counter, low half -// Counts up once per cycle, when `mcountinhibit.cy` is 0. -// Disabled by default to save power. -#define RVCSR_MCYCLE_OFFSET _u(0x00000b00) -#define RVCSR_MCYCLE_BITS _u(0xffffffff) -#define RVCSR_MCYCLE_RESET _u(0x00000000) -#define RVCSR_MCYCLE_MSB _u(31) -#define RVCSR_MCYCLE_LSB _u(0) -#define RVCSR_MCYCLE_ACCESS "RW" -// ============================================================================= -// Register : RVCSR_MINSTRET -// Description : Machine-mode instruction retire counter, low half -// Counts up once per instruction, when `mcountinhibit.ir` is 0. -// Disabled by default to save power. -#define RVCSR_MINSTRET_OFFSET _u(0x00000b02) -#define RVCSR_MINSTRET_BITS _u(0xffffffff) -#define RVCSR_MINSTRET_RESET _u(0x00000000) -#define RVCSR_MINSTRET_MSB _u(31) -#define RVCSR_MINSTRET_LSB _u(0) -#define RVCSR_MINSTRET_ACCESS "RW" -// ============================================================================= -// Register : RVCSR_MHPMCOUNTER3 -// Description : Extended performance counter, hardwired to 0. -#define RVCSR_MHPMCOUNTER3_OFFSET _u(0x00000b03) -#define RVCSR_MHPMCOUNTER3_BITS _u(0xffffffff) -#define RVCSR_MHPMCOUNTER3_RESET _u(0x00000000) -#define RVCSR_MHPMCOUNTER3_MSB _u(31) -#define RVCSR_MHPMCOUNTER3_LSB _u(0) -#define RVCSR_MHPMCOUNTER3_ACCESS "RO" -// ============================================================================= -// Register : RVCSR_MHPMCOUNTER4 -// Description : Extended performance counter, hardwired to 0. -#define RVCSR_MHPMCOUNTER4_OFFSET _u(0x00000b04) -#define RVCSR_MHPMCOUNTER4_BITS _u(0xffffffff) -#define RVCSR_MHPMCOUNTER4_RESET _u(0x00000000) -#define RVCSR_MHPMCOUNTER4_MSB _u(31) -#define RVCSR_MHPMCOUNTER4_LSB _u(0) -#define RVCSR_MHPMCOUNTER4_ACCESS "RO" -// ============================================================================= -// Register : RVCSR_MHPMCOUNTER5 -// Description : Extended performance counter, hardwired to 0. -#define RVCSR_MHPMCOUNTER5_OFFSET _u(0x00000b05) -#define RVCSR_MHPMCOUNTER5_BITS _u(0xffffffff) -#define RVCSR_MHPMCOUNTER5_RESET _u(0x00000000) -#define RVCSR_MHPMCOUNTER5_MSB _u(31) -#define RVCSR_MHPMCOUNTER5_LSB _u(0) -#define RVCSR_MHPMCOUNTER5_ACCESS "RO" -// ============================================================================= -// Register : RVCSR_MHPMCOUNTER6 -// Description : Extended performance counter, hardwired to 0. -#define RVCSR_MHPMCOUNTER6_OFFSET _u(0x00000b06) -#define RVCSR_MHPMCOUNTER6_BITS _u(0xffffffff) -#define RVCSR_MHPMCOUNTER6_RESET _u(0x00000000) -#define RVCSR_MHPMCOUNTER6_MSB _u(31) -#define RVCSR_MHPMCOUNTER6_LSB _u(0) -#define RVCSR_MHPMCOUNTER6_ACCESS "RO" -// ============================================================================= -// Register : RVCSR_MHPMCOUNTER7 -// Description : Extended performance counter, hardwired to 0. -#define RVCSR_MHPMCOUNTER7_OFFSET _u(0x00000b07) -#define RVCSR_MHPMCOUNTER7_BITS _u(0xffffffff) -#define RVCSR_MHPMCOUNTER7_RESET _u(0x00000000) -#define RVCSR_MHPMCOUNTER7_MSB _u(31) -#define RVCSR_MHPMCOUNTER7_LSB _u(0) -#define RVCSR_MHPMCOUNTER7_ACCESS "RO" -// ============================================================================= -// Register : RVCSR_MHPMCOUNTER8 -// Description : Extended performance counter, hardwired to 0. -#define RVCSR_MHPMCOUNTER8_OFFSET _u(0x00000b08) -#define RVCSR_MHPMCOUNTER8_BITS _u(0xffffffff) -#define RVCSR_MHPMCOUNTER8_RESET _u(0x00000000) -#define RVCSR_MHPMCOUNTER8_MSB _u(31) -#define RVCSR_MHPMCOUNTER8_LSB _u(0) -#define RVCSR_MHPMCOUNTER8_ACCESS "RO" -// ============================================================================= -// Register : RVCSR_MHPMCOUNTER9 -// Description : Extended performance counter, hardwired to 0. -#define RVCSR_MHPMCOUNTER9_OFFSET _u(0x00000b09) -#define RVCSR_MHPMCOUNTER9_BITS _u(0xffffffff) -#define RVCSR_MHPMCOUNTER9_RESET _u(0x00000000) -#define RVCSR_MHPMCOUNTER9_MSB _u(31) -#define RVCSR_MHPMCOUNTER9_LSB _u(0) -#define RVCSR_MHPMCOUNTER9_ACCESS "RO" -// ============================================================================= -// Register : RVCSR_MHPMCOUNTER10 -// Description : Extended performance counter, hardwired to 0. -#define RVCSR_MHPMCOUNTER10_OFFSET _u(0x00000b0a) -#define RVCSR_MHPMCOUNTER10_BITS _u(0xffffffff) -#define RVCSR_MHPMCOUNTER10_RESET _u(0x00000000) -#define RVCSR_MHPMCOUNTER10_MSB _u(31) -#define RVCSR_MHPMCOUNTER10_LSB _u(0) -#define RVCSR_MHPMCOUNTER10_ACCESS "RO" -// ============================================================================= -// Register : RVCSR_MHPMCOUNTER11 -// Description : Extended performance counter, hardwired to 0. -#define RVCSR_MHPMCOUNTER11_OFFSET _u(0x00000b0b) -#define RVCSR_MHPMCOUNTER11_BITS _u(0xffffffff) -#define RVCSR_MHPMCOUNTER11_RESET _u(0x00000000) -#define RVCSR_MHPMCOUNTER11_MSB _u(31) -#define RVCSR_MHPMCOUNTER11_LSB _u(0) -#define RVCSR_MHPMCOUNTER11_ACCESS "RO" -// ============================================================================= -// Register : RVCSR_MHPMCOUNTER12 -// Description : Extended performance counter, hardwired to 0. -#define RVCSR_MHPMCOUNTER12_OFFSET _u(0x00000b0c) -#define RVCSR_MHPMCOUNTER12_BITS _u(0xffffffff) -#define RVCSR_MHPMCOUNTER12_RESET _u(0x00000000) -#define RVCSR_MHPMCOUNTER12_MSB _u(31) -#define RVCSR_MHPMCOUNTER12_LSB _u(0) -#define RVCSR_MHPMCOUNTER12_ACCESS "RO" -// ============================================================================= -// Register : RVCSR_MHPMCOUNTER13 -// Description : Extended performance counter, hardwired to 0. -#define RVCSR_MHPMCOUNTER13_OFFSET _u(0x00000b0d) -#define RVCSR_MHPMCOUNTER13_BITS _u(0xffffffff) -#define RVCSR_MHPMCOUNTER13_RESET _u(0x00000000) -#define RVCSR_MHPMCOUNTER13_MSB _u(31) -#define RVCSR_MHPMCOUNTER13_LSB _u(0) -#define RVCSR_MHPMCOUNTER13_ACCESS "RO" -// ============================================================================= -// Register : RVCSR_MHPMCOUNTER14 -// Description : Extended performance counter, hardwired to 0. -#define RVCSR_MHPMCOUNTER14_OFFSET _u(0x00000b0e) -#define RVCSR_MHPMCOUNTER14_BITS _u(0xffffffff) -#define RVCSR_MHPMCOUNTER14_RESET _u(0x00000000) -#define RVCSR_MHPMCOUNTER14_MSB _u(31) -#define RVCSR_MHPMCOUNTER14_LSB _u(0) -#define RVCSR_MHPMCOUNTER14_ACCESS "RO" -// ============================================================================= -// Register : RVCSR_MHPMCOUNTER15 -// Description : Extended performance counter, hardwired to 0. -#define RVCSR_MHPMCOUNTER15_OFFSET _u(0x00000b0f) -#define RVCSR_MHPMCOUNTER15_BITS _u(0xffffffff) -#define RVCSR_MHPMCOUNTER15_RESET _u(0x00000000) -#define RVCSR_MHPMCOUNTER15_MSB _u(31) -#define RVCSR_MHPMCOUNTER15_LSB _u(0) -#define RVCSR_MHPMCOUNTER15_ACCESS "RO" -// ============================================================================= -// Register : RVCSR_MHPMCOUNTER16 -// Description : Extended performance counter, hardwired to 0. -#define RVCSR_MHPMCOUNTER16_OFFSET _u(0x00000b10) -#define RVCSR_MHPMCOUNTER16_BITS _u(0xffffffff) -#define RVCSR_MHPMCOUNTER16_RESET _u(0x00000000) -#define RVCSR_MHPMCOUNTER16_MSB _u(31) -#define RVCSR_MHPMCOUNTER16_LSB _u(0) -#define RVCSR_MHPMCOUNTER16_ACCESS "RO" -// ============================================================================= -// Register : RVCSR_MHPMCOUNTER17 -// Description : Extended performance counter, hardwired to 0. -#define RVCSR_MHPMCOUNTER17_OFFSET _u(0x00000b11) -#define RVCSR_MHPMCOUNTER17_BITS _u(0xffffffff) -#define RVCSR_MHPMCOUNTER17_RESET _u(0x00000000) -#define RVCSR_MHPMCOUNTER17_MSB _u(31) -#define RVCSR_MHPMCOUNTER17_LSB _u(0) -#define RVCSR_MHPMCOUNTER17_ACCESS "RO" -// ============================================================================= -// Register : RVCSR_MHPMCOUNTER18 -// Description : Extended performance counter, hardwired to 0. -#define RVCSR_MHPMCOUNTER18_OFFSET _u(0x00000b12) -#define RVCSR_MHPMCOUNTER18_BITS _u(0xffffffff) -#define RVCSR_MHPMCOUNTER18_RESET _u(0x00000000) -#define RVCSR_MHPMCOUNTER18_MSB _u(31) -#define RVCSR_MHPMCOUNTER18_LSB _u(0) -#define RVCSR_MHPMCOUNTER18_ACCESS "RO" -// ============================================================================= -// Register : RVCSR_MHPMCOUNTER19 -// Description : Extended performance counter, hardwired to 0. -#define RVCSR_MHPMCOUNTER19_OFFSET _u(0x00000b13) -#define RVCSR_MHPMCOUNTER19_BITS _u(0xffffffff) -#define RVCSR_MHPMCOUNTER19_RESET _u(0x00000000) -#define RVCSR_MHPMCOUNTER19_MSB _u(31) -#define RVCSR_MHPMCOUNTER19_LSB _u(0) -#define RVCSR_MHPMCOUNTER19_ACCESS "RO" -// ============================================================================= -// Register : RVCSR_MHPMCOUNTER20 -// Description : Extended performance counter, hardwired to 0. -#define RVCSR_MHPMCOUNTER20_OFFSET _u(0x00000b14) -#define RVCSR_MHPMCOUNTER20_BITS _u(0xffffffff) -#define RVCSR_MHPMCOUNTER20_RESET _u(0x00000000) -#define RVCSR_MHPMCOUNTER20_MSB _u(31) -#define RVCSR_MHPMCOUNTER20_LSB _u(0) -#define RVCSR_MHPMCOUNTER20_ACCESS "RO" -// ============================================================================= -// Register : RVCSR_MHPMCOUNTER21 -// Description : Extended performance counter, hardwired to 0. -#define RVCSR_MHPMCOUNTER21_OFFSET _u(0x00000b15) -#define RVCSR_MHPMCOUNTER21_BITS _u(0xffffffff) -#define RVCSR_MHPMCOUNTER21_RESET _u(0x00000000) -#define RVCSR_MHPMCOUNTER21_MSB _u(31) -#define RVCSR_MHPMCOUNTER21_LSB _u(0) -#define RVCSR_MHPMCOUNTER21_ACCESS "RO" -// ============================================================================= -// Register : RVCSR_MHPMCOUNTER22 -// Description : Extended performance counter, hardwired to 0. -#define RVCSR_MHPMCOUNTER22_OFFSET _u(0x00000b16) -#define RVCSR_MHPMCOUNTER22_BITS _u(0xffffffff) -#define RVCSR_MHPMCOUNTER22_RESET _u(0x00000000) -#define RVCSR_MHPMCOUNTER22_MSB _u(31) -#define RVCSR_MHPMCOUNTER22_LSB _u(0) -#define RVCSR_MHPMCOUNTER22_ACCESS "RO" -// ============================================================================= -// Register : RVCSR_MHPMCOUNTER23 -// Description : Extended performance counter, hardwired to 0. -#define RVCSR_MHPMCOUNTER23_OFFSET _u(0x00000b17) -#define RVCSR_MHPMCOUNTER23_BITS _u(0xffffffff) -#define RVCSR_MHPMCOUNTER23_RESET _u(0x00000000) -#define RVCSR_MHPMCOUNTER23_MSB _u(31) -#define RVCSR_MHPMCOUNTER23_LSB _u(0) -#define RVCSR_MHPMCOUNTER23_ACCESS "RO" -// ============================================================================= -// Register : RVCSR_MHPMCOUNTER24 -// Description : Extended performance counter, hardwired to 0. -#define RVCSR_MHPMCOUNTER24_OFFSET _u(0x00000b18) -#define RVCSR_MHPMCOUNTER24_BITS _u(0xffffffff) -#define RVCSR_MHPMCOUNTER24_RESET _u(0x00000000) -#define RVCSR_MHPMCOUNTER24_MSB _u(31) -#define RVCSR_MHPMCOUNTER24_LSB _u(0) -#define RVCSR_MHPMCOUNTER24_ACCESS "RO" -// ============================================================================= -// Register : RVCSR_MHPMCOUNTER25 -// Description : Extended performance counter, hardwired to 0. -#define RVCSR_MHPMCOUNTER25_OFFSET _u(0x00000b19) -#define RVCSR_MHPMCOUNTER25_BITS _u(0xffffffff) -#define RVCSR_MHPMCOUNTER25_RESET _u(0x00000000) -#define RVCSR_MHPMCOUNTER25_MSB _u(31) -#define RVCSR_MHPMCOUNTER25_LSB _u(0) -#define RVCSR_MHPMCOUNTER25_ACCESS "RO" -// ============================================================================= -// Register : RVCSR_MHPMCOUNTER26 -// Description : Extended performance counter, hardwired to 0. -#define RVCSR_MHPMCOUNTER26_OFFSET _u(0x00000b1a) -#define RVCSR_MHPMCOUNTER26_BITS _u(0xffffffff) -#define RVCSR_MHPMCOUNTER26_RESET _u(0x00000000) -#define RVCSR_MHPMCOUNTER26_MSB _u(31) -#define RVCSR_MHPMCOUNTER26_LSB _u(0) -#define RVCSR_MHPMCOUNTER26_ACCESS "RO" -// ============================================================================= -// Register : RVCSR_MHPMCOUNTER27 -// Description : Extended performance counter, hardwired to 0. -#define RVCSR_MHPMCOUNTER27_OFFSET _u(0x00000b1b) -#define RVCSR_MHPMCOUNTER27_BITS _u(0xffffffff) -#define RVCSR_MHPMCOUNTER27_RESET _u(0x00000000) -#define RVCSR_MHPMCOUNTER27_MSB _u(31) -#define RVCSR_MHPMCOUNTER27_LSB _u(0) -#define RVCSR_MHPMCOUNTER27_ACCESS "RO" -// ============================================================================= -// Register : RVCSR_MHPMCOUNTER28 -// Description : Extended performance counter, hardwired to 0. -#define RVCSR_MHPMCOUNTER28_OFFSET _u(0x00000b1c) -#define RVCSR_MHPMCOUNTER28_BITS _u(0xffffffff) -#define RVCSR_MHPMCOUNTER28_RESET _u(0x00000000) -#define RVCSR_MHPMCOUNTER28_MSB _u(31) -#define RVCSR_MHPMCOUNTER28_LSB _u(0) -#define RVCSR_MHPMCOUNTER28_ACCESS "RO" -// ============================================================================= -// Register : RVCSR_MHPMCOUNTER29 -// Description : Extended performance counter, hardwired to 0. -#define RVCSR_MHPMCOUNTER29_OFFSET _u(0x00000b1d) -#define RVCSR_MHPMCOUNTER29_BITS _u(0xffffffff) -#define RVCSR_MHPMCOUNTER29_RESET _u(0x00000000) -#define RVCSR_MHPMCOUNTER29_MSB _u(31) -#define RVCSR_MHPMCOUNTER29_LSB _u(0) -#define RVCSR_MHPMCOUNTER29_ACCESS "RO" -// ============================================================================= -// Register : RVCSR_MHPMCOUNTER30 -// Description : Extended performance counter, hardwired to 0. -#define RVCSR_MHPMCOUNTER30_OFFSET _u(0x00000b1e) -#define RVCSR_MHPMCOUNTER30_BITS _u(0xffffffff) -#define RVCSR_MHPMCOUNTER30_RESET _u(0x00000000) -#define RVCSR_MHPMCOUNTER30_MSB _u(31) -#define RVCSR_MHPMCOUNTER30_LSB _u(0) -#define RVCSR_MHPMCOUNTER30_ACCESS "RO" -// ============================================================================= -// Register : RVCSR_MHPMCOUNTER31 -// Description : Extended performance counter, hardwired to 0. -#define RVCSR_MHPMCOUNTER31_OFFSET _u(0x00000b1f) -#define RVCSR_MHPMCOUNTER31_BITS _u(0xffffffff) -#define RVCSR_MHPMCOUNTER31_RESET _u(0x00000000) -#define RVCSR_MHPMCOUNTER31_MSB _u(31) -#define RVCSR_MHPMCOUNTER31_LSB _u(0) -#define RVCSR_MHPMCOUNTER31_ACCESS "RO" -// ============================================================================= -// Register : RVCSR_MCYCLEH -// Description : Machine-mode cycle counter, high half -// Counts up once per 1 << 32 cycles, when `mcountinhibit.cy` is -// 0. Disabled by default to save power. -#define RVCSR_MCYCLEH_OFFSET _u(0x00000b80) -#define RVCSR_MCYCLEH_BITS _u(0xffffffff) -#define RVCSR_MCYCLEH_RESET _u(0x00000000) -#define RVCSR_MCYCLEH_MSB _u(31) -#define RVCSR_MCYCLEH_LSB _u(0) -#define RVCSR_MCYCLEH_ACCESS "RW" -// ============================================================================= -// Register : RVCSR_MINSTRETH -// Description : Machine-mode instruction retire counter, low half -// Counts up once per 1 << 32 instructions, when -// `mcountinhibit.ir` is 0. Disabled by default to save power. -#define RVCSR_MINSTRETH_OFFSET _u(0x00000b82) -#define RVCSR_MINSTRETH_BITS _u(0xffffffff) -#define RVCSR_MINSTRETH_RESET _u(0x00000000) -#define RVCSR_MINSTRETH_MSB _u(31) -#define RVCSR_MINSTRETH_LSB _u(0) -#define RVCSR_MINSTRETH_ACCESS "RW" -// ============================================================================= -// Register : RVCSR_MHPMCOUNTER3H -// Description : Extended performance counter, hardwired to 0. -#define RVCSR_MHPMCOUNTER3H_OFFSET _u(0x00000b83) -#define RVCSR_MHPMCOUNTER3H_BITS _u(0xffffffff) -#define RVCSR_MHPMCOUNTER3H_RESET _u(0x00000000) -#define RVCSR_MHPMCOUNTER3H_MSB _u(31) -#define RVCSR_MHPMCOUNTER3H_LSB _u(0) -#define RVCSR_MHPMCOUNTER3H_ACCESS "RO" -// ============================================================================= -// Register : RVCSR_MHPMCOUNTER4H -// Description : Extended performance counter, hardwired to 0. -#define RVCSR_MHPMCOUNTER4H_OFFSET _u(0x00000b84) -#define RVCSR_MHPMCOUNTER4H_BITS _u(0xffffffff) -#define RVCSR_MHPMCOUNTER4H_RESET _u(0x00000000) -#define RVCSR_MHPMCOUNTER4H_MSB _u(31) -#define RVCSR_MHPMCOUNTER4H_LSB _u(0) -#define RVCSR_MHPMCOUNTER4H_ACCESS "RO" -// ============================================================================= -// Register : RVCSR_MHPMCOUNTER5H -// Description : Extended performance counter, hardwired to 0. -#define RVCSR_MHPMCOUNTER5H_OFFSET _u(0x00000b85) -#define RVCSR_MHPMCOUNTER5H_BITS _u(0xffffffff) -#define RVCSR_MHPMCOUNTER5H_RESET _u(0x00000000) -#define RVCSR_MHPMCOUNTER5H_MSB _u(31) -#define RVCSR_MHPMCOUNTER5H_LSB _u(0) -#define RVCSR_MHPMCOUNTER5H_ACCESS "RO" -// ============================================================================= -// Register : RVCSR_MHPMCOUNTER6H -// Description : Extended performance counter, hardwired to 0. -#define RVCSR_MHPMCOUNTER6H_OFFSET _u(0x00000b86) -#define RVCSR_MHPMCOUNTER6H_BITS _u(0xffffffff) -#define RVCSR_MHPMCOUNTER6H_RESET _u(0x00000000) -#define RVCSR_MHPMCOUNTER6H_MSB _u(31) -#define RVCSR_MHPMCOUNTER6H_LSB _u(0) -#define RVCSR_MHPMCOUNTER6H_ACCESS "RO" -// ============================================================================= -// Register : RVCSR_MHPMCOUNTER7H -// Description : Extended performance counter, hardwired to 0. -#define RVCSR_MHPMCOUNTER7H_OFFSET _u(0x00000b87) -#define RVCSR_MHPMCOUNTER7H_BITS _u(0xffffffff) -#define RVCSR_MHPMCOUNTER7H_RESET _u(0x00000000) -#define RVCSR_MHPMCOUNTER7H_MSB _u(31) -#define RVCSR_MHPMCOUNTER7H_LSB _u(0) -#define RVCSR_MHPMCOUNTER7H_ACCESS "RO" -// ============================================================================= -// Register : RVCSR_MHPMCOUNTER8H -// Description : Extended performance counter, hardwired to 0. -#define RVCSR_MHPMCOUNTER8H_OFFSET _u(0x00000b88) -#define RVCSR_MHPMCOUNTER8H_BITS _u(0xffffffff) -#define RVCSR_MHPMCOUNTER8H_RESET _u(0x00000000) -#define RVCSR_MHPMCOUNTER8H_MSB _u(31) -#define RVCSR_MHPMCOUNTER8H_LSB _u(0) -#define RVCSR_MHPMCOUNTER8H_ACCESS "RO" -// ============================================================================= -// Register : RVCSR_MHPMCOUNTER9H -// Description : Extended performance counter, hardwired to 0. -#define RVCSR_MHPMCOUNTER9H_OFFSET _u(0x00000b89) -#define RVCSR_MHPMCOUNTER9H_BITS _u(0xffffffff) -#define RVCSR_MHPMCOUNTER9H_RESET _u(0x00000000) -#define RVCSR_MHPMCOUNTER9H_MSB _u(31) -#define RVCSR_MHPMCOUNTER9H_LSB _u(0) -#define RVCSR_MHPMCOUNTER9H_ACCESS "RO" -// ============================================================================= -// Register : RVCSR_MHPMCOUNTER10H -// Description : Extended performance counter, hardwired to 0. -#define RVCSR_MHPMCOUNTER10H_OFFSET _u(0x00000b8a) -#define RVCSR_MHPMCOUNTER10H_BITS _u(0xffffffff) -#define RVCSR_MHPMCOUNTER10H_RESET _u(0x00000000) -#define RVCSR_MHPMCOUNTER10H_MSB _u(31) -#define RVCSR_MHPMCOUNTER10H_LSB _u(0) -#define RVCSR_MHPMCOUNTER10H_ACCESS "RO" -// ============================================================================= -// Register : RVCSR_MHPMCOUNTER11H -// Description : Extended performance counter, hardwired to 0. -#define RVCSR_MHPMCOUNTER11H_OFFSET _u(0x00000b8b) -#define RVCSR_MHPMCOUNTER11H_BITS _u(0xffffffff) -#define RVCSR_MHPMCOUNTER11H_RESET _u(0x00000000) -#define RVCSR_MHPMCOUNTER11H_MSB _u(31) -#define RVCSR_MHPMCOUNTER11H_LSB _u(0) -#define RVCSR_MHPMCOUNTER11H_ACCESS "RO" -// ============================================================================= -// Register : RVCSR_MHPMCOUNTER12H -// Description : Extended performance counter, hardwired to 0. -#define RVCSR_MHPMCOUNTER12H_OFFSET _u(0x00000b8c) -#define RVCSR_MHPMCOUNTER12H_BITS _u(0xffffffff) -#define RVCSR_MHPMCOUNTER12H_RESET _u(0x00000000) -#define RVCSR_MHPMCOUNTER12H_MSB _u(31) -#define RVCSR_MHPMCOUNTER12H_LSB _u(0) -#define RVCSR_MHPMCOUNTER12H_ACCESS "RO" -// ============================================================================= -// Register : RVCSR_MHPMCOUNTER13H -// Description : Extended performance counter, hardwired to 0. -#define RVCSR_MHPMCOUNTER13H_OFFSET _u(0x00000b8d) -#define RVCSR_MHPMCOUNTER13H_BITS _u(0xffffffff) -#define RVCSR_MHPMCOUNTER13H_RESET _u(0x00000000) -#define RVCSR_MHPMCOUNTER13H_MSB _u(31) -#define RVCSR_MHPMCOUNTER13H_LSB _u(0) -#define RVCSR_MHPMCOUNTER13H_ACCESS "RO" -// ============================================================================= -// Register : RVCSR_MHPMCOUNTER14H -// Description : Extended performance counter, hardwired to 0. -#define RVCSR_MHPMCOUNTER14H_OFFSET _u(0x00000b8e) -#define RVCSR_MHPMCOUNTER14H_BITS _u(0xffffffff) -#define RVCSR_MHPMCOUNTER14H_RESET _u(0x00000000) -#define RVCSR_MHPMCOUNTER14H_MSB _u(31) -#define RVCSR_MHPMCOUNTER14H_LSB _u(0) -#define RVCSR_MHPMCOUNTER14H_ACCESS "RO" -// ============================================================================= -// Register : RVCSR_MHPMCOUNTER15H -// Description : Extended performance counter, hardwired to 0. -#define RVCSR_MHPMCOUNTER15H_OFFSET _u(0x00000b8f) -#define RVCSR_MHPMCOUNTER15H_BITS _u(0xffffffff) -#define RVCSR_MHPMCOUNTER15H_RESET _u(0x00000000) -#define RVCSR_MHPMCOUNTER15H_MSB _u(31) -#define RVCSR_MHPMCOUNTER15H_LSB _u(0) -#define RVCSR_MHPMCOUNTER15H_ACCESS "RO" -// ============================================================================= -// Register : RVCSR_MHPMCOUNTER16H -// Description : Extended performance counter, hardwired to 0. -#define RVCSR_MHPMCOUNTER16H_OFFSET _u(0x00000b90) -#define RVCSR_MHPMCOUNTER16H_BITS _u(0xffffffff) -#define RVCSR_MHPMCOUNTER16H_RESET _u(0x00000000) -#define RVCSR_MHPMCOUNTER16H_MSB _u(31) -#define RVCSR_MHPMCOUNTER16H_LSB _u(0) -#define RVCSR_MHPMCOUNTER16H_ACCESS "RO" -// ============================================================================= -// Register : RVCSR_MHPMCOUNTER17H -// Description : Extended performance counter, hardwired to 0. -#define RVCSR_MHPMCOUNTER17H_OFFSET _u(0x00000b91) -#define RVCSR_MHPMCOUNTER17H_BITS _u(0xffffffff) -#define RVCSR_MHPMCOUNTER17H_RESET _u(0x00000000) -#define RVCSR_MHPMCOUNTER17H_MSB _u(31) -#define RVCSR_MHPMCOUNTER17H_LSB _u(0) -#define RVCSR_MHPMCOUNTER17H_ACCESS "RO" -// ============================================================================= -// Register : RVCSR_MHPMCOUNTER18H -// Description : Extended performance counter, hardwired to 0. -#define RVCSR_MHPMCOUNTER18H_OFFSET _u(0x00000b92) -#define RVCSR_MHPMCOUNTER18H_BITS _u(0xffffffff) -#define RVCSR_MHPMCOUNTER18H_RESET _u(0x00000000) -#define RVCSR_MHPMCOUNTER18H_MSB _u(31) -#define RVCSR_MHPMCOUNTER18H_LSB _u(0) -#define RVCSR_MHPMCOUNTER18H_ACCESS "RO" -// ============================================================================= -// Register : RVCSR_MHPMCOUNTER19H -// Description : Extended performance counter, hardwired to 0. -#define RVCSR_MHPMCOUNTER19H_OFFSET _u(0x00000b93) -#define RVCSR_MHPMCOUNTER19H_BITS _u(0xffffffff) -#define RVCSR_MHPMCOUNTER19H_RESET _u(0x00000000) -#define RVCSR_MHPMCOUNTER19H_MSB _u(31) -#define RVCSR_MHPMCOUNTER19H_LSB _u(0) -#define RVCSR_MHPMCOUNTER19H_ACCESS "RO" -// ============================================================================= -// Register : RVCSR_MHPMCOUNTER20H -// Description : Extended performance counter, hardwired to 0. -#define RVCSR_MHPMCOUNTER20H_OFFSET _u(0x00000b94) -#define RVCSR_MHPMCOUNTER20H_BITS _u(0xffffffff) -#define RVCSR_MHPMCOUNTER20H_RESET _u(0x00000000) -#define RVCSR_MHPMCOUNTER20H_MSB _u(31) -#define RVCSR_MHPMCOUNTER20H_LSB _u(0) -#define RVCSR_MHPMCOUNTER20H_ACCESS "RO" -// ============================================================================= -// Register : RVCSR_MHPMCOUNTER21H -// Description : Extended performance counter, hardwired to 0. -#define RVCSR_MHPMCOUNTER21H_OFFSET _u(0x00000b95) -#define RVCSR_MHPMCOUNTER21H_BITS _u(0xffffffff) -#define RVCSR_MHPMCOUNTER21H_RESET _u(0x00000000) -#define RVCSR_MHPMCOUNTER21H_MSB _u(31) -#define RVCSR_MHPMCOUNTER21H_LSB _u(0) -#define RVCSR_MHPMCOUNTER21H_ACCESS "RO" -// ============================================================================= -// Register : RVCSR_MHPMCOUNTER22H -// Description : Extended performance counter, hardwired to 0. -#define RVCSR_MHPMCOUNTER22H_OFFSET _u(0x00000b96) -#define RVCSR_MHPMCOUNTER22H_BITS _u(0xffffffff) -#define RVCSR_MHPMCOUNTER22H_RESET _u(0x00000000) -#define RVCSR_MHPMCOUNTER22H_MSB _u(31) -#define RVCSR_MHPMCOUNTER22H_LSB _u(0) -#define RVCSR_MHPMCOUNTER22H_ACCESS "RO" -// ============================================================================= -// Register : RVCSR_MHPMCOUNTER23H -// Description : Extended performance counter, hardwired to 0. -#define RVCSR_MHPMCOUNTER23H_OFFSET _u(0x00000b97) -#define RVCSR_MHPMCOUNTER23H_BITS _u(0xffffffff) -#define RVCSR_MHPMCOUNTER23H_RESET _u(0x00000000) -#define RVCSR_MHPMCOUNTER23H_MSB _u(31) -#define RVCSR_MHPMCOUNTER23H_LSB _u(0) -#define RVCSR_MHPMCOUNTER23H_ACCESS "RO" -// ============================================================================= -// Register : RVCSR_MHPMCOUNTER24H -// Description : Extended performance counter, hardwired to 0. -#define RVCSR_MHPMCOUNTER24H_OFFSET _u(0x00000b98) -#define RVCSR_MHPMCOUNTER24H_BITS _u(0xffffffff) -#define RVCSR_MHPMCOUNTER24H_RESET _u(0x00000000) -#define RVCSR_MHPMCOUNTER24H_MSB _u(31) -#define RVCSR_MHPMCOUNTER24H_LSB _u(0) -#define RVCSR_MHPMCOUNTER24H_ACCESS "RO" -// ============================================================================= -// Register : RVCSR_MHPMCOUNTER25H -// Description : Extended performance counter, hardwired to 0. -#define RVCSR_MHPMCOUNTER25H_OFFSET _u(0x00000b99) -#define RVCSR_MHPMCOUNTER25H_BITS _u(0xffffffff) -#define RVCSR_MHPMCOUNTER25H_RESET _u(0x00000000) -#define RVCSR_MHPMCOUNTER25H_MSB _u(31) -#define RVCSR_MHPMCOUNTER25H_LSB _u(0) -#define RVCSR_MHPMCOUNTER25H_ACCESS "RO" -// ============================================================================= -// Register : RVCSR_MHPMCOUNTER26H -// Description : Extended performance counter, hardwired to 0. -#define RVCSR_MHPMCOUNTER26H_OFFSET _u(0x00000b9a) -#define RVCSR_MHPMCOUNTER26H_BITS _u(0xffffffff) -#define RVCSR_MHPMCOUNTER26H_RESET _u(0x00000000) -#define RVCSR_MHPMCOUNTER26H_MSB _u(31) -#define RVCSR_MHPMCOUNTER26H_LSB _u(0) -#define RVCSR_MHPMCOUNTER26H_ACCESS "RO" -// ============================================================================= -// Register : RVCSR_MHPMCOUNTER27H -// Description : Extended performance counter, hardwired to 0. -#define RVCSR_MHPMCOUNTER27H_OFFSET _u(0x00000b9b) -#define RVCSR_MHPMCOUNTER27H_BITS _u(0xffffffff) -#define RVCSR_MHPMCOUNTER27H_RESET _u(0x00000000) -#define RVCSR_MHPMCOUNTER27H_MSB _u(31) -#define RVCSR_MHPMCOUNTER27H_LSB _u(0) -#define RVCSR_MHPMCOUNTER27H_ACCESS "RO" -// ============================================================================= -// Register : RVCSR_MHPMCOUNTER28H -// Description : Extended performance counter, hardwired to 0. -#define RVCSR_MHPMCOUNTER28H_OFFSET _u(0x00000b9c) -#define RVCSR_MHPMCOUNTER28H_BITS _u(0xffffffff) -#define RVCSR_MHPMCOUNTER28H_RESET _u(0x00000000) -#define RVCSR_MHPMCOUNTER28H_MSB _u(31) -#define RVCSR_MHPMCOUNTER28H_LSB _u(0) -#define RVCSR_MHPMCOUNTER28H_ACCESS "RO" -// ============================================================================= -// Register : RVCSR_MHPMCOUNTER29H -// Description : Extended performance counter, hardwired to 0. -#define RVCSR_MHPMCOUNTER29H_OFFSET _u(0x00000b9d) -#define RVCSR_MHPMCOUNTER29H_BITS _u(0xffffffff) -#define RVCSR_MHPMCOUNTER29H_RESET _u(0x00000000) -#define RVCSR_MHPMCOUNTER29H_MSB _u(31) -#define RVCSR_MHPMCOUNTER29H_LSB _u(0) -#define RVCSR_MHPMCOUNTER29H_ACCESS "RO" -// ============================================================================= -// Register : RVCSR_MHPMCOUNTER30H -// Description : Extended performance counter, hardwired to 0. -#define RVCSR_MHPMCOUNTER30H_OFFSET _u(0x00000b9e) -#define RVCSR_MHPMCOUNTER30H_BITS _u(0xffffffff) -#define RVCSR_MHPMCOUNTER30H_RESET _u(0x00000000) -#define RVCSR_MHPMCOUNTER30H_MSB _u(31) -#define RVCSR_MHPMCOUNTER30H_LSB _u(0) -#define RVCSR_MHPMCOUNTER30H_ACCESS "RO" -// ============================================================================= -// Register : RVCSR_MHPMCOUNTER31H -// Description : Extended performance counter, hardwired to 0. -#define RVCSR_MHPMCOUNTER31H_OFFSET _u(0x00000b9f) -#define RVCSR_MHPMCOUNTER31H_BITS _u(0xffffffff) -#define RVCSR_MHPMCOUNTER31H_RESET _u(0x00000000) -#define RVCSR_MHPMCOUNTER31H_MSB _u(31) -#define RVCSR_MHPMCOUNTER31H_LSB _u(0) -#define RVCSR_MHPMCOUNTER31H_ACCESS "RO" -// ============================================================================= -// Register : RVCSR_PMPCFGM0 -// Description : PMP M-mode configuration. One bit per PMP region. Setting a bit -// makes the corresponding region apply to M-mode (like the -// `pmpcfg.L` bit) but does not lock the region. -// -// PMP is useful for non-security-related purposes, such as stack -// guarding and peripheral emulation. This extension allows M-mode -// to freely use any currently unlocked regions for its own -// purposes, without the inconvenience of having to lock them. -// -// Note that this does not grant any new capabilities to M-mode, -// since in the base standard it is already possible to apply -// unlocked regions to M-mode by locking them. In general, PMP -// regions should be locked in ascending region number order so -// they can't be subsequently overridden by currently unlocked -// regions. -// -// Note also that this is not the same as the rule locking bypass -// bit in the ePMP extension, which does not permit locked and -// unlocked M-mode regions to coexist. -// -// This is a Hazard3 custom CSR. -#define RVCSR_PMPCFGM0_OFFSET _u(0x00000bd0) -#define RVCSR_PMPCFGM0_BITS _u(0x0000ffff) -#define RVCSR_PMPCFGM0_RESET _u(0x00000000) -#define RVCSR_PMPCFGM0_MSB _u(15) -#define RVCSR_PMPCFGM0_LSB _u(0) -#define RVCSR_PMPCFGM0_ACCESS "RW" -// ============================================================================= -// Register : RVCSR_MEIEA -// Description : External interrupt enable array. -// -// The array contains a read-write bit for each external interrupt -// request: a `1` bit indicates that interrupt is currently -// enabled. At reset, all external interrupts are disabled. -// -// If enabled, an external interrupt can cause assertion of the -// standard RISC-V machine external interrupt pending flag -// (`mip.meip`), and therefore cause the processor to enter the -// external interrupt vector. See `meipa`. -// -// There are up to 512 external interrupts. The upper half of this -// register contains a 16-bit window into the full 512-bit vector. -// The window is indexed by the 5 LSBs of the write data. -#define RVCSR_MEIEA_OFFSET _u(0x00000be0) -#define RVCSR_MEIEA_BITS _u(0xffff001f) -#define RVCSR_MEIEA_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : RVCSR_MEIEA_WINDOW -// Description : 16-bit read/write window into the external interrupt enable -// array -#define RVCSR_MEIEA_WINDOW_RESET _u(0x0000) -#define RVCSR_MEIEA_WINDOW_BITS _u(0xffff0000) -#define RVCSR_MEIEA_WINDOW_MSB _u(31) -#define RVCSR_MEIEA_WINDOW_LSB _u(16) -#define RVCSR_MEIEA_WINDOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RVCSR_MEIEA_INDEX -// Description : Write-only self-clearing field (no value is stored) used to -// control which window of the array appears in `window`. -#define RVCSR_MEIEA_INDEX_RESET _u(0x00) -#define RVCSR_MEIEA_INDEX_BITS _u(0x0000001f) -#define RVCSR_MEIEA_INDEX_MSB _u(4) -#define RVCSR_MEIEA_INDEX_LSB _u(0) -#define RVCSR_MEIEA_INDEX_ACCESS "WO" -// ============================================================================= -// Register : RVCSR_MEIPA -// Description : External interrupt pending array -// -// Contains a read-only bit for each external interrupt request. -// Similarly to `meiea`, this register is a window into an array -// of up to 512 external interrupt flags. The status appears in -// the upper 16 bits of the value read from `meipa`, and the lower -// 5 bits of the value _written_ by the same CSR instruction (or 0 -// if no write takes place) select a 16-bit window of the full -// interrupt pending array. -// -// A `1` bit indicates that interrupt is currently asserted. IRQs -// are assumed to be level-sensitive, and the relevant `meipa` bit -// is cleared by servicing the requestor so that it deasserts its -// interrupt request. -// -// When any interrupt of sufficient priority is both set in -// `meipa` and enabled in `meiea`, the standard RISC-V external -// interrupt pending bit `mip.meip` is asserted. In other words, -// `meipa` is filtered by `meiea` to generate the standard -// `mip.meip` flag. -#define RVCSR_MEIPA_OFFSET _u(0x00000be1) -#define RVCSR_MEIPA_BITS _u(0xffff001f) -#define RVCSR_MEIPA_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : RVCSR_MEIPA_WINDOW -// Description : 16-bit read-only window into the external interrupt pending -// array -#define RVCSR_MEIPA_WINDOW_RESET "-" -#define RVCSR_MEIPA_WINDOW_BITS _u(0xffff0000) -#define RVCSR_MEIPA_WINDOW_MSB _u(31) -#define RVCSR_MEIPA_WINDOW_LSB _u(16) -#define RVCSR_MEIPA_WINDOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RVCSR_MEIPA_INDEX -// Description : Write-only, self-clearing field (no value is stored) used to -// control which window of the array appears in `window`. -#define RVCSR_MEIPA_INDEX_RESET _u(0x00) -#define RVCSR_MEIPA_INDEX_BITS _u(0x0000001f) -#define RVCSR_MEIPA_INDEX_MSB _u(4) -#define RVCSR_MEIPA_INDEX_LSB _u(0) -#define RVCSR_MEIPA_INDEX_ACCESS "WO" -// ============================================================================= -// Register : RVCSR_MEIFA -// Description : External interrupt force array -// -// Contains a read-write bit for every interrupt request. Writing -// a 1 to a bit in the interrupt force array causes the -// corresponding bit to become pending in `meipa`. Software can -// use this feature to manually trigger a particular interrupt. -// -// There are no restrictions on using `meifa` inside of an -// interrupt. The more useful case here is to schedule some lower- -// priority handler from within a high-priority interrupt, so that -// it will execute before the core returns to the foreground code. -// Implementers may wish to reserve some external IRQs with their -// external inputs tied to 0 for this purpose. -// -// Bits can be cleared by software, and are cleared automatically -// by hardware upon a read of `meinext` which returns the -// corresponding IRQ number in `meinext.irq` with `mienext.noirq` -// clear (no matter whether `meinext.update` is written). -// -// `meifa` implements the same array window indexing scheme as -// `meiea` and `meipa`. -#define RVCSR_MEIFA_OFFSET _u(0x00000be2) -#define RVCSR_MEIFA_BITS _u(0xffff001f) -#define RVCSR_MEIFA_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : RVCSR_MEIFA_WINDOW -// Description : 16-bit read/write window into the external interrupt force -// array -#define RVCSR_MEIFA_WINDOW_RESET _u(0x0000) -#define RVCSR_MEIFA_WINDOW_BITS _u(0xffff0000) -#define RVCSR_MEIFA_WINDOW_MSB _u(31) -#define RVCSR_MEIFA_WINDOW_LSB _u(16) -#define RVCSR_MEIFA_WINDOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RVCSR_MEIFA_INDEX -// Description : Write-only, self-clearing field (no value is stored) used to -// control which window of the array appears in `window`. -#define RVCSR_MEIFA_INDEX_RESET _u(0x00) -#define RVCSR_MEIFA_INDEX_BITS _u(0x0000001f) -#define RVCSR_MEIFA_INDEX_MSB _u(4) -#define RVCSR_MEIFA_INDEX_LSB _u(0) -#define RVCSR_MEIFA_INDEX_ACCESS "WO" -// ============================================================================= -// Register : RVCSR_MEIPRA -// Description : External interrupt priority array -// -// Each interrupt has an (up to) 4-bit priority value associated -// with it, and each access to this register reads and/or writes a -// 16-bit window containing four such priority values. When less -// than 16 priority levels are available, the LSBs of the priority -// fields are hardwired to 0. -// -// When an interrupt's priority is lower than the current -// preemption priority `meicontext.preempt`, it is treated as not -// being pending for the purposes of `mip.meip`. The pending bit -// in `meipa` will still assert, but the machine external -// interrupt pending bit `mip.meip` will not, so the processor -// will ignore this interrupt. See `meicontext`. -#define RVCSR_MEIPRA_OFFSET _u(0x00000be3) -#define RVCSR_MEIPRA_BITS _u(0xffff001f) -#define RVCSR_MEIPRA_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : RVCSR_MEIPRA_WINDOW -// Description : 16-bit read/write window into the external interrupt priority -// array, containing four 4-bit priority values. -#define RVCSR_MEIPRA_WINDOW_RESET _u(0x0000) -#define RVCSR_MEIPRA_WINDOW_BITS _u(0xffff0000) -#define RVCSR_MEIPRA_WINDOW_MSB _u(31) -#define RVCSR_MEIPRA_WINDOW_LSB _u(16) -#define RVCSR_MEIPRA_WINDOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RVCSR_MEIPRA_INDEX -// Description : Write-only, self-clearing field (no value is stored) used to -// control which window of the array appears in `window`. -#define RVCSR_MEIPRA_INDEX_RESET _u(0x00) -#define RVCSR_MEIPRA_INDEX_BITS _u(0x0000001f) -#define RVCSR_MEIPRA_INDEX_MSB _u(4) -#define RVCSR_MEIPRA_INDEX_LSB _u(0) -#define RVCSR_MEIPRA_INDEX_ACCESS "WO" -// ============================================================================= -// Register : RVCSR_MEINEXT -// Description : Get next external interrupt -// -// Contains the index of the highest-priority external interrupt -// which is both asserted in `meipa` and enabled in `meiea`, left- -// shifted by 2 so that it can be used to index an array of 32-bit -// function pointers. If there is no such interrupt, the MSB is -// set. -// -// When multiple interrupts of the same priority are both pending -// and enabled, the lowest-numbered wins. Interrupts with priority -// less than `meicontext.ppreempt` -- the _previous_ preemption -// priority -- are treated as though they are not pending. This is -// to ensure that a preempting interrupt frame does not service -// interrupts which may be in progress in the frame that was -// preempted. -#define RVCSR_MEINEXT_OFFSET _u(0x00000be4) -#define RVCSR_MEINEXT_BITS _u(0x800007fd) -#define RVCSR_MEINEXT_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : RVCSR_MEINEXT_NOIRQ -// Description : Set when there is no external interrupt which is enabled, -// pending, and has priority greater than or equal to -// `meicontext.ppreempt`. Can be efficiently tested with a `bltz` -// or `bgez` instruction. -#define RVCSR_MEINEXT_NOIRQ_RESET _u(0x0) -#define RVCSR_MEINEXT_NOIRQ_BITS _u(0x80000000) -#define RVCSR_MEINEXT_NOIRQ_MSB _u(31) -#define RVCSR_MEINEXT_NOIRQ_LSB _u(31) -#define RVCSR_MEINEXT_NOIRQ_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RVCSR_MEINEXT_IRQ -// Description : Index of the highest-priority active external interrupt. Zero -// when no external interrupts with sufficient priority are both -// pending and enabled. -#define RVCSR_MEINEXT_IRQ_RESET _u(0x000) -#define RVCSR_MEINEXT_IRQ_BITS _u(0x000007fc) -#define RVCSR_MEINEXT_IRQ_MSB _u(10) -#define RVCSR_MEINEXT_IRQ_LSB _u(2) -#define RVCSR_MEINEXT_IRQ_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RVCSR_MEINEXT_UPDATE -// Description : Writing 1 (self-clearing) causes hardware to update -// `meicontext` according to the IRQ number and preemption -// priority of the interrupt indicated in `noirq`/`irq`. This -// should be done in a single atomic operation, i.e. `csrrsi a0, -// meinext, 0x1`. -#define RVCSR_MEINEXT_UPDATE_RESET _u(0x0) -#define RVCSR_MEINEXT_UPDATE_BITS _u(0x00000001) -#define RVCSR_MEINEXT_UPDATE_MSB _u(0) -#define RVCSR_MEINEXT_UPDATE_LSB _u(0) -#define RVCSR_MEINEXT_UPDATE_ACCESS "SC" -// ============================================================================= -// Register : RVCSR_MEICONTEXT -// Description : External interrupt context register -// -// Configures the priority level for interrupt preemption, and -// helps software track which interrupt it is currently in. The -// latter is useful when a common interrupt service routine -// handles interrupt requests from multiple instances of the same -// peripheral. -// -// A three-level stack of preemption priorities is maintained in -// the `preempt`, `ppreempt` and `pppreempt` fields. The priority -// stack is saved when hardware enters the external interrupt -// vector, and restored by an `mret` instruction if -// `meicontext.mreteirq` is set. -// -// The top entry of the priority stack, `preempt`, is used by -// hardware to ensure that only higher-priority interrupts can -// preempt the current interrupt. The next entry, `ppreempt`, is -// used to avoid servicing interrupts which may already be in -// progress in a frame that was preempted. The third entry, -// `pppreempt`, has no hardware effect, but ensures that `preempt` -// and `ppreempt` can be correctly saved/restored across arbitrary -// levels of preemption. -#define RVCSR_MEICONTEXT_OFFSET _u(0x00000be5) -#define RVCSR_MEICONTEXT_BITS _u(0xff1f9fff) -#define RVCSR_MEICONTEXT_RESET _u(0x00008000) -// ----------------------------------------------------------------------------- -// Field : RVCSR_MEICONTEXT_PPPREEMPT -// Description : Previous `ppreempt`. Set to `ppreempt` on priority save, set to -// zero on priority restore. Has no hardware effect, but ensures -// that when `meicontext` is saved/restored correctly, `preempt` -// and `ppreempt` stack correctly through arbitrarily many -// preemption frames. -#define RVCSR_MEICONTEXT_PPPREEMPT_RESET _u(0x0) -#define RVCSR_MEICONTEXT_PPPREEMPT_BITS _u(0xf0000000) -#define RVCSR_MEICONTEXT_PPPREEMPT_MSB _u(31) -#define RVCSR_MEICONTEXT_PPPREEMPT_LSB _u(28) -#define RVCSR_MEICONTEXT_PPPREEMPT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RVCSR_MEICONTEXT_PPREEMPT -// Description : Previous `preempt`. Set to `preempt` on priority save, restored -// to to `pppreempt` on priority restore. -// -// IRQs of lower priority than `ppreempt` are not visible in -// `meinext`, so that a preemptee is not re-taken in the -// preempting frame. -#define RVCSR_MEICONTEXT_PPREEMPT_RESET _u(0x0) -#define RVCSR_MEICONTEXT_PPREEMPT_BITS _u(0x0f000000) -#define RVCSR_MEICONTEXT_PPREEMPT_MSB _u(27) -#define RVCSR_MEICONTEXT_PPREEMPT_LSB _u(24) -#define RVCSR_MEICONTEXT_PPREEMPT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RVCSR_MEICONTEXT_PREEMPT -// Description : Minimum interrupt priority to preempt the current interrupt. -// Interrupts with lower priority than `preempt` do not cause the -// core to transfer to an interrupt handler. Updated by hardware -// when when `meinext.update` is written, or when hardware enters -// the external interrupt vector. -// -// If an interrupt is present in `meinext` when this field is -// updated, then `preempt` is set to one level greater than that -// interrupt's priority. Otherwise, `ppreempt` is set to one level -// greater than the maximum interrupt priority, disabling -// preemption. -#define RVCSR_MEICONTEXT_PREEMPT_RESET _u(0x00) -#define RVCSR_MEICONTEXT_PREEMPT_BITS _u(0x001f0000) -#define RVCSR_MEICONTEXT_PREEMPT_MSB _u(20) -#define RVCSR_MEICONTEXT_PREEMPT_LSB _u(16) -#define RVCSR_MEICONTEXT_PREEMPT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RVCSR_MEICONTEXT_NOIRQ -// Description : Not in interrupt (read/write). Set to 1 at reset. Set to -// `meinext.noirq` when `meinext.update` is written. No hardware -// effect. -#define RVCSR_MEICONTEXT_NOIRQ_RESET _u(0x1) -#define RVCSR_MEICONTEXT_NOIRQ_BITS _u(0x00008000) -#define RVCSR_MEICONTEXT_NOIRQ_MSB _u(15) -#define RVCSR_MEICONTEXT_NOIRQ_LSB _u(15) -#define RVCSR_MEICONTEXT_NOIRQ_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RVCSR_MEICONTEXT_IRQ -// Description : Current IRQ number (read/write). Set to `meinext.irq` when -// `meinext.update` is written. No hardware effect. -#define RVCSR_MEICONTEXT_IRQ_RESET _u(0x000) -#define RVCSR_MEICONTEXT_IRQ_BITS _u(0x00001ff0) -#define RVCSR_MEICONTEXT_IRQ_MSB _u(12) -#define RVCSR_MEICONTEXT_IRQ_LSB _u(4) -#define RVCSR_MEICONTEXT_IRQ_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RVCSR_MEICONTEXT_MTIESAVE -// Description : Reads as the current value of `mie.mtie`, if `clearts` is set -// by the same CSR access instruction. Otherwise reads as 0. -// Writes are ORed into `mie.mtie`. -#define RVCSR_MEICONTEXT_MTIESAVE_RESET _u(0x0) -#define RVCSR_MEICONTEXT_MTIESAVE_BITS _u(0x00000008) -#define RVCSR_MEICONTEXT_MTIESAVE_MSB _u(3) -#define RVCSR_MEICONTEXT_MTIESAVE_LSB _u(3) -#define RVCSR_MEICONTEXT_MTIESAVE_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RVCSR_MEICONTEXT_MSIESAVE -// Description : Reads as the current value of `mie.msie`, if `clearts` is set -// by the same CSR access instruction. Otherwise reads as 0. -// Writes are ORed into `mie.msie`. -#define RVCSR_MEICONTEXT_MSIESAVE_RESET _u(0x0) -#define RVCSR_MEICONTEXT_MSIESAVE_BITS _u(0x00000004) -#define RVCSR_MEICONTEXT_MSIESAVE_MSB _u(2) -#define RVCSR_MEICONTEXT_MSIESAVE_LSB _u(2) -#define RVCSR_MEICONTEXT_MSIESAVE_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RVCSR_MEICONTEXT_CLEARTS -// Description : Write-1 self-clearing field. Writing 1 will clear `mie.mtie` -// and `mie.msie`, and present their prior values in the -// `mtiesave` and `msiesave` of this register. This makes it safe -// to re-enable IRQs (via `mstatus.mie`) without the possibility -// of being preempted by the standard timer and soft interrupt -// handlers, which may not be aware of Hazard3's interrupt -// hardware. -// -// The clear due to `clearts` takes precedence over the set due to -// `mtiesave`/`msiesave`, although it would be unusual for -// software to write both on the same cycle. -#define RVCSR_MEICONTEXT_CLEARTS_RESET _u(0x0) -#define RVCSR_MEICONTEXT_CLEARTS_BITS _u(0x00000002) -#define RVCSR_MEICONTEXT_CLEARTS_MSB _u(1) -#define RVCSR_MEICONTEXT_CLEARTS_LSB _u(1) -#define RVCSR_MEICONTEXT_CLEARTS_ACCESS "SC" -// ----------------------------------------------------------------------------- -// Field : RVCSR_MEICONTEXT_MRETEIRQ -// Description : If 1, enable restore of the preemption priority stack on -// `mret`. This bit is set on entering the external interrupt -// vector, cleared by `mret`, and cleared upon taking any trap -// other than an external interrupt. -// -// Provided `meicontext` is saved on entry to the external -// interrupt vector (before enabling preemption), is restored -// before exiting, and the standard software/timer IRQs are -// prevented from preempting (e.g. by using `clearts`), this flag -// allows the hardware to safely manage the preemption priority -// stack even when an external interrupt handler may take -// exceptions. -#define RVCSR_MEICONTEXT_MRETEIRQ_RESET _u(0x0) -#define RVCSR_MEICONTEXT_MRETEIRQ_BITS _u(0x00000001) -#define RVCSR_MEICONTEXT_MRETEIRQ_MSB _u(0) -#define RVCSR_MEICONTEXT_MRETEIRQ_LSB _u(0) -#define RVCSR_MEICONTEXT_MRETEIRQ_ACCESS "RW" -// ============================================================================= -// Register : RVCSR_MSLEEP -// Description : M-mode sleep control register -#define RVCSR_MSLEEP_OFFSET _u(0x00000bf0) -#define RVCSR_MSLEEP_BITS _u(0x00000007) -#define RVCSR_MSLEEP_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : RVCSR_MSLEEP_SLEEPONBLOCK -// Description : Enter the deep sleep state configured by -// msleep.deepsleep/msleep.powerdown on a `h3.block` instruction, -// as well as a standard `wfi`. If this bit is clear, a `h3.block` -// is always implemented as a simple pipeline stall. -#define RVCSR_MSLEEP_SLEEPONBLOCK_RESET _u(0x0) -#define RVCSR_MSLEEP_SLEEPONBLOCK_BITS _u(0x00000004) -#define RVCSR_MSLEEP_SLEEPONBLOCK_MSB _u(2) -#define RVCSR_MSLEEP_SLEEPONBLOCK_LSB _u(2) -#define RVCSR_MSLEEP_SLEEPONBLOCK_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RVCSR_MSLEEP_POWERDOWN -// Description : Release the external power request when going to sleep. The -// function of this is platform-defined -- it may do nothing, it -// may do something simple like clock-gating the fabric, or it may -// be tied to some complex system-level power controller. -// -// When waking, the processor reasserts its external power-up -// request, and will not fetch any instructions until the request -// is acknowledged. This may add considerable latency to the -// wakeup. -#define RVCSR_MSLEEP_POWERDOWN_RESET _u(0x0) -#define RVCSR_MSLEEP_POWERDOWN_BITS _u(0x00000002) -#define RVCSR_MSLEEP_POWERDOWN_MSB _u(1) -#define RVCSR_MSLEEP_POWERDOWN_LSB _u(1) -#define RVCSR_MSLEEP_POWERDOWN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : RVCSR_MSLEEP_DEEPSLEEP -// Description : Deassert the processor clock enable when entering the sleep -// state. If a clock gate is instantiated, this allows most of the -// processor (everything except the power state machine and the -// interrupt and halt input registers) to be clock gated whilst -// asleep, which may reduce the sleep current. This adds one cycle -// to the wakeup latency. -#define RVCSR_MSLEEP_DEEPSLEEP_RESET _u(0x0) -#define RVCSR_MSLEEP_DEEPSLEEP_BITS _u(0x00000001) -#define RVCSR_MSLEEP_DEEPSLEEP_MSB _u(0) -#define RVCSR_MSLEEP_DEEPSLEEP_LSB _u(0) -#define RVCSR_MSLEEP_DEEPSLEEP_ACCESS "RW" -// ============================================================================= -// Register : RVCSR_DMDATA0 -// Description : The Debug Module's DATA0 register is mapped into Hazard3's CSR -// space so that the Debug Module can exchange data with the core -// by executing CSR access instructions (this is used to implement -// the Abstract Access Register command). Only accessible in Debug -// Mode. -#define RVCSR_DMDATA0_OFFSET _u(0x00000bff) -#define RVCSR_DMDATA0_BITS _u(0xffffffff) -#define RVCSR_DMDATA0_RESET _u(0x00000000) -#define RVCSR_DMDATA0_MSB _u(31) -#define RVCSR_DMDATA0_LSB _u(0) -#define RVCSR_DMDATA0_ACCESS "RW" -// ============================================================================= -// Register : RVCSR_CYCLE -// Description : Read-only U-mode alias of mcycle, accessible when -// `mcounteren.cy` is set -#define RVCSR_CYCLE_OFFSET _u(0x00000c00) -#define RVCSR_CYCLE_BITS _u(0xffffffff) -#define RVCSR_CYCLE_RESET _u(0x00000000) -#define RVCSR_CYCLE_MSB _u(31) -#define RVCSR_CYCLE_LSB _u(0) -#define RVCSR_CYCLE_ACCESS "RO" -// ============================================================================= -// Register : RVCSR_INSTRET -// Description : Read-only U-mode alias of minstret, accessible when -// `mcounteren.ir` is set -#define RVCSR_INSTRET_OFFSET _u(0x00000c02) -#define RVCSR_INSTRET_BITS _u(0xffffffff) -#define RVCSR_INSTRET_RESET _u(0x00000000) -#define RVCSR_INSTRET_MSB _u(31) -#define RVCSR_INSTRET_LSB _u(0) -#define RVCSR_INSTRET_ACCESS "RO" -// ============================================================================= -// Register : RVCSR_CYCLEH -// Description : Read-only U-mode alias of mcycleh, accessible when -// `mcounteren.cy` is set -#define RVCSR_CYCLEH_OFFSET _u(0x00000c80) -#define RVCSR_CYCLEH_BITS _u(0xffffffff) -#define RVCSR_CYCLEH_RESET _u(0x00000000) -#define RVCSR_CYCLEH_MSB _u(31) -#define RVCSR_CYCLEH_LSB _u(0) -#define RVCSR_CYCLEH_ACCESS "RO" -// ============================================================================= -// Register : RVCSR_INSTRETH -// Description : Read-only U-mode alias of minstreth, accessible when -// `mcounteren.ir` is set -#define RVCSR_INSTRETH_OFFSET _u(0x00000c82) -#define RVCSR_INSTRETH_BITS _u(0xffffffff) -#define RVCSR_INSTRETH_RESET _u(0x00000000) -#define RVCSR_INSTRETH_MSB _u(31) -#define RVCSR_INSTRETH_LSB _u(0) -#define RVCSR_INSTRETH_ACCESS "RO" -// ============================================================================= -// Register : RVCSR_MVENDORID -// Description : Vendor ID -#define RVCSR_MVENDORID_OFFSET _u(0x00000f11) -#define RVCSR_MVENDORID_BITS _u(0xffffffff) -#define RVCSR_MVENDORID_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : RVCSR_MVENDORID_BANK -#define RVCSR_MVENDORID_BANK_RESET "-" -#define RVCSR_MVENDORID_BANK_BITS _u(0xffffff80) -#define RVCSR_MVENDORID_BANK_MSB _u(31) -#define RVCSR_MVENDORID_BANK_LSB _u(7) -#define RVCSR_MVENDORID_BANK_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : RVCSR_MVENDORID_OFFSET -#define RVCSR_MVENDORID_OFFSET_RESET "-" -#define RVCSR_MVENDORID_OFFSET_BITS _u(0x0000007f) -#define RVCSR_MVENDORID_OFFSET_MSB _u(6) -#define RVCSR_MVENDORID_OFFSET_LSB _u(0) -#define RVCSR_MVENDORID_OFFSET_ACCESS "RO" -// ============================================================================= -// Register : RVCSR_MARCHID -// Description : Architecture ID (Hazard3) -#define RVCSR_MARCHID_OFFSET _u(0x00000f12) -#define RVCSR_MARCHID_BITS _u(0xffffffff) -#define RVCSR_MARCHID_RESET _u(0x0000001b) -#define RVCSR_MARCHID_MSB _u(31) -#define RVCSR_MARCHID_LSB _u(0) -#define RVCSR_MARCHID_ACCESS "RO" -// ============================================================================= -// Register : RVCSR_MIMPID -// Description : Implementation ID -#define RVCSR_MIMPID_OFFSET _u(0x00000f13) -#define RVCSR_MIMPID_BITS _u(0xffffffff) -#define RVCSR_MIMPID_RESET "-" -#define RVCSR_MIMPID_MSB _u(31) -#define RVCSR_MIMPID_LSB _u(0) -#define RVCSR_MIMPID_ACCESS "RO" -// ============================================================================= -// Register : RVCSR_MHARTID -// Description : Hardware thread ID -// On RP2350, core 0 has a hart ID of 0, and core 1 has a hart ID -// of 1. -#define RVCSR_MHARTID_OFFSET _u(0x00000f14) -#define RVCSR_MHARTID_BITS _u(0xffffffff) -#define RVCSR_MHARTID_RESET "-" -#define RVCSR_MHARTID_MSB _u(31) -#define RVCSR_MHARTID_LSB _u(0) -#define RVCSR_MHARTID_ACCESS "RO" -// ============================================================================= -// Register : RVCSR_MCONFIGPTR -// Description : Pointer to configuration data structure (hardwired to 0) -#define RVCSR_MCONFIGPTR_OFFSET _u(0x00000f15) -#define RVCSR_MCONFIGPTR_BITS _u(0xffffffff) -#define RVCSR_MCONFIGPTR_RESET _u(0x00000000) -#define RVCSR_MCONFIGPTR_MSB _u(31) -#define RVCSR_MCONFIGPTR_LSB _u(0) -#define RVCSR_MCONFIGPTR_ACCESS "RO" -// ============================================================================= -#endif // _HARDWARE_REGS_RVCSR_H - diff --git a/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/sha256.h b/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/sha256.h deleted file mode 100644 index 112963c08e..0000000000 --- a/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/sha256.h +++ /dev/null @@ -1,228 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -// ============================================================================= -// Register block : SHA256 -// Version : 1 -// Bus type : apb -// Description : SHA-256 hash function implementation -// ============================================================================= -#ifndef _HARDWARE_REGS_SHA256_H -#define _HARDWARE_REGS_SHA256_H -// ============================================================================= -// Register : SHA256_CSR -// Description : Control and status register -#define SHA256_CSR_OFFSET _u(0x00000000) -#define SHA256_CSR_BITS _u(0x00001317) -#define SHA256_CSR_RESET _u(0x00001206) -// ----------------------------------------------------------------------------- -// Field : SHA256_CSR_BSWAP -// Description : Enable byte swapping of 32-bit values at the point they are -// committed to the SHA message scheduler. -// -// This block's bus interface assembles byte/halfword data into -// message words in little-endian order, so that DMAing the same -// buffer with different transfer sizes always gives the same -// result on a little-endian system like RP2350. -// -// However, when marshalling bytes into blocks, SHA expects that -// the first byte is the *most significant* in each message word. -// To resolve this, once the bus interface has accumulated 32 bits -// of data (either a word write, two halfword writes in little- -// endian order, or four byte writes in little-endian order) the -// final value can be byte-swapped before passing to the actual -// SHA core. -// -// This feature is enabled by default because using the SHA core -// to checksum byte buffers is expected to be more common than -// having preformatted SHA message words lying around. -#define SHA256_CSR_BSWAP_RESET _u(0x1) -#define SHA256_CSR_BSWAP_BITS _u(0x00001000) -#define SHA256_CSR_BSWAP_MSB _u(12) -#define SHA256_CSR_BSWAP_LSB _u(12) -#define SHA256_CSR_BSWAP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SHA256_CSR_DMA_SIZE -// Description : Configure DREQ logic for the correct DMA data size. Must be -// configured before the DMA channel is triggered. -// -// The SHA-256 core's DREQ logic requests one entire block of data -// at once, since there is no FIFO, and data goes straight into -// the core's message schedule and digest hardware. Therefore, -// when transferring data with DMA, CSR_DMA_SIZE must be -// configured in advance so that the correct number of transfers -// can be requested per block. -// 0x0 -> 8bit -// 0x1 -> 16bit -// 0x2 -> 32bit -#define SHA256_CSR_DMA_SIZE_RESET _u(0x2) -#define SHA256_CSR_DMA_SIZE_BITS _u(0x00000300) -#define SHA256_CSR_DMA_SIZE_MSB _u(9) -#define SHA256_CSR_DMA_SIZE_LSB _u(8) -#define SHA256_CSR_DMA_SIZE_ACCESS "RW" -#define SHA256_CSR_DMA_SIZE_VALUE_8BIT _u(0x0) -#define SHA256_CSR_DMA_SIZE_VALUE_16BIT _u(0x1) -#define SHA256_CSR_DMA_SIZE_VALUE_32BIT _u(0x2) -// ----------------------------------------------------------------------------- -// Field : SHA256_CSR_ERR_WDATA_NOT_RDY -// Description : Set when a write occurs whilst the SHA-256 core is not ready -// for data (WDATA_RDY is low). Write one to clear. -#define SHA256_CSR_ERR_WDATA_NOT_RDY_RESET _u(0x0) -#define SHA256_CSR_ERR_WDATA_NOT_RDY_BITS _u(0x00000010) -#define SHA256_CSR_ERR_WDATA_NOT_RDY_MSB _u(4) -#define SHA256_CSR_ERR_WDATA_NOT_RDY_LSB _u(4) -#define SHA256_CSR_ERR_WDATA_NOT_RDY_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : SHA256_CSR_SUM_VLD -// Description : If 1, the SHA-256 checksum presented in registers SUM0 through -// SUM7 is currently valid. -// -// Goes low when WDATA is first written, then returns high once 16 -// words have been written and the digest of the current 512-bit -// block has subsequently completed. -#define SHA256_CSR_SUM_VLD_RESET _u(0x1) -#define SHA256_CSR_SUM_VLD_BITS _u(0x00000004) -#define SHA256_CSR_SUM_VLD_MSB _u(2) -#define SHA256_CSR_SUM_VLD_LSB _u(2) -#define SHA256_CSR_SUM_VLD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : SHA256_CSR_WDATA_RDY -// Description : If 1, the SHA-256 core is ready to accept more data through the -// WDATA register. -// -// After writing 16 words, this flag will go low for 57 cycles -// whilst the core completes its digest. -#define SHA256_CSR_WDATA_RDY_RESET _u(0x1) -#define SHA256_CSR_WDATA_RDY_BITS _u(0x00000002) -#define SHA256_CSR_WDATA_RDY_MSB _u(1) -#define SHA256_CSR_WDATA_RDY_LSB _u(1) -#define SHA256_CSR_WDATA_RDY_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : SHA256_CSR_START -// Description : Write 1 to prepare the SHA-256 core for a new checksum. -// -// The SUMx registers are initialised to the proper values -// (fractional bits of square roots of first 8 primes) and -// internal counters are cleared. This immediately forces -// WDATA_RDY and SUM_VLD high. -// -// START must be written before initiating a DMA transfer to the -// SHA-256 core, because the core will always request 16 transfers -// at a time (1 512-bit block). Additionally, the DMA channel -// should be configured for a multiple of 16 32-bit transfers. -#define SHA256_CSR_START_RESET _u(0x0) -#define SHA256_CSR_START_BITS _u(0x00000001) -#define SHA256_CSR_START_MSB _u(0) -#define SHA256_CSR_START_LSB _u(0) -#define SHA256_CSR_START_ACCESS "SC" -// ============================================================================= -// Register : SHA256_WDATA -// Description : Write data register -// After pulsing START and writing 16 words of data to this -// register, WDATA_RDY will go low and the SHA-256 core will -// complete the digest of the current 512-bit block. -// -// Software is responsible for ensuring the data is correctly -// padded and terminated to a whole number of 512-bit blocks. -// -// After this, WDATA_RDY will return high, and more data can be -// written (if any). -// -// This register supports word, halfword and byte writes, so that -// DMA from non-word-aligned buffers can be supported. The total -// amount of data per block remains the same (16 words, 32 -// halfwords or 64 bytes) and byte/halfword transfers must not be -// mixed within a block. -#define SHA256_WDATA_OFFSET _u(0x00000004) -#define SHA256_WDATA_BITS _u(0xffffffff) -#define SHA256_WDATA_RESET _u(0x00000000) -#define SHA256_WDATA_MSB _u(31) -#define SHA256_WDATA_LSB _u(0) -#define SHA256_WDATA_ACCESS "WF" -// ============================================================================= -// Register : SHA256_SUM0 -// Description : 256-bit checksum result. Contents are undefined when -// CSR_SUM_VLD is 0. -#define SHA256_SUM0_OFFSET _u(0x00000008) -#define SHA256_SUM0_BITS _u(0xffffffff) -#define SHA256_SUM0_RESET _u(0x00000000) -#define SHA256_SUM0_MSB _u(31) -#define SHA256_SUM0_LSB _u(0) -#define SHA256_SUM0_ACCESS "RO" -// ============================================================================= -// Register : SHA256_SUM1 -// Description : 256-bit checksum result. Contents are undefined when -// CSR_SUM_VLD is 0. -#define SHA256_SUM1_OFFSET _u(0x0000000c) -#define SHA256_SUM1_BITS _u(0xffffffff) -#define SHA256_SUM1_RESET _u(0x00000000) -#define SHA256_SUM1_MSB _u(31) -#define SHA256_SUM1_LSB _u(0) -#define SHA256_SUM1_ACCESS "RO" -// ============================================================================= -// Register : SHA256_SUM2 -// Description : 256-bit checksum result. Contents are undefined when -// CSR_SUM_VLD is 0. -#define SHA256_SUM2_OFFSET _u(0x00000010) -#define SHA256_SUM2_BITS _u(0xffffffff) -#define SHA256_SUM2_RESET _u(0x00000000) -#define SHA256_SUM2_MSB _u(31) -#define SHA256_SUM2_LSB _u(0) -#define SHA256_SUM2_ACCESS "RO" -// ============================================================================= -// Register : SHA256_SUM3 -// Description : 256-bit checksum result. Contents are undefined when -// CSR_SUM_VLD is 0. -#define SHA256_SUM3_OFFSET _u(0x00000014) -#define SHA256_SUM3_BITS _u(0xffffffff) -#define SHA256_SUM3_RESET _u(0x00000000) -#define SHA256_SUM3_MSB _u(31) -#define SHA256_SUM3_LSB _u(0) -#define SHA256_SUM3_ACCESS "RO" -// ============================================================================= -// Register : SHA256_SUM4 -// Description : 256-bit checksum result. Contents are undefined when -// CSR_SUM_VLD is 0. -#define SHA256_SUM4_OFFSET _u(0x00000018) -#define SHA256_SUM4_BITS _u(0xffffffff) -#define SHA256_SUM4_RESET _u(0x00000000) -#define SHA256_SUM4_MSB _u(31) -#define SHA256_SUM4_LSB _u(0) -#define SHA256_SUM4_ACCESS "RO" -// ============================================================================= -// Register : SHA256_SUM5 -// Description : 256-bit checksum result. Contents are undefined when -// CSR_SUM_VLD is 0. -#define SHA256_SUM5_OFFSET _u(0x0000001c) -#define SHA256_SUM5_BITS _u(0xffffffff) -#define SHA256_SUM5_RESET _u(0x00000000) -#define SHA256_SUM5_MSB _u(31) -#define SHA256_SUM5_LSB _u(0) -#define SHA256_SUM5_ACCESS "RO" -// ============================================================================= -// Register : SHA256_SUM6 -// Description : 256-bit checksum result. Contents are undefined when -// CSR_SUM_VLD is 0. -#define SHA256_SUM6_OFFSET _u(0x00000020) -#define SHA256_SUM6_BITS _u(0xffffffff) -#define SHA256_SUM6_RESET _u(0x00000000) -#define SHA256_SUM6_MSB _u(31) -#define SHA256_SUM6_LSB _u(0) -#define SHA256_SUM6_ACCESS "RO" -// ============================================================================= -// Register : SHA256_SUM7 -// Description : 256-bit checksum result. Contents are undefined when -// CSR_SUM_VLD is 0. -#define SHA256_SUM7_OFFSET _u(0x00000024) -#define SHA256_SUM7_BITS _u(0xffffffff) -#define SHA256_SUM7_RESET _u(0x00000000) -#define SHA256_SUM7_MSB _u(31) -#define SHA256_SUM7_LSB _u(0) -#define SHA256_SUM7_ACCESS "RO" -// ============================================================================= -#endif // _HARDWARE_REGS_SHA256_H - diff --git a/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/sio.h b/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/sio.h deleted file mode 100644 index c4cb29042c..0000000000 --- a/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/sio.h +++ /dev/null @@ -1,2461 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -// ============================================================================= -// Register block : SIO -// Version : 1 -// Bus type : apb -// Description : Single-cycle IO block -// Provides core-local and inter-core hardware for the two -// processors, with single-cycle access. -// ============================================================================= -#ifndef _HARDWARE_REGS_SIO_H -#define _HARDWARE_REGS_SIO_H -// ============================================================================= -// Register : SIO_CPUID -// Description : Processor core identifier -// Value is 0 when read from processor core 0, and 1 when read -// from processor core 1. -#define SIO_CPUID_OFFSET _u(0x00000000) -#define SIO_CPUID_BITS _u(0xffffffff) -#define SIO_CPUID_RESET "-" -#define SIO_CPUID_MSB _u(31) -#define SIO_CPUID_LSB _u(0) -#define SIO_CPUID_ACCESS "RO" -// ============================================================================= -// Register : SIO_GPIO_IN -// Description : Input value for GPIO0...31. -// -// In the Non-secure SIO, Secure-only GPIOs (as per ACCESSCTRL) -// appear as zero. -#define SIO_GPIO_IN_OFFSET _u(0x00000004) -#define SIO_GPIO_IN_BITS _u(0xffffffff) -#define SIO_GPIO_IN_RESET _u(0x00000000) -#define SIO_GPIO_IN_MSB _u(31) -#define SIO_GPIO_IN_LSB _u(0) -#define SIO_GPIO_IN_ACCESS "RO" -// ============================================================================= -// Register : SIO_GPIO_HI_IN -// Description : Input value on GPIO32...47, QSPI IOs and USB pins -// -// In the Non-secure SIO, Secure-only GPIOs (as per ACCESSCTRL) -// appear as zero. -#define SIO_GPIO_HI_IN_OFFSET _u(0x00000008) -#define SIO_GPIO_HI_IN_BITS _u(0xff00ffff) -#define SIO_GPIO_HI_IN_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : SIO_GPIO_HI_IN_QSPI_SD -// Description : Input value on QSPI SD0 (MOSI), SD1 (MISO), SD2 and SD3 pins -#define SIO_GPIO_HI_IN_QSPI_SD_RESET _u(0x0) -#define SIO_GPIO_HI_IN_QSPI_SD_BITS _u(0xf0000000) -#define SIO_GPIO_HI_IN_QSPI_SD_MSB _u(31) -#define SIO_GPIO_HI_IN_QSPI_SD_LSB _u(28) -#define SIO_GPIO_HI_IN_QSPI_SD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : SIO_GPIO_HI_IN_QSPI_CSN -// Description : Input value on QSPI CSn pin -#define SIO_GPIO_HI_IN_QSPI_CSN_RESET _u(0x0) -#define SIO_GPIO_HI_IN_QSPI_CSN_BITS _u(0x08000000) -#define SIO_GPIO_HI_IN_QSPI_CSN_MSB _u(27) -#define SIO_GPIO_HI_IN_QSPI_CSN_LSB _u(27) -#define SIO_GPIO_HI_IN_QSPI_CSN_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : SIO_GPIO_HI_IN_QSPI_SCK -// Description : Input value on QSPI SCK pin -#define SIO_GPIO_HI_IN_QSPI_SCK_RESET _u(0x0) -#define SIO_GPIO_HI_IN_QSPI_SCK_BITS _u(0x04000000) -#define SIO_GPIO_HI_IN_QSPI_SCK_MSB _u(26) -#define SIO_GPIO_HI_IN_QSPI_SCK_LSB _u(26) -#define SIO_GPIO_HI_IN_QSPI_SCK_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : SIO_GPIO_HI_IN_USB_DM -// Description : Input value on USB D- pin -#define SIO_GPIO_HI_IN_USB_DM_RESET _u(0x0) -#define SIO_GPIO_HI_IN_USB_DM_BITS _u(0x02000000) -#define SIO_GPIO_HI_IN_USB_DM_MSB _u(25) -#define SIO_GPIO_HI_IN_USB_DM_LSB _u(25) -#define SIO_GPIO_HI_IN_USB_DM_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : SIO_GPIO_HI_IN_USB_DP -// Description : Input value on USB D+ pin -#define SIO_GPIO_HI_IN_USB_DP_RESET _u(0x0) -#define SIO_GPIO_HI_IN_USB_DP_BITS _u(0x01000000) -#define SIO_GPIO_HI_IN_USB_DP_MSB _u(24) -#define SIO_GPIO_HI_IN_USB_DP_LSB _u(24) -#define SIO_GPIO_HI_IN_USB_DP_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : SIO_GPIO_HI_IN_GPIO -// Description : Input value on GPIO32...47 -#define SIO_GPIO_HI_IN_GPIO_RESET _u(0x0000) -#define SIO_GPIO_HI_IN_GPIO_BITS _u(0x0000ffff) -#define SIO_GPIO_HI_IN_GPIO_MSB _u(15) -#define SIO_GPIO_HI_IN_GPIO_LSB _u(0) -#define SIO_GPIO_HI_IN_GPIO_ACCESS "RO" -// ============================================================================= -// Register : SIO_GPIO_OUT -// Description : GPIO0...31 output value -// Set output level (1/0 -> high/low) for GPIO0...31. Reading back -// gives the last value written, NOT the input value from the -// pins. -// -// If core 0 and core 1 both write to GPIO_OUT simultaneously (or -// to a SET/CLR/XOR alias), the result is as though the write from -// core 0 took place first, and the write from core 1 was then -// applied to that intermediate result. -// -// In the Non-secure SIO, Secure-only GPIOs (as per ACCESSCTRL) -// ignore writes, and their output status reads back as zero. This -// is also true for SET/CLR/XOR aliases of this register. -#define SIO_GPIO_OUT_OFFSET _u(0x00000010) -#define SIO_GPIO_OUT_BITS _u(0xffffffff) -#define SIO_GPIO_OUT_RESET _u(0x00000000) -#define SIO_GPIO_OUT_MSB _u(31) -#define SIO_GPIO_OUT_LSB _u(0) -#define SIO_GPIO_OUT_ACCESS "RW" -// ============================================================================= -// Register : SIO_GPIO_HI_OUT -// Description : Output value for GPIO32...47, QSPI IOs and USB pins. -// -// Write to set output level (1/0 -> high/low). Reading back gives -// the last value written, NOT the input value from the pins. If -// core 0 and core 1 both write to GPIO_HI_OUT simultaneously (or -// to a SET/CLR/XOR alias), the result is as though the write from -// core 0 took place first, and the write from core 1 was then -// applied to that intermediate result. -// -// In the Non-secure SIO, Secure-only GPIOs (as per ACCESSCTRL) -// ignore writes, and their output status reads back as zero. This -// is also true for SET/CLR/XOR aliases of this register. -#define SIO_GPIO_HI_OUT_OFFSET _u(0x00000014) -#define SIO_GPIO_HI_OUT_BITS _u(0xff00ffff) -#define SIO_GPIO_HI_OUT_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : SIO_GPIO_HI_OUT_QSPI_SD -// Description : Output value for QSPI SD0 (MOSI), SD1 (MISO), SD2 and SD3 pins -#define SIO_GPIO_HI_OUT_QSPI_SD_RESET _u(0x0) -#define SIO_GPIO_HI_OUT_QSPI_SD_BITS _u(0xf0000000) -#define SIO_GPIO_HI_OUT_QSPI_SD_MSB _u(31) -#define SIO_GPIO_HI_OUT_QSPI_SD_LSB _u(28) -#define SIO_GPIO_HI_OUT_QSPI_SD_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SIO_GPIO_HI_OUT_QSPI_CSN -// Description : Output value for QSPI CSn pin -#define SIO_GPIO_HI_OUT_QSPI_CSN_RESET _u(0x0) -#define SIO_GPIO_HI_OUT_QSPI_CSN_BITS _u(0x08000000) -#define SIO_GPIO_HI_OUT_QSPI_CSN_MSB _u(27) -#define SIO_GPIO_HI_OUT_QSPI_CSN_LSB _u(27) -#define SIO_GPIO_HI_OUT_QSPI_CSN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SIO_GPIO_HI_OUT_QSPI_SCK -// Description : Output value for QSPI SCK pin -#define SIO_GPIO_HI_OUT_QSPI_SCK_RESET _u(0x0) -#define SIO_GPIO_HI_OUT_QSPI_SCK_BITS _u(0x04000000) -#define SIO_GPIO_HI_OUT_QSPI_SCK_MSB _u(26) -#define SIO_GPIO_HI_OUT_QSPI_SCK_LSB _u(26) -#define SIO_GPIO_HI_OUT_QSPI_SCK_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SIO_GPIO_HI_OUT_USB_DM -// Description : Output value for USB D- pin -#define SIO_GPIO_HI_OUT_USB_DM_RESET _u(0x0) -#define SIO_GPIO_HI_OUT_USB_DM_BITS _u(0x02000000) -#define SIO_GPIO_HI_OUT_USB_DM_MSB _u(25) -#define SIO_GPIO_HI_OUT_USB_DM_LSB _u(25) -#define SIO_GPIO_HI_OUT_USB_DM_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SIO_GPIO_HI_OUT_USB_DP -// Description : Output value for USB D+ pin -#define SIO_GPIO_HI_OUT_USB_DP_RESET _u(0x0) -#define SIO_GPIO_HI_OUT_USB_DP_BITS _u(0x01000000) -#define SIO_GPIO_HI_OUT_USB_DP_MSB _u(24) -#define SIO_GPIO_HI_OUT_USB_DP_LSB _u(24) -#define SIO_GPIO_HI_OUT_USB_DP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SIO_GPIO_HI_OUT_GPIO -// Description : Output value for GPIO32...47 -#define SIO_GPIO_HI_OUT_GPIO_RESET _u(0x0000) -#define SIO_GPIO_HI_OUT_GPIO_BITS _u(0x0000ffff) -#define SIO_GPIO_HI_OUT_GPIO_MSB _u(15) -#define SIO_GPIO_HI_OUT_GPIO_LSB _u(0) -#define SIO_GPIO_HI_OUT_GPIO_ACCESS "RW" -// ============================================================================= -// Register : SIO_GPIO_OUT_SET -// Description : GPIO0...31 output value set -// Perform an atomic bit-set on GPIO_OUT, i.e. `GPIO_OUT |= wdata` -#define SIO_GPIO_OUT_SET_OFFSET _u(0x00000018) -#define SIO_GPIO_OUT_SET_BITS _u(0xffffffff) -#define SIO_GPIO_OUT_SET_RESET _u(0x00000000) -#define SIO_GPIO_OUT_SET_MSB _u(31) -#define SIO_GPIO_OUT_SET_LSB _u(0) -#define SIO_GPIO_OUT_SET_ACCESS "WO" -// ============================================================================= -// Register : SIO_GPIO_HI_OUT_SET -// Description : Output value set for GPIO32..47, QSPI IOs and USB pins. -// Perform an atomic bit-set on GPIO_HI_OUT, i.e. `GPIO_HI_OUT |= -// wdata` -#define SIO_GPIO_HI_OUT_SET_OFFSET _u(0x0000001c) -#define SIO_GPIO_HI_OUT_SET_BITS _u(0xff00ffff) -#define SIO_GPIO_HI_OUT_SET_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : SIO_GPIO_HI_OUT_SET_QSPI_SD -#define SIO_GPIO_HI_OUT_SET_QSPI_SD_RESET _u(0x0) -#define SIO_GPIO_HI_OUT_SET_QSPI_SD_BITS _u(0xf0000000) -#define SIO_GPIO_HI_OUT_SET_QSPI_SD_MSB _u(31) -#define SIO_GPIO_HI_OUT_SET_QSPI_SD_LSB _u(28) -#define SIO_GPIO_HI_OUT_SET_QSPI_SD_ACCESS "WO" -// ----------------------------------------------------------------------------- -// Field : SIO_GPIO_HI_OUT_SET_QSPI_CSN -#define SIO_GPIO_HI_OUT_SET_QSPI_CSN_RESET _u(0x0) -#define SIO_GPIO_HI_OUT_SET_QSPI_CSN_BITS _u(0x08000000) -#define SIO_GPIO_HI_OUT_SET_QSPI_CSN_MSB _u(27) -#define SIO_GPIO_HI_OUT_SET_QSPI_CSN_LSB _u(27) -#define SIO_GPIO_HI_OUT_SET_QSPI_CSN_ACCESS "WO" -// ----------------------------------------------------------------------------- -// Field : SIO_GPIO_HI_OUT_SET_QSPI_SCK -#define SIO_GPIO_HI_OUT_SET_QSPI_SCK_RESET _u(0x0) -#define SIO_GPIO_HI_OUT_SET_QSPI_SCK_BITS _u(0x04000000) -#define SIO_GPIO_HI_OUT_SET_QSPI_SCK_MSB _u(26) -#define SIO_GPIO_HI_OUT_SET_QSPI_SCK_LSB _u(26) -#define SIO_GPIO_HI_OUT_SET_QSPI_SCK_ACCESS "WO" -// ----------------------------------------------------------------------------- -// Field : SIO_GPIO_HI_OUT_SET_USB_DM -#define SIO_GPIO_HI_OUT_SET_USB_DM_RESET _u(0x0) -#define SIO_GPIO_HI_OUT_SET_USB_DM_BITS _u(0x02000000) -#define SIO_GPIO_HI_OUT_SET_USB_DM_MSB _u(25) -#define SIO_GPIO_HI_OUT_SET_USB_DM_LSB _u(25) -#define SIO_GPIO_HI_OUT_SET_USB_DM_ACCESS "WO" -// ----------------------------------------------------------------------------- -// Field : SIO_GPIO_HI_OUT_SET_USB_DP -#define SIO_GPIO_HI_OUT_SET_USB_DP_RESET _u(0x0) -#define SIO_GPIO_HI_OUT_SET_USB_DP_BITS _u(0x01000000) -#define SIO_GPIO_HI_OUT_SET_USB_DP_MSB _u(24) -#define SIO_GPIO_HI_OUT_SET_USB_DP_LSB _u(24) -#define SIO_GPIO_HI_OUT_SET_USB_DP_ACCESS "WO" -// ----------------------------------------------------------------------------- -// Field : SIO_GPIO_HI_OUT_SET_GPIO -#define SIO_GPIO_HI_OUT_SET_GPIO_RESET _u(0x0000) -#define SIO_GPIO_HI_OUT_SET_GPIO_BITS _u(0x0000ffff) -#define SIO_GPIO_HI_OUT_SET_GPIO_MSB _u(15) -#define SIO_GPIO_HI_OUT_SET_GPIO_LSB _u(0) -#define SIO_GPIO_HI_OUT_SET_GPIO_ACCESS "WO" -// ============================================================================= -// Register : SIO_GPIO_OUT_CLR -// Description : GPIO0...31 output value clear -// Perform an atomic bit-clear on GPIO_OUT, i.e. `GPIO_OUT &= -// ~wdata` -#define SIO_GPIO_OUT_CLR_OFFSET _u(0x00000020) -#define SIO_GPIO_OUT_CLR_BITS _u(0xffffffff) -#define SIO_GPIO_OUT_CLR_RESET _u(0x00000000) -#define SIO_GPIO_OUT_CLR_MSB _u(31) -#define SIO_GPIO_OUT_CLR_LSB _u(0) -#define SIO_GPIO_OUT_CLR_ACCESS "WO" -// ============================================================================= -// Register : SIO_GPIO_HI_OUT_CLR -// Description : Output value clear for GPIO32..47, QSPI IOs and USB pins. -// Perform an atomic bit-clear on GPIO_HI_OUT, i.e. `GPIO_HI_OUT -// &= ~wdata` -#define SIO_GPIO_HI_OUT_CLR_OFFSET _u(0x00000024) -#define SIO_GPIO_HI_OUT_CLR_BITS _u(0xff00ffff) -#define SIO_GPIO_HI_OUT_CLR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : SIO_GPIO_HI_OUT_CLR_QSPI_SD -#define SIO_GPIO_HI_OUT_CLR_QSPI_SD_RESET _u(0x0) -#define SIO_GPIO_HI_OUT_CLR_QSPI_SD_BITS _u(0xf0000000) -#define SIO_GPIO_HI_OUT_CLR_QSPI_SD_MSB _u(31) -#define SIO_GPIO_HI_OUT_CLR_QSPI_SD_LSB _u(28) -#define SIO_GPIO_HI_OUT_CLR_QSPI_SD_ACCESS "WO" -// ----------------------------------------------------------------------------- -// Field : SIO_GPIO_HI_OUT_CLR_QSPI_CSN -#define SIO_GPIO_HI_OUT_CLR_QSPI_CSN_RESET _u(0x0) -#define SIO_GPIO_HI_OUT_CLR_QSPI_CSN_BITS _u(0x08000000) -#define SIO_GPIO_HI_OUT_CLR_QSPI_CSN_MSB _u(27) -#define SIO_GPIO_HI_OUT_CLR_QSPI_CSN_LSB _u(27) -#define SIO_GPIO_HI_OUT_CLR_QSPI_CSN_ACCESS "WO" -// ----------------------------------------------------------------------------- -// Field : SIO_GPIO_HI_OUT_CLR_QSPI_SCK -#define SIO_GPIO_HI_OUT_CLR_QSPI_SCK_RESET _u(0x0) -#define SIO_GPIO_HI_OUT_CLR_QSPI_SCK_BITS _u(0x04000000) -#define SIO_GPIO_HI_OUT_CLR_QSPI_SCK_MSB _u(26) -#define SIO_GPIO_HI_OUT_CLR_QSPI_SCK_LSB _u(26) -#define SIO_GPIO_HI_OUT_CLR_QSPI_SCK_ACCESS "WO" -// ----------------------------------------------------------------------------- -// Field : SIO_GPIO_HI_OUT_CLR_USB_DM -#define SIO_GPIO_HI_OUT_CLR_USB_DM_RESET _u(0x0) -#define SIO_GPIO_HI_OUT_CLR_USB_DM_BITS _u(0x02000000) -#define SIO_GPIO_HI_OUT_CLR_USB_DM_MSB _u(25) -#define SIO_GPIO_HI_OUT_CLR_USB_DM_LSB _u(25) -#define SIO_GPIO_HI_OUT_CLR_USB_DM_ACCESS "WO" -// ----------------------------------------------------------------------------- -// Field : SIO_GPIO_HI_OUT_CLR_USB_DP -#define SIO_GPIO_HI_OUT_CLR_USB_DP_RESET _u(0x0) -#define SIO_GPIO_HI_OUT_CLR_USB_DP_BITS _u(0x01000000) -#define SIO_GPIO_HI_OUT_CLR_USB_DP_MSB _u(24) -#define SIO_GPIO_HI_OUT_CLR_USB_DP_LSB _u(24) -#define SIO_GPIO_HI_OUT_CLR_USB_DP_ACCESS "WO" -// ----------------------------------------------------------------------------- -// Field : SIO_GPIO_HI_OUT_CLR_GPIO -#define SIO_GPIO_HI_OUT_CLR_GPIO_RESET _u(0x0000) -#define SIO_GPIO_HI_OUT_CLR_GPIO_BITS _u(0x0000ffff) -#define SIO_GPIO_HI_OUT_CLR_GPIO_MSB _u(15) -#define SIO_GPIO_HI_OUT_CLR_GPIO_LSB _u(0) -#define SIO_GPIO_HI_OUT_CLR_GPIO_ACCESS "WO" -// ============================================================================= -// Register : SIO_GPIO_OUT_XOR -// Description : GPIO0...31 output value XOR -// Perform an atomic bitwise XOR on GPIO_OUT, i.e. `GPIO_OUT ^= -// wdata` -#define SIO_GPIO_OUT_XOR_OFFSET _u(0x00000028) -#define SIO_GPIO_OUT_XOR_BITS _u(0xffffffff) -#define SIO_GPIO_OUT_XOR_RESET _u(0x00000000) -#define SIO_GPIO_OUT_XOR_MSB _u(31) -#define SIO_GPIO_OUT_XOR_LSB _u(0) -#define SIO_GPIO_OUT_XOR_ACCESS "WO" -// ============================================================================= -// Register : SIO_GPIO_HI_OUT_XOR -// Description : Output value XOR for GPIO32..47, QSPI IOs and USB pins. -// Perform an atomic bitwise XOR on GPIO_HI_OUT, i.e. `GPIO_HI_OUT -// ^= wdata` -#define SIO_GPIO_HI_OUT_XOR_OFFSET _u(0x0000002c) -#define SIO_GPIO_HI_OUT_XOR_BITS _u(0xff00ffff) -#define SIO_GPIO_HI_OUT_XOR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : SIO_GPIO_HI_OUT_XOR_QSPI_SD -#define SIO_GPIO_HI_OUT_XOR_QSPI_SD_RESET _u(0x0) -#define SIO_GPIO_HI_OUT_XOR_QSPI_SD_BITS _u(0xf0000000) -#define SIO_GPIO_HI_OUT_XOR_QSPI_SD_MSB _u(31) -#define SIO_GPIO_HI_OUT_XOR_QSPI_SD_LSB _u(28) -#define SIO_GPIO_HI_OUT_XOR_QSPI_SD_ACCESS "WO" -// ----------------------------------------------------------------------------- -// Field : SIO_GPIO_HI_OUT_XOR_QSPI_CSN -#define SIO_GPIO_HI_OUT_XOR_QSPI_CSN_RESET _u(0x0) -#define SIO_GPIO_HI_OUT_XOR_QSPI_CSN_BITS _u(0x08000000) -#define SIO_GPIO_HI_OUT_XOR_QSPI_CSN_MSB _u(27) -#define SIO_GPIO_HI_OUT_XOR_QSPI_CSN_LSB _u(27) -#define SIO_GPIO_HI_OUT_XOR_QSPI_CSN_ACCESS "WO" -// ----------------------------------------------------------------------------- -// Field : SIO_GPIO_HI_OUT_XOR_QSPI_SCK -#define SIO_GPIO_HI_OUT_XOR_QSPI_SCK_RESET _u(0x0) -#define SIO_GPIO_HI_OUT_XOR_QSPI_SCK_BITS _u(0x04000000) -#define SIO_GPIO_HI_OUT_XOR_QSPI_SCK_MSB _u(26) -#define SIO_GPIO_HI_OUT_XOR_QSPI_SCK_LSB _u(26) -#define SIO_GPIO_HI_OUT_XOR_QSPI_SCK_ACCESS "WO" -// ----------------------------------------------------------------------------- -// Field : SIO_GPIO_HI_OUT_XOR_USB_DM -#define SIO_GPIO_HI_OUT_XOR_USB_DM_RESET _u(0x0) -#define SIO_GPIO_HI_OUT_XOR_USB_DM_BITS _u(0x02000000) -#define SIO_GPIO_HI_OUT_XOR_USB_DM_MSB _u(25) -#define SIO_GPIO_HI_OUT_XOR_USB_DM_LSB _u(25) -#define SIO_GPIO_HI_OUT_XOR_USB_DM_ACCESS "WO" -// ----------------------------------------------------------------------------- -// Field : SIO_GPIO_HI_OUT_XOR_USB_DP -#define SIO_GPIO_HI_OUT_XOR_USB_DP_RESET _u(0x0) -#define SIO_GPIO_HI_OUT_XOR_USB_DP_BITS _u(0x01000000) -#define SIO_GPIO_HI_OUT_XOR_USB_DP_MSB _u(24) -#define SIO_GPIO_HI_OUT_XOR_USB_DP_LSB _u(24) -#define SIO_GPIO_HI_OUT_XOR_USB_DP_ACCESS "WO" -// ----------------------------------------------------------------------------- -// Field : SIO_GPIO_HI_OUT_XOR_GPIO -#define SIO_GPIO_HI_OUT_XOR_GPIO_RESET _u(0x0000) -#define SIO_GPIO_HI_OUT_XOR_GPIO_BITS _u(0x0000ffff) -#define SIO_GPIO_HI_OUT_XOR_GPIO_MSB _u(15) -#define SIO_GPIO_HI_OUT_XOR_GPIO_LSB _u(0) -#define SIO_GPIO_HI_OUT_XOR_GPIO_ACCESS "WO" -// ============================================================================= -// Register : SIO_GPIO_OE -// Description : GPIO0...31 output enable -// Set output enable (1/0 -> output/input) for GPIO0...31. Reading -// back gives the last value written. -// -// If core 0 and core 1 both write to GPIO_OE simultaneously (or -// to a SET/CLR/XOR alias), the result is as though the write from -// core 0 took place first, and the write from core 1 was then -// applied to that intermediate result. -// -// In the Non-secure SIO, Secure-only GPIOs (as per ACCESSCTRL) -// ignore writes, and their output status reads back as zero. This -// is also true for SET/CLR/XOR aliases of this register. -#define SIO_GPIO_OE_OFFSET _u(0x00000030) -#define SIO_GPIO_OE_BITS _u(0xffffffff) -#define SIO_GPIO_OE_RESET _u(0x00000000) -#define SIO_GPIO_OE_MSB _u(31) -#define SIO_GPIO_OE_LSB _u(0) -#define SIO_GPIO_OE_ACCESS "RW" -// ============================================================================= -// Register : SIO_GPIO_HI_OE -// Description : Output enable value for GPIO32...47, QSPI IOs and USB pins. -// -// Write output enable (1/0 -> output/input). Reading back gives -// the last value written. If core 0 and core 1 both write to -// GPIO_HI_OE simultaneously (or to a SET/CLR/XOR alias), the -// result is as though the write from core 0 took place first, and -// the write from core 1 was then applied to that intermediate -// result. -// -// In the Non-secure SIO, Secure-only GPIOs (as per ACCESSCTRL) -// ignore writes, and their output status reads back as zero. This -// is also true for SET/CLR/XOR aliases of this register. -#define SIO_GPIO_HI_OE_OFFSET _u(0x00000034) -#define SIO_GPIO_HI_OE_BITS _u(0xff00ffff) -#define SIO_GPIO_HI_OE_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : SIO_GPIO_HI_OE_QSPI_SD -// Description : Output enable value for QSPI SD0 (MOSI), SD1 (MISO), SD2 and -// SD3 pins -#define SIO_GPIO_HI_OE_QSPI_SD_RESET _u(0x0) -#define SIO_GPIO_HI_OE_QSPI_SD_BITS _u(0xf0000000) -#define SIO_GPIO_HI_OE_QSPI_SD_MSB _u(31) -#define SIO_GPIO_HI_OE_QSPI_SD_LSB _u(28) -#define SIO_GPIO_HI_OE_QSPI_SD_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SIO_GPIO_HI_OE_QSPI_CSN -// Description : Output enable value for QSPI CSn pin -#define SIO_GPIO_HI_OE_QSPI_CSN_RESET _u(0x0) -#define SIO_GPIO_HI_OE_QSPI_CSN_BITS _u(0x08000000) -#define SIO_GPIO_HI_OE_QSPI_CSN_MSB _u(27) -#define SIO_GPIO_HI_OE_QSPI_CSN_LSB _u(27) -#define SIO_GPIO_HI_OE_QSPI_CSN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SIO_GPIO_HI_OE_QSPI_SCK -// Description : Output enable value for QSPI SCK pin -#define SIO_GPIO_HI_OE_QSPI_SCK_RESET _u(0x0) -#define SIO_GPIO_HI_OE_QSPI_SCK_BITS _u(0x04000000) -#define SIO_GPIO_HI_OE_QSPI_SCK_MSB _u(26) -#define SIO_GPIO_HI_OE_QSPI_SCK_LSB _u(26) -#define SIO_GPIO_HI_OE_QSPI_SCK_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SIO_GPIO_HI_OE_USB_DM -// Description : Output enable value for USB D- pin -#define SIO_GPIO_HI_OE_USB_DM_RESET _u(0x0) -#define SIO_GPIO_HI_OE_USB_DM_BITS _u(0x02000000) -#define SIO_GPIO_HI_OE_USB_DM_MSB _u(25) -#define SIO_GPIO_HI_OE_USB_DM_LSB _u(25) -#define SIO_GPIO_HI_OE_USB_DM_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SIO_GPIO_HI_OE_USB_DP -// Description : Output enable value for USB D+ pin -#define SIO_GPIO_HI_OE_USB_DP_RESET _u(0x0) -#define SIO_GPIO_HI_OE_USB_DP_BITS _u(0x01000000) -#define SIO_GPIO_HI_OE_USB_DP_MSB _u(24) -#define SIO_GPIO_HI_OE_USB_DP_LSB _u(24) -#define SIO_GPIO_HI_OE_USB_DP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SIO_GPIO_HI_OE_GPIO -// Description : Output enable value for GPIO32...47 -#define SIO_GPIO_HI_OE_GPIO_RESET _u(0x0000) -#define SIO_GPIO_HI_OE_GPIO_BITS _u(0x0000ffff) -#define SIO_GPIO_HI_OE_GPIO_MSB _u(15) -#define SIO_GPIO_HI_OE_GPIO_LSB _u(0) -#define SIO_GPIO_HI_OE_GPIO_ACCESS "RW" -// ============================================================================= -// Register : SIO_GPIO_OE_SET -// Description : GPIO0...31 output enable set -// Perform an atomic bit-set on GPIO_OE, i.e. `GPIO_OE |= wdata` -#define SIO_GPIO_OE_SET_OFFSET _u(0x00000038) -#define SIO_GPIO_OE_SET_BITS _u(0xffffffff) -#define SIO_GPIO_OE_SET_RESET _u(0x00000000) -#define SIO_GPIO_OE_SET_MSB _u(31) -#define SIO_GPIO_OE_SET_LSB _u(0) -#define SIO_GPIO_OE_SET_ACCESS "WO" -// ============================================================================= -// Register : SIO_GPIO_HI_OE_SET -// Description : Output enable set for GPIO32...47, QSPI IOs and USB pins. -// Perform an atomic bit-set on GPIO_HI_OE, i.e. `GPIO_HI_OE |= -// wdata` -#define SIO_GPIO_HI_OE_SET_OFFSET _u(0x0000003c) -#define SIO_GPIO_HI_OE_SET_BITS _u(0xff00ffff) -#define SIO_GPIO_HI_OE_SET_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : SIO_GPIO_HI_OE_SET_QSPI_SD -#define SIO_GPIO_HI_OE_SET_QSPI_SD_RESET _u(0x0) -#define SIO_GPIO_HI_OE_SET_QSPI_SD_BITS _u(0xf0000000) -#define SIO_GPIO_HI_OE_SET_QSPI_SD_MSB _u(31) -#define SIO_GPIO_HI_OE_SET_QSPI_SD_LSB _u(28) -#define SIO_GPIO_HI_OE_SET_QSPI_SD_ACCESS "WO" -// ----------------------------------------------------------------------------- -// Field : SIO_GPIO_HI_OE_SET_QSPI_CSN -#define SIO_GPIO_HI_OE_SET_QSPI_CSN_RESET _u(0x0) -#define SIO_GPIO_HI_OE_SET_QSPI_CSN_BITS _u(0x08000000) -#define SIO_GPIO_HI_OE_SET_QSPI_CSN_MSB _u(27) -#define SIO_GPIO_HI_OE_SET_QSPI_CSN_LSB _u(27) -#define SIO_GPIO_HI_OE_SET_QSPI_CSN_ACCESS "WO" -// ----------------------------------------------------------------------------- -// Field : SIO_GPIO_HI_OE_SET_QSPI_SCK -#define SIO_GPIO_HI_OE_SET_QSPI_SCK_RESET _u(0x0) -#define SIO_GPIO_HI_OE_SET_QSPI_SCK_BITS _u(0x04000000) -#define SIO_GPIO_HI_OE_SET_QSPI_SCK_MSB _u(26) -#define SIO_GPIO_HI_OE_SET_QSPI_SCK_LSB _u(26) -#define SIO_GPIO_HI_OE_SET_QSPI_SCK_ACCESS "WO" -// ----------------------------------------------------------------------------- -// Field : SIO_GPIO_HI_OE_SET_USB_DM -#define SIO_GPIO_HI_OE_SET_USB_DM_RESET _u(0x0) -#define SIO_GPIO_HI_OE_SET_USB_DM_BITS _u(0x02000000) -#define SIO_GPIO_HI_OE_SET_USB_DM_MSB _u(25) -#define SIO_GPIO_HI_OE_SET_USB_DM_LSB _u(25) -#define SIO_GPIO_HI_OE_SET_USB_DM_ACCESS "WO" -// ----------------------------------------------------------------------------- -// Field : SIO_GPIO_HI_OE_SET_USB_DP -#define SIO_GPIO_HI_OE_SET_USB_DP_RESET _u(0x0) -#define SIO_GPIO_HI_OE_SET_USB_DP_BITS _u(0x01000000) -#define SIO_GPIO_HI_OE_SET_USB_DP_MSB _u(24) -#define SIO_GPIO_HI_OE_SET_USB_DP_LSB _u(24) -#define SIO_GPIO_HI_OE_SET_USB_DP_ACCESS "WO" -// ----------------------------------------------------------------------------- -// Field : SIO_GPIO_HI_OE_SET_GPIO -#define SIO_GPIO_HI_OE_SET_GPIO_RESET _u(0x0000) -#define SIO_GPIO_HI_OE_SET_GPIO_BITS _u(0x0000ffff) -#define SIO_GPIO_HI_OE_SET_GPIO_MSB _u(15) -#define SIO_GPIO_HI_OE_SET_GPIO_LSB _u(0) -#define SIO_GPIO_HI_OE_SET_GPIO_ACCESS "WO" -// ============================================================================= -// Register : SIO_GPIO_OE_CLR -// Description : GPIO0...31 output enable clear -// Perform an atomic bit-clear on GPIO_OE, i.e. `GPIO_OE &= -// ~wdata` -#define SIO_GPIO_OE_CLR_OFFSET _u(0x00000040) -#define SIO_GPIO_OE_CLR_BITS _u(0xffffffff) -#define SIO_GPIO_OE_CLR_RESET _u(0x00000000) -#define SIO_GPIO_OE_CLR_MSB _u(31) -#define SIO_GPIO_OE_CLR_LSB _u(0) -#define SIO_GPIO_OE_CLR_ACCESS "WO" -// ============================================================================= -// Register : SIO_GPIO_HI_OE_CLR -// Description : Output enable clear for GPIO32...47, QSPI IOs and USB pins. -// Perform an atomic bit-clear on GPIO_HI_OE, i.e. `GPIO_HI_OE &= -// ~wdata` -#define SIO_GPIO_HI_OE_CLR_OFFSET _u(0x00000044) -#define SIO_GPIO_HI_OE_CLR_BITS _u(0xff00ffff) -#define SIO_GPIO_HI_OE_CLR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : SIO_GPIO_HI_OE_CLR_QSPI_SD -#define SIO_GPIO_HI_OE_CLR_QSPI_SD_RESET _u(0x0) -#define SIO_GPIO_HI_OE_CLR_QSPI_SD_BITS _u(0xf0000000) -#define SIO_GPIO_HI_OE_CLR_QSPI_SD_MSB _u(31) -#define SIO_GPIO_HI_OE_CLR_QSPI_SD_LSB _u(28) -#define SIO_GPIO_HI_OE_CLR_QSPI_SD_ACCESS "WO" -// ----------------------------------------------------------------------------- -// Field : SIO_GPIO_HI_OE_CLR_QSPI_CSN -#define SIO_GPIO_HI_OE_CLR_QSPI_CSN_RESET _u(0x0) -#define SIO_GPIO_HI_OE_CLR_QSPI_CSN_BITS _u(0x08000000) -#define SIO_GPIO_HI_OE_CLR_QSPI_CSN_MSB _u(27) -#define SIO_GPIO_HI_OE_CLR_QSPI_CSN_LSB _u(27) -#define SIO_GPIO_HI_OE_CLR_QSPI_CSN_ACCESS "WO" -// ----------------------------------------------------------------------------- -// Field : SIO_GPIO_HI_OE_CLR_QSPI_SCK -#define SIO_GPIO_HI_OE_CLR_QSPI_SCK_RESET _u(0x0) -#define SIO_GPIO_HI_OE_CLR_QSPI_SCK_BITS _u(0x04000000) -#define SIO_GPIO_HI_OE_CLR_QSPI_SCK_MSB _u(26) -#define SIO_GPIO_HI_OE_CLR_QSPI_SCK_LSB _u(26) -#define SIO_GPIO_HI_OE_CLR_QSPI_SCK_ACCESS "WO" -// ----------------------------------------------------------------------------- -// Field : SIO_GPIO_HI_OE_CLR_USB_DM -#define SIO_GPIO_HI_OE_CLR_USB_DM_RESET _u(0x0) -#define SIO_GPIO_HI_OE_CLR_USB_DM_BITS _u(0x02000000) -#define SIO_GPIO_HI_OE_CLR_USB_DM_MSB _u(25) -#define SIO_GPIO_HI_OE_CLR_USB_DM_LSB _u(25) -#define SIO_GPIO_HI_OE_CLR_USB_DM_ACCESS "WO" -// ----------------------------------------------------------------------------- -// Field : SIO_GPIO_HI_OE_CLR_USB_DP -#define SIO_GPIO_HI_OE_CLR_USB_DP_RESET _u(0x0) -#define SIO_GPIO_HI_OE_CLR_USB_DP_BITS _u(0x01000000) -#define SIO_GPIO_HI_OE_CLR_USB_DP_MSB _u(24) -#define SIO_GPIO_HI_OE_CLR_USB_DP_LSB _u(24) -#define SIO_GPIO_HI_OE_CLR_USB_DP_ACCESS "WO" -// ----------------------------------------------------------------------------- -// Field : SIO_GPIO_HI_OE_CLR_GPIO -#define SIO_GPIO_HI_OE_CLR_GPIO_RESET _u(0x0000) -#define SIO_GPIO_HI_OE_CLR_GPIO_BITS _u(0x0000ffff) -#define SIO_GPIO_HI_OE_CLR_GPIO_MSB _u(15) -#define SIO_GPIO_HI_OE_CLR_GPIO_LSB _u(0) -#define SIO_GPIO_HI_OE_CLR_GPIO_ACCESS "WO" -// ============================================================================= -// Register : SIO_GPIO_OE_XOR -// Description : GPIO0...31 output enable XOR -// Perform an atomic bitwise XOR on GPIO_OE, i.e. `GPIO_OE ^= -// wdata` -#define SIO_GPIO_OE_XOR_OFFSET _u(0x00000048) -#define SIO_GPIO_OE_XOR_BITS _u(0xffffffff) -#define SIO_GPIO_OE_XOR_RESET _u(0x00000000) -#define SIO_GPIO_OE_XOR_MSB _u(31) -#define SIO_GPIO_OE_XOR_LSB _u(0) -#define SIO_GPIO_OE_XOR_ACCESS "WO" -// ============================================================================= -// Register : SIO_GPIO_HI_OE_XOR -// Description : Output enable XOR for GPIO32...47, QSPI IOs and USB pins. -// Perform an atomic bitwise XOR on GPIO_HI_OE, i.e. `GPIO_HI_OE -// ^= wdata` -#define SIO_GPIO_HI_OE_XOR_OFFSET _u(0x0000004c) -#define SIO_GPIO_HI_OE_XOR_BITS _u(0xff00ffff) -#define SIO_GPIO_HI_OE_XOR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : SIO_GPIO_HI_OE_XOR_QSPI_SD -#define SIO_GPIO_HI_OE_XOR_QSPI_SD_RESET _u(0x0) -#define SIO_GPIO_HI_OE_XOR_QSPI_SD_BITS _u(0xf0000000) -#define SIO_GPIO_HI_OE_XOR_QSPI_SD_MSB _u(31) -#define SIO_GPIO_HI_OE_XOR_QSPI_SD_LSB _u(28) -#define SIO_GPIO_HI_OE_XOR_QSPI_SD_ACCESS "WO" -// ----------------------------------------------------------------------------- -// Field : SIO_GPIO_HI_OE_XOR_QSPI_CSN -#define SIO_GPIO_HI_OE_XOR_QSPI_CSN_RESET _u(0x0) -#define SIO_GPIO_HI_OE_XOR_QSPI_CSN_BITS _u(0x08000000) -#define SIO_GPIO_HI_OE_XOR_QSPI_CSN_MSB _u(27) -#define SIO_GPIO_HI_OE_XOR_QSPI_CSN_LSB _u(27) -#define SIO_GPIO_HI_OE_XOR_QSPI_CSN_ACCESS "WO" -// ----------------------------------------------------------------------------- -// Field : SIO_GPIO_HI_OE_XOR_QSPI_SCK -#define SIO_GPIO_HI_OE_XOR_QSPI_SCK_RESET _u(0x0) -#define SIO_GPIO_HI_OE_XOR_QSPI_SCK_BITS _u(0x04000000) -#define SIO_GPIO_HI_OE_XOR_QSPI_SCK_MSB _u(26) -#define SIO_GPIO_HI_OE_XOR_QSPI_SCK_LSB _u(26) -#define SIO_GPIO_HI_OE_XOR_QSPI_SCK_ACCESS "WO" -// ----------------------------------------------------------------------------- -// Field : SIO_GPIO_HI_OE_XOR_USB_DM -#define SIO_GPIO_HI_OE_XOR_USB_DM_RESET _u(0x0) -#define SIO_GPIO_HI_OE_XOR_USB_DM_BITS _u(0x02000000) -#define SIO_GPIO_HI_OE_XOR_USB_DM_MSB _u(25) -#define SIO_GPIO_HI_OE_XOR_USB_DM_LSB _u(25) -#define SIO_GPIO_HI_OE_XOR_USB_DM_ACCESS "WO" -// ----------------------------------------------------------------------------- -// Field : SIO_GPIO_HI_OE_XOR_USB_DP -#define SIO_GPIO_HI_OE_XOR_USB_DP_RESET _u(0x0) -#define SIO_GPIO_HI_OE_XOR_USB_DP_BITS _u(0x01000000) -#define SIO_GPIO_HI_OE_XOR_USB_DP_MSB _u(24) -#define SIO_GPIO_HI_OE_XOR_USB_DP_LSB _u(24) -#define SIO_GPIO_HI_OE_XOR_USB_DP_ACCESS "WO" -// ----------------------------------------------------------------------------- -// Field : SIO_GPIO_HI_OE_XOR_GPIO -#define SIO_GPIO_HI_OE_XOR_GPIO_RESET _u(0x0000) -#define SIO_GPIO_HI_OE_XOR_GPIO_BITS _u(0x0000ffff) -#define SIO_GPIO_HI_OE_XOR_GPIO_MSB _u(15) -#define SIO_GPIO_HI_OE_XOR_GPIO_LSB _u(0) -#define SIO_GPIO_HI_OE_XOR_GPIO_ACCESS "WO" -// ============================================================================= -// Register : SIO_FIFO_ST -// Description : Status register for inter-core FIFOs (mailboxes). -// There is one FIFO in the core 0 -> core 1 direction, and one -// core 1 -> core 0. Both are 32 bits wide and 8 words deep. -// Core 0 can see the read side of the 1->0 FIFO (RX), and the -// write side of 0->1 FIFO (TX). -// Core 1 can see the read side of the 0->1 FIFO (RX), and the -// write side of 1->0 FIFO (TX). -// The SIO IRQ for each core is the logical OR of the VLD, WOF and -// ROE fields of its FIFO_ST register. -#define SIO_FIFO_ST_OFFSET _u(0x00000050) -#define SIO_FIFO_ST_BITS _u(0x0000000f) -#define SIO_FIFO_ST_RESET _u(0x00000002) -// ----------------------------------------------------------------------------- -// Field : SIO_FIFO_ST_ROE -// Description : Sticky flag indicating the RX FIFO was read when empty. This -// read was ignored by the FIFO. -#define SIO_FIFO_ST_ROE_RESET _u(0x0) -#define SIO_FIFO_ST_ROE_BITS _u(0x00000008) -#define SIO_FIFO_ST_ROE_MSB _u(3) -#define SIO_FIFO_ST_ROE_LSB _u(3) -#define SIO_FIFO_ST_ROE_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : SIO_FIFO_ST_WOF -// Description : Sticky flag indicating the TX FIFO was written when full. This -// write was ignored by the FIFO. -#define SIO_FIFO_ST_WOF_RESET _u(0x0) -#define SIO_FIFO_ST_WOF_BITS _u(0x00000004) -#define SIO_FIFO_ST_WOF_MSB _u(2) -#define SIO_FIFO_ST_WOF_LSB _u(2) -#define SIO_FIFO_ST_WOF_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : SIO_FIFO_ST_RDY -// Description : Value is 1 if this core's TX FIFO is not full (i.e. if FIFO_WR -// is ready for more data) -#define SIO_FIFO_ST_RDY_RESET _u(0x1) -#define SIO_FIFO_ST_RDY_BITS _u(0x00000002) -#define SIO_FIFO_ST_RDY_MSB _u(1) -#define SIO_FIFO_ST_RDY_LSB _u(1) -#define SIO_FIFO_ST_RDY_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : SIO_FIFO_ST_VLD -// Description : Value is 1 if this core's RX FIFO is not empty (i.e. if FIFO_RD -// is valid) -#define SIO_FIFO_ST_VLD_RESET _u(0x0) -#define SIO_FIFO_ST_VLD_BITS _u(0x00000001) -#define SIO_FIFO_ST_VLD_MSB _u(0) -#define SIO_FIFO_ST_VLD_LSB _u(0) -#define SIO_FIFO_ST_VLD_ACCESS "RO" -// ============================================================================= -// Register : SIO_FIFO_WR -// Description : Write access to this core's TX FIFO -#define SIO_FIFO_WR_OFFSET _u(0x00000054) -#define SIO_FIFO_WR_BITS _u(0xffffffff) -#define SIO_FIFO_WR_RESET _u(0x00000000) -#define SIO_FIFO_WR_MSB _u(31) -#define SIO_FIFO_WR_LSB _u(0) -#define SIO_FIFO_WR_ACCESS "WF" -// ============================================================================= -// Register : SIO_FIFO_RD -// Description : Read access to this core's RX FIFO -#define SIO_FIFO_RD_OFFSET _u(0x00000058) -#define SIO_FIFO_RD_BITS _u(0xffffffff) -#define SIO_FIFO_RD_RESET "-" -#define SIO_FIFO_RD_MSB _u(31) -#define SIO_FIFO_RD_LSB _u(0) -#define SIO_FIFO_RD_ACCESS "RF" -// ============================================================================= -// Register : SIO_SPINLOCK_ST -// Description : Spinlock state -// A bitmap containing the state of all 32 spinlocks (1=locked). -// Mainly intended for debugging. -#define SIO_SPINLOCK_ST_OFFSET _u(0x0000005c) -#define SIO_SPINLOCK_ST_BITS _u(0xffffffff) -#define SIO_SPINLOCK_ST_RESET _u(0x00000000) -#define SIO_SPINLOCK_ST_MSB _u(31) -#define SIO_SPINLOCK_ST_LSB _u(0) -#define SIO_SPINLOCK_ST_ACCESS "RO" -// ============================================================================= -// Register : SIO_INTERP0_ACCUM0 -// Description : Read/write access to accumulator 0 -#define SIO_INTERP0_ACCUM0_OFFSET _u(0x00000080) -#define SIO_INTERP0_ACCUM0_BITS _u(0xffffffff) -#define SIO_INTERP0_ACCUM0_RESET _u(0x00000000) -#define SIO_INTERP0_ACCUM0_MSB _u(31) -#define SIO_INTERP0_ACCUM0_LSB _u(0) -#define SIO_INTERP0_ACCUM0_ACCESS "RW" -// ============================================================================= -// Register : SIO_INTERP0_ACCUM1 -// Description : Read/write access to accumulator 1 -#define SIO_INTERP0_ACCUM1_OFFSET _u(0x00000084) -#define SIO_INTERP0_ACCUM1_BITS _u(0xffffffff) -#define SIO_INTERP0_ACCUM1_RESET _u(0x00000000) -#define SIO_INTERP0_ACCUM1_MSB _u(31) -#define SIO_INTERP0_ACCUM1_LSB _u(0) -#define SIO_INTERP0_ACCUM1_ACCESS "RW" -// ============================================================================= -// Register : SIO_INTERP0_BASE0 -// Description : Read/write access to BASE0 register. -#define SIO_INTERP0_BASE0_OFFSET _u(0x00000088) -#define SIO_INTERP0_BASE0_BITS _u(0xffffffff) -#define SIO_INTERP0_BASE0_RESET _u(0x00000000) -#define SIO_INTERP0_BASE0_MSB _u(31) -#define SIO_INTERP0_BASE0_LSB _u(0) -#define SIO_INTERP0_BASE0_ACCESS "RW" -// ============================================================================= -// Register : SIO_INTERP0_BASE1 -// Description : Read/write access to BASE1 register. -#define SIO_INTERP0_BASE1_OFFSET _u(0x0000008c) -#define SIO_INTERP0_BASE1_BITS _u(0xffffffff) -#define SIO_INTERP0_BASE1_RESET _u(0x00000000) -#define SIO_INTERP0_BASE1_MSB _u(31) -#define SIO_INTERP0_BASE1_LSB _u(0) -#define SIO_INTERP0_BASE1_ACCESS "RW" -// ============================================================================= -// Register : SIO_INTERP0_BASE2 -// Description : Read/write access to BASE2 register. -#define SIO_INTERP0_BASE2_OFFSET _u(0x00000090) -#define SIO_INTERP0_BASE2_BITS _u(0xffffffff) -#define SIO_INTERP0_BASE2_RESET _u(0x00000000) -#define SIO_INTERP0_BASE2_MSB _u(31) -#define SIO_INTERP0_BASE2_LSB _u(0) -#define SIO_INTERP0_BASE2_ACCESS "RW" -// ============================================================================= -// Register : SIO_INTERP0_POP_LANE0 -// Description : Read LANE0 result, and simultaneously write lane results to -// both accumulators (POP). -#define SIO_INTERP0_POP_LANE0_OFFSET _u(0x00000094) -#define SIO_INTERP0_POP_LANE0_BITS _u(0xffffffff) -#define SIO_INTERP0_POP_LANE0_RESET _u(0x00000000) -#define SIO_INTERP0_POP_LANE0_MSB _u(31) -#define SIO_INTERP0_POP_LANE0_LSB _u(0) -#define SIO_INTERP0_POP_LANE0_ACCESS "RO" -// ============================================================================= -// Register : SIO_INTERP0_POP_LANE1 -// Description : Read LANE1 result, and simultaneously write lane results to -// both accumulators (POP). -#define SIO_INTERP0_POP_LANE1_OFFSET _u(0x00000098) -#define SIO_INTERP0_POP_LANE1_BITS _u(0xffffffff) -#define SIO_INTERP0_POP_LANE1_RESET _u(0x00000000) -#define SIO_INTERP0_POP_LANE1_MSB _u(31) -#define SIO_INTERP0_POP_LANE1_LSB _u(0) -#define SIO_INTERP0_POP_LANE1_ACCESS "RO" -// ============================================================================= -// Register : SIO_INTERP0_POP_FULL -// Description : Read FULL result, and simultaneously write lane results to both -// accumulators (POP). -#define SIO_INTERP0_POP_FULL_OFFSET _u(0x0000009c) -#define SIO_INTERP0_POP_FULL_BITS _u(0xffffffff) -#define SIO_INTERP0_POP_FULL_RESET _u(0x00000000) -#define SIO_INTERP0_POP_FULL_MSB _u(31) -#define SIO_INTERP0_POP_FULL_LSB _u(0) -#define SIO_INTERP0_POP_FULL_ACCESS "RO" -// ============================================================================= -// Register : SIO_INTERP0_PEEK_LANE0 -// Description : Read LANE0 result, without altering any internal state (PEEK). -#define SIO_INTERP0_PEEK_LANE0_OFFSET _u(0x000000a0) -#define SIO_INTERP0_PEEK_LANE0_BITS _u(0xffffffff) -#define SIO_INTERP0_PEEK_LANE0_RESET _u(0x00000000) -#define SIO_INTERP0_PEEK_LANE0_MSB _u(31) -#define SIO_INTERP0_PEEK_LANE0_LSB _u(0) -#define SIO_INTERP0_PEEK_LANE0_ACCESS "RO" -// ============================================================================= -// Register : SIO_INTERP0_PEEK_LANE1 -// Description : Read LANE1 result, without altering any internal state (PEEK). -#define SIO_INTERP0_PEEK_LANE1_OFFSET _u(0x000000a4) -#define SIO_INTERP0_PEEK_LANE1_BITS _u(0xffffffff) -#define SIO_INTERP0_PEEK_LANE1_RESET _u(0x00000000) -#define SIO_INTERP0_PEEK_LANE1_MSB _u(31) -#define SIO_INTERP0_PEEK_LANE1_LSB _u(0) -#define SIO_INTERP0_PEEK_LANE1_ACCESS "RO" -// ============================================================================= -// Register : SIO_INTERP0_PEEK_FULL -// Description : Read FULL result, without altering any internal state (PEEK). -#define SIO_INTERP0_PEEK_FULL_OFFSET _u(0x000000a8) -#define SIO_INTERP0_PEEK_FULL_BITS _u(0xffffffff) -#define SIO_INTERP0_PEEK_FULL_RESET _u(0x00000000) -#define SIO_INTERP0_PEEK_FULL_MSB _u(31) -#define SIO_INTERP0_PEEK_FULL_LSB _u(0) -#define SIO_INTERP0_PEEK_FULL_ACCESS "RO" -// ============================================================================= -// Register : SIO_INTERP0_CTRL_LANE0 -// Description : Control register for lane 0 -#define SIO_INTERP0_CTRL_LANE0_OFFSET _u(0x000000ac) -#define SIO_INTERP0_CTRL_LANE0_BITS _u(0x03bfffff) -#define SIO_INTERP0_CTRL_LANE0_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : SIO_INTERP0_CTRL_LANE0_OVERF -// Description : Set if either OVERF0 or OVERF1 is set. -#define SIO_INTERP0_CTRL_LANE0_OVERF_RESET _u(0x0) -#define SIO_INTERP0_CTRL_LANE0_OVERF_BITS _u(0x02000000) -#define SIO_INTERP0_CTRL_LANE0_OVERF_MSB _u(25) -#define SIO_INTERP0_CTRL_LANE0_OVERF_LSB _u(25) -#define SIO_INTERP0_CTRL_LANE0_OVERF_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : SIO_INTERP0_CTRL_LANE0_OVERF1 -// Description : Indicates if any masked-off MSBs in ACCUM1 are set. -#define SIO_INTERP0_CTRL_LANE0_OVERF1_RESET _u(0x0) -#define SIO_INTERP0_CTRL_LANE0_OVERF1_BITS _u(0x01000000) -#define SIO_INTERP0_CTRL_LANE0_OVERF1_MSB _u(24) -#define SIO_INTERP0_CTRL_LANE0_OVERF1_LSB _u(24) -#define SIO_INTERP0_CTRL_LANE0_OVERF1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : SIO_INTERP0_CTRL_LANE0_OVERF0 -// Description : Indicates if any masked-off MSBs in ACCUM0 are set. -#define SIO_INTERP0_CTRL_LANE0_OVERF0_RESET _u(0x0) -#define SIO_INTERP0_CTRL_LANE0_OVERF0_BITS _u(0x00800000) -#define SIO_INTERP0_CTRL_LANE0_OVERF0_MSB _u(23) -#define SIO_INTERP0_CTRL_LANE0_OVERF0_LSB _u(23) -#define SIO_INTERP0_CTRL_LANE0_OVERF0_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : SIO_INTERP0_CTRL_LANE0_BLEND -// Description : Only present on INTERP0 on each core. If BLEND mode is enabled: -// - LANE1 result is a linear interpolation between BASE0 and -// BASE1, controlled -// by the 8 LSBs of lane 1 shift and mask value (a fractional -// number between -// 0 and 255/256ths) -// - LANE0 result does not have BASE0 added (yields only the 8 -// LSBs of lane 1 shift+mask value) -// - FULL result does not have lane 1 shift+mask value added -// (BASE2 + lane 0 shift+mask) -// LANE1 SIGNED flag controls whether the interpolation is signed -// or unsigned. -#define SIO_INTERP0_CTRL_LANE0_BLEND_RESET _u(0x0) -#define SIO_INTERP0_CTRL_LANE0_BLEND_BITS _u(0x00200000) -#define SIO_INTERP0_CTRL_LANE0_BLEND_MSB _u(21) -#define SIO_INTERP0_CTRL_LANE0_BLEND_LSB _u(21) -#define SIO_INTERP0_CTRL_LANE0_BLEND_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SIO_INTERP0_CTRL_LANE0_FORCE_MSB -// Description : ORed into bits 29:28 of the lane result presented to the -// processor on the bus. -// No effect on the internal 32-bit datapath. Handy for using a -// lane to generate sequence -// of pointers into flash or SRAM. -#define SIO_INTERP0_CTRL_LANE0_FORCE_MSB_RESET _u(0x0) -#define SIO_INTERP0_CTRL_LANE0_FORCE_MSB_BITS _u(0x00180000) -#define SIO_INTERP0_CTRL_LANE0_FORCE_MSB_MSB _u(20) -#define SIO_INTERP0_CTRL_LANE0_FORCE_MSB_LSB _u(19) -#define SIO_INTERP0_CTRL_LANE0_FORCE_MSB_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SIO_INTERP0_CTRL_LANE0_ADD_RAW -// Description : If 1, mask + shift is bypassed for LANE0 result. This does not -// affect FULL result. -#define SIO_INTERP0_CTRL_LANE0_ADD_RAW_RESET _u(0x0) -#define SIO_INTERP0_CTRL_LANE0_ADD_RAW_BITS _u(0x00040000) -#define SIO_INTERP0_CTRL_LANE0_ADD_RAW_MSB _u(18) -#define SIO_INTERP0_CTRL_LANE0_ADD_RAW_LSB _u(18) -#define SIO_INTERP0_CTRL_LANE0_ADD_RAW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SIO_INTERP0_CTRL_LANE0_CROSS_RESULT -// Description : If 1, feed the opposite lane's result into this lane's -// accumulator on POP. -#define SIO_INTERP0_CTRL_LANE0_CROSS_RESULT_RESET _u(0x0) -#define SIO_INTERP0_CTRL_LANE0_CROSS_RESULT_BITS _u(0x00020000) -#define SIO_INTERP0_CTRL_LANE0_CROSS_RESULT_MSB _u(17) -#define SIO_INTERP0_CTRL_LANE0_CROSS_RESULT_LSB _u(17) -#define SIO_INTERP0_CTRL_LANE0_CROSS_RESULT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SIO_INTERP0_CTRL_LANE0_CROSS_INPUT -// Description : If 1, feed the opposite lane's accumulator into this lane's -// shift + mask hardware. -// Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is -// before the shift+mask bypass) -#define SIO_INTERP0_CTRL_LANE0_CROSS_INPUT_RESET _u(0x0) -#define SIO_INTERP0_CTRL_LANE0_CROSS_INPUT_BITS _u(0x00010000) -#define SIO_INTERP0_CTRL_LANE0_CROSS_INPUT_MSB _u(16) -#define SIO_INTERP0_CTRL_LANE0_CROSS_INPUT_LSB _u(16) -#define SIO_INTERP0_CTRL_LANE0_CROSS_INPUT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SIO_INTERP0_CTRL_LANE0_SIGNED -// Description : If SIGNED is set, the shifted and masked accumulator value is -// sign-extended to 32 bits -// before adding to BASE0, and LANE0 PEEK/POP appear extended to -// 32 bits when read by processor. -#define SIO_INTERP0_CTRL_LANE0_SIGNED_RESET _u(0x0) -#define SIO_INTERP0_CTRL_LANE0_SIGNED_BITS _u(0x00008000) -#define SIO_INTERP0_CTRL_LANE0_SIGNED_MSB _u(15) -#define SIO_INTERP0_CTRL_LANE0_SIGNED_LSB _u(15) -#define SIO_INTERP0_CTRL_LANE0_SIGNED_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SIO_INTERP0_CTRL_LANE0_MASK_MSB -// Description : The most-significant bit allowed to pass by the mask -// (inclusive) -// Setting MSB < LSB may cause chip to turn inside-out -#define SIO_INTERP0_CTRL_LANE0_MASK_MSB_RESET _u(0x00) -#define SIO_INTERP0_CTRL_LANE0_MASK_MSB_BITS _u(0x00007c00) -#define SIO_INTERP0_CTRL_LANE0_MASK_MSB_MSB _u(14) -#define SIO_INTERP0_CTRL_LANE0_MASK_MSB_LSB _u(10) -#define SIO_INTERP0_CTRL_LANE0_MASK_MSB_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SIO_INTERP0_CTRL_LANE0_MASK_LSB -// Description : The least-significant bit allowed to pass by the mask -// (inclusive) -#define SIO_INTERP0_CTRL_LANE0_MASK_LSB_RESET _u(0x00) -#define SIO_INTERP0_CTRL_LANE0_MASK_LSB_BITS _u(0x000003e0) -#define SIO_INTERP0_CTRL_LANE0_MASK_LSB_MSB _u(9) -#define SIO_INTERP0_CTRL_LANE0_MASK_LSB_LSB _u(5) -#define SIO_INTERP0_CTRL_LANE0_MASK_LSB_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SIO_INTERP0_CTRL_LANE0_SHIFT -// Description : Right-rotate applied to accumulator before masking. By -// appropriately configuring the masks, left and right shifts can -// be synthesised. -#define SIO_INTERP0_CTRL_LANE0_SHIFT_RESET _u(0x00) -#define SIO_INTERP0_CTRL_LANE0_SHIFT_BITS _u(0x0000001f) -#define SIO_INTERP0_CTRL_LANE0_SHIFT_MSB _u(4) -#define SIO_INTERP0_CTRL_LANE0_SHIFT_LSB _u(0) -#define SIO_INTERP0_CTRL_LANE0_SHIFT_ACCESS "RW" -// ============================================================================= -// Register : SIO_INTERP0_CTRL_LANE1 -// Description : Control register for lane 1 -#define SIO_INTERP0_CTRL_LANE1_OFFSET _u(0x000000b0) -#define SIO_INTERP0_CTRL_LANE1_BITS _u(0x001fffff) -#define SIO_INTERP0_CTRL_LANE1_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : SIO_INTERP0_CTRL_LANE1_FORCE_MSB -// Description : ORed into bits 29:28 of the lane result presented to the -// processor on the bus. -// No effect on the internal 32-bit datapath. Handy for using a -// lane to generate sequence -// of pointers into flash or SRAM. -#define SIO_INTERP0_CTRL_LANE1_FORCE_MSB_RESET _u(0x0) -#define SIO_INTERP0_CTRL_LANE1_FORCE_MSB_BITS _u(0x00180000) -#define SIO_INTERP0_CTRL_LANE1_FORCE_MSB_MSB _u(20) -#define SIO_INTERP0_CTRL_LANE1_FORCE_MSB_LSB _u(19) -#define SIO_INTERP0_CTRL_LANE1_FORCE_MSB_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SIO_INTERP0_CTRL_LANE1_ADD_RAW -// Description : If 1, mask + shift is bypassed for LANE1 result. This does not -// affect FULL result. -#define SIO_INTERP0_CTRL_LANE1_ADD_RAW_RESET _u(0x0) -#define SIO_INTERP0_CTRL_LANE1_ADD_RAW_BITS _u(0x00040000) -#define SIO_INTERP0_CTRL_LANE1_ADD_RAW_MSB _u(18) -#define SIO_INTERP0_CTRL_LANE1_ADD_RAW_LSB _u(18) -#define SIO_INTERP0_CTRL_LANE1_ADD_RAW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SIO_INTERP0_CTRL_LANE1_CROSS_RESULT -// Description : If 1, feed the opposite lane's result into this lane's -// accumulator on POP. -#define SIO_INTERP0_CTRL_LANE1_CROSS_RESULT_RESET _u(0x0) -#define SIO_INTERP0_CTRL_LANE1_CROSS_RESULT_BITS _u(0x00020000) -#define SIO_INTERP0_CTRL_LANE1_CROSS_RESULT_MSB _u(17) -#define SIO_INTERP0_CTRL_LANE1_CROSS_RESULT_LSB _u(17) -#define SIO_INTERP0_CTRL_LANE1_CROSS_RESULT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SIO_INTERP0_CTRL_LANE1_CROSS_INPUT -// Description : If 1, feed the opposite lane's accumulator into this lane's -// shift + mask hardware. -// Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is -// before the shift+mask bypass) -#define SIO_INTERP0_CTRL_LANE1_CROSS_INPUT_RESET _u(0x0) -#define SIO_INTERP0_CTRL_LANE1_CROSS_INPUT_BITS _u(0x00010000) -#define SIO_INTERP0_CTRL_LANE1_CROSS_INPUT_MSB _u(16) -#define SIO_INTERP0_CTRL_LANE1_CROSS_INPUT_LSB _u(16) -#define SIO_INTERP0_CTRL_LANE1_CROSS_INPUT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SIO_INTERP0_CTRL_LANE1_SIGNED -// Description : If SIGNED is set, the shifted and masked accumulator value is -// sign-extended to 32 bits -// before adding to BASE1, and LANE1 PEEK/POP appear extended to -// 32 bits when read by processor. -#define SIO_INTERP0_CTRL_LANE1_SIGNED_RESET _u(0x0) -#define SIO_INTERP0_CTRL_LANE1_SIGNED_BITS _u(0x00008000) -#define SIO_INTERP0_CTRL_LANE1_SIGNED_MSB _u(15) -#define SIO_INTERP0_CTRL_LANE1_SIGNED_LSB _u(15) -#define SIO_INTERP0_CTRL_LANE1_SIGNED_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SIO_INTERP0_CTRL_LANE1_MASK_MSB -// Description : The most-significant bit allowed to pass by the mask -// (inclusive) -// Setting MSB < LSB may cause chip to turn inside-out -#define SIO_INTERP0_CTRL_LANE1_MASK_MSB_RESET _u(0x00) -#define SIO_INTERP0_CTRL_LANE1_MASK_MSB_BITS _u(0x00007c00) -#define SIO_INTERP0_CTRL_LANE1_MASK_MSB_MSB _u(14) -#define SIO_INTERP0_CTRL_LANE1_MASK_MSB_LSB _u(10) -#define SIO_INTERP0_CTRL_LANE1_MASK_MSB_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SIO_INTERP0_CTRL_LANE1_MASK_LSB -// Description : The least-significant bit allowed to pass by the mask -// (inclusive) -#define SIO_INTERP0_CTRL_LANE1_MASK_LSB_RESET _u(0x00) -#define SIO_INTERP0_CTRL_LANE1_MASK_LSB_BITS _u(0x000003e0) -#define SIO_INTERP0_CTRL_LANE1_MASK_LSB_MSB _u(9) -#define SIO_INTERP0_CTRL_LANE1_MASK_LSB_LSB _u(5) -#define SIO_INTERP0_CTRL_LANE1_MASK_LSB_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SIO_INTERP0_CTRL_LANE1_SHIFT -// Description : Right-rotate applied to accumulator before masking. By -// appropriately configuring the masks, left and right shifts can -// be synthesised. -#define SIO_INTERP0_CTRL_LANE1_SHIFT_RESET _u(0x00) -#define SIO_INTERP0_CTRL_LANE1_SHIFT_BITS _u(0x0000001f) -#define SIO_INTERP0_CTRL_LANE1_SHIFT_MSB _u(4) -#define SIO_INTERP0_CTRL_LANE1_SHIFT_LSB _u(0) -#define SIO_INTERP0_CTRL_LANE1_SHIFT_ACCESS "RW" -// ============================================================================= -// Register : SIO_INTERP0_ACCUM0_ADD -// Description : Values written here are atomically added to ACCUM0 -// Reading yields lane 0's raw shift and mask value (BASE0 not -// added). -#define SIO_INTERP0_ACCUM0_ADD_OFFSET _u(0x000000b4) -#define SIO_INTERP0_ACCUM0_ADD_BITS _u(0x00ffffff) -#define SIO_INTERP0_ACCUM0_ADD_RESET _u(0x00000000) -#define SIO_INTERP0_ACCUM0_ADD_MSB _u(23) -#define SIO_INTERP0_ACCUM0_ADD_LSB _u(0) -#define SIO_INTERP0_ACCUM0_ADD_ACCESS "RW" -// ============================================================================= -// Register : SIO_INTERP0_ACCUM1_ADD -// Description : Values written here are atomically added to ACCUM1 -// Reading yields lane 1's raw shift and mask value (BASE1 not -// added). -#define SIO_INTERP0_ACCUM1_ADD_OFFSET _u(0x000000b8) -#define SIO_INTERP0_ACCUM1_ADD_BITS _u(0x00ffffff) -#define SIO_INTERP0_ACCUM1_ADD_RESET _u(0x00000000) -#define SIO_INTERP0_ACCUM1_ADD_MSB _u(23) -#define SIO_INTERP0_ACCUM1_ADD_LSB _u(0) -#define SIO_INTERP0_ACCUM1_ADD_ACCESS "RW" -// ============================================================================= -// Register : SIO_INTERP0_BASE_1AND0 -// Description : On write, the lower 16 bits go to BASE0, upper bits to BASE1 -// simultaneously. -// Each half is sign-extended to 32 bits if that lane's SIGNED -// flag is set. -#define SIO_INTERP0_BASE_1AND0_OFFSET _u(0x000000bc) -#define SIO_INTERP0_BASE_1AND0_BITS _u(0xffffffff) -#define SIO_INTERP0_BASE_1AND0_RESET _u(0x00000000) -#define SIO_INTERP0_BASE_1AND0_MSB _u(31) -#define SIO_INTERP0_BASE_1AND0_LSB _u(0) -#define SIO_INTERP0_BASE_1AND0_ACCESS "WO" -// ============================================================================= -// Register : SIO_INTERP1_ACCUM0 -// Description : Read/write access to accumulator 0 -#define SIO_INTERP1_ACCUM0_OFFSET _u(0x000000c0) -#define SIO_INTERP1_ACCUM0_BITS _u(0xffffffff) -#define SIO_INTERP1_ACCUM0_RESET _u(0x00000000) -#define SIO_INTERP1_ACCUM0_MSB _u(31) -#define SIO_INTERP1_ACCUM0_LSB _u(0) -#define SIO_INTERP1_ACCUM0_ACCESS "RW" -// ============================================================================= -// Register : SIO_INTERP1_ACCUM1 -// Description : Read/write access to accumulator 1 -#define SIO_INTERP1_ACCUM1_OFFSET _u(0x000000c4) -#define SIO_INTERP1_ACCUM1_BITS _u(0xffffffff) -#define SIO_INTERP1_ACCUM1_RESET _u(0x00000000) -#define SIO_INTERP1_ACCUM1_MSB _u(31) -#define SIO_INTERP1_ACCUM1_LSB _u(0) -#define SIO_INTERP1_ACCUM1_ACCESS "RW" -// ============================================================================= -// Register : SIO_INTERP1_BASE0 -// Description : Read/write access to BASE0 register. -#define SIO_INTERP1_BASE0_OFFSET _u(0x000000c8) -#define SIO_INTERP1_BASE0_BITS _u(0xffffffff) -#define SIO_INTERP1_BASE0_RESET _u(0x00000000) -#define SIO_INTERP1_BASE0_MSB _u(31) -#define SIO_INTERP1_BASE0_LSB _u(0) -#define SIO_INTERP1_BASE0_ACCESS "RW" -// ============================================================================= -// Register : SIO_INTERP1_BASE1 -// Description : Read/write access to BASE1 register. -#define SIO_INTERP1_BASE1_OFFSET _u(0x000000cc) -#define SIO_INTERP1_BASE1_BITS _u(0xffffffff) -#define SIO_INTERP1_BASE1_RESET _u(0x00000000) -#define SIO_INTERP1_BASE1_MSB _u(31) -#define SIO_INTERP1_BASE1_LSB _u(0) -#define SIO_INTERP1_BASE1_ACCESS "RW" -// ============================================================================= -// Register : SIO_INTERP1_BASE2 -// Description : Read/write access to BASE2 register. -#define SIO_INTERP1_BASE2_OFFSET _u(0x000000d0) -#define SIO_INTERP1_BASE2_BITS _u(0xffffffff) -#define SIO_INTERP1_BASE2_RESET _u(0x00000000) -#define SIO_INTERP1_BASE2_MSB _u(31) -#define SIO_INTERP1_BASE2_LSB _u(0) -#define SIO_INTERP1_BASE2_ACCESS "RW" -// ============================================================================= -// Register : SIO_INTERP1_POP_LANE0 -// Description : Read LANE0 result, and simultaneously write lane results to -// both accumulators (POP). -#define SIO_INTERP1_POP_LANE0_OFFSET _u(0x000000d4) -#define SIO_INTERP1_POP_LANE0_BITS _u(0xffffffff) -#define SIO_INTERP1_POP_LANE0_RESET _u(0x00000000) -#define SIO_INTERP1_POP_LANE0_MSB _u(31) -#define SIO_INTERP1_POP_LANE0_LSB _u(0) -#define SIO_INTERP1_POP_LANE0_ACCESS "RO" -// ============================================================================= -// Register : SIO_INTERP1_POP_LANE1 -// Description : Read LANE1 result, and simultaneously write lane results to -// both accumulators (POP). -#define SIO_INTERP1_POP_LANE1_OFFSET _u(0x000000d8) -#define SIO_INTERP1_POP_LANE1_BITS _u(0xffffffff) -#define SIO_INTERP1_POP_LANE1_RESET _u(0x00000000) -#define SIO_INTERP1_POP_LANE1_MSB _u(31) -#define SIO_INTERP1_POP_LANE1_LSB _u(0) -#define SIO_INTERP1_POP_LANE1_ACCESS "RO" -// ============================================================================= -// Register : SIO_INTERP1_POP_FULL -// Description : Read FULL result, and simultaneously write lane results to both -// accumulators (POP). -#define SIO_INTERP1_POP_FULL_OFFSET _u(0x000000dc) -#define SIO_INTERP1_POP_FULL_BITS _u(0xffffffff) -#define SIO_INTERP1_POP_FULL_RESET _u(0x00000000) -#define SIO_INTERP1_POP_FULL_MSB _u(31) -#define SIO_INTERP1_POP_FULL_LSB _u(0) -#define SIO_INTERP1_POP_FULL_ACCESS "RO" -// ============================================================================= -// Register : SIO_INTERP1_PEEK_LANE0 -// Description : Read LANE0 result, without altering any internal state (PEEK). -#define SIO_INTERP1_PEEK_LANE0_OFFSET _u(0x000000e0) -#define SIO_INTERP1_PEEK_LANE0_BITS _u(0xffffffff) -#define SIO_INTERP1_PEEK_LANE0_RESET _u(0x00000000) -#define SIO_INTERP1_PEEK_LANE0_MSB _u(31) -#define SIO_INTERP1_PEEK_LANE0_LSB _u(0) -#define SIO_INTERP1_PEEK_LANE0_ACCESS "RO" -// ============================================================================= -// Register : SIO_INTERP1_PEEK_LANE1 -// Description : Read LANE1 result, without altering any internal state (PEEK). -#define SIO_INTERP1_PEEK_LANE1_OFFSET _u(0x000000e4) -#define SIO_INTERP1_PEEK_LANE1_BITS _u(0xffffffff) -#define SIO_INTERP1_PEEK_LANE1_RESET _u(0x00000000) -#define SIO_INTERP1_PEEK_LANE1_MSB _u(31) -#define SIO_INTERP1_PEEK_LANE1_LSB _u(0) -#define SIO_INTERP1_PEEK_LANE1_ACCESS "RO" -// ============================================================================= -// Register : SIO_INTERP1_PEEK_FULL -// Description : Read FULL result, without altering any internal state (PEEK). -#define SIO_INTERP1_PEEK_FULL_OFFSET _u(0x000000e8) -#define SIO_INTERP1_PEEK_FULL_BITS _u(0xffffffff) -#define SIO_INTERP1_PEEK_FULL_RESET _u(0x00000000) -#define SIO_INTERP1_PEEK_FULL_MSB _u(31) -#define SIO_INTERP1_PEEK_FULL_LSB _u(0) -#define SIO_INTERP1_PEEK_FULL_ACCESS "RO" -// ============================================================================= -// Register : SIO_INTERP1_CTRL_LANE0 -// Description : Control register for lane 0 -#define SIO_INTERP1_CTRL_LANE0_OFFSET _u(0x000000ec) -#define SIO_INTERP1_CTRL_LANE0_BITS _u(0x03dfffff) -#define SIO_INTERP1_CTRL_LANE0_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : SIO_INTERP1_CTRL_LANE0_OVERF -// Description : Set if either OVERF0 or OVERF1 is set. -#define SIO_INTERP1_CTRL_LANE0_OVERF_RESET _u(0x0) -#define SIO_INTERP1_CTRL_LANE0_OVERF_BITS _u(0x02000000) -#define SIO_INTERP1_CTRL_LANE0_OVERF_MSB _u(25) -#define SIO_INTERP1_CTRL_LANE0_OVERF_LSB _u(25) -#define SIO_INTERP1_CTRL_LANE0_OVERF_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : SIO_INTERP1_CTRL_LANE0_OVERF1 -// Description : Indicates if any masked-off MSBs in ACCUM1 are set. -#define SIO_INTERP1_CTRL_LANE0_OVERF1_RESET _u(0x0) -#define SIO_INTERP1_CTRL_LANE0_OVERF1_BITS _u(0x01000000) -#define SIO_INTERP1_CTRL_LANE0_OVERF1_MSB _u(24) -#define SIO_INTERP1_CTRL_LANE0_OVERF1_LSB _u(24) -#define SIO_INTERP1_CTRL_LANE0_OVERF1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : SIO_INTERP1_CTRL_LANE0_OVERF0 -// Description : Indicates if any masked-off MSBs in ACCUM0 are set. -#define SIO_INTERP1_CTRL_LANE0_OVERF0_RESET _u(0x0) -#define SIO_INTERP1_CTRL_LANE0_OVERF0_BITS _u(0x00800000) -#define SIO_INTERP1_CTRL_LANE0_OVERF0_MSB _u(23) -#define SIO_INTERP1_CTRL_LANE0_OVERF0_LSB _u(23) -#define SIO_INTERP1_CTRL_LANE0_OVERF0_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : SIO_INTERP1_CTRL_LANE0_CLAMP -// Description : Only present on INTERP1 on each core. If CLAMP mode is enabled: -// - LANE0 result is shifted and masked ACCUM0, clamped by a lower -// bound of -// BASE0 and an upper bound of BASE1. -// - Signedness of these comparisons is determined by -// LANE0_CTRL_SIGNED -#define SIO_INTERP1_CTRL_LANE0_CLAMP_RESET _u(0x0) -#define SIO_INTERP1_CTRL_LANE0_CLAMP_BITS _u(0x00400000) -#define SIO_INTERP1_CTRL_LANE0_CLAMP_MSB _u(22) -#define SIO_INTERP1_CTRL_LANE0_CLAMP_LSB _u(22) -#define SIO_INTERP1_CTRL_LANE0_CLAMP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SIO_INTERP1_CTRL_LANE0_FORCE_MSB -// Description : ORed into bits 29:28 of the lane result presented to the -// processor on the bus. -// No effect on the internal 32-bit datapath. Handy for using a -// lane to generate sequence -// of pointers into flash or SRAM. -#define SIO_INTERP1_CTRL_LANE0_FORCE_MSB_RESET _u(0x0) -#define SIO_INTERP1_CTRL_LANE0_FORCE_MSB_BITS _u(0x00180000) -#define SIO_INTERP1_CTRL_LANE0_FORCE_MSB_MSB _u(20) -#define SIO_INTERP1_CTRL_LANE0_FORCE_MSB_LSB _u(19) -#define SIO_INTERP1_CTRL_LANE0_FORCE_MSB_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SIO_INTERP1_CTRL_LANE0_ADD_RAW -// Description : If 1, mask + shift is bypassed for LANE0 result. This does not -// affect FULL result. -#define SIO_INTERP1_CTRL_LANE0_ADD_RAW_RESET _u(0x0) -#define SIO_INTERP1_CTRL_LANE0_ADD_RAW_BITS _u(0x00040000) -#define SIO_INTERP1_CTRL_LANE0_ADD_RAW_MSB _u(18) -#define SIO_INTERP1_CTRL_LANE0_ADD_RAW_LSB _u(18) -#define SIO_INTERP1_CTRL_LANE0_ADD_RAW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SIO_INTERP1_CTRL_LANE0_CROSS_RESULT -// Description : If 1, feed the opposite lane's result into this lane's -// accumulator on POP. -#define SIO_INTERP1_CTRL_LANE0_CROSS_RESULT_RESET _u(0x0) -#define SIO_INTERP1_CTRL_LANE0_CROSS_RESULT_BITS _u(0x00020000) -#define SIO_INTERP1_CTRL_LANE0_CROSS_RESULT_MSB _u(17) -#define SIO_INTERP1_CTRL_LANE0_CROSS_RESULT_LSB _u(17) -#define SIO_INTERP1_CTRL_LANE0_CROSS_RESULT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SIO_INTERP1_CTRL_LANE0_CROSS_INPUT -// Description : If 1, feed the opposite lane's accumulator into this lane's -// shift + mask hardware. -// Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is -// before the shift+mask bypass) -#define SIO_INTERP1_CTRL_LANE0_CROSS_INPUT_RESET _u(0x0) -#define SIO_INTERP1_CTRL_LANE0_CROSS_INPUT_BITS _u(0x00010000) -#define SIO_INTERP1_CTRL_LANE0_CROSS_INPUT_MSB _u(16) -#define SIO_INTERP1_CTRL_LANE0_CROSS_INPUT_LSB _u(16) -#define SIO_INTERP1_CTRL_LANE0_CROSS_INPUT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SIO_INTERP1_CTRL_LANE0_SIGNED -// Description : If SIGNED is set, the shifted and masked accumulator value is -// sign-extended to 32 bits -// before adding to BASE0, and LANE0 PEEK/POP appear extended to -// 32 bits when read by processor. -#define SIO_INTERP1_CTRL_LANE0_SIGNED_RESET _u(0x0) -#define SIO_INTERP1_CTRL_LANE0_SIGNED_BITS _u(0x00008000) -#define SIO_INTERP1_CTRL_LANE0_SIGNED_MSB _u(15) -#define SIO_INTERP1_CTRL_LANE0_SIGNED_LSB _u(15) -#define SIO_INTERP1_CTRL_LANE0_SIGNED_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SIO_INTERP1_CTRL_LANE0_MASK_MSB -// Description : The most-significant bit allowed to pass by the mask -// (inclusive) -// Setting MSB < LSB may cause chip to turn inside-out -#define SIO_INTERP1_CTRL_LANE0_MASK_MSB_RESET _u(0x00) -#define SIO_INTERP1_CTRL_LANE0_MASK_MSB_BITS _u(0x00007c00) -#define SIO_INTERP1_CTRL_LANE0_MASK_MSB_MSB _u(14) -#define SIO_INTERP1_CTRL_LANE0_MASK_MSB_LSB _u(10) -#define SIO_INTERP1_CTRL_LANE0_MASK_MSB_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SIO_INTERP1_CTRL_LANE0_MASK_LSB -// Description : The least-significant bit allowed to pass by the mask -// (inclusive) -#define SIO_INTERP1_CTRL_LANE0_MASK_LSB_RESET _u(0x00) -#define SIO_INTERP1_CTRL_LANE0_MASK_LSB_BITS _u(0x000003e0) -#define SIO_INTERP1_CTRL_LANE0_MASK_LSB_MSB _u(9) -#define SIO_INTERP1_CTRL_LANE0_MASK_LSB_LSB _u(5) -#define SIO_INTERP1_CTRL_LANE0_MASK_LSB_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SIO_INTERP1_CTRL_LANE0_SHIFT -// Description : Right-rotate applied to accumulator before masking. By -// appropriately configuring the masks, left and right shifts can -// be synthesised. -#define SIO_INTERP1_CTRL_LANE0_SHIFT_RESET _u(0x00) -#define SIO_INTERP1_CTRL_LANE0_SHIFT_BITS _u(0x0000001f) -#define SIO_INTERP1_CTRL_LANE0_SHIFT_MSB _u(4) -#define SIO_INTERP1_CTRL_LANE0_SHIFT_LSB _u(0) -#define SIO_INTERP1_CTRL_LANE0_SHIFT_ACCESS "RW" -// ============================================================================= -// Register : SIO_INTERP1_CTRL_LANE1 -// Description : Control register for lane 1 -#define SIO_INTERP1_CTRL_LANE1_OFFSET _u(0x000000f0) -#define SIO_INTERP1_CTRL_LANE1_BITS _u(0x001fffff) -#define SIO_INTERP1_CTRL_LANE1_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : SIO_INTERP1_CTRL_LANE1_FORCE_MSB -// Description : ORed into bits 29:28 of the lane result presented to the -// processor on the bus. -// No effect on the internal 32-bit datapath. Handy for using a -// lane to generate sequence -// of pointers into flash or SRAM. -#define SIO_INTERP1_CTRL_LANE1_FORCE_MSB_RESET _u(0x0) -#define SIO_INTERP1_CTRL_LANE1_FORCE_MSB_BITS _u(0x00180000) -#define SIO_INTERP1_CTRL_LANE1_FORCE_MSB_MSB _u(20) -#define SIO_INTERP1_CTRL_LANE1_FORCE_MSB_LSB _u(19) -#define SIO_INTERP1_CTRL_LANE1_FORCE_MSB_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SIO_INTERP1_CTRL_LANE1_ADD_RAW -// Description : If 1, mask + shift is bypassed for LANE1 result. This does not -// affect FULL result. -#define SIO_INTERP1_CTRL_LANE1_ADD_RAW_RESET _u(0x0) -#define SIO_INTERP1_CTRL_LANE1_ADD_RAW_BITS _u(0x00040000) -#define SIO_INTERP1_CTRL_LANE1_ADD_RAW_MSB _u(18) -#define SIO_INTERP1_CTRL_LANE1_ADD_RAW_LSB _u(18) -#define SIO_INTERP1_CTRL_LANE1_ADD_RAW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SIO_INTERP1_CTRL_LANE1_CROSS_RESULT -// Description : If 1, feed the opposite lane's result into this lane's -// accumulator on POP. -#define SIO_INTERP1_CTRL_LANE1_CROSS_RESULT_RESET _u(0x0) -#define SIO_INTERP1_CTRL_LANE1_CROSS_RESULT_BITS _u(0x00020000) -#define SIO_INTERP1_CTRL_LANE1_CROSS_RESULT_MSB _u(17) -#define SIO_INTERP1_CTRL_LANE1_CROSS_RESULT_LSB _u(17) -#define SIO_INTERP1_CTRL_LANE1_CROSS_RESULT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SIO_INTERP1_CTRL_LANE1_CROSS_INPUT -// Description : If 1, feed the opposite lane's accumulator into this lane's -// shift + mask hardware. -// Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is -// before the shift+mask bypass) -#define SIO_INTERP1_CTRL_LANE1_CROSS_INPUT_RESET _u(0x0) -#define SIO_INTERP1_CTRL_LANE1_CROSS_INPUT_BITS _u(0x00010000) -#define SIO_INTERP1_CTRL_LANE1_CROSS_INPUT_MSB _u(16) -#define SIO_INTERP1_CTRL_LANE1_CROSS_INPUT_LSB _u(16) -#define SIO_INTERP1_CTRL_LANE1_CROSS_INPUT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SIO_INTERP1_CTRL_LANE1_SIGNED -// Description : If SIGNED is set, the shifted and masked accumulator value is -// sign-extended to 32 bits -// before adding to BASE1, and LANE1 PEEK/POP appear extended to -// 32 bits when read by processor. -#define SIO_INTERP1_CTRL_LANE1_SIGNED_RESET _u(0x0) -#define SIO_INTERP1_CTRL_LANE1_SIGNED_BITS _u(0x00008000) -#define SIO_INTERP1_CTRL_LANE1_SIGNED_MSB _u(15) -#define SIO_INTERP1_CTRL_LANE1_SIGNED_LSB _u(15) -#define SIO_INTERP1_CTRL_LANE1_SIGNED_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SIO_INTERP1_CTRL_LANE1_MASK_MSB -// Description : The most-significant bit allowed to pass by the mask -// (inclusive) -// Setting MSB < LSB may cause chip to turn inside-out -#define SIO_INTERP1_CTRL_LANE1_MASK_MSB_RESET _u(0x00) -#define SIO_INTERP1_CTRL_LANE1_MASK_MSB_BITS _u(0x00007c00) -#define SIO_INTERP1_CTRL_LANE1_MASK_MSB_MSB _u(14) -#define SIO_INTERP1_CTRL_LANE1_MASK_MSB_LSB _u(10) -#define SIO_INTERP1_CTRL_LANE1_MASK_MSB_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SIO_INTERP1_CTRL_LANE1_MASK_LSB -// Description : The least-significant bit allowed to pass by the mask -// (inclusive) -#define SIO_INTERP1_CTRL_LANE1_MASK_LSB_RESET _u(0x00) -#define SIO_INTERP1_CTRL_LANE1_MASK_LSB_BITS _u(0x000003e0) -#define SIO_INTERP1_CTRL_LANE1_MASK_LSB_MSB _u(9) -#define SIO_INTERP1_CTRL_LANE1_MASK_LSB_LSB _u(5) -#define SIO_INTERP1_CTRL_LANE1_MASK_LSB_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SIO_INTERP1_CTRL_LANE1_SHIFT -// Description : Right-rotate applied to accumulator before masking. By -// appropriately configuring the masks, left and right shifts can -// be synthesised. -#define SIO_INTERP1_CTRL_LANE1_SHIFT_RESET _u(0x00) -#define SIO_INTERP1_CTRL_LANE1_SHIFT_BITS _u(0x0000001f) -#define SIO_INTERP1_CTRL_LANE1_SHIFT_MSB _u(4) -#define SIO_INTERP1_CTRL_LANE1_SHIFT_LSB _u(0) -#define SIO_INTERP1_CTRL_LANE1_SHIFT_ACCESS "RW" -// ============================================================================= -// Register : SIO_INTERP1_ACCUM0_ADD -// Description : Values written here are atomically added to ACCUM0 -// Reading yields lane 0's raw shift and mask value (BASE0 not -// added). -#define SIO_INTERP1_ACCUM0_ADD_OFFSET _u(0x000000f4) -#define SIO_INTERP1_ACCUM0_ADD_BITS _u(0x00ffffff) -#define SIO_INTERP1_ACCUM0_ADD_RESET _u(0x00000000) -#define SIO_INTERP1_ACCUM0_ADD_MSB _u(23) -#define SIO_INTERP1_ACCUM0_ADD_LSB _u(0) -#define SIO_INTERP1_ACCUM0_ADD_ACCESS "RW" -// ============================================================================= -// Register : SIO_INTERP1_ACCUM1_ADD -// Description : Values written here are atomically added to ACCUM1 -// Reading yields lane 1's raw shift and mask value (BASE1 not -// added). -#define SIO_INTERP1_ACCUM1_ADD_OFFSET _u(0x000000f8) -#define SIO_INTERP1_ACCUM1_ADD_BITS _u(0x00ffffff) -#define SIO_INTERP1_ACCUM1_ADD_RESET _u(0x00000000) -#define SIO_INTERP1_ACCUM1_ADD_MSB _u(23) -#define SIO_INTERP1_ACCUM1_ADD_LSB _u(0) -#define SIO_INTERP1_ACCUM1_ADD_ACCESS "RW" -// ============================================================================= -// Register : SIO_INTERP1_BASE_1AND0 -// Description : On write, the lower 16 bits go to BASE0, upper bits to BASE1 -// simultaneously. -// Each half is sign-extended to 32 bits if that lane's SIGNED -// flag is set. -#define SIO_INTERP1_BASE_1AND0_OFFSET _u(0x000000fc) -#define SIO_INTERP1_BASE_1AND0_BITS _u(0xffffffff) -#define SIO_INTERP1_BASE_1AND0_RESET _u(0x00000000) -#define SIO_INTERP1_BASE_1AND0_MSB _u(31) -#define SIO_INTERP1_BASE_1AND0_LSB _u(0) -#define SIO_INTERP1_BASE_1AND0_ACCESS "WO" -// ============================================================================= -// Register : SIO_SPINLOCK0 -// Description : Reading from a spinlock address will: -// - Return 0 if lock is already locked -// - Otherwise return nonzero, and simultaneously claim the lock -// -// Writing (any value) releases the lock. -// If core 0 and core 1 attempt to claim the same lock -// simultaneously, core 0 wins. -// The value returned on success is 0x1 << lock number. -#define SIO_SPINLOCK0_OFFSET _u(0x00000100) -#define SIO_SPINLOCK0_BITS _u(0xffffffff) -#define SIO_SPINLOCK0_RESET _u(0x00000000) -#define SIO_SPINLOCK0_MSB _u(31) -#define SIO_SPINLOCK0_LSB _u(0) -#define SIO_SPINLOCK0_ACCESS "RW" -// ============================================================================= -// Register : SIO_SPINLOCK1 -// Description : Reading from a spinlock address will: -// - Return 0 if lock is already locked -// - Otherwise return nonzero, and simultaneously claim the lock -// -// Writing (any value) releases the lock. -// If core 0 and core 1 attempt to claim the same lock -// simultaneously, core 0 wins. -// The value returned on success is 0x1 << lock number. -#define SIO_SPINLOCK1_OFFSET _u(0x00000104) -#define SIO_SPINLOCK1_BITS _u(0xffffffff) -#define SIO_SPINLOCK1_RESET _u(0x00000000) -#define SIO_SPINLOCK1_MSB _u(31) -#define SIO_SPINLOCK1_LSB _u(0) -#define SIO_SPINLOCK1_ACCESS "RW" -// ============================================================================= -// Register : SIO_SPINLOCK2 -// Description : Reading from a spinlock address will: -// - Return 0 if lock is already locked -// - Otherwise return nonzero, and simultaneously claim the lock -// -// Writing (any value) releases the lock. -// If core 0 and core 1 attempt to claim the same lock -// simultaneously, core 0 wins. -// The value returned on success is 0x1 << lock number. -#define SIO_SPINLOCK2_OFFSET _u(0x00000108) -#define SIO_SPINLOCK2_BITS _u(0xffffffff) -#define SIO_SPINLOCK2_RESET _u(0x00000000) -#define SIO_SPINLOCK2_MSB _u(31) -#define SIO_SPINLOCK2_LSB _u(0) -#define SIO_SPINLOCK2_ACCESS "RW" -// ============================================================================= -// Register : SIO_SPINLOCK3 -// Description : Reading from a spinlock address will: -// - Return 0 if lock is already locked -// - Otherwise return nonzero, and simultaneously claim the lock -// -// Writing (any value) releases the lock. -// If core 0 and core 1 attempt to claim the same lock -// simultaneously, core 0 wins. -// The value returned on success is 0x1 << lock number. -#define SIO_SPINLOCK3_OFFSET _u(0x0000010c) -#define SIO_SPINLOCK3_BITS _u(0xffffffff) -#define SIO_SPINLOCK3_RESET _u(0x00000000) -#define SIO_SPINLOCK3_MSB _u(31) -#define SIO_SPINLOCK3_LSB _u(0) -#define SIO_SPINLOCK3_ACCESS "RW" -// ============================================================================= -// Register : SIO_SPINLOCK4 -// Description : Reading from a spinlock address will: -// - Return 0 if lock is already locked -// - Otherwise return nonzero, and simultaneously claim the lock -// -// Writing (any value) releases the lock. -// If core 0 and core 1 attempt to claim the same lock -// simultaneously, core 0 wins. -// The value returned on success is 0x1 << lock number. -#define SIO_SPINLOCK4_OFFSET _u(0x00000110) -#define SIO_SPINLOCK4_BITS _u(0xffffffff) -#define SIO_SPINLOCK4_RESET _u(0x00000000) -#define SIO_SPINLOCK4_MSB _u(31) -#define SIO_SPINLOCK4_LSB _u(0) -#define SIO_SPINLOCK4_ACCESS "RW" -// ============================================================================= -// Register : SIO_SPINLOCK5 -// Description : Reading from a spinlock address will: -// - Return 0 if lock is already locked -// - Otherwise return nonzero, and simultaneously claim the lock -// -// Writing (any value) releases the lock. -// If core 0 and core 1 attempt to claim the same lock -// simultaneously, core 0 wins. -// The value returned on success is 0x1 << lock number. -#define SIO_SPINLOCK5_OFFSET _u(0x00000114) -#define SIO_SPINLOCK5_BITS _u(0xffffffff) -#define SIO_SPINLOCK5_RESET _u(0x00000000) -#define SIO_SPINLOCK5_MSB _u(31) -#define SIO_SPINLOCK5_LSB _u(0) -#define SIO_SPINLOCK5_ACCESS "RW" -// ============================================================================= -// Register : SIO_SPINLOCK6 -// Description : Reading from a spinlock address will: -// - Return 0 if lock is already locked -// - Otherwise return nonzero, and simultaneously claim the lock -// -// Writing (any value) releases the lock. -// If core 0 and core 1 attempt to claim the same lock -// simultaneously, core 0 wins. -// The value returned on success is 0x1 << lock number. -#define SIO_SPINLOCK6_OFFSET _u(0x00000118) -#define SIO_SPINLOCK6_BITS _u(0xffffffff) -#define SIO_SPINLOCK6_RESET _u(0x00000000) -#define SIO_SPINLOCK6_MSB _u(31) -#define SIO_SPINLOCK6_LSB _u(0) -#define SIO_SPINLOCK6_ACCESS "RW" -// ============================================================================= -// Register : SIO_SPINLOCK7 -// Description : Reading from a spinlock address will: -// - Return 0 if lock is already locked -// - Otherwise return nonzero, and simultaneously claim the lock -// -// Writing (any value) releases the lock. -// If core 0 and core 1 attempt to claim the same lock -// simultaneously, core 0 wins. -// The value returned on success is 0x1 << lock number. -#define SIO_SPINLOCK7_OFFSET _u(0x0000011c) -#define SIO_SPINLOCK7_BITS _u(0xffffffff) -#define SIO_SPINLOCK7_RESET _u(0x00000000) -#define SIO_SPINLOCK7_MSB _u(31) -#define SIO_SPINLOCK7_LSB _u(0) -#define SIO_SPINLOCK7_ACCESS "RW" -// ============================================================================= -// Register : SIO_SPINLOCK8 -// Description : Reading from a spinlock address will: -// - Return 0 if lock is already locked -// - Otherwise return nonzero, and simultaneously claim the lock -// -// Writing (any value) releases the lock. -// If core 0 and core 1 attempt to claim the same lock -// simultaneously, core 0 wins. -// The value returned on success is 0x1 << lock number. -#define SIO_SPINLOCK8_OFFSET _u(0x00000120) -#define SIO_SPINLOCK8_BITS _u(0xffffffff) -#define SIO_SPINLOCK8_RESET _u(0x00000000) -#define SIO_SPINLOCK8_MSB _u(31) -#define SIO_SPINLOCK8_LSB _u(0) -#define SIO_SPINLOCK8_ACCESS "RW" -// ============================================================================= -// Register : SIO_SPINLOCK9 -// Description : Reading from a spinlock address will: -// - Return 0 if lock is already locked -// - Otherwise return nonzero, and simultaneously claim the lock -// -// Writing (any value) releases the lock. -// If core 0 and core 1 attempt to claim the same lock -// simultaneously, core 0 wins. -// The value returned on success is 0x1 << lock number. -#define SIO_SPINLOCK9_OFFSET _u(0x00000124) -#define SIO_SPINLOCK9_BITS _u(0xffffffff) -#define SIO_SPINLOCK9_RESET _u(0x00000000) -#define SIO_SPINLOCK9_MSB _u(31) -#define SIO_SPINLOCK9_LSB _u(0) -#define SIO_SPINLOCK9_ACCESS "RW" -// ============================================================================= -// Register : SIO_SPINLOCK10 -// Description : Reading from a spinlock address will: -// - Return 0 if lock is already locked -// - Otherwise return nonzero, and simultaneously claim the lock -// -// Writing (any value) releases the lock. -// If core 0 and core 1 attempt to claim the same lock -// simultaneously, core 0 wins. -// The value returned on success is 0x1 << lock number. -#define SIO_SPINLOCK10_OFFSET _u(0x00000128) -#define SIO_SPINLOCK10_BITS _u(0xffffffff) -#define SIO_SPINLOCK10_RESET _u(0x00000000) -#define SIO_SPINLOCK10_MSB _u(31) -#define SIO_SPINLOCK10_LSB _u(0) -#define SIO_SPINLOCK10_ACCESS "RW" -// ============================================================================= -// Register : SIO_SPINLOCK11 -// Description : Reading from a spinlock address will: -// - Return 0 if lock is already locked -// - Otherwise return nonzero, and simultaneously claim the lock -// -// Writing (any value) releases the lock. -// If core 0 and core 1 attempt to claim the same lock -// simultaneously, core 0 wins. -// The value returned on success is 0x1 << lock number. -#define SIO_SPINLOCK11_OFFSET _u(0x0000012c) -#define SIO_SPINLOCK11_BITS _u(0xffffffff) -#define SIO_SPINLOCK11_RESET _u(0x00000000) -#define SIO_SPINLOCK11_MSB _u(31) -#define SIO_SPINLOCK11_LSB _u(0) -#define SIO_SPINLOCK11_ACCESS "RW" -// ============================================================================= -// Register : SIO_SPINLOCK12 -// Description : Reading from a spinlock address will: -// - Return 0 if lock is already locked -// - Otherwise return nonzero, and simultaneously claim the lock -// -// Writing (any value) releases the lock. -// If core 0 and core 1 attempt to claim the same lock -// simultaneously, core 0 wins. -// The value returned on success is 0x1 << lock number. -#define SIO_SPINLOCK12_OFFSET _u(0x00000130) -#define SIO_SPINLOCK12_BITS _u(0xffffffff) -#define SIO_SPINLOCK12_RESET _u(0x00000000) -#define SIO_SPINLOCK12_MSB _u(31) -#define SIO_SPINLOCK12_LSB _u(0) -#define SIO_SPINLOCK12_ACCESS "RW" -// ============================================================================= -// Register : SIO_SPINLOCK13 -// Description : Reading from a spinlock address will: -// - Return 0 if lock is already locked -// - Otherwise return nonzero, and simultaneously claim the lock -// -// Writing (any value) releases the lock. -// If core 0 and core 1 attempt to claim the same lock -// simultaneously, core 0 wins. -// The value returned on success is 0x1 << lock number. -#define SIO_SPINLOCK13_OFFSET _u(0x00000134) -#define SIO_SPINLOCK13_BITS _u(0xffffffff) -#define SIO_SPINLOCK13_RESET _u(0x00000000) -#define SIO_SPINLOCK13_MSB _u(31) -#define SIO_SPINLOCK13_LSB _u(0) -#define SIO_SPINLOCK13_ACCESS "RW" -// ============================================================================= -// Register : SIO_SPINLOCK14 -// Description : Reading from a spinlock address will: -// - Return 0 if lock is already locked -// - Otherwise return nonzero, and simultaneously claim the lock -// -// Writing (any value) releases the lock. -// If core 0 and core 1 attempt to claim the same lock -// simultaneously, core 0 wins. -// The value returned on success is 0x1 << lock number. -#define SIO_SPINLOCK14_OFFSET _u(0x00000138) -#define SIO_SPINLOCK14_BITS _u(0xffffffff) -#define SIO_SPINLOCK14_RESET _u(0x00000000) -#define SIO_SPINLOCK14_MSB _u(31) -#define SIO_SPINLOCK14_LSB _u(0) -#define SIO_SPINLOCK14_ACCESS "RW" -// ============================================================================= -// Register : SIO_SPINLOCK15 -// Description : Reading from a spinlock address will: -// - Return 0 if lock is already locked -// - Otherwise return nonzero, and simultaneously claim the lock -// -// Writing (any value) releases the lock. -// If core 0 and core 1 attempt to claim the same lock -// simultaneously, core 0 wins. -// The value returned on success is 0x1 << lock number. -#define SIO_SPINLOCK15_OFFSET _u(0x0000013c) -#define SIO_SPINLOCK15_BITS _u(0xffffffff) -#define SIO_SPINLOCK15_RESET _u(0x00000000) -#define SIO_SPINLOCK15_MSB _u(31) -#define SIO_SPINLOCK15_LSB _u(0) -#define SIO_SPINLOCK15_ACCESS "RW" -// ============================================================================= -// Register : SIO_SPINLOCK16 -// Description : Reading from a spinlock address will: -// - Return 0 if lock is already locked -// - Otherwise return nonzero, and simultaneously claim the lock -// -// Writing (any value) releases the lock. -// If core 0 and core 1 attempt to claim the same lock -// simultaneously, core 0 wins. -// The value returned on success is 0x1 << lock number. -#define SIO_SPINLOCK16_OFFSET _u(0x00000140) -#define SIO_SPINLOCK16_BITS _u(0xffffffff) -#define SIO_SPINLOCK16_RESET _u(0x00000000) -#define SIO_SPINLOCK16_MSB _u(31) -#define SIO_SPINLOCK16_LSB _u(0) -#define SIO_SPINLOCK16_ACCESS "RW" -// ============================================================================= -// Register : SIO_SPINLOCK17 -// Description : Reading from a spinlock address will: -// - Return 0 if lock is already locked -// - Otherwise return nonzero, and simultaneously claim the lock -// -// Writing (any value) releases the lock. -// If core 0 and core 1 attempt to claim the same lock -// simultaneously, core 0 wins. -// The value returned on success is 0x1 << lock number. -#define SIO_SPINLOCK17_OFFSET _u(0x00000144) -#define SIO_SPINLOCK17_BITS _u(0xffffffff) -#define SIO_SPINLOCK17_RESET _u(0x00000000) -#define SIO_SPINLOCK17_MSB _u(31) -#define SIO_SPINLOCK17_LSB _u(0) -#define SIO_SPINLOCK17_ACCESS "RW" -// ============================================================================= -// Register : SIO_SPINLOCK18 -// Description : Reading from a spinlock address will: -// - Return 0 if lock is already locked -// - Otherwise return nonzero, and simultaneously claim the lock -// -// Writing (any value) releases the lock. -// If core 0 and core 1 attempt to claim the same lock -// simultaneously, core 0 wins. -// The value returned on success is 0x1 << lock number. -#define SIO_SPINLOCK18_OFFSET _u(0x00000148) -#define SIO_SPINLOCK18_BITS _u(0xffffffff) -#define SIO_SPINLOCK18_RESET _u(0x00000000) -#define SIO_SPINLOCK18_MSB _u(31) -#define SIO_SPINLOCK18_LSB _u(0) -#define SIO_SPINLOCK18_ACCESS "RW" -// ============================================================================= -// Register : SIO_SPINLOCK19 -// Description : Reading from a spinlock address will: -// - Return 0 if lock is already locked -// - Otherwise return nonzero, and simultaneously claim the lock -// -// Writing (any value) releases the lock. -// If core 0 and core 1 attempt to claim the same lock -// simultaneously, core 0 wins. -// The value returned on success is 0x1 << lock number. -#define SIO_SPINLOCK19_OFFSET _u(0x0000014c) -#define SIO_SPINLOCK19_BITS _u(0xffffffff) -#define SIO_SPINLOCK19_RESET _u(0x00000000) -#define SIO_SPINLOCK19_MSB _u(31) -#define SIO_SPINLOCK19_LSB _u(0) -#define SIO_SPINLOCK19_ACCESS "RW" -// ============================================================================= -// Register : SIO_SPINLOCK20 -// Description : Reading from a spinlock address will: -// - Return 0 if lock is already locked -// - Otherwise return nonzero, and simultaneously claim the lock -// -// Writing (any value) releases the lock. -// If core 0 and core 1 attempt to claim the same lock -// simultaneously, core 0 wins. -// The value returned on success is 0x1 << lock number. -#define SIO_SPINLOCK20_OFFSET _u(0x00000150) -#define SIO_SPINLOCK20_BITS _u(0xffffffff) -#define SIO_SPINLOCK20_RESET _u(0x00000000) -#define SIO_SPINLOCK20_MSB _u(31) -#define SIO_SPINLOCK20_LSB _u(0) -#define SIO_SPINLOCK20_ACCESS "RW" -// ============================================================================= -// Register : SIO_SPINLOCK21 -// Description : Reading from a spinlock address will: -// - Return 0 if lock is already locked -// - Otherwise return nonzero, and simultaneously claim the lock -// -// Writing (any value) releases the lock. -// If core 0 and core 1 attempt to claim the same lock -// simultaneously, core 0 wins. -// The value returned on success is 0x1 << lock number. -#define SIO_SPINLOCK21_OFFSET _u(0x00000154) -#define SIO_SPINLOCK21_BITS _u(0xffffffff) -#define SIO_SPINLOCK21_RESET _u(0x00000000) -#define SIO_SPINLOCK21_MSB _u(31) -#define SIO_SPINLOCK21_LSB _u(0) -#define SIO_SPINLOCK21_ACCESS "RW" -// ============================================================================= -// Register : SIO_SPINLOCK22 -// Description : Reading from a spinlock address will: -// - Return 0 if lock is already locked -// - Otherwise return nonzero, and simultaneously claim the lock -// -// Writing (any value) releases the lock. -// If core 0 and core 1 attempt to claim the same lock -// simultaneously, core 0 wins. -// The value returned on success is 0x1 << lock number. -#define SIO_SPINLOCK22_OFFSET _u(0x00000158) -#define SIO_SPINLOCK22_BITS _u(0xffffffff) -#define SIO_SPINLOCK22_RESET _u(0x00000000) -#define SIO_SPINLOCK22_MSB _u(31) -#define SIO_SPINLOCK22_LSB _u(0) -#define SIO_SPINLOCK22_ACCESS "RW" -// ============================================================================= -// Register : SIO_SPINLOCK23 -// Description : Reading from a spinlock address will: -// - Return 0 if lock is already locked -// - Otherwise return nonzero, and simultaneously claim the lock -// -// Writing (any value) releases the lock. -// If core 0 and core 1 attempt to claim the same lock -// simultaneously, core 0 wins. -// The value returned on success is 0x1 << lock number. -#define SIO_SPINLOCK23_OFFSET _u(0x0000015c) -#define SIO_SPINLOCK23_BITS _u(0xffffffff) -#define SIO_SPINLOCK23_RESET _u(0x00000000) -#define SIO_SPINLOCK23_MSB _u(31) -#define SIO_SPINLOCK23_LSB _u(0) -#define SIO_SPINLOCK23_ACCESS "RW" -// ============================================================================= -// Register : SIO_SPINLOCK24 -// Description : Reading from a spinlock address will: -// - Return 0 if lock is already locked -// - Otherwise return nonzero, and simultaneously claim the lock -// -// Writing (any value) releases the lock. -// If core 0 and core 1 attempt to claim the same lock -// simultaneously, core 0 wins. -// The value returned on success is 0x1 << lock number. -#define SIO_SPINLOCK24_OFFSET _u(0x00000160) -#define SIO_SPINLOCK24_BITS _u(0xffffffff) -#define SIO_SPINLOCK24_RESET _u(0x00000000) -#define SIO_SPINLOCK24_MSB _u(31) -#define SIO_SPINLOCK24_LSB _u(0) -#define SIO_SPINLOCK24_ACCESS "RW" -// ============================================================================= -// Register : SIO_SPINLOCK25 -// Description : Reading from a spinlock address will: -// - Return 0 if lock is already locked -// - Otherwise return nonzero, and simultaneously claim the lock -// -// Writing (any value) releases the lock. -// If core 0 and core 1 attempt to claim the same lock -// simultaneously, core 0 wins. -// The value returned on success is 0x1 << lock number. -#define SIO_SPINLOCK25_OFFSET _u(0x00000164) -#define SIO_SPINLOCK25_BITS _u(0xffffffff) -#define SIO_SPINLOCK25_RESET _u(0x00000000) -#define SIO_SPINLOCK25_MSB _u(31) -#define SIO_SPINLOCK25_LSB _u(0) -#define SIO_SPINLOCK25_ACCESS "RW" -// ============================================================================= -// Register : SIO_SPINLOCK26 -// Description : Reading from a spinlock address will: -// - Return 0 if lock is already locked -// - Otherwise return nonzero, and simultaneously claim the lock -// -// Writing (any value) releases the lock. -// If core 0 and core 1 attempt to claim the same lock -// simultaneously, core 0 wins. -// The value returned on success is 0x1 << lock number. -#define SIO_SPINLOCK26_OFFSET _u(0x00000168) -#define SIO_SPINLOCK26_BITS _u(0xffffffff) -#define SIO_SPINLOCK26_RESET _u(0x00000000) -#define SIO_SPINLOCK26_MSB _u(31) -#define SIO_SPINLOCK26_LSB _u(0) -#define SIO_SPINLOCK26_ACCESS "RW" -// ============================================================================= -// Register : SIO_SPINLOCK27 -// Description : Reading from a spinlock address will: -// - Return 0 if lock is already locked -// - Otherwise return nonzero, and simultaneously claim the lock -// -// Writing (any value) releases the lock. -// If core 0 and core 1 attempt to claim the same lock -// simultaneously, core 0 wins. -// The value returned on success is 0x1 << lock number. -#define SIO_SPINLOCK27_OFFSET _u(0x0000016c) -#define SIO_SPINLOCK27_BITS _u(0xffffffff) -#define SIO_SPINLOCK27_RESET _u(0x00000000) -#define SIO_SPINLOCK27_MSB _u(31) -#define SIO_SPINLOCK27_LSB _u(0) -#define SIO_SPINLOCK27_ACCESS "RW" -// ============================================================================= -// Register : SIO_SPINLOCK28 -// Description : Reading from a spinlock address will: -// - Return 0 if lock is already locked -// - Otherwise return nonzero, and simultaneously claim the lock -// -// Writing (any value) releases the lock. -// If core 0 and core 1 attempt to claim the same lock -// simultaneously, core 0 wins. -// The value returned on success is 0x1 << lock number. -#define SIO_SPINLOCK28_OFFSET _u(0x00000170) -#define SIO_SPINLOCK28_BITS _u(0xffffffff) -#define SIO_SPINLOCK28_RESET _u(0x00000000) -#define SIO_SPINLOCK28_MSB _u(31) -#define SIO_SPINLOCK28_LSB _u(0) -#define SIO_SPINLOCK28_ACCESS "RW" -// ============================================================================= -// Register : SIO_SPINLOCK29 -// Description : Reading from a spinlock address will: -// - Return 0 if lock is already locked -// - Otherwise return nonzero, and simultaneously claim the lock -// -// Writing (any value) releases the lock. -// If core 0 and core 1 attempt to claim the same lock -// simultaneously, core 0 wins. -// The value returned on success is 0x1 << lock number. -#define SIO_SPINLOCK29_OFFSET _u(0x00000174) -#define SIO_SPINLOCK29_BITS _u(0xffffffff) -#define SIO_SPINLOCK29_RESET _u(0x00000000) -#define SIO_SPINLOCK29_MSB _u(31) -#define SIO_SPINLOCK29_LSB _u(0) -#define SIO_SPINLOCK29_ACCESS "RW" -// ============================================================================= -// Register : SIO_SPINLOCK30 -// Description : Reading from a spinlock address will: -// - Return 0 if lock is already locked -// - Otherwise return nonzero, and simultaneously claim the lock -// -// Writing (any value) releases the lock. -// If core 0 and core 1 attempt to claim the same lock -// simultaneously, core 0 wins. -// The value returned on success is 0x1 << lock number. -#define SIO_SPINLOCK30_OFFSET _u(0x00000178) -#define SIO_SPINLOCK30_BITS _u(0xffffffff) -#define SIO_SPINLOCK30_RESET _u(0x00000000) -#define SIO_SPINLOCK30_MSB _u(31) -#define SIO_SPINLOCK30_LSB _u(0) -#define SIO_SPINLOCK30_ACCESS "RW" -// ============================================================================= -// Register : SIO_SPINLOCK31 -// Description : Reading from a spinlock address will: -// - Return 0 if lock is already locked -// - Otherwise return nonzero, and simultaneously claim the lock -// -// Writing (any value) releases the lock. -// If core 0 and core 1 attempt to claim the same lock -// simultaneously, core 0 wins. -// The value returned on success is 0x1 << lock number. -#define SIO_SPINLOCK31_OFFSET _u(0x0000017c) -#define SIO_SPINLOCK31_BITS _u(0xffffffff) -#define SIO_SPINLOCK31_RESET _u(0x00000000) -#define SIO_SPINLOCK31_MSB _u(31) -#define SIO_SPINLOCK31_LSB _u(0) -#define SIO_SPINLOCK31_ACCESS "RW" -// ============================================================================= -// Register : SIO_DOORBELL_OUT_SET -// Description : Trigger a doorbell interrupt on the opposite core. -// -// Write 1 to a bit to set the corresponding bit in DOORBELL_IN on -// the opposite core. This raises the opposite core's doorbell -// interrupt. -// -// Read to get the status of the doorbells currently asserted on -// the opposite core. This is equivalent to that core reading its -// own DOORBELL_IN status. -#define SIO_DOORBELL_OUT_SET_OFFSET _u(0x00000180) -#define SIO_DOORBELL_OUT_SET_BITS _u(0x000000ff) -#define SIO_DOORBELL_OUT_SET_RESET _u(0x00000000) -#define SIO_DOORBELL_OUT_SET_MSB _u(7) -#define SIO_DOORBELL_OUT_SET_LSB _u(0) -#define SIO_DOORBELL_OUT_SET_ACCESS "RW" -// ============================================================================= -// Register : SIO_DOORBELL_OUT_CLR -// Description : Clear doorbells which have been posted to the opposite core. -// This register is intended for debugging and initialisation -// purposes. -// -// Writing 1 to a bit in DOORBELL_OUT_CLR clears the corresponding -// bit in DOORBELL_IN on the opposite core. Clearing all bits will -// cause that core's doorbell interrupt to deassert. Since the -// usual order of events is for software to send events using -// DOORBELL_OUT_SET, and acknowledge incoming events by writing to -// DOORBELL_IN_CLR, this register should be used with caution to -// avoid race conditions. -// -// Reading returns the status of the doorbells currently asserted -// on the other core, i.e. is equivalent to that core reading its -// own DOORBELL_IN status. -#define SIO_DOORBELL_OUT_CLR_OFFSET _u(0x00000184) -#define SIO_DOORBELL_OUT_CLR_BITS _u(0x000000ff) -#define SIO_DOORBELL_OUT_CLR_RESET _u(0x00000000) -#define SIO_DOORBELL_OUT_CLR_MSB _u(7) -#define SIO_DOORBELL_OUT_CLR_LSB _u(0) -#define SIO_DOORBELL_OUT_CLR_ACCESS "WC" -// ============================================================================= -// Register : SIO_DOORBELL_IN_SET -// Description : Write 1s to trigger doorbell interrupts on this core. Read to -// get status of doorbells currently asserted on this core. -#define SIO_DOORBELL_IN_SET_OFFSET _u(0x00000188) -#define SIO_DOORBELL_IN_SET_BITS _u(0x000000ff) -#define SIO_DOORBELL_IN_SET_RESET _u(0x00000000) -#define SIO_DOORBELL_IN_SET_MSB _u(7) -#define SIO_DOORBELL_IN_SET_LSB _u(0) -#define SIO_DOORBELL_IN_SET_ACCESS "RW" -// ============================================================================= -// Register : SIO_DOORBELL_IN_CLR -// Description : Check and acknowledge doorbells posted to this core. This -// core's doorbell interrupt is asserted when any bit in this -// register is 1. -// -// Write 1 to each bit to clear that bit. The doorbell interrupt -// deasserts once all bits are cleared. Read to get status of -// doorbells currently asserted on this core. -#define SIO_DOORBELL_IN_CLR_OFFSET _u(0x0000018c) -#define SIO_DOORBELL_IN_CLR_BITS _u(0x000000ff) -#define SIO_DOORBELL_IN_CLR_RESET _u(0x00000000) -#define SIO_DOORBELL_IN_CLR_MSB _u(7) -#define SIO_DOORBELL_IN_CLR_LSB _u(0) -#define SIO_DOORBELL_IN_CLR_ACCESS "WC" -// ============================================================================= -// Register : SIO_PERI_NONSEC -// Description : Detach certain core-local peripherals from Secure SIO, and -// attach them to Non-secure SIO, so that Non-secure software can -// use them. Attempting to access one of these peripherals from -// the Secure SIO when it is attached to the Non-secure SIO, or -// vice versa, will generate a bus error. -// -// This register is per-core, and is only present on the Secure -// SIO. -// -// Most SIO hardware is duplicated across the Secure and Non- -// secure SIO, so is not listed in this register. -#define SIO_PERI_NONSEC_OFFSET _u(0x00000190) -#define SIO_PERI_NONSEC_BITS _u(0x00000023) -#define SIO_PERI_NONSEC_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : SIO_PERI_NONSEC_TMDS -// Description : IF 1, detach TMDS encoder (of this core) from the Secure SIO, -// and attach to the Non-secure SIO. -#define SIO_PERI_NONSEC_TMDS_RESET _u(0x0) -#define SIO_PERI_NONSEC_TMDS_BITS _u(0x00000020) -#define SIO_PERI_NONSEC_TMDS_MSB _u(5) -#define SIO_PERI_NONSEC_TMDS_LSB _u(5) -#define SIO_PERI_NONSEC_TMDS_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SIO_PERI_NONSEC_INTERP1 -// Description : If 1, detach interpolator 1 (of this core) from the Secure SIO, -// and attach to the Non-secure SIO. -#define SIO_PERI_NONSEC_INTERP1_RESET _u(0x0) -#define SIO_PERI_NONSEC_INTERP1_BITS _u(0x00000002) -#define SIO_PERI_NONSEC_INTERP1_MSB _u(1) -#define SIO_PERI_NONSEC_INTERP1_LSB _u(1) -#define SIO_PERI_NONSEC_INTERP1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SIO_PERI_NONSEC_INTERP0 -// Description : If 1, detach interpolator 0 (of this core) from the Secure SIO, -// and attach to the Non-secure SIO. -#define SIO_PERI_NONSEC_INTERP0_RESET _u(0x0) -#define SIO_PERI_NONSEC_INTERP0_BITS _u(0x00000001) -#define SIO_PERI_NONSEC_INTERP0_MSB _u(0) -#define SIO_PERI_NONSEC_INTERP0_LSB _u(0) -#define SIO_PERI_NONSEC_INTERP0_ACCESS "RW" -// ============================================================================= -// Register : SIO_RISCV_SOFTIRQ -// Description : Control the assertion of the standard software interrupt -// (MIP.MSIP) on the RISC-V cores. -// -// Unlike the RISC-V timer, this interrupt is not routed to a -// normal system-level interrupt line, so can not be used by the -// Arm cores. -// -// It is safe for both cores to write to this register on the same -// cycle. The set/clear effect is accumulated across both cores, -// and then applied. If a flag is both set and cleared on the same -// cycle, only the set takes effect. -#define SIO_RISCV_SOFTIRQ_OFFSET _u(0x000001a0) -#define SIO_RISCV_SOFTIRQ_BITS _u(0x00000303) -#define SIO_RISCV_SOFTIRQ_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : SIO_RISCV_SOFTIRQ_CORE1_CLR -// Description : Write 1 to atomically clear the core 1 software interrupt flag. -// Read to get the status of this flag. -#define SIO_RISCV_SOFTIRQ_CORE1_CLR_RESET _u(0x0) -#define SIO_RISCV_SOFTIRQ_CORE1_CLR_BITS _u(0x00000200) -#define SIO_RISCV_SOFTIRQ_CORE1_CLR_MSB _u(9) -#define SIO_RISCV_SOFTIRQ_CORE1_CLR_LSB _u(9) -#define SIO_RISCV_SOFTIRQ_CORE1_CLR_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SIO_RISCV_SOFTIRQ_CORE0_CLR -// Description : Write 1 to atomically clear the core 0 software interrupt flag. -// Read to get the status of this flag. -#define SIO_RISCV_SOFTIRQ_CORE0_CLR_RESET _u(0x0) -#define SIO_RISCV_SOFTIRQ_CORE0_CLR_BITS _u(0x00000100) -#define SIO_RISCV_SOFTIRQ_CORE0_CLR_MSB _u(8) -#define SIO_RISCV_SOFTIRQ_CORE0_CLR_LSB _u(8) -#define SIO_RISCV_SOFTIRQ_CORE0_CLR_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SIO_RISCV_SOFTIRQ_CORE1_SET -// Description : Write 1 to atomically set the core 1 software interrupt flag. -// Read to get the status of this flag. -#define SIO_RISCV_SOFTIRQ_CORE1_SET_RESET _u(0x0) -#define SIO_RISCV_SOFTIRQ_CORE1_SET_BITS _u(0x00000002) -#define SIO_RISCV_SOFTIRQ_CORE1_SET_MSB _u(1) -#define SIO_RISCV_SOFTIRQ_CORE1_SET_LSB _u(1) -#define SIO_RISCV_SOFTIRQ_CORE1_SET_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SIO_RISCV_SOFTIRQ_CORE0_SET -// Description : Write 1 to atomically set the core 0 software interrupt flag. -// Read to get the status of this flag. -#define SIO_RISCV_SOFTIRQ_CORE0_SET_RESET _u(0x0) -#define SIO_RISCV_SOFTIRQ_CORE0_SET_BITS _u(0x00000001) -#define SIO_RISCV_SOFTIRQ_CORE0_SET_MSB _u(0) -#define SIO_RISCV_SOFTIRQ_CORE0_SET_LSB _u(0) -#define SIO_RISCV_SOFTIRQ_CORE0_SET_ACCESS "RW" -// ============================================================================= -// Register : SIO_MTIME_CTRL -// Description : Control register for the RISC-V 64-bit Machine-mode timer. This -// timer is only present in the Secure SIO, so is only accessible -// to an Arm core in Secure mode or a RISC-V core in Machine mode. -// -// Note whilst this timer follows the RISC-V privileged -// specification, it is equally usable by the Arm cores. The -// interrupts are routed to normal system-level interrupt lines as -// well as to the MIP.MTIP inputs on the RISC-V cores. -#define SIO_MTIME_CTRL_OFFSET _u(0x000001a4) -#define SIO_MTIME_CTRL_BITS _u(0x0000000f) -#define SIO_MTIME_CTRL_RESET _u(0x0000000d) -// ----------------------------------------------------------------------------- -// Field : SIO_MTIME_CTRL_DBGPAUSE_CORE1 -// Description : If 1, the timer pauses when core 1 is in the debug halt state. -#define SIO_MTIME_CTRL_DBGPAUSE_CORE1_RESET _u(0x1) -#define SIO_MTIME_CTRL_DBGPAUSE_CORE1_BITS _u(0x00000008) -#define SIO_MTIME_CTRL_DBGPAUSE_CORE1_MSB _u(3) -#define SIO_MTIME_CTRL_DBGPAUSE_CORE1_LSB _u(3) -#define SIO_MTIME_CTRL_DBGPAUSE_CORE1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SIO_MTIME_CTRL_DBGPAUSE_CORE0 -// Description : If 1, the timer pauses when core 0 is in the debug halt state. -#define SIO_MTIME_CTRL_DBGPAUSE_CORE0_RESET _u(0x1) -#define SIO_MTIME_CTRL_DBGPAUSE_CORE0_BITS _u(0x00000004) -#define SIO_MTIME_CTRL_DBGPAUSE_CORE0_MSB _u(2) -#define SIO_MTIME_CTRL_DBGPAUSE_CORE0_LSB _u(2) -#define SIO_MTIME_CTRL_DBGPAUSE_CORE0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SIO_MTIME_CTRL_FULLSPEED -// Description : If 1, increment the timer every cycle (i.e. run directly from -// the system clock), rather than incrementing on the system-level -// timer tick input. -#define SIO_MTIME_CTRL_FULLSPEED_RESET _u(0x0) -#define SIO_MTIME_CTRL_FULLSPEED_BITS _u(0x00000002) -#define SIO_MTIME_CTRL_FULLSPEED_MSB _u(1) -#define SIO_MTIME_CTRL_FULLSPEED_LSB _u(1) -#define SIO_MTIME_CTRL_FULLSPEED_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SIO_MTIME_CTRL_EN -// Description : Timer enable bit. When 0, the timer will not increment -// automatically. -#define SIO_MTIME_CTRL_EN_RESET _u(0x1) -#define SIO_MTIME_CTRL_EN_BITS _u(0x00000001) -#define SIO_MTIME_CTRL_EN_MSB _u(0) -#define SIO_MTIME_CTRL_EN_LSB _u(0) -#define SIO_MTIME_CTRL_EN_ACCESS "RW" -// ============================================================================= -// Register : SIO_MTIME -// Description : Read/write access to the high half of RISC-V Machine-mode -// timer. This register is shared between both cores. If both -// cores write on the same cycle, core 1 takes precedence. -#define SIO_MTIME_OFFSET _u(0x000001b0) -#define SIO_MTIME_BITS _u(0xffffffff) -#define SIO_MTIME_RESET _u(0x00000000) -#define SIO_MTIME_MSB _u(31) -#define SIO_MTIME_LSB _u(0) -#define SIO_MTIME_ACCESS "RW" -// ============================================================================= -// Register : SIO_MTIMEH -// Description : Read/write access to the high half of RISC-V Machine-mode -// timer. This register is shared between both cores. If both -// cores write on the same cycle, core 1 takes precedence. -#define SIO_MTIMEH_OFFSET _u(0x000001b4) -#define SIO_MTIMEH_BITS _u(0xffffffff) -#define SIO_MTIMEH_RESET _u(0x00000000) -#define SIO_MTIMEH_MSB _u(31) -#define SIO_MTIMEH_LSB _u(0) -#define SIO_MTIMEH_ACCESS "RW" -// ============================================================================= -// Register : SIO_MTIMECMP -// Description : Low half of RISC-V Machine-mode timer comparator. This register -// is core-local, i.e., each core gets a copy of this register, -// with the comparison result routed to its own interrupt line. -// -// The timer interrupt is asserted whenever MTIME is greater than -// or equal to MTIMECMP. This comparison is unsigned, and -// performed on the full 64-bit values. -#define SIO_MTIMECMP_OFFSET _u(0x000001b8) -#define SIO_MTIMECMP_BITS _u(0xffffffff) -#define SIO_MTIMECMP_RESET _u(0xffffffff) -#define SIO_MTIMECMP_MSB _u(31) -#define SIO_MTIMECMP_LSB _u(0) -#define SIO_MTIMECMP_ACCESS "RW" -// ============================================================================= -// Register : SIO_MTIMECMPH -// Description : High half of RISC-V Machine-mode timer comparator. This -// register is core-local. -// -// The timer interrupt is asserted whenever MTIME is greater than -// or equal to MTIMECMP. This comparison is unsigned, and -// performed on the full 64-bit values. -#define SIO_MTIMECMPH_OFFSET _u(0x000001bc) -#define SIO_MTIMECMPH_BITS _u(0xffffffff) -#define SIO_MTIMECMPH_RESET _u(0xffffffff) -#define SIO_MTIMECMPH_MSB _u(31) -#define SIO_MTIMECMPH_LSB _u(0) -#define SIO_MTIMECMPH_ACCESS "RW" -// ============================================================================= -// Register : SIO_TMDS_CTRL -// Description : Control register for TMDS encoder. -#define SIO_TMDS_CTRL_OFFSET _u(0x000001c0) -#define SIO_TMDS_CTRL_BITS _u(0x1f9fffff) -#define SIO_TMDS_CTRL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : SIO_TMDS_CTRL_CLEAR_BALANCE -// Description : Clear the running DC balance state of the TMDS encoders. This -// bit should be written once at the beginning of each scanline. -#define SIO_TMDS_CTRL_CLEAR_BALANCE_RESET _u(0x0) -#define SIO_TMDS_CTRL_CLEAR_BALANCE_BITS _u(0x10000000) -#define SIO_TMDS_CTRL_CLEAR_BALANCE_MSB _u(28) -#define SIO_TMDS_CTRL_CLEAR_BALANCE_LSB _u(28) -#define SIO_TMDS_CTRL_CLEAR_BALANCE_ACCESS "SC" -// ----------------------------------------------------------------------------- -// Field : SIO_TMDS_CTRL_PIX2_NOSHIFT -// Description : When encoding two pixels's worth of symbols in one cycle (a -// read of a PEEK/POP_DOUBLE register), the second encoder sees a -// shifted version of the colour data register. -// -// This control disables that shift, so that both encoder layers -// see the same pixel data. This is used for pixel doubling. -#define SIO_TMDS_CTRL_PIX2_NOSHIFT_RESET _u(0x0) -#define SIO_TMDS_CTRL_PIX2_NOSHIFT_BITS _u(0x08000000) -#define SIO_TMDS_CTRL_PIX2_NOSHIFT_MSB _u(27) -#define SIO_TMDS_CTRL_PIX2_NOSHIFT_LSB _u(27) -#define SIO_TMDS_CTRL_PIX2_NOSHIFT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SIO_TMDS_CTRL_PIX_SHIFT -// Description : Shift applied to the colour data register with each read of a -// POP alias register. -// -// Reading from the POP_SINGLE register, or reading from the -// POP_DOUBLE register with PIX2_NOSHIFT set (for pixel doubling), -// shifts by the indicated amount. -// -// Reading from a POP_DOUBLE register when PIX2_NOSHIFT is clear -// will shift by double the indicated amount. (Shift by 32 means -// no shift.) -// 0x0 -> Do not shift the colour data register. -// 0x1 -> Shift the colour data register by 1 bit -// 0x2 -> Shift the colour data register by 2 bits -// 0x3 -> Shift the colour data register by 4 bits -// 0x4 -> Shift the colour data register by 8 bits -// 0x5 -> Shift the colour data register by 16 bits -#define SIO_TMDS_CTRL_PIX_SHIFT_RESET _u(0x0) -#define SIO_TMDS_CTRL_PIX_SHIFT_BITS _u(0x07000000) -#define SIO_TMDS_CTRL_PIX_SHIFT_MSB _u(26) -#define SIO_TMDS_CTRL_PIX_SHIFT_LSB _u(24) -#define SIO_TMDS_CTRL_PIX_SHIFT_ACCESS "RW" -#define SIO_TMDS_CTRL_PIX_SHIFT_VALUE_0 _u(0x0) -#define SIO_TMDS_CTRL_PIX_SHIFT_VALUE_1 _u(0x1) -#define SIO_TMDS_CTRL_PIX_SHIFT_VALUE_2 _u(0x2) -#define SIO_TMDS_CTRL_PIX_SHIFT_VALUE_4 _u(0x3) -#define SIO_TMDS_CTRL_PIX_SHIFT_VALUE_8 _u(0x4) -#define SIO_TMDS_CTRL_PIX_SHIFT_VALUE_16 _u(0x5) -// ----------------------------------------------------------------------------- -// Field : SIO_TMDS_CTRL_INTERLEAVE -// Description : Enable lane interleaving for reads of PEEK_SINGLE/POP_SINGLE. -// -// When interleaving is disabled, each of the 3 symbols appears as -// a contiguous 10-bit field, with lane 0 being the least- -// significant and starting at bit 0 of the register. -// -// When interleaving is enabled, the symbols are packed into 5 -// chunks of 3 lanes times 2 bits (30 bits total). Each chunk -// contains two bits of a TMDS symbol per lane, with lane 0 being -// the least significant. -#define SIO_TMDS_CTRL_INTERLEAVE_RESET _u(0x0) -#define SIO_TMDS_CTRL_INTERLEAVE_BITS _u(0x00800000) -#define SIO_TMDS_CTRL_INTERLEAVE_MSB _u(23) -#define SIO_TMDS_CTRL_INTERLEAVE_LSB _u(23) -#define SIO_TMDS_CTRL_INTERLEAVE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SIO_TMDS_CTRL_L2_NBITS -// Description : Number of valid colour MSBs for lane 2 (1-8 bits, encoded as 0 -// through 7). Remaining LSBs are masked to 0 after the rotate. -#define SIO_TMDS_CTRL_L2_NBITS_RESET _u(0x0) -#define SIO_TMDS_CTRL_L2_NBITS_BITS _u(0x001c0000) -#define SIO_TMDS_CTRL_L2_NBITS_MSB _u(20) -#define SIO_TMDS_CTRL_L2_NBITS_LSB _u(18) -#define SIO_TMDS_CTRL_L2_NBITS_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SIO_TMDS_CTRL_L1_NBITS -// Description : Number of valid colour MSBs for lane 1 (1-8 bits, encoded as 0 -// through 7). Remaining LSBs are masked to 0 after the rotate. -#define SIO_TMDS_CTRL_L1_NBITS_RESET _u(0x0) -#define SIO_TMDS_CTRL_L1_NBITS_BITS _u(0x00038000) -#define SIO_TMDS_CTRL_L1_NBITS_MSB _u(17) -#define SIO_TMDS_CTRL_L1_NBITS_LSB _u(15) -#define SIO_TMDS_CTRL_L1_NBITS_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SIO_TMDS_CTRL_L0_NBITS -// Description : Number of valid colour MSBs for lane 0 (1-8 bits, encoded as 0 -// through 7). Remaining LSBs are masked to 0 after the rotate. -#define SIO_TMDS_CTRL_L0_NBITS_RESET _u(0x0) -#define SIO_TMDS_CTRL_L0_NBITS_BITS _u(0x00007000) -#define SIO_TMDS_CTRL_L0_NBITS_MSB _u(14) -#define SIO_TMDS_CTRL_L0_NBITS_LSB _u(12) -#define SIO_TMDS_CTRL_L0_NBITS_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SIO_TMDS_CTRL_L2_ROT -// Description : Right-rotate the 16 LSBs of the colour accumulator by 0-15 -// bits, in order to get the MSB of the lane 2 (red) colour data -// aligned with the MSB of the 8-bit encoder input. -// -// For example, for RGB565 (red most significant), red is bits -// 15:11, so should be right-rotated by 8 bits to align with bits -// 7:3 of the encoder input. -#define SIO_TMDS_CTRL_L2_ROT_RESET _u(0x0) -#define SIO_TMDS_CTRL_L2_ROT_BITS _u(0x00000f00) -#define SIO_TMDS_CTRL_L2_ROT_MSB _u(11) -#define SIO_TMDS_CTRL_L2_ROT_LSB _u(8) -#define SIO_TMDS_CTRL_L2_ROT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SIO_TMDS_CTRL_L1_ROT -// Description : Right-rotate the 16 LSBs of the colour accumulator by 0-15 -// bits, in order to get the MSB of the lane 1 (green) colour data -// aligned with the MSB of the 8-bit encoder input. -// -// For example, for RGB565, green is bits 10:5, so should be -// right-rotated by 3 bits to align with bits 7:2 of the encoder -// input. -#define SIO_TMDS_CTRL_L1_ROT_RESET _u(0x0) -#define SIO_TMDS_CTRL_L1_ROT_BITS _u(0x000000f0) -#define SIO_TMDS_CTRL_L1_ROT_MSB _u(7) -#define SIO_TMDS_CTRL_L1_ROT_LSB _u(4) -#define SIO_TMDS_CTRL_L1_ROT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SIO_TMDS_CTRL_L0_ROT -// Description : Right-rotate the 16 LSBs of the colour accumulator by 0-15 -// bits, in order to get the MSB of the lane 0 (blue) colour data -// aligned with the MSB of the 8-bit encoder input. -// -// For example, for RGB565 (red most significant), blue is bits -// 4:0, so should be right-rotated by 13 to align with bits 7:3 of -// the encoder input. -#define SIO_TMDS_CTRL_L0_ROT_RESET _u(0x0) -#define SIO_TMDS_CTRL_L0_ROT_BITS _u(0x0000000f) -#define SIO_TMDS_CTRL_L0_ROT_MSB _u(3) -#define SIO_TMDS_CTRL_L0_ROT_LSB _u(0) -#define SIO_TMDS_CTRL_L0_ROT_ACCESS "RW" -// ============================================================================= -// Register : SIO_TMDS_WDATA -// Description : Write-only access to the TMDS colour data register. -#define SIO_TMDS_WDATA_OFFSET _u(0x000001c4) -#define SIO_TMDS_WDATA_BITS _u(0xffffffff) -#define SIO_TMDS_WDATA_RESET _u(0x00000000) -#define SIO_TMDS_WDATA_MSB _u(31) -#define SIO_TMDS_WDATA_LSB _u(0) -#define SIO_TMDS_WDATA_ACCESS "WO" -// ============================================================================= -// Register : SIO_TMDS_PEEK_SINGLE -// Description : Get the encoding of one pixel's worth of colour data, packed -// into a 32-bit value (3x10-bit symbols). -// -// The PEEK alias does not shift the colour register when read, -// but still advances the running DC balance state of each -// encoder. This is useful for pixel doubling. -#define SIO_TMDS_PEEK_SINGLE_OFFSET _u(0x000001c8) -#define SIO_TMDS_PEEK_SINGLE_BITS _u(0xffffffff) -#define SIO_TMDS_PEEK_SINGLE_RESET _u(0x00000000) -#define SIO_TMDS_PEEK_SINGLE_MSB _u(31) -#define SIO_TMDS_PEEK_SINGLE_LSB _u(0) -#define SIO_TMDS_PEEK_SINGLE_ACCESS "RF" -// ============================================================================= -// Register : SIO_TMDS_POP_SINGLE -// Description : Get the encoding of one pixel's worth of colour data, packed -// into a 32-bit value. The packing is 5 chunks of 3 lanes times 2 -// bits (30 bits total). Each chunk contains two bits of a TMDS -// symbol per lane. This format is intended for shifting out with -// the HSTX peripheral on RP2350. -// -// The POP alias shifts the colour register when read, as well as -// advancing the running DC balance state of each encoder. -#define SIO_TMDS_POP_SINGLE_OFFSET _u(0x000001cc) -#define SIO_TMDS_POP_SINGLE_BITS _u(0xffffffff) -#define SIO_TMDS_POP_SINGLE_RESET _u(0x00000000) -#define SIO_TMDS_POP_SINGLE_MSB _u(31) -#define SIO_TMDS_POP_SINGLE_LSB _u(0) -#define SIO_TMDS_POP_SINGLE_ACCESS "RF" -// ============================================================================= -// Register : SIO_TMDS_PEEK_DOUBLE_L0 -// Description : Get lane 0 of the encoding of two pixels' worth of colour data. -// Two 10-bit TMDS symbols are packed at the bottom of a 32-bit -// word. -// -// The PEEK alias does not shift the colour register when read, -// but still advances the lane 0 DC balance state. This is useful -// if all 3 lanes' worth of encode are to be read at once, rather -// than processing the entire scanline for one lane before moving -// to the next lane. -#define SIO_TMDS_PEEK_DOUBLE_L0_OFFSET _u(0x000001d0) -#define SIO_TMDS_PEEK_DOUBLE_L0_BITS _u(0xffffffff) -#define SIO_TMDS_PEEK_DOUBLE_L0_RESET _u(0x00000000) -#define SIO_TMDS_PEEK_DOUBLE_L0_MSB _u(31) -#define SIO_TMDS_PEEK_DOUBLE_L0_LSB _u(0) -#define SIO_TMDS_PEEK_DOUBLE_L0_ACCESS "RF" -// ============================================================================= -// Register : SIO_TMDS_POP_DOUBLE_L0 -// Description : Get lane 0 of the encoding of two pixels' worth of colour data. -// Two 10-bit TMDS symbols are packed at the bottom of a 32-bit -// word. -// -// The POP alias shifts the colour register when read, according -// to the values of PIX_SHIFT and PIX2_NOSHIFT. -#define SIO_TMDS_POP_DOUBLE_L0_OFFSET _u(0x000001d4) -#define SIO_TMDS_POP_DOUBLE_L0_BITS _u(0xffffffff) -#define SIO_TMDS_POP_DOUBLE_L0_RESET _u(0x00000000) -#define SIO_TMDS_POP_DOUBLE_L0_MSB _u(31) -#define SIO_TMDS_POP_DOUBLE_L0_LSB _u(0) -#define SIO_TMDS_POP_DOUBLE_L0_ACCESS "RF" -// ============================================================================= -// Register : SIO_TMDS_PEEK_DOUBLE_L1 -// Description : Get lane 1 of the encoding of two pixels' worth of colour data. -// Two 10-bit TMDS symbols are packed at the bottom of a 32-bit -// word. -// -// The PEEK alias does not shift the colour register when read, -// but still advances the lane 1 DC balance state. This is useful -// if all 3 lanes' worth of encode are to be read at once, rather -// than processing the entire scanline for one lane before moving -// to the next lane. -#define SIO_TMDS_PEEK_DOUBLE_L1_OFFSET _u(0x000001d8) -#define SIO_TMDS_PEEK_DOUBLE_L1_BITS _u(0xffffffff) -#define SIO_TMDS_PEEK_DOUBLE_L1_RESET _u(0x00000000) -#define SIO_TMDS_PEEK_DOUBLE_L1_MSB _u(31) -#define SIO_TMDS_PEEK_DOUBLE_L1_LSB _u(0) -#define SIO_TMDS_PEEK_DOUBLE_L1_ACCESS "RF" -// ============================================================================= -// Register : SIO_TMDS_POP_DOUBLE_L1 -// Description : Get lane 1 of the encoding of two pixels' worth of colour data. -// Two 10-bit TMDS symbols are packed at the bottom of a 32-bit -// word. -// -// The POP alias shifts the colour register when read, according -// to the values of PIX_SHIFT and PIX2_NOSHIFT. -#define SIO_TMDS_POP_DOUBLE_L1_OFFSET _u(0x000001dc) -#define SIO_TMDS_POP_DOUBLE_L1_BITS _u(0xffffffff) -#define SIO_TMDS_POP_DOUBLE_L1_RESET _u(0x00000000) -#define SIO_TMDS_POP_DOUBLE_L1_MSB _u(31) -#define SIO_TMDS_POP_DOUBLE_L1_LSB _u(0) -#define SIO_TMDS_POP_DOUBLE_L1_ACCESS "RF" -// ============================================================================= -// Register : SIO_TMDS_PEEK_DOUBLE_L2 -// Description : Get lane 2 of the encoding of two pixels' worth of colour data. -// Two 10-bit TMDS symbols are packed at the bottom of a 32-bit -// word. -// -// The PEEK alias does not shift the colour register when read, -// but still advances the lane 2 DC balance state. This is useful -// if all 3 lanes' worth of encode are to be read at once, rather -// than processing the entire scanline for one lane before moving -// to the next lane. -#define SIO_TMDS_PEEK_DOUBLE_L2_OFFSET _u(0x000001e0) -#define SIO_TMDS_PEEK_DOUBLE_L2_BITS _u(0xffffffff) -#define SIO_TMDS_PEEK_DOUBLE_L2_RESET _u(0x00000000) -#define SIO_TMDS_PEEK_DOUBLE_L2_MSB _u(31) -#define SIO_TMDS_PEEK_DOUBLE_L2_LSB _u(0) -#define SIO_TMDS_PEEK_DOUBLE_L2_ACCESS "RF" -// ============================================================================= -// Register : SIO_TMDS_POP_DOUBLE_L2 -// Description : Get lane 2 of the encoding of two pixels' worth of colour data. -// Two 10-bit TMDS symbols are packed at the bottom of a 32-bit -// word. -// -// The POP alias shifts the colour register when read, according -// to the values of PIX_SHIFT and PIX2_NOSHIFT. -#define SIO_TMDS_POP_DOUBLE_L2_OFFSET _u(0x000001e4) -#define SIO_TMDS_POP_DOUBLE_L2_BITS _u(0xffffffff) -#define SIO_TMDS_POP_DOUBLE_L2_RESET _u(0x00000000) -#define SIO_TMDS_POP_DOUBLE_L2_MSB _u(31) -#define SIO_TMDS_POP_DOUBLE_L2_LSB _u(0) -#define SIO_TMDS_POP_DOUBLE_L2_ACCESS "RF" -// ============================================================================= -#endif // _HARDWARE_REGS_SIO_H - diff --git a/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/spi.h b/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/spi.h deleted file mode 100644 index d9d3b14df6..0000000000 --- a/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/spi.h +++ /dev/null @@ -1,523 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -// ============================================================================= -// Register block : SPI -// Version : 1 -// Bus type : apb -// ============================================================================= -#ifndef _HARDWARE_REGS_SPI_H -#define _HARDWARE_REGS_SPI_H -// ============================================================================= -// Register : SPI_SSPCR0 -// Description : Control register 0, SSPCR0 on page 3-4 -#define SPI_SSPCR0_OFFSET _u(0x00000000) -#define SPI_SSPCR0_BITS _u(0x0000ffff) -#define SPI_SSPCR0_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : SPI_SSPCR0_SCR -// Description : Serial clock rate. The value SCR is used to generate the -// transmit and receive bit rate of the PrimeCell SSP. The bit -// rate is: F SSPCLK CPSDVSR x (1+SCR) where CPSDVSR is an even -// value from 2-254, programmed through the SSPCPSR register and -// SCR is a value from 0-255. -#define SPI_SSPCR0_SCR_RESET _u(0x00) -#define SPI_SSPCR0_SCR_BITS _u(0x0000ff00) -#define SPI_SSPCR0_SCR_MSB _u(15) -#define SPI_SSPCR0_SCR_LSB _u(8) -#define SPI_SSPCR0_SCR_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SPI_SSPCR0_SPH -// Description : SSPCLKOUT phase, applicable to Motorola SPI frame format only. -// See Motorola SPI frame format on page 2-10. -#define SPI_SSPCR0_SPH_RESET _u(0x0) -#define SPI_SSPCR0_SPH_BITS _u(0x00000080) -#define SPI_SSPCR0_SPH_MSB _u(7) -#define SPI_SSPCR0_SPH_LSB _u(7) -#define SPI_SSPCR0_SPH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SPI_SSPCR0_SPO -// Description : SSPCLKOUT polarity, applicable to Motorola SPI frame format -// only. See Motorola SPI frame format on page 2-10. -#define SPI_SSPCR0_SPO_RESET _u(0x0) -#define SPI_SSPCR0_SPO_BITS _u(0x00000040) -#define SPI_SSPCR0_SPO_MSB _u(6) -#define SPI_SSPCR0_SPO_LSB _u(6) -#define SPI_SSPCR0_SPO_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SPI_SSPCR0_FRF -// Description : Frame format: 00 Motorola SPI frame format. 01 TI synchronous -// serial frame format. 10 National Microwire frame format. 11 -// Reserved, undefined operation. -#define SPI_SSPCR0_FRF_RESET _u(0x0) -#define SPI_SSPCR0_FRF_BITS _u(0x00000030) -#define SPI_SSPCR0_FRF_MSB _u(5) -#define SPI_SSPCR0_FRF_LSB _u(4) -#define SPI_SSPCR0_FRF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SPI_SSPCR0_DSS -// Description : Data Size Select: 0000 Reserved, undefined operation. 0001 -// Reserved, undefined operation. 0010 Reserved, undefined -// operation. 0011 4-bit data. 0100 5-bit data. 0101 6-bit data. -// 0110 7-bit data. 0111 8-bit data. 1000 9-bit data. 1001 10-bit -// data. 1010 11-bit data. 1011 12-bit data. 1100 13-bit data. -// 1101 14-bit data. 1110 15-bit data. 1111 16-bit data. -#define SPI_SSPCR0_DSS_RESET _u(0x0) -#define SPI_SSPCR0_DSS_BITS _u(0x0000000f) -#define SPI_SSPCR0_DSS_MSB _u(3) -#define SPI_SSPCR0_DSS_LSB _u(0) -#define SPI_SSPCR0_DSS_ACCESS "RW" -// ============================================================================= -// Register : SPI_SSPCR1 -// Description : Control register 1, SSPCR1 on page 3-5 -#define SPI_SSPCR1_OFFSET _u(0x00000004) -#define SPI_SSPCR1_BITS _u(0x0000000f) -#define SPI_SSPCR1_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : SPI_SSPCR1_SOD -// Description : Slave-mode output disable. This bit is relevant only in the -// slave mode, MS=1. In multiple-slave systems, it is possible for -// an PrimeCell SSP master to broadcast a message to all slaves in -// the system while ensuring that only one slave drives data onto -// its serial output line. In such systems the RXD lines from -// multiple slaves could be tied together. To operate in such -// systems, the SOD bit can be set if the PrimeCell SSP slave is -// not supposed to drive the SSPTXD line: 0 SSP can drive the -// SSPTXD output in slave mode. 1 SSP must not drive the SSPTXD -// output in slave mode. -#define SPI_SSPCR1_SOD_RESET _u(0x0) -#define SPI_SSPCR1_SOD_BITS _u(0x00000008) -#define SPI_SSPCR1_SOD_MSB _u(3) -#define SPI_SSPCR1_SOD_LSB _u(3) -#define SPI_SSPCR1_SOD_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SPI_SSPCR1_MS -// Description : Master or slave mode select. This bit can be modified only when -// the PrimeCell SSP is disabled, SSE=0: 0 Device configured as -// master, default. 1 Device configured as slave. -#define SPI_SSPCR1_MS_RESET _u(0x0) -#define SPI_SSPCR1_MS_BITS _u(0x00000004) -#define SPI_SSPCR1_MS_MSB _u(2) -#define SPI_SSPCR1_MS_LSB _u(2) -#define SPI_SSPCR1_MS_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SPI_SSPCR1_SSE -// Description : Synchronous serial port enable: 0 SSP operation disabled. 1 SSP -// operation enabled. -#define SPI_SSPCR1_SSE_RESET _u(0x0) -#define SPI_SSPCR1_SSE_BITS _u(0x00000002) -#define SPI_SSPCR1_SSE_MSB _u(1) -#define SPI_SSPCR1_SSE_LSB _u(1) -#define SPI_SSPCR1_SSE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SPI_SSPCR1_LBM -// Description : Loop back mode: 0 Normal serial port operation enabled. 1 -// Output of transmit serial shifter is connected to input of -// receive serial shifter internally. -#define SPI_SSPCR1_LBM_RESET _u(0x0) -#define SPI_SSPCR1_LBM_BITS _u(0x00000001) -#define SPI_SSPCR1_LBM_MSB _u(0) -#define SPI_SSPCR1_LBM_LSB _u(0) -#define SPI_SSPCR1_LBM_ACCESS "RW" -// ============================================================================= -// Register : SPI_SSPDR -// Description : Data register, SSPDR on page 3-6 -#define SPI_SSPDR_OFFSET _u(0x00000008) -#define SPI_SSPDR_BITS _u(0x0000ffff) -#define SPI_SSPDR_RESET "-" -// ----------------------------------------------------------------------------- -// Field : SPI_SSPDR_DATA -// Description : Transmit/Receive FIFO: Read Receive FIFO. Write Transmit FIFO. -// You must right-justify data when the PrimeCell SSP is -// programmed for a data size that is less than 16 bits. Unused -// bits at the top are ignored by transmit logic. The receive -// logic automatically right-justifies. -#define SPI_SSPDR_DATA_RESET "-" -#define SPI_SSPDR_DATA_BITS _u(0x0000ffff) -#define SPI_SSPDR_DATA_MSB _u(15) -#define SPI_SSPDR_DATA_LSB _u(0) -#define SPI_SSPDR_DATA_ACCESS "RWF" -// ============================================================================= -// Register : SPI_SSPSR -// Description : Status register, SSPSR on page 3-7 -#define SPI_SSPSR_OFFSET _u(0x0000000c) -#define SPI_SSPSR_BITS _u(0x0000001f) -#define SPI_SSPSR_RESET _u(0x00000003) -// ----------------------------------------------------------------------------- -// Field : SPI_SSPSR_BSY -// Description : PrimeCell SSP busy flag, RO: 0 SSP is idle. 1 SSP is currently -// transmitting and/or receiving a frame or the transmit FIFO is -// not empty. -#define SPI_SSPSR_BSY_RESET _u(0x0) -#define SPI_SSPSR_BSY_BITS _u(0x00000010) -#define SPI_SSPSR_BSY_MSB _u(4) -#define SPI_SSPSR_BSY_LSB _u(4) -#define SPI_SSPSR_BSY_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : SPI_SSPSR_RFF -// Description : Receive FIFO full, RO: 0 Receive FIFO is not full. 1 Receive -// FIFO is full. -#define SPI_SSPSR_RFF_RESET _u(0x0) -#define SPI_SSPSR_RFF_BITS _u(0x00000008) -#define SPI_SSPSR_RFF_MSB _u(3) -#define SPI_SSPSR_RFF_LSB _u(3) -#define SPI_SSPSR_RFF_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : SPI_SSPSR_RNE -// Description : Receive FIFO not empty, RO: 0 Receive FIFO is empty. 1 Receive -// FIFO is not empty. -#define SPI_SSPSR_RNE_RESET _u(0x0) -#define SPI_SSPSR_RNE_BITS _u(0x00000004) -#define SPI_SSPSR_RNE_MSB _u(2) -#define SPI_SSPSR_RNE_LSB _u(2) -#define SPI_SSPSR_RNE_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : SPI_SSPSR_TNF -// Description : Transmit FIFO not full, RO: 0 Transmit FIFO is full. 1 Transmit -// FIFO is not full. -#define SPI_SSPSR_TNF_RESET _u(0x1) -#define SPI_SSPSR_TNF_BITS _u(0x00000002) -#define SPI_SSPSR_TNF_MSB _u(1) -#define SPI_SSPSR_TNF_LSB _u(1) -#define SPI_SSPSR_TNF_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : SPI_SSPSR_TFE -// Description : Transmit FIFO empty, RO: 0 Transmit FIFO is not empty. 1 -// Transmit FIFO is empty. -#define SPI_SSPSR_TFE_RESET _u(0x1) -#define SPI_SSPSR_TFE_BITS _u(0x00000001) -#define SPI_SSPSR_TFE_MSB _u(0) -#define SPI_SSPSR_TFE_LSB _u(0) -#define SPI_SSPSR_TFE_ACCESS "RO" -// ============================================================================= -// Register : SPI_SSPCPSR -// Description : Clock prescale register, SSPCPSR on page 3-8 -#define SPI_SSPCPSR_OFFSET _u(0x00000010) -#define SPI_SSPCPSR_BITS _u(0x000000ff) -#define SPI_SSPCPSR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : SPI_SSPCPSR_CPSDVSR -// Description : Clock prescale divisor. Must be an even number from 2-254, -// depending on the frequency of SSPCLK. The least significant bit -// always returns zero on reads. -#define SPI_SSPCPSR_CPSDVSR_RESET _u(0x00) -#define SPI_SSPCPSR_CPSDVSR_BITS _u(0x000000ff) -#define SPI_SSPCPSR_CPSDVSR_MSB _u(7) -#define SPI_SSPCPSR_CPSDVSR_LSB _u(0) -#define SPI_SSPCPSR_CPSDVSR_ACCESS "RW" -// ============================================================================= -// Register : SPI_SSPIMSC -// Description : Interrupt mask set or clear register, SSPIMSC on page 3-9 -#define SPI_SSPIMSC_OFFSET _u(0x00000014) -#define SPI_SSPIMSC_BITS _u(0x0000000f) -#define SPI_SSPIMSC_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : SPI_SSPIMSC_TXIM -// Description : Transmit FIFO interrupt mask: 0 Transmit FIFO half empty or -// less condition interrupt is masked. 1 Transmit FIFO half empty -// or less condition interrupt is not masked. -#define SPI_SSPIMSC_TXIM_RESET _u(0x0) -#define SPI_SSPIMSC_TXIM_BITS _u(0x00000008) -#define SPI_SSPIMSC_TXIM_MSB _u(3) -#define SPI_SSPIMSC_TXIM_LSB _u(3) -#define SPI_SSPIMSC_TXIM_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SPI_SSPIMSC_RXIM -// Description : Receive FIFO interrupt mask: 0 Receive FIFO half full or less -// condition interrupt is masked. 1 Receive FIFO half full or less -// condition interrupt is not masked. -#define SPI_SSPIMSC_RXIM_RESET _u(0x0) -#define SPI_SSPIMSC_RXIM_BITS _u(0x00000004) -#define SPI_SSPIMSC_RXIM_MSB _u(2) -#define SPI_SSPIMSC_RXIM_LSB _u(2) -#define SPI_SSPIMSC_RXIM_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SPI_SSPIMSC_RTIM -// Description : Receive timeout interrupt mask: 0 Receive FIFO not empty and no -// read prior to timeout period interrupt is masked. 1 Receive -// FIFO not empty and no read prior to timeout period interrupt is -// not masked. -#define SPI_SSPIMSC_RTIM_RESET _u(0x0) -#define SPI_SSPIMSC_RTIM_BITS _u(0x00000002) -#define SPI_SSPIMSC_RTIM_MSB _u(1) -#define SPI_SSPIMSC_RTIM_LSB _u(1) -#define SPI_SSPIMSC_RTIM_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SPI_SSPIMSC_RORIM -// Description : Receive overrun interrupt mask: 0 Receive FIFO written to while -// full condition interrupt is masked. 1 Receive FIFO written to -// while full condition interrupt is not masked. -#define SPI_SSPIMSC_RORIM_RESET _u(0x0) -#define SPI_SSPIMSC_RORIM_BITS _u(0x00000001) -#define SPI_SSPIMSC_RORIM_MSB _u(0) -#define SPI_SSPIMSC_RORIM_LSB _u(0) -#define SPI_SSPIMSC_RORIM_ACCESS "RW" -// ============================================================================= -// Register : SPI_SSPRIS -// Description : Raw interrupt status register, SSPRIS on page 3-10 -#define SPI_SSPRIS_OFFSET _u(0x00000018) -#define SPI_SSPRIS_BITS _u(0x0000000f) -#define SPI_SSPRIS_RESET _u(0x00000008) -// ----------------------------------------------------------------------------- -// Field : SPI_SSPRIS_TXRIS -// Description : Gives the raw interrupt state, prior to masking, of the -// SSPTXINTR interrupt -#define SPI_SSPRIS_TXRIS_RESET _u(0x1) -#define SPI_SSPRIS_TXRIS_BITS _u(0x00000008) -#define SPI_SSPRIS_TXRIS_MSB _u(3) -#define SPI_SSPRIS_TXRIS_LSB _u(3) -#define SPI_SSPRIS_TXRIS_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : SPI_SSPRIS_RXRIS -// Description : Gives the raw interrupt state, prior to masking, of the -// SSPRXINTR interrupt -#define SPI_SSPRIS_RXRIS_RESET _u(0x0) -#define SPI_SSPRIS_RXRIS_BITS _u(0x00000004) -#define SPI_SSPRIS_RXRIS_MSB _u(2) -#define SPI_SSPRIS_RXRIS_LSB _u(2) -#define SPI_SSPRIS_RXRIS_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : SPI_SSPRIS_RTRIS -// Description : Gives the raw interrupt state, prior to masking, of the -// SSPRTINTR interrupt -#define SPI_SSPRIS_RTRIS_RESET _u(0x0) -#define SPI_SSPRIS_RTRIS_BITS _u(0x00000002) -#define SPI_SSPRIS_RTRIS_MSB _u(1) -#define SPI_SSPRIS_RTRIS_LSB _u(1) -#define SPI_SSPRIS_RTRIS_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : SPI_SSPRIS_RORRIS -// Description : Gives the raw interrupt state, prior to masking, of the -// SSPRORINTR interrupt -#define SPI_SSPRIS_RORRIS_RESET _u(0x0) -#define SPI_SSPRIS_RORRIS_BITS _u(0x00000001) -#define SPI_SSPRIS_RORRIS_MSB _u(0) -#define SPI_SSPRIS_RORRIS_LSB _u(0) -#define SPI_SSPRIS_RORRIS_ACCESS "RO" -// ============================================================================= -// Register : SPI_SSPMIS -// Description : Masked interrupt status register, SSPMIS on page 3-11 -#define SPI_SSPMIS_OFFSET _u(0x0000001c) -#define SPI_SSPMIS_BITS _u(0x0000000f) -#define SPI_SSPMIS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : SPI_SSPMIS_TXMIS -// Description : Gives the transmit FIFO masked interrupt state, after masking, -// of the SSPTXINTR interrupt -#define SPI_SSPMIS_TXMIS_RESET _u(0x0) -#define SPI_SSPMIS_TXMIS_BITS _u(0x00000008) -#define SPI_SSPMIS_TXMIS_MSB _u(3) -#define SPI_SSPMIS_TXMIS_LSB _u(3) -#define SPI_SSPMIS_TXMIS_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : SPI_SSPMIS_RXMIS -// Description : Gives the receive FIFO masked interrupt state, after masking, -// of the SSPRXINTR interrupt -#define SPI_SSPMIS_RXMIS_RESET _u(0x0) -#define SPI_SSPMIS_RXMIS_BITS _u(0x00000004) -#define SPI_SSPMIS_RXMIS_MSB _u(2) -#define SPI_SSPMIS_RXMIS_LSB _u(2) -#define SPI_SSPMIS_RXMIS_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : SPI_SSPMIS_RTMIS -// Description : Gives the receive timeout masked interrupt state, after -// masking, of the SSPRTINTR interrupt -#define SPI_SSPMIS_RTMIS_RESET _u(0x0) -#define SPI_SSPMIS_RTMIS_BITS _u(0x00000002) -#define SPI_SSPMIS_RTMIS_MSB _u(1) -#define SPI_SSPMIS_RTMIS_LSB _u(1) -#define SPI_SSPMIS_RTMIS_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : SPI_SSPMIS_RORMIS -// Description : Gives the receive over run masked interrupt status, after -// masking, of the SSPRORINTR interrupt -#define SPI_SSPMIS_RORMIS_RESET _u(0x0) -#define SPI_SSPMIS_RORMIS_BITS _u(0x00000001) -#define SPI_SSPMIS_RORMIS_MSB _u(0) -#define SPI_SSPMIS_RORMIS_LSB _u(0) -#define SPI_SSPMIS_RORMIS_ACCESS "RO" -// ============================================================================= -// Register : SPI_SSPICR -// Description : Interrupt clear register, SSPICR on page 3-11 -#define SPI_SSPICR_OFFSET _u(0x00000020) -#define SPI_SSPICR_BITS _u(0x00000003) -#define SPI_SSPICR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : SPI_SSPICR_RTIC -// Description : Clears the SSPRTINTR interrupt -#define SPI_SSPICR_RTIC_RESET _u(0x0) -#define SPI_SSPICR_RTIC_BITS _u(0x00000002) -#define SPI_SSPICR_RTIC_MSB _u(1) -#define SPI_SSPICR_RTIC_LSB _u(1) -#define SPI_SSPICR_RTIC_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : SPI_SSPICR_RORIC -// Description : Clears the SSPRORINTR interrupt -#define SPI_SSPICR_RORIC_RESET _u(0x0) -#define SPI_SSPICR_RORIC_BITS _u(0x00000001) -#define SPI_SSPICR_RORIC_MSB _u(0) -#define SPI_SSPICR_RORIC_LSB _u(0) -#define SPI_SSPICR_RORIC_ACCESS "WC" -// ============================================================================= -// Register : SPI_SSPDMACR -// Description : DMA control register, SSPDMACR on page 3-12 -#define SPI_SSPDMACR_OFFSET _u(0x00000024) -#define SPI_SSPDMACR_BITS _u(0x00000003) -#define SPI_SSPDMACR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : SPI_SSPDMACR_TXDMAE -// Description : Transmit DMA Enable. If this bit is set to 1, DMA for the -// transmit FIFO is enabled. -#define SPI_SSPDMACR_TXDMAE_RESET _u(0x0) -#define SPI_SSPDMACR_TXDMAE_BITS _u(0x00000002) -#define SPI_SSPDMACR_TXDMAE_MSB _u(1) -#define SPI_SSPDMACR_TXDMAE_LSB _u(1) -#define SPI_SSPDMACR_TXDMAE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SPI_SSPDMACR_RXDMAE -// Description : Receive DMA Enable. If this bit is set to 1, DMA for the -// receive FIFO is enabled. -#define SPI_SSPDMACR_RXDMAE_RESET _u(0x0) -#define SPI_SSPDMACR_RXDMAE_BITS _u(0x00000001) -#define SPI_SSPDMACR_RXDMAE_MSB _u(0) -#define SPI_SSPDMACR_RXDMAE_LSB _u(0) -#define SPI_SSPDMACR_RXDMAE_ACCESS "RW" -// ============================================================================= -// Register : SPI_SSPPERIPHID0 -// Description : Peripheral identification registers, SSPPeriphID0-3 on page -// 3-13 -#define SPI_SSPPERIPHID0_OFFSET _u(0x00000fe0) -#define SPI_SSPPERIPHID0_BITS _u(0x000000ff) -#define SPI_SSPPERIPHID0_RESET _u(0x00000022) -// ----------------------------------------------------------------------------- -// Field : SPI_SSPPERIPHID0_PARTNUMBER0 -// Description : These bits read back as 0x22 -#define SPI_SSPPERIPHID0_PARTNUMBER0_RESET _u(0x22) -#define SPI_SSPPERIPHID0_PARTNUMBER0_BITS _u(0x000000ff) -#define SPI_SSPPERIPHID0_PARTNUMBER0_MSB _u(7) -#define SPI_SSPPERIPHID0_PARTNUMBER0_LSB _u(0) -#define SPI_SSPPERIPHID0_PARTNUMBER0_ACCESS "RO" -// ============================================================================= -// Register : SPI_SSPPERIPHID1 -// Description : Peripheral identification registers, SSPPeriphID0-3 on page -// 3-13 -#define SPI_SSPPERIPHID1_OFFSET _u(0x00000fe4) -#define SPI_SSPPERIPHID1_BITS _u(0x000000ff) -#define SPI_SSPPERIPHID1_RESET _u(0x00000010) -// ----------------------------------------------------------------------------- -// Field : SPI_SSPPERIPHID1_DESIGNER0 -// Description : These bits read back as 0x1 -#define SPI_SSPPERIPHID1_DESIGNER0_RESET _u(0x1) -#define SPI_SSPPERIPHID1_DESIGNER0_BITS _u(0x000000f0) -#define SPI_SSPPERIPHID1_DESIGNER0_MSB _u(7) -#define SPI_SSPPERIPHID1_DESIGNER0_LSB _u(4) -#define SPI_SSPPERIPHID1_DESIGNER0_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : SPI_SSPPERIPHID1_PARTNUMBER1 -// Description : These bits read back as 0x0 -#define SPI_SSPPERIPHID1_PARTNUMBER1_RESET _u(0x0) -#define SPI_SSPPERIPHID1_PARTNUMBER1_BITS _u(0x0000000f) -#define SPI_SSPPERIPHID1_PARTNUMBER1_MSB _u(3) -#define SPI_SSPPERIPHID1_PARTNUMBER1_LSB _u(0) -#define SPI_SSPPERIPHID1_PARTNUMBER1_ACCESS "RO" -// ============================================================================= -// Register : SPI_SSPPERIPHID2 -// Description : Peripheral identification registers, SSPPeriphID0-3 on page -// 3-13 -#define SPI_SSPPERIPHID2_OFFSET _u(0x00000fe8) -#define SPI_SSPPERIPHID2_BITS _u(0x000000ff) -#define SPI_SSPPERIPHID2_RESET _u(0x00000034) -// ----------------------------------------------------------------------------- -// Field : SPI_SSPPERIPHID2_REVISION -// Description : These bits return the peripheral revision -#define SPI_SSPPERIPHID2_REVISION_RESET _u(0x3) -#define SPI_SSPPERIPHID2_REVISION_BITS _u(0x000000f0) -#define SPI_SSPPERIPHID2_REVISION_MSB _u(7) -#define SPI_SSPPERIPHID2_REVISION_LSB _u(4) -#define SPI_SSPPERIPHID2_REVISION_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : SPI_SSPPERIPHID2_DESIGNER1 -// Description : These bits read back as 0x4 -#define SPI_SSPPERIPHID2_DESIGNER1_RESET _u(0x4) -#define SPI_SSPPERIPHID2_DESIGNER1_BITS _u(0x0000000f) -#define SPI_SSPPERIPHID2_DESIGNER1_MSB _u(3) -#define SPI_SSPPERIPHID2_DESIGNER1_LSB _u(0) -#define SPI_SSPPERIPHID2_DESIGNER1_ACCESS "RO" -// ============================================================================= -// Register : SPI_SSPPERIPHID3 -// Description : Peripheral identification registers, SSPPeriphID0-3 on page -// 3-13 -#define SPI_SSPPERIPHID3_OFFSET _u(0x00000fec) -#define SPI_SSPPERIPHID3_BITS _u(0x000000ff) -#define SPI_SSPPERIPHID3_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : SPI_SSPPERIPHID3_CONFIGURATION -// Description : These bits read back as 0x00 -#define SPI_SSPPERIPHID3_CONFIGURATION_RESET _u(0x00) -#define SPI_SSPPERIPHID3_CONFIGURATION_BITS _u(0x000000ff) -#define SPI_SSPPERIPHID3_CONFIGURATION_MSB _u(7) -#define SPI_SSPPERIPHID3_CONFIGURATION_LSB _u(0) -#define SPI_SSPPERIPHID3_CONFIGURATION_ACCESS "RO" -// ============================================================================= -// Register : SPI_SSPPCELLID0 -// Description : PrimeCell identification registers, SSPPCellID0-3 on page 3-16 -#define SPI_SSPPCELLID0_OFFSET _u(0x00000ff0) -#define SPI_SSPPCELLID0_BITS _u(0x000000ff) -#define SPI_SSPPCELLID0_RESET _u(0x0000000d) -// ----------------------------------------------------------------------------- -// Field : SPI_SSPPCELLID0_SSPPCELLID0 -// Description : These bits read back as 0x0D -#define SPI_SSPPCELLID0_SSPPCELLID0_RESET _u(0x0d) -#define SPI_SSPPCELLID0_SSPPCELLID0_BITS _u(0x000000ff) -#define SPI_SSPPCELLID0_SSPPCELLID0_MSB _u(7) -#define SPI_SSPPCELLID0_SSPPCELLID0_LSB _u(0) -#define SPI_SSPPCELLID0_SSPPCELLID0_ACCESS "RO" -// ============================================================================= -// Register : SPI_SSPPCELLID1 -// Description : PrimeCell identification registers, SSPPCellID0-3 on page 3-16 -#define SPI_SSPPCELLID1_OFFSET _u(0x00000ff4) -#define SPI_SSPPCELLID1_BITS _u(0x000000ff) -#define SPI_SSPPCELLID1_RESET _u(0x000000f0) -// ----------------------------------------------------------------------------- -// Field : SPI_SSPPCELLID1_SSPPCELLID1 -// Description : These bits read back as 0xF0 -#define SPI_SSPPCELLID1_SSPPCELLID1_RESET _u(0xf0) -#define SPI_SSPPCELLID1_SSPPCELLID1_BITS _u(0x000000ff) -#define SPI_SSPPCELLID1_SSPPCELLID1_MSB _u(7) -#define SPI_SSPPCELLID1_SSPPCELLID1_LSB _u(0) -#define SPI_SSPPCELLID1_SSPPCELLID1_ACCESS "RO" -// ============================================================================= -// Register : SPI_SSPPCELLID2 -// Description : PrimeCell identification registers, SSPPCellID0-3 on page 3-16 -#define SPI_SSPPCELLID2_OFFSET _u(0x00000ff8) -#define SPI_SSPPCELLID2_BITS _u(0x000000ff) -#define SPI_SSPPCELLID2_RESET _u(0x00000005) -// ----------------------------------------------------------------------------- -// Field : SPI_SSPPCELLID2_SSPPCELLID2 -// Description : These bits read back as 0x05 -#define SPI_SSPPCELLID2_SSPPCELLID2_RESET _u(0x05) -#define SPI_SSPPCELLID2_SSPPCELLID2_BITS _u(0x000000ff) -#define SPI_SSPPCELLID2_SSPPCELLID2_MSB _u(7) -#define SPI_SSPPCELLID2_SSPPCELLID2_LSB _u(0) -#define SPI_SSPPCELLID2_SSPPCELLID2_ACCESS "RO" -// ============================================================================= -// Register : SPI_SSPPCELLID3 -// Description : PrimeCell identification registers, SSPPCellID0-3 on page 3-16 -#define SPI_SSPPCELLID3_OFFSET _u(0x00000ffc) -#define SPI_SSPPCELLID3_BITS _u(0x000000ff) -#define SPI_SSPPCELLID3_RESET _u(0x000000b1) -// ----------------------------------------------------------------------------- -// Field : SPI_SSPPCELLID3_SSPPCELLID3 -// Description : These bits read back as 0xB1 -#define SPI_SSPPCELLID3_SSPPCELLID3_RESET _u(0xb1) -#define SPI_SSPPCELLID3_SSPPCELLID3_BITS _u(0x000000ff) -#define SPI_SSPPCELLID3_SSPPCELLID3_MSB _u(7) -#define SPI_SSPPCELLID3_SSPPCELLID3_LSB _u(0) -#define SPI_SSPPCELLID3_SSPPCELLID3_ACCESS "RO" -// ============================================================================= -#endif // _HARDWARE_REGS_SPI_H - diff --git a/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/syscfg.h b/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/syscfg.h deleted file mode 100644 index 455ebf1759..0000000000 --- a/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/syscfg.h +++ /dev/null @@ -1,279 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -// ============================================================================= -// Register block : SYSCFG -// Version : 1 -// Bus type : apb -// Description : Register block for various chip control signals -// ============================================================================= -#ifndef _HARDWARE_REGS_SYSCFG_H -#define _HARDWARE_REGS_SYSCFG_H -// ============================================================================= -// Register : SYSCFG_PROC_CONFIG -// Description : Configuration for processors -#define SYSCFG_PROC_CONFIG_OFFSET _u(0x00000000) -#define SYSCFG_PROC_CONFIG_BITS _u(0x00000003) -#define SYSCFG_PROC_CONFIG_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : SYSCFG_PROC_CONFIG_PROC1_HALTED -// Description : Indication that proc1 has halted -#define SYSCFG_PROC_CONFIG_PROC1_HALTED_RESET _u(0x0) -#define SYSCFG_PROC_CONFIG_PROC1_HALTED_BITS _u(0x00000002) -#define SYSCFG_PROC_CONFIG_PROC1_HALTED_MSB _u(1) -#define SYSCFG_PROC_CONFIG_PROC1_HALTED_LSB _u(1) -#define SYSCFG_PROC_CONFIG_PROC1_HALTED_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : SYSCFG_PROC_CONFIG_PROC0_HALTED -// Description : Indication that proc0 has halted -#define SYSCFG_PROC_CONFIG_PROC0_HALTED_RESET _u(0x0) -#define SYSCFG_PROC_CONFIG_PROC0_HALTED_BITS _u(0x00000001) -#define SYSCFG_PROC_CONFIG_PROC0_HALTED_MSB _u(0) -#define SYSCFG_PROC_CONFIG_PROC0_HALTED_LSB _u(0) -#define SYSCFG_PROC_CONFIG_PROC0_HALTED_ACCESS "RO" -// ============================================================================= -// Register : SYSCFG_PROC_IN_SYNC_BYPASS -// Description : For each bit, if 1, bypass the input synchronizer between that -// GPIO -// and the GPIO input register in the SIO. The input synchronizers -// should -// generally be unbypassed, to avoid injecting metastabilities -// into processors. -// If you're feeling brave, you can bypass to save two cycles of -// input -// latency. This register applies to GPIO 0...31. -#define SYSCFG_PROC_IN_SYNC_BYPASS_OFFSET _u(0x00000004) -#define SYSCFG_PROC_IN_SYNC_BYPASS_BITS _u(0xffffffff) -#define SYSCFG_PROC_IN_SYNC_BYPASS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : SYSCFG_PROC_IN_SYNC_BYPASS_GPIO -#define SYSCFG_PROC_IN_SYNC_BYPASS_GPIO_RESET _u(0x00000000) -#define SYSCFG_PROC_IN_SYNC_BYPASS_GPIO_BITS _u(0xffffffff) -#define SYSCFG_PROC_IN_SYNC_BYPASS_GPIO_MSB _u(31) -#define SYSCFG_PROC_IN_SYNC_BYPASS_GPIO_LSB _u(0) -#define SYSCFG_PROC_IN_SYNC_BYPASS_GPIO_ACCESS "RW" -// ============================================================================= -// Register : SYSCFG_PROC_IN_SYNC_BYPASS_HI -// Description : For each bit, if 1, bypass the input synchronizer between that -// GPIO -// and the GPIO input register in the SIO. The input synchronizers -// should -// generally be unbypassed, to avoid injecting metastabilities -// into processors. -// If you're feeling brave, you can bypass to save two cycles of -// input -// latency. This register applies to GPIO 32...47. USB GPIO 56..57 -// QSPI GPIO 58..63 -#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_OFFSET _u(0x00000008) -#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_BITS _u(0xff00ffff) -#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_SD -#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_SD_RESET _u(0x0) -#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_SD_BITS _u(0xf0000000) -#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_SD_MSB _u(31) -#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_SD_LSB _u(28) -#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_SD_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_CSN -#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_CSN_RESET _u(0x0) -#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_CSN_BITS _u(0x08000000) -#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_CSN_MSB _u(27) -#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_CSN_LSB _u(27) -#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_CSN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_SCK -#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_SCK_RESET _u(0x0) -#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_SCK_BITS _u(0x04000000) -#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_SCK_MSB _u(26) -#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_SCK_LSB _u(26) -#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_SCK_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SYSCFG_PROC_IN_SYNC_BYPASS_HI_USB_DM -#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_USB_DM_RESET _u(0x0) -#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_USB_DM_BITS _u(0x02000000) -#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_USB_DM_MSB _u(25) -#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_USB_DM_LSB _u(25) -#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_USB_DM_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SYSCFG_PROC_IN_SYNC_BYPASS_HI_USB_DP -#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_USB_DP_RESET _u(0x0) -#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_USB_DP_BITS _u(0x01000000) -#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_USB_DP_MSB _u(24) -#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_USB_DP_LSB _u(24) -#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_USB_DP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SYSCFG_PROC_IN_SYNC_BYPASS_HI_GPIO -#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_GPIO_RESET _u(0x0000) -#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_GPIO_BITS _u(0x0000ffff) -#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_GPIO_MSB _u(15) -#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_GPIO_LSB _u(0) -#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_GPIO_ACCESS "RW" -// ============================================================================= -// Register : SYSCFG_DBGFORCE -// Description : Directly control the chip SWD debug port -#define SYSCFG_DBGFORCE_OFFSET _u(0x0000000c) -#define SYSCFG_DBGFORCE_BITS _u(0x0000000f) -#define SYSCFG_DBGFORCE_RESET _u(0x00000006) -// ----------------------------------------------------------------------------- -// Field : SYSCFG_DBGFORCE_ATTACH -// Description : Attach chip debug port to syscfg controls, and disconnect it -// from external SWD pads. -#define SYSCFG_DBGFORCE_ATTACH_RESET _u(0x0) -#define SYSCFG_DBGFORCE_ATTACH_BITS _u(0x00000008) -#define SYSCFG_DBGFORCE_ATTACH_MSB _u(3) -#define SYSCFG_DBGFORCE_ATTACH_LSB _u(3) -#define SYSCFG_DBGFORCE_ATTACH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SYSCFG_DBGFORCE_SWCLK -// Description : Directly drive SWCLK, if ATTACH is set -#define SYSCFG_DBGFORCE_SWCLK_RESET _u(0x1) -#define SYSCFG_DBGFORCE_SWCLK_BITS _u(0x00000004) -#define SYSCFG_DBGFORCE_SWCLK_MSB _u(2) -#define SYSCFG_DBGFORCE_SWCLK_LSB _u(2) -#define SYSCFG_DBGFORCE_SWCLK_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SYSCFG_DBGFORCE_SWDI -// Description : Directly drive SWDIO input, if ATTACH is set -#define SYSCFG_DBGFORCE_SWDI_RESET _u(0x1) -#define SYSCFG_DBGFORCE_SWDI_BITS _u(0x00000002) -#define SYSCFG_DBGFORCE_SWDI_MSB _u(1) -#define SYSCFG_DBGFORCE_SWDI_LSB _u(1) -#define SYSCFG_DBGFORCE_SWDI_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SYSCFG_DBGFORCE_SWDO -// Description : Observe the value of SWDIO output. -#define SYSCFG_DBGFORCE_SWDO_RESET "-" -#define SYSCFG_DBGFORCE_SWDO_BITS _u(0x00000001) -#define SYSCFG_DBGFORCE_SWDO_MSB _u(0) -#define SYSCFG_DBGFORCE_SWDO_LSB _u(0) -#define SYSCFG_DBGFORCE_SWDO_ACCESS "RO" -// ============================================================================= -// Register : SYSCFG_MEMPOWERDOWN -// Description : Control PD pins to memories. -// Set high to put memories to a low power state. In this state -// the memories will retain contents but not be accessible -// Use with caution -#define SYSCFG_MEMPOWERDOWN_OFFSET _u(0x00000010) -#define SYSCFG_MEMPOWERDOWN_BITS _u(0x00001fff) -#define SYSCFG_MEMPOWERDOWN_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : SYSCFG_MEMPOWERDOWN_BOOTRAM -#define SYSCFG_MEMPOWERDOWN_BOOTRAM_RESET _u(0x0) -#define SYSCFG_MEMPOWERDOWN_BOOTRAM_BITS _u(0x00001000) -#define SYSCFG_MEMPOWERDOWN_BOOTRAM_MSB _u(12) -#define SYSCFG_MEMPOWERDOWN_BOOTRAM_LSB _u(12) -#define SYSCFG_MEMPOWERDOWN_BOOTRAM_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SYSCFG_MEMPOWERDOWN_ROM -#define SYSCFG_MEMPOWERDOWN_ROM_RESET _u(0x0) -#define SYSCFG_MEMPOWERDOWN_ROM_BITS _u(0x00000800) -#define SYSCFG_MEMPOWERDOWN_ROM_MSB _u(11) -#define SYSCFG_MEMPOWERDOWN_ROM_LSB _u(11) -#define SYSCFG_MEMPOWERDOWN_ROM_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SYSCFG_MEMPOWERDOWN_USB -#define SYSCFG_MEMPOWERDOWN_USB_RESET _u(0x0) -#define SYSCFG_MEMPOWERDOWN_USB_BITS _u(0x00000400) -#define SYSCFG_MEMPOWERDOWN_USB_MSB _u(10) -#define SYSCFG_MEMPOWERDOWN_USB_LSB _u(10) -#define SYSCFG_MEMPOWERDOWN_USB_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SYSCFG_MEMPOWERDOWN_SRAM9 -#define SYSCFG_MEMPOWERDOWN_SRAM9_RESET _u(0x0) -#define SYSCFG_MEMPOWERDOWN_SRAM9_BITS _u(0x00000200) -#define SYSCFG_MEMPOWERDOWN_SRAM9_MSB _u(9) -#define SYSCFG_MEMPOWERDOWN_SRAM9_LSB _u(9) -#define SYSCFG_MEMPOWERDOWN_SRAM9_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SYSCFG_MEMPOWERDOWN_SRAM8 -#define SYSCFG_MEMPOWERDOWN_SRAM8_RESET _u(0x0) -#define SYSCFG_MEMPOWERDOWN_SRAM8_BITS _u(0x00000100) -#define SYSCFG_MEMPOWERDOWN_SRAM8_MSB _u(8) -#define SYSCFG_MEMPOWERDOWN_SRAM8_LSB _u(8) -#define SYSCFG_MEMPOWERDOWN_SRAM8_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SYSCFG_MEMPOWERDOWN_SRAM7 -#define SYSCFG_MEMPOWERDOWN_SRAM7_RESET _u(0x0) -#define SYSCFG_MEMPOWERDOWN_SRAM7_BITS _u(0x00000080) -#define SYSCFG_MEMPOWERDOWN_SRAM7_MSB _u(7) -#define SYSCFG_MEMPOWERDOWN_SRAM7_LSB _u(7) -#define SYSCFG_MEMPOWERDOWN_SRAM7_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SYSCFG_MEMPOWERDOWN_SRAM6 -#define SYSCFG_MEMPOWERDOWN_SRAM6_RESET _u(0x0) -#define SYSCFG_MEMPOWERDOWN_SRAM6_BITS _u(0x00000040) -#define SYSCFG_MEMPOWERDOWN_SRAM6_MSB _u(6) -#define SYSCFG_MEMPOWERDOWN_SRAM6_LSB _u(6) -#define SYSCFG_MEMPOWERDOWN_SRAM6_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SYSCFG_MEMPOWERDOWN_SRAM5 -#define SYSCFG_MEMPOWERDOWN_SRAM5_RESET _u(0x0) -#define SYSCFG_MEMPOWERDOWN_SRAM5_BITS _u(0x00000020) -#define SYSCFG_MEMPOWERDOWN_SRAM5_MSB _u(5) -#define SYSCFG_MEMPOWERDOWN_SRAM5_LSB _u(5) -#define SYSCFG_MEMPOWERDOWN_SRAM5_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SYSCFG_MEMPOWERDOWN_SRAM4 -#define SYSCFG_MEMPOWERDOWN_SRAM4_RESET _u(0x0) -#define SYSCFG_MEMPOWERDOWN_SRAM4_BITS _u(0x00000010) -#define SYSCFG_MEMPOWERDOWN_SRAM4_MSB _u(4) -#define SYSCFG_MEMPOWERDOWN_SRAM4_LSB _u(4) -#define SYSCFG_MEMPOWERDOWN_SRAM4_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SYSCFG_MEMPOWERDOWN_SRAM3 -#define SYSCFG_MEMPOWERDOWN_SRAM3_RESET _u(0x0) -#define SYSCFG_MEMPOWERDOWN_SRAM3_BITS _u(0x00000008) -#define SYSCFG_MEMPOWERDOWN_SRAM3_MSB _u(3) -#define SYSCFG_MEMPOWERDOWN_SRAM3_LSB _u(3) -#define SYSCFG_MEMPOWERDOWN_SRAM3_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SYSCFG_MEMPOWERDOWN_SRAM2 -#define SYSCFG_MEMPOWERDOWN_SRAM2_RESET _u(0x0) -#define SYSCFG_MEMPOWERDOWN_SRAM2_BITS _u(0x00000004) -#define SYSCFG_MEMPOWERDOWN_SRAM2_MSB _u(2) -#define SYSCFG_MEMPOWERDOWN_SRAM2_LSB _u(2) -#define SYSCFG_MEMPOWERDOWN_SRAM2_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SYSCFG_MEMPOWERDOWN_SRAM1 -#define SYSCFG_MEMPOWERDOWN_SRAM1_RESET _u(0x0) -#define SYSCFG_MEMPOWERDOWN_SRAM1_BITS _u(0x00000002) -#define SYSCFG_MEMPOWERDOWN_SRAM1_MSB _u(1) -#define SYSCFG_MEMPOWERDOWN_SRAM1_LSB _u(1) -#define SYSCFG_MEMPOWERDOWN_SRAM1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : SYSCFG_MEMPOWERDOWN_SRAM0 -#define SYSCFG_MEMPOWERDOWN_SRAM0_RESET _u(0x0) -#define SYSCFG_MEMPOWERDOWN_SRAM0_BITS _u(0x00000001) -#define SYSCFG_MEMPOWERDOWN_SRAM0_MSB _u(0) -#define SYSCFG_MEMPOWERDOWN_SRAM0_LSB _u(0) -#define SYSCFG_MEMPOWERDOWN_SRAM0_ACCESS "RW" -// ============================================================================= -// Register : SYSCFG_AUXCTRL -// Description : Auxiliary system control register -// * Bits 7:2: Reserved -// -// * Bit 1: When clear, the LPOSC output is XORed into the TRNG -// ROSC output as an additional, uncorrelated entropy source. When -// set, this behaviour is disabled. -// -// * Bit 0: Force POWMAN clock to switch to LPOSC, by asserting -// its WDRESET input. This must be set before initiating a -// watchdog reset of the RSM from a stage that includes CLOCKS, if -// POWMAN is running from clk_ref at the point that the watchdog -// reset takes place. Otherwise, the short pulse generated on -// clk_ref by the reset of the CLOCKS block may affect POWMAN -// register state. -#define SYSCFG_AUXCTRL_OFFSET _u(0x00000014) -#define SYSCFG_AUXCTRL_BITS _u(0x000000ff) -#define SYSCFG_AUXCTRL_RESET _u(0x00000000) -#define SYSCFG_AUXCTRL_MSB _u(7) -#define SYSCFG_AUXCTRL_LSB _u(0) -#define SYSCFG_AUXCTRL_ACCESS "RW" -// ============================================================================= -#endif // _HARDWARE_REGS_SYSCFG_H - diff --git a/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/sysinfo.h b/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/sysinfo.h deleted file mode 100644 index a6409bc2d2..0000000000 --- a/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/sysinfo.h +++ /dev/null @@ -1,111 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -// ============================================================================= -// Register block : SYSINFO -// Version : 1 -// Bus type : apb -// ============================================================================= -#ifndef _HARDWARE_REGS_SYSINFO_H -#define _HARDWARE_REGS_SYSINFO_H -// ============================================================================= -// Register : SYSINFO_CHIP_ID -// Description : JEDEC JEP-106 compliant chip identifier. -#define SYSINFO_CHIP_ID_OFFSET _u(0x00000000) -#define SYSINFO_CHIP_ID_BITS _u(0xffffffff) -#define SYSINFO_CHIP_ID_RESET _u(0x00000001) -// ----------------------------------------------------------------------------- -// Field : SYSINFO_CHIP_ID_REVISION -#define SYSINFO_CHIP_ID_REVISION_RESET "-" -#define SYSINFO_CHIP_ID_REVISION_BITS _u(0xf0000000) -#define SYSINFO_CHIP_ID_REVISION_MSB _u(31) -#define SYSINFO_CHIP_ID_REVISION_LSB _u(28) -#define SYSINFO_CHIP_ID_REVISION_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : SYSINFO_CHIP_ID_PART -#define SYSINFO_CHIP_ID_PART_RESET "-" -#define SYSINFO_CHIP_ID_PART_BITS _u(0x0ffff000) -#define SYSINFO_CHIP_ID_PART_MSB _u(27) -#define SYSINFO_CHIP_ID_PART_LSB _u(12) -#define SYSINFO_CHIP_ID_PART_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : SYSINFO_CHIP_ID_MANUFACTURER -#define SYSINFO_CHIP_ID_MANUFACTURER_RESET "-" -#define SYSINFO_CHIP_ID_MANUFACTURER_BITS _u(0x00000ffe) -#define SYSINFO_CHIP_ID_MANUFACTURER_MSB _u(11) -#define SYSINFO_CHIP_ID_MANUFACTURER_LSB _u(1) -#define SYSINFO_CHIP_ID_MANUFACTURER_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : SYSINFO_CHIP_ID_STOP_BIT -#define SYSINFO_CHIP_ID_STOP_BIT_RESET _u(0x1) -#define SYSINFO_CHIP_ID_STOP_BIT_BITS _u(0x00000001) -#define SYSINFO_CHIP_ID_STOP_BIT_MSB _u(0) -#define SYSINFO_CHIP_ID_STOP_BIT_LSB _u(0) -#define SYSINFO_CHIP_ID_STOP_BIT_ACCESS "RO" -// ============================================================================= -// Register : SYSINFO_PACKAGE_SEL -#define SYSINFO_PACKAGE_SEL_OFFSET _u(0x00000004) -#define SYSINFO_PACKAGE_SEL_BITS _u(0x00000001) -#define SYSINFO_PACKAGE_SEL_RESET _u(0x00000000) -#define SYSINFO_PACKAGE_SEL_MSB _u(0) -#define SYSINFO_PACKAGE_SEL_LSB _u(0) -#define SYSINFO_PACKAGE_SEL_ACCESS "RO" -// ============================================================================= -// Register : SYSINFO_PLATFORM -// Description : Platform register. Allows software to know what environment it -// is running in during pre-production development. Post- -// production, the PLATFORM is always ASIC, non-SIM. -#define SYSINFO_PLATFORM_OFFSET _u(0x00000008) -#define SYSINFO_PLATFORM_BITS _u(0x0000001f) -#define SYSINFO_PLATFORM_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : SYSINFO_PLATFORM_GATESIM -#define SYSINFO_PLATFORM_GATESIM_RESET "-" -#define SYSINFO_PLATFORM_GATESIM_BITS _u(0x00000010) -#define SYSINFO_PLATFORM_GATESIM_MSB _u(4) -#define SYSINFO_PLATFORM_GATESIM_LSB _u(4) -#define SYSINFO_PLATFORM_GATESIM_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : SYSINFO_PLATFORM_BATCHSIM -#define SYSINFO_PLATFORM_BATCHSIM_RESET "-" -#define SYSINFO_PLATFORM_BATCHSIM_BITS _u(0x00000008) -#define SYSINFO_PLATFORM_BATCHSIM_MSB _u(3) -#define SYSINFO_PLATFORM_BATCHSIM_LSB _u(3) -#define SYSINFO_PLATFORM_BATCHSIM_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : SYSINFO_PLATFORM_HDLSIM -#define SYSINFO_PLATFORM_HDLSIM_RESET "-" -#define SYSINFO_PLATFORM_HDLSIM_BITS _u(0x00000004) -#define SYSINFO_PLATFORM_HDLSIM_MSB _u(2) -#define SYSINFO_PLATFORM_HDLSIM_LSB _u(2) -#define SYSINFO_PLATFORM_HDLSIM_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : SYSINFO_PLATFORM_ASIC -#define SYSINFO_PLATFORM_ASIC_RESET "-" -#define SYSINFO_PLATFORM_ASIC_BITS _u(0x00000002) -#define SYSINFO_PLATFORM_ASIC_MSB _u(1) -#define SYSINFO_PLATFORM_ASIC_LSB _u(1) -#define SYSINFO_PLATFORM_ASIC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : SYSINFO_PLATFORM_FPGA -#define SYSINFO_PLATFORM_FPGA_RESET "-" -#define SYSINFO_PLATFORM_FPGA_BITS _u(0x00000001) -#define SYSINFO_PLATFORM_FPGA_MSB _u(0) -#define SYSINFO_PLATFORM_FPGA_LSB _u(0) -#define SYSINFO_PLATFORM_FPGA_ACCESS "RO" -// ============================================================================= -// Register : SYSINFO_GITREF_RP2350 -// Description : Git hash of the chip source. Used to identify chip version. -#define SYSINFO_GITREF_RP2350_OFFSET _u(0x00000014) -#define SYSINFO_GITREF_RP2350_BITS _u(0xffffffff) -#define SYSINFO_GITREF_RP2350_RESET "-" -#define SYSINFO_GITREF_RP2350_MSB _u(31) -#define SYSINFO_GITREF_RP2350_LSB _u(0) -#define SYSINFO_GITREF_RP2350_ACCESS "RO" -// ============================================================================= -#endif // _HARDWARE_REGS_SYSINFO_H - diff --git a/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/tbman.h b/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/tbman.h deleted file mode 100644 index 59cf2d1bf1..0000000000 --- a/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/tbman.h +++ /dev/null @@ -1,48 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -// ============================================================================= -// Register block : TBMAN -// Version : 1 -// Bus type : apb -// Description : For managing simulation testbenches -// ============================================================================= -#ifndef _HARDWARE_REGS_TBMAN_H -#define _HARDWARE_REGS_TBMAN_H -// ============================================================================= -// Register : TBMAN_PLATFORM -// Description : Indicates the type of platform in use -#define TBMAN_PLATFORM_OFFSET _u(0x00000000) -#define TBMAN_PLATFORM_BITS _u(0x00000007) -#define TBMAN_PLATFORM_RESET _u(0x00000001) -// ----------------------------------------------------------------------------- -// Field : TBMAN_PLATFORM_HDLSIM -// Description : Indicates the platform is a simulation -#define TBMAN_PLATFORM_HDLSIM_RESET _u(0x0) -#define TBMAN_PLATFORM_HDLSIM_BITS _u(0x00000004) -#define TBMAN_PLATFORM_HDLSIM_MSB _u(2) -#define TBMAN_PLATFORM_HDLSIM_LSB _u(2) -#define TBMAN_PLATFORM_HDLSIM_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : TBMAN_PLATFORM_FPGA -// Description : Indicates the platform is an FPGA -#define TBMAN_PLATFORM_FPGA_RESET _u(0x0) -#define TBMAN_PLATFORM_FPGA_BITS _u(0x00000002) -#define TBMAN_PLATFORM_FPGA_MSB _u(1) -#define TBMAN_PLATFORM_FPGA_LSB _u(1) -#define TBMAN_PLATFORM_FPGA_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : TBMAN_PLATFORM_ASIC -// Description : Indicates the platform is an ASIC -#define TBMAN_PLATFORM_ASIC_RESET _u(0x1) -#define TBMAN_PLATFORM_ASIC_BITS _u(0x00000001) -#define TBMAN_PLATFORM_ASIC_MSB _u(0) -#define TBMAN_PLATFORM_ASIC_LSB _u(0) -#define TBMAN_PLATFORM_ASIC_ACCESS "RO" -// ============================================================================= -#endif // _HARDWARE_REGS_TBMAN_H - diff --git a/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/ticks.h b/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/ticks.h deleted file mode 100644 index 79e13523dc..0000000000 --- a/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/ticks.h +++ /dev/null @@ -1,275 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -// ============================================================================= -// Register block : TICKS -// Version : 1 -// Bus type : apb -// ============================================================================= -#ifndef _HARDWARE_REGS_TICKS_H -#define _HARDWARE_REGS_TICKS_H -// ============================================================================= -// Register : TICKS_PROC0_CTRL -// Description : Controls the tick generator -#define TICKS_PROC0_CTRL_OFFSET _u(0x00000000) -#define TICKS_PROC0_CTRL_BITS _u(0x00000003) -#define TICKS_PROC0_CTRL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : TICKS_PROC0_CTRL_RUNNING -// Description : Is the tick generator running? -#define TICKS_PROC0_CTRL_RUNNING_RESET "-" -#define TICKS_PROC0_CTRL_RUNNING_BITS _u(0x00000002) -#define TICKS_PROC0_CTRL_RUNNING_MSB _u(1) -#define TICKS_PROC0_CTRL_RUNNING_LSB _u(1) -#define TICKS_PROC0_CTRL_RUNNING_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : TICKS_PROC0_CTRL_ENABLE -// Description : start / stop tick generation -#define TICKS_PROC0_CTRL_ENABLE_RESET _u(0x0) -#define TICKS_PROC0_CTRL_ENABLE_BITS _u(0x00000001) -#define TICKS_PROC0_CTRL_ENABLE_MSB _u(0) -#define TICKS_PROC0_CTRL_ENABLE_LSB _u(0) -#define TICKS_PROC0_CTRL_ENABLE_ACCESS "RW" -// ============================================================================= -// Register : TICKS_PROC0_CYCLES -// Description : None -// Total number of clk_tick cycles before the next tick. -#define TICKS_PROC0_CYCLES_OFFSET _u(0x00000004) -#define TICKS_PROC0_CYCLES_BITS _u(0x000001ff) -#define TICKS_PROC0_CYCLES_RESET _u(0x00000000) -#define TICKS_PROC0_CYCLES_MSB _u(8) -#define TICKS_PROC0_CYCLES_LSB _u(0) -#define TICKS_PROC0_CYCLES_ACCESS "RW" -// ============================================================================= -// Register : TICKS_PROC0_COUNT -// Description : None -// Count down timer: the remaining number clk_tick cycles before -// the next tick is generated. -#define TICKS_PROC0_COUNT_OFFSET _u(0x00000008) -#define TICKS_PROC0_COUNT_BITS _u(0x000001ff) -#define TICKS_PROC0_COUNT_RESET "-" -#define TICKS_PROC0_COUNT_MSB _u(8) -#define TICKS_PROC0_COUNT_LSB _u(0) -#define TICKS_PROC0_COUNT_ACCESS "RO" -// ============================================================================= -// Register : TICKS_PROC1_CTRL -// Description : Controls the tick generator -#define TICKS_PROC1_CTRL_OFFSET _u(0x0000000c) -#define TICKS_PROC1_CTRL_BITS _u(0x00000003) -#define TICKS_PROC1_CTRL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : TICKS_PROC1_CTRL_RUNNING -// Description : Is the tick generator running? -#define TICKS_PROC1_CTRL_RUNNING_RESET "-" -#define TICKS_PROC1_CTRL_RUNNING_BITS _u(0x00000002) -#define TICKS_PROC1_CTRL_RUNNING_MSB _u(1) -#define TICKS_PROC1_CTRL_RUNNING_LSB _u(1) -#define TICKS_PROC1_CTRL_RUNNING_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : TICKS_PROC1_CTRL_ENABLE -// Description : start / stop tick generation -#define TICKS_PROC1_CTRL_ENABLE_RESET _u(0x0) -#define TICKS_PROC1_CTRL_ENABLE_BITS _u(0x00000001) -#define TICKS_PROC1_CTRL_ENABLE_MSB _u(0) -#define TICKS_PROC1_CTRL_ENABLE_LSB _u(0) -#define TICKS_PROC1_CTRL_ENABLE_ACCESS "RW" -// ============================================================================= -// Register : TICKS_PROC1_CYCLES -// Description : None -// Total number of clk_tick cycles before the next tick. -#define TICKS_PROC1_CYCLES_OFFSET _u(0x00000010) -#define TICKS_PROC1_CYCLES_BITS _u(0x000001ff) -#define TICKS_PROC1_CYCLES_RESET _u(0x00000000) -#define TICKS_PROC1_CYCLES_MSB _u(8) -#define TICKS_PROC1_CYCLES_LSB _u(0) -#define TICKS_PROC1_CYCLES_ACCESS "RW" -// ============================================================================= -// Register : TICKS_PROC1_COUNT -// Description : None -// Count down timer: the remaining number clk_tick cycles before -// the next tick is generated. -#define TICKS_PROC1_COUNT_OFFSET _u(0x00000014) -#define TICKS_PROC1_COUNT_BITS _u(0x000001ff) -#define TICKS_PROC1_COUNT_RESET "-" -#define TICKS_PROC1_COUNT_MSB _u(8) -#define TICKS_PROC1_COUNT_LSB _u(0) -#define TICKS_PROC1_COUNT_ACCESS "RO" -// ============================================================================= -// Register : TICKS_TIMER0_CTRL -// Description : Controls the tick generator -#define TICKS_TIMER0_CTRL_OFFSET _u(0x00000018) -#define TICKS_TIMER0_CTRL_BITS _u(0x00000003) -#define TICKS_TIMER0_CTRL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : TICKS_TIMER0_CTRL_RUNNING -// Description : Is the tick generator running? -#define TICKS_TIMER0_CTRL_RUNNING_RESET "-" -#define TICKS_TIMER0_CTRL_RUNNING_BITS _u(0x00000002) -#define TICKS_TIMER0_CTRL_RUNNING_MSB _u(1) -#define TICKS_TIMER0_CTRL_RUNNING_LSB _u(1) -#define TICKS_TIMER0_CTRL_RUNNING_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : TICKS_TIMER0_CTRL_ENABLE -// Description : start / stop tick generation -#define TICKS_TIMER0_CTRL_ENABLE_RESET _u(0x0) -#define TICKS_TIMER0_CTRL_ENABLE_BITS _u(0x00000001) -#define TICKS_TIMER0_CTRL_ENABLE_MSB _u(0) -#define TICKS_TIMER0_CTRL_ENABLE_LSB _u(0) -#define TICKS_TIMER0_CTRL_ENABLE_ACCESS "RW" -// ============================================================================= -// Register : TICKS_TIMER0_CYCLES -// Description : None -// Total number of clk_tick cycles before the next tick. -#define TICKS_TIMER0_CYCLES_OFFSET _u(0x0000001c) -#define TICKS_TIMER0_CYCLES_BITS _u(0x000001ff) -#define TICKS_TIMER0_CYCLES_RESET _u(0x00000000) -#define TICKS_TIMER0_CYCLES_MSB _u(8) -#define TICKS_TIMER0_CYCLES_LSB _u(0) -#define TICKS_TIMER0_CYCLES_ACCESS "RW" -// ============================================================================= -// Register : TICKS_TIMER0_COUNT -// Description : None -// Count down timer: the remaining number clk_tick cycles before -// the next tick is generated. -#define TICKS_TIMER0_COUNT_OFFSET _u(0x00000020) -#define TICKS_TIMER0_COUNT_BITS _u(0x000001ff) -#define TICKS_TIMER0_COUNT_RESET "-" -#define TICKS_TIMER0_COUNT_MSB _u(8) -#define TICKS_TIMER0_COUNT_LSB _u(0) -#define TICKS_TIMER0_COUNT_ACCESS "RO" -// ============================================================================= -// Register : TICKS_TIMER1_CTRL -// Description : Controls the tick generator -#define TICKS_TIMER1_CTRL_OFFSET _u(0x00000024) -#define TICKS_TIMER1_CTRL_BITS _u(0x00000003) -#define TICKS_TIMER1_CTRL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : TICKS_TIMER1_CTRL_RUNNING -// Description : Is the tick generator running? -#define TICKS_TIMER1_CTRL_RUNNING_RESET "-" -#define TICKS_TIMER1_CTRL_RUNNING_BITS _u(0x00000002) -#define TICKS_TIMER1_CTRL_RUNNING_MSB _u(1) -#define TICKS_TIMER1_CTRL_RUNNING_LSB _u(1) -#define TICKS_TIMER1_CTRL_RUNNING_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : TICKS_TIMER1_CTRL_ENABLE -// Description : start / stop tick generation -#define TICKS_TIMER1_CTRL_ENABLE_RESET _u(0x0) -#define TICKS_TIMER1_CTRL_ENABLE_BITS _u(0x00000001) -#define TICKS_TIMER1_CTRL_ENABLE_MSB _u(0) -#define TICKS_TIMER1_CTRL_ENABLE_LSB _u(0) -#define TICKS_TIMER1_CTRL_ENABLE_ACCESS "RW" -// ============================================================================= -// Register : TICKS_TIMER1_CYCLES -// Description : None -// Total number of clk_tick cycles before the next tick. -#define TICKS_TIMER1_CYCLES_OFFSET _u(0x00000028) -#define TICKS_TIMER1_CYCLES_BITS _u(0x000001ff) -#define TICKS_TIMER1_CYCLES_RESET _u(0x00000000) -#define TICKS_TIMER1_CYCLES_MSB _u(8) -#define TICKS_TIMER1_CYCLES_LSB _u(0) -#define TICKS_TIMER1_CYCLES_ACCESS "RW" -// ============================================================================= -// Register : TICKS_TIMER1_COUNT -// Description : None -// Count down timer: the remaining number clk_tick cycles before -// the next tick is generated. -#define TICKS_TIMER1_COUNT_OFFSET _u(0x0000002c) -#define TICKS_TIMER1_COUNT_BITS _u(0x000001ff) -#define TICKS_TIMER1_COUNT_RESET "-" -#define TICKS_TIMER1_COUNT_MSB _u(8) -#define TICKS_TIMER1_COUNT_LSB _u(0) -#define TICKS_TIMER1_COUNT_ACCESS "RO" -// ============================================================================= -// Register : TICKS_WATCHDOG_CTRL -// Description : Controls the tick generator -#define TICKS_WATCHDOG_CTRL_OFFSET _u(0x00000030) -#define TICKS_WATCHDOG_CTRL_BITS _u(0x00000003) -#define TICKS_WATCHDOG_CTRL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : TICKS_WATCHDOG_CTRL_RUNNING -// Description : Is the tick generator running? -#define TICKS_WATCHDOG_CTRL_RUNNING_RESET "-" -#define TICKS_WATCHDOG_CTRL_RUNNING_BITS _u(0x00000002) -#define TICKS_WATCHDOG_CTRL_RUNNING_MSB _u(1) -#define TICKS_WATCHDOG_CTRL_RUNNING_LSB _u(1) -#define TICKS_WATCHDOG_CTRL_RUNNING_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : TICKS_WATCHDOG_CTRL_ENABLE -// Description : start / stop tick generation -#define TICKS_WATCHDOG_CTRL_ENABLE_RESET _u(0x0) -#define TICKS_WATCHDOG_CTRL_ENABLE_BITS _u(0x00000001) -#define TICKS_WATCHDOG_CTRL_ENABLE_MSB _u(0) -#define TICKS_WATCHDOG_CTRL_ENABLE_LSB _u(0) -#define TICKS_WATCHDOG_CTRL_ENABLE_ACCESS "RW" -// ============================================================================= -// Register : TICKS_WATCHDOG_CYCLES -// Description : None -// Total number of clk_tick cycles before the next tick. -#define TICKS_WATCHDOG_CYCLES_OFFSET _u(0x00000034) -#define TICKS_WATCHDOG_CYCLES_BITS _u(0x000001ff) -#define TICKS_WATCHDOG_CYCLES_RESET _u(0x00000000) -#define TICKS_WATCHDOG_CYCLES_MSB _u(8) -#define TICKS_WATCHDOG_CYCLES_LSB _u(0) -#define TICKS_WATCHDOG_CYCLES_ACCESS "RW" -// ============================================================================= -// Register : TICKS_WATCHDOG_COUNT -// Description : None -// Count down timer: the remaining number clk_tick cycles before -// the next tick is generated. -#define TICKS_WATCHDOG_COUNT_OFFSET _u(0x00000038) -#define TICKS_WATCHDOG_COUNT_BITS _u(0x000001ff) -#define TICKS_WATCHDOG_COUNT_RESET "-" -#define TICKS_WATCHDOG_COUNT_MSB _u(8) -#define TICKS_WATCHDOG_COUNT_LSB _u(0) -#define TICKS_WATCHDOG_COUNT_ACCESS "RO" -// ============================================================================= -// Register : TICKS_RISCV_CTRL -// Description : Controls the tick generator -#define TICKS_RISCV_CTRL_OFFSET _u(0x0000003c) -#define TICKS_RISCV_CTRL_BITS _u(0x00000003) -#define TICKS_RISCV_CTRL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : TICKS_RISCV_CTRL_RUNNING -// Description : Is the tick generator running? -#define TICKS_RISCV_CTRL_RUNNING_RESET "-" -#define TICKS_RISCV_CTRL_RUNNING_BITS _u(0x00000002) -#define TICKS_RISCV_CTRL_RUNNING_MSB _u(1) -#define TICKS_RISCV_CTRL_RUNNING_LSB _u(1) -#define TICKS_RISCV_CTRL_RUNNING_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : TICKS_RISCV_CTRL_ENABLE -// Description : start / stop tick generation -#define TICKS_RISCV_CTRL_ENABLE_RESET _u(0x0) -#define TICKS_RISCV_CTRL_ENABLE_BITS _u(0x00000001) -#define TICKS_RISCV_CTRL_ENABLE_MSB _u(0) -#define TICKS_RISCV_CTRL_ENABLE_LSB _u(0) -#define TICKS_RISCV_CTRL_ENABLE_ACCESS "RW" -// ============================================================================= -// Register : TICKS_RISCV_CYCLES -// Description : None -// Total number of clk_tick cycles before the next tick. -#define TICKS_RISCV_CYCLES_OFFSET _u(0x00000040) -#define TICKS_RISCV_CYCLES_BITS _u(0x000001ff) -#define TICKS_RISCV_CYCLES_RESET _u(0x00000000) -#define TICKS_RISCV_CYCLES_MSB _u(8) -#define TICKS_RISCV_CYCLES_LSB _u(0) -#define TICKS_RISCV_CYCLES_ACCESS "RW" -// ============================================================================= -// Register : TICKS_RISCV_COUNT -// Description : None -// Count down timer: the remaining number clk_tick cycles before -// the next tick is generated. -#define TICKS_RISCV_COUNT_OFFSET _u(0x00000044) -#define TICKS_RISCV_COUNT_BITS _u(0x000001ff) -#define TICKS_RISCV_COUNT_RESET "-" -#define TICKS_RISCV_COUNT_MSB _u(8) -#define TICKS_RISCV_COUNT_LSB _u(0) -#define TICKS_RISCV_COUNT_ACCESS "RO" -// ============================================================================= -#endif // _HARDWARE_REGS_TICKS_H - diff --git a/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/timer.h b/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/timer.h deleted file mode 100644 index c5f4d05b2c..0000000000 --- a/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/timer.h +++ /dev/null @@ -1,346 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -// ============================================================================= -// Register block : TIMER -// Version : 1 -// Bus type : apb -// Description : Controls time and alarms -// -// time is a 64 bit value indicating the time since power-on -// -// timeh is the top 32 bits of time & timel is the bottom 32 -// bits to change time write to timelw before timehw to read -// time read from timelr before timehr -// -// An alarm is set by setting alarm_enable and writing to the -// corresponding alarm register When an alarm is pending, the -// corresponding alarm_running signal will be high An alarm can -// be cancelled before it has finished by clearing the -// alarm_enable When an alarm fires, the corresponding -// alarm_irq is set and alarm_running is cleared To clear the -// interrupt write a 1 to the corresponding alarm_irq The timer -// can be locked to prevent writing -// ============================================================================= -#ifndef _HARDWARE_REGS_TIMER_H -#define _HARDWARE_REGS_TIMER_H -// ============================================================================= -// Register : TIMER_TIMEHW -// Description : Write to bits 63:32 of time always write timelw before timehw -#define TIMER_TIMEHW_OFFSET _u(0x00000000) -#define TIMER_TIMEHW_BITS _u(0xffffffff) -#define TIMER_TIMEHW_RESET _u(0x00000000) -#define TIMER_TIMEHW_MSB _u(31) -#define TIMER_TIMEHW_LSB _u(0) -#define TIMER_TIMEHW_ACCESS "WF" -// ============================================================================= -// Register : TIMER_TIMELW -// Description : Write to bits 31:0 of time writes do not get copied to time -// until timehw is written -#define TIMER_TIMELW_OFFSET _u(0x00000004) -#define TIMER_TIMELW_BITS _u(0xffffffff) -#define TIMER_TIMELW_RESET _u(0x00000000) -#define TIMER_TIMELW_MSB _u(31) -#define TIMER_TIMELW_LSB _u(0) -#define TIMER_TIMELW_ACCESS "WF" -// ============================================================================= -// Register : TIMER_TIMEHR -// Description : Read from bits 63:32 of time always read timelr before timehr -#define TIMER_TIMEHR_OFFSET _u(0x00000008) -#define TIMER_TIMEHR_BITS _u(0xffffffff) -#define TIMER_TIMEHR_RESET _u(0x00000000) -#define TIMER_TIMEHR_MSB _u(31) -#define TIMER_TIMEHR_LSB _u(0) -#define TIMER_TIMEHR_ACCESS "RO" -// ============================================================================= -// Register : TIMER_TIMELR -// Description : Read from bits 31:0 of time -#define TIMER_TIMELR_OFFSET _u(0x0000000c) -#define TIMER_TIMELR_BITS _u(0xffffffff) -#define TIMER_TIMELR_RESET _u(0x00000000) -#define TIMER_TIMELR_MSB _u(31) -#define TIMER_TIMELR_LSB _u(0) -#define TIMER_TIMELR_ACCESS "RO" -// ============================================================================= -// Register : TIMER_ALARM0 -// Description : Arm alarm 0, and configure the time it will fire. Once armed, -// the alarm fires when TIMER_ALARM0 == TIMELR. The alarm will -// disarm itself once it fires, and can be disarmed early using -// the ARMED status register. -#define TIMER_ALARM0_OFFSET _u(0x00000010) -#define TIMER_ALARM0_BITS _u(0xffffffff) -#define TIMER_ALARM0_RESET _u(0x00000000) -#define TIMER_ALARM0_MSB _u(31) -#define TIMER_ALARM0_LSB _u(0) -#define TIMER_ALARM0_ACCESS "RW" -// ============================================================================= -// Register : TIMER_ALARM1 -// Description : Arm alarm 1, and configure the time it will fire. Once armed, -// the alarm fires when TIMER_ALARM1 == TIMELR. The alarm will -// disarm itself once it fires, and can be disarmed early using -// the ARMED status register. -#define TIMER_ALARM1_OFFSET _u(0x00000014) -#define TIMER_ALARM1_BITS _u(0xffffffff) -#define TIMER_ALARM1_RESET _u(0x00000000) -#define TIMER_ALARM1_MSB _u(31) -#define TIMER_ALARM1_LSB _u(0) -#define TIMER_ALARM1_ACCESS "RW" -// ============================================================================= -// Register : TIMER_ALARM2 -// Description : Arm alarm 2, and configure the time it will fire. Once armed, -// the alarm fires when TIMER_ALARM2 == TIMELR. The alarm will -// disarm itself once it fires, and can be disarmed early using -// the ARMED status register. -#define TIMER_ALARM2_OFFSET _u(0x00000018) -#define TIMER_ALARM2_BITS _u(0xffffffff) -#define TIMER_ALARM2_RESET _u(0x00000000) -#define TIMER_ALARM2_MSB _u(31) -#define TIMER_ALARM2_LSB _u(0) -#define TIMER_ALARM2_ACCESS "RW" -// ============================================================================= -// Register : TIMER_ALARM3 -// Description : Arm alarm 3, and configure the time it will fire. Once armed, -// the alarm fires when TIMER_ALARM3 == TIMELR. The alarm will -// disarm itself once it fires, and can be disarmed early using -// the ARMED status register. -#define TIMER_ALARM3_OFFSET _u(0x0000001c) -#define TIMER_ALARM3_BITS _u(0xffffffff) -#define TIMER_ALARM3_RESET _u(0x00000000) -#define TIMER_ALARM3_MSB _u(31) -#define TIMER_ALARM3_LSB _u(0) -#define TIMER_ALARM3_ACCESS "RW" -// ============================================================================= -// Register : TIMER_ARMED -// Description : Indicates the armed/disarmed status of each alarm. A write to -// the corresponding ALARMx register arms the alarm. Alarms -// automatically disarm upon firing, but writing ones here will -// disarm immediately without waiting to fire. -#define TIMER_ARMED_OFFSET _u(0x00000020) -#define TIMER_ARMED_BITS _u(0x0000000f) -#define TIMER_ARMED_RESET _u(0x00000000) -#define TIMER_ARMED_MSB _u(3) -#define TIMER_ARMED_LSB _u(0) -#define TIMER_ARMED_ACCESS "WC" -// ============================================================================= -// Register : TIMER_TIMERAWH -// Description : Raw read from bits 63:32 of time (no side effects) -#define TIMER_TIMERAWH_OFFSET _u(0x00000024) -#define TIMER_TIMERAWH_BITS _u(0xffffffff) -#define TIMER_TIMERAWH_RESET _u(0x00000000) -#define TIMER_TIMERAWH_MSB _u(31) -#define TIMER_TIMERAWH_LSB _u(0) -#define TIMER_TIMERAWH_ACCESS "RO" -// ============================================================================= -// Register : TIMER_TIMERAWL -// Description : Raw read from bits 31:0 of time (no side effects) -#define TIMER_TIMERAWL_OFFSET _u(0x00000028) -#define TIMER_TIMERAWL_BITS _u(0xffffffff) -#define TIMER_TIMERAWL_RESET _u(0x00000000) -#define TIMER_TIMERAWL_MSB _u(31) -#define TIMER_TIMERAWL_LSB _u(0) -#define TIMER_TIMERAWL_ACCESS "RO" -// ============================================================================= -// Register : TIMER_DBGPAUSE -// Description : Set bits high to enable pause when the corresponding debug -// ports are active -#define TIMER_DBGPAUSE_OFFSET _u(0x0000002c) -#define TIMER_DBGPAUSE_BITS _u(0x00000006) -#define TIMER_DBGPAUSE_RESET _u(0x00000007) -// ----------------------------------------------------------------------------- -// Field : TIMER_DBGPAUSE_DBG1 -// Description : Pause when processor 1 is in debug mode -#define TIMER_DBGPAUSE_DBG1_RESET _u(0x1) -#define TIMER_DBGPAUSE_DBG1_BITS _u(0x00000004) -#define TIMER_DBGPAUSE_DBG1_MSB _u(2) -#define TIMER_DBGPAUSE_DBG1_LSB _u(2) -#define TIMER_DBGPAUSE_DBG1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : TIMER_DBGPAUSE_DBG0 -// Description : Pause when processor 0 is in debug mode -#define TIMER_DBGPAUSE_DBG0_RESET _u(0x1) -#define TIMER_DBGPAUSE_DBG0_BITS _u(0x00000002) -#define TIMER_DBGPAUSE_DBG0_MSB _u(1) -#define TIMER_DBGPAUSE_DBG0_LSB _u(1) -#define TIMER_DBGPAUSE_DBG0_ACCESS "RW" -// ============================================================================= -// Register : TIMER_PAUSE -// Description : Set high to pause the timer -#define TIMER_PAUSE_OFFSET _u(0x00000030) -#define TIMER_PAUSE_BITS _u(0x00000001) -#define TIMER_PAUSE_RESET _u(0x00000000) -#define TIMER_PAUSE_MSB _u(0) -#define TIMER_PAUSE_LSB _u(0) -#define TIMER_PAUSE_ACCESS "RW" -// ============================================================================= -// Register : TIMER_LOCKED -// Description : Set locked bit to disable write access to timer Once set, -// cannot be cleared (without a reset) -#define TIMER_LOCKED_OFFSET _u(0x00000034) -#define TIMER_LOCKED_BITS _u(0x00000001) -#define TIMER_LOCKED_RESET _u(0x00000000) -#define TIMER_LOCKED_MSB _u(0) -#define TIMER_LOCKED_LSB _u(0) -#define TIMER_LOCKED_ACCESS "RW" -// ============================================================================= -// Register : TIMER_SOURCE -// Description : Selects the source for the timer. Defaults to the normal tick -// configured in the ticks block (typically configured to 1 -// microsecond). Writing to 1 will ignore the tick and count -// clk_sys cycles instead. -#define TIMER_SOURCE_OFFSET _u(0x00000038) -#define TIMER_SOURCE_BITS _u(0x00000001) -#define TIMER_SOURCE_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : TIMER_SOURCE_CLK_SYS -// 0x0 -> TICK -// 0x1 -> CLK_SYS -#define TIMER_SOURCE_CLK_SYS_RESET _u(0x0) -#define TIMER_SOURCE_CLK_SYS_BITS _u(0x00000001) -#define TIMER_SOURCE_CLK_SYS_MSB _u(0) -#define TIMER_SOURCE_CLK_SYS_LSB _u(0) -#define TIMER_SOURCE_CLK_SYS_ACCESS "RW" -#define TIMER_SOURCE_CLK_SYS_VALUE_TICK _u(0x0) -#define TIMER_SOURCE_CLK_SYS_VALUE_CLK_SYS _u(0x1) -// ============================================================================= -// Register : TIMER_INTR -// Description : Raw Interrupts -#define TIMER_INTR_OFFSET _u(0x0000003c) -#define TIMER_INTR_BITS _u(0x0000000f) -#define TIMER_INTR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : TIMER_INTR_ALARM_3 -#define TIMER_INTR_ALARM_3_RESET _u(0x0) -#define TIMER_INTR_ALARM_3_BITS _u(0x00000008) -#define TIMER_INTR_ALARM_3_MSB _u(3) -#define TIMER_INTR_ALARM_3_LSB _u(3) -#define TIMER_INTR_ALARM_3_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : TIMER_INTR_ALARM_2 -#define TIMER_INTR_ALARM_2_RESET _u(0x0) -#define TIMER_INTR_ALARM_2_BITS _u(0x00000004) -#define TIMER_INTR_ALARM_2_MSB _u(2) -#define TIMER_INTR_ALARM_2_LSB _u(2) -#define TIMER_INTR_ALARM_2_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : TIMER_INTR_ALARM_1 -#define TIMER_INTR_ALARM_1_RESET _u(0x0) -#define TIMER_INTR_ALARM_1_BITS _u(0x00000002) -#define TIMER_INTR_ALARM_1_MSB _u(1) -#define TIMER_INTR_ALARM_1_LSB _u(1) -#define TIMER_INTR_ALARM_1_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : TIMER_INTR_ALARM_0 -#define TIMER_INTR_ALARM_0_RESET _u(0x0) -#define TIMER_INTR_ALARM_0_BITS _u(0x00000001) -#define TIMER_INTR_ALARM_0_MSB _u(0) -#define TIMER_INTR_ALARM_0_LSB _u(0) -#define TIMER_INTR_ALARM_0_ACCESS "WC" -// ============================================================================= -// Register : TIMER_INTE -// Description : Interrupt Enable -#define TIMER_INTE_OFFSET _u(0x00000040) -#define TIMER_INTE_BITS _u(0x0000000f) -#define TIMER_INTE_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : TIMER_INTE_ALARM_3 -#define TIMER_INTE_ALARM_3_RESET _u(0x0) -#define TIMER_INTE_ALARM_3_BITS _u(0x00000008) -#define TIMER_INTE_ALARM_3_MSB _u(3) -#define TIMER_INTE_ALARM_3_LSB _u(3) -#define TIMER_INTE_ALARM_3_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : TIMER_INTE_ALARM_2 -#define TIMER_INTE_ALARM_2_RESET _u(0x0) -#define TIMER_INTE_ALARM_2_BITS _u(0x00000004) -#define TIMER_INTE_ALARM_2_MSB _u(2) -#define TIMER_INTE_ALARM_2_LSB _u(2) -#define TIMER_INTE_ALARM_2_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : TIMER_INTE_ALARM_1 -#define TIMER_INTE_ALARM_1_RESET _u(0x0) -#define TIMER_INTE_ALARM_1_BITS _u(0x00000002) -#define TIMER_INTE_ALARM_1_MSB _u(1) -#define TIMER_INTE_ALARM_1_LSB _u(1) -#define TIMER_INTE_ALARM_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : TIMER_INTE_ALARM_0 -#define TIMER_INTE_ALARM_0_RESET _u(0x0) -#define TIMER_INTE_ALARM_0_BITS _u(0x00000001) -#define TIMER_INTE_ALARM_0_MSB _u(0) -#define TIMER_INTE_ALARM_0_LSB _u(0) -#define TIMER_INTE_ALARM_0_ACCESS "RW" -// ============================================================================= -// Register : TIMER_INTF -// Description : Interrupt Force -#define TIMER_INTF_OFFSET _u(0x00000044) -#define TIMER_INTF_BITS _u(0x0000000f) -#define TIMER_INTF_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : TIMER_INTF_ALARM_3 -#define TIMER_INTF_ALARM_3_RESET _u(0x0) -#define TIMER_INTF_ALARM_3_BITS _u(0x00000008) -#define TIMER_INTF_ALARM_3_MSB _u(3) -#define TIMER_INTF_ALARM_3_LSB _u(3) -#define TIMER_INTF_ALARM_3_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : TIMER_INTF_ALARM_2 -#define TIMER_INTF_ALARM_2_RESET _u(0x0) -#define TIMER_INTF_ALARM_2_BITS _u(0x00000004) -#define TIMER_INTF_ALARM_2_MSB _u(2) -#define TIMER_INTF_ALARM_2_LSB _u(2) -#define TIMER_INTF_ALARM_2_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : TIMER_INTF_ALARM_1 -#define TIMER_INTF_ALARM_1_RESET _u(0x0) -#define TIMER_INTF_ALARM_1_BITS _u(0x00000002) -#define TIMER_INTF_ALARM_1_MSB _u(1) -#define TIMER_INTF_ALARM_1_LSB _u(1) -#define TIMER_INTF_ALARM_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : TIMER_INTF_ALARM_0 -#define TIMER_INTF_ALARM_0_RESET _u(0x0) -#define TIMER_INTF_ALARM_0_BITS _u(0x00000001) -#define TIMER_INTF_ALARM_0_MSB _u(0) -#define TIMER_INTF_ALARM_0_LSB _u(0) -#define TIMER_INTF_ALARM_0_ACCESS "RW" -// ============================================================================= -// Register : TIMER_INTS -// Description : Interrupt status after masking & forcing -#define TIMER_INTS_OFFSET _u(0x00000048) -#define TIMER_INTS_BITS _u(0x0000000f) -#define TIMER_INTS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : TIMER_INTS_ALARM_3 -#define TIMER_INTS_ALARM_3_RESET _u(0x0) -#define TIMER_INTS_ALARM_3_BITS _u(0x00000008) -#define TIMER_INTS_ALARM_3_MSB _u(3) -#define TIMER_INTS_ALARM_3_LSB _u(3) -#define TIMER_INTS_ALARM_3_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : TIMER_INTS_ALARM_2 -#define TIMER_INTS_ALARM_2_RESET _u(0x0) -#define TIMER_INTS_ALARM_2_BITS _u(0x00000004) -#define TIMER_INTS_ALARM_2_MSB _u(2) -#define TIMER_INTS_ALARM_2_LSB _u(2) -#define TIMER_INTS_ALARM_2_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : TIMER_INTS_ALARM_1 -#define TIMER_INTS_ALARM_1_RESET _u(0x0) -#define TIMER_INTS_ALARM_1_BITS _u(0x00000002) -#define TIMER_INTS_ALARM_1_MSB _u(1) -#define TIMER_INTS_ALARM_1_LSB _u(1) -#define TIMER_INTS_ALARM_1_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : TIMER_INTS_ALARM_0 -#define TIMER_INTS_ALARM_0_RESET _u(0x0) -#define TIMER_INTS_ALARM_0_BITS _u(0x00000001) -#define TIMER_INTS_ALARM_0_MSB _u(0) -#define TIMER_INTS_ALARM_0_LSB _u(0) -#define TIMER_INTS_ALARM_0_ACCESS "RO" -// ============================================================================= -#endif // _HARDWARE_REGS_TIMER_H - diff --git a/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/trng.h b/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/trng.h deleted file mode 100644 index c84c715b3d..0000000000 --- a/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/trng.h +++ /dev/null @@ -1,625 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -// ============================================================================= -// Register block : TRNG -// Version : 1 -// Bus type : apb -// Description : ARM TrustZone RNG register block -// ============================================================================= -#ifndef _HARDWARE_REGS_TRNG_H -#define _HARDWARE_REGS_TRNG_H -// ============================================================================= -// Register : TRNG_RNG_IMR -// Description : Interrupt masking. -#define TRNG_RNG_IMR_OFFSET _u(0x00000100) -#define TRNG_RNG_IMR_BITS _u(0xffffffff) -#define TRNG_RNG_IMR_RESET _u(0x0000000f) -// ----------------------------------------------------------------------------- -// Field : TRNG_RNG_IMR_RESERVED -// Description : RESERVED -#define TRNG_RNG_IMR_RESERVED_RESET _u(0x0000000) -#define TRNG_RNG_IMR_RESERVED_BITS _u(0xfffffff0) -#define TRNG_RNG_IMR_RESERVED_MSB _u(31) -#define TRNG_RNG_IMR_RESERVED_LSB _u(4) -#define TRNG_RNG_IMR_RESERVED_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : TRNG_RNG_IMR_VN_ERR_INT_MASK -// Description : 1'b1-mask interrupt, no interrupt will be generated. See -// RNG_ISR for an explanation on this interrupt. -#define TRNG_RNG_IMR_VN_ERR_INT_MASK_RESET _u(0x1) -#define TRNG_RNG_IMR_VN_ERR_INT_MASK_BITS _u(0x00000008) -#define TRNG_RNG_IMR_VN_ERR_INT_MASK_MSB _u(3) -#define TRNG_RNG_IMR_VN_ERR_INT_MASK_LSB _u(3) -#define TRNG_RNG_IMR_VN_ERR_INT_MASK_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : TRNG_RNG_IMR_CRNGT_ERR_INT_MASK -// Description : 1'b1-mask interrupt, no interrupt will be generated. See -// RNG_ISR for an explanation on this interrupt. -#define TRNG_RNG_IMR_CRNGT_ERR_INT_MASK_RESET _u(0x1) -#define TRNG_RNG_IMR_CRNGT_ERR_INT_MASK_BITS _u(0x00000004) -#define TRNG_RNG_IMR_CRNGT_ERR_INT_MASK_MSB _u(2) -#define TRNG_RNG_IMR_CRNGT_ERR_INT_MASK_LSB _u(2) -#define TRNG_RNG_IMR_CRNGT_ERR_INT_MASK_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : TRNG_RNG_IMR_AUTOCORR_ERR_INT_MASK -// Description : 1'b1-mask interrupt, no interrupt will be generated. See -// RNG_ISR for an explanation on this interrupt. -#define TRNG_RNG_IMR_AUTOCORR_ERR_INT_MASK_RESET _u(0x1) -#define TRNG_RNG_IMR_AUTOCORR_ERR_INT_MASK_BITS _u(0x00000002) -#define TRNG_RNG_IMR_AUTOCORR_ERR_INT_MASK_MSB _u(1) -#define TRNG_RNG_IMR_AUTOCORR_ERR_INT_MASK_LSB _u(1) -#define TRNG_RNG_IMR_AUTOCORR_ERR_INT_MASK_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : TRNG_RNG_IMR_EHR_VALID_INT_MASK -// Description : 1'b1-mask interrupt, no interrupt will be generated. See -// RNG_ISR for an explanation on this interrupt. -#define TRNG_RNG_IMR_EHR_VALID_INT_MASK_RESET _u(0x1) -#define TRNG_RNG_IMR_EHR_VALID_INT_MASK_BITS _u(0x00000001) -#define TRNG_RNG_IMR_EHR_VALID_INT_MASK_MSB _u(0) -#define TRNG_RNG_IMR_EHR_VALID_INT_MASK_LSB _u(0) -#define TRNG_RNG_IMR_EHR_VALID_INT_MASK_ACCESS "RW" -// ============================================================================= -// Register : TRNG_RNG_ISR -// Description : RNG status register. If corresponding RNG_IMR bit is unmasked, -// an interrupt will be generated. -#define TRNG_RNG_ISR_OFFSET _u(0x00000104) -#define TRNG_RNG_ISR_BITS _u(0xffffffff) -#define TRNG_RNG_ISR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : TRNG_RNG_ISR_RESERVED -// Description : RESERVED -#define TRNG_RNG_ISR_RESERVED_RESET _u(0x0000000) -#define TRNG_RNG_ISR_RESERVED_BITS _u(0xfffffff0) -#define TRNG_RNG_ISR_RESERVED_MSB _u(31) -#define TRNG_RNG_ISR_RESERVED_LSB _u(4) -#define TRNG_RNG_ISR_RESERVED_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : TRNG_RNG_ISR_VN_ERR -// Description : 1'b1 indicates Von Neuman error. Error in von Neuman occurs if -// 32 consecutive collected bits are identical, ZERO or ONE. -#define TRNG_RNG_ISR_VN_ERR_RESET _u(0x0) -#define TRNG_RNG_ISR_VN_ERR_BITS _u(0x00000008) -#define TRNG_RNG_ISR_VN_ERR_MSB _u(3) -#define TRNG_RNG_ISR_VN_ERR_LSB _u(3) -#define TRNG_RNG_ISR_VN_ERR_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : TRNG_RNG_ISR_CRNGT_ERR -// Description : 1'b1 indicates CRNGT in the RNG test failed. Failure occurs -// when two consecutive blocks of 16 collected bits are equal. -#define TRNG_RNG_ISR_CRNGT_ERR_RESET _u(0x0) -#define TRNG_RNG_ISR_CRNGT_ERR_BITS _u(0x00000004) -#define TRNG_RNG_ISR_CRNGT_ERR_MSB _u(2) -#define TRNG_RNG_ISR_CRNGT_ERR_LSB _u(2) -#define TRNG_RNG_ISR_CRNGT_ERR_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : TRNG_RNG_ISR_AUTOCORR_ERR -// Description : 1'b1 indicates Autocorrelation test failed four times in a row. -// When set, RNG cease from functioning until next reset. -#define TRNG_RNG_ISR_AUTOCORR_ERR_RESET _u(0x0) -#define TRNG_RNG_ISR_AUTOCORR_ERR_BITS _u(0x00000002) -#define TRNG_RNG_ISR_AUTOCORR_ERR_MSB _u(1) -#define TRNG_RNG_ISR_AUTOCORR_ERR_LSB _u(1) -#define TRNG_RNG_ISR_AUTOCORR_ERR_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : TRNG_RNG_ISR_EHR_VALID -// Description : 1'b1 indicates that 192 bits have been collected in the RNG, -// and are ready to be read. -#define TRNG_RNG_ISR_EHR_VALID_RESET _u(0x0) -#define TRNG_RNG_ISR_EHR_VALID_BITS _u(0x00000001) -#define TRNG_RNG_ISR_EHR_VALID_MSB _u(0) -#define TRNG_RNG_ISR_EHR_VALID_LSB _u(0) -#define TRNG_RNG_ISR_EHR_VALID_ACCESS "RO" -// ============================================================================= -// Register : TRNG_RNG_ICR -// Description : Interrupt/status bit clear Register. -#define TRNG_RNG_ICR_OFFSET _u(0x00000108) -#define TRNG_RNG_ICR_BITS _u(0xffffffff) -#define TRNG_RNG_ICR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : TRNG_RNG_ICR_RESERVED -// Description : RESERVED -#define TRNG_RNG_ICR_RESERVED_RESET _u(0x0000000) -#define TRNG_RNG_ICR_RESERVED_BITS _u(0xfffffff0) -#define TRNG_RNG_ICR_RESERVED_MSB _u(31) -#define TRNG_RNG_ICR_RESERVED_LSB _u(4) -#define TRNG_RNG_ICR_RESERVED_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : TRNG_RNG_ICR_VN_ERR -// Description : Write 1'b1 - clear corresponding bit in RNG_ISR. -#define TRNG_RNG_ICR_VN_ERR_RESET _u(0x0) -#define TRNG_RNG_ICR_VN_ERR_BITS _u(0x00000008) -#define TRNG_RNG_ICR_VN_ERR_MSB _u(3) -#define TRNG_RNG_ICR_VN_ERR_LSB _u(3) -#define TRNG_RNG_ICR_VN_ERR_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : TRNG_RNG_ICR_CRNGT_ERR -// Description : Write 1'b1 - clear corresponding bit in RNG_ISR. -#define TRNG_RNG_ICR_CRNGT_ERR_RESET _u(0x0) -#define TRNG_RNG_ICR_CRNGT_ERR_BITS _u(0x00000004) -#define TRNG_RNG_ICR_CRNGT_ERR_MSB _u(2) -#define TRNG_RNG_ICR_CRNGT_ERR_LSB _u(2) -#define TRNG_RNG_ICR_CRNGT_ERR_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : TRNG_RNG_ICR_AUTOCORR_ERR -// Description : Cannot be cleared by SW! Only RNG reset clears this bit. -#define TRNG_RNG_ICR_AUTOCORR_ERR_RESET _u(0x0) -#define TRNG_RNG_ICR_AUTOCORR_ERR_BITS _u(0x00000002) -#define TRNG_RNG_ICR_AUTOCORR_ERR_MSB _u(1) -#define TRNG_RNG_ICR_AUTOCORR_ERR_LSB _u(1) -#define TRNG_RNG_ICR_AUTOCORR_ERR_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : TRNG_RNG_ICR_EHR_VALID -// Description : Write 1'b1 - clear corresponding bit in RNG_ISR. -#define TRNG_RNG_ICR_EHR_VALID_RESET _u(0x0) -#define TRNG_RNG_ICR_EHR_VALID_BITS _u(0x00000001) -#define TRNG_RNG_ICR_EHR_VALID_MSB _u(0) -#define TRNG_RNG_ICR_EHR_VALID_LSB _u(0) -#define TRNG_RNG_ICR_EHR_VALID_ACCESS "RW" -// ============================================================================= -// Register : TRNG_TRNG_CONFIG -// Description : Selecting the inverter-chain length. -#define TRNG_TRNG_CONFIG_OFFSET _u(0x0000010c) -#define TRNG_TRNG_CONFIG_BITS _u(0xffffffff) -#define TRNG_TRNG_CONFIG_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : TRNG_TRNG_CONFIG_RESERVED -// Description : RESERVED -#define TRNG_TRNG_CONFIG_RESERVED_RESET _u(0x00000000) -#define TRNG_TRNG_CONFIG_RESERVED_BITS _u(0xfffffffc) -#define TRNG_TRNG_CONFIG_RESERVED_MSB _u(31) -#define TRNG_TRNG_CONFIG_RESERVED_LSB _u(2) -#define TRNG_TRNG_CONFIG_RESERVED_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : TRNG_TRNG_CONFIG_RND_SRC_SEL -// Description : Selects the number of inverters (out of four possible -// selections) in the ring oscillator (the entropy source). -#define TRNG_TRNG_CONFIG_RND_SRC_SEL_RESET _u(0x0) -#define TRNG_TRNG_CONFIG_RND_SRC_SEL_BITS _u(0x00000003) -#define TRNG_TRNG_CONFIG_RND_SRC_SEL_MSB _u(1) -#define TRNG_TRNG_CONFIG_RND_SRC_SEL_LSB _u(0) -#define TRNG_TRNG_CONFIG_RND_SRC_SEL_ACCESS "RW" -// ============================================================================= -// Register : TRNG_TRNG_VALID -// Description : 192 bit collection indication. -#define TRNG_TRNG_VALID_OFFSET _u(0x00000110) -#define TRNG_TRNG_VALID_BITS _u(0xffffffff) -#define TRNG_TRNG_VALID_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : TRNG_TRNG_VALID_RESERVED -// Description : RESERVED -#define TRNG_TRNG_VALID_RESERVED_RESET _u(0x00000000) -#define TRNG_TRNG_VALID_RESERVED_BITS _u(0xfffffffe) -#define TRNG_TRNG_VALID_RESERVED_MSB _u(31) -#define TRNG_TRNG_VALID_RESERVED_LSB _u(1) -#define TRNG_TRNG_VALID_RESERVED_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : TRNG_TRNG_VALID_EHR_VALID -// Description : 1'b1 indicates that collection of bits in the RNG is completed, -// and data can be read from EHR_DATA register. -#define TRNG_TRNG_VALID_EHR_VALID_RESET _u(0x0) -#define TRNG_TRNG_VALID_EHR_VALID_BITS _u(0x00000001) -#define TRNG_TRNG_VALID_EHR_VALID_MSB _u(0) -#define TRNG_TRNG_VALID_EHR_VALID_LSB _u(0) -#define TRNG_TRNG_VALID_EHR_VALID_ACCESS "RO" -// ============================================================================= -// Register : TRNG_EHR_DATA0 -// Description : RNG collected bits. -// Bits [31:0] of Entropy Holding Register (EHR) - RNG output -// register -#define TRNG_EHR_DATA0_OFFSET _u(0x00000114) -#define TRNG_EHR_DATA0_BITS _u(0xffffffff) -#define TRNG_EHR_DATA0_RESET _u(0x00000000) -#define TRNG_EHR_DATA0_MSB _u(31) -#define TRNG_EHR_DATA0_LSB _u(0) -#define TRNG_EHR_DATA0_ACCESS "RO" -// ============================================================================= -// Register : TRNG_EHR_DATA1 -// Description : RNG collected bits. -// Bits [63:32] of Entropy Holding Register (EHR) - RNG output -// register -#define TRNG_EHR_DATA1_OFFSET _u(0x00000118) -#define TRNG_EHR_DATA1_BITS _u(0xffffffff) -#define TRNG_EHR_DATA1_RESET _u(0x00000000) -#define TRNG_EHR_DATA1_MSB _u(31) -#define TRNG_EHR_DATA1_LSB _u(0) -#define TRNG_EHR_DATA1_ACCESS "RO" -// ============================================================================= -// Register : TRNG_EHR_DATA2 -// Description : RNG collected bits. -// Bits [95:64] of Entropy Holding Register (EHR) - RNG output -// register -#define TRNG_EHR_DATA2_OFFSET _u(0x0000011c) -#define TRNG_EHR_DATA2_BITS _u(0xffffffff) -#define TRNG_EHR_DATA2_RESET _u(0x00000000) -#define TRNG_EHR_DATA2_MSB _u(31) -#define TRNG_EHR_DATA2_LSB _u(0) -#define TRNG_EHR_DATA2_ACCESS "RO" -// ============================================================================= -// Register : TRNG_EHR_DATA3 -// Description : RNG collected bits. -// Bits [127:96] of Entropy Holding Register (EHR) - RNG output -// register -#define TRNG_EHR_DATA3_OFFSET _u(0x00000120) -#define TRNG_EHR_DATA3_BITS _u(0xffffffff) -#define TRNG_EHR_DATA3_RESET _u(0x00000000) -#define TRNG_EHR_DATA3_MSB _u(31) -#define TRNG_EHR_DATA3_LSB _u(0) -#define TRNG_EHR_DATA3_ACCESS "RO" -// ============================================================================= -// Register : TRNG_EHR_DATA4 -// Description : RNG collected bits. -// Bits [159:128] of Entropy Holding Register (EHR) - RNG output -// register -#define TRNG_EHR_DATA4_OFFSET _u(0x00000124) -#define TRNG_EHR_DATA4_BITS _u(0xffffffff) -#define TRNG_EHR_DATA4_RESET _u(0x00000000) -#define TRNG_EHR_DATA4_MSB _u(31) -#define TRNG_EHR_DATA4_LSB _u(0) -#define TRNG_EHR_DATA4_ACCESS "RO" -// ============================================================================= -// Register : TRNG_EHR_DATA5 -// Description : RNG collected bits. -// Bits [191:160] of Entropy Holding Register (EHR) - RNG output -// register -#define TRNG_EHR_DATA5_OFFSET _u(0x00000128) -#define TRNG_EHR_DATA5_BITS _u(0xffffffff) -#define TRNG_EHR_DATA5_RESET _u(0x00000000) -#define TRNG_EHR_DATA5_MSB _u(31) -#define TRNG_EHR_DATA5_LSB _u(0) -#define TRNG_EHR_DATA5_ACCESS "RO" -// ============================================================================= -// Register : TRNG_RND_SOURCE_ENABLE -// Description : Enable signal for the random source. -#define TRNG_RND_SOURCE_ENABLE_OFFSET _u(0x0000012c) -#define TRNG_RND_SOURCE_ENABLE_BITS _u(0xffffffff) -#define TRNG_RND_SOURCE_ENABLE_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : TRNG_RND_SOURCE_ENABLE_RESERVED -// Description : RESERVED -#define TRNG_RND_SOURCE_ENABLE_RESERVED_RESET _u(0x00000000) -#define TRNG_RND_SOURCE_ENABLE_RESERVED_BITS _u(0xfffffffe) -#define TRNG_RND_SOURCE_ENABLE_RESERVED_MSB _u(31) -#define TRNG_RND_SOURCE_ENABLE_RESERVED_LSB _u(1) -#define TRNG_RND_SOURCE_ENABLE_RESERVED_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : TRNG_RND_SOURCE_ENABLE_RND_SRC_EN -// Description : * 1'b1 - entropy source is enabled. *1'b0 - entropy source is -// disabled -#define TRNG_RND_SOURCE_ENABLE_RND_SRC_EN_RESET _u(0x0) -#define TRNG_RND_SOURCE_ENABLE_RND_SRC_EN_BITS _u(0x00000001) -#define TRNG_RND_SOURCE_ENABLE_RND_SRC_EN_MSB _u(0) -#define TRNG_RND_SOURCE_ENABLE_RND_SRC_EN_LSB _u(0) -#define TRNG_RND_SOURCE_ENABLE_RND_SRC_EN_ACCESS "RW" -// ============================================================================= -// Register : TRNG_SAMPLE_CNT1 -// Description : Counts clocks between sampling of random bit. -#define TRNG_SAMPLE_CNT1_OFFSET _u(0x00000130) -#define TRNG_SAMPLE_CNT1_BITS _u(0xffffffff) -#define TRNG_SAMPLE_CNT1_RESET _u(0x0000ffff) -// ----------------------------------------------------------------------------- -// Field : TRNG_SAMPLE_CNT1_SAMPLE_CNTR1 -// Description : Sets the number of rng_clk cycles between two consecutive ring -// oscillator samples. Note! If the Von-Neuman is bypassed, the -// minimum value for sample counter must not be less then decimal -// seventeen -#define TRNG_SAMPLE_CNT1_SAMPLE_CNTR1_RESET _u(0x0000ffff) -#define TRNG_SAMPLE_CNT1_SAMPLE_CNTR1_BITS _u(0xffffffff) -#define TRNG_SAMPLE_CNT1_SAMPLE_CNTR1_MSB _u(31) -#define TRNG_SAMPLE_CNT1_SAMPLE_CNTR1_LSB _u(0) -#define TRNG_SAMPLE_CNT1_SAMPLE_CNTR1_ACCESS "RW" -// ============================================================================= -// Register : TRNG_AUTOCORR_STATISTIC -// Description : Statistic about Autocorrelation test activations. -#define TRNG_AUTOCORR_STATISTIC_OFFSET _u(0x00000134) -#define TRNG_AUTOCORR_STATISTIC_BITS _u(0xffffffff) -#define TRNG_AUTOCORR_STATISTIC_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : TRNG_AUTOCORR_STATISTIC_RESERVED -// Description : RESERVED -#define TRNG_AUTOCORR_STATISTIC_RESERVED_RESET _u(0x000) -#define TRNG_AUTOCORR_STATISTIC_RESERVED_BITS _u(0xffc00000) -#define TRNG_AUTOCORR_STATISTIC_RESERVED_MSB _u(31) -#define TRNG_AUTOCORR_STATISTIC_RESERVED_LSB _u(22) -#define TRNG_AUTOCORR_STATISTIC_RESERVED_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : TRNG_AUTOCORR_STATISTIC_AUTOCORR_FAILS -// Description : Count each time an autocorrelation test fails. Any write to the -// register reset the counter. Stop collecting statistic if one of -// the counters reached the limit. -#define TRNG_AUTOCORR_STATISTIC_AUTOCORR_FAILS_RESET _u(0x00) -#define TRNG_AUTOCORR_STATISTIC_AUTOCORR_FAILS_BITS _u(0x003fc000) -#define TRNG_AUTOCORR_STATISTIC_AUTOCORR_FAILS_MSB _u(21) -#define TRNG_AUTOCORR_STATISTIC_AUTOCORR_FAILS_LSB _u(14) -#define TRNG_AUTOCORR_STATISTIC_AUTOCORR_FAILS_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : TRNG_AUTOCORR_STATISTIC_AUTOCORR_TRYS -// Description : Count each time an autocorrelation test starts. Any write to -// the register reset the counter. Stop collecting statistic if -// one of the counters reached the limit. -#define TRNG_AUTOCORR_STATISTIC_AUTOCORR_TRYS_RESET _u(0x0000) -#define TRNG_AUTOCORR_STATISTIC_AUTOCORR_TRYS_BITS _u(0x00003fff) -#define TRNG_AUTOCORR_STATISTIC_AUTOCORR_TRYS_MSB _u(13) -#define TRNG_AUTOCORR_STATISTIC_AUTOCORR_TRYS_LSB _u(0) -#define TRNG_AUTOCORR_STATISTIC_AUTOCORR_TRYS_ACCESS "RW" -// ============================================================================= -// Register : TRNG_TRNG_DEBUG_CONTROL -// Description : Debug register. -#define TRNG_TRNG_DEBUG_CONTROL_OFFSET _u(0x00000138) -#define TRNG_TRNG_DEBUG_CONTROL_BITS _u(0x0000000f) -#define TRNG_TRNG_DEBUG_CONTROL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : TRNG_TRNG_DEBUG_CONTROL_AUTO_CORRELATE_BYPASS -// Description : When set, the autocorrelation test in the TRNG module is -// bypassed. -#define TRNG_TRNG_DEBUG_CONTROL_AUTO_CORRELATE_BYPASS_RESET _u(0x0) -#define TRNG_TRNG_DEBUG_CONTROL_AUTO_CORRELATE_BYPASS_BITS _u(0x00000008) -#define TRNG_TRNG_DEBUG_CONTROL_AUTO_CORRELATE_BYPASS_MSB _u(3) -#define TRNG_TRNG_DEBUG_CONTROL_AUTO_CORRELATE_BYPASS_LSB _u(3) -#define TRNG_TRNG_DEBUG_CONTROL_AUTO_CORRELATE_BYPASS_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : TRNG_TRNG_DEBUG_CONTROL_TRNG_CRNGT_BYPASS -// Description : When set, the CRNGT test in the RNG is bypassed. -#define TRNG_TRNG_DEBUG_CONTROL_TRNG_CRNGT_BYPASS_RESET _u(0x0) -#define TRNG_TRNG_DEBUG_CONTROL_TRNG_CRNGT_BYPASS_BITS _u(0x00000004) -#define TRNG_TRNG_DEBUG_CONTROL_TRNG_CRNGT_BYPASS_MSB _u(2) -#define TRNG_TRNG_DEBUG_CONTROL_TRNG_CRNGT_BYPASS_LSB _u(2) -#define TRNG_TRNG_DEBUG_CONTROL_TRNG_CRNGT_BYPASS_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : TRNG_TRNG_DEBUG_CONTROL_VNC_BYPASS -// Description : When set, the Von-Neuman balancer is bypassed (including the 32 -// consecutive bits test). -#define TRNG_TRNG_DEBUG_CONTROL_VNC_BYPASS_RESET _u(0x0) -#define TRNG_TRNG_DEBUG_CONTROL_VNC_BYPASS_BITS _u(0x00000002) -#define TRNG_TRNG_DEBUG_CONTROL_VNC_BYPASS_MSB _u(1) -#define TRNG_TRNG_DEBUG_CONTROL_VNC_BYPASS_LSB _u(1) -#define TRNG_TRNG_DEBUG_CONTROL_VNC_BYPASS_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : TRNG_TRNG_DEBUG_CONTROL_RESERVED -// Description : N/A -#define TRNG_TRNG_DEBUG_CONTROL_RESERVED_RESET _u(0x0) -#define TRNG_TRNG_DEBUG_CONTROL_RESERVED_BITS _u(0x00000001) -#define TRNG_TRNG_DEBUG_CONTROL_RESERVED_MSB _u(0) -#define TRNG_TRNG_DEBUG_CONTROL_RESERVED_LSB _u(0) -#define TRNG_TRNG_DEBUG_CONTROL_RESERVED_ACCESS "RO" -// ============================================================================= -// Register : TRNG_TRNG_SW_RESET -// Description : Generate internal SW reset within the RNG block. -#define TRNG_TRNG_SW_RESET_OFFSET _u(0x00000140) -#define TRNG_TRNG_SW_RESET_BITS _u(0xffffffff) -#define TRNG_TRNG_SW_RESET_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : TRNG_TRNG_SW_RESET_RESERVED -// Description : RESERVED -#define TRNG_TRNG_SW_RESET_RESERVED_RESET _u(0x00000000) -#define TRNG_TRNG_SW_RESET_RESERVED_BITS _u(0xfffffffe) -#define TRNG_TRNG_SW_RESET_RESERVED_MSB _u(31) -#define TRNG_TRNG_SW_RESET_RESERVED_LSB _u(1) -#define TRNG_TRNG_SW_RESET_RESERVED_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : TRNG_TRNG_SW_RESET_TRNG_SW_RESET -// Description : Writing 1'b1 to this register causes an internal RNG reset. -#define TRNG_TRNG_SW_RESET_TRNG_SW_RESET_RESET _u(0x0) -#define TRNG_TRNG_SW_RESET_TRNG_SW_RESET_BITS _u(0x00000001) -#define TRNG_TRNG_SW_RESET_TRNG_SW_RESET_MSB _u(0) -#define TRNG_TRNG_SW_RESET_TRNG_SW_RESET_LSB _u(0) -#define TRNG_TRNG_SW_RESET_TRNG_SW_RESET_ACCESS "RW" -// ============================================================================= -// Register : TRNG_RNG_DEBUG_EN_INPUT -// Description : Enable the RNG debug mode -#define TRNG_RNG_DEBUG_EN_INPUT_OFFSET _u(0x000001b4) -#define TRNG_RNG_DEBUG_EN_INPUT_BITS _u(0xffffffff) -#define TRNG_RNG_DEBUG_EN_INPUT_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : TRNG_RNG_DEBUG_EN_INPUT_RESERVED -// Description : RESERVED -#define TRNG_RNG_DEBUG_EN_INPUT_RESERVED_RESET _u(0x00000000) -#define TRNG_RNG_DEBUG_EN_INPUT_RESERVED_BITS _u(0xfffffffe) -#define TRNG_RNG_DEBUG_EN_INPUT_RESERVED_MSB _u(31) -#define TRNG_RNG_DEBUG_EN_INPUT_RESERVED_LSB _u(1) -#define TRNG_RNG_DEBUG_EN_INPUT_RESERVED_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : TRNG_RNG_DEBUG_EN_INPUT_RNG_DEBUG_EN -// Description : * 1'b1 - debug mode is enabled. *1'b0 - debug mode is disabled -#define TRNG_RNG_DEBUG_EN_INPUT_RNG_DEBUG_EN_RESET _u(0x0) -#define TRNG_RNG_DEBUG_EN_INPUT_RNG_DEBUG_EN_BITS _u(0x00000001) -#define TRNG_RNG_DEBUG_EN_INPUT_RNG_DEBUG_EN_MSB _u(0) -#define TRNG_RNG_DEBUG_EN_INPUT_RNG_DEBUG_EN_LSB _u(0) -#define TRNG_RNG_DEBUG_EN_INPUT_RNG_DEBUG_EN_ACCESS "RW" -// ============================================================================= -// Register : TRNG_TRNG_BUSY -// Description : RNG Busy indication. -#define TRNG_TRNG_BUSY_OFFSET _u(0x000001b8) -#define TRNG_TRNG_BUSY_BITS _u(0xffffffff) -#define TRNG_TRNG_BUSY_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : TRNG_TRNG_BUSY_RESERVED -// Description : RESERVED -#define TRNG_TRNG_BUSY_RESERVED_RESET _u(0x00000000) -#define TRNG_TRNG_BUSY_RESERVED_BITS _u(0xfffffffe) -#define TRNG_TRNG_BUSY_RESERVED_MSB _u(31) -#define TRNG_TRNG_BUSY_RESERVED_LSB _u(1) -#define TRNG_TRNG_BUSY_RESERVED_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : TRNG_TRNG_BUSY_TRNG_BUSY -// Description : Reflects rng_busy status. -#define TRNG_TRNG_BUSY_TRNG_BUSY_RESET _u(0x0) -#define TRNG_TRNG_BUSY_TRNG_BUSY_BITS _u(0x00000001) -#define TRNG_TRNG_BUSY_TRNG_BUSY_MSB _u(0) -#define TRNG_TRNG_BUSY_TRNG_BUSY_LSB _u(0) -#define TRNG_TRNG_BUSY_TRNG_BUSY_ACCESS "RO" -// ============================================================================= -// Register : TRNG_RST_BITS_COUNTER -// Description : Reset the counter of collected bits in the RNG. -#define TRNG_RST_BITS_COUNTER_OFFSET _u(0x000001bc) -#define TRNG_RST_BITS_COUNTER_BITS _u(0xffffffff) -#define TRNG_RST_BITS_COUNTER_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : TRNG_RST_BITS_COUNTER_RESERVED -// Description : RESERVED -#define TRNG_RST_BITS_COUNTER_RESERVED_RESET _u(0x00000000) -#define TRNG_RST_BITS_COUNTER_RESERVED_BITS _u(0xfffffffe) -#define TRNG_RST_BITS_COUNTER_RESERVED_MSB _u(31) -#define TRNG_RST_BITS_COUNTER_RESERVED_LSB _u(1) -#define TRNG_RST_BITS_COUNTER_RESERVED_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : TRNG_RST_BITS_COUNTER_RST_BITS_COUNTER -// Description : Writing any value to this address will reset the bits counter -// and RNG valid registers. RND_SORCE_ENABLE register must be -// unset in order for the reset to take place. -#define TRNG_RST_BITS_COUNTER_RST_BITS_COUNTER_RESET _u(0x0) -#define TRNG_RST_BITS_COUNTER_RST_BITS_COUNTER_BITS _u(0x00000001) -#define TRNG_RST_BITS_COUNTER_RST_BITS_COUNTER_MSB _u(0) -#define TRNG_RST_BITS_COUNTER_RST_BITS_COUNTER_LSB _u(0) -#define TRNG_RST_BITS_COUNTER_RST_BITS_COUNTER_ACCESS "RW" -// ============================================================================= -// Register : TRNG_RNG_VERSION -// Description : Displays the version settings of the TRNG. -#define TRNG_RNG_VERSION_OFFSET _u(0x000001c0) -#define TRNG_RNG_VERSION_BITS _u(0xffffffff) -#define TRNG_RNG_VERSION_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : TRNG_RNG_VERSION_RESERVED -// Description : RESERVED -#define TRNG_RNG_VERSION_RESERVED_RESET _u(0x000000) -#define TRNG_RNG_VERSION_RESERVED_BITS _u(0xffffff00) -#define TRNG_RNG_VERSION_RESERVED_MSB _u(31) -#define TRNG_RNG_VERSION_RESERVED_LSB _u(8) -#define TRNG_RNG_VERSION_RESERVED_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : TRNG_RNG_VERSION_RNG_USE_5_SBOXES -// Description : * 1'b1 - 5 SBOX AES. *1'b0 - 20 SBOX AES -#define TRNG_RNG_VERSION_RNG_USE_5_SBOXES_RESET _u(0x0) -#define TRNG_RNG_VERSION_RNG_USE_5_SBOXES_BITS _u(0x00000080) -#define TRNG_RNG_VERSION_RNG_USE_5_SBOXES_MSB _u(7) -#define TRNG_RNG_VERSION_RNG_USE_5_SBOXES_LSB _u(7) -#define TRNG_RNG_VERSION_RNG_USE_5_SBOXES_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : TRNG_RNG_VERSION_RESEEDING_EXISTS -// Description : * 1'b1 - Exists. *1'b0 - Does not exist -#define TRNG_RNG_VERSION_RESEEDING_EXISTS_RESET _u(0x0) -#define TRNG_RNG_VERSION_RESEEDING_EXISTS_BITS _u(0x00000040) -#define TRNG_RNG_VERSION_RESEEDING_EXISTS_MSB _u(6) -#define TRNG_RNG_VERSION_RESEEDING_EXISTS_LSB _u(6) -#define TRNG_RNG_VERSION_RESEEDING_EXISTS_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : TRNG_RNG_VERSION_KAT_EXISTS -// Description : * 1'b1 - Exists. *1'b0 - Does not exist -#define TRNG_RNG_VERSION_KAT_EXISTS_RESET _u(0x0) -#define TRNG_RNG_VERSION_KAT_EXISTS_BITS _u(0x00000020) -#define TRNG_RNG_VERSION_KAT_EXISTS_MSB _u(5) -#define TRNG_RNG_VERSION_KAT_EXISTS_LSB _u(5) -#define TRNG_RNG_VERSION_KAT_EXISTS_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : TRNG_RNG_VERSION_PRNG_EXISTS -// Description : * 1'b1 - Exists. *1'b0 - Does not exist -#define TRNG_RNG_VERSION_PRNG_EXISTS_RESET _u(0x0) -#define TRNG_RNG_VERSION_PRNG_EXISTS_BITS _u(0x00000010) -#define TRNG_RNG_VERSION_PRNG_EXISTS_MSB _u(4) -#define TRNG_RNG_VERSION_PRNG_EXISTS_LSB _u(4) -#define TRNG_RNG_VERSION_PRNG_EXISTS_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : TRNG_RNG_VERSION_TRNG_TESTS_BYPASS_EN -// Description : * 1'b1 - Exists. *1'b0 - Does not exist -#define TRNG_RNG_VERSION_TRNG_TESTS_BYPASS_EN_RESET _u(0x0) -#define TRNG_RNG_VERSION_TRNG_TESTS_BYPASS_EN_BITS _u(0x00000008) -#define TRNG_RNG_VERSION_TRNG_TESTS_BYPASS_EN_MSB _u(3) -#define TRNG_RNG_VERSION_TRNG_TESTS_BYPASS_EN_LSB _u(3) -#define TRNG_RNG_VERSION_TRNG_TESTS_BYPASS_EN_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : TRNG_RNG_VERSION_AUTOCORR_EXISTS -// Description : * 1'b1 - Exists. *1'b0 - Does not exist -#define TRNG_RNG_VERSION_AUTOCORR_EXISTS_RESET _u(0x0) -#define TRNG_RNG_VERSION_AUTOCORR_EXISTS_BITS _u(0x00000004) -#define TRNG_RNG_VERSION_AUTOCORR_EXISTS_MSB _u(2) -#define TRNG_RNG_VERSION_AUTOCORR_EXISTS_LSB _u(2) -#define TRNG_RNG_VERSION_AUTOCORR_EXISTS_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : TRNG_RNG_VERSION_CRNGT_EXISTS -// Description : * 1'b1 - Exists. *1'b0 - Does not exist -#define TRNG_RNG_VERSION_CRNGT_EXISTS_RESET _u(0x0) -#define TRNG_RNG_VERSION_CRNGT_EXISTS_BITS _u(0x00000002) -#define TRNG_RNG_VERSION_CRNGT_EXISTS_MSB _u(1) -#define TRNG_RNG_VERSION_CRNGT_EXISTS_LSB _u(1) -#define TRNG_RNG_VERSION_CRNGT_EXISTS_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : TRNG_RNG_VERSION_EHR_WIDTH_192 -// Description : * 1'b1 - 192-bit EHR. *1'b0 - 128-bit EHR -#define TRNG_RNG_VERSION_EHR_WIDTH_192_RESET _u(0x0) -#define TRNG_RNG_VERSION_EHR_WIDTH_192_BITS _u(0x00000001) -#define TRNG_RNG_VERSION_EHR_WIDTH_192_MSB _u(0) -#define TRNG_RNG_VERSION_EHR_WIDTH_192_LSB _u(0) -#define TRNG_RNG_VERSION_EHR_WIDTH_192_ACCESS "RO" -// ============================================================================= -// Register : TRNG_RNG_BIST_CNTR_0 -// Description : Collected BIST results. -#define TRNG_RNG_BIST_CNTR_0_OFFSET _u(0x000001e0) -#define TRNG_RNG_BIST_CNTR_0_BITS _u(0xffffffff) -#define TRNG_RNG_BIST_CNTR_0_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : TRNG_RNG_BIST_CNTR_0_RESERVED -// Description : RESERVED -#define TRNG_RNG_BIST_CNTR_0_RESERVED_RESET _u(0x000) -#define TRNG_RNG_BIST_CNTR_0_RESERVED_BITS _u(0xffc00000) -#define TRNG_RNG_BIST_CNTR_0_RESERVED_MSB _u(31) -#define TRNG_RNG_BIST_CNTR_0_RESERVED_LSB _u(22) -#define TRNG_RNG_BIST_CNTR_0_RESERVED_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : TRNG_RNG_BIST_CNTR_0_ROSC_CNTR_VAL -// Description : Reflects the results of RNG BIST counter. -#define TRNG_RNG_BIST_CNTR_0_ROSC_CNTR_VAL_RESET _u(0x000000) -#define TRNG_RNG_BIST_CNTR_0_ROSC_CNTR_VAL_BITS _u(0x003fffff) -#define TRNG_RNG_BIST_CNTR_0_ROSC_CNTR_VAL_MSB _u(21) -#define TRNG_RNG_BIST_CNTR_0_ROSC_CNTR_VAL_LSB _u(0) -#define TRNG_RNG_BIST_CNTR_0_ROSC_CNTR_VAL_ACCESS "RO" -// ============================================================================= -// Register : TRNG_RNG_BIST_CNTR_1 -// Description : Collected BIST results. -#define TRNG_RNG_BIST_CNTR_1_OFFSET _u(0x000001e4) -#define TRNG_RNG_BIST_CNTR_1_BITS _u(0xffffffff) -#define TRNG_RNG_BIST_CNTR_1_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : TRNG_RNG_BIST_CNTR_1_RESERVED -// Description : RESERVED -#define TRNG_RNG_BIST_CNTR_1_RESERVED_RESET _u(0x000) -#define TRNG_RNG_BIST_CNTR_1_RESERVED_BITS _u(0xffc00000) -#define TRNG_RNG_BIST_CNTR_1_RESERVED_MSB _u(31) -#define TRNG_RNG_BIST_CNTR_1_RESERVED_LSB _u(22) -#define TRNG_RNG_BIST_CNTR_1_RESERVED_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : TRNG_RNG_BIST_CNTR_1_ROSC_CNTR_VAL -// Description : Reflects the results of RNG BIST counter. -#define TRNG_RNG_BIST_CNTR_1_ROSC_CNTR_VAL_RESET _u(0x000000) -#define TRNG_RNG_BIST_CNTR_1_ROSC_CNTR_VAL_BITS _u(0x003fffff) -#define TRNG_RNG_BIST_CNTR_1_ROSC_CNTR_VAL_MSB _u(21) -#define TRNG_RNG_BIST_CNTR_1_ROSC_CNTR_VAL_LSB _u(0) -#define TRNG_RNG_BIST_CNTR_1_ROSC_CNTR_VAL_ACCESS "RO" -// ============================================================================= -// Register : TRNG_RNG_BIST_CNTR_2 -// Description : Collected BIST results. -#define TRNG_RNG_BIST_CNTR_2_OFFSET _u(0x000001e8) -#define TRNG_RNG_BIST_CNTR_2_BITS _u(0xffffffff) -#define TRNG_RNG_BIST_CNTR_2_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : TRNG_RNG_BIST_CNTR_2_RESERVED -// Description : RESERVED -#define TRNG_RNG_BIST_CNTR_2_RESERVED_RESET _u(0x000) -#define TRNG_RNG_BIST_CNTR_2_RESERVED_BITS _u(0xffc00000) -#define TRNG_RNG_BIST_CNTR_2_RESERVED_MSB _u(31) -#define TRNG_RNG_BIST_CNTR_2_RESERVED_LSB _u(22) -#define TRNG_RNG_BIST_CNTR_2_RESERVED_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : TRNG_RNG_BIST_CNTR_2_ROSC_CNTR_VAL -// Description : Reflects the results of RNG BIST counter. -#define TRNG_RNG_BIST_CNTR_2_ROSC_CNTR_VAL_RESET _u(0x000000) -#define TRNG_RNG_BIST_CNTR_2_ROSC_CNTR_VAL_BITS _u(0x003fffff) -#define TRNG_RNG_BIST_CNTR_2_ROSC_CNTR_VAL_MSB _u(21) -#define TRNG_RNG_BIST_CNTR_2_ROSC_CNTR_VAL_LSB _u(0) -#define TRNG_RNG_BIST_CNTR_2_ROSC_CNTR_VAL_ACCESS "RO" -// ============================================================================= -#endif // _HARDWARE_REGS_TRNG_H - diff --git a/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/uart.h b/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/uart.h deleted file mode 100644 index 0f7f17ec0f..0000000000 --- a/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/uart.h +++ /dev/null @@ -1,1150 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -// ============================================================================= -// Register block : UART -// Version : 1 -// Bus type : apb -// ============================================================================= -#ifndef _HARDWARE_REGS_UART_H -#define _HARDWARE_REGS_UART_H -// ============================================================================= -// Register : UART_UARTDR -// Description : Data Register, UARTDR -#define UART_UARTDR_OFFSET _u(0x00000000) -#define UART_UARTDR_BITS _u(0x00000fff) -#define UART_UARTDR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : UART_UARTDR_OE -// Description : Overrun error. This bit is set to 1 if data is received and the -// receive FIFO is already full. This is cleared to 0 once there -// is an empty space in the FIFO and a new character can be -// written to it. -#define UART_UARTDR_OE_RESET "-" -#define UART_UARTDR_OE_BITS _u(0x00000800) -#define UART_UARTDR_OE_MSB _u(11) -#define UART_UARTDR_OE_LSB _u(11) -#define UART_UARTDR_OE_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : UART_UARTDR_BE -// Description : Break error. This bit is set to 1 if a break condition was -// detected, indicating that the received data input was held LOW -// for longer than a full-word transmission time (defined as -// start, data, parity and stop bits). In FIFO mode, this error is -// associated with the character at the top of the FIFO. When a -// break occurs, only one 0 character is loaded into the FIFO. The -// next character is only enabled after the receive data input -// goes to a 1 (marking state), and the next valid start bit is -// received. -#define UART_UARTDR_BE_RESET "-" -#define UART_UARTDR_BE_BITS _u(0x00000400) -#define UART_UARTDR_BE_MSB _u(10) -#define UART_UARTDR_BE_LSB _u(10) -#define UART_UARTDR_BE_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : UART_UARTDR_PE -// Description : Parity error. When set to 1, it indicates that the parity of -// the received data character does not match the parity that the -// EPS and SPS bits in the Line Control Register, UARTLCR_H. In -// FIFO mode, this error is associated with the character at the -// top of the FIFO. -#define UART_UARTDR_PE_RESET "-" -#define UART_UARTDR_PE_BITS _u(0x00000200) -#define UART_UARTDR_PE_MSB _u(9) -#define UART_UARTDR_PE_LSB _u(9) -#define UART_UARTDR_PE_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : UART_UARTDR_FE -// Description : Framing error. When set to 1, it indicates that the received -// character did not have a valid stop bit (a valid stop bit is -// 1). In FIFO mode, this error is associated with the character -// at the top of the FIFO. -#define UART_UARTDR_FE_RESET "-" -#define UART_UARTDR_FE_BITS _u(0x00000100) -#define UART_UARTDR_FE_MSB _u(8) -#define UART_UARTDR_FE_LSB _u(8) -#define UART_UARTDR_FE_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : UART_UARTDR_DATA -// Description : Receive (read) data character. Transmit (write) data character. -#define UART_UARTDR_DATA_RESET "-" -#define UART_UARTDR_DATA_BITS _u(0x000000ff) -#define UART_UARTDR_DATA_MSB _u(7) -#define UART_UARTDR_DATA_LSB _u(0) -#define UART_UARTDR_DATA_ACCESS "RWF" -// ============================================================================= -// Register : UART_UARTRSR -// Description : Receive Status Register/Error Clear Register, UARTRSR/UARTECR -#define UART_UARTRSR_OFFSET _u(0x00000004) -#define UART_UARTRSR_BITS _u(0x0000000f) -#define UART_UARTRSR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : UART_UARTRSR_OE -// Description : Overrun error. This bit is set to 1 if data is received and the -// FIFO is already full. This bit is cleared to 0 by a write to -// UARTECR. The FIFO contents remain valid because no more data is -// written when the FIFO is full, only the contents of the shift -// register are overwritten. The CPU must now read the data, to -// empty the FIFO. -#define UART_UARTRSR_OE_RESET _u(0x0) -#define UART_UARTRSR_OE_BITS _u(0x00000008) -#define UART_UARTRSR_OE_MSB _u(3) -#define UART_UARTRSR_OE_LSB _u(3) -#define UART_UARTRSR_OE_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : UART_UARTRSR_BE -// Description : Break error. This bit is set to 1 if a break condition was -// detected, indicating that the received data input was held LOW -// for longer than a full-word transmission time (defined as -// start, data, parity, and stop bits). This bit is cleared to 0 -// after a write to UARTECR. In FIFO mode, this error is -// associated with the character at the top of the FIFO. When a -// break occurs, only one 0 character is loaded into the FIFO. The -// next character is only enabled after the receive data input -// goes to a 1 (marking state) and the next valid start bit is -// received. -#define UART_UARTRSR_BE_RESET _u(0x0) -#define UART_UARTRSR_BE_BITS _u(0x00000004) -#define UART_UARTRSR_BE_MSB _u(2) -#define UART_UARTRSR_BE_LSB _u(2) -#define UART_UARTRSR_BE_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : UART_UARTRSR_PE -// Description : Parity error. When set to 1, it indicates that the parity of -// the received data character does not match the parity that the -// EPS and SPS bits in the Line Control Register, UARTLCR_H. This -// bit is cleared to 0 by a write to UARTECR. In FIFO mode, this -// error is associated with the character at the top of the FIFO. -#define UART_UARTRSR_PE_RESET _u(0x0) -#define UART_UARTRSR_PE_BITS _u(0x00000002) -#define UART_UARTRSR_PE_MSB _u(1) -#define UART_UARTRSR_PE_LSB _u(1) -#define UART_UARTRSR_PE_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : UART_UARTRSR_FE -// Description : Framing error. When set to 1, it indicates that the received -// character did not have a valid stop bit (a valid stop bit is -// 1). This bit is cleared to 0 by a write to UARTECR. In FIFO -// mode, this error is associated with the character at the top of -// the FIFO. -#define UART_UARTRSR_FE_RESET _u(0x0) -#define UART_UARTRSR_FE_BITS _u(0x00000001) -#define UART_UARTRSR_FE_MSB _u(0) -#define UART_UARTRSR_FE_LSB _u(0) -#define UART_UARTRSR_FE_ACCESS "WC" -// ============================================================================= -// Register : UART_UARTFR -// Description : Flag Register, UARTFR -#define UART_UARTFR_OFFSET _u(0x00000018) -#define UART_UARTFR_BITS _u(0x000001ff) -#define UART_UARTFR_RESET _u(0x00000090) -// ----------------------------------------------------------------------------- -// Field : UART_UARTFR_RI -// Description : Ring indicator. This bit is the complement of the UART ring -// indicator, nUARTRI, modem status input. That is, the bit is 1 -// when nUARTRI is LOW. -#define UART_UARTFR_RI_RESET "-" -#define UART_UARTFR_RI_BITS _u(0x00000100) -#define UART_UARTFR_RI_MSB _u(8) -#define UART_UARTFR_RI_LSB _u(8) -#define UART_UARTFR_RI_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : UART_UARTFR_TXFE -// Description : Transmit FIFO empty. The meaning of this bit depends on the -// state of the FEN bit in the Line Control Register, UARTLCR_H. -// If the FIFO is disabled, this bit is set when the transmit -// holding register is empty. If the FIFO is enabled, the TXFE bit -// is set when the transmit FIFO is empty. This bit does not -// indicate if there is data in the transmit shift register. -#define UART_UARTFR_TXFE_RESET _u(0x1) -#define UART_UARTFR_TXFE_BITS _u(0x00000080) -#define UART_UARTFR_TXFE_MSB _u(7) -#define UART_UARTFR_TXFE_LSB _u(7) -#define UART_UARTFR_TXFE_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : UART_UARTFR_RXFF -// Description : Receive FIFO full. The meaning of this bit depends on the state -// of the FEN bit in the UARTLCR_H Register. If the FIFO is -// disabled, this bit is set when the receive holding register is -// full. If the FIFO is enabled, the RXFF bit is set when the -// receive FIFO is full. -#define UART_UARTFR_RXFF_RESET _u(0x0) -#define UART_UARTFR_RXFF_BITS _u(0x00000040) -#define UART_UARTFR_RXFF_MSB _u(6) -#define UART_UARTFR_RXFF_LSB _u(6) -#define UART_UARTFR_RXFF_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : UART_UARTFR_TXFF -// Description : Transmit FIFO full. The meaning of this bit depends on the -// state of the FEN bit in the UARTLCR_H Register. If the FIFO is -// disabled, this bit is set when the transmit holding register is -// full. If the FIFO is enabled, the TXFF bit is set when the -// transmit FIFO is full. -#define UART_UARTFR_TXFF_RESET _u(0x0) -#define UART_UARTFR_TXFF_BITS _u(0x00000020) -#define UART_UARTFR_TXFF_MSB _u(5) -#define UART_UARTFR_TXFF_LSB _u(5) -#define UART_UARTFR_TXFF_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : UART_UARTFR_RXFE -// Description : Receive FIFO empty. The meaning of this bit depends on the -// state of the FEN bit in the UARTLCR_H Register. If the FIFO is -// disabled, this bit is set when the receive holding register is -// empty. If the FIFO is enabled, the RXFE bit is set when the -// receive FIFO is empty. -#define UART_UARTFR_RXFE_RESET _u(0x1) -#define UART_UARTFR_RXFE_BITS _u(0x00000010) -#define UART_UARTFR_RXFE_MSB _u(4) -#define UART_UARTFR_RXFE_LSB _u(4) -#define UART_UARTFR_RXFE_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : UART_UARTFR_BUSY -// Description : UART busy. If this bit is set to 1, the UART is busy -// transmitting data. This bit remains set until the complete -// byte, including all the stop bits, has been sent from the shift -// register. This bit is set as soon as the transmit FIFO becomes -// non-empty, regardless of whether the UART is enabled or not. -#define UART_UARTFR_BUSY_RESET _u(0x0) -#define UART_UARTFR_BUSY_BITS _u(0x00000008) -#define UART_UARTFR_BUSY_MSB _u(3) -#define UART_UARTFR_BUSY_LSB _u(3) -#define UART_UARTFR_BUSY_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : UART_UARTFR_DCD -// Description : Data carrier detect. This bit is the complement of the UART -// data carrier detect, nUARTDCD, modem status input. That is, the -// bit is 1 when nUARTDCD is LOW. -#define UART_UARTFR_DCD_RESET "-" -#define UART_UARTFR_DCD_BITS _u(0x00000004) -#define UART_UARTFR_DCD_MSB _u(2) -#define UART_UARTFR_DCD_LSB _u(2) -#define UART_UARTFR_DCD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : UART_UARTFR_DSR -// Description : Data set ready. This bit is the complement of the UART data set -// ready, nUARTDSR, modem status input. That is, the bit is 1 when -// nUARTDSR is LOW. -#define UART_UARTFR_DSR_RESET "-" -#define UART_UARTFR_DSR_BITS _u(0x00000002) -#define UART_UARTFR_DSR_MSB _u(1) -#define UART_UARTFR_DSR_LSB _u(1) -#define UART_UARTFR_DSR_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : UART_UARTFR_CTS -// Description : Clear to send. This bit is the complement of the UART clear to -// send, nUARTCTS, modem status input. That is, the bit is 1 when -// nUARTCTS is LOW. -#define UART_UARTFR_CTS_RESET "-" -#define UART_UARTFR_CTS_BITS _u(0x00000001) -#define UART_UARTFR_CTS_MSB _u(0) -#define UART_UARTFR_CTS_LSB _u(0) -#define UART_UARTFR_CTS_ACCESS "RO" -// ============================================================================= -// Register : UART_UARTILPR -// Description : IrDA Low-Power Counter Register, UARTILPR -#define UART_UARTILPR_OFFSET _u(0x00000020) -#define UART_UARTILPR_BITS _u(0x000000ff) -#define UART_UARTILPR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : UART_UARTILPR_ILPDVSR -// Description : 8-bit low-power divisor value. These bits are cleared to 0 at -// reset. -#define UART_UARTILPR_ILPDVSR_RESET _u(0x00) -#define UART_UARTILPR_ILPDVSR_BITS _u(0x000000ff) -#define UART_UARTILPR_ILPDVSR_MSB _u(7) -#define UART_UARTILPR_ILPDVSR_LSB _u(0) -#define UART_UARTILPR_ILPDVSR_ACCESS "RW" -// ============================================================================= -// Register : UART_UARTIBRD -// Description : Integer Baud Rate Register, UARTIBRD -#define UART_UARTIBRD_OFFSET _u(0x00000024) -#define UART_UARTIBRD_BITS _u(0x0000ffff) -#define UART_UARTIBRD_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : UART_UARTIBRD_BAUD_DIVINT -// Description : The integer baud rate divisor. These bits are cleared to 0 on -// reset. -#define UART_UARTIBRD_BAUD_DIVINT_RESET _u(0x0000) -#define UART_UARTIBRD_BAUD_DIVINT_BITS _u(0x0000ffff) -#define UART_UARTIBRD_BAUD_DIVINT_MSB _u(15) -#define UART_UARTIBRD_BAUD_DIVINT_LSB _u(0) -#define UART_UARTIBRD_BAUD_DIVINT_ACCESS "RW" -// ============================================================================= -// Register : UART_UARTFBRD -// Description : Fractional Baud Rate Register, UARTFBRD -#define UART_UARTFBRD_OFFSET _u(0x00000028) -#define UART_UARTFBRD_BITS _u(0x0000003f) -#define UART_UARTFBRD_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : UART_UARTFBRD_BAUD_DIVFRAC -// Description : The fractional baud rate divisor. These bits are cleared to 0 -// on reset. -#define UART_UARTFBRD_BAUD_DIVFRAC_RESET _u(0x00) -#define UART_UARTFBRD_BAUD_DIVFRAC_BITS _u(0x0000003f) -#define UART_UARTFBRD_BAUD_DIVFRAC_MSB _u(5) -#define UART_UARTFBRD_BAUD_DIVFRAC_LSB _u(0) -#define UART_UARTFBRD_BAUD_DIVFRAC_ACCESS "RW" -// ============================================================================= -// Register : UART_UARTLCR_H -// Description : Line Control Register, UARTLCR_H -#define UART_UARTLCR_H_OFFSET _u(0x0000002c) -#define UART_UARTLCR_H_BITS _u(0x000000ff) -#define UART_UARTLCR_H_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : UART_UARTLCR_H_SPS -// Description : Stick parity select. 0 = stick parity is disabled 1 = either: * -// if the EPS bit is 0 then the parity bit is transmitted and -// checked as a 1 * if the EPS bit is 1 then the parity bit is -// transmitted and checked as a 0. This bit has no effect when the -// PEN bit disables parity checking and generation. -#define UART_UARTLCR_H_SPS_RESET _u(0x0) -#define UART_UARTLCR_H_SPS_BITS _u(0x00000080) -#define UART_UARTLCR_H_SPS_MSB _u(7) -#define UART_UARTLCR_H_SPS_LSB _u(7) -#define UART_UARTLCR_H_SPS_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : UART_UARTLCR_H_WLEN -// Description : Word length. These bits indicate the number of data bits -// transmitted or received in a frame as follows: b11 = 8 bits b10 -// = 7 bits b01 = 6 bits b00 = 5 bits. -#define UART_UARTLCR_H_WLEN_RESET _u(0x0) -#define UART_UARTLCR_H_WLEN_BITS _u(0x00000060) -#define UART_UARTLCR_H_WLEN_MSB _u(6) -#define UART_UARTLCR_H_WLEN_LSB _u(5) -#define UART_UARTLCR_H_WLEN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : UART_UARTLCR_H_FEN -// Description : Enable FIFOs: 0 = FIFOs are disabled (character mode) that is, -// the FIFOs become 1-byte-deep holding registers 1 = transmit and -// receive FIFO buffers are enabled (FIFO mode). -#define UART_UARTLCR_H_FEN_RESET _u(0x0) -#define UART_UARTLCR_H_FEN_BITS _u(0x00000010) -#define UART_UARTLCR_H_FEN_MSB _u(4) -#define UART_UARTLCR_H_FEN_LSB _u(4) -#define UART_UARTLCR_H_FEN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : UART_UARTLCR_H_STP2 -// Description : Two stop bits select. If this bit is set to 1, two stop bits -// are transmitted at the end of the frame. The receive logic does -// not check for two stop bits being received. -#define UART_UARTLCR_H_STP2_RESET _u(0x0) -#define UART_UARTLCR_H_STP2_BITS _u(0x00000008) -#define UART_UARTLCR_H_STP2_MSB _u(3) -#define UART_UARTLCR_H_STP2_LSB _u(3) -#define UART_UARTLCR_H_STP2_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : UART_UARTLCR_H_EPS -// Description : Even parity select. Controls the type of parity the UART uses -// during transmission and reception: 0 = odd parity. The UART -// generates or checks for an odd number of 1s in the data and -// parity bits. 1 = even parity. The UART generates or checks for -// an even number of 1s in the data and parity bits. This bit has -// no effect when the PEN bit disables parity checking and -// generation. -#define UART_UARTLCR_H_EPS_RESET _u(0x0) -#define UART_UARTLCR_H_EPS_BITS _u(0x00000004) -#define UART_UARTLCR_H_EPS_MSB _u(2) -#define UART_UARTLCR_H_EPS_LSB _u(2) -#define UART_UARTLCR_H_EPS_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : UART_UARTLCR_H_PEN -// Description : Parity enable: 0 = parity is disabled and no parity bit added -// to the data frame 1 = parity checking and generation is -// enabled. -#define UART_UARTLCR_H_PEN_RESET _u(0x0) -#define UART_UARTLCR_H_PEN_BITS _u(0x00000002) -#define UART_UARTLCR_H_PEN_MSB _u(1) -#define UART_UARTLCR_H_PEN_LSB _u(1) -#define UART_UARTLCR_H_PEN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : UART_UARTLCR_H_BRK -// Description : Send break. If this bit is set to 1, a low-level is continually -// output on the UARTTXD output, after completing transmission of -// the current character. For the proper execution of the break -// command, the software must set this bit for at least two -// complete frames. For normal use, this bit must be cleared to 0. -#define UART_UARTLCR_H_BRK_RESET _u(0x0) -#define UART_UARTLCR_H_BRK_BITS _u(0x00000001) -#define UART_UARTLCR_H_BRK_MSB _u(0) -#define UART_UARTLCR_H_BRK_LSB _u(0) -#define UART_UARTLCR_H_BRK_ACCESS "RW" -// ============================================================================= -// Register : UART_UARTCR -// Description : Control Register, UARTCR -#define UART_UARTCR_OFFSET _u(0x00000030) -#define UART_UARTCR_BITS _u(0x0000ff87) -#define UART_UARTCR_RESET _u(0x00000300) -// ----------------------------------------------------------------------------- -// Field : UART_UARTCR_CTSEN -// Description : CTS hardware flow control enable. If this bit is set to 1, CTS -// hardware flow control is enabled. Data is only transmitted when -// the nUARTCTS signal is asserted. -#define UART_UARTCR_CTSEN_RESET _u(0x0) -#define UART_UARTCR_CTSEN_BITS _u(0x00008000) -#define UART_UARTCR_CTSEN_MSB _u(15) -#define UART_UARTCR_CTSEN_LSB _u(15) -#define UART_UARTCR_CTSEN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : UART_UARTCR_RTSEN -// Description : RTS hardware flow control enable. If this bit is set to 1, RTS -// hardware flow control is enabled. Data is only requested when -// there is space in the receive FIFO for it to be received. -#define UART_UARTCR_RTSEN_RESET _u(0x0) -#define UART_UARTCR_RTSEN_BITS _u(0x00004000) -#define UART_UARTCR_RTSEN_MSB _u(14) -#define UART_UARTCR_RTSEN_LSB _u(14) -#define UART_UARTCR_RTSEN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : UART_UARTCR_OUT2 -// Description : This bit is the complement of the UART Out2 (nUARTOut2) modem -// status output. That is, when the bit is programmed to a 1, the -// output is 0. For DTE this can be used as Ring Indicator (RI). -#define UART_UARTCR_OUT2_RESET _u(0x0) -#define UART_UARTCR_OUT2_BITS _u(0x00002000) -#define UART_UARTCR_OUT2_MSB _u(13) -#define UART_UARTCR_OUT2_LSB _u(13) -#define UART_UARTCR_OUT2_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : UART_UARTCR_OUT1 -// Description : This bit is the complement of the UART Out1 (nUARTOut1) modem -// status output. That is, when the bit is programmed to a 1 the -// output is 0. For DTE this can be used as Data Carrier Detect -// (DCD). -#define UART_UARTCR_OUT1_RESET _u(0x0) -#define UART_UARTCR_OUT1_BITS _u(0x00001000) -#define UART_UARTCR_OUT1_MSB _u(12) -#define UART_UARTCR_OUT1_LSB _u(12) -#define UART_UARTCR_OUT1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : UART_UARTCR_RTS -// Description : Request to send. This bit is the complement of the UART request -// to send, nUARTRTS, modem status output. That is, when the bit -// is programmed to a 1 then nUARTRTS is LOW. -#define UART_UARTCR_RTS_RESET _u(0x0) -#define UART_UARTCR_RTS_BITS _u(0x00000800) -#define UART_UARTCR_RTS_MSB _u(11) -#define UART_UARTCR_RTS_LSB _u(11) -#define UART_UARTCR_RTS_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : UART_UARTCR_DTR -// Description : Data transmit ready. This bit is the complement of the UART -// data transmit ready, nUARTDTR, modem status output. That is, -// when the bit is programmed to a 1 then nUARTDTR is LOW. -#define UART_UARTCR_DTR_RESET _u(0x0) -#define UART_UARTCR_DTR_BITS _u(0x00000400) -#define UART_UARTCR_DTR_MSB _u(10) -#define UART_UARTCR_DTR_LSB _u(10) -#define UART_UARTCR_DTR_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : UART_UARTCR_RXE -// Description : Receive enable. If this bit is set to 1, the receive section of -// the UART is enabled. Data reception occurs for either UART -// signals or SIR signals depending on the setting of the SIREN -// bit. When the UART is disabled in the middle of reception, it -// completes the current character before stopping. -#define UART_UARTCR_RXE_RESET _u(0x1) -#define UART_UARTCR_RXE_BITS _u(0x00000200) -#define UART_UARTCR_RXE_MSB _u(9) -#define UART_UARTCR_RXE_LSB _u(9) -#define UART_UARTCR_RXE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : UART_UARTCR_TXE -// Description : Transmit enable. If this bit is set to 1, the transmit section -// of the UART is enabled. Data transmission occurs for either -// UART signals, or SIR signals depending on the setting of the -// SIREN bit. When the UART is disabled in the middle of -// transmission, it completes the current character before -// stopping. -#define UART_UARTCR_TXE_RESET _u(0x1) -#define UART_UARTCR_TXE_BITS _u(0x00000100) -#define UART_UARTCR_TXE_MSB _u(8) -#define UART_UARTCR_TXE_LSB _u(8) -#define UART_UARTCR_TXE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : UART_UARTCR_LBE -// Description : Loopback enable. If this bit is set to 1 and the SIREN bit is -// set to 1 and the SIRTEST bit in the Test Control Register, -// UARTTCR is set to 1, then the nSIROUT path is inverted, and fed -// through to the SIRIN path. The SIRTEST bit in the test register -// must be set to 1 to override the normal half-duplex SIR -// operation. This must be the requirement for accessing the test -// registers during normal operation, and SIRTEST must be cleared -// to 0 when loopback testing is finished. This feature reduces -// the amount of external coupling required during system test. If -// this bit is set to 1, and the SIRTEST bit is set to 0, the -// UARTTXD path is fed through to the UARTRXD path. In either SIR -// mode or UART mode, when this bit is set, the modem outputs are -// also fed through to the modem inputs. This bit is cleared to 0 -// on reset, to disable loopback. -#define UART_UARTCR_LBE_RESET _u(0x0) -#define UART_UARTCR_LBE_BITS _u(0x00000080) -#define UART_UARTCR_LBE_MSB _u(7) -#define UART_UARTCR_LBE_LSB _u(7) -#define UART_UARTCR_LBE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : UART_UARTCR_SIRLP -// Description : SIR low-power IrDA mode. This bit selects the IrDA encoding -// mode. If this bit is cleared to 0, low-level bits are -// transmitted as an active high pulse with a width of 3 / 16th of -// the bit period. If this bit is set to 1, low-level bits are -// transmitted with a pulse width that is 3 times the period of -// the IrLPBaud16 input signal, regardless of the selected bit -// rate. Setting this bit uses less power, but might reduce -// transmission distances. -#define UART_UARTCR_SIRLP_RESET _u(0x0) -#define UART_UARTCR_SIRLP_BITS _u(0x00000004) -#define UART_UARTCR_SIRLP_MSB _u(2) -#define UART_UARTCR_SIRLP_LSB _u(2) -#define UART_UARTCR_SIRLP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : UART_UARTCR_SIREN -// Description : SIR enable: 0 = IrDA SIR ENDEC is disabled. nSIROUT remains LOW -// (no light pulse generated), and signal transitions on SIRIN -// have no effect. 1 = IrDA SIR ENDEC is enabled. Data is -// transmitted and received on nSIROUT and SIRIN. UARTTXD remains -// HIGH, in the marking state. Signal transitions on UARTRXD or -// modem status inputs have no effect. This bit has no effect if -// the UARTEN bit disables the UART. -#define UART_UARTCR_SIREN_RESET _u(0x0) -#define UART_UARTCR_SIREN_BITS _u(0x00000002) -#define UART_UARTCR_SIREN_MSB _u(1) -#define UART_UARTCR_SIREN_LSB _u(1) -#define UART_UARTCR_SIREN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : UART_UARTCR_UARTEN -// Description : UART enable: 0 = UART is disabled. If the UART is disabled in -// the middle of transmission or reception, it completes the -// current character before stopping. 1 = the UART is enabled. -// Data transmission and reception occurs for either UART signals -// or SIR signals depending on the setting of the SIREN bit. -#define UART_UARTCR_UARTEN_RESET _u(0x0) -#define UART_UARTCR_UARTEN_BITS _u(0x00000001) -#define UART_UARTCR_UARTEN_MSB _u(0) -#define UART_UARTCR_UARTEN_LSB _u(0) -#define UART_UARTCR_UARTEN_ACCESS "RW" -// ============================================================================= -// Register : UART_UARTIFLS -// Description : Interrupt FIFO Level Select Register, UARTIFLS -#define UART_UARTIFLS_OFFSET _u(0x00000034) -#define UART_UARTIFLS_BITS _u(0x0000003f) -#define UART_UARTIFLS_RESET _u(0x00000012) -// ----------------------------------------------------------------------------- -// Field : UART_UARTIFLS_RXIFLSEL -// Description : Receive interrupt FIFO level select. The trigger points for the -// receive interrupt are as follows: b000 = Receive FIFO becomes -// >= 1 / 8 full b001 = Receive FIFO becomes >= 1 / 4 full b010 = -// Receive FIFO becomes >= 1 / 2 full b011 = Receive FIFO becomes -// >= 3 / 4 full b100 = Receive FIFO becomes >= 7 / 8 full -// b101-b111 = reserved. -#define UART_UARTIFLS_RXIFLSEL_RESET _u(0x2) -#define UART_UARTIFLS_RXIFLSEL_BITS _u(0x00000038) -#define UART_UARTIFLS_RXIFLSEL_MSB _u(5) -#define UART_UARTIFLS_RXIFLSEL_LSB _u(3) -#define UART_UARTIFLS_RXIFLSEL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : UART_UARTIFLS_TXIFLSEL -// Description : Transmit interrupt FIFO level select. The trigger points for -// the transmit interrupt are as follows: b000 = Transmit FIFO -// becomes <= 1 / 8 full b001 = Transmit FIFO becomes <= 1 / 4 -// full b010 = Transmit FIFO becomes <= 1 / 2 full b011 = Transmit -// FIFO becomes <= 3 / 4 full b100 = Transmit FIFO becomes <= 7 / -// 8 full b101-b111 = reserved. -#define UART_UARTIFLS_TXIFLSEL_RESET _u(0x2) -#define UART_UARTIFLS_TXIFLSEL_BITS _u(0x00000007) -#define UART_UARTIFLS_TXIFLSEL_MSB _u(2) -#define UART_UARTIFLS_TXIFLSEL_LSB _u(0) -#define UART_UARTIFLS_TXIFLSEL_ACCESS "RW" -// ============================================================================= -// Register : UART_UARTIMSC -// Description : Interrupt Mask Set/Clear Register, UARTIMSC -#define UART_UARTIMSC_OFFSET _u(0x00000038) -#define UART_UARTIMSC_BITS _u(0x000007ff) -#define UART_UARTIMSC_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : UART_UARTIMSC_OEIM -// Description : Overrun error interrupt mask. A read returns the current mask -// for the UARTOEINTR interrupt. On a write of 1, the mask of the -// UARTOEINTR interrupt is set. A write of 0 clears the mask. -#define UART_UARTIMSC_OEIM_RESET _u(0x0) -#define UART_UARTIMSC_OEIM_BITS _u(0x00000400) -#define UART_UARTIMSC_OEIM_MSB _u(10) -#define UART_UARTIMSC_OEIM_LSB _u(10) -#define UART_UARTIMSC_OEIM_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : UART_UARTIMSC_BEIM -// Description : Break error interrupt mask. A read returns the current mask for -// the UARTBEINTR interrupt. On a write of 1, the mask of the -// UARTBEINTR interrupt is set. A write of 0 clears the mask. -#define UART_UARTIMSC_BEIM_RESET _u(0x0) -#define UART_UARTIMSC_BEIM_BITS _u(0x00000200) -#define UART_UARTIMSC_BEIM_MSB _u(9) -#define UART_UARTIMSC_BEIM_LSB _u(9) -#define UART_UARTIMSC_BEIM_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : UART_UARTIMSC_PEIM -// Description : Parity error interrupt mask. A read returns the current mask -// for the UARTPEINTR interrupt. On a write of 1, the mask of the -// UARTPEINTR interrupt is set. A write of 0 clears the mask. -#define UART_UARTIMSC_PEIM_RESET _u(0x0) -#define UART_UARTIMSC_PEIM_BITS _u(0x00000100) -#define UART_UARTIMSC_PEIM_MSB _u(8) -#define UART_UARTIMSC_PEIM_LSB _u(8) -#define UART_UARTIMSC_PEIM_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : UART_UARTIMSC_FEIM -// Description : Framing error interrupt mask. A read returns the current mask -// for the UARTFEINTR interrupt. On a write of 1, the mask of the -// UARTFEINTR interrupt is set. A write of 0 clears the mask. -#define UART_UARTIMSC_FEIM_RESET _u(0x0) -#define UART_UARTIMSC_FEIM_BITS _u(0x00000080) -#define UART_UARTIMSC_FEIM_MSB _u(7) -#define UART_UARTIMSC_FEIM_LSB _u(7) -#define UART_UARTIMSC_FEIM_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : UART_UARTIMSC_RTIM -// Description : Receive timeout interrupt mask. A read returns the current mask -// for the UARTRTINTR interrupt. On a write of 1, the mask of the -// UARTRTINTR interrupt is set. A write of 0 clears the mask. -#define UART_UARTIMSC_RTIM_RESET _u(0x0) -#define UART_UARTIMSC_RTIM_BITS _u(0x00000040) -#define UART_UARTIMSC_RTIM_MSB _u(6) -#define UART_UARTIMSC_RTIM_LSB _u(6) -#define UART_UARTIMSC_RTIM_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : UART_UARTIMSC_TXIM -// Description : Transmit interrupt mask. A read returns the current mask for -// the UARTTXINTR interrupt. On a write of 1, the mask of the -// UARTTXINTR interrupt is set. A write of 0 clears the mask. -#define UART_UARTIMSC_TXIM_RESET _u(0x0) -#define UART_UARTIMSC_TXIM_BITS _u(0x00000020) -#define UART_UARTIMSC_TXIM_MSB _u(5) -#define UART_UARTIMSC_TXIM_LSB _u(5) -#define UART_UARTIMSC_TXIM_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : UART_UARTIMSC_RXIM -// Description : Receive interrupt mask. A read returns the current mask for the -// UARTRXINTR interrupt. On a write of 1, the mask of the -// UARTRXINTR interrupt is set. A write of 0 clears the mask. -#define UART_UARTIMSC_RXIM_RESET _u(0x0) -#define UART_UARTIMSC_RXIM_BITS _u(0x00000010) -#define UART_UARTIMSC_RXIM_MSB _u(4) -#define UART_UARTIMSC_RXIM_LSB _u(4) -#define UART_UARTIMSC_RXIM_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : UART_UARTIMSC_DSRMIM -// Description : nUARTDSR modem interrupt mask. A read returns the current mask -// for the UARTDSRINTR interrupt. On a write of 1, the mask of the -// UARTDSRINTR interrupt is set. A write of 0 clears the mask. -#define UART_UARTIMSC_DSRMIM_RESET _u(0x0) -#define UART_UARTIMSC_DSRMIM_BITS _u(0x00000008) -#define UART_UARTIMSC_DSRMIM_MSB _u(3) -#define UART_UARTIMSC_DSRMIM_LSB _u(3) -#define UART_UARTIMSC_DSRMIM_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : UART_UARTIMSC_DCDMIM -// Description : nUARTDCD modem interrupt mask. A read returns the current mask -// for the UARTDCDINTR interrupt. On a write of 1, the mask of the -// UARTDCDINTR interrupt is set. A write of 0 clears the mask. -#define UART_UARTIMSC_DCDMIM_RESET _u(0x0) -#define UART_UARTIMSC_DCDMIM_BITS _u(0x00000004) -#define UART_UARTIMSC_DCDMIM_MSB _u(2) -#define UART_UARTIMSC_DCDMIM_LSB _u(2) -#define UART_UARTIMSC_DCDMIM_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : UART_UARTIMSC_CTSMIM -// Description : nUARTCTS modem interrupt mask. A read returns the current mask -// for the UARTCTSINTR interrupt. On a write of 1, the mask of the -// UARTCTSINTR interrupt is set. A write of 0 clears the mask. -#define UART_UARTIMSC_CTSMIM_RESET _u(0x0) -#define UART_UARTIMSC_CTSMIM_BITS _u(0x00000002) -#define UART_UARTIMSC_CTSMIM_MSB _u(1) -#define UART_UARTIMSC_CTSMIM_LSB _u(1) -#define UART_UARTIMSC_CTSMIM_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : UART_UARTIMSC_RIMIM -// Description : nUARTRI modem interrupt mask. A read returns the current mask -// for the UARTRIINTR interrupt. On a write of 1, the mask of the -// UARTRIINTR interrupt is set. A write of 0 clears the mask. -#define UART_UARTIMSC_RIMIM_RESET _u(0x0) -#define UART_UARTIMSC_RIMIM_BITS _u(0x00000001) -#define UART_UARTIMSC_RIMIM_MSB _u(0) -#define UART_UARTIMSC_RIMIM_LSB _u(0) -#define UART_UARTIMSC_RIMIM_ACCESS "RW" -// ============================================================================= -// Register : UART_UARTRIS -// Description : Raw Interrupt Status Register, UARTRIS -#define UART_UARTRIS_OFFSET _u(0x0000003c) -#define UART_UARTRIS_BITS _u(0x000007ff) -#define UART_UARTRIS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : UART_UARTRIS_OERIS -// Description : Overrun error interrupt status. Returns the raw interrupt state -// of the UARTOEINTR interrupt. -#define UART_UARTRIS_OERIS_RESET _u(0x0) -#define UART_UARTRIS_OERIS_BITS _u(0x00000400) -#define UART_UARTRIS_OERIS_MSB _u(10) -#define UART_UARTRIS_OERIS_LSB _u(10) -#define UART_UARTRIS_OERIS_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : UART_UARTRIS_BERIS -// Description : Break error interrupt status. Returns the raw interrupt state -// of the UARTBEINTR interrupt. -#define UART_UARTRIS_BERIS_RESET _u(0x0) -#define UART_UARTRIS_BERIS_BITS _u(0x00000200) -#define UART_UARTRIS_BERIS_MSB _u(9) -#define UART_UARTRIS_BERIS_LSB _u(9) -#define UART_UARTRIS_BERIS_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : UART_UARTRIS_PERIS -// Description : Parity error interrupt status. Returns the raw interrupt state -// of the UARTPEINTR interrupt. -#define UART_UARTRIS_PERIS_RESET _u(0x0) -#define UART_UARTRIS_PERIS_BITS _u(0x00000100) -#define UART_UARTRIS_PERIS_MSB _u(8) -#define UART_UARTRIS_PERIS_LSB _u(8) -#define UART_UARTRIS_PERIS_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : UART_UARTRIS_FERIS -// Description : Framing error interrupt status. Returns the raw interrupt state -// of the UARTFEINTR interrupt. -#define UART_UARTRIS_FERIS_RESET _u(0x0) -#define UART_UARTRIS_FERIS_BITS _u(0x00000080) -#define UART_UARTRIS_FERIS_MSB _u(7) -#define UART_UARTRIS_FERIS_LSB _u(7) -#define UART_UARTRIS_FERIS_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : UART_UARTRIS_RTRIS -// Description : Receive timeout interrupt status. Returns the raw interrupt -// state of the UARTRTINTR interrupt. a -#define UART_UARTRIS_RTRIS_RESET _u(0x0) -#define UART_UARTRIS_RTRIS_BITS _u(0x00000040) -#define UART_UARTRIS_RTRIS_MSB _u(6) -#define UART_UARTRIS_RTRIS_LSB _u(6) -#define UART_UARTRIS_RTRIS_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : UART_UARTRIS_TXRIS -// Description : Transmit interrupt status. Returns the raw interrupt state of -// the UARTTXINTR interrupt. -#define UART_UARTRIS_TXRIS_RESET _u(0x0) -#define UART_UARTRIS_TXRIS_BITS _u(0x00000020) -#define UART_UARTRIS_TXRIS_MSB _u(5) -#define UART_UARTRIS_TXRIS_LSB _u(5) -#define UART_UARTRIS_TXRIS_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : UART_UARTRIS_RXRIS -// Description : Receive interrupt status. Returns the raw interrupt state of -// the UARTRXINTR interrupt. -#define UART_UARTRIS_RXRIS_RESET _u(0x0) -#define UART_UARTRIS_RXRIS_BITS _u(0x00000010) -#define UART_UARTRIS_RXRIS_MSB _u(4) -#define UART_UARTRIS_RXRIS_LSB _u(4) -#define UART_UARTRIS_RXRIS_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : UART_UARTRIS_DSRRMIS -// Description : nUARTDSR modem interrupt status. Returns the raw interrupt -// state of the UARTDSRINTR interrupt. -#define UART_UARTRIS_DSRRMIS_RESET "-" -#define UART_UARTRIS_DSRRMIS_BITS _u(0x00000008) -#define UART_UARTRIS_DSRRMIS_MSB _u(3) -#define UART_UARTRIS_DSRRMIS_LSB _u(3) -#define UART_UARTRIS_DSRRMIS_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : UART_UARTRIS_DCDRMIS -// Description : nUARTDCD modem interrupt status. Returns the raw interrupt -// state of the UARTDCDINTR interrupt. -#define UART_UARTRIS_DCDRMIS_RESET "-" -#define UART_UARTRIS_DCDRMIS_BITS _u(0x00000004) -#define UART_UARTRIS_DCDRMIS_MSB _u(2) -#define UART_UARTRIS_DCDRMIS_LSB _u(2) -#define UART_UARTRIS_DCDRMIS_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : UART_UARTRIS_CTSRMIS -// Description : nUARTCTS modem interrupt status. Returns the raw interrupt -// state of the UARTCTSINTR interrupt. -#define UART_UARTRIS_CTSRMIS_RESET "-" -#define UART_UARTRIS_CTSRMIS_BITS _u(0x00000002) -#define UART_UARTRIS_CTSRMIS_MSB _u(1) -#define UART_UARTRIS_CTSRMIS_LSB _u(1) -#define UART_UARTRIS_CTSRMIS_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : UART_UARTRIS_RIRMIS -// Description : nUARTRI modem interrupt status. Returns the raw interrupt state -// of the UARTRIINTR interrupt. -#define UART_UARTRIS_RIRMIS_RESET "-" -#define UART_UARTRIS_RIRMIS_BITS _u(0x00000001) -#define UART_UARTRIS_RIRMIS_MSB _u(0) -#define UART_UARTRIS_RIRMIS_LSB _u(0) -#define UART_UARTRIS_RIRMIS_ACCESS "RO" -// ============================================================================= -// Register : UART_UARTMIS -// Description : Masked Interrupt Status Register, UARTMIS -#define UART_UARTMIS_OFFSET _u(0x00000040) -#define UART_UARTMIS_BITS _u(0x000007ff) -#define UART_UARTMIS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : UART_UARTMIS_OEMIS -// Description : Overrun error masked interrupt status. Returns the masked -// interrupt state of the UARTOEINTR interrupt. -#define UART_UARTMIS_OEMIS_RESET _u(0x0) -#define UART_UARTMIS_OEMIS_BITS _u(0x00000400) -#define UART_UARTMIS_OEMIS_MSB _u(10) -#define UART_UARTMIS_OEMIS_LSB _u(10) -#define UART_UARTMIS_OEMIS_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : UART_UARTMIS_BEMIS -// Description : Break error masked interrupt status. Returns the masked -// interrupt state of the UARTBEINTR interrupt. -#define UART_UARTMIS_BEMIS_RESET _u(0x0) -#define UART_UARTMIS_BEMIS_BITS _u(0x00000200) -#define UART_UARTMIS_BEMIS_MSB _u(9) -#define UART_UARTMIS_BEMIS_LSB _u(9) -#define UART_UARTMIS_BEMIS_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : UART_UARTMIS_PEMIS -// Description : Parity error masked interrupt status. Returns the masked -// interrupt state of the UARTPEINTR interrupt. -#define UART_UARTMIS_PEMIS_RESET _u(0x0) -#define UART_UARTMIS_PEMIS_BITS _u(0x00000100) -#define UART_UARTMIS_PEMIS_MSB _u(8) -#define UART_UARTMIS_PEMIS_LSB _u(8) -#define UART_UARTMIS_PEMIS_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : UART_UARTMIS_FEMIS -// Description : Framing error masked interrupt status. Returns the masked -// interrupt state of the UARTFEINTR interrupt. -#define UART_UARTMIS_FEMIS_RESET _u(0x0) -#define UART_UARTMIS_FEMIS_BITS _u(0x00000080) -#define UART_UARTMIS_FEMIS_MSB _u(7) -#define UART_UARTMIS_FEMIS_LSB _u(7) -#define UART_UARTMIS_FEMIS_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : UART_UARTMIS_RTMIS -// Description : Receive timeout masked interrupt status. Returns the masked -// interrupt state of the UARTRTINTR interrupt. -#define UART_UARTMIS_RTMIS_RESET _u(0x0) -#define UART_UARTMIS_RTMIS_BITS _u(0x00000040) -#define UART_UARTMIS_RTMIS_MSB _u(6) -#define UART_UARTMIS_RTMIS_LSB _u(6) -#define UART_UARTMIS_RTMIS_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : UART_UARTMIS_TXMIS -// Description : Transmit masked interrupt status. Returns the masked interrupt -// state of the UARTTXINTR interrupt. -#define UART_UARTMIS_TXMIS_RESET _u(0x0) -#define UART_UARTMIS_TXMIS_BITS _u(0x00000020) -#define UART_UARTMIS_TXMIS_MSB _u(5) -#define UART_UARTMIS_TXMIS_LSB _u(5) -#define UART_UARTMIS_TXMIS_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : UART_UARTMIS_RXMIS -// Description : Receive masked interrupt status. Returns the masked interrupt -// state of the UARTRXINTR interrupt. -#define UART_UARTMIS_RXMIS_RESET _u(0x0) -#define UART_UARTMIS_RXMIS_BITS _u(0x00000010) -#define UART_UARTMIS_RXMIS_MSB _u(4) -#define UART_UARTMIS_RXMIS_LSB _u(4) -#define UART_UARTMIS_RXMIS_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : UART_UARTMIS_DSRMMIS -// Description : nUARTDSR modem masked interrupt status. Returns the masked -// interrupt state of the UARTDSRINTR interrupt. -#define UART_UARTMIS_DSRMMIS_RESET "-" -#define UART_UARTMIS_DSRMMIS_BITS _u(0x00000008) -#define UART_UARTMIS_DSRMMIS_MSB _u(3) -#define UART_UARTMIS_DSRMMIS_LSB _u(3) -#define UART_UARTMIS_DSRMMIS_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : UART_UARTMIS_DCDMMIS -// Description : nUARTDCD modem masked interrupt status. Returns the masked -// interrupt state of the UARTDCDINTR interrupt. -#define UART_UARTMIS_DCDMMIS_RESET "-" -#define UART_UARTMIS_DCDMMIS_BITS _u(0x00000004) -#define UART_UARTMIS_DCDMMIS_MSB _u(2) -#define UART_UARTMIS_DCDMMIS_LSB _u(2) -#define UART_UARTMIS_DCDMMIS_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : UART_UARTMIS_CTSMMIS -// Description : nUARTCTS modem masked interrupt status. Returns the masked -// interrupt state of the UARTCTSINTR interrupt. -#define UART_UARTMIS_CTSMMIS_RESET "-" -#define UART_UARTMIS_CTSMMIS_BITS _u(0x00000002) -#define UART_UARTMIS_CTSMMIS_MSB _u(1) -#define UART_UARTMIS_CTSMMIS_LSB _u(1) -#define UART_UARTMIS_CTSMMIS_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : UART_UARTMIS_RIMMIS -// Description : nUARTRI modem masked interrupt status. Returns the masked -// interrupt state of the UARTRIINTR interrupt. -#define UART_UARTMIS_RIMMIS_RESET "-" -#define UART_UARTMIS_RIMMIS_BITS _u(0x00000001) -#define UART_UARTMIS_RIMMIS_MSB _u(0) -#define UART_UARTMIS_RIMMIS_LSB _u(0) -#define UART_UARTMIS_RIMMIS_ACCESS "RO" -// ============================================================================= -// Register : UART_UARTICR -// Description : Interrupt Clear Register, UARTICR -#define UART_UARTICR_OFFSET _u(0x00000044) -#define UART_UARTICR_BITS _u(0x000007ff) -#define UART_UARTICR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : UART_UARTICR_OEIC -// Description : Overrun error interrupt clear. Clears the UARTOEINTR interrupt. -#define UART_UARTICR_OEIC_RESET "-" -#define UART_UARTICR_OEIC_BITS _u(0x00000400) -#define UART_UARTICR_OEIC_MSB _u(10) -#define UART_UARTICR_OEIC_LSB _u(10) -#define UART_UARTICR_OEIC_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : UART_UARTICR_BEIC -// Description : Break error interrupt clear. Clears the UARTBEINTR interrupt. -#define UART_UARTICR_BEIC_RESET "-" -#define UART_UARTICR_BEIC_BITS _u(0x00000200) -#define UART_UARTICR_BEIC_MSB _u(9) -#define UART_UARTICR_BEIC_LSB _u(9) -#define UART_UARTICR_BEIC_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : UART_UARTICR_PEIC -// Description : Parity error interrupt clear. Clears the UARTPEINTR interrupt. -#define UART_UARTICR_PEIC_RESET "-" -#define UART_UARTICR_PEIC_BITS _u(0x00000100) -#define UART_UARTICR_PEIC_MSB _u(8) -#define UART_UARTICR_PEIC_LSB _u(8) -#define UART_UARTICR_PEIC_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : UART_UARTICR_FEIC -// Description : Framing error interrupt clear. Clears the UARTFEINTR interrupt. -#define UART_UARTICR_FEIC_RESET "-" -#define UART_UARTICR_FEIC_BITS _u(0x00000080) -#define UART_UARTICR_FEIC_MSB _u(7) -#define UART_UARTICR_FEIC_LSB _u(7) -#define UART_UARTICR_FEIC_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : UART_UARTICR_RTIC -// Description : Receive timeout interrupt clear. Clears the UARTRTINTR -// interrupt. -#define UART_UARTICR_RTIC_RESET "-" -#define UART_UARTICR_RTIC_BITS _u(0x00000040) -#define UART_UARTICR_RTIC_MSB _u(6) -#define UART_UARTICR_RTIC_LSB _u(6) -#define UART_UARTICR_RTIC_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : UART_UARTICR_TXIC -// Description : Transmit interrupt clear. Clears the UARTTXINTR interrupt. -#define UART_UARTICR_TXIC_RESET "-" -#define UART_UARTICR_TXIC_BITS _u(0x00000020) -#define UART_UARTICR_TXIC_MSB _u(5) -#define UART_UARTICR_TXIC_LSB _u(5) -#define UART_UARTICR_TXIC_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : UART_UARTICR_RXIC -// Description : Receive interrupt clear. Clears the UARTRXINTR interrupt. -#define UART_UARTICR_RXIC_RESET "-" -#define UART_UARTICR_RXIC_BITS _u(0x00000010) -#define UART_UARTICR_RXIC_MSB _u(4) -#define UART_UARTICR_RXIC_LSB _u(4) -#define UART_UARTICR_RXIC_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : UART_UARTICR_DSRMIC -// Description : nUARTDSR modem interrupt clear. Clears the UARTDSRINTR -// interrupt. -#define UART_UARTICR_DSRMIC_RESET "-" -#define UART_UARTICR_DSRMIC_BITS _u(0x00000008) -#define UART_UARTICR_DSRMIC_MSB _u(3) -#define UART_UARTICR_DSRMIC_LSB _u(3) -#define UART_UARTICR_DSRMIC_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : UART_UARTICR_DCDMIC -// Description : nUARTDCD modem interrupt clear. Clears the UARTDCDINTR -// interrupt. -#define UART_UARTICR_DCDMIC_RESET "-" -#define UART_UARTICR_DCDMIC_BITS _u(0x00000004) -#define UART_UARTICR_DCDMIC_MSB _u(2) -#define UART_UARTICR_DCDMIC_LSB _u(2) -#define UART_UARTICR_DCDMIC_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : UART_UARTICR_CTSMIC -// Description : nUARTCTS modem interrupt clear. Clears the UARTCTSINTR -// interrupt. -#define UART_UARTICR_CTSMIC_RESET "-" -#define UART_UARTICR_CTSMIC_BITS _u(0x00000002) -#define UART_UARTICR_CTSMIC_MSB _u(1) -#define UART_UARTICR_CTSMIC_LSB _u(1) -#define UART_UARTICR_CTSMIC_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : UART_UARTICR_RIMIC -// Description : nUARTRI modem interrupt clear. Clears the UARTRIINTR interrupt. -#define UART_UARTICR_RIMIC_RESET "-" -#define UART_UARTICR_RIMIC_BITS _u(0x00000001) -#define UART_UARTICR_RIMIC_MSB _u(0) -#define UART_UARTICR_RIMIC_LSB _u(0) -#define UART_UARTICR_RIMIC_ACCESS "WC" -// ============================================================================= -// Register : UART_UARTDMACR -// Description : DMA Control Register, UARTDMACR -#define UART_UARTDMACR_OFFSET _u(0x00000048) -#define UART_UARTDMACR_BITS _u(0x00000007) -#define UART_UARTDMACR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : UART_UARTDMACR_DMAONERR -// Description : DMA on error. If this bit is set to 1, the DMA receive request -// outputs, UARTRXDMASREQ or UARTRXDMABREQ, are disabled when the -// UART error interrupt is asserted. -#define UART_UARTDMACR_DMAONERR_RESET _u(0x0) -#define UART_UARTDMACR_DMAONERR_BITS _u(0x00000004) -#define UART_UARTDMACR_DMAONERR_MSB _u(2) -#define UART_UARTDMACR_DMAONERR_LSB _u(2) -#define UART_UARTDMACR_DMAONERR_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : UART_UARTDMACR_TXDMAE -// Description : Transmit DMA enable. If this bit is set to 1, DMA for the -// transmit FIFO is enabled. -#define UART_UARTDMACR_TXDMAE_RESET _u(0x0) -#define UART_UARTDMACR_TXDMAE_BITS _u(0x00000002) -#define UART_UARTDMACR_TXDMAE_MSB _u(1) -#define UART_UARTDMACR_TXDMAE_LSB _u(1) -#define UART_UARTDMACR_TXDMAE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : UART_UARTDMACR_RXDMAE -// Description : Receive DMA enable. If this bit is set to 1, DMA for the -// receive FIFO is enabled. -#define UART_UARTDMACR_RXDMAE_RESET _u(0x0) -#define UART_UARTDMACR_RXDMAE_BITS _u(0x00000001) -#define UART_UARTDMACR_RXDMAE_MSB _u(0) -#define UART_UARTDMACR_RXDMAE_LSB _u(0) -#define UART_UARTDMACR_RXDMAE_ACCESS "RW" -// ============================================================================= -// Register : UART_UARTPERIPHID0 -// Description : UARTPeriphID0 Register -#define UART_UARTPERIPHID0_OFFSET _u(0x00000fe0) -#define UART_UARTPERIPHID0_BITS _u(0x000000ff) -#define UART_UARTPERIPHID0_RESET _u(0x00000011) -// ----------------------------------------------------------------------------- -// Field : UART_UARTPERIPHID0_PARTNUMBER0 -// Description : These bits read back as 0x11 -#define UART_UARTPERIPHID0_PARTNUMBER0_RESET _u(0x11) -#define UART_UARTPERIPHID0_PARTNUMBER0_BITS _u(0x000000ff) -#define UART_UARTPERIPHID0_PARTNUMBER0_MSB _u(7) -#define UART_UARTPERIPHID0_PARTNUMBER0_LSB _u(0) -#define UART_UARTPERIPHID0_PARTNUMBER0_ACCESS "RO" -// ============================================================================= -// Register : UART_UARTPERIPHID1 -// Description : UARTPeriphID1 Register -#define UART_UARTPERIPHID1_OFFSET _u(0x00000fe4) -#define UART_UARTPERIPHID1_BITS _u(0x000000ff) -#define UART_UARTPERIPHID1_RESET _u(0x00000010) -// ----------------------------------------------------------------------------- -// Field : UART_UARTPERIPHID1_DESIGNER0 -// Description : These bits read back as 0x1 -#define UART_UARTPERIPHID1_DESIGNER0_RESET _u(0x1) -#define UART_UARTPERIPHID1_DESIGNER0_BITS _u(0x000000f0) -#define UART_UARTPERIPHID1_DESIGNER0_MSB _u(7) -#define UART_UARTPERIPHID1_DESIGNER0_LSB _u(4) -#define UART_UARTPERIPHID1_DESIGNER0_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : UART_UARTPERIPHID1_PARTNUMBER1 -// Description : These bits read back as 0x0 -#define UART_UARTPERIPHID1_PARTNUMBER1_RESET _u(0x0) -#define UART_UARTPERIPHID1_PARTNUMBER1_BITS _u(0x0000000f) -#define UART_UARTPERIPHID1_PARTNUMBER1_MSB _u(3) -#define UART_UARTPERIPHID1_PARTNUMBER1_LSB _u(0) -#define UART_UARTPERIPHID1_PARTNUMBER1_ACCESS "RO" -// ============================================================================= -// Register : UART_UARTPERIPHID2 -// Description : UARTPeriphID2 Register -#define UART_UARTPERIPHID2_OFFSET _u(0x00000fe8) -#define UART_UARTPERIPHID2_BITS _u(0x000000ff) -#define UART_UARTPERIPHID2_RESET _u(0x00000034) -// ----------------------------------------------------------------------------- -// Field : UART_UARTPERIPHID2_REVISION -// Description : This field depends on the revision of the UART: r1p0 0x0 r1p1 -// 0x1 r1p3 0x2 r1p4 0x2 r1p5 0x3 -#define UART_UARTPERIPHID2_REVISION_RESET _u(0x3) -#define UART_UARTPERIPHID2_REVISION_BITS _u(0x000000f0) -#define UART_UARTPERIPHID2_REVISION_MSB _u(7) -#define UART_UARTPERIPHID2_REVISION_LSB _u(4) -#define UART_UARTPERIPHID2_REVISION_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : UART_UARTPERIPHID2_DESIGNER1 -// Description : These bits read back as 0x4 -#define UART_UARTPERIPHID2_DESIGNER1_RESET _u(0x4) -#define UART_UARTPERIPHID2_DESIGNER1_BITS _u(0x0000000f) -#define UART_UARTPERIPHID2_DESIGNER1_MSB _u(3) -#define UART_UARTPERIPHID2_DESIGNER1_LSB _u(0) -#define UART_UARTPERIPHID2_DESIGNER1_ACCESS "RO" -// ============================================================================= -// Register : UART_UARTPERIPHID3 -// Description : UARTPeriphID3 Register -#define UART_UARTPERIPHID3_OFFSET _u(0x00000fec) -#define UART_UARTPERIPHID3_BITS _u(0x000000ff) -#define UART_UARTPERIPHID3_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : UART_UARTPERIPHID3_CONFIGURATION -// Description : These bits read back as 0x00 -#define UART_UARTPERIPHID3_CONFIGURATION_RESET _u(0x00) -#define UART_UARTPERIPHID3_CONFIGURATION_BITS _u(0x000000ff) -#define UART_UARTPERIPHID3_CONFIGURATION_MSB _u(7) -#define UART_UARTPERIPHID3_CONFIGURATION_LSB _u(0) -#define UART_UARTPERIPHID3_CONFIGURATION_ACCESS "RO" -// ============================================================================= -// Register : UART_UARTPCELLID0 -// Description : UARTPCellID0 Register -#define UART_UARTPCELLID0_OFFSET _u(0x00000ff0) -#define UART_UARTPCELLID0_BITS _u(0x000000ff) -#define UART_UARTPCELLID0_RESET _u(0x0000000d) -// ----------------------------------------------------------------------------- -// Field : UART_UARTPCELLID0_UARTPCELLID0 -// Description : These bits read back as 0x0D -#define UART_UARTPCELLID0_UARTPCELLID0_RESET _u(0x0d) -#define UART_UARTPCELLID0_UARTPCELLID0_BITS _u(0x000000ff) -#define UART_UARTPCELLID0_UARTPCELLID0_MSB _u(7) -#define UART_UARTPCELLID0_UARTPCELLID0_LSB _u(0) -#define UART_UARTPCELLID0_UARTPCELLID0_ACCESS "RO" -// ============================================================================= -// Register : UART_UARTPCELLID1 -// Description : UARTPCellID1 Register -#define UART_UARTPCELLID1_OFFSET _u(0x00000ff4) -#define UART_UARTPCELLID1_BITS _u(0x000000ff) -#define UART_UARTPCELLID1_RESET _u(0x000000f0) -// ----------------------------------------------------------------------------- -// Field : UART_UARTPCELLID1_UARTPCELLID1 -// Description : These bits read back as 0xF0 -#define UART_UARTPCELLID1_UARTPCELLID1_RESET _u(0xf0) -#define UART_UARTPCELLID1_UARTPCELLID1_BITS _u(0x000000ff) -#define UART_UARTPCELLID1_UARTPCELLID1_MSB _u(7) -#define UART_UARTPCELLID1_UARTPCELLID1_LSB _u(0) -#define UART_UARTPCELLID1_UARTPCELLID1_ACCESS "RO" -// ============================================================================= -// Register : UART_UARTPCELLID2 -// Description : UARTPCellID2 Register -#define UART_UARTPCELLID2_OFFSET _u(0x00000ff8) -#define UART_UARTPCELLID2_BITS _u(0x000000ff) -#define UART_UARTPCELLID2_RESET _u(0x00000005) -// ----------------------------------------------------------------------------- -// Field : UART_UARTPCELLID2_UARTPCELLID2 -// Description : These bits read back as 0x05 -#define UART_UARTPCELLID2_UARTPCELLID2_RESET _u(0x05) -#define UART_UARTPCELLID2_UARTPCELLID2_BITS _u(0x000000ff) -#define UART_UARTPCELLID2_UARTPCELLID2_MSB _u(7) -#define UART_UARTPCELLID2_UARTPCELLID2_LSB _u(0) -#define UART_UARTPCELLID2_UARTPCELLID2_ACCESS "RO" -// ============================================================================= -// Register : UART_UARTPCELLID3 -// Description : UARTPCellID3 Register -#define UART_UARTPCELLID3_OFFSET _u(0x00000ffc) -#define UART_UARTPCELLID3_BITS _u(0x000000ff) -#define UART_UARTPCELLID3_RESET _u(0x000000b1) -// ----------------------------------------------------------------------------- -// Field : UART_UARTPCELLID3_UARTPCELLID3 -// Description : These bits read back as 0xB1 -#define UART_UARTPCELLID3_UARTPCELLID3_RESET _u(0xb1) -#define UART_UARTPCELLID3_UARTPCELLID3_BITS _u(0x000000ff) -#define UART_UARTPCELLID3_UARTPCELLID3_MSB _u(7) -#define UART_UARTPCELLID3_UARTPCELLID3_LSB _u(0) -#define UART_UARTPCELLID3_UARTPCELLID3_ACCESS "RO" -// ============================================================================= -#endif // _HARDWARE_REGS_UART_H - diff --git a/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/usb.h b/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/usb.h deleted file mode 100644 index fbf1b7b363..0000000000 --- a/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/usb.h +++ /dev/null @@ -1,4209 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -// ============================================================================= -// Register block : USB -// Version : 1 -// Bus type : ahbl -// Description : USB FS/LS controller device registers -// ============================================================================= -#ifndef _HARDWARE_REGS_USB_H -#define _HARDWARE_REGS_USB_H -// ============================================================================= -// Register : USB_ADDR_ENDP -// Description : Device address and endpoint control -#define USB_ADDR_ENDP_OFFSET _u(0x00000000) -#define USB_ADDR_ENDP_BITS _u(0x000f007f) -#define USB_ADDR_ENDP_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_ADDR_ENDP_ENDPOINT -// Description : Device endpoint to send data to. Only valid for HOST mode. -#define USB_ADDR_ENDP_ENDPOINT_RESET _u(0x0) -#define USB_ADDR_ENDP_ENDPOINT_BITS _u(0x000f0000) -#define USB_ADDR_ENDP_ENDPOINT_MSB _u(19) -#define USB_ADDR_ENDP_ENDPOINT_LSB _u(16) -#define USB_ADDR_ENDP_ENDPOINT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_ADDR_ENDP_ADDRESS -// Description : In device mode, the address that the device should respond to. -// Set in response to a SET_ADDR setup packet from the host. In -// host mode set to the address of the device to communicate with. -#define USB_ADDR_ENDP_ADDRESS_RESET _u(0x00) -#define USB_ADDR_ENDP_ADDRESS_BITS _u(0x0000007f) -#define USB_ADDR_ENDP_ADDRESS_MSB _u(6) -#define USB_ADDR_ENDP_ADDRESS_LSB _u(0) -#define USB_ADDR_ENDP_ADDRESS_ACCESS "RW" -// ============================================================================= -// Register : USB_ADDR_ENDP1 -// Description : Interrupt endpoint 1. Only valid for HOST mode. -#define USB_ADDR_ENDP1_OFFSET _u(0x00000004) -#define USB_ADDR_ENDP1_BITS _u(0x060f007f) -#define USB_ADDR_ENDP1_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_ADDR_ENDP1_INTEP_PREAMBLE -// Description : Interrupt EP requires preamble (is a low speed device on a full -// speed hub) -#define USB_ADDR_ENDP1_INTEP_PREAMBLE_RESET _u(0x0) -#define USB_ADDR_ENDP1_INTEP_PREAMBLE_BITS _u(0x04000000) -#define USB_ADDR_ENDP1_INTEP_PREAMBLE_MSB _u(26) -#define USB_ADDR_ENDP1_INTEP_PREAMBLE_LSB _u(26) -#define USB_ADDR_ENDP1_INTEP_PREAMBLE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_ADDR_ENDP1_INTEP_DIR -// Description : Direction of the interrupt endpoint. In=0, Out=1 -#define USB_ADDR_ENDP1_INTEP_DIR_RESET _u(0x0) -#define USB_ADDR_ENDP1_INTEP_DIR_BITS _u(0x02000000) -#define USB_ADDR_ENDP1_INTEP_DIR_MSB _u(25) -#define USB_ADDR_ENDP1_INTEP_DIR_LSB _u(25) -#define USB_ADDR_ENDP1_INTEP_DIR_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_ADDR_ENDP1_ENDPOINT -// Description : Endpoint number of the interrupt endpoint -#define USB_ADDR_ENDP1_ENDPOINT_RESET _u(0x0) -#define USB_ADDR_ENDP1_ENDPOINT_BITS _u(0x000f0000) -#define USB_ADDR_ENDP1_ENDPOINT_MSB _u(19) -#define USB_ADDR_ENDP1_ENDPOINT_LSB _u(16) -#define USB_ADDR_ENDP1_ENDPOINT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_ADDR_ENDP1_ADDRESS -// Description : Device address -#define USB_ADDR_ENDP1_ADDRESS_RESET _u(0x00) -#define USB_ADDR_ENDP1_ADDRESS_BITS _u(0x0000007f) -#define USB_ADDR_ENDP1_ADDRESS_MSB _u(6) -#define USB_ADDR_ENDP1_ADDRESS_LSB _u(0) -#define USB_ADDR_ENDP1_ADDRESS_ACCESS "RW" -// ============================================================================= -// Register : USB_ADDR_ENDP2 -// Description : Interrupt endpoint 2. Only valid for HOST mode. -#define USB_ADDR_ENDP2_OFFSET _u(0x00000008) -#define USB_ADDR_ENDP2_BITS _u(0x060f007f) -#define USB_ADDR_ENDP2_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_ADDR_ENDP2_INTEP_PREAMBLE -// Description : Interrupt EP requires preamble (is a low speed device on a full -// speed hub) -#define USB_ADDR_ENDP2_INTEP_PREAMBLE_RESET _u(0x0) -#define USB_ADDR_ENDP2_INTEP_PREAMBLE_BITS _u(0x04000000) -#define USB_ADDR_ENDP2_INTEP_PREAMBLE_MSB _u(26) -#define USB_ADDR_ENDP2_INTEP_PREAMBLE_LSB _u(26) -#define USB_ADDR_ENDP2_INTEP_PREAMBLE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_ADDR_ENDP2_INTEP_DIR -// Description : Direction of the interrupt endpoint. In=0, Out=1 -#define USB_ADDR_ENDP2_INTEP_DIR_RESET _u(0x0) -#define USB_ADDR_ENDP2_INTEP_DIR_BITS _u(0x02000000) -#define USB_ADDR_ENDP2_INTEP_DIR_MSB _u(25) -#define USB_ADDR_ENDP2_INTEP_DIR_LSB _u(25) -#define USB_ADDR_ENDP2_INTEP_DIR_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_ADDR_ENDP2_ENDPOINT -// Description : Endpoint number of the interrupt endpoint -#define USB_ADDR_ENDP2_ENDPOINT_RESET _u(0x0) -#define USB_ADDR_ENDP2_ENDPOINT_BITS _u(0x000f0000) -#define USB_ADDR_ENDP2_ENDPOINT_MSB _u(19) -#define USB_ADDR_ENDP2_ENDPOINT_LSB _u(16) -#define USB_ADDR_ENDP2_ENDPOINT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_ADDR_ENDP2_ADDRESS -// Description : Device address -#define USB_ADDR_ENDP2_ADDRESS_RESET _u(0x00) -#define USB_ADDR_ENDP2_ADDRESS_BITS _u(0x0000007f) -#define USB_ADDR_ENDP2_ADDRESS_MSB _u(6) -#define USB_ADDR_ENDP2_ADDRESS_LSB _u(0) -#define USB_ADDR_ENDP2_ADDRESS_ACCESS "RW" -// ============================================================================= -// Register : USB_ADDR_ENDP3 -// Description : Interrupt endpoint 3. Only valid for HOST mode. -#define USB_ADDR_ENDP3_OFFSET _u(0x0000000c) -#define USB_ADDR_ENDP3_BITS _u(0x060f007f) -#define USB_ADDR_ENDP3_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_ADDR_ENDP3_INTEP_PREAMBLE -// Description : Interrupt EP requires preamble (is a low speed device on a full -// speed hub) -#define USB_ADDR_ENDP3_INTEP_PREAMBLE_RESET _u(0x0) -#define USB_ADDR_ENDP3_INTEP_PREAMBLE_BITS _u(0x04000000) -#define USB_ADDR_ENDP3_INTEP_PREAMBLE_MSB _u(26) -#define USB_ADDR_ENDP3_INTEP_PREAMBLE_LSB _u(26) -#define USB_ADDR_ENDP3_INTEP_PREAMBLE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_ADDR_ENDP3_INTEP_DIR -// Description : Direction of the interrupt endpoint. In=0, Out=1 -#define USB_ADDR_ENDP3_INTEP_DIR_RESET _u(0x0) -#define USB_ADDR_ENDP3_INTEP_DIR_BITS _u(0x02000000) -#define USB_ADDR_ENDP3_INTEP_DIR_MSB _u(25) -#define USB_ADDR_ENDP3_INTEP_DIR_LSB _u(25) -#define USB_ADDR_ENDP3_INTEP_DIR_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_ADDR_ENDP3_ENDPOINT -// Description : Endpoint number of the interrupt endpoint -#define USB_ADDR_ENDP3_ENDPOINT_RESET _u(0x0) -#define USB_ADDR_ENDP3_ENDPOINT_BITS _u(0x000f0000) -#define USB_ADDR_ENDP3_ENDPOINT_MSB _u(19) -#define USB_ADDR_ENDP3_ENDPOINT_LSB _u(16) -#define USB_ADDR_ENDP3_ENDPOINT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_ADDR_ENDP3_ADDRESS -// Description : Device address -#define USB_ADDR_ENDP3_ADDRESS_RESET _u(0x00) -#define USB_ADDR_ENDP3_ADDRESS_BITS _u(0x0000007f) -#define USB_ADDR_ENDP3_ADDRESS_MSB _u(6) -#define USB_ADDR_ENDP3_ADDRESS_LSB _u(0) -#define USB_ADDR_ENDP3_ADDRESS_ACCESS "RW" -// ============================================================================= -// Register : USB_ADDR_ENDP4 -// Description : Interrupt endpoint 4. Only valid for HOST mode. -#define USB_ADDR_ENDP4_OFFSET _u(0x00000010) -#define USB_ADDR_ENDP4_BITS _u(0x060f007f) -#define USB_ADDR_ENDP4_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_ADDR_ENDP4_INTEP_PREAMBLE -// Description : Interrupt EP requires preamble (is a low speed device on a full -// speed hub) -#define USB_ADDR_ENDP4_INTEP_PREAMBLE_RESET _u(0x0) -#define USB_ADDR_ENDP4_INTEP_PREAMBLE_BITS _u(0x04000000) -#define USB_ADDR_ENDP4_INTEP_PREAMBLE_MSB _u(26) -#define USB_ADDR_ENDP4_INTEP_PREAMBLE_LSB _u(26) -#define USB_ADDR_ENDP4_INTEP_PREAMBLE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_ADDR_ENDP4_INTEP_DIR -// Description : Direction of the interrupt endpoint. In=0, Out=1 -#define USB_ADDR_ENDP4_INTEP_DIR_RESET _u(0x0) -#define USB_ADDR_ENDP4_INTEP_DIR_BITS _u(0x02000000) -#define USB_ADDR_ENDP4_INTEP_DIR_MSB _u(25) -#define USB_ADDR_ENDP4_INTEP_DIR_LSB _u(25) -#define USB_ADDR_ENDP4_INTEP_DIR_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_ADDR_ENDP4_ENDPOINT -// Description : Endpoint number of the interrupt endpoint -#define USB_ADDR_ENDP4_ENDPOINT_RESET _u(0x0) -#define USB_ADDR_ENDP4_ENDPOINT_BITS _u(0x000f0000) -#define USB_ADDR_ENDP4_ENDPOINT_MSB _u(19) -#define USB_ADDR_ENDP4_ENDPOINT_LSB _u(16) -#define USB_ADDR_ENDP4_ENDPOINT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_ADDR_ENDP4_ADDRESS -// Description : Device address -#define USB_ADDR_ENDP4_ADDRESS_RESET _u(0x00) -#define USB_ADDR_ENDP4_ADDRESS_BITS _u(0x0000007f) -#define USB_ADDR_ENDP4_ADDRESS_MSB _u(6) -#define USB_ADDR_ENDP4_ADDRESS_LSB _u(0) -#define USB_ADDR_ENDP4_ADDRESS_ACCESS "RW" -// ============================================================================= -// Register : USB_ADDR_ENDP5 -// Description : Interrupt endpoint 5. Only valid for HOST mode. -#define USB_ADDR_ENDP5_OFFSET _u(0x00000014) -#define USB_ADDR_ENDP5_BITS _u(0x060f007f) -#define USB_ADDR_ENDP5_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_ADDR_ENDP5_INTEP_PREAMBLE -// Description : Interrupt EP requires preamble (is a low speed device on a full -// speed hub) -#define USB_ADDR_ENDP5_INTEP_PREAMBLE_RESET _u(0x0) -#define USB_ADDR_ENDP5_INTEP_PREAMBLE_BITS _u(0x04000000) -#define USB_ADDR_ENDP5_INTEP_PREAMBLE_MSB _u(26) -#define USB_ADDR_ENDP5_INTEP_PREAMBLE_LSB _u(26) -#define USB_ADDR_ENDP5_INTEP_PREAMBLE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_ADDR_ENDP5_INTEP_DIR -// Description : Direction of the interrupt endpoint. In=0, Out=1 -#define USB_ADDR_ENDP5_INTEP_DIR_RESET _u(0x0) -#define USB_ADDR_ENDP5_INTEP_DIR_BITS _u(0x02000000) -#define USB_ADDR_ENDP5_INTEP_DIR_MSB _u(25) -#define USB_ADDR_ENDP5_INTEP_DIR_LSB _u(25) -#define USB_ADDR_ENDP5_INTEP_DIR_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_ADDR_ENDP5_ENDPOINT -// Description : Endpoint number of the interrupt endpoint -#define USB_ADDR_ENDP5_ENDPOINT_RESET _u(0x0) -#define USB_ADDR_ENDP5_ENDPOINT_BITS _u(0x000f0000) -#define USB_ADDR_ENDP5_ENDPOINT_MSB _u(19) -#define USB_ADDR_ENDP5_ENDPOINT_LSB _u(16) -#define USB_ADDR_ENDP5_ENDPOINT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_ADDR_ENDP5_ADDRESS -// Description : Device address -#define USB_ADDR_ENDP5_ADDRESS_RESET _u(0x00) -#define USB_ADDR_ENDP5_ADDRESS_BITS _u(0x0000007f) -#define USB_ADDR_ENDP5_ADDRESS_MSB _u(6) -#define USB_ADDR_ENDP5_ADDRESS_LSB _u(0) -#define USB_ADDR_ENDP5_ADDRESS_ACCESS "RW" -// ============================================================================= -// Register : USB_ADDR_ENDP6 -// Description : Interrupt endpoint 6. Only valid for HOST mode. -#define USB_ADDR_ENDP6_OFFSET _u(0x00000018) -#define USB_ADDR_ENDP6_BITS _u(0x060f007f) -#define USB_ADDR_ENDP6_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_ADDR_ENDP6_INTEP_PREAMBLE -// Description : Interrupt EP requires preamble (is a low speed device on a full -// speed hub) -#define USB_ADDR_ENDP6_INTEP_PREAMBLE_RESET _u(0x0) -#define USB_ADDR_ENDP6_INTEP_PREAMBLE_BITS _u(0x04000000) -#define USB_ADDR_ENDP6_INTEP_PREAMBLE_MSB _u(26) -#define USB_ADDR_ENDP6_INTEP_PREAMBLE_LSB _u(26) -#define USB_ADDR_ENDP6_INTEP_PREAMBLE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_ADDR_ENDP6_INTEP_DIR -// Description : Direction of the interrupt endpoint. In=0, Out=1 -#define USB_ADDR_ENDP6_INTEP_DIR_RESET _u(0x0) -#define USB_ADDR_ENDP6_INTEP_DIR_BITS _u(0x02000000) -#define USB_ADDR_ENDP6_INTEP_DIR_MSB _u(25) -#define USB_ADDR_ENDP6_INTEP_DIR_LSB _u(25) -#define USB_ADDR_ENDP6_INTEP_DIR_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_ADDR_ENDP6_ENDPOINT -// Description : Endpoint number of the interrupt endpoint -#define USB_ADDR_ENDP6_ENDPOINT_RESET _u(0x0) -#define USB_ADDR_ENDP6_ENDPOINT_BITS _u(0x000f0000) -#define USB_ADDR_ENDP6_ENDPOINT_MSB _u(19) -#define USB_ADDR_ENDP6_ENDPOINT_LSB _u(16) -#define USB_ADDR_ENDP6_ENDPOINT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_ADDR_ENDP6_ADDRESS -// Description : Device address -#define USB_ADDR_ENDP6_ADDRESS_RESET _u(0x00) -#define USB_ADDR_ENDP6_ADDRESS_BITS _u(0x0000007f) -#define USB_ADDR_ENDP6_ADDRESS_MSB _u(6) -#define USB_ADDR_ENDP6_ADDRESS_LSB _u(0) -#define USB_ADDR_ENDP6_ADDRESS_ACCESS "RW" -// ============================================================================= -// Register : USB_ADDR_ENDP7 -// Description : Interrupt endpoint 7. Only valid for HOST mode. -#define USB_ADDR_ENDP7_OFFSET _u(0x0000001c) -#define USB_ADDR_ENDP7_BITS _u(0x060f007f) -#define USB_ADDR_ENDP7_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_ADDR_ENDP7_INTEP_PREAMBLE -// Description : Interrupt EP requires preamble (is a low speed device on a full -// speed hub) -#define USB_ADDR_ENDP7_INTEP_PREAMBLE_RESET _u(0x0) -#define USB_ADDR_ENDP7_INTEP_PREAMBLE_BITS _u(0x04000000) -#define USB_ADDR_ENDP7_INTEP_PREAMBLE_MSB _u(26) -#define USB_ADDR_ENDP7_INTEP_PREAMBLE_LSB _u(26) -#define USB_ADDR_ENDP7_INTEP_PREAMBLE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_ADDR_ENDP7_INTEP_DIR -// Description : Direction of the interrupt endpoint. In=0, Out=1 -#define USB_ADDR_ENDP7_INTEP_DIR_RESET _u(0x0) -#define USB_ADDR_ENDP7_INTEP_DIR_BITS _u(0x02000000) -#define USB_ADDR_ENDP7_INTEP_DIR_MSB _u(25) -#define USB_ADDR_ENDP7_INTEP_DIR_LSB _u(25) -#define USB_ADDR_ENDP7_INTEP_DIR_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_ADDR_ENDP7_ENDPOINT -// Description : Endpoint number of the interrupt endpoint -#define USB_ADDR_ENDP7_ENDPOINT_RESET _u(0x0) -#define USB_ADDR_ENDP7_ENDPOINT_BITS _u(0x000f0000) -#define USB_ADDR_ENDP7_ENDPOINT_MSB _u(19) -#define USB_ADDR_ENDP7_ENDPOINT_LSB _u(16) -#define USB_ADDR_ENDP7_ENDPOINT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_ADDR_ENDP7_ADDRESS -// Description : Device address -#define USB_ADDR_ENDP7_ADDRESS_RESET _u(0x00) -#define USB_ADDR_ENDP7_ADDRESS_BITS _u(0x0000007f) -#define USB_ADDR_ENDP7_ADDRESS_MSB _u(6) -#define USB_ADDR_ENDP7_ADDRESS_LSB _u(0) -#define USB_ADDR_ENDP7_ADDRESS_ACCESS "RW" -// ============================================================================= -// Register : USB_ADDR_ENDP8 -// Description : Interrupt endpoint 8. Only valid for HOST mode. -#define USB_ADDR_ENDP8_OFFSET _u(0x00000020) -#define USB_ADDR_ENDP8_BITS _u(0x060f007f) -#define USB_ADDR_ENDP8_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_ADDR_ENDP8_INTEP_PREAMBLE -// Description : Interrupt EP requires preamble (is a low speed device on a full -// speed hub) -#define USB_ADDR_ENDP8_INTEP_PREAMBLE_RESET _u(0x0) -#define USB_ADDR_ENDP8_INTEP_PREAMBLE_BITS _u(0x04000000) -#define USB_ADDR_ENDP8_INTEP_PREAMBLE_MSB _u(26) -#define USB_ADDR_ENDP8_INTEP_PREAMBLE_LSB _u(26) -#define USB_ADDR_ENDP8_INTEP_PREAMBLE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_ADDR_ENDP8_INTEP_DIR -// Description : Direction of the interrupt endpoint. In=0, Out=1 -#define USB_ADDR_ENDP8_INTEP_DIR_RESET _u(0x0) -#define USB_ADDR_ENDP8_INTEP_DIR_BITS _u(0x02000000) -#define USB_ADDR_ENDP8_INTEP_DIR_MSB _u(25) -#define USB_ADDR_ENDP8_INTEP_DIR_LSB _u(25) -#define USB_ADDR_ENDP8_INTEP_DIR_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_ADDR_ENDP8_ENDPOINT -// Description : Endpoint number of the interrupt endpoint -#define USB_ADDR_ENDP8_ENDPOINT_RESET _u(0x0) -#define USB_ADDR_ENDP8_ENDPOINT_BITS _u(0x000f0000) -#define USB_ADDR_ENDP8_ENDPOINT_MSB _u(19) -#define USB_ADDR_ENDP8_ENDPOINT_LSB _u(16) -#define USB_ADDR_ENDP8_ENDPOINT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_ADDR_ENDP8_ADDRESS -// Description : Device address -#define USB_ADDR_ENDP8_ADDRESS_RESET _u(0x00) -#define USB_ADDR_ENDP8_ADDRESS_BITS _u(0x0000007f) -#define USB_ADDR_ENDP8_ADDRESS_MSB _u(6) -#define USB_ADDR_ENDP8_ADDRESS_LSB _u(0) -#define USB_ADDR_ENDP8_ADDRESS_ACCESS "RW" -// ============================================================================= -// Register : USB_ADDR_ENDP9 -// Description : Interrupt endpoint 9. Only valid for HOST mode. -#define USB_ADDR_ENDP9_OFFSET _u(0x00000024) -#define USB_ADDR_ENDP9_BITS _u(0x060f007f) -#define USB_ADDR_ENDP9_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_ADDR_ENDP9_INTEP_PREAMBLE -// Description : Interrupt EP requires preamble (is a low speed device on a full -// speed hub) -#define USB_ADDR_ENDP9_INTEP_PREAMBLE_RESET _u(0x0) -#define USB_ADDR_ENDP9_INTEP_PREAMBLE_BITS _u(0x04000000) -#define USB_ADDR_ENDP9_INTEP_PREAMBLE_MSB _u(26) -#define USB_ADDR_ENDP9_INTEP_PREAMBLE_LSB _u(26) -#define USB_ADDR_ENDP9_INTEP_PREAMBLE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_ADDR_ENDP9_INTEP_DIR -// Description : Direction of the interrupt endpoint. In=0, Out=1 -#define USB_ADDR_ENDP9_INTEP_DIR_RESET _u(0x0) -#define USB_ADDR_ENDP9_INTEP_DIR_BITS _u(0x02000000) -#define USB_ADDR_ENDP9_INTEP_DIR_MSB _u(25) -#define USB_ADDR_ENDP9_INTEP_DIR_LSB _u(25) -#define USB_ADDR_ENDP9_INTEP_DIR_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_ADDR_ENDP9_ENDPOINT -// Description : Endpoint number of the interrupt endpoint -#define USB_ADDR_ENDP9_ENDPOINT_RESET _u(0x0) -#define USB_ADDR_ENDP9_ENDPOINT_BITS _u(0x000f0000) -#define USB_ADDR_ENDP9_ENDPOINT_MSB _u(19) -#define USB_ADDR_ENDP9_ENDPOINT_LSB _u(16) -#define USB_ADDR_ENDP9_ENDPOINT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_ADDR_ENDP9_ADDRESS -// Description : Device address -#define USB_ADDR_ENDP9_ADDRESS_RESET _u(0x00) -#define USB_ADDR_ENDP9_ADDRESS_BITS _u(0x0000007f) -#define USB_ADDR_ENDP9_ADDRESS_MSB _u(6) -#define USB_ADDR_ENDP9_ADDRESS_LSB _u(0) -#define USB_ADDR_ENDP9_ADDRESS_ACCESS "RW" -// ============================================================================= -// Register : USB_ADDR_ENDP10 -// Description : Interrupt endpoint 10. Only valid for HOST mode. -#define USB_ADDR_ENDP10_OFFSET _u(0x00000028) -#define USB_ADDR_ENDP10_BITS _u(0x060f007f) -#define USB_ADDR_ENDP10_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_ADDR_ENDP10_INTEP_PREAMBLE -// Description : Interrupt EP requires preamble (is a low speed device on a full -// speed hub) -#define USB_ADDR_ENDP10_INTEP_PREAMBLE_RESET _u(0x0) -#define USB_ADDR_ENDP10_INTEP_PREAMBLE_BITS _u(0x04000000) -#define USB_ADDR_ENDP10_INTEP_PREAMBLE_MSB _u(26) -#define USB_ADDR_ENDP10_INTEP_PREAMBLE_LSB _u(26) -#define USB_ADDR_ENDP10_INTEP_PREAMBLE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_ADDR_ENDP10_INTEP_DIR -// Description : Direction of the interrupt endpoint. In=0, Out=1 -#define USB_ADDR_ENDP10_INTEP_DIR_RESET _u(0x0) -#define USB_ADDR_ENDP10_INTEP_DIR_BITS _u(0x02000000) -#define USB_ADDR_ENDP10_INTEP_DIR_MSB _u(25) -#define USB_ADDR_ENDP10_INTEP_DIR_LSB _u(25) -#define USB_ADDR_ENDP10_INTEP_DIR_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_ADDR_ENDP10_ENDPOINT -// Description : Endpoint number of the interrupt endpoint -#define USB_ADDR_ENDP10_ENDPOINT_RESET _u(0x0) -#define USB_ADDR_ENDP10_ENDPOINT_BITS _u(0x000f0000) -#define USB_ADDR_ENDP10_ENDPOINT_MSB _u(19) -#define USB_ADDR_ENDP10_ENDPOINT_LSB _u(16) -#define USB_ADDR_ENDP10_ENDPOINT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_ADDR_ENDP10_ADDRESS -// Description : Device address -#define USB_ADDR_ENDP10_ADDRESS_RESET _u(0x00) -#define USB_ADDR_ENDP10_ADDRESS_BITS _u(0x0000007f) -#define USB_ADDR_ENDP10_ADDRESS_MSB _u(6) -#define USB_ADDR_ENDP10_ADDRESS_LSB _u(0) -#define USB_ADDR_ENDP10_ADDRESS_ACCESS "RW" -// ============================================================================= -// Register : USB_ADDR_ENDP11 -// Description : Interrupt endpoint 11. Only valid for HOST mode. -#define USB_ADDR_ENDP11_OFFSET _u(0x0000002c) -#define USB_ADDR_ENDP11_BITS _u(0x060f007f) -#define USB_ADDR_ENDP11_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_ADDR_ENDP11_INTEP_PREAMBLE -// Description : Interrupt EP requires preamble (is a low speed device on a full -// speed hub) -#define USB_ADDR_ENDP11_INTEP_PREAMBLE_RESET _u(0x0) -#define USB_ADDR_ENDP11_INTEP_PREAMBLE_BITS _u(0x04000000) -#define USB_ADDR_ENDP11_INTEP_PREAMBLE_MSB _u(26) -#define USB_ADDR_ENDP11_INTEP_PREAMBLE_LSB _u(26) -#define USB_ADDR_ENDP11_INTEP_PREAMBLE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_ADDR_ENDP11_INTEP_DIR -// Description : Direction of the interrupt endpoint. In=0, Out=1 -#define USB_ADDR_ENDP11_INTEP_DIR_RESET _u(0x0) -#define USB_ADDR_ENDP11_INTEP_DIR_BITS _u(0x02000000) -#define USB_ADDR_ENDP11_INTEP_DIR_MSB _u(25) -#define USB_ADDR_ENDP11_INTEP_DIR_LSB _u(25) -#define USB_ADDR_ENDP11_INTEP_DIR_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_ADDR_ENDP11_ENDPOINT -// Description : Endpoint number of the interrupt endpoint -#define USB_ADDR_ENDP11_ENDPOINT_RESET _u(0x0) -#define USB_ADDR_ENDP11_ENDPOINT_BITS _u(0x000f0000) -#define USB_ADDR_ENDP11_ENDPOINT_MSB _u(19) -#define USB_ADDR_ENDP11_ENDPOINT_LSB _u(16) -#define USB_ADDR_ENDP11_ENDPOINT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_ADDR_ENDP11_ADDRESS -// Description : Device address -#define USB_ADDR_ENDP11_ADDRESS_RESET _u(0x00) -#define USB_ADDR_ENDP11_ADDRESS_BITS _u(0x0000007f) -#define USB_ADDR_ENDP11_ADDRESS_MSB _u(6) -#define USB_ADDR_ENDP11_ADDRESS_LSB _u(0) -#define USB_ADDR_ENDP11_ADDRESS_ACCESS "RW" -// ============================================================================= -// Register : USB_ADDR_ENDP12 -// Description : Interrupt endpoint 12. Only valid for HOST mode. -#define USB_ADDR_ENDP12_OFFSET _u(0x00000030) -#define USB_ADDR_ENDP12_BITS _u(0x060f007f) -#define USB_ADDR_ENDP12_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_ADDR_ENDP12_INTEP_PREAMBLE -// Description : Interrupt EP requires preamble (is a low speed device on a full -// speed hub) -#define USB_ADDR_ENDP12_INTEP_PREAMBLE_RESET _u(0x0) -#define USB_ADDR_ENDP12_INTEP_PREAMBLE_BITS _u(0x04000000) -#define USB_ADDR_ENDP12_INTEP_PREAMBLE_MSB _u(26) -#define USB_ADDR_ENDP12_INTEP_PREAMBLE_LSB _u(26) -#define USB_ADDR_ENDP12_INTEP_PREAMBLE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_ADDR_ENDP12_INTEP_DIR -// Description : Direction of the interrupt endpoint. In=0, Out=1 -#define USB_ADDR_ENDP12_INTEP_DIR_RESET _u(0x0) -#define USB_ADDR_ENDP12_INTEP_DIR_BITS _u(0x02000000) -#define USB_ADDR_ENDP12_INTEP_DIR_MSB _u(25) -#define USB_ADDR_ENDP12_INTEP_DIR_LSB _u(25) -#define USB_ADDR_ENDP12_INTEP_DIR_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_ADDR_ENDP12_ENDPOINT -// Description : Endpoint number of the interrupt endpoint -#define USB_ADDR_ENDP12_ENDPOINT_RESET _u(0x0) -#define USB_ADDR_ENDP12_ENDPOINT_BITS _u(0x000f0000) -#define USB_ADDR_ENDP12_ENDPOINT_MSB _u(19) -#define USB_ADDR_ENDP12_ENDPOINT_LSB _u(16) -#define USB_ADDR_ENDP12_ENDPOINT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_ADDR_ENDP12_ADDRESS -// Description : Device address -#define USB_ADDR_ENDP12_ADDRESS_RESET _u(0x00) -#define USB_ADDR_ENDP12_ADDRESS_BITS _u(0x0000007f) -#define USB_ADDR_ENDP12_ADDRESS_MSB _u(6) -#define USB_ADDR_ENDP12_ADDRESS_LSB _u(0) -#define USB_ADDR_ENDP12_ADDRESS_ACCESS "RW" -// ============================================================================= -// Register : USB_ADDR_ENDP13 -// Description : Interrupt endpoint 13. Only valid for HOST mode. -#define USB_ADDR_ENDP13_OFFSET _u(0x00000034) -#define USB_ADDR_ENDP13_BITS _u(0x060f007f) -#define USB_ADDR_ENDP13_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_ADDR_ENDP13_INTEP_PREAMBLE -// Description : Interrupt EP requires preamble (is a low speed device on a full -// speed hub) -#define USB_ADDR_ENDP13_INTEP_PREAMBLE_RESET _u(0x0) -#define USB_ADDR_ENDP13_INTEP_PREAMBLE_BITS _u(0x04000000) -#define USB_ADDR_ENDP13_INTEP_PREAMBLE_MSB _u(26) -#define USB_ADDR_ENDP13_INTEP_PREAMBLE_LSB _u(26) -#define USB_ADDR_ENDP13_INTEP_PREAMBLE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_ADDR_ENDP13_INTEP_DIR -// Description : Direction of the interrupt endpoint. In=0, Out=1 -#define USB_ADDR_ENDP13_INTEP_DIR_RESET _u(0x0) -#define USB_ADDR_ENDP13_INTEP_DIR_BITS _u(0x02000000) -#define USB_ADDR_ENDP13_INTEP_DIR_MSB _u(25) -#define USB_ADDR_ENDP13_INTEP_DIR_LSB _u(25) -#define USB_ADDR_ENDP13_INTEP_DIR_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_ADDR_ENDP13_ENDPOINT -// Description : Endpoint number of the interrupt endpoint -#define USB_ADDR_ENDP13_ENDPOINT_RESET _u(0x0) -#define USB_ADDR_ENDP13_ENDPOINT_BITS _u(0x000f0000) -#define USB_ADDR_ENDP13_ENDPOINT_MSB _u(19) -#define USB_ADDR_ENDP13_ENDPOINT_LSB _u(16) -#define USB_ADDR_ENDP13_ENDPOINT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_ADDR_ENDP13_ADDRESS -// Description : Device address -#define USB_ADDR_ENDP13_ADDRESS_RESET _u(0x00) -#define USB_ADDR_ENDP13_ADDRESS_BITS _u(0x0000007f) -#define USB_ADDR_ENDP13_ADDRESS_MSB _u(6) -#define USB_ADDR_ENDP13_ADDRESS_LSB _u(0) -#define USB_ADDR_ENDP13_ADDRESS_ACCESS "RW" -// ============================================================================= -// Register : USB_ADDR_ENDP14 -// Description : Interrupt endpoint 14. Only valid for HOST mode. -#define USB_ADDR_ENDP14_OFFSET _u(0x00000038) -#define USB_ADDR_ENDP14_BITS _u(0x060f007f) -#define USB_ADDR_ENDP14_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_ADDR_ENDP14_INTEP_PREAMBLE -// Description : Interrupt EP requires preamble (is a low speed device on a full -// speed hub) -#define USB_ADDR_ENDP14_INTEP_PREAMBLE_RESET _u(0x0) -#define USB_ADDR_ENDP14_INTEP_PREAMBLE_BITS _u(0x04000000) -#define USB_ADDR_ENDP14_INTEP_PREAMBLE_MSB _u(26) -#define USB_ADDR_ENDP14_INTEP_PREAMBLE_LSB _u(26) -#define USB_ADDR_ENDP14_INTEP_PREAMBLE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_ADDR_ENDP14_INTEP_DIR -// Description : Direction of the interrupt endpoint. In=0, Out=1 -#define USB_ADDR_ENDP14_INTEP_DIR_RESET _u(0x0) -#define USB_ADDR_ENDP14_INTEP_DIR_BITS _u(0x02000000) -#define USB_ADDR_ENDP14_INTEP_DIR_MSB _u(25) -#define USB_ADDR_ENDP14_INTEP_DIR_LSB _u(25) -#define USB_ADDR_ENDP14_INTEP_DIR_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_ADDR_ENDP14_ENDPOINT -// Description : Endpoint number of the interrupt endpoint -#define USB_ADDR_ENDP14_ENDPOINT_RESET _u(0x0) -#define USB_ADDR_ENDP14_ENDPOINT_BITS _u(0x000f0000) -#define USB_ADDR_ENDP14_ENDPOINT_MSB _u(19) -#define USB_ADDR_ENDP14_ENDPOINT_LSB _u(16) -#define USB_ADDR_ENDP14_ENDPOINT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_ADDR_ENDP14_ADDRESS -// Description : Device address -#define USB_ADDR_ENDP14_ADDRESS_RESET _u(0x00) -#define USB_ADDR_ENDP14_ADDRESS_BITS _u(0x0000007f) -#define USB_ADDR_ENDP14_ADDRESS_MSB _u(6) -#define USB_ADDR_ENDP14_ADDRESS_LSB _u(0) -#define USB_ADDR_ENDP14_ADDRESS_ACCESS "RW" -// ============================================================================= -// Register : USB_ADDR_ENDP15 -// Description : Interrupt endpoint 15. Only valid for HOST mode. -#define USB_ADDR_ENDP15_OFFSET _u(0x0000003c) -#define USB_ADDR_ENDP15_BITS _u(0x060f007f) -#define USB_ADDR_ENDP15_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_ADDR_ENDP15_INTEP_PREAMBLE -// Description : Interrupt EP requires preamble (is a low speed device on a full -// speed hub) -#define USB_ADDR_ENDP15_INTEP_PREAMBLE_RESET _u(0x0) -#define USB_ADDR_ENDP15_INTEP_PREAMBLE_BITS _u(0x04000000) -#define USB_ADDR_ENDP15_INTEP_PREAMBLE_MSB _u(26) -#define USB_ADDR_ENDP15_INTEP_PREAMBLE_LSB _u(26) -#define USB_ADDR_ENDP15_INTEP_PREAMBLE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_ADDR_ENDP15_INTEP_DIR -// Description : Direction of the interrupt endpoint. In=0, Out=1 -#define USB_ADDR_ENDP15_INTEP_DIR_RESET _u(0x0) -#define USB_ADDR_ENDP15_INTEP_DIR_BITS _u(0x02000000) -#define USB_ADDR_ENDP15_INTEP_DIR_MSB _u(25) -#define USB_ADDR_ENDP15_INTEP_DIR_LSB _u(25) -#define USB_ADDR_ENDP15_INTEP_DIR_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_ADDR_ENDP15_ENDPOINT -// Description : Endpoint number of the interrupt endpoint -#define USB_ADDR_ENDP15_ENDPOINT_RESET _u(0x0) -#define USB_ADDR_ENDP15_ENDPOINT_BITS _u(0x000f0000) -#define USB_ADDR_ENDP15_ENDPOINT_MSB _u(19) -#define USB_ADDR_ENDP15_ENDPOINT_LSB _u(16) -#define USB_ADDR_ENDP15_ENDPOINT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_ADDR_ENDP15_ADDRESS -// Description : Device address -#define USB_ADDR_ENDP15_ADDRESS_RESET _u(0x00) -#define USB_ADDR_ENDP15_ADDRESS_BITS _u(0x0000007f) -#define USB_ADDR_ENDP15_ADDRESS_MSB _u(6) -#define USB_ADDR_ENDP15_ADDRESS_LSB _u(0) -#define USB_ADDR_ENDP15_ADDRESS_ACCESS "RW" -// ============================================================================= -// Register : USB_MAIN_CTRL -// Description : Main control register -#define USB_MAIN_CTRL_OFFSET _u(0x00000040) -#define USB_MAIN_CTRL_BITS _u(0x80000007) -#define USB_MAIN_CTRL_RESET _u(0x00000004) -// ----------------------------------------------------------------------------- -// Field : USB_MAIN_CTRL_SIM_TIMING -// Description : Reduced timings for simulation -#define USB_MAIN_CTRL_SIM_TIMING_RESET _u(0x0) -#define USB_MAIN_CTRL_SIM_TIMING_BITS _u(0x80000000) -#define USB_MAIN_CTRL_SIM_TIMING_MSB _u(31) -#define USB_MAIN_CTRL_SIM_TIMING_LSB _u(31) -#define USB_MAIN_CTRL_SIM_TIMING_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_MAIN_CTRL_PHY_ISO -// Description : Isolates USB phy after controller power-up -// Remove isolation once software has configured the controller -// Not isolated = 0, Isolated = 1 -#define USB_MAIN_CTRL_PHY_ISO_RESET _u(0x1) -#define USB_MAIN_CTRL_PHY_ISO_BITS _u(0x00000004) -#define USB_MAIN_CTRL_PHY_ISO_MSB _u(2) -#define USB_MAIN_CTRL_PHY_ISO_LSB _u(2) -#define USB_MAIN_CTRL_PHY_ISO_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_MAIN_CTRL_HOST_NDEVICE -// Description : Device mode = 0, Host mode = 1 -#define USB_MAIN_CTRL_HOST_NDEVICE_RESET _u(0x0) -#define USB_MAIN_CTRL_HOST_NDEVICE_BITS _u(0x00000002) -#define USB_MAIN_CTRL_HOST_NDEVICE_MSB _u(1) -#define USB_MAIN_CTRL_HOST_NDEVICE_LSB _u(1) -#define USB_MAIN_CTRL_HOST_NDEVICE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_MAIN_CTRL_CONTROLLER_EN -// Description : Enable controller -#define USB_MAIN_CTRL_CONTROLLER_EN_RESET _u(0x0) -#define USB_MAIN_CTRL_CONTROLLER_EN_BITS _u(0x00000001) -#define USB_MAIN_CTRL_CONTROLLER_EN_MSB _u(0) -#define USB_MAIN_CTRL_CONTROLLER_EN_LSB _u(0) -#define USB_MAIN_CTRL_CONTROLLER_EN_ACCESS "RW" -// ============================================================================= -// Register : USB_SOF_WR -// Description : Set the SOF (Start of Frame) frame number in the host -// controller. The SOF packet is sent every 1ms and the host will -// increment the frame number by 1 each time. -#define USB_SOF_WR_OFFSET _u(0x00000044) -#define USB_SOF_WR_BITS _u(0x000007ff) -#define USB_SOF_WR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_SOF_WR_COUNT -#define USB_SOF_WR_COUNT_RESET _u(0x000) -#define USB_SOF_WR_COUNT_BITS _u(0x000007ff) -#define USB_SOF_WR_COUNT_MSB _u(10) -#define USB_SOF_WR_COUNT_LSB _u(0) -#define USB_SOF_WR_COUNT_ACCESS "WF" -// ============================================================================= -// Register : USB_SOF_RD -// Description : Read the last SOF (Start of Frame) frame number seen. In device -// mode the last SOF received from the host. In host mode the last -// SOF sent by the host. -#define USB_SOF_RD_OFFSET _u(0x00000048) -#define USB_SOF_RD_BITS _u(0x000007ff) -#define USB_SOF_RD_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_SOF_RD_COUNT -#define USB_SOF_RD_COUNT_RESET _u(0x000) -#define USB_SOF_RD_COUNT_BITS _u(0x000007ff) -#define USB_SOF_RD_COUNT_MSB _u(10) -#define USB_SOF_RD_COUNT_LSB _u(0) -#define USB_SOF_RD_COUNT_ACCESS "RO" -// ============================================================================= -// Register : USB_SIE_CTRL -// Description : SIE control register -#define USB_SIE_CTRL_OFFSET _u(0x0000004c) -#define USB_SIE_CTRL_BITS _u(0xff0fbf5f) -#define USB_SIE_CTRL_RESET _u(0x00008000) -// ----------------------------------------------------------------------------- -// Field : USB_SIE_CTRL_EP0_INT_STALL -// Description : Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a STALL -#define USB_SIE_CTRL_EP0_INT_STALL_RESET _u(0x0) -#define USB_SIE_CTRL_EP0_INT_STALL_BITS _u(0x80000000) -#define USB_SIE_CTRL_EP0_INT_STALL_MSB _u(31) -#define USB_SIE_CTRL_EP0_INT_STALL_LSB _u(31) -#define USB_SIE_CTRL_EP0_INT_STALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_SIE_CTRL_EP0_DOUBLE_BUF -// Description : Device: EP0 single buffered = 0, double buffered = 1 -#define USB_SIE_CTRL_EP0_DOUBLE_BUF_RESET _u(0x0) -#define USB_SIE_CTRL_EP0_DOUBLE_BUF_BITS _u(0x40000000) -#define USB_SIE_CTRL_EP0_DOUBLE_BUF_MSB _u(30) -#define USB_SIE_CTRL_EP0_DOUBLE_BUF_LSB _u(30) -#define USB_SIE_CTRL_EP0_DOUBLE_BUF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_SIE_CTRL_EP0_INT_1BUF -// Description : Device: Set bit in BUFF_STATUS for every buffer completed on -// EP0 -#define USB_SIE_CTRL_EP0_INT_1BUF_RESET _u(0x0) -#define USB_SIE_CTRL_EP0_INT_1BUF_BITS _u(0x20000000) -#define USB_SIE_CTRL_EP0_INT_1BUF_MSB _u(29) -#define USB_SIE_CTRL_EP0_INT_1BUF_LSB _u(29) -#define USB_SIE_CTRL_EP0_INT_1BUF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_SIE_CTRL_EP0_INT_2BUF -// Description : Device: Set bit in BUFF_STATUS for every 2 buffers completed on -// EP0 -#define USB_SIE_CTRL_EP0_INT_2BUF_RESET _u(0x0) -#define USB_SIE_CTRL_EP0_INT_2BUF_BITS _u(0x10000000) -#define USB_SIE_CTRL_EP0_INT_2BUF_MSB _u(28) -#define USB_SIE_CTRL_EP0_INT_2BUF_LSB _u(28) -#define USB_SIE_CTRL_EP0_INT_2BUF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_SIE_CTRL_EP0_INT_NAK -// Description : Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a NAK -#define USB_SIE_CTRL_EP0_INT_NAK_RESET _u(0x0) -#define USB_SIE_CTRL_EP0_INT_NAK_BITS _u(0x08000000) -#define USB_SIE_CTRL_EP0_INT_NAK_MSB _u(27) -#define USB_SIE_CTRL_EP0_INT_NAK_LSB _u(27) -#define USB_SIE_CTRL_EP0_INT_NAK_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_SIE_CTRL_DIRECT_EN -// Description : Direct bus drive enable -#define USB_SIE_CTRL_DIRECT_EN_RESET _u(0x0) -#define USB_SIE_CTRL_DIRECT_EN_BITS _u(0x04000000) -#define USB_SIE_CTRL_DIRECT_EN_MSB _u(26) -#define USB_SIE_CTRL_DIRECT_EN_LSB _u(26) -#define USB_SIE_CTRL_DIRECT_EN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_SIE_CTRL_DIRECT_DP -// Description : Direct control of DP -#define USB_SIE_CTRL_DIRECT_DP_RESET _u(0x0) -#define USB_SIE_CTRL_DIRECT_DP_BITS _u(0x02000000) -#define USB_SIE_CTRL_DIRECT_DP_MSB _u(25) -#define USB_SIE_CTRL_DIRECT_DP_LSB _u(25) -#define USB_SIE_CTRL_DIRECT_DP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_SIE_CTRL_DIRECT_DM -// Description : Direct control of DM -#define USB_SIE_CTRL_DIRECT_DM_RESET _u(0x0) -#define USB_SIE_CTRL_DIRECT_DM_BITS _u(0x01000000) -#define USB_SIE_CTRL_DIRECT_DM_MSB _u(24) -#define USB_SIE_CTRL_DIRECT_DM_LSB _u(24) -#define USB_SIE_CTRL_DIRECT_DM_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_SIE_CTRL_EP0_STOP_ON_SHORT_PACKET -// Description : Device: Stop EP0 on a short packet. -#define USB_SIE_CTRL_EP0_STOP_ON_SHORT_PACKET_RESET _u(0x0) -#define USB_SIE_CTRL_EP0_STOP_ON_SHORT_PACKET_BITS _u(0x00080000) -#define USB_SIE_CTRL_EP0_STOP_ON_SHORT_PACKET_MSB _u(19) -#define USB_SIE_CTRL_EP0_STOP_ON_SHORT_PACKET_LSB _u(19) -#define USB_SIE_CTRL_EP0_STOP_ON_SHORT_PACKET_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_SIE_CTRL_TRANSCEIVER_PD -// Description : Power down bus transceiver -#define USB_SIE_CTRL_TRANSCEIVER_PD_RESET _u(0x0) -#define USB_SIE_CTRL_TRANSCEIVER_PD_BITS _u(0x00040000) -#define USB_SIE_CTRL_TRANSCEIVER_PD_MSB _u(18) -#define USB_SIE_CTRL_TRANSCEIVER_PD_LSB _u(18) -#define USB_SIE_CTRL_TRANSCEIVER_PD_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_SIE_CTRL_RPU_OPT -// Description : Device: Pull-up strength (0=1K2, 1=2k3) -#define USB_SIE_CTRL_RPU_OPT_RESET _u(0x0) -#define USB_SIE_CTRL_RPU_OPT_BITS _u(0x00020000) -#define USB_SIE_CTRL_RPU_OPT_MSB _u(17) -#define USB_SIE_CTRL_RPU_OPT_LSB _u(17) -#define USB_SIE_CTRL_RPU_OPT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_SIE_CTRL_PULLUP_EN -// Description : Device: Enable pull up resistor -#define USB_SIE_CTRL_PULLUP_EN_RESET _u(0x0) -#define USB_SIE_CTRL_PULLUP_EN_BITS _u(0x00010000) -#define USB_SIE_CTRL_PULLUP_EN_MSB _u(16) -#define USB_SIE_CTRL_PULLUP_EN_LSB _u(16) -#define USB_SIE_CTRL_PULLUP_EN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_SIE_CTRL_PULLDOWN_EN -// Description : Host: Enable pull down resistors -#define USB_SIE_CTRL_PULLDOWN_EN_RESET _u(0x1) -#define USB_SIE_CTRL_PULLDOWN_EN_BITS _u(0x00008000) -#define USB_SIE_CTRL_PULLDOWN_EN_MSB _u(15) -#define USB_SIE_CTRL_PULLDOWN_EN_LSB _u(15) -#define USB_SIE_CTRL_PULLDOWN_EN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_SIE_CTRL_RESET_BUS -// Description : Host: Reset bus -#define USB_SIE_CTRL_RESET_BUS_RESET _u(0x0) -#define USB_SIE_CTRL_RESET_BUS_BITS _u(0x00002000) -#define USB_SIE_CTRL_RESET_BUS_MSB _u(13) -#define USB_SIE_CTRL_RESET_BUS_LSB _u(13) -#define USB_SIE_CTRL_RESET_BUS_ACCESS "SC" -// ----------------------------------------------------------------------------- -// Field : USB_SIE_CTRL_RESUME -// Description : Device: Remote wakeup. Device can initiate its own resume after -// suspend. -#define USB_SIE_CTRL_RESUME_RESET _u(0x0) -#define USB_SIE_CTRL_RESUME_BITS _u(0x00001000) -#define USB_SIE_CTRL_RESUME_MSB _u(12) -#define USB_SIE_CTRL_RESUME_LSB _u(12) -#define USB_SIE_CTRL_RESUME_ACCESS "SC" -// ----------------------------------------------------------------------------- -// Field : USB_SIE_CTRL_VBUS_EN -// Description : Host: Enable VBUS -#define USB_SIE_CTRL_VBUS_EN_RESET _u(0x0) -#define USB_SIE_CTRL_VBUS_EN_BITS _u(0x00000800) -#define USB_SIE_CTRL_VBUS_EN_MSB _u(11) -#define USB_SIE_CTRL_VBUS_EN_LSB _u(11) -#define USB_SIE_CTRL_VBUS_EN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_SIE_CTRL_KEEP_ALIVE_EN -// Description : Host: Enable keep alive packet (for low speed bus) -#define USB_SIE_CTRL_KEEP_ALIVE_EN_RESET _u(0x0) -#define USB_SIE_CTRL_KEEP_ALIVE_EN_BITS _u(0x00000400) -#define USB_SIE_CTRL_KEEP_ALIVE_EN_MSB _u(10) -#define USB_SIE_CTRL_KEEP_ALIVE_EN_LSB _u(10) -#define USB_SIE_CTRL_KEEP_ALIVE_EN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_SIE_CTRL_SOF_EN -// Description : Host: Enable SOF generation (for full speed bus) -#define USB_SIE_CTRL_SOF_EN_RESET _u(0x0) -#define USB_SIE_CTRL_SOF_EN_BITS _u(0x00000200) -#define USB_SIE_CTRL_SOF_EN_MSB _u(9) -#define USB_SIE_CTRL_SOF_EN_LSB _u(9) -#define USB_SIE_CTRL_SOF_EN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_SIE_CTRL_SOF_SYNC -// Description : Host: Delay packet(s) until after SOF -#define USB_SIE_CTRL_SOF_SYNC_RESET _u(0x0) -#define USB_SIE_CTRL_SOF_SYNC_BITS _u(0x00000100) -#define USB_SIE_CTRL_SOF_SYNC_MSB _u(8) -#define USB_SIE_CTRL_SOF_SYNC_LSB _u(8) -#define USB_SIE_CTRL_SOF_SYNC_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_SIE_CTRL_PREAMBLE_EN -// Description : Host: Preable enable for LS device on FS hub -#define USB_SIE_CTRL_PREAMBLE_EN_RESET _u(0x0) -#define USB_SIE_CTRL_PREAMBLE_EN_BITS _u(0x00000040) -#define USB_SIE_CTRL_PREAMBLE_EN_MSB _u(6) -#define USB_SIE_CTRL_PREAMBLE_EN_LSB _u(6) -#define USB_SIE_CTRL_PREAMBLE_EN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_SIE_CTRL_STOP_TRANS -// Description : Host: Stop transaction -#define USB_SIE_CTRL_STOP_TRANS_RESET _u(0x0) -#define USB_SIE_CTRL_STOP_TRANS_BITS _u(0x00000010) -#define USB_SIE_CTRL_STOP_TRANS_MSB _u(4) -#define USB_SIE_CTRL_STOP_TRANS_LSB _u(4) -#define USB_SIE_CTRL_STOP_TRANS_ACCESS "SC" -// ----------------------------------------------------------------------------- -// Field : USB_SIE_CTRL_RECEIVE_DATA -// Description : Host: Receive transaction (IN to host) -#define USB_SIE_CTRL_RECEIVE_DATA_RESET _u(0x0) -#define USB_SIE_CTRL_RECEIVE_DATA_BITS _u(0x00000008) -#define USB_SIE_CTRL_RECEIVE_DATA_MSB _u(3) -#define USB_SIE_CTRL_RECEIVE_DATA_LSB _u(3) -#define USB_SIE_CTRL_RECEIVE_DATA_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_SIE_CTRL_SEND_DATA -// Description : Host: Send transaction (OUT from host) -#define USB_SIE_CTRL_SEND_DATA_RESET _u(0x0) -#define USB_SIE_CTRL_SEND_DATA_BITS _u(0x00000004) -#define USB_SIE_CTRL_SEND_DATA_MSB _u(2) -#define USB_SIE_CTRL_SEND_DATA_LSB _u(2) -#define USB_SIE_CTRL_SEND_DATA_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_SIE_CTRL_SEND_SETUP -// Description : Host: Send Setup packet -#define USB_SIE_CTRL_SEND_SETUP_RESET _u(0x0) -#define USB_SIE_CTRL_SEND_SETUP_BITS _u(0x00000002) -#define USB_SIE_CTRL_SEND_SETUP_MSB _u(1) -#define USB_SIE_CTRL_SEND_SETUP_LSB _u(1) -#define USB_SIE_CTRL_SEND_SETUP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_SIE_CTRL_START_TRANS -// Description : Host: Start transaction -#define USB_SIE_CTRL_START_TRANS_RESET _u(0x0) -#define USB_SIE_CTRL_START_TRANS_BITS _u(0x00000001) -#define USB_SIE_CTRL_START_TRANS_MSB _u(0) -#define USB_SIE_CTRL_START_TRANS_LSB _u(0) -#define USB_SIE_CTRL_START_TRANS_ACCESS "SC" -// ============================================================================= -// Register : USB_SIE_STATUS -// Description : SIE status register -#define USB_SIE_STATUS_OFFSET _u(0x00000050) -#define USB_SIE_STATUS_BITS _u(0xff8f1f1d) -#define USB_SIE_STATUS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_SIE_STATUS_DATA_SEQ_ERROR -// Description : Data Sequence Error. -// -// The device can raise a sequence error in the following -// conditions: -// -// * A SETUP packet is received followed by a DATA1 packet (data -// phase should always be DATA0) * An OUT packet is received from -// the host but doesn't match the data pid in the buffer control -// register read from DPSRAM -// -// The host can raise a data sequence error in the following -// conditions: -// -// * An IN packet from the device has the wrong data PID -#define USB_SIE_STATUS_DATA_SEQ_ERROR_RESET _u(0x0) -#define USB_SIE_STATUS_DATA_SEQ_ERROR_BITS _u(0x80000000) -#define USB_SIE_STATUS_DATA_SEQ_ERROR_MSB _u(31) -#define USB_SIE_STATUS_DATA_SEQ_ERROR_LSB _u(31) -#define USB_SIE_STATUS_DATA_SEQ_ERROR_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_SIE_STATUS_ACK_REC -// Description : ACK received. Raised by both host and device. -#define USB_SIE_STATUS_ACK_REC_RESET _u(0x0) -#define USB_SIE_STATUS_ACK_REC_BITS _u(0x40000000) -#define USB_SIE_STATUS_ACK_REC_MSB _u(30) -#define USB_SIE_STATUS_ACK_REC_LSB _u(30) -#define USB_SIE_STATUS_ACK_REC_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_SIE_STATUS_STALL_REC -// Description : Host: STALL received -#define USB_SIE_STATUS_STALL_REC_RESET _u(0x0) -#define USB_SIE_STATUS_STALL_REC_BITS _u(0x20000000) -#define USB_SIE_STATUS_STALL_REC_MSB _u(29) -#define USB_SIE_STATUS_STALL_REC_LSB _u(29) -#define USB_SIE_STATUS_STALL_REC_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_SIE_STATUS_NAK_REC -// Description : Host: NAK received -#define USB_SIE_STATUS_NAK_REC_RESET _u(0x0) -#define USB_SIE_STATUS_NAK_REC_BITS _u(0x10000000) -#define USB_SIE_STATUS_NAK_REC_MSB _u(28) -#define USB_SIE_STATUS_NAK_REC_LSB _u(28) -#define USB_SIE_STATUS_NAK_REC_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_SIE_STATUS_RX_TIMEOUT -// Description : RX timeout is raised by both the host and device if an ACK is -// not received in the maximum time specified by the USB spec. -#define USB_SIE_STATUS_RX_TIMEOUT_RESET _u(0x0) -#define USB_SIE_STATUS_RX_TIMEOUT_BITS _u(0x08000000) -#define USB_SIE_STATUS_RX_TIMEOUT_MSB _u(27) -#define USB_SIE_STATUS_RX_TIMEOUT_LSB _u(27) -#define USB_SIE_STATUS_RX_TIMEOUT_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_SIE_STATUS_RX_OVERFLOW -// Description : RX overflow is raised by the Serial RX engine if the incoming -// data is too fast. -#define USB_SIE_STATUS_RX_OVERFLOW_RESET _u(0x0) -#define USB_SIE_STATUS_RX_OVERFLOW_BITS _u(0x04000000) -#define USB_SIE_STATUS_RX_OVERFLOW_MSB _u(26) -#define USB_SIE_STATUS_RX_OVERFLOW_LSB _u(26) -#define USB_SIE_STATUS_RX_OVERFLOW_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_SIE_STATUS_BIT_STUFF_ERROR -// Description : Bit Stuff Error. Raised by the Serial RX engine. -#define USB_SIE_STATUS_BIT_STUFF_ERROR_RESET _u(0x0) -#define USB_SIE_STATUS_BIT_STUFF_ERROR_BITS _u(0x02000000) -#define USB_SIE_STATUS_BIT_STUFF_ERROR_MSB _u(25) -#define USB_SIE_STATUS_BIT_STUFF_ERROR_LSB _u(25) -#define USB_SIE_STATUS_BIT_STUFF_ERROR_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_SIE_STATUS_CRC_ERROR -// Description : CRC Error. Raised by the Serial RX engine. -#define USB_SIE_STATUS_CRC_ERROR_RESET _u(0x0) -#define USB_SIE_STATUS_CRC_ERROR_BITS _u(0x01000000) -#define USB_SIE_STATUS_CRC_ERROR_MSB _u(24) -#define USB_SIE_STATUS_CRC_ERROR_LSB _u(24) -#define USB_SIE_STATUS_CRC_ERROR_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_SIE_STATUS_ENDPOINT_ERROR -// Description : An endpoint has encountered an error. Read the ep_rx_error and -// ep_tx_error registers to find out which endpoint had an error. -#define USB_SIE_STATUS_ENDPOINT_ERROR_RESET _u(0x0) -#define USB_SIE_STATUS_ENDPOINT_ERROR_BITS _u(0x00800000) -#define USB_SIE_STATUS_ENDPOINT_ERROR_MSB _u(23) -#define USB_SIE_STATUS_ENDPOINT_ERROR_LSB _u(23) -#define USB_SIE_STATUS_ENDPOINT_ERROR_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_SIE_STATUS_BUS_RESET -// Description : Device: bus reset received -#define USB_SIE_STATUS_BUS_RESET_RESET _u(0x0) -#define USB_SIE_STATUS_BUS_RESET_BITS _u(0x00080000) -#define USB_SIE_STATUS_BUS_RESET_MSB _u(19) -#define USB_SIE_STATUS_BUS_RESET_LSB _u(19) -#define USB_SIE_STATUS_BUS_RESET_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_SIE_STATUS_TRANS_COMPLETE -// Description : Transaction complete. -// -// Raised by device if: -// -// * An IN or OUT packet is sent with the `LAST_BUFF` bit set in -// the buffer control register -// -// Raised by host if: -// -// * A setup packet is sent when no data in or data out -// transaction follows * An IN packet is received and the -// `LAST_BUFF` bit is set in the buffer control register * An IN -// packet is received with zero length * An OUT packet is sent and -// the `LAST_BUFF` bit is set -#define USB_SIE_STATUS_TRANS_COMPLETE_RESET _u(0x0) -#define USB_SIE_STATUS_TRANS_COMPLETE_BITS _u(0x00040000) -#define USB_SIE_STATUS_TRANS_COMPLETE_MSB _u(18) -#define USB_SIE_STATUS_TRANS_COMPLETE_LSB _u(18) -#define USB_SIE_STATUS_TRANS_COMPLETE_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_SIE_STATUS_SETUP_REC -// Description : Device: Setup packet received -#define USB_SIE_STATUS_SETUP_REC_RESET _u(0x0) -#define USB_SIE_STATUS_SETUP_REC_BITS _u(0x00020000) -#define USB_SIE_STATUS_SETUP_REC_MSB _u(17) -#define USB_SIE_STATUS_SETUP_REC_LSB _u(17) -#define USB_SIE_STATUS_SETUP_REC_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_SIE_STATUS_CONNECTED -// Description : Device: connected -#define USB_SIE_STATUS_CONNECTED_RESET _u(0x0) -#define USB_SIE_STATUS_CONNECTED_BITS _u(0x00010000) -#define USB_SIE_STATUS_CONNECTED_MSB _u(16) -#define USB_SIE_STATUS_CONNECTED_LSB _u(16) -#define USB_SIE_STATUS_CONNECTED_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_SIE_STATUS_RX_SHORT_PACKET -// Description : Device or Host has received a short packet. This is when the -// data received is less than configured in the buffer control -// register. Device: If using double buffered mode on device the -// buffer select will not be toggled after writing status back to -// the buffer control register. This is to prevent any further -// transactions on that endpoint until the user has reset the -// buffer control registers. Host: the current transfer will be -// stopped early. -#define USB_SIE_STATUS_RX_SHORT_PACKET_RESET _u(0x0) -#define USB_SIE_STATUS_RX_SHORT_PACKET_BITS _u(0x00001000) -#define USB_SIE_STATUS_RX_SHORT_PACKET_MSB _u(12) -#define USB_SIE_STATUS_RX_SHORT_PACKET_LSB _u(12) -#define USB_SIE_STATUS_RX_SHORT_PACKET_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_SIE_STATUS_RESUME -// Description : Host: Device has initiated a remote resume. Device: host has -// initiated a resume. -#define USB_SIE_STATUS_RESUME_RESET _u(0x0) -#define USB_SIE_STATUS_RESUME_BITS _u(0x00000800) -#define USB_SIE_STATUS_RESUME_MSB _u(11) -#define USB_SIE_STATUS_RESUME_LSB _u(11) -#define USB_SIE_STATUS_RESUME_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_SIE_STATUS_VBUS_OVER_CURR -// Description : VBUS over current detected -#define USB_SIE_STATUS_VBUS_OVER_CURR_RESET _u(0x0) -#define USB_SIE_STATUS_VBUS_OVER_CURR_BITS _u(0x00000400) -#define USB_SIE_STATUS_VBUS_OVER_CURR_MSB _u(10) -#define USB_SIE_STATUS_VBUS_OVER_CURR_LSB _u(10) -#define USB_SIE_STATUS_VBUS_OVER_CURR_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_SIE_STATUS_SPEED -// Description : Host: device speed. Disconnected = 00, LS = 01, FS = 10 -#define USB_SIE_STATUS_SPEED_RESET _u(0x0) -#define USB_SIE_STATUS_SPEED_BITS _u(0x00000300) -#define USB_SIE_STATUS_SPEED_MSB _u(9) -#define USB_SIE_STATUS_SPEED_LSB _u(8) -#define USB_SIE_STATUS_SPEED_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_SIE_STATUS_SUSPENDED -// Description : Bus in suspended state. Valid for device. Device will go into -// suspend if neither Keep Alive / SOF frames are enabled. -#define USB_SIE_STATUS_SUSPENDED_RESET _u(0x0) -#define USB_SIE_STATUS_SUSPENDED_BITS _u(0x00000010) -#define USB_SIE_STATUS_SUSPENDED_MSB _u(4) -#define USB_SIE_STATUS_SUSPENDED_LSB _u(4) -#define USB_SIE_STATUS_SUSPENDED_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_SIE_STATUS_LINE_STATE -// Description : USB bus line state -#define USB_SIE_STATUS_LINE_STATE_RESET _u(0x0) -#define USB_SIE_STATUS_LINE_STATE_BITS _u(0x0000000c) -#define USB_SIE_STATUS_LINE_STATE_MSB _u(3) -#define USB_SIE_STATUS_LINE_STATE_LSB _u(2) -#define USB_SIE_STATUS_LINE_STATE_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_SIE_STATUS_VBUS_DETECTED -// Description : Device: VBUS Detected -#define USB_SIE_STATUS_VBUS_DETECTED_RESET _u(0x0) -#define USB_SIE_STATUS_VBUS_DETECTED_BITS _u(0x00000001) -#define USB_SIE_STATUS_VBUS_DETECTED_MSB _u(0) -#define USB_SIE_STATUS_VBUS_DETECTED_LSB _u(0) -#define USB_SIE_STATUS_VBUS_DETECTED_ACCESS "RO" -// ============================================================================= -// Register : USB_INT_EP_CTRL -// Description : interrupt endpoint control register -#define USB_INT_EP_CTRL_OFFSET _u(0x00000054) -#define USB_INT_EP_CTRL_BITS _u(0x0000fffe) -#define USB_INT_EP_CTRL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_INT_EP_CTRL_INT_EP_ACTIVE -// Description : Host: Enable interrupt endpoint 1 -> 15 -#define USB_INT_EP_CTRL_INT_EP_ACTIVE_RESET _u(0x0000) -#define USB_INT_EP_CTRL_INT_EP_ACTIVE_BITS _u(0x0000fffe) -#define USB_INT_EP_CTRL_INT_EP_ACTIVE_MSB _u(15) -#define USB_INT_EP_CTRL_INT_EP_ACTIVE_LSB _u(1) -#define USB_INT_EP_CTRL_INT_EP_ACTIVE_ACCESS "RW" -// ============================================================================= -// Register : USB_BUFF_STATUS -// Description : Buffer status register. A bit set here indicates that a buffer -// has completed on the endpoint (if the buffer interrupt is -// enabled). It is possible for 2 buffers to be completed, so -// clearing the buffer status bit may instantly re set it on the -// next clock cycle. -#define USB_BUFF_STATUS_OFFSET _u(0x00000058) -#define USB_BUFF_STATUS_BITS _u(0xffffffff) -#define USB_BUFF_STATUS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_BUFF_STATUS_EP15_OUT -#define USB_BUFF_STATUS_EP15_OUT_RESET _u(0x0) -#define USB_BUFF_STATUS_EP15_OUT_BITS _u(0x80000000) -#define USB_BUFF_STATUS_EP15_OUT_MSB _u(31) -#define USB_BUFF_STATUS_EP15_OUT_LSB _u(31) -#define USB_BUFF_STATUS_EP15_OUT_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_BUFF_STATUS_EP15_IN -#define USB_BUFF_STATUS_EP15_IN_RESET _u(0x0) -#define USB_BUFF_STATUS_EP15_IN_BITS _u(0x40000000) -#define USB_BUFF_STATUS_EP15_IN_MSB _u(30) -#define USB_BUFF_STATUS_EP15_IN_LSB _u(30) -#define USB_BUFF_STATUS_EP15_IN_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_BUFF_STATUS_EP14_OUT -#define USB_BUFF_STATUS_EP14_OUT_RESET _u(0x0) -#define USB_BUFF_STATUS_EP14_OUT_BITS _u(0x20000000) -#define USB_BUFF_STATUS_EP14_OUT_MSB _u(29) -#define USB_BUFF_STATUS_EP14_OUT_LSB _u(29) -#define USB_BUFF_STATUS_EP14_OUT_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_BUFF_STATUS_EP14_IN -#define USB_BUFF_STATUS_EP14_IN_RESET _u(0x0) -#define USB_BUFF_STATUS_EP14_IN_BITS _u(0x10000000) -#define USB_BUFF_STATUS_EP14_IN_MSB _u(28) -#define USB_BUFF_STATUS_EP14_IN_LSB _u(28) -#define USB_BUFF_STATUS_EP14_IN_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_BUFF_STATUS_EP13_OUT -#define USB_BUFF_STATUS_EP13_OUT_RESET _u(0x0) -#define USB_BUFF_STATUS_EP13_OUT_BITS _u(0x08000000) -#define USB_BUFF_STATUS_EP13_OUT_MSB _u(27) -#define USB_BUFF_STATUS_EP13_OUT_LSB _u(27) -#define USB_BUFF_STATUS_EP13_OUT_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_BUFF_STATUS_EP13_IN -#define USB_BUFF_STATUS_EP13_IN_RESET _u(0x0) -#define USB_BUFF_STATUS_EP13_IN_BITS _u(0x04000000) -#define USB_BUFF_STATUS_EP13_IN_MSB _u(26) -#define USB_BUFF_STATUS_EP13_IN_LSB _u(26) -#define USB_BUFF_STATUS_EP13_IN_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_BUFF_STATUS_EP12_OUT -#define USB_BUFF_STATUS_EP12_OUT_RESET _u(0x0) -#define USB_BUFF_STATUS_EP12_OUT_BITS _u(0x02000000) -#define USB_BUFF_STATUS_EP12_OUT_MSB _u(25) -#define USB_BUFF_STATUS_EP12_OUT_LSB _u(25) -#define USB_BUFF_STATUS_EP12_OUT_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_BUFF_STATUS_EP12_IN -#define USB_BUFF_STATUS_EP12_IN_RESET _u(0x0) -#define USB_BUFF_STATUS_EP12_IN_BITS _u(0x01000000) -#define USB_BUFF_STATUS_EP12_IN_MSB _u(24) -#define USB_BUFF_STATUS_EP12_IN_LSB _u(24) -#define USB_BUFF_STATUS_EP12_IN_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_BUFF_STATUS_EP11_OUT -#define USB_BUFF_STATUS_EP11_OUT_RESET _u(0x0) -#define USB_BUFF_STATUS_EP11_OUT_BITS _u(0x00800000) -#define USB_BUFF_STATUS_EP11_OUT_MSB _u(23) -#define USB_BUFF_STATUS_EP11_OUT_LSB _u(23) -#define USB_BUFF_STATUS_EP11_OUT_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_BUFF_STATUS_EP11_IN -#define USB_BUFF_STATUS_EP11_IN_RESET _u(0x0) -#define USB_BUFF_STATUS_EP11_IN_BITS _u(0x00400000) -#define USB_BUFF_STATUS_EP11_IN_MSB _u(22) -#define USB_BUFF_STATUS_EP11_IN_LSB _u(22) -#define USB_BUFF_STATUS_EP11_IN_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_BUFF_STATUS_EP10_OUT -#define USB_BUFF_STATUS_EP10_OUT_RESET _u(0x0) -#define USB_BUFF_STATUS_EP10_OUT_BITS _u(0x00200000) -#define USB_BUFF_STATUS_EP10_OUT_MSB _u(21) -#define USB_BUFF_STATUS_EP10_OUT_LSB _u(21) -#define USB_BUFF_STATUS_EP10_OUT_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_BUFF_STATUS_EP10_IN -#define USB_BUFF_STATUS_EP10_IN_RESET _u(0x0) -#define USB_BUFF_STATUS_EP10_IN_BITS _u(0x00100000) -#define USB_BUFF_STATUS_EP10_IN_MSB _u(20) -#define USB_BUFF_STATUS_EP10_IN_LSB _u(20) -#define USB_BUFF_STATUS_EP10_IN_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_BUFF_STATUS_EP9_OUT -#define USB_BUFF_STATUS_EP9_OUT_RESET _u(0x0) -#define USB_BUFF_STATUS_EP9_OUT_BITS _u(0x00080000) -#define USB_BUFF_STATUS_EP9_OUT_MSB _u(19) -#define USB_BUFF_STATUS_EP9_OUT_LSB _u(19) -#define USB_BUFF_STATUS_EP9_OUT_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_BUFF_STATUS_EP9_IN -#define USB_BUFF_STATUS_EP9_IN_RESET _u(0x0) -#define USB_BUFF_STATUS_EP9_IN_BITS _u(0x00040000) -#define USB_BUFF_STATUS_EP9_IN_MSB _u(18) -#define USB_BUFF_STATUS_EP9_IN_LSB _u(18) -#define USB_BUFF_STATUS_EP9_IN_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_BUFF_STATUS_EP8_OUT -#define USB_BUFF_STATUS_EP8_OUT_RESET _u(0x0) -#define USB_BUFF_STATUS_EP8_OUT_BITS _u(0x00020000) -#define USB_BUFF_STATUS_EP8_OUT_MSB _u(17) -#define USB_BUFF_STATUS_EP8_OUT_LSB _u(17) -#define USB_BUFF_STATUS_EP8_OUT_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_BUFF_STATUS_EP8_IN -#define USB_BUFF_STATUS_EP8_IN_RESET _u(0x0) -#define USB_BUFF_STATUS_EP8_IN_BITS _u(0x00010000) -#define USB_BUFF_STATUS_EP8_IN_MSB _u(16) -#define USB_BUFF_STATUS_EP8_IN_LSB _u(16) -#define USB_BUFF_STATUS_EP8_IN_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_BUFF_STATUS_EP7_OUT -#define USB_BUFF_STATUS_EP7_OUT_RESET _u(0x0) -#define USB_BUFF_STATUS_EP7_OUT_BITS _u(0x00008000) -#define USB_BUFF_STATUS_EP7_OUT_MSB _u(15) -#define USB_BUFF_STATUS_EP7_OUT_LSB _u(15) -#define USB_BUFF_STATUS_EP7_OUT_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_BUFF_STATUS_EP7_IN -#define USB_BUFF_STATUS_EP7_IN_RESET _u(0x0) -#define USB_BUFF_STATUS_EP7_IN_BITS _u(0x00004000) -#define USB_BUFF_STATUS_EP7_IN_MSB _u(14) -#define USB_BUFF_STATUS_EP7_IN_LSB _u(14) -#define USB_BUFF_STATUS_EP7_IN_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_BUFF_STATUS_EP6_OUT -#define USB_BUFF_STATUS_EP6_OUT_RESET _u(0x0) -#define USB_BUFF_STATUS_EP6_OUT_BITS _u(0x00002000) -#define USB_BUFF_STATUS_EP6_OUT_MSB _u(13) -#define USB_BUFF_STATUS_EP6_OUT_LSB _u(13) -#define USB_BUFF_STATUS_EP6_OUT_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_BUFF_STATUS_EP6_IN -#define USB_BUFF_STATUS_EP6_IN_RESET _u(0x0) -#define USB_BUFF_STATUS_EP6_IN_BITS _u(0x00001000) -#define USB_BUFF_STATUS_EP6_IN_MSB _u(12) -#define USB_BUFF_STATUS_EP6_IN_LSB _u(12) -#define USB_BUFF_STATUS_EP6_IN_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_BUFF_STATUS_EP5_OUT -#define USB_BUFF_STATUS_EP5_OUT_RESET _u(0x0) -#define USB_BUFF_STATUS_EP5_OUT_BITS _u(0x00000800) -#define USB_BUFF_STATUS_EP5_OUT_MSB _u(11) -#define USB_BUFF_STATUS_EP5_OUT_LSB _u(11) -#define USB_BUFF_STATUS_EP5_OUT_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_BUFF_STATUS_EP5_IN -#define USB_BUFF_STATUS_EP5_IN_RESET _u(0x0) -#define USB_BUFF_STATUS_EP5_IN_BITS _u(0x00000400) -#define USB_BUFF_STATUS_EP5_IN_MSB _u(10) -#define USB_BUFF_STATUS_EP5_IN_LSB _u(10) -#define USB_BUFF_STATUS_EP5_IN_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_BUFF_STATUS_EP4_OUT -#define USB_BUFF_STATUS_EP4_OUT_RESET _u(0x0) -#define USB_BUFF_STATUS_EP4_OUT_BITS _u(0x00000200) -#define USB_BUFF_STATUS_EP4_OUT_MSB _u(9) -#define USB_BUFF_STATUS_EP4_OUT_LSB _u(9) -#define USB_BUFF_STATUS_EP4_OUT_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_BUFF_STATUS_EP4_IN -#define USB_BUFF_STATUS_EP4_IN_RESET _u(0x0) -#define USB_BUFF_STATUS_EP4_IN_BITS _u(0x00000100) -#define USB_BUFF_STATUS_EP4_IN_MSB _u(8) -#define USB_BUFF_STATUS_EP4_IN_LSB _u(8) -#define USB_BUFF_STATUS_EP4_IN_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_BUFF_STATUS_EP3_OUT -#define USB_BUFF_STATUS_EP3_OUT_RESET _u(0x0) -#define USB_BUFF_STATUS_EP3_OUT_BITS _u(0x00000080) -#define USB_BUFF_STATUS_EP3_OUT_MSB _u(7) -#define USB_BUFF_STATUS_EP3_OUT_LSB _u(7) -#define USB_BUFF_STATUS_EP3_OUT_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_BUFF_STATUS_EP3_IN -#define USB_BUFF_STATUS_EP3_IN_RESET _u(0x0) -#define USB_BUFF_STATUS_EP3_IN_BITS _u(0x00000040) -#define USB_BUFF_STATUS_EP3_IN_MSB _u(6) -#define USB_BUFF_STATUS_EP3_IN_LSB _u(6) -#define USB_BUFF_STATUS_EP3_IN_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_BUFF_STATUS_EP2_OUT -#define USB_BUFF_STATUS_EP2_OUT_RESET _u(0x0) -#define USB_BUFF_STATUS_EP2_OUT_BITS _u(0x00000020) -#define USB_BUFF_STATUS_EP2_OUT_MSB _u(5) -#define USB_BUFF_STATUS_EP2_OUT_LSB _u(5) -#define USB_BUFF_STATUS_EP2_OUT_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_BUFF_STATUS_EP2_IN -#define USB_BUFF_STATUS_EP2_IN_RESET _u(0x0) -#define USB_BUFF_STATUS_EP2_IN_BITS _u(0x00000010) -#define USB_BUFF_STATUS_EP2_IN_MSB _u(4) -#define USB_BUFF_STATUS_EP2_IN_LSB _u(4) -#define USB_BUFF_STATUS_EP2_IN_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_BUFF_STATUS_EP1_OUT -#define USB_BUFF_STATUS_EP1_OUT_RESET _u(0x0) -#define USB_BUFF_STATUS_EP1_OUT_BITS _u(0x00000008) -#define USB_BUFF_STATUS_EP1_OUT_MSB _u(3) -#define USB_BUFF_STATUS_EP1_OUT_LSB _u(3) -#define USB_BUFF_STATUS_EP1_OUT_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_BUFF_STATUS_EP1_IN -#define USB_BUFF_STATUS_EP1_IN_RESET _u(0x0) -#define USB_BUFF_STATUS_EP1_IN_BITS _u(0x00000004) -#define USB_BUFF_STATUS_EP1_IN_MSB _u(2) -#define USB_BUFF_STATUS_EP1_IN_LSB _u(2) -#define USB_BUFF_STATUS_EP1_IN_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_BUFF_STATUS_EP0_OUT -#define USB_BUFF_STATUS_EP0_OUT_RESET _u(0x0) -#define USB_BUFF_STATUS_EP0_OUT_BITS _u(0x00000002) -#define USB_BUFF_STATUS_EP0_OUT_MSB _u(1) -#define USB_BUFF_STATUS_EP0_OUT_LSB _u(1) -#define USB_BUFF_STATUS_EP0_OUT_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_BUFF_STATUS_EP0_IN -#define USB_BUFF_STATUS_EP0_IN_RESET _u(0x0) -#define USB_BUFF_STATUS_EP0_IN_BITS _u(0x00000001) -#define USB_BUFF_STATUS_EP0_IN_MSB _u(0) -#define USB_BUFF_STATUS_EP0_IN_LSB _u(0) -#define USB_BUFF_STATUS_EP0_IN_ACCESS "WC" -// ============================================================================= -// Register : USB_BUFF_CPU_SHOULD_HANDLE -// Description : Which of the double buffers should be handled. Only valid if -// using an interrupt per buffer (i.e. not per 2 buffers). Not -// valid for host interrupt endpoint polling because they are only -// single buffered. -#define USB_BUFF_CPU_SHOULD_HANDLE_OFFSET _u(0x0000005c) -#define USB_BUFF_CPU_SHOULD_HANDLE_BITS _u(0xffffffff) -#define USB_BUFF_CPU_SHOULD_HANDLE_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP15_OUT -#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_OUT_RESET _u(0x0) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_OUT_BITS _u(0x80000000) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_OUT_MSB _u(31) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_OUT_LSB _u(31) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_OUT_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP15_IN -#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_IN_RESET _u(0x0) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_IN_BITS _u(0x40000000) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_IN_MSB _u(30) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_IN_LSB _u(30) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_IN_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP14_OUT -#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_OUT_RESET _u(0x0) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_OUT_BITS _u(0x20000000) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_OUT_MSB _u(29) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_OUT_LSB _u(29) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_OUT_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP14_IN -#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_IN_RESET _u(0x0) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_IN_BITS _u(0x10000000) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_IN_MSB _u(28) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_IN_LSB _u(28) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_IN_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP13_OUT -#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_OUT_RESET _u(0x0) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_OUT_BITS _u(0x08000000) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_OUT_MSB _u(27) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_OUT_LSB _u(27) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_OUT_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP13_IN -#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_IN_RESET _u(0x0) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_IN_BITS _u(0x04000000) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_IN_MSB _u(26) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_IN_LSB _u(26) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_IN_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP12_OUT -#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_OUT_RESET _u(0x0) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_OUT_BITS _u(0x02000000) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_OUT_MSB _u(25) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_OUT_LSB _u(25) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_OUT_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP12_IN -#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_IN_RESET _u(0x0) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_IN_BITS _u(0x01000000) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_IN_MSB _u(24) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_IN_LSB _u(24) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_IN_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP11_OUT -#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_OUT_RESET _u(0x0) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_OUT_BITS _u(0x00800000) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_OUT_MSB _u(23) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_OUT_LSB _u(23) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_OUT_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP11_IN -#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_IN_RESET _u(0x0) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_IN_BITS _u(0x00400000) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_IN_MSB _u(22) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_IN_LSB _u(22) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_IN_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP10_OUT -#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_OUT_RESET _u(0x0) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_OUT_BITS _u(0x00200000) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_OUT_MSB _u(21) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_OUT_LSB _u(21) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_OUT_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP10_IN -#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_IN_RESET _u(0x0) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_IN_BITS _u(0x00100000) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_IN_MSB _u(20) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_IN_LSB _u(20) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_IN_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP9_OUT -#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_OUT_RESET _u(0x0) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_OUT_BITS _u(0x00080000) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_OUT_MSB _u(19) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_OUT_LSB _u(19) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_OUT_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP9_IN -#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_IN_RESET _u(0x0) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_IN_BITS _u(0x00040000) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_IN_MSB _u(18) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_IN_LSB _u(18) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_IN_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP8_OUT -#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_OUT_RESET _u(0x0) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_OUT_BITS _u(0x00020000) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_OUT_MSB _u(17) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_OUT_LSB _u(17) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_OUT_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP8_IN -#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_IN_RESET _u(0x0) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_IN_BITS _u(0x00010000) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_IN_MSB _u(16) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_IN_LSB _u(16) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_IN_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP7_OUT -#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_OUT_RESET _u(0x0) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_OUT_BITS _u(0x00008000) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_OUT_MSB _u(15) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_OUT_LSB _u(15) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_OUT_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP7_IN -#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_IN_RESET _u(0x0) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_IN_BITS _u(0x00004000) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_IN_MSB _u(14) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_IN_LSB _u(14) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_IN_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP6_OUT -#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_OUT_RESET _u(0x0) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_OUT_BITS _u(0x00002000) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_OUT_MSB _u(13) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_OUT_LSB _u(13) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_OUT_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP6_IN -#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_IN_RESET _u(0x0) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_IN_BITS _u(0x00001000) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_IN_MSB _u(12) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_IN_LSB _u(12) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_IN_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP5_OUT -#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_OUT_RESET _u(0x0) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_OUT_BITS _u(0x00000800) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_OUT_MSB _u(11) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_OUT_LSB _u(11) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_OUT_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP5_IN -#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_IN_RESET _u(0x0) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_IN_BITS _u(0x00000400) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_IN_MSB _u(10) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_IN_LSB _u(10) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_IN_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP4_OUT -#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_OUT_RESET _u(0x0) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_OUT_BITS _u(0x00000200) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_OUT_MSB _u(9) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_OUT_LSB _u(9) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_OUT_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP4_IN -#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_IN_RESET _u(0x0) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_IN_BITS _u(0x00000100) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_IN_MSB _u(8) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_IN_LSB _u(8) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_IN_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP3_OUT -#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_OUT_RESET _u(0x0) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_OUT_BITS _u(0x00000080) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_OUT_MSB _u(7) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_OUT_LSB _u(7) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_OUT_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP3_IN -#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_IN_RESET _u(0x0) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_IN_BITS _u(0x00000040) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_IN_MSB _u(6) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_IN_LSB _u(6) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_IN_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP2_OUT -#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_OUT_RESET _u(0x0) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_OUT_BITS _u(0x00000020) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_OUT_MSB _u(5) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_OUT_LSB _u(5) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_OUT_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP2_IN -#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_IN_RESET _u(0x0) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_IN_BITS _u(0x00000010) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_IN_MSB _u(4) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_IN_LSB _u(4) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_IN_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP1_OUT -#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_OUT_RESET _u(0x0) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_OUT_BITS _u(0x00000008) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_OUT_MSB _u(3) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_OUT_LSB _u(3) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_OUT_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP1_IN -#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_IN_RESET _u(0x0) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_IN_BITS _u(0x00000004) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_IN_MSB _u(2) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_IN_LSB _u(2) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_IN_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP0_OUT -#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_OUT_RESET _u(0x0) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_OUT_BITS _u(0x00000002) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_OUT_MSB _u(1) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_OUT_LSB _u(1) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_OUT_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP0_IN -#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_IN_RESET _u(0x0) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_IN_BITS _u(0x00000001) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_IN_MSB _u(0) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_IN_LSB _u(0) -#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_IN_ACCESS "RO" -// ============================================================================= -// Register : USB_EP_ABORT -// Description : Device only: Can be set to ignore the buffer control register -// for this endpoint in case you would like to revoke a buffer. A -// NAK will be sent for every access to the endpoint until this -// bit is cleared. A corresponding bit in `EP_ABORT_DONE` is set -// when it is safe to modify the buffer control register. -#define USB_EP_ABORT_OFFSET _u(0x00000060) -#define USB_EP_ABORT_BITS _u(0xffffffff) -#define USB_EP_ABORT_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_EP_ABORT_EP15_OUT -#define USB_EP_ABORT_EP15_OUT_RESET _u(0x0) -#define USB_EP_ABORT_EP15_OUT_BITS _u(0x80000000) -#define USB_EP_ABORT_EP15_OUT_MSB _u(31) -#define USB_EP_ABORT_EP15_OUT_LSB _u(31) -#define USB_EP_ABORT_EP15_OUT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_EP_ABORT_EP15_IN -#define USB_EP_ABORT_EP15_IN_RESET _u(0x0) -#define USB_EP_ABORT_EP15_IN_BITS _u(0x40000000) -#define USB_EP_ABORT_EP15_IN_MSB _u(30) -#define USB_EP_ABORT_EP15_IN_LSB _u(30) -#define USB_EP_ABORT_EP15_IN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_EP_ABORT_EP14_OUT -#define USB_EP_ABORT_EP14_OUT_RESET _u(0x0) -#define USB_EP_ABORT_EP14_OUT_BITS _u(0x20000000) -#define USB_EP_ABORT_EP14_OUT_MSB _u(29) -#define USB_EP_ABORT_EP14_OUT_LSB _u(29) -#define USB_EP_ABORT_EP14_OUT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_EP_ABORT_EP14_IN -#define USB_EP_ABORT_EP14_IN_RESET _u(0x0) -#define USB_EP_ABORT_EP14_IN_BITS _u(0x10000000) -#define USB_EP_ABORT_EP14_IN_MSB _u(28) -#define USB_EP_ABORT_EP14_IN_LSB _u(28) -#define USB_EP_ABORT_EP14_IN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_EP_ABORT_EP13_OUT -#define USB_EP_ABORT_EP13_OUT_RESET _u(0x0) -#define USB_EP_ABORT_EP13_OUT_BITS _u(0x08000000) -#define USB_EP_ABORT_EP13_OUT_MSB _u(27) -#define USB_EP_ABORT_EP13_OUT_LSB _u(27) -#define USB_EP_ABORT_EP13_OUT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_EP_ABORT_EP13_IN -#define USB_EP_ABORT_EP13_IN_RESET _u(0x0) -#define USB_EP_ABORT_EP13_IN_BITS _u(0x04000000) -#define USB_EP_ABORT_EP13_IN_MSB _u(26) -#define USB_EP_ABORT_EP13_IN_LSB _u(26) -#define USB_EP_ABORT_EP13_IN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_EP_ABORT_EP12_OUT -#define USB_EP_ABORT_EP12_OUT_RESET _u(0x0) -#define USB_EP_ABORT_EP12_OUT_BITS _u(0x02000000) -#define USB_EP_ABORT_EP12_OUT_MSB _u(25) -#define USB_EP_ABORT_EP12_OUT_LSB _u(25) -#define USB_EP_ABORT_EP12_OUT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_EP_ABORT_EP12_IN -#define USB_EP_ABORT_EP12_IN_RESET _u(0x0) -#define USB_EP_ABORT_EP12_IN_BITS _u(0x01000000) -#define USB_EP_ABORT_EP12_IN_MSB _u(24) -#define USB_EP_ABORT_EP12_IN_LSB _u(24) -#define USB_EP_ABORT_EP12_IN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_EP_ABORT_EP11_OUT -#define USB_EP_ABORT_EP11_OUT_RESET _u(0x0) -#define USB_EP_ABORT_EP11_OUT_BITS _u(0x00800000) -#define USB_EP_ABORT_EP11_OUT_MSB _u(23) -#define USB_EP_ABORT_EP11_OUT_LSB _u(23) -#define USB_EP_ABORT_EP11_OUT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_EP_ABORT_EP11_IN -#define USB_EP_ABORT_EP11_IN_RESET _u(0x0) -#define USB_EP_ABORT_EP11_IN_BITS _u(0x00400000) -#define USB_EP_ABORT_EP11_IN_MSB _u(22) -#define USB_EP_ABORT_EP11_IN_LSB _u(22) -#define USB_EP_ABORT_EP11_IN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_EP_ABORT_EP10_OUT -#define USB_EP_ABORT_EP10_OUT_RESET _u(0x0) -#define USB_EP_ABORT_EP10_OUT_BITS _u(0x00200000) -#define USB_EP_ABORT_EP10_OUT_MSB _u(21) -#define USB_EP_ABORT_EP10_OUT_LSB _u(21) -#define USB_EP_ABORT_EP10_OUT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_EP_ABORT_EP10_IN -#define USB_EP_ABORT_EP10_IN_RESET _u(0x0) -#define USB_EP_ABORT_EP10_IN_BITS _u(0x00100000) -#define USB_EP_ABORT_EP10_IN_MSB _u(20) -#define USB_EP_ABORT_EP10_IN_LSB _u(20) -#define USB_EP_ABORT_EP10_IN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_EP_ABORT_EP9_OUT -#define USB_EP_ABORT_EP9_OUT_RESET _u(0x0) -#define USB_EP_ABORT_EP9_OUT_BITS _u(0x00080000) -#define USB_EP_ABORT_EP9_OUT_MSB _u(19) -#define USB_EP_ABORT_EP9_OUT_LSB _u(19) -#define USB_EP_ABORT_EP9_OUT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_EP_ABORT_EP9_IN -#define USB_EP_ABORT_EP9_IN_RESET _u(0x0) -#define USB_EP_ABORT_EP9_IN_BITS _u(0x00040000) -#define USB_EP_ABORT_EP9_IN_MSB _u(18) -#define USB_EP_ABORT_EP9_IN_LSB _u(18) -#define USB_EP_ABORT_EP9_IN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_EP_ABORT_EP8_OUT -#define USB_EP_ABORT_EP8_OUT_RESET _u(0x0) -#define USB_EP_ABORT_EP8_OUT_BITS _u(0x00020000) -#define USB_EP_ABORT_EP8_OUT_MSB _u(17) -#define USB_EP_ABORT_EP8_OUT_LSB _u(17) -#define USB_EP_ABORT_EP8_OUT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_EP_ABORT_EP8_IN -#define USB_EP_ABORT_EP8_IN_RESET _u(0x0) -#define USB_EP_ABORT_EP8_IN_BITS _u(0x00010000) -#define USB_EP_ABORT_EP8_IN_MSB _u(16) -#define USB_EP_ABORT_EP8_IN_LSB _u(16) -#define USB_EP_ABORT_EP8_IN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_EP_ABORT_EP7_OUT -#define USB_EP_ABORT_EP7_OUT_RESET _u(0x0) -#define USB_EP_ABORT_EP7_OUT_BITS _u(0x00008000) -#define USB_EP_ABORT_EP7_OUT_MSB _u(15) -#define USB_EP_ABORT_EP7_OUT_LSB _u(15) -#define USB_EP_ABORT_EP7_OUT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_EP_ABORT_EP7_IN -#define USB_EP_ABORT_EP7_IN_RESET _u(0x0) -#define USB_EP_ABORT_EP7_IN_BITS _u(0x00004000) -#define USB_EP_ABORT_EP7_IN_MSB _u(14) -#define USB_EP_ABORT_EP7_IN_LSB _u(14) -#define USB_EP_ABORT_EP7_IN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_EP_ABORT_EP6_OUT -#define USB_EP_ABORT_EP6_OUT_RESET _u(0x0) -#define USB_EP_ABORT_EP6_OUT_BITS _u(0x00002000) -#define USB_EP_ABORT_EP6_OUT_MSB _u(13) -#define USB_EP_ABORT_EP6_OUT_LSB _u(13) -#define USB_EP_ABORT_EP6_OUT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_EP_ABORT_EP6_IN -#define USB_EP_ABORT_EP6_IN_RESET _u(0x0) -#define USB_EP_ABORT_EP6_IN_BITS _u(0x00001000) -#define USB_EP_ABORT_EP6_IN_MSB _u(12) -#define USB_EP_ABORT_EP6_IN_LSB _u(12) -#define USB_EP_ABORT_EP6_IN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_EP_ABORT_EP5_OUT -#define USB_EP_ABORT_EP5_OUT_RESET _u(0x0) -#define USB_EP_ABORT_EP5_OUT_BITS _u(0x00000800) -#define USB_EP_ABORT_EP5_OUT_MSB _u(11) -#define USB_EP_ABORT_EP5_OUT_LSB _u(11) -#define USB_EP_ABORT_EP5_OUT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_EP_ABORT_EP5_IN -#define USB_EP_ABORT_EP5_IN_RESET _u(0x0) -#define USB_EP_ABORT_EP5_IN_BITS _u(0x00000400) -#define USB_EP_ABORT_EP5_IN_MSB _u(10) -#define USB_EP_ABORT_EP5_IN_LSB _u(10) -#define USB_EP_ABORT_EP5_IN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_EP_ABORT_EP4_OUT -#define USB_EP_ABORT_EP4_OUT_RESET _u(0x0) -#define USB_EP_ABORT_EP4_OUT_BITS _u(0x00000200) -#define USB_EP_ABORT_EP4_OUT_MSB _u(9) -#define USB_EP_ABORT_EP4_OUT_LSB _u(9) -#define USB_EP_ABORT_EP4_OUT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_EP_ABORT_EP4_IN -#define USB_EP_ABORT_EP4_IN_RESET _u(0x0) -#define USB_EP_ABORT_EP4_IN_BITS _u(0x00000100) -#define USB_EP_ABORT_EP4_IN_MSB _u(8) -#define USB_EP_ABORT_EP4_IN_LSB _u(8) -#define USB_EP_ABORT_EP4_IN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_EP_ABORT_EP3_OUT -#define USB_EP_ABORT_EP3_OUT_RESET _u(0x0) -#define USB_EP_ABORT_EP3_OUT_BITS _u(0x00000080) -#define USB_EP_ABORT_EP3_OUT_MSB _u(7) -#define USB_EP_ABORT_EP3_OUT_LSB _u(7) -#define USB_EP_ABORT_EP3_OUT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_EP_ABORT_EP3_IN -#define USB_EP_ABORT_EP3_IN_RESET _u(0x0) -#define USB_EP_ABORT_EP3_IN_BITS _u(0x00000040) -#define USB_EP_ABORT_EP3_IN_MSB _u(6) -#define USB_EP_ABORT_EP3_IN_LSB _u(6) -#define USB_EP_ABORT_EP3_IN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_EP_ABORT_EP2_OUT -#define USB_EP_ABORT_EP2_OUT_RESET _u(0x0) -#define USB_EP_ABORT_EP2_OUT_BITS _u(0x00000020) -#define USB_EP_ABORT_EP2_OUT_MSB _u(5) -#define USB_EP_ABORT_EP2_OUT_LSB _u(5) -#define USB_EP_ABORT_EP2_OUT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_EP_ABORT_EP2_IN -#define USB_EP_ABORT_EP2_IN_RESET _u(0x0) -#define USB_EP_ABORT_EP2_IN_BITS _u(0x00000010) -#define USB_EP_ABORT_EP2_IN_MSB _u(4) -#define USB_EP_ABORT_EP2_IN_LSB _u(4) -#define USB_EP_ABORT_EP2_IN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_EP_ABORT_EP1_OUT -#define USB_EP_ABORT_EP1_OUT_RESET _u(0x0) -#define USB_EP_ABORT_EP1_OUT_BITS _u(0x00000008) -#define USB_EP_ABORT_EP1_OUT_MSB _u(3) -#define USB_EP_ABORT_EP1_OUT_LSB _u(3) -#define USB_EP_ABORT_EP1_OUT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_EP_ABORT_EP1_IN -#define USB_EP_ABORT_EP1_IN_RESET _u(0x0) -#define USB_EP_ABORT_EP1_IN_BITS _u(0x00000004) -#define USB_EP_ABORT_EP1_IN_MSB _u(2) -#define USB_EP_ABORT_EP1_IN_LSB _u(2) -#define USB_EP_ABORT_EP1_IN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_EP_ABORT_EP0_OUT -#define USB_EP_ABORT_EP0_OUT_RESET _u(0x0) -#define USB_EP_ABORT_EP0_OUT_BITS _u(0x00000002) -#define USB_EP_ABORT_EP0_OUT_MSB _u(1) -#define USB_EP_ABORT_EP0_OUT_LSB _u(1) -#define USB_EP_ABORT_EP0_OUT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_EP_ABORT_EP0_IN -#define USB_EP_ABORT_EP0_IN_RESET _u(0x0) -#define USB_EP_ABORT_EP0_IN_BITS _u(0x00000001) -#define USB_EP_ABORT_EP0_IN_MSB _u(0) -#define USB_EP_ABORT_EP0_IN_LSB _u(0) -#define USB_EP_ABORT_EP0_IN_ACCESS "RW" -// ============================================================================= -// Register : USB_EP_ABORT_DONE -// Description : Device only: Used in conjunction with `EP_ABORT`. Set once an -// endpoint is idle so the programmer knows it is safe to modify -// the buffer control register. -#define USB_EP_ABORT_DONE_OFFSET _u(0x00000064) -#define USB_EP_ABORT_DONE_BITS _u(0xffffffff) -#define USB_EP_ABORT_DONE_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_EP_ABORT_DONE_EP15_OUT -#define USB_EP_ABORT_DONE_EP15_OUT_RESET _u(0x0) -#define USB_EP_ABORT_DONE_EP15_OUT_BITS _u(0x80000000) -#define USB_EP_ABORT_DONE_EP15_OUT_MSB _u(31) -#define USB_EP_ABORT_DONE_EP15_OUT_LSB _u(31) -#define USB_EP_ABORT_DONE_EP15_OUT_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_ABORT_DONE_EP15_IN -#define USB_EP_ABORT_DONE_EP15_IN_RESET _u(0x0) -#define USB_EP_ABORT_DONE_EP15_IN_BITS _u(0x40000000) -#define USB_EP_ABORT_DONE_EP15_IN_MSB _u(30) -#define USB_EP_ABORT_DONE_EP15_IN_LSB _u(30) -#define USB_EP_ABORT_DONE_EP15_IN_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_ABORT_DONE_EP14_OUT -#define USB_EP_ABORT_DONE_EP14_OUT_RESET _u(0x0) -#define USB_EP_ABORT_DONE_EP14_OUT_BITS _u(0x20000000) -#define USB_EP_ABORT_DONE_EP14_OUT_MSB _u(29) -#define USB_EP_ABORT_DONE_EP14_OUT_LSB _u(29) -#define USB_EP_ABORT_DONE_EP14_OUT_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_ABORT_DONE_EP14_IN -#define USB_EP_ABORT_DONE_EP14_IN_RESET _u(0x0) -#define USB_EP_ABORT_DONE_EP14_IN_BITS _u(0x10000000) -#define USB_EP_ABORT_DONE_EP14_IN_MSB _u(28) -#define USB_EP_ABORT_DONE_EP14_IN_LSB _u(28) -#define USB_EP_ABORT_DONE_EP14_IN_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_ABORT_DONE_EP13_OUT -#define USB_EP_ABORT_DONE_EP13_OUT_RESET _u(0x0) -#define USB_EP_ABORT_DONE_EP13_OUT_BITS _u(0x08000000) -#define USB_EP_ABORT_DONE_EP13_OUT_MSB _u(27) -#define USB_EP_ABORT_DONE_EP13_OUT_LSB _u(27) -#define USB_EP_ABORT_DONE_EP13_OUT_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_ABORT_DONE_EP13_IN -#define USB_EP_ABORT_DONE_EP13_IN_RESET _u(0x0) -#define USB_EP_ABORT_DONE_EP13_IN_BITS _u(0x04000000) -#define USB_EP_ABORT_DONE_EP13_IN_MSB _u(26) -#define USB_EP_ABORT_DONE_EP13_IN_LSB _u(26) -#define USB_EP_ABORT_DONE_EP13_IN_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_ABORT_DONE_EP12_OUT -#define USB_EP_ABORT_DONE_EP12_OUT_RESET _u(0x0) -#define USB_EP_ABORT_DONE_EP12_OUT_BITS _u(0x02000000) -#define USB_EP_ABORT_DONE_EP12_OUT_MSB _u(25) -#define USB_EP_ABORT_DONE_EP12_OUT_LSB _u(25) -#define USB_EP_ABORT_DONE_EP12_OUT_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_ABORT_DONE_EP12_IN -#define USB_EP_ABORT_DONE_EP12_IN_RESET _u(0x0) -#define USB_EP_ABORT_DONE_EP12_IN_BITS _u(0x01000000) -#define USB_EP_ABORT_DONE_EP12_IN_MSB _u(24) -#define USB_EP_ABORT_DONE_EP12_IN_LSB _u(24) -#define USB_EP_ABORT_DONE_EP12_IN_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_ABORT_DONE_EP11_OUT -#define USB_EP_ABORT_DONE_EP11_OUT_RESET _u(0x0) -#define USB_EP_ABORT_DONE_EP11_OUT_BITS _u(0x00800000) -#define USB_EP_ABORT_DONE_EP11_OUT_MSB _u(23) -#define USB_EP_ABORT_DONE_EP11_OUT_LSB _u(23) -#define USB_EP_ABORT_DONE_EP11_OUT_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_ABORT_DONE_EP11_IN -#define USB_EP_ABORT_DONE_EP11_IN_RESET _u(0x0) -#define USB_EP_ABORT_DONE_EP11_IN_BITS _u(0x00400000) -#define USB_EP_ABORT_DONE_EP11_IN_MSB _u(22) -#define USB_EP_ABORT_DONE_EP11_IN_LSB _u(22) -#define USB_EP_ABORT_DONE_EP11_IN_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_ABORT_DONE_EP10_OUT -#define USB_EP_ABORT_DONE_EP10_OUT_RESET _u(0x0) -#define USB_EP_ABORT_DONE_EP10_OUT_BITS _u(0x00200000) -#define USB_EP_ABORT_DONE_EP10_OUT_MSB _u(21) -#define USB_EP_ABORT_DONE_EP10_OUT_LSB _u(21) -#define USB_EP_ABORT_DONE_EP10_OUT_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_ABORT_DONE_EP10_IN -#define USB_EP_ABORT_DONE_EP10_IN_RESET _u(0x0) -#define USB_EP_ABORT_DONE_EP10_IN_BITS _u(0x00100000) -#define USB_EP_ABORT_DONE_EP10_IN_MSB _u(20) -#define USB_EP_ABORT_DONE_EP10_IN_LSB _u(20) -#define USB_EP_ABORT_DONE_EP10_IN_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_ABORT_DONE_EP9_OUT -#define USB_EP_ABORT_DONE_EP9_OUT_RESET _u(0x0) -#define USB_EP_ABORT_DONE_EP9_OUT_BITS _u(0x00080000) -#define USB_EP_ABORT_DONE_EP9_OUT_MSB _u(19) -#define USB_EP_ABORT_DONE_EP9_OUT_LSB _u(19) -#define USB_EP_ABORT_DONE_EP9_OUT_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_ABORT_DONE_EP9_IN -#define USB_EP_ABORT_DONE_EP9_IN_RESET _u(0x0) -#define USB_EP_ABORT_DONE_EP9_IN_BITS _u(0x00040000) -#define USB_EP_ABORT_DONE_EP9_IN_MSB _u(18) -#define USB_EP_ABORT_DONE_EP9_IN_LSB _u(18) -#define USB_EP_ABORT_DONE_EP9_IN_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_ABORT_DONE_EP8_OUT -#define USB_EP_ABORT_DONE_EP8_OUT_RESET _u(0x0) -#define USB_EP_ABORT_DONE_EP8_OUT_BITS _u(0x00020000) -#define USB_EP_ABORT_DONE_EP8_OUT_MSB _u(17) -#define USB_EP_ABORT_DONE_EP8_OUT_LSB _u(17) -#define USB_EP_ABORT_DONE_EP8_OUT_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_ABORT_DONE_EP8_IN -#define USB_EP_ABORT_DONE_EP8_IN_RESET _u(0x0) -#define USB_EP_ABORT_DONE_EP8_IN_BITS _u(0x00010000) -#define USB_EP_ABORT_DONE_EP8_IN_MSB _u(16) -#define USB_EP_ABORT_DONE_EP8_IN_LSB _u(16) -#define USB_EP_ABORT_DONE_EP8_IN_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_ABORT_DONE_EP7_OUT -#define USB_EP_ABORT_DONE_EP7_OUT_RESET _u(0x0) -#define USB_EP_ABORT_DONE_EP7_OUT_BITS _u(0x00008000) -#define USB_EP_ABORT_DONE_EP7_OUT_MSB _u(15) -#define USB_EP_ABORT_DONE_EP7_OUT_LSB _u(15) -#define USB_EP_ABORT_DONE_EP7_OUT_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_ABORT_DONE_EP7_IN -#define USB_EP_ABORT_DONE_EP7_IN_RESET _u(0x0) -#define USB_EP_ABORT_DONE_EP7_IN_BITS _u(0x00004000) -#define USB_EP_ABORT_DONE_EP7_IN_MSB _u(14) -#define USB_EP_ABORT_DONE_EP7_IN_LSB _u(14) -#define USB_EP_ABORT_DONE_EP7_IN_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_ABORT_DONE_EP6_OUT -#define USB_EP_ABORT_DONE_EP6_OUT_RESET _u(0x0) -#define USB_EP_ABORT_DONE_EP6_OUT_BITS _u(0x00002000) -#define USB_EP_ABORT_DONE_EP6_OUT_MSB _u(13) -#define USB_EP_ABORT_DONE_EP6_OUT_LSB _u(13) -#define USB_EP_ABORT_DONE_EP6_OUT_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_ABORT_DONE_EP6_IN -#define USB_EP_ABORT_DONE_EP6_IN_RESET _u(0x0) -#define USB_EP_ABORT_DONE_EP6_IN_BITS _u(0x00001000) -#define USB_EP_ABORT_DONE_EP6_IN_MSB _u(12) -#define USB_EP_ABORT_DONE_EP6_IN_LSB _u(12) -#define USB_EP_ABORT_DONE_EP6_IN_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_ABORT_DONE_EP5_OUT -#define USB_EP_ABORT_DONE_EP5_OUT_RESET _u(0x0) -#define USB_EP_ABORT_DONE_EP5_OUT_BITS _u(0x00000800) -#define USB_EP_ABORT_DONE_EP5_OUT_MSB _u(11) -#define USB_EP_ABORT_DONE_EP5_OUT_LSB _u(11) -#define USB_EP_ABORT_DONE_EP5_OUT_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_ABORT_DONE_EP5_IN -#define USB_EP_ABORT_DONE_EP5_IN_RESET _u(0x0) -#define USB_EP_ABORT_DONE_EP5_IN_BITS _u(0x00000400) -#define USB_EP_ABORT_DONE_EP5_IN_MSB _u(10) -#define USB_EP_ABORT_DONE_EP5_IN_LSB _u(10) -#define USB_EP_ABORT_DONE_EP5_IN_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_ABORT_DONE_EP4_OUT -#define USB_EP_ABORT_DONE_EP4_OUT_RESET _u(0x0) -#define USB_EP_ABORT_DONE_EP4_OUT_BITS _u(0x00000200) -#define USB_EP_ABORT_DONE_EP4_OUT_MSB _u(9) -#define USB_EP_ABORT_DONE_EP4_OUT_LSB _u(9) -#define USB_EP_ABORT_DONE_EP4_OUT_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_ABORT_DONE_EP4_IN -#define USB_EP_ABORT_DONE_EP4_IN_RESET _u(0x0) -#define USB_EP_ABORT_DONE_EP4_IN_BITS _u(0x00000100) -#define USB_EP_ABORT_DONE_EP4_IN_MSB _u(8) -#define USB_EP_ABORT_DONE_EP4_IN_LSB _u(8) -#define USB_EP_ABORT_DONE_EP4_IN_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_ABORT_DONE_EP3_OUT -#define USB_EP_ABORT_DONE_EP3_OUT_RESET _u(0x0) -#define USB_EP_ABORT_DONE_EP3_OUT_BITS _u(0x00000080) -#define USB_EP_ABORT_DONE_EP3_OUT_MSB _u(7) -#define USB_EP_ABORT_DONE_EP3_OUT_LSB _u(7) -#define USB_EP_ABORT_DONE_EP3_OUT_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_ABORT_DONE_EP3_IN -#define USB_EP_ABORT_DONE_EP3_IN_RESET _u(0x0) -#define USB_EP_ABORT_DONE_EP3_IN_BITS _u(0x00000040) -#define USB_EP_ABORT_DONE_EP3_IN_MSB _u(6) -#define USB_EP_ABORT_DONE_EP3_IN_LSB _u(6) -#define USB_EP_ABORT_DONE_EP3_IN_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_ABORT_DONE_EP2_OUT -#define USB_EP_ABORT_DONE_EP2_OUT_RESET _u(0x0) -#define USB_EP_ABORT_DONE_EP2_OUT_BITS _u(0x00000020) -#define USB_EP_ABORT_DONE_EP2_OUT_MSB _u(5) -#define USB_EP_ABORT_DONE_EP2_OUT_LSB _u(5) -#define USB_EP_ABORT_DONE_EP2_OUT_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_ABORT_DONE_EP2_IN -#define USB_EP_ABORT_DONE_EP2_IN_RESET _u(0x0) -#define USB_EP_ABORT_DONE_EP2_IN_BITS _u(0x00000010) -#define USB_EP_ABORT_DONE_EP2_IN_MSB _u(4) -#define USB_EP_ABORT_DONE_EP2_IN_LSB _u(4) -#define USB_EP_ABORT_DONE_EP2_IN_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_ABORT_DONE_EP1_OUT -#define USB_EP_ABORT_DONE_EP1_OUT_RESET _u(0x0) -#define USB_EP_ABORT_DONE_EP1_OUT_BITS _u(0x00000008) -#define USB_EP_ABORT_DONE_EP1_OUT_MSB _u(3) -#define USB_EP_ABORT_DONE_EP1_OUT_LSB _u(3) -#define USB_EP_ABORT_DONE_EP1_OUT_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_ABORT_DONE_EP1_IN -#define USB_EP_ABORT_DONE_EP1_IN_RESET _u(0x0) -#define USB_EP_ABORT_DONE_EP1_IN_BITS _u(0x00000004) -#define USB_EP_ABORT_DONE_EP1_IN_MSB _u(2) -#define USB_EP_ABORT_DONE_EP1_IN_LSB _u(2) -#define USB_EP_ABORT_DONE_EP1_IN_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_ABORT_DONE_EP0_OUT -#define USB_EP_ABORT_DONE_EP0_OUT_RESET _u(0x0) -#define USB_EP_ABORT_DONE_EP0_OUT_BITS _u(0x00000002) -#define USB_EP_ABORT_DONE_EP0_OUT_MSB _u(1) -#define USB_EP_ABORT_DONE_EP0_OUT_LSB _u(1) -#define USB_EP_ABORT_DONE_EP0_OUT_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_ABORT_DONE_EP0_IN -#define USB_EP_ABORT_DONE_EP0_IN_RESET _u(0x0) -#define USB_EP_ABORT_DONE_EP0_IN_BITS _u(0x00000001) -#define USB_EP_ABORT_DONE_EP0_IN_MSB _u(0) -#define USB_EP_ABORT_DONE_EP0_IN_LSB _u(0) -#define USB_EP_ABORT_DONE_EP0_IN_ACCESS "WC" -// ============================================================================= -// Register : USB_EP_STALL_ARM -// Description : Device: this bit must be set in conjunction with the `STALL` -// bit in the buffer control register to send a STALL on EP0. The -// device controller clears these bits when a SETUP packet is -// received because the USB spec requires that a STALL condition -// is cleared when a SETUP packet is received. -#define USB_EP_STALL_ARM_OFFSET _u(0x00000068) -#define USB_EP_STALL_ARM_BITS _u(0x00000003) -#define USB_EP_STALL_ARM_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_EP_STALL_ARM_EP0_OUT -#define USB_EP_STALL_ARM_EP0_OUT_RESET _u(0x0) -#define USB_EP_STALL_ARM_EP0_OUT_BITS _u(0x00000002) -#define USB_EP_STALL_ARM_EP0_OUT_MSB _u(1) -#define USB_EP_STALL_ARM_EP0_OUT_LSB _u(1) -#define USB_EP_STALL_ARM_EP0_OUT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_EP_STALL_ARM_EP0_IN -#define USB_EP_STALL_ARM_EP0_IN_RESET _u(0x0) -#define USB_EP_STALL_ARM_EP0_IN_BITS _u(0x00000001) -#define USB_EP_STALL_ARM_EP0_IN_MSB _u(0) -#define USB_EP_STALL_ARM_EP0_IN_LSB _u(0) -#define USB_EP_STALL_ARM_EP0_IN_ACCESS "RW" -// ============================================================================= -// Register : USB_NAK_POLL -// Description : Used by the host controller. Sets the wait time in microseconds -// before trying again if the device replies with a NAK. -#define USB_NAK_POLL_OFFSET _u(0x0000006c) -#define USB_NAK_POLL_BITS _u(0xffffffff) -#define USB_NAK_POLL_RESET _u(0x00100010) -// ----------------------------------------------------------------------------- -// Field : USB_NAK_POLL_RETRY_COUNT_HI -// Description : Bits 9:6 of nak_retry count -#define USB_NAK_POLL_RETRY_COUNT_HI_RESET _u(0x0) -#define USB_NAK_POLL_RETRY_COUNT_HI_BITS _u(0xf0000000) -#define USB_NAK_POLL_RETRY_COUNT_HI_MSB _u(31) -#define USB_NAK_POLL_RETRY_COUNT_HI_LSB _u(28) -#define USB_NAK_POLL_RETRY_COUNT_HI_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_NAK_POLL_EPX_STOPPED_ON_NAK -// Description : EPX polling has stopped because a nak was received -#define USB_NAK_POLL_EPX_STOPPED_ON_NAK_RESET _u(0x0) -#define USB_NAK_POLL_EPX_STOPPED_ON_NAK_BITS _u(0x08000000) -#define USB_NAK_POLL_EPX_STOPPED_ON_NAK_MSB _u(27) -#define USB_NAK_POLL_EPX_STOPPED_ON_NAK_LSB _u(27) -#define USB_NAK_POLL_EPX_STOPPED_ON_NAK_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_NAK_POLL_STOP_EPX_ON_NAK -// Description : Stop polling epx when a nak is received -#define USB_NAK_POLL_STOP_EPX_ON_NAK_RESET _u(0x0) -#define USB_NAK_POLL_STOP_EPX_ON_NAK_BITS _u(0x04000000) -#define USB_NAK_POLL_STOP_EPX_ON_NAK_MSB _u(26) -#define USB_NAK_POLL_STOP_EPX_ON_NAK_LSB _u(26) -#define USB_NAK_POLL_STOP_EPX_ON_NAK_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_NAK_POLL_DELAY_FS -// Description : NAK polling interval for a full speed device -#define USB_NAK_POLL_DELAY_FS_RESET _u(0x010) -#define USB_NAK_POLL_DELAY_FS_BITS _u(0x03ff0000) -#define USB_NAK_POLL_DELAY_FS_MSB _u(25) -#define USB_NAK_POLL_DELAY_FS_LSB _u(16) -#define USB_NAK_POLL_DELAY_FS_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_NAK_POLL_RETRY_COUNT_LO -// Description : Bits 5:0 of nak_retry_count -#define USB_NAK_POLL_RETRY_COUNT_LO_RESET _u(0x00) -#define USB_NAK_POLL_RETRY_COUNT_LO_BITS _u(0x0000fc00) -#define USB_NAK_POLL_RETRY_COUNT_LO_MSB _u(15) -#define USB_NAK_POLL_RETRY_COUNT_LO_LSB _u(10) -#define USB_NAK_POLL_RETRY_COUNT_LO_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_NAK_POLL_DELAY_LS -// Description : NAK polling interval for a low speed device -#define USB_NAK_POLL_DELAY_LS_RESET _u(0x010) -#define USB_NAK_POLL_DELAY_LS_BITS _u(0x000003ff) -#define USB_NAK_POLL_DELAY_LS_MSB _u(9) -#define USB_NAK_POLL_DELAY_LS_LSB _u(0) -#define USB_NAK_POLL_DELAY_LS_ACCESS "RW" -// ============================================================================= -// Register : USB_EP_STATUS_STALL_NAK -// Description : Device: bits are set when the `IRQ_ON_NAK` or `IRQ_ON_STALL` -// bits are set. For EP0 this comes from `SIE_CTRL`. For all other -// endpoints it comes from the endpoint control register. -#define USB_EP_STATUS_STALL_NAK_OFFSET _u(0x00000070) -#define USB_EP_STATUS_STALL_NAK_BITS _u(0xffffffff) -#define USB_EP_STATUS_STALL_NAK_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_EP_STATUS_STALL_NAK_EP15_OUT -#define USB_EP_STATUS_STALL_NAK_EP15_OUT_RESET _u(0x0) -#define USB_EP_STATUS_STALL_NAK_EP15_OUT_BITS _u(0x80000000) -#define USB_EP_STATUS_STALL_NAK_EP15_OUT_MSB _u(31) -#define USB_EP_STATUS_STALL_NAK_EP15_OUT_LSB _u(31) -#define USB_EP_STATUS_STALL_NAK_EP15_OUT_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_STATUS_STALL_NAK_EP15_IN -#define USB_EP_STATUS_STALL_NAK_EP15_IN_RESET _u(0x0) -#define USB_EP_STATUS_STALL_NAK_EP15_IN_BITS _u(0x40000000) -#define USB_EP_STATUS_STALL_NAK_EP15_IN_MSB _u(30) -#define USB_EP_STATUS_STALL_NAK_EP15_IN_LSB _u(30) -#define USB_EP_STATUS_STALL_NAK_EP15_IN_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_STATUS_STALL_NAK_EP14_OUT -#define USB_EP_STATUS_STALL_NAK_EP14_OUT_RESET _u(0x0) -#define USB_EP_STATUS_STALL_NAK_EP14_OUT_BITS _u(0x20000000) -#define USB_EP_STATUS_STALL_NAK_EP14_OUT_MSB _u(29) -#define USB_EP_STATUS_STALL_NAK_EP14_OUT_LSB _u(29) -#define USB_EP_STATUS_STALL_NAK_EP14_OUT_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_STATUS_STALL_NAK_EP14_IN -#define USB_EP_STATUS_STALL_NAK_EP14_IN_RESET _u(0x0) -#define USB_EP_STATUS_STALL_NAK_EP14_IN_BITS _u(0x10000000) -#define USB_EP_STATUS_STALL_NAK_EP14_IN_MSB _u(28) -#define USB_EP_STATUS_STALL_NAK_EP14_IN_LSB _u(28) -#define USB_EP_STATUS_STALL_NAK_EP14_IN_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_STATUS_STALL_NAK_EP13_OUT -#define USB_EP_STATUS_STALL_NAK_EP13_OUT_RESET _u(0x0) -#define USB_EP_STATUS_STALL_NAK_EP13_OUT_BITS _u(0x08000000) -#define USB_EP_STATUS_STALL_NAK_EP13_OUT_MSB _u(27) -#define USB_EP_STATUS_STALL_NAK_EP13_OUT_LSB _u(27) -#define USB_EP_STATUS_STALL_NAK_EP13_OUT_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_STATUS_STALL_NAK_EP13_IN -#define USB_EP_STATUS_STALL_NAK_EP13_IN_RESET _u(0x0) -#define USB_EP_STATUS_STALL_NAK_EP13_IN_BITS _u(0x04000000) -#define USB_EP_STATUS_STALL_NAK_EP13_IN_MSB _u(26) -#define USB_EP_STATUS_STALL_NAK_EP13_IN_LSB _u(26) -#define USB_EP_STATUS_STALL_NAK_EP13_IN_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_STATUS_STALL_NAK_EP12_OUT -#define USB_EP_STATUS_STALL_NAK_EP12_OUT_RESET _u(0x0) -#define USB_EP_STATUS_STALL_NAK_EP12_OUT_BITS _u(0x02000000) -#define USB_EP_STATUS_STALL_NAK_EP12_OUT_MSB _u(25) -#define USB_EP_STATUS_STALL_NAK_EP12_OUT_LSB _u(25) -#define USB_EP_STATUS_STALL_NAK_EP12_OUT_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_STATUS_STALL_NAK_EP12_IN -#define USB_EP_STATUS_STALL_NAK_EP12_IN_RESET _u(0x0) -#define USB_EP_STATUS_STALL_NAK_EP12_IN_BITS _u(0x01000000) -#define USB_EP_STATUS_STALL_NAK_EP12_IN_MSB _u(24) -#define USB_EP_STATUS_STALL_NAK_EP12_IN_LSB _u(24) -#define USB_EP_STATUS_STALL_NAK_EP12_IN_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_STATUS_STALL_NAK_EP11_OUT -#define USB_EP_STATUS_STALL_NAK_EP11_OUT_RESET _u(0x0) -#define USB_EP_STATUS_STALL_NAK_EP11_OUT_BITS _u(0x00800000) -#define USB_EP_STATUS_STALL_NAK_EP11_OUT_MSB _u(23) -#define USB_EP_STATUS_STALL_NAK_EP11_OUT_LSB _u(23) -#define USB_EP_STATUS_STALL_NAK_EP11_OUT_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_STATUS_STALL_NAK_EP11_IN -#define USB_EP_STATUS_STALL_NAK_EP11_IN_RESET _u(0x0) -#define USB_EP_STATUS_STALL_NAK_EP11_IN_BITS _u(0x00400000) -#define USB_EP_STATUS_STALL_NAK_EP11_IN_MSB _u(22) -#define USB_EP_STATUS_STALL_NAK_EP11_IN_LSB _u(22) -#define USB_EP_STATUS_STALL_NAK_EP11_IN_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_STATUS_STALL_NAK_EP10_OUT -#define USB_EP_STATUS_STALL_NAK_EP10_OUT_RESET _u(0x0) -#define USB_EP_STATUS_STALL_NAK_EP10_OUT_BITS _u(0x00200000) -#define USB_EP_STATUS_STALL_NAK_EP10_OUT_MSB _u(21) -#define USB_EP_STATUS_STALL_NAK_EP10_OUT_LSB _u(21) -#define USB_EP_STATUS_STALL_NAK_EP10_OUT_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_STATUS_STALL_NAK_EP10_IN -#define USB_EP_STATUS_STALL_NAK_EP10_IN_RESET _u(0x0) -#define USB_EP_STATUS_STALL_NAK_EP10_IN_BITS _u(0x00100000) -#define USB_EP_STATUS_STALL_NAK_EP10_IN_MSB _u(20) -#define USB_EP_STATUS_STALL_NAK_EP10_IN_LSB _u(20) -#define USB_EP_STATUS_STALL_NAK_EP10_IN_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_STATUS_STALL_NAK_EP9_OUT -#define USB_EP_STATUS_STALL_NAK_EP9_OUT_RESET _u(0x0) -#define USB_EP_STATUS_STALL_NAK_EP9_OUT_BITS _u(0x00080000) -#define USB_EP_STATUS_STALL_NAK_EP9_OUT_MSB _u(19) -#define USB_EP_STATUS_STALL_NAK_EP9_OUT_LSB _u(19) -#define USB_EP_STATUS_STALL_NAK_EP9_OUT_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_STATUS_STALL_NAK_EP9_IN -#define USB_EP_STATUS_STALL_NAK_EP9_IN_RESET _u(0x0) -#define USB_EP_STATUS_STALL_NAK_EP9_IN_BITS _u(0x00040000) -#define USB_EP_STATUS_STALL_NAK_EP9_IN_MSB _u(18) -#define USB_EP_STATUS_STALL_NAK_EP9_IN_LSB _u(18) -#define USB_EP_STATUS_STALL_NAK_EP9_IN_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_STATUS_STALL_NAK_EP8_OUT -#define USB_EP_STATUS_STALL_NAK_EP8_OUT_RESET _u(0x0) -#define USB_EP_STATUS_STALL_NAK_EP8_OUT_BITS _u(0x00020000) -#define USB_EP_STATUS_STALL_NAK_EP8_OUT_MSB _u(17) -#define USB_EP_STATUS_STALL_NAK_EP8_OUT_LSB _u(17) -#define USB_EP_STATUS_STALL_NAK_EP8_OUT_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_STATUS_STALL_NAK_EP8_IN -#define USB_EP_STATUS_STALL_NAK_EP8_IN_RESET _u(0x0) -#define USB_EP_STATUS_STALL_NAK_EP8_IN_BITS _u(0x00010000) -#define USB_EP_STATUS_STALL_NAK_EP8_IN_MSB _u(16) -#define USB_EP_STATUS_STALL_NAK_EP8_IN_LSB _u(16) -#define USB_EP_STATUS_STALL_NAK_EP8_IN_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_STATUS_STALL_NAK_EP7_OUT -#define USB_EP_STATUS_STALL_NAK_EP7_OUT_RESET _u(0x0) -#define USB_EP_STATUS_STALL_NAK_EP7_OUT_BITS _u(0x00008000) -#define USB_EP_STATUS_STALL_NAK_EP7_OUT_MSB _u(15) -#define USB_EP_STATUS_STALL_NAK_EP7_OUT_LSB _u(15) -#define USB_EP_STATUS_STALL_NAK_EP7_OUT_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_STATUS_STALL_NAK_EP7_IN -#define USB_EP_STATUS_STALL_NAK_EP7_IN_RESET _u(0x0) -#define USB_EP_STATUS_STALL_NAK_EP7_IN_BITS _u(0x00004000) -#define USB_EP_STATUS_STALL_NAK_EP7_IN_MSB _u(14) -#define USB_EP_STATUS_STALL_NAK_EP7_IN_LSB _u(14) -#define USB_EP_STATUS_STALL_NAK_EP7_IN_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_STATUS_STALL_NAK_EP6_OUT -#define USB_EP_STATUS_STALL_NAK_EP6_OUT_RESET _u(0x0) -#define USB_EP_STATUS_STALL_NAK_EP6_OUT_BITS _u(0x00002000) -#define USB_EP_STATUS_STALL_NAK_EP6_OUT_MSB _u(13) -#define USB_EP_STATUS_STALL_NAK_EP6_OUT_LSB _u(13) -#define USB_EP_STATUS_STALL_NAK_EP6_OUT_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_STATUS_STALL_NAK_EP6_IN -#define USB_EP_STATUS_STALL_NAK_EP6_IN_RESET _u(0x0) -#define USB_EP_STATUS_STALL_NAK_EP6_IN_BITS _u(0x00001000) -#define USB_EP_STATUS_STALL_NAK_EP6_IN_MSB _u(12) -#define USB_EP_STATUS_STALL_NAK_EP6_IN_LSB _u(12) -#define USB_EP_STATUS_STALL_NAK_EP6_IN_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_STATUS_STALL_NAK_EP5_OUT -#define USB_EP_STATUS_STALL_NAK_EP5_OUT_RESET _u(0x0) -#define USB_EP_STATUS_STALL_NAK_EP5_OUT_BITS _u(0x00000800) -#define USB_EP_STATUS_STALL_NAK_EP5_OUT_MSB _u(11) -#define USB_EP_STATUS_STALL_NAK_EP5_OUT_LSB _u(11) -#define USB_EP_STATUS_STALL_NAK_EP5_OUT_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_STATUS_STALL_NAK_EP5_IN -#define USB_EP_STATUS_STALL_NAK_EP5_IN_RESET _u(0x0) -#define USB_EP_STATUS_STALL_NAK_EP5_IN_BITS _u(0x00000400) -#define USB_EP_STATUS_STALL_NAK_EP5_IN_MSB _u(10) -#define USB_EP_STATUS_STALL_NAK_EP5_IN_LSB _u(10) -#define USB_EP_STATUS_STALL_NAK_EP5_IN_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_STATUS_STALL_NAK_EP4_OUT -#define USB_EP_STATUS_STALL_NAK_EP4_OUT_RESET _u(0x0) -#define USB_EP_STATUS_STALL_NAK_EP4_OUT_BITS _u(0x00000200) -#define USB_EP_STATUS_STALL_NAK_EP4_OUT_MSB _u(9) -#define USB_EP_STATUS_STALL_NAK_EP4_OUT_LSB _u(9) -#define USB_EP_STATUS_STALL_NAK_EP4_OUT_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_STATUS_STALL_NAK_EP4_IN -#define USB_EP_STATUS_STALL_NAK_EP4_IN_RESET _u(0x0) -#define USB_EP_STATUS_STALL_NAK_EP4_IN_BITS _u(0x00000100) -#define USB_EP_STATUS_STALL_NAK_EP4_IN_MSB _u(8) -#define USB_EP_STATUS_STALL_NAK_EP4_IN_LSB _u(8) -#define USB_EP_STATUS_STALL_NAK_EP4_IN_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_STATUS_STALL_NAK_EP3_OUT -#define USB_EP_STATUS_STALL_NAK_EP3_OUT_RESET _u(0x0) -#define USB_EP_STATUS_STALL_NAK_EP3_OUT_BITS _u(0x00000080) -#define USB_EP_STATUS_STALL_NAK_EP3_OUT_MSB _u(7) -#define USB_EP_STATUS_STALL_NAK_EP3_OUT_LSB _u(7) -#define USB_EP_STATUS_STALL_NAK_EP3_OUT_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_STATUS_STALL_NAK_EP3_IN -#define USB_EP_STATUS_STALL_NAK_EP3_IN_RESET _u(0x0) -#define USB_EP_STATUS_STALL_NAK_EP3_IN_BITS _u(0x00000040) -#define USB_EP_STATUS_STALL_NAK_EP3_IN_MSB _u(6) -#define USB_EP_STATUS_STALL_NAK_EP3_IN_LSB _u(6) -#define USB_EP_STATUS_STALL_NAK_EP3_IN_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_STATUS_STALL_NAK_EP2_OUT -#define USB_EP_STATUS_STALL_NAK_EP2_OUT_RESET _u(0x0) -#define USB_EP_STATUS_STALL_NAK_EP2_OUT_BITS _u(0x00000020) -#define USB_EP_STATUS_STALL_NAK_EP2_OUT_MSB _u(5) -#define USB_EP_STATUS_STALL_NAK_EP2_OUT_LSB _u(5) -#define USB_EP_STATUS_STALL_NAK_EP2_OUT_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_STATUS_STALL_NAK_EP2_IN -#define USB_EP_STATUS_STALL_NAK_EP2_IN_RESET _u(0x0) -#define USB_EP_STATUS_STALL_NAK_EP2_IN_BITS _u(0x00000010) -#define USB_EP_STATUS_STALL_NAK_EP2_IN_MSB _u(4) -#define USB_EP_STATUS_STALL_NAK_EP2_IN_LSB _u(4) -#define USB_EP_STATUS_STALL_NAK_EP2_IN_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_STATUS_STALL_NAK_EP1_OUT -#define USB_EP_STATUS_STALL_NAK_EP1_OUT_RESET _u(0x0) -#define USB_EP_STATUS_STALL_NAK_EP1_OUT_BITS _u(0x00000008) -#define USB_EP_STATUS_STALL_NAK_EP1_OUT_MSB _u(3) -#define USB_EP_STATUS_STALL_NAK_EP1_OUT_LSB _u(3) -#define USB_EP_STATUS_STALL_NAK_EP1_OUT_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_STATUS_STALL_NAK_EP1_IN -#define USB_EP_STATUS_STALL_NAK_EP1_IN_RESET _u(0x0) -#define USB_EP_STATUS_STALL_NAK_EP1_IN_BITS _u(0x00000004) -#define USB_EP_STATUS_STALL_NAK_EP1_IN_MSB _u(2) -#define USB_EP_STATUS_STALL_NAK_EP1_IN_LSB _u(2) -#define USB_EP_STATUS_STALL_NAK_EP1_IN_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_STATUS_STALL_NAK_EP0_OUT -#define USB_EP_STATUS_STALL_NAK_EP0_OUT_RESET _u(0x0) -#define USB_EP_STATUS_STALL_NAK_EP0_OUT_BITS _u(0x00000002) -#define USB_EP_STATUS_STALL_NAK_EP0_OUT_MSB _u(1) -#define USB_EP_STATUS_STALL_NAK_EP0_OUT_LSB _u(1) -#define USB_EP_STATUS_STALL_NAK_EP0_OUT_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_STATUS_STALL_NAK_EP0_IN -#define USB_EP_STATUS_STALL_NAK_EP0_IN_RESET _u(0x0) -#define USB_EP_STATUS_STALL_NAK_EP0_IN_BITS _u(0x00000001) -#define USB_EP_STATUS_STALL_NAK_EP0_IN_MSB _u(0) -#define USB_EP_STATUS_STALL_NAK_EP0_IN_LSB _u(0) -#define USB_EP_STATUS_STALL_NAK_EP0_IN_ACCESS "WC" -// ============================================================================= -// Register : USB_USB_MUXING -// Description : Where to connect the USB controller. Should be to_phy by -// default. -#define USB_USB_MUXING_OFFSET _u(0x00000074) -#define USB_USB_MUXING_BITS _u(0x8000001f) -#define USB_USB_MUXING_RESET _u(0x00000001) -// ----------------------------------------------------------------------------- -// Field : USB_USB_MUXING_SWAP_DPDM -// Description : Swap the USB PHY DP and DM pins and all related controls and -// flip receive differential data. Can be used to switch USB DP/DP -// on the PCB. -// This is done at a low level so overrides all other controls. -#define USB_USB_MUXING_SWAP_DPDM_RESET _u(0x0) -#define USB_USB_MUXING_SWAP_DPDM_BITS _u(0x80000000) -#define USB_USB_MUXING_SWAP_DPDM_MSB _u(31) -#define USB_USB_MUXING_SWAP_DPDM_LSB _u(31) -#define USB_USB_MUXING_SWAP_DPDM_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_USB_MUXING_USBPHY_AS_GPIO -// Description : Use the usb DP and DM pins as GPIO pins instead of connecting -// them to the USB controller. -#define USB_USB_MUXING_USBPHY_AS_GPIO_RESET _u(0x0) -#define USB_USB_MUXING_USBPHY_AS_GPIO_BITS _u(0x00000010) -#define USB_USB_MUXING_USBPHY_AS_GPIO_MSB _u(4) -#define USB_USB_MUXING_USBPHY_AS_GPIO_LSB _u(4) -#define USB_USB_MUXING_USBPHY_AS_GPIO_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_USB_MUXING_SOFTCON -#define USB_USB_MUXING_SOFTCON_RESET _u(0x0) -#define USB_USB_MUXING_SOFTCON_BITS _u(0x00000008) -#define USB_USB_MUXING_SOFTCON_MSB _u(3) -#define USB_USB_MUXING_SOFTCON_LSB _u(3) -#define USB_USB_MUXING_SOFTCON_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_USB_MUXING_TO_DIGITAL_PAD -#define USB_USB_MUXING_TO_DIGITAL_PAD_RESET _u(0x0) -#define USB_USB_MUXING_TO_DIGITAL_PAD_BITS _u(0x00000004) -#define USB_USB_MUXING_TO_DIGITAL_PAD_MSB _u(2) -#define USB_USB_MUXING_TO_DIGITAL_PAD_LSB _u(2) -#define USB_USB_MUXING_TO_DIGITAL_PAD_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_USB_MUXING_TO_EXTPHY -#define USB_USB_MUXING_TO_EXTPHY_RESET _u(0x0) -#define USB_USB_MUXING_TO_EXTPHY_BITS _u(0x00000002) -#define USB_USB_MUXING_TO_EXTPHY_MSB _u(1) -#define USB_USB_MUXING_TO_EXTPHY_LSB _u(1) -#define USB_USB_MUXING_TO_EXTPHY_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_USB_MUXING_TO_PHY -#define USB_USB_MUXING_TO_PHY_RESET _u(0x1) -#define USB_USB_MUXING_TO_PHY_BITS _u(0x00000001) -#define USB_USB_MUXING_TO_PHY_MSB _u(0) -#define USB_USB_MUXING_TO_PHY_LSB _u(0) -#define USB_USB_MUXING_TO_PHY_ACCESS "RW" -// ============================================================================= -// Register : USB_USB_PWR -// Description : Overrides for the power signals in the event that the VBUS -// signals are not hooked up to GPIO. Set the value of the -// override and then the override enable to switch over to the -// override value. -#define USB_USB_PWR_OFFSET _u(0x00000078) -#define USB_USB_PWR_BITS _u(0x0000003f) -#define USB_USB_PWR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_USB_PWR_OVERCURR_DETECT_EN -#define USB_USB_PWR_OVERCURR_DETECT_EN_RESET _u(0x0) -#define USB_USB_PWR_OVERCURR_DETECT_EN_BITS _u(0x00000020) -#define USB_USB_PWR_OVERCURR_DETECT_EN_MSB _u(5) -#define USB_USB_PWR_OVERCURR_DETECT_EN_LSB _u(5) -#define USB_USB_PWR_OVERCURR_DETECT_EN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_USB_PWR_OVERCURR_DETECT -#define USB_USB_PWR_OVERCURR_DETECT_RESET _u(0x0) -#define USB_USB_PWR_OVERCURR_DETECT_BITS _u(0x00000010) -#define USB_USB_PWR_OVERCURR_DETECT_MSB _u(4) -#define USB_USB_PWR_OVERCURR_DETECT_LSB _u(4) -#define USB_USB_PWR_OVERCURR_DETECT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_USB_PWR_VBUS_DETECT_OVERRIDE_EN -#define USB_USB_PWR_VBUS_DETECT_OVERRIDE_EN_RESET _u(0x0) -#define USB_USB_PWR_VBUS_DETECT_OVERRIDE_EN_BITS _u(0x00000008) -#define USB_USB_PWR_VBUS_DETECT_OVERRIDE_EN_MSB _u(3) -#define USB_USB_PWR_VBUS_DETECT_OVERRIDE_EN_LSB _u(3) -#define USB_USB_PWR_VBUS_DETECT_OVERRIDE_EN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_USB_PWR_VBUS_DETECT -#define USB_USB_PWR_VBUS_DETECT_RESET _u(0x0) -#define USB_USB_PWR_VBUS_DETECT_BITS _u(0x00000004) -#define USB_USB_PWR_VBUS_DETECT_MSB _u(2) -#define USB_USB_PWR_VBUS_DETECT_LSB _u(2) -#define USB_USB_PWR_VBUS_DETECT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_USB_PWR_VBUS_EN_OVERRIDE_EN -#define USB_USB_PWR_VBUS_EN_OVERRIDE_EN_RESET _u(0x0) -#define USB_USB_PWR_VBUS_EN_OVERRIDE_EN_BITS _u(0x00000002) -#define USB_USB_PWR_VBUS_EN_OVERRIDE_EN_MSB _u(1) -#define USB_USB_PWR_VBUS_EN_OVERRIDE_EN_LSB _u(1) -#define USB_USB_PWR_VBUS_EN_OVERRIDE_EN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_USB_PWR_VBUS_EN -#define USB_USB_PWR_VBUS_EN_RESET _u(0x0) -#define USB_USB_PWR_VBUS_EN_BITS _u(0x00000001) -#define USB_USB_PWR_VBUS_EN_MSB _u(0) -#define USB_USB_PWR_VBUS_EN_LSB _u(0) -#define USB_USB_PWR_VBUS_EN_ACCESS "RW" -// ============================================================================= -// Register : USB_USBPHY_DIRECT -// Description : This register allows for direct control of the USB phy. Use in -// conjunction with usbphy_direct_override register to enable each -// override bit. -#define USB_USBPHY_DIRECT_OFFSET _u(0x0000007c) -#define USB_USBPHY_DIRECT_BITS _u(0x03ffff77) -#define USB_USBPHY_DIRECT_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_USBPHY_DIRECT_RX_DM_OVERRIDE -// Description : Override rx_dm value into controller -#define USB_USBPHY_DIRECT_RX_DM_OVERRIDE_RESET _u(0x0) -#define USB_USBPHY_DIRECT_RX_DM_OVERRIDE_BITS _u(0x02000000) -#define USB_USBPHY_DIRECT_RX_DM_OVERRIDE_MSB _u(25) -#define USB_USBPHY_DIRECT_RX_DM_OVERRIDE_LSB _u(25) -#define USB_USBPHY_DIRECT_RX_DM_OVERRIDE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_USBPHY_DIRECT_RX_DP_OVERRIDE -// Description : Override rx_dp value into controller -#define USB_USBPHY_DIRECT_RX_DP_OVERRIDE_RESET _u(0x0) -#define USB_USBPHY_DIRECT_RX_DP_OVERRIDE_BITS _u(0x01000000) -#define USB_USBPHY_DIRECT_RX_DP_OVERRIDE_MSB _u(24) -#define USB_USBPHY_DIRECT_RX_DP_OVERRIDE_LSB _u(24) -#define USB_USBPHY_DIRECT_RX_DP_OVERRIDE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_USBPHY_DIRECT_RX_DD_OVERRIDE -// Description : Override rx_dd value into controller -#define USB_USBPHY_DIRECT_RX_DD_OVERRIDE_RESET _u(0x0) -#define USB_USBPHY_DIRECT_RX_DD_OVERRIDE_BITS _u(0x00800000) -#define USB_USBPHY_DIRECT_RX_DD_OVERRIDE_MSB _u(23) -#define USB_USBPHY_DIRECT_RX_DD_OVERRIDE_LSB _u(23) -#define USB_USBPHY_DIRECT_RX_DD_OVERRIDE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_USBPHY_DIRECT_DM_OVV -// Description : DM over voltage -#define USB_USBPHY_DIRECT_DM_OVV_RESET _u(0x0) -#define USB_USBPHY_DIRECT_DM_OVV_BITS _u(0x00400000) -#define USB_USBPHY_DIRECT_DM_OVV_MSB _u(22) -#define USB_USBPHY_DIRECT_DM_OVV_LSB _u(22) -#define USB_USBPHY_DIRECT_DM_OVV_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_USBPHY_DIRECT_DP_OVV -// Description : DP over voltage -#define USB_USBPHY_DIRECT_DP_OVV_RESET _u(0x0) -#define USB_USBPHY_DIRECT_DP_OVV_BITS _u(0x00200000) -#define USB_USBPHY_DIRECT_DP_OVV_MSB _u(21) -#define USB_USBPHY_DIRECT_DP_OVV_LSB _u(21) -#define USB_USBPHY_DIRECT_DP_OVV_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_USBPHY_DIRECT_DM_OVCN -// Description : DM overcurrent -#define USB_USBPHY_DIRECT_DM_OVCN_RESET _u(0x0) -#define USB_USBPHY_DIRECT_DM_OVCN_BITS _u(0x00100000) -#define USB_USBPHY_DIRECT_DM_OVCN_MSB _u(20) -#define USB_USBPHY_DIRECT_DM_OVCN_LSB _u(20) -#define USB_USBPHY_DIRECT_DM_OVCN_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_USBPHY_DIRECT_DP_OVCN -// Description : DP overcurrent -#define USB_USBPHY_DIRECT_DP_OVCN_RESET _u(0x0) -#define USB_USBPHY_DIRECT_DP_OVCN_BITS _u(0x00080000) -#define USB_USBPHY_DIRECT_DP_OVCN_MSB _u(19) -#define USB_USBPHY_DIRECT_DP_OVCN_LSB _u(19) -#define USB_USBPHY_DIRECT_DP_OVCN_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_USBPHY_DIRECT_RX_DM -// Description : DPM pin state -#define USB_USBPHY_DIRECT_RX_DM_RESET _u(0x0) -#define USB_USBPHY_DIRECT_RX_DM_BITS _u(0x00040000) -#define USB_USBPHY_DIRECT_RX_DM_MSB _u(18) -#define USB_USBPHY_DIRECT_RX_DM_LSB _u(18) -#define USB_USBPHY_DIRECT_RX_DM_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_USBPHY_DIRECT_RX_DP -// Description : DPP pin state -#define USB_USBPHY_DIRECT_RX_DP_RESET _u(0x0) -#define USB_USBPHY_DIRECT_RX_DP_BITS _u(0x00020000) -#define USB_USBPHY_DIRECT_RX_DP_MSB _u(17) -#define USB_USBPHY_DIRECT_RX_DP_LSB _u(17) -#define USB_USBPHY_DIRECT_RX_DP_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_USBPHY_DIRECT_RX_DD -// Description : Differential RX -#define USB_USBPHY_DIRECT_RX_DD_RESET _u(0x0) -#define USB_USBPHY_DIRECT_RX_DD_BITS _u(0x00010000) -#define USB_USBPHY_DIRECT_RX_DD_MSB _u(16) -#define USB_USBPHY_DIRECT_RX_DD_LSB _u(16) -#define USB_USBPHY_DIRECT_RX_DD_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_USBPHY_DIRECT_TX_DIFFMODE -// Description : TX_DIFFMODE=0: Single ended mode -// TX_DIFFMODE=1: Differential drive mode (TX_DM, TX_DM_OE -// ignored) -#define USB_USBPHY_DIRECT_TX_DIFFMODE_RESET _u(0x0) -#define USB_USBPHY_DIRECT_TX_DIFFMODE_BITS _u(0x00008000) -#define USB_USBPHY_DIRECT_TX_DIFFMODE_MSB _u(15) -#define USB_USBPHY_DIRECT_TX_DIFFMODE_LSB _u(15) -#define USB_USBPHY_DIRECT_TX_DIFFMODE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_USBPHY_DIRECT_TX_FSSLEW -// Description : TX_FSSLEW=0: Low speed slew rate -// TX_FSSLEW=1: Full speed slew rate -#define USB_USBPHY_DIRECT_TX_FSSLEW_RESET _u(0x0) -#define USB_USBPHY_DIRECT_TX_FSSLEW_BITS _u(0x00004000) -#define USB_USBPHY_DIRECT_TX_FSSLEW_MSB _u(14) -#define USB_USBPHY_DIRECT_TX_FSSLEW_LSB _u(14) -#define USB_USBPHY_DIRECT_TX_FSSLEW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_USBPHY_DIRECT_TX_PD -// Description : TX power down override (if override enable is set). 1 = powered -// down. -#define USB_USBPHY_DIRECT_TX_PD_RESET _u(0x0) -#define USB_USBPHY_DIRECT_TX_PD_BITS _u(0x00002000) -#define USB_USBPHY_DIRECT_TX_PD_MSB _u(13) -#define USB_USBPHY_DIRECT_TX_PD_LSB _u(13) -#define USB_USBPHY_DIRECT_TX_PD_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_USBPHY_DIRECT_RX_PD -// Description : RX power down override (if override enable is set). 1 = powered -// down. -#define USB_USBPHY_DIRECT_RX_PD_RESET _u(0x0) -#define USB_USBPHY_DIRECT_RX_PD_BITS _u(0x00001000) -#define USB_USBPHY_DIRECT_RX_PD_MSB _u(12) -#define USB_USBPHY_DIRECT_RX_PD_LSB _u(12) -#define USB_USBPHY_DIRECT_RX_PD_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_USBPHY_DIRECT_TX_DM -// Description : Output data. TX_DIFFMODE=1, Ignored -// TX_DIFFMODE=0, Drives DPM only. TX_DM_OE=1 to enable drive. -// DPM=TX_DM -#define USB_USBPHY_DIRECT_TX_DM_RESET _u(0x0) -#define USB_USBPHY_DIRECT_TX_DM_BITS _u(0x00000800) -#define USB_USBPHY_DIRECT_TX_DM_MSB _u(11) -#define USB_USBPHY_DIRECT_TX_DM_LSB _u(11) -#define USB_USBPHY_DIRECT_TX_DM_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_USBPHY_DIRECT_TX_DP -// Description : Output data. If TX_DIFFMODE=1, Drives DPP/DPM diff pair. -// TX_DP_OE=1 to enable drive. DPP=TX_DP, DPM=~TX_DP -// If TX_DIFFMODE=0, Drives DPP only. TX_DP_OE=1 to enable drive. -// DPP=TX_DP -#define USB_USBPHY_DIRECT_TX_DP_RESET _u(0x0) -#define USB_USBPHY_DIRECT_TX_DP_BITS _u(0x00000400) -#define USB_USBPHY_DIRECT_TX_DP_MSB _u(10) -#define USB_USBPHY_DIRECT_TX_DP_LSB _u(10) -#define USB_USBPHY_DIRECT_TX_DP_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_USBPHY_DIRECT_TX_DM_OE -// Description : Output enable. If TX_DIFFMODE=1, Ignored. -// If TX_DIFFMODE=0, OE for DPM only. 0 - DPM in Hi-Z state; 1 - -// DPM driving -#define USB_USBPHY_DIRECT_TX_DM_OE_RESET _u(0x0) -#define USB_USBPHY_DIRECT_TX_DM_OE_BITS _u(0x00000200) -#define USB_USBPHY_DIRECT_TX_DM_OE_MSB _u(9) -#define USB_USBPHY_DIRECT_TX_DM_OE_LSB _u(9) -#define USB_USBPHY_DIRECT_TX_DM_OE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_USBPHY_DIRECT_TX_DP_OE -// Description : Output enable. If TX_DIFFMODE=1, OE for DPP/DPM diff pair. 0 - -// DPP/DPM in Hi-Z state; 1 - DPP/DPM driving -// If TX_DIFFMODE=0, OE for DPP only. 0 - DPP in Hi-Z state; 1 - -// DPP driving -#define USB_USBPHY_DIRECT_TX_DP_OE_RESET _u(0x0) -#define USB_USBPHY_DIRECT_TX_DP_OE_BITS _u(0x00000100) -#define USB_USBPHY_DIRECT_TX_DP_OE_MSB _u(8) -#define USB_USBPHY_DIRECT_TX_DP_OE_LSB _u(8) -#define USB_USBPHY_DIRECT_TX_DP_OE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_USBPHY_DIRECT_DM_PULLDN_EN -// Description : DM pull down enable -#define USB_USBPHY_DIRECT_DM_PULLDN_EN_RESET _u(0x0) -#define USB_USBPHY_DIRECT_DM_PULLDN_EN_BITS _u(0x00000040) -#define USB_USBPHY_DIRECT_DM_PULLDN_EN_MSB _u(6) -#define USB_USBPHY_DIRECT_DM_PULLDN_EN_LSB _u(6) -#define USB_USBPHY_DIRECT_DM_PULLDN_EN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_USBPHY_DIRECT_DM_PULLUP_EN -// Description : DM pull up enable -#define USB_USBPHY_DIRECT_DM_PULLUP_EN_RESET _u(0x0) -#define USB_USBPHY_DIRECT_DM_PULLUP_EN_BITS _u(0x00000020) -#define USB_USBPHY_DIRECT_DM_PULLUP_EN_MSB _u(5) -#define USB_USBPHY_DIRECT_DM_PULLUP_EN_LSB _u(5) -#define USB_USBPHY_DIRECT_DM_PULLUP_EN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_USBPHY_DIRECT_DM_PULLUP_HISEL -// Description : Enable the second DM pull up resistor. 0 - Pull = Rpu2; 1 - -// Pull = Rpu1 + Rpu2 -#define USB_USBPHY_DIRECT_DM_PULLUP_HISEL_RESET _u(0x0) -#define USB_USBPHY_DIRECT_DM_PULLUP_HISEL_BITS _u(0x00000010) -#define USB_USBPHY_DIRECT_DM_PULLUP_HISEL_MSB _u(4) -#define USB_USBPHY_DIRECT_DM_PULLUP_HISEL_LSB _u(4) -#define USB_USBPHY_DIRECT_DM_PULLUP_HISEL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_USBPHY_DIRECT_DP_PULLDN_EN -// Description : DP pull down enable -#define USB_USBPHY_DIRECT_DP_PULLDN_EN_RESET _u(0x0) -#define USB_USBPHY_DIRECT_DP_PULLDN_EN_BITS _u(0x00000004) -#define USB_USBPHY_DIRECT_DP_PULLDN_EN_MSB _u(2) -#define USB_USBPHY_DIRECT_DP_PULLDN_EN_LSB _u(2) -#define USB_USBPHY_DIRECT_DP_PULLDN_EN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_USBPHY_DIRECT_DP_PULLUP_EN -// Description : DP pull up enable -#define USB_USBPHY_DIRECT_DP_PULLUP_EN_RESET _u(0x0) -#define USB_USBPHY_DIRECT_DP_PULLUP_EN_BITS _u(0x00000002) -#define USB_USBPHY_DIRECT_DP_PULLUP_EN_MSB _u(1) -#define USB_USBPHY_DIRECT_DP_PULLUP_EN_LSB _u(1) -#define USB_USBPHY_DIRECT_DP_PULLUP_EN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_USBPHY_DIRECT_DP_PULLUP_HISEL -// Description : Enable the second DP pull up resistor. 0 - Pull = Rpu2; 1 - -// Pull = Rpu1 + Rpu2 -#define USB_USBPHY_DIRECT_DP_PULLUP_HISEL_RESET _u(0x0) -#define USB_USBPHY_DIRECT_DP_PULLUP_HISEL_BITS _u(0x00000001) -#define USB_USBPHY_DIRECT_DP_PULLUP_HISEL_MSB _u(0) -#define USB_USBPHY_DIRECT_DP_PULLUP_HISEL_LSB _u(0) -#define USB_USBPHY_DIRECT_DP_PULLUP_HISEL_ACCESS "RW" -// ============================================================================= -// Register : USB_USBPHY_DIRECT_OVERRIDE -// Description : Override enable for each control in usbphy_direct -#define USB_USBPHY_DIRECT_OVERRIDE_OFFSET _u(0x00000080) -#define USB_USBPHY_DIRECT_OVERRIDE_BITS _u(0x00079fff) -#define USB_USBPHY_DIRECT_OVERRIDE_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_USBPHY_DIRECT_OVERRIDE_RX_DM_OVERRIDE_EN -#define USB_USBPHY_DIRECT_OVERRIDE_RX_DM_OVERRIDE_EN_RESET _u(0x0) -#define USB_USBPHY_DIRECT_OVERRIDE_RX_DM_OVERRIDE_EN_BITS _u(0x00040000) -#define USB_USBPHY_DIRECT_OVERRIDE_RX_DM_OVERRIDE_EN_MSB _u(18) -#define USB_USBPHY_DIRECT_OVERRIDE_RX_DM_OVERRIDE_EN_LSB _u(18) -#define USB_USBPHY_DIRECT_OVERRIDE_RX_DM_OVERRIDE_EN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_USBPHY_DIRECT_OVERRIDE_RX_DP_OVERRIDE_EN -#define USB_USBPHY_DIRECT_OVERRIDE_RX_DP_OVERRIDE_EN_RESET _u(0x0) -#define USB_USBPHY_DIRECT_OVERRIDE_RX_DP_OVERRIDE_EN_BITS _u(0x00020000) -#define USB_USBPHY_DIRECT_OVERRIDE_RX_DP_OVERRIDE_EN_MSB _u(17) -#define USB_USBPHY_DIRECT_OVERRIDE_RX_DP_OVERRIDE_EN_LSB _u(17) -#define USB_USBPHY_DIRECT_OVERRIDE_RX_DP_OVERRIDE_EN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_USBPHY_DIRECT_OVERRIDE_RX_DD_OVERRIDE_EN -#define USB_USBPHY_DIRECT_OVERRIDE_RX_DD_OVERRIDE_EN_RESET _u(0x0) -#define USB_USBPHY_DIRECT_OVERRIDE_RX_DD_OVERRIDE_EN_BITS _u(0x00010000) -#define USB_USBPHY_DIRECT_OVERRIDE_RX_DD_OVERRIDE_EN_MSB _u(16) -#define USB_USBPHY_DIRECT_OVERRIDE_RX_DD_OVERRIDE_EN_LSB _u(16) -#define USB_USBPHY_DIRECT_OVERRIDE_RX_DD_OVERRIDE_EN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_USBPHY_DIRECT_OVERRIDE_TX_DIFFMODE_OVERRIDE_EN -#define USB_USBPHY_DIRECT_OVERRIDE_TX_DIFFMODE_OVERRIDE_EN_RESET _u(0x0) -#define USB_USBPHY_DIRECT_OVERRIDE_TX_DIFFMODE_OVERRIDE_EN_BITS _u(0x00008000) -#define USB_USBPHY_DIRECT_OVERRIDE_TX_DIFFMODE_OVERRIDE_EN_MSB _u(15) -#define USB_USBPHY_DIRECT_OVERRIDE_TX_DIFFMODE_OVERRIDE_EN_LSB _u(15) -#define USB_USBPHY_DIRECT_OVERRIDE_TX_DIFFMODE_OVERRIDE_EN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_OVERRIDE_EN -#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_OVERRIDE_EN_RESET _u(0x0) -#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_OVERRIDE_EN_BITS _u(0x00001000) -#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_OVERRIDE_EN_MSB _u(12) -#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_OVERRIDE_EN_LSB _u(12) -#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_OVERRIDE_EN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_USBPHY_DIRECT_OVERRIDE_TX_FSSLEW_OVERRIDE_EN -#define USB_USBPHY_DIRECT_OVERRIDE_TX_FSSLEW_OVERRIDE_EN_RESET _u(0x0) -#define USB_USBPHY_DIRECT_OVERRIDE_TX_FSSLEW_OVERRIDE_EN_BITS _u(0x00000800) -#define USB_USBPHY_DIRECT_OVERRIDE_TX_FSSLEW_OVERRIDE_EN_MSB _u(11) -#define USB_USBPHY_DIRECT_OVERRIDE_TX_FSSLEW_OVERRIDE_EN_LSB _u(11) -#define USB_USBPHY_DIRECT_OVERRIDE_TX_FSSLEW_OVERRIDE_EN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_USBPHY_DIRECT_OVERRIDE_TX_PD_OVERRIDE_EN -#define USB_USBPHY_DIRECT_OVERRIDE_TX_PD_OVERRIDE_EN_RESET _u(0x0) -#define USB_USBPHY_DIRECT_OVERRIDE_TX_PD_OVERRIDE_EN_BITS _u(0x00000400) -#define USB_USBPHY_DIRECT_OVERRIDE_TX_PD_OVERRIDE_EN_MSB _u(10) -#define USB_USBPHY_DIRECT_OVERRIDE_TX_PD_OVERRIDE_EN_LSB _u(10) -#define USB_USBPHY_DIRECT_OVERRIDE_TX_PD_OVERRIDE_EN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_USBPHY_DIRECT_OVERRIDE_RX_PD_OVERRIDE_EN -#define USB_USBPHY_DIRECT_OVERRIDE_RX_PD_OVERRIDE_EN_RESET _u(0x0) -#define USB_USBPHY_DIRECT_OVERRIDE_RX_PD_OVERRIDE_EN_BITS _u(0x00000200) -#define USB_USBPHY_DIRECT_OVERRIDE_RX_PD_OVERRIDE_EN_MSB _u(9) -#define USB_USBPHY_DIRECT_OVERRIDE_RX_PD_OVERRIDE_EN_LSB _u(9) -#define USB_USBPHY_DIRECT_OVERRIDE_RX_PD_OVERRIDE_EN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OVERRIDE_EN -#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OVERRIDE_EN_RESET _u(0x0) -#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OVERRIDE_EN_BITS _u(0x00000100) -#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OVERRIDE_EN_MSB _u(8) -#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OVERRIDE_EN_LSB _u(8) -#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OVERRIDE_EN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OVERRIDE_EN -#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OVERRIDE_EN_RESET _u(0x0) -#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OVERRIDE_EN_BITS _u(0x00000080) -#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OVERRIDE_EN_MSB _u(7) -#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OVERRIDE_EN_LSB _u(7) -#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OVERRIDE_EN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OE_OVERRIDE_EN -#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OE_OVERRIDE_EN_RESET _u(0x0) -#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OE_OVERRIDE_EN_BITS _u(0x00000040) -#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OE_OVERRIDE_EN_MSB _u(6) -#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OE_OVERRIDE_EN_LSB _u(6) -#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OE_OVERRIDE_EN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OE_OVERRIDE_EN -#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OE_OVERRIDE_EN_RESET _u(0x0) -#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OE_OVERRIDE_EN_BITS _u(0x00000020) -#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OE_OVERRIDE_EN_MSB _u(5) -#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OE_OVERRIDE_EN_LSB _u(5) -#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OE_OVERRIDE_EN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_USBPHY_DIRECT_OVERRIDE_DM_PULLDN_EN_OVERRIDE_EN -#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLDN_EN_OVERRIDE_EN_RESET _u(0x0) -#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLDN_EN_OVERRIDE_EN_BITS _u(0x00000010) -#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLDN_EN_OVERRIDE_EN_MSB _u(4) -#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLDN_EN_OVERRIDE_EN_LSB _u(4) -#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLDN_EN_OVERRIDE_EN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_USBPHY_DIRECT_OVERRIDE_DP_PULLDN_EN_OVERRIDE_EN -#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLDN_EN_OVERRIDE_EN_RESET _u(0x0) -#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLDN_EN_OVERRIDE_EN_BITS _u(0x00000008) -#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLDN_EN_OVERRIDE_EN_MSB _u(3) -#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLDN_EN_OVERRIDE_EN_LSB _u(3) -#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLDN_EN_OVERRIDE_EN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_EN_OVERRIDE_EN -#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_EN_OVERRIDE_EN_RESET _u(0x0) -#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_EN_OVERRIDE_EN_BITS _u(0x00000004) -#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_EN_OVERRIDE_EN_MSB _u(2) -#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_EN_OVERRIDE_EN_LSB _u(2) -#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_EN_OVERRIDE_EN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_HISEL_OVERRIDE_EN -#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_HISEL_OVERRIDE_EN_RESET _u(0x0) -#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_HISEL_OVERRIDE_EN_BITS _u(0x00000002) -#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_HISEL_OVERRIDE_EN_MSB _u(1) -#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_HISEL_OVERRIDE_EN_LSB _u(1) -#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_HISEL_OVERRIDE_EN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_HISEL_OVERRIDE_EN -#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_HISEL_OVERRIDE_EN_RESET _u(0x0) -#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_HISEL_OVERRIDE_EN_BITS _u(0x00000001) -#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_HISEL_OVERRIDE_EN_MSB _u(0) -#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_HISEL_OVERRIDE_EN_LSB _u(0) -#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_HISEL_OVERRIDE_EN_ACCESS "RW" -// ============================================================================= -// Register : USB_USBPHY_TRIM -// Description : Used to adjust trim values of USB phy pull down resistors. -#define USB_USBPHY_TRIM_OFFSET _u(0x00000084) -#define USB_USBPHY_TRIM_BITS _u(0x00001f1f) -#define USB_USBPHY_TRIM_RESET _u(0x00001f1f) -// ----------------------------------------------------------------------------- -// Field : USB_USBPHY_TRIM_DM_PULLDN_TRIM -// Description : Value to drive to USB PHY -// DM pulldown resistor trim control -// Experimental data suggests that the reset value will work, but -// this register allows adjustment if required -#define USB_USBPHY_TRIM_DM_PULLDN_TRIM_RESET _u(0x1f) -#define USB_USBPHY_TRIM_DM_PULLDN_TRIM_BITS _u(0x00001f00) -#define USB_USBPHY_TRIM_DM_PULLDN_TRIM_MSB _u(12) -#define USB_USBPHY_TRIM_DM_PULLDN_TRIM_LSB _u(8) -#define USB_USBPHY_TRIM_DM_PULLDN_TRIM_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_USBPHY_TRIM_DP_PULLDN_TRIM -// Description : Value to drive to USB PHY -// DP pulldown resistor trim control -// Experimental data suggests that the reset value will work, but -// this register allows adjustment if required -#define USB_USBPHY_TRIM_DP_PULLDN_TRIM_RESET _u(0x1f) -#define USB_USBPHY_TRIM_DP_PULLDN_TRIM_BITS _u(0x0000001f) -#define USB_USBPHY_TRIM_DP_PULLDN_TRIM_MSB _u(4) -#define USB_USBPHY_TRIM_DP_PULLDN_TRIM_LSB _u(0) -#define USB_USBPHY_TRIM_DP_PULLDN_TRIM_ACCESS "RW" -// ============================================================================= -// Register : USB_LINESTATE_TUNING -// Description : Used for debug only. -#define USB_LINESTATE_TUNING_OFFSET _u(0x00000088) -#define USB_LINESTATE_TUNING_BITS _u(0x00000fff) -#define USB_LINESTATE_TUNING_RESET _u(0x000000f8) -// ----------------------------------------------------------------------------- -// Field : USB_LINESTATE_TUNING_SPARE_FIX -#define USB_LINESTATE_TUNING_SPARE_FIX_RESET _u(0x0) -#define USB_LINESTATE_TUNING_SPARE_FIX_BITS _u(0x00000f00) -#define USB_LINESTATE_TUNING_SPARE_FIX_MSB _u(11) -#define USB_LINESTATE_TUNING_SPARE_FIX_LSB _u(8) -#define USB_LINESTATE_TUNING_SPARE_FIX_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_LINESTATE_TUNING_DEV_LS_WAKE_FIX -// Description : Device - exit suspend on any non-idle signalling, not qualified -// with a 1ms timer -#define USB_LINESTATE_TUNING_DEV_LS_WAKE_FIX_RESET _u(0x1) -#define USB_LINESTATE_TUNING_DEV_LS_WAKE_FIX_BITS _u(0x00000080) -#define USB_LINESTATE_TUNING_DEV_LS_WAKE_FIX_MSB _u(7) -#define USB_LINESTATE_TUNING_DEV_LS_WAKE_FIX_LSB _u(7) -#define USB_LINESTATE_TUNING_DEV_LS_WAKE_FIX_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_LINESTATE_TUNING_DEV_RX_ERR_QUIESCE -// Description : Device - suppress repeated errors until the device FSM is next -// in the process of decoding an inbound packet. -#define USB_LINESTATE_TUNING_DEV_RX_ERR_QUIESCE_RESET _u(0x1) -#define USB_LINESTATE_TUNING_DEV_RX_ERR_QUIESCE_BITS _u(0x00000040) -#define USB_LINESTATE_TUNING_DEV_RX_ERR_QUIESCE_MSB _u(6) -#define USB_LINESTATE_TUNING_DEV_RX_ERR_QUIESCE_LSB _u(6) -#define USB_LINESTATE_TUNING_DEV_RX_ERR_QUIESCE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_LINESTATE_TUNING_SIE_RX_CHATTER_SE0_FIX -// Description : RX - when recovering from line chatter or bitstuff errors, -// treat SE0 as the end of chatter as well as -// 8 consecutive idle bits. -#define USB_LINESTATE_TUNING_SIE_RX_CHATTER_SE0_FIX_RESET _u(0x1) -#define USB_LINESTATE_TUNING_SIE_RX_CHATTER_SE0_FIX_BITS _u(0x00000020) -#define USB_LINESTATE_TUNING_SIE_RX_CHATTER_SE0_FIX_MSB _u(5) -#define USB_LINESTATE_TUNING_SIE_RX_CHATTER_SE0_FIX_LSB _u(5) -#define USB_LINESTATE_TUNING_SIE_RX_CHATTER_SE0_FIX_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_LINESTATE_TUNING_SIE_RX_BITSTUFF_FIX -// Description : RX - when a bitstuff error is signalled by rx_dasm, -// unconditionally terminate RX decode to -// avoid a hang during certain packet phases. -#define USB_LINESTATE_TUNING_SIE_RX_BITSTUFF_FIX_RESET _u(0x1) -#define USB_LINESTATE_TUNING_SIE_RX_BITSTUFF_FIX_BITS _u(0x00000010) -#define USB_LINESTATE_TUNING_SIE_RX_BITSTUFF_FIX_MSB _u(4) -#define USB_LINESTATE_TUNING_SIE_RX_BITSTUFF_FIX_LSB _u(4) -#define USB_LINESTATE_TUNING_SIE_RX_BITSTUFF_FIX_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_LINESTATE_TUNING_DEV_BUFF_CONTROL_DOUBLE_READ_FIX -// Description : Device - the controller FSM performs two reads of the buffer -// status memory address to -// avoid sampling metastable data. An enabled buffer is only used -// if both reads match. -#define USB_LINESTATE_TUNING_DEV_BUFF_CONTROL_DOUBLE_READ_FIX_RESET _u(0x1) -#define USB_LINESTATE_TUNING_DEV_BUFF_CONTROL_DOUBLE_READ_FIX_BITS _u(0x00000008) -#define USB_LINESTATE_TUNING_DEV_BUFF_CONTROL_DOUBLE_READ_FIX_MSB _u(3) -#define USB_LINESTATE_TUNING_DEV_BUFF_CONTROL_DOUBLE_READ_FIX_LSB _u(3) -#define USB_LINESTATE_TUNING_DEV_BUFF_CONTROL_DOUBLE_READ_FIX_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_LINESTATE_TUNING_MULTI_HUB_FIX -// Description : Host - increase inter-packet and turnaround timeouts to -// accommodate worst-case hub delays. -#define USB_LINESTATE_TUNING_MULTI_HUB_FIX_RESET _u(0x0) -#define USB_LINESTATE_TUNING_MULTI_HUB_FIX_BITS _u(0x00000004) -#define USB_LINESTATE_TUNING_MULTI_HUB_FIX_MSB _u(2) -#define USB_LINESTATE_TUNING_MULTI_HUB_FIX_LSB _u(2) -#define USB_LINESTATE_TUNING_MULTI_HUB_FIX_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_LINESTATE_TUNING_LINESTATE_DELAY -// Description : Device/Host - add an extra 1-bit debounce of linestate -// sampling. -#define USB_LINESTATE_TUNING_LINESTATE_DELAY_RESET _u(0x0) -#define USB_LINESTATE_TUNING_LINESTATE_DELAY_BITS _u(0x00000002) -#define USB_LINESTATE_TUNING_LINESTATE_DELAY_MSB _u(1) -#define USB_LINESTATE_TUNING_LINESTATE_DELAY_LSB _u(1) -#define USB_LINESTATE_TUNING_LINESTATE_DELAY_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_LINESTATE_TUNING_RCV_DELAY -// Description : Device - register the received data to account for hub bit -// dribble before EOP. Only affects certain hubs. -#define USB_LINESTATE_TUNING_RCV_DELAY_RESET _u(0x0) -#define USB_LINESTATE_TUNING_RCV_DELAY_BITS _u(0x00000001) -#define USB_LINESTATE_TUNING_RCV_DELAY_MSB _u(0) -#define USB_LINESTATE_TUNING_RCV_DELAY_LSB _u(0) -#define USB_LINESTATE_TUNING_RCV_DELAY_ACCESS "RW" -// ============================================================================= -// Register : USB_INTR -// Description : Raw Interrupts -#define USB_INTR_OFFSET _u(0x0000008c) -#define USB_INTR_BITS _u(0x00ffffff) -#define USB_INTR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_INTR_EPX_STOPPED_ON_NAK -// Description : Source: NAK_POLL.EPX_STOPPED_ON_NAK -#define USB_INTR_EPX_STOPPED_ON_NAK_RESET _u(0x0) -#define USB_INTR_EPX_STOPPED_ON_NAK_BITS _u(0x00800000) -#define USB_INTR_EPX_STOPPED_ON_NAK_MSB _u(23) -#define USB_INTR_EPX_STOPPED_ON_NAK_LSB _u(23) -#define USB_INTR_EPX_STOPPED_ON_NAK_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_INTR_DEV_SM_WATCHDOG_FIRED -// Description : Source: DEV_SM_WATCHDOG.FIRED -#define USB_INTR_DEV_SM_WATCHDOG_FIRED_RESET _u(0x0) -#define USB_INTR_DEV_SM_WATCHDOG_FIRED_BITS _u(0x00400000) -#define USB_INTR_DEV_SM_WATCHDOG_FIRED_MSB _u(22) -#define USB_INTR_DEV_SM_WATCHDOG_FIRED_LSB _u(22) -#define USB_INTR_DEV_SM_WATCHDOG_FIRED_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_INTR_ENDPOINT_ERROR -// Description : Source: SIE_STATUS.ENDPOINT_ERROR -#define USB_INTR_ENDPOINT_ERROR_RESET _u(0x0) -#define USB_INTR_ENDPOINT_ERROR_BITS _u(0x00200000) -#define USB_INTR_ENDPOINT_ERROR_MSB _u(21) -#define USB_INTR_ENDPOINT_ERROR_LSB _u(21) -#define USB_INTR_ENDPOINT_ERROR_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_INTR_RX_SHORT_PACKET -// Description : Source: SIE_STATUS.RX_SHORT_PACKET -#define USB_INTR_RX_SHORT_PACKET_RESET _u(0x0) -#define USB_INTR_RX_SHORT_PACKET_BITS _u(0x00100000) -#define USB_INTR_RX_SHORT_PACKET_MSB _u(20) -#define USB_INTR_RX_SHORT_PACKET_LSB _u(20) -#define USB_INTR_RX_SHORT_PACKET_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_INTR_EP_STALL_NAK -// Description : Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by -// clearing all bits in EP_STATUS_STALL_NAK. -#define USB_INTR_EP_STALL_NAK_RESET _u(0x0) -#define USB_INTR_EP_STALL_NAK_BITS _u(0x00080000) -#define USB_INTR_EP_STALL_NAK_MSB _u(19) -#define USB_INTR_EP_STALL_NAK_LSB _u(19) -#define USB_INTR_EP_STALL_NAK_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_INTR_ABORT_DONE -// Description : Raised when any bit in ABORT_DONE is set. Clear by clearing all -// bits in ABORT_DONE. -#define USB_INTR_ABORT_DONE_RESET _u(0x0) -#define USB_INTR_ABORT_DONE_BITS _u(0x00040000) -#define USB_INTR_ABORT_DONE_MSB _u(18) -#define USB_INTR_ABORT_DONE_LSB _u(18) -#define USB_INTR_ABORT_DONE_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_INTR_DEV_SOF -// Description : Set every time the device receives a SOF (Start of Frame) -// packet. Cleared by reading SOF_RD -#define USB_INTR_DEV_SOF_RESET _u(0x0) -#define USB_INTR_DEV_SOF_BITS _u(0x00020000) -#define USB_INTR_DEV_SOF_MSB _u(17) -#define USB_INTR_DEV_SOF_LSB _u(17) -#define USB_INTR_DEV_SOF_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_INTR_SETUP_REQ -// Description : Device. Source: SIE_STATUS.SETUP_REC -#define USB_INTR_SETUP_REQ_RESET _u(0x0) -#define USB_INTR_SETUP_REQ_BITS _u(0x00010000) -#define USB_INTR_SETUP_REQ_MSB _u(16) -#define USB_INTR_SETUP_REQ_LSB _u(16) -#define USB_INTR_SETUP_REQ_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_INTR_DEV_RESUME_FROM_HOST -// Description : Set when the device receives a resume from the host. Cleared by -// writing to SIE_STATUS.RESUME -#define USB_INTR_DEV_RESUME_FROM_HOST_RESET _u(0x0) -#define USB_INTR_DEV_RESUME_FROM_HOST_BITS _u(0x00008000) -#define USB_INTR_DEV_RESUME_FROM_HOST_MSB _u(15) -#define USB_INTR_DEV_RESUME_FROM_HOST_LSB _u(15) -#define USB_INTR_DEV_RESUME_FROM_HOST_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_INTR_DEV_SUSPEND -// Description : Set when the device suspend state changes. Cleared by writing -// to SIE_STATUS.SUSPENDED -#define USB_INTR_DEV_SUSPEND_RESET _u(0x0) -#define USB_INTR_DEV_SUSPEND_BITS _u(0x00004000) -#define USB_INTR_DEV_SUSPEND_MSB _u(14) -#define USB_INTR_DEV_SUSPEND_LSB _u(14) -#define USB_INTR_DEV_SUSPEND_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_INTR_DEV_CONN_DIS -// Description : Set when the device connection state changes. Cleared by -// writing to SIE_STATUS.CONNECTED -#define USB_INTR_DEV_CONN_DIS_RESET _u(0x0) -#define USB_INTR_DEV_CONN_DIS_BITS _u(0x00002000) -#define USB_INTR_DEV_CONN_DIS_MSB _u(13) -#define USB_INTR_DEV_CONN_DIS_LSB _u(13) -#define USB_INTR_DEV_CONN_DIS_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_INTR_BUS_RESET -// Description : Source: SIE_STATUS.BUS_RESET -#define USB_INTR_BUS_RESET_RESET _u(0x0) -#define USB_INTR_BUS_RESET_BITS _u(0x00001000) -#define USB_INTR_BUS_RESET_MSB _u(12) -#define USB_INTR_BUS_RESET_LSB _u(12) -#define USB_INTR_BUS_RESET_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_INTR_VBUS_DETECT -// Description : Source: SIE_STATUS.VBUS_DETECTED -#define USB_INTR_VBUS_DETECT_RESET _u(0x0) -#define USB_INTR_VBUS_DETECT_BITS _u(0x00000800) -#define USB_INTR_VBUS_DETECT_MSB _u(11) -#define USB_INTR_VBUS_DETECT_LSB _u(11) -#define USB_INTR_VBUS_DETECT_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_INTR_STALL -// Description : Source: SIE_STATUS.STALL_REC -#define USB_INTR_STALL_RESET _u(0x0) -#define USB_INTR_STALL_BITS _u(0x00000400) -#define USB_INTR_STALL_MSB _u(10) -#define USB_INTR_STALL_LSB _u(10) -#define USB_INTR_STALL_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_INTR_ERROR_CRC -// Description : Source: SIE_STATUS.CRC_ERROR -#define USB_INTR_ERROR_CRC_RESET _u(0x0) -#define USB_INTR_ERROR_CRC_BITS _u(0x00000200) -#define USB_INTR_ERROR_CRC_MSB _u(9) -#define USB_INTR_ERROR_CRC_LSB _u(9) -#define USB_INTR_ERROR_CRC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_INTR_ERROR_BIT_STUFF -// Description : Source: SIE_STATUS.BIT_STUFF_ERROR -#define USB_INTR_ERROR_BIT_STUFF_RESET _u(0x0) -#define USB_INTR_ERROR_BIT_STUFF_BITS _u(0x00000100) -#define USB_INTR_ERROR_BIT_STUFF_MSB _u(8) -#define USB_INTR_ERROR_BIT_STUFF_LSB _u(8) -#define USB_INTR_ERROR_BIT_STUFF_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_INTR_ERROR_RX_OVERFLOW -// Description : Source: SIE_STATUS.RX_OVERFLOW -#define USB_INTR_ERROR_RX_OVERFLOW_RESET _u(0x0) -#define USB_INTR_ERROR_RX_OVERFLOW_BITS _u(0x00000080) -#define USB_INTR_ERROR_RX_OVERFLOW_MSB _u(7) -#define USB_INTR_ERROR_RX_OVERFLOW_LSB _u(7) -#define USB_INTR_ERROR_RX_OVERFLOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_INTR_ERROR_RX_TIMEOUT -// Description : Source: SIE_STATUS.RX_TIMEOUT -#define USB_INTR_ERROR_RX_TIMEOUT_RESET _u(0x0) -#define USB_INTR_ERROR_RX_TIMEOUT_BITS _u(0x00000040) -#define USB_INTR_ERROR_RX_TIMEOUT_MSB _u(6) -#define USB_INTR_ERROR_RX_TIMEOUT_LSB _u(6) -#define USB_INTR_ERROR_RX_TIMEOUT_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_INTR_ERROR_DATA_SEQ -// Description : Source: SIE_STATUS.DATA_SEQ_ERROR -#define USB_INTR_ERROR_DATA_SEQ_RESET _u(0x0) -#define USB_INTR_ERROR_DATA_SEQ_BITS _u(0x00000020) -#define USB_INTR_ERROR_DATA_SEQ_MSB _u(5) -#define USB_INTR_ERROR_DATA_SEQ_LSB _u(5) -#define USB_INTR_ERROR_DATA_SEQ_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_INTR_BUFF_STATUS -// Description : Raised when any bit in BUFF_STATUS is set. Clear by clearing -// all bits in BUFF_STATUS. -#define USB_INTR_BUFF_STATUS_RESET _u(0x0) -#define USB_INTR_BUFF_STATUS_BITS _u(0x00000010) -#define USB_INTR_BUFF_STATUS_MSB _u(4) -#define USB_INTR_BUFF_STATUS_LSB _u(4) -#define USB_INTR_BUFF_STATUS_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_INTR_TRANS_COMPLETE -// Description : Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by -// writing to this bit. -#define USB_INTR_TRANS_COMPLETE_RESET _u(0x0) -#define USB_INTR_TRANS_COMPLETE_BITS _u(0x00000008) -#define USB_INTR_TRANS_COMPLETE_MSB _u(3) -#define USB_INTR_TRANS_COMPLETE_LSB _u(3) -#define USB_INTR_TRANS_COMPLETE_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_INTR_HOST_SOF -// Description : Host: raised every time the host sends a SOF (Start of Frame). -// Cleared by reading SOF_RD -#define USB_INTR_HOST_SOF_RESET _u(0x0) -#define USB_INTR_HOST_SOF_BITS _u(0x00000004) -#define USB_INTR_HOST_SOF_MSB _u(2) -#define USB_INTR_HOST_SOF_LSB _u(2) -#define USB_INTR_HOST_SOF_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_INTR_HOST_RESUME -// Description : Host: raised when a device wakes up the host. Cleared by -// writing to SIE_STATUS.RESUME -#define USB_INTR_HOST_RESUME_RESET _u(0x0) -#define USB_INTR_HOST_RESUME_BITS _u(0x00000002) -#define USB_INTR_HOST_RESUME_MSB _u(1) -#define USB_INTR_HOST_RESUME_LSB _u(1) -#define USB_INTR_HOST_RESUME_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_INTR_HOST_CONN_DIS -// Description : Host: raised when a device is connected or disconnected (i.e. -// when SIE_STATUS.SPEED changes). Cleared by writing to -// SIE_STATUS.SPEED -#define USB_INTR_HOST_CONN_DIS_RESET _u(0x0) -#define USB_INTR_HOST_CONN_DIS_BITS _u(0x00000001) -#define USB_INTR_HOST_CONN_DIS_MSB _u(0) -#define USB_INTR_HOST_CONN_DIS_LSB _u(0) -#define USB_INTR_HOST_CONN_DIS_ACCESS "RO" -// ============================================================================= -// Register : USB_INTE -// Description : Interrupt Enable -#define USB_INTE_OFFSET _u(0x00000090) -#define USB_INTE_BITS _u(0x00ffffff) -#define USB_INTE_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_INTE_EPX_STOPPED_ON_NAK -// Description : Source: NAK_POLL.EPX_STOPPED_ON_NAK -#define USB_INTE_EPX_STOPPED_ON_NAK_RESET _u(0x0) -#define USB_INTE_EPX_STOPPED_ON_NAK_BITS _u(0x00800000) -#define USB_INTE_EPX_STOPPED_ON_NAK_MSB _u(23) -#define USB_INTE_EPX_STOPPED_ON_NAK_LSB _u(23) -#define USB_INTE_EPX_STOPPED_ON_NAK_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_INTE_DEV_SM_WATCHDOG_FIRED -// Description : Source: DEV_SM_WATCHDOG.FIRED -#define USB_INTE_DEV_SM_WATCHDOG_FIRED_RESET _u(0x0) -#define USB_INTE_DEV_SM_WATCHDOG_FIRED_BITS _u(0x00400000) -#define USB_INTE_DEV_SM_WATCHDOG_FIRED_MSB _u(22) -#define USB_INTE_DEV_SM_WATCHDOG_FIRED_LSB _u(22) -#define USB_INTE_DEV_SM_WATCHDOG_FIRED_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_INTE_ENDPOINT_ERROR -// Description : Source: SIE_STATUS.ENDPOINT_ERROR -#define USB_INTE_ENDPOINT_ERROR_RESET _u(0x0) -#define USB_INTE_ENDPOINT_ERROR_BITS _u(0x00200000) -#define USB_INTE_ENDPOINT_ERROR_MSB _u(21) -#define USB_INTE_ENDPOINT_ERROR_LSB _u(21) -#define USB_INTE_ENDPOINT_ERROR_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_INTE_RX_SHORT_PACKET -// Description : Source: SIE_STATUS.RX_SHORT_PACKET -#define USB_INTE_RX_SHORT_PACKET_RESET _u(0x0) -#define USB_INTE_RX_SHORT_PACKET_BITS _u(0x00100000) -#define USB_INTE_RX_SHORT_PACKET_MSB _u(20) -#define USB_INTE_RX_SHORT_PACKET_LSB _u(20) -#define USB_INTE_RX_SHORT_PACKET_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_INTE_EP_STALL_NAK -// Description : Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by -// clearing all bits in EP_STATUS_STALL_NAK. -#define USB_INTE_EP_STALL_NAK_RESET _u(0x0) -#define USB_INTE_EP_STALL_NAK_BITS _u(0x00080000) -#define USB_INTE_EP_STALL_NAK_MSB _u(19) -#define USB_INTE_EP_STALL_NAK_LSB _u(19) -#define USB_INTE_EP_STALL_NAK_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_INTE_ABORT_DONE -// Description : Raised when any bit in ABORT_DONE is set. Clear by clearing all -// bits in ABORT_DONE. -#define USB_INTE_ABORT_DONE_RESET _u(0x0) -#define USB_INTE_ABORT_DONE_BITS _u(0x00040000) -#define USB_INTE_ABORT_DONE_MSB _u(18) -#define USB_INTE_ABORT_DONE_LSB _u(18) -#define USB_INTE_ABORT_DONE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_INTE_DEV_SOF -// Description : Set every time the device receives a SOF (Start of Frame) -// packet. Cleared by reading SOF_RD -#define USB_INTE_DEV_SOF_RESET _u(0x0) -#define USB_INTE_DEV_SOF_BITS _u(0x00020000) -#define USB_INTE_DEV_SOF_MSB _u(17) -#define USB_INTE_DEV_SOF_LSB _u(17) -#define USB_INTE_DEV_SOF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_INTE_SETUP_REQ -// Description : Device. Source: SIE_STATUS.SETUP_REC -#define USB_INTE_SETUP_REQ_RESET _u(0x0) -#define USB_INTE_SETUP_REQ_BITS _u(0x00010000) -#define USB_INTE_SETUP_REQ_MSB _u(16) -#define USB_INTE_SETUP_REQ_LSB _u(16) -#define USB_INTE_SETUP_REQ_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_INTE_DEV_RESUME_FROM_HOST -// Description : Set when the device receives a resume from the host. Cleared by -// writing to SIE_STATUS.RESUME -#define USB_INTE_DEV_RESUME_FROM_HOST_RESET _u(0x0) -#define USB_INTE_DEV_RESUME_FROM_HOST_BITS _u(0x00008000) -#define USB_INTE_DEV_RESUME_FROM_HOST_MSB _u(15) -#define USB_INTE_DEV_RESUME_FROM_HOST_LSB _u(15) -#define USB_INTE_DEV_RESUME_FROM_HOST_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_INTE_DEV_SUSPEND -// Description : Set when the device suspend state changes. Cleared by writing -// to SIE_STATUS.SUSPENDED -#define USB_INTE_DEV_SUSPEND_RESET _u(0x0) -#define USB_INTE_DEV_SUSPEND_BITS _u(0x00004000) -#define USB_INTE_DEV_SUSPEND_MSB _u(14) -#define USB_INTE_DEV_SUSPEND_LSB _u(14) -#define USB_INTE_DEV_SUSPEND_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_INTE_DEV_CONN_DIS -// Description : Set when the device connection state changes. Cleared by -// writing to SIE_STATUS.CONNECTED -#define USB_INTE_DEV_CONN_DIS_RESET _u(0x0) -#define USB_INTE_DEV_CONN_DIS_BITS _u(0x00002000) -#define USB_INTE_DEV_CONN_DIS_MSB _u(13) -#define USB_INTE_DEV_CONN_DIS_LSB _u(13) -#define USB_INTE_DEV_CONN_DIS_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_INTE_BUS_RESET -// Description : Source: SIE_STATUS.BUS_RESET -#define USB_INTE_BUS_RESET_RESET _u(0x0) -#define USB_INTE_BUS_RESET_BITS _u(0x00001000) -#define USB_INTE_BUS_RESET_MSB _u(12) -#define USB_INTE_BUS_RESET_LSB _u(12) -#define USB_INTE_BUS_RESET_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_INTE_VBUS_DETECT -// Description : Source: SIE_STATUS.VBUS_DETECTED -#define USB_INTE_VBUS_DETECT_RESET _u(0x0) -#define USB_INTE_VBUS_DETECT_BITS _u(0x00000800) -#define USB_INTE_VBUS_DETECT_MSB _u(11) -#define USB_INTE_VBUS_DETECT_LSB _u(11) -#define USB_INTE_VBUS_DETECT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_INTE_STALL -// Description : Source: SIE_STATUS.STALL_REC -#define USB_INTE_STALL_RESET _u(0x0) -#define USB_INTE_STALL_BITS _u(0x00000400) -#define USB_INTE_STALL_MSB _u(10) -#define USB_INTE_STALL_LSB _u(10) -#define USB_INTE_STALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_INTE_ERROR_CRC -// Description : Source: SIE_STATUS.CRC_ERROR -#define USB_INTE_ERROR_CRC_RESET _u(0x0) -#define USB_INTE_ERROR_CRC_BITS _u(0x00000200) -#define USB_INTE_ERROR_CRC_MSB _u(9) -#define USB_INTE_ERROR_CRC_LSB _u(9) -#define USB_INTE_ERROR_CRC_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_INTE_ERROR_BIT_STUFF -// Description : Source: SIE_STATUS.BIT_STUFF_ERROR -#define USB_INTE_ERROR_BIT_STUFF_RESET _u(0x0) -#define USB_INTE_ERROR_BIT_STUFF_BITS _u(0x00000100) -#define USB_INTE_ERROR_BIT_STUFF_MSB _u(8) -#define USB_INTE_ERROR_BIT_STUFF_LSB _u(8) -#define USB_INTE_ERROR_BIT_STUFF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_INTE_ERROR_RX_OVERFLOW -// Description : Source: SIE_STATUS.RX_OVERFLOW -#define USB_INTE_ERROR_RX_OVERFLOW_RESET _u(0x0) -#define USB_INTE_ERROR_RX_OVERFLOW_BITS _u(0x00000080) -#define USB_INTE_ERROR_RX_OVERFLOW_MSB _u(7) -#define USB_INTE_ERROR_RX_OVERFLOW_LSB _u(7) -#define USB_INTE_ERROR_RX_OVERFLOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_INTE_ERROR_RX_TIMEOUT -// Description : Source: SIE_STATUS.RX_TIMEOUT -#define USB_INTE_ERROR_RX_TIMEOUT_RESET _u(0x0) -#define USB_INTE_ERROR_RX_TIMEOUT_BITS _u(0x00000040) -#define USB_INTE_ERROR_RX_TIMEOUT_MSB _u(6) -#define USB_INTE_ERROR_RX_TIMEOUT_LSB _u(6) -#define USB_INTE_ERROR_RX_TIMEOUT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_INTE_ERROR_DATA_SEQ -// Description : Source: SIE_STATUS.DATA_SEQ_ERROR -#define USB_INTE_ERROR_DATA_SEQ_RESET _u(0x0) -#define USB_INTE_ERROR_DATA_SEQ_BITS _u(0x00000020) -#define USB_INTE_ERROR_DATA_SEQ_MSB _u(5) -#define USB_INTE_ERROR_DATA_SEQ_LSB _u(5) -#define USB_INTE_ERROR_DATA_SEQ_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_INTE_BUFF_STATUS -// Description : Raised when any bit in BUFF_STATUS is set. Clear by clearing -// all bits in BUFF_STATUS. -#define USB_INTE_BUFF_STATUS_RESET _u(0x0) -#define USB_INTE_BUFF_STATUS_BITS _u(0x00000010) -#define USB_INTE_BUFF_STATUS_MSB _u(4) -#define USB_INTE_BUFF_STATUS_LSB _u(4) -#define USB_INTE_BUFF_STATUS_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_INTE_TRANS_COMPLETE -// Description : Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by -// writing to this bit. -#define USB_INTE_TRANS_COMPLETE_RESET _u(0x0) -#define USB_INTE_TRANS_COMPLETE_BITS _u(0x00000008) -#define USB_INTE_TRANS_COMPLETE_MSB _u(3) -#define USB_INTE_TRANS_COMPLETE_LSB _u(3) -#define USB_INTE_TRANS_COMPLETE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_INTE_HOST_SOF -// Description : Host: raised every time the host sends a SOF (Start of Frame). -// Cleared by reading SOF_RD -#define USB_INTE_HOST_SOF_RESET _u(0x0) -#define USB_INTE_HOST_SOF_BITS _u(0x00000004) -#define USB_INTE_HOST_SOF_MSB _u(2) -#define USB_INTE_HOST_SOF_LSB _u(2) -#define USB_INTE_HOST_SOF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_INTE_HOST_RESUME -// Description : Host: raised when a device wakes up the host. Cleared by -// writing to SIE_STATUS.RESUME -#define USB_INTE_HOST_RESUME_RESET _u(0x0) -#define USB_INTE_HOST_RESUME_BITS _u(0x00000002) -#define USB_INTE_HOST_RESUME_MSB _u(1) -#define USB_INTE_HOST_RESUME_LSB _u(1) -#define USB_INTE_HOST_RESUME_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_INTE_HOST_CONN_DIS -// Description : Host: raised when a device is connected or disconnected (i.e. -// when SIE_STATUS.SPEED changes). Cleared by writing to -// SIE_STATUS.SPEED -#define USB_INTE_HOST_CONN_DIS_RESET _u(0x0) -#define USB_INTE_HOST_CONN_DIS_BITS _u(0x00000001) -#define USB_INTE_HOST_CONN_DIS_MSB _u(0) -#define USB_INTE_HOST_CONN_DIS_LSB _u(0) -#define USB_INTE_HOST_CONN_DIS_ACCESS "RW" -// ============================================================================= -// Register : USB_INTF -// Description : Interrupt Force -#define USB_INTF_OFFSET _u(0x00000094) -#define USB_INTF_BITS _u(0x00ffffff) -#define USB_INTF_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_INTF_EPX_STOPPED_ON_NAK -// Description : Source: NAK_POLL.EPX_STOPPED_ON_NAK -#define USB_INTF_EPX_STOPPED_ON_NAK_RESET _u(0x0) -#define USB_INTF_EPX_STOPPED_ON_NAK_BITS _u(0x00800000) -#define USB_INTF_EPX_STOPPED_ON_NAK_MSB _u(23) -#define USB_INTF_EPX_STOPPED_ON_NAK_LSB _u(23) -#define USB_INTF_EPX_STOPPED_ON_NAK_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_INTF_DEV_SM_WATCHDOG_FIRED -// Description : Source: DEV_SM_WATCHDOG.FIRED -#define USB_INTF_DEV_SM_WATCHDOG_FIRED_RESET _u(0x0) -#define USB_INTF_DEV_SM_WATCHDOG_FIRED_BITS _u(0x00400000) -#define USB_INTF_DEV_SM_WATCHDOG_FIRED_MSB _u(22) -#define USB_INTF_DEV_SM_WATCHDOG_FIRED_LSB _u(22) -#define USB_INTF_DEV_SM_WATCHDOG_FIRED_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_INTF_ENDPOINT_ERROR -// Description : Source: SIE_STATUS.ENDPOINT_ERROR -#define USB_INTF_ENDPOINT_ERROR_RESET _u(0x0) -#define USB_INTF_ENDPOINT_ERROR_BITS _u(0x00200000) -#define USB_INTF_ENDPOINT_ERROR_MSB _u(21) -#define USB_INTF_ENDPOINT_ERROR_LSB _u(21) -#define USB_INTF_ENDPOINT_ERROR_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_INTF_RX_SHORT_PACKET -// Description : Source: SIE_STATUS.RX_SHORT_PACKET -#define USB_INTF_RX_SHORT_PACKET_RESET _u(0x0) -#define USB_INTF_RX_SHORT_PACKET_BITS _u(0x00100000) -#define USB_INTF_RX_SHORT_PACKET_MSB _u(20) -#define USB_INTF_RX_SHORT_PACKET_LSB _u(20) -#define USB_INTF_RX_SHORT_PACKET_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_INTF_EP_STALL_NAK -// Description : Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by -// clearing all bits in EP_STATUS_STALL_NAK. -#define USB_INTF_EP_STALL_NAK_RESET _u(0x0) -#define USB_INTF_EP_STALL_NAK_BITS _u(0x00080000) -#define USB_INTF_EP_STALL_NAK_MSB _u(19) -#define USB_INTF_EP_STALL_NAK_LSB _u(19) -#define USB_INTF_EP_STALL_NAK_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_INTF_ABORT_DONE -// Description : Raised when any bit in ABORT_DONE is set. Clear by clearing all -// bits in ABORT_DONE. -#define USB_INTF_ABORT_DONE_RESET _u(0x0) -#define USB_INTF_ABORT_DONE_BITS _u(0x00040000) -#define USB_INTF_ABORT_DONE_MSB _u(18) -#define USB_INTF_ABORT_DONE_LSB _u(18) -#define USB_INTF_ABORT_DONE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_INTF_DEV_SOF -// Description : Set every time the device receives a SOF (Start of Frame) -// packet. Cleared by reading SOF_RD -#define USB_INTF_DEV_SOF_RESET _u(0x0) -#define USB_INTF_DEV_SOF_BITS _u(0x00020000) -#define USB_INTF_DEV_SOF_MSB _u(17) -#define USB_INTF_DEV_SOF_LSB _u(17) -#define USB_INTF_DEV_SOF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_INTF_SETUP_REQ -// Description : Device. Source: SIE_STATUS.SETUP_REC -#define USB_INTF_SETUP_REQ_RESET _u(0x0) -#define USB_INTF_SETUP_REQ_BITS _u(0x00010000) -#define USB_INTF_SETUP_REQ_MSB _u(16) -#define USB_INTF_SETUP_REQ_LSB _u(16) -#define USB_INTF_SETUP_REQ_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_INTF_DEV_RESUME_FROM_HOST -// Description : Set when the device receives a resume from the host. Cleared by -// writing to SIE_STATUS.RESUME -#define USB_INTF_DEV_RESUME_FROM_HOST_RESET _u(0x0) -#define USB_INTF_DEV_RESUME_FROM_HOST_BITS _u(0x00008000) -#define USB_INTF_DEV_RESUME_FROM_HOST_MSB _u(15) -#define USB_INTF_DEV_RESUME_FROM_HOST_LSB _u(15) -#define USB_INTF_DEV_RESUME_FROM_HOST_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_INTF_DEV_SUSPEND -// Description : Set when the device suspend state changes. Cleared by writing -// to SIE_STATUS.SUSPENDED -#define USB_INTF_DEV_SUSPEND_RESET _u(0x0) -#define USB_INTF_DEV_SUSPEND_BITS _u(0x00004000) -#define USB_INTF_DEV_SUSPEND_MSB _u(14) -#define USB_INTF_DEV_SUSPEND_LSB _u(14) -#define USB_INTF_DEV_SUSPEND_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_INTF_DEV_CONN_DIS -// Description : Set when the device connection state changes. Cleared by -// writing to SIE_STATUS.CONNECTED -#define USB_INTF_DEV_CONN_DIS_RESET _u(0x0) -#define USB_INTF_DEV_CONN_DIS_BITS _u(0x00002000) -#define USB_INTF_DEV_CONN_DIS_MSB _u(13) -#define USB_INTF_DEV_CONN_DIS_LSB _u(13) -#define USB_INTF_DEV_CONN_DIS_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_INTF_BUS_RESET -// Description : Source: SIE_STATUS.BUS_RESET -#define USB_INTF_BUS_RESET_RESET _u(0x0) -#define USB_INTF_BUS_RESET_BITS _u(0x00001000) -#define USB_INTF_BUS_RESET_MSB _u(12) -#define USB_INTF_BUS_RESET_LSB _u(12) -#define USB_INTF_BUS_RESET_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_INTF_VBUS_DETECT -// Description : Source: SIE_STATUS.VBUS_DETECTED -#define USB_INTF_VBUS_DETECT_RESET _u(0x0) -#define USB_INTF_VBUS_DETECT_BITS _u(0x00000800) -#define USB_INTF_VBUS_DETECT_MSB _u(11) -#define USB_INTF_VBUS_DETECT_LSB _u(11) -#define USB_INTF_VBUS_DETECT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_INTF_STALL -// Description : Source: SIE_STATUS.STALL_REC -#define USB_INTF_STALL_RESET _u(0x0) -#define USB_INTF_STALL_BITS _u(0x00000400) -#define USB_INTF_STALL_MSB _u(10) -#define USB_INTF_STALL_LSB _u(10) -#define USB_INTF_STALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_INTF_ERROR_CRC -// Description : Source: SIE_STATUS.CRC_ERROR -#define USB_INTF_ERROR_CRC_RESET _u(0x0) -#define USB_INTF_ERROR_CRC_BITS _u(0x00000200) -#define USB_INTF_ERROR_CRC_MSB _u(9) -#define USB_INTF_ERROR_CRC_LSB _u(9) -#define USB_INTF_ERROR_CRC_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_INTF_ERROR_BIT_STUFF -// Description : Source: SIE_STATUS.BIT_STUFF_ERROR -#define USB_INTF_ERROR_BIT_STUFF_RESET _u(0x0) -#define USB_INTF_ERROR_BIT_STUFF_BITS _u(0x00000100) -#define USB_INTF_ERROR_BIT_STUFF_MSB _u(8) -#define USB_INTF_ERROR_BIT_STUFF_LSB _u(8) -#define USB_INTF_ERROR_BIT_STUFF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_INTF_ERROR_RX_OVERFLOW -// Description : Source: SIE_STATUS.RX_OVERFLOW -#define USB_INTF_ERROR_RX_OVERFLOW_RESET _u(0x0) -#define USB_INTF_ERROR_RX_OVERFLOW_BITS _u(0x00000080) -#define USB_INTF_ERROR_RX_OVERFLOW_MSB _u(7) -#define USB_INTF_ERROR_RX_OVERFLOW_LSB _u(7) -#define USB_INTF_ERROR_RX_OVERFLOW_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_INTF_ERROR_RX_TIMEOUT -// Description : Source: SIE_STATUS.RX_TIMEOUT -#define USB_INTF_ERROR_RX_TIMEOUT_RESET _u(0x0) -#define USB_INTF_ERROR_RX_TIMEOUT_BITS _u(0x00000040) -#define USB_INTF_ERROR_RX_TIMEOUT_MSB _u(6) -#define USB_INTF_ERROR_RX_TIMEOUT_LSB _u(6) -#define USB_INTF_ERROR_RX_TIMEOUT_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_INTF_ERROR_DATA_SEQ -// Description : Source: SIE_STATUS.DATA_SEQ_ERROR -#define USB_INTF_ERROR_DATA_SEQ_RESET _u(0x0) -#define USB_INTF_ERROR_DATA_SEQ_BITS _u(0x00000020) -#define USB_INTF_ERROR_DATA_SEQ_MSB _u(5) -#define USB_INTF_ERROR_DATA_SEQ_LSB _u(5) -#define USB_INTF_ERROR_DATA_SEQ_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_INTF_BUFF_STATUS -// Description : Raised when any bit in BUFF_STATUS is set. Clear by clearing -// all bits in BUFF_STATUS. -#define USB_INTF_BUFF_STATUS_RESET _u(0x0) -#define USB_INTF_BUFF_STATUS_BITS _u(0x00000010) -#define USB_INTF_BUFF_STATUS_MSB _u(4) -#define USB_INTF_BUFF_STATUS_LSB _u(4) -#define USB_INTF_BUFF_STATUS_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_INTF_TRANS_COMPLETE -// Description : Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by -// writing to this bit. -#define USB_INTF_TRANS_COMPLETE_RESET _u(0x0) -#define USB_INTF_TRANS_COMPLETE_BITS _u(0x00000008) -#define USB_INTF_TRANS_COMPLETE_MSB _u(3) -#define USB_INTF_TRANS_COMPLETE_LSB _u(3) -#define USB_INTF_TRANS_COMPLETE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_INTF_HOST_SOF -// Description : Host: raised every time the host sends a SOF (Start of Frame). -// Cleared by reading SOF_RD -#define USB_INTF_HOST_SOF_RESET _u(0x0) -#define USB_INTF_HOST_SOF_BITS _u(0x00000004) -#define USB_INTF_HOST_SOF_MSB _u(2) -#define USB_INTF_HOST_SOF_LSB _u(2) -#define USB_INTF_HOST_SOF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_INTF_HOST_RESUME -// Description : Host: raised when a device wakes up the host. Cleared by -// writing to SIE_STATUS.RESUME -#define USB_INTF_HOST_RESUME_RESET _u(0x0) -#define USB_INTF_HOST_RESUME_BITS _u(0x00000002) -#define USB_INTF_HOST_RESUME_MSB _u(1) -#define USB_INTF_HOST_RESUME_LSB _u(1) -#define USB_INTF_HOST_RESUME_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_INTF_HOST_CONN_DIS -// Description : Host: raised when a device is connected or disconnected (i.e. -// when SIE_STATUS.SPEED changes). Cleared by writing to -// SIE_STATUS.SPEED -#define USB_INTF_HOST_CONN_DIS_RESET _u(0x0) -#define USB_INTF_HOST_CONN_DIS_BITS _u(0x00000001) -#define USB_INTF_HOST_CONN_DIS_MSB _u(0) -#define USB_INTF_HOST_CONN_DIS_LSB _u(0) -#define USB_INTF_HOST_CONN_DIS_ACCESS "RW" -// ============================================================================= -// Register : USB_INTS -// Description : Interrupt status after masking & forcing -#define USB_INTS_OFFSET _u(0x00000098) -#define USB_INTS_BITS _u(0x00ffffff) -#define USB_INTS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_INTS_EPX_STOPPED_ON_NAK -// Description : Source: NAK_POLL.EPX_STOPPED_ON_NAK -#define USB_INTS_EPX_STOPPED_ON_NAK_RESET _u(0x0) -#define USB_INTS_EPX_STOPPED_ON_NAK_BITS _u(0x00800000) -#define USB_INTS_EPX_STOPPED_ON_NAK_MSB _u(23) -#define USB_INTS_EPX_STOPPED_ON_NAK_LSB _u(23) -#define USB_INTS_EPX_STOPPED_ON_NAK_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_INTS_DEV_SM_WATCHDOG_FIRED -// Description : Source: DEV_SM_WATCHDOG.FIRED -#define USB_INTS_DEV_SM_WATCHDOG_FIRED_RESET _u(0x0) -#define USB_INTS_DEV_SM_WATCHDOG_FIRED_BITS _u(0x00400000) -#define USB_INTS_DEV_SM_WATCHDOG_FIRED_MSB _u(22) -#define USB_INTS_DEV_SM_WATCHDOG_FIRED_LSB _u(22) -#define USB_INTS_DEV_SM_WATCHDOG_FIRED_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_INTS_ENDPOINT_ERROR -// Description : Source: SIE_STATUS.ENDPOINT_ERROR -#define USB_INTS_ENDPOINT_ERROR_RESET _u(0x0) -#define USB_INTS_ENDPOINT_ERROR_BITS _u(0x00200000) -#define USB_INTS_ENDPOINT_ERROR_MSB _u(21) -#define USB_INTS_ENDPOINT_ERROR_LSB _u(21) -#define USB_INTS_ENDPOINT_ERROR_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_INTS_RX_SHORT_PACKET -// Description : Source: SIE_STATUS.RX_SHORT_PACKET -#define USB_INTS_RX_SHORT_PACKET_RESET _u(0x0) -#define USB_INTS_RX_SHORT_PACKET_BITS _u(0x00100000) -#define USB_INTS_RX_SHORT_PACKET_MSB _u(20) -#define USB_INTS_RX_SHORT_PACKET_LSB _u(20) -#define USB_INTS_RX_SHORT_PACKET_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_INTS_EP_STALL_NAK -// Description : Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by -// clearing all bits in EP_STATUS_STALL_NAK. -#define USB_INTS_EP_STALL_NAK_RESET _u(0x0) -#define USB_INTS_EP_STALL_NAK_BITS _u(0x00080000) -#define USB_INTS_EP_STALL_NAK_MSB _u(19) -#define USB_INTS_EP_STALL_NAK_LSB _u(19) -#define USB_INTS_EP_STALL_NAK_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_INTS_ABORT_DONE -// Description : Raised when any bit in ABORT_DONE is set. Clear by clearing all -// bits in ABORT_DONE. -#define USB_INTS_ABORT_DONE_RESET _u(0x0) -#define USB_INTS_ABORT_DONE_BITS _u(0x00040000) -#define USB_INTS_ABORT_DONE_MSB _u(18) -#define USB_INTS_ABORT_DONE_LSB _u(18) -#define USB_INTS_ABORT_DONE_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_INTS_DEV_SOF -// Description : Set every time the device receives a SOF (Start of Frame) -// packet. Cleared by reading SOF_RD -#define USB_INTS_DEV_SOF_RESET _u(0x0) -#define USB_INTS_DEV_SOF_BITS _u(0x00020000) -#define USB_INTS_DEV_SOF_MSB _u(17) -#define USB_INTS_DEV_SOF_LSB _u(17) -#define USB_INTS_DEV_SOF_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_INTS_SETUP_REQ -// Description : Device. Source: SIE_STATUS.SETUP_REC -#define USB_INTS_SETUP_REQ_RESET _u(0x0) -#define USB_INTS_SETUP_REQ_BITS _u(0x00010000) -#define USB_INTS_SETUP_REQ_MSB _u(16) -#define USB_INTS_SETUP_REQ_LSB _u(16) -#define USB_INTS_SETUP_REQ_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_INTS_DEV_RESUME_FROM_HOST -// Description : Set when the device receives a resume from the host. Cleared by -// writing to SIE_STATUS.RESUME -#define USB_INTS_DEV_RESUME_FROM_HOST_RESET _u(0x0) -#define USB_INTS_DEV_RESUME_FROM_HOST_BITS _u(0x00008000) -#define USB_INTS_DEV_RESUME_FROM_HOST_MSB _u(15) -#define USB_INTS_DEV_RESUME_FROM_HOST_LSB _u(15) -#define USB_INTS_DEV_RESUME_FROM_HOST_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_INTS_DEV_SUSPEND -// Description : Set when the device suspend state changes. Cleared by writing -// to SIE_STATUS.SUSPENDED -#define USB_INTS_DEV_SUSPEND_RESET _u(0x0) -#define USB_INTS_DEV_SUSPEND_BITS _u(0x00004000) -#define USB_INTS_DEV_SUSPEND_MSB _u(14) -#define USB_INTS_DEV_SUSPEND_LSB _u(14) -#define USB_INTS_DEV_SUSPEND_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_INTS_DEV_CONN_DIS -// Description : Set when the device connection state changes. Cleared by -// writing to SIE_STATUS.CONNECTED -#define USB_INTS_DEV_CONN_DIS_RESET _u(0x0) -#define USB_INTS_DEV_CONN_DIS_BITS _u(0x00002000) -#define USB_INTS_DEV_CONN_DIS_MSB _u(13) -#define USB_INTS_DEV_CONN_DIS_LSB _u(13) -#define USB_INTS_DEV_CONN_DIS_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_INTS_BUS_RESET -// Description : Source: SIE_STATUS.BUS_RESET -#define USB_INTS_BUS_RESET_RESET _u(0x0) -#define USB_INTS_BUS_RESET_BITS _u(0x00001000) -#define USB_INTS_BUS_RESET_MSB _u(12) -#define USB_INTS_BUS_RESET_LSB _u(12) -#define USB_INTS_BUS_RESET_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_INTS_VBUS_DETECT -// Description : Source: SIE_STATUS.VBUS_DETECTED -#define USB_INTS_VBUS_DETECT_RESET _u(0x0) -#define USB_INTS_VBUS_DETECT_BITS _u(0x00000800) -#define USB_INTS_VBUS_DETECT_MSB _u(11) -#define USB_INTS_VBUS_DETECT_LSB _u(11) -#define USB_INTS_VBUS_DETECT_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_INTS_STALL -// Description : Source: SIE_STATUS.STALL_REC -#define USB_INTS_STALL_RESET _u(0x0) -#define USB_INTS_STALL_BITS _u(0x00000400) -#define USB_INTS_STALL_MSB _u(10) -#define USB_INTS_STALL_LSB _u(10) -#define USB_INTS_STALL_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_INTS_ERROR_CRC -// Description : Source: SIE_STATUS.CRC_ERROR -#define USB_INTS_ERROR_CRC_RESET _u(0x0) -#define USB_INTS_ERROR_CRC_BITS _u(0x00000200) -#define USB_INTS_ERROR_CRC_MSB _u(9) -#define USB_INTS_ERROR_CRC_LSB _u(9) -#define USB_INTS_ERROR_CRC_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_INTS_ERROR_BIT_STUFF -// Description : Source: SIE_STATUS.BIT_STUFF_ERROR -#define USB_INTS_ERROR_BIT_STUFF_RESET _u(0x0) -#define USB_INTS_ERROR_BIT_STUFF_BITS _u(0x00000100) -#define USB_INTS_ERROR_BIT_STUFF_MSB _u(8) -#define USB_INTS_ERROR_BIT_STUFF_LSB _u(8) -#define USB_INTS_ERROR_BIT_STUFF_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_INTS_ERROR_RX_OVERFLOW -// Description : Source: SIE_STATUS.RX_OVERFLOW -#define USB_INTS_ERROR_RX_OVERFLOW_RESET _u(0x0) -#define USB_INTS_ERROR_RX_OVERFLOW_BITS _u(0x00000080) -#define USB_INTS_ERROR_RX_OVERFLOW_MSB _u(7) -#define USB_INTS_ERROR_RX_OVERFLOW_LSB _u(7) -#define USB_INTS_ERROR_RX_OVERFLOW_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_INTS_ERROR_RX_TIMEOUT -// Description : Source: SIE_STATUS.RX_TIMEOUT -#define USB_INTS_ERROR_RX_TIMEOUT_RESET _u(0x0) -#define USB_INTS_ERROR_RX_TIMEOUT_BITS _u(0x00000040) -#define USB_INTS_ERROR_RX_TIMEOUT_MSB _u(6) -#define USB_INTS_ERROR_RX_TIMEOUT_LSB _u(6) -#define USB_INTS_ERROR_RX_TIMEOUT_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_INTS_ERROR_DATA_SEQ -// Description : Source: SIE_STATUS.DATA_SEQ_ERROR -#define USB_INTS_ERROR_DATA_SEQ_RESET _u(0x0) -#define USB_INTS_ERROR_DATA_SEQ_BITS _u(0x00000020) -#define USB_INTS_ERROR_DATA_SEQ_MSB _u(5) -#define USB_INTS_ERROR_DATA_SEQ_LSB _u(5) -#define USB_INTS_ERROR_DATA_SEQ_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_INTS_BUFF_STATUS -// Description : Raised when any bit in BUFF_STATUS is set. Clear by clearing -// all bits in BUFF_STATUS. -#define USB_INTS_BUFF_STATUS_RESET _u(0x0) -#define USB_INTS_BUFF_STATUS_BITS _u(0x00000010) -#define USB_INTS_BUFF_STATUS_MSB _u(4) -#define USB_INTS_BUFF_STATUS_LSB _u(4) -#define USB_INTS_BUFF_STATUS_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_INTS_TRANS_COMPLETE -// Description : Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by -// writing to this bit. -#define USB_INTS_TRANS_COMPLETE_RESET _u(0x0) -#define USB_INTS_TRANS_COMPLETE_BITS _u(0x00000008) -#define USB_INTS_TRANS_COMPLETE_MSB _u(3) -#define USB_INTS_TRANS_COMPLETE_LSB _u(3) -#define USB_INTS_TRANS_COMPLETE_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_INTS_HOST_SOF -// Description : Host: raised every time the host sends a SOF (Start of Frame). -// Cleared by reading SOF_RD -#define USB_INTS_HOST_SOF_RESET _u(0x0) -#define USB_INTS_HOST_SOF_BITS _u(0x00000004) -#define USB_INTS_HOST_SOF_MSB _u(2) -#define USB_INTS_HOST_SOF_LSB _u(2) -#define USB_INTS_HOST_SOF_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_INTS_HOST_RESUME -// Description : Host: raised when a device wakes up the host. Cleared by -// writing to SIE_STATUS.RESUME -#define USB_INTS_HOST_RESUME_RESET _u(0x0) -#define USB_INTS_HOST_RESUME_BITS _u(0x00000002) -#define USB_INTS_HOST_RESUME_MSB _u(1) -#define USB_INTS_HOST_RESUME_LSB _u(1) -#define USB_INTS_HOST_RESUME_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_INTS_HOST_CONN_DIS -// Description : Host: raised when a device is connected or disconnected (i.e. -// when SIE_STATUS.SPEED changes). Cleared by writing to -// SIE_STATUS.SPEED -#define USB_INTS_HOST_CONN_DIS_RESET _u(0x0) -#define USB_INTS_HOST_CONN_DIS_BITS _u(0x00000001) -#define USB_INTS_HOST_CONN_DIS_MSB _u(0) -#define USB_INTS_HOST_CONN_DIS_LSB _u(0) -#define USB_INTS_HOST_CONN_DIS_ACCESS "RO" -// ============================================================================= -// Register : USB_SOF_TIMESTAMP_RAW -// Description : Device only. Raw value of free-running PHY clock counter -// @48MHz. Used to calculate time between SOF events. -#define USB_SOF_TIMESTAMP_RAW_OFFSET _u(0x00000100) -#define USB_SOF_TIMESTAMP_RAW_BITS _u(0x001fffff) -#define USB_SOF_TIMESTAMP_RAW_RESET _u(0x00000000) -#define USB_SOF_TIMESTAMP_RAW_MSB _u(20) -#define USB_SOF_TIMESTAMP_RAW_LSB _u(0) -#define USB_SOF_TIMESTAMP_RAW_ACCESS "RO" -// ============================================================================= -// Register : USB_SOF_TIMESTAMP_LAST -// Description : Device only. Value of free-running PHY clock counter @48MHz -// when last SOF event occurred. -#define USB_SOF_TIMESTAMP_LAST_OFFSET _u(0x00000104) -#define USB_SOF_TIMESTAMP_LAST_BITS _u(0x001fffff) -#define USB_SOF_TIMESTAMP_LAST_RESET _u(0x00000000) -#define USB_SOF_TIMESTAMP_LAST_MSB _u(20) -#define USB_SOF_TIMESTAMP_LAST_LSB _u(0) -#define USB_SOF_TIMESTAMP_LAST_ACCESS "RO" -// ============================================================================= -// Register : USB_SM_STATE -#define USB_SM_STATE_OFFSET _u(0x00000108) -#define USB_SM_STATE_BITS _u(0x00000fff) -#define USB_SM_STATE_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_SM_STATE_RX_DASM -#define USB_SM_STATE_RX_DASM_RESET _u(0x0) -#define USB_SM_STATE_RX_DASM_BITS _u(0x00000f00) -#define USB_SM_STATE_RX_DASM_MSB _u(11) -#define USB_SM_STATE_RX_DASM_LSB _u(8) -#define USB_SM_STATE_RX_DASM_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_SM_STATE_BC_STATE -#define USB_SM_STATE_BC_STATE_RESET _u(0x0) -#define USB_SM_STATE_BC_STATE_BITS _u(0x000000e0) -#define USB_SM_STATE_BC_STATE_MSB _u(7) -#define USB_SM_STATE_BC_STATE_LSB _u(5) -#define USB_SM_STATE_BC_STATE_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : USB_SM_STATE_STATE -#define USB_SM_STATE_STATE_RESET _u(0x00) -#define USB_SM_STATE_STATE_BITS _u(0x0000001f) -#define USB_SM_STATE_STATE_MSB _u(4) -#define USB_SM_STATE_STATE_LSB _u(0) -#define USB_SM_STATE_STATE_ACCESS "RO" -// ============================================================================= -// Register : USB_EP_TX_ERROR -// Description : TX error count for each endpoint. Write to each field to reset -// the counter to 0. -#define USB_EP_TX_ERROR_OFFSET _u(0x0000010c) -#define USB_EP_TX_ERROR_BITS _u(0xffffffff) -#define USB_EP_TX_ERROR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_EP_TX_ERROR_EP15 -#define USB_EP_TX_ERROR_EP15_RESET _u(0x0) -#define USB_EP_TX_ERROR_EP15_BITS _u(0xc0000000) -#define USB_EP_TX_ERROR_EP15_MSB _u(31) -#define USB_EP_TX_ERROR_EP15_LSB _u(30) -#define USB_EP_TX_ERROR_EP15_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_TX_ERROR_EP14 -#define USB_EP_TX_ERROR_EP14_RESET _u(0x0) -#define USB_EP_TX_ERROR_EP14_BITS _u(0x30000000) -#define USB_EP_TX_ERROR_EP14_MSB _u(29) -#define USB_EP_TX_ERROR_EP14_LSB _u(28) -#define USB_EP_TX_ERROR_EP14_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_TX_ERROR_EP13 -#define USB_EP_TX_ERROR_EP13_RESET _u(0x0) -#define USB_EP_TX_ERROR_EP13_BITS _u(0x0c000000) -#define USB_EP_TX_ERROR_EP13_MSB _u(27) -#define USB_EP_TX_ERROR_EP13_LSB _u(26) -#define USB_EP_TX_ERROR_EP13_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_TX_ERROR_EP12 -#define USB_EP_TX_ERROR_EP12_RESET _u(0x0) -#define USB_EP_TX_ERROR_EP12_BITS _u(0x03000000) -#define USB_EP_TX_ERROR_EP12_MSB _u(25) -#define USB_EP_TX_ERROR_EP12_LSB _u(24) -#define USB_EP_TX_ERROR_EP12_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_TX_ERROR_EP11 -#define USB_EP_TX_ERROR_EP11_RESET _u(0x0) -#define USB_EP_TX_ERROR_EP11_BITS _u(0x00c00000) -#define USB_EP_TX_ERROR_EP11_MSB _u(23) -#define USB_EP_TX_ERROR_EP11_LSB _u(22) -#define USB_EP_TX_ERROR_EP11_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_TX_ERROR_EP10 -#define USB_EP_TX_ERROR_EP10_RESET _u(0x0) -#define USB_EP_TX_ERROR_EP10_BITS _u(0x00300000) -#define USB_EP_TX_ERROR_EP10_MSB _u(21) -#define USB_EP_TX_ERROR_EP10_LSB _u(20) -#define USB_EP_TX_ERROR_EP10_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_TX_ERROR_EP9 -#define USB_EP_TX_ERROR_EP9_RESET _u(0x0) -#define USB_EP_TX_ERROR_EP9_BITS _u(0x000c0000) -#define USB_EP_TX_ERROR_EP9_MSB _u(19) -#define USB_EP_TX_ERROR_EP9_LSB _u(18) -#define USB_EP_TX_ERROR_EP9_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_TX_ERROR_EP8 -#define USB_EP_TX_ERROR_EP8_RESET _u(0x0) -#define USB_EP_TX_ERROR_EP8_BITS _u(0x00030000) -#define USB_EP_TX_ERROR_EP8_MSB _u(17) -#define USB_EP_TX_ERROR_EP8_LSB _u(16) -#define USB_EP_TX_ERROR_EP8_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_TX_ERROR_EP7 -#define USB_EP_TX_ERROR_EP7_RESET _u(0x0) -#define USB_EP_TX_ERROR_EP7_BITS _u(0x0000c000) -#define USB_EP_TX_ERROR_EP7_MSB _u(15) -#define USB_EP_TX_ERROR_EP7_LSB _u(14) -#define USB_EP_TX_ERROR_EP7_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_TX_ERROR_EP6 -#define USB_EP_TX_ERROR_EP6_RESET _u(0x0) -#define USB_EP_TX_ERROR_EP6_BITS _u(0x00003000) -#define USB_EP_TX_ERROR_EP6_MSB _u(13) -#define USB_EP_TX_ERROR_EP6_LSB _u(12) -#define USB_EP_TX_ERROR_EP6_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_TX_ERROR_EP5 -#define USB_EP_TX_ERROR_EP5_RESET _u(0x0) -#define USB_EP_TX_ERROR_EP5_BITS _u(0x00000c00) -#define USB_EP_TX_ERROR_EP5_MSB _u(11) -#define USB_EP_TX_ERROR_EP5_LSB _u(10) -#define USB_EP_TX_ERROR_EP5_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_TX_ERROR_EP4 -#define USB_EP_TX_ERROR_EP4_RESET _u(0x0) -#define USB_EP_TX_ERROR_EP4_BITS _u(0x00000300) -#define USB_EP_TX_ERROR_EP4_MSB _u(9) -#define USB_EP_TX_ERROR_EP4_LSB _u(8) -#define USB_EP_TX_ERROR_EP4_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_TX_ERROR_EP3 -#define USB_EP_TX_ERROR_EP3_RESET _u(0x0) -#define USB_EP_TX_ERROR_EP3_BITS _u(0x000000c0) -#define USB_EP_TX_ERROR_EP3_MSB _u(7) -#define USB_EP_TX_ERROR_EP3_LSB _u(6) -#define USB_EP_TX_ERROR_EP3_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_TX_ERROR_EP2 -#define USB_EP_TX_ERROR_EP2_RESET _u(0x0) -#define USB_EP_TX_ERROR_EP2_BITS _u(0x00000030) -#define USB_EP_TX_ERROR_EP2_MSB _u(5) -#define USB_EP_TX_ERROR_EP2_LSB _u(4) -#define USB_EP_TX_ERROR_EP2_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_TX_ERROR_EP1 -#define USB_EP_TX_ERROR_EP1_RESET _u(0x0) -#define USB_EP_TX_ERROR_EP1_BITS _u(0x0000000c) -#define USB_EP_TX_ERROR_EP1_MSB _u(3) -#define USB_EP_TX_ERROR_EP1_LSB _u(2) -#define USB_EP_TX_ERROR_EP1_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_TX_ERROR_EP0 -#define USB_EP_TX_ERROR_EP0_RESET _u(0x0) -#define USB_EP_TX_ERROR_EP0_BITS _u(0x00000003) -#define USB_EP_TX_ERROR_EP0_MSB _u(1) -#define USB_EP_TX_ERROR_EP0_LSB _u(0) -#define USB_EP_TX_ERROR_EP0_ACCESS "WC" -// ============================================================================= -// Register : USB_EP_RX_ERROR -// Description : RX error count for each endpoint. Write to each field to reset -// the counter to 0. -#define USB_EP_RX_ERROR_OFFSET _u(0x00000110) -#define USB_EP_RX_ERROR_BITS _u(0xffffffff) -#define USB_EP_RX_ERROR_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_EP_RX_ERROR_EP15_SEQ -#define USB_EP_RX_ERROR_EP15_SEQ_RESET _u(0x0) -#define USB_EP_RX_ERROR_EP15_SEQ_BITS _u(0x80000000) -#define USB_EP_RX_ERROR_EP15_SEQ_MSB _u(31) -#define USB_EP_RX_ERROR_EP15_SEQ_LSB _u(31) -#define USB_EP_RX_ERROR_EP15_SEQ_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_RX_ERROR_EP15_TRANSACTION -#define USB_EP_RX_ERROR_EP15_TRANSACTION_RESET _u(0x0) -#define USB_EP_RX_ERROR_EP15_TRANSACTION_BITS _u(0x40000000) -#define USB_EP_RX_ERROR_EP15_TRANSACTION_MSB _u(30) -#define USB_EP_RX_ERROR_EP15_TRANSACTION_LSB _u(30) -#define USB_EP_RX_ERROR_EP15_TRANSACTION_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_RX_ERROR_EP14_SEQ -#define USB_EP_RX_ERROR_EP14_SEQ_RESET _u(0x0) -#define USB_EP_RX_ERROR_EP14_SEQ_BITS _u(0x20000000) -#define USB_EP_RX_ERROR_EP14_SEQ_MSB _u(29) -#define USB_EP_RX_ERROR_EP14_SEQ_LSB _u(29) -#define USB_EP_RX_ERROR_EP14_SEQ_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_RX_ERROR_EP14_TRANSACTION -#define USB_EP_RX_ERROR_EP14_TRANSACTION_RESET _u(0x0) -#define USB_EP_RX_ERROR_EP14_TRANSACTION_BITS _u(0x10000000) -#define USB_EP_RX_ERROR_EP14_TRANSACTION_MSB _u(28) -#define USB_EP_RX_ERROR_EP14_TRANSACTION_LSB _u(28) -#define USB_EP_RX_ERROR_EP14_TRANSACTION_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_RX_ERROR_EP13_SEQ -#define USB_EP_RX_ERROR_EP13_SEQ_RESET _u(0x0) -#define USB_EP_RX_ERROR_EP13_SEQ_BITS _u(0x08000000) -#define USB_EP_RX_ERROR_EP13_SEQ_MSB _u(27) -#define USB_EP_RX_ERROR_EP13_SEQ_LSB _u(27) -#define USB_EP_RX_ERROR_EP13_SEQ_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_RX_ERROR_EP13_TRANSACTION -#define USB_EP_RX_ERROR_EP13_TRANSACTION_RESET _u(0x0) -#define USB_EP_RX_ERROR_EP13_TRANSACTION_BITS _u(0x04000000) -#define USB_EP_RX_ERROR_EP13_TRANSACTION_MSB _u(26) -#define USB_EP_RX_ERROR_EP13_TRANSACTION_LSB _u(26) -#define USB_EP_RX_ERROR_EP13_TRANSACTION_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_RX_ERROR_EP12_SEQ -#define USB_EP_RX_ERROR_EP12_SEQ_RESET _u(0x0) -#define USB_EP_RX_ERROR_EP12_SEQ_BITS _u(0x02000000) -#define USB_EP_RX_ERROR_EP12_SEQ_MSB _u(25) -#define USB_EP_RX_ERROR_EP12_SEQ_LSB _u(25) -#define USB_EP_RX_ERROR_EP12_SEQ_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_RX_ERROR_EP12_TRANSACTION -#define USB_EP_RX_ERROR_EP12_TRANSACTION_RESET _u(0x0) -#define USB_EP_RX_ERROR_EP12_TRANSACTION_BITS _u(0x01000000) -#define USB_EP_RX_ERROR_EP12_TRANSACTION_MSB _u(24) -#define USB_EP_RX_ERROR_EP12_TRANSACTION_LSB _u(24) -#define USB_EP_RX_ERROR_EP12_TRANSACTION_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_RX_ERROR_EP11_SEQ -#define USB_EP_RX_ERROR_EP11_SEQ_RESET _u(0x0) -#define USB_EP_RX_ERROR_EP11_SEQ_BITS _u(0x00800000) -#define USB_EP_RX_ERROR_EP11_SEQ_MSB _u(23) -#define USB_EP_RX_ERROR_EP11_SEQ_LSB _u(23) -#define USB_EP_RX_ERROR_EP11_SEQ_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_RX_ERROR_EP11_TRANSACTION -#define USB_EP_RX_ERROR_EP11_TRANSACTION_RESET _u(0x0) -#define USB_EP_RX_ERROR_EP11_TRANSACTION_BITS _u(0x00400000) -#define USB_EP_RX_ERROR_EP11_TRANSACTION_MSB _u(22) -#define USB_EP_RX_ERROR_EP11_TRANSACTION_LSB _u(22) -#define USB_EP_RX_ERROR_EP11_TRANSACTION_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_RX_ERROR_EP10_SEQ -#define USB_EP_RX_ERROR_EP10_SEQ_RESET _u(0x0) -#define USB_EP_RX_ERROR_EP10_SEQ_BITS _u(0x00200000) -#define USB_EP_RX_ERROR_EP10_SEQ_MSB _u(21) -#define USB_EP_RX_ERROR_EP10_SEQ_LSB _u(21) -#define USB_EP_RX_ERROR_EP10_SEQ_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_RX_ERROR_EP10_TRANSACTION -#define USB_EP_RX_ERROR_EP10_TRANSACTION_RESET _u(0x0) -#define USB_EP_RX_ERROR_EP10_TRANSACTION_BITS _u(0x00100000) -#define USB_EP_RX_ERROR_EP10_TRANSACTION_MSB _u(20) -#define USB_EP_RX_ERROR_EP10_TRANSACTION_LSB _u(20) -#define USB_EP_RX_ERROR_EP10_TRANSACTION_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_RX_ERROR_EP9_SEQ -#define USB_EP_RX_ERROR_EP9_SEQ_RESET _u(0x0) -#define USB_EP_RX_ERROR_EP9_SEQ_BITS _u(0x00080000) -#define USB_EP_RX_ERROR_EP9_SEQ_MSB _u(19) -#define USB_EP_RX_ERROR_EP9_SEQ_LSB _u(19) -#define USB_EP_RX_ERROR_EP9_SEQ_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_RX_ERROR_EP9_TRANSACTION -#define USB_EP_RX_ERROR_EP9_TRANSACTION_RESET _u(0x0) -#define USB_EP_RX_ERROR_EP9_TRANSACTION_BITS _u(0x00040000) -#define USB_EP_RX_ERROR_EP9_TRANSACTION_MSB _u(18) -#define USB_EP_RX_ERROR_EP9_TRANSACTION_LSB _u(18) -#define USB_EP_RX_ERROR_EP9_TRANSACTION_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_RX_ERROR_EP8_SEQ -#define USB_EP_RX_ERROR_EP8_SEQ_RESET _u(0x0) -#define USB_EP_RX_ERROR_EP8_SEQ_BITS _u(0x00020000) -#define USB_EP_RX_ERROR_EP8_SEQ_MSB _u(17) -#define USB_EP_RX_ERROR_EP8_SEQ_LSB _u(17) -#define USB_EP_RX_ERROR_EP8_SEQ_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_RX_ERROR_EP8_TRANSACTION -#define USB_EP_RX_ERROR_EP8_TRANSACTION_RESET _u(0x0) -#define USB_EP_RX_ERROR_EP8_TRANSACTION_BITS _u(0x00010000) -#define USB_EP_RX_ERROR_EP8_TRANSACTION_MSB _u(16) -#define USB_EP_RX_ERROR_EP8_TRANSACTION_LSB _u(16) -#define USB_EP_RX_ERROR_EP8_TRANSACTION_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_RX_ERROR_EP7_SEQ -#define USB_EP_RX_ERROR_EP7_SEQ_RESET _u(0x0) -#define USB_EP_RX_ERROR_EP7_SEQ_BITS _u(0x00008000) -#define USB_EP_RX_ERROR_EP7_SEQ_MSB _u(15) -#define USB_EP_RX_ERROR_EP7_SEQ_LSB _u(15) -#define USB_EP_RX_ERROR_EP7_SEQ_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_RX_ERROR_EP7_TRANSACTION -#define USB_EP_RX_ERROR_EP7_TRANSACTION_RESET _u(0x0) -#define USB_EP_RX_ERROR_EP7_TRANSACTION_BITS _u(0x00004000) -#define USB_EP_RX_ERROR_EP7_TRANSACTION_MSB _u(14) -#define USB_EP_RX_ERROR_EP7_TRANSACTION_LSB _u(14) -#define USB_EP_RX_ERROR_EP7_TRANSACTION_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_RX_ERROR_EP6_SEQ -#define USB_EP_RX_ERROR_EP6_SEQ_RESET _u(0x0) -#define USB_EP_RX_ERROR_EP6_SEQ_BITS _u(0x00002000) -#define USB_EP_RX_ERROR_EP6_SEQ_MSB _u(13) -#define USB_EP_RX_ERROR_EP6_SEQ_LSB _u(13) -#define USB_EP_RX_ERROR_EP6_SEQ_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_RX_ERROR_EP6_TRANSACTION -#define USB_EP_RX_ERROR_EP6_TRANSACTION_RESET _u(0x0) -#define USB_EP_RX_ERROR_EP6_TRANSACTION_BITS _u(0x00001000) -#define USB_EP_RX_ERROR_EP6_TRANSACTION_MSB _u(12) -#define USB_EP_RX_ERROR_EP6_TRANSACTION_LSB _u(12) -#define USB_EP_RX_ERROR_EP6_TRANSACTION_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_RX_ERROR_EP5_SEQ -#define USB_EP_RX_ERROR_EP5_SEQ_RESET _u(0x0) -#define USB_EP_RX_ERROR_EP5_SEQ_BITS _u(0x00000800) -#define USB_EP_RX_ERROR_EP5_SEQ_MSB _u(11) -#define USB_EP_RX_ERROR_EP5_SEQ_LSB _u(11) -#define USB_EP_RX_ERROR_EP5_SEQ_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_RX_ERROR_EP5_TRANSACTION -#define USB_EP_RX_ERROR_EP5_TRANSACTION_RESET _u(0x0) -#define USB_EP_RX_ERROR_EP5_TRANSACTION_BITS _u(0x00000400) -#define USB_EP_RX_ERROR_EP5_TRANSACTION_MSB _u(10) -#define USB_EP_RX_ERROR_EP5_TRANSACTION_LSB _u(10) -#define USB_EP_RX_ERROR_EP5_TRANSACTION_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_RX_ERROR_EP4_SEQ -#define USB_EP_RX_ERROR_EP4_SEQ_RESET _u(0x0) -#define USB_EP_RX_ERROR_EP4_SEQ_BITS _u(0x00000200) -#define USB_EP_RX_ERROR_EP4_SEQ_MSB _u(9) -#define USB_EP_RX_ERROR_EP4_SEQ_LSB _u(9) -#define USB_EP_RX_ERROR_EP4_SEQ_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_RX_ERROR_EP4_TRANSACTION -#define USB_EP_RX_ERROR_EP4_TRANSACTION_RESET _u(0x0) -#define USB_EP_RX_ERROR_EP4_TRANSACTION_BITS _u(0x00000100) -#define USB_EP_RX_ERROR_EP4_TRANSACTION_MSB _u(8) -#define USB_EP_RX_ERROR_EP4_TRANSACTION_LSB _u(8) -#define USB_EP_RX_ERROR_EP4_TRANSACTION_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_RX_ERROR_EP3_SEQ -#define USB_EP_RX_ERROR_EP3_SEQ_RESET _u(0x0) -#define USB_EP_RX_ERROR_EP3_SEQ_BITS _u(0x00000080) -#define USB_EP_RX_ERROR_EP3_SEQ_MSB _u(7) -#define USB_EP_RX_ERROR_EP3_SEQ_LSB _u(7) -#define USB_EP_RX_ERROR_EP3_SEQ_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_RX_ERROR_EP3_TRANSACTION -#define USB_EP_RX_ERROR_EP3_TRANSACTION_RESET _u(0x0) -#define USB_EP_RX_ERROR_EP3_TRANSACTION_BITS _u(0x00000040) -#define USB_EP_RX_ERROR_EP3_TRANSACTION_MSB _u(6) -#define USB_EP_RX_ERROR_EP3_TRANSACTION_LSB _u(6) -#define USB_EP_RX_ERROR_EP3_TRANSACTION_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_RX_ERROR_EP2_SEQ -#define USB_EP_RX_ERROR_EP2_SEQ_RESET _u(0x0) -#define USB_EP_RX_ERROR_EP2_SEQ_BITS _u(0x00000020) -#define USB_EP_RX_ERROR_EP2_SEQ_MSB _u(5) -#define USB_EP_RX_ERROR_EP2_SEQ_LSB _u(5) -#define USB_EP_RX_ERROR_EP2_SEQ_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_RX_ERROR_EP2_TRANSACTION -#define USB_EP_RX_ERROR_EP2_TRANSACTION_RESET _u(0x0) -#define USB_EP_RX_ERROR_EP2_TRANSACTION_BITS _u(0x00000010) -#define USB_EP_RX_ERROR_EP2_TRANSACTION_MSB _u(4) -#define USB_EP_RX_ERROR_EP2_TRANSACTION_LSB _u(4) -#define USB_EP_RX_ERROR_EP2_TRANSACTION_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_RX_ERROR_EP1_SEQ -#define USB_EP_RX_ERROR_EP1_SEQ_RESET _u(0x0) -#define USB_EP_RX_ERROR_EP1_SEQ_BITS _u(0x00000008) -#define USB_EP_RX_ERROR_EP1_SEQ_MSB _u(3) -#define USB_EP_RX_ERROR_EP1_SEQ_LSB _u(3) -#define USB_EP_RX_ERROR_EP1_SEQ_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_RX_ERROR_EP1_TRANSACTION -#define USB_EP_RX_ERROR_EP1_TRANSACTION_RESET _u(0x0) -#define USB_EP_RX_ERROR_EP1_TRANSACTION_BITS _u(0x00000004) -#define USB_EP_RX_ERROR_EP1_TRANSACTION_MSB _u(2) -#define USB_EP_RX_ERROR_EP1_TRANSACTION_LSB _u(2) -#define USB_EP_RX_ERROR_EP1_TRANSACTION_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_RX_ERROR_EP0_SEQ -#define USB_EP_RX_ERROR_EP0_SEQ_RESET _u(0x0) -#define USB_EP_RX_ERROR_EP0_SEQ_BITS _u(0x00000002) -#define USB_EP_RX_ERROR_EP0_SEQ_MSB _u(1) -#define USB_EP_RX_ERROR_EP0_SEQ_LSB _u(1) -#define USB_EP_RX_ERROR_EP0_SEQ_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_EP_RX_ERROR_EP0_TRANSACTION -#define USB_EP_RX_ERROR_EP0_TRANSACTION_RESET _u(0x0) -#define USB_EP_RX_ERROR_EP0_TRANSACTION_BITS _u(0x00000001) -#define USB_EP_RX_ERROR_EP0_TRANSACTION_MSB _u(0) -#define USB_EP_RX_ERROR_EP0_TRANSACTION_LSB _u(0) -#define USB_EP_RX_ERROR_EP0_TRANSACTION_ACCESS "WC" -// ============================================================================= -// Register : USB_DEV_SM_WATCHDOG -// Description : Watchdog that forces the device state machine to idle and -// raises an interrupt if the device stays in a state that isn't -// idle for the configured limit. The counter is reset on every -// state transition. -// Set limit while enable is low and then set the enable. -#define USB_DEV_SM_WATCHDOG_OFFSET _u(0x00000114) -#define USB_DEV_SM_WATCHDOG_BITS _u(0x001fffff) -#define USB_DEV_SM_WATCHDOG_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_DEV_SM_WATCHDOG_FIRED -#define USB_DEV_SM_WATCHDOG_FIRED_RESET _u(0x0) -#define USB_DEV_SM_WATCHDOG_FIRED_BITS _u(0x00100000) -#define USB_DEV_SM_WATCHDOG_FIRED_MSB _u(20) -#define USB_DEV_SM_WATCHDOG_FIRED_LSB _u(20) -#define USB_DEV_SM_WATCHDOG_FIRED_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : USB_DEV_SM_WATCHDOG_RESET -// Description : Set to 1 to forcibly reset the device state machine on watchdog -// expiry -#define USB_DEV_SM_WATCHDOG_RESET_RESET _u(0x0) -#define USB_DEV_SM_WATCHDOG_RESET_BITS _u(0x00080000) -#define USB_DEV_SM_WATCHDOG_RESET_MSB _u(19) -#define USB_DEV_SM_WATCHDOG_RESET_LSB _u(19) -#define USB_DEV_SM_WATCHDOG_RESET_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEV_SM_WATCHDOG_ENABLE -#define USB_DEV_SM_WATCHDOG_ENABLE_RESET _u(0x0) -#define USB_DEV_SM_WATCHDOG_ENABLE_BITS _u(0x00040000) -#define USB_DEV_SM_WATCHDOG_ENABLE_MSB _u(18) -#define USB_DEV_SM_WATCHDOG_ENABLE_LSB _u(18) -#define USB_DEV_SM_WATCHDOG_ENABLE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEV_SM_WATCHDOG_LIMIT -#define USB_DEV_SM_WATCHDOG_LIMIT_RESET _u(0x00000) -#define USB_DEV_SM_WATCHDOG_LIMIT_BITS _u(0x0003ffff) -#define USB_DEV_SM_WATCHDOG_LIMIT_MSB _u(17) -#define USB_DEV_SM_WATCHDOG_LIMIT_LSB _u(0) -#define USB_DEV_SM_WATCHDOG_LIMIT_ACCESS "RW" -// ============================================================================= -#endif // _HARDWARE_REGS_USB_H - diff --git a/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/usb_device_dpram.h b/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/usb_device_dpram.h deleted file mode 100644 index 27203f4e19..0000000000 --- a/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/usb_device_dpram.h +++ /dev/null @@ -1,6753 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -// ============================================================================= -// Register block : USB_DEVICE_DPRAM -// Version : 1 -// Bus type : ahbl -// Description : DPRAM layout for USB device. -// ============================================================================= -#ifndef _HARDWARE_REGS_USB_DEVICE_DPRAM_H -#define _HARDWARE_REGS_USB_DEVICE_DPRAM_H -// ============================================================================= -// Register : USB_DEVICE_DPRAM_SETUP_PACKET_LOW -// Description : Bytes 0-3 of the SETUP packet from the host. -#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_OFFSET _u(0x00000000) -#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BITS _u(0xffffffff) -#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_SETUP_PACKET_LOW_WVALUE -#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_WVALUE_RESET _u(0x0000) -#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_WVALUE_BITS _u(0xffff0000) -#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_WVALUE_MSB _u(31) -#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_WVALUE_LSB _u(16) -#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_WVALUE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BREQUEST -#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BREQUEST_RESET _u(0x00) -#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BREQUEST_BITS _u(0x0000ff00) -#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BREQUEST_MSB _u(15) -#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BREQUEST_LSB _u(8) -#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BREQUEST_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BMREQUESTTYPE -#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BMREQUESTTYPE_RESET _u(0x00) -#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BMREQUESTTYPE_BITS _u(0x000000ff) -#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BMREQUESTTYPE_MSB _u(7) -#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BMREQUESTTYPE_LSB _u(0) -#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BMREQUESTTYPE_ACCESS "RW" -// ============================================================================= -// Register : USB_DEVICE_DPRAM_SETUP_PACKET_HIGH -// Description : Bytes 4-7 of the setup packet from the host. -#define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_OFFSET _u(0x00000004) -#define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_BITS _u(0xffffffff) -#define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_WLENGTH -#define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_WLENGTH_RESET _u(0x0000) -#define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_WLENGTH_BITS _u(0xffff0000) -#define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_WLENGTH_MSB _u(31) -#define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_WLENGTH_LSB _u(16) -#define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_WLENGTH_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_WINDEX -#define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_WINDEX_RESET _u(0x0000) -#define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_WINDEX_BITS _u(0x0000ffff) -#define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_WINDEX_MSB _u(15) -#define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_WINDEX_LSB _u(0) -#define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_WINDEX_ACCESS "RW" -// ============================================================================= -// Register : USB_DEVICE_DPRAM_EP1_IN_CONTROL -#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_OFFSET _u(0x00000008) -#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_BITS _u(0xfc03ffff) -#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENABLE -// Description : Enable this endpoint. The device will not reply to any packets -// for this endpoint if this bit is not set. -#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENABLE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENABLE_BITS _u(0x80000000) -#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENABLE_MSB _u(31) -#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENABLE_LSB _u(31) -#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENABLE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP1_IN_CONTROL_DOUBLE_BUFFERED -// Description : This endpoint is double buffered. -#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) -#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_DOUBLE_BUFFERED_MSB _u(30) -#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_DOUBLE_BUFFERED_LSB _u(30) -#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_PER_BUFF -// Description : Trigger an interrupt each time a buffer is done. -#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) -#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) -#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) -#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF -// Description : Trigger an interrupt each time both buffers are done. Only -// valid in double buffered mode. -#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) -#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) -#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) -#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE -// 0x0 -> Control -// 0x1 -> Isochronous -// 0x2 -> Bulk -// 0x3 -> Interrupt -#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) -#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) -#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) -#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) -#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) -#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) -#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_ON_STALL -// Description : Trigger an interrupt if a STALL is sent. Intended for debug -// only. -#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) -#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) -#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) -#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_ON_NAK -// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. -#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) -#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) -#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) -#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP1_IN_CONTROL_BUFFER_ADDRESS -// Description : 64 byte aligned buffer address for this EP (bits 0-5 are -// ignored). Relative to the start of the DPRAM. -#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) -#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) -#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_BUFFER_ADDRESS_MSB _u(15) -#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_BUFFER_ADDRESS_LSB _u(0) -#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW" -// ============================================================================= -// Register : USB_DEVICE_DPRAM_EP1_OUT_CONTROL -#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_OFFSET _u(0x0000000c) -#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_BITS _u(0xfc03ffff) -#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENABLE -// Description : Enable this endpoint. The device will not reply to any packets -// for this endpoint if this bit is not set. -#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENABLE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENABLE_BITS _u(0x80000000) -#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENABLE_MSB _u(31) -#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENABLE_LSB _u(31) -#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENABLE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP1_OUT_CONTROL_DOUBLE_BUFFERED -// Description : This endpoint is double buffered. -#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) -#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_DOUBLE_BUFFERED_MSB _u(30) -#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_DOUBLE_BUFFERED_LSB _u(30) -#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_PER_BUFF -// Description : Trigger an interrupt each time a buffer is done. -#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) -#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) -#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) -#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF -// Description : Trigger an interrupt each time both buffers are done. Only -// valid in double buffered mode. -#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) -#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) -#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) -#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE -// 0x0 -> Control -// 0x1 -> Isochronous -// 0x2 -> Bulk -// 0x3 -> Interrupt -#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) -#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) -#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) -#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) -#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) -#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) -#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_ON_STALL -// Description : Trigger an interrupt if a STALL is sent. Intended for debug -// only. -#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) -#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) -#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) -#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_ON_NAK -// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. -#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) -#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) -#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) -#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP1_OUT_CONTROL_BUFFER_ADDRESS -// Description : 64 byte aligned buffer address for this EP (bits 0-5 are -// ignored). Relative to the start of the DPRAM. -#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) -#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) -#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_BUFFER_ADDRESS_MSB _u(15) -#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_BUFFER_ADDRESS_LSB _u(0) -#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW" -// ============================================================================= -// Register : USB_DEVICE_DPRAM_EP2_IN_CONTROL -#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_OFFSET _u(0x00000010) -#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_BITS _u(0xfc03ffff) -#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENABLE -// Description : Enable this endpoint. The device will not reply to any packets -// for this endpoint if this bit is not set. -#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENABLE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENABLE_BITS _u(0x80000000) -#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENABLE_MSB _u(31) -#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENABLE_LSB _u(31) -#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENABLE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP2_IN_CONTROL_DOUBLE_BUFFERED -// Description : This endpoint is double buffered. -#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) -#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_DOUBLE_BUFFERED_MSB _u(30) -#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_DOUBLE_BUFFERED_LSB _u(30) -#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_PER_BUFF -// Description : Trigger an interrupt each time a buffer is done. -#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) -#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) -#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) -#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF -// Description : Trigger an interrupt each time both buffers are done. Only -// valid in double buffered mode. -#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) -#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) -#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) -#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE -// 0x0 -> Control -// 0x1 -> Isochronous -// 0x2 -> Bulk -// 0x3 -> Interrupt -#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) -#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) -#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) -#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) -#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) -#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) -#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_ON_STALL -// Description : Trigger an interrupt if a STALL is sent. Intended for debug -// only. -#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) -#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) -#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) -#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_ON_NAK -// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. -#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) -#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) -#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) -#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP2_IN_CONTROL_BUFFER_ADDRESS -// Description : 64 byte aligned buffer address for this EP (bits 0-5 are -// ignored). Relative to the start of the DPRAM. -#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) -#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) -#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_BUFFER_ADDRESS_MSB _u(15) -#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_BUFFER_ADDRESS_LSB _u(0) -#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW" -// ============================================================================= -// Register : USB_DEVICE_DPRAM_EP2_OUT_CONTROL -#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_OFFSET _u(0x00000014) -#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_BITS _u(0xfc03ffff) -#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENABLE -// Description : Enable this endpoint. The device will not reply to any packets -// for this endpoint if this bit is not set. -#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENABLE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENABLE_BITS _u(0x80000000) -#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENABLE_MSB _u(31) -#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENABLE_LSB _u(31) -#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENABLE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP2_OUT_CONTROL_DOUBLE_BUFFERED -// Description : This endpoint is double buffered. -#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) -#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_DOUBLE_BUFFERED_MSB _u(30) -#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_DOUBLE_BUFFERED_LSB _u(30) -#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_PER_BUFF -// Description : Trigger an interrupt each time a buffer is done. -#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) -#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) -#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) -#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF -// Description : Trigger an interrupt each time both buffers are done. Only -// valid in double buffered mode. -#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) -#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) -#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) -#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE -// 0x0 -> Control -// 0x1 -> Isochronous -// 0x2 -> Bulk -// 0x3 -> Interrupt -#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) -#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) -#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) -#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) -#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) -#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) -#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_ON_STALL -// Description : Trigger an interrupt if a STALL is sent. Intended for debug -// only. -#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) -#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) -#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) -#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_ON_NAK -// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. -#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) -#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) -#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) -#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP2_OUT_CONTROL_BUFFER_ADDRESS -// Description : 64 byte aligned buffer address for this EP (bits 0-5 are -// ignored). Relative to the start of the DPRAM. -#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) -#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) -#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_BUFFER_ADDRESS_MSB _u(15) -#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_BUFFER_ADDRESS_LSB _u(0) -#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW" -// ============================================================================= -// Register : USB_DEVICE_DPRAM_EP3_IN_CONTROL -#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_OFFSET _u(0x00000018) -#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_BITS _u(0xfc03ffff) -#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENABLE -// Description : Enable this endpoint. The device will not reply to any packets -// for this endpoint if this bit is not set. -#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENABLE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENABLE_BITS _u(0x80000000) -#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENABLE_MSB _u(31) -#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENABLE_LSB _u(31) -#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENABLE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP3_IN_CONTROL_DOUBLE_BUFFERED -// Description : This endpoint is double buffered. -#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) -#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_DOUBLE_BUFFERED_MSB _u(30) -#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_DOUBLE_BUFFERED_LSB _u(30) -#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_PER_BUFF -// Description : Trigger an interrupt each time a buffer is done. -#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) -#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) -#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) -#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF -// Description : Trigger an interrupt each time both buffers are done. Only -// valid in double buffered mode. -#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) -#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) -#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) -#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE -// 0x0 -> Control -// 0x1 -> Isochronous -// 0x2 -> Bulk -// 0x3 -> Interrupt -#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) -#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) -#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) -#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) -#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) -#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) -#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_ON_STALL -// Description : Trigger an interrupt if a STALL is sent. Intended for debug -// only. -#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) -#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) -#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) -#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_ON_NAK -// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. -#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) -#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) -#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) -#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP3_IN_CONTROL_BUFFER_ADDRESS -// Description : 64 byte aligned buffer address for this EP (bits 0-5 are -// ignored). Relative to the start of the DPRAM. -#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) -#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) -#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_BUFFER_ADDRESS_MSB _u(15) -#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_BUFFER_ADDRESS_LSB _u(0) -#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW" -// ============================================================================= -// Register : USB_DEVICE_DPRAM_EP3_OUT_CONTROL -#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_OFFSET _u(0x0000001c) -#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_BITS _u(0xfc03ffff) -#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENABLE -// Description : Enable this endpoint. The device will not reply to any packets -// for this endpoint if this bit is not set. -#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENABLE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENABLE_BITS _u(0x80000000) -#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENABLE_MSB _u(31) -#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENABLE_LSB _u(31) -#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENABLE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP3_OUT_CONTROL_DOUBLE_BUFFERED -// Description : This endpoint is double buffered. -#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) -#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_DOUBLE_BUFFERED_MSB _u(30) -#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_DOUBLE_BUFFERED_LSB _u(30) -#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_PER_BUFF -// Description : Trigger an interrupt each time a buffer is done. -#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) -#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) -#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) -#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF -// Description : Trigger an interrupt each time both buffers are done. Only -// valid in double buffered mode. -#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) -#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) -#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) -#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE -// 0x0 -> Control -// 0x1 -> Isochronous -// 0x2 -> Bulk -// 0x3 -> Interrupt -#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) -#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) -#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) -#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) -#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) -#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) -#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_ON_STALL -// Description : Trigger an interrupt if a STALL is sent. Intended for debug -// only. -#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) -#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) -#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) -#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_ON_NAK -// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. -#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) -#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) -#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) -#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP3_OUT_CONTROL_BUFFER_ADDRESS -// Description : 64 byte aligned buffer address for this EP (bits 0-5 are -// ignored). Relative to the start of the DPRAM. -#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) -#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) -#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_BUFFER_ADDRESS_MSB _u(15) -#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_BUFFER_ADDRESS_LSB _u(0) -#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW" -// ============================================================================= -// Register : USB_DEVICE_DPRAM_EP4_IN_CONTROL -#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_OFFSET _u(0x00000020) -#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_BITS _u(0xfc03ffff) -#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENABLE -// Description : Enable this endpoint. The device will not reply to any packets -// for this endpoint if this bit is not set. -#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENABLE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENABLE_BITS _u(0x80000000) -#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENABLE_MSB _u(31) -#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENABLE_LSB _u(31) -#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENABLE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP4_IN_CONTROL_DOUBLE_BUFFERED -// Description : This endpoint is double buffered. -#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) -#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_DOUBLE_BUFFERED_MSB _u(30) -#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_DOUBLE_BUFFERED_LSB _u(30) -#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_PER_BUFF -// Description : Trigger an interrupt each time a buffer is done. -#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) -#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) -#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) -#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF -// Description : Trigger an interrupt each time both buffers are done. Only -// valid in double buffered mode. -#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) -#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) -#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) -#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE -// 0x0 -> Control -// 0x1 -> Isochronous -// 0x2 -> Bulk -// 0x3 -> Interrupt -#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) -#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) -#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) -#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) -#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) -#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) -#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_ON_STALL -// Description : Trigger an interrupt if a STALL is sent. Intended for debug -// only. -#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) -#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) -#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) -#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_ON_NAK -// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. -#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) -#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) -#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) -#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP4_IN_CONTROL_BUFFER_ADDRESS -// Description : 64 byte aligned buffer address for this EP (bits 0-5 are -// ignored). Relative to the start of the DPRAM. -#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) -#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) -#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_BUFFER_ADDRESS_MSB _u(15) -#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_BUFFER_ADDRESS_LSB _u(0) -#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW" -// ============================================================================= -// Register : USB_DEVICE_DPRAM_EP4_OUT_CONTROL -#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_OFFSET _u(0x00000024) -#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_BITS _u(0xfc03ffff) -#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENABLE -// Description : Enable this endpoint. The device will not reply to any packets -// for this endpoint if this bit is not set. -#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENABLE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENABLE_BITS _u(0x80000000) -#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENABLE_MSB _u(31) -#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENABLE_LSB _u(31) -#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENABLE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP4_OUT_CONTROL_DOUBLE_BUFFERED -// Description : This endpoint is double buffered. -#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) -#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_DOUBLE_BUFFERED_MSB _u(30) -#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_DOUBLE_BUFFERED_LSB _u(30) -#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_PER_BUFF -// Description : Trigger an interrupt each time a buffer is done. -#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) -#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) -#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) -#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF -// Description : Trigger an interrupt each time both buffers are done. Only -// valid in double buffered mode. -#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) -#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) -#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) -#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE -// 0x0 -> Control -// 0x1 -> Isochronous -// 0x2 -> Bulk -// 0x3 -> Interrupt -#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) -#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) -#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) -#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) -#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) -#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) -#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_ON_STALL -// Description : Trigger an interrupt if a STALL is sent. Intended for debug -// only. -#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) -#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) -#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) -#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_ON_NAK -// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. -#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) -#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) -#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) -#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP4_OUT_CONTROL_BUFFER_ADDRESS -// Description : 64 byte aligned buffer address for this EP (bits 0-5 are -// ignored). Relative to the start of the DPRAM. -#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) -#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) -#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_BUFFER_ADDRESS_MSB _u(15) -#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_BUFFER_ADDRESS_LSB _u(0) -#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW" -// ============================================================================= -// Register : USB_DEVICE_DPRAM_EP5_IN_CONTROL -#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_OFFSET _u(0x00000028) -#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_BITS _u(0xfc03ffff) -#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENABLE -// Description : Enable this endpoint. The device will not reply to any packets -// for this endpoint if this bit is not set. -#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENABLE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENABLE_BITS _u(0x80000000) -#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENABLE_MSB _u(31) -#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENABLE_LSB _u(31) -#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENABLE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP5_IN_CONTROL_DOUBLE_BUFFERED -// Description : This endpoint is double buffered. -#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) -#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_DOUBLE_BUFFERED_MSB _u(30) -#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_DOUBLE_BUFFERED_LSB _u(30) -#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_PER_BUFF -// Description : Trigger an interrupt each time a buffer is done. -#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) -#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) -#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) -#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF -// Description : Trigger an interrupt each time both buffers are done. Only -// valid in double buffered mode. -#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) -#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) -#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) -#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE -// 0x0 -> Control -// 0x1 -> Isochronous -// 0x2 -> Bulk -// 0x3 -> Interrupt -#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) -#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) -#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) -#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) -#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) -#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) -#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_ON_STALL -// Description : Trigger an interrupt if a STALL is sent. Intended for debug -// only. -#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) -#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) -#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) -#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_ON_NAK -// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. -#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) -#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) -#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) -#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP5_IN_CONTROL_BUFFER_ADDRESS -// Description : 64 byte aligned buffer address for this EP (bits 0-5 are -// ignored). Relative to the start of the DPRAM. -#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) -#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) -#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_BUFFER_ADDRESS_MSB _u(15) -#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_BUFFER_ADDRESS_LSB _u(0) -#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW" -// ============================================================================= -// Register : USB_DEVICE_DPRAM_EP5_OUT_CONTROL -#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_OFFSET _u(0x0000002c) -#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_BITS _u(0xfc03ffff) -#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENABLE -// Description : Enable this endpoint. The device will not reply to any packets -// for this endpoint if this bit is not set. -#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENABLE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENABLE_BITS _u(0x80000000) -#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENABLE_MSB _u(31) -#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENABLE_LSB _u(31) -#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENABLE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP5_OUT_CONTROL_DOUBLE_BUFFERED -// Description : This endpoint is double buffered. -#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) -#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_DOUBLE_BUFFERED_MSB _u(30) -#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_DOUBLE_BUFFERED_LSB _u(30) -#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_PER_BUFF -// Description : Trigger an interrupt each time a buffer is done. -#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) -#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) -#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) -#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF -// Description : Trigger an interrupt each time both buffers are done. Only -// valid in double buffered mode. -#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) -#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) -#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) -#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE -// 0x0 -> Control -// 0x1 -> Isochronous -// 0x2 -> Bulk -// 0x3 -> Interrupt -#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) -#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) -#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) -#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) -#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) -#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) -#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_ON_STALL -// Description : Trigger an interrupt if a STALL is sent. Intended for debug -// only. -#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) -#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) -#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) -#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_ON_NAK -// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. -#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) -#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) -#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) -#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP5_OUT_CONTROL_BUFFER_ADDRESS -// Description : 64 byte aligned buffer address for this EP (bits 0-5 are -// ignored). Relative to the start of the DPRAM. -#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) -#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) -#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_BUFFER_ADDRESS_MSB _u(15) -#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_BUFFER_ADDRESS_LSB _u(0) -#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW" -// ============================================================================= -// Register : USB_DEVICE_DPRAM_EP6_IN_CONTROL -#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_OFFSET _u(0x00000030) -#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_BITS _u(0xfc03ffff) -#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENABLE -// Description : Enable this endpoint. The device will not reply to any packets -// for this endpoint if this bit is not set. -#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENABLE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENABLE_BITS _u(0x80000000) -#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENABLE_MSB _u(31) -#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENABLE_LSB _u(31) -#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENABLE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP6_IN_CONTROL_DOUBLE_BUFFERED -// Description : This endpoint is double buffered. -#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) -#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_DOUBLE_BUFFERED_MSB _u(30) -#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_DOUBLE_BUFFERED_LSB _u(30) -#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_PER_BUFF -// Description : Trigger an interrupt each time a buffer is done. -#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) -#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) -#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) -#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF -// Description : Trigger an interrupt each time both buffers are done. Only -// valid in double buffered mode. -#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) -#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) -#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) -#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE -// 0x0 -> Control -// 0x1 -> Isochronous -// 0x2 -> Bulk -// 0x3 -> Interrupt -#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) -#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) -#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) -#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) -#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) -#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) -#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_ON_STALL -// Description : Trigger an interrupt if a STALL is sent. Intended for debug -// only. -#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) -#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) -#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) -#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_ON_NAK -// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. -#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) -#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) -#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) -#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP6_IN_CONTROL_BUFFER_ADDRESS -// Description : 64 byte aligned buffer address for this EP (bits 0-5 are -// ignored). Relative to the start of the DPRAM. -#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) -#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) -#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_BUFFER_ADDRESS_MSB _u(15) -#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_BUFFER_ADDRESS_LSB _u(0) -#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW" -// ============================================================================= -// Register : USB_DEVICE_DPRAM_EP6_OUT_CONTROL -#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_OFFSET _u(0x00000034) -#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_BITS _u(0xfc03ffff) -#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENABLE -// Description : Enable this endpoint. The device will not reply to any packets -// for this endpoint if this bit is not set. -#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENABLE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENABLE_BITS _u(0x80000000) -#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENABLE_MSB _u(31) -#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENABLE_LSB _u(31) -#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENABLE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP6_OUT_CONTROL_DOUBLE_BUFFERED -// Description : This endpoint is double buffered. -#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) -#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_DOUBLE_BUFFERED_MSB _u(30) -#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_DOUBLE_BUFFERED_LSB _u(30) -#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_PER_BUFF -// Description : Trigger an interrupt each time a buffer is done. -#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) -#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) -#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) -#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF -// Description : Trigger an interrupt each time both buffers are done. Only -// valid in double buffered mode. -#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) -#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) -#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) -#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE -// 0x0 -> Control -// 0x1 -> Isochronous -// 0x2 -> Bulk -// 0x3 -> Interrupt -#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) -#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) -#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) -#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) -#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) -#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) -#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_ON_STALL -// Description : Trigger an interrupt if a STALL is sent. Intended for debug -// only. -#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) -#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) -#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) -#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_ON_NAK -// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. -#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) -#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) -#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) -#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP6_OUT_CONTROL_BUFFER_ADDRESS -// Description : 64 byte aligned buffer address for this EP (bits 0-5 are -// ignored). Relative to the start of the DPRAM. -#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) -#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) -#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_BUFFER_ADDRESS_MSB _u(15) -#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_BUFFER_ADDRESS_LSB _u(0) -#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW" -// ============================================================================= -// Register : USB_DEVICE_DPRAM_EP7_IN_CONTROL -#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_OFFSET _u(0x00000038) -#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_BITS _u(0xfc03ffff) -#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENABLE -// Description : Enable this endpoint. The device will not reply to any packets -// for this endpoint if this bit is not set. -#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENABLE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENABLE_BITS _u(0x80000000) -#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENABLE_MSB _u(31) -#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENABLE_LSB _u(31) -#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENABLE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP7_IN_CONTROL_DOUBLE_BUFFERED -// Description : This endpoint is double buffered. -#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) -#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_DOUBLE_BUFFERED_MSB _u(30) -#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_DOUBLE_BUFFERED_LSB _u(30) -#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_PER_BUFF -// Description : Trigger an interrupt each time a buffer is done. -#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) -#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) -#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) -#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF -// Description : Trigger an interrupt each time both buffers are done. Only -// valid in double buffered mode. -#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) -#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) -#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) -#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE -// 0x0 -> Control -// 0x1 -> Isochronous -// 0x2 -> Bulk -// 0x3 -> Interrupt -#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) -#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) -#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) -#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) -#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) -#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) -#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_ON_STALL -// Description : Trigger an interrupt if a STALL is sent. Intended for debug -// only. -#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) -#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) -#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) -#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_ON_NAK -// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. -#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) -#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) -#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) -#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP7_IN_CONTROL_BUFFER_ADDRESS -// Description : 64 byte aligned buffer address for this EP (bits 0-5 are -// ignored). Relative to the start of the DPRAM. -#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) -#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) -#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_BUFFER_ADDRESS_MSB _u(15) -#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_BUFFER_ADDRESS_LSB _u(0) -#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW" -// ============================================================================= -// Register : USB_DEVICE_DPRAM_EP7_OUT_CONTROL -#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_OFFSET _u(0x0000003c) -#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_BITS _u(0xfc03ffff) -#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENABLE -// Description : Enable this endpoint. The device will not reply to any packets -// for this endpoint if this bit is not set. -#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENABLE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENABLE_BITS _u(0x80000000) -#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENABLE_MSB _u(31) -#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENABLE_LSB _u(31) -#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENABLE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP7_OUT_CONTROL_DOUBLE_BUFFERED -// Description : This endpoint is double buffered. -#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) -#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_DOUBLE_BUFFERED_MSB _u(30) -#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_DOUBLE_BUFFERED_LSB _u(30) -#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_PER_BUFF -// Description : Trigger an interrupt each time a buffer is done. -#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) -#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) -#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) -#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF -// Description : Trigger an interrupt each time both buffers are done. Only -// valid in double buffered mode. -#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) -#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) -#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) -#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE -// 0x0 -> Control -// 0x1 -> Isochronous -// 0x2 -> Bulk -// 0x3 -> Interrupt -#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) -#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) -#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) -#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) -#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) -#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) -#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_ON_STALL -// Description : Trigger an interrupt if a STALL is sent. Intended for debug -// only. -#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) -#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) -#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) -#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_ON_NAK -// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. -#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) -#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) -#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) -#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP7_OUT_CONTROL_BUFFER_ADDRESS -// Description : 64 byte aligned buffer address for this EP (bits 0-5 are -// ignored). Relative to the start of the DPRAM. -#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) -#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) -#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_BUFFER_ADDRESS_MSB _u(15) -#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_BUFFER_ADDRESS_LSB _u(0) -#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW" -// ============================================================================= -// Register : USB_DEVICE_DPRAM_EP8_IN_CONTROL -#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_OFFSET _u(0x00000040) -#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_BITS _u(0xfc03ffff) -#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENABLE -// Description : Enable this endpoint. The device will not reply to any packets -// for this endpoint if this bit is not set. -#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENABLE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENABLE_BITS _u(0x80000000) -#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENABLE_MSB _u(31) -#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENABLE_LSB _u(31) -#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENABLE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP8_IN_CONTROL_DOUBLE_BUFFERED -// Description : This endpoint is double buffered. -#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) -#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_DOUBLE_BUFFERED_MSB _u(30) -#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_DOUBLE_BUFFERED_LSB _u(30) -#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_PER_BUFF -// Description : Trigger an interrupt each time a buffer is done. -#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) -#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) -#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) -#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF -// Description : Trigger an interrupt each time both buffers are done. Only -// valid in double buffered mode. -#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) -#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) -#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) -#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE -// 0x0 -> Control -// 0x1 -> Isochronous -// 0x2 -> Bulk -// 0x3 -> Interrupt -#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) -#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) -#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) -#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) -#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) -#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) -#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_ON_STALL -// Description : Trigger an interrupt if a STALL is sent. Intended for debug -// only. -#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) -#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) -#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) -#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_ON_NAK -// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. -#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) -#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) -#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) -#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP8_IN_CONTROL_BUFFER_ADDRESS -// Description : 64 byte aligned buffer address for this EP (bits 0-5 are -// ignored). Relative to the start of the DPRAM. -#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) -#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) -#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_BUFFER_ADDRESS_MSB _u(15) -#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_BUFFER_ADDRESS_LSB _u(0) -#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW" -// ============================================================================= -// Register : USB_DEVICE_DPRAM_EP8_OUT_CONTROL -#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_OFFSET _u(0x00000044) -#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_BITS _u(0xfc03ffff) -#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENABLE -// Description : Enable this endpoint. The device will not reply to any packets -// for this endpoint if this bit is not set. -#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENABLE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENABLE_BITS _u(0x80000000) -#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENABLE_MSB _u(31) -#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENABLE_LSB _u(31) -#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENABLE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP8_OUT_CONTROL_DOUBLE_BUFFERED -// Description : This endpoint is double buffered. -#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) -#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_DOUBLE_BUFFERED_MSB _u(30) -#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_DOUBLE_BUFFERED_LSB _u(30) -#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_PER_BUFF -// Description : Trigger an interrupt each time a buffer is done. -#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) -#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) -#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) -#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF -// Description : Trigger an interrupt each time both buffers are done. Only -// valid in double buffered mode. -#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) -#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) -#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) -#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE -// 0x0 -> Control -// 0x1 -> Isochronous -// 0x2 -> Bulk -// 0x3 -> Interrupt -#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) -#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) -#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) -#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) -#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) -#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) -#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_ON_STALL -// Description : Trigger an interrupt if a STALL is sent. Intended for debug -// only. -#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) -#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) -#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) -#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_ON_NAK -// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. -#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) -#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) -#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) -#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP8_OUT_CONTROL_BUFFER_ADDRESS -// Description : 64 byte aligned buffer address for this EP (bits 0-5 are -// ignored). Relative to the start of the DPRAM. -#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) -#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) -#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_BUFFER_ADDRESS_MSB _u(15) -#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_BUFFER_ADDRESS_LSB _u(0) -#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW" -// ============================================================================= -// Register : USB_DEVICE_DPRAM_EP9_IN_CONTROL -#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_OFFSET _u(0x00000048) -#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_BITS _u(0xfc03ffff) -#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENABLE -// Description : Enable this endpoint. The device will not reply to any packets -// for this endpoint if this bit is not set. -#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENABLE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENABLE_BITS _u(0x80000000) -#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENABLE_MSB _u(31) -#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENABLE_LSB _u(31) -#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENABLE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP9_IN_CONTROL_DOUBLE_BUFFERED -// Description : This endpoint is double buffered. -#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) -#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_DOUBLE_BUFFERED_MSB _u(30) -#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_DOUBLE_BUFFERED_LSB _u(30) -#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_PER_BUFF -// Description : Trigger an interrupt each time a buffer is done. -#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) -#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) -#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) -#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF -// Description : Trigger an interrupt each time both buffers are done. Only -// valid in double buffered mode. -#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) -#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) -#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) -#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE -// 0x0 -> Control -// 0x1 -> Isochronous -// 0x2 -> Bulk -// 0x3 -> Interrupt -#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) -#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) -#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) -#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) -#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) -#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) -#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_ON_STALL -// Description : Trigger an interrupt if a STALL is sent. Intended for debug -// only. -#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) -#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) -#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) -#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_ON_NAK -// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. -#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) -#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) -#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) -#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP9_IN_CONTROL_BUFFER_ADDRESS -// Description : 64 byte aligned buffer address for this EP (bits 0-5 are -// ignored). Relative to the start of the DPRAM. -#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) -#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) -#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_BUFFER_ADDRESS_MSB _u(15) -#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_BUFFER_ADDRESS_LSB _u(0) -#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW" -// ============================================================================= -// Register : USB_DEVICE_DPRAM_EP9_OUT_CONTROL -#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_OFFSET _u(0x0000004c) -#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_BITS _u(0xfc03ffff) -#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENABLE -// Description : Enable this endpoint. The device will not reply to any packets -// for this endpoint if this bit is not set. -#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENABLE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENABLE_BITS _u(0x80000000) -#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENABLE_MSB _u(31) -#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENABLE_LSB _u(31) -#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENABLE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP9_OUT_CONTROL_DOUBLE_BUFFERED -// Description : This endpoint is double buffered. -#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) -#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_DOUBLE_BUFFERED_MSB _u(30) -#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_DOUBLE_BUFFERED_LSB _u(30) -#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_PER_BUFF -// Description : Trigger an interrupt each time a buffer is done. -#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) -#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) -#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) -#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF -// Description : Trigger an interrupt each time both buffers are done. Only -// valid in double buffered mode. -#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) -#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) -#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) -#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE -// 0x0 -> Control -// 0x1 -> Isochronous -// 0x2 -> Bulk -// 0x3 -> Interrupt -#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) -#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) -#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) -#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) -#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) -#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) -#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_ON_STALL -// Description : Trigger an interrupt if a STALL is sent. Intended for debug -// only. -#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) -#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) -#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) -#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_ON_NAK -// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. -#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) -#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) -#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) -#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP9_OUT_CONTROL_BUFFER_ADDRESS -// Description : 64 byte aligned buffer address for this EP (bits 0-5 are -// ignored). Relative to the start of the DPRAM. -#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) -#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) -#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_BUFFER_ADDRESS_MSB _u(15) -#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_BUFFER_ADDRESS_LSB _u(0) -#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW" -// ============================================================================= -// Register : USB_DEVICE_DPRAM_EP10_IN_CONTROL -#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_OFFSET _u(0x00000050) -#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_BITS _u(0xfc03ffff) -#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENABLE -// Description : Enable this endpoint. The device will not reply to any packets -// for this endpoint if this bit is not set. -#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENABLE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENABLE_BITS _u(0x80000000) -#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENABLE_MSB _u(31) -#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENABLE_LSB _u(31) -#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENABLE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP10_IN_CONTROL_DOUBLE_BUFFERED -// Description : This endpoint is double buffered. -#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) -#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_DOUBLE_BUFFERED_MSB _u(30) -#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_DOUBLE_BUFFERED_LSB _u(30) -#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_PER_BUFF -// Description : Trigger an interrupt each time a buffer is done. -#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) -#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) -#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) -#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF -// Description : Trigger an interrupt each time both buffers are done. Only -// valid in double buffered mode. -#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) -#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) -#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) -#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE -// 0x0 -> Control -// 0x1 -> Isochronous -// 0x2 -> Bulk -// 0x3 -> Interrupt -#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) -#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) -#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) -#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) -#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) -#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) -#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_ON_STALL -// Description : Trigger an interrupt if a STALL is sent. Intended for debug -// only. -#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) -#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) -#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) -#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_ON_NAK -// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. -#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) -#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) -#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) -#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP10_IN_CONTROL_BUFFER_ADDRESS -// Description : 64 byte aligned buffer address for this EP (bits 0-5 are -// ignored). Relative to the start of the DPRAM. -#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) -#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) -#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_BUFFER_ADDRESS_MSB _u(15) -#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_BUFFER_ADDRESS_LSB _u(0) -#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW" -// ============================================================================= -// Register : USB_DEVICE_DPRAM_EP10_OUT_CONTROL -#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_OFFSET _u(0x00000054) -#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_BITS _u(0xfc03ffff) -#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENABLE -// Description : Enable this endpoint. The device will not reply to any packets -// for this endpoint if this bit is not set. -#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENABLE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENABLE_BITS _u(0x80000000) -#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENABLE_MSB _u(31) -#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENABLE_LSB _u(31) -#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENABLE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP10_OUT_CONTROL_DOUBLE_BUFFERED -// Description : This endpoint is double buffered. -#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) -#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_DOUBLE_BUFFERED_MSB _u(30) -#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_DOUBLE_BUFFERED_LSB _u(30) -#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_PER_BUFF -// Description : Trigger an interrupt each time a buffer is done. -#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) -#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) -#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) -#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF -// Description : Trigger an interrupt each time both buffers are done. Only -// valid in double buffered mode. -#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) -#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) -#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) -#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE -// 0x0 -> Control -// 0x1 -> Isochronous -// 0x2 -> Bulk -// 0x3 -> Interrupt -#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) -#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) -#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) -#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) -#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) -#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) -#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_ON_STALL -// Description : Trigger an interrupt if a STALL is sent. Intended for debug -// only. -#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) -#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) -#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) -#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_ON_NAK -// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. -#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) -#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) -#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) -#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP10_OUT_CONTROL_BUFFER_ADDRESS -// Description : 64 byte aligned buffer address for this EP (bits 0-5 are -// ignored). Relative to the start of the DPRAM. -#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) -#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) -#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_BUFFER_ADDRESS_MSB _u(15) -#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_BUFFER_ADDRESS_LSB _u(0) -#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW" -// ============================================================================= -// Register : USB_DEVICE_DPRAM_EP11_IN_CONTROL -#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_OFFSET _u(0x00000058) -#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_BITS _u(0xfc03ffff) -#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENABLE -// Description : Enable this endpoint. The device will not reply to any packets -// for this endpoint if this bit is not set. -#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENABLE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENABLE_BITS _u(0x80000000) -#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENABLE_MSB _u(31) -#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENABLE_LSB _u(31) -#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENABLE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP11_IN_CONTROL_DOUBLE_BUFFERED -// Description : This endpoint is double buffered. -#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) -#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_DOUBLE_BUFFERED_MSB _u(30) -#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_DOUBLE_BUFFERED_LSB _u(30) -#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_PER_BUFF -// Description : Trigger an interrupt each time a buffer is done. -#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) -#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) -#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) -#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF -// Description : Trigger an interrupt each time both buffers are done. Only -// valid in double buffered mode. -#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) -#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) -#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) -#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE -// 0x0 -> Control -// 0x1 -> Isochronous -// 0x2 -> Bulk -// 0x3 -> Interrupt -#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) -#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) -#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) -#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) -#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) -#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) -#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_ON_STALL -// Description : Trigger an interrupt if a STALL is sent. Intended for debug -// only. -#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) -#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) -#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) -#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_ON_NAK -// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. -#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) -#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) -#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) -#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP11_IN_CONTROL_BUFFER_ADDRESS -// Description : 64 byte aligned buffer address for this EP (bits 0-5 are -// ignored). Relative to the start of the DPRAM. -#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) -#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) -#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_BUFFER_ADDRESS_MSB _u(15) -#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_BUFFER_ADDRESS_LSB _u(0) -#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW" -// ============================================================================= -// Register : USB_DEVICE_DPRAM_EP11_OUT_CONTROL -#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_OFFSET _u(0x0000005c) -#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_BITS _u(0xfc03ffff) -#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENABLE -// Description : Enable this endpoint. The device will not reply to any packets -// for this endpoint if this bit is not set. -#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENABLE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENABLE_BITS _u(0x80000000) -#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENABLE_MSB _u(31) -#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENABLE_LSB _u(31) -#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENABLE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP11_OUT_CONTROL_DOUBLE_BUFFERED -// Description : This endpoint is double buffered. -#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) -#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_DOUBLE_BUFFERED_MSB _u(30) -#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_DOUBLE_BUFFERED_LSB _u(30) -#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_PER_BUFF -// Description : Trigger an interrupt each time a buffer is done. -#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) -#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) -#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) -#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF -// Description : Trigger an interrupt each time both buffers are done. Only -// valid in double buffered mode. -#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) -#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) -#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) -#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE -// 0x0 -> Control -// 0x1 -> Isochronous -// 0x2 -> Bulk -// 0x3 -> Interrupt -#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) -#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) -#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) -#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) -#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) -#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) -#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_ON_STALL -// Description : Trigger an interrupt if a STALL is sent. Intended for debug -// only. -#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) -#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) -#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) -#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_ON_NAK -// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. -#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) -#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) -#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) -#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP11_OUT_CONTROL_BUFFER_ADDRESS -// Description : 64 byte aligned buffer address for this EP (bits 0-5 are -// ignored). Relative to the start of the DPRAM. -#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) -#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) -#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_BUFFER_ADDRESS_MSB _u(15) -#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_BUFFER_ADDRESS_LSB _u(0) -#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW" -// ============================================================================= -// Register : USB_DEVICE_DPRAM_EP12_IN_CONTROL -#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_OFFSET _u(0x00000060) -#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_BITS _u(0xfc03ffff) -#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENABLE -// Description : Enable this endpoint. The device will not reply to any packets -// for this endpoint if this bit is not set. -#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENABLE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENABLE_BITS _u(0x80000000) -#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENABLE_MSB _u(31) -#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENABLE_LSB _u(31) -#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENABLE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP12_IN_CONTROL_DOUBLE_BUFFERED -// Description : This endpoint is double buffered. -#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) -#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_DOUBLE_BUFFERED_MSB _u(30) -#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_DOUBLE_BUFFERED_LSB _u(30) -#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_PER_BUFF -// Description : Trigger an interrupt each time a buffer is done. -#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) -#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) -#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) -#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF -// Description : Trigger an interrupt each time both buffers are done. Only -// valid in double buffered mode. -#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) -#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) -#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) -#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE -// 0x0 -> Control -// 0x1 -> Isochronous -// 0x2 -> Bulk -// 0x3 -> Interrupt -#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) -#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) -#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) -#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) -#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) -#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) -#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_ON_STALL -// Description : Trigger an interrupt if a STALL is sent. Intended for debug -// only. -#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) -#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) -#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) -#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_ON_NAK -// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. -#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) -#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) -#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) -#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP12_IN_CONTROL_BUFFER_ADDRESS -// Description : 64 byte aligned buffer address for this EP (bits 0-5 are -// ignored). Relative to the start of the DPRAM. -#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) -#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) -#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_BUFFER_ADDRESS_MSB _u(15) -#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_BUFFER_ADDRESS_LSB _u(0) -#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW" -// ============================================================================= -// Register : USB_DEVICE_DPRAM_EP12_OUT_CONTROL -#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_OFFSET _u(0x00000064) -#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_BITS _u(0xfc03ffff) -#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENABLE -// Description : Enable this endpoint. The device will not reply to any packets -// for this endpoint if this bit is not set. -#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENABLE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENABLE_BITS _u(0x80000000) -#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENABLE_MSB _u(31) -#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENABLE_LSB _u(31) -#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENABLE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP12_OUT_CONTROL_DOUBLE_BUFFERED -// Description : This endpoint is double buffered. -#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) -#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_DOUBLE_BUFFERED_MSB _u(30) -#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_DOUBLE_BUFFERED_LSB _u(30) -#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_PER_BUFF -// Description : Trigger an interrupt each time a buffer is done. -#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) -#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) -#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) -#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF -// Description : Trigger an interrupt each time both buffers are done. Only -// valid in double buffered mode. -#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) -#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) -#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) -#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE -// 0x0 -> Control -// 0x1 -> Isochronous -// 0x2 -> Bulk -// 0x3 -> Interrupt -#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) -#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) -#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) -#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) -#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) -#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) -#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_ON_STALL -// Description : Trigger an interrupt if a STALL is sent. Intended for debug -// only. -#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) -#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) -#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) -#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_ON_NAK -// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. -#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) -#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) -#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) -#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP12_OUT_CONTROL_BUFFER_ADDRESS -// Description : 64 byte aligned buffer address for this EP (bits 0-5 are -// ignored). Relative to the start of the DPRAM. -#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) -#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) -#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_BUFFER_ADDRESS_MSB _u(15) -#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_BUFFER_ADDRESS_LSB _u(0) -#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW" -// ============================================================================= -// Register : USB_DEVICE_DPRAM_EP13_IN_CONTROL -#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_OFFSET _u(0x00000068) -#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_BITS _u(0xfc03ffff) -#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENABLE -// Description : Enable this endpoint. The device will not reply to any packets -// for this endpoint if this bit is not set. -#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENABLE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENABLE_BITS _u(0x80000000) -#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENABLE_MSB _u(31) -#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENABLE_LSB _u(31) -#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENABLE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP13_IN_CONTROL_DOUBLE_BUFFERED -// Description : This endpoint is double buffered. -#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) -#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_DOUBLE_BUFFERED_MSB _u(30) -#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_DOUBLE_BUFFERED_LSB _u(30) -#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_PER_BUFF -// Description : Trigger an interrupt each time a buffer is done. -#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) -#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) -#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) -#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF -// Description : Trigger an interrupt each time both buffers are done. Only -// valid in double buffered mode. -#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) -#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) -#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) -#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE -// 0x0 -> Control -// 0x1 -> Isochronous -// 0x2 -> Bulk -// 0x3 -> Interrupt -#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) -#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) -#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) -#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) -#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) -#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) -#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_ON_STALL -// Description : Trigger an interrupt if a STALL is sent. Intended for debug -// only. -#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) -#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) -#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) -#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_ON_NAK -// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. -#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) -#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) -#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) -#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP13_IN_CONTROL_BUFFER_ADDRESS -// Description : 64 byte aligned buffer address for this EP (bits 0-5 are -// ignored). Relative to the start of the DPRAM. -#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) -#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) -#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_BUFFER_ADDRESS_MSB _u(15) -#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_BUFFER_ADDRESS_LSB _u(0) -#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW" -// ============================================================================= -// Register : USB_DEVICE_DPRAM_EP13_OUT_CONTROL -#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_OFFSET _u(0x0000006c) -#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_BITS _u(0xfc03ffff) -#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENABLE -// Description : Enable this endpoint. The device will not reply to any packets -// for this endpoint if this bit is not set. -#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENABLE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENABLE_BITS _u(0x80000000) -#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENABLE_MSB _u(31) -#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENABLE_LSB _u(31) -#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENABLE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP13_OUT_CONTROL_DOUBLE_BUFFERED -// Description : This endpoint is double buffered. -#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) -#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_DOUBLE_BUFFERED_MSB _u(30) -#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_DOUBLE_BUFFERED_LSB _u(30) -#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_PER_BUFF -// Description : Trigger an interrupt each time a buffer is done. -#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) -#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) -#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) -#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF -// Description : Trigger an interrupt each time both buffers are done. Only -// valid in double buffered mode. -#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) -#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) -#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) -#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE -// 0x0 -> Control -// 0x1 -> Isochronous -// 0x2 -> Bulk -// 0x3 -> Interrupt -#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) -#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) -#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) -#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) -#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) -#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) -#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_ON_STALL -// Description : Trigger an interrupt if a STALL is sent. Intended for debug -// only. -#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) -#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) -#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) -#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_ON_NAK -// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. -#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) -#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) -#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) -#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP13_OUT_CONTROL_BUFFER_ADDRESS -// Description : 64 byte aligned buffer address for this EP (bits 0-5 are -// ignored). Relative to the start of the DPRAM. -#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) -#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) -#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_BUFFER_ADDRESS_MSB _u(15) -#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_BUFFER_ADDRESS_LSB _u(0) -#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW" -// ============================================================================= -// Register : USB_DEVICE_DPRAM_EP14_IN_CONTROL -#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_OFFSET _u(0x00000070) -#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_BITS _u(0xfc03ffff) -#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENABLE -// Description : Enable this endpoint. The device will not reply to any packets -// for this endpoint if this bit is not set. -#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENABLE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENABLE_BITS _u(0x80000000) -#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENABLE_MSB _u(31) -#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENABLE_LSB _u(31) -#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENABLE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP14_IN_CONTROL_DOUBLE_BUFFERED -// Description : This endpoint is double buffered. -#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) -#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_DOUBLE_BUFFERED_MSB _u(30) -#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_DOUBLE_BUFFERED_LSB _u(30) -#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_PER_BUFF -// Description : Trigger an interrupt each time a buffer is done. -#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) -#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) -#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) -#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF -// Description : Trigger an interrupt each time both buffers are done. Only -// valid in double buffered mode. -#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) -#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) -#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) -#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE -// 0x0 -> Control -// 0x1 -> Isochronous -// 0x2 -> Bulk -// 0x3 -> Interrupt -#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) -#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) -#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) -#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) -#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) -#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) -#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_ON_STALL -// Description : Trigger an interrupt if a STALL is sent. Intended for debug -// only. -#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) -#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) -#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) -#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_ON_NAK -// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. -#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) -#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) -#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) -#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP14_IN_CONTROL_BUFFER_ADDRESS -// Description : 64 byte aligned buffer address for this EP (bits 0-5 are -// ignored). Relative to the start of the DPRAM. -#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) -#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) -#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_BUFFER_ADDRESS_MSB _u(15) -#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_BUFFER_ADDRESS_LSB _u(0) -#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW" -// ============================================================================= -// Register : USB_DEVICE_DPRAM_EP14_OUT_CONTROL -#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_OFFSET _u(0x00000074) -#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_BITS _u(0xfc03ffff) -#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENABLE -// Description : Enable this endpoint. The device will not reply to any packets -// for this endpoint if this bit is not set. -#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENABLE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENABLE_BITS _u(0x80000000) -#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENABLE_MSB _u(31) -#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENABLE_LSB _u(31) -#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENABLE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP14_OUT_CONTROL_DOUBLE_BUFFERED -// Description : This endpoint is double buffered. -#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) -#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_DOUBLE_BUFFERED_MSB _u(30) -#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_DOUBLE_BUFFERED_LSB _u(30) -#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_PER_BUFF -// Description : Trigger an interrupt each time a buffer is done. -#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) -#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) -#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) -#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF -// Description : Trigger an interrupt each time both buffers are done. Only -// valid in double buffered mode. -#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) -#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) -#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) -#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE -// 0x0 -> Control -// 0x1 -> Isochronous -// 0x2 -> Bulk -// 0x3 -> Interrupt -#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) -#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) -#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) -#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) -#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) -#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) -#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_ON_STALL -// Description : Trigger an interrupt if a STALL is sent. Intended for debug -// only. -#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) -#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) -#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) -#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_ON_NAK -// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. -#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) -#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) -#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) -#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP14_OUT_CONTROL_BUFFER_ADDRESS -// Description : 64 byte aligned buffer address for this EP (bits 0-5 are -// ignored). Relative to the start of the DPRAM. -#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) -#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) -#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_BUFFER_ADDRESS_MSB _u(15) -#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_BUFFER_ADDRESS_LSB _u(0) -#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW" -// ============================================================================= -// Register : USB_DEVICE_DPRAM_EP15_IN_CONTROL -#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_OFFSET _u(0x00000078) -#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_BITS _u(0xfc03ffff) -#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENABLE -// Description : Enable this endpoint. The device will not reply to any packets -// for this endpoint if this bit is not set. -#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENABLE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENABLE_BITS _u(0x80000000) -#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENABLE_MSB _u(31) -#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENABLE_LSB _u(31) -#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENABLE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP15_IN_CONTROL_DOUBLE_BUFFERED -// Description : This endpoint is double buffered. -#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) -#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_DOUBLE_BUFFERED_MSB _u(30) -#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_DOUBLE_BUFFERED_LSB _u(30) -#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_PER_BUFF -// Description : Trigger an interrupt each time a buffer is done. -#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) -#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) -#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) -#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF -// Description : Trigger an interrupt each time both buffers are done. Only -// valid in double buffered mode. -#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) -#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) -#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) -#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE -// 0x0 -> Control -// 0x1 -> Isochronous -// 0x2 -> Bulk -// 0x3 -> Interrupt -#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) -#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) -#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) -#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) -#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) -#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) -#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_ON_STALL -// Description : Trigger an interrupt if a STALL is sent. Intended for debug -// only. -#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) -#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) -#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) -#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_ON_NAK -// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. -#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) -#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) -#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) -#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP15_IN_CONTROL_BUFFER_ADDRESS -// Description : 64 byte aligned buffer address for this EP (bits 0-5 are -// ignored). Relative to the start of the DPRAM. -#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) -#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) -#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_BUFFER_ADDRESS_MSB _u(15) -#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_BUFFER_ADDRESS_LSB _u(0) -#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW" -// ============================================================================= -// Register : USB_DEVICE_DPRAM_EP15_OUT_CONTROL -#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_OFFSET _u(0x0000007c) -#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_BITS _u(0xfc03ffff) -#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENABLE -// Description : Enable this endpoint. The device will not reply to any packets -// for this endpoint if this bit is not set. -#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENABLE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENABLE_BITS _u(0x80000000) -#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENABLE_MSB _u(31) -#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENABLE_LSB _u(31) -#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENABLE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP15_OUT_CONTROL_DOUBLE_BUFFERED -// Description : This endpoint is double buffered. -#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) -#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_DOUBLE_BUFFERED_MSB _u(30) -#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_DOUBLE_BUFFERED_LSB _u(30) -#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_PER_BUFF -// Description : Trigger an interrupt each time a buffer is done. -#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) -#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) -#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) -#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF -// Description : Trigger an interrupt each time both buffers are done. Only -// valid in double buffered mode. -#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) -#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) -#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) -#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE -// 0x0 -> Control -// 0x1 -> Isochronous -// 0x2 -> Bulk -// 0x3 -> Interrupt -#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) -#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) -#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) -#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) -#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) -#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) -#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_ON_STALL -// Description : Trigger an interrupt if a STALL is sent. Intended for debug -// only. -#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) -#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) -#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) -#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_ON_NAK -// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. -#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) -#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) -#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) -#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP15_OUT_CONTROL_BUFFER_ADDRESS -// Description : 64 byte aligned buffer address for this EP (bits 0-5 are -// ignored). Relative to the start of the DPRAM. -#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) -#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) -#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_BUFFER_ADDRESS_MSB _u(15) -#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_BUFFER_ADDRESS_LSB _u(0) -#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW" -// ============================================================================= -// Register : USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL -// Description : Buffer control for both buffers of an endpoint. Fields ending -// in a _1 are for buffer 1. -// Fields ending in a _0 are for buffer 0. Buffer 1 controls are -// only valid if the endpoint is in double buffered mode. -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_OFFSET _u(0x00000080) -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_BITS _u(0xffffffff) -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_FULL_1 -// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit -// is set to indicate the data is valid. For an OUT transfer (RX -// from the host) this bit should be left as a 0. The host will -// set it when it has filled the buffer with data. -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_FULL_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_FULL_1_MSB _u(31) -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_FULL_1_LSB _u(31) -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LAST_1 -// Description : Buffer 1 is the last buffer of the transfer. -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LAST_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LAST_1_MSB _u(30) -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LAST_1_LSB _u(30) -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_PID_1 -// Description : The data pid of buffer 1. -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_PID_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_PID_1_MSB _u(29) -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_PID_1_LSB _u(29) -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_PID_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET -// Description : The number of bytes buffer 1 is offset from buffer 0 in -// Isochronous mode. Only valid in double buffered mode for an -// Isochronous endpoint. -// For a non Isochronous endpoint the offset is always 64 bytes. -// 0x0 -> 128 -// 0x1 -> 256 -// 0x2 -> 512 -// 0x3 -> 1024 -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_AVAILABLE_1 -// Description : Buffer 1 is available. This bit is set to indicate the buffer -// can be used by the controller. The controller clears the -// available bit when writing the status back. -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_1 -// Description : The length of the data in buffer 1. -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_1_MSB _u(25) -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_1_LSB _u(16) -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_FULL_0 -// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit -// is set to indicate the data is valid. For an OUT transfer (RX -// from the host) this bit should be left as a 0. The host will -// set it when it has filled the buffer with data. -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_FULL_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_FULL_0_MSB _u(15) -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_FULL_0_LSB _u(15) -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LAST_0 -// Description : Buffer 0 is the last buffer of the transfer. -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LAST_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LAST_0_MSB _u(14) -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LAST_0_LSB _u(14) -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_PID_0 -// Description : The data pid of buffer 0. -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_PID_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_PID_0_MSB _u(13) -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_PID_0_LSB _u(13) -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_PID_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_RESET -// Description : Reset the buffer selector to buffer 0. -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_RESET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_RESET_BITS _u(0x00001000) -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_RESET_MSB _u(12) -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_RESET_LSB _u(12) -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_RESET_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_STALL -// Description : Reply with a stall (valid for both buffers). -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_STALL_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_STALL_BITS _u(0x00000800) -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_STALL_MSB _u(11) -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_STALL_LSB _u(11) -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_STALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_AVAILABLE_0 -// Description : Buffer 0 is available. This bit is set to indicate the buffer -// can be used by the controller. The controller clears the -// available bit when writing the status back. -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_0 -// Description : The length of the data in buffer 1. -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_0_MSB _u(9) -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_0_LSB _u(0) -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" -// ============================================================================= -// Register : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL -// Description : Buffer control for both buffers of an endpoint. Fields ending -// in a _1 are for buffer 1. -// Fields ending in a _0 are for buffer 0. Buffer 1 controls are -// only valid if the endpoint is in double buffered mode. -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_OFFSET _u(0x00000084) -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_BITS _u(0xffffffff) -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_FULL_1 -// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit -// is set to indicate the data is valid. For an OUT transfer (RX -// from the host) this bit should be left as a 0. The host will -// set it when it has filled the buffer with data. -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_FULL_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_FULL_1_MSB _u(31) -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_FULL_1_LSB _u(31) -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LAST_1 -// Description : Buffer 1 is the last buffer of the transfer. -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LAST_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LAST_1_MSB _u(30) -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LAST_1_LSB _u(30) -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_PID_1 -// Description : The data pid of buffer 1. -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_PID_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_PID_1_MSB _u(29) -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_PID_1_LSB _u(29) -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET -// Description : The number of bytes buffer 1 is offset from buffer 0 in -// Isochronous mode. Only valid in double buffered mode for an -// Isochronous endpoint. -// For a non Isochronous endpoint the offset is always 64 bytes. -// 0x0 -> 128 -// 0x1 -> 256 -// 0x2 -> 512 -// 0x3 -> 1024 -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_AVAILABLE_1 -// Description : Buffer 1 is available. This bit is set to indicate the buffer -// can be used by the controller. The controller clears the -// available bit when writing the status back. -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_1 -// Description : The length of the data in buffer 1. -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_1_MSB _u(25) -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_1_LSB _u(16) -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_FULL_0 -// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit -// is set to indicate the data is valid. For an OUT transfer (RX -// from the host) this bit should be left as a 0. The host will -// set it when it has filled the buffer with data. -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_FULL_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_FULL_0_MSB _u(15) -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_FULL_0_LSB _u(15) -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LAST_0 -// Description : Buffer 0 is the last buffer of the transfer. -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LAST_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LAST_0_MSB _u(14) -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LAST_0_LSB _u(14) -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_PID_0 -// Description : The data pid of buffer 0. -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_PID_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_PID_0_MSB _u(13) -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_PID_0_LSB _u(13) -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_RESET -// Description : Reset the buffer selector to buffer 0. -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_RESET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_RESET_BITS _u(0x00001000) -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_RESET_MSB _u(12) -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_RESET_LSB _u(12) -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_RESET_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_STALL -// Description : Reply with a stall (valid for both buffers). -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_STALL_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_STALL_BITS _u(0x00000800) -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_STALL_MSB _u(11) -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_STALL_LSB _u(11) -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_STALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_AVAILABLE_0 -// Description : Buffer 0 is available. This bit is set to indicate the buffer -// can be used by the controller. The controller clears the -// available bit when writing the status back. -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_0 -// Description : The length of the data in buffer 1. -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_0_MSB _u(9) -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_0_LSB _u(0) -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" -// ============================================================================= -// Register : USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL -// Description : Buffer control for both buffers of an endpoint. Fields ending -// in a _1 are for buffer 1. -// Fields ending in a _0 are for buffer 0. Buffer 1 controls are -// only valid if the endpoint is in double buffered mode. -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_OFFSET _u(0x00000088) -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_BITS _u(0xffffffff) -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_FULL_1 -// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit -// is set to indicate the data is valid. For an OUT transfer (RX -// from the host) this bit should be left as a 0. The host will -// set it when it has filled the buffer with data. -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_FULL_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_FULL_1_MSB _u(31) -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_FULL_1_LSB _u(31) -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LAST_1 -// Description : Buffer 1 is the last buffer of the transfer. -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LAST_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LAST_1_MSB _u(30) -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LAST_1_LSB _u(30) -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_PID_1 -// Description : The data pid of buffer 1. -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_PID_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_PID_1_MSB _u(29) -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_PID_1_LSB _u(29) -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_PID_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET -// Description : The number of bytes buffer 1 is offset from buffer 0 in -// Isochronous mode. Only valid in double buffered mode for an -// Isochronous endpoint. -// For a non Isochronous endpoint the offset is always 64 bytes. -// 0x0 -> 128 -// 0x1 -> 256 -// 0x2 -> 512 -// 0x3 -> 1024 -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_AVAILABLE_1 -// Description : Buffer 1 is available. This bit is set to indicate the buffer -// can be used by the controller. The controller clears the -// available bit when writing the status back. -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_1 -// Description : The length of the data in buffer 1. -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_1_MSB _u(25) -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_1_LSB _u(16) -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_FULL_0 -// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit -// is set to indicate the data is valid. For an OUT transfer (RX -// from the host) this bit should be left as a 0. The host will -// set it when it has filled the buffer with data. -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_FULL_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_FULL_0_MSB _u(15) -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_FULL_0_LSB _u(15) -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LAST_0 -// Description : Buffer 0 is the last buffer of the transfer. -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LAST_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LAST_0_MSB _u(14) -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LAST_0_LSB _u(14) -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_PID_0 -// Description : The data pid of buffer 0. -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_PID_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_PID_0_MSB _u(13) -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_PID_0_LSB _u(13) -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_PID_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_RESET -// Description : Reset the buffer selector to buffer 0. -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_RESET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_RESET_BITS _u(0x00001000) -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_RESET_MSB _u(12) -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_RESET_LSB _u(12) -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_RESET_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_STALL -// Description : Reply with a stall (valid for both buffers). -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_STALL_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_STALL_BITS _u(0x00000800) -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_STALL_MSB _u(11) -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_STALL_LSB _u(11) -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_STALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_AVAILABLE_0 -// Description : Buffer 0 is available. This bit is set to indicate the buffer -// can be used by the controller. The controller clears the -// available bit when writing the status back. -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_0 -// Description : The length of the data in buffer 1. -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_0_MSB _u(9) -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_0_LSB _u(0) -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" -// ============================================================================= -// Register : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL -// Description : Buffer control for both buffers of an endpoint. Fields ending -// in a _1 are for buffer 1. -// Fields ending in a _0 are for buffer 0. Buffer 1 controls are -// only valid if the endpoint is in double buffered mode. -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_OFFSET _u(0x0000008c) -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_BITS _u(0xffffffff) -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_FULL_1 -// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit -// is set to indicate the data is valid. For an OUT transfer (RX -// from the host) this bit should be left as a 0. The host will -// set it when it has filled the buffer with data. -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_FULL_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_FULL_1_MSB _u(31) -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_FULL_1_LSB _u(31) -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LAST_1 -// Description : Buffer 1 is the last buffer of the transfer. -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LAST_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LAST_1_MSB _u(30) -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LAST_1_LSB _u(30) -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_PID_1 -// Description : The data pid of buffer 1. -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_PID_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_PID_1_MSB _u(29) -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_PID_1_LSB _u(29) -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET -// Description : The number of bytes buffer 1 is offset from buffer 0 in -// Isochronous mode. Only valid in double buffered mode for an -// Isochronous endpoint. -// For a non Isochronous endpoint the offset is always 64 bytes. -// 0x0 -> 128 -// 0x1 -> 256 -// 0x2 -> 512 -// 0x3 -> 1024 -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_AVAILABLE_1 -// Description : Buffer 1 is available. This bit is set to indicate the buffer -// can be used by the controller. The controller clears the -// available bit when writing the status back. -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_1 -// Description : The length of the data in buffer 1. -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_1_MSB _u(25) -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_1_LSB _u(16) -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_FULL_0 -// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit -// is set to indicate the data is valid. For an OUT transfer (RX -// from the host) this bit should be left as a 0. The host will -// set it when it has filled the buffer with data. -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_FULL_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_FULL_0_MSB _u(15) -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_FULL_0_LSB _u(15) -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LAST_0 -// Description : Buffer 0 is the last buffer of the transfer. -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LAST_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LAST_0_MSB _u(14) -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LAST_0_LSB _u(14) -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_PID_0 -// Description : The data pid of buffer 0. -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_PID_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_PID_0_MSB _u(13) -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_PID_0_LSB _u(13) -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_RESET -// Description : Reset the buffer selector to buffer 0. -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_RESET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_RESET_BITS _u(0x00001000) -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_RESET_MSB _u(12) -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_RESET_LSB _u(12) -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_RESET_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_STALL -// Description : Reply with a stall (valid for both buffers). -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_STALL_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_STALL_BITS _u(0x00000800) -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_STALL_MSB _u(11) -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_STALL_LSB _u(11) -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_STALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_AVAILABLE_0 -// Description : Buffer 0 is available. This bit is set to indicate the buffer -// can be used by the controller. The controller clears the -// available bit when writing the status back. -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_0 -// Description : The length of the data in buffer 1. -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_0_MSB _u(9) -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_0_LSB _u(0) -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" -// ============================================================================= -// Register : USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL -// Description : Buffer control for both buffers of an endpoint. Fields ending -// in a _1 are for buffer 1. -// Fields ending in a _0 are for buffer 0. Buffer 1 controls are -// only valid if the endpoint is in double buffered mode. -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_OFFSET _u(0x00000090) -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_BITS _u(0xffffffff) -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_FULL_1 -// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit -// is set to indicate the data is valid. For an OUT transfer (RX -// from the host) this bit should be left as a 0. The host will -// set it when it has filled the buffer with data. -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_FULL_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_FULL_1_MSB _u(31) -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_FULL_1_LSB _u(31) -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LAST_1 -// Description : Buffer 1 is the last buffer of the transfer. -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LAST_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LAST_1_MSB _u(30) -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LAST_1_LSB _u(30) -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_PID_1 -// Description : The data pid of buffer 1. -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_PID_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_PID_1_MSB _u(29) -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_PID_1_LSB _u(29) -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_PID_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET -// Description : The number of bytes buffer 1 is offset from buffer 0 in -// Isochronous mode. Only valid in double buffered mode for an -// Isochronous endpoint. -// For a non Isochronous endpoint the offset is always 64 bytes. -// 0x0 -> 128 -// 0x1 -> 256 -// 0x2 -> 512 -// 0x3 -> 1024 -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_AVAILABLE_1 -// Description : Buffer 1 is available. This bit is set to indicate the buffer -// can be used by the controller. The controller clears the -// available bit when writing the status back. -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_1 -// Description : The length of the data in buffer 1. -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_1_MSB _u(25) -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_1_LSB _u(16) -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_FULL_0 -// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit -// is set to indicate the data is valid. For an OUT transfer (RX -// from the host) this bit should be left as a 0. The host will -// set it when it has filled the buffer with data. -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_FULL_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_FULL_0_MSB _u(15) -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_FULL_0_LSB _u(15) -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LAST_0 -// Description : Buffer 0 is the last buffer of the transfer. -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LAST_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LAST_0_MSB _u(14) -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LAST_0_LSB _u(14) -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_PID_0 -// Description : The data pid of buffer 0. -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_PID_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_PID_0_MSB _u(13) -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_PID_0_LSB _u(13) -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_PID_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_RESET -// Description : Reset the buffer selector to buffer 0. -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_RESET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_RESET_BITS _u(0x00001000) -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_RESET_MSB _u(12) -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_RESET_LSB _u(12) -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_RESET_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_STALL -// Description : Reply with a stall (valid for both buffers). -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_STALL_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_STALL_BITS _u(0x00000800) -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_STALL_MSB _u(11) -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_STALL_LSB _u(11) -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_STALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_AVAILABLE_0 -// Description : Buffer 0 is available. This bit is set to indicate the buffer -// can be used by the controller. The controller clears the -// available bit when writing the status back. -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_0 -// Description : The length of the data in buffer 1. -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_0_MSB _u(9) -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_0_LSB _u(0) -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" -// ============================================================================= -// Register : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL -// Description : Buffer control for both buffers of an endpoint. Fields ending -// in a _1 are for buffer 1. -// Fields ending in a _0 are for buffer 0. Buffer 1 controls are -// only valid if the endpoint is in double buffered mode. -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_OFFSET _u(0x00000094) -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_BITS _u(0xffffffff) -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_FULL_1 -// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit -// is set to indicate the data is valid. For an OUT transfer (RX -// from the host) this bit should be left as a 0. The host will -// set it when it has filled the buffer with data. -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_FULL_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_FULL_1_MSB _u(31) -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_FULL_1_LSB _u(31) -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LAST_1 -// Description : Buffer 1 is the last buffer of the transfer. -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LAST_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LAST_1_MSB _u(30) -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LAST_1_LSB _u(30) -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_PID_1 -// Description : The data pid of buffer 1. -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_PID_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_PID_1_MSB _u(29) -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_PID_1_LSB _u(29) -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET -// Description : The number of bytes buffer 1 is offset from buffer 0 in -// Isochronous mode. Only valid in double buffered mode for an -// Isochronous endpoint. -// For a non Isochronous endpoint the offset is always 64 bytes. -// 0x0 -> 128 -// 0x1 -> 256 -// 0x2 -> 512 -// 0x3 -> 1024 -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_AVAILABLE_1 -// Description : Buffer 1 is available. This bit is set to indicate the buffer -// can be used by the controller. The controller clears the -// available bit when writing the status back. -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_1 -// Description : The length of the data in buffer 1. -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_1_MSB _u(25) -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_1_LSB _u(16) -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_FULL_0 -// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit -// is set to indicate the data is valid. For an OUT transfer (RX -// from the host) this bit should be left as a 0. The host will -// set it when it has filled the buffer with data. -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_FULL_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_FULL_0_MSB _u(15) -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_FULL_0_LSB _u(15) -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LAST_0 -// Description : Buffer 0 is the last buffer of the transfer. -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LAST_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LAST_0_MSB _u(14) -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LAST_0_LSB _u(14) -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_PID_0 -// Description : The data pid of buffer 0. -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_PID_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_PID_0_MSB _u(13) -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_PID_0_LSB _u(13) -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_RESET -// Description : Reset the buffer selector to buffer 0. -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_RESET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_RESET_BITS _u(0x00001000) -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_RESET_MSB _u(12) -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_RESET_LSB _u(12) -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_RESET_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_STALL -// Description : Reply with a stall (valid for both buffers). -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_STALL_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_STALL_BITS _u(0x00000800) -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_STALL_MSB _u(11) -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_STALL_LSB _u(11) -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_STALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_AVAILABLE_0 -// Description : Buffer 0 is available. This bit is set to indicate the buffer -// can be used by the controller. The controller clears the -// available bit when writing the status back. -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_0 -// Description : The length of the data in buffer 1. -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_0_MSB _u(9) -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_0_LSB _u(0) -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" -// ============================================================================= -// Register : USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL -// Description : Buffer control for both buffers of an endpoint. Fields ending -// in a _1 are for buffer 1. -// Fields ending in a _0 are for buffer 0. Buffer 1 controls are -// only valid if the endpoint is in double buffered mode. -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_OFFSET _u(0x00000098) -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_BITS _u(0xffffffff) -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_FULL_1 -// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit -// is set to indicate the data is valid. For an OUT transfer (RX -// from the host) this bit should be left as a 0. The host will -// set it when it has filled the buffer with data. -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_FULL_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_FULL_1_MSB _u(31) -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_FULL_1_LSB _u(31) -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LAST_1 -// Description : Buffer 1 is the last buffer of the transfer. -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LAST_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LAST_1_MSB _u(30) -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LAST_1_LSB _u(30) -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_PID_1 -// Description : The data pid of buffer 1. -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_PID_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_PID_1_MSB _u(29) -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_PID_1_LSB _u(29) -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_PID_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET -// Description : The number of bytes buffer 1 is offset from buffer 0 in -// Isochronous mode. Only valid in double buffered mode for an -// Isochronous endpoint. -// For a non Isochronous endpoint the offset is always 64 bytes. -// 0x0 -> 128 -// 0x1 -> 256 -// 0x2 -> 512 -// 0x3 -> 1024 -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_AVAILABLE_1 -// Description : Buffer 1 is available. This bit is set to indicate the buffer -// can be used by the controller. The controller clears the -// available bit when writing the status back. -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_1 -// Description : The length of the data in buffer 1. -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_1_MSB _u(25) -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_1_LSB _u(16) -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_FULL_0 -// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit -// is set to indicate the data is valid. For an OUT transfer (RX -// from the host) this bit should be left as a 0. The host will -// set it when it has filled the buffer with data. -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_FULL_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_FULL_0_MSB _u(15) -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_FULL_0_LSB _u(15) -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LAST_0 -// Description : Buffer 0 is the last buffer of the transfer. -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LAST_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LAST_0_MSB _u(14) -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LAST_0_LSB _u(14) -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_PID_0 -// Description : The data pid of buffer 0. -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_PID_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_PID_0_MSB _u(13) -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_PID_0_LSB _u(13) -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_PID_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_RESET -// Description : Reset the buffer selector to buffer 0. -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_RESET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_RESET_BITS _u(0x00001000) -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_RESET_MSB _u(12) -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_RESET_LSB _u(12) -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_RESET_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_STALL -// Description : Reply with a stall (valid for both buffers). -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_STALL_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_STALL_BITS _u(0x00000800) -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_STALL_MSB _u(11) -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_STALL_LSB _u(11) -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_STALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_AVAILABLE_0 -// Description : Buffer 0 is available. This bit is set to indicate the buffer -// can be used by the controller. The controller clears the -// available bit when writing the status back. -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_0 -// Description : The length of the data in buffer 1. -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_0_MSB _u(9) -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_0_LSB _u(0) -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" -// ============================================================================= -// Register : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL -// Description : Buffer control for both buffers of an endpoint. Fields ending -// in a _1 are for buffer 1. -// Fields ending in a _0 are for buffer 0. Buffer 1 controls are -// only valid if the endpoint is in double buffered mode. -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_OFFSET _u(0x0000009c) -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_BITS _u(0xffffffff) -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_FULL_1 -// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit -// is set to indicate the data is valid. For an OUT transfer (RX -// from the host) this bit should be left as a 0. The host will -// set it when it has filled the buffer with data. -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_FULL_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_FULL_1_MSB _u(31) -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_FULL_1_LSB _u(31) -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LAST_1 -// Description : Buffer 1 is the last buffer of the transfer. -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LAST_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LAST_1_MSB _u(30) -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LAST_1_LSB _u(30) -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_PID_1 -// Description : The data pid of buffer 1. -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_PID_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_PID_1_MSB _u(29) -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_PID_1_LSB _u(29) -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET -// Description : The number of bytes buffer 1 is offset from buffer 0 in -// Isochronous mode. Only valid in double buffered mode for an -// Isochronous endpoint. -// For a non Isochronous endpoint the offset is always 64 bytes. -// 0x0 -> 128 -// 0x1 -> 256 -// 0x2 -> 512 -// 0x3 -> 1024 -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_AVAILABLE_1 -// Description : Buffer 1 is available. This bit is set to indicate the buffer -// can be used by the controller. The controller clears the -// available bit when writing the status back. -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_1 -// Description : The length of the data in buffer 1. -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_1_MSB _u(25) -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_1_LSB _u(16) -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_FULL_0 -// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit -// is set to indicate the data is valid. For an OUT transfer (RX -// from the host) this bit should be left as a 0. The host will -// set it when it has filled the buffer with data. -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_FULL_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_FULL_0_MSB _u(15) -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_FULL_0_LSB _u(15) -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LAST_0 -// Description : Buffer 0 is the last buffer of the transfer. -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LAST_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LAST_0_MSB _u(14) -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LAST_0_LSB _u(14) -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_PID_0 -// Description : The data pid of buffer 0. -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_PID_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_PID_0_MSB _u(13) -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_PID_0_LSB _u(13) -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_RESET -// Description : Reset the buffer selector to buffer 0. -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_RESET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_RESET_BITS _u(0x00001000) -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_RESET_MSB _u(12) -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_RESET_LSB _u(12) -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_RESET_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_STALL -// Description : Reply with a stall (valid for both buffers). -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_STALL_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_STALL_BITS _u(0x00000800) -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_STALL_MSB _u(11) -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_STALL_LSB _u(11) -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_STALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_AVAILABLE_0 -// Description : Buffer 0 is available. This bit is set to indicate the buffer -// can be used by the controller. The controller clears the -// available bit when writing the status back. -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_0 -// Description : The length of the data in buffer 1. -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_0_MSB _u(9) -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_0_LSB _u(0) -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" -// ============================================================================= -// Register : USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL -// Description : Buffer control for both buffers of an endpoint. Fields ending -// in a _1 are for buffer 1. -// Fields ending in a _0 are for buffer 0. Buffer 1 controls are -// only valid if the endpoint is in double buffered mode. -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_OFFSET _u(0x000000a0) -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_BITS _u(0xffffffff) -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_FULL_1 -// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit -// is set to indicate the data is valid. For an OUT transfer (RX -// from the host) this bit should be left as a 0. The host will -// set it when it has filled the buffer with data. -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_FULL_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_FULL_1_MSB _u(31) -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_FULL_1_LSB _u(31) -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LAST_1 -// Description : Buffer 1 is the last buffer of the transfer. -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LAST_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LAST_1_MSB _u(30) -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LAST_1_LSB _u(30) -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_PID_1 -// Description : The data pid of buffer 1. -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_PID_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_PID_1_MSB _u(29) -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_PID_1_LSB _u(29) -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_PID_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET -// Description : The number of bytes buffer 1 is offset from buffer 0 in -// Isochronous mode. Only valid in double buffered mode for an -// Isochronous endpoint. -// For a non Isochronous endpoint the offset is always 64 bytes. -// 0x0 -> 128 -// 0x1 -> 256 -// 0x2 -> 512 -// 0x3 -> 1024 -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_AVAILABLE_1 -// Description : Buffer 1 is available. This bit is set to indicate the buffer -// can be used by the controller. The controller clears the -// available bit when writing the status back. -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_1 -// Description : The length of the data in buffer 1. -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_1_MSB _u(25) -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_1_LSB _u(16) -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_FULL_0 -// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit -// is set to indicate the data is valid. For an OUT transfer (RX -// from the host) this bit should be left as a 0. The host will -// set it when it has filled the buffer with data. -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_FULL_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_FULL_0_MSB _u(15) -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_FULL_0_LSB _u(15) -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LAST_0 -// Description : Buffer 0 is the last buffer of the transfer. -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LAST_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LAST_0_MSB _u(14) -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LAST_0_LSB _u(14) -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_PID_0 -// Description : The data pid of buffer 0. -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_PID_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_PID_0_MSB _u(13) -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_PID_0_LSB _u(13) -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_PID_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_RESET -// Description : Reset the buffer selector to buffer 0. -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_RESET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_RESET_BITS _u(0x00001000) -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_RESET_MSB _u(12) -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_RESET_LSB _u(12) -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_RESET_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_STALL -// Description : Reply with a stall (valid for both buffers). -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_STALL_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_STALL_BITS _u(0x00000800) -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_STALL_MSB _u(11) -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_STALL_LSB _u(11) -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_STALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_AVAILABLE_0 -// Description : Buffer 0 is available. This bit is set to indicate the buffer -// can be used by the controller. The controller clears the -// available bit when writing the status back. -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_0 -// Description : The length of the data in buffer 1. -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_0_MSB _u(9) -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_0_LSB _u(0) -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" -// ============================================================================= -// Register : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL -// Description : Buffer control for both buffers of an endpoint. Fields ending -// in a _1 are for buffer 1. -// Fields ending in a _0 are for buffer 0. Buffer 1 controls are -// only valid if the endpoint is in double buffered mode. -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_OFFSET _u(0x000000a4) -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_BITS _u(0xffffffff) -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_FULL_1 -// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit -// is set to indicate the data is valid. For an OUT transfer (RX -// from the host) this bit should be left as a 0. The host will -// set it when it has filled the buffer with data. -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_FULL_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_FULL_1_MSB _u(31) -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_FULL_1_LSB _u(31) -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LAST_1 -// Description : Buffer 1 is the last buffer of the transfer. -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LAST_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LAST_1_MSB _u(30) -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LAST_1_LSB _u(30) -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_PID_1 -// Description : The data pid of buffer 1. -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_PID_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_PID_1_MSB _u(29) -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_PID_1_LSB _u(29) -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET -// Description : The number of bytes buffer 1 is offset from buffer 0 in -// Isochronous mode. Only valid in double buffered mode for an -// Isochronous endpoint. -// For a non Isochronous endpoint the offset is always 64 bytes. -// 0x0 -> 128 -// 0x1 -> 256 -// 0x2 -> 512 -// 0x3 -> 1024 -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_AVAILABLE_1 -// Description : Buffer 1 is available. This bit is set to indicate the buffer -// can be used by the controller. The controller clears the -// available bit when writing the status back. -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_1 -// Description : The length of the data in buffer 1. -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_1_MSB _u(25) -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_1_LSB _u(16) -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_FULL_0 -// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit -// is set to indicate the data is valid. For an OUT transfer (RX -// from the host) this bit should be left as a 0. The host will -// set it when it has filled the buffer with data. -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_FULL_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_FULL_0_MSB _u(15) -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_FULL_0_LSB _u(15) -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LAST_0 -// Description : Buffer 0 is the last buffer of the transfer. -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LAST_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LAST_0_MSB _u(14) -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LAST_0_LSB _u(14) -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_PID_0 -// Description : The data pid of buffer 0. -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_PID_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_PID_0_MSB _u(13) -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_PID_0_LSB _u(13) -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_RESET -// Description : Reset the buffer selector to buffer 0. -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_RESET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_RESET_BITS _u(0x00001000) -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_RESET_MSB _u(12) -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_RESET_LSB _u(12) -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_RESET_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_STALL -// Description : Reply with a stall (valid for both buffers). -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_STALL_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_STALL_BITS _u(0x00000800) -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_STALL_MSB _u(11) -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_STALL_LSB _u(11) -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_STALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_AVAILABLE_0 -// Description : Buffer 0 is available. This bit is set to indicate the buffer -// can be used by the controller. The controller clears the -// available bit when writing the status back. -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_0 -// Description : The length of the data in buffer 1. -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_0_MSB _u(9) -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_0_LSB _u(0) -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" -// ============================================================================= -// Register : USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL -// Description : Buffer control for both buffers of an endpoint. Fields ending -// in a _1 are for buffer 1. -// Fields ending in a _0 are for buffer 0. Buffer 1 controls are -// only valid if the endpoint is in double buffered mode. -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_OFFSET _u(0x000000a8) -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_BITS _u(0xffffffff) -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_FULL_1 -// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit -// is set to indicate the data is valid. For an OUT transfer (RX -// from the host) this bit should be left as a 0. The host will -// set it when it has filled the buffer with data. -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_FULL_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_FULL_1_MSB _u(31) -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_FULL_1_LSB _u(31) -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LAST_1 -// Description : Buffer 1 is the last buffer of the transfer. -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LAST_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LAST_1_MSB _u(30) -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LAST_1_LSB _u(30) -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_PID_1 -// Description : The data pid of buffer 1. -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_PID_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_PID_1_MSB _u(29) -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_PID_1_LSB _u(29) -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_PID_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET -// Description : The number of bytes buffer 1 is offset from buffer 0 in -// Isochronous mode. Only valid in double buffered mode for an -// Isochronous endpoint. -// For a non Isochronous endpoint the offset is always 64 bytes. -// 0x0 -> 128 -// 0x1 -> 256 -// 0x2 -> 512 -// 0x3 -> 1024 -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_AVAILABLE_1 -// Description : Buffer 1 is available. This bit is set to indicate the buffer -// can be used by the controller. The controller clears the -// available bit when writing the status back. -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_1 -// Description : The length of the data in buffer 1. -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_1_MSB _u(25) -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_1_LSB _u(16) -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_FULL_0 -// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit -// is set to indicate the data is valid. For an OUT transfer (RX -// from the host) this bit should be left as a 0. The host will -// set it when it has filled the buffer with data. -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_FULL_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_FULL_0_MSB _u(15) -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_FULL_0_LSB _u(15) -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LAST_0 -// Description : Buffer 0 is the last buffer of the transfer. -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LAST_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LAST_0_MSB _u(14) -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LAST_0_LSB _u(14) -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_PID_0 -// Description : The data pid of buffer 0. -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_PID_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_PID_0_MSB _u(13) -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_PID_0_LSB _u(13) -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_PID_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_RESET -// Description : Reset the buffer selector to buffer 0. -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_RESET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_RESET_BITS _u(0x00001000) -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_RESET_MSB _u(12) -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_RESET_LSB _u(12) -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_RESET_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_STALL -// Description : Reply with a stall (valid for both buffers). -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_STALL_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_STALL_BITS _u(0x00000800) -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_STALL_MSB _u(11) -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_STALL_LSB _u(11) -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_STALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_AVAILABLE_0 -// Description : Buffer 0 is available. This bit is set to indicate the buffer -// can be used by the controller. The controller clears the -// available bit when writing the status back. -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_0 -// Description : The length of the data in buffer 1. -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_0_MSB _u(9) -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_0_LSB _u(0) -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" -// ============================================================================= -// Register : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL -// Description : Buffer control for both buffers of an endpoint. Fields ending -// in a _1 are for buffer 1. -// Fields ending in a _0 are for buffer 0. Buffer 1 controls are -// only valid if the endpoint is in double buffered mode. -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_OFFSET _u(0x000000ac) -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_BITS _u(0xffffffff) -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_FULL_1 -// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit -// is set to indicate the data is valid. For an OUT transfer (RX -// from the host) this bit should be left as a 0. The host will -// set it when it has filled the buffer with data. -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_FULL_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_FULL_1_MSB _u(31) -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_FULL_1_LSB _u(31) -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LAST_1 -// Description : Buffer 1 is the last buffer of the transfer. -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LAST_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LAST_1_MSB _u(30) -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LAST_1_LSB _u(30) -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_PID_1 -// Description : The data pid of buffer 1. -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_PID_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_PID_1_MSB _u(29) -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_PID_1_LSB _u(29) -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET -// Description : The number of bytes buffer 1 is offset from buffer 0 in -// Isochronous mode. Only valid in double buffered mode for an -// Isochronous endpoint. -// For a non Isochronous endpoint the offset is always 64 bytes. -// 0x0 -> 128 -// 0x1 -> 256 -// 0x2 -> 512 -// 0x3 -> 1024 -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_AVAILABLE_1 -// Description : Buffer 1 is available. This bit is set to indicate the buffer -// can be used by the controller. The controller clears the -// available bit when writing the status back. -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_1 -// Description : The length of the data in buffer 1. -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_1_MSB _u(25) -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_1_LSB _u(16) -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_FULL_0 -// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit -// is set to indicate the data is valid. For an OUT transfer (RX -// from the host) this bit should be left as a 0. The host will -// set it when it has filled the buffer with data. -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_FULL_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_FULL_0_MSB _u(15) -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_FULL_0_LSB _u(15) -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LAST_0 -// Description : Buffer 0 is the last buffer of the transfer. -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LAST_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LAST_0_MSB _u(14) -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LAST_0_LSB _u(14) -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_PID_0 -// Description : The data pid of buffer 0. -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_PID_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_PID_0_MSB _u(13) -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_PID_0_LSB _u(13) -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_RESET -// Description : Reset the buffer selector to buffer 0. -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_RESET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_RESET_BITS _u(0x00001000) -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_RESET_MSB _u(12) -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_RESET_LSB _u(12) -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_RESET_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_STALL -// Description : Reply with a stall (valid for both buffers). -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_STALL_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_STALL_BITS _u(0x00000800) -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_STALL_MSB _u(11) -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_STALL_LSB _u(11) -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_STALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_AVAILABLE_0 -// Description : Buffer 0 is available. This bit is set to indicate the buffer -// can be used by the controller. The controller clears the -// available bit when writing the status back. -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_0 -// Description : The length of the data in buffer 1. -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_0_MSB _u(9) -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_0_LSB _u(0) -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" -// ============================================================================= -// Register : USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL -// Description : Buffer control for both buffers of an endpoint. Fields ending -// in a _1 are for buffer 1. -// Fields ending in a _0 are for buffer 0. Buffer 1 controls are -// only valid if the endpoint is in double buffered mode. -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_OFFSET _u(0x000000b0) -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_BITS _u(0xffffffff) -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_FULL_1 -// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit -// is set to indicate the data is valid. For an OUT transfer (RX -// from the host) this bit should be left as a 0. The host will -// set it when it has filled the buffer with data. -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_FULL_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_FULL_1_MSB _u(31) -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_FULL_1_LSB _u(31) -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LAST_1 -// Description : Buffer 1 is the last buffer of the transfer. -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LAST_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LAST_1_MSB _u(30) -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LAST_1_LSB _u(30) -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_PID_1 -// Description : The data pid of buffer 1. -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_PID_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_PID_1_MSB _u(29) -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_PID_1_LSB _u(29) -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_PID_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET -// Description : The number of bytes buffer 1 is offset from buffer 0 in -// Isochronous mode. Only valid in double buffered mode for an -// Isochronous endpoint. -// For a non Isochronous endpoint the offset is always 64 bytes. -// 0x0 -> 128 -// 0x1 -> 256 -// 0x2 -> 512 -// 0x3 -> 1024 -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_AVAILABLE_1 -// Description : Buffer 1 is available. This bit is set to indicate the buffer -// can be used by the controller. The controller clears the -// available bit when writing the status back. -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_1 -// Description : The length of the data in buffer 1. -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_1_MSB _u(25) -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_1_LSB _u(16) -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_FULL_0 -// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit -// is set to indicate the data is valid. For an OUT transfer (RX -// from the host) this bit should be left as a 0. The host will -// set it when it has filled the buffer with data. -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_FULL_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_FULL_0_MSB _u(15) -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_FULL_0_LSB _u(15) -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LAST_0 -// Description : Buffer 0 is the last buffer of the transfer. -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LAST_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LAST_0_MSB _u(14) -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LAST_0_LSB _u(14) -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_PID_0 -// Description : The data pid of buffer 0. -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_PID_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_PID_0_MSB _u(13) -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_PID_0_LSB _u(13) -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_PID_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_RESET -// Description : Reset the buffer selector to buffer 0. -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_RESET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_RESET_BITS _u(0x00001000) -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_RESET_MSB _u(12) -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_RESET_LSB _u(12) -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_RESET_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_STALL -// Description : Reply with a stall (valid for both buffers). -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_STALL_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_STALL_BITS _u(0x00000800) -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_STALL_MSB _u(11) -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_STALL_LSB _u(11) -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_STALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_AVAILABLE_0 -// Description : Buffer 0 is available. This bit is set to indicate the buffer -// can be used by the controller. The controller clears the -// available bit when writing the status back. -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_0 -// Description : The length of the data in buffer 1. -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_0_MSB _u(9) -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_0_LSB _u(0) -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" -// ============================================================================= -// Register : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL -// Description : Buffer control for both buffers of an endpoint. Fields ending -// in a _1 are for buffer 1. -// Fields ending in a _0 are for buffer 0. Buffer 1 controls are -// only valid if the endpoint is in double buffered mode. -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_OFFSET _u(0x000000b4) -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_BITS _u(0xffffffff) -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_FULL_1 -// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit -// is set to indicate the data is valid. For an OUT transfer (RX -// from the host) this bit should be left as a 0. The host will -// set it when it has filled the buffer with data. -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_FULL_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_FULL_1_MSB _u(31) -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_FULL_1_LSB _u(31) -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LAST_1 -// Description : Buffer 1 is the last buffer of the transfer. -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LAST_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LAST_1_MSB _u(30) -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LAST_1_LSB _u(30) -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_PID_1 -// Description : The data pid of buffer 1. -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_PID_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_PID_1_MSB _u(29) -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_PID_1_LSB _u(29) -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET -// Description : The number of bytes buffer 1 is offset from buffer 0 in -// Isochronous mode. Only valid in double buffered mode for an -// Isochronous endpoint. -// For a non Isochronous endpoint the offset is always 64 bytes. -// 0x0 -> 128 -// 0x1 -> 256 -// 0x2 -> 512 -// 0x3 -> 1024 -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_AVAILABLE_1 -// Description : Buffer 1 is available. This bit is set to indicate the buffer -// can be used by the controller. The controller clears the -// available bit when writing the status back. -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_1 -// Description : The length of the data in buffer 1. -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_1_MSB _u(25) -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_1_LSB _u(16) -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_FULL_0 -// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit -// is set to indicate the data is valid. For an OUT transfer (RX -// from the host) this bit should be left as a 0. The host will -// set it when it has filled the buffer with data. -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_FULL_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_FULL_0_MSB _u(15) -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_FULL_0_LSB _u(15) -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LAST_0 -// Description : Buffer 0 is the last buffer of the transfer. -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LAST_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LAST_0_MSB _u(14) -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LAST_0_LSB _u(14) -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_PID_0 -// Description : The data pid of buffer 0. -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_PID_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_PID_0_MSB _u(13) -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_PID_0_LSB _u(13) -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_RESET -// Description : Reset the buffer selector to buffer 0. -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_RESET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_RESET_BITS _u(0x00001000) -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_RESET_MSB _u(12) -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_RESET_LSB _u(12) -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_RESET_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_STALL -// Description : Reply with a stall (valid for both buffers). -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_STALL_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_STALL_BITS _u(0x00000800) -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_STALL_MSB _u(11) -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_STALL_LSB _u(11) -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_STALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_AVAILABLE_0 -// Description : Buffer 0 is available. This bit is set to indicate the buffer -// can be used by the controller. The controller clears the -// available bit when writing the status back. -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_0 -// Description : The length of the data in buffer 1. -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_0_MSB _u(9) -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_0_LSB _u(0) -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" -// ============================================================================= -// Register : USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL -// Description : Buffer control for both buffers of an endpoint. Fields ending -// in a _1 are for buffer 1. -// Fields ending in a _0 are for buffer 0. Buffer 1 controls are -// only valid if the endpoint is in double buffered mode. -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_OFFSET _u(0x000000b8) -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_BITS _u(0xffffffff) -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_FULL_1 -// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit -// is set to indicate the data is valid. For an OUT transfer (RX -// from the host) this bit should be left as a 0. The host will -// set it when it has filled the buffer with data. -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_FULL_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_FULL_1_MSB _u(31) -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_FULL_1_LSB _u(31) -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LAST_1 -// Description : Buffer 1 is the last buffer of the transfer. -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LAST_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LAST_1_MSB _u(30) -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LAST_1_LSB _u(30) -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_PID_1 -// Description : The data pid of buffer 1. -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_PID_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_PID_1_MSB _u(29) -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_PID_1_LSB _u(29) -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_PID_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET -// Description : The number of bytes buffer 1 is offset from buffer 0 in -// Isochronous mode. Only valid in double buffered mode for an -// Isochronous endpoint. -// For a non Isochronous endpoint the offset is always 64 bytes. -// 0x0 -> 128 -// 0x1 -> 256 -// 0x2 -> 512 -// 0x3 -> 1024 -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_AVAILABLE_1 -// Description : Buffer 1 is available. This bit is set to indicate the buffer -// can be used by the controller. The controller clears the -// available bit when writing the status back. -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_1 -// Description : The length of the data in buffer 1. -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_1_MSB _u(25) -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_1_LSB _u(16) -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_FULL_0 -// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit -// is set to indicate the data is valid. For an OUT transfer (RX -// from the host) this bit should be left as a 0. The host will -// set it when it has filled the buffer with data. -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_FULL_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_FULL_0_MSB _u(15) -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_FULL_0_LSB _u(15) -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LAST_0 -// Description : Buffer 0 is the last buffer of the transfer. -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LAST_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LAST_0_MSB _u(14) -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LAST_0_LSB _u(14) -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_PID_0 -// Description : The data pid of buffer 0. -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_PID_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_PID_0_MSB _u(13) -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_PID_0_LSB _u(13) -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_PID_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_RESET -// Description : Reset the buffer selector to buffer 0. -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_RESET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_RESET_BITS _u(0x00001000) -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_RESET_MSB _u(12) -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_RESET_LSB _u(12) -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_RESET_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_STALL -// Description : Reply with a stall (valid for both buffers). -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_STALL_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_STALL_BITS _u(0x00000800) -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_STALL_MSB _u(11) -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_STALL_LSB _u(11) -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_STALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_AVAILABLE_0 -// Description : Buffer 0 is available. This bit is set to indicate the buffer -// can be used by the controller. The controller clears the -// available bit when writing the status back. -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_0 -// Description : The length of the data in buffer 1. -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_0_MSB _u(9) -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_0_LSB _u(0) -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" -// ============================================================================= -// Register : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL -// Description : Buffer control for both buffers of an endpoint. Fields ending -// in a _1 are for buffer 1. -// Fields ending in a _0 are for buffer 0. Buffer 1 controls are -// only valid if the endpoint is in double buffered mode. -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_OFFSET _u(0x000000bc) -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_BITS _u(0xffffffff) -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_FULL_1 -// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit -// is set to indicate the data is valid. For an OUT transfer (RX -// from the host) this bit should be left as a 0. The host will -// set it when it has filled the buffer with data. -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_FULL_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_FULL_1_MSB _u(31) -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_FULL_1_LSB _u(31) -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LAST_1 -// Description : Buffer 1 is the last buffer of the transfer. -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LAST_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LAST_1_MSB _u(30) -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LAST_1_LSB _u(30) -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_PID_1 -// Description : The data pid of buffer 1. -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_PID_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_PID_1_MSB _u(29) -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_PID_1_LSB _u(29) -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET -// Description : The number of bytes buffer 1 is offset from buffer 0 in -// Isochronous mode. Only valid in double buffered mode for an -// Isochronous endpoint. -// For a non Isochronous endpoint the offset is always 64 bytes. -// 0x0 -> 128 -// 0x1 -> 256 -// 0x2 -> 512 -// 0x3 -> 1024 -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_AVAILABLE_1 -// Description : Buffer 1 is available. This bit is set to indicate the buffer -// can be used by the controller. The controller clears the -// available bit when writing the status back. -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_1 -// Description : The length of the data in buffer 1. -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_1_MSB _u(25) -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_1_LSB _u(16) -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_FULL_0 -// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit -// is set to indicate the data is valid. For an OUT transfer (RX -// from the host) this bit should be left as a 0. The host will -// set it when it has filled the buffer with data. -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_FULL_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_FULL_0_MSB _u(15) -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_FULL_0_LSB _u(15) -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LAST_0 -// Description : Buffer 0 is the last buffer of the transfer. -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LAST_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LAST_0_MSB _u(14) -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LAST_0_LSB _u(14) -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_PID_0 -// Description : The data pid of buffer 0. -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_PID_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_PID_0_MSB _u(13) -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_PID_0_LSB _u(13) -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_RESET -// Description : Reset the buffer selector to buffer 0. -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_RESET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_RESET_BITS _u(0x00001000) -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_RESET_MSB _u(12) -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_RESET_LSB _u(12) -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_RESET_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_STALL -// Description : Reply with a stall (valid for both buffers). -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_STALL_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_STALL_BITS _u(0x00000800) -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_STALL_MSB _u(11) -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_STALL_LSB _u(11) -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_STALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_AVAILABLE_0 -// Description : Buffer 0 is available. This bit is set to indicate the buffer -// can be used by the controller. The controller clears the -// available bit when writing the status back. -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_0 -// Description : The length of the data in buffer 1. -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_0_MSB _u(9) -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_0_LSB _u(0) -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" -// ============================================================================= -// Register : USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL -// Description : Buffer control for both buffers of an endpoint. Fields ending -// in a _1 are for buffer 1. -// Fields ending in a _0 are for buffer 0. Buffer 1 controls are -// only valid if the endpoint is in double buffered mode. -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_OFFSET _u(0x000000c0) -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_BITS _u(0xffffffff) -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_FULL_1 -// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit -// is set to indicate the data is valid. For an OUT transfer (RX -// from the host) this bit should be left as a 0. The host will -// set it when it has filled the buffer with data. -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_FULL_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_FULL_1_MSB _u(31) -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_FULL_1_LSB _u(31) -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LAST_1 -// Description : Buffer 1 is the last buffer of the transfer. -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LAST_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LAST_1_MSB _u(30) -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LAST_1_LSB _u(30) -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_PID_1 -// Description : The data pid of buffer 1. -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_PID_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_PID_1_MSB _u(29) -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_PID_1_LSB _u(29) -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_PID_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET -// Description : The number of bytes buffer 1 is offset from buffer 0 in -// Isochronous mode. Only valid in double buffered mode for an -// Isochronous endpoint. -// For a non Isochronous endpoint the offset is always 64 bytes. -// 0x0 -> 128 -// 0x1 -> 256 -// 0x2 -> 512 -// 0x3 -> 1024 -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_AVAILABLE_1 -// Description : Buffer 1 is available. This bit is set to indicate the buffer -// can be used by the controller. The controller clears the -// available bit when writing the status back. -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_1 -// Description : The length of the data in buffer 1. -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_1_MSB _u(25) -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_1_LSB _u(16) -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_FULL_0 -// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit -// is set to indicate the data is valid. For an OUT transfer (RX -// from the host) this bit should be left as a 0. The host will -// set it when it has filled the buffer with data. -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_FULL_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_FULL_0_MSB _u(15) -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_FULL_0_LSB _u(15) -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LAST_0 -// Description : Buffer 0 is the last buffer of the transfer. -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LAST_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LAST_0_MSB _u(14) -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LAST_0_LSB _u(14) -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_PID_0 -// Description : The data pid of buffer 0. -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_PID_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_PID_0_MSB _u(13) -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_PID_0_LSB _u(13) -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_PID_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_RESET -// Description : Reset the buffer selector to buffer 0. -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_RESET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_RESET_BITS _u(0x00001000) -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_RESET_MSB _u(12) -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_RESET_LSB _u(12) -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_RESET_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_STALL -// Description : Reply with a stall (valid for both buffers). -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_STALL_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_STALL_BITS _u(0x00000800) -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_STALL_MSB _u(11) -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_STALL_LSB _u(11) -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_STALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_AVAILABLE_0 -// Description : Buffer 0 is available. This bit is set to indicate the buffer -// can be used by the controller. The controller clears the -// available bit when writing the status back. -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_0 -// Description : The length of the data in buffer 1. -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_0_MSB _u(9) -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_0_LSB _u(0) -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" -// ============================================================================= -// Register : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL -// Description : Buffer control for both buffers of an endpoint. Fields ending -// in a _1 are for buffer 1. -// Fields ending in a _0 are for buffer 0. Buffer 1 controls are -// only valid if the endpoint is in double buffered mode. -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_OFFSET _u(0x000000c4) -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_BITS _u(0xffffffff) -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_FULL_1 -// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit -// is set to indicate the data is valid. For an OUT transfer (RX -// from the host) this bit should be left as a 0. The host will -// set it when it has filled the buffer with data. -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_FULL_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_FULL_1_MSB _u(31) -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_FULL_1_LSB _u(31) -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LAST_1 -// Description : Buffer 1 is the last buffer of the transfer. -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LAST_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LAST_1_MSB _u(30) -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LAST_1_LSB _u(30) -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_PID_1 -// Description : The data pid of buffer 1. -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_PID_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_PID_1_MSB _u(29) -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_PID_1_LSB _u(29) -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET -// Description : The number of bytes buffer 1 is offset from buffer 0 in -// Isochronous mode. Only valid in double buffered mode for an -// Isochronous endpoint. -// For a non Isochronous endpoint the offset is always 64 bytes. -// 0x0 -> 128 -// 0x1 -> 256 -// 0x2 -> 512 -// 0x3 -> 1024 -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_AVAILABLE_1 -// Description : Buffer 1 is available. This bit is set to indicate the buffer -// can be used by the controller. The controller clears the -// available bit when writing the status back. -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_1 -// Description : The length of the data in buffer 1. -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_1_MSB _u(25) -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_1_LSB _u(16) -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_FULL_0 -// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit -// is set to indicate the data is valid. For an OUT transfer (RX -// from the host) this bit should be left as a 0. The host will -// set it when it has filled the buffer with data. -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_FULL_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_FULL_0_MSB _u(15) -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_FULL_0_LSB _u(15) -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LAST_0 -// Description : Buffer 0 is the last buffer of the transfer. -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LAST_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LAST_0_MSB _u(14) -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LAST_0_LSB _u(14) -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_PID_0 -// Description : The data pid of buffer 0. -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_PID_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_PID_0_MSB _u(13) -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_PID_0_LSB _u(13) -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_RESET -// Description : Reset the buffer selector to buffer 0. -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_RESET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_RESET_BITS _u(0x00001000) -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_RESET_MSB _u(12) -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_RESET_LSB _u(12) -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_RESET_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_STALL -// Description : Reply with a stall (valid for both buffers). -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_STALL_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_STALL_BITS _u(0x00000800) -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_STALL_MSB _u(11) -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_STALL_LSB _u(11) -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_STALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_AVAILABLE_0 -// Description : Buffer 0 is available. This bit is set to indicate the buffer -// can be used by the controller. The controller clears the -// available bit when writing the status back. -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_0 -// Description : The length of the data in buffer 1. -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_0_MSB _u(9) -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_0_LSB _u(0) -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" -// ============================================================================= -// Register : USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL -// Description : Buffer control for both buffers of an endpoint. Fields ending -// in a _1 are for buffer 1. -// Fields ending in a _0 are for buffer 0. Buffer 1 controls are -// only valid if the endpoint is in double buffered mode. -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_OFFSET _u(0x000000c8) -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_BITS _u(0xffffffff) -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_FULL_1 -// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit -// is set to indicate the data is valid. For an OUT transfer (RX -// from the host) this bit should be left as a 0. The host will -// set it when it has filled the buffer with data. -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_FULL_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_FULL_1_MSB _u(31) -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_FULL_1_LSB _u(31) -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LAST_1 -// Description : Buffer 1 is the last buffer of the transfer. -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LAST_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LAST_1_MSB _u(30) -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LAST_1_LSB _u(30) -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_PID_1 -// Description : The data pid of buffer 1. -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_PID_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_PID_1_MSB _u(29) -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_PID_1_LSB _u(29) -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_PID_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET -// Description : The number of bytes buffer 1 is offset from buffer 0 in -// Isochronous mode. Only valid in double buffered mode for an -// Isochronous endpoint. -// For a non Isochronous endpoint the offset is always 64 bytes. -// 0x0 -> 128 -// 0x1 -> 256 -// 0x2 -> 512 -// 0x3 -> 1024 -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_AVAILABLE_1 -// Description : Buffer 1 is available. This bit is set to indicate the buffer -// can be used by the controller. The controller clears the -// available bit when writing the status back. -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_1 -// Description : The length of the data in buffer 1. -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_1_MSB _u(25) -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_1_LSB _u(16) -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_FULL_0 -// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit -// is set to indicate the data is valid. For an OUT transfer (RX -// from the host) this bit should be left as a 0. The host will -// set it when it has filled the buffer with data. -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_FULL_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_FULL_0_MSB _u(15) -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_FULL_0_LSB _u(15) -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LAST_0 -// Description : Buffer 0 is the last buffer of the transfer. -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LAST_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LAST_0_MSB _u(14) -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LAST_0_LSB _u(14) -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_PID_0 -// Description : The data pid of buffer 0. -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_PID_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_PID_0_MSB _u(13) -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_PID_0_LSB _u(13) -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_PID_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_RESET -// Description : Reset the buffer selector to buffer 0. -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_RESET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_RESET_BITS _u(0x00001000) -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_RESET_MSB _u(12) -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_RESET_LSB _u(12) -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_RESET_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_STALL -// Description : Reply with a stall (valid for both buffers). -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_STALL_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_STALL_BITS _u(0x00000800) -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_STALL_MSB _u(11) -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_STALL_LSB _u(11) -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_STALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_AVAILABLE_0 -// Description : Buffer 0 is available. This bit is set to indicate the buffer -// can be used by the controller. The controller clears the -// available bit when writing the status back. -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_0 -// Description : The length of the data in buffer 1. -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_0_MSB _u(9) -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_0_LSB _u(0) -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" -// ============================================================================= -// Register : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL -// Description : Buffer control for both buffers of an endpoint. Fields ending -// in a _1 are for buffer 1. -// Fields ending in a _0 are for buffer 0. Buffer 1 controls are -// only valid if the endpoint is in double buffered mode. -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_OFFSET _u(0x000000cc) -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_BITS _u(0xffffffff) -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_FULL_1 -// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit -// is set to indicate the data is valid. For an OUT transfer (RX -// from the host) this bit should be left as a 0. The host will -// set it when it has filled the buffer with data. -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_FULL_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_FULL_1_MSB _u(31) -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_FULL_1_LSB _u(31) -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LAST_1 -// Description : Buffer 1 is the last buffer of the transfer. -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LAST_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LAST_1_MSB _u(30) -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LAST_1_LSB _u(30) -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_PID_1 -// Description : The data pid of buffer 1. -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_PID_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_PID_1_MSB _u(29) -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_PID_1_LSB _u(29) -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET -// Description : The number of bytes buffer 1 is offset from buffer 0 in -// Isochronous mode. Only valid in double buffered mode for an -// Isochronous endpoint. -// For a non Isochronous endpoint the offset is always 64 bytes. -// 0x0 -> 128 -// 0x1 -> 256 -// 0x2 -> 512 -// 0x3 -> 1024 -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_AVAILABLE_1 -// Description : Buffer 1 is available. This bit is set to indicate the buffer -// can be used by the controller. The controller clears the -// available bit when writing the status back. -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_1 -// Description : The length of the data in buffer 1. -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_1_MSB _u(25) -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_1_LSB _u(16) -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_FULL_0 -// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit -// is set to indicate the data is valid. For an OUT transfer (RX -// from the host) this bit should be left as a 0. The host will -// set it when it has filled the buffer with data. -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_FULL_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_FULL_0_MSB _u(15) -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_FULL_0_LSB _u(15) -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LAST_0 -// Description : Buffer 0 is the last buffer of the transfer. -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LAST_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LAST_0_MSB _u(14) -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LAST_0_LSB _u(14) -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_PID_0 -// Description : The data pid of buffer 0. -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_PID_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_PID_0_MSB _u(13) -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_PID_0_LSB _u(13) -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_RESET -// Description : Reset the buffer selector to buffer 0. -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_RESET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_RESET_BITS _u(0x00001000) -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_RESET_MSB _u(12) -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_RESET_LSB _u(12) -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_RESET_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_STALL -// Description : Reply with a stall (valid for both buffers). -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_STALL_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_STALL_BITS _u(0x00000800) -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_STALL_MSB _u(11) -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_STALL_LSB _u(11) -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_STALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_AVAILABLE_0 -// Description : Buffer 0 is available. This bit is set to indicate the buffer -// can be used by the controller. The controller clears the -// available bit when writing the status back. -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_0 -// Description : The length of the data in buffer 1. -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_0_MSB _u(9) -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_0_LSB _u(0) -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" -// ============================================================================= -// Register : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL -// Description : Buffer control for both buffers of an endpoint. Fields ending -// in a _1 are for buffer 1. -// Fields ending in a _0 are for buffer 0. Buffer 1 controls are -// only valid if the endpoint is in double buffered mode. -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_OFFSET _u(0x000000d0) -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_BITS _u(0xffffffff) -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_FULL_1 -// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit -// is set to indicate the data is valid. For an OUT transfer (RX -// from the host) this bit should be left as a 0. The host will -// set it when it has filled the buffer with data. -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_FULL_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_FULL_1_MSB _u(31) -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_FULL_1_LSB _u(31) -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LAST_1 -// Description : Buffer 1 is the last buffer of the transfer. -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LAST_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LAST_1_MSB _u(30) -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LAST_1_LSB _u(30) -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_PID_1 -// Description : The data pid of buffer 1. -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_PID_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_PID_1_MSB _u(29) -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_PID_1_LSB _u(29) -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_PID_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET -// Description : The number of bytes buffer 1 is offset from buffer 0 in -// Isochronous mode. Only valid in double buffered mode for an -// Isochronous endpoint. -// For a non Isochronous endpoint the offset is always 64 bytes. -// 0x0 -> 128 -// 0x1 -> 256 -// 0x2 -> 512 -// 0x3 -> 1024 -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_AVAILABLE_1 -// Description : Buffer 1 is available. This bit is set to indicate the buffer -// can be used by the controller. The controller clears the -// available bit when writing the status back. -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_1 -// Description : The length of the data in buffer 1. -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_1_MSB _u(25) -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_1_LSB _u(16) -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_FULL_0 -// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit -// is set to indicate the data is valid. For an OUT transfer (RX -// from the host) this bit should be left as a 0. The host will -// set it when it has filled the buffer with data. -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_FULL_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_FULL_0_MSB _u(15) -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_FULL_0_LSB _u(15) -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LAST_0 -// Description : Buffer 0 is the last buffer of the transfer. -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LAST_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LAST_0_MSB _u(14) -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LAST_0_LSB _u(14) -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_PID_0 -// Description : The data pid of buffer 0. -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_PID_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_PID_0_MSB _u(13) -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_PID_0_LSB _u(13) -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_PID_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_RESET -// Description : Reset the buffer selector to buffer 0. -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_RESET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_RESET_BITS _u(0x00001000) -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_RESET_MSB _u(12) -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_RESET_LSB _u(12) -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_RESET_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_STALL -// Description : Reply with a stall (valid for both buffers). -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_STALL_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_STALL_BITS _u(0x00000800) -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_STALL_MSB _u(11) -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_STALL_LSB _u(11) -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_STALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_AVAILABLE_0 -// Description : Buffer 0 is available. This bit is set to indicate the buffer -// can be used by the controller. The controller clears the -// available bit when writing the status back. -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_0 -// Description : The length of the data in buffer 1. -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_0_MSB _u(9) -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_0_LSB _u(0) -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" -// ============================================================================= -// Register : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL -// Description : Buffer control for both buffers of an endpoint. Fields ending -// in a _1 are for buffer 1. -// Fields ending in a _0 are for buffer 0. Buffer 1 controls are -// only valid if the endpoint is in double buffered mode. -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_OFFSET _u(0x000000d4) -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_BITS _u(0xffffffff) -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_FULL_1 -// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit -// is set to indicate the data is valid. For an OUT transfer (RX -// from the host) this bit should be left as a 0. The host will -// set it when it has filled the buffer with data. -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_FULL_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_FULL_1_MSB _u(31) -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_FULL_1_LSB _u(31) -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LAST_1 -// Description : Buffer 1 is the last buffer of the transfer. -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LAST_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LAST_1_MSB _u(30) -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LAST_1_LSB _u(30) -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_PID_1 -// Description : The data pid of buffer 1. -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_PID_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_PID_1_MSB _u(29) -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_PID_1_LSB _u(29) -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET -// Description : The number of bytes buffer 1 is offset from buffer 0 in -// Isochronous mode. Only valid in double buffered mode for an -// Isochronous endpoint. -// For a non Isochronous endpoint the offset is always 64 bytes. -// 0x0 -> 128 -// 0x1 -> 256 -// 0x2 -> 512 -// 0x3 -> 1024 -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_AVAILABLE_1 -// Description : Buffer 1 is available. This bit is set to indicate the buffer -// can be used by the controller. The controller clears the -// available bit when writing the status back. -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_1 -// Description : The length of the data in buffer 1. -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_1_MSB _u(25) -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_1_LSB _u(16) -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_FULL_0 -// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit -// is set to indicate the data is valid. For an OUT transfer (RX -// from the host) this bit should be left as a 0. The host will -// set it when it has filled the buffer with data. -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_FULL_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_FULL_0_MSB _u(15) -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_FULL_0_LSB _u(15) -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LAST_0 -// Description : Buffer 0 is the last buffer of the transfer. -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LAST_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LAST_0_MSB _u(14) -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LAST_0_LSB _u(14) -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_PID_0 -// Description : The data pid of buffer 0. -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_PID_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_PID_0_MSB _u(13) -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_PID_0_LSB _u(13) -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_RESET -// Description : Reset the buffer selector to buffer 0. -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_RESET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_RESET_BITS _u(0x00001000) -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_RESET_MSB _u(12) -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_RESET_LSB _u(12) -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_RESET_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_STALL -// Description : Reply with a stall (valid for both buffers). -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_STALL_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_STALL_BITS _u(0x00000800) -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_STALL_MSB _u(11) -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_STALL_LSB _u(11) -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_STALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_AVAILABLE_0 -// Description : Buffer 0 is available. This bit is set to indicate the buffer -// can be used by the controller. The controller clears the -// available bit when writing the status back. -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_0 -// Description : The length of the data in buffer 1. -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_0_MSB _u(9) -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_0_LSB _u(0) -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" -// ============================================================================= -// Register : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL -// Description : Buffer control for both buffers of an endpoint. Fields ending -// in a _1 are for buffer 1. -// Fields ending in a _0 are for buffer 0. Buffer 1 controls are -// only valid if the endpoint is in double buffered mode. -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_OFFSET _u(0x000000d8) -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_BITS _u(0xffffffff) -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_FULL_1 -// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit -// is set to indicate the data is valid. For an OUT transfer (RX -// from the host) this bit should be left as a 0. The host will -// set it when it has filled the buffer with data. -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_FULL_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_FULL_1_MSB _u(31) -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_FULL_1_LSB _u(31) -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LAST_1 -// Description : Buffer 1 is the last buffer of the transfer. -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LAST_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LAST_1_MSB _u(30) -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LAST_1_LSB _u(30) -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_PID_1 -// Description : The data pid of buffer 1. -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_PID_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_PID_1_MSB _u(29) -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_PID_1_LSB _u(29) -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_PID_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET -// Description : The number of bytes buffer 1 is offset from buffer 0 in -// Isochronous mode. Only valid in double buffered mode for an -// Isochronous endpoint. -// For a non Isochronous endpoint the offset is always 64 bytes. -// 0x0 -> 128 -// 0x1 -> 256 -// 0x2 -> 512 -// 0x3 -> 1024 -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_AVAILABLE_1 -// Description : Buffer 1 is available. This bit is set to indicate the buffer -// can be used by the controller. The controller clears the -// available bit when writing the status back. -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_1 -// Description : The length of the data in buffer 1. -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_1_MSB _u(25) -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_1_LSB _u(16) -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_FULL_0 -// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit -// is set to indicate the data is valid. For an OUT transfer (RX -// from the host) this bit should be left as a 0. The host will -// set it when it has filled the buffer with data. -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_FULL_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_FULL_0_MSB _u(15) -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_FULL_0_LSB _u(15) -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LAST_0 -// Description : Buffer 0 is the last buffer of the transfer. -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LAST_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LAST_0_MSB _u(14) -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LAST_0_LSB _u(14) -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_PID_0 -// Description : The data pid of buffer 0. -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_PID_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_PID_0_MSB _u(13) -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_PID_0_LSB _u(13) -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_PID_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_RESET -// Description : Reset the buffer selector to buffer 0. -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_RESET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_RESET_BITS _u(0x00001000) -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_RESET_MSB _u(12) -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_RESET_LSB _u(12) -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_RESET_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_STALL -// Description : Reply with a stall (valid for both buffers). -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_STALL_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_STALL_BITS _u(0x00000800) -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_STALL_MSB _u(11) -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_STALL_LSB _u(11) -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_STALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_AVAILABLE_0 -// Description : Buffer 0 is available. This bit is set to indicate the buffer -// can be used by the controller. The controller clears the -// available bit when writing the status back. -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_0 -// Description : The length of the data in buffer 1. -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_0_MSB _u(9) -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_0_LSB _u(0) -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" -// ============================================================================= -// Register : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL -// Description : Buffer control for both buffers of an endpoint. Fields ending -// in a _1 are for buffer 1. -// Fields ending in a _0 are for buffer 0. Buffer 1 controls are -// only valid if the endpoint is in double buffered mode. -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_OFFSET _u(0x000000dc) -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_BITS _u(0xffffffff) -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_FULL_1 -// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit -// is set to indicate the data is valid. For an OUT transfer (RX -// from the host) this bit should be left as a 0. The host will -// set it when it has filled the buffer with data. -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_FULL_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_FULL_1_MSB _u(31) -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_FULL_1_LSB _u(31) -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LAST_1 -// Description : Buffer 1 is the last buffer of the transfer. -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LAST_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LAST_1_MSB _u(30) -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LAST_1_LSB _u(30) -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_PID_1 -// Description : The data pid of buffer 1. -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_PID_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_PID_1_MSB _u(29) -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_PID_1_LSB _u(29) -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET -// Description : The number of bytes buffer 1 is offset from buffer 0 in -// Isochronous mode. Only valid in double buffered mode for an -// Isochronous endpoint. -// For a non Isochronous endpoint the offset is always 64 bytes. -// 0x0 -> 128 -// 0x1 -> 256 -// 0x2 -> 512 -// 0x3 -> 1024 -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_AVAILABLE_1 -// Description : Buffer 1 is available. This bit is set to indicate the buffer -// can be used by the controller. The controller clears the -// available bit when writing the status back. -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_1 -// Description : The length of the data in buffer 1. -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_1_MSB _u(25) -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_1_LSB _u(16) -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_FULL_0 -// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit -// is set to indicate the data is valid. For an OUT transfer (RX -// from the host) this bit should be left as a 0. The host will -// set it when it has filled the buffer with data. -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_FULL_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_FULL_0_MSB _u(15) -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_FULL_0_LSB _u(15) -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LAST_0 -// Description : Buffer 0 is the last buffer of the transfer. -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LAST_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LAST_0_MSB _u(14) -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LAST_0_LSB _u(14) -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_PID_0 -// Description : The data pid of buffer 0. -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_PID_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_PID_0_MSB _u(13) -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_PID_0_LSB _u(13) -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_RESET -// Description : Reset the buffer selector to buffer 0. -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_RESET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_RESET_BITS _u(0x00001000) -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_RESET_MSB _u(12) -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_RESET_LSB _u(12) -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_RESET_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_STALL -// Description : Reply with a stall (valid for both buffers). -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_STALL_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_STALL_BITS _u(0x00000800) -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_STALL_MSB _u(11) -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_STALL_LSB _u(11) -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_STALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_AVAILABLE_0 -// Description : Buffer 0 is available. This bit is set to indicate the buffer -// can be used by the controller. The controller clears the -// available bit when writing the status back. -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_0 -// Description : The length of the data in buffer 1. -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_0_MSB _u(9) -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_0_LSB _u(0) -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" -// ============================================================================= -// Register : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL -// Description : Buffer control for both buffers of an endpoint. Fields ending -// in a _1 are for buffer 1. -// Fields ending in a _0 are for buffer 0. Buffer 1 controls are -// only valid if the endpoint is in double buffered mode. -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_OFFSET _u(0x000000e0) -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_BITS _u(0xffffffff) -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_FULL_1 -// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit -// is set to indicate the data is valid. For an OUT transfer (RX -// from the host) this bit should be left as a 0. The host will -// set it when it has filled the buffer with data. -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_FULL_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_FULL_1_MSB _u(31) -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_FULL_1_LSB _u(31) -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LAST_1 -// Description : Buffer 1 is the last buffer of the transfer. -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LAST_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LAST_1_MSB _u(30) -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LAST_1_LSB _u(30) -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_PID_1 -// Description : The data pid of buffer 1. -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_PID_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_PID_1_MSB _u(29) -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_PID_1_LSB _u(29) -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_PID_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET -// Description : The number of bytes buffer 1 is offset from buffer 0 in -// Isochronous mode. Only valid in double buffered mode for an -// Isochronous endpoint. -// For a non Isochronous endpoint the offset is always 64 bytes. -// 0x0 -> 128 -// 0x1 -> 256 -// 0x2 -> 512 -// 0x3 -> 1024 -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_AVAILABLE_1 -// Description : Buffer 1 is available. This bit is set to indicate the buffer -// can be used by the controller. The controller clears the -// available bit when writing the status back. -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_1 -// Description : The length of the data in buffer 1. -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_1_MSB _u(25) -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_1_LSB _u(16) -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_FULL_0 -// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit -// is set to indicate the data is valid. For an OUT transfer (RX -// from the host) this bit should be left as a 0. The host will -// set it when it has filled the buffer with data. -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_FULL_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_FULL_0_MSB _u(15) -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_FULL_0_LSB _u(15) -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LAST_0 -// Description : Buffer 0 is the last buffer of the transfer. -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LAST_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LAST_0_MSB _u(14) -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LAST_0_LSB _u(14) -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_PID_0 -// Description : The data pid of buffer 0. -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_PID_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_PID_0_MSB _u(13) -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_PID_0_LSB _u(13) -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_PID_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_RESET -// Description : Reset the buffer selector to buffer 0. -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_RESET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_RESET_BITS _u(0x00001000) -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_RESET_MSB _u(12) -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_RESET_LSB _u(12) -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_RESET_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_STALL -// Description : Reply with a stall (valid for both buffers). -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_STALL_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_STALL_BITS _u(0x00000800) -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_STALL_MSB _u(11) -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_STALL_LSB _u(11) -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_STALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_AVAILABLE_0 -// Description : Buffer 0 is available. This bit is set to indicate the buffer -// can be used by the controller. The controller clears the -// available bit when writing the status back. -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_0 -// Description : The length of the data in buffer 1. -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_0_MSB _u(9) -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_0_LSB _u(0) -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" -// ============================================================================= -// Register : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL -// Description : Buffer control for both buffers of an endpoint. Fields ending -// in a _1 are for buffer 1. -// Fields ending in a _0 are for buffer 0. Buffer 1 controls are -// only valid if the endpoint is in double buffered mode. -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_OFFSET _u(0x000000e4) -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_BITS _u(0xffffffff) -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_FULL_1 -// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit -// is set to indicate the data is valid. For an OUT transfer (RX -// from the host) this bit should be left as a 0. The host will -// set it when it has filled the buffer with data. -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_FULL_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_FULL_1_MSB _u(31) -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_FULL_1_LSB _u(31) -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LAST_1 -// Description : Buffer 1 is the last buffer of the transfer. -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LAST_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LAST_1_MSB _u(30) -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LAST_1_LSB _u(30) -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_PID_1 -// Description : The data pid of buffer 1. -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_PID_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_PID_1_MSB _u(29) -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_PID_1_LSB _u(29) -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET -// Description : The number of bytes buffer 1 is offset from buffer 0 in -// Isochronous mode. Only valid in double buffered mode for an -// Isochronous endpoint. -// For a non Isochronous endpoint the offset is always 64 bytes. -// 0x0 -> 128 -// 0x1 -> 256 -// 0x2 -> 512 -// 0x3 -> 1024 -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_AVAILABLE_1 -// Description : Buffer 1 is available. This bit is set to indicate the buffer -// can be used by the controller. The controller clears the -// available bit when writing the status back. -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_1 -// Description : The length of the data in buffer 1. -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_1_MSB _u(25) -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_1_LSB _u(16) -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_FULL_0 -// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit -// is set to indicate the data is valid. For an OUT transfer (RX -// from the host) this bit should be left as a 0. The host will -// set it when it has filled the buffer with data. -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_FULL_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_FULL_0_MSB _u(15) -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_FULL_0_LSB _u(15) -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LAST_0 -// Description : Buffer 0 is the last buffer of the transfer. -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LAST_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LAST_0_MSB _u(14) -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LAST_0_LSB _u(14) -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_PID_0 -// Description : The data pid of buffer 0. -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_PID_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_PID_0_MSB _u(13) -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_PID_0_LSB _u(13) -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_RESET -// Description : Reset the buffer selector to buffer 0. -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_RESET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_RESET_BITS _u(0x00001000) -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_RESET_MSB _u(12) -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_RESET_LSB _u(12) -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_RESET_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_STALL -// Description : Reply with a stall (valid for both buffers). -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_STALL_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_STALL_BITS _u(0x00000800) -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_STALL_MSB _u(11) -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_STALL_LSB _u(11) -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_STALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_AVAILABLE_0 -// Description : Buffer 0 is available. This bit is set to indicate the buffer -// can be used by the controller. The controller clears the -// available bit when writing the status back. -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_0 -// Description : The length of the data in buffer 1. -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_0_MSB _u(9) -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_0_LSB _u(0) -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" -// ============================================================================= -// Register : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL -// Description : Buffer control for both buffers of an endpoint. Fields ending -// in a _1 are for buffer 1. -// Fields ending in a _0 are for buffer 0. Buffer 1 controls are -// only valid if the endpoint is in double buffered mode. -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_OFFSET _u(0x000000e8) -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_BITS _u(0xffffffff) -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_FULL_1 -// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit -// is set to indicate the data is valid. For an OUT transfer (RX -// from the host) this bit should be left as a 0. The host will -// set it when it has filled the buffer with data. -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_FULL_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_FULL_1_MSB _u(31) -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_FULL_1_LSB _u(31) -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LAST_1 -// Description : Buffer 1 is the last buffer of the transfer. -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LAST_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LAST_1_MSB _u(30) -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LAST_1_LSB _u(30) -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_PID_1 -// Description : The data pid of buffer 1. -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_PID_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_PID_1_MSB _u(29) -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_PID_1_LSB _u(29) -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_PID_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET -// Description : The number of bytes buffer 1 is offset from buffer 0 in -// Isochronous mode. Only valid in double buffered mode for an -// Isochronous endpoint. -// For a non Isochronous endpoint the offset is always 64 bytes. -// 0x0 -> 128 -// 0x1 -> 256 -// 0x2 -> 512 -// 0x3 -> 1024 -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_AVAILABLE_1 -// Description : Buffer 1 is available. This bit is set to indicate the buffer -// can be used by the controller. The controller clears the -// available bit when writing the status back. -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_1 -// Description : The length of the data in buffer 1. -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_1_MSB _u(25) -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_1_LSB _u(16) -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_FULL_0 -// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit -// is set to indicate the data is valid. For an OUT transfer (RX -// from the host) this bit should be left as a 0. The host will -// set it when it has filled the buffer with data. -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_FULL_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_FULL_0_MSB _u(15) -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_FULL_0_LSB _u(15) -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LAST_0 -// Description : Buffer 0 is the last buffer of the transfer. -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LAST_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LAST_0_MSB _u(14) -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LAST_0_LSB _u(14) -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_PID_0 -// Description : The data pid of buffer 0. -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_PID_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_PID_0_MSB _u(13) -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_PID_0_LSB _u(13) -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_PID_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_RESET -// Description : Reset the buffer selector to buffer 0. -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_RESET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_RESET_BITS _u(0x00001000) -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_RESET_MSB _u(12) -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_RESET_LSB _u(12) -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_RESET_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_STALL -// Description : Reply with a stall (valid for both buffers). -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_STALL_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_STALL_BITS _u(0x00000800) -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_STALL_MSB _u(11) -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_STALL_LSB _u(11) -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_STALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_AVAILABLE_0 -// Description : Buffer 0 is available. This bit is set to indicate the buffer -// can be used by the controller. The controller clears the -// available bit when writing the status back. -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_0 -// Description : The length of the data in buffer 1. -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_0_MSB _u(9) -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_0_LSB _u(0) -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" -// ============================================================================= -// Register : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL -// Description : Buffer control for both buffers of an endpoint. Fields ending -// in a _1 are for buffer 1. -// Fields ending in a _0 are for buffer 0. Buffer 1 controls are -// only valid if the endpoint is in double buffered mode. -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_OFFSET _u(0x000000ec) -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_BITS _u(0xffffffff) -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_FULL_1 -// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit -// is set to indicate the data is valid. For an OUT transfer (RX -// from the host) this bit should be left as a 0. The host will -// set it when it has filled the buffer with data. -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_FULL_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_FULL_1_MSB _u(31) -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_FULL_1_LSB _u(31) -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LAST_1 -// Description : Buffer 1 is the last buffer of the transfer. -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LAST_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LAST_1_MSB _u(30) -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LAST_1_LSB _u(30) -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_PID_1 -// Description : The data pid of buffer 1. -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_PID_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_PID_1_MSB _u(29) -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_PID_1_LSB _u(29) -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET -// Description : The number of bytes buffer 1 is offset from buffer 0 in -// Isochronous mode. Only valid in double buffered mode for an -// Isochronous endpoint. -// For a non Isochronous endpoint the offset is always 64 bytes. -// 0x0 -> 128 -// 0x1 -> 256 -// 0x2 -> 512 -// 0x3 -> 1024 -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_AVAILABLE_1 -// Description : Buffer 1 is available. This bit is set to indicate the buffer -// can be used by the controller. The controller clears the -// available bit when writing the status back. -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_1 -// Description : The length of the data in buffer 1. -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_1_MSB _u(25) -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_1_LSB _u(16) -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_FULL_0 -// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit -// is set to indicate the data is valid. For an OUT transfer (RX -// from the host) this bit should be left as a 0. The host will -// set it when it has filled the buffer with data. -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_FULL_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_FULL_0_MSB _u(15) -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_FULL_0_LSB _u(15) -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LAST_0 -// Description : Buffer 0 is the last buffer of the transfer. -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LAST_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LAST_0_MSB _u(14) -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LAST_0_LSB _u(14) -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_PID_0 -// Description : The data pid of buffer 0. -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_PID_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_PID_0_MSB _u(13) -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_PID_0_LSB _u(13) -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_RESET -// Description : Reset the buffer selector to buffer 0. -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_RESET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_RESET_BITS _u(0x00001000) -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_RESET_MSB _u(12) -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_RESET_LSB _u(12) -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_RESET_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_STALL -// Description : Reply with a stall (valid for both buffers). -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_STALL_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_STALL_BITS _u(0x00000800) -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_STALL_MSB _u(11) -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_STALL_LSB _u(11) -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_STALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_AVAILABLE_0 -// Description : Buffer 0 is available. This bit is set to indicate the buffer -// can be used by the controller. The controller clears the -// available bit when writing the status back. -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_0 -// Description : The length of the data in buffer 1. -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_0_MSB _u(9) -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_0_LSB _u(0) -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" -// ============================================================================= -// Register : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL -// Description : Buffer control for both buffers of an endpoint. Fields ending -// in a _1 are for buffer 1. -// Fields ending in a _0 are for buffer 0. Buffer 1 controls are -// only valid if the endpoint is in double buffered mode. -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_OFFSET _u(0x000000f0) -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_BITS _u(0xffffffff) -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_FULL_1 -// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit -// is set to indicate the data is valid. For an OUT transfer (RX -// from the host) this bit should be left as a 0. The host will -// set it when it has filled the buffer with data. -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_FULL_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_FULL_1_MSB _u(31) -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_FULL_1_LSB _u(31) -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LAST_1 -// Description : Buffer 1 is the last buffer of the transfer. -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LAST_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LAST_1_MSB _u(30) -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LAST_1_LSB _u(30) -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_PID_1 -// Description : The data pid of buffer 1. -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_PID_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_PID_1_MSB _u(29) -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_PID_1_LSB _u(29) -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_PID_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET -// Description : The number of bytes buffer 1 is offset from buffer 0 in -// Isochronous mode. Only valid in double buffered mode for an -// Isochronous endpoint. -// For a non Isochronous endpoint the offset is always 64 bytes. -// 0x0 -> 128 -// 0x1 -> 256 -// 0x2 -> 512 -// 0x3 -> 1024 -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_AVAILABLE_1 -// Description : Buffer 1 is available. This bit is set to indicate the buffer -// can be used by the controller. The controller clears the -// available bit when writing the status back. -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_1 -// Description : The length of the data in buffer 1. -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_1_MSB _u(25) -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_1_LSB _u(16) -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_FULL_0 -// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit -// is set to indicate the data is valid. For an OUT transfer (RX -// from the host) this bit should be left as a 0. The host will -// set it when it has filled the buffer with data. -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_FULL_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_FULL_0_MSB _u(15) -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_FULL_0_LSB _u(15) -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LAST_0 -// Description : Buffer 0 is the last buffer of the transfer. -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LAST_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LAST_0_MSB _u(14) -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LAST_0_LSB _u(14) -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_PID_0 -// Description : The data pid of buffer 0. -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_PID_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_PID_0_MSB _u(13) -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_PID_0_LSB _u(13) -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_PID_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_RESET -// Description : Reset the buffer selector to buffer 0. -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_RESET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_RESET_BITS _u(0x00001000) -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_RESET_MSB _u(12) -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_RESET_LSB _u(12) -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_RESET_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_STALL -// Description : Reply with a stall (valid for both buffers). -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_STALL_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_STALL_BITS _u(0x00000800) -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_STALL_MSB _u(11) -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_STALL_LSB _u(11) -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_STALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_AVAILABLE_0 -// Description : Buffer 0 is available. This bit is set to indicate the buffer -// can be used by the controller. The controller clears the -// available bit when writing the status back. -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_0 -// Description : The length of the data in buffer 1. -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_0_MSB _u(9) -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_0_LSB _u(0) -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" -// ============================================================================= -// Register : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL -// Description : Buffer control for both buffers of an endpoint. Fields ending -// in a _1 are for buffer 1. -// Fields ending in a _0 are for buffer 0. Buffer 1 controls are -// only valid if the endpoint is in double buffered mode. -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_OFFSET _u(0x000000f4) -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_BITS _u(0xffffffff) -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_FULL_1 -// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit -// is set to indicate the data is valid. For an OUT transfer (RX -// from the host) this bit should be left as a 0. The host will -// set it when it has filled the buffer with data. -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_FULL_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_FULL_1_MSB _u(31) -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_FULL_1_LSB _u(31) -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LAST_1 -// Description : Buffer 1 is the last buffer of the transfer. -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LAST_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LAST_1_MSB _u(30) -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LAST_1_LSB _u(30) -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_PID_1 -// Description : The data pid of buffer 1. -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_PID_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_PID_1_MSB _u(29) -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_PID_1_LSB _u(29) -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET -// Description : The number of bytes buffer 1 is offset from buffer 0 in -// Isochronous mode. Only valid in double buffered mode for an -// Isochronous endpoint. -// For a non Isochronous endpoint the offset is always 64 bytes. -// 0x0 -> 128 -// 0x1 -> 256 -// 0x2 -> 512 -// 0x3 -> 1024 -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_AVAILABLE_1 -// Description : Buffer 1 is available. This bit is set to indicate the buffer -// can be used by the controller. The controller clears the -// available bit when writing the status back. -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_1 -// Description : The length of the data in buffer 1. -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_1_MSB _u(25) -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_1_LSB _u(16) -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_FULL_0 -// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit -// is set to indicate the data is valid. For an OUT transfer (RX -// from the host) this bit should be left as a 0. The host will -// set it when it has filled the buffer with data. -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_FULL_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_FULL_0_MSB _u(15) -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_FULL_0_LSB _u(15) -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LAST_0 -// Description : Buffer 0 is the last buffer of the transfer. -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LAST_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LAST_0_MSB _u(14) -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LAST_0_LSB _u(14) -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_PID_0 -// Description : The data pid of buffer 0. -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_PID_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_PID_0_MSB _u(13) -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_PID_0_LSB _u(13) -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_RESET -// Description : Reset the buffer selector to buffer 0. -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_RESET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_RESET_BITS _u(0x00001000) -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_RESET_MSB _u(12) -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_RESET_LSB _u(12) -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_RESET_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_STALL -// Description : Reply with a stall (valid for both buffers). -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_STALL_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_STALL_BITS _u(0x00000800) -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_STALL_MSB _u(11) -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_STALL_LSB _u(11) -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_STALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_AVAILABLE_0 -// Description : Buffer 0 is available. This bit is set to indicate the buffer -// can be used by the controller. The controller clears the -// available bit when writing the status back. -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_0 -// Description : The length of the data in buffer 1. -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_0_MSB _u(9) -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_0_LSB _u(0) -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" -// ============================================================================= -// Register : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL -// Description : Buffer control for both buffers of an endpoint. Fields ending -// in a _1 are for buffer 1. -// Fields ending in a _0 are for buffer 0. Buffer 1 controls are -// only valid if the endpoint is in double buffered mode. -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_OFFSET _u(0x000000f8) -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_BITS _u(0xffffffff) -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_FULL_1 -// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit -// is set to indicate the data is valid. For an OUT transfer (RX -// from the host) this bit should be left as a 0. The host will -// set it when it has filled the buffer with data. -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_FULL_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_FULL_1_MSB _u(31) -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_FULL_1_LSB _u(31) -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LAST_1 -// Description : Buffer 1 is the last buffer of the transfer. -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LAST_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LAST_1_MSB _u(30) -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LAST_1_LSB _u(30) -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_PID_1 -// Description : The data pid of buffer 1. -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_PID_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_PID_1_MSB _u(29) -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_PID_1_LSB _u(29) -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_PID_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET -// Description : The number of bytes buffer 1 is offset from buffer 0 in -// Isochronous mode. Only valid in double buffered mode for an -// Isochronous endpoint. -// For a non Isochronous endpoint the offset is always 64 bytes. -// 0x0 -> 128 -// 0x1 -> 256 -// 0x2 -> 512 -// 0x3 -> 1024 -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_AVAILABLE_1 -// Description : Buffer 1 is available. This bit is set to indicate the buffer -// can be used by the controller. The controller clears the -// available bit when writing the status back. -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_1 -// Description : The length of the data in buffer 1. -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_1_MSB _u(25) -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_1_LSB _u(16) -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_FULL_0 -// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit -// is set to indicate the data is valid. For an OUT transfer (RX -// from the host) this bit should be left as a 0. The host will -// set it when it has filled the buffer with data. -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_FULL_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_FULL_0_MSB _u(15) -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_FULL_0_LSB _u(15) -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LAST_0 -// Description : Buffer 0 is the last buffer of the transfer. -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LAST_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LAST_0_MSB _u(14) -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LAST_0_LSB _u(14) -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_PID_0 -// Description : The data pid of buffer 0. -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_PID_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_PID_0_MSB _u(13) -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_PID_0_LSB _u(13) -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_PID_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_RESET -// Description : Reset the buffer selector to buffer 0. -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_RESET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_RESET_BITS _u(0x00001000) -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_RESET_MSB _u(12) -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_RESET_LSB _u(12) -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_RESET_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_STALL -// Description : Reply with a stall (valid for both buffers). -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_STALL_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_STALL_BITS _u(0x00000800) -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_STALL_MSB _u(11) -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_STALL_LSB _u(11) -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_STALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_AVAILABLE_0 -// Description : Buffer 0 is available. This bit is set to indicate the buffer -// can be used by the controller. The controller clears the -// available bit when writing the status back. -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_0 -// Description : The length of the data in buffer 1. -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_0_MSB _u(9) -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_0_LSB _u(0) -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" -// ============================================================================= -// Register : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL -// Description : Buffer control for both buffers of an endpoint. Fields ending -// in a _1 are for buffer 1. -// Fields ending in a _0 are for buffer 0. Buffer 1 controls are -// only valid if the endpoint is in double buffered mode. -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_OFFSET _u(0x000000fc) -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_BITS _u(0xffffffff) -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_FULL_1 -// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit -// is set to indicate the data is valid. For an OUT transfer (RX -// from the host) this bit should be left as a 0. The host will -// set it when it has filled the buffer with data. -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_FULL_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_FULL_1_MSB _u(31) -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_FULL_1_LSB _u(31) -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LAST_1 -// Description : Buffer 1 is the last buffer of the transfer. -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LAST_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LAST_1_MSB _u(30) -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LAST_1_LSB _u(30) -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_PID_1 -// Description : The data pid of buffer 1. -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_PID_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_PID_1_MSB _u(29) -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_PID_1_LSB _u(29) -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET -// Description : The number of bytes buffer 1 is offset from buffer 0 in -// Isochronous mode. Only valid in double buffered mode for an -// Isochronous endpoint. -// For a non Isochronous endpoint the offset is always 64 bytes. -// 0x0 -> 128 -// 0x1 -> 256 -// 0x2 -> 512 -// 0x3 -> 1024 -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_AVAILABLE_1 -// Description : Buffer 1 is available. This bit is set to indicate the buffer -// can be used by the controller. The controller clears the -// available bit when writing the status back. -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_1 -// Description : The length of the data in buffer 1. -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_1_MSB _u(25) -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_1_LSB _u(16) -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_FULL_0 -// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit -// is set to indicate the data is valid. For an OUT transfer (RX -// from the host) this bit should be left as a 0. The host will -// set it when it has filled the buffer with data. -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_FULL_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_FULL_0_MSB _u(15) -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_FULL_0_LSB _u(15) -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LAST_0 -// Description : Buffer 0 is the last buffer of the transfer. -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LAST_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LAST_0_MSB _u(14) -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LAST_0_LSB _u(14) -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_PID_0 -// Description : The data pid of buffer 0. -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_PID_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_PID_0_MSB _u(13) -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_PID_0_LSB _u(13) -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_RESET -// Description : Reset the buffer selector to buffer 0. -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_RESET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_RESET_BITS _u(0x00001000) -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_RESET_MSB _u(12) -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_RESET_LSB _u(12) -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_RESET_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_STALL -// Description : Reply with a stall (valid for both buffers). -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_STALL_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_STALL_BITS _u(0x00000800) -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_STALL_MSB _u(11) -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_STALL_LSB _u(11) -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_STALL_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_AVAILABLE_0 -// Description : Buffer 0 is available. This bit is set to indicate the buffer -// can be used by the controller. The controller clears the -// available bit when writing the status back. -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_0 -// Description : The length of the data in buffer 1. -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_0_MSB _u(9) -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_0_LSB _u(0) -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" -// ============================================================================= -#endif // _HARDWARE_REGS_USB_DEVICE_DPRAM_H - diff --git a/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/watchdog.h b/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/watchdog.h deleted file mode 100644 index 07e5b405e0..0000000000 --- a/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/watchdog.h +++ /dev/null @@ -1,192 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -// ============================================================================= -// Register block : WATCHDOG -// Version : 1 -// Bus type : apb -// ============================================================================= -#ifndef _HARDWARE_REGS_WATCHDOG_H -#define _HARDWARE_REGS_WATCHDOG_H -// ============================================================================= -// Register : WATCHDOG_CTRL -// Description : Watchdog control -// The rst_wdsel register determines which subsystems are reset -// when the watchdog is triggered. -// The watchdog can be triggered in software. -#define WATCHDOG_CTRL_OFFSET _u(0x00000000) -#define WATCHDOG_CTRL_BITS _u(0xc7ffffff) -#define WATCHDOG_CTRL_RESET _u(0x07000000) -// ----------------------------------------------------------------------------- -// Field : WATCHDOG_CTRL_TRIGGER -// Description : Trigger a watchdog reset -#define WATCHDOG_CTRL_TRIGGER_RESET _u(0x0) -#define WATCHDOG_CTRL_TRIGGER_BITS _u(0x80000000) -#define WATCHDOG_CTRL_TRIGGER_MSB _u(31) -#define WATCHDOG_CTRL_TRIGGER_LSB _u(31) -#define WATCHDOG_CTRL_TRIGGER_ACCESS "SC" -// ----------------------------------------------------------------------------- -// Field : WATCHDOG_CTRL_ENABLE -// Description : When not enabled the watchdog timer is paused -#define WATCHDOG_CTRL_ENABLE_RESET _u(0x0) -#define WATCHDOG_CTRL_ENABLE_BITS _u(0x40000000) -#define WATCHDOG_CTRL_ENABLE_MSB _u(30) -#define WATCHDOG_CTRL_ENABLE_LSB _u(30) -#define WATCHDOG_CTRL_ENABLE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : WATCHDOG_CTRL_PAUSE_DBG1 -// Description : Pause the watchdog timer when processor 1 is in debug mode -#define WATCHDOG_CTRL_PAUSE_DBG1_RESET _u(0x1) -#define WATCHDOG_CTRL_PAUSE_DBG1_BITS _u(0x04000000) -#define WATCHDOG_CTRL_PAUSE_DBG1_MSB _u(26) -#define WATCHDOG_CTRL_PAUSE_DBG1_LSB _u(26) -#define WATCHDOG_CTRL_PAUSE_DBG1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : WATCHDOG_CTRL_PAUSE_DBG0 -// Description : Pause the watchdog timer when processor 0 is in debug mode -#define WATCHDOG_CTRL_PAUSE_DBG0_RESET _u(0x1) -#define WATCHDOG_CTRL_PAUSE_DBG0_BITS _u(0x02000000) -#define WATCHDOG_CTRL_PAUSE_DBG0_MSB _u(25) -#define WATCHDOG_CTRL_PAUSE_DBG0_LSB _u(25) -#define WATCHDOG_CTRL_PAUSE_DBG0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : WATCHDOG_CTRL_PAUSE_JTAG -// Description : Pause the watchdog timer when JTAG is accessing the bus fabric -#define WATCHDOG_CTRL_PAUSE_JTAG_RESET _u(0x1) -#define WATCHDOG_CTRL_PAUSE_JTAG_BITS _u(0x01000000) -#define WATCHDOG_CTRL_PAUSE_JTAG_MSB _u(24) -#define WATCHDOG_CTRL_PAUSE_JTAG_LSB _u(24) -#define WATCHDOG_CTRL_PAUSE_JTAG_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : WATCHDOG_CTRL_TIME -// Description : Indicates the time in usec before a watchdog reset will be -// triggered -#define WATCHDOG_CTRL_TIME_RESET _u(0x000000) -#define WATCHDOG_CTRL_TIME_BITS _u(0x00ffffff) -#define WATCHDOG_CTRL_TIME_MSB _u(23) -#define WATCHDOG_CTRL_TIME_LSB _u(0) -#define WATCHDOG_CTRL_TIME_ACCESS "RO" -// ============================================================================= -// Register : WATCHDOG_LOAD -// Description : Load the watchdog timer. The maximum setting is 0xffffff which -// corresponds to approximately 16 seconds. -#define WATCHDOG_LOAD_OFFSET _u(0x00000004) -#define WATCHDOG_LOAD_BITS _u(0x00ffffff) -#define WATCHDOG_LOAD_RESET _u(0x00000000) -#define WATCHDOG_LOAD_MSB _u(23) -#define WATCHDOG_LOAD_LSB _u(0) -#define WATCHDOG_LOAD_ACCESS "WF" -// ============================================================================= -// Register : WATCHDOG_REASON -// Description : Logs the reason for the last reset. Both bits are zero for the -// case of a hardware reset. -// -// Additionally, as of RP2350, a debugger warm reset of either -// core (SYSRESETREQ or hartreset) will also clear the watchdog -// reason register, so that software loaded under the debugger -// following a watchdog timeout will not continue to see the -// timeout condition. -#define WATCHDOG_REASON_OFFSET _u(0x00000008) -#define WATCHDOG_REASON_BITS _u(0x00000003) -#define WATCHDOG_REASON_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : WATCHDOG_REASON_FORCE -#define WATCHDOG_REASON_FORCE_RESET _u(0x0) -#define WATCHDOG_REASON_FORCE_BITS _u(0x00000002) -#define WATCHDOG_REASON_FORCE_MSB _u(1) -#define WATCHDOG_REASON_FORCE_LSB _u(1) -#define WATCHDOG_REASON_FORCE_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : WATCHDOG_REASON_TIMER -#define WATCHDOG_REASON_TIMER_RESET _u(0x0) -#define WATCHDOG_REASON_TIMER_BITS _u(0x00000001) -#define WATCHDOG_REASON_TIMER_MSB _u(0) -#define WATCHDOG_REASON_TIMER_LSB _u(0) -#define WATCHDOG_REASON_TIMER_ACCESS "RO" -// ============================================================================= -// Register : WATCHDOG_SCRATCH0 -// Description : Scratch register. Information persists through soft reset of -// the chip. -#define WATCHDOG_SCRATCH0_OFFSET _u(0x0000000c) -#define WATCHDOG_SCRATCH0_BITS _u(0xffffffff) -#define WATCHDOG_SCRATCH0_RESET _u(0x00000000) -#define WATCHDOG_SCRATCH0_MSB _u(31) -#define WATCHDOG_SCRATCH0_LSB _u(0) -#define WATCHDOG_SCRATCH0_ACCESS "RW" -// ============================================================================= -// Register : WATCHDOG_SCRATCH1 -// Description : Scratch register. Information persists through soft reset of -// the chip. -#define WATCHDOG_SCRATCH1_OFFSET _u(0x00000010) -#define WATCHDOG_SCRATCH1_BITS _u(0xffffffff) -#define WATCHDOG_SCRATCH1_RESET _u(0x00000000) -#define WATCHDOG_SCRATCH1_MSB _u(31) -#define WATCHDOG_SCRATCH1_LSB _u(0) -#define WATCHDOG_SCRATCH1_ACCESS "RW" -// ============================================================================= -// Register : WATCHDOG_SCRATCH2 -// Description : Scratch register. Information persists through soft reset of -// the chip. -#define WATCHDOG_SCRATCH2_OFFSET _u(0x00000014) -#define WATCHDOG_SCRATCH2_BITS _u(0xffffffff) -#define WATCHDOG_SCRATCH2_RESET _u(0x00000000) -#define WATCHDOG_SCRATCH2_MSB _u(31) -#define WATCHDOG_SCRATCH2_LSB _u(0) -#define WATCHDOG_SCRATCH2_ACCESS "RW" -// ============================================================================= -// Register : WATCHDOG_SCRATCH3 -// Description : Scratch register. Information persists through soft reset of -// the chip. -#define WATCHDOG_SCRATCH3_OFFSET _u(0x00000018) -#define WATCHDOG_SCRATCH3_BITS _u(0xffffffff) -#define WATCHDOG_SCRATCH3_RESET _u(0x00000000) -#define WATCHDOG_SCRATCH3_MSB _u(31) -#define WATCHDOG_SCRATCH3_LSB _u(0) -#define WATCHDOG_SCRATCH3_ACCESS "RW" -// ============================================================================= -// Register : WATCHDOG_SCRATCH4 -// Description : Scratch register. Information persists through soft reset of -// the chip. -#define WATCHDOG_SCRATCH4_OFFSET _u(0x0000001c) -#define WATCHDOG_SCRATCH4_BITS _u(0xffffffff) -#define WATCHDOG_SCRATCH4_RESET _u(0x00000000) -#define WATCHDOG_SCRATCH4_MSB _u(31) -#define WATCHDOG_SCRATCH4_LSB _u(0) -#define WATCHDOG_SCRATCH4_ACCESS "RW" -// ============================================================================= -// Register : WATCHDOG_SCRATCH5 -// Description : Scratch register. Information persists through soft reset of -// the chip. -#define WATCHDOG_SCRATCH5_OFFSET _u(0x00000020) -#define WATCHDOG_SCRATCH5_BITS _u(0xffffffff) -#define WATCHDOG_SCRATCH5_RESET _u(0x00000000) -#define WATCHDOG_SCRATCH5_MSB _u(31) -#define WATCHDOG_SCRATCH5_LSB _u(0) -#define WATCHDOG_SCRATCH5_ACCESS "RW" -// ============================================================================= -// Register : WATCHDOG_SCRATCH6 -// Description : Scratch register. Information persists through soft reset of -// the chip. -#define WATCHDOG_SCRATCH6_OFFSET _u(0x00000024) -#define WATCHDOG_SCRATCH6_BITS _u(0xffffffff) -#define WATCHDOG_SCRATCH6_RESET _u(0x00000000) -#define WATCHDOG_SCRATCH6_MSB _u(31) -#define WATCHDOG_SCRATCH6_LSB _u(0) -#define WATCHDOG_SCRATCH6_ACCESS "RW" -// ============================================================================= -// Register : WATCHDOG_SCRATCH7 -// Description : Scratch register. Information persists through soft reset of -// the chip. -#define WATCHDOG_SCRATCH7_OFFSET _u(0x00000028) -#define WATCHDOG_SCRATCH7_BITS _u(0xffffffff) -#define WATCHDOG_SCRATCH7_RESET _u(0x00000000) -#define WATCHDOG_SCRATCH7_MSB _u(31) -#define WATCHDOG_SCRATCH7_LSB _u(0) -#define WATCHDOG_SCRATCH7_ACCESS "RW" -// ============================================================================= -#endif // _HARDWARE_REGS_WATCHDOG_H - diff --git a/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/xip.h b/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/xip.h deleted file mode 100644 index 7487ec63f2..0000000000 --- a/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/xip.h +++ /dev/null @@ -1,313 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -// ============================================================================= -// Register block : XIP -// Version : 1 -// Bus type : ahb -// Description : QSPI flash execute-in-place block -// ============================================================================= -#ifndef _HARDWARE_REGS_XIP_H -#define _HARDWARE_REGS_XIP_H -// ============================================================================= -// Register : XIP_CTRL -// Description : Cache control register. Read-only from a Non-secure context. -#define XIP_CTRL_OFFSET _u(0x00000000) -#define XIP_CTRL_BITS _u(0x00000ffb) -#define XIP_CTRL_RESET _u(0x00000083) -// ----------------------------------------------------------------------------- -// Field : XIP_CTRL_WRITABLE_M1 -// Description : If 1, enable writes to XIP memory window 1 (addresses -// 0x11000000 through 0x11ffffff, and their uncached mirrors). If -// 0, this region is read-only. -// -// XIP memory is *read-only by default*. This bit must be set to -// enable writes if a RAM device is attached on QSPI chip select -// 1. -// -// The default read-only behaviour avoids two issues with writing -// to a read-only QSPI device (e.g. flash). First, a write will -// initially appear to succeed due to caching, but the data will -// eventually be lost when the written line is evicted, causing -// unpredictable behaviour. -// -// Second, when a written line is evicted, it will cause a write -// command to be issued to the flash, which can break the flash -// out of its continuous read mode. After this point, flash reads -// will return garbage. This is a security concern, as it allows -// Non-secure software to break Secure flash reads if it has -// permission to write to any flash address. -// -// Note the read-only behaviour is implemented by downgrading -// writes to reads, so writes will still cause allocation of an -// address, but have no other effect. -#define XIP_CTRL_WRITABLE_M1_RESET _u(0x0) -#define XIP_CTRL_WRITABLE_M1_BITS _u(0x00000800) -#define XIP_CTRL_WRITABLE_M1_MSB _u(11) -#define XIP_CTRL_WRITABLE_M1_LSB _u(11) -#define XIP_CTRL_WRITABLE_M1_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : XIP_CTRL_WRITABLE_M0 -// Description : If 1, enable writes to XIP memory window 0 (addresses -// 0x10000000 through 0x10ffffff, and their uncached mirrors). If -// 0, this region is read-only. -// -// XIP memory is *read-only by default*. This bit must be set to -// enable writes if a RAM device is attached on QSPI chip select -// 0. -// -// The default read-only behaviour avoids two issues with writing -// to a read-only QSPI device (e.g. flash). First, a write will -// initially appear to succeed due to caching, but the data will -// eventually be lost when the written line is evicted, causing -// unpredictable behaviour. -// -// Second, when a written line is evicted, it will cause a write -// command to be issued to the flash, which can break the flash -// out of its continuous read mode. After this point, flash reads -// will return garbage. This is a security concern, as it allows -// Non-secure software to break Secure flash reads if it has -// permission to write to any flash address. -// -// Note the read-only behaviour is implemented by downgrading -// writes to reads, so writes will still cause allocation of an -// address, but have no other effect. -#define XIP_CTRL_WRITABLE_M0_RESET _u(0x0) -#define XIP_CTRL_WRITABLE_M0_BITS _u(0x00000400) -#define XIP_CTRL_WRITABLE_M0_MSB _u(10) -#define XIP_CTRL_WRITABLE_M0_LSB _u(10) -#define XIP_CTRL_WRITABLE_M0_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : XIP_CTRL_SPLIT_WAYS -// Description : When 1, route all cached+Secure accesses to way 0 of the cache, -// and route all cached+Non-secure accesses to way 1 of the cache. -// -// This partitions the cache into two half-sized direct-mapped -// regions, such that Non-secure code can not observe cache line -// state changes caused by Secure execution. -// -// A full cache flush is required when changing the value of -// SPLIT_WAYS. The flush should be performed whilst SPLIT_WAYS is -// 0, so that both cache ways are accessible for invalidation. -#define XIP_CTRL_SPLIT_WAYS_RESET _u(0x0) -#define XIP_CTRL_SPLIT_WAYS_BITS _u(0x00000200) -#define XIP_CTRL_SPLIT_WAYS_MSB _u(9) -#define XIP_CTRL_SPLIT_WAYS_LSB _u(9) -#define XIP_CTRL_SPLIT_WAYS_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : XIP_CTRL_MAINT_NONSEC -// Description : When 0, Non-secure accesses to the cache maintenance address -// window (addr[27] == 1, addr[26] == 0) will generate a bus -// error. When 1, Non-secure accesses can perform cache -// maintenance operations by writing to the cache maintenance -// address window. -// -// Cache maintenance operations may be used to corrupt Secure data -// by invalidating cache lines inappropriately, or map Secure -// content into a Non-secure region by pinning cache lines. -// Therefore this bit should generally be set to 0, unless Secure -// code is not using the cache. -// -// Care should also be taken to clear the cache data memory and -// tag memory before granting maintenance operations to Non-secure -// code. -#define XIP_CTRL_MAINT_NONSEC_RESET _u(0x0) -#define XIP_CTRL_MAINT_NONSEC_BITS _u(0x00000100) -#define XIP_CTRL_MAINT_NONSEC_MSB _u(8) -#define XIP_CTRL_MAINT_NONSEC_LSB _u(8) -#define XIP_CTRL_MAINT_NONSEC_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : XIP_CTRL_NO_UNTRANSLATED_NONSEC -// Description : When 1, Non-secure accesses to the uncached, untranslated -// window (addr[27:26] == 3) will generate a bus error. -#define XIP_CTRL_NO_UNTRANSLATED_NONSEC_RESET _u(0x1) -#define XIP_CTRL_NO_UNTRANSLATED_NONSEC_BITS _u(0x00000080) -#define XIP_CTRL_NO_UNTRANSLATED_NONSEC_MSB _u(7) -#define XIP_CTRL_NO_UNTRANSLATED_NONSEC_LSB _u(7) -#define XIP_CTRL_NO_UNTRANSLATED_NONSEC_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : XIP_CTRL_NO_UNTRANSLATED_SEC -// Description : When 1, Secure accesses to the uncached, untranslated window -// (addr[27:26] == 3) will generate a bus error. -#define XIP_CTRL_NO_UNTRANSLATED_SEC_RESET _u(0x0) -#define XIP_CTRL_NO_UNTRANSLATED_SEC_BITS _u(0x00000040) -#define XIP_CTRL_NO_UNTRANSLATED_SEC_MSB _u(6) -#define XIP_CTRL_NO_UNTRANSLATED_SEC_LSB _u(6) -#define XIP_CTRL_NO_UNTRANSLATED_SEC_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : XIP_CTRL_NO_UNCACHED_NONSEC -// Description : When 1, Non-secure accesses to the uncached window (addr[27:26] -// == 1) will generate a bus error. This may reduce the number of -// SAU/MPU/PMP regions required to protect flash contents. -// -// Note this does not disable access to the uncached, untranslated -// window -- see NO_UNTRANSLATED_SEC. -#define XIP_CTRL_NO_UNCACHED_NONSEC_RESET _u(0x0) -#define XIP_CTRL_NO_UNCACHED_NONSEC_BITS _u(0x00000020) -#define XIP_CTRL_NO_UNCACHED_NONSEC_MSB _u(5) -#define XIP_CTRL_NO_UNCACHED_NONSEC_LSB _u(5) -#define XIP_CTRL_NO_UNCACHED_NONSEC_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : XIP_CTRL_NO_UNCACHED_SEC -// Description : When 1, Secure accesses to the uncached window (addr[27:26] == -// 1) will generate a bus error. This may reduce the number of -// SAU/MPU/PMP regions required to protect flash contents. -// -// Note this does not disable access to the uncached, untranslated -// window -- see NO_UNTRANSLATED_SEC. -#define XIP_CTRL_NO_UNCACHED_SEC_RESET _u(0x0) -#define XIP_CTRL_NO_UNCACHED_SEC_BITS _u(0x00000010) -#define XIP_CTRL_NO_UNCACHED_SEC_MSB _u(4) -#define XIP_CTRL_NO_UNCACHED_SEC_LSB _u(4) -#define XIP_CTRL_NO_UNCACHED_SEC_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : XIP_CTRL_POWER_DOWN -// Description : When 1, the cache memories are powered down. They retain state, -// but can not be accessed. This reduces static power dissipation. -// Writing 1 to this bit forces CTRL_EN_SECURE and -// CTRL_EN_NONSECURE to 0, i.e. the cache cannot be enabled when -// powered down. -#define XIP_CTRL_POWER_DOWN_RESET _u(0x0) -#define XIP_CTRL_POWER_DOWN_BITS _u(0x00000008) -#define XIP_CTRL_POWER_DOWN_MSB _u(3) -#define XIP_CTRL_POWER_DOWN_LSB _u(3) -#define XIP_CTRL_POWER_DOWN_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : XIP_CTRL_EN_NONSECURE -// Description : When 1, enable the cache for Non-secure accesses. When enabled, -// Non-secure XIP accesses to the cached (addr[26] == 0) window -// will query the cache, and QSPI accesses are performed only if -// the requested data is not present. When disabled, Secure access -// ignore the cache contents, and always access the QSPI -// interface. -// -// Accesses to the uncached (addr[26] == 1) window will never -// query the cache, irrespective of this bit. -#define XIP_CTRL_EN_NONSECURE_RESET _u(0x1) -#define XIP_CTRL_EN_NONSECURE_BITS _u(0x00000002) -#define XIP_CTRL_EN_NONSECURE_MSB _u(1) -#define XIP_CTRL_EN_NONSECURE_LSB _u(1) -#define XIP_CTRL_EN_NONSECURE_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : XIP_CTRL_EN_SECURE -// Description : When 1, enable the cache for Secure accesses. When enabled, -// Secure XIP accesses to the cached (addr[26] == 0) window will -// query the cache, and QSPI accesses are performed only if the -// requested data is not present. When disabled, Secure access -// ignore the cache contents, and always access the QSPI -// interface. -// -// Accesses to the uncached (addr[26] == 1) window will never -// query the cache, irrespective of this bit. -// -// There is no cache-as-SRAM address window. Cache lines are -// allocated for SRAM-like use by individually pinning them, and -// keeping the cache enabled. -#define XIP_CTRL_EN_SECURE_RESET _u(0x1) -#define XIP_CTRL_EN_SECURE_BITS _u(0x00000001) -#define XIP_CTRL_EN_SECURE_MSB _u(0) -#define XIP_CTRL_EN_SECURE_LSB _u(0) -#define XIP_CTRL_EN_SECURE_ACCESS "RW" -// ============================================================================= -// Register : XIP_STAT -#define XIP_STAT_OFFSET _u(0x00000008) -#define XIP_STAT_BITS _u(0x00000006) -#define XIP_STAT_RESET _u(0x00000002) -// ----------------------------------------------------------------------------- -// Field : XIP_STAT_FIFO_FULL -// Description : When 1, indicates the XIP streaming FIFO is completely full. -// The streaming FIFO is 2 entries deep, so the full and empty -// flag allow its level to be ascertained. -#define XIP_STAT_FIFO_FULL_RESET _u(0x0) -#define XIP_STAT_FIFO_FULL_BITS _u(0x00000004) -#define XIP_STAT_FIFO_FULL_MSB _u(2) -#define XIP_STAT_FIFO_FULL_LSB _u(2) -#define XIP_STAT_FIFO_FULL_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : XIP_STAT_FIFO_EMPTY -// Description : When 1, indicates the XIP streaming FIFO is completely empty. -#define XIP_STAT_FIFO_EMPTY_RESET _u(0x1) -#define XIP_STAT_FIFO_EMPTY_BITS _u(0x00000002) -#define XIP_STAT_FIFO_EMPTY_MSB _u(1) -#define XIP_STAT_FIFO_EMPTY_LSB _u(1) -#define XIP_STAT_FIFO_EMPTY_ACCESS "RO" -// ============================================================================= -// Register : XIP_CTR_HIT -// Description : Cache Hit counter -// A 32 bit saturating counter that increments upon each cache -// hit, -// i.e. when an XIP access is serviced directly from cached data. -// Write any value to clear. -#define XIP_CTR_HIT_OFFSET _u(0x0000000c) -#define XIP_CTR_HIT_BITS _u(0xffffffff) -#define XIP_CTR_HIT_RESET _u(0x00000000) -#define XIP_CTR_HIT_MSB _u(31) -#define XIP_CTR_HIT_LSB _u(0) -#define XIP_CTR_HIT_ACCESS "WC" -// ============================================================================= -// Register : XIP_CTR_ACC -// Description : Cache Access counter -// A 32 bit saturating counter that increments upon each XIP -// access, -// whether the cache is hit or not. This includes noncacheable -// accesses. -// Write any value to clear. -#define XIP_CTR_ACC_OFFSET _u(0x00000010) -#define XIP_CTR_ACC_BITS _u(0xffffffff) -#define XIP_CTR_ACC_RESET _u(0x00000000) -#define XIP_CTR_ACC_MSB _u(31) -#define XIP_CTR_ACC_LSB _u(0) -#define XIP_CTR_ACC_ACCESS "WC" -// ============================================================================= -// Register : XIP_STREAM_ADDR -// Description : FIFO stream address -// The address of the next word to be streamed from flash to the -// streaming FIFO. -// Increments automatically after each flash access. -// Write the initial access address here before starting a -// streaming read. -#define XIP_STREAM_ADDR_OFFSET _u(0x00000014) -#define XIP_STREAM_ADDR_BITS _u(0xfffffffc) -#define XIP_STREAM_ADDR_RESET _u(0x00000000) -#define XIP_STREAM_ADDR_MSB _u(31) -#define XIP_STREAM_ADDR_LSB _u(2) -#define XIP_STREAM_ADDR_ACCESS "RW" -// ============================================================================= -// Register : XIP_STREAM_CTR -// Description : FIFO stream control -// Write a nonzero value to start a streaming read. This will then -// progress in the background, using flash idle cycles to transfer -// a linear data block from flash to the streaming FIFO. -// Decrements automatically (1 at a time) as the stream -// progresses, and halts on reaching 0. -// Write 0 to halt an in-progress stream, and discard any in- -// flight -// read, so that a new stream can immediately be started (after -// draining the FIFO and reinitialising STREAM_ADDR) -#define XIP_STREAM_CTR_OFFSET _u(0x00000018) -#define XIP_STREAM_CTR_BITS _u(0x003fffff) -#define XIP_STREAM_CTR_RESET _u(0x00000000) -#define XIP_STREAM_CTR_MSB _u(21) -#define XIP_STREAM_CTR_LSB _u(0) -#define XIP_STREAM_CTR_ACCESS "RW" -// ============================================================================= -// Register : XIP_STREAM_FIFO -// Description : FIFO stream data -// Streamed data is buffered here, for retrieval by the system -// DMA. -// This FIFO can also be accessed via the XIP_AUX slave, to avoid -// exposing -// the DMA to bus stalls caused by other XIP traffic. -#define XIP_STREAM_FIFO_OFFSET _u(0x0000001c) -#define XIP_STREAM_FIFO_BITS _u(0xffffffff) -#define XIP_STREAM_FIFO_RESET _u(0x00000000) -#define XIP_STREAM_FIFO_MSB _u(31) -#define XIP_STREAM_FIFO_LSB _u(0) -#define XIP_STREAM_FIFO_ACCESS "RF" -// ============================================================================= -#endif // _HARDWARE_REGS_XIP_H - diff --git a/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/xip_aux.h b/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/xip_aux.h deleted file mode 100644 index 07940ca442..0000000000 --- a/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/xip_aux.h +++ /dev/null @@ -1,123 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -// ============================================================================= -// Register block : XIP_AUX -// Version : 1 -// Bus type : ahb -// Description : Auxiliary DMA access to XIP FIFOs, via fast AHB bus access -// ============================================================================= -#ifndef _HARDWARE_REGS_XIP_AUX_H -#define _HARDWARE_REGS_XIP_AUX_H -// ============================================================================= -// Register : XIP_AUX_STREAM -// Description : Read the XIP stream FIFO (fast bus access to -// XIP_CTRL_STREAM_FIFO) -#define XIP_AUX_STREAM_OFFSET _u(0x00000000) -#define XIP_AUX_STREAM_BITS _u(0xffffffff) -#define XIP_AUX_STREAM_RESET _u(0x00000000) -#define XIP_AUX_STREAM_MSB _u(31) -#define XIP_AUX_STREAM_LSB _u(0) -#define XIP_AUX_STREAM_ACCESS "RF" -// ============================================================================= -// Register : XIP_AUX_QMI_DIRECT_TX -// Description : Write to the QMI direct-mode TX FIFO (fast bus access to -// QMI_DIRECT_TX) -#define XIP_AUX_QMI_DIRECT_TX_OFFSET _u(0x00000004) -#define XIP_AUX_QMI_DIRECT_TX_BITS _u(0x001fffff) -#define XIP_AUX_QMI_DIRECT_TX_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : XIP_AUX_QMI_DIRECT_TX_NOPUSH -// Description : Inhibit the RX FIFO push that would correspond to this TX FIFO -// entry. -// -// Useful to avoid garbage appearing in the RX FIFO when pushing -// the command at the beginning of a SPI transfer. -#define XIP_AUX_QMI_DIRECT_TX_NOPUSH_RESET _u(0x0) -#define XIP_AUX_QMI_DIRECT_TX_NOPUSH_BITS _u(0x00100000) -#define XIP_AUX_QMI_DIRECT_TX_NOPUSH_MSB _u(20) -#define XIP_AUX_QMI_DIRECT_TX_NOPUSH_LSB _u(20) -#define XIP_AUX_QMI_DIRECT_TX_NOPUSH_ACCESS "WF" -// ----------------------------------------------------------------------------- -// Field : XIP_AUX_QMI_DIRECT_TX_OE -// Description : Output enable (active-high). For single width (SPI), this field -// is ignored, and SD0 is always set to output, with SD1 always -// set to input. -// -// For dual and quad width (DSPI/QSPI), this sets whether the -// relevant SDx pads are set to output whilst transferring this -// FIFO record. In this case the command/address should have OE -// set, and the data transfer should have OE set or clear -// depending on the direction of the transfer. -#define XIP_AUX_QMI_DIRECT_TX_OE_RESET _u(0x0) -#define XIP_AUX_QMI_DIRECT_TX_OE_BITS _u(0x00080000) -#define XIP_AUX_QMI_DIRECT_TX_OE_MSB _u(19) -#define XIP_AUX_QMI_DIRECT_TX_OE_LSB _u(19) -#define XIP_AUX_QMI_DIRECT_TX_OE_ACCESS "WF" -// ----------------------------------------------------------------------------- -// Field : XIP_AUX_QMI_DIRECT_TX_DWIDTH -// Description : Data width. If 0, hardware will transmit the 8 LSBs of the -// DIRECT_TX DATA field, and return an 8-bit value in the 8 LSBs -// of DIRECT_RX. If 1, the full 16-bit width is used. 8-bit and -// 16-bit transfers can be mixed freely. -#define XIP_AUX_QMI_DIRECT_TX_DWIDTH_RESET _u(0x0) -#define XIP_AUX_QMI_DIRECT_TX_DWIDTH_BITS _u(0x00040000) -#define XIP_AUX_QMI_DIRECT_TX_DWIDTH_MSB _u(18) -#define XIP_AUX_QMI_DIRECT_TX_DWIDTH_LSB _u(18) -#define XIP_AUX_QMI_DIRECT_TX_DWIDTH_ACCESS "WF" -// ----------------------------------------------------------------------------- -// Field : XIP_AUX_QMI_DIRECT_TX_IWIDTH -// Description : Configure whether this FIFO record is transferred with -// single/dual/quad interface width (0/1/2). Different widths can -// be mixed freely. -// 0x0 -> Single width -// 0x1 -> Dual width -// 0x2 -> Quad width -#define XIP_AUX_QMI_DIRECT_TX_IWIDTH_RESET _u(0x0) -#define XIP_AUX_QMI_DIRECT_TX_IWIDTH_BITS _u(0x00030000) -#define XIP_AUX_QMI_DIRECT_TX_IWIDTH_MSB _u(17) -#define XIP_AUX_QMI_DIRECT_TX_IWIDTH_LSB _u(16) -#define XIP_AUX_QMI_DIRECT_TX_IWIDTH_ACCESS "WF" -#define XIP_AUX_QMI_DIRECT_TX_IWIDTH_VALUE_S _u(0x0) -#define XIP_AUX_QMI_DIRECT_TX_IWIDTH_VALUE_D _u(0x1) -#define XIP_AUX_QMI_DIRECT_TX_IWIDTH_VALUE_Q _u(0x2) -// ----------------------------------------------------------------------------- -// Field : XIP_AUX_QMI_DIRECT_TX_DATA -// Description : Data pushed here will be clocked out falling edges of SCK (or -// before the very first rising edge of SCK, if this is the first -// pulse). For each byte clocked out, the interface will -// simultaneously sample one byte, on rising edges of SCK, and -// push this to the DIRECT_RX FIFO. -// -// For 16-bit data, the least-significant byte is transmitted -// first. -#define XIP_AUX_QMI_DIRECT_TX_DATA_RESET _u(0x0000) -#define XIP_AUX_QMI_DIRECT_TX_DATA_BITS _u(0x0000ffff) -#define XIP_AUX_QMI_DIRECT_TX_DATA_MSB _u(15) -#define XIP_AUX_QMI_DIRECT_TX_DATA_LSB _u(0) -#define XIP_AUX_QMI_DIRECT_TX_DATA_ACCESS "WF" -// ============================================================================= -// Register : XIP_AUX_QMI_DIRECT_RX -// Description : Read from the QMI direct-mode RX FIFO (fast bus access to -// QMI_DIRECT_RX) -// With each byte clocked out on the serial interface, one byte -// will simultaneously be clocked in, and will appear in this -// FIFO. The serial interface will stall when this FIFO is full, -// to avoid dropping data. -// -// When 16-bit data is pushed into the TX FIFO, the corresponding -// RX FIFO push will also contain 16 bits of data. The least- -// significant byte is the first one received. -#define XIP_AUX_QMI_DIRECT_RX_OFFSET _u(0x00000008) -#define XIP_AUX_QMI_DIRECT_RX_BITS _u(0x0000ffff) -#define XIP_AUX_QMI_DIRECT_RX_RESET _u(0x00000000) -#define XIP_AUX_QMI_DIRECT_RX_MSB _u(15) -#define XIP_AUX_QMI_DIRECT_RX_LSB _u(0) -#define XIP_AUX_QMI_DIRECT_RX_ACCESS "RF" -// ============================================================================= -#endif // _HARDWARE_REGS_XIP_AUX_H - diff --git a/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/xosc.h b/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/xosc.h deleted file mode 100644 index 782c30ca1b..0000000000 --- a/lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/xosc.h +++ /dev/null @@ -1,175 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -// ============================================================================= -// Register block : XOSC -// Version : 1 -// Bus type : apb -// Description : Controls the crystal oscillator -// ============================================================================= -#ifndef _HARDWARE_REGS_XOSC_H -#define _HARDWARE_REGS_XOSC_H -// ============================================================================= -// Register : XOSC_CTRL -// Description : Crystal Oscillator Control -#define XOSC_CTRL_OFFSET _u(0x00000000) -#define XOSC_CTRL_BITS _u(0x00ffffff) -#define XOSC_CTRL_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : XOSC_CTRL_ENABLE -// Description : On power-up this field is initialised to DISABLE and the chip -// runs from the ROSC. -// If the chip has subsequently been programmed to run from the -// XOSC then setting this field to DISABLE may lock-up the chip. -// If this is a concern then run the clk_ref from the ROSC and -// enable the clk_sys RESUS feature. -// The 12-bit code is intended to give some protection against -// accidental writes. An invalid setting will retain the previous -// value. The actual value being used can be read from -// STATUS_ENABLED -// 0xd1e -> DISABLE -// 0xfab -> ENABLE -#define XOSC_CTRL_ENABLE_RESET "-" -#define XOSC_CTRL_ENABLE_BITS _u(0x00fff000) -#define XOSC_CTRL_ENABLE_MSB _u(23) -#define XOSC_CTRL_ENABLE_LSB _u(12) -#define XOSC_CTRL_ENABLE_ACCESS "RW" -#define XOSC_CTRL_ENABLE_VALUE_DISABLE _u(0xd1e) -#define XOSC_CTRL_ENABLE_VALUE_ENABLE _u(0xfab) -// ----------------------------------------------------------------------------- -// Field : XOSC_CTRL_FREQ_RANGE -// Description : The 12-bit code is intended to give some protection against -// accidental writes. An invalid setting will retain the previous -// value. The actual value being used can be read from -// STATUS_FREQ_RANGE -// 0xaa0 -> 1_15MHZ -// 0xaa1 -> 10_30MHZ -// 0xaa2 -> 25_60MHZ -// 0xaa3 -> 40_100MHZ -#define XOSC_CTRL_FREQ_RANGE_RESET "-" -#define XOSC_CTRL_FREQ_RANGE_BITS _u(0x00000fff) -#define XOSC_CTRL_FREQ_RANGE_MSB _u(11) -#define XOSC_CTRL_FREQ_RANGE_LSB _u(0) -#define XOSC_CTRL_FREQ_RANGE_ACCESS "RW" -#define XOSC_CTRL_FREQ_RANGE_VALUE_1_15MHZ _u(0xaa0) -#define XOSC_CTRL_FREQ_RANGE_VALUE_10_30MHZ _u(0xaa1) -#define XOSC_CTRL_FREQ_RANGE_VALUE_25_60MHZ _u(0xaa2) -#define XOSC_CTRL_FREQ_RANGE_VALUE_40_100MHZ _u(0xaa3) -// ============================================================================= -// Register : XOSC_STATUS -// Description : Crystal Oscillator Status -#define XOSC_STATUS_OFFSET _u(0x00000004) -#define XOSC_STATUS_BITS _u(0x81001003) -#define XOSC_STATUS_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : XOSC_STATUS_STABLE -// Description : Oscillator is running and stable -#define XOSC_STATUS_STABLE_RESET _u(0x0) -#define XOSC_STATUS_STABLE_BITS _u(0x80000000) -#define XOSC_STATUS_STABLE_MSB _u(31) -#define XOSC_STATUS_STABLE_LSB _u(31) -#define XOSC_STATUS_STABLE_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : XOSC_STATUS_BADWRITE -// Description : An invalid value has been written to CTRL_ENABLE or -// CTRL_FREQ_RANGE or DORMANT -#define XOSC_STATUS_BADWRITE_RESET _u(0x0) -#define XOSC_STATUS_BADWRITE_BITS _u(0x01000000) -#define XOSC_STATUS_BADWRITE_MSB _u(24) -#define XOSC_STATUS_BADWRITE_LSB _u(24) -#define XOSC_STATUS_BADWRITE_ACCESS "WC" -// ----------------------------------------------------------------------------- -// Field : XOSC_STATUS_ENABLED -// Description : Oscillator is enabled but not necessarily running and stable, -// resets to 0 -#define XOSC_STATUS_ENABLED_RESET "-" -#define XOSC_STATUS_ENABLED_BITS _u(0x00001000) -#define XOSC_STATUS_ENABLED_MSB _u(12) -#define XOSC_STATUS_ENABLED_LSB _u(12) -#define XOSC_STATUS_ENABLED_ACCESS "RO" -// ----------------------------------------------------------------------------- -// Field : XOSC_STATUS_FREQ_RANGE -// Description : The current frequency range setting -// 0x0 -> 1_15MHZ -// 0x1 -> 10_30MHZ -// 0x2 -> 25_60MHZ -// 0x3 -> 40_100MHZ -#define XOSC_STATUS_FREQ_RANGE_RESET "-" -#define XOSC_STATUS_FREQ_RANGE_BITS _u(0x00000003) -#define XOSC_STATUS_FREQ_RANGE_MSB _u(1) -#define XOSC_STATUS_FREQ_RANGE_LSB _u(0) -#define XOSC_STATUS_FREQ_RANGE_ACCESS "RO" -#define XOSC_STATUS_FREQ_RANGE_VALUE_1_15MHZ _u(0x0) -#define XOSC_STATUS_FREQ_RANGE_VALUE_10_30MHZ _u(0x1) -#define XOSC_STATUS_FREQ_RANGE_VALUE_25_60MHZ _u(0x2) -#define XOSC_STATUS_FREQ_RANGE_VALUE_40_100MHZ _u(0x3) -// ============================================================================= -// Register : XOSC_DORMANT -// Description : Crystal Oscillator pause control -// This is used to save power by pausing the XOSC -// On power-up this field is initialised to WAKE -// An invalid write will also select WAKE -// Warning: stop the PLLs before selecting dormant mode -// Warning: setup the irq before selecting dormant mode -// 0x636f6d61 -> dormant -// 0x77616b65 -> WAKE -#define XOSC_DORMANT_OFFSET _u(0x00000008) -#define XOSC_DORMANT_BITS _u(0xffffffff) -#define XOSC_DORMANT_RESET "-" -#define XOSC_DORMANT_MSB _u(31) -#define XOSC_DORMANT_LSB _u(0) -#define XOSC_DORMANT_ACCESS "RW" -#define XOSC_DORMANT_VALUE_DORMANT _u(0x636f6d61) -#define XOSC_DORMANT_VALUE_WAKE _u(0x77616b65) -// ============================================================================= -// Register : XOSC_STARTUP -// Description : Controls the startup delay -#define XOSC_STARTUP_OFFSET _u(0x0000000c) -#define XOSC_STARTUP_BITS _u(0x00103fff) -#define XOSC_STARTUP_RESET _u(0x00000000) -// ----------------------------------------------------------------------------- -// Field : XOSC_STARTUP_X4 -// Description : Multiplies the startup_delay by 4, just in case. The reset -// value is controlled by a mask-programmable tiecell and is -// provided in case we are booting from XOSC and the default -// startup delay is insufficient. The reset value is 0x0. -#define XOSC_STARTUP_X4_RESET "-" -#define XOSC_STARTUP_X4_BITS _u(0x00100000) -#define XOSC_STARTUP_X4_MSB _u(20) -#define XOSC_STARTUP_X4_LSB _u(20) -#define XOSC_STARTUP_X4_ACCESS "RW" -// ----------------------------------------------------------------------------- -// Field : XOSC_STARTUP_DELAY -// Description : in multiples of 256*xtal_period. The reset value of 0xc4 -// corresponds to approx 50 000 cycles. -#define XOSC_STARTUP_DELAY_RESET "-" -#define XOSC_STARTUP_DELAY_BITS _u(0x00003fff) -#define XOSC_STARTUP_DELAY_MSB _u(13) -#define XOSC_STARTUP_DELAY_LSB _u(0) -#define XOSC_STARTUP_DELAY_ACCESS "RW" -// ============================================================================= -// Register : XOSC_COUNT -// Description : A down counter running at the xosc frequency which counts to -// zero and stops. -// Can be used for short software pauses when setting up time -// sensitive hardware. -// To start the counter, write a non-zero value. Reads will return -// 1 while the count is running and 0 when it has finished. -// Minimum count value is 4. Count values <4 will be treated as -// count value =4. -// Note that synchronisation to the register clock domain costs 2 -// register clock cycles and the counter cannot compensate for -// that. -#define XOSC_COUNT_OFFSET _u(0x00000010) -#define XOSC_COUNT_BITS _u(0x0000ffff) -#define XOSC_COUNT_RESET _u(0x00000000) -#define XOSC_COUNT_MSB _u(15) -#define XOSC_COUNT_LSB _u(0) -#define XOSC_COUNT_ACCESS "RW" -// ============================================================================= -#endif // _HARDWARE_REGS_XOSC_H - diff --git a/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/accessctrl.h b/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/accessctrl.h deleted file mode 100644 index 5fd30cb2d9..0000000000 --- a/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/accessctrl.h +++ /dev/null @@ -1,519 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _HARDWARE_STRUCTS_ACCESSCTRL_H -#define _HARDWARE_STRUCTS_ACCESSCTRL_H - -/** - * \file rp2350/accessctrl.h - */ - -#include "hardware/address_mapped.h" -#include "hardware/regs/accessctrl.h" - -// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_accessctrl -// -// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) -// _REG_(x) will link to the corresponding register in hardware/regs/accessctrl.h. -// -// Bit-field descriptions are of the form: -// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION - -typedef struct { - _REG_(ACCESSCTRL_LOCK_OFFSET) // ACCESSCTRL_LOCK - // Once a LOCK bit is written to 1, ACCESSCTRL silently ignores writes from that master - // 0x00000008 [3] DEBUG (0) - // 0x00000004 [2] DMA (1) - // 0x00000002 [1] CORE1 (0) - // 0x00000001 [0] CORE0 (0) - io_rw_32 lock; - - _REG_(ACCESSCTRL_FORCE_CORE_NS_OFFSET) // ACCESSCTRL_FORCE_CORE_NS - // Force core 1's bus accesses to always be Non-secure, no matter the core's internal state - // 0x00000002 [1] CORE1 (0) - io_rw_32 force_core_ns; - - _REG_(ACCESSCTRL_CFGRESET_OFFSET) // ACCESSCTRL_CFGRESET - // Write 1 to reset all ACCESSCTRL configuration, except for the LOCK and FORCE_CORE_NS registers - // 0x00000001 [0] CFGRESET (0) - io_wo_32 cfgreset; - - // (Description copied from array index 0 register ACCESSCTRL_GPIO_NSMASK0 applies similarly to other array indexes) - _REG_(ACCESSCTRL_GPIO_NSMASK0_OFFSET) // ACCESSCTRL_GPIO_NSMASK0 - // Control whether GPIO0 - // 0xffffffff [31:0] GPIO_NSMASK0 (0x00000000) - io_rw_32 gpio_nsmask[2]; - - _REG_(ACCESSCTRL_ROM_OFFSET) // ACCESSCTRL_ROM - // Control access to ROM. Defaults to fully open access. - // 0x00000080 [7] DBG (1) If 1, ROM can be accessed by the debugger, at... - // 0x00000040 [6] DMA (1) If 1, ROM can be accessed by the DMA, at... - // 0x00000020 [5] CORE1 (1) If 1, ROM can be accessed by core 1, at... - // 0x00000010 [4] CORE0 (1) If 1, ROM can be accessed by core 0, at... - // 0x00000008 [3] SP (1) If 1, ROM can be accessed from a Secure, Privileged context - // 0x00000004 [2] SU (1) If 1, and SP is also set, ROM can be accessed from a... - // 0x00000002 [1] NSP (1) If 1, ROM can be accessed from a Non-secure, Privileged context - // 0x00000001 [0] NSU (1) If 1, and NSP is also set, ROM can be accessed from a... - io_rw_32 rom; - - _REG_(ACCESSCTRL_XIP_MAIN_OFFSET) // ACCESSCTRL_XIP_MAIN - // Control access to XIP_MAIN. Defaults to fully open access. - // 0x00000080 [7] DBG (1) If 1, XIP_MAIN can be accessed by the debugger, at... - // 0x00000040 [6] DMA (1) If 1, XIP_MAIN can be accessed by the DMA, at... - // 0x00000020 [5] CORE1 (1) If 1, XIP_MAIN can be accessed by core 1, at... - // 0x00000010 [4] CORE0 (1) If 1, XIP_MAIN can be accessed by core 0, at... - // 0x00000008 [3] SP (1) If 1, XIP_MAIN can be accessed from a Secure, Privileged context - // 0x00000004 [2] SU (1) If 1, and SP is also set, XIP_MAIN can be accessed from... - // 0x00000002 [1] NSP (1) If 1, XIP_MAIN can be accessed from a Non-secure,... - // 0x00000001 [0] NSU (1) If 1, and NSP is also set, XIP_MAIN can be accessed from... - io_rw_32 xip_main; - - // (Description copied from array index 0 register ACCESSCTRL_SRAM0 applies similarly to other array indexes) - _REG_(ACCESSCTRL_SRAM0_OFFSET) // ACCESSCTRL_SRAM0 - // Control access to SRAM0. Defaults to fully open access. - // 0x00000080 [7] DBG (1) If 1, SRAM0 can be accessed by the debugger, at... - // 0x00000040 [6] DMA (1) If 1, SRAM0 can be accessed by the DMA, at... - // 0x00000020 [5] CORE1 (1) If 1, SRAM0 can be accessed by core 1, at... - // 0x00000010 [4] CORE0 (1) If 1, SRAM0 can be accessed by core 0, at... - // 0x00000008 [3] SP (1) If 1, SRAM0 can be accessed from a Secure, Privileged context - // 0x00000004 [2] SU (1) If 1, and SP is also set, SRAM0 can be accessed from a... - // 0x00000002 [1] NSP (1) If 1, SRAM0 can be accessed from a Non-secure, Privileged context - // 0x00000001 [0] NSU (1) If 1, and NSP is also set, SRAM0 can be accessed from a... - io_rw_32 sram[10]; - - _REG_(ACCESSCTRL_DMA_OFFSET) // ACCESSCTRL_DMA - // Control access to DMA. Defaults to Secure access from any master. - // 0x00000080 [7] DBG (1) If 1, DMA can be accessed by the debugger, at... - // 0x00000040 [6] DMA (1) If 1, DMA can be accessed by the DMA, at... - // 0x00000020 [5] CORE1 (1) If 1, DMA can be accessed by core 1, at... - // 0x00000010 [4] CORE0 (1) If 1, DMA can be accessed by core 0, at... - // 0x00000008 [3] SP (1) If 1, DMA can be accessed from a Secure, Privileged context - // 0x00000004 [2] SU (1) If 1, and SP is also set, DMA can be accessed from a... - // 0x00000002 [1] NSP (0) If 1, DMA can be accessed from a Non-secure, Privileged context - // 0x00000001 [0] NSU (0) If 1, and NSP is also set, DMA can be accessed from a... - io_rw_32 dma; - - _REG_(ACCESSCTRL_USBCTRL_OFFSET) // ACCESSCTRL_USBCTRL - // Control access to USBCTRL. Defaults to Secure access from any master. - // 0x00000080 [7] DBG (1) If 1, USBCTRL can be accessed by the debugger, at... - // 0x00000040 [6] DMA (1) If 1, USBCTRL can be accessed by the DMA, at... - // 0x00000020 [5] CORE1 (1) If 1, USBCTRL can be accessed by core 1, at... - // 0x00000010 [4] CORE0 (1) If 1, USBCTRL can be accessed by core 0, at... - // 0x00000008 [3] SP (1) If 1, USBCTRL can be accessed from a Secure, Privileged context - // 0x00000004 [2] SU (1) If 1, and SP is also set, USBCTRL can be accessed from a... - // 0x00000002 [1] NSP (0) If 1, USBCTRL can be accessed from a Non-secure,... - // 0x00000001 [0] NSU (0) If 1, and NSP is also set, USBCTRL can be accessed from... - io_rw_32 usbctrl; - - // (Description copied from array index 0 register ACCESSCTRL_PIO0 applies similarly to other array indexes) - _REG_(ACCESSCTRL_PIO0_OFFSET) // ACCESSCTRL_PIO0 - // Control access to PIO0. Defaults to Secure access from any master. - // 0x00000080 [7] DBG (1) If 1, PIO0 can be accessed by the debugger, at... - // 0x00000040 [6] DMA (1) If 1, PIO0 can be accessed by the DMA, at... - // 0x00000020 [5] CORE1 (1) If 1, PIO0 can be accessed by core 1, at... - // 0x00000010 [4] CORE0 (1) If 1, PIO0 can be accessed by core 0, at... - // 0x00000008 [3] SP (1) If 1, PIO0 can be accessed from a Secure, Privileged context - // 0x00000004 [2] SU (1) If 1, and SP is also set, PIO0 can be accessed from a... - // 0x00000002 [1] NSP (0) If 1, PIO0 can be accessed from a Non-secure, Privileged context - // 0x00000001 [0] NSU (0) If 1, and NSP is also set, PIO0 can be accessed from a... - io_rw_32 pio[3]; - - _REG_(ACCESSCTRL_CORESIGHT_TRACE_OFFSET) // ACCESSCTRL_CORESIGHT_TRACE - // Control access to CORESIGHT_TRACE. Defaults to Secure, Privileged processor or debug access only. - // 0x00000080 [7] DBG (1) If 1, CORESIGHT_TRACE can be accessed by the debugger,... - // 0x00000040 [6] DMA (0) If 1, CORESIGHT_TRACE can be accessed by the DMA, at... - // 0x00000020 [5] CORE1 (1) If 1, CORESIGHT_TRACE can be accessed by core 1, at... - // 0x00000010 [4] CORE0 (1) If 1, CORESIGHT_TRACE can be accessed by core 0, at... - // 0x00000008 [3] SP (1) If 1, CORESIGHT_TRACE can be accessed from a Secure,... - // 0x00000004 [2] SU (0) If 1, and SP is also set, CORESIGHT_TRACE can be... - // 0x00000002 [1] NSP (0) If 1, CORESIGHT_TRACE can be accessed from a Non-secure,... - // 0x00000001 [0] NSU (0) If 1, and NSP is also set, CORESIGHT_TRACE can be... - io_rw_32 coresight_trace; - - _REG_(ACCESSCTRL_CORESIGHT_PERIPH_OFFSET) // ACCESSCTRL_CORESIGHT_PERIPH - // Control access to CORESIGHT_PERIPH. Defaults to Secure, Privileged processor or debug access only. - // 0x00000080 [7] DBG (1) If 1, CORESIGHT_PERIPH can be accessed by the debugger,... - // 0x00000040 [6] DMA (0) If 1, CORESIGHT_PERIPH can be accessed by the DMA, at... - // 0x00000020 [5] CORE1 (1) If 1, CORESIGHT_PERIPH can be accessed by core 1, at... - // 0x00000010 [4] CORE0 (1) If 1, CORESIGHT_PERIPH can be accessed by core 0, at... - // 0x00000008 [3] SP (1) If 1, CORESIGHT_PERIPH can be accessed from a Secure,... - // 0x00000004 [2] SU (0) If 1, and SP is also set, CORESIGHT_PERIPH can be... - // 0x00000002 [1] NSP (0) If 1, CORESIGHT_PERIPH can be accessed from a... - // 0x00000001 [0] NSU (0) If 1, and NSP is also set, CORESIGHT_PERIPH can be... - io_rw_32 coresight_periph; - - _REG_(ACCESSCTRL_SYSINFO_OFFSET) // ACCESSCTRL_SYSINFO - // Control access to SYSINFO. Defaults to fully open access. - // 0x00000080 [7] DBG (1) If 1, SYSINFO can be accessed by the debugger, at... - // 0x00000040 [6] DMA (1) If 1, SYSINFO can be accessed by the DMA, at... - // 0x00000020 [5] CORE1 (1) If 1, SYSINFO can be accessed by core 1, at... - // 0x00000010 [4] CORE0 (1) If 1, SYSINFO can be accessed by core 0, at... - // 0x00000008 [3] SP (1) If 1, SYSINFO can be accessed from a Secure, Privileged context - // 0x00000004 [2] SU (1) If 1, and SP is also set, SYSINFO can be accessed from a... - // 0x00000002 [1] NSP (1) If 1, SYSINFO can be accessed from a Non-secure,... - // 0x00000001 [0] NSU (1) If 1, and NSP is also set, SYSINFO can be accessed from... - io_rw_32 sysinfo; - - _REG_(ACCESSCTRL_RESETS_OFFSET) // ACCESSCTRL_RESETS - // Control access to RESETS. Defaults to Secure access from any master. - // 0x00000080 [7] DBG (1) If 1, RESETS can be accessed by the debugger, at... - // 0x00000040 [6] DMA (1) If 1, RESETS can be accessed by the DMA, at... - // 0x00000020 [5] CORE1 (1) If 1, RESETS can be accessed by core 1, at... - // 0x00000010 [4] CORE0 (1) If 1, RESETS can be accessed by core 0, at... - // 0x00000008 [3] SP (1) If 1, RESETS can be accessed from a Secure, Privileged context - // 0x00000004 [2] SU (1) If 1, and SP is also set, RESETS can be accessed from a... - // 0x00000002 [1] NSP (0) If 1, RESETS can be accessed from a Non-secure,... - // 0x00000001 [0] NSU (0) If 1, and NSP is also set, RESETS can be accessed from a... - io_rw_32 resets; - - // (Description copied from array index 0 register ACCESSCTRL_IO_BANK0 applies similarly to other array indexes) - _REG_(ACCESSCTRL_IO_BANK0_OFFSET) // ACCESSCTRL_IO_BANK0 - // Control access to IO_BANK0. Defaults to Secure access from any master. - // 0x00000080 [7] DBG (1) If 1, IO_BANK0 can be accessed by the debugger, at... - // 0x00000040 [6] DMA (1) If 1, IO_BANK0 can be accessed by the DMA, at... - // 0x00000020 [5] CORE1 (1) If 1, IO_BANK0 can be accessed by core 1, at... - // 0x00000010 [4] CORE0 (1) If 1, IO_BANK0 can be accessed by core 0, at... - // 0x00000008 [3] SP (1) If 1, IO_BANK0 can be accessed from a Secure, Privileged context - // 0x00000004 [2] SU (1) If 1, and SP is also set, IO_BANK0 can be accessed from... - // 0x00000002 [1] NSP (0) If 1, IO_BANK0 can be accessed from a Non-secure,... - // 0x00000001 [0] NSU (0) If 1, and NSP is also set, IO_BANK0 can be accessed from... - io_rw_32 io_bank[2]; - - _REG_(ACCESSCTRL_PADS_BANK0_OFFSET) // ACCESSCTRL_PADS_BANK0 - // Control access to PADS_BANK0. Defaults to Secure access from any master. - // 0x00000080 [7] DBG (1) If 1, PADS_BANK0 can be accessed by the debugger, at... - // 0x00000040 [6] DMA (1) If 1, PADS_BANK0 can be accessed by the DMA, at... - // 0x00000020 [5] CORE1 (1) If 1, PADS_BANK0 can be accessed by core 1, at... - // 0x00000010 [4] CORE0 (1) If 1, PADS_BANK0 can be accessed by core 0, at... - // 0x00000008 [3] SP (1) If 1, PADS_BANK0 can be accessed from a Secure,... - // 0x00000004 [2] SU (1) If 1, and SP is also set, PADS_BANK0 can be accessed... - // 0x00000002 [1] NSP (0) If 1, PADS_BANK0 can be accessed from a Non-secure,... - // 0x00000001 [0] NSU (0) If 1, and NSP is also set, PADS_BANK0 can be accessed... - io_rw_32 pads_bank0; - - _REG_(ACCESSCTRL_PADS_QSPI_OFFSET) // ACCESSCTRL_PADS_QSPI - // Control access to PADS_QSPI. Defaults to Secure access from any master. - // 0x00000080 [7] DBG (1) If 1, PADS_QSPI can be accessed by the debugger, at... - // 0x00000040 [6] DMA (1) If 1, PADS_QSPI can be accessed by the DMA, at... - // 0x00000020 [5] CORE1 (1) If 1, PADS_QSPI can be accessed by core 1, at... - // 0x00000010 [4] CORE0 (1) If 1, PADS_QSPI can be accessed by core 0, at... - // 0x00000008 [3] SP (1) If 1, PADS_QSPI can be accessed from a Secure, Privileged context - // 0x00000004 [2] SU (1) If 1, and SP is also set, PADS_QSPI can be accessed from... - // 0x00000002 [1] NSP (0) If 1, PADS_QSPI can be accessed from a Non-secure,... - // 0x00000001 [0] NSU (0) If 1, and NSP is also set, PADS_QSPI can be accessed... - io_rw_32 pads_qspi; - - _REG_(ACCESSCTRL_BUSCTRL_OFFSET) // ACCESSCTRL_BUSCTRL - // Control access to BUSCTRL. Defaults to Secure access from any master. - // 0x00000080 [7] DBG (1) If 1, BUSCTRL can be accessed by the debugger, at... - // 0x00000040 [6] DMA (1) If 1, BUSCTRL can be accessed by the DMA, at... - // 0x00000020 [5] CORE1 (1) If 1, BUSCTRL can be accessed by core 1, at... - // 0x00000010 [4] CORE0 (1) If 1, BUSCTRL can be accessed by core 0, at... - // 0x00000008 [3] SP (1) If 1, BUSCTRL can be accessed from a Secure, Privileged context - // 0x00000004 [2] SU (1) If 1, and SP is also set, BUSCTRL can be accessed from a... - // 0x00000002 [1] NSP (0) If 1, BUSCTRL can be accessed from a Non-secure,... - // 0x00000001 [0] NSU (0) If 1, and NSP is also set, BUSCTRL can be accessed from... - io_rw_32 busctrl; - - _REG_(ACCESSCTRL_ADC0_OFFSET) // ACCESSCTRL_ADC0 - // Control access to ADC0. Defaults to Secure access from any master. - // 0x00000080 [7] DBG (1) If 1, ADC0 can be accessed by the debugger, at... - // 0x00000040 [6] DMA (1) If 1, ADC0 can be accessed by the DMA, at... - // 0x00000020 [5] CORE1 (1) If 1, ADC0 can be accessed by core 1, at... - // 0x00000010 [4] CORE0 (1) If 1, ADC0 can be accessed by core 0, at... - // 0x00000008 [3] SP (1) If 1, ADC0 can be accessed from a Secure, Privileged context - // 0x00000004 [2] SU (1) If 1, and SP is also set, ADC0 can be accessed from a... - // 0x00000002 [1] NSP (0) If 1, ADC0 can be accessed from a Non-secure, Privileged context - // 0x00000001 [0] NSU (0) If 1, and NSP is also set, ADC0 can be accessed from a... - io_rw_32 adc0; - - _REG_(ACCESSCTRL_HSTX_OFFSET) // ACCESSCTRL_HSTX - // Control access to HSTX. Defaults to Secure access from any master. - // 0x00000080 [7] DBG (1) If 1, HSTX can be accessed by the debugger, at... - // 0x00000040 [6] DMA (1) If 1, HSTX can be accessed by the DMA, at... - // 0x00000020 [5] CORE1 (1) If 1, HSTX can be accessed by core 1, at... - // 0x00000010 [4] CORE0 (1) If 1, HSTX can be accessed by core 0, at... - // 0x00000008 [3] SP (1) If 1, HSTX can be accessed from a Secure, Privileged context - // 0x00000004 [2] SU (1) If 1, and SP is also set, HSTX can be accessed from a... - // 0x00000002 [1] NSP (0) If 1, HSTX can be accessed from a Non-secure, Privileged context - // 0x00000001 [0] NSU (0) If 1, and NSP is also set, HSTX can be accessed from a... - io_rw_32 hstx; - - // (Description copied from array index 0 register ACCESSCTRL_I2C0 applies similarly to other array indexes) - _REG_(ACCESSCTRL_I2C0_OFFSET) // ACCESSCTRL_I2C0 - // Control access to I2C0. Defaults to Secure access from any master. - // 0x00000080 [7] DBG (1) If 1, I2C0 can be accessed by the debugger, at... - // 0x00000040 [6] DMA (1) If 1, I2C0 can be accessed by the DMA, at... - // 0x00000020 [5] CORE1 (1) If 1, I2C0 can be accessed by core 1, at... - // 0x00000010 [4] CORE0 (1) If 1, I2C0 can be accessed by core 0, at... - // 0x00000008 [3] SP (1) If 1, I2C0 can be accessed from a Secure, Privileged context - // 0x00000004 [2] SU (1) If 1, and SP is also set, I2C0 can be accessed from a... - // 0x00000002 [1] NSP (0) If 1, I2C0 can be accessed from a Non-secure, Privileged context - // 0x00000001 [0] NSU (0) If 1, and NSP is also set, I2C0 can be accessed from a... - io_rw_32 i2c[2]; - - _REG_(ACCESSCTRL_PWM_OFFSET) // ACCESSCTRL_PWM - // Control access to PWM. Defaults to Secure access from any master. - // 0x00000080 [7] DBG (1) If 1, PWM can be accessed by the debugger, at... - // 0x00000040 [6] DMA (1) If 1, PWM can be accessed by the DMA, at... - // 0x00000020 [5] CORE1 (1) If 1, PWM can be accessed by core 1, at... - // 0x00000010 [4] CORE0 (1) If 1, PWM can be accessed by core 0, at... - // 0x00000008 [3] SP (1) If 1, PWM can be accessed from a Secure, Privileged context - // 0x00000004 [2] SU (1) If 1, and SP is also set, PWM can be accessed from a... - // 0x00000002 [1] NSP (0) If 1, PWM can be accessed from a Non-secure, Privileged context - // 0x00000001 [0] NSU (0) If 1, and NSP is also set, PWM can be accessed from a... - io_rw_32 pwm; - - // (Description copied from array index 0 register ACCESSCTRL_SPI0 applies similarly to other array indexes) - _REG_(ACCESSCTRL_SPI0_OFFSET) // ACCESSCTRL_SPI0 - // Control access to SPI0. Defaults to Secure access from any master. - // 0x00000080 [7] DBG (1) If 1, SPI0 can be accessed by the debugger, at... - // 0x00000040 [6] DMA (1) If 1, SPI0 can be accessed by the DMA, at... - // 0x00000020 [5] CORE1 (1) If 1, SPI0 can be accessed by core 1, at... - // 0x00000010 [4] CORE0 (1) If 1, SPI0 can be accessed by core 0, at... - // 0x00000008 [3] SP (1) If 1, SPI0 can be accessed from a Secure, Privileged context - // 0x00000004 [2] SU (1) If 1, and SP is also set, SPI0 can be accessed from a... - // 0x00000002 [1] NSP (0) If 1, SPI0 can be accessed from a Non-secure, Privileged context - // 0x00000001 [0] NSU (0) If 1, and NSP is also set, SPI0 can be accessed from a... - io_rw_32 spi[2]; - - // (Description copied from array index 0 register ACCESSCTRL_TIMER0 applies similarly to other array indexes) - _REG_(ACCESSCTRL_TIMER0_OFFSET) // ACCESSCTRL_TIMER0 - // Control access to TIMER0. Defaults to Secure access from any master. - // 0x00000080 [7] DBG (1) If 1, TIMER0 can be accessed by the debugger, at... - // 0x00000040 [6] DMA (1) If 1, TIMER0 can be accessed by the DMA, at... - // 0x00000020 [5] CORE1 (1) If 1, TIMER0 can be accessed by core 1, at... - // 0x00000010 [4] CORE0 (1) If 1, TIMER0 can be accessed by core 0, at... - // 0x00000008 [3] SP (1) If 1, TIMER0 can be accessed from a Secure, Privileged context - // 0x00000004 [2] SU (1) If 1, and SP is also set, TIMER0 can be accessed from a... - // 0x00000002 [1] NSP (0) If 1, TIMER0 can be accessed from a Non-secure,... - // 0x00000001 [0] NSU (0) If 1, and NSP is also set, TIMER0 can be accessed from a... - io_rw_32 timer[2]; - - // (Description copied from array index 0 register ACCESSCTRL_UART0 applies similarly to other array indexes) - _REG_(ACCESSCTRL_UART0_OFFSET) // ACCESSCTRL_UART0 - // Control access to UART0. Defaults to Secure access from any master. - // 0x00000080 [7] DBG (1) If 1, UART0 can be accessed by the debugger, at... - // 0x00000040 [6] DMA (1) If 1, UART0 can be accessed by the DMA, at... - // 0x00000020 [5] CORE1 (1) If 1, UART0 can be accessed by core 1, at... - // 0x00000010 [4] CORE0 (1) If 1, UART0 can be accessed by core 0, at... - // 0x00000008 [3] SP (1) If 1, UART0 can be accessed from a Secure, Privileged context - // 0x00000004 [2] SU (1) If 1, and SP is also set, UART0 can be accessed from a... - // 0x00000002 [1] NSP (0) If 1, UART0 can be accessed from a Non-secure, Privileged context - // 0x00000001 [0] NSU (0) If 1, and NSP is also set, UART0 can be accessed from a... - io_rw_32 uart[2]; - - _REG_(ACCESSCTRL_OTP_OFFSET) // ACCESSCTRL_OTP - // Control access to OTP. Defaults to Secure access from any master. - // 0x00000080 [7] DBG (1) If 1, OTP can be accessed by the debugger, at... - // 0x00000040 [6] DMA (1) If 1, OTP can be accessed by the DMA, at... - // 0x00000020 [5] CORE1 (1) If 1, OTP can be accessed by core 1, at... - // 0x00000010 [4] CORE0 (1) If 1, OTP can be accessed by core 0, at... - // 0x00000008 [3] SP (1) If 1, OTP can be accessed from a Secure, Privileged context - // 0x00000004 [2] SU (1) If 1, and SP is also set, OTP can be accessed from a... - // 0x00000002 [1] NSP (0) If 1, OTP can be accessed from a Non-secure, Privileged context - // 0x00000001 [0] NSU (0) If 1, and NSP is also set, OTP can be accessed from a... - io_rw_32 otp; - - _REG_(ACCESSCTRL_TBMAN_OFFSET) // ACCESSCTRL_TBMAN - // Control access to TBMAN. Defaults to Secure access from any master. - // 0x00000080 [7] DBG (1) If 1, TBMAN can be accessed by the debugger, at... - // 0x00000040 [6] DMA (1) If 1, TBMAN can be accessed by the DMA, at... - // 0x00000020 [5] CORE1 (1) If 1, TBMAN can be accessed by core 1, at... - // 0x00000010 [4] CORE0 (1) If 1, TBMAN can be accessed by core 0, at... - // 0x00000008 [3] SP (1) If 1, TBMAN can be accessed from a Secure, Privileged context - // 0x00000004 [2] SU (1) If 1, and SP is also set, TBMAN can be accessed from a... - // 0x00000002 [1] NSP (0) If 1, TBMAN can be accessed from a Non-secure, Privileged context - // 0x00000001 [0] NSU (0) If 1, and NSP is also set, TBMAN can be accessed from a... - io_rw_32 tbman; - - _REG_(ACCESSCTRL_POWMAN_OFFSET) // ACCESSCTRL_POWMAN - // Control access to POWMAN. Defaults to Secure, Privileged processor or debug access only. - // 0x00000080 [7] DBG (1) If 1, POWMAN can be accessed by the debugger, at... - // 0x00000040 [6] DMA (0) If 1, POWMAN can be accessed by the DMA, at... - // 0x00000020 [5] CORE1 (1) If 1, POWMAN can be accessed by core 1, at... - // 0x00000010 [4] CORE0 (1) If 1, POWMAN can be accessed by core 0, at... - // 0x00000008 [3] SP (1) If 1, POWMAN can be accessed from a Secure, Privileged context - // 0x00000004 [2] SU (0) If 1, and SP is also set, POWMAN can be accessed from a... - // 0x00000002 [1] NSP (0) If 1, POWMAN can be accessed from a Non-secure,... - // 0x00000001 [0] NSU (0) If 1, and NSP is also set, POWMAN can be accessed from a... - io_rw_32 powman; - - _REG_(ACCESSCTRL_TRNG_OFFSET) // ACCESSCTRL_TRNG - // Control access to TRNG. Defaults to Secure, Privileged processor or debug access only. - // 0x00000080 [7] DBG (1) If 1, TRNG can be accessed by the debugger, at... - // 0x00000040 [6] DMA (0) If 1, TRNG can be accessed by the DMA, at... - // 0x00000020 [5] CORE1 (1) If 1, TRNG can be accessed by core 1, at... - // 0x00000010 [4] CORE0 (1) If 1, TRNG can be accessed by core 0, at... - // 0x00000008 [3] SP (1) If 1, TRNG can be accessed from a Secure, Privileged context - // 0x00000004 [2] SU (0) If 1, and SP is also set, TRNG can be accessed from a... - // 0x00000002 [1] NSP (0) If 1, TRNG can be accessed from a Non-secure, Privileged context - // 0x00000001 [0] NSU (0) If 1, and NSP is also set, TRNG can be accessed from a... - io_rw_32 trng; - - _REG_(ACCESSCTRL_SHA256_OFFSET) // ACCESSCTRL_SHA256 - // Control access to SHA256. Defaults to Secure, Privileged access only. - // 0x00000080 [7] DBG (1) If 1, SHA256 can be accessed by the debugger, at... - // 0x00000040 [6] DMA (1) If 1, SHA256 can be accessed by the DMA, at... - // 0x00000020 [5] CORE1 (1) If 1, SHA256 can be accessed by core 1, at... - // 0x00000010 [4] CORE0 (1) If 1, SHA256 can be accessed by core 0, at... - // 0x00000008 [3] SP (1) If 1, SHA256 can be accessed from a Secure, Privileged context - // 0x00000004 [2] SU (0) If 1, and SP is also set, SHA256 can be accessed from a... - // 0x00000002 [1] NSP (0) If 1, SHA256 can be accessed from a Non-secure,... - // 0x00000001 [0] NSU (0) If 1, and NSP is also set, SHA256 can be accessed from a... - io_rw_32 sha256; - - _REG_(ACCESSCTRL_SYSCFG_OFFSET) // ACCESSCTRL_SYSCFG - // Control access to SYSCFG. Defaults to Secure, Privileged processor or debug access only. - // 0x00000080 [7] DBG (1) If 1, SYSCFG can be accessed by the debugger, at... - // 0x00000040 [6] DMA (0) If 1, SYSCFG can be accessed by the DMA, at... - // 0x00000020 [5] CORE1 (1) If 1, SYSCFG can be accessed by core 1, at... - // 0x00000010 [4] CORE0 (1) If 1, SYSCFG can be accessed by core 0, at... - // 0x00000008 [3] SP (1) If 1, SYSCFG can be accessed from a Secure, Privileged context - // 0x00000004 [2] SU (0) If 1, and SP is also set, SYSCFG can be accessed from a... - // 0x00000002 [1] NSP (0) If 1, SYSCFG can be accessed from a Non-secure,... - // 0x00000001 [0] NSU (0) If 1, and NSP is also set, SYSCFG can be accessed from a... - io_rw_32 syscfg; - - _REG_(ACCESSCTRL_CLOCKS_OFFSET) // ACCESSCTRL_CLOCKS - // Control access to CLOCKS. Defaults to Secure, Privileged processor or debug access only. - // 0x00000080 [7] DBG (1) If 1, CLOCKS can be accessed by the debugger, at... - // 0x00000040 [6] DMA (0) If 1, CLOCKS can be accessed by the DMA, at... - // 0x00000020 [5] CORE1 (1) If 1, CLOCKS can be accessed by core 1, at... - // 0x00000010 [4] CORE0 (1) If 1, CLOCKS can be accessed by core 0, at... - // 0x00000008 [3] SP (1) If 1, CLOCKS can be accessed from a Secure, Privileged context - // 0x00000004 [2] SU (0) If 1, and SP is also set, CLOCKS can be accessed from a... - // 0x00000002 [1] NSP (0) If 1, CLOCKS can be accessed from a Non-secure,... - // 0x00000001 [0] NSU (0) If 1, and NSP is also set, CLOCKS can be accessed from a... - io_rw_32 clocks; - - _REG_(ACCESSCTRL_XOSC_OFFSET) // ACCESSCTRL_XOSC - // Control access to XOSC. Defaults to Secure, Privileged processor or debug access only. - // 0x00000080 [7] DBG (1) If 1, XOSC can be accessed by the debugger, at... - // 0x00000040 [6] DMA (0) If 1, XOSC can be accessed by the DMA, at... - // 0x00000020 [5] CORE1 (1) If 1, XOSC can be accessed by core 1, at... - // 0x00000010 [4] CORE0 (1) If 1, XOSC can be accessed by core 0, at... - // 0x00000008 [3] SP (1) If 1, XOSC can be accessed from a Secure, Privileged context - // 0x00000004 [2] SU (0) If 1, and SP is also set, XOSC can be accessed from a... - // 0x00000002 [1] NSP (0) If 1, XOSC can be accessed from a Non-secure, Privileged context - // 0x00000001 [0] NSU (0) If 1, and NSP is also set, XOSC can be accessed from a... - io_rw_32 xosc; - - _REG_(ACCESSCTRL_ROSC_OFFSET) // ACCESSCTRL_ROSC - // Control access to ROSC. Defaults to Secure, Privileged processor or debug access only. - // 0x00000080 [7] DBG (1) If 1, ROSC can be accessed by the debugger, at... - // 0x00000040 [6] DMA (0) If 1, ROSC can be accessed by the DMA, at... - // 0x00000020 [5] CORE1 (1) If 1, ROSC can be accessed by core 1, at... - // 0x00000010 [4] CORE0 (1) If 1, ROSC can be accessed by core 0, at... - // 0x00000008 [3] SP (1) If 1, ROSC can be accessed from a Secure, Privileged context - // 0x00000004 [2] SU (0) If 1, and SP is also set, ROSC can be accessed from a... - // 0x00000002 [1] NSP (0) If 1, ROSC can be accessed from a Non-secure, Privileged context - // 0x00000001 [0] NSU (0) If 1, and NSP is also set, ROSC can be accessed from a... - io_rw_32 rosc; - - _REG_(ACCESSCTRL_PLL_SYS_OFFSET) // ACCESSCTRL_PLL_SYS - // Control access to PLL_SYS. Defaults to Secure, Privileged processor or debug access only. - // 0x00000080 [7] DBG (1) If 1, PLL_SYS can be accessed by the debugger, at... - // 0x00000040 [6] DMA (0) If 1, PLL_SYS can be accessed by the DMA, at... - // 0x00000020 [5] CORE1 (1) If 1, PLL_SYS can be accessed by core 1, at... - // 0x00000010 [4] CORE0 (1) If 1, PLL_SYS can be accessed by core 0, at... - // 0x00000008 [3] SP (1) If 1, PLL_SYS can be accessed from a Secure, Privileged context - // 0x00000004 [2] SU (0) If 1, and SP is also set, PLL_SYS can be accessed from a... - // 0x00000002 [1] NSP (0) If 1, PLL_SYS can be accessed from a Non-secure,... - // 0x00000001 [0] NSU (0) If 1, and NSP is also set, PLL_SYS can be accessed from... - io_rw_32 pll_sys; - - _REG_(ACCESSCTRL_PLL_USB_OFFSET) // ACCESSCTRL_PLL_USB - // Control access to PLL_USB. Defaults to Secure, Privileged processor or debug access only. - // 0x00000080 [7] DBG (1) If 1, PLL_USB can be accessed by the debugger, at... - // 0x00000040 [6] DMA (0) If 1, PLL_USB can be accessed by the DMA, at... - // 0x00000020 [5] CORE1 (1) If 1, PLL_USB can be accessed by core 1, at... - // 0x00000010 [4] CORE0 (1) If 1, PLL_USB can be accessed by core 0, at... - // 0x00000008 [3] SP (1) If 1, PLL_USB can be accessed from a Secure, Privileged context - // 0x00000004 [2] SU (0) If 1, and SP is also set, PLL_USB can be accessed from a... - // 0x00000002 [1] NSP (0) If 1, PLL_USB can be accessed from a Non-secure,... - // 0x00000001 [0] NSU (0) If 1, and NSP is also set, PLL_USB can be accessed from... - io_rw_32 pll_usb; - - _REG_(ACCESSCTRL_TICKS_OFFSET) // ACCESSCTRL_TICKS - // Control access to TICKS. Defaults to Secure, Privileged processor or debug access only. - // 0x00000080 [7] DBG (1) If 1, TICKS can be accessed by the debugger, at... - // 0x00000040 [6] DMA (0) If 1, TICKS can be accessed by the DMA, at... - // 0x00000020 [5] CORE1 (1) If 1, TICKS can be accessed by core 1, at... - // 0x00000010 [4] CORE0 (1) If 1, TICKS can be accessed by core 0, at... - // 0x00000008 [3] SP (1) If 1, TICKS can be accessed from a Secure, Privileged context - // 0x00000004 [2] SU (0) If 1, and SP is also set, TICKS can be accessed from a... - // 0x00000002 [1] NSP (0) If 1, TICKS can be accessed from a Non-secure, Privileged context - // 0x00000001 [0] NSU (0) If 1, and NSP is also set, TICKS can be accessed from a... - io_rw_32 ticks; - - _REG_(ACCESSCTRL_WATCHDOG_OFFSET) // ACCESSCTRL_WATCHDOG - // Control access to WATCHDOG. Defaults to Secure, Privileged processor or debug access only. - // 0x00000080 [7] DBG (1) If 1, WATCHDOG can be accessed by the debugger, at... - // 0x00000040 [6] DMA (0) If 1, WATCHDOG can be accessed by the DMA, at... - // 0x00000020 [5] CORE1 (1) If 1, WATCHDOG can be accessed by core 1, at... - // 0x00000010 [4] CORE0 (1) If 1, WATCHDOG can be accessed by core 0, at... - // 0x00000008 [3] SP (1) If 1, WATCHDOG can be accessed from a Secure, Privileged context - // 0x00000004 [2] SU (0) If 1, and SP is also set, WATCHDOG can be accessed from... - // 0x00000002 [1] NSP (0) If 1, WATCHDOG can be accessed from a Non-secure,... - // 0x00000001 [0] NSU (0) If 1, and NSP is also set, WATCHDOG can be accessed from... - io_rw_32 watchdog; - - _REG_(ACCESSCTRL_RSM_OFFSET) // ACCESSCTRL_RSM - // Control access to RSM. Defaults to Secure, Privileged processor or debug access only. - // 0x00000080 [7] DBG (1) If 1, RSM can be accessed by the debugger, at... - // 0x00000040 [6] DMA (0) If 1, RSM can be accessed by the DMA, at... - // 0x00000020 [5] CORE1 (1) If 1, RSM can be accessed by core 1, at... - // 0x00000010 [4] CORE0 (1) If 1, RSM can be accessed by core 0, at... - // 0x00000008 [3] SP (1) If 1, RSM can be accessed from a Secure, Privileged context - // 0x00000004 [2] SU (0) If 1, and SP is also set, RSM can be accessed from a... - // 0x00000002 [1] NSP (0) If 1, RSM can be accessed from a Non-secure, Privileged context - // 0x00000001 [0] NSU (0) If 1, and NSP is also set, RSM can be accessed from a... - io_rw_32 rsm; - - _REG_(ACCESSCTRL_XIP_CTRL_OFFSET) // ACCESSCTRL_XIP_CTRL - // Control access to XIP_CTRL. Defaults to Secure, Privileged processor or debug access only. - // 0x00000080 [7] DBG (1) If 1, XIP_CTRL can be accessed by the debugger, at... - // 0x00000040 [6] DMA (0) If 1, XIP_CTRL can be accessed by the DMA, at... - // 0x00000020 [5] CORE1 (1) If 1, XIP_CTRL can be accessed by core 1, at... - // 0x00000010 [4] CORE0 (1) If 1, XIP_CTRL can be accessed by core 0, at... - // 0x00000008 [3] SP (1) If 1, XIP_CTRL can be accessed from a Secure, Privileged context - // 0x00000004 [2] SU (0) If 1, and SP is also set, XIP_CTRL can be accessed from... - // 0x00000002 [1] NSP (0) If 1, XIP_CTRL can be accessed from a Non-secure,... - // 0x00000001 [0] NSU (0) If 1, and NSP is also set, XIP_CTRL can be accessed from... - io_rw_32 xip_ctrl; - - _REG_(ACCESSCTRL_XIP_QMI_OFFSET) // ACCESSCTRL_XIP_QMI - // Control access to XIP_QMI. Defaults to Secure, Privileged processor or debug access only. - // 0x00000080 [7] DBG (1) If 1, XIP_QMI can be accessed by the debugger, at... - // 0x00000040 [6] DMA (0) If 1, XIP_QMI can be accessed by the DMA, at... - // 0x00000020 [5] CORE1 (1) If 1, XIP_QMI can be accessed by core 1, at... - // 0x00000010 [4] CORE0 (1) If 1, XIP_QMI can be accessed by core 0, at... - // 0x00000008 [3] SP (1) If 1, XIP_QMI can be accessed from a Secure, Privileged context - // 0x00000004 [2] SU (0) If 1, and SP is also set, XIP_QMI can be accessed from a... - // 0x00000002 [1] NSP (0) If 1, XIP_QMI can be accessed from a Non-secure,... - // 0x00000001 [0] NSU (0) If 1, and NSP is also set, XIP_QMI can be accessed from... - io_rw_32 xip_qmi; - - _REG_(ACCESSCTRL_XIP_AUX_OFFSET) // ACCESSCTRL_XIP_AUX - // Control access to XIP_AUX. Defaults to Secure, Privileged access only. - // 0x00000080 [7] DBG (1) If 1, XIP_AUX can be accessed by the debugger, at... - // 0x00000040 [6] DMA (1) If 1, XIP_AUX can be accessed by the DMA, at... - // 0x00000020 [5] CORE1 (1) If 1, XIP_AUX can be accessed by core 1, at... - // 0x00000010 [4] CORE0 (1) If 1, XIP_AUX can be accessed by core 0, at... - // 0x00000008 [3] SP (1) If 1, XIP_AUX can be accessed from a Secure, Privileged context - // 0x00000004 [2] SU (0) If 1, and SP is also set, XIP_AUX can be accessed from a... - // 0x00000002 [1] NSP (0) If 1, XIP_AUX can be accessed from a Non-secure,... - // 0x00000001 [0] NSU (0) If 1, and NSP is also set, XIP_AUX can be accessed from... - io_rw_32 xip_aux; -} accessctrl_hw_t; - -#define accessctrl_hw ((accessctrl_hw_t *)ACCESSCTRL_BASE) -static_assert(sizeof (accessctrl_hw_t) == 0x00ec, ""); - -#endif // _HARDWARE_STRUCTS_ACCESSCTRL_H - diff --git a/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/adc.h b/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/adc.h deleted file mode 100644 index 687128eba3..0000000000 --- a/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/adc.h +++ /dev/null @@ -1,96 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _HARDWARE_STRUCTS_ADC_H -#define _HARDWARE_STRUCTS_ADC_H - -/** - * \file rp2350/adc.h - */ - -#include "hardware/address_mapped.h" -#include "hardware/regs/adc.h" - -// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_adc -// -// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) -// _REG_(x) will link to the corresponding register in hardware/regs/adc.h. -// -// Bit-field descriptions are of the form: -// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION - -typedef struct { - _REG_(ADC_CS_OFFSET) // ADC_CS - // ADC Control and Status - // 0x01ff0000 [24:16] RROBIN (0x000) Round-robin sampling - // 0x0000f000 [15:12] AINSEL (0x0) Select analog mux input - // 0x00000400 [10] ERR_STICKY (0) Some past ADC conversion encountered an error - // 0x00000200 [9] ERR (0) The most recent ADC conversion encountered an error;... - // 0x00000100 [8] READY (0) 1 if the ADC is ready to start a new conversion - // 0x00000008 [3] START_MANY (0) Continuously perform conversions whilst this bit is 1 - // 0x00000004 [2] START_ONCE (0) Start a single conversion - // 0x00000002 [1] TS_EN (0) Power on temperature sensor - // 0x00000001 [0] EN (0) Power on ADC and enable its clock - io_rw_32 cs; - - _REG_(ADC_RESULT_OFFSET) // ADC_RESULT - // Result of most recent ADC conversion - // 0x00000fff [11:0] RESULT (0x000) - io_ro_32 result; - - _REG_(ADC_FCS_OFFSET) // ADC_FCS - // FIFO control and status - // 0x0f000000 [27:24] THRESH (0x0) DREQ/IRQ asserted when level >= threshold - // 0x000f0000 [19:16] LEVEL (0x0) The number of conversion results currently waiting in the FIFO - // 0x00000800 [11] OVER (0) 1 if the FIFO has been overflowed - // 0x00000400 [10] UNDER (0) 1 if the FIFO has been underflowed - // 0x00000200 [9] FULL (0) - // 0x00000100 [8] EMPTY (0) - // 0x00000008 [3] DREQ_EN (0) If 1: assert DMA requests when FIFO contains data - // 0x00000004 [2] ERR (0) If 1: conversion error bit appears in the FIFO alongside... - // 0x00000002 [1] SHIFT (0) If 1: FIFO results are right-shifted to be one byte in size - // 0x00000001 [0] EN (0) If 1: write result to the FIFO after each conversion - io_rw_32 fcs; - - _REG_(ADC_FIFO_OFFSET) // ADC_FIFO - // Conversion result FIFO - // 0x00008000 [15] ERR (-) 1 if this particular sample experienced a conversion error - // 0x00000fff [11:0] VAL (-) - io_ro_32 fifo; - - _REG_(ADC_DIV_OFFSET) // ADC_DIV - // Clock divider - // 0x00ffff00 [23:8] INT (0x0000) Integer part of clock divisor - // 0x000000ff [7:0] FRAC (0x00) Fractional part of clock divisor - io_rw_32 div; - - _REG_(ADC_INTR_OFFSET) // ADC_INTR - // Raw Interrupts - // 0x00000001 [0] FIFO (0) Triggered when the sample FIFO reaches a certain level - io_ro_32 intr; - - _REG_(ADC_INTE_OFFSET) // ADC_INTE - // Interrupt Enable - // 0x00000001 [0] FIFO (0) Triggered when the sample FIFO reaches a certain level - io_rw_32 inte; - - _REG_(ADC_INTF_OFFSET) // ADC_INTF - // Interrupt Force - // 0x00000001 [0] FIFO (0) Triggered when the sample FIFO reaches a certain level - io_rw_32 intf; - - _REG_(ADC_INTS_OFFSET) // ADC_INTS - // Interrupt status after masking & forcing - // 0x00000001 [0] FIFO (0) Triggered when the sample FIFO reaches a certain level - io_ro_32 ints; -} adc_hw_t; - -#define adc_hw ((adc_hw_t *)ADC_BASE) -static_assert(sizeof (adc_hw_t) == 0x0024, ""); - -#endif // _HARDWARE_STRUCTS_ADC_H - diff --git a/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/bootram.h b/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/bootram.h deleted file mode 100644 index b40a0393f3..0000000000 --- a/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/bootram.h +++ /dev/null @@ -1,49 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _HARDWARE_STRUCTS_BOOTRAM_H -#define _HARDWARE_STRUCTS_BOOTRAM_H - -/** - * \file rp2350/bootram.h - */ - -#include "hardware/address_mapped.h" -#include "hardware/regs/bootram.h" - -// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_bootram -// -// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) -// _REG_(x) will link to the corresponding register in hardware/regs/bootram.h. -// -// Bit-field descriptions are of the form: -// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION - -typedef struct { - // (Description copied from array index 0 register BOOTRAM_WRITE_ONCE0 applies similarly to other array indexes) - _REG_(BOOTRAM_WRITE_ONCE0_OFFSET) // BOOTRAM_WRITE_ONCE0 - // This registers always ORs writes into its current contents - // 0xffffffff [31:0] WRITE_ONCE0 (0x00000000) - io_rw_32 write_once[2]; - - _REG_(BOOTRAM_BOOTLOCK_STAT_OFFSET) // BOOTRAM_BOOTLOCK_STAT - // Bootlock status register - // 0x000000ff [7:0] BOOTLOCK_STAT (0xff) - io_rw_32 bootlock_stat; - - // (Description copied from array index 0 register BOOTRAM_BOOTLOCK0 applies similarly to other array indexes) - _REG_(BOOTRAM_BOOTLOCK0_OFFSET) // BOOTRAM_BOOTLOCK0 - // Read to claim and check - // 0xffffffff [31:0] BOOTLOCK0 (0x00000000) - io_rw_32 bootlock[8]; -} bootram_hw_t; - -#define bootram_hw ((bootram_hw_t *)(BOOTRAM_BASE + BOOTRAM_WRITE_ONCE0_OFFSET)) -static_assert(sizeof (bootram_hw_t) == 0x002c, ""); - -#endif // _HARDWARE_STRUCTS_BOOTRAM_H - diff --git a/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/bus_ctrl.h b/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/bus_ctrl.h deleted file mode 100644 index b94a40459c..0000000000 --- a/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/bus_ctrl.h +++ /dev/null @@ -1,9 +0,0 @@ -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -// Support old header for compatibility (and if included, support old variable name) -#include "hardware/structs/busctrl.h" -#define bus_ctrl_hw busctrl_hw \ No newline at end of file diff --git a/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/busctrl.h b/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/busctrl.h deleted file mode 100644 index 2eb83a9925..0000000000 --- a/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/busctrl.h +++ /dev/null @@ -1,90 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _HARDWARE_STRUCTS_BUSCTRL_H -#define _HARDWARE_STRUCTS_BUSCTRL_H - -/** - * \file rp2350/busctrl.h - */ - -#include "hardware/address_mapped.h" -#include "hardware/regs/busctrl.h" - -// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_busctrl -// -// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) -// _REG_(x) will link to the corresponding register in hardware/regs/busctrl.h. -// -// Bit-field descriptions are of the form: -// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION - -/** \brief Bus fabric performance counters on RP2350 (used as typedef \ref bus_ctrl_perf_counter_t) - * \ingroup hardware_busctrl - */ -typedef enum bus_ctrl_perf_counter_rp2350 { - arbiter_rom_perf_event_access = 19, - arbiter_rom_perf_event_access_contested = 18, - arbiter_xip_main_perf_event_access = 17, - arbiter_xip_main_perf_event_access_contested = 16, - arbiter_sram0_perf_event_access = 15, - arbiter_sram0_perf_event_access_contested = 14, - arbiter_sram1_perf_event_access = 13, - arbiter_sram1_perf_event_access_contested = 12, - arbiter_sram2_perf_event_access = 11, - arbiter_sram2_perf_event_access_contested = 10, - arbiter_sram3_perf_event_access = 9, - arbiter_sram3_perf_event_access_contested = 8, - arbiter_sram4_perf_event_access = 7, - arbiter_sram4_perf_event_access_contested = 6, - arbiter_sram5_perf_event_access = 5, - arbiter_sram5_perf_event_access_contested = 4, - arbiter_fastperi_perf_event_access = 3, - arbiter_fastperi_perf_event_access_contested = 2, - arbiter_apb_perf_event_access = 1, - arbiter_apb_perf_event_access_contested = 0 -} bus_ctrl_perf_counter_t; - -typedef struct { - _REG_(BUSCTRL_PERFCTR0_OFFSET) // BUSCTRL_PERFCTR0 - // Bus fabric performance counter 0 - // 0x00ffffff [23:0] PERFCTR0 (0x000000) Busfabric saturating performance counter 0 + - io_rw_32 value; - - _REG_(BUSCTRL_PERFSEL0_OFFSET) // BUSCTRL_PERFSEL0 - // Bus fabric performance event select for PERFCTR0 - // 0x0000007f [6:0] PERFSEL0 (0x1f) Select an event for PERFCTR0 - io_rw_32 sel; -} bus_ctrl_perf_hw_t; - -typedef struct { - _REG_(BUSCTRL_BUS_PRIORITY_OFFSET) // BUSCTRL_BUS_PRIORITY - // Set the priority of each master for bus arbitration - // 0x00001000 [12] DMA_W (0) 0 - low priority, 1 - high priority - // 0x00000100 [8] DMA_R (0) 0 - low priority, 1 - high priority - // 0x00000010 [4] PROC1 (0) 0 - low priority, 1 - high priority - // 0x00000001 [0] PROC0 (0) 0 - low priority, 1 - high priority - io_rw_32 priority; - - _REG_(BUSCTRL_BUS_PRIORITY_ACK_OFFSET) // BUSCTRL_BUS_PRIORITY_ACK - // Bus priority acknowledge - // 0x00000001 [0] BUS_PRIORITY_ACK (0) Goes to 1 once all arbiters have registered the new... - io_ro_32 priority_ack; - - _REG_(BUSCTRL_PERFCTR_EN_OFFSET) // BUSCTRL_PERFCTR_EN - // Enable the performance counters - // 0x00000001 [0] PERFCTR_EN (0) - io_rw_32 perfctr_en; - - bus_ctrl_perf_hw_t counter[4]; -} busctrl_hw_t; - -#define busctrl_hw ((busctrl_hw_t *)BUSCTRL_BASE) -static_assert(sizeof (busctrl_hw_t) == 0x002c, ""); - -#endif // _HARDWARE_STRUCTS_BUSCTRL_H - diff --git a/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/clocks.h b/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/clocks.h deleted file mode 100644 index 2cdc1b824e..0000000000 --- a/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/clocks.h +++ /dev/null @@ -1,580 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _HARDWARE_STRUCTS_CLOCKS_H -#define _HARDWARE_STRUCTS_CLOCKS_H - -/** - * \file rp2350/clocks.h - */ - -#include "hardware/address_mapped.h" -#include "hardware/regs/clocks.h" - -// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_clocks -// -// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) -// _REG_(x) will link to the corresponding register in hardware/regs/clocks.h. -// -// Bit-field descriptions are of the form: -// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION - -/** \brief Clock numbers on RP2350 (used as typedef \ref clock_num_t) - * \ingroup hardware_clocks - */ -/// \tag::clkenum[] -typedef enum clock_num_rp2350 { - clk_gpout0 = 0, ///< Select CLK_GPOUT0 as clock source - clk_gpout1 = 1, ///< Select CLK_GPOUT1 as clock source - clk_gpout2 = 2, ///< Select CLK_GPOUT2 as clock source - clk_gpout3 = 3, ///< Select CLK_GPOUT3 as clock source - clk_ref = 4, ///< Select CLK_REF as clock source - clk_sys = 5, ///< Select CLK_SYS as clock source - clk_peri = 6, ///< Select CLK_PERI as clock source - clk_hstx = 7, ///< Select CLK_HSTX as clock source - clk_usb = 8, ///< Select CLK_USB as clock source - clk_adc = 9, ///< Select CLK_ADC as clock source - CLK_COUNT -} clock_num_t; -/// \end::clkenum[] - -/** \brief Clock destination numbers on RP2350 (used as typedef \ref clock_dest_num_t) - * \ingroup hardware_clocks - */ -typedef enum clock_dest_num_rp2350 { - CLK_DEST_SYS_CLOCKS = 0, ///< Select SYS_CLOCKS as clock destination - CLK_DEST_SYS_ACCESSCTRL = 1, ///< Select SYS_ACCESSCTRL as clock destination - CLK_DEST_ADC = 2, ///< Select ADC as clock destination - CLK_DEST_SYS_ADC = 3, ///< Select SYS_ADC as clock destination - CLK_DEST_SYS_BOOTRAM = 4, ///< Select SYS_BOOTRAM as clock destination - CLK_DEST_SYS_BUSCTRL = 5, ///< Select SYS_BUSCTRL as clock destination - CLK_DEST_SYS_BUSFABRIC = 6, ///< Select SYS_BUSFABRIC as clock destination - CLK_DEST_SYS_DMA = 7, ///< Select SYS_DMA as clock destination - CLK_DEST_SYS_GLITCH_DETECTOR = 8, ///< Select SYS_GLITCH_DETECTOR as clock destination - CLK_DEST_HSTX = 9, ///< Select HSTX as clock destination - CLK_DEST_SYS_HSTX = 10, ///< Select SYS_HSTX as clock destination - CLK_DEST_SYS_I2C0 = 11, ///< Select SYS_I2C0 as clock destination - CLK_DEST_SYS_I2C1 = 12, ///< Select SYS_I2C1 as clock destination - CLK_DEST_SYS_IO = 13, ///< Select SYS_IO as clock destination - CLK_DEST_SYS_JTAG = 14, ///< Select SYS_JTAG as clock destination - CLK_DEST_REF_OTP = 15, ///< Select REF_OTP as clock destination - CLK_DEST_SYS_OTP = 16, ///< Select SYS_OTP as clock destination - CLK_DEST_SYS_PADS = 17, ///< Select SYS_PADS as clock destination - CLK_DEST_SYS_PIO0 = 18, ///< Select SYS_PIO0 as clock destination - CLK_DEST_SYS_PIO1 = 19, ///< Select SYS_PIO1 as clock destination - CLK_DEST_SYS_PIO2 = 20, ///< Select SYS_PIO2 as clock destination - CLK_DEST_SYS_PLL_SYS = 21, ///< Select SYS_PLL_SYS as clock destination - CLK_DEST_SYS_PLL_USB = 22, ///< Select SYS_PLL_USB as clock destination - CLK_DEST_REF_POWMAN = 23, ///< Select REF_POWMAN as clock destination - CLK_DEST_SYS_POWMAN = 24, ///< Select SYS_POWMAN as clock destination - CLK_DEST_SYS_PWM = 25, ///< Select SYS_PWM as clock destination - CLK_DEST_SYS_RESETS = 26, ///< Select SYS_RESETS as clock destination - CLK_DEST_SYS_ROM = 27, ///< Select SYS_ROM as clock destination - CLK_DEST_SYS_ROSC = 28, ///< Select SYS_ROSC as clock destination - CLK_DEST_SYS_PSM = 29, ///< Select SYS_PSM as clock destination - CLK_DEST_SYS_SHA256 = 30, ///< Select SYS_SHA256 as clock destination - CLK_DEST_SYS_SIO = 31, ///< Select SYS_SIO as clock destination - CLK_DEST_PERI_SPI0 = 32, ///< Select PERI_SPI0 as clock destination - CLK_DEST_SYS_SPI0 = 33, ///< Select SYS_SPI0 as clock destination - CLK_DEST_PERI_SPI1 = 34, ///< Select PERI_SPI1 as clock destination - CLK_DEST_SYS_SPI1 = 35, ///< Select SYS_SPI1 as clock destination - CLK_DEST_SYS_SRAM0 = 36, ///< Select SYS_SRAM0 as clock destination - CLK_DEST_SYS_SRAM1 = 37, ///< Select SYS_SRAM1 as clock destination - CLK_DEST_SYS_SRAM2 = 38, ///< Select SYS_SRAM2 as clock destination - CLK_DEST_SYS_SRAM3 = 39, ///< Select SYS_SRAM3 as clock destination - CLK_DEST_SYS_SRAM4 = 40, ///< Select SYS_SRAM4 as clock destination - CLK_DEST_SYS_SRAM5 = 41, ///< Select SYS_SRAM5 as clock destination - CLK_DEST_SYS_SRAM6 = 42, ///< Select SYS_SRAM6 as clock destination - CLK_DEST_SYS_SRAM7 = 43, ///< Select SYS_SRAM7 as clock destination - CLK_DEST_SYS_SRAM8 = 44, ///< Select SYS_SRAM8 as clock destination - CLK_DEST_SYS_SRAM9 = 45, ///< Select SYS_SRAM9 as clock destination - CLK_DEST_SYS_SYSCFG = 46, ///< Select SYS_SYSCFG as clock destination - CLK_DEST_SYS_SYSINFO = 47, ///< Select SYS_SYSINFO as clock destination - CLK_DEST_SYS_TBMAN = 48, ///< Select SYS_TBMAN as clock destination - CLK_DEST_REF_TICKS = 49, ///< Select REF_TICKS as clock destination - CLK_DEST_SYS_TICKS = 50, ///< Select SYS_TICKS as clock destination - CLK_DEST_SYS_TIMER0 = 51, ///< Select SYS_TIMER0 as clock destination - CLK_DEST_SYS_TIMER1 = 52, ///< Select SYS_TIMER1 as clock destination - CLK_DEST_SYS_TRNG = 53, ///< Select SYS_TRNG as clock destination - CLK_DEST_PERI_UART0 = 54, ///< Select PERI_UART0 as clock destination - CLK_DEST_SYS_UART0 = 55, ///< Select SYS_UART0 as clock destination - CLK_DEST_PERI_UART1 = 56, ///< Select PERI_UART1 as clock destination - CLK_DEST_SYS_UART1 = 57, ///< Select SYS_UART1 as clock destination - CLK_DEST_SYS_USBCTRL = 58, ///< Select SYS_USBCTRL as clock destination - CLK_DEST_USB = 59, ///< Select USB as clock destination - CLK_DEST_SYS_WATCHDOG = 60, ///< Select SYS_WATCHDOG as clock destination - CLK_DEST_SYS_XIP = 61, ///< Select SYS_XIP as clock destination - CLK_DEST_SYS_XOSC = 62, ///< Select SYS_XOSC as clock destination - NUM_CLOCK_DESTINATIONS -} clock_dest_num_t; - -/// \tag::clock_hw[] -typedef struct { - _REG_(CLOCKS_CLK_GPOUT0_CTRL_OFFSET) // CLOCKS_CLK_GPOUT0_CTRL - // Clock control, can be changed on-the-fly (except for auxsrc) - // 0x10000000 [28] ENABLED (0) clock generator is enabled - // 0x00100000 [20] NUDGE (0) An edge on this signal shifts the phase of the output by... - // 0x00030000 [17:16] PHASE (0x0) This delays the enable signal by up to 3 cycles of the... - // 0x00001000 [12] DC50 (0) Enables duty cycle correction for odd divisors, can be... - // 0x00000800 [11] ENABLE (0) Starts and stops the clock generator cleanly - // 0x00000400 [10] KILL (0) Asynchronously kills the clock generator, enable must be... - // 0x000001e0 [8:5] AUXSRC (0x0) Selects the auxiliary clock source, will glitch when switching - io_rw_32 ctrl; - - _REG_(CLOCKS_CLK_GPOUT0_DIV_OFFSET) // CLOCKS_CLK_GPOUT0_DIV - // 0xffff0000 [31:16] INT (0x0001) Integer part of clock divisor, 0 -> max+1, can be... - // 0x0000ffff [15:0] FRAC (0x0000) Fractional component of the divisor, can be changed on-the-fly - io_rw_32 div; - - _REG_(CLOCKS_CLK_GPOUT0_SELECTED_OFFSET) // CLOCKS_CLK_GPOUT0_SELECTED - // Indicates which src is currently selected (one-hot) - // 0x00000001 [0] CLK_GPOUT0_SELECTED (1) This slice does not have a glitchless mux (only the... - io_ro_32 selected; -} clock_hw_t; -/// \end::clock_hw[] - -typedef struct { - _REG_(CLOCKS_CLK_SYS_RESUS_CTRL_OFFSET) // CLOCKS_CLK_SYS_RESUS_CTRL - // 0x00010000 [16] CLEAR (0) For clearing the resus after the fault that triggered it... - // 0x00001000 [12] FRCE (0) Force a resus, for test purposes only - // 0x00000100 [8] ENABLE (0) Enable resus - // 0x000000ff [7:0] TIMEOUT (0xff) This is expressed as a number of clk_ref cycles + - io_rw_32 ctrl; - - _REG_(CLOCKS_CLK_SYS_RESUS_STATUS_OFFSET) // CLOCKS_CLK_SYS_RESUS_STATUS - // 0x00000001 [0] RESUSSED (0) Clock has been resuscitated, correct the error then send... - io_ro_32 status; -} clock_resus_hw_t; - -typedef struct { - _REG_(CLOCKS_FC0_REF_KHZ_OFFSET) // CLOCKS_FC0_REF_KHZ - // Reference clock frequency in kHz - // 0x000fffff [19:0] FC0_REF_KHZ (0x00000) - io_rw_32 ref_khz; - - _REG_(CLOCKS_FC0_MIN_KHZ_OFFSET) // CLOCKS_FC0_MIN_KHZ - // Minimum pass frequency in kHz - // 0x01ffffff [24:0] FC0_MIN_KHZ (0x0000000) - io_rw_32 min_khz; - - _REG_(CLOCKS_FC0_MAX_KHZ_OFFSET) // CLOCKS_FC0_MAX_KHZ - // Maximum pass frequency in kHz - // 0x01ffffff [24:0] FC0_MAX_KHZ (0x1ffffff) - io_rw_32 max_khz; - - _REG_(CLOCKS_FC0_DELAY_OFFSET) // CLOCKS_FC0_DELAY - // Delays the start of frequency counting to allow the mux to settle + - // 0x00000007 [2:0] FC0_DELAY (0x1) - io_rw_32 delay; - - _REG_(CLOCKS_FC0_INTERVAL_OFFSET) // CLOCKS_FC0_INTERVAL - // The test interval is 0 - // 0x0000000f [3:0] FC0_INTERVAL (0x8) - io_rw_32 interval; - - _REG_(CLOCKS_FC0_SRC_OFFSET) // CLOCKS_FC0_SRC - // Clock sent to frequency counter, set to 0 when not required + - // 0x000000ff [7:0] FC0_SRC (0x00) - io_rw_32 src; - - _REG_(CLOCKS_FC0_STATUS_OFFSET) // CLOCKS_FC0_STATUS - // Frequency counter status - // 0x10000000 [28] DIED (0) Test clock stopped during test - // 0x01000000 [24] FAST (0) Test clock faster than expected, only valid when status_done=1 - // 0x00100000 [20] SLOW (0) Test clock slower than expected, only valid when status_done=1 - // 0x00010000 [16] FAIL (0) Test failed - // 0x00001000 [12] WAITING (0) Waiting for test clock to start - // 0x00000100 [8] RUNNING (0) Test running - // 0x00000010 [4] DONE (0) Test complete - // 0x00000001 [0] PASS (0) Test passed - io_ro_32 status; - - _REG_(CLOCKS_FC0_RESULT_OFFSET) // CLOCKS_FC0_RESULT - // Result of frequency measurement, only valid when status_done=1 - // 0x3fffffe0 [29:5] KHZ (0x0000000) - // 0x0000001f [4:0] FRAC (0x00) - io_ro_32 result; -} fc_hw_t; - -typedef struct { - clock_hw_t clk[10]; - - _REG_(CLOCKS_DFTCLK_XOSC_CTRL_OFFSET) // CLOCKS_DFTCLK_XOSC_CTRL - // 0x00000003 [1:0] SRC (0x0) - io_rw_32 dftclk_xosc_ctrl; - - _REG_(CLOCKS_DFTCLK_ROSC_CTRL_OFFSET) // CLOCKS_DFTCLK_ROSC_CTRL - // 0x00000003 [1:0] SRC (0x0) - io_rw_32 dftclk_rosc_ctrl; - - _REG_(CLOCKS_DFTCLK_LPOSC_CTRL_OFFSET) // CLOCKS_DFTCLK_LPOSC_CTRL - // 0x00000003 [1:0] SRC (0x0) - io_rw_32 dftclk_lposc_ctrl; - - clock_resus_hw_t resus; - - fc_hw_t fc0; - - union { - struct { - _REG_(CLOCKS_WAKE_EN0_OFFSET) // CLOCKS_WAKE_EN0 - // enable clock in wake mode - // 0x80000000 [31] CLK_SYS_SIOB (1) - // 0x40000000 [30] CLK_SYS_SHA256 (1) - // 0x20000000 [29] CLK_SYS_RSM (1) - // 0x10000000 [28] CLK_SYS_ROSC (1) - // 0x08000000 [27] CLK_SYS_ROM (1) - // 0x04000000 [26] CLK_SYS_RESETS (1) - // 0x02000000 [25] CLK_SYS_PWM (1) - // 0x01000000 [24] CLK_SYS_POWMAN (1) - // 0x00800000 [23] CLK_REF_POWMAN (1) - // 0x00400000 [22] CLK_SYS_PLL_USB (1) - // 0x00200000 [21] CLK_SYS_PLL_SYS (1) - // 0x00100000 [20] CLK_SYS_PIO2 (1) - // 0x00080000 [19] CLK_SYS_PIO1 (1) - // 0x00040000 [18] CLK_SYS_PIO0 (1) - // 0x00020000 [17] CLK_SYS_PADS (1) - // 0x00010000 [16] CLK_SYS_OTP (1) - // 0x00008000 [15] CLK_REF_OTP (1) - // 0x00004000 [14] CLK_SYS_JTAG (1) - // 0x00002000 [13] CLK_SYS_IO (1) - // 0x00001000 [12] CLK_SYS_I2C1 (1) - // 0x00000800 [11] CLK_SYS_I2C0 (1) - // 0x00000400 [10] CLK_SYS_HSTX (1) - // 0x00000200 [9] CLK_HSTX (1) - // 0x00000100 [8] CLK_SYS_GLITCH_DETECTOR (1) - // 0x00000080 [7] CLK_SYS_DMA (1) - // 0x00000040 [6] CLK_SYS_BUSFABRIC (1) - // 0x00000020 [5] CLK_SYS_BUSCTRL (1) - // 0x00000010 [4] CLK_SYS_BOOTRAM (1) - // 0x00000008 [3] CLK_SYS_ADC (1) - // 0x00000004 [2] CLK_ADC (1) - // 0x00000002 [1] CLK_SYS_ACCESSCTRL (1) - // 0x00000001 [0] CLK_SYS_CLOCKS (1) - io_rw_32 wake_en0; - - _REG_(CLOCKS_WAKE_EN1_OFFSET) // CLOCKS_WAKE_EN1 - // enable clock in wake mode - // 0x40000000 [30] CLK_SYS_XOSC (1) - // 0x20000000 [29] CLK_SYS_XIP (1) - // 0x10000000 [28] CLK_SYS_WATCHDOG (1) - // 0x08000000 [27] CLK_USB (1) - // 0x04000000 [26] CLK_SYS_USBCTRL (1) - // 0x02000000 [25] CLK_SYS_UART1 (1) - // 0x01000000 [24] CLK_PERI_UART1 (1) - // 0x00800000 [23] CLK_SYS_UART0 (1) - // 0x00400000 [22] CLK_PERI_UART0 (1) - // 0x00200000 [21] CLK_SYS_TRNG (1) - // 0x00100000 [20] CLK_SYS_TIMER1 (1) - // 0x00080000 [19] CLK_SYS_TIMER0 (1) - // 0x00040000 [18] CLK_SYS_TICKS (1) - // 0x00020000 [17] CLK_REF_TICKS (1) - // 0x00010000 [16] CLK_SYS_TBMAN (1) - // 0x00008000 [15] CLK_SYS_SYSINFO (1) - // 0x00004000 [14] CLK_SYS_SYSCFG (1) - // 0x00002000 [13] CLK_SYS_SRAM9 (1) - // 0x00001000 [12] CLK_SYS_SRAM8 (1) - // 0x00000800 [11] CLK_SYS_SRAM7 (1) - // 0x00000400 [10] CLK_SYS_SRAM6 (1) - // 0x00000200 [9] CLK_SYS_SRAM5 (1) - // 0x00000100 [8] CLK_SYS_SRAM4 (1) - // 0x00000080 [7] CLK_SYS_SRAM3 (1) - // 0x00000040 [6] CLK_SYS_SRAM2 (1) - // 0x00000020 [5] CLK_SYS_SRAM1 (1) - // 0x00000010 [4] CLK_SYS_SRAM0 (1) - // 0x00000008 [3] CLK_SYS_SPI1 (1) - // 0x00000004 [2] CLK_PERI_SPI1 (1) - // 0x00000002 [1] CLK_SYS_SPI0 (1) - // 0x00000001 [0] CLK_PERI_SPI0 (1) - io_rw_32 wake_en1; - }; - // (Description copied from array index 0 register CLOCKS_WAKE_EN0 applies similarly to other array indexes) - _REG_(CLOCKS_WAKE_EN0_OFFSET) // CLOCKS_WAKE_EN0 - // enable clock in wake mode - // 0x80000000 [31] CLK_SYS_SIO (1) - // 0x40000000 [30] CLK_SYS_SHA256 (1) - // 0x20000000 [29] CLK_SYS_PSM (1) - // 0x10000000 [28] CLK_SYS_ROSC (1) - // 0x08000000 [27] CLK_SYS_ROM (1) - // 0x04000000 [26] CLK_SYS_RESETS (1) - // 0x02000000 [25] CLK_SYS_PWM (1) - // 0x01000000 [24] CLK_SYS_POWMAN (1) - // 0x00800000 [23] CLK_REF_POWMAN (1) - // 0x00400000 [22] CLK_SYS_PLL_USB (1) - // 0x00200000 [21] CLK_SYS_PLL_SYS (1) - // 0x00100000 [20] CLK_SYS_PIO2 (1) - // 0x00080000 [19] CLK_SYS_PIO1 (1) - // 0x00040000 [18] CLK_SYS_PIO0 (1) - // 0x00020000 [17] CLK_SYS_PADS (1) - // 0x00010000 [16] CLK_SYS_OTP (1) - // 0x00008000 [15] CLK_REF_OTP (1) - // 0x00004000 [14] CLK_SYS_JTAG (1) - // 0x00002000 [13] CLK_SYS_IO (1) - // 0x00001000 [12] CLK_SYS_I2C1 (1) - // 0x00000800 [11] CLK_SYS_I2C0 (1) - // 0x00000400 [10] CLK_SYS_HSTX (1) - // 0x00000200 [9] CLK_HSTX (1) - // 0x00000100 [8] CLK_SYS_GLITCH_DETECTOR (1) - // 0x00000080 [7] CLK_SYS_DMA (1) - // 0x00000040 [6] CLK_SYS_BUSFABRIC (1) - // 0x00000020 [5] CLK_SYS_BUSCTRL (1) - // 0x00000010 [4] CLK_SYS_BOOTRAM (1) - // 0x00000008 [3] CLK_SYS_ADC (1) - // 0x00000004 [2] CLK_ADC (1) - // 0x00000002 [1] CLK_SYS_ACCESSCTRL (1) - // 0x00000001 [0] CLK_SYS_CLOCKS (1) - io_rw_32 wake_en[2]; - }; - - union { - struct { - _REG_(CLOCKS_SLEEP_EN0_OFFSET) // CLOCKS_SLEEP_EN0 - // enable clock in sleep mode - // 0x80000000 [31] CLK_SYS_SIOB (1) - // 0x40000000 [30] CLK_SYS_SHA256 (1) - // 0x20000000 [29] CLK_SYS_RSM (1) - // 0x10000000 [28] CLK_SYS_ROSC (1) - // 0x08000000 [27] CLK_SYS_ROM (1) - // 0x04000000 [26] CLK_SYS_RESETS (1) - // 0x02000000 [25] CLK_SYS_PWM (1) - // 0x01000000 [24] CLK_SYS_POWMAN (1) - // 0x00800000 [23] CLK_REF_POWMAN (1) - // 0x00400000 [22] CLK_SYS_PLL_USB (1) - // 0x00200000 [21] CLK_SYS_PLL_SYS (1) - // 0x00100000 [20] CLK_SYS_PIO2 (1) - // 0x00080000 [19] CLK_SYS_PIO1 (1) - // 0x00040000 [18] CLK_SYS_PIO0 (1) - // 0x00020000 [17] CLK_SYS_PADS (1) - // 0x00010000 [16] CLK_SYS_OTP (1) - // 0x00008000 [15] CLK_REF_OTP (1) - // 0x00004000 [14] CLK_SYS_JTAG (1) - // 0x00002000 [13] CLK_SYS_IO (1) - // 0x00001000 [12] CLK_SYS_I2C1 (1) - // 0x00000800 [11] CLK_SYS_I2C0 (1) - // 0x00000400 [10] CLK_SYS_HSTX (1) - // 0x00000200 [9] CLK_HSTX (1) - // 0x00000100 [8] CLK_SYS_GLITCH_DETECTOR (1) - // 0x00000080 [7] CLK_SYS_DMA (1) - // 0x00000040 [6] CLK_SYS_BUSFABRIC (1) - // 0x00000020 [5] CLK_SYS_BUSCTRL (1) - // 0x00000010 [4] CLK_SYS_BOOTRAM (1) - // 0x00000008 [3] CLK_SYS_ADC (1) - // 0x00000004 [2] CLK_ADC (1) - // 0x00000002 [1] CLK_SYS_ACCESSCTRL (1) - // 0x00000001 [0] CLK_SYS_CLOCKS (1) - io_rw_32 sleep_en0; - - _REG_(CLOCKS_SLEEP_EN1_OFFSET) // CLOCKS_SLEEP_EN1 - // enable clock in sleep mode - // 0x40000000 [30] CLK_SYS_XOSC (1) - // 0x20000000 [29] CLK_SYS_XIP (1) - // 0x10000000 [28] CLK_SYS_WATCHDOG (1) - // 0x08000000 [27] CLK_USB (1) - // 0x04000000 [26] CLK_SYS_USBCTRL (1) - // 0x02000000 [25] CLK_SYS_UART1 (1) - // 0x01000000 [24] CLK_PERI_UART1 (1) - // 0x00800000 [23] CLK_SYS_UART0 (1) - // 0x00400000 [22] CLK_PERI_UART0 (1) - // 0x00200000 [21] CLK_SYS_TRNG (1) - // 0x00100000 [20] CLK_SYS_TIMER1 (1) - // 0x00080000 [19] CLK_SYS_TIMER0 (1) - // 0x00040000 [18] CLK_SYS_TICKS (1) - // 0x00020000 [17] CLK_REF_TICKS (1) - // 0x00010000 [16] CLK_SYS_TBMAN (1) - // 0x00008000 [15] CLK_SYS_SYSINFO (1) - // 0x00004000 [14] CLK_SYS_SYSCFG (1) - // 0x00002000 [13] CLK_SYS_SRAM9 (1) - // 0x00001000 [12] CLK_SYS_SRAM8 (1) - // 0x00000800 [11] CLK_SYS_SRAM7 (1) - // 0x00000400 [10] CLK_SYS_SRAM6 (1) - // 0x00000200 [9] CLK_SYS_SRAM5 (1) - // 0x00000100 [8] CLK_SYS_SRAM4 (1) - // 0x00000080 [7] CLK_SYS_SRAM3 (1) - // 0x00000040 [6] CLK_SYS_SRAM2 (1) - // 0x00000020 [5] CLK_SYS_SRAM1 (1) - // 0x00000010 [4] CLK_SYS_SRAM0 (1) - // 0x00000008 [3] CLK_SYS_SPI1 (1) - // 0x00000004 [2] CLK_PERI_SPI1 (1) - // 0x00000002 [1] CLK_SYS_SPI0 (1) - // 0x00000001 [0] CLK_PERI_SPI0 (1) - io_rw_32 sleep_en1; - }; - // (Description copied from array index 0 register CLOCKS_SLEEP_EN0 applies similarly to other array indexes) - _REG_(CLOCKS_SLEEP_EN0_OFFSET) // CLOCKS_SLEEP_EN0 - // enable clock in sleep mode - // 0x80000000 [31] CLK_SYS_SIO (1) - // 0x40000000 [30] CLK_SYS_SHA256 (1) - // 0x20000000 [29] CLK_SYS_PSM (1) - // 0x10000000 [28] CLK_SYS_ROSC (1) - // 0x08000000 [27] CLK_SYS_ROM (1) - // 0x04000000 [26] CLK_SYS_RESETS (1) - // 0x02000000 [25] CLK_SYS_PWM (1) - // 0x01000000 [24] CLK_SYS_POWMAN (1) - // 0x00800000 [23] CLK_REF_POWMAN (1) - // 0x00400000 [22] CLK_SYS_PLL_USB (1) - // 0x00200000 [21] CLK_SYS_PLL_SYS (1) - // 0x00100000 [20] CLK_SYS_PIO2 (1) - // 0x00080000 [19] CLK_SYS_PIO1 (1) - // 0x00040000 [18] CLK_SYS_PIO0 (1) - // 0x00020000 [17] CLK_SYS_PADS (1) - // 0x00010000 [16] CLK_SYS_OTP (1) - // 0x00008000 [15] CLK_REF_OTP (1) - // 0x00004000 [14] CLK_SYS_JTAG (1) - // 0x00002000 [13] CLK_SYS_IO (1) - // 0x00001000 [12] CLK_SYS_I2C1 (1) - // 0x00000800 [11] CLK_SYS_I2C0 (1) - // 0x00000400 [10] CLK_SYS_HSTX (1) - // 0x00000200 [9] CLK_HSTX (1) - // 0x00000100 [8] CLK_SYS_GLITCH_DETECTOR (1) - // 0x00000080 [7] CLK_SYS_DMA (1) - // 0x00000040 [6] CLK_SYS_BUSFABRIC (1) - // 0x00000020 [5] CLK_SYS_BUSCTRL (1) - // 0x00000010 [4] CLK_SYS_BOOTRAM (1) - // 0x00000008 [3] CLK_SYS_ADC (1) - // 0x00000004 [2] CLK_ADC (1) - // 0x00000002 [1] CLK_SYS_ACCESSCTRL (1) - // 0x00000001 [0] CLK_SYS_CLOCKS (1) - io_rw_32 sleep_en[2]; - }; - - union { - struct { - _REG_(CLOCKS_ENABLED0_OFFSET) // CLOCKS_ENABLED0 - // indicates the state of the clock enable - // 0x80000000 [31] CLK_SYS_SIOB (0) - // 0x40000000 [30] CLK_SYS_SHA256 (0) - // 0x20000000 [29] CLK_SYS_RSM (0) - // 0x10000000 [28] CLK_SYS_ROSC (0) - // 0x08000000 [27] CLK_SYS_ROM (0) - // 0x04000000 [26] CLK_SYS_RESETS (0) - // 0x02000000 [25] CLK_SYS_PWM (0) - // 0x01000000 [24] CLK_SYS_POWMAN (0) - // 0x00800000 [23] CLK_REF_POWMAN (0) - // 0x00400000 [22] CLK_SYS_PLL_USB (0) - // 0x00200000 [21] CLK_SYS_PLL_SYS (0) - // 0x00100000 [20] CLK_SYS_PIO2 (0) - // 0x00080000 [19] CLK_SYS_PIO1 (0) - // 0x00040000 [18] CLK_SYS_PIO0 (0) - // 0x00020000 [17] CLK_SYS_PADS (0) - // 0x00010000 [16] CLK_SYS_OTP (0) - // 0x00008000 [15] CLK_REF_OTP (0) - // 0x00004000 [14] CLK_SYS_JTAG (0) - // 0x00002000 [13] CLK_SYS_IO (0) - // 0x00001000 [12] CLK_SYS_I2C1 (0) - // 0x00000800 [11] CLK_SYS_I2C0 (0) - // 0x00000400 [10] CLK_SYS_HSTX (0) - // 0x00000200 [9] CLK_HSTX (0) - // 0x00000100 [8] CLK_SYS_GLITCH_DETECTOR (0) - // 0x00000080 [7] CLK_SYS_DMA (0) - // 0x00000040 [6] CLK_SYS_BUSFABRIC (0) - // 0x00000020 [5] CLK_SYS_BUSCTRL (0) - // 0x00000010 [4] CLK_SYS_BOOTRAM (0) - // 0x00000008 [3] CLK_SYS_ADC (0) - // 0x00000004 [2] CLK_ADC (0) - // 0x00000002 [1] CLK_SYS_ACCESSCTRL (0) - // 0x00000001 [0] CLK_SYS_CLOCKS (0) - io_ro_32 enabled0; - - _REG_(CLOCKS_ENABLED1_OFFSET) // CLOCKS_ENABLED1 - // indicates the state of the clock enable - // 0x40000000 [30] CLK_SYS_XOSC (0) - // 0x20000000 [29] CLK_SYS_XIP (0) - // 0x10000000 [28] CLK_SYS_WATCHDOG (0) - // 0x08000000 [27] CLK_USB (0) - // 0x04000000 [26] CLK_SYS_USBCTRL (0) - // 0x02000000 [25] CLK_SYS_UART1 (0) - // 0x01000000 [24] CLK_PERI_UART1 (0) - // 0x00800000 [23] CLK_SYS_UART0 (0) - // 0x00400000 [22] CLK_PERI_UART0 (0) - // 0x00200000 [21] CLK_SYS_TRNG (0) - // 0x00100000 [20] CLK_SYS_TIMER1 (0) - // 0x00080000 [19] CLK_SYS_TIMER0 (0) - // 0x00040000 [18] CLK_SYS_TICKS (0) - // 0x00020000 [17] CLK_REF_TICKS (0) - // 0x00010000 [16] CLK_SYS_TBMAN (0) - // 0x00008000 [15] CLK_SYS_SYSINFO (0) - // 0x00004000 [14] CLK_SYS_SYSCFG (0) - // 0x00002000 [13] CLK_SYS_SRAM9 (0) - // 0x00001000 [12] CLK_SYS_SRAM8 (0) - // 0x00000800 [11] CLK_SYS_SRAM7 (0) - // 0x00000400 [10] CLK_SYS_SRAM6 (0) - // 0x00000200 [9] CLK_SYS_SRAM5 (0) - // 0x00000100 [8] CLK_SYS_SRAM4 (0) - // 0x00000080 [7] CLK_SYS_SRAM3 (0) - // 0x00000040 [6] CLK_SYS_SRAM2 (0) - // 0x00000020 [5] CLK_SYS_SRAM1 (0) - // 0x00000010 [4] CLK_SYS_SRAM0 (0) - // 0x00000008 [3] CLK_SYS_SPI1 (0) - // 0x00000004 [2] CLK_PERI_SPI1 (0) - // 0x00000002 [1] CLK_SYS_SPI0 (0) - // 0x00000001 [0] CLK_PERI_SPI0 (0) - io_ro_32 enabled1; - }; - // (Description copied from array index 0 register CLOCKS_ENABLED0 applies similarly to other array indexes) - _REG_(CLOCKS_ENABLED0_OFFSET) // CLOCKS_ENABLED0 - // indicates the state of the clock enable - // 0x80000000 [31] CLK_SYS_SIO (0) - // 0x40000000 [30] CLK_SYS_SHA256 (0) - // 0x20000000 [29] CLK_SYS_PSM (0) - // 0x10000000 [28] CLK_SYS_ROSC (0) - // 0x08000000 [27] CLK_SYS_ROM (0) - // 0x04000000 [26] CLK_SYS_RESETS (0) - // 0x02000000 [25] CLK_SYS_PWM (0) - // 0x01000000 [24] CLK_SYS_POWMAN (0) - // 0x00800000 [23] CLK_REF_POWMAN (0) - // 0x00400000 [22] CLK_SYS_PLL_USB (0) - // 0x00200000 [21] CLK_SYS_PLL_SYS (0) - // 0x00100000 [20] CLK_SYS_PIO2 (0) - // 0x00080000 [19] CLK_SYS_PIO1 (0) - // 0x00040000 [18] CLK_SYS_PIO0 (0) - // 0x00020000 [17] CLK_SYS_PADS (0) - // 0x00010000 [16] CLK_SYS_OTP (0) - // 0x00008000 [15] CLK_REF_OTP (0) - // 0x00004000 [14] CLK_SYS_JTAG (0) - // 0x00002000 [13] CLK_SYS_IO (0) - // 0x00001000 [12] CLK_SYS_I2C1 (0) - // 0x00000800 [11] CLK_SYS_I2C0 (0) - // 0x00000400 [10] CLK_SYS_HSTX (0) - // 0x00000200 [9] CLK_HSTX (0) - // 0x00000100 [8] CLK_SYS_GLITCH_DETECTOR (0) - // 0x00000080 [7] CLK_SYS_DMA (0) - // 0x00000040 [6] CLK_SYS_BUSFABRIC (0) - // 0x00000020 [5] CLK_SYS_BUSCTRL (0) - // 0x00000010 [4] CLK_SYS_BOOTRAM (0) - // 0x00000008 [3] CLK_SYS_ADC (0) - // 0x00000004 [2] CLK_ADC (0) - // 0x00000002 [1] CLK_SYS_ACCESSCTRL (0) - // 0x00000001 [0] CLK_SYS_CLOCKS (0) - io_ro_32 enabled[2]; - }; - - _REG_(CLOCKS_INTR_OFFSET) // CLOCKS_INTR - // Raw Interrupts - // 0x00000001 [0] CLK_SYS_RESUS (0) - io_ro_32 intr; - - _REG_(CLOCKS_INTE_OFFSET) // CLOCKS_INTE - // Interrupt Enable - // 0x00000001 [0] CLK_SYS_RESUS (0) - io_rw_32 inte; - - _REG_(CLOCKS_INTF_OFFSET) // CLOCKS_INTF - // Interrupt Force - // 0x00000001 [0] CLK_SYS_RESUS (0) - io_rw_32 intf; - - _REG_(CLOCKS_INTS_OFFSET) // CLOCKS_INTS - // Interrupt status after masking & forcing - // 0x00000001 [0] CLK_SYS_RESUS (0) - io_ro_32 ints; -} clocks_hw_t; - -#define clocks_hw ((clocks_hw_t *)CLOCKS_BASE) -static_assert(sizeof (clocks_hw_t) == 0x00d4, ""); - -#endif // _HARDWARE_STRUCTS_CLOCKS_H - diff --git a/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/coresight_trace.h b/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/coresight_trace.h deleted file mode 100644 index 61ffb06234..0000000000 --- a/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/coresight_trace.h +++ /dev/null @@ -1,43 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _HARDWARE_STRUCTS_CORESIGHT_TRACE_H -#define _HARDWARE_STRUCTS_CORESIGHT_TRACE_H - -/** - * \file rp2350/coresight_trace.h - */ - -#include "hardware/address_mapped.h" -#include "hardware/regs/coresight_trace.h" - -// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_coresight_trace -// -// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) -// _REG_(x) will link to the corresponding register in hardware/regs/coresight_trace.h. -// -// Bit-field descriptions are of the form: -// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION - -typedef struct { - _REG_(CORESIGHT_TRACE_CTRL_STATUS_OFFSET) // CORESIGHT_TRACE_CTRL_STATUS - // Control and status register - // 0x00000002 [1] TRACE_CAPTURE_FIFO_OVERFLOW (0) This status flag is set high when trace data has been... - // 0x00000001 [0] TRACE_CAPTURE_FIFO_FLUSH (1) Set to 1 to continuously hold the trace FIFO in a... - io_rw_32 ctrl_status; - - _REG_(CORESIGHT_TRACE_TRACE_CAPTURE_FIFO_OFFSET) // CORESIGHT_TRACE_TRACE_CAPTURE_FIFO - // FIFO for trace data captured from the TPIU - // 0xffffffff [31:0] RDATA (0x00000000) Read from an 8 x 32-bit FIFO containing trace data... - io_ro_32 trace_capture_fifo; -} coresight_trace_hw_t; - -#define coresight_trace_hw ((coresight_trace_hw_t *)CORESIGHT_TRACE_BASE) -static_assert(sizeof (coresight_trace_hw_t) == 0x0008, ""); - -#endif // _HARDWARE_STRUCTS_CORESIGHT_TRACE_H - diff --git a/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/dma.h b/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/dma.h deleted file mode 100644 index 6097a98440..0000000000 --- a/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/dma.h +++ /dev/null @@ -1,336 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _HARDWARE_STRUCTS_DMA_H -#define _HARDWARE_STRUCTS_DMA_H - -/** - * \file rp2350/dma.h - */ - -#include "hardware/address_mapped.h" -#include "hardware/regs/dma.h" -#include "hardware/structs/dma_debug.h" - -// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_dma -// -// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) -// _REG_(x) will link to the corresponding register in hardware/regs/dma.h. -// -// Bit-field descriptions are of the form: -// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION - -typedef struct { - _REG_(DMA_CH0_READ_ADDR_OFFSET) // DMA_CH0_READ_ADDR - // DMA Channel 0 Read Address pointer - // 0xffffffff [31:0] CH0_READ_ADDR (0x00000000) This register updates automatically each time a read completes - io_rw_32 read_addr; - - _REG_(DMA_CH0_WRITE_ADDR_OFFSET) // DMA_CH0_WRITE_ADDR - // DMA Channel 0 Write Address pointer - // 0xffffffff [31:0] CH0_WRITE_ADDR (0x00000000) This register updates automatically each time a write completes - io_rw_32 write_addr; - - _REG_(DMA_CH0_TRANS_COUNT_OFFSET) // DMA_CH0_TRANS_COUNT - // DMA Channel 0 Transfer Count - // 0xf0000000 [31:28] MODE (0x0) When MODE is 0x0, the transfer count decrements with... - // 0x0fffffff [27:0] COUNT (0x0000000) 28-bit transfer count (256 million transfers maximum) - io_rw_32 transfer_count; - - _REG_(DMA_CH0_CTRL_TRIG_OFFSET) // DMA_CH0_CTRL_TRIG - // DMA Channel 0 Control and Status - // 0x80000000 [31] AHB_ERROR (0) Logical OR of the READ_ERROR and WRITE_ERROR flags - // 0x40000000 [30] READ_ERROR (0) If 1, the channel received a read bus error - // 0x20000000 [29] WRITE_ERROR (0) If 1, the channel received a write bus error - // 0x04000000 [26] BUSY (0) This flag goes high when the channel starts a new... - // 0x02000000 [25] SNIFF_EN (0) If 1, this channel's data transfers are visible to the... - // 0x01000000 [24] BSWAP (0) Apply byte-swap transformation to DMA data - // 0x00800000 [23] IRQ_QUIET (0) In QUIET mode, the channel does not generate IRQs at the... - // 0x007e0000 [22:17] TREQ_SEL (0x00) Select a Transfer Request signal - // 0x0001e000 [16:13] CHAIN_TO (0x0) When this channel completes, it will trigger the channel... - // 0x00001000 [12] RING_SEL (0) Select whether RING_SIZE applies to read or write addresses - // 0x00000f00 [11:8] RING_SIZE (0x0) Size of address wrap region - // 0x00000080 [7] INCR_WRITE_REV (0) If 1, and INCR_WRITE is 1, the write address is... - // 0x00000040 [6] INCR_WRITE (0) If 1, the write address increments with each transfer - // 0x00000020 [5] INCR_READ_REV (0) If 1, and INCR_READ is 1, the read address is... - // 0x00000010 [4] INCR_READ (0) If 1, the read address increments with each transfer - // 0x0000000c [3:2] DATA_SIZE (0x0) Set the size of each bus transfer (byte/halfword/word) - // 0x00000002 [1] HIGH_PRIORITY (0) HIGH_PRIORITY gives a channel preferential treatment in... - // 0x00000001 [0] EN (0) DMA Channel Enable - io_rw_32 ctrl_trig; - - _REG_(DMA_CH0_AL1_CTRL_OFFSET) // DMA_CH0_AL1_CTRL - // Alias for channel 0 CTRL register - // 0xffffffff [31:0] CH0_AL1_CTRL (-) - io_rw_32 al1_ctrl; - - _REG_(DMA_CH0_AL1_READ_ADDR_OFFSET) // DMA_CH0_AL1_READ_ADDR - // Alias for channel 0 READ_ADDR register - // 0xffffffff [31:0] CH0_AL1_READ_ADDR (-) - io_rw_32 al1_read_addr; - - _REG_(DMA_CH0_AL1_WRITE_ADDR_OFFSET) // DMA_CH0_AL1_WRITE_ADDR - // Alias for channel 0 WRITE_ADDR register - // 0xffffffff [31:0] CH0_AL1_WRITE_ADDR (-) - io_rw_32 al1_write_addr; - - _REG_(DMA_CH0_AL1_TRANS_COUNT_TRIG_OFFSET) // DMA_CH0_AL1_TRANS_COUNT_TRIG - // Alias for channel 0 TRANS_COUNT register + - // 0xffffffff [31:0] CH0_AL1_TRANS_COUNT_TRIG (-) - io_rw_32 al1_transfer_count_trig; - - _REG_(DMA_CH0_AL2_CTRL_OFFSET) // DMA_CH0_AL2_CTRL - // Alias for channel 0 CTRL register - // 0xffffffff [31:0] CH0_AL2_CTRL (-) - io_rw_32 al2_ctrl; - - _REG_(DMA_CH0_AL2_TRANS_COUNT_OFFSET) // DMA_CH0_AL2_TRANS_COUNT - // Alias for channel 0 TRANS_COUNT register - // 0xffffffff [31:0] CH0_AL2_TRANS_COUNT (-) - io_rw_32 al2_transfer_count; - - _REG_(DMA_CH0_AL2_READ_ADDR_OFFSET) // DMA_CH0_AL2_READ_ADDR - // Alias for channel 0 READ_ADDR register - // 0xffffffff [31:0] CH0_AL2_READ_ADDR (-) - io_rw_32 al2_read_addr; - - _REG_(DMA_CH0_AL2_WRITE_ADDR_TRIG_OFFSET) // DMA_CH0_AL2_WRITE_ADDR_TRIG - // Alias for channel 0 WRITE_ADDR register + - // 0xffffffff [31:0] CH0_AL2_WRITE_ADDR_TRIG (-) - io_rw_32 al2_write_addr_trig; - - _REG_(DMA_CH0_AL3_CTRL_OFFSET) // DMA_CH0_AL3_CTRL - // Alias for channel 0 CTRL register - // 0xffffffff [31:0] CH0_AL3_CTRL (-) - io_rw_32 al3_ctrl; - - _REG_(DMA_CH0_AL3_WRITE_ADDR_OFFSET) // DMA_CH0_AL3_WRITE_ADDR - // Alias for channel 0 WRITE_ADDR register - // 0xffffffff [31:0] CH0_AL3_WRITE_ADDR (-) - io_rw_32 al3_write_addr; - - _REG_(DMA_CH0_AL3_TRANS_COUNT_OFFSET) // DMA_CH0_AL3_TRANS_COUNT - // Alias for channel 0 TRANS_COUNT register - // 0xffffffff [31:0] CH0_AL3_TRANS_COUNT (-) - io_rw_32 al3_transfer_count; - - _REG_(DMA_CH0_AL3_READ_ADDR_TRIG_OFFSET) // DMA_CH0_AL3_READ_ADDR_TRIG - // Alias for channel 0 READ_ADDR register + - // 0xffffffff [31:0] CH0_AL3_READ_ADDR_TRIG (-) - io_rw_32 al3_read_addr_trig; -} dma_channel_hw_t; - -typedef struct { - _REG_(DMA_MPU_BAR0_OFFSET) // DMA_MPU_BAR0 - // Base address register for MPU region 0 - // 0xffffffe0 [31:5] ADDR (0x0000000) This MPU region matches addresses where addr[31:5] (the... - io_rw_32 bar; - - _REG_(DMA_MPU_LAR0_OFFSET) // DMA_MPU_LAR0 - // Limit address register for MPU region 0 - // 0xffffffe0 [31:5] ADDR (0x0000000) Limit address bits 31:5 - // 0x00000004 [2] S (0) Determines the Secure/Non-secure (=1/0) status of... - // 0x00000002 [1] P (0) Determines the Privileged/Unprivileged (=1/0) status of... - // 0x00000001 [0] EN (0) Region enable - io_rw_32 lar; -} dma_mpu_region_hw_t; - -typedef struct { - _REG_(DMA_INTR_OFFSET) // DMA_INTR - // Interrupt Status (raw) - // 0x0000ffff [15:0] INTR (0x0000) Raw interrupt status for DMA Channels 0 - io_rw_32 intr; - - _REG_(DMA_INTE0_OFFSET) // DMA_INTE0 - // Interrupt Enables for IRQ 0 - // 0x0000ffff [15:0] INTE0 (0x0000) Set bit n to pass interrupts from channel n to DMA IRQ 0 - io_rw_32 inte; - - _REG_(DMA_INTF0_OFFSET) // DMA_INTF0 - // Force Interrupts - // 0x0000ffff [15:0] INTF0 (0x0000) Write 1s to force the corresponding bits in INTS0 - io_rw_32 intf; - - _REG_(DMA_INTS0_OFFSET) // DMA_INTS0 - // Interrupt Status for IRQ 0 - // 0x0000ffff [15:0] INTS0 (0x0000) Indicates active channel interrupt requests which are... - io_rw_32 ints; -} dma_irq_ctrl_hw_t; - -typedef struct { - dma_channel_hw_t ch[16]; - - union { - struct { - _REG_(DMA_INTR_OFFSET) // DMA_INTR - // Interrupt Status (raw) - // 0x0000ffff [15:0] INTR (0x0000) Raw interrupt status for DMA Channels 0 - io_rw_32 intr; - - _REG_(DMA_INTE0_OFFSET) // DMA_INTE0 - // Interrupt Enables for IRQ 0 - // 0x0000ffff [15:0] INTE0 (0x0000) Set bit n to pass interrupts from channel n to DMA IRQ 0 - io_rw_32 inte0; - - _REG_(DMA_INTF0_OFFSET) // DMA_INTF0 - // Force Interrupts - // 0x0000ffff [15:0] INTF0 (0x0000) Write 1s to force the corresponding bits in INTE0 - io_rw_32 intf0; - - _REG_(DMA_INTS0_OFFSET) // DMA_INTS0 - // Interrupt Status for IRQ 0 - // 0x0000ffff [15:0] INTS0 (0x0000) Indicates active channel interrupt requests which are... - io_rw_32 ints0; - - uint32_t __pad0; - - _REG_(DMA_INTE1_OFFSET) // DMA_INTE1 - // Interrupt Enables for IRQ 1 - // 0x0000ffff [15:0] INTE1 (0x0000) Set bit n to pass interrupts from channel n to DMA IRQ 1 - io_rw_32 inte1; - - _REG_(DMA_INTF1_OFFSET) // DMA_INTF1 - // Force Interrupts for IRQ 1 - // 0x0000ffff [15:0] INTF1 (0x0000) Write 1s to force the corresponding bits in INTF1 - io_rw_32 intf1; - - _REG_(DMA_INTS1_OFFSET) // DMA_INTS1 - // Interrupt Status (masked) for IRQ 1 - // 0x0000ffff [15:0] INTS1 (0x0000) Indicates active channel interrupt requests which are... - io_rw_32 ints1; - - uint32_t __pad1; - - _REG_(DMA_INTE2_OFFSET) // DMA_INTE2 - // Interrupt Enables for IRQ 2 - // 0x0000ffff [15:0] INTE2 (0x0000) Set bit n to pass interrupts from channel n to DMA IRQ 2 - io_rw_32 inte2; - - _REG_(DMA_INTF2_OFFSET) // DMA_INTF2 - // Force Interrupts for IRQ 2 - // 0x0000ffff [15:0] INTF2 (0x0000) Set bit n to pass interrupts from channel n to DMA IRQ 2 - io_rw_32 intf2; - - _REG_(DMA_INTS2_OFFSET) // DMA_INTS2 - // Interrupt Status (masked) for IRQ 2 - // 0x0000ffff [15:0] INTS2 (0x0000) Set bit n to pass interrupts from channel n to DMA IRQ 2 - io_rw_32 ints2; - - uint32_t __pad2; - - _REG_(DMA_INTE3_OFFSET) // DMA_INTE3 - // Interrupt Enables for IRQ 3 - // 0x0000ffff [15:0] INTE3 (0x0000) Set bit n to pass interrupts from channel n to DMA IRQ 3 - io_rw_32 inte3; - - _REG_(DMA_INTF3_OFFSET) // DMA_INTF3 - // Force Interrupts for IRQ 3 - // 0x0000ffff [15:0] INTF3 (0x0000) Set bit n to pass interrupts from channel n to DMA IRQ 3 - io_rw_32 intf3; - - _REG_(DMA_INTS3_OFFSET) // DMA_INTS3 - // Interrupt Status (masked) for IRQ 3 - // 0x0000ffff [15:0] INTS3 (0x0000) Set bit n to pass interrupts from channel n to DMA IRQ 3 - io_rw_32 ints3; - }; - dma_irq_ctrl_hw_t irq_ctrl[4]; - }; - - // (Description copied from array index 0 register DMA_TIMER0 applies similarly to other array indexes) - _REG_(DMA_TIMER0_OFFSET) // DMA_TIMER0 - // Pacing timer (generate periodic TREQs) - // 0xffff0000 [31:16] X (0x0000) Pacing Timer Dividend - // 0x0000ffff [15:0] Y (0x0000) Pacing Timer Divisor - io_rw_32 timer[4]; - - _REG_(DMA_MULTI_CHAN_TRIGGER_OFFSET) // DMA_MULTI_CHAN_TRIGGER - // Trigger one or more channels simultaneously - // 0x0000ffff [15:0] MULTI_CHAN_TRIGGER (0x0000) Each bit in this register corresponds to a DMA channel - io_wo_32 multi_channel_trigger; - - _REG_(DMA_SNIFF_CTRL_OFFSET) // DMA_SNIFF_CTRL - // Sniffer Control - // 0x00000800 [11] OUT_INV (0) If set, the result appears inverted (bitwise complement)... - // 0x00000400 [10] OUT_REV (0) If set, the result appears bit-reversed when read - // 0x00000200 [9] BSWAP (0) Locally perform a byte reverse on the sniffed data,... - // 0x000001e0 [8:5] CALC (0x0) - // 0x0000001e [4:1] DMACH (0x0) DMA channel for Sniffer to observe - // 0x00000001 [0] EN (0) Enable sniffer - io_rw_32 sniff_ctrl; - - _REG_(DMA_SNIFF_DATA_OFFSET) // DMA_SNIFF_DATA - // Data accumulator for sniff hardware - // 0xffffffff [31:0] SNIFF_DATA (0x00000000) Write an initial seed value here before starting a DMA... - io_rw_32 sniff_data; - - uint32_t _pad0; - - _REG_(DMA_FIFO_LEVELS_OFFSET) // DMA_FIFO_LEVELS - // Debug RAF, WAF, TDF levels - // 0x00ff0000 [23:16] RAF_LVL (0x00) Current Read-Address-FIFO fill level - // 0x0000ff00 [15:8] WAF_LVL (0x00) Current Write-Address-FIFO fill level - // 0x000000ff [7:0] TDF_LVL (0x00) Current Transfer-Data-FIFO fill level - io_ro_32 fifo_levels; - - _REG_(DMA_CHAN_ABORT_OFFSET) // DMA_CHAN_ABORT - // Abort an in-progress transfer sequence on one or more channels - // 0x0000ffff [15:0] CHAN_ABORT (0x0000) Each bit corresponds to a channel - io_wo_32 abort; - - _REG_(DMA_N_CHANNELS_OFFSET) // DMA_N_CHANNELS - // The number of channels this DMA instance is equipped with - // 0x0000001f [4:0] N_CHANNELS (-) - io_ro_32 n_channels; - - uint32_t _pad1[5]; - - // (Description copied from array index 0 register DMA_SECCFG_CH0 applies similarly to other array indexes) - _REG_(DMA_SECCFG_CH0_OFFSET) // DMA_SECCFG_CH0 - // Security level configuration for channel 0. - // 0x00000004 [2] LOCK (0) LOCK is 0 at reset, and is set to 1 automatically upon a... - // 0x00000002 [1] S (1) Secure channel - // 0x00000001 [0] P (1) Privileged channel - io_rw_32 seccfg_ch[16]; - - // (Description copied from array index 0 register DMA_SECCFG_IRQ0 applies similarly to other array indexes) - _REG_(DMA_SECCFG_IRQ0_OFFSET) // DMA_SECCFG_IRQ0 - // Security configuration for IRQ 0 - // 0x00000002 [1] S (1) Secure IRQ - // 0x00000001 [0] P (1) Privileged IRQ - io_rw_32 seccfg_irq[4]; - - _REG_(DMA_SECCFG_MISC_OFFSET) // DMA_SECCFG_MISC - // Miscellaneous security configuration - // 0x00000200 [9] TIMER3_S (1) If 1, the TIMER3 register is only accessible from a... - // 0x00000100 [8] TIMER3_P (1) If 1, the TIMER3 register is only accessible from a... - // 0x00000080 [7] TIMER2_S (1) If 1, the TIMER2 register is only accessible from a... - // 0x00000040 [6] TIMER2_P (1) If 1, the TIMER2 register is only accessible from a... - // 0x00000020 [5] TIMER1_S (1) If 1, the TIMER1 register is only accessible from a... - // 0x00000010 [4] TIMER1_P (1) If 1, the TIMER1 register is only accessible from a... - // 0x00000008 [3] TIMER0_S (1) If 1, the TIMER0 register is only accessible from a... - // 0x00000004 [2] TIMER0_P (1) If 1, the TIMER0 register is only accessible from a... - // 0x00000002 [1] SNIFF_S (1) If 1, the sniffer can see data transfers from Secure... - // 0x00000001 [0] SNIFF_P (1) If 1, the sniffer can see data transfers from Privileged... - io_rw_32 seccfg_misc; - - uint32_t _pad2[11]; - - _REG_(DMA_MPU_CTRL_OFFSET) // DMA_MPU_CTRL - // Control register for DMA MPU - // 0x00000008 [3] NS_HIDE_ADDR (0) By default, when a region's S bit is clear,... - // 0x00000004 [2] S (0) Determine whether an address not covered by an active... - // 0x00000002 [1] P (0) Determine whether an address not covered by an active... - io_rw_32 mpu_ctrl; - - dma_mpu_region_hw_t mpu_region[8]; -} dma_hw_t; - -#define dma_hw ((dma_hw_t *)DMA_BASE) -static_assert(sizeof (dma_hw_t) == 0x0544, ""); - -#endif // _HARDWARE_STRUCTS_DMA_H - diff --git a/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/dma_debug.h b/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/dma_debug.h deleted file mode 100644 index 73c8bf43e0..0000000000 --- a/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/dma_debug.h +++ /dev/null @@ -1,47 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _HARDWARE_STRUCTS_DMA_DEBUG_H -#define _HARDWARE_STRUCTS_DMA_DEBUG_H - -/** - * \file rp2350/dma_debug.h - */ - -#include "hardware/address_mapped.h" -#include "hardware/regs/dma.h" - -// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_dma -// -// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) -// _REG_(x) will link to the corresponding register in hardware/regs/dma.h. -// -// Bit-field descriptions are of the form: -// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION - -typedef struct { - _REG_(DMA_CH0_DBG_CTDREQ_OFFSET) // DMA_CH0_DBG_CTDREQ - // Read: get channel DREQ counter (i - // 0x0000003f [5:0] CH0_DBG_CTDREQ (0x00) - io_rw_32 dbg_ctdreq; - - _REG_(DMA_CH0_DBG_TCR_OFFSET) // DMA_CH0_DBG_TCR - // Read to get channel TRANS_COUNT reload value, i - // 0xffffffff [31:0] CH0_DBG_TCR (0x00000000) - io_ro_32 dbg_tcr; - - uint32_t _pad0[14]; -} dma_debug_channel_hw_t; - -typedef struct { - dma_debug_channel_hw_t ch[16]; -} dma_debug_hw_t; - -#define dma_debug_hw ((dma_debug_hw_t *)(DMA_BASE + DMA_CH0_DBG_CTDREQ_OFFSET)) - -#endif // _HARDWARE_STRUCTS_DMA_DEBUG_H - diff --git a/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/glitch_detector.h b/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/glitch_detector.h deleted file mode 100644 index f25ebb23a1..0000000000 --- a/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/glitch_detector.h +++ /dev/null @@ -1,71 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _HARDWARE_STRUCTS_GLITCH_DETECTOR_H -#define _HARDWARE_STRUCTS_GLITCH_DETECTOR_H - -/** - * \file rp2350/glitch_detector.h - */ - -#include "hardware/address_mapped.h" -#include "hardware/regs/glitch_detector.h" - -// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_glitch_detector -// -// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) -// _REG_(x) will link to the corresponding register in hardware/regs/glitch_detector.h. -// -// Bit-field descriptions are of the form: -// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION - -typedef struct { - _REG_(GLITCH_DETECTOR_ARM_OFFSET) // GLITCH_DETECTOR_ARM - // Forcibly arm the glitch detectors, if they are not already armed by OTP - // 0x0000ffff [15:0] ARM (0x5bad) - io_rw_32 arm; - - _REG_(GLITCH_DETECTOR_DISARM_OFFSET) // GLITCH_DETECTOR_DISARM - // 0x0000ffff [15:0] DISARM (0x0000) Forcibly disarm the glitch detectors, if they are armed by OTP - io_rw_32 disarm; - - _REG_(GLITCH_DETECTOR_SENSITIVITY_OFFSET) // GLITCH_DETECTOR_SENSITIVITY - // Adjust the sensitivity of glitch detectors to values other than their OTP-provided defaults - // 0xff000000 [31:24] DEFAULT (0x00) - // 0x0000c000 [15:14] DET3_INV (0x0) Must be the inverse of DET3, else the default value is used - // 0x00003000 [13:12] DET2_INV (0x0) Must be the inverse of DET2, else the default value is used - // 0x00000c00 [11:10] DET1_INV (0x0) Must be the inverse of DET1, else the default value is used - // 0x00000300 [9:8] DET0_INV (0x0) Must be the inverse of DET0, else the default value is used - // 0x000000c0 [7:6] DET3 (0x0) Set sensitivity for detector 3 - // 0x00000030 [5:4] DET2 (0x0) Set sensitivity for detector 2 - // 0x0000000c [3:2] DET1 (0x0) Set sensitivity for detector 1 - // 0x00000003 [1:0] DET0 (0x0) Set sensitivity for detector 0 - io_rw_32 sensitivity; - - _REG_(GLITCH_DETECTOR_LOCK_OFFSET) // GLITCH_DETECTOR_LOCK - // 0x000000ff [7:0] LOCK (0x00) Write any nonzero value to disable writes to ARM,... - io_rw_32 lock; - - _REG_(GLITCH_DETECTOR_TRIG_STATUS_OFFSET) // GLITCH_DETECTOR_TRIG_STATUS - // Set when a detector output triggers - // 0x00000008 [3] DET3 (0) - // 0x00000004 [2] DET2 (0) - // 0x00000002 [1] DET1 (0) - // 0x00000001 [0] DET0 (0) - io_rw_32 trig_status; - - _REG_(GLITCH_DETECTOR_TRIG_FORCE_OFFSET) // GLITCH_DETECTOR_TRIG_FORCE - // Simulate the firing of one or more detectors - // 0x0000000f [3:0] TRIG_FORCE (0x0) - io_wo_32 trig_force; -} glitch_detector_hw_t; - -#define glitch_detector_hw ((glitch_detector_hw_t *)GLITCH_DETECTOR_BASE) -static_assert(sizeof (glitch_detector_hw_t) == 0x0018, ""); - -#endif // _HARDWARE_STRUCTS_GLITCH_DETECTOR_H - diff --git a/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/hstx_ctrl.h b/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/hstx_ctrl.h deleted file mode 100644 index 735ecee7e9..0000000000 --- a/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/hstx_ctrl.h +++ /dev/null @@ -1,70 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _HARDWARE_STRUCTS_HSTX_CTRL_H -#define _HARDWARE_STRUCTS_HSTX_CTRL_H - -/** - * \file rp2350/hstx_ctrl.h - */ - -#include "hardware/address_mapped.h" -#include "hardware/regs/hstx_ctrl.h" - -// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_hstx_ctrl -// -// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) -// _REG_(x) will link to the corresponding register in hardware/regs/hstx_ctrl.h. -// -// Bit-field descriptions are of the form: -// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION - -typedef struct { - _REG_(HSTX_CTRL_CSR_OFFSET) // HSTX_CTRL_CSR - // 0xf0000000 [31:28] CLKDIV (0x1) Clock period of the generated clock, measured in HSTX... - // 0x0f000000 [27:24] CLKPHASE (0x0) Set the initial phase of the generated clock - // 0x001f0000 [20:16] N_SHIFTS (0x05) Number of times to shift the shift register before... - // 0x00001f00 [12:8] SHIFT (0x06) How many bits to right-rotate the shift register by each cycle - // 0x00000060 [6:5] COUPLED_SEL (0x0) Select which PIO to use for coupled mode operation - // 0x00000010 [4] COUPLED_MODE (0) Enable the PIO-to-HSTX 1:1 connection - // 0x00000002 [1] EXPAND_EN (0) Enable the command expander - // 0x00000001 [0] EN (0) When EN is 1, the HSTX will shift out data as it appears... - io_rw_32 csr; - - // (Description copied from array index 0 register HSTX_CTRL_BIT0 applies similarly to other array indexes) - _REG_(HSTX_CTRL_BIT0_OFFSET) // HSTX_CTRL_BIT0 - // Data control register for output bit 0 - // 0x00020000 [17] CLK (0) Connect this output to the generated clock, rather than... - // 0x00010000 [16] INV (0) Invert this data output (logical NOT) - // 0x00001f00 [12:8] SEL_N (0x00) Shift register data bit select for the second half of... - // 0x0000001f [4:0] SEL_P (0x00) Shift register data bit select for the first half of the... - io_rw_32 bit[8]; - - _REG_(HSTX_CTRL_EXPAND_SHIFT_OFFSET) // HSTX_CTRL_EXPAND_SHIFT - // Configure the optional shifter inside the command expander - // 0x1f000000 [28:24] ENC_N_SHIFTS (0x01) Number of times to consume from the shift register... - // 0x001f0000 [20:16] ENC_SHIFT (0x00) How many bits to right-rotate the shift register by each... - // 0x00001f00 [12:8] RAW_N_SHIFTS (0x01) Number of times to consume from the shift register... - // 0x0000001f [4:0] RAW_SHIFT (0x00) How many bits to right-rotate the shift register by each... - io_rw_32 expand_shift; - - _REG_(HSTX_CTRL_EXPAND_TMDS_OFFSET) // HSTX_CTRL_EXPAND_TMDS - // Configure the optional TMDS encoder inside the command expander - // 0x00e00000 [23:21] L2_NBITS (0x0) Number of valid data bits for the lane 2 TMDS encoder,... - // 0x001f0000 [20:16] L2_ROT (0x00) Right-rotate applied to the current shifter data before... - // 0x0000e000 [15:13] L1_NBITS (0x0) Number of valid data bits for the lane 1 TMDS encoder,... - // 0x00001f00 [12:8] L1_ROT (0x00) Right-rotate applied to the current shifter data before... - // 0x000000e0 [7:5] L0_NBITS (0x0) Number of valid data bits for the lane 0 TMDS encoder,... - // 0x0000001f [4:0] L0_ROT (0x00) Right-rotate applied to the current shifter data before... - io_rw_32 expand_tmds; -} hstx_ctrl_hw_t; - -#define hstx_ctrl_hw ((hstx_ctrl_hw_t *)HSTX_CTRL_BASE) -static_assert(sizeof (hstx_ctrl_hw_t) == 0x002c, ""); - -#endif // _HARDWARE_STRUCTS_HSTX_CTRL_H - diff --git a/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/hstx_fifo.h b/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/hstx_fifo.h deleted file mode 100644 index a8399fad36..0000000000 --- a/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/hstx_fifo.h +++ /dev/null @@ -1,45 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _HARDWARE_STRUCTS_HSTX_FIFO_H -#define _HARDWARE_STRUCTS_HSTX_FIFO_H - -/** - * \file rp2350/hstx_fifo.h - */ - -#include "hardware/address_mapped.h" -#include "hardware/regs/hstx_fifo.h" - -// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_hstx_fifo -// -// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) -// _REG_(x) will link to the corresponding register in hardware/regs/hstx_fifo.h. -// -// Bit-field descriptions are of the form: -// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION - -typedef struct { - _REG_(HSTX_FIFO_STAT_OFFSET) // HSTX_FIFO_STAT - // FIFO status - // 0x00000400 [10] WOF (0) FIFO was written when full - // 0x00000200 [9] EMPTY (-) - // 0x00000100 [8] FULL (-) - // 0x000000ff [7:0] LEVEL (0x00) - io_rw_32 stat; - - _REG_(HSTX_FIFO_FIFO_OFFSET) // HSTX_FIFO_FIFO - // Write access to FIFO - // 0xffffffff [31:0] FIFO (0x00000000) - io_wo_32 fifo; -} hstx_fifo_hw_t; - -#define hstx_fifo_hw ((hstx_fifo_hw_t *)HSTX_FIFO_BASE) -static_assert(sizeof (hstx_fifo_hw_t) == 0x0008, ""); - -#endif // _HARDWARE_STRUCTS_HSTX_FIFO_H - diff --git a/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/i2c.h b/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/i2c.h deleted file mode 100644 index 7cd990dbfa..0000000000 --- a/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/i2c.h +++ /dev/null @@ -1,338 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _HARDWARE_STRUCTS_I2C_H -#define _HARDWARE_STRUCTS_I2C_H - -/** - * \file rp2350/i2c.h - */ - -#include "hardware/address_mapped.h" -#include "hardware/regs/i2c.h" - -// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_i2c -// -// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) -// _REG_(x) will link to the corresponding register in hardware/regs/i2c.h. -// -// Bit-field descriptions are of the form: -// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION - -typedef struct { - _REG_(I2C_IC_CON_OFFSET) // I2C_IC_CON - // I2C Control Register - // 0x00000400 [10] STOP_DET_IF_MASTER_ACTIVE (0) Master issues the STOP_DET interrupt irrespective of... - // 0x00000200 [9] RX_FIFO_FULL_HLD_CTRL (0) This bit controls whether DW_apb_i2c should hold the bus... - // 0x00000100 [8] TX_EMPTY_CTRL (0) This bit controls the generation of the TX_EMPTY... - // 0x00000080 [7] STOP_DET_IFADDRESSED (0) In slave mode: - 1'b1: issues the STOP_DET interrupt... - // 0x00000040 [6] IC_SLAVE_DISABLE (1) This bit controls whether I2C has its slave disabled,... - // 0x00000020 [5] IC_RESTART_EN (1) Determines whether RESTART conditions may be sent when... - // 0x00000010 [4] IC_10BITADDR_MASTER (0) Controls whether the DW_apb_i2c starts its transfers in... - // 0x00000008 [3] IC_10BITADDR_SLAVE (0) When acting as a slave, this bit controls whether the... - // 0x00000006 [2:1] SPEED (0x2) These bits control at which speed the DW_apb_i2c... - // 0x00000001 [0] MASTER_MODE (1) This bit controls whether the DW_apb_i2c master is enabled - io_rw_32 con; - - _REG_(I2C_IC_TAR_OFFSET) // I2C_IC_TAR - // I2C Target Address Register - // 0x00000800 [11] SPECIAL (0) This bit indicates whether software performs a Device-ID... - // 0x00000400 [10] GC_OR_START (0) If bit 11 (SPECIAL) is set to 1 and bit 13(Device-ID) is... - // 0x000003ff [9:0] IC_TAR (0x055) This is the target address for any master transaction - io_rw_32 tar; - - _REG_(I2C_IC_SAR_OFFSET) // I2C_IC_SAR - // I2C Slave Address Register - // 0x000003ff [9:0] IC_SAR (0x055) The IC_SAR holds the slave address when the I2C is... - io_rw_32 sar; - - uint32_t _pad0; - - _REG_(I2C_IC_DATA_CMD_OFFSET) // I2C_IC_DATA_CMD - // I2C Rx/Tx Data Buffer and Command Register - // 0x00000800 [11] FIRST_DATA_BYTE (0) Indicates the first data byte received after the address... - // 0x00000400 [10] RESTART (0) This bit controls whether a RESTART is issued before the... - // 0x00000200 [9] STOP (0) This bit controls whether a STOP is issued after the... - // 0x00000100 [8] CMD (0) This bit controls whether a read or a write is performed - // 0x000000ff [7:0] DAT (0x00) This register contains the data to be transmitted or... - io_rw_32 data_cmd; - - _REG_(I2C_IC_SS_SCL_HCNT_OFFSET) // I2C_IC_SS_SCL_HCNT - // Standard Speed I2C Clock SCL High Count Register - // 0x0000ffff [15:0] IC_SS_SCL_HCNT (0x0028) This register must be set before any I2C bus transaction... - io_rw_32 ss_scl_hcnt; - - _REG_(I2C_IC_SS_SCL_LCNT_OFFSET) // I2C_IC_SS_SCL_LCNT - // Standard Speed I2C Clock SCL Low Count Register - // 0x0000ffff [15:0] IC_SS_SCL_LCNT (0x002f) This register must be set before any I2C bus transaction... - io_rw_32 ss_scl_lcnt; - - _REG_(I2C_IC_FS_SCL_HCNT_OFFSET) // I2C_IC_FS_SCL_HCNT - // Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register - // 0x0000ffff [15:0] IC_FS_SCL_HCNT (0x0006) This register must be set before any I2C bus transaction... - io_rw_32 fs_scl_hcnt; - - _REG_(I2C_IC_FS_SCL_LCNT_OFFSET) // I2C_IC_FS_SCL_LCNT - // Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register - // 0x0000ffff [15:0] IC_FS_SCL_LCNT (0x000d) This register must be set before any I2C bus transaction... - io_rw_32 fs_scl_lcnt; - - uint32_t _pad1[2]; - - _REG_(I2C_IC_INTR_STAT_OFFSET) // I2C_IC_INTR_STAT - // I2C Interrupt Status Register - // 0x00001000 [12] R_RESTART_DET (0) See IC_RAW_INTR_STAT for a detailed description of... - // 0x00000800 [11] R_GEN_CALL (0) See IC_RAW_INTR_STAT for a detailed description of R_GEN_CALL bit - // 0x00000400 [10] R_START_DET (0) See IC_RAW_INTR_STAT for a detailed description of... - // 0x00000200 [9] R_STOP_DET (0) See IC_RAW_INTR_STAT for a detailed description of R_STOP_DET bit - // 0x00000100 [8] R_ACTIVITY (0) See IC_RAW_INTR_STAT for a detailed description of R_ACTIVITY bit - // 0x00000080 [7] R_RX_DONE (0) See IC_RAW_INTR_STAT for a detailed description of R_RX_DONE bit - // 0x00000040 [6] R_TX_ABRT (0) See IC_RAW_INTR_STAT for a detailed description of R_TX_ABRT bit - // 0x00000020 [5] R_RD_REQ (0) See IC_RAW_INTR_STAT for a detailed description of R_RD_REQ bit - // 0x00000010 [4] R_TX_EMPTY (0) See IC_RAW_INTR_STAT for a detailed description of R_TX_EMPTY bit - // 0x00000008 [3] R_TX_OVER (0) See IC_RAW_INTR_STAT for a detailed description of R_TX_OVER bit - // 0x00000004 [2] R_RX_FULL (0) See IC_RAW_INTR_STAT for a detailed description of R_RX_FULL bit - // 0x00000002 [1] R_RX_OVER (0) See IC_RAW_INTR_STAT for a detailed description of R_RX_OVER bit - // 0x00000001 [0] R_RX_UNDER (0) See IC_RAW_INTR_STAT for a detailed description of R_RX_UNDER bit - io_ro_32 intr_stat; - - _REG_(I2C_IC_INTR_MASK_OFFSET) // I2C_IC_INTR_MASK - // I2C Interrupt Mask Register - // 0x00001000 [12] M_RESTART_DET (0) This bit masks the R_RESTART_DET interrupt in... - // 0x00000800 [11] M_GEN_CALL (1) This bit masks the R_GEN_CALL interrupt in IC_INTR_STAT register - // 0x00000400 [10] M_START_DET (0) This bit masks the R_START_DET interrupt in IC_INTR_STAT register - // 0x00000200 [9] M_STOP_DET (0) This bit masks the R_STOP_DET interrupt in IC_INTR_STAT register - // 0x00000100 [8] M_ACTIVITY (0) This bit masks the R_ACTIVITY interrupt in IC_INTR_STAT register - // 0x00000080 [7] M_RX_DONE (1) This bit masks the R_RX_DONE interrupt in IC_INTR_STAT register - // 0x00000040 [6] M_TX_ABRT (1) This bit masks the R_TX_ABRT interrupt in IC_INTR_STAT register - // 0x00000020 [5] M_RD_REQ (1) This bit masks the R_RD_REQ interrupt in IC_INTR_STAT register - // 0x00000010 [4] M_TX_EMPTY (1) This bit masks the R_TX_EMPTY interrupt in IC_INTR_STAT register - // 0x00000008 [3] M_TX_OVER (1) This bit masks the R_TX_OVER interrupt in IC_INTR_STAT register - // 0x00000004 [2] M_RX_FULL (1) This bit masks the R_RX_FULL interrupt in IC_INTR_STAT register - // 0x00000002 [1] M_RX_OVER (1) This bit masks the R_RX_OVER interrupt in IC_INTR_STAT register - // 0x00000001 [0] M_RX_UNDER (1) This bit masks the R_RX_UNDER interrupt in IC_INTR_STAT register - io_rw_32 intr_mask; - - _REG_(I2C_IC_RAW_INTR_STAT_OFFSET) // I2C_IC_RAW_INTR_STAT - // I2C Raw Interrupt Status Register - // 0x00001000 [12] RESTART_DET (0) Indicates whether a RESTART condition has occurred on... - // 0x00000800 [11] GEN_CALL (0) Set only when a General Call address is received and it... - // 0x00000400 [10] START_DET (0) Indicates whether a START or RESTART condition has... - // 0x00000200 [9] STOP_DET (0) Indicates whether a STOP condition has occurred on the... - // 0x00000100 [8] ACTIVITY (0) This bit captures DW_apb_i2c activity and stays set... - // 0x00000080 [7] RX_DONE (0) When the DW_apb_i2c is acting as a slave-transmitter,... - // 0x00000040 [6] TX_ABRT (0) This bit indicates if DW_apb_i2c, as an I2C transmitter,... - // 0x00000020 [5] RD_REQ (0) This bit is set to 1 when DW_apb_i2c is acting as a... - // 0x00000010 [4] TX_EMPTY (0) The behavior of the TX_EMPTY interrupt status differs... - // 0x00000008 [3] TX_OVER (0) Set during transmit if the transmit buffer is filled to... - // 0x00000004 [2] RX_FULL (0) Set when the receive buffer reaches or goes above the... - // 0x00000002 [1] RX_OVER (0) Set if the receive buffer is completely filled to... - // 0x00000001 [0] RX_UNDER (0) Set if the processor attempts to read the receive buffer... - io_ro_32 raw_intr_stat; - - _REG_(I2C_IC_RX_TL_OFFSET) // I2C_IC_RX_TL - // I2C Receive FIFO Threshold Register - // 0x000000ff [7:0] RX_TL (0x00) Receive FIFO Threshold Level - io_rw_32 rx_tl; - - _REG_(I2C_IC_TX_TL_OFFSET) // I2C_IC_TX_TL - // I2C Transmit FIFO Threshold Register - // 0x000000ff [7:0] TX_TL (0x00) Transmit FIFO Threshold Level - io_rw_32 tx_tl; - - _REG_(I2C_IC_CLR_INTR_OFFSET) // I2C_IC_CLR_INTR - // Clear Combined and Individual Interrupt Register - // 0x00000001 [0] CLR_INTR (0) Read this register to clear the combined interrupt, all... - io_ro_32 clr_intr; - - _REG_(I2C_IC_CLR_RX_UNDER_OFFSET) // I2C_IC_CLR_RX_UNDER - // Clear RX_UNDER Interrupt Register - // 0x00000001 [0] CLR_RX_UNDER (0) Read this register to clear the RX_UNDER interrupt (bit... - io_ro_32 clr_rx_under; - - _REG_(I2C_IC_CLR_RX_OVER_OFFSET) // I2C_IC_CLR_RX_OVER - // Clear RX_OVER Interrupt Register - // 0x00000001 [0] CLR_RX_OVER (0) Read this register to clear the RX_OVER interrupt (bit... - io_ro_32 clr_rx_over; - - _REG_(I2C_IC_CLR_TX_OVER_OFFSET) // I2C_IC_CLR_TX_OVER - // Clear TX_OVER Interrupt Register - // 0x00000001 [0] CLR_TX_OVER (0) Read this register to clear the TX_OVER interrupt (bit... - io_ro_32 clr_tx_over; - - _REG_(I2C_IC_CLR_RD_REQ_OFFSET) // I2C_IC_CLR_RD_REQ - // Clear RD_REQ Interrupt Register - // 0x00000001 [0] CLR_RD_REQ (0) Read this register to clear the RD_REQ interrupt (bit 5)... - io_ro_32 clr_rd_req; - - _REG_(I2C_IC_CLR_TX_ABRT_OFFSET) // I2C_IC_CLR_TX_ABRT - // Clear TX_ABRT Interrupt Register - // 0x00000001 [0] CLR_TX_ABRT (0) Read this register to clear the TX_ABRT interrupt (bit... - io_ro_32 clr_tx_abrt; - - _REG_(I2C_IC_CLR_RX_DONE_OFFSET) // I2C_IC_CLR_RX_DONE - // Clear RX_DONE Interrupt Register - // 0x00000001 [0] CLR_RX_DONE (0) Read this register to clear the RX_DONE interrupt (bit... - io_ro_32 clr_rx_done; - - _REG_(I2C_IC_CLR_ACTIVITY_OFFSET) // I2C_IC_CLR_ACTIVITY - // Clear ACTIVITY Interrupt Register - // 0x00000001 [0] CLR_ACTIVITY (0) Reading this register clears the ACTIVITY interrupt if... - io_ro_32 clr_activity; - - _REG_(I2C_IC_CLR_STOP_DET_OFFSET) // I2C_IC_CLR_STOP_DET - // Clear STOP_DET Interrupt Register - // 0x00000001 [0] CLR_STOP_DET (0) Read this register to clear the STOP_DET interrupt (bit... - io_ro_32 clr_stop_det; - - _REG_(I2C_IC_CLR_START_DET_OFFSET) // I2C_IC_CLR_START_DET - // Clear START_DET Interrupt Register - // 0x00000001 [0] CLR_START_DET (0) Read this register to clear the START_DET interrupt (bit... - io_ro_32 clr_start_det; - - _REG_(I2C_IC_CLR_GEN_CALL_OFFSET) // I2C_IC_CLR_GEN_CALL - // Clear GEN_CALL Interrupt Register - // 0x00000001 [0] CLR_GEN_CALL (0) Read this register to clear the GEN_CALL interrupt (bit... - io_ro_32 clr_gen_call; - - _REG_(I2C_IC_ENABLE_OFFSET) // I2C_IC_ENABLE - // I2C ENABLE Register - // 0x00000004 [2] TX_CMD_BLOCK (0) In Master mode: - 1'b1: Blocks the transmission of data... - // 0x00000002 [1] ABORT (0) When set, the controller initiates the transfer abort - // 0x00000001 [0] ENABLE (0) Controls whether the DW_apb_i2c is enabled - io_rw_32 enable; - - _REG_(I2C_IC_STATUS_OFFSET) // I2C_IC_STATUS - // I2C STATUS Register - // 0x00000040 [6] SLV_ACTIVITY (0) Slave FSM Activity Status - // 0x00000020 [5] MST_ACTIVITY (0) Master FSM Activity Status - // 0x00000010 [4] RFF (0) Receive FIFO Completely Full - // 0x00000008 [3] RFNE (0) Receive FIFO Not Empty - // 0x00000004 [2] TFE (1) Transmit FIFO Completely Empty - // 0x00000002 [1] TFNF (1) Transmit FIFO Not Full - // 0x00000001 [0] ACTIVITY (0) I2C Activity Status - io_ro_32 status; - - _REG_(I2C_IC_TXFLR_OFFSET) // I2C_IC_TXFLR - // I2C Transmit FIFO Level Register - // 0x0000001f [4:0] TXFLR (0x00) Transmit FIFO Level - io_ro_32 txflr; - - _REG_(I2C_IC_RXFLR_OFFSET) // I2C_IC_RXFLR - // I2C Receive FIFO Level Register - // 0x0000001f [4:0] RXFLR (0x00) Receive FIFO Level - io_ro_32 rxflr; - - _REG_(I2C_IC_SDA_HOLD_OFFSET) // I2C_IC_SDA_HOLD - // I2C SDA Hold Time Length Register - // 0x00ff0000 [23:16] IC_SDA_RX_HOLD (0x00) Sets the required SDA hold time in units of ic_clk... - // 0x0000ffff [15:0] IC_SDA_TX_HOLD (0x0001) Sets the required SDA hold time in units of ic_clk... - io_rw_32 sda_hold; - - _REG_(I2C_IC_TX_ABRT_SOURCE_OFFSET) // I2C_IC_TX_ABRT_SOURCE - // I2C Transmit Abort Source Register - // 0xff800000 [31:23] TX_FLUSH_CNT (0x000) This field indicates the number of Tx FIFO Data Commands... - // 0x00010000 [16] ABRT_USER_ABRT (0) This is a master-mode-only bit - // 0x00008000 [15] ABRT_SLVRD_INTX (0) 1: When the processor side responds to a slave mode... - // 0x00004000 [14] ABRT_SLV_ARBLOST (0) This field indicates that a Slave has lost the bus while... - // 0x00002000 [13] ABRT_SLVFLUSH_TXFIFO (0) This field specifies that the Slave has received a read... - // 0x00001000 [12] ARB_LOST (0) This field specifies that the Master has lost... - // 0x00000800 [11] ABRT_MASTER_DIS (0) This field indicates that the User tries to initiate a... - // 0x00000400 [10] ABRT_10B_RD_NORSTRT (0) This field indicates that the restart is disabled... - // 0x00000200 [9] ABRT_SBYTE_NORSTRT (0) To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT... - // 0x00000100 [8] ABRT_HS_NORSTRT (0) This field indicates that the restart is disabled... - // 0x00000080 [7] ABRT_SBYTE_ACKDET (0) This field indicates that the Master has sent a START... - // 0x00000040 [6] ABRT_HS_ACKDET (0) This field indicates that the Master is in High Speed... - // 0x00000020 [5] ABRT_GCALL_READ (0) This field indicates that DW_apb_i2c in the master mode... - // 0x00000010 [4] ABRT_GCALL_NOACK (0) This field indicates that DW_apb_i2c in master mode has... - // 0x00000008 [3] ABRT_TXDATA_NOACK (0) This field indicates the master-mode only bit - // 0x00000004 [2] ABRT_10ADDR2_NOACK (0) This field indicates that the Master is in 10-bit... - // 0x00000002 [1] ABRT_10ADDR1_NOACK (0) This field indicates that the Master is in 10-bit... - // 0x00000001 [0] ABRT_7B_ADDR_NOACK (0) This field indicates that the Master is in 7-bit... - io_ro_32 tx_abrt_source; - - _REG_(I2C_IC_SLV_DATA_NACK_ONLY_OFFSET) // I2C_IC_SLV_DATA_NACK_ONLY - // Generate Slave Data NACK Register - // 0x00000001 [0] NACK (0) Generate NACK - io_rw_32 slv_data_nack_only; - - _REG_(I2C_IC_DMA_CR_OFFSET) // I2C_IC_DMA_CR - // DMA Control Register - // 0x00000002 [1] TDMAE (0) Transmit DMA Enable - // 0x00000001 [0] RDMAE (0) Receive DMA Enable - io_rw_32 dma_cr; - - _REG_(I2C_IC_DMA_TDLR_OFFSET) // I2C_IC_DMA_TDLR - // DMA Transmit Data Level Register - // 0x0000000f [3:0] DMATDL (0x0) Transmit Data Level - io_rw_32 dma_tdlr; - - _REG_(I2C_IC_DMA_RDLR_OFFSET) // I2C_IC_DMA_RDLR - // DMA Transmit Data Level Register - // 0x0000000f [3:0] DMARDL (0x0) Receive Data Level - io_rw_32 dma_rdlr; - - _REG_(I2C_IC_SDA_SETUP_OFFSET) // I2C_IC_SDA_SETUP - // I2C SDA Setup Register - // 0x000000ff [7:0] SDA_SETUP (0x64) SDA Setup - io_rw_32 sda_setup; - - _REG_(I2C_IC_ACK_GENERAL_CALL_OFFSET) // I2C_IC_ACK_GENERAL_CALL - // I2C ACK General Call Register - // 0x00000001 [0] ACK_GEN_CALL (1) ACK General Call - io_rw_32 ack_general_call; - - _REG_(I2C_IC_ENABLE_STATUS_OFFSET) // I2C_IC_ENABLE_STATUS - // I2C Enable Status Register - // 0x00000004 [2] SLV_RX_DATA_LOST (0) Slave Received Data Lost - // 0x00000002 [1] SLV_DISABLED_WHILE_BUSY (0) Slave Disabled While Busy (Transmit, Receive) - // 0x00000001 [0] IC_EN (0) ic_en Status - io_ro_32 enable_status; - - _REG_(I2C_IC_FS_SPKLEN_OFFSET) // I2C_IC_FS_SPKLEN - // I2C SS, FS or FM+ spike suppression limit - // 0x000000ff [7:0] IC_FS_SPKLEN (0x07) This register must be set before any I2C bus transaction... - io_rw_32 fs_spklen; - - uint32_t _pad2; - - _REG_(I2C_IC_CLR_RESTART_DET_OFFSET) // I2C_IC_CLR_RESTART_DET - // Clear RESTART_DET Interrupt Register - // 0x00000001 [0] CLR_RESTART_DET (0) Read this register to clear the RESTART_DET interrupt... - io_ro_32 clr_restart_det; - - uint32_t _pad3[18]; - - _REG_(I2C_IC_COMP_PARAM_1_OFFSET) // I2C_IC_COMP_PARAM_1 - // Component Parameter Register 1 - // 0x00ff0000 [23:16] TX_BUFFER_DEPTH (0x00) TX Buffer Depth = 16 - // 0x0000ff00 [15:8] RX_BUFFER_DEPTH (0x00) RX Buffer Depth = 16 - // 0x00000080 [7] ADD_ENCODED_PARAMS (0) Encoded parameters not visible - // 0x00000040 [6] HAS_DMA (0) DMA handshaking signals are enabled - // 0x00000020 [5] INTR_IO (0) COMBINED Interrupt outputs - // 0x00000010 [4] HC_COUNT_VALUES (0) Programmable count values for each mode - // 0x0000000c [3:2] MAX_SPEED_MODE (0x0) MAX SPEED MODE = FAST MODE - // 0x00000003 [1:0] APB_DATA_WIDTH (0x0) APB data bus width is 32 bits - io_ro_32 comp_param_1; - - _REG_(I2C_IC_COMP_VERSION_OFFSET) // I2C_IC_COMP_VERSION - // I2C Component Version Register - // 0xffffffff [31:0] IC_COMP_VERSION (0x3230312a) - io_ro_32 comp_version; - - _REG_(I2C_IC_COMP_TYPE_OFFSET) // I2C_IC_COMP_TYPE - // I2C Component Type Register - // 0xffffffff [31:0] IC_COMP_TYPE (0x44570140) Designware Component Type number = 0x44_57_01_40 - io_ro_32 comp_type; -} i2c_hw_t; - -#define i2c0_hw ((i2c_hw_t *)I2C0_BASE) -#define i2c1_hw ((i2c_hw_t *)I2C1_BASE) -static_assert(sizeof (i2c_hw_t) == 0x0100, ""); - -#endif // _HARDWARE_STRUCTS_I2C_H - diff --git a/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/interp.h b/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/interp.h deleted file mode 100644 index eec0e3da63..0000000000 --- a/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/interp.h +++ /dev/null @@ -1,87 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _HARDWARE_STRUCTS_INTERP_H -#define _HARDWARE_STRUCTS_INTERP_H - -/** - * \file rp2350/interp.h - */ - -#include "hardware/address_mapped.h" -#include "hardware/regs/sio.h" - -// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_sio -// -// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) -// _REG_(x) will link to the corresponding register in hardware/regs/sio.h. -// -// Bit-field descriptions are of the form: -// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION - -typedef struct { - // (Description copied from array index 0 register SIO_INTERP0_ACCUM0 applies similarly to other array indexes) - _REG_(SIO_INTERP0_ACCUM0_OFFSET) // SIO_INTERP0_ACCUM0 - // Read/write access to accumulator 0 - // 0xffffffff [31:0] INTERP0_ACCUM0 (0x00000000) - io_rw_32 accum[2]; - - // (Description copied from array index 0 register SIO_INTERP0_BASE0 applies similarly to other array indexes) - _REG_(SIO_INTERP0_BASE0_OFFSET) // SIO_INTERP0_BASE0 - // Read/write access to BASE0 register - // 0xffffffff [31:0] INTERP0_BASE0 (0x00000000) - io_rw_32 base[3]; - - // (Description copied from array index 0 register SIO_INTERP0_POP_LANE0 applies similarly to other array indexes) - _REG_(SIO_INTERP0_POP_LANE0_OFFSET) // SIO_INTERP0_POP_LANE0 - // Read LANE0 result, and simultaneously write lane results to both accumulators (POP) - // 0xffffffff [31:0] INTERP0_POP_LANE0 (0x00000000) - io_ro_32 pop[3]; - - // (Description copied from array index 0 register SIO_INTERP0_PEEK_LANE0 applies similarly to other array indexes) - _REG_(SIO_INTERP0_PEEK_LANE0_OFFSET) // SIO_INTERP0_PEEK_LANE0 - // Read LANE0 result, without altering any internal state (PEEK) - // 0xffffffff [31:0] INTERP0_PEEK_LANE0 (0x00000000) - io_ro_32 peek[3]; - - // (Description copied from array index 0 register SIO_INTERP0_CTRL_LANE0 applies similarly to other array indexes) - _REG_(SIO_INTERP0_CTRL_LANE0_OFFSET) // SIO_INTERP0_CTRL_LANE0 - // Control register for lane 0 - // 0x02000000 [25] OVERF (0) Set if either OVERF0 or OVERF1 is set - // 0x01000000 [24] OVERF1 (0) Indicates if any masked-off MSBs in ACCUM1 are set - // 0x00800000 [23] OVERF0 (0) Indicates if any masked-off MSBs in ACCUM0 are set - // 0x00200000 [21] BLEND (0) Only present on INTERP0 on each core - // 0x00180000 [20:19] FORCE_MSB (0x0) ORed into bits 29:28 of the lane result presented to the... - // 0x00040000 [18] ADD_RAW (0) If 1, mask + shift is bypassed for LANE0 result - // 0x00020000 [17] CROSS_RESULT (0) If 1, feed the opposite lane's result into this lane's... - // 0x00010000 [16] CROSS_INPUT (0) If 1, feed the opposite lane's accumulator into this... - // 0x00008000 [15] SIGNED (0) If SIGNED is set, the shifted and masked accumulator... - // 0x00007c00 [14:10] MASK_MSB (0x00) The most-significant bit allowed to pass by the mask... - // 0x000003e0 [9:5] MASK_LSB (0x00) The least-significant bit allowed to pass by the mask (inclusive) - // 0x0000001f [4:0] SHIFT (0x00) Right-rotate applied to accumulator before masking - io_rw_32 ctrl[2]; - - // (Description copied from array index 0 register SIO_INTERP0_ACCUM0_ADD applies similarly to other array indexes) - _REG_(SIO_INTERP0_ACCUM0_ADD_OFFSET) // SIO_INTERP0_ACCUM0_ADD - // Values written here are atomically added to ACCUM0 - // 0x00ffffff [23:0] INTERP0_ACCUM0_ADD (0x000000) - io_rw_32 add_raw[2]; - - _REG_(SIO_INTERP0_BASE_1AND0_OFFSET) // SIO_INTERP0_BASE_1AND0 - // On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously. - // 0xffffffff [31:0] INTERP0_BASE_1AND0 (0x00000000) - io_wo_32 base01; -} interp_hw_t; - -#define interp_hw_array ((interp_hw_t *)(SIO_BASE + SIO_INTERP0_ACCUM0_OFFSET)) -#define interp_hw_array_ns ((interp_hw_t *)(SIO_NONSEC_BASE + SIO_INTERP0_ACCUM0_OFFSET)) -static_assert(sizeof (interp_hw_t) == 0x0040, ""); -#define interp0_hw (&interp_hw_array[0]) -#define interp1_hw (&interp_hw_array[1]) - -#endif // _HARDWARE_STRUCTS_INTERP_H - diff --git a/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/io_bank0.h b/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/io_bank0.h deleted file mode 100644 index c5020e2325..0000000000 --- a/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/io_bank0.h +++ /dev/null @@ -1,452 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _HARDWARE_STRUCTS_IO_BANK0_H -#define _HARDWARE_STRUCTS_IO_BANK0_H - -/** - * \file rp2350/io_bank0.h - */ - -#include "hardware/address_mapped.h" -#include "hardware/regs/io_bank0.h" - -// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_io_bank0 -// -// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) -// _REG_(x) will link to the corresponding register in hardware/regs/io_bank0.h. -// -// Bit-field descriptions are of the form: -// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION - -/** - * \brief GPIO pin function selectors on RP2350 (used as typedef \ref gpio_function_t) - * \ingroup hardware_gpio - */ -typedef enum gpio_function_rp2350 { - GPIO_FUNC_HSTX = 0, ///< Select HSTX as GPIO pin function - GPIO_FUNC_SPI = 1, ///< Select SPI as GPIO pin function - GPIO_FUNC_UART = 2, ///< Select UART as GPIO pin function - GPIO_FUNC_I2C = 3, ///< Select I2C as GPIO pin function - GPIO_FUNC_PWM = 4, ///< Select PWM as GPIO pin function - GPIO_FUNC_SIO = 5, ///< Select SIO as GPIO pin function - GPIO_FUNC_PIO0 = 6, ///< Select PIO0 as GPIO pin function - GPIO_FUNC_PIO1 = 7, ///< Select PIO1 as GPIO pin function - GPIO_FUNC_PIO2 = 8, ///< Select PIO2 as GPIO pin function - GPIO_FUNC_GPCK = 9, ///< Select GPCK as GPIO pin function - GPIO_FUNC_XIP_CS1 = 9, ///< Select XIP CS1 as GPIO pin function - GPIO_FUNC_CORESIGHT_TRACE = 9, ///< Select CORESIGHT TRACE as GPIO pin function - GPIO_FUNC_USB = 10, ///< Select USB as GPIO pin function - GPIO_FUNC_UART_AUX = 11, ///< Select UART_AUX as GPIO pin function - GPIO_FUNC_NULL = 0x1f, ///< Select NULL as GPIO pin function -} gpio_function_t; - -typedef struct { - _REG_(IO_BANK0_GPIO0_STATUS_OFFSET) // IO_BANK0_GPIO0_STATUS - // 0x04000000 [26] IRQTOPROC (0) interrupt to processors, after override is applied - // 0x00020000 [17] INFROMPAD (0) input signal from pad, before filtering and override are applied - // 0x00002000 [13] OETOPAD (0) output enable to pad after register override is applied - // 0x00000200 [9] OUTTOPAD (0) output signal to pad after register override is applied - io_ro_32 status; - - _REG_(IO_BANK0_GPIO0_CTRL_OFFSET) // IO_BANK0_GPIO0_CTRL - // 0x30000000 [29:28] IRQOVER (0x0) - // 0x00030000 [17:16] INOVER (0x0) - // 0x0000c000 [15:14] OEOVER (0x0) - // 0x00003000 [13:12] OUTOVER (0x0) - // 0x0000001f [4:0] FUNCSEL (0x1f) 0-31 -> selects pin function according to the gpio table + - io_rw_32 ctrl; -} io_bank0_status_ctrl_hw_t; - -typedef struct { - // (Description copied from array index 0 register IO_BANK0_PROC0_INTE0 applies similarly to other array indexes) - _REG_(IO_BANK0_PROC0_INTE0_OFFSET) // IO_BANK0_PROC0_INTE0 - // Interrupt Enable for proc0 - // 0x80000000 [31] GPIO7_EDGE_HIGH (0) - // 0x40000000 [30] GPIO7_EDGE_LOW (0) - // 0x20000000 [29] GPIO7_LEVEL_HIGH (0) - // 0x10000000 [28] GPIO7_LEVEL_LOW (0) - // 0x08000000 [27] GPIO6_EDGE_HIGH (0) - // 0x04000000 [26] GPIO6_EDGE_LOW (0) - // 0x02000000 [25] GPIO6_LEVEL_HIGH (0) - // 0x01000000 [24] GPIO6_LEVEL_LOW (0) - // 0x00800000 [23] GPIO5_EDGE_HIGH (0) - // 0x00400000 [22] GPIO5_EDGE_LOW (0) - // 0x00200000 [21] GPIO5_LEVEL_HIGH (0) - // 0x00100000 [20] GPIO5_LEVEL_LOW (0) - // 0x00080000 [19] GPIO4_EDGE_HIGH (0) - // 0x00040000 [18] GPIO4_EDGE_LOW (0) - // 0x00020000 [17] GPIO4_LEVEL_HIGH (0) - // 0x00010000 [16] GPIO4_LEVEL_LOW (0) - // 0x00008000 [15] GPIO3_EDGE_HIGH (0) - // 0x00004000 [14] GPIO3_EDGE_LOW (0) - // 0x00002000 [13] GPIO3_LEVEL_HIGH (0) - // 0x00001000 [12] GPIO3_LEVEL_LOW (0) - // 0x00000800 [11] GPIO2_EDGE_HIGH (0) - // 0x00000400 [10] GPIO2_EDGE_LOW (0) - // 0x00000200 [9] GPIO2_LEVEL_HIGH (0) - // 0x00000100 [8] GPIO2_LEVEL_LOW (0) - // 0x00000080 [7] GPIO1_EDGE_HIGH (0) - // 0x00000040 [6] GPIO1_EDGE_LOW (0) - // 0x00000020 [5] GPIO1_LEVEL_HIGH (0) - // 0x00000010 [4] GPIO1_LEVEL_LOW (0) - // 0x00000008 [3] GPIO0_EDGE_HIGH (0) - // 0x00000004 [2] GPIO0_EDGE_LOW (0) - // 0x00000002 [1] GPIO0_LEVEL_HIGH (0) - // 0x00000001 [0] GPIO0_LEVEL_LOW (0) - io_rw_32 inte[6]; - - // (Description copied from array index 0 register IO_BANK0_PROC0_INTF0 applies similarly to other array indexes) - _REG_(IO_BANK0_PROC0_INTF0_OFFSET) // IO_BANK0_PROC0_INTF0 - // Interrupt Force for proc0 - // 0x80000000 [31] GPIO7_EDGE_HIGH (0) - // 0x40000000 [30] GPIO7_EDGE_LOW (0) - // 0x20000000 [29] GPIO7_LEVEL_HIGH (0) - // 0x10000000 [28] GPIO7_LEVEL_LOW (0) - // 0x08000000 [27] GPIO6_EDGE_HIGH (0) - // 0x04000000 [26] GPIO6_EDGE_LOW (0) - // 0x02000000 [25] GPIO6_LEVEL_HIGH (0) - // 0x01000000 [24] GPIO6_LEVEL_LOW (0) - // 0x00800000 [23] GPIO5_EDGE_HIGH (0) - // 0x00400000 [22] GPIO5_EDGE_LOW (0) - // 0x00200000 [21] GPIO5_LEVEL_HIGH (0) - // 0x00100000 [20] GPIO5_LEVEL_LOW (0) - // 0x00080000 [19] GPIO4_EDGE_HIGH (0) - // 0x00040000 [18] GPIO4_EDGE_LOW (0) - // 0x00020000 [17] GPIO4_LEVEL_HIGH (0) - // 0x00010000 [16] GPIO4_LEVEL_LOW (0) - // 0x00008000 [15] GPIO3_EDGE_HIGH (0) - // 0x00004000 [14] GPIO3_EDGE_LOW (0) - // 0x00002000 [13] GPIO3_LEVEL_HIGH (0) - // 0x00001000 [12] GPIO3_LEVEL_LOW (0) - // 0x00000800 [11] GPIO2_EDGE_HIGH (0) - // 0x00000400 [10] GPIO2_EDGE_LOW (0) - // 0x00000200 [9] GPIO2_LEVEL_HIGH (0) - // 0x00000100 [8] GPIO2_LEVEL_LOW (0) - // 0x00000080 [7] GPIO1_EDGE_HIGH (0) - // 0x00000040 [6] GPIO1_EDGE_LOW (0) - // 0x00000020 [5] GPIO1_LEVEL_HIGH (0) - // 0x00000010 [4] GPIO1_LEVEL_LOW (0) - // 0x00000008 [3] GPIO0_EDGE_HIGH (0) - // 0x00000004 [2] GPIO0_EDGE_LOW (0) - // 0x00000002 [1] GPIO0_LEVEL_HIGH (0) - // 0x00000001 [0] GPIO0_LEVEL_LOW (0) - io_rw_32 intf[6]; - - // (Description copied from array index 0 register IO_BANK0_PROC0_INTS0 applies similarly to other array indexes) - _REG_(IO_BANK0_PROC0_INTS0_OFFSET) // IO_BANK0_PROC0_INTS0 - // Interrupt status after masking & forcing for proc0 - // 0x80000000 [31] GPIO7_EDGE_HIGH (0) - // 0x40000000 [30] GPIO7_EDGE_LOW (0) - // 0x20000000 [29] GPIO7_LEVEL_HIGH (0) - // 0x10000000 [28] GPIO7_LEVEL_LOW (0) - // 0x08000000 [27] GPIO6_EDGE_HIGH (0) - // 0x04000000 [26] GPIO6_EDGE_LOW (0) - // 0x02000000 [25] GPIO6_LEVEL_HIGH (0) - // 0x01000000 [24] GPIO6_LEVEL_LOW (0) - // 0x00800000 [23] GPIO5_EDGE_HIGH (0) - // 0x00400000 [22] GPIO5_EDGE_LOW (0) - // 0x00200000 [21] GPIO5_LEVEL_HIGH (0) - // 0x00100000 [20] GPIO5_LEVEL_LOW (0) - // 0x00080000 [19] GPIO4_EDGE_HIGH (0) - // 0x00040000 [18] GPIO4_EDGE_LOW (0) - // 0x00020000 [17] GPIO4_LEVEL_HIGH (0) - // 0x00010000 [16] GPIO4_LEVEL_LOW (0) - // 0x00008000 [15] GPIO3_EDGE_HIGH (0) - // 0x00004000 [14] GPIO3_EDGE_LOW (0) - // 0x00002000 [13] GPIO3_LEVEL_HIGH (0) - // 0x00001000 [12] GPIO3_LEVEL_LOW (0) - // 0x00000800 [11] GPIO2_EDGE_HIGH (0) - // 0x00000400 [10] GPIO2_EDGE_LOW (0) - // 0x00000200 [9] GPIO2_LEVEL_HIGH (0) - // 0x00000100 [8] GPIO2_LEVEL_LOW (0) - // 0x00000080 [7] GPIO1_EDGE_HIGH (0) - // 0x00000040 [6] GPIO1_EDGE_LOW (0) - // 0x00000020 [5] GPIO1_LEVEL_HIGH (0) - // 0x00000010 [4] GPIO1_LEVEL_LOW (0) - // 0x00000008 [3] GPIO0_EDGE_HIGH (0) - // 0x00000004 [2] GPIO0_EDGE_LOW (0) - // 0x00000002 [1] GPIO0_LEVEL_HIGH (0) - // 0x00000001 [0] GPIO0_LEVEL_LOW (0) - io_ro_32 ints[6]; -} io_bank0_irq_ctrl_hw_t; - -/// \tag::io_bank0_hw[] -typedef struct { - io_bank0_status_ctrl_hw_t io[48]; - - uint32_t _pad0[32]; - - // (Description copied from array index 0 register IO_BANK0_IRQSUMMARY_PROC0_SECURE0 applies similarly to other array indexes) - _REG_(IO_BANK0_IRQSUMMARY_PROC0_SECURE0_OFFSET) // IO_BANK0_IRQSUMMARY_PROC0_SECURE0 - // 0x80000000 [31] GPIO31 (0) - // 0x40000000 [30] GPIO30 (0) - // 0x20000000 [29] GPIO29 (0) - // 0x10000000 [28] GPIO28 (0) - // 0x08000000 [27] GPIO27 (0) - // 0x04000000 [26] GPIO26 (0) - // 0x02000000 [25] GPIO25 (0) - // 0x01000000 [24] GPIO24 (0) - // 0x00800000 [23] GPIO23 (0) - // 0x00400000 [22] GPIO22 (0) - // 0x00200000 [21] GPIO21 (0) - // 0x00100000 [20] GPIO20 (0) - // 0x00080000 [19] GPIO19 (0) - // 0x00040000 [18] GPIO18 (0) - // 0x00020000 [17] GPIO17 (0) - // 0x00010000 [16] GPIO16 (0) - // 0x00008000 [15] GPIO15 (0) - // 0x00004000 [14] GPIO14 (0) - // 0x00002000 [13] GPIO13 (0) - // 0x00001000 [12] GPIO12 (0) - // 0x00000800 [11] GPIO11 (0) - // 0x00000400 [10] GPIO10 (0) - // 0x00000200 [9] GPIO9 (0) - // 0x00000100 [8] GPIO8 (0) - // 0x00000080 [7] GPIO7 (0) - // 0x00000040 [6] GPIO6 (0) - // 0x00000020 [5] GPIO5 (0) - // 0x00000010 [4] GPIO4 (0) - // 0x00000008 [3] GPIO3 (0) - // 0x00000004 [2] GPIO2 (0) - // 0x00000002 [1] GPIO1 (0) - // 0x00000001 [0] GPIO0 (0) - io_ro_32 irqsummary_proc0_secure[2]; - - // (Description copied from array index 0 register IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0 applies similarly to other array indexes) - _REG_(IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_OFFSET) // IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0 - // 0x80000000 [31] GPIO31 (0) - // 0x40000000 [30] GPIO30 (0) - // 0x20000000 [29] GPIO29 (0) - // 0x10000000 [28] GPIO28 (0) - // 0x08000000 [27] GPIO27 (0) - // 0x04000000 [26] GPIO26 (0) - // 0x02000000 [25] GPIO25 (0) - // 0x01000000 [24] GPIO24 (0) - // 0x00800000 [23] GPIO23 (0) - // 0x00400000 [22] GPIO22 (0) - // 0x00200000 [21] GPIO21 (0) - // 0x00100000 [20] GPIO20 (0) - // 0x00080000 [19] GPIO19 (0) - // 0x00040000 [18] GPIO18 (0) - // 0x00020000 [17] GPIO17 (0) - // 0x00010000 [16] GPIO16 (0) - // 0x00008000 [15] GPIO15 (0) - // 0x00004000 [14] GPIO14 (0) - // 0x00002000 [13] GPIO13 (0) - // 0x00001000 [12] GPIO12 (0) - // 0x00000800 [11] GPIO11 (0) - // 0x00000400 [10] GPIO10 (0) - // 0x00000200 [9] GPIO9 (0) - // 0x00000100 [8] GPIO8 (0) - // 0x00000080 [7] GPIO7 (0) - // 0x00000040 [6] GPIO6 (0) - // 0x00000020 [5] GPIO5 (0) - // 0x00000010 [4] GPIO4 (0) - // 0x00000008 [3] GPIO3 (0) - // 0x00000004 [2] GPIO2 (0) - // 0x00000002 [1] GPIO1 (0) - // 0x00000001 [0] GPIO0 (0) - io_ro_32 irqsummary_proc0_nonsecure[2]; - - // (Description copied from array index 0 register IO_BANK0_IRQSUMMARY_PROC1_SECURE0 applies similarly to other array indexes) - _REG_(IO_BANK0_IRQSUMMARY_PROC1_SECURE0_OFFSET) // IO_BANK0_IRQSUMMARY_PROC1_SECURE0 - // 0x80000000 [31] GPIO31 (0) - // 0x40000000 [30] GPIO30 (0) - // 0x20000000 [29] GPIO29 (0) - // 0x10000000 [28] GPIO28 (0) - // 0x08000000 [27] GPIO27 (0) - // 0x04000000 [26] GPIO26 (0) - // 0x02000000 [25] GPIO25 (0) - // 0x01000000 [24] GPIO24 (0) - // 0x00800000 [23] GPIO23 (0) - // 0x00400000 [22] GPIO22 (0) - // 0x00200000 [21] GPIO21 (0) - // 0x00100000 [20] GPIO20 (0) - // 0x00080000 [19] GPIO19 (0) - // 0x00040000 [18] GPIO18 (0) - // 0x00020000 [17] GPIO17 (0) - // 0x00010000 [16] GPIO16 (0) - // 0x00008000 [15] GPIO15 (0) - // 0x00004000 [14] GPIO14 (0) - // 0x00002000 [13] GPIO13 (0) - // 0x00001000 [12] GPIO12 (0) - // 0x00000800 [11] GPIO11 (0) - // 0x00000400 [10] GPIO10 (0) - // 0x00000200 [9] GPIO9 (0) - // 0x00000100 [8] GPIO8 (0) - // 0x00000080 [7] GPIO7 (0) - // 0x00000040 [6] GPIO6 (0) - // 0x00000020 [5] GPIO5 (0) - // 0x00000010 [4] GPIO4 (0) - // 0x00000008 [3] GPIO3 (0) - // 0x00000004 [2] GPIO2 (0) - // 0x00000002 [1] GPIO1 (0) - // 0x00000001 [0] GPIO0 (0) - io_ro_32 irqsummary_proc1_secure[2]; - - // (Description copied from array index 0 register IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0 applies similarly to other array indexes) - _REG_(IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_OFFSET) // IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0 - // 0x80000000 [31] GPIO31 (0) - // 0x40000000 [30] GPIO30 (0) - // 0x20000000 [29] GPIO29 (0) - // 0x10000000 [28] GPIO28 (0) - // 0x08000000 [27] GPIO27 (0) - // 0x04000000 [26] GPIO26 (0) - // 0x02000000 [25] GPIO25 (0) - // 0x01000000 [24] GPIO24 (0) - // 0x00800000 [23] GPIO23 (0) - // 0x00400000 [22] GPIO22 (0) - // 0x00200000 [21] GPIO21 (0) - // 0x00100000 [20] GPIO20 (0) - // 0x00080000 [19] GPIO19 (0) - // 0x00040000 [18] GPIO18 (0) - // 0x00020000 [17] GPIO17 (0) - // 0x00010000 [16] GPIO16 (0) - // 0x00008000 [15] GPIO15 (0) - // 0x00004000 [14] GPIO14 (0) - // 0x00002000 [13] GPIO13 (0) - // 0x00001000 [12] GPIO12 (0) - // 0x00000800 [11] GPIO11 (0) - // 0x00000400 [10] GPIO10 (0) - // 0x00000200 [9] GPIO9 (0) - // 0x00000100 [8] GPIO8 (0) - // 0x00000080 [7] GPIO7 (0) - // 0x00000040 [6] GPIO6 (0) - // 0x00000020 [5] GPIO5 (0) - // 0x00000010 [4] GPIO4 (0) - // 0x00000008 [3] GPIO3 (0) - // 0x00000004 [2] GPIO2 (0) - // 0x00000002 [1] GPIO1 (0) - // 0x00000001 [0] GPIO0 (0) - io_ro_32 irqsummary_proc1_nonsecure[2]; - - // (Description copied from array index 0 register IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0 applies similarly to other array indexes) - _REG_(IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_OFFSET) // IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0 - // 0x80000000 [31] GPIO31 (0) - // 0x40000000 [30] GPIO30 (0) - // 0x20000000 [29] GPIO29 (0) - // 0x10000000 [28] GPIO28 (0) - // 0x08000000 [27] GPIO27 (0) - // 0x04000000 [26] GPIO26 (0) - // 0x02000000 [25] GPIO25 (0) - // 0x01000000 [24] GPIO24 (0) - // 0x00800000 [23] GPIO23 (0) - // 0x00400000 [22] GPIO22 (0) - // 0x00200000 [21] GPIO21 (0) - // 0x00100000 [20] GPIO20 (0) - // 0x00080000 [19] GPIO19 (0) - // 0x00040000 [18] GPIO18 (0) - // 0x00020000 [17] GPIO17 (0) - // 0x00010000 [16] GPIO16 (0) - // 0x00008000 [15] GPIO15 (0) - // 0x00004000 [14] GPIO14 (0) - // 0x00002000 [13] GPIO13 (0) - // 0x00001000 [12] GPIO12 (0) - // 0x00000800 [11] GPIO11 (0) - // 0x00000400 [10] GPIO10 (0) - // 0x00000200 [9] GPIO9 (0) - // 0x00000100 [8] GPIO8 (0) - // 0x00000080 [7] GPIO7 (0) - // 0x00000040 [6] GPIO6 (0) - // 0x00000020 [5] GPIO5 (0) - // 0x00000010 [4] GPIO4 (0) - // 0x00000008 [3] GPIO3 (0) - // 0x00000004 [2] GPIO2 (0) - // 0x00000002 [1] GPIO1 (0) - // 0x00000001 [0] GPIO0 (0) - io_ro_32 irqsummary_dormant_wake_secure[2]; - - // (Description copied from array index 0 register IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0 applies similarly to other array indexes) - _REG_(IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_OFFSET) // IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0 - // 0x80000000 [31] GPIO31 (0) - // 0x40000000 [30] GPIO30 (0) - // 0x20000000 [29] GPIO29 (0) - // 0x10000000 [28] GPIO28 (0) - // 0x08000000 [27] GPIO27 (0) - // 0x04000000 [26] GPIO26 (0) - // 0x02000000 [25] GPIO25 (0) - // 0x01000000 [24] GPIO24 (0) - // 0x00800000 [23] GPIO23 (0) - // 0x00400000 [22] GPIO22 (0) - // 0x00200000 [21] GPIO21 (0) - // 0x00100000 [20] GPIO20 (0) - // 0x00080000 [19] GPIO19 (0) - // 0x00040000 [18] GPIO18 (0) - // 0x00020000 [17] GPIO17 (0) - // 0x00010000 [16] GPIO16 (0) - // 0x00008000 [15] GPIO15 (0) - // 0x00004000 [14] GPIO14 (0) - // 0x00002000 [13] GPIO13 (0) - // 0x00001000 [12] GPIO12 (0) - // 0x00000800 [11] GPIO11 (0) - // 0x00000400 [10] GPIO10 (0) - // 0x00000200 [9] GPIO9 (0) - // 0x00000100 [8] GPIO8 (0) - // 0x00000080 [7] GPIO7 (0) - // 0x00000040 [6] GPIO6 (0) - // 0x00000020 [5] GPIO5 (0) - // 0x00000010 [4] GPIO4 (0) - // 0x00000008 [3] GPIO3 (0) - // 0x00000004 [2] GPIO2 (0) - // 0x00000002 [1] GPIO1 (0) - // 0x00000001 [0] GPIO0 (0) - io_ro_32 irqsummary_dormant_wake_nonsecure[2]; - - // (Description copied from array index 0 register IO_BANK0_INTR0 applies similarly to other array indexes) - _REG_(IO_BANK0_INTR0_OFFSET) // IO_BANK0_INTR0 - // Raw Interrupts - // 0x80000000 [31] GPIO7_EDGE_HIGH (0) - // 0x40000000 [30] GPIO7_EDGE_LOW (0) - // 0x20000000 [29] GPIO7_LEVEL_HIGH (0) - // 0x10000000 [28] GPIO7_LEVEL_LOW (0) - // 0x08000000 [27] GPIO6_EDGE_HIGH (0) - // 0x04000000 [26] GPIO6_EDGE_LOW (0) - // 0x02000000 [25] GPIO6_LEVEL_HIGH (0) - // 0x01000000 [24] GPIO6_LEVEL_LOW (0) - // 0x00800000 [23] GPIO5_EDGE_HIGH (0) - // 0x00400000 [22] GPIO5_EDGE_LOW (0) - // 0x00200000 [21] GPIO5_LEVEL_HIGH (0) - // 0x00100000 [20] GPIO5_LEVEL_LOW (0) - // 0x00080000 [19] GPIO4_EDGE_HIGH (0) - // 0x00040000 [18] GPIO4_EDGE_LOW (0) - // 0x00020000 [17] GPIO4_LEVEL_HIGH (0) - // 0x00010000 [16] GPIO4_LEVEL_LOW (0) - // 0x00008000 [15] GPIO3_EDGE_HIGH (0) - // 0x00004000 [14] GPIO3_EDGE_LOW (0) - // 0x00002000 [13] GPIO3_LEVEL_HIGH (0) - // 0x00001000 [12] GPIO3_LEVEL_LOW (0) - // 0x00000800 [11] GPIO2_EDGE_HIGH (0) - // 0x00000400 [10] GPIO2_EDGE_LOW (0) - // 0x00000200 [9] GPIO2_LEVEL_HIGH (0) - // 0x00000100 [8] GPIO2_LEVEL_LOW (0) - // 0x00000080 [7] GPIO1_EDGE_HIGH (0) - // 0x00000040 [6] GPIO1_EDGE_LOW (0) - // 0x00000020 [5] GPIO1_LEVEL_HIGH (0) - // 0x00000010 [4] GPIO1_LEVEL_LOW (0) - // 0x00000008 [3] GPIO0_EDGE_HIGH (0) - // 0x00000004 [2] GPIO0_EDGE_LOW (0) - // 0x00000002 [1] GPIO0_LEVEL_HIGH (0) - // 0x00000001 [0] GPIO0_LEVEL_LOW (0) - io_rw_32 intr[6]; - - union { - struct { - io_bank0_irq_ctrl_hw_t proc0_irq_ctrl; - io_bank0_irq_ctrl_hw_t proc1_irq_ctrl; - io_bank0_irq_ctrl_hw_t dormant_wake_irq_ctrl; - }; - io_bank0_irq_ctrl_hw_t irq_ctrl[3]; - }; -} io_bank0_hw_t; -/// \end::io_bank0_hw[] - -#define io_bank0_hw ((io_bank0_hw_t *)IO_BANK0_BASE) -static_assert(sizeof (io_bank0_hw_t) == 0x0320, ""); - -#endif // _HARDWARE_STRUCTS_IO_BANK0_H - diff --git a/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/io_qspi.h b/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/io_qspi.h deleted file mode 100644 index cec2bba656..0000000000 --- a/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/io_qspi.h +++ /dev/null @@ -1,316 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _HARDWARE_STRUCTS_IO_QSPI_H -#define _HARDWARE_STRUCTS_IO_QSPI_H - -/** - * \file rp2350/io_qspi.h - */ - -#include "hardware/address_mapped.h" -#include "hardware/regs/io_qspi.h" - -// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_io_qspi -// -// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) -// _REG_(x) will link to the corresponding register in hardware/regs/io_qspi.h. -// -// Bit-field descriptions are of the form: -// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION - -/** - * \brief QSPI pin function selectors on RP2350 (used as typedef \ref gpio_function1_t) - */ -typedef enum gpio_function1_rp2350 { - GPIO_FUNC1_XIP = 0, ///< Select XIP as QSPI pin function - GPIO_FUNC1_UART = 2, ///< Select UART as QSPI pin function - GPIO_FUNC1_I2C = 3, ///< Select I2C as QSPI pin function - GPIO_FUNC1_SIO = 5, ///< Select SIO as QSPI pin function - GPIO_FUNC1_UART_AUX = 11, ///< Select UART_AUX as QSPI pin function - GPIO_FUNC1_NULL = 0x1f, ///< Select NULL as QSPI pin function -} gpio_function1_t; - -typedef struct { - _REG_(IO_QSPI_GPIO_QSPI_SCLK_STATUS_OFFSET) // IO_QSPI_GPIO_QSPI_SCLK_STATUS - // 0x04000000 [26] IRQTOPROC (0) interrupt to processors, after override is applied - // 0x00020000 [17] INFROMPAD (0) input signal from pad, before filtering and override are applied - // 0x00002000 [13] OETOPAD (0) output enable to pad after register override is applied - // 0x00000200 [9] OUTTOPAD (0) output signal to pad after register override is applied - io_ro_32 status; - - _REG_(IO_QSPI_GPIO_QSPI_SCLK_CTRL_OFFSET) // IO_QSPI_GPIO_QSPI_SCLK_CTRL - // 0x30000000 [29:28] IRQOVER (0x0) - // 0x00030000 [17:16] INOVER (0x0) - // 0x0000c000 [15:14] OEOVER (0x0) - // 0x00003000 [13:12] OUTOVER (0x0) - // 0x0000001f [4:0] FUNCSEL (0x1f) 0-31 -> selects pin function according to the gpio table + - io_rw_32 ctrl; -} io_qspi_status_ctrl_hw_t; - -typedef struct { - _REG_(IO_QSPI_PROC0_INTE_OFFSET) // IO_QSPI_PROC0_INTE - // Interrupt Enable for proc0 - // 0x80000000 [31] GPIO_QSPI_SD3_EDGE_HIGH (0) - // 0x40000000 [30] GPIO_QSPI_SD3_EDGE_LOW (0) - // 0x20000000 [29] GPIO_QSPI_SD3_LEVEL_HIGH (0) - // 0x10000000 [28] GPIO_QSPI_SD3_LEVEL_LOW (0) - // 0x08000000 [27] GPIO_QSPI_SD2_EDGE_HIGH (0) - // 0x04000000 [26] GPIO_QSPI_SD2_EDGE_LOW (0) - // 0x02000000 [25] GPIO_QSPI_SD2_LEVEL_HIGH (0) - // 0x01000000 [24] GPIO_QSPI_SD2_LEVEL_LOW (0) - // 0x00800000 [23] GPIO_QSPI_SD1_EDGE_HIGH (0) - // 0x00400000 [22] GPIO_QSPI_SD1_EDGE_LOW (0) - // 0x00200000 [21] GPIO_QSPI_SD1_LEVEL_HIGH (0) - // 0x00100000 [20] GPIO_QSPI_SD1_LEVEL_LOW (0) - // 0x00080000 [19] GPIO_QSPI_SD0_EDGE_HIGH (0) - // 0x00040000 [18] GPIO_QSPI_SD0_EDGE_LOW (0) - // 0x00020000 [17] GPIO_QSPI_SD0_LEVEL_HIGH (0) - // 0x00010000 [16] GPIO_QSPI_SD0_LEVEL_LOW (0) - // 0x00008000 [15] GPIO_QSPI_SS_EDGE_HIGH (0) - // 0x00004000 [14] GPIO_QSPI_SS_EDGE_LOW (0) - // 0x00002000 [13] GPIO_QSPI_SS_LEVEL_HIGH (0) - // 0x00001000 [12] GPIO_QSPI_SS_LEVEL_LOW (0) - // 0x00000800 [11] GPIO_QSPI_SCLK_EDGE_HIGH (0) - // 0x00000400 [10] GPIO_QSPI_SCLK_EDGE_LOW (0) - // 0x00000200 [9] GPIO_QSPI_SCLK_LEVEL_HIGH (0) - // 0x00000100 [8] GPIO_QSPI_SCLK_LEVEL_LOW (0) - // 0x00000080 [7] USBPHY_DM_EDGE_HIGH (0) - // 0x00000040 [6] USBPHY_DM_EDGE_LOW (0) - // 0x00000020 [5] USBPHY_DM_LEVEL_HIGH (0) - // 0x00000010 [4] USBPHY_DM_LEVEL_LOW (0) - // 0x00000008 [3] USBPHY_DP_EDGE_HIGH (0) - // 0x00000004 [2] USBPHY_DP_EDGE_LOW (0) - // 0x00000002 [1] USBPHY_DP_LEVEL_HIGH (0) - // 0x00000001 [0] USBPHY_DP_LEVEL_LOW (0) - io_rw_32 inte; - - _REG_(IO_QSPI_PROC0_INTF_OFFSET) // IO_QSPI_PROC0_INTF - // Interrupt Force for proc0 - // 0x80000000 [31] GPIO_QSPI_SD3_EDGE_HIGH (0) - // 0x40000000 [30] GPIO_QSPI_SD3_EDGE_LOW (0) - // 0x20000000 [29] GPIO_QSPI_SD3_LEVEL_HIGH (0) - // 0x10000000 [28] GPIO_QSPI_SD3_LEVEL_LOW (0) - // 0x08000000 [27] GPIO_QSPI_SD2_EDGE_HIGH (0) - // 0x04000000 [26] GPIO_QSPI_SD2_EDGE_LOW (0) - // 0x02000000 [25] GPIO_QSPI_SD2_LEVEL_HIGH (0) - // 0x01000000 [24] GPIO_QSPI_SD2_LEVEL_LOW (0) - // 0x00800000 [23] GPIO_QSPI_SD1_EDGE_HIGH (0) - // 0x00400000 [22] GPIO_QSPI_SD1_EDGE_LOW (0) - // 0x00200000 [21] GPIO_QSPI_SD1_LEVEL_HIGH (0) - // 0x00100000 [20] GPIO_QSPI_SD1_LEVEL_LOW (0) - // 0x00080000 [19] GPIO_QSPI_SD0_EDGE_HIGH (0) - // 0x00040000 [18] GPIO_QSPI_SD0_EDGE_LOW (0) - // 0x00020000 [17] GPIO_QSPI_SD0_LEVEL_HIGH (0) - // 0x00010000 [16] GPIO_QSPI_SD0_LEVEL_LOW (0) - // 0x00008000 [15] GPIO_QSPI_SS_EDGE_HIGH (0) - // 0x00004000 [14] GPIO_QSPI_SS_EDGE_LOW (0) - // 0x00002000 [13] GPIO_QSPI_SS_LEVEL_HIGH (0) - // 0x00001000 [12] GPIO_QSPI_SS_LEVEL_LOW (0) - // 0x00000800 [11] GPIO_QSPI_SCLK_EDGE_HIGH (0) - // 0x00000400 [10] GPIO_QSPI_SCLK_EDGE_LOW (0) - // 0x00000200 [9] GPIO_QSPI_SCLK_LEVEL_HIGH (0) - // 0x00000100 [8] GPIO_QSPI_SCLK_LEVEL_LOW (0) - // 0x00000080 [7] USBPHY_DM_EDGE_HIGH (0) - // 0x00000040 [6] USBPHY_DM_EDGE_LOW (0) - // 0x00000020 [5] USBPHY_DM_LEVEL_HIGH (0) - // 0x00000010 [4] USBPHY_DM_LEVEL_LOW (0) - // 0x00000008 [3] USBPHY_DP_EDGE_HIGH (0) - // 0x00000004 [2] USBPHY_DP_EDGE_LOW (0) - // 0x00000002 [1] USBPHY_DP_LEVEL_HIGH (0) - // 0x00000001 [0] USBPHY_DP_LEVEL_LOW (0) - io_rw_32 intf; - - _REG_(IO_QSPI_PROC0_INTS_OFFSET) // IO_QSPI_PROC0_INTS - // Interrupt status after masking & forcing for proc0 - // 0x80000000 [31] GPIO_QSPI_SD3_EDGE_HIGH (0) - // 0x40000000 [30] GPIO_QSPI_SD3_EDGE_LOW (0) - // 0x20000000 [29] GPIO_QSPI_SD3_LEVEL_HIGH (0) - // 0x10000000 [28] GPIO_QSPI_SD3_LEVEL_LOW (0) - // 0x08000000 [27] GPIO_QSPI_SD2_EDGE_HIGH (0) - // 0x04000000 [26] GPIO_QSPI_SD2_EDGE_LOW (0) - // 0x02000000 [25] GPIO_QSPI_SD2_LEVEL_HIGH (0) - // 0x01000000 [24] GPIO_QSPI_SD2_LEVEL_LOW (0) - // 0x00800000 [23] GPIO_QSPI_SD1_EDGE_HIGH (0) - // 0x00400000 [22] GPIO_QSPI_SD1_EDGE_LOW (0) - // 0x00200000 [21] GPIO_QSPI_SD1_LEVEL_HIGH (0) - // 0x00100000 [20] GPIO_QSPI_SD1_LEVEL_LOW (0) - // 0x00080000 [19] GPIO_QSPI_SD0_EDGE_HIGH (0) - // 0x00040000 [18] GPIO_QSPI_SD0_EDGE_LOW (0) - // 0x00020000 [17] GPIO_QSPI_SD0_LEVEL_HIGH (0) - // 0x00010000 [16] GPIO_QSPI_SD0_LEVEL_LOW (0) - // 0x00008000 [15] GPIO_QSPI_SS_EDGE_HIGH (0) - // 0x00004000 [14] GPIO_QSPI_SS_EDGE_LOW (0) - // 0x00002000 [13] GPIO_QSPI_SS_LEVEL_HIGH (0) - // 0x00001000 [12] GPIO_QSPI_SS_LEVEL_LOW (0) - // 0x00000800 [11] GPIO_QSPI_SCLK_EDGE_HIGH (0) - // 0x00000400 [10] GPIO_QSPI_SCLK_EDGE_LOW (0) - // 0x00000200 [9] GPIO_QSPI_SCLK_LEVEL_HIGH (0) - // 0x00000100 [8] GPIO_QSPI_SCLK_LEVEL_LOW (0) - // 0x00000080 [7] USBPHY_DM_EDGE_HIGH (0) - // 0x00000040 [6] USBPHY_DM_EDGE_LOW (0) - // 0x00000020 [5] USBPHY_DM_LEVEL_HIGH (0) - // 0x00000010 [4] USBPHY_DM_LEVEL_LOW (0) - // 0x00000008 [3] USBPHY_DP_EDGE_HIGH (0) - // 0x00000004 [2] USBPHY_DP_EDGE_LOW (0) - // 0x00000002 [1] USBPHY_DP_LEVEL_HIGH (0) - // 0x00000001 [0] USBPHY_DP_LEVEL_LOW (0) - io_ro_32 ints; -} io_qspi_irq_ctrl_hw_t; - -typedef struct { - _REG_(IO_QSPI_USBPHY_DP_STATUS_OFFSET) // IO_QSPI_USBPHY_DP_STATUS - // 0x04000000 [26] IRQTOPROC (0) interrupt to processors, after override is applied - // 0x00020000 [17] INFROMPAD (0) input signal from pad, before filtering and override are applied - // 0x00002000 [13] OETOPAD (0) output enable to pad after register override is applied - // 0x00000200 [9] OUTTOPAD (0) output signal to pad after register override is applied - io_ro_32 usbphy_dp_status; - - _REG_(IO_QSPI_USBPHY_DP_CTRL_OFFSET) // IO_QSPI_USBPHY_DP_CTRL - // 0x30000000 [29:28] IRQOVER (0x0) - // 0x00030000 [17:16] INOVER (0x0) - // 0x0000c000 [15:14] OEOVER (0x0) - // 0x00003000 [13:12] OUTOVER (0x0) - // 0x0000001f [4:0] FUNCSEL (0x1f) 0-31 -> selects pin function according to the gpio table + - io_rw_32 usbphy_dp_ctrl; - - _REG_(IO_QSPI_USBPHY_DM_STATUS_OFFSET) // IO_QSPI_USBPHY_DM_STATUS - // 0x04000000 [26] IRQTOPROC (0) interrupt to processors, after override is applied - // 0x00020000 [17] INFROMPAD (0) input signal from pad, before filtering and override are applied - // 0x00002000 [13] OETOPAD (0) output enable to pad after register override is applied - // 0x00000200 [9] OUTTOPAD (0) output signal to pad after register override is applied - io_ro_32 usbphy_dm_status; - - _REG_(IO_QSPI_USBPHY_DM_CTRL_OFFSET) // IO_QSPI_USBPHY_DM_CTRL - // 0x30000000 [29:28] IRQOVER (0x0) - // 0x00030000 [17:16] INOVER (0x0) - // 0x0000c000 [15:14] OEOVER (0x0) - // 0x00003000 [13:12] OUTOVER (0x0) - // 0x0000001f [4:0] FUNCSEL (0x1f) 0-31 -> selects pin function according to the gpio table + - io_rw_32 usbphy_dm_ctrl; - - io_qspi_status_ctrl_hw_t io[6]; - - uint32_t _pad0[112]; - - _REG_(IO_QSPI_IRQSUMMARY_PROC0_SECURE_OFFSET) // IO_QSPI_IRQSUMMARY_PROC0_SECURE - // 0x00000080 [7] GPIO_QSPI_SD3 (0) - // 0x00000040 [6] GPIO_QSPI_SD2 (0) - // 0x00000020 [5] GPIO_QSPI_SD1 (0) - // 0x00000010 [4] GPIO_QSPI_SD0 (0) - // 0x00000008 [3] GPIO_QSPI_SS (0) - // 0x00000004 [2] GPIO_QSPI_SCLK (0) - // 0x00000002 [1] USBPHY_DM (0) - // 0x00000001 [0] USBPHY_DP (0) - io_ro_32 irqsummary_proc0_secure; - - _REG_(IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_OFFSET) // IO_QSPI_IRQSUMMARY_PROC0_NONSECURE - // 0x00000080 [7] GPIO_QSPI_SD3 (0) - // 0x00000040 [6] GPIO_QSPI_SD2 (0) - // 0x00000020 [5] GPIO_QSPI_SD1 (0) - // 0x00000010 [4] GPIO_QSPI_SD0 (0) - // 0x00000008 [3] GPIO_QSPI_SS (0) - // 0x00000004 [2] GPIO_QSPI_SCLK (0) - // 0x00000002 [1] USBPHY_DM (0) - // 0x00000001 [0] USBPHY_DP (0) - io_ro_32 irqsummary_proc0_nonsecure; - - _REG_(IO_QSPI_IRQSUMMARY_PROC1_SECURE_OFFSET) // IO_QSPI_IRQSUMMARY_PROC1_SECURE - // 0x00000080 [7] GPIO_QSPI_SD3 (0) - // 0x00000040 [6] GPIO_QSPI_SD2 (0) - // 0x00000020 [5] GPIO_QSPI_SD1 (0) - // 0x00000010 [4] GPIO_QSPI_SD0 (0) - // 0x00000008 [3] GPIO_QSPI_SS (0) - // 0x00000004 [2] GPIO_QSPI_SCLK (0) - // 0x00000002 [1] USBPHY_DM (0) - // 0x00000001 [0] USBPHY_DP (0) - io_ro_32 irqsummary_proc1_secure; - - _REG_(IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_OFFSET) // IO_QSPI_IRQSUMMARY_PROC1_NONSECURE - // 0x00000080 [7] GPIO_QSPI_SD3 (0) - // 0x00000040 [6] GPIO_QSPI_SD2 (0) - // 0x00000020 [5] GPIO_QSPI_SD1 (0) - // 0x00000010 [4] GPIO_QSPI_SD0 (0) - // 0x00000008 [3] GPIO_QSPI_SS (0) - // 0x00000004 [2] GPIO_QSPI_SCLK (0) - // 0x00000002 [1] USBPHY_DM (0) - // 0x00000001 [0] USBPHY_DP (0) - io_ro_32 irqsummary_proc1_nonsecure; - - _REG_(IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_OFFSET) // IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE - // 0x00000080 [7] GPIO_QSPI_SD3 (0) - // 0x00000040 [6] GPIO_QSPI_SD2 (0) - // 0x00000020 [5] GPIO_QSPI_SD1 (0) - // 0x00000010 [4] GPIO_QSPI_SD0 (0) - // 0x00000008 [3] GPIO_QSPI_SS (0) - // 0x00000004 [2] GPIO_QSPI_SCLK (0) - // 0x00000002 [1] USBPHY_DM (0) - // 0x00000001 [0] USBPHY_DP (0) - io_ro_32 irqsummary_dormant_wake_secure; - - _REG_(IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_OFFSET) // IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE - // 0x00000080 [7] GPIO_QSPI_SD3 (0) - // 0x00000040 [6] GPIO_QSPI_SD2 (0) - // 0x00000020 [5] GPIO_QSPI_SD1 (0) - // 0x00000010 [4] GPIO_QSPI_SD0 (0) - // 0x00000008 [3] GPIO_QSPI_SS (0) - // 0x00000004 [2] GPIO_QSPI_SCLK (0) - // 0x00000002 [1] USBPHY_DM (0) - // 0x00000001 [0] USBPHY_DP (0) - io_ro_32 irqsummary_dormant_wake_nonsecure; - - _REG_(IO_QSPI_INTR_OFFSET) // IO_QSPI_INTR - // Raw Interrupts - // 0x80000000 [31] GPIO_QSPI_SD3_EDGE_HIGH (0) - // 0x40000000 [30] GPIO_QSPI_SD3_EDGE_LOW (0) - // 0x20000000 [29] GPIO_QSPI_SD3_LEVEL_HIGH (0) - // 0x10000000 [28] GPIO_QSPI_SD3_LEVEL_LOW (0) - // 0x08000000 [27] GPIO_QSPI_SD2_EDGE_HIGH (0) - // 0x04000000 [26] GPIO_QSPI_SD2_EDGE_LOW (0) - // 0x02000000 [25] GPIO_QSPI_SD2_LEVEL_HIGH (0) - // 0x01000000 [24] GPIO_QSPI_SD2_LEVEL_LOW (0) - // 0x00800000 [23] GPIO_QSPI_SD1_EDGE_HIGH (0) - // 0x00400000 [22] GPIO_QSPI_SD1_EDGE_LOW (0) - // 0x00200000 [21] GPIO_QSPI_SD1_LEVEL_HIGH (0) - // 0x00100000 [20] GPIO_QSPI_SD1_LEVEL_LOW (0) - // 0x00080000 [19] GPIO_QSPI_SD0_EDGE_HIGH (0) - // 0x00040000 [18] GPIO_QSPI_SD0_EDGE_LOW (0) - // 0x00020000 [17] GPIO_QSPI_SD0_LEVEL_HIGH (0) - // 0x00010000 [16] GPIO_QSPI_SD0_LEVEL_LOW (0) - // 0x00008000 [15] GPIO_QSPI_SS_EDGE_HIGH (0) - // 0x00004000 [14] GPIO_QSPI_SS_EDGE_LOW (0) - // 0x00002000 [13] GPIO_QSPI_SS_LEVEL_HIGH (0) - // 0x00001000 [12] GPIO_QSPI_SS_LEVEL_LOW (0) - // 0x00000800 [11] GPIO_QSPI_SCLK_EDGE_HIGH (0) - // 0x00000400 [10] GPIO_QSPI_SCLK_EDGE_LOW (0) - // 0x00000200 [9] GPIO_QSPI_SCLK_LEVEL_HIGH (0) - // 0x00000100 [8] GPIO_QSPI_SCLK_LEVEL_LOW (0) - // 0x00000080 [7] USBPHY_DM_EDGE_HIGH (0) - // 0x00000040 [6] USBPHY_DM_EDGE_LOW (0) - // 0x00000020 [5] USBPHY_DM_LEVEL_HIGH (0) - // 0x00000010 [4] USBPHY_DM_LEVEL_LOW (0) - // 0x00000008 [3] USBPHY_DP_EDGE_HIGH (0) - // 0x00000004 [2] USBPHY_DP_EDGE_LOW (0) - // 0x00000002 [1] USBPHY_DP_LEVEL_HIGH (0) - // 0x00000001 [0] USBPHY_DP_LEVEL_LOW (0) - io_rw_32 intr; - - union { - struct { - io_qspi_irq_ctrl_hw_t proc0_irq_ctrl; - io_qspi_irq_ctrl_hw_t proc1_irq_ctrl; - io_qspi_irq_ctrl_hw_t dormant_wake_irq_ctrl; - }; - io_qspi_irq_ctrl_hw_t irq_ctrl[3]; - }; -} io_qspi_hw_t; - -#define io_qspi_hw ((io_qspi_hw_t *)IO_QSPI_BASE) -static_assert(sizeof (io_qspi_hw_t) == 0x0240, ""); - -#endif // _HARDWARE_STRUCTS_IO_QSPI_H - diff --git a/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/iobank0.h b/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/iobank0.h deleted file mode 100644 index 2dc31e38d4..0000000000 --- a/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/iobank0.h +++ /dev/null @@ -1,9 +0,0 @@ -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -// Support old header for compatibility (and if included, support old variable name) -#include "hardware/structs/io_bank0.h" -#define iobank0_hw io_bank0_hw \ No newline at end of file diff --git a/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/ioqspi.h b/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/ioqspi.h deleted file mode 100644 index 20cc74c79b..0000000000 --- a/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/ioqspi.h +++ /dev/null @@ -1,9 +0,0 @@ -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -// Support old header for compatibility (and if included, support old variable name) -#include "hardware/structs/io_qspi.h" -#define ioqspi_hw io_qspi_hw \ No newline at end of file diff --git a/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/m33.h b/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/m33.h deleted file mode 100644 index d527c917fa..0000000000 --- a/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/m33.h +++ /dev/null @@ -1,1651 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _HARDWARE_STRUCTS_M33_H -#define _HARDWARE_STRUCTS_M33_H - -/** - * \file rp2350/m33.h - */ - -#include "hardware/address_mapped.h" -#include "hardware/regs/m33.h" - -// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_m33 -// -// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) -// _REG_(x) will link to the corresponding register in hardware/regs/m33.h. -// -// Bit-field descriptions are of the form: -// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION - -#if defined(__riscv) && PICO_FORBID_ARM_HEADERS_ON_RISCV -#error "Arm header included in a RISC-V build with PICO_FORBID_ARM_HEADERS_ON_RISCV=1" -#endif - -typedef struct { - // (Description copied from array index 0 register M33_ITM_STIM0 applies similarly to other array indexes) - _REG_(M33_ITM_STIM0_OFFSET) // M33_ITM_STIM0 - // ITM Stimulus Port Register 0 - // 0xffffffff [31:0] STIMULUS (0x00000000) Data to write to the Stimulus Port FIFO, for forwarding... - io_rw_32 itm_stim[32]; - - uint32_t _pad0[864]; - - _REG_(M33_ITM_TER0_OFFSET) // M33_ITM_TER0 - // Provide an individual enable bit for each ITM_STIM register - // 0xffffffff [31:0] STIMENA (0x00000000) For STIMENA[m] in ITM_TER*n, controls whether... - io_rw_32 itm_ter0; - - uint32_t _pad1[15]; - - _REG_(M33_ITM_TPR_OFFSET) // M33_ITM_TPR - // Controls which stimulus ports can be accessed by unprivileged code - // 0x0000000f [3:0] PRIVMASK (0x0) Bit mask to enable tracing on ITM stimulus ports - io_rw_32 itm_tpr; - - uint32_t _pad2[15]; - - _REG_(M33_ITM_TCR_OFFSET) // M33_ITM_TCR - // Configures and controls transfers through the ITM interface - // 0x00800000 [23] BUSY (0) Indicates whether the ITM is currently processing events - // 0x007f0000 [22:16] TRACEBUSID (0x00) Identifier for multi-source trace stream formatting - // 0x00000c00 [11:10] GTSFREQ (0x0) Defines how often the ITM generates a global timestamp,... - // 0x00000300 [9:8] TSPRESCALE (0x0) Local timestamp prescaler, used with the trace packet... - // 0x00000020 [5] STALLENA (0) Stall the PE to guarantee delivery of Data Trace packets - // 0x00000010 [4] SWOENA (0) Enables asynchronous clocking of the timestamp counter - // 0x00000008 [3] TXENA (0) Enables forwarding of hardware event packet from the DWT... - // 0x00000004 [2] SYNCENA (0) Enables Synchronization packet transmission for a... - // 0x00000002 [1] TSENA (0) Enables Local timestamp generation - // 0x00000001 [0] ITMENA (0) Enables the ITM - io_rw_32 itm_tcr; - - uint32_t _pad3[27]; - - _REG_(M33_INT_ATREADY_OFFSET) // M33_INT_ATREADY - // Integration Mode: Read ATB Ready - // 0x00000002 [1] AFVALID (0) A read of this bit returns the value of AFVALID - // 0x00000001 [0] ATREADY (0) A read of this bit returns the value of ATREADY - io_ro_32 int_atready; - - uint32_t _pad4; - - _REG_(M33_INT_ATVALID_OFFSET) // M33_INT_ATVALID - // Integration Mode: Write ATB Valid - // 0x00000002 [1] AFREADY (0) A write to this bit gives the value of AFREADY - // 0x00000001 [0] ATREADY (0) A write to this bit gives the value of ATVALID - io_rw_32 int_atvalid; - - uint32_t _pad5; - - _REG_(M33_ITM_ITCTRL_OFFSET) // M33_ITM_ITCTRL - // Integration Mode Control Register - // 0x00000001 [0] IME (0) Integration mode enable bit - The possible values are: ... - io_rw_32 itm_itctrl; - - uint32_t _pad6[46]; - - _REG_(M33_ITM_DEVARCH_OFFSET) // M33_ITM_DEVARCH - // Provides CoreSight discovery information for the ITM - // 0xffe00000 [31:21] ARCHITECT (0x23b) Defines the architect of the component - // 0x00100000 [20] PRESENT (1) Defines that the DEVARCH register is present - // 0x000f0000 [19:16] REVISION (0x0) Defines the architecture revision of the component - // 0x0000f000 [15:12] ARCHVER (0x1) Defines the architecture version of the component - // 0x00000fff [11:0] ARCHPART (0xa01) Defines the architecture of the component - io_ro_32 itm_devarch; - - uint32_t _pad7[3]; - - _REG_(M33_ITM_DEVTYPE_OFFSET) // M33_ITM_DEVTYPE - // Provides CoreSight discovery information for the ITM - // 0x000000f0 [7:4] SUB (0x4) Component sub-type - // 0x0000000f [3:0] MAJOR (0x3) Component major type - io_ro_32 itm_devtype; - - _REG_(M33_ITM_PIDR4_OFFSET) // M33_ITM_PIDR4 - // Provides CoreSight discovery information for the ITM - // 0x000000f0 [7:4] SIZE (0x0) See CoreSight Architecture Specification - // 0x0000000f [3:0] DES_2 (0x4) See CoreSight Architecture Specification - io_ro_32 itm_pidr4; - - _REG_(M33_ITM_PIDR5_OFFSET) // M33_ITM_PIDR5 - // Provides CoreSight discovery information for the ITM - // 0x00000000 [31:0] ITM_PIDR5 (0x00000000) - io_rw_32 itm_pidr5; - - _REG_(M33_ITM_PIDR6_OFFSET) // M33_ITM_PIDR6 - // Provides CoreSight discovery information for the ITM - // 0x00000000 [31:0] ITM_PIDR6 (0x00000000) - io_rw_32 itm_pidr6; - - _REG_(M33_ITM_PIDR7_OFFSET) // M33_ITM_PIDR7 - // Provides CoreSight discovery information for the ITM - // 0x00000000 [31:0] ITM_PIDR7 (0x00000000) - io_rw_32 itm_pidr7; - - _REG_(M33_ITM_PIDR0_OFFSET) // M33_ITM_PIDR0 - // Provides CoreSight discovery information for the ITM - // 0x000000ff [7:0] PART_0 (0x21) See CoreSight Architecture Specification - io_ro_32 itm_pidr0; - - _REG_(M33_ITM_PIDR1_OFFSET) // M33_ITM_PIDR1 - // Provides CoreSight discovery information for the ITM - // 0x000000f0 [7:4] DES_0 (0xb) See CoreSight Architecture Specification - // 0x0000000f [3:0] PART_1 (0xd) See CoreSight Architecture Specification - io_ro_32 itm_pidr1; - - _REG_(M33_ITM_PIDR2_OFFSET) // M33_ITM_PIDR2 - // Provides CoreSight discovery information for the ITM - // 0x000000f0 [7:4] REVISION (0x0) See CoreSight Architecture Specification - // 0x00000008 [3] JEDEC (1) See CoreSight Architecture Specification - // 0x00000007 [2:0] DES_1 (0x3) See CoreSight Architecture Specification - io_ro_32 itm_pidr2; - - _REG_(M33_ITM_PIDR3_OFFSET) // M33_ITM_PIDR3 - // Provides CoreSight discovery information for the ITM - // 0x000000f0 [7:4] REVAND (0x0) See CoreSight Architecture Specification - // 0x0000000f [3:0] CMOD (0x0) See CoreSight Architecture Specification - io_ro_32 itm_pidr3; - - // (Description copied from array index 0 register M33_ITM_CIDR0 applies similarly to other array indexes) - _REG_(M33_ITM_CIDR0_OFFSET) // M33_ITM_CIDR0 - // Provides CoreSight discovery information for the ITM - // 0x000000ff [7:0] PRMBL_0 (0x0d) See CoreSight Architecture Specification - io_ro_32 itm_cidr[4]; - - _REG_(M33_DWT_CTRL_OFFSET) // M33_DWT_CTRL - // Provides configuration and status information for the DWT unit, and used to control features of the unit - // 0xf0000000 [31:28] NUMCOMP (0x7) Number of DWT comparators implemented - // 0x08000000 [27] NOTRCPKT (0) Indicates whether the implementation does not support trace - // 0x04000000 [26] NOEXTTRIG (0) Reserved, RAZ - // 0x02000000 [25] NOCYCCNT (1) Indicates whether the implementation does not include a... - // 0x01000000 [24] NOPRFCNT (1) Indicates whether the implementation does not include... - // 0x00800000 [23] CYCDISS (0) Controls whether the cycle counter is disabled in Secure state - // 0x00400000 [22] CYCEVTENA (1) Enables Event Counter packet generation on POSTCNT underflow - // 0x00200000 [21] FOLDEVTENA (1) Enables DWT_FOLDCNT counter - // 0x00100000 [20] LSUEVTENA (1) Enables DWT_LSUCNT counter - // 0x00080000 [19] SLEEPEVTENA (0) Enable DWT_SLEEPCNT counter - // 0x00040000 [18] EXCEVTENA (1) Enables DWT_EXCCNT counter - // 0x00020000 [17] CPIEVTENA (0) Enables DWT_CPICNT counter - // 0x00010000 [16] EXTTRCENA (0) Enables generation of Exception Trace packets - // 0x00001000 [12] PCSAMPLENA (1) Enables use of POSTCNT counter as a timer for Periodic... - // 0x00000c00 [11:10] SYNCTAP (0x2) Selects the position of the synchronization packet... - // 0x00000200 [9] CYCTAP (0) Selects the position of the POSTCNT tap on the CYCCNT counter - // 0x000001e0 [8:5] POSTINIT (0x1) Initial value for the POSTCNT counter - // 0x0000001e [4:1] POSTPRESET (0x2) Reload value for the POSTCNT counter - // 0x00000001 [0] CYCCNTENA (0) Enables CYCCNT - io_rw_32 dwt_ctrl; - - _REG_(M33_DWT_CYCCNT_OFFSET) // M33_DWT_CYCCNT - // Shows or sets the value of the processor cycle counter, CYCCNT - // 0xffffffff [31:0] CYCCNT (0x00000000) Increments one on each processor clock cycle when DWT_CTRL - io_rw_32 dwt_cyccnt; - - uint32_t _pad8; - - _REG_(M33_DWT_EXCCNT_OFFSET) // M33_DWT_EXCCNT - // Counts the total cycles spent in exception processing - // 0x000000ff [7:0] EXCCNT (0x00) Counts one on each cycle when all of the following are... - io_rw_32 dwt_exccnt; - - uint32_t _pad9; - - _REG_(M33_DWT_LSUCNT_OFFSET) // M33_DWT_LSUCNT - // Increments on the additional cycles required to execute all load or store instructions - // 0x000000ff [7:0] LSUCNT (0x00) Counts one on each cycle when all of the following are... - io_rw_32 dwt_lsucnt; - - _REG_(M33_DWT_FOLDCNT_OFFSET) // M33_DWT_FOLDCNT - // Increments on the additional cycles required to execute all load or store instructions - // 0x000000ff [7:0] FOLDCNT (0x00) Counts on each cycle when all of the following are true:... - io_rw_32 dwt_foldcnt; - - uint32_t _pad10; - - _REG_(M33_DWT_COMP0_OFFSET) // M33_DWT_COMP0 - // Provides a reference value for use by watchpoint comparator 0 - // 0xffffffff [31:0] DWT_COMP0 (0x00000000) - io_rw_32 dwt_comp0; - - uint32_t _pad11; - - _REG_(M33_DWT_FUNCTION0_OFFSET) // M33_DWT_FUNCTION0 - // Controls the operation of watchpoint comparator 0 - // 0xf8000000 [31:27] ID (0x0b) Identifies the capabilities for MATCH for comparator *n - // 0x01000000 [24] MATCHED (0) Set to 1 when the comparator matches - // 0x00000c00 [11:10] DATAVSIZE (0x0) Defines the size of the object being watched for by Data... - // 0x00000030 [5:4] ACTION (0x0) Defines the action on a match - // 0x0000000f [3:0] MATCH (0x0) Controls the type of match generated by this comparator - io_rw_32 dwt_function0; - - uint32_t _pad12; - - _REG_(M33_DWT_COMP1_OFFSET) // M33_DWT_COMP1 - // Provides a reference value for use by watchpoint comparator 1 - // 0xffffffff [31:0] DWT_COMP1 (0x00000000) - io_rw_32 dwt_comp1; - - uint32_t _pad13; - - _REG_(M33_DWT_FUNCTION1_OFFSET) // M33_DWT_FUNCTION1 - // Controls the operation of watchpoint comparator 1 - // 0xf8000000 [31:27] ID (0x11) Identifies the capabilities for MATCH for comparator *n - // 0x01000000 [24] MATCHED (1) Set to 1 when the comparator matches - // 0x00000c00 [11:10] DATAVSIZE (0x2) Defines the size of the object being watched for by Data... - // 0x00000030 [5:4] ACTION (0x2) Defines the action on a match - // 0x0000000f [3:0] MATCH (0x8) Controls the type of match generated by this comparator - io_rw_32 dwt_function1; - - uint32_t _pad14; - - _REG_(M33_DWT_COMP2_OFFSET) // M33_DWT_COMP2 - // Provides a reference value for use by watchpoint comparator 2 - // 0xffffffff [31:0] DWT_COMP2 (0x00000000) - io_rw_32 dwt_comp2; - - uint32_t _pad15; - - _REG_(M33_DWT_FUNCTION2_OFFSET) // M33_DWT_FUNCTION2 - // Controls the operation of watchpoint comparator 2 - // 0xf8000000 [31:27] ID (0x0a) Identifies the capabilities for MATCH for comparator *n - // 0x01000000 [24] MATCHED (0) Set to 1 when the comparator matches - // 0x00000c00 [11:10] DATAVSIZE (0x0) Defines the size of the object being watched for by Data... - // 0x00000030 [5:4] ACTION (0x0) Defines the action on a match - // 0x0000000f [3:0] MATCH (0x0) Controls the type of match generated by this comparator - io_rw_32 dwt_function2; - - uint32_t _pad16; - - _REG_(M33_DWT_COMP3_OFFSET) // M33_DWT_COMP3 - // Provides a reference value for use by watchpoint comparator 3 - // 0xffffffff [31:0] DWT_COMP3 (0x00000000) - io_rw_32 dwt_comp3; - - uint32_t _pad17; - - _REG_(M33_DWT_FUNCTION3_OFFSET) // M33_DWT_FUNCTION3 - // Controls the operation of watchpoint comparator 3 - // 0xf8000000 [31:27] ID (0x04) Identifies the capabilities for MATCH for comparator *n - // 0x01000000 [24] MATCHED (0) Set to 1 when the comparator matches - // 0x00000c00 [11:10] DATAVSIZE (0x2) Defines the size of the object being watched for by Data... - // 0x00000030 [5:4] ACTION (0x0) Defines the action on a match - // 0x0000000f [3:0] MATCH (0x0) Controls the type of match generated by this comparator - io_rw_32 dwt_function3; - - uint32_t _pad18[984]; - - _REG_(M33_DWT_DEVARCH_OFFSET) // M33_DWT_DEVARCH - // Provides CoreSight discovery information for the DWT - // 0xffe00000 [31:21] ARCHITECT (0x23b) Defines the architect of the component - // 0x00100000 [20] PRESENT (1) Defines that the DEVARCH register is present - // 0x000f0000 [19:16] REVISION (0x0) Defines the architecture revision of the component - // 0x0000f000 [15:12] ARCHVER (0x1) Defines the architecture version of the component - // 0x00000fff [11:0] ARCHPART (0xa02) Defines the architecture of the component - io_ro_32 dwt_devarch; - - uint32_t _pad19[3]; - - _REG_(M33_DWT_DEVTYPE_OFFSET) // M33_DWT_DEVTYPE - // Provides CoreSight discovery information for the DWT - // 0x000000f0 [7:4] SUB (0x0) Component sub-type - // 0x0000000f [3:0] MAJOR (0x0) Component major type - io_ro_32 dwt_devtype; - - _REG_(M33_DWT_PIDR4_OFFSET) // M33_DWT_PIDR4 - // Provides CoreSight discovery information for the DWT - // 0x000000f0 [7:4] SIZE (0x0) See CoreSight Architecture Specification - // 0x0000000f [3:0] DES_2 (0x4) See CoreSight Architecture Specification - io_ro_32 dwt_pidr4; - - _REG_(M33_DWT_PIDR5_OFFSET) // M33_DWT_PIDR5 - // Provides CoreSight discovery information for the DWT - // 0x00000000 [31:0] DWT_PIDR5 (0x00000000) - io_rw_32 dwt_pidr5; - - _REG_(M33_DWT_PIDR6_OFFSET) // M33_DWT_PIDR6 - // Provides CoreSight discovery information for the DWT - // 0x00000000 [31:0] DWT_PIDR6 (0x00000000) - io_rw_32 dwt_pidr6; - - _REG_(M33_DWT_PIDR7_OFFSET) // M33_DWT_PIDR7 - // Provides CoreSight discovery information for the DWT - // 0x00000000 [31:0] DWT_PIDR7 (0x00000000) - io_rw_32 dwt_pidr7; - - _REG_(M33_DWT_PIDR0_OFFSET) // M33_DWT_PIDR0 - // Provides CoreSight discovery information for the DWT - // 0x000000ff [7:0] PART_0 (0x21) See CoreSight Architecture Specification - io_ro_32 dwt_pidr0; - - _REG_(M33_DWT_PIDR1_OFFSET) // M33_DWT_PIDR1 - // Provides CoreSight discovery information for the DWT - // 0x000000f0 [7:4] DES_0 (0xb) See CoreSight Architecture Specification - // 0x0000000f [3:0] PART_1 (0xd) See CoreSight Architecture Specification - io_ro_32 dwt_pidr1; - - _REG_(M33_DWT_PIDR2_OFFSET) // M33_DWT_PIDR2 - // Provides CoreSight discovery information for the DWT - // 0x000000f0 [7:4] REVISION (0x0) See CoreSight Architecture Specification - // 0x00000008 [3] JEDEC (1) See CoreSight Architecture Specification - // 0x00000007 [2:0] DES_1 (0x3) See CoreSight Architecture Specification - io_ro_32 dwt_pidr2; - - _REG_(M33_DWT_PIDR3_OFFSET) // M33_DWT_PIDR3 - // Provides CoreSight discovery information for the DWT - // 0x000000f0 [7:4] REVAND (0x0) See CoreSight Architecture Specification - // 0x0000000f [3:0] CMOD (0x0) See CoreSight Architecture Specification - io_ro_32 dwt_pidr3; - - // (Description copied from array index 0 register M33_DWT_CIDR0 applies similarly to other array indexes) - _REG_(M33_DWT_CIDR0_OFFSET) // M33_DWT_CIDR0 - // Provides CoreSight discovery information for the DWT - // 0x000000ff [7:0] PRMBL_0 (0x0d) See CoreSight Architecture Specification - io_ro_32 dwt_cidr[4]; - - _REG_(M33_FP_CTRL_OFFSET) // M33_FP_CTRL - // Provides FPB implementation information, and the global enable for the FPB unit - // 0xf0000000 [31:28] REV (0x6) Flash Patch and Breakpoint Unit architecture revision - // 0x00007000 [14:12] NUM_CODE_14_12_ (0x5) Indicates the number of implemented instruction address... - // 0x00000f00 [11:8] NUM_LIT (0x5) Indicates the number of implemented literal address comparators - // 0x000000f0 [7:4] NUM_CODE_7_4_ (0x8) Indicates the number of implemented instruction address... - // 0x00000002 [1] KEY (0) Writes to the FP_CTRL are ignored unless KEY is... - // 0x00000001 [0] ENABLE (0) Enables the FPB - io_rw_32 fp_ctrl; - - _REG_(M33_FP_REMAP_OFFSET) // M33_FP_REMAP - // Indicates whether the implementation supports Flash Patch remap and, if it does, holds the... - // 0x20000000 [29] RMPSPT (0) Indicates whether the FPB unit supports the Flash Patch... - // 0x1fffffe0 [28:5] REMAP (0x000000) Holds the bits[28:5] of the Flash Patch remap address - io_ro_32 fp_remap; - - // (Description copied from array index 0 register M33_FP_COMP0 applies similarly to other array indexes) - _REG_(M33_FP_COMP0_OFFSET) // M33_FP_COMP0 - // Holds an address for comparison - // 0x00000001 [0] BE (0) Selects between flashpatch and breakpoint functionality - io_rw_32 fp_comp[8]; - - uint32_t _pad20[997]; - - _REG_(M33_FP_DEVARCH_OFFSET) // M33_FP_DEVARCH - // Provides CoreSight discovery information for the FPB - // 0xffe00000 [31:21] ARCHITECT (0x23b) Defines the architect of the component - // 0x00100000 [20] PRESENT (1) Defines that the DEVARCH register is present - // 0x000f0000 [19:16] REVISION (0x0) Defines the architecture revision of the component - // 0x0000f000 [15:12] ARCHVER (0x1) Defines the architecture version of the component - // 0x00000fff [11:0] ARCHPART (0xa03) Defines the architecture of the component - io_ro_32 fp_devarch; - - uint32_t _pad21[3]; - - _REG_(M33_FP_DEVTYPE_OFFSET) // M33_FP_DEVTYPE - // Provides CoreSight discovery information for the FPB - // 0x000000f0 [7:4] SUB (0x0) Component sub-type - // 0x0000000f [3:0] MAJOR (0x0) Component major type - io_ro_32 fp_devtype; - - _REG_(M33_FP_PIDR4_OFFSET) // M33_FP_PIDR4 - // Provides CoreSight discovery information for the FP - // 0x000000f0 [7:4] SIZE (0x0) See CoreSight Architecture Specification - // 0x0000000f [3:0] DES_2 (0x4) See CoreSight Architecture Specification - io_ro_32 fp_pidr4; - - _REG_(M33_FP_PIDR5_OFFSET) // M33_FP_PIDR5 - // Provides CoreSight discovery information for the FP - // 0x00000000 [31:0] FP_PIDR5 (0x00000000) - io_rw_32 fp_pidr5; - - _REG_(M33_FP_PIDR6_OFFSET) // M33_FP_PIDR6 - // Provides CoreSight discovery information for the FP - // 0x00000000 [31:0] FP_PIDR6 (0x00000000) - io_rw_32 fp_pidr6; - - _REG_(M33_FP_PIDR7_OFFSET) // M33_FP_PIDR7 - // Provides CoreSight discovery information for the FP - // 0x00000000 [31:0] FP_PIDR7 (0x00000000) - io_rw_32 fp_pidr7; - - _REG_(M33_FP_PIDR0_OFFSET) // M33_FP_PIDR0 - // Provides CoreSight discovery information for the FP - // 0x000000ff [7:0] PART_0 (0x21) See CoreSight Architecture Specification - io_ro_32 fp_pidr0; - - _REG_(M33_FP_PIDR1_OFFSET) // M33_FP_PIDR1 - // Provides CoreSight discovery information for the FP - // 0x000000f0 [7:4] DES_0 (0xb) See CoreSight Architecture Specification - // 0x0000000f [3:0] PART_1 (0xd) See CoreSight Architecture Specification - io_ro_32 fp_pidr1; - - _REG_(M33_FP_PIDR2_OFFSET) // M33_FP_PIDR2 - // Provides CoreSight discovery information for the FP - // 0x000000f0 [7:4] REVISION (0x0) See CoreSight Architecture Specification - // 0x00000008 [3] JEDEC (1) See CoreSight Architecture Specification - // 0x00000007 [2:0] DES_1 (0x3) See CoreSight Architecture Specification - io_ro_32 fp_pidr2; - - _REG_(M33_FP_PIDR3_OFFSET) // M33_FP_PIDR3 - // Provides CoreSight discovery information for the FP - // 0x000000f0 [7:4] REVAND (0x0) See CoreSight Architecture Specification - // 0x0000000f [3:0] CMOD (0x0) See CoreSight Architecture Specification - io_ro_32 fp_pidr3; - - // (Description copied from array index 0 register M33_FP_CIDR0 applies similarly to other array indexes) - _REG_(M33_FP_CIDR0_OFFSET) // M33_FP_CIDR0 - // Provides CoreSight discovery information for the FP - // 0x000000ff [7:0] PRMBL_0 (0x0d) See CoreSight Architecture Specification - io_ro_32 fp_cidr[4]; - - uint32_t _pad22[11265]; - - _REG_(M33_ICTR_OFFSET) // M33_ICTR - // Provides information about the interrupt controller - // 0x0000000f [3:0] INTLINESNUM (0x1) Indicates the number of the highest implemented register... - io_ro_32 ictr; - - _REG_(M33_ACTLR_OFFSET) // M33_ACTLR - // Provides IMPLEMENTATION DEFINED configuration and control options - // 0x20000000 [29] EXTEXCLALL (0) External Exclusives Allowed with no MPU - // 0x00001000 [12] DISITMATBFLUSH (0) Disable ATB Flush - // 0x00000400 [10] FPEXCODIS (0) Disable FPU exception outputs - // 0x00000200 [9] DISOOFP (0) Disable out-of-order FP instruction completion - // 0x00000004 [2] DISFOLD (0) Disable dual-issue - // 0x00000001 [0] DISMCYCINT (0) Disable dual-issue - io_rw_32 actlr; - - uint32_t _pad23; - - _REG_(M33_SYST_CSR_OFFSET) // M33_SYST_CSR - // SysTick Control and Status Register - // 0x00010000 [16] COUNTFLAG (0) Returns 1 if timer counted to 0 since last time this was read - // 0x00000004 [2] CLKSOURCE (0) SysTick clock source - // 0x00000002 [1] TICKINT (0) Enables SysTick exception request: + - // 0x00000001 [0] ENABLE (0) Enable SysTick counter: + - io_rw_32 syst_csr; - - _REG_(M33_SYST_RVR_OFFSET) // M33_SYST_RVR - // SysTick Reload Value Register - // 0x00ffffff [23:0] RELOAD (0x000000) Value to load into the SysTick Current Value Register... - io_rw_32 syst_rvr; - - _REG_(M33_SYST_CVR_OFFSET) // M33_SYST_CVR - // SysTick Current Value Register - // 0x00ffffff [23:0] CURRENT (0x000000) Reads return the current value of the SysTick counter - io_rw_32 syst_cvr; - - _REG_(M33_SYST_CALIB_OFFSET) // M33_SYST_CALIB - // SysTick Calibration Value Register - // 0x80000000 [31] NOREF (0) If reads as 1, the Reference clock is not provided - the... - // 0x40000000 [30] SKEW (0) If reads as 1, the calibration value for 10ms is inexact... - // 0x00ffffff [23:0] TENMS (0x000000) An optional Reload value to be used for 10ms (100Hz)... - io_ro_32 syst_calib; - - uint32_t _pad24[56]; - - // (Description copied from array index 0 register M33_NVIC_ISER0 applies similarly to other array indexes) - _REG_(M33_NVIC_ISER0_OFFSET) // M33_NVIC_ISER0 - // Enables or reads the enabled state of each group of 32 interrupts - // 0xffffffff [31:0] SETENA (0x00000000) For SETENA[m] in NVIC_ISER*n, indicates whether... - io_rw_32 nvic_iser[2]; - - uint32_t _pad25[30]; - - // (Description copied from array index 0 register M33_NVIC_ICER0 applies similarly to other array indexes) - _REG_(M33_NVIC_ICER0_OFFSET) // M33_NVIC_ICER0 - // Clears or reads the enabled state of each group of 32 interrupts - // 0xffffffff [31:0] CLRENA (0x00000000) For CLRENA[m] in NVIC_ICER*n, indicates whether... - io_rw_32 nvic_icer[2]; - - uint32_t _pad26[30]; - - // (Description copied from array index 0 register M33_NVIC_ISPR0 applies similarly to other array indexes) - _REG_(M33_NVIC_ISPR0_OFFSET) // M33_NVIC_ISPR0 - // Enables or reads the pending state of each group of 32 interrupts - // 0xffffffff [31:0] SETPEND (0x00000000) For SETPEND[m] in NVIC_ISPR*n, indicates whether... - io_rw_32 nvic_ispr[2]; - - uint32_t _pad27[30]; - - // (Description copied from array index 0 register M33_NVIC_ICPR0 applies similarly to other array indexes) - _REG_(M33_NVIC_ICPR0_OFFSET) // M33_NVIC_ICPR0 - // Clears or reads the pending state of each group of 32 interrupts - // 0xffffffff [31:0] CLRPEND (0x00000000) For CLRPEND[m] in NVIC_ICPR*n, indicates whether... - io_rw_32 nvic_icpr[2]; - - uint32_t _pad28[30]; - - // (Description copied from array index 0 register M33_NVIC_IABR0 applies similarly to other array indexes) - _REG_(M33_NVIC_IABR0_OFFSET) // M33_NVIC_IABR0 - // For each group of 32 interrupts, shows the active state of each interrupt - // 0xffffffff [31:0] ACTIVE (0x00000000) For ACTIVE[m] in NVIC_IABR*n, indicates the active state... - io_rw_32 nvic_iabr[2]; - - uint32_t _pad29[30]; - - // (Description copied from array index 0 register M33_NVIC_ITNS0 applies similarly to other array indexes) - _REG_(M33_NVIC_ITNS0_OFFSET) // M33_NVIC_ITNS0 - // For each group of 32 interrupts, determines whether each interrupt targets Non-secure or Secure state - // 0xffffffff [31:0] ITNS (0x00000000) For ITNS[m] in NVIC_ITNS*n, `IAAMO the target Security... - io_rw_32 nvic_itns[2]; - - uint32_t _pad30[30]; - - // (Description copied from array index 0 register M33_NVIC_IPR0 applies similarly to other array indexes) - _REG_(M33_NVIC_IPR0_OFFSET) // M33_NVIC_IPR0 - // Sets or reads interrupt priorities - // 0xf0000000 [31:28] PRI_N3 (0x0) For register NVIC_IPRn, the priority of interrupt number... - // 0x00f00000 [23:20] PRI_N2 (0x0) For register NVIC_IPRn, the priority of interrupt number... - // 0x0000f000 [15:12] PRI_N1 (0x0) For register NVIC_IPRn, the priority of interrupt number... - // 0x000000f0 [7:4] PRI_N0 (0x0) For register NVIC_IPRn, the priority of interrupt number... - io_rw_32 nvic_ipr[16]; - - uint32_t _pad31[560]; - - _REG_(M33_CPUID_OFFSET) // M33_CPUID - // Provides identification information for the PE, including an implementer code for the device and... - // 0xff000000 [31:24] IMPLEMENTER (0x41) This field must hold an implementer code that has been... - // 0x00f00000 [23:20] VARIANT (0x1) IMPLEMENTATION DEFINED variant number - // 0x000f0000 [19:16] ARCHITECTURE (0xf) Defines the Architecture implemented by the PE - // 0x0000fff0 [15:4] PARTNO (0xd21) IMPLEMENTATION DEFINED primary part number for the device - // 0x0000000f [3:0] REVISION (0x0) IMPLEMENTATION DEFINED revision number for the device - io_ro_32 cpuid; - - _REG_(M33_ICSR_OFFSET) // M33_ICSR - // Controls and provides status information for NMI, PendSV, SysTick and interrupts - // 0x80000000 [31] PENDNMISET (0) Indicates whether the NMI exception is pending - // 0x40000000 [30] PENDNMICLR (0) Allows the NMI exception pend state to be cleared - // 0x10000000 [28] PENDSVSET (0) Indicates whether the PendSV `FTSSS exception is pending - // 0x08000000 [27] PENDSVCLR (0) Allows the PendSV exception pend state to be cleared `FTSSS - // 0x04000000 [26] PENDSTSET (0) Indicates whether the SysTick `FTSSS exception is pending - // 0x02000000 [25] PENDSTCLR (0) Allows the SysTick exception pend state to be cleared `FTSSS - // 0x01000000 [24] STTNS (0) Controls whether in a single SysTick implementation, the... - // 0x00800000 [23] ISRPREEMPT (0) Indicates whether a pending exception will be serviced... - // 0x00400000 [22] ISRPENDING (0) Indicates whether an external interrupt, generated by... - // 0x001ff000 [20:12] VECTPENDING (0x000) The exception number of the highest priority pending and... - // 0x00000800 [11] RETTOBASE (0) In Handler mode, indicates whether there is more than... - // 0x000001ff [8:0] VECTACTIVE (0x000) The exception number of the current executing exception - io_rw_32 icsr; - - _REG_(M33_VTOR_OFFSET) // M33_VTOR - // Vector Table Offset Register - // 0xffffff80 [31:7] TBLOFF (0x0000000) Vector table base offset field - io_rw_32 vtor; - - _REG_(M33_AIRCR_OFFSET) // M33_AIRCR - // Application Interrupt and Reset Control Register - // 0xffff0000 [31:16] VECTKEY (0x0000) Register key: + - // 0x00008000 [15] ENDIANESS (0) Data endianness implemented: + - // 0x00004000 [14] PRIS (0) Prioritize Secure exceptions - // 0x00002000 [13] BFHFNMINS (0) BusFault, HardFault, and NMI Non-secure enable - // 0x00000700 [10:8] PRIGROUP (0x0) Interrupt priority grouping field - // 0x00000008 [3] SYSRESETREQS (0) System reset request, Secure state only - // 0x00000004 [2] SYSRESETREQ (0) Writing 1 to this bit causes the SYSRESETREQ signal to... - // 0x00000002 [1] VECTCLRACTIVE (0) Clears all active state information for fixed and... - io_rw_32 aircr; - - _REG_(M33_SCR_OFFSET) // M33_SCR - // System Control Register - // 0x00000010 [4] SEVONPEND (0) Send Event on Pending bit: + - // 0x00000008 [3] SLEEPDEEPS (0) 0 SLEEPDEEP is available to both security states + - // 0x00000004 [2] SLEEPDEEP (0) Controls whether the processor uses sleep or deep sleep... - // 0x00000002 [1] SLEEPONEXIT (0) Indicates sleep-on-exit when returning from Handler mode... - io_rw_32 scr; - - _REG_(M33_CCR_OFFSET) // M33_CCR - // Sets or returns configuration and control data - // 0x00040000 [18] BP (0) Enables program flow prediction `FTSSS - // 0x00020000 [17] IC (0) This is a global enable bit for instruction caches in... - // 0x00010000 [16] DC (0) Enables data caching of all data accesses to Normal memory `FTSSS - // 0x00000400 [10] STKOFHFNMIGN (0) Controls the effect of a stack limit violation while... - // 0x00000200 [9] RES1 (1) Reserved, RES1 - // 0x00000100 [8] BFHFNMIGN (0) Determines the effect of precise BusFaults on handlers... - // 0x00000010 [4] DIV_0_TRP (0) Controls the generation of a DIVBYZERO UsageFault when... - // 0x00000008 [3] UNALIGN_TRP (0) Controls the trapping of unaligned word or halfword accesses - // 0x00000002 [1] USERSETMPEND (0) Determines whether unprivileged accesses are permitted... - // 0x00000001 [0] RES1_1 (1) Reserved, RES1 - io_rw_32 ccr; - - // (Description copied from array index 0 register M33_SHPR1 applies similarly to other array indexes) - _REG_(M33_SHPR1_OFFSET) // M33_SHPR1 - // Sets or returns priority for system handlers 4 - 7 - // 0xe0000000 [31:29] PRI_7_3 (0x0) Priority of system handler 7, SecureFault - // 0x00e00000 [23:21] PRI_6_3 (0x0) Priority of system handler 6, SecureFault - // 0x0000e000 [15:13] PRI_5_3 (0x0) Priority of system handler 5, SecureFault - // 0x000000e0 [7:5] PRI_4_3 (0x0) Priority of system handler 4, SecureFault - io_rw_32 shpr[3]; - - _REG_(M33_SHCSR_OFFSET) // M33_SHCSR - // Provides access to the active and pending status of system exceptions - // 0x00200000 [21] HARDFAULTPENDED (0) `IAAMO the pending state of the HardFault exception `CTTSSS - // 0x00100000 [20] SECUREFAULTPENDED (0) `IAAMO the pending state of the SecureFault exception - // 0x00080000 [19] SECUREFAULTENA (0) `DW the SecureFault exception is enabled - // 0x00040000 [18] USGFAULTENA (0) `DW the UsageFault exception is enabled `FTSSS - // 0x00020000 [17] BUSFAULTENA (0) `DW the BusFault exception is enabled - // 0x00010000 [16] MEMFAULTENA (0) `DW the MemManage exception is enabled `FTSSS - // 0x00008000 [15] SVCALLPENDED (0) `IAAMO the pending state of the SVCall exception `FTSSS - // 0x00004000 [14] BUSFAULTPENDED (0) `IAAMO the pending state of the BusFault exception - // 0x00002000 [13] MEMFAULTPENDED (0) `IAAMO the pending state of the MemManage exception `FTSSS - // 0x00001000 [12] USGFAULTPENDED (0) The UsageFault exception is banked between Security... - // 0x00000800 [11] SYSTICKACT (0) `IAAMO the active state of the SysTick exception `FTSSS - // 0x00000400 [10] PENDSVACT (0) `IAAMO the active state of the PendSV exception `FTSSS - // 0x00000100 [8] MONITORACT (0) `IAAMO the active state of the DebugMonitor exception - // 0x00000080 [7] SVCALLACT (0) `IAAMO the active state of the SVCall exception `FTSSS - // 0x00000020 [5] NMIACT (0) `IAAMO the active state of the NMI exception - // 0x00000010 [4] SECUREFAULTACT (0) `IAAMO the active state of the SecureFault exception - // 0x00000008 [3] USGFAULTACT (0) `IAAMO the active state of the UsageFault exception `FTSSS - // 0x00000004 [2] HARDFAULTACT (0) Indicates and allows limited modification of the active... - // 0x00000002 [1] BUSFAULTACT (0) `IAAMO the active state of the BusFault exception - // 0x00000001 [0] MEMFAULTACT (0) `IAAMO the active state of the MemManage exception `FTSSS - io_rw_32 shcsr; - - _REG_(M33_CFSR_OFFSET) // M33_CFSR - // Contains the three Configurable Fault Status Registers - // 0x02000000 [25] UFSR_DIVBYZERO (0) Sticky flag indicating whether an integer division by... - // 0x01000000 [24] UFSR_UNALIGNED (0) Sticky flag indicating whether an unaligned access error... - // 0x00100000 [20] UFSR_STKOF (0) Sticky flag indicating whether a stack overflow error... - // 0x00080000 [19] UFSR_NOCP (0) Sticky flag indicating whether a coprocessor disabled or... - // 0x00040000 [18] UFSR_INVPC (0) Sticky flag indicating whether an integrity check error... - // 0x00020000 [17] UFSR_INVSTATE (0) Sticky flag indicating whether an EPSR - // 0x00010000 [16] UFSR_UNDEFINSTR (0) Sticky flag indicating whether an undefined instruction... - // 0x00008000 [15] BFSR_BFARVALID (0) Indicates validity of the contents of the BFAR register - // 0x00002000 [13] BFSR_LSPERR (0) Records whether a BusFault occurred during FP lazy state... - // 0x00001000 [12] BFSR_STKERR (0) Records whether a derived BusFault occurred during... - // 0x00000800 [11] BFSR_UNSTKERR (0) Records whether a derived BusFault occurred during... - // 0x00000400 [10] BFSR_IMPRECISERR (0) Records whether an imprecise data access error has occurred - // 0x00000200 [9] BFSR_PRECISERR (0) Records whether a precise data access error has occurred - // 0x00000100 [8] BFSR_IBUSERR (0) Records whether a BusFault on an instruction prefetch... - // 0x000000ff [7:0] MMFSR (0x00) Provides information on MemManage exceptions - io_rw_32 cfsr; - - _REG_(M33_HFSR_OFFSET) // M33_HFSR - // Shows the cause of any HardFaults - // 0x80000000 [31] DEBUGEVT (0) Indicates when a Debug event has occurred - // 0x40000000 [30] FORCED (0) Indicates that a fault with configurable priority has... - // 0x00000002 [1] VECTTBL (0) Indicates when a fault has occurred because of a vector... - io_rw_32 hfsr; - - _REG_(M33_DFSR_OFFSET) // M33_DFSR - // Shows which debug event occurred - // 0x00000010 [4] EXTERNAL (0) Sticky flag indicating whether an External debug request... - // 0x00000008 [3] VCATCH (0) Sticky flag indicating whether a Vector catch debug... - // 0x00000004 [2] DWTTRAP (0) Sticky flag indicating whether a Watchpoint debug event... - // 0x00000002 [1] BKPT (0) Sticky flag indicating whether a Breakpoint debug event... - // 0x00000001 [0] HALTED (0) Sticky flag indicating that a Halt request debug event... - io_rw_32 dfsr; - - _REG_(M33_MMFAR_OFFSET) // M33_MMFAR - // Shows the address of the memory location that caused an MPU fault - // 0xffffffff [31:0] ADDRESS (0x00000000) This register is updated with the address of a location... - io_rw_32 mmfar; - - _REG_(M33_BFAR_OFFSET) // M33_BFAR - // Shows the address associated with a precise data access BusFault - // 0xffffffff [31:0] ADDRESS (0x00000000) This register is updated with the address of a location... - io_rw_32 bfar; - - uint32_t _pad32; - - // (Description copied from array index 0 register M33_ID_PFR0 applies similarly to other array indexes) - _REG_(M33_ID_PFR0_OFFSET) // M33_ID_PFR0 - // Gives top-level information about the instruction set supported by the PE - // 0x000000f0 [7:4] STATE1 (0x3) T32 instruction set support - // 0x0000000f [3:0] STATE0 (0x0) A32 instruction set support - io_ro_32 id_pfr[2]; - - _REG_(M33_ID_DFR0_OFFSET) // M33_ID_DFR0 - // Provides top level information about the debug system - // 0x00f00000 [23:20] MPROFDBG (0x2) Indicates the supported M-profile debug architecture - io_ro_32 id_dfr0; - - _REG_(M33_ID_AFR0_OFFSET) // M33_ID_AFR0 - // Provides information about the IMPLEMENTATION DEFINED features of the PE - // 0x0000f000 [15:12] IMPDEF3 (0x0) IMPLEMENTATION DEFINED meaning - // 0x00000f00 [11:8] IMPDEF2 (0x0) IMPLEMENTATION DEFINED meaning - // 0x000000f0 [7:4] IMPDEF1 (0x0) IMPLEMENTATION DEFINED meaning - // 0x0000000f [3:0] IMPDEF0 (0x0) IMPLEMENTATION DEFINED meaning - io_ro_32 id_afr0; - - // (Description copied from array index 0 register M33_ID_MMFR0 applies similarly to other array indexes) - _REG_(M33_ID_MMFR0_OFFSET) // M33_ID_MMFR0 - // Provides information about the implemented memory model and memory management support - // 0x00f00000 [23:20] AUXREG (0x1) Indicates support for Auxiliary Control Registers - // 0x000f0000 [19:16] TCM (0x0) Indicates support for tightly coupled memories (TCMs) - // 0x0000f000 [15:12] SHARELVL (0x1) Indicates the number of shareability levels implemented - // 0x00000f00 [11:8] OUTERSHR (0xf) Indicates the outermost shareability domain implemented - // 0x000000f0 [7:4] PMSA (0x4) Indicates support for the protected memory system... - io_ro_32 id_mmfr[4]; - - // (Description copied from array index 0 register M33_ID_ISAR0 applies similarly to other array indexes) - _REG_(M33_ID_ISAR0_OFFSET) // M33_ID_ISAR0 - // Provides information about the instruction set implemented by the PE - // 0x0f000000 [27:24] DIVIDE (0x8) Indicates the supported Divide instructions - // 0x00f00000 [23:20] DEBUG (0x0) Indicates the implemented Debug instructions - // 0x000f0000 [19:16] COPROC (0x9) Indicates the supported Coprocessor instructions - // 0x0000f000 [15:12] CMPBRANCH (0x2) Indicates the supported combined Compare and Branch instructions - // 0x00000f00 [11:8] BITFIELD (0x3) Indicates the supported bit field instructions - // 0x000000f0 [7:4] BITCOUNT (0x0) Indicates the supported bit count instructions - io_ro_32 id_isar[6]; - - uint32_t _pad33; - - _REG_(M33_CTR_OFFSET) // M33_CTR - // Provides information about the architecture of the caches - // 0x80000000 [31] RES1 (1) Reserved, RES1 - // 0x0f000000 [27:24] CWG (0x0) Log2 of the number of words of the maximum size of... - // 0x00f00000 [23:20] ERG (0x0) Log2 of the number of words of the maximum size of the... - // 0x000f0000 [19:16] DMINLINE (0x0) Log2 of the number of words in the smallest cache line... - // 0x0000c000 [15:14] RES1_1 (0x3) Reserved, RES1 - // 0x0000000f [3:0] IMINLINE (0x0) Log2 of the number of words in the smallest cache line... - io_ro_32 ctr; - - uint32_t _pad34[2]; - - _REG_(M33_CPACR_OFFSET) // M33_CPACR - // Specifies the access privileges for coprocessors and the FP Extension - // 0x00c00000 [23:22] CP11 (0x0) The value in this field is ignored - // 0x00300000 [21:20] CP10 (0x0) Defines the access rights for the floating-point functionality - // 0x0000c000 [15:14] CP7 (0x0) Controls access privileges for coprocessor 7 - // 0x00003000 [13:12] CP6 (0x0) Controls access privileges for coprocessor 6 - // 0x00000c00 [11:10] CP5 (0x0) Controls access privileges for coprocessor 5 - // 0x00000300 [9:8] CP4 (0x0) Controls access privileges for coprocessor 4 - // 0x000000c0 [7:6] CP3 (0x0) Controls access privileges for coprocessor 3 - // 0x00000030 [5:4] CP2 (0x0) Controls access privileges for coprocessor 2 - // 0x0000000c [3:2] CP1 (0x0) Controls access privileges for coprocessor 1 - // 0x00000003 [1:0] CP0 (0x0) Controls access privileges for coprocessor 0 - io_rw_32 cpacr; - - _REG_(M33_NSACR_OFFSET) // M33_NSACR - // Defines the Non-secure access permissions for both the FP Extension and coprocessors CP0 to CP7 - // 0x00000800 [11] CP11 (0) Enables Non-secure access to the Floating-point Extension - // 0x00000400 [10] CP10 (0) Enables Non-secure access to the Floating-point Extension - // 0x00000080 [7] CP7 (0) Enables Non-secure access to coprocessor CP7 - // 0x00000040 [6] CP6 (0) Enables Non-secure access to coprocessor CP6 - // 0x00000020 [5] CP5 (0) Enables Non-secure access to coprocessor CP5 - // 0x00000010 [4] CP4 (0) Enables Non-secure access to coprocessor CP4 - // 0x00000008 [3] CP3 (0) Enables Non-secure access to coprocessor CP3 - // 0x00000004 [2] CP2 (0) Enables Non-secure access to coprocessor CP2 - // 0x00000002 [1] CP1 (0) Enables Non-secure access to coprocessor CP1 - // 0x00000001 [0] CP0 (0) Enables Non-secure access to coprocessor CP0 - io_rw_32 nsacr; - - _REG_(M33_MPU_TYPE_OFFSET) // M33_MPU_TYPE - // The MPU Type Register indicates how many regions the MPU `FTSSS supports - // 0x0000ff00 [15:8] DREGION (0x08) Number of regions supported by the MPU - // 0x00000001 [0] SEPARATE (0) Indicates support for separate instructions and data... - io_ro_32 mpu_type; - - _REG_(M33_MPU_CTRL_OFFSET) // M33_MPU_CTRL - // Enables the MPU and, when the MPU is enabled, controls whether the default memory map is enabled... - // 0x00000004 [2] PRIVDEFENA (0) Controls whether the default memory map is enabled for... - // 0x00000002 [1] HFNMIENA (0) Controls whether handlers executing with priority less... - // 0x00000001 [0] ENABLE (0) Enables the MPU - io_rw_32 mpu_ctrl; - - _REG_(M33_MPU_RNR_OFFSET) // M33_MPU_RNR - // Selects the region currently accessed by MPU_RBAR and MPU_RLAR - // 0x00000007 [2:0] REGION (0x0) Indicates the memory region accessed by MPU_RBAR and MPU_RLAR - io_rw_32 mpu_rnr; - - _REG_(M33_MPU_RBAR_OFFSET) // M33_MPU_RBAR - // Provides indirect read and write access to the base address of the currently selected MPU region `FTSSS - // 0xffffffe0 [31:5] BASE (0x0000000) Contains bits [31:5] of the lower inclusive limit of the... - // 0x00000018 [4:3] SH (0x0) Defines the Shareability domain of this region for Normal memory - // 0x00000006 [2:1] AP (0x0) Defines the access permissions for this region - // 0x00000001 [0] XN (0) Defines whether code can be executed from this region - io_rw_32 mpu_rbar; - - _REG_(M33_MPU_RLAR_OFFSET) // M33_MPU_RLAR - // Provides indirect read and write access to the limit address of the currently selected MPU region `FTSSS - // 0xffffffe0 [31:5] LIMIT (0x0000000) Contains bits [31:5] of the upper inclusive limit of the... - // 0x0000000e [3:1] ATTRINDX (0x0) Associates a set of attributes in the MPU_MAIR0 and... - // 0x00000001 [0] EN (0) Region enable - io_rw_32 mpu_rlar; - - _REG_(M33_MPU_RBAR_A1_OFFSET) // M33_MPU_RBAR_A1 - // Provides indirect read and write access to the base address of the MPU region selected by... - // 0xffffffe0 [31:5] BASE (0x0000000) Contains bits [31:5] of the lower inclusive limit of the... - // 0x00000018 [4:3] SH (0x0) Defines the Shareability domain of this region for Normal memory - // 0x00000006 [2:1] AP (0x0) Defines the access permissions for this region - // 0x00000001 [0] XN (0) Defines whether code can be executed from this region - io_rw_32 mpu_rbar_a1; - - _REG_(M33_MPU_RLAR_A1_OFFSET) // M33_MPU_RLAR_A1 - // Provides indirect read and write access to the limit address of the currently selected MPU... - // 0xffffffe0 [31:5] LIMIT (0x0000000) Contains bits [31:5] of the upper inclusive limit of the... - // 0x0000000e [3:1] ATTRINDX (0x0) Associates a set of attributes in the MPU_MAIR0 and... - // 0x00000001 [0] EN (0) Region enable - io_rw_32 mpu_rlar_a1; - - _REG_(M33_MPU_RBAR_A2_OFFSET) // M33_MPU_RBAR_A2 - // Provides indirect read and write access to the base address of the MPU region selected by... - // 0xffffffe0 [31:5] BASE (0x0000000) Contains bits [31:5] of the lower inclusive limit of the... - // 0x00000018 [4:3] SH (0x0) Defines the Shareability domain of this region for Normal memory - // 0x00000006 [2:1] AP (0x0) Defines the access permissions for this region - // 0x00000001 [0] XN (0) Defines whether code can be executed from this region - io_rw_32 mpu_rbar_a2; - - _REG_(M33_MPU_RLAR_A2_OFFSET) // M33_MPU_RLAR_A2 - // Provides indirect read and write access to the limit address of the currently selected MPU... - // 0xffffffe0 [31:5] LIMIT (0x0000000) Contains bits [31:5] of the upper inclusive limit of the... - // 0x0000000e [3:1] ATTRINDX (0x0) Associates a set of attributes in the MPU_MAIR0 and... - // 0x00000001 [0] EN (0) Region enable - io_rw_32 mpu_rlar_a2; - - _REG_(M33_MPU_RBAR_A3_OFFSET) // M33_MPU_RBAR_A3 - // Provides indirect read and write access to the base address of the MPU region selected by... - // 0xffffffe0 [31:5] BASE (0x0000000) Contains bits [31:5] of the lower inclusive limit of the... - // 0x00000018 [4:3] SH (0x0) Defines the Shareability domain of this region for Normal memory - // 0x00000006 [2:1] AP (0x0) Defines the access permissions for this region - // 0x00000001 [0] XN (0) Defines whether code can be executed from this region - io_rw_32 mpu_rbar_a3; - - _REG_(M33_MPU_RLAR_A3_OFFSET) // M33_MPU_RLAR_A3 - // Provides indirect read and write access to the limit address of the currently selected MPU... - // 0xffffffe0 [31:5] LIMIT (0x0000000) Contains bits [31:5] of the upper inclusive limit of the... - // 0x0000000e [3:1] ATTRINDX (0x0) Associates a set of attributes in the MPU_MAIR0 and... - // 0x00000001 [0] EN (0) Region enable - io_rw_32 mpu_rlar_a3; - - uint32_t _pad35; - - // (Description copied from array index 0 register M33_MPU_MAIR0 applies similarly to other array indexes) - _REG_(M33_MPU_MAIR0_OFFSET) // M33_MPU_MAIR0 - // Along with MPU_MAIR1, provides the memory attribute encodings corresponding to the AttrIndex values - // 0xff000000 [31:24] ATTR3 (0x00) Memory attribute encoding for MPU regions with an AttrIndex of 3 - // 0x00ff0000 [23:16] ATTR2 (0x00) Memory attribute encoding for MPU regions with an AttrIndex of 2 - // 0x0000ff00 [15:8] ATTR1 (0x00) Memory attribute encoding for MPU regions with an AttrIndex of 1 - // 0x000000ff [7:0] ATTR0 (0x00) Memory attribute encoding for MPU regions with an AttrIndex of 0 - io_rw_32 mpu_mair[2]; - - uint32_t _pad36[2]; - - _REG_(M33_SAU_CTRL_OFFSET) // M33_SAU_CTRL - // Allows enabling of the Security Attribution Unit - // 0x00000002 [1] ALLNS (0) When SAU_CTRL - // 0x00000001 [0] ENABLE (0) Enables the SAU - io_rw_32 sau_ctrl; - - _REG_(M33_SAU_TYPE_OFFSET) // M33_SAU_TYPE - // Indicates the number of regions implemented by the Security Attribution Unit - // 0x000000ff [7:0] SREGION (0x08) The number of implemented SAU regions - io_ro_32 sau_type; - - _REG_(M33_SAU_RNR_OFFSET) // M33_SAU_RNR - // Selects the region currently accessed by SAU_RBAR and SAU_RLAR - // 0x000000ff [7:0] REGION (0x00) Indicates the SAU region accessed by SAU_RBAR and SAU_RLAR - io_rw_32 sau_rnr; - - _REG_(M33_SAU_RBAR_OFFSET) // M33_SAU_RBAR - // Provides indirect read and write access to the base address of the currently selected SAU region - // 0xffffffe0 [31:5] BADDR (0x0000000) Holds bits [31:5] of the base address for the selected SAU region - io_rw_32 sau_rbar; - - _REG_(M33_SAU_RLAR_OFFSET) // M33_SAU_RLAR - // Provides indirect read and write access to the limit address of the currently selected SAU region - // 0xffffffe0 [31:5] LADDR (0x0000000) Holds bits [31:5] of the limit address for the selected... - // 0x00000002 [1] NSC (0) Controls whether Non-secure state is permitted to... - // 0x00000001 [0] ENABLE (0) SAU region enable - io_rw_32 sau_rlar; - - _REG_(M33_SFSR_OFFSET) // M33_SFSR - // Provides information about any security related faults - // 0x00000080 [7] LSERR (0) Sticky flag indicating that an error occurred during... - // 0x00000040 [6] SFARVALID (0) This bit is set when the SFAR register contains a valid value - // 0x00000020 [5] LSPERR (0) Stick flag indicating that an SAU or IDAU violation... - // 0x00000010 [4] INVTRAN (0) Sticky flag indicating that an exception was raised due... - // 0x00000008 [3] AUVIOL (0) Sticky flag indicating that an attempt was made to... - // 0x00000004 [2] INVER (0) This can be caused by EXC_RETURN - // 0x00000002 [1] INVIS (0) This bit is set if the integrity signature in an... - // 0x00000001 [0] INVEP (0) This bit is set if a function call from the Non-secure... - io_rw_32 sfsr; - - _REG_(M33_SFAR_OFFSET) // M33_SFAR - // Shows the address of the memory location that caused a Security violation - // 0xffffffff [31:0] ADDRESS (0x00000000) The address of an access that caused a attribution unit violation - io_rw_32 sfar; - - uint32_t _pad37; - - _REG_(M33_DHCSR_OFFSET) // M33_DHCSR - // Controls halting debug - // 0x04000000 [26] S_RESTART_ST (0) Indicates the PE has processed a request to clear DHCSR - // 0x02000000 [25] S_RESET_ST (0) Indicates whether the PE has been reset since the last... - // 0x01000000 [24] S_RETIRE_ST (0) Set to 1 every time the PE retires one of more instructions - // 0x00100000 [20] S_SDE (0) Indicates whether Secure invasive debug is allowed - // 0x00080000 [19] S_LOCKUP (0) Indicates whether the PE is in Lockup state - // 0x00040000 [18] S_SLEEP (0) Indicates whether the PE is sleeping - // 0x00020000 [17] S_HALT (0) Indicates whether the PE is in Debug state - // 0x00010000 [16] S_REGRDY (0) Handshake flag to transfers through the DCRDR - // 0x00000020 [5] C_SNAPSTALL (0) Allow imprecise entry to Debug state - // 0x00000008 [3] C_MASKINTS (0) When debug is enabled, the debugger can write to this... - // 0x00000004 [2] C_STEP (0) Enable single instruction step - // 0x00000002 [1] C_HALT (0) PE enter Debug state halt request - // 0x00000001 [0] C_DEBUGEN (0) Enable Halting debug - io_rw_32 dhcsr; - - _REG_(M33_DCRSR_OFFSET) // M33_DCRSR - // With the DCRDR, provides debug access to the general-purpose registers, special-purpose... - // 0x00010000 [16] REGWNR (0) Specifies the access type for the transfer - // 0x0000007f [6:0] REGSEL (0x00) Specifies the general-purpose register, special-purpose... - io_rw_32 dcrsr; - - _REG_(M33_DCRDR_OFFSET) // M33_DCRDR - // With the DCRSR, provides debug access to the general-purpose registers, special-purpose... - // 0xffffffff [31:0] DBGTMP (0x00000000) Provides debug access for reading and writing the... - io_rw_32 dcrdr; - - _REG_(M33_DEMCR_OFFSET) // M33_DEMCR - // Manages vector catch behavior and DebugMonitor handling when debugging - // 0x01000000 [24] TRCENA (0) Global enable for all DWT and ITM features - // 0x00100000 [20] SDME (0) Indicates whether the DebugMonitor targets the Secure or... - // 0x00080000 [19] MON_REQ (0) DebugMonitor semaphore bit - // 0x00040000 [18] MON_STEP (0) Enable DebugMonitor stepping - // 0x00020000 [17] MON_PEND (0) Sets or clears the pending state of the DebugMonitor exception - // 0x00010000 [16] MON_EN (0) Enable the DebugMonitor exception - // 0x00000800 [11] VC_SFERR (0) SecureFault exception halting debug vector catch enable - // 0x00000400 [10] VC_HARDERR (0) HardFault exception halting debug vector catch enable - // 0x00000200 [9] VC_INTERR (0) Enable halting debug vector catch for faults during... - // 0x00000100 [8] VC_BUSERR (0) BusFault exception halting debug vector catch enable - // 0x00000080 [7] VC_STATERR (0) Enable halting debug trap on a UsageFault exception... - // 0x00000040 [6] VC_CHKERR (0) Enable halting debug trap on a UsageFault exception... - // 0x00000020 [5] VC_NOCPERR (0) Enable halting debug trap on a UsageFault caused by an... - // 0x00000010 [4] VC_MMERR (0) Enable halting debug trap on a MemManage exception - // 0x00000001 [0] VC_CORERESET (0) Enable Reset Vector Catch - io_rw_32 demcr; - - uint32_t _pad38[2]; - - _REG_(M33_DSCSR_OFFSET) // M33_DSCSR - // Provides control and status information for Secure debug - // 0x00020000 [17] CDSKEY (0) Writes to the CDS bit are ignored unless CDSKEY is... - // 0x00010000 [16] CDS (0) This field indicates the current Security state of the processor - // 0x00000002 [1] SBRSEL (0) If SBRSELEN is 1 this bit selects whether the Non-secure... - // 0x00000001 [0] SBRSELEN (0) Controls whether the SBRSEL field or the current... - io_rw_32 dscsr; - - uint32_t _pad39[61]; - - _REG_(M33_STIR_OFFSET) // M33_STIR - // Provides a mechanism for software to generate an interrupt - // 0x000001ff [8:0] INTID (0x000) Indicates the interrupt to be pended - io_rw_32 stir; - - uint32_t _pad40[12]; - - _REG_(M33_FPCCR_OFFSET) // M33_FPCCR - // Holds control data for the Floating-point extension - // 0x80000000 [31] ASPEN (0) When this bit is set to 1, execution of a floating-point... - // 0x40000000 [30] LSPEN (0) Enables lazy context save of floating-point state - // 0x20000000 [29] LSPENS (1) This bit controls whether the LSPEN bit is writeable... - // 0x10000000 [28] CLRONRET (0) Clear floating-point caller saved registers on exception return - // 0x08000000 [27] CLRONRETS (0) This bit controls whether the CLRONRET bit is writeable... - // 0x04000000 [26] TS (0) Treat floating-point registers as Secure enable - // 0x00000400 [10] UFRDY (1) Indicates whether the software executing when the PE... - // 0x00000200 [9] SPLIMVIOL (0) This bit is banked between the Security states and... - // 0x00000100 [8] MONRDY (0) Indicates whether the software executing when the PE... - // 0x00000080 [7] SFRDY (0) Indicates whether the software executing when the PE... - // 0x00000040 [6] BFRDY (1) Indicates whether the software executing when the PE... - // 0x00000020 [5] MMRDY (1) Indicates whether the software executing when the PE... - // 0x00000010 [4] HFRDY (1) Indicates whether the software executing when the PE... - // 0x00000008 [3] THREAD (0) Indicates the PE mode when it allocated the... - // 0x00000004 [2] S (0) Security status of the floating-point context - // 0x00000002 [1] USER (1) Indicates the privilege level of the software executing... - // 0x00000001 [0] LSPACT (0) Indicates whether lazy preservation of the... - io_rw_32 fpccr; - - _REG_(M33_FPCAR_OFFSET) // M33_FPCAR - // Holds the location of the unpopulated floating-point register space allocated on an exception stack frame - // 0xfffffff8 [31:3] ADDRESS (0x00000000) The location of the unpopulated floating-point register... - io_rw_32 fpcar; - - _REG_(M33_FPDSCR_OFFSET) // M33_FPDSCR - // Holds the default values for the floating-point status control data that the PE assigns to the... - // 0x04000000 [26] AHP (0) Default value for FPSCR - // 0x02000000 [25] DN (0) Default value for FPSCR - // 0x01000000 [24] FZ (0) Default value for FPSCR - // 0x00c00000 [23:22] RMODE (0x0) Default value for FPSCR - io_rw_32 fpdscr; - - // (Description copied from array index 0 register M33_MVFR0 applies similarly to other array indexes) - _REG_(M33_MVFR0_OFFSET) // M33_MVFR0 - // Describes the features provided by the Floating-point Extension - // 0xf0000000 [31:28] FPROUND (0x6) Indicates the rounding modes supported by the FP Extension - // 0x00f00000 [23:20] FPSQRT (0x5) Indicates the support for FP square root operations - // 0x000f0000 [19:16] FPDIVIDE (0x4) Indicates the support for FP divide operations - // 0x00000f00 [11:8] FPDP (0x6) Indicates support for FP double-precision operations - // 0x000000f0 [7:4] FPSP (0x0) Indicates support for FP single-precision operations - // 0x0000000f [3:0] SIMDREG (0x1) Indicates size of FP register file - io_ro_32 mvfr[3]; - - uint32_t _pad41[28]; - - _REG_(M33_DDEVARCH_OFFSET) // M33_DDEVARCH - // Provides CoreSight discovery information for the SCS - // 0xffe00000 [31:21] ARCHITECT (0x23b) Defines the architect of the component - // 0x00100000 [20] PRESENT (1) Defines that the DEVARCH register is present - // 0x000f0000 [19:16] REVISION (0x0) Defines the architecture revision of the component - // 0x0000f000 [15:12] ARCHVER (0x2) Defines the architecture version of the component - // 0x00000fff [11:0] ARCHPART (0xa04) Defines the architecture of the component - io_ro_32 ddevarch; - - uint32_t _pad42[3]; - - _REG_(M33_DDEVTYPE_OFFSET) // M33_DDEVTYPE - // Provides CoreSight discovery information for the SCS - // 0x000000f0 [7:4] SUB (0x0) Component sub-type - // 0x0000000f [3:0] MAJOR (0x0) CoreSight major type - io_ro_32 ddevtype; - - _REG_(M33_DPIDR4_OFFSET) // M33_DPIDR4 - // Provides CoreSight discovery information for the SCS - // 0x000000f0 [7:4] SIZE (0x0) See CoreSight Architecture Specification - // 0x0000000f [3:0] DES_2 (0x4) See CoreSight Architecture Specification - io_ro_32 dpidr4; - - _REG_(M33_DPIDR5_OFFSET) // M33_DPIDR5 - // Provides CoreSight discovery information for the SCS - // 0x00000000 [31:0] DPIDR5 (0x00000000) - io_rw_32 dpidr5; - - _REG_(M33_DPIDR6_OFFSET) // M33_DPIDR6 - // Provides CoreSight discovery information for the SCS - // 0x00000000 [31:0] DPIDR6 (0x00000000) - io_rw_32 dpidr6; - - _REG_(M33_DPIDR7_OFFSET) // M33_DPIDR7 - // Provides CoreSight discovery information for the SCS - // 0x00000000 [31:0] DPIDR7 (0x00000000) - io_rw_32 dpidr7; - - _REG_(M33_DPIDR0_OFFSET) // M33_DPIDR0 - // Provides CoreSight discovery information for the SCS - // 0x000000ff [7:0] PART_0 (0x21) See CoreSight Architecture Specification - io_ro_32 dpidr0; - - _REG_(M33_DPIDR1_OFFSET) // M33_DPIDR1 - // Provides CoreSight discovery information for the SCS - // 0x000000f0 [7:4] DES_0 (0xb) See CoreSight Architecture Specification - // 0x0000000f [3:0] PART_1 (0xd) See CoreSight Architecture Specification - io_ro_32 dpidr1; - - _REG_(M33_DPIDR2_OFFSET) // M33_DPIDR2 - // Provides CoreSight discovery information for the SCS - // 0x000000f0 [7:4] REVISION (0x0) See CoreSight Architecture Specification - // 0x00000008 [3] JEDEC (1) See CoreSight Architecture Specification - // 0x00000007 [2:0] DES_1 (0x3) See CoreSight Architecture Specification - io_ro_32 dpidr2; - - _REG_(M33_DPIDR3_OFFSET) // M33_DPIDR3 - // Provides CoreSight discovery information for the SCS - // 0x000000f0 [7:4] REVAND (0x0) See CoreSight Architecture Specification - // 0x0000000f [3:0] CMOD (0x0) See CoreSight Architecture Specification - io_ro_32 dpidr3; - - // (Description copied from array index 0 register M33_DCIDR0 applies similarly to other array indexes) - _REG_(M33_DCIDR0_OFFSET) // M33_DCIDR0 - // Provides CoreSight discovery information for the SCS - // 0x000000ff [7:0] PRMBL_0 (0x0d) See CoreSight Architecture Specification - io_ro_32 dcidr[4]; - - uint32_t _pad43[51201]; - - _REG_(M33_TRCPRGCTLR_OFFSET) // M33_TRCPRGCTLR - // Programming Control Register - // 0x00000001 [0] EN (0) Trace Unit Enable - io_rw_32 trcprgctlr; - - uint32_t _pad44; - - _REG_(M33_TRCSTATR_OFFSET) // M33_TRCSTATR - // The TRCSTATR indicates the ETM-Teal status - // 0x00000002 [1] PMSTABLE (0) Indicates whether the ETM-Teal registers are stable and... - // 0x00000001 [0] IDLE (0) Indicates that the trace unit is inactive - io_ro_32 trcstatr; - - _REG_(M33_TRCCONFIGR_OFFSET) // M33_TRCCONFIGR - // The TRCCONFIGR sets the basic tracing options for the trace unit - // 0x00001000 [12] RS (0) Return stack enable - // 0x00000800 [11] TS (0) Global timestamp tracing - // 0x000007e0 [10:5] COND (0x00) Conditional instruction tracing - // 0x00000010 [4] CCI (0) Cycle counting in instruction trace - // 0x00000008 [3] BB (0) Branch broadcast mode - io_rw_32 trcconfigr; - - uint32_t _pad45[3]; - - _REG_(M33_TRCEVENTCTL0R_OFFSET) // M33_TRCEVENTCTL0R - // The TRCEVENTCTL0R controls the tracing of events in the trace stream - // 0x00008000 [15] TYPE1 (0) Selects the resource type for event 1 - // 0x00000700 [10:8] SEL1 (0x0) Selects the resource number, based on the value of... - // 0x00000080 [7] TYPE0 (0) Selects the resource type for event 0 - // 0x00000007 [2:0] SEL0 (0x0) Selects the resource number, based on the value of... - io_rw_32 trceventctl0r; - - _REG_(M33_TRCEVENTCTL1R_OFFSET) // M33_TRCEVENTCTL1R - // The TRCEVENTCTL1R controls how the events selected by TRCEVENTCTL0R behave - // 0x00001000 [12] LPOVERRIDE (0) Low power state behavior override - // 0x00000800 [11] ATB (0) ATB enabled - // 0x00000002 [1] INSTEN1 (0) One bit per event, to enable generation of an event... - // 0x00000001 [0] INSTEN0 (0) One bit per event, to enable generation of an event... - io_rw_32 trceventctl1r; - - uint32_t _pad46; - - _REG_(M33_TRCSTALLCTLR_OFFSET) // M33_TRCSTALLCTLR - // The TRCSTALLCTLR enables ETM-Teal to stall the processor if the ETM-Teal FIFO goes over the... - // 0x00000400 [10] INSTPRIORITY (0) Reserved, RES0 - // 0x00000100 [8] ISTALL (0) Stall processor based on instruction trace buffer space - // 0x0000000c [3:2] LEVEL (0x0) Threshold at which stalling becomes active - io_rw_32 trcstallctlr; - - _REG_(M33_TRCTSCTLR_OFFSET) // M33_TRCTSCTLR - // The TRCTSCTLR controls the insertion of global timestamps into the trace stream - // 0x00000080 [7] TYPE0 (0) Selects the resource type for event 0 - // 0x00000003 [1:0] SEL0 (0x0) Selects the resource number, based on the value of... - io_rw_32 trctsctlr; - - _REG_(M33_TRCSYNCPR_OFFSET) // M33_TRCSYNCPR - // The TRCSYNCPR specifies the period of trace synchronization of the trace streams - // 0x0000001f [4:0] PERIOD (0x0a) Defines the number of bytes of trace between trace... - io_ro_32 trcsyncpr; - - _REG_(M33_TRCCCCTLR_OFFSET) // M33_TRCCCCTLR - // The TRCCCCTLR sets the threshold value for instruction trace cycle counting - // 0x00000fff [11:0] THRESHOLD (0x000) Instruction trace cycle count threshold - io_rw_32 trcccctlr; - - uint32_t _pad47[17]; - - _REG_(M33_TRCVICTLR_OFFSET) // M33_TRCVICTLR - // The TRCVICTLR controls instruction trace filtering - // 0x00080000 [19] EXLEVEL_S3 (0) In Secure state, each bit controls whether instruction... - // 0x00010000 [16] EXLEVEL_S0 (0) In Secure state, each bit controls whether instruction... - // 0x00000800 [11] TRCERR (0) Selects whether a system error exception must always be traced - // 0x00000400 [10] TRCRESET (0) Selects whether a reset exception must always be traced - // 0x00000200 [9] SSSTATUS (0) Indicates the current status of the start/stop logic - // 0x00000080 [7] TYPE0 (0) Selects the resource type for event 0 - // 0x00000003 [1:0] SEL0 (0x0) Selects the resource number, based on the value of... - io_rw_32 trcvictlr; - - uint32_t _pad48[47]; - - _REG_(M33_TRCCNTRLDVR0_OFFSET) // M33_TRCCNTRLDVR0 - // The TRCCNTRLDVR defines the reload value for the reduced function counter - // 0x0000ffff [15:0] VALUE (0x0000) Defines the reload value for the counter - io_rw_32 trccntrldvr0; - - uint32_t _pad49[15]; - - _REG_(M33_TRCIDR8_OFFSET) // M33_TRCIDR8 - // TRCIDR8 - // 0xffffffff [31:0] MAXSPEC (0x00000000) reads as `ImpDef - io_ro_32 trcidr8; - - _REG_(M33_TRCIDR9_OFFSET) // M33_TRCIDR9 - // TRCIDR9 - // 0xffffffff [31:0] NUMP0KEY (0x00000000) reads as `ImpDef - io_ro_32 trcidr9; - - _REG_(M33_TRCIDR10_OFFSET) // M33_TRCIDR10 - // TRCIDR10 - // 0xffffffff [31:0] NUMP1KEY (0x00000000) reads as `ImpDef - io_ro_32 trcidr10; - - _REG_(M33_TRCIDR11_OFFSET) // M33_TRCIDR11 - // TRCIDR11 - // 0xffffffff [31:0] NUMP1SPC (0x00000000) reads as `ImpDef - io_ro_32 trcidr11; - - _REG_(M33_TRCIDR12_OFFSET) // M33_TRCIDR12 - // TRCIDR12 - // 0xffffffff [31:0] NUMCONDKEY (0x00000001) reads as `ImpDef - io_ro_32 trcidr12; - - _REG_(M33_TRCIDR13_OFFSET) // M33_TRCIDR13 - // TRCIDR13 - // 0xffffffff [31:0] NUMCONDSPC (0x00000000) reads as `ImpDef - io_ro_32 trcidr13; - - uint32_t _pad50[10]; - - _REG_(M33_TRCIMSPEC_OFFSET) // M33_TRCIMSPEC - // The TRCIMSPEC shows the presence of any IMPLEMENTATION SPECIFIC features, and enables any... - // 0x0000000f [3:0] SUPPORT (0x0) Reserved, RES0 - io_ro_32 trcimspec; - - uint32_t _pad51[7]; - - _REG_(M33_TRCIDR0_OFFSET) // M33_TRCIDR0 - // TRCIDR0 - // 0x20000000 [29] COMMOPT (1) reads as `ImpDef - // 0x1f000000 [28:24] TSSIZE (0x08) reads as `ImpDef - // 0x00020000 [17] TRCEXDATA (0) reads as `ImpDef - // 0x00018000 [16:15] QSUPP (0x0) reads as `ImpDef - // 0x00004000 [14] QFILT (0) reads as `ImpDef - // 0x00003000 [13:12] CONDTYPE (0x0) reads as `ImpDef - // 0x00000c00 [11:10] NUMEVENT (0x1) reads as `ImpDef - // 0x00000200 [9] RETSTACK (1) reads as `ImpDef - // 0x00000080 [7] TRCCCI (1) reads as `ImpDef - // 0x00000040 [6] TRCCOND (1) reads as `ImpDef - // 0x00000020 [5] TRCBB (1) reads as `ImpDef - // 0x00000018 [4:3] TRCDATA (0x0) reads as `ImpDef - // 0x00000006 [2:1] INSTP0 (0x0) reads as `ImpDef - // 0x00000001 [0] RES1 (1) Reserved, RES1 - io_ro_32 trcidr0; - - _REG_(M33_TRCIDR1_OFFSET) // M33_TRCIDR1 - // TRCIDR1 - // 0xff000000 [31:24] DESIGNER (0x41) reads as `ImpDef - // 0x0000f000 [15:12] RES1 (0xf) Reserved, RES1 - // 0x00000f00 [11:8] TRCARCHMAJ (0x4) reads as 0b0100 - // 0x000000f0 [7:4] TRCARCHMIN (0x2) reads as 0b0000 - // 0x0000000f [3:0] REVISION (0x1) reads as `ImpDef - io_ro_32 trcidr1; - - _REG_(M33_TRCIDR2_OFFSET) // M33_TRCIDR2 - // TRCIDR2 - // 0x1e000000 [28:25] CCSIZE (0x0) reads as `ImpDef - // 0x01f00000 [24:20] DVSIZE (0x00) reads as `ImpDef - // 0x000f8000 [19:15] DASIZE (0x00) reads as `ImpDef - // 0x00007c00 [14:10] VMIDSIZE (0x00) reads as `ImpDef - // 0x000003e0 [9:5] CIDSIZE (0x00) reads as `ImpDef - // 0x0000001f [4:0] IASIZE (0x04) reads as `ImpDef - io_ro_32 trcidr2; - - _REG_(M33_TRCIDR3_OFFSET) // M33_TRCIDR3 - // TRCIDR3 - // 0x80000000 [31] NOOVERFLOW (0) reads as `ImpDef - // 0x70000000 [30:28] NUMPROC (0x0) reads as `ImpDef - // 0x08000000 [27] SYSSTALL (1) reads as `ImpDef - // 0x04000000 [26] STALLCTL (1) reads as `ImpDef - // 0x02000000 [25] SYNCPR (1) reads as `ImpDef - // 0x01000000 [24] TRCERR (1) reads as `ImpDef - // 0x00f00000 [23:20] EXLEVEL_NS (0x0) reads as `ImpDef - // 0x000f0000 [19:16] EXLEVEL_S (0x9) reads as `ImpDef - // 0x00000fff [11:0] CCITMIN (0x004) reads as `ImpDef - io_ro_32 trcidr3; - - _REG_(M33_TRCIDR4_OFFSET) // M33_TRCIDR4 - // TRCIDR4 - // 0xf0000000 [31:28] NUMVMIDC (0x0) reads as `ImpDef - // 0x0f000000 [27:24] NUMCIDC (0x0) reads as `ImpDef - // 0x00f00000 [23:20] NUMSSCC (0x1) reads as `ImpDef - // 0x000f0000 [19:16] NUMRSPAIR (0x1) reads as `ImpDef - // 0x0000f000 [15:12] NUMPC (0x4) reads as `ImpDef - // 0x00000100 [8] SUPPDAC (0) reads as `ImpDef - // 0x000000f0 [7:4] NUMDVC (0x0) reads as `ImpDef - // 0x0000000f [3:0] NUMACPAIRS (0x0) reads as `ImpDef - io_ro_32 trcidr4; - - _REG_(M33_TRCIDR5_OFFSET) // M33_TRCIDR5 - // TRCIDR5 - // 0x80000000 [31] REDFUNCNTR (1) reads as `ImpDef - // 0x70000000 [30:28] NUMCNTR (0x1) reads as `ImpDef - // 0x0e000000 [27:25] NUMSEQSTATE (0x0) reads as `ImpDef - // 0x00800000 [23] LPOVERRIDE (1) reads as `ImpDef - // 0x00400000 [22] ATBTRIG (1) reads as `ImpDef - // 0x003f0000 [21:16] TRACEIDSIZE (0x07) reads as 0x07 - // 0x00000e00 [11:9] NUMEXTINSEL (0x0) reads as `ImpDef - // 0x000001ff [8:0] NUMEXTIN (0x004) reads as `ImpDef - io_ro_32 trcidr5; - - _REG_(M33_TRCIDR6_OFFSET) // M33_TRCIDR6 - // TRCIDR6 - // 0x00000000 [31:0] TRCIDR6 (0x00000000) - io_rw_32 trcidr6; - - _REG_(M33_TRCIDR7_OFFSET) // M33_TRCIDR7 - // TRCIDR7 - // 0x00000000 [31:0] TRCIDR7 (0x00000000) - io_rw_32 trcidr7; - - uint32_t _pad52[2]; - - // (Description copied from array index 0 register M33_TRCRSCTLR2 applies similarly to other array indexes) - _REG_(M33_TRCRSCTLR2_OFFSET) // M33_TRCRSCTLR2 - // The TRCRSCTLR controls the trace resources - // 0x00200000 [21] PAIRINV (0) Inverts the result of a combined pair of resources - // 0x00100000 [20] INV (0) Inverts the selected resources - // 0x00070000 [18:16] GROUP (0x0) Selects a group of resource - // 0x000000ff [7:0] SELECT (0x00) Selects one or more resources from the wanted group - io_rw_32 trcrsctlr[2]; - - uint32_t _pad53[36]; - - _REG_(M33_TRCSSCSR_OFFSET) // M33_TRCSSCSR - // Controls the corresponding single-shot comparator resource - // 0x80000000 [31] STATUS (0) Single-shot status bit - // 0x00000008 [3] PC (0) Reserved, RES1 - // 0x00000004 [2] DV (0) Reserved, RES0 - // 0x00000002 [1] DA (0) Reserved, RES0 - // 0x00000001 [0] INST (0) Reserved, RES0 - io_rw_32 trcsscsr; - - uint32_t _pad54[7]; - - _REG_(M33_TRCSSPCICR_OFFSET) // M33_TRCSSPCICR - // Selects the PE comparator inputs for Single-shot control - // 0x0000000f [3:0] PC (0x0) Selects one or more PE comparator inputs for Single-shot control - io_rw_32 trcsspcicr; - - uint32_t _pad55[19]; - - _REG_(M33_TRCPDCR_OFFSET) // M33_TRCPDCR - // Requests the system to provide power to the trace unit - // 0x00000008 [3] PU (0) Powerup request bit: - io_rw_32 trcpdcr; - - _REG_(M33_TRCPDSR_OFFSET) // M33_TRCPDSR - // Returns the following information about the trace unit: - OS Lock status - // 0x00000020 [5] OSLK (0) OS Lock status bit: - // 0x00000002 [1] STICKYPD (1) Sticky powerdown status bit - // 0x00000001 [0] POWER (1) Power status bit: - io_ro_32 trcpdsr; - - uint32_t _pad56[755]; - - _REG_(M33_TRCITATBIDR_OFFSET) // M33_TRCITATBIDR - // Trace Integration ATB Identification Register - // 0x0000007f [6:0] ID (0x00) Trace ID - io_rw_32 trcitatbidr; - - uint32_t _pad57[3]; - - _REG_(M33_TRCITIATBINR_OFFSET) // M33_TRCITIATBINR - // Trace Integration Instruction ATB In Register - // 0x00000002 [1] AFVALIDM (0) Integration Mode instruction AFVALIDM in - // 0x00000001 [0] ATREADYM (0) Integration Mode instruction ATREADYM in - io_rw_32 trcitiatbinr; - - uint32_t _pad58; - - _REG_(M33_TRCITIATBOUTR_OFFSET) // M33_TRCITIATBOUTR - // Trace Integration Instruction ATB Out Register - // 0x00000002 [1] AFREADY (0) Integration Mode instruction AFREADY out - // 0x00000001 [0] ATVALID (0) Integration Mode instruction ATVALID out - io_rw_32 trcitiatboutr; - - uint32_t _pad59[40]; - - _REG_(M33_TRCCLAIMSET_OFFSET) // M33_TRCCLAIMSET - // Claim Tag Set Register - // 0x00000008 [3] SET3 (1) When a write to one of these bits occurs, with the value: - // 0x00000004 [2] SET2 (1) When a write to one of these bits occurs, with the value: - // 0x00000002 [1] SET1 (1) When a write to one of these bits occurs, with the value: - // 0x00000001 [0] SET0 (1) When a write to one of these bits occurs, with the value: - io_rw_32 trcclaimset; - - _REG_(M33_TRCCLAIMCLR_OFFSET) // M33_TRCCLAIMCLR - // Claim Tag Clear Register - // 0x00000008 [3] CLR3 (0) When a write to one of these bits occurs, with the value: - // 0x00000004 [2] CLR2 (0) When a write to one of these bits occurs, with the value: - // 0x00000002 [1] CLR1 (0) When a write to one of these bits occurs, with the value: - // 0x00000001 [0] CLR0 (0) When a write to one of these bits occurs, with the value: - io_rw_32 trcclaimclr; - - uint32_t _pad60[4]; - - _REG_(M33_TRCAUTHSTATUS_OFFSET) // M33_TRCAUTHSTATUS - // Returns the level of tracing that the trace unit can support - // 0x000000c0 [7:6] SNID (0x0) Indicates whether the system enables the trace unit to... - // 0x00000030 [5:4] SID (0x0) Indicates whether the trace unit supports Secure invasive debug: - // 0x0000000c [3:2] NSNID (0x0) Indicates whether the system enables the trace unit to... - // 0x00000003 [1:0] NSID (0x0) Indicates whether the trace unit supports Non-secure... - io_ro_32 trcauthstatus; - - _REG_(M33_TRCDEVARCH_OFFSET) // M33_TRCDEVARCH - // TRCDEVARCH - // 0xffe00000 [31:21] ARCHITECT (0x23b) reads as 0b01000111011 - // 0x00100000 [20] PRESENT (1) reads as 0b1 - // 0x000f0000 [19:16] REVISION (0x2) reads as 0b0000 - // 0x0000ffff [15:0] ARCHID (0x4a13) reads as 0b0100101000010011 - io_ro_32 trcdevarch; - - uint32_t _pad61[2]; - - _REG_(M33_TRCDEVID_OFFSET) // M33_TRCDEVID - // TRCDEVID - // 0x00000000 [31:0] TRCDEVID (0x00000000) - io_rw_32 trcdevid; - - _REG_(M33_TRCDEVTYPE_OFFSET) // M33_TRCDEVTYPE - // TRCDEVTYPE - // 0x000000f0 [7:4] SUB (0x1) reads as 0b0001 - // 0x0000000f [3:0] MAJOR (0x3) reads as 0b0011 - io_ro_32 trcdevtype; - - _REG_(M33_TRCPIDR4_OFFSET) // M33_TRCPIDR4 - // TRCPIDR4 - // 0x000000f0 [7:4] SIZE (0x0) reads as `ImpDef - // 0x0000000f [3:0] DES_2 (0x4) reads as `ImpDef - io_ro_32 trcpidr4; - - _REG_(M33_TRCPIDR5_OFFSET) // M33_TRCPIDR5 - // TRCPIDR5 - // 0x00000000 [31:0] TRCPIDR5 (0x00000000) - io_rw_32 trcpidr5; - - _REG_(M33_TRCPIDR6_OFFSET) // M33_TRCPIDR6 - // TRCPIDR6 - // 0x00000000 [31:0] TRCPIDR6 (0x00000000) - io_rw_32 trcpidr6; - - _REG_(M33_TRCPIDR7_OFFSET) // M33_TRCPIDR7 - // TRCPIDR7 - // 0x00000000 [31:0] TRCPIDR7 (0x00000000) - io_rw_32 trcpidr7; - - _REG_(M33_TRCPIDR0_OFFSET) // M33_TRCPIDR0 - // TRCPIDR0 - // 0x000000ff [7:0] PART_0 (0x21) reads as `ImpDef - io_ro_32 trcpidr0; - - _REG_(M33_TRCPIDR1_OFFSET) // M33_TRCPIDR1 - // TRCPIDR1 - // 0x000000f0 [7:4] DES_0 (0xb) reads as `ImpDef - // 0x0000000f [3:0] PART_0 (0xd) reads as `ImpDef - io_ro_32 trcpidr1; - - _REG_(M33_TRCPIDR2_OFFSET) // M33_TRCPIDR2 - // TRCPIDR2 - // 0x000000f0 [7:4] REVISION (0x2) reads as `ImpDef - // 0x00000008 [3] JEDEC (1) reads as 0b1 - // 0x00000007 [2:0] DES_0 (0x3) reads as `ImpDef - io_ro_32 trcpidr2; - - _REG_(M33_TRCPIDR3_OFFSET) // M33_TRCPIDR3 - // TRCPIDR3 - // 0x000000f0 [7:4] REVAND (0x0) reads as `ImpDef - // 0x0000000f [3:0] CMOD (0x0) reads as `ImpDef - io_ro_32 trcpidr3; - - // (Description copied from array index 0 register M33_TRCCIDR0 applies similarly to other array indexes) - _REG_(M33_TRCCIDR0_OFFSET) // M33_TRCCIDR0 - // TRCCIDR0 - // 0x000000ff [7:0] PRMBL_0 (0x0d) reads as 0b00001101 - io_ro_32 trccidr[4]; - - _REG_(M33_CTICONTROL_OFFSET) // M33_CTICONTROL - // CTI Control Register - // 0x00000001 [0] GLBEN (0) Enables or disables the CTI - io_rw_32 cticontrol; - - uint32_t _pad62[3]; - - _REG_(M33_CTIINTACK_OFFSET) // M33_CTIINTACK - // CTI Interrupt Acknowledge Register - // 0x000000ff [7:0] INTACK (0x00) Acknowledges the corresponding ctitrigout output - io_rw_32 ctiintack; - - _REG_(M33_CTIAPPSET_OFFSET) // M33_CTIAPPSET - // CTI Application Trigger Set Register - // 0x0000000f [3:0] APPSET (0x0) Setting a bit HIGH generates a channel event for the... - io_rw_32 ctiappset; - - _REG_(M33_CTIAPPCLEAR_OFFSET) // M33_CTIAPPCLEAR - // CTI Application Trigger Clear Register - // 0x0000000f [3:0] APPCLEAR (0x0) Sets the corresponding bits in the CTIAPPSET to 0 - io_rw_32 ctiappclear; - - _REG_(M33_CTIAPPPULSE_OFFSET) // M33_CTIAPPPULSE - // CTI Application Pulse Register - // 0x0000000f [3:0] APPULSE (0x0) Setting a bit HIGH generates a channel event pulse for... - io_rw_32 ctiapppulse; - - // (Description copied from array index 0 register M33_CTIINEN0 applies similarly to other array indexes) - _REG_(M33_CTIINEN0_OFFSET) // M33_CTIINEN0 - // CTI Trigger to Channel Enable Registers - // 0x0000000f [3:0] TRIGINEN (0x0) Enables a cross trigger event to the corresponding... - io_rw_32 ctiinen[8]; - - uint32_t _pad63[24]; - - // (Description copied from array index 0 register M33_CTIOUTEN0 applies similarly to other array indexes) - _REG_(M33_CTIOUTEN0_OFFSET) // M33_CTIOUTEN0 - // CTI Trigger to Channel Enable Registers - // 0x0000000f [3:0] TRIGOUTEN (0x0) Enables a cross trigger event to ctitrigout when the... - io_rw_32 ctiouten[8]; - - uint32_t _pad64[28]; - - _REG_(M33_CTITRIGINSTATUS_OFFSET) // M33_CTITRIGINSTATUS - // CTI Trigger to Channel Enable Registers - // 0x000000ff [7:0] TRIGINSTATUS (0x00) Shows the status of the ctitrigin inputs - io_ro_32 ctitriginstatus; - - _REG_(M33_CTITRIGOUTSTATUS_OFFSET) // M33_CTITRIGOUTSTATUS - // CTI Trigger In Status Register - // 0x000000ff [7:0] TRIGOUTSTATUS (0x00) Shows the status of the ctitrigout outputs - io_ro_32 ctitrigoutstatus; - - _REG_(M33_CTICHINSTATUS_OFFSET) // M33_CTICHINSTATUS - // CTI Channel In Status Register - // 0x0000000f [3:0] CTICHOUTSTATUS (0x0) Shows the status of the ctichout outputs - io_ro_32 ctichinstatus; - - uint32_t _pad65; - - _REG_(M33_CTIGATE_OFFSET) // M33_CTIGATE - // Enable CTI Channel Gate register - // 0x00000008 [3] CTIGATEEN3 (1) Enable ctichout3 - // 0x00000004 [2] CTIGATEEN2 (1) Enable ctichout2 - // 0x00000002 [1] CTIGATEEN1 (1) Enable ctichout1 - // 0x00000001 [0] CTIGATEEN0 (1) Enable ctichout0 - io_rw_32 ctigate; - - _REG_(M33_ASICCTL_OFFSET) // M33_ASICCTL - // External Multiplexer Control register - // 0x00000000 [31:0] ASICCTL (0x00000000) - io_rw_32 asicctl; - - uint32_t _pad66[871]; - - _REG_(M33_ITCHOUT_OFFSET) // M33_ITCHOUT - // Integration Test Channel Output register - // 0x0000000f [3:0] CTCHOUT (0x0) Sets the value of the ctichout outputs - io_rw_32 itchout; - - _REG_(M33_ITTRIGOUT_OFFSET) // M33_ITTRIGOUT - // Integration Test Trigger Output register - // 0x000000ff [7:0] CTTRIGOUT (0x00) Sets the value of the ctitrigout outputs - io_rw_32 ittrigout; - - uint32_t _pad67[2]; - - _REG_(M33_ITCHIN_OFFSET) // M33_ITCHIN - // Integration Test Channel Input register - // 0x0000000f [3:0] CTCHIN (0x0) Reads the value of the ctichin inputs - io_ro_32 itchin; - - uint32_t _pad68[2]; - - _REG_(M33_ITCTRL_OFFSET) // M33_ITCTRL - // Integration Mode Control register - // 0x00000001 [0] IME (0) Integration Mode Enable - io_rw_32 itctrl; - - uint32_t _pad69[46]; - - _REG_(M33_DEVARCH_OFFSET) // M33_DEVARCH - // Device Architecture register - // 0xffe00000 [31:21] ARCHITECT (0x23b) Indicates the component architect - // 0x00100000 [20] PRESENT (1) Indicates whether the DEVARCH register is present - // 0x000f0000 [19:16] REVISION (0x0) Indicates the architecture revision - // 0x0000ffff [15:0] ARCHID (0x1a14) Indicates the component - io_ro_32 devarch; - - uint32_t _pad70[2]; - - _REG_(M33_DEVID_OFFSET) // M33_DEVID - // Device Configuration register - // 0x000f0000 [19:16] NUMCH (0x4) Number of ECT channels available - // 0x0000ff00 [15:8] NUMTRIG (0x08) Number of ECT triggers available - // 0x0000001f [4:0] EXTMUXNUM (0x00) Indicates the number of multiplexers available on... - io_ro_32 devid; - - _REG_(M33_DEVTYPE_OFFSET) // M33_DEVTYPE - // Device Type Identifier register - // 0x000000f0 [7:4] SUB (0x1) Sub-classification of the type of the debug component as... - // 0x0000000f [3:0] MAJOR (0x4) Major classification of the type of the debug component... - io_ro_32 devtype; - - _REG_(M33_PIDR4_OFFSET) // M33_PIDR4 - // CoreSight Peripheral ID4 - // 0x000000f0 [7:4] SIZE (0x0) Always 0b0000 - // 0x0000000f [3:0] DES_2 (0x4) Together, PIDR1 - io_ro_32 pidr4; - - _REG_(M33_PIDR5_OFFSET) // M33_PIDR5 - // CoreSight Peripheral ID5 - // 0x00000000 [31:0] PIDR5 (0x00000000) - io_rw_32 pidr5; - - _REG_(M33_PIDR6_OFFSET) // M33_PIDR6 - // CoreSight Peripheral ID6 - // 0x00000000 [31:0] PIDR6 (0x00000000) - io_rw_32 pidr6; - - _REG_(M33_PIDR7_OFFSET) // M33_PIDR7 - // CoreSight Peripheral ID7 - // 0x00000000 [31:0] PIDR7 (0x00000000) - io_rw_32 pidr7; - - _REG_(M33_PIDR0_OFFSET) // M33_PIDR0 - // CoreSight Peripheral ID0 - // 0x000000ff [7:0] PART_0 (0x21) Bits[7:0] of the 12-bit part number of the component - io_ro_32 pidr0; - - _REG_(M33_PIDR1_OFFSET) // M33_PIDR1 - // CoreSight Peripheral ID1 - // 0x000000f0 [7:4] DES_0 (0xb) Together, PIDR1 - // 0x0000000f [3:0] PART_1 (0xd) Bits[11:8] of the 12-bit part number of the component - io_ro_32 pidr1; - - _REG_(M33_PIDR2_OFFSET) // M33_PIDR2 - // CoreSight Peripheral ID2 - // 0x000000f0 [7:4] REVISION (0x0) This device is at r1p0 - // 0x00000008 [3] JEDEC (1) Always 1 - // 0x00000007 [2:0] DES_1 (0x3) Together, PIDR1 - io_ro_32 pidr2; - - _REG_(M33_PIDR3_OFFSET) // M33_PIDR3 - // CoreSight Peripheral ID3 - // 0x000000f0 [7:4] REVAND (0x0) Indicates minor errata fixes specific to the revision of... - // 0x0000000f [3:0] CMOD (0x0) Customer Modified - io_ro_32 pidr3; - - // (Description copied from array index 0 register M33_CIDR0 applies similarly to other array indexes) - _REG_(M33_CIDR0_OFFSET) // M33_CIDR0 - // CoreSight Component ID0 - // 0x000000ff [7:0] PRMBL_0 (0x0d) Preamble[0] - io_ro_32 cidr[4]; -} m33_hw_t; - -#define m33_hw ((m33_hw_t *)PPB_BASE) -#define m33_ns_hw ((m33_hw_t *)PPB_NONSEC_BASE) -static_assert(sizeof (m33_hw_t) == 0x43000, ""); - -#endif // _HARDWARE_STRUCTS_M33_H - diff --git a/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/m33_eppb.h b/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/m33_eppb.h deleted file mode 100644 index 3b271e6f00..0000000000 --- a/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/m33_eppb.h +++ /dev/null @@ -1,50 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _HARDWARE_STRUCTS_M33_EPPB_H -#define _HARDWARE_STRUCTS_M33_EPPB_H - -/** - * \file rp2350/m33_eppb.h - */ - -#include "hardware/address_mapped.h" -#include "hardware/regs/m33_eppb.h" - -// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_m33_eppb -// -// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) -// _REG_(x) will link to the corresponding register in hardware/regs/m33_eppb.h. -// -// Bit-field descriptions are of the form: -// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION - -#if defined(__riscv) && PICO_FORBID_ARM_HEADERS_ON_RISCV -#error "Arm header included in a RISC-V build with PICO_FORBID_ARM_HEADERS_ON_RISCV=1" -#endif - - -typedef struct { - // (Description copied from array index 0 register M33_EPPB_NMI_MASK0 applies similarly to other array indexes) - _REG_(M33_EPPB_NMI_MASK0_OFFSET) // M33_EPPB_NMI_MASK0 - // NMI mask for IRQs 0 through 31 - // 0xffffffff [31:0] NMI_MASK0 (0x00000000) - io_rw_32 nmi_mask[2]; - - _REG_(M33_EPPB_SLEEPCTRL_OFFSET) // M33_EPPB_SLEEPCTRL - // Nonstandard sleep control register - // 0x00000004 [2] WICENACK (0) Status signal from the processor's interrupt controller - // 0x00000002 [1] WICENREQ (1) Request that the next processor deep sleep is a WIC sleep - // 0x00000001 [0] LIGHT_SLEEP (0) By default, any processor sleep will deassert the... - io_rw_32 sleepctrl; -} m33_eppb_hw_t; - -#define eppb_hw ((m33_eppb_hw_t *)EPPB_BASE) -static_assert(sizeof (m33_eppb_hw_t) == 0x000c, ""); - -#endif // _HARDWARE_STRUCTS_M33_EPPB_H - diff --git a/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/mpu.h b/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/mpu.h deleted file mode 100644 index e3bf920d19..0000000000 --- a/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/mpu.h +++ /dev/null @@ -1,126 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _HARDWARE_STRUCTS_MPU_H -#define _HARDWARE_STRUCTS_MPU_H - -/** - * \file rp2350/mpu.h - */ - -#include "hardware/address_mapped.h" -#include "hardware/regs/m33.h" - -// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_m33 -// -// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) -// _REG_(x) will link to the corresponding register in hardware/regs/m33.h. -// -// Bit-field descriptions are of the form: -// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION - -#if defined(__riscv) && PICO_FORBID_ARM_HEADERS_ON_RISCV -#error "Arm header included in a RISC-V build with PICO_FORBID_ARM_HEADERS_ON_RISCV=1" -#endif - -typedef struct { - _REG_(M33_MPU_TYPE_OFFSET) // M33_MPU_TYPE - // The MPU Type Register indicates how many regions the MPU `FTSSS supports - // 0x0000ff00 [15:8] DREGION (0x08) Number of regions supported by the MPU - // 0x00000001 [0] SEPARATE (0) Indicates support for separate instructions and data... - io_ro_32 type; - - _REG_(M33_MPU_CTRL_OFFSET) // M33_MPU_CTRL - // Enables the MPU and, when the MPU is enabled, controls whether the default memory map is enabled... - // 0x00000004 [2] PRIVDEFENA (0) Controls whether the default memory map is enabled for... - // 0x00000002 [1] HFNMIENA (0) Controls whether handlers executing with priority less... - // 0x00000001 [0] ENABLE (0) Enables the MPU - io_rw_32 ctrl; - - _REG_(M33_MPU_RNR_OFFSET) // M33_MPU_RNR - // Selects the region currently accessed by MPU_RBAR and MPU_RLAR - // 0x00000007 [2:0] REGION (0x0) Indicates the memory region accessed by MPU_RBAR and MPU_RLAR - io_rw_32 rnr; - - _REG_(M33_MPU_RBAR_OFFSET) // M33_MPU_RBAR - // Provides indirect read and write access to the base address of the currently selected MPU region `FTSSS - // 0xffffffe0 [31:5] BASE (0x0000000) Contains bits [31:5] of the lower inclusive limit of the... - // 0x00000018 [4:3] SH (0x0) Defines the Shareability domain of this region for Normal memory - // 0x00000006 [2:1] AP (0x0) Defines the access permissions for this region - // 0x00000001 [0] XN (0) Defines whether code can be executed from this region - io_rw_32 rbar; - - _REG_(M33_MPU_RLAR_OFFSET) // M33_MPU_RLAR - // Provides indirect read and write access to the limit address of the currently selected MPU region `FTSSS - // 0xffffffe0 [31:5] LIMIT (0x0000000) Contains bits [31:5] of the upper inclusive limit of the... - // 0x0000000e [3:1] ATTRINDX (0x0) Associates a set of attributes in the MPU_MAIR0 and... - // 0x00000001 [0] EN (0) Region enable - io_rw_32 rlar; - - _REG_(M33_MPU_RBAR_A1_OFFSET) // M33_MPU_RBAR_A1 - // Provides indirect read and write access to the base address of the MPU region selected by... - // 0xffffffe0 [31:5] BASE (0x0000000) Contains bits [31:5] of the lower inclusive limit of the... - // 0x00000018 [4:3] SH (0x0) Defines the Shareability domain of this region for Normal memory - // 0x00000006 [2:1] AP (0x0) Defines the access permissions for this region - // 0x00000001 [0] XN (0) Defines whether code can be executed from this region - io_rw_32 rbar_a1; - - _REG_(M33_MPU_RLAR_A1_OFFSET) // M33_MPU_RLAR_A1 - // Provides indirect read and write access to the limit address of the currently selected MPU... - // 0xffffffe0 [31:5] LIMIT (0x0000000) Contains bits [31:5] of the upper inclusive limit of the... - // 0x0000000e [3:1] ATTRINDX (0x0) Associates a set of attributes in the MPU_MAIR0 and... - // 0x00000001 [0] EN (0) Region enable - io_rw_32 rlar_a1; - - _REG_(M33_MPU_RBAR_A2_OFFSET) // M33_MPU_RBAR_A2 - // Provides indirect read and write access to the base address of the MPU region selected by... - // 0xffffffe0 [31:5] BASE (0x0000000) Contains bits [31:5] of the lower inclusive limit of the... - // 0x00000018 [4:3] SH (0x0) Defines the Shareability domain of this region for Normal memory - // 0x00000006 [2:1] AP (0x0) Defines the access permissions for this region - // 0x00000001 [0] XN (0) Defines whether code can be executed from this region - io_rw_32 rbar_a2; - - _REG_(M33_MPU_RLAR_A2_OFFSET) // M33_MPU_RLAR_A2 - // Provides indirect read and write access to the limit address of the currently selected MPU... - // 0xffffffe0 [31:5] LIMIT (0x0000000) Contains bits [31:5] of the upper inclusive limit of the... - // 0x0000000e [3:1] ATTRINDX (0x0) Associates a set of attributes in the MPU_MAIR0 and... - // 0x00000001 [0] EN (0) Region enable - io_rw_32 rlar_a2; - - _REG_(M33_MPU_RBAR_A3_OFFSET) // M33_MPU_RBAR_A3 - // Provides indirect read and write access to the base address of the MPU region selected by... - // 0xffffffe0 [31:5] BASE (0x0000000) Contains bits [31:5] of the lower inclusive limit of the... - // 0x00000018 [4:3] SH (0x0) Defines the Shareability domain of this region for Normal memory - // 0x00000006 [2:1] AP (0x0) Defines the access permissions for this region - // 0x00000001 [0] XN (0) Defines whether code can be executed from this region - io_rw_32 rbar_a3; - - _REG_(M33_MPU_RLAR_A3_OFFSET) // M33_MPU_RLAR_A3 - // Provides indirect read and write access to the limit address of the currently selected MPU... - // 0xffffffe0 [31:5] LIMIT (0x0000000) Contains bits [31:5] of the upper inclusive limit of the... - // 0x0000000e [3:1] ATTRINDX (0x0) Associates a set of attributes in the MPU_MAIR0 and... - // 0x00000001 [0] EN (0) Region enable - io_rw_32 rlar_a3; - - uint32_t _pad0; - - // (Description copied from array index 0 register M33_MPU_MAIR0 applies similarly to other array indexes) - _REG_(M33_MPU_MAIR0_OFFSET) // M33_MPU_MAIR0 - // Along with MPU_MAIR1, provides the memory attribute encodings corresponding to the AttrIndex values - // 0xff000000 [31:24] ATTR3 (0x00) Memory attribute encoding for MPU regions with an AttrIndex of 3 - // 0x00ff0000 [23:16] ATTR2 (0x00) Memory attribute encoding for MPU regions with an AttrIndex of 2 - // 0x0000ff00 [15:8] ATTR1 (0x00) Memory attribute encoding for MPU regions with an AttrIndex of 1 - // 0x000000ff [7:0] ATTR0 (0x00) Memory attribute encoding for MPU regions with an AttrIndex of 0 - io_rw_32 mair[2]; -} mpu_hw_t; - -#define mpu_hw ((mpu_hw_t *)(PPB_BASE + M33_MPU_TYPE_OFFSET)) -#define mpu_ns_hw ((mpu_hw_t *)(PPB_NONSEC_BASE + M33_MPU_TYPE_OFFSET)) -static_assert(sizeof (mpu_hw_t) == 0x0038, ""); - -#endif // _HARDWARE_STRUCTS_MPU_H - diff --git a/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/nvic.h b/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/nvic.h deleted file mode 100644 index c0c7b76bde..0000000000 --- a/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/nvic.h +++ /dev/null @@ -1,94 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _HARDWARE_STRUCTS_NVIC_H -#define _HARDWARE_STRUCTS_NVIC_H - -/** - * \file rp2350/nvic.h - */ - -#include "hardware/address_mapped.h" -#include "hardware/regs/m33.h" - -// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_m33 -// -// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) -// _REG_(x) will link to the corresponding register in hardware/regs/m33.h. -// -// Bit-field descriptions are of the form: -// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION - -#if defined(__riscv) && PICO_FORBID_ARM_HEADERS_ON_RISCV -#error "Arm header included in a RISC-V build with PICO_FORBID_ARM_HEADERS_ON_RISCV=1" -#endif - -typedef struct { - // (Description copied from array index 0 register M33_NVIC_ISER0 applies similarly to other array indexes) - _REG_(M33_NVIC_ISER0_OFFSET) // M33_NVIC_ISER0 - // Enables or reads the enabled state of each group of 32 interrupts - // 0xffffffff [31:0] SETENA (0x00000000) For SETENA[m] in NVIC_ISER*n, indicates whether... - io_rw_32 iser[2]; - - uint32_t _pad0[30]; - - // (Description copied from array index 0 register M33_NVIC_ICER0 applies similarly to other array indexes) - _REG_(M33_NVIC_ICER0_OFFSET) // M33_NVIC_ICER0 - // Clears or reads the enabled state of each group of 32 interrupts - // 0xffffffff [31:0] CLRENA (0x00000000) For CLRENA[m] in NVIC_ICER*n, indicates whether... - io_rw_32 icer[2]; - - uint32_t _pad1[30]; - - // (Description copied from array index 0 register M33_NVIC_ISPR0 applies similarly to other array indexes) - _REG_(M33_NVIC_ISPR0_OFFSET) // M33_NVIC_ISPR0 - // Enables or reads the pending state of each group of 32 interrupts - // 0xffffffff [31:0] SETPEND (0x00000000) For SETPEND[m] in NVIC_ISPR*n, indicates whether... - io_rw_32 ispr[2]; - - uint32_t _pad2[30]; - - // (Description copied from array index 0 register M33_NVIC_ICPR0 applies similarly to other array indexes) - _REG_(M33_NVIC_ICPR0_OFFSET) // M33_NVIC_ICPR0 - // Clears or reads the pending state of each group of 32 interrupts - // 0xffffffff [31:0] CLRPEND (0x00000000) For CLRPEND[m] in NVIC_ICPR*n, indicates whether... - io_rw_32 icpr[2]; - - uint32_t _pad3[30]; - - // (Description copied from array index 0 register M33_NVIC_IABR0 applies similarly to other array indexes) - _REG_(M33_NVIC_IABR0_OFFSET) // M33_NVIC_IABR0 - // For each group of 32 interrupts, shows the active state of each interrupt - // 0xffffffff [31:0] ACTIVE (0x00000000) For ACTIVE[m] in NVIC_IABR*n, indicates the active state... - io_rw_32 iabr[2]; - - uint32_t _pad4[30]; - - // (Description copied from array index 0 register M33_NVIC_ITNS0 applies similarly to other array indexes) - _REG_(M33_NVIC_ITNS0_OFFSET) // M33_NVIC_ITNS0 - // For each group of 32 interrupts, determines whether each interrupt targets Non-secure or Secure state - // 0xffffffff [31:0] ITNS (0x00000000) For ITNS[m] in NVIC_ITNS*n, `IAAMO the target Security... - io_rw_32 itns[2]; - - uint32_t _pad5[30]; - - // (Description copied from array index 0 register M33_NVIC_IPR0 applies similarly to other array indexes) - _REG_(M33_NVIC_IPR0_OFFSET) // M33_NVIC_IPR0 - // Sets or reads interrupt priorities - // 0xf0000000 [31:28] PRI_N3 (0x0) For register NVIC_IPRn, the priority of interrupt number... - // 0x00f00000 [23:20] PRI_N2 (0x0) For register NVIC_IPRn, the priority of interrupt number... - // 0x0000f000 [15:12] PRI_N1 (0x0) For register NVIC_IPRn, the priority of interrupt number... - // 0x000000f0 [7:4] PRI_N0 (0x0) For register NVIC_IPRn, the priority of interrupt number... - io_rw_32 ipr[16]; -} nvic_hw_t; - -#define nvic_hw ((nvic_hw_t *)(PPB_BASE + M33_NVIC_ISER0_OFFSET)) -#define nvic_ns_hw ((nvic_hw_t *)(PPB_NONSEC_BASE + M33_NVIC_ISER0_OFFSET)) -static_assert(sizeof (nvic_hw_t) == 0x0340, ""); - -#endif // _HARDWARE_STRUCTS_NVIC_H - diff --git a/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/otp.h b/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/otp.h deleted file mode 100644 index 803643b86e..0000000000 --- a/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/otp.h +++ /dev/null @@ -1,192 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _HARDWARE_STRUCTS_OTP_H -#define _HARDWARE_STRUCTS_OTP_H - -/** - * \file rp2350/otp.h - */ - -#include "hardware/address_mapped.h" -#include "hardware/regs/otp.h" - -// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_otp -// -// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) -// _REG_(x) will link to the corresponding register in hardware/regs/otp.h. -// -// Bit-field descriptions are of the form: -// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION - -typedef struct { - // (Description copied from array index 0 register OTP_SW_LOCK0 applies similarly to other array indexes) - _REG_(OTP_SW_LOCK0_OFFSET) // OTP_SW_LOCK0 - // Software lock register for page 0. - // 0x0000000c [3:2] NSEC (-) Non-secure lock status - // 0x00000003 [1:0] SEC (-) Secure lock status - io_rw_32 sw_lock[64]; - - _REG_(OTP_SBPI_INSTR_OFFSET) // OTP_SBPI_INSTR - // Dispatch instructions to the SBPI interface, used for programming the OTP fuses - // 0x40000000 [30] EXEC (0) Execute instruction - // 0x20000000 [29] IS_WR (0) Payload type is write - // 0x10000000 [28] HAS_PAYLOAD (0) Instruction has payload (data to be written or to be read) - // 0x0f000000 [27:24] PAYLOAD_SIZE_M1 (0x0) Instruction payload size in bytes minus 1 - // 0x00ff0000 [23:16] TARGET (0x00) Instruction target, it can be PMC (0x3a) or DAP (0x02) - // 0x0000ff00 [15:8] CMD (0x00) - // 0x000000ff [7:0] SHORT_WDATA (0x00) wdata to be used only when payload_size_m1=0 - io_rw_32 sbpi_instr; - - // (Description copied from array index 0 register OTP_SBPI_WDATA_0 applies similarly to other array indexes) - _REG_(OTP_SBPI_WDATA_0_OFFSET) // OTP_SBPI_WDATA_0 - // SBPI write payload bytes 3 - // 0xffffffff [31:0] SBPI_WDATA_0 (0x00000000) - io_rw_32 sbpi_wdata[4]; - - // (Description copied from array index 0 register OTP_SBPI_RDATA_0 applies similarly to other array indexes) - _REG_(OTP_SBPI_RDATA_0_OFFSET) // OTP_SBPI_RDATA_0 - // Read payload bytes 3 - // 0xffffffff [31:0] SBPI_RDATA_0 (0x00000000) - io_ro_32 sbpi_rdata[4]; - - _REG_(OTP_SBPI_STATUS_OFFSET) // OTP_SBPI_STATUS - // 0x00ff0000 [23:16] MISO (-) SBPI MISO (master in - slave out): response from SBPI - // 0x00001000 [12] FLAG (-) SBPI flag - // 0x00000100 [8] INSTR_MISS (0) Last instruction missed (dropped), as the previous has... - // 0x00000010 [4] INSTR_DONE (0) Last instruction done - // 0x00000001 [0] RDATA_VLD (0) Read command has returned data - io_rw_32 sbpi_status; - - _REG_(OTP_USR_OFFSET) // OTP_USR - // Controls for APB data read interface (USER interface) - // 0x00000010 [4] PD (0) Power-down; 1 disables current reference - // 0x00000001 [0] DCTRL (1) 1 enables USER interface; 0 disables USER interface... - io_rw_32 usr; - - _REG_(OTP_DBG_OFFSET) // OTP_DBG - // Debug for OTP power-on state machine - // 0x00001000 [12] CUSTOMER_RMA_FLAG (-) The chip is in RMA mode - // 0x000000f0 [7:4] PSM_STATE (-) Monitor the PSM FSM's state - // 0x00000008 [3] ROSC_UP (-) Ring oscillator is up and running - // 0x00000004 [2] ROSC_UP_SEEN (0) Ring oscillator was seen up and running - // 0x00000002 [1] BOOT_DONE (-) PSM boot done status flag - // 0x00000001 [0] PSM_DONE (-) PSM done status flag - io_rw_32 dbg; - - uint32_t _pad0; - - _REG_(OTP_BIST_OFFSET) // OTP_BIST - // During BIST, count address locations that have at least one leaky bit - // 0x40000000 [30] CNT_FAIL (-) Flag if the count of address locations with at least one... - // 0x20000000 [29] CNT_CLR (0) Clear counter before use - // 0x10000000 [28] CNT_ENA (0) Enable the counter before the BIST function is initiated - // 0x0fff0000 [27:16] CNT_MAX (0xfff) The cnt_fail flag will be set if the number of leaky... - // 0x00001fff [12:0] CNT (-) Number of locations that have at least one leaky bit - io_rw_32 bist; - - // (Description copied from array index 0 register OTP_CRT_KEY_W0 applies similarly to other array indexes) - _REG_(OTP_CRT_KEY_W0_OFFSET) // OTP_CRT_KEY_W0 - // Word 0 (bits 31 - // 0xffffffff [31:0] CRT_KEY_W0 (0x00000000) - io_wo_32 crt_key_w[4]; - - _REG_(OTP_CRITICAL_OFFSET) // OTP_CRITICAL - // Quickly check values of critical flags read during boot up - // 0x00020000 [17] RISCV_DISABLE (0) - // 0x00010000 [16] ARM_DISABLE (0) - // 0x00000060 [6:5] GLITCH_DETECTOR_SENS (0x0) - // 0x00000010 [4] GLITCH_DETECTOR_ENABLE (0) - // 0x00000008 [3] DEFAULT_ARCHSEL (0) - // 0x00000004 [2] DEBUG_DISABLE (0) - // 0x00000002 [1] SECURE_DEBUG_DISABLE (0) - // 0x00000001 [0] SECURE_BOOT_ENABLE (0) - io_ro_32 critical; - - _REG_(OTP_KEY_VALID_OFFSET) // OTP_KEY_VALID - // Which keys were valid (enrolled) at boot time - // 0x000000ff [7:0] KEY_VALID (0x00) - io_ro_32 key_valid; - - _REG_(OTP_DEBUGEN_OFFSET) // OTP_DEBUGEN - // Enable a debug feature that has been disabled. Debug features are disabled if one of the relevant critical boot flags is set in OTP (DEBUG_DISABLE or SECURE_DEBUG_DISABLE), OR if a debug key is marked valid in OTP, and the matching key value has not been supplied over SWD. - // 0x00000100 [8] MISC (0) Enable other debug components - // 0x00000008 [3] PROC1_SECURE (0) Permit core 1's Mem-AP to generate Secure accesses,... - // 0x00000004 [2] PROC1 (0) Enable core 1's Mem-AP if it is currently disabled - // 0x00000002 [1] PROC0_SECURE (0) Permit core 0's Mem-AP to generate Secure accesses,... - // 0x00000001 [0] PROC0 (0) Enable core 0's Mem-AP if it is currently disabled - io_rw_32 debugen; - - _REG_(OTP_DEBUGEN_LOCK_OFFSET) // OTP_DEBUGEN_LOCK - // Write 1s to lock corresponding bits in DEBUGEN - // 0x00000100 [8] MISC (0) Write 1 to lock the MISC bit of DEBUGEN - // 0x00000008 [3] PROC1_SECURE (0) Write 1 to lock the PROC1_SECURE bit of DEBUGEN - // 0x00000004 [2] PROC1 (0) Write 1 to lock the PROC1 bit of DEBUGEN - // 0x00000002 [1] PROC0_SECURE (0) Write 1 to lock the PROC0_SECURE bit of DEBUGEN - // 0x00000001 [0] PROC0 (0) Write 1 to lock the PROC0 bit of DEBUGEN - io_rw_32 debugen_lock; - - _REG_(OTP_ARCHSEL_OFFSET) // OTP_ARCHSEL - // Architecture select (Arm/RISC-V), applied on next processor reset. The default and allowable values of this register are constrained by the critical boot flags. - // 0x00000002 [1] CORE1 (0) Select architecture for core 1 - // 0x00000001 [0] CORE0 (0) Select architecture for core 0 - io_rw_32 archsel; - - _REG_(OTP_ARCHSEL_STATUS_OFFSET) // OTP_ARCHSEL_STATUS - // Get the current architecture select state of each core - // 0x00000002 [1] CORE1 (0) Current architecture for core 0 - // 0x00000001 [0] CORE0 (0) Current architecture for core 0 - io_ro_32 archsel_status; - - _REG_(OTP_BOOTDIS_OFFSET) // OTP_BOOTDIS - // Tell the bootrom to ignore scratch register boot vectors (both power manager and watchdog) on the next power up. - // 0x00000002 [1] NEXT (0) This flag always ORs writes into its current contents - // 0x00000001 [0] NOW (0) When the core is powered down, the current value of... - io_rw_32 bootdis; - - _REG_(OTP_INTR_OFFSET) // OTP_INTR - // Raw Interrupts - // 0x00000010 [4] APB_RD_NSEC_FAIL (0) - // 0x00000008 [3] APB_RD_SEC_FAIL (0) - // 0x00000004 [2] APB_DCTRL_FAIL (0) - // 0x00000002 [1] SBPI_WR_FAIL (0) - // 0x00000001 [0] SBPI_FLAG_N (0) - io_rw_32 intr; - - _REG_(OTP_INTE_OFFSET) // OTP_INTE - // Interrupt Enable - // 0x00000010 [4] APB_RD_NSEC_FAIL (0) - // 0x00000008 [3] APB_RD_SEC_FAIL (0) - // 0x00000004 [2] APB_DCTRL_FAIL (0) - // 0x00000002 [1] SBPI_WR_FAIL (0) - // 0x00000001 [0] SBPI_FLAG_N (0) - io_rw_32 inte; - - _REG_(OTP_INTF_OFFSET) // OTP_INTF - // Interrupt Force - // 0x00000010 [4] APB_RD_NSEC_FAIL (0) - // 0x00000008 [3] APB_RD_SEC_FAIL (0) - // 0x00000004 [2] APB_DCTRL_FAIL (0) - // 0x00000002 [1] SBPI_WR_FAIL (0) - // 0x00000001 [0] SBPI_FLAG_N (0) - io_rw_32 intf; - - _REG_(OTP_INTS_OFFSET) // OTP_INTS - // Interrupt status after masking & forcing - // 0x00000010 [4] APB_RD_NSEC_FAIL (0) - // 0x00000008 [3] APB_RD_SEC_FAIL (0) - // 0x00000004 [2] APB_DCTRL_FAIL (0) - // 0x00000002 [1] SBPI_WR_FAIL (0) - // 0x00000001 [0] SBPI_FLAG_N (0) - io_ro_32 ints; -} otp_hw_t; - -#define otp_hw ((otp_hw_t *)OTP_BASE) -static_assert(sizeof (otp_hw_t) == 0x0174, ""); - -#endif // _HARDWARE_STRUCTS_OTP_H - diff --git a/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/pads_bank0.h b/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/pads_bank0.h deleted file mode 100644 index bf0f4a53f1..0000000000 --- a/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/pads_bank0.h +++ /dev/null @@ -1,49 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _HARDWARE_STRUCTS_PADS_BANK0_H -#define _HARDWARE_STRUCTS_PADS_BANK0_H - -/** - * \file rp2350/pads_bank0.h - */ - -#include "hardware/address_mapped.h" -#include "hardware/regs/pads_bank0.h" - -// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_pads_bank0 -// -// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) -// _REG_(x) will link to the corresponding register in hardware/regs/pads_bank0.h. -// -// Bit-field descriptions are of the form: -// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION - -typedef struct { - _REG_(PADS_BANK0_VOLTAGE_SELECT_OFFSET) // PADS_BANK0_VOLTAGE_SELECT - // Voltage select - // 0x00000001 [0] VOLTAGE_SELECT (0) - io_rw_32 voltage_select; - - // (Description copied from array index 0 register PADS_BANK0_GPIO0 applies similarly to other array indexes) - _REG_(PADS_BANK0_GPIO0_OFFSET) // PADS_BANK0_GPIO0 - // 0x00000100 [8] ISO (1) Pad isolation control - // 0x00000080 [7] OD (0) Output disable - // 0x00000040 [6] IE (0) Input enable - // 0x00000030 [5:4] DRIVE (0x1) Drive strength - // 0x00000008 [3] PUE (0) Pull up enable - // 0x00000004 [2] PDE (1) Pull down enable - // 0x00000002 [1] SCHMITT (1) Enable schmitt trigger - // 0x00000001 [0] SLEWFAST (0) Slew rate control - io_rw_32 io[48]; -} pads_bank0_hw_t; - -#define pads_bank0_hw ((pads_bank0_hw_t *)PADS_BANK0_BASE) -static_assert(sizeof (pads_bank0_hw_t) == 0x00c4, ""); - -#endif // _HARDWARE_STRUCTS_PADS_BANK0_H - diff --git a/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/pads_qspi.h b/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/pads_qspi.h deleted file mode 100644 index e6b0f68100..0000000000 --- a/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/pads_qspi.h +++ /dev/null @@ -1,49 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _HARDWARE_STRUCTS_PADS_QSPI_H -#define _HARDWARE_STRUCTS_PADS_QSPI_H - -/** - * \file rp2350/pads_qspi.h - */ - -#include "hardware/address_mapped.h" -#include "hardware/regs/pads_qspi.h" - -// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_pads_qspi -// -// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) -// _REG_(x) will link to the corresponding register in hardware/regs/pads_qspi.h. -// -// Bit-field descriptions are of the form: -// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION - -typedef struct { - _REG_(PADS_QSPI_VOLTAGE_SELECT_OFFSET) // PADS_QSPI_VOLTAGE_SELECT - // Voltage select - // 0x00000001 [0] VOLTAGE_SELECT (0) - io_rw_32 voltage_select; - - // (Description copied from array index 0 register PADS_QSPI_GPIO_QSPI_SCLK applies similarly to other array indexes) - _REG_(PADS_QSPI_GPIO_QSPI_SCLK_OFFSET) // PADS_QSPI_GPIO_QSPI_SCLK - // 0x00000100 [8] ISO (1) Pad isolation control - // 0x00000080 [7] OD (0) Output disable - // 0x00000040 [6] IE (1) Input enable - // 0x00000030 [5:4] DRIVE (0x1) Drive strength - // 0x00000008 [3] PUE (0) Pull up enable - // 0x00000004 [2] PDE (1) Pull down enable - // 0x00000002 [1] SCHMITT (1) Enable schmitt trigger - // 0x00000001 [0] SLEWFAST (0) Slew rate control - io_rw_32 io[6]; -} pads_qspi_hw_t; - -#define pads_qspi_hw ((pads_qspi_hw_t *)PADS_QSPI_BASE) -static_assert(sizeof (pads_qspi_hw_t) == 0x001c, ""); - -#endif // _HARDWARE_STRUCTS_PADS_QSPI_H - diff --git a/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/padsbank0.h b/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/padsbank0.h deleted file mode 100644 index cb14e792b7..0000000000 --- a/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/padsbank0.h +++ /dev/null @@ -1,9 +0,0 @@ -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -// Support old header for compatibility (and if included, support old variable name) -#include "hardware/structs/pads_bank0.h" -#define padsbank0_hw pads_bank0_hw \ No newline at end of file diff --git a/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/pio.h b/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/pio.h deleted file mode 100644 index 68e5bac086..0000000000 --- a/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/pio.h +++ /dev/null @@ -1,380 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _HARDWARE_STRUCTS_PIO_H -#define _HARDWARE_STRUCTS_PIO_H - -/** - * \file rp2350/pio.h - */ - -#include "hardware/address_mapped.h" -#include "hardware/regs/pio.h" - -// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_pio -// -// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) -// _REG_(x) will link to the corresponding register in hardware/regs/pio.h. -// -// Bit-field descriptions are of the form: -// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION - -typedef struct { - _REG_(PIO_SM0_CLKDIV_OFFSET) // PIO_SM0_CLKDIV - // Clock divisor register for state machine 0 + - // 0xffff0000 [31:16] INT (0x0001) Effective frequency is sysclk/(int + frac/256) - // 0x0000ff00 [15:8] FRAC (0x00) Fractional part of clock divisor - io_rw_32 clkdiv; - - _REG_(PIO_SM0_EXECCTRL_OFFSET) // PIO_SM0_EXECCTRL - // Execution/behavioural settings for state machine 0 - // 0x80000000 [31] EXEC_STALLED (0) If 1, an instruction written to SMx_INSTR is stalled,... - // 0x40000000 [30] SIDE_EN (0) If 1, the MSB of the Delay/Side-set instruction field is... - // 0x20000000 [29] SIDE_PINDIR (0) If 1, side-set data is asserted to pin directions,... - // 0x1f000000 [28:24] JMP_PIN (0x00) The GPIO number to use as condition for JMP PIN - // 0x00f80000 [23:19] OUT_EN_SEL (0x00) Which data bit to use for inline OUT enable - // 0x00040000 [18] INLINE_OUT_EN (0) If 1, use a bit of OUT data as an auxiliary write enable + - // 0x00020000 [17] OUT_STICKY (0) Continuously assert the most recent OUT/SET to the pins - // 0x0001f000 [16:12] WRAP_TOP (0x1f) After reaching this address, execution is wrapped to wrap_bottom - // 0x00000f80 [11:7] WRAP_BOTTOM (0x00) After reaching wrap_top, execution is wrapped to this address - // 0x00000060 [6:5] STATUS_SEL (0x0) Comparison used for the MOV x, STATUS instruction - // 0x0000001f [4:0] STATUS_N (0x00) Comparison level or IRQ index for the MOV x, STATUS instruction - io_rw_32 execctrl; - - _REG_(PIO_SM0_SHIFTCTRL_OFFSET) // PIO_SM0_SHIFTCTRL - // Control behaviour of the input/output shift registers for state machine 0 - // 0x80000000 [31] FJOIN_RX (0) When 1, RX FIFO steals the TX FIFO's storage, and... - // 0x40000000 [30] FJOIN_TX (0) When 1, TX FIFO steals the RX FIFO's storage, and... - // 0x3e000000 [29:25] PULL_THRESH (0x00) Number of bits shifted out of OSR before autopull, or... - // 0x01f00000 [24:20] PUSH_THRESH (0x00) Number of bits shifted into ISR before autopush, or... - // 0x00080000 [19] OUT_SHIFTDIR (1) 1 = shift out of output shift register to right - // 0x00040000 [18] IN_SHIFTDIR (1) 1 = shift input shift register to right (data enters from left) - // 0x00020000 [17] AUTOPULL (0) Pull automatically when the output shift register is emptied, i - // 0x00010000 [16] AUTOPUSH (0) Push automatically when the input shift register is filled, i - // 0x00008000 [15] FJOIN_RX_PUT (0) If 1, disable this state machine's RX FIFO, make its... - // 0x00004000 [14] FJOIN_RX_GET (0) If 1, disable this state machine's RX FIFO, make its... - // 0x0000001f [4:0] IN_COUNT (0x00) Set the number of pins which are not masked to 0 when... - io_rw_32 shiftctrl; - - _REG_(PIO_SM0_ADDR_OFFSET) // PIO_SM0_ADDR - // Current instruction address of state machine 0 - // 0x0000001f [4:0] SM0_ADDR (0x00) - io_ro_32 addr; - - _REG_(PIO_SM0_INSTR_OFFSET) // PIO_SM0_INSTR - // Read to see the instruction currently addressed by state machine 0's program counter + - // 0x0000ffff [15:0] SM0_INSTR (-) - io_rw_32 instr; - - _REG_(PIO_SM0_PINCTRL_OFFSET) // PIO_SM0_PINCTRL - // State machine pin control - // 0xe0000000 [31:29] SIDESET_COUNT (0x0) The number of MSBs of the Delay/Side-set instruction... - // 0x1c000000 [28:26] SET_COUNT (0x5) The number of pins asserted by a SET - // 0x03f00000 [25:20] OUT_COUNT (0x00) The number of pins asserted by an OUT PINS, OUT PINDIRS... - // 0x000f8000 [19:15] IN_BASE (0x00) The pin which is mapped to the least-significant bit of... - // 0x00007c00 [14:10] SIDESET_BASE (0x00) The lowest-numbered pin that will be affected by a... - // 0x000003e0 [9:5] SET_BASE (0x00) The lowest-numbered pin that will be affected by a SET... - // 0x0000001f [4:0] OUT_BASE (0x00) The lowest-numbered pin that will be affected by an OUT... - io_rw_32 pinctrl; -} pio_sm_hw_t; - -typedef struct { - _REG_(PIO_IRQ0_INTE_OFFSET) // PIO_IRQ0_INTE - // Interrupt Enable for irq0 - // 0x00008000 [15] SM7 (0) - // 0x00004000 [14] SM6 (0) - // 0x00002000 [13] SM5 (0) - // 0x00001000 [12] SM4 (0) - // 0x00000800 [11] SM3 (0) - // 0x00000400 [10] SM2 (0) - // 0x00000200 [9] SM1 (0) - // 0x00000100 [8] SM0 (0) - // 0x00000080 [7] SM3_TXNFULL (0) - // 0x00000040 [6] SM2_TXNFULL (0) - // 0x00000020 [5] SM1_TXNFULL (0) - // 0x00000010 [4] SM0_TXNFULL (0) - // 0x00000008 [3] SM3_RXNEMPTY (0) - // 0x00000004 [2] SM2_RXNEMPTY (0) - // 0x00000002 [1] SM1_RXNEMPTY (0) - // 0x00000001 [0] SM0_RXNEMPTY (0) - io_rw_32 inte; - - _REG_(PIO_IRQ0_INTF_OFFSET) // PIO_IRQ0_INTF - // Interrupt Force for irq0 - // 0x00008000 [15] SM7 (0) - // 0x00004000 [14] SM6 (0) - // 0x00002000 [13] SM5 (0) - // 0x00001000 [12] SM4 (0) - // 0x00000800 [11] SM3 (0) - // 0x00000400 [10] SM2 (0) - // 0x00000200 [9] SM1 (0) - // 0x00000100 [8] SM0 (0) - // 0x00000080 [7] SM3_TXNFULL (0) - // 0x00000040 [6] SM2_TXNFULL (0) - // 0x00000020 [5] SM1_TXNFULL (0) - // 0x00000010 [4] SM0_TXNFULL (0) - // 0x00000008 [3] SM3_RXNEMPTY (0) - // 0x00000004 [2] SM2_RXNEMPTY (0) - // 0x00000002 [1] SM1_RXNEMPTY (0) - // 0x00000001 [0] SM0_RXNEMPTY (0) - io_rw_32 intf; - - _REG_(PIO_IRQ0_INTS_OFFSET) // PIO_IRQ0_INTS - // Interrupt status after masking & forcing for irq0 - // 0x00008000 [15] SM7 (0) - // 0x00004000 [14] SM6 (0) - // 0x00002000 [13] SM5 (0) - // 0x00001000 [12] SM4 (0) - // 0x00000800 [11] SM3 (0) - // 0x00000400 [10] SM2 (0) - // 0x00000200 [9] SM1 (0) - // 0x00000100 [8] SM0 (0) - // 0x00000080 [7] SM3_TXNFULL (0) - // 0x00000040 [6] SM2_TXNFULL (0) - // 0x00000020 [5] SM1_TXNFULL (0) - // 0x00000010 [4] SM0_TXNFULL (0) - // 0x00000008 [3] SM3_RXNEMPTY (0) - // 0x00000004 [2] SM2_RXNEMPTY (0) - // 0x00000002 [1] SM1_RXNEMPTY (0) - // 0x00000001 [0] SM0_RXNEMPTY (0) - io_ro_32 ints; -} pio_irq_ctrl_hw_t; - -typedef struct { - _REG_(PIO_CTRL_OFFSET) // PIO_CTRL - // PIO control register - // 0x04000000 [26] NEXTPREV_CLKDIV_RESTART (0) Write 1 to restart the clock dividers of state machines... - // 0x02000000 [25] NEXTPREV_SM_DISABLE (0) Write 1 to disable state machines in neighbouring PIO... - // 0x01000000 [24] NEXTPREV_SM_ENABLE (0) Write 1 to enable state machines in neighbouring PIO... - // 0x00f00000 [23:20] NEXT_PIO_MASK (0x0) A mask of state machines in the neighbouring... - // 0x000f0000 [19:16] PREV_PIO_MASK (0x0) A mask of state machines in the neighbouring... - // 0x00000f00 [11:8] CLKDIV_RESTART (0x0) Restart a state machine's clock divider from an initial... - // 0x000000f0 [7:4] SM_RESTART (0x0) Write 1 to instantly clear internal SM state which may... - // 0x0000000f [3:0] SM_ENABLE (0x0) Enable/disable each of the four state machines by... - io_rw_32 ctrl; - - _REG_(PIO_FSTAT_OFFSET) // PIO_FSTAT - // FIFO status register - // 0x0f000000 [27:24] TXEMPTY (0xf) State machine TX FIFO is empty - // 0x000f0000 [19:16] TXFULL (0x0) State machine TX FIFO is full - // 0x00000f00 [11:8] RXEMPTY (0xf) State machine RX FIFO is empty - // 0x0000000f [3:0] RXFULL (0x0) State machine RX FIFO is full - io_ro_32 fstat; - - _REG_(PIO_FDEBUG_OFFSET) // PIO_FDEBUG - // FIFO debug register - // 0x0f000000 [27:24] TXSTALL (0x0) State machine has stalled on empty TX FIFO during a... - // 0x000f0000 [19:16] TXOVER (0x0) TX FIFO overflow (i - // 0x00000f00 [11:8] RXUNDER (0x0) RX FIFO underflow (i - // 0x0000000f [3:0] RXSTALL (0x0) State machine has stalled on full RX FIFO during a... - io_rw_32 fdebug; - - _REG_(PIO_FLEVEL_OFFSET) // PIO_FLEVEL - // FIFO levels - // 0xf0000000 [31:28] RX3 (0x0) - // 0x0f000000 [27:24] TX3 (0x0) - // 0x00f00000 [23:20] RX2 (0x0) - // 0x000f0000 [19:16] TX2 (0x0) - // 0x0000f000 [15:12] RX1 (0x0) - // 0x00000f00 [11:8] TX1 (0x0) - // 0x000000f0 [7:4] RX0 (0x0) - // 0x0000000f [3:0] TX0 (0x0) - io_ro_32 flevel; - - // (Description copied from array index 0 register PIO_TXF0 applies similarly to other array indexes) - _REG_(PIO_TXF0_OFFSET) // PIO_TXF0 - // Direct write access to the TX FIFO for this state machine - // 0xffffffff [31:0] TXF0 (0x00000000) - io_wo_32 txf[4]; - - // (Description copied from array index 0 register PIO_RXF0 applies similarly to other array indexes) - _REG_(PIO_RXF0_OFFSET) // PIO_RXF0 - // Direct read access to the RX FIFO for this state machine - // 0xffffffff [31:0] RXF0 (-) - io_ro_32 rxf[4]; - - _REG_(PIO_IRQ_OFFSET) // PIO_IRQ - // State machine IRQ flags register - // 0x000000ff [7:0] IRQ (0x00) - io_rw_32 irq; - - _REG_(PIO_IRQ_FORCE_OFFSET) // PIO_IRQ_FORCE - // Writing a 1 to each of these bits will forcibly assert the corresponding IRQ - // 0x000000ff [7:0] IRQ_FORCE (0x00) - io_wo_32 irq_force; - - _REG_(PIO_INPUT_SYNC_BYPASS_OFFSET) // PIO_INPUT_SYNC_BYPASS - // There is a 2-flipflop synchronizer on each GPIO input, which protects PIO logic from metastabilities - // 0xffffffff [31:0] INPUT_SYNC_BYPASS (0x00000000) - io_rw_32 input_sync_bypass; - - _REG_(PIO_DBG_PADOUT_OFFSET) // PIO_DBG_PADOUT - // Read to sample the pad output values PIO is currently driving to the GPIOs - // 0xffffffff [31:0] DBG_PADOUT (0x00000000) - io_ro_32 dbg_padout; - - _REG_(PIO_DBG_PADOE_OFFSET) // PIO_DBG_PADOE - // Read to sample the pad output enables (direction) PIO is currently driving to the GPIOs - // 0xffffffff [31:0] DBG_PADOE (0x00000000) - io_ro_32 dbg_padoe; - - _REG_(PIO_DBG_CFGINFO_OFFSET) // PIO_DBG_CFGINFO - // The PIO hardware has some free parameters that may vary between chip products - // 0xf0000000 [31:28] VERSION (0x1) Version of the core PIO hardware - // 0x003f0000 [21:16] IMEM_SIZE (-) The size of the instruction memory, measured in units of... - // 0x00000f00 [11:8] SM_COUNT (-) The number of state machines this PIO instance is equipped with - // 0x0000003f [5:0] FIFO_DEPTH (-) The depth of the state machine TX/RX FIFOs, measured in words - io_ro_32 dbg_cfginfo; - - // (Description copied from array index 0 register PIO_INSTR_MEM0 applies similarly to other array indexes) - _REG_(PIO_INSTR_MEM0_OFFSET) // PIO_INSTR_MEM0 - // Write-only access to instruction memory location 0 - // 0x0000ffff [15:0] INSTR_MEM0 (0x0000) - io_wo_32 instr_mem[32]; - - pio_sm_hw_t sm[4]; - - // (Description copied from array index 0 register PIO_RXF0_PUTGET0 applies similarly to other array indexes) - _REG_(PIO_RXF0_PUTGET0_OFFSET) // PIO_RXF0_PUTGET0 - // Direct read/write access to the RX FIFO on all SMs, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set - // 0xffffffff [31:0] RXF0_PUTGET0 (0x00000000) - io_rw_32 rxf_putget[4][4]; - - _REG_(PIO_GPIOBASE_OFFSET) // PIO_GPIOBASE - // Relocate GPIO 0 (from PIO's point of view) in the system GPIO numbering, to access more than 32... - // 0x00000010 [4] GPIOBASE (0) - io_rw_32 gpiobase; - - _REG_(PIO_INTR_OFFSET) // PIO_INTR - // Raw Interrupts - // 0x00008000 [15] SM7 (0) - // 0x00004000 [14] SM6 (0) - // 0x00002000 [13] SM5 (0) - // 0x00001000 [12] SM4 (0) - // 0x00000800 [11] SM3 (0) - // 0x00000400 [10] SM2 (0) - // 0x00000200 [9] SM1 (0) - // 0x00000100 [8] SM0 (0) - // 0x00000080 [7] SM3_TXNFULL (0) - // 0x00000040 [6] SM2_TXNFULL (0) - // 0x00000020 [5] SM1_TXNFULL (0) - // 0x00000010 [4] SM0_TXNFULL (0) - // 0x00000008 [3] SM3_RXNEMPTY (0) - // 0x00000004 [2] SM2_RXNEMPTY (0) - // 0x00000002 [1] SM1_RXNEMPTY (0) - // 0x00000001 [0] SM0_RXNEMPTY (0) - io_ro_32 intr; - - union { - struct { - _REG_(PIO_IRQ0_INTE_OFFSET) // PIO_IRQ0_INTE - // Interrupt Enable for irq0 - // 0x00000800 [11] SM3 (0) - // 0x00000400 [10] SM2 (0) - // 0x00000200 [9] SM1 (0) - // 0x00000100 [8] SM0 (0) - // 0x00000080 [7] SM3_TXNFULL (0) - // 0x00000040 [6] SM2_TXNFULL (0) - // 0x00000020 [5] SM1_TXNFULL (0) - // 0x00000010 [4] SM0_TXNFULL (0) - // 0x00000008 [3] SM3_RXNEMPTY (0) - // 0x00000004 [2] SM2_RXNEMPTY (0) - // 0x00000002 [1] SM1_RXNEMPTY (0) - // 0x00000001 [0] SM0_RXNEMPTY (0) - io_rw_32 inte0; - - _REG_(PIO_IRQ0_INTF_OFFSET) // PIO_IRQ0_INTF - // Interrupt Force for irq0 - // 0x00000800 [11] SM3 (0) - // 0x00000400 [10] SM2 (0) - // 0x00000200 [9] SM1 (0) - // 0x00000100 [8] SM0 (0) - // 0x00000080 [7] SM3_TXNFULL (0) - // 0x00000040 [6] SM2_TXNFULL (0) - // 0x00000020 [5] SM1_TXNFULL (0) - // 0x00000010 [4] SM0_TXNFULL (0) - // 0x00000008 [3] SM3_RXNEMPTY (0) - // 0x00000004 [2] SM2_RXNEMPTY (0) - // 0x00000002 [1] SM1_RXNEMPTY (0) - // 0x00000001 [0] SM0_RXNEMPTY (0) - io_rw_32 intf0; - - _REG_(PIO_IRQ0_INTS_OFFSET) // PIO_IRQ0_INTS - // Interrupt status after masking & forcing for irq0 - // 0x00000800 [11] SM3 (0) - // 0x00000400 [10] SM2 (0) - // 0x00000200 [9] SM1 (0) - // 0x00000100 [8] SM0 (0) - // 0x00000080 [7] SM3_TXNFULL (0) - // 0x00000040 [6] SM2_TXNFULL (0) - // 0x00000020 [5] SM1_TXNFULL (0) - // 0x00000010 [4] SM0_TXNFULL (0) - // 0x00000008 [3] SM3_RXNEMPTY (0) - // 0x00000004 [2] SM2_RXNEMPTY (0) - // 0x00000002 [1] SM1_RXNEMPTY (0) - // 0x00000001 [0] SM0_RXNEMPTY (0) - io_ro_32 ints0; - - _REG_(PIO_IRQ1_INTE_OFFSET) // PIO_IRQ1_INTE - // Interrupt Enable for irq1 - // 0x00000800 [11] SM3 (0) - // 0x00000400 [10] SM2 (0) - // 0x00000200 [9] SM1 (0) - // 0x00000100 [8] SM0 (0) - // 0x00000080 [7] SM3_TXNFULL (0) - // 0x00000040 [6] SM2_TXNFULL (0) - // 0x00000020 [5] SM1_TXNFULL (0) - // 0x00000010 [4] SM0_TXNFULL (0) - // 0x00000008 [3] SM3_RXNEMPTY (0) - // 0x00000004 [2] SM2_RXNEMPTY (0) - // 0x00000002 [1] SM1_RXNEMPTY (0) - // 0x00000001 [0] SM0_RXNEMPTY (0) - io_rw_32 inte1; - - _REG_(PIO_IRQ1_INTF_OFFSET) // PIO_IRQ1_INTF - // Interrupt Force for irq1 - // 0x00000800 [11] SM3 (0) - // 0x00000400 [10] SM2 (0) - // 0x00000200 [9] SM1 (0) - // 0x00000100 [8] SM0 (0) - // 0x00000080 [7] SM3_TXNFULL (0) - // 0x00000040 [6] SM2_TXNFULL (0) - // 0x00000020 [5] SM1_TXNFULL (0) - // 0x00000010 [4] SM0_TXNFULL (0) - // 0x00000008 [3] SM3_RXNEMPTY (0) - // 0x00000004 [2] SM2_RXNEMPTY (0) - // 0x00000002 [1] SM1_RXNEMPTY (0) - // 0x00000001 [0] SM0_RXNEMPTY (0) - io_rw_32 intf1; - - _REG_(PIO_IRQ1_INTS_OFFSET) // PIO_IRQ1_INTS - // Interrupt status after masking & forcing for irq1 - // 0x00000800 [11] SM3 (0) - // 0x00000400 [10] SM2 (0) - // 0x00000200 [9] SM1 (0) - // 0x00000100 [8] SM0 (0) - // 0x00000080 [7] SM3_TXNFULL (0) - // 0x00000040 [6] SM2_TXNFULL (0) - // 0x00000020 [5] SM1_TXNFULL (0) - // 0x00000010 [4] SM0_TXNFULL (0) - // 0x00000008 [3] SM3_RXNEMPTY (0) - // 0x00000004 [2] SM2_RXNEMPTY (0) - // 0x00000002 [1] SM1_RXNEMPTY (0) - // 0x00000001 [0] SM0_RXNEMPTY (0) - io_ro_32 ints1; - }; - pio_irq_ctrl_hw_t irq_ctrl[2]; - }; -} pio_hw_t; - -#define pio0_hw ((pio_hw_t *)PIO0_BASE) -#define pio1_hw ((pio_hw_t *)PIO1_BASE) -#define pio2_hw ((pio_hw_t *)PIO2_BASE) -static_assert(sizeof (pio_hw_t) == 0x0188, ""); - -#endif // _HARDWARE_STRUCTS_PIO_H - diff --git a/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/pll.h b/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/pll.h deleted file mode 100644 index 8a7276048d..0000000000 --- a/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/pll.h +++ /dev/null @@ -1,82 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _HARDWARE_STRUCTS_PLL_H -#define _HARDWARE_STRUCTS_PLL_H - -/** - * \file rp2350/pll.h - */ - -#include "hardware/address_mapped.h" -#include "hardware/regs/pll.h" - -// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_pll -// -// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) -// _REG_(x) will link to the corresponding register in hardware/regs/pll.h. -// -// Bit-field descriptions are of the form: -// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION - -/// \tag::pll_hw[] -typedef struct { - _REG_(PLL_CS_OFFSET) // PLL_CS - // Control and Status - // 0x80000000 [31] LOCK (0) PLL is locked - // 0x40000000 [30] LOCK_N (0) PLL is not locked + - // 0x00000100 [8] BYPASS (0) Passes the reference clock to the output instead of the... - // 0x0000003f [5:0] REFDIV (0x01) Divides the PLL input reference clock - io_rw_32 cs; - - _REG_(PLL_PWR_OFFSET) // PLL_PWR - // Controls the PLL power modes - // 0x00000020 [5] VCOPD (1) PLL VCO powerdown + - // 0x00000008 [3] POSTDIVPD (1) PLL post divider powerdown + - // 0x00000004 [2] DSMPD (1) PLL DSM powerdown + - // 0x00000001 [0] PD (1) PLL powerdown + - io_rw_32 pwr; - - _REG_(PLL_FBDIV_INT_OFFSET) // PLL_FBDIV_INT - // Feedback divisor - // 0x00000fff [11:0] FBDIV_INT (0x000) see ctrl reg description for constraints - io_rw_32 fbdiv_int; - - _REG_(PLL_PRIM_OFFSET) // PLL_PRIM - // Controls the PLL post dividers for the primary output - // 0x00070000 [18:16] POSTDIV1 (0x7) divide by 1-7 - // 0x00007000 [14:12] POSTDIV2 (0x7) divide by 1-7 - io_rw_32 prim; - - _REG_(PLL_INTR_OFFSET) // PLL_INTR - // Raw Interrupts - // 0x00000001 [0] LOCK_N_STICKY (0) - io_rw_32 intr; - - _REG_(PLL_INTE_OFFSET) // PLL_INTE - // Interrupt Enable - // 0x00000001 [0] LOCK_N_STICKY (0) - io_rw_32 inte; - - _REG_(PLL_INTF_OFFSET) // PLL_INTF - // Interrupt Force - // 0x00000001 [0] LOCK_N_STICKY (0) - io_rw_32 intf; - - _REG_(PLL_INTS_OFFSET) // PLL_INTS - // Interrupt status after masking & forcing - // 0x00000001 [0] LOCK_N_STICKY (0) - io_ro_32 ints; -} pll_hw_t; -/// \end::pll_hw[] - -#define pll_sys_hw ((pll_hw_t *)PLL_SYS_BASE) -#define pll_usb_hw ((pll_hw_t *)PLL_USB_BASE) -static_assert(sizeof (pll_hw_t) == 0x0020, ""); - -#endif // _HARDWARE_STRUCTS_PLL_H - diff --git a/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/powman.h b/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/powman.h deleted file mode 100644 index a81890e3cf..0000000000 --- a/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/powman.h +++ /dev/null @@ -1,338 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _HARDWARE_STRUCTS_POWMAN_H -#define _HARDWARE_STRUCTS_POWMAN_H - -/** - * \file rp2350/powman.h - */ - -#include "hardware/address_mapped.h" -#include "hardware/regs/powman.h" - -// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_powman -// -// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) -// _REG_(x) will link to the corresponding register in hardware/regs/powman.h. -// -// Bit-field descriptions are of the form: -// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION - -typedef struct { - _REG_(POWMAN_BADPASSWD_OFFSET) // POWMAN_BADPASSWD - // Indicates a bad password has been used - // 0x00000001 [0] BADPASSWD (0) - io_rw_32 badpasswd; - - _REG_(POWMAN_VREG_CTRL_OFFSET) // POWMAN_VREG_CTRL - // Voltage Regulator Control - // 0x00008000 [15] RST_N (1) returns the regulator to its startup settings + - // 0x00002000 [13] UNLOCK (0) unlocks the VREG control interface after power up + - // 0x00001000 [12] ISOLATE (0) isolates the VREG control interface + - // 0x00000100 [8] DISABLE_VOLTAGE_LIMIT (0) 0=not disabled, 1=enabled - // 0x00000070 [6:4] HT_TH (0x5) high temperature protection threshold + - io_rw_32 vreg_ctrl; - - _REG_(POWMAN_VREG_STS_OFFSET) // POWMAN_VREG_STS - // Voltage Regulator Status - // 0x00000010 [4] VOUT_OK (0) output regulation status + - // 0x00000001 [0] STARTUP (0) startup status + - io_ro_32 vreg_sts; - - _REG_(POWMAN_VREG_OFFSET) // POWMAN_VREG - // Voltage Regulator Settings - // 0x00008000 [15] UPDATE_IN_PROGRESS (0) regulator state is being updated + - // 0x000001f0 [8:4] VSEL (0x0b) output voltage select + - // 0x00000002 [1] HIZ (0) high impedance mode select + - io_rw_32 vreg; - - _REG_(POWMAN_VREG_LP_ENTRY_OFFSET) // POWMAN_VREG_LP_ENTRY - // Voltage Regulator Low Power Entry Settings - // 0x000001f0 [8:4] VSEL (0x0b) output voltage select + - // 0x00000004 [2] MODE (1) selects either normal (switching) mode or low power... - // 0x00000002 [1] HIZ (0) high impedance mode select + - io_rw_32 vreg_lp_entry; - - _REG_(POWMAN_VREG_LP_EXIT_OFFSET) // POWMAN_VREG_LP_EXIT - // Voltage Regulator Low Power Exit Settings - // 0x000001f0 [8:4] VSEL (0x0b) output voltage select + - // 0x00000004 [2] MODE (0) selects either normal (switching) mode or low power... - // 0x00000002 [1] HIZ (0) high impedance mode select + - io_rw_32 vreg_lp_exit; - - _REG_(POWMAN_BOD_CTRL_OFFSET) // POWMAN_BOD_CTRL - // Brown-out Detection Control - // 0x00001000 [12] ISOLATE (0) isolates the brown-out detection control interface + - io_rw_32 bod_ctrl; - - _REG_(POWMAN_BOD_OFFSET) // POWMAN_BOD - // Brown-out Detection Settings - // 0x000001f0 [8:4] VSEL (0x0b) threshold select + - // 0x00000001 [0] EN (1) enable brown-out detection + - io_rw_32 bod; - - _REG_(POWMAN_BOD_LP_ENTRY_OFFSET) // POWMAN_BOD_LP_ENTRY - // Brown-out Detection Low Power Entry Settings - // 0x000001f0 [8:4] VSEL (0x0b) threshold select + - // 0x00000001 [0] EN (0) enable brown-out detection + - io_rw_32 bod_lp_entry; - - _REG_(POWMAN_BOD_LP_EXIT_OFFSET) // POWMAN_BOD_LP_EXIT - // Brown-out Detection Low Power Exit Settings - // 0x000001f0 [8:4] VSEL (0x0b) threshold select + - // 0x00000001 [0] EN (1) enable brown-out detection + - io_rw_32 bod_lp_exit; - - _REG_(POWMAN_LPOSC_OFFSET) // POWMAN_LPOSC - // Low power oscillator control register - // 0x000003f0 [9:4] TRIM (0x20) Frequency trim - the trim step is typically 1% of the... - // 0x00000003 [1:0] MODE (0x3) This feature has been removed - io_rw_32 lposc; - - _REG_(POWMAN_CHIP_RESET_OFFSET) // POWMAN_CHIP_RESET - // Chip reset control and status - // 0x10000000 [28] HAD_WATCHDOG_RESET_RSM (0) Last reset was a watchdog timeout which was configured... - // 0x08000000 [27] HAD_HZD_SYS_RESET_REQ (0) Last reset was a system reset from the hazard debugger + - // 0x04000000 [26] HAD_GLITCH_DETECT (0) Last reset was due to a power supply glitch + - // 0x02000000 [25] HAD_SWCORE_PD (0) Last reset was a switched core powerdown + - // 0x01000000 [24] HAD_WATCHDOG_RESET_SWCORE (0) Last reset was a watchdog timeout which was configured... - // 0x00800000 [23] HAD_WATCHDOG_RESET_POWMAN (0) Last reset was a watchdog timeout which was configured... - // 0x00400000 [22] HAD_WATCHDOG_RESET_POWMAN_ASYNC (0) Last reset was a watchdog timeout which was configured... - // 0x00200000 [21] HAD_RESCUE (0) Last reset was a rescue reset from the debugger + - // 0x00080000 [19] HAD_DP_RESET_REQ (0) Last reset was an reset request from the arm debugger + - // 0x00040000 [18] HAD_RUN_LOW (0) Last reset was from the RUN pin + - // 0x00020000 [17] HAD_BOR (0) Last reset was from the brown-out detection block + - // 0x00010000 [16] HAD_POR (0) Last reset was from the power-on reset + - // 0x00000010 [4] RESCUE_FLAG (0) This is set by a rescue reset from the RP-AP - // 0x00000001 [0] DOUBLE_TAP (0) This flag is set by double-tapping RUN - io_rw_32 chip_reset; - - _REG_(POWMAN_WDSEL_OFFSET) // POWMAN_WDSEL - // Allows a watchdog reset to reset the internal state of powman in addition to the power-on state... - // 0x00001000 [12] RESET_RSM (0) If set to 1, a watchdog reset will run the full power-on... - // 0x00000100 [8] RESET_SWCORE (0) If set to 1, a watchdog reset will reset the switched... - // 0x00000010 [4] RESET_POWMAN (0) If set to 1, a watchdog reset will restore powman... - // 0x00000001 [0] RESET_POWMAN_ASYNC (0) If set to 1, a watchdog reset will restore powman... - io_rw_32 wdsel; - - _REG_(POWMAN_SEQ_CFG_OFFSET) // POWMAN_SEQ_CFG - // For configuration of the power sequencer + - // 0x00100000 [20] USING_FAST_POWCK (1) 0 indicates the POWMAN clock is running from the low... - // 0x00020000 [17] USING_BOD_LP (0) Indicates the brown-out detector (BOD) mode + - // 0x00010000 [16] USING_VREG_LP (0) Indicates the voltage regulator (VREG) mode + - // 0x00001000 [12] USE_FAST_POWCK (1) selects the reference clock (clk_ref) as the source of... - // 0x00000100 [8] RUN_LPOSC_IN_LP (1) Set to 0 to stop the low power osc when the... - // 0x00000080 [7] USE_BOD_HP (1) Set to 0 to prevent automatic switching to bod high... - // 0x00000040 [6] USE_BOD_LP (1) Set to 0 to prevent automatic switching to bod low power... - // 0x00000020 [5] USE_VREG_HP (1) Set to 0 to prevent automatic switching to vreg high... - // 0x00000010 [4] USE_VREG_LP (1) Set to 0 to prevent automatic switching to vreg low... - // 0x00000002 [1] HW_PWRUP_SRAM0 (0) Specifies the power state of SRAM0 when powering up... - // 0x00000001 [0] HW_PWRUP_SRAM1 (0) Specifies the power state of SRAM1 when powering up... - io_rw_32 seq_cfg; - - _REG_(POWMAN_STATE_OFFSET) // POWMAN_STATE - // This register controls the power state of the 4 power domains - // 0x00002000 [13] CHANGING (0) - // 0x00001000 [12] WAITING (0) - // 0x00000800 [11] BAD_HW_REQ (0) Bad hardware initiated state request - // 0x00000400 [10] BAD_SW_REQ (0) Bad software initiated state request - // 0x00000200 [9] PWRUP_WHILE_WAITING (0) Request ignored because of a pending pwrup request - // 0x00000100 [8] REQ_IGNORED (0) - // 0x000000f0 [7:4] REQ (0x0) - // 0x0000000f [3:0] CURRENT (0xf) - io_rw_32 state; - - _REG_(POWMAN_POW_FASTDIV_OFFSET) // POWMAN_POW_FASTDIV - // 0x000007ff [10:0] POW_FASTDIV (0x040) divides the POWMAN clock to provide a tick for the delay... - io_rw_32 pow_fastdiv; - - _REG_(POWMAN_POW_DELAY_OFFSET) // POWMAN_POW_DELAY - // power state machine delays - // 0x0000ff00 [15:8] SRAM_STEP (0x20) timing between the sram0 and sram1 power state machine steps + - // 0x000000f0 [7:4] XIP_STEP (0x1) timing between the xip power state machine steps + - // 0x0000000f [3:0] SWCORE_STEP (0x1) timing between the swcore power state machine steps + - io_rw_32 pow_delay; - - // (Description copied from array index 0 register POWMAN_EXT_CTRL0 applies similarly to other array indexes) - _REG_(POWMAN_EXT_CTRL0_OFFSET) // POWMAN_EXT_CTRL0 - // Configures a gpio as a power mode aware control output - // 0x00004000 [14] LP_EXIT_STATE (0) output level when exiting the low power state - // 0x00002000 [13] LP_ENTRY_STATE (0) output level when entering the low power state - // 0x00001000 [12] INIT_STATE (0) - // 0x00000100 [8] INIT (0) - // 0x0000003f [5:0] GPIO_SELECT (0x3f) selects from gpio 0->30 + - io_rw_32 ext_ctrl[2]; - - _REG_(POWMAN_EXT_TIME_REF_OFFSET) // POWMAN_EXT_TIME_REF - // Select a GPIO to use as a time reference, the source can be used to drive the low power clock at... - // 0x00000010 [4] DRIVE_LPCK (0) Use the selected GPIO to drive the 32kHz low power... - // 0x00000003 [1:0] SOURCE_SEL (0x0) 0 -> gpio12 + - io_rw_32 ext_time_ref; - - _REG_(POWMAN_LPOSC_FREQ_KHZ_INT_OFFSET) // POWMAN_LPOSC_FREQ_KHZ_INT - // Informs the AON Timer of the integer component of the clock frequency when running off the LPOSC - // 0x0000003f [5:0] LPOSC_FREQ_KHZ_INT (0x20) Integer component of the LPOSC or GPIO clock source... - io_rw_32 lposc_freq_khz_int; - - _REG_(POWMAN_LPOSC_FREQ_KHZ_FRAC_OFFSET) // POWMAN_LPOSC_FREQ_KHZ_FRAC - // Informs the AON Timer of the fractional component of the clock frequency when running off the LPOSC - // 0x0000ffff [15:0] LPOSC_FREQ_KHZ_FRAC (0xc49c) Fractional component of the LPOSC or GPIO clock source... - io_rw_32 lposc_freq_khz_frac; - - _REG_(POWMAN_XOSC_FREQ_KHZ_INT_OFFSET) // POWMAN_XOSC_FREQ_KHZ_INT - // Informs the AON Timer of the integer component of the clock frequency when running off the XOSC - // 0x0000ffff [15:0] XOSC_FREQ_KHZ_INT (0x2ee0) Integer component of the XOSC frequency in kHz - io_rw_32 xosc_freq_khz_int; - - _REG_(POWMAN_XOSC_FREQ_KHZ_FRAC_OFFSET) // POWMAN_XOSC_FREQ_KHZ_FRAC - // Informs the AON Timer of the fractional component of the clock frequency when running off the XOSC - // 0x0000ffff [15:0] XOSC_FREQ_KHZ_FRAC (0x0000) Fractional component of the XOSC frequency in kHz - io_rw_32 xosc_freq_khz_frac; - - _REG_(POWMAN_SET_TIME_63TO48_OFFSET) // POWMAN_SET_TIME_63TO48 - // 0x0000ffff [15:0] SET_TIME_63TO48 (0x0000) For setting the time, do not use for reading the time,... - io_rw_32 set_time_63to48; - - _REG_(POWMAN_SET_TIME_47TO32_OFFSET) // POWMAN_SET_TIME_47TO32 - // 0x0000ffff [15:0] SET_TIME_47TO32 (0x0000) For setting the time, do not use for reading the time,... - io_rw_32 set_time_47to32; - - _REG_(POWMAN_SET_TIME_31TO16_OFFSET) // POWMAN_SET_TIME_31TO16 - // 0x0000ffff [15:0] SET_TIME_31TO16 (0x0000) For setting the time, do not use for reading the time,... - io_rw_32 set_time_31to16; - - _REG_(POWMAN_SET_TIME_15TO0_OFFSET) // POWMAN_SET_TIME_15TO0 - // 0x0000ffff [15:0] SET_TIME_15TO0 (0x0000) For setting the time, do not use for reading the time,... - io_rw_32 set_time_15to0; - - _REG_(POWMAN_READ_TIME_UPPER_OFFSET) // POWMAN_READ_TIME_UPPER - // 0xffffffff [31:0] READ_TIME_UPPER (0x00000000) For reading bits 63:32 of the timer - io_ro_32 read_time_upper; - - _REG_(POWMAN_READ_TIME_LOWER_OFFSET) // POWMAN_READ_TIME_LOWER - // 0xffffffff [31:0] READ_TIME_LOWER (0x00000000) For reading bits 31:0 of the timer - io_ro_32 read_time_lower; - - _REG_(POWMAN_ALARM_TIME_63TO48_OFFSET) // POWMAN_ALARM_TIME_63TO48 - // 0x0000ffff [15:0] ALARM_TIME_63TO48 (0x0000) This field must only be written when POWMAN_ALARM_ENAB=0 - io_rw_32 alarm_time_63to48; - - _REG_(POWMAN_ALARM_TIME_47TO32_OFFSET) // POWMAN_ALARM_TIME_47TO32 - // 0x0000ffff [15:0] ALARM_TIME_47TO32 (0x0000) This field must only be written when POWMAN_ALARM_ENAB=0 - io_rw_32 alarm_time_47to32; - - _REG_(POWMAN_ALARM_TIME_31TO16_OFFSET) // POWMAN_ALARM_TIME_31TO16 - // 0x0000ffff [15:0] ALARM_TIME_31TO16 (0x0000) This field must only be written when POWMAN_ALARM_ENAB=0 - io_rw_32 alarm_time_31to16; - - _REG_(POWMAN_ALARM_TIME_15TO0_OFFSET) // POWMAN_ALARM_TIME_15TO0 - // 0x0000ffff [15:0] ALARM_TIME_15TO0 (0x0000) This field must only be written when POWMAN_ALARM_ENAB=0 - io_rw_32 alarm_time_15to0; - - _REG_(POWMAN_TIMER_OFFSET) // POWMAN_TIMER - // 0x00080000 [19] USING_GPIO_1HZ (0) Timer is synchronised to a 1hz gpio source - // 0x00040000 [18] USING_GPIO_1KHZ (0) Timer is running from a 1khz gpio source - // 0x00020000 [17] USING_LPOSC (0) Timer is running from lposc - // 0x00010000 [16] USING_XOSC (0) Timer is running from xosc - // 0x00002000 [13] USE_GPIO_1HZ (0) Selects the gpio source as the reference for the sec counter - // 0x00000400 [10] USE_GPIO_1KHZ (0) switch to gpio as the source of the 1kHz timer tick - // 0x00000200 [9] USE_XOSC (0) switch to xosc as the source of the 1kHz timer tick - // 0x00000100 [8] USE_LPOSC (0) Switch to lposc as the source of the 1kHz timer tick - // 0x00000040 [6] ALARM (0) Alarm has fired - // 0x00000020 [5] PWRUP_ON_ALARM (0) Alarm wakes the chip from low power mode - // 0x00000010 [4] ALARM_ENAB (0) Enables the alarm - // 0x00000004 [2] CLEAR (0) Clears the timer, does not disable the timer and does... - // 0x00000002 [1] RUN (0) Timer enable - // 0x00000001 [0] NONSEC_WRITE (0) Control whether Non-secure software can write to the... - io_rw_32 timer; - - // (Description copied from array index 0 register POWMAN_PWRUP0 applies similarly to other array indexes) - _REG_(POWMAN_PWRUP0_OFFSET) // POWMAN_PWRUP0 - // 4 GPIO powerup events can be configured to wake the chip up from a low power state - // 0x00000400 [10] RAW_STATUS (0) Value of selected gpio pin (only if enable == 1) - // 0x00000200 [9] STATUS (0) Status of gpio wakeup - // 0x00000100 [8] MODE (0) Edge or level detect - // 0x00000080 [7] DIRECTION (0) - // 0x00000040 [6] ENABLE (0) Set to 1 to enable the wakeup source - // 0x0000003f [5:0] SOURCE (0x3f) - io_rw_32 pwrup[4]; - - _REG_(POWMAN_CURRENT_PWRUP_REQ_OFFSET) // POWMAN_CURRENT_PWRUP_REQ - // Indicates current powerup request state + - // 0x0000007f [6:0] CURRENT_PWRUP_REQ (0x00) - io_ro_32 current_pwrup_req; - - _REG_(POWMAN_LAST_SWCORE_PWRUP_OFFSET) // POWMAN_LAST_SWCORE_PWRUP - // Indicates which pwrup source triggered the last switched-core power up + - // 0x0000007f [6:0] LAST_SWCORE_PWRUP (0x00) - io_ro_32 last_swcore_pwrup; - - _REG_(POWMAN_DBG_PWRCFG_OFFSET) // POWMAN_DBG_PWRCFG - // 0x00000001 [0] IGNORE (0) Ignore pwrup req from debugger - io_rw_32 dbg_pwrcfg; - - _REG_(POWMAN_BOOTDIS_OFFSET) // POWMAN_BOOTDIS - // Tell the bootrom to ignore the BOOT0 - // 0x00000002 [1] NEXT (0) This flag always ORs writes into its current contents - // 0x00000001 [0] NOW (0) When powman resets the RSM, the current value of... - io_rw_32 bootdis; - - _REG_(POWMAN_DBGCONFIG_OFFSET) // POWMAN_DBGCONFIG - // 0x0000000f [3:0] DP_INSTID (0x0) Configure DP instance ID for SWD multidrop selection - io_rw_32 dbgconfig; - - // (Description copied from array index 0 register POWMAN_SCRATCH0 applies similarly to other array indexes) - _REG_(POWMAN_SCRATCH0_OFFSET) // POWMAN_SCRATCH0 - // Scratch register - // 0xffffffff [31:0] SCRATCH0 (0x00000000) - io_rw_32 scratch[8]; - - // (Description copied from array index 0 register POWMAN_BOOT0 applies similarly to other array indexes) - _REG_(POWMAN_BOOT0_OFFSET) // POWMAN_BOOT0 - // Scratch register - // 0xffffffff [31:0] BOOT0 (0x00000000) - io_rw_32 boot[4]; - - _REG_(POWMAN_INTR_OFFSET) // POWMAN_INTR - // Raw Interrupts - // 0x00000008 [3] PWRUP_WHILE_WAITING (0) Source is state - // 0x00000004 [2] STATE_REQ_IGNORED (0) Source is state - // 0x00000002 [1] TIMER (0) - // 0x00000001 [0] VREG_OUTPUT_LOW (0) - io_rw_32 intr; - - _REG_(POWMAN_INTE_OFFSET) // POWMAN_INTE - // Interrupt Enable - // 0x00000008 [3] PWRUP_WHILE_WAITING (0) Source is state - // 0x00000004 [2] STATE_REQ_IGNORED (0) Source is state - // 0x00000002 [1] TIMER (0) - // 0x00000001 [0] VREG_OUTPUT_LOW (0) - io_rw_32 inte; - - _REG_(POWMAN_INTF_OFFSET) // POWMAN_INTF - // Interrupt Force - // 0x00000008 [3] PWRUP_WHILE_WAITING (0) Source is state - // 0x00000004 [2] STATE_REQ_IGNORED (0) Source is state - // 0x00000002 [1] TIMER (0) - // 0x00000001 [0] VREG_OUTPUT_LOW (0) - io_rw_32 intf; - - _REG_(POWMAN_INTS_OFFSET) // POWMAN_INTS - // Interrupt status after masking & forcing - // 0x00000008 [3] PWRUP_WHILE_WAITING (0) Source is state - // 0x00000004 [2] STATE_REQ_IGNORED (0) Source is state - // 0x00000002 [1] TIMER (0) - // 0x00000001 [0] VREG_OUTPUT_LOW (0) - io_ro_32 ints; -} powman_hw_t; - -#define powman_hw ((powman_hw_t *)POWMAN_BASE) -static_assert(sizeof (powman_hw_t) == 0x00f0, ""); - -#endif // _HARDWARE_STRUCTS_POWMAN_H - diff --git a/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/psm.h b/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/psm.h deleted file mode 100644 index 92144ac630..0000000000 --- a/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/psm.h +++ /dev/null @@ -1,148 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _HARDWARE_STRUCTS_PSM_H -#define _HARDWARE_STRUCTS_PSM_H - -/** - * \file rp2350/psm.h - */ - -#include "hardware/address_mapped.h" -#include "hardware/regs/psm.h" - -// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_psm -// -// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) -// _REG_(x) will link to the corresponding register in hardware/regs/psm.h. -// -// Bit-field descriptions are of the form: -// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION - -typedef struct { - _REG_(PSM_FRCE_ON_OFFSET) // PSM_FRCE_ON - // Force block out of reset (i - // 0x01000000 [24] PROC1 (0) - // 0x00800000 [23] PROC0 (0) - // 0x00400000 [22] ACCESSCTRL (0) - // 0x00200000 [21] SIO (0) - // 0x00100000 [20] XIP (0) - // 0x00080000 [19] SRAM9 (0) - // 0x00040000 [18] SRAM8 (0) - // 0x00020000 [17] SRAM7 (0) - // 0x00010000 [16] SRAM6 (0) - // 0x00008000 [15] SRAM5 (0) - // 0x00004000 [14] SRAM4 (0) - // 0x00002000 [13] SRAM3 (0) - // 0x00001000 [12] SRAM2 (0) - // 0x00000800 [11] SRAM1 (0) - // 0x00000400 [10] SRAM0 (0) - // 0x00000200 [9] BOOTRAM (0) - // 0x00000100 [8] ROM (0) - // 0x00000080 [7] BUSFABRIC (0) - // 0x00000040 [6] PSM_READY (0) - // 0x00000020 [5] CLOCKS (0) - // 0x00000010 [4] RESETS (0) - // 0x00000008 [3] XOSC (0) - // 0x00000004 [2] ROSC (0) - // 0x00000002 [1] OTP (0) - // 0x00000001 [0] PROC_COLD (0) - io_rw_32 frce_on; - - _REG_(PSM_FRCE_OFF_OFFSET) // PSM_FRCE_OFF - // Force into reset (i - // 0x01000000 [24] PROC1 (0) - // 0x00800000 [23] PROC0 (0) - // 0x00400000 [22] ACCESSCTRL (0) - // 0x00200000 [21] SIO (0) - // 0x00100000 [20] XIP (0) - // 0x00080000 [19] SRAM9 (0) - // 0x00040000 [18] SRAM8 (0) - // 0x00020000 [17] SRAM7 (0) - // 0x00010000 [16] SRAM6 (0) - // 0x00008000 [15] SRAM5 (0) - // 0x00004000 [14] SRAM4 (0) - // 0x00002000 [13] SRAM3 (0) - // 0x00001000 [12] SRAM2 (0) - // 0x00000800 [11] SRAM1 (0) - // 0x00000400 [10] SRAM0 (0) - // 0x00000200 [9] BOOTRAM (0) - // 0x00000100 [8] ROM (0) - // 0x00000080 [7] BUSFABRIC (0) - // 0x00000040 [6] PSM_READY (0) - // 0x00000020 [5] CLOCKS (0) - // 0x00000010 [4] RESETS (0) - // 0x00000008 [3] XOSC (0) - // 0x00000004 [2] ROSC (0) - // 0x00000002 [1] OTP (0) - // 0x00000001 [0] PROC_COLD (0) - io_rw_32 frce_off; - - _REG_(PSM_WDSEL_OFFSET) // PSM_WDSEL - // Set to 1 if the watchdog should reset this - // 0x01000000 [24] PROC1 (0) - // 0x00800000 [23] PROC0 (0) - // 0x00400000 [22] ACCESSCTRL (0) - // 0x00200000 [21] SIO (0) - // 0x00100000 [20] XIP (0) - // 0x00080000 [19] SRAM9 (0) - // 0x00040000 [18] SRAM8 (0) - // 0x00020000 [17] SRAM7 (0) - // 0x00010000 [16] SRAM6 (0) - // 0x00008000 [15] SRAM5 (0) - // 0x00004000 [14] SRAM4 (0) - // 0x00002000 [13] SRAM3 (0) - // 0x00001000 [12] SRAM2 (0) - // 0x00000800 [11] SRAM1 (0) - // 0x00000400 [10] SRAM0 (0) - // 0x00000200 [9] BOOTRAM (0) - // 0x00000100 [8] ROM (0) - // 0x00000080 [7] BUSFABRIC (0) - // 0x00000040 [6] PSM_READY (0) - // 0x00000020 [5] CLOCKS (0) - // 0x00000010 [4] RESETS (0) - // 0x00000008 [3] XOSC (0) - // 0x00000004 [2] ROSC (0) - // 0x00000002 [1] OTP (0) - // 0x00000001 [0] PROC_COLD (0) - io_rw_32 wdsel; - - _REG_(PSM_DONE_OFFSET) // PSM_DONE - // Is the subsystem ready? - // 0x01000000 [24] PROC1 (0) - // 0x00800000 [23] PROC0 (0) - // 0x00400000 [22] ACCESSCTRL (0) - // 0x00200000 [21] SIO (0) - // 0x00100000 [20] XIP (0) - // 0x00080000 [19] SRAM9 (0) - // 0x00040000 [18] SRAM8 (0) - // 0x00020000 [17] SRAM7 (0) - // 0x00010000 [16] SRAM6 (0) - // 0x00008000 [15] SRAM5 (0) - // 0x00004000 [14] SRAM4 (0) - // 0x00002000 [13] SRAM3 (0) - // 0x00001000 [12] SRAM2 (0) - // 0x00000800 [11] SRAM1 (0) - // 0x00000400 [10] SRAM0 (0) - // 0x00000200 [9] BOOTRAM (0) - // 0x00000100 [8] ROM (0) - // 0x00000080 [7] BUSFABRIC (0) - // 0x00000040 [6] PSM_READY (0) - // 0x00000020 [5] CLOCKS (0) - // 0x00000010 [4] RESETS (0) - // 0x00000008 [3] XOSC (0) - // 0x00000004 [2] ROSC (0) - // 0x00000002 [1] OTP (0) - // 0x00000001 [0] PROC_COLD (0) - io_ro_32 done; -} psm_hw_t; - -#define psm_hw ((psm_hw_t *)PSM_BASE) -static_assert(sizeof (psm_hw_t) == 0x0010, ""); - -#endif // _HARDWARE_STRUCTS_PSM_H - diff --git a/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/pwm.h b/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/pwm.h deleted file mode 100644 index be0e24e5dd..0000000000 --- a/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/pwm.h +++ /dev/null @@ -1,252 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _HARDWARE_STRUCTS_PWM_H -#define _HARDWARE_STRUCTS_PWM_H - -/** - * \file rp2350/pwm.h - */ - -#include "hardware/address_mapped.h" -#include "hardware/regs/pwm.h" - -// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_pwm -// -// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) -// _REG_(x) will link to the corresponding register in hardware/regs/pwm.h. -// -// Bit-field descriptions are of the form: -// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION - -typedef struct { - _REG_(PWM_CH0_CSR_OFFSET) // PWM_CH0_CSR - // Control and status register - // 0x00000080 [7] PH_ADV (0) Advance the phase of the counter by 1 count, while it is running - // 0x00000040 [6] PH_RET (0) Retard the phase of the counter by 1 count, while it is running - // 0x00000030 [5:4] DIVMODE (0x0) - // 0x00000008 [3] B_INV (0) Invert output B - // 0x00000004 [2] A_INV (0) Invert output A - // 0x00000002 [1] PH_CORRECT (0) 1: Enable phase-correct modulation - // 0x00000001 [0] EN (0) Enable the PWM channel - io_rw_32 csr; - - _REG_(PWM_CH0_DIV_OFFSET) // PWM_CH0_DIV - // INT and FRAC form a fixed-point fractional number - // 0x00000ff0 [11:4] INT (0x01) - // 0x0000000f [3:0] FRAC (0x0) - io_rw_32 div; - - _REG_(PWM_CH0_CTR_OFFSET) // PWM_CH0_CTR - // Direct access to the PWM counter - // 0x0000ffff [15:0] CH0_CTR (0x0000) - io_rw_32 ctr; - - _REG_(PWM_CH0_CC_OFFSET) // PWM_CH0_CC - // Counter compare values - // 0xffff0000 [31:16] B (0x0000) - // 0x0000ffff [15:0] A (0x0000) - io_rw_32 cc; - - _REG_(PWM_CH0_TOP_OFFSET) // PWM_CH0_TOP - // Counter wrap value - // 0x0000ffff [15:0] CH0_TOP (0xffff) - io_rw_32 top; -} pwm_slice_hw_t; - -typedef struct { - _REG_(PWM_IRQ0_INTE_OFFSET) // PWM_IRQ0_INTE - // Interrupt Enable for irq0 - // 0x00000800 [11] CH11 (0) - // 0x00000400 [10] CH10 (0) - // 0x00000200 [9] CH9 (0) - // 0x00000100 [8] CH8 (0) - // 0x00000080 [7] CH7 (0) - // 0x00000040 [6] CH6 (0) - // 0x00000020 [5] CH5 (0) - // 0x00000010 [4] CH4 (0) - // 0x00000008 [3] CH3 (0) - // 0x00000004 [2] CH2 (0) - // 0x00000002 [1] CH1 (0) - // 0x00000001 [0] CH0 (0) - io_rw_32 inte; - - _REG_(PWM_IRQ0_INTF_OFFSET) // PWM_IRQ0_INTF - // Interrupt Force for irq0 - // 0x00000800 [11] CH11 (0) - // 0x00000400 [10] CH10 (0) - // 0x00000200 [9] CH9 (0) - // 0x00000100 [8] CH8 (0) - // 0x00000080 [7] CH7 (0) - // 0x00000040 [6] CH6 (0) - // 0x00000020 [5] CH5 (0) - // 0x00000010 [4] CH4 (0) - // 0x00000008 [3] CH3 (0) - // 0x00000004 [2] CH2 (0) - // 0x00000002 [1] CH1 (0) - // 0x00000001 [0] CH0 (0) - io_rw_32 intf; - - _REG_(PWM_IRQ0_INTS_OFFSET) // PWM_IRQ0_INTS - // Interrupt status after masking & forcing for irq0 - // 0x00000800 [11] CH11 (0) - // 0x00000400 [10] CH10 (0) - // 0x00000200 [9] CH9 (0) - // 0x00000100 [8] CH8 (0) - // 0x00000080 [7] CH7 (0) - // 0x00000040 [6] CH6 (0) - // 0x00000020 [5] CH5 (0) - // 0x00000010 [4] CH4 (0) - // 0x00000008 [3] CH3 (0) - // 0x00000004 [2] CH2 (0) - // 0x00000002 [1] CH1 (0) - // 0x00000001 [0] CH0 (0) - io_ro_32 ints; -} pwm_irq_ctrl_hw_t; - -typedef struct { - pwm_slice_hw_t slice[12]; - - _REG_(PWM_EN_OFFSET) // PWM_EN - // This register aliases the CSR_EN bits for all channels - // 0x00000800 [11] CH11 (0) - // 0x00000400 [10] CH10 (0) - // 0x00000200 [9] CH9 (0) - // 0x00000100 [8] CH8 (0) - // 0x00000080 [7] CH7 (0) - // 0x00000040 [6] CH6 (0) - // 0x00000020 [5] CH5 (0) - // 0x00000010 [4] CH4 (0) - // 0x00000008 [3] CH3 (0) - // 0x00000004 [2] CH2 (0) - // 0x00000002 [1] CH1 (0) - // 0x00000001 [0] CH0 (0) - io_rw_32 en; - - _REG_(PWM_INTR_OFFSET) // PWM_INTR - // Raw Interrupts - // 0x00000800 [11] CH11 (0) - // 0x00000400 [10] CH10 (0) - // 0x00000200 [9] CH9 (0) - // 0x00000100 [8] CH8 (0) - // 0x00000080 [7] CH7 (0) - // 0x00000040 [6] CH6 (0) - // 0x00000020 [5] CH5 (0) - // 0x00000010 [4] CH4 (0) - // 0x00000008 [3] CH3 (0) - // 0x00000004 [2] CH2 (0) - // 0x00000002 [1] CH1 (0) - // 0x00000001 [0] CH0 (0) - io_rw_32 intr; - - union { - struct { - _REG_(PWM_IRQ0_INTE_OFFSET) // PWM_IRQ0_INTE - // Interrupt Enable for irq0 - // 0x00000800 [11] CH11 (0) - // 0x00000400 [10] CH10 (0) - // 0x00000200 [9] CH9 (0) - // 0x00000100 [8] CH8 (0) - // 0x00000080 [7] CH7 (0) - // 0x00000040 [6] CH6 (0) - // 0x00000020 [5] CH5 (0) - // 0x00000010 [4] CH4 (0) - // 0x00000008 [3] CH3 (0) - // 0x00000004 [2] CH2 (0) - // 0x00000002 [1] CH1 (0) - // 0x00000001 [0] CH0 (0) - io_rw_32 inte; - - _REG_(PWM_IRQ0_INTF_OFFSET) // PWM_IRQ0_INTF - // Interrupt Force for irq0 - // 0x00000800 [11] CH11 (0) - // 0x00000400 [10] CH10 (0) - // 0x00000200 [9] CH9 (0) - // 0x00000100 [8] CH8 (0) - // 0x00000080 [7] CH7 (0) - // 0x00000040 [6] CH6 (0) - // 0x00000020 [5] CH5 (0) - // 0x00000010 [4] CH4 (0) - // 0x00000008 [3] CH3 (0) - // 0x00000004 [2] CH2 (0) - // 0x00000002 [1] CH1 (0) - // 0x00000001 [0] CH0 (0) - io_rw_32 intf; - - _REG_(PWM_IRQ0_INTS_OFFSET) // PWM_IRQ0_INTS - // Interrupt status after masking & forcing for irq0 - // 0x00000800 [11] CH11 (0) - // 0x00000400 [10] CH10 (0) - // 0x00000200 [9] CH9 (0) - // 0x00000100 [8] CH8 (0) - // 0x00000080 [7] CH7 (0) - // 0x00000040 [6] CH6 (0) - // 0x00000020 [5] CH5 (0) - // 0x00000010 [4] CH4 (0) - // 0x00000008 [3] CH3 (0) - // 0x00000004 [2] CH2 (0) - // 0x00000002 [1] CH1 (0) - // 0x00000001 [0] CH0 (0) - io_rw_32 ints; - - _REG_(PWM_IRQ1_INTE_OFFSET) // PWM_IRQ1_INTE - // Interrupt Enable for irq1 - // 0x00000800 [11] CH11 (0) - // 0x00000400 [10] CH10 (0) - // 0x00000200 [9] CH9 (0) - // 0x00000100 [8] CH8 (0) - // 0x00000080 [7] CH7 (0) - // 0x00000040 [6] CH6 (0) - // 0x00000020 [5] CH5 (0) - // 0x00000010 [4] CH4 (0) - // 0x00000008 [3] CH3 (0) - // 0x00000004 [2] CH2 (0) - // 0x00000002 [1] CH1 (0) - // 0x00000001 [0] CH0 (0) - io_rw_32 inte1; - - _REG_(PWM_IRQ1_INTF_OFFSET) // PWM_IRQ1_INTF - // Interrupt Force for irq1 - // 0x00000800 [11] CH11 (0) - // 0x00000400 [10] CH10 (0) - // 0x00000200 [9] CH9 (0) - // 0x00000100 [8] CH8 (0) - // 0x00000080 [7] CH7 (0) - // 0x00000040 [6] CH6 (0) - // 0x00000020 [5] CH5 (0) - // 0x00000010 [4] CH4 (0) - // 0x00000008 [3] CH3 (0) - // 0x00000004 [2] CH2 (0) - // 0x00000002 [1] CH1 (0) - // 0x00000001 [0] CH0 (0) - io_rw_32 intf1; - - _REG_(PWM_IRQ1_INTS_OFFSET) // PWM_IRQ1_INTS - // Interrupt status after masking & forcing for irq1 - // 0x00000800 [11] CH11 (0) - // 0x00000400 [10] CH10 (0) - // 0x00000200 [9] CH9 (0) - // 0x00000100 [8] CH8 (0) - // 0x00000080 [7] CH7 (0) - // 0x00000040 [6] CH6 (0) - // 0x00000020 [5] CH5 (0) - // 0x00000010 [4] CH4 (0) - // 0x00000008 [3] CH3 (0) - // 0x00000004 [2] CH2 (0) - // 0x00000002 [1] CH1 (0) - // 0x00000001 [0] CH0 (0) - io_rw_32 ints1; - }; - pwm_irq_ctrl_hw_t irq_ctrl[2]; - }; -} pwm_hw_t; - -#define pwm_hw ((pwm_hw_t *)PWM_BASE) -static_assert(sizeof (pwm_hw_t) == 0x0110, ""); - -#endif // _HARDWARE_STRUCTS_PWM_H - diff --git a/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/qmi.h b/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/qmi.h deleted file mode 100644 index bbcbd76985..0000000000 --- a/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/qmi.h +++ /dev/null @@ -1,125 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _HARDWARE_STRUCTS_QMI_H -#define _HARDWARE_STRUCTS_QMI_H - -/** - * \file rp2350/qmi.h - */ - -#include "hardware/address_mapped.h" -#include "hardware/regs/qmi.h" - -// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_qmi -// -// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) -// _REG_(x) will link to the corresponding register in hardware/regs/qmi.h. -// -// Bit-field descriptions are of the form: -// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION - -typedef struct { - _REG_(QMI_M0_TIMING_OFFSET) // QMI_M0_TIMING - // Timing configuration register for memory address window 0 - // 0xc0000000 [31:30] COOLDOWN (0x1) Chip select cooldown period - // 0x30000000 [29:28] PAGEBREAK (0x0) When page break is enabled, chip select will... - // 0x02000000 [25] SELECT_SETUP (0) Add up to one additional system clock cycle of setup... - // 0x01800000 [24:23] SELECT_HOLD (0x0) Add up to three additional system clock cycles of active... - // 0x007e0000 [22:17] MAX_SELECT (0x00) Enforce a maximum assertion duration for this window's... - // 0x0001f000 [16:12] MIN_DESELECT (0x00) After this window's chip select is deasserted, it... - // 0x00000700 [10:8] RXDELAY (0x0) Delay the read data sample timing, in units of one half... - // 0x000000ff [7:0] CLKDIV (0x04) Clock divisor - io_rw_32 timing; - - _REG_(QMI_M0_RFMT_OFFSET) // QMI_M0_RFMT - // Read transfer format configuration for memory address window 0. - // 0x10000000 [28] DTR (0) Enable double transfer rate (DTR) for read commands:... - // 0x00070000 [18:16] DUMMY_LEN (0x0) Length of dummy phase between command suffix and data... - // 0x0000c000 [15:14] SUFFIX_LEN (0x0) Length of post-address command suffix, in units of 4 bits - // 0x00001000 [12] PREFIX_LEN (1) Length of command prefix, in units of 8 bits - // 0x00000300 [9:8] DATA_WIDTH (0x0) The width used for the data transfer - // 0x000000c0 [7:6] DUMMY_WIDTH (0x0) The width used for the dummy phase, if any - // 0x00000030 [5:4] SUFFIX_WIDTH (0x0) The width used for the post-address command suffix, if any - // 0x0000000c [3:2] ADDR_WIDTH (0x0) The transfer width used for the address - // 0x00000003 [1:0] PREFIX_WIDTH (0x0) The transfer width used for the command prefix, if any - io_rw_32 rfmt; - - _REG_(QMI_M0_RCMD_OFFSET) // QMI_M0_RCMD - // Command constants used for reads from memory address window 0. - // 0x0000ff00 [15:8] SUFFIX (0xa0) The command suffix bits following the address, if... - // 0x000000ff [7:0] PREFIX (0x03) The command prefix bits to prepend on each new transfer,... - io_rw_32 rcmd; - - _REG_(QMI_M0_WFMT_OFFSET) // QMI_M0_WFMT - // Write transfer format configuration for memory address window 0. - // 0x10000000 [28] DTR (0) Enable double transfer rate (DTR) for write commands:... - // 0x00070000 [18:16] DUMMY_LEN (0x0) Length of dummy phase between command suffix and data... - // 0x0000c000 [15:14] SUFFIX_LEN (0x0) Length of post-address command suffix, in units of 4 bits - // 0x00001000 [12] PREFIX_LEN (1) Length of command prefix, in units of 8 bits - // 0x00000300 [9:8] DATA_WIDTH (0x0) The width used for the data transfer - // 0x000000c0 [7:6] DUMMY_WIDTH (0x0) The width used for the dummy phase, if any - // 0x00000030 [5:4] SUFFIX_WIDTH (0x0) The width used for the post-address command suffix, if any - // 0x0000000c [3:2] ADDR_WIDTH (0x0) The transfer width used for the address - // 0x00000003 [1:0] PREFIX_WIDTH (0x0) The transfer width used for the command prefix, if any - io_rw_32 wfmt; - - _REG_(QMI_M0_WCMD_OFFSET) // QMI_M0_WCMD - // Command constants used for writes to memory address window 0. - // 0x0000ff00 [15:8] SUFFIX (0xa0) The command suffix bits following the address, if... - // 0x000000ff [7:0] PREFIX (0x02) The command prefix bits to prepend on each new transfer,... - io_rw_32 wcmd; -} qmi_mem_hw_t; - -typedef struct { - _REG_(QMI_DIRECT_CSR_OFFSET) // QMI_DIRECT_CSR - // Control and status for direct serial mode - // 0xc0000000 [31:30] RXDELAY (0x0) Delay the read data sample timing, in units of one half... - // 0x3fc00000 [29:22] CLKDIV (0x06) Clock divisor for direct serial mode - // 0x001c0000 [20:18] RXLEVEL (0x0) Current level of DIRECT_RX FIFO - // 0x00020000 [17] RXFULL (0) When 1, the DIRECT_RX FIFO is currently full - // 0x00010000 [16] RXEMPTY (0) When 1, the DIRECT_RX FIFO is currently empty - // 0x00007000 [14:12] TXLEVEL (0x0) Current level of DIRECT_TX FIFO - // 0x00000800 [11] TXEMPTY (0) When 1, the DIRECT_TX FIFO is currently empty - // 0x00000400 [10] TXFULL (0) When 1, the DIRECT_TX FIFO is currently full - // 0x00000080 [7] AUTO_CS1N (0) When 1, automatically assert the CS1n chip select line... - // 0x00000040 [6] AUTO_CS0N (0) When 1, automatically assert the CS0n chip select line... - // 0x00000008 [3] ASSERT_CS1N (0) When 1, assert (i - // 0x00000004 [2] ASSERT_CS0N (0) When 1, assert (i - // 0x00000002 [1] BUSY (0) Direct mode busy flag - // 0x00000001 [0] EN (0) Enable direct mode - io_rw_32 direct_csr; - - _REG_(QMI_DIRECT_TX_OFFSET) // QMI_DIRECT_TX - // Transmit FIFO for direct mode - // 0x00100000 [20] NOPUSH (0) Inhibit the RX FIFO push that would correspond to this... - // 0x00080000 [19] OE (0) Output enable (active-high) - // 0x00040000 [18] DWIDTH (0) Data width - // 0x00030000 [17:16] IWIDTH (0x0) Configure whether this FIFO record is transferred with... - // 0x0000ffff [15:0] DATA (0x0000) Data pushed here will be clocked out falling edges of... - io_wo_32 direct_tx; - - _REG_(QMI_DIRECT_RX_OFFSET) // QMI_DIRECT_RX - // Receive FIFO for direct mode - // 0x0000ffff [15:0] DIRECT_RX (0x0000) With each byte clocked out on the serial interface, one... - io_ro_32 direct_rx; - - qmi_mem_hw_t m[2]; - - // (Description copied from array index 0 register QMI_ATRANS0 applies similarly to other array indexes) - _REG_(QMI_ATRANS0_OFFSET) // QMI_ATRANS0 - // Configure address translation for XIP virtual addresses 0x000000 through 0x3fffff (a 4 MiB window starting at +0 MiB). - // 0x07ff0000 [26:16] SIZE (0x400) Translation aperture size for this virtual address... - // 0x00000fff [11:0] BASE (0x000) Physical address base for this virtual address range, in... - io_rw_32 atrans[8]; -} qmi_hw_t; - -#define qmi_hw ((qmi_hw_t *)XIP_QMI_BASE) -static_assert(sizeof (qmi_hw_t) == 0x0054, ""); - -#endif // _HARDWARE_STRUCTS_QMI_H - diff --git a/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/resets.h b/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/resets.h deleted file mode 100644 index 5d5d0e6983..0000000000 --- a/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/resets.h +++ /dev/null @@ -1,166 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _HARDWARE_STRUCTS_RESETS_H -#define _HARDWARE_STRUCTS_RESETS_H - -/** - * \file rp2350/resets.h - */ - -#include "hardware/address_mapped.h" -#include "hardware/regs/resets.h" - -// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_resets -// -// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) -// _REG_(x) will link to the corresponding register in hardware/regs/resets.h. -// -// Bit-field descriptions are of the form: -// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION - -/** \brief Resettable component numbers on RP2350 (used as typedef \ref reset_num_t) - * \ingroup hardware_resets - */ -typedef enum reset_num_rp2350 { - RESET_ADC = 0, ///< Select ADC to be reset - RESET_BUSCTRL = 1, ///< Select BUSCTRL to be reset - RESET_DMA = 2, ///< Select DMA to be reset - RESET_HSTX = 3, ///< Select HSTX to be reset - RESET_I2C0 = 4, ///< Select I2C0 to be reset - RESET_I2C1 = 5, ///< Select I2C1 to be reset - RESET_IO_BANK0 = 6, ///< Select IO_BANK0 to be reset - RESET_IO_QSPI = 7, ///< Select IO_QSPI to be reset - RESET_JTAG = 8, ///< Select JTAG to be reset - RESET_PADS_BANK0 = 9, ///< Select PADS_BANK0 to be reset - RESET_PADS_QSPI = 10, ///< Select PADS_QSPI to be reset - RESET_PIO0 = 11, ///< Select PIO0 to be reset - RESET_PIO1 = 12, ///< Select PIO1 to be reset - RESET_PIO2 = 13, ///< Select PIO2 to be reset - RESET_PLL_SYS = 14, ///< Select PLL_SYS to be reset - RESET_PLL_USB = 15, ///< Select PLL_USB to be reset - RESET_PWM = 16, ///< Select PWM to be reset - RESET_SHA256 = 17, ///< Select SHA256 to be reset - RESET_SPI0 = 18, ///< Select SPI0 to be reset - RESET_SPI1 = 19, ///< Select SPI1 to be reset - RESET_SYSCFG = 20, ///< Select SYSCFG to be reset - RESET_SYSINFO = 21, ///< Select SYSINFO to be reset - RESET_TBMAN = 22, ///< Select TBMAN to be reset - RESET_TIMER0 = 23, ///< Select TIMER0 to be reset - RESET_TIMER1 = 24, ///< Select TIMER1 to be reset - RESET_TRNG = 25, ///< Select TRNG to be reset - RESET_UART0 = 26, ///< Select UART0 to be reset - RESET_UART1 = 27, ///< Select UART1 to be reset - RESET_USBCTRL = 28, ///< Select USBCTRL to be reset - RESET_COUNT -} reset_num_t; - -/// \tag::resets_hw[] -typedef struct { - _REG_(RESETS_RESET_OFFSET) // RESETS_RESET - // 0x10000000 [28] USBCTRL (1) - // 0x08000000 [27] UART1 (1) - // 0x04000000 [26] UART0 (1) - // 0x02000000 [25] TRNG (1) - // 0x01000000 [24] TIMER1 (1) - // 0x00800000 [23] TIMER0 (1) - // 0x00400000 [22] TBMAN (1) - // 0x00200000 [21] SYSINFO (1) - // 0x00100000 [20] SYSCFG (1) - // 0x00080000 [19] SPI1 (1) - // 0x00040000 [18] SPI0 (1) - // 0x00020000 [17] SHA256 (1) - // 0x00010000 [16] PWM (1) - // 0x00008000 [15] PLL_USB (1) - // 0x00004000 [14] PLL_SYS (1) - // 0x00002000 [13] PIO2 (1) - // 0x00001000 [12] PIO1 (1) - // 0x00000800 [11] PIO0 (1) - // 0x00000400 [10] PADS_QSPI (1) - // 0x00000200 [9] PADS_BANK0 (1) - // 0x00000100 [8] JTAG (1) - // 0x00000080 [7] IO_QSPI (1) - // 0x00000040 [6] IO_BANK0 (1) - // 0x00000020 [5] I2C1 (1) - // 0x00000010 [4] I2C0 (1) - // 0x00000008 [3] HSTX (1) - // 0x00000004 [2] DMA (1) - // 0x00000002 [1] BUSCTRL (1) - // 0x00000001 [0] ADC (1) - io_rw_32 reset; - - _REG_(RESETS_WDSEL_OFFSET) // RESETS_WDSEL - // 0x10000000 [28] USBCTRL (0) - // 0x08000000 [27] UART1 (0) - // 0x04000000 [26] UART0 (0) - // 0x02000000 [25] TRNG (0) - // 0x01000000 [24] TIMER1 (0) - // 0x00800000 [23] TIMER0 (0) - // 0x00400000 [22] TBMAN (0) - // 0x00200000 [21] SYSINFO (0) - // 0x00100000 [20] SYSCFG (0) - // 0x00080000 [19] SPI1 (0) - // 0x00040000 [18] SPI0 (0) - // 0x00020000 [17] SHA256 (0) - // 0x00010000 [16] PWM (0) - // 0x00008000 [15] PLL_USB (0) - // 0x00004000 [14] PLL_SYS (0) - // 0x00002000 [13] PIO2 (0) - // 0x00001000 [12] PIO1 (0) - // 0x00000800 [11] PIO0 (0) - // 0x00000400 [10] PADS_QSPI (0) - // 0x00000200 [9] PADS_BANK0 (0) - // 0x00000100 [8] JTAG (0) - // 0x00000080 [7] IO_QSPI (0) - // 0x00000040 [6] IO_BANK0 (0) - // 0x00000020 [5] I2C1 (0) - // 0x00000010 [4] I2C0 (0) - // 0x00000008 [3] HSTX (0) - // 0x00000004 [2] DMA (0) - // 0x00000002 [1] BUSCTRL (0) - // 0x00000001 [0] ADC (0) - io_rw_32 wdsel; - - _REG_(RESETS_RESET_DONE_OFFSET) // RESETS_RESET_DONE - // 0x10000000 [28] USBCTRL (0) - // 0x08000000 [27] UART1 (0) - // 0x04000000 [26] UART0 (0) - // 0x02000000 [25] TRNG (0) - // 0x01000000 [24] TIMER1 (0) - // 0x00800000 [23] TIMER0 (0) - // 0x00400000 [22] TBMAN (0) - // 0x00200000 [21] SYSINFO (0) - // 0x00100000 [20] SYSCFG (0) - // 0x00080000 [19] SPI1 (0) - // 0x00040000 [18] SPI0 (0) - // 0x00020000 [17] SHA256 (0) - // 0x00010000 [16] PWM (0) - // 0x00008000 [15] PLL_USB (0) - // 0x00004000 [14] PLL_SYS (0) - // 0x00002000 [13] PIO2 (0) - // 0x00001000 [12] PIO1 (0) - // 0x00000800 [11] PIO0 (0) - // 0x00000400 [10] PADS_QSPI (0) - // 0x00000200 [9] PADS_BANK0 (0) - // 0x00000100 [8] JTAG (0) - // 0x00000080 [7] IO_QSPI (0) - // 0x00000040 [6] IO_BANK0 (0) - // 0x00000020 [5] I2C1 (0) - // 0x00000010 [4] I2C0 (0) - // 0x00000008 [3] HSTX (0) - // 0x00000004 [2] DMA (0) - // 0x00000002 [1] BUSCTRL (0) - // 0x00000001 [0] ADC (0) - io_ro_32 reset_done; -} resets_hw_t; -/// \end::resets_hw[] - -#define resets_hw ((resets_hw_t *)RESETS_BASE) -static_assert(sizeof (resets_hw_t) == 0x000c, ""); - -#endif // _HARDWARE_STRUCTS_RESETS_H - diff --git a/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/rosc.h b/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/rosc.h deleted file mode 100644 index 73503cc155..0000000000 --- a/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/rosc.h +++ /dev/null @@ -1,99 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _HARDWARE_STRUCTS_ROSC_H -#define _HARDWARE_STRUCTS_ROSC_H - -/** - * \file rp2350/rosc.h - */ - -#include "hardware/address_mapped.h" -#include "hardware/regs/rosc.h" - -// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_rosc -// -// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) -// _REG_(x) will link to the corresponding register in hardware/regs/rosc.h. -// -// Bit-field descriptions are of the form: -// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION - -typedef struct { - _REG_(ROSC_CTRL_OFFSET) // ROSC_CTRL - // Ring Oscillator control - // 0x00fff000 [23:12] ENABLE (-) On power-up this field is initialised to ENABLE + - // 0x00000fff [11:0] FREQ_RANGE (0xaa0) Controls the number of delay stages in the ROSC ring + - io_rw_32 ctrl; - - _REG_(ROSC_FREQA_OFFSET) // ROSC_FREQA - // Ring Oscillator frequency control A - // 0xffff0000 [31:16] PASSWD (0x0000) Set to 0x9696 to apply the settings + - // 0x00007000 [14:12] DS3 (0x0) Stage 3 drive strength - // 0x00000700 [10:8] DS2 (0x0) Stage 2 drive strength - // 0x00000080 [7] DS1_RANDOM (0) Randomises the stage 1 drive strength - // 0x00000070 [6:4] DS1 (0x0) Stage 1 drive strength - // 0x00000008 [3] DS0_RANDOM (0) Randomises the stage 0 drive strength - // 0x00000007 [2:0] DS0 (0x0) Stage 0 drive strength - io_rw_32 freqa; - - _REG_(ROSC_FREQB_OFFSET) // ROSC_FREQB - // Ring Oscillator frequency control B - // 0xffff0000 [31:16] PASSWD (0x0000) Set to 0x9696 to apply the settings + - // 0x00007000 [14:12] DS7 (0x0) Stage 7 drive strength - // 0x00000700 [10:8] DS6 (0x0) Stage 6 drive strength - // 0x00000070 [6:4] DS5 (0x0) Stage 5 drive strength - // 0x00000007 [2:0] DS4 (0x0) Stage 4 drive strength - io_rw_32 freqb; - - _REG_(ROSC_RANDOM_OFFSET) // ROSC_RANDOM - // Loads a value to the LFSR randomiser - // 0xffffffff [31:0] SEED (0x3f04b16d) - io_rw_32 random; - - _REG_(ROSC_DORMANT_OFFSET) // ROSC_DORMANT - // Ring Oscillator pause control - // 0xffffffff [31:0] DORMANT (-) This is used to save power by pausing the ROSC + - io_rw_32 dormant; - - _REG_(ROSC_DIV_OFFSET) // ROSC_DIV - // Controls the output divider - // 0x0000ffff [15:0] DIV (-) set to 0xaa00 + div where + - io_rw_32 div; - - _REG_(ROSC_PHASE_OFFSET) // ROSC_PHASE - // Controls the phase shifted output - // 0x00000ff0 [11:4] PASSWD (0x00) set to 0xaa + - // 0x00000008 [3] ENABLE (1) enable the phase-shifted output + - // 0x00000004 [2] FLIP (0) invert the phase-shifted output + - // 0x00000003 [1:0] SHIFT (0x0) phase shift the phase-shifted output by SHIFT input clocks + - io_rw_32 phase; - - _REG_(ROSC_STATUS_OFFSET) // ROSC_STATUS - // Ring Oscillator Status - // 0x80000000 [31] STABLE (0) Oscillator is running and stable - // 0x01000000 [24] BADWRITE (0) An invalid value has been written to CTRL_ENABLE or... - // 0x00010000 [16] DIV_RUNNING (-) post-divider is running + - // 0x00001000 [12] ENABLED (-) Oscillator is enabled but not necessarily running and stable + - io_rw_32 status; - - _REG_(ROSC_RANDOMBIT_OFFSET) // ROSC_RANDOMBIT - // Returns a 1 bit random value - // 0x00000001 [0] RANDOMBIT (1) - io_ro_32 randombit; - - _REG_(ROSC_COUNT_OFFSET) // ROSC_COUNT - // A down counter running at the ROSC frequency which counts to zero and stops. - // 0x0000ffff [15:0] COUNT (0x0000) - io_rw_32 count; -} rosc_hw_t; - -#define rosc_hw ((rosc_hw_t *)ROSC_BASE) -static_assert(sizeof (rosc_hw_t) == 0x0028, ""); - -#endif // _HARDWARE_STRUCTS_ROSC_H - diff --git a/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/sau.h b/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/sau.h deleted file mode 100644 index 803f35637d..0000000000 --- a/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/sau.h +++ /dev/null @@ -1,65 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _HARDWARE_STRUCTS_SAU_H -#define _HARDWARE_STRUCTS_SAU_H - -/** - * \file rp2350/sau.h - */ - -#include "hardware/address_mapped.h" -#include "hardware/regs/m33.h" - -// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_m33 -// -// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) -// _REG_(x) will link to the corresponding register in hardware/regs/m33.h. -// -// Bit-field descriptions are of the form: -// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION - -#if defined(__riscv) && PICO_FORBID_ARM_HEADERS_ON_RISCV -#error "Arm header included in a RISC-V build with PICO_FORBID_ARM_HEADERS_ON_RISCV=1" -#endif - -typedef struct { - _REG_(M33_SAU_CTRL_OFFSET) // M33_SAU_CTRL - // Allows enabling of the Security Attribution Unit - // 0x00000002 [1] ALLNS (0) When SAU_CTRL - // 0x00000001 [0] ENABLE (0) Enables the SAU - io_rw_32 ctrl; - - _REG_(M33_SAU_TYPE_OFFSET) // M33_SAU_TYPE - // Indicates the number of regions implemented by the Security Attribution Unit - // 0x000000ff [7:0] SREGION (0x08) The number of implemented SAU regions - io_ro_32 type; - - _REG_(M33_SAU_RNR_OFFSET) // M33_SAU_RNR - // Selects the region currently accessed by SAU_RBAR and SAU_RLAR - // 0x000000ff [7:0] REGION (0x00) Indicates the SAU region accessed by SAU_RBAR and SAU_RLAR - io_rw_32 rnr; - - _REG_(M33_SAU_RBAR_OFFSET) // M33_SAU_RBAR - // Provides indirect read and write access to the base address of the currently selected SAU region - // 0xffffffe0 [31:5] BADDR (0x0000000) Holds bits [31:5] of the base address for the selected SAU region - io_rw_32 rbar; - - _REG_(M33_SAU_RLAR_OFFSET) // M33_SAU_RLAR - // Provides indirect read and write access to the limit address of the currently selected SAU region - // 0xffffffe0 [31:5] LADDR (0x0000000) Holds bits [31:5] of the limit address for the selected... - // 0x00000002 [1] NSC (0) Controls whether Non-secure state is permitted to... - // 0x00000001 [0] ENABLE (0) SAU region enable - io_rw_32 rlar; -} armv8m_sau_hw_t; - -#define sau_hw ((armv8m_sau_hw_t *)(PPB_BASE + M33_SAU_CTRL_OFFSET)) -#define sau_ns_hw ((armv8m_sau_hw_t *)(PPB_NONSEC_BASE + M33_SAU_CTRL_OFFSET)) -static_assert(sizeof (armv8m_sau_hw_t) == 0x0014, ""); - -#endif // _HARDWARE_STRUCTS_SAU_H - diff --git a/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/scb.h b/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/scb.h deleted file mode 100644 index 9777023dc9..0000000000 --- a/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/scb.h +++ /dev/null @@ -1,264 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _HARDWARE_STRUCTS_SCB_H -#define _HARDWARE_STRUCTS_SCB_H - -/** - * \file rp2350/scb.h - */ - -#include "hardware/address_mapped.h" -#include "hardware/regs/m33.h" - -// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_m33 -// -// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) -// _REG_(x) will link to the corresponding register in hardware/regs/m33.h. -// -// Bit-field descriptions are of the form: -// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION - -#if defined(__riscv) && PICO_FORBID_ARM_HEADERS_ON_RISCV -#error "Arm header included in a RISC-V build with PICO_FORBID_ARM_HEADERS_ON_RISCV=1" -#endif - -typedef struct { - _REG_(M33_CPUID_OFFSET) // M33_CPUID - // Provides identification information for the PE, including an implementer code for the device and... - // 0xff000000 [31:24] IMPLEMENTER (0x41) This field must hold an implementer code that has been... - // 0x00f00000 [23:20] VARIANT (0x1) IMPLEMENTATION DEFINED variant number - // 0x000f0000 [19:16] ARCHITECTURE (0xf) Defines the Architecture implemented by the PE - // 0x0000fff0 [15:4] PARTNO (0xd21) IMPLEMENTATION DEFINED primary part number for the device - // 0x0000000f [3:0] REVISION (0x0) IMPLEMENTATION DEFINED revision number for the device - io_ro_32 cpuid; - - _REG_(M33_ICSR_OFFSET) // M33_ICSR - // Controls and provides status information for NMI, PendSV, SysTick and interrupts - // 0x80000000 [31] PENDNMISET (0) Indicates whether the NMI exception is pending - // 0x40000000 [30] PENDNMICLR (0) Allows the NMI exception pend state to be cleared - // 0x10000000 [28] PENDSVSET (0) Indicates whether the PendSV `FTSSS exception is pending - // 0x08000000 [27] PENDSVCLR (0) Allows the PendSV exception pend state to be cleared `FTSSS - // 0x04000000 [26] PENDSTSET (0) Indicates whether the SysTick `FTSSS exception is pending - // 0x02000000 [25] PENDSTCLR (0) Allows the SysTick exception pend state to be cleared `FTSSS - // 0x01000000 [24] STTNS (0) Controls whether in a single SysTick implementation, the... - // 0x00800000 [23] ISRPREEMPT (0) Indicates whether a pending exception will be serviced... - // 0x00400000 [22] ISRPENDING (0) Indicates whether an external interrupt, generated by... - // 0x001ff000 [20:12] VECTPENDING (0x000) The exception number of the highest priority pending and... - // 0x00000800 [11] RETTOBASE (0) In Handler mode, indicates whether there is more than... - // 0x000001ff [8:0] VECTACTIVE (0x000) The exception number of the current executing exception - io_rw_32 icsr; - - _REG_(M33_VTOR_OFFSET) // M33_VTOR - // Vector Table Offset Register - // 0xffffff80 [31:7] TBLOFF (0x0000000) Vector table base offset field - io_rw_32 vtor; - - _REG_(M33_AIRCR_OFFSET) // M33_AIRCR - // Application Interrupt and Reset Control Register - // 0xffff0000 [31:16] VECTKEY (0x0000) Register key: + - // 0x00008000 [15] ENDIANESS (0) Data endianness implemented: + - // 0x00004000 [14] PRIS (0) Prioritize Secure exceptions - // 0x00002000 [13] BFHFNMINS (0) BusFault, HardFault, and NMI Non-secure enable - // 0x00000700 [10:8] PRIGROUP (0x0) Interrupt priority grouping field - // 0x00000008 [3] SYSRESETREQS (0) System reset request, Secure state only - // 0x00000004 [2] SYSRESETREQ (0) Writing 1 to this bit causes the SYSRESETREQ signal to... - // 0x00000002 [1] VECTCLRACTIVE (0) Clears all active state information for fixed and... - io_rw_32 aircr; - - _REG_(M33_SCR_OFFSET) // M33_SCR - // System Control Register - // 0x00000010 [4] SEVONPEND (0) Send Event on Pending bit: + - // 0x00000008 [3] SLEEPDEEPS (0) 0 SLEEPDEEP is available to both security states + - // 0x00000004 [2] SLEEPDEEP (0) Controls whether the processor uses sleep or deep sleep... - // 0x00000002 [1] SLEEPONEXIT (0) Indicates sleep-on-exit when returning from Handler mode... - io_rw_32 scr; - - _REG_(M33_CCR_OFFSET) // M33_CCR - // Sets or returns configuration and control data - // 0x00040000 [18] BP (0) Enables program flow prediction `FTSSS - // 0x00020000 [17] IC (0) This is a global enable bit for instruction caches in... - // 0x00010000 [16] DC (0) Enables data caching of all data accesses to Normal memory `FTSSS - // 0x00000400 [10] STKOFHFNMIGN (0) Controls the effect of a stack limit violation while... - // 0x00000200 [9] RES1 (1) Reserved, RES1 - // 0x00000100 [8] BFHFNMIGN (0) Determines the effect of precise BusFaults on handlers... - // 0x00000010 [4] DIV_0_TRP (0) Controls the generation of a DIVBYZERO UsageFault when... - // 0x00000008 [3] UNALIGN_TRP (0) Controls the trapping of unaligned word or halfword accesses - // 0x00000002 [1] USERSETMPEND (0) Determines whether unprivileged accesses are permitted... - // 0x00000001 [0] RES1_1 (1) Reserved, RES1 - io_rw_32 ccr; - - // (Description copied from array index 0 register M33_SHPR1 applies similarly to other array indexes) - _REG_(M33_SHPR1_OFFSET) // M33_SHPR1 - // Sets or returns priority for system handlers 4 - 7 - // 0xe0000000 [31:29] PRI_7_3 (0x0) Priority of system handler 7, SecureFault - // 0x00e00000 [23:21] PRI_6_3 (0x0) Priority of system handler 6, SecureFault - // 0x0000e000 [15:13] PRI_5_3 (0x0) Priority of system handler 5, SecureFault - // 0x000000e0 [7:5] PRI_4_3 (0x0) Priority of system handler 4, SecureFault - io_rw_32 shpr[3]; - - _REG_(M33_SHCSR_OFFSET) // M33_SHCSR - // Provides access to the active and pending status of system exceptions - // 0x00200000 [21] HARDFAULTPENDED (0) `IAAMO the pending state of the HardFault exception `CTTSSS - // 0x00100000 [20] SECUREFAULTPENDED (0) `IAAMO the pending state of the SecureFault exception - // 0x00080000 [19] SECUREFAULTENA (0) `DW the SecureFault exception is enabled - // 0x00040000 [18] USGFAULTENA (0) `DW the UsageFault exception is enabled `FTSSS - // 0x00020000 [17] BUSFAULTENA (0) `DW the BusFault exception is enabled - // 0x00010000 [16] MEMFAULTENA (0) `DW the MemManage exception is enabled `FTSSS - // 0x00008000 [15] SVCALLPENDED (0) `IAAMO the pending state of the SVCall exception `FTSSS - // 0x00004000 [14] BUSFAULTPENDED (0) `IAAMO the pending state of the BusFault exception - // 0x00002000 [13] MEMFAULTPENDED (0) `IAAMO the pending state of the MemManage exception `FTSSS - // 0x00001000 [12] USGFAULTPENDED (0) The UsageFault exception is banked between Security... - // 0x00000800 [11] SYSTICKACT (0) `IAAMO the active state of the SysTick exception `FTSSS - // 0x00000400 [10] PENDSVACT (0) `IAAMO the active state of the PendSV exception `FTSSS - // 0x00000100 [8] MONITORACT (0) `IAAMO the active state of the DebugMonitor exception - // 0x00000080 [7] SVCALLACT (0) `IAAMO the active state of the SVCall exception `FTSSS - // 0x00000020 [5] NMIACT (0) `IAAMO the active state of the NMI exception - // 0x00000010 [4] SECUREFAULTACT (0) `IAAMO the active state of the SecureFault exception - // 0x00000008 [3] USGFAULTACT (0) `IAAMO the active state of the UsageFault exception `FTSSS - // 0x00000004 [2] HARDFAULTACT (0) Indicates and allows limited modification of the active... - // 0x00000002 [1] BUSFAULTACT (0) `IAAMO the active state of the BusFault exception - // 0x00000001 [0] MEMFAULTACT (0) `IAAMO the active state of the MemManage exception `FTSSS - io_rw_32 shcsr; - - _REG_(M33_CFSR_OFFSET) // M33_CFSR - // Contains the three Configurable Fault Status Registers - // 0x02000000 [25] UFSR_DIVBYZERO (0) Sticky flag indicating whether an integer division by... - // 0x01000000 [24] UFSR_UNALIGNED (0) Sticky flag indicating whether an unaligned access error... - // 0x00100000 [20] UFSR_STKOF (0) Sticky flag indicating whether a stack overflow error... - // 0x00080000 [19] UFSR_NOCP (0) Sticky flag indicating whether a coprocessor disabled or... - // 0x00040000 [18] UFSR_INVPC (0) Sticky flag indicating whether an integrity check error... - // 0x00020000 [17] UFSR_INVSTATE (0) Sticky flag indicating whether an EPSR - // 0x00010000 [16] UFSR_UNDEFINSTR (0) Sticky flag indicating whether an undefined instruction... - // 0x00008000 [15] BFSR_BFARVALID (0) Indicates validity of the contents of the BFAR register - // 0x00002000 [13] BFSR_LSPERR (0) Records whether a BusFault occurred during FP lazy state... - // 0x00001000 [12] BFSR_STKERR (0) Records whether a derived BusFault occurred during... - // 0x00000800 [11] BFSR_UNSTKERR (0) Records whether a derived BusFault occurred during... - // 0x00000400 [10] BFSR_IMPRECISERR (0) Records whether an imprecise data access error has occurred - // 0x00000200 [9] BFSR_PRECISERR (0) Records whether a precise data access error has occurred - // 0x00000100 [8] BFSR_IBUSERR (0) Records whether a BusFault on an instruction prefetch... - // 0x000000ff [7:0] MMFSR (0x00) Provides information on MemManage exceptions - io_rw_32 cfsr; - - _REG_(M33_HFSR_OFFSET) // M33_HFSR - // Shows the cause of any HardFaults - // 0x80000000 [31] DEBUGEVT (0) Indicates when a Debug event has occurred - // 0x40000000 [30] FORCED (0) Indicates that a fault with configurable priority has... - // 0x00000002 [1] VECTTBL (0) Indicates when a fault has occurred because of a vector... - io_rw_32 hfsr; - - _REG_(M33_DFSR_OFFSET) // M33_DFSR - // Shows which debug event occurred - // 0x00000010 [4] EXTERNAL (0) Sticky flag indicating whether an External debug request... - // 0x00000008 [3] VCATCH (0) Sticky flag indicating whether a Vector catch debug... - // 0x00000004 [2] DWTTRAP (0) Sticky flag indicating whether a Watchpoint debug event... - // 0x00000002 [1] BKPT (0) Sticky flag indicating whether a Breakpoint debug event... - // 0x00000001 [0] HALTED (0) Sticky flag indicating that a Halt request debug event... - io_rw_32 dfsr; - - _REG_(M33_MMFAR_OFFSET) // M33_MMFAR - // Shows the address of the memory location that caused an MPU fault - // 0xffffffff [31:0] ADDRESS (0x00000000) This register is updated with the address of a location... - io_rw_32 mmfar; - - _REG_(M33_BFAR_OFFSET) // M33_BFAR - // Shows the address associated with a precise data access BusFault - // 0xffffffff [31:0] ADDRESS (0x00000000) This register is updated with the address of a location... - io_rw_32 bfar; - - uint32_t _pad0; - - // (Description copied from array index 0 register M33_ID_PFR0 applies similarly to other array indexes) - _REG_(M33_ID_PFR0_OFFSET) // M33_ID_PFR0 - // Gives top-level information about the instruction set supported by the PE - // 0x000000f0 [7:4] STATE1 (0x3) T32 instruction set support - // 0x0000000f [3:0] STATE0 (0x0) A32 instruction set support - io_ro_32 id_pfr[2]; - - _REG_(M33_ID_DFR0_OFFSET) // M33_ID_DFR0 - // Provides top level information about the debug system - // 0x00f00000 [23:20] MPROFDBG (0x2) Indicates the supported M-profile debug architecture - io_ro_32 id_dfr0; - - _REG_(M33_ID_AFR0_OFFSET) // M33_ID_AFR0 - // Provides information about the IMPLEMENTATION DEFINED features of the PE - // 0x0000f000 [15:12] IMPDEF3 (0x0) IMPLEMENTATION DEFINED meaning - // 0x00000f00 [11:8] IMPDEF2 (0x0) IMPLEMENTATION DEFINED meaning - // 0x000000f0 [7:4] IMPDEF1 (0x0) IMPLEMENTATION DEFINED meaning - // 0x0000000f [3:0] IMPDEF0 (0x0) IMPLEMENTATION DEFINED meaning - io_ro_32 id_afr0; - - // (Description copied from array index 0 register M33_ID_MMFR0 applies similarly to other array indexes) - _REG_(M33_ID_MMFR0_OFFSET) // M33_ID_MMFR0 - // Provides information about the implemented memory model and memory management support - // 0x00f00000 [23:20] AUXREG (0x1) Indicates support for Auxiliary Control Registers - // 0x000f0000 [19:16] TCM (0x0) Indicates support for tightly coupled memories (TCMs) - // 0x0000f000 [15:12] SHARELVL (0x1) Indicates the number of shareability levels implemented - // 0x00000f00 [11:8] OUTERSHR (0xf) Indicates the outermost shareability domain implemented - // 0x000000f0 [7:4] PMSA (0x4) Indicates support for the protected memory system... - io_ro_32 id_mmfr[4]; - - // (Description copied from array index 0 register M33_ID_ISAR0 applies similarly to other array indexes) - _REG_(M33_ID_ISAR0_OFFSET) // M33_ID_ISAR0 - // Provides information about the instruction set implemented by the PE - // 0x0f000000 [27:24] DIVIDE (0x8) Indicates the supported Divide instructions - // 0x00f00000 [23:20] DEBUG (0x0) Indicates the implemented Debug instructions - // 0x000f0000 [19:16] COPROC (0x9) Indicates the supported Coprocessor instructions - // 0x0000f000 [15:12] CMPBRANCH (0x2) Indicates the supported combined Compare and Branch instructions - // 0x00000f00 [11:8] BITFIELD (0x3) Indicates the supported bit field instructions - // 0x000000f0 [7:4] BITCOUNT (0x0) Indicates the supported bit count instructions - io_ro_32 id_isar[6]; - - uint32_t _pad1; - - _REG_(M33_CTR_OFFSET) // M33_CTR - // Provides information about the architecture of the caches - // 0x80000000 [31] RES1 (1) Reserved, RES1 - // 0x0f000000 [27:24] CWG (0x0) Log2 of the number of words of the maximum size of... - // 0x00f00000 [23:20] ERG (0x0) Log2 of the number of words of the maximum size of the... - // 0x000f0000 [19:16] DMINLINE (0x0) Log2 of the number of words in the smallest cache line... - // 0x0000c000 [15:14] RES1_1 (0x3) Reserved, RES1 - // 0x0000000f [3:0] IMINLINE (0x0) Log2 of the number of words in the smallest cache line... - io_ro_32 ctr; - - uint32_t _pad2[2]; - - _REG_(M33_CPACR_OFFSET) // M33_CPACR - // Specifies the access privileges for coprocessors and the FP Extension - // 0x00c00000 [23:22] CP11 (0x0) The value in this field is ignored - // 0x00300000 [21:20] CP10 (0x0) Defines the access rights for the floating-point functionality - // 0x0000c000 [15:14] CP7 (0x0) Controls access privileges for coprocessor 7 - // 0x00003000 [13:12] CP6 (0x0) Controls access privileges for coprocessor 6 - // 0x00000c00 [11:10] CP5 (0x0) Controls access privileges for coprocessor 5 - // 0x00000300 [9:8] CP4 (0x0) Controls access privileges for coprocessor 4 - // 0x000000c0 [7:6] CP3 (0x0) Controls access privileges for coprocessor 3 - // 0x00000030 [5:4] CP2 (0x0) Controls access privileges for coprocessor 2 - // 0x0000000c [3:2] CP1 (0x0) Controls access privileges for coprocessor 1 - // 0x00000003 [1:0] CP0 (0x0) Controls access privileges for coprocessor 0 - io_rw_32 cpacr; - - _REG_(M33_NSACR_OFFSET) // M33_NSACR - // Defines the Non-secure access permissions for both the FP Extension and coprocessors CP0 to CP7 - // 0x00000800 [11] CP11 (0) Enables Non-secure access to the Floating-point Extension - // 0x00000400 [10] CP10 (0) Enables Non-secure access to the Floating-point Extension - // 0x00000080 [7] CP7 (0) Enables Non-secure access to coprocessor CP7 - // 0x00000040 [6] CP6 (0) Enables Non-secure access to coprocessor CP6 - // 0x00000020 [5] CP5 (0) Enables Non-secure access to coprocessor CP5 - // 0x00000010 [4] CP4 (0) Enables Non-secure access to coprocessor CP4 - // 0x00000008 [3] CP3 (0) Enables Non-secure access to coprocessor CP3 - // 0x00000004 [2] CP2 (0) Enables Non-secure access to coprocessor CP2 - // 0x00000002 [1] CP1 (0) Enables Non-secure access to coprocessor CP1 - // 0x00000001 [0] CP0 (0) Enables Non-secure access to coprocessor CP0 - io_rw_32 nsacr; -} armv8m_scb_hw_t; - -#define scb_hw ((armv8m_scb_hw_t *)(PPB_BASE + M33_CPUID_OFFSET)) -#define scb_ns_hw ((armv8m_scb_hw_t *)(PPB_NONSEC_BASE + M33_CPUID_OFFSET)) -static_assert(sizeof (armv8m_scb_hw_t) == 0x0090, ""); - -#endif // _HARDWARE_STRUCTS_SCB_H - diff --git a/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/sha256.h b/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/sha256.h deleted file mode 100644 index 248a00ab4b..0000000000 --- a/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/sha256.h +++ /dev/null @@ -1,53 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _HARDWARE_STRUCTS_SHA256_H -#define _HARDWARE_STRUCTS_SHA256_H - -/** - * \file rp2350/sha256.h - */ - -#include "hardware/address_mapped.h" -#include "hardware/regs/sha256.h" - -// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_sha256 -// -// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) -// _REG_(x) will link to the corresponding register in hardware/regs/sha256.h. -// -// Bit-field descriptions are of the form: -// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION - -typedef struct { - _REG_(SHA256_CSR_OFFSET) // SHA256_CSR - // Control and status register - // 0x00001000 [12] BSWAP (1) Enable byte swapping of 32-bit values at the point they... - // 0x00000300 [9:8] DMA_SIZE (0x2) Configure DREQ logic for the correct DMA data size - // 0x00000010 [4] ERR_WDATA_NOT_RDY (0) Set when a write occurs whilst the SHA-256 core is not... - // 0x00000004 [2] SUM_VLD (1) If 1, the SHA-256 checksum presented in registers SUM0... - // 0x00000002 [1] WDATA_RDY (1) If 1, the SHA-256 core is ready to accept more data... - // 0x00000001 [0] START (0) Write 1 to prepare the SHA-256 core for a new checksum - io_rw_32 csr; - - _REG_(SHA256_WDATA_OFFSET) // SHA256_WDATA - // Write data register - // 0xffffffff [31:0] WDATA (0x00000000) After pulsing START and writing 16 words of data to this... - io_wo_32 wdata; - - // (Description copied from array index 0 register SHA256_SUM0 applies similarly to other array indexes) - _REG_(SHA256_SUM0_OFFSET) // SHA256_SUM0 - // 256-bit checksum result - // 0xffffffff [31:0] SUM0 (0x00000000) - io_ro_32 sum[8]; -} sha256_hw_t; - -#define sha256_hw ((sha256_hw_t *)SHA256_BASE) -static_assert(sizeof (sha256_hw_t) == 0x0028, ""); - -#endif // _HARDWARE_STRUCTS_SHA256_H - diff --git a/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/sio.h b/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/sio.h deleted file mode 100644 index 49a452c8ad..0000000000 --- a/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/sio.h +++ /dev/null @@ -1,336 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _HARDWARE_STRUCTS_SIO_H -#define _HARDWARE_STRUCTS_SIO_H - -/** - * \file rp2350/sio.h - */ - -#include "hardware/address_mapped.h" -#include "hardware/regs/sio.h" -#include "hardware/structs/interp.h" - -// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_sio -// -// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) -// _REG_(x) will link to the corresponding register in hardware/regs/sio.h. -// -// Bit-field descriptions are of the form: -// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION - - -typedef struct { - _REG_(SIO_CPUID_OFFSET) // SIO_CPUID - // Processor core identifier - // 0xffffffff [31:0] CPUID (-) Value is 0 when read from processor core 0, and 1 when... - io_ro_32 cpuid; - - _REG_(SIO_GPIO_IN_OFFSET) // SIO_GPIO_IN - // Input value for GPIO0 - // 0xffffffff [31:0] GPIO_IN (0x00000000) - io_ro_32 gpio_in; - - _REG_(SIO_GPIO_HI_IN_OFFSET) // SIO_GPIO_HI_IN - // Input value on GPIO32 - // 0xf0000000 [31:28] QSPI_SD (0x0) Input value on QSPI SD0 (MOSI), SD1 (MISO), SD2 and SD3 pins - // 0x08000000 [27] QSPI_CSN (0) Input value on QSPI CSn pin - // 0x04000000 [26] QSPI_SCK (0) Input value on QSPI SCK pin - // 0x02000000 [25] USB_DM (0) Input value on USB D- pin - // 0x01000000 [24] USB_DP (0) Input value on USB D+ pin - // 0x0000ffff [15:0] GPIO (0x0000) Input value on GPIO32 - io_ro_32 gpio_hi_in; - - uint32_t _pad0; - - _REG_(SIO_GPIO_OUT_OFFSET) // SIO_GPIO_OUT - // GPIO0 - // 0xffffffff [31:0] GPIO_OUT (0x00000000) Set output level (1/0 -> high/low) for GPIO0 - io_rw_32 gpio_out; - - _REG_(SIO_GPIO_HI_OUT_OFFSET) // SIO_GPIO_HI_OUT - // Output value for GPIO32 - // 0xf0000000 [31:28] QSPI_SD (0x0) Output value for QSPI SD0 (MOSI), SD1 (MISO), SD2 and SD3 pins - // 0x08000000 [27] QSPI_CSN (0) Output value for QSPI CSn pin - // 0x04000000 [26] QSPI_SCK (0) Output value for QSPI SCK pin - // 0x02000000 [25] USB_DM (0) Output value for USB D- pin - // 0x01000000 [24] USB_DP (0) Output value for USB D+ pin - // 0x0000ffff [15:0] GPIO (0x0000) Output value for GPIO32 - io_rw_32 gpio_hi_out; - - _REG_(SIO_GPIO_OUT_SET_OFFSET) // SIO_GPIO_OUT_SET - // GPIO0 - // 0xffffffff [31:0] GPIO_OUT_SET (0x00000000) Perform an atomic bit-set on GPIO_OUT, i - io_wo_32 gpio_set; - - _REG_(SIO_GPIO_HI_OUT_SET_OFFSET) // SIO_GPIO_HI_OUT_SET - // Output value set for GPIO32 - // 0xf0000000 [31:28] QSPI_SD (0x0) - // 0x08000000 [27] QSPI_CSN (0) - // 0x04000000 [26] QSPI_SCK (0) - // 0x02000000 [25] USB_DM (0) - // 0x01000000 [24] USB_DP (0) - // 0x0000ffff [15:0] GPIO (0x0000) - io_wo_32 gpio_hi_set; - - _REG_(SIO_GPIO_OUT_CLR_OFFSET) // SIO_GPIO_OUT_CLR - // GPIO0 - // 0xffffffff [31:0] GPIO_OUT_CLR (0x00000000) Perform an atomic bit-clear on GPIO_OUT, i - io_wo_32 gpio_clr; - - _REG_(SIO_GPIO_HI_OUT_CLR_OFFSET) // SIO_GPIO_HI_OUT_CLR - // Output value clear for GPIO32 - // 0xf0000000 [31:28] QSPI_SD (0x0) - // 0x08000000 [27] QSPI_CSN (0) - // 0x04000000 [26] QSPI_SCK (0) - // 0x02000000 [25] USB_DM (0) - // 0x01000000 [24] USB_DP (0) - // 0x0000ffff [15:0] GPIO (0x0000) - io_wo_32 gpio_hi_clr; - - _REG_(SIO_GPIO_OUT_XOR_OFFSET) // SIO_GPIO_OUT_XOR - // GPIO0 - // 0xffffffff [31:0] GPIO_OUT_XOR (0x00000000) Perform an atomic bitwise XOR on GPIO_OUT, i - io_wo_32 gpio_togl; - - _REG_(SIO_GPIO_HI_OUT_XOR_OFFSET) // SIO_GPIO_HI_OUT_XOR - // Output value XOR for GPIO32 - // 0xf0000000 [31:28] QSPI_SD (0x0) - // 0x08000000 [27] QSPI_CSN (0) - // 0x04000000 [26] QSPI_SCK (0) - // 0x02000000 [25] USB_DM (0) - // 0x01000000 [24] USB_DP (0) - // 0x0000ffff [15:0] GPIO (0x0000) - io_wo_32 gpio_hi_togl; - - _REG_(SIO_GPIO_OE_OFFSET) // SIO_GPIO_OE - // GPIO0 - // 0xffffffff [31:0] GPIO_OE (0x00000000) Set output enable (1/0 -> output/input) for GPIO0 - io_rw_32 gpio_oe; - - _REG_(SIO_GPIO_HI_OE_OFFSET) // SIO_GPIO_HI_OE - // Output enable value for GPIO32 - // 0xf0000000 [31:28] QSPI_SD (0x0) Output enable value for QSPI SD0 (MOSI), SD1 (MISO), SD2... - // 0x08000000 [27] QSPI_CSN (0) Output enable value for QSPI CSn pin - // 0x04000000 [26] QSPI_SCK (0) Output enable value for QSPI SCK pin - // 0x02000000 [25] USB_DM (0) Output enable value for USB D- pin - // 0x01000000 [24] USB_DP (0) Output enable value for USB D+ pin - // 0x0000ffff [15:0] GPIO (0x0000) Output enable value for GPIO32 - io_rw_32 gpio_hi_oe; - - _REG_(SIO_GPIO_OE_SET_OFFSET) // SIO_GPIO_OE_SET - // GPIO0 - // 0xffffffff [31:0] GPIO_OE_SET (0x00000000) Perform an atomic bit-set on GPIO_OE, i - io_wo_32 gpio_oe_set; - - _REG_(SIO_GPIO_HI_OE_SET_OFFSET) // SIO_GPIO_HI_OE_SET - // Output enable set for GPIO32 - // 0xf0000000 [31:28] QSPI_SD (0x0) - // 0x08000000 [27] QSPI_CSN (0) - // 0x04000000 [26] QSPI_SCK (0) - // 0x02000000 [25] USB_DM (0) - // 0x01000000 [24] USB_DP (0) - // 0x0000ffff [15:0] GPIO (0x0000) - io_wo_32 gpio_hi_oe_set; - - _REG_(SIO_GPIO_OE_CLR_OFFSET) // SIO_GPIO_OE_CLR - // GPIO0 - // 0xffffffff [31:0] GPIO_OE_CLR (0x00000000) Perform an atomic bit-clear on GPIO_OE, i - io_wo_32 gpio_oe_clr; - - _REG_(SIO_GPIO_HI_OE_CLR_OFFSET) // SIO_GPIO_HI_OE_CLR - // Output enable clear for GPIO32 - // 0xf0000000 [31:28] QSPI_SD (0x0) - // 0x08000000 [27] QSPI_CSN (0) - // 0x04000000 [26] QSPI_SCK (0) - // 0x02000000 [25] USB_DM (0) - // 0x01000000 [24] USB_DP (0) - // 0x0000ffff [15:0] GPIO (0x0000) - io_wo_32 gpio_hi_oe_clr; - - _REG_(SIO_GPIO_OE_XOR_OFFSET) // SIO_GPIO_OE_XOR - // GPIO0 - // 0xffffffff [31:0] GPIO_OE_XOR (0x00000000) Perform an atomic bitwise XOR on GPIO_OE, i - io_wo_32 gpio_oe_togl; - - _REG_(SIO_GPIO_HI_OE_XOR_OFFSET) // SIO_GPIO_HI_OE_XOR - // Output enable XOR for GPIO32 - // 0xf0000000 [31:28] QSPI_SD (0x0) - // 0x08000000 [27] QSPI_CSN (0) - // 0x04000000 [26] QSPI_SCK (0) - // 0x02000000 [25] USB_DM (0) - // 0x01000000 [24] USB_DP (0) - // 0x0000ffff [15:0] GPIO (0x0000) - io_wo_32 gpio_hi_oe_togl; - - _REG_(SIO_FIFO_ST_OFFSET) // SIO_FIFO_ST - // Status register for inter-core FIFOs (mailboxes). - // 0x00000008 [3] ROE (0) Sticky flag indicating the RX FIFO was read when empty - // 0x00000004 [2] WOF (0) Sticky flag indicating the TX FIFO was written when full - // 0x00000002 [1] RDY (1) Value is 1 if this core's TX FIFO is not full (i - // 0x00000001 [0] VLD (0) Value is 1 if this core's RX FIFO is not empty (i - io_rw_32 fifo_st; - - _REG_(SIO_FIFO_WR_OFFSET) // SIO_FIFO_WR - // Write access to this core's TX FIFO - // 0xffffffff [31:0] FIFO_WR (0x00000000) - io_wo_32 fifo_wr; - - _REG_(SIO_FIFO_RD_OFFSET) // SIO_FIFO_RD - // Read access to this core's RX FIFO - // 0xffffffff [31:0] FIFO_RD (-) - io_ro_32 fifo_rd; - - _REG_(SIO_SPINLOCK_ST_OFFSET) // SIO_SPINLOCK_ST - // Spinlock state - // 0xffffffff [31:0] SPINLOCK_ST (0x00000000) - io_ro_32 spinlock_st; - - uint32_t _pad1[8]; - - interp_hw_t interp[2]; - - // (Description copied from array index 0 register SIO_SPINLOCK0 applies similarly to other array indexes) - _REG_(SIO_SPINLOCK0_OFFSET) // SIO_SPINLOCK0 - // Spinlock register 0 - // 0xffffffff [31:0] SPINLOCK0 (0x00000000) - io_rw_32 spinlock[32]; - - _REG_(SIO_DOORBELL_OUT_SET_OFFSET) // SIO_DOORBELL_OUT_SET - // Trigger a doorbell interrupt on the opposite core - // 0x000000ff [7:0] DOORBELL_OUT_SET (0x00) - io_rw_32 doorbell_out_set; - - _REG_(SIO_DOORBELL_OUT_CLR_OFFSET) // SIO_DOORBELL_OUT_CLR - // Clear doorbells which have been posted to the opposite core - // 0x000000ff [7:0] DOORBELL_OUT_CLR (0x00) - io_rw_32 doorbell_out_clr; - - _REG_(SIO_DOORBELL_IN_SET_OFFSET) // SIO_DOORBELL_IN_SET - // Write 1s to trigger doorbell interrupts on this core - // 0x000000ff [7:0] DOORBELL_IN_SET (0x00) - io_rw_32 doorbell_in_set; - - _REG_(SIO_DOORBELL_IN_CLR_OFFSET) // SIO_DOORBELL_IN_CLR - // Check and acknowledge doorbells posted to this core - // 0x000000ff [7:0] DOORBELL_IN_CLR (0x00) - io_rw_32 doorbell_in_clr; - - _REG_(SIO_PERI_NONSEC_OFFSET) // SIO_PERI_NONSEC - // Detach certain core-local peripherals from Secure SIO, and attach them to Non-secure SIO, so... - // 0x00000020 [5] TMDS (0) IF 1, detach TMDS encoder (of this core) from the Secure... - // 0x00000002 [1] INTERP1 (0) If 1, detach interpolator 1 (of this core) from the... - // 0x00000001 [0] INTERP0 (0) If 1, detach interpolator 0 (of this core) from the... - io_rw_32 peri_nonsec; - - uint32_t _pad2[3]; - - _REG_(SIO_RISCV_SOFTIRQ_OFFSET) // SIO_RISCV_SOFTIRQ - // Control the assertion of the standard software interrupt (MIP - // 0x00000200 [9] CORE1_CLR (0) Write 1 to atomically clear the core 1 software interrupt flag - // 0x00000100 [8] CORE0_CLR (0) Write 1 to atomically clear the core 0 software interrupt flag - // 0x00000002 [1] CORE1_SET (0) Write 1 to atomically set the core 1 software interrupt flag - // 0x00000001 [0] CORE0_SET (0) Write 1 to atomically set the core 0 software interrupt flag - io_rw_32 riscv_softirq; - - _REG_(SIO_MTIME_CTRL_OFFSET) // SIO_MTIME_CTRL - // Control register for the RISC-V 64-bit Machine-mode timer - // 0x00000008 [3] DBGPAUSE_CORE1 (1) If 1, the timer pauses when core 1 is in the debug halt state - // 0x00000004 [2] DBGPAUSE_CORE0 (1) If 1, the timer pauses when core 0 is in the debug halt state - // 0x00000002 [1] FULLSPEED (0) If 1, increment the timer every cycle (i - // 0x00000001 [0] EN (1) Timer enable bit - io_rw_32 mtime_ctrl; - - uint32_t _pad3[2]; - - _REG_(SIO_MTIME_OFFSET) // SIO_MTIME - // Read/write access to the high half of RISC-V Machine-mode timer - // 0xffffffff [31:0] MTIME (0x00000000) - io_rw_32 mtime; - - _REG_(SIO_MTIMEH_OFFSET) // SIO_MTIMEH - // Read/write access to the high half of RISC-V Machine-mode timer - // 0xffffffff [31:0] MTIMEH (0x00000000) - io_rw_32 mtimeh; - - _REG_(SIO_MTIMECMP_OFFSET) // SIO_MTIMECMP - // Low half of RISC-V Machine-mode timer comparator - // 0xffffffff [31:0] MTIMECMP (0xffffffff) - io_rw_32 mtimecmp; - - _REG_(SIO_MTIMECMPH_OFFSET) // SIO_MTIMECMPH - // High half of RISC-V Machine-mode timer comparator - // 0xffffffff [31:0] MTIMECMPH (0xffffffff) - io_rw_32 mtimecmph; - - _REG_(SIO_TMDS_CTRL_OFFSET) // SIO_TMDS_CTRL - // Control register for TMDS encoder - // 0x10000000 [28] CLEAR_BALANCE (0) Clear the running DC balance state of the TMDS encoders - // 0x08000000 [27] PIX2_NOSHIFT (0) When encoding two pixels's worth of symbols in one cycle... - // 0x07000000 [26:24] PIX_SHIFT (0x0) Shift applied to the colour data register with each read... - // 0x00800000 [23] INTERLEAVE (0) Enable lane interleaving for reads of PEEK_SINGLE/POP_SINGLE - // 0x001c0000 [20:18] L2_NBITS (0x0) Number of valid colour MSBs for lane 2 (1-8 bits,... - // 0x00038000 [17:15] L1_NBITS (0x0) Number of valid colour MSBs for lane 1 (1-8 bits,... - // 0x00007000 [14:12] L0_NBITS (0x0) Number of valid colour MSBs for lane 0 (1-8 bits,... - // 0x00000f00 [11:8] L2_ROT (0x0) Right-rotate the 16 LSBs of the colour accumulator by... - // 0x000000f0 [7:4] L1_ROT (0x0) Right-rotate the 16 LSBs of the colour accumulator by... - // 0x0000000f [3:0] L0_ROT (0x0) Right-rotate the 16 LSBs of the colour accumulator by... - io_rw_32 tmds_ctrl; - - _REG_(SIO_TMDS_WDATA_OFFSET) // SIO_TMDS_WDATA - // Write-only access to the TMDS colour data register - // 0xffffffff [31:0] TMDS_WDATA (0x00000000) - io_wo_32 tmds_wdata; - - _REG_(SIO_TMDS_PEEK_SINGLE_OFFSET) // SIO_TMDS_PEEK_SINGLE - // Get the encoding of one pixel's worth of colour data, packed into a 32-bit value (3x10-bit symbols) - // 0xffffffff [31:0] TMDS_PEEK_SINGLE (0x00000000) - io_ro_32 tmds_peek_single; - - _REG_(SIO_TMDS_POP_SINGLE_OFFSET) // SIO_TMDS_POP_SINGLE - // Get the encoding of one pixel's worth of colour data, packed into a 32-bit value - // 0xffffffff [31:0] TMDS_POP_SINGLE (0x00000000) - io_ro_32 tmds_pop_single; - - _REG_(SIO_TMDS_PEEK_DOUBLE_L0_OFFSET) // SIO_TMDS_PEEK_DOUBLE_L0 - // Get lane 0 of the encoding of two pixels' worth of colour data - // 0xffffffff [31:0] TMDS_PEEK_DOUBLE_L0 (0x00000000) - io_ro_32 tmds_peek_double_l0; - - _REG_(SIO_TMDS_POP_DOUBLE_L0_OFFSET) // SIO_TMDS_POP_DOUBLE_L0 - // Get lane 0 of the encoding of two pixels' worth of colour data - // 0xffffffff [31:0] TMDS_POP_DOUBLE_L0 (0x00000000) - io_ro_32 tmds_pop_double_l0; - - _REG_(SIO_TMDS_PEEK_DOUBLE_L1_OFFSET) // SIO_TMDS_PEEK_DOUBLE_L1 - // Get lane 1 of the encoding of two pixels' worth of colour data - // 0xffffffff [31:0] TMDS_PEEK_DOUBLE_L1 (0x00000000) - io_ro_32 tmds_peek_double_l1; - - _REG_(SIO_TMDS_POP_DOUBLE_L1_OFFSET) // SIO_TMDS_POP_DOUBLE_L1 - // Get lane 1 of the encoding of two pixels' worth of colour data - // 0xffffffff [31:0] TMDS_POP_DOUBLE_L1 (0x00000000) - io_ro_32 tmds_pop_double_l1; - - _REG_(SIO_TMDS_PEEK_DOUBLE_L2_OFFSET) // SIO_TMDS_PEEK_DOUBLE_L2 - // Get lane 2 of the encoding of two pixels' worth of colour data - // 0xffffffff [31:0] TMDS_PEEK_DOUBLE_L2 (0x00000000) - io_ro_32 tmds_peek_double_l2; - - _REG_(SIO_TMDS_POP_DOUBLE_L2_OFFSET) // SIO_TMDS_POP_DOUBLE_L2 - // Get lane 2 of the encoding of two pixels' worth of colour data - // 0xffffffff [31:0] TMDS_POP_DOUBLE_L2 (0x00000000) - io_ro_32 tmds_pop_double_l2; -} sio_hw_t; - -#define sio_hw ((sio_hw_t *)SIO_BASE) -#define sio_ns_hw ((sio_hw_t *)SIO_NONSEC_BASE) -static_assert(sizeof (sio_hw_t) == 0x01e8, ""); - -#endif // _HARDWARE_STRUCTS_SIO_H - diff --git a/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/spi.h b/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/spi.h deleted file mode 100644 index 454128ea26..0000000000 --- a/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/spi.h +++ /dev/null @@ -1,105 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _HARDWARE_STRUCTS_SPI_H -#define _HARDWARE_STRUCTS_SPI_H - -/** - * \file rp2350/spi.h - */ - -#include "hardware/address_mapped.h" -#include "hardware/regs/spi.h" - -// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_spi -// -// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) -// _REG_(x) will link to the corresponding register in hardware/regs/spi.h. -// -// Bit-field descriptions are of the form: -// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION - -typedef struct { - _REG_(SPI_SSPCR0_OFFSET) // SPI_SSPCR0 - // Control register 0, SSPCR0 on page 3-4 - // 0x0000ff00 [15:8] SCR (0x00) Serial clock rate - // 0x00000080 [7] SPH (0) SSPCLKOUT phase, applicable to Motorola SPI frame format only - // 0x00000040 [6] SPO (0) SSPCLKOUT polarity, applicable to Motorola SPI frame format only - // 0x00000030 [5:4] FRF (0x0) Frame format: 00 Motorola SPI frame format - // 0x0000000f [3:0] DSS (0x0) Data Size Select: 0000 Reserved, undefined operation - io_rw_32 cr0; - - _REG_(SPI_SSPCR1_OFFSET) // SPI_SSPCR1 - // Control register 1, SSPCR1 on page 3-5 - // 0x00000008 [3] SOD (0) Slave-mode output disable - // 0x00000004 [2] MS (0) Master or slave mode select - // 0x00000002 [1] SSE (0) Synchronous serial port enable: 0 SSP operation disabled - // 0x00000001 [0] LBM (0) Loop back mode: 0 Normal serial port operation enabled - io_rw_32 cr1; - - _REG_(SPI_SSPDR_OFFSET) // SPI_SSPDR - // Data register, SSPDR on page 3-6 - // 0x0000ffff [15:0] DATA (-) Transmit/Receive FIFO: Read Receive FIFO - io_rw_32 dr; - - _REG_(SPI_SSPSR_OFFSET) // SPI_SSPSR - // Status register, SSPSR on page 3-7 - // 0x00000010 [4] BSY (0) PrimeCell SSP busy flag, RO: 0 SSP is idle - // 0x00000008 [3] RFF (0) Receive FIFO full, RO: 0 Receive FIFO is not full - // 0x00000004 [2] RNE (0) Receive FIFO not empty, RO: 0 Receive FIFO is empty - // 0x00000002 [1] TNF (1) Transmit FIFO not full, RO: 0 Transmit FIFO is full - // 0x00000001 [0] TFE (1) Transmit FIFO empty, RO: 0 Transmit FIFO is not empty - io_ro_32 sr; - - _REG_(SPI_SSPCPSR_OFFSET) // SPI_SSPCPSR - // Clock prescale register, SSPCPSR on page 3-8 - // 0x000000ff [7:0] CPSDVSR (0x00) Clock prescale divisor - io_rw_32 cpsr; - - _REG_(SPI_SSPIMSC_OFFSET) // SPI_SSPIMSC - // Interrupt mask set or clear register, SSPIMSC on page 3-9 - // 0x00000008 [3] TXIM (0) Transmit FIFO interrupt mask: 0 Transmit FIFO half empty... - // 0x00000004 [2] RXIM (0) Receive FIFO interrupt mask: 0 Receive FIFO half full or... - // 0x00000002 [1] RTIM (0) Receive timeout interrupt mask: 0 Receive FIFO not empty... - // 0x00000001 [0] RORIM (0) Receive overrun interrupt mask: 0 Receive FIFO written... - io_rw_32 imsc; - - _REG_(SPI_SSPRIS_OFFSET) // SPI_SSPRIS - // Raw interrupt status register, SSPRIS on page 3-10 - // 0x00000008 [3] TXRIS (1) Gives the raw interrupt state, prior to masking, of the... - // 0x00000004 [2] RXRIS (0) Gives the raw interrupt state, prior to masking, of the... - // 0x00000002 [1] RTRIS (0) Gives the raw interrupt state, prior to masking, of the... - // 0x00000001 [0] RORRIS (0) Gives the raw interrupt state, prior to masking, of the... - io_ro_32 ris; - - _REG_(SPI_SSPMIS_OFFSET) // SPI_SSPMIS - // Masked interrupt status register, SSPMIS on page 3-11 - // 0x00000008 [3] TXMIS (0) Gives the transmit FIFO masked interrupt state, after... - // 0x00000004 [2] RXMIS (0) Gives the receive FIFO masked interrupt state, after... - // 0x00000002 [1] RTMIS (0) Gives the receive timeout masked interrupt state, after... - // 0x00000001 [0] RORMIS (0) Gives the receive over run masked interrupt status,... - io_ro_32 mis; - - _REG_(SPI_SSPICR_OFFSET) // SPI_SSPICR - // Interrupt clear register, SSPICR on page 3-11 - // 0x00000002 [1] RTIC (0) Clears the SSPRTINTR interrupt - // 0x00000001 [0] RORIC (0) Clears the SSPRORINTR interrupt - io_rw_32 icr; - - _REG_(SPI_SSPDMACR_OFFSET) // SPI_SSPDMACR - // DMA control register, SSPDMACR on page 3-12 - // 0x00000002 [1] TXDMAE (0) Transmit DMA Enable - // 0x00000001 [0] RXDMAE (0) Receive DMA Enable - io_rw_32 dmacr; -} spi_hw_t; - -#define spi0_hw ((spi_hw_t *)SPI0_BASE) -#define spi1_hw ((spi_hw_t *)SPI1_BASE) -static_assert(sizeof (spi_hw_t) == 0x0028, ""); - -#endif // _HARDWARE_STRUCTS_SPI_H - diff --git a/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/syscfg.h b/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/syscfg.h deleted file mode 100644 index 8909c0dbf9..0000000000 --- a/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/syscfg.h +++ /dev/null @@ -1,83 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _HARDWARE_STRUCTS_SYSCFG_H -#define _HARDWARE_STRUCTS_SYSCFG_H - -/** - * \file rp2350/syscfg.h - */ - -#include "hardware/address_mapped.h" -#include "hardware/regs/syscfg.h" - -// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_syscfg -// -// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) -// _REG_(x) will link to the corresponding register in hardware/regs/syscfg.h. -// -// Bit-field descriptions are of the form: -// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION - -typedef struct { - _REG_(SYSCFG_PROC_CONFIG_OFFSET) // SYSCFG_PROC_CONFIG - // Configuration for processors - // 0x00000002 [1] PROC1_HALTED (0) Indication that proc1 has halted - // 0x00000001 [0] PROC0_HALTED (0) Indication that proc0 has halted - io_ro_32 proc_config; - - _REG_(SYSCFG_PROC_IN_SYNC_BYPASS_OFFSET) // SYSCFG_PROC_IN_SYNC_BYPASS - // For each bit, if 1, bypass the input synchronizer between that GPIO + - // 0xffffffff [31:0] GPIO (0x00000000) - io_rw_32 proc_in_sync_bypass; - - _REG_(SYSCFG_PROC_IN_SYNC_BYPASS_HI_OFFSET) // SYSCFG_PROC_IN_SYNC_BYPASS_HI - // For each bit, if 1, bypass the input synchronizer between that GPIO + - // 0xf0000000 [31:28] QSPI_SD (0x0) - // 0x08000000 [27] QSPI_CSN (0) - // 0x04000000 [26] QSPI_SCK (0) - // 0x02000000 [25] USB_DM (0) - // 0x01000000 [24] USB_DP (0) - // 0x0000ffff [15:0] GPIO (0x0000) - io_rw_32 proc_in_sync_bypass_hi; - - _REG_(SYSCFG_DBGFORCE_OFFSET) // SYSCFG_DBGFORCE - // Directly control the chip SWD debug port - // 0x00000008 [3] ATTACH (0) Attach chip debug port to syscfg controls, and... - // 0x00000004 [2] SWCLK (1) Directly drive SWCLK, if ATTACH is set - // 0x00000002 [1] SWDI (1) Directly drive SWDIO input, if ATTACH is set - // 0x00000001 [0] SWDO (-) Observe the value of SWDIO output - io_rw_32 dbgforce; - - _REG_(SYSCFG_MEMPOWERDOWN_OFFSET) // SYSCFG_MEMPOWERDOWN - // Control PD pins to memories - // 0x00001000 [12] BOOTRAM (0) - // 0x00000800 [11] ROM (0) - // 0x00000400 [10] USB (0) - // 0x00000200 [9] SRAM9 (0) - // 0x00000100 [8] SRAM8 (0) - // 0x00000080 [7] SRAM7 (0) - // 0x00000040 [6] SRAM6 (0) - // 0x00000020 [5] SRAM5 (0) - // 0x00000010 [4] SRAM4 (0) - // 0x00000008 [3] SRAM3 (0) - // 0x00000004 [2] SRAM2 (0) - // 0x00000002 [1] SRAM1 (0) - // 0x00000001 [0] SRAM0 (0) - io_rw_32 mempowerdown; - - _REG_(SYSCFG_AUXCTRL_OFFSET) // SYSCFG_AUXCTRL - // Auxiliary system control register - // 0x000000ff [7:0] AUXCTRL (0x00) * Bits 7:2: Reserved - io_rw_32 auxctrl; -} syscfg_hw_t; - -#define syscfg_hw ((syscfg_hw_t *)SYSCFG_BASE) -static_assert(sizeof (syscfg_hw_t) == 0x0018, ""); - -#endif // _HARDWARE_STRUCTS_SYSCFG_H - diff --git a/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/sysinfo.h b/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/sysinfo.h deleted file mode 100644 index 688b577e4d..0000000000 --- a/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/sysinfo.h +++ /dev/null @@ -1,60 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _HARDWARE_STRUCTS_SYSINFO_H -#define _HARDWARE_STRUCTS_SYSINFO_H - -/** - * \file rp2350/sysinfo.h - */ - -#include "hardware/address_mapped.h" -#include "hardware/regs/sysinfo.h" - -// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_sysinfo -// -// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) -// _REG_(x) will link to the corresponding register in hardware/regs/sysinfo.h. -// -// Bit-field descriptions are of the form: -// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION - -typedef struct { - _REG_(SYSINFO_CHIP_ID_OFFSET) // SYSINFO_CHIP_ID - // JEDEC JEP-106 compliant chip identifier - // 0xf0000000 [31:28] REVISION (-) - // 0x0ffff000 [27:12] PART (-) - // 0x00000ffe [11:1] MANUFACTURER (-) - // 0x00000001 [0] STOP_BIT (1) - io_ro_32 chip_id; - - _REG_(SYSINFO_PACKAGE_SEL_OFFSET) // SYSINFO_PACKAGE_SEL - // 0x00000001 [0] PACKAGE_SEL (0) - io_ro_32 package_sel; - - _REG_(SYSINFO_PLATFORM_OFFSET) // SYSINFO_PLATFORM - // Platform register - // 0x00000010 [4] GATESIM (-) - // 0x00000008 [3] BATCHSIM (-) - // 0x00000004 [2] HDLSIM (-) - // 0x00000002 [1] ASIC (-) - // 0x00000001 [0] FPGA (-) - io_ro_32 platform; - - uint32_t _pad0[2]; - - _REG_(SYSINFO_GITREF_RP2350_OFFSET) // SYSINFO_GITREF_RP2350 - // Git hash of the chip source - // 0xffffffff [31:0] GITREF_RP2350 (-) - io_ro_32 gitref_rp2350; -} sysinfo_hw_t; - -#define sysinfo_hw ((sysinfo_hw_t *)SYSINFO_BASE) -static_assert(sizeof (sysinfo_hw_t) == 0x0018, ""); - -#endif // _HARDWARE_STRUCTS_SYSINFO_H - diff --git a/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/systick.h b/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/systick.h deleted file mode 100644 index f6024b1e93..0000000000 --- a/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/systick.h +++ /dev/null @@ -1,62 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _HARDWARE_STRUCTS_SYSTICK_H -#define _HARDWARE_STRUCTS_SYSTICK_H - -/** - * \file rp2350/systick.h - */ - -#include "hardware/address_mapped.h" -#include "hardware/regs/m33.h" - -// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_m33 -// -// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) -// _REG_(x) will link to the corresponding register in hardware/regs/m33.h. -// -// Bit-field descriptions are of the form: -// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION - -#if defined(__riscv) && PICO_FORBID_ARM_HEADERS_ON_RISCV -#error "Arm header included in a RISC-V build with PICO_FORBID_ARM_HEADERS_ON_RISCV=1" -#endif - -typedef struct { - _REG_(M33_SYST_CSR_OFFSET) // M33_SYST_CSR - // SysTick Control and Status Register - // 0x00010000 [16] COUNTFLAG (0) Returns 1 if timer counted to 0 since last time this was read - // 0x00000004 [2] CLKSOURCE (0) SysTick clock source - // 0x00000002 [1] TICKINT (0) Enables SysTick exception request: + - // 0x00000001 [0] ENABLE (0) Enable SysTick counter: + - io_rw_32 csr; - - _REG_(M33_SYST_RVR_OFFSET) // M33_SYST_RVR - // SysTick Reload Value Register - // 0x00ffffff [23:0] RELOAD (0x000000) Value to load into the SysTick Current Value Register... - io_rw_32 rvr; - - _REG_(M33_SYST_CVR_OFFSET) // M33_SYST_CVR - // SysTick Current Value Register - // 0x00ffffff [23:0] CURRENT (0x000000) Reads return the current value of the SysTick counter - io_rw_32 cvr; - - _REG_(M33_SYST_CALIB_OFFSET) // M33_SYST_CALIB - // SysTick Calibration Value Register - // 0x80000000 [31] NOREF (0) If reads as 1, the Reference clock is not provided - the... - // 0x40000000 [30] SKEW (0) If reads as 1, the calibration value for 10ms is inexact... - // 0x00ffffff [23:0] TENMS (0x000000) An optional Reload value to be used for 10ms (100Hz)... - io_ro_32 calib; -} systick_hw_t; - -#define systick_hw ((systick_hw_t *)(PPB_BASE + M33_SYST_CSR_OFFSET)) -#define systick_ns_hw ((systick_hw_t *)(PPB_NONSEC_BASE + M33_SYST_CSR_OFFSET)) -static_assert(sizeof (systick_hw_t) == 0x0010, ""); - -#endif // _HARDWARE_STRUCTS_SYSTICK_H - diff --git a/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/tbman.h b/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/tbman.h deleted file mode 100644 index 58d80dd86e..0000000000 --- a/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/tbman.h +++ /dev/null @@ -1,39 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _HARDWARE_STRUCTS_TBMAN_H -#define _HARDWARE_STRUCTS_TBMAN_H - -/** - * \file rp2350/tbman.h - */ - -#include "hardware/address_mapped.h" -#include "hardware/regs/tbman.h" - -// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_tbman -// -// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) -// _REG_(x) will link to the corresponding register in hardware/regs/tbman.h. -// -// Bit-field descriptions are of the form: -// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION - -typedef struct { - _REG_(TBMAN_PLATFORM_OFFSET) // TBMAN_PLATFORM - // Indicates the type of platform in use - // 0x00000004 [2] HDLSIM (0) Indicates the platform is a simulation - // 0x00000002 [1] FPGA (0) Indicates the platform is an FPGA - // 0x00000001 [0] ASIC (1) Indicates the platform is an ASIC - io_ro_32 platform; -} tbman_hw_t; - -#define tbman_hw ((tbman_hw_t *)TBMAN_BASE) -static_assert(sizeof (tbman_hw_t) == 0x0004, ""); - -#endif // _HARDWARE_STRUCTS_TBMAN_H - diff --git a/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/ticks.h b/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/ticks.h deleted file mode 100644 index b436484a3b..0000000000 --- a/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/ticks.h +++ /dev/null @@ -1,63 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _HARDWARE_STRUCTS_TICKS_H -#define _HARDWARE_STRUCTS_TICKS_H - -/** - * \file rp2350/ticks.h - */ - -#include "hardware/address_mapped.h" -#include "hardware/regs/ticks.h" - -// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_ticks -// -// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) -// _REG_(x) will link to the corresponding register in hardware/regs/ticks.h. -// -// Bit-field descriptions are of the form: -// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION - -/*! \brief Tick generator numbers on RP2350 (used as typedef \ref tick_gen_num_t) - * \ingroup hardware_ticks - */ -typedef enum tick_gen_num_rp2350 { - TICK_PROC0 = 0, - TICK_PROC1 = 1, - TICK_TIMER0 = 2, - TICK_TIMER1 = 3, - TICK_WATCHDOG = 4, - TICK_RISCV = 5, - TICK_COUNT -} tick_gen_num_t; - -typedef struct { - _REG_(TICKS_PROC0_CTRL_OFFSET) // TICKS_PROC0_CTRL - // Controls the tick generator - // 0x00000002 [1] RUNNING (-) Is the tick generator running? - // 0x00000001 [0] ENABLE (0) start / stop tick generation - io_rw_32 ctrl; - - _REG_(TICKS_PROC0_CYCLES_OFFSET) // TICKS_PROC0_CYCLES - // 0x000001ff [8:0] PROC0_CYCLES (0x000) Total number of clk_tick cycles before the next tick - io_rw_32 cycles; - - _REG_(TICKS_PROC0_COUNT_OFFSET) // TICKS_PROC0_COUNT - // 0x000001ff [8:0] PROC0_COUNT (-) Count down timer: the remaining number clk_tick cycles... - io_ro_32 count; -} ticks_slice_hw_t; - -typedef struct { - ticks_slice_hw_t ticks[6]; -} ticks_hw_t; - -#define ticks_hw ((ticks_hw_t *)TICKS_BASE) -static_assert(sizeof (ticks_hw_t) == 0x0048, ""); - -#endif // _HARDWARE_STRUCTS_TICKS_H - diff --git a/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/timer.h b/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/timer.h deleted file mode 100644 index 978dd56881..0000000000 --- a/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/timer.h +++ /dev/null @@ -1,127 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _HARDWARE_STRUCTS_TIMER_H -#define _HARDWARE_STRUCTS_TIMER_H - -/** - * \file rp2350/timer.h - */ - -#include "hardware/address_mapped.h" -#include "hardware/regs/timer.h" - -// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_timer -// -// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) -// _REG_(x) will link to the corresponding register in hardware/regs/timer.h. -// -// Bit-field descriptions are of the form: -// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION - -typedef struct { - _REG_(TIMER_TIMEHW_OFFSET) // TIMER_TIMEHW - // Write to bits 63:32 of time always write timelw before timehw - // 0xffffffff [31:0] TIMEHW (0x00000000) - io_wo_32 timehw; - - _REG_(TIMER_TIMELW_OFFSET) // TIMER_TIMELW - // Write to bits 31:0 of time writes do not get copied to time until timehw is written - // 0xffffffff [31:0] TIMELW (0x00000000) - io_wo_32 timelw; - - _REG_(TIMER_TIMEHR_OFFSET) // TIMER_TIMEHR - // Read from bits 63:32 of time always read timelr before timehr - // 0xffffffff [31:0] TIMEHR (0x00000000) - io_ro_32 timehr; - - _REG_(TIMER_TIMELR_OFFSET) // TIMER_TIMELR - // Read from bits 31:0 of time - // 0xffffffff [31:0] TIMELR (0x00000000) - io_ro_32 timelr; - - // (Description copied from array index 0 register TIMER_ALARM0 applies similarly to other array indexes) - _REG_(TIMER_ALARM0_OFFSET) // TIMER_ALARM0 - // Arm alarm 0, and configure the time it will fire - // 0xffffffff [31:0] ALARM0 (0x00000000) - io_rw_32 alarm[4]; - - _REG_(TIMER_ARMED_OFFSET) // TIMER_ARMED - // Indicates the armed/disarmed status of each alarm - // 0x0000000f [3:0] ARMED (0x0) - io_rw_32 armed; - - _REG_(TIMER_TIMERAWH_OFFSET) // TIMER_TIMERAWH - // Raw read from bits 63:32 of time (no side effects) - // 0xffffffff [31:0] TIMERAWH (0x00000000) - io_ro_32 timerawh; - - _REG_(TIMER_TIMERAWL_OFFSET) // TIMER_TIMERAWL - // Raw read from bits 31:0 of time (no side effects) - // 0xffffffff [31:0] TIMERAWL (0x00000000) - io_ro_32 timerawl; - - _REG_(TIMER_DBGPAUSE_OFFSET) // TIMER_DBGPAUSE - // Set bits high to enable pause when the corresponding debug ports are active - // 0x00000004 [2] DBG1 (1) Pause when processor 1 is in debug mode - // 0x00000002 [1] DBG0 (1) Pause when processor 0 is in debug mode - io_rw_32 dbgpause; - - _REG_(TIMER_PAUSE_OFFSET) // TIMER_PAUSE - // Set high to pause the timer - // 0x00000001 [0] PAUSE (0) - io_rw_32 pause; - - _REG_(TIMER_LOCKED_OFFSET) // TIMER_LOCKED - // Set locked bit to disable write access to timer Once set, cannot be cleared (without a reset) - // 0x00000001 [0] LOCKED (0) - io_rw_32 locked; - - _REG_(TIMER_SOURCE_OFFSET) // TIMER_SOURCE - // Selects the source for the timer - // 0x00000001 [0] CLK_SYS (0) - io_rw_32 source; - - _REG_(TIMER_INTR_OFFSET) // TIMER_INTR - // Raw Interrupts - // 0x00000008 [3] ALARM_3 (0) - // 0x00000004 [2] ALARM_2 (0) - // 0x00000002 [1] ALARM_1 (0) - // 0x00000001 [0] ALARM_0 (0) - io_rw_32 intr; - - _REG_(TIMER_INTE_OFFSET) // TIMER_INTE - // Interrupt Enable - // 0x00000008 [3] ALARM_3 (0) - // 0x00000004 [2] ALARM_2 (0) - // 0x00000002 [1] ALARM_1 (0) - // 0x00000001 [0] ALARM_0 (0) - io_rw_32 inte; - - _REG_(TIMER_INTF_OFFSET) // TIMER_INTF - // Interrupt Force - // 0x00000008 [3] ALARM_3 (0) - // 0x00000004 [2] ALARM_2 (0) - // 0x00000002 [1] ALARM_1 (0) - // 0x00000001 [0] ALARM_0 (0) - io_rw_32 intf; - - _REG_(TIMER_INTS_OFFSET) // TIMER_INTS - // Interrupt status after masking & forcing - // 0x00000008 [3] ALARM_3 (0) - // 0x00000004 [2] ALARM_2 (0) - // 0x00000002 [1] ALARM_1 (0) - // 0x00000001 [0] ALARM_0 (0) - io_ro_32 ints; -} timer_hw_t; - -#define timer0_hw ((timer_hw_t *)TIMER0_BASE) -#define timer1_hw ((timer_hw_t *)TIMER1_BASE) -static_assert(sizeof (timer_hw_t) == 0x004c, ""); - -#endif // _HARDWARE_STRUCTS_TIMER_H - diff --git a/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/tmds_encode.h b/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/tmds_encode.h deleted file mode 100644 index c1213af198..0000000000 --- a/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/tmds_encode.h +++ /dev/null @@ -1,92 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _HARDWARE_STRUCTS_TMDS_ENCODE_H -#define _HARDWARE_STRUCTS_TMDS_ENCODE_H - -/** - * \file rp2350/tmds_encode.h - */ - -#include "hardware/address_mapped.h" -#include "hardware/regs/sio.h" - -// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_sio -// -// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) -// _REG_(x) will link to the corresponding register in hardware/regs/sio.h. -// -// Bit-field descriptions are of the form: -// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION - -typedef struct { - _REG_(SIO_TMDS_CTRL_OFFSET) // SIO_TMDS_CTRL - // Control register for TMDS encoder - // 0x10000000 [28] CLEAR_BALANCE (0) Clear the running DC balance state of the TMDS encoders - // 0x08000000 [27] PIX2_NOSHIFT (0) When encoding two pixels's worth of symbols in one cycle... - // 0x07000000 [26:24] PIX_SHIFT (0x0) Shift applied to the colour data register with each read... - // 0x00800000 [23] INTERLEAVE (0) Enable lane interleaving for reads of PEEK_SINGLE/POP_SINGLE - // 0x001c0000 [20:18] L2_NBITS (0x0) Number of valid colour MSBs for lane 2 (1-8 bits,... - // 0x00038000 [17:15] L1_NBITS (0x0) Number of valid colour MSBs for lane 1 (1-8 bits,... - // 0x00007000 [14:12] L0_NBITS (0x0) Number of valid colour MSBs for lane 0 (1-8 bits,... - // 0x00000f00 [11:8] L2_ROT (0x0) Right-rotate the 16 LSBs of the colour accumulator by... - // 0x000000f0 [7:4] L1_ROT (0x0) Right-rotate the 16 LSBs of the colour accumulator by... - // 0x0000000f [3:0] L0_ROT (0x0) Right-rotate the 16 LSBs of the colour accumulator by... - io_rw_32 tmds_ctrl; - - _REG_(SIO_TMDS_WDATA_OFFSET) // SIO_TMDS_WDATA - // Write-only access to the TMDS colour data register - // 0xffffffff [31:0] TMDS_WDATA (0x00000000) - io_wo_32 tmds_wdata; - - _REG_(SIO_TMDS_PEEK_SINGLE_OFFSET) // SIO_TMDS_PEEK_SINGLE - // Get the encoding of one pixel's worth of colour data, packed into a 32-bit value (3x10-bit symbols) - // 0xffffffff [31:0] TMDS_PEEK_SINGLE (0x00000000) - io_ro_32 tmds_peek_single; - - _REG_(SIO_TMDS_POP_SINGLE_OFFSET) // SIO_TMDS_POP_SINGLE - // Get the encoding of one pixel's worth of colour data, packed into a 32-bit value - // 0xffffffff [31:0] TMDS_POP_SINGLE (0x00000000) - io_ro_32 tmds_pop_single; - - _REG_(SIO_TMDS_PEEK_DOUBLE_L0_OFFSET) // SIO_TMDS_PEEK_DOUBLE_L0 - // Get lane 0 of the encoding of two pixels' worth of colour data - // 0xffffffff [31:0] TMDS_PEEK_DOUBLE_L0 (0x00000000) - io_ro_32 tmds_peek_double_l0; - - _REG_(SIO_TMDS_POP_DOUBLE_L0_OFFSET) // SIO_TMDS_POP_DOUBLE_L0 - // Get lane 0 of the encoding of two pixels' worth of colour data - // 0xffffffff [31:0] TMDS_POP_DOUBLE_L0 (0x00000000) - io_ro_32 tmds_pop_double_l0; - - _REG_(SIO_TMDS_PEEK_DOUBLE_L1_OFFSET) // SIO_TMDS_PEEK_DOUBLE_L1 - // Get lane 1 of the encoding of two pixels' worth of colour data - // 0xffffffff [31:0] TMDS_PEEK_DOUBLE_L1 (0x00000000) - io_ro_32 tmds_peek_double_l1; - - _REG_(SIO_TMDS_POP_DOUBLE_L1_OFFSET) // SIO_TMDS_POP_DOUBLE_L1 - // Get lane 1 of the encoding of two pixels' worth of colour data - // 0xffffffff [31:0] TMDS_POP_DOUBLE_L1 (0x00000000) - io_ro_32 tmds_pop_double_l1; - - _REG_(SIO_TMDS_PEEK_DOUBLE_L2_OFFSET) // SIO_TMDS_PEEK_DOUBLE_L2 - // Get lane 2 of the encoding of two pixels' worth of colour data - // 0xffffffff [31:0] TMDS_PEEK_DOUBLE_L2 (0x00000000) - io_ro_32 tmds_peek_double_l2; - - _REG_(SIO_TMDS_POP_DOUBLE_L2_OFFSET) // SIO_TMDS_POP_DOUBLE_L2 - // Get lane 2 of the encoding of two pixels' worth of colour data - // 0xffffffff [31:0] TMDS_POP_DOUBLE_L2 (0x00000000) - io_ro_32 tmds_pop_double_l2; -} tmds_encode_hw_t; - -#define tmds_encode_hw ((tmds_encode_hw_t *)(SIO_BASE + SIO_TMDS_CTRL_OFFSET)) -#define tmds_encode_ns_hw ((tmds_encode_hw_t *)(SIO_NONSEC_BASE + SIO_TMDS_CTRL_OFFSET)) -static_assert(sizeof (tmds_encode_hw_t) == 0x0028, ""); - -#endif // _HARDWARE_STRUCTS_TMDS_ENCODE_H - diff --git a/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/trng.h b/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/trng.h deleted file mode 100644 index 5ae592961a..0000000000 --- a/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/trng.h +++ /dev/null @@ -1,153 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _HARDWARE_STRUCTS_TRNG_H -#define _HARDWARE_STRUCTS_TRNG_H - -/** - * \file rp2350/trng.h - */ - -#include "hardware/address_mapped.h" -#include "hardware/regs/trng.h" - -// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_trng -// -// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) -// _REG_(x) will link to the corresponding register in hardware/regs/trng.h. -// -// Bit-field descriptions are of the form: -// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION - -typedef struct { - _REG_(TRNG_RNG_IMR_OFFSET) // TRNG_RNG_IMR - // Interrupt masking - // 0xfffffff0 [31:4] RESERVED (0x0000000) RESERVED - // 0x00000008 [3] VN_ERR_INT_MASK (1) 1'b1-mask interrupt, no interrupt will be generated - // 0x00000004 [2] CRNGT_ERR_INT_MASK (1) 1'b1-mask interrupt, no interrupt will be generated - // 0x00000002 [1] AUTOCORR_ERR_INT_MASK (1) 1'b1-mask interrupt, no interrupt will be generated - // 0x00000001 [0] EHR_VALID_INT_MASK (1) 1'b1-mask interrupt, no interrupt will be generated - io_rw_32 rng_imr; - - _REG_(TRNG_RNG_ISR_OFFSET) // TRNG_RNG_ISR - // RNG status register - // 0xfffffff0 [31:4] RESERVED (0x0000000) RESERVED - // 0x00000008 [3] VN_ERR (0) 1'b1 indicates Von Neuman error - // 0x00000004 [2] CRNGT_ERR (0) 1'b1 indicates CRNGT in the RNG test failed - // 0x00000002 [1] AUTOCORR_ERR (0) 1'b1 indicates Autocorrelation test failed four times in a row - // 0x00000001 [0] EHR_VALID (0) 1'b1 indicates that 192 bits have been collected in the... - io_ro_32 rng_isr; - - _REG_(TRNG_RNG_ICR_OFFSET) // TRNG_RNG_ICR - // Interrupt/status bit clear Register - // 0xfffffff0 [31:4] RESERVED (0x0000000) RESERVED - // 0x00000008 [3] VN_ERR (0) Write 1'b1 - clear corresponding bit in RNG_ISR - // 0x00000004 [2] CRNGT_ERR (0) Write 1'b1 - clear corresponding bit in RNG_ISR - // 0x00000002 [1] AUTOCORR_ERR (0) Cannot be cleared by SW! Only RNG reset clears this bit - // 0x00000001 [0] EHR_VALID (0) Write 1'b1 - clear corresponding bit in RNG_ISR - io_rw_32 rng_icr; - - _REG_(TRNG_TRNG_CONFIG_OFFSET) // TRNG_TRNG_CONFIG - // Selecting the inverter-chain length - // 0xfffffffc [31:2] RESERVED (0x00000000) RESERVED - // 0x00000003 [1:0] RND_SRC_SEL (0x0) Selects the number of inverters (out of four possible... - io_rw_32 trng_config; - - _REG_(TRNG_TRNG_VALID_OFFSET) // TRNG_TRNG_VALID - // 192 bit collection indication - // 0xfffffffe [31:1] RESERVED (0x00000000) RESERVED - // 0x00000001 [0] EHR_VALID (0) 1'b1 indicates that collection of bits in the RNG is... - io_ro_32 trng_valid; - - // (Description copied from array index 0 register TRNG_EHR_DATA0 applies similarly to other array indexes) - _REG_(TRNG_EHR_DATA0_OFFSET) // TRNG_EHR_DATA0 - // RNG collected bits - // 0xffffffff [31:0] EHR_DATA0 (0x00000000) Bits [31:0] of Entropy Holding Register (EHR) - RNG... - io_ro_32 ehr_data[6]; - - _REG_(TRNG_RND_SOURCE_ENABLE_OFFSET) // TRNG_RND_SOURCE_ENABLE - // Enable signal for the random source - // 0xfffffffe [31:1] RESERVED (0x00000000) RESERVED - // 0x00000001 [0] RND_SRC_EN (0) * 1'b1 - entropy source is enabled - io_rw_32 rnd_source_enable; - - _REG_(TRNG_SAMPLE_CNT1_OFFSET) // TRNG_SAMPLE_CNT1 - // Counts clocks between sampling of random bit - // 0xffffffff [31:0] SAMPLE_CNTR1 (0x0000ffff) Sets the number of rng_clk cycles between two... - io_rw_32 sample_cnt1; - - _REG_(TRNG_AUTOCORR_STATISTIC_OFFSET) // TRNG_AUTOCORR_STATISTIC - // Statistic about Autocorrelation test activations - // 0xffc00000 [31:22] RESERVED (0x000) RESERVED - // 0x003fc000 [21:14] AUTOCORR_FAILS (0x00) Count each time an autocorrelation test fails - // 0x00003fff [13:0] AUTOCORR_TRYS (0x0000) Count each time an autocorrelation test starts - io_rw_32 autocorr_statistic; - - _REG_(TRNG_TRNG_DEBUG_CONTROL_OFFSET) // TRNG_TRNG_DEBUG_CONTROL - // Debug register - // 0x00000008 [3] AUTO_CORRELATE_BYPASS (0) When set, the autocorrelation test in the TRNG module is bypassed - // 0x00000004 [2] TRNG_CRNGT_BYPASS (0) When set, the CRNGT test in the RNG is bypassed - // 0x00000002 [1] VNC_BYPASS (0) When set, the Von-Neuman balancer is bypassed (including... - // 0x00000001 [0] RESERVED (0) N/A - io_rw_32 trng_debug_control; - - uint32_t _pad0; - - _REG_(TRNG_TRNG_SW_RESET_OFFSET) // TRNG_TRNG_SW_RESET - // Generate internal SW reset within the RNG block - // 0xfffffffe [31:1] RESERVED (0x00000000) RESERVED - // 0x00000001 [0] TRNG_SW_RESET (0) Writing 1'b1 to this register causes an internal RNG reset - io_rw_32 trng_sw_reset; - - uint32_t _pad1[28]; - - _REG_(TRNG_RNG_DEBUG_EN_INPUT_OFFSET) // TRNG_RNG_DEBUG_EN_INPUT - // Enable the RNG debug mode - // 0xfffffffe [31:1] RESERVED (0x00000000) RESERVED - // 0x00000001 [0] RNG_DEBUG_EN (0) * 1'b1 - debug mode is enabled - io_rw_32 rng_debug_en_input; - - _REG_(TRNG_TRNG_BUSY_OFFSET) // TRNG_TRNG_BUSY - // RNG Busy indication - // 0xfffffffe [31:1] RESERVED (0x00000000) RESERVED - // 0x00000001 [0] TRNG_BUSY (0) Reflects rng_busy status - io_ro_32 trng_busy; - - _REG_(TRNG_RST_BITS_COUNTER_OFFSET) // TRNG_RST_BITS_COUNTER - // Reset the counter of collected bits in the RNG - // 0xfffffffe [31:1] RESERVED (0x00000000) RESERVED - // 0x00000001 [0] RST_BITS_COUNTER (0) Writing any value to this address will reset the bits... - io_rw_32 rst_bits_counter; - - _REG_(TRNG_RNG_VERSION_OFFSET) // TRNG_RNG_VERSION - // Displays the version settings of the TRNG - // 0xffffff00 [31:8] RESERVED (0x000000) RESERVED - // 0x00000080 [7] RNG_USE_5_SBOXES (0) * 1'b1 - 5 SBOX AES - // 0x00000040 [6] RESEEDING_EXISTS (0) * 1'b1 - Exists - // 0x00000020 [5] KAT_EXISTS (0) * 1'b1 - Exists - // 0x00000010 [4] PRNG_EXISTS (0) * 1'b1 - Exists - // 0x00000008 [3] TRNG_TESTS_BYPASS_EN (0) * 1'b1 - Exists - // 0x00000004 [2] AUTOCORR_EXISTS (0) * 1'b1 - Exists - // 0x00000002 [1] CRNGT_EXISTS (0) * 1'b1 - Exists - // 0x00000001 [0] EHR_WIDTH_192 (0) * 1'b1 - 192-bit EHR - io_ro_32 rng_version; - - uint32_t _pad2[7]; - - // (Description copied from array index 0 register TRNG_RNG_BIST_CNTR_0 applies similarly to other array indexes) - _REG_(TRNG_RNG_BIST_CNTR_0_OFFSET) // TRNG_RNG_BIST_CNTR_0 - // Collected BIST results - // 0xffc00000 [31:22] RESERVED (0x000) RESERVED - // 0x003fffff [21:0] ROSC_CNTR_VAL (0x000000) Reflects the results of RNG BIST counter - io_ro_32 rng_bist_cntr[3]; -} trng_hw_t; - -#define trng_hw ((trng_hw_t *)(TRNG_BASE + TRNG_RNG_IMR_OFFSET)) -static_assert(sizeof (trng_hw_t) == 0x00ec, ""); - -#endif // _HARDWARE_STRUCTS_TRNG_H - diff --git a/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/uart.h b/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/uart.h deleted file mode 100644 index 47ff324e37..0000000000 --- a/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/uart.h +++ /dev/null @@ -1,182 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _HARDWARE_STRUCTS_UART_H -#define _HARDWARE_STRUCTS_UART_H - -/** - * \file rp2350/uart.h - */ - -#include "hardware/address_mapped.h" -#include "hardware/regs/uart.h" - -// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_uart -// -// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) -// _REG_(x) will link to the corresponding register in hardware/regs/uart.h. -// -// Bit-field descriptions are of the form: -// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION - -typedef struct { - _REG_(UART_UARTDR_OFFSET) // UART_UARTDR - // Data Register, UARTDR - // 0x00000800 [11] OE (-) Overrun error - // 0x00000400 [10] BE (-) Break error - // 0x00000200 [9] PE (-) Parity error - // 0x00000100 [8] FE (-) Framing error - // 0x000000ff [7:0] DATA (-) Receive (read) data character - io_rw_32 dr; - - _REG_(UART_UARTRSR_OFFSET) // UART_UARTRSR - // Receive Status Register/Error Clear Register, UARTRSR/UARTECR - // 0x00000008 [3] OE (0) Overrun error - // 0x00000004 [2] BE (0) Break error - // 0x00000002 [1] PE (0) Parity error - // 0x00000001 [0] FE (0) Framing error - io_rw_32 rsr; - - uint32_t _pad0[4]; - - _REG_(UART_UARTFR_OFFSET) // UART_UARTFR - // Flag Register, UARTFR - // 0x00000100 [8] RI (-) Ring indicator - // 0x00000080 [7] TXFE (1) Transmit FIFO empty - // 0x00000040 [6] RXFF (0) Receive FIFO full - // 0x00000020 [5] TXFF (0) Transmit FIFO full - // 0x00000010 [4] RXFE (1) Receive FIFO empty - // 0x00000008 [3] BUSY (0) UART busy - // 0x00000004 [2] DCD (-) Data carrier detect - // 0x00000002 [1] DSR (-) Data set ready - // 0x00000001 [0] CTS (-) Clear to send - io_ro_32 fr; - - uint32_t _pad1; - - _REG_(UART_UARTILPR_OFFSET) // UART_UARTILPR - // IrDA Low-Power Counter Register, UARTILPR - // 0x000000ff [7:0] ILPDVSR (0x00) 8-bit low-power divisor value - io_rw_32 ilpr; - - _REG_(UART_UARTIBRD_OFFSET) // UART_UARTIBRD - // Integer Baud Rate Register, UARTIBRD - // 0x0000ffff [15:0] BAUD_DIVINT (0x0000) The integer baud rate divisor - io_rw_32 ibrd; - - _REG_(UART_UARTFBRD_OFFSET) // UART_UARTFBRD - // Fractional Baud Rate Register, UARTFBRD - // 0x0000003f [5:0] BAUD_DIVFRAC (0x00) The fractional baud rate divisor - io_rw_32 fbrd; - - _REG_(UART_UARTLCR_H_OFFSET) // UART_UARTLCR_H - // Line Control Register, UARTLCR_H - // 0x00000080 [7] SPS (0) Stick parity select - // 0x00000060 [6:5] WLEN (0x0) Word length - // 0x00000010 [4] FEN (0) Enable FIFOs: 0 = FIFOs are disabled (character mode)... - // 0x00000008 [3] STP2 (0) Two stop bits select - // 0x00000004 [2] EPS (0) Even parity select - // 0x00000002 [1] PEN (0) Parity enable: 0 = parity is disabled and no parity bit... - // 0x00000001 [0] BRK (0) Send break - io_rw_32 lcr_h; - - _REG_(UART_UARTCR_OFFSET) // UART_UARTCR - // Control Register, UARTCR - // 0x00008000 [15] CTSEN (0) CTS hardware flow control enable - // 0x00004000 [14] RTSEN (0) RTS hardware flow control enable - // 0x00002000 [13] OUT2 (0) This bit is the complement of the UART Out2 (nUARTOut2)... - // 0x00001000 [12] OUT1 (0) This bit is the complement of the UART Out1 (nUARTOut1)... - // 0x00000800 [11] RTS (0) Request to send - // 0x00000400 [10] DTR (0) Data transmit ready - // 0x00000200 [9] RXE (1) Receive enable - // 0x00000100 [8] TXE (1) Transmit enable - // 0x00000080 [7] LBE (0) Loopback enable - // 0x00000004 [2] SIRLP (0) SIR low-power IrDA mode - // 0x00000002 [1] SIREN (0) SIR enable: 0 = IrDA SIR ENDEC is disabled - // 0x00000001 [0] UARTEN (0) UART enable: 0 = UART is disabled - io_rw_32 cr; - - _REG_(UART_UARTIFLS_OFFSET) // UART_UARTIFLS - // Interrupt FIFO Level Select Register, UARTIFLS - // 0x00000038 [5:3] RXIFLSEL (0x2) Receive interrupt FIFO level select - // 0x00000007 [2:0] TXIFLSEL (0x2) Transmit interrupt FIFO level select - io_rw_32 ifls; - - _REG_(UART_UARTIMSC_OFFSET) // UART_UARTIMSC - // Interrupt Mask Set/Clear Register, UARTIMSC - // 0x00000400 [10] OEIM (0) Overrun error interrupt mask - // 0x00000200 [9] BEIM (0) Break error interrupt mask - // 0x00000100 [8] PEIM (0) Parity error interrupt mask - // 0x00000080 [7] FEIM (0) Framing error interrupt mask - // 0x00000040 [6] RTIM (0) Receive timeout interrupt mask - // 0x00000020 [5] TXIM (0) Transmit interrupt mask - // 0x00000010 [4] RXIM (0) Receive interrupt mask - // 0x00000008 [3] DSRMIM (0) nUARTDSR modem interrupt mask - // 0x00000004 [2] DCDMIM (0) nUARTDCD modem interrupt mask - // 0x00000002 [1] CTSMIM (0) nUARTCTS modem interrupt mask - // 0x00000001 [0] RIMIM (0) nUARTRI modem interrupt mask - io_rw_32 imsc; - - _REG_(UART_UARTRIS_OFFSET) // UART_UARTRIS - // Raw Interrupt Status Register, UARTRIS - // 0x00000400 [10] OERIS (0) Overrun error interrupt status - // 0x00000200 [9] BERIS (0) Break error interrupt status - // 0x00000100 [8] PERIS (0) Parity error interrupt status - // 0x00000080 [7] FERIS (0) Framing error interrupt status - // 0x00000040 [6] RTRIS (0) Receive timeout interrupt status - // 0x00000020 [5] TXRIS (0) Transmit interrupt status - // 0x00000010 [4] RXRIS (0) Receive interrupt status - // 0x00000008 [3] DSRRMIS (-) nUARTDSR modem interrupt status - // 0x00000004 [2] DCDRMIS (-) nUARTDCD modem interrupt status - // 0x00000002 [1] CTSRMIS (-) nUARTCTS modem interrupt status - // 0x00000001 [0] RIRMIS (-) nUARTRI modem interrupt status - io_ro_32 ris; - - _REG_(UART_UARTMIS_OFFSET) // UART_UARTMIS - // Masked Interrupt Status Register, UARTMIS - // 0x00000400 [10] OEMIS (0) Overrun error masked interrupt status - // 0x00000200 [9] BEMIS (0) Break error masked interrupt status - // 0x00000100 [8] PEMIS (0) Parity error masked interrupt status - // 0x00000080 [7] FEMIS (0) Framing error masked interrupt status - // 0x00000040 [6] RTMIS (0) Receive timeout masked interrupt status - // 0x00000020 [5] TXMIS (0) Transmit masked interrupt status - // 0x00000010 [4] RXMIS (0) Receive masked interrupt status - // 0x00000008 [3] DSRMMIS (-) nUARTDSR modem masked interrupt status - // 0x00000004 [2] DCDMMIS (-) nUARTDCD modem masked interrupt status - // 0x00000002 [1] CTSMMIS (-) nUARTCTS modem masked interrupt status - // 0x00000001 [0] RIMMIS (-) nUARTRI modem masked interrupt status - io_ro_32 mis; - - _REG_(UART_UARTICR_OFFSET) // UART_UARTICR - // Interrupt Clear Register, UARTICR - // 0x00000400 [10] OEIC (-) Overrun error interrupt clear - // 0x00000200 [9] BEIC (-) Break error interrupt clear - // 0x00000100 [8] PEIC (-) Parity error interrupt clear - // 0x00000080 [7] FEIC (-) Framing error interrupt clear - // 0x00000040 [6] RTIC (-) Receive timeout interrupt clear - // 0x00000020 [5] TXIC (-) Transmit interrupt clear - // 0x00000010 [4] RXIC (-) Receive interrupt clear - // 0x00000008 [3] DSRMIC (-) nUARTDSR modem interrupt clear - // 0x00000004 [2] DCDMIC (-) nUARTDCD modem interrupt clear - // 0x00000002 [1] CTSMIC (-) nUARTCTS modem interrupt clear - // 0x00000001 [0] RIMIC (-) nUARTRI modem interrupt clear - io_rw_32 icr; - - _REG_(UART_UARTDMACR_OFFSET) // UART_UARTDMACR - // DMA Control Register, UARTDMACR - // 0x00000004 [2] DMAONERR (0) DMA on error - // 0x00000002 [1] TXDMAE (0) Transmit DMA enable - // 0x00000001 [0] RXDMAE (0) Receive DMA enable - io_rw_32 dmacr; -} uart_hw_t; - -#define uart0_hw ((uart_hw_t *)UART0_BASE) -#define uart1_hw ((uart_hw_t *)UART1_BASE) -static_assert(sizeof (uart_hw_t) == 0x004c, ""); - -#endif // _HARDWARE_STRUCTS_UART_H - diff --git a/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/usb.h b/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/usb.h deleted file mode 100644 index 1c6229bd34..0000000000 --- a/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/usb.h +++ /dev/null @@ -1,602 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _HARDWARE_STRUCTS_USB_H -#define _HARDWARE_STRUCTS_USB_H - -/** - * \file rp2350/usb.h - */ - -#include "hardware/address_mapped.h" -#include "hardware/regs/usb.h" -#include "hardware/structs/usb_dpram.h" - -// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_usb -// -// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) -// _REG_(x) will link to the corresponding register in hardware/regs/usb.h. -// -// Bit-field descriptions are of the form: -// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION - -typedef struct { - _REG_(USB_ADDR_ENDP_OFFSET) // USB_ADDR_ENDP - // Device address and endpoint control - // 0x000f0000 [19:16] ENDPOINT (0x0) Device endpoint to send data to - // 0x0000007f [6:0] ADDRESS (0x00) In device mode, the address that the device should respond to - io_rw_32 dev_addr_ctrl; - - // (Description copied from array index 0 register USB_ADDR_ENDP1 applies similarly to other array indexes) - _REG_(USB_ADDR_ENDP1_OFFSET) // USB_ADDR_ENDP1 - // Interrupt endpoint 1 - // 0x04000000 [26] INTEP_PREAMBLE (0) Interrupt EP requires preamble (is a low speed device on... - // 0x02000000 [25] INTEP_DIR (0) Direction of the interrupt endpoint - // 0x000f0000 [19:16] ENDPOINT (0x0) Endpoint number of the interrupt endpoint - // 0x0000007f [6:0] ADDRESS (0x00) Device address - io_rw_32 int_ep_addr_ctrl[15]; - - _REG_(USB_MAIN_CTRL_OFFSET) // USB_MAIN_CTRL - // Main control register - // 0x80000000 [31] SIM_TIMING (0) Reduced timings for simulation - // 0x00000004 [2] PHY_ISO (1) Isolates USB phy after controller power-up + - // 0x00000002 [1] HOST_NDEVICE (0) Device mode = 0, Host mode = 1 - // 0x00000001 [0] CONTROLLER_EN (0) Enable controller - io_rw_32 main_ctrl; - - _REG_(USB_SOF_WR_OFFSET) // USB_SOF_WR - // Set the SOF (Start of Frame) frame number in the host controller - // 0x000007ff [10:0] COUNT (0x000) - io_wo_32 sof_wr; - - _REG_(USB_SOF_RD_OFFSET) // USB_SOF_RD - // Read the last SOF (Start of Frame) frame number seen - // 0x000007ff [10:0] COUNT (0x000) - io_ro_32 sof_rd; - - _REG_(USB_SIE_CTRL_OFFSET) // USB_SIE_CTRL - // SIE control register - // 0x80000000 [31] EP0_INT_STALL (0) Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a STALL - // 0x40000000 [30] EP0_DOUBLE_BUF (0) Device: EP0 single buffered = 0, double buffered = 1 - // 0x20000000 [29] EP0_INT_1BUF (0) Device: Set bit in BUFF_STATUS for every buffer completed on EP0 - // 0x10000000 [28] EP0_INT_2BUF (0) Device: Set bit in BUFF_STATUS for every 2 buffers... - // 0x08000000 [27] EP0_INT_NAK (0) Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a NAK - // 0x04000000 [26] DIRECT_EN (0) Direct bus drive enable - // 0x02000000 [25] DIRECT_DP (0) Direct control of DP - // 0x01000000 [24] DIRECT_DM (0) Direct control of DM - // 0x00080000 [19] EP0_STOP_ON_SHORT_PACKET (0) Device: Stop EP0 on a short packet - // 0x00040000 [18] TRANSCEIVER_PD (0) Power down bus transceiver - // 0x00020000 [17] RPU_OPT (0) Device: Pull-up strength (0=1K2, 1=2k3) - // 0x00010000 [16] PULLUP_EN (0) Device: Enable pull up resistor - // 0x00008000 [15] PULLDOWN_EN (1) Host: Enable pull down resistors - // 0x00002000 [13] RESET_BUS (0) Host: Reset bus - // 0x00001000 [12] RESUME (0) Device: Remote wakeup - // 0x00000800 [11] VBUS_EN (0) Host: Enable VBUS - // 0x00000400 [10] KEEP_ALIVE_EN (0) Host: Enable keep alive packet (for low speed bus) - // 0x00000200 [9] SOF_EN (0) Host: Enable SOF generation (for full speed bus) - // 0x00000100 [8] SOF_SYNC (0) Host: Delay packet(s) until after SOF - // 0x00000040 [6] PREAMBLE_EN (0) Host: Preable enable for LS device on FS hub - // 0x00000010 [4] STOP_TRANS (0) Host: Stop transaction - // 0x00000008 [3] RECEIVE_DATA (0) Host: Receive transaction (IN to host) - // 0x00000004 [2] SEND_DATA (0) Host: Send transaction (OUT from host) - // 0x00000002 [1] SEND_SETUP (0) Host: Send Setup packet - // 0x00000001 [0] START_TRANS (0) Host: Start transaction - io_rw_32 sie_ctrl; - - _REG_(USB_SIE_STATUS_OFFSET) // USB_SIE_STATUS - // SIE status register - // 0x80000000 [31] DATA_SEQ_ERROR (0) Data Sequence Error - // 0x40000000 [30] ACK_REC (0) ACK received - // 0x20000000 [29] STALL_REC (0) Host: STALL received - // 0x10000000 [28] NAK_REC (0) Host: NAK received - // 0x08000000 [27] RX_TIMEOUT (0) RX timeout is raised by both the host and device if an... - // 0x04000000 [26] RX_OVERFLOW (0) RX overflow is raised by the Serial RX engine if the... - // 0x02000000 [25] BIT_STUFF_ERROR (0) Bit Stuff Error - // 0x01000000 [24] CRC_ERROR (0) CRC Error - // 0x00800000 [23] ENDPOINT_ERROR (0) An endpoint has encountered an error - // 0x00080000 [19] BUS_RESET (0) Device: bus reset received - // 0x00040000 [18] TRANS_COMPLETE (0) Transaction complete - // 0x00020000 [17] SETUP_REC (0) Device: Setup packet received - // 0x00010000 [16] CONNECTED (0) Device: connected - // 0x00001000 [12] RX_SHORT_PACKET (0) Device or Host has received a short packet - // 0x00000800 [11] RESUME (0) Host: Device has initiated a remote resume - // 0x00000400 [10] VBUS_OVER_CURR (0) VBUS over current detected - // 0x00000300 [9:8] SPEED (0x0) Host: device speed - // 0x00000010 [4] SUSPENDED (0) Bus in suspended state - // 0x0000000c [3:2] LINE_STATE (0x0) USB bus line state - // 0x00000001 [0] VBUS_DETECTED (0) Device: VBUS Detected - io_rw_32 sie_status; - - _REG_(USB_INT_EP_CTRL_OFFSET) // USB_INT_EP_CTRL - // interrupt endpoint control register - // 0x0000fffe [15:1] INT_EP_ACTIVE (0x0000) Host: Enable interrupt endpoint 1 -> 15 - io_rw_32 int_ep_ctrl; - - _REG_(USB_BUFF_STATUS_OFFSET) // USB_BUFF_STATUS - // Buffer status register - // 0x80000000 [31] EP15_OUT (0) - // 0x40000000 [30] EP15_IN (0) - // 0x20000000 [29] EP14_OUT (0) - // 0x10000000 [28] EP14_IN (0) - // 0x08000000 [27] EP13_OUT (0) - // 0x04000000 [26] EP13_IN (0) - // 0x02000000 [25] EP12_OUT (0) - // 0x01000000 [24] EP12_IN (0) - // 0x00800000 [23] EP11_OUT (0) - // 0x00400000 [22] EP11_IN (0) - // 0x00200000 [21] EP10_OUT (0) - // 0x00100000 [20] EP10_IN (0) - // 0x00080000 [19] EP9_OUT (0) - // 0x00040000 [18] EP9_IN (0) - // 0x00020000 [17] EP8_OUT (0) - // 0x00010000 [16] EP8_IN (0) - // 0x00008000 [15] EP7_OUT (0) - // 0x00004000 [14] EP7_IN (0) - // 0x00002000 [13] EP6_OUT (0) - // 0x00001000 [12] EP6_IN (0) - // 0x00000800 [11] EP5_OUT (0) - // 0x00000400 [10] EP5_IN (0) - // 0x00000200 [9] EP4_OUT (0) - // 0x00000100 [8] EP4_IN (0) - // 0x00000080 [7] EP3_OUT (0) - // 0x00000040 [6] EP3_IN (0) - // 0x00000020 [5] EP2_OUT (0) - // 0x00000010 [4] EP2_IN (0) - // 0x00000008 [3] EP1_OUT (0) - // 0x00000004 [2] EP1_IN (0) - // 0x00000002 [1] EP0_OUT (0) - // 0x00000001 [0] EP0_IN (0) - io_rw_32 buf_status; - - _REG_(USB_BUFF_CPU_SHOULD_HANDLE_OFFSET) // USB_BUFF_CPU_SHOULD_HANDLE - // Which of the double buffers should be handled - // 0x80000000 [31] EP15_OUT (0) - // 0x40000000 [30] EP15_IN (0) - // 0x20000000 [29] EP14_OUT (0) - // 0x10000000 [28] EP14_IN (0) - // 0x08000000 [27] EP13_OUT (0) - // 0x04000000 [26] EP13_IN (0) - // 0x02000000 [25] EP12_OUT (0) - // 0x01000000 [24] EP12_IN (0) - // 0x00800000 [23] EP11_OUT (0) - // 0x00400000 [22] EP11_IN (0) - // 0x00200000 [21] EP10_OUT (0) - // 0x00100000 [20] EP10_IN (0) - // 0x00080000 [19] EP9_OUT (0) - // 0x00040000 [18] EP9_IN (0) - // 0x00020000 [17] EP8_OUT (0) - // 0x00010000 [16] EP8_IN (0) - // 0x00008000 [15] EP7_OUT (0) - // 0x00004000 [14] EP7_IN (0) - // 0x00002000 [13] EP6_OUT (0) - // 0x00001000 [12] EP6_IN (0) - // 0x00000800 [11] EP5_OUT (0) - // 0x00000400 [10] EP5_IN (0) - // 0x00000200 [9] EP4_OUT (0) - // 0x00000100 [8] EP4_IN (0) - // 0x00000080 [7] EP3_OUT (0) - // 0x00000040 [6] EP3_IN (0) - // 0x00000020 [5] EP2_OUT (0) - // 0x00000010 [4] EP2_IN (0) - // 0x00000008 [3] EP1_OUT (0) - // 0x00000004 [2] EP1_IN (0) - // 0x00000002 [1] EP0_OUT (0) - // 0x00000001 [0] EP0_IN (0) - io_ro_32 buf_cpu_should_handle; - - _REG_(USB_EP_ABORT_OFFSET) // USB_EP_ABORT - // Device only: Can be set to ignore the buffer control register for this endpoint in case you... - // 0x80000000 [31] EP15_OUT (0) - // 0x40000000 [30] EP15_IN (0) - // 0x20000000 [29] EP14_OUT (0) - // 0x10000000 [28] EP14_IN (0) - // 0x08000000 [27] EP13_OUT (0) - // 0x04000000 [26] EP13_IN (0) - // 0x02000000 [25] EP12_OUT (0) - // 0x01000000 [24] EP12_IN (0) - // 0x00800000 [23] EP11_OUT (0) - // 0x00400000 [22] EP11_IN (0) - // 0x00200000 [21] EP10_OUT (0) - // 0x00100000 [20] EP10_IN (0) - // 0x00080000 [19] EP9_OUT (0) - // 0x00040000 [18] EP9_IN (0) - // 0x00020000 [17] EP8_OUT (0) - // 0x00010000 [16] EP8_IN (0) - // 0x00008000 [15] EP7_OUT (0) - // 0x00004000 [14] EP7_IN (0) - // 0x00002000 [13] EP6_OUT (0) - // 0x00001000 [12] EP6_IN (0) - // 0x00000800 [11] EP5_OUT (0) - // 0x00000400 [10] EP5_IN (0) - // 0x00000200 [9] EP4_OUT (0) - // 0x00000100 [8] EP4_IN (0) - // 0x00000080 [7] EP3_OUT (0) - // 0x00000040 [6] EP3_IN (0) - // 0x00000020 [5] EP2_OUT (0) - // 0x00000010 [4] EP2_IN (0) - // 0x00000008 [3] EP1_OUT (0) - // 0x00000004 [2] EP1_IN (0) - // 0x00000002 [1] EP0_OUT (0) - // 0x00000001 [0] EP0_IN (0) - io_rw_32 abort; - - _REG_(USB_EP_ABORT_DONE_OFFSET) // USB_EP_ABORT_DONE - // Device only: Used in conjunction with `EP_ABORT` - // 0x80000000 [31] EP15_OUT (0) - // 0x40000000 [30] EP15_IN (0) - // 0x20000000 [29] EP14_OUT (0) - // 0x10000000 [28] EP14_IN (0) - // 0x08000000 [27] EP13_OUT (0) - // 0x04000000 [26] EP13_IN (0) - // 0x02000000 [25] EP12_OUT (0) - // 0x01000000 [24] EP12_IN (0) - // 0x00800000 [23] EP11_OUT (0) - // 0x00400000 [22] EP11_IN (0) - // 0x00200000 [21] EP10_OUT (0) - // 0x00100000 [20] EP10_IN (0) - // 0x00080000 [19] EP9_OUT (0) - // 0x00040000 [18] EP9_IN (0) - // 0x00020000 [17] EP8_OUT (0) - // 0x00010000 [16] EP8_IN (0) - // 0x00008000 [15] EP7_OUT (0) - // 0x00004000 [14] EP7_IN (0) - // 0x00002000 [13] EP6_OUT (0) - // 0x00001000 [12] EP6_IN (0) - // 0x00000800 [11] EP5_OUT (0) - // 0x00000400 [10] EP5_IN (0) - // 0x00000200 [9] EP4_OUT (0) - // 0x00000100 [8] EP4_IN (0) - // 0x00000080 [7] EP3_OUT (0) - // 0x00000040 [6] EP3_IN (0) - // 0x00000020 [5] EP2_OUT (0) - // 0x00000010 [4] EP2_IN (0) - // 0x00000008 [3] EP1_OUT (0) - // 0x00000004 [2] EP1_IN (0) - // 0x00000002 [1] EP0_OUT (0) - // 0x00000001 [0] EP0_IN (0) - io_rw_32 abort_done; - - _REG_(USB_EP_STALL_ARM_OFFSET) // USB_EP_STALL_ARM - // Device: this bit must be set in conjunction with the `STALL` bit in the buffer control register... - // 0x00000002 [1] EP0_OUT (0) - // 0x00000001 [0] EP0_IN (0) - io_rw_32 ep_stall_arm; - - _REG_(USB_NAK_POLL_OFFSET) // USB_NAK_POLL - // Used by the host controller - // 0xf0000000 [31:28] RETRY_COUNT_HI (0x0) Bits 9:6 of nak_retry count - // 0x08000000 [27] EPX_STOPPED_ON_NAK (0) EPX polling has stopped because a nak was received - // 0x04000000 [26] STOP_EPX_ON_NAK (0) Stop polling epx when a nak is received - // 0x03ff0000 [25:16] DELAY_FS (0x010) NAK polling interval for a full speed device - // 0x0000fc00 [15:10] RETRY_COUNT_LO (0x00) Bits 5:0 of nak_retry_count - // 0x000003ff [9:0] DELAY_LS (0x010) NAK polling interval for a low speed device - io_rw_32 nak_poll; - - _REG_(USB_EP_STATUS_STALL_NAK_OFFSET) // USB_EP_STATUS_STALL_NAK - // Device: bits are set when the `IRQ_ON_NAK` or `IRQ_ON_STALL` bits are set - // 0x80000000 [31] EP15_OUT (0) - // 0x40000000 [30] EP15_IN (0) - // 0x20000000 [29] EP14_OUT (0) - // 0x10000000 [28] EP14_IN (0) - // 0x08000000 [27] EP13_OUT (0) - // 0x04000000 [26] EP13_IN (0) - // 0x02000000 [25] EP12_OUT (0) - // 0x01000000 [24] EP12_IN (0) - // 0x00800000 [23] EP11_OUT (0) - // 0x00400000 [22] EP11_IN (0) - // 0x00200000 [21] EP10_OUT (0) - // 0x00100000 [20] EP10_IN (0) - // 0x00080000 [19] EP9_OUT (0) - // 0x00040000 [18] EP9_IN (0) - // 0x00020000 [17] EP8_OUT (0) - // 0x00010000 [16] EP8_IN (0) - // 0x00008000 [15] EP7_OUT (0) - // 0x00004000 [14] EP7_IN (0) - // 0x00002000 [13] EP6_OUT (0) - // 0x00001000 [12] EP6_IN (0) - // 0x00000800 [11] EP5_OUT (0) - // 0x00000400 [10] EP5_IN (0) - // 0x00000200 [9] EP4_OUT (0) - // 0x00000100 [8] EP4_IN (0) - // 0x00000080 [7] EP3_OUT (0) - // 0x00000040 [6] EP3_IN (0) - // 0x00000020 [5] EP2_OUT (0) - // 0x00000010 [4] EP2_IN (0) - // 0x00000008 [3] EP1_OUT (0) - // 0x00000004 [2] EP1_IN (0) - // 0x00000002 [1] EP0_OUT (0) - // 0x00000001 [0] EP0_IN (0) - io_rw_32 ep_nak_stall_status; - - _REG_(USB_USB_MUXING_OFFSET) // USB_USB_MUXING - // Where to connect the USB controller - // 0x80000000 [31] SWAP_DPDM (0) Swap the USB PHY DP and DM pins and all related controls... - // 0x00000010 [4] USBPHY_AS_GPIO (0) Use the usb DP and DM pins as GPIO pins instead of... - // 0x00000008 [3] SOFTCON (0) - // 0x00000004 [2] TO_DIGITAL_PAD (0) - // 0x00000002 [1] TO_EXTPHY (0) - // 0x00000001 [0] TO_PHY (1) - io_rw_32 muxing; - - _REG_(USB_USB_PWR_OFFSET) // USB_USB_PWR - // Overrides for the power signals in the event that the VBUS signals are not hooked up to GPIO - // 0x00000020 [5] OVERCURR_DETECT_EN (0) - // 0x00000010 [4] OVERCURR_DETECT (0) - // 0x00000008 [3] VBUS_DETECT_OVERRIDE_EN (0) - // 0x00000004 [2] VBUS_DETECT (0) - // 0x00000002 [1] VBUS_EN_OVERRIDE_EN (0) - // 0x00000001 [0] VBUS_EN (0) - io_rw_32 pwr; - - _REG_(USB_USBPHY_DIRECT_OFFSET) // USB_USBPHY_DIRECT - // This register allows for direct control of the USB phy - // 0x02000000 [25] RX_DM_OVERRIDE (0) Override rx_dm value into controller - // 0x01000000 [24] RX_DP_OVERRIDE (0) Override rx_dp value into controller - // 0x00800000 [23] RX_DD_OVERRIDE (0) Override rx_dd value into controller - // 0x00400000 [22] DM_OVV (0) DM over voltage - // 0x00200000 [21] DP_OVV (0) DP over voltage - // 0x00100000 [20] DM_OVCN (0) DM overcurrent - // 0x00080000 [19] DP_OVCN (0) DP overcurrent - // 0x00040000 [18] RX_DM (0) DPM pin state - // 0x00020000 [17] RX_DP (0) DPP pin state - // 0x00010000 [16] RX_DD (0) Differential RX - // 0x00008000 [15] TX_DIFFMODE (0) TX_DIFFMODE=0: Single ended mode + - // 0x00004000 [14] TX_FSSLEW (0) TX_FSSLEW=0: Low speed slew rate + - // 0x00002000 [13] TX_PD (0) TX power down override (if override enable is set) - // 0x00001000 [12] RX_PD (0) RX power down override (if override enable is set) - // 0x00000800 [11] TX_DM (0) Output data - // 0x00000400 [10] TX_DP (0) Output data - // 0x00000200 [9] TX_DM_OE (0) Output enable - // 0x00000100 [8] TX_DP_OE (0) Output enable - // 0x00000040 [6] DM_PULLDN_EN (0) DM pull down enable - // 0x00000020 [5] DM_PULLUP_EN (0) DM pull up enable - // 0x00000010 [4] DM_PULLUP_HISEL (0) Enable the second DM pull up resistor - // 0x00000004 [2] DP_PULLDN_EN (0) DP pull down enable - // 0x00000002 [1] DP_PULLUP_EN (0) DP pull up enable - // 0x00000001 [0] DP_PULLUP_HISEL (0) Enable the second DP pull up resistor - io_rw_32 phy_direct; - - _REG_(USB_USBPHY_DIRECT_OVERRIDE_OFFSET) // USB_USBPHY_DIRECT_OVERRIDE - // Override enable for each control in usbphy_direct - // 0x00040000 [18] RX_DM_OVERRIDE_EN (0) - // 0x00020000 [17] RX_DP_OVERRIDE_EN (0) - // 0x00010000 [16] RX_DD_OVERRIDE_EN (0) - // 0x00008000 [15] TX_DIFFMODE_OVERRIDE_EN (0) - // 0x00001000 [12] DM_PULLUP_OVERRIDE_EN (0) - // 0x00000800 [11] TX_FSSLEW_OVERRIDE_EN (0) - // 0x00000400 [10] TX_PD_OVERRIDE_EN (0) - // 0x00000200 [9] RX_PD_OVERRIDE_EN (0) - // 0x00000100 [8] TX_DM_OVERRIDE_EN (0) - // 0x00000080 [7] TX_DP_OVERRIDE_EN (0) - // 0x00000040 [6] TX_DM_OE_OVERRIDE_EN (0) - // 0x00000020 [5] TX_DP_OE_OVERRIDE_EN (0) - // 0x00000010 [4] DM_PULLDN_EN_OVERRIDE_EN (0) - // 0x00000008 [3] DP_PULLDN_EN_OVERRIDE_EN (0) - // 0x00000004 [2] DP_PULLUP_EN_OVERRIDE_EN (0) - // 0x00000002 [1] DM_PULLUP_HISEL_OVERRIDE_EN (0) - // 0x00000001 [0] DP_PULLUP_HISEL_OVERRIDE_EN (0) - io_rw_32 phy_direct_override; - - _REG_(USB_USBPHY_TRIM_OFFSET) // USB_USBPHY_TRIM - // Used to adjust trim values of USB phy pull down resistors - // 0x00001f00 [12:8] DM_PULLDN_TRIM (0x1f) Value to drive to USB PHY + - // 0x0000001f [4:0] DP_PULLDN_TRIM (0x1f) Value to drive to USB PHY + - io_rw_32 phy_trim; - - _REG_(USB_LINESTATE_TUNING_OFFSET) // USB_LINESTATE_TUNING - // Used for debug only - // 0x00000f00 [11:8] SPARE_FIX (0x0) - // 0x00000080 [7] DEV_LS_WAKE_FIX (1) Device - exit suspend on any non-idle signalling, not... - // 0x00000040 [6] DEV_RX_ERR_QUIESCE (1) Device - suppress repeated errors until the device FSM... - // 0x00000020 [5] SIE_RX_CHATTER_SE0_FIX (1) RX - when recovering from line chatter or bitstuff... - // 0x00000010 [4] SIE_RX_BITSTUFF_FIX (1) RX - when a bitstuff error is signalled by rx_dasm,... - // 0x00000008 [3] DEV_BUFF_CONTROL_DOUBLE_READ_FIX (1) Device - the controller FSM performs two reads of the... - // 0x00000004 [2] MULTI_HUB_FIX (0) Host - increase inter-packet and turnaround timeouts to... - // 0x00000002 [1] LINESTATE_DELAY (0) Device/Host - add an extra 1-bit debounce of linestate sampling - // 0x00000001 [0] RCV_DELAY (0) Device - register the received data to account for hub... - io_rw_32 linestate_tuning; - - _REG_(USB_INTR_OFFSET) // USB_INTR - // Raw Interrupts - // 0x00800000 [23] EPX_STOPPED_ON_NAK (0) Source: NAK_POLL - // 0x00400000 [22] DEV_SM_WATCHDOG_FIRED (0) Source: DEV_SM_WATCHDOG - // 0x00200000 [21] ENDPOINT_ERROR (0) Source: SIE_STATUS - // 0x00100000 [20] RX_SHORT_PACKET (0) Source: SIE_STATUS - // 0x00080000 [19] EP_STALL_NAK (0) Raised when any bit in EP_STATUS_STALL_NAK is set - // 0x00040000 [18] ABORT_DONE (0) Raised when any bit in ABORT_DONE is set - // 0x00020000 [17] DEV_SOF (0) Set every time the device receives a SOF (Start of Frame) packet - // 0x00010000 [16] SETUP_REQ (0) Device - // 0x00008000 [15] DEV_RESUME_FROM_HOST (0) Set when the device receives a resume from the host - // 0x00004000 [14] DEV_SUSPEND (0) Set when the device suspend state changes - // 0x00002000 [13] DEV_CONN_DIS (0) Set when the device connection state changes - // 0x00001000 [12] BUS_RESET (0) Source: SIE_STATUS - // 0x00000800 [11] VBUS_DETECT (0) Source: SIE_STATUS - // 0x00000400 [10] STALL (0) Source: SIE_STATUS - // 0x00000200 [9] ERROR_CRC (0) Source: SIE_STATUS - // 0x00000100 [8] ERROR_BIT_STUFF (0) Source: SIE_STATUS - // 0x00000080 [7] ERROR_RX_OVERFLOW (0) Source: SIE_STATUS - // 0x00000040 [6] ERROR_RX_TIMEOUT (0) Source: SIE_STATUS - // 0x00000020 [5] ERROR_DATA_SEQ (0) Source: SIE_STATUS - // 0x00000010 [4] BUFF_STATUS (0) Raised when any bit in BUFF_STATUS is set - // 0x00000008 [3] TRANS_COMPLETE (0) Raised every time SIE_STATUS - // 0x00000004 [2] HOST_SOF (0) Host: raised every time the host sends a SOF (Start of Frame) - // 0x00000002 [1] HOST_RESUME (0) Host: raised when a device wakes up the host - // 0x00000001 [0] HOST_CONN_DIS (0) Host: raised when a device is connected or disconnected (i - io_ro_32 intr; - - _REG_(USB_INTE_OFFSET) // USB_INTE - // Interrupt Enable - // 0x00800000 [23] EPX_STOPPED_ON_NAK (0) Source: NAK_POLL - // 0x00400000 [22] DEV_SM_WATCHDOG_FIRED (0) Source: DEV_SM_WATCHDOG - // 0x00200000 [21] ENDPOINT_ERROR (0) Source: SIE_STATUS - // 0x00100000 [20] RX_SHORT_PACKET (0) Source: SIE_STATUS - // 0x00080000 [19] EP_STALL_NAK (0) Raised when any bit in EP_STATUS_STALL_NAK is set - // 0x00040000 [18] ABORT_DONE (0) Raised when any bit in ABORT_DONE is set - // 0x00020000 [17] DEV_SOF (0) Set every time the device receives a SOF (Start of Frame) packet - // 0x00010000 [16] SETUP_REQ (0) Device - // 0x00008000 [15] DEV_RESUME_FROM_HOST (0) Set when the device receives a resume from the host - // 0x00004000 [14] DEV_SUSPEND (0) Set when the device suspend state changes - // 0x00002000 [13] DEV_CONN_DIS (0) Set when the device connection state changes - // 0x00001000 [12] BUS_RESET (0) Source: SIE_STATUS - // 0x00000800 [11] VBUS_DETECT (0) Source: SIE_STATUS - // 0x00000400 [10] STALL (0) Source: SIE_STATUS - // 0x00000200 [9] ERROR_CRC (0) Source: SIE_STATUS - // 0x00000100 [8] ERROR_BIT_STUFF (0) Source: SIE_STATUS - // 0x00000080 [7] ERROR_RX_OVERFLOW (0) Source: SIE_STATUS - // 0x00000040 [6] ERROR_RX_TIMEOUT (0) Source: SIE_STATUS - // 0x00000020 [5] ERROR_DATA_SEQ (0) Source: SIE_STATUS - // 0x00000010 [4] BUFF_STATUS (0) Raised when any bit in BUFF_STATUS is set - // 0x00000008 [3] TRANS_COMPLETE (0) Raised every time SIE_STATUS - // 0x00000004 [2] HOST_SOF (0) Host: raised every time the host sends a SOF (Start of Frame) - // 0x00000002 [1] HOST_RESUME (0) Host: raised when a device wakes up the host - // 0x00000001 [0] HOST_CONN_DIS (0) Host: raised when a device is connected or disconnected (i - io_rw_32 inte; - - _REG_(USB_INTF_OFFSET) // USB_INTF - // Interrupt Force - // 0x00800000 [23] EPX_STOPPED_ON_NAK (0) Source: NAK_POLL - // 0x00400000 [22] DEV_SM_WATCHDOG_FIRED (0) Source: DEV_SM_WATCHDOG - // 0x00200000 [21] ENDPOINT_ERROR (0) Source: SIE_STATUS - // 0x00100000 [20] RX_SHORT_PACKET (0) Source: SIE_STATUS - // 0x00080000 [19] EP_STALL_NAK (0) Raised when any bit in EP_STATUS_STALL_NAK is set - // 0x00040000 [18] ABORT_DONE (0) Raised when any bit in ABORT_DONE is set - // 0x00020000 [17] DEV_SOF (0) Set every time the device receives a SOF (Start of Frame) packet - // 0x00010000 [16] SETUP_REQ (0) Device - // 0x00008000 [15] DEV_RESUME_FROM_HOST (0) Set when the device receives a resume from the host - // 0x00004000 [14] DEV_SUSPEND (0) Set when the device suspend state changes - // 0x00002000 [13] DEV_CONN_DIS (0) Set when the device connection state changes - // 0x00001000 [12] BUS_RESET (0) Source: SIE_STATUS - // 0x00000800 [11] VBUS_DETECT (0) Source: SIE_STATUS - // 0x00000400 [10] STALL (0) Source: SIE_STATUS - // 0x00000200 [9] ERROR_CRC (0) Source: SIE_STATUS - // 0x00000100 [8] ERROR_BIT_STUFF (0) Source: SIE_STATUS - // 0x00000080 [7] ERROR_RX_OVERFLOW (0) Source: SIE_STATUS - // 0x00000040 [6] ERROR_RX_TIMEOUT (0) Source: SIE_STATUS - // 0x00000020 [5] ERROR_DATA_SEQ (0) Source: SIE_STATUS - // 0x00000010 [4] BUFF_STATUS (0) Raised when any bit in BUFF_STATUS is set - // 0x00000008 [3] TRANS_COMPLETE (0) Raised every time SIE_STATUS - // 0x00000004 [2] HOST_SOF (0) Host: raised every time the host sends a SOF (Start of Frame) - // 0x00000002 [1] HOST_RESUME (0) Host: raised when a device wakes up the host - // 0x00000001 [0] HOST_CONN_DIS (0) Host: raised when a device is connected or disconnected (i - io_rw_32 intf; - - _REG_(USB_INTS_OFFSET) // USB_INTS - // Interrupt status after masking & forcing - // 0x00800000 [23] EPX_STOPPED_ON_NAK (0) Source: NAK_POLL - // 0x00400000 [22] DEV_SM_WATCHDOG_FIRED (0) Source: DEV_SM_WATCHDOG - // 0x00200000 [21] ENDPOINT_ERROR (0) Source: SIE_STATUS - // 0x00100000 [20] RX_SHORT_PACKET (0) Source: SIE_STATUS - // 0x00080000 [19] EP_STALL_NAK (0) Raised when any bit in EP_STATUS_STALL_NAK is set - // 0x00040000 [18] ABORT_DONE (0) Raised when any bit in ABORT_DONE is set - // 0x00020000 [17] DEV_SOF (0) Set every time the device receives a SOF (Start of Frame) packet - // 0x00010000 [16] SETUP_REQ (0) Device - // 0x00008000 [15] DEV_RESUME_FROM_HOST (0) Set when the device receives a resume from the host - // 0x00004000 [14] DEV_SUSPEND (0) Set when the device suspend state changes - // 0x00002000 [13] DEV_CONN_DIS (0) Set when the device connection state changes - // 0x00001000 [12] BUS_RESET (0) Source: SIE_STATUS - // 0x00000800 [11] VBUS_DETECT (0) Source: SIE_STATUS - // 0x00000400 [10] STALL (0) Source: SIE_STATUS - // 0x00000200 [9] ERROR_CRC (0) Source: SIE_STATUS - // 0x00000100 [8] ERROR_BIT_STUFF (0) Source: SIE_STATUS - // 0x00000080 [7] ERROR_RX_OVERFLOW (0) Source: SIE_STATUS - // 0x00000040 [6] ERROR_RX_TIMEOUT (0) Source: SIE_STATUS - // 0x00000020 [5] ERROR_DATA_SEQ (0) Source: SIE_STATUS - // 0x00000010 [4] BUFF_STATUS (0) Raised when any bit in BUFF_STATUS is set - // 0x00000008 [3] TRANS_COMPLETE (0) Raised every time SIE_STATUS - // 0x00000004 [2] HOST_SOF (0) Host: raised every time the host sends a SOF (Start of Frame) - // 0x00000002 [1] HOST_RESUME (0) Host: raised when a device wakes up the host - // 0x00000001 [0] HOST_CONN_DIS (0) Host: raised when a device is connected or disconnected (i - io_ro_32 ints; - - uint32_t _pad0[25]; - - _REG_(USB_SOF_TIMESTAMP_RAW_OFFSET) // USB_SOF_TIMESTAMP_RAW - // Device only - // 0x001fffff [20:0] SOF_TIMESTAMP_RAW (0x000000) - io_ro_32 sof_timestamp_raw; - - _REG_(USB_SOF_TIMESTAMP_LAST_OFFSET) // USB_SOF_TIMESTAMP_LAST - // Device only - // 0x001fffff [20:0] SOF_TIMESTAMP_LAST (0x000000) - io_ro_32 sof_timestamp_last; - - _REG_(USB_SM_STATE_OFFSET) // USB_SM_STATE - // 0x00000f00 [11:8] RX_DASM (0x0) - // 0x000000e0 [7:5] BC_STATE (0x0) - // 0x0000001f [4:0] STATE (0x00) - io_ro_32 sm_state; - - _REG_(USB_EP_TX_ERROR_OFFSET) // USB_EP_TX_ERROR - // TX error count for each endpoint - // 0xc0000000 [31:30] EP15 (0x0) - // 0x30000000 [29:28] EP14 (0x0) - // 0x0c000000 [27:26] EP13 (0x0) - // 0x03000000 [25:24] EP12 (0x0) - // 0x00c00000 [23:22] EP11 (0x0) - // 0x00300000 [21:20] EP10 (0x0) - // 0x000c0000 [19:18] EP9 (0x0) - // 0x00030000 [17:16] EP8 (0x0) - // 0x0000c000 [15:14] EP7 (0x0) - // 0x00003000 [13:12] EP6 (0x0) - // 0x00000c00 [11:10] EP5 (0x0) - // 0x00000300 [9:8] EP4 (0x0) - // 0x000000c0 [7:6] EP3 (0x0) - // 0x00000030 [5:4] EP2 (0x0) - // 0x0000000c [3:2] EP1 (0x0) - // 0x00000003 [1:0] EP0 (0x0) - io_rw_32 ep_tx_error; - - _REG_(USB_EP_RX_ERROR_OFFSET) // USB_EP_RX_ERROR - // RX error count for each endpoint - // 0x80000000 [31] EP15_SEQ (0) - // 0x40000000 [30] EP15_TRANSACTION (0) - // 0x20000000 [29] EP14_SEQ (0) - // 0x10000000 [28] EP14_TRANSACTION (0) - // 0x08000000 [27] EP13_SEQ (0) - // 0x04000000 [26] EP13_TRANSACTION (0) - // 0x02000000 [25] EP12_SEQ (0) - // 0x01000000 [24] EP12_TRANSACTION (0) - // 0x00800000 [23] EP11_SEQ (0) - // 0x00400000 [22] EP11_TRANSACTION (0) - // 0x00200000 [21] EP10_SEQ (0) - // 0x00100000 [20] EP10_TRANSACTION (0) - // 0x00080000 [19] EP9_SEQ (0) - // 0x00040000 [18] EP9_TRANSACTION (0) - // 0x00020000 [17] EP8_SEQ (0) - // 0x00010000 [16] EP8_TRANSACTION (0) - // 0x00008000 [15] EP7_SEQ (0) - // 0x00004000 [14] EP7_TRANSACTION (0) - // 0x00002000 [13] EP6_SEQ (0) - // 0x00001000 [12] EP6_TRANSACTION (0) - // 0x00000800 [11] EP5_SEQ (0) - // 0x00000400 [10] EP5_TRANSACTION (0) - // 0x00000200 [9] EP4_SEQ (0) - // 0x00000100 [8] EP4_TRANSACTION (0) - // 0x00000080 [7] EP3_SEQ (0) - // 0x00000040 [6] EP3_TRANSACTION (0) - // 0x00000020 [5] EP2_SEQ (0) - // 0x00000010 [4] EP2_TRANSACTION (0) - // 0x00000008 [3] EP1_SEQ (0) - // 0x00000004 [2] EP1_TRANSACTION (0) - // 0x00000002 [1] EP0_SEQ (0) - // 0x00000001 [0] EP0_TRANSACTION (0) - io_rw_32 ep_rx_error; - - _REG_(USB_DEV_SM_WATCHDOG_OFFSET) // USB_DEV_SM_WATCHDOG - // Watchdog that forces the device state machine to idle and raises an interrupt if the device... - // 0x00100000 [20] FIRED (0) - // 0x00080000 [19] RESET (0) Set to 1 to forcibly reset the device state machine on... - // 0x00040000 [18] ENABLE (0) - // 0x0003ffff [17:0] LIMIT (0x00000) - io_rw_32 dev_sm_watchdog; -} usb_hw_t; - -#define usb_hw ((usb_hw_t *)USBCTRL_REGS_BASE) -static_assert(sizeof (usb_hw_t) == 0x0118, ""); - -#endif // _HARDWARE_STRUCTS_USB_H - diff --git a/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/usb_dpram.h b/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/usb_dpram.h deleted file mode 100644 index aaa4ec58b8..0000000000 --- a/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/usb_dpram.h +++ /dev/null @@ -1,128 +0,0 @@ -/** - * Copyright (c) 2024 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _HARDWARE_STRUCTS_USB_DPRAM_H -#define _HARDWARE_STRUCTS_USB_DPRAM_H - -#include "hardware/address_mapped.h" -#include "hardware/regs/usb.h" - -// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_usb -// -// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) -// _REG_(x) will link to the corresponding register in hardware/regs/usb.h. -// -// Bit-field descriptions are of the form: -// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION - - -// 0-15 -#define USB_NUM_ENDPOINTS 16 - -// allow user to restrict number of endpoints available to save RAN -#ifndef USB_MAX_ENDPOINTS -#define USB_MAX_ENDPOINTS USB_NUM_ENDPOINTS -#endif - -// 1-15 -#define USB_HOST_INTERRUPT_ENDPOINTS (USB_NUM_ENDPOINTS - 1) - -// Endpoint buffer control bits -#define USB_BUF_CTRL_FULL 0x00008000u -#define USB_BUF_CTRL_LAST 0x00004000u -#define USB_BUF_CTRL_DATA0_PID 0x00000000u -#define USB_BUF_CTRL_DATA1_PID 0x00002000u -#define USB_BUF_CTRL_SEL 0x00001000u -#define USB_BUF_CTRL_STALL 0x00000800u -#define USB_BUF_CTRL_AVAIL 0x00000400u -#define USB_BUF_CTRL_LEN_MASK 0x000003FFu -#define USB_BUF_CTRL_LEN_LSB 0 - -// ep_inout_ctrl bits -#define EP_CTRL_ENABLE_BITS (1u << 31u) -#define EP_CTRL_DOUBLE_BUFFERED_BITS (1u << 30) -#define EP_CTRL_INTERRUPT_PER_BUFFER (1u << 29) -#define EP_CTRL_INTERRUPT_PER_DOUBLE_BUFFER (1u << 28) -#define EP_CTRL_INTERRUPT_ON_NAK (1u << 16) -#define EP_CTRL_INTERRUPT_ON_STALL (1u << 17) -#define EP_CTRL_BUFFER_TYPE_LSB 26u -#define EP_CTRL_HOST_INTERRUPT_INTERVAL_LSB 16u - -#define USB_DPRAM_SIZE 4096u - -// PICO_CONFIG: USB_DPRAM_MAX, Set amount of USB RAM used by USB system, min=0, max=4096, default=4096, group=hardware_usb -// Allow user to claim some of the USB RAM for themselves -#ifndef USB_DPRAM_MAX -#define USB_DPRAM_MAX USB_DPRAM_SIZE -#endif - -// Define maximum packet sizes -#define USB_MAX_ISO_PACKET_SIZE 1023 -#define USB_MAX_PACKET_SIZE 64 - -typedef struct { - // 4K of DPSRAM at beginning. Note this supports 8, 16, and 32 bit accesses - volatile uint8_t setup_packet[8]; // First 8 bytes are always for setup packets - - // Starts at ep1 - struct usb_device_dpram_ep_ctrl { - io_rw_32 in; - io_rw_32 out; - } ep_ctrl[USB_NUM_ENDPOINTS - 1]; - - // Starts at ep0 - struct usb_device_dpram_ep_buf_ctrl { - io_rw_32 in; - io_rw_32 out; - } ep_buf_ctrl[USB_NUM_ENDPOINTS]; - - // EP0 buffers are fixed. Assumes single buffered mode for EP0 - uint8_t ep0_buf_a[0x40]; - uint8_t ep0_buf_b[0x40]; - - // Rest of DPRAM can be carved up as needed - uint8_t epx_data[USB_DPRAM_MAX - 0x180]; -} usb_device_dpram_t; - -static_assert(sizeof(usb_device_dpram_t) == USB_DPRAM_MAX, ""); -static_assert(offsetof(usb_device_dpram_t, epx_data) == 0x180, ""); - -typedef struct { - // 4K of DPSRAM at beginning. Note this supports 8, 16, and 32 bit accesses - volatile uint8_t setup_packet[8]; // First 8 bytes are always for setup packets - - // Interrupt endpoint control 1 -> 15 - struct usb_host_dpram_ep_ctrl { - io_rw_32 ctrl; - io_rw_32 spare; - } int_ep_ctrl[USB_HOST_INTERRUPT_ENDPOINTS]; - - io_rw_32 epx_buf_ctrl; - io_rw_32 _spare0; - - // Interrupt endpoint buffer control - struct usb_host_dpram_ep_buf_ctrl { - io_rw_32 ctrl; - io_rw_32 spare; - } int_ep_buffer_ctrl[USB_HOST_INTERRUPT_ENDPOINTS]; - - io_rw_32 epx_ctrl; - - uint8_t _spare1[124]; - - // Should start at 0x180 - uint8_t epx_data[USB_DPRAM_MAX - 0x180]; -} usb_host_dpram_t; - -static_assert(sizeof(usb_host_dpram_t) == USB_DPRAM_MAX, ""); -static_assert(offsetof(usb_host_dpram_t, epx_data) == 0x180, ""); - -#define usb_dpram ((usb_device_dpram_t *)USBCTRL_DPRAM_BASE) -#define usbh_dpram ((usb_host_dpram_t *)USBCTRL_DPRAM_BASE) - -static_assert( USB_HOST_INTERRUPT_ENDPOINTS == 15, ""); - -#endif // _HARDWARE_STRUCTS_USB_DPRAM_H \ No newline at end of file diff --git a/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/watchdog.h b/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/watchdog.h deleted file mode 100644 index 19c7bfaeea..0000000000 --- a/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/watchdog.h +++ /dev/null @@ -1,59 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _HARDWARE_STRUCTS_WATCHDOG_H -#define _HARDWARE_STRUCTS_WATCHDOG_H - -/** - * \file rp2350/watchdog.h - */ - -#include "hardware/address_mapped.h" -#include "hardware/regs/watchdog.h" - -// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_watchdog -// -// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) -// _REG_(x) will link to the corresponding register in hardware/regs/watchdog.h. -// -// Bit-field descriptions are of the form: -// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION - -typedef struct { - _REG_(WATCHDOG_CTRL_OFFSET) // WATCHDOG_CTRL - // Watchdog control + - // 0x80000000 [31] TRIGGER (0) Trigger a watchdog reset - // 0x40000000 [30] ENABLE (0) When not enabled the watchdog timer is paused - // 0x04000000 [26] PAUSE_DBG1 (1) Pause the watchdog timer when processor 1 is in debug mode - // 0x02000000 [25] PAUSE_DBG0 (1) Pause the watchdog timer when processor 0 is in debug mode - // 0x01000000 [24] PAUSE_JTAG (1) Pause the watchdog timer when JTAG is accessing the bus fabric - // 0x00ffffff [23:0] TIME (0x000000) Indicates the time in usec before a watchdog reset will... - io_rw_32 ctrl; - - _REG_(WATCHDOG_LOAD_OFFSET) // WATCHDOG_LOAD - // Load the watchdog timer - // 0x00ffffff [23:0] LOAD (0x000000) - io_wo_32 load; - - _REG_(WATCHDOG_REASON_OFFSET) // WATCHDOG_REASON - // Logs the reason for the last reset - // 0x00000002 [1] FORCE (0) - // 0x00000001 [0] TIMER (0) - io_ro_32 reason; - - // (Description copied from array index 0 register WATCHDOG_SCRATCH0 applies similarly to other array indexes) - _REG_(WATCHDOG_SCRATCH0_OFFSET) // WATCHDOG_SCRATCH0 - // Scratch register - // 0xffffffff [31:0] SCRATCH0 (0x00000000) - io_rw_32 scratch[8]; -} watchdog_hw_t; - -#define watchdog_hw ((watchdog_hw_t *)WATCHDOG_BASE) -static_assert(sizeof (watchdog_hw_t) == 0x002c, ""); - -#endif // _HARDWARE_STRUCTS_WATCHDOG_H - diff --git a/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/xip.h b/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/xip.h deleted file mode 100644 index ee5cb23668..0000000000 --- a/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/xip.h +++ /dev/null @@ -1,79 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _HARDWARE_STRUCTS_XIP_H -#define _HARDWARE_STRUCTS_XIP_H - -/** - * \file rp2350/xip.h - */ - -#include "hardware/address_mapped.h" -#include "hardware/regs/xip.h" - -// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_xip -// -// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) -// _REG_(x) will link to the corresponding register in hardware/regs/xip.h. -// -// Bit-field descriptions are of the form: -// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION - -typedef struct { - _REG_(XIP_CTRL_OFFSET) // XIP_CTRL - // Cache control register - // 0x00000800 [11] WRITABLE_M1 (0) If 1, enable writes to XIP memory window 1 (addresses... - // 0x00000400 [10] WRITABLE_M0 (0) If 1, enable writes to XIP memory window 0 (addresses... - // 0x00000200 [9] SPLIT_WAYS (0) When 1, route all cached+Secure accesses to way 0 of the... - // 0x00000100 [8] MAINT_NONSEC (0) When 0, Non-secure accesses to the cache maintenance... - // 0x00000080 [7] NO_UNTRANSLATED_NONSEC (1) When 1, Non-secure accesses to the uncached,... - // 0x00000040 [6] NO_UNTRANSLATED_SEC (0) When 1, Secure accesses to the uncached, untranslated... - // 0x00000020 [5] NO_UNCACHED_NONSEC (0) When 1, Non-secure accesses to the uncached window... - // 0x00000010 [4] NO_UNCACHED_SEC (0) When 1, Secure accesses to the uncached window... - // 0x00000008 [3] POWER_DOWN (0) When 1, the cache memories are powered down - // 0x00000002 [1] EN_NONSECURE (1) When 1, enable the cache for Non-secure accesses - // 0x00000001 [0] EN_SECURE (1) When 1, enable the cache for Secure accesses - io_rw_32 ctrl; - - uint32_t _pad0; - - _REG_(XIP_STAT_OFFSET) // XIP_STAT - // 0x00000004 [2] FIFO_FULL (0) When 1, indicates the XIP streaming FIFO is completely full - // 0x00000002 [1] FIFO_EMPTY (1) When 1, indicates the XIP streaming FIFO is completely empty - io_ro_32 stat; - - _REG_(XIP_CTR_HIT_OFFSET) // XIP_CTR_HIT - // Cache Hit counter - // 0xffffffff [31:0] CTR_HIT (0x00000000) A 32 bit saturating counter that increments upon each... - io_rw_32 ctr_hit; - - _REG_(XIP_CTR_ACC_OFFSET) // XIP_CTR_ACC - // Cache Access counter - // 0xffffffff [31:0] CTR_ACC (0x00000000) A 32 bit saturating counter that increments upon each... - io_rw_32 ctr_acc; - - _REG_(XIP_STREAM_ADDR_OFFSET) // XIP_STREAM_ADDR - // FIFO stream address - // 0xfffffffc [31:2] STREAM_ADDR (0x00000000) The address of the next word to be streamed from flash... - io_rw_32 stream_addr; - - _REG_(XIP_STREAM_CTR_OFFSET) // XIP_STREAM_CTR - // FIFO stream control - // 0x003fffff [21:0] STREAM_CTR (0x000000) Write a nonzero value to start a streaming read - io_rw_32 stream_ctr; - - _REG_(XIP_STREAM_FIFO_OFFSET) // XIP_STREAM_FIFO - // FIFO stream data - // 0xffffffff [31:0] STREAM_FIFO (0x00000000) Streamed data is buffered here, for retrieval by the system DMA - io_ro_32 stream_fifo; -} xip_ctrl_hw_t; - -#define xip_ctrl_hw ((xip_ctrl_hw_t *)XIP_CTRL_BASE) -static_assert(sizeof (xip_ctrl_hw_t) == 0x0020, ""); - -#endif // _HARDWARE_STRUCTS_XIP_H - diff --git a/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/xip_aux.h b/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/xip_aux.h deleted file mode 100644 index 1e1caf8c78..0000000000 --- a/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/xip_aux.h +++ /dev/null @@ -1,51 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _HARDWARE_STRUCTS_XIP_AUX_H -#define _HARDWARE_STRUCTS_XIP_AUX_H - -/** - * \file rp2350/xip_aux.h - */ - -#include "hardware/address_mapped.h" -#include "hardware/regs/xip_aux.h" - -// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_xip_aux -// -// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) -// _REG_(x) will link to the corresponding register in hardware/regs/xip_aux.h. -// -// Bit-field descriptions are of the form: -// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION - -typedef struct { - _REG_(XIP_AUX_STREAM_OFFSET) // XIP_AUX_STREAM - // Read the XIP stream FIFO (fast bus access to XIP_CTRL_STREAM_FIFO) - // 0xffffffff [31:0] STREAM (0x00000000) - io_ro_32 stream; - - _REG_(XIP_AUX_QMI_DIRECT_TX_OFFSET) // XIP_AUX_QMI_DIRECT_TX - // Write to the QMI direct-mode TX FIFO (fast bus access to QMI_DIRECT_TX) - // 0x00100000 [20] NOPUSH (0) Inhibit the RX FIFO push that would correspond to this... - // 0x00080000 [19] OE (0) Output enable (active-high) - // 0x00040000 [18] DWIDTH (0) Data width - // 0x00030000 [17:16] IWIDTH (0x0) Configure whether this FIFO record is transferred with... - // 0x0000ffff [15:0] DATA (0x0000) Data pushed here will be clocked out falling edges of... - io_wo_32 qmi_direct_tx; - - _REG_(XIP_AUX_QMI_DIRECT_RX_OFFSET) // XIP_AUX_QMI_DIRECT_RX - // Read from the QMI direct-mode RX FIFO (fast bus access to QMI_DIRECT_RX) - // 0x0000ffff [15:0] QMI_DIRECT_RX (0x0000) With each byte clocked out on the serial interface, one... - io_ro_32 qmi_direct_rx; -} xip_aux_hw_t; - -#define xip_aux_hw ((xip_aux_hw_t *)XIP_AUX_BASE) -static_assert(sizeof (xip_aux_hw_t) == 0x000c, ""); - -#endif // _HARDWARE_STRUCTS_XIP_AUX_H - diff --git a/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/xip_ctrl.h b/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/xip_ctrl.h deleted file mode 100644 index c31569b60f..0000000000 --- a/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/xip_ctrl.h +++ /dev/null @@ -1,11 +0,0 @@ -/** - * Copyright (c) 2024 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -// Support old header for compatibility (and if included, support old variable name) -#include "hardware/structs/xip.h" -#define XIP_STAT_FIFO_FULL XIP_STAT_FIFO_FULL_BITS -#define XIP_STAT_FIFO_EMPTY XIP_STAT_FIFO_EMPTY_BITS -#define XIP_STAT_FLUSH_RDY XIP_STAT_FLUSH_READY_BITS diff --git a/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/xosc.h b/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/xosc.h deleted file mode 100644 index dca0c05e8c..0000000000 --- a/lib/main/pico-sdk/rp2350/hardware_structs/include/hardware/structs/xosc.h +++ /dev/null @@ -1,64 +0,0 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/** - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _HARDWARE_STRUCTS_XOSC_H -#define _HARDWARE_STRUCTS_XOSC_H - -/** - * \file rp2350/xosc.h - */ - -#include "hardware/address_mapped.h" -#include "hardware/regs/xosc.h" - -// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_xosc -// -// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) -// _REG_(x) will link to the corresponding register in hardware/regs/xosc.h. -// -// Bit-field descriptions are of the form: -// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION - -/// \tag::xosc_hw[] -typedef struct { - _REG_(XOSC_CTRL_OFFSET) // XOSC_CTRL - // Crystal Oscillator Control - // 0x00fff000 [23:12] ENABLE (-) On power-up this field is initialised to DISABLE and the... - // 0x00000fff [11:0] FREQ_RANGE (-) The 12-bit code is intended to give some protection... - io_rw_32 ctrl; - - _REG_(XOSC_STATUS_OFFSET) // XOSC_STATUS - // Crystal Oscillator Status - // 0x80000000 [31] STABLE (0) Oscillator is running and stable - // 0x01000000 [24] BADWRITE (0) An invalid value has been written to CTRL_ENABLE or... - // 0x00001000 [12] ENABLED (-) Oscillator is enabled but not necessarily running and... - // 0x00000003 [1:0] FREQ_RANGE (-) The current frequency range setting - io_rw_32 status; - - _REG_(XOSC_DORMANT_OFFSET) // XOSC_DORMANT - // Crystal Oscillator pause control - // 0xffffffff [31:0] DORMANT (-) This is used to save power by pausing the XOSC + - io_rw_32 dormant; - - _REG_(XOSC_STARTUP_OFFSET) // XOSC_STARTUP - // Controls the startup delay - // 0x00100000 [20] X4 (-) Multiplies the startup_delay by 4, just in case - // 0x00003fff [13:0] DELAY (-) in multiples of 256*xtal_period - io_rw_32 startup; - - _REG_(XOSC_COUNT_OFFSET) // XOSC_COUNT - // A down counter running at the XOSC frequency which counts to zero and stops. - // 0x0000ffff [15:0] COUNT (0x0000) - io_rw_32 count; -} xosc_hw_t; -/// \end::xosc_hw[] - -#define xosc_hw ((xosc_hw_t *)XOSC_BASE) -static_assert(sizeof (xosc_hw_t) == 0x0014, ""); - -#endif // _HARDWARE_STRUCTS_XOSC_H - diff --git a/lib/main/pico-sdk/rp2350/pico_platform/include/pico/asm_helper.S b/lib/main/pico-sdk/rp2350/pico_platform/include/pico/asm_helper.S deleted file mode 100644 index b8eeb53c76..0000000000 --- a/lib/main/pico-sdk/rp2350/pico_platform/include/pico/asm_helper.S +++ /dev/null @@ -1,71 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "pico.h" - -#ifdef __riscv -// Get macros for convenient use of Hazard3 instructions without binutils support -#include "hardware/hazard3/instructions.h" -#endif - -#if !PICO_ASSEMBLER_IS_CLANG -#define apsr_nzcv r15 -#endif -// note we don't do this by default in this file for backwards comaptibility with user code -// that may include this file, but not use unified syntax. Note that this macro does equivalent -// setup to the pico_default_asm macro for inline assembly in C code. -.macro pico_default_asm_setup -#ifndef __riscv -.syntax unified -.cpu cortex-m33 -.fpu fpv5-sp-d16 -.thumb -#endif -.endm - -// do not put align in here as it is used mid function sometimes -.macro regular_func x -.global \x -.type \x,%function -#ifndef __riscv -.thumb_func -#endif -\x: -.endm - -.macro weak_func x -.weak \x -.type \x,%function -#ifndef __riscv -.thumb_func -#endif -\x: -.endm - -.macro regular_func_with_section x -.section .text.\x -regular_func \x -.endm - -// do not put align in here as it is used mid function sometimes -.macro wrapper_func x -regular_func WRAPPER_FUNC_NAME(\x) -.endm - -.macro weak_wrapper_func x -weak_func WRAPPER_FUNC_NAME(\x) -.endm - -.macro __pre_init_with_offset func, offset, priority_string1 -.section .preinit_array.\priority_string1 -.p2align 2 -.word \func + \offset -.endm - -// backwards compatibility -.macro __pre_init func, priority_string1 -__pre_init_with_offset func, 0, priority_string1 -.endm diff --git a/lib/main/pico-sdk/rp2350/pico_platform/include/pico/platform.h b/lib/main/pico-sdk/rp2350/pico_platform/include/pico/platform.h deleted file mode 100644 index bfc4fabe64..0000000000 --- a/lib/main/pico-sdk/rp2350/pico_platform/include/pico/platform.h +++ /dev/null @@ -1,282 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -/** \file platform.h - * \defgroup pico_platform pico_platform - * - * \brief Macros and definitions (and functions when included by non assembly code) for the RP2 family device / architecture - * to provide a common abstraction over low level compiler / platform specifics - * - * This header may be included by assembly code - */ - -#ifndef _PICO_PLATFORM_H -#define _PICO_PLATFORM_H - -#ifndef _PICO_H -#error pico/platform.h should not be included directly; include pico.h instead -#endif - -#include "pico/platform/compiler.h" -#include "pico/platform/sections.h" -#include "pico/platform/panic.h" -#include "hardware/regs/addressmap.h" -#include "hardware/regs/sio.h" -#ifdef __riscv -#include "hardware/regs/rvcsr.h" -#endif - -// PICO_CONFIG: PICO_RP2350A, Whether the current board has an RP2350 in an A (30 GPIO) package, type=bool, default=Usually provided via board header, group=pico_platform -#if 0 // make tooling checks happy -#define PICO_RP2350A 0 -#endif - -// PICO_CONFIG: PICO_RP2350_A2_SUPPORTED, Whether to include any specific software support for RP2350 A2 revision, type=bool, default=1, advanced=true, group=pico_platform -#ifndef PICO_RP2350_A2_SUPPORTED -#define PICO_RP2350_A2_SUPPORTED 1 -#endif - -// PICO_CONFIG: PICO_STACK_SIZE, Minimum amount of stack space reserved in the linker script for each core. See also PICO_CORE1_STACK_SIZE, min=0x100, default=0x800, advanced=true, group=pico_platform -#ifndef PICO_STACK_SIZE -#define PICO_STACK_SIZE _u(0x800) -#endif - -// PICO_CONFIG: PICO_HEAP_SIZE, Minimum amount of heap space reserved by the linker script, min=0x100, default=0x800, advanced=true, group=pico_platform -#ifndef PICO_HEAP_SIZE -#define PICO_HEAP_SIZE _u(0x800) -#endif - -// PICO_CONFIG: PICO_NO_RAM_VECTOR_TABLE, Enable/disable the RAM vector table, type=bool, default=0, advanced=true, group=pico_platform -#ifndef PICO_NO_RAM_VECTOR_TABLE -#define PICO_NO_RAM_VECTOR_TABLE 0 -#endif - -#ifndef PICO_RAM_VECTOR_TABLE_SIZE -#define PICO_RAM_VECTOR_TABLE_SIZE (VTABLE_FIRST_IRQ + NUM_IRQS) -#endif - -// PICO_CONFIG: PICO_USE_STACK_GUARDS, Enable/disable stack guards, type=bool, default=0, advanced=true, group=pico_platform -#ifndef PICO_USE_STACK_GUARDS -#define PICO_USE_STACK_GUARDS 0 -#endif - -#ifndef __ASSEMBLER__ - -/*! \brief No-op function for the body of tight loops - * \ingroup pico_platform - * - * No-op function intended to be called by any tight hardware polling loop. Using this ubiquitously - * makes it much easier to find tight loops, but also in the future \#ifdef-ed support for lockup - * debugging might be added - */ -static __force_inline void tight_loop_contents(void) {} - -/*! \brief Helper method to busy-wait for at least the given number of cycles - * \ingroup pico_platform - * - * This method is useful for introducing very short delays. - * - * This method busy-waits in a tight loop for the given number of system clock cycles. The total wait time is only accurate to within 2 cycles, - * and this method uses a loop counter rather than a hardware timer, so the method will always take longer than expected if an - * interrupt is handled on the calling core during the busy-wait; you can of course disable interrupts to prevent this. - * - * You can use \ref clock_get_hz(clk_sys) to determine the number of clock cycles per second if you want to convert an actual - * time duration to a number of cycles. - * - * \param minimum_cycles the minimum number of system clock cycles to delay for - */ -static inline void busy_wait_at_least_cycles(uint32_t minimum_cycles) { - pico_default_asm_volatile ( -#ifdef __riscv - // Note the range is halved on RISC-V due to signed comparison (no carry flag) - ".option push\n" - ".option norvc\n" // force 32 bit addi, so branch prediction guaranteed - ".p2align 2\n" - "1: \n" - "addi %0, %0, -2 \n" - "bgez %0, 1b\n" - ".option pop" -#else - "1: subs %0, #3\n" - "bcs 1b\n" -#endif - : "+r" (minimum_cycles) : : "cc", "memory" - ); -} - -// PICO_CONFIG: PICO_NO_FPGA_CHECK, Remove the FPGA platform check for small code size reduction, type=bool, default=1, advanced=true, group=pico_runtime -#ifndef PICO_NO_FPGA_CHECK -#define PICO_NO_FPGA_CHECK 1 -#endif - -// PICO_CONFIG: PICO_NO_SIM_CHECK, Remove the SIM platform check for small code size reduction, type=bool, default=1, advanced=true, group=pico_runtime -#ifndef PICO_NO_SIM_CHECK -#define PICO_NO_SIM_CHECK 1 -#endif - -#if PICO_NO_FPGA_CHECK -static inline bool running_on_fpga(void) {return false;} -#else -bool running_on_fpga(void); -#endif -#if PICO_NO_SIM_CHECK -static inline bool running_in_sim(void) {return false;} -#else -bool running_in_sim(void); -#endif - -/*! \brief Execute a breakpoint instruction - * \ingroup pico_platform - */ -static __force_inline void __breakpoint(void) { -#ifdef __riscv - __asm ("ebreak"); -#else - pico_default_asm_volatile ("bkpt #0" : : : "memory"); -#endif -} - -/*! \brief Get the current core number - * \ingroup pico_platform - * - * \return The core number the call was made from - */ -__force_inline static uint get_core_num(void) { - return (*(uint32_t *) (SIO_BASE + SIO_CPUID_OFFSET)); -} - -/*! \brief Get the current exception level on this core - * \ingroup pico_platform - * - * On Cortex-M this is the exception number defined in the architecture - * reference, which is equal to VTABLE_FIRST_IRQ + irq num if inside an - * interrupt handler. (VTABLE_FIRST_IRQ is defined in platform_defs.h). - * - * On Hazard3, this function returns VTABLE_FIRST_IRQ + irq num if inside of - * an external IRQ handler (or a fault from such a handler), and 0 otherwise, - * generally aligning with the Cortex-M values. - * - * \return the exception number if the CPU is handling an exception, or 0 otherwise - */ -static __force_inline uint __get_current_exception(void) { -#ifdef __riscv - uint32_t meicontext; - pico_default_asm_volatile ( - "csrr %0, %1\n" - : "=r" (meicontext) : "i" (RVCSR_MEICONTEXT_OFFSET) - ); - if (meicontext & RVCSR_MEICONTEXT_NOIRQ_BITS) { - return 0; - } else { - return VTABLE_FIRST_IRQ + ( - (meicontext & RVCSR_MEICONTEXT_IRQ_BITS) >> RVCSR_MEICONTEXT_IRQ_LSB - ); - } -#else - uint exception; - pico_default_asm_volatile ( - "mrs %0, ipsr\n" - "uxtb %0, %0\n" - : "=l" (exception) - ); - return exception; -#endif -} - -/*! \brief Return true if executing in the NonSecure state (Arm-only) - * \ingroup pico_platform - * - * \return True if currently executing in the NonSecure state on an Arm processor - */ -__force_inline static bool pico_processor_state_is_nonsecure(void) { -#ifndef __riscv - // todo add a define to disable NS checking at all? - // IDAU-Exempt addresses return S=1 when tested in the Secure state, - // whereas executing a tt in the NonSecure state will always return S=0. - uint32_t tt; - pico_default_asm_volatile ( - "movs %0, #0\n" - "tt %0, %0\n" - : "=r" (tt) : : "cc" - ); - return !(tt & (1u << 22)); -#else - // NonSecure is an Arm concept, there is nothing meaningful to return - // here. Note it's not possible in general to detect whether you are - // executing in U-mode as, for example, M-mode is classically - // virtualisable in U-mode. - return false; -#endif -} - -#define host_safe_hw_ptr(x) ((uintptr_t)(x)) -#define native_safe_hw_ptr(x) host_safe_hw_ptr(x) - -/*! \brief Returns the RP2350 chip revision number - * \ingroup pico_platform - * @return the RP2350 chip revision number (1 for B0/B1, 2 for B2) - */ -uint8_t rp2350_chip_version(void); - -/*! \brief Returns the RP2040 chip revision number for compatibility - * \ingroup pico_platform - * @return 2 RP2040 errata fixed in B2 are fixed in RP2350 - */ -static inline uint8_t rp2040_chip_version(void) { - return 2; -} - -/*! \brief Returns the RP2040 rom version number - * \ingroup pico_platform - * @return the RP2040 rom version number (1 for RP2040-B0, 2 for RP2040-B1, 3 for RP2040-B2) - */ -static inline uint8_t rp2040_rom_version(void) { - GCC_Pragma("GCC diagnostic push") - GCC_Pragma("GCC diagnostic ignored \"-Warray-bounds\"") - return *(uint8_t*)0x13; - GCC_Pragma("GCC diagnostic pop") -} - -/*! \brief Multiply two integers using an assembly `MUL` instruction - * \ingroup pico_platform - * - * This multiplies a by b using multiply instruction using the ARM mul instruction regardless of values (the compiler - * might otherwise choose to perform shifts/adds), i.e. this is a 1 cycle operation. - * - * \param a the first operand - * \param b the second operand - * \return a * b - */ -__force_inline static int32_t __mul_instruction(int32_t a, int32_t b) { -#ifdef __riscv - __asm ("mul %0, %0, %1" : "+r" (a) : "r" (b) : ); -#else - pico_default_asm ("muls %0, %1" : "+l" (a) : "l" (b) : "cc"); -#endif - return a; -} - -/*! \brief multiply two integer values using the fastest method possible - * \ingroup pico_platform - * - * Efficiently multiplies value a by possibly constant value b. - * - * If b is known to be constant and not zero or a power of 2, then a mul instruction is used rather than gcc's default - * which is often a slow combination of shifts and adds. If b is a power of 2 then a single shift is of course preferable - * and will be used - * - * \param a the first operand - * \param b the second operand - * \return a * b - */ -#define __fast_mul(a, b) __builtin_choose_expr(__builtin_constant_p(b) && !__builtin_constant_p(a), \ - (__builtin_popcount(b) >= 2 ? __mul_instruction(a,b) : (a)*(b)), \ - (a)*(b)) - -#endif // __ASSEMBLER__ - -#endif - diff --git a/lib/main/pico-sdk/rp2350/pico_platform/include/pico/platform/cpu_regs.h b/lib/main/pico-sdk/rp2350/pico_platform/include/pico/platform/cpu_regs.h deleted file mode 100644 index b79127c791..0000000000 --- a/lib/main/pico-sdk/rp2350/pico_platform/include/pico/platform/cpu_regs.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -/** \file platform.h - * \defgroup pico_platform pico_platform - * - * \brief Macros and definitions for accessing the CPU registers - * - * This header may be included by assembly code - */ - -#ifndef _PICO_PLATFORM_CPU_REGS_H -#define _PICO_PLATFORM_CPU_REGS_H - -#if defined(__riscv) -#include "hardware/hazard3.h" -#else -#include "hardware/regs/m33.h" -#define ARM_CPU_PREFIXED(x) M33_ ## x -#ifndef __ASSEMBLER__ -#include "hardware/structs/m33.h" -#define arm_cpu_hw m33_hw -#include "hardware/structs/nvic.h" -#include "hardware/structs/scb.h" -#endif -#endif -#endif \ No newline at end of file diff --git a/lib/main/pico-sdk/rp2350/pico_platform/platform.c b/lib/main/pico-sdk/rp2350/pico_platform/platform.c deleted file mode 100644 index 97960478fe..0000000000 --- a/lib/main/pico-sdk/rp2350/pico_platform/platform.c +++ /dev/null @@ -1,44 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "pico.h" -#include "hardware/address_mapped.h" -#include "hardware/regs/tbman.h" -#include "hardware/regs/sysinfo.h" - -// Note we leave the FPGA check in by default so that we can run bug repro -// binaries coming in from the wild on the FPGA platform. It takes up around -// 48 bytes if you include all the calls, so you can pass PICO_NO_FPGA_CHECK=1 -// to remove it. The FPGA check is used to skip initialisation of hardware -// (mainly clock generators and oscillators) that aren't present on FPGA. - -#if !PICO_NO_FPGA_CHECK -// Inline stub provided in header if this code is unused (so folding can be -// done in each TU instead of relying on LTO) -bool __attribute__((weak)) running_on_fpga(void) { - return (*(io_ro_32 *)TBMAN_BASE) & TBMAN_PLATFORM_FPGA_BITS; -} -#endif -#if !PICO_NO_SIM_CHECK -bool __attribute__((weak)) running_in_sim(void) { - return (*(io_ro_32 *)TBMAN_BASE) & TBMAN_PLATFORM_HDLSIM_BITS; -} -#endif - -#define MANUFACTURER_RPI 0x926 -#define PART_RP4 0x4 - -uint8_t rp2350_chip_version(void) { - // First register of sysinfo is chip id - uint32_t chip_id = *((io_ro_32*)(SYSINFO_BASE + SYSINFO_CHIP_ID_OFFSET)); - uint32_t __unused manufacturer = chip_id & SYSINFO_CHIP_ID_MANUFACTURER_BITS; - uint32_t __unused part = (chip_id & SYSINFO_CHIP_ID_PART_BITS) >> SYSINFO_CHIP_ID_PART_LSB; - assert(manufacturer == MANUFACTURER_RPI); - assert(part == PART_RP4); - // 0 == A0, 1 == A1, 2 == A2 - uint version = (chip_id & SYSINFO_CHIP_ID_REVISION_BITS) >> SYSINFO_CHIP_ID_REVISION_LSB; - return (uint8_t)version; -} \ No newline at end of file diff --git a/lib/main/pico-sdk/rp2350/rp2350a_interface_pins.json b/lib/main/pico-sdk/rp2350/rp2350a_interface_pins.json deleted file mode 100644 index 7869d2aada..0000000000 --- a/lib/main/pico-sdk/rp2350/rp2350a_interface_pins.json +++ /dev/null @@ -1,95 +0,0 @@ -{ - "interfaces": { - "UART": { - "instances": { - "0": { - "TX": [0, 2, 12, 14, 16, 18, 28], - "RX": [1, 3, 13, 15, 17, 19, 29], - "CTS": [2, 14, 18], - "RTS": [3, 15, 19] - }, - "1": { - "TX": [4, 6, 8, 10, 20, 22, 24, 26], - "RX": [5, 7, 9, 11, 21, 23, 25, 27], - "CTS": [6, 10, 22, 26], - "RTS": [7, 11, 23, 27] - } - }, - "expected_functions": { - "one_of": ["TX", "RX"] - } - }, - "I2C": { - "instances": { - "0": { - "SDA": [0, 4, 8, 12, 16, 20, 24, 28], - "SCL": [1, 5, 9, 13, 17, 21, 25, 29] - }, - "1": { - "SDA": [2, 6, 10, 14, 18, 22, 26], - "SCL": [3, 7, 11, 15, 19, 23, 27] - } - }, - "expected_functions": { - "required": ["SDA", "SCL"] - } - }, - "SPI": { - "instances": { - "0": { - "RX": [0, 4, 16, 20], - "CSN": [1, 5, 17, 21], - "SCK": [2, 6, 18, 22], - "TX": [3, 7, 19, 23] - }, - "1": { - "RX": [8, 12, 24, 28], - "CSN": [9, 13, 25, 29], - "SCK": [10, 14, 26], - "TX": [11, 15, 27] - } - }, - "expected_functions": { - "required": ["SCK"], - "one_of": ["RX", "TX"] - } - }, - "PWM": { - "instances": { - "0": { - "A": [0, 16], - "B": [1, 17] - }, - "1": { - "A": [2, 18], - "B": [3, 19] - }, - "2": { - "A": [4, 20], - "B": [5, 21] - }, - "3": { - "A": [6, 22], - "B": [7, 23] - }, - "4": { - "A": [8, 24], - "B": [9, 25] - }, - "5": { - "A": [10, 26], - "B": [11, 27] - }, - "6": { - "A": [12, 28], - "B": [13, 29] - }, - "7": { - "A": [14], - "B": [15] - } - } - } - }, - "pins": [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29] -} diff --git a/lib/main/pico-sdk/rp2350/rp2350b_interface_pins.json b/lib/main/pico-sdk/rp2350/rp2350b_interface_pins.json deleted file mode 100644 index ee90ad27f7..0000000000 --- a/lib/main/pico-sdk/rp2350/rp2350b_interface_pins.json +++ /dev/null @@ -1,111 +0,0 @@ -{ - "interfaces": { - "UART": { - "instances": { - "0": { - "TX": [0, 2, 12, 14, 16, 18, 28, 30, 32, 34, 44, 46], - "RX": [1, 3, 13, 15, 17, 19, 29, 31, 33, 35, 45, 47], - "CTS": [2, 14, 18, 30, 34, 46], - "RTS": [3, 15, 19, 31, 35, 47] - }, - "1": { - "TX": [4, 6, 8, 10, 20, 22, 24, 26, 36, 38, 40, 42], - "RX": [5, 7, 9, 11, 21, 23, 25, 27, 37, 39, 41, 43], - "CTS": [6, 10, 22, 26, 38, 42], - "RTS": [7, 11, 23, 27, 39, 43] - } - }, - "expected_functions": { - "one_of": ["TX", "RX"] - } - }, - "I2C": { - "instances": { - "0": { - "SDA": [0, 4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44], - "SCL": [1, 5, 9, 13, 17, 21, 25, 29, 33, 37, 41, 45] - }, - "1": { - "SDA": [2, 6, 10, 14, 18, 22, 26, 30, 34, 38, 42, 46], - "SCL": [3, 7, 11, 15, 19, 23, 27, 31, 35, 39, 43, 47] - } - }, - "expected_functions": { - "required": ["SDA", "SCL"] - } - }, - "SPI": { - "instances": { - "0": { - "RX": [0, 4, 16, 20, 32, 36], - "CSN": [1, 5, 17, 21, 33, 37], - "SCK": [2, 6, 18, 22, 34, 38], - "TX": [3, 7, 19, 23, 35, 39] - }, - "1": { - "RX": [8, 12, 24, 28, 40, 44], - "CSN": [9, 13, 25, 29, 41, 45], - "SCK": [10, 14, 26, 30, 42, 46], - "TX": [11, 15, 27, 31, 43, 47] - } - }, - "expected_functions": { - "required": ["SCK"], - "one_of": ["RX", "TX"] - } - }, - "PWM": { - "instances": { - "0": { - "A": [0, 16], - "B": [1, 17] - }, - "1": { - "A": [2, 18], - "B": [3, 19] - }, - "2": { - "A": [4, 20], - "B": [5, 21] - }, - "3": { - "A": [6, 22], - "B": [7, 23] - }, - "4": { - "A": [8, 24], - "B": [9, 25] - }, - "5": { - "A": [10, 26], - "B": [11, 27] - }, - "6": { - "A": [12, 28], - "B": [13, 29] - }, - "7": { - "A": [14, 30], - "B": [15, 31] - }, - "8": { - "A": [32, 40], - "B": [33, 41] - }, - "9": { - "A": [34, 42], - "B": [35, 43] - }, - "10": { - "A": [36, 44], - "B": [37, 45] - }, - "11": { - "A": [38, 46], - "B": [39, 47] - } - } - } - }, - "pins": [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47] -} diff --git a/lib/main/pico-sdk/rp2_common/README.md b/lib/main/pico-sdk/rp2_common/README.md deleted file mode 100644 index a598ebc5a2..0000000000 --- a/lib/main/pico-sdk/rp2_common/README.md +++ /dev/null @@ -1,7 +0,0 @@ -This directory contains libraries specifically targeting the RP2040, RP2350 and possible future related devices. - -`hardware_` libraries exist for individual hardware components to provide a simple API -providing a thin abstraction hiding the details of accessing the hardware registers directly. - -`pico_` provides higher level functionality you might generally find in say an OS kernel, as well -as runtime support familiar to most C programmers. diff --git a/lib/main/pico-sdk/rp2_common/boot_bootrom_headers/include/boot/bootrom_constants.h b/lib/main/pico-sdk/rp2_common/boot_bootrom_headers/include/boot/bootrom_constants.h deleted file mode 100644 index fcf4c652ce..0000000000 --- a/lib/main/pico-sdk/rp2_common/boot_bootrom_headers/include/boot/bootrom_constants.h +++ /dev/null @@ -1,340 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _BOOT_BOOTROM_CONSTANTS_H -#define _BOOT_BOOTROM_CONSTANTS_H - -#ifndef NO_PICO_PLATFORM -#include "pico/platform.h" -#endif - -// ROOT ADDRESSES -#define BOOTROM_MAGIC_OFFSET 0x10 -#define BOOTROM_FUNC_TABLE_OFFSET 0x14 -#if PICO_RP2040 -#define BOOTROM_DATA_TABLE_OFFSET 0x16 -#endif - -#if PICO_RP2040 -#define BOOTROM_VTABLE_OFFSET 0x00 -#define BOOTROM_TABLE_LOOKUP_OFFSET 0x18 -#else -#define BOOTROM_WELL_KNOWN_PTR_SIZE 2 -#if defined(__riscv) -#define BOOTROM_ENTRY_OFFSET 0x7dfc -#define BOOTROM_TABLE_LOOKUP_ENTRY_OFFSET (BOOTROM_ENTRY_OFFSET - BOOTROM_WELL_KNOWN_PTR_SIZE) -#define BOOTROM_TABLE_LOOKUP_OFFSET (BOOTROM_ENTRY_OFFSET - BOOTROM_WELL_KNOWN_PTR_SIZE*2) -#else -#define BOOTROM_VTABLE_OFFSET 0x00 -#define BOOTROM_TABLE_LOOKUP_OFFSET (BOOTROM_FUNC_TABLE_OFFSET + BOOTROM_WELL_KNOWN_PTR_SIZE) -#endif -#endif - -#if !PICO_RP2040 || PICO_COMBINED_DOCS - -#define BOOTROM_OK 0 -//#define BOOTROM_ERROR_TIMEOUT (-1) -//#define BOOTROM_ERROR_GENERIC (-2) -//#define BOOTROM_ERROR_NO_DATA (-3) // E.g. read from an empty buffer/FIFO -#define BOOTROM_ERROR_NOT_PERMITTED (-4) // Permission violation e.g. write to read-only flash partition -#define BOOTROM_ERROR_INVALID_ARG (-5) // Argument is outside of range of supported values` -//#define BOOTROM_ERROR_IO (-6) -//#define BOOTROM_ERROR_BADAUTH (-7) -//#define BOOTROM_ERROR_CONNECT_FAILED (-8) -//#define BOOTROM_ERROR_INSUFFICIENT_RESOURCES (-9) // Dynamic allocation of resources failed -#define BOOTROM_ERROR_INVALID_ADDRESS (-10) // Address argument was out-of-bounds or was determined to be an address that the caller may not access -#define BOOTROM_ERROR_BAD_ALIGNMENT (-11) // Address modulo transfer chunk size was nonzero (e.g. word-aligned transfer with address % 4 != 0) -#define BOOTROM_ERROR_INVALID_STATE (-12) // Something happened or failed to happen in the past, and consequently we (currently) can't service the request -#define BOOTROM_ERROR_BUFFER_TOO_SMALL (-13) // A user-allocated buffer was too small to hold the result or working state of this function -#define BOOTROM_ERROR_PRECONDITION_NOT_MET (-14) // This call failed because another ROM function must be called first -#define BOOTROM_ERROR_MODIFIED_DATA (-15) // Cached data was determined to be inconsistent with the full version of the data it was calculated from -#define BOOTROM_ERROR_INVALID_DATA (-16) // A data structure failed to validate -#define BOOTROM_ERROR_NOT_FOUND (-17) // Attempted to access something that does not exist; or, a search failed -#define BOOTROM_ERROR_UNSUPPORTED_MODIFICATION (-18) // Write is impossible based on previous writes; e.g. attempted to clear an OTP bit -#define BOOTROM_ERROR_LOCK_REQUIRED (-19) // A required lock is not owned -#define BOOTROM_ERROR_LAST (-19) - -#define RT_FLAG_FUNC_RISCV 0x0001 -#define RT_FLAG_FUNC_RISCV_FAR 0x0003 -#define RT_FLAG_FUNC_ARM_SEC 0x0004 -// reserved for 32-bit pointer: 0x0008 -#define RT_FLAG_FUNC_ARM_NONSEC 0x0010 -// reserved for 32-bit pointer: 0x0020 -#define RT_FLAG_DATA 0x0040 -// reserved for 32-bit pointer: 0x0080 - -#define PARTITION_TABLE_MAX_PARTITIONS 16 -// note this is deliberately > MAX_PARTITIONs is likely to be, and also -1 as a signed byte -#define PARTITION_TABLE_NO_PARTITION_INDEX 0xff - -// todo these are duplicated in picoboot_constants.h -// values 0-7 are secure/non-secure -#define BOOT_TYPE_NORMAL 0 -#define BOOT_TYPE_BOOTSEL 2 -#define BOOT_TYPE_RAM_IMAGE 3 -#define BOOT_TYPE_FLASH_UPDATE 4 - -// values 8-15 are secure only -#define BOOT_TYPE_PC_SP 0xd - -// ORed in if a bootloader chained into the image -#define BOOT_TYPE_CHAINED_FLAG 0x80 - -// call from NS to S -#ifndef __riscv -#define BOOTROM_API_CALLBACK_secure_call 0 -#endif -#define BOOTROM_API_CALLBACK_COUNT 1 - -#define BOOTROM_LOCK_SHA_256 0 -#define BOOTROM_LOCK_FLASH_OP 1 -#define BOOTROM_LOCK_OTP 2 -#define BOOTROM_LOCK_MAX 2 - -#define BOOTROM_LOCK_ENABLE 7 - -#define BOOT_PARTITION_NONE (-1) -#define BOOT_PARTITION_SLOT0 (-2) -#define BOOT_PARTITION_SLOT1 (-3) -#define BOOT_PARTITION_WINDOW (-4) - -#define BOOT_DIAGNOSTIC_WINDOW_SEARCHED 0x01 -// note if both BOOT_DIAGNOSTIC_INVALID_BLOCK_LOOP and BOOT_DIAGNOSTIC_VALID_BLOCK_LOOP then the block loop was valid -// but it has a PARTITION_TABLE which while it passed the initial verification (and hash/sig) had invalid contents -// (discovered when it was later loaded) -#define BOOT_DIAGNOSTIC_INVALID_BLOCK_LOOP 0x02 -#define BOOT_DIAGNOSTIC_VALID_BLOCK_LOOP 0x04 -#define BOOT_DIAGNOSTIC_VALID_IMAGE_DEF 0x08 -#define BOOT_DIAGNOSTIC_HAS_PARTITION_TABLE 0x10 -#define BOOT_DIAGNOSTIC_CONSIDERED 0x20 -#define BOOT_DIAGNOSTIC_CHOSEN 0x40 -#define BOOT_DIAGNOSTIC_PARTITION_TABLE_LSB 7 -#define BOOT_DIAGNOSTIC_PARTITION_TABLE_MATCHING_KEY_FOR_VERIFY 0x80 -#define BOOT_DIAGNOSTIC_PARTITION_TABLE_HASH_FOR_VERIFY 0x100 -#define BOOT_DIAGNOSTIC_PARTITION_TABLE_VERIFIED_OK 0x200 -#define BOOT_DIAGNOSTIC_IMAGE_DEF_LSB 10 -#define BOOT_DIAGNOSTIC_IMAGE_DEF_MATCHING_KEY_FOR_VERIFY 0x400 -#define BOOT_DIAGNOSTIC_IMAGE_DEF_HASH_FOR_VERIFY 0x800 -#define BOOT_DIAGNOSTIC_IMAGE_DEF_VERIFIED_OK 0x1000 - -#define BOOT_DIAGNOSTIC_LOAD_MAP_ENTRIES_LOADED 0x2000 -#define BOOT_DIAGNOSTIC_IMAGE_LAUNCHED 0x4000 -#define BOOT_DIAGNOSTIC_IMAGE_CONDITION_FAILURE 0x8000 - -#define BOOT_PARSED_BLOCK_DIAGNOSTIC_MATCHING_KEY_FOR_VERIFY 0x1 // if this is present and VERIFIED_OK isn't the sig check failed -#define BOOT_PARSED_BLOCK_DIAGNOSTIC_HASH_FOR_VERIFY 0x2 // if this is present and VERIFIED_OL isn't then hash check failed -#define BOOT_PARSED_BLOCK_DIAGNOSTIC_VERIFIED_OK 0x4 - -#define BOOT_TBYB_AND_UPDATE_FLAG_BUY_PENDING 0x1 -#define BOOT_TBYB_AND_UPDATE_FLAG_OTP_VERSION_APPLIED 0x2 -#define BOOT_TBYB_AND_UPDATE_FLAG_OTHER_ERASED 0x4 - -#ifndef __ASSEMBLER__ -// Limited to 3 arguments in case of varm multiplex hint (trashes Arm r3) -typedef int (*bootrom_api_callback_generic_t)(uint32_t r0, uint32_t r1, uint32_t r2); -// Return negative for error, else number of bytes transferred: -//typedef int (*bootrom_api_callback_stdout_put_blocking_t)(const uint8_t *buffer, uint32_t size); -//typedef int (*bootrom_api_callback_stdin_get_t)(uint8_t *buffer, uint32_t size); -//typedef void (*bootrom_api_callback_core1_security_setup_t)(void); -#endif - -#endif - -/*! \brief Return a bootrom lookup code based on two ASCII characters - * \ingroup pico_bootrom - * - * These codes are uses to lookup data or function addresses in the bootrom - * - * \param c1 the first character - * \param c2 the second character - * \return the 'code' to use in rom_func_lookup() or rom_data_lookup() - */ -#define ROM_TABLE_CODE(c1, c2) ((c1) | ((c2) << 8)) - -// ROM FUNCTIONS - -// RP2040 & RP2350 -#define ROM_DATA_SOFTWARE_GIT_REVISION ROM_TABLE_CODE('G', 'R') -#define ROM_FUNC_FLASH_ENTER_CMD_XIP ROM_TABLE_CODE('C', 'X') -#define ROM_FUNC_FLASH_EXIT_XIP ROM_TABLE_CODE('E', 'X') -#define ROM_FUNC_FLASH_FLUSH_CACHE ROM_TABLE_CODE('F', 'C') -#define ROM_FUNC_CONNECT_INTERNAL_FLASH ROM_TABLE_CODE('I', 'F') -#define ROM_FUNC_FLASH_RANGE_ERASE ROM_TABLE_CODE('R', 'E') -#define ROM_FUNC_FLASH_RANGE_PROGRAM ROM_TABLE_CODE('R', 'P') - - -#if PICO_RP2040 -// RP2040 only -#define ROM_FUNC_MEMCPY44 ROM_TABLE_CODE('C', '4') -#define ROM_DATA_COPYRIGHT ROM_TABLE_CODE('C', 'R') -#define ROM_FUNC_CLZ32 ROM_TABLE_CODE('L', '3') -#define ROM_FUNC_MEMCPY ROM_TABLE_CODE('M', 'C') -#define ROM_FUNC_MEMSET ROM_TABLE_CODE('M', 'S') -#define ROM_FUNC_POPCOUNT32 ROM_TABLE_CODE('P', '3') -#define ROM_FUNC_REVERSE32 ROM_TABLE_CODE('R', '3') -#define ROM_FUNC_MEMSET4 ROM_TABLE_CODE('S', '4') -#define ROM_FUNC_CTZ32 ROM_TABLE_CODE('T', '3') -#define ROM_FUNC_RESET_USB_BOOT ROM_TABLE_CODE('U', 'B') -#endif - -#if !PICO_RP2040 || PICO_COMBINED_DOCS -// RP2350 only -#define ROM_FUNC_PICK_AB_PARTITION ROM_TABLE_CODE('A', 'B') -#define ROM_FUNC_CHAIN_IMAGE ROM_TABLE_CODE('C', 'I') -#define ROM_FUNC_EXPLICIT_BUY ROM_TABLE_CODE('E', 'B') -#define ROM_FUNC_FLASH_RUNTIME_TO_STORAGE_ADDR ROM_TABLE_CODE('F', 'A') -#define ROM_DATA_FLASH_DEVINFO16_PTR ROM_TABLE_CODE('F', 'D') -#define ROM_FUNC_FLASH_OP ROM_TABLE_CODE('F', 'O') -#define ROM_FUNC_GET_B_PARTITION ROM_TABLE_CODE('G', 'B') -#define ROM_FUNC_GET_PARTITION_TABLE_INFO ROM_TABLE_CODE('G', 'P') -#define ROM_FUNC_GET_SYS_INFO ROM_TABLE_CODE('G', 'S') -#define ROM_FUNC_GET_UF2_TARGET_PARTITION ROM_TABLE_CODE('G', 'U') -#define ROM_FUNC_LOAD_PARTITION_TABLE ROM_TABLE_CODE('L', 'P') -#define ROM_FUNC_OTP_ACCESS ROM_TABLE_CODE('O', 'A') -#define ROM_DATA_PARTITION_TABLE_PTR ROM_TABLE_CODE('P', 'T') -#define ROM_FUNC_FLASH_RESET_ADDRESS_TRANS ROM_TABLE_CODE('R', 'A') -#define ROM_FUNC_REBOOT ROM_TABLE_CODE('R', 'B') -#define ROM_FUNC_SET_ROM_CALLBACK ROM_TABLE_CODE('R', 'C') -#define ROM_FUNC_SECURE_CALL ROM_TABLE_CODE('S', 'C') -#define ROM_FUNC_SET_NS_API_PERMISSION ROM_TABLE_CODE('S', 'P') -#define ROM_FUNC_BOOTROM_STATE_RESET ROM_TABLE_CODE('S', 'R') -#define ROM_FUNC_SET_BOOTROM_STACK ROM_TABLE_CODE('S', 'S') -#define ROM_DATA_SAVED_XIP_SETUP_FUNC_PTR ROM_TABLE_CODE('X', 'F') -#define ROM_FUNC_FLASH_SELECT_XIP_READ_MODE ROM_TABLE_CODE('X', 'M') -#define ROM_FUNC_VALIDATE_NS_BUFFER ROM_TABLE_CODE('V', 'B') -#endif - -// these form a bit set -#define BOOTROM_STATE_RESET_CURRENT_CORE 0x01 -#define BOOTROM_STATE_RESET_OTHER_CORE 0x02 -#define BOOTROM_STATE_RESET_GLOBAL_STATE 0x04 // reset any global state (e.g. permissions) - -// partition level stuff is returned first (note PT_INFO flags is only 16 bits) - -// 3 words: pt_count, unpartitioned_perm_loc, unpartioned_perm_flags -#define PT_INFO_PT_INFO 0x0001 -#define PT_INFO_SINGLE_PARTITION 0x8000 // marker to just include a single partition in the results) - -// then in order per partition selected - -// 2 words: unpartitioned_perm_loc, unpartioned_perm_flags -#define PT_INFO_PARTITION_LOCATION_AND_FLAGS 0x0010 -// 2 words: id lsb first -#define PT_INFO_PARTITION_ID 0x0020 -// n+1 words: n, family_id... -#define PT_INFO_PARTITION_FAMILY_IDS 0x0040 -// (n+3)/4 words... bytes are: n (len), c0, c1, ... cn-1 padded to word boundary with zeroes -#define PT_INFO_PARTITION_NAME 0x0080 - -// items are returned in order -// 3 words package_id, device_id, wafer_id -#define SYS_INFO_CHIP_INFO 0x0001 -// 1 word: chip specific critical bits -#define SYS_INFO_CRITICAL 0x0002 -// 1 word: bytes: cpu_type, supported_cpu_type_bitfield -#define SYS_INFO_CPU_INFO 0x0004 -// 1 word: same as FLASH_DEVINFO row in OTP -#define SYS_INFO_FLASH_DEV_INFO 0x0008 -// 4 words -#define SYS_INFO_BOOT_RANDOM 0x0010 -// 2 words lsb first -#define SYS_INFO_NONCE 0x0020 -// 4 words boot_info, boot_diagnostic, boot_param0, boot_param1 -#define SYS_INFO_BOOT_INFO 0x0040 - -#define BOOTROM_NS_API_get_sys_info 0 -#define BOOTROM_NS_API_checked_flash_op 1 -#define BOOTROM_NS_API_flash_runtime_to_storage_addr 2 -#define BOOTROM_NS_API_get_partition_table_info 3 -#define BOOTROM_NS_API_secure_call 4 -#define BOOTROM_NS_API_otp_access 5 -#define BOOTROM_NS_API_reboot 6 -#define BOOTROM_NS_API_get_b_partition 7 -#define BOOTROM_NS_API_COUNT 8 - -#ifndef __ASSEMBLER__ - -typedef struct { - uint32_t permissions_and_location; - uint32_t permissions_and_flags; -} resident_partition_t; -static_assert(sizeof(resident_partition_t) == 8, ""); - -#define OTP_CMD_ROW_BITS 0x0000ffffu -#define OTP_CMD_ROW_LSB 0u -#define OTP_CMD_WRITE_BITS 0x00010000u -#define OTP_CMD_ECC_BITS 0x00020000u - -typedef struct otp_cmd { - uint32_t flags; -} otp_cmd_t; - -typedef enum { - BOOTROM_XIP_MODE_03H_SERIAL = 0, - BOOTROM_XIP_MODE_0BH_SERIAL, - BOOTROM_XIP_MODE_BBH_DUAL, - BOOTROM_XIP_MODE_EBH_QUAD, - BOOTROM_XIP_MODE_N_MODES -} bootrom_xip_mode_t; - -// The checked flash API wraps the low-level flash routines from generic_flash, adding bounds -// checking, permission checking against the resident partition table, and simple address -// translation. The low-level API deals with flash offsets (i.e. distance from the start of the -// first flash device, measured in bytes) but the checked flash API accepts one of two types of -// address: -// -// - Flash runtime addresses: the address of some flash-resident data or code in the currently -// running image. The flash addresses your binary is "linked at" by the linker. -// - Flash storage addresses: a flash offset, plus the address base where QSPI hardware is first -// mapped on the system bus (XIP_BASE constant from addressmap.h) -// -// These addresses are one and the same *if* the currently running program is stored at the -// beginning of flash. They are different if the start of your image has been "rolled" by the flash -// boot path to make it appear at the address it was linked at even though it is stored at a -// different location in flash, which is necessary when you have A/B images for example. -// -// The address translation between flash runtime and flash storage addresses is configured in -// hardware by the QMI_ATRANSx registers, and this API assumes those registers contain a valid -// address mapping which it can use to translate runtime to storage addresses. - -typedef struct cflash_flags { - uint32_t flags; -} cflash_flags_t; - -// Bits which are permitted to be set in a flags variable -- any other bits being set is an error -#define CFLASH_FLAGS_BITS 0x00070301u - -// Used to tell checked flash API which space a given address belongs to -#define CFLASH_ASPACE_BITS 0x00000001u -#define CFLASH_ASPACE_LSB 0u -#define CFLASH_ASPACE_VALUE_STORAGE 0u -#define CFLASH_ASPACE_VALUE_RUNTIME 1u - -// Used to tell checked flash APIs the effective security level of a flash access (may be forced to -// one of these values for the NonSecure-exported version of this API) -#define CFLASH_SECLEVEL_BITS 0x00000300u -#define CFLASH_SECLEVEL_LSB 8u -// Zero is not a valid security level: -#define CFLASH_SECLEVEL_VALUE_SECURE 1u -#define CFLASH_SECLEVEL_VALUE_NONSECURE 2u -#define CFLASH_SECLEVEL_VALUE_BOOTLOADER 3u - -#define CFLASH_OP_BITS 0x00070000u -#define CFLASH_OP_LSB 16u -// Erase size_bytes bytes of flash, starting at address addr. Both addr and size_bytes must be a -// multiple of 4096 bytes (one flash sector). -#define CFLASH_OP_VALUE_ERASE 0u -// Program size_bytes bytes of flash, starting at address addr. Both addr and size_bytes must be a -// multiple of 256 bytes (one flash page). -#define CFLASH_OP_VALUE_PROGRAM 1u -// Read size_bytes bytes of flash, starting at address addr. There are no alignment restrictions on -// addr or size_bytes. -#define CFLASH_OP_VALUE_READ 2u -#define CFLASH_OP_MAX 2u - -#endif - -#endif diff --git a/lib/main/pico-sdk/rp2_common/cmsis/include/cmsis/rename_exceptions.h b/lib/main/pico-sdk/rp2_common/cmsis/include/cmsis/rename_exceptions.h deleted file mode 100644 index 0db37f4cac..0000000000 --- a/lib/main/pico-sdk/rp2_common/cmsis/include/cmsis/rename_exceptions.h +++ /dev/null @@ -1,106 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _CMSIS_RENAME_EXCEPTIONS_H -#define _CMSIS_RENAME_EXCEPTIONS_H - -#if LIB_CMSIS_CORE -// PICO_CONFIG: PICO_CMSIS_RENAME_EXCEPTIONS, Whether to rename SDK exceptions such as isr_nmi to their CMSIS equivalent i.e. NMI_Handler, type=bool, default=1, group=cmsis_core - -// Note that since this header is included at the config stage, if you wish to override this you should do so via build compiler define -#ifndef PICO_CMSIS_RENAME_EXCEPTIONS -#define PICO_CMSIS_RENAME_EXCEPTIONS 1 -#endif - -#if PICO_CMSIS_RENAME_EXCEPTIONS -#if PICO_RP2040 -#define isr_nmi NMI_Handler -#define isr_hardfault HardFault_Handler -#define isr_svcall SVC_Handler -#define isr_pendsv PendSV_Handler -#define isr_systick SysTick_Handler -#define isr_irq0 TIMER_IRQ_0_Handler -#define isr_irq1 TIMER_IRQ_1_Handler -#define isr_irq2 TIMER_IRQ_2_Handler -#define isr_irq3 TIMER_IRQ_3_Handler -#define isr_irq4 PWM_IRQ_WRAP_Handler -#define isr_irq5 USBCTRL_IRQ_Handler -#define isr_irq6 XIP_IRQ_Handler -#define isr_irq7 PIO0_IRQ_0_Handler -#define isr_irq8 PIO0_IRQ_1_Handler -#define isr_irq9 PIO1_IRQ_0_Handler -#define isr_irq10 PIO1_IRQ_1_Handler -#define isr_irq11 DMA_IRQ_0_Handler -#define isr_irq12 DMA_IRQ_1_Handler -#define isr_irq13 IO_IRQ_BANK0_Handler -#define isr_irq14 IO_IRQ_QSPI_Handler -#define isr_irq15 SIO_IRQ_PROC0_Handler -#define isr_irq16 SIO_IRQ_PROC1_Handler -#define isr_irq17 CLOCKS_IRQ_Handler -#define isr_irq18 SPI0_IRQ_Handler -#define isr_irq19 SPI1_IRQ_Handler -#define isr_irq20 UART0_IRQ_Handler -#define isr_irq21 UART1_IRQ_Handler -#define isr_irq22 ADC_IRQ_FIFO_Handler -#define isr_irq23 I2C0_IRQ_Handler -#define isr_irq24 I2C1_IRQ_Handler -#define isr_irq25 RTC_IRQ_Handler -#endif -#if PICO_RP2350 -#define isr_nmi NMI_Handler -#define isr_hardfault HardFault_Handler -#define isr_svcall SVC_Handler -#define isr_pendsv PendSV_Handler -#define isr_systick SysTick_Handler -#define isr_irq0 TIMER0_IRQ_0_Handler -#define isr_irq1 TIMER0_IRQ_1_Handler -#define isr_irq2 TIMER0_IRQ_2_Handler -#define isr_irq3 TIMER0_IRQ_3_Handler -#define isr_irq4 TIMER1_IRQ_0_Handler -#define isr_irq5 TIMER1_IRQ_1_Handler -#define isr_irq6 TIMER1_IRQ_2_Handler -#define isr_irq7 TIMER1_IRQ_3_Handler -#define isr_irq8 PWM_IRQ_WRAP_0_Handler -#define isr_irq9 PWM_IRQ_WRAP_1_Handler -#define isr_irq10 DMA_IRQ_0_Handler -#define isr_irq11 DMA_IRQ_1_Handler -#define isr_irq12 DMA_IRQ_2_Handler -#define isr_irq13 DMA_IRQ_3_Handler -#define isr_irq14 USBCTRL_IRQ_Handler -#define isr_irq15 PIO0_IRQ_0_Handler -#define isr_irq16 PIO0_IRQ_1_Handler -#define isr_irq17 PIO1_IRQ_0_Handler -#define isr_irq18 PIO1_IRQ_1_Handler -#define isr_irq19 PIO2_IRQ_0_Handler -#define isr_irq20 PIO2_IRQ_1_Handler -#define isr_irq21 IO_IRQ_BANK0_Handler -#define isr_irq22 IO_IRQ_BANK0_NS_Handler -#define isr_irq23 IO_IRQ_QSPI_Handler -#define isr_irq24 IO_IRQ_QSPI_NS_Handler -#define isr_irq25 SIO_IRQ_FIFO_Handler -#define isr_irq26 SIO_IRQ_BELL_Handler -#define isr_irq27 SIO_IRQ_FIFO_NS_Handler -#define isr_irq28 SIO_IRQ_BELL_NS_Handler -#define isr_irq29 SIO_IRQ_MTIMECMP_Handler -#define isr_irq30 CLOCKS_IRQ_Handler -#define isr_irq31 SPI0_IRQ_Handler -#define isr_irq32 SPI1_IRQ_Handler -#define isr_irq33 UART0_IRQ_Handler -#define isr_irq34 UART1_IRQ_Handler -#define isr_irq35 ADC_IRQ_FIFO_Handler -#define isr_irq36 I2C0_IRQ_Handler -#define isr_irq37 I2C1_IRQ_Handler -#define isr_irq38 OTP_IRQ_Handler -#define isr_irq39 TRNG_IRQ_Handler -#define isr_irq42 PLL_SYS_IRQ_Handler -#define isr_irq43 PLL_USB_IRQ_Handler -#define isr_irq44 POWMAN_IRQ_POW_Handler -#define isr_irq45 POWMAN_IRQ_TIMER_Handler -#endif -#endif - -#endif -#endif /* _CMSIS_RENAME_EXCEPTIONS_H */ diff --git a/lib/main/pico-sdk/rp2_common/cmsis/stub/CMSIS/Core/Include/cmsis_armcc.h b/lib/main/pico-sdk/rp2_common/cmsis/stub/CMSIS/Core/Include/cmsis_armcc.h deleted file mode 100644 index 237ff6ec3e..0000000000 --- a/lib/main/pico-sdk/rp2_common/cmsis/stub/CMSIS/Core/Include/cmsis_armcc.h +++ /dev/null @@ -1,885 +0,0 @@ -/**************************************************************************//** - * @file cmsis_armcc.h - * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file - * @version V5.2.1 - * @date 26. March 2020 - ******************************************************************************/ -/* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __CMSIS_ARMCC_H -#define __CMSIS_ARMCC_H - - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) - #error "Please use Arm Compiler Toolchain V4.0.677 or later!" -#endif - -/* CMSIS compiler control architecture macros */ -#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \ - (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) ) - #define __ARM_ARCH_6M__ 1 -#endif - -#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1)) - #define __ARM_ARCH_7M__ 1 -#endif - -#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1)) - #define __ARM_ARCH_7EM__ 1 -#endif - - /* __ARM_ARCH_8M_BASE__ not applicable */ - /* __ARM_ARCH_8M_MAIN__ not applicable */ - /* __ARM_ARCH_8_1M_MAIN__ not applicable */ - -/* CMSIS compiler control DSP macros */ -#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) - #define __ARM_FEATURE_DSP 1 -#endif - -/* CMSIS compiler specific defines */ -#ifndef __ASM - #define __ASM __asm -#endif -#ifndef __INLINE - #define __INLINE __inline -#endif -#ifndef __STATIC_INLINE - #define __STATIC_INLINE static __inline -#endif -#ifndef __STATIC_FORCEINLINE - #define __STATIC_FORCEINLINE static __forceinline -#endif -#ifndef __NO_RETURN - #define __NO_RETURN __declspec(noreturn) -#endif -#ifndef __USED - #define __USED __attribute__((used)) -#endif -#ifndef __WEAK - #define __WEAK __attribute__((weak)) -#endif -#ifndef __PACKED - #define __PACKED __attribute__((packed)) -#endif -#ifndef __PACKED_STRUCT - #define __PACKED_STRUCT __packed struct -#endif -#ifndef __PACKED_UNION - #define __PACKED_UNION __packed union -#endif -#ifndef __UNALIGNED_UINT32 /* deprecated */ - #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x))) -#endif -#ifndef __UNALIGNED_UINT16_WRITE - #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val)) -#endif -#ifndef __UNALIGNED_UINT16_READ - #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr))) -#endif -#ifndef __UNALIGNED_UINT32_WRITE - #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val)) -#endif -#ifndef __UNALIGNED_UINT32_READ - #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr))) -#endif -#ifndef __ALIGNED - #define __ALIGNED(x) __attribute__((aligned(x))) -#endif -#ifndef __RESTRICT - #define __RESTRICT __restrict -#endif -#ifndef __COMPILER_BARRIER - #define __COMPILER_BARRIER() __memory_changed() -#endif - -/* ######################### Startup and Lowlevel Init ######################## */ - -#ifndef __PROGRAM_START -#define __PROGRAM_START __main -#endif - -#ifndef __INITIAL_SP -#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit -#endif - -#ifndef __STACK_LIMIT -#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base -#endif - -#ifndef __VECTOR_TABLE -#define __VECTOR_TABLE __Vectors -#endif - -#ifndef __VECTOR_TABLE_ATTRIBUTE -#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) -#endif - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -/** - \brief Enable IRQ Interrupts - \details Enables IRQ interrupts by clearing the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -/* intrinsic void __enable_irq(); */ - - -/** - \brief Disable IRQ Interrupts - \details Disables IRQ interrupts by setting the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -/* intrinsic void __disable_irq(); */ - -/** - \brief Get Control Register - \details Returns the content of the Control Register. - \return Control Register value - */ -__STATIC_INLINE uint32_t __get_CONTROL(void) -{ - register uint32_t __regControl __ASM("control"); - return(__regControl); -} - - -/** - \brief Set Control Register - \details Writes the given value to the Control Register. - \param [in] control Control Register value to set - */ -__STATIC_INLINE void __set_CONTROL(uint32_t control) -{ - register uint32_t __regControl __ASM("control"); - __regControl = control; -} - - -/** - \brief Get IPSR Register - \details Returns the content of the IPSR Register. - \return IPSR Register value - */ -__STATIC_INLINE uint32_t __get_IPSR(void) -{ - register uint32_t __regIPSR __ASM("ipsr"); - return(__regIPSR); -} - - -/** - \brief Get APSR Register - \details Returns the content of the APSR Register. - \return APSR Register value - */ -__STATIC_INLINE uint32_t __get_APSR(void) -{ - register uint32_t __regAPSR __ASM("apsr"); - return(__regAPSR); -} - - -/** - \brief Get xPSR Register - \details Returns the content of the xPSR Register. - \return xPSR Register value - */ -__STATIC_INLINE uint32_t __get_xPSR(void) -{ - register uint32_t __regXPSR __ASM("xpsr"); - return(__regXPSR); -} - - -/** - \brief Get Process Stack Pointer - \details Returns the current value of the Process Stack Pointer (PSP). - \return PSP Register value - */ -__STATIC_INLINE uint32_t __get_PSP(void) -{ - register uint32_t __regProcessStackPointer __ASM("psp"); - return(__regProcessStackPointer); -} - - -/** - \brief Set Process Stack Pointer - \details Assigns the given value to the Process Stack Pointer (PSP). - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) -{ - register uint32_t __regProcessStackPointer __ASM("psp"); - __regProcessStackPointer = topOfProcStack; -} - - -/** - \brief Get Main Stack Pointer - \details Returns the current value of the Main Stack Pointer (MSP). - \return MSP Register value - */ -__STATIC_INLINE uint32_t __get_MSP(void) -{ - register uint32_t __regMainStackPointer __ASM("msp"); - return(__regMainStackPointer); -} - - -/** - \brief Set Main Stack Pointer - \details Assigns the given value to the Main Stack Pointer (MSP). - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) -{ - register uint32_t __regMainStackPointer __ASM("msp"); - __regMainStackPointer = topOfMainStack; -} - - -/** - \brief Get Priority Mask - \details Returns the current state of the priority mask bit from the Priority Mask Register. - \return Priority Mask value - */ -__STATIC_INLINE uint32_t __get_PRIMASK(void) -{ - register uint32_t __regPriMask __ASM("primask"); - return(__regPriMask); -} - - -/** - \brief Set Priority Mask - \details Assigns the given value to the Priority Mask Register. - \param [in] priMask Priority Mask - */ -__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) -{ - register uint32_t __regPriMask __ASM("primask"); - __regPriMask = (priMask); -} - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) - -/** - \brief Enable FIQ - \details Enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __enable_fault_irq __enable_fiq - - -/** - \brief Disable FIQ - \details Disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __disable_fault_irq __disable_fiq - - -/** - \brief Get Base Priority - \details Returns the current value of the Base Priority register. - \return Base Priority register value - */ -__STATIC_INLINE uint32_t __get_BASEPRI(void) -{ - register uint32_t __regBasePri __ASM("basepri"); - return(__regBasePri); -} - - -/** - \brief Set Base Priority - \details Assigns the given value to the Base Priority register. - \param [in] basePri Base Priority value to set - */ -__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) -{ - register uint32_t __regBasePri __ASM("basepri"); - __regBasePri = (basePri & 0xFFU); -} - - -/** - \brief Set Base Priority with condition - \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, - or the new value increases the BASEPRI priority level. - \param [in] basePri Base Priority value to set - */ -__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) -{ - register uint32_t __regBasePriMax __ASM("basepri_max"); - __regBasePriMax = (basePri & 0xFFU); -} - - -/** - \brief Get Fault Mask - \details Returns the current value of the Fault Mask register. - \return Fault Mask register value - */ -__STATIC_INLINE uint32_t __get_FAULTMASK(void) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - return(__regFaultMask); -} - - -/** - \brief Set Fault Mask - \details Assigns the given value to the Fault Mask register. - \param [in] faultMask Fault Mask value to set - */ -__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - __regFaultMask = (faultMask & (uint32_t)1U); -} - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ - - -/** - \brief Get FPSCR - \details Returns the current value of the Floating Point Status/Control register. - \return Floating Point Status/Control register value - */ -__STATIC_INLINE uint32_t __get_FPSCR(void) -{ -#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) - register uint32_t __regfpscr __ASM("fpscr"); - return(__regfpscr); -#else - return(0U); -#endif -} - - -/** - \brief Set FPSCR - \details Assigns the given value to the Floating Point Status/Control register. - \param [in] fpscr Floating Point Status/Control value to set - */ -__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) - register uint32_t __regfpscr __ASM("fpscr"); - __regfpscr = (fpscr); -#else - (void)fpscr; -#endif -} - - -/*@} end of CMSIS_Core_RegAccFunctions */ - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -/** - \brief No Operation - \details No Operation does nothing. This instruction can be used for code alignment purposes. - */ -#define __NOP __nop - - -/** - \brief Wait For Interrupt - \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. - */ -#define __WFI __wfi - - -/** - \brief Wait For Event - \details Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -#define __WFE __wfe - - -/** - \brief Send Event - \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -#define __SEV __sev - - -/** - \brief Instruction Synchronization Barrier - \details Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or memory, - after the instruction has been completed. - */ -#define __ISB() __isb(0xF) - -/** - \brief Data Synchronization Barrier - \details Acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -#define __DSB() __dsb(0xF) - -/** - \brief Data Memory Barrier - \details Ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -#define __DMB() __dmb(0xF) - - -/** - \brief Reverse byte order (32 bit) - \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV __rev - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. - \param [in] value Value to reverse - \return Reversed value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) -{ - rev16 r0, r0 - bx lr -} -#endif - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. - \param [in] value Value to reverse - \return Reversed value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value) -{ - revsh r0, r0 - bx lr -} -#endif - - -/** - \brief Rotate Right in unsigned value (32 bit) - \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - \param [in] op1 Value to rotate - \param [in] op2 Number of Bits to rotate - \return Rotated value - */ -#define __ROR __ror - - -/** - \brief Breakpoint - \details Causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __breakpoint(value) - - -/** - \brief Reverse bit order of value - \details Reverses the bit order of the given value. - \param [in] value Value to reverse - \return Reversed value - */ -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) - #define __RBIT __rbit -#else -__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) -{ - uint32_t result; - uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ - - result = value; /* r will be reversed bits of v; first get LSB of v */ - for (value >>= 1U; value != 0U; value >>= 1U) - { - result <<= 1U; - result |= value & 1U; - s--; - } - result <<= s; /* shift when v's highest bits are zero */ - return result; -} -#endif - - -/** - \brief Count leading zeros - \details Counts the number of leading zeros of a data value. - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -#define __CLZ __clz - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) - -/** - \brief LDR Exclusive (8 bit) - \details Executes a exclusive LDR instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) -#else - #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") -#endif - - -/** - \brief LDR Exclusive (16 bit) - \details Executes a exclusive LDR instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) -#else - #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") -#endif - - -/** - \brief LDR Exclusive (32 bit) - \details Executes a exclusive LDR instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) -#else - #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") -#endif - - -/** - \brief STR Exclusive (8 bit) - \details Executes a exclusive STR instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __STREXB(value, ptr) __strex(value, ptr) -#else - #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") -#endif - - -/** - \brief STR Exclusive (16 bit) - \details Executes a exclusive STR instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __STREXH(value, ptr) __strex(value, ptr) -#else - #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") -#endif - - -/** - \brief STR Exclusive (32 bit) - \details Executes a exclusive STR instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __STREXW(value, ptr) __strex(value, ptr) -#else - #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") -#endif - - -/** - \brief Remove the exclusive lock - \details Removes the exclusive lock which is created by LDREX. - */ -#define __CLREX __clrex - - -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT __ssat - - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT __usat - - -/** - \brief Rotate Right with Extend (32 bit) - \details Moves each bit of a bitstring right by one bit. - The carry input is shifted in at the left end of the bitstring. - \param [in] value Value to rotate - \return Rotated value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) -{ - rrx r0, r0 - bx lr -} -#endif - - -/** - \brief LDRT Unprivileged (8 bit) - \details Executes a Unprivileged LDRT instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) - - -/** - \brief LDRT Unprivileged (16 bit) - \details Executes a Unprivileged LDRT instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) - - -/** - \brief LDRT Unprivileged (32 bit) - \details Executes a Unprivileged LDRT instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) - - -/** - \brief STRT Unprivileged (8 bit) - \details Executes a Unprivileged STRT instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -#define __STRBT(value, ptr) __strt(value, ptr) - - -/** - \brief STRT Unprivileged (16 bit) - \details Executes a Unprivileged STRT instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -#define __STRHT(value, ptr) __strt(value, ptr) - - -/** - \brief STRT Unprivileged (32 bit) - \details Executes a Unprivileged STRT instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -#define __STRT(value, ptr) __strt(value, ptr) - -#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ - -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) -{ - if ((sat >= 1U) && (sat <= 32U)) - { - const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); - const int32_t min = -1 - max ; - if (val > max) - { - return max; - } - else if (val < min) - { - return min; - } - } - return val; -} - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) -{ - if (sat <= 31U) - { - const uint32_t max = ((1U << sat) - 1U); - if (val > (int32_t)max) - { - return max; - } - else if (val < 0) - { - return 0U; - } - } - return (uint32_t)val; -} - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - - -/* ################### Compiler specific Intrinsics ########################### */ -/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics - Access to dedicated SIMD instructions - @{ -*/ - -#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) - -#define __SADD8 __sadd8 -#define __QADD8 __qadd8 -#define __SHADD8 __shadd8 -#define __UADD8 __uadd8 -#define __UQADD8 __uqadd8 -#define __UHADD8 __uhadd8 -#define __SSUB8 __ssub8 -#define __QSUB8 __qsub8 -#define __SHSUB8 __shsub8 -#define __USUB8 __usub8 -#define __UQSUB8 __uqsub8 -#define __UHSUB8 __uhsub8 -#define __SADD16 __sadd16 -#define __QADD16 __qadd16 -#define __SHADD16 __shadd16 -#define __UADD16 __uadd16 -#define __UQADD16 __uqadd16 -#define __UHADD16 __uhadd16 -#define __SSUB16 __ssub16 -#define __QSUB16 __qsub16 -#define __SHSUB16 __shsub16 -#define __USUB16 __usub16 -#define __UQSUB16 __uqsub16 -#define __UHSUB16 __uhsub16 -#define __SASX __sasx -#define __QASX __qasx -#define __SHASX __shasx -#define __UASX __uasx -#define __UQASX __uqasx -#define __UHASX __uhasx -#define __SSAX __ssax -#define __QSAX __qsax -#define __SHSAX __shsax -#define __USAX __usax -#define __UQSAX __uqsax -#define __UHSAX __uhsax -#define __USAD8 __usad8 -#define __USADA8 __usada8 -#define __SSAT16 __ssat16 -#define __USAT16 __usat16 -#define __UXTB16 __uxtb16 -#define __UXTAB16 __uxtab16 -#define __SXTB16 __sxtb16 -#define __SXTAB16 __sxtab16 -#define __SMUAD __smuad -#define __SMUADX __smuadx -#define __SMLAD __smlad -#define __SMLADX __smladx -#define __SMLALD __smlald -#define __SMLALDX __smlaldx -#define __SMUSD __smusd -#define __SMUSDX __smusdx -#define __SMLSD __smlsd -#define __SMLSDX __smlsdx -#define __SMLSLD __smlsld -#define __SMLSLDX __smlsldx -#define __SEL __sel -#define __QADD __qadd -#define __QSUB __qsub - -#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ - ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) - -#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ - ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) - -#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ - ((int64_t)(ARG3) << 32U) ) >> 32U)) - -#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) - -#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ -/*@} end of group CMSIS_SIMD_intrinsics */ - - -#endif /* __CMSIS_ARMCC_H */ diff --git a/lib/main/pico-sdk/rp2_common/cmsis/stub/CMSIS/Core/Include/cmsis_armclang.h b/lib/main/pico-sdk/rp2_common/cmsis/stub/CMSIS/Core/Include/cmsis_armclang.h deleted file mode 100644 index 446d21a918..0000000000 --- a/lib/main/pico-sdk/rp2_common/cmsis/stub/CMSIS/Core/Include/cmsis_armclang.h +++ /dev/null @@ -1,707 +0,0 @@ -/**************************************************************************//** - * @file cmsis_armclang.h - * @brief CMSIS compiler armclang (Arm Compiler 6) header file - * @version V6.0.0 - * @date 27. July 2024 - ******************************************************************************/ -/* - * Copyright (c) 2009-2023 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __CMSIS_ARMCLANG_H -#define __CMSIS_ARMCLANG_H - -#pragma clang system_header /* treat file as system include file */ - -#if (__ARM_ACLE >= 200) - #include -#else - #error Compiler must support ACLE V2.0 -#endif /* (__ARM_ACLE >= 200) */ - -/* CMSIS compiler specific defines */ -#ifndef __ASM - #define __ASM __asm -#endif -#ifndef __INLINE - #define __INLINE inline -#endif -#ifndef __STATIC_INLINE - #define __STATIC_INLINE static inline -#endif -#ifndef __STATIC_FORCEINLINE - #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline -#endif -#ifndef __NO_RETURN - #define __NO_RETURN __attribute__((__noreturn__)) -#endif -#ifndef CMSIS_DEPRECATED - #define CMSIS_DEPRECATED __attribute__((deprecated)) -#endif -#ifndef __USED - #define __USED __attribute__((used)) -#endif -#ifndef __WEAK - #define __WEAK __attribute__((weak)) -#endif -#ifndef __PACKED - #define __PACKED __attribute__((packed, aligned(1))) -#endif -#ifndef __PACKED_STRUCT - #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) -#endif -#ifndef __PACKED_UNION - #define __PACKED_UNION union __attribute__((packed, aligned(1))) -#endif -#ifndef __UNALIGNED_UINT16_WRITE - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wpacked" - __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; - #pragma clang diagnostic pop - #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) -#endif -#ifndef __UNALIGNED_UINT16_READ - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wpacked" - __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; - #pragma clang diagnostic pop - #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) -#endif -#ifndef __UNALIGNED_UINT32_WRITE - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wpacked" - __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; - #pragma clang diagnostic pop - #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) -#endif -#ifndef __UNALIGNED_UINT32_READ - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wpacked" - __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; - #pragma clang diagnostic pop - #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) -#endif -#ifndef __ALIGNED - #define __ALIGNED(x) __attribute__((aligned(x))) -#endif -#ifndef __RESTRICT - #define __RESTRICT __restrict -#endif -#ifndef __COMPILER_BARRIER - #define __COMPILER_BARRIER() __ASM volatile("":::"memory") -#endif -#ifndef __NO_INIT - #define __NO_INIT __attribute__ ((section (".bss.noinit"))) -#endif -#ifndef __ALIAS - #define __ALIAS(x) __attribute__ ((alias(x))) -#endif - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -/* Define macros for porting to both thumb1 and thumb2. - * For thumb1, use low register (r0-r7), specified by constraint "l" - * Otherwise, use general registers, specified by constraint "r" */ -#if defined (__thumb__) && !defined (__thumb2__) -#define __CMSIS_GCC_OUT_REG(r) "=l" (r) -#define __CMSIS_GCC_RW_REG(r) "+l" (r) -#define __CMSIS_GCC_USE_REG(r) "l" (r) -#else -#define __CMSIS_GCC_OUT_REG(r) "=r" (r) -#define __CMSIS_GCC_RW_REG(r) "+r" (r) -#define __CMSIS_GCC_USE_REG(r) "r" (r) -#endif - -/** - \brief No Operation - \details No Operation does nothing. This instruction can be used for code alignment purposes. - */ -#define __NOP() __nop() - - -/** - \brief Wait For Interrupt - \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. - */ -#define __WFI() __wfi() - - -/** - \brief Wait For Event - \details Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -#define __WFE() __wfe() - - -/** - \brief Send Event - \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -#define __SEV() __sev() - - -/** - \brief Instruction Synchronization Barrier - \details Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or memory, - after the instruction has been completed. - */ -#define __ISB() __isb(0xF) - - -/** - \brief Data Synchronization Barrier - \details Acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -#define __DSB() __dsb(0xF) - - -/** - \brief Data Memory Barrier - \details Ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -#define __DMB() __dmb(0xF) - - -/** - \brief Reverse byte order (32 bit) - \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV(value) __rev(value) - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV16(value) __rev16(value) - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. - \param [in] value Value to reverse - \return Reversed value - */ -#define __REVSH(value) __revsh(value) - - -/** - \brief Rotate Right in unsigned value (32 bit) - \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - \param [in] op1 Value to rotate - \param [in] op2 Number of Bits to rotate - \return Rotated value - */ -#define __ROR(op1, op2) __ror(op1, op2) - - -/** - \brief Breakpoint - \details Causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __ASM volatile ("bkpt "#value) - - -/** - \brief Reverse bit order of value - \details Reverses the bit order of the given value. - \param [in] value Value to reverse - \return Reversed value - */ -#define __RBIT(value) __rbit(value) - - -/** - \brief Count leading zeros - \details Counts the number of leading zeros of a data value. - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -#define __CLZ(value) __clz(value) - - -#if ((__ARM_FEATURE_SAT >= 1) && \ - (__ARM_ARCH_ISA_THUMB >= 2) ) -/* __ARM_FEATURE_SAT is wrong for Armv8-M Baseline devices */ -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT(value, sat) __ssat(value, sat) - - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT(value, sat) __usat(value, sat) - -#else /* (__ARM_FEATURE_SAT >= 1) */ -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) -{ - if ((sat >= 1U) && (sat <= 32U)) - { - const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); - const int32_t min = -1 - max ; - if (val > max) - { - return (max); - } - else if (val < min) - { - return (min); - } - } - return (val); -} - - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) -{ - if (sat <= 31U) - { - const uint32_t max = ((1U << sat) - 1U); - if (val > (int32_t)max) - { - return (max); - } - else if (val < 0) - { - return (0U); - } - } - return ((uint32_t)val); -} -#endif /* (__ARM_FEATURE_SAT >= 1) */ - - -#if (__ARM_FEATURE_LDREX >= 1) -/** - \brief Remove the exclusive lock - \details Removes the exclusive lock which is created by LDREX. - */ -#define __CLREX __builtin_arm_clrex - - -/** - \brief LDR Exclusive (8 bit) - \details Executes a exclusive LDR instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDREXB (uint8_t)__builtin_arm_ldrex - - -/** - \brief STR Exclusive (8 bit) - \details Executes a exclusive STR instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXB (uint32_t)__builtin_arm_strex -#endif /* (__ARM_FEATURE_LDREX >= 1) */ - - -#if (__ARM_FEATURE_LDREX >= 2) -/** - \brief LDR Exclusive (16 bit) - \details Executes a exclusive LDR instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDREXH (uint16_t)__builtin_arm_ldrex - - -/** - \brief STR Exclusive (16 bit) - \details Executes a exclusive STR instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXH (uint32_t)__builtin_arm_strex -#endif /* (__ARM_FEATURE_LDREX >= 2) */ - - -#if (__ARM_FEATURE_LDREX >= 4) -/** - \brief LDR Exclusive (32 bit) - \details Executes a exclusive LDR instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDREXW (uint32_t)__builtin_arm_ldrex - - -/** - \brief STR Exclusive (32 bit) - \details Executes a exclusive STR instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXW (uint32_t)__builtin_arm_strex -#endif /* (__ARM_FEATURE_LDREX >= 4) */ - - -#if (__ARM_ARCH_ISA_THUMB >= 2) -/** - \brief Rotate Right with Extend (32 bit) - \details Moves each bit of a bitstring right by one bit. - The carry input is shifted in at the left end of the bitstring. - \param [in] value Value to rotate - \return Rotated value - */ -__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rrx %0, %1" : "=r" (result) : "r" (value)); - return (result); -} - - -/** - \brief LDRT Unprivileged (8 bit) - \details Executes a Unprivileged LDRT instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint8_t)result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (16 bit) - \details Executes a Unprivileged LDRT instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint16_t)result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (32 bit) - \details Executes a Unprivileged LDRT instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); - return (result); -} -#endif /* (__ARM_ARCH_ISA_THUMB >= 2) */ - - -#if (__ARM_ARCH >= 8) -/** - \brief Load-Acquire (8 bit) - \details Executes a LDAB instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); - return ((uint8_t)result); /* Add explicit type cast here */ -} - - -/** - \brief Load-Acquire (16 bit) - \details Executes a LDAH instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); - return ((uint16_t)result); /* Add explicit type cast here */ -} - - -/** - \brief Load-Acquire (32 bit) - \details Executes a LDA instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); - return (result); -} - - -/** - \brief Store-Release (8 bit) - \details Executes a STLB instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) -{ - __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); -} - - -/** - \brief Store-Release (16 bit) - \details Executes a STLH instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) -{ - __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); -} - - -/** - \brief Store-Release (32 bit) - \details Executes a STL instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) -{ - __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); -} - - -/** - \brief Load-Acquire Exclusive (8 bit) - \details Executes a LDAB exclusive instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDAEXB (uint8_t)__builtin_arm_ldaex - - -/** - \brief Load-Acquire Exclusive (16 bit) - \details Executes a LDAH exclusive instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDAEXH (uint16_t)__builtin_arm_ldaex - - -/** - \brief Load-Acquire Exclusive (32 bit) - \details Executes a LDA exclusive instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDAEX (uint32_t)__builtin_arm_ldaex - - -/** - \brief Store-Release Exclusive (8 bit) - \details Executes a STLB exclusive instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STLEXB (uint32_t)__builtin_arm_stlex - - -/** - \brief Store-Release Exclusive (16 bit) - \details Executes a STLH exclusive instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STLEXH (uint32_t)__builtin_arm_stlex - - -/** - \brief Store-Release Exclusive (32 bit) - \details Executes a STL exclusive instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STLEX (uint32_t)__builtin_arm_stlex - -#endif /* (__ARM_ARCH >= 8) */ - -/** @}*/ /* end of group CMSIS_Core_InstructionInterface */ - - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -/** - \brief Enable IRQ Interrupts - \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. - Can only be executed in Privileged modes. - */ -#ifndef __ARM_COMPAT_H -__STATIC_FORCEINLINE void __enable_irq(void) -{ - __ASM volatile ("cpsie i" : : : "memory"); -} -#endif - - -/** - \brief Disable IRQ Interrupts - \details Disables IRQ interrupts by setting special-purpose register PRIMASK. - Can only be executed in Privileged modes. - */ -#ifndef __ARM_COMPAT_H -__STATIC_FORCEINLINE void __disable_irq(void) -{ - __ASM volatile ("cpsid i" : : : "memory"); -} -#endif - -#if (__ARM_ARCH_ISA_THUMB >= 2) -/** - \brief Enable FIQ - \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. - Can only be executed in Privileged modes. - */ -__STATIC_FORCEINLINE void __enable_fault_irq(void) -{ - __ASM volatile ("cpsie f" : : : "memory"); -} - - -/** - \brief Disable FIQ - \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. - Can only be executed in Privileged modes. - */ -__STATIC_FORCEINLINE void __disable_fault_irq(void) -{ - __ASM volatile ("cpsid f" : : : "memory"); -} -#endif - - - -/** - \brief Get FPSCR - \details Returns the current value of the Floating Point Status/Control register. - \return Floating Point Status/Control register value - */ -__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) -{ -#if (defined(__ARM_FP) && (__ARM_FP >= 1)) - return (__builtin_arm_get_fpscr()); -#else - return (0U); -#endif -} - - -/** - \brief Set FPSCR - \details Assigns the given value to the Floating Point Status/Control register. - \param [in] fpscr Floating Point Status/Control value to set - */ -__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) -{ -#if (defined(__ARM_FP) && (__ARM_FP >= 1)) - __builtin_arm_set_fpscr(fpscr); -#else - (void)fpscr; -#endif -} - -/** @} end of CMSIS_Core_RegAccFunctions */ - -// Include the profile specific settings: -#if __ARM_ARCH_PROFILE == 'A' - #include "./a-profile/cmsis_armclang_a.h" -#elif __ARM_ARCH_PROFILE == 'R' - #include "./r-profile/cmsis_armclang_r.h" -#elif __ARM_ARCH_PROFILE == 'M' - #include "./m-profile/cmsis_armclang_m.h" -#else - #error "Unknown Arm architecture profile" -#endif - -#endif /* __CMSIS_ARMCLANG_H */ diff --git a/lib/main/pico-sdk/rp2_common/cmsis/stub/CMSIS/Core/Include/cmsis_armclang_ltm.h b/lib/main/pico-sdk/rp2_common/cmsis/stub/CMSIS/Core/Include/cmsis_armclang_ltm.h deleted file mode 100644 index 1e255d5907..0000000000 --- a/lib/main/pico-sdk/rp2_common/cmsis/stub/CMSIS/Core/Include/cmsis_armclang_ltm.h +++ /dev/null @@ -1,1928 +0,0 @@ -/**************************************************************************//** - * @file cmsis_armclang_ltm.h - * @brief CMSIS compiler armclang (Arm Compiler 6) header file - * @version V1.5.3 - * @date 27. May 2021 - ******************************************************************************/ -/* - * Copyright (c) 2018-2021 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ - -#ifndef __CMSIS_ARMCLANG_H -#define __CMSIS_ARMCLANG_H - -#pragma clang system_header /* treat file as system include file */ - -/* CMSIS compiler specific defines */ -#ifndef __ASM - #define __ASM __asm -#endif -#ifndef __INLINE - #define __INLINE __inline -#endif -#ifndef __STATIC_INLINE - #define __STATIC_INLINE static __inline -#endif -#ifndef __STATIC_FORCEINLINE - #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline -#endif -#ifndef __NO_RETURN - #define __NO_RETURN __attribute__((__noreturn__)) -#endif -#ifndef __USED - #define __USED __attribute__((used)) -#endif -#ifndef __WEAK - #define __WEAK __attribute__((weak)) -#endif -#ifndef __PACKED - #define __PACKED __attribute__((packed, aligned(1))) -#endif -#ifndef __PACKED_STRUCT - #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) -#endif -#ifndef __PACKED_UNION - #define __PACKED_UNION union __attribute__((packed, aligned(1))) -#endif -#ifndef __UNALIGNED_UINT32 /* deprecated */ - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wpacked" -/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ - struct __attribute__((packed)) T_UINT32 { uint32_t v; }; - #pragma clang diagnostic pop - #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) -#endif -#ifndef __UNALIGNED_UINT16_WRITE - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wpacked" -/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ - __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; - #pragma clang diagnostic pop - #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) -#endif -#ifndef __UNALIGNED_UINT16_READ - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wpacked" -/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ - __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; - #pragma clang diagnostic pop - #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) -#endif -#ifndef __UNALIGNED_UINT32_WRITE - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wpacked" -/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ - __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; - #pragma clang diagnostic pop - #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) -#endif -#ifndef __UNALIGNED_UINT32_READ - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wpacked" -/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ - __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; - #pragma clang diagnostic pop - #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) -#endif -#ifndef __ALIGNED - #define __ALIGNED(x) __attribute__((aligned(x))) -#endif -#ifndef __RESTRICT - #define __RESTRICT __restrict -#endif -#ifndef __COMPILER_BARRIER - #define __COMPILER_BARRIER() __ASM volatile("":::"memory") -#endif - -/* ######################### Startup and Lowlevel Init ######################## */ - -#ifndef __PROGRAM_START -#define __PROGRAM_START __main -#endif - -#ifndef __INITIAL_SP -#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit -#endif - -#ifndef __STACK_LIMIT -#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base -#endif - -#ifndef __VECTOR_TABLE -#define __VECTOR_TABLE __Vectors -#endif - -#ifndef __VECTOR_TABLE_ATTRIBUTE -#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) -#endif - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#ifndef __STACK_SEAL -#define __STACK_SEAL Image$$STACKSEAL$$ZI$$Base -#endif - -#ifndef __TZ_STACK_SEAL_SIZE -#define __TZ_STACK_SEAL_SIZE 8U -#endif - -#ifndef __TZ_STACK_SEAL_VALUE -#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL -#endif - - -__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { - *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; -} -#endif - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -/* Define macros for porting to both thumb1 and thumb2. - * For thumb1, use low register (r0-r7), specified by constraint "l" - * Otherwise, use general registers, specified by constraint "r" */ -#if defined (__thumb__) && !defined (__thumb2__) -#define __CMSIS_GCC_OUT_REG(r) "=l" (r) -#define __CMSIS_GCC_USE_REG(r) "l" (r) -#else -#define __CMSIS_GCC_OUT_REG(r) "=r" (r) -#define __CMSIS_GCC_USE_REG(r) "r" (r) -#endif - -/** - \brief No Operation - \details No Operation does nothing. This instruction can be used for code alignment purposes. - */ -#define __NOP __builtin_arm_nop - -/** - \brief Wait For Interrupt - \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. - */ -#define __WFI __builtin_arm_wfi - - -/** - \brief Wait For Event - \details Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -#define __WFE __builtin_arm_wfe - - -/** - \brief Send Event - \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -#define __SEV __builtin_arm_sev - - -/** - \brief Instruction Synchronization Barrier - \details Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or memory, - after the instruction has been completed. - */ -#define __ISB() __builtin_arm_isb(0xF) - -/** - \brief Data Synchronization Barrier - \details Acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -#define __DSB() __builtin_arm_dsb(0xF) - - -/** - \brief Data Memory Barrier - \details Ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -#define __DMB() __builtin_arm_dmb(0xF) - - -/** - \brief Reverse byte order (32 bit) - \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV(value) __builtin_bswap32(value) - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV16(value) __ROR(__REV(value), 16) - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. - \param [in] value Value to reverse - \return Reversed value - */ -#define __REVSH(value) (int16_t)__builtin_bswap16(value) - - -/** - \brief Rotate Right in unsigned value (32 bit) - \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - \param [in] op1 Value to rotate - \param [in] op2 Number of Bits to rotate - \return Rotated value - */ -__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) -{ - op2 %= 32U; - if (op2 == 0U) - { - return op1; - } - return (op1 >> op2) | (op1 << (32U - op2)); -} - - -/** - \brief Breakpoint - \details Causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __ASM volatile ("bkpt "#value) - - -/** - \brief Reverse bit order of value - \details Reverses the bit order of the given value. - \param [in] value Value to reverse - \return Reversed value - */ -#define __RBIT __builtin_arm_rbit - -/** - \brief Count leading zeros - \details Counts the number of leading zeros of a data value. - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) -{ - /* Even though __builtin_clz produces a CLZ instruction on ARM, formally - __builtin_clz(0) is undefined behaviour, so handle this case specially. - This guarantees ARM-compatible results if happening to compile on a non-ARM - target, and ensures the compiler doesn't decide to activate any - optimisations using the logic "value was passed to __builtin_clz, so it - is non-zero". - ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a - single CLZ instruction. - */ - if (value == 0U) - { - return 32U; - } - return __builtin_clz(value); -} - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) -/** - \brief LDR Exclusive (8 bit) - \details Executes a exclusive LDR instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDREXB (uint8_t)__builtin_arm_ldrex - - -/** - \brief LDR Exclusive (16 bit) - \details Executes a exclusive LDR instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDREXH (uint16_t)__builtin_arm_ldrex - - -/** - \brief LDR Exclusive (32 bit) - \details Executes a exclusive LDR instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDREXW (uint32_t)__builtin_arm_ldrex - - -/** - \brief STR Exclusive (8 bit) - \details Executes a exclusive STR instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXB (uint32_t)__builtin_arm_strex - - -/** - \brief STR Exclusive (16 bit) - \details Executes a exclusive STR instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXH (uint32_t)__builtin_arm_strex - - -/** - \brief STR Exclusive (32 bit) - \details Executes a exclusive STR instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXW (uint32_t)__builtin_arm_strex - - -/** - \brief Remove the exclusive lock - \details Removes the exclusive lock which is created by LDREX. - */ -#define __CLREX __builtin_arm_clrex - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) - -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT __builtin_arm_ssat - - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT __builtin_arm_usat - - -/** - \brief Rotate Right with Extend (32 bit) - \details Moves each bit of a bitstring right by one bit. - The carry input is shifted in at the left end of the bitstring. - \param [in] value Value to rotate - \return Rotated value - */ -__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} - - -/** - \brief LDRT Unprivileged (8 bit) - \details Executes a Unprivileged LDRT instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint8_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (16 bit) - \details Executes a Unprivileged LDRT instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint16_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (32 bit) - \details Executes a Unprivileged LDRT instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); - return(result); -} - - -/** - \brief STRT Unprivileged (8 bit) - \details Executes a Unprivileged STRT instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) -{ - __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (16 bit) - \details Executes a Unprivileged STRT instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) -{ - __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (32 bit) - \details Executes a Unprivileged STRT instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) -{ - __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); -} - -#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ - -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) -{ - if ((sat >= 1U) && (sat <= 32U)) - { - const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); - const int32_t min = -1 - max ; - if (val > max) - { - return max; - } - else if (val < min) - { - return min; - } - } - return val; -} - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) -{ - if (sat <= 31U) - { - const uint32_t max = ((1U << sat) - 1U); - if (val > (int32_t)max) - { - return max; - } - else if (val < 0) - { - return 0U; - } - } - return (uint32_t)val; -} - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) -/** - \brief Load-Acquire (8 bit) - \details Executes a LDAB instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); - return ((uint8_t) result); -} - - -/** - \brief Load-Acquire (16 bit) - \details Executes a LDAH instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); - return ((uint16_t) result); -} - - -/** - \brief Load-Acquire (32 bit) - \details Executes a LDA instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); - return(result); -} - - -/** - \brief Store-Release (8 bit) - \details Executes a STLB instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) -{ - __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); -} - - -/** - \brief Store-Release (16 bit) - \details Executes a STLH instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) -{ - __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); -} - - -/** - \brief Store-Release (32 bit) - \details Executes a STL instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) -{ - __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); -} - - -/** - \brief Load-Acquire Exclusive (8 bit) - \details Executes a LDAB exclusive instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDAEXB (uint8_t)__builtin_arm_ldaex - - -/** - \brief Load-Acquire Exclusive (16 bit) - \details Executes a LDAH exclusive instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDAEXH (uint16_t)__builtin_arm_ldaex - - -/** - \brief Load-Acquire Exclusive (32 bit) - \details Executes a LDA exclusive instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDAEX (uint32_t)__builtin_arm_ldaex - - -/** - \brief Store-Release Exclusive (8 bit) - \details Executes a STLB exclusive instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STLEXB (uint32_t)__builtin_arm_stlex - - -/** - \brief Store-Release Exclusive (16 bit) - \details Executes a STLH exclusive instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STLEXH (uint32_t)__builtin_arm_stlex - - -/** - \brief Store-Release Exclusive (32 bit) - \details Executes a STL exclusive instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STLEX (uint32_t)__builtin_arm_stlex - -#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -/** - \brief Enable IRQ Interrupts - \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. - Can only be executed in Privileged modes. - */ -#ifndef __ARM_COMPAT_H -__STATIC_FORCEINLINE void __enable_irq(void) -{ - __ASM volatile ("cpsie i" : : : "memory"); -} -#endif - - -/** - \brief Disable IRQ Interrupts - \details Disables IRQ interrupts by setting special-purpose register PRIMASK. - Can only be executed in Privileged modes. - */ -#ifndef __ARM_COMPAT_H -__STATIC_FORCEINLINE void __disable_irq(void) -{ - __ASM volatile ("cpsid i" : : : "memory"); -} -#endif - - -/** - \brief Get Control Register - \details Returns the content of the Control Register. - \return Control Register value - */ -__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Control Register (non-secure) - \details Returns the content of the non-secure Control Register when in secure mode. - \return non-secure Control Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Control Register - \details Writes the given value to the Control Register. - \param [in] control Control Register value to set - */ -__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) -{ - __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); - __ISB(); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Control Register (non-secure) - \details Writes the given value to the non-secure Control Register when in secure state. - \param [in] control Control Register value to set - */ -__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) -{ - __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); - __ISB(); -} -#endif - - -/** - \brief Get IPSR Register - \details Returns the content of the IPSR Register. - \return IPSR Register value - */ -__STATIC_FORCEINLINE uint32_t __get_IPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get APSR Register - \details Returns the content of the APSR Register. - \return APSR Register value - */ -__STATIC_FORCEINLINE uint32_t __get_APSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, apsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get xPSR Register - \details Returns the content of the xPSR Register. - \return xPSR Register value - */ -__STATIC_FORCEINLINE uint32_t __get_xPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get Process Stack Pointer - \details Returns the current value of the Process Stack Pointer (PSP). - \return PSP Register value - */ -__STATIC_FORCEINLINE uint32_t __get_PSP(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, psp" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Process Stack Pointer (non-secure) - \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. - \return PSP Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Process Stack Pointer - \details Assigns the given value to the Process Stack Pointer (PSP). - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Process Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); -} -#endif - - -/** - \brief Get Main Stack Pointer - \details Returns the current value of the Main Stack Pointer (MSP). - \return MSP Register value - */ -__STATIC_FORCEINLINE uint32_t __get_MSP(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, msp" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Main Stack Pointer (non-secure) - \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. - \return MSP Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Main Stack Pointer - \details Assigns the given value to the Main Stack Pointer (MSP). - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Main Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); -} -#endif - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Stack Pointer (non-secure) - \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. - \return SP Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); - return(result); -} - - -/** - \brief Set Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. - \param [in] topOfStack Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) -{ - __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); -} -#endif - - -/** - \brief Get Priority Mask - \details Returns the current state of the priority mask bit from the Priority Mask Register. - \return Priority Mask value - */ -__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Priority Mask (non-secure) - \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. - \return Priority Mask value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Priority Mask - \details Assigns the given value to the Priority Mask Register. - \param [in] priMask Priority Mask - */ -__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) -{ - __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Priority Mask (non-secure) - \details Assigns the given value to the non-secure Priority Mask Register when in secure state. - \param [in] priMask Priority Mask - */ -__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) -{ - __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); -} -#endif - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) -/** - \brief Enable FIQ - \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. - Can only be executed in Privileged modes. - */ -__STATIC_FORCEINLINE void __enable_fault_irq(void) -{ - __ASM volatile ("cpsie f" : : : "memory"); -} - - -/** - \brief Disable FIQ - \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. - Can only be executed in Privileged modes. - */ -__STATIC_FORCEINLINE void __disable_fault_irq(void) -{ - __ASM volatile ("cpsid f" : : : "memory"); -} - - -/** - \brief Get Base Priority - \details Returns the current value of the Base Priority register. - \return Base Priority register value - */ -__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Base Priority (non-secure) - \details Returns the current value of the non-secure Base Priority register when in secure state. - \return Base Priority register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Base Priority - \details Assigns the given value to the Base Priority register. - \param [in] basePri Base Priority value to set - */ -__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) -{ - __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Base Priority (non-secure) - \details Assigns the given value to the non-secure Base Priority register when in secure state. - \param [in] basePri Base Priority value to set - */ -__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) -{ - __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); -} -#endif - - -/** - \brief Set Base Priority with condition - \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, - or the new value increases the BASEPRI priority level. - \param [in] basePri Base Priority value to set - */ -__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) -{ - __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); -} - - -/** - \brief Get Fault Mask - \details Returns the current value of the Fault Mask register. - \return Fault Mask register value - */ -__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Fault Mask (non-secure) - \details Returns the current value of the non-secure Fault Mask register when in secure state. - \return Fault Mask register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Fault Mask - \details Assigns the given value to the Fault Mask register. - \param [in] faultMask Fault Mask value to set - */ -__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Fault Mask (non-secure) - \details Assigns the given value to the non-secure Fault Mask register when in secure state. - \param [in] faultMask Fault Mask value to set - */ -__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); -} -#endif - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) - -/** - \brief Get Process Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always in non-secure - mode. - - \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). - \return PSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - return 0U; -#else - uint32_t result; - __ASM volatile ("MRS %0, psplim" : "=r" (result) ); - return result; -#endif -} - -#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Process Stack Pointer Limit (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always in non-secure - mode. - - \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. - \return PSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - return 0U; -#else - uint32_t result; - __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); - return result; -#endif -} -#endif - - -/** - \brief Set Process Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored in non-secure - mode. - - \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). - \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set - */ -__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - (void)ProcStackPtrLimit; -#else - __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); -#endif -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Process Stack Pointer (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored in non-secure - mode. - - \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. - \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set - */ -__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - (void)ProcStackPtrLimit; -#else - __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); -#endif -} -#endif - - -/** - \brief Get Main Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always. - - \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). - \return MSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - return 0U; -#else - uint32_t result; - __ASM volatile ("MRS %0, msplim" : "=r" (result) ); - return result; -#endif -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Main Stack Pointer Limit (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always. - - \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. - \return MSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - return 0U; -#else - uint32_t result; - __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); - return result; -#endif -} -#endif - - -/** - \brief Set Main Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored. - - \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). - \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set - */ -__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - (void)MainStackPtrLimit; -#else - __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); -#endif -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Main Stack Pointer Limit (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored. - - \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. - \param [in] MainStackPtrLimit Main Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - (void)MainStackPtrLimit; -#else - __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); -#endif -} -#endif - -#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ - -/** - \brief Get FPSCR - \details Returns the current value of the Floating Point Status/Control register. - \return Floating Point Status/Control register value - */ -#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) -#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr -#else -#define __get_FPSCR() ((uint32_t)0U) -#endif - -/** - \brief Set FPSCR - \details Assigns the given value to the Floating Point Status/Control register. - \param [in] fpscr Floating Point Status/Control value to set - */ -#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) -#define __set_FPSCR __builtin_arm_set_fpscr -#else -#define __set_FPSCR(x) ((void)(x)) -#endif - - -/*@} end of CMSIS_Core_RegAccFunctions */ - - -/* ################### Compiler specific Intrinsics ########################### */ -/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics - Access to dedicated SIMD instructions - @{ -*/ - -#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) - -__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#define __SSAT16(ARG1,ARG2) \ -({ \ - int32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -#define __USAT16(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) -{ - int32_t result; - - __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) -{ - int32_t result; - - __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ - ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) - -#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ - ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) - -#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) - -#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) - -__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) -{ - int32_t result; - - __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#endif /* (__ARM_FEATURE_DSP == 1) */ -/*@} end of group CMSIS_SIMD_intrinsics */ - - -#endif /* __CMSIS_ARMCLANG_H */ diff --git a/lib/main/pico-sdk/rp2_common/cmsis/stub/CMSIS/Core/Include/cmsis_clang.h b/lib/main/pico-sdk/rp2_common/cmsis/stub/CMSIS/Core/Include/cmsis_clang.h deleted file mode 100644 index 364d18e14c..0000000000 --- a/lib/main/pico-sdk/rp2_common/cmsis/stub/CMSIS/Core/Include/cmsis_clang.h +++ /dev/null @@ -1,708 +0,0 @@ -/**************************************************************************//** - * @file cmsis_clang.h - * @brief CMSIS compiler LLVM/Clang header file - * @version V6.0.0 - * @date 27. July 2024 - ******************************************************************************/ -/* - * Copyright (c) 2009-2023 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __CMSIS_CLANG_H -#define __CMSIS_CLANG_H - -#pragma clang system_header /* treat file as system include file */ - -#if (__ARM_ACLE >= 200) -#include -#else -#error Compiler must support ACLE V2.0 -#endif /* (__ARM_ACLE >= 200) */ - -/* Fallback for __has_builtin */ -#ifndef __has_builtin -#define __has_builtin(x) (0) -#endif - -/* CMSIS compiler specific defines */ -#ifndef __ASM -#define __ASM __asm -#endif -#ifndef __INLINE -#define __INLINE inline -#endif -#ifndef __STATIC_INLINE -#define __STATIC_INLINE static inline -#endif -#ifndef __STATIC_FORCEINLINE -#define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline -#endif -#ifndef __NO_RETURN -#define __NO_RETURN __attribute__((__noreturn__)) -#endif -#ifndef CMSIS_DEPRECATED -#define CMSIS_DEPRECATED __attribute__((deprecated)) -#endif -#ifndef __USED -#define __USED __attribute__((used)) -#endif -#ifndef __WEAK -#define __WEAK __attribute__((weak)) -#endif -#ifndef __PACKED -#define __PACKED __attribute__((packed, aligned(1))) -#endif -#ifndef __PACKED_STRUCT -#define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) -#endif -#ifndef __PACKED_UNION -#define __PACKED_UNION union __attribute__((packed, aligned(1))) -#endif -#ifndef __UNALIGNED_UINT16_WRITE -#pragma clang diagnostic push -#pragma clang diagnostic ignored "-Wpacked" -__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; -#pragma clang diagnostic pop -#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) -#endif -#ifndef __UNALIGNED_UINT16_READ -#pragma clang diagnostic push -#pragma clang diagnostic ignored "-Wpacked" -__PACKED_STRUCT T_UINT16_READ { uint16_t v; }; -#pragma clang diagnostic pop -#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) -#endif -#ifndef __UNALIGNED_UINT32_WRITE -#pragma clang diagnostic push -#pragma clang diagnostic ignored "-Wpacked" -__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; -#pragma clang diagnostic pop -#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) -#endif -#ifndef __UNALIGNED_UINT32_READ -#pragma clang diagnostic push -#pragma clang diagnostic ignored "-Wpacked" -__PACKED_STRUCT T_UINT32_READ { uint32_t v; }; -#pragma clang diagnostic pop -#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) -#endif -#ifndef __ALIGNED -#define __ALIGNED(x) __attribute__((aligned(x))) -#endif -#ifndef __RESTRICT -#define __RESTRICT __restrict -#endif -#ifndef __COMPILER_BARRIER -#define __COMPILER_BARRIER() __ASM volatile("":::"memory") -#endif -#ifndef __NO_INIT -#define __NO_INIT __attribute__ ((section (".noinit"))) -#endif -#ifndef __ALIAS -#define __ALIAS(x) __attribute__ ((alias(x))) -#endif - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -/* Define macros for porting to both thumb1 and thumb2. - * For thumb1, use low register (r0-r7), specified by constraint "l" - * Otherwise, use general registers, specified by constraint "r" */ -#if defined (__thumb__) && !defined (__thumb2__) -#define __CMSIS_GCC_OUT_REG(r) "=l" (r) -#define __CMSIS_GCC_RW_REG(r) "+l" (r) -#define __CMSIS_GCC_USE_REG(r) "l" (r) -#else -#define __CMSIS_GCC_OUT_REG(r) "=r" (r) -#define __CMSIS_GCC_RW_REG(r) "+r" (r) -#define __CMSIS_GCC_USE_REG(r) "r" (r) -#endif - -/** - \brief No Operation - \details No Operation does nothing. This instruction can be used for code alignment purposes. - */ -#define __NOP() __nop() - - -/** - \brief Wait For Interrupt - \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. - */ -#define __WFI() __wfi() - - -/** - \brief Wait For Event - \details Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -#define __WFE() __wfe() - - -/** - \brief Send Event - \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -#define __SEV() __sev() - - -/** - \brief Instruction Synchronization Barrier - \details Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or memory, - after the instruction has been completed. - */ -#define __ISB() __isb(0xF) - - -/** - \brief Data Synchronization Barrier - \details Acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -#define __DSB() __dsb(0xF) - - -/** - \brief Data Memory Barrier - \details Ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -#define __DMB() __dmb(0xF) - - -/** - \brief Reverse byte order (32 bit) - \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV(value) __rev(value) - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV16(value) __rev16(value) - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. - \param [in] value Value to reverse - \return Reversed value - */ -#define __REVSH(value) __revsh(value) - - -/** - \brief Rotate Right in unsigned value (32 bit) - \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - \param [in] op1 Value to rotate - \param [in] op2 Number of Bits to rotate - \return Rotated value - */ -#define __ROR(op1, op2) __ror(op1, op2) - - -/** - \brief Breakpoint - \details Causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __ASM volatile ("bkpt "#value) - - -/** - \brief Reverse bit order of value - \details Reverses the bit order of the given value. - \param [in] value Value to reverse - \return Reversed value - */ -#define __RBIT(value) __rbit(value) - - -/** - \brief Count leading zeros - \details Counts the number of leading zeros of a data value. - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -#define __CLZ(value) __clz(value) - - -#if ((__ARM_FEATURE_SAT >= 1) && \ - (__ARM_ARCH_ISA_THUMB >= 2) ) -/* __ARM_FEATURE_SAT is wrong for Armv8-M Baseline devices */ -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT(value, sat) __ssat(value, sat) - - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT(value, sat) __usat(value, sat) - -#else /* (__ARM_FEATURE_SAT >= 1) */ -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) -{ - if ((sat >= 1U) && (sat <= 32U)) - { - const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); - const int32_t min = -1 - max ; - if (val > max) - { - return (max); - } - else if (val < min) - { - return (min); - } - } - return (val); -} - - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) -{ - if (sat <= 31U) - { - const uint32_t max = ((1U << sat) - 1U); - if (val > (int32_t)max) - { - return (max); - } - else if (val < 0) - { - return (0U); - } - } - return ((uint32_t)val); -} -#endif /* (__ARM_FEATURE_SAT >= 1) */ - - -#if (__ARM_FEATURE_LDREX >= 1) -/** - \brief Remove the exclusive lock - \details Removes the exclusive lock which is created by LDREX. - */ -#define __CLREX __builtin_arm_clrex - - -/** - \brief LDR Exclusive (8 bit) - \details Executes a exclusive LDR instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDREXB (uint8_t)__builtin_arm_ldrex - - -/** - \brief STR Exclusive (8 bit) - \details Executes a exclusive STR instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXB (uint32_t)__builtin_arm_strex -#endif /* (__ARM_FEATURE_LDREX >= 1) */ - - -#if (__ARM_FEATURE_LDREX >= 2) -/** - \brief LDR Exclusive (16 bit) - \details Executes a exclusive LDR instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDREXH (uint16_t)__builtin_arm_ldrex - - -/** - \brief STR Exclusive (16 bit) - \details Executes a exclusive STR instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXH (uint32_t)__builtin_arm_strex -#endif /* (__ARM_FEATURE_LDREX >= 2) */ - - -#if (__ARM_FEATURE_LDREX >= 4) -/** - \brief LDR Exclusive (32 bit) - \details Executes a exclusive LDR instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDREXW (uint32_t)__builtin_arm_ldrex - - -/** - \brief STR Exclusive (32 bit) - \details Executes a exclusive STR instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXW (uint32_t)__builtin_arm_strex -#endif /* (__ARM_FEATURE_LDREX >= 4) */ - - -#if (__ARM_ARCH_ISA_THUMB >= 2) -/** - \brief Rotate Right with Extend (32 bit) - \details Moves each bit of a bitstring right by one bit. - The carry input is shifted in at the left end of the bitstring. - \param [in] value Value to rotate - \return Rotated value - */ -__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rrx %0, %1" : "=r" (result) : "r" (value)); - return (result); -} - - -/** - \brief LDRT Unprivileged (8 bit) - \details Executes a Unprivileged LDRT instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint8_t)result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (16 bit) - \details Executes a Unprivileged LDRT instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint16_t)result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (32 bit) - \details Executes a Unprivileged LDRT instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); - return (result); -} -#endif /* (__ARM_ARCH_ISA_THUMB >= 2) */ - - -#if (__ARM_ARCH >= 8) -/** - \brief Load-Acquire (8 bit) - \details Executes a LDAB instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); - return ((uint8_t)result); /* Add explicit type cast here */ -} - - -/** - \brief Load-Acquire (16 bit) - \details Executes a LDAH instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); - return ((uint16_t)result); /* Add explicit type cast here */ -} - - -/** - \brief Load-Acquire (32 bit) - \details Executes a LDA instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); - return (result); -} - - -/** - \brief Store-Release (8 bit) - \details Executes a STLB instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) -{ - __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); -} - - -/** - \brief Store-Release (16 bit) - \details Executes a STLH instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) -{ - __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); -} - - -/** - \brief Store-Release (32 bit) - \details Executes a STL instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) -{ - __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); -} - - -/** - \brief Load-Acquire Exclusive (8 bit) - \details Executes a LDAB exclusive instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDAEXB (uint8_t)__builtin_arm_ldaex - - -/** - \brief Load-Acquire Exclusive (16 bit) - \details Executes a LDAH exclusive instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDAEXH (uint16_t)__builtin_arm_ldaex - - -/** - \brief Load-Acquire Exclusive (32 bit) - \details Executes a LDA exclusive instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDAEX (uint32_t)__builtin_arm_ldaex - - -/** - \brief Store-Release Exclusive (8 bit) - \details Executes a STLB exclusive instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STLEXB (uint32_t)__builtin_arm_stlex - - -/** - \brief Store-Release Exclusive (16 bit) - \details Executes a STLH exclusive instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STLEXH (uint32_t)__builtin_arm_stlex - - -/** - \brief Store-Release Exclusive (32 bit) - \details Executes a STL exclusive instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STLEX (uint32_t)__builtin_arm_stlex - -#endif /* (__ARM_ARCH >= 8) */ - -/** @}*/ /* end of group CMSIS_Core_InstructionInterface */ - - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -/** - \brief Enable IRQ Interrupts - \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. - Can only be executed in Privileged modes. - */ -__STATIC_FORCEINLINE void __enable_irq(void) -{ - __ASM volatile ("cpsie i" : : : "memory"); -} - - -/** - \brief Disable IRQ Interrupts - \details Disables IRQ interrupts by setting special-purpose register PRIMASK. - Can only be executed in Privileged modes. - */ -__STATIC_FORCEINLINE void __disable_irq(void) -{ - __ASM volatile ("cpsid i" : : : "memory"); -} - -#if (__ARM_ARCH_ISA_THUMB >= 2) -/** - \brief Enable FIQ - \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. - Can only be executed in Privileged modes. - */ -__STATIC_FORCEINLINE void __enable_fault_irq(void) -{ - __ASM volatile ("cpsie f" : : : "memory"); -} - - -/** - \brief Disable FIQ - \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. - Can only be executed in Privileged modes. - */ -__STATIC_FORCEINLINE void __disable_fault_irq(void) -{ - __ASM volatile ("cpsid f" : : : "memory"); -} -#endif - - - -/** - \brief Get FPSCR - \details Returns the current value of the Floating Point Status/Control register. - \return Floating Point Status/Control register value - */ -__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) -{ -#if (defined(__ARM_FP) && (__ARM_FP >= 1)) - return (__builtin_arm_get_fpscr()); -#else - return (0U); -#endif -} - - -/** - \brief Set FPSCR - \details Assigns the given value to the Floating Point Status/Control register. - \param [in] fpscr Floating Point Status/Control value to set - */ -__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) -{ -#if (defined(__ARM_FP) && (__ARM_FP >= 1)) - __builtin_arm_set_fpscr(fpscr); -#else - (void)fpscr; -#endif -} - -/** @} end of CMSIS_Core_RegAccFunctions */ - -// Include the profile specific settings: -#if __ARM_ARCH_PROFILE == 'A' -#include "./a-profile/cmsis_clang_a.h" -#elif __ARM_ARCH_PROFILE == 'R' -#include "./r-profile/cmsis_clang_r.h" -#elif __ARM_ARCH_PROFILE == 'M' -#include "./m-profile/cmsis_clang_m.h" -#else -#error "Unknown Arm architecture profile" -#endif - -#endif /* __CMSIS_CLANG_H */ diff --git a/lib/main/pico-sdk/rp2_common/cmsis/stub/CMSIS/Core/Include/cmsis_compiler.h b/lib/main/pico-sdk/rp2_common/cmsis/stub/CMSIS/Core/Include/cmsis_compiler.h deleted file mode 100644 index cf3f5b027d..0000000000 --- a/lib/main/pico-sdk/rp2_common/cmsis/stub/CMSIS/Core/Include/cmsis_compiler.h +++ /dev/null @@ -1,292 +0,0 @@ -/* - * Copyright (c) 2009-2023 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* - * CMSIS Compiler Generic Header File - */ - -#ifndef __CMSIS_COMPILER_H -#define __CMSIS_COMPILER_H - -#include - -/* - * Arm Compiler above 6.10.1 (armclang) - */ -#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) - #include "cmsis_armclang.h" - -/* - * TI Arm Clang Compiler (tiarmclang) - */ -#elif defined (__ti__) - #include "cmsis_tiarmclang.h" - - -/* - * LLVM/Clang Compiler - */ -#elif defined ( __clang__ ) - #include "cmsis_clang.h" - - -/* - * GNU Compiler - */ -#elif defined ( __GNUC__ ) - #include "cmsis_gcc.h" - - -/* - * IAR Compiler - */ -#elif defined ( __ICCARM__ ) - #if __ARM_ARCH_PROFILE == 'A' - #include "a-profile/cmsis_iccarm_a.h" - #elif __ARM_ARCH_PROFILE == 'R' - #include "r-profile/cmsis_iccarm_r.h" - #elif __ARM_ARCH_PROFILE == 'M' - #include "m-profile/cmsis_iccarm_m.h" - #else - #error "Unknown Arm architecture profile" - #endif - - -/* - * TI Arm Compiler (armcl) - */ -#elif defined ( __TI_ARM__ ) - #include - - #ifndef __ASM - #define __ASM __asm - #endif - #ifndef __INLINE - #define __INLINE inline - #endif - #ifndef __STATIC_INLINE - #define __STATIC_INLINE static inline - #endif - #ifndef __STATIC_FORCEINLINE - #define __STATIC_FORCEINLINE __STATIC_INLINE - #endif - #ifndef __NO_RETURN - #define __NO_RETURN __attribute__((noreturn)) - #endif - #ifndef __USED - #define __USED __attribute__((used)) - #endif - #ifndef __WEAK - #define __WEAK __attribute__((weak)) - #endif - #ifndef __PACKED - #define __PACKED __attribute__((packed)) - #endif - #ifndef __PACKED_STRUCT - #define __PACKED_STRUCT struct __attribute__((packed)) - #endif - #ifndef __PACKED_UNION - #define __PACKED_UNION union __attribute__((packed)) - #endif - #ifndef __UNALIGNED_UINT16_WRITE - __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; - #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) - #endif - #ifndef __UNALIGNED_UINT16_READ - __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; - #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) - #endif - #ifndef __UNALIGNED_UINT32_WRITE - __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; - #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) - #endif - #ifndef __UNALIGNED_UINT32_READ - __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; - #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) - #endif - #ifndef __ALIGNED - #define __ALIGNED(x) __attribute__((aligned(x))) - #endif - #ifndef __RESTRICT - #define __RESTRICT __restrict - #endif - #ifndef __COMPILER_BARRIER - #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. - #define __COMPILER_BARRIER() (void)0 - #endif - #ifndef __NO_INIT - #define __NO_INIT __attribute__ ((section (".noinit"))) - #endif - #ifndef __ALIAS - #define __ALIAS(x) __attribute__ ((alias(x))) - #endif - -/* - * TASKING Compiler - */ -#elif defined ( __TASKING__ ) - /* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all intrinsics, - * Including the CMSIS ones. - */ - - #ifndef __ASM - #define __ASM __asm - #endif - #ifndef __INLINE - #define __INLINE inline - #endif - #ifndef __STATIC_INLINE - #define __STATIC_INLINE static inline - #endif - #ifndef __STATIC_FORCEINLINE - #define __STATIC_FORCEINLINE __STATIC_INLINE - #endif - #ifndef __NO_RETURN - #define __NO_RETURN __attribute__((noreturn)) - #endif - #ifndef __USED - #define __USED __attribute__((used)) - #endif - #ifndef __WEAK - #define __WEAK __attribute__((weak)) - #endif - #ifndef __PACKED - #define __PACKED __packed__ - #endif - #ifndef __PACKED_STRUCT - #define __PACKED_STRUCT struct __packed__ - #endif - #ifndef __PACKED_UNION - #define __PACKED_UNION union __packed__ - #endif - #ifndef __UNALIGNED_UINT16_WRITE - __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; - #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) - #endif - #ifndef __UNALIGNED_UINT16_READ - __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; - #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) - #endif - #ifndef __UNALIGNED_UINT32_WRITE - __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; - #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) - #endif - #ifndef __UNALIGNED_UINT32_READ - __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; - #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) - #endif - #ifndef __ALIGNED - #define __ALIGNED(x) __align(x) - #endif - #ifndef __RESTRICT - #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. - #define __RESTRICT - #endif - #ifndef __COMPILER_BARRIER - #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. - #define __COMPILER_BARRIER() (void)0 - #endif - #ifndef __NO_INIT - #define __NO_INIT __attribute__ ((section (".noinit"))) - #endif - #ifndef __ALIAS - #define __ALIAS(x) __attribute__ ((alias(x))) - #endif - -/* - * COSMIC Compiler - */ -#elif defined ( __CSMC__ ) - #include - - #ifndef __ASM - #define __ASM _asm - #endif - #ifndef __INLINE - #define __INLINE inline - #endif - #ifndef __STATIC_INLINE - #define __STATIC_INLINE static inline - #endif - #ifndef __STATIC_FORCEINLINE - #define __STATIC_FORCEINLINE __STATIC_INLINE - #endif - #ifndef __NO_RETURN - // NO RETURN is automatically detected hence no warning here - #define __NO_RETURN - #endif - #ifndef __USED - #warning No compiler specific solution for __USED. __USED is ignored. - #define __USED - #endif - #ifndef __WEAK - #define __WEAK __weak - #endif - #ifndef __PACKED - #define __PACKED @packed - #endif - #ifndef __PACKED_STRUCT - #define __PACKED_STRUCT @packed struct - #endif - #ifndef __PACKED_UNION - #define __PACKED_UNION @packed union - #endif - #ifndef __UNALIGNED_UINT16_WRITE - __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; - #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) - #endif - #ifndef __UNALIGNED_UINT16_READ - __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; - #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) - #endif - #ifndef __UNALIGNED_UINT32_WRITE - __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; - #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) - #endif - #ifndef __UNALIGNED_UINT32_READ - __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; - #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) - #endif - #ifndef __ALIGNED - #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. - #define __ALIGNED(x) - #endif - #ifndef __RESTRICT - #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. - #define __RESTRICT - #endif - #ifndef __COMPILER_BARRIER - #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. - #define __COMPILER_BARRIER() (void)0 - #endif - #ifndef __NO_INIT - #define __NO_INIT __attribute__ ((section (".noinit"))) - #endif - #ifndef __ALIAS - #define __ALIAS(x) __attribute__ ((alias(x))) - #endif - -#else - #error Unknown compiler. -#endif - - -#endif /* __CMSIS_COMPILER_H */ - diff --git a/lib/main/pico-sdk/rp2_common/cmsis/stub/CMSIS/Core/Include/cmsis_gcc.h b/lib/main/pico-sdk/rp2_common/cmsis/stub/CMSIS/Core/Include/cmsis_gcc.h deleted file mode 100644 index 4771466f06..0000000000 --- a/lib/main/pico-sdk/rp2_common/cmsis/stub/CMSIS/Core/Include/cmsis_gcc.h +++ /dev/null @@ -1,1006 +0,0 @@ -/**************************************************************************//** - * @file cmsis_gcc.h - * @brief CMSIS compiler GCC header file - * @version V6.0.0 - * @date 27. July 2024 - ******************************************************************************/ -/* - * Copyright (c) 2009-2023 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __CMSIS_GCC_H -#define __CMSIS_GCC_H - -#pragma GCC system_header /* treat file as system include file */ - -#include - -/* Fallback for __has_builtin */ -#ifndef __has_builtin - #define __has_builtin(x) (0) -#endif - -/* CMSIS compiler specific defines */ -#ifndef __ASM - #define __ASM __asm -#endif -#ifndef __INLINE - #define __INLINE inline -#endif -#ifndef __STATIC_INLINE - #define __STATIC_INLINE static inline -#endif -#ifndef __STATIC_FORCEINLINE - #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline -#endif -#ifndef __NO_RETURN - #define __NO_RETURN __attribute__((__noreturn__)) -#endif -#ifndef CMSIS_DEPRECATED - #define CMSIS_DEPRECATED __attribute__((deprecated)) -#endif -#ifndef __USED - #define __USED __attribute__((used)) -#endif -#ifndef __WEAK - #define __WEAK __attribute__((weak)) -#endif -#ifndef __PACKED - #define __PACKED __attribute__((packed, aligned(1))) -#endif -#ifndef __PACKED_STRUCT - #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) -#endif -#ifndef __PACKED_UNION - #define __PACKED_UNION union __attribute__((packed, aligned(1))) -#endif -#ifndef __UNALIGNED_UINT16_WRITE - #pragma GCC diagnostic push - #pragma GCC diagnostic ignored "-Wpacked" - #pragma GCC diagnostic ignored "-Wattributes" - __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; - #pragma GCC diagnostic pop - #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) -#endif -#ifndef __UNALIGNED_UINT16_READ - #pragma GCC diagnostic push - #pragma GCC diagnostic ignored "-Wpacked" - #pragma GCC diagnostic ignored "-Wattributes" - __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; - #pragma GCC diagnostic pop - #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) -#endif -#ifndef __UNALIGNED_UINT32_WRITE - #pragma GCC diagnostic push - #pragma GCC diagnostic ignored "-Wpacked" - #pragma GCC diagnostic ignored "-Wattributes" - __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; - #pragma GCC diagnostic pop - #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) -#endif -#ifndef __UNALIGNED_UINT32_READ - #pragma GCC diagnostic push - #pragma GCC diagnostic ignored "-Wpacked" - #pragma GCC diagnostic ignored "-Wattributes" - __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; - #pragma GCC diagnostic pop - #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) -#endif -#ifndef __ALIGNED - #define __ALIGNED(x) __attribute__((aligned(x))) -#endif -#ifndef __RESTRICT - #define __RESTRICT __restrict -#endif -#ifndef __COMPILER_BARRIER - #define __COMPILER_BARRIER() __ASM volatile("":::"memory") -#endif -#ifndef __NO_INIT - #define __NO_INIT __attribute__ ((section (".noinit"))) -#endif -#ifndef __ALIAS - #define __ALIAS(x) __attribute__ ((alias(x))) -#endif - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -/* Define macros for porting to both thumb1 and thumb2. - * For thumb1, use low register (r0-r7), specified by constraint "l" - * Otherwise, use general registers, specified by constraint "r" */ -#if defined (__thumb__) && !defined (__thumb2__) -#define __CMSIS_GCC_OUT_REG(r) "=l" (r) -#define __CMSIS_GCC_RW_REG(r) "+l" (r) -#define __CMSIS_GCC_USE_REG(r) "l" (r) -#else -#define __CMSIS_GCC_OUT_REG(r) "=r" (r) -#define __CMSIS_GCC_RW_REG(r) "+r" (r) -#define __CMSIS_GCC_USE_REG(r) "r" (r) -#endif - -/** - \brief No Operation - \details No Operation does nothing. This instruction can be used for code alignment purposes. - */ -#define __NOP() __ASM volatile ("nop") - - -/** - \brief Wait For Interrupt - \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. - */ -#define __WFI() __ASM volatile ("wfi":::"memory") - - -/** - \brief Wait For Event - \details Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -#define __WFE() __ASM volatile ("wfe":::"memory") - - -/** - \brief Send Event - \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -#define __SEV() __ASM volatile ("sev") - - -/** - \brief Instruction Synchronization Barrier - \details Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or memory, - after the instruction has been completed. - */ -__STATIC_FORCEINLINE void __ISB(void) -{ - __ASM volatile ("isb 0xF":::"memory"); -} - - -/** - \brief Data Synchronization Barrier - \details Acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -__STATIC_FORCEINLINE void __DSB(void) -{ - __ASM volatile ("dsb 0xF":::"memory"); -} - - -/** - \brief Data Memory Barrier - \details Ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -__STATIC_FORCEINLINE void __DMB(void) -{ - __ASM volatile ("dmb 0xF":::"memory"); -} - - -/** - \brief Reverse byte order (32 bit) - \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. - \param [in] value Value to reverse - \return Reversed value - */ -__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) -{ - return __builtin_bswap32(value); -} - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. - \param [in] value Value to reverse - \return Reversed value - */ -__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) -{ - uint32_t result; - - __ASM ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return (result); -} - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. - \param [in] value Value to reverse - \return Reversed value - */ -__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) -{ - return (int16_t)__builtin_bswap16(value); -} - - -/** - \brief Rotate Right in unsigned value (32 bit) - \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - \param [in] op1 Value to rotate - \param [in] op2 Number of Bits to rotate - \return Rotated value - */ -__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) -{ - op2 %= 32U; - if (op2 == 0U) - { - return op1; - } - return (op1 >> op2) | (op1 << (32U - op2)); -} - - -/** - \brief Breakpoint - \details Causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __ASM volatile ("bkpt "#value) - - -/** - \brief Reverse bit order of value - \details Reverses the bit order of the given value. - \param [in] value Value to reverse - \return Reversed value - */ -__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) -{ - uint32_t result; - -#if (__ARM_ARCH_ISA_THUMB >= 2) - __ASM ("rbit %0, %1" : "=r" (result) : "r" (value) ); -#else - uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ - - result = value; /* r will be reversed bits of v; first get LSB of v */ - for (value >>= 1U; value != 0U; value >>= 1U) - { - result <<= 1U; - result |= value & 1U; - s--; - } - result <<= s; /* shift when v's highest bits are zero */ -#endif - return (result); -} - - -/** - \brief Count leading zeros - \details Counts the number of leading zeros of a data value. - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) -{ - /* Even though __builtin_clz produces a CLZ instruction on ARM, formally - __builtin_clz(0) is undefined behaviour, so handle this case specially. - This guarantees ARM-compatible results if happening to compile on a non-ARM - target, and ensures the compiler doesn't decide to activate any - optimisations using the logic "value was passed to __builtin_clz, so it - is non-zero". - ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a - single CLZ instruction. - */ - if (value == 0U) - { - return 32U; - } - return __builtin_clz(value); -} - - -#if (__ARM_FEATURE_SAT >= 1) -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT(value, sat) __ssat(value, sat) - - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT(value, sat) __usat(value, sat) - -#else /* (__ARM_FEATURE_SAT >= 1) */ -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) -{ - if ((sat >= 1U) && (sat <= 32U)) - { - const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); - const int32_t min = -1 - max ; - if (val > max) - { - return (max); - } - else if (val < min) - { - return (min); - } - } - return (val); -} - - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) -{ - if (sat <= 31U) - { - const uint32_t max = ((1U << sat) - 1U); - if (val > (int32_t)max) - { - return (max); - } - else if (val < 0) - { - return (0U); - } - } - return ((uint32_t)val); -} -#endif /* (__ARM_FEATURE_SAT >= 1) */ - - -#if (__ARM_FEATURE_LDREX >= 1) -/** - \brief Remove the exclusive lock - \details Removes the exclusive lock which is created by LDREX. - */ -__STATIC_FORCEINLINE void __CLREX(void) -{ - __ASM volatile ("clrex" ::: "memory"); -} - - -/** - \brief LDR Exclusive (8 bit) - \details Executes a exclusive LDR instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) -{ - uint32_t result; - - __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); - return ((uint8_t) result); /* Add explicit type cast here */ -} - - -/** - \brief STR Exclusive (8 bit) - \details Executes a exclusive STR instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); - return (result); -} -#endif /* (__ARM_FEATURE_LDREX >= 1) */ - - -#if (__ARM_FEATURE_LDREX >= 2) -/** - \brief LDR Exclusive (16 bit) - \details Executes a exclusive LDR instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) -{ - uint32_t result; - - __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); - return ((uint16_t)result); /* Add explicit type cast here */ -} - - -/** - \brief STR Exclusive (16 bit) - \details Executes a exclusive STR instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); - return (result); -} -#endif /* (__ARM_FEATURE_LDREX >= 2) */ - - -#if (__ARM_FEATURE_LDREX >= 4) -/** - \brief LDR Exclusive (32 bit) - \details Executes a exclusive LDR instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - return (result); -} - - -/** - \brief STR Exclusive (32 bit) - \details Executes a exclusive STR instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - return (result); -} -#endif /* (__ARM_FEATURE_LDREX >= 4) */ - - -#if (__ARM_ARCH_ISA_THUMB >= 2) -/** - \brief Rotate Right with Extend (32 bit) - \details Moves each bit of a bitstring right by one bit. - The carry input is shifted in at the left end of the bitstring. - \param [in] value Value to rotate - \return Rotated value - */ -__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rrx %0, %1" : "=r" (result) : "r" (value)); - return (result); -} - - -/** - \brief LDRT Unprivileged (8 bit) - \details Executes a Unprivileged LDRT instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint8_t)result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (16 bit) - \details Executes a Unprivileged LDRT instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint16_t)result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (32 bit) - \details Executes a Unprivileged LDRT instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); - return (result); -} - - -/** - \brief STRT Unprivileged (8 bit) - \details Executes a Unprivileged STRT instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) -{ - __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (16 bit) - \details Executes a Unprivileged STRT instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) -{ - __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (32 bit) - \details Executes a Unprivileged STRT instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) -{ - __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); -} -#endif /* (__ARM_ARCH_ISA_THUMB >= 2) */ - - -#if (__ARM_ARCH >= 8) -/** - \brief Load-Acquire (8 bit) - \details Executes a LDAB instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); - return ((uint8_t)result); /* Add explicit type cast here */ -} - - -/** - \brief Load-Acquire (16 bit) - \details Executes a LDAH instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); - return ((uint16_t)result); /* Add explicit type cast here */ -} - - -/** - \brief Load-Acquire (32 bit) - \details Executes a LDA instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); - return (result); -} - - -/** - \brief Store-Release (8 bit) - \details Executes a STLB instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) -{ - __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); -} - - -/** - \brief Store-Release (16 bit) - \details Executes a STLH instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) -{ - __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); -} - - -/** - \brief Store-Release (32 bit) - \details Executes a STL instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) -{ - __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); -} - - -/** - \brief Load-Acquire Exclusive (8 bit) - \details Executes a LDAB exclusive instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); - return ((uint8_t)result); /* Add explicit type cast here */ -} - - -/** - \brief Load-Acquire Exclusive (16 bit) - \details Executes a LDAH exclusive instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); - return ((uint16_t)result); /* Add explicit type cast here */ -} - - -/** - \brief Load-Acquire Exclusive (32 bit) - \details Executes a LDA exclusive instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); - return (result); -} - - -/** - \brief Store-Release Exclusive (8 bit) - \details Executes a STLB exclusive instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) -{ - uint32_t result; - - __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); - return (result); -} - - -/** - \brief Store-Release Exclusive (16 bit) - \details Executes a STLH exclusive instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) -{ - uint32_t result; - - __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); - return (result); -} - - -/** - \brief Store-Release Exclusive (32 bit) - \details Executes a STL exclusive instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); - return (result); -} - -#endif /* (__ARM_ARCH >= 8) */ - -/** @}*/ /* end of group CMSIS_Core_InstructionInterface */ - - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -/** - \brief Enable IRQ Interrupts - \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. - Can only be executed in Privileged modes. - */ -__STATIC_FORCEINLINE void __enable_irq(void) -{ - __ASM volatile ("cpsie i" : : : "memory"); -} - - -/** - \brief Disable IRQ Interrupts - \details Disables IRQ interrupts by setting special-purpose register PRIMASK. - Can only be executed in Privileged modes. - */ -__STATIC_FORCEINLINE void __disable_irq(void) -{ - __ASM volatile ("cpsid i" : : : "memory"); -} - -#if (__ARM_ARCH_ISA_THUMB >= 2) - /** - \brief Enable FIQ - \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. - Can only be executed in Privileged modes. - */ - __STATIC_FORCEINLINE void __enable_fault_irq(void) - { - __ASM volatile ("cpsie f" : : : "memory"); - } - - - /** - \brief Disable FIQ - \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. - Can only be executed in Privileged modes. - */ - __STATIC_FORCEINLINE void __disable_fault_irq(void) - { - __ASM volatile ("cpsid f" : : : "memory"); - } -#endif - - -/** - \brief Get FPSCR - \details Returns the current value of the Floating Point Status/Control register. - \return Floating Point Status/Control register value - */ -__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) -{ -#if (defined(__ARM_FP) && (__ARM_FP >= 1)) - return (__builtin_arm_get_fpscr()); -#else - return (0U); -#endif -} - - -/** - \brief Set FPSCR - \details Assigns the given value to the Floating Point Status/Control register. - \param [in] fpscr Floating Point Status/Control value to set - */ -__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) -{ -#if (defined(__ARM_FP) && (__ARM_FP >= 1)) - __builtin_arm_set_fpscr(fpscr); -#else - (void)fpscr; -#endif -} - - -/** @} end of CMSIS_Core_RegAccFunctions */ - - -/* ################### Compiler specific Intrinsics ########################### */ -/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics - Access to dedicated SIMD instructions - @{ -*/ - -#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) - #define __SADD8 __sadd8 - #define __QADD8 __qadd8 - #define __SHADD8 __shadd8 - #define __UADD8 __uadd8 - #define __UQADD8 __uqadd8 - #define __UHADD8 __uhadd8 - #define __SSUB8 __ssub8 - #define __QSUB8 __qsub8 - #define __SHSUB8 __shsub8 - #define __USUB8 __usub8 - #define __UQSUB8 __uqsub8 - #define __UHSUB8 __uhsub8 - #define __SADD16 __sadd16 - #define __QADD16 __qadd16 - #define __SHADD16 __shadd16 - #define __UADD16 __uadd16 - #define __UQADD16 __uqadd16 - #define __UHADD16 __uhadd16 - #define __SSUB16 __ssub16 - #define __QSUB16 __qsub16 - #define __SHSUB16 __shsub16 - #define __USUB16 __usub16 - #define __UQSUB16 __uqsub16 - #define __UHSUB16 __uhsub16 - #define __SASX __sasx - #define __QASX __qasx - #define __SHASX __shasx - #define __UASX __uasx - #define __UQASX __uqasx - #define __UHASX __uhasx - #define __SSAX __ssax - #define __QSAX __qsax - #define __SHSAX __shsax - #define __USAX __usax - #define __UQSAX __uqsax - #define __UHSAX __uhsax - #define __USAD8 __usad8 - #define __USADA8 __usada8 - #define __SSAT16 __ssat16 - #define __USAT16 __usat16 - #define __UXTB16 __uxtb16 - #define __UXTAB16 __uxtab16 - #define __SXTB16 __sxtb16 - #define __SXTAB16 __sxtab16 - #define __SMUAD __smuad - #define __SMUADX __smuadx - #define __SMLAD __smlad - #define __SMLADX __smladx - #define __SMLALD __smlald - #define __SMLALDX __smlaldx - #define __SMUSD __smusd - #define __SMUSDX __smusdx - #define __SMLSD __smlsd - #define __SMLSDX __smlsdx - #define __SMLSLD __smlsld - #define __SMLSLDX __smlsldx - #define __SEL __sel - #define __QADD __qadd - #define __QSUB __qsub - - #define __PKHBT(ARG1,ARG2,ARG3) \ - __extension__ \ - ({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - - #define __PKHTB(ARG1,ARG2,ARG3) \ - __extension__ \ - ({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - if (ARG3 == 0) \ - __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ - else \ - __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - - __STATIC_FORCEINLINE uint32_t __SXTB16_RORn(uint32_t op1, uint32_t rotate) - { - uint32_t result; - if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) - { - __ASM volatile("sxtb16 %0, %1, ROR %2" : "=r"(result) : "r"(op1), "i"(rotate)); - } - else - { - result = __SXTB16(__ROR(op1, rotate)); - } - return result; - } - - __STATIC_FORCEINLINE uint32_t __SXTAB16_RORn(uint32_t op1, uint32_t op2, uint32_t rotate) - { - uint32_t result; - if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) - { - __ASM volatile("sxtab16 %0, %1, %2, ROR %3" : "=r"(result) : "r"(op1), "r"(op2), "i"(rotate)); - } - else - { - result = __SXTAB16(op1, __ROR(op2, rotate)); - } - return result; - } - - __STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) - { - int32_t result; - - __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); - return (result); - } -#endif /* (__ARM_FEATURE_DSP == 1) */ -/** @} end of group CMSIS_SIMD_intrinsics */ - -// Include the profile specific settings: -#if __ARM_ARCH_PROFILE == 'A' - #include "a-profile/cmsis_gcc_a.h" -#elif __ARM_ARCH_PROFILE == 'R' - #include "r-profile/cmsis_gcc_r.h" -#elif __ARM_ARCH_PROFILE == 'M' - #include "m-profile/cmsis_gcc_m.h" -#else - #error "Unknown Arm architecture profile" -#endif - -#endif /* __CMSIS_GCC_H */ diff --git a/lib/main/pico-sdk/rp2_common/cmsis/stub/CMSIS/Core/Include/cmsis_iccarm.h b/lib/main/pico-sdk/rp2_common/cmsis/stub/CMSIS/Core/Include/cmsis_iccarm.h deleted file mode 100644 index 65b824b009..0000000000 --- a/lib/main/pico-sdk/rp2_common/cmsis/stub/CMSIS/Core/Include/cmsis_iccarm.h +++ /dev/null @@ -1,1002 +0,0 @@ -/**************************************************************************//** - * @file cmsis_iccarm.h - * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file - * @version V5.3.0 - * @date 14. April 2021 - ******************************************************************************/ - -//------------------------------------------------------------------------------ -// -// Copyright (c) 2017-2021 IAR Systems -// Copyright (c) 2017-2021 Arm Limited. All rights reserved. -// -// SPDX-License-Identifier: Apache-2.0 -// -// Licensed under the Apache License, Version 2.0 (the "License") -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// -//------------------------------------------------------------------------------ - - -#ifndef __CMSIS_ICCARM_H__ -#define __CMSIS_ICCARM_H__ - -#ifndef __ICCARM__ - #error This file should only be compiled by ICCARM -#endif - -#pragma system_include - -#define __IAR_FT _Pragma("inline=forced") __intrinsic - -#if (__VER__ >= 8000000) - #define __ICCARM_V8 1 -#else - #define __ICCARM_V8 0 -#endif - -#ifndef __ALIGNED - #if __ICCARM_V8 - #define __ALIGNED(x) __attribute__((aligned(x))) - #elif (__VER__ >= 7080000) - /* Needs IAR language extensions */ - #define __ALIGNED(x) __attribute__((aligned(x))) - #else - #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. - #define __ALIGNED(x) - #endif -#endif - - -/* Define compiler macros for CPU architecture, used in CMSIS 5. - */ -#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__ -/* Macros already defined */ -#else - #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__) - #define __ARM_ARCH_8M_MAIN__ 1 - #elif defined(__ARM8M_BASELINE__) - #define __ARM_ARCH_8M_BASE__ 1 - #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' - #if __ARM_ARCH == 6 - #define __ARM_ARCH_6M__ 1 - #elif __ARM_ARCH == 7 - #if __ARM_FEATURE_DSP - #define __ARM_ARCH_7EM__ 1 - #else - #define __ARM_ARCH_7M__ 1 - #endif - #endif /* __ARM_ARCH */ - #endif /* __ARM_ARCH_PROFILE == 'M' */ -#endif - -/* Alternativ core deduction for older ICCARM's */ -#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \ - !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__) - #if defined(__ARM6M__) && (__CORE__ == __ARM6M__) - #define __ARM_ARCH_6M__ 1 - #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__) - #define __ARM_ARCH_7M__ 1 - #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__) - #define __ARM_ARCH_7EM__ 1 - #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__) - #define __ARM_ARCH_8M_BASE__ 1 - #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__) - #define __ARM_ARCH_8M_MAIN__ 1 - #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__) - #define __ARM_ARCH_8M_MAIN__ 1 - #else - #error "Unknown target." - #endif -#endif - - - -#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1 - #define __IAR_M0_FAMILY 1 -#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1 - #define __IAR_M0_FAMILY 1 -#else - #define __IAR_M0_FAMILY 0 -#endif - - -#ifndef __ASM - #define __ASM __asm -#endif - -#ifndef __COMPILER_BARRIER - #define __COMPILER_BARRIER() __ASM volatile("":::"memory") -#endif - -#ifndef __INLINE - #define __INLINE inline -#endif - -#ifndef __NO_RETURN - #if __ICCARM_V8 - #define __NO_RETURN __attribute__((__noreturn__)) - #else - #define __NO_RETURN _Pragma("object_attribute=__noreturn") - #endif -#endif - -#ifndef __PACKED - #if __ICCARM_V8 - #define __PACKED __attribute__((packed, aligned(1))) - #else - /* Needs IAR language extensions */ - #define __PACKED __packed - #endif -#endif - -#ifndef __PACKED_STRUCT - #if __ICCARM_V8 - #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) - #else - /* Needs IAR language extensions */ - #define __PACKED_STRUCT __packed struct - #endif -#endif - -#ifndef __PACKED_UNION - #if __ICCARM_V8 - #define __PACKED_UNION union __attribute__((packed, aligned(1))) - #else - /* Needs IAR language extensions */ - #define __PACKED_UNION __packed union - #endif -#endif - -#ifndef __RESTRICT - #if __ICCARM_V8 - #define __RESTRICT __restrict - #else - /* Needs IAR language extensions */ - #define __RESTRICT restrict - #endif -#endif - -#ifndef __STATIC_INLINE - #define __STATIC_INLINE static inline -#endif - -#ifndef __FORCEINLINE - #define __FORCEINLINE _Pragma("inline=forced") -#endif - -#ifndef __STATIC_FORCEINLINE - #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE -#endif - -#ifndef __UNALIGNED_UINT16_READ -#pragma language=save -#pragma language=extended -__IAR_FT uint16_t __iar_uint16_read(void const *ptr) -{ - return *(__packed uint16_t*)(ptr); -} -#pragma language=restore -#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) -#endif - - -#ifndef __UNALIGNED_UINT16_WRITE -#pragma language=save -#pragma language=extended -__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) -{ - *(__packed uint16_t*)(ptr) = val;; -} -#pragma language=restore -#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) -#endif - -#ifndef __UNALIGNED_UINT32_READ -#pragma language=save -#pragma language=extended -__IAR_FT uint32_t __iar_uint32_read(void const *ptr) -{ - return *(__packed uint32_t*)(ptr); -} -#pragma language=restore -#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) -#endif - -#ifndef __UNALIGNED_UINT32_WRITE -#pragma language=save -#pragma language=extended -__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) -{ - *(__packed uint32_t*)(ptr) = val;; -} -#pragma language=restore -#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) -#endif - -#ifndef __UNALIGNED_UINT32 /* deprecated */ -#pragma language=save -#pragma language=extended -__packed struct __iar_u32 { uint32_t v; }; -#pragma language=restore -#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) -#endif - -#ifndef __USED - #if __ICCARM_V8 - #define __USED __attribute__((used)) - #else - #define __USED _Pragma("__root") - #endif -#endif - -#undef __WEAK /* undo the definition from DLib_Defaults.h */ -#ifndef __WEAK - #if __ICCARM_V8 - #define __WEAK __attribute__((weak)) - #else - #define __WEAK _Pragma("__weak") - #endif -#endif - -#ifndef __PROGRAM_START -#define __PROGRAM_START __iar_program_start -#endif - -#ifndef __INITIAL_SP -#define __INITIAL_SP CSTACK$$Limit -#endif - -#ifndef __STACK_LIMIT -#define __STACK_LIMIT CSTACK$$Base -#endif - -#ifndef __VECTOR_TABLE -#define __VECTOR_TABLE __vector_table -#endif - -#ifndef __VECTOR_TABLE_ATTRIBUTE -#define __VECTOR_TABLE_ATTRIBUTE @".intvec" -#endif - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#ifndef __STACK_SEAL -#define __STACK_SEAL STACKSEAL$$Base -#endif - -#ifndef __TZ_STACK_SEAL_SIZE -#define __TZ_STACK_SEAL_SIZE 8U -#endif - -#ifndef __TZ_STACK_SEAL_VALUE -#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL -#endif - -__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { - *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; -} -#endif - -#ifndef __ICCARM_INTRINSICS_VERSION__ - #define __ICCARM_INTRINSICS_VERSION__ 0 -#endif - -#if __ICCARM_INTRINSICS_VERSION__ == 2 - - #if defined(__CLZ) - #undef __CLZ - #endif - #if defined(__REVSH) - #undef __REVSH - #endif - #if defined(__RBIT) - #undef __RBIT - #endif - #if defined(__SSAT) - #undef __SSAT - #endif - #if defined(__USAT) - #undef __USAT - #endif - - #include "iccarm_builtin.h" - - #define __disable_fault_irq __iar_builtin_disable_fiq - #define __disable_irq __iar_builtin_disable_interrupt - #define __enable_fault_irq __iar_builtin_enable_fiq - #define __enable_irq __iar_builtin_enable_interrupt - #define __arm_rsr __iar_builtin_rsr - #define __arm_wsr __iar_builtin_wsr - - - #define __get_APSR() (__arm_rsr("APSR")) - #define __get_BASEPRI() (__arm_rsr("BASEPRI")) - #define __get_CONTROL() (__arm_rsr("CONTROL")) - #define __get_FAULTMASK() (__arm_rsr("FAULTMASK")) - - #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) - #define __get_FPSCR() (__arm_rsr("FPSCR")) - #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE))) - #else - #define __get_FPSCR() ( 0 ) - #define __set_FPSCR(VALUE) ((void)VALUE) - #endif - - #define __get_IPSR() (__arm_rsr("IPSR")) - #define __get_MSP() (__arm_rsr("MSP")) - #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - #define __get_MSPLIM() (0U) - #else - #define __get_MSPLIM() (__arm_rsr("MSPLIM")) - #endif - #define __get_PRIMASK() (__arm_rsr("PRIMASK")) - #define __get_PSP() (__arm_rsr("PSP")) - - #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - #define __get_PSPLIM() (0U) - #else - #define __get_PSPLIM() (__arm_rsr("PSPLIM")) - #endif - - #define __get_xPSR() (__arm_rsr("xPSR")) - - #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE))) - #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE))) - -__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) -{ - __arm_wsr("CONTROL", control); - __iar_builtin_ISB(); -} - - #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE))) - #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE))) - - #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - #define __set_MSPLIM(VALUE) ((void)(VALUE)) - #else - #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE))) - #endif - #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE))) - #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE))) - #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - #define __set_PSPLIM(VALUE) ((void)(VALUE)) - #else - #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE))) - #endif - - #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS")) - -__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) -{ - __arm_wsr("CONTROL_NS", control); - __iar_builtin_ISB(); -} - - #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS")) - #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE))) - #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS")) - #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE))) - #define __TZ_get_SP_NS() (__arm_rsr("SP_NS")) - #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE))) - #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS")) - #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE))) - #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS")) - #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE))) - #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS")) - #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE))) - - #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - #define __TZ_get_PSPLIM_NS() (0U) - #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE)) - #else - #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS")) - #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE))) - #endif - - #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS")) - #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE))) - - #define __NOP __iar_builtin_no_operation - - #define __CLZ __iar_builtin_CLZ - #define __CLREX __iar_builtin_CLREX - - #define __DMB __iar_builtin_DMB - #define __DSB __iar_builtin_DSB - #define __ISB __iar_builtin_ISB - - #define __LDREXB __iar_builtin_LDREXB - #define __LDREXH __iar_builtin_LDREXH - #define __LDREXW __iar_builtin_LDREX - - #define __RBIT __iar_builtin_RBIT - #define __REV __iar_builtin_REV - #define __REV16 __iar_builtin_REV16 - - __IAR_FT int16_t __REVSH(int16_t val) - { - return (int16_t) __iar_builtin_REVSH(val); - } - - #define __ROR __iar_builtin_ROR - #define __RRX __iar_builtin_RRX - - #define __SEV __iar_builtin_SEV - - #if !__IAR_M0_FAMILY - #define __SSAT __iar_builtin_SSAT - #endif - - #define __STREXB __iar_builtin_STREXB - #define __STREXH __iar_builtin_STREXH - #define __STREXW __iar_builtin_STREX - - #if !__IAR_M0_FAMILY - #define __USAT __iar_builtin_USAT - #endif - - #define __WFE __iar_builtin_WFE - #define __WFI __iar_builtin_WFI - - #if __ARM_MEDIA__ - #define __SADD8 __iar_builtin_SADD8 - #define __QADD8 __iar_builtin_QADD8 - #define __SHADD8 __iar_builtin_SHADD8 - #define __UADD8 __iar_builtin_UADD8 - #define __UQADD8 __iar_builtin_UQADD8 - #define __UHADD8 __iar_builtin_UHADD8 - #define __SSUB8 __iar_builtin_SSUB8 - #define __QSUB8 __iar_builtin_QSUB8 - #define __SHSUB8 __iar_builtin_SHSUB8 - #define __USUB8 __iar_builtin_USUB8 - #define __UQSUB8 __iar_builtin_UQSUB8 - #define __UHSUB8 __iar_builtin_UHSUB8 - #define __SADD16 __iar_builtin_SADD16 - #define __QADD16 __iar_builtin_QADD16 - #define __SHADD16 __iar_builtin_SHADD16 - #define __UADD16 __iar_builtin_UADD16 - #define __UQADD16 __iar_builtin_UQADD16 - #define __UHADD16 __iar_builtin_UHADD16 - #define __SSUB16 __iar_builtin_SSUB16 - #define __QSUB16 __iar_builtin_QSUB16 - #define __SHSUB16 __iar_builtin_SHSUB16 - #define __USUB16 __iar_builtin_USUB16 - #define __UQSUB16 __iar_builtin_UQSUB16 - #define __UHSUB16 __iar_builtin_UHSUB16 - #define __SASX __iar_builtin_SASX - #define __QASX __iar_builtin_QASX - #define __SHASX __iar_builtin_SHASX - #define __UASX __iar_builtin_UASX - #define __UQASX __iar_builtin_UQASX - #define __UHASX __iar_builtin_UHASX - #define __SSAX __iar_builtin_SSAX - #define __QSAX __iar_builtin_QSAX - #define __SHSAX __iar_builtin_SHSAX - #define __USAX __iar_builtin_USAX - #define __UQSAX __iar_builtin_UQSAX - #define __UHSAX __iar_builtin_UHSAX - #define __USAD8 __iar_builtin_USAD8 - #define __USADA8 __iar_builtin_USADA8 - #define __SSAT16 __iar_builtin_SSAT16 - #define __USAT16 __iar_builtin_USAT16 - #define __UXTB16 __iar_builtin_UXTB16 - #define __UXTAB16 __iar_builtin_UXTAB16 - #define __SXTB16 __iar_builtin_SXTB16 - #define __SXTAB16 __iar_builtin_SXTAB16 - #define __SMUAD __iar_builtin_SMUAD - #define __SMUADX __iar_builtin_SMUADX - #define __SMMLA __iar_builtin_SMMLA - #define __SMLAD __iar_builtin_SMLAD - #define __SMLADX __iar_builtin_SMLADX - #define __SMLALD __iar_builtin_SMLALD - #define __SMLALDX __iar_builtin_SMLALDX - #define __SMUSD __iar_builtin_SMUSD - #define __SMUSDX __iar_builtin_SMUSDX - #define __SMLSD __iar_builtin_SMLSD - #define __SMLSDX __iar_builtin_SMLSDX - #define __SMLSLD __iar_builtin_SMLSLD - #define __SMLSLDX __iar_builtin_SMLSLDX - #define __SEL __iar_builtin_SEL - #define __QADD __iar_builtin_QADD - #define __QSUB __iar_builtin_QSUB - #define __PKHBT __iar_builtin_PKHBT - #define __PKHTB __iar_builtin_PKHTB - #endif - -#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ - - #if __IAR_M0_FAMILY - /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ - #define __CLZ __cmsis_iar_clz_not_active - #define __SSAT __cmsis_iar_ssat_not_active - #define __USAT __cmsis_iar_usat_not_active - #define __RBIT __cmsis_iar_rbit_not_active - #define __get_APSR __cmsis_iar_get_APSR_not_active - #endif - - - #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) - #define __get_FPSCR __cmsis_iar_get_FPSR_not_active - #define __set_FPSCR __cmsis_iar_set_FPSR_not_active - #endif - - #ifdef __INTRINSICS_INCLUDED - #error intrinsics.h is already included previously! - #endif - - #include - - #if __IAR_M0_FAMILY - /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ - #undef __CLZ - #undef __SSAT - #undef __USAT - #undef __RBIT - #undef __get_APSR - - __STATIC_INLINE uint8_t __CLZ(uint32_t data) - { - if (data == 0U) { return 32U; } - - uint32_t count = 0U; - uint32_t mask = 0x80000000U; - - while ((data & mask) == 0U) - { - count += 1U; - mask = mask >> 1U; - } - return count; - } - - __STATIC_INLINE uint32_t __RBIT(uint32_t v) - { - uint8_t sc = 31U; - uint32_t r = v; - for (v >>= 1U; v; v >>= 1U) - { - r <<= 1U; - r |= v & 1U; - sc--; - } - return (r << sc); - } - - __STATIC_INLINE uint32_t __get_APSR(void) - { - uint32_t res; - __asm("MRS %0,APSR" : "=r" (res)); - return res; - } - - #endif - - #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) - #undef __get_FPSCR - #undef __set_FPSCR - #define __get_FPSCR() (0) - #define __set_FPSCR(VALUE) ((void)VALUE) - #endif - - #pragma diag_suppress=Pe940 - #pragma diag_suppress=Pe177 - - #define __enable_irq __enable_interrupt - #define __disable_irq __disable_interrupt - #define __NOP __no_operation - - #define __get_xPSR __get_PSR - - #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0) - - __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) - { - return __LDREX((unsigned long *)ptr); - } - - __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) - { - return __STREX(value, (unsigned long *)ptr); - } - #endif - - - /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ - #if (__CORTEX_M >= 0x03) - - __IAR_FT uint32_t __RRX(uint32_t value) - { - uint32_t result; - __ASM volatile("RRX %0, %1" : "=r"(result) : "r" (value)); - return(result); - } - - __IAR_FT void __set_BASEPRI_MAX(uint32_t value) - { - __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value)); - } - - - #define __enable_fault_irq __enable_fiq - #define __disable_fault_irq __disable_fiq - - - #endif /* (__CORTEX_M >= 0x03) */ - - __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) - { - return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); - } - - #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) - - __IAR_FT uint32_t __get_MSPLIM(void) - { - uint32_t res; - #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - res = 0U; - #else - __asm volatile("MRS %0,MSPLIM" : "=r" (res)); - #endif - return res; - } - - __IAR_FT void __set_MSPLIM(uint32_t value) - { - #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - (void)value; - #else - __asm volatile("MSR MSPLIM,%0" :: "r" (value)); - #endif - } - - __IAR_FT uint32_t __get_PSPLIM(void) - { - uint32_t res; - #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - res = 0U; - #else - __asm volatile("MRS %0,PSPLIM" : "=r" (res)); - #endif - return res; - } - - __IAR_FT void __set_PSPLIM(uint32_t value) - { - #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - (void)value; - #else - __asm volatile("MSR PSPLIM,%0" :: "r" (value)); - #endif - } - - __IAR_FT uint32_t __TZ_get_CONTROL_NS(void) - { - uint32_t res; - __asm volatile("MRS %0,CONTROL_NS" : "=r" (res)); - return res; - } - - __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) - { - __asm volatile("MSR CONTROL_NS,%0" :: "r" (value)); - __iar_builtin_ISB(); - } - - __IAR_FT uint32_t __TZ_get_PSP_NS(void) - { - uint32_t res; - __asm volatile("MRS %0,PSP_NS" : "=r" (res)); - return res; - } - - __IAR_FT void __TZ_set_PSP_NS(uint32_t value) - { - __asm volatile("MSR PSP_NS,%0" :: "r" (value)); - } - - __IAR_FT uint32_t __TZ_get_MSP_NS(void) - { - uint32_t res; - __asm volatile("MRS %0,MSP_NS" : "=r" (res)); - return res; - } - - __IAR_FT void __TZ_set_MSP_NS(uint32_t value) - { - __asm volatile("MSR MSP_NS,%0" :: "r" (value)); - } - - __IAR_FT uint32_t __TZ_get_SP_NS(void) - { - uint32_t res; - __asm volatile("MRS %0,SP_NS" : "=r" (res)); - return res; - } - __IAR_FT void __TZ_set_SP_NS(uint32_t value) - { - __asm volatile("MSR SP_NS,%0" :: "r" (value)); - } - - __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void) - { - uint32_t res; - __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res)); - return res; - } - - __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value) - { - __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value)); - } - - __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void) - { - uint32_t res; - __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res)); - return res; - } - - __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value) - { - __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value)); - } - - __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void) - { - uint32_t res; - __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res)); - return res; - } - - __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value) - { - __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value)); - } - - __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) - { - uint32_t res; - #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - res = 0U; - #else - __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res)); - #endif - return res; - } - - __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) - { - #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - (void)value; - #else - __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value)); - #endif - } - - __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) - { - uint32_t res; - __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res)); - return res; - } - - __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value) - { - __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value)); - } - - #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ - -#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ - -#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) - -#if __IAR_M0_FAMILY - __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) - { - if ((sat >= 1U) && (sat <= 32U)) - { - const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); - const int32_t min = -1 - max ; - if (val > max) - { - return max; - } - else if (val < min) - { - return min; - } - } - return val; - } - - __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) - { - if (sat <= 31U) - { - const uint32_t max = ((1U << sat) - 1U); - if (val > (int32_t)max) - { - return max; - } - else if (val < 0) - { - return 0U; - } - } - return (uint32_t)val; - } -#endif - -#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ - - __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) - { - uint32_t res; - __ASM volatile ("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); - return ((uint8_t)res); - } - - __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) - { - uint32_t res; - __ASM volatile ("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); - return ((uint16_t)res); - } - - __IAR_FT uint32_t __LDRT(volatile uint32_t *addr) - { - uint32_t res; - __ASM volatile ("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); - return res; - } - - __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) - { - __ASM volatile ("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); - } - - __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) - { - __ASM volatile ("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); - } - - __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) - { - __ASM volatile ("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory"); - } - -#endif /* (__CORTEX_M >= 0x03) */ - -#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) - - - __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) - { - uint32_t res; - __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); - return ((uint8_t)res); - } - - __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) - { - uint32_t res; - __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); - return ((uint16_t)res); - } - - __IAR_FT uint32_t __LDA(volatile uint32_t *ptr) - { - uint32_t res; - __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); - return res; - } - - __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) - { - __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); - } - - __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) - { - __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); - } - - __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) - { - __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); - } - - __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) - { - uint32_t res; - __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); - return ((uint8_t)res); - } - - __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) - { - uint32_t res; - __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); - return ((uint16_t)res); - } - - __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) - { - uint32_t res; - __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); - return res; - } - - __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) - { - uint32_t res; - __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); - return res; - } - - __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) - { - uint32_t res; - __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); - return res; - } - - __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) - { - uint32_t res; - __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); - return res; - } - -#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ - -#undef __IAR_FT -#undef __IAR_M0_FAMILY -#undef __ICCARM_V8 - -#pragma diag_default=Pe940 -#pragma diag_default=Pe177 - -#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) - -#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) - -#endif /* __CMSIS_ICCARM_H__ */ diff --git a/lib/main/pico-sdk/rp2_common/cmsis/stub/CMSIS/Core/Include/cmsis_version.h b/lib/main/pico-sdk/rp2_common/cmsis/stub/CMSIS/Core/Include/cmsis_version.h deleted file mode 100644 index 849a8a4a15..0000000000 --- a/lib/main/pico-sdk/rp2_common/cmsis/stub/CMSIS/Core/Include/cmsis_version.h +++ /dev/null @@ -1,44 +0,0 @@ -/* - * Copyright (c) 2009-2023 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* - * CMSIS Core Version Definitions - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CMSIS_VERSION_H -#define __CMSIS_VERSION_H - -/* CMSIS-Core(M) Version definitions */ -#define __CM_CMSIS_VERSION_MAIN ( 6U) /*!< \brief [31:16] CMSIS-Core(M) main version */ -#define __CM_CMSIS_VERSION_SUB ( 1U) /*!< \brief [15:0] CMSIS-Core(M) sub version */ -#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ - __CM_CMSIS_VERSION_SUB ) /*!< \brief CMSIS Core(M) version number */ - -/* CMSIS-Core(A) Version definitions */ -#define __CA_CMSIS_VERSION_MAIN ( 6U) /*!< \brief [31:16] CMSIS-Core(A) main version */ -#define __CA_CMSIS_VERSION_SUB ( 1U) /*!< \brief [15:0] CMSIS-Core(A) sub version */ -#define __CA_CMSIS_VERSION ((__CA_CMSIS_VERSION_MAIN << 16U) | \ - __CA_CMSIS_VERSION_SUB ) /*!< \brief CMSIS-Core(A) version number */ - -#endif diff --git a/lib/main/pico-sdk/rp2_common/cmsis/stub/CMSIS/Core/Include/core_cm0plus.h b/lib/main/pico-sdk/rp2_common/cmsis/stub/CMSIS/Core/Include/core_cm0plus.h deleted file mode 100644 index 1ee9457560..0000000000 --- a/lib/main/pico-sdk/rp2_common/cmsis/stub/CMSIS/Core/Include/core_cm0plus.h +++ /dev/null @@ -1,1103 +0,0 @@ -/* - * Copyright (c) 2009-2024 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* - * CMSIS Cortex-M0+ Core Peripheral Access Layer Header File - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#elif defined ( __GNUC__ ) - #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ -#endif - -#ifndef __CORE_CM0PLUS_H_GENERIC -#define __CORE_CM0PLUS_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex-M0+ - @{ - */ - -#include "cmsis_version.h" - -/* CMSIS CM0+ definitions */ - -#define __CORTEX_M (0U) /*!< Cortex-M Core */ - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0U - -#if defined ( __CC_ARM ) - #if defined (__TARGET_FPU_VFP) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined (__ARM_FP) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined (__ti__) - #if defined (__ARM_FP) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined (__ARMVFP__) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TI_ARM__ ) - #if defined (__TI_VFP_SUPPORT__) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined (__FPU_VFP__) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM0PLUS_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM0PLUS_H_DEPENDANT -#define __CORE_CM0PLUS_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM0PLUS_REV - #define __CM0PLUS_REV 0x0000U - #warning "__CM0PLUS_REV not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __VTOR_PRESENT - #define __VTOR_PRESENT 0U - #warning "__VTOR_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 2U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex-M0+ */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core MPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/** \brief APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/** \brief IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/** \brief xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/** \brief CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[31U]; - __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RESERVED1[31U]; - __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[31U]; - __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[31U]; - uint32_t RESERVED4[64U]; - __IOM uint32_t IPR[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ -} NVIC_Type; - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ -#else - uint32_t RESERVED0; -#endif - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED1; - __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ -} SCB_Type; - -/** \brief SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/** \brief SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) -/** \brief SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#endif - -/** \brief SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANNESS_Pos 15U /*!< SCB AIRCR: ENDIANNESS Position */ -#define SCB_AIRCR_ENDIANNESS_Msk (1UL << SCB_AIRCR_ENDIANNESS_Pos) /*!< SCB AIRCR: ENDIANNESS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/** \brief SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/** \brief SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -/** \brief SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/** \brief SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/** \brief SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/** \brief SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/** \brief SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ -} MPU_Type; - -#define MPU_TYPE_RALIASES 1U - -/** \brief MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/** \brief MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/** \brief MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/** \brief MPU Region Base Address Register Definitions */ -#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ - -/** \brief MPU Region Attribute and Size Register Definitions */ -#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. - Therefore they are not covered by the Cortex-M0+ header file. - @{ - */ -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -/*@} */ - - -/** - \defgroup CMSIS_deprecated_aliases Backwards Compatibility Aliases - \brief Alias definitions present for backwards compatibility for deprecated symbols. - @{ - */ - -#ifndef CMSIS_DISABLE_DEPRECATED - -#define SCB_AIRCR_ENDIANESS_Pos SCB_AIRCR_ENDIANNESS_Pos -#define SCB_AIRCR_ENDIANESS_Msk SCB_AIRCR_ENDIANNESS_Msk - -#endif // CMSIS_DISABLE_DEPRECATED - -/*@} */ - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifdef CMSIS_NVIC_VIRTUAL - #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE - #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" - #endif - #include CMSIS_NVIC_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping - #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping - #define NVIC_EnableIRQ __NVIC_EnableIRQ - #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ - #define NVIC_DisableIRQ __NVIC_DisableIRQ - #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ - #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ - #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ -/* NVIC_GetActive not available for Cortex-M0+ */ - #define NVIC_SetPriority __NVIC_SetPriority - #define NVIC_GetPriority __NVIC_GetPriority - #define NVIC_SystemReset __NVIC_SystemReset -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifdef CMSIS_VECTAB_VIRTUAL - #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE - #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" - #endif - #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetVector __NVIC_SetVector - #define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - -/* The following EXC_RETURN values are saved the LR on exception entry */ -#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ -#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ -#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ - - -/* Interrupt Priorities are WORD accessible only under Armv6-M */ -/* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) -#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) -#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) - -#define __NVIC_SetPriorityGrouping(X) (void)(X) -#define __NVIC_GetPriorityGrouping() (0U) - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - __COMPILER_BARRIER(); - NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __COMPILER_BARRIER(); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } - else - { - SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - VTOR must been relocated to SRAM before. - If VTOR is not present address 0 must be mapped to SRAM. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR); - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; -#else - uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ - *(vectors + (int32_t)IRQn) = vector; /* use pointer arithmetic to access vector */ -#endif - /* ARM Application Note 321 states that the M0+ does not require the architectural barrier */ -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR); - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; -#else - uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ - return *(vectors + (int32_t)IRQn); /* use pointer arithmetic to access vector */ -#endif -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - -/* ########################## MPU functions #################################### */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - -#include "m-profile/armv7m_mpu.h" - -#endif - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - return 0U; /* No FPU */ -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM0PLUS_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/lib/main/pico-sdk/rp2_common/cmsis/stub/CMSIS/Core/Include/core_cm33.h b/lib/main/pico-sdk/rp2_common/cmsis/stub/CMSIS/Core/Include/core_cm33.h deleted file mode 100644 index 464bfdd269..0000000000 --- a/lib/main/pico-sdk/rp2_common/cmsis/stub/CMSIS/Core/Include/core_cm33.h +++ /dev/null @@ -1,3245 +0,0 @@ -/* - * Copyright (c) 2009-2024 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* - * CMSIS Cortex-M33 Core Peripheral Access Layer Header File - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#elif defined ( __GNUC__ ) - #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ -#endif - -#ifndef __CORE_CM33_H_GENERIC -#define __CORE_CM33_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_M33 - @{ - */ - -#include "cmsis_version.h" - -/* CMSIS CM33 definitions */ - -#define __CORTEX_M (33U) /*!< Cortex-M Core */ - -/** __FPU_USED indicates whether an FPU is used or not. - For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. -*/ -#if defined ( __CC_ARM ) - #if defined (__TARGET_FPU_VFP) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - - #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) - #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) - #define __DSP_USED 1U - #else - #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U - #endif - #else - #define __DSP_USED 0U - #endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined (__ARM_FP) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - - #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) - #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) - #define __DSP_USED 1U - #else - #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U - #endif - #else - #define __DSP_USED 0U - #endif - -#elif defined (__ti__) - #if defined (__ARM_FP) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - - #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) - #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) - #define __DSP_USED 1U - #else - #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U - #endif - #else - #define __DSP_USED 0U - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - - #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) - #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) - #define __DSP_USED 1U - #else - #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U - #endif - #else - #define __DSP_USED 0U - #endif - -#elif defined ( __ICCARM__ ) - #if defined (__ARMVFP__) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - - #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) - #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) - #define __DSP_USED 1U - #else - #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U - #endif - #else - #define __DSP_USED 0U - #endif - -#elif defined ( __TI_ARM__ ) - #if defined (__TI_VFP_SUPPORT__) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __TASKING__ ) - #if defined (__FPU_VFP__) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM33_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM33_H_DEPENDANT -#define __CORE_CM33_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM33_REV - #define __CM33_REV 0x0000U - #warning "__CM33_REV not defined in device header file; using default!" - #endif - - #ifndef __FPU_PRESENT - #define __FPU_PRESENT 0U - #warning "__FPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __SAUREGION_PRESENT - #define __SAUREGION_PRESENT 0U - #warning "__SAUREGION_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __DSP_PRESENT - #define __DSP_PRESENT 0U - #warning "__DSP_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __VTOR_PRESENT - #define __VTOR_PRESENT 1U - #warning "__VTOR_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 3U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex_M33 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - - Core SAU Register - - Core FPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/** \brief APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - -#define APSR_Q_Pos 27U /*!< APSR: Q Position */ -#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ - -#define APSR_GE_Pos 16U /*!< APSR: GE Position */ -#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/** \brief IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/** \brief xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ -#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ - -#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ -#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ -#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ - uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ - uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ - uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/** \brief CONTROL Register Definitions */ -#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ -#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ - -#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ -#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ - -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[16U]; - __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RESERVED1[16U]; - __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[16U]; - __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[16U]; - __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[16U]; - __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ - uint32_t RESERVED5[16U]; - __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED6[580U]; - __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/** \brief NVIC Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ - __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ - __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ - __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ - __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ - __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ - uint32_t RESERVED7[21U]; - __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ - __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ - uint32_t RESERVED3[69U]; - __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ - uint32_t RESERVED4[15U]; - __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ - __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ - uint32_t RESERVED5[1U]; - __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ - uint32_t RESERVED6[1U]; - __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ - __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ - __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ - __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ - __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ - __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ - __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ - __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ - __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ -} SCB_Type; - -/** \brief SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/** \brief SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ -#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ - -#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ -#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ - -#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ -#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ -#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/** \brief SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/** \brief SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANNESS_Pos 15U /*!< SCB AIRCR: ENDIANNESS Position */ -#define SCB_AIRCR_ENDIANNESS_Msk (1UL << SCB_AIRCR_ENDIANNESS_Pos) /*!< SCB AIRCR: ENDIANNESS Mask */ - -#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ -#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ - -#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ -#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ -#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/** \brief SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ -#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/** \brief SCB Configuration Control Register Definitions */ -#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ -#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ - -#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ -#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ - -#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ -#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ - -#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ -#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -/** \brief SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ -#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ - -#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ -#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ - -#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ -#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ - -#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ -#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ - -#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ -#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ -#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/** \brief SCB Configurable Fault Status Register Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/** \brief SCB MemManage Fault Status Register Definitions (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ -#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ - -#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ -#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ - -#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ -#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ - -#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ -#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ - -#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ -#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ - -#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ -#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ - -/** \brief SCB BusFault Status Register Definitions (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ -#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ - -#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ -#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ - -#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ -#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ - -#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ -#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ - -#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ -#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ - -#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ -#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ - -#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ -#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ - -/** \brief SCB UsageFault Status Register Definitions (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ -#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ - -#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ -#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ - -#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ -#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ - -#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ -#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ - -#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ -#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ - -#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ -#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ - -#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ -#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ - -/** \brief SCB Hard Fault Status Register Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/** \brief SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ - -/** \brief SCB Non-Secure Access Control Register Definitions */ -#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ -#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ - -#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ -#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ - -#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ -#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ - -/** \brief SCB Cache Level ID Register Definitions */ -#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ -#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ - -#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ -#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ - -/** \brief SCB Cache Type Register Definitions */ -#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ -#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ - -#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ -#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ - -#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ -#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ - -#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ -#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ - -#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ -#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ - -/** \brief SCB Cache Size ID Register Definitions */ -#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ -#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ - -#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ -#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ - -#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ -#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ - -#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ -#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ - -#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ -#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ - -#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ -#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ - -#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ -#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ - -/** \brief SCB Cache Size Selection Register Definitions */ -#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ -#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ - -#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ -#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ - -/** \brief SCB Software Triggered Interrupt Register Definitions */ -#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ -#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ - -/** \brief SCB D-Cache Invalidate by Set-way Register Definitions */ -#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ -#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ - -#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ -#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ - -/** \brief SCB D-Cache Clean by Set-way Register Definitions */ -#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ -#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ - -#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ -#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ - -/** \brief SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ -#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ -#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ - -#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ -#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** - \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ - __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ -} SCnSCB_Type; - -/** \brief SCnSCB Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/** \brief SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/** \brief SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/** \brief SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/** \brief SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** - \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __OM union - { - __OM uint8_t u8; /*!< Offset: 0x000 ( /W) Stimulus Port 8-bit */ - __OM uint16_t u16; /*!< Offset: 0x000 ( /W) Stimulus Port 16-bit */ - __OM uint32_t u32; /*!< Offset: 0x000 ( /W) Stimulus Port 32-bit */ - } PORT [32U]; /*!< Offset: 0x000 ( /W) Stimulus Port Registers */ - uint32_t RESERVED0[864U]; - __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) Trace Enable Register */ - uint32_t RESERVED1[15U]; - __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) Trace Privilege Register */ - uint32_t RESERVED2[15U]; - __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) Trace Control Register */ - uint32_t RESERVED3[27U]; - __IM uint32_t ITREAD; /*!< Offset: 0xEF0 (R/ ) Integration Read Register */ - uint32_t RESERVED4[1U]; - __OM uint32_t ITWRITE; /*!< Offset: 0xEF8 ( /W) Integration Write Register */ - uint32_t RESERVED5[1U]; - __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control Register */ - uint32_t RESERVED6[46U]; - __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ - uint32_t RESERVED7[3U]; - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ -} ITM_Type; - -/** \brief ITM Stimulus Port Register Definitions */ -#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ -#define ITM_STIM_DISABLED_Msk (1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ - -#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ -#define ITM_STIM_FIFOREADY_Msk (1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ - -/** \brief ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ - -/** \brief ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ -#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ - -#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ -#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ - -#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ - -/** \brief ITM Integration Read Register Definitions */ -#define ITM_ITREAD_AFVALID_Pos 1U /*!< ITM ITREAD: AFVALID Position */ -#define ITM_ITREAD_AFVALID_Msk (1UL << ITM_ITREAD_AFVALID_Pos) /*!< ITM ITREAD: AFVALID Mask */ - -#define ITM_ITREAD_ATREADY_Pos 0U /*!< ITM ITREAD: ATREADY Position */ -#define ITM_ITREAD_ATREADY_Msk (1UL /*<< ITM_ITREAD_ATREADY_Pos*/) /*!< ITM ITREAD: ATREADY Mask */ - -/** \brief ITM Integration Write Register Definitions */ -#define ITM_ITWRITE_AFVALID_Pos 1U /*!< ITM ITWRITE: AFVALID Position */ -#define ITM_ITWRITE_AFVALID_Msk (1UL << ITM_ITWRITE_AFVALID_Pos) /*!< ITM ITWRITE: AFVALID Mask */ - -#define ITM_ITWRITE_ATREADY_Pos 0U /*!< ITM ITWRITE: ATREADY Position */ -#define ITM_ITWRITE_ATREADY_Msk (1UL /*<< ITM_ITWRITE_ATREADY_Pos*/) /*!< ITM ITWRITE: ATREADY Mask */ - -/** \brief ITM Integration Mode Control Register Definitions */ -#define ITM_ITCTRL_IME_Pos 0U /*!< ITM ITCTRL: IME Position */ -#define ITM_ITCTRL_IME_Msk (1UL /*<< ITM_ITCTRL_IME_Pos*/) /*!< ITM ITCTRL: IME Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - uint32_t RESERVED3[1U]; - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED4[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - uint32_t RESERVED5[1U]; - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED6[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - uint32_t RESERVED7[1U]; - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ - uint32_t RESERVED14[984U]; - __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Type Architecture Register */ - uint32_t RESERVED15[3U]; - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ -} DWT_Type; - -/** \brief DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ -#define DWT_CTRL_CYCDISS_Msk (1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ - -/** \brief DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ - -/** \brief DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ - -/** \brief DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/** \brief DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ - -/** \brief DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/** \brief DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ -#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ - -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ -#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ - -#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ -#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPIU Trace Port Interface Unit (TPIU) - \brief Type definitions for the Trace Port Interface Unit (TPIU) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Unit Register (TPIU). - */ -typedef struct -{ - __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ - uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ - __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ - __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ - uint32_t RESERVED4[1U]; - __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ - __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ - __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39U]; - __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8U]; - __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ -} TPIU_Type; - -/** \brief TPIU Asynchronous Clock Prescaler Register Definitions */ -#define TPIU_ACPR_PRESCALER_Pos 0U /*!< TPIU ACPR: PRESCALER Position */ -#define TPIU_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPIU_ACPR_PRESCALER_Pos*/) /*!< TPIU ACPR: PRESCALER Mask */ - -/** \brief TPIU Selected Pin Protocol Register Definitions */ -#define TPIU_SPPR_TXMODE_Pos 0U /*!< TPIU SPPR: TXMODE Position */ -#define TPIU_SPPR_TXMODE_Msk (0x3UL /*<< TPIU_SPPR_TXMODE_Pos*/) /*!< TPIU SPPR: TXMODE Mask */ - -/** \brief TPIU Formatter and Flush Status Register Definitions */ -#define TPIU_FFSR_FtNonStop_Pos 3U /*!< TPIU FFSR: FtNonStop Position */ -#define TPIU_FFSR_FtNonStop_Msk (1UL << TPIU_FFSR_FtNonStop_Pos) /*!< TPIU FFSR: FtNonStop Mask */ - -#define TPIU_FFSR_TCPresent_Pos 2U /*!< TPIU FFSR: TCPresent Position */ -#define TPIU_FFSR_TCPresent_Msk (1UL << TPIU_FFSR_TCPresent_Pos) /*!< TPIU FFSR: TCPresent Mask */ - -#define TPIU_FFSR_FtStopped_Pos 1U /*!< TPIU FFSR: FtStopped Position */ -#define TPIU_FFSR_FtStopped_Msk (1UL << TPIU_FFSR_FtStopped_Pos) /*!< TPIU FFSR: FtStopped Mask */ - -#define TPIU_FFSR_FlInProg_Pos 0U /*!< TPIU FFSR: FlInProg Position */ -#define TPIU_FFSR_FlInProg_Msk (1UL /*<< TPIU_FFSR_FlInProg_Pos*/) /*!< TPIU FFSR: FlInProg Mask */ - -/** \brief TPIU Formatter and Flush Control Register Definitions */ -#define TPIU_FFCR_TrigIn_Pos 8U /*!< TPIU FFCR: TrigIn Position */ -#define TPIU_FFCR_TrigIn_Msk (1UL << TPIU_FFCR_TrigIn_Pos) /*!< TPIU FFCR: TrigIn Mask */ - -#define TPIU_FFCR_FOnMan_Pos 6U /*!< TPIU FFCR: FOnMan Position */ -#define TPIU_FFCR_FOnMan_Msk (1UL << TPIU_FFCR_FOnMan_Pos) /*!< TPIU FFCR: FOnMan Mask */ - -#define TPIU_FFCR_EnFCont_Pos 1U /*!< TPIU FFCR: EnFCont Position */ -#define TPIU_FFCR_EnFCont_Msk (1UL << TPIU_FFCR_EnFCont_Pos) /*!< TPIU FFCR: EnFCont Mask */ - -/** \brief TPIU Periodic Synchronization Control Register Definitions */ -#define TPIU_PSCR_PSCount_Pos 0U /*!< TPIU PSCR: PSCount Position */ -#define TPIU_PSCR_PSCount_Msk (0x1FUL /*<< TPIU_PSCR_PSCount_Pos*/) /*!< TPIU PSCR: TPSCount Mask */ - -/** \brief TPIU TRIGGER Register Definitions */ -#define TPIU_TRIGGER_TRIGGER_Pos 0U /*!< TPIU TRIGGER: TRIGGER Position */ -#define TPIU_TRIGGER_TRIGGER_Msk (1UL /*<< TPIU_TRIGGER_TRIGGER_Pos*/) /*!< TPIU TRIGGER: TRIGGER Mask */ - -/** \brief TPIU Integration Test FIFO Test Data 0 Register Definitions */ -#define TPIU_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPIU ITFTTD0: ATB Interface 2 ATVALIDPosition */ -#define TPIU_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPIU ITFTTD0: ATB Interface 2 ATVALID Mask */ - -#define TPIU_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPIU ITFTTD0: ATB Interface 2 byte count Position */ -#define TPIU_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPIU ITFTTD0: ATB Interface 2 byte count Mask */ - -#define TPIU_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPIU ITFTTD0: ATB Interface 1 ATVALID Position */ -#define TPIU_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 ATVALID Mask */ - -#define TPIU_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPIU ITFTTD0: ATB Interface 1 byte count Position */ -#define TPIU_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 byte countt Mask */ - -#define TPIU_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPIU ITFTTD0: ATB Interface 1 data2 Position */ -#define TPIU_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPIU_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 data2 Mask */ - -#define TPIU_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPIU ITFTTD0: ATB Interface 1 data1 Position */ -#define TPIU_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPIU_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 data1 Mask */ - -#define TPIU_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPIU ITFTTD0: ATB Interface 1 data0 Position */ -#define TPIU_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPIU_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPIU ITFTTD0: ATB Interface 1 data0 Mask */ - -/** \brief TPIU Integration Test ATB Control Register 2 Register Definitions */ -#define TPIU_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPIU ITATBCTR2: AFVALID2S Position */ -#define TPIU_ITATBCTR2_AFVALID2S_Msk (1UL << TPIU_ITATBCTR2_AFVALID2S_Pos) /*!< TPIU ITATBCTR2: AFVALID2SS Mask */ - -#define TPIU_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPIU ITATBCTR2: AFVALID1S Position */ -#define TPIU_ITATBCTR2_AFVALID1S_Msk (1UL << TPIU_ITATBCTR2_AFVALID1S_Pos) /*!< TPIU ITATBCTR2: AFVALID1SS Mask */ - -#define TPIU_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPIU ITATBCTR2: ATREADY2S Position */ -#define TPIU_ITATBCTR2_ATREADY2S_Msk (1UL /*<< TPIU_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPIU ITATBCTR2: ATREADY2S Mask */ - -#define TPIU_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPIU ITATBCTR2: ATREADY1S Position */ -#define TPIU_ITATBCTR2_ATREADY1S_Msk (1UL /*<< TPIU_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPIU ITATBCTR2: ATREADY1S Mask */ - -/** \brief TPIU Integration Test FIFO Test Data 1 Register Definitions */ -#define TPIU_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPIU ITFTTD1: ATB Interface 2 ATVALID Position */ -#define TPIU_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 ATVALID Mask */ - -#define TPIU_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPIU ITFTTD1: ATB Interface 2 byte count Position */ -#define TPIU_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 byte count Mask */ - -#define TPIU_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPIU ITFTTD1: ATB Interface 1 ATVALID Position */ -#define TPIU_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPIU ITFTTD1: ATB Interface 1 ATVALID Mask */ - -#define TPIU_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPIU ITFTTD1: ATB Interface 1 byte count Position */ -#define TPIU_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPIU ITFTTD1: ATB Interface 1 byte countt Mask */ - -#define TPIU_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPIU ITFTTD1: ATB Interface 2 data2 Position */ -#define TPIU_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPIU_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 data2 Mask */ - -#define TPIU_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPIU ITFTTD1: ATB Interface 2 data1 Position */ -#define TPIU_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPIU_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 data1 Mask */ - -#define TPIU_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPIU ITFTTD1: ATB Interface 2 data0 Position */ -#define TPIU_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPIU_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPIU ITFTTD1: ATB Interface 2 data0 Mask */ - -/** \brief TPIU Integration Test ATB Control Register 0 Definitions */ -#define TPIU_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPIU ITATBCTR0: AFVALID2S Position */ -#define TPIU_ITATBCTR0_AFVALID2S_Msk (1UL << TPIU_ITATBCTR0_AFVALID2S_Pos) /*!< TPIU ITATBCTR0: AFVALID2SS Mask */ - -#define TPIU_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPIU ITATBCTR0: AFVALID1S Position */ -#define TPIU_ITATBCTR0_AFVALID1S_Msk (1UL << TPIU_ITATBCTR0_AFVALID1S_Pos) /*!< TPIU ITATBCTR0: AFVALID1SS Mask */ - -#define TPIU_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPIU ITATBCTR0: ATREADY2S Position */ -#define TPIU_ITATBCTR0_ATREADY2S_Msk (1UL /*<< TPIU_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPIU ITATBCTR0: ATREADY2S Mask */ - -#define TPIU_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPIU ITATBCTR0: ATREADY1S Position */ -#define TPIU_ITATBCTR0_ATREADY1S_Msk (1UL /*<< TPIU_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPIU ITATBCTR0: ATREADY1S Mask */ - -/** \brief TPIU Integration Mode Control Register Definitions */ -#define TPIU_ITCTRL_Mode_Pos 0U /*!< TPIU ITCTRL: Mode Position */ -#define TPIU_ITCTRL_Mode_Msk (0x3UL /*<< TPIU_ITCTRL_Mode_Pos*/) /*!< TPIU ITCTRL: Mode Mask */ - -/** \brief TPIU DEVID Register Definitions */ -#define TPIU_DEVID_NRZVALID_Pos 11U /*!< TPIU DEVID: NRZVALID Position */ -#define TPIU_DEVID_NRZVALID_Msk (1UL << TPIU_DEVID_NRZVALID_Pos) /*!< TPIU DEVID: NRZVALID Mask */ - -#define TPIU_DEVID_MANCVALID_Pos 10U /*!< TPIU DEVID: MANCVALID Position */ -#define TPIU_DEVID_MANCVALID_Msk (1UL << TPIU_DEVID_MANCVALID_Pos) /*!< TPIU DEVID: MANCVALID Mask */ - -#define TPIU_DEVID_PTINVALID_Pos 9U /*!< TPIU DEVID: PTINVALID Position */ -#define TPIU_DEVID_PTINVALID_Msk (1UL << TPIU_DEVID_PTINVALID_Pos) /*!< TPIU DEVID: PTINVALID Mask */ - -#define TPIU_DEVID_FIFOSZ_Pos 6U /*!< TPIU DEVID: FIFOSZ Position */ -#define TPIU_DEVID_FIFOSZ_Msk (0x7UL << TPIU_DEVID_FIFOSZ_Pos) /*!< TPIU DEVID: FIFOSZ Mask */ - -#define TPIU_DEVID_NrTraceInput_Pos 0U /*!< TPIU DEVID: NrTraceInput Position */ -#define TPIU_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPIU_DEVID_NrTraceInput_Pos*/) /*!< TPIU DEVID: NrTraceInput Mask */ - -/** \brief TPIU DEVTYPE Register Definitions */ -#define TPIU_DEVTYPE_SubType_Pos 4U /*!< TPIU DEVTYPE: SubType Position */ -#define TPIU_DEVTYPE_SubType_Msk (0xFUL /*<< TPIU_DEVTYPE_SubType_Pos*/) /*!< TPIU DEVTYPE: SubType Mask */ - -#define TPIU_DEVTYPE_MajorType_Pos 0U /*!< TPIU DEVTYPE: MajorType Position */ -#define TPIU_DEVTYPE_MajorType_Msk (0xFUL << TPIU_DEVTYPE_MajorType_Pos) /*!< TPIU DEVTYPE: MajorType Mask */ - -/*@}*/ /* end of group CMSIS_TPIU */ - - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ - __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ - __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ - __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ - __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ - __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ - __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ - uint32_t RESERVED0[1]; - union { - __IOM uint32_t MAIR[2]; - struct { - __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ - __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ - }; - }; -} MPU_Type; - -#define MPU_TYPE_RALIASES 4U - -/** \brief MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/** \brief MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/** \brief MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/** \brief MPU Region Base Address Register Definitions */ -#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ -#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ - -#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ -#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ - -#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ -#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ - -#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ -#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ - -/** \brief MPU Region Limit Address Register Definitions */ -#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ -#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ - -#define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */ -#define MPU_RLAR_PXN_Msk (1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */ - -#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ -#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ - -#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ -#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Mask */ - -/** \brief MPU Memory Attribute Indirection Register 0 Definitions */ -#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ -#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ - -#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ -#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ - -#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ -#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ - -#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ -#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ - -/** \brief MPU Memory Attribute Indirection Register 1 Definitions */ -#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ -#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ - -#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ -#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ - -#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ -#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ - -#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ -#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SAU Security Attribution Unit (SAU) - \brief Type definitions for the Security Attribution Unit (SAU) - @{ - */ - -/** - \brief Structure type to access the Security Attribution Unit (SAU). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ - __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ - __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ -#else - uint32_t RESERVED0[3]; -#endif - __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ - __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ -} SAU_Type; - -/** \brief SAU Control Register Definitions */ -#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ -#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ - -#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ -#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ - -/** \brief SAU Type Register Definitions */ -#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ -#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ - -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) -/** \brief SAU Region Number Register Definitions */ -#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ -#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ - -/** \brief SAU Region Base Address Register Definitions */ -#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ -#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ - -/** \brief SAU Region Limit Address Register Definitions */ -#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ -#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ - -#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ -#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ - -#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ -#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ - -#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ - -/** \brief SAU Secure Fault Status Register Definitions */ -#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ -#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ - -#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ -#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ - -#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ -#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ - -#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ -#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ - -#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ -#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ - -#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ -#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ - -#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ -#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ - -#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ -#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ - -/*@} end of group CMSIS_SAU */ -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_FPU Floating Point Unit (FPU) - \brief Type definitions for the Floating Point Unit (FPU) - @{ - */ - -/** - \brief Structure type to access the Floating Point Unit (FPU). - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ - __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ - __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ - __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ - __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ -} FPU_Type; - -/** \brief FPU Floating-Point Context Control Register Definitions */ -#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ -#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ - -#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ -#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ - -#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ -#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ - -#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ -#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ - -#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ -#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ - -#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ -#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ - -#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ -#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ - -#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ -#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ - -#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ -#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ - -#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ -#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ - -#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ -#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ - -#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ -#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ - -#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ -#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ - -#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ -#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ - -#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ -#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ - -#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ -#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ - -#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ -#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ - -/** \brief FPU Floating-Point Context Address Register Definitions */ -#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ -#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ - -/** \brief FPU Floating-Point Default Status Control Register Definitions */ -#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ -#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ - -#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ -#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ - -#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ -#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ - -#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ -#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ - -/** \brief FPU Media and VFP Feature Register 0 Definitions */ -#define FPU_MVFR0_FPRound_Pos 28U /*!< MVFR0: Rounding modes bits Position */ -#define FPU_MVFR0_FPRound_Msk (0xFUL << FPU_MVFR0_FPRound_Pos) /*!< MVFR0: Rounding modes bits Mask */ - -#define FPU_MVFR0_FPShortvec_Pos 24U /*!< MVFR0: Short vectors bits Position */ -#define FPU_MVFR0_FPShortvec_Msk (0xFUL << FPU_MVFR0_FPShortvec_Pos) /*!< MVFR0: Short vectors bits Mask */ - -#define FPU_MVFR0_FPSqrt_Pos 20U /*!< MVFR0: Square root bits Position */ -#define FPU_MVFR0_FPSqrt_Msk (0xFUL << FPU_MVFR0_FPSqrt_Pos) /*!< MVFR0: Square root bits Mask */ - -#define FPU_MVFR0_FPDivide_Pos 16U /*!< MVFR0: Divide bits Position */ -#define FPU_MVFR0_FPDivide_Msk (0xFUL << FPU_MVFR0_FPDivide_Pos) /*!< MVFR0: Divide bits Mask */ - -#define FPU_MVFR0_FPExceptrap_Pos 12U /*!< MVFR0: Exception trapping bits Position */ -#define FPU_MVFR0_FPExceptrap_Msk (0xFUL << FPU_MVFR0_FPExceptrap_Pos) /*!< MVFR0: Exception trapping bits Mask */ - -#define FPU_MVFR0_FPDP_Pos 8U /*!< MVFR0: Double-precision bits Position */ -#define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) /*!< MVFR0: Double-precision bits Mask */ - -#define FPU_MVFR0_FPSP_Pos 4U /*!< MVFR0: Single-precision bits Position */ -#define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) /*!< MVFR0: Single-precision bits Mask */ - -#define FPU_MVFR0_SIMDReg_Pos 0U /*!< MVFR0: SIMD registers bits Position */ -#define FPU_MVFR0_SIMDReg_Msk (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/) /*!< MVFR0: SIMD registers bits Mask */ - -/** \brief FPU Media and VFP Feature Register 1 Definitions */ -#define FPU_MVFR1_FMAC_Pos 28U /*!< MVFR1: Fused MAC bits Position */ -#define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) /*!< MVFR1: Fused MAC bits Mask */ - -#define FPU_MVFR1_FPHP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ -#define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) /*!< MVFR1: FP HPFP bits Mask */ - -#define FPU_MVFR1_FPDNaN_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ -#define FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) /*!< MVFR1: D_NaN mode bits Mask */ - -#define FPU_MVFR1_FPFtZ_Pos 0U /*!< MVFR1: FtZ mode bits Position */ -#define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ - -/** \brief FPU Media and VFP Feature Register 2 Definitions */ -#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ -#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: VFP Misc bits Mask */ - -/*@} end of group CMSIS_FPU */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DCB Debug Control Block - \brief Type definitions for the Debug Control Block Registers - @{ - */ - -/** - \brief Structure type to access the Debug Control Block Registers (DCB). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ - uint32_t RESERVED0[1U]; - __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ - __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ -} DCB_Type; - -/** \brief DCB Debug Halting Control and Status Register Definitions */ -#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ -#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ - -#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ -#define DCB_DHCSR_S_RESTART_ST_Msk (1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ - -#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ -#define DCB_DHCSR_S_RESET_ST_Msk (1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ - -#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ -#define DCB_DHCSR_S_RETIRE_ST_Msk (1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ - -#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ -#define DCB_DHCSR_S_SDE_Msk (1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ - -#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ -#define DCB_DHCSR_S_LOCKUP_Msk (1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ - -#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ -#define DCB_DHCSR_S_SLEEP_Msk (1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ - -#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ -#define DCB_DHCSR_S_HALT_Msk (1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ - -#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ -#define DCB_DHCSR_S_REGRDY_Msk (1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ - -#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ -#define DCB_DHCSR_C_SNAPSTALL_Msk (1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ - -#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ -#define DCB_DHCSR_C_MASKINTS_Msk (1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ - -#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ -#define DCB_DHCSR_C_STEP_Msk (1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ - -#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ -#define DCB_DHCSR_C_HALT_Msk (1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ - -#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ -#define DCB_DHCSR_C_DEBUGEN_Msk (1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ - -/** \brief DCB Debug Core Register Selector Register Definitions */ -#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ -#define DCB_DCRSR_REGWnR_Msk (1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ - -#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ -#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ - -/** \brief DCB Debug Core Register Data Register Definitions */ -#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ -#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ - -/** \brief DCB Debug Exception and Monitor Control Register Definitions */ -#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ -#define DCB_DEMCR_TRCENA_Msk (1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ - -#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ -#define DCB_DEMCR_MONPRKEY_Msk (1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ - -#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ -#define DCB_DEMCR_UMON_EN_Msk (1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ - -#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ -#define DCB_DEMCR_SDME_Msk (1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ - -#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ -#define DCB_DEMCR_MON_REQ_Msk (1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ - -#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ -#define DCB_DEMCR_MON_STEP_Msk (1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ - -#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ -#define DCB_DEMCR_MON_PEND_Msk (1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ - -#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ -#define DCB_DEMCR_MON_EN_Msk (1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ - -#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ -#define DCB_DEMCR_VC_SFERR_Msk (1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ - -#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ -#define DCB_DEMCR_VC_HARDERR_Msk (1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ - -#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ -#define DCB_DEMCR_VC_INTERR_Msk (1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ - -#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ -#define DCB_DEMCR_VC_BUSERR_Msk (1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ - -#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ -#define DCB_DEMCR_VC_STATERR_Msk (1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ - -#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ -#define DCB_DEMCR_VC_CHKERR_Msk (1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ - -#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ -#define DCB_DEMCR_VC_NOCPERR_Msk (1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ - -#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ -#define DCB_DEMCR_VC_MMERR_Msk (1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ - -#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ -#define DCB_DEMCR_VC_CORERESET_Msk (1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ - -/** \brief DCB Debug Authentication Control Register Definitions */ -#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ -#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ - -#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ -#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ - -#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ -#define DCB_DAUTHCTRL_INTSPIDEN_Msk (1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ - -#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ -#define DCB_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ - -/** \brief DCB Debug Security Control and Status Register Definitions */ -#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ -#define DCB_DSCSR_CDSKEY_Msk (1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ - -#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ -#define DCB_DSCSR_CDS_Msk (1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ - -#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ -#define DCB_DSCSR_SBRSEL_Msk (1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ - -#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ -#define DCB_DSCSR_SBRSELEN_Msk (1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ - -/*@} end of group CMSIS_DCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DIB Debug Identification Block - \brief Type definitions for the Debug Identification Block Registers - @{ - */ - -/** - \brief Structure type to access the Debug Identification Block Registers (DIB). - */ -typedef struct -{ - __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ - __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ - __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ - __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ - __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ -} DIB_Type; - -/** \brief DIB SCS Software Lock Access Register Definitions */ -#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ -#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ - -/** \brief DIB SCS Software Lock Status Register Definitions */ -#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ -#define DIB_DLSR_nTT_Msk (1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ - -#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ -#define DIB_DLSR_SLK_Msk (1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ - -#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ -#define DIB_DLSR_SLI_Msk (1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ - -/** \brief DIB Debug Authentication Status Register Definitions */ -#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ -#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ - -#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ -#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ - -#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ -#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ - -#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ -#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ - -/** \brief DIB SCS Device Architecture Register Definitions */ -#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ -#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ - -#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ -#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ - -#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ -#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ - -#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ -#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ - -#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ -#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ - -/** \brief DIB SCS Device Type Register Definitions */ -#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ -#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ - -#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ -#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ - -/*@} end of group CMSIS_DIB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ - #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ - #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ - #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ - #define TPIU_BASE (0xE0040000UL) /*!< TPIU Base Address */ - #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ - #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ - #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ - #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ - #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - - #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ - #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ - #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ - #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ - #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ - #define TPIU ((TPIU_Type *) TPIU_BASE ) /*!< TPIU configuration struct */ - #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ - #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ - - #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ - #endif - - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ - #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ - #endif - - #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ - #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ - #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ - #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ - #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ - #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ - #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ - - #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ - #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ - #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ - #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ - #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ - #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ - - #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ - #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ - #endif - - #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ - #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ - -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ -/*@} */ - - -/** - \defgroup CMSIS_deprecated_aliases Backwards Compatibility Aliases - \brief Alias definitions present for backwards compatibility for deprecated symbols. - @{ - */ - -#ifndef CMSIS_DISABLE_DEPRECATED - -#define SCB_AIRCR_ENDIANESS_Pos SCB_AIRCR_ENDIANNESS_Pos -#define SCB_AIRCR_ENDIANESS_Msk SCB_AIRCR_ENDIANNESS_Msk - -/* deprecated, CMSIS_5 backward compatibility */ -typedef struct -{ - __IOM uint32_t DHCSR; - __OM uint32_t DCRSR; - __IOM uint32_t DCRDR; - __IOM uint32_t DEMCR; - uint32_t RESERVED0[1U]; - __IOM uint32_t DAUTHCTRL; - __IOM uint32_t DSCSR; -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos DCB_DHCSR_DBGKEY_Pos -#define CoreDebug_DHCSR_DBGKEY_Msk DCB_DHCSR_DBGKEY_Msk - -#define CoreDebug_DHCSR_S_RESTART_ST_Pos DCB_DHCSR_S_RESTART_ST_Pos -#define CoreDebug_DHCSR_S_RESTART_ST_Msk DCB_DHCSR_S_RESTART_ST_Msk - -#define CoreDebug_DHCSR_S_RESET_ST_Pos DCB_DHCSR_S_RESET_ST_Pos -#define CoreDebug_DHCSR_S_RESET_ST_Msk DCB_DHCSR_S_RESET_ST_Msk - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos DCB_DHCSR_S_RETIRE_ST_Pos -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk DCB_DHCSR_S_RETIRE_ST_Msk - -#define CoreDebug_DHCSR_S_LOCKUP_Pos DCB_DHCSR_S_LOCKUP_Pos -#define CoreDebug_DHCSR_S_LOCKUP_Msk DCB_DHCSR_S_LOCKUP_Msk - -#define CoreDebug_DHCSR_S_SLEEP_Pos DCB_DHCSR_S_SLEEP_Pos -#define CoreDebug_DHCSR_S_SLEEP_Msk DCB_DHCSR_S_SLEEP_Msk - -#define CoreDebug_DHCSR_S_HALT_Pos DCB_DHCSR_S_HALT_Pos -#define CoreDebug_DHCSR_S_HALT_Msk DCB_DHCSR_S_HALT_Msk - -#define CoreDebug_DHCSR_S_REGRDY_Pos DCB_DHCSR_S_REGRDY_Pos -#define CoreDebug_DHCSR_S_REGRDY_Msk DCB_DHCSR_S_REGRDY_Msk - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos DCB_DHCSR_C_SNAPSTALL_Pos -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk DCB_DHCSR_C_SNAPSTALL_Msk - -#define CoreDebug_DHCSR_C_MASKINTS_Pos DCB_DHCSR_C_MASKINTS_Pos -#define CoreDebug_DHCSR_C_MASKINTS_Msk DCB_DHCSR_C_MASKINTS_Msk - -#define CoreDebug_DHCSR_C_STEP_Pos DCB_DHCSR_C_STEP_Pos -#define CoreDebug_DHCSR_C_STEP_Msk DCB_DHCSR_C_STEP_Msk - -#define CoreDebug_DHCSR_C_HALT_Pos DCB_DHCSR_C_HALT_Pos -#define CoreDebug_DHCSR_C_HALT_Msk DCB_DHCSR_C_HALT_Msk - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos DCB_DHCSR_C_DEBUGEN_Pos -#define CoreDebug_DHCSR_C_DEBUGEN_Msk DCB_DHCSR_C_DEBUGEN_Msk - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos DCB_DCRSR_REGWnR_Pos -#define CoreDebug_DCRSR_REGWnR_Msk DCB_DCRSR_REGWnR_Msk - -#define CoreDebug_DCRSR_REGSEL_Pos DCB_DCRSR_REGSEL_Pos -#define CoreDebug_DCRSR_REGSEL_Msk DCB_DCRSR_REGSEL_Msk - -/* Debug Exception and Monitor Control Register Definitions */ -#define CoreDebug_DEMCR_TRCENA_Pos DCB_DEMCR_TRCENA_Pos -#define CoreDebug_DEMCR_TRCENA_Msk DCB_DEMCR_TRCENA_Msk - -#define CoreDebug_DEMCR_MON_REQ_Pos DCB_DEMCR_MON_REQ_Pos -#define CoreDebug_DEMCR_MON_REQ_Msk DCB_DEMCR_MON_REQ_Msk - -#define CoreDebug_DEMCR_MON_STEP_Pos DCB_DEMCR_MON_STEP_Pos -#define CoreDebug_DEMCR_MON_STEP_Msk DCB_DEMCR_MON_STEP_Msk - -#define CoreDebug_DEMCR_MON_PEND_Pos DCB_DEMCR_MON_PEND_Pos -#define CoreDebug_DEMCR_MON_PEND_Msk DCB_DEMCR_MON_PEND_Msk - -#define CoreDebug_DEMCR_MON_EN_Pos DCB_DEMCR_MON_EN_Pos -#define CoreDebug_DEMCR_MON_EN_Msk DCB_DEMCR_MON_EN_Msk - -#define CoreDebug_DEMCR_VC_HARDERR_Pos DCB_DEMCR_VC_HARDERR_Pos -#define CoreDebug_DEMCR_VC_HARDERR_Msk DCB_DEMCR_VC_HARDERR_Msk - -#define CoreDebug_DEMCR_VC_INTERR_Pos DCB_DEMCR_VC_INTERR_Pos -#define CoreDebug_DEMCR_VC_INTERR_Msk DCB_DEMCR_VC_INTERR_Msk - -#define CoreDebug_DEMCR_VC_BUSERR_Pos DCB_DEMCR_VC_BUSERR_Pos -#define CoreDebug_DEMCR_VC_BUSERR_Msk DCB_DEMCR_VC_BUSERR_Msk - -#define CoreDebug_DEMCR_VC_STATERR_Pos DCB_DEMCR_VC_STATERR_Pos -#define CoreDebug_DEMCR_VC_STATERR_Msk DCB_DEMCR_VC_STATERR_Msk - -#define CoreDebug_DEMCR_VC_CHKERR_Pos DCB_DEMCR_VC_CHKERR_Pos -#define CoreDebug_DEMCR_VC_CHKERR_Msk DCB_DEMCR_VC_CHKERR_Msk - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos DCB_DEMCR_VC_NOCPERR_Pos -#define CoreDebug_DEMCR_VC_NOCPERR_Msk DCB_DEMCR_VC_NOCPERR_Msk - -#define CoreDebug_DEMCR_VC_MMERR_Pos DCB_DEMCR_VC_MMERR_Pos -#define CoreDebug_DEMCR_VC_MMERR_Msk DCB_DEMCR_VC_MMERR_Msk - -#define CoreDebug_DEMCR_VC_CORERESET_Pos DCB_DEMCR_VC_CORERESET_Pos -#define CoreDebug_DEMCR_VC_CORERESET_Msk DCB_DEMCR_VC_CORERESET_Msk - -/* Debug Authentication Control Register Definitions */ -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos DCB_DAUTHCTRL_INTSPNIDEN_Pos -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk DCB_DAUTHCTRL_INTSPNIDEN_Msk - -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos DCB_DAUTHCTRL_SPNIDENSEL_Pos -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk DCB_DAUTHCTRL_SPNIDENSEL_Msk - -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos DCB_DAUTHCTRL_INTSPIDEN_Pos -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk DCB_DAUTHCTRL_INTSPIDEN_Msk - -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos DCB_DAUTHCTRL_SPIDENSEL_Pos -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk DCB_DAUTHCTRL_SPIDENSEL_Msk - -/* Debug Security Control and Status Register Definitions */ -#define CoreDebug_DSCSR_CDS_Pos DCB_DSCSR_CDS_Pos -#define CoreDebug_DSCSR_CDS_Msk DCB_DSCSR_CDS_Msk - -#define CoreDebug_DSCSR_SBRSEL_Pos DCB_DSCSR_SBRSEL_Pos -#define CoreDebug_DSCSR_SBRSEL_Msk DCB_DSCSR_SBRSEL_Msk - -#define CoreDebug_DSCSR_SBRSELEN_Pos DCB_DSCSR_SBRSELEN_Pos -#define CoreDebug_DSCSR_SBRSELEN_Msk DCB_DSCSR_SBRSELEN_Msk - -#define CoreDebug ((CoreDebug_Type *) DCB_BASE) -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define CoreDebug_NS ((CoreDebug_Type *) DCB_BASE_NS) -#endif - -#endif // CMSIS_DISABLE_DEPRECATED - -/*@} */ - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifdef CMSIS_NVIC_VIRTUAL - #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE - #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" - #endif - #include CMSIS_NVIC_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping - #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping - #define NVIC_EnableIRQ __NVIC_EnableIRQ - #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ - #define NVIC_DisableIRQ __NVIC_DisableIRQ - #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ - #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ - #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ - #define NVIC_GetActive __NVIC_GetActive - #define NVIC_SetPriority __NVIC_SetPriority - #define NVIC_GetPriority __NVIC_GetPriority - #define NVIC_SystemReset __NVIC_SystemReset -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifdef CMSIS_VECTAB_VIRTUAL - #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE - #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" - #endif - #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetVector __NVIC_SetVector - #define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - -/* Special LR values for Secure/Non-Secure call handling and exception handling */ - -/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ -#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ - -/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ -#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ -#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ -#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ -#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ -#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ -#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ -#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ - -/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ -#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ -#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ -#else -#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ -#endif - - -/** - \brief Set Priority Grouping - \details Sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ - SCB->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping - \details Reads the priority grouping field from the NVIC Interrupt Controller. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) -{ - return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - __COMPILER_BARRIER(); - NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __COMPILER_BARRIER(); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Interrupt Target State - \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - \return 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Target State - \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Clear Interrupt Target State - \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - VTOR must been relocated to SRAM before. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ - uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR); - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; - __DSB(); -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ - uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR); - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set Priority Grouping (non-secure) - \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB_NS->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ - SCB_NS->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping (non-secure) - \details Reads the priority grouping field from the non-secure NVIC when in secure state. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) -{ - return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable Interrupt (non-secure) - \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status (non-secure) - \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt (non-secure) - \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Pending Interrupt (non-secure) - \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt (non-secure) - \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt (non-secure) - \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt (non-secure) - \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Priority (non-secure) - \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every non-secure processor exception. - */ -__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority (non-secure) - \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } -} -#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_NVICFunctions */ - -/* ########################## MPU functions #################################### */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - - #include "m-profile/armv8m_mpu.h" - -#endif - - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - uint32_t mvfr0; - - mvfr0 = FPU->MVFR0; - if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x220U) - { - return 2U; /* Double + Single precision FPU */ - } - else if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x020U) - { - return 1U; /* Single precision FPU */ - } - else - { - return 0U; /* No FPU */ - } -} - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ########################## SAU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SAUFunctions SAU Functions - \brief Functions that configure the SAU. - @{ - */ - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - -/** - \brief Enable SAU - \details Enables the Security Attribution Unit (SAU). - */ -__STATIC_INLINE void TZ_SAU_Enable(void) -{ - SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); -} - - - -/** - \brief Disable SAU - \details Disables the Security Attribution Unit (SAU). - */ -__STATIC_INLINE void TZ_SAU_Disable(void) -{ - SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); -} - -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_SAUFunctions */ - - - - -/* ################################## Debug Control function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_DCBFunctions Debug Control Functions - \brief Functions that access the Debug Control Block. - @{ - */ - - -/** - \brief Set Debug Authentication Control Register - \details writes to Debug Authentication Control register. - \param [in] value value to be written. - */ -__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) -{ - __DSB(); - __ISB(); - DCB->DAUTHCTRL = value; - __DSB(); - __ISB(); -} - - -/** - \brief Get Debug Authentication Control Register - \details Reads Debug Authentication Control register. - \return Debug Authentication Control Register. - */ -__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) -{ - return (DCB->DAUTHCTRL); -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set Debug Authentication Control Register (non-secure) - \details writes to non-secure Debug Authentication Control register when in secure state. - \param [in] value value to be written - */ -__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) -{ - __DSB(); - __ISB(); - DCB_NS->DAUTHCTRL = value; - __DSB(); - __ISB(); -} - - -/** - \brief Get Debug Authentication Control Register (non-secure) - \details Reads non-secure Debug Authentication Control register when in secure state. - \return Debug Authentication Control Register. - */ -__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) -{ - return (DCB_NS->DAUTHCTRL); -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_DCBFunctions */ - - - - -/* ################################## Debug Identification function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions - \brief Functions that access the Debug Identification Block. - @{ - */ - - -/** - \brief Get Debug Authentication Status Register - \details Reads Debug Authentication Status register. - \return Debug Authentication Status Register. - */ -__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) -{ - return (DIB->DAUTHSTATUS); -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Debug Authentication Status Register (non-secure) - \details Reads non-secure Debug Authentication Status register when in secure state. - \return Debug Authentication Status Register. - */ -__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) -{ - return (DIB_NS->DAUTHSTATUS); -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_DCBFunctions */ - - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief System Tick Configuration (non-secure) - \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function TZ_SysTick_Config_NS is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** - \brief ITM Send Character - \details Transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - \param [in] ch Character to transmit. - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ - ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0U].u32 == 0UL) - { - __NOP(); - } - ITM->PORT[0U].u8 = (uint8_t)ch; - } - return (ch); -} - - -/** - \brief ITM Receive Character - \details Inputs a character via the external variable \ref ITM_RxBuffer. - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) -{ - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) - { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** - \brief ITM Check Character - \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) -{ - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) - { - return (0); /* no character available */ - } - else - { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM33_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/lib/main/pico-sdk/rp2_common/cmsis/stub/CMSIS/Core/Include/m-profile/armv7m_cachel1.h b/lib/main/pico-sdk/rp2_common/cmsis/stub/CMSIS/Core/Include/m-profile/armv7m_cachel1.h deleted file mode 100644 index d7338a72e0..0000000000 --- a/lib/main/pico-sdk/rp2_common/cmsis/stub/CMSIS/Core/Include/m-profile/armv7m_cachel1.h +++ /dev/null @@ -1,439 +0,0 @@ -/* - * Copyright (c) 2020-2021 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* - * CMSIS-Core(M) Level 1 Cache API for Armv7-M and later - */ - -#ifndef ARM_ARMV7M_CACHEL1_H -#define ARM_ARMV7M_CACHEL1_H - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_CacheFunctions Cache Functions - \brief Functions that configure Instruction and Data cache. - @{ - */ - -/* Cache Size ID Register Macros */ -#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) -#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) - -#ifndef __SCB_DCACHE_LINE_SIZE -#define __SCB_DCACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ -#endif - -#ifndef __SCB_ICACHE_LINE_SIZE -#define __SCB_ICACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ -#endif - -/** - \brief Enable I-Cache - \details Turns on I-Cache - */ -__STATIC_FORCEINLINE void SCB_EnableICache (void) -{ - #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) - if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ - - __DSB(); - __ISB(); - SCB->ICIALLU = 0UL; /* invalidate I-Cache */ - __DSB(); - __ISB(); - SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Disable I-Cache - \details Turns off I-Cache - */ -__STATIC_FORCEINLINE void SCB_DisableICache (void) -{ - #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) - __DSB(); - __ISB(); - SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ - SCB->ICIALLU = 0UL; /* invalidate I-Cache */ - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Invalidate I-Cache - \details Invalidates I-Cache - */ -__STATIC_FORCEINLINE void SCB_InvalidateICache (void) -{ - #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) - __DSB(); - __ISB(); - SCB->ICIALLU = 0UL; - __DSB(); - __ISB(); - #endif -} - - -/** - \brief I-Cache Invalidate by address - \details Invalidates I-Cache for the given address. - I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. - I-Cache memory blocks which are part of given address + given size are invalidated. - \param[in] addr address - \param[in] isize size of memory block (in number of bytes) -*/ -__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (volatile void *addr, int32_t isize) -{ - #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) - if ( isize > 0 ) { - int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U)); - uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */; - - __DSB(); - - do { - SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ - op_addr += __SCB_ICACHE_LINE_SIZE; - op_size -= __SCB_ICACHE_LINE_SIZE; - } while ( op_size > 0 ); - - __DSB(); - __ISB(); - } - #endif -} - - -/** - \brief Enable D-Cache - \details Turns on D-Cache - */ -__STATIC_FORCEINLINE void SCB_EnableDCache (void) -{ - #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - uint32_t ccsidr; - uint32_t sets; - uint32_t ways; - - if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ - - SCB->CSSELR = 0U; /* select Level 1 data cache */ - __DSB(); - - ccsidr = SCB->CCSIDR; - - /* invalidate D-Cache */ - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - do { - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - do { - SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | - ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); - #if defined ( __CC_ARM ) - __schedule_barrier(); - #endif - } while (ways-- != 0U); - } while(sets-- != 0U); - __DSB(); - - SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Disable D-Cache - \details Turns off D-Cache - */ -__STATIC_FORCEINLINE void SCB_DisableDCache (void) -{ - #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - struct { - uint32_t ccsidr; - uint32_t sets; - uint32_t ways; - } locals - #if ((defined(__GNUC__) || defined(__clang__)) && !defined(__OPTIMIZE__)) - __ALIGNED(__SCB_DCACHE_LINE_SIZE) - #endif - ; - - SCB->CSSELR = 0U; /* select Level 1 data cache */ - __DSB(); - - SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ - __DSB(); - - #if !defined(__OPTIMIZE__) - /* - * For the endless loop issue with no optimization builds. - * More details, see https://github.com/ARM-software/CMSIS_5/issues/620 - * - * The issue only happens when local variables are in stack. If - * local variables are saved in general purpose register, then the function - * is OK. - * - * When local variables are in stack, after disabling the cache, flush the - * local variables cache line for data consistency. - */ - /* Clean and invalidate the local variable cache. */ - #if defined(__ICCARM__) - /* As we can't align the stack to the cache line size, invalidate each of the variables */ - SCB->DCCIMVAC = (uint32_t)&locals.sets; - SCB->DCCIMVAC = (uint32_t)&locals.ways; - SCB->DCCIMVAC = (uint32_t)&locals.ccsidr; - #else - SCB->DCCIMVAC = (uint32_t)&locals; - #endif - __DSB(); - __ISB(); - #endif - - locals.ccsidr = SCB->CCSIDR; - /* clean & invalidate D-Cache */ - locals.sets = (uint32_t)(CCSIDR_SETS(locals.ccsidr)); - do { - locals.ways = (uint32_t)(CCSIDR_WAYS(locals.ccsidr)); - do { - SCB->DCCISW = (((locals.sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | - ((locals.ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); - #if defined ( __CC_ARM ) - __schedule_barrier(); - #endif - } while (locals.ways-- != 0U); - } while(locals.sets-- != 0U); - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Invalidate D-Cache - \details Invalidates D-Cache - */ -__STATIC_FORCEINLINE void SCB_InvalidateDCache (void) -{ - #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - uint32_t ccsidr; - uint32_t sets; - uint32_t ways; - - SCB->CSSELR = 0U; /* select Level 1 data cache */ - __DSB(); - - ccsidr = SCB->CCSIDR; - - /* invalidate D-Cache */ - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - do { - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - do { - SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | - ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); - #if defined ( __CC_ARM ) - __schedule_barrier(); - #endif - } while (ways-- != 0U); - } while(sets-- != 0U); - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Clean D-Cache - \details Cleans D-Cache - */ -__STATIC_FORCEINLINE void SCB_CleanDCache (void) -{ - #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - uint32_t ccsidr; - uint32_t sets; - uint32_t ways; - - SCB->CSSELR = 0U; /* select Level 1 data cache */ - __DSB(); - - ccsidr = SCB->CCSIDR; - - /* clean D-Cache */ - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - do { - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - do { - SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | - ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); - #if defined ( __CC_ARM ) - __schedule_barrier(); - #endif - } while (ways-- != 0U); - } while(sets-- != 0U); - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Clean & Invalidate D-Cache - \details Cleans and Invalidates D-Cache - */ -__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void) -{ - #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - uint32_t ccsidr; - uint32_t sets; - uint32_t ways; - - SCB->CSSELR = 0U; /* select Level 1 data cache */ - __DSB(); - - ccsidr = SCB->CCSIDR; - - /* clean & invalidate D-Cache */ - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - do { - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - do { - SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | - ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); - #if defined ( __CC_ARM ) - __schedule_barrier(); - #endif - } while (ways-- != 0U); - } while(sets-- != 0U); - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief D-Cache Invalidate by address - \details Invalidates D-Cache for the given address. - D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. - D-Cache memory blocks which are part of given address + given size are invalidated. - \param[in] addr address - \param[in] dsize size of memory block (in number of bytes) -*/ -__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (volatile void *addr, int32_t dsize) -{ - #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - if ( dsize > 0 ) { - int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); - uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; - - __DSB(); - - do { - SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ - op_addr += __SCB_DCACHE_LINE_SIZE; - op_size -= __SCB_DCACHE_LINE_SIZE; - } while ( op_size > 0 ); - - __DSB(); - __ISB(); - } - #endif -} - - -/** - \brief D-Cache Clean by address - \details Cleans D-Cache for the given address - D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity. - D-Cache memory blocks which are part of given address + given size are cleaned. - \param[in] addr address - \param[in] dsize size of memory block (in number of bytes) -*/ -__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (volatile void *addr, int32_t dsize) -{ - #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - if ( dsize > 0 ) { - int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); - uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; - - __DSB(); - - do { - SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ - op_addr += __SCB_DCACHE_LINE_SIZE; - op_size -= __SCB_DCACHE_LINE_SIZE; - } while ( op_size > 0 ); - - __DSB(); - __ISB(); - } - #endif -} - - -/** - \brief D-Cache Clean and Invalidate by address - \details Cleans and invalidates D_Cache for the given address - D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity. - D-Cache memory blocks which are part of given address + given size are cleaned and invalidated. - \param[in] addr address (aligned to 32-byte boundary) - \param[in] dsize size of memory block (in number of bytes) -*/ -__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (volatile void *addr, int32_t dsize) -{ - #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - if ( dsize > 0 ) { - int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); - uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; - - __DSB(); - - do { - SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ - op_addr += __SCB_DCACHE_LINE_SIZE; - op_size -= __SCB_DCACHE_LINE_SIZE; - } while ( op_size > 0 ); - - __DSB(); - __ISB(); - } - #endif -} - -/*@} end of CMSIS_Core_CacheFunctions */ - -#endif /* ARM_ARMV7M_CACHEL1_H */ diff --git a/lib/main/pico-sdk/rp2_common/cmsis/stub/CMSIS/Core/Include/m-profile/armv7m_mpu.h b/lib/main/pico-sdk/rp2_common/cmsis/stub/CMSIS/Core/Include/m-profile/armv7m_mpu.h deleted file mode 100644 index 5a4eba231c..0000000000 --- a/lib/main/pico-sdk/rp2_common/cmsis/stub/CMSIS/Core/Include/m-profile/armv7m_mpu.h +++ /dev/null @@ -1,273 +0,0 @@ -/* - * Copyright (c) 2017-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* - * CMSIS-Core(M) MPU API for Armv7-M MPU - */ - -#ifndef ARM_MPU_ARMV7_H -#define ARM_MPU_ARMV7_H - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes -#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes -#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes -#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes -#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes -#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte -#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes -#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes -#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes -#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes -#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes -#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes -#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes -#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes -#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes -#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte -#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes -#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes -#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes -#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes -#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes -#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes -#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes -#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes -#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes -#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte -#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes -#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes - -#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access -#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only -#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only -#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access -#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only -#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access - -/** MPU Region Base Address Register Value -* -* \param Region The region to be configured, number 0 to 15. -* \param BaseAddress The base address for the region. -*/ -#define ARM_MPU_RBAR(Region, BaseAddress) \ - (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \ - ((Region) & MPU_RBAR_REGION_Msk) | \ - (MPU_RBAR_VALID_Msk)) - -/** -* MPU Memory Access Attributes -* -* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. -* \param IsShareable Region is shareable between multiple bus masters. -* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. -* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. -*/ -#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ - ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ - (((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ - (((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ - (((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk)) - -/** -* MPU Region Attribute and Size Register Value -* -* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. -* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. -* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_. -* \param SubRegionDisable Sub-region disable field. -* \param Size Region size of the region to be configured, for example 4K, 8K. -*/ -#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \ - ((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ - (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ - (((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \ - (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \ - (((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \ - (((MPU_RASR_ENABLE_Msk)))) - -/** -* MPU Region Attribute and Size Register Value -* -* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. -* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. -* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. -* \param IsShareable Region is shareable between multiple bus masters. -* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. -* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. -* \param SubRegionDisable Sub-region disable field. -* \param Size Region size of the region to be configured, for example 4K, 8K. -*/ -#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ - ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size) - -/** -* MPU Memory Access Attribute for strongly ordered memory. -* - TEX: 000b -* - Shareable -* - Non-cacheable -* - Non-bufferable -*/ -#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U) - -/** -* MPU Memory Access Attribute for device memory. -* - TEX: 000b (if shareable) or 010b (if non-shareable) -* - Shareable or non-shareable -* - Non-cacheable -* - Bufferable (if shareable) or non-bufferable (if non-shareable) -* -* \param IsShareable Configures the device memory as shareable or non-shareable. -*/ -#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U)) - -/** -* MPU Memory Access Attribute for normal memory. -* - TEX: 1BBb (reflecting outer cacheability rules) -* - Shareable or non-shareable -* - Cacheable or non-cacheable (reflecting inner cacheability rules) -* - Bufferable or non-bufferable (reflecting inner cacheability rules) -* -* \param OuterCp Configures the outer cache policy. -* \param InnerCp Configures the inner cache policy. -* \param IsShareable Configures the memory as shareable or non-shareable. -*/ -#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) >> 1U), ((InnerCp) & 1U)) - -/** -* MPU Memory Access Attribute non-cacheable policy. -*/ -#define ARM_MPU_CACHEP_NOCACHE 0U - -/** -* MPU Memory Access Attribute write-back, write and read allocate policy. -*/ -#define ARM_MPU_CACHEP_WB_WRA 1U - -/** -* MPU Memory Access Attribute write-through, no write allocate policy. -*/ -#define ARM_MPU_CACHEP_WT_NWA 2U - -/** -* MPU Memory Access Attribute write-back, no write allocate policy. -*/ -#define ARM_MPU_CACHEP_WB_NWA 3U - - -/** -* Struct for a single MPU Region -*/ -typedef struct { - uint32_t RBAR; //!< The region base address register value (RBAR) - uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR -} ARM_MPU_Region_t; - -/** Enable the MPU. -* \param MPU_Control Default access permissions for unconfigured regions. -*/ -__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) -{ - __DMB(); - MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; -#ifdef SCB_SHCSR_MEMFAULTENA_Msk - SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; -#endif - __DSB(); - __ISB(); -} - -/** Disable the MPU. -*/ -__STATIC_INLINE void ARM_MPU_Disable(void) -{ - __DMB(); -#ifdef SCB_SHCSR_MEMFAULTENA_Msk - SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; -#endif - MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; - __DSB(); - __ISB(); -} - -/** Clear and disable the given MPU region. -* \param rnr Region number to be cleared. -*/ -__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) -{ - MPU->RNR = rnr; - MPU->RASR = 0U; -} - -/** Configure an MPU region. -* \param rbar Value for RBAR register. -* \param rasr Value for RASR register. -*/ -__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) -{ - MPU->RBAR = rbar; - MPU->RASR = rasr; -} - -/** Configure the given MPU region. -* \param rnr Region number to be configured. -* \param rbar Value for RBAR register. -* \param rasr Value for RASR register. -*/ -__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) -{ - MPU->RNR = rnr; - MPU->RBAR = rbar; - MPU->RASR = rasr; -} - -/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_Load(). -* \param dst Destination data is copied to. -* \param src Source data is copied from. -* \param len Amount of data words to be copied. -*/ -__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) -{ - uint32_t i; - for (i = 0U; i < len; ++i) - { - dst[i] = src[i]; - } -} - -/** Load the given number of MPU regions from a table. -* \param table Pointer to the MPU configuration table. -* \param cnt Amount of regions to be configured. -*/ -__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) -{ - const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; - while (cnt > MPU_TYPE_RALIASES) { - ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); - table += MPU_TYPE_RALIASES; - cnt -= MPU_TYPE_RALIASES; - } - ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); -} - -#endif diff --git a/lib/main/pico-sdk/rp2_common/cmsis/stub/CMSIS/Core/Include/m-profile/armv81m_pac.h b/lib/main/pico-sdk/rp2_common/cmsis/stub/CMSIS/Core/Include/m-profile/armv81m_pac.h deleted file mode 100644 index 648cf88647..0000000000 --- a/lib/main/pico-sdk/rp2_common/cmsis/stub/CMSIS/Core/Include/m-profile/armv81m_pac.h +++ /dev/null @@ -1,203 +0,0 @@ -/* - * Copyright (c) 2022 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* - * CMSIS-Core(M) PAC key functions for Armv8.1-M PAC extension - */ - -#ifndef PAC_ARMV81_H -#define PAC_ARMV81_H - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -/* ################### PAC Key functions ########################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_PacKeyFunctions PAC Key functions - \brief Functions that access the PAC keys. - @{ - */ - -#if (defined (__ARM_FEATURE_PAUTH) && (__ARM_FEATURE_PAUTH == 1)) - -/** - \brief read the PAC key used for privileged mode - \details Reads the PAC key stored in the PAC_KEY_P registers. - \param [out] pPacKey 128bit PAC key - */ -__STATIC_FORCEINLINE void __get_PAC_KEY_P (uint32_t* pPacKey) { - __ASM volatile ( - "mrs r1, pac_key_p_0\n" - "str r1,[%0,#0]\n" - "mrs r1, pac_key_p_1\n" - "str r1,[%0,#4]\n" - "mrs r1, pac_key_p_2\n" - "str r1,[%0,#8]\n" - "mrs r1, pac_key_p_3\n" - "str r1,[%0,#12]\n" - : : "r" (pPacKey) : "memory", "r1" - ); -} - -/** - \brief write the PAC key used for privileged mode - \details writes the given PAC key to the PAC_KEY_P registers. - \param [in] pPacKey 128bit PAC key - */ -__STATIC_FORCEINLINE void __set_PAC_KEY_P (uint32_t* pPacKey) { - __ASM volatile ( - "ldr r1,[%0,#0]\n" - "msr pac_key_p_0, r1\n" - "ldr r1,[%0,#4]\n" - "msr pac_key_p_1, r1\n" - "ldr r1,[%0,#8]\n" - "msr pac_key_p_2, r1\n" - "ldr r1,[%0,#12]\n" - "msr pac_key_p_3, r1\n" - : : "r" (pPacKey) : "memory", "r1" - ); -} - -/** - \brief read the PAC key used for unprivileged mode - \details Reads the PAC key stored in the PAC_KEY_U registers. - \param [out] pPacKey 128bit PAC key - */ -__STATIC_FORCEINLINE void __get_PAC_KEY_U (uint32_t* pPacKey) { - __ASM volatile ( - "mrs r1, pac_key_u_0\n" - "str r1,[%0,#0]\n" - "mrs r1, pac_key_u_1\n" - "str r1,[%0,#4]\n" - "mrs r1, pac_key_u_2\n" - "str r1,[%0,#8]\n" - "mrs r1, pac_key_u_3\n" - "str r1,[%0,#12]\n" - : : "r" (pPacKey) : "memory", "r1" - ); -} - -/** - \brief write the PAC key used for unprivileged mode - \details writes the given PAC key to the PAC_KEY_U registers. - \param [in] pPacKey 128bit PAC key - */ -__STATIC_FORCEINLINE void __set_PAC_KEY_U (uint32_t* pPacKey) { - __ASM volatile ( - "ldr r1,[%0,#0]\n" - "msr pac_key_u_0, r1\n" - "ldr r1,[%0,#4]\n" - "msr pac_key_u_1, r1\n" - "ldr r1,[%0,#8]\n" - "msr pac_key_u_2, r1\n" - "ldr r1,[%0,#12]\n" - "msr pac_key_u_3, r1\n" - : : "r" (pPacKey) : "memory", "r1" - ); -} - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) - -/** - \brief read the PAC key used for privileged mode (non-secure) - \details Reads the PAC key stored in the non-secure PAC_KEY_P registers when in secure mode. - \param [out] pPacKey 128bit PAC key - */ -__STATIC_FORCEINLINE void __TZ_get_PAC_KEY_P_NS (uint32_t* pPacKey) { - __ASM volatile ( - "mrs r1, pac_key_p_0_ns\n" - "str r1,[%0,#0]\n" - "mrs r1, pac_key_p_1_ns\n" - "str r1,[%0,#4]\n" - "mrs r1, pac_key_p_2_ns\n" - "str r1,[%0,#8]\n" - "mrs r1, pac_key_p_3_ns\n" - "str r1,[%0,#12]\n" - : : "r" (pPacKey) : "memory", "r1" - ); -} - -/** - \brief write the PAC key used for privileged mode (non-secure) - \details writes the given PAC key to the non-secure PAC_KEY_P registers when in secure mode. - \param [in] pPacKey 128bit PAC key - */ -__STATIC_FORCEINLINE void __TZ_set_PAC_KEY_P_NS (uint32_t* pPacKey) { - __ASM volatile ( - "ldr r1,[%0,#0]\n" - "msr pac_key_p_0_ns, r1\n" - "ldr r1,[%0,#4]\n" - "msr pac_key_p_1_ns, r1\n" - "ldr r1,[%0,#8]\n" - "msr pac_key_p_2_ns, r1\n" - "ldr r1,[%0,#12]\n" - "msr pac_key_p_3_ns, r1\n" - : : "r" (pPacKey) : "memory", "r1" - ); -} - -/** - \brief read the PAC key used for unprivileged mode (non-secure) - \details Reads the PAC key stored in the non-secure PAC_KEY_U registers when in secure mode. - \param [out] pPacKey 128bit PAC key - */ -__STATIC_FORCEINLINE void __TZ_get_PAC_KEY_U_NS (uint32_t* pPacKey) { - __ASM volatile ( - "mrs r1, pac_key_u_0_ns\n" - "str r1,[%0,#0]\n" - "mrs r1, pac_key_u_1_ns\n" - "str r1,[%0,#4]\n" - "mrs r1, pac_key_u_2_ns\n" - "str r1,[%0,#8]\n" - "mrs r1, pac_key_u_3_ns\n" - "str r1,[%0,#12]\n" - : : "r" (pPacKey) : "memory", "r1" - ); -} - -/** - \brief write the PAC key used for unprivileged mode (non-secure) - \details writes the given PAC key to the non-secure PAC_KEY_U registers when in secure mode. - \param [in] pPacKey 128bit PAC key - */ -__STATIC_FORCEINLINE void __TZ_set_PAC_KEY_U_NS (uint32_t* pPacKey) { - __ASM volatile ( - "ldr r1,[%0,#0]\n" - "msr pac_key_u_0_ns, r1\n" - "ldr r1,[%0,#4]\n" - "msr pac_key_u_1_ns, r1\n" - "ldr r1,[%0,#8]\n" - "msr pac_key_u_2_ns, r1\n" - "ldr r1,[%0,#12]\n" - "msr pac_key_u_3_ns, r1\n" - : : "r" (pPacKey) : "memory", "r1" - ); -} - -#endif /* (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) */ - -#endif /* (defined (__ARM_FEATURE_PAUTH) && (__ARM_FEATURE_PAUTH == 1)) */ - -/*@} end of CMSIS_Core_PacKeyFunctions */ - - -#endif /* PAC_ARMV81_H */ diff --git a/lib/main/pico-sdk/rp2_common/cmsis/stub/CMSIS/Core/Include/m-profile/armv8m_mpu.h b/lib/main/pico-sdk/rp2_common/cmsis/stub/CMSIS/Core/Include/m-profile/armv8m_mpu.h deleted file mode 100644 index 2b4707854b..0000000000 --- a/lib/main/pico-sdk/rp2_common/cmsis/stub/CMSIS/Core/Include/m-profile/armv8m_mpu.h +++ /dev/null @@ -1,421 +0,0 @@ -/* - * Copyright (c) 2017-2022 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* - * CMSIS-Core(M) MPU API for Armv8-M and Armv8.1-M MPU - */ - -#ifndef ARM_MPU_ARMV8_H -#define ARM_MPU_ARMV8_H - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -/** \brief Attribute for device memory (outer only) */ -#define ARM_MPU_ATTR_DEVICE ( 0U ) - -/** \brief Attribute for non-cacheable, normal memory */ -#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U ) - -/** \brief Attribute for Normal memory, Outer and Inner cacheability. -* \param NT Non-Transient: Set to 1 for Non-transient data. Set to 0 for Transient data. -* \param WB Write-Back: Set to 1 to use a Write-Back policy. Set to 0 to use a Write-Through policy. -* \param RA Read Allocation: Set to 1 to enable cache allocation on read miss. Set to 0 to disable cache allocation on read miss. -* \param WA Write Allocation: Set to 1 to enable cache allocation on write miss. Set to 0 to disable cache allocation on write miss. -*/ -#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \ - ((((NT) & 1U) << 3U) | (((WB) & 1U) << 2U) | (((RA) & 1U) << 1U) | ((WA) & 1U)) - -/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */ -#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U) - -/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */ -#define ARM_MPU_ATTR_DEVICE_nGnRE (1U) - -/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */ -#define ARM_MPU_ATTR_DEVICE_nGRE (2U) - -/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */ -#define ARM_MPU_ATTR_DEVICE_GRE (3U) - -/** \brief Normal memory outer-cacheable and inner-cacheable attributes -* WT = Write Through, WB = Write Back, TR = Transient, RA = Read-Allocate, WA = Write Allocate -*/ -#define MPU_ATTR_NORMAL_OUTER_NON_CACHEABLE (0b0100) -#define MPU_ATTR_NORMAL_OUTER_WT_TR_RA (0b0010) -#define MPU_ATTR_NORMAL_OUTER_WT_TR_WA (0b0001) -#define MPU_ATTR_NORMAL_OUTER_WT_TR_RA_WA (0b0011) -#define MPU_ATTR_NORMAL_OUTER_WT_RA (0b1010) -#define MPU_ATTR_NORMAL_OUTER_WT_WA (0b1001) -#define MPU_ATTR_NORMAL_OUTER_WT_RA_WA (0b1011) -#define MPU_ATTR_NORMAL_OUTER_WB_TR_RA (0b0101) -#define MPU_ATTR_NORMAL_OUTER_WB_TR_WA (0b0110) -#define MPU_ATTR_NORMAL_OUTER_WB_TR_RA_WA (0b0111) -#define MPU_ATTR_NORMAL_OUTER_WB_RA (0b1101) -#define MPU_ATTR_NORMAL_OUTER_WB_WA (0b1110) -#define MPU_ATTR_NORMAL_OUTER_WB_RA_WA (0b1111) -#define MPU_ATTR_NORMAL_INNER_NON_CACHEABLE (0b0100) -#define MPU_ATTR_NORMAL_INNER_WT_TR_RA (0b0010) -#define MPU_ATTR_NORMAL_INNER_WT_TR_WA (0b0001) -#define MPU_ATTR_NORMAL_INNER_WT_TR_RA_WA (0b0011) -#define MPU_ATTR_NORMAL_INNER_WT_RA (0b1010) -#define MPU_ATTR_NORMAL_INNER_WT_WA (0b1001) -#define MPU_ATTR_NORMAL_INNER_WT_RA_WA (0b1011) -#define MPU_ATTR_NORMAL_INNER_WB_TR_RA (0b0101) -#define MPU_ATTR_NORMAL_INNER_WB_TR_WA (0b0110) -#define MPU_ATTR_NORMAL_INNER_WB_TR_RA_WA (0b0111) -#define MPU_ATTR_NORMAL_INNER_WB_RA (0b1101) -#define MPU_ATTR_NORMAL_INNER_WB_WA (0b1110) -#define MPU_ATTR_NORMAL_INNER_WB_RA_WA (0b1111) - -/** \brief Memory Attribute -* \param O Outer memory attributes -* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes -*/ -#define ARM_MPU_ATTR(O, I) ((((O) & 0xFU) << 4U) | ((((O) & 0xFU) != 0U) ? ((I) & 0xFU) : (((I) & 0x3U) << 2U))) - -/* \brief Specifies MAIR_ATTR number */ -#define MAIR_ATTR(x) ((x > 7 || x < 0) ? 0 : x) - -/** - * Shareability - */ -/** \brief Normal memory, non-shareable */ -#define ARM_MPU_SH_NON (0U) - -/** \brief Normal memory, outer shareable */ -#define ARM_MPU_SH_OUTER (2U) - -/** \brief Normal memory, inner shareable */ -#define ARM_MPU_SH_INNER (3U) - -/** - * Access permissions - * AP = Access permission, RO = Read-only, RW = Read/Write, NP = Any privilege, PO = Privileged code only - */ -/** \brief Normal memory, read/write */ -#define ARM_MPU_AP_RW (0U) - -/** \brief Normal memory, read-only */ -#define ARM_MPU_AP_RO (1U) - -/** \brief Normal memory, any privilege level */ -#define ARM_MPU_AP_NP (1U) - -/** \brief Normal memory, privileged access only */ -#define ARM_MPU_AP_PO (0U) - -/* - * Execute-never - * XN = Execute-never, EX = Executable - */ -/** \brief Normal memory, Execution only permitted if read permitted */ -#define ARM_MPU_XN (1U) - -/** \brief Normal memory, Execution only permitted if read permitted */ -#define ARM_MPU_EX (0U) - -/** \brief Memory access permissions -* \param RO Read-Only: Set to 1 for read-only memory. Set to 0 for a read/write memory. -* \param NP Non-Privileged: Set to 1 for non-privileged memory. Set to 0 for privileged memory. -*/ -#define ARM_MPU_AP_(RO, NP) ((((RO) & 1U) << 1U) | ((NP) & 1U)) - -/** \brief Region Base Address Register value -* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned. -* \param SH Defines the Shareability domain for this memory region. -* \param RO Read-Only: Set to 1 for a read-only memory region. Set to 0 for a read/write memory region. -* \param NP Non-Privileged: Set to 1 for a non-privileged memory region. Set to 0 for privileged memory region. -* \param XN eXecute Never: Set to 1 for a non-executable memory region. Set to 0 for an executable memory region. -*/ -#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ - (((BASE) & MPU_RBAR_BASE_Msk) | \ - (((SH) << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \ - ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \ - (((XN) << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk)) - -/** \brief Region Limit Address Register value -* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. -* \param IDX The attribute index to be associated with this memory region. -*/ -#define ARM_MPU_RLAR(LIMIT, IDX) \ - (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \ - (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ - (MPU_RLAR_EN_Msk)) - -#if defined(MPU_RLAR_PXN_Pos) - -/** \brief Region Limit Address Register with PXN value -* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. -* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region. -* \param IDX The attribute index to be associated with this memory region. -*/ -#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \ - (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \ - (((PXN) << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \ - (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ - (MPU_RLAR_EN_Msk)) - -#endif - -/** -* Struct for a single MPU Region -*/ -typedef struct { - uint32_t RBAR; /*!< Region Base Address Register value */ - uint32_t RLAR; /*!< Region Limit Address Register value */ -} ARM_MPU_Region_t; - -/** - \brief Read MPU Type Register - \return Number of MPU regions -*/ -__STATIC_INLINE uint32_t ARM_MPU_TYPE(void) -{ - return ((MPU->TYPE) >> 8); -} - -/** Enable the MPU. -* \param MPU_Control Default access permissions for unconfigured regions. -*/ -__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) -{ - __DMB(); - MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; -#ifdef SCB_SHCSR_MEMFAULTENA_Msk - SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; -#endif - __DSB(); - __ISB(); -} - -/** Disable the MPU. -*/ -__STATIC_INLINE void ARM_MPU_Disable(void) -{ - __DMB(); -#ifdef SCB_SHCSR_MEMFAULTENA_Msk - SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; -#endif - MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; - __DSB(); - __ISB(); -} - -#ifdef MPU_NS -/** Enable the Non-secure MPU. -* \param MPU_Control Default access permissions for unconfigured regions. -*/ -__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control) -{ - __DMB(); - MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; -#ifdef SCB_SHCSR_MEMFAULTENA_Msk - SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; -#endif - __DSB(); - __ISB(); -} - -/** Disable the Non-secure MPU. -*/ -__STATIC_INLINE void ARM_MPU_Disable_NS(void) -{ - __DMB(); -#ifdef SCB_SHCSR_MEMFAULTENA_Msk - SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; -#endif - MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; - __DSB(); - __ISB(); -} -#endif - -/** Set the memory attribute encoding to the given MPU. -* \param mpu Pointer to the MPU to be configured. -* \param idx The attribute index to be set [0-7] -* \param attr The attribute value to be set. -*/ -__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr) -{ - const uint8_t reg = idx / 4U; - const uint32_t pos = ((idx % 4U) * 8U); - const uint32_t mask = 0xFFU << pos; - - if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) { - return; // invalid index - } - - mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask)); -} - -/** Set the memory attribute encoding. -* \param idx The attribute index to be set [0-7] -* \param attr The attribute value to be set. -*/ -__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr) -{ - ARM_MPU_SetMemAttrEx(MPU, idx, attr); -} - -#ifdef MPU_NS -/** Set the memory attribute encoding to the Non-secure MPU. -* \param idx The attribute index to be set [0-7] -* \param attr The attribute value to be set. -*/ -__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr) -{ - ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr); -} -#endif - -/** Clear and disable the given MPU region of the given MPU. -* \param mpu Pointer to MPU to be used. -* \param rnr Region number to be cleared. -*/ -__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr) -{ - mpu->RNR = rnr; - mpu->RLAR = 0U; -} - -/** Clear and disable the given MPU region. -* \param rnr Region number to be cleared. -*/ -__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) -{ - ARM_MPU_ClrRegionEx(MPU, rnr); -} - -#ifdef MPU_NS -/** Clear and disable the given Non-secure MPU region. -* \param rnr Region number to be cleared. -*/ -__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) -{ - ARM_MPU_ClrRegionEx(MPU_NS, rnr); -} -#endif - -/** Configure the given MPU region of the given MPU. -* \param mpu Pointer to MPU to be used. -* \param rnr Region number to be configured. -* \param rbar Value for RBAR register. -* \param rlar Value for RLAR register. -*/ -__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) -{ - mpu->RNR = rnr; - mpu->RBAR = rbar; - mpu->RLAR = rlar; -} - -/** Configure the given MPU region. -* \param rnr Region number to be configured. -* \param rbar Value for RBAR register. -* \param rlar Value for RLAR register. -*/ -__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar) -{ - ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar); -} - -#ifdef MPU_NS -/** Configure the given Non-secure MPU region. -* \param rnr Region number to be configured. -* \param rbar Value for RBAR register. -* \param rlar Value for RLAR register. -*/ -__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar) -{ - ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); -} -#endif - -/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_LoadEx() -* \param dst Destination data is copied to. -* \param src Source data is copied from. -* \param len Amount of data words to be copied. -*/ -__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) -{ - uint32_t i; - for (i = 0U; i < len; ++i) - { - dst[i] = src[i]; - } -} - -/** Load the given number of MPU regions from a table to the given MPU. -* \param mpu Pointer to the MPU registers to be used. -* \param rnr First region number to be configured. -* \param table Pointer to the MPU configuration table. -* \param cnt Amount of regions to be configured. -*/ -__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) -{ - const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; - if (cnt == 1U) { - mpu->RNR = rnr; - ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize); - } else { - uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U); - uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; - - mpu->RNR = rnrBase; - while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { - uint32_t c = MPU_TYPE_RALIASES - rnrOffset; - ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize); - table += c; - cnt -= c; - rnrOffset = 0U; - rnrBase += MPU_TYPE_RALIASES; - mpu->RNR = rnrBase; - } - - ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); - } -} - -/** Load the given number of MPU regions from a table. -* \param rnr First region number to be configured. -* \param table Pointer to the MPU configuration table. -* \param cnt Amount of regions to be configured. -*/ -__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) -{ - ARM_MPU_LoadEx(MPU, rnr, table, cnt); -} - -#ifdef MPU_NS -/** Load the given number of MPU regions from a table to the Non-secure MPU. -* \param rnr First region number to be configured. -* \param table Pointer to the MPU configuration table. -* \param cnt Amount of regions to be configured. -*/ -__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) -{ - ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt); -} -#endif - -#endif - diff --git a/lib/main/pico-sdk/rp2_common/cmsis/stub/CMSIS/Core/Include/m-profile/armv8m_pmu.h b/lib/main/pico-sdk/rp2_common/cmsis/stub/CMSIS/Core/Include/m-profile/armv8m_pmu.h deleted file mode 100644 index fb16533173..0000000000 --- a/lib/main/pico-sdk/rp2_common/cmsis/stub/CMSIS/Core/Include/m-profile/armv8m_pmu.h +++ /dev/null @@ -1,335 +0,0 @@ -/* - * Copyright (c) 2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* - * CMSIS-Core(M) PMU API for Armv8.1-M PMU - */ - -#ifndef ARM_PMU_ARMV8_H -#define ARM_PMU_ARMV8_H - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -/** - * \brief PMU Events - * \note See the Armv8.1-M Architecture Reference Manual for full details on these PMU events. - * */ - -#define ARM_PMU_SW_INCR 0x0000 /*!< Software update to the PMU_SWINC register, architecturally executed and condition code check pass */ -#define ARM_PMU_L1I_CACHE_REFILL 0x0001 /*!< L1 I-Cache refill */ -#define ARM_PMU_L1D_CACHE_REFILL 0x0003 /*!< L1 D-Cache refill */ -#define ARM_PMU_L1D_CACHE 0x0004 /*!< L1 D-Cache access */ -#define ARM_PMU_LD_RETIRED 0x0006 /*!< Memory-reading instruction architecturally executed and condition code check pass */ -#define ARM_PMU_ST_RETIRED 0x0007 /*!< Memory-writing instruction architecturally executed and condition code check pass */ -#define ARM_PMU_INST_RETIRED 0x0008 /*!< Instruction architecturally executed */ -#define ARM_PMU_EXC_TAKEN 0x0009 /*!< Exception entry */ -#define ARM_PMU_EXC_RETURN 0x000A /*!< Exception return instruction architecturally executed and the condition code check pass */ -#define ARM_PMU_PC_WRITE_RETIRED 0x000C /*!< Software change to the Program Counter (PC). Instruction is architecturally executed and condition code check pass */ -#define ARM_PMU_BR_IMMED_RETIRED 0x000D /*!< Immediate branch architecturally executed */ -#define ARM_PMU_BR_RETURN_RETIRED 0x000E /*!< Function return instruction architecturally executed and the condition code check pass */ -#define ARM_PMU_UNALIGNED_LDST_RETIRED 0x000F /*!< Unaligned memory memory-reading or memory-writing instruction architecturally executed and condition code check pass */ -#define ARM_PMU_BR_MIS_PRED 0x0010 /*!< Mispredicted or not predicted branch speculatively executed */ -#define ARM_PMU_CPU_CYCLES 0x0011 /*!< Cycle */ -#define ARM_PMU_BR_PRED 0x0012 /*!< Predictable branch speculatively executed */ -#define ARM_PMU_MEM_ACCESS 0x0013 /*!< Data memory access */ -#define ARM_PMU_L1I_CACHE 0x0014 /*!< Level 1 instruction cache access */ -#define ARM_PMU_L1D_CACHE_WB 0x0015 /*!< Level 1 data cache write-back */ -#define ARM_PMU_L2D_CACHE 0x0016 /*!< Level 2 data cache access */ -#define ARM_PMU_L2D_CACHE_REFILL 0x0017 /*!< Level 2 data cache refill */ -#define ARM_PMU_L2D_CACHE_WB 0x0018 /*!< Level 2 data cache write-back */ -#define ARM_PMU_BUS_ACCESS 0x0019 /*!< Bus access */ -#define ARM_PMU_MEMORY_ERROR 0x001A /*!< Local memory error */ -#define ARM_PMU_INST_SPEC 0x001B /*!< Instruction speculatively executed */ -#define ARM_PMU_BUS_CYCLES 0x001D /*!< Bus cycles */ -#define ARM_PMU_CHAIN 0x001E /*!< For an odd numbered counter, increment when an overflow occurs on the preceding even-numbered counter on the same PE */ -#define ARM_PMU_L1D_CACHE_ALLOCATE 0x001F /*!< Level 1 data cache allocation without refill */ -#define ARM_PMU_L2D_CACHE_ALLOCATE 0x0020 /*!< Level 2 data cache allocation without refill */ -#define ARM_PMU_BR_RETIRED 0x0021 /*!< Branch instruction architecturally executed */ -#define ARM_PMU_BR_MIS_PRED_RETIRED 0x0022 /*!< Mispredicted branch instruction architecturally executed */ -#define ARM_PMU_STALL_FRONTEND 0x0023 /*!< No operation issued because of the frontend */ -#define ARM_PMU_STALL_BACKEND 0x0024 /*!< No operation issued because of the backend */ -#define ARM_PMU_L2I_CACHE 0x0027 /*!< Level 2 instruction cache access */ -#define ARM_PMU_L2I_CACHE_REFILL 0x0028 /*!< Level 2 instruction cache refill */ -#define ARM_PMU_L3D_CACHE_ALLOCATE 0x0029 /*!< Level 3 data cache allocation without refill */ -#define ARM_PMU_L3D_CACHE_REFILL 0x002A /*!< Level 3 data cache refill */ -#define ARM_PMU_L3D_CACHE 0x002B /*!< Level 3 data cache access */ -#define ARM_PMU_L3D_CACHE_WB 0x002C /*!< Level 3 data cache write-back */ -#define ARM_PMU_LL_CACHE_RD 0x0036 /*!< Last level data cache read */ -#define ARM_PMU_LL_CACHE_MISS_RD 0x0037 /*!< Last level data cache read miss */ -#define ARM_PMU_L1D_CACHE_MISS_RD 0x0039 /*!< Level 1 data cache read miss */ -#define ARM_PMU_OP_COMPLETE 0x003A /*!< Operation retired */ -#define ARM_PMU_OP_SPEC 0x003B /*!< Operation speculatively executed */ -#define ARM_PMU_STALL 0x003C /*!< Stall cycle for instruction or operation not sent for execution */ -#define ARM_PMU_STALL_OP_BACKEND 0x003D /*!< Stall cycle for instruction or operation not sent for execution due to pipeline backend */ -#define ARM_PMU_STALL_OP_FRONTEND 0x003E /*!< Stall cycle for instruction or operation not sent for execution due to pipeline frontend */ -#define ARM_PMU_STALL_OP 0x003F /*!< Instruction or operation slots not occupied each cycle */ -#define ARM_PMU_L1D_CACHE_RD 0x0040 /*!< Level 1 data cache read */ -#define ARM_PMU_LE_RETIRED 0x0100 /*!< Loop end instruction executed */ -#define ARM_PMU_LE_SPEC 0x0101 /*!< Loop end instruction speculatively executed */ -#define ARM_PMU_BF_RETIRED 0x0104 /*!< Branch future instruction architecturally executed and condition code check pass */ -#define ARM_PMU_BF_SPEC 0x0105 /*!< Branch future instruction speculatively executed and condition code check pass */ -#define ARM_PMU_LE_CANCEL 0x0108 /*!< Loop end instruction not taken */ -#define ARM_PMU_BF_CANCEL 0x0109 /*!< Branch future instruction not taken */ -#define ARM_PMU_SE_CALL_S 0x0114 /*!< Call to secure function, resulting in Security state change */ -#define ARM_PMU_SE_CALL_NS 0x0115 /*!< Call to non-secure function, resulting in Security state change */ -#define ARM_PMU_DWT_CMPMATCH0 0x0118 /*!< DWT comparator 0 match */ -#define ARM_PMU_DWT_CMPMATCH1 0x0119 /*!< DWT comparator 1 match */ -#define ARM_PMU_DWT_CMPMATCH2 0x011A /*!< DWT comparator 2 match */ -#define ARM_PMU_DWT_CMPMATCH3 0x011B /*!< DWT comparator 3 match */ -#define ARM_PMU_MVE_INST_RETIRED 0x0200 /*!< MVE instruction architecturally executed */ -#define ARM_PMU_MVE_INST_SPEC 0x0201 /*!< MVE instruction speculatively executed */ -#define ARM_PMU_MVE_FP_RETIRED 0x0204 /*!< MVE floating-point instruction architecturally executed */ -#define ARM_PMU_MVE_FP_SPEC 0x0205 /*!< MVE floating-point instruction speculatively executed */ -#define ARM_PMU_MVE_FP_HP_RETIRED 0x0208 /*!< MVE half-precision floating-point instruction architecturally executed */ -#define ARM_PMU_MVE_FP_HP_SPEC 0x0209 /*!< MVE half-precision floating-point instruction speculatively executed */ -#define ARM_PMU_MVE_FP_SP_RETIRED 0x020C /*!< MVE single-precision floating-point instruction architecturally executed */ -#define ARM_PMU_MVE_FP_SP_SPEC 0x020D /*!< MVE single-precision floating-point instruction speculatively executed */ -#define ARM_PMU_MVE_FP_MAC_RETIRED 0x0214 /*!< MVE floating-point multiply or multiply-accumulate instruction architecturally executed */ -#define ARM_PMU_MVE_FP_MAC_SPEC 0x0215 /*!< MVE floating-point multiply or multiply-accumulate instruction speculatively executed */ -#define ARM_PMU_MVE_INT_RETIRED 0x0224 /*!< MVE integer instruction architecturally executed */ -#define ARM_PMU_MVE_INT_SPEC 0x0225 /*!< MVE integer instruction speculatively executed */ -#define ARM_PMU_MVE_INT_MAC_RETIRED 0x0228 /*!< MVE multiply or multiply-accumulate instruction architecturally executed */ -#define ARM_PMU_MVE_INT_MAC_SPEC 0x0229 /*!< MVE multiply or multiply-accumulate instruction speculatively executed */ -#define ARM_PMU_MVE_LDST_RETIRED 0x0238 /*!< MVE load or store instruction architecturally executed */ -#define ARM_PMU_MVE_LDST_SPEC 0x0239 /*!< MVE load or store instruction speculatively executed */ -#define ARM_PMU_MVE_LD_RETIRED 0x023C /*!< MVE load instruction architecturally executed */ -#define ARM_PMU_MVE_LD_SPEC 0x023D /*!< MVE load instruction speculatively executed */ -#define ARM_PMU_MVE_ST_RETIRED 0x0240 /*!< MVE store instruction architecturally executed */ -#define ARM_PMU_MVE_ST_SPEC 0x0241 /*!< MVE store instruction speculatively executed */ -#define ARM_PMU_MVE_LDST_CONTIG_RETIRED 0x0244 /*!< MVE contiguous load or store instruction architecturally executed */ -#define ARM_PMU_MVE_LDST_CONTIG_SPEC 0x0245 /*!< MVE contiguous load or store instruction speculatively executed */ -#define ARM_PMU_MVE_LD_CONTIG_RETIRED 0x0248 /*!< MVE contiguous load instruction architecturally executed */ -#define ARM_PMU_MVE_LD_CONTIG_SPEC 0x0249 /*!< MVE contiguous load instruction speculatively executed */ -#define ARM_PMU_MVE_ST_CONTIG_RETIRED 0x024C /*!< MVE contiguous store instruction architecturally executed */ -#define ARM_PMU_MVE_ST_CONTIG_SPEC 0x024D /*!< MVE contiguous store instruction speculatively executed */ -#define ARM_PMU_MVE_LDST_NONCONTIG_RETIRED 0x0250 /*!< MVE non-contiguous load or store instruction architecturally executed */ -#define ARM_PMU_MVE_LDST_NONCONTIG_SPEC 0x0251 /*!< MVE non-contiguous load or store instruction speculatively executed */ -#define ARM_PMU_MVE_LD_NONCONTIG_RETIRED 0x0254 /*!< MVE non-contiguous load instruction architecturally executed */ -#define ARM_PMU_MVE_LD_NONCONTIG_SPEC 0x0255 /*!< MVE non-contiguous load instruction speculatively executed */ -#define ARM_PMU_MVE_ST_NONCONTIG_RETIRED 0x0258 /*!< MVE non-contiguous store instruction architecturally executed */ -#define ARM_PMU_MVE_ST_NONCONTIG_SPEC 0x0259 /*!< MVE non-contiguous store instruction speculatively executed */ -#define ARM_PMU_MVE_LDST_MULTI_RETIRED 0x025C /*!< MVE memory instruction targeting multiple registers architecturally executed */ -#define ARM_PMU_MVE_LDST_MULTI_SPEC 0x025D /*!< MVE memory instruction targeting multiple registers speculatively executed */ -#define ARM_PMU_MVE_LD_MULTI_RETIRED 0x0260 /*!< MVE memory load instruction targeting multiple registers architecturally executed */ -#define ARM_PMU_MVE_LD_MULTI_SPEC 0x0261 /*!< MVE memory load instruction targeting multiple registers speculatively executed */ -#define ARM_PMU_MVE_ST_MULTI_RETIRED 0x0261 /*!< MVE memory store instruction targeting multiple registers architecturally executed */ -#define ARM_PMU_MVE_ST_MULTI_SPEC 0x0265 /*!< MVE memory store instruction targeting multiple registers speculatively executed */ -#define ARM_PMU_MVE_LDST_UNALIGNED_RETIRED 0x028C /*!< MVE unaligned memory load or store instruction architecturally executed */ -#define ARM_PMU_MVE_LDST_UNALIGNED_SPEC 0x028D /*!< MVE unaligned memory load or store instruction speculatively executed */ -#define ARM_PMU_MVE_LD_UNALIGNED_RETIRED 0x0290 /*!< MVE unaligned load instruction architecturally executed */ -#define ARM_PMU_MVE_LD_UNALIGNED_SPEC 0x0291 /*!< MVE unaligned load instruction speculatively executed */ -#define ARM_PMU_MVE_ST_UNALIGNED_RETIRED 0x0294 /*!< MVE unaligned store instruction architecturally executed */ -#define ARM_PMU_MVE_ST_UNALIGNED_SPEC 0x0295 /*!< MVE unaligned store instruction speculatively executed */ -#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_RETIRED 0x0298 /*!< MVE unaligned noncontiguous load or store instruction architecturally executed */ -#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_SPEC 0x0299 /*!< MVE unaligned noncontiguous load or store instruction speculatively executed */ -#define ARM_PMU_MVE_VREDUCE_RETIRED 0x02A0 /*!< MVE vector reduction instruction architecturally executed */ -#define ARM_PMU_MVE_VREDUCE_SPEC 0x02A1 /*!< MVE vector reduction instruction speculatively executed */ -#define ARM_PMU_MVE_VREDUCE_FP_RETIRED 0x02A4 /*!< MVE floating-point vector reduction instruction architecturally executed */ -#define ARM_PMU_MVE_VREDUCE_FP_SPEC 0x02A5 /*!< MVE floating-point vector reduction instruction speculatively executed */ -#define ARM_PMU_MVE_VREDUCE_INT_RETIRED 0x02A8 /*!< MVE integer vector reduction instruction architecturally executed */ -#define ARM_PMU_MVE_VREDUCE_INT_SPEC 0x02A9 /*!< MVE integer vector reduction instruction speculatively executed */ -#define ARM_PMU_MVE_PRED 0x02B8 /*!< Cycles where one or more predicated beats architecturally executed */ -#define ARM_PMU_MVE_STALL 0x02CC /*!< Stall cycles caused by an MVE instruction */ -#define ARM_PMU_MVE_STALL_RESOURCE 0x02CD /*!< Stall cycles caused by an MVE instruction because of resource conflicts */ -#define ARM_PMU_MVE_STALL_RESOURCE_MEM 0x02CE /*!< Stall cycles caused by an MVE instruction because of memory resource conflicts */ -#define ARM_PMU_MVE_STALL_RESOURCE_FP 0x02CF /*!< Stall cycles caused by an MVE instruction because of floating-point resource conflicts */ -#define ARM_PMU_MVE_STALL_RESOURCE_INT 0x02D0 /*!< Stall cycles caused by an MVE instruction because of integer resource conflicts */ -#define ARM_PMU_MVE_STALL_BREAK 0x02D3 /*!< Stall cycles caused by an MVE chain break */ -#define ARM_PMU_MVE_STALL_DEPENDENCY 0x02D4 /*!< Stall cycles caused by MVE register dependency */ -#define ARM_PMU_ITCM_ACCESS 0x4007 /*!< Instruction TCM access */ -#define ARM_PMU_DTCM_ACCESS 0x4008 /*!< Data TCM access */ -#define ARM_PMU_TRCEXTOUT0 0x4010 /*!< ETM external output 0 */ -#define ARM_PMU_TRCEXTOUT1 0x4011 /*!< ETM external output 1 */ -#define ARM_PMU_TRCEXTOUT2 0x4012 /*!< ETM external output 2 */ -#define ARM_PMU_TRCEXTOUT3 0x4013 /*!< ETM external output 3 */ -#define ARM_PMU_CTI_TRIGOUT4 0x4018 /*!< Cross-trigger Interface output trigger 4 */ -#define ARM_PMU_CTI_TRIGOUT5 0x4019 /*!< Cross-trigger Interface output trigger 5 */ -#define ARM_PMU_CTI_TRIGOUT6 0x401A /*!< Cross-trigger Interface output trigger 6 */ -#define ARM_PMU_CTI_TRIGOUT7 0x401B /*!< Cross-trigger Interface output trigger 7 */ - -/** \brief PMU Functions */ - -__STATIC_INLINE void ARM_PMU_Enable(void); -__STATIC_INLINE void ARM_PMU_Disable(void); - -__STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type); - -__STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void); -__STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void); - -__STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask); -__STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask); - -__STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void); -__STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num); - -__STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void); -__STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask); - -__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask); -__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask); - -__STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask); - -/** - \brief Enable the PMU -*/ -__STATIC_INLINE void ARM_PMU_Enable(void) -{ - PMU->CTRL |= PMU_CTRL_ENABLE_Msk; -} - -/** - \brief Disable the PMU -*/ -__STATIC_INLINE void ARM_PMU_Disable(void) -{ - PMU->CTRL &= ~PMU_CTRL_ENABLE_Msk; -} - -/** - \brief Set event to count for PMU eventer counter - \param [in] num Event counter (0-30) to configure - \param [in] type Event to count -*/ -__STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type) -{ - PMU->EVTYPER[num] = type; -} - -/** - \brief Reset cycle counter -*/ -__STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void) -{ - PMU->CTRL |= PMU_CTRL_CYCCNT_RESET_Msk; -} - -/** - \brief Reset all event counters -*/ -__STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void) -{ - PMU->CTRL |= PMU_CTRL_EVENTCNT_RESET_Msk; -} - -/** - \brief Enable counters - \param [in] mask Counters to enable - \note Enables one or more of the following: - - event counters (0-30) - - cycle counter -*/ -__STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask) -{ - PMU->CNTENSET = mask; -} - -/** - \brief Disable counters - \param [in] mask Counters to enable - \note Disables one or more of the following: - - event counters (0-30) - - cycle counter -*/ -__STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask) -{ - PMU->CNTENCLR = mask; -} - -/** - \brief Read cycle counter - \return Cycle count -*/ -__STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void) -{ - return PMU->CCNTR; -} - -/** - \brief Read event counter - \param [in] num Event counter (0-30) to read - \return Event count -*/ -__STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num) -{ - return PMU_EVCNTR_CNT_Msk & PMU->EVCNTR[num]; -} - -/** - \brief Read counter overflow status - \return Counter overflow status bits for the following: - - event counters (0-30) - - cycle counter -*/ -__STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void) -{ - return PMU->OVSSET; -} - -/** - \brief Clear counter overflow status - \param [in] mask Counter overflow status bits to clear - \note Clears overflow status bits for one or more of the following: - - event counters (0-30) - - cycle counter -*/ -__STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask) -{ - PMU->OVSCLR = mask; -} - -/** - \brief Enable counter overflow interrupt request - \param [in] mask Counter overflow interrupt request bits to set - \note Sets overflow interrupt request bits for one or more of the following: - - event counters (0-30) - - cycle counter -*/ -__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask) -{ - PMU->INTENSET = mask; -} - -/** - \brief Disable counter overflow interrupt request - \param [in] mask Counter overflow interrupt request bits to clear - \note Clears overflow interrupt request bits for one or more of the following: - - event counters (0-30) - - cycle counter -*/ -__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask) -{ - PMU->INTENCLR = mask; -} - -/** - \brief Software increment event counter - \param [in] mask Counters to increment - \note Software increment bits for one or more event counters (0-30) -*/ -__STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask) -{ - PMU->SWINC = mask; -} - -#endif diff --git a/lib/main/pico-sdk/rp2_common/cmsis/stub/CMSIS/Core/Include/m-profile/cmsis_armclang_m.h b/lib/main/pico-sdk/rp2_common/cmsis/stub/CMSIS/Core/Include/m-profile/cmsis_armclang_m.h deleted file mode 100644 index 82fb6d46f4..0000000000 --- a/lib/main/pico-sdk/rp2_common/cmsis/stub/CMSIS/Core/Include/m-profile/cmsis_armclang_m.h +++ /dev/null @@ -1,818 +0,0 @@ -/* - * Copyright (c) 2009-2024 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* - * CMSIS-Core(M) Compiler ARMClang (Arm Compiler 6) Header File - */ - -#ifndef __CMSIS_ARMCLANG_M_H -#define __CMSIS_ARMCLANG_M_H - -#pragma clang system_header /* treat file as system include file */ - -#ifndef __CMSIS_ARMCLANG_H - #error "This file must not be included directly" -#endif - -#if (__ARM_ACLE >= 200) - #include -#else - #error Compiler must support ACLE V2.0 -#endif /* (__ARM_ACLE >= 200) */ - -/* ######################### Startup and Lowlevel Init ######################## */ -#ifndef __PROGRAM_START -#define __PROGRAM_START __main -#endif - -#ifndef __INITIAL_SP -#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit -#endif - -#ifndef __STACK_LIMIT -#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base -#endif - -#ifndef __VECTOR_TABLE -#define __VECTOR_TABLE __Vectors -#endif - -#ifndef __VECTOR_TABLE_ATTRIBUTE -#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) -#endif - -#if (__ARM_FEATURE_CMSE == 3) -#ifndef __STACK_SEAL -#define __STACK_SEAL Image$$STACKSEAL$$ZI$$Base -#endif - -#ifndef __TZ_STACK_SEAL_SIZE -#define __TZ_STACK_SEAL_SIZE 8U -#endif - -#ifndef __TZ_STACK_SEAL_VALUE -#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL -#endif - - -__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { - *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; - } -#endif - -#if (__ARM_ARCH_ISA_THUMB >= 2) -/** - \brief STRT Unprivileged (8 bit) - \details Executes a Unprivileged STRT instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) -{ - __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (16 bit) - \details Executes a Unprivileged STRT instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) -{ - __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (32 bit) - \details Executes a Unprivileged STRT instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) -{ - __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); -} -#endif /* (__ARM_ARCH_ISA_THUMB >= 2) */ - - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - - -/** - \brief Get Control Register - \details Returns the content of the Control Register. - \return Control Register value - */ -__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control" : "=r" (result) ); - return (result); -} - - -#if (__ARM_FEATURE_CMSE == 3) -/** - \brief Get Control Register (non-secure) - \details Returns the content of the non-secure Control Register when in secure mode. - \return non-secure Control Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); - return (result); -} -#endif - - -/** - \brief Set Control Register - \details Writes the given value to the Control Register. - \param [in] control Control Register value to set - */ -__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) -{ - __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); - __ISB(); -} - - -#if (__ARM_FEATURE_CMSE == 3) -/** - \brief Set Control Register (non-secure) - \details Writes the given value to the non-secure Control Register when in secure state. - \param [in] control Control Register value to set - */ -__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) -{ - __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); - __ISB(); -} -#endif - - -/** - \brief Get IPSR Register - \details Returns the content of the IPSR Register. - \return IPSR Register value - */ -__STATIC_FORCEINLINE uint32_t __get_IPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); - return (result); -} - - -/** - \brief Get APSR Register - \details Returns the content of the APSR Register. - \return APSR Register value - */ -__STATIC_FORCEINLINE uint32_t __get_APSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, apsr" : "=r" (result) ); - return (result); -} - - -/** - \brief Get xPSR Register - \details Returns the content of the xPSR Register. - \return xPSR Register value - */ -__STATIC_FORCEINLINE uint32_t __get_xPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); - return (result); -} - - -/** - \brief Get Process Stack Pointer - \details Returns the current value of the Process Stack Pointer (PSP). - \return PSP Register value - */ -__STATIC_FORCEINLINE uint32_t __get_PSP(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, psp" : "=r" (result) ); - return (result); -} - - -#if (__ARM_FEATURE_CMSE == 3) -/** - \brief Get Process Stack Pointer (non-secure) - \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. - \return PSP Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); - return (result); -} -#endif - - -/** - \brief Set Process Stack Pointer - \details Assigns the given value to the Process Stack Pointer (PSP). - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); -} - - -#if (__ARM_FEATURE_CMSE == 3) -/** - \brief Set Process Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); -} -#endif - - -/** - \brief Get Main Stack Pointer - \details Returns the current value of the Main Stack Pointer (MSP). - \return MSP Register value - */ -__STATIC_FORCEINLINE uint32_t __get_MSP(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, msp" : "=r" (result) ); - return (result); -} - - -#if (__ARM_FEATURE_CMSE == 3) -/** - \brief Get Main Stack Pointer (non-secure) - \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. - \return MSP Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); - return (result); -} -#endif - - -/** - \brief Set Main Stack Pointer - \details Assigns the given value to the Main Stack Pointer (MSP). - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); -} - - -#if (__ARM_FEATURE_CMSE == 3) -/** - \brief Set Main Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); -} -#endif - - -#if (__ARM_FEATURE_CMSE == 3) -/** - \brief Get Stack Pointer (non-secure) - \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. - \return SP Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); - return (result); -} - - -/** - \brief Set Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. - \param [in] topOfStack Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) -{ - __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); -} -#endif - - -/** - \brief Get Priority Mask - \details Returns the current state of the priority mask bit from the Priority Mask Register. - \return Priority Mask value - */ -__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask" : "=r" (result) ); - return (result); -} - - -#if (__ARM_FEATURE_CMSE == 3) -/** - \brief Get Priority Mask (non-secure) - \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. - \return Priority Mask value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); - return (result); -} -#endif - - -/** - \brief Set Priority Mask - \details Assigns the given value to the Priority Mask Register. - \param [in] priMask Priority Mask - */ -__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) -{ - __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); -} - - -#if (__ARM_FEATURE_CMSE == 3) -/** - \brief Set Priority Mask (non-secure) - \details Assigns the given value to the non-secure Priority Mask Register when in secure state. - \param [in] priMask Priority Mask - */ -__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) -{ - __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); -} -#endif - - -#if (__ARM_ARCH_ISA_THUMB >= 2) -/** - \brief Get Base Priority - \details Returns the current value of the Base Priority register. - \return Base Priority register value - */ -__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri" : "=r" (result) ); - return (result); -} - - -#if (__ARM_FEATURE_CMSE == 3) -/** - \brief Get Base Priority (non-secure) - \details Returns the current value of the non-secure Base Priority register when in secure state. - \return Base Priority register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); - return (result); -} -#endif - - -/** - \brief Set Base Priority - \details Assigns the given value to the Base Priority register. - \param [in] basePri Base Priority value to set - */ -__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) -{ - __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); -} - - -#if (__ARM_FEATURE_CMSE == 3) -/** - \brief Set Base Priority (non-secure) - \details Assigns the given value to the non-secure Base Priority register when in secure state. - \param [in] basePri Base Priority value to set - */ -__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) -{ - __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); -} -#endif - - -/** - \brief Set Base Priority with condition - \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, - or the new value increases the BASEPRI priority level. - \param [in] basePri Base Priority value to set - */ -__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) -{ - __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); -} - - -/** - \brief Get Fault Mask - \details Returns the current value of the Fault Mask register. - \return Fault Mask register value - */ -__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); - return (result); -} - - -#if (__ARM_FEATURE_CMSE == 3) -/** - \brief Get Fault Mask (non-secure) - \details Returns the current value of the non-secure Fault Mask register when in secure state. - \return Fault Mask register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); - return (result); -} -#endif - - -/** - \brief Set Fault Mask - \details Assigns the given value to the Fault Mask register. - \param [in] faultMask Fault Mask value to set - */ -__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); -} - - -#if (__ARM_FEATURE_CMSE == 3) -/** - \brief Set Fault Mask (non-secure) - \details Assigns the given value to the non-secure Fault Mask register when in secure state. - \param [in] faultMask Fault Mask value to set - */ -__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); -} -#endif - -#endif /* (__ARM_ARCH_ISA_THUMB >= 2) */ - - -#if (__ARM_ARCH >= 8) -/** - \brief Get Process Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always in non-secure - mode. - - \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). - \return PSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) -{ -#if (((__ARM_ARCH_8M_MAIN__ < 1) && \ - (__ARM_ARCH_8_1M_MAIN__ < 1) ) && \ - (__ARM_FEATURE_CMSE < 3) ) - /* without main extensions, the non-secure PSPLIM is RAZ/WI */ - return (0U); -#else - uint32_t result; - __ASM volatile ("MRS %0, psplim" : "=r" (result) ); - return (result); -#endif -} - -#if (__ARM_FEATURE_CMSE == 3) -/** - \brief Get Process Stack Pointer Limit (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always. - - \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. - \return PSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) -{ -#if ((__ARM_ARCH_8M_MAIN__ < 1) && \ - (__ARM_ARCH_8_1M_MAIN__ < 1) ) - /* without main extensions, the non-secure PSPLIM is RAZ/WI */ - return (0U); -#else - uint32_t result; - __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); - return (result); -#endif -} -#endif - - -/** - \brief Set Process Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored in non-secure - mode. - - \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). - \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set - */ -__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) -{ -#if (((__ARM_ARCH_8M_MAIN__ < 1) && \ - (__ARM_ARCH_8_1M_MAIN__ < 1) ) && \ - (__ARM_FEATURE_CMSE < 3) ) - /* without main extensions, the non-secure PSPLIM is RAZ/WI */ - (void)ProcStackPtrLimit; -#else - __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); -#endif -} - - -#if (__ARM_FEATURE_CMSE == 3) -/** - \brief Set Process Stack Pointer (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored. - - \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. - \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set - */ -__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) -{ -#if ((__ARM_ARCH_8M_MAIN__ < 1) && \ - (__ARM_ARCH_8_1M_MAIN__ < 1) ) - /* without main extensions, the non-secure PSPLIM is RAZ/WI */ - (void)ProcStackPtrLimit; -#else - __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); -#endif -} -#endif - - -/** - \brief Get Main Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always. - - \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). - \return MSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) -{ -#if (((__ARM_ARCH_8M_MAIN__ < 1) && \ - (__ARM_ARCH_8_1M_MAIN__ < 1) ) && \ - (__ARM_FEATURE_CMSE < 3) ) - /* without main extensions, the non-secure MSPLIM is RAZ/WI */ - return (0U); -#else - uint32_t result; - __ASM volatile ("MRS %0, msplim" : "=r" (result) ); - return (result); -#endif -} - - -#if (__ARM_FEATURE_CMSE == 3) -/** - \brief Get Main Stack Pointer Limit (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always. - - \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. - \return MSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) -{ -#if ((__ARM_ARCH_8M_MAIN__ < 1) && \ - (__ARM_ARCH_8_1M_MAIN__ < 1) ) - /* without main extensions, the non-secure MSPLIM is RAZ/WI */ - return (0U); -#else - uint32_t result; - __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); - return (result); -#endif -} -#endif - - -/** - \brief Set Main Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored. - - \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). - \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set - */ -__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) -{ -#if (((__ARM_ARCH_8M_MAIN__ < 1) && \ - (__ARM_ARCH_8_1M_MAIN__ < 1) ) && \ - (__ARM_FEATURE_CMSE < 3) ) - /* without main extensions, the non-secure MSPLIM is RAZ/WI */ - (void)MainStackPtrLimit; -#else - __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); -#endif -} - - -#if (__ARM_FEATURE_CMSE == 3) -/** - \brief Set Main Stack Pointer Limit (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored. - - \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. - \param [in] MainStackPtrLimit Main Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) -{ -#if ((__ARM_ARCH_8M_MAIN__ < 1) && \ - (__ARM_ARCH_8_1M_MAIN__ < 1) ) - /* without main extensions, the non-secure MSPLIM is RAZ/WI */ - (void)MainStackPtrLimit; -#else - __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); -#endif -} -#endif -#endif /* (__ARM_ARCH >= 8) */ -/** @} end of CMSIS_Core_RegAccFunctions */ - - -/* ################### Compiler specific Intrinsics ########################### */ -/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics - Access to dedicated SIMD instructions - @{ -*/ - -#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) -#define __SADD8 __sadd8 -#define __QADD8 __qadd8 -#define __SHADD8 __shadd8 -#define __UADD8 __uadd8 -#define __UQADD8 __uqadd8 -#define __UHADD8 __uhadd8 -#define __SSUB8 __ssub8 -#define __QSUB8 __qsub8 -#define __SHSUB8 __shsub8 -#define __USUB8 __usub8 -#define __UQSUB8 __uqsub8 -#define __UHSUB8 __uhsub8 -#define __SADD16 __sadd16 -#define __QADD16 __qadd16 -#define __SHADD16 __shadd16 -#define __UADD16 __uadd16 -#define __UQADD16 __uqadd16 -#define __UHADD16 __uhadd16 -#define __SSUB16 __ssub16 -#define __QSUB16 __qsub16 -#define __SHSUB16 __shsub16 -#define __USUB16 __usub16 -#define __UQSUB16 __uqsub16 -#define __UHSUB16 __uhsub16 -#define __SASX __sasx -#define __QASX __qasx -#define __SHASX __shasx -#define __UASX __uasx -#define __UQASX __uqasx -#define __UHASX __uhasx -#define __SSAX __ssax -#define __QSAX __qsax -#define __SHSAX __shsax -#define __USAX __usax -#define __UQSAX __uqsax -#define __UHSAX __uhsax -#define __USAD8 __usad8 -#define __USADA8 __usada8 -#define __SSAT16 __ssat16 -#define __USAT16 __usat16 -#define __UXTB16 __uxtb16 -#define __UXTAB16 __uxtab16 -#define __SXTB16 __sxtb16 -#define __SXTAB16 __sxtab16 -#define __SMUAD __smuad -#define __SMUADX __smuadx -#define __SMLAD __smlad -#define __SMLADX __smladx -#define __SMLALD __smlald -#define __SMLALDX __smlaldx -#define __SMUSD __smusd -#define __SMUSDX __smusdx -#define __SMLSD __smlsd -#define __SMLSDX __smlsdx -#define __SMLSLD __smlsld -#define __SMLSLDX __smlsldx -#define __SEL __sel -#define __QADD __qadd -#define __QSUB __qsub - -#define __PKHBT(ARG1,ARG2,ARG3) \ -__extension__ \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - -#define __PKHTB(ARG1,ARG2,ARG3) \ -__extension__ \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - if (ARG3 == 0) \ - __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ - else \ - __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - -#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) - -#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) - -__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) -{ - int32_t result; - - __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); - return (result); -} -#endif /* (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) */ - /** @} end of group CMSIS_SIMD_intrinsics */ - - -#endif /* __CMSIS_ARMCLANG_M_H */ diff --git a/lib/main/pico-sdk/rp2_common/cmsis/stub/CMSIS/Core/Include/m-profile/cmsis_clang_m.h b/lib/main/pico-sdk/rp2_common/cmsis/stub/CMSIS/Core/Include/m-profile/cmsis_clang_m.h deleted file mode 100644 index a594442664..0000000000 --- a/lib/main/pico-sdk/rp2_common/cmsis/stub/CMSIS/Core/Include/m-profile/cmsis_clang_m.h +++ /dev/null @@ -1,824 +0,0 @@ -/* - * Copyright (c) 2009-2024 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* - * CMSIS-Core(M) Compiler LLVM/Clang Header File - */ - -#ifndef __CMSIS_CLANG_M_H -#define __CMSIS_CLANG_M_H - -#pragma clang system_header /* treat file as system include file */ - -#ifndef __CMSIS_CLANG_H - #error "This file must not be included directly" -#endif - -#if (__ARM_ACLE >= 200) - #include -#else - #error Compiler must support ACLE V2.0 -#endif /* (__ARM_ACLE >= 200) */ - -/* Fallback for __has_builtin */ -#ifndef __has_builtin - #define __has_builtin(x) (0) -#endif - - -/* ######################### Startup and Lowlevel Init ######################## */ -#ifndef __PROGRAM_START -#define __PROGRAM_START _start -#endif - -#ifndef __INITIAL_SP -#define __INITIAL_SP __stack -#endif - -#ifndef __STACK_LIMIT -#define __STACK_LIMIT __stack_limit -#endif - -#ifndef __VECTOR_TABLE -#define __VECTOR_TABLE __Vectors -#endif - -#ifndef __VECTOR_TABLE_ATTRIBUTE -#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section(".vectors"))) -#endif - -#if (__ARM_FEATURE_CMSE == 3) -#ifndef __STACK_SEAL -#define __STACK_SEAL __stack_seal -#endif - -#ifndef __TZ_STACK_SEAL_SIZE -#define __TZ_STACK_SEAL_SIZE 8U -#endif - -#ifndef __TZ_STACK_SEAL_VALUE -#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL -#endif - - -__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { - *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; - } -#endif - - -#if (__ARM_ARCH_ISA_THUMB >= 2) -/** - \brief STRT Unprivileged (8 bit) - \details Executes a Unprivileged STRT instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) -{ - __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (16 bit) - \details Executes a Unprivileged STRT instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) -{ - __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (32 bit) - \details Executes a Unprivileged STRT instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) -{ - __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); -} -#endif /* (__ARM_ARCH_ISA_THUMB >= 2) */ - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - - -/** - \brief Get Control Register - \details Returns the content of the Control Register. - \return Control Register value - */ -__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control" : "=r" (result) ); - return (result); -} - - -#if (__ARM_FEATURE_CMSE == 3) -/** - \brief Get Control Register (non-secure) - \details Returns the content of the non-secure Control Register when in secure mode. - \return non-secure Control Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); - return (result); -} -#endif - - -/** - \brief Set Control Register - \details Writes the given value to the Control Register. - \param [in] control Control Register value to set - */ -__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) -{ - __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); - __ISB(); -} - - -#if (__ARM_FEATURE_CMSE == 3) -/** - \brief Set Control Register (non-secure) - \details Writes the given value to the non-secure Control Register when in secure state. - \param [in] control Control Register value to set - */ -__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) -{ - __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); - __ISB(); -} -#endif - - -/** - \brief Get IPSR Register - \details Returns the content of the IPSR Register. - \return IPSR Register value - */ -__STATIC_FORCEINLINE uint32_t __get_IPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); - return (result); -} - - -/** - \brief Get APSR Register - \details Returns the content of the APSR Register. - \return APSR Register value - */ -__STATIC_FORCEINLINE uint32_t __get_APSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, apsr" : "=r" (result) ); - return (result); -} - - -/** - \brief Get xPSR Register - \details Returns the content of the xPSR Register. - \return xPSR Register value - */ -__STATIC_FORCEINLINE uint32_t __get_xPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); - return (result); -} - - -/** - \brief Get Process Stack Pointer - \details Returns the current value of the Process Stack Pointer (PSP). - \return PSP Register value - */ -__STATIC_FORCEINLINE uint32_t __get_PSP(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, psp" : "=r" (result) ); - return (result); -} - - -#if (__ARM_FEATURE_CMSE == 3) -/** - \brief Get Process Stack Pointer (non-secure) - \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. - \return PSP Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); - return (result); -} -#endif - - -/** - \brief Set Process Stack Pointer - \details Assigns the given value to the Process Stack Pointer (PSP). - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); -} - - -#if (__ARM_FEATURE_CMSE == 3) -/** - \brief Set Process Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); -} -#endif - - -/** - \brief Get Main Stack Pointer - \details Returns the current value of the Main Stack Pointer (MSP). - \return MSP Register value - */ -__STATIC_FORCEINLINE uint32_t __get_MSP(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, msp" : "=r" (result) ); - return (result); -} - - -#if (__ARM_FEATURE_CMSE == 3) -/** - \brief Get Main Stack Pointer (non-secure) - \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. - \return MSP Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); - return (result); -} -#endif - - -/** - \brief Set Main Stack Pointer - \details Assigns the given value to the Main Stack Pointer (MSP). - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); -} - - -#if (__ARM_FEATURE_CMSE == 3) -/** - \brief Set Main Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); -} -#endif - - -#if (__ARM_FEATURE_CMSE == 3) -/** - \brief Get Stack Pointer (non-secure) - \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. - \return SP Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); - return (result); -} - - -/** - \brief Set Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. - \param [in] topOfStack Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) -{ - __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); -} -#endif - - -/** - \brief Get Priority Mask - \details Returns the current state of the priority mask bit from the Priority Mask Register. - \return Priority Mask value - */ -__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask" : "=r" (result) ); - return (result); -} - - -#if (__ARM_FEATURE_CMSE == 3) -/** - \brief Get Priority Mask (non-secure) - \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. - \return Priority Mask value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); - return (result); -} -#endif - - -/** - \brief Set Priority Mask - \details Assigns the given value to the Priority Mask Register. - \param [in] priMask Priority Mask - */ -__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) -{ - __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); -} - - -#if (__ARM_FEATURE_CMSE == 3) -/** - \brief Set Priority Mask (non-secure) - \details Assigns the given value to the non-secure Priority Mask Register when in secure state. - \param [in] priMask Priority Mask - */ -__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) -{ - __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); -} -#endif - - -#if (__ARM_ARCH_ISA_THUMB >= 2) -/** - \brief Get Base Priority - \details Returns the current value of the Base Priority register. - \return Base Priority register value - */ -__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri" : "=r" (result) ); - return (result); -} - - -#if (__ARM_FEATURE_CMSE == 3) -/** - \brief Get Base Priority (non-secure) - \details Returns the current value of the non-secure Base Priority register when in secure state. - \return Base Priority register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); - return (result); -} -#endif - - -/** - \brief Set Base Priority - \details Assigns the given value to the Base Priority register. - \param [in] basePri Base Priority value to set - */ -__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) -{ - __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); -} - - -#if (__ARM_FEATURE_CMSE == 3) -/** - \brief Set Base Priority (non-secure) - \details Assigns the given value to the non-secure Base Priority register when in secure state. - \param [in] basePri Base Priority value to set - */ -__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) -{ - __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); -} -#endif - - -/** - \brief Set Base Priority with condition - \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, - or the new value increases the BASEPRI priority level. - \param [in] basePri Base Priority value to set - */ -__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) -{ - __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); -} - - -/** - \brief Get Fault Mask - \details Returns the current value of the Fault Mask register. - \return Fault Mask register value - */ -__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); - return (result); -} - - -#if (__ARM_FEATURE_CMSE == 3) -/** - \brief Get Fault Mask (non-secure) - \details Returns the current value of the non-secure Fault Mask register when in secure state. - \return Fault Mask register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); - return (result); -} -#endif - - -/** - \brief Set Fault Mask - \details Assigns the given value to the Fault Mask register. - \param [in] faultMask Fault Mask value to set - */ -__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); -} - - -#if (__ARM_FEATURE_CMSE == 3) -/** - \brief Set Fault Mask (non-secure) - \details Assigns the given value to the non-secure Fault Mask register when in secure state. - \param [in] faultMask Fault Mask value to set - */ -__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); -} -#endif - -#endif /* (__ARM_ARCH_ISA_THUMB >= 2) */ - - -#if (__ARM_ARCH >= 8) -/** - \brief Get Process Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always in non-secure - mode. - - \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). - \return PSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) -{ -#if (((__ARM_ARCH_8M_MAIN__ < 1) && \ - (__ARM_ARCH_8_1M_MAIN__ < 1) ) && \ - (__ARM_FEATURE_CMSE < 3) ) - /* without main extensions, the non-secure PSPLIM is RAZ/WI */ - return (0U); -#else - uint32_t result; - __ASM volatile ("MRS %0, psplim" : "=r" (result) ); - return (result); -#endif -} - -#if (__ARM_FEATURE_CMSE == 3) -/** - \brief Get Process Stack Pointer Limit (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always. - - \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. - \return PSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) -{ -#if ((__ARM_ARCH_8M_MAIN__ < 1) && \ - (__ARM_ARCH_8_1M_MAIN__ < 1) ) - /* without main extensions, the non-secure PSPLIM is RAZ/WI */ - return (0U); -#else - uint32_t result; - __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); - return (result); -#endif -} -#endif - - -/** - \brief Set Process Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored in non-secure - mode. - - \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). - \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set - */ -__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) -{ -#if (((__ARM_ARCH_8M_MAIN__ < 1) && \ - (__ARM_ARCH_8_1M_MAIN__ < 1) ) && \ - (__ARM_FEATURE_CMSE < 3) ) - /* without main extensions, the non-secure PSPLIM is RAZ/WI */ - (void)ProcStackPtrLimit; -#else - __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); -#endif -} - - -#if (__ARM_FEATURE_CMSE == 3) -/** - \brief Set Process Stack Pointer (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored. - - \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. - \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set - */ -__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) -{ -#if ((__ARM_ARCH_8M_MAIN__ < 1) && \ - (__ARM_ARCH_8_1M_MAIN__ < 1) ) - /* without main extensions, the non-secure PSPLIM is RAZ/WI */ - (void)ProcStackPtrLimit; -#else - __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); -#endif -} -#endif - - -/** - \brief Get Main Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always. - - \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). - \return MSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) -{ -#if (((__ARM_ARCH_8M_MAIN__ < 1) && \ - (__ARM_ARCH_8_1M_MAIN__ < 1) ) && \ - (__ARM_FEATURE_CMSE < 3) ) - /* without main extensions, the non-secure MSPLIM is RAZ/WI */ - return (0U); -#else - uint32_t result; - __ASM volatile ("MRS %0, msplim" : "=r" (result) ); - return (result); -#endif -} - - -#if (__ARM_FEATURE_CMSE == 3) -/** - \brief Get Main Stack Pointer Limit (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always. - - \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. - \return MSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) -{ -#if ((__ARM_ARCH_8M_MAIN__ < 1) && \ - (__ARM_ARCH_8_1M_MAIN__ < 1) ) - /* without main extensions, the non-secure MSPLIM is RAZ/WI */ - return (0U); -#else - uint32_t result; - __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); - return (result); -#endif -} -#endif - - -/** - \brief Set Main Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored. - - \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). - \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set - */ -__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) -{ -#if (((__ARM_ARCH_8M_MAIN__ < 1) && \ - (__ARM_ARCH_8_1M_MAIN__ < 1) ) && \ - (__ARM_FEATURE_CMSE < 3) ) - /* without main extensions, the non-secure MSPLIM is RAZ/WI */ - (void)MainStackPtrLimit; -#else - __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); -#endif -} - - -#if (__ARM_FEATURE_CMSE == 3) -/** - \brief Set Main Stack Pointer Limit (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored. - - \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. - \param [in] MainStackPtrLimit Main Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) -{ -#if ((__ARM_ARCH_8M_MAIN__ < 1) && \ - (__ARM_ARCH_8_1M_MAIN__ < 1) ) - /* without main extensions, the non-secure MSPLIM is RAZ/WI */ - (void)MainStackPtrLimit; -#else - __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); -#endif -} -#endif - -#endif /* (__ARM_ARCH >= 8) */ - -/* ################### Compiler specific Intrinsics ########################### */ -/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics - Access to dedicated SIMD instructions - @{ -*/ -#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) -#define __SADD8 __sadd8 -#define __QADD8 __qadd8 -#define __SHADD8 __shadd8 -#define __UADD8 __uadd8 -#define __UQADD8 __uqadd8 -#define __UHADD8 __uhadd8 -#define __SSUB8 __ssub8 -#define __QSUB8 __qsub8 -#define __SHSUB8 __shsub8 -#define __USUB8 __usub8 -#define __UQSUB8 __uqsub8 -#define __UHSUB8 __uhsub8 -#define __SADD16 __sadd16 -#define __QADD16 __qadd16 -#define __SHADD16 __shadd16 -#define __UADD16 __uadd16 -#define __UQADD16 __uqadd16 -#define __UHADD16 __uhadd16 -#define __SSUB16 __ssub16 -#define __QSUB16 __qsub16 -#define __SHSUB16 __shsub16 -#define __USUB16 __usub16 -#define __UQSUB16 __uqsub16 -#define __UHSUB16 __uhsub16 -#define __SASX __sasx -#define __QASX __qasx -#define __SHASX __shasx -#define __UASX __uasx -#define __UQASX __uqasx -#define __UHASX __uhasx -#define __SSAX __ssax -#define __QSAX __qsax -#define __SHSAX __shsax -#define __USAX __usax -#define __UQSAX __uqsax -#define __UHSAX __uhsax -#define __USAD8 __usad8 -#define __USADA8 __usada8 -#define __SSAT16 __ssat16 -#define __USAT16 __usat16 -#define __UXTB16 __uxtb16 -#define __UXTAB16 __uxtab16 -#define __SXTB16 __sxtb16 -#define __SXTAB16 __sxtab16 -#define __SMUAD __smuad -#define __SMUADX __smuadx -#define __SMLAD __smlad -#define __SMLADX __smladx -#define __SMLALD __smlald -#define __SMLALDX __smlaldx -#define __SMUSD __smusd -#define __SMUSDX __smusdx -#define __SMLSD __smlsd -#define __SMLSDX __smlsdx -#define __SMLSLD __smlsld -#define __SMLSLDX __smlsldx -#define __SEL __sel -#define __QADD __qadd -#define __QSUB __qsub - -#define __PKHBT(ARG1,ARG2,ARG3) \ -__extension__ \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - -#define __PKHTB(ARG1,ARG2,ARG3) \ -__extension__ \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - if (ARG3 == 0) \ - __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ - else \ - __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - -#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) - -#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) - -__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) -{ - int32_t result; - - __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); - return (result); -} - -#endif /* (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) */ - /** @} end of group CMSIS_SIMD_intrinsics */ -/** @} end of CMSIS_Core_RegAccFunctions */ - - -#endif /* __CMSIS_CLANG_M_H */ diff --git a/lib/main/pico-sdk/rp2_common/cmsis/stub/CMSIS/Core/Include/m-profile/cmsis_gcc_m.h b/lib/main/pico-sdk/rp2_common/cmsis/stub/CMSIS/Core/Include/m-profile/cmsis_gcc_m.h deleted file mode 100644 index 54d1f54957..0000000000 --- a/lib/main/pico-sdk/rp2_common/cmsis/stub/CMSIS/Core/Include/m-profile/cmsis_gcc_m.h +++ /dev/null @@ -1,717 +0,0 @@ -/* - * Copyright (c) 2009-2023 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* - * CMSIS-Core(M) Compiler GCC Header File - */ - -#ifndef __CMSIS_GCC_M_H -#define __CMSIS_GCC_M_H - -#ifndef __CMSIS_GCC_H - #error "This file must not be included directly" -#endif - -#include - -/* ######################### Startup and Lowlevel Init ######################## */ -#ifndef __PROGRAM_START - -/** - \brief Initializes data and bss sections - \details This default implementations initialized all data and additional bss - sections relying on .copy.table and .zero.table specified properly - in the used linker script. - - */ -__STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void) -{ - extern void _start(void) __NO_RETURN; - - typedef struct __copy_table { - uint32_t const* src; - uint32_t* dest; - uint32_t wlen; - } __copy_table_t; - - typedef struct __zero_table { - uint32_t* dest; - uint32_t wlen; - } __zero_table_t; - - extern const __copy_table_t __copy_table_start__; - extern const __copy_table_t __copy_table_end__; - extern const __zero_table_t __zero_table_start__; - extern const __zero_table_t __zero_table_end__; - - for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) { - for(uint32_t i=0u; iwlen; ++i) { - pTable->dest[i] = pTable->src[i]; - } - } - - for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) { - for(uint32_t i=0u; iwlen; ++i) { - pTable->dest[i] = 0u; - } - } - - _start(); -} - -#define __PROGRAM_START __cmsis_start -#endif - -#ifndef __INITIAL_SP -#define __INITIAL_SP __StackTop -#endif - -#ifndef __STACK_LIMIT -#define __STACK_LIMIT __StackLimit -#endif - -#ifndef __VECTOR_TABLE -#define __VECTOR_TABLE __Vectors -#endif - -#ifndef __VECTOR_TABLE_ATTRIBUTE -#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section(".vectors"))) -#endif - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) -#ifndef __STACK_SEAL -#define __STACK_SEAL __StackSeal -#endif - -#ifndef __TZ_STACK_SEAL_SIZE -#define __TZ_STACK_SEAL_SIZE 8U -#endif - -#ifndef __TZ_STACK_SEAL_VALUE -#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL -#endif - - -__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { - *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; -} -#endif - - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -/** - \brief Get Control Register - \details Returns the content of the Control Register. - \return Control Register value - */ -__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control" : "=r" (result) ); - return (result); -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) -/** - \brief Get Control Register (non-secure) - \details Returns the content of the non-secure Control Register when in secure mode. - \return non-secure Control Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); - return (result); -} -#endif - - -/** - \brief Set Control Register - \details Writes the given value to the Control Register. - \param [in] control Control Register value to set - */ -__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) -{ - __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); - __ISB(); -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) -/** - \brief Set Control Register (non-secure) - \details Writes the given value to the non-secure Control Register when in secure state. - \param [in] control Control Register value to set - */ -__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) -{ - __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); - __ISB(); -} -#endif - - -/** - \brief Get IPSR Register - \details Returns the content of the IPSR Register. - \return IPSR Register value - */ -__STATIC_FORCEINLINE uint32_t __get_IPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); - return (result); -} - - -/** - \brief Get APSR Register - \details Returns the content of the APSR Register. - \return APSR Register value - */ -__STATIC_FORCEINLINE uint32_t __get_APSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, apsr" : "=r" (result) ); - return (result); -} - - -/** - \brief Get xPSR Register - \details Returns the content of the xPSR Register. - \return xPSR Register value - */ -__STATIC_FORCEINLINE uint32_t __get_xPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); - return (result); -} - - -/** - \brief Get Process Stack Pointer - \details Returns the current value of the Process Stack Pointer (PSP). - \return PSP Register value - */ -__STATIC_FORCEINLINE uint32_t __get_PSP(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, psp" : "=r" (result) ); - return (result); -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) -/** - \brief Get Process Stack Pointer (non-secure) - \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. - \return PSP Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); - return (result); -} -#endif - - -/** - \brief Set Process Stack Pointer - \details Assigns the given value to the Process Stack Pointer (PSP). - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) -/** - \brief Set Process Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); -} -#endif - - -/** - \brief Get Main Stack Pointer - \details Returns the current value of the Main Stack Pointer (MSP). - \return MSP Register value - */ -__STATIC_FORCEINLINE uint32_t __get_MSP(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, msp" : "=r" (result) ); - return (result); -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) -/** - \brief Get Main Stack Pointer (non-secure) - \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. - \return MSP Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); - return (result); -} -#endif - - -/** - \brief Set Main Stack Pointer - \details Assigns the given value to the Main Stack Pointer (MSP). - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) -/** - \brief Set Main Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); -} -#endif - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) -/** - \brief Get Stack Pointer (non-secure) - \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. - \return SP Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); - return (result); -} - - -/** - \brief Set Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. - \param [in] topOfStack Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) -{ - __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); -} -#endif - - -/** - \brief Get Priority Mask - \details Returns the current state of the priority mask bit from the Priority Mask Register. - \return Priority Mask value - */ -__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask" : "=r" (result) ); - return (result); -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) -/** - \brief Get Priority Mask (non-secure) - \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. - \return Priority Mask value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); - return (result); -} -#endif - - -/** - \brief Set Priority Mask - \details Assigns the given value to the Priority Mask Register. - \param [in] priMask Priority Mask - */ -__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) -{ - __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) -/** - \brief Set Priority Mask (non-secure) - \details Assigns the given value to the non-secure Priority Mask Register when in secure state. - \param [in] priMask Priority Mask - */ -__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) -{ - __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); -} -#endif - - -#if (__ARM_ARCH_ISA_THUMB >= 2) -/** - \brief Get Base Priority - \details Returns the current value of the Base Priority register. - \return Base Priority register value - */ -__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri" : "=r" (result) ); - return (result); -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) -/** - \brief Get Base Priority (non-secure) - \details Returns the current value of the non-secure Base Priority register when in secure state. - \return Base Priority register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); - return (result); -} -#endif - - -/** - \brief Set Base Priority - \details Assigns the given value to the Base Priority register. - \param [in] basePri Base Priority value to set - */ -__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) -{ - __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) -/** - \brief Set Base Priority (non-secure) - \details Assigns the given value to the non-secure Base Priority register when in secure state. - \param [in] basePri Base Priority value to set - */ -__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) -{ - __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); -} -#endif - - -/** - \brief Set Base Priority with condition - \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, - or the new value increases the BASEPRI priority level. - \param [in] basePri Base Priority value to set - */ -__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) -{ - __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); -} - - -/** - \brief Get Fault Mask - \details Returns the current value of the Fault Mask register. - \return Fault Mask register value - */ -__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); - return (result); -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) -/** - \brief Get Fault Mask (non-secure) - \details Returns the current value of the non-secure Fault Mask register when in secure state. - \return Fault Mask register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); - return (result); -} -#endif - - -/** - \brief Set Fault Mask - \details Assigns the given value to the Fault Mask register. - \param [in] faultMask Fault Mask value to set - */ -__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) -/** - \brief Set Fault Mask (non-secure) - \details Assigns the given value to the non-secure Fault Mask register when in secure state. - \param [in] faultMask Fault Mask value to set - */ -__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); -} -#endif - -#endif /* (__ARM_ARCH_ISA_THUMB >= 2) */ - - -#if (__ARM_ARCH >= 8) -/** - \brief Get Process Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always in non-secure - mode. - - \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). - \return PSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) - /* without main extensions, the non-secure PSPLIM is RAZ/WI */ - return (0U); -#else - uint32_t result; - __ASM volatile ("MRS %0, psplim" : "=r" (result) ); - return (result); -#endif -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) -/** - \brief Get Process Stack Pointer Limit (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always. - - \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. - \return PSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1))) - /* without main extensions, the non-secure PSPLIM is RAZ/WI */ - return (0U); -#else - uint32_t result; - __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); - return (result); -#endif -} -#endif - - -/** - \brief Set Process Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored in non-secure - mode. - - \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). - \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set - */ -__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) - /* without main extensions, the non-secure PSPLIM is RAZ/WI */ - (void)ProcStackPtrLimit; -#else - __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); -#endif -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) -/** - \brief Set Process Stack Pointer (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored. - - \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. - \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set - */ -__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1))) - /* without main extensions, the non-secure PSPLIM is RAZ/WI */ - (void)ProcStackPtrLimit; -#else - __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); -#endif -} -#endif - - -/** - \brief Get Main Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always. - - \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). - \return MSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) - /* without main extensions, the non-secure MSPLIM is RAZ/WI */ - return (0U); -#else - uint32_t result; - __ASM volatile ("MRS %0, msplim" : "=r" (result) ); - return (result); -#endif -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) -/** - \brief Get Main Stack Pointer Limit (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always. - - \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. - \return MSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1))) - /* without main extensions, the non-secure MSPLIM is RAZ/WI */ - return (0U); -#else - uint32_t result; - __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); - return (result); -#endif -} -#endif - - -/** - \brief Set Main Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored. - - \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). - \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set - */ -__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) - /* without main extensions, the non-secure MSPLIM is RAZ/WI */ - (void)MainStackPtrLimit; -#else - __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); -#endif -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) -/** - \brief Set Main Stack Pointer Limit (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored. - - \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. - \param [in] MainStackPtrLimit Main Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1))) - /* without main extensions, the non-secure MSPLIM is RAZ/WI */ - (void)MainStackPtrLimit; -#else - __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); -#endif -} -#endif - -#endif /* (__ARM_ARCH >= 8) */ - -/*@} end of CMSIS_Core_RegAccFunctions */ - -#endif /* __CMSIS_GCC_M_H */ diff --git a/lib/main/pico-sdk/rp2_common/cmsis/stub/CMSIS/Core/Include/m-profile/cmsis_iccarm_m.h b/lib/main/pico-sdk/rp2_common/cmsis/stub/CMSIS/Core/Include/m-profile/cmsis_iccarm_m.h deleted file mode 100644 index cfc6f80836..0000000000 --- a/lib/main/pico-sdk/rp2_common/cmsis/stub/CMSIS/Core/Include/m-profile/cmsis_iccarm_m.h +++ /dev/null @@ -1,1043 +0,0 @@ -/* - * Copyright (c) 2017-2021 IAR Systems - * Copyright (c) 2017-2024 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* - * CMSIS-Core(M) Compiler ICCARM (IAR Compiler for Arm) Header File - */ - -#ifndef __CMSIS_ICCARM_M_H__ -#define __CMSIS_ICCARM_M_H__ - -#ifndef __ICCARM__ - #error This file should only be compiled by ICCARM -#endif - -#pragma system_include - -#define __IAR_FT _Pragma("inline=forced") __intrinsic - -#if (__VER__ >= 8000000) - #define __ICCARM_V8 1 -#else - #define __ICCARM_V8 0 -#endif - -#ifndef __ALIGNED - #if __ICCARM_V8 - #define __ALIGNED(x) __attribute__((aligned(x))) - #elif (__VER__ >= 7080000) - /* Needs IAR language extensions */ - #define __ALIGNED(x) __attribute__((aligned(x))) - #else - #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. - #define __ALIGNED(x) - #endif -#endif - - -/* Define compiler macros for CPU architecture, used in CMSIS 5. - */ -#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__ || __ARM_ARCH_8_1M_MAIN__ -/* Macros already defined */ -#else - #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__) - #define __ARM_ARCH_8M_MAIN__ 1 - #elif defined(__ARM8M_BASELINE__) - #define __ARM_ARCH_8M_BASE__ 1 - #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' - #if __ARM_ARCH == 6 - #define __ARM_ARCH_6M__ 1 - #elif __ARM_ARCH == 7 - #if __ARM_FEATURE_DSP - #define __ARM_ARCH_7EM__ 1 - #else - #define __ARM_ARCH_7M__ 1 - #endif - #elif __ARM_ARCH == 801 - #define __ARM_ARCH_8_1M_MAIN__ 1 - #endif /* __ARM_ARCH */ - #endif /* __ARM_ARCH_PROFILE == 'M' */ -#endif - -/* Alternativ core deduction for older ICCARM's */ -#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \ - !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__) && !defined(__ARM_ARCH_8_1M_MAIN__) - #if defined(__ARM6M__) && (__CORE__ == __ARM6M__) - #define __ARM_ARCH_6M__ 1 - #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__) - #define __ARM_ARCH_7M__ 1 - #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__) - #define __ARM_ARCH_7EM__ 1 - #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__) - #define __ARM_ARCH_8M_BASE__ 1 - #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__) - #define __ARM_ARCH_8M_MAIN__ 1 - #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__) - #define __ARM_ARCH_8M_MAIN__ 1 - #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' && __ARM_ARCH == 801 - #define __ARM_ARCH_8_1M_MAIN__ 1 - #else - #error "Unknown target." - #endif -#endif - - - -#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1 - #define __IAR_M0_FAMILY 1 -#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1 - #define __IAR_M0_FAMILY 1 -#else - #define __IAR_M0_FAMILY 0 -#endif - -#ifndef __NO_INIT - #define __NO_INIT __attribute__ ((section (".noinit"))) -#endif -#ifndef __ALIAS - #define __ALIAS(x) __attribute__ ((alias(x))) -#endif - -#ifndef __ASM - #define __ASM __asm -#endif - -#ifndef __COMPILER_BARRIER - #define __COMPILER_BARRIER() __ASM volatile("":::"memory") -#endif - -#ifndef __INLINE - #define __INLINE inline -#endif - -#ifndef __NO_RETURN - #if defined(__cplusplus) && __cplusplus >= 201103L - #define __NO_RETURN [[noreturn]] - #elif defined(__STDC_VERSION__) && __STDC_VERSION__ >= 201112L - #define __NO_RETURN _Noreturn - #else - #define __NO_RETURN _Pragma("object_attribute=__noreturn") - #endif -#endif - -#ifndef __PACKED - #if __ICCARM_V8 - #define __PACKED __attribute__((packed, aligned(1))) - #else - /* Needs IAR language extensions */ - #define __PACKED __packed - #endif -#endif - -#ifndef __PACKED_STRUCT - #if __ICCARM_V8 - #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) - #else - /* Needs IAR language extensions */ - #define __PACKED_STRUCT __packed struct - #endif -#endif - -#ifndef __PACKED_UNION - #if __ICCARM_V8 - #define __PACKED_UNION union __attribute__((packed, aligned(1))) - #else - /* Needs IAR language extensions */ - #define __PACKED_UNION __packed union - #endif -#endif - -#ifndef __RESTRICT - #if __ICCARM_V8 - #define __RESTRICT __restrict - #else - /* Needs IAR language extensions */ - #define __RESTRICT restrict - #endif -#endif - -#ifndef __STATIC_INLINE - #define __STATIC_INLINE static inline -#endif - -#ifndef __FORCEINLINE - #define __FORCEINLINE _Pragma("inline=forced") -#endif - -#ifndef __STATIC_FORCEINLINE - #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE -#endif - -#ifndef __UNALIGNED_UINT16_READ -#pragma language=save -#pragma language=extended -__IAR_FT uint16_t __iar_uint16_read(void const *ptr) -{ - return *(__packed uint16_t*)(ptr); -} -#pragma language=restore -#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) -#endif - - -#ifndef __UNALIGNED_UINT16_WRITE -#pragma language=save -#pragma language=extended -__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) -{ - *(__packed uint16_t*)(ptr) = val;; -} -#pragma language=restore -#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) -#endif - -#ifndef __UNALIGNED_UINT32_READ -#pragma language=save -#pragma language=extended -__IAR_FT uint32_t __iar_uint32_read(void const *ptr) -{ - return *(__packed uint32_t*)(ptr); -} -#pragma language=restore -#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) -#endif - -#ifndef __UNALIGNED_UINT32_WRITE -#pragma language=save -#pragma language=extended -__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) -{ - *(__packed uint32_t*)(ptr) = val;; -} -#pragma language=restore -#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) -#endif - -#ifndef __UNALIGNED_UINT32 /* deprecated */ -#pragma language=save -#pragma language=extended -__packed struct __iar_u32 { uint32_t v; }; -#pragma language=restore -#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) -#endif - -#ifndef __USED - #if __ICCARM_V8 - #define __USED __attribute__((used)) - #else - #define __USED _Pragma("__root") - #endif -#endif - -#undef __WEAK /* undo the definition from DLib_Defaults.h */ -#ifndef __WEAK - #if __ICCARM_V8 - #define __WEAK __attribute__((weak)) - #else - #define __WEAK _Pragma("__weak") - #endif -#endif - -#ifndef __PROGRAM_START -#define __PROGRAM_START __iar_program_start -#endif - -#ifndef __INITIAL_SP -#define __INITIAL_SP CSTACK$$Limit -#endif - -#ifndef __STACK_LIMIT -#define __STACK_LIMIT CSTACK$$Base -#endif - -#ifndef __VECTOR_TABLE -#define __VECTOR_TABLE __vector_table -#endif - -#ifndef __VECTOR_TABLE_ATTRIBUTE -#define __VECTOR_TABLE_ATTRIBUTE @".intvec" -#endif - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#ifndef __STACK_SEAL -#define __STACK_SEAL STACKSEAL$$Base -#endif - -#ifndef __TZ_STACK_SEAL_SIZE -#define __TZ_STACK_SEAL_SIZE 8U -#endif - -#ifndef __TZ_STACK_SEAL_VALUE -#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL -#endif - -__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { - *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; -} -#endif - -#ifndef __ICCARM_INTRINSICS_VERSION__ - #define __ICCARM_INTRINSICS_VERSION__ 0 -#endif - -#if __ICCARM_INTRINSICS_VERSION__ == 2 - - #if defined(__CLZ) - #undef __CLZ - #endif - #if defined(__REVSH) - #undef __REVSH - #endif - #if defined(__RBIT) - #undef __RBIT - #endif - #if defined(__SSAT) - #undef __SSAT - #endif - #if defined(__USAT) - #undef __USAT - #endif - - #include "iccarm_builtin.h" - - #define __disable_irq __iar_builtin_disable_interrupt - #define __enable_irq __iar_builtin_enable_interrupt - #define __arm_rsr __iar_builtin_rsr - #define __arm_wsr __iar_builtin_wsr - - - #if (defined(__ARM_ARCH_ISA_THUMB) && __ARM_ARCH_ISA_THUMB >= 2) - __IAR_FT void __disable_fault_irq() - { - __ASM volatile ("CPSID F" ::: "memory"); - } - - __IAR_FT void __enable_fault_irq() - { - __ASM volatile ("CPSIE F" ::: "memory"); - } - #endif - - - #define __get_APSR() (__arm_rsr("APSR")) - #define __get_BASEPRI() (__arm_rsr("BASEPRI")) - #define __get_CONTROL() (__arm_rsr("CONTROL")) - #define __get_FAULTMASK() (__arm_rsr("FAULTMASK")) - - #if (defined (__ARM_FP) && (__ARM_FP >= 1)) - #define __get_FPSCR() (__arm_rsr("FPSCR")) - #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE))) - #else - #define __get_FPSCR() ( 0 ) - #define __set_FPSCR(VALUE) ((void)VALUE) - #endif - - #define __get_IPSR() (__arm_rsr("IPSR")) - #define __get_MSP() (__arm_rsr("MSP")) - #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - #define __get_MSPLIM() (0U) - #else - #define __get_MSPLIM() (__arm_rsr("MSPLIM")) - #endif - #define __get_PRIMASK() (__arm_rsr("PRIMASK")) - #define __get_PSP() (__arm_rsr("PSP")) - - #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - #define __get_PSPLIM() (0U) - #else - #define __get_PSPLIM() (__arm_rsr("PSPLIM")) - #endif - - #define __get_xPSR() (__arm_rsr("xPSR")) - - #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE))) - #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE))) - -__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) -{ - __arm_wsr("CONTROL", control); - __iar_builtin_ISB(); -} - - #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE))) - #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE))) - - #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - #define __set_MSPLIM(VALUE) ((void)(VALUE)) - #else - #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE))) - #endif - #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE))) - #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE))) - #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - #define __set_PSPLIM(VALUE) ((void)(VALUE)) - #else - #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE))) - #endif - - #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS")) - -__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) -{ - __arm_wsr("CONTROL_NS", control); - __iar_builtin_ISB(); -} - - #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS")) - #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE))) - #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS")) - #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE))) - #define __TZ_get_SP_NS() (__arm_rsr("SP_NS")) - #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE))) - #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS")) - #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE))) - #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS")) - #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE))) - #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS")) - #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE))) - - #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - #define __TZ_get_PSPLIM_NS() (0U) - #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE)) - #else - #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS")) - #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE))) - #endif - - #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS")) - #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE))) - - #define __NOP __iar_builtin_no_operation - - #define __CLZ __iar_builtin_CLZ - - /* - * __iar_builtin_CLREX can be reordered w.r.t. STREX during high optimizations. - * As a workaround we use inline assembly and a memory barrier. - * (IAR issue EWARM-11901) - */ - #define __CLREX() (__ASM volatile ("CLREX" ::: "memory")) - - #define __DMB __iar_builtin_DMB - #define __DSB __iar_builtin_DSB - #define __ISB __iar_builtin_ISB - - #define __LDREXB __iar_builtin_LDREXB - #define __LDREXH __iar_builtin_LDREXH - #define __LDREXW __iar_builtin_LDREX - - #define __RBIT __iar_builtin_RBIT - #define __REV __iar_builtin_REV - #define __REV16 __iar_builtin_REV16 - - __IAR_FT int16_t __REVSH(int16_t val) - { - return (int16_t) __iar_builtin_REVSH(val); - } - - #define __ROR __iar_builtin_ROR - #define __RRX __iar_builtin_RRX - - #define __SEV __iar_builtin_SEV - - #if !__IAR_M0_FAMILY - #define __SSAT __iar_builtin_SSAT - #endif - - #define __STREXB __iar_builtin_STREXB - #define __STREXH __iar_builtin_STREXH - #define __STREXW __iar_builtin_STREX - - #if !__IAR_M0_FAMILY - #define __USAT __iar_builtin_USAT - #endif - - #define __WFE __iar_builtin_WFE - #define __WFI __iar_builtin_WFI - - #if __ARM_MEDIA__ - #define __SADD8 __iar_builtin_SADD8 - #define __QADD8 __iar_builtin_QADD8 - #define __SHADD8 __iar_builtin_SHADD8 - #define __UADD8 __iar_builtin_UADD8 - #define __UQADD8 __iar_builtin_UQADD8 - #define __UHADD8 __iar_builtin_UHADD8 - #define __SSUB8 __iar_builtin_SSUB8 - #define __QSUB8 __iar_builtin_QSUB8 - #define __SHSUB8 __iar_builtin_SHSUB8 - #define __USUB8 __iar_builtin_USUB8 - #define __UQSUB8 __iar_builtin_UQSUB8 - #define __UHSUB8 __iar_builtin_UHSUB8 - #define __SADD16 __iar_builtin_SADD16 - #define __QADD16 __iar_builtin_QADD16 - #define __SHADD16 __iar_builtin_SHADD16 - #define __UADD16 __iar_builtin_UADD16 - #define __UQADD16 __iar_builtin_UQADD16 - #define __UHADD16 __iar_builtin_UHADD16 - #define __SSUB16 __iar_builtin_SSUB16 - #define __QSUB16 __iar_builtin_QSUB16 - #define __SHSUB16 __iar_builtin_SHSUB16 - #define __USUB16 __iar_builtin_USUB16 - #define __UQSUB16 __iar_builtin_UQSUB16 - #define __UHSUB16 __iar_builtin_UHSUB16 - #define __SASX __iar_builtin_SASX - #define __QASX __iar_builtin_QASX - #define __SHASX __iar_builtin_SHASX - #define __UASX __iar_builtin_UASX - #define __UQASX __iar_builtin_UQASX - #define __UHASX __iar_builtin_UHASX - #define __SSAX __iar_builtin_SSAX - #define __QSAX __iar_builtin_QSAX - #define __SHSAX __iar_builtin_SHSAX - #define __USAX __iar_builtin_USAX - #define __UQSAX __iar_builtin_UQSAX - #define __UHSAX __iar_builtin_UHSAX - #define __USAD8 __iar_builtin_USAD8 - #define __USADA8 __iar_builtin_USADA8 - #define __SSAT16 __iar_builtin_SSAT16 - #define __USAT16 __iar_builtin_USAT16 - #define __UXTB16 __iar_builtin_UXTB16 - #define __UXTAB16 __iar_builtin_UXTAB16 - #define __SXTB16 __iar_builtin_SXTB16 - #define __SXTAB16 __iar_builtin_SXTAB16 - #define __SMUAD __iar_builtin_SMUAD - #define __SMUADX __iar_builtin_SMUADX - #define __SMMLA __iar_builtin_SMMLA - #define __SMLAD __iar_builtin_SMLAD - #define __SMLADX __iar_builtin_SMLADX - #define __SMLALD __iar_builtin_SMLALD - #define __SMLALDX __iar_builtin_SMLALDX - #define __SMUSD __iar_builtin_SMUSD - #define __SMUSDX __iar_builtin_SMUSDX - #define __SMLSD __iar_builtin_SMLSD - #define __SMLSDX __iar_builtin_SMLSDX - #define __SMLSLD __iar_builtin_SMLSLD - #define __SMLSLDX __iar_builtin_SMLSLDX - #define __SEL __iar_builtin_SEL - #define __QADD __iar_builtin_QADD - #define __QSUB __iar_builtin_QSUB - #define __PKHBT __iar_builtin_PKHBT - #define __PKHTB __iar_builtin_PKHTB - #endif - -#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ - - #if __IAR_M0_FAMILY - /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ - #define __CLZ __cmsis_iar_clz_not_active - #define __SSAT __cmsis_iar_ssat_not_active - #define __USAT __cmsis_iar_usat_not_active - #define __RBIT __cmsis_iar_rbit_not_active - #define __get_APSR __cmsis_iar_get_APSR_not_active - #endif - - - #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) - #define __get_FPSCR __cmsis_iar_get_FPSR_not_active - #define __set_FPSCR __cmsis_iar_set_FPSR_not_active - #endif - - #ifdef __INTRINSICS_INCLUDED - #error intrinsics.h is already included previously! - #endif - - #include - - #if __IAR_M0_FAMILY - /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ - #undef __CLZ - #undef __SSAT - #undef __USAT - #undef __RBIT - #undef __get_APSR - - __STATIC_INLINE uint8_t __CLZ(uint32_t data) - { - if (data == 0U) { return 32U; } - - uint32_t count = 0U; - uint32_t mask = 0x80000000U; - - while ((data & mask) == 0U) - { - count += 1U; - mask = mask >> 1U; - } - return count; - } - - __STATIC_INLINE uint32_t __RBIT(uint32_t v) - { - uint8_t sc = 31U; - uint32_t r = v; - for (v >>= 1U; v; v >>= 1U) - { - r <<= 1U; - r |= v & 1U; - sc--; - } - return (r << sc); - } - - __STATIC_INLINE uint32_t __get_APSR(void) - { - uint32_t res; - __asm("MRS %0,APSR" : "=r" (res)); - return res; - } - - #endif - - #if (!(defined (__ARM_FP) && (__ARM_FP >= 1))) - #undef __get_FPSCR - #undef __set_FPSCR - #define __get_FPSCR() (0) - #define __set_FPSCR(VALUE) ((void)VALUE) - #endif - - #pragma diag_suppress=Pe940 - #pragma diag_suppress=Pe177 - - #define __enable_irq __enable_interrupt - #define __disable_irq __disable_interrupt - #define __NOP __no_operation - - #define __get_xPSR __get_PSR - - #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0) - - __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) - { - return __LDREX((unsigned long *)ptr); - } - - __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) - { - return __STREX(value, (unsigned long *)ptr); - } - #endif - - - /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ - #if (__CORTEX_M >= 0x03) - - __IAR_FT uint32_t __RRX(uint32_t value) - { - uint32_t result; - __ASM volatile("RRX %0, %1" : "=r"(result) : "r" (value)); - return(result); - } - - __IAR_FT void __set_BASEPRI_MAX(uint32_t value) - { - __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value)); - } - - __IAR_FT void __disable_fault_irq() - { - __ASM volatile ("CPSID F" ::: "memory"); - } - - __IAR_FT void __enable_fault_irq() - { - __ASM volatile ("CPSIE F" ::: "memory"); - } - - - #endif /* (__CORTEX_M >= 0x03) */ - - __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) - { - return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); - } - - #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) - - __IAR_FT uint32_t __get_MSPLIM(void) - { - uint32_t res; - #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) - // without main extension and secure, there is no stack limit check. - res = 0U; - #else - __asm volatile("MRS %0,MSPLIM" : "=r" (res)); - #endif - return res; - } - - __IAR_FT void __set_MSPLIM(uint32_t value) - { - #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions and secure, there is no stack limit check. - (void)value; - #else - __asm volatile("MSR MSPLIM,%0" :: "r" (value)); - #endif - } - - __IAR_FT uint32_t __get_PSPLIM(void) - { - uint32_t res; - #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions and secure, there is no stack limit check. - res = 0U; - #else - __asm volatile("MRS %0,PSPLIM" : "=r" (res)); - #endif - return res; - } - - __IAR_FT void __set_PSPLIM(uint32_t value) - { - #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions and secure, there is no stack limit check. - (void)value; - #else - __asm volatile("MSR PSPLIM,%0" :: "r" (value)); - #endif - } - - __IAR_FT uint32_t __TZ_get_CONTROL_NS(void) - { - uint32_t res; - __asm volatile("MRS %0,CONTROL_NS" : "=r" (res)); - return res; - } - - __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) - { - __asm volatile("MSR CONTROL_NS,%0" :: "r" (value)); - __iar_builtin_ISB(); - } - - __IAR_FT uint32_t __TZ_get_PSP_NS(void) - { - uint32_t res; - __asm volatile("MRS %0,PSP_NS" : "=r" (res)); - return res; - } - - __IAR_FT void __TZ_set_PSP_NS(uint32_t value) - { - __asm volatile("MSR PSP_NS,%0" :: "r" (value)); - } - - __IAR_FT uint32_t __TZ_get_MSP_NS(void) - { - uint32_t res; - __asm volatile("MRS %0,MSP_NS" : "=r" (res)); - return res; - } - - __IAR_FT void __TZ_set_MSP_NS(uint32_t value) - { - __asm volatile("MSR MSP_NS,%0" :: "r" (value)); - } - - __IAR_FT uint32_t __TZ_get_SP_NS(void) - { - uint32_t res; - __asm volatile("MRS %0,SP_NS" : "=r" (res)); - return res; - } - __IAR_FT void __TZ_set_SP_NS(uint32_t value) - { - __asm volatile("MSR SP_NS,%0" :: "r" (value)); - } - - __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void) - { - uint32_t res; - __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res)); - return res; - } - - __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value) - { - __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value)); - } - - __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void) - { - uint32_t res; - __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res)); - return res; - } - - __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value) - { - __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value)); - } - - __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void) - { - uint32_t res; - __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res)); - return res; - } - - __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value) - { - __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value)); - } - - __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) - { - uint32_t res; - #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - res = 0U; - #else - __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res)); - #endif - return res; - } - - __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) - { - #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - (void)value; - #else - __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value)); - #endif - } - - __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) - { - uint32_t res; - __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res)); - return res; - } - - __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value) - { - __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value)); - } - - #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ or __ARM_ARCH_8_1M_MAIN__ */ - -#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ - -#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) - -#if __IAR_M0_FAMILY - __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) - { - if ((sat >= 1U) && (sat <= 32U)) - { - const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); - const int32_t min = -1 - max ; - if (val > max) - { - return max; - } - else if (val < min) - { - return min; - } - } - return val; - } - - __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) - { - if (sat <= 31U) - { - const uint32_t max = ((1U << sat) - 1U); - if (val > (int32_t)max) - { - return max; - } - else if (val < 0) - { - return 0U; - } - } - return (uint32_t)val; - } -#endif - -#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ - - __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) - { - uint32_t res; - __ASM volatile ("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); - return ((uint8_t)res); - } - - __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) - { - uint32_t res; - __ASM volatile ("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); - return ((uint16_t)res); - } - - __IAR_FT uint32_t __LDRT(volatile uint32_t *addr) - { - uint32_t res; - __ASM volatile ("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); - return res; - } - - __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) - { - __ASM volatile ("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); - } - - __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) - { - __ASM volatile ("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); - } - - __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) - { - __ASM volatile ("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory"); - } - -#endif /* (__CORTEX_M >= 0x03) */ - -#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) - - - __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) - { - uint32_t res; - __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); - return ((uint8_t)res); - } - - __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) - { - uint32_t res; - __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); - return ((uint16_t)res); - } - - __IAR_FT uint32_t __LDA(volatile uint32_t *ptr) - { - uint32_t res; - __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); - return res; - } - - __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) - { - __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); - } - - __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) - { - __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); - } - - __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) - { - __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); - } - - __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) - { - uint32_t res; - __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); - return ((uint8_t)res); - } - - __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) - { - uint32_t res; - __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); - return ((uint16_t)res); - } - - __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) - { - uint32_t res; - __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); - return res; - } - - __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) - { - uint32_t res; - __ASM volatile ("STLEXB %0, %2, [%1]" : "=&r" (res) : "r" (ptr), "r" (value) : "memory"); - return res; - } - - __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) - { - uint32_t res; - __ASM volatile ("STLEXH %0, %2, [%1]" : "=&r" (res) : "r" (ptr), "r" (value) : "memory"); - return res; - } - - __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) - { - uint32_t res; - __ASM volatile ("STLEX %0, %2, [%1]" : "=&r" (res) : "r" (ptr), "r" (value) : "memory"); - return res; - } - -#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ - -#undef __IAR_FT -#undef __IAR_M0_FAMILY -#undef __ICCARM_V8 - -#pragma diag_default=Pe940 -#pragma diag_default=Pe177 - -#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) - -#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) - -#endif /* __CMSIS_ICCARM_M_H__ */ diff --git a/lib/main/pico-sdk/rp2_common/cmsis/stub/CMSIS/Core/Include/m-profile/cmsis_tiarmclang_m.h b/lib/main/pico-sdk/rp2_common/cmsis/stub/CMSIS/Core/Include/m-profile/cmsis_tiarmclang_m.h deleted file mode 100644 index 5b193a17a5..0000000000 --- a/lib/main/pico-sdk/rp2_common/cmsis/stub/CMSIS/Core/Include/m-profile/cmsis_tiarmclang_m.h +++ /dev/null @@ -1,1451 +0,0 @@ -/* - * Copyright (c) 2023-2024 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* - * CMSIS-Core(M) Compiler TIARMClang Header File - */ - -#ifndef __CMSIS_TIARMCLANG_M_H -#define __CMSIS_TIARMCLANG_M_H - -#pragma clang system_header /* treat file as system include file */ - -#if (__ARM_ACLE >= 200) - #include -#else - #error Compiler must support ACLE V2.0 -#endif /* (__ARM_ACLE >= 200) */ - -/* CMSIS compiler specific defines */ -#ifndef __ASM - #define __ASM __asm -#endif -#ifndef __INLINE - #define __INLINE __inline -#endif -#ifndef __STATIC_INLINE - #define __STATIC_INLINE static __inline -#endif -#ifndef __STATIC_FORCEINLINE - #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline -#endif -#ifndef __NO_RETURN - #define __NO_RETURN __attribute__((__noreturn__)) -#endif -#ifndef __USED - #define __USED __attribute__((used)) -#endif -#ifndef __WEAK - #define __WEAK __attribute__((weak)) -#endif -#ifndef __PACKED - #define __PACKED __attribute__((packed, aligned(1))) -#endif -#ifndef __PACKED_STRUCT - #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) -#endif -#ifndef __PACKED_UNION - #define __PACKED_UNION union __attribute__((packed, aligned(1))) -#endif -#ifndef __UNALIGNED_UINT16_WRITE - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wpacked" - __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; - #pragma clang diagnostic pop - #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) -#endif -#ifndef __UNALIGNED_UINT16_READ - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wpacked" - __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; - #pragma clang diagnostic pop - #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) -#endif -#ifndef __UNALIGNED_UINT32_WRITE - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wpacked" - __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; - #pragma clang diagnostic pop - #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) -#endif -#ifndef __UNALIGNED_UINT32_READ - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wpacked" - __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; - #pragma clang diagnostic pop - #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) -#endif -#ifndef __ALIGNED - #define __ALIGNED(x) __attribute__((aligned(x))) -#endif -#ifndef __RESTRICT - #define __RESTRICT __restrict -#endif -#ifndef __COMPILER_BARRIER - #define __COMPILER_BARRIER() __ASM volatile("":::"memory") -#endif -#ifndef __NO_INIT - #define __NO_INIT __attribute__ ((section (".noinit"))) -#endif -#ifndef __ALIAS - #define __ALIAS(x) __attribute__ ((alias(x))) -#endif - -/* ######################### Startup and Lowlevel Init ######################## */ -#ifndef __PROGRAM_START -#define __PROGRAM_START _c_int00 -#endif - -#ifndef __INITIAL_SP -#define __INITIAL_SP __STACK_END -#endif - -#ifndef __STACK_LIMIT -#define __STACK_LIMIT __STACK_SIZE -#endif - -#ifndef __VECTOR_TABLE -#define __VECTOR_TABLE __Vectors -#endif - -#ifndef __VECTOR_TABLE_ATTRIBUTE -#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section(".intvecs"))) -#endif - -#if (__ARM_FEATURE_CMSE == 3) -#ifndef __STACK_SEAL -#define __STACK_SEAL Image$$STACKSEAL$$ZI$$Base -#endif - -#ifndef __TZ_STACK_SEAL_SIZE -#define __TZ_STACK_SEAL_SIZE 8U -#endif - -#ifndef __TZ_STACK_SEAL_VALUE -#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL -#endif - - -__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { - *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; -} -#endif - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -/* Define macros for porting to both thumb1 and thumb2. - * For thumb1, use low register (r0-r7), specified by constraint "l" - * Otherwise, use general registers, specified by constraint "r" */ -#if defined (__thumb__) && !defined (__thumb2__) -#define __CMSIS_GCC_OUT_REG(r) "=l" (r) -#define __CMSIS_GCC_RW_REG(r) "+l" (r) -#define __CMSIS_GCC_USE_REG(r) "l" (r) -#else -#define __CMSIS_GCC_OUT_REG(r) "=r" (r) -#define __CMSIS_GCC_RW_REG(r) "+r" (r) -#define __CMSIS_GCC_USE_REG(r) "r" (r) -#endif - -/** - \brief No Operation - \details No Operation does nothing. This instruction can be used for code alignment purposes. - */ -#define __NOP() __nop() - - -/** - \brief Wait For Interrupt - \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. - */ -#define __WFI() __wfi() - - -/** - \brief Wait For Event - \details Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -#define __WFE() __wfe() - - -/** - \brief Send Event - \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -#define __SEV() __sev() - - -/** - \brief Instruction Synchronization Barrier - \details Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or memory, - after the instruction has been completed. - */ -#define __ISB() __isb(0xF) - - -/** - \brief Data Synchronization Barrier - \details Acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -#define __DSB() __dsb(0xF) - - -/** - \brief Data Memory Barrier - \details Ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -#define __DMB() __dmb(0xF) - - -/** - \brief Reverse byte order (32 bit) - \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV(value) __rev(value) - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV16(value) __rev16(value) - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. - \param [in] value Value to reverse - \return Reversed value - */ -#define __REVSH(value) __revsh(value) - - -/** - \brief Rotate Right in unsigned value (32 bit) - \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - \param [in] op1 Value to rotate - \param [in] op2 Number of Bits to rotate - \return Rotated value - */ -#define __ROR(op1, op2) __ror(op1, op2) - - -/** - \brief Breakpoint - \details Causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __ASM volatile ("bkpt "#value) - - -/** - \brief Reverse bit order of value - \details Reverses the bit order of the given value. - \param [in] value Value to reverse - \return Reversed value - */ -#define __RBIT(value) __rbit(value) - - -/** - \brief Count leading zeros - \details Counts the number of leading zeros of a data value. - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -#define __CLZ(value) __clz(value) - - -/* __ARM_FEATURE_SAT is wrong for for Armv8-M Baseline devices */ -#if ((__ARM_FEATURE_SAT >= 1) && \ - (__ARM_ARCH_ISA_THUMB >= 2) ) -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT(value, sat) __ssat(value, sat) - - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT(value, sat) __usat(value, sat) - -#else /* (__ARM_FEATURE_SAT >= 1) */ -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) -{ - if ((sat >= 1U) && (sat <= 32U)) - { - const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); - const int32_t min = -1 - max ; - if (val > max) - { - return (max); - } - else if (val < min) - { - return (min); - } - } - return (val); -} - - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) -{ - if (sat <= 31U) - { - const uint32_t max = ((1U << sat) - 1U); - if (val > (int32_t)max) - { - return (max); - } - else if (val < 0) - { - return (0U); - } - } - return ((uint32_t)val); -} -#endif /* (__ARM_FEATURE_SAT >= 1) */ - - -#if (__ARM_FEATURE_LDREX >= 1) -/** - \brief Remove the exclusive lock - \details Removes the exclusive lock which is created by LDREX. - */ -#define __CLREX __builtin_arm_clrex - - -/** - \brief LDR Exclusive (8 bit) - \details Executes a exclusive LDR instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDREXB (uint8_t)__builtin_arm_ldrex - - -/** - \brief STR Exclusive (8 bit) - \details Executes a exclusive STR instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXB (uint32_t)__builtin_arm_strex -#endif /* (__ARM_FEATURE_LDREX >= 1) */ - - -#if (__ARM_FEATURE_LDREX >= 2) -/** - \brief LDR Exclusive (16 bit) - \details Executes a exclusive LDR instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDREXH (uint16_t)__builtin_arm_ldrex - - -/** - \brief STR Exclusive (16 bit) - \details Executes a exclusive STR instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXH (uint32_t)__builtin_arm_strex -#endif /* (__ARM_FEATURE_LDREX >= 2) */ - - -#if (__ARM_FEATURE_LDREX >= 4) -/** - \brief LDR Exclusive (32 bit) - \details Executes a exclusive LDR instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDREXW (uint32_t)__builtin_arm_ldrex - - -/** - \brief STR Exclusive (32 bit) - \details Executes a exclusive STR instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXW (uint32_t)__builtin_arm_strex -#endif /* (__ARM_FEATURE_LDREX >= 4) */ - - -#if (__ARM_ARCH_ISA_THUMB >= 2) -/** - \brief Rotate Right with Extend (32 bit) - \details Moves each bit of a bitstring right by one bit. - The carry input is shifted in at the left end of the bitstring. - \param [in] value Value to rotate - \return Rotated value - */ -__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rrx %0, %1" : "=r" (result) : "r" (value)); - return (result); -} - - -/** - \brief LDRT Unprivileged (8 bit) - \details Executes a Unprivileged LDRT instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint8_t)result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (16 bit) - \details Executes a Unprivileged LDRT instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint16_t)result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (32 bit) - \details Executes a Unprivileged LDRT instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); - return (result); -} - - -/** - \brief STRT Unprivileged (8 bit) - \details Executes a Unprivileged STRT instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) -{ - __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (16 bit) - \details Executes a Unprivileged STRT instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) -{ - __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (32 bit) - \details Executes a Unprivileged STRT instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) -{ - __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); -} -#endif /* (__ARM_ARCH_ISA_THUMB >= 2) */ - - -#if (__ARM_ARCH >= 8) -/** - \brief Load-Acquire (8 bit) - \details Executes a LDAB instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); - return ((uint8_t)result); /* Add explicit type cast here */ -} - - -/** - \brief Load-Acquire (16 bit) - \details Executes a LDAH instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); - return ((uint16_t)result); /* Add explicit type cast here */ -} - - -/** - \brief Load-Acquire (32 bit) - \details Executes a LDA instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); - return (result); -} - - -/** - \brief Store-Release (8 bit) - \details Executes a STLB instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) -{ - __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); -} - - -/** - \brief Store-Release (16 bit) - \details Executes a STLH instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) -{ - __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); -} - - -/** - \brief Store-Release (32 bit) - \details Executes a STL instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) -{ - __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); -} - - -/** - \brief Load-Acquire Exclusive (8 bit) - \details Executes a LDAB exclusive instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDAEXB (uint8_t)__builtin_arm_ldaex - - -/** - \brief Load-Acquire Exclusive (16 bit) - \details Executes a LDAH exclusive instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDAEXH (uint16_t)__builtin_arm_ldaex - - -/** - \brief Load-Acquire Exclusive (32 bit) - \details Executes a LDA exclusive instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDAEX (uint32_t)__builtin_arm_ldaex - - -/** - \brief Store-Release Exclusive (8 bit) - \details Executes a STLB exclusive instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STLEXB (uint32_t)__builtin_arm_stlex - - -/** - \brief Store-Release Exclusive (16 bit) - \details Executes a STLH exclusive instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STLEXH (uint32_t)__builtin_arm_stlex - - -/** - \brief Store-Release Exclusive (32 bit) - \details Executes a STL exclusive instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STLEX (uint32_t)__builtin_arm_stlex - -#endif /* (__ARM_ARCH >= 8) */ - -/** @}*/ /* end of group CMSIS_Core_InstructionInterface */ - - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -/** - \brief Enable IRQ Interrupts - \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. - Can only be executed in Privileged modes. - */ -#ifndef __ARM_COMPAT_H -__STATIC_FORCEINLINE void __enable_irq(void) -{ - __ASM volatile ("cpsie i" : : : "memory"); -} -#endif - - -/** - \brief Disable IRQ Interrupts - \details Disables IRQ interrupts by setting special-purpose register PRIMASK. - Can only be executed in Privileged modes. - */ -#ifndef __ARM_COMPAT_H -__STATIC_FORCEINLINE void __disable_irq(void) -{ - __ASM volatile ("cpsid i" : : : "memory"); -} -#endif - - -/** - \brief Get Control Register - \details Returns the content of the Control Register. - \return Control Register value - */ -__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control" : "=r" (result) ); - return (result); -} - - -#if (__ARM_FEATURE_CMSE == 3) -/** - \brief Get Control Register (non-secure) - \details Returns the content of the non-secure Control Register when in secure mode. - \return non-secure Control Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); - return (result); -} -#endif - - -/** - \brief Set Control Register - \details Writes the given value to the Control Register. - \param [in] control Control Register value to set - */ -__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) -{ - __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); - __ISB(); -} - - -#if (__ARM_FEATURE_CMSE == 3) -/** - \brief Set Control Register (non-secure) - \details Writes the given value to the non-secure Control Register when in secure state. - \param [in] control Control Register value to set - */ -__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) -{ - __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); - __ISB(); -} -#endif - - -/** - \brief Get IPSR Register - \details Returns the content of the IPSR Register. - \return IPSR Register value - */ -__STATIC_FORCEINLINE uint32_t __get_IPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); - return (result); -} - - -/** - \brief Get APSR Register - \details Returns the content of the APSR Register. - \return APSR Register value - */ -__STATIC_FORCEINLINE uint32_t __get_APSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, apsr" : "=r" (result) ); - return (result); -} - - -/** - \brief Get xPSR Register - \details Returns the content of the xPSR Register. - \return xPSR Register value - */ -__STATIC_FORCEINLINE uint32_t __get_xPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); - return (result); -} - - -/** - \brief Get Process Stack Pointer - \details Returns the current value of the Process Stack Pointer (PSP). - \return PSP Register value - */ -__STATIC_FORCEINLINE uint32_t __get_PSP(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, psp" : "=r" (result) ); - return (result); -} - - -#if (__ARM_FEATURE_CMSE == 3) -/** - \brief Get Process Stack Pointer (non-secure) - \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. - \return PSP Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); - return (result); -} -#endif - - -/** - \brief Set Process Stack Pointer - \details Assigns the given value to the Process Stack Pointer (PSP). - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); -} - - -#if (__ARM_FEATURE_CMSE == 3) -/** - \brief Set Process Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); -} -#endif - - -/** - \brief Get Main Stack Pointer - \details Returns the current value of the Main Stack Pointer (MSP). - \return MSP Register value - */ -__STATIC_FORCEINLINE uint32_t __get_MSP(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, msp" : "=r" (result) ); - return (result); -} - - -#if (__ARM_FEATURE_CMSE == 3) -/** - \brief Get Main Stack Pointer (non-secure) - \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. - \return MSP Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); - return (result); -} -#endif - - -/** - \brief Set Main Stack Pointer - \details Assigns the given value to the Main Stack Pointer (MSP). - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); -} - - -#if (__ARM_FEATURE_CMSE == 3) -/** - \brief Set Main Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); -} -#endif - - -#if (__ARM_FEATURE_CMSE == 3) -/** - \brief Get Stack Pointer (non-secure) - \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. - \return SP Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); - return (result); -} - - -/** - \brief Set Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. - \param [in] topOfStack Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) -{ - __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); -} -#endif - - -/** - \brief Get Priority Mask - \details Returns the current state of the priority mask bit from the Priority Mask Register. - \return Priority Mask value - */ -__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask" : "=r" (result) ); - return (result); -} - - -#if (__ARM_FEATURE_CMSE == 3) -/** - \brief Get Priority Mask (non-secure) - \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. - \return Priority Mask value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); - return (result); -} -#endif - - -/** - \brief Set Priority Mask - \details Assigns the given value to the Priority Mask Register. - \param [in] priMask Priority Mask - */ -__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) -{ - __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); -} - - -#if (__ARM_FEATURE_CMSE == 3) -/** - \brief Set Priority Mask (non-secure) - \details Assigns the given value to the non-secure Priority Mask Register when in secure state. - \param [in] priMask Priority Mask - */ -__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) -{ - __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); -} -#endif - - -#if (__ARM_ARCH_ISA_THUMB >= 2) -/** - \brief Enable FIQ - \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. - Can only be executed in Privileged modes. - */ -__STATIC_FORCEINLINE void __enable_fault_irq(void) -{ - __ASM volatile ("cpsie f" : : : "memory"); -} - - -/** - \brief Disable FIQ - \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. - Can only be executed in Privileged modes. - */ -__STATIC_FORCEINLINE void __disable_fault_irq(void) -{ - __ASM volatile ("cpsid f" : : : "memory"); -} - - -/** - \brief Get Base Priority - \details Returns the current value of the Base Priority register. - \return Base Priority register value - */ -__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri" : "=r" (result) ); - return (result); -} - - -#if (__ARM_FEATURE_CMSE == 3) -/** - \brief Get Base Priority (non-secure) - \details Returns the current value of the non-secure Base Priority register when in secure state. - \return Base Priority register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); - return (result); -} -#endif - - -/** - \brief Set Base Priority - \details Assigns the given value to the Base Priority register. - \param [in] basePri Base Priority value to set - */ -__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) -{ - __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); -} - - -#if (__ARM_FEATURE_CMSE == 3) -/** - \brief Set Base Priority (non-secure) - \details Assigns the given value to the non-secure Base Priority register when in secure state. - \param [in] basePri Base Priority value to set - */ -__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) -{ - __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); -} -#endif - - -/** - \brief Set Base Priority with condition - \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, - or the new value increases the BASEPRI priority level. - \param [in] basePri Base Priority value to set - */ -__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) -{ - __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); -} - - -/** - \brief Get Fault Mask - \details Returns the current value of the Fault Mask register. - \return Fault Mask register value - */ -__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); - return (result); -} - - -#if (__ARM_FEATURE_CMSE == 3) -/** - \brief Get Fault Mask (non-secure) - \details Returns the current value of the non-secure Fault Mask register when in secure state. - \return Fault Mask register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); - return (result); -} -#endif - - -/** - \brief Set Fault Mask - \details Assigns the given value to the Fault Mask register. - \param [in] faultMask Fault Mask value to set - */ -__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); -} - - -#if (__ARM_FEATURE_CMSE == 3) -/** - \brief Set Fault Mask (non-secure) - \details Assigns the given value to the non-secure Fault Mask register when in secure state. - \param [in] faultMask Fault Mask value to set - */ -__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); -} -#endif - -#endif /* (__ARM_ARCH_ISA_THUMB >= 2) */ - - -#if (__ARM_ARCH >= 8) -/** - \brief Get Process Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always in non-secure - mode. - - \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). - \return PSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) -{ -#if (((__ARM_ARCH_8M_MAIN__ < 1) && \ - (__ARM_ARCH_8_1M_MAIN__ < 1) ) && \ - (__ARM_FEATURE_CMSE < 3) ) - /* without main extensions, the non-secure PSPLIM is RAZ/WI */ - return (0U); -#else - uint32_t result; - __ASM volatile ("MRS %0, psplim" : "=r" (result) ); - return (result); -#endif -} - -#if (__ARM_FEATURE_CMSE == 3) -/** - \brief Get Process Stack Pointer Limit (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always. - - \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. - \return PSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) -{ -#if ((__ARM_ARCH_8M_MAIN__ < 1) && \ - (__ARM_ARCH_8_1M_MAIN__ < 1) ) - /* without main extensions, the non-secure PSPLIM is RAZ/WI */ - return (0U); -#else - uint32_t result; - __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); - return (result); -#endif -} -#endif - - -/** - \brief Set Process Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored in non-secure - mode. - - \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). - \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set - */ -__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) -{ -#if (((__ARM_ARCH_8M_MAIN__ < 1) && \ - (__ARM_ARCH_8_1M_MAIN__ < 1) ) && \ - (__ARM_FEATURE_CMSE < 3) ) - /* without main extensions, the non-secure PSPLIM is RAZ/WI */ - (void)ProcStackPtrLimit; -#else - __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); -#endif -} - - -#if (__ARM_FEATURE_CMSE == 3) -/** - \brief Set Process Stack Pointer (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored. - - \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. - \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set - */ -__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) -{ -#if ((__ARM_ARCH_8M_MAIN__ < 1) && \ - (__ARM_ARCH_8_1M_MAIN__ < 1) ) - /* without main extensions, the non-secure PSPLIM is RAZ/WI */ - (void)ProcStackPtrLimit; -#else - __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); -#endif -} -#endif - - -/** - \brief Get Main Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always. - - \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). - \return MSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) -{ -#if (((__ARM_ARCH_8M_MAIN__ < 1) && \ - (__ARM_ARCH_8_1M_MAIN__ < 1) ) && \ - (__ARM_FEATURE_CMSE < 3) ) - /* without main extensions, the non-secure MSPLIM is RAZ/WI */ - return (0U); -#else - uint32_t result; - __ASM volatile ("MRS %0, msplim" : "=r" (result) ); - return (result); -#endif -} - - -#if (__ARM_FEATURE_CMSE == 3) -/** - \brief Get Main Stack Pointer Limit (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always. - - \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. - \return MSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) -{ -#if ((__ARM_ARCH_8M_MAIN__ < 1) && \ - (__ARM_ARCH_8_1M_MAIN__ < 1) ) - /* without main extensions, the non-secure MSPLIM is RAZ/WI */ - return (0U); -#else - uint32_t result; - __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); - return (result); -#endif -} -#endif - - -/** - \brief Set Main Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored. - - \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). - \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set - */ -__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) -{ -#if (((__ARM_ARCH_8M_MAIN__ < 1) && \ - (__ARM_ARCH_8_1M_MAIN__ < 1) ) && \ - (__ARM_FEATURE_CMSE < 3) ) - /* without main extensions, the non-secure MSPLIM is RAZ/WI */ - (void)MainStackPtrLimit; -#else - __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); -#endif -} - - -#if (__ARM_FEATURE_CMSE == 3) -/** - \brief Set Main Stack Pointer Limit (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored. - - \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. - \param [in] MainStackPtrLimit Main Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) -{ -#if ((__ARM_ARCH_8M_MAIN__ < 1) && \ - (__ARM_ARCH_8_1M_MAIN__ < 1) ) - /* without main extensions, the non-secure MSPLIM is RAZ/WI */ - (void)MainStackPtrLimit; -#else - __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); -#endif -} -#endif - -#endif /* (__ARM_ARCH >= 8) */ - - -/** - \brief Get FPSCR - \details Returns the current value of the Floating Point Status/Control register. - \return Floating Point Status/Control register value - */ -__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) -{ -#if (defined(__ARM_FP) && (__ARM_FP >= 1)) - return (__builtin_arm_get_fpscr()); -#else - return (0U); -#endif -} - - -/** - \brief Set FPSCR - \details Assigns the given value to the Floating Point Status/Control register. - \param [in] fpscr Floating Point Status/Control value to set - */ -__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) -{ -#if (defined(__ARM_FP) && (__ARM_FP >= 1)) - __builtin_arm_set_fpscr(fpscr); -#else - (void)fpscr; -#endif -} - - -/** @} end of CMSIS_Core_RegAccFunctions */ - - -/* ################### Compiler specific Intrinsics ########################### */ -/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics - Access to dedicated SIMD instructions - @{ -*/ - -#if (__ARM_FEATURE_DSP == 1) -#define __SADD8 __sadd8 -#define __QADD8 __qadd8 -#define __SHADD8 __shadd8 -#define __UADD8 __uadd8 -#define __UQADD8 __uqadd8 -#define __UHADD8 __uhadd8 -#define __SSUB8 __ssub8 -#define __QSUB8 __qsub8 -#define __SHSUB8 __shsub8 -#define __USUB8 __usub8 -#define __UQSUB8 __uqsub8 -#define __UHSUB8 __uhsub8 -#define __SADD16 __sadd16 -#define __QADD16 __qadd16 -#define __SHADD16 __shadd16 -#define __UADD16 __uadd16 -#define __UQADD16 __uqadd16 -#define __UHADD16 __uhadd16 -#define __SSUB16 __ssub16 -#define __QSUB16 __qsub16 -#define __SHSUB16 __shsub16 -#define __USUB16 __usub16 -#define __UQSUB16 __uqsub16 -#define __UHSUB16 __uhsub16 -#define __SASX __sasx -#define __QASX __qasx -#define __SHASX __shasx -#define __UASX __uasx -#define __UQASX __uqasx -#define __UHASX __uhasx -#define __SSAX __ssax -#define __QSAX __qsax -#define __SHSAX __shsax -#define __USAX __usax -#define __UQSAX __uqsax -#define __UHSAX __uhsax -#define __USAD8 __usad8 -#define __USADA8 __usada8 -#define __SSAT16 __ssat16 -#define __USAT16 __usat16 -#define __UXTB16 __uxtb16 -#define __UXTAB16 __uxtab16 -#define __SXTB16 __sxtb16 -#define __SXTAB16 __sxtab16 -#define __SMUAD __smuad -#define __SMUADX __smuadx -#define __SMLAD __smlad -#define __SMLADX __smladx -#define __SMLALD __smlald -#define __SMLALDX __smlaldx -#define __SMUSD __smusd -#define __SMUSDX __smusdx -#define __SMLSD __smlsd -#define __SMLSDX __smlsdx -#define __SMLSLD __smlsld -#define __SMLSLDX __smlsldx -#define __SEL __sel -#define __QADD __qadd -#define __QSUB __qsub - -#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ - ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) - -#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ - ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) - -#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) - -#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) - -__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) -{ - int32_t result; - - __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); - return (result); -} - -#endif /* (__ARM_FEATURE_DSP == 1) */ -/** @} end of group CMSIS_SIMD_intrinsics */ - - -#endif /* __CMSIS_TIARMCLANG_M_H */ diff --git a/lib/main/pico-sdk/rp2_common/cmsis/stub/CMSIS/Core/Include/mpu_armv7.h b/lib/main/pico-sdk/rp2_common/cmsis/stub/CMSIS/Core/Include/mpu_armv7.h deleted file mode 100644 index 6e27fe3210..0000000000 --- a/lib/main/pico-sdk/rp2_common/cmsis/stub/CMSIS/Core/Include/mpu_armv7.h +++ /dev/null @@ -1,275 +0,0 @@ -/****************************************************************************** - * @file mpu_armv7.h - * @brief CMSIS MPU API for Armv7-M MPU - * @version V5.1.1 - * @date 10. February 2020 - ******************************************************************************/ -/* - * Copyright (c) 2017-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef ARM_MPU_ARMV7_H -#define ARM_MPU_ARMV7_H - -#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes -#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes -#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes -#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes -#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes -#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte -#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes -#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes -#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes -#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes -#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes -#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes -#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes -#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes -#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes -#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte -#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes -#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes -#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes -#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes -#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes -#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes -#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes -#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes -#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes -#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte -#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes -#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes - -#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access -#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only -#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only -#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access -#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only -#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access - -/** MPU Region Base Address Register Value -* -* \param Region The region to be configured, number 0 to 15. -* \param BaseAddress The base address for the region. -*/ -#define ARM_MPU_RBAR(Region, BaseAddress) \ - (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \ - ((Region) & MPU_RBAR_REGION_Msk) | \ - (MPU_RBAR_VALID_Msk)) - -/** -* \brief MPU Memory Access Attributes -* -* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. -* \param IsShareable Region is shareable between multiple bus masters. -* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. -* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. -*/ -#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ - ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ - (((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ - (((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ - (((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk)) - -/** -* \brief MPU Region Attribute and Size Register Value -* -* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. -* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. -* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_. -* \param SubRegionDisable Sub-region disable field. -* \param Size Region size of the region to be configured, for example 4K, 8K. -*/ -#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \ - ((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ - (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ - (((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \ - (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \ - (((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \ - (((MPU_RASR_ENABLE_Msk)))) - -/** -* \brief MPU Region Attribute and Size Register Value -* -* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. -* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. -* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. -* \param IsShareable Region is shareable between multiple bus masters. -* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. -* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. -* \param SubRegionDisable Sub-region disable field. -* \param Size Region size of the region to be configured, for example 4K, 8K. -*/ -#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ - ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size) - -/** -* \brief MPU Memory Access Attribute for strongly ordered memory. -* - TEX: 000b -* - Shareable -* - Non-cacheable -* - Non-bufferable -*/ -#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U) - -/** -* \brief MPU Memory Access Attribute for device memory. -* - TEX: 000b (if shareable) or 010b (if non-shareable) -* - Shareable or non-shareable -* - Non-cacheable -* - Bufferable (if shareable) or non-bufferable (if non-shareable) -* -* \param IsShareable Configures the device memory as shareable or non-shareable. -*/ -#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U)) - -/** -* \brief MPU Memory Access Attribute for normal memory. -* - TEX: 1BBb (reflecting outer cacheability rules) -* - Shareable or non-shareable -* - Cacheable or non-cacheable (reflecting inner cacheability rules) -* - Bufferable or non-bufferable (reflecting inner cacheability rules) -* -* \param OuterCp Configures the outer cache policy. -* \param InnerCp Configures the inner cache policy. -* \param IsShareable Configures the memory as shareable or non-shareable. -*/ -#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) >> 1U), ((InnerCp) & 1U)) - -/** -* \brief MPU Memory Access Attribute non-cacheable policy. -*/ -#define ARM_MPU_CACHEP_NOCACHE 0U - -/** -* \brief MPU Memory Access Attribute write-back, write and read allocate policy. -*/ -#define ARM_MPU_CACHEP_WB_WRA 1U - -/** -* \brief MPU Memory Access Attribute write-through, no write allocate policy. -*/ -#define ARM_MPU_CACHEP_WT_NWA 2U - -/** -* \brief MPU Memory Access Attribute write-back, no write allocate policy. -*/ -#define ARM_MPU_CACHEP_WB_NWA 3U - - -/** -* \brief Struct for a single MPU Region -*/ -typedef struct { - uint32_t RBAR; //!< The region base address register value (RBAR) - uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR -} ARM_MPU_Region_t; - -/** Enable the MPU. -* \param MPU_Control Default access permissions for unconfigured regions. -*/ -__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) -{ - __DMB(); - MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; -#ifdef SCB_SHCSR_MEMFAULTENA_Msk - SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; -#endif - __DSB(); - __ISB(); -} - -/** Disable the MPU. -*/ -__STATIC_INLINE void ARM_MPU_Disable(void) -{ - __DMB(); -#ifdef SCB_SHCSR_MEMFAULTENA_Msk - SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; -#endif - MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; - __DSB(); - __ISB(); -} - -/** Clear and disable the given MPU region. -* \param rnr Region number to be cleared. -*/ -__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) -{ - MPU->RNR = rnr; - MPU->RASR = 0U; -} - -/** Configure an MPU region. -* \param rbar Value for RBAR register. -* \param rsar Value for RSAR register. -*/ -__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) -{ - MPU->RBAR = rbar; - MPU->RASR = rasr; -} - -/** Configure the given MPU region. -* \param rnr Region number to be configured. -* \param rbar Value for RBAR register. -* \param rsar Value for RSAR register. -*/ -__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) -{ - MPU->RNR = rnr; - MPU->RBAR = rbar; - MPU->RASR = rasr; -} - -/** Memcopy with strictly ordered memory access, e.g. for register targets. -* \param dst Destination data is copied to. -* \param src Source data is copied from. -* \param len Amount of data words to be copied. -*/ -__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) -{ - uint32_t i; - for (i = 0U; i < len; ++i) - { - dst[i] = src[i]; - } -} - -/** Load the given number of MPU regions from a table. -* \param table Pointer to the MPU configuration table. -* \param cnt Amount of regions to be configured. -*/ -__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) -{ - const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; - while (cnt > MPU_TYPE_RALIASES) { - ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); - table += MPU_TYPE_RALIASES; - cnt -= MPU_TYPE_RALIASES; - } - ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); -} - -#endif diff --git a/lib/main/pico-sdk/rp2_common/cmsis/stub/CMSIS/Core/Include/mpu_armv8.h b/lib/main/pico-sdk/rp2_common/cmsis/stub/CMSIS/Core/Include/mpu_armv8.h deleted file mode 100644 index 3de16efc86..0000000000 --- a/lib/main/pico-sdk/rp2_common/cmsis/stub/CMSIS/Core/Include/mpu_armv8.h +++ /dev/null @@ -1,352 +0,0 @@ -/****************************************************************************** - * @file mpu_armv8.h - * @brief CMSIS MPU API for Armv8-M and Armv8.1-M MPU - * @version V5.1.3 - * @date 03. February 2021 - ******************************************************************************/ -/* - * Copyright (c) 2017-2021 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef ARM_MPU_ARMV8_H -#define ARM_MPU_ARMV8_H - -/** \brief Attribute for device memory (outer only) */ -#define ARM_MPU_ATTR_DEVICE ( 0U ) - -/** \brief Attribute for non-cacheable, normal memory */ -#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U ) - -/** \brief Attribute for normal memory (outer and inner) -* \param NT Non-Transient: Set to 1 for non-transient data. -* \param WB Write-Back: Set to 1 to use write-back update policy. -* \param RA Read Allocation: Set to 1 to use cache allocation on read miss. -* \param WA Write Allocation: Set to 1 to use cache allocation on write miss. -*/ -#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \ - ((((NT) & 1U) << 3U) | (((WB) & 1U) << 2U) | (((RA) & 1U) << 1U) | ((WA) & 1U)) - -/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */ -#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U) - -/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */ -#define ARM_MPU_ATTR_DEVICE_nGnRE (1U) - -/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */ -#define ARM_MPU_ATTR_DEVICE_nGRE (2U) - -/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */ -#define ARM_MPU_ATTR_DEVICE_GRE (3U) - -/** \brief Memory Attribute -* \param O Outer memory attributes -* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes -*/ -#define ARM_MPU_ATTR(O, I) ((((O) & 0xFU) << 4U) | ((((O) & 0xFU) != 0U) ? ((I) & 0xFU) : (((I) & 0x3U) << 2U))) - -/** \brief Normal memory non-shareable */ -#define ARM_MPU_SH_NON (0U) - -/** \brief Normal memory outer shareable */ -#define ARM_MPU_SH_OUTER (2U) - -/** \brief Normal memory inner shareable */ -#define ARM_MPU_SH_INNER (3U) - -/** \brief Memory access permissions -* \param RO Read-Only: Set to 1 for read-only memory. -* \param NP Non-Privileged: Set to 1 for non-privileged memory. -*/ -#define ARM_MPU_AP_(RO, NP) ((((RO) & 1U) << 1U) | ((NP) & 1U)) - -/** \brief Region Base Address Register value -* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned. -* \param SH Defines the Shareability domain for this memory region. -* \param RO Read-Only: Set to 1 for a read-only memory region. -* \param NP Non-Privileged: Set to 1 for a non-privileged memory region. -* \oaram XN eXecute Never: Set to 1 for a non-executable memory region. -*/ -#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ - (((BASE) & MPU_RBAR_BASE_Msk) | \ - (((SH) << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \ - ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \ - (((XN) << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk)) - -/** \brief Region Limit Address Register value -* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. -* \param IDX The attribute index to be associated with this memory region. -*/ -#define ARM_MPU_RLAR(LIMIT, IDX) \ - (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \ - (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ - (MPU_RLAR_EN_Msk)) - -#if defined(MPU_RLAR_PXN_Pos) - -/** \brief Region Limit Address Register with PXN value -* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. -* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region. -* \param IDX The attribute index to be associated with this memory region. -*/ -#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \ - (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \ - (((PXN) << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \ - (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ - (MPU_RLAR_EN_Msk)) - -#endif - -/** -* Struct for a single MPU Region -*/ -typedef struct { - uint32_t RBAR; /*!< Region Base Address Register value */ - uint32_t RLAR; /*!< Region Limit Address Register value */ -} ARM_MPU_Region_t; - -/** Enable the MPU. -* \param MPU_Control Default access permissions for unconfigured regions. -*/ -__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) -{ - __DMB(); - MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; -#ifdef SCB_SHCSR_MEMFAULTENA_Msk - SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; -#endif - __DSB(); - __ISB(); -} - -/** Disable the MPU. -*/ -__STATIC_INLINE void ARM_MPU_Disable(void) -{ - __DMB(); -#ifdef SCB_SHCSR_MEMFAULTENA_Msk - SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; -#endif - MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; - __DSB(); - __ISB(); -} - -#ifdef MPU_NS -/** Enable the Non-secure MPU. -* \param MPU_Control Default access permissions for unconfigured regions. -*/ -__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control) -{ - __DMB(); - MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; -#ifdef SCB_SHCSR_MEMFAULTENA_Msk - SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; -#endif - __DSB(); - __ISB(); -} - -/** Disable the Non-secure MPU. -*/ -__STATIC_INLINE void ARM_MPU_Disable_NS(void) -{ - __DMB(); -#ifdef SCB_SHCSR_MEMFAULTENA_Msk - SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; -#endif - MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; - __DSB(); - __ISB(); -} -#endif - -/** Set the memory attribute encoding to the given MPU. -* \param mpu Pointer to the MPU to be configured. -* \param idx The attribute index to be set [0-7] -* \param attr The attribute value to be set. -*/ -__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr) -{ - const uint8_t reg = idx / 4U; - const uint32_t pos = ((idx % 4U) * 8U); - const uint32_t mask = 0xFFU << pos; - - if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) { - return; // invalid index - } - - mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask)); -} - -/** Set the memory attribute encoding. -* \param idx The attribute index to be set [0-7] -* \param attr The attribute value to be set. -*/ -__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr) -{ - ARM_MPU_SetMemAttrEx(MPU, idx, attr); -} - -#ifdef MPU_NS -/** Set the memory attribute encoding to the Non-secure MPU. -* \param idx The attribute index to be set [0-7] -* \param attr The attribute value to be set. -*/ -__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr) -{ - ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr); -} -#endif - -/** Clear and disable the given MPU region of the given MPU. -* \param mpu Pointer to MPU to be used. -* \param rnr Region number to be cleared. -*/ -__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr) -{ - mpu->RNR = rnr; - mpu->RLAR = 0U; -} - -/** Clear and disable the given MPU region. -* \param rnr Region number to be cleared. -*/ -__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) -{ - ARM_MPU_ClrRegionEx(MPU, rnr); -} - -#ifdef MPU_NS -/** Clear and disable the given Non-secure MPU region. -* \param rnr Region number to be cleared. -*/ -__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) -{ - ARM_MPU_ClrRegionEx(MPU_NS, rnr); -} -#endif - -/** Configure the given MPU region of the given MPU. -* \param mpu Pointer to MPU to be used. -* \param rnr Region number to be configured. -* \param rbar Value for RBAR register. -* \param rlar Value for RLAR register. -*/ -__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) -{ - mpu->RNR = rnr; - mpu->RBAR = rbar; - mpu->RLAR = rlar; -} - -/** Configure the given MPU region. -* \param rnr Region number to be configured. -* \param rbar Value for RBAR register. -* \param rlar Value for RLAR register. -*/ -__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar) -{ - ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar); -} - -#ifdef MPU_NS -/** Configure the given Non-secure MPU region. -* \param rnr Region number to be configured. -* \param rbar Value for RBAR register. -* \param rlar Value for RLAR register. -*/ -__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar) -{ - ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); -} -#endif - -/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_LoadEx() -* \param dst Destination data is copied to. -* \param src Source data is copied from. -* \param len Amount of data words to be copied. -*/ -__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) -{ - uint32_t i; - for (i = 0U; i < len; ++i) - { - dst[i] = src[i]; - } -} - -/** Load the given number of MPU regions from a table to the given MPU. -* \param mpu Pointer to the MPU registers to be used. -* \param rnr First region number to be configured. -* \param table Pointer to the MPU configuration table. -* \param cnt Amount of regions to be configured. -*/ -__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) -{ - const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; - if (cnt == 1U) { - mpu->RNR = rnr; - ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize); - } else { - uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U); - uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; - - mpu->RNR = rnrBase; - while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { - uint32_t c = MPU_TYPE_RALIASES - rnrOffset; - ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize); - table += c; - cnt -= c; - rnrOffset = 0U; - rnrBase += MPU_TYPE_RALIASES; - mpu->RNR = rnrBase; - } - - ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); - } -} - -/** Load the given number of MPU regions from a table. -* \param rnr First region number to be configured. -* \param table Pointer to the MPU configuration table. -* \param cnt Amount of regions to be configured. -*/ -__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) -{ - ARM_MPU_LoadEx(MPU, rnr, table, cnt); -} - -#ifdef MPU_NS -/** Load the given number of MPU regions from a table to the Non-secure MPU. -* \param rnr First region number to be configured. -* \param table Pointer to the MPU configuration table. -* \param cnt Amount of regions to be configured. -*/ -__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) -{ - ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt); -} -#endif - -#endif - diff --git a/lib/main/pico-sdk/rp2_common/cmsis/stub/CMSIS/Core/Include/tz_context.h b/lib/main/pico-sdk/rp2_common/cmsis/stub/CMSIS/Core/Include/tz_context.h deleted file mode 100644 index e095956a8c..0000000000 --- a/lib/main/pico-sdk/rp2_common/cmsis/stub/CMSIS/Core/Include/tz_context.h +++ /dev/null @@ -1,68 +0,0 @@ -/* - * Copyright (c) 2017-2023 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* - * CMSIS Core(M) Context Management for Armv8-M TrustZone - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef TZ_CONTEXT_H -#define TZ_CONTEXT_H - -#include - -#ifndef TZ_MODULEID_T -#define TZ_MODULEID_T -/// \details Data type that identifies secure software modules called by a process. -typedef uint32_t TZ_ModuleId_t; -#endif - -/// \details TZ Memory ID identifies an allocated memory slot. -typedef uint32_t TZ_MemoryId_t; - -/// Initialize secure context memory system -/// \return execution status (1: success, 0: error) -uint32_t TZ_InitContextSystem_S (void); - -/// Allocate context memory for calling secure software modules in TrustZone -/// \param[in] module identifies software modules called from non-secure mode -/// \return value != 0 id TrustZone memory slot identifier -/// \return value 0 no memory available or internal error -TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module); - -/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S -/// \param[in] id TrustZone memory slot identifier -/// \return execution status (1: success, 0: error) -uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id); - -/// Load secure context (called on RTOS thread context switch) -/// \param[in] id TrustZone memory slot identifier -/// \return execution status (1: success, 0: error) -uint32_t TZ_LoadContext_S (TZ_MemoryId_t id); - -/// Store secure context (called on RTOS thread context switch) -/// \param[in] id TrustZone memory slot identifier -/// \return execution status (1: success, 0: error) -uint32_t TZ_StoreContext_S (TZ_MemoryId_t id); - -#endif // TZ_CONTEXT_H diff --git a/lib/main/pico-sdk/rp2_common/cmsis/stub/CMSIS/Device/RP2040/Include/RP2040.h b/lib/main/pico-sdk/rp2_common/cmsis/stub/CMSIS/Device/RP2040/Include/RP2040.h deleted file mode 100644 index 8da431fae2..0000000000 --- a/lib/main/pico-sdk/rp2_common/cmsis/stub/CMSIS/Device/RP2040/Include/RP2040.h +++ /dev/null @@ -1,2673 +0,0 @@ -/* - * Copyright (c) 2024 Raspberry Pi Ltd. SPDX-License-Identifier: BSD-3-Clause - * - * @file src/rp2_common/cmsis/stub/CMSIS/Device/RP2040/Include/RP2040.h - * @brief CMSIS HeaderFile - * @version 0.1 - * @date Tue Aug 6 18:22:05 2024 - * @note Generated by SVDConv V3.3.47 - * from File 'src/rp2_common/cmsis/../../rp2040/hardware_regs/RP2040.svd', - * last modified on Tue Aug 6 17:58:50 2024 - */ - - -/** @addtogroup Raspberry Pi - * @{ - */ - - -/** @addtogroup RP2040 - * @{ - */ - - -#ifndef RP2040_H -#define RP2040_H - -#ifdef __cplusplus -extern "C" { -#endif - - -/** @addtogroup Configuration_of_CMSIS - * @{ - */ - - - -/* =========================================================================================================================== */ -/* ================ Interrupt Number Definition ================ */ -/* =========================================================================================================================== */ - -typedef enum { -/* ======================================= ARM Cortex-M0+ Specific Interrupt Numbers ======================================= */ - Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ - NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ - HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ - SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ - PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ - SysTick_IRQn = -1, /*!< -1 System Tick Timer */ -/* =========================================== RP2040 Specific Interrupt Numbers =========================================== */ - TIMER_IRQ_0_IRQn = 0, /*!< 0 TIMER_IRQ_0 */ - TIMER_IRQ_1_IRQn = 1, /*!< 1 TIMER_IRQ_1 */ - TIMER_IRQ_2_IRQn = 2, /*!< 2 TIMER_IRQ_2 */ - TIMER_IRQ_3_IRQn = 3, /*!< 3 TIMER_IRQ_3 */ - PWM_IRQ_WRAP_IRQn = 4, /*!< 4 PWM_IRQ_WRAP */ - USBCTRL_IRQ_IRQn = 5, /*!< 5 USBCTRL_IRQ */ - XIP_IRQ_IRQn = 6, /*!< 6 XIP_IRQ */ - PIO0_IRQ_0_IRQn = 7, /*!< 7 PIO0_IRQ_0 */ - PIO0_IRQ_1_IRQn = 8, /*!< 8 PIO0_IRQ_1 */ - PIO1_IRQ_0_IRQn = 9, /*!< 9 PIO1_IRQ_0 */ - PIO1_IRQ_1_IRQn = 10, /*!< 10 PIO1_IRQ_1 */ - DMA_IRQ_0_IRQn = 11, /*!< 11 DMA_IRQ_0 */ - DMA_IRQ_1_IRQn = 12, /*!< 12 DMA_IRQ_1 */ - IO_IRQ_BANK0_IRQn = 13, /*!< 13 IO_IRQ_BANK0 */ - IO_IRQ_QSPI_IRQn = 14, /*!< 14 IO_IRQ_QSPI */ - SIO_IRQ_PROC0_IRQn = 15, /*!< 15 SIO_IRQ_PROC0 */ - SIO_IRQ_PROC1_IRQn = 16, /*!< 16 SIO_IRQ_PROC1 */ - CLOCKS_IRQ_IRQn = 17, /*!< 17 CLOCKS_IRQ */ - SPI0_IRQ_IRQn = 18, /*!< 18 SPI0_IRQ */ - SPI1_IRQ_IRQn = 19, /*!< 19 SPI1_IRQ */ - UART0_IRQ_IRQn = 20, /*!< 20 UART0_IRQ */ - UART1_IRQ_IRQn = 21, /*!< 21 UART1_IRQ */ - ADC_IRQ_FIFO_IRQn = 22, /*!< 22 ADC_IRQ_FIFO */ - I2C0_IRQ_IRQn = 23, /*!< 23 I2C0_IRQ */ - I2C1_IRQ_IRQn = 24, /*!< 24 I2C1_IRQ */ - RTC_IRQ_IRQn = 25 /*!< 25 RTC_IRQ */ -} IRQn_Type; - - - -/* =========================================================================================================================== */ -/* ================ Processor and Core Peripheral Section ================ */ -/* =========================================================================================================================== */ - -/* ========================== Configuration of the ARM Cortex-M0+ Processor and Core Peripherals =========================== */ -#define __CM0PLUS_REV 0x0001U /*!< CM0PLUS Core Revision */ -#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ -#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ -#define __MPU_PRESENT 1 /*!< MPU present */ -#define __FPU_PRESENT 0 /*!< FPU present */ - - -/** @} */ /* End of group Configuration_of_CMSIS */ - -#include "core_cm0plus.h" /*!< ARM Cortex-M0+ processor and core peripherals */ -#include "system_RP2040.h" /*!< RP2040 System */ - -#ifndef __IM /*!< Fallback for older CMSIS versions */ - #define __IM __I -#endif -#ifndef __OM /*!< Fallback for older CMSIS versions */ - #define __OM __O -#endif -#ifndef __IOM /*!< Fallback for older CMSIS versions */ - #define __IOM __IO -#endif - - -/* =========================================================================================================================== */ -/* ================ Device Specific Peripheral Section ================ */ -/* =========================================================================================================================== */ - - -/** @addtogroup Device_Peripheral_peripherals - * @{ - */ - - - -/* =========================================================================================================================== */ -/* ================ RESETS ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief RESETS (RESETS) - */ - -typedef struct { /*!< RESETS Structure */ - __IOM uint32_t RESET; /*!< Reset control. If a bit is set it means the peripheral is in - reset. 0 means the peripheral's reset is deasserted. */ - __IOM uint32_t WDSEL; /*!< Watchdog select. If a bit is set then the watchdog will reset - this peripheral when the watchdog fires. */ - __IOM uint32_t RESET_DONE; /*!< Reset done. If a bit is set then a reset done signal has been - returned by the peripheral. This indicates that the peripheral's - registers are ready to be accessed. */ -} RESETS_Type; /*!< Size = 12 (0xc) */ - - - -/* =========================================================================================================================== */ -/* ================ PSM ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief PSM (PSM) - */ - -typedef struct { /*!< PSM Structure */ - __IOM uint32_t FRCE_ON; /*!< Force block out of reset (i.e. power it on) */ - __IOM uint32_t FRCE_OFF; /*!< Force into reset (i.e. power it off) */ - __IOM uint32_t WDSEL; /*!< Set to 1 if this peripheral should be reset when the watchdog - fires. */ - __IOM uint32_t DONE; /*!< Indicates the peripheral's registers are ready to access. */ -} PSM_Type; /*!< Size = 16 (0x10) */ - - - -/* =========================================================================================================================== */ -/* ================ CLOCKS ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief CLOCKS (CLOCKS) - */ - -typedef struct { /*!< CLOCKS Structure */ - __IOM uint32_t CLK_GPOUT0_CTRL; /*!< Clock control, can be changed on-the-fly (except for auxsrc) */ - __IOM uint32_t CLK_GPOUT0_DIV; /*!< Clock divisor, can be changed on-the-fly */ - __IOM uint32_t CLK_GPOUT0_SELECTED; /*!< Indicates which SRC is currently selected by the glitchless - mux (one-hot). */ - __IOM uint32_t CLK_GPOUT1_CTRL; /*!< Clock control, can be changed on-the-fly (except for auxsrc) */ - __IOM uint32_t CLK_GPOUT1_DIV; /*!< Clock divisor, can be changed on-the-fly */ - __IOM uint32_t CLK_GPOUT1_SELECTED; /*!< Indicates which SRC is currently selected by the glitchless - mux (one-hot). */ - __IOM uint32_t CLK_GPOUT2_CTRL; /*!< Clock control, can be changed on-the-fly (except for auxsrc) */ - __IOM uint32_t CLK_GPOUT2_DIV; /*!< Clock divisor, can be changed on-the-fly */ - __IOM uint32_t CLK_GPOUT2_SELECTED; /*!< Indicates which SRC is currently selected by the glitchless - mux (one-hot). */ - __IOM uint32_t CLK_GPOUT3_CTRL; /*!< Clock control, can be changed on-the-fly (except for auxsrc) */ - __IOM uint32_t CLK_GPOUT3_DIV; /*!< Clock divisor, can be changed on-the-fly */ - __IOM uint32_t CLK_GPOUT3_SELECTED; /*!< Indicates which SRC is currently selected by the glitchless - mux (one-hot). */ - __IOM uint32_t CLK_REF_CTRL; /*!< Clock control, can be changed on-the-fly (except for auxsrc) */ - __IOM uint32_t CLK_REF_DIV; /*!< Clock divisor, can be changed on-the-fly */ - __IOM uint32_t CLK_REF_SELECTED; /*!< Indicates which SRC is currently selected by the glitchless - mux (one-hot). */ - __IOM uint32_t CLK_SYS_CTRL; /*!< Clock control, can be changed on-the-fly (except for auxsrc) */ - __IOM uint32_t CLK_SYS_DIV; /*!< Clock divisor, can be changed on-the-fly */ - __IOM uint32_t CLK_SYS_SELECTED; /*!< Indicates which SRC is currently selected by the glitchless - mux (one-hot). */ - __IOM uint32_t CLK_PERI_CTRL; /*!< Clock control, can be changed on-the-fly (except for auxsrc) */ - __IOM uint32_t CLK_PERI_DIV; /*!< Clock divisor, can be changed on-the-fly */ - __IOM uint32_t CLK_PERI_SELECTED; /*!< Indicates which SRC is currently selected by the glitchless - mux (one-hot). */ - __IOM uint32_t CLK_USB_CTRL; /*!< Clock control, can be changed on-the-fly (except for auxsrc) */ - __IOM uint32_t CLK_USB_DIV; /*!< Clock divisor, can be changed on-the-fly */ - __IOM uint32_t CLK_USB_SELECTED; /*!< Indicates which SRC is currently selected by the glitchless - mux (one-hot). */ - __IOM uint32_t CLK_ADC_CTRL; /*!< Clock control, can be changed on-the-fly (except for auxsrc) */ - __IOM uint32_t CLK_ADC_DIV; /*!< Clock divisor, can be changed on-the-fly */ - __IOM uint32_t CLK_ADC_SELECTED; /*!< Indicates which SRC is currently selected by the glitchless - mux (one-hot). */ - __IOM uint32_t CLK_RTC_CTRL; /*!< Clock control, can be changed on-the-fly (except for auxsrc) */ - __IOM uint32_t CLK_RTC_DIV; /*!< Clock divisor, can be changed on-the-fly */ - __IOM uint32_t CLK_RTC_SELECTED; /*!< Indicates which SRC is currently selected by the glitchless - mux (one-hot). */ - __IOM uint32_t CLK_SYS_RESUS_CTRL; /*!< CLK_SYS_RESUS_CTRL */ - __IOM uint32_t CLK_SYS_RESUS_STATUS; /*!< CLK_SYS_RESUS_STATUS */ - __IOM uint32_t FC0_REF_KHZ; /*!< Reference clock frequency in kHz */ - __IOM uint32_t FC0_MIN_KHZ; /*!< Minimum pass frequency in kHz. This is optional. Set to 0 if - you are not using the pass/fail flags */ - __IOM uint32_t FC0_MAX_KHZ; /*!< Maximum pass frequency in kHz. This is optional. Set to 0x1ffffff - if you are not using the pass/fail flags */ - __IOM uint32_t FC0_DELAY; /*!< Delays the start of frequency counting to allow the mux to settle - Delay is measured in multiples of the reference clock period */ - __IOM uint32_t FC0_INTERVAL; /*!< The test interval is 0.98us * 2**interval, but let's call it - 1us * 2**interval The default gives a test interval of - 250us */ - __IOM uint32_t FC0_SRC; /*!< Clock sent to frequency counter, set to 0 when not required - Writing to this register initiates the frequency count */ - __IOM uint32_t FC0_STATUS; /*!< Frequency counter status */ - __IOM uint32_t FC0_RESULT; /*!< Result of frequency measurement, only valid when status_done=1 */ - __IOM uint32_t WAKE_EN0; /*!< enable clock in wake mode */ - __IOM uint32_t WAKE_EN1; /*!< enable clock in wake mode */ - __IOM uint32_t SLEEP_EN0; /*!< enable clock in sleep mode */ - __IOM uint32_t SLEEP_EN1; /*!< enable clock in sleep mode */ - __IOM uint32_t ENABLED0; /*!< indicates the state of the clock enable */ - __IOM uint32_t ENABLED1; /*!< indicates the state of the clock enable */ - __IOM uint32_t INTR; /*!< Raw Interrupts */ - __IOM uint32_t INTE; /*!< Interrupt Enable */ - __IOM uint32_t INTF; /*!< Interrupt Force */ - __IOM uint32_t INTS; /*!< Interrupt status after masking & forcing */ -} CLOCKS_Type; /*!< Size = 200 (0xc8) */ - - - -/* =========================================================================================================================== */ -/* ================ PADS_BANK0 ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief PADS_BANK0 (PADS_BANK0) - */ - -typedef struct { /*!< PADS_BANK0 Structure */ - __IOM uint32_t VOLTAGE_SELECT; /*!< Voltage select. Per bank control */ - __IOM uint32_t GPIO0; /*!< Pad control register */ - __IOM uint32_t GPIO1; /*!< Pad control register */ - __IOM uint32_t GPIO2; /*!< Pad control register */ - __IOM uint32_t GPIO3; /*!< Pad control register */ - __IOM uint32_t GPIO4; /*!< Pad control register */ - __IOM uint32_t GPIO5; /*!< Pad control register */ - __IOM uint32_t GPIO6; /*!< Pad control register */ - __IOM uint32_t GPIO7; /*!< Pad control register */ - __IOM uint32_t GPIO8; /*!< Pad control register */ - __IOM uint32_t GPIO9; /*!< Pad control register */ - __IOM uint32_t GPIO10; /*!< Pad control register */ - __IOM uint32_t GPIO11; /*!< Pad control register */ - __IOM uint32_t GPIO12; /*!< Pad control register */ - __IOM uint32_t GPIO13; /*!< Pad control register */ - __IOM uint32_t GPIO14; /*!< Pad control register */ - __IOM uint32_t GPIO15; /*!< Pad control register */ - __IOM uint32_t GPIO16; /*!< Pad control register */ - __IOM uint32_t GPIO17; /*!< Pad control register */ - __IOM uint32_t GPIO18; /*!< Pad control register */ - __IOM uint32_t GPIO19; /*!< Pad control register */ - __IOM uint32_t GPIO20; /*!< Pad control register */ - __IOM uint32_t GPIO21; /*!< Pad control register */ - __IOM uint32_t GPIO22; /*!< Pad control register */ - __IOM uint32_t GPIO23; /*!< Pad control register */ - __IOM uint32_t GPIO24; /*!< Pad control register */ - __IOM uint32_t GPIO25; /*!< Pad control register */ - __IOM uint32_t GPIO26; /*!< Pad control register */ - __IOM uint32_t GPIO27; /*!< Pad control register */ - __IOM uint32_t GPIO28; /*!< Pad control register */ - __IOM uint32_t GPIO29; /*!< Pad control register */ - __IOM uint32_t SWCLK; /*!< Pad control register */ - __IOM uint32_t SWD; /*!< Pad control register */ -} PADS_BANK0_Type; /*!< Size = 132 (0x84) */ - - - -/* =========================================================================================================================== */ -/* ================ PADS_QSPI ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief PADS_QSPI (PADS_QSPI) - */ - -typedef struct { /*!< PADS_QSPI Structure */ - __IOM uint32_t VOLTAGE_SELECT; /*!< Voltage select. Per bank control */ - __IOM uint32_t GPIO_QSPI_SCLK; /*!< Pad control register */ - __IOM uint32_t GPIO_QSPI_SD0; /*!< Pad control register */ - __IOM uint32_t GPIO_QSPI_SD1; /*!< Pad control register */ - __IOM uint32_t GPIO_QSPI_SD2; /*!< Pad control register */ - __IOM uint32_t GPIO_QSPI_SD3; /*!< Pad control register */ - __IOM uint32_t GPIO_QSPI_SS; /*!< Pad control register */ -} PADS_QSPI_Type; /*!< Size = 28 (0x1c) */ - - - -/* =========================================================================================================================== */ -/* ================ IO_QSPI ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief IO_QSPI (IO_QSPI) - */ - -typedef struct { /*!< IO_QSPI Structure */ - __IOM uint32_t GPIO_QSPI_SCLK_STATUS; /*!< GPIO status */ - __IOM uint32_t GPIO_QSPI_SCLK_CTRL; /*!< GPIO control including function select and overrides. */ - __IOM uint32_t GPIO_QSPI_SS_STATUS; /*!< GPIO status */ - __IOM uint32_t GPIO_QSPI_SS_CTRL; /*!< GPIO control including function select and overrides. */ - __IOM uint32_t GPIO_QSPI_SD0_STATUS; /*!< GPIO status */ - __IOM uint32_t GPIO_QSPI_SD0_CTRL; /*!< GPIO control including function select and overrides. */ - __IOM uint32_t GPIO_QSPI_SD1_STATUS; /*!< GPIO status */ - __IOM uint32_t GPIO_QSPI_SD1_CTRL; /*!< GPIO control including function select and overrides. */ - __IOM uint32_t GPIO_QSPI_SD2_STATUS; /*!< GPIO status */ - __IOM uint32_t GPIO_QSPI_SD2_CTRL; /*!< GPIO control including function select and overrides. */ - __IOM uint32_t GPIO_QSPI_SD3_STATUS; /*!< GPIO status */ - __IOM uint32_t GPIO_QSPI_SD3_CTRL; /*!< GPIO control including function select and overrides. */ - __IOM uint32_t INTR; /*!< Raw Interrupts */ - __IOM uint32_t PROC0_INTE; /*!< Interrupt Enable for proc0 */ - __IOM uint32_t PROC0_INTF; /*!< Interrupt Force for proc0 */ - __IOM uint32_t PROC0_INTS; /*!< Interrupt status after masking & forcing for proc0 */ - __IOM uint32_t PROC1_INTE; /*!< Interrupt Enable for proc1 */ - __IOM uint32_t PROC1_INTF; /*!< Interrupt Force for proc1 */ - __IOM uint32_t PROC1_INTS; /*!< Interrupt status after masking & forcing for proc1 */ - __IOM uint32_t DORMANT_WAKE_INTE; /*!< Interrupt Enable for dormant_wake */ - __IOM uint32_t DORMANT_WAKE_INTF; /*!< Interrupt Force for dormant_wake */ - __IOM uint32_t DORMANT_WAKE_INTS; /*!< Interrupt status after masking & forcing for dormant_wake */ -} IO_QSPI_Type; /*!< Size = 88 (0x58) */ - - - -/* =========================================================================================================================== */ -/* ================ IO_BANK0 ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief IO_BANK0 (IO_BANK0) - */ - -typedef struct { /*!< IO_BANK0 Structure */ - __IOM uint32_t GPIO0_STATUS; /*!< GPIO status */ - __IOM uint32_t GPIO0_CTRL; /*!< GPIO control including function select and overrides. */ - __IOM uint32_t GPIO1_STATUS; /*!< GPIO status */ - __IOM uint32_t GPIO1_CTRL; /*!< GPIO control including function select and overrides. */ - __IOM uint32_t GPIO2_STATUS; /*!< GPIO status */ - __IOM uint32_t GPIO2_CTRL; /*!< GPIO control including function select and overrides. */ - __IOM uint32_t GPIO3_STATUS; /*!< GPIO status */ - __IOM uint32_t GPIO3_CTRL; /*!< GPIO control including function select and overrides. */ - __IOM uint32_t GPIO4_STATUS; /*!< GPIO status */ - __IOM uint32_t GPIO4_CTRL; /*!< GPIO control including function select and overrides. */ - __IOM uint32_t GPIO5_STATUS; /*!< GPIO status */ - __IOM uint32_t GPIO5_CTRL; /*!< GPIO control including function select and overrides. */ - __IOM uint32_t GPIO6_STATUS; /*!< GPIO status */ - __IOM uint32_t GPIO6_CTRL; /*!< GPIO control including function select and overrides. */ - __IOM uint32_t GPIO7_STATUS; /*!< GPIO status */ - __IOM uint32_t GPIO7_CTRL; /*!< GPIO control including function select and overrides. */ - __IOM uint32_t GPIO8_STATUS; /*!< GPIO status */ - __IOM uint32_t GPIO8_CTRL; /*!< GPIO control including function select and overrides. */ - __IOM uint32_t GPIO9_STATUS; /*!< GPIO status */ - __IOM uint32_t GPIO9_CTRL; /*!< GPIO control including function select and overrides. */ - __IOM uint32_t GPIO10_STATUS; /*!< GPIO status */ - __IOM uint32_t GPIO10_CTRL; /*!< GPIO control including function select and overrides. */ - __IOM uint32_t GPIO11_STATUS; /*!< GPIO status */ - __IOM uint32_t GPIO11_CTRL; /*!< GPIO control including function select and overrides. */ - __IOM uint32_t GPIO12_STATUS; /*!< GPIO status */ - __IOM uint32_t GPIO12_CTRL; /*!< GPIO control including function select and overrides. */ - __IOM uint32_t GPIO13_STATUS; /*!< GPIO status */ - __IOM uint32_t GPIO13_CTRL; /*!< GPIO control including function select and overrides. */ - __IOM uint32_t GPIO14_STATUS; /*!< GPIO status */ - __IOM uint32_t GPIO14_CTRL; /*!< GPIO control including function select and overrides. */ - __IOM uint32_t GPIO15_STATUS; /*!< GPIO status */ - __IOM uint32_t GPIO15_CTRL; /*!< GPIO control including function select and overrides. */ - __IOM uint32_t GPIO16_STATUS; /*!< GPIO status */ - __IOM uint32_t GPIO16_CTRL; /*!< GPIO control including function select and overrides. */ - __IOM uint32_t GPIO17_STATUS; /*!< GPIO status */ - __IOM uint32_t GPIO17_CTRL; /*!< GPIO control including function select and overrides. */ - __IOM uint32_t GPIO18_STATUS; /*!< GPIO status */ - __IOM uint32_t GPIO18_CTRL; /*!< GPIO control including function select and overrides. */ - __IOM uint32_t GPIO19_STATUS; /*!< GPIO status */ - __IOM uint32_t GPIO19_CTRL; /*!< GPIO control including function select and overrides. */ - __IOM uint32_t GPIO20_STATUS; /*!< GPIO status */ - __IOM uint32_t GPIO20_CTRL; /*!< GPIO control including function select and overrides. */ - __IOM uint32_t GPIO21_STATUS; /*!< GPIO status */ - __IOM uint32_t GPIO21_CTRL; /*!< GPIO control including function select and overrides. */ - __IOM uint32_t GPIO22_STATUS; /*!< GPIO status */ - __IOM uint32_t GPIO22_CTRL; /*!< GPIO control including function select and overrides. */ - __IOM uint32_t GPIO23_STATUS; /*!< GPIO status */ - __IOM uint32_t GPIO23_CTRL; /*!< GPIO control including function select and overrides. */ - __IOM uint32_t GPIO24_STATUS; /*!< GPIO status */ - __IOM uint32_t GPIO24_CTRL; /*!< GPIO control including function select and overrides. */ - __IOM uint32_t GPIO25_STATUS; /*!< GPIO status */ - __IOM uint32_t GPIO25_CTRL; /*!< GPIO control including function select and overrides. */ - __IOM uint32_t GPIO26_STATUS; /*!< GPIO status */ - __IOM uint32_t GPIO26_CTRL; /*!< GPIO control including function select and overrides. */ - __IOM uint32_t GPIO27_STATUS; /*!< GPIO status */ - __IOM uint32_t GPIO27_CTRL; /*!< GPIO control including function select and overrides. */ - __IOM uint32_t GPIO28_STATUS; /*!< GPIO status */ - __IOM uint32_t GPIO28_CTRL; /*!< GPIO control including function select and overrides. */ - __IOM uint32_t GPIO29_STATUS; /*!< GPIO status */ - __IOM uint32_t GPIO29_CTRL; /*!< GPIO control including function select and overrides. */ - __IOM uint32_t INTR0; /*!< Raw Interrupts */ - __IOM uint32_t INTR1; /*!< Raw Interrupts */ - __IOM uint32_t INTR2; /*!< Raw Interrupts */ - __IOM uint32_t INTR3; /*!< Raw Interrupts */ - __IOM uint32_t PROC0_INTE0; /*!< Interrupt Enable for proc0 */ - __IOM uint32_t PROC0_INTE1; /*!< Interrupt Enable for proc0 */ - __IOM uint32_t PROC0_INTE2; /*!< Interrupt Enable for proc0 */ - __IOM uint32_t PROC0_INTE3; /*!< Interrupt Enable for proc0 */ - __IOM uint32_t PROC0_INTF0; /*!< Interrupt Force for proc0 */ - __IOM uint32_t PROC0_INTF1; /*!< Interrupt Force for proc0 */ - __IOM uint32_t PROC0_INTF2; /*!< Interrupt Force for proc0 */ - __IOM uint32_t PROC0_INTF3; /*!< Interrupt Force for proc0 */ - __IOM uint32_t PROC0_INTS0; /*!< Interrupt status after masking & forcing for proc0 */ - __IOM uint32_t PROC0_INTS1; /*!< Interrupt status after masking & forcing for proc0 */ - __IOM uint32_t PROC0_INTS2; /*!< Interrupt status after masking & forcing for proc0 */ - __IOM uint32_t PROC0_INTS3; /*!< Interrupt status after masking & forcing for proc0 */ - __IOM uint32_t PROC1_INTE0; /*!< Interrupt Enable for proc1 */ - __IOM uint32_t PROC1_INTE1; /*!< Interrupt Enable for proc1 */ - __IOM uint32_t PROC1_INTE2; /*!< Interrupt Enable for proc1 */ - __IOM uint32_t PROC1_INTE3; /*!< Interrupt Enable for proc1 */ - __IOM uint32_t PROC1_INTF0; /*!< Interrupt Force for proc1 */ - __IOM uint32_t PROC1_INTF1; /*!< Interrupt Force for proc1 */ - __IOM uint32_t PROC1_INTF2; /*!< Interrupt Force for proc1 */ - __IOM uint32_t PROC1_INTF3; /*!< Interrupt Force for proc1 */ - __IOM uint32_t PROC1_INTS0; /*!< Interrupt status after masking & forcing for proc1 */ - __IOM uint32_t PROC1_INTS1; /*!< Interrupt status after masking & forcing for proc1 */ - __IOM uint32_t PROC1_INTS2; /*!< Interrupt status after masking & forcing for proc1 */ - __IOM uint32_t PROC1_INTS3; /*!< Interrupt status after masking & forcing for proc1 */ - __IOM uint32_t DORMANT_WAKE_INTE0; /*!< Interrupt Enable for dormant_wake */ - __IOM uint32_t DORMANT_WAKE_INTE1; /*!< Interrupt Enable for dormant_wake */ - __IOM uint32_t DORMANT_WAKE_INTE2; /*!< Interrupt Enable for dormant_wake */ - __IOM uint32_t DORMANT_WAKE_INTE3; /*!< Interrupt Enable for dormant_wake */ - __IOM uint32_t DORMANT_WAKE_INTF0; /*!< Interrupt Force for dormant_wake */ - __IOM uint32_t DORMANT_WAKE_INTF1; /*!< Interrupt Force for dormant_wake */ - __IOM uint32_t DORMANT_WAKE_INTF2; /*!< Interrupt Force for dormant_wake */ - __IOM uint32_t DORMANT_WAKE_INTF3; /*!< Interrupt Force for dormant_wake */ - __IOM uint32_t DORMANT_WAKE_INTS0; /*!< Interrupt status after masking & forcing for dormant_wake */ - __IOM uint32_t DORMANT_WAKE_INTS1; /*!< Interrupt status after masking & forcing for dormant_wake */ - __IOM uint32_t DORMANT_WAKE_INTS2; /*!< Interrupt status after masking & forcing for dormant_wake */ - __IOM uint32_t DORMANT_WAKE_INTS3; /*!< Interrupt status after masking & forcing for dormant_wake */ -} IO_BANK0_Type; /*!< Size = 400 (0x190) */ - - - -/* =========================================================================================================================== */ -/* ================ SYSINFO ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief SYSINFO (SYSINFO) - */ - -typedef struct { /*!< SYSINFO Structure */ - __IOM uint32_t CHIP_ID; /*!< JEDEC JEP-106 compliant chip identifier. */ - __IOM uint32_t PLATFORM; /*!< Platform register. Allows software to know what environment - it is running in. */ - __IM uint32_t RESERVED[2]; - __IOM uint32_t GITREF_RP2040; /*!< Git hash of the chip source. Used to identify chip version. */ -} SYSINFO_Type; /*!< Size = 20 (0x14) */ - - - -/* =========================================================================================================================== */ -/* ================ PPB ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief PPB (PPB) - */ - -typedef struct { /*!< PPB Structure */ - __IM uint32_t RESERVED[14340]; - __IOM uint32_t SYST_CSR; /*!< Use the SysTick Control and Status Register to enable the SysTick - features. */ - __IOM uint32_t SYST_RVR; /*!< Use the SysTick Reload Value Register to specify the start value - to load into the current value register when the counter - reaches 0. It can be any value between 0 and 0x00FFFFFF. - A start value of 0 is possible, but has no effect because - the SysTick interrupt and COUNTFLAG are activated when - counting from 1 to 0. The reset value of this register - is UNKNOWN. To generate a multi-shot timer with a period - of N processor clock cycles, use a RELOAD value of N-1. - For example, if the SysTick interrupt is required every - 100 clock pulses, set RELOAD to 99. */ - __IOM uint32_t SYST_CVR; /*!< Use the SysTick Current Value Register to find the current value - in the register. The reset value of this register is UNKNOWN. */ - __IOM uint32_t SYST_CALIB; /*!< Use the SysTick Calibration Value Register to enable software - to scale to any required speed using divide and multiply. */ - __IM uint32_t RESERVED1[56]; - __IOM uint32_t NVIC_ISER; /*!< Use the Interrupt Set-Enable Register to enable interrupts and - determine which interrupts are currently enabled. If a - pending interrupt is enabled, the NVIC activates the interrupt - based on its priority. If an interrupt is not enabled, - asserting its interrupt signal changes the interrupt state - to pending, but the NVIC never activates the interrupt, - regardless of its priority. */ - __IM uint32_t RESERVED2[31]; - __IOM uint32_t NVIC_ICER; /*!< Use the Interrupt Clear-Enable Registers to disable interrupts - and determine which interrupts are currently enabled. */ - __IM uint32_t RESERVED3[31]; - __IOM uint32_t NVIC_ISPR; /*!< The NVIC_ISPR forces interrupts into the pending state, and - shows which interrupts are pending. */ - __IM uint32_t RESERVED4[31]; - __IOM uint32_t NVIC_ICPR; /*!< Use the Interrupt Clear-Pending Register to clear pending interrupts - and determine which interrupts are currently pending. */ - __IM uint32_t RESERVED5[95]; - __IOM uint32_t NVIC_IPR0; /*!< Use the Interrupt Priority Registers to assign a priority from - 0 to 3 to each of the available interrupts. 0 is the highest - priority, and 3 is the lowest. Note: Writing 1 to an NVIC_ICPR - bit does not affect the active state of the corresponding - interrupt. These registers are only word-accessible */ - __IOM uint32_t NVIC_IPR1; /*!< Use the Interrupt Priority Registers to assign a priority from - 0 to 3 to each of the available interrupts. 0 is the highest - priority, and 3 is the lowest. */ - __IOM uint32_t NVIC_IPR2; /*!< Use the Interrupt Priority Registers to assign a priority from - 0 to 3 to each of the available interrupts. 0 is the highest - priority, and 3 is the lowest. */ - __IOM uint32_t NVIC_IPR3; /*!< Use the Interrupt Priority Registers to assign a priority from - 0 to 3 to each of the available interrupts. 0 is the highest - priority, and 3 is the lowest. */ - __IOM uint32_t NVIC_IPR4; /*!< Use the Interrupt Priority Registers to assign a priority from - 0 to 3 to each of the available interrupts. 0 is the highest - priority, and 3 is the lowest. */ - __IOM uint32_t NVIC_IPR5; /*!< Use the Interrupt Priority Registers to assign a priority from - 0 to 3 to each of the available interrupts. 0 is the highest - priority, and 3 is the lowest. */ - __IOM uint32_t NVIC_IPR6; /*!< Use the Interrupt Priority Registers to assign a priority from - 0 to 3 to each of the available interrupts. 0 is the highest - priority, and 3 is the lowest. */ - __IOM uint32_t NVIC_IPR7; /*!< Use the Interrupt Priority Registers to assign a priority from - 0 to 3 to each of the available interrupts. 0 is the highest - priority, and 3 is the lowest. */ - __IM uint32_t RESERVED6[568]; - __IOM uint32_t CPUID; /*!< Read the CPU ID Base Register to determine: the ID number of - the processor core, the version number of the processor - core, the implementation details of the processor core. */ - __IOM uint32_t ICSR; /*!< Use the Interrupt Control State Register to set a pending Non-Maskable - Interrupt (NMI), set or clear a pending PendSV, set or - clear a pending SysTick, check for pending exceptions, - check the vector number of the highest priority pended - exception, check the vector number of the active exception. */ - __IOM uint32_t VTOR; /*!< The VTOR holds the vector table offset address. */ - __IOM uint32_t AIRCR; /*!< Use the Application Interrupt and Reset Control Register to: - determine data endianness, clear all active state information - from debug halt mode, request a system reset. */ - __IOM uint32_t SCR; /*!< System Control Register. Use the System Control Register for - power-management functions: signal to the system when the - processor can enter a low power state, control how the - processor enters and exits low power states. */ - __IOM uint32_t CCR; /*!< The Configuration and Control Register permanently enables stack - alignment and causes unaligned accesses to result in a - Hard Fault. */ - __IM uint32_t RESERVED7; - __IOM uint32_t SHPR2; /*!< System handlers are a special class of exception handler that - can have their priority set to any of the priority levels. - Use the System Handler Priority Register 2 to set the priority - of SVCall. */ - __IOM uint32_t SHPR3; /*!< System handlers are a special class of exception handler that - can have their priority set to any of the priority levels. - Use the System Handler Priority Register 3 to set the priority - of PendSV and SysTick. */ - __IOM uint32_t SHCSR; /*!< Use the System Handler Control and State Register to determine - or clear the pending status of SVCall. */ - __IM uint32_t RESERVED8[26]; - __IOM uint32_t MPU_TYPE; /*!< Read the MPU Type Register to determine if the processor implements - an MPU, and how many regions the MPU supports. */ - __IOM uint32_t MPU_CTRL; /*!< Use the MPU Control Register to enable and disable the MPU, - and to control whether the default memory map is enabled - as a background region for privileged accesses, and whether - the MPU is enabled for HardFaults and NMIs. */ - __IOM uint32_t MPU_RNR; /*!< Use the MPU Region Number Register to select the region currently - accessed by MPU_RBAR and MPU_RASR. */ - __IOM uint32_t MPU_RBAR; /*!< Read the MPU Region Base Address Register to determine the base - address of the region identified by MPU_RNR. Write to update - the base address of said region or that of a specified - region, with whose number MPU_RNR will also be updated. */ - __IOM uint32_t MPU_RASR; /*!< Use the MPU Region Attribute and Size Register to define the - size, access behaviour and memory type of the region identified - by MPU_RNR, and enable that region. */ -} PPB_Type; /*!< Size = 60836 (0xeda4) */ - - - -/* =========================================================================================================================== */ -/* ================ SSI ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief DW_apb_ssi has the following features: - * APB interface – Allows for easy integration into a DesignWare Synthesizable Components for AMBA 2 implementation. - * APB3 and APB4 protocol support. - * Scalable APB data bus width – Supports APB data bus widths of 8, 16, and 32 bits. - * Serial-master or serial-slave operation – Enables serial communication with serial-master or serial-slave peripheral devices. - * Programmable Dual/Quad/Octal SPI support in Master Mode. - * Dual Data Rate (DDR) and Read Data Strobe (RDS) Support - Enables the DW_apb_ssi master to perform operations with the device in DDR and RDS modes when working in Dual/Quad/Octal mode of operation. - * Data Mask Support - Enables the DW_apb_ssi to selectively update the bytes in the device. This feature is applicable only in enhanced SPI modes. - * eXecute-In-Place (XIP) support - Enables the DW_apb_ssi master to behave as a memory mapped I/O and fetches the data from the device based on the APB read request. This feature is applicable only in enhanced SPI modes. - * DMA Controller Interface – Enables the DW_apb_ssi to interface to a DMA controller over the bus using a handshaking interface for transfer requests. - * Independent masking of interrupts – Master collision, transmit FIFO overflow, transmit FIFO empty, receive FIFO full, receive FIFO underflow, and receive FIFO overflow interrupts can all be masked independently. - * Multi-master contention detection – Informs the processor of multiple serial-master accesses on the serial bus. - * Bypass of meta-stability flip-flops for synchronous clocks – When the APB clock (pclk) and the DW_apb_ssi serial clock (ssi_clk) are synchronous, meta-stable flip-flops are not used when transferring control signals across these clock domains. - * Programmable delay on the sample time of the received serial data bit (rxd); enables programmable control of routing delays resulting in higher serial data-bit rates. - * Programmable features: - - Serial interface operation – Choice of Motorola SPI, Texas Instruments Synchronous Serial Protocol or National Semiconductor Microwire. - - Clock bit-rate – Dynamic control of the serial bit rate of the data transfer; used in only serial-master mode of operation. - - Data Item size (4 to 32 bits) – Item size of each data transfer under the control of the programmer. - * Configured features: - - FIFO depth – 16 words deep. The FIFO width is fixed at 32 bits. - - 1 slave select output. - - Hardware slave-select – Dedicated hardware slave-select line. - - Combined interrupt line - one combined interrupt line from the DW_apb_ssi to the interrupt controller. - - Interrupt polarity – active high interrupt lines. - - Serial clock polarity – low serial-clock polarity directly after reset. - - Serial clock phase – capture on first edge of serial-clock directly after reset. (SSI) - */ - -typedef struct { /*!< SSI Structure */ - __IOM uint32_t CTRLR0; /*!< Control register 0 */ - __IOM uint32_t CTRLR1; /*!< Master Control register 1 */ - __IOM uint32_t SSIENR; /*!< SSI Enable */ - __IOM uint32_t MWCR; /*!< Microwire Control */ - __IOM uint32_t SER; /*!< Slave enable */ - __IOM uint32_t BAUDR; /*!< Baud rate */ - __IOM uint32_t TXFTLR; /*!< TX FIFO threshold level */ - __IOM uint32_t RXFTLR; /*!< RX FIFO threshold level */ - __IOM uint32_t TXFLR; /*!< TX FIFO level */ - __IOM uint32_t RXFLR; /*!< RX FIFO level */ - __IOM uint32_t SR; /*!< Status register */ - __IOM uint32_t IMR; /*!< Interrupt mask */ - __IOM uint32_t ISR; /*!< Interrupt status */ - __IOM uint32_t RISR; /*!< Raw interrupt status */ - __IOM uint32_t TXOICR; /*!< TX FIFO overflow interrupt clear */ - __IOM uint32_t RXOICR; /*!< RX FIFO overflow interrupt clear */ - __IOM uint32_t RXUICR; /*!< RX FIFO underflow interrupt clear */ - __IOM uint32_t MSTICR; /*!< Multi-master interrupt clear */ - __IOM uint32_t ICR; /*!< Interrupt clear */ - __IOM uint32_t DMACR; /*!< DMA control */ - __IOM uint32_t DMATDLR; /*!< DMA TX data level */ - __IOM uint32_t DMARDLR; /*!< DMA RX data level */ - __IOM uint32_t IDR; /*!< Identification register */ - __IOM uint32_t SSI_VERSION_ID; /*!< Version ID */ - __IOM uint32_t DR0; /*!< Data Register 0 (of 36) */ - __IM uint32_t RESERVED[35]; - __IOM uint32_t RX_SAMPLE_DLY; /*!< RX sample delay */ - __IOM uint32_t SPI_CTRLR0; /*!< SPI control */ - __IOM uint32_t TXD_DRIVE_EDGE; /*!< TX drive edge */ -} SSI_Type; /*!< Size = 252 (0xfc) */ - - - -/* =========================================================================================================================== */ -/* ================ XIP_CTRL ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief QSPI flash execute-in-place block (XIP_CTRL) - */ - -typedef struct { /*!< XIP_CTRL Structure */ - __IOM uint32_t CTRL; /*!< Cache control */ - __IOM uint32_t FLUSH; /*!< Cache Flush control */ - __IOM uint32_t STAT; /*!< Cache Status */ - __IOM uint32_t CTR_HIT; /*!< Cache Hit counter */ - __IOM uint32_t CTR_ACC; /*!< Cache Access counter */ - __IOM uint32_t STREAM_ADDR; /*!< FIFO stream address */ - __IOM uint32_t STREAM_CTR; /*!< FIFO stream control */ - __IOM uint32_t STREAM_FIFO; /*!< FIFO stream data */ -} XIP_CTRL_Type; /*!< Size = 32 (0x20) */ - - - -/* =========================================================================================================================== */ -/* ================ SYSCFG ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief Register block for various chip control signals (SYSCFG) - */ - -typedef struct { /*!< SYSCFG Structure */ - __IOM uint32_t PROC0_NMI_MASK; /*!< Processor core 0 NMI source mask */ - __IOM uint32_t PROC1_NMI_MASK; /*!< Processor core 1 NMI source mask */ - __IOM uint32_t PROC_CONFIG; /*!< Configuration for processors */ - __IOM uint32_t PROC_IN_SYNC_BYPASS; /*!< For each bit, if 1, bypass the input synchronizer between that - GPIO and the GPIO input register in the SIO. The input - synchronizers should generally be unbypassed, to avoid - injecting metastabilities into processors. If you're feeling - brave, you can bypass to save two cycles of input latency. - This register applies to GPIO 0...29. */ - __IOM uint32_t PROC_IN_SYNC_BYPASS_HI; /*!< For each bit, if 1, bypass the input synchronizer between that - GPIO and the GPIO input register in the SIO. The input - synchronizers should generally be unbypassed, to avoid - injecting metastabilities into processors. If you're feeling - brave, you can bypass to save two cycles of input latency. - This register applies to GPIO 30...35 (the QSPI IOs). */ - __IOM uint32_t DBGFORCE; /*!< Directly control the SWD debug port of either processor */ - __IOM uint32_t MEMPOWERDOWN; /*!< Control power downs to memories. Set high to power down memories. - Use with extreme caution */ -} SYSCFG_Type; /*!< Size = 28 (0x1c) */ - - - -/* =========================================================================================================================== */ -/* ================ XOSC ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief Controls the crystal oscillator (XOSC) - */ - -typedef struct { /*!< XOSC Structure */ - __IOM uint32_t CTRL; /*!< Crystal Oscillator Control */ - __IOM uint32_t STATUS; /*!< Crystal Oscillator Status */ - __IOM uint32_t DORMANT; /*!< Crystal Oscillator pause control */ - __IOM uint32_t STARTUP; /*!< Controls the startup delay */ - __IM uint32_t RESERVED[3]; - __IOM uint32_t COUNT; /*!< A down counter running at the xosc frequency which counts to - zero and stops. To start the counter write a non-zero value. - Can be used for short software pauses when setting up time - sensitive hardware. */ -} XOSC_Type; /*!< Size = 32 (0x20) */ - - - -/* =========================================================================================================================== */ -/* ================ PLL_SYS ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief PLL_SYS (PLL_SYS) - */ - -typedef struct { /*!< PLL_SYS Structure */ - __IOM uint32_t CS; /*!< Control and Status GENERAL CONSTRAINTS: Reference clock frequency - min=5MHz, max=800MHz Feedback divider min=16, max=320 VCO - frequency min=750MHz, max=1600MHz */ - __IOM uint32_t PWR; /*!< Controls the PLL power modes. */ - __IOM uint32_t FBDIV_INT; /*!< Feedback divisor (note: this PLL does not support fractional - division) */ - __IOM uint32_t PRIM; /*!< Controls the PLL post dividers for the primary output (note: - this PLL does not have a secondary output) the primary - output is driven from VCO divided by postdiv1*postdiv2 */ -} PLL_SYS_Type; /*!< Size = 16 (0x10) */ - - - -/* =========================================================================================================================== */ -/* ================ UART0 ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief UART0 (UART0) - */ - -typedef struct { /*!< UART0 Structure */ - __IOM uint32_t UARTDR; /*!< Data Register, UARTDR */ - __IOM uint32_t UARTRSR; /*!< Receive Status Register/Error Clear Register, UARTRSR/UARTECR */ - __IM uint32_t RESERVED[4]; - __IOM uint32_t UARTFR; /*!< Flag Register, UARTFR */ - __IM uint32_t RESERVED1; - __IOM uint32_t UARTILPR; /*!< IrDA Low-Power Counter Register, UARTILPR */ - __IOM uint32_t UARTIBRD; /*!< Integer Baud Rate Register, UARTIBRD */ - __IOM uint32_t UARTFBRD; /*!< Fractional Baud Rate Register, UARTFBRD */ - __IOM uint32_t UARTLCR_H; /*!< Line Control Register, UARTLCR_H */ - __IOM uint32_t UARTCR; /*!< Control Register, UARTCR */ - __IOM uint32_t UARTIFLS; /*!< Interrupt FIFO Level Select Register, UARTIFLS */ - __IOM uint32_t UARTIMSC; /*!< Interrupt Mask Set/Clear Register, UARTIMSC */ - __IOM uint32_t UARTRIS; /*!< Raw Interrupt Status Register, UARTRIS */ - __IOM uint32_t UARTMIS; /*!< Masked Interrupt Status Register, UARTMIS */ - __IOM uint32_t UARTICR; /*!< Interrupt Clear Register, UARTICR */ - __IOM uint32_t UARTDMACR; /*!< DMA Control Register, UARTDMACR */ - __IM uint32_t RESERVED2[997]; - __IOM uint32_t UARTPERIPHID0; /*!< UARTPeriphID0 Register */ - __IOM uint32_t UARTPERIPHID1; /*!< UARTPeriphID1 Register */ - __IOM uint32_t UARTPERIPHID2; /*!< UARTPeriphID2 Register */ - __IOM uint32_t UARTPERIPHID3; /*!< UARTPeriphID3 Register */ - __IOM uint32_t UARTPCELLID0; /*!< UARTPCellID0 Register */ - __IOM uint32_t UARTPCELLID1; /*!< UARTPCellID1 Register */ - __IOM uint32_t UARTPCELLID2; /*!< UARTPCellID2 Register */ - __IOM uint32_t UARTPCELLID3; /*!< UARTPCellID3 Register */ -} UART0_Type; /*!< Size = 4096 (0x1000) */ - - - -/* =========================================================================================================================== */ -/* ================ ROSC ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief ROSC (ROSC) - */ - -typedef struct { /*!< ROSC Structure */ - __IOM uint32_t CTRL; /*!< Ring Oscillator control */ - __IOM uint32_t FREQA; /*!< The FREQA & FREQB registers control the frequency by controlling - the drive strength of each stage The drive strength has - 4 levels determined by the number of bits set Increasing - the number of bits set increases the drive strength and - increases the oscillation frequency 0 bits set is the default - drive strength 1 bit set doubles the drive strength 2 bits - set triples drive strength 3 bits set quadruples drive - strength */ - __IOM uint32_t FREQB; /*!< For a detailed description see freqa register */ - __IOM uint32_t DORMANT; /*!< Ring Oscillator pause control */ - __IOM uint32_t DIV; /*!< Controls the output divider */ - __IOM uint32_t PHASE; /*!< Controls the phase shifted output */ - __IOM uint32_t STATUS; /*!< Ring Oscillator Status */ - __IOM uint32_t RANDOMBIT; /*!< This just reads the state of the oscillator output so randomness - is compromised if the ring oscillator is stopped or run - at a harmonic of the bus frequency */ - __IOM uint32_t COUNT; /*!< A down counter running at the ROSC frequency which counts to - zero and stops. To start the counter write a non-zero value. - Can be used for short software pauses when setting up time - sensitive hardware. */ -} ROSC_Type; /*!< Size = 36 (0x24) */ - - - -/* =========================================================================================================================== */ -/* ================ WATCHDOG ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief WATCHDOG (WATCHDOG) - */ - -typedef struct { /*!< WATCHDOG Structure */ - __IOM uint32_t CTRL; /*!< Watchdog control The rst_wdsel register determines which subsystems - are reset when the watchdog is triggered. The watchdog - can be triggered in software. */ - __IOM uint32_t LOAD; /*!< Load the watchdog timer. The maximum setting is 0xffffff which - corresponds to 0xffffff / 2 ticks before triggering a watchdog - reset (see errata RP2040-E1). */ - __IOM uint32_t REASON; /*!< Logs the reason for the last reset. Both bits are zero for the - case of a hardware reset. */ - __IOM uint32_t SCRATCH0; /*!< Scratch register. Information persists through soft reset of - the chip. */ - __IOM uint32_t SCRATCH1; /*!< Scratch register. Information persists through soft reset of - the chip. */ - __IOM uint32_t SCRATCH2; /*!< Scratch register. Information persists through soft reset of - the chip. */ - __IOM uint32_t SCRATCH3; /*!< Scratch register. Information persists through soft reset of - the chip. */ - __IOM uint32_t SCRATCH4; /*!< Scratch register. Information persists through soft reset of - the chip. */ - __IOM uint32_t SCRATCH5; /*!< Scratch register. Information persists through soft reset of - the chip. */ - __IOM uint32_t SCRATCH6; /*!< Scratch register. Information persists through soft reset of - the chip. */ - __IOM uint32_t SCRATCH7; /*!< Scratch register. Information persists through soft reset of - the chip. */ - __IOM uint32_t TICK; /*!< Controls the tick generator */ -} WATCHDOG_Type; /*!< Size = 48 (0x30) */ - - - -/* =========================================================================================================================== */ -/* ================ DMA ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief DMA with separate read and write masters (DMA) - */ - -typedef struct { /*!< DMA Structure */ - __IOM uint32_t CH0_READ_ADDR; /*!< DMA Channel 0 Read Address pointer */ - __IOM uint32_t CH0_WRITE_ADDR; /*!< DMA Channel 0 Write Address pointer */ - __IOM uint32_t CH0_TRANS_COUNT; /*!< DMA Channel 0 Transfer Count */ - __IOM uint32_t CH0_CTRL_TRIG; /*!< DMA Channel 0 Control and Status */ - __IOM uint32_t CH0_AL1_CTRL; /*!< Alias for channel 0 CTRL register */ - __IOM uint32_t CH0_AL1_READ_ADDR; /*!< Alias for channel 0 READ_ADDR register */ - __IOM uint32_t CH0_AL1_WRITE_ADDR; /*!< Alias for channel 0 WRITE_ADDR register */ - __IOM uint32_t CH0_AL1_TRANS_COUNT_TRIG; /*!< Alias for channel 0 TRANS_COUNT register This is a trigger register - (0xc). Writing a nonzero value will reload the channel - counter and start the channel. */ - __IOM uint32_t CH0_AL2_CTRL; /*!< Alias for channel 0 CTRL register */ - __IOM uint32_t CH0_AL2_TRANS_COUNT; /*!< Alias for channel 0 TRANS_COUNT register */ - __IOM uint32_t CH0_AL2_READ_ADDR; /*!< Alias for channel 0 READ_ADDR register */ - __IOM uint32_t CH0_AL2_WRITE_ADDR_TRIG; /*!< Alias for channel 0 WRITE_ADDR register This is a trigger register - (0xc). Writing a nonzero value will reload the channel - counter and start the channel. */ - __IOM uint32_t CH0_AL3_CTRL; /*!< Alias for channel 0 CTRL register */ - __IOM uint32_t CH0_AL3_WRITE_ADDR; /*!< Alias for channel 0 WRITE_ADDR register */ - __IOM uint32_t CH0_AL3_TRANS_COUNT; /*!< Alias for channel 0 TRANS_COUNT register */ - __IOM uint32_t CH0_AL3_READ_ADDR_TRIG; /*!< Alias for channel 0 READ_ADDR register This is a trigger register - (0xc). Writing a nonzero value will reload the channel - counter and start the channel. */ - __IOM uint32_t CH1_READ_ADDR; /*!< DMA Channel 1 Read Address pointer */ - __IOM uint32_t CH1_WRITE_ADDR; /*!< DMA Channel 1 Write Address pointer */ - __IOM uint32_t CH1_TRANS_COUNT; /*!< DMA Channel 1 Transfer Count */ - __IOM uint32_t CH1_CTRL_TRIG; /*!< DMA Channel 1 Control and Status */ - __IOM uint32_t CH1_AL1_CTRL; /*!< Alias for channel 1 CTRL register */ - __IOM uint32_t CH1_AL1_READ_ADDR; /*!< Alias for channel 1 READ_ADDR register */ - __IOM uint32_t CH1_AL1_WRITE_ADDR; /*!< Alias for channel 1 WRITE_ADDR register */ - __IOM uint32_t CH1_AL1_TRANS_COUNT_TRIG; /*!< Alias for channel 1 TRANS_COUNT register This is a trigger register - (0xc). Writing a nonzero value will reload the channel - counter and start the channel. */ - __IOM uint32_t CH1_AL2_CTRL; /*!< Alias for channel 1 CTRL register */ - __IOM uint32_t CH1_AL2_TRANS_COUNT; /*!< Alias for channel 1 TRANS_COUNT register */ - __IOM uint32_t CH1_AL2_READ_ADDR; /*!< Alias for channel 1 READ_ADDR register */ - __IOM uint32_t CH1_AL2_WRITE_ADDR_TRIG; /*!< Alias for channel 1 WRITE_ADDR register This is a trigger register - (0xc). Writing a nonzero value will reload the channel - counter and start the channel. */ - __IOM uint32_t CH1_AL3_CTRL; /*!< Alias for channel 1 CTRL register */ - __IOM uint32_t CH1_AL3_WRITE_ADDR; /*!< Alias for channel 1 WRITE_ADDR register */ - __IOM uint32_t CH1_AL3_TRANS_COUNT; /*!< Alias for channel 1 TRANS_COUNT register */ - __IOM uint32_t CH1_AL3_READ_ADDR_TRIG; /*!< Alias for channel 1 READ_ADDR register This is a trigger register - (0xc). Writing a nonzero value will reload the channel - counter and start the channel. */ - __IOM uint32_t CH2_READ_ADDR; /*!< DMA Channel 2 Read Address pointer */ - __IOM uint32_t CH2_WRITE_ADDR; /*!< DMA Channel 2 Write Address pointer */ - __IOM uint32_t CH2_TRANS_COUNT; /*!< DMA Channel 2 Transfer Count */ - __IOM uint32_t CH2_CTRL_TRIG; /*!< DMA Channel 2 Control and Status */ - __IOM uint32_t CH2_AL1_CTRL; /*!< Alias for channel 2 CTRL register */ - __IOM uint32_t CH2_AL1_READ_ADDR; /*!< Alias for channel 2 READ_ADDR register */ - __IOM uint32_t CH2_AL1_WRITE_ADDR; /*!< Alias for channel 2 WRITE_ADDR register */ - __IOM uint32_t CH2_AL1_TRANS_COUNT_TRIG; /*!< Alias for channel 2 TRANS_COUNT register This is a trigger register - (0xc). Writing a nonzero value will reload the channel - counter and start the channel. */ - __IOM uint32_t CH2_AL2_CTRL; /*!< Alias for channel 2 CTRL register */ - __IOM uint32_t CH2_AL2_TRANS_COUNT; /*!< Alias for channel 2 TRANS_COUNT register */ - __IOM uint32_t CH2_AL2_READ_ADDR; /*!< Alias for channel 2 READ_ADDR register */ - __IOM uint32_t CH2_AL2_WRITE_ADDR_TRIG; /*!< Alias for channel 2 WRITE_ADDR register This is a trigger register - (0xc). Writing a nonzero value will reload the channel - counter and start the channel. */ - __IOM uint32_t CH2_AL3_CTRL; /*!< Alias for channel 2 CTRL register */ - __IOM uint32_t CH2_AL3_WRITE_ADDR; /*!< Alias for channel 2 WRITE_ADDR register */ - __IOM uint32_t CH2_AL3_TRANS_COUNT; /*!< Alias for channel 2 TRANS_COUNT register */ - __IOM uint32_t CH2_AL3_READ_ADDR_TRIG; /*!< Alias for channel 2 READ_ADDR register This is a trigger register - (0xc). Writing a nonzero value will reload the channel - counter and start the channel. */ - __IOM uint32_t CH3_READ_ADDR; /*!< DMA Channel 3 Read Address pointer */ - __IOM uint32_t CH3_WRITE_ADDR; /*!< DMA Channel 3 Write Address pointer */ - __IOM uint32_t CH3_TRANS_COUNT; /*!< DMA Channel 3 Transfer Count */ - __IOM uint32_t CH3_CTRL_TRIG; /*!< DMA Channel 3 Control and Status */ - __IOM uint32_t CH3_AL1_CTRL; /*!< Alias for channel 3 CTRL register */ - __IOM uint32_t CH3_AL1_READ_ADDR; /*!< Alias for channel 3 READ_ADDR register */ - __IOM uint32_t CH3_AL1_WRITE_ADDR; /*!< Alias for channel 3 WRITE_ADDR register */ - __IOM uint32_t CH3_AL1_TRANS_COUNT_TRIG; /*!< Alias for channel 3 TRANS_COUNT register This is a trigger register - (0xc). Writing a nonzero value will reload the channel - counter and start the channel. */ - __IOM uint32_t CH3_AL2_CTRL; /*!< Alias for channel 3 CTRL register */ - __IOM uint32_t CH3_AL2_TRANS_COUNT; /*!< Alias for channel 3 TRANS_COUNT register */ - __IOM uint32_t CH3_AL2_READ_ADDR; /*!< Alias for channel 3 READ_ADDR register */ - __IOM uint32_t CH3_AL2_WRITE_ADDR_TRIG; /*!< Alias for channel 3 WRITE_ADDR register This is a trigger register - (0xc). Writing a nonzero value will reload the channel - counter and start the channel. */ - __IOM uint32_t CH3_AL3_CTRL; /*!< Alias for channel 3 CTRL register */ - __IOM uint32_t CH3_AL3_WRITE_ADDR; /*!< Alias for channel 3 WRITE_ADDR register */ - __IOM uint32_t CH3_AL3_TRANS_COUNT; /*!< Alias for channel 3 TRANS_COUNT register */ - __IOM uint32_t CH3_AL3_READ_ADDR_TRIG; /*!< Alias for channel 3 READ_ADDR register This is a trigger register - (0xc). Writing a nonzero value will reload the channel - counter and start the channel. */ - __IOM uint32_t CH4_READ_ADDR; /*!< DMA Channel 4 Read Address pointer */ - __IOM uint32_t CH4_WRITE_ADDR; /*!< DMA Channel 4 Write Address pointer */ - __IOM uint32_t CH4_TRANS_COUNT; /*!< DMA Channel 4 Transfer Count */ - __IOM uint32_t CH4_CTRL_TRIG; /*!< DMA Channel 4 Control and Status */ - __IOM uint32_t CH4_AL1_CTRL; /*!< Alias for channel 4 CTRL register */ - __IOM uint32_t CH4_AL1_READ_ADDR; /*!< Alias for channel 4 READ_ADDR register */ - __IOM uint32_t CH4_AL1_WRITE_ADDR; /*!< Alias for channel 4 WRITE_ADDR register */ - __IOM uint32_t CH4_AL1_TRANS_COUNT_TRIG; /*!< Alias for channel 4 TRANS_COUNT register This is a trigger register - (0xc). Writing a nonzero value will reload the channel - counter and start the channel. */ - __IOM uint32_t CH4_AL2_CTRL; /*!< Alias for channel 4 CTRL register */ - __IOM uint32_t CH4_AL2_TRANS_COUNT; /*!< Alias for channel 4 TRANS_COUNT register */ - __IOM uint32_t CH4_AL2_READ_ADDR; /*!< Alias for channel 4 READ_ADDR register */ - __IOM uint32_t CH4_AL2_WRITE_ADDR_TRIG; /*!< Alias for channel 4 WRITE_ADDR register This is a trigger register - (0xc). Writing a nonzero value will reload the channel - counter and start the channel. */ - __IOM uint32_t CH4_AL3_CTRL; /*!< Alias for channel 4 CTRL register */ - __IOM uint32_t CH4_AL3_WRITE_ADDR; /*!< Alias for channel 4 WRITE_ADDR register */ - __IOM uint32_t CH4_AL3_TRANS_COUNT; /*!< Alias for channel 4 TRANS_COUNT register */ - __IOM uint32_t CH4_AL3_READ_ADDR_TRIG; /*!< Alias for channel 4 READ_ADDR register This is a trigger register - (0xc). Writing a nonzero value will reload the channel - counter and start the channel. */ - __IOM uint32_t CH5_READ_ADDR; /*!< DMA Channel 5 Read Address pointer */ - __IOM uint32_t CH5_WRITE_ADDR; /*!< DMA Channel 5 Write Address pointer */ - __IOM uint32_t CH5_TRANS_COUNT; /*!< DMA Channel 5 Transfer Count */ - __IOM uint32_t CH5_CTRL_TRIG; /*!< DMA Channel 5 Control and Status */ - __IOM uint32_t CH5_AL1_CTRL; /*!< Alias for channel 5 CTRL register */ - __IOM uint32_t CH5_AL1_READ_ADDR; /*!< Alias for channel 5 READ_ADDR register */ - __IOM uint32_t CH5_AL1_WRITE_ADDR; /*!< Alias for channel 5 WRITE_ADDR register */ - __IOM uint32_t CH5_AL1_TRANS_COUNT_TRIG; /*!< Alias for channel 5 TRANS_COUNT register This is a trigger register - (0xc). Writing a nonzero value will reload the channel - counter and start the channel. */ - __IOM uint32_t CH5_AL2_CTRL; /*!< Alias for channel 5 CTRL register */ - __IOM uint32_t CH5_AL2_TRANS_COUNT; /*!< Alias for channel 5 TRANS_COUNT register */ - __IOM uint32_t CH5_AL2_READ_ADDR; /*!< Alias for channel 5 READ_ADDR register */ - __IOM uint32_t CH5_AL2_WRITE_ADDR_TRIG; /*!< Alias for channel 5 WRITE_ADDR register This is a trigger register - (0xc). Writing a nonzero value will reload the channel - counter and start the channel. */ - __IOM uint32_t CH5_AL3_CTRL; /*!< Alias for channel 5 CTRL register */ - __IOM uint32_t CH5_AL3_WRITE_ADDR; /*!< Alias for channel 5 WRITE_ADDR register */ - __IOM uint32_t CH5_AL3_TRANS_COUNT; /*!< Alias for channel 5 TRANS_COUNT register */ - __IOM uint32_t CH5_AL3_READ_ADDR_TRIG; /*!< Alias for channel 5 READ_ADDR register This is a trigger register - (0xc). Writing a nonzero value will reload the channel - counter and start the channel. */ - __IOM uint32_t CH6_READ_ADDR; /*!< DMA Channel 6 Read Address pointer */ - __IOM uint32_t CH6_WRITE_ADDR; /*!< DMA Channel 6 Write Address pointer */ - __IOM uint32_t CH6_TRANS_COUNT; /*!< DMA Channel 6 Transfer Count */ - __IOM uint32_t CH6_CTRL_TRIG; /*!< DMA Channel 6 Control and Status */ - __IOM uint32_t CH6_AL1_CTRL; /*!< Alias for channel 6 CTRL register */ - __IOM uint32_t CH6_AL1_READ_ADDR; /*!< Alias for channel 6 READ_ADDR register */ - __IOM uint32_t CH6_AL1_WRITE_ADDR; /*!< Alias for channel 6 WRITE_ADDR register */ - __IOM uint32_t CH6_AL1_TRANS_COUNT_TRIG; /*!< Alias for channel 6 TRANS_COUNT register This is a trigger register - (0xc). Writing a nonzero value will reload the channel - counter and start the channel. */ - __IOM uint32_t CH6_AL2_CTRL; /*!< Alias for channel 6 CTRL register */ - __IOM uint32_t CH6_AL2_TRANS_COUNT; /*!< Alias for channel 6 TRANS_COUNT register */ - __IOM uint32_t CH6_AL2_READ_ADDR; /*!< Alias for channel 6 READ_ADDR register */ - __IOM uint32_t CH6_AL2_WRITE_ADDR_TRIG; /*!< Alias for channel 6 WRITE_ADDR register This is a trigger register - (0xc). Writing a nonzero value will reload the channel - counter and start the channel. */ - __IOM uint32_t CH6_AL3_CTRL; /*!< Alias for channel 6 CTRL register */ - __IOM uint32_t CH6_AL3_WRITE_ADDR; /*!< Alias for channel 6 WRITE_ADDR register */ - __IOM uint32_t CH6_AL3_TRANS_COUNT; /*!< Alias for channel 6 TRANS_COUNT register */ - __IOM uint32_t CH6_AL3_READ_ADDR_TRIG; /*!< Alias for channel 6 READ_ADDR register This is a trigger register - (0xc). Writing a nonzero value will reload the channel - counter and start the channel. */ - __IOM uint32_t CH7_READ_ADDR; /*!< DMA Channel 7 Read Address pointer */ - __IOM uint32_t CH7_WRITE_ADDR; /*!< DMA Channel 7 Write Address pointer */ - __IOM uint32_t CH7_TRANS_COUNT; /*!< DMA Channel 7 Transfer Count */ - __IOM uint32_t CH7_CTRL_TRIG; /*!< DMA Channel 7 Control and Status */ - __IOM uint32_t CH7_AL1_CTRL; /*!< Alias for channel 7 CTRL register */ - __IOM uint32_t CH7_AL1_READ_ADDR; /*!< Alias for channel 7 READ_ADDR register */ - __IOM uint32_t CH7_AL1_WRITE_ADDR; /*!< Alias for channel 7 WRITE_ADDR register */ - __IOM uint32_t CH7_AL1_TRANS_COUNT_TRIG; /*!< Alias for channel 7 TRANS_COUNT register This is a trigger register - (0xc). Writing a nonzero value will reload the channel - counter and start the channel. */ - __IOM uint32_t CH7_AL2_CTRL; /*!< Alias for channel 7 CTRL register */ - __IOM uint32_t CH7_AL2_TRANS_COUNT; /*!< Alias for channel 7 TRANS_COUNT register */ - __IOM uint32_t CH7_AL2_READ_ADDR; /*!< Alias for channel 7 READ_ADDR register */ - __IOM uint32_t CH7_AL2_WRITE_ADDR_TRIG; /*!< Alias for channel 7 WRITE_ADDR register This is a trigger register - (0xc). Writing a nonzero value will reload the channel - counter and start the channel. */ - __IOM uint32_t CH7_AL3_CTRL; /*!< Alias for channel 7 CTRL register */ - __IOM uint32_t CH7_AL3_WRITE_ADDR; /*!< Alias for channel 7 WRITE_ADDR register */ - __IOM uint32_t CH7_AL3_TRANS_COUNT; /*!< Alias for channel 7 TRANS_COUNT register */ - __IOM uint32_t CH7_AL3_READ_ADDR_TRIG; /*!< Alias for channel 7 READ_ADDR register This is a trigger register - (0xc). Writing a nonzero value will reload the channel - counter and start the channel. */ - __IOM uint32_t CH8_READ_ADDR; /*!< DMA Channel 8 Read Address pointer */ - __IOM uint32_t CH8_WRITE_ADDR; /*!< DMA Channel 8 Write Address pointer */ - __IOM uint32_t CH8_TRANS_COUNT; /*!< DMA Channel 8 Transfer Count */ - __IOM uint32_t CH8_CTRL_TRIG; /*!< DMA Channel 8 Control and Status */ - __IOM uint32_t CH8_AL1_CTRL; /*!< Alias for channel 8 CTRL register */ - __IOM uint32_t CH8_AL1_READ_ADDR; /*!< Alias for channel 8 READ_ADDR register */ - __IOM uint32_t CH8_AL1_WRITE_ADDR; /*!< Alias for channel 8 WRITE_ADDR register */ - __IOM uint32_t CH8_AL1_TRANS_COUNT_TRIG; /*!< Alias for channel 8 TRANS_COUNT register This is a trigger register - (0xc). Writing a nonzero value will reload the channel - counter and start the channel. */ - __IOM uint32_t CH8_AL2_CTRL; /*!< Alias for channel 8 CTRL register */ - __IOM uint32_t CH8_AL2_TRANS_COUNT; /*!< Alias for channel 8 TRANS_COUNT register */ - __IOM uint32_t CH8_AL2_READ_ADDR; /*!< Alias for channel 8 READ_ADDR register */ - __IOM uint32_t CH8_AL2_WRITE_ADDR_TRIG; /*!< Alias for channel 8 WRITE_ADDR register This is a trigger register - (0xc). Writing a nonzero value will reload the channel - counter and start the channel. */ - __IOM uint32_t CH8_AL3_CTRL; /*!< Alias for channel 8 CTRL register */ - __IOM uint32_t CH8_AL3_WRITE_ADDR; /*!< Alias for channel 8 WRITE_ADDR register */ - __IOM uint32_t CH8_AL3_TRANS_COUNT; /*!< Alias for channel 8 TRANS_COUNT register */ - __IOM uint32_t CH8_AL3_READ_ADDR_TRIG; /*!< Alias for channel 8 READ_ADDR register This is a trigger register - (0xc). Writing a nonzero value will reload the channel - counter and start the channel. */ - __IOM uint32_t CH9_READ_ADDR; /*!< DMA Channel 9 Read Address pointer */ - __IOM uint32_t CH9_WRITE_ADDR; /*!< DMA Channel 9 Write Address pointer */ - __IOM uint32_t CH9_TRANS_COUNT; /*!< DMA Channel 9 Transfer Count */ - __IOM uint32_t CH9_CTRL_TRIG; /*!< DMA Channel 9 Control and Status */ - __IOM uint32_t CH9_AL1_CTRL; /*!< Alias for channel 9 CTRL register */ - __IOM uint32_t CH9_AL1_READ_ADDR; /*!< Alias for channel 9 READ_ADDR register */ - __IOM uint32_t CH9_AL1_WRITE_ADDR; /*!< Alias for channel 9 WRITE_ADDR register */ - __IOM uint32_t CH9_AL1_TRANS_COUNT_TRIG; /*!< Alias for channel 9 TRANS_COUNT register This is a trigger register - (0xc). Writing a nonzero value will reload the channel - counter and start the channel. */ - __IOM uint32_t CH9_AL2_CTRL; /*!< Alias for channel 9 CTRL register */ - __IOM uint32_t CH9_AL2_TRANS_COUNT; /*!< Alias for channel 9 TRANS_COUNT register */ - __IOM uint32_t CH9_AL2_READ_ADDR; /*!< Alias for channel 9 READ_ADDR register */ - __IOM uint32_t CH9_AL2_WRITE_ADDR_TRIG; /*!< Alias for channel 9 WRITE_ADDR register This is a trigger register - (0xc). Writing a nonzero value will reload the channel - counter and start the channel. */ - __IOM uint32_t CH9_AL3_CTRL; /*!< Alias for channel 9 CTRL register */ - __IOM uint32_t CH9_AL3_WRITE_ADDR; /*!< Alias for channel 9 WRITE_ADDR register */ - __IOM uint32_t CH9_AL3_TRANS_COUNT; /*!< Alias for channel 9 TRANS_COUNT register */ - __IOM uint32_t CH9_AL3_READ_ADDR_TRIG; /*!< Alias for channel 9 READ_ADDR register This is a trigger register - (0xc). Writing a nonzero value will reload the channel - counter and start the channel. */ - __IOM uint32_t CH10_READ_ADDR; /*!< DMA Channel 10 Read Address pointer */ - __IOM uint32_t CH10_WRITE_ADDR; /*!< DMA Channel 10 Write Address pointer */ - __IOM uint32_t CH10_TRANS_COUNT; /*!< DMA Channel 10 Transfer Count */ - __IOM uint32_t CH10_CTRL_TRIG; /*!< DMA Channel 10 Control and Status */ - __IOM uint32_t CH10_AL1_CTRL; /*!< Alias for channel 10 CTRL register */ - __IOM uint32_t CH10_AL1_READ_ADDR; /*!< Alias for channel 10 READ_ADDR register */ - __IOM uint32_t CH10_AL1_WRITE_ADDR; /*!< Alias for channel 10 WRITE_ADDR register */ - __IOM uint32_t CH10_AL1_TRANS_COUNT_TRIG; /*!< Alias for channel 10 TRANS_COUNT register This is a trigger - register (0xc). Writing a nonzero value will reload the - channel counter and start the channel. */ - __IOM uint32_t CH10_AL2_CTRL; /*!< Alias for channel 10 CTRL register */ - __IOM uint32_t CH10_AL2_TRANS_COUNT; /*!< Alias for channel 10 TRANS_COUNT register */ - __IOM uint32_t CH10_AL2_READ_ADDR; /*!< Alias for channel 10 READ_ADDR register */ - __IOM uint32_t CH10_AL2_WRITE_ADDR_TRIG; /*!< Alias for channel 10 WRITE_ADDR register This is a trigger register - (0xc). Writing a nonzero value will reload the channel - counter and start the channel. */ - __IOM uint32_t CH10_AL3_CTRL; /*!< Alias for channel 10 CTRL register */ - __IOM uint32_t CH10_AL3_WRITE_ADDR; /*!< Alias for channel 10 WRITE_ADDR register */ - __IOM uint32_t CH10_AL3_TRANS_COUNT; /*!< Alias for channel 10 TRANS_COUNT register */ - __IOM uint32_t CH10_AL3_READ_ADDR_TRIG; /*!< Alias for channel 10 READ_ADDR register This is a trigger register - (0xc). Writing a nonzero value will reload the channel - counter and start the channel. */ - __IOM uint32_t CH11_READ_ADDR; /*!< DMA Channel 11 Read Address pointer */ - __IOM uint32_t CH11_WRITE_ADDR; /*!< DMA Channel 11 Write Address pointer */ - __IOM uint32_t CH11_TRANS_COUNT; /*!< DMA Channel 11 Transfer Count */ - __IOM uint32_t CH11_CTRL_TRIG; /*!< DMA Channel 11 Control and Status */ - __IOM uint32_t CH11_AL1_CTRL; /*!< Alias for channel 11 CTRL register */ - __IOM uint32_t CH11_AL1_READ_ADDR; /*!< Alias for channel 11 READ_ADDR register */ - __IOM uint32_t CH11_AL1_WRITE_ADDR; /*!< Alias for channel 11 WRITE_ADDR register */ - __IOM uint32_t CH11_AL1_TRANS_COUNT_TRIG; /*!< Alias for channel 11 TRANS_COUNT register This is a trigger - register (0xc). Writing a nonzero value will reload the - channel counter and start the channel. */ - __IOM uint32_t CH11_AL2_CTRL; /*!< Alias for channel 11 CTRL register */ - __IOM uint32_t CH11_AL2_TRANS_COUNT; /*!< Alias for channel 11 TRANS_COUNT register */ - __IOM uint32_t CH11_AL2_READ_ADDR; /*!< Alias for channel 11 READ_ADDR register */ - __IOM uint32_t CH11_AL2_WRITE_ADDR_TRIG; /*!< Alias for channel 11 WRITE_ADDR register This is a trigger register - (0xc). Writing a nonzero value will reload the channel - counter and start the channel. */ - __IOM uint32_t CH11_AL3_CTRL; /*!< Alias for channel 11 CTRL register */ - __IOM uint32_t CH11_AL3_WRITE_ADDR; /*!< Alias for channel 11 WRITE_ADDR register */ - __IOM uint32_t CH11_AL3_TRANS_COUNT; /*!< Alias for channel 11 TRANS_COUNT register */ - __IOM uint32_t CH11_AL3_READ_ADDR_TRIG; /*!< Alias for channel 11 READ_ADDR register This is a trigger register - (0xc). Writing a nonzero value will reload the channel - counter and start the channel. */ - __IM uint32_t RESERVED[64]; - __IOM uint32_t INTR; /*!< Interrupt Status (raw) */ - __IOM uint32_t INTE0; /*!< Interrupt Enables for IRQ 0 */ - __IOM uint32_t INTF0; /*!< Force Interrupts */ - __IOM uint32_t INTS0; /*!< Interrupt Status for IRQ 0 */ - __IOM uint32_t INTR1; /*!< Interrupt Status (raw) */ - __IOM uint32_t INTE1; /*!< Interrupt Enables for IRQ 1 */ - __IOM uint32_t INTF1; /*!< Force Interrupts for IRQ 1 */ - __IOM uint32_t INTS1; /*!< Interrupt Status (masked) for IRQ 1 */ - __IOM uint32_t TIMER0; /*!< Pacing (X/Y) Fractional Timer The pacing timer produces TREQ - assertions at a rate set by ((X/Y) * sys_clk). This equation - is evaluated every sys_clk cycles and therefore can only - generate TREQs at a rate of 1 per sys_clk (i.e. permanent - TREQ) or less. */ - __IOM uint32_t TIMER1; /*!< Pacing (X/Y) Fractional Timer The pacing timer produces TREQ - assertions at a rate set by ((X/Y) * sys_clk). This equation - is evaluated every sys_clk cycles and therefore can only - generate TREQs at a rate of 1 per sys_clk (i.e. permanent - TREQ) or less. */ - __IOM uint32_t TIMER2; /*!< Pacing (X/Y) Fractional Timer The pacing timer produces TREQ - assertions at a rate set by ((X/Y) * sys_clk). This equation - is evaluated every sys_clk cycles and therefore can only - generate TREQs at a rate of 1 per sys_clk (i.e. permanent - TREQ) or less. */ - __IOM uint32_t TIMER3; /*!< Pacing (X/Y) Fractional Timer The pacing timer produces TREQ - assertions at a rate set by ((X/Y) * sys_clk). This equation - is evaluated every sys_clk cycles and therefore can only - generate TREQs at a rate of 1 per sys_clk (i.e. permanent - TREQ) or less. */ - __IOM uint32_t MULTI_CHAN_TRIGGER; /*!< Trigger one or more channels simultaneously */ - __IOM uint32_t SNIFF_CTRL; /*!< Sniffer Control */ - __IOM uint32_t SNIFF_DATA; /*!< Data accumulator for sniff hardware */ - __IM uint32_t RESERVED1; - __IOM uint32_t FIFO_LEVELS; /*!< Debug RAF, WAF, TDF levels */ - __IOM uint32_t CHAN_ABORT; /*!< Abort an in-progress transfer sequence on one or more channels */ - __IOM uint32_t N_CHANNELS; /*!< The number of channels this DMA instance is equipped with. This - DMA supports up to 16 hardware channels, but can be configured - with as few as one, to minimise silicon area. */ - __IM uint32_t RESERVED2[237]; - __IOM uint32_t CH0_DBG_CTDREQ; /*!< Read: get channel DREQ counter (i.e. how many accesses the DMA - expects it can perform on the peripheral without overflow/underflow. - Write any value: clears the counter, and cause channel - to re-initiate DREQ handshake. */ - __IOM uint32_t CH0_DBG_TCR; /*!< Read to get channel TRANS_COUNT reload value, i.e. the length - of the next transfer */ - __IM uint32_t RESERVED3[14]; - __IOM uint32_t CH1_DBG_CTDREQ; /*!< Read: get channel DREQ counter (i.e. how many accesses the DMA - expects it can perform on the peripheral without overflow/underflow. - Write any value: clears the counter, and cause channel - to re-initiate DREQ handshake. */ - __IOM uint32_t CH1_DBG_TCR; /*!< Read to get channel TRANS_COUNT reload value, i.e. the length - of the next transfer */ - __IM uint32_t RESERVED4[14]; - __IOM uint32_t CH2_DBG_CTDREQ; /*!< Read: get channel DREQ counter (i.e. how many accesses the DMA - expects it can perform on the peripheral without overflow/underflow. - Write any value: clears the counter, and cause channel - to re-initiate DREQ handshake. */ - __IOM uint32_t CH2_DBG_TCR; /*!< Read to get channel TRANS_COUNT reload value, i.e. the length - of the next transfer */ - __IM uint32_t RESERVED5[14]; - __IOM uint32_t CH3_DBG_CTDREQ; /*!< Read: get channel DREQ counter (i.e. how many accesses the DMA - expects it can perform on the peripheral without overflow/underflow. - Write any value: clears the counter, and cause channel - to re-initiate DREQ handshake. */ - __IOM uint32_t CH3_DBG_TCR; /*!< Read to get channel TRANS_COUNT reload value, i.e. the length - of the next transfer */ - __IM uint32_t RESERVED6[14]; - __IOM uint32_t CH4_DBG_CTDREQ; /*!< Read: get channel DREQ counter (i.e. how many accesses the DMA - expects it can perform on the peripheral without overflow/underflow. - Write any value: clears the counter, and cause channel - to re-initiate DREQ handshake. */ - __IOM uint32_t CH4_DBG_TCR; /*!< Read to get channel TRANS_COUNT reload value, i.e. the length - of the next transfer */ - __IM uint32_t RESERVED7[14]; - __IOM uint32_t CH5_DBG_CTDREQ; /*!< Read: get channel DREQ counter (i.e. how many accesses the DMA - expects it can perform on the peripheral without overflow/underflow. - Write any value: clears the counter, and cause channel - to re-initiate DREQ handshake. */ - __IOM uint32_t CH5_DBG_TCR; /*!< Read to get channel TRANS_COUNT reload value, i.e. the length - of the next transfer */ - __IM uint32_t RESERVED8[14]; - __IOM uint32_t CH6_DBG_CTDREQ; /*!< Read: get channel DREQ counter (i.e. how many accesses the DMA - expects it can perform on the peripheral without overflow/underflow. - Write any value: clears the counter, and cause channel - to re-initiate DREQ handshake. */ - __IOM uint32_t CH6_DBG_TCR; /*!< Read to get channel TRANS_COUNT reload value, i.e. the length - of the next transfer */ - __IM uint32_t RESERVED9[14]; - __IOM uint32_t CH7_DBG_CTDREQ; /*!< Read: get channel DREQ counter (i.e. how many accesses the DMA - expects it can perform on the peripheral without overflow/underflow. - Write any value: clears the counter, and cause channel - to re-initiate DREQ handshake. */ - __IOM uint32_t CH7_DBG_TCR; /*!< Read to get channel TRANS_COUNT reload value, i.e. the length - of the next transfer */ - __IM uint32_t RESERVED10[14]; - __IOM uint32_t CH8_DBG_CTDREQ; /*!< Read: get channel DREQ counter (i.e. how many accesses the DMA - expects it can perform on the peripheral without overflow/underflow. - Write any value: clears the counter, and cause channel - to re-initiate DREQ handshake. */ - __IOM uint32_t CH8_DBG_TCR; /*!< Read to get channel TRANS_COUNT reload value, i.e. the length - of the next transfer */ - __IM uint32_t RESERVED11[14]; - __IOM uint32_t CH9_DBG_CTDREQ; /*!< Read: get channel DREQ counter (i.e. how many accesses the DMA - expects it can perform on the peripheral without overflow/underflow. - Write any value: clears the counter, and cause channel - to re-initiate DREQ handshake. */ - __IOM uint32_t CH9_DBG_TCR; /*!< Read to get channel TRANS_COUNT reload value, i.e. the length - of the next transfer */ - __IM uint32_t RESERVED12[14]; - __IOM uint32_t CH10_DBG_CTDREQ; /*!< Read: get channel DREQ counter (i.e. how many accesses the DMA - expects it can perform on the peripheral without overflow/underflow. - Write any value: clears the counter, and cause channel - to re-initiate DREQ handshake. */ - __IOM uint32_t CH10_DBG_TCR; /*!< Read to get channel TRANS_COUNT reload value, i.e. the length - of the next transfer */ - __IM uint32_t RESERVED13[14]; - __IOM uint32_t CH11_DBG_CTDREQ; /*!< Read: get channel DREQ counter (i.e. how many accesses the DMA - expects it can perform on the peripheral without overflow/underflow. - Write any value: clears the counter, and cause channel - to re-initiate DREQ handshake. */ - __IOM uint32_t CH11_DBG_TCR; /*!< Read to get channel TRANS_COUNT reload value, i.e. the length - of the next transfer */ -} DMA_Type; /*!< Size = 2760 (0xac8) */ - - - -/* =========================================================================================================================== */ -/* ================ TIMER ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief Controls time and alarms - time is a 64 bit value indicating the time in usec since power-on - timeh is the top 32 bits of time & timel is the bottom 32 bits - to change time write to timelw before timehw - to read time read from timelr before timehr - An alarm is set by setting alarm_enable and writing to the corresponding alarm register - When an alarm is pending, the corresponding alarm_running signal will be high - An alarm can be cancelled before it has finished by clearing the alarm_enable - When an alarm fires, the corresponding alarm_irq is set and alarm_running is cleared - To clear the interrupt write a 1 to the corresponding alarm_irq (TIMER) - */ - -typedef struct { /*!< TIMER Structure */ - __IOM uint32_t TIMEHW; /*!< Write to bits 63:32 of time always write timelw before timehw */ - __IOM uint32_t TIMELW; /*!< Write to bits 31:0 of time writes do not get copied to time - until timehw is written */ - __IOM uint32_t TIMEHR; /*!< Read from bits 63:32 of time always read timelr before timehr */ - __IOM uint32_t TIMELR; /*!< Read from bits 31:0 of time */ - __IOM uint32_t ALARM0; /*!< Arm alarm 0, and configure the time it will fire. Once armed, - the alarm fires when TIMER_ALARM0 == TIMELR. The alarm - will disarm itself once it fires, and can be disarmed early - using the ARMED status register. */ - __IOM uint32_t ALARM1; /*!< Arm alarm 1, and configure the time it will fire. Once armed, - the alarm fires when TIMER_ALARM1 == TIMELR. The alarm - will disarm itself once it fires, and can be disarmed early - using the ARMED status register. */ - __IOM uint32_t ALARM2; /*!< Arm alarm 2, and configure the time it will fire. Once armed, - the alarm fires when TIMER_ALARM2 == TIMELR. The alarm - will disarm itself once it fires, and can be disarmed early - using the ARMED status register. */ - __IOM uint32_t ALARM3; /*!< Arm alarm 3, and configure the time it will fire. Once armed, - the alarm fires when TIMER_ALARM3 == TIMELR. The alarm - will disarm itself once it fires, and can be disarmed early - using the ARMED status register. */ - __IOM uint32_t ARMED; /*!< Indicates the armed/disarmed status of each alarm. A write to - the corresponding ALARMx register arms the alarm. Alarms - automatically disarm upon firing, but writing ones here - will disarm immediately without waiting to fire. */ - __IOM uint32_t TIMERAWH; /*!< Raw read from bits 63:32 of time (no side effects) */ - __IOM uint32_t TIMERAWL; /*!< Raw read from bits 31:0 of time (no side effects) */ - __IOM uint32_t DBGPAUSE; /*!< Set bits high to enable pause when the corresponding debug ports - are active */ - __IOM uint32_t PAUSE; /*!< Set high to pause the timer */ - __IOM uint32_t INTR; /*!< Raw Interrupts */ - __IOM uint32_t INTE; /*!< Interrupt Enable */ - __IOM uint32_t INTF; /*!< Interrupt Force */ - __IOM uint32_t INTS; /*!< Interrupt status after masking & forcing */ -} TIMER_Type; /*!< Size = 68 (0x44) */ - - - -/* =========================================================================================================================== */ -/* ================ PWM ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief Simple PWM (PWM) - */ - -typedef struct { /*!< PWM Structure */ - __IOM uint32_t CH0_CSR; /*!< Control and status register */ - __IOM uint32_t CH0_DIV; /*!< INT and FRAC form a fixed-point fractional number. Counting - rate is system clock frequency divided by this number. - Fractional division uses simple 1st-order sigma-delta. */ - __IOM uint32_t CH0_CTR; /*!< Direct access to the PWM counter */ - __IOM uint32_t CH0_CC; /*!< Counter compare values */ - __IOM uint32_t CH0_TOP; /*!< Counter wrap value */ - __IOM uint32_t CH1_CSR; /*!< Control and status register */ - __IOM uint32_t CH1_DIV; /*!< INT and FRAC form a fixed-point fractional number. Counting - rate is system clock frequency divided by this number. - Fractional division uses simple 1st-order sigma-delta. */ - __IOM uint32_t CH1_CTR; /*!< Direct access to the PWM counter */ - __IOM uint32_t CH1_CC; /*!< Counter compare values */ - __IOM uint32_t CH1_TOP; /*!< Counter wrap value */ - __IOM uint32_t CH2_CSR; /*!< Control and status register */ - __IOM uint32_t CH2_DIV; /*!< INT and FRAC form a fixed-point fractional number. Counting - rate is system clock frequency divided by this number. - Fractional division uses simple 1st-order sigma-delta. */ - __IOM uint32_t CH2_CTR; /*!< Direct access to the PWM counter */ - __IOM uint32_t CH2_CC; /*!< Counter compare values */ - __IOM uint32_t CH2_TOP; /*!< Counter wrap value */ - __IOM uint32_t CH3_CSR; /*!< Control and status register */ - __IOM uint32_t CH3_DIV; /*!< INT and FRAC form a fixed-point fractional number. Counting - rate is system clock frequency divided by this number. - Fractional division uses simple 1st-order sigma-delta. */ - __IOM uint32_t CH3_CTR; /*!< Direct access to the PWM counter */ - __IOM uint32_t CH3_CC; /*!< Counter compare values */ - __IOM uint32_t CH3_TOP; /*!< Counter wrap value */ - __IOM uint32_t CH4_CSR; /*!< Control and status register */ - __IOM uint32_t CH4_DIV; /*!< INT and FRAC form a fixed-point fractional number. Counting - rate is system clock frequency divided by this number. - Fractional division uses simple 1st-order sigma-delta. */ - __IOM uint32_t CH4_CTR; /*!< Direct access to the PWM counter */ - __IOM uint32_t CH4_CC; /*!< Counter compare values */ - __IOM uint32_t CH4_TOP; /*!< Counter wrap value */ - __IOM uint32_t CH5_CSR; /*!< Control and status register */ - __IOM uint32_t CH5_DIV; /*!< INT and FRAC form a fixed-point fractional number. Counting - rate is system clock frequency divided by this number. - Fractional division uses simple 1st-order sigma-delta. */ - __IOM uint32_t CH5_CTR; /*!< Direct access to the PWM counter */ - __IOM uint32_t CH5_CC; /*!< Counter compare values */ - __IOM uint32_t CH5_TOP; /*!< Counter wrap value */ - __IOM uint32_t CH6_CSR; /*!< Control and status register */ - __IOM uint32_t CH6_DIV; /*!< INT and FRAC form a fixed-point fractional number. Counting - rate is system clock frequency divided by this number. - Fractional division uses simple 1st-order sigma-delta. */ - __IOM uint32_t CH6_CTR; /*!< Direct access to the PWM counter */ - __IOM uint32_t CH6_CC; /*!< Counter compare values */ - __IOM uint32_t CH6_TOP; /*!< Counter wrap value */ - __IOM uint32_t CH7_CSR; /*!< Control and status register */ - __IOM uint32_t CH7_DIV; /*!< INT and FRAC form a fixed-point fractional number. Counting - rate is system clock frequency divided by this number. - Fractional division uses simple 1st-order sigma-delta. */ - __IOM uint32_t CH7_CTR; /*!< Direct access to the PWM counter */ - __IOM uint32_t CH7_CC; /*!< Counter compare values */ - __IOM uint32_t CH7_TOP; /*!< Counter wrap value */ - __IOM uint32_t EN; /*!< This register aliases the CSR_EN bits for all channels. Writing - to this register allows multiple channels to be enabled - or disabled simultaneously, so they can run in perfect - sync. For each channel, there is only one physical EN register - bit, which can be accessed through here or CHx_CSR. */ - __IOM uint32_t INTR; /*!< Raw Interrupts */ - __IOM uint32_t INTE; /*!< Interrupt Enable */ - __IOM uint32_t INTF; /*!< Interrupt Force */ - __IOM uint32_t INTS; /*!< Interrupt status after masking & forcing */ -} PWM_Type; /*!< Size = 180 (0xb4) */ - - - -/* =========================================================================================================================== */ -/* ================ ADC ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief Control and data interface to SAR ADC (ADC) - */ - -typedef struct { /*!< ADC Structure */ - __IOM uint32_t CS; /*!< ADC Control and Status */ - __IOM uint32_t RESULT; /*!< Result of most recent ADC conversion */ - __IOM uint32_t FCS; /*!< FIFO control and status */ - __IOM uint32_t FIFO; /*!< Conversion result FIFO */ - __IOM uint32_t DIV; /*!< Clock divider. If non-zero, CS_START_MANY will start conversions - at regular intervals rather than back-to-back. The divider - is reset when either of these fields are written. Total - period is 1 + INT + FRAC / 256 */ - __IOM uint32_t INTR; /*!< Raw Interrupts */ - __IOM uint32_t INTE; /*!< Interrupt Enable */ - __IOM uint32_t INTF; /*!< Interrupt Force */ - __IOM uint32_t INTS; /*!< Interrupt status after masking & forcing */ -} ADC_Type; /*!< Size = 36 (0x24) */ - - - -/* =========================================================================================================================== */ -/* ================ I2C0 ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief DW_apb_i2c address block - - List of configuration constants for the Synopsys I2C hardware (you may see references to these in I2C register header; these are *fixed* values, set at hardware design time): - - IC_ULTRA_FAST_MODE ................ 0x0 - IC_UFM_TBUF_CNT_DEFAULT ........... 0x8 - IC_UFM_SCL_LOW_COUNT .............. 0x0008 - IC_UFM_SCL_HIGH_COUNT ............. 0x0006 - IC_TX_TL .......................... 0x0 - IC_TX_CMD_BLOCK ................... 0x1 - IC_HAS_DMA ........................ 0x1 - IC_HAS_ASYNC_FIFO ................. 0x0 - IC_SMBUS_ARP ...................... 0x0 - IC_FIRST_DATA_BYTE_STATUS ......... 0x1 - IC_INTR_IO ........................ 0x1 - IC_MASTER_MODE .................... 0x1 - IC_DEFAULT_ACK_GENERAL_CALL ....... 0x1 - IC_INTR_POL ....................... 0x1 - IC_OPTIONAL_SAR ................... 0x0 - IC_DEFAULT_TAR_SLAVE_ADDR ......... 0x055 - IC_DEFAULT_SLAVE_ADDR ............. 0x055 - IC_DEFAULT_HS_SPKLEN .............. 0x1 - IC_FS_SCL_HIGH_COUNT .............. 0x0006 - IC_HS_SCL_LOW_COUNT ............... 0x0008 - IC_DEVICE_ID_VALUE ................ 0x0 - IC_10BITADDR_MASTER ............... 0x0 - IC_CLK_FREQ_OPTIMIZATION .......... 0x0 - IC_DEFAULT_FS_SPKLEN .............. 0x7 - IC_ADD_ENCODED_PARAMS ............. 0x0 - IC_DEFAULT_SDA_HOLD ............... 0x000001 - IC_DEFAULT_SDA_SETUP .............. 0x64 - IC_AVOID_RX_FIFO_FLUSH_ON_TX_ABRT . 0x0 - IC_CLOCK_PERIOD ................... 100 - IC_EMPTYFIFO_HOLD_MASTER_EN ....... 1 - IC_RESTART_EN ..................... 0x1 - IC_TX_CMD_BLOCK_DEFAULT ........... 0x0 - IC_BUS_CLEAR_FEATURE .............. 0x0 - IC_CAP_LOADING .................... 100 - IC_FS_SCL_LOW_COUNT ............... 0x000d - APB_DATA_WIDTH .................... 32 - IC_SDA_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff - IC_SLV_DATA_NACK_ONLY ............. 0x1 - IC_10BITADDR_SLAVE ................ 0x0 - IC_CLK_TYPE ....................... 0x0 - IC_SMBUS_UDID_MSB ................. 0x0 - IC_SMBUS_SUSPEND_ALERT ............ 0x0 - IC_HS_SCL_HIGH_COUNT .............. 0x0006 - IC_SLV_RESTART_DET_EN ............. 0x1 - IC_SMBUS .......................... 0x0 - IC_OPTIONAL_SAR_DEFAULT ........... 0x0 - IC_PERSISTANT_SLV_ADDR_DEFAULT .... 0x0 - IC_USE_COUNTS ..................... 0x0 - IC_RX_BUFFER_DEPTH ................ 16 - IC_SCL_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff - IC_RX_FULL_HLD_BUS_EN ............. 0x1 - IC_SLAVE_DISABLE .................. 0x1 - IC_RX_TL .......................... 0x0 - IC_DEVICE_ID ...................... 0x0 - IC_HC_COUNT_VALUES ................ 0x0 - I2C_DYNAMIC_TAR_UPDATE ............ 0 - IC_SMBUS_CLK_LOW_MEXT_DEFAULT ..... 0xffffffff - IC_SMBUS_CLK_LOW_SEXT_DEFAULT ..... 0xffffffff - IC_HS_MASTER_CODE ................. 0x1 - IC_SMBUS_RST_IDLE_CNT_DEFAULT ..... 0xffff - IC_SMBUS_UDID_LSB_DEFAULT ......... 0xffffffff - IC_SS_SCL_HIGH_COUNT .............. 0x0028 - IC_SS_SCL_LOW_COUNT ............... 0x002f - IC_MAX_SPEED_MODE ................. 0x2 - IC_STAT_FOR_CLK_STRETCH ........... 0x0 - IC_STOP_DET_IF_MASTER_ACTIVE ...... 0x0 - IC_DEFAULT_UFM_SPKLEN ............. 0x1 - IC_TX_BUFFER_DEPTH ................ 16 (I2C0) - */ - -typedef struct { /*!< I2C0 Structure */ - __IOM uint32_t IC_CON; /*!< I2C Control Register. This register can be written only when - the DW_apb_i2c is disabled, which corresponds to the IC_ENABLE[0] - register being set to 0. Writes at other times have no - effect. Read/Write Access: - bit 10 is read only. - bit - 11 is read only - bit 16 is read only - bit 17 is read - only - bits 18 and 19 are read only. */ - __IOM uint32_t IC_TAR; /*!< I2C Target Address Register This register is 12 bits wide, and - bits 31:12 are reserved. This register can be written to - only when IC_ENABLE[0] is set to 0. Note: If the software - or application is aware that the DW_apb_i2c is not using - the TAR address for the pending commands in the Tx FIFO, - then it is possible to update the TAR address even while - the Tx FIFO has entries (IC_STATUS[2]= 0). - It is not - necessary to perform any write to this register if DW_apb_i2c - is enabled as an I2C slave only. */ - __IOM uint32_t IC_SAR; /*!< I2C Slave Address Register */ - __IM uint32_t RESERVED; - __IOM uint32_t IC_DATA_CMD; /*!< I2C Rx/Tx Data Buffer and Command Register; this is the register - the CPU writes to when filling the TX FIFO and the CPU - reads from when retrieving bytes from RX FIFO. The size - of the register changes as follows: Write: - 11 bits when - IC_EMPTYFIFO_HOLD_MASTER_EN=1 - 9 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=0 - Read: - 12 bits when IC_FIRST_DATA_BYTE_STATUS = 1 - 8 - bits when IC_FIRST_DATA_BYTE_STATUS = 0 Note: In order - for the DW_apb_i2c to continue acknowledging reads, a read - command should be written for every byte that is to be - received; otherwise the DW_apb_i2c will stop acknowledging. */ - __IOM uint32_t IC_SS_SCL_HCNT; /*!< Standard Speed I2C Clock SCL High Count Register */ - __IOM uint32_t IC_SS_SCL_LCNT; /*!< Standard Speed I2C Clock SCL Low Count Register */ - __IOM uint32_t IC_FS_SCL_HCNT; /*!< Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register */ - __IOM uint32_t IC_FS_SCL_LCNT; /*!< Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register */ - __IM uint32_t RESERVED1[2]; - __IOM uint32_t IC_INTR_STAT; /*!< I2C Interrupt Status Register Each bit in this register has - a corresponding mask bit in the IC_INTR_MASK register. - These bits are cleared by reading the matching interrupt - clear register. The unmasked raw versions of these bits - are available in the IC_RAW_INTR_STAT register. */ - __IOM uint32_t IC_INTR_MASK; /*!< I2C Interrupt Mask Register. These bits mask their corresponding - interrupt status bits. This register is active low; a value - of 0 masks the interrupt, whereas a value of 1 unmasks - the interrupt. */ - __IOM uint32_t IC_RAW_INTR_STAT; /*!< I2C Raw Interrupt Status Register Unlike the IC_INTR_STAT register, - these bits are not masked so they always show the true - status of the DW_apb_i2c. */ - __IOM uint32_t IC_RX_TL; /*!< I2C Receive FIFO Threshold Register */ - __IOM uint32_t IC_TX_TL; /*!< I2C Transmit FIFO Threshold Register */ - __IOM uint32_t IC_CLR_INTR; /*!< Clear Combined and Individual Interrupt Register */ - __IOM uint32_t IC_CLR_RX_UNDER; /*!< Clear RX_UNDER Interrupt Register */ - __IOM uint32_t IC_CLR_RX_OVER; /*!< Clear RX_OVER Interrupt Register */ - __IOM uint32_t IC_CLR_TX_OVER; /*!< Clear TX_OVER Interrupt Register */ - __IOM uint32_t IC_CLR_RD_REQ; /*!< Clear RD_REQ Interrupt Register */ - __IOM uint32_t IC_CLR_TX_ABRT; /*!< Clear TX_ABRT Interrupt Register */ - __IOM uint32_t IC_CLR_RX_DONE; /*!< Clear RX_DONE Interrupt Register */ - __IOM uint32_t IC_CLR_ACTIVITY; /*!< Clear ACTIVITY Interrupt Register */ - __IOM uint32_t IC_CLR_STOP_DET; /*!< Clear STOP_DET Interrupt Register */ - __IOM uint32_t IC_CLR_START_DET; /*!< Clear START_DET Interrupt Register */ - __IOM uint32_t IC_CLR_GEN_CALL; /*!< Clear GEN_CALL Interrupt Register */ - __IOM uint32_t IC_ENABLE; /*!< I2C Enable Register */ - __IOM uint32_t IC_STATUS; /*!< I2C Status Register This is a read-only register used to indicate - the current transfer status and FIFO status. The status - register may be read at any time. None of the bits in this - register request an interrupt. When the I2C is disabled - by writing 0 in bit 0 of the IC_ENABLE register: - Bits - 1 and 2 are set to 1 - Bits 3 and 10 are set to 0 When - the master or slave state machines goes to idle and ic_en=0: - - Bits 5 and 6 are set to 0 */ - __IOM uint32_t IC_TXFLR; /*!< I2C Transmit FIFO Level Register This register contains the - number of valid data entries in the transmit FIFO buffer. - It is cleared whenever: - The I2C is disabled - There is - a transmit abort - that is, TX_ABRT bit is set in the IC_RAW_INTR_STAT - register - The slave bulk transmit mode is aborted The - register increments whenever data is placed into the transmit - FIFO and decrements when data is taken from the transmit - FIFO. */ - __IOM uint32_t IC_RXFLR; /*!< I2C Receive FIFO Level Register This register contains the number - of valid data entries in the receive FIFO buffer. It is - cleared whenever: - The I2C is disabled - Whenever there - is a transmit abort caused by any of the events tracked - in IC_TX_ABRT_SOURCE The register increments whenever data - is placed into the receive FIFO and decrements when data - is taken from the receive FIFO. */ - __IOM uint32_t IC_SDA_HOLD; /*!< I2C SDA Hold Time Length Register The bits [15:0] of this register - are used to control the hold time of SDA during transmit - in both slave and master mode (after SCL goes from HIGH - to LOW). The bits [23:16] of this register are used to - extend the SDA transition (if any) whenever SCL is HIGH - in the receiver in either master or slave mode. Writes - to this register succeed only when IC_ENABLE[0]=0. The - values in this register are in units of ic_clk period. - The value programmed in IC_SDA_TX_HOLD must be greater - than the minimum hold time in each mode (one cycle in master - mode, seven cycles in slave mode) for the value to be implemented. - The programmed SDA hold time during transmit (IC_SDA_TX_HOLD) - cannot exceed at any time the duration of the low part - of scl. Therefore the programmed value cannot be larger - than N_SCL_LOW-2, where N_SCL_LOW is the duration of the - low part of the scl period measured in ic_clk cycles. */ - __IOM uint32_t IC_TX_ABRT_SOURCE; /*!< I2C Transmit Abort Source Register This register has 32 bits - that indicate the source of the TX_ABRT bit. Except for - Bit 9, this register is cleared whenever the IC_CLR_TX_ABRT - register or the IC_CLR_INTR register is read. To clear - Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed - first; RESTART must be enabled (IC_CON[5]=1), the SPECIAL - bit must be cleared (IC_TAR[11]), or the GC_OR_START bit - must be cleared (IC_TAR[10]). Once the source of the ABRT_SBYTE_NORSTRT - is fixed, then this bit can be cleared in the same manner - as other bits in this register. If the source of the ABRT_SBYTE_NORSTRT - is not fixed before attempting to clear this bit, Bit 9 - clears for one cycle and is then re-asserted. */ - __IOM uint32_t IC_SLV_DATA_NACK_ONLY; /*!< Generate Slave Data NACK Register The register is used to generate - a NACK for the data part of a transfer when DW_apb_i2c - is acting as a slave-receiver. This register only exists - when the IC_SLV_DATA_NACK_ONLY parameter is set to 1. When - this parameter disabled, this register does not exist and - writing to the register's address has no effect. A write - can occur on this register if both of the following conditions - are met: - DW_apb_i2c is disabled (IC_ENABLE[0] = 0) - - Slave part is inactive (IC_STATUS[6] = 0) Note: The IC_STATUS[6] - is a register read-back location for the internal slv_activity - signal; the user should poll this before writing the ic_slv_data_nack_onl - bit. */ - __IOM uint32_t IC_DMA_CR; /*!< DMA Control Register The register is used to enable the DMA - Controller interface operation. There is a separate bit - for transmit and receive. This can be programmed regardless - of the state of IC_ENABLE. */ - __IOM uint32_t IC_DMA_TDLR; /*!< DMA Transmit Data Level Register */ - __IOM uint32_t IC_DMA_RDLR; /*!< I2C Receive Data Level Register */ - __IOM uint32_t IC_SDA_SETUP; /*!< I2C SDA Setup Register This register controls the amount of - time delay (in terms of number of ic_clk clock periods) - introduced in the rising edge of SCL - relative to SDA - changing - when DW_apb_i2c services a read request in a - slave-transmitter operation. The relevant I2C requirement - is tSU:DAT (note 4) as detailed in the I2C Bus Specification. - This register must be programmed with a value equal to - or greater than 2. Writes to this register succeed only - when IC_ENABLE[0] = 0. Note: The length of setup time is - calculated using [(IC_SDA_SETUP - 1) * (ic_clk_period)], - so if the user requires 10 ic_clk periods of setup time, - they should program a value of 11. The IC_SDA_SETUP register - is only used by the DW_apb_i2c when operating as a slave - transmitter. */ - __IOM uint32_t IC_ACK_GENERAL_CALL; /*!< I2C ACK General Call Register The register controls whether - DW_apb_i2c responds with a ACK or NACK when it receives - an I2C General Call address. This register is applicable - only when the DW_apb_i2c is in slave mode. */ - __IOM uint32_t IC_ENABLE_STATUS; /*!< I2C Enable Status Register The register is used to report the - DW_apb_i2c hardware status when the IC_ENABLE[0] register - is set from 1 to 0; that is, when DW_apb_i2c is disabled. - If IC_ENABLE[0] has been set to 1, bits 2:1 are forced - to 0, and bit 0 is forced to 1. If IC_ENABLE[0] has been - set to 0, bits 2:1 is only be valid as soon as bit 0 is - read as '0'. Note: When IC_ENABLE[0] has been set to 0, - a delay occurs for bit 0 to be read as 0 because disabling - the DW_apb_i2c depends on I2C bus activities. */ - __IOM uint32_t IC_FS_SPKLEN; /*!< I2C SS, FS or FM+ spike suppression limit This register is used - to store the duration, measured in ic_clk cycles, of the - longest spike that is filtered out by the spike suppression - logic when the component is operating in SS, FS or FM+ - modes. The relevant I2C requirement is tSP (table 4) as - detailed in the I2C Bus Specification. This register must - be programmed with a minimum value of 1. */ - __IM uint32_t RESERVED2; - __IOM uint32_t IC_CLR_RESTART_DET; /*!< Clear RESTART_DET Interrupt Register */ - __IM uint32_t RESERVED3[18]; - __IOM uint32_t IC_COMP_PARAM_1; /*!< Component Parameter Register 1 Note This register is not implemented - and therefore reads as 0. If it was implemented it would - be a constant read-only register that contains encoded - information about the component's parameter settings. Fields - shown below are the settings for those parameters */ - __IOM uint32_t IC_COMP_VERSION; /*!< I2C Component Version Register */ - __IOM uint32_t IC_COMP_TYPE; /*!< I2C Component Type Register */ -} I2C0_Type; /*!< Size = 256 (0x100) */ - - - -/* =========================================================================================================================== */ -/* ================ SPI0 ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief SPI0 (SPI0) - */ - -typedef struct { /*!< SPI0 Structure */ - __IOM uint32_t SSPCR0; /*!< Control register 0, SSPCR0 on page 3-4 */ - __IOM uint32_t SSPCR1; /*!< Control register 1, SSPCR1 on page 3-5 */ - __IOM uint32_t SSPDR; /*!< Data register, SSPDR on page 3-6 */ - __IOM uint32_t SSPSR; /*!< Status register, SSPSR on page 3-7 */ - __IOM uint32_t SSPCPSR; /*!< Clock prescale register, SSPCPSR on page 3-8 */ - __IOM uint32_t SSPIMSC; /*!< Interrupt mask set or clear register, SSPIMSC on page 3-9 */ - __IOM uint32_t SSPRIS; /*!< Raw interrupt status register, SSPRIS on page 3-10 */ - __IOM uint32_t SSPMIS; /*!< Masked interrupt status register, SSPMIS on page 3-11 */ - __IOM uint32_t SSPICR; /*!< Interrupt clear register, SSPICR on page 3-11 */ - __IOM uint32_t SSPDMACR; /*!< DMA control register, SSPDMACR on page 3-12 */ - __IM uint32_t RESERVED[1006]; - __IOM uint32_t SSPPERIPHID0; /*!< Peripheral identification registers, SSPPeriphID0-3 on page - 3-13 */ - __IOM uint32_t SSPPERIPHID1; /*!< Peripheral identification registers, SSPPeriphID0-3 on page - 3-13 */ - __IOM uint32_t SSPPERIPHID2; /*!< Peripheral identification registers, SSPPeriphID0-3 on page - 3-13 */ - __IOM uint32_t SSPPERIPHID3; /*!< Peripheral identification registers, SSPPeriphID0-3 on page - 3-13 */ - __IOM uint32_t SSPPCELLID0; /*!< PrimeCell identification registers, SSPPCellID0-3 on page 3-16 */ - __IOM uint32_t SSPPCELLID1; /*!< PrimeCell identification registers, SSPPCellID0-3 on page 3-16 */ - __IOM uint32_t SSPPCELLID2; /*!< PrimeCell identification registers, SSPPCellID0-3 on page 3-16 */ - __IOM uint32_t SSPPCELLID3; /*!< PrimeCell identification registers, SSPPCellID0-3 on page 3-16 */ -} SPI0_Type; /*!< Size = 4096 (0x1000) */ - - - -/* =========================================================================================================================== */ -/* ================ PIO0 ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief Programmable IO block (PIO0) - */ - -typedef struct { /*!< PIO0 Structure */ - __IOM uint32_t CTRL; /*!< PIO control register */ - __IOM uint32_t FSTAT; /*!< FIFO status register */ - __IOM uint32_t FDEBUG; /*!< FIFO debug register */ - __IOM uint32_t FLEVEL; /*!< FIFO levels */ - __IOM uint32_t TXF0; /*!< Direct write access to the TX FIFO for this state machine. Each - write pushes one word to the FIFO. Attempting to write - to a full FIFO has no effect on the FIFO state or contents, - and sets the sticky FDEBUG_TXOVER error flag for this FIFO. */ - __IOM uint32_t TXF1; /*!< Direct write access to the TX FIFO for this state machine. Each - write pushes one word to the FIFO. Attempting to write - to a full FIFO has no effect on the FIFO state or contents, - and sets the sticky FDEBUG_TXOVER error flag for this FIFO. */ - __IOM uint32_t TXF2; /*!< Direct write access to the TX FIFO for this state machine. Each - write pushes one word to the FIFO. Attempting to write - to a full FIFO has no effect on the FIFO state or contents, - and sets the sticky FDEBUG_TXOVER error flag for this FIFO. */ - __IOM uint32_t TXF3; /*!< Direct write access to the TX FIFO for this state machine. Each - write pushes one word to the FIFO. Attempting to write - to a full FIFO has no effect on the FIFO state or contents, - and sets the sticky FDEBUG_TXOVER error flag for this FIFO. */ - __IOM uint32_t RXF0; /*!< Direct read access to the RX FIFO for this state machine. Each - read pops one word from the FIFO. Attempting to read from - an empty FIFO has no effect on the FIFO state, and sets - the sticky FDEBUG_RXUNDER error flag for this FIFO. The - data returned to the system on a read from an empty FIFO - is undefined. */ - __IOM uint32_t RXF1; /*!< Direct read access to the RX FIFO for this state machine. Each - read pops one word from the FIFO. Attempting to read from - an empty FIFO has no effect on the FIFO state, and sets - the sticky FDEBUG_RXUNDER error flag for this FIFO. The - data returned to the system on a read from an empty FIFO - is undefined. */ - __IOM uint32_t RXF2; /*!< Direct read access to the RX FIFO for this state machine. Each - read pops one word from the FIFO. Attempting to read from - an empty FIFO has no effect on the FIFO state, and sets - the sticky FDEBUG_RXUNDER error flag for this FIFO. The - data returned to the system on a read from an empty FIFO - is undefined. */ - __IOM uint32_t RXF3; /*!< Direct read access to the RX FIFO for this state machine. Each - read pops one word from the FIFO. Attempting to read from - an empty FIFO has no effect on the FIFO state, and sets - the sticky FDEBUG_RXUNDER error flag for this FIFO. The - data returned to the system on a read from an empty FIFO - is undefined. */ - __IOM uint32_t IRQ; /*!< State machine IRQ flags register. Write 1 to clear. There are - 8 state machine IRQ flags, which can be set, cleared, and - waited on by the state machines. There's no fixed association - between flags and state machines -- any state machine can - use any flag. Any of the 8 flags can be used for timing - synchronisation between state machines, using IRQ and WAIT - instructions. The lower four of these flags are also routed - out to system-level interrupt requests, alongside FIFO - status interrupts -- see e.g. IRQ0_INTE. */ - __IOM uint32_t IRQ_FORCE; /*!< Writing a 1 to each of these bits will forcibly assert the corresponding - IRQ. Note this is different to the INTF register: writing - here affects PIO internal state. INTF just asserts the - processor-facing IRQ signal for testing ISRs, and is not - visible to the state machines. */ - __IOM uint32_t INPUT_SYNC_BYPASS; /*!< There is a 2-flipflop synchronizer on each GPIO input, which - protects PIO logic from metastabilities. This increases - input delay, and for fast synchronous IO (e.g. SPI) these - synchronizers may need to be bypassed. Each bit in this - register corresponds to one GPIO. 0 -> input is synchronized - (default) 1 -> synchronizer is bypassed If in doubt, leave - this register as all zeroes. */ - __IOM uint32_t DBG_PADOUT; /*!< Read to sample the pad output values PIO is currently driving - to the GPIOs. On RP2040 there are 30 GPIOs, so the two - most significant bits are hardwired to 0. */ - __IOM uint32_t DBG_PADOE; /*!< Read to sample the pad output enables (direction) PIO is currently - driving to the GPIOs. On RP2040 there are 30 GPIOs, so - the two most significant bits are hardwired to 0. */ - __IOM uint32_t DBG_CFGINFO; /*!< The PIO hardware has some free parameters that may vary between - chip products. These should be provided in the chip datasheet, - but are also exposed here. */ - __IOM uint32_t INSTR_MEM0; /*!< Write-only access to instruction memory location 0 */ - __IOM uint32_t INSTR_MEM1; /*!< Write-only access to instruction memory location 1 */ - __IOM uint32_t INSTR_MEM2; /*!< Write-only access to instruction memory location 2 */ - __IOM uint32_t INSTR_MEM3; /*!< Write-only access to instruction memory location 3 */ - __IOM uint32_t INSTR_MEM4; /*!< Write-only access to instruction memory location 4 */ - __IOM uint32_t INSTR_MEM5; /*!< Write-only access to instruction memory location 5 */ - __IOM uint32_t INSTR_MEM6; /*!< Write-only access to instruction memory location 6 */ - __IOM uint32_t INSTR_MEM7; /*!< Write-only access to instruction memory location 7 */ - __IOM uint32_t INSTR_MEM8; /*!< Write-only access to instruction memory location 8 */ - __IOM uint32_t INSTR_MEM9; /*!< Write-only access to instruction memory location 9 */ - __IOM uint32_t INSTR_MEM10; /*!< Write-only access to instruction memory location 10 */ - __IOM uint32_t INSTR_MEM11; /*!< Write-only access to instruction memory location 11 */ - __IOM uint32_t INSTR_MEM12; /*!< Write-only access to instruction memory location 12 */ - __IOM uint32_t INSTR_MEM13; /*!< Write-only access to instruction memory location 13 */ - __IOM uint32_t INSTR_MEM14; /*!< Write-only access to instruction memory location 14 */ - __IOM uint32_t INSTR_MEM15; /*!< Write-only access to instruction memory location 15 */ - __IOM uint32_t INSTR_MEM16; /*!< Write-only access to instruction memory location 16 */ - __IOM uint32_t INSTR_MEM17; /*!< Write-only access to instruction memory location 17 */ - __IOM uint32_t INSTR_MEM18; /*!< Write-only access to instruction memory location 18 */ - __IOM uint32_t INSTR_MEM19; /*!< Write-only access to instruction memory location 19 */ - __IOM uint32_t INSTR_MEM20; /*!< Write-only access to instruction memory location 20 */ - __IOM uint32_t INSTR_MEM21; /*!< Write-only access to instruction memory location 21 */ - __IOM uint32_t INSTR_MEM22; /*!< Write-only access to instruction memory location 22 */ - __IOM uint32_t INSTR_MEM23; /*!< Write-only access to instruction memory location 23 */ - __IOM uint32_t INSTR_MEM24; /*!< Write-only access to instruction memory location 24 */ - __IOM uint32_t INSTR_MEM25; /*!< Write-only access to instruction memory location 25 */ - __IOM uint32_t INSTR_MEM26; /*!< Write-only access to instruction memory location 26 */ - __IOM uint32_t INSTR_MEM27; /*!< Write-only access to instruction memory location 27 */ - __IOM uint32_t INSTR_MEM28; /*!< Write-only access to instruction memory location 28 */ - __IOM uint32_t INSTR_MEM29; /*!< Write-only access to instruction memory location 29 */ - __IOM uint32_t INSTR_MEM30; /*!< Write-only access to instruction memory location 30 */ - __IOM uint32_t INSTR_MEM31; /*!< Write-only access to instruction memory location 31 */ - __IOM uint32_t SM0_CLKDIV; /*!< Clock divisor register for state machine 0 Frequency = clock - freq / (CLKDIV_INT + CLKDIV_FRAC / 256) */ - __IOM uint32_t SM0_EXECCTRL; /*!< Execution/behavioural settings for state machine 0 */ - __IOM uint32_t SM0_SHIFTCTRL; /*!< Control behaviour of the input/output shift registers for state - machine 0 */ - __IOM uint32_t SM0_ADDR; /*!< Current instruction address of state machine 0 */ - __IOM uint32_t SM0_INSTR; /*!< Read to see the instruction currently addressed by state machine - 0's program counter Write to execute an instruction immediately - (including jumps) and then resume execution. */ - __IOM uint32_t SM0_PINCTRL; /*!< State machine pin control */ - __IOM uint32_t SM1_CLKDIV; /*!< Clock divisor register for state machine 1 Frequency = clock - freq / (CLKDIV_INT + CLKDIV_FRAC / 256) */ - __IOM uint32_t SM1_EXECCTRL; /*!< Execution/behavioural settings for state machine 1 */ - __IOM uint32_t SM1_SHIFTCTRL; /*!< Control behaviour of the input/output shift registers for state - machine 1 */ - __IOM uint32_t SM1_ADDR; /*!< Current instruction address of state machine 1 */ - __IOM uint32_t SM1_INSTR; /*!< Read to see the instruction currently addressed by state machine - 1's program counter Write to execute an instruction immediately - (including jumps) and then resume execution. */ - __IOM uint32_t SM1_PINCTRL; /*!< State machine pin control */ - __IOM uint32_t SM2_CLKDIV; /*!< Clock divisor register for state machine 2 Frequency = clock - freq / (CLKDIV_INT + CLKDIV_FRAC / 256) */ - __IOM uint32_t SM2_EXECCTRL; /*!< Execution/behavioural settings for state machine 2 */ - __IOM uint32_t SM2_SHIFTCTRL; /*!< Control behaviour of the input/output shift registers for state - machine 2 */ - __IOM uint32_t SM2_ADDR; /*!< Current instruction address of state machine 2 */ - __IOM uint32_t SM2_INSTR; /*!< Read to see the instruction currently addressed by state machine - 2's program counter Write to execute an instruction immediately - (including jumps) and then resume execution. */ - __IOM uint32_t SM2_PINCTRL; /*!< State machine pin control */ - __IOM uint32_t SM3_CLKDIV; /*!< Clock divisor register for state machine 3 Frequency = clock - freq / (CLKDIV_INT + CLKDIV_FRAC / 256) */ - __IOM uint32_t SM3_EXECCTRL; /*!< Execution/behavioural settings for state machine 3 */ - __IOM uint32_t SM3_SHIFTCTRL; /*!< Control behaviour of the input/output shift registers for state - machine 3 */ - __IOM uint32_t SM3_ADDR; /*!< Current instruction address of state machine 3 */ - __IOM uint32_t SM3_INSTR; /*!< Read to see the instruction currently addressed by state machine - 3's program counter Write to execute an instruction immediately - (including jumps) and then resume execution. */ - __IOM uint32_t SM3_PINCTRL; /*!< State machine pin control */ - __IOM uint32_t INTR; /*!< Raw Interrupts */ - __IOM uint32_t IRQ0_INTE; /*!< Interrupt Enable for irq0 */ - __IOM uint32_t IRQ0_INTF; /*!< Interrupt Force for irq0 */ - __IOM uint32_t IRQ0_INTS; /*!< Interrupt status after masking & forcing for irq0 */ - __IOM uint32_t IRQ1_INTE; /*!< Interrupt Enable for irq1 */ - __IOM uint32_t IRQ1_INTF; /*!< Interrupt Force for irq1 */ - __IOM uint32_t IRQ1_INTS; /*!< Interrupt status after masking & forcing for irq1 */ -} PIO0_Type; /*!< Size = 324 (0x144) */ - - - -/* =========================================================================================================================== */ -/* ================ BUSCTRL ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief Register block for busfabric control signals and performance counters (BUSCTRL) - */ - -typedef struct { /*!< BUSCTRL Structure */ - __IOM uint32_t BUS_PRIORITY; /*!< Set the priority of each master for bus arbitration. */ - __IOM uint32_t BUS_PRIORITY_ACK; /*!< Bus priority acknowledge */ - __IOM uint32_t PERFCTR0; /*!< Bus fabric performance counter 0 */ - __IOM uint32_t PERFSEL0; /*!< Bus fabric performance event select for PERFCTR0 */ - __IOM uint32_t PERFCTR1; /*!< Bus fabric performance counter 1 */ - __IOM uint32_t PERFSEL1; /*!< Bus fabric performance event select for PERFCTR1 */ - __IOM uint32_t PERFCTR2; /*!< Bus fabric performance counter 2 */ - __IOM uint32_t PERFSEL2; /*!< Bus fabric performance event select for PERFCTR2 */ - __IOM uint32_t PERFCTR3; /*!< Bus fabric performance counter 3 */ - __IOM uint32_t PERFSEL3; /*!< Bus fabric performance event select for PERFCTR3 */ -} BUSCTRL_Type; /*!< Size = 40 (0x28) */ - - - -/* =========================================================================================================================== */ -/* ================ SIO ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief Single-cycle IO block - Provides core-local and inter-core hardware for the two processors, with single-cycle access. (SIO) - */ - -typedef struct { /*!< SIO Structure */ - __IOM uint32_t CPUID; /*!< Processor core identifier */ - __IOM uint32_t GPIO_IN; /*!< Input value for GPIO pins */ - __IOM uint32_t GPIO_HI_IN; /*!< Input value for QSPI pins */ - __IM uint32_t RESERVED; - __IOM uint32_t GPIO_OUT; /*!< GPIO output value */ - __IOM uint32_t GPIO_OUT_SET; /*!< GPIO output value set */ - __IOM uint32_t GPIO_OUT_CLR; /*!< GPIO output value clear */ - __IOM uint32_t GPIO_OUT_XOR; /*!< GPIO output value XOR */ - __IOM uint32_t GPIO_OE; /*!< GPIO output enable */ - __IOM uint32_t GPIO_OE_SET; /*!< GPIO output enable set */ - __IOM uint32_t GPIO_OE_CLR; /*!< GPIO output enable clear */ - __IOM uint32_t GPIO_OE_XOR; /*!< GPIO output enable XOR */ - __IOM uint32_t GPIO_HI_OUT; /*!< QSPI output value */ - __IOM uint32_t GPIO_HI_OUT_SET; /*!< QSPI output value set */ - __IOM uint32_t GPIO_HI_OUT_CLR; /*!< QSPI output value clear */ - __IOM uint32_t GPIO_HI_OUT_XOR; /*!< QSPI output value XOR */ - __IOM uint32_t GPIO_HI_OE; /*!< QSPI output enable */ - __IOM uint32_t GPIO_HI_OE_SET; /*!< QSPI output enable set */ - __IOM uint32_t GPIO_HI_OE_CLR; /*!< QSPI output enable clear */ - __IOM uint32_t GPIO_HI_OE_XOR; /*!< QSPI output enable XOR */ - __IOM uint32_t FIFO_ST; /*!< Status register for inter-core FIFOs (mailboxes). There is one - FIFO in the core 0 -> core 1 direction, and one core 1 - -> core 0. Both are 32 bits wide and 8 words deep. Core - 0 can see the read side of the 1->0 FIFO (RX), and the - write side of 0->1 FIFO (TX). Core 1 can see the read side - of the 0->1 FIFO (RX), and the write side of 1->0 FIFO - (TX). The SIO IRQ for each core is the logical OR of the - VLD, WOF and ROE fields of its FIFO_ST register. */ - __IOM uint32_t FIFO_WR; /*!< Write access to this core's TX FIFO */ - __IOM uint32_t FIFO_RD; /*!< Read access to this core's RX FIFO */ - __IOM uint32_t SPINLOCK_ST; /*!< Spinlock state A bitmap containing the state of all 32 spinlocks - (1=locked). Mainly intended for debugging. */ - __IOM uint32_t DIV_UDIVIDEND; /*!< Divider unsigned dividend Write to the DIVIDEND operand of the - divider, i.e. the p in `p / q`. Any operand write starts - a new calculation. The results appear in QUOTIENT, REMAINDER. - UDIVIDEND/SDIVIDEND are aliases of the same internal register. - The U alias starts an unsigned calculation, and the S alias - starts a signed calculation. */ - __IOM uint32_t DIV_UDIVISOR; /*!< Divider unsigned divisor Write to the DIVISOR operand of the - divider, i.e. the q in `p / q`. Any operand write starts - a new calculation. The results appear in QUOTIENT, REMAINDER. - UDIVISOR/SDIVISOR are aliases of the same internal register. - The U alias starts an unsigned calculation, and the S alias - starts a signed calculation. */ - __IOM uint32_t DIV_SDIVIDEND; /*!< Divider signed dividend The same as UDIVIDEND, but starts a - signed calculation, rather than unsigned. */ - __IOM uint32_t DIV_SDIVISOR; /*!< Divider signed divisor The same as UDIVISOR, but starts a signed - calculation, rather than unsigned. */ - __IOM uint32_t DIV_QUOTIENT; /*!< Divider result quotient The result of `DIVIDEND / DIVISOR` (division). - Contents undefined while CSR_READY is low. For signed calculations, - QUOTIENT is negative when the signs of DIVIDEND and DIVISOR - differ. This register can be written to directly, for context - save/restore purposes. This halts any in-progress calculation - and sets the CSR_READY and CSR_DIRTY flags. Reading from - QUOTIENT clears the CSR_DIRTY flag, so should read results - in the order REMAINDER, QUOTIENT if CSR_DIRTY is used. */ - __IOM uint32_t DIV_REMAINDER; /*!< Divider result remainder The result of `DIVIDEND % DIVISOR` - (modulo). Contents undefined while CSR_READY is low. For - signed calculations, REMAINDER is negative only when DIVIDEND - is negative. This register can be written to directly, - for context save/restore purposes. This halts any in-progress - calculation and sets the CSR_READY and CSR_DIRTY flags. */ - __IOM uint32_t DIV_CSR; /*!< Control and status register for divider. */ - __IM uint32_t RESERVED1; - __IOM uint32_t INTERP0_ACCUM0; /*!< Read/write access to accumulator 0 */ - __IOM uint32_t INTERP0_ACCUM1; /*!< Read/write access to accumulator 1 */ - __IOM uint32_t INTERP0_BASE0; /*!< Read/write access to BASE0 register. */ - __IOM uint32_t INTERP0_BASE1; /*!< Read/write access to BASE1 register. */ - __IOM uint32_t INTERP0_BASE2; /*!< Read/write access to BASE2 register. */ - __IOM uint32_t INTERP0_POP_LANE0; /*!< Read LANE0 result, and simultaneously write lane results to - both accumulators (POP). */ - __IOM uint32_t INTERP0_POP_LANE1; /*!< Read LANE1 result, and simultaneously write lane results to - both accumulators (POP). */ - __IOM uint32_t INTERP0_POP_FULL; /*!< Read FULL result, and simultaneously write lane results to both - accumulators (POP). */ - __IOM uint32_t INTERP0_PEEK_LANE0; /*!< Read LANE0 result, without altering any internal state (PEEK). */ - __IOM uint32_t INTERP0_PEEK_LANE1; /*!< Read LANE1 result, without altering any internal state (PEEK). */ - __IOM uint32_t INTERP0_PEEK_FULL; /*!< Read FULL result, without altering any internal state (PEEK). */ - __IOM uint32_t INTERP0_CTRL_LANE0; /*!< Control register for lane 0 */ - __IOM uint32_t INTERP0_CTRL_LANE1; /*!< Control register for lane 1 */ - __IOM uint32_t INTERP0_ACCUM0_ADD; /*!< Values written here are atomically added to ACCUM0 Reading yields - lane 0's raw shift and mask value (BASE0 not added). */ - __IOM uint32_t INTERP0_ACCUM1_ADD; /*!< Values written here are atomically added to ACCUM1 Reading yields - lane 1's raw shift and mask value (BASE1 not added). */ - __IOM uint32_t INTERP0_BASE_1AND0; /*!< On write, the lower 16 bits go to BASE0, upper bits to BASE1 - simultaneously. Each half is sign-extended to 32 bits if - that lane's SIGNED flag is set. */ - __IOM uint32_t INTERP1_ACCUM0; /*!< Read/write access to accumulator 0 */ - __IOM uint32_t INTERP1_ACCUM1; /*!< Read/write access to accumulator 1 */ - __IOM uint32_t INTERP1_BASE0; /*!< Read/write access to BASE0 register. */ - __IOM uint32_t INTERP1_BASE1; /*!< Read/write access to BASE1 register. */ - __IOM uint32_t INTERP1_BASE2; /*!< Read/write access to BASE2 register. */ - __IOM uint32_t INTERP1_POP_LANE0; /*!< Read LANE0 result, and simultaneously write lane results to - both accumulators (POP). */ - __IOM uint32_t INTERP1_POP_LANE1; /*!< Read LANE1 result, and simultaneously write lane results to - both accumulators (POP). */ - __IOM uint32_t INTERP1_POP_FULL; /*!< Read FULL result, and simultaneously write lane results to both - accumulators (POP). */ - __IOM uint32_t INTERP1_PEEK_LANE0; /*!< Read LANE0 result, without altering any internal state (PEEK). */ - __IOM uint32_t INTERP1_PEEK_LANE1; /*!< Read LANE1 result, without altering any internal state (PEEK). */ - __IOM uint32_t INTERP1_PEEK_FULL; /*!< Read FULL result, without altering any internal state (PEEK). */ - __IOM uint32_t INTERP1_CTRL_LANE0; /*!< Control register for lane 0 */ - __IOM uint32_t INTERP1_CTRL_LANE1; /*!< Control register for lane 1 */ - __IOM uint32_t INTERP1_ACCUM0_ADD; /*!< Values written here are atomically added to ACCUM0 Reading yields - lane 0's raw shift and mask value (BASE0 not added). */ - __IOM uint32_t INTERP1_ACCUM1_ADD; /*!< Values written here are atomically added to ACCUM1 Reading yields - lane 1's raw shift and mask value (BASE1 not added). */ - __IOM uint32_t INTERP1_BASE_1AND0; /*!< On write, the lower 16 bits go to BASE0, upper bits to BASE1 - simultaneously. Each half is sign-extended to 32 bits if - that lane's SIGNED flag is set. */ - __IOM uint32_t SPINLOCK0; /*!< Reading from a spinlock address will: - Return 0 if lock is - already locked - Otherwise return nonzero, and simultaneously - claim the lock Writing (any value) releases the lock. If - core 0 and core 1 attempt to claim the same lock simultaneously, - core 0 wins. The value returned on success is 0x1 << lock - number. */ - __IOM uint32_t SPINLOCK1; /*!< Reading from a spinlock address will: - Return 0 if lock is - already locked - Otherwise return nonzero, and simultaneously - claim the lock Writing (any value) releases the lock. If - core 0 and core 1 attempt to claim the same lock simultaneously, - core 0 wins. The value returned on success is 0x1 << lock - number. */ - __IOM uint32_t SPINLOCK2; /*!< Reading from a spinlock address will: - Return 0 if lock is - already locked - Otherwise return nonzero, and simultaneously - claim the lock Writing (any value) releases the lock. If - core 0 and core 1 attempt to claim the same lock simultaneously, - core 0 wins. The value returned on success is 0x1 << lock - number. */ - __IOM uint32_t SPINLOCK3; /*!< Reading from a spinlock address will: - Return 0 if lock is - already locked - Otherwise return nonzero, and simultaneously - claim the lock Writing (any value) releases the lock. If - core 0 and core 1 attempt to claim the same lock simultaneously, - core 0 wins. The value returned on success is 0x1 << lock - number. */ - __IOM uint32_t SPINLOCK4; /*!< Reading from a spinlock address will: - Return 0 if lock is - already locked - Otherwise return nonzero, and simultaneously - claim the lock Writing (any value) releases the lock. If - core 0 and core 1 attempt to claim the same lock simultaneously, - core 0 wins. The value returned on success is 0x1 << lock - number. */ - __IOM uint32_t SPINLOCK5; /*!< Reading from a spinlock address will: - Return 0 if lock is - already locked - Otherwise return nonzero, and simultaneously - claim the lock Writing (any value) releases the lock. If - core 0 and core 1 attempt to claim the same lock simultaneously, - core 0 wins. The value returned on success is 0x1 << lock - number. */ - __IOM uint32_t SPINLOCK6; /*!< Reading from a spinlock address will: - Return 0 if lock is - already locked - Otherwise return nonzero, and simultaneously - claim the lock Writing (any value) releases the lock. If - core 0 and core 1 attempt to claim the same lock simultaneously, - core 0 wins. The value returned on success is 0x1 << lock - number. */ - __IOM uint32_t SPINLOCK7; /*!< Reading from a spinlock address will: - Return 0 if lock is - already locked - Otherwise return nonzero, and simultaneously - claim the lock Writing (any value) releases the lock. If - core 0 and core 1 attempt to claim the same lock simultaneously, - core 0 wins. The value returned on success is 0x1 << lock - number. */ - __IOM uint32_t SPINLOCK8; /*!< Reading from a spinlock address will: - Return 0 if lock is - already locked - Otherwise return nonzero, and simultaneously - claim the lock Writing (any value) releases the lock. If - core 0 and core 1 attempt to claim the same lock simultaneously, - core 0 wins. The value returned on success is 0x1 << lock - number. */ - __IOM uint32_t SPINLOCK9; /*!< Reading from a spinlock address will: - Return 0 if lock is - already locked - Otherwise return nonzero, and simultaneously - claim the lock Writing (any value) releases the lock. If - core 0 and core 1 attempt to claim the same lock simultaneously, - core 0 wins. The value returned on success is 0x1 << lock - number. */ - __IOM uint32_t SPINLOCK10; /*!< Reading from a spinlock address will: - Return 0 if lock is - already locked - Otherwise return nonzero, and simultaneously - claim the lock Writing (any value) releases the lock. If - core 0 and core 1 attempt to claim the same lock simultaneously, - core 0 wins. The value returned on success is 0x1 << lock - number. */ - __IOM uint32_t SPINLOCK11; /*!< Reading from a spinlock address will: - Return 0 if lock is - already locked - Otherwise return nonzero, and simultaneously - claim the lock Writing (any value) releases the lock. If - core 0 and core 1 attempt to claim the same lock simultaneously, - core 0 wins. The value returned on success is 0x1 << lock - number. */ - __IOM uint32_t SPINLOCK12; /*!< Reading from a spinlock address will: - Return 0 if lock is - already locked - Otherwise return nonzero, and simultaneously - claim the lock Writing (any value) releases the lock. If - core 0 and core 1 attempt to claim the same lock simultaneously, - core 0 wins. The value returned on success is 0x1 << lock - number. */ - __IOM uint32_t SPINLOCK13; /*!< Reading from a spinlock address will: - Return 0 if lock is - already locked - Otherwise return nonzero, and simultaneously - claim the lock Writing (any value) releases the lock. If - core 0 and core 1 attempt to claim the same lock simultaneously, - core 0 wins. The value returned on success is 0x1 << lock - number. */ - __IOM uint32_t SPINLOCK14; /*!< Reading from a spinlock address will: - Return 0 if lock is - already locked - Otherwise return nonzero, and simultaneously - claim the lock Writing (any value) releases the lock. If - core 0 and core 1 attempt to claim the same lock simultaneously, - core 0 wins. The value returned on success is 0x1 << lock - number. */ - __IOM uint32_t SPINLOCK15; /*!< Reading from a spinlock address will: - Return 0 if lock is - already locked - Otherwise return nonzero, and simultaneously - claim the lock Writing (any value) releases the lock. If - core 0 and core 1 attempt to claim the same lock simultaneously, - core 0 wins. The value returned on success is 0x1 << lock - number. */ - __IOM uint32_t SPINLOCK16; /*!< Reading from a spinlock address will: - Return 0 if lock is - already locked - Otherwise return nonzero, and simultaneously - claim the lock Writing (any value) releases the lock. If - core 0 and core 1 attempt to claim the same lock simultaneously, - core 0 wins. The value returned on success is 0x1 << lock - number. */ - __IOM uint32_t SPINLOCK17; /*!< Reading from a spinlock address will: - Return 0 if lock is - already locked - Otherwise return nonzero, and simultaneously - claim the lock Writing (any value) releases the lock. If - core 0 and core 1 attempt to claim the same lock simultaneously, - core 0 wins. The value returned on success is 0x1 << lock - number. */ - __IOM uint32_t SPINLOCK18; /*!< Reading from a spinlock address will: - Return 0 if lock is - already locked - Otherwise return nonzero, and simultaneously - claim the lock Writing (any value) releases the lock. If - core 0 and core 1 attempt to claim the same lock simultaneously, - core 0 wins. The value returned on success is 0x1 << lock - number. */ - __IOM uint32_t SPINLOCK19; /*!< Reading from a spinlock address will: - Return 0 if lock is - already locked - Otherwise return nonzero, and simultaneously - claim the lock Writing (any value) releases the lock. If - core 0 and core 1 attempt to claim the same lock simultaneously, - core 0 wins. The value returned on success is 0x1 << lock - number. */ - __IOM uint32_t SPINLOCK20; /*!< Reading from a spinlock address will: - Return 0 if lock is - already locked - Otherwise return nonzero, and simultaneously - claim the lock Writing (any value) releases the lock. If - core 0 and core 1 attempt to claim the same lock simultaneously, - core 0 wins. The value returned on success is 0x1 << lock - number. */ - __IOM uint32_t SPINLOCK21; /*!< Reading from a spinlock address will: - Return 0 if lock is - already locked - Otherwise return nonzero, and simultaneously - claim the lock Writing (any value) releases the lock. If - core 0 and core 1 attempt to claim the same lock simultaneously, - core 0 wins. The value returned on success is 0x1 << lock - number. */ - __IOM uint32_t SPINLOCK22; /*!< Reading from a spinlock address will: - Return 0 if lock is - already locked - Otherwise return nonzero, and simultaneously - claim the lock Writing (any value) releases the lock. If - core 0 and core 1 attempt to claim the same lock simultaneously, - core 0 wins. The value returned on success is 0x1 << lock - number. */ - __IOM uint32_t SPINLOCK23; /*!< Reading from a spinlock address will: - Return 0 if lock is - already locked - Otherwise return nonzero, and simultaneously - claim the lock Writing (any value) releases the lock. If - core 0 and core 1 attempt to claim the same lock simultaneously, - core 0 wins. The value returned on success is 0x1 << lock - number. */ - __IOM uint32_t SPINLOCK24; /*!< Reading from a spinlock address will: - Return 0 if lock is - already locked - Otherwise return nonzero, and simultaneously - claim the lock Writing (any value) releases the lock. If - core 0 and core 1 attempt to claim the same lock simultaneously, - core 0 wins. The value returned on success is 0x1 << lock - number. */ - __IOM uint32_t SPINLOCK25; /*!< Reading from a spinlock address will: - Return 0 if lock is - already locked - Otherwise return nonzero, and simultaneously - claim the lock Writing (any value) releases the lock. If - core 0 and core 1 attempt to claim the same lock simultaneously, - core 0 wins. The value returned on success is 0x1 << lock - number. */ - __IOM uint32_t SPINLOCK26; /*!< Reading from a spinlock address will: - Return 0 if lock is - already locked - Otherwise return nonzero, and simultaneously - claim the lock Writing (any value) releases the lock. If - core 0 and core 1 attempt to claim the same lock simultaneously, - core 0 wins. The value returned on success is 0x1 << lock - number. */ - __IOM uint32_t SPINLOCK27; /*!< Reading from a spinlock address will: - Return 0 if lock is - already locked - Otherwise return nonzero, and simultaneously - claim the lock Writing (any value) releases the lock. If - core 0 and core 1 attempt to claim the same lock simultaneously, - core 0 wins. The value returned on success is 0x1 << lock - number. */ - __IOM uint32_t SPINLOCK28; /*!< Reading from a spinlock address will: - Return 0 if lock is - already locked - Otherwise return nonzero, and simultaneously - claim the lock Writing (any value) releases the lock. If - core 0 and core 1 attempt to claim the same lock simultaneously, - core 0 wins. The value returned on success is 0x1 << lock - number. */ - __IOM uint32_t SPINLOCK29; /*!< Reading from a spinlock address will: - Return 0 if lock is - already locked - Otherwise return nonzero, and simultaneously - claim the lock Writing (any value) releases the lock. If - core 0 and core 1 attempt to claim the same lock simultaneously, - core 0 wins. The value returned on success is 0x1 << lock - number. */ - __IOM uint32_t SPINLOCK30; /*!< Reading from a spinlock address will: - Return 0 if lock is - already locked - Otherwise return nonzero, and simultaneously - claim the lock Writing (any value) releases the lock. If - core 0 and core 1 attempt to claim the same lock simultaneously, - core 0 wins. The value returned on success is 0x1 << lock - number. */ - __IOM uint32_t SPINLOCK31; /*!< Reading from a spinlock address will: - Return 0 if lock is - already locked - Otherwise return nonzero, and simultaneously - claim the lock Writing (any value) releases the lock. If - core 0 and core 1 attempt to claim the same lock simultaneously, - core 0 wins. The value returned on success is 0x1 << lock - number. */ -} SIO_Type; /*!< Size = 384 (0x180) */ - - - -/* =========================================================================================================================== */ -/* ================ USB ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief USB FS/LS controller device registers (USB) - */ - -typedef struct { /*!< USB Structure */ - __IOM uint32_t ADDR_ENDP; /*!< Device address and endpoint control */ - __IOM uint32_t ADDR_ENDP1; /*!< Interrupt endpoint 1. Only valid for HOST mode. */ - __IOM uint32_t ADDR_ENDP2; /*!< Interrupt endpoint 2. Only valid for HOST mode. */ - __IOM uint32_t ADDR_ENDP3; /*!< Interrupt endpoint 3. Only valid for HOST mode. */ - __IOM uint32_t ADDR_ENDP4; /*!< Interrupt endpoint 4. Only valid for HOST mode. */ - __IOM uint32_t ADDR_ENDP5; /*!< Interrupt endpoint 5. Only valid for HOST mode. */ - __IOM uint32_t ADDR_ENDP6; /*!< Interrupt endpoint 6. Only valid for HOST mode. */ - __IOM uint32_t ADDR_ENDP7; /*!< Interrupt endpoint 7. Only valid for HOST mode. */ - __IOM uint32_t ADDR_ENDP8; /*!< Interrupt endpoint 8. Only valid for HOST mode. */ - __IOM uint32_t ADDR_ENDP9; /*!< Interrupt endpoint 9. Only valid for HOST mode. */ - __IOM uint32_t ADDR_ENDP10; /*!< Interrupt endpoint 10. Only valid for HOST mode. */ - __IOM uint32_t ADDR_ENDP11; /*!< Interrupt endpoint 11. Only valid for HOST mode. */ - __IOM uint32_t ADDR_ENDP12; /*!< Interrupt endpoint 12. Only valid for HOST mode. */ - __IOM uint32_t ADDR_ENDP13; /*!< Interrupt endpoint 13. Only valid for HOST mode. */ - __IOM uint32_t ADDR_ENDP14; /*!< Interrupt endpoint 14. Only valid for HOST mode. */ - __IOM uint32_t ADDR_ENDP15; /*!< Interrupt endpoint 15. Only valid for HOST mode. */ - __IOM uint32_t MAIN_CTRL; /*!< Main control register */ - __IOM uint32_t SOF_WR; /*!< Set the SOF (Start of Frame) frame number in the host controller. - The SOF packet is sent every 1ms and the host will increment - the frame number by 1 each time. */ - __IOM uint32_t SOF_RD; /*!< Read the last SOF (Start of Frame) frame number seen. In device - mode the last SOF received from the host. In host mode - the last SOF sent by the host. */ - __IOM uint32_t SIE_CTRL; /*!< SIE control register */ - __IOM uint32_t SIE_STATUS; /*!< SIE status register */ - __IOM uint32_t INT_EP_CTRL; /*!< interrupt endpoint control register */ - __IOM uint32_t BUFF_STATUS; /*!< Buffer status register. A bit set here indicates that a buffer - has completed on the endpoint (if the buffer interrupt - is enabled). It is possible for 2 buffers to be completed, - so clearing the buffer status bit may instantly re set - it on the next clock cycle. */ - __IOM uint32_t BUFF_CPU_SHOULD_HANDLE; /*!< Which of the double buffers should be handled. Only valid if - using an interrupt per buffer (i.e. not per 2 buffers). - Not valid for host interrupt endpoint polling because they - are only single buffered. */ - __IOM uint32_t EP_ABORT; /*!< Device only: Can be set to ignore the buffer control register - for this endpoint in case you would like to revoke a buffer. - A NAK will be sent for every access to the endpoint until - this bit is cleared. A corresponding bit in `EP_ABORT_DONE` - is set when it is safe to modify the buffer control register. */ - __IOM uint32_t EP_ABORT_DONE; /*!< Device only: Used in conjunction with `EP_ABORT`. Set once an - endpoint is idle so the programmer knows it is safe to - modify the buffer control register. */ - __IOM uint32_t EP_STALL_ARM; /*!< Device: this bit must be set in conjunction with the `STALL` - bit in the buffer control register to send a STALL on EP0. - The device controller clears these bits when a SETUP packet - is received because the USB spec requires that a STALL - condition is cleared when a SETUP packet is received. */ - __IOM uint32_t NAK_POLL; /*!< Used by the host controller. Sets the wait time in microseconds - before trying again if the device replies with a NAK. */ - __IOM uint32_t EP_STATUS_STALL_NAK; /*!< Device: bits are set when the `IRQ_ON_NAK` or `IRQ_ON_STALL` - bits are set. For EP0 this comes from `SIE_CTRL`. For all - other endpoints it comes from the endpoint control register. */ - __IOM uint32_t USB_MUXING; /*!< Where to connect the USB controller. Should be to_phy by default. */ - __IOM uint32_t USB_PWR; /*!< Overrides for the power signals in the event that the VBUS signals - are not hooked up to GPIO. Set the value of the override - and then the override enable so switch over to the override - value. */ - __IOM uint32_t USBPHY_DIRECT; /*!< Note that most functions are driven directly from usb_fsls controller. - This register allows more detailed control/status from - the USB PHY. Useful for debug but not expected to be used - in normal operation Use in conjunction with usbphy_direct_override - register */ - __IOM uint32_t USBPHY_DIRECT_OVERRIDE; /*!< USBPHY_DIRECT_OVERRIDE */ - __IOM uint32_t USBPHY_TRIM; /*!< Note that most functions are driven directly from usb_fsls controller. - This register allows more detailed control/status from - the USB PHY. Useful for debug but not expected to be used - in normal operation */ - __IM uint32_t RESERVED; - __IOM uint32_t INTR; /*!< Raw Interrupts */ - __IOM uint32_t INTE; /*!< Interrupt Enable */ - __IOM uint32_t INTF; /*!< Interrupt Force */ - __IOM uint32_t INTS; /*!< Interrupt status after masking & forcing */ -} USB_Type; /*!< Size = 156 (0x9c) */ - - - -/* =========================================================================================================================== */ -/* ================ USB_DPRAM ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief DPRAM layout for USB device. (USB_DPRAM) - */ - -typedef struct { /*!< USB_DPRAM Structure */ - __IOM uint32_t SETUP_PACKET_LOW; /*!< Bytes 0-3 of the SETUP packet from the host. */ - __IOM uint32_t SETUP_PACKET_HIGH; /*!< Bytes 4-7 of the setup packet from the host. */ - __IOM uint32_t EP1_IN_CONTROL; /*!< EP1_IN_CONTROL */ - __IOM uint32_t EP1_OUT_CONTROL; /*!< EP1_OUT_CONTROL */ - __IOM uint32_t EP2_IN_CONTROL; /*!< EP2_IN_CONTROL */ - __IOM uint32_t EP2_OUT_CONTROL; /*!< EP2_OUT_CONTROL */ - __IOM uint32_t EP3_IN_CONTROL; /*!< EP3_IN_CONTROL */ - __IOM uint32_t EP3_OUT_CONTROL; /*!< EP3_OUT_CONTROL */ - __IOM uint32_t EP4_IN_CONTROL; /*!< EP4_IN_CONTROL */ - __IOM uint32_t EP4_OUT_CONTROL; /*!< EP4_OUT_CONTROL */ - __IOM uint32_t EP5_IN_CONTROL; /*!< EP5_IN_CONTROL */ - __IOM uint32_t EP5_OUT_CONTROL; /*!< EP5_OUT_CONTROL */ - __IOM uint32_t EP6_IN_CONTROL; /*!< EP6_IN_CONTROL */ - __IOM uint32_t EP6_OUT_CONTROL; /*!< EP6_OUT_CONTROL */ - __IOM uint32_t EP7_IN_CONTROL; /*!< EP7_IN_CONTROL */ - __IOM uint32_t EP7_OUT_CONTROL; /*!< EP7_OUT_CONTROL */ - __IOM uint32_t EP8_IN_CONTROL; /*!< EP8_IN_CONTROL */ - __IOM uint32_t EP8_OUT_CONTROL; /*!< EP8_OUT_CONTROL */ - __IOM uint32_t EP9_IN_CONTROL; /*!< EP9_IN_CONTROL */ - __IOM uint32_t EP9_OUT_CONTROL; /*!< EP9_OUT_CONTROL */ - __IOM uint32_t EP10_IN_CONTROL; /*!< EP10_IN_CONTROL */ - __IOM uint32_t EP10_OUT_CONTROL; /*!< EP10_OUT_CONTROL */ - __IOM uint32_t EP11_IN_CONTROL; /*!< EP11_IN_CONTROL */ - __IOM uint32_t EP11_OUT_CONTROL; /*!< EP11_OUT_CONTROL */ - __IOM uint32_t EP12_IN_CONTROL; /*!< EP12_IN_CONTROL */ - __IOM uint32_t EP12_OUT_CONTROL; /*!< EP12_OUT_CONTROL */ - __IOM uint32_t EP13_IN_CONTROL; /*!< EP13_IN_CONTROL */ - __IOM uint32_t EP13_OUT_CONTROL; /*!< EP13_OUT_CONTROL */ - __IOM uint32_t EP14_IN_CONTROL; /*!< EP14_IN_CONTROL */ - __IOM uint32_t EP14_OUT_CONTROL; /*!< EP14_OUT_CONTROL */ - __IOM uint32_t EP15_IN_CONTROL; /*!< EP15_IN_CONTROL */ - __IOM uint32_t EP15_OUT_CONTROL; /*!< EP15_OUT_CONTROL */ - __IOM uint32_t EP0_IN_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending - in a _1 are for buffer 1. Fields ending in a _0 are for - buffer 0. Buffer 1 controls are only valid if the endpoint - is in double buffered mode. */ - __IOM uint32_t EP0_OUT_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending - in a _1 are for buffer 1. Fields ending in a _0 are for - buffer 0. Buffer 1 controls are only valid if the endpoint - is in double buffered mode. */ - __IOM uint32_t EP1_IN_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending - in a _1 are for buffer 1. Fields ending in a _0 are for - buffer 0. Buffer 1 controls are only valid if the endpoint - is in double buffered mode. */ - __IOM uint32_t EP1_OUT_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending - in a _1 are for buffer 1. Fields ending in a _0 are for - buffer 0. Buffer 1 controls are only valid if the endpoint - is in double buffered mode. */ - __IOM uint32_t EP2_IN_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending - in a _1 are for buffer 1. Fields ending in a _0 are for - buffer 0. Buffer 1 controls are only valid if the endpoint - is in double buffered mode. */ - __IOM uint32_t EP2_OUT_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending - in a _1 are for buffer 1. Fields ending in a _0 are for - buffer 0. Buffer 1 controls are only valid if the endpoint - is in double buffered mode. */ - __IOM uint32_t EP3_IN_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending - in a _1 are for buffer 1. Fields ending in a _0 are for - buffer 0. Buffer 1 controls are only valid if the endpoint - is in double buffered mode. */ - __IOM uint32_t EP3_OUT_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending - in a _1 are for buffer 1. Fields ending in a _0 are for - buffer 0. Buffer 1 controls are only valid if the endpoint - is in double buffered mode. */ - __IOM uint32_t EP4_IN_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending - in a _1 are for buffer 1. Fields ending in a _0 are for - buffer 0. Buffer 1 controls are only valid if the endpoint - is in double buffered mode. */ - __IOM uint32_t EP4_OUT_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending - in a _1 are for buffer 1. Fields ending in a _0 are for - buffer 0. Buffer 1 controls are only valid if the endpoint - is in double buffered mode. */ - __IOM uint32_t EP5_IN_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending - in a _1 are for buffer 1. Fields ending in a _0 are for - buffer 0. Buffer 1 controls are only valid if the endpoint - is in double buffered mode. */ - __IOM uint32_t EP5_OUT_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending - in a _1 are for buffer 1. Fields ending in a _0 are for - buffer 0. Buffer 1 controls are only valid if the endpoint - is in double buffered mode. */ - __IOM uint32_t EP6_IN_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending - in a _1 are for buffer 1. Fields ending in a _0 are for - buffer 0. Buffer 1 controls are only valid if the endpoint - is in double buffered mode. */ - __IOM uint32_t EP6_OUT_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending - in a _1 are for buffer 1. Fields ending in a _0 are for - buffer 0. Buffer 1 controls are only valid if the endpoint - is in double buffered mode. */ - __IOM uint32_t EP7_IN_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending - in a _1 are for buffer 1. Fields ending in a _0 are for - buffer 0. Buffer 1 controls are only valid if the endpoint - is in double buffered mode. */ - __IOM uint32_t EP7_OUT_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending - in a _1 are for buffer 1. Fields ending in a _0 are for - buffer 0. Buffer 1 controls are only valid if the endpoint - is in double buffered mode. */ - __IOM uint32_t EP8_IN_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending - in a _1 are for buffer 1. Fields ending in a _0 are for - buffer 0. Buffer 1 controls are only valid if the endpoint - is in double buffered mode. */ - __IOM uint32_t EP8_OUT_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending - in a _1 are for buffer 1. Fields ending in a _0 are for - buffer 0. Buffer 1 controls are only valid if the endpoint - is in double buffered mode. */ - __IOM uint32_t EP9_IN_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending - in a _1 are for buffer 1. Fields ending in a _0 are for - buffer 0. Buffer 1 controls are only valid if the endpoint - is in double buffered mode. */ - __IOM uint32_t EP9_OUT_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending - in a _1 are for buffer 1. Fields ending in a _0 are for - buffer 0. Buffer 1 controls are only valid if the endpoint - is in double buffered mode. */ - __IOM uint32_t EP10_IN_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending - in a _1 are for buffer 1. Fields ending in a _0 are for - buffer 0. Buffer 1 controls are only valid if the endpoint - is in double buffered mode. */ - __IOM uint32_t EP10_OUT_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending - in a _1 are for buffer 1. Fields ending in a _0 are for - buffer 0. Buffer 1 controls are only valid if the endpoint - is in double buffered mode. */ - __IOM uint32_t EP11_IN_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending - in a _1 are for buffer 1. Fields ending in a _0 are for - buffer 0. Buffer 1 controls are only valid if the endpoint - is in double buffered mode. */ - __IOM uint32_t EP11_OUT_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending - in a _1 are for buffer 1. Fields ending in a _0 are for - buffer 0. Buffer 1 controls are only valid if the endpoint - is in double buffered mode. */ - __IOM uint32_t EP12_IN_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending - in a _1 are for buffer 1. Fields ending in a _0 are for - buffer 0. Buffer 1 controls are only valid if the endpoint - is in double buffered mode. */ - __IOM uint32_t EP12_OUT_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending - in a _1 are for buffer 1. Fields ending in a _0 are for - buffer 0. Buffer 1 controls are only valid if the endpoint - is in double buffered mode. */ - __IOM uint32_t EP13_IN_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending - in a _1 are for buffer 1. Fields ending in a _0 are for - buffer 0. Buffer 1 controls are only valid if the endpoint - is in double buffered mode. */ - __IOM uint32_t EP13_OUT_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending - in a _1 are for buffer 1. Fields ending in a _0 are for - buffer 0. Buffer 1 controls are only valid if the endpoint - is in double buffered mode. */ - __IOM uint32_t EP14_IN_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending - in a _1 are for buffer 1. Fields ending in a _0 are for - buffer 0. Buffer 1 controls are only valid if the endpoint - is in double buffered mode. */ - __IOM uint32_t EP14_OUT_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending - in a _1 are for buffer 1. Fields ending in a _0 are for - buffer 0. Buffer 1 controls are only valid if the endpoint - is in double buffered mode. */ - __IOM uint32_t EP15_IN_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending - in a _1 are for buffer 1. Fields ending in a _0 are for - buffer 0. Buffer 1 controls are only valid if the endpoint - is in double buffered mode. */ - __IOM uint32_t EP15_OUT_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending - in a _1 are for buffer 1. Fields ending in a _0 are for - buffer 0. Buffer 1 controls are only valid if the endpoint - is in double buffered mode. */ -} USB_DPRAM_Type; /*!< Size = 256 (0x100) */ - - - -/* =========================================================================================================================== */ -/* ================ TBMAN ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief Testbench manager. Allows the programmer to know what platform their software is running on. (TBMAN) - */ - -typedef struct { /*!< TBMAN Structure */ - __IOM uint32_t PLATFORM; /*!< Indicates the type of platform in use */ -} TBMAN_Type; /*!< Size = 4 (0x4) */ - - - -/* =========================================================================================================================== */ -/* ================ VREG_AND_CHIP_RESET ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief control and status for on-chip voltage regulator and chip level reset subsystem (VREG_AND_CHIP_RESET) - */ - -typedef struct { /*!< VREG_AND_CHIP_RESET Structure */ - __IOM uint32_t VREG; /*!< Voltage regulator control and status */ - __IOM uint32_t BOD; /*!< brown-out detection control */ - __IOM uint32_t CHIP_RESET; /*!< Chip reset control and status */ -} VREG_AND_CHIP_RESET_Type; /*!< Size = 12 (0xc) */ - - - -/* =========================================================================================================================== */ -/* ================ RTC ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief Register block to control RTC (RTC) - */ - -typedef struct { /*!< RTC Structure */ - __IOM uint32_t CLKDIV_M1; /*!< Divider minus 1 for the 1 second counter. Safe to change the - value when RTC is not enabled. */ - __IOM uint32_t SETUP_0; /*!< RTC setup register 0 */ - __IOM uint32_t SETUP_1; /*!< RTC setup register 1 */ - __IOM uint32_t CTRL; /*!< RTC Control and status */ - __IOM uint32_t IRQ_SETUP_0; /*!< Interrupt setup register 0 */ - __IOM uint32_t IRQ_SETUP_1; /*!< Interrupt setup register 1 */ - __IOM uint32_t RTC_1; /*!< RTC register 1. */ - __IOM uint32_t RTC_0; /*!< RTC register 0 Read this before RTC 1! */ - __IOM uint32_t INTR; /*!< Raw Interrupts */ - __IOM uint32_t INTE; /*!< Interrupt Enable */ - __IOM uint32_t INTF; /*!< Interrupt Force */ - __IOM uint32_t INTS; /*!< Interrupt status after masking & forcing */ -} RTC_Type; /*!< Size = 48 (0x30) */ - - -/** @} */ /* End of group Device_Peripheral_peripherals */ - - -/* =========================================================================================================================== */ -/* ================ Device Specific Peripheral Address Map ================ */ -/* =========================================================================================================================== */ - - -/** @addtogroup Device_Peripheral_peripheralAddr - * @{ - */ - -#define RESETS_BASE 0x4000C000UL -#define PSM_BASE 0x40010000UL -#define CLOCKS_BASE 0x40008000UL -#define PADS_BANK0_BASE 0x4001C000UL -#define PADS_QSPI_BASE 0x40020000UL -#define IO_QSPI_BASE 0x40018000UL -#define IO_BANK0_BASE 0x40014000UL -#define SYSINFO_BASE 0x40000000UL -#define PPB_BASE 0xE0000000UL -#define SSI_BASE 0x18000000UL -#define XIP_CTRL_BASE 0x14000000UL -#define SYSCFG_BASE 0x40004000UL -#define XOSC_BASE 0x40024000UL -#define PLL_SYS_BASE 0x40028000UL -#define PLL_USB_BASE 0x4002C000UL -#define UART0_BASE 0x40034000UL -#define UART1_BASE 0x40038000UL -#define ROSC_BASE 0x40060000UL -#define WATCHDOG_BASE 0x40058000UL -#define DMA_BASE 0x50000000UL -#define TIMER_BASE 0x40054000UL -#define PWM_BASE 0x40050000UL -#define ADC_BASE 0x4004C000UL -#define I2C0_BASE 0x40044000UL -#define I2C1_BASE 0x40048000UL -#define SPI0_BASE 0x4003C000UL -#define SPI1_BASE 0x40040000UL -#define PIO0_BASE 0x50200000UL -#define PIO1_BASE 0x50300000UL -#define BUSCTRL_BASE 0x40030000UL -#define SIO_BASE 0xD0000000UL -#define USB_BASE 0x50110000UL -#define USB_DPRAM_BASE 0x50100000UL -#define TBMAN_BASE 0x4006C000UL -#define VREG_AND_CHIP_RESET_BASE 0x40064000UL -#define RTC_BASE 0x4005C000UL - -/** @} */ /* End of group Device_Peripheral_peripheralAddr */ - - -/* =========================================================================================================================== */ -/* ================ Peripheral declaration ================ */ -/* =========================================================================================================================== */ - - -/** @addtogroup Device_Peripheral_declaration - * @{ - */ - -#define RESETS ((RESETS_Type*) RESETS_BASE) -#define PSM ((PSM_Type*) PSM_BASE) -#define CLOCKS ((CLOCKS_Type*) CLOCKS_BASE) -#define PADS_BANK0 ((PADS_BANK0_Type*) PADS_BANK0_BASE) -#define PADS_QSPI ((PADS_QSPI_Type*) PADS_QSPI_BASE) -#define IO_QSPI ((IO_QSPI_Type*) IO_QSPI_BASE) -#define IO_BANK0 ((IO_BANK0_Type*) IO_BANK0_BASE) -#define SYSINFO ((SYSINFO_Type*) SYSINFO_BASE) -#define PPB ((PPB_Type*) PPB_BASE) -#define SSI ((SSI_Type*) SSI_BASE) -#define XIP_CTRL ((XIP_CTRL_Type*) XIP_CTRL_BASE) -#define SYSCFG ((SYSCFG_Type*) SYSCFG_BASE) -#define XOSC ((XOSC_Type*) XOSC_BASE) -#define PLL_SYS ((PLL_SYS_Type*) PLL_SYS_BASE) -#define PLL_USB ((PLL_SYS_Type*) PLL_USB_BASE) -#define UART0 ((UART0_Type*) UART0_BASE) -#define UART1 ((UART0_Type*) UART1_BASE) -#define ROSC ((ROSC_Type*) ROSC_BASE) -#define WATCHDOG ((WATCHDOG_Type*) WATCHDOG_BASE) -#define DMA ((DMA_Type*) DMA_BASE) -#define TIMER ((TIMER_Type*) TIMER_BASE) -#define PWM ((PWM_Type*) PWM_BASE) -#define ADC ((ADC_Type*) ADC_BASE) -#define I2C0 ((I2C0_Type*) I2C0_BASE) -#define I2C1 ((I2C0_Type*) I2C1_BASE) -#define SPI0 ((SPI0_Type*) SPI0_BASE) -#define SPI1 ((SPI0_Type*) SPI1_BASE) -#define PIO0 ((PIO0_Type*) PIO0_BASE) -#define PIO1 ((PIO0_Type*) PIO1_BASE) -#define BUSCTRL ((BUSCTRL_Type*) BUSCTRL_BASE) -#define SIO ((SIO_Type*) SIO_BASE) -#define USB ((USB_Type*) USB_BASE) -#define USB_DPRAM ((USB_DPRAM_Type*) USB_DPRAM_BASE) -#define TBMAN ((TBMAN_Type*) TBMAN_BASE) -#define VREG_AND_CHIP_RESET ((VREG_AND_CHIP_RESET_Type*) VREG_AND_CHIP_RESET_BASE) -#define RTC ((RTC_Type*) RTC_BASE) - -/** @} */ /* End of group Device_Peripheral_declaration */ - - -#ifdef __cplusplus -} -#endif - -#endif /* RP2040_H */ - - -/** @} */ /* End of group RP2040 */ - -/** @} */ /* End of group Raspberry Pi */ diff --git a/lib/main/pico-sdk/rp2_common/cmsis/stub/CMSIS/Device/RP2040/Include/system_RP2040.h b/lib/main/pico-sdk/rp2_common/cmsis/stub/CMSIS/Device/RP2040/Include/system_RP2040.h deleted file mode 100644 index 30881ccc63..0000000000 --- a/lib/main/pico-sdk/rp2_common/cmsis/stub/CMSIS/Device/RP2040/Include/system_RP2040.h +++ /dev/null @@ -1,65 +0,0 @@ -/*************************************************************************//** - * @file system_RP2040.h - * @brief CMSIS-Core(M) Device Peripheral Access Layer Header File for - * Device RP2040 - * @version V1.0.0 - * @date 5. May 2021 - *****************************************************************************/ -/* - * Copyright (c) 2009-2021 Arm Limited. All rights reserved. - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _CMSIS_SYSTEM_RP2040_H -#define _CMSIS_SYSTEM_RP2040_H - -#ifdef __cplusplus -extern "C" { -#endif - -/** - \brief Exception / Interrupt Handler Function Prototype -*/ -typedef void(*VECTOR_TABLE_Type)(void); - -/** - \brief System Clock Frequency (Core Clock) -*/ -extern uint32_t SystemCoreClock; - -/** - \brief Setup the microcontroller system. - - Initialize the System and update the SystemCoreClock variable. - */ -extern void SystemInit (void); - - -/** - \brief Update SystemCoreClock variable. - - Updates the SystemCoreClock with current core Clock retrieved from cpu registers. - */ -extern void SystemCoreClockUpdate (void); - -#ifdef __cplusplus -} -#endif - -#endif /* _CMSIS_SYSTEM_RP2040_H */ diff --git a/lib/main/pico-sdk/rp2_common/cmsis/stub/CMSIS/Device/RP2040/Source/system_RP2040.c b/lib/main/pico-sdk/rp2_common/cmsis/stub/CMSIS/Device/RP2040/Source/system_RP2040.c deleted file mode 100644 index 055a0752c1..0000000000 --- a/lib/main/pico-sdk/rp2_common/cmsis/stub/CMSIS/Device/RP2040/Source/system_RP2040.c +++ /dev/null @@ -1,52 +0,0 @@ -/*************************************************************************//** - * @file system_RP2040.c - * @brief CMSIS-Core(M) Device Peripheral Access Layer Header File for - * Device RP2040 - * @version V1.0.0 - * @date 5. May 2021 - *****************************************************************************/ -/* - * Copyright (c) 2009-2021 Arm Limited. All rights reserved. - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include "RP2040.h" -#include "hardware/clocks.h" - -/*--------------------------------------------------------------------------- - System Core Clock Variable - *---------------------------------------------------------------------------*/ -uint32_t SystemCoreClock; /* System Clock Frequency (Core Clock)*/ - -/*--------------------------------------------------------------------------- - System Core Clock function - *---------------------------------------------------------------------------*/ -void SystemCoreClockUpdate (void) -{ - SystemCoreClock = clock_get_hz(clk_sys); -} - -/*--------------------------------------------------------------------------- - System initialization function - *---------------------------------------------------------------------------*/ -void __attribute__((constructor)) SystemInit (void) -{ - SystemCoreClockUpdate(); -} \ No newline at end of file diff --git a/lib/main/pico-sdk/rp2_common/cmsis/stub/CMSIS/Device/RP2350/Include/RP2350.h b/lib/main/pico-sdk/rp2_common/cmsis/stub/CMSIS/Device/RP2350/Include/RP2350.h deleted file mode 100644 index 8ae014e047..0000000000 --- a/lib/main/pico-sdk/rp2_common/cmsis/stub/CMSIS/Device/RP2350/Include/RP2350.h +++ /dev/null @@ -1,6068 +0,0 @@ -/* - * Copyright (c) 2024 Raspberry Pi Ltd. SPDX-License-Identifier: BSD-3-Clause - * - * @file src/rp2_common/cmsis/stub/CMSIS/Device/RP2350/Include/RP2350.h - * @brief CMSIS HeaderFile - * @version 0.1 - * @date Thu Aug 8 04:04:02 2024 - * @note Generated by SVDConv V3.3.47 - * from File 'src/rp2_common/cmsis/../../rp2350/hardware_regs/RP2350.svd', - * last modified on Thu Aug 8 03:59:33 2024 - */ - - -/** @addtogroup Raspberry Pi - * @{ - */ - - -/** @addtogroup RP2350 - * @{ - */ - - -#ifndef RP2350_H -#define RP2350_H - -#ifdef __cplusplus -extern "C" { -#endif - - -/** @addtogroup Configuration_of_CMSIS - * @{ - */ - - - -/* =========================================================================================================================== */ -/* ================ Interrupt Number Definition ================ */ -/* =========================================================================================================================== */ - -typedef enum { -/* ======================================= ARM Cortex-M33 Specific Interrupt Numbers ======================================= */ - Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ - NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ - HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ - MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation - and No Match */ - BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory - related Fault */ - UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ - SecureFault_IRQn = -9, /*!< -9 Secure Fault Handler */ - SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ - DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ - PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ - SysTick_IRQn = -1, /*!< -1 System Tick Timer */ -/* =========================================== RP2350 Specific Interrupt Numbers =========================================== */ - TIMER0_IRQ_0_IRQn = 0, /*!< 0 TIMER0_IRQ_0 */ - TIMER0_IRQ_1_IRQn = 1, /*!< 1 TIMER0_IRQ_1 */ - TIMER0_IRQ_2_IRQn = 2, /*!< 2 TIMER0_IRQ_2 */ - TIMER0_IRQ_3_IRQn = 3, /*!< 3 TIMER0_IRQ_3 */ - TIMER1_IRQ_0_IRQn = 4, /*!< 4 TIMER1_IRQ_0 */ - TIMER1_IRQ_1_IRQn = 5, /*!< 5 TIMER1_IRQ_1 */ - TIMER1_IRQ_2_IRQn = 6, /*!< 6 TIMER1_IRQ_2 */ - TIMER1_IRQ_3_IRQn = 7, /*!< 7 TIMER1_IRQ_3 */ - PWM_IRQ_WRAP_0_IRQn = 8, /*!< 8 PWM_IRQ_WRAP_0 */ - PWM_IRQ_WRAP_1_IRQn = 9, /*!< 9 PWM_IRQ_WRAP_1 */ - DMA_IRQ_0_IRQn = 10, /*!< 10 DMA_IRQ_0 */ - DMA_IRQ_1_IRQn = 11, /*!< 11 DMA_IRQ_1 */ - DMA_IRQ_2_IRQn = 12, /*!< 12 DMA_IRQ_2 */ - DMA_IRQ_3_IRQn = 13, /*!< 13 DMA_IRQ_3 */ - USBCTRL_IRQ_IRQn = 14, /*!< 14 USBCTRL_IRQ */ - PIO0_IRQ_0_IRQn = 15, /*!< 15 PIO0_IRQ_0 */ - PIO0_IRQ_1_IRQn = 16, /*!< 16 PIO0_IRQ_1 */ - PIO1_IRQ_0_IRQn = 17, /*!< 17 PIO1_IRQ_0 */ - PIO1_IRQ_1_IRQn = 18, /*!< 18 PIO1_IRQ_1 */ - PIO2_IRQ_0_IRQn = 19, /*!< 19 PIO2_IRQ_0 */ - PIO2_IRQ_1_IRQn = 20, /*!< 20 PIO2_IRQ_1 */ - IO_IRQ_BANK0_IRQn = 21, /*!< 21 IO_IRQ_BANK0 */ - IO_IRQ_BANK0_NS_IRQn = 22, /*!< 22 IO_IRQ_BANK0_NS */ - IO_IRQ_QSPI_IRQn = 23, /*!< 23 IO_IRQ_QSPI */ - IO_IRQ_QSPI_NS_IRQn = 24, /*!< 24 IO_IRQ_QSPI_NS */ - SIO_IRQ_FIFO_IRQn = 25, /*!< 25 SIO_IRQ_FIFO */ - SIO_IRQ_BELL_IRQn = 26, /*!< 26 SIO_IRQ_BELL */ - SIO_IRQ_FIFO_NS_IRQn = 27, /*!< 27 SIO_IRQ_FIFO_NS */ - SIO_IRQ_BELL_NS_IRQn = 28, /*!< 28 SIO_IRQ_BELL_NS */ - SIO_IRQ_MTIMECMP_IRQn = 29, /*!< 29 SIO_IRQ_MTIMECMP */ - CLOCKS_IRQ_IRQn = 30, /*!< 30 CLOCKS_IRQ */ - SPI0_IRQ_IRQn = 31, /*!< 31 SPI0_IRQ */ - SPI1_IRQ_IRQn = 32, /*!< 32 SPI1_IRQ */ - UART0_IRQ_IRQn = 33, /*!< 33 UART0_IRQ */ - UART1_IRQ_IRQn = 34, /*!< 34 UART1_IRQ */ - ADC_IRQ_FIFO_IRQn = 35, /*!< 35 ADC_IRQ_FIFO */ - I2C0_IRQ_IRQn = 36, /*!< 36 I2C0_IRQ */ - I2C1_IRQ_IRQn = 37, /*!< 37 I2C1_IRQ */ - OTP_IRQ_IRQn = 38, /*!< 38 OTP_IRQ */ - TRNG_IRQ_IRQn = 39, /*!< 39 TRNG_IRQ */ - PLL_SYS_IRQ_IRQn = 42, /*!< 42 PLL_SYS_IRQ */ - PLL_USB_IRQ_IRQn = 43, /*!< 43 PLL_USB_IRQ */ - POWMAN_IRQ_POW_IRQn = 44, /*!< 44 POWMAN_IRQ_POW */ - POWMAN_IRQ_TIMER_IRQn = 45 /*!< 45 POWMAN_IRQ_TIMER */ -} IRQn_Type; - - - -/* =========================================================================================================================== */ -/* ================ Processor and Core Peripheral Section ================ */ -/* =========================================================================================================================== */ - -/* ========================== Configuration of the ARM Cortex-M33 Processor and Core Peripherals =========================== */ -#define __CM33_REV 0x0100U /*!< CM33 Core Revision */ -#define __NVIC_PRIO_BITS 4 /*!< Number of Bits used for Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ -#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ -#define __MPU_PRESENT 1 /*!< MPU present */ -#define __FPU_PRESENT 1 /*!< FPU present */ -#define __FPU_DP 0 /*!< Double Precision FPU */ -#define __DSP_PRESENT 1 /*!< DSP extension present */ -#define __SAUREGION_PRESENT 1 /*!< SAU region present */ - - -/** @} */ /* End of group Configuration_of_CMSIS */ - -#include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ -#include "system_RP2350.h" /*!< RP2350 System */ - -#ifndef __IM /*!< Fallback for older CMSIS versions */ - #define __IM __I -#endif -#ifndef __OM /*!< Fallback for older CMSIS versions */ - #define __OM __O -#endif -#ifndef __IOM /*!< Fallback for older CMSIS versions */ - #define __IOM __IO -#endif - - -/* =========================================================================================================================== */ -/* ================ Device Specific Peripheral Section ================ */ -/* =========================================================================================================================== */ - - -/** @addtogroup Device_Peripheral_peripherals - * @{ - */ - - - -/* =========================================================================================================================== */ -/* ================ RESETS ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief RESETS (RESETS) - */ - -typedef struct { /*!< RESETS Structure */ - __IOM uint32_t RESET; /*!< RESET */ - __IOM uint32_t WDSEL; /*!< WDSEL */ - __IOM uint32_t RESET_DONE; /*!< RESET_DONE */ -} RESETS_Type; /*!< Size = 12 (0xc) */ - - - -/* =========================================================================================================================== */ -/* ================ PSM ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief PSM (PSM) - */ - -typedef struct { /*!< PSM Structure */ - __IOM uint32_t FRCE_ON; /*!< Force block out of reset (i.e. power it on) */ - __IOM uint32_t FRCE_OFF; /*!< Force into reset (i.e. power it off) */ - __IOM uint32_t WDSEL; /*!< Set to 1 if the watchdog should reset this */ - __IOM uint32_t DONE; /*!< Is the subsystem ready? */ -} PSM_Type; /*!< Size = 16 (0x10) */ - - - -/* =========================================================================================================================== */ -/* ================ CLOCKS ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief CLOCKS (CLOCKS) - */ - -typedef struct { /*!< CLOCKS Structure */ - __IOM uint32_t CLK_GPOUT0_CTRL; /*!< Clock control, can be changed on-the-fly (except for auxsrc) */ - __IOM uint32_t CLK_GPOUT0_DIV; /*!< CLK_GPOUT0_DIV */ - __IOM uint32_t CLK_GPOUT0_SELECTED; /*!< Indicates which src is currently selected (one-hot) */ - __IOM uint32_t CLK_GPOUT1_CTRL; /*!< Clock control, can be changed on-the-fly (except for auxsrc) */ - __IOM uint32_t CLK_GPOUT1_DIV; /*!< CLK_GPOUT1_DIV */ - __IOM uint32_t CLK_GPOUT1_SELECTED; /*!< Indicates which src is currently selected (one-hot) */ - __IOM uint32_t CLK_GPOUT2_CTRL; /*!< Clock control, can be changed on-the-fly (except for auxsrc) */ - __IOM uint32_t CLK_GPOUT2_DIV; /*!< CLK_GPOUT2_DIV */ - __IOM uint32_t CLK_GPOUT2_SELECTED; /*!< Indicates which src is currently selected (one-hot) */ - __IOM uint32_t CLK_GPOUT3_CTRL; /*!< Clock control, can be changed on-the-fly (except for auxsrc) */ - __IOM uint32_t CLK_GPOUT3_DIV; /*!< CLK_GPOUT3_DIV */ - __IOM uint32_t CLK_GPOUT3_SELECTED; /*!< Indicates which src is currently selected (one-hot) */ - __IOM uint32_t CLK_REF_CTRL; /*!< Clock control, can be changed on-the-fly (except for auxsrc) */ - __IOM uint32_t CLK_REF_DIV; /*!< CLK_REF_DIV */ - __IOM uint32_t CLK_REF_SELECTED; /*!< Indicates which src is currently selected (one-hot) */ - __IOM uint32_t CLK_SYS_CTRL; /*!< Clock control, can be changed on-the-fly (except for auxsrc) */ - __IOM uint32_t CLK_SYS_DIV; /*!< CLK_SYS_DIV */ - __IOM uint32_t CLK_SYS_SELECTED; /*!< Indicates which src is currently selected (one-hot) */ - __IOM uint32_t CLK_PERI_CTRL; /*!< Clock control, can be changed on-the-fly (except for auxsrc) */ - __IOM uint32_t CLK_PERI_DIV; /*!< CLK_PERI_DIV */ - __IOM uint32_t CLK_PERI_SELECTED; /*!< Indicates which src is currently selected (one-hot) */ - __IOM uint32_t CLK_HSTX_CTRL; /*!< Clock control, can be changed on-the-fly (except for auxsrc) */ - __IOM uint32_t CLK_HSTX_DIV; /*!< CLK_HSTX_DIV */ - __IOM uint32_t CLK_HSTX_SELECTED; /*!< Indicates which src is currently selected (one-hot) */ - __IOM uint32_t CLK_USB_CTRL; /*!< Clock control, can be changed on-the-fly (except for auxsrc) */ - __IOM uint32_t CLK_USB_DIV; /*!< CLK_USB_DIV */ - __IOM uint32_t CLK_USB_SELECTED; /*!< Indicates which src is currently selected (one-hot) */ - __IOM uint32_t CLK_ADC_CTRL; /*!< Clock control, can be changed on-the-fly (except for auxsrc) */ - __IOM uint32_t CLK_ADC_DIV; /*!< CLK_ADC_DIV */ - __IOM uint32_t CLK_ADC_SELECTED; /*!< Indicates which src is currently selected (one-hot) */ - __IOM uint32_t DFTCLK_XOSC_CTRL; /*!< DFTCLK_XOSC_CTRL */ - __IOM uint32_t DFTCLK_ROSC_CTRL; /*!< DFTCLK_ROSC_CTRL */ - __IOM uint32_t DFTCLK_LPOSC_CTRL; /*!< DFTCLK_LPOSC_CTRL */ - __IOM uint32_t CLK_SYS_RESUS_CTRL; /*!< CLK_SYS_RESUS_CTRL */ - __IOM uint32_t CLK_SYS_RESUS_STATUS; /*!< CLK_SYS_RESUS_STATUS */ - __IOM uint32_t FC0_REF_KHZ; /*!< Reference clock frequency in kHz */ - __IOM uint32_t FC0_MIN_KHZ; /*!< Minimum pass frequency in kHz. This is optional. Set to 0 if - you are not using the pass/fail flags */ - __IOM uint32_t FC0_MAX_KHZ; /*!< Maximum pass frequency in kHz. This is optional. Set to 0x1ffffff - if you are not using the pass/fail flags */ - __IOM uint32_t FC0_DELAY; /*!< Delays the start of frequency counting to allow the mux to settle - Delay is measured in multiples of the reference clock period */ - __IOM uint32_t FC0_INTERVAL; /*!< The test interval is 0.98us * 2**interval, but let's call it - 1us * 2**interval The default gives a test interval of - 250us */ - __IOM uint32_t FC0_SRC; /*!< Clock sent to frequency counter, set to 0 when not required - Writing to this register initiates the frequency count */ - __IOM uint32_t FC0_STATUS; /*!< Frequency counter status */ - __IOM uint32_t FC0_RESULT; /*!< Result of frequency measurement, only valid when status_done=1 */ - __IOM uint32_t WAKE_EN0; /*!< enable clock in wake mode */ - __IOM uint32_t WAKE_EN1; /*!< enable clock in wake mode */ - __IOM uint32_t SLEEP_EN0; /*!< enable clock in sleep mode */ - __IOM uint32_t SLEEP_EN1; /*!< enable clock in sleep mode */ - __IOM uint32_t ENABLED0; /*!< indicates the state of the clock enable */ - __IOM uint32_t ENABLED1; /*!< indicates the state of the clock enable */ - __IOM uint32_t INTR; /*!< Raw Interrupts */ - __IOM uint32_t INTE; /*!< Interrupt Enable */ - __IOM uint32_t INTF; /*!< Interrupt Force */ - __IOM uint32_t INTS; /*!< Interrupt status after masking & forcing */ -} CLOCKS_Type; /*!< Size = 212 (0xd4) */ - - - -/* =========================================================================================================================== */ -/* ================ TICKS ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief TICKS (TICKS) - */ - -typedef struct { /*!< TICKS Structure */ - __IOM uint32_t PROC0_CTRL; /*!< Controls the tick generator */ - __IOM uint32_t PROC0_CYCLES; /*!< PROC0_CYCLES */ - __IOM uint32_t PROC0_COUNT; /*!< PROC0_COUNT */ - __IOM uint32_t PROC1_CTRL; /*!< Controls the tick generator */ - __IOM uint32_t PROC1_CYCLES; /*!< PROC1_CYCLES */ - __IOM uint32_t PROC1_COUNT; /*!< PROC1_COUNT */ - __IOM uint32_t TIMER0_CTRL; /*!< Controls the tick generator */ - __IOM uint32_t TIMER0_CYCLES; /*!< TIMER0_CYCLES */ - __IOM uint32_t TIMER0_COUNT; /*!< TIMER0_COUNT */ - __IOM uint32_t TIMER1_CTRL; /*!< Controls the tick generator */ - __IOM uint32_t TIMER1_CYCLES; /*!< TIMER1_CYCLES */ - __IOM uint32_t TIMER1_COUNT; /*!< TIMER1_COUNT */ - __IOM uint32_t WATCHDOG_CTRL; /*!< Controls the tick generator */ - __IOM uint32_t WATCHDOG_CYCLES; /*!< WATCHDOG_CYCLES */ - __IOM uint32_t WATCHDOG_COUNT; /*!< WATCHDOG_COUNT */ - __IOM uint32_t RISCV_CTRL; /*!< Controls the tick generator */ - __IOM uint32_t RISCV_CYCLES; /*!< RISCV_CYCLES */ - __IOM uint32_t RISCV_COUNT; /*!< RISCV_COUNT */ -} TICKS_Type; /*!< Size = 72 (0x48) */ - - - -/* =========================================================================================================================== */ -/* ================ PADS_BANK0 ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief PADS_BANK0 (PADS_BANK0) - */ - -typedef struct { /*!< PADS_BANK0 Structure */ - __IOM uint32_t VOLTAGE_SELECT; /*!< Voltage select. Per bank control */ - __IOM uint32_t GPIO0; /*!< GPIO0 */ - __IOM uint32_t GPIO1; /*!< GPIO1 */ - __IOM uint32_t GPIO2; /*!< GPIO2 */ - __IOM uint32_t GPIO3; /*!< GPIO3 */ - __IOM uint32_t GPIO4; /*!< GPIO4 */ - __IOM uint32_t GPIO5; /*!< GPIO5 */ - __IOM uint32_t GPIO6; /*!< GPIO6 */ - __IOM uint32_t GPIO7; /*!< GPIO7 */ - __IOM uint32_t GPIO8; /*!< GPIO8 */ - __IOM uint32_t GPIO9; /*!< GPIO9 */ - __IOM uint32_t GPIO10; /*!< GPIO10 */ - __IOM uint32_t GPIO11; /*!< GPIO11 */ - __IOM uint32_t GPIO12; /*!< GPIO12 */ - __IOM uint32_t GPIO13; /*!< GPIO13 */ - __IOM uint32_t GPIO14; /*!< GPIO14 */ - __IOM uint32_t GPIO15; /*!< GPIO15 */ - __IOM uint32_t GPIO16; /*!< GPIO16 */ - __IOM uint32_t GPIO17; /*!< GPIO17 */ - __IOM uint32_t GPIO18; /*!< GPIO18 */ - __IOM uint32_t GPIO19; /*!< GPIO19 */ - __IOM uint32_t GPIO20; /*!< GPIO20 */ - __IOM uint32_t GPIO21; /*!< GPIO21 */ - __IOM uint32_t GPIO22; /*!< GPIO22 */ - __IOM uint32_t GPIO23; /*!< GPIO23 */ - __IOM uint32_t GPIO24; /*!< GPIO24 */ - __IOM uint32_t GPIO25; /*!< GPIO25 */ - __IOM uint32_t GPIO26; /*!< GPIO26 */ - __IOM uint32_t GPIO27; /*!< GPIO27 */ - __IOM uint32_t GPIO28; /*!< GPIO28 */ - __IOM uint32_t GPIO29; /*!< GPIO29 */ - __IOM uint32_t GPIO30; /*!< GPIO30 */ - __IOM uint32_t GPIO31; /*!< GPIO31 */ - __IOM uint32_t GPIO32; /*!< GPIO32 */ - __IOM uint32_t GPIO33; /*!< GPIO33 */ - __IOM uint32_t GPIO34; /*!< GPIO34 */ - __IOM uint32_t GPIO35; /*!< GPIO35 */ - __IOM uint32_t GPIO36; /*!< GPIO36 */ - __IOM uint32_t GPIO37; /*!< GPIO37 */ - __IOM uint32_t GPIO38; /*!< GPIO38 */ - __IOM uint32_t GPIO39; /*!< GPIO39 */ - __IOM uint32_t GPIO40; /*!< GPIO40 */ - __IOM uint32_t GPIO41; /*!< GPIO41 */ - __IOM uint32_t GPIO42; /*!< GPIO42 */ - __IOM uint32_t GPIO43; /*!< GPIO43 */ - __IOM uint32_t GPIO44; /*!< GPIO44 */ - __IOM uint32_t GPIO45; /*!< GPIO45 */ - __IOM uint32_t GPIO46; /*!< GPIO46 */ - __IOM uint32_t GPIO47; /*!< GPIO47 */ - __IOM uint32_t SWCLK; /*!< SWCLK */ - __IOM uint32_t SWD; /*!< SWD */ -} PADS_BANK0_Type; /*!< Size = 204 (0xcc) */ - - - -/* =========================================================================================================================== */ -/* ================ PADS_QSPI ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief PADS_QSPI (PADS_QSPI) - */ - -typedef struct { /*!< PADS_QSPI Structure */ - __IOM uint32_t VOLTAGE_SELECT; /*!< Voltage select. Per bank control */ - __IOM uint32_t GPIO_QSPI_SCLK; /*!< GPIO_QSPI_SCLK */ - __IOM uint32_t GPIO_QSPI_SD0; /*!< GPIO_QSPI_SD0 */ - __IOM uint32_t GPIO_QSPI_SD1; /*!< GPIO_QSPI_SD1 */ - __IOM uint32_t GPIO_QSPI_SD2; /*!< GPIO_QSPI_SD2 */ - __IOM uint32_t GPIO_QSPI_SD3; /*!< GPIO_QSPI_SD3 */ - __IOM uint32_t GPIO_QSPI_SS; /*!< GPIO_QSPI_SS */ -} PADS_QSPI_Type; /*!< Size = 28 (0x1c) */ - - - -/* =========================================================================================================================== */ -/* ================ IO_QSPI ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief IO_QSPI (IO_QSPI) - */ - -typedef struct { /*!< IO_QSPI Structure */ - __IOM uint32_t USBPHY_DP_STATUS; /*!< USBPHY_DP_STATUS */ - __IOM uint32_t USBPHY_DP_CTRL; /*!< USBPHY_DP_CTRL */ - __IOM uint32_t USBPHY_DM_STATUS; /*!< USBPHY_DM_STATUS */ - __IOM uint32_t USBPHY_DM_CTRL; /*!< USBPHY_DM_CTRL */ - __IOM uint32_t GPIO_QSPI_SCLK_STATUS; /*!< GPIO_QSPI_SCLK_STATUS */ - __IOM uint32_t GPIO_QSPI_SCLK_CTRL; /*!< GPIO_QSPI_SCLK_CTRL */ - __IOM uint32_t GPIO_QSPI_SS_STATUS; /*!< GPIO_QSPI_SS_STATUS */ - __IOM uint32_t GPIO_QSPI_SS_CTRL; /*!< GPIO_QSPI_SS_CTRL */ - __IOM uint32_t GPIO_QSPI_SD0_STATUS; /*!< GPIO_QSPI_SD0_STATUS */ - __IOM uint32_t GPIO_QSPI_SD0_CTRL; /*!< GPIO_QSPI_SD0_CTRL */ - __IOM uint32_t GPIO_QSPI_SD1_STATUS; /*!< GPIO_QSPI_SD1_STATUS */ - __IOM uint32_t GPIO_QSPI_SD1_CTRL; /*!< GPIO_QSPI_SD1_CTRL */ - __IOM uint32_t GPIO_QSPI_SD2_STATUS; /*!< GPIO_QSPI_SD2_STATUS */ - __IOM uint32_t GPIO_QSPI_SD2_CTRL; /*!< GPIO_QSPI_SD2_CTRL */ - __IOM uint32_t GPIO_QSPI_SD3_STATUS; /*!< GPIO_QSPI_SD3_STATUS */ - __IOM uint32_t GPIO_QSPI_SD3_CTRL; /*!< GPIO_QSPI_SD3_CTRL */ - __IM uint32_t RESERVED[112]; - __IOM uint32_t IRQSUMMARY_PROC0_SECURE; /*!< IRQSUMMARY_PROC0_SECURE */ - __IOM uint32_t IRQSUMMARY_PROC0_NONSECURE; /*!< IRQSUMMARY_PROC0_NONSECURE */ - __IOM uint32_t IRQSUMMARY_PROC1_SECURE; /*!< IRQSUMMARY_PROC1_SECURE */ - __IOM uint32_t IRQSUMMARY_PROC1_NONSECURE; /*!< IRQSUMMARY_PROC1_NONSECURE */ - __IOM uint32_t IRQSUMMARY_DORMANT_WAKE_SECURE;/*!< IRQSUMMARY_DORMANT_WAKE_SECURE */ - __IOM uint32_t IRQSUMMARY_DORMANT_WAKE_NONSECURE;/*!< IRQSUMMARY_DORMANT_WAKE_NONSECURE */ - __IOM uint32_t INTR; /*!< Raw Interrupts */ - __IOM uint32_t PROC0_INTE; /*!< Interrupt Enable for proc0 */ - __IOM uint32_t PROC0_INTF; /*!< Interrupt Force for proc0 */ - __IOM uint32_t PROC0_INTS; /*!< Interrupt status after masking & forcing for proc0 */ - __IOM uint32_t PROC1_INTE; /*!< Interrupt Enable for proc1 */ - __IOM uint32_t PROC1_INTF; /*!< Interrupt Force for proc1 */ - __IOM uint32_t PROC1_INTS; /*!< Interrupt status after masking & forcing for proc1 */ - __IOM uint32_t DORMANT_WAKE_INTE; /*!< Interrupt Enable for dormant_wake */ - __IOM uint32_t DORMANT_WAKE_INTF; /*!< Interrupt Force for dormant_wake */ - __IOM uint32_t DORMANT_WAKE_INTS; /*!< Interrupt status after masking & forcing for dormant_wake */ -} IO_QSPI_Type; /*!< Size = 576 (0x240) */ - - - -/* =========================================================================================================================== */ -/* ================ IO_BANK0 ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief IO_BANK0 (IO_BANK0) - */ - -typedef struct { /*!< IO_BANK0 Structure */ - __IOM uint32_t GPIO0_STATUS; /*!< GPIO0_STATUS */ - __IOM uint32_t GPIO0_CTRL; /*!< GPIO0_CTRL */ - __IOM uint32_t GPIO1_STATUS; /*!< GPIO1_STATUS */ - __IOM uint32_t GPIO1_CTRL; /*!< GPIO1_CTRL */ - __IOM uint32_t GPIO2_STATUS; /*!< GPIO2_STATUS */ - __IOM uint32_t GPIO2_CTRL; /*!< GPIO2_CTRL */ - __IOM uint32_t GPIO3_STATUS; /*!< GPIO3_STATUS */ - __IOM uint32_t GPIO3_CTRL; /*!< GPIO3_CTRL */ - __IOM uint32_t GPIO4_STATUS; /*!< GPIO4_STATUS */ - __IOM uint32_t GPIO4_CTRL; /*!< GPIO4_CTRL */ - __IOM uint32_t GPIO5_STATUS; /*!< GPIO5_STATUS */ - __IOM uint32_t GPIO5_CTRL; /*!< GPIO5_CTRL */ - __IOM uint32_t GPIO6_STATUS; /*!< GPIO6_STATUS */ - __IOM uint32_t GPIO6_CTRL; /*!< GPIO6_CTRL */ - __IOM uint32_t GPIO7_STATUS; /*!< GPIO7_STATUS */ - __IOM uint32_t GPIO7_CTRL; /*!< GPIO7_CTRL */ - __IOM uint32_t GPIO8_STATUS; /*!< GPIO8_STATUS */ - __IOM uint32_t GPIO8_CTRL; /*!< GPIO8_CTRL */ - __IOM uint32_t GPIO9_STATUS; /*!< GPIO9_STATUS */ - __IOM uint32_t GPIO9_CTRL; /*!< GPIO9_CTRL */ - __IOM uint32_t GPIO10_STATUS; /*!< GPIO10_STATUS */ - __IOM uint32_t GPIO10_CTRL; /*!< GPIO10_CTRL */ - __IOM uint32_t GPIO11_STATUS; /*!< GPIO11_STATUS */ - __IOM uint32_t GPIO11_CTRL; /*!< GPIO11_CTRL */ - __IOM uint32_t GPIO12_STATUS; /*!< GPIO12_STATUS */ - __IOM uint32_t GPIO12_CTRL; /*!< GPIO12_CTRL */ - __IOM uint32_t GPIO13_STATUS; /*!< GPIO13_STATUS */ - __IOM uint32_t GPIO13_CTRL; /*!< GPIO13_CTRL */ - __IOM uint32_t GPIO14_STATUS; /*!< GPIO14_STATUS */ - __IOM uint32_t GPIO14_CTRL; /*!< GPIO14_CTRL */ - __IOM uint32_t GPIO15_STATUS; /*!< GPIO15_STATUS */ - __IOM uint32_t GPIO15_CTRL; /*!< GPIO15_CTRL */ - __IOM uint32_t GPIO16_STATUS; /*!< GPIO16_STATUS */ - __IOM uint32_t GPIO16_CTRL; /*!< GPIO16_CTRL */ - __IOM uint32_t GPIO17_STATUS; /*!< GPIO17_STATUS */ - __IOM uint32_t GPIO17_CTRL; /*!< GPIO17_CTRL */ - __IOM uint32_t GPIO18_STATUS; /*!< GPIO18_STATUS */ - __IOM uint32_t GPIO18_CTRL; /*!< GPIO18_CTRL */ - __IOM uint32_t GPIO19_STATUS; /*!< GPIO19_STATUS */ - __IOM uint32_t GPIO19_CTRL; /*!< GPIO19_CTRL */ - __IOM uint32_t GPIO20_STATUS; /*!< GPIO20_STATUS */ - __IOM uint32_t GPIO20_CTRL; /*!< GPIO20_CTRL */ - __IOM uint32_t GPIO21_STATUS; /*!< GPIO21_STATUS */ - __IOM uint32_t GPIO21_CTRL; /*!< GPIO21_CTRL */ - __IOM uint32_t GPIO22_STATUS; /*!< GPIO22_STATUS */ - __IOM uint32_t GPIO22_CTRL; /*!< GPIO22_CTRL */ - __IOM uint32_t GPIO23_STATUS; /*!< GPIO23_STATUS */ - __IOM uint32_t GPIO23_CTRL; /*!< GPIO23_CTRL */ - __IOM uint32_t GPIO24_STATUS; /*!< GPIO24_STATUS */ - __IOM uint32_t GPIO24_CTRL; /*!< GPIO24_CTRL */ - __IOM uint32_t GPIO25_STATUS; /*!< GPIO25_STATUS */ - __IOM uint32_t GPIO25_CTRL; /*!< GPIO25_CTRL */ - __IOM uint32_t GPIO26_STATUS; /*!< GPIO26_STATUS */ - __IOM uint32_t GPIO26_CTRL; /*!< GPIO26_CTRL */ - __IOM uint32_t GPIO27_STATUS; /*!< GPIO27_STATUS */ - __IOM uint32_t GPIO27_CTRL; /*!< GPIO27_CTRL */ - __IOM uint32_t GPIO28_STATUS; /*!< GPIO28_STATUS */ - __IOM uint32_t GPIO28_CTRL; /*!< GPIO28_CTRL */ - __IOM uint32_t GPIO29_STATUS; /*!< GPIO29_STATUS */ - __IOM uint32_t GPIO29_CTRL; /*!< GPIO29_CTRL */ - __IOM uint32_t GPIO30_STATUS; /*!< GPIO30_STATUS */ - __IOM uint32_t GPIO30_CTRL; /*!< GPIO30_CTRL */ - __IOM uint32_t GPIO31_STATUS; /*!< GPIO31_STATUS */ - __IOM uint32_t GPIO31_CTRL; /*!< GPIO31_CTRL */ - __IOM uint32_t GPIO32_STATUS; /*!< GPIO32_STATUS */ - __IOM uint32_t GPIO32_CTRL; /*!< GPIO32_CTRL */ - __IOM uint32_t GPIO33_STATUS; /*!< GPIO33_STATUS */ - __IOM uint32_t GPIO33_CTRL; /*!< GPIO33_CTRL */ - __IOM uint32_t GPIO34_STATUS; /*!< GPIO34_STATUS */ - __IOM uint32_t GPIO34_CTRL; /*!< GPIO34_CTRL */ - __IOM uint32_t GPIO35_STATUS; /*!< GPIO35_STATUS */ - __IOM uint32_t GPIO35_CTRL; /*!< GPIO35_CTRL */ - __IOM uint32_t GPIO36_STATUS; /*!< GPIO36_STATUS */ - __IOM uint32_t GPIO36_CTRL; /*!< GPIO36_CTRL */ - __IOM uint32_t GPIO37_STATUS; /*!< GPIO37_STATUS */ - __IOM uint32_t GPIO37_CTRL; /*!< GPIO37_CTRL */ - __IOM uint32_t GPIO38_STATUS; /*!< GPIO38_STATUS */ - __IOM uint32_t GPIO38_CTRL; /*!< GPIO38_CTRL */ - __IOM uint32_t GPIO39_STATUS; /*!< GPIO39_STATUS */ - __IOM uint32_t GPIO39_CTRL; /*!< GPIO39_CTRL */ - __IOM uint32_t GPIO40_STATUS; /*!< GPIO40_STATUS */ - __IOM uint32_t GPIO40_CTRL; /*!< GPIO40_CTRL */ - __IOM uint32_t GPIO41_STATUS; /*!< GPIO41_STATUS */ - __IOM uint32_t GPIO41_CTRL; /*!< GPIO41_CTRL */ - __IOM uint32_t GPIO42_STATUS; /*!< GPIO42_STATUS */ - __IOM uint32_t GPIO42_CTRL; /*!< GPIO42_CTRL */ - __IOM uint32_t GPIO43_STATUS; /*!< GPIO43_STATUS */ - __IOM uint32_t GPIO43_CTRL; /*!< GPIO43_CTRL */ - __IOM uint32_t GPIO44_STATUS; /*!< GPIO44_STATUS */ - __IOM uint32_t GPIO44_CTRL; /*!< GPIO44_CTRL */ - __IOM uint32_t GPIO45_STATUS; /*!< GPIO45_STATUS */ - __IOM uint32_t GPIO45_CTRL; /*!< GPIO45_CTRL */ - __IOM uint32_t GPIO46_STATUS; /*!< GPIO46_STATUS */ - __IOM uint32_t GPIO46_CTRL; /*!< GPIO46_CTRL */ - __IOM uint32_t GPIO47_STATUS; /*!< GPIO47_STATUS */ - __IOM uint32_t GPIO47_CTRL; /*!< GPIO47_CTRL */ - __IM uint32_t RESERVED[32]; - __IOM uint32_t IRQSUMMARY_PROC0_SECURE0; /*!< IRQSUMMARY_PROC0_SECURE0 */ - __IOM uint32_t IRQSUMMARY_PROC0_SECURE1; /*!< IRQSUMMARY_PROC0_SECURE1 */ - __IOM uint32_t IRQSUMMARY_PROC0_NONSECURE0; /*!< IRQSUMMARY_PROC0_NONSECURE0 */ - __IOM uint32_t IRQSUMMARY_PROC0_NONSECURE1; /*!< IRQSUMMARY_PROC0_NONSECURE1 */ - __IOM uint32_t IRQSUMMARY_PROC1_SECURE0; /*!< IRQSUMMARY_PROC1_SECURE0 */ - __IOM uint32_t IRQSUMMARY_PROC1_SECURE1; /*!< IRQSUMMARY_PROC1_SECURE1 */ - __IOM uint32_t IRQSUMMARY_PROC1_NONSECURE0; /*!< IRQSUMMARY_PROC1_NONSECURE0 */ - __IOM uint32_t IRQSUMMARY_PROC1_NONSECURE1; /*!< IRQSUMMARY_PROC1_NONSECURE1 */ - __IOM uint32_t IRQSUMMARY_DORMANT_WAKE_SECURE0;/*!< IRQSUMMARY_DORMANT_WAKE_SECURE0 */ - __IOM uint32_t IRQSUMMARY_DORMANT_WAKE_SECURE1;/*!< IRQSUMMARY_DORMANT_WAKE_SECURE1 */ - __IOM uint32_t IRQSUMMARY_DORMANT_WAKE_NONSECURE0;/*!< IRQSUMMARY_DORMANT_WAKE_NONSECURE0 */ - __IOM uint32_t IRQSUMMARY_DORMANT_WAKE_NONSECURE1;/*!< IRQSUMMARY_DORMANT_WAKE_NONSECURE1 */ - __IOM uint32_t INTR0; /*!< Raw Interrupts */ - __IOM uint32_t INTR1; /*!< Raw Interrupts */ - __IOM uint32_t INTR2; /*!< Raw Interrupts */ - __IOM uint32_t INTR3; /*!< Raw Interrupts */ - __IOM uint32_t INTR4; /*!< Raw Interrupts */ - __IOM uint32_t INTR5; /*!< Raw Interrupts */ - __IOM uint32_t PROC0_INTE0; /*!< Interrupt Enable for proc0 */ - __IOM uint32_t PROC0_INTE1; /*!< Interrupt Enable for proc0 */ - __IOM uint32_t PROC0_INTE2; /*!< Interrupt Enable for proc0 */ - __IOM uint32_t PROC0_INTE3; /*!< Interrupt Enable for proc0 */ - __IOM uint32_t PROC0_INTE4; /*!< Interrupt Enable for proc0 */ - __IOM uint32_t PROC0_INTE5; /*!< Interrupt Enable for proc0 */ - __IOM uint32_t PROC0_INTF0; /*!< Interrupt Force for proc0 */ - __IOM uint32_t PROC0_INTF1; /*!< Interrupt Force for proc0 */ - __IOM uint32_t PROC0_INTF2; /*!< Interrupt Force for proc0 */ - __IOM uint32_t PROC0_INTF3; /*!< Interrupt Force for proc0 */ - __IOM uint32_t PROC0_INTF4; /*!< Interrupt Force for proc0 */ - __IOM uint32_t PROC0_INTF5; /*!< Interrupt Force for proc0 */ - __IOM uint32_t PROC0_INTS0; /*!< Interrupt status after masking & forcing for proc0 */ - __IOM uint32_t PROC0_INTS1; /*!< Interrupt status after masking & forcing for proc0 */ - __IOM uint32_t PROC0_INTS2; /*!< Interrupt status after masking & forcing for proc0 */ - __IOM uint32_t PROC0_INTS3; /*!< Interrupt status after masking & forcing for proc0 */ - __IOM uint32_t PROC0_INTS4; /*!< Interrupt status after masking & forcing for proc0 */ - __IOM uint32_t PROC0_INTS5; /*!< Interrupt status after masking & forcing for proc0 */ - __IOM uint32_t PROC1_INTE0; /*!< Interrupt Enable for proc1 */ - __IOM uint32_t PROC1_INTE1; /*!< Interrupt Enable for proc1 */ - __IOM uint32_t PROC1_INTE2; /*!< Interrupt Enable for proc1 */ - __IOM uint32_t PROC1_INTE3; /*!< Interrupt Enable for proc1 */ - __IOM uint32_t PROC1_INTE4; /*!< Interrupt Enable for proc1 */ - __IOM uint32_t PROC1_INTE5; /*!< Interrupt Enable for proc1 */ - __IOM uint32_t PROC1_INTF0; /*!< Interrupt Force for proc1 */ - __IOM uint32_t PROC1_INTF1; /*!< Interrupt Force for proc1 */ - __IOM uint32_t PROC1_INTF2; /*!< Interrupt Force for proc1 */ - __IOM uint32_t PROC1_INTF3; /*!< Interrupt Force for proc1 */ - __IOM uint32_t PROC1_INTF4; /*!< Interrupt Force for proc1 */ - __IOM uint32_t PROC1_INTF5; /*!< Interrupt Force for proc1 */ - __IOM uint32_t PROC1_INTS0; /*!< Interrupt status after masking & forcing for proc1 */ - __IOM uint32_t PROC1_INTS1; /*!< Interrupt status after masking & forcing for proc1 */ - __IOM uint32_t PROC1_INTS2; /*!< Interrupt status after masking & forcing for proc1 */ - __IOM uint32_t PROC1_INTS3; /*!< Interrupt status after masking & forcing for proc1 */ - __IOM uint32_t PROC1_INTS4; /*!< Interrupt status after masking & forcing for proc1 */ - __IOM uint32_t PROC1_INTS5; /*!< Interrupt status after masking & forcing for proc1 */ - __IOM uint32_t DORMANT_WAKE_INTE0; /*!< Interrupt Enable for dormant_wake */ - __IOM uint32_t DORMANT_WAKE_INTE1; /*!< Interrupt Enable for dormant_wake */ - __IOM uint32_t DORMANT_WAKE_INTE2; /*!< Interrupt Enable for dormant_wake */ - __IOM uint32_t DORMANT_WAKE_INTE3; /*!< Interrupt Enable for dormant_wake */ - __IOM uint32_t DORMANT_WAKE_INTE4; /*!< Interrupt Enable for dormant_wake */ - __IOM uint32_t DORMANT_WAKE_INTE5; /*!< Interrupt Enable for dormant_wake */ - __IOM uint32_t DORMANT_WAKE_INTF0; /*!< Interrupt Force for dormant_wake */ - __IOM uint32_t DORMANT_WAKE_INTF1; /*!< Interrupt Force for dormant_wake */ - __IOM uint32_t DORMANT_WAKE_INTF2; /*!< Interrupt Force for dormant_wake */ - __IOM uint32_t DORMANT_WAKE_INTF3; /*!< Interrupt Force for dormant_wake */ - __IOM uint32_t DORMANT_WAKE_INTF4; /*!< Interrupt Force for dormant_wake */ - __IOM uint32_t DORMANT_WAKE_INTF5; /*!< Interrupt Force for dormant_wake */ - __IOM uint32_t DORMANT_WAKE_INTS0; /*!< Interrupt status after masking & forcing for dormant_wake */ - __IOM uint32_t DORMANT_WAKE_INTS1; /*!< Interrupt status after masking & forcing for dormant_wake */ - __IOM uint32_t DORMANT_WAKE_INTS2; /*!< Interrupt status after masking & forcing for dormant_wake */ - __IOM uint32_t DORMANT_WAKE_INTS3; /*!< Interrupt status after masking & forcing for dormant_wake */ - __IOM uint32_t DORMANT_WAKE_INTS4; /*!< Interrupt status after masking & forcing for dormant_wake */ - __IOM uint32_t DORMANT_WAKE_INTS5; /*!< Interrupt status after masking & forcing for dormant_wake */ -} IO_BANK0_Type; /*!< Size = 800 (0x320) */ - - - -/* =========================================================================================================================== */ -/* ================ SYSINFO ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief SYSINFO (SYSINFO) - */ - -typedef struct { /*!< SYSINFO Structure */ - __IOM uint32_t CHIP_ID; /*!< JEDEC JEP-106 compliant chip identifier. */ - __IOM uint32_t PACKAGE_SEL; /*!< PACKAGE_SEL */ - __IOM uint32_t PLATFORM; /*!< Platform register. Allows software to know what environment - it is running in during pre-production development. Post-production, - the PLATFORM is always ASIC, non-SIM. */ - __IM uint32_t RESERVED[2]; - __IOM uint32_t GITREF_RP2350; /*!< Git hash of the chip source. Used to identify chip version. */ -} SYSINFO_Type; /*!< Size = 24 (0x18) */ - - - -/* =========================================================================================================================== */ -/* ================ SHA256 ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief SHA-256 hash function implementation (SHA256) - */ - -typedef struct { /*!< SHA256 Structure */ - __IOM uint32_t CSR; /*!< Control and status register */ - __IOM uint32_t WDATA; /*!< Write data register */ - __IOM uint32_t SUM0; /*!< 256-bit checksum result. Contents are undefined when CSR_SUM_VLD - is 0. */ - __IOM uint32_t SUM1; /*!< 256-bit checksum result. Contents are undefined when CSR_SUM_VLD - is 0. */ - __IOM uint32_t SUM2; /*!< 256-bit checksum result. Contents are undefined when CSR_SUM_VLD - is 0. */ - __IOM uint32_t SUM3; /*!< 256-bit checksum result. Contents are undefined when CSR_SUM_VLD - is 0. */ - __IOM uint32_t SUM4; /*!< 256-bit checksum result. Contents are undefined when CSR_SUM_VLD - is 0. */ - __IOM uint32_t SUM5; /*!< 256-bit checksum result. Contents are undefined when CSR_SUM_VLD - is 0. */ - __IOM uint32_t SUM6; /*!< 256-bit checksum result. Contents are undefined when CSR_SUM_VLD - is 0. */ - __IOM uint32_t SUM7; /*!< 256-bit checksum result. Contents are undefined when CSR_SUM_VLD - is 0. */ -} SHA256_Type; /*!< Size = 40 (0x28) */ - - - -/* =========================================================================================================================== */ -/* ================ HSTX_FIFO ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief FIFO status and write access for HSTX (HSTX_FIFO) - */ - -typedef struct { /*!< HSTX_FIFO Structure */ - __IOM uint32_t STAT; /*!< FIFO status */ - __IOM uint32_t FIFO; /*!< Write access to FIFO */ -} HSTX_FIFO_Type; /*!< Size = 8 (0x8) */ - - - -/* =========================================================================================================================== */ -/* ================ HSTX_CTRL ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief Control interface to HSTX. For FIFO write access and status, see the HSTX_FIFO register block. (HSTX_CTRL) - */ - -typedef struct { /*!< HSTX_CTRL Structure */ - __IOM uint32_t CSR; /*!< CSR */ - __IOM uint32_t BIT0; /*!< Data control register for output bit 0 */ - __IOM uint32_t BIT1; /*!< Data control register for output bit 1 */ - __IOM uint32_t BIT2; /*!< Data control register for output bit 2 */ - __IOM uint32_t BIT3; /*!< Data control register for output bit 3 */ - __IOM uint32_t BIT4; /*!< Data control register for output bit 4 */ - __IOM uint32_t BIT5; /*!< Data control register for output bit 5 */ - __IOM uint32_t BIT6; /*!< Data control register for output bit 6 */ - __IOM uint32_t BIT7; /*!< Data control register for output bit 7 */ - __IOM uint32_t EXPAND_SHIFT; /*!< Configure the optional shifter inside the command expander */ - __IOM uint32_t EXPAND_TMDS; /*!< Configure the optional TMDS encoder inside the command expander */ -} HSTX_CTRL_Type; /*!< Size = 44 (0x2c) */ - - - -/* =========================================================================================================================== */ -/* ================ EPPB ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief Cortex-M33 EPPB vendor register block for RP2350 (EPPB) - */ - -typedef struct { /*!< EPPB Structure */ - __IOM uint32_t NMI_MASK0; /*!< NMI mask for IRQs 0 through 31. This register is core-local, - and is reset by a processor warm reset. */ - __IOM uint32_t NMI_MASK1; /*!< NMI mask for IRQs 0 though 51. This register is core-local, - and is reset by a processor warm reset. */ - __IOM uint32_t SLEEPCTRL; /*!< Nonstandard sleep control register */ -} EPPB_Type; /*!< Size = 12 (0xc) */ - - - -/* =========================================================================================================================== */ -/* ================ PPB ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief TEAL registers accessible through the debug interface (PPB) - */ - -typedef struct { /*!< PPB Structure */ - __IOM uint32_t ITM_STIM0; /*!< Provides the interface for generating Instrumentation packets */ - __IOM uint32_t ITM_STIM1; /*!< Provides the interface for generating Instrumentation packets */ - __IOM uint32_t ITM_STIM2; /*!< Provides the interface for generating Instrumentation packets */ - __IOM uint32_t ITM_STIM3; /*!< Provides the interface for generating Instrumentation packets */ - __IOM uint32_t ITM_STIM4; /*!< Provides the interface for generating Instrumentation packets */ - __IOM uint32_t ITM_STIM5; /*!< Provides the interface for generating Instrumentation packets */ - __IOM uint32_t ITM_STIM6; /*!< Provides the interface for generating Instrumentation packets */ - __IOM uint32_t ITM_STIM7; /*!< Provides the interface for generating Instrumentation packets */ - __IOM uint32_t ITM_STIM8; /*!< Provides the interface for generating Instrumentation packets */ - __IOM uint32_t ITM_STIM9; /*!< Provides the interface for generating Instrumentation packets */ - __IOM uint32_t ITM_STIM10; /*!< Provides the interface for generating Instrumentation packets */ - __IOM uint32_t ITM_STIM11; /*!< Provides the interface for generating Instrumentation packets */ - __IOM uint32_t ITM_STIM12; /*!< Provides the interface for generating Instrumentation packets */ - __IOM uint32_t ITM_STIM13; /*!< Provides the interface for generating Instrumentation packets */ - __IOM uint32_t ITM_STIM14; /*!< Provides the interface for generating Instrumentation packets */ - __IOM uint32_t ITM_STIM15; /*!< Provides the interface for generating Instrumentation packets */ - __IOM uint32_t ITM_STIM16; /*!< Provides the interface for generating Instrumentation packets */ - __IOM uint32_t ITM_STIM17; /*!< Provides the interface for generating Instrumentation packets */ - __IOM uint32_t ITM_STIM18; /*!< Provides the interface for generating Instrumentation packets */ - __IOM uint32_t ITM_STIM19; /*!< Provides the interface for generating Instrumentation packets */ - __IOM uint32_t ITM_STIM20; /*!< Provides the interface for generating Instrumentation packets */ - __IOM uint32_t ITM_STIM21; /*!< Provides the interface for generating Instrumentation packets */ - __IOM uint32_t ITM_STIM22; /*!< Provides the interface for generating Instrumentation packets */ - __IOM uint32_t ITM_STIM23; /*!< Provides the interface for generating Instrumentation packets */ - __IOM uint32_t ITM_STIM24; /*!< Provides the interface for generating Instrumentation packets */ - __IOM uint32_t ITM_STIM25; /*!< Provides the interface for generating Instrumentation packets */ - __IOM uint32_t ITM_STIM26; /*!< Provides the interface for generating Instrumentation packets */ - __IOM uint32_t ITM_STIM27; /*!< Provides the interface for generating Instrumentation packets */ - __IOM uint32_t ITM_STIM28; /*!< Provides the interface for generating Instrumentation packets */ - __IOM uint32_t ITM_STIM29; /*!< Provides the interface for generating Instrumentation packets */ - __IOM uint32_t ITM_STIM30; /*!< Provides the interface for generating Instrumentation packets */ - __IOM uint32_t ITM_STIM31; /*!< Provides the interface for generating Instrumentation packets */ - __IM uint32_t RESERVED[864]; - __IOM uint32_t ITM_TER0; /*!< Provide an individual enable bit for each ITM_STIM register */ - __IM uint32_t RESERVED1[15]; - __IOM uint32_t ITM_TPR; /*!< Controls which stimulus ports can be accessed by unprivileged - code */ - __IM uint32_t RESERVED2[15]; - __IOM uint32_t ITM_TCR; /*!< Configures and controls transfers through the ITM interface */ - __IM uint32_t RESERVED3[27]; - __IOM uint32_t INT_ATREADY; /*!< Integration Mode: Read ATB Ready */ - __IM uint32_t RESERVED4; - __IOM uint32_t INT_ATVALID; /*!< Integration Mode: Write ATB Valid */ - __IM uint32_t RESERVED5; - __IOM uint32_t ITM_ITCTRL; /*!< Integration Mode Control Register */ - __IM uint32_t RESERVED6[46]; - __IOM uint32_t ITM_DEVARCH; /*!< Provides CoreSight discovery information for the ITM */ - __IM uint32_t RESERVED7[3]; - __IOM uint32_t ITM_DEVTYPE; /*!< Provides CoreSight discovery information for the ITM */ - __IOM uint32_t ITM_PIDR4; /*!< Provides CoreSight discovery information for the ITM */ - __IOM uint32_t ITM_PIDR5; /*!< Provides CoreSight discovery information for the ITM */ - __IOM uint32_t ITM_PIDR6; /*!< Provides CoreSight discovery information for the ITM */ - __IOM uint32_t ITM_PIDR7; /*!< Provides CoreSight discovery information for the ITM */ - __IOM uint32_t ITM_PIDR0; /*!< Provides CoreSight discovery information for the ITM */ - __IOM uint32_t ITM_PIDR1; /*!< Provides CoreSight discovery information for the ITM */ - __IOM uint32_t ITM_PIDR2; /*!< Provides CoreSight discovery information for the ITM */ - __IOM uint32_t ITM_PIDR3; /*!< Provides CoreSight discovery information for the ITM */ - __IOM uint32_t ITM_CIDR0; /*!< Provides CoreSight discovery information for the ITM */ - __IOM uint32_t ITM_CIDR1; /*!< Provides CoreSight discovery information for the ITM */ - __IOM uint32_t ITM_CIDR2; /*!< Provides CoreSight discovery information for the ITM */ - __IOM uint32_t ITM_CIDR3; /*!< Provides CoreSight discovery information for the ITM */ - __IOM uint32_t DWT_CTRL; /*!< Provides configuration and status information for the DWT unit, - and used to control features of the unit */ - __IOM uint32_t DWT_CYCCNT; /*!< Shows or sets the value of the processor cycle counter, CYCCNT */ - __IM uint32_t RESERVED8; - __IOM uint32_t DWT_EXCCNT; /*!< Counts the total cycles spent in exception processing */ - __IM uint32_t RESERVED9; - __IOM uint32_t DWT_LSUCNT; /*!< Increments on the additional cycles required to execute all - load or store instructions */ - __IOM uint32_t DWT_FOLDCNT; /*!< Increments on the additional cycles required to execute all - load or store instructions */ - __IM uint32_t RESERVED10; - __IOM uint32_t DWT_COMP0; /*!< Provides a reference value for use by watchpoint comparator - 0 */ - __IM uint32_t RESERVED11; - __IOM uint32_t DWT_FUNCTION0; /*!< Controls the operation of watchpoint comparator 0 */ - __IM uint32_t RESERVED12; - __IOM uint32_t DWT_COMP1; /*!< Provides a reference value for use by watchpoint comparator - 1 */ - __IM uint32_t RESERVED13; - __IOM uint32_t DWT_FUNCTION1; /*!< Controls the operation of watchpoint comparator 1 */ - __IM uint32_t RESERVED14; - __IOM uint32_t DWT_COMP2; /*!< Provides a reference value for use by watchpoint comparator - 2 */ - __IM uint32_t RESERVED15; - __IOM uint32_t DWT_FUNCTION2; /*!< Controls the operation of watchpoint comparator 2 */ - __IM uint32_t RESERVED16; - __IOM uint32_t DWT_COMP3; /*!< Provides a reference value for use by watchpoint comparator - 3 */ - __IM uint32_t RESERVED17; - __IOM uint32_t DWT_FUNCTION3; /*!< Controls the operation of watchpoint comparator 3 */ - __IM uint32_t RESERVED18[984]; - __IOM uint32_t DWT_DEVARCH; /*!< Provides CoreSight discovery information for the DWT */ - __IM uint32_t RESERVED19[3]; - __IOM uint32_t DWT_DEVTYPE; /*!< Provides CoreSight discovery information for the DWT */ - __IOM uint32_t DWT_PIDR4; /*!< Provides CoreSight discovery information for the DWT */ - __IOM uint32_t DWT_PIDR5; /*!< Provides CoreSight discovery information for the DWT */ - __IOM uint32_t DWT_PIDR6; /*!< Provides CoreSight discovery information for the DWT */ - __IOM uint32_t DWT_PIDR7; /*!< Provides CoreSight discovery information for the DWT */ - __IOM uint32_t DWT_PIDR0; /*!< Provides CoreSight discovery information for the DWT */ - __IOM uint32_t DWT_PIDR1; /*!< Provides CoreSight discovery information for the DWT */ - __IOM uint32_t DWT_PIDR2; /*!< Provides CoreSight discovery information for the DWT */ - __IOM uint32_t DWT_PIDR3; /*!< Provides CoreSight discovery information for the DWT */ - __IOM uint32_t DWT_CIDR0; /*!< Provides CoreSight discovery information for the DWT */ - __IOM uint32_t DWT_CIDR1; /*!< Provides CoreSight discovery information for the DWT */ - __IOM uint32_t DWT_CIDR2; /*!< Provides CoreSight discovery information for the DWT */ - __IOM uint32_t DWT_CIDR3; /*!< Provides CoreSight discovery information for the DWT */ - __IOM uint32_t FP_CTRL; /*!< Provides FPB implementation information, and the global enable - for the FPB unit */ - __IOM uint32_t FP_REMAP; /*!< Indicates whether the implementation supports Flash Patch remap - and, if it does, holds the target address for remap */ - __IOM uint32_t FP_COMP0; /*!< Holds an address for comparison. The effect of the match depends - on the configuration of the FPB and whether the comparator - is an instruction address comparator or a literal address - comparator */ - __IOM uint32_t FP_COMP1; /*!< Holds an address for comparison. The effect of the match depends - on the configuration of the FPB and whether the comparator - is an instruction address comparator or a literal address - comparator */ - __IOM uint32_t FP_COMP2; /*!< Holds an address for comparison. The effect of the match depends - on the configuration of the FPB and whether the comparator - is an instruction address comparator or a literal address - comparator */ - __IOM uint32_t FP_COMP3; /*!< Holds an address for comparison. The effect of the match depends - on the configuration of the FPB and whether the comparator - is an instruction address comparator or a literal address - comparator */ - __IOM uint32_t FP_COMP4; /*!< Holds an address for comparison. The effect of the match depends - on the configuration of the FPB and whether the comparator - is an instruction address comparator or a literal address - comparator */ - __IOM uint32_t FP_COMP5; /*!< Holds an address for comparison. The effect of the match depends - on the configuration of the FPB and whether the comparator - is an instruction address comparator or a literal address - comparator */ - __IOM uint32_t FP_COMP6; /*!< Holds an address for comparison. The effect of the match depends - on the configuration of the FPB and whether the comparator - is an instruction address comparator or a literal address - comparator */ - __IOM uint32_t FP_COMP7; /*!< Holds an address for comparison. The effect of the match depends - on the configuration of the FPB and whether the comparator - is an instruction address comparator or a literal address - comparator */ - __IM uint32_t RESERVED20[997]; - __IOM uint32_t FP_DEVARCH; /*!< Provides CoreSight discovery information for the FPB */ - __IM uint32_t RESERVED21[3]; - __IOM uint32_t FP_DEVTYPE; /*!< Provides CoreSight discovery information for the FPB */ - __IOM uint32_t FP_PIDR4; /*!< Provides CoreSight discovery information for the FP */ - __IOM uint32_t FP_PIDR5; /*!< Provides CoreSight discovery information for the FP */ - __IOM uint32_t FP_PIDR6; /*!< Provides CoreSight discovery information for the FP */ - __IOM uint32_t FP_PIDR7; /*!< Provides CoreSight discovery information for the FP */ - __IOM uint32_t FP_PIDR0; /*!< Provides CoreSight discovery information for the FP */ - __IOM uint32_t FP_PIDR1; /*!< Provides CoreSight discovery information for the FP */ - __IOM uint32_t FP_PIDR2; /*!< Provides CoreSight discovery information for the FP */ - __IOM uint32_t FP_PIDR3; /*!< Provides CoreSight discovery information for the FP */ - __IOM uint32_t FP_CIDR0; /*!< Provides CoreSight discovery information for the FP */ - __IOM uint32_t FP_CIDR1; /*!< Provides CoreSight discovery information for the FP */ - __IOM uint32_t FP_CIDR2; /*!< Provides CoreSight discovery information for the FP */ - __IOM uint32_t FP_CIDR3; /*!< Provides CoreSight discovery information for the FP */ - __IM uint32_t RESERVED22[11265]; - __IOM uint32_t ICTR; /*!< Provides information about the interrupt controller */ - __IOM uint32_t ACTLR; /*!< Provides IMPLEMENTATION DEFINED configuration and control options */ - __IM uint32_t RESERVED23; - __IOM uint32_t SYST_CSR; /*!< Use the SysTick Control and Status Register to enable the SysTick - features. */ - __IOM uint32_t SYST_RVR; /*!< Use the SysTick Reload Value Register to specify the start value - to load into the current value register when the counter - reaches 0. It can be any value between 0 and 0x00FFFFFF. - A start value of 0 is possible, but has no effect because - the SysTick interrupt and COUNTFLAG are activated when - counting from 1 to 0. The reset value of this register - is UNKNOWN. To generate a multi-shot timer with a period - of N processor clock cycles, use a RELOAD value of N-1. - For example, if the SysTick interrupt is required every - 100 clock pulses, set RELOAD to 99. */ - __IOM uint32_t SYST_CVR; /*!< Use the SysTick Current Value Register to find the current value - in the register. The reset value of this register is UNKNOWN. */ - __IOM uint32_t SYST_CALIB; /*!< Use the SysTick Calibration Value Register to enable software - to scale to any required speed using divide and multiply. */ - __IM uint32_t RESERVED24[56]; - __IOM uint32_t NVIC_ISER0; /*!< Enables or reads the enabled state of each group of 32 interrupts */ - __IOM uint32_t NVIC_ISER1; /*!< Enables or reads the enabled state of each group of 32 interrupts */ - __IM uint32_t RESERVED25[30]; - __IOM uint32_t NVIC_ICER0; /*!< Clears or reads the enabled state of each group of 32 interrupts */ - __IOM uint32_t NVIC_ICER1; /*!< Clears or reads the enabled state of each group of 32 interrupts */ - __IM uint32_t RESERVED26[30]; - __IOM uint32_t NVIC_ISPR0; /*!< Enables or reads the pending state of each group of 32 interrupts */ - __IOM uint32_t NVIC_ISPR1; /*!< Enables or reads the pending state of each group of 32 interrupts */ - __IM uint32_t RESERVED27[30]; - __IOM uint32_t NVIC_ICPR0; /*!< Clears or reads the pending state of each group of 32 interrupts */ - __IOM uint32_t NVIC_ICPR1; /*!< Clears or reads the pending state of each group of 32 interrupts */ - __IM uint32_t RESERVED28[30]; - __IOM uint32_t NVIC_IABR0; /*!< For each group of 32 interrupts, shows the active state of each - interrupt */ - __IOM uint32_t NVIC_IABR1; /*!< For each group of 32 interrupts, shows the active state of each - interrupt */ - __IM uint32_t RESERVED29[30]; - __IOM uint32_t NVIC_ITNS0; /*!< For each group of 32 interrupts, determines whether each interrupt - targets Non-secure or Secure state */ - __IOM uint32_t NVIC_ITNS1; /*!< For each group of 32 interrupts, determines whether each interrupt - targets Non-secure or Secure state */ - __IM uint32_t RESERVED30[30]; - __IOM uint32_t NVIC_IPR0; /*!< Sets or reads interrupt priorities */ - __IOM uint32_t NVIC_IPR1; /*!< Sets or reads interrupt priorities */ - __IOM uint32_t NVIC_IPR2; /*!< Sets or reads interrupt priorities */ - __IOM uint32_t NVIC_IPR3; /*!< Sets or reads interrupt priorities */ - __IOM uint32_t NVIC_IPR4; /*!< Sets or reads interrupt priorities */ - __IOM uint32_t NVIC_IPR5; /*!< Sets or reads interrupt priorities */ - __IOM uint32_t NVIC_IPR6; /*!< Sets or reads interrupt priorities */ - __IOM uint32_t NVIC_IPR7; /*!< Sets or reads interrupt priorities */ - __IOM uint32_t NVIC_IPR8; /*!< Sets or reads interrupt priorities */ - __IOM uint32_t NVIC_IPR9; /*!< Sets or reads interrupt priorities */ - __IOM uint32_t NVIC_IPR10; /*!< Sets or reads interrupt priorities */ - __IOM uint32_t NVIC_IPR11; /*!< Sets or reads interrupt priorities */ - __IOM uint32_t NVIC_IPR12; /*!< Sets or reads interrupt priorities */ - __IOM uint32_t NVIC_IPR13; /*!< Sets or reads interrupt priorities */ - __IOM uint32_t NVIC_IPR14; /*!< Sets or reads interrupt priorities */ - __IOM uint32_t NVIC_IPR15; /*!< Sets or reads interrupt priorities */ - __IM uint32_t RESERVED31[560]; - __IOM uint32_t CPUID; /*!< Provides identification information for the PE, including an - implementer code for the device and a device ID number */ - __IOM uint32_t ICSR; /*!< Controls and provides status information for NMI, PendSV, SysTick - and interrupts */ - __IOM uint32_t VTOR; /*!< The VTOR indicates the offset of the vector table base address - from memory address 0x00000000. */ - __IOM uint32_t AIRCR; /*!< Use the Application Interrupt and Reset Control Register to: - determine data endianness, clear all active state information - from debug halt mode, request a system reset. */ - __IOM uint32_t SCR; /*!< System Control Register. Use the System Control Register for - power-management functions: signal to the system when the - processor can enter a low power state, control how the - processor enters and exits low power states. */ - __IOM uint32_t CCR; /*!< Sets or returns configuration and control data */ - __IOM uint32_t SHPR1; /*!< Sets or returns priority for system handlers 4 - 7 */ - __IOM uint32_t SHPR2; /*!< Sets or returns priority for system handlers 8 - 11 */ - __IOM uint32_t SHPR3; /*!< Sets or returns priority for system handlers 12 - 15 */ - __IOM uint32_t SHCSR; /*!< Provides access to the active and pending status of system exceptions */ - __IOM uint32_t CFSR; /*!< Contains the three Configurable Fault Status Registers. 31:16 - UFSR: Provides information on UsageFault exceptions 15:8 - BFSR: Provides information on BusFault exceptions 7:0 MMFSR: - Provides information on MemManage exceptions */ - __IOM uint32_t HFSR; /*!< Shows the cause of any HardFaults */ - __IOM uint32_t DFSR; /*!< Shows which debug event occurred */ - __IOM uint32_t MMFAR; /*!< Shows the address of the memory location that caused an MPU - fault */ - __IOM uint32_t BFAR; /*!< Shows the address associated with a precise data access BusFault */ - __IM uint32_t RESERVED32; - __IOM uint32_t ID_PFR0; /*!< Gives top-level information about the instruction set supported - by the PE */ - __IOM uint32_t ID_PFR1; /*!< Gives information about the programmers' model and Extensions - support */ - __IOM uint32_t ID_DFR0; /*!< Provides top level information about the debug system */ - __IOM uint32_t ID_AFR0; /*!< Provides information about the IMPLEMENTATION DEFINED features - of the PE */ - __IOM uint32_t ID_MMFR0; /*!< Provides information about the implemented memory model and - memory management support */ - __IOM uint32_t ID_MMFR1; /*!< Provides information about the implemented memory model and - memory management support */ - __IOM uint32_t ID_MMFR2; /*!< Provides information about the implemented memory model and - memory management support */ - __IOM uint32_t ID_MMFR3; /*!< Provides information about the implemented memory model and - memory management support */ - __IOM uint32_t ID_ISAR0; /*!< Provides information about the instruction set implemented by - the PE */ - __IOM uint32_t ID_ISAR1; /*!< Provides information about the instruction set implemented by - the PE */ - __IOM uint32_t ID_ISAR2; /*!< Provides information about the instruction set implemented by - the PE */ - __IOM uint32_t ID_ISAR3; /*!< Provides information about the instruction set implemented by - the PE */ - __IOM uint32_t ID_ISAR4; /*!< Provides information about the instruction set implemented by - the PE */ - __IOM uint32_t ID_ISAR5; /*!< Provides information about the instruction set implemented by - the PE */ - __IM uint32_t RESERVED33; - __IOM uint32_t CTR; /*!< Provides information about the architecture of the caches. CTR - is RES0 if CLIDR is zero. */ - __IM uint32_t RESERVED34[2]; - __IOM uint32_t CPACR; /*!< Specifies the access privileges for coprocessors and the FP - Extension */ - __IOM uint32_t NSACR; /*!< Defines the Non-secure access permissions for both the FP Extension - and coprocessors CP0 to CP7 */ - __IOM uint32_t MPU_TYPE; /*!< The MPU Type Register indicates how many regions the MPU `FTSSS - supports */ - __IOM uint32_t MPU_CTRL; /*!< Enables the MPU and, when the MPU is enabled, controls whether - the default memory map is enabled as a background region - for privileged accesses, and whether the MPU is enabled - for HardFaults, NMIs, and exception handlers when FAULTMASK - is set to 1 */ - __IOM uint32_t MPU_RNR; /*!< Selects the region currently accessed by MPU_RBAR and MPU_RLAR */ - __IOM uint32_t MPU_RBAR; /*!< Provides indirect read and write access to the base address - of the currently selected MPU region `FTSSS */ - __IOM uint32_t MPU_RLAR; /*!< Provides indirect read and write access to the limit address - of the currently selected MPU region `FTSSS */ - __IOM uint32_t MPU_RBAR_A1; /*!< Provides indirect read and write access to the base address - of the MPU region selected by MPU_RNR[7:2]:(1[1:0]) `FTSSS */ - __IOM uint32_t MPU_RLAR_A1; /*!< Provides indirect read and write access to the limit address - of the currently selected MPU region selected by MPU_RNR[7:2]:(1[1:0]) - `FTSSS */ - __IOM uint32_t MPU_RBAR_A2; /*!< Provides indirect read and write access to the base address - of the MPU region selected by MPU_RNR[7:2]:(2[1:0]) `FTSSS */ - __IOM uint32_t MPU_RLAR_A2; /*!< Provides indirect read and write access to the limit address - of the currently selected MPU region selected by MPU_RNR[7:2]:(2[1:0]) - `FTSSS */ - __IOM uint32_t MPU_RBAR_A3; /*!< Provides indirect read and write access to the base address - of the MPU region selected by MPU_RNR[7:2]:(3[1:0]) `FTSSS */ - __IOM uint32_t MPU_RLAR_A3; /*!< Provides indirect read and write access to the limit address - of the currently selected MPU region selected by MPU_RNR[7:2]:(3[1:0]) - `FTSSS */ - __IM uint32_t RESERVED35; - __IOM uint32_t MPU_MAIR0; /*!< Along with MPU_MAIR1, provides the memory attribute encodings - corresponding to the AttrIndex values */ - __IOM uint32_t MPU_MAIR1; /*!< Along with MPU_MAIR0, provides the memory attribute encodings - corresponding to the AttrIndex values */ - __IM uint32_t RESERVED36[2]; - __IOM uint32_t SAU_CTRL; /*!< Allows enabling of the Security Attribution Unit */ - __IOM uint32_t SAU_TYPE; /*!< Indicates the number of regions implemented by the Security - Attribution Unit */ - __IOM uint32_t SAU_RNR; /*!< Selects the region currently accessed by SAU_RBAR and SAU_RLAR */ - __IOM uint32_t SAU_RBAR; /*!< Provides indirect read and write access to the base address - of the currently selected SAU region */ - __IOM uint32_t SAU_RLAR; /*!< Provides indirect read and write access to the limit address - of the currently selected SAU region */ - __IOM uint32_t SFSR; /*!< Provides information about any security related faults */ - __IOM uint32_t SFAR; /*!< Shows the address of the memory location that caused a Security - violation */ - __IM uint32_t RESERVED37; - __IOM uint32_t DHCSR; /*!< Controls halting debug */ - __IOM uint32_t DCRSR; /*!< With the DCRDR, provides debug access to the general-purpose - registers, special-purpose registers, and the FP extension - registers. A write to the DCRSR specifies the register - to transfer, whether the transfer is a read or write, and - starts the transfer */ - __IOM uint32_t DCRDR; /*!< With the DCRSR, provides debug access to the general-purpose - registers, special-purpose registers, and the FP Extension - registers. If the Main Extension is implemented, it can - also be used for message passing between an external debugger - and a debug agent running on the PE */ - __IOM uint32_t DEMCR; /*!< Manages vector catch behavior and DebugMonitor handling when - debugging */ - __IM uint32_t RESERVED38[2]; - __IOM uint32_t DSCSR; /*!< Provides control and status information for Secure debug */ - __IM uint32_t RESERVED39[61]; - __IOM uint32_t STIR; /*!< Provides a mechanism for software to generate an interrupt */ - __IM uint32_t RESERVED40[12]; - __IOM uint32_t FPCCR; /*!< Holds control data for the Floating-point extension */ - __IOM uint32_t FPCAR; /*!< Holds the location of the unpopulated floating-point register - space allocated on an exception stack frame */ - __IOM uint32_t FPDSCR; /*!< Holds the default values for the floating-point status control - data that the PE assigns to the FPSCR when it creates a - new floating-point context */ - __IOM uint32_t MVFR0; /*!< Describes the features provided by the Floating-point Extension */ - __IOM uint32_t MVFR1; /*!< Describes the features provided by the Floating-point Extension */ - __IOM uint32_t MVFR2; /*!< Describes the features provided by the Floating-point Extension */ - __IM uint32_t RESERVED41[28]; - __IOM uint32_t DDEVARCH; /*!< Provides CoreSight discovery information for the SCS */ - __IM uint32_t RESERVED42[3]; - __IOM uint32_t DDEVTYPE; /*!< Provides CoreSight discovery information for the SCS */ - __IOM uint32_t DPIDR4; /*!< Provides CoreSight discovery information for the SCS */ - __IOM uint32_t DPIDR5; /*!< Provides CoreSight discovery information for the SCS */ - __IOM uint32_t DPIDR6; /*!< Provides CoreSight discovery information for the SCS */ - __IOM uint32_t DPIDR7; /*!< Provides CoreSight discovery information for the SCS */ - __IOM uint32_t DPIDR0; /*!< Provides CoreSight discovery information for the SCS */ - __IOM uint32_t DPIDR1; /*!< Provides CoreSight discovery information for the SCS */ - __IOM uint32_t DPIDR2; /*!< Provides CoreSight discovery information for the SCS */ - __IOM uint32_t DPIDR3; /*!< Provides CoreSight discovery information for the SCS */ - __IOM uint32_t DCIDR0; /*!< Provides CoreSight discovery information for the SCS */ - __IOM uint32_t DCIDR1; /*!< Provides CoreSight discovery information for the SCS */ - __IOM uint32_t DCIDR2; /*!< Provides CoreSight discovery information for the SCS */ - __IOM uint32_t DCIDR3; /*!< Provides CoreSight discovery information for the SCS */ - __IM uint32_t RESERVED43[51201]; - __IOM uint32_t TRCPRGCTLR; /*!< Programming Control Register */ - __IM uint32_t RESERVED44; - __IOM uint32_t TRCSTATR; /*!< The TRCSTATR indicates the ETM-Teal status */ - __IOM uint32_t TRCCONFIGR; /*!< The TRCCONFIGR sets the basic tracing options for the trace - unit */ - __IM uint32_t RESERVED45[3]; - __IOM uint32_t TRCEVENTCTL0R; /*!< The TRCEVENTCTL0R controls the tracing of events in the trace - stream. The events also drive the ETM-Teal external outputs. */ - __IOM uint32_t TRCEVENTCTL1R; /*!< The TRCEVENTCTL1R controls how the events selected by TRCEVENTCTL0R - behave */ - __IM uint32_t RESERVED46; - __IOM uint32_t TRCSTALLCTLR; /*!< The TRCSTALLCTLR enables ETM-Teal to stall the processor if - the ETM-Teal FIFO goes over the programmed level to minimize - risk of overflow */ - __IOM uint32_t TRCTSCTLR; /*!< The TRCTSCTLR controls the insertion of global timestamps into - the trace stream. A timestamp is always inserted into the - instruction trace stream */ - __IOM uint32_t TRCSYNCPR; /*!< The TRCSYNCPR specifies the period of trace synchronization - of the trace streams. TRCSYNCPR defines a number of bytes - of trace between requests for trace synchronization. This - value is always a power of two */ - __IOM uint32_t TRCCCCTLR; /*!< The TRCCCCTLR sets the threshold value for instruction trace - cycle counting. The threshold represents the minimum interval - between cycle count trace packets */ - __IM uint32_t RESERVED47[17]; - __IOM uint32_t TRCVICTLR; /*!< The TRCVICTLR controls instruction trace filtering */ - __IM uint32_t RESERVED48[47]; - __IOM uint32_t TRCCNTRLDVR0; /*!< The TRCCNTRLDVR defines the reload value for the reduced function - counter */ - __IM uint32_t RESERVED49[15]; - __IOM uint32_t TRCIDR8; /*!< TRCIDR8 */ - __IOM uint32_t TRCIDR9; /*!< TRCIDR9 */ - __IOM uint32_t TRCIDR10; /*!< TRCIDR10 */ - __IOM uint32_t TRCIDR11; /*!< TRCIDR11 */ - __IOM uint32_t TRCIDR12; /*!< TRCIDR12 */ - __IOM uint32_t TRCIDR13; /*!< TRCIDR13 */ - __IM uint32_t RESERVED50[10]; - __IOM uint32_t TRCIMSPEC; /*!< The TRCIMSPEC shows the presence of any IMPLEMENTATION SPECIFIC - features, and enables any features that are provided */ - __IM uint32_t RESERVED51[7]; - __IOM uint32_t TRCIDR0; /*!< TRCIDR0 */ - __IOM uint32_t TRCIDR1; /*!< TRCIDR1 */ - __IOM uint32_t TRCIDR2; /*!< TRCIDR2 */ - __IOM uint32_t TRCIDR3; /*!< TRCIDR3 */ - __IOM uint32_t TRCIDR4; /*!< TRCIDR4 */ - __IOM uint32_t TRCIDR5; /*!< TRCIDR5 */ - __IOM uint32_t TRCIDR6; /*!< TRCIDR6 */ - __IOM uint32_t TRCIDR7; /*!< TRCIDR7 */ - __IM uint32_t RESERVED52[2]; - __IOM uint32_t TRCRSCTLR2; /*!< The TRCRSCTLR controls the trace resources */ - __IOM uint32_t TRCRSCTLR3; /*!< The TRCRSCTLR controls the trace resources */ - __IM uint32_t RESERVED53[36]; - __IOM uint32_t TRCSSCSR; /*!< Controls the corresponding single-shot comparator resource */ - __IM uint32_t RESERVED54[7]; - __IOM uint32_t TRCSSPCICR; /*!< Selects the PE comparator inputs for Single-shot control */ - __IM uint32_t RESERVED55[19]; - __IOM uint32_t TRCPDCR; /*!< Requests the system to provide power to the trace unit */ - __IOM uint32_t TRCPDSR; /*!< Returns the following information about the trace unit: - OS - Lock status. - Core power domain status. - Power interruption - status */ - __IM uint32_t RESERVED56[755]; - __IOM uint32_t TRCITATBIDR; /*!< Trace Integration ATB Identification Register */ - __IM uint32_t RESERVED57[3]; - __IOM uint32_t TRCITIATBINR; /*!< Trace Integration Instruction ATB In Register */ - __IM uint32_t RESERVED58; - __IOM uint32_t TRCITIATBOUTR; /*!< Trace Integration Instruction ATB Out Register */ - __IM uint32_t RESERVED59[40]; - __IOM uint32_t TRCCLAIMSET; /*!< Claim Tag Set Register */ - __IOM uint32_t TRCCLAIMCLR; /*!< Claim Tag Clear Register */ - __IM uint32_t RESERVED60[4]; - __IOM uint32_t TRCAUTHSTATUS; /*!< Returns the level of tracing that the trace unit can support */ - __IOM uint32_t TRCDEVARCH; /*!< TRCDEVARCH */ - __IM uint32_t RESERVED61[2]; - __IOM uint32_t TRCDEVID; /*!< TRCDEVID */ - __IOM uint32_t TRCDEVTYPE; /*!< TRCDEVTYPE */ - __IOM uint32_t TRCPIDR4; /*!< TRCPIDR4 */ - __IOM uint32_t TRCPIDR5; /*!< TRCPIDR5 */ - __IOM uint32_t TRCPIDR6; /*!< TRCPIDR6 */ - __IOM uint32_t TRCPIDR7; /*!< TRCPIDR7 */ - __IOM uint32_t TRCPIDR0; /*!< TRCPIDR0 */ - __IOM uint32_t TRCPIDR1; /*!< TRCPIDR1 */ - __IOM uint32_t TRCPIDR2; /*!< TRCPIDR2 */ - __IOM uint32_t TRCPIDR3; /*!< TRCPIDR3 */ - __IOM uint32_t TRCCIDR0; /*!< TRCCIDR0 */ - __IOM uint32_t TRCCIDR1; /*!< TRCCIDR1 */ - __IOM uint32_t TRCCIDR2; /*!< TRCCIDR2 */ - __IOM uint32_t TRCCIDR3; /*!< TRCCIDR3 */ - __IOM uint32_t CTICONTROL; /*!< CTI Control Register */ - __IM uint32_t RESERVED62[3]; - __IOM uint32_t CTIINTACK; /*!< CTI Interrupt Acknowledge Register */ - __IOM uint32_t CTIAPPSET; /*!< CTI Application Trigger Set Register */ - __IOM uint32_t CTIAPPCLEAR; /*!< CTI Application Trigger Clear Register */ - __IOM uint32_t CTIAPPPULSE; /*!< CTI Application Pulse Register */ - __IOM uint32_t CTIINEN0; /*!< CTI Trigger to Channel Enable Registers */ - __IOM uint32_t CTIINEN1; /*!< CTI Trigger to Channel Enable Registers */ - __IOM uint32_t CTIINEN2; /*!< CTI Trigger to Channel Enable Registers */ - __IOM uint32_t CTIINEN3; /*!< CTI Trigger to Channel Enable Registers */ - __IOM uint32_t CTIINEN4; /*!< CTI Trigger to Channel Enable Registers */ - __IOM uint32_t CTIINEN5; /*!< CTI Trigger to Channel Enable Registers */ - __IOM uint32_t CTIINEN6; /*!< CTI Trigger to Channel Enable Registers */ - __IOM uint32_t CTIINEN7; /*!< CTI Trigger to Channel Enable Registers */ - __IM uint32_t RESERVED63[24]; - __IOM uint32_t CTIOUTEN0; /*!< CTI Trigger to Channel Enable Registers */ - __IOM uint32_t CTIOUTEN1; /*!< CTI Trigger to Channel Enable Registers */ - __IOM uint32_t CTIOUTEN2; /*!< CTI Trigger to Channel Enable Registers */ - __IOM uint32_t CTIOUTEN3; /*!< CTI Trigger to Channel Enable Registers */ - __IOM uint32_t CTIOUTEN4; /*!< CTI Trigger to Channel Enable Registers */ - __IOM uint32_t CTIOUTEN5; /*!< CTI Trigger to Channel Enable Registers */ - __IOM uint32_t CTIOUTEN6; /*!< CTI Trigger to Channel Enable Registers */ - __IOM uint32_t CTIOUTEN7; /*!< CTI Trigger to Channel Enable Registers */ - __IM uint32_t RESERVED64[28]; - __IOM uint32_t CTITRIGINSTATUS; /*!< CTI Trigger to Channel Enable Registers */ - __IOM uint32_t CTITRIGOUTSTATUS; /*!< CTI Trigger In Status Register */ - __IOM uint32_t CTICHINSTATUS; /*!< CTI Channel In Status Register */ - __IM uint32_t RESERVED65; - __IOM uint32_t CTIGATE; /*!< Enable CTI Channel Gate register */ - __IOM uint32_t ASICCTL; /*!< External Multiplexer Control register */ - __IM uint32_t RESERVED66[871]; - __IOM uint32_t ITCHOUT; /*!< Integration Test Channel Output register */ - __IOM uint32_t ITTRIGOUT; /*!< Integration Test Trigger Output register */ - __IM uint32_t RESERVED67[2]; - __IOM uint32_t ITCHIN; /*!< Integration Test Channel Input register */ - __IM uint32_t RESERVED68[2]; - __IOM uint32_t ITCTRL; /*!< Integration Mode Control register */ - __IM uint32_t RESERVED69[46]; - __IOM uint32_t DEVARCH; /*!< Device Architecture register */ - __IM uint32_t RESERVED70[2]; - __IOM uint32_t DEVID; /*!< Device Configuration register */ - __IOM uint32_t DEVTYPE; /*!< Device Type Identifier register */ - __IOM uint32_t PIDR4; /*!< CoreSight Peripheral ID4 */ - __IOM uint32_t PIDR5; /*!< CoreSight Peripheral ID5 */ - __IOM uint32_t PIDR6; /*!< CoreSight Peripheral ID6 */ - __IOM uint32_t PIDR7; /*!< CoreSight Peripheral ID7 */ - __IOM uint32_t PIDR0; /*!< CoreSight Peripheral ID0 */ - __IOM uint32_t PIDR1; /*!< CoreSight Peripheral ID1 */ - __IOM uint32_t PIDR2; /*!< CoreSight Peripheral ID2 */ - __IOM uint32_t PIDR3; /*!< CoreSight Peripheral ID3 */ - __IOM uint32_t CIDR0; /*!< CoreSight Component ID0 */ - __IOM uint32_t CIDR1; /*!< CoreSight Component ID1 */ - __IOM uint32_t CIDR2; /*!< CoreSight Component ID2 */ - __IOM uint32_t CIDR3; /*!< CoreSight Component ID3 */ -} PPB_Type; /*!< Size = 274432 (0x43000) */ - - - -/* =========================================================================================================================== */ -/* ================ QMI ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief QSPI Memory Interface. - - Provides a memory-mapped interface to up to two SPI/DSPI/QSPI flash or PSRAM devices. Also provides a serial interface for programming and configuration of the external device. (QMI) - */ - -typedef struct { /*!< QMI Structure */ - __IOM uint32_t DIRECT_CSR; /*!< Control and status for direct serial mode Direct serial mode - allows the processor to send and receive raw serial frames, - for programming, configuration and control of the external - memory devices. Only SPI mode 0 (CPOL=0 CPHA=0) is supported. */ - __IOM uint32_t DIRECT_TX; /*!< Transmit FIFO for direct mode */ - __IOM uint32_t DIRECT_RX; /*!< Receive FIFO for direct mode */ - __IOM uint32_t M0_TIMING; /*!< Timing configuration register for memory address window 0. */ - __IOM uint32_t M0_RFMT; /*!< Read transfer format configuration for memory address window - 0. Configure the bus width of each transfer phase individually, - and configure the length or presence of the command prefix, - command suffix and dummy/turnaround transfer phases. Only - 24-bit addresses are supported. The reset value of the - M0_RFMT register is configured to support a basic 03h serial - read transfer with no additional configuration. */ - __IOM uint32_t M0_RCMD; /*!< Command constants used for reads from memory address window - 0. The reset value of the M0_RCMD register is configured - to support a basic 03h serial read transfer with no additional - configuration. */ - __IOM uint32_t M0_WFMT; /*!< Write transfer format configuration for memory address window - 0. Configure the bus width of each transfer phase individually, - and configure the length or presence of the command prefix, - command suffix and dummy/turnaround transfer phases. Only - 24-bit addresses are supported. The reset value of the - M0_WFMT register is configured to support a basic 02h serial - write transfer. However, writes to this window must first - be enabled via the XIP_CTRL_WRITABLE_M0 bit, as XIP memory - is read-only by default. */ - __IOM uint32_t M0_WCMD; /*!< Command constants used for writes to memory address window 0. - The reset value of the M0_WCMD register is configured to - support a basic 02h serial write transfer with no additional - configuration. */ - __IOM uint32_t M1_TIMING; /*!< Timing configuration register for memory address window 1. */ - __IOM uint32_t M1_RFMT; /*!< Read transfer format configuration for memory address window - 1. Configure the bus width of each transfer phase individually, - and configure the length or presence of the command prefix, - command suffix and dummy/turnaround transfer phases. Only - 24-bit addresses are supported. The reset value of the - M1_RFMT register is configured to support a basic 03h serial - read transfer with no additional configuration. */ - __IOM uint32_t M1_RCMD; /*!< Command constants used for reads from memory address window - 1. The reset value of the M1_RCMD register is configured - to support a basic 03h serial read transfer with no additional - configuration. */ - __IOM uint32_t M1_WFMT; /*!< Write transfer format configuration for memory address window - 1. Configure the bus width of each transfer phase individually, - and configure the length or presence of the command prefix, - command suffix and dummy/turnaround transfer phases. Only - 24-bit addresses are supported. The reset value of the - M1_WFMT register is configured to support a basic 02h serial - write transfer. However, writes to this window must first - be enabled via the XIP_CTRL_WRITABLE_M1 bit, as XIP memory - is read-only by default. */ - __IOM uint32_t M1_WCMD; /*!< Command constants used for writes to memory address window 1. - The reset value of the M1_WCMD register is configured to - support a basic 02h serial write transfer with no additional - configuration. */ - __IOM uint32_t ATRANS0; /*!< Configure address translation for XIP virtual addresses 0x000000 - through 0x3fffff (a 4 MiB window starting at +0 MiB). Address - translation allows a program image to be executed in place - at multiple physical flash addresses (for example, a double-buffered - flash image for over-the-air updates), without the overhead - of position-independent code. At reset, the address translation - registers are initialised to an identity mapping, so that - they can be ignored if address translation is not required. - Note that the XIP cache is fully virtually addressed, so - a cache flush is required after changing the address translation. */ - __IOM uint32_t ATRANS1; /*!< Configure address translation for XIP virtual addresses 0x400000 - through 0x7fffff (a 4 MiB window starting at +4 MiB). Address - translation allows a program image to be executed in place - at multiple physical flash addresses (for example, a double-buffered - flash image for over-the-air updates), without the overhead - of position-independent code. At reset, the address translation - registers are initialised to an identity mapping, so that - they can be ignored if address translation is not required. - Note that the XIP cache is fully virtually addressed, so - a cache flush is required after changing the address translation. */ - __IOM uint32_t ATRANS2; /*!< Configure address translation for XIP virtual addresses 0x800000 - through 0xbfffff (a 4 MiB window starting at +8 MiB). Address - translation allows a program image to be executed in place - at multiple physical flash addresses (for example, a double-buffered - flash image for over-the-air updates), without the overhead - of position-independent code. At reset, the address translation - registers are initialised to an identity mapping, so that - they can be ignored if address translation is not required. - Note that the XIP cache is fully virtually addressed, so - a cache flush is required after changing the address translation. */ - __IOM uint32_t ATRANS3; /*!< Configure address translation for XIP virtual addresses 0xc00000 - through 0xffffff (a 4 MiB window starting at +12 MiB). - Address translation allows a program image to be executed - in place at multiple physical flash addresses (for example, - a double-buffered flash image for over-the-air updates), - without the overhead of position-independent code. At reset, - the address translation registers are initialised to an - identity mapping, so that they can be ignored if address - translation is not required. Note that the XIP cache is - fully virtually addressed, so a cache flush is required - after changing the address translation. */ - __IOM uint32_t ATRANS4; /*!< Configure address translation for XIP virtual addresses 0x1000000 - through 0x13fffff (a 4 MiB window starting at +16 MiB). - Address translation allows a program image to be executed - in place at multiple physical flash addresses (for example, - a double-buffered flash image for over-the-air updates), - without the overhead of position-independent code. At reset, - the address translation registers are initialised to an - identity mapping, so that they can be ignored if address - translation is not required. Note that the XIP cache is - fully virtually addressed, so a cache flush is required - after changing the address translation. */ - __IOM uint32_t ATRANS5; /*!< Configure address translation for XIP virtual addresses 0x1400000 - through 0x17fffff (a 4 MiB window starting at +20 MiB). - Address translation allows a program image to be executed - in place at multiple physical flash addresses (for example, - a double-buffered flash image for over-the-air updates), - without the overhead of position-independent code. At reset, - the address translation registers are initialised to an - identity mapping, so that they can be ignored if address - translation is not required. Note that the XIP cache is - fully virtually addressed, so a cache flush is required - after changing the address translation. */ - __IOM uint32_t ATRANS6; /*!< Configure address translation for XIP virtual addresses 0x1800000 - through 0x1bfffff (a 4 MiB window starting at +24 MiB). - Address translation allows a program image to be executed - in place at multiple physical flash addresses (for example, - a double-buffered flash image for over-the-air updates), - without the overhead of position-independent code. At reset, - the address translation registers are initialised to an - identity mapping, so that they can be ignored if address - translation is not required. Note that the XIP cache is - fully virtually addressed, so a cache flush is required - after changing the address translation. */ - __IOM uint32_t ATRANS7; /*!< Configure address translation for XIP virtual addresses 0x1c00000 - through 0x1ffffff (a 4 MiB window starting at +28 MiB). - Address translation allows a program image to be executed - in place at multiple physical flash addresses (for example, - a double-buffered flash image for over-the-air updates), - without the overhead of position-independent code. At reset, - the address translation registers are initialised to an - identity mapping, so that they can be ignored if address - translation is not required. Note that the XIP cache is - fully virtually addressed, so a cache flush is required - after changing the address translation. */ -} QMI_Type; /*!< Size = 84 (0x54) */ - - - -/* =========================================================================================================================== */ -/* ================ XIP_CTRL ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief QSPI flash execute-in-place block (XIP_CTRL) - */ - -typedef struct { /*!< XIP_CTRL Structure */ - __IOM uint32_t CTRL; /*!< Cache control register. Read-only from a Non-secure context. */ - __IM uint32_t RESERVED; - __IOM uint32_t STAT; /*!< STAT */ - __IOM uint32_t CTR_HIT; /*!< Cache Hit counter */ - __IOM uint32_t CTR_ACC; /*!< Cache Access counter */ - __IOM uint32_t STREAM_ADDR; /*!< FIFO stream address */ - __IOM uint32_t STREAM_CTR; /*!< FIFO stream control */ - __IOM uint32_t STREAM_FIFO; /*!< FIFO stream data */ -} XIP_CTRL_Type; /*!< Size = 32 (0x20) */ - - - -/* =========================================================================================================================== */ -/* ================ XIP_AUX ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief Auxiliary DMA access to XIP FIFOs, via fast AHB bus access (XIP_AUX) - */ - -typedef struct { /*!< XIP_AUX Structure */ - __IOM uint32_t STREAM; /*!< Read the XIP stream FIFO (fast bus access to XIP_CTRL_STREAM_FIFO) */ - __IOM uint32_t QMI_DIRECT_TX; /*!< Write to the QMI direct-mode TX FIFO (fast bus access to QMI_DIRECT_TX) */ - __IOM uint32_t QMI_DIRECT_RX; /*!< Read from the QMI direct-mode RX FIFO (fast bus access to QMI_DIRECT_RX) */ -} XIP_AUX_Type; /*!< Size = 12 (0xc) */ - - - -/* =========================================================================================================================== */ -/* ================ SYSCFG ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief Register block for various chip control signals (SYSCFG) - */ - -typedef struct { /*!< SYSCFG Structure */ - __IOM uint32_t PROC_CONFIG; /*!< Configuration for processors */ - __IOM uint32_t PROC_IN_SYNC_BYPASS; /*!< For each bit, if 1, bypass the input synchronizer between that - GPIO and the GPIO input register in the SIO. The input - synchronizers should generally be unbypassed, to avoid - injecting metastabilities into processors. If you're feeling - brave, you can bypass to save two cycles of input latency. - This register applies to GPIO 0...31. */ - __IOM uint32_t PROC_IN_SYNC_BYPASS_HI; /*!< For each bit, if 1, bypass the input synchronizer between that - GPIO and the GPIO input register in the SIO. The input - synchronizers should generally be unbypassed, to avoid - injecting metastabilities into processors. If you're feeling - brave, you can bypass to save two cycles of input latency. - This register applies to GPIO 32...47. USB GPIO 56..57 - QSPI GPIO 58..63 */ - __IOM uint32_t DBGFORCE; /*!< Directly control the chip SWD debug port */ - __IOM uint32_t MEMPOWERDOWN; /*!< Control PD pins to memories. Set high to put memories to a low - power state. In this state the memories will retain contents - but not be accessible Use with caution */ - __IOM uint32_t AUXCTRL; /*!< Auxiliary system control register */ -} SYSCFG_Type; /*!< Size = 24 (0x18) */ - - - -/* =========================================================================================================================== */ -/* ================ XOSC ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief Controls the crystal oscillator (XOSC) - */ - -typedef struct { /*!< XOSC Structure */ - __IOM uint32_t CTRL; /*!< Crystal Oscillator Control */ - __IOM uint32_t STATUS; /*!< Crystal Oscillator Status */ - __IOM uint32_t DORMANT; /*!< Crystal Oscillator pause control */ - __IOM uint32_t STARTUP; /*!< Controls the startup delay */ - __IOM uint32_t COUNT; /*!< A down counter running at the xosc frequency which counts to - zero and stops. Can be used for short software pauses when - setting up time sensitive hardware. To start the counter, - write a non-zero value. Reads will return 1 while the count - is running and 0 when it has finished. Minimum count value - is 4. Count values <4 will be treated as count value =4. - Note that synchronisation to the register clock domain - costs 2 register clock cycles and the counter cannot compensate - for that. */ -} XOSC_Type; /*!< Size = 20 (0x14) */ - - - -/* =========================================================================================================================== */ -/* ================ PLL_SYS ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief PLL_SYS (PLL_SYS) - */ - -typedef struct { /*!< PLL_SYS Structure */ - __IOM uint32_t CS; /*!< Control and Status GENERAL CONSTRAINTS: Reference clock frequency - min=5MHz, max=800MHz Feedback divider min=16, max=320 VCO - frequency min=750MHz, max=1600MHz */ - __IOM uint32_t PWR; /*!< Controls the PLL power modes. */ - __IOM uint32_t FBDIV_INT; /*!< Feedback divisor (note: this PLL does not support fractional - division) */ - __IOM uint32_t PRIM; /*!< Controls the PLL post dividers for the primary output (note: - this PLL does not have a secondary output) the primary - output is driven from VCO divided by postdiv1*postdiv2 */ - __IOM uint32_t INTR; /*!< Raw Interrupts */ - __IOM uint32_t INTE; /*!< Interrupt Enable */ - __IOM uint32_t INTF; /*!< Interrupt Force */ - __IOM uint32_t INTS; /*!< Interrupt status after masking & forcing */ -} PLL_SYS_Type; /*!< Size = 32 (0x20) */ - - - -/* =========================================================================================================================== */ -/* ================ ACCESSCTRL ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief Hardware access control registers (ACCESSCTRL) - */ - -typedef struct { /*!< ACCESSCTRL Structure */ - __IOM uint32_t LOCK; /*!< Once a LOCK bit is written to 1, ACCESSCTRL silently ignores - writes from that master. LOCK is writable only by a Secure, - Privileged processor or debugger. LOCK bits are only writable - when their value is zero. Once set, they can never be cleared, - except by a full reset of ACCESSCTRL Setting the LOCK bit - does not affect whether an access raises a bus error. Unprivileged - writes, or writes from the DMA, will continue to raise - bus errors. All other accesses will continue not to. */ - __IOM uint32_t FORCE_CORE_NS; /*!< Force core 1's bus accesses to always be Non-secure, no matter - the core's internal state. Useful for schemes where one - core is designated as the Non-secure core, since some peripherals - may filter individual registers internally based on security - state but not on master ID. */ - __IOM uint32_t CFGRESET; /*!< Write 1 to reset all ACCESSCTRL configuration, except for the - LOCK and FORCE_CORE_NS registers. This bit is used in the - RP2350 bootrom to quickly restore ACCESSCTRL to a known - state during the boot path. Note that, like all registers - in ACCESSCTRL, this register is not writable when the writer's - corresponding LOCK bit is set, therefore a master which - has been locked out of ACCESSCTRL can not use the CFGRESET - register to disturb its contents. */ - __IOM uint32_t GPIO_NSMASK0; /*!< Control whether GPIO0...31 are accessible to Non-secure code. - Writable only by a Secure, Privileged processor or debugger. - 0 -> Secure access only 1 -> Secure + Non-secure access */ - __IOM uint32_t GPIO_NSMASK1; /*!< Control whether GPIO32..47 are accessible to Non-secure code, - and whether QSPI and USB bitbang are accessible through - the Non-secure SIO. Writable only by a Secure, Privileged - processor or debugger. */ - __IOM uint32_t ROM; /*!< Control whether debugger, DMA, core 0 and core 1 can access - ROM, and at what security/privilege levels they can do - so. Defaults to fully open access. This register is writable - only from a Secure, Privileged processor or debugger, with - the exception of the NSU bit, which becomes Non-secure-Privileged-writabl - when the NSP bit is set. */ - __IOM uint32_t XIP_MAIN; /*!< Control whether debugger, DMA, core 0 and core 1 can access - XIP_MAIN, and at what security/privilege levels they can - do so. Defaults to fully open access. This register is - writable only from a Secure, Privileged processor or debugger, - with the exception of the NSU bit, which becomes Non-secure-Privileged-wr - table when the NSP bit is set. */ - __IOM uint32_t SRAM0; /*!< Control whether debugger, DMA, core 0 and core 1 can access - SRAM0, and at what security/privilege levels they can do - so. Defaults to fully open access. This register is writable - only from a Secure, Privileged processor or debugger, with - the exception of the NSU bit, which becomes Non-secure-Privileged-writabl - when the NSP bit is set. */ - __IOM uint32_t SRAM1; /*!< Control whether debugger, DMA, core 0 and core 1 can access - SRAM1, and at what security/privilege levels they can do - so. Defaults to fully open access. This register is writable - only from a Secure, Privileged processor or debugger, with - the exception of the NSU bit, which becomes Non-secure-Privileged-writabl - when the NSP bit is set. */ - __IOM uint32_t SRAM2; /*!< Control whether debugger, DMA, core 0 and core 1 can access - SRAM2, and at what security/privilege levels they can do - so. Defaults to fully open access. This register is writable - only from a Secure, Privileged processor or debugger, with - the exception of the NSU bit, which becomes Non-secure-Privileged-writabl - when the NSP bit is set. */ - __IOM uint32_t SRAM3; /*!< Control whether debugger, DMA, core 0 and core 1 can access - SRAM3, and at what security/privilege levels they can do - so. Defaults to fully open access. This register is writable - only from a Secure, Privileged processor or debugger, with - the exception of the NSU bit, which becomes Non-secure-Privileged-writabl - when the NSP bit is set. */ - __IOM uint32_t SRAM4; /*!< Control whether debugger, DMA, core 0 and core 1 can access - SRAM4, and at what security/privilege levels they can do - so. Defaults to fully open access. This register is writable - only from a Secure, Privileged processor or debugger, with - the exception of the NSU bit, which becomes Non-secure-Privileged-writabl - when the NSP bit is set. */ - __IOM uint32_t SRAM5; /*!< Control whether debugger, DMA, core 0 and core 1 can access - SRAM5, and at what security/privilege levels they can do - so. Defaults to fully open access. This register is writable - only from a Secure, Privileged processor or debugger, with - the exception of the NSU bit, which becomes Non-secure-Privileged-writabl - when the NSP bit is set. */ - __IOM uint32_t SRAM6; /*!< Control whether debugger, DMA, core 0 and core 1 can access - SRAM6, and at what security/privilege levels they can do - so. Defaults to fully open access. This register is writable - only from a Secure, Privileged processor or debugger, with - the exception of the NSU bit, which becomes Non-secure-Privileged-writabl - when the NSP bit is set. */ - __IOM uint32_t SRAM7; /*!< Control whether debugger, DMA, core 0 and core 1 can access - SRAM7, and at what security/privilege levels they can do - so. Defaults to fully open access. This register is writable - only from a Secure, Privileged processor or debugger, with - the exception of the NSU bit, which becomes Non-secure-Privileged-writabl - when the NSP bit is set. */ - __IOM uint32_t SRAM8; /*!< Control whether debugger, DMA, core 0 and core 1 can access - SRAM8, and at what security/privilege levels they can do - so. Defaults to fully open access. This register is writable - only from a Secure, Privileged processor or debugger, with - the exception of the NSU bit, which becomes Non-secure-Privileged-writabl - when the NSP bit is set. */ - __IOM uint32_t SRAM9; /*!< Control whether debugger, DMA, core 0 and core 1 can access - SRAM9, and at what security/privilege levels they can do - so. Defaults to fully open access. This register is writable - only from a Secure, Privileged processor or debugger, with - the exception of the NSU bit, which becomes Non-secure-Privileged-writabl - when the NSP bit is set. */ - __IOM uint32_t DMA; /*!< Control whether debugger, DMA, core 0 and core 1 can access - DMA, and at what security/privilege levels they can do - so. Defaults to Secure access from any master. This register - is writable only from a Secure, Privileged processor or - debugger, with the exception of the NSU bit, which becomes - Non-secure-Privileged-writable when the NSP bit is set. */ - __IOM uint32_t USBCTRL; /*!< Control whether debugger, DMA, core 0 and core 1 can access - USBCTRL, and at what security/privilege levels they can - do so. Defaults to Secure access from any master. This - register is writable only from a Secure, Privileged processor - or debugger, with the exception of the NSU bit, which becomes - Non-secure-Privileged-writable when the NSP bit is set. */ - __IOM uint32_t PIO0; /*!< Control whether debugger, DMA, core 0 and core 1 can access - PIO0, and at what security/privilege levels they can do - so. Defaults to Secure access from any master. This register - is writable only from a Secure, Privileged processor or - debugger, with the exception of the NSU bit, which becomes - Non-secure-Privileged-writable when the NSP bit is set. */ - __IOM uint32_t PIO1; /*!< Control whether debugger, DMA, core 0 and core 1 can access - PIO1, and at what security/privilege levels they can do - so. Defaults to Secure access from any master. This register - is writable only from a Secure, Privileged processor or - debugger, with the exception of the NSU bit, which becomes - Non-secure-Privileged-writable when the NSP bit is set. */ - __IOM uint32_t PIO2; /*!< Control whether debugger, DMA, core 0 and core 1 can access - PIO2, and at what security/privilege levels they can do - so. Defaults to Secure access from any master. This register - is writable only from a Secure, Privileged processor or - debugger, with the exception of the NSU bit, which becomes - Non-secure-Privileged-writable when the NSP bit is set. */ - __IOM uint32_t CORESIGHT_TRACE; /*!< Control whether debugger, DMA, core 0 and core 1 can access - CORESIGHT_TRACE, and at what security/privilege levels - they can do so. Defaults to Secure, Privileged processor - or debug access only. This register is writable only from - a Secure, Privileged processor or debugger, with the exception - of the NSU bit, which becomes Non-secure-Privileged-writable - when the NSP bit is set. */ - __IOM uint32_t CORESIGHT_PERIPH; /*!< Control whether debugger, DMA, core 0 and core 1 can access - CORESIGHT_PERIPH, and at what security/privilege levels - they can do so. Defaults to Secure, Privileged processor - or debug access only. This register is writable only from - a Secure, Privileged processor or debugger, with the exception - of the NSU bit, which becomes Non-secure-Privileged-writable - when the NSP bit is set. */ - __IOM uint32_t SYSINFO; /*!< Control whether debugger, DMA, core 0 and core 1 can access - SYSINFO, and at what security/privilege levels they can - do so. Defaults to fully open access. This register is - writable only from a Secure, Privileged processor or debugger, - with the exception of the NSU bit, which becomes Non-secure-Privileged-wr - table when the NSP bit is set. */ - __IOM uint32_t RESETS; /*!< Control whether debugger, DMA, core 0 and core 1 can access - RESETS, and at what security/privilege levels they can - do so. Defaults to Secure access from any master. This - register is writable only from a Secure, Privileged processor - or debugger, with the exception of the NSU bit, which becomes - Non-secure-Privileged-writable when the NSP bit is set. */ - __IOM uint32_t IO_BANK0; /*!< Control whether debugger, DMA, core 0 and core 1 can access - IO_BANK0, and at what security/privilege levels they can - do so. Defaults to Secure access from any master. This - register is writable only from a Secure, Privileged processor - or debugger, with the exception of the NSU bit, which becomes - Non-secure-Privileged-writable when the NSP bit is set. */ - __IOM uint32_t IO_BANK1; /*!< Control whether debugger, DMA, core 0 and core 1 can access - IO_BANK1, and at what security/privilege levels they can - do so. Defaults to Secure access from any master. This - register is writable only from a Secure, Privileged processor - or debugger, with the exception of the NSU bit, which becomes - Non-secure-Privileged-writable when the NSP bit is set. */ - __IOM uint32_t PADS_BANK0; /*!< Control whether debugger, DMA, core 0 and core 1 can access - PADS_BANK0, and at what security/privilege levels they - can do so. Defaults to Secure access from any master. This - register is writable only from a Secure, Privileged processor - or debugger, with the exception of the NSU bit, which becomes - Non-secure-Privileged-writable when the NSP bit is set. */ - __IOM uint32_t PADS_QSPI; /*!< Control whether debugger, DMA, core 0 and core 1 can access - PADS_QSPI, and at what security/privilege levels they can - do so. Defaults to Secure access from any master. This - register is writable only from a Secure, Privileged processor - or debugger, with the exception of the NSU bit, which becomes - Non-secure-Privileged-writable when the NSP bit is set. */ - __IOM uint32_t BUSCTRL; /*!< Control whether debugger, DMA, core 0 and core 1 can access - BUSCTRL, and at what security/privilege levels they can - do so. Defaults to Secure access from any master. This - register is writable only from a Secure, Privileged processor - or debugger, with the exception of the NSU bit, which becomes - Non-secure-Privileged-writable when the NSP bit is set. */ - __IOM uint32_t ADC0; /*!< Control whether debugger, DMA, core 0 and core 1 can access - ADC0, and at what security/privilege levels they can do - so. Defaults to Secure access from any master. This register - is writable only from a Secure, Privileged processor or - debugger, with the exception of the NSU bit, which becomes - Non-secure-Privileged-writable when the NSP bit is set. */ - __IOM uint32_t HSTX; /*!< Control whether debugger, DMA, core 0 and core 1 can access - HSTX, and at what security/privilege levels they can do - so. Defaults to Secure access from any master. This register - is writable only from a Secure, Privileged processor or - debugger, with the exception of the NSU bit, which becomes - Non-secure-Privileged-writable when the NSP bit is set. */ - __IOM uint32_t I2C0; /*!< Control whether debugger, DMA, core 0 and core 1 can access - I2C0, and at what security/privilege levels they can do - so. Defaults to Secure access from any master. This register - is writable only from a Secure, Privileged processor or - debugger, with the exception of the NSU bit, which becomes - Non-secure-Privileged-writable when the NSP bit is set. */ - __IOM uint32_t I2C1; /*!< Control whether debugger, DMA, core 0 and core 1 can access - I2C1, and at what security/privilege levels they can do - so. Defaults to Secure access from any master. This register - is writable only from a Secure, Privileged processor or - debugger, with the exception of the NSU bit, which becomes - Non-secure-Privileged-writable when the NSP bit is set. */ - __IOM uint32_t PWM; /*!< Control whether debugger, DMA, core 0 and core 1 can access - PWM, and at what security/privilege levels they can do - so. Defaults to Secure access from any master. This register - is writable only from a Secure, Privileged processor or - debugger, with the exception of the NSU bit, which becomes - Non-secure-Privileged-writable when the NSP bit is set. */ - __IOM uint32_t SPI0; /*!< Control whether debugger, DMA, core 0 and core 1 can access - SPI0, and at what security/privilege levels they can do - so. Defaults to Secure access from any master. This register - is writable only from a Secure, Privileged processor or - debugger, with the exception of the NSU bit, which becomes - Non-secure-Privileged-writable when the NSP bit is set. */ - __IOM uint32_t SPI1; /*!< Control whether debugger, DMA, core 0 and core 1 can access - SPI1, and at what security/privilege levels they can do - so. Defaults to Secure access from any master. This register - is writable only from a Secure, Privileged processor or - debugger, with the exception of the NSU bit, which becomes - Non-secure-Privileged-writable when the NSP bit is set. */ - __IOM uint32_t TIMER0; /*!< Control whether debugger, DMA, core 0 and core 1 can access - TIMER0, and at what security/privilege levels they can - do so. Defaults to Secure access from any master. This - register is writable only from a Secure, Privileged processor - or debugger, with the exception of the NSU bit, which becomes - Non-secure-Privileged-writable when the NSP bit is set. */ - __IOM uint32_t TIMER1; /*!< Control whether debugger, DMA, core 0 and core 1 can access - TIMER1, and at what security/privilege levels they can - do so. Defaults to Secure access from any master. This - register is writable only from a Secure, Privileged processor - or debugger, with the exception of the NSU bit, which becomes - Non-secure-Privileged-writable when the NSP bit is set. */ - __IOM uint32_t UART0; /*!< Control whether debugger, DMA, core 0 and core 1 can access - UART0, and at what security/privilege levels they can do - so. Defaults to Secure access from any master. This register - is writable only from a Secure, Privileged processor or - debugger, with the exception of the NSU bit, which becomes - Non-secure-Privileged-writable when the NSP bit is set. */ - __IOM uint32_t UART1; /*!< Control whether debugger, DMA, core 0 and core 1 can access - UART1, and at what security/privilege levels they can do - so. Defaults to Secure access from any master. This register - is writable only from a Secure, Privileged processor or - debugger, with the exception of the NSU bit, which becomes - Non-secure-Privileged-writable when the NSP bit is set. */ - __IOM uint32_t OTP; /*!< Control whether debugger, DMA, core 0 and core 1 can access - OTP, and at what security/privilege levels they can do - so. Defaults to Secure access from any master. This register - is writable only from a Secure, Privileged processor or - debugger, with the exception of the NSU bit, which becomes - Non-secure-Privileged-writable when the NSP bit is set. */ - __IOM uint32_t TBMAN; /*!< Control whether debugger, DMA, core 0 and core 1 can access - TBMAN, and at what security/privilege levels they can do - so. Defaults to Secure access from any master. This register - is writable only from a Secure, Privileged processor or - debugger, with the exception of the NSU bit, which becomes - Non-secure-Privileged-writable when the NSP bit is set. */ - __IOM uint32_t POWMAN; /*!< Control whether debugger, DMA, core 0 and core 1 can access - POWMAN, and at what security/privilege levels they can - do so. Defaults to Secure, Privileged processor or debug - access only. This register is writable only from a Secure, - Privileged processor or debugger, with the exception of - the NSU bit, which becomes Non-secure-Privileged-writable - when the NSP bit is set. */ - __IOM uint32_t TRNG; /*!< Control whether debugger, DMA, core 0 and core 1 can access - TRNG, and at what security/privilege levels they can do - so. Defaults to Secure, Privileged processor or debug access - only. This register is writable only from a Secure, Privileged - processor or debugger, with the exception of the NSU bit, - which becomes Non-secure-Privileged-writable when the NSP - bit is set. */ - __IOM uint32_t SHA256; /*!< Control whether debugger, DMA, core 0 and core 1 can access - SHA256, and at what security/privilege levels they can - do so. Defaults to Secure, Privileged access only. This - register is writable only from a Secure, Privileged processor - or debugger, with the exception of the NSU bit, which becomes - Non-secure-Privileged-writable when the NSP bit is set. */ - __IOM uint32_t SYSCFG; /*!< Control whether debugger, DMA, core 0 and core 1 can access - SYSCFG, and at what security/privilege levels they can - do so. Defaults to Secure, Privileged processor or debug - access only. This register is writable only from a Secure, - Privileged processor or debugger, with the exception of - the NSU bit, which becomes Non-secure-Privileged-writable - when the NSP bit is set. */ - __IOM uint32_t CLOCKS; /*!< Control whether debugger, DMA, core 0 and core 1 can access - CLOCKS, and at what security/privilege levels they can - do so. Defaults to Secure, Privileged processor or debug - access only. This register is writable only from a Secure, - Privileged processor or debugger, with the exception of - the NSU bit, which becomes Non-secure-Privileged-writable - when the NSP bit is set. */ - __IOM uint32_t XOSC; /*!< Control whether debugger, DMA, core 0 and core 1 can access - XOSC, and at what security/privilege levels they can do - so. Defaults to Secure, Privileged processor or debug access - only. This register is writable only from a Secure, Privileged - processor or debugger, with the exception of the NSU bit, - which becomes Non-secure-Privileged-writable when the NSP - bit is set. */ - __IOM uint32_t ROSC; /*!< Control whether debugger, DMA, core 0 and core 1 can access - ROSC, and at what security/privilege levels they can do - so. Defaults to Secure, Privileged processor or debug access - only. This register is writable only from a Secure, Privileged - processor or debugger, with the exception of the NSU bit, - which becomes Non-secure-Privileged-writable when the NSP - bit is set. */ - __IOM uint32_t PLL_SYS; /*!< Control whether debugger, DMA, core 0 and core 1 can access - PLL_SYS, and at what security/privilege levels they can - do so. Defaults to Secure, Privileged processor or debug - access only. This register is writable only from a Secure, - Privileged processor or debugger, with the exception of - the NSU bit, which becomes Non-secure-Privileged-writable - when the NSP bit is set. */ - __IOM uint32_t PLL_USB; /*!< Control whether debugger, DMA, core 0 and core 1 can access - PLL_USB, and at what security/privilege levels they can - do so. Defaults to Secure, Privileged processor or debug - access only. This register is writable only from a Secure, - Privileged processor or debugger, with the exception of - the NSU bit, which becomes Non-secure-Privileged-writable - when the NSP bit is set. */ - __IOM uint32_t TICKS; /*!< Control whether debugger, DMA, core 0 and core 1 can access - TICKS, and at what security/privilege levels they can do - so. Defaults to Secure, Privileged processor or debug access - only. This register is writable only from a Secure, Privileged - processor or debugger, with the exception of the NSU bit, - which becomes Non-secure-Privileged-writable when the NSP - bit is set. */ - __IOM uint32_t WATCHDOG; /*!< Control whether debugger, DMA, core 0 and core 1 can access - WATCHDOG, and at what security/privilege levels they can - do so. Defaults to Secure, Privileged processor or debug - access only. This register is writable only from a Secure, - Privileged processor or debugger, with the exception of - the NSU bit, which becomes Non-secure-Privileged-writable - when the NSP bit is set. */ - __IOM uint32_t RSM; /*!< Control whether debugger, DMA, core 0 and core 1 can access - RSM, and at what security/privilege levels they can do - so. Defaults to Secure, Privileged processor or debug access - only. This register is writable only from a Secure, Privileged - processor or debugger, with the exception of the NSU bit, - which becomes Non-secure-Privileged-writable when the NSP - bit is set. */ - __IOM uint32_t XIP_CTRL; /*!< Control whether debugger, DMA, core 0 and core 1 can access - XIP_CTRL, and at what security/privilege levels they can - do so. Defaults to Secure, Privileged processor or debug - access only. This register is writable only from a Secure, - Privileged processor or debugger, with the exception of - the NSU bit, which becomes Non-secure-Privileged-writable - when the NSP bit is set. */ - __IOM uint32_t XIP_QMI; /*!< Control whether debugger, DMA, core 0 and core 1 can access - XIP_QMI, and at what security/privilege levels they can - do so. Defaults to Secure, Privileged processor or debug - access only. This register is writable only from a Secure, - Privileged processor or debugger, with the exception of - the NSU bit, which becomes Non-secure-Privileged-writable - when the NSP bit is set. */ - __IOM uint32_t XIP_AUX; /*!< Control whether debugger, DMA, core 0 and core 1 can access - XIP_AUX, and at what security/privilege levels they can - do so. Defaults to Secure, Privileged access only. This - register is writable only from a Secure, Privileged processor - or debugger, with the exception of the NSU bit, which becomes - Non-secure-Privileged-writable when the NSP bit is set. */ -} ACCESSCTRL_Type; /*!< Size = 236 (0xec) */ - - - -/* =========================================================================================================================== */ -/* ================ UART0 ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief UART0 (UART0) - */ - -typedef struct { /*!< UART0 Structure */ - __IOM uint32_t UARTDR; /*!< Data Register, UARTDR */ - __IOM uint32_t UARTRSR; /*!< Receive Status Register/Error Clear Register, UARTRSR/UARTECR */ - __IM uint32_t RESERVED[4]; - __IOM uint32_t UARTFR; /*!< Flag Register, UARTFR */ - __IM uint32_t RESERVED1; - __IOM uint32_t UARTILPR; /*!< IrDA Low-Power Counter Register, UARTILPR */ - __IOM uint32_t UARTIBRD; /*!< Integer Baud Rate Register, UARTIBRD */ - __IOM uint32_t UARTFBRD; /*!< Fractional Baud Rate Register, UARTFBRD */ - __IOM uint32_t UARTLCR_H; /*!< Line Control Register, UARTLCR_H */ - __IOM uint32_t UARTCR; /*!< Control Register, UARTCR */ - __IOM uint32_t UARTIFLS; /*!< Interrupt FIFO Level Select Register, UARTIFLS */ - __IOM uint32_t UARTIMSC; /*!< Interrupt Mask Set/Clear Register, UARTIMSC */ - __IOM uint32_t UARTRIS; /*!< Raw Interrupt Status Register, UARTRIS */ - __IOM uint32_t UARTMIS; /*!< Masked Interrupt Status Register, UARTMIS */ - __IOM uint32_t UARTICR; /*!< Interrupt Clear Register, UARTICR */ - __IOM uint32_t UARTDMACR; /*!< DMA Control Register, UARTDMACR */ - __IM uint32_t RESERVED2[997]; - __IOM uint32_t UARTPERIPHID0; /*!< UARTPeriphID0 Register */ - __IOM uint32_t UARTPERIPHID1; /*!< UARTPeriphID1 Register */ - __IOM uint32_t UARTPERIPHID2; /*!< UARTPeriphID2 Register */ - __IOM uint32_t UARTPERIPHID3; /*!< UARTPeriphID3 Register */ - __IOM uint32_t UARTPCELLID0; /*!< UARTPCellID0 Register */ - __IOM uint32_t UARTPCELLID1; /*!< UARTPCellID1 Register */ - __IOM uint32_t UARTPCELLID2; /*!< UARTPCellID2 Register */ - __IOM uint32_t UARTPCELLID3; /*!< UARTPCellID3 Register */ -} UART0_Type; /*!< Size = 4096 (0x1000) */ - - - -/* =========================================================================================================================== */ -/* ================ ROSC ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief ROSC (ROSC) - */ - -typedef struct { /*!< ROSC Structure */ - __IOM uint32_t CTRL; /*!< Ring Oscillator control */ - __IOM uint32_t FREQA; /*!< The FREQA & FREQB registers control the frequency by controlling - the drive strength of each stage The drive strength has - 4 levels determined by the number of bits set Increasing - the number of bits set increases the drive strength and - increases the oscillation frequency 0 bits set is the default - drive strength 1 bit set doubles the drive strength 2 bits - set triples drive strength 3 bits set quadruples drive - strength For frequency randomisation set both DS0_RANDOM=1 - & DS1_RANDOM=1 */ - __IOM uint32_t FREQB; /*!< For a detailed description see freqa register */ - __IOM uint32_t RANDOM; /*!< Loads a value to the LFSR randomiser */ - __IOM uint32_t DORMANT; /*!< Ring Oscillator pause control */ - __IOM uint32_t DIV; /*!< Controls the output divider */ - __IOM uint32_t PHASE; /*!< Controls the phase shifted output */ - __IOM uint32_t STATUS; /*!< Ring Oscillator Status */ - __IOM uint32_t RANDOMBIT; /*!< This just reads the state of the oscillator output so randomness - is compromised if the ring oscillator is stopped or run - at a harmonic of the bus frequency */ - __IOM uint32_t COUNT; /*!< A down counter running at the ROSC frequency which counts to - zero and stops. To start the counter write a non-zero value. - Can be used for short software pauses when setting up time - sensitive hardware. */ -} ROSC_Type; /*!< Size = 40 (0x28) */ - - - -/* =========================================================================================================================== */ -/* ================ POWMAN ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief Controls vreg, bor, lposc, chip resets & xosc startup, powman and provides scratch register for general use and for bootcode use (POWMAN) - */ - -typedef struct { /*!< POWMAN Structure */ - __IOM uint32_t BADPASSWD; /*!< Indicates a bad password has been used */ - __IOM uint32_t VREG_CTRL; /*!< Voltage Regulator Control */ - __IOM uint32_t VREG_STS; /*!< Voltage Regulator Status */ - __IOM uint32_t VREG; /*!< Voltage Regulator Settings */ - __IOM uint32_t VREG_LP_ENTRY; /*!< Voltage Regulator Low Power Entry Settings */ - __IOM uint32_t VREG_LP_EXIT; /*!< Voltage Regulator Low Power Exit Settings */ - __IOM uint32_t BOD_CTRL; /*!< Brown-out Detection Control */ - __IOM uint32_t BOD; /*!< Brown-out Detection Settings */ - __IOM uint32_t BOD_LP_ENTRY; /*!< Brown-out Detection Low Power Entry Settings */ - __IOM uint32_t BOD_LP_EXIT; /*!< Brown-out Detection Low Power Exit Settings */ - __IOM uint32_t LPOSC; /*!< Low power oscillator control register. */ - __IOM uint32_t CHIP_RESET; /*!< Chip reset control and status */ - __IOM uint32_t WDSEL; /*!< Allows a watchdog reset to reset the internal state of powman - in addition to the power-on state machine (PSM). Note that - powman ignores watchdog resets that do not select at least - the CLOCKS stage or earlier stages in the PSM. If using - these bits, it's recommended to set PSM_WDSEL to all-ones - in addition to the desired bits in this register. Failing - to select CLOCKS or earlier will result in the POWMAN_WDSEL - register having no effect. */ - __IOM uint32_t SEQ_CFG; /*!< For configuration of the power sequencer Writes are ignored - while POWMAN_STATE_CHANGING=1 */ - __IOM uint32_t STATE; /*!< This register controls the power state of the 4 power domains. - The current power state is indicated in POWMAN_STATE_CURRENT - which is read-only. To change the state, write to POWMAN_STATE_REQ. - The coding of POWMAN_STATE_CURRENT & POWMAN_STATE_REQ corresponds - to the power states defined in the datasheet: bit 3 = SWCORE - bit 2 = XIP cache bit 1 = SRAM0 bit 0 = SRAM1 0 = powered - up 1 = powered down When POWMAN_STATE_REQ is written, the - POWMAN_STATE_WAITING flag is set while the Power Manager - determines what is required. If an invalid transition is - requested the Power Manager will still register the request - in POWMAN_STATE_REQ but will also set the POWMAN_BAD_REQ - flag. It will then implement the power-up requests and - ignore the power down requests. To do nothing would risk - entering an unrecoverable lock-up state. Invalid requests - are: any combination of power up and power down requests - any request that results in swcore boing powered and xip - unpowered If the request is to power down the switched-core - domain then POWMAN_STATE_WAITING stays active until the - processors halt. During this time the POWMAN_STATE_REQ - field can be re-written to change or cancel the request. - When the power state transition begins the POWMAN_STATE_WAITING_flag - is cleared, the POWMAN_STATE_CHANGING flag is set and POWMAN - register writes are ignored until the transition completes. */ - __IOM uint32_t POW_FASTDIV; /*!< POW_FASTDIV */ - __IOM uint32_t POW_DELAY; /*!< power state machine delays */ - __IOM uint32_t EXT_CTRL0; /*!< Configures a gpio as a power mode aware control output */ - __IOM uint32_t EXT_CTRL1; /*!< Configures a gpio as a power mode aware control output */ - __IOM uint32_t EXT_TIME_REF; /*!< Select a GPIO to use as a time reference, the source can be - used to drive the low power clock at 32kHz, or to provide - a 1ms tick to the timer, or provide a 1Hz tick to the timer. - The tick selection is controlled by the POWMAN_TIMER register. */ - __IOM uint32_t LPOSC_FREQ_KHZ_INT; /*!< Informs the AON Timer of the integer component of the clock - frequency when running off the LPOSC. */ - __IOM uint32_t LPOSC_FREQ_KHZ_FRAC; /*!< Informs the AON Timer of the fractional component of the clock - frequency when running off the LPOSC. */ - __IOM uint32_t XOSC_FREQ_KHZ_INT; /*!< Informs the AON Timer of the integer component of the clock - frequency when running off the XOSC. */ - __IOM uint32_t XOSC_FREQ_KHZ_FRAC; /*!< Informs the AON Timer of the fractional component of the clock - frequency when running off the XOSC. */ - __IOM uint32_t SET_TIME_63TO48; /*!< SET_TIME_63TO48 */ - __IOM uint32_t SET_TIME_47TO32; /*!< SET_TIME_47TO32 */ - __IOM uint32_t SET_TIME_31TO16; /*!< SET_TIME_31TO16 */ - __IOM uint32_t SET_TIME_15TO0; /*!< SET_TIME_15TO0 */ - __IOM uint32_t READ_TIME_UPPER; /*!< READ_TIME_UPPER */ - __IOM uint32_t READ_TIME_LOWER; /*!< READ_TIME_LOWER */ - __IOM uint32_t ALARM_TIME_63TO48; /*!< ALARM_TIME_63TO48 */ - __IOM uint32_t ALARM_TIME_47TO32; /*!< ALARM_TIME_47TO32 */ - __IOM uint32_t ALARM_TIME_31TO16; /*!< ALARM_TIME_31TO16 */ - __IOM uint32_t ALARM_TIME_15TO0; /*!< ALARM_TIME_15TO0 */ - __IOM uint32_t TIMER; /*!< TIMER */ - __IOM uint32_t PWRUP0; /*!< 4 GPIO powerup events can be configured to wake the chip up - from a low power state. The pwrups are level/edge sensitive - and can be set to trigger on a high/rising or low/falling - event The number of gpios available depends on the package - option. An invalid selection will be ignored source = 0 - selects gpio0 . . source = 47 selects gpio47 source = 48 - selects qspi_ss source = 49 selects qspi_sd0 source = 50 - selects qspi_sd1 source = 51 selects qspi_sd2 source = - 52 selects qspi_sd3 source = 53 selects qspi_sclk level - = 0 triggers the pwrup when the source is low level = 1 - triggers the pwrup when the source is high */ - __IOM uint32_t PWRUP1; /*!< 4 GPIO powerup events can be configured to wake the chip up - from a low power state. The pwrups are level/edge sensitive - and can be set to trigger on a high/rising or low/falling - event The number of gpios available depends on the package - option. An invalid selection will be ignored source = 0 - selects gpio0 . . source = 47 selects gpio47 source = 48 - selects qspi_ss source = 49 selects qspi_sd0 source = 50 - selects qspi_sd1 source = 51 selects qspi_sd2 source = - 52 selects qspi_sd3 source = 53 selects qspi_sclk level - = 0 triggers the pwrup when the source is low level = 1 - triggers the pwrup when the source is high */ - __IOM uint32_t PWRUP2; /*!< 4 GPIO powerup events can be configured to wake the chip up - from a low power state. The pwrups are level/edge sensitive - and can be set to trigger on a high/rising or low/falling - event The number of gpios available depends on the package - option. An invalid selection will be ignored source = 0 - selects gpio0 . . source = 47 selects gpio47 source = 48 - selects qspi_ss source = 49 selects qspi_sd0 source = 50 - selects qspi_sd1 source = 51 selects qspi_sd2 source = - 52 selects qspi_sd3 source = 53 selects qspi_sclk level - = 0 triggers the pwrup when the source is low level = 1 - triggers the pwrup when the source is high */ - __IOM uint32_t PWRUP3; /*!< 4 GPIO powerup events can be configured to wake the chip up - from a low power state. The pwrups are level/edge sensitive - and can be set to trigger on a high/rising or low/falling - event The number of gpios available depends on the package - option. An invalid selection will be ignored source = 0 - selects gpio0 . . source = 47 selects gpio47 source = 48 - selects qspi_ss source = 49 selects qspi_sd0 source = 50 - selects qspi_sd1 source = 51 selects qspi_sd2 source = - 52 selects qspi_sd3 source = 53 selects qspi_sclk level - = 0 triggers the pwrup when the source is low level = 1 - triggers the pwrup when the source is high */ - __IOM uint32_t CURRENT_PWRUP_REQ; /*!< Indicates current powerup request state pwrup events can be - cleared by removing the enable from the pwrup register. - The alarm pwrup req can be cleared by clearing timer.alarm_enab - 0 = chip reset, for the source of the last reset see POWMAN_CHIP_RESET - 1 = pwrup0 2 = pwrup1 3 = pwrup2 4 = pwrup3 5 = coresight_pwrup - 6 = alarm_pwrup */ - __IOM uint32_t LAST_SWCORE_PWRUP; /*!< Indicates which pwrup source triggered the last switched-core - power up 0 = chip reset, for the source of the last reset - see POWMAN_CHIP_RESET 1 = pwrup0 2 = pwrup1 3 = pwrup2 - 4 = pwrup3 5 = coresight_pwrup 6 = alarm_pwrup */ - __IOM uint32_t DBG_PWRCFG; /*!< DBG_PWRCFG */ - __IOM uint32_t BOOTDIS; /*!< Tell the bootrom to ignore the BOOT0..3 registers following - the next RSM reset (e.g. the next core power down/up). - If an early boot stage has soft-locked some OTP pages in - order to protect their contents from later stages, there - is a risk that Secure code running at a later stage can - unlock the pages by powering the core up and down. This - register can be used to ensure that the bootloader runs - as normal on the next power up, preventing Secure code - at a later stage from accessing OTP in its unlocked state. - Should be used in conjunction with the OTP BOOTDIS register. */ - __IOM uint32_t DBGCONFIG; /*!< DBGCONFIG */ - __IOM uint32_t SCRATCH0; /*!< Scratch register. Information persists in low power mode */ - __IOM uint32_t SCRATCH1; /*!< Scratch register. Information persists in low power mode */ - __IOM uint32_t SCRATCH2; /*!< Scratch register. Information persists in low power mode */ - __IOM uint32_t SCRATCH3; /*!< Scratch register. Information persists in low power mode */ - __IOM uint32_t SCRATCH4; /*!< Scratch register. Information persists in low power mode */ - __IOM uint32_t SCRATCH5; /*!< Scratch register. Information persists in low power mode */ - __IOM uint32_t SCRATCH6; /*!< Scratch register. Information persists in low power mode */ - __IOM uint32_t SCRATCH7; /*!< Scratch register. Information persists in low power mode */ - __IOM uint32_t BOOT0; /*!< Scratch register. Information persists in low power mode */ - __IOM uint32_t BOOT1; /*!< Scratch register. Information persists in low power mode */ - __IOM uint32_t BOOT2; /*!< Scratch register. Information persists in low power mode */ - __IOM uint32_t BOOT3; /*!< Scratch register. Information persists in low power mode */ - __IOM uint32_t INTR; /*!< Raw Interrupts */ - __IOM uint32_t INTE; /*!< Interrupt Enable */ - __IOM uint32_t INTF; /*!< Interrupt Force */ - __IOM uint32_t INTS; /*!< Interrupt status after masking & forcing */ -} POWMAN_Type; /*!< Size = 240 (0xf0) */ - - - -/* =========================================================================================================================== */ -/* ================ WATCHDOG ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief WATCHDOG (WATCHDOG) - */ - -typedef struct { /*!< WATCHDOG Structure */ - __IOM uint32_t CTRL; /*!< Watchdog control The rst_wdsel register determines which subsystems - are reset when the watchdog is triggered. The watchdog - can be triggered in software. */ - __IOM uint32_t LOAD; /*!< Load the watchdog timer. The maximum setting is 0xffffff which - corresponds to approximately 16 seconds. */ - __IOM uint32_t REASON; /*!< Logs the reason for the last reset. Both bits are zero for the - case of a hardware reset. Additionally, as of RP2350, a - debugger warm reset of either core (SYSRESETREQ or hartreset) - will also clear the watchdog reason register, so that software - loaded under the debugger following a watchdog timeout - will not continue to see the timeout condition. */ - __IOM uint32_t SCRATCH0; /*!< Scratch register. Information persists through soft reset of - the chip. */ - __IOM uint32_t SCRATCH1; /*!< Scratch register. Information persists through soft reset of - the chip. */ - __IOM uint32_t SCRATCH2; /*!< Scratch register. Information persists through soft reset of - the chip. */ - __IOM uint32_t SCRATCH3; /*!< Scratch register. Information persists through soft reset of - the chip. */ - __IOM uint32_t SCRATCH4; /*!< Scratch register. Information persists through soft reset of - the chip. */ - __IOM uint32_t SCRATCH5; /*!< Scratch register. Information persists through soft reset of - the chip. */ - __IOM uint32_t SCRATCH6; /*!< Scratch register. Information persists through soft reset of - the chip. */ - __IOM uint32_t SCRATCH7; /*!< Scratch register. Information persists through soft reset of - the chip. */ -} WATCHDOG_Type; /*!< Size = 44 (0x2c) */ - - - -/* =========================================================================================================================== */ -/* ================ DMA ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief DMA with separate read and write masters (DMA) - */ - -typedef struct { /*!< DMA Structure */ - __IOM uint32_t CH0_READ_ADDR; /*!< DMA Channel 0 Read Address pointer */ - __IOM uint32_t CH0_WRITE_ADDR; /*!< DMA Channel 0 Write Address pointer */ - __IOM uint32_t CH0_TRANS_COUNT; /*!< DMA Channel 0 Transfer Count */ - __IOM uint32_t CH0_CTRL_TRIG; /*!< DMA Channel 0 Control and Status */ - __IOM uint32_t CH0_AL1_CTRL; /*!< Alias for channel 0 CTRL register */ - __IOM uint32_t CH0_AL1_READ_ADDR; /*!< Alias for channel 0 READ_ADDR register */ - __IOM uint32_t CH0_AL1_WRITE_ADDR; /*!< Alias for channel 0 WRITE_ADDR register */ - __IOM uint32_t CH0_AL1_TRANS_COUNT_TRIG; /*!< Alias for channel 0 TRANS_COUNT register This is a trigger register - (0xc). Writing a nonzero value will reload the channel - counter and start the channel. */ - __IOM uint32_t CH0_AL2_CTRL; /*!< Alias for channel 0 CTRL register */ - __IOM uint32_t CH0_AL2_TRANS_COUNT; /*!< Alias for channel 0 TRANS_COUNT register */ - __IOM uint32_t CH0_AL2_READ_ADDR; /*!< Alias for channel 0 READ_ADDR register */ - __IOM uint32_t CH0_AL2_WRITE_ADDR_TRIG; /*!< Alias for channel 0 WRITE_ADDR register This is a trigger register - (0xc). Writing a nonzero value will reload the channel - counter and start the channel. */ - __IOM uint32_t CH0_AL3_CTRL; /*!< Alias for channel 0 CTRL register */ - __IOM uint32_t CH0_AL3_WRITE_ADDR; /*!< Alias for channel 0 WRITE_ADDR register */ - __IOM uint32_t CH0_AL3_TRANS_COUNT; /*!< Alias for channel 0 TRANS_COUNT register */ - __IOM uint32_t CH0_AL3_READ_ADDR_TRIG; /*!< Alias for channel 0 READ_ADDR register This is a trigger register - (0xc). Writing a nonzero value will reload the channel - counter and start the channel. */ - __IOM uint32_t CH1_READ_ADDR; /*!< DMA Channel 1 Read Address pointer */ - __IOM uint32_t CH1_WRITE_ADDR; /*!< DMA Channel 1 Write Address pointer */ - __IOM uint32_t CH1_TRANS_COUNT; /*!< DMA Channel 1 Transfer Count */ - __IOM uint32_t CH1_CTRL_TRIG; /*!< DMA Channel 1 Control and Status */ - __IOM uint32_t CH1_AL1_CTRL; /*!< Alias for channel 1 CTRL register */ - __IOM uint32_t CH1_AL1_READ_ADDR; /*!< Alias for channel 1 READ_ADDR register */ - __IOM uint32_t CH1_AL1_WRITE_ADDR; /*!< Alias for channel 1 WRITE_ADDR register */ - __IOM uint32_t CH1_AL1_TRANS_COUNT_TRIG; /*!< Alias for channel 1 TRANS_COUNT register This is a trigger register - (0xc). Writing a nonzero value will reload the channel - counter and start the channel. */ - __IOM uint32_t CH1_AL2_CTRL; /*!< Alias for channel 1 CTRL register */ - __IOM uint32_t CH1_AL2_TRANS_COUNT; /*!< Alias for channel 1 TRANS_COUNT register */ - __IOM uint32_t CH1_AL2_READ_ADDR; /*!< Alias for channel 1 READ_ADDR register */ - __IOM uint32_t CH1_AL2_WRITE_ADDR_TRIG; /*!< Alias for channel 1 WRITE_ADDR register This is a trigger register - (0xc). Writing a nonzero value will reload the channel - counter and start the channel. */ - __IOM uint32_t CH1_AL3_CTRL; /*!< Alias for channel 1 CTRL register */ - __IOM uint32_t CH1_AL3_WRITE_ADDR; /*!< Alias for channel 1 WRITE_ADDR register */ - __IOM uint32_t CH1_AL3_TRANS_COUNT; /*!< Alias for channel 1 TRANS_COUNT register */ - __IOM uint32_t CH1_AL3_READ_ADDR_TRIG; /*!< Alias for channel 1 READ_ADDR register This is a trigger register - (0xc). Writing a nonzero value will reload the channel - counter and start the channel. */ - __IOM uint32_t CH2_READ_ADDR; /*!< DMA Channel 2 Read Address pointer */ - __IOM uint32_t CH2_WRITE_ADDR; /*!< DMA Channel 2 Write Address pointer */ - __IOM uint32_t CH2_TRANS_COUNT; /*!< DMA Channel 2 Transfer Count */ - __IOM uint32_t CH2_CTRL_TRIG; /*!< DMA Channel 2 Control and Status */ - __IOM uint32_t CH2_AL1_CTRL; /*!< Alias for channel 2 CTRL register */ - __IOM uint32_t CH2_AL1_READ_ADDR; /*!< Alias for channel 2 READ_ADDR register */ - __IOM uint32_t CH2_AL1_WRITE_ADDR; /*!< Alias for channel 2 WRITE_ADDR register */ - __IOM uint32_t CH2_AL1_TRANS_COUNT_TRIG; /*!< Alias for channel 2 TRANS_COUNT register This is a trigger register - (0xc). Writing a nonzero value will reload the channel - counter and start the channel. */ - __IOM uint32_t CH2_AL2_CTRL; /*!< Alias for channel 2 CTRL register */ - __IOM uint32_t CH2_AL2_TRANS_COUNT; /*!< Alias for channel 2 TRANS_COUNT register */ - __IOM uint32_t CH2_AL2_READ_ADDR; /*!< Alias for channel 2 READ_ADDR register */ - __IOM uint32_t CH2_AL2_WRITE_ADDR_TRIG; /*!< Alias for channel 2 WRITE_ADDR register This is a trigger register - (0xc). Writing a nonzero value will reload the channel - counter and start the channel. */ - __IOM uint32_t CH2_AL3_CTRL; /*!< Alias for channel 2 CTRL register */ - __IOM uint32_t CH2_AL3_WRITE_ADDR; /*!< Alias for channel 2 WRITE_ADDR register */ - __IOM uint32_t CH2_AL3_TRANS_COUNT; /*!< Alias for channel 2 TRANS_COUNT register */ - __IOM uint32_t CH2_AL3_READ_ADDR_TRIG; /*!< Alias for channel 2 READ_ADDR register This is a trigger register - (0xc). Writing a nonzero value will reload the channel - counter and start the channel. */ - __IOM uint32_t CH3_READ_ADDR; /*!< DMA Channel 3 Read Address pointer */ - __IOM uint32_t CH3_WRITE_ADDR; /*!< DMA Channel 3 Write Address pointer */ - __IOM uint32_t CH3_TRANS_COUNT; /*!< DMA Channel 3 Transfer Count */ - __IOM uint32_t CH3_CTRL_TRIG; /*!< DMA Channel 3 Control and Status */ - __IOM uint32_t CH3_AL1_CTRL; /*!< Alias for channel 3 CTRL register */ - __IOM uint32_t CH3_AL1_READ_ADDR; /*!< Alias for channel 3 READ_ADDR register */ - __IOM uint32_t CH3_AL1_WRITE_ADDR; /*!< Alias for channel 3 WRITE_ADDR register */ - __IOM uint32_t CH3_AL1_TRANS_COUNT_TRIG; /*!< Alias for channel 3 TRANS_COUNT register This is a trigger register - (0xc). Writing a nonzero value will reload the channel - counter and start the channel. */ - __IOM uint32_t CH3_AL2_CTRL; /*!< Alias for channel 3 CTRL register */ - __IOM uint32_t CH3_AL2_TRANS_COUNT; /*!< Alias for channel 3 TRANS_COUNT register */ - __IOM uint32_t CH3_AL2_READ_ADDR; /*!< Alias for channel 3 READ_ADDR register */ - __IOM uint32_t CH3_AL2_WRITE_ADDR_TRIG; /*!< Alias for channel 3 WRITE_ADDR register This is a trigger register - (0xc). Writing a nonzero value will reload the channel - counter and start the channel. */ - __IOM uint32_t CH3_AL3_CTRL; /*!< Alias for channel 3 CTRL register */ - __IOM uint32_t CH3_AL3_WRITE_ADDR; /*!< Alias for channel 3 WRITE_ADDR register */ - __IOM uint32_t CH3_AL3_TRANS_COUNT; /*!< Alias for channel 3 TRANS_COUNT register */ - __IOM uint32_t CH3_AL3_READ_ADDR_TRIG; /*!< Alias for channel 3 READ_ADDR register This is a trigger register - (0xc). Writing a nonzero value will reload the channel - counter and start the channel. */ - __IOM uint32_t CH4_READ_ADDR; /*!< DMA Channel 4 Read Address pointer */ - __IOM uint32_t CH4_WRITE_ADDR; /*!< DMA Channel 4 Write Address pointer */ - __IOM uint32_t CH4_TRANS_COUNT; /*!< DMA Channel 4 Transfer Count */ - __IOM uint32_t CH4_CTRL_TRIG; /*!< DMA Channel 4 Control and Status */ - __IOM uint32_t CH4_AL1_CTRL; /*!< Alias for channel 4 CTRL register */ - __IOM uint32_t CH4_AL1_READ_ADDR; /*!< Alias for channel 4 READ_ADDR register */ - __IOM uint32_t CH4_AL1_WRITE_ADDR; /*!< Alias for channel 4 WRITE_ADDR register */ - __IOM uint32_t CH4_AL1_TRANS_COUNT_TRIG; /*!< Alias for channel 4 TRANS_COUNT register This is a trigger register - (0xc). Writing a nonzero value will reload the channel - counter and start the channel. */ - __IOM uint32_t CH4_AL2_CTRL; /*!< Alias for channel 4 CTRL register */ - __IOM uint32_t CH4_AL2_TRANS_COUNT; /*!< Alias for channel 4 TRANS_COUNT register */ - __IOM uint32_t CH4_AL2_READ_ADDR; /*!< Alias for channel 4 READ_ADDR register */ - __IOM uint32_t CH4_AL2_WRITE_ADDR_TRIG; /*!< Alias for channel 4 WRITE_ADDR register This is a trigger register - (0xc). Writing a nonzero value will reload the channel - counter and start the channel. */ - __IOM uint32_t CH4_AL3_CTRL; /*!< Alias for channel 4 CTRL register */ - __IOM uint32_t CH4_AL3_WRITE_ADDR; /*!< Alias for channel 4 WRITE_ADDR register */ - __IOM uint32_t CH4_AL3_TRANS_COUNT; /*!< Alias for channel 4 TRANS_COUNT register */ - __IOM uint32_t CH4_AL3_READ_ADDR_TRIG; /*!< Alias for channel 4 READ_ADDR register This is a trigger register - (0xc). Writing a nonzero value will reload the channel - counter and start the channel. */ - __IOM uint32_t CH5_READ_ADDR; /*!< DMA Channel 5 Read Address pointer */ - __IOM uint32_t CH5_WRITE_ADDR; /*!< DMA Channel 5 Write Address pointer */ - __IOM uint32_t CH5_TRANS_COUNT; /*!< DMA Channel 5 Transfer Count */ - __IOM uint32_t CH5_CTRL_TRIG; /*!< DMA Channel 5 Control and Status */ - __IOM uint32_t CH5_AL1_CTRL; /*!< Alias for channel 5 CTRL register */ - __IOM uint32_t CH5_AL1_READ_ADDR; /*!< Alias for channel 5 READ_ADDR register */ - __IOM uint32_t CH5_AL1_WRITE_ADDR; /*!< Alias for channel 5 WRITE_ADDR register */ - __IOM uint32_t CH5_AL1_TRANS_COUNT_TRIG; /*!< Alias for channel 5 TRANS_COUNT register This is a trigger register - (0xc). Writing a nonzero value will reload the channel - counter and start the channel. */ - __IOM uint32_t CH5_AL2_CTRL; /*!< Alias for channel 5 CTRL register */ - __IOM uint32_t CH5_AL2_TRANS_COUNT; /*!< Alias for channel 5 TRANS_COUNT register */ - __IOM uint32_t CH5_AL2_READ_ADDR; /*!< Alias for channel 5 READ_ADDR register */ - __IOM uint32_t CH5_AL2_WRITE_ADDR_TRIG; /*!< Alias for channel 5 WRITE_ADDR register This is a trigger register - (0xc). Writing a nonzero value will reload the channel - counter and start the channel. */ - __IOM uint32_t CH5_AL3_CTRL; /*!< Alias for channel 5 CTRL register */ - __IOM uint32_t CH5_AL3_WRITE_ADDR; /*!< Alias for channel 5 WRITE_ADDR register */ - __IOM uint32_t CH5_AL3_TRANS_COUNT; /*!< Alias for channel 5 TRANS_COUNT register */ - __IOM uint32_t CH5_AL3_READ_ADDR_TRIG; /*!< Alias for channel 5 READ_ADDR register This is a trigger register - (0xc). Writing a nonzero value will reload the channel - counter and start the channel. */ - __IOM uint32_t CH6_READ_ADDR; /*!< DMA Channel 6 Read Address pointer */ - __IOM uint32_t CH6_WRITE_ADDR; /*!< DMA Channel 6 Write Address pointer */ - __IOM uint32_t CH6_TRANS_COUNT; /*!< DMA Channel 6 Transfer Count */ - __IOM uint32_t CH6_CTRL_TRIG; /*!< DMA Channel 6 Control and Status */ - __IOM uint32_t CH6_AL1_CTRL; /*!< Alias for channel 6 CTRL register */ - __IOM uint32_t CH6_AL1_READ_ADDR; /*!< Alias for channel 6 READ_ADDR register */ - __IOM uint32_t CH6_AL1_WRITE_ADDR; /*!< Alias for channel 6 WRITE_ADDR register */ - __IOM uint32_t CH6_AL1_TRANS_COUNT_TRIG; /*!< Alias for channel 6 TRANS_COUNT register This is a trigger register - (0xc). Writing a nonzero value will reload the channel - counter and start the channel. */ - __IOM uint32_t CH6_AL2_CTRL; /*!< Alias for channel 6 CTRL register */ - __IOM uint32_t CH6_AL2_TRANS_COUNT; /*!< Alias for channel 6 TRANS_COUNT register */ - __IOM uint32_t CH6_AL2_READ_ADDR; /*!< Alias for channel 6 READ_ADDR register */ - __IOM uint32_t CH6_AL2_WRITE_ADDR_TRIG; /*!< Alias for channel 6 WRITE_ADDR register This is a trigger register - (0xc). Writing a nonzero value will reload the channel - counter and start the channel. */ - __IOM uint32_t CH6_AL3_CTRL; /*!< Alias for channel 6 CTRL register */ - __IOM uint32_t CH6_AL3_WRITE_ADDR; /*!< Alias for channel 6 WRITE_ADDR register */ - __IOM uint32_t CH6_AL3_TRANS_COUNT; /*!< Alias for channel 6 TRANS_COUNT register */ - __IOM uint32_t CH6_AL3_READ_ADDR_TRIG; /*!< Alias for channel 6 READ_ADDR register This is a trigger register - (0xc). Writing a nonzero value will reload the channel - counter and start the channel. */ - __IOM uint32_t CH7_READ_ADDR; /*!< DMA Channel 7 Read Address pointer */ - __IOM uint32_t CH7_WRITE_ADDR; /*!< DMA Channel 7 Write Address pointer */ - __IOM uint32_t CH7_TRANS_COUNT; /*!< DMA Channel 7 Transfer Count */ - __IOM uint32_t CH7_CTRL_TRIG; /*!< DMA Channel 7 Control and Status */ - __IOM uint32_t CH7_AL1_CTRL; /*!< Alias for channel 7 CTRL register */ - __IOM uint32_t CH7_AL1_READ_ADDR; /*!< Alias for channel 7 READ_ADDR register */ - __IOM uint32_t CH7_AL1_WRITE_ADDR; /*!< Alias for channel 7 WRITE_ADDR register */ - __IOM uint32_t CH7_AL1_TRANS_COUNT_TRIG; /*!< Alias for channel 7 TRANS_COUNT register This is a trigger register - (0xc). Writing a nonzero value will reload the channel - counter and start the channel. */ - __IOM uint32_t CH7_AL2_CTRL; /*!< Alias for channel 7 CTRL register */ - __IOM uint32_t CH7_AL2_TRANS_COUNT; /*!< Alias for channel 7 TRANS_COUNT register */ - __IOM uint32_t CH7_AL2_READ_ADDR; /*!< Alias for channel 7 READ_ADDR register */ - __IOM uint32_t CH7_AL2_WRITE_ADDR_TRIG; /*!< Alias for channel 7 WRITE_ADDR register This is a trigger register - (0xc). Writing a nonzero value will reload the channel - counter and start the channel. */ - __IOM uint32_t CH7_AL3_CTRL; /*!< Alias for channel 7 CTRL register */ - __IOM uint32_t CH7_AL3_WRITE_ADDR; /*!< Alias for channel 7 WRITE_ADDR register */ - __IOM uint32_t CH7_AL3_TRANS_COUNT; /*!< Alias for channel 7 TRANS_COUNT register */ - __IOM uint32_t CH7_AL3_READ_ADDR_TRIG; /*!< Alias for channel 7 READ_ADDR register This is a trigger register - (0xc). Writing a nonzero value will reload the channel - counter and start the channel. */ - __IOM uint32_t CH8_READ_ADDR; /*!< DMA Channel 8 Read Address pointer */ - __IOM uint32_t CH8_WRITE_ADDR; /*!< DMA Channel 8 Write Address pointer */ - __IOM uint32_t CH8_TRANS_COUNT; /*!< DMA Channel 8 Transfer Count */ - __IOM uint32_t CH8_CTRL_TRIG; /*!< DMA Channel 8 Control and Status */ - __IOM uint32_t CH8_AL1_CTRL; /*!< Alias for channel 8 CTRL register */ - __IOM uint32_t CH8_AL1_READ_ADDR; /*!< Alias for channel 8 READ_ADDR register */ - __IOM uint32_t CH8_AL1_WRITE_ADDR; /*!< Alias for channel 8 WRITE_ADDR register */ - __IOM uint32_t CH8_AL1_TRANS_COUNT_TRIG; /*!< Alias for channel 8 TRANS_COUNT register This is a trigger register - (0xc). Writing a nonzero value will reload the channel - counter and start the channel. */ - __IOM uint32_t CH8_AL2_CTRL; /*!< Alias for channel 8 CTRL register */ - __IOM uint32_t CH8_AL2_TRANS_COUNT; /*!< Alias for channel 8 TRANS_COUNT register */ - __IOM uint32_t CH8_AL2_READ_ADDR; /*!< Alias for channel 8 READ_ADDR register */ - __IOM uint32_t CH8_AL2_WRITE_ADDR_TRIG; /*!< Alias for channel 8 WRITE_ADDR register This is a trigger register - (0xc). Writing a nonzero value will reload the channel - counter and start the channel. */ - __IOM uint32_t CH8_AL3_CTRL; /*!< Alias for channel 8 CTRL register */ - __IOM uint32_t CH8_AL3_WRITE_ADDR; /*!< Alias for channel 8 WRITE_ADDR register */ - __IOM uint32_t CH8_AL3_TRANS_COUNT; /*!< Alias for channel 8 TRANS_COUNT register */ - __IOM uint32_t CH8_AL3_READ_ADDR_TRIG; /*!< Alias for channel 8 READ_ADDR register This is a trigger register - (0xc). Writing a nonzero value will reload the channel - counter and start the channel. */ - __IOM uint32_t CH9_READ_ADDR; /*!< DMA Channel 9 Read Address pointer */ - __IOM uint32_t CH9_WRITE_ADDR; /*!< DMA Channel 9 Write Address pointer */ - __IOM uint32_t CH9_TRANS_COUNT; /*!< DMA Channel 9 Transfer Count */ - __IOM uint32_t CH9_CTRL_TRIG; /*!< DMA Channel 9 Control and Status */ - __IOM uint32_t CH9_AL1_CTRL; /*!< Alias for channel 9 CTRL register */ - __IOM uint32_t CH9_AL1_READ_ADDR; /*!< Alias for channel 9 READ_ADDR register */ - __IOM uint32_t CH9_AL1_WRITE_ADDR; /*!< Alias for channel 9 WRITE_ADDR register */ - __IOM uint32_t CH9_AL1_TRANS_COUNT_TRIG; /*!< Alias for channel 9 TRANS_COUNT register This is a trigger register - (0xc). Writing a nonzero value will reload the channel - counter and start the channel. */ - __IOM uint32_t CH9_AL2_CTRL; /*!< Alias for channel 9 CTRL register */ - __IOM uint32_t CH9_AL2_TRANS_COUNT; /*!< Alias for channel 9 TRANS_COUNT register */ - __IOM uint32_t CH9_AL2_READ_ADDR; /*!< Alias for channel 9 READ_ADDR register */ - __IOM uint32_t CH9_AL2_WRITE_ADDR_TRIG; /*!< Alias for channel 9 WRITE_ADDR register This is a trigger register - (0xc). Writing a nonzero value will reload the channel - counter and start the channel. */ - __IOM uint32_t CH9_AL3_CTRL; /*!< Alias for channel 9 CTRL register */ - __IOM uint32_t CH9_AL3_WRITE_ADDR; /*!< Alias for channel 9 WRITE_ADDR register */ - __IOM uint32_t CH9_AL3_TRANS_COUNT; /*!< Alias for channel 9 TRANS_COUNT register */ - __IOM uint32_t CH9_AL3_READ_ADDR_TRIG; /*!< Alias for channel 9 READ_ADDR register This is a trigger register - (0xc). Writing a nonzero value will reload the channel - counter and start the channel. */ - __IOM uint32_t CH10_READ_ADDR; /*!< DMA Channel 10 Read Address pointer */ - __IOM uint32_t CH10_WRITE_ADDR; /*!< DMA Channel 10 Write Address pointer */ - __IOM uint32_t CH10_TRANS_COUNT; /*!< DMA Channel 10 Transfer Count */ - __IOM uint32_t CH10_CTRL_TRIG; /*!< DMA Channel 10 Control and Status */ - __IOM uint32_t CH10_AL1_CTRL; /*!< Alias for channel 10 CTRL register */ - __IOM uint32_t CH10_AL1_READ_ADDR; /*!< Alias for channel 10 READ_ADDR register */ - __IOM uint32_t CH10_AL1_WRITE_ADDR; /*!< Alias for channel 10 WRITE_ADDR register */ - __IOM uint32_t CH10_AL1_TRANS_COUNT_TRIG; /*!< Alias for channel 10 TRANS_COUNT register This is a trigger - register (0xc). Writing a nonzero value will reload the - channel counter and start the channel. */ - __IOM uint32_t CH10_AL2_CTRL; /*!< Alias for channel 10 CTRL register */ - __IOM uint32_t CH10_AL2_TRANS_COUNT; /*!< Alias for channel 10 TRANS_COUNT register */ - __IOM uint32_t CH10_AL2_READ_ADDR; /*!< Alias for channel 10 READ_ADDR register */ - __IOM uint32_t CH10_AL2_WRITE_ADDR_TRIG; /*!< Alias for channel 10 WRITE_ADDR register This is a trigger register - (0xc). Writing a nonzero value will reload the channel - counter and start the channel. */ - __IOM uint32_t CH10_AL3_CTRL; /*!< Alias for channel 10 CTRL register */ - __IOM uint32_t CH10_AL3_WRITE_ADDR; /*!< Alias for channel 10 WRITE_ADDR register */ - __IOM uint32_t CH10_AL3_TRANS_COUNT; /*!< Alias for channel 10 TRANS_COUNT register */ - __IOM uint32_t CH10_AL3_READ_ADDR_TRIG; /*!< Alias for channel 10 READ_ADDR register This is a trigger register - (0xc). Writing a nonzero value will reload the channel - counter and start the channel. */ - __IOM uint32_t CH11_READ_ADDR; /*!< DMA Channel 11 Read Address pointer */ - __IOM uint32_t CH11_WRITE_ADDR; /*!< DMA Channel 11 Write Address pointer */ - __IOM uint32_t CH11_TRANS_COUNT; /*!< DMA Channel 11 Transfer Count */ - __IOM uint32_t CH11_CTRL_TRIG; /*!< DMA Channel 11 Control and Status */ - __IOM uint32_t CH11_AL1_CTRL; /*!< Alias for channel 11 CTRL register */ - __IOM uint32_t CH11_AL1_READ_ADDR; /*!< Alias for channel 11 READ_ADDR register */ - __IOM uint32_t CH11_AL1_WRITE_ADDR; /*!< Alias for channel 11 WRITE_ADDR register */ - __IOM uint32_t CH11_AL1_TRANS_COUNT_TRIG; /*!< Alias for channel 11 TRANS_COUNT register This is a trigger - register (0xc). Writing a nonzero value will reload the - channel counter and start the channel. */ - __IOM uint32_t CH11_AL2_CTRL; /*!< Alias for channel 11 CTRL register */ - __IOM uint32_t CH11_AL2_TRANS_COUNT; /*!< Alias for channel 11 TRANS_COUNT register */ - __IOM uint32_t CH11_AL2_READ_ADDR; /*!< Alias for channel 11 READ_ADDR register */ - __IOM uint32_t CH11_AL2_WRITE_ADDR_TRIG; /*!< Alias for channel 11 WRITE_ADDR register This is a trigger register - (0xc). Writing a nonzero value will reload the channel - counter and start the channel. */ - __IOM uint32_t CH11_AL3_CTRL; /*!< Alias for channel 11 CTRL register */ - __IOM uint32_t CH11_AL3_WRITE_ADDR; /*!< Alias for channel 11 WRITE_ADDR register */ - __IOM uint32_t CH11_AL3_TRANS_COUNT; /*!< Alias for channel 11 TRANS_COUNT register */ - __IOM uint32_t CH11_AL3_READ_ADDR_TRIG; /*!< Alias for channel 11 READ_ADDR register This is a trigger register - (0xc). Writing a nonzero value will reload the channel - counter and start the channel. */ - __IOM uint32_t CH12_READ_ADDR; /*!< DMA Channel 12 Read Address pointer */ - __IOM uint32_t CH12_WRITE_ADDR; /*!< DMA Channel 12 Write Address pointer */ - __IOM uint32_t CH12_TRANS_COUNT; /*!< DMA Channel 12 Transfer Count */ - __IOM uint32_t CH12_CTRL_TRIG; /*!< DMA Channel 12 Control and Status */ - __IOM uint32_t CH12_AL1_CTRL; /*!< Alias for channel 12 CTRL register */ - __IOM uint32_t CH12_AL1_READ_ADDR; /*!< Alias for channel 12 READ_ADDR register */ - __IOM uint32_t CH12_AL1_WRITE_ADDR; /*!< Alias for channel 12 WRITE_ADDR register */ - __IOM uint32_t CH12_AL1_TRANS_COUNT_TRIG; /*!< Alias for channel 12 TRANS_COUNT register This is a trigger - register (0xc). Writing a nonzero value will reload the - channel counter and start the channel. */ - __IOM uint32_t CH12_AL2_CTRL; /*!< Alias for channel 12 CTRL register */ - __IOM uint32_t CH12_AL2_TRANS_COUNT; /*!< Alias for channel 12 TRANS_COUNT register */ - __IOM uint32_t CH12_AL2_READ_ADDR; /*!< Alias for channel 12 READ_ADDR register */ - __IOM uint32_t CH12_AL2_WRITE_ADDR_TRIG; /*!< Alias for channel 12 WRITE_ADDR register This is a trigger register - (0xc). Writing a nonzero value will reload the channel - counter and start the channel. */ - __IOM uint32_t CH12_AL3_CTRL; /*!< Alias for channel 12 CTRL register */ - __IOM uint32_t CH12_AL3_WRITE_ADDR; /*!< Alias for channel 12 WRITE_ADDR register */ - __IOM uint32_t CH12_AL3_TRANS_COUNT; /*!< Alias for channel 12 TRANS_COUNT register */ - __IOM uint32_t CH12_AL3_READ_ADDR_TRIG; /*!< Alias for channel 12 READ_ADDR register This is a trigger register - (0xc). Writing a nonzero value will reload the channel - counter and start the channel. */ - __IOM uint32_t CH13_READ_ADDR; /*!< DMA Channel 13 Read Address pointer */ - __IOM uint32_t CH13_WRITE_ADDR; /*!< DMA Channel 13 Write Address pointer */ - __IOM uint32_t CH13_TRANS_COUNT; /*!< DMA Channel 13 Transfer Count */ - __IOM uint32_t CH13_CTRL_TRIG; /*!< DMA Channel 13 Control and Status */ - __IOM uint32_t CH13_AL1_CTRL; /*!< Alias for channel 13 CTRL register */ - __IOM uint32_t CH13_AL1_READ_ADDR; /*!< Alias for channel 13 READ_ADDR register */ - __IOM uint32_t CH13_AL1_WRITE_ADDR; /*!< Alias for channel 13 WRITE_ADDR register */ - __IOM uint32_t CH13_AL1_TRANS_COUNT_TRIG; /*!< Alias for channel 13 TRANS_COUNT register This is a trigger - register (0xc). Writing a nonzero value will reload the - channel counter and start the channel. */ - __IOM uint32_t CH13_AL2_CTRL; /*!< Alias for channel 13 CTRL register */ - __IOM uint32_t CH13_AL2_TRANS_COUNT; /*!< Alias for channel 13 TRANS_COUNT register */ - __IOM uint32_t CH13_AL2_READ_ADDR; /*!< Alias for channel 13 READ_ADDR register */ - __IOM uint32_t CH13_AL2_WRITE_ADDR_TRIG; /*!< Alias for channel 13 WRITE_ADDR register This is a trigger register - (0xc). Writing a nonzero value will reload the channel - counter and start the channel. */ - __IOM uint32_t CH13_AL3_CTRL; /*!< Alias for channel 13 CTRL register */ - __IOM uint32_t CH13_AL3_WRITE_ADDR; /*!< Alias for channel 13 WRITE_ADDR register */ - __IOM uint32_t CH13_AL3_TRANS_COUNT; /*!< Alias for channel 13 TRANS_COUNT register */ - __IOM uint32_t CH13_AL3_READ_ADDR_TRIG; /*!< Alias for channel 13 READ_ADDR register This is a trigger register - (0xc). Writing a nonzero value will reload the channel - counter and start the channel. */ - __IOM uint32_t CH14_READ_ADDR; /*!< DMA Channel 14 Read Address pointer */ - __IOM uint32_t CH14_WRITE_ADDR; /*!< DMA Channel 14 Write Address pointer */ - __IOM uint32_t CH14_TRANS_COUNT; /*!< DMA Channel 14 Transfer Count */ - __IOM uint32_t CH14_CTRL_TRIG; /*!< DMA Channel 14 Control and Status */ - __IOM uint32_t CH14_AL1_CTRL; /*!< Alias for channel 14 CTRL register */ - __IOM uint32_t CH14_AL1_READ_ADDR; /*!< Alias for channel 14 READ_ADDR register */ - __IOM uint32_t CH14_AL1_WRITE_ADDR; /*!< Alias for channel 14 WRITE_ADDR register */ - __IOM uint32_t CH14_AL1_TRANS_COUNT_TRIG; /*!< Alias for channel 14 TRANS_COUNT register This is a trigger - register (0xc). Writing a nonzero value will reload the - channel counter and start the channel. */ - __IOM uint32_t CH14_AL2_CTRL; /*!< Alias for channel 14 CTRL register */ - __IOM uint32_t CH14_AL2_TRANS_COUNT; /*!< Alias for channel 14 TRANS_COUNT register */ - __IOM uint32_t CH14_AL2_READ_ADDR; /*!< Alias for channel 14 READ_ADDR register */ - __IOM uint32_t CH14_AL2_WRITE_ADDR_TRIG; /*!< Alias for channel 14 WRITE_ADDR register This is a trigger register - (0xc). Writing a nonzero value will reload the channel - counter and start the channel. */ - __IOM uint32_t CH14_AL3_CTRL; /*!< Alias for channel 14 CTRL register */ - __IOM uint32_t CH14_AL3_WRITE_ADDR; /*!< Alias for channel 14 WRITE_ADDR register */ - __IOM uint32_t CH14_AL3_TRANS_COUNT; /*!< Alias for channel 14 TRANS_COUNT register */ - __IOM uint32_t CH14_AL3_READ_ADDR_TRIG; /*!< Alias for channel 14 READ_ADDR register This is a trigger register - (0xc). Writing a nonzero value will reload the channel - counter and start the channel. */ - __IOM uint32_t CH15_READ_ADDR; /*!< DMA Channel 15 Read Address pointer */ - __IOM uint32_t CH15_WRITE_ADDR; /*!< DMA Channel 15 Write Address pointer */ - __IOM uint32_t CH15_TRANS_COUNT; /*!< DMA Channel 15 Transfer Count */ - __IOM uint32_t CH15_CTRL_TRIG; /*!< DMA Channel 15 Control and Status */ - __IOM uint32_t CH15_AL1_CTRL; /*!< Alias for channel 15 CTRL register */ - __IOM uint32_t CH15_AL1_READ_ADDR; /*!< Alias for channel 15 READ_ADDR register */ - __IOM uint32_t CH15_AL1_WRITE_ADDR; /*!< Alias for channel 15 WRITE_ADDR register */ - __IOM uint32_t CH15_AL1_TRANS_COUNT_TRIG; /*!< Alias for channel 15 TRANS_COUNT register This is a trigger - register (0xc). Writing a nonzero value will reload the - channel counter and start the channel. */ - __IOM uint32_t CH15_AL2_CTRL; /*!< Alias for channel 15 CTRL register */ - __IOM uint32_t CH15_AL2_TRANS_COUNT; /*!< Alias for channel 15 TRANS_COUNT register */ - __IOM uint32_t CH15_AL2_READ_ADDR; /*!< Alias for channel 15 READ_ADDR register */ - __IOM uint32_t CH15_AL2_WRITE_ADDR_TRIG; /*!< Alias for channel 15 WRITE_ADDR register This is a trigger register - (0xc). Writing a nonzero value will reload the channel - counter and start the channel. */ - __IOM uint32_t CH15_AL3_CTRL; /*!< Alias for channel 15 CTRL register */ - __IOM uint32_t CH15_AL3_WRITE_ADDR; /*!< Alias for channel 15 WRITE_ADDR register */ - __IOM uint32_t CH15_AL3_TRANS_COUNT; /*!< Alias for channel 15 TRANS_COUNT register */ - __IOM uint32_t CH15_AL3_READ_ADDR_TRIG; /*!< Alias for channel 15 READ_ADDR register This is a trigger register - (0xc). Writing a nonzero value will reload the channel - counter and start the channel. */ - __IOM uint32_t INTR; /*!< Interrupt Status (raw) */ - __IOM uint32_t INTE0; /*!< Interrupt Enables for IRQ 0 */ - __IOM uint32_t INTF0; /*!< Force Interrupts */ - __IOM uint32_t INTS0; /*!< Interrupt Status for IRQ 0 */ - __IOM uint32_t INTR1; /*!< Interrupt Status (raw) */ - __IOM uint32_t INTE1; /*!< Interrupt Enables for IRQ 1 */ - __IOM uint32_t INTF1; /*!< Force Interrupts */ - __IOM uint32_t INTS1; /*!< Interrupt Status for IRQ 1 */ - __IOM uint32_t INTR2; /*!< Interrupt Status (raw) */ - __IOM uint32_t INTE2; /*!< Interrupt Enables for IRQ 2 */ - __IOM uint32_t INTF2; /*!< Force Interrupts */ - __IOM uint32_t INTS2; /*!< Interrupt Status for IRQ 2 */ - __IOM uint32_t INTR3; /*!< Interrupt Status (raw) */ - __IOM uint32_t INTE3; /*!< Interrupt Enables for IRQ 3 */ - __IOM uint32_t INTF3; /*!< Force Interrupts */ - __IOM uint32_t INTS3; /*!< Interrupt Status for IRQ 3 */ - __IOM uint32_t TIMER0; /*!< Pacing (X/Y) fractional timer The pacing timer produces TREQ - assertions at a rate set by ((X/Y) * sys_clk). This equation - is evaluated every sys_clk cycles and therefore can only - generate TREQs at a rate of 1 per sys_clk (i.e. permanent - TREQ) or less. */ - __IOM uint32_t TIMER1; /*!< Pacing (X/Y) fractional timer The pacing timer produces TREQ - assertions at a rate set by ((X/Y) * sys_clk). This equation - is evaluated every sys_clk cycles and therefore can only - generate TREQs at a rate of 1 per sys_clk (i.e. permanent - TREQ) or less. */ - __IOM uint32_t TIMER2; /*!< Pacing (X/Y) fractional timer The pacing timer produces TREQ - assertions at a rate set by ((X/Y) * sys_clk). This equation - is evaluated every sys_clk cycles and therefore can only - generate TREQs at a rate of 1 per sys_clk (i.e. permanent - TREQ) or less. */ - __IOM uint32_t TIMER3; /*!< Pacing (X/Y) fractional timer The pacing timer produces TREQ - assertions at a rate set by ((X/Y) * sys_clk). This equation - is evaluated every sys_clk cycles and therefore can only - generate TREQs at a rate of 1 per sys_clk (i.e. permanent - TREQ) or less. */ - __IOM uint32_t MULTI_CHAN_TRIGGER; /*!< Trigger one or more channels simultaneously */ - __IOM uint32_t SNIFF_CTRL; /*!< Sniffer Control */ - __IOM uint32_t SNIFF_DATA; /*!< Data accumulator for sniff hardware */ - __IM uint32_t RESERVED; - __IOM uint32_t FIFO_LEVELS; /*!< Debug RAF, WAF, TDF levels */ - __IOM uint32_t CHAN_ABORT; /*!< Abort an in-progress transfer sequence on one or more channels */ - __IOM uint32_t N_CHANNELS; /*!< The number of channels this DMA instance is equipped with. This - DMA supports up to 16 hardware channels, but can be configured - with as few as one, to minimise silicon area. */ - __IM uint32_t RESERVED1[5]; - __IOM uint32_t SECCFG_CH0; /*!< Security configuration for channel 0. Control whether this channel - performs Secure/Non-secure and Privileged/Unprivileged - bus accesses. If this channel generates bus accesses of - some security level, an access of at least that level (in - the order S+P > S+U > NS+P > NS+U) is required to program, - trigger, abort, check the status of, interrupt on or acknowledge - the interrupt of this channel. This register automatically - locks down (becomes read-only) once software starts to - configure the channel. This register is world-readable, - but is writable only from a Secure, Privileged context. */ - __IOM uint32_t SECCFG_CH1; /*!< Security configuration for channel 1. Control whether this channel - performs Secure/Non-secure and Privileged/Unprivileged - bus accesses. If this channel generates bus accesses of - some security level, an access of at least that level (in - the order S+P > S+U > NS+P > NS+U) is required to program, - trigger, abort, check the status of, interrupt on or acknowledge - the interrupt of this channel. This register automatically - locks down (becomes read-only) once software starts to - configure the channel. This register is world-readable, - but is writable only from a Secure, Privileged context. */ - __IOM uint32_t SECCFG_CH2; /*!< Security configuration for channel 2. Control whether this channel - performs Secure/Non-secure and Privileged/Unprivileged - bus accesses. If this channel generates bus accesses of - some security level, an access of at least that level (in - the order S+P > S+U > NS+P > NS+U) is required to program, - trigger, abort, check the status of, interrupt on or acknowledge - the interrupt of this channel. This register automatically - locks down (becomes read-only) once software starts to - configure the channel. This register is world-readable, - but is writable only from a Secure, Privileged context. */ - __IOM uint32_t SECCFG_CH3; /*!< Security configuration for channel 3. Control whether this channel - performs Secure/Non-secure and Privileged/Unprivileged - bus accesses. If this channel generates bus accesses of - some security level, an access of at least that level (in - the order S+P > S+U > NS+P > NS+U) is required to program, - trigger, abort, check the status of, interrupt on or acknowledge - the interrupt of this channel. This register automatically - locks down (becomes read-only) once software starts to - configure the channel. This register is world-readable, - but is writable only from a Secure, Privileged context. */ - __IOM uint32_t SECCFG_CH4; /*!< Security configuration for channel 4. Control whether this channel - performs Secure/Non-secure and Privileged/Unprivileged - bus accesses. If this channel generates bus accesses of - some security level, an access of at least that level (in - the order S+P > S+U > NS+P > NS+U) is required to program, - trigger, abort, check the status of, interrupt on or acknowledge - the interrupt of this channel. This register automatically - locks down (becomes read-only) once software starts to - configure the channel. This register is world-readable, - but is writable only from a Secure, Privileged context. */ - __IOM uint32_t SECCFG_CH5; /*!< Security configuration for channel 5. Control whether this channel - performs Secure/Non-secure and Privileged/Unprivileged - bus accesses. If this channel generates bus accesses of - some security level, an access of at least that level (in - the order S+P > S+U > NS+P > NS+U) is required to program, - trigger, abort, check the status of, interrupt on or acknowledge - the interrupt of this channel. This register automatically - locks down (becomes read-only) once software starts to - configure the channel. This register is world-readable, - but is writable only from a Secure, Privileged context. */ - __IOM uint32_t SECCFG_CH6; /*!< Security configuration for channel 6. Control whether this channel - performs Secure/Non-secure and Privileged/Unprivileged - bus accesses. If this channel generates bus accesses of - some security level, an access of at least that level (in - the order S+P > S+U > NS+P > NS+U) is required to program, - trigger, abort, check the status of, interrupt on or acknowledge - the interrupt of this channel. This register automatically - locks down (becomes read-only) once software starts to - configure the channel. This register is world-readable, - but is writable only from a Secure, Privileged context. */ - __IOM uint32_t SECCFG_CH7; /*!< Security configuration for channel 7. Control whether this channel - performs Secure/Non-secure and Privileged/Unprivileged - bus accesses. If this channel generates bus accesses of - some security level, an access of at least that level (in - the order S+P > S+U > NS+P > NS+U) is required to program, - trigger, abort, check the status of, interrupt on or acknowledge - the interrupt of this channel. This register automatically - locks down (becomes read-only) once software starts to - configure the channel. This register is world-readable, - but is writable only from a Secure, Privileged context. */ - __IOM uint32_t SECCFG_CH8; /*!< Security configuration for channel 8. Control whether this channel - performs Secure/Non-secure and Privileged/Unprivileged - bus accesses. If this channel generates bus accesses of - some security level, an access of at least that level (in - the order S+P > S+U > NS+P > NS+U) is required to program, - trigger, abort, check the status of, interrupt on or acknowledge - the interrupt of this channel. This register automatically - locks down (becomes read-only) once software starts to - configure the channel. This register is world-readable, - but is writable only from a Secure, Privileged context. */ - __IOM uint32_t SECCFG_CH9; /*!< Security configuration for channel 9. Control whether this channel - performs Secure/Non-secure and Privileged/Unprivileged - bus accesses. If this channel generates bus accesses of - some security level, an access of at least that level (in - the order S+P > S+U > NS+P > NS+U) is required to program, - trigger, abort, check the status of, interrupt on or acknowledge - the interrupt of this channel. This register automatically - locks down (becomes read-only) once software starts to - configure the channel. This register is world-readable, - but is writable only from a Secure, Privileged context. */ - __IOM uint32_t SECCFG_CH10; /*!< Security configuration for channel 10. Control whether this - channel performs Secure/Non-secure and Privileged/Unprivileged - bus accesses. If this channel generates bus accesses of - some security level, an access of at least that level (in - the order S+P > S+U > NS+P > NS+U) is required to program, - trigger, abort, check the status of, interrupt on or acknowledge - the interrupt of this channel. This register automatically - locks down (becomes read-only) once software starts to - configure the channel. This register is world-readable, - but is writable only from a Secure, Privileged context. */ - __IOM uint32_t SECCFG_CH11; /*!< Security configuration for channel 11. Control whether this - channel performs Secure/Non-secure and Privileged/Unprivileged - bus accesses. If this channel generates bus accesses of - some security level, an access of at least that level (in - the order S+P > S+U > NS+P > NS+U) is required to program, - trigger, abort, check the status of, interrupt on or acknowledge - the interrupt of this channel. This register automatically - locks down (becomes read-only) once software starts to - configure the channel. This register is world-readable, - but is writable only from a Secure, Privileged context. */ - __IOM uint32_t SECCFG_CH12; /*!< Security configuration for channel 12. Control whether this - channel performs Secure/Non-secure and Privileged/Unprivileged - bus accesses. If this channel generates bus accesses of - some security level, an access of at least that level (in - the order S+P > S+U > NS+P > NS+U) is required to program, - trigger, abort, check the status of, interrupt on or acknowledge - the interrupt of this channel. This register automatically - locks down (becomes read-only) once software starts to - configure the channel. This register is world-readable, - but is writable only from a Secure, Privileged context. */ - __IOM uint32_t SECCFG_CH13; /*!< Security configuration for channel 13. Control whether this - channel performs Secure/Non-secure and Privileged/Unprivileged - bus accesses. If this channel generates bus accesses of - some security level, an access of at least that level (in - the order S+P > S+U > NS+P > NS+U) is required to program, - trigger, abort, check the status of, interrupt on or acknowledge - the interrupt of this channel. This register automatically - locks down (becomes read-only) once software starts to - configure the channel. This register is world-readable, - but is writable only from a Secure, Privileged context. */ - __IOM uint32_t SECCFG_CH14; /*!< Security configuration for channel 14. Control whether this - channel performs Secure/Non-secure and Privileged/Unprivileged - bus accesses. If this channel generates bus accesses of - some security level, an access of at least that level (in - the order S+P > S+U > NS+P > NS+U) is required to program, - trigger, abort, check the status of, interrupt on or acknowledge - the interrupt of this channel. This register automatically - locks down (becomes read-only) once software starts to - configure the channel. This register is world-readable, - but is writable only from a Secure, Privileged context. */ - __IOM uint32_t SECCFG_CH15; /*!< Security configuration for channel 15. Control whether this - channel performs Secure/Non-secure and Privileged/Unprivileged - bus accesses. If this channel generates bus accesses of - some security level, an access of at least that level (in - the order S+P > S+U > NS+P > NS+U) is required to program, - trigger, abort, check the status of, interrupt on or acknowledge - the interrupt of this channel. This register automatically - locks down (becomes read-only) once software starts to - configure the channel. This register is world-readable, - but is writable only from a Secure, Privileged context. */ - __IOM uint32_t SECCFG_IRQ0; /*!< Security configuration for IRQ 0. Control whether the IRQ permits - configuration by Non-secure/Unprivileged contexts, and - whether it can observe Secure/Privileged channel interrupt - flags. */ - __IOM uint32_t SECCFG_IRQ1; /*!< Security configuration for IRQ 1. Control whether the IRQ permits - configuration by Non-secure/Unprivileged contexts, and - whether it can observe Secure/Privileged channel interrupt - flags. */ - __IOM uint32_t SECCFG_IRQ2; /*!< Security configuration for IRQ 2. Control whether the IRQ permits - configuration by Non-secure/Unprivileged contexts, and - whether it can observe Secure/Privileged channel interrupt - flags. */ - __IOM uint32_t SECCFG_IRQ3; /*!< Security configuration for IRQ 3. Control whether the IRQ permits - configuration by Non-secure/Unprivileged contexts, and - whether it can observe Secure/Privileged channel interrupt - flags. */ - __IOM uint32_t SECCFG_MISC; /*!< Miscellaneous security configuration */ - __IM uint32_t RESERVED2[11]; - __IOM uint32_t MPU_CTRL; /*!< Control register for DMA MPU. Accessible only from a Privileged - context. */ - __IOM uint32_t MPU_BAR0; /*!< Base address register for MPU region 0. Writable only from a - Secure, Privileged context. */ - __IOM uint32_t MPU_LAR0; /*!< Limit address register for MPU region 0. Writable only from - a Secure, Privileged context, with the exception of the - P bit. */ - __IOM uint32_t MPU_BAR1; /*!< Base address register for MPU region 1. Writable only from a - Secure, Privileged context. */ - __IOM uint32_t MPU_LAR1; /*!< Limit address register for MPU region 1. Writable only from - a Secure, Privileged context, with the exception of the - P bit. */ - __IOM uint32_t MPU_BAR2; /*!< Base address register for MPU region 2. Writable only from a - Secure, Privileged context. */ - __IOM uint32_t MPU_LAR2; /*!< Limit address register for MPU region 2. Writable only from - a Secure, Privileged context, with the exception of the - P bit. */ - __IOM uint32_t MPU_BAR3; /*!< Base address register for MPU region 3. Writable only from a - Secure, Privileged context. */ - __IOM uint32_t MPU_LAR3; /*!< Limit address register for MPU region 3. Writable only from - a Secure, Privileged context, with the exception of the - P bit. */ - __IOM uint32_t MPU_BAR4; /*!< Base address register for MPU region 4. Writable only from a - Secure, Privileged context. */ - __IOM uint32_t MPU_LAR4; /*!< Limit address register for MPU region 4. Writable only from - a Secure, Privileged context, with the exception of the - P bit. */ - __IOM uint32_t MPU_BAR5; /*!< Base address register for MPU region 5. Writable only from a - Secure, Privileged context. */ - __IOM uint32_t MPU_LAR5; /*!< Limit address register for MPU region 5. Writable only from - a Secure, Privileged context, with the exception of the - P bit. */ - __IOM uint32_t MPU_BAR6; /*!< Base address register for MPU region 6. Writable only from a - Secure, Privileged context. */ - __IOM uint32_t MPU_LAR6; /*!< Limit address register for MPU region 6. Writable only from - a Secure, Privileged context, with the exception of the - P bit. */ - __IOM uint32_t MPU_BAR7; /*!< Base address register for MPU region 7. Writable only from a - Secure, Privileged context. */ - __IOM uint32_t MPU_LAR7; /*!< Limit address register for MPU region 7. Writable only from - a Secure, Privileged context, with the exception of the - P bit. */ - __IM uint32_t RESERVED3[175]; - __IOM uint32_t CH0_DBG_CTDREQ; /*!< Read: get channel DREQ counter (i.e. how many accesses the DMA - expects it can perform on the peripheral without overflow/underflow. - Write any value: clears the counter, and cause channel - to re-initiate DREQ handshake. */ - __IOM uint32_t CH0_DBG_TCR; /*!< Read to get channel TRANS_COUNT reload value, i.e. the length - of the next transfer */ - __IM uint32_t RESERVED4[14]; - __IOM uint32_t CH1_DBG_CTDREQ; /*!< Read: get channel DREQ counter (i.e. how many accesses the DMA - expects it can perform on the peripheral without overflow/underflow. - Write any value: clears the counter, and cause channel - to re-initiate DREQ handshake. */ - __IOM uint32_t CH1_DBG_TCR; /*!< Read to get channel TRANS_COUNT reload value, i.e. the length - of the next transfer */ - __IM uint32_t RESERVED5[14]; - __IOM uint32_t CH2_DBG_CTDREQ; /*!< Read: get channel DREQ counter (i.e. how many accesses the DMA - expects it can perform on the peripheral without overflow/underflow. - Write any value: clears the counter, and cause channel - to re-initiate DREQ handshake. */ - __IOM uint32_t CH2_DBG_TCR; /*!< Read to get channel TRANS_COUNT reload value, i.e. the length - of the next transfer */ - __IM uint32_t RESERVED6[14]; - __IOM uint32_t CH3_DBG_CTDREQ; /*!< Read: get channel DREQ counter (i.e. how many accesses the DMA - expects it can perform on the peripheral without overflow/underflow. - Write any value: clears the counter, and cause channel - to re-initiate DREQ handshake. */ - __IOM uint32_t CH3_DBG_TCR; /*!< Read to get channel TRANS_COUNT reload value, i.e. the length - of the next transfer */ - __IM uint32_t RESERVED7[14]; - __IOM uint32_t CH4_DBG_CTDREQ; /*!< Read: get channel DREQ counter (i.e. how many accesses the DMA - expects it can perform on the peripheral without overflow/underflow. - Write any value: clears the counter, and cause channel - to re-initiate DREQ handshake. */ - __IOM uint32_t CH4_DBG_TCR; /*!< Read to get channel TRANS_COUNT reload value, i.e. the length - of the next transfer */ - __IM uint32_t RESERVED8[14]; - __IOM uint32_t CH5_DBG_CTDREQ; /*!< Read: get channel DREQ counter (i.e. how many accesses the DMA - expects it can perform on the peripheral without overflow/underflow. - Write any value: clears the counter, and cause channel - to re-initiate DREQ handshake. */ - __IOM uint32_t CH5_DBG_TCR; /*!< Read to get channel TRANS_COUNT reload value, i.e. the length - of the next transfer */ - __IM uint32_t RESERVED9[14]; - __IOM uint32_t CH6_DBG_CTDREQ; /*!< Read: get channel DREQ counter (i.e. how many accesses the DMA - expects it can perform on the peripheral without overflow/underflow. - Write any value: clears the counter, and cause channel - to re-initiate DREQ handshake. */ - __IOM uint32_t CH6_DBG_TCR; /*!< Read to get channel TRANS_COUNT reload value, i.e. the length - of the next transfer */ - __IM uint32_t RESERVED10[14]; - __IOM uint32_t CH7_DBG_CTDREQ; /*!< Read: get channel DREQ counter (i.e. how many accesses the DMA - expects it can perform on the peripheral without overflow/underflow. - Write any value: clears the counter, and cause channel - to re-initiate DREQ handshake. */ - __IOM uint32_t CH7_DBG_TCR; /*!< Read to get channel TRANS_COUNT reload value, i.e. the length - of the next transfer */ - __IM uint32_t RESERVED11[14]; - __IOM uint32_t CH8_DBG_CTDREQ; /*!< Read: get channel DREQ counter (i.e. how many accesses the DMA - expects it can perform on the peripheral without overflow/underflow. - Write any value: clears the counter, and cause channel - to re-initiate DREQ handshake. */ - __IOM uint32_t CH8_DBG_TCR; /*!< Read to get channel TRANS_COUNT reload value, i.e. the length - of the next transfer */ - __IM uint32_t RESERVED12[14]; - __IOM uint32_t CH9_DBG_CTDREQ; /*!< Read: get channel DREQ counter (i.e. how many accesses the DMA - expects it can perform on the peripheral without overflow/underflow. - Write any value: clears the counter, and cause channel - to re-initiate DREQ handshake. */ - __IOM uint32_t CH9_DBG_TCR; /*!< Read to get channel TRANS_COUNT reload value, i.e. the length - of the next transfer */ - __IM uint32_t RESERVED13[14]; - __IOM uint32_t CH10_DBG_CTDREQ; /*!< Read: get channel DREQ counter (i.e. how many accesses the DMA - expects it can perform on the peripheral without overflow/underflow. - Write any value: clears the counter, and cause channel - to re-initiate DREQ handshake. */ - __IOM uint32_t CH10_DBG_TCR; /*!< Read to get channel TRANS_COUNT reload value, i.e. the length - of the next transfer */ - __IM uint32_t RESERVED14[14]; - __IOM uint32_t CH11_DBG_CTDREQ; /*!< Read: get channel DREQ counter (i.e. how many accesses the DMA - expects it can perform on the peripheral without overflow/underflow. - Write any value: clears the counter, and cause channel - to re-initiate DREQ handshake. */ - __IOM uint32_t CH11_DBG_TCR; /*!< Read to get channel TRANS_COUNT reload value, i.e. the length - of the next transfer */ - __IM uint32_t RESERVED15[14]; - __IOM uint32_t CH12_DBG_CTDREQ; /*!< Read: get channel DREQ counter (i.e. how many accesses the DMA - expects it can perform on the peripheral without overflow/underflow. - Write any value: clears the counter, and cause channel - to re-initiate DREQ handshake. */ - __IOM uint32_t CH12_DBG_TCR; /*!< Read to get channel TRANS_COUNT reload value, i.e. the length - of the next transfer */ - __IM uint32_t RESERVED16[14]; - __IOM uint32_t CH13_DBG_CTDREQ; /*!< Read: get channel DREQ counter (i.e. how many accesses the DMA - expects it can perform on the peripheral without overflow/underflow. - Write any value: clears the counter, and cause channel - to re-initiate DREQ handshake. */ - __IOM uint32_t CH13_DBG_TCR; /*!< Read to get channel TRANS_COUNT reload value, i.e. the length - of the next transfer */ - __IM uint32_t RESERVED17[14]; - __IOM uint32_t CH14_DBG_CTDREQ; /*!< Read: get channel DREQ counter (i.e. how many accesses the DMA - expects it can perform on the peripheral without overflow/underflow. - Write any value: clears the counter, and cause channel - to re-initiate DREQ handshake. */ - __IOM uint32_t CH14_DBG_TCR; /*!< Read to get channel TRANS_COUNT reload value, i.e. the length - of the next transfer */ - __IM uint32_t RESERVED18[14]; - __IOM uint32_t CH15_DBG_CTDREQ; /*!< Read: get channel DREQ counter (i.e. how many accesses the DMA - expects it can perform on the peripheral without overflow/underflow. - Write any value: clears the counter, and cause channel - to re-initiate DREQ handshake. */ - __IOM uint32_t CH15_DBG_TCR; /*!< Read to get channel TRANS_COUNT reload value, i.e. the length - of the next transfer */ -} DMA_Type; /*!< Size = 3016 (0xbc8) */ - - - -/* =========================================================================================================================== */ -/* ================ TIMER0 ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief Controls time and alarms - - time is a 64 bit value indicating the time since power-on - - timeh is the top 32 bits of time & timel is the bottom 32 bits to change time write to timelw before timehw to read time read from timelr before timehr - - An alarm is set by setting alarm_enable and writing to the corresponding alarm register When an alarm is pending, the corresponding alarm_running signal will be high An alarm can be cancelled before it has finished by clearing the alarm_enable When an alarm fires, the corresponding alarm_irq is set and alarm_running is cleared To clear the interrupt write a 1 to the corresponding alarm_irq The timer can be locked to prevent writing (TIMER0) - */ - -typedef struct { /*!< TIMER0 Structure */ - __IOM uint32_t TIMEHW; /*!< Write to bits 63:32 of time always write timelw before timehw */ - __IOM uint32_t TIMELW; /*!< Write to bits 31:0 of time writes do not get copied to time - until timehw is written */ - __IOM uint32_t TIMEHR; /*!< Read from bits 63:32 of time always read timelr before timehr */ - __IOM uint32_t TIMELR; /*!< Read from bits 31:0 of time */ - __IOM uint32_t ALARM0; /*!< Arm alarm 0, and configure the time it will fire. Once armed, - the alarm fires when TIMER_ALARM0 == TIMELR. The alarm - will disarm itself once it fires, and can be disarmed early - using the ARMED status register. */ - __IOM uint32_t ALARM1; /*!< Arm alarm 1, and configure the time it will fire. Once armed, - the alarm fires when TIMER_ALARM1 == TIMELR. The alarm - will disarm itself once it fires, and can be disarmed early - using the ARMED status register. */ - __IOM uint32_t ALARM2; /*!< Arm alarm 2, and configure the time it will fire. Once armed, - the alarm fires when TIMER_ALARM2 == TIMELR. The alarm - will disarm itself once it fires, and can be disarmed early - using the ARMED status register. */ - __IOM uint32_t ALARM3; /*!< Arm alarm 3, and configure the time it will fire. Once armed, - the alarm fires when TIMER_ALARM3 == TIMELR. The alarm - will disarm itself once it fires, and can be disarmed early - using the ARMED status register. */ - __IOM uint32_t ARMED; /*!< Indicates the armed/disarmed status of each alarm. A write to - the corresponding ALARMx register arms the alarm. Alarms - automatically disarm upon firing, but writing ones here - will disarm immediately without waiting to fire. */ - __IOM uint32_t TIMERAWH; /*!< Raw read from bits 63:32 of time (no side effects) */ - __IOM uint32_t TIMERAWL; /*!< Raw read from bits 31:0 of time (no side effects) */ - __IOM uint32_t DBGPAUSE; /*!< Set bits high to enable pause when the corresponding debug ports - are active */ - __IOM uint32_t PAUSE; /*!< Set high to pause the timer */ - __IOM uint32_t LOCKED; /*!< Set locked bit to disable write access to timer Once set, cannot - be cleared (without a reset) */ - __IOM uint32_t SOURCE; /*!< Selects the source for the timer. Defaults to the normal tick - configured in the ticks block (typically configured to - 1 microsecond). Writing to 1 will ignore the tick and count - clk_sys cycles instead. */ - __IOM uint32_t INTR; /*!< Raw Interrupts */ - __IOM uint32_t INTE; /*!< Interrupt Enable */ - __IOM uint32_t INTF; /*!< Interrupt Force */ - __IOM uint32_t INTS; /*!< Interrupt status after masking & forcing */ -} TIMER0_Type; /*!< Size = 76 (0x4c) */ - - - -/* =========================================================================================================================== */ -/* ================ PWM ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief Simple PWM (PWM) - */ - -typedef struct { /*!< PWM Structure */ - __IOM uint32_t CH0_CSR; /*!< Control and status register */ - __IOM uint32_t CH0_DIV; /*!< INT and FRAC form a fixed-point fractional number. Counting - rate is system clock frequency divided by this number. - Fractional division uses simple 1st-order sigma-delta. */ - __IOM uint32_t CH0_CTR; /*!< Direct access to the PWM counter */ - __IOM uint32_t CH0_CC; /*!< Counter compare values */ - __IOM uint32_t CH0_TOP; /*!< Counter wrap value */ - __IOM uint32_t CH1_CSR; /*!< Control and status register */ - __IOM uint32_t CH1_DIV; /*!< INT and FRAC form a fixed-point fractional number. Counting - rate is system clock frequency divided by this number. - Fractional division uses simple 1st-order sigma-delta. */ - __IOM uint32_t CH1_CTR; /*!< Direct access to the PWM counter */ - __IOM uint32_t CH1_CC; /*!< Counter compare values */ - __IOM uint32_t CH1_TOP; /*!< Counter wrap value */ - __IOM uint32_t CH2_CSR; /*!< Control and status register */ - __IOM uint32_t CH2_DIV; /*!< INT and FRAC form a fixed-point fractional number. Counting - rate is system clock frequency divided by this number. - Fractional division uses simple 1st-order sigma-delta. */ - __IOM uint32_t CH2_CTR; /*!< Direct access to the PWM counter */ - __IOM uint32_t CH2_CC; /*!< Counter compare values */ - __IOM uint32_t CH2_TOP; /*!< Counter wrap value */ - __IOM uint32_t CH3_CSR; /*!< Control and status register */ - __IOM uint32_t CH3_DIV; /*!< INT and FRAC form a fixed-point fractional number. Counting - rate is system clock frequency divided by this number. - Fractional division uses simple 1st-order sigma-delta. */ - __IOM uint32_t CH3_CTR; /*!< Direct access to the PWM counter */ - __IOM uint32_t CH3_CC; /*!< Counter compare values */ - __IOM uint32_t CH3_TOP; /*!< Counter wrap value */ - __IOM uint32_t CH4_CSR; /*!< Control and status register */ - __IOM uint32_t CH4_DIV; /*!< INT and FRAC form a fixed-point fractional number. Counting - rate is system clock frequency divided by this number. - Fractional division uses simple 1st-order sigma-delta. */ - __IOM uint32_t CH4_CTR; /*!< Direct access to the PWM counter */ - __IOM uint32_t CH4_CC; /*!< Counter compare values */ - __IOM uint32_t CH4_TOP; /*!< Counter wrap value */ - __IOM uint32_t CH5_CSR; /*!< Control and status register */ - __IOM uint32_t CH5_DIV; /*!< INT and FRAC form a fixed-point fractional number. Counting - rate is system clock frequency divided by this number. - Fractional division uses simple 1st-order sigma-delta. */ - __IOM uint32_t CH5_CTR; /*!< Direct access to the PWM counter */ - __IOM uint32_t CH5_CC; /*!< Counter compare values */ - __IOM uint32_t CH5_TOP; /*!< Counter wrap value */ - __IOM uint32_t CH6_CSR; /*!< Control and status register */ - __IOM uint32_t CH6_DIV; /*!< INT and FRAC form a fixed-point fractional number. Counting - rate is system clock frequency divided by this number. - Fractional division uses simple 1st-order sigma-delta. */ - __IOM uint32_t CH6_CTR; /*!< Direct access to the PWM counter */ - __IOM uint32_t CH6_CC; /*!< Counter compare values */ - __IOM uint32_t CH6_TOP; /*!< Counter wrap value */ - __IOM uint32_t CH7_CSR; /*!< Control and status register */ - __IOM uint32_t CH7_DIV; /*!< INT and FRAC form a fixed-point fractional number. Counting - rate is system clock frequency divided by this number. - Fractional division uses simple 1st-order sigma-delta. */ - __IOM uint32_t CH7_CTR; /*!< Direct access to the PWM counter */ - __IOM uint32_t CH7_CC; /*!< Counter compare values */ - __IOM uint32_t CH7_TOP; /*!< Counter wrap value */ - __IOM uint32_t CH8_CSR; /*!< Control and status register */ - __IOM uint32_t CH8_DIV; /*!< INT and FRAC form a fixed-point fractional number. Counting - rate is system clock frequency divided by this number. - Fractional division uses simple 1st-order sigma-delta. */ - __IOM uint32_t CH8_CTR; /*!< Direct access to the PWM counter */ - __IOM uint32_t CH8_CC; /*!< Counter compare values */ - __IOM uint32_t CH8_TOP; /*!< Counter wrap value */ - __IOM uint32_t CH9_CSR; /*!< Control and status register */ - __IOM uint32_t CH9_DIV; /*!< INT and FRAC form a fixed-point fractional number. Counting - rate is system clock frequency divided by this number. - Fractional division uses simple 1st-order sigma-delta. */ - __IOM uint32_t CH9_CTR; /*!< Direct access to the PWM counter */ - __IOM uint32_t CH9_CC; /*!< Counter compare values */ - __IOM uint32_t CH9_TOP; /*!< Counter wrap value */ - __IOM uint32_t CH10_CSR; /*!< Control and status register */ - __IOM uint32_t CH10_DIV; /*!< INT and FRAC form a fixed-point fractional number. Counting - rate is system clock frequency divided by this number. - Fractional division uses simple 1st-order sigma-delta. */ - __IOM uint32_t CH10_CTR; /*!< Direct access to the PWM counter */ - __IOM uint32_t CH10_CC; /*!< Counter compare values */ - __IOM uint32_t CH10_TOP; /*!< Counter wrap value */ - __IOM uint32_t CH11_CSR; /*!< Control and status register */ - __IOM uint32_t CH11_DIV; /*!< INT and FRAC form a fixed-point fractional number. Counting - rate is system clock frequency divided by this number. - Fractional division uses simple 1st-order sigma-delta. */ - __IOM uint32_t CH11_CTR; /*!< Direct access to the PWM counter */ - __IOM uint32_t CH11_CC; /*!< Counter compare values */ - __IOM uint32_t CH11_TOP; /*!< Counter wrap value */ - __IOM uint32_t EN; /*!< This register aliases the CSR_EN bits for all channels. Writing - to this register allows multiple channels to be enabled - or disabled simultaneously, so they can run in perfect - sync. For each channel, there is only one physical EN register - bit, which can be accessed through here or CHx_CSR. */ - __IOM uint32_t INTR; /*!< Raw Interrupts */ - __IOM uint32_t IRQ0_INTE; /*!< Interrupt Enable for irq0 */ - __IOM uint32_t IRQ0_INTF; /*!< Interrupt Force for irq0 */ - __IOM uint32_t IRQ0_INTS; /*!< Interrupt status after masking & forcing for irq0 */ - __IOM uint32_t IRQ1_INTE; /*!< Interrupt Enable for irq1 */ - __IOM uint32_t IRQ1_INTF; /*!< Interrupt Force for irq1 */ - __IOM uint32_t IRQ1_INTS; /*!< Interrupt status after masking & forcing for irq1 */ -} PWM_Type; /*!< Size = 272 (0x110) */ - - - -/* =========================================================================================================================== */ -/* ================ ADC ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief Control and data interface to SAR ADC (ADC) - */ - -typedef struct { /*!< ADC Structure */ - __IOM uint32_t CS; /*!< ADC Control and Status */ - __IOM uint32_t RESULT; /*!< Result of most recent ADC conversion */ - __IOM uint32_t FCS; /*!< FIFO control and status */ - __IOM uint32_t FIFO; /*!< Conversion result FIFO */ - __IOM uint32_t DIV; /*!< Clock divider. If non-zero, CS_START_MANY will start conversions - at regular intervals rather than back-to-back. The divider - is reset when either of these fields are written. Total - period is 1 + INT + FRAC / 256 */ - __IOM uint32_t INTR; /*!< Raw Interrupts */ - __IOM uint32_t INTE; /*!< Interrupt Enable */ - __IOM uint32_t INTF; /*!< Interrupt Force */ - __IOM uint32_t INTS; /*!< Interrupt status after masking & forcing */ -} ADC_Type; /*!< Size = 36 (0x24) */ - - - -/* =========================================================================================================================== */ -/* ================ I2C0 ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief DW_apb_i2c address block - - List of configuration constants for the Synopsys I2C hardware (you may see references to these in I2C register header; these are *fixed* values, set at hardware design time): - - IC_ULTRA_FAST_MODE ................ 0x0 - IC_UFM_TBUF_CNT_DEFAULT ........... 0x8 - IC_UFM_SCL_LOW_COUNT .............. 0x0008 - IC_UFM_SCL_HIGH_COUNT ............. 0x0006 - IC_TX_TL .......................... 0x0 - IC_TX_CMD_BLOCK ................... 0x1 - IC_HAS_DMA ........................ 0x1 - IC_HAS_ASYNC_FIFO ................. 0x0 - IC_SMBUS_ARP ...................... 0x0 - IC_FIRST_DATA_BYTE_STATUS ......... 0x1 - IC_INTR_IO ........................ 0x1 - IC_MASTER_MODE .................... 0x1 - IC_DEFAULT_ACK_GENERAL_CALL ....... 0x1 - IC_INTR_POL ....................... 0x1 - IC_OPTIONAL_SAR ................... 0x0 - IC_DEFAULT_TAR_SLAVE_ADDR ......... 0x055 - IC_DEFAULT_SLAVE_ADDR ............. 0x055 - IC_DEFAULT_HS_SPKLEN .............. 0x1 - IC_FS_SCL_HIGH_COUNT .............. 0x0006 - IC_HS_SCL_LOW_COUNT ............... 0x0008 - IC_DEVICE_ID_VALUE ................ 0x0 - IC_10BITADDR_MASTER ............... 0x0 - IC_CLK_FREQ_OPTIMIZATION .......... 0x0 - IC_DEFAULT_FS_SPKLEN .............. 0x7 - IC_ADD_ENCODED_PARAMS ............. 0x0 - IC_DEFAULT_SDA_HOLD ............... 0x000001 - IC_DEFAULT_SDA_SETUP .............. 0x64 - IC_AVOID_RX_FIFO_FLUSH_ON_TX_ABRT . 0x0 - IC_CLOCK_PERIOD ................... 100 - IC_EMPTYFIFO_HOLD_MASTER_EN ....... 1 - IC_RESTART_EN ..................... 0x1 - IC_TX_CMD_BLOCK_DEFAULT ........... 0x0 - IC_BUS_CLEAR_FEATURE .............. 0x0 - IC_CAP_LOADING .................... 100 - IC_FS_SCL_LOW_COUNT ............... 0x000d - APB_DATA_WIDTH .................... 32 - IC_SDA_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff - IC_SLV_DATA_NACK_ONLY ............. 0x1 - IC_10BITADDR_SLAVE ................ 0x0 - IC_CLK_TYPE ....................... 0x0 - IC_SMBUS_UDID_MSB ................. 0x0 - IC_SMBUS_SUSPEND_ALERT ............ 0x0 - IC_HS_SCL_HIGH_COUNT .............. 0x0006 - IC_SLV_RESTART_DET_EN ............. 0x1 - IC_SMBUS .......................... 0x0 - IC_OPTIONAL_SAR_DEFAULT ........... 0x0 - IC_PERSISTANT_SLV_ADDR_DEFAULT .... 0x0 - IC_USE_COUNTS ..................... 0x0 - IC_RX_BUFFER_DEPTH ................ 16 - IC_SCL_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff - IC_RX_FULL_HLD_BUS_EN ............. 0x1 - IC_SLAVE_DISABLE .................. 0x1 - IC_RX_TL .......................... 0x0 - IC_DEVICE_ID ...................... 0x0 - IC_HC_COUNT_VALUES ................ 0x0 - I2C_DYNAMIC_TAR_UPDATE ............ 0 - IC_SMBUS_CLK_LOW_MEXT_DEFAULT ..... 0xffffffff - IC_SMBUS_CLK_LOW_SEXT_DEFAULT ..... 0xffffffff - IC_HS_MASTER_CODE ................. 0x1 - IC_SMBUS_RST_IDLE_CNT_DEFAULT ..... 0xffff - IC_SMBUS_UDID_LSB_DEFAULT ......... 0xffffffff - IC_SS_SCL_HIGH_COUNT .............. 0x0028 - IC_SS_SCL_LOW_COUNT ............... 0x002f - IC_MAX_SPEED_MODE ................. 0x2 - IC_STAT_FOR_CLK_STRETCH ........... 0x0 - IC_STOP_DET_IF_MASTER_ACTIVE ...... 0x0 - IC_DEFAULT_UFM_SPKLEN ............. 0x1 - IC_TX_BUFFER_DEPTH ................ 16 (I2C0) - */ - -typedef struct { /*!< I2C0 Structure */ - __IOM uint32_t IC_CON; /*!< I2C Control Register. This register can be written only when - the DW_apb_i2c is disabled, which corresponds to the IC_ENABLE[0] - register being set to 0. Writes at other times have no - effect. Read/Write Access: - bit 10 is read only. - bit - 11 is read only - bit 16 is read only - bit 17 is read - only - bits 18 and 19 are read only. */ - __IOM uint32_t IC_TAR; /*!< I2C Target Address Register This register is 12 bits wide, and - bits 31:12 are reserved. This register can be written to - only when IC_ENABLE[0] is set to 0. Note: If the software - or application is aware that the DW_apb_i2c is not using - the TAR address for the pending commands in the Tx FIFO, - then it is possible to update the TAR address even while - the Tx FIFO has entries (IC_STATUS[2]= 0). - It is not - necessary to perform any write to this register if DW_apb_i2c - is enabled as an I2C slave only. */ - __IOM uint32_t IC_SAR; /*!< I2C Slave Address Register */ - __IM uint32_t RESERVED; - __IOM uint32_t IC_DATA_CMD; /*!< I2C Rx/Tx Data Buffer and Command Register; this is the register - the CPU writes to when filling the TX FIFO and the CPU - reads from when retrieving bytes from RX FIFO. The size - of the register changes as follows: Write: - 11 bits when - IC_EMPTYFIFO_HOLD_MASTER_EN=1 - 9 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=0 - Read: - 12 bits when IC_FIRST_DATA_BYTE_STATUS = 1 - 8 - bits when IC_FIRST_DATA_BYTE_STATUS = 0 Note: In order - for the DW_apb_i2c to continue acknowledging reads, a read - command should be written for every byte that is to be - received; otherwise the DW_apb_i2c will stop acknowledging. */ - __IOM uint32_t IC_SS_SCL_HCNT; /*!< Standard Speed I2C Clock SCL High Count Register */ - __IOM uint32_t IC_SS_SCL_LCNT; /*!< Standard Speed I2C Clock SCL Low Count Register */ - __IOM uint32_t IC_FS_SCL_HCNT; /*!< Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register */ - __IOM uint32_t IC_FS_SCL_LCNT; /*!< Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register */ - __IM uint32_t RESERVED1[2]; - __IOM uint32_t IC_INTR_STAT; /*!< I2C Interrupt Status Register Each bit in this register has - a corresponding mask bit in the IC_INTR_MASK register. - These bits are cleared by reading the matching interrupt - clear register. The unmasked raw versions of these bits - are available in the IC_RAW_INTR_STAT register. */ - __IOM uint32_t IC_INTR_MASK; /*!< I2C Interrupt Mask Register. These bits mask their corresponding - interrupt status bits. This register is active low; a value - of 0 masks the interrupt, whereas a value of 1 unmasks - the interrupt. */ - __IOM uint32_t IC_RAW_INTR_STAT; /*!< I2C Raw Interrupt Status Register Unlike the IC_INTR_STAT register, - these bits are not masked so they always show the true - status of the DW_apb_i2c. */ - __IOM uint32_t IC_RX_TL; /*!< I2C Receive FIFO Threshold Register */ - __IOM uint32_t IC_TX_TL; /*!< I2C Transmit FIFO Threshold Register */ - __IOM uint32_t IC_CLR_INTR; /*!< Clear Combined and Individual Interrupt Register */ - __IOM uint32_t IC_CLR_RX_UNDER; /*!< Clear RX_UNDER Interrupt Register */ - __IOM uint32_t IC_CLR_RX_OVER; /*!< Clear RX_OVER Interrupt Register */ - __IOM uint32_t IC_CLR_TX_OVER; /*!< Clear TX_OVER Interrupt Register */ - __IOM uint32_t IC_CLR_RD_REQ; /*!< Clear RD_REQ Interrupt Register */ - __IOM uint32_t IC_CLR_TX_ABRT; /*!< Clear TX_ABRT Interrupt Register */ - __IOM uint32_t IC_CLR_RX_DONE; /*!< Clear RX_DONE Interrupt Register */ - __IOM uint32_t IC_CLR_ACTIVITY; /*!< Clear ACTIVITY Interrupt Register */ - __IOM uint32_t IC_CLR_STOP_DET; /*!< Clear STOP_DET Interrupt Register */ - __IOM uint32_t IC_CLR_START_DET; /*!< Clear START_DET Interrupt Register */ - __IOM uint32_t IC_CLR_GEN_CALL; /*!< Clear GEN_CALL Interrupt Register */ - __IOM uint32_t IC_ENABLE; /*!< I2C Enable Register */ - __IOM uint32_t IC_STATUS; /*!< I2C Status Register This is a read-only register used to indicate - the current transfer status and FIFO status. The status - register may be read at any time. None of the bits in this - register request an interrupt. When the I2C is disabled - by writing 0 in bit 0 of the IC_ENABLE register: - Bits - 1 and 2 are set to 1 - Bits 3 and 10 are set to 0 When - the master or slave state machines goes to idle and ic_en=0: - - Bits 5 and 6 are set to 0 */ - __IOM uint32_t IC_TXFLR; /*!< I2C Transmit FIFO Level Register This register contains the - number of valid data entries in the transmit FIFO buffer. - It is cleared whenever: - The I2C is disabled - There is - a transmit abort - that is, TX_ABRT bit is set in the IC_RAW_INTR_STAT - register - The slave bulk transmit mode is aborted The - register increments whenever data is placed into the transmit - FIFO and decrements when data is taken from the transmit - FIFO. */ - __IOM uint32_t IC_RXFLR; /*!< I2C Receive FIFO Level Register This register contains the number - of valid data entries in the receive FIFO buffer. It is - cleared whenever: - The I2C is disabled - Whenever there - is a transmit abort caused by any of the events tracked - in IC_TX_ABRT_SOURCE The register increments whenever data - is placed into the receive FIFO and decrements when data - is taken from the receive FIFO. */ - __IOM uint32_t IC_SDA_HOLD; /*!< I2C SDA Hold Time Length Register The bits [15:0] of this register - are used to control the hold time of SDA during transmit - in both slave and master mode (after SCL goes from HIGH - to LOW). The bits [23:16] of this register are used to - extend the SDA transition (if any) whenever SCL is HIGH - in the receiver in either master or slave mode. Writes - to this register succeed only when IC_ENABLE[0]=0. The - values in this register are in units of ic_clk period. - The value programmed in IC_SDA_TX_HOLD must be greater - than the minimum hold time in each mode (one cycle in master - mode, seven cycles in slave mode) for the value to be implemented. - The programmed SDA hold time during transmit (IC_SDA_TX_HOLD) - cannot exceed at any time the duration of the low part - of scl. Therefore the programmed value cannot be larger - than N_SCL_LOW-2, where N_SCL_LOW is the duration of the - low part of the scl period measured in ic_clk cycles. */ - __IOM uint32_t IC_TX_ABRT_SOURCE; /*!< I2C Transmit Abort Source Register This register has 32 bits - that indicate the source of the TX_ABRT bit. Except for - Bit 9, this register is cleared whenever the IC_CLR_TX_ABRT - register or the IC_CLR_INTR register is read. To clear - Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed - first; RESTART must be enabled (IC_CON[5]=1), the SPECIAL - bit must be cleared (IC_TAR[11]), or the GC_OR_START bit - must be cleared (IC_TAR[10]). Once the source of the ABRT_SBYTE_NORSTRT - is fixed, then this bit can be cleared in the same manner - as other bits in this register. If the source of the ABRT_SBYTE_NORSTRT - is not fixed before attempting to clear this bit, Bit 9 - clears for one cycle and is then re-asserted. */ - __IOM uint32_t IC_SLV_DATA_NACK_ONLY; /*!< Generate Slave Data NACK Register The register is used to generate - a NACK for the data part of a transfer when DW_apb_i2c - is acting as a slave-receiver. This register only exists - when the IC_SLV_DATA_NACK_ONLY parameter is set to 1. When - this parameter disabled, this register does not exist and - writing to the register's address has no effect. A write - can occur on this register if both of the following conditions - are met: - DW_apb_i2c is disabled (IC_ENABLE[0] = 0) - - Slave part is inactive (IC_STATUS[6] = 0) Note: The IC_STATUS[6] - is a register read-back location for the internal slv_activity - signal; the user should poll this before writing the ic_slv_data_nack_onl - bit. */ - __IOM uint32_t IC_DMA_CR; /*!< DMA Control Register The register is used to enable the DMA - Controller interface operation. There is a separate bit - for transmit and receive. This can be programmed regardless - of the state of IC_ENABLE. */ - __IOM uint32_t IC_DMA_TDLR; /*!< DMA Transmit Data Level Register */ - __IOM uint32_t IC_DMA_RDLR; /*!< I2C Receive Data Level Register */ - __IOM uint32_t IC_SDA_SETUP; /*!< I2C SDA Setup Register This register controls the amount of - time delay (in terms of number of ic_clk clock periods) - introduced in the rising edge of SCL - relative to SDA - changing - when DW_apb_i2c services a read request in a - slave-transmitter operation. The relevant I2C requirement - is tSU:DAT (note 4) as detailed in the I2C Bus Specification. - This register must be programmed with a value equal to - or greater than 2. Writes to this register succeed only - when IC_ENABLE[0] = 0. Note: The length of setup time is - calculated using [(IC_SDA_SETUP - 1) * (ic_clk_period)], - so if the user requires 10 ic_clk periods of setup time, - they should program a value of 11. The IC_SDA_SETUP register - is only used by the DW_apb_i2c when operating as a slave - transmitter. */ - __IOM uint32_t IC_ACK_GENERAL_CALL; /*!< I2C ACK General Call Register The register controls whether - DW_apb_i2c responds with a ACK or NACK when it receives - an I2C General Call address. This register is applicable - only when the DW_apb_i2c is in slave mode. */ - __IOM uint32_t IC_ENABLE_STATUS; /*!< I2C Enable Status Register The register is used to report the - DW_apb_i2c hardware status when the IC_ENABLE[0] register - is set from 1 to 0; that is, when DW_apb_i2c is disabled. - If IC_ENABLE[0] has been set to 1, bits 2:1 are forced - to 0, and bit 0 is forced to 1. If IC_ENABLE[0] has been - set to 0, bits 2:1 is only be valid as soon as bit 0 is - read as '0'. Note: When IC_ENABLE[0] has been set to 0, - a delay occurs for bit 0 to be read as 0 because disabling - the DW_apb_i2c depends on I2C bus activities. */ - __IOM uint32_t IC_FS_SPKLEN; /*!< I2C SS, FS or FM+ spike suppression limit This register is used - to store the duration, measured in ic_clk cycles, of the - longest spike that is filtered out by the spike suppression - logic when the component is operating in SS, FS or FM+ - modes. The relevant I2C requirement is tSP (table 4) as - detailed in the I2C Bus Specification. This register must - be programmed with a minimum value of 1. */ - __IM uint32_t RESERVED2; - __IOM uint32_t IC_CLR_RESTART_DET; /*!< Clear RESTART_DET Interrupt Register */ - __IM uint32_t RESERVED3[18]; - __IOM uint32_t IC_COMP_PARAM_1; /*!< Component Parameter Register 1 Note This register is not implemented - and therefore reads as 0. If it was implemented it would - be a constant read-only register that contains encoded - information about the component's parameter settings. Fields - shown below are the settings for those parameters */ - __IOM uint32_t IC_COMP_VERSION; /*!< I2C Component Version Register */ - __IOM uint32_t IC_COMP_TYPE; /*!< I2C Component Type Register */ -} I2C0_Type; /*!< Size = 256 (0x100) */ - - - -/* =========================================================================================================================== */ -/* ================ SPI0 ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief SPI0 (SPI0) - */ - -typedef struct { /*!< SPI0 Structure */ - __IOM uint32_t SSPCR0; /*!< Control register 0, SSPCR0 on page 3-4 */ - __IOM uint32_t SSPCR1; /*!< Control register 1, SSPCR1 on page 3-5 */ - __IOM uint32_t SSPDR; /*!< Data register, SSPDR on page 3-6 */ - __IOM uint32_t SSPSR; /*!< Status register, SSPSR on page 3-7 */ - __IOM uint32_t SSPCPSR; /*!< Clock prescale register, SSPCPSR on page 3-8 */ - __IOM uint32_t SSPIMSC; /*!< Interrupt mask set or clear register, SSPIMSC on page 3-9 */ - __IOM uint32_t SSPRIS; /*!< Raw interrupt status register, SSPRIS on page 3-10 */ - __IOM uint32_t SSPMIS; /*!< Masked interrupt status register, SSPMIS on page 3-11 */ - __IOM uint32_t SSPICR; /*!< Interrupt clear register, SSPICR on page 3-11 */ - __IOM uint32_t SSPDMACR; /*!< DMA control register, SSPDMACR on page 3-12 */ - __IM uint32_t RESERVED[1006]; - __IOM uint32_t SSPPERIPHID0; /*!< Peripheral identification registers, SSPPeriphID0-3 on page - 3-13 */ - __IOM uint32_t SSPPERIPHID1; /*!< Peripheral identification registers, SSPPeriphID0-3 on page - 3-13 */ - __IOM uint32_t SSPPERIPHID2; /*!< Peripheral identification registers, SSPPeriphID0-3 on page - 3-13 */ - __IOM uint32_t SSPPERIPHID3; /*!< Peripheral identification registers, SSPPeriphID0-3 on page - 3-13 */ - __IOM uint32_t SSPPCELLID0; /*!< PrimeCell identification registers, SSPPCellID0-3 on page 3-16 */ - __IOM uint32_t SSPPCELLID1; /*!< PrimeCell identification registers, SSPPCellID0-3 on page 3-16 */ - __IOM uint32_t SSPPCELLID2; /*!< PrimeCell identification registers, SSPPCellID0-3 on page 3-16 */ - __IOM uint32_t SSPPCELLID3; /*!< PrimeCell identification registers, SSPPCellID0-3 on page 3-16 */ -} SPI0_Type; /*!< Size = 4096 (0x1000) */ - - - -/* =========================================================================================================================== */ -/* ================ PIO0 ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief Programmable IO block (PIO0) - */ - -typedef struct { /*!< PIO0 Structure */ - __IOM uint32_t CTRL; /*!< PIO control register */ - __IOM uint32_t FSTAT; /*!< FIFO status register */ - __IOM uint32_t FDEBUG; /*!< FIFO debug register */ - __IOM uint32_t FLEVEL; /*!< FIFO levels */ - __IOM uint32_t TXF0; /*!< Direct write access to the TX FIFO for this state machine. Each - write pushes one word to the FIFO. Attempting to write - to a full FIFO has no effect on the FIFO state or contents, - and sets the sticky FDEBUG_TXOVER error flag for this FIFO. */ - __IOM uint32_t TXF1; /*!< Direct write access to the TX FIFO for this state machine. Each - write pushes one word to the FIFO. Attempting to write - to a full FIFO has no effect on the FIFO state or contents, - and sets the sticky FDEBUG_TXOVER error flag for this FIFO. */ - __IOM uint32_t TXF2; /*!< Direct write access to the TX FIFO for this state machine. Each - write pushes one word to the FIFO. Attempting to write - to a full FIFO has no effect on the FIFO state or contents, - and sets the sticky FDEBUG_TXOVER error flag for this FIFO. */ - __IOM uint32_t TXF3; /*!< Direct write access to the TX FIFO for this state machine. Each - write pushes one word to the FIFO. Attempting to write - to a full FIFO has no effect on the FIFO state or contents, - and sets the sticky FDEBUG_TXOVER error flag for this FIFO. */ - __IOM uint32_t RXF0; /*!< Direct read access to the RX FIFO for this state machine. Each - read pops one word from the FIFO. Attempting to read from - an empty FIFO has no effect on the FIFO state, and sets - the sticky FDEBUG_RXUNDER error flag for this FIFO. The - data returned to the system on a read from an empty FIFO - is undefined. */ - __IOM uint32_t RXF1; /*!< Direct read access to the RX FIFO for this state machine. Each - read pops one word from the FIFO. Attempting to read from - an empty FIFO has no effect on the FIFO state, and sets - the sticky FDEBUG_RXUNDER error flag for this FIFO. The - data returned to the system on a read from an empty FIFO - is undefined. */ - __IOM uint32_t RXF2; /*!< Direct read access to the RX FIFO for this state machine. Each - read pops one word from the FIFO. Attempting to read from - an empty FIFO has no effect on the FIFO state, and sets - the sticky FDEBUG_RXUNDER error flag for this FIFO. The - data returned to the system on a read from an empty FIFO - is undefined. */ - __IOM uint32_t RXF3; /*!< Direct read access to the RX FIFO for this state machine. Each - read pops one word from the FIFO. Attempting to read from - an empty FIFO has no effect on the FIFO state, and sets - the sticky FDEBUG_RXUNDER error flag for this FIFO. The - data returned to the system on a read from an empty FIFO - is undefined. */ - __IOM uint32_t IRQ; /*!< State machine IRQ flags register. Write 1 to clear. There are - eight state machine IRQ flags, which can be set, cleared, - and waited on by the state machines. There's no fixed association - between flags and state machines -- any state machine can - use any flag. Any of the eight flags can be used for timing - synchronisation between state machines, using IRQ and WAIT - instructions. Any combination of the eight flags can also - routed out to either of the two system-level interrupt - requests, alongside FIFO status interrupts -- see e.g. - IRQ0_INTE. */ - __IOM uint32_t IRQ_FORCE; /*!< Writing a 1 to each of these bits will forcibly assert the corresponding - IRQ. Note this is different to the INTF register: writing - here affects PIO internal state. INTF just asserts the - processor-facing IRQ signal for testing ISRs, and is not - visible to the state machines. */ - __IOM uint32_t INPUT_SYNC_BYPASS; /*!< There is a 2-flipflop synchronizer on each GPIO input, which - protects PIO logic from metastabilities. This increases - input delay, and for fast synchronous IO (e.g. SPI) these - synchronizers may need to be bypassed. Each bit in this - register corresponds to one GPIO. 0 -> input is synchronized - (default) 1 -> synchronizer is bypassed If in doubt, leave - this register as all zeroes. */ - __IOM uint32_t DBG_PADOUT; /*!< Read to sample the pad output values PIO is currently driving - to the GPIOs. On RP2040 there are 30 GPIOs, so the two - most significant bits are hardwired to 0. */ - __IOM uint32_t DBG_PADOE; /*!< Read to sample the pad output enables (direction) PIO is currently - driving to the GPIOs. On RP2040 there are 30 GPIOs, so - the two most significant bits are hardwired to 0. */ - __IOM uint32_t DBG_CFGINFO; /*!< The PIO hardware has some free parameters that may vary between - chip products. These should be provided in the chip datasheet, - but are also exposed here. */ - __IOM uint32_t INSTR_MEM0; /*!< Write-only access to instruction memory location 0 */ - __IOM uint32_t INSTR_MEM1; /*!< Write-only access to instruction memory location 1 */ - __IOM uint32_t INSTR_MEM2; /*!< Write-only access to instruction memory location 2 */ - __IOM uint32_t INSTR_MEM3; /*!< Write-only access to instruction memory location 3 */ - __IOM uint32_t INSTR_MEM4; /*!< Write-only access to instruction memory location 4 */ - __IOM uint32_t INSTR_MEM5; /*!< Write-only access to instruction memory location 5 */ - __IOM uint32_t INSTR_MEM6; /*!< Write-only access to instruction memory location 6 */ - __IOM uint32_t INSTR_MEM7; /*!< Write-only access to instruction memory location 7 */ - __IOM uint32_t INSTR_MEM8; /*!< Write-only access to instruction memory location 8 */ - __IOM uint32_t INSTR_MEM9; /*!< Write-only access to instruction memory location 9 */ - __IOM uint32_t INSTR_MEM10; /*!< Write-only access to instruction memory location 10 */ - __IOM uint32_t INSTR_MEM11; /*!< Write-only access to instruction memory location 11 */ - __IOM uint32_t INSTR_MEM12; /*!< Write-only access to instruction memory location 12 */ - __IOM uint32_t INSTR_MEM13; /*!< Write-only access to instruction memory location 13 */ - __IOM uint32_t INSTR_MEM14; /*!< Write-only access to instruction memory location 14 */ - __IOM uint32_t INSTR_MEM15; /*!< Write-only access to instruction memory location 15 */ - __IOM uint32_t INSTR_MEM16; /*!< Write-only access to instruction memory location 16 */ - __IOM uint32_t INSTR_MEM17; /*!< Write-only access to instruction memory location 17 */ - __IOM uint32_t INSTR_MEM18; /*!< Write-only access to instruction memory location 18 */ - __IOM uint32_t INSTR_MEM19; /*!< Write-only access to instruction memory location 19 */ - __IOM uint32_t INSTR_MEM20; /*!< Write-only access to instruction memory location 20 */ - __IOM uint32_t INSTR_MEM21; /*!< Write-only access to instruction memory location 21 */ - __IOM uint32_t INSTR_MEM22; /*!< Write-only access to instruction memory location 22 */ - __IOM uint32_t INSTR_MEM23; /*!< Write-only access to instruction memory location 23 */ - __IOM uint32_t INSTR_MEM24; /*!< Write-only access to instruction memory location 24 */ - __IOM uint32_t INSTR_MEM25; /*!< Write-only access to instruction memory location 25 */ - __IOM uint32_t INSTR_MEM26; /*!< Write-only access to instruction memory location 26 */ - __IOM uint32_t INSTR_MEM27; /*!< Write-only access to instruction memory location 27 */ - __IOM uint32_t INSTR_MEM28; /*!< Write-only access to instruction memory location 28 */ - __IOM uint32_t INSTR_MEM29; /*!< Write-only access to instruction memory location 29 */ - __IOM uint32_t INSTR_MEM30; /*!< Write-only access to instruction memory location 30 */ - __IOM uint32_t INSTR_MEM31; /*!< Write-only access to instruction memory location 31 */ - __IOM uint32_t SM0_CLKDIV; /*!< Clock divisor register for state machine 0 Frequency = clock - freq / (CLKDIV_INT + CLKDIV_FRAC / 256) */ - __IOM uint32_t SM0_EXECCTRL; /*!< Execution/behavioural settings for state machine 0 */ - __IOM uint32_t SM0_SHIFTCTRL; /*!< Control behaviour of the input/output shift registers for state - machine 0 */ - __IOM uint32_t SM0_ADDR; /*!< Current instruction address of state machine 0 */ - __IOM uint32_t SM0_INSTR; /*!< Read to see the instruction currently addressed by state machine - 0's program counter Write to execute an instruction immediately - (including jumps) and then resume execution. */ - __IOM uint32_t SM0_PINCTRL; /*!< State machine pin control */ - __IOM uint32_t SM1_CLKDIV; /*!< Clock divisor register for state machine 1 Frequency = clock - freq / (CLKDIV_INT + CLKDIV_FRAC / 256) */ - __IOM uint32_t SM1_EXECCTRL; /*!< Execution/behavioural settings for state machine 1 */ - __IOM uint32_t SM1_SHIFTCTRL; /*!< Control behaviour of the input/output shift registers for state - machine 1 */ - __IOM uint32_t SM1_ADDR; /*!< Current instruction address of state machine 1 */ - __IOM uint32_t SM1_INSTR; /*!< Read to see the instruction currently addressed by state machine - 1's program counter Write to execute an instruction immediately - (including jumps) and then resume execution. */ - __IOM uint32_t SM1_PINCTRL; /*!< State machine pin control */ - __IOM uint32_t SM2_CLKDIV; /*!< Clock divisor register for state machine 2 Frequency = clock - freq / (CLKDIV_INT + CLKDIV_FRAC / 256) */ - __IOM uint32_t SM2_EXECCTRL; /*!< Execution/behavioural settings for state machine 2 */ - __IOM uint32_t SM2_SHIFTCTRL; /*!< Control behaviour of the input/output shift registers for state - machine 2 */ - __IOM uint32_t SM2_ADDR; /*!< Current instruction address of state machine 2 */ - __IOM uint32_t SM2_INSTR; /*!< Read to see the instruction currently addressed by state machine - 2's program counter Write to execute an instruction immediately - (including jumps) and then resume execution. */ - __IOM uint32_t SM2_PINCTRL; /*!< State machine pin control */ - __IOM uint32_t SM3_CLKDIV; /*!< Clock divisor register for state machine 3 Frequency = clock - freq / (CLKDIV_INT + CLKDIV_FRAC / 256) */ - __IOM uint32_t SM3_EXECCTRL; /*!< Execution/behavioural settings for state machine 3 */ - __IOM uint32_t SM3_SHIFTCTRL; /*!< Control behaviour of the input/output shift registers for state - machine 3 */ - __IOM uint32_t SM3_ADDR; /*!< Current instruction address of state machine 3 */ - __IOM uint32_t SM3_INSTR; /*!< Read to see the instruction currently addressed by state machine - 3's program counter Write to execute an instruction immediately - (including jumps) and then resume execution. */ - __IOM uint32_t SM3_PINCTRL; /*!< State machine pin control */ - __IOM uint32_t RXF0_PUTGET0; /*!< Direct read/write access to entry 0 of SM0's RX FIFO, if SHIFTCTRL_FJOIN_RX_PU - xor SHIFTCTRL_FJOIN_RX_GET is set. */ - __IOM uint32_t RXF0_PUTGET1; /*!< Direct read/write access to entry 1 of SM0's RX FIFO, if SHIFTCTRL_FJOIN_RX_PU - xor SHIFTCTRL_FJOIN_RX_GET is set. */ - __IOM uint32_t RXF0_PUTGET2; /*!< Direct read/write access to entry 2 of SM0's RX FIFO, if SHIFTCTRL_FJOIN_RX_PU - xor SHIFTCTRL_FJOIN_RX_GET is set. */ - __IOM uint32_t RXF0_PUTGET3; /*!< Direct read/write access to entry 3 of SM0's RX FIFO, if SHIFTCTRL_FJOIN_RX_PU - xor SHIFTCTRL_FJOIN_RX_GET is set. */ - __IOM uint32_t RXF1_PUTGET0; /*!< Direct read/write access to entry 0 of SM1's RX FIFO, if SHIFTCTRL_FJOIN_RX_PU - xor SHIFTCTRL_FJOIN_RX_GET is set. */ - __IOM uint32_t RXF1_PUTGET1; /*!< Direct read/write access to entry 1 of SM1's RX FIFO, if SHIFTCTRL_FJOIN_RX_PU - xor SHIFTCTRL_FJOIN_RX_GET is set. */ - __IOM uint32_t RXF1_PUTGET2; /*!< Direct read/write access to entry 2 of SM1's RX FIFO, if SHIFTCTRL_FJOIN_RX_PU - xor SHIFTCTRL_FJOIN_RX_GET is set. */ - __IOM uint32_t RXF1_PUTGET3; /*!< Direct read/write access to entry 3 of SM1's RX FIFO, if SHIFTCTRL_FJOIN_RX_PU - xor SHIFTCTRL_FJOIN_RX_GET is set. */ - __IOM uint32_t RXF2_PUTGET0; /*!< Direct read/write access to entry 0 of SM2's RX FIFO, if SHIFTCTRL_FJOIN_RX_PU - xor SHIFTCTRL_FJOIN_RX_GET is set. */ - __IOM uint32_t RXF2_PUTGET1; /*!< Direct read/write access to entry 1 of SM2's RX FIFO, if SHIFTCTRL_FJOIN_RX_PU - xor SHIFTCTRL_FJOIN_RX_GET is set. */ - __IOM uint32_t RXF2_PUTGET2; /*!< Direct read/write access to entry 2 of SM2's RX FIFO, if SHIFTCTRL_FJOIN_RX_PU - xor SHIFTCTRL_FJOIN_RX_GET is set. */ - __IOM uint32_t RXF2_PUTGET3; /*!< Direct read/write access to entry 3 of SM2's RX FIFO, if SHIFTCTRL_FJOIN_RX_PU - xor SHIFTCTRL_FJOIN_RX_GET is set. */ - __IOM uint32_t RXF3_PUTGET0; /*!< Direct read/write access to entry 0 of SM3's RX FIFO, if SHIFTCTRL_FJOIN_RX_PU - xor SHIFTCTRL_FJOIN_RX_GET is set. */ - __IOM uint32_t RXF3_PUTGET1; /*!< Direct read/write access to entry 1 of SM3's RX FIFO, if SHIFTCTRL_FJOIN_RX_PU - xor SHIFTCTRL_FJOIN_RX_GET is set. */ - __IOM uint32_t RXF3_PUTGET2; /*!< Direct read/write access to entry 2 of SM3's RX FIFO, if SHIFTCTRL_FJOIN_RX_PU - xor SHIFTCTRL_FJOIN_RX_GET is set. */ - __IOM uint32_t RXF3_PUTGET3; /*!< Direct read/write access to entry 3 of SM3's RX FIFO, if SHIFTCTRL_FJOIN_RX_PU - xor SHIFTCTRL_FJOIN_RX_GET is set. */ - __IOM uint32_t GPIOBASE; /*!< Relocate GPIO 0 (from PIO's point of view) in the system GPIO - numbering, to access more than 32 GPIOs from PIO. Only - the values 0 and 16 are supported (only bit 4 is writable). */ - __IOM uint32_t INTR; /*!< Raw Interrupts */ - __IOM uint32_t IRQ0_INTE; /*!< Interrupt Enable for irq0 */ - __IOM uint32_t IRQ0_INTF; /*!< Interrupt Force for irq0 */ - __IOM uint32_t IRQ0_INTS; /*!< Interrupt status after masking & forcing for irq0 */ - __IOM uint32_t IRQ1_INTE; /*!< Interrupt Enable for irq1 */ - __IOM uint32_t IRQ1_INTF; /*!< Interrupt Force for irq1 */ - __IOM uint32_t IRQ1_INTS; /*!< Interrupt status after masking & forcing for irq1 */ -} PIO0_Type; /*!< Size = 392 (0x188) */ - - - -/* =========================================================================================================================== */ -/* ================ BUSCTRL ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief Register block for busfabric control signals and performance counters (BUSCTRL) - */ - -typedef struct { /*!< BUSCTRL Structure */ - __IOM uint32_t BUS_PRIORITY; /*!< Set the priority of each master for bus arbitration. */ - __IOM uint32_t BUS_PRIORITY_ACK; /*!< Bus priority acknowledge */ - __IOM uint32_t PERFCTR_EN; /*!< Enable the performance counters. If 0, the performance counters - do not increment. This can be used to precisely start/stop - event sampling around the profiled section of code. The - performance counters are initially disabled, to save energy. */ - __IOM uint32_t PERFCTR0; /*!< Bus fabric performance counter 0 */ - __IOM uint32_t PERFSEL0; /*!< Bus fabric performance event select for PERFCTR0 */ - __IOM uint32_t PERFCTR1; /*!< Bus fabric performance counter 1 */ - __IOM uint32_t PERFSEL1; /*!< Bus fabric performance event select for PERFCTR1 */ - __IOM uint32_t PERFCTR2; /*!< Bus fabric performance counter 2 */ - __IOM uint32_t PERFSEL2; /*!< Bus fabric performance event select for PERFCTR2 */ - __IOM uint32_t PERFCTR3; /*!< Bus fabric performance counter 3 */ - __IOM uint32_t PERFSEL3; /*!< Bus fabric performance event select for PERFCTR3 */ -} BUSCTRL_Type; /*!< Size = 44 (0x2c) */ - - - -/* =========================================================================================================================== */ -/* ================ SIO ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief Single-cycle IO block - Provides core-local and inter-core hardware for the two processors, with single-cycle access. (SIO) - */ - -typedef struct { /*!< SIO Structure */ - __IOM uint32_t CPUID; /*!< Processor core identifier */ - __IOM uint32_t GPIO_IN; /*!< Input value for GPIO0...31. In the Non-secure SIO, Secure-only - GPIOs (as per ACCESSCTRL) appear as zero. */ - __IOM uint32_t GPIO_HI_IN; /*!< Input value on GPIO32...47, QSPI IOs and USB pins In the Non-secure - SIO, Secure-only GPIOs (as per ACCESSCTRL) appear as zero. */ - __IM uint32_t RESERVED; - __IOM uint32_t GPIO_OUT; /*!< GPIO0...31 output value */ - __IOM uint32_t GPIO_HI_OUT; /*!< Output value for GPIO32...47, QSPI IOs and USB pins. Write to - set output level (1/0 -> high/low). Reading back gives - the last value written, NOT the input value from the pins. - If core 0 and core 1 both write to GPIO_HI_OUT simultaneously - (or to a SET/CLR/XOR alias), the result is as though the - write from core 0 took place first, and the write from - core 1 was then applied to that intermediate result. In - the Non-secure SIO, Secure-only GPIOs (as per ACCESSCTRL) - ignore writes, and their output status reads back as zero. - This is also true for SET/CLR/XOR aliases of this register. */ - __IOM uint32_t GPIO_OUT_SET; /*!< GPIO0...31 output value set */ - __IOM uint32_t GPIO_HI_OUT_SET; /*!< Output value set for GPIO32..47, QSPI IOs and USB pins. Perform - an atomic bit-set on GPIO_HI_OUT, i.e. `GPIO_HI_OUT |= - wdata` */ - __IOM uint32_t GPIO_OUT_CLR; /*!< GPIO0...31 output value clear */ - __IOM uint32_t GPIO_HI_OUT_CLR; /*!< Output value clear for GPIO32..47, QSPI IOs and USB pins. Perform - an atomic bit-clear on GPIO_HI_OUT, i.e. `GPIO_HI_OUT &= - ~wdata` */ - __IOM uint32_t GPIO_OUT_XOR; /*!< GPIO0...31 output value XOR */ - __IOM uint32_t GPIO_HI_OUT_XOR; /*!< Output value XOR for GPIO32..47, QSPI IOs and USB pins. Perform - an atomic bitwise XOR on GPIO_HI_OUT, i.e. `GPIO_HI_OUT - ^= wdata` */ - __IOM uint32_t GPIO_OE; /*!< GPIO0...31 output enable */ - __IOM uint32_t GPIO_HI_OE; /*!< Output enable value for GPIO32...47, QSPI IOs and USB pins. - Write output enable (1/0 -> output/input). Reading back - gives the last value written. If core 0 and core 1 both - write to GPIO_HI_OE simultaneously (or to a SET/CLR/XOR - alias), the result is as though the write from core 0 took - place first, and the write from core 1 was then applied - to that intermediate result. In the Non-secure SIO, Secure-only - GPIOs (as per ACCESSCTRL) ignore writes, and their output - status reads back as zero. This is also true for SET/CLR/XOR - aliases of this register. */ - __IOM uint32_t GPIO_OE_SET; /*!< GPIO0...31 output enable set */ - __IOM uint32_t GPIO_HI_OE_SET; /*!< Output enable set for GPIO32...47, QSPI IOs and USB pins. Perform - an atomic bit-set on GPIO_HI_OE, i.e. `GPIO_HI_OE |= wdata` */ - __IOM uint32_t GPIO_OE_CLR; /*!< GPIO0...31 output enable clear */ - __IOM uint32_t GPIO_HI_OE_CLR; /*!< Output enable clear for GPIO32...47, QSPI IOs and USB pins. - Perform an atomic bit-clear on GPIO_HI_OE, i.e. `GPIO_HI_OE - &= ~wdata` */ - __IOM uint32_t GPIO_OE_XOR; /*!< GPIO0...31 output enable XOR */ - __IOM uint32_t GPIO_HI_OE_XOR; /*!< Output enable XOR for GPIO32...47, QSPI IOs and USB pins. Perform - an atomic bitwise XOR on GPIO_HI_OE, i.e. `GPIO_HI_OE ^= - wdata` */ - __IOM uint32_t FIFO_ST; /*!< Status register for inter-core FIFOs (mailboxes). There is one - FIFO in the core 0 -> core 1 direction, and one core 1 - -> core 0. Both are 32 bits wide and 8 words deep. Core - 0 can see the read side of the 1->0 FIFO (RX), and the - write side of 0->1 FIFO (TX). Core 1 can see the read side - of the 0->1 FIFO (RX), and the write side of 1->0 FIFO - (TX). The SIO IRQ for each core is the logical OR of the - VLD, WOF and ROE fields of its FIFO_ST register. */ - __IOM uint32_t FIFO_WR; /*!< Write access to this core's TX FIFO */ - __IOM uint32_t FIFO_RD; /*!< Read access to this core's RX FIFO */ - __IOM uint32_t SPINLOCK_ST; /*!< Spinlock state A bitmap containing the state of all 32 spinlocks - (1=locked). Mainly intended for debugging. */ - __IM uint32_t RESERVED1[8]; - __IOM uint32_t INTERP0_ACCUM0; /*!< Read/write access to accumulator 0 */ - __IOM uint32_t INTERP0_ACCUM1; /*!< Read/write access to accumulator 1 */ - __IOM uint32_t INTERP0_BASE0; /*!< Read/write access to BASE0 register. */ - __IOM uint32_t INTERP0_BASE1; /*!< Read/write access to BASE1 register. */ - __IOM uint32_t INTERP0_BASE2; /*!< Read/write access to BASE2 register. */ - __IOM uint32_t INTERP0_POP_LANE0; /*!< Read LANE0 result, and simultaneously write lane results to - both accumulators (POP). */ - __IOM uint32_t INTERP0_POP_LANE1; /*!< Read LANE1 result, and simultaneously write lane results to - both accumulators (POP). */ - __IOM uint32_t INTERP0_POP_FULL; /*!< Read FULL result, and simultaneously write lane results to both - accumulators (POP). */ - __IOM uint32_t INTERP0_PEEK_LANE0; /*!< Read LANE0 result, without altering any internal state (PEEK). */ - __IOM uint32_t INTERP0_PEEK_LANE1; /*!< Read LANE1 result, without altering any internal state (PEEK). */ - __IOM uint32_t INTERP0_PEEK_FULL; /*!< Read FULL result, without altering any internal state (PEEK). */ - __IOM uint32_t INTERP0_CTRL_LANE0; /*!< Control register for lane 0 */ - __IOM uint32_t INTERP0_CTRL_LANE1; /*!< Control register for lane 1 */ - __IOM uint32_t INTERP0_ACCUM0_ADD; /*!< Values written here are atomically added to ACCUM0 Reading yields - lane 0's raw shift and mask value (BASE0 not added). */ - __IOM uint32_t INTERP0_ACCUM1_ADD; /*!< Values written here are atomically added to ACCUM1 Reading yields - lane 1's raw shift and mask value (BASE1 not added). */ - __IOM uint32_t INTERP0_BASE_1AND0; /*!< On write, the lower 16 bits go to BASE0, upper bits to BASE1 - simultaneously. Each half is sign-extended to 32 bits if - that lane's SIGNED flag is set. */ - __IOM uint32_t INTERP1_ACCUM0; /*!< Read/write access to accumulator 0 */ - __IOM uint32_t INTERP1_ACCUM1; /*!< Read/write access to accumulator 1 */ - __IOM uint32_t INTERP1_BASE0; /*!< Read/write access to BASE0 register. */ - __IOM uint32_t INTERP1_BASE1; /*!< Read/write access to BASE1 register. */ - __IOM uint32_t INTERP1_BASE2; /*!< Read/write access to BASE2 register. */ - __IOM uint32_t INTERP1_POP_LANE0; /*!< Read LANE0 result, and simultaneously write lane results to - both accumulators (POP). */ - __IOM uint32_t INTERP1_POP_LANE1; /*!< Read LANE1 result, and simultaneously write lane results to - both accumulators (POP). */ - __IOM uint32_t INTERP1_POP_FULL; /*!< Read FULL result, and simultaneously write lane results to both - accumulators (POP). */ - __IOM uint32_t INTERP1_PEEK_LANE0; /*!< Read LANE0 result, without altering any internal state (PEEK). */ - __IOM uint32_t INTERP1_PEEK_LANE1; /*!< Read LANE1 result, without altering any internal state (PEEK). */ - __IOM uint32_t INTERP1_PEEK_FULL; /*!< Read FULL result, without altering any internal state (PEEK). */ - __IOM uint32_t INTERP1_CTRL_LANE0; /*!< Control register for lane 0 */ - __IOM uint32_t INTERP1_CTRL_LANE1; /*!< Control register for lane 1 */ - __IOM uint32_t INTERP1_ACCUM0_ADD; /*!< Values written here are atomically added to ACCUM0 Reading yields - lane 0's raw shift and mask value (BASE0 not added). */ - __IOM uint32_t INTERP1_ACCUM1_ADD; /*!< Values written here are atomically added to ACCUM1 Reading yields - lane 1's raw shift and mask value (BASE1 not added). */ - __IOM uint32_t INTERP1_BASE_1AND0; /*!< On write, the lower 16 bits go to BASE0, upper bits to BASE1 - simultaneously. Each half is sign-extended to 32 bits if - that lane's SIGNED flag is set. */ - __IOM uint32_t SPINLOCK0; /*!< Reading from a spinlock address will: - Return 0 if lock is - already locked - Otherwise return nonzero, and simultaneously - claim the lock Writing (any value) releases the lock. If - core 0 and core 1 attempt to claim the same lock simultaneously, - core 0 wins. The value returned on success is 0x1 << lock - number. */ - __IOM uint32_t SPINLOCK1; /*!< Reading from a spinlock address will: - Return 0 if lock is - already locked - Otherwise return nonzero, and simultaneously - claim the lock Writing (any value) releases the lock. If - core 0 and core 1 attempt to claim the same lock simultaneously, - core 0 wins. The value returned on success is 0x1 << lock - number. */ - __IOM uint32_t SPINLOCK2; /*!< Reading from a spinlock address will: - Return 0 if lock is - already locked - Otherwise return nonzero, and simultaneously - claim the lock Writing (any value) releases the lock. If - core 0 and core 1 attempt to claim the same lock simultaneously, - core 0 wins. The value returned on success is 0x1 << lock - number. */ - __IOM uint32_t SPINLOCK3; /*!< Reading from a spinlock address will: - Return 0 if lock is - already locked - Otherwise return nonzero, and simultaneously - claim the lock Writing (any value) releases the lock. If - core 0 and core 1 attempt to claim the same lock simultaneously, - core 0 wins. The value returned on success is 0x1 << lock - number. */ - __IOM uint32_t SPINLOCK4; /*!< Reading from a spinlock address will: - Return 0 if lock is - already locked - Otherwise return nonzero, and simultaneously - claim the lock Writing (any value) releases the lock. If - core 0 and core 1 attempt to claim the same lock simultaneously, - core 0 wins. The value returned on success is 0x1 << lock - number. */ - __IOM uint32_t SPINLOCK5; /*!< Reading from a spinlock address will: - Return 0 if lock is - already locked - Otherwise return nonzero, and simultaneously - claim the lock Writing (any value) releases the lock. If - core 0 and core 1 attempt to claim the same lock simultaneously, - core 0 wins. The value returned on success is 0x1 << lock - number. */ - __IOM uint32_t SPINLOCK6; /*!< Reading from a spinlock address will: - Return 0 if lock is - already locked - Otherwise return nonzero, and simultaneously - claim the lock Writing (any value) releases the lock. If - core 0 and core 1 attempt to claim the same lock simultaneously, - core 0 wins. The value returned on success is 0x1 << lock - number. */ - __IOM uint32_t SPINLOCK7; /*!< Reading from a spinlock address will: - Return 0 if lock is - already locked - Otherwise return nonzero, and simultaneously - claim the lock Writing (any value) releases the lock. If - core 0 and core 1 attempt to claim the same lock simultaneously, - core 0 wins. The value returned on success is 0x1 << lock - number. */ - __IOM uint32_t SPINLOCK8; /*!< Reading from a spinlock address will: - Return 0 if lock is - already locked - Otherwise return nonzero, and simultaneously - claim the lock Writing (any value) releases the lock. If - core 0 and core 1 attempt to claim the same lock simultaneously, - core 0 wins. The value returned on success is 0x1 << lock - number. */ - __IOM uint32_t SPINLOCK9; /*!< Reading from a spinlock address will: - Return 0 if lock is - already locked - Otherwise return nonzero, and simultaneously - claim the lock Writing (any value) releases the lock. If - core 0 and core 1 attempt to claim the same lock simultaneously, - core 0 wins. The value returned on success is 0x1 << lock - number. */ - __IOM uint32_t SPINLOCK10; /*!< Reading from a spinlock address will: - Return 0 if lock is - already locked - Otherwise return nonzero, and simultaneously - claim the lock Writing (any value) releases the lock. If - core 0 and core 1 attempt to claim the same lock simultaneously, - core 0 wins. The value returned on success is 0x1 << lock - number. */ - __IOM uint32_t SPINLOCK11; /*!< Reading from a spinlock address will: - Return 0 if lock is - already locked - Otherwise return nonzero, and simultaneously - claim the lock Writing (any value) releases the lock. If - core 0 and core 1 attempt to claim the same lock simultaneously, - core 0 wins. The value returned on success is 0x1 << lock - number. */ - __IOM uint32_t SPINLOCK12; /*!< Reading from a spinlock address will: - Return 0 if lock is - already locked - Otherwise return nonzero, and simultaneously - claim the lock Writing (any value) releases the lock. If - core 0 and core 1 attempt to claim the same lock simultaneously, - core 0 wins. The value returned on success is 0x1 << lock - number. */ - __IOM uint32_t SPINLOCK13; /*!< Reading from a spinlock address will: - Return 0 if lock is - already locked - Otherwise return nonzero, and simultaneously - claim the lock Writing (any value) releases the lock. If - core 0 and core 1 attempt to claim the same lock simultaneously, - core 0 wins. The value returned on success is 0x1 << lock - number. */ - __IOM uint32_t SPINLOCK14; /*!< Reading from a spinlock address will: - Return 0 if lock is - already locked - Otherwise return nonzero, and simultaneously - claim the lock Writing (any value) releases the lock. If - core 0 and core 1 attempt to claim the same lock simultaneously, - core 0 wins. The value returned on success is 0x1 << lock - number. */ - __IOM uint32_t SPINLOCK15; /*!< Reading from a spinlock address will: - Return 0 if lock is - already locked - Otherwise return nonzero, and simultaneously - claim the lock Writing (any value) releases the lock. If - core 0 and core 1 attempt to claim the same lock simultaneously, - core 0 wins. The value returned on success is 0x1 << lock - number. */ - __IOM uint32_t SPINLOCK16; /*!< Reading from a spinlock address will: - Return 0 if lock is - already locked - Otherwise return nonzero, and simultaneously - claim the lock Writing (any value) releases the lock. If - core 0 and core 1 attempt to claim the same lock simultaneously, - core 0 wins. The value returned on success is 0x1 << lock - number. */ - __IOM uint32_t SPINLOCK17; /*!< Reading from a spinlock address will: - Return 0 if lock is - already locked - Otherwise return nonzero, and simultaneously - claim the lock Writing (any value) releases the lock. If - core 0 and core 1 attempt to claim the same lock simultaneously, - core 0 wins. The value returned on success is 0x1 << lock - number. */ - __IOM uint32_t SPINLOCK18; /*!< Reading from a spinlock address will: - Return 0 if lock is - already locked - Otherwise return nonzero, and simultaneously - claim the lock Writing (any value) releases the lock. If - core 0 and core 1 attempt to claim the same lock simultaneously, - core 0 wins. The value returned on success is 0x1 << lock - number. */ - __IOM uint32_t SPINLOCK19; /*!< Reading from a spinlock address will: - Return 0 if lock is - already locked - Otherwise return nonzero, and simultaneously - claim the lock Writing (any value) releases the lock. If - core 0 and core 1 attempt to claim the same lock simultaneously, - core 0 wins. The value returned on success is 0x1 << lock - number. */ - __IOM uint32_t SPINLOCK20; /*!< Reading from a spinlock address will: - Return 0 if lock is - already locked - Otherwise return nonzero, and simultaneously - claim the lock Writing (any value) releases the lock. If - core 0 and core 1 attempt to claim the same lock simultaneously, - core 0 wins. The value returned on success is 0x1 << lock - number. */ - __IOM uint32_t SPINLOCK21; /*!< Reading from a spinlock address will: - Return 0 if lock is - already locked - Otherwise return nonzero, and simultaneously - claim the lock Writing (any value) releases the lock. If - core 0 and core 1 attempt to claim the same lock simultaneously, - core 0 wins. The value returned on success is 0x1 << lock - number. */ - __IOM uint32_t SPINLOCK22; /*!< Reading from a spinlock address will: - Return 0 if lock is - already locked - Otherwise return nonzero, and simultaneously - claim the lock Writing (any value) releases the lock. If - core 0 and core 1 attempt to claim the same lock simultaneously, - core 0 wins. The value returned on success is 0x1 << lock - number. */ - __IOM uint32_t SPINLOCK23; /*!< Reading from a spinlock address will: - Return 0 if lock is - already locked - Otherwise return nonzero, and simultaneously - claim the lock Writing (any value) releases the lock. If - core 0 and core 1 attempt to claim the same lock simultaneously, - core 0 wins. The value returned on success is 0x1 << lock - number. */ - __IOM uint32_t SPINLOCK24; /*!< Reading from a spinlock address will: - Return 0 if lock is - already locked - Otherwise return nonzero, and simultaneously - claim the lock Writing (any value) releases the lock. If - core 0 and core 1 attempt to claim the same lock simultaneously, - core 0 wins. The value returned on success is 0x1 << lock - number. */ - __IOM uint32_t SPINLOCK25; /*!< Reading from a spinlock address will: - Return 0 if lock is - already locked - Otherwise return nonzero, and simultaneously - claim the lock Writing (any value) releases the lock. If - core 0 and core 1 attempt to claim the same lock simultaneously, - core 0 wins. The value returned on success is 0x1 << lock - number. */ - __IOM uint32_t SPINLOCK26; /*!< Reading from a spinlock address will: - Return 0 if lock is - already locked - Otherwise return nonzero, and simultaneously - claim the lock Writing (any value) releases the lock. If - core 0 and core 1 attempt to claim the same lock simultaneously, - core 0 wins. The value returned on success is 0x1 << lock - number. */ - __IOM uint32_t SPINLOCK27; /*!< Reading from a spinlock address will: - Return 0 if lock is - already locked - Otherwise return nonzero, and simultaneously - claim the lock Writing (any value) releases the lock. If - core 0 and core 1 attempt to claim the same lock simultaneously, - core 0 wins. The value returned on success is 0x1 << lock - number. */ - __IOM uint32_t SPINLOCK28; /*!< Reading from a spinlock address will: - Return 0 if lock is - already locked - Otherwise return nonzero, and simultaneously - claim the lock Writing (any value) releases the lock. If - core 0 and core 1 attempt to claim the same lock simultaneously, - core 0 wins. The value returned on success is 0x1 << lock - number. */ - __IOM uint32_t SPINLOCK29; /*!< Reading from a spinlock address will: - Return 0 if lock is - already locked - Otherwise return nonzero, and simultaneously - claim the lock Writing (any value) releases the lock. If - core 0 and core 1 attempt to claim the same lock simultaneously, - core 0 wins. The value returned on success is 0x1 << lock - number. */ - __IOM uint32_t SPINLOCK30; /*!< Reading from a spinlock address will: - Return 0 if lock is - already locked - Otherwise return nonzero, and simultaneously - claim the lock Writing (any value) releases the lock. If - core 0 and core 1 attempt to claim the same lock simultaneously, - core 0 wins. The value returned on success is 0x1 << lock - number. */ - __IOM uint32_t SPINLOCK31; /*!< Reading from a spinlock address will: - Return 0 if lock is - already locked - Otherwise return nonzero, and simultaneously - claim the lock Writing (any value) releases the lock. If - core 0 and core 1 attempt to claim the same lock simultaneously, - core 0 wins. The value returned on success is 0x1 << lock - number. */ - __IOM uint32_t DOORBELL_OUT_SET; /*!< Trigger a doorbell interrupt on the opposite core. Write 1 to - a bit to set the corresponding bit in DOORBELL_IN on the - opposite core. This raises the opposite core's doorbell - interrupt. Read to get the status of the doorbells currently - asserted on the opposite core. This is equivalent to that - core reading its own DOORBELL_IN status. */ - __IOM uint32_t DOORBELL_OUT_CLR; /*!< Clear doorbells which have been posted to the opposite core. - This register is intended for debugging and initialisation - purposes. Writing 1 to a bit in DOORBELL_OUT_CLR clears - the corresponding bit in DOORBELL_IN on the opposite core. - Clearing all bits will cause that core's doorbell interrupt - to deassert. Since the usual order of events is for software - to send events using DOORBELL_OUT_SET, and acknowledge - incoming events by writing to DOORBELL_IN_CLR, this register - should be used with caution to avoid race conditions. Reading - returns the status of the doorbells currently asserted - on the other core, i.e. is equivalent to that core reading - its own DOORBELL_IN status. */ - __IOM uint32_t DOORBELL_IN_SET; /*!< Write 1s to trigger doorbell interrupts on this core. Read to - get status of doorbells currently asserted on this core. */ - __IOM uint32_t DOORBELL_IN_CLR; /*!< Check and acknowledge doorbells posted to this core. This core's - doorbell interrupt is asserted when any bit in this register - is 1. Write 1 to each bit to clear that bit. The doorbell - interrupt deasserts once all bits are cleared. Read to - get status of doorbells currently asserted on this core. */ - __IOM uint32_t PERI_NONSEC; /*!< Detach certain core-local peripherals from Secure SIO, and attach - them to Non-secure SIO, so that Non-secure software can - use them. Attempting to access one of these peripherals - from the Secure SIO when it is attached to the Non-secure - SIO, or vice versa, will generate a bus error. This register - is per-core, and is only present on the Secure SIO. Most - SIO hardware is duplicated across the Secure and Non-secure - SIO, so is not listed in this register. */ - __IM uint32_t RESERVED2[3]; - __IOM uint32_t RISCV_SOFTIRQ; /*!< Control the assertion of the standard software interrupt (MIP.MSIP) - on the RISC-V cores. Unlike the RISC-V timer, this interrupt - is not routed to a normal system-level interrupt line, - so can not be used by the Arm cores. It is safe for both - cores to write to this register on the same cycle. The - set/clear effect is accumulated across both cores, and - then applied. If a flag is both set and cleared on the - same cycle, only the set takes effect. */ - __IOM uint32_t MTIME_CTRL; /*!< Control register for the RISC-V 64-bit Machine-mode timer. This - timer is only present in the Secure SIO, so is only accessible - to an Arm core in Secure mode or a RISC-V core in Machine - mode. Note whilst this timer follows the RISC-V privileged - specification, it is equally usable by the Arm cores. The - interrupts are routed to normal system-level interrupt - lines as well as to the MIP.MTIP inputs on the RISC-V cores. */ - __IM uint32_t RESERVED3[2]; - __IOM uint32_t MTIME; /*!< Read/write access to the high half of RISC-V Machine-mode timer. - This register is shared between both cores. If both cores - write on the same cycle, core 1 takes precedence. */ - __IOM uint32_t MTIMEH; /*!< Read/write access to the high half of RISC-V Machine-mode timer. - This register is shared between both cores. If both cores - write on the same cycle, core 1 takes precedence. */ - __IOM uint32_t MTIMECMP; /*!< Low half of RISC-V Machine-mode timer comparator. This register - is core-local, i.e., each core gets a copy of this register, - with the comparison result routed to its own interrupt - line. The timer interrupt is asserted whenever MTIME is - greater than or equal to MTIMECMP. This comparison is unsigned, - and performed on the full 64-bit values. */ - __IOM uint32_t MTIMECMPH; /*!< High half of RISC-V Machine-mode timer comparator. This register - is core-local. The timer interrupt is asserted whenever - MTIME is greater than or equal to MTIMECMP. This comparison - is unsigned, and performed on the full 64-bit values. */ - __IOM uint32_t TMDS_CTRL; /*!< Control register for TMDS encoder. */ - __IOM uint32_t TMDS_WDATA; /*!< Write-only access to the TMDS colour data register. */ - __IOM uint32_t TMDS_PEEK_SINGLE; /*!< Get the encoding of one pixel's worth of colour data, packed - into a 32-bit value (3x10-bit symbols). The PEEK alias - does not shift the colour register when read, but still - advances the running DC balance state of each encoder. - This is useful for pixel doubling. */ - __IOM uint32_t TMDS_POP_SINGLE; /*!< Get the encoding of one pixel's worth of colour data, packed - into a 32-bit value. The packing is 5 chunks of 3 lanes - times 2 bits (30 bits total). Each chunk contains two bits - of a TMDS symbol per lane. This format is intended for - shifting out with the HSTX peripheral on RP2350. The POP - alias shifts the colour register when read, as well as - advancing the running DC balance state of each encoder. */ - __IOM uint32_t TMDS_PEEK_DOUBLE_L0; /*!< Get lane 0 of the encoding of two pixels' worth of colour data. - Two 10-bit TMDS symbols are packed at the bottom of a 32-bit - word. The PEEK alias does not shift the colour register - when read, but still advances the lane 0 DC balance state. - This is useful if all 3 lanes' worth of encode are to be - read at once, rather than processing the entire scanline - for one lane before moving to the next lane. */ - __IOM uint32_t TMDS_POP_DOUBLE_L0; /*!< Get lane 0 of the encoding of two pixels' worth of colour data. - Two 10-bit TMDS symbols are packed at the bottom of a 32-bit - word. The POP alias shifts the colour register when read, - according to the values of PIX_SHIFT and PIX2_NOSHIFT. */ - __IOM uint32_t TMDS_PEEK_DOUBLE_L1; /*!< Get lane 1 of the encoding of two pixels' worth of colour data. - Two 10-bit TMDS symbols are packed at the bottom of a 32-bit - word. The PEEK alias does not shift the colour register - when read, but still advances the lane 1 DC balance state. - This is useful if all 3 lanes' worth of encode are to be - read at once, rather than processing the entire scanline - for one lane before moving to the next lane. */ - __IOM uint32_t TMDS_POP_DOUBLE_L1; /*!< Get lane 1 of the encoding of two pixels' worth of colour data. - Two 10-bit TMDS symbols are packed at the bottom of a 32-bit - word. The POP alias shifts the colour register when read, - according to the values of PIX_SHIFT and PIX2_NOSHIFT. */ - __IOM uint32_t TMDS_PEEK_DOUBLE_L2; /*!< Get lane 2 of the encoding of two pixels' worth of colour data. - Two 10-bit TMDS symbols are packed at the bottom of a 32-bit - word. The PEEK alias does not shift the colour register - when read, but still advances the lane 2 DC balance state. - This is useful if all 3 lanes' worth of encode are to be - read at once, rather than processing the entire scanline - for one lane before moving to the next lane. */ - __IOM uint32_t TMDS_POP_DOUBLE_L2; /*!< Get lane 2 of the encoding of two pixels' worth of colour data. - Two 10-bit TMDS symbols are packed at the bottom of a 32-bit - word. The POP alias shifts the colour register when read, - according to the values of PIX_SHIFT and PIX2_NOSHIFT. */ -} SIO_Type; /*!< Size = 488 (0x1e8) */ - - - -/* =========================================================================================================================== */ -/* ================ BOOTRAM ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief Additional registers mapped adjacent to the bootram, for use by the bootrom. (BOOTRAM) - */ - -typedef struct { /*!< BOOTRAM Structure */ - __IM uint32_t RESERVED[512]; - __IOM uint32_t WRITE_ONCE0; /*!< This registers always ORs writes into its current contents. - Once a bit is set, it can only be cleared by a reset. */ - __IOM uint32_t WRITE_ONCE1; /*!< This registers always ORs writes into its current contents. - Once a bit is set, it can only be cleared by a reset. */ - __IOM uint32_t BOOTLOCK_STAT; /*!< Bootlock status register. 1=unclaimed, 0=claimed. These locks - function identically to the SIO spinlocks, but are reserved - for bootrom use. */ - __IOM uint32_t BOOTLOCK0; /*!< Read to claim and check. Write to unclaim. The value returned - on successful claim is 1 << n, and on failed claim is zero. */ - __IOM uint32_t BOOTLOCK1; /*!< Read to claim and check. Write to unclaim. The value returned - on successful claim is 1 << n, and on failed claim is zero. */ - __IOM uint32_t BOOTLOCK2; /*!< Read to claim and check. Write to unclaim. The value returned - on successful claim is 1 << n, and on failed claim is zero. */ - __IOM uint32_t BOOTLOCK3; /*!< Read to claim and check. Write to unclaim. The value returned - on successful claim is 1 << n, and on failed claim is zero. */ - __IOM uint32_t BOOTLOCK4; /*!< Read to claim and check. Write to unclaim. The value returned - on successful claim is 1 << n, and on failed claim is zero. */ - __IOM uint32_t BOOTLOCK5; /*!< Read to claim and check. Write to unclaim. The value returned - on successful claim is 1 << n, and on failed claim is zero. */ - __IOM uint32_t BOOTLOCK6; /*!< Read to claim and check. Write to unclaim. The value returned - on successful claim is 1 << n, and on failed claim is zero. */ - __IOM uint32_t BOOTLOCK7; /*!< Read to claim and check. Write to unclaim. The value returned - on successful claim is 1 << n, and on failed claim is zero. */ -} BOOTRAM_Type; /*!< Size = 2092 (0x82c) */ - - - -/* =========================================================================================================================== */ -/* ================ CORESIGHT_TRACE ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief Coresight block - RP specific registers (CORESIGHT_TRACE) - */ - -typedef struct { /*!< CORESIGHT_TRACE Structure */ - __IOM uint32_t CTRL_STATUS; /*!< Control and status register */ - __IOM uint32_t TRACE_CAPTURE_FIFO; /*!< FIFO for trace data captured from the TPIU */ -} CORESIGHT_TRACE_Type; /*!< Size = 8 (0x8) */ - - - -/* =========================================================================================================================== */ -/* ================ USB ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief USB FS/LS controller device registers (USB) - */ - -typedef struct { /*!< USB Structure */ - __IOM uint32_t ADDR_ENDP; /*!< Device address and endpoint control */ - __IOM uint32_t ADDR_ENDP1; /*!< Interrupt endpoint 1. Only valid for HOST mode. */ - __IOM uint32_t ADDR_ENDP2; /*!< Interrupt endpoint 2. Only valid for HOST mode. */ - __IOM uint32_t ADDR_ENDP3; /*!< Interrupt endpoint 3. Only valid for HOST mode. */ - __IOM uint32_t ADDR_ENDP4; /*!< Interrupt endpoint 4. Only valid for HOST mode. */ - __IOM uint32_t ADDR_ENDP5; /*!< Interrupt endpoint 5. Only valid for HOST mode. */ - __IOM uint32_t ADDR_ENDP6; /*!< Interrupt endpoint 6. Only valid for HOST mode. */ - __IOM uint32_t ADDR_ENDP7; /*!< Interrupt endpoint 7. Only valid for HOST mode. */ - __IOM uint32_t ADDR_ENDP8; /*!< Interrupt endpoint 8. Only valid for HOST mode. */ - __IOM uint32_t ADDR_ENDP9; /*!< Interrupt endpoint 9. Only valid for HOST mode. */ - __IOM uint32_t ADDR_ENDP10; /*!< Interrupt endpoint 10. Only valid for HOST mode. */ - __IOM uint32_t ADDR_ENDP11; /*!< Interrupt endpoint 11. Only valid for HOST mode. */ - __IOM uint32_t ADDR_ENDP12; /*!< Interrupt endpoint 12. Only valid for HOST mode. */ - __IOM uint32_t ADDR_ENDP13; /*!< Interrupt endpoint 13. Only valid for HOST mode. */ - __IOM uint32_t ADDR_ENDP14; /*!< Interrupt endpoint 14. Only valid for HOST mode. */ - __IOM uint32_t ADDR_ENDP15; /*!< Interrupt endpoint 15. Only valid for HOST mode. */ - __IOM uint32_t MAIN_CTRL; /*!< Main control register */ - __IOM uint32_t SOF_WR; /*!< Set the SOF (Start of Frame) frame number in the host controller. - The SOF packet is sent every 1ms and the host will increment - the frame number by 1 each time. */ - __IOM uint32_t SOF_RD; /*!< Read the last SOF (Start of Frame) frame number seen. In device - mode the last SOF received from the host. In host mode - the last SOF sent by the host. */ - __IOM uint32_t SIE_CTRL; /*!< SIE control register */ - __IOM uint32_t SIE_STATUS; /*!< SIE status register */ - __IOM uint32_t INT_EP_CTRL; /*!< interrupt endpoint control register */ - __IOM uint32_t BUFF_STATUS; /*!< Buffer status register. A bit set here indicates that a buffer - has completed on the endpoint (if the buffer interrupt - is enabled). It is possible for 2 buffers to be completed, - so clearing the buffer status bit may instantly re set - it on the next clock cycle. */ - __IOM uint32_t BUFF_CPU_SHOULD_HANDLE; /*!< Which of the double buffers should be handled. Only valid if - using an interrupt per buffer (i.e. not per 2 buffers). - Not valid for host interrupt endpoint polling because they - are only single buffered. */ - __IOM uint32_t EP_ABORT; /*!< Device only: Can be set to ignore the buffer control register - for this endpoint in case you would like to revoke a buffer. - A NAK will be sent for every access to the endpoint until - this bit is cleared. A corresponding bit in `EP_ABORT_DONE` - is set when it is safe to modify the buffer control register. */ - __IOM uint32_t EP_ABORT_DONE; /*!< Device only: Used in conjunction with `EP_ABORT`. Set once an - endpoint is idle so the programmer knows it is safe to - modify the buffer control register. */ - __IOM uint32_t EP_STALL_ARM; /*!< Device: this bit must be set in conjunction with the `STALL` - bit in the buffer control register to send a STALL on EP0. - The device controller clears these bits when a SETUP packet - is received because the USB spec requires that a STALL - condition is cleared when a SETUP packet is received. */ - __IOM uint32_t NAK_POLL; /*!< Used by the host controller. Sets the wait time in microseconds - before trying again if the device replies with a NAK. */ - __IOM uint32_t EP_STATUS_STALL_NAK; /*!< Device: bits are set when the `IRQ_ON_NAK` or `IRQ_ON_STALL` - bits are set. For EP0 this comes from `SIE_CTRL`. For all - other endpoints it comes from the endpoint control register. */ - __IOM uint32_t USB_MUXING; /*!< Where to connect the USB controller. Should be to_phy by default. */ - __IOM uint32_t USB_PWR; /*!< Overrides for the power signals in the event that the VBUS signals - are not hooked up to GPIO. Set the value of the override - and then the override enable to switch over to the override - value. */ - __IOM uint32_t USBPHY_DIRECT; /*!< This register allows for direct control of the USB phy. Use - in conjunction with usbphy_direct_override register to - enable each override bit. */ - __IOM uint32_t USBPHY_DIRECT_OVERRIDE; /*!< Override enable for each control in usbphy_direct */ - __IOM uint32_t USBPHY_TRIM; /*!< Used to adjust trim values of USB phy pull down resistors. */ - __IOM uint32_t LINESTATE_TUNING; /*!< Used for debug only. */ - __IOM uint32_t INTR; /*!< Raw Interrupts */ - __IOM uint32_t INTE; /*!< Interrupt Enable */ - __IOM uint32_t INTF; /*!< Interrupt Force */ - __IOM uint32_t INTS; /*!< Interrupt status after masking & forcing */ - __IM uint32_t RESERVED[25]; - __IOM uint32_t SOF_TIMESTAMP_RAW; /*!< Device only. Raw value of free-running PHY clock counter @48MHz. - Used to calculate time between SOF events. */ - __IOM uint32_t SOF_TIMESTAMP_LAST; /*!< Device only. Value of free-running PHY clock counter @48MHz - when last SOF event occurred. */ - __IOM uint32_t SM_STATE; /*!< SM_STATE */ - __IOM uint32_t EP_TX_ERROR; /*!< TX error count for each endpoint. Write to each field to reset - the counter to 0. */ - __IOM uint32_t EP_RX_ERROR; /*!< RX error count for each endpoint. Write to each field to reset - the counter to 0. */ - __IOM uint32_t DEV_SM_WATCHDOG; /*!< Watchdog that forces the device state machine to idle and raises - an interrupt if the device stays in a state that isn't - idle for the configured limit. The counter is reset on - every state transition. Set limit while enable is low and - then set the enable. */ -} USB_Type; /*!< Size = 280 (0x118) */ - - - -/* =========================================================================================================================== */ -/* ================ TRNG ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief ARM TrustZone RNG register block (TRNG) - */ - -typedef struct { /*!< TRNG Structure */ - __IM uint32_t RESERVED[64]; - __IOM uint32_t RNG_IMR; /*!< Interrupt masking. */ - __IOM uint32_t RNG_ISR; /*!< RNG status register. If corresponding RNG_IMR bit is unmasked, - an interrupt will be generated. */ - __IOM uint32_t RNG_ICR; /*!< Interrupt/status bit clear Register. */ - __IOM uint32_t TRNG_CONFIG; /*!< Selecting the inverter-chain length. */ - __IOM uint32_t TRNG_VALID; /*!< 192 bit collection indication. */ - __IOM uint32_t EHR_DATA0; /*!< RNG collected bits. */ - __IOM uint32_t EHR_DATA1; /*!< RNG collected bits. */ - __IOM uint32_t EHR_DATA2; /*!< RNG collected bits. */ - __IOM uint32_t EHR_DATA3; /*!< RNG collected bits. */ - __IOM uint32_t EHR_DATA4; /*!< RNG collected bits. */ - __IOM uint32_t EHR_DATA5; /*!< RNG collected bits. */ - __IOM uint32_t RND_SOURCE_ENABLE; /*!< Enable signal for the random source. */ - __IOM uint32_t SAMPLE_CNT1; /*!< Counts clocks between sampling of random bit. */ - __IOM uint32_t AUTOCORR_STATISTIC; /*!< Statistic about Autocorrelation test activations. */ - __IOM uint32_t TRNG_DEBUG_CONTROL; /*!< Debug register. */ - __IM uint32_t RESERVED1; - __IOM uint32_t TRNG_SW_RESET; /*!< Generate internal SW reset within the RNG block. */ - __IM uint32_t RESERVED2[28]; - __IOM uint32_t RNG_DEBUG_EN_INPUT; /*!< Enable the RNG debug mode */ - __IOM uint32_t TRNG_BUSY; /*!< RNG Busy indication. */ - __IOM uint32_t RST_BITS_COUNTER; /*!< Reset the counter of collected bits in the RNG. */ - __IOM uint32_t RNG_VERSION; /*!< Displays the version settings of the TRNG. */ - __IM uint32_t RESERVED3[7]; - __IOM uint32_t RNG_BIST_CNTR_0; /*!< Collected BIST results. */ - __IOM uint32_t RNG_BIST_CNTR_1; /*!< Collected BIST results. */ - __IOM uint32_t RNG_BIST_CNTR_2; /*!< Collected BIST results. */ -} TRNG_Type; /*!< Size = 492 (0x1ec) */ - - - -/* =========================================================================================================================== */ -/* ================ GLITCH_DETECTOR ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief Glitch detector controls (GLITCH_DETECTOR) - */ - -typedef struct { /*!< GLITCH_DETECTOR Structure */ - __IOM uint32_t ARM; /*!< Forcibly arm the glitch detectors, if they are not already armed - by OTP. When armed, any individual detector trigger will - cause a restart of the switched core power domain's power-on - reset state machine. Glitch detector triggers are recorded - accumulatively in TRIG_STATUS. If the system is reset by - a glitch detector trigger, this is recorded in POWMAN_CHIP_RESET. - This register is Secure read/write only. */ - __IOM uint32_t DISARM; /*!< DISARM */ - __IOM uint32_t SENSITIVITY; /*!< Adjust the sensitivity of glitch detectors to values other than - their OTP-provided defaults. This register is Secure read/write - only. */ - __IOM uint32_t LOCK; /*!< LOCK */ - __IOM uint32_t TRIG_STATUS; /*!< Set when a detector output triggers. Write-1-clear. (May immediately - return high if the detector remains in a failed state. - Detectors can only be cleared by a full reset of the switched - core power domain.) This register is Secure read/write - only. */ - __IOM uint32_t TRIG_FORCE; /*!< Simulate the firing of one or more detectors. Writing ones to - this register will set the matching bits in STATUS_TRIG. - If the glitch detectors are currently armed, writing ones - will also immediately reset the switched core power domain, - and set the reset reason latches in POWMAN_CHIP_RESET to - indicate a glitch detector resets. This register is Secure - read/write only. */ -} GLITCH_DETECTOR_Type; /*!< Size = 24 (0x18) */ - - - -/* =========================================================================================================================== */ -/* ================ OTP ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief SNPS OTP control IF (SBPI and RPi wrapper control) (OTP) - */ - -typedef struct { /*!< OTP Structure */ - __IOM uint32_t SW_LOCK0; /*!< Software lock register for page 0. Locks are initialised from - the OTP lock pages at reset. This register can be written - to further advance the lock state of each page (until next - reset), and read to check the current lock state of a page. */ - __IOM uint32_t SW_LOCK1; /*!< Software lock register for page 1. Locks are initialised from - the OTP lock pages at reset. This register can be written - to further advance the lock state of each page (until next - reset), and read to check the current lock state of a page. */ - __IOM uint32_t SW_LOCK2; /*!< Software lock register for page 2. Locks are initialised from - the OTP lock pages at reset. This register can be written - to further advance the lock state of each page (until next - reset), and read to check the current lock state of a page. */ - __IOM uint32_t SW_LOCK3; /*!< Software lock register for page 3. Locks are initialised from - the OTP lock pages at reset. This register can be written - to further advance the lock state of each page (until next - reset), and read to check the current lock state of a page. */ - __IOM uint32_t SW_LOCK4; /*!< Software lock register for page 4. Locks are initialised from - the OTP lock pages at reset. This register can be written - to further advance the lock state of each page (until next - reset), and read to check the current lock state of a page. */ - __IOM uint32_t SW_LOCK5; /*!< Software lock register for page 5. Locks are initialised from - the OTP lock pages at reset. This register can be written - to further advance the lock state of each page (until next - reset), and read to check the current lock state of a page. */ - __IOM uint32_t SW_LOCK6; /*!< Software lock register for page 6. Locks are initialised from - the OTP lock pages at reset. This register can be written - to further advance the lock state of each page (until next - reset), and read to check the current lock state of a page. */ - __IOM uint32_t SW_LOCK7; /*!< Software lock register for page 7. Locks are initialised from - the OTP lock pages at reset. This register can be written - to further advance the lock state of each page (until next - reset), and read to check the current lock state of a page. */ - __IOM uint32_t SW_LOCK8; /*!< Software lock register for page 8. Locks are initialised from - the OTP lock pages at reset. This register can be written - to further advance the lock state of each page (until next - reset), and read to check the current lock state of a page. */ - __IOM uint32_t SW_LOCK9; /*!< Software lock register for page 9. Locks are initialised from - the OTP lock pages at reset. This register can be written - to further advance the lock state of each page (until next - reset), and read to check the current lock state of a page. */ - __IOM uint32_t SW_LOCK10; /*!< Software lock register for page 10. Locks are initialised from - the OTP lock pages at reset. This register can be written - to further advance the lock state of each page (until next - reset), and read to check the current lock state of a page. */ - __IOM uint32_t SW_LOCK11; /*!< Software lock register for page 11. Locks are initialised from - the OTP lock pages at reset. This register can be written - to further advance the lock state of each page (until next - reset), and read to check the current lock state of a page. */ - __IOM uint32_t SW_LOCK12; /*!< Software lock register for page 12. Locks are initialised from - the OTP lock pages at reset. This register can be written - to further advance the lock state of each page (until next - reset), and read to check the current lock state of a page. */ - __IOM uint32_t SW_LOCK13; /*!< Software lock register for page 13. Locks are initialised from - the OTP lock pages at reset. This register can be written - to further advance the lock state of each page (until next - reset), and read to check the current lock state of a page. */ - __IOM uint32_t SW_LOCK14; /*!< Software lock register for page 14. Locks are initialised from - the OTP lock pages at reset. This register can be written - to further advance the lock state of each page (until next - reset), and read to check the current lock state of a page. */ - __IOM uint32_t SW_LOCK15; /*!< Software lock register for page 15. Locks are initialised from - the OTP lock pages at reset. This register can be written - to further advance the lock state of each page (until next - reset), and read to check the current lock state of a page. */ - __IOM uint32_t SW_LOCK16; /*!< Software lock register for page 16. Locks are initialised from - the OTP lock pages at reset. This register can be written - to further advance the lock state of each page (until next - reset), and read to check the current lock state of a page. */ - __IOM uint32_t SW_LOCK17; /*!< Software lock register for page 17. Locks are initialised from - the OTP lock pages at reset. This register can be written - to further advance the lock state of each page (until next - reset), and read to check the current lock state of a page. */ - __IOM uint32_t SW_LOCK18; /*!< Software lock register for page 18. Locks are initialised from - the OTP lock pages at reset. This register can be written - to further advance the lock state of each page (until next - reset), and read to check the current lock state of a page. */ - __IOM uint32_t SW_LOCK19; /*!< Software lock register for page 19. Locks are initialised from - the OTP lock pages at reset. This register can be written - to further advance the lock state of each page (until next - reset), and read to check the current lock state of a page. */ - __IOM uint32_t SW_LOCK20; /*!< Software lock register for page 20. Locks are initialised from - the OTP lock pages at reset. This register can be written - to further advance the lock state of each page (until next - reset), and read to check the current lock state of a page. */ - __IOM uint32_t SW_LOCK21; /*!< Software lock register for page 21. Locks are initialised from - the OTP lock pages at reset. This register can be written - to further advance the lock state of each page (until next - reset), and read to check the current lock state of a page. */ - __IOM uint32_t SW_LOCK22; /*!< Software lock register for page 22. Locks are initialised from - the OTP lock pages at reset. This register can be written - to further advance the lock state of each page (until next - reset), and read to check the current lock state of a page. */ - __IOM uint32_t SW_LOCK23; /*!< Software lock register for page 23. Locks are initialised from - the OTP lock pages at reset. This register can be written - to further advance the lock state of each page (until next - reset), and read to check the current lock state of a page. */ - __IOM uint32_t SW_LOCK24; /*!< Software lock register for page 24. Locks are initialised from - the OTP lock pages at reset. This register can be written - to further advance the lock state of each page (until next - reset), and read to check the current lock state of a page. */ - __IOM uint32_t SW_LOCK25; /*!< Software lock register for page 25. Locks are initialised from - the OTP lock pages at reset. This register can be written - to further advance the lock state of each page (until next - reset), and read to check the current lock state of a page. */ - __IOM uint32_t SW_LOCK26; /*!< Software lock register for page 26. Locks are initialised from - the OTP lock pages at reset. This register can be written - to further advance the lock state of each page (until next - reset), and read to check the current lock state of a page. */ - __IOM uint32_t SW_LOCK27; /*!< Software lock register for page 27. Locks are initialised from - the OTP lock pages at reset. This register can be written - to further advance the lock state of each page (until next - reset), and read to check the current lock state of a page. */ - __IOM uint32_t SW_LOCK28; /*!< Software lock register for page 28. Locks are initialised from - the OTP lock pages at reset. This register can be written - to further advance the lock state of each page (until next - reset), and read to check the current lock state of a page. */ - __IOM uint32_t SW_LOCK29; /*!< Software lock register for page 29. Locks are initialised from - the OTP lock pages at reset. This register can be written - to further advance the lock state of each page (until next - reset), and read to check the current lock state of a page. */ - __IOM uint32_t SW_LOCK30; /*!< Software lock register for page 30. Locks are initialised from - the OTP lock pages at reset. This register can be written - to further advance the lock state of each page (until next - reset), and read to check the current lock state of a page. */ - __IOM uint32_t SW_LOCK31; /*!< Software lock register for page 31. Locks are initialised from - the OTP lock pages at reset. This register can be written - to further advance the lock state of each page (until next - reset), and read to check the current lock state of a page. */ - __IOM uint32_t SW_LOCK32; /*!< Software lock register for page 32. Locks are initialised from - the OTP lock pages at reset. This register can be written - to further advance the lock state of each page (until next - reset), and read to check the current lock state of a page. */ - __IOM uint32_t SW_LOCK33; /*!< Software lock register for page 33. Locks are initialised from - the OTP lock pages at reset. This register can be written - to further advance the lock state of each page (until next - reset), and read to check the current lock state of a page. */ - __IOM uint32_t SW_LOCK34; /*!< Software lock register for page 34. Locks are initialised from - the OTP lock pages at reset. This register can be written - to further advance the lock state of each page (until next - reset), and read to check the current lock state of a page. */ - __IOM uint32_t SW_LOCK35; /*!< Software lock register for page 35. Locks are initialised from - the OTP lock pages at reset. This register can be written - to further advance the lock state of each page (until next - reset), and read to check the current lock state of a page. */ - __IOM uint32_t SW_LOCK36; /*!< Software lock register for page 36. Locks are initialised from - the OTP lock pages at reset. This register can be written - to further advance the lock state of each page (until next - reset), and read to check the current lock state of a page. */ - __IOM uint32_t SW_LOCK37; /*!< Software lock register for page 37. Locks are initialised from - the OTP lock pages at reset. This register can be written - to further advance the lock state of each page (until next - reset), and read to check the current lock state of a page. */ - __IOM uint32_t SW_LOCK38; /*!< Software lock register for page 38. Locks are initialised from - the OTP lock pages at reset. This register can be written - to further advance the lock state of each page (until next - reset), and read to check the current lock state of a page. */ - __IOM uint32_t SW_LOCK39; /*!< Software lock register for page 39. Locks are initialised from - the OTP lock pages at reset. This register can be written - to further advance the lock state of each page (until next - reset), and read to check the current lock state of a page. */ - __IOM uint32_t SW_LOCK40; /*!< Software lock register for page 40. Locks are initialised from - the OTP lock pages at reset. This register can be written - to further advance the lock state of each page (until next - reset), and read to check the current lock state of a page. */ - __IOM uint32_t SW_LOCK41; /*!< Software lock register for page 41. Locks are initialised from - the OTP lock pages at reset. This register can be written - to further advance the lock state of each page (until next - reset), and read to check the current lock state of a page. */ - __IOM uint32_t SW_LOCK42; /*!< Software lock register for page 42. Locks are initialised from - the OTP lock pages at reset. This register can be written - to further advance the lock state of each page (until next - reset), and read to check the current lock state of a page. */ - __IOM uint32_t SW_LOCK43; /*!< Software lock register for page 43. Locks are initialised from - the OTP lock pages at reset. This register can be written - to further advance the lock state of each page (until next - reset), and read to check the current lock state of a page. */ - __IOM uint32_t SW_LOCK44; /*!< Software lock register for page 44. Locks are initialised from - the OTP lock pages at reset. This register can be written - to further advance the lock state of each page (until next - reset), and read to check the current lock state of a page. */ - __IOM uint32_t SW_LOCK45; /*!< Software lock register for page 45. Locks are initialised from - the OTP lock pages at reset. This register can be written - to further advance the lock state of each page (until next - reset), and read to check the current lock state of a page. */ - __IOM uint32_t SW_LOCK46; /*!< Software lock register for page 46. Locks are initialised from - the OTP lock pages at reset. This register can be written - to further advance the lock state of each page (until next - reset), and read to check the current lock state of a page. */ - __IOM uint32_t SW_LOCK47; /*!< Software lock register for page 47. Locks are initialised from - the OTP lock pages at reset. This register can be written - to further advance the lock state of each page (until next - reset), and read to check the current lock state of a page. */ - __IOM uint32_t SW_LOCK48; /*!< Software lock register for page 48. Locks are initialised from - the OTP lock pages at reset. This register can be written - to further advance the lock state of each page (until next - reset), and read to check the current lock state of a page. */ - __IOM uint32_t SW_LOCK49; /*!< Software lock register for page 49. Locks are initialised from - the OTP lock pages at reset. This register can be written - to further advance the lock state of each page (until next - reset), and read to check the current lock state of a page. */ - __IOM uint32_t SW_LOCK50; /*!< Software lock register for page 50. Locks are initialised from - the OTP lock pages at reset. This register can be written - to further advance the lock state of each page (until next - reset), and read to check the current lock state of a page. */ - __IOM uint32_t SW_LOCK51; /*!< Software lock register for page 51. Locks are initialised from - the OTP lock pages at reset. This register can be written - to further advance the lock state of each page (until next - reset), and read to check the current lock state of a page. */ - __IOM uint32_t SW_LOCK52; /*!< Software lock register for page 52. Locks are initialised from - the OTP lock pages at reset. This register can be written - to further advance the lock state of each page (until next - reset), and read to check the current lock state of a page. */ - __IOM uint32_t SW_LOCK53; /*!< Software lock register for page 53. Locks are initialised from - the OTP lock pages at reset. This register can be written - to further advance the lock state of each page (until next - reset), and read to check the current lock state of a page. */ - __IOM uint32_t SW_LOCK54; /*!< Software lock register for page 54. Locks are initialised from - the OTP lock pages at reset. This register can be written - to further advance the lock state of each page (until next - reset), and read to check the current lock state of a page. */ - __IOM uint32_t SW_LOCK55; /*!< Software lock register for page 55. Locks are initialised from - the OTP lock pages at reset. This register can be written - to further advance the lock state of each page (until next - reset), and read to check the current lock state of a page. */ - __IOM uint32_t SW_LOCK56; /*!< Software lock register for page 56. Locks are initialised from - the OTP lock pages at reset. This register can be written - to further advance the lock state of each page (until next - reset), and read to check the current lock state of a page. */ - __IOM uint32_t SW_LOCK57; /*!< Software lock register for page 57. Locks are initialised from - the OTP lock pages at reset. This register can be written - to further advance the lock state of each page (until next - reset), and read to check the current lock state of a page. */ - __IOM uint32_t SW_LOCK58; /*!< Software lock register for page 58. Locks are initialised from - the OTP lock pages at reset. This register can be written - to further advance the lock state of each page (until next - reset), and read to check the current lock state of a page. */ - __IOM uint32_t SW_LOCK59; /*!< Software lock register for page 59. Locks are initialised from - the OTP lock pages at reset. This register can be written - to further advance the lock state of each page (until next - reset), and read to check the current lock state of a page. */ - __IOM uint32_t SW_LOCK60; /*!< Software lock register for page 60. Locks are initialised from - the OTP lock pages at reset. This register can be written - to further advance the lock state of each page (until next - reset), and read to check the current lock state of a page. */ - __IOM uint32_t SW_LOCK61; /*!< Software lock register for page 61. Locks are initialised from - the OTP lock pages at reset. This register can be written - to further advance the lock state of each page (until next - reset), and read to check the current lock state of a page. */ - __IOM uint32_t SW_LOCK62; /*!< Software lock register for page 62. Locks are initialised from - the OTP lock pages at reset. This register can be written - to further advance the lock state of each page (until next - reset), and read to check the current lock state of a page. */ - __IOM uint32_t SW_LOCK63; /*!< Software lock register for page 63. Locks are initialised from - the OTP lock pages at reset. This register can be written - to further advance the lock state of each page (until next - reset), and read to check the current lock state of a page. */ - __IOM uint32_t SBPI_INSTR; /*!< Dispatch instructions to the SBPI interface, used for programming - the OTP fuses. */ - __IOM uint32_t SBPI_WDATA_0; /*!< SBPI write payload bytes 3..0 */ - __IOM uint32_t SBPI_WDATA_1; /*!< SBPI write payload bytes 7..4 */ - __IOM uint32_t SBPI_WDATA_2; /*!< SBPI write payload bytes 11..8 */ - __IOM uint32_t SBPI_WDATA_3; /*!< SBPI write payload bytes 15..12 */ - __IOM uint32_t SBPI_RDATA_0; /*!< Read payload bytes 3..0. Once read, the data in the register - will automatically clear to 0. */ - __IOM uint32_t SBPI_RDATA_1; /*!< Read payload bytes 7..4. Once read, the data in the register - will automatically clear to 0. */ - __IOM uint32_t SBPI_RDATA_2; /*!< Read payload bytes 11..8. Once read, the data in the register - will automatically clear to 0. */ - __IOM uint32_t SBPI_RDATA_3; /*!< Read payload bytes 15..12. Once read, the data in the register - will automatically clear to 0. */ - __IOM uint32_t SBPI_STATUS; /*!< SBPI_STATUS */ - __IOM uint32_t USR; /*!< Controls for APB data read interface (USER interface) */ - __IOM uint32_t DBG; /*!< Debug for OTP power-on state machine */ - __IM uint32_t RESERVED; - __IOM uint32_t BIST; /*!< During BIST, count address locations that have at least one - leaky bit */ - __IOM uint32_t CRT_KEY_W0; /*!< Word 0 (bits 31..0) of the key. Write only, read returns 0x0 */ - __IOM uint32_t CRT_KEY_W1; /*!< Word 1 (bits 63..32) of the key. Write only, read returns 0x0 */ - __IOM uint32_t CRT_KEY_W2; /*!< Word 2 (bits 95..64) of the key. Write only, read returns 0x0 */ - __IOM uint32_t CRT_KEY_W3; /*!< Word 3 (bits 127..96) of the key. Write only, read returns 0x0 */ - __IOM uint32_t CRITICAL; /*!< Quickly check values of critical flags read during boot up */ - __IOM uint32_t KEY_VALID; /*!< Which keys were valid (enrolled) at boot time */ - __IOM uint32_t DEBUGEN; /*!< Enable a debug feature that has been disabled. Debug features - are disabled if one of the relevant critical boot flags - is set in OTP (DEBUG_DISABLE or SECURE_DEBUG_DISABLE), - OR if a debug key is marked valid in OTP, and the matching - key value has not been supplied over SWD. Specifically: - - The DEBUG_DISABLE flag disables all debug features. This - can be fully overridden by setting all bits of this register. - - The SECURE_DEBUG_DISABLE flag disables secure processor - debug. This can be fully overridden by setting the PROC0_SECURE - and PROC1_SECURE bits of this register. - If a single debug - key has been registered, and no matching key value has - been supplied over SWD, then all debug features are disabled. - This can be fully overridden by setting all bits of this - register. - If both debug keys have been registered, and - the Non-secure key's value (key 6) has been supplied over - SWD, secure processor debug is disabled. This can be fully - overridden by setting the PROC0_SECURE and PROC1_SECURE - bits of this register. - If both debug keys have been registered, - and the Secure key's value (key 5) has been supplied over - SWD, then no debug features are disabled by the key mechanism. - However, note that in this case debug features may still - be disabled by the critical boot flags. */ - __IOM uint32_t DEBUGEN_LOCK; /*!< Write 1s to lock corresponding bits in DEBUGEN. This register - is reset by the processor cold reset. */ - __IOM uint32_t ARCHSEL; /*!< Architecture select (Arm/RISC-V). The default and allowable - values of this register are constrained by the critical - boot flags. This register is reset by the earliest reset - in the switched core power domain (before a processor cold - reset). Cores sample their architecture select signal on - a warm reset. The source of the warm reset could be the - system power-up state machine, the watchdog timer, Arm - SYSRESETREQ or from RISC-V hartresetreq. Note that when - an Arm core is deselected, its cold reset domain is also - held in reset, since in particular the SYSRESETREQ bit - becomes inaccessible once the core is deselected. Note - also the RISC-V cores do not have a cold reset domain, - since their corresponding controls are located in the Debug - Module. */ - __IOM uint32_t ARCHSEL_STATUS; /*!< Get the current architecture select state of each core. Cores - sample the current value of the ARCHSEL register when their - warm reset is released, at which point the corresponding - bit in this register will also update. */ - __IOM uint32_t BOOTDIS; /*!< Tell the bootrom to ignore scratch register boot vectors (both - power manager and watchdog) on the next power up. If an - early boot stage has soft-locked some OTP pages in order - to protect their contents from later stages, there is a - risk that Secure code running at a later stage can unlock - the pages by performing a watchdog reset that resets the - OTP. This register can be used to ensure that the bootloader - runs as normal on the next power up, preventing Secure - code at a later stage from accessing OTP in its unlocked - state. Should be used in conjunction with the power manager - BOOTDIS register. */ - __IOM uint32_t INTR; /*!< Raw Interrupts */ - __IOM uint32_t INTE; /*!< Interrupt Enable */ - __IOM uint32_t INTF; /*!< Interrupt Force */ - __IOM uint32_t INTS; /*!< Interrupt status after masking & forcing */ -} OTP_Type; /*!< Size = 372 (0x174) */ - - - -/* =========================================================================================================================== */ -/* ================ OTP_DATA ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief Predefined OTP data layout for RP2350 (OTP_DATA) - */ - -typedef struct { /*!< OTP_DATA Structure */ - __IOM uint16_t CHIPID0; /*!< Bits 15:0 of public device ID. (ECC) The CHIPID0..3 rows contain - a 64-bit random identifier for this chip, which can be - read from the USB bootloader PICOBOOT interface or from - the get_sys_info ROM API. The number of random bits makes - the occurrence of twins exceedingly unlikely: for example, - a fleet of a hundred million devices has a 99.97% probability - of no twinned IDs. This is estimated to be lower than the - occurrence of process errors in the assignment of sequential - random IDs, and for practical purposes CHIPID may be treated - as unique. */ - __IOM uint16_t CHIPID1; /*!< Bits 31:16 of public device ID (ECC) */ - __IOM uint16_t CHIPID2; /*!< Bits 47:32 of public device ID (ECC) */ - __IOM uint16_t CHIPID3; /*!< Bits 63:48 of public device ID (ECC) */ - __IOM uint16_t RANDID0; /*!< Bits 15:0 of private per-device random number (ECC) The RANDID0..7 - rows form a 128-bit random number generated during device - test. This ID is not exposed through the USB PICOBOOT GET_INFO - command or the ROM `get_sys_info()` API. However note that - the USB PICOBOOT OTP access point can read the entirety - of page 0, so this value is not meaningfully private unless - the USB PICOBOOT interface is disabled via the DISABLE_BOOTSEL_USB_PICOBO - T_IFC flag in BOOT_FLAGS0. */ - __IOM uint16_t RANDID1; /*!< Bits 31:16 of private per-device random number (ECC) */ - __IOM uint16_t RANDID2; /*!< Bits 47:32 of private per-device random number (ECC) */ - __IOM uint16_t RANDID3; /*!< Bits 63:48 of private per-device random number (ECC) */ - __IOM uint16_t RANDID4; /*!< Bits 79:64 of private per-device random number (ECC) */ - __IOM uint16_t RANDID5; /*!< Bits 95:80 of private per-device random number (ECC) */ - __IOM uint16_t RANDID6; /*!< Bits 111:96 of private per-device random number (ECC) */ - __IOM uint16_t RANDID7; /*!< Bits 127:112 of private per-device random number (ECC) */ - __IM uint16_t RESERVED[4]; - __IOM uint16_t ROSC_CALIB; /*!< Ring oscillator frequency in kHz, measured during manufacturing - (ECC) This is measured at 1.1 V, at room temperature, with - the ROSC configuration registers in their reset state. */ - __IOM uint16_t LPOSC_CALIB; /*!< Low-power oscillator frequency in Hz, measured during manufacturing - (ECC) This is measured at 1.1V, at room temperature, with - the LPOSC trim register in its reset state. */ - __IM uint16_t RESERVED1[6]; - __IOM uint16_t NUM_GPIOS; /*!< The number of main user GPIOs (bank 0). Should read 48 in the - QFN80 package, and 30 in the QFN60 package. (ECC) */ - __IM uint16_t RESERVED2[29]; - __IOM uint16_t INFO_CRC0; /*!< Lower 16 bits of CRC32 of OTP addresses 0x00 through 0x6b (polynomial - 0x4c11db7, input reflected, output reflected, seed all-ones, - final XOR all-ones) (ECC) */ - __IOM uint16_t INFO_CRC1; /*!< Upper 16 bits of CRC32 of OTP addresses 0x00 through 0x6b (ECC) */ - __IM uint16_t RESERVED3[28]; - __IOM uint16_t FLASH_DEVINFO; /*!< Stores information about external flash device(s). (ECC) Assumed - to be valid if BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is set. */ - __IOM uint16_t FLASH_PARTITION_SLOT_SIZE; /*!< Gap between partition table slot 0 and slot 1 at the start of - flash (the default size is 4096 bytes) (ECC) Enabled by - the OVERRIDE_FLASH_PARTITION_SLOT_SIZE bit in BOOT_FLAGS, - the size is 4096 * (value + 1) */ - __IOM uint16_t BOOTSEL_LED_CFG; /*!< Pin configuration for LED status, used by USB bootloader. (ECC) - Must be valid if BOOT_FLAGS0_ENABLE_BOOTSEL_LED is set. */ - __IOM uint16_t BOOTSEL_PLL_CFG; /*!< Optional PLL configuration for BOOTSEL mode. (ECC) This should - be configured to produce an exact 48 MHz based on the crystal - oscillator frequency. User mode software may also use this - value to calculate the expected crystal frequency based - on an assumed 48 MHz PLL output. If no configuration is - given, the crystal is assumed to be 12 MHz. The PLL frequency - can be calculated as: PLL out = (XOSC frequency / (REFDIV+1)) - x FBDIV / (POSTDIV1 x POSTDIV2) Conversely the crystal - frequency can be calculated as: XOSC frequency = 48 MHz - x (REFDIV+1) x (POSTDIV1 x POSTDIV2) / FBDIV (Note the - +1 on REFDIV is because the value stored in this OTP location - is the actual divisor value minus one.) Used if and only - if ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG is set in BOOT_FLAGS0. - That bit should be set only after this row and BOOTSEL_XOSC_CFG - are both correctly programmed. */ - __IOM uint16_t BOOTSEL_XOSC_CFG; /*!< Non-default crystal oscillator configuration for the USB bootloader. - (ECC) These values may also be used by user code configuring - the crystal oscillator. Used if and only if ENABLE_BOOTSEL_NON_DEFAULT_PL - _XOSC_CFG is set in BOOT_FLAGS0. That bit should be set - only after this row and BOOTSEL_PLL_CFG are both correctly - programmed. */ - __IM uint16_t RESERVED4[3]; - __IOM uint16_t USB_WHITE_LABEL_ADDR; /*!< Row index of the USB_WHITE_LABEL structure within OTP (ECC) - The table has 16 rows, each of which are also ECC and marked - valid by the corresponding valid bit in USB_BOOT_FLAGS - (ECC). The entries are either _VALUEs where the 16 bit - value is used as is, or _STRDEFs which acts as a pointers - to a string value. The value stored in a _STRDEF is two - separate bytes: The low seven bits of the first (LSB) byte - indicates the number of characters in the string, and the - top bit of the first (LSB) byte if set to indicate that - each character in the string is two bytes (Unicode) versus - one byte if unset. The second (MSB) byte represents the - location of the string data, and is encoded as the number - of rows from this USB_WHITE_LABEL_ADDR; i.e. the row of - the start of the string is USB_WHITE_LABEL_ADDR value + - msb_byte. In each case, the corresponding valid bit enables - replacing the default value for the corresponding item - provided by the boot rom. Note that Unicode _STRDEFs are - only supported for USB_DEVICE_PRODUCT_STRDEF, USB_DEVICE_SERIAL_NUMBER_ST - DEF and USB_DEVICE_MANUFACTURER_STRDEF. Unicode values - will be ignored if specified for other fields, and non-unicode - values for these three items will be converted to Unicode - characters by setting the upper 8 bits to zero. Note that - if the USB_WHITE_LABEL structure or the corresponding strings - are not readable by BOOTSEL mode based on OTP permissions, - or if alignment requirements are not met, then the corresponding - default values are used. The index values indicate where - each field is located (row USB_WHITE_LABEL_ADDR value + - index): */ - __IM uint16_t RESERVED5; - __IOM uint16_t OTPBOOT_SRC; /*!< OTP start row for the OTP boot image. (ECC) If OTP boot is enabled, - the bootrom will load from this location into SRAM and - then directly enter the loaded image. Note that the image - must be signed if SECURE_BOOT_ENABLE is set. The image - itself is assumed to be ECC-protected. This must be an - even number. Equivalently, the OTP boot image must start - at a word-aligned location in the ECC read data address - window. */ - __IOM uint16_t OTPBOOT_LEN; /*!< Length in rows of the OTP boot image. (ECC) OTPBOOT_LEN must - be even. The total image size must be a multiple of 4 bytes - (32 bits). */ - __IOM uint16_t OTPBOOT_DST0; /*!< Bits 15:0 of the OTP boot image load destination (and entry - point). (ECC) This must be a location in main SRAM (main - SRAM is addresses 0x20000000 through 0x20082000) and must - be word-aligned. */ - __IOM uint16_t OTPBOOT_DST1; /*!< Bits 31:16 of the OTP boot image load destination (and entry - point). (ECC) This must be a location in main SRAM (main - SRAM is addresses 0x20000000 through 0x20082000) and must - be word-aligned. */ - __IM uint16_t RESERVED6[30]; - __IOM uint16_t BOOTKEY0_0; /*!< Bits 15:0 of SHA-256 hash of boot key 0 (ECC) */ - __IOM uint16_t BOOTKEY0_1; /*!< Bits 31:16 of SHA-256 hash of boot key 0 (ECC) */ - __IOM uint16_t BOOTKEY0_2; /*!< Bits 47:32 of SHA-256 hash of boot key 0 (ECC) */ - __IOM uint16_t BOOTKEY0_3; /*!< Bits 63:48 of SHA-256 hash of boot key 0 (ECC) */ - __IOM uint16_t BOOTKEY0_4; /*!< Bits 79:64 of SHA-256 hash of boot key 0 (ECC) */ - __IOM uint16_t BOOTKEY0_5; /*!< Bits 95:80 of SHA-256 hash of boot key 0 (ECC) */ - __IOM uint16_t BOOTKEY0_6; /*!< Bits 111:96 of SHA-256 hash of boot key 0 (ECC) */ - __IOM uint16_t BOOTKEY0_7; /*!< Bits 127:112 of SHA-256 hash of boot key 0 (ECC) */ - __IOM uint16_t BOOTKEY0_8; /*!< Bits 143:128 of SHA-256 hash of boot key 0 (ECC) */ - __IOM uint16_t BOOTKEY0_9; /*!< Bits 159:144 of SHA-256 hash of boot key 0 (ECC) */ - __IOM uint16_t BOOTKEY0_10; /*!< Bits 175:160 of SHA-256 hash of boot key 0 (ECC) */ - __IOM uint16_t BOOTKEY0_11; /*!< Bits 191:176 of SHA-256 hash of boot key 0 (ECC) */ - __IOM uint16_t BOOTKEY0_12; /*!< Bits 207:192 of SHA-256 hash of boot key 0 (ECC) */ - __IOM uint16_t BOOTKEY0_13; /*!< Bits 223:208 of SHA-256 hash of boot key 0 (ECC) */ - __IOM uint16_t BOOTKEY0_14; /*!< Bits 239:224 of SHA-256 hash of boot key 0 (ECC) */ - __IOM uint16_t BOOTKEY0_15; /*!< Bits 255:240 of SHA-256 hash of boot key 0 (ECC) */ - __IOM uint16_t BOOTKEY1_0; /*!< Bits 15:0 of SHA-256 hash of boot key 1 (ECC) */ - __IOM uint16_t BOOTKEY1_1; /*!< Bits 31:16 of SHA-256 hash of boot key 1 (ECC) */ - __IOM uint16_t BOOTKEY1_2; /*!< Bits 47:32 of SHA-256 hash of boot key 1 (ECC) */ - __IOM uint16_t BOOTKEY1_3; /*!< Bits 63:48 of SHA-256 hash of boot key 1 (ECC) */ - __IOM uint16_t BOOTKEY1_4; /*!< Bits 79:64 of SHA-256 hash of boot key 1 (ECC) */ - __IOM uint16_t BOOTKEY1_5; /*!< Bits 95:80 of SHA-256 hash of boot key 1 (ECC) */ - __IOM uint16_t BOOTKEY1_6; /*!< Bits 111:96 of SHA-256 hash of boot key 1 (ECC) */ - __IOM uint16_t BOOTKEY1_7; /*!< Bits 127:112 of SHA-256 hash of boot key 1 (ECC) */ - __IOM uint16_t BOOTKEY1_8; /*!< Bits 143:128 of SHA-256 hash of boot key 1 (ECC) */ - __IOM uint16_t BOOTKEY1_9; /*!< Bits 159:144 of SHA-256 hash of boot key 1 (ECC) */ - __IOM uint16_t BOOTKEY1_10; /*!< Bits 175:160 of SHA-256 hash of boot key 1 (ECC) */ - __IOM uint16_t BOOTKEY1_11; /*!< Bits 191:176 of SHA-256 hash of boot key 1 (ECC) */ - __IOM uint16_t BOOTKEY1_12; /*!< Bits 207:192 of SHA-256 hash of boot key 1 (ECC) */ - __IOM uint16_t BOOTKEY1_13; /*!< Bits 223:208 of SHA-256 hash of boot key 1 (ECC) */ - __IOM uint16_t BOOTKEY1_14; /*!< Bits 239:224 of SHA-256 hash of boot key 1 (ECC) */ - __IOM uint16_t BOOTKEY1_15; /*!< Bits 255:240 of SHA-256 hash of boot key 1 (ECC) */ - __IOM uint16_t BOOTKEY2_0; /*!< Bits 15:0 of SHA-256 hash of boot key 2 (ECC) */ - __IOM uint16_t BOOTKEY2_1; /*!< Bits 31:16 of SHA-256 hash of boot key 2 (ECC) */ - __IOM uint16_t BOOTKEY2_2; /*!< Bits 47:32 of SHA-256 hash of boot key 2 (ECC) */ - __IOM uint16_t BOOTKEY2_3; /*!< Bits 63:48 of SHA-256 hash of boot key 2 (ECC) */ - __IOM uint16_t BOOTKEY2_4; /*!< Bits 79:64 of SHA-256 hash of boot key 2 (ECC) */ - __IOM uint16_t BOOTKEY2_5; /*!< Bits 95:80 of SHA-256 hash of boot key 2 (ECC) */ - __IOM uint16_t BOOTKEY2_6; /*!< Bits 111:96 of SHA-256 hash of boot key 2 (ECC) */ - __IOM uint16_t BOOTKEY2_7; /*!< Bits 127:112 of SHA-256 hash of boot key 2 (ECC) */ - __IOM uint16_t BOOTKEY2_8; /*!< Bits 143:128 of SHA-256 hash of boot key 2 (ECC) */ - __IOM uint16_t BOOTKEY2_9; /*!< Bits 159:144 of SHA-256 hash of boot key 2 (ECC) */ - __IOM uint16_t BOOTKEY2_10; /*!< Bits 175:160 of SHA-256 hash of boot key 2 (ECC) */ - __IOM uint16_t BOOTKEY2_11; /*!< Bits 191:176 of SHA-256 hash of boot key 2 (ECC) */ - __IOM uint16_t BOOTKEY2_12; /*!< Bits 207:192 of SHA-256 hash of boot key 2 (ECC) */ - __IOM uint16_t BOOTKEY2_13; /*!< Bits 223:208 of SHA-256 hash of boot key 2 (ECC) */ - __IOM uint16_t BOOTKEY2_14; /*!< Bits 239:224 of SHA-256 hash of boot key 2 (ECC) */ - __IOM uint16_t BOOTKEY2_15; /*!< Bits 255:240 of SHA-256 hash of boot key 2 (ECC) */ - __IOM uint16_t BOOTKEY3_0; /*!< Bits 15:0 of SHA-256 hash of boot key 3 (ECC) */ - __IOM uint16_t BOOTKEY3_1; /*!< Bits 31:16 of SHA-256 hash of boot key 3 (ECC) */ - __IOM uint16_t BOOTKEY3_2; /*!< Bits 47:32 of SHA-256 hash of boot key 3 (ECC) */ - __IOM uint16_t BOOTKEY3_3; /*!< Bits 63:48 of SHA-256 hash of boot key 3 (ECC) */ - __IOM uint16_t BOOTKEY3_4; /*!< Bits 79:64 of SHA-256 hash of boot key 3 (ECC) */ - __IOM uint16_t BOOTKEY3_5; /*!< Bits 95:80 of SHA-256 hash of boot key 3 (ECC) */ - __IOM uint16_t BOOTKEY3_6; /*!< Bits 111:96 of SHA-256 hash of boot key 3 (ECC) */ - __IOM uint16_t BOOTKEY3_7; /*!< Bits 127:112 of SHA-256 hash of boot key 3 (ECC) */ - __IOM uint16_t BOOTKEY3_8; /*!< Bits 143:128 of SHA-256 hash of boot key 3 (ECC) */ - __IOM uint16_t BOOTKEY3_9; /*!< Bits 159:144 of SHA-256 hash of boot key 3 (ECC) */ - __IOM uint16_t BOOTKEY3_10; /*!< Bits 175:160 of SHA-256 hash of boot key 3 (ECC) */ - __IOM uint16_t BOOTKEY3_11; /*!< Bits 191:176 of SHA-256 hash of boot key 3 (ECC) */ - __IOM uint16_t BOOTKEY3_12; /*!< Bits 207:192 of SHA-256 hash of boot key 3 (ECC) */ - __IOM uint16_t BOOTKEY3_13; /*!< Bits 223:208 of SHA-256 hash of boot key 3 (ECC) */ - __IOM uint16_t BOOTKEY3_14; /*!< Bits 239:224 of SHA-256 hash of boot key 3 (ECC) */ - __IOM uint16_t BOOTKEY3_15; /*!< Bits 255:240 of SHA-256 hash of boot key 3 (ECC) */ - __IM uint16_t RESERVED7[3720]; - __IOM uint16_t KEY1_0; /*!< Bits 15:0 of OTP access key 1 (ECC) */ - __IOM uint16_t KEY1_1; /*!< Bits 31:16 of OTP access key 1 (ECC) */ - __IOM uint16_t KEY1_2; /*!< Bits 47:32 of OTP access key 1 (ECC) */ - __IOM uint16_t KEY1_3; /*!< Bits 63:48 of OTP access key 1 (ECC) */ - __IOM uint16_t KEY1_4; /*!< Bits 79:64 of OTP access key 1 (ECC) */ - __IOM uint16_t KEY1_5; /*!< Bits 95:80 of OTP access key 1 (ECC) */ - __IOM uint16_t KEY1_6; /*!< Bits 111:96 of OTP access key 1 (ECC) */ - __IOM uint16_t KEY1_7; /*!< Bits 127:112 of OTP access key 1 (ECC) */ - __IOM uint16_t KEY2_0; /*!< Bits 15:0 of OTP access key 2 (ECC) */ - __IOM uint16_t KEY2_1; /*!< Bits 31:16 of OTP access key 2 (ECC) */ - __IOM uint16_t KEY2_2; /*!< Bits 47:32 of OTP access key 2 (ECC) */ - __IOM uint16_t KEY2_3; /*!< Bits 63:48 of OTP access key 2 (ECC) */ - __IOM uint16_t KEY2_4; /*!< Bits 79:64 of OTP access key 2 (ECC) */ - __IOM uint16_t KEY2_5; /*!< Bits 95:80 of OTP access key 2 (ECC) */ - __IOM uint16_t KEY2_6; /*!< Bits 111:96 of OTP access key 2 (ECC) */ - __IOM uint16_t KEY2_7; /*!< Bits 127:112 of OTP access key 2 (ECC) */ - __IOM uint16_t KEY3_0; /*!< Bits 15:0 of OTP access key 3 (ECC) */ - __IOM uint16_t KEY3_1; /*!< Bits 31:16 of OTP access key 3 (ECC) */ - __IOM uint16_t KEY3_2; /*!< Bits 47:32 of OTP access key 3 (ECC) */ - __IOM uint16_t KEY3_3; /*!< Bits 63:48 of OTP access key 3 (ECC) */ - __IOM uint16_t KEY3_4; /*!< Bits 79:64 of OTP access key 3 (ECC) */ - __IOM uint16_t KEY3_5; /*!< Bits 95:80 of OTP access key 3 (ECC) */ - __IOM uint16_t KEY3_6; /*!< Bits 111:96 of OTP access key 3 (ECC) */ - __IOM uint16_t KEY3_7; /*!< Bits 127:112 of OTP access key 3 (ECC) */ - __IOM uint16_t KEY4_0; /*!< Bits 15:0 of OTP access key 4 (ECC) */ - __IOM uint16_t KEY4_1; /*!< Bits 31:16 of OTP access key 4 (ECC) */ - __IOM uint16_t KEY4_2; /*!< Bits 47:32 of OTP access key 4 (ECC) */ - __IOM uint16_t KEY4_3; /*!< Bits 63:48 of OTP access key 4 (ECC) */ - __IOM uint16_t KEY4_4; /*!< Bits 79:64 of OTP access key 4 (ECC) */ - __IOM uint16_t KEY4_5; /*!< Bits 95:80 of OTP access key 4 (ECC) */ - __IOM uint16_t KEY4_6; /*!< Bits 111:96 of OTP access key 4 (ECC) */ - __IOM uint16_t KEY4_7; /*!< Bits 127:112 of OTP access key 4 (ECC) */ - __IOM uint16_t KEY5_0; /*!< Bits 15:0 of OTP access key 5 (ECC) */ - __IOM uint16_t KEY5_1; /*!< Bits 31:16 of OTP access key 5 (ECC) */ - __IOM uint16_t KEY5_2; /*!< Bits 47:32 of OTP access key 5 (ECC) */ - __IOM uint16_t KEY5_3; /*!< Bits 63:48 of OTP access key 5 (ECC) */ - __IOM uint16_t KEY5_4; /*!< Bits 79:64 of OTP access key 5 (ECC) */ - __IOM uint16_t KEY5_5; /*!< Bits 95:80 of OTP access key 5 (ECC) */ - __IOM uint16_t KEY5_6; /*!< Bits 111:96 of OTP access key 5 (ECC) */ - __IOM uint16_t KEY5_7; /*!< Bits 127:112 of OTP access key 5 (ECC) */ - __IOM uint16_t KEY6_0; /*!< Bits 15:0 of OTP access key 6 (ECC) */ - __IOM uint16_t KEY6_1; /*!< Bits 31:16 of OTP access key 6 (ECC) */ - __IOM uint16_t KEY6_2; /*!< Bits 47:32 of OTP access key 6 (ECC) */ - __IOM uint16_t KEY6_3; /*!< Bits 63:48 of OTP access key 6 (ECC) */ - __IOM uint16_t KEY6_4; /*!< Bits 79:64 of OTP access key 6 (ECC) */ - __IOM uint16_t KEY6_5; /*!< Bits 95:80 of OTP access key 6 (ECC) */ - __IOM uint16_t KEY6_6; /*!< Bits 111:96 of OTP access key 6 (ECC) */ - __IOM uint16_t KEY6_7; /*!< Bits 127:112 of OTP access key 6 (ECC) */ -} OTP_DATA_Type; /*!< Size = 7920 (0x1ef0) */ - - - -/* =========================================================================================================================== */ -/* ================ OTP_DATA_RAW ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief Predefined OTP data layout for RP2350 (OTP_DATA_RAW) - */ - -typedef struct { /*!< OTP_DATA_RAW Structure */ - __IOM uint32_t CHIPID0; /*!< Bits 15:0 of public device ID. (ECC) The CHIPID0..3 rows contain - a 64-bit random identifier for this chip, which can be - read from the USB bootloader PICOBOOT interface or from - the get_sys_info ROM API. The number of random bits makes - the occurrence of twins exceedingly unlikely: for example, - a fleet of a hundred million devices has a 99.97% probability - of no twinned IDs. This is estimated to be lower than the - occurrence of process errors in the assignment of sequential - random IDs, and for practical purposes CHIPID may be treated - as unique. */ - __IOM uint32_t CHIPID1; /*!< Bits 31:16 of public device ID (ECC) */ - __IOM uint32_t CHIPID2; /*!< Bits 47:32 of public device ID (ECC) */ - __IOM uint32_t CHIPID3; /*!< Bits 63:48 of public device ID (ECC) */ - __IOM uint32_t RANDID0; /*!< Bits 15:0 of private per-device random number (ECC) The RANDID0..7 - rows form a 128-bit random number generated during device - test. This ID is not exposed through the USB PICOBOOT GET_INFO - command or the ROM `get_sys_info()` API. However note that - the USB PICOBOOT OTP access point can read the entirety - of page 0, so this value is not meaningfully private unless - the USB PICOBOOT interface is disabled via the DISABLE_BOOTSEL_USB_PICOBO - T_IFC flag in BOOT_FLAGS0. */ - __IOM uint32_t RANDID1; /*!< Bits 31:16 of private per-device random number (ECC) */ - __IOM uint32_t RANDID2; /*!< Bits 47:32 of private per-device random number (ECC) */ - __IOM uint32_t RANDID3; /*!< Bits 63:48 of private per-device random number (ECC) */ - __IOM uint32_t RANDID4; /*!< Bits 79:64 of private per-device random number (ECC) */ - __IOM uint32_t RANDID5; /*!< Bits 95:80 of private per-device random number (ECC) */ - __IOM uint32_t RANDID6; /*!< Bits 111:96 of private per-device random number (ECC) */ - __IOM uint32_t RANDID7; /*!< Bits 127:112 of private per-device random number (ECC) */ - __IM uint32_t RESERVED[4]; - __IOM uint32_t ROSC_CALIB; /*!< Ring oscillator frequency in kHz, measured during manufacturing - (ECC) This is measured at 1.1 V, at room temperature, with - the ROSC configuration registers in their reset state. */ - __IOM uint32_t LPOSC_CALIB; /*!< Low-power oscillator frequency in Hz, measured during manufacturing - (ECC) This is measured at 1.1V, at room temperature, with - the LPOSC trim register in its reset state. */ - __IM uint32_t RESERVED1[6]; - __IOM uint32_t NUM_GPIOS; /*!< The number of main user GPIOs (bank 0). Should read 48 in the - QFN80 package, and 30 in the QFN60 package. (ECC) */ - __IM uint32_t RESERVED2[29]; - __IOM uint32_t INFO_CRC0; /*!< Lower 16 bits of CRC32 of OTP addresses 0x00 through 0x6b (polynomial - 0x4c11db7, input reflected, output reflected, seed all-ones, - final XOR all-ones) (ECC) */ - __IOM uint32_t INFO_CRC1; /*!< Upper 16 bits of CRC32 of OTP addresses 0x00 through 0x6b (ECC) */ - __IOM uint32_t CRIT0; /*!< Page 0 critical boot flags (RBIT-8) */ - __IOM uint32_t CRIT0_R1; /*!< Redundant copy of CRIT0 */ - __IOM uint32_t CRIT0_R2; /*!< Redundant copy of CRIT0 */ - __IOM uint32_t CRIT0_R3; /*!< Redundant copy of CRIT0 */ - __IOM uint32_t CRIT0_R4; /*!< Redundant copy of CRIT0 */ - __IOM uint32_t CRIT0_R5; /*!< Redundant copy of CRIT0 */ - __IOM uint32_t CRIT0_R6; /*!< Redundant copy of CRIT0 */ - __IOM uint32_t CRIT0_R7; /*!< Redundant copy of CRIT0 */ - __IOM uint32_t CRIT1; /*!< Page 1 critical boot flags (RBIT-8) */ - __IOM uint32_t CRIT1_R1; /*!< Redundant copy of CRIT1 */ - __IOM uint32_t CRIT1_R2; /*!< Redundant copy of CRIT1 */ - __IOM uint32_t CRIT1_R3; /*!< Redundant copy of CRIT1 */ - __IOM uint32_t CRIT1_R4; /*!< Redundant copy of CRIT1 */ - __IOM uint32_t CRIT1_R5; /*!< Redundant copy of CRIT1 */ - __IOM uint32_t CRIT1_R6; /*!< Redundant copy of CRIT1 */ - __IOM uint32_t CRIT1_R7; /*!< Redundant copy of CRIT1 */ - __IOM uint32_t BOOT_FLAGS0; /*!< Disable/Enable boot paths/features in the RP2350 mask ROM. Disables - always supersede enables. Enables are provided where there - are other configurations in OTP that must be valid. (RBIT-3) */ - __IOM uint32_t BOOT_FLAGS0_R1; /*!< Redundant copy of BOOT_FLAGS0 */ - __IOM uint32_t BOOT_FLAGS0_R2; /*!< Redundant copy of BOOT_FLAGS0 */ - __IOM uint32_t BOOT_FLAGS1; /*!< Disable/Enable boot paths/features in the RP2350 mask ROM. Disables - always supersede enables. Enables are provided where there - are other configurations in OTP that must be valid. (RBIT-3) */ - __IOM uint32_t BOOT_FLAGS1_R1; /*!< Redundant copy of BOOT_FLAGS1 */ - __IOM uint32_t BOOT_FLAGS1_R2; /*!< Redundant copy of BOOT_FLAGS1 */ - __IOM uint32_t DEFAULT_BOOT_VERSION0; /*!< Default boot version thermometer counter, bits 23:0 (RBIT-3) */ - __IOM uint32_t DEFAULT_BOOT_VERSION0_R1; /*!< Redundant copy of DEFAULT_BOOT_VERSION0 */ - __IOM uint32_t DEFAULT_BOOT_VERSION0_R2; /*!< Redundant copy of DEFAULT_BOOT_VERSION0 */ - __IOM uint32_t DEFAULT_BOOT_VERSION1; /*!< Default boot version thermometer counter, bits 47:24 (RBIT-3) */ - __IOM uint32_t DEFAULT_BOOT_VERSION1_R1; /*!< Redundant copy of DEFAULT_BOOT_VERSION1 */ - __IOM uint32_t DEFAULT_BOOT_VERSION1_R2; /*!< Redundant copy of DEFAULT_BOOT_VERSION1 */ - __IOM uint32_t FLASH_DEVINFO; /*!< Stores information about external flash device(s). (ECC) Assumed - to be valid if BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is set. */ - __IOM uint32_t FLASH_PARTITION_SLOT_SIZE; /*!< Gap between partition table slot 0 and slot 1 at the start of - flash (the default size is 4096 bytes) (ECC) Enabled by - the OVERRIDE_FLASH_PARTITION_SLOT_SIZE bit in BOOT_FLAGS, - the size is 4096 * (value + 1) */ - __IOM uint32_t BOOTSEL_LED_CFG; /*!< Pin configuration for LED status, used by USB bootloader. (ECC) - Must be valid if BOOT_FLAGS0_ENABLE_BOOTSEL_LED is set. */ - __IOM uint32_t BOOTSEL_PLL_CFG; /*!< Optional PLL configuration for BOOTSEL mode. (ECC) This should - be configured to produce an exact 48 MHz based on the crystal - oscillator frequency. User mode software may also use this - value to calculate the expected crystal frequency based - on an assumed 48 MHz PLL output. If no configuration is - given, the crystal is assumed to be 12 MHz. The PLL frequency - can be calculated as: PLL out = (XOSC frequency / (REFDIV+1)) - x FBDIV / (POSTDIV1 x POSTDIV2) Conversely the crystal - frequency can be calculated as: XOSC frequency = 48 MHz - x (REFDIV+1) x (POSTDIV1 x POSTDIV2) / FBDIV (Note the - +1 on REFDIV is because the value stored in this OTP location - is the actual divisor value minus one.) Used if and only - if ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG is set in BOOT_FLAGS0. - That bit should be set only after this row and BOOTSEL_XOSC_CFG - are both correctly programmed. */ - __IOM uint32_t BOOTSEL_XOSC_CFG; /*!< Non-default crystal oscillator configuration for the USB bootloader. - (ECC) These values may also be used by user code configuring - the crystal oscillator. Used if and only if ENABLE_BOOTSEL_NON_DEFAULT_PL - _XOSC_CFG is set in BOOT_FLAGS0. That bit should be set - only after this row and BOOTSEL_PLL_CFG are both correctly - programmed. */ - __IOM uint32_t USB_BOOT_FLAGS; /*!< USB boot specific feature flags (RBIT-3) */ - __IOM uint32_t USB_BOOT_FLAGS_R1; /*!< Redundant copy of USB_BOOT_FLAGS */ - __IOM uint32_t USB_BOOT_FLAGS_R2; /*!< Redundant copy of USB_BOOT_FLAGS */ - __IOM uint32_t USB_WHITE_LABEL_ADDR; /*!< Row index of the USB_WHITE_LABEL structure within OTP (ECC) - The table has 16 rows, each of which are also ECC and marked - valid by the corresponding valid bit in USB_BOOT_FLAGS - (ECC). The entries are either _VALUEs where the 16 bit - value is used as is, or _STRDEFs which acts as a pointers - to a string value. The value stored in a _STRDEF is two - separate bytes: The low seven bits of the first (LSB) byte - indicates the number of characters in the string, and the - top bit of the first (LSB) byte if set to indicate that - each character in the string is two bytes (Unicode) versus - one byte if unset. The second (MSB) byte represents the - location of the string data, and is encoded as the number - of rows from this USB_WHITE_LABEL_ADDR; i.e. the row of - the start of the string is USB_WHITE_LABEL_ADDR value + - msb_byte. In each case, the corresponding valid bit enables - replacing the default value for the corresponding item - provided by the boot rom. Note that Unicode _STRDEFs are - only supported for USB_DEVICE_PRODUCT_STRDEF, USB_DEVICE_SERIAL_NUMBER_ST - DEF and USB_DEVICE_MANUFACTURER_STRDEF. Unicode values - will be ignored if specified for other fields, and non-unicode - values for these three items will be converted to Unicode - characters by setting the upper 8 bits to zero. Note that - if the USB_WHITE_LABEL structure or the corresponding strings - are not readable by BOOTSEL mode based on OTP permissions, - or if alignment requirements are not met, then the corresponding - default values are used. The index values indicate where - each field is located (row USB_WHITE_LABEL_ADDR value + - index): */ - __IM uint32_t RESERVED3; - __IOM uint32_t OTPBOOT_SRC; /*!< OTP start row for the OTP boot image. (ECC) If OTP boot is enabled, - the bootrom will load from this location into SRAM and - then directly enter the loaded image. Note that the image - must be signed if SECURE_BOOT_ENABLE is set. The image - itself is assumed to be ECC-protected. This must be an - even number. Equivalently, the OTP boot image must start - at a word-aligned location in the ECC read data address - window. */ - __IOM uint32_t OTPBOOT_LEN; /*!< Length in rows of the OTP boot image. (ECC) OTPBOOT_LEN must - be even. The total image size must be a multiple of 4 bytes - (32 bits). */ - __IOM uint32_t OTPBOOT_DST0; /*!< Bits 15:0 of the OTP boot image load destination (and entry - point). (ECC) This must be a location in main SRAM (main - SRAM is addresses 0x20000000 through 0x20082000) and must - be word-aligned. */ - __IOM uint32_t OTPBOOT_DST1; /*!< Bits 31:16 of the OTP boot image load destination (and entry - point). (ECC) This must be a location in main SRAM (main - SRAM is addresses 0x20000000 through 0x20082000) and must - be word-aligned. */ - __IM uint32_t RESERVED4[30]; - __IOM uint32_t BOOTKEY0_0; /*!< Bits 15:0 of SHA-256 hash of boot key 0 (ECC) */ - __IOM uint32_t BOOTKEY0_1; /*!< Bits 31:16 of SHA-256 hash of boot key 0 (ECC) */ - __IOM uint32_t BOOTKEY0_2; /*!< Bits 47:32 of SHA-256 hash of boot key 0 (ECC) */ - __IOM uint32_t BOOTKEY0_3; /*!< Bits 63:48 of SHA-256 hash of boot key 0 (ECC) */ - __IOM uint32_t BOOTKEY0_4; /*!< Bits 79:64 of SHA-256 hash of boot key 0 (ECC) */ - __IOM uint32_t BOOTKEY0_5; /*!< Bits 95:80 of SHA-256 hash of boot key 0 (ECC) */ - __IOM uint32_t BOOTKEY0_6; /*!< Bits 111:96 of SHA-256 hash of boot key 0 (ECC) */ - __IOM uint32_t BOOTKEY0_7; /*!< Bits 127:112 of SHA-256 hash of boot key 0 (ECC) */ - __IOM uint32_t BOOTKEY0_8; /*!< Bits 143:128 of SHA-256 hash of boot key 0 (ECC) */ - __IOM uint32_t BOOTKEY0_9; /*!< Bits 159:144 of SHA-256 hash of boot key 0 (ECC) */ - __IOM uint32_t BOOTKEY0_10; /*!< Bits 175:160 of SHA-256 hash of boot key 0 (ECC) */ - __IOM uint32_t BOOTKEY0_11; /*!< Bits 191:176 of SHA-256 hash of boot key 0 (ECC) */ - __IOM uint32_t BOOTKEY0_12; /*!< Bits 207:192 of SHA-256 hash of boot key 0 (ECC) */ - __IOM uint32_t BOOTKEY0_13; /*!< Bits 223:208 of SHA-256 hash of boot key 0 (ECC) */ - __IOM uint32_t BOOTKEY0_14; /*!< Bits 239:224 of SHA-256 hash of boot key 0 (ECC) */ - __IOM uint32_t BOOTKEY0_15; /*!< Bits 255:240 of SHA-256 hash of boot key 0 (ECC) */ - __IOM uint32_t BOOTKEY1_0; /*!< Bits 15:0 of SHA-256 hash of boot key 1 (ECC) */ - __IOM uint32_t BOOTKEY1_1; /*!< Bits 31:16 of SHA-256 hash of boot key 1 (ECC) */ - __IOM uint32_t BOOTKEY1_2; /*!< Bits 47:32 of SHA-256 hash of boot key 1 (ECC) */ - __IOM uint32_t BOOTKEY1_3; /*!< Bits 63:48 of SHA-256 hash of boot key 1 (ECC) */ - __IOM uint32_t BOOTKEY1_4; /*!< Bits 79:64 of SHA-256 hash of boot key 1 (ECC) */ - __IOM uint32_t BOOTKEY1_5; /*!< Bits 95:80 of SHA-256 hash of boot key 1 (ECC) */ - __IOM uint32_t BOOTKEY1_6; /*!< Bits 111:96 of SHA-256 hash of boot key 1 (ECC) */ - __IOM uint32_t BOOTKEY1_7; /*!< Bits 127:112 of SHA-256 hash of boot key 1 (ECC) */ - __IOM uint32_t BOOTKEY1_8; /*!< Bits 143:128 of SHA-256 hash of boot key 1 (ECC) */ - __IOM uint32_t BOOTKEY1_9; /*!< Bits 159:144 of SHA-256 hash of boot key 1 (ECC) */ - __IOM uint32_t BOOTKEY1_10; /*!< Bits 175:160 of SHA-256 hash of boot key 1 (ECC) */ - __IOM uint32_t BOOTKEY1_11; /*!< Bits 191:176 of SHA-256 hash of boot key 1 (ECC) */ - __IOM uint32_t BOOTKEY1_12; /*!< Bits 207:192 of SHA-256 hash of boot key 1 (ECC) */ - __IOM uint32_t BOOTKEY1_13; /*!< Bits 223:208 of SHA-256 hash of boot key 1 (ECC) */ - __IOM uint32_t BOOTKEY1_14; /*!< Bits 239:224 of SHA-256 hash of boot key 1 (ECC) */ - __IOM uint32_t BOOTKEY1_15; /*!< Bits 255:240 of SHA-256 hash of boot key 1 (ECC) */ - __IOM uint32_t BOOTKEY2_0; /*!< Bits 15:0 of SHA-256 hash of boot key 2 (ECC) */ - __IOM uint32_t BOOTKEY2_1; /*!< Bits 31:16 of SHA-256 hash of boot key 2 (ECC) */ - __IOM uint32_t BOOTKEY2_2; /*!< Bits 47:32 of SHA-256 hash of boot key 2 (ECC) */ - __IOM uint32_t BOOTKEY2_3; /*!< Bits 63:48 of SHA-256 hash of boot key 2 (ECC) */ - __IOM uint32_t BOOTKEY2_4; /*!< Bits 79:64 of SHA-256 hash of boot key 2 (ECC) */ - __IOM uint32_t BOOTKEY2_5; /*!< Bits 95:80 of SHA-256 hash of boot key 2 (ECC) */ - __IOM uint32_t BOOTKEY2_6; /*!< Bits 111:96 of SHA-256 hash of boot key 2 (ECC) */ - __IOM uint32_t BOOTKEY2_7; /*!< Bits 127:112 of SHA-256 hash of boot key 2 (ECC) */ - __IOM uint32_t BOOTKEY2_8; /*!< Bits 143:128 of SHA-256 hash of boot key 2 (ECC) */ - __IOM uint32_t BOOTKEY2_9; /*!< Bits 159:144 of SHA-256 hash of boot key 2 (ECC) */ - __IOM uint32_t BOOTKEY2_10; /*!< Bits 175:160 of SHA-256 hash of boot key 2 (ECC) */ - __IOM uint32_t BOOTKEY2_11; /*!< Bits 191:176 of SHA-256 hash of boot key 2 (ECC) */ - __IOM uint32_t BOOTKEY2_12; /*!< Bits 207:192 of SHA-256 hash of boot key 2 (ECC) */ - __IOM uint32_t BOOTKEY2_13; /*!< Bits 223:208 of SHA-256 hash of boot key 2 (ECC) */ - __IOM uint32_t BOOTKEY2_14; /*!< Bits 239:224 of SHA-256 hash of boot key 2 (ECC) */ - __IOM uint32_t BOOTKEY2_15; /*!< Bits 255:240 of SHA-256 hash of boot key 2 (ECC) */ - __IOM uint32_t BOOTKEY3_0; /*!< Bits 15:0 of SHA-256 hash of boot key 3 (ECC) */ - __IOM uint32_t BOOTKEY3_1; /*!< Bits 31:16 of SHA-256 hash of boot key 3 (ECC) */ - __IOM uint32_t BOOTKEY3_2; /*!< Bits 47:32 of SHA-256 hash of boot key 3 (ECC) */ - __IOM uint32_t BOOTKEY3_3; /*!< Bits 63:48 of SHA-256 hash of boot key 3 (ECC) */ - __IOM uint32_t BOOTKEY3_4; /*!< Bits 79:64 of SHA-256 hash of boot key 3 (ECC) */ - __IOM uint32_t BOOTKEY3_5; /*!< Bits 95:80 of SHA-256 hash of boot key 3 (ECC) */ - __IOM uint32_t BOOTKEY3_6; /*!< Bits 111:96 of SHA-256 hash of boot key 3 (ECC) */ - __IOM uint32_t BOOTKEY3_7; /*!< Bits 127:112 of SHA-256 hash of boot key 3 (ECC) */ - __IOM uint32_t BOOTKEY3_8; /*!< Bits 143:128 of SHA-256 hash of boot key 3 (ECC) */ - __IOM uint32_t BOOTKEY3_9; /*!< Bits 159:144 of SHA-256 hash of boot key 3 (ECC) */ - __IOM uint32_t BOOTKEY3_10; /*!< Bits 175:160 of SHA-256 hash of boot key 3 (ECC) */ - __IOM uint32_t BOOTKEY3_11; /*!< Bits 191:176 of SHA-256 hash of boot key 3 (ECC) */ - __IOM uint32_t BOOTKEY3_12; /*!< Bits 207:192 of SHA-256 hash of boot key 3 (ECC) */ - __IOM uint32_t BOOTKEY3_13; /*!< Bits 223:208 of SHA-256 hash of boot key 3 (ECC) */ - __IOM uint32_t BOOTKEY3_14; /*!< Bits 239:224 of SHA-256 hash of boot key 3 (ECC) */ - __IOM uint32_t BOOTKEY3_15; /*!< Bits 255:240 of SHA-256 hash of boot key 3 (ECC) */ - __IM uint32_t RESERVED5[3720]; - __IOM uint32_t KEY1_0; /*!< Bits 15:0 of OTP access key 1 (ECC) */ - __IOM uint32_t KEY1_1; /*!< Bits 31:16 of OTP access key 1 (ECC) */ - __IOM uint32_t KEY1_2; /*!< Bits 47:32 of OTP access key 1 (ECC) */ - __IOM uint32_t KEY1_3; /*!< Bits 63:48 of OTP access key 1 (ECC) */ - __IOM uint32_t KEY1_4; /*!< Bits 79:64 of OTP access key 1 (ECC) */ - __IOM uint32_t KEY1_5; /*!< Bits 95:80 of OTP access key 1 (ECC) */ - __IOM uint32_t KEY1_6; /*!< Bits 111:96 of OTP access key 1 (ECC) */ - __IOM uint32_t KEY1_7; /*!< Bits 127:112 of OTP access key 1 (ECC) */ - __IOM uint32_t KEY2_0; /*!< Bits 15:0 of OTP access key 2 (ECC) */ - __IOM uint32_t KEY2_1; /*!< Bits 31:16 of OTP access key 2 (ECC) */ - __IOM uint32_t KEY2_2; /*!< Bits 47:32 of OTP access key 2 (ECC) */ - __IOM uint32_t KEY2_3; /*!< Bits 63:48 of OTP access key 2 (ECC) */ - __IOM uint32_t KEY2_4; /*!< Bits 79:64 of OTP access key 2 (ECC) */ - __IOM uint32_t KEY2_5; /*!< Bits 95:80 of OTP access key 2 (ECC) */ - __IOM uint32_t KEY2_6; /*!< Bits 111:96 of OTP access key 2 (ECC) */ - __IOM uint32_t KEY2_7; /*!< Bits 127:112 of OTP access key 2 (ECC) */ - __IOM uint32_t KEY3_0; /*!< Bits 15:0 of OTP access key 3 (ECC) */ - __IOM uint32_t KEY3_1; /*!< Bits 31:16 of OTP access key 3 (ECC) */ - __IOM uint32_t KEY3_2; /*!< Bits 47:32 of OTP access key 3 (ECC) */ - __IOM uint32_t KEY3_3; /*!< Bits 63:48 of OTP access key 3 (ECC) */ - __IOM uint32_t KEY3_4; /*!< Bits 79:64 of OTP access key 3 (ECC) */ - __IOM uint32_t KEY3_5; /*!< Bits 95:80 of OTP access key 3 (ECC) */ - __IOM uint32_t KEY3_6; /*!< Bits 111:96 of OTP access key 3 (ECC) */ - __IOM uint32_t KEY3_7; /*!< Bits 127:112 of OTP access key 3 (ECC) */ - __IOM uint32_t KEY4_0; /*!< Bits 15:0 of OTP access key 4 (ECC) */ - __IOM uint32_t KEY4_1; /*!< Bits 31:16 of OTP access key 4 (ECC) */ - __IOM uint32_t KEY4_2; /*!< Bits 47:32 of OTP access key 4 (ECC) */ - __IOM uint32_t KEY4_3; /*!< Bits 63:48 of OTP access key 4 (ECC) */ - __IOM uint32_t KEY4_4; /*!< Bits 79:64 of OTP access key 4 (ECC) */ - __IOM uint32_t KEY4_5; /*!< Bits 95:80 of OTP access key 4 (ECC) */ - __IOM uint32_t KEY4_6; /*!< Bits 111:96 of OTP access key 4 (ECC) */ - __IOM uint32_t KEY4_7; /*!< Bits 127:112 of OTP access key 4 (ECC) */ - __IOM uint32_t KEY5_0; /*!< Bits 15:0 of OTP access key 5 (ECC) */ - __IOM uint32_t KEY5_1; /*!< Bits 31:16 of OTP access key 5 (ECC) */ - __IOM uint32_t KEY5_2; /*!< Bits 47:32 of OTP access key 5 (ECC) */ - __IOM uint32_t KEY5_3; /*!< Bits 63:48 of OTP access key 5 (ECC) */ - __IOM uint32_t KEY5_4; /*!< Bits 79:64 of OTP access key 5 (ECC) */ - __IOM uint32_t KEY5_5; /*!< Bits 95:80 of OTP access key 5 (ECC) */ - __IOM uint32_t KEY5_6; /*!< Bits 111:96 of OTP access key 5 (ECC) */ - __IOM uint32_t KEY5_7; /*!< Bits 127:112 of OTP access key 5 (ECC) */ - __IOM uint32_t KEY6_0; /*!< Bits 15:0 of OTP access key 6 (ECC) */ - __IOM uint32_t KEY6_1; /*!< Bits 31:16 of OTP access key 6 (ECC) */ - __IOM uint32_t KEY6_2; /*!< Bits 47:32 of OTP access key 6 (ECC) */ - __IOM uint32_t KEY6_3; /*!< Bits 63:48 of OTP access key 6 (ECC) */ - __IOM uint32_t KEY6_4; /*!< Bits 79:64 of OTP access key 6 (ECC) */ - __IOM uint32_t KEY6_5; /*!< Bits 95:80 of OTP access key 6 (ECC) */ - __IOM uint32_t KEY6_6; /*!< Bits 111:96 of OTP access key 6 (ECC) */ - __IOM uint32_t KEY6_7; /*!< Bits 127:112 of OTP access key 6 (ECC) */ - __IM uint32_t RESERVED6; - __IOM uint32_t KEY1_VALID; /*!< Valid flag for key 1. Once the valid flag is set, the key can - no longer be read or written, and becomes a valid fixed - key for protecting OTP pages. */ - __IOM uint32_t KEY2_VALID; /*!< Valid flag for key 2. Once the valid flag is set, the key can - no longer be read or written, and becomes a valid fixed - key for protecting OTP pages. */ - __IOM uint32_t KEY3_VALID; /*!< Valid flag for key 3. Once the valid flag is set, the key can - no longer be read or written, and becomes a valid fixed - key for protecting OTP pages. */ - __IOM uint32_t KEY4_VALID; /*!< Valid flag for key 4. Once the valid flag is set, the key can - no longer be read or written, and becomes a valid fixed - key for protecting OTP pages. */ - __IOM uint32_t KEY5_VALID; /*!< Valid flag for key 5. Once the valid flag is set, the key can - no longer be read or written, and becomes a valid fixed - key for protecting OTP pages. */ - __IOM uint32_t KEY6_VALID; /*!< Valid flag for key 6. Once the valid flag is set, the key can - no longer be read or written, and becomes a valid fixed - key for protecting OTP pages. */ - __IM uint32_t RESERVED7; - __IOM uint32_t PAGE0_LOCK0; /*!< Lock configuration LSBs for page 0 (rows 0x0 through 0x3f). - Locks are stored with 3-way majority vote encoding, so - that bits can be set independently. This OTP location is - always readable, and is write-protected by its own permissions. */ - __IOM uint32_t PAGE0_LOCK1; /*!< Lock configuration MSBs for page 0 (rows 0x0 through 0x3f). - Locks are stored with 3-way majority vote encoding, so - that bits can be set independently. This OTP location is - always readable, and is write-protected by its own permissions. */ - __IOM uint32_t PAGE1_LOCK0; /*!< Lock configuration LSBs for page 1 (rows 0x40 through 0x7f). - Locks are stored with 3-way majority vote encoding, so - that bits can be set independently. This OTP location is - always readable, and is write-protected by its own permissions. */ - __IOM uint32_t PAGE1_LOCK1; /*!< Lock configuration MSBs for page 1 (rows 0x40 through 0x7f). - Locks are stored with 3-way majority vote encoding, so - that bits can be set independently. This OTP location is - always readable, and is write-protected by its own permissions. */ - __IOM uint32_t PAGE2_LOCK0; /*!< Lock configuration LSBs for page 2 (rows 0x80 through 0xbf). - Locks are stored with 3-way majority vote encoding, so - that bits can be set independently. This OTP location is - always readable, and is write-protected by its own permissions. */ - __IOM uint32_t PAGE2_LOCK1; /*!< Lock configuration MSBs for page 2 (rows 0x80 through 0xbf). - Locks are stored with 3-way majority vote encoding, so - that bits can be set independently. This OTP location is - always readable, and is write-protected by its own permissions. */ - __IOM uint32_t PAGE3_LOCK0; /*!< Lock configuration LSBs for page 3 (rows 0xc0 through 0xff). - Locks are stored with 3-way majority vote encoding, so - that bits can be set independently. This OTP location is - always readable, and is write-protected by its own permissions. */ - __IOM uint32_t PAGE3_LOCK1; /*!< Lock configuration MSBs for page 3 (rows 0xc0 through 0xff). - Locks are stored with 3-way majority vote encoding, so - that bits can be set independently. This OTP location is - always readable, and is write-protected by its own permissions. */ - __IOM uint32_t PAGE4_LOCK0; /*!< Lock configuration LSBs for page 4 (rows 0x100 through 0x13f). - Locks are stored with 3-way majority vote encoding, so - that bits can be set independently. This OTP location is - always readable, and is write-protected by its own permissions. */ - __IOM uint32_t PAGE4_LOCK1; /*!< Lock configuration MSBs for page 4 (rows 0x100 through 0x13f). - Locks are stored with 3-way majority vote encoding, so - that bits can be set independently. This OTP location is - always readable, and is write-protected by its own permissions. */ - __IOM uint32_t PAGE5_LOCK0; /*!< Lock configuration LSBs for page 5 (rows 0x140 through 0x17f). - Locks are stored with 3-way majority vote encoding, so - that bits can be set independently. This OTP location is - always readable, and is write-protected by its own permissions. */ - __IOM uint32_t PAGE5_LOCK1; /*!< Lock configuration MSBs for page 5 (rows 0x140 through 0x17f). - Locks are stored with 3-way majority vote encoding, so - that bits can be set independently. This OTP location is - always readable, and is write-protected by its own permissions. */ - __IOM uint32_t PAGE6_LOCK0; /*!< Lock configuration LSBs for page 6 (rows 0x180 through 0x1bf). - Locks are stored with 3-way majority vote encoding, so - that bits can be set independently. This OTP location is - always readable, and is write-protected by its own permissions. */ - __IOM uint32_t PAGE6_LOCK1; /*!< Lock configuration MSBs for page 6 (rows 0x180 through 0x1bf). - Locks are stored with 3-way majority vote encoding, so - that bits can be set independently. This OTP location is - always readable, and is write-protected by its own permissions. */ - __IOM uint32_t PAGE7_LOCK0; /*!< Lock configuration LSBs for page 7 (rows 0x1c0 through 0x1ff). - Locks are stored with 3-way majority vote encoding, so - that bits can be set independently. This OTP location is - always readable, and is write-protected by its own permissions. */ - __IOM uint32_t PAGE7_LOCK1; /*!< Lock configuration MSBs for page 7 (rows 0x1c0 through 0x1ff). - Locks are stored with 3-way majority vote encoding, so - that bits can be set independently. This OTP location is - always readable, and is write-protected by its own permissions. */ - __IOM uint32_t PAGE8_LOCK0; /*!< Lock configuration LSBs for page 8 (rows 0x200 through 0x23f). - Locks are stored with 3-way majority vote encoding, so - that bits can be set independently. This OTP location is - always readable, and is write-protected by its own permissions. */ - __IOM uint32_t PAGE8_LOCK1; /*!< Lock configuration MSBs for page 8 (rows 0x200 through 0x23f). - Locks are stored with 3-way majority vote encoding, so - that bits can be set independently. This OTP location is - always readable, and is write-protected by its own permissions. */ - __IOM uint32_t PAGE9_LOCK0; /*!< Lock configuration LSBs for page 9 (rows 0x240 through 0x27f). - Locks are stored with 3-way majority vote encoding, so - that bits can be set independently. This OTP location is - always readable, and is write-protected by its own permissions. */ - __IOM uint32_t PAGE9_LOCK1; /*!< Lock configuration MSBs for page 9 (rows 0x240 through 0x27f). - Locks are stored with 3-way majority vote encoding, so - that bits can be set independently. This OTP location is - always readable, and is write-protected by its own permissions. */ - __IOM uint32_t PAGE10_LOCK0; /*!< Lock configuration LSBs for page 10 (rows 0x280 through 0x2bf). - Locks are stored with 3-way majority vote encoding, so - that bits can be set independently. This OTP location is - always readable, and is write-protected by its own permissions. */ - __IOM uint32_t PAGE10_LOCK1; /*!< Lock configuration MSBs for page 10 (rows 0x280 through 0x2bf). - Locks are stored with 3-way majority vote encoding, so - that bits can be set independently. This OTP location is - always readable, and is write-protected by its own permissions. */ - __IOM uint32_t PAGE11_LOCK0; /*!< Lock configuration LSBs for page 11 (rows 0x2c0 through 0x2ff). - Locks are stored with 3-way majority vote encoding, so - that bits can be set independently. This OTP location is - always readable, and is write-protected by its own permissions. */ - __IOM uint32_t PAGE11_LOCK1; /*!< Lock configuration MSBs for page 11 (rows 0x2c0 through 0x2ff). - Locks are stored with 3-way majority vote encoding, so - that bits can be set independently. This OTP location is - always readable, and is write-protected by its own permissions. */ - __IOM uint32_t PAGE12_LOCK0; /*!< Lock configuration LSBs for page 12 (rows 0x300 through 0x33f). - Locks are stored with 3-way majority vote encoding, so - that bits can be set independently. This OTP location is - always readable, and is write-protected by its own permissions. */ - __IOM uint32_t PAGE12_LOCK1; /*!< Lock configuration MSBs for page 12 (rows 0x300 through 0x33f). - Locks are stored with 3-way majority vote encoding, so - that bits can be set independently. This OTP location is - always readable, and is write-protected by its own permissions. */ - __IOM uint32_t PAGE13_LOCK0; /*!< Lock configuration LSBs for page 13 (rows 0x340 through 0x37f). - Locks are stored with 3-way majority vote encoding, so - that bits can be set independently. This OTP location is - always readable, and is write-protected by its own permissions. */ - __IOM uint32_t PAGE13_LOCK1; /*!< Lock configuration MSBs for page 13 (rows 0x340 through 0x37f). - Locks are stored with 3-way majority vote encoding, so - that bits can be set independently. This OTP location is - always readable, and is write-protected by its own permissions. */ - __IOM uint32_t PAGE14_LOCK0; /*!< Lock configuration LSBs for page 14 (rows 0x380 through 0x3bf). - Locks are stored with 3-way majority vote encoding, so - that bits can be set independently. This OTP location is - always readable, and is write-protected by its own permissions. */ - __IOM uint32_t PAGE14_LOCK1; /*!< Lock configuration MSBs for page 14 (rows 0x380 through 0x3bf). - Locks are stored with 3-way majority vote encoding, so - that bits can be set independently. This OTP location is - always readable, and is write-protected by its own permissions. */ - __IOM uint32_t PAGE15_LOCK0; /*!< Lock configuration LSBs for page 15 (rows 0x3c0 through 0x3ff). - Locks are stored with 3-way majority vote encoding, so - that bits can be set independently. This OTP location is - always readable, and is write-protected by its own permissions. */ - __IOM uint32_t PAGE15_LOCK1; /*!< Lock configuration MSBs for page 15 (rows 0x3c0 through 0x3ff). - Locks are stored with 3-way majority vote encoding, so - that bits can be set independently. This OTP location is - always readable, and is write-protected by its own permissions. */ - __IOM uint32_t PAGE16_LOCK0; /*!< Lock configuration LSBs for page 16 (rows 0x400 through 0x43f). - Locks are stored with 3-way majority vote encoding, so - that bits can be set independently. This OTP location is - always readable, and is write-protected by its own permissions. */ - __IOM uint32_t PAGE16_LOCK1; /*!< Lock configuration MSBs for page 16 (rows 0x400 through 0x43f). - Locks are stored with 3-way majority vote encoding, so - that bits can be set independently. This OTP location is - always readable, and is write-protected by its own permissions. */ - __IOM uint32_t PAGE17_LOCK0; /*!< Lock configuration LSBs for page 17 (rows 0x440 through 0x47f). - Locks are stored with 3-way majority vote encoding, so - that bits can be set independently. This OTP location is - always readable, and is write-protected by its own permissions. */ - __IOM uint32_t PAGE17_LOCK1; /*!< Lock configuration MSBs for page 17 (rows 0x440 through 0x47f). - Locks are stored with 3-way majority vote encoding, so - that bits can be set independently. This OTP location is - always readable, and is write-protected by its own permissions. */ - __IOM uint32_t PAGE18_LOCK0; /*!< Lock configuration LSBs for page 18 (rows 0x480 through 0x4bf). - Locks are stored with 3-way majority vote encoding, so - that bits can be set independently. This OTP location is - always readable, and is write-protected by its own permissions. */ - __IOM uint32_t PAGE18_LOCK1; /*!< Lock configuration MSBs for page 18 (rows 0x480 through 0x4bf). - Locks are stored with 3-way majority vote encoding, so - that bits can be set independently. This OTP location is - always readable, and is write-protected by its own permissions. */ - __IOM uint32_t PAGE19_LOCK0; /*!< Lock configuration LSBs for page 19 (rows 0x4c0 through 0x4ff). - Locks are stored with 3-way majority vote encoding, so - that bits can be set independently. This OTP location is - always readable, and is write-protected by its own permissions. */ - __IOM uint32_t PAGE19_LOCK1; /*!< Lock configuration MSBs for page 19 (rows 0x4c0 through 0x4ff). - Locks are stored with 3-way majority vote encoding, so - that bits can be set independently. This OTP location is - always readable, and is write-protected by its own permissions. */ - __IOM uint32_t PAGE20_LOCK0; /*!< Lock configuration LSBs for page 20 (rows 0x500 through 0x53f). - Locks are stored with 3-way majority vote encoding, so - that bits can be set independently. This OTP location is - always readable, and is write-protected by its own permissions. */ - __IOM uint32_t PAGE20_LOCK1; /*!< Lock configuration MSBs for page 20 (rows 0x500 through 0x53f). - Locks are stored with 3-way majority vote encoding, so - that bits can be set independently. This OTP location is - always readable, and is write-protected by its own permissions. */ - __IOM uint32_t PAGE21_LOCK0; /*!< Lock configuration LSBs for page 21 (rows 0x540 through 0x57f). - Locks are stored with 3-way majority vote encoding, so - that bits can be set independently. This OTP location is - always readable, and is write-protected by its own permissions. */ - __IOM uint32_t PAGE21_LOCK1; /*!< Lock configuration MSBs for page 21 (rows 0x540 through 0x57f). - Locks are stored with 3-way majority vote encoding, so - that bits can be set independently. This OTP location is - always readable, and is write-protected by its own permissions. */ - __IOM uint32_t PAGE22_LOCK0; /*!< Lock configuration LSBs for page 22 (rows 0x580 through 0x5bf). - Locks are stored with 3-way majority vote encoding, so - that bits can be set independently. This OTP location is - always readable, and is write-protected by its own permissions. */ - __IOM uint32_t PAGE22_LOCK1; /*!< Lock configuration MSBs for page 22 (rows 0x580 through 0x5bf). - Locks are stored with 3-way majority vote encoding, so - that bits can be set independently. This OTP location is - always readable, and is write-protected by its own permissions. */ - __IOM uint32_t PAGE23_LOCK0; /*!< Lock configuration LSBs for page 23 (rows 0x5c0 through 0x5ff). - Locks are stored with 3-way majority vote encoding, so - that bits can be set independently. This OTP location is - always readable, and is write-protected by its own permissions. */ - __IOM uint32_t PAGE23_LOCK1; /*!< Lock configuration MSBs for page 23 (rows 0x5c0 through 0x5ff). - Locks are stored with 3-way majority vote encoding, so - that bits can be set independently. This OTP location is - always readable, and is write-protected by its own permissions. */ - __IOM uint32_t PAGE24_LOCK0; /*!< Lock configuration LSBs for page 24 (rows 0x600 through 0x63f). - Locks are stored with 3-way majority vote encoding, so - that bits can be set independently. This OTP location is - always readable, and is write-protected by its own permissions. */ - __IOM uint32_t PAGE24_LOCK1; /*!< Lock configuration MSBs for page 24 (rows 0x600 through 0x63f). - Locks are stored with 3-way majority vote encoding, so - that bits can be set independently. This OTP location is - always readable, and is write-protected by its own permissions. */ - __IOM uint32_t PAGE25_LOCK0; /*!< Lock configuration LSBs for page 25 (rows 0x640 through 0x67f). - Locks are stored with 3-way majority vote encoding, so - that bits can be set independently. This OTP location is - always readable, and is write-protected by its own permissions. */ - __IOM uint32_t PAGE25_LOCK1; /*!< Lock configuration MSBs for page 25 (rows 0x640 through 0x67f). - Locks are stored with 3-way majority vote encoding, so - that bits can be set independently. This OTP location is - always readable, and is write-protected by its own permissions. */ - __IOM uint32_t PAGE26_LOCK0; /*!< Lock configuration LSBs for page 26 (rows 0x680 through 0x6bf). - Locks are stored with 3-way majority vote encoding, so - that bits can be set independently. This OTP location is - always readable, and is write-protected by its own permissions. */ - __IOM uint32_t PAGE26_LOCK1; /*!< Lock configuration MSBs for page 26 (rows 0x680 through 0x6bf). - Locks are stored with 3-way majority vote encoding, so - that bits can be set independently. This OTP location is - always readable, and is write-protected by its own permissions. */ - __IOM uint32_t PAGE27_LOCK0; /*!< Lock configuration LSBs for page 27 (rows 0x6c0 through 0x6ff). - Locks are stored with 3-way majority vote encoding, so - that bits can be set independently. This OTP location is - always readable, and is write-protected by its own permissions. */ - __IOM uint32_t PAGE27_LOCK1; /*!< Lock configuration MSBs for page 27 (rows 0x6c0 through 0x6ff). - Locks are stored with 3-way majority vote encoding, so - that bits can be set independently. This OTP location is - always readable, and is write-protected by its own permissions. */ - __IOM uint32_t PAGE28_LOCK0; /*!< Lock configuration LSBs for page 28 (rows 0x700 through 0x73f). - Locks are stored with 3-way majority vote encoding, so - that bits can be set independently. This OTP location is - always readable, and is write-protected by its own permissions. */ - __IOM uint32_t PAGE28_LOCK1; /*!< Lock configuration MSBs for page 28 (rows 0x700 through 0x73f). - Locks are stored with 3-way majority vote encoding, so - that bits can be set independently. This OTP location is - always readable, and is write-protected by its own permissions. */ - __IOM uint32_t PAGE29_LOCK0; /*!< Lock configuration LSBs for page 29 (rows 0x740 through 0x77f). - Locks are stored with 3-way majority vote encoding, so - that bits can be set independently. This OTP location is - always readable, and is write-protected by its own permissions. */ - __IOM uint32_t PAGE29_LOCK1; /*!< Lock configuration MSBs for page 29 (rows 0x740 through 0x77f). - Locks are stored with 3-way majority vote encoding, so - that bits can be set independently. This OTP location is - always readable, and is write-protected by its own permissions. */ - __IOM uint32_t PAGE30_LOCK0; /*!< Lock configuration LSBs for page 30 (rows 0x780 through 0x7bf). - Locks are stored with 3-way majority vote encoding, so - that bits can be set independently. This OTP location is - always readable, and is write-protected by its own permissions. */ - __IOM uint32_t PAGE30_LOCK1; /*!< Lock configuration MSBs for page 30 (rows 0x780 through 0x7bf). - Locks are stored with 3-way majority vote encoding, so - that bits can be set independently. This OTP location is - always readable, and is write-protected by its own permissions. */ - __IOM uint32_t PAGE31_LOCK0; /*!< Lock configuration LSBs for page 31 (rows 0x7c0 through 0x7ff). - Locks are stored with 3-way majority vote encoding, so - that bits can be set independently. This OTP location is - always readable, and is write-protected by its own permissions. */ - __IOM uint32_t PAGE31_LOCK1; /*!< Lock configuration MSBs for page 31 (rows 0x7c0 through 0x7ff). - Locks are stored with 3-way majority vote encoding, so - that bits can be set independently. This OTP location is - always readable, and is write-protected by its own permissions. */ - __IOM uint32_t PAGE32_LOCK0; /*!< Lock configuration LSBs for page 32 (rows 0x800 through 0x83f). - Locks are stored with 3-way majority vote encoding, so - that bits can be set independently. This OTP location is - always readable, and is write-protected by its own permissions. */ - __IOM uint32_t PAGE32_LOCK1; /*!< Lock configuration MSBs for page 32 (rows 0x800 through 0x83f). - Locks are stored with 3-way majority vote encoding, so - that bits can be set independently. This OTP location is - always readable, and is write-protected by its own permissions. */ - __IOM uint32_t PAGE33_LOCK0; /*!< Lock configuration LSBs for page 33 (rows 0x840 through 0x87f). - Locks are stored with 3-way majority vote encoding, so - that bits can be set independently. This OTP location is - always readable, and is write-protected by its own permissions. */ - __IOM uint32_t PAGE33_LOCK1; /*!< Lock configuration MSBs for page 33 (rows 0x840 through 0x87f). - Locks are stored with 3-way majority vote encoding, so - that bits can be set independently. This OTP location is - always readable, and is write-protected by its own permissions. */ - __IOM uint32_t PAGE34_LOCK0; /*!< Lock configuration LSBs for page 34 (rows 0x880 through 0x8bf). - Locks are stored with 3-way majority vote encoding, so - that bits can be set independently. This OTP location is - always readable, and is write-protected by its own permissions. */ - __IOM uint32_t PAGE34_LOCK1; /*!< Lock configuration MSBs for page 34 (rows 0x880 through 0x8bf). - Locks are stored with 3-way majority vote encoding, so - that bits can be set independently. This OTP location is - always readable, and is write-protected by its own permissions. */ - __IOM uint32_t PAGE35_LOCK0; /*!< Lock configuration LSBs for page 35 (rows 0x8c0 through 0x8ff). - Locks are stored with 3-way majority vote encoding, so - that bits can be set independently. This OTP location is - always readable, and is write-protected by its own permissions. */ - __IOM uint32_t PAGE35_LOCK1; /*!< Lock configuration MSBs for page 35 (rows 0x8c0 through 0x8ff). - Locks are stored with 3-way majority vote encoding, so - that bits can be set independently. This OTP location is - always readable, and is write-protected by its own permissions. */ - __IOM uint32_t PAGE36_LOCK0; /*!< Lock configuration LSBs for page 36 (rows 0x900 through 0x93f). - Locks are stored with 3-way majority vote encoding, so - that bits can be set independently. This OTP location is - always readable, and is write-protected by its own permissions. */ - __IOM uint32_t PAGE36_LOCK1; /*!< Lock configuration MSBs for page 36 (rows 0x900 through 0x93f). - Locks are stored with 3-way majority vote encoding, so - that bits can be set independently. This OTP location is - always readable, and is write-protected by its own permissions. */ - __IOM uint32_t PAGE37_LOCK0; /*!< Lock configuration LSBs for page 37 (rows 0x940 through 0x97f). - Locks are stored with 3-way majority vote encoding, so - that bits can be set independently. This OTP location is - always readable, and is write-protected by its own permissions. */ - __IOM uint32_t PAGE37_LOCK1; /*!< Lock configuration MSBs for page 37 (rows 0x940 through 0x97f). - Locks are stored with 3-way majority vote encoding, so - that bits can be set independently. This OTP location is - always readable, and is write-protected by its own permissions. */ - __IOM uint32_t PAGE38_LOCK0; /*!< Lock configuration LSBs for page 38 (rows 0x980 through 0x9bf). - Locks are stored with 3-way majority vote encoding, so - that bits can be set independently. This OTP location is - always readable, and is write-protected by its own permissions. */ - __IOM uint32_t PAGE38_LOCK1; /*!< Lock configuration MSBs for page 38 (rows 0x980 through 0x9bf). - Locks are stored with 3-way majority vote encoding, so - that bits can be set independently. This OTP location is - always readable, and is write-protected by its own permissions. */ - __IOM uint32_t PAGE39_LOCK0; /*!< Lock configuration LSBs for page 39 (rows 0x9c0 through 0x9ff). - Locks are stored with 3-way majority vote encoding, so - that bits can be set independently. This OTP location is - always readable, and is write-protected by its own permissions. */ - __IOM uint32_t PAGE39_LOCK1; /*!< Lock configuration MSBs for page 39 (rows 0x9c0 through 0x9ff). - Locks are stored with 3-way majority vote encoding, so - that bits can be set independently. This OTP location is - always readable, and is write-protected by its own permissions. */ - __IOM uint32_t PAGE40_LOCK0; /*!< Lock configuration LSBs for page 40 (rows 0xa00 through 0xa3f). - Locks are stored with 3-way majority vote encoding, so - that bits can be set independently. This OTP location is - always readable, and is write-protected by its own permissions. */ - __IOM uint32_t PAGE40_LOCK1; /*!< Lock configuration MSBs for page 40 (rows 0xa00 through 0xa3f). - Locks are stored with 3-way majority vote encoding, so - that bits can be set independently. This OTP location is - always readable, and is write-protected by its own permissions. */ - __IOM uint32_t PAGE41_LOCK0; /*!< Lock configuration LSBs for page 41 (rows 0xa40 through 0xa7f). - Locks are stored with 3-way majority vote encoding, so - that bits can be set independently. This OTP location is - always readable, and is write-protected by its own permissions. */ - __IOM uint32_t PAGE41_LOCK1; /*!< Lock configuration MSBs for page 41 (rows 0xa40 through 0xa7f). - Locks are stored with 3-way majority vote encoding, so - that bits can be set independently. This OTP location is - always readable, and is write-protected by its own permissions. */ - __IOM uint32_t PAGE42_LOCK0; /*!< Lock configuration LSBs for page 42 (rows 0xa80 through 0xabf). - Locks are stored with 3-way majority vote encoding, so - that bits can be set independently. This OTP location is - always readable, and is write-protected by its own permissions. */ - __IOM uint32_t PAGE42_LOCK1; /*!< Lock configuration MSBs for page 42 (rows 0xa80 through 0xabf). - Locks are stored with 3-way majority vote encoding, so - that bits can be set independently. This OTP location is - always readable, and is write-protected by its own permissions. */ - __IOM uint32_t PAGE43_LOCK0; /*!< Lock configuration LSBs for page 43 (rows 0xac0 through 0xaff). - Locks are stored with 3-way majority vote encoding, so - that bits can be set independently. This OTP location is - always readable, and is write-protected by its own permissions. */ - __IOM uint32_t PAGE43_LOCK1; /*!< Lock configuration MSBs for page 43 (rows 0xac0 through 0xaff). - Locks are stored with 3-way majority vote encoding, so - that bits can be set independently. This OTP location is - always readable, and is write-protected by its own permissions. */ - __IOM uint32_t PAGE44_LOCK0; /*!< Lock configuration LSBs for page 44 (rows 0xb00 through 0xb3f). - Locks are stored with 3-way majority vote encoding, so - that bits can be set independently. This OTP location is - always readable, and is write-protected by its own permissions. */ - __IOM uint32_t PAGE44_LOCK1; /*!< Lock configuration MSBs for page 44 (rows 0xb00 through 0xb3f). - Locks are stored with 3-way majority vote encoding, so - that bits can be set independently. This OTP location is - always readable, and is write-protected by its own permissions. */ - __IOM uint32_t PAGE45_LOCK0; /*!< Lock configuration LSBs for page 45 (rows 0xb40 through 0xb7f). - Locks are stored with 3-way majority vote encoding, so - that bits can be set independently. This OTP location is - always readable, and is write-protected by its own permissions. */ - __IOM uint32_t PAGE45_LOCK1; /*!< Lock configuration MSBs for page 45 (rows 0xb40 through 0xb7f). - Locks are stored with 3-way majority vote encoding, so - that bits can be set independently. This OTP location is - always readable, and is write-protected by its own permissions. */ - __IOM uint32_t PAGE46_LOCK0; /*!< Lock configuration LSBs for page 46 (rows 0xb80 through 0xbbf). - Locks are stored with 3-way majority vote encoding, so - that bits can be set independently. This OTP location is - always readable, and is write-protected by its own permissions. */ - __IOM uint32_t PAGE46_LOCK1; /*!< Lock configuration MSBs for page 46 (rows 0xb80 through 0xbbf). - Locks are stored with 3-way majority vote encoding, so - that bits can be set independently. This OTP location is - always readable, and is write-protected by its own permissions. */ - __IOM uint32_t PAGE47_LOCK0; /*!< Lock configuration LSBs for page 47 (rows 0xbc0 through 0xbff). - Locks are stored with 3-way majority vote encoding, so - that bits can be set independently. This OTP location is - always readable, and is write-protected by its own permissions. */ - __IOM uint32_t PAGE47_LOCK1; /*!< Lock configuration MSBs for page 47 (rows 0xbc0 through 0xbff). - Locks are stored with 3-way majority vote encoding, so - that bits can be set independently. This OTP location is - always readable, and is write-protected by its own permissions. */ - __IOM uint32_t PAGE48_LOCK0; /*!< Lock configuration LSBs for page 48 (rows 0xc00 through 0xc3f). - Locks are stored with 3-way majority vote encoding, so - that bits can be set independently. This OTP location is - always readable, and is write-protected by its own permissions. */ - __IOM uint32_t PAGE48_LOCK1; /*!< Lock configuration MSBs for page 48 (rows 0xc00 through 0xc3f). - Locks are stored with 3-way majority vote encoding, so - that bits can be set independently. This OTP location is - always readable, and is write-protected by its own permissions. */ - __IOM uint32_t PAGE49_LOCK0; /*!< Lock configuration LSBs for page 49 (rows 0xc40 through 0xc7f). - Locks are stored with 3-way majority vote encoding, so - that bits can be set independently. This OTP location is - always readable, and is write-protected by its own permissions. */ - __IOM uint32_t PAGE49_LOCK1; /*!< Lock configuration MSBs for page 49 (rows 0xc40 through 0xc7f). - Locks are stored with 3-way majority vote encoding, so - that bits can be set independently. This OTP location is - always readable, and is write-protected by its own permissions. */ - __IOM uint32_t PAGE50_LOCK0; /*!< Lock configuration LSBs for page 50 (rows 0xc80 through 0xcbf). - Locks are stored with 3-way majority vote encoding, so - that bits can be set independently. This OTP location is - always readable, and is write-protected by its own permissions. */ - __IOM uint32_t PAGE50_LOCK1; /*!< Lock configuration MSBs for page 50 (rows 0xc80 through 0xcbf). - Locks are stored with 3-way majority vote encoding, so - that bits can be set independently. This OTP location is - always readable, and is write-protected by its own permissions. */ - __IOM uint32_t PAGE51_LOCK0; /*!< Lock configuration LSBs for page 51 (rows 0xcc0 through 0xcff). - Locks are stored with 3-way majority vote encoding, so - that bits can be set independently. This OTP location is - always readable, and is write-protected by its own permissions. */ - __IOM uint32_t PAGE51_LOCK1; /*!< Lock configuration MSBs for page 51 (rows 0xcc0 through 0xcff). - Locks are stored with 3-way majority vote encoding, so - that bits can be set independently. This OTP location is - always readable, and is write-protected by its own permissions. */ - __IOM uint32_t PAGE52_LOCK0; /*!< Lock configuration LSBs for page 52 (rows 0xd00 through 0xd3f). - Locks are stored with 3-way majority vote encoding, so - that bits can be set independently. This OTP location is - always readable, and is write-protected by its own permissions. */ - __IOM uint32_t PAGE52_LOCK1; /*!< Lock configuration MSBs for page 52 (rows 0xd00 through 0xd3f). - Locks are stored with 3-way majority vote encoding, so - that bits can be set independently. This OTP location is - always readable, and is write-protected by its own permissions. */ - __IOM uint32_t PAGE53_LOCK0; /*!< Lock configuration LSBs for page 53 (rows 0xd40 through 0xd7f). - Locks are stored with 3-way majority vote encoding, so - that bits can be set independently. This OTP location is - always readable, and is write-protected by its own permissions. */ - __IOM uint32_t PAGE53_LOCK1; /*!< Lock configuration MSBs for page 53 (rows 0xd40 through 0xd7f). - Locks are stored with 3-way majority vote encoding, so - that bits can be set independently. This OTP location is - always readable, and is write-protected by its own permissions. */ - __IOM uint32_t PAGE54_LOCK0; /*!< Lock configuration LSBs for page 54 (rows 0xd80 through 0xdbf). - Locks are stored with 3-way majority vote encoding, so - that bits can be set independently. This OTP location is - always readable, and is write-protected by its own permissions. */ - __IOM uint32_t PAGE54_LOCK1; /*!< Lock configuration MSBs for page 54 (rows 0xd80 through 0xdbf). - Locks are stored with 3-way majority vote encoding, so - that bits can be set independently. This OTP location is - always readable, and is write-protected by its own permissions. */ - __IOM uint32_t PAGE55_LOCK0; /*!< Lock configuration LSBs for page 55 (rows 0xdc0 through 0xdff). - Locks are stored with 3-way majority vote encoding, so - that bits can be set independently. This OTP location is - always readable, and is write-protected by its own permissions. */ - __IOM uint32_t PAGE55_LOCK1; /*!< Lock configuration MSBs for page 55 (rows 0xdc0 through 0xdff). - Locks are stored with 3-way majority vote encoding, so - that bits can be set independently. This OTP location is - always readable, and is write-protected by its own permissions. */ - __IOM uint32_t PAGE56_LOCK0; /*!< Lock configuration LSBs for page 56 (rows 0xe00 through 0xe3f). - Locks are stored with 3-way majority vote encoding, so - that bits can be set independently. This OTP location is - always readable, and is write-protected by its own permissions. */ - __IOM uint32_t PAGE56_LOCK1; /*!< Lock configuration MSBs for page 56 (rows 0xe00 through 0xe3f). - Locks are stored with 3-way majority vote encoding, so - that bits can be set independently. This OTP location is - always readable, and is write-protected by its own permissions. */ - __IOM uint32_t PAGE57_LOCK0; /*!< Lock configuration LSBs for page 57 (rows 0xe40 through 0xe7f). - Locks are stored with 3-way majority vote encoding, so - that bits can be set independently. This OTP location is - always readable, and is write-protected by its own permissions. */ - __IOM uint32_t PAGE57_LOCK1; /*!< Lock configuration MSBs for page 57 (rows 0xe40 through 0xe7f). - Locks are stored with 3-way majority vote encoding, so - that bits can be set independently. This OTP location is - always readable, and is write-protected by its own permissions. */ - __IOM uint32_t PAGE58_LOCK0; /*!< Lock configuration LSBs for page 58 (rows 0xe80 through 0xebf). - Locks are stored with 3-way majority vote encoding, so - that bits can be set independently. This OTP location is - always readable, and is write-protected by its own permissions. */ - __IOM uint32_t PAGE58_LOCK1; /*!< Lock configuration MSBs for page 58 (rows 0xe80 through 0xebf). - Locks are stored with 3-way majority vote encoding, so - that bits can be set independently. This OTP location is - always readable, and is write-protected by its own permissions. */ - __IOM uint32_t PAGE59_LOCK0; /*!< Lock configuration LSBs for page 59 (rows 0xec0 through 0xeff). - Locks are stored with 3-way majority vote encoding, so - that bits can be set independently. This OTP location is - always readable, and is write-protected by its own permissions. */ - __IOM uint32_t PAGE59_LOCK1; /*!< Lock configuration MSBs for page 59 (rows 0xec0 through 0xeff). - Locks are stored with 3-way majority vote encoding, so - that bits can be set independently. This OTP location is - always readable, and is write-protected by its own permissions. */ - __IOM uint32_t PAGE60_LOCK0; /*!< Lock configuration LSBs for page 60 (rows 0xf00 through 0xf3f). - Locks are stored with 3-way majority vote encoding, so - that bits can be set independently. This OTP location is - always readable, and is write-protected by its own permissions. */ - __IOM uint32_t PAGE60_LOCK1; /*!< Lock configuration MSBs for page 60 (rows 0xf00 through 0xf3f). - Locks are stored with 3-way majority vote encoding, so - that bits can be set independently. This OTP location is - always readable, and is write-protected by its own permissions. */ - __IOM uint32_t PAGE61_LOCK0; /*!< Lock configuration LSBs for page 61 (rows 0xf40 through 0xf7f). - Locks are stored with 3-way majority vote encoding, so - that bits can be set independently. This OTP location is - always readable, and is write-protected by its own permissions. */ - __IOM uint32_t PAGE61_LOCK1; /*!< Lock configuration MSBs for page 61 (rows 0xf40 through 0xf7f). - Locks are stored with 3-way majority vote encoding, so - that bits can be set independently. This OTP location is - always readable, and is write-protected by its own permissions. */ - __IOM uint32_t PAGE62_LOCK0; /*!< Lock configuration LSBs for page 62 (rows 0xf80 through 0xfbf). - Locks are stored with 3-way majority vote encoding, so - that bits can be set independently. This OTP location is - always readable, and is write-protected by its own permissions. */ - __IOM uint32_t PAGE62_LOCK1; /*!< Lock configuration MSBs for page 62 (rows 0xf80 through 0xfbf). - Locks are stored with 3-way majority vote encoding, so - that bits can be set independently. This OTP location is - always readable, and is write-protected by its own permissions. */ - __IOM uint32_t PAGE63_LOCK0; /*!< Lock configuration LSBs for page 63 (rows 0xfc0 through 0xfff). - Locks are stored with 3-way majority vote encoding, so - that bits can be set independently. This OTP location is - always readable, and is write-protected by its own permissions. */ - __IOM uint32_t PAGE63_LOCK1; /*!< Lock configuration MSBs for page 63 (rows 0xfc0 through 0xfff). - Locks are stored with 3-way majority vote encoding, so - that bits can be set independently. This OTP location is - always readable, and is write-protected by its own permissions. */ -} OTP_DATA_RAW_Type; /*!< Size = 16384 (0x4000) */ - - - -/* =========================================================================================================================== */ -/* ================ TBMAN ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief For managing simulation testbenches (TBMAN) - */ - -typedef struct { /*!< TBMAN Structure */ - __IOM uint32_t PLATFORM; /*!< Indicates the type of platform in use */ -} TBMAN_Type; /*!< Size = 4 (0x4) */ - - - -/* =========================================================================================================================== */ -/* ================ USB_DPRAM ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief DPRAM layout for USB device. (USB_DPRAM) - */ - -typedef struct { /*!< USB_DPRAM Structure */ - __IOM uint32_t SETUP_PACKET_LOW; /*!< Bytes 0-3 of the SETUP packet from the host. */ - __IOM uint32_t SETUP_PACKET_HIGH; /*!< Bytes 4-7 of the setup packet from the host. */ - __IOM uint32_t EP1_IN_CONTROL; /*!< EP1_IN_CONTROL */ - __IOM uint32_t EP1_OUT_CONTROL; /*!< EP1_OUT_CONTROL */ - __IOM uint32_t EP2_IN_CONTROL; /*!< EP2_IN_CONTROL */ - __IOM uint32_t EP2_OUT_CONTROL; /*!< EP2_OUT_CONTROL */ - __IOM uint32_t EP3_IN_CONTROL; /*!< EP3_IN_CONTROL */ - __IOM uint32_t EP3_OUT_CONTROL; /*!< EP3_OUT_CONTROL */ - __IOM uint32_t EP4_IN_CONTROL; /*!< EP4_IN_CONTROL */ - __IOM uint32_t EP4_OUT_CONTROL; /*!< EP4_OUT_CONTROL */ - __IOM uint32_t EP5_IN_CONTROL; /*!< EP5_IN_CONTROL */ - __IOM uint32_t EP5_OUT_CONTROL; /*!< EP5_OUT_CONTROL */ - __IOM uint32_t EP6_IN_CONTROL; /*!< EP6_IN_CONTROL */ - __IOM uint32_t EP6_OUT_CONTROL; /*!< EP6_OUT_CONTROL */ - __IOM uint32_t EP7_IN_CONTROL; /*!< EP7_IN_CONTROL */ - __IOM uint32_t EP7_OUT_CONTROL; /*!< EP7_OUT_CONTROL */ - __IOM uint32_t EP8_IN_CONTROL; /*!< EP8_IN_CONTROL */ - __IOM uint32_t EP8_OUT_CONTROL; /*!< EP8_OUT_CONTROL */ - __IOM uint32_t EP9_IN_CONTROL; /*!< EP9_IN_CONTROL */ - __IOM uint32_t EP9_OUT_CONTROL; /*!< EP9_OUT_CONTROL */ - __IOM uint32_t EP10_IN_CONTROL; /*!< EP10_IN_CONTROL */ - __IOM uint32_t EP10_OUT_CONTROL; /*!< EP10_OUT_CONTROL */ - __IOM uint32_t EP11_IN_CONTROL; /*!< EP11_IN_CONTROL */ - __IOM uint32_t EP11_OUT_CONTROL; /*!< EP11_OUT_CONTROL */ - __IOM uint32_t EP12_IN_CONTROL; /*!< EP12_IN_CONTROL */ - __IOM uint32_t EP12_OUT_CONTROL; /*!< EP12_OUT_CONTROL */ - __IOM uint32_t EP13_IN_CONTROL; /*!< EP13_IN_CONTROL */ - __IOM uint32_t EP13_OUT_CONTROL; /*!< EP13_OUT_CONTROL */ - __IOM uint32_t EP14_IN_CONTROL; /*!< EP14_IN_CONTROL */ - __IOM uint32_t EP14_OUT_CONTROL; /*!< EP14_OUT_CONTROL */ - __IOM uint32_t EP15_IN_CONTROL; /*!< EP15_IN_CONTROL */ - __IOM uint32_t EP15_OUT_CONTROL; /*!< EP15_OUT_CONTROL */ - __IOM uint32_t EP0_IN_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending - in a _1 are for buffer 1. Fields ending in a _0 are for - buffer 0. Buffer 1 controls are only valid if the endpoint - is in double buffered mode. */ - __IOM uint32_t EP0_OUT_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending - in a _1 are for buffer 1. Fields ending in a _0 are for - buffer 0. Buffer 1 controls are only valid if the endpoint - is in double buffered mode. */ - __IOM uint32_t EP1_IN_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending - in a _1 are for buffer 1. Fields ending in a _0 are for - buffer 0. Buffer 1 controls are only valid if the endpoint - is in double buffered mode. */ - __IOM uint32_t EP1_OUT_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending - in a _1 are for buffer 1. Fields ending in a _0 are for - buffer 0. Buffer 1 controls are only valid if the endpoint - is in double buffered mode. */ - __IOM uint32_t EP2_IN_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending - in a _1 are for buffer 1. Fields ending in a _0 are for - buffer 0. Buffer 1 controls are only valid if the endpoint - is in double buffered mode. */ - __IOM uint32_t EP2_OUT_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending - in a _1 are for buffer 1. Fields ending in a _0 are for - buffer 0. Buffer 1 controls are only valid if the endpoint - is in double buffered mode. */ - __IOM uint32_t EP3_IN_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending - in a _1 are for buffer 1. Fields ending in a _0 are for - buffer 0. Buffer 1 controls are only valid if the endpoint - is in double buffered mode. */ - __IOM uint32_t EP3_OUT_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending - in a _1 are for buffer 1. Fields ending in a _0 are for - buffer 0. Buffer 1 controls are only valid if the endpoint - is in double buffered mode. */ - __IOM uint32_t EP4_IN_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending - in a _1 are for buffer 1. Fields ending in a _0 are for - buffer 0. Buffer 1 controls are only valid if the endpoint - is in double buffered mode. */ - __IOM uint32_t EP4_OUT_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending - in a _1 are for buffer 1. Fields ending in a _0 are for - buffer 0. Buffer 1 controls are only valid if the endpoint - is in double buffered mode. */ - __IOM uint32_t EP5_IN_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending - in a _1 are for buffer 1. Fields ending in a _0 are for - buffer 0. Buffer 1 controls are only valid if the endpoint - is in double buffered mode. */ - __IOM uint32_t EP5_OUT_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending - in a _1 are for buffer 1. Fields ending in a _0 are for - buffer 0. Buffer 1 controls are only valid if the endpoint - is in double buffered mode. */ - __IOM uint32_t EP6_IN_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending - in a _1 are for buffer 1. Fields ending in a _0 are for - buffer 0. Buffer 1 controls are only valid if the endpoint - is in double buffered mode. */ - __IOM uint32_t EP6_OUT_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending - in a _1 are for buffer 1. Fields ending in a _0 are for - buffer 0. Buffer 1 controls are only valid if the endpoint - is in double buffered mode. */ - __IOM uint32_t EP7_IN_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending - in a _1 are for buffer 1. Fields ending in a _0 are for - buffer 0. Buffer 1 controls are only valid if the endpoint - is in double buffered mode. */ - __IOM uint32_t EP7_OUT_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending - in a _1 are for buffer 1. Fields ending in a _0 are for - buffer 0. Buffer 1 controls are only valid if the endpoint - is in double buffered mode. */ - __IOM uint32_t EP8_IN_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending - in a _1 are for buffer 1. Fields ending in a _0 are for - buffer 0. Buffer 1 controls are only valid if the endpoint - is in double buffered mode. */ - __IOM uint32_t EP8_OUT_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending - in a _1 are for buffer 1. Fields ending in a _0 are for - buffer 0. Buffer 1 controls are only valid if the endpoint - is in double buffered mode. */ - __IOM uint32_t EP9_IN_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending - in a _1 are for buffer 1. Fields ending in a _0 are for - buffer 0. Buffer 1 controls are only valid if the endpoint - is in double buffered mode. */ - __IOM uint32_t EP9_OUT_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending - in a _1 are for buffer 1. Fields ending in a _0 are for - buffer 0. Buffer 1 controls are only valid if the endpoint - is in double buffered mode. */ - __IOM uint32_t EP10_IN_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending - in a _1 are for buffer 1. Fields ending in a _0 are for - buffer 0. Buffer 1 controls are only valid if the endpoint - is in double buffered mode. */ - __IOM uint32_t EP10_OUT_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending - in a _1 are for buffer 1. Fields ending in a _0 are for - buffer 0. Buffer 1 controls are only valid if the endpoint - is in double buffered mode. */ - __IOM uint32_t EP11_IN_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending - in a _1 are for buffer 1. Fields ending in a _0 are for - buffer 0. Buffer 1 controls are only valid if the endpoint - is in double buffered mode. */ - __IOM uint32_t EP11_OUT_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending - in a _1 are for buffer 1. Fields ending in a _0 are for - buffer 0. Buffer 1 controls are only valid if the endpoint - is in double buffered mode. */ - __IOM uint32_t EP12_IN_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending - in a _1 are for buffer 1. Fields ending in a _0 are for - buffer 0. Buffer 1 controls are only valid if the endpoint - is in double buffered mode. */ - __IOM uint32_t EP12_OUT_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending - in a _1 are for buffer 1. Fields ending in a _0 are for - buffer 0. Buffer 1 controls are only valid if the endpoint - is in double buffered mode. */ - __IOM uint32_t EP13_IN_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending - in a _1 are for buffer 1. Fields ending in a _0 are for - buffer 0. Buffer 1 controls are only valid if the endpoint - is in double buffered mode. */ - __IOM uint32_t EP13_OUT_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending - in a _1 are for buffer 1. Fields ending in a _0 are for - buffer 0. Buffer 1 controls are only valid if the endpoint - is in double buffered mode. */ - __IOM uint32_t EP14_IN_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending - in a _1 are for buffer 1. Fields ending in a _0 are for - buffer 0. Buffer 1 controls are only valid if the endpoint - is in double buffered mode. */ - __IOM uint32_t EP14_OUT_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending - in a _1 are for buffer 1. Fields ending in a _0 are for - buffer 0. Buffer 1 controls are only valid if the endpoint - is in double buffered mode. */ - __IOM uint32_t EP15_IN_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending - in a _1 are for buffer 1. Fields ending in a _0 are for - buffer 0. Buffer 1 controls are only valid if the endpoint - is in double buffered mode. */ - __IOM uint32_t EP15_OUT_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending - in a _1 are for buffer 1. Fields ending in a _0 are for - buffer 0. Buffer 1 controls are only valid if the endpoint - is in double buffered mode. */ -} USB_DPRAM_Type; /*!< Size = 256 (0x100) */ - - -/** @} */ /* End of group Device_Peripheral_peripherals */ - - -/* =========================================================================================================================== */ -/* ================ Device Specific Peripheral Address Map ================ */ -/* =========================================================================================================================== */ - - -/** @addtogroup Device_Peripheral_peripheralAddr - * @{ - */ - -#define RESETS_BASE 0x40020000UL -#define PSM_BASE 0x40018000UL -#define CLOCKS_BASE 0x40010000UL -#define TICKS_BASE 0x40108000UL -#define PADS_BANK0_BASE 0x40038000UL -#define PADS_QSPI_BASE 0x40040000UL -#define IO_QSPI_BASE 0x40030000UL -#define IO_BANK0_BASE 0x40028000UL -#define SYSINFO_BASE 0x40000000UL -#define SHA256_BASE 0x400F8000UL -#define HSTX_FIFO_BASE 0x50600000UL -#define HSTX_CTRL_BASE 0x400C0000UL -#define EPPB_BASE 0xE0080000UL -#define PPB_BASE 0xE0000000UL -#define PPB_NS_BASE 0xE0020000UL -#define QMI_BASE 0x400D0000UL -#define XIP_CTRL_BASE 0x400C8000UL -#define XIP_AUX_BASE 0x50500000UL -#define SYSCFG_BASE 0x40008000UL -#define XOSC_BASE 0x40048000UL -#define PLL_SYS_BASE 0x40050000UL -#define PLL_USB_BASE 0x40058000UL -#define ACCESSCTRL_BASE 0x40060000UL -#define UART0_BASE 0x40070000UL -#define UART1_BASE 0x40078000UL -#define ROSC_BASE 0x400E8000UL -#define POWMAN_BASE 0x40100000UL -#define WATCHDOG_BASE 0x400D8000UL -#define DMA_BASE 0x50000000UL -#define TIMER0_BASE 0x400B0000UL -#define TIMER1_BASE 0x400B8000UL -#define PWM_BASE 0x400A8000UL -#define ADC_BASE 0x400A0000UL -#define I2C0_BASE 0x40090000UL -#define I2C1_BASE 0x40098000UL -#define SPI0_BASE 0x40080000UL -#define SPI1_BASE 0x40088000UL -#define PIO0_BASE 0x50200000UL -#define PIO1_BASE 0x50300000UL -#define PIO2_BASE 0x50400000UL -#define BUSCTRL_BASE 0x40068000UL -#define SIO_BASE 0xD0000000UL -#define SIO_NS_BASE 0xD0020000UL -#define BOOTRAM_BASE 0x400E0000UL -#define CORESIGHT_TRACE_BASE 0x50700000UL -#define USB_BASE 0x50110000UL -#define TRNG_BASE 0x400F0000UL -#define GLITCH_DETECTOR_BASE 0x40158000UL -#define OTP_BASE 0x40120000UL -#define OTP_DATA_BASE 0x40130000UL -#define OTP_DATA_RAW_BASE 0x40134000UL -#define TBMAN_BASE 0x40160000UL -#define USB_DPRAM_BASE 0x50100000UL - -/** @} */ /* End of group Device_Peripheral_peripheralAddr */ - - -/* =========================================================================================================================== */ -/* ================ Peripheral declaration ================ */ -/* =========================================================================================================================== */ - - -/** @addtogroup Device_Peripheral_declaration - * @{ - */ - -#define RESETS ((RESETS_Type*) RESETS_BASE) -#define PSM ((PSM_Type*) PSM_BASE) -#define CLOCKS ((CLOCKS_Type*) CLOCKS_BASE) -#define TICKS ((TICKS_Type*) TICKS_BASE) -#define PADS_BANK0 ((PADS_BANK0_Type*) PADS_BANK0_BASE) -#define PADS_QSPI ((PADS_QSPI_Type*) PADS_QSPI_BASE) -#define IO_QSPI ((IO_QSPI_Type*) IO_QSPI_BASE) -#define IO_BANK0 ((IO_BANK0_Type*) IO_BANK0_BASE) -#define SYSINFO ((SYSINFO_Type*) SYSINFO_BASE) -#define SHA256 ((SHA256_Type*) SHA256_BASE) -#define HSTX_FIFO ((HSTX_FIFO_Type*) HSTX_FIFO_BASE) -#define HSTX_CTRL ((HSTX_CTRL_Type*) HSTX_CTRL_BASE) -#define EPPB ((EPPB_Type*) EPPB_BASE) -#define PPB ((PPB_Type*) PPB_BASE) -#define PPB_NS ((PPB_Type*) PPB_NS_BASE) -#define QMI ((QMI_Type*) QMI_BASE) -#define XIP_CTRL ((XIP_CTRL_Type*) XIP_CTRL_BASE) -#define XIP_AUX ((XIP_AUX_Type*) XIP_AUX_BASE) -#define SYSCFG ((SYSCFG_Type*) SYSCFG_BASE) -#define XOSC ((XOSC_Type*) XOSC_BASE) -#define PLL_SYS ((PLL_SYS_Type*) PLL_SYS_BASE) -#define PLL_USB ((PLL_SYS_Type*) PLL_USB_BASE) -#define ACCESSCTRL ((ACCESSCTRL_Type*) ACCESSCTRL_BASE) -#define UART0 ((UART0_Type*) UART0_BASE) -#define UART1 ((UART0_Type*) UART1_BASE) -#define ROSC ((ROSC_Type*) ROSC_BASE) -#define POWMAN ((POWMAN_Type*) POWMAN_BASE) -#define WATCHDOG ((WATCHDOG_Type*) WATCHDOG_BASE) -#define DMA ((DMA_Type*) DMA_BASE) -#define TIMER0 ((TIMER0_Type*) TIMER0_BASE) -#define TIMER1 ((TIMER0_Type*) TIMER1_BASE) -#define PWM ((PWM_Type*) PWM_BASE) -#define ADC ((ADC_Type*) ADC_BASE) -#define I2C0 ((I2C0_Type*) I2C0_BASE) -#define I2C1 ((I2C0_Type*) I2C1_BASE) -#define SPI0 ((SPI0_Type*) SPI0_BASE) -#define SPI1 ((SPI0_Type*) SPI1_BASE) -#define PIO0 ((PIO0_Type*) PIO0_BASE) -#define PIO1 ((PIO0_Type*) PIO1_BASE) -#define PIO2 ((PIO0_Type*) PIO2_BASE) -#define BUSCTRL ((BUSCTRL_Type*) BUSCTRL_BASE) -#define SIO ((SIO_Type*) SIO_BASE) -#define SIO_NS ((SIO_Type*) SIO_NS_BASE) -#define BOOTRAM ((BOOTRAM_Type*) BOOTRAM_BASE) -#define CORESIGHT_TRACE ((CORESIGHT_TRACE_Type*) CORESIGHT_TRACE_BASE) -#define USB ((USB_Type*) USB_BASE) -#define TRNG ((TRNG_Type*) TRNG_BASE) -#define GLITCH_DETECTOR ((GLITCH_DETECTOR_Type*) GLITCH_DETECTOR_BASE) -#define OTP ((OTP_Type*) OTP_BASE) -#define OTP_DATA ((OTP_DATA_Type*) OTP_DATA_BASE) -#define OTP_DATA_RAW ((OTP_DATA_RAW_Type*) OTP_DATA_RAW_BASE) -#define TBMAN ((TBMAN_Type*) TBMAN_BASE) -#define USB_DPRAM ((USB_DPRAM_Type*) USB_DPRAM_BASE) - -/** @} */ /* End of group Device_Peripheral_declaration */ - - -#ifdef __cplusplus -} -#endif - -#endif /* RP2350_H */ - - -/** @} */ /* End of group RP2350 */ - -/** @} */ /* End of group Raspberry Pi */ diff --git a/lib/main/pico-sdk/rp2_common/cmsis/stub/CMSIS/Device/RP2350/Include/system_RP2350.h b/lib/main/pico-sdk/rp2_common/cmsis/stub/CMSIS/Device/RP2350/Include/system_RP2350.h deleted file mode 100644 index d85fbeb6c2..0000000000 --- a/lib/main/pico-sdk/rp2_common/cmsis/stub/CMSIS/Device/RP2350/Include/system_RP2350.h +++ /dev/null @@ -1,65 +0,0 @@ -/*************************************************************************//** - * @file system_RP2350.h - * @brief CMSIS-Core(M) Device Peripheral Access Layer Header File for - * Device RP2350 - * @version V1.0.1 - * @date 6. Sep 2024 - *****************************************************************************/ -/* - * Copyright (c) 2009-2021 Arm Limited. All rights reserved. - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _CMSIS_SYSTEM_RP2350_H -#define _CMSIS_SYSTEM_RP2350_H - -#ifdef __cplusplus -extern "C" { -#endif - -/** - \brief Exception / Interrupt Handler Function Prototype -*/ -typedef void(*VECTOR_TABLE_Type)(void); - -/** - \brief System Clock Frequency (Core Clock) -*/ -extern uint32_t SystemCoreClock; - -/** - \brief Setup the microcontroller system. - - Initialize the System and update the SystemCoreClock variable. - */ -extern void SystemInit (void); - - -/** - \brief Update SystemCoreClock variable. - - Updates the SystemCoreClock with current core Clock retrieved from cpu registers. - */ -extern void SystemCoreClockUpdate (void); - -#ifdef __cplusplus -} -#endif - -#endif /* _CMSIS_SYSTEM_RP2350_H */ diff --git a/lib/main/pico-sdk/rp2_common/cmsis/stub/CMSIS/Device/RP2350/Source/system_RP2350.c b/lib/main/pico-sdk/rp2_common/cmsis/stub/CMSIS/Device/RP2350/Source/system_RP2350.c deleted file mode 100644 index 3dc2113460..0000000000 --- a/lib/main/pico-sdk/rp2_common/cmsis/stub/CMSIS/Device/RP2350/Source/system_RP2350.c +++ /dev/null @@ -1,52 +0,0 @@ -/*************************************************************************//** - * @file system_RP2350.c - * @brief CMSIS-Core(M) Device Peripheral Access Layer Header File for - * Device RP2350 - * @version V1.0.1 - * @date 6. Sep 2024 - *****************************************************************************/ -/* - * Copyright (c) 2009-2021 Arm Limited. All rights reserved. - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include "RP2350.h" -#include "hardware/clocks.h" - -/*--------------------------------------------------------------------------- - System Core Clock Variable - *---------------------------------------------------------------------------*/ -uint32_t SystemCoreClock; /* System Clock Frequency (Core Clock)*/ - -/*--------------------------------------------------------------------------- - System Core Clock function - *---------------------------------------------------------------------------*/ -void SystemCoreClockUpdate (void) -{ - SystemCoreClock = clock_get_hz(clk_sys); -} - -/*--------------------------------------------------------------------------- - System initialization function - *---------------------------------------------------------------------------*/ -void __attribute__((constructor)) SystemInit (void) -{ - SystemCoreClockUpdate(); -} diff --git a/lib/main/pico-sdk/rp2_common/cmsis/stub/CMSIS/LICENSE.txt b/lib/main/pico-sdk/rp2_common/cmsis/stub/CMSIS/LICENSE.txt deleted file mode 100644 index 8dada3edaf..0000000000 --- a/lib/main/pico-sdk/rp2_common/cmsis/stub/CMSIS/LICENSE.txt +++ /dev/null @@ -1,201 +0,0 @@ - Apache License - Version 2.0, January 2004 - http://www.apache.org/licenses/ - - TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION - - 1. Definitions. - - "License" shall mean the terms and conditions for use, reproduction, - and distribution as defined by Sections 1 through 9 of this document. - - "Licensor" shall mean the copyright owner or entity authorized by - the copyright owner that is granting the License. - - "Legal Entity" shall mean the union of the acting entity and all - other entities that control, are controlled by, or are under common - control with that entity. For the purposes of this definition, - "control" means (i) the power, direct or indirect, to cause the - direction or management of such entity, whether by contract or - otherwise, or (ii) ownership of fifty percent (50%) or more of the - outstanding shares, or (iii) beneficial ownership of such entity. - - "You" (or "Your") shall mean an individual or Legal Entity - exercising permissions granted by this License. - - "Source" form shall mean the preferred form for making modifications, - including but not limited to software source code, documentation - source, and configuration files. - - "Object" form shall mean any form resulting from mechanical - transformation or translation of a Source form, including but - not limited to compiled object code, generated documentation, - and conversions to other media types. - - "Work" shall mean the work of authorship, whether in Source or - Object form, made available under the License, as indicated by a - copyright notice that is included in or attached to the work - (an example is provided in the Appendix below). - - "Derivative Works" shall mean any work, whether in Source or Object - form, that is based on (or derived from) the Work and for which the - editorial revisions, annotations, elaborations, or other modifications - represent, as a whole, an original work of authorship. For the purposes - of this License, Derivative Works shall not include works that remain - separable from, or merely link (or bind by name) to the interfaces of, - the Work and Derivative Works thereof. - - "Contribution" shall mean any work of authorship, including - the original version of the Work and any modifications or additions - to that Work or Derivative Works thereof, that is intentionally - submitted to Licensor for inclusion in the Work by the copyright owner - or by an individual or Legal Entity authorized to submit on behalf of - the copyright owner. For the purposes of this definition, "submitted" - means any form of electronic, verbal, or written communication sent - to the Licensor or its representatives, including but not limited to - communication on electronic mailing lists, source code control systems, - and issue tracking systems that are managed by, or on behalf of, the - Licensor for the purpose of discussing and improving the Work, but - excluding communication that is conspicuously marked or otherwise - designated in writing by the copyright owner as "Not a Contribution." - - "Contributor" shall mean Licensor and any individual or Legal Entity - on behalf of whom a Contribution has been received by Licensor and - subsequently incorporated within the Work. - - 2. Grant of Copyright License. Subject to the terms and conditions of - this License, each Contributor hereby grants to You a perpetual, - worldwide, non-exclusive, no-charge, royalty-free, irrevocable - copyright license to reproduce, prepare Derivative Works of, - publicly display, publicly perform, sublicense, and distribute the - Work and such Derivative Works in Source or Object form. - - 3. Grant of Patent License. Subject to the terms and conditions of - this License, each Contributor hereby grants to You a perpetual, - worldwide, non-exclusive, no-charge, royalty-free, irrevocable - (except as stated in this section) patent license to make, have made, - use, offer to sell, sell, import, and otherwise transfer the Work, - where such license applies only to those patent claims licensable - by such Contributor that are necessarily infringed by their - Contribution(s) alone or by combination of their Contribution(s) - with the Work to which such Contribution(s) was submitted. If You - institute patent litigation against any entity (including a - cross-claim or counterclaim in a lawsuit) alleging that the Work - or a Contribution incorporated within the Work constitutes direct - or contributory patent infringement, then any patent licenses - granted to You under this License for that Work shall terminate - as of the date such litigation is filed. - - 4. Redistribution. You may reproduce and distribute copies of the - Work or Derivative Works thereof in any medium, with or without - modifications, and in Source or Object form, provided that You - meet the following conditions: - - (a) You must give any other recipients of the Work or - Derivative Works a copy of this License; and - - (b) You must cause any modified files to carry prominent notices - stating that You changed the files; and - - (c) You must retain, in the Source form of any Derivative Works - that You distribute, all copyright, patent, trademark, and - attribution notices from the Source form of the Work, - excluding those notices that do not pertain to any part of - the Derivative Works; and - - (d) If the Work includes a "NOTICE" text file as part of its - distribution, then any Derivative Works that You distribute must - include a readable copy of the attribution notices contained - within such NOTICE file, excluding those notices that do not - pertain to any part of the Derivative Works, in at least one - of the following places: within a NOTICE text file distributed - as part of the Derivative Works; within the Source form or - documentation, if provided along with the Derivative Works; or, - within a display generated by the Derivative Works, if and - wherever such third-party notices normally appear. The contents - of the NOTICE file are for informational purposes only and - do not modify the License. You may add Your own attribution - notices within Derivative Works that You distribute, alongside - or as an addendum to the NOTICE text from the Work, provided - that such additional attribution notices cannot be construed - as modifying the License. - - You may add Your own copyright statement to Your modifications and - may provide additional or different license terms and conditions - for use, reproduction, or distribution of Your modifications, or - for any such Derivative Works as a whole, provided Your use, - reproduction, and distribution of the Work otherwise complies with - the conditions stated in this License. - - 5. Submission of Contributions. Unless You explicitly state otherwise, - any Contribution intentionally submitted for inclusion in the Work - by You to the Licensor shall be under the terms and conditions of - this License, without any additional terms or conditions. - Notwithstanding the above, nothing herein shall supersede or modify - the terms of any separate license agreement you may have executed - with Licensor regarding such Contributions. - - 6. Trademarks. This License does not grant permission to use the trade - names, trademarks, service marks, or product names of the Licensor, - except as required for reasonable and customary use in describing the - origin of the Work and reproducing the content of the NOTICE file. - - 7. Disclaimer of Warranty. Unless required by applicable law or - agreed to in writing, Licensor provides the Work (and each - Contributor provides its Contributions) on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or - implied, including, without limitation, any warranties or conditions - of TITLE, NON-INFRINGEMENT, MERCHANTABILITY, or FITNESS FOR A - PARTICULAR PURPOSE. You are solely responsible for determining the - appropriateness of using or redistributing the Work and assume any - risks associated with Your exercise of permissions under this License. - - 8. Limitation of Liability. In no event and under no legal theory, - whether in tort (including negligence), contract, or otherwise, - unless required by applicable law (such as deliberate and grossly - negligent acts) or agreed to in writing, shall any Contributor be - liable to You for damages, including any direct, indirect, special, - incidental, or consequential damages of any character arising as a - result of this License or out of the use or inability to use the - Work (including but not limited to damages for loss of goodwill, - work stoppage, computer failure or malfunction, or any and all - other commercial damages or losses), even if such Contributor - has been advised of the possibility of such damages. - - 9. Accepting Warranty or Additional Liability. While redistributing - the Work or Derivative Works thereof, You may choose to offer, - and charge a fee for, acceptance of support, warranty, indemnity, - or other liability obligations and/or rights consistent with this - License. However, in accepting such obligations, You may act only - on Your own behalf and on Your sole responsibility, not on behalf - of any other Contributor, and only if You agree to indemnify, - defend, and hold each Contributor harmless for any liability - incurred by, or claims asserted against, such Contributor by reason - of your accepting any such warranty or additional liability. - - END OF TERMS AND CONDITIONS - - APPENDIX: How to apply the Apache License to your work. - - To apply the Apache License to your work, attach the following - boilerplate notice, with the fields enclosed by brackets "{}" - replaced with your own identifying information. (Don't include - the brackets!) The text should be enclosed in the appropriate - comment syntax for the file format. We also recommend that a - file or class name and description of purpose be included on the - same "printed page" as the copyright notice for easier - identification within third-party archives. - - Copyright {yyyy} {name of copyright owner} - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. diff --git a/lib/main/pico-sdk/rp2_common/hardware_adc/adc.c b/lib/main/pico-sdk/rp2_common/hardware_adc/adc.c deleted file mode 100644 index 7f7378d95e..0000000000 --- a/lib/main/pico-sdk/rp2_common/hardware_adc/adc.c +++ /dev/null @@ -1,22 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "pico.h" -#include "hardware/adc.h" -#include "hardware/resets.h" - -void adc_init(void) { - // ADC is in an unknown state. We should start by resetting it - reset_unreset_block_num_wait_blocking(RESET_ADC); - - // Now turn it back on. Staging of clock etc is handled internally - adc_hw->cs = ADC_CS_EN_BITS; - - // Internal staging completes in a few cycles, but poll to be sure - while (!(adc_hw->cs & ADC_CS_READY_BITS)) { - tight_loop_contents(); - } -} diff --git a/lib/main/pico-sdk/rp2_common/hardware_adc/include/hardware/adc.h b/lib/main/pico-sdk/rp2_common/hardware_adc/include/hardware/adc.h deleted file mode 100644 index 095a3f5b8f..0000000000 --- a/lib/main/pico-sdk/rp2_common/hardware_adc/include/hardware/adc.h +++ /dev/null @@ -1,309 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _HARDWARE_ADC_H -#define _HARDWARE_ADC_H - -#include "pico.h" -#include "hardware/structs/adc.h" -#include "hardware/gpio.h" - -/** \file hardware/adc.h - * \defgroup hardware_adc hardware_adc - * - * \brief Analog to Digital Converter (ADC) API - * - * RP-series microcontrollers have - * an internal analogue-digital converter (ADC) with the following features: - * - SAR ADC - * - 500 kS/s (Using an independent 48MHz clock) - * - 12 bit (RP2040 8.7 ENOB, RP2350 9.2 ENOB) - * \if rp2040_specific - * - RP2040 5 input mux: - * - 4 inputs that are available on package pins shared with GPIO[29:26] - * - 1 input is dedicated to the internal temperature sensor - * - 4 element receive sample FIFO - * \endif - * - * \if rp2350_specific - * - RP2350 5 or 9 input mux: - * - 4 inputs available on QFN-60 package pins shared with GPIO[29:26] - * - 8 inputs available on QFN-80 package pins shared with GPIO[47:40] - * - 8 element receive sample FIFO - * \endif - * - One input dedicated to the internal temperature sensor (see Section 12.4.6) - * - Interrupt generation - * - DMA interface - * - * Although there is only one ADC you can specify the input to it using the adc_select_input() function. - * In round robin mode (adc_set_round_robin()), the ADC will use that input and move to the next one after a read. - * - * RP2040, RP2350 QFN-60: User ADC inputs are on 0-3 (GPIO 26-29), the temperature sensor is on input 4. - * RP2350 QFN-80 : User ADC inputs are on 0-7 (GPIO 40-47), the temperature sensor is on input 8. - * - * Temperature sensor values can be approximated in centigrade as: - * - * T = 27 - (ADC_Voltage - 0.706)/0.001721 - * - * \subsection adc_example Example - * \addtogroup hardware_adc - * - * \include hello_adc.c - */ - -// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_HARDWARE_ADC, Enable/disable assertions in the hardware_adc module, type=bool, default=0, group=hardware_adc -#ifndef PARAM_ASSERTIONS_ENABLED_HARDWARE_ADC -#ifdef PARAM_ASSERTIONS_ENABLED_ADC // backwards compatibility with SDK < 2.0.0 -#define PARAM_ASSERTIONS_ENABLED_HARDWARE_ADC PARAM_ASSERTIONS_ENABLED_ADC -#else -#define PARAM_ASSERTIONS_ENABLED_HARDWARE_ADC 0 -#endif -#endif - -/** - * The ADC channel number of the on-board temperature sensor - */ -#ifndef ADC_TEMPERATURE_CHANNEL_NUM -#define ADC_TEMPERATURE_CHANNEL_NUM (NUM_ADC_CHANNELS - 1) -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -/*! \brief Initialise the ADC HW - * \ingroup hardware_adc - * - */ -void adc_init(void); - -/*! \brief Initialise the gpio for use as an ADC pin - * \ingroup hardware_adc - * - * Prepare a GPIO for use with ADC by disabling all digital functions. - * - * \param gpio The GPIO number to use. Allowable GPIO numbers are 26 to 29 inclusive on RP2040 or RP2350A, 40-48 inclusive on RP2350B - */ -static inline void adc_gpio_init(uint gpio) { - invalid_params_if(HARDWARE_ADC, gpio < ADC_BASE_PIN || gpio >= ADC_BASE_PIN + NUM_ADC_CHANNELS - 1); - // Select NULL function to make output driver hi-Z - gpio_set_function(gpio, GPIO_FUNC_NULL); - // Also disable digital pulls and digital receiver - gpio_disable_pulls(gpio); - gpio_set_input_enabled(gpio, false); -} - -/*! \brief ADC input select - * \ingroup hardware_adc - * - * Select an ADC input - * \if rp2040_specific - * On RP02040 0...3 are GPIOs 26...29 respectively. Input 4 is the onboard temperature sensor. - * \endif - * \if rp2350_specific - * On RP2350A 0...3 are GPIOs 26...29 respectively. Input 4 is the onboard temperature sensor. - * On RP2350B 0...7 are GPIOs 40...47 respectively. Input 8 is the onboard temperature sensor. - * \endif - * - * \param input Input to select. - */ -static inline void adc_select_input(uint input) { - valid_params_if(HARDWARE_ADC, input < NUM_ADC_CHANNELS); - hw_write_masked(&adc_hw->cs, input << ADC_CS_AINSEL_LSB, ADC_CS_AINSEL_BITS); -} - -/*! \brief Get the currently selected ADC input channel - * \ingroup hardware_adc - * - * \return The currently selected input channel. - * - * \if rp2040_specific - * On RP02040 0...3 are GPIOs 26...29 respectively. Input 4 is the onboard temperature sensor. - * \endif - * - * \if rp2350_specific - * On RP2350A 0...3 are GPIOs 26...29 respectively. Input 4 is the onboard temperature sensor. - * On RP2350B 0...7 are GPIOs 40...47 respectively. Input 8 is the onboard temperature sensor. - * \endif - */ -static inline uint adc_get_selected_input(void) { - return (adc_hw->cs & ADC_CS_AINSEL_BITS) >> ADC_CS_AINSEL_LSB; -} - -/*! \brief Round Robin sampling selector - * \ingroup hardware_adc - * - * This function sets which inputs are to be run through in round robin mode. - * RP2040, RP2350 QFN-60: Value between 0 and 0x1f (bit 0 to bit 4 for GPIO 26 to 29 and temperature sensor input respectively) - * RP2350 QFN-80: Value between 0 and 0xff (bit 0 to bit 7 for GPIO 40 to 47 and temperature sensor input respectively) - * - * \param input_mask A bit pattern indicating which of the 5/8 inputs are to be sampled. Write a value of 0 to disable round robin sampling. - */ -static inline void adc_set_round_robin(uint input_mask) { - valid_params_if(HARDWARE_ADC, input_mask < (1 << NUM_ADC_CHANNELS)); - hw_write_masked(&adc_hw->cs, input_mask << ADC_CS_RROBIN_LSB, ADC_CS_RROBIN_BITS); -} - -/*! \brief Enable the onboard temperature sensor - * \ingroup hardware_adc - * - * \param enable Set true to power on the onboard temperature sensor, false to power off. - * - */ -static inline void adc_set_temp_sensor_enabled(bool enable) { - if (enable) - hw_set_bits(&adc_hw->cs, ADC_CS_TS_EN_BITS); - else - hw_clear_bits(&adc_hw->cs, ADC_CS_TS_EN_BITS); -} - -/*! \brief Perform a single conversion - * \ingroup hardware_adc - * - * Performs an ADC conversion, waits for the result, and then returns it. - * - * \return Result of the conversion. - */ -static inline uint16_t adc_read(void) { - hw_set_bits(&adc_hw->cs, ADC_CS_START_ONCE_BITS); - - while (!(adc_hw->cs & ADC_CS_READY_BITS)) - tight_loop_contents(); - - return (uint16_t) adc_hw->result; -} - -/*! \brief Enable or disable free-running sampling mode - * \ingroup hardware_adc - * - * \param run false to disable, true to enable free running conversion mode. - */ -static inline void adc_run(bool run) { - if (run) - hw_set_bits(&adc_hw->cs, ADC_CS_START_MANY_BITS); - else - hw_clear_bits(&adc_hw->cs, ADC_CS_START_MANY_BITS); -} - -/*! \brief Set the ADC Clock divisor - * \ingroup hardware_adc - * - * Period of samples will be (1 + div) cycles on average. Note it takes 96 cycles to perform a conversion, - * so any period less than that will be clamped to 96. - * - * \param clkdiv If non-zero, conversion will be started at intervals rather than back to back. - */ -static inline void adc_set_clkdiv(float clkdiv) { - invalid_params_if(HARDWARE_ADC, clkdiv >= 1 << (ADC_DIV_INT_MSB - ADC_DIV_INT_LSB + 1)); - adc_hw->div = (uint32_t)(clkdiv * (float) (1 << ADC_DIV_INT_LSB)); -} - -/*! \brief Setup the ADC FIFO - * \ingroup hardware_adc - * - * \if rp2040_specific - * On RP2040 the FIFO is 4 samples long. - * \endif - * - * \if rp2350_specific - * On RP2350 the FIFO is 8 samples long. - * \endif - * - * If a conversion is completed and the FIFO is full, the result is dropped. - * - * \param en Enables write each conversion result to the FIFO - * \param dreq_en Enable DMA requests when FIFO contains data - * \param dreq_thresh Threshold for DMA requests/FIFO IRQ if enabled. - * \param err_in_fifo If enabled, bit 15 of the FIFO contains error flag for each sample - * \param byte_shift Shift FIFO contents to be one byte in size (for byte DMA) - enables DMA to byte buffers. - */ - static inline void adc_fifo_setup(bool en, bool dreq_en, uint16_t dreq_thresh, bool err_in_fifo, bool byte_shift) { - hw_write_masked(&adc_hw->fcs, - (bool_to_bit(en) << ADC_FCS_EN_LSB) | - (bool_to_bit(dreq_en) << ADC_FCS_DREQ_EN_LSB) | - (((uint)dreq_thresh) << ADC_FCS_THRESH_LSB) | - (bool_to_bit(err_in_fifo) << ADC_FCS_ERR_LSB) | - (bool_to_bit(byte_shift) << ADC_FCS_SHIFT_LSB), - ADC_FCS_EN_BITS | - ADC_FCS_DREQ_EN_BITS | - ADC_FCS_THRESH_BITS | - ADC_FCS_ERR_BITS | - ADC_FCS_SHIFT_BITS - ); -} - -/*! \brief Check FIFO empty state - * \ingroup hardware_adc - * - * \return Returns true if the FIFO is empty - */ -static inline bool adc_fifo_is_empty(void) { - return adc_hw->fcs & ADC_FCS_EMPTY_BITS; -} - -/*! \brief Get number of entries in the ADC FIFO - * \ingroup hardware_adc - * - * \if rp2040_specific - * On RP2040 the FIFO is 4 samples long. - * \endif - * \if rp2350_specific - * On RP2350 the FIFO is 8 samples long. - * \endif - * - * This function will return how many samples are currently present. - */ -static inline uint8_t adc_fifo_get_level(void) { - return (adc_hw->fcs & ADC_FCS_LEVEL_BITS) >> ADC_FCS_LEVEL_LSB; -} - -/*! \brief Get ADC result from FIFO - * \ingroup hardware_adc - * - * Pops the latest result from the ADC FIFO. - */ -static inline uint16_t adc_fifo_get(void) { - return (uint16_t)adc_hw->fifo; -} - -/*! \brief Wait for the ADC FIFO to have data. - * \ingroup hardware_adc - * - * Blocks until data is present in the FIFO - */ -static inline uint16_t adc_fifo_get_blocking(void) { - while (adc_fifo_is_empty()) - tight_loop_contents(); - return (uint16_t)adc_hw->fifo; -} - -/*! \brief Drain the ADC FIFO - * \ingroup hardware_adc - * - * Will wait for any conversion to complete then drain the FIFO, discarding any results. - */ -static inline void adc_fifo_drain(void) { - // Potentially there is still a conversion in progress -- wait for this to complete before draining - while (!(adc_hw->cs & ADC_CS_READY_BITS)) - tight_loop_contents(); - while (!adc_fifo_is_empty()) - (void) adc_fifo_get(); -} - -/*! \brief Enable/Disable ADC interrupts. - * \ingroup hardware_adc - * - * \param enabled Set to true to enable the ADC interrupts, false to disable - */ -static inline void adc_irq_set_enabled(bool enabled) { - adc_hw->inte = !!enabled; -} - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/lib/main/pico-sdk/rp2_common/hardware_base/include/hardware/address_mapped.h b/lib/main/pico-sdk/rp2_common/hardware_base/include/hardware/address_mapped.h deleted file mode 100644 index b384f55727..0000000000 --- a/lib/main/pico-sdk/rp2_common/hardware_base/include/hardware/address_mapped.h +++ /dev/null @@ -1,184 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _HARDWARE_ADDRESS_MAPPED_H -#define _HARDWARE_ADDRESS_MAPPED_H - -#include "pico.h" -#include "hardware/regs/addressmap.h" - -/** \file address_mapped.h - * \defgroup hardware_base hardware_base - * - * \brief Low-level types and (atomic) accessors for memory-mapped hardware registers - * - * `hardware_base` defines the low level types and access functions for memory mapped hardware registers. It is included - * by default by all other hardware libraries. - * - * The following register access typedefs codify the access type (read/write) and the bus size (8/16/32) of the hardware register. - * The register type names are formed by concatenating one from each of the 3 parts A, B, C - - * A | B | C | Meaning - * ------|---|---|-------- - * io_ | | | A Memory mapped IO register - *  |ro_| | read-only access - *  |rw_| | read-write access - *  |wo_| | write-only access (can't actually be enforced via C API) - *  | | 8| 8-bit wide access - *  | | 16| 16-bit wide access - *  | | 32| 32-bit wide access - * - * When dealing with these types, you will always use a pointer, i.e. `io_rw_32 *some_reg` is a pointer to a read/write - * 32 bit register that you can write with `*some_reg = value`, or read with `value = *some_reg`. - * - * RP-series hardware is also aliased to provide atomic setting, clear or flipping of a subset of the bits within - * a hardware register so that concurrent access by two cores is always consistent with one atomic operation - * being performed first, followed by the second. - * - * See hw_set_bits(), hw_clear_bits() and hw_xor_bits() provide for atomic access via a pointer to a 32 bit register - * - * Additionally given a pointer to a structure representing a piece of hardware (e.g. `dma_hw_t *dma_hw` for the DMA controller), you can - * get an alias to the entire structure such that writing any member (register) within the structure is equivalent - * to an atomic operation via hw_set_alias(), hw_clear_alias() or hw_xor_alias()... - * - * For example `hw_set_alias(dma_hw)->inte1 = 0x80;` will set bit 7 of the INTE1 register of the DMA controller, - * leaving the other bits unchanged. - */ - -#ifdef __cplusplus -extern "C" { -#endif - -#define check_hw_layout(type, member, offset) static_assert(offsetof(type, member) == (offset), "hw offset mismatch") -#define check_hw_size(type, size) static_assert(sizeof(type) == (size), "hw size mismatch") - -// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_ADDRESS_ALIAS, Enable/disable assertions in memory address aliasing macros, type=bool, default=0, group=hardware_base -#ifndef PARAM_ASSERTIONS_ENABLED_ADDRESS_ALIAS -#define PARAM_ASSERTIONS_ENABLED_ADDRESS_ALIAS 0 -#endif - -typedef volatile uint64_t io_rw_64; -typedef const volatile uint64_t io_ro_64; -typedef volatile uint64_t io_wo_64; -typedef volatile uint32_t io_rw_32; -typedef const volatile uint32_t io_ro_32; -typedef volatile uint32_t io_wo_32; -typedef volatile uint16_t io_rw_16; -typedef const volatile uint16_t io_ro_16; -typedef volatile uint16_t io_wo_16; -typedef volatile uint8_t io_rw_8; -typedef const volatile uint8_t io_ro_8; -typedef volatile uint8_t io_wo_8; - -typedef volatile uint8_t *const ioptr; -typedef ioptr const const_ioptr; - -// A non-functional (empty) helper macro to help IDEs follow links from the autogenerated -// hardware struct headers in hardware/structs/xxx.h to the raw register definitions -// in hardware/regs/xxx.h. A preprocessor define such as TIMER_TIMEHW_OFFSET (a timer register offset) -// is not generally clickable (in an IDE) if placed in a C comment, so _REG_(TIMER_TIMEHW_OFFSET) is -// included outside of a comment instead -#define _REG_(x) - -// Helper method used by hw_alias macros to optionally check input validity -#define hw_alias_check_addr(addr) ((uintptr_t)(addr)) -// can't use the following impl as it breaks existing static declarations using hw_alias, so would be a backwards incompatibility -//static __force_inline uint32_t hw_alias_check_addr(volatile void *addr) { -// uint32_t rc = (uintptr_t)addr; -// invalid_params_if(ADDRESS_ALIAS, rc < 0x40000000); // catch likely non HW pointer types -// return rc; -//} - -#if PICO_RP2040 -// Helper method used by xip_alias macros to optionally check input validity -__force_inline static uint32_t xip_alias_check_addr(const void *addr) { - uint32_t rc = (uintptr_t)addr; - valid_params_if(ADDRESS_ALIAS, rc >= XIP_MAIN_BASE && rc < XIP_NOALLOC_BASE); - return rc; -} -#else -//static __force_inline uint32_t xip_alias_check_addr(const void *addr) { -// uint32_t rc = (uintptr_t)addr; -// valid_params_if(ADDRESS_ALIAS, rc >= XIP_BASE && rc < XIP_END); -// return rc; -//} -#endif - -// Untyped conversion alias pointer generation macros -#define hw_set_alias_untyped(addr) ((void *)(REG_ALIAS_SET_BITS + hw_alias_check_addr(addr))) -#define hw_clear_alias_untyped(addr) ((void *)(REG_ALIAS_CLR_BITS + hw_alias_check_addr(addr))) -#define hw_xor_alias_untyped(addr) ((void *)(REG_ALIAS_XOR_BITS + hw_alias_check_addr(addr))) - -#if PICO_RP2040 -#define xip_noalloc_alias_untyped(addr) ((void *)(XIP_NOALLOC_BASE | xip_alias_check_addr(addr))) -#define xip_nocache_alias_untyped(addr) ((void *)(XIP_NOCACHE_BASE | xip_alias_check_addr(addr))) -#define xip_nocache_noalloc_alias_untyped(addr) ((void *)(XIP_NOCACHE_NOALLOC_BASE | xip_alias_check_addr(addr))) -#endif - -// Typed conversion alias pointer generation macros -#define hw_set_alias(p) ((typeof(p))hw_set_alias_untyped(p)) -#define hw_clear_alias(p) ((typeof(p))hw_clear_alias_untyped(p)) -#define hw_xor_alias(p) ((typeof(p))hw_xor_alias_untyped(p)) -#define xip_noalloc_alias(p) ((typeof(p))xip_noalloc_alias_untyped(p)) -#define xip_nocache_alias(p) ((typeof(p))xip_nocache_alias_untyped(p)) -#define xip_nocache_noalloc_alias(p) ((typeof(p))xip_nocache_noalloc_alias_untyped(p)) - -/*! \brief Atomically set the specified bits to 1 in a HW register - * \ingroup hardware_base - * - * \param addr Address of writable register - * \param mask Bit-mask specifying bits to set - */ -__force_inline static void hw_set_bits(io_rw_32 *addr, uint32_t mask) { - *(io_rw_32 *) hw_set_alias_untyped((volatile void *) addr) = mask; -} - -/*! \brief Atomically clear the specified bits to 0 in a HW register - * \ingroup hardware_base - * - * \param addr Address of writable register - * \param mask Bit-mask specifying bits to clear - */ -__force_inline static void hw_clear_bits(io_rw_32 *addr, uint32_t mask) { - *(io_rw_32 *) hw_clear_alias_untyped((volatile void *) addr) = mask; -} - -/*! \brief Atomically flip the specified bits in a HW register - * \ingroup hardware_base - * - * \param addr Address of writable register - * \param mask Bit-mask specifying bits to invert - */ -__force_inline static void hw_xor_bits(io_rw_32 *addr, uint32_t mask) { - *(io_rw_32 *) hw_xor_alias_untyped((volatile void *) addr) = mask; -} - -/*! \brief Set new values for a sub-set of the bits in a HW register - * \ingroup hardware_base - * - * Sets destination bits to values specified in \p values, if and only if corresponding bit in \p write_mask is set - * - * Note: this method allows safe concurrent modification of *different* bits of - * a register, but multiple concurrent access to the same bits is still unsafe. - * - * \param addr Address of writable register - * \param values Bits values - * \param write_mask Mask of bits to change - */ -__force_inline static void hw_write_masked(io_rw_32 *addr, uint32_t values, uint32_t write_mask) { - hw_xor_bits(addr, (*addr ^ values) & write_mask); -} - -#if !PICO_RP2040 -// include this here to avoid the check in every other hardware/structs header that needs it -#include "hardware/structs/accessctrl.h" -#endif - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/lib/main/pico-sdk/rp2_common/hardware_boot_lock/boot_lock.c b/lib/main/pico-sdk/rp2_common/hardware_boot_lock/boot_lock.c deleted file mode 100644 index a344631b3b..0000000000 --- a/lib/main/pico-sdk/rp2_common/hardware_boot_lock/boot_lock.c +++ /dev/null @@ -1,35 +0,0 @@ -/* - * Copyright (c) 2024 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#include "hardware/boot_lock.h" -#include "pico/runtime_init.h" - -#if NUM_BOOT_LOCKS > 0 -void boot_locks_reset(void) { - GCC_Pragma("GCC unroll 1") // prevent GCC unrolling this loop which is 8 bytes per - for (uint i = 0; i < NUM_BOOT_LOCKS; i++) { - boot_unlock_unsafe(boot_lock_instance(i)); - } -} - -boot_lock_t *boot_lock_init(uint lock_num) { - assert(lock_num < NUM_BOOT_LOCKS); - boot_lock_t *lock = boot_lock_instance(lock_num); - boot_unlock_unsafe(lock); - return lock; -} - -#if !PICO_RUNTIME_NO_INIT_BOOT_LOCKS_RESET -#include "hardware/sync.h" -void __weak runtime_init_boot_locks_reset(void) { - boot_locks_reset(); -} -#endif - -#if !PICO_RUNTIME_SKIP_INIT_BOOT_LOCKS_RESET -PICO_RUNTIME_INIT_FUNC_RUNTIME(runtime_init_boot_locks_reset, PICO_RUNTIME_INIT_BOOT_LOCKS_RESET); -#endif - -#endif diff --git a/lib/main/pico-sdk/rp2_common/hardware_boot_lock/include/hardware/boot_lock.h b/lib/main/pico-sdk/rp2_common/hardware_boot_lock/include/hardware/boot_lock.h deleted file mode 100644 index dd63ef0e82..0000000000 --- a/lib/main/pico-sdk/rp2_common/hardware_boot_lock/include/hardware/boot_lock.h +++ /dev/null @@ -1,144 +0,0 @@ -/* - * Copyright (c) 2024 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _HARDWARE_BOOT_LOCK_H -#define _HARDWARE_BOOT_LOCK_H - -#include "pico.h" - -// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_HARDWARE_BOOT_LOCK, Enable/disable assertions in the hardware_boot_lock module, type=bool, default=0, group=hardware_boot_lock -#ifndef PARAM_ASSERTIONS_ENABLED_HARDWARE_BOOT_LOCK -#define PARAM_ASSERTIONS_ENABLED_HARDWARE_BOOT_LOCK 0 -#endif - -#if NUM_BOOT_LOCKS > 0 -#include "hardware/sync.h" -#include "hardware/structs/bootram.h" - -/** \brief A boot lock identifier - * \ingroup hardware_sync - */ -typedef volatile uint32_t boot_lock_t; - -/*! \brief Get HW Bootlock instance from number - * \ingroup hardware_sync - * - * \param lock_num Bootlock ID - * \return The bootlock instance - */ -__force_inline static boot_lock_t *boot_lock_instance(uint lock_num) { - invalid_params_if(HARDWARE_BOOT_LOCK, lock_num >= NUM_BOOT_LOCKS); - return (boot_lock_t *) (BOOTRAM_BASE + BOOTRAM_BOOTLOCK0_OFFSET + lock_num * 4); -} - -/*! \brief Get HW Bootlock number from instance - * \ingroup hardware_sync - * - * \param lock The Bootlock instance - * \return The Bootlock ID - */ -__force_inline static uint boot_lock_get_num(boot_lock_t *lock) { - invalid_params_if(HARDWARE_BOOT_LOCK, (uint) lock < BOOTRAM_BASE + BOOTRAM_BOOTLOCK0_OFFSET || - (uint) lock >= NUM_BOOT_LOCKS * sizeof(boot_lock_t) + BOOTRAM_BASE + BOOTRAM_BOOTLOCK0_OFFSET || - ((uint) lock - BOOTRAM_BASE + BOOTRAM_BOOTLOCK0_OFFSET) % sizeof(boot_lock_t) != 0); - return (uint) (lock - (boot_lock_t *) (BOOTRAM_BASE + BOOTRAM_BOOTLOCK0_OFFSET)); -} - -/*! \brief Acquire a boot lock without disabling interrupts (hence unsafe) - * \ingroup hardware_sync - * - * \param lock Bootlock instance - */ -__force_inline static void boot_lock_unsafe_blocking(boot_lock_t *lock) { - // Note we don't do a wfe or anything, because by convention these boot_locks are VERY SHORT LIVED and NEVER BLOCK and run - // with INTERRUPTS disabled (to ensure that)... therefore nothing on our core could be blocking us, so we just need to wait on another core - // anyway which should be finished soon - while (__builtin_expect(!*lock, 0)) { // read from bootlock register (tries to acquire the lock) - tight_loop_contents(); - } - __mem_fence_acquire(); -} - -/*! \brief try to acquire a boot lock without disabling interrupts (hence unsafe) - * \ingroup hardware_sync - * - * \param lock Bootlock instance - */ -__force_inline static bool boot_try_lock_unsafe(boot_lock_t *lock) { - if (*lock) { - __mem_fence_acquire(); - return true; - } - return false; -} - -/*! \brief Release a boot lock without re-enabling interrupts - * \ingroup hardware_sync - * - * \param lock Bootlock instance - */ -__force_inline static void boot_unlock_unsafe(boot_lock_t *lock) { - __mem_fence_release(); - *lock = 0; // write to bootlock register (release lock) -} - -/*! \brief Acquire a boot lock safely - * \ingroup hardware_sync - * - * This function will disable interrupts prior to acquiring the bootlock - * - * \param lock Bootlock instance - * \return interrupt status to be used when unlocking, to restore to original state - */ -__force_inline static uint32_t boot_lock_blocking(boot_lock_t *lock) { - uint32_t save = save_and_disable_interrupts(); - boot_lock_unsafe_blocking(lock); - return save; -} - -/*! \brief Check to see if a bootlock is currently acquired elsewhere. - * \ingroup hardware_sync - * - * \param lock Bootlock instance - */ -inline static bool is_boot_locked(boot_lock_t *lock) { - check_hw_size(boot_lock_t, 4); - uint lock_num = boot_lock_get_num(lock); - return 0 != (*(io_ro_32 *) (BOOTRAM_BASE + BOOTRAM_BOOTLOCK_STAT_OFFSET) & (1u << lock_num)); -} - -/*! \brief Release a boot lock safely - * \ingroup hardware_sync - * - * This function will re-enable interrupts according to the parameters. - * - * \param lock Bootlock instance - * \param saved_irq Return value from the \ref boot_lock_blocking() function. - * - * \sa boot_lock_blocking() - */ -__force_inline static void boot_unlock(boot_lock_t *lock, uint32_t saved_irq) { - boot_unlock_unsafe(lock); - restore_interrupts_from_disabled(saved_irq); -} - -/*! \brief Initialise a boot lock - * \ingroup hardware_sync - * - * The boot lock is initially unlocked - * - * \param lock_num The boot lock number - * \return The boot lock instance - */ -boot_lock_t *boot_lock_init(uint lock_num); - -/*! \brief Release all boot locks - * \ingroup hardware_sync - */ -void boot_locks_reset(void); - -#endif -#endif \ No newline at end of file diff --git a/lib/main/pico-sdk/rp2_common/hardware_clocks/clocks.c b/lib/main/pico-sdk/rp2_common/hardware_clocks/clocks.c deleted file mode 100644 index e04cebefc5..0000000000 --- a/lib/main/pico-sdk/rp2_common/hardware_clocks/clocks.c +++ /dev/null @@ -1,435 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "pico.h" -#include "hardware/regs/clocks.h" -#include "hardware/platform_defs.h" -#include "hardware/clocks.h" -#include "hardware/pll.h" -#include "hardware/irq.h" -#include "hardware/gpio.h" - -check_hw_layout(clocks_hw_t, clk[clk_adc].selected, CLOCKS_CLK_ADC_SELECTED_OFFSET); -check_hw_layout(clocks_hw_t, fc0.result, CLOCKS_FC0_RESULT_OFFSET); -check_hw_layout(clocks_hw_t, ints, CLOCKS_INTS_OFFSET); - -static uint32_t configured_freq[CLK_COUNT]; - -static resus_callback_t _resus_callback; - -// Clock muxing consists of two components: -// - A glitchless mux, which can be switched freely, but whose inputs must be -// free-running -// - An auxiliary (glitchy) mux, whose output glitches when switched, but has -// no constraints on its inputs -// Not all clocks have both types of mux. -static inline bool has_glitchless_mux(clock_handle_t clock) { - return clock == clk_sys || clock == clk_ref; -} - -void clock_stop(clock_handle_t clock) { - clock_hw_t *clock_hw = &clocks_hw->clk[clock]; - hw_clear_bits(&clock_hw->ctrl, CLOCKS_CLK_USB_CTRL_ENABLE_BITS); - configured_freq[clock] = 0; -} - -/// \tag::clock_configure[] -static void clock_configure_internal(clock_handle_t clock, uint32_t src, uint32_t auxsrc, uint32_t actual_freq, uint32_t div) { - clock_hw_t *clock_hw = &clocks_hw->clk[clock]; - - // If increasing divisor, set divisor before source. Otherwise set source - // before divisor. This avoids a momentary overspeed when e.g. switching - // to a faster source and increasing divisor to compensate. - if (div > clock_hw->div) - clock_hw->div = div; - - // If switching a glitchless slice (ref or sys) to an aux source, switch - // away from aux *first* to avoid passing glitches when changing aux mux. - // Assume (!!!) glitchless source 0 is no faster than the aux source. - if (has_glitchless_mux(clock) && src == CLOCKS_CLK_SYS_CTRL_SRC_VALUE_CLKSRC_CLK_SYS_AUX) { - hw_clear_bits(&clock_hw->ctrl, CLOCKS_CLK_REF_CTRL_SRC_BITS); - while (!(clock_hw->selected & 1u)) - tight_loop_contents(); - } - // If no glitchless mux, cleanly stop the clock to avoid glitches - // propagating when changing aux mux. Note it would be a really bad idea - // to do this on one of the glitchless clocks (clk_sys, clk_ref). - else { - // Disable clock. On clk_ref and clk_sys this does nothing, - // all other clocks have the ENABLE bit in the same position. - hw_clear_bits(&clock_hw->ctrl, CLOCKS_CLK_GPOUT0_CTRL_ENABLE_BITS); - if (configured_freq[clock] > 0) { - // Delay for 3 cycles of the target clock, for ENABLE propagation. - // Note XOSC_COUNT is not helpful here because XOSC is not - // necessarily running, nor is timer... - uint delay_cyc = configured_freq[clk_sys] / configured_freq[clock] + 1; - busy_wait_at_least_cycles(delay_cyc * 3); - } - } - - // Set aux mux first, and then glitchless mux if this clock has one - hw_write_masked(&clock_hw->ctrl, - (auxsrc << CLOCKS_CLK_SYS_CTRL_AUXSRC_LSB), - CLOCKS_CLK_SYS_CTRL_AUXSRC_BITS - ); - - if (has_glitchless_mux(clock)) { - hw_write_masked(&clock_hw->ctrl, - src << CLOCKS_CLK_REF_CTRL_SRC_LSB, - CLOCKS_CLK_REF_CTRL_SRC_BITS - ); - while (!(clock_hw->selected & (1u << src))) - tight_loop_contents(); - } - - // Enable clock. On clk_ref and clk_sys this does nothing, - // all other clocks have the ENABLE bit in the same position. - hw_set_bits(&clock_hw->ctrl, CLOCKS_CLK_GPOUT0_CTRL_ENABLE_BITS); - - // Now that the source is configured, we can trust that the user-supplied - // divisor is a safe value. - clock_hw->div = div; - configured_freq[clock] = actual_freq; -} - -bool clock_configure(clock_handle_t clock, uint32_t src, uint32_t auxsrc, uint32_t src_freq, uint32_t freq) { - assert(src_freq >= freq); - - if (freq > src_freq) - return false; - - uint32_t div = (uint32_t)((((uint64_t) src_freq) << CLOCKS_CLK_GPOUT0_DIV_INT_LSB) / freq); - uint32_t actual_freq = (uint32_t) ((((uint64_t) src_freq) << CLOCKS_CLK_GPOUT0_DIV_INT_LSB) / div); - - clock_configure_internal(clock, src, auxsrc, actual_freq, div); - // Store the configured frequency - return true; -} - -void clock_configure_int_divider(clock_handle_t clock, uint32_t src, uint32_t auxsrc, uint32_t src_freq, uint32_t int_divider) { - clock_configure_internal(clock, src, auxsrc, src_freq / int_divider, int_divider << CLOCKS_CLK_GPOUT0_DIV_INT_LSB); -} - -void clock_configure_undivided(clock_handle_t clock, uint32_t src, uint32_t auxsrc, uint32_t src_freq) { - clock_configure_internal(clock, src, auxsrc, src_freq, 1u << CLOCKS_CLK_GPOUT0_DIV_INT_LSB); -} - -/// \end::clock_configure[] - -/// \tag::clock_get_hz[] -uint32_t clock_get_hz(clock_handle_t clock) { - return configured_freq[clock]; -} -/// \end::clock_get_hz[] - -void clock_set_reported_hz(clock_handle_t clock, uint hz) { - configured_freq[clock] = hz; -} - -/// \tag::frequency_count_khz[] -uint32_t frequency_count_khz(uint src) { - fc_hw_t *fc = &clocks_hw->fc0; - - // If frequency counter is running need to wait for it. It runs even if the source is NULL - while(fc->status & CLOCKS_FC0_STATUS_RUNNING_BITS) { - tight_loop_contents(); - } - - // Set reference freq - fc->ref_khz = clock_get_hz(clk_ref) / 1000; - - // FIXME: Don't pick random interval. Use best interval - fc->interval = 10; - - // No min or max - fc->min_khz = 0; - fc->max_khz = 0xffffffff; - - // Set SRC which automatically starts the measurement - fc->src = src; - - while(!(fc->status & CLOCKS_FC0_STATUS_DONE_BITS)) { - tight_loop_contents(); - } - - // Return the result - return fc->result >> CLOCKS_FC0_RESULT_KHZ_LSB; -} -/// \end::frequency_count_khz[] - -static void clocks_handle_resus(void) { - // Set clk_sys back to the ref clock rather than it being forced to clk_ref - // by resus. Call the user's resus callback if they have set one - - // CLK SYS = CLK_REF. Must be running for this code to be running - uint clk_ref_freq = clock_get_hz(clk_ref); - clock_configure_undivided(clk_sys, - CLOCKS_CLK_SYS_CTRL_SRC_VALUE_CLK_REF, - 0, - clk_ref_freq); - - // Assert we have been resussed - assert(clocks_hw->resus.status & CLOCKS_CLK_SYS_RESUS_STATUS_RESUSSED_BITS); - - // Now we have fixed clk_sys we can safely remove the resus - hw_set_bits(&clocks_hw->resus.ctrl, CLOCKS_CLK_SYS_RESUS_CTRL_CLEAR_BITS); - hw_clear_bits(&clocks_hw->resus.ctrl, CLOCKS_CLK_SYS_RESUS_CTRL_CLEAR_BITS); - - // Now we should no longer be resussed - assert(!(clocks_hw->resus.status & CLOCKS_CLK_SYS_RESUS_STATUS_RESUSSED_BITS)); - - // Call the user's callback to notify them of the resus event - if (_resus_callback) { - _resus_callback(); - } -} - -static void clocks_irq_handler(void) { - // Clocks interrupt handler. Only resus but handle irq - // defensively just in case. - uint32_t ints = clocks_hw->ints; - - if (ints & CLOCKS_INTE_CLK_SYS_RESUS_BITS) { - ints &= ~CLOCKS_INTE_CLK_SYS_RESUS_BITS; - clocks_handle_resus(); - } - -#ifndef NDEBUG - if (ints) { - panic("Unexpected clocks irq\n"); - } -#endif -} - -void clocks_enable_resus(resus_callback_t resus_callback) { - // Restart clk_sys if it is stopped by forcing it - // to the default source of clk_ref. If clk_ref stops running this will - // not work. - - // Store user's resus callback - _resus_callback = resus_callback; - - irq_set_exclusive_handler(CLOCKS_IRQ, clocks_irq_handler); - - // Enable the resus interrupt in clocks - clocks_hw->inte = CLOCKS_INTE_CLK_SYS_RESUS_BITS; - - // Enable the clocks irq - irq_set_enabled(CLOCKS_IRQ, true); - - // 2 * clk_ref freq / clk_sys_min_freq; - // assume clk_ref is 3MHz and we want clk_sys to be no lower than 1MHz - uint timeout = 2 * 3 * 1; - - // Enable resus with the maximum timeout - clocks_hw->resus.ctrl = CLOCKS_CLK_SYS_RESUS_CTRL_ENABLE_BITS | timeout; -} - -void clock_gpio_init_int_frac(uint gpio, uint src, uint32_t div_int, uint8_t div_frac) { - // Bit messy but it's as much code to loop through a lookup - // table. The sources for each gpout generators are the same - // so just call with the sources from GP0 - uint gpclk = 0; - if (gpio == 21) gpclk = clk_gpout0; - else if (gpio == 23) gpclk = clk_gpout1; - else if (gpio == 24) gpclk = clk_gpout2; - else if (gpio == 25) gpclk = clk_gpout3; -#if !PICO_RP2040 - else if (gpio == 13) gpclk = clk_gpout0; - else if (gpio == 15) gpclk = clk_gpout1; -#endif - else { - invalid_params_if(HARDWARE_CLOCKS, true); - } - - // Set up the gpclk generator - clocks_hw->clk[gpclk].ctrl = (src << CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_LSB) | - CLOCKS_CLK_GPOUT0_CTRL_ENABLE_BITS; - clocks_hw->clk[gpclk].div = (div_int << CLOCKS_CLK_GPOUT0_DIV_INT_LSB) | div_frac; - - // Set gpio pin to gpclock function - gpio_set_function(gpio, GPIO_FUNC_GPCK); -} - -static const uint8_t gpin0_src[CLK_COUNT] = { - CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0, // CLK_GPOUT0 - CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0, // CLK_GPOUT1 - CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0, // CLK_GPOUT2 - CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0, // CLK_GPOUT3 - CLOCKS_CLK_REF_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0, // CLK_REF - CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0, // CLK_SYS - CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0, // CLK_PERI -#if !PICO_RP2040 - CLOCKS_CLK_HSTX_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0, // CLK_HSTX -#endif - CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0, // CLK_USB - CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0, // CLK_ADC -#if PICO_RP2040 - CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0, // CLK_RTC -#endif -}; - -// Assert GPIN1 is GPIN0 + 1 -static_assert(CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 == (CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 + 1), "hw mismatch"); -static_assert(CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 == (CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 + 1), "hw mismatch"); -static_assert(CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 == (CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 + 1), "hw mismatch"); -static_assert(CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 == (CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 + 1), "hw mismatch"); -static_assert(CLOCKS_CLK_REF_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 == (CLOCKS_CLK_REF_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 + 1), "hw mismatch"); -static_assert(CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 == (CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 + 1), "hw mismatch"); -static_assert(CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 == (CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 + 1), "hw mismatch"); -#if HAS_HSTX -static_assert(CLOCKS_CLK_HSTX_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 == (CLOCKS_CLK_HSTX_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 + 1), "hw mismatch"); -#endif -static_assert(CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 == (CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 + 1), "hw mismatch"); -static_assert(CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 == (CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 + 1), "hw mismatch"); -#if HAS_RP2040_RTC -static_assert(CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 == (CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 + 1), "hw mismatch"); -#endif - -bool clock_configure_gpin(clock_handle_t clock, uint gpio, uint32_t src_freq, uint32_t freq) { - // Configure a clock to run from a GPIO input - uint gpin = 0; - if (gpio == 20) gpin = 0; - else if (gpio == 22) gpin = 1; -#if PICO_RP2350 - else if (gpio == 12) gpin = 0; - else if (gpio == 14) gpin = 1; -#endif - else { - invalid_params_if(HARDWARE_CLOCKS, true); - } - - // Work out sources. GPIN is always an auxsrc - uint src = 0; - - // GPIN1 == GPIN0 + 1 - uint auxsrc = gpin0_src[clock] + gpin; - - if (has_glitchless_mux(clock)) { - // AUX src is always 1 - src = 1; - } - - // Set the GPIO function - gpio_set_function(gpio, GPIO_FUNC_GPCK); - - // Now we have the src, auxsrc, and configured the gpio input - // call clock configure to run the clock from a gpio - return clock_configure(clock, src, auxsrc, src_freq, freq); -} - -// everything running off the USB oscillator -void set_sys_clock_48mhz(void) { - if (!running_on_fpga()) { - // Change clk_sys to be 48MHz. The simplest way is to take this from PLL_USB - // which has a source frequency of 48MHz - clock_configure_undivided(clk_sys, - CLOCKS_CLK_SYS_CTRL_SRC_VALUE_CLKSRC_CLK_SYS_AUX, - CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB, - USB_CLK_HZ); - - // Turn off PLL sys for good measure - pll_deinit(pll_sys); - - // CLK peri is clocked from clk_sys so need to change clk_peri's freq - clock_configure_undivided(clk_peri, - 0, - CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLK_SYS, - USB_CLK_HZ); - } -} - -// PICO_CONFIG: PICO_CLOCK_ADJUST_PERI_CLOCK_WITH_SYS_CLOCK, When the SYS clock PLL is changed keep the peripheral clock attached to it, type=bool, default=0, advanced=true, group=hardware_clocks -#ifndef PICO_CLOCK_ADJUST_PERI_CLOCK_WITH_SYS_CLOCK -// support old incorrect spelling too -#ifdef PICO_CLOCK_AJDUST_PERI_CLOCK_WITH_SYS_CLOCK -#define PICO_CLOCK_ADJUST_PERI_CLOCK_WITH_SYS_CLOCK PICO_CLOCK_AJDUST_PERI_CLOCK_WITH_SYS_CLOCK -#else -// By default, when reconfiguring the system clock PLL settings after runtime initialization, -// the peripheral clock is switched to the 48MHz USB clock to ensure continuity of peripheral operation. -// Setting this value to 1 changes the behavior to have the peripheral clock re-configured -// to the system clock at it's new frequency. -#define PICO_CLOCK_ADJUST_PERI_CLOCK_WITH_SYS_CLOCK 0 -#endif -#endif - -void set_sys_clock_pll(uint32_t vco_freq, uint post_div1, uint post_div2) { - if (!running_on_fpga()) { - clock_configure_undivided(clk_sys, - CLOCKS_CLK_SYS_CTRL_SRC_VALUE_CLKSRC_CLK_SYS_AUX, - CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB, - USB_CLK_HZ); - - pll_init(pll_sys, PLL_SYS_REFDIV, vco_freq, post_div1, post_div2); - uint32_t freq = vco_freq / (post_div1 * post_div2); - - // Configure clocks - // CLK_REF is the XOSC source - clock_configure_undivided(clk_ref, - CLOCKS_CLK_REF_CTRL_SRC_VALUE_XOSC_CLKSRC, - 0, // No aux mux - XOSC_HZ); - - // CLK SYS = PLL SYS (usually) 125MHz / 1 = 125MHz - clock_configure_undivided(clk_sys, - CLOCKS_CLK_SYS_CTRL_SRC_VALUE_CLKSRC_CLK_SYS_AUX, - CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS, - freq); - -#if PICO_CLOCK_ADJUST_PERI_CLOCK_WITH_SYS_CLOCK - clock_configure_undivided(clk_peri, - 0, - CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS, - freq); -#else - clock_configure_undivided(clk_peri, - 0, // Only AUX mux on ADC - CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB, - USB_CLK_HZ); -#endif - } -} - -bool check_sys_clock_hz(uint32_t freq_hz, uint *vco_out, uint *postdiv1_out, uint *postdiv2_out) { - uint reference_freq_hz = XOSC_HZ / PLL_SYS_REFDIV; - for (uint fbdiv = 320; fbdiv >= 16; fbdiv--) { - uint vco_hz = fbdiv * reference_freq_hz; - if (vco_hz < PICO_PLL_VCO_MIN_FREQ_HZ || vco_hz > PICO_PLL_VCO_MAX_FREQ_HZ) continue; - for (uint postdiv1 = 7; postdiv1 >= 1; postdiv1--) { - for (uint postdiv2 = postdiv1; postdiv2 >= 1; postdiv2--) { - uint out = vco_hz / (postdiv1 * postdiv2); - if (out == freq_hz && !(vco_hz % (postdiv1 * postdiv2))) { - *vco_out = vco_hz; - *postdiv1_out = postdiv1; - *postdiv2_out = postdiv2; - return true; - } - } - } - } - return false; -} - -// Note this impl is kept to preserve previous rounding behavior, vs calling check_sys_clock_hz -bool check_sys_clock_khz(uint32_t freq_khz, uint *vco_out, uint *postdiv1_out, uint *postdiv2_out) { - uint reference_freq_khz = (XOSC_HZ / KHZ) / PLL_SYS_REFDIV; - for (uint fbdiv = 320; fbdiv >= 16; fbdiv--) { - uint vco_khz = fbdiv * reference_freq_khz; - if (vco_khz < PICO_PLL_VCO_MIN_FREQ_HZ / KHZ || vco_khz > PICO_PLL_VCO_MAX_FREQ_HZ / KHZ) continue; - for (uint postdiv1 = 7; postdiv1 >= 1; postdiv1--) { - for (uint postdiv2 = postdiv1; postdiv2 >= 1; postdiv2--) { - uint out = vco_khz / (postdiv1 * postdiv2); - if (out == freq_khz && !(vco_khz % (postdiv1 * postdiv2))) { - *vco_out = vco_khz * KHZ; - *postdiv1_out = postdiv1; - *postdiv2_out = postdiv2; - return true; - } - } - } - } - return false; -} \ No newline at end of file diff --git a/lib/main/pico-sdk/rp2_common/hardware_clocks/include/hardware/clocks.h b/lib/main/pico-sdk/rp2_common/hardware_clocks/include/hardware/clocks.h deleted file mode 100644 index 7ad577e875..0000000000 --- a/lib/main/pico-sdk/rp2_common/hardware_clocks/include/hardware/clocks.h +++ /dev/null @@ -1,473 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _HARDWARE_CLOCKS_H -#define _HARDWARE_CLOCKS_H - -#include "pico.h" -#include "hardware/structs/clocks.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** \file hardware/clocks.h - * \defgroup hardware_clocks hardware_clocks - * - * \brief Clock Management API - * - * This API provides a high level interface to the clock functions. - * - * The clocks block provides independent clocks to on-chip and external components. It takes inputs from a variety of clock - * sources allowing the user to trade off performance against cost, board area and power consumption. From these sources - * it uses multiple clock generators to provide the required clocks. This architecture allows the user flexibility to start and - * stop clocks independently and to vary some clock frequencies whilst maintaining others at their optimum frequencies - * - * Please refer to the appropriate datasheet for more details on the RP-series clocks. - * - * The clock source depends on which clock you are attempting to configure. The first table below shows main clock sources. If - * you are not setting the Reference clock or the System clock, or you are specifying that one of those two will be using an auxiliary - * clock source, then you will need to use one of the entries from the subsequent tables. - * - * * \if rp2040_specific - * On RP2040 the clock sources are: - * - * **Main Clock Sources** - * - * Source | Reference Clock | System Clock - * -------|-----------------|--------- - * ROSC | CLOCKS_CLK_REF_CTRL_SRC_VALUE_ROSC_CLKSRC_PH | | - * Auxiliary | CLOCKS_CLK_REF_CTRL_SRC_VALUE_CLKSRC_CLK_REF_AUX | CLOCKS_CLK_SYS_CTRL_SRC_VALUE_CLKSRC_CLK_SYS_AUX - * XOSC | CLOCKS_CLK_REF_CTRL_SRC_VALUE_XOSC_CLKSRC | | - * Reference | | CLOCKS_CLK_SYS_CTRL_SRC_VALUE_CLK_REF - * - * **Auxiliary Clock Sources** - * - * The auxiliary clock sources available for use in the configure function depend on which clock is being configured. The following table - * describes the available values that can be used. Note that for clk_gpout[x], x can be 0-3. - * - * - * Aux Source | clk_gpout[x] | clk_ref | clk_sys - * -----------|------------|---------|-------- - * System PLL | CLOCKS_CLK_GPOUTx_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS | | CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS - * GPIO in 0 | CLOCKS_CLK_GPOUTx_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 | CLOCKS_CLK_REF_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 | CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 - * GPIO in 1 | CLOCKS_CLK_GPOUTx_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 | CLOCKS_CLK_REF_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 | CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 - * USB PLL | CLOCKS_CLK_GPOUTx_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB | CLOCKS_CLK_REF_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB| CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB - * ROSC | CLOCKS_CLK_GPOUTx_CTRL_AUXSRC_VALUE_ROSC_CLKSRC | | CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_ROSC_CLKSRC - * XOSC | CLOCKS_CLK_GPOUTx_CTRL_AUXSRC_VALUE_XOSC_CLKSRC | | CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_XOSC_CLKSRC - * System clock | CLOCKS_CLK_GPOUTx_CTRL_AUXSRC_VALUE_CLK_SYS | | | - * USB Clock | CLOCKS_CLK_GPOUTx_CTRL_AUXSRC_VALUE_CLK_USB | | | - * ADC clock | CLOCKS_CLK_GPOUTx_CTRL_AUXSRC_VALUE_CLK_ADC | | | - * RTC Clock | CLOCKS_CLK_GPOUTx_CTRL_AUXSRC_VALUE_CLK_RTC | | | - * Ref clock | CLOCKS_CLK_GPOUTx_CTRL_AUXSRC_VALUE_CLK_REF | | | - * - * Aux Source | clk_peri | clk_usb | clk_adc - * -----------|-----------|---------|-------- - * System PLL | CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS | CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS | CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS - * GPIO in 0 | CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 | CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 | CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 - * GPIO in 1 | CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 | CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 | CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 - * USB PLL | CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB | CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB | CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB - * ROSC | CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH | CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH | CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH - * XOSC | CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_XOSC_CLKSRC | CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_XOSC_CLKSRC | CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_XOSC_CLKSRC - * System clock | CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLK_SYS | | | - * - * Aux Source | clk_rtc - * -----------|---------- - * System PLL | CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS - * GPIO in 0 | CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 - * GPIO in 1 | CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 - * USB PLL | CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB - * ROSC | CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH - * XOSC | CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_XOSC_CLKSRC - * \endif - * - * \if rp2350_specific - * On RP2350 the clock sources are: - * * **Main Clock Sources** - * - * Source | Reference Clock | System Clock - * -------|-----------------|--------- - * ROSC | CLOCKS_CLK_REF_CTRL_SRC_VALUE_ROSC_CLKSRC_PH | | - * Auxiliary | CLOCKS_CLK_REF_CTRL_SRC_VALUE_CLKSRC_CLK_REF_AUX | CLOCKS_CLK_SYS_CTRL_SRC_VALUE_CLKSRC_CLK_SYS_AUX - * XOSC | CLOCKS_CLK_REF_CTRL_SRC_VALUE_XOSC_CLKSRC | | - * LPOSC | CLOCKS_CLK_REF_CTRL_SRC_VALUE_LPOSC_CLKSRC | | - * Reference | | CLOCKS_CLK_SYS_CTRL_SRC_VALUE_CLK_REF - * - * **Auxiliary Clock Sources** - * - * The auxiliary clock sources available for use in the configure function depend on which clock is being configured. The following table - * describes the available values that can be used. Note that for clk_gpout[x], x can be 0-3. - * - * - * Aux Source | clk_gpout[x] | clk_ref | clk_sys - * -----------|------------|---------|-------- - * System PLL | CLOCKS_CLK_GPOUTx_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS | | CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS - * GPIO in 0 | CLOCKS_CLK_GPOUTx_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 | CLOCKS_CLK_REF_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 | CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 - * GPIO in 1 | CLOCKS_CLK_GPOUTx_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 | CLOCKS_CLK_REF_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 | CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 - * USB PLL | CLOCKS_CLK_GPOUTx_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB | CLOCKS_CLK_REF_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB| CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB - * ROSC | CLOCKS_CLK_GPOUTx_CTRL_AUXSRC_VALUE_ROSC_CLKSRC | | CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_ROSC_CLKSRC - * XOSC | CLOCKS_CLK_GPOUTx_CTRL_AUXSRC_VALUE_XOSC_CLKSRC | | CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_XOSC_CLKSRC - * LPOSC | CLOCKS_CLK_GPOUTx_CTRL_AUXSRC_VALUE_LPOSC_CLKSRC | CLOCKS_CLK_REF_CTRL_AUXSRC_VALUE_LPOSC_CLKSRC | | - * System clock | CLOCKS_CLK_GPOUTx_CTRL_AUXSRC_VALUE_CLK_SYS | | | - * USB Clock | CLOCKS_CLK_GPOUTx_CTRL_AUXSRC_VALUE_CLK_USB | | | - * ADC clock | CLOCKS_CLK_GPOUTx_CTRL_AUXSRC_VALUE_CLK_ADC | | | - * REF clock | CLOCKS_CLK_GPOUTx_CTRL_AUXSRC_VALUE_CLK_REF | | | - * PERI clock | CLOCKS_CLK_GPOUTx_CTRL_AUXSRC_VALUE_CLK_PERI | | | - * HSTX clock | CLOCKS_CLK_GPOUTx_CTRL_AUXSRC_VALUE_CLK_PERI | | | - - * - * Aux Source | clk_peri | clk_hstx | clk_usb | clk_adc - * -----------|-----------|----------|---------|-------- - * System PLL | CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS | CLOCKS_CLK_HSTX_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS | CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS | CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS - * GPIO in 0 | CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 | | CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 | CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 - * GPIO in 1 | CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 | | CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 | CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 - * USB PLL | CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB | CLOCKS_CLK_HSTX_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB | CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB | CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB - * ROSC | CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH | | CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH | CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH - * XOSC | CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_XOSC_CLKSRC | | CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_XOSC_CLKSRC | CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_XOSC_CLKSRC - * System clock | CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLK_SYS | CLOCKS_CLK_HSTX_CTRL_AUXSRC_VALUE_CLK_SYS | | | - * \endif - - * - * \section clock_example Example - * \addtogroup hardware_clocks - * \include hello_48MHz.c - */ - -#define KHZ 1000 -#define MHZ 1000000 - -// \tag::pll_settings[] -// There are two PLLs in RP-series microcontrollers: -// 1. The 'SYS PLL' generates the system clock, the frequency is defined by `SYS_CLK_KHZ`. -// 2. The 'USB PLL' generates the USB clock, the frequency is defined by `USB_CLK_KHZ`. -// -// The two PLLs use the crystal oscillator output directly as their reference frequency input; the PLLs reference -// frequency cannot be reduced by the dividers present in the clocks block. The crystal frequency is defined by `XOSC_HZ` (or -// `XOSC_KHZ` or `XOSC_MHZ`). -// -// The system's default definitions are correct for the above frequencies with a 12MHz -// crystal frequency. If different frequencies are required, these must be defined in -// the board configuration file together with the revised PLL settings -// Use `vcocalc.py` to check and calculate new PLL settings if you change any of these frequencies. -// -// Default PLL configuration RP2040: -// REF FBDIV VCO POSTDIV -// PLL SYS: 12 / 1 = 12MHz * 125 = 1500MHz / 6 / 2 = 125MHz -// PLL USB: 12 / 1 = 12MHz * 100 = 1200MHz / 5 / 5 = 48MHz -// -// Default PLL configuration RP2350: -// REF FBDIV VCO POSTDIV -// PLL SYS: 12 / 1 = 12MHz * 125 = 1500MHz / 5 / 2 = 150MHz -// PLL USB: 12 / 1 = 12MHz * 100 = 1200MHz / 5 / 5 = 48MHz -// \end::pll_settings[] - -#ifndef PLL_COMMON_REFDIV -// backwards compatibility, but now deprecated -#define PLL_COMMON_REFDIV 1 -#endif - -// PICO_CONFIG: PLL_SYS_REFDIV, PLL reference divider setting for PLL_SYS, type=int, default=1, advanced=true, group=hardware_clocks -#ifndef PLL_SYS_REFDIV -// backwards compatibility with deprecated PLL_COMMON_REFDIV -#ifdef PLL_COMMON_REFDIV -#define PLL_SYS_REFDIV PLL_COMMON_REFDIV -#else -#define PLL_SYS_REFDIV 1 -#endif -#endif - -#ifndef PLL_SYS_VCO_FREQ_HZ -// For backwards compatibility define PLL_SYS_VCO_FREQ_HZ if PLL_SYS_VCO_FREQ_KHZ is defined -#ifdef PLL_SYS_VCO_FREQ_KHZ -#define PLL_SYS_VCO_FREQ_HZ (PLL_SYS_VCO_FREQ_KHZ * KHZ) -#endif -#endif - -#if (SYS_CLK_HZ == 125 * MHZ || SYS_CLK_HZ == 150 * MHZ) && (XOSC_HZ == 12 * MHZ) && (PLL_SYS_REFDIV == 1) -// PLL settings for standard 125/150 MHz system clock. -// PICO_CONFIG: PLL_SYS_VCO_FREQ_HZ, System clock PLL frequency, type=int, default=(1500 * MHZ), advanced=true, group=hardware_clocks -#ifndef PLL_SYS_VCO_FREQ_HZ -#define PLL_SYS_VCO_FREQ_HZ (1500 * MHZ) -#endif -// PICO_CONFIG: PLL_SYS_POSTDIV1, System clock PLL post divider 1 setting, type=int, default=6 on RP2040 or 5 on RP2350, advanced=true, group=hardware_clocks -#ifndef PLL_SYS_POSTDIV1 -#if SYS_CLK_HZ == 125 * MHZ -#define PLL_SYS_POSTDIV1 6 -#else -#define PLL_SYS_POSTDIV1 5 -#endif -#endif -// PICO_CONFIG: PLL_SYS_POSTDIV2, System clock PLL post divider 2 setting, type=int, default=2, advanced=true, group=hardware_clocks -#ifndef PLL_SYS_POSTDIV2 -#define PLL_SYS_POSTDIV2 2 -#endif -#endif // SYS_CLK_KHZ == 125000 && XOSC_KHZ == 12000 && PLL_COMMON_REFDIV == 1 - -#if !defined(PLL_SYS_VCO_FREQ_HZ) || !defined(PLL_SYS_POSTDIV1) || !defined(PLL_SYS_POSTDIV2) -#error PLL_SYS_VCO_FREQ_HZ, PLL_SYS_POSTDIV1 and PLL_SYS_POSTDIV2 must all be specified when using custom clock setup -#endif - -// PICO_CONFIG: PLL_USB_REFDIV, PLL reference divider setting for PLL_USB, type=int, default=1, advanced=true, group=hardware_clocks -#ifndef PLL_USB_REFDIV -// backwards compatibility with deprecated PLL_COMMON_REFDIV -#ifdef PLL_COMMON_REFDIV -#define PLL_USB_REFDIV PLL_COMMON_REFDIV -#else -#define PLL_USB_REFDIV 1 -#endif -#endif - -#ifndef PLL_USB_VCO_FREQ_HZ -// For backwards compatibility define PLL_USB_VCO_FREQ_HZ if PLL_USB_VCO_FREQ_KHZ is defined -#ifdef PLL_USB_VCO_FREQ_KHZ -#define PLL_USB_VCO_FREQ_HZ (PLL_USB_VCO_FREQ_KHZ * KHZ) -#endif -#endif - -#if (USB_CLK_HZ == 48 * MHZ) && (XOSC_HZ == 12 * MHZ) && (PLL_USB_REFDIV == 1) -// PLL settings for a USB clock of 48MHz. -// PICO_CONFIG: PLL_USB_VCO_FREQ_HZ, USB clock PLL frequency, type=int, default=(1200 * MHZ), advanced=true, group=hardware_clocks -#ifndef PLL_USB_VCO_FREQ_HZ -#define PLL_USB_VCO_FREQ_HZ (1200 * MHZ) -#endif -// PICO_CONFIG: PLL_USB_POSTDIV1, USB clock PLL post divider 1 setting, type=int, default=5, advanced=true, group=hardware_clocks -#ifndef PLL_USB_POSTDIV1 -#define PLL_USB_POSTDIV1 5 -#endif -// PICO_CONFIG: PLL_USB_POSTDIV2, USB clock PLL post divider 2 setting, type=int, default=5, advanced=true, group=hardware_clocks -#ifndef PLL_USB_POSTDIV2 -#define PLL_USB_POSTDIV2 5 -#endif -#endif // USB_CLK_HZ == 48000000 && XOSC_HZ == 12000000 && PLL_COMMON_REFDIV == 1 -#if !defined(PLL_USB_VCO_FREQ_HZ) || !defined(PLL_USB_POSTDIV1) || !defined(PLL_USB_POSTDIV2) -#error PLL_USB_VCO_FREQ_HZ, PLL_USB_POSTDIV1 and PLL_USB_POSTDIV2 must all be specified when using custom clock setup. -#endif - -// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_HARDWARE_CLOCKS, Enable/disable assertions in the hardware_clocks module, type=bool, default=0, group=hardware_clocks -#ifndef PARAM_ASSERTIONS_ENABLED_HARDWARE_CLOCKS -#ifdef PARAM_ASSERTIONS_ENABLED_CLOCKS // backwards compatibility with SDK < 2.0.0 -#define PARAM_ASSERTIONS_ENABLED_HARDWARE_CLOCKS PARAM_ASSERTIONS_ENABLED_CLOCKS -#else -#define PARAM_ASSERTIONS_ENABLED_HARDWARE_CLOCKS 0 -#endif -#endif - -typedef clock_num_t clock_handle_t; - -/*! \brief Configure the specified clock - * \ingroup hardware_clocks - * - * See the tables in the description for details on the possible values for clock sources. - * - * \param clock The clock to configure - * \param src The main clock source, can be 0. - * \param auxsrc The auxiliary clock source, which depends on which clock is being set. Can be 0 - * \param src_freq Frequency of the input clock source - * \param freq Requested frequency - */ -bool clock_configure(clock_handle_t clock, uint32_t src, uint32_t auxsrc, uint32_t src_freq, uint32_t freq); - -/*! \brief Configure the specified clock to use the undividded input source - * \ingroup hardware_clocks - * - * See the tables in the description for details on the possible values for clock sources. - * - * \param clock The clock to configure - * \param src The main clock source, can be 0. - * \param auxsrc The auxiliary clock source, which depends on which clock is being set. Can be 0 - * \param src_freq Frequency of the input clock source - */ -void clock_configure_undivided(clock_handle_t clock, uint32_t src, uint32_t auxsrc, uint32_t src_freq); - -/*! \brief Configure the specified clock to use the undividded input source - * \ingroup hardware_clocks - * - * See the tables in the description for details on the possible values for clock sources. - * - * \param clock The clock to configure - * \param src The main clock source, can be 0. - * \param auxsrc The auxiliary clock source, which depends on which clock is being set. Can be 0 - * \param src_freq Frequency of the input clock source - * \param int_divider an integer divider - */ -void clock_configure_int_divider(clock_handle_t clock, uint32_t src, uint32_t auxsrc, uint32_t src_freq, uint32_t int_divider); - -/*! \brief Stop the specified clock - * \ingroup hardware_clocks - * - * \param clock The clock to stop - */ -void clock_stop(clock_handle_t clock); - -/*! \brief Get the current frequency of the specified clock - * \ingroup hardware_clocks - * - * \param clock Clock - * \return Clock frequency in Hz - */ -uint32_t clock_get_hz(clock_handle_t clock); - -/*! \brief Measure a clocks frequency using the Frequency counter. - * \ingroup hardware_clocks - * - * Uses the inbuilt frequency counter to measure the specified clocks frequency. - * Currently, this function is accurate to +-1KHz. See the datasheet for more details. - */ -uint32_t frequency_count_khz(uint src); - -/*! \brief Set the "current frequency" of the clock as reported by clock_get_hz without actually changing the clock - * \ingroup hardware_clocks - * - * \see clock_get_hz() - */ -void clock_set_reported_hz(clock_handle_t clock, uint hz); - -/// \tag::frequency_count_mhz[] -static inline float frequency_count_mhz(uint src) { - return ((float) (frequency_count_khz(src))) / KHZ; -} -/// \end::frequency_count_mhz[] - -/*! \brief Resus callback function type. - * \ingroup hardware_clocks - * - * User provided callback for a resus event (when clk_sys is stopped by the programmer and is restarted for them). - */ -typedef void (*resus_callback_t)(void); - -/*! \brief Enable the resus function. Restarts clk_sys if it is accidentally stopped. - * \ingroup hardware_clocks - * - * The resuscitate function will restart the system clock if it falls below a certain speed (or stops). This - * could happen if the clock source the system clock is running from stops. For example if a PLL is stopped. - * - * \param resus_callback a function pointer provided by the user to call if a resus event happens. - */ -void clocks_enable_resus(resus_callback_t resus_callback); - -/*! \brief Output an optionally divided clock to the specified gpio pin. - * \ingroup hardware_clocks - * - * \param gpio The GPIO pin to output the clock to. Valid GPIOs are: 21, 23, 24, 25. These GPIOs are connected to the GPOUT0-3 clock generators. - * \param src The source clock. See the register field CLOCKS_CLK_GPOUT0_CTRL_AUXSRC for a full list. The list is the same for each GPOUT clock generator. - * \param div_int The integer part of the value to divide the source clock by. This is useful to not overwhelm the GPIO pin with a fast clock. this is in range of 1..2^24-1. - * \param div_frac The fractional part of the value to divide the source clock by. This is in range of 0..255 (/256). - */ -void clock_gpio_init_int_frac(uint gpio, uint src, uint32_t div_int, uint8_t div_frac); - -/*! \brief Output an optionally divided clock to the specified gpio pin. - * \ingroup hardware_clocks - * - * \param gpio The GPIO pin to output the clock to. Valid GPIOs are: 21, 23, 24, 25. These GPIOs are connected to the GPOUT0-3 clock generators. - * \param src The source clock. See the register field CLOCKS_CLK_GPOUT0_CTRL_AUXSRC for a full list. The list is the same for each GPOUT clock generator. - * \param div The float amount to divide the source clock by. This is useful to not overwhelm the GPIO pin with a fast clock. - */ -static inline void clock_gpio_init(uint gpio, uint src, float div) -{ - uint div_int = (uint)div; - uint8_t frac = (uint8_t)((div - (float)div_int) * (1u << CLOCKS_CLK_GPOUT0_DIV_INT_LSB)); - clock_gpio_init_int_frac(gpio, src, div_int, frac); -} - -/*! \brief Configure a clock to come from a gpio input - * \ingroup hardware_clocks - * - * \param clock The clock to configure - * \param gpio The GPIO pin to run the clock from. Valid GPIOs are: 20 and 22. - * \param src_freq Frequency of the input clock source - * \param freq Requested frequency - */ -bool clock_configure_gpin(clock_handle_t clock, uint gpio, uint32_t src_freq, uint32_t freq); - -/*! \brief Initialise the system clock to 48MHz - * \ingroup hardware_clocks - * - * Set the system clock to 48MHz, and set the peripheral clock to match. - */ -void set_sys_clock_48mhz(void); - -/*! \brief Initialise the system clock - * \ingroup hardware_clocks - * - * \param vco_freq The voltage controller oscillator frequency to be used by the SYS PLL - * \param post_div1 The first post divider for the SYS PLL - * \param post_div2 The second post divider for the SYS PLL. - * - * See the PLL documentation in the datasheet for details of driving the PLLs. - */ -void set_sys_clock_pll(uint32_t vco_freq, uint post_div1, uint post_div2); - -/*! \brief Check if a given system clock frequency is valid/attainable - * \ingroup hardware_clocks - * - * \param freq_hz Requested frequency - * \param vco_freq_out On success, the voltage controlled oscillator frequency to be used by the SYS PLL - * \param post_div1_out On success, The first post divider for the SYS PLL - * \param post_div2_out On success, The second post divider for the SYS PLL. - * @return true if the frequency is possible and the output parameters have been written. - */ -bool check_sys_clock_hz(uint32_t freq_hz, uint *vco_freq_out, uint *post_div1_out, uint *post_div2_out); - -/*! \brief Check if a given system clock frequency is valid/attainable - * \ingroup hardware_clocks - * - * \param freq_khz Requested frequency - * \param vco_freq_out On success, the voltage controlled oscillator frequency to be used by the SYS PLL - * \param post_div1_out On success, The first post divider for the SYS PLL - * \param post_div2_out On success, The second post divider for the SYS PLL. - * @return true if the frequency is possible and the output parameters have been written. - */ -bool check_sys_clock_khz(uint32_t freq_khz, uint *vco_freq_out, uint *post_div1_out, uint *post_div2_out); - -/*! \brief Attempt to set a system clock frequency in hz - * \ingroup hardware_clocks - * - * Note that not all clock frequencies are possible; it is preferred that you - * use src/rp2_common/hardware_clocks/scripts/vcocalc.py to calculate the parameters - * for use with set_sys_clock_pll - * - * \param freq_hz Requested frequency - * \param required if true then this function will assert if the frequency is not attainable. - * \return true if the clock was configured - */ -static inline bool set_sys_clock_hz(uint32_t freq_hz, bool required) { - uint vco, postdiv1, postdiv2; - if (check_sys_clock_hz(freq_hz, &vco, &postdiv1, &postdiv2)) { - set_sys_clock_pll(vco, postdiv1, postdiv2); - return true; - } else if (required) { - panic("System clock of %u Hz cannot be exactly achieved", freq_hz); - } - return false; -} - -/*! \brief Attempt to set a system clock frequency in khz - * \ingroup hardware_clocks - * - * Note that not all clock frequencies are possible; it is preferred that you - * use src/rp2_common/hardware_clocks/scripts/vcocalc.py to calculate the parameters - * for use with set_sys_clock_pll - * - * \param freq_khz Requested frequency - * \param required if true then this function will assert if the frequency is not attainable. - * \return true if the clock was configured - */ -static inline bool set_sys_clock_khz(uint32_t freq_khz, bool required) { - uint vco, postdiv1, postdiv2; - if (check_sys_clock_khz(freq_khz, &vco, &postdiv1, &postdiv2)) { - set_sys_clock_pll(vco, postdiv1, postdiv2); - return true; - } else if (required) { - panic("System clock of %u kHz cannot be exactly achieved", freq_khz); - } - return false; -} - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/lib/main/pico-sdk/rp2_common/hardware_clocks/scripts/vcocalc.py b/lib/main/pico-sdk/rp2_common/hardware_clocks/scripts/vcocalc.py deleted file mode 100644 index 08cca41262..0000000000 --- a/lib/main/pico-sdk/rp2_common/hardware_clocks/scripts/vcocalc.py +++ /dev/null @@ -1,84 +0,0 @@ -#!/usr/bin/env python3 - -import argparse -import sys - -# Fixed hardware parameters -fbdiv_range = range(16, 320 + 1) -postdiv_range = range(1, 7 + 1) -ref_min = 5 -refdiv_min = 1 -refdiv_max = 63 - -def validRefdiv(string): - if ((int(string) < refdiv_min) or (int(string) > refdiv_max)): - raise ValueError("REFDIV must be in the range {} to {}".format(refdiv_min, refdiv_max)) - return int(string) - -parser = argparse.ArgumentParser(description="PLL parameter calculator") -parser.add_argument("--input", "-i", default=12, help="Input (reference) frequency. Default 12 MHz", type=float) -parser.add_argument("--ref-min", default=5, help="Override minimum reference frequency. Default 5 MHz", type=float) -parser.add_argument("--vco-max", default=1600, help="Override maximum VCO frequency. Default 1600 MHz", type=float) -parser.add_argument("--vco-min", default=750, help="Override minimum VCO frequency. Default 750 MHz", type=float) -parser.add_argument("--cmake", action="store_true", help="Print out a CMake snippet to apply the selected PLL parameters to your program") -parser.add_argument("--cmake-only", action="store_true", help="Same as --cmake, but do not print anything other than the CMake output") -parser.add_argument("--cmake-executable-name", default="", help="Set the executable name to use in the generated CMake output") -parser.add_argument("--lock-refdiv", help="Lock REFDIV to specified number in the range {} to {}".format(refdiv_min, refdiv_max), type=validRefdiv) -parser.add_argument("--low-vco", "-l", action="store_true", help="Use a lower VCO frequency when possible. This reduces power consumption, at the cost of increased jitter") -parser.add_argument("output", help="Output frequency in MHz.", type=float) -args = parser.parse_args() - -refdiv_range = range(refdiv_min, max(refdiv_min, min(refdiv_max, int(args.input / args.ref_min))) + 1) -if args.lock_refdiv: - print("Locking REFDIV to", args.lock_refdiv) - refdiv_range = [args.lock_refdiv] - -best = (0, 0, 0, 0, 0, 0) -best_margin = args.output - -for refdiv in refdiv_range: - for fbdiv in fbdiv_range: - vco = args.input / refdiv * fbdiv - if vco < args.vco_min or vco > args.vco_max: - continue - # pd1 is inner loop so that we prefer higher ratios of pd1:pd2 - for pd2 in postdiv_range: - for pd1 in postdiv_range: - out = vco / pd1 / pd2 - margin = abs(out - args.output) - vco_is_better = vco < best[5] if args.low_vco else vco > best[5] - if ((vco * 1000) % (pd1 * pd2)): - continue - if margin < best_margin or (abs(margin - best_margin) < 1e-9 and vco_is_better): - best = (out, fbdiv, pd1, pd2, refdiv, vco) - best_margin = margin - -best_out, best_fbdiv, best_pd1, best_pd2, best_refdiv, best_vco = best - -if best[0] > 0: - cmake_output = \ -f"""target_compile_definitions({args.cmake_executable_name} PRIVATE - PLL_SYS_REFDIV={best_refdiv} - PLL_SYS_VCO_FREQ_HZ={int((args.input * 1_000_000) / best_refdiv * best_fbdiv)} - PLL_SYS_POSTDIV1={best_pd1} - PLL_SYS_POSTDIV2={best_pd2} -) -""" - if not args.cmake_only: - print("Requested: {} MHz".format(args.output)) - print("Achieved: {} MHz".format(best_out)) - print("REFDIV: {}".format(best_refdiv)) - print("FBDIV: {} (VCO = {} MHz)".format(best_fbdiv, args.input / best_refdiv * best_fbdiv)) - print("PD1: {}".format(best_pd1)) - print("PD2: {}".format(best_pd2)) - if best_refdiv != 1: - print( - "\nThis requires a non-default REFDIV value.\n" - "Add the following to your CMakeLists.txt to apply the REFDIV:\n" - ) - elif args.cmake or args.cmake_only: - print("") - if args.cmake or args.cmake_only or best_refdiv != 1: - print(cmake_output) -else: - sys.exit("No solution found") diff --git a/lib/main/pico-sdk/rp2_common/hardware_dcp/doc.h b/lib/main/pico-sdk/rp2_common/hardware_dcp/doc.h deleted file mode 100644 index 4ccef81edf..0000000000 --- a/lib/main/pico-sdk/rp2_common/hardware_dcp/doc.h +++ /dev/null @@ -1,4 +0,0 @@ -/** - * \defgroup hardware_dcp hardware_dcp - * \brief Assembly macros for the Double Coprocessor - */ diff --git a/lib/main/pico-sdk/rp2_common/hardware_dcp/include/hardware/dcp_canned.inc.S b/lib/main/pico-sdk/rp2_common/hardware_dcp/include/hardware/dcp_canned.inc.S deleted file mode 100644 index e4fe2fe6f6..0000000000 --- a/lib/main/pico-sdk/rp2_common/hardware_dcp/include/hardware/dcp_canned.inc.S +++ /dev/null @@ -1,420 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -// Canned instruction sequences for use with the DCP - -.macro dcp_fadd_m rz,rx,ry - WXYU \rx,\ry - ADD0 - ADD1 - NRDF - RDFA \rz -.endm - -.macro dcp_fsub_m rz,rx,ry - WXYU \rx,\ry - ADD0 - SUB1 - NRDF - RDFS \rz -.endm - -.macro dcp_fmul_m rz,rx,ry,ra,rb - WXYU \rx,\ry - RXYH \ra,\rb - umull \ra,\rb,\ra,\rb - WXFM \ra,\rb - NRDF - RDFM \rz -.endm - -.macro dcp_fxprod_m rzl,rzh,rx,ry,ra,rb - WXYU \rx,\ry - RXYH \ra,\rb - umull \ra,\rb,\ra,\rb - WXMO \ra,\rb - NRDD - RDDM \rzl,\rzh -.endm - -.macro dcp_fdiv_fast_m rz,rx,ry,ra,rb,rc - WXYU \rx,\ry - RYMR \ra,\rb - umull \rb,\rc,\ra,\rb - mvn \rc,\rc,lsl #2 - smmlar \ra,\rc,\ra,\ra - smmulr \rc,\rc,\rc - smmlar \ra,\rc,\ra,\ra - RXYH \rb,\rc - umull \ra,\rb,\ra,\rb - WXFD \rb,\rb - NRDF - RDFD \rz -.endm - -.macro dcp_fdiv_m rz,rx,ry,ra,rb,rc,rd - WXYU \rx,\ry - RYMR \ra,\rb - umull \rb,\rc,\ra,\rb - mvn \rc,\rc,lsl #2 - smmlar \ra,\rc,\ra,\ra - smmulr \rc,\rc,\rc - smmlar \ra,\rc,\ra,\ra - RXYH \rb,\rc - umull \rd,\ra,\ra,\rb - orr \ra,\ra,\ra,lsr #24 - bic \ra,\ra,\ra,lsr #25 - bic \ra,\ra,#15 - mov \rc,\rc,lsr #7 - mul \rd,\ra,\rc - rsb \rd,\rd,\rb,lsl #22 - sub \ra,\ra,\rd,lsr #31 - WXFD \ra,\ra - NRDF - RDFD \rz -.endm - -.macro dcp_fsqrt_fast_m rz,rx,ra,rb,rc,rd - WXYU \rx,\rx - SQR0 - RXMQ \rc,\rd - umull \ra,\rb,\rc,\rc - umull \ra,\rb,\rb,\rd - mov \rb,\rb,lsl #3 - sub \rb,\rb,#2147483648 - smmlsr \rc,\rc,\rb,\rc - umull \ra,\rb,\rc,\rc - umull \ra,\rb,\rb,\rd - movs \ra,\ra,lsr #28 - adc \rb,\ra,\rb,lsl #4 - smmulr \ra,\rb,\rc - sub \rc,\rc,\ra,asr #1 - umull \ra,\rb,\rc,\rd - WXFQ \ra,\rb - NRDF - RDFQ \rz -.endm - -.macro dcp_fsqrt_m rz,rx,ra,rb,rc,rd - WXYU \rx,\rx - SQR0 - RXMQ \rc,\rd - umull \ra,\rb,\rc,\rc - umull \ra,\rb,\rb,\rd - mov \rb,\rb,lsl #3 - sub \rb,\rb,#2147483648 - smmlsr \rc,\rc,\rb,\rc - umull \ra,\rb,\rc,\rc - umull \ra,\rb,\rb,\rd - movs \ra,\ra,lsr #28 - adc \rb,\ra,\rb,lsl #4 - smmulr \ra,\rb,\rc - sub \rc,\rc,\ra,asr #1 - umull \ra,\rb,\rc,\rd - orr \rb,\rb,#63 - mov \ra,\rb,lsr #5 - mul \ra,\ra,\ra - rsb \ra,\ra,\rd,lsl #18 - bic \rb,\rb,\ra,lsr #26 - WXFQ \ra,\rb - NRDF - RDFQ \rz -.endm - -.macro dcp_fclassify_m rz,rx - WXYU \rx,\rx - RXVD \rz -.endm - -.macro dcp_fcmp_m rz,rx,ry - WXYU \rx,\ry - ADD0 - RCMP \rz -.endm - -.macro dcp_dadd_m rzl,rzh,rxl,rxh,ryl,ryh - WXUP \rxl,\rxh - WYUP \ryl,\ryh - ADD0 - ADD1 - NRDD - RDDA \rzl,\rzh -.endm - -.macro dcp_dsub_m rzl,rzh,rxl,rxh,ryl,ryh - WXUP \rxl,\rxh - WYUP \ryl,\ryh - ADD0 - SUB1 - NRDD - RDDS \rzl,\rzh -.endm - -.macro dcp_dmul_m rzl,rzh,rxl,rxh,ryl,ryh,ra,rb,rc,rd,re,rf,rg - WXUP \rxl,\rxh - WYUP \ryl,\ryh - RXMS \ra,\rb,0 - RYMS \rc,\rd,0 - umull \re,\rf,\ra,\rc - movs \rg,#0 - umlal \rf,\rg,\ra,\rd - umlal \rf,\rg,\rb,\rc - WXMS \re,\rf - movs \re,#0 - umlal \rg,\re,\rb,\rd - WXMO \rg,\re - NRDD - RDDM \rzl,\rzh -.endm - -.macro dcp_ddiv_fast_m rzl,rzh,rxl,rxh,ryl,ryh,ra,rb,rc,rd,re - WXUP \rxl,\rxh - WYUP \ryl,\ryh - RYMR \ra,\rb - umull \rb,\rc,\ra,\rb - mvn \rc,\rc,lsl #2 - smmlar \ra,\rc,\ra,\ra - smmulr \rc,\rc,\rc - smmlar \ra,\rc,\ra,\ra - sub \re,\ra,\ra,lsr #31 - RXMS \rc,\rd,0 - smmulr \rb,\re,\rd - RYMS \rc,\rd,1 - umull \rc,\ra,\rb,\rc - mla \ra,\rb,\rd,\ra - RXMS \rc,\rd,4 - sub \ra,\rc,\ra - smmulr \rc,\ra,\re - mov \rd,\rb,lsr #4 - adds \ra,\rc,\rb,lsl #28 - adc \rb,\rd,\rc,asr #31 - WXDD \ra,\rb - NRDD - RDDD \rzl,\rzh -.endm - -.macro dcp_ddiv_m rzl,rzh,rxl,rxh,ryl,ryh,ra,rb,rc,rd,re - WXUP \rxl,\rxh - WYUP \ryl,\ryh - RYMR \ra,\rb - umull \rb,\rc,\ra,\rb - mvn \rc,\rc,lsl #2 - smmlar \ra,\rc,\ra,\ra - smmulr \rc,\rc,\rc - smmlar \ra,\rc,\ra,\ra - sub \re,\ra,\ra,lsr #31 - RXMS \rc,\rd,0 - smmulr \rb,\re,\rd - RYMS \rc,\rd,1 - umull \rc,\ra,\rb,\rc - mla \ra,\rb,\rd,\ra - RXMS \rc,\rd,4 - sub \ra,\rc,\ra - smmulr \rc,\ra,\re - mov \rd,\rb,lsr #4 - adds \ra,\rc,\rb,lsl #28 - adc \rb,\rd,\rc,asr #31 - orr \ra,\ra,\rb,lsr #21 - bic \ra,\ra,\rb,lsr #22 - bic \ra,\ra,#7 - RYMS \rc,\rd,7 - umull \rd,\re,\ra,\rc - RYMS \rc,\rd,7 - mla \re,\ra,\rd,\re - mla \re,\rb,\rc,\re - RXMS \rc,\rd,0 - sub \re,\re,\rc,lsl #18 - orr \ra,\ra,\re,lsr #29 - sub \ra,\ra,#1 - WXDD \ra,\rb - NRDD - RDDD \rzl,\rzh -.endm - -.macro dcp_dsqrt_fast_m rzl,rzh,rxl,rxh,ra,rb,rc,rd,re - WXUP \rxl,\rxh - SQR0 - RXMQ \rc,\rd - umull \ra,\rb,\rc,\rc - umull \ra,\rb,\rb,\rd - mov \rb,\rb,lsl #3 - sub \rb,\rb,#2147483648 - smmlsr \rc,\rc,\rb,\rc - umull \ra,\rb,\rc,\rc - umull \ra,\rb,\rb,\rd - movs \ra,\ra,lsr #28 - adc \rb,\ra,\rb,lsl #4 - smmulr \ra,\rb,\rc - sub \rc,\rc,\ra,asr #1 - umull \ra,\rb,\rc,\rd - mov \rb,\rb,lsr #1 - umull \rd,\ra,\rb,\rb - RXMS \ra,\re,6 - sub \ra,\ra,\rd - smmulr \ra,\ra,\rc - add \rb,\rb,\ra,asr #28 - mov \ra,\ra,lsl #4 - WXDQ \ra,\rb - NRDD - RDDQ \rzl,\rzh -.endm - -.macro dcp_dsqrt_m rzl,rzh,rxl,rxh,ra,rb,rc,rd,re - WXUP \rxl,\rxh - SQR0 - RXMQ \rc,\rd - umull \ra,\rb,\rc,\rc - umull \ra,\rb,\rb,\rd - mov \rb,\rb,lsl #3 - sub \rb,\rb,#2147483648 - smmlsr \rc,\rc,\rb,\rc - umull \ra,\rb,\rc,\rc - umull \ra,\rb,\rb,\rd - movs \ra,\ra,lsr #28 - adc \rb,\ra,\rb,lsl #4 - smmulr \ra,\rb,\rc - sub \rc,\rc,\ra,asr #1 - umull \ra,\rb,\rc,\rd - mov \rb,\rb,lsr #1 - umull \rd,\ra,\rb,\rb - RXMS \ra,\re,6 - sub \rd,\ra,\rd - smmulr \rd,\rd,\rc - add \rb,\rb,\rd,asr #28 - mov \rd,\rd,lsl #4 - bic \rd,\rd,#255 - orr \rd,\rd,#128 - umull \re,\rc,\rd,\rd - mul \re,\rb,\rb - umlal \rc,\re,\rb,\rd - umlal \rc,\re,\rb,\rd - sub \re,\re,\ra - orr \rd,\rd,\re,lsr #24 - sub \rd,\rd,#11 - WXDQ \rd,\rb - NRDD - RDDQ \rzl,\rzh -.endm - -.macro dcp_dclassify_m rz,rxl,rxh - WXUP \rxl,\rxh - RXVD \rz -.endm - -.macro dcp_dcmp_m rz,rxl,rxh,ryl,ryh - WXUP \rxl,\rxh - WYUP \ryl,\ryh - ADD0 - RCMP \rz -.endm - -.macro dcp_float2double_m rzl,rzh,rx - WXYU \rx,\rx - NRDD - RDDG \rzl,\rzh -.endm - -.macro dcp_double2float_m rz,rxl,rxh - WXUP \rxl,\rxh - NRDF - RDFG \rz -.endm - -.macro dcp_int2double_m rzl,rzh,rx - WXIC \rx,\rx - ADD0 - SUB1 - NRDD - RDDS \rzl,\rzh -.endm - -.macro dcp_uint2double_m rzl,rzh,rx - WXUC \rx,\rx - ADD0 - SUB1 - NRDD - RDDS \rzl,\rzh -.endm - -.macro dcp_int2float_m rz,rx - WXIC \rx,\rx - ADD0 - SUB1 - NRDF - RDFS \rz -.endm - -.macro dcp_uint2float_m rz,rx - WXUC \rx,\rx - ADD0 - SUB1 - NRDF - RDFS \rz -.endm - -.macro dcp_double2int_m rz,rxl,rxh - WXDC \rxl,\rxh - ADD0 - ADD1 - NTDC - RDIC \rz -.endm - -.macro dcp_double2uint_m rz,rxl,rxh - WXDC \rxl,\rxh - ADD0 - ADD1 - NTDC - RDUC \rz -.endm - -.macro dcp_float2int_m rz,rx - WXFC \rx,\rx - ADD0 - ADD1 - NTDC - RDIC \rz -.endm - -.macro dcp_float2uint_m rz,rx - WXFC \rx,\rx - ADD0 - ADD1 - NTDC - RDUC \rz -.endm - -.macro dcp_double2int_r_m rz,rxl,rxh - WXDC \rxl,\rxh - ADD0 - ADD1 - NRDC - RDIC \rz -.endm - -.macro dcp_double2uint_r_m rz,rxl,rxh - WXDC \rxl,\rxh - ADD0 - ADD1 - NRDC - RDUC \rz -.endm - -.macro dcp_float2int_r_m rz,rx - WXFC \rx,\rx - ADD0 - ADD1 - NRDC - RDIC \rz -.endm - -.macro dcp_float2uint_r_m rz,rx - WXFC \rx,\rx - ADD0 - ADD1 - NRDC - RDUC \rz -.endm diff --git a/lib/main/pico-sdk/rp2_common/hardware_dcp/include/hardware/dcp_instr.inc.S b/lib/main/pico-sdk/rp2_common/hardware_dcp/include/hardware/dcp_instr.inc.S deleted file mode 100644 index 2dc2f523c1..0000000000 --- a/lib/main/pico-sdk/rp2_common/hardware_dcp/include/hardware/dcp_instr.inc.S +++ /dev/null @@ -1,232 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -.macro INIT - cdp p4,#0,c0,c0,c0,#0 -.endm -.macro ADD0 - cdp p4,#0,c0,c0,c1,#0 -.endm -.macro ADD1 - cdp p4,#1,c0,c0,c1,#0 -.endm -.macro SUB1 - cdp p4,#1,c0,c0,c1,#1 -.endm -.macro SQR0 - cdp p4,#2,c0,c0,c1,#0 -.endm -.macro NORM - cdp p4,#8,c0,c0,c2,#0 -.endm -.macro NRDF - cdp p4,#8,c0,c0,c2,#1 -.endm -.macro NRDD - cdp p4,#8,c0,c0,c0,#1 -.endm -.macro NTDC - cdp p4,#8,c0,c0,c0,#2 -.endm -.macro NRDC - cdp p4,#8,c0,c0,c0,#3 -.endm -.macro WXMD rl,rh - mcrr p4,#0,\rl,\rh,c0 -.endm -.macro WYMD rl,rh - mcrr p4,#0,\rl,\rh,c1 -.endm -.macro WEFD rl,rh - mcrr p4,#0,\rl,\rh,c2 -.endm -.macro WXUP rl,rh - mcrr p4,#1,\rl,\rh,c0 -.endm -.macro WYUP rl,rh - mcrr p4,#1,\rl,\rh,c1 -.endm -.macro WXYU rl,rh - mcrr p4,#1,\rl,\rh,c2 -.endm -.macro WXMS rl,rh - mcrr p4,#2,\rl,\rh,c0 -.endm -.macro WXMO rl,rh - mcrr p4,#3,\rl,\rh,c0 -.endm -.macro WXDD rl,rh - mcrr p4,#4,\rl,\rh,c0 -.endm -.macro WXDQ rl,rh - mcrr p4,#5,\rl,\rh,c0 -.endm -.macro WXUC rl,rh - mcrr p4,#6,\rl,\rh,c0 -.endm -.macro WXIC rl,rh - mcrr p4,#7,\rl,\rh,c0 -.endm -.macro WXDC rl,rh - mcrr p4,#8,\rl,\rh,c0 -.endm -.macro WXFC rl,rh - mcrr p4,#9,\rl,\rh,c2 -.endm -.macro WXFM rl,rh - mcrr p4,#10,\rl,\rh,c0 -.endm -.macro WXFD rl,rh - mcrr p4,#11,\rl,\rh,c0 -.endm -.macro WXFQ rl,rh - mcrr p4,#12,\rl,\rh,c0 -.endm -.macro RXVD rt - mrc p4,#0,\rt,c0,c0,#0 -.endm -.macro RCMP rt - mrc p4,#0,\rt,c0,c0,#1 -.endm -.macro RDFA rt - mrc p4,#0,\rt,c0,c2,#0 -.endm -.macro RDFS rt - mrc p4,#0,\rt,c0,c2,#1 -.endm -.macro RDFM rt - mrc p4,#0,\rt,c0,c2,#2 -.endm -.macro RDFD rt - mrc p4,#0,\rt,c0,c2,#3 -.endm -.macro RDFQ rt - mrc p4,#0,\rt,c0,c2,#4 -.endm -.macro RDFG rt - mrc p4,#0,\rt,c0,c2,#5 -.endm -.macro RDIC rt - mrc p4,#0,\rt,c0,c3,#0 -.endm -.macro RDUC rt - mrc p4,#0,\rt,c0,c3,#1 -.endm -.macro RXMD rl,rh - mrrc p4,#0,\rl,\rh,c8 -.endm -.macro RYMD rl,rh - mrrc p4,#0,\rl,\rh,c9 -.endm -.macro REFD rl,rh - mrrc p4,#0,\rl,\rh,c10 -.endm -.macro RXMS rl,rh,s - mrrc p4,#\s,\rl,\rh,c4 -.endm -.macro RYMS rl,rh,s - mrrc p4,#\s,\rl,\rh,c5 -.endm -.macro RXYH rl,rh - mrrc p4,#1,\rl,\rh,c1 -.endm -.macro RYMR rl,rh - mrrc p4,#2,\rl,\rh,c1 -.endm -.macro RXMQ rl,rh - mrrc p4,#4,\rl,\rh,c1 -.endm -.macro RDDA rl,rh - mrrc p4,#1,\rl,\rh,c0 -.endm -.macro RDDS rl,rh - mrrc p4,#3,\rl,\rh,c0 -.endm -.macro RDDM rl,rh - mrrc p4,#5,\rl,\rh,c0 -.endm -.macro RDDD rl,rh - mrrc p4,#7,\rl,\rh,c0 -.endm -.macro RDDQ rl,rh - mrrc p4,#9,\rl,\rh,c0 -.endm -.macro RDDG rl,rh - mrrc p4,#11,\rl,\rh,c0 -.endm -.macro PXVD rt - mrc2 p4,#0,\rt,c0,c0,#0 -.endm -.macro PCMP rt - mrc2 p4,#0,\rt,c0,c0,#1 -.endm -.macro PDFA rt - mrc2 p4,#0,\rt,c0,c2,#0 -.endm -.macro PDFS rt - mrc2 p4,#0,\rt,c0,c2,#1 -.endm -.macro PDFM rt - mrc2 p4,#0,\rt,c0,c2,#2 -.endm -.macro PDFD rt - mrc2 p4,#0,\rt,c0,c2,#3 -.endm -.macro PDFQ rt - mrc2 p4,#0,\rt,c0,c2,#4 -.endm -.macro PDFG rt - mrc2 p4,#0,\rt,c0,c2,#5 -.endm -.macro PDIC rt - mrc2 p4,#0,\rt,c0,c3,#0 -.endm -.macro PDUC rt - mrc2 p4,#0,\rt,c0,c3,#1 -.endm -.macro PXMD rl,rh - mrrc2 p4,#0,\rl,\rh,c8 -.endm -.macro PYMD rl,rh - mrrc2 p4,#0,\rl,\rh,c9 -.endm -.macro PEFD rl,rh - mrrc2 p4,#0,\rl,\rh,c10 -.endm -.macro PXMS rl,rh,s - mrrc2 p4,#\s,\rl,\rh,c4 -.endm -.macro PYMS rl,rh,s - mrrc2 p4,#\s,\rl,\rh,c5 -.endm -.macro PXYH rl,rh - mrrc2 p4,#1,\rl,\rh,c1 -.endm -.macro PYMR rl,rh - mrrc2 p4,#2,\rl,\rh,c1 -.endm -.macro PXMQ rl,rh - mrrc2 p4,#4,\rl,\rh,c1 -.endm -.macro PDDA rl,rh - mrrc2 p4,#1,\rl,\rh,c0 -.endm -.macro PDDS rl,rh - mrrc2 p4,#3,\rl,\rh,c0 -.endm -.macro PDDM rl,rh - mrrc2 p4,#5,\rl,\rh,c0 -.endm -.macro PDDD rl,rh - mrrc2 p4,#7,\rl,\rh,c0 -.endm -.macro PDDQ rl,rh - mrrc2 p4,#9,\rl,\rh,c0 -.endm -.macro PDDG rl,rh - mrrc2 p4,#11,\rl,\rh,c0 -.endm - diff --git a/lib/main/pico-sdk/rp2_common/hardware_divider/divider.S b/lib/main/pico-sdk/rp2_common/hardware_divider/divider.S deleted file mode 100644 index 1292331926..0000000000 --- a/lib/main/pico-sdk/rp2_common/hardware_divider/divider.S +++ /dev/null @@ -1,59 +0,0 @@ -#include "pico/asm_helper.S" -#include "hardware/regs/addressmap.h" -#include "hardware/regs/sio.h" - -#if !PICO_RP2040 -#warning "Building hardware/divider.S on a platform with no SIO divider hardware" -#endif - -pico_default_asm_setup - -// tag::hw_div_s32[] -regular_func_with_section hw_divider_divmod_s32 - ldr r3, =(SIO_BASE) - str r0, [r3, #SIO_DIV_SDIVIDEND_OFFSET] - str r1, [r3, #SIO_DIV_SDIVISOR_OFFSET] - b hw_divider_divmod_return -// end::hw_div_s32[] - -// tag::hw_div_u32[] -regular_func_with_section hw_divider_divmod_u32 - ldr r3, =(SIO_BASE) - str r0, [r3, #SIO_DIV_UDIVIDEND_OFFSET] - str r1, [r3, #SIO_DIV_UDIVISOR_OFFSET] - b hw_divider_divmod_return -// end::hw_div_u32[] - -// Common delay and return section for s32 and u32 -.section .text.hw_divider_divmod_return -hw_divider_divmod_return: - // Branching here is 2 cycles, delay another 6 - b 1f -1: b 1f -1: b 1f -1: // return 64 bit value so we can efficiently return both (note quotient must be read last) - ldr r1, [r3, #SIO_DIV_REMAINDER_OFFSET] - ldr r0, [r3, #SIO_DIV_QUOTIENT_OFFSET] - bx lr - -regular_func_with_section hw_divider_save_state - ldr r3, =SIO_BASE - ldr r1, [r3, #SIO_DIV_UDIVIDEND_OFFSET] - ldr r2, [r3, #SIO_DIV_UDIVISOR_OFFSET] - stmia r0!, {r1-r2} - // The 8 cycles needed to guarantee that the result is ready is ensured by the preceding - // code of 7 cycles together with any branch to it taking at least 2 cycles. - ldr r1, [r3, #SIO_DIV_REMAINDER_OFFSET] - ldr r2, [r3, #SIO_DIV_QUOTIENT_OFFSET] - stmia r0!, {r1-r2} - bx lr - -regular_func_with_section hw_divider_restore_state - ldr r3, =SIO_BASE - ldmia r0!, {r1-r2} - str r1, [r3, #SIO_DIV_UDIVIDEND_OFFSET] - str r2, [r3, #SIO_DIV_UDIVISOR_OFFSET] - ldmia r0!, {r1-r2} - str r1, [r3, #SIO_DIV_REMAINDER_OFFSET] - str r2, [r3, #SIO_DIV_QUOTIENT_OFFSET] - bx lr diff --git a/lib/main/pico-sdk/rp2_common/hardware_divider/divider.c b/lib/main/pico-sdk/rp2_common/hardware_divider/divider.c deleted file mode 100644 index fc444eee8b..0000000000 --- a/lib/main/pico-sdk/rp2_common/hardware_divider/divider.c +++ /dev/null @@ -1,11 +0,0 @@ -/* - * Copyright (c) 2023 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "hardware/divider.h" - -#if PICO_EMULATE_DIVIDER -divmod_result_t hw_divider_results[NUM_CORES]; -#endif \ No newline at end of file diff --git a/lib/main/pico-sdk/rp2_common/hardware_divider/include/hardware/divider.h b/lib/main/pico-sdk/rp2_common/hardware_divider/include/hardware/divider.h deleted file mode 100644 index de8772dfd2..0000000000 --- a/lib/main/pico-sdk/rp2_common/hardware_divider/include/hardware/divider.h +++ /dev/null @@ -1,515 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _HARDWARE_DIVIDER_H -#define _HARDWARE_DIVIDER_H - -#include "pico.h" - -/** \file hardware/divider.h - * \defgroup hardware_divider hardware_divider - * - * \brief RP2040 Low Low-level hardware-divider API. Non-RP2040 platforms provide software versions of all the functions - * - * The SIO contains an 8-cycle signed/unsigned divide/modulo circuit, per core. Calculation is started by writing a dividend - * and divisor to the two argument registers, DIVIDEND and DIVISOR. The divider calculates the quotient / and remainder % of - * this division over the next 8 cycles, and on the 9th cycle the results can be read from the two result registers - * DIV_QUOTIENT and DIV_REMAINDER. A 'ready' bit in register DIV_CSR can be polled to wait for the calculation to - * complete, or software can insert a fixed 8-cycle delay - * - * This header provides low level macros and inline functions for accessing the hardware dividers directly, - * and perhaps most usefully performing asynchronous divides. These functions however do not follow the regular - * SDK conventions for saving/restoring the divider state, so are not generally safe to call from interrupt handlers - * - * The pico_divider library provides a more user friendly set of APIs over the divider (and support for - * 64 bit divides), and of course by default regular C language integer divisions are redirected through that library, meaning - * you can just use C level `/` and `%` operators and gain the benefits of the fast hardware divider. - * - * \if rp2350_specific - * On RP2350 there is no hardware divider, and the functions are implemented in software - * \endif - * - * @see pico_divider - * - * \subsection divider_example Example - * \addtogroup hardware_divider - * \include hello_divider.c - */ - -#if HAS_SIO_DIVIDER -#include "hardware/structs/sio.h" -#else -#define PICO_EMULATE_DIVIDER 1 -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -typedef uint64_t divmod_result_t; - -#if PICO_EMULATE_DIVIDER -extern divmod_result_t hw_divider_results[NUM_CORES]; - -static inline int __sign_of(int32_t v) { - return v > 0 ? 1 : (v < 0 ? -1 : 0); -} -#endif - -/*! \brief Do a signed HW divide and wait for result - * \ingroup hardware_divider - * - * Divide \p a by \p b, wait for calculation to complete, return result as a pair of 32-bit quotient/remainder values. - * - * \param a The dividend - * \param b The divisor - * \return Results of divide as a pair of 32-bit quotient/remainder values. - */ -#if !PICO_EMULATE_DIVIDER -divmod_result_t hw_divider_divmod_s32(int32_t a, int32_t b); -#else -static inline divmod_result_t hw_divider_divmod_s32(int32_t a, int32_t b) { - if (!b) return (((uint64_t)a)<<32u) | (uint32_t)(-__sign_of(a)); - return (((uint64_t)(a%b))<<32u) | (uint32_t)(a/b); -} -#endif - -/*! \brief Do an unsigned HW divide and wait for result - * \ingroup hardware_divider - * - * Divide \p a by \p b, wait for calculation to complete, return result as a pair of 32-bit quotient/remainder values. - * - * \param a The dividend - * \param b The divisor - * \return Results of divide as a pair of 32-bit quotient/remainder values. - */ -#if !PICO_EMULATE_DIVIDER -divmod_result_t hw_divider_divmod_u32(uint32_t a, uint32_t b); -#else -static inline divmod_result_t hw_divider_divmod_u32(uint32_t a, uint32_t b) { - if (!b) return (((uint64_t)a)<<32u) | (uint32_t)(-1); // todo check this - return (((uint64_t)(a%b))<<32u) | (a/b); -} -#endif - -/*! \brief Start a signed asynchronous divide - * \ingroup hardware_divider - * - * Start a divide of the specified signed parameters. You should wait for 8 cycles (__div_pause()) or wait for the ready bit to be set - * (hw_divider_wait_ready()) prior to reading the results. - * - * \param a The dividend - * \param b The divisor - */ -static inline void hw_divider_divmod_s32_start(int32_t a, int32_t b) { -#if !PICO_EMULATE_DIVIDER - check_hw_layout( sio_hw_t, div_sdividend, SIO_DIV_SDIVIDEND_OFFSET); - sio_hw->div_sdividend = (uint32_t)a; - sio_hw->div_sdivisor = (uint32_t)b; -#else - hw_divider_divmod_s32(a, b); -#endif -} - -/*! \brief Start an unsigned asynchronous divide - * \ingroup hardware_divider - * - * Start a divide of the specified unsigned parameters. You should wait for 8 cycles (__div_pause()) or wait for the ready bit to be set - * (hw_divider_wait_ready()) prior to reading the results. - * - * \param a The dividend - * \param b The divisor - */ -static inline void hw_divider_divmod_u32_start(uint32_t a, uint32_t b) { -#if !PICO_EMULATE_DIVIDER - check_hw_layout( - sio_hw_t, div_udividend, SIO_DIV_UDIVIDEND_OFFSET); - sio_hw->div_udividend = a; - sio_hw->div_udivisor = b; -#else - hw_divider_divmod_u32(a, b); -#endif -} - -/*! \brief Wait for a divide to complete - * \ingroup hardware_divider - * - * Wait for a divide to complete - */ -static inline void hw_divider_wait_ready(void) { -#if !PICO_EMULATE_DIVIDER - // this is #1 in lsr below - static_assert(SIO_DIV_CSR_READY_BITS == 1, ""); - - // we use one less register and instruction than gcc which uses a TST instruction - - uint32_t tmp; // allow compiler to pick scratch register - pico_default_asm_volatile ( - "hw_divider_result_loop_%=:" - "ldr %0, [%1, %2]\n\t" - "lsrs %0, %0, #1\n\t" - "bcc hw_divider_result_loop_%=\n\t" - : "=&l" (tmp) - : "l" (sio_hw), "I" (SIO_DIV_CSR_OFFSET) - : "cc" - ); -#endif -} - -/*! \brief Return result of HW divide, nowait - * \ingroup hardware_divider - * - * \note This is UNSAFE in that the calculation may not have been completed. - * - * \return Current result. Most significant 32 bits are the remainder, lower 32 bits are the quotient. - */ -static inline divmod_result_t hw_divider_result_nowait(void) { -#if !PICO_EMULATE_DIVIDER - // as ugly as this looks it is actually quite efficient - divmod_result_t rc = ((divmod_result_t) sio_hw->div_remainder) << 32u; - rc |= sio_hw->div_quotient; - return rc; -#else - return hw_divider_results[get_core_num()]; -#endif -} - -/*! \brief Return result of last asynchronous HW divide - * \ingroup hardware_divider - * - * This function waits for the result to be ready by calling hw_divider_wait_ready(). - * - * \return Current result. Most significant 32 bits are the remainder, lower 32 bits are the quotient. - */ -static inline divmod_result_t hw_divider_result_wait(void) { - hw_divider_wait_ready(); - return hw_divider_result_nowait(); -} - -/*! \brief Efficient extraction of unsigned quotient from 32p32 fixed point - * \ingroup hardware_divider - * - * \param r A pair of 32-bit quotient/remainder values. - * \return Unsigned quotient - */ -inline static uint32_t to_quotient_u32(divmod_result_t r) { - return (uint32_t) r; -} - -/*! \brief Efficient extraction of signed quotient from 32p32 fixed point - * \ingroup hardware_divider - * - * \param r A pair of 32-bit quotient/remainder values. - * \return Unsigned quotient - */ -inline static int32_t to_quotient_s32(divmod_result_t r) { - return (int32_t)(uint32_t)r; -} - -/*! \brief Efficient extraction of unsigned remainder from 32p32 fixed point - * \ingroup hardware_divider - * - * \param r A pair of 32-bit quotient/remainder values. - * \return Unsigned remainder - * - * \note On Arm this is just a 32 bit register move or a nop - */ -inline static uint32_t to_remainder_u32(divmod_result_t r) { - return (uint32_t)(r >> 32u); -} - -/*! \brief Efficient extraction of signed remainder from 32p32 fixed point - * \ingroup hardware_divider - * - * \param r A pair of 32-bit quotient/remainder values. - * \return Signed remainder - * - * \note On arm this is just a 32 bit register move or a nop - */ -inline static int32_t to_remainder_s32(divmod_result_t r) { - return (int32_t)(r >> 32u); -} - - -/*! \brief Return result of last asynchronous HW divide, unsigned quotient only - * \ingroup hardware_divider - * - * This function waits for the result to be ready by calling hw_divider_wait_ready(). - * - * \return Current unsigned quotient result. - */ -static inline uint32_t hw_divider_u32_quotient_wait(void) { -#if !PICO_EMULATE_DIVIDER - hw_divider_wait_ready(); - return sio_hw->div_quotient; -#else - return to_quotient_u32(hw_divider_result_wait()); -#endif -} - -/*! \brief Return result of last asynchronous HW divide, signed quotient only - * \ingroup hardware_divider - * - * This function waits for the result to be ready by calling hw_divider_wait_ready(). - * - * \return Current signed quotient result. - */ -static inline int32_t hw_divider_s32_quotient_wait(void) { -#if !PICO_EMULATE_DIVIDER - hw_divider_wait_ready(); - return (int32_t)sio_hw->div_quotient; -#else - return to_quotient_s32(hw_divider_result_wait()); -#endif -} - -/*! \brief Return result of last asynchronous HW divide, unsigned remainder only - * \ingroup hardware_divider - * - * This function waits for the result to be ready by calling hw_divider_wait_ready(). - * - * \return Current unsigned remainder result. - */ -static inline uint32_t hw_divider_u32_remainder_wait(void) { -#if !PICO_EMULATE_DIVIDER - hw_divider_wait_ready(); - uint32_t rc = sio_hw->div_remainder; - sio_hw->div_quotient; // must read quotient to cooperate with other SDK code - return rc; -#else - return to_remainder_u32(hw_divider_result_wait()); -#endif -} - -/*! \brief Return result of last asynchronous HW divide, signed remainder only - * \ingroup hardware_divider - * - * This function waits for the result to be ready by calling hw_divider_wait_ready(). - * - * \return Current remainder results. - */ -static inline int32_t hw_divider_s32_remainder_wait(void) { -#if !PICO_EMULATE_DIVIDER - hw_divider_wait_ready(); - int32_t rc = (int32_t)sio_hw->div_remainder; - sio_hw->div_quotient; // must read quotient to cooperate with other SDK code - return rc; -#else - return to_remainder_s32(hw_divider_result_wait()); -#endif -} - -/*! \brief Do an unsigned HW divide, wait for result, return quotient - * \ingroup hardware_divider - * - * Divide \p a by \p b, wait for calculation to complete, return quotient. - * - * \param a The dividend - * \param b The divisor - * \return Quotient results of the divide - */ -static inline uint32_t hw_divider_u32_quotient(uint32_t a, uint32_t b) { -#if !PICO_EMULATE_DIVIDER - return to_quotient_u32(hw_divider_divmod_u32(a, b)); -#else - return b ? (a / b) : (uint32_t)(-1); -#endif -} - -/*! \brief Do an unsigned HW divide, wait for result, return remainder - * \ingroup hardware_divider - * - * Divide \p a by \p b, wait for calculation to complete, return remainder. - * - * \param a The dividend - * \param b The divisor - * \return Remainder results of the divide - */ -static inline uint32_t hw_divider_u32_remainder(uint32_t a, uint32_t b) { -#if !PICO_EMULATE_DIVIDER - return to_remainder_u32(hw_divider_divmod_u32(a, b)); -#else - return b ? (a % b) : a; -#endif -} - -/*! \brief Do a signed HW divide, wait for result, return quotient - * \ingroup hardware_divider - * - * Divide \p a by \p b, wait for calculation to complete, return quotient. - * - * \param a The dividend - * \param b The divisor - * \return Quotient results of the divide - */ -static inline int32_t hw_divider_quotient_s32(int32_t a, int32_t b) { -#if !PICO_EMULATE_DIVIDER - return to_quotient_s32(hw_divider_divmod_s32(a, b)); -#else - return b ? (a / b) : -1; -#endif -} - -/*! \brief Do a signed HW divide, wait for result, return remainder - * \ingroup hardware_divider - * - * Divide \p a by \p b, wait for calculation to complete, return remainder. - * - * \param a The dividend - * \param b The divisor - * \return Remainder results of the divide - */ -static inline int32_t hw_divider_remainder_s32(int32_t a, int32_t b) { -#if !PICO_EMULATE_DIVIDER - return to_remainder_s32(hw_divider_divmod_s32(a, b)); -#else - return b ? (a % b) : a; -#endif -} - -/*! \brief Pause for exact amount of time needed for a asynchronous divide to complete - * \ingroup hardware_divider - */ -static inline void hw_divider_pause(void) { -#if !PICO_EMULATE_DIVIDER - pico_default_asm_volatile( - "b _1_%=\n" - "_1_%=:\n" - "b _2_%=\n" - "_2_%=:\n" - "b _3_%=\n" - "_3_%=:\n" - "b _4_%=\n" - "_4_%=:\n" - :::); -#endif -} - -/*! \brief Do a hardware unsigned HW divide, wait for result, return quotient - * \ingroup hardware_divider - * - * Divide \p a by \p b, wait for calculation to complete, return quotient. - * - * \param a The dividend - * \param b The divisor - * \return Quotient result of the divide - */ -static inline uint32_t hw_divider_u32_quotient_inlined(uint32_t a, uint32_t b) { -#if !PICO_EMULATE_DIVIDER - hw_divider_divmod_u32_start(a, b); - hw_divider_pause(); - return sio_hw->div_quotient; -#else - return hw_divider_u32_quotient(a,b); -#endif -} - -/*! \brief Do a hardware unsigned HW divide, wait for result, return remainder - * \ingroup hardware_divider - * - * Divide \p a by \p b, wait for calculation to complete, return remainder. - * - * \param a The dividend - * \param b The divisor - * \return Remainder result of the divide - */ -static inline uint32_t hw_divider_u32_remainder_inlined(uint32_t a, uint32_t b) { -#if !PICO_EMULATE_DIVIDER - hw_divider_divmod_u32_start(a, b); - hw_divider_pause(); - uint32_t rc = sio_hw->div_remainder; - sio_hw->div_quotient; // must read quotient to cooperate with other SDK code - return rc; -#else - return hw_divider_u32_remainder(a,b); -#endif -} - -/*! \brief Do a hardware signed HW divide, wait for result, return quotient - * \ingroup hardware_divider - * - * Divide \p a by \p b, wait for calculation to complete, return quotient. - * - * \param a The dividend - * \param b The divisor - * \return Quotient result of the divide - */ -static inline int32_t hw_divider_s32_quotient_inlined(int32_t a, int32_t b) { -#if !PICO_EMULATE_DIVIDER - hw_divider_divmod_s32_start(a, b); - hw_divider_pause(); - return (int32_t)sio_hw->div_quotient; -#else - return hw_divider_quotient_s32(a,b); -#endif -} - -/*! \brief Do a hardware signed HW divide, wait for result, return remainder - * \ingroup hardware_divider - * - * Divide \p a by \p b, wait for calculation to complete, return remainder. - * - * \param a The dividend - * \param b The divisor - * \return Remainder result of the divide - */ -static inline int32_t hw_divider_s32_remainder_inlined(int32_t a, int32_t b) { -#if !PICO_EMULATE_DIVIDER - hw_divider_divmod_s32_start(a, b); - hw_divider_pause(); - int32_t rc = (int32_t)sio_hw->div_remainder; - sio_hw->div_quotient; // must read quotient to cooperate with other SDK code - return rc; -#else - return hw_divider_remainder_s32(a,b); -#endif -} - -#if !PICO_EMULATE_DIVIDER -typedef struct { - uint32_t values[4]; -} hw_divider_state_t; -#else -typedef uint64_t hw_divider_state_t; -#endif - -/*! \brief Save the calling cores hardware divider state - * \ingroup hardware_divider - * - * Copy the current core's hardware divider state into the provided structure. This method - * waits for the divider results to be stable, then copies them to memory. - * They can be restored via hw_divider_restore_state() - * - * \param dest the location to store the divider state - */ -#if !PICO_EMULATE_DIVIDER -void hw_divider_save_state(hw_divider_state_t *dest); -#else -static inline void hw_divider_save_state(hw_divider_state_t *dest) { - *dest = hw_divider_results[get_core_num()]; -} -#endif - -/*! \brief Load a saved hardware divider state into the current core's hardware divider - * \ingroup hardware_divider - * - * Copy the passed hardware divider state into the hardware divider. - * - * \param src the location to load the divider state from - */ -#if !PICO_EMULATE_DIVIDER -void hw_divider_restore_state(hw_divider_state_t *src); -#else -static inline void hw_divider_restore_state(hw_divider_state_t *src) { - hw_divider_results[get_core_num()] = *src; -} -#endif - -#ifdef __cplusplus -} -#endif - -#endif // _HARDWARE_DIVIDER_H diff --git a/lib/main/pico-sdk/rp2_common/hardware_divider/include/hardware/divider_helper.S b/lib/main/pico-sdk/rp2_common/hardware_divider/include/hardware/divider_helper.S deleted file mode 100644 index ff4ed919bd..0000000000 --- a/lib/main/pico-sdk/rp2_common/hardware_divider/include/hardware/divider_helper.S +++ /dev/null @@ -1,68 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -// Note this file is always included by another, so does not do pico_default_asm_setup -#include "hardware/regs/addressmap.h" -#include "hardware/regs/sio.h" - -#if SIO_DIV_CSR_READY_LSB == 0 -.equ SIO_DIV_CSR_READY_SHIFT_FOR_CARRY, 1 -#else -need to change SHIFT above -#endif -#if SIO_DIV_CSR_DIRTY_LSB == 1 -.equ SIO_DIV_CSR_DIRTY_SHIFT_FOR_CARRY, 2 -#else -need to change SHIFT above -#endif - -// SIO_BASE ptr in r2; pushes r4-r7, lr to stack -.macro save_div_state_and_lr -// originally we did this, however a) it uses r3, and b) the push and dividend/divisor -// readout takes 8 cycles, c) any IRQ which uses the divider will necessarily put the -// data back, which will immediately make it ready -// -// // ldr r3, [r2, #SIO_DIV_CSR_OFFSET] -// // // wait for results as we can't save signed-ness of operation -// // 1: -// // lsrs r3, #SIO_DIV_CSR_READY_SHIFT_FOR_CARRY -// // bcc 1b - -// 6 cycle push + 2 ldr ensures the 8 cycle delay before remainder and quotient are ready -push {r4, r5, r6, r7, lr} -// note we must read quotient last, and since it isn't the last reg, we'll not use ldmia! -ldr r4, [r2, #SIO_DIV_UDIVIDEND_OFFSET] -ldr r5, [r2, #SIO_DIV_UDIVISOR_OFFSET] -ldr r7, [r2, #SIO_DIV_REMAINDER_OFFSET] -ldr r6, [r2, #SIO_DIV_QUOTIENT_OFFSET] -.endm - -// restores divider state from r4-r7, then pops them and pc -.macro restore_div_state_and_return -// writing sdividend (r4), sdivisor (r5), quotient (r6), remainder (r7) in that order -// -// it is worth considering what happens if we are interrupted -// -// after writing r4: we are DIRTY and !READY -// ... interruptor using div will complete based on incorrect inputs, but dividend at least will be -// saved/restored correctly and we'll restore the rest ourselves -// after writing r4, r5: we are DIRTY and !READY -// ... interruptor using div will complete based on possibly wrongly signed inputs, but dividend, divisor -// at least will be saved/restored correctly and and we'll restore the rest ourselves -// after writing r4, r5, r6: we are DIRTY and READY -// ... interruptor using div will dividend, divisor, quotient registers as is (what we just restored ourselves), -// and we'll restore the remainder after the fact - -// note we are not use STM not because it can be restarted due to interrupt which is harmless, more because this is 1 cycle IO space -// and so 4 reads is cheaper (and we don't have to adjust r2) -// note also, that we must restore via UDIVI* rather than SDIVI* to prevent the quotient/remainder being negated on read based -// on the signs of the inputs -str r4, [r2, #SIO_DIV_UDIVIDEND_OFFSET] -str r5, [r2, #SIO_DIV_UDIVISOR_OFFSET] -str r7, [r2, #SIO_DIV_REMAINDER_OFFSET] -str r6, [r2, #SIO_DIV_QUOTIENT_OFFSET] -pop {r4, r5, r6, r7, pc} -.endm \ No newline at end of file diff --git a/lib/main/pico-sdk/rp2_common/hardware_dma/dma.c b/lib/main/pico-sdk/rp2_common/hardware_dma/dma.c deleted file mode 100644 index 5c405959f0..0000000000 --- a/lib/main/pico-sdk/rp2_common/hardware_dma/dma.c +++ /dev/null @@ -1,112 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include "hardware/dma.h" -#include "hardware/claim.h" - -#define DMA_CHAN_STRIDE (DMA_CH1_CTRL_TRIG_OFFSET - DMA_CH0_CTRL_TRIG_OFFSET) -check_hw_size(dma_channel_hw_t, DMA_CHAN_STRIDE); -check_hw_layout(dma_hw_t, abort, DMA_CHAN_ABORT_OFFSET); - -// sanity check -static_assert(offsetof(dma_hw_t, ch[0].ctrl_trig) == DMA_CH0_CTRL_TRIG_OFFSET, "hw mismatch"); -static_assert(offsetof(dma_hw_t, ch[1].ctrl_trig) == DMA_CH1_CTRL_TRIG_OFFSET, "hw mismatch"); - -static_assert(NUM_DMA_CHANNELS <= 16, ""); -static uint16_t _claimed; -static uint8_t _timer_claimed; - -void dma_channel_claim(uint channel) { - check_dma_channel_param(channel); - hw_claim_or_assert((uint8_t *) &_claimed, channel, "DMA channel %d is already claimed"); -} - -void dma_claim_mask(uint32_t mask) { - for(uint i = 0; mask; i++, mask >>= 1u) { - if (mask & 1u) dma_channel_claim(i); - } -} - -void dma_channel_unclaim(uint channel) { - check_dma_channel_param(channel); - hw_claim_clear((uint8_t *) &_claimed, channel); -} - -void dma_unclaim_mask(uint32_t mask) { - for(uint i = 0; mask; i++, mask >>= 1u) { - if (mask & 1u) dma_channel_unclaim(i); - } -} - -int dma_claim_unused_channel(bool required) { - return hw_claim_unused_from_range((uint8_t*)&_claimed, required, 0, NUM_DMA_CHANNELS-1, "No DMA channels are available"); -} - -bool dma_channel_is_claimed(uint channel) { - check_dma_channel_param(channel); - return hw_is_claimed((uint8_t *) &_claimed, channel); -} - -void dma_timer_claim(uint timer) { - check_dma_timer_param(timer); - hw_claim_or_assert(&_timer_claimed, timer, "DMA timer %d is already claimed"); -} - -void dma_timer_unclaim(uint timer) { - check_dma_timer_param(timer); - hw_claim_clear(&_timer_claimed, timer); -} - -int dma_claim_unused_timer(bool required) { - return hw_claim_unused_from_range(&_timer_claimed, required, 0, NUM_DMA_TIMERS-1, "No DMA timers are available"); -} - -bool dma_timer_is_claimed(uint timer) { - check_dma_timer_param(timer); - return hw_is_claimed(&_timer_claimed, timer); -} - -void dma_channel_cleanup(uint channel) { - check_dma_channel_param(channel); - // Disable CHAIN_TO, and disable channel, so that it ignores any further triggers - hw_write_masked( &dma_hw->ch[channel].al1_ctrl, (channel << DMA_CH0_CTRL_TRIG_CHAIN_TO_LSB) | (0u << DMA_CH0_CTRL_TRIG_EN_LSB), DMA_CH0_CTRL_TRIG_CHAIN_TO_BITS | DMA_CH0_CTRL_TRIG_EN_BITS ); - // disable IRQs first as abort can cause spurious IRQs - dma_channel_set_irq0_enabled(channel, false); - dma_channel_set_irq1_enabled(channel, false); - dma_channel_abort(channel); - // finally clear the IRQ status, which may have been set during abort - dma_hw->intr = 1u << channel; -} - -#ifndef NDEBUG - -void print_dma_ctrl(dma_channel_hw_t *channel) { - uint32_t ctrl = channel->ctrl_trig; - int rgsz = (ctrl & DMA_CH0_CTRL_TRIG_RING_SIZE_BITS) >> DMA_CH0_CTRL_TRIG_RING_SIZE_LSB; - printf("(%08x) ber %d rer %d wer %d busy %d trq %d cto %d rgsl %d rgsz %d inw %d inr %d sz %d hip %d en %d", - (uint) ctrl, - ctrl & DMA_CH0_CTRL_TRIG_AHB_ERROR_BITS ? 1 : 0, - ctrl & DMA_CH0_CTRL_TRIG_READ_ERROR_BITS ? 1 : 0, - ctrl & DMA_CH0_CTRL_TRIG_WRITE_ERROR_BITS ? 1 : 0, - ctrl & DMA_CH0_CTRL_TRIG_BUSY_BITS ? 1 : 0, - (int) ((ctrl & DMA_CH0_CTRL_TRIG_TREQ_SEL_BITS) >> DMA_CH0_CTRL_TRIG_TREQ_SEL_LSB), - (int) ((ctrl & DMA_CH0_CTRL_TRIG_CHAIN_TO_BITS) >> DMA_CH0_CTRL_TRIG_CHAIN_TO_LSB), - ctrl & DMA_CH0_CTRL_TRIG_RING_SEL_BITS ? 1 : 0, - rgsz ? (1 << rgsz) : 0, - ctrl & DMA_CH0_CTRL_TRIG_INCR_WRITE_BITS ? 1 : 0, - ctrl & DMA_CH0_CTRL_TRIG_INCR_READ_BITS ? 1 : 0, - 1 << ((ctrl & DMA_CH0_CTRL_TRIG_DATA_SIZE_BITS) >> DMA_CH0_CTRL_TRIG_DATA_SIZE_LSB), - ctrl & DMA_CH0_CTRL_TRIG_HIGH_PRIORITY_BITS ? 1 : 0, - ctrl & DMA_CH0_CTRL_TRIG_EN_BITS ? 1 : 0); -} -#endif - -#if PARAM_ASSERTIONS_ENABLED(HARDWARE_DMA) -void check_dma_channel_param_impl(uint __unused channel) { - valid_params_if(HARDWARE_DMA, channel < NUM_DMA_CHANNELS); -} -#endif diff --git a/lib/main/pico-sdk/rp2_common/hardware_dma/include/hardware/dma.h b/lib/main/pico-sdk/rp2_common/hardware_dma/include/hardware/dma.h deleted file mode 100644 index 8bb35ec1fd..0000000000 --- a/lib/main/pico-sdk/rp2_common/hardware_dma/include/hardware/dma.h +++ /dev/null @@ -1,948 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _HARDWARE_DMA_H -#define _HARDWARE_DMA_H - -#include "pico.h" -#include "hardware/structs/dma.h" -#include "hardware/regs/dreq.h" -#include "pico/assert.h" -#include "hardware/regs/intctrl.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** \file hardware/dma.h - * \defgroup hardware_dma hardware_dma - * - * \brief DMA Controller API - * - * The RP-series microcontroller Direct Memory Access (DMA) master performs bulk data transfers on a processor’s - * behalf. This leaves processors free to attend to other tasks, or enter low-power sleep states. The - * data throughput of the DMA is also significantly higher than one of RP-series microcontroller’s processors. - * - * The DMA can perform one read access and one write access, up to 32 bits in size, every clock cycle. - * There are 12 independent channels, which each supervise a sequence of bus transfers, usually in - * one of the following scenarios: - * - * * Memory to peripheral - * * Peripheral to memory - * * Memory to memory - */ - -// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_HARDWARE_DMA, Enable/disable hardware_dma assertions, type=bool, default=0, group=hardware_dma -#ifndef PARAM_ASSERTIONS_ENABLED_HARDWARE_DMA -#ifdef PARAM_ASSERTIONS_ENABLED_DMA // backwards compatibility with SDK < 2.0.0 -#define PARAM_ASSERTIONS_ENABLED_HARDWARE_DMA PARAM_ASSERTIONS_ENABLED_DMA -#else -#define PARAM_ASSERTIONS_ENABLED_HARDWARE_DMA 0 -#endif -#endif - -/** - * \def DMA_IRQ_NUM(n) - * \ingroup hardware_dma - * \hideinitializer - * \brief Returns the \ref irq_num_t for the nth DMA interrupt - * - * Note this macro is intended to resolve at compile time, and does no parameter checking - */ -#ifndef DMA_IRQ_NUM -#define DMA_IRQ_NUM(irq_index) (DMA_IRQ_0 + (irq_index)) -#endif - -static inline void check_dma_channel_param(__unused uint channel) { -#if PARAM_ASSERTIONS_ENABLED(HARDWARE_DMA) - // this method is used a lot by inline functions so avoid code bloat by deferring to function - extern void check_dma_channel_param_impl(uint channel); - check_dma_channel_param_impl(channel); -#endif -} - -static inline void check_dma_timer_param(__unused uint timer_num) { - valid_params_if(HARDWARE_DMA, timer_num < NUM_DMA_TIMERS); -} - -inline static dma_channel_hw_t *dma_channel_hw_addr(uint channel) { - check_dma_channel_param(channel); - return &dma_hw->ch[channel]; -} - -/*! \brief Mark a dma channel as used - * \ingroup hardware_dma - * - * Method for cooperative claiming of hardware. Will cause a panic if the channel - * is already claimed. Use of this method by libraries detects accidental - * configurations that would fail in unpredictable ways. - * - * \param channel the dma channel - */ -void dma_channel_claim(uint channel); - -/*! \brief Mark multiple dma channels as used - * \ingroup hardware_dma - * - * Method for cooperative claiming of hardware. Will cause a panic if any of the channels - * are already claimed. Use of this method by libraries detects accidental - * configurations that would fail in unpredictable ways. - * - * \param channel_mask Bitfield of all required channels to claim (bit 0 == channel 0, bit 1 == channel 1 etc) - */ -void dma_claim_mask(uint32_t channel_mask); - -/*! \brief Mark a dma channel as no longer used - * \ingroup hardware_dma - * - * \param channel the dma channel to release - */ -void dma_channel_unclaim(uint channel); - -/*! \brief Mark multiple dma channels as no longer used - * \ingroup hardware_dma - * - * \param channel_mask Bitfield of all channels to unclaim (bit 0 == channel 0, bit 1 == channel 1 etc) - */ -void dma_unclaim_mask(uint32_t channel_mask); - -/*! \brief Claim a free dma channel - * \ingroup hardware_dma - * - * \param required if true the function will panic if none are available - * \return the dma channel number or -1 if required was false, and none were free - */ -int dma_claim_unused_channel(bool required); - -/*! \brief Determine if a dma channel is claimed - * \ingroup hardware_dma - * - * \param channel the dma channel - * \return true if the channel is claimed, false otherwise - * \see dma_channel_claim - * \see dma_channel_claim_mask - */ -bool dma_channel_is_claimed(uint channel); - -/** \brief DMA channel configuration - * \defgroup channel_config channel_config - * \ingroup hardware_dma - * - * A DMA channel needs to be configured, these functions provide handy helpers to set up configuration - * structures. See \ref dma_channel_config - */ - -/*! \brief Enumeration of available DMA channel transfer sizes. - * \ingroup hardware_dma - * - * Names indicate the number of bits. - */ -enum dma_channel_transfer_size { - DMA_SIZE_8 = 0, ///< Byte transfer (8 bits) - DMA_SIZE_16 = 1, ///< Half word transfer (16 bits) - DMA_SIZE_32 = 2 ///< Word transfer (32 bits) -}; - -typedef struct { - uint32_t ctrl; -} dma_channel_config; - -/*! \brief Set DMA channel read increment in a channel configuration object - * \ingroup channel_config - * - * \param c Pointer to channel configuration object - * \param incr True to enable read address increments, if false, each read will be from the same address - * Usually disabled for peripheral to memory transfers - */ -static inline void channel_config_set_read_increment(dma_channel_config *c, bool incr) { - c->ctrl = incr ? (c->ctrl | DMA_CH0_CTRL_TRIG_INCR_READ_BITS) : (c->ctrl & ~DMA_CH0_CTRL_TRIG_INCR_READ_BITS); -} - -/*! \brief Set DMA channel write increment in a channel configuration object - * \ingroup channel_config - * - * \param c Pointer to channel configuration object - * \param incr True to enable write address increments, if false, each write will be to the same address - * Usually disabled for memory to peripheral transfers - */ -static inline void channel_config_set_write_increment(dma_channel_config *c, bool incr) { - c->ctrl = incr ? (c->ctrl | DMA_CH0_CTRL_TRIG_INCR_WRITE_BITS) : (c->ctrl & ~DMA_CH0_CTRL_TRIG_INCR_WRITE_BITS); -} - -/*! \brief Select a transfer request signal in a channel configuration object - * \ingroup channel_config - * - * The channel uses the transfer request signal to pace its data transfer rate. - * Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). - * 0x0 to 0x3a -> select DREQ n as TREQ - * 0x3b -> Select Timer 0 as TREQ - * 0x3c -> Select Timer 1 as TREQ - * 0x3d -> Select Timer 2 as TREQ (Optional) - * 0x3e -> Select Timer 3 as TREQ (Optional) - * 0x3f -> Permanent request, for unpaced transfers. - * - * \param c Pointer to channel configuration data - * \param dreq Source (see description) - */ -static inline void channel_config_set_dreq(dma_channel_config *c, uint dreq) { - assert(dreq <= DREQ_FORCE); - c->ctrl = (c->ctrl & ~DMA_CH0_CTRL_TRIG_TREQ_SEL_BITS) | (dreq << DMA_CH0_CTRL_TRIG_TREQ_SEL_LSB); -} - -/*! \brief Set DMA channel chain_to channel in a channel configuration object - * \ingroup channel_config - * - * When this channel completes, it will trigger the channel indicated by chain_to. Disable by - * setting chain_to to itself (the same channel) - * - * \param c Pointer to channel configuration object - * \param chain_to Channel to trigger when this channel completes. - */ -static inline void channel_config_set_chain_to(dma_channel_config *c, uint chain_to) { - assert(chain_to <= NUM_DMA_CHANNELS); - c->ctrl = (c->ctrl & ~DMA_CH0_CTRL_TRIG_CHAIN_TO_BITS) | (chain_to << DMA_CH0_CTRL_TRIG_CHAIN_TO_LSB); -} - -/*! \brief Set the size of each DMA bus transfer in a channel configuration object - * \ingroup channel_config - * - * Set the size of each bus transfer (byte/halfword/word). The read and write addresses - * advance by the specific amount (1/2/4 bytes) with each transfer. - * - * \param c Pointer to channel configuration object - * \param size See enum for possible values. - */ -static inline void channel_config_set_transfer_data_size(dma_channel_config *c, enum dma_channel_transfer_size size) { - assert(size == DMA_SIZE_8 || size == DMA_SIZE_16 || size == DMA_SIZE_32); - c->ctrl = (c->ctrl & ~DMA_CH0_CTRL_TRIG_DATA_SIZE_BITS) | (((uint)size) << DMA_CH0_CTRL_TRIG_DATA_SIZE_LSB); -} - -/*! \brief Set address wrapping parameters in a channel configuration object - * \ingroup channel_config - * - * Size of address wrap region. If 0, don’t wrap. For values n > 0, only the lower n bits of the address - * will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned - * ring buffers. - * Ring sizes between 2 and 32768 bytes are possible (size_bits from 1 - 15) - * - * 0x0 -> No wrapping. - * - * \param c Pointer to channel configuration object - * \param write True to apply to write addresses, false to apply to read addresses - * \param size_bits 0 to disable wrapping. Otherwise the size in bits of the changing part of the address. - * Effectively wraps the address on a (1 << size_bits) byte boundary. - */ -static inline void channel_config_set_ring(dma_channel_config *c, bool write, uint size_bits) { - assert(size_bits < 32); - c->ctrl = (c->ctrl & ~(DMA_CH0_CTRL_TRIG_RING_SIZE_BITS | DMA_CH0_CTRL_TRIG_RING_SEL_BITS)) | - (size_bits << DMA_CH0_CTRL_TRIG_RING_SIZE_LSB) | - (write ? DMA_CH0_CTRL_TRIG_RING_SEL_BITS : 0); -} - -/*! \brief Set DMA byte swapping config in a channel configuration object - * \ingroup channel_config - * - * No effect for byte data, for halfword data, the two bytes of each halfword are - * swapped. For word data, the four bytes of each word are swapped to reverse their order. - * - * \param c Pointer to channel configuration object - * \param bswap True to enable byte swapping - */ -static inline void channel_config_set_bswap(dma_channel_config *c, bool bswap) { - c->ctrl = bswap ? (c->ctrl | DMA_CH0_CTRL_TRIG_BSWAP_BITS) : (c->ctrl & ~DMA_CH0_CTRL_TRIG_BSWAP_BITS); -} - -/*! \brief Set IRQ quiet mode in a channel configuration object - * \ingroup channel_config - * - * In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, - * an IRQ is raised when NULL is written to a trigger register, indicating the end of a control - * block chain. - * - * \param c Pointer to channel configuration object - * \param irq_quiet True to enable quiet mode, false to disable. - */ -static inline void channel_config_set_irq_quiet(dma_channel_config *c, bool irq_quiet) { - c->ctrl = irq_quiet ? (c->ctrl | DMA_CH0_CTRL_TRIG_IRQ_QUIET_BITS) : (c->ctrl & ~DMA_CH0_CTRL_TRIG_IRQ_QUIET_BITS); -} - -/*! - * \brief Set the channel priority in a channel configuration object - * \ingroup channel_config - * - * When true, gives a channel preferential treatment in issue scheduling: in each scheduling round, - * all high priority channels are considered first, and then only a single low - * priority channel, before returning to the high priority channels. - * - * This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. - * If the DMA is not saturated then a low priority channel will see no loss of throughput. - * - * \param c Pointer to channel configuration object - * \param high_priority True to enable high priority - */ -static inline void channel_config_set_high_priority(dma_channel_config *c, bool high_priority) { - c->ctrl = high_priority ? (c->ctrl | DMA_CH0_CTRL_TRIG_HIGH_PRIORITY_BITS) : (c->ctrl & ~DMA_CH0_CTRL_TRIG_HIGH_PRIORITY_BITS); -} - -/*! - * \brief Enable/Disable the DMA channel in a channel configuration object - * \ingroup channel_config - * - * When false, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will - * remain high if already high) - * - * \param c Pointer to channel configuration object - * \param enable True to enable the DMA channel. When enabled, the channel will respond to triggering events, and start transferring data. - * - */ -static inline void channel_config_set_enable(dma_channel_config *c, bool enable) { - c->ctrl = enable ? (c->ctrl | DMA_CH0_CTRL_TRIG_EN_BITS) : (c->ctrl & ~DMA_CH0_CTRL_TRIG_EN_BITS); -} - -/*! \brief Enable access to channel by sniff hardware in a channel configuration object - * \ingroup channel_config - * - * Sniff HW must be enabled and have this channel selected. - * - * \param c Pointer to channel configuration object - * \param sniff_enable True to enable the Sniff HW access to this DMA channel. - */ -static inline void channel_config_set_sniff_enable(dma_channel_config *c, bool sniff_enable) { - c->ctrl = sniff_enable ? (c->ctrl | DMA_CH0_CTRL_TRIG_SNIFF_EN_BITS) : (c->ctrl & - ~DMA_CH0_CTRL_TRIG_SNIFF_EN_BITS); -} - -/*! \brief Get the default channel configuration for a given channel - * \ingroup channel_config - * - * Setting | Default - * --------|-------- - * Read Increment | true - * Write Increment | false - * DReq | DREQ_FORCE - * Chain to | self - * Data size | DMA_SIZE_32 - * Ring | write=false, size=0 (i.e. off) - * Byte Swap | false - * Quiet IRQs | false - * High Priority | false - * Channel Enable | true - * Sniff Enable | false - * - * \param channel DMA channel - * \return the default configuration which can then be modified. - */ -static inline dma_channel_config dma_channel_get_default_config(uint channel) { - dma_channel_config c = {0}; - channel_config_set_read_increment(&c, true); - channel_config_set_write_increment(&c, false); - channel_config_set_dreq(&c, DREQ_FORCE); - channel_config_set_chain_to(&c, channel); - channel_config_set_transfer_data_size(&c, DMA_SIZE_32); - channel_config_set_ring(&c, false, 0); - channel_config_set_bswap(&c, false); - channel_config_set_irq_quiet(&c, false); - channel_config_set_enable(&c, true); - channel_config_set_sniff_enable(&c, false); - channel_config_set_high_priority( &c, false); - return c; -} - -/*! \brief Get the current configuration for the specified channel. - * \ingroup channel_config - * - * \param channel DMA channel - * \return The current configuration as read from the HW register (not cached) - */ -static inline dma_channel_config dma_get_channel_config(uint channel) { - dma_channel_config c; - c.ctrl = dma_channel_hw_addr(channel)->ctrl_trig; - return c; -} - -/*! \brief Get the raw configuration register from a channel configuration - * \ingroup channel_config - * - * \param config Pointer to a config structure. - * \return Register content - */ -static inline uint32_t channel_config_get_ctrl_value(const dma_channel_config *config) { - return config->ctrl; -} - -/*! \brief Set a channel configuration - * \ingroup hardware_dma - * - * \param channel DMA channel - * \param config Pointer to a config structure with required configuration - * \param trigger True to trigger the transfer immediately - */ -static inline void dma_channel_set_config(uint channel, const dma_channel_config *config, bool trigger) { - // Don't use CTRL_TRIG since we don't want to start a transfer - if (!trigger) { - dma_channel_hw_addr(channel)->al1_ctrl = channel_config_get_ctrl_value(config); - } else { - dma_channel_hw_addr(channel)->ctrl_trig = channel_config_get_ctrl_value(config); - } -} - -/*! \brief Set the DMA initial read address. - * \ingroup hardware_dma - * - * \param channel DMA channel - * \param read_addr Initial read address of transfer. - * \param trigger True to start the transfer immediately - */ -static inline void dma_channel_set_read_addr(uint channel, const volatile void *read_addr, bool trigger) { - if (!trigger) { - dma_channel_hw_addr(channel)->read_addr = (uintptr_t) read_addr; - } else { - dma_channel_hw_addr(channel)->al3_read_addr_trig = (uintptr_t) read_addr; - } -} - -/*! \brief Set the DMA initial write address - * \ingroup hardware_dma - * - * \param channel DMA channel - * \param write_addr Initial write address of transfer. - * \param trigger True to start the transfer immediately - */ -static inline void dma_channel_set_write_addr(uint channel, volatile void *write_addr, bool trigger) { - if (!trigger) { - dma_channel_hw_addr(channel)->write_addr = (uintptr_t) write_addr; - } else { - dma_channel_hw_addr(channel)->al2_write_addr_trig = (uintptr_t) write_addr; - } -} - -/*! \brief Set the number of bus transfers the channel will do - * \ingroup hardware_dma - * - * \param channel DMA channel - * \param trans_count The number of transfers (not NOT bytes, see channel_config_set_transfer_data_size) - * \param trigger True to start the transfer immediately - */ -static inline void dma_channel_set_trans_count(uint channel, uint32_t trans_count, bool trigger) { - if (!trigger) { - dma_channel_hw_addr(channel)->transfer_count = trans_count; - } else { - dma_channel_hw_addr(channel)->al1_transfer_count_trig = trans_count; - } -} - -/*! \brief Configure all DMA parameters and optionally start transfer - * \ingroup hardware_dma - * - * \param channel DMA channel - * \param config Pointer to DMA config structure - * \param write_addr Initial write address - * \param read_addr Initial read address - * \param transfer_count Number of transfers to perform - * \param trigger True to start the transfer immediately - */ -static inline void dma_channel_configure(uint channel, const dma_channel_config *config, volatile void *write_addr, - const volatile void *read_addr, - uint transfer_count, bool trigger) { - dma_channel_set_read_addr(channel, read_addr, false); - dma_channel_set_write_addr(channel, write_addr, false); - dma_channel_set_trans_count(channel, transfer_count, false); - dma_channel_set_config(channel, config, trigger); -} - -/*! \brief Start a DMA transfer from a buffer immediately - * \ingroup hardware_dma - * - * \param channel DMA channel - * \param read_addr Sets the initial read address - * \param transfer_count Number of transfers to make. Not bytes, but the number of transfers of channel_config_set_transfer_data_size() to be sent. - */ -inline static void __attribute__((always_inline)) dma_channel_transfer_from_buffer_now(uint channel, - const volatile void *read_addr, - uint32_t transfer_count) { -// check_dma_channel_param(channel); - dma_channel_hw_t *hw = dma_channel_hw_addr(channel); - hw->read_addr = (uintptr_t) read_addr; - hw->al1_transfer_count_trig = transfer_count; -} - -/*! \brief Start a DMA transfer to a buffer immediately - * \ingroup hardware_dma - * - * \param channel DMA channel - * \param write_addr Sets the initial write address - * \param transfer_count Number of transfers to make. Not bytes, but the number of transfers of channel_config_set_transfer_data_size() to be sent. - */ -inline static void dma_channel_transfer_to_buffer_now(uint channel, volatile void *write_addr, uint32_t transfer_count) { - dma_channel_hw_t *hw = dma_channel_hw_addr(channel); - hw->write_addr = (uintptr_t) write_addr; - hw->al1_transfer_count_trig = transfer_count; -} - -/*! \brief Start one or more channels simultaneously - * \ingroup hardware_dma - * - * \param chan_mask Bitmask of all the channels requiring starting. Channel 0 = bit 0, channel 1 = bit 1 etc. - */ -static inline void dma_start_channel_mask(uint32_t chan_mask) { - valid_params_if(HARDWARE_DMA, chan_mask && chan_mask < (1u << NUM_DMA_CHANNELS)); - dma_hw->multi_channel_trigger = chan_mask; -} - -/*! \brief Start a single DMA channel - * \ingroup hardware_dma - * - * \param channel DMA channel - */ -static inline void dma_channel_start(uint channel) { - dma_start_channel_mask(1u << channel); -} - -/*! \brief Stop a DMA transfer - * \ingroup hardware_dma - * - * Function will only return once the DMA has stopped. - * - * \if rp2040_specific - * RP2040 only: Note that due to errata RP2040-E13, aborting a channel which has transfers - * in-flight (i.e. an individual read has taken place but the corresponding write has not), the ABORT - * status bit will clear prematurely, and subsequently the in-flight - * transfers will trigger a completion interrupt once they complete. - *\endif - * - * The effect of this is that you \em may see a spurious completion interrupt - * on the channel as a result of calling this method. - * - * The calling code should be sure to ignore a completion IRQ as a result of this method. This may - * not require any additional work, as aborting a channel which may be about to complete, when you have a completion - * IRQ handler registered, is inherently race-prone, and so code is likely needed to disambiguate the two occurrences. - * - * If that is not the case, but you do have a channel completion IRQ handler registered, you can simply - * disable/re-enable the IRQ around the call to this method as shown by this code fragment (using DMA IRQ0). - * - * \code - * // disable the channel on IRQ0 - * dma_channel_set_irq0_enabled(channel, false); - * // abort the channel - * dma_channel_abort(channel); - * // clear the spurious IRQ (if there was one) - * dma_channel_acknowledge_irq0(channel); - * // re-enable the channel on IRQ0 - * dma_channel_set_irq0_enabled(channel, true); - *\endcode - * - * \if rp2350_specific - * RP2350 only: Due to errata RP12350-E5 (see the RP2350 datasheet for further detail), it is necessary to clear the enable bit of - * the aborted channel and any chained channels prior to the abort to prevent re-triggering. - * \endif - * - * \param channel DMA channel - */ -static inline void dma_channel_abort(uint channel) { - check_dma_channel_param(channel); - dma_hw->abort = 1u << channel; - // Bit will go 0 once channel has reached safe state - // (i.e. any in-flight transfers have retired) - while (dma_hw->ch[channel].ctrl_trig & DMA_CH0_CTRL_TRIG_BUSY_BITS) tight_loop_contents(); -} - -/*! \brief Enable single DMA channel's interrupt via DMA_IRQ_0 - * \ingroup hardware_dma - * - * \param channel DMA channel - * \param enabled true to enable interrupt 0 on specified channel, false to disable. - */ -static inline void dma_channel_set_irq0_enabled(uint channel, bool enabled) { - check_dma_channel_param(channel); - check_hw_layout(dma_hw_t, inte0, DMA_INTE0_OFFSET); - if (enabled) - hw_set_bits(&dma_hw->inte0, 1u << channel); - else - hw_clear_bits(&dma_hw->inte0, 1u << channel); -} - -/*! \brief Enable multiple DMA channels' interrupts via DMA_IRQ_0 - * \ingroup hardware_dma - * - * \param channel_mask Bitmask of all the channels to enable/disable. Channel 0 = bit 0, channel 1 = bit 1 etc. - * \param enabled true to enable all the interrupts specified in the mask, false to disable all the interrupts specified in the mask. - */ -static inline void dma_set_irq0_channel_mask_enabled(uint32_t channel_mask, bool enabled) { - if (enabled) { - hw_set_bits(&dma_hw->inte0, channel_mask); - } else { - hw_clear_bits(&dma_hw->inte0, channel_mask); - } -} - -/*! \brief Enable single DMA channel's interrupt via DMA_IRQ_1 - * \ingroup hardware_dma - * - * \param channel DMA channel - * \param enabled true to enable interrupt 1 on specified channel, false to disable. - */ -static inline void dma_channel_set_irq1_enabled(uint channel, bool enabled) { - check_dma_channel_param(channel); - check_hw_layout(dma_hw_t, inte1, DMA_INTE1_OFFSET); - if (enabled) - hw_set_bits(&dma_hw->inte1, 1u << channel); - else - hw_clear_bits(&dma_hw->inte1, 1u << channel); -} - -/*! \brief Enable multiple DMA channels' interrupts via DMA_IRQ_1 - * \ingroup hardware_dma - * - * \param channel_mask Bitmask of all the channels to enable/disable. Channel 0 = bit 0, channel 1 = bit 1 etc. - * \param enabled true to enable all the interrupts specified in the mask, false to disable all the interrupts specified in the mask. - */ -static inline void dma_set_irq1_channel_mask_enabled(uint32_t channel_mask, bool enabled) { - if (enabled) { - hw_set_bits(&dma_hw->inte1, channel_mask); - } else { - hw_clear_bits(&dma_hw->inte1, channel_mask); - } -} - -/*! \brief Enable single DMA channel interrupt on either DMA_IRQ_0 or DMA_IRQ_1 - * \ingroup hardware_dma - * - * \param irq_index the IRQ index; either 0 or 1 for DMA_IRQ_0 or DMA_IRQ_1 - * \param channel DMA channel - * \param enabled true to enable interrupt via irq_index for specified channel, false to disable. - */ -static inline void dma_irqn_set_channel_enabled(uint irq_index, uint channel, bool enabled) { - invalid_params_if(HARDWARE_DMA, irq_index >= NUM_DMA_IRQS); - - if (enabled) - hw_set_bits(&dma_hw->irq_ctrl[irq_index].inte, 1u << channel); - else - hw_clear_bits(&dma_hw->irq_ctrl[irq_index].inte, 1u << channel); -} - -/*! \brief Enable multiple DMA channels' interrupt via either DMA_IRQ_0 or DMA_IRQ_1 - * \ingroup hardware_dma - * - * \param irq_index the IRQ index; either 0 or 1 for DMA_IRQ_0 or DMA_IRQ_1 - * \param channel_mask Bitmask of all the channels to enable/disable. Channel 0 = bit 0, channel 1 = bit 1 etc. - * \param enabled true to enable all the interrupts specified in the mask, false to disable all the interrupts specified in the mask. - */ -static inline void dma_irqn_set_channel_mask_enabled(uint irq_index, uint32_t channel_mask, bool enabled) { - invalid_params_if(HARDWARE_DMA, irq_index >= NUM_DMA_IRQS); - if (enabled) { - hw_set_bits(&dma_hw->irq_ctrl[irq_index].inte, channel_mask); - } else { - hw_clear_bits(&dma_hw->irq_ctrl[irq_index].inte, channel_mask); - } -} - -/*! \brief Determine if a particular channel is a cause of DMA_IRQ_0 - * \ingroup hardware_dma - * - * \param channel DMA channel - * \return true if the channel is a cause of DMA_IRQ_0, false otherwise - */ -static inline bool dma_channel_get_irq0_status(uint channel) { - check_dma_channel_param(channel); - return dma_hw->ints0 & (1u << channel); -} - -/*! \brief Determine if a particular channel is a cause of DMA_IRQ_1 - * \ingroup hardware_dma - * - * \param channel DMA channel - * \return true if the channel is a cause of DMA_IRQ_1, false otherwise - */ -static inline bool dma_channel_get_irq1_status(uint channel) { - check_dma_channel_param(channel); - return dma_hw->ints1 & (1u << channel); -} - -/*! \brief Determine if a particular channel is a cause of DMA_IRQ_N - * \ingroup hardware_dma - * - * \param irq_index the IRQ index; either 0 or 1 for DMA_IRQ_0 or DMA_IRQ_1 - * \param channel DMA channel - * \return true if the channel is a cause of the DMA_IRQ_N, false otherwise - */ -static inline bool dma_irqn_get_channel_status(uint irq_index, uint channel) { - invalid_params_if(HARDWARE_DMA, irq_index >= NUM_DMA_IRQS); - check_dma_channel_param(channel); - return dma_hw->irq_ctrl[irq_index].ints & (1u << channel); -} - -/*! \brief Acknowledge a channel IRQ, resetting it as the cause of DMA_IRQ_0 - * \ingroup hardware_dma - * - * \param channel DMA channel - */ -static inline void dma_channel_acknowledge_irq0(uint channel) { - check_dma_channel_param(channel); - dma_hw->ints0 = 1u << channel; -} - -/*! \brief Acknowledge a channel IRQ, resetting it as the cause of DMA_IRQ_1 - * \ingroup hardware_dma - * - * \param channel DMA channel - */ -static inline void dma_channel_acknowledge_irq1(uint channel) { - check_dma_channel_param(channel); - dma_hw->ints1 = 1u << channel; -} - -/*! \brief Acknowledge a channel IRQ, resetting it as the cause of DMA_IRQ_N - * \ingroup hardware_dma - * - * \param irq_index the IRQ index; either 0 or 1 for DMA_IRQ_0 or DMA_IRQ_1 - * \param channel DMA channel - */ -static inline void dma_irqn_acknowledge_channel(uint irq_index, uint channel) { - invalid_params_if(HARDWARE_DMA, irq_index >= NUM_DMA_IRQS); - check_dma_channel_param(channel); - dma_hw->irq_ctrl[irq_index].ints = 1u << channel; -} - -/*! \brief Check if DMA channel is busy - * \ingroup hardware_dma - * - * \param channel DMA channel - * \return true if the channel is currently busy - */ -inline static bool dma_channel_is_busy(uint channel) { - check_dma_channel_param(channel); - return dma_hw->ch[channel].al1_ctrl & DMA_CH0_CTRL_TRIG_BUSY_BITS; -} - -/*! \brief Wait for a DMA channel transfer to complete - * \ingroup hardware_dma - * - * \param channel DMA channel - */ -inline static void dma_channel_wait_for_finish_blocking(uint channel) { - while (dma_channel_is_busy(channel)) tight_loop_contents(); - // stop the compiler hoisting a non-volatile buffer access above the DMA completion. - __compiler_memory_barrier(); -} - -/*! \brief Enable the DMA sniffing targeting the specified channel - * \ingroup hardware_dma - * - * The mode can be one of the following: - * - * Mode | Function - * -----|--------- - * 0x0 | Calculate a CRC-32 (IEEE802.3 polynomial) - * 0x1 | Calculate a CRC-32 (IEEE802.3 polynomial) with bit reversed data - * 0x2 | Calculate a CRC-16-CCITT - * 0x3 | Calculate a CRC-16-CCITT with bit reversed data - * 0xe | XOR reduction over all data. == 1 if the total 1 population count is odd. - * 0xf | Calculate a simple 32-bit checksum (addition with a 32 bit accumulator) - * - * \param channel DMA channel - * \param mode See description - * \param force_channel_enable Set true to also turn on sniffing in the channel configuration (this - * is usually what you want, but sometimes you might have a chain DMA with only certain segments - * of the chain sniffed, in which case you might pass false). - */ -inline static void dma_sniffer_enable(uint channel, uint mode, bool force_channel_enable) { - check_dma_channel_param(channel); - check_hw_layout(dma_hw_t, sniff_ctrl, DMA_SNIFF_CTRL_OFFSET); - if (force_channel_enable) { - hw_set_bits(&dma_hw->ch[channel].al1_ctrl, DMA_CH0_CTRL_TRIG_SNIFF_EN_BITS); - } - hw_write_masked(&dma_hw->sniff_ctrl, - (((channel << DMA_SNIFF_CTRL_DMACH_LSB) & DMA_SNIFF_CTRL_DMACH_BITS) | - ((mode << DMA_SNIFF_CTRL_CALC_LSB) & DMA_SNIFF_CTRL_CALC_BITS) | - DMA_SNIFF_CTRL_EN_BITS), - (DMA_SNIFF_CTRL_DMACH_BITS | - DMA_SNIFF_CTRL_CALC_BITS | - DMA_SNIFF_CTRL_EN_BITS)); -} - -/*! \brief Enable the Sniffer byte swap function - * \ingroup hardware_dma - * - * Locally perform a byte reverse on the sniffed data, before feeding into checksum. - * - * Note that the sniff hardware is downstream of the DMA channel byteswap performed in the - * read master: if channel_config_set_bswap() and dma_sniffer_set_byte_swap_enabled() are both enabled, - * their effects cancel from the sniffer’s point of view. - * - * \param swap Set true to enable byte swapping - */ -inline static void dma_sniffer_set_byte_swap_enabled(bool swap) { - if (swap) - hw_set_bits(&dma_hw->sniff_ctrl, DMA_SNIFF_CTRL_BSWAP_BITS); - else - hw_clear_bits(&dma_hw->sniff_ctrl, DMA_SNIFF_CTRL_BSWAP_BITS); -} - -/*! \brief Enable the Sniffer output invert function - * \ingroup hardware_dma - * - * If enabled, the sniff data result appears bit-inverted when read. - * This does not affect the way the checksum is calculated. - * - * \param invert Set true to enable output bit inversion - */ -inline static void dma_sniffer_set_output_invert_enabled(bool invert) { - if (invert) - hw_set_bits(&dma_hw->sniff_ctrl, DMA_SNIFF_CTRL_OUT_INV_BITS); - else - hw_clear_bits(&dma_hw->sniff_ctrl, DMA_SNIFF_CTRL_OUT_INV_BITS); -} - -/*! \brief Enable the Sniffer output bit reversal function - * \ingroup hardware_dma - * - * If enabled, the sniff data result appears bit-reversed when read. - * This does not affect the way the checksum is calculated. - * - * \param reverse Set true to enable output bit reversal - */ -inline static void dma_sniffer_set_output_reverse_enabled(bool reverse) { - if (reverse) - hw_set_bits(&dma_hw->sniff_ctrl, DMA_SNIFF_CTRL_OUT_REV_BITS); - else - hw_clear_bits(&dma_hw->sniff_ctrl, DMA_SNIFF_CTRL_OUT_REV_BITS); -} - -/*! \brief Disable the DMA sniffer - * \ingroup hardware_dma - * - */ -inline static void dma_sniffer_disable(void) { - dma_hw->sniff_ctrl = 0; -} - -/*! \brief Set the sniffer's data accumulator with initial value - * \ingroup hardware_dma - * - * Generally, CRC algorithms are used with the data accumulator initially - * seeded with 0xFFFF or 0xFFFFFFFF (for crc16 and crc32 algorithms) - * - * \param seed_value value to set data accumulator - */ -inline static void dma_sniffer_set_data_accumulator(uint32_t seed_value) { - dma_hw->sniff_data = seed_value; -} - -/*! \brief Get the sniffer's data accumulator value - * \ingroup hardware_dma - * - * Read value calculated by the hardware from sniffing the DMA stream - */ -inline static uint32_t dma_sniffer_get_data_accumulator(void) { - return dma_hw->sniff_data; -} - -/*! \brief Mark a dma timer as used - * \ingroup hardware_dma - * - * Method for cooperative claiming of hardware. Will cause a panic if the timer - * is already claimed. Use of this method by libraries detects accidental - * configurations that would fail in unpredictable ways. - * - * \param timer the dma timer - */ -void dma_timer_claim(uint timer); - -/*! \brief Mark a dma timer as no longer used - * \ingroup hardware_dma - * - * Method for cooperative claiming of hardware. - * - * \param timer the dma timer to release - */ -void dma_timer_unclaim(uint timer); - -/*! \brief Claim a free dma timer - * \ingroup hardware_dma - * - * \param required if true the function will panic if none are available - * \return the dma timer number or -1 if required was false, and none were free - */ -int dma_claim_unused_timer(bool required); - -/*! \brief Determine if a dma timer is claimed - * \ingroup hardware_dma - * - * \param timer the dma timer - * \return true if the timer is claimed, false otherwise - * \see dma_timer_claim - */ -bool dma_timer_is_claimed(uint timer); - -/*! \brief Set the multiplier for the given DMA timer - * \ingroup hardware_dma - * - * The timer will run at the system_clock_freq * numerator / denominator, so this is the speed - * that data elements will be transferred at via a DMA channel using this timer as a DREQ. The - * multiplier must be less than or equal to one. - * - * \param timer the dma timer - * \param numerator the fraction's numerator - * \param denominator the fraction's denominator - */ -static inline void dma_timer_set_fraction(uint timer, uint16_t numerator, uint16_t denominator) { - check_dma_timer_param(timer); - invalid_params_if(HARDWARE_DMA, numerator > denominator); - dma_hw->timer[timer] = (((uint32_t)numerator) << DMA_TIMER0_X_LSB) | (((uint32_t)denominator) << DMA_TIMER0_Y_LSB); -} - -/*! \brief Return the DREQ number for a given DMA timer - * \ingroup hardware_dma - * - * \param timer_num DMA timer number 0-3 - */ -static inline uint dma_get_timer_dreq(uint timer_num) { - static_assert(DREQ_DMA_TIMER1 == DREQ_DMA_TIMER0 + 1, ""); - static_assert(DREQ_DMA_TIMER2 == DREQ_DMA_TIMER0 + 2, ""); - static_assert(DREQ_DMA_TIMER3 == DREQ_DMA_TIMER0 + 3, ""); - check_dma_timer_param(timer_num); - return DREQ_DMA_TIMER0 + timer_num; -} - -/*! \brief Return DMA_IRQ_ - * \ingroup hardware_dma - * - * \param irq_index 0 the DMA irq index - * \return The \ref irq_num_t to use for DMA - */ -static inline int dma_get_irq_num(uint irq_index) { - valid_params_if(HARDWARE_DMA, irq_index < NUM_DMA_IRQS); - return DMA_IRQ_NUM(irq_index); -} - -/*! \brief Performs DMA channel cleanup after use - * \ingroup hardware_dma - * - * This can be used to cleanup dma channels when they're no longer needed, such that they are in a clean state for reuse. - * IRQ's for the channel are disabled, any in flight-transfer is aborted and any outstanding interrupts are cleared. - * The channel is then clear to be reused for other purposes. - * - * \code - * if (dma_channel >= 0) { - * dma_channel_cleanup(dma_channel); - * dma_channel_unclaim(dma_channel); - * dma_channel = -1; - * } - * \endcode - * - * \param channel DMA channel - */ -void dma_channel_cleanup(uint channel); - -#ifndef NDEBUG -void print_dma_ctrl(dma_channel_hw_t *channel); -#endif - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/lib/main/pico-sdk/rp2_common/hardware_exception/exception.c b/lib/main/pico-sdk/rp2_common/hardware_exception/exception.c deleted file mode 100644 index d3134fbc85..0000000000 --- a/lib/main/pico-sdk/rp2_common/hardware_exception/exception.c +++ /dev/null @@ -1,105 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "hardware/exception.h" -#include "hardware/sync.h" -#include "pico/platform/cpu_regs.h" - -#ifndef exception_is_compile_time_default -static bool exception_is_compile_time_default(exception_handler_t handler) { -#ifdef __riscv - extern char __unhandled_exception; - return (uintptr_t)handler == (uintptr_t)__unhandled_exception; -#else - extern char __default_isrs_start; - extern char __default_isrs_end; - return ((uintptr_t)handler) >= (uintptr_t)&__default_isrs_start && - ((uintptr_t)handler) < (uintptr_t)&__default_isrs_end; -#endif -} -#endif - -static inline exception_handler_t *get_exception_table(void) { -#ifdef __riscv - extern uintptr_t __riscv_exception_table; - return (exception_handler_t *) &__riscv_exception_table; -#else - return (exception_handler_t *) scb_hw->vtor; -#endif -} - -static void set_raw_exception_handler_and_restore_interrupts(enum exception_number num, exception_handler_t handler, uint32_t save) { - // update vtable (vtable_handler may be same or updated depending on cases, but we do it anyway for compactness) - get_exception_table()[num] = handler; - __dmb(); - restore_interrupts_from_disabled(save); -} - -static inline void check_exception_param(__unused enum exception_number num) { - invalid_params_if(HARDWARE_EXCEPTION, num < MIN_EXCEPTION_NUM || num > MAX_EXCEPTION_NUM); -} - -exception_handler_t exception_get_vtable_handler(enum exception_number num) { - check_exception_param(num); - return get_exception_table()[num]; -} - -exception_handler_t exception_set_exclusive_handler(enum exception_number num, exception_handler_t handler) { - check_exception_param(num); -#if !PICO_NO_RAM_VECTOR_TABLE - uint32_t save = save_and_disable_interrupts(); - exception_handler_t current = exception_get_vtable_handler(num); - hard_assert(handler == current || exception_is_compile_time_default(current)); - set_raw_exception_handler_and_restore_interrupts(num, handler, save); -#else - panic_unsupported(); -#endif - return current; -} - -void exception_restore_handler(enum exception_number num, exception_handler_t original_handler) { - hard_assert(exception_is_compile_time_default(original_handler)); -#if !PICO_NO_RAM_VECTOR_TABLE - uint32_t save = save_and_disable_interrupts(); - set_raw_exception_handler_and_restore_interrupts(num, original_handler, save); -#else - panic_unsupported(); -#endif -} - -#ifndef __riscv - -static io_rw_32 *get_shpr0(uint num) { - io_rw_32 *shpr0 = NULL; -#if __ARM_ARCH_6M__ - // only has shpr2-3 - if (num >= 8 && num < 16) shpr0 = (io_rw_32 *) (PPB_BASE + ARM_CPU_PREFIXED(SHPR2_OFFSET) - 8); -#elif __ARM_ARCH_8M_MAIN__ - // only has shpr1-3 - if (num >= 4 && num < 16) shpr0 = (io_rw_32 *)(PPB_BASE + ARM_CPU_PREFIXED(SHPR1_OFFSET) - 4); -#endif - return shpr0; -} - -bool exception_set_priority(uint num, uint8_t hardware_priority) { - io_rw_32 *shpr0 = get_shpr0(num); - if (shpr0) { - // note that only 32 bit writes are supported - shpr0[num / 4] = (shpr0[num/4] & ~(0xffu << (8 * (num & 3u)))) | (((uint32_t) hardware_priority) << (8 * (num & 3u))); - return true; - } - return false; -} - -uint exception_get_priority(uint num) { - io_rw_32 *shpr0 = get_shpr0(num); - if (shpr0) { - // note that only 32 bit writes are supported - return (uint8_t) (shpr0[num/4] >> (8 * (num & 3))); - } - return PICO_LOWEST_EXCEPTION_PRIORITY; -} -#endif \ No newline at end of file diff --git a/lib/main/pico-sdk/rp2_common/hardware_exception/exception_table_riscv.S b/lib/main/pico-sdk/rp2_common/hardware_exception/exception_table_riscv.S deleted file mode 100644 index 1bd24c910f..0000000000 --- a/lib/main/pico-sdk/rp2_common/hardware_exception/exception_table_riscv.S +++ /dev/null @@ -1,135 +0,0 @@ -#include "pico/asm_helper.S" - -// Support for breaking out individual RISC-V exception causes to handlers -// implemented as normal C functions. Note the handler is still responsible -// for incrementing `mepc` before return, if it intends to return to the -// instruction after the one that caused the exception. - -.macro decl_isr name -.weak \name -\name: -.endm - -// must be in RAM due to branches from vector table -.section .time_critical.hardware_exception - -.p2align 2 -.global __riscv_exception_table -__riscv_exception_table: -.word isr_riscv_machine_instr_align_exception -.word isr_riscv_machine_instr_fault_exception -.word isr_riscv_machine_instr_illegal_exception -.word isr_riscv_machine_ebreak_exception -.word isr_riscv_machine_load_align_exception -.word isr_riscv_machine_load_fault_exception -.word isr_riscv_machine_store_align_exception -.word isr_riscv_machine_store_fault_exception -.word isr_riscv_machine_ecall_umode_exception -.word isr_riscv_machine_ecall_smode_exception -.word __unhandled_exception // reserved -.word isr_riscv_machine_ecall_mmode_exception - -// mscratch = 0 outside of exception handler. mscratch = user ra during -// exception handler. Assume 0 is not a valid ra. -.global isr_riscv_machine_exception -// still allow override just in case hardware_exception is pulled in by a library -// note: that when LIX_HARDWARE_EXCEPTION=1, crt0_riscv.S does not define its own weak method -.weak isr_riscv_machine_exception -isr_riscv_machine_exception: - csrrw ra, mscratch, ra - bnez ra, __nested_exception - // Exception handler runs on foreground stack: this may fault, but we will - // catch the fault and go to __nested_exception. - addi sp, sp, -64 - // Work downward, to ensure that after tripping a stack guard PMP region - // we re-trip it before trashing memory below the guard. - sw t6, 60(sp) - sw t5, 56(sp) - sw t4, 52(sp) - sw t3, 48(sp) - sw a7, 44(sp) - sw a6, 40(sp) - sw a5, 36(sp) - sw a4, 32(sp) - sw a3, 28(sp) - sw a2, 24(sp) - sw a1, 20(sp) - sw a0, 16(sp) - sw t2, 12(sp) - sw t1, 8(sp) - sw t0, 4(sp) - // ra already saved - - // Using unsigned comparison for double-ended bounds check - csrr ra, mcause - li t6, 11 // XCAUSE_ECALL_M - bltu t6, ra, __unhandled_exception - - // Enter exception through table - la t6, __riscv_exception_table - sh2add ra, ra, t6 - lw ra, (ra) - jalr ra, ra - - // Restore saved registers - lw t6, 60(sp) - lw t5, 56(sp) - lw t4, 52(sp) - lw t3, 48(sp) - lw a7, 44(sp) - lw a6, 40(sp) - lw a5, 36(sp) - lw a4, 32(sp) - lw a3, 28(sp) - lw a2, 24(sp) - lw a1, 20(sp) - lw a0, 16(sp) - lw t2, 12(sp) - lw t1, 8(sp) - lw t0, 4(sp) - // ra restored from mscratch - addi sp, sp, 64 - - // Restore mscratch to 0 to avoid tripping next exception - csrrw ra, mscratch, zero - mret - -decl_isr isr_riscv_machine_instr_align_exception -decl_isr isr_riscv_machine_instr_fault_exception -decl_isr isr_riscv_machine_instr_illegal_exception -decl_isr isr_riscv_machine_ebreak_exception -decl_isr isr_riscv_machine_load_align_exception -decl_isr isr_riscv_machine_load_fault_exception -decl_isr isr_riscv_machine_store_align_exception -decl_isr isr_riscv_machine_store_fault_exception -decl_isr isr_riscv_machine_ecall_umode_exception -decl_isr isr_riscv_machine_ecall_smode_exception -decl_isr isr_riscv_machine_ecall_mmode_exception - // fall through - -// Reach here when executing an exception that did not have a non-default -// handler assigned. Since a breakpoint will cause another exception if the -// debugger is not connected, we can't have an ebreak here. Just spin the -// core forever. You can check `mcause` and `mepc` to see what happened and -// where. -.global __unhandled_exception -__unhandled_exception: - // Restore original registers and stack pointer so debugger can backtrace - csrr ra, mscratch - lw t6, 60(sp) - addi sp, sp, -64 - // Second symbol here just to make it clearer in the debugger why you got - // here; the entry point can appear labelled with the name of any one of the - // unhandled exceptions, which is less clear. -.global __halt_on_unhandled_exception -__halt_on_unhandled_exception: -1: - j 1b - -// Detected an exception occurring whilst running an exception handler. State -// of original exception was trashed by new exception, so this is not -// recoverable. Best we can do is to halt now to avoid further trashing. -__nested_exception: -1: - j 1b - diff --git a/lib/main/pico-sdk/rp2_common/hardware_exception/include/hardware/exception.h b/lib/main/pico-sdk/rp2_common/hardware_exception/include/hardware/exception.h deleted file mode 100644 index 377ec01566..0000000000 --- a/lib/main/pico-sdk/rp2_common/hardware_exception/include/hardware/exception.h +++ /dev/null @@ -1,194 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _HARDWARE_EXCEPTION_H -#define _HARDWARE_EXCEPTION_H - -#include "pico.h" -#include "hardware/address_mapped.h" - -/** \file exception.h - * \defgroup hardware_exception hardware_exception - * - * \brief Methods for setting processor exception handlers - * - * Exceptions are identified by a \ref exception_number which is a number from -15 to -1; these are the numbers relative to - * the index of the first IRQ vector in the vector table. (i.e. vector table index is exception_num plus 16) - * - * There is one set of exception handlers per core, so the exception handlers for each core as set by these methods are independent. - * - * \note That all exception APIs affect the executing core only (i.e. the core calling the function). - */ - -// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_HARDWARE_EXCEPTION, Enable/disable assertions in the hardware_exception module, type=bool, default=0, group=hardware_exception -#ifndef PARAM_ASSERTIONS_ENABLED_HARDWARE_EXCEPTION -#ifdef PARAM_ASSERTIONS_ENABLED_EXCEPTION // backwards compatibility with SDK < 2.0.0 -#define PARAM_ASSERTIONS_ENABLED_HARDWARE_EXCEPTION PARAM_ASSERTIONS_ENABLED_EXCEPTION -#else -#define PARAM_ASSERTIONS_ENABLED_HARDWARE_EXCEPTION 0 -#endif -#endif -#ifdef __cplusplus -extern "C" { -#endif - -/*! \brief Exception number definitions - * - * On Arm these are vector table indices: - * - * Name | Value | Exception - * ---------------------|-------|----------------------- - * NMI_EXCEPTION | 2 | Non Maskable Interrupt - * HARDFAULT_EXCEPTION | 3 | HardFault - * SVCALL_EXCEPTION | 11 | SV Call - * PENDSV_EXCEPTION | 14 | Pend SV - * SYSTICK_EXCEPTION | 15 | System Tick - * - * \if rp2350_specific - * On RISC-V these are exception cause numbers: - * - * Name | Value | Exception - * ------------------------|-------|----------------------------- - * INSTR_ALIGN_EXCEPTION | 0 | Instruction fetch misaligned - * INSTR_FAULT_EXCEPTION | 1 | Instruction fetch bus fault - * INSTR_ILLEGAL_EXCEPTION | 2 | Invalid or illegal instruction - * EBREAK_EXCEPTION | 3 | ebreak was not caught by an ex - * LOAD_ALIGN_EXCEPTION | 4 | Load address not naturally ali - * LOAD_FAULT_EXCEPTION | 5 | Load bus fault - * STORE_ALIGN_EXCEPTION | 6 | Store or AMO address not natur - * STORE_FAULT_EXCEPTION | 7 | Store or AMO bus fault - * ECALL_UMODE_EXCEPTION | 8 | ecall was executed in U-mode - * ECALL_SMODE_EXCEPTION | 9 | ecall was executed in S-mode - * ECALL_MMODE_EXCEPTION | 11 | ecall was executed in M-mode - * \endif - * - * \ingroup hardware_exception - */ -#ifdef __riscv -enum exception_number { - // Assigned to non-IRQ xcause values - MIN_EXCEPTION_NUM = 0, - INSTR_ALIGN_EXCEPTION = 0, ///< Instruction fetch misaligned (never fires if C/Zca is present) - INSTR_FAULT_EXCEPTION = 1, ///< Instruction fetch bus fault - INSTR_ILLEGAL_EXCEPTION = 2, ///< Invalid or illegal instruction - EBREAK_EXCEPTION = 3, ///< ebreak was not caught by an external debugger - LOAD_ALIGN_EXCEPTION = 4, ///< Load address not naturally aligned - LOAD_FAULT_EXCEPTION = 5, ///< Load bus fault - STORE_ALIGN_EXCEPTION = 6, ///< Store or AMO address not naturally aligned - STORE_FAULT_EXCEPTION = 7, ///< Store or AMO bus fault - ECALL_UMODE_EXCEPTION = 8, ///< ecall was executed in U-mode - ECALL_SMODE_EXCEPTION = 9, ///< ecall was executed in S-mode - ECALL_MMODE_EXCEPTION = 11, ///< ecall was executed in M-mode - MAX_EXCEPTION_NUM = 11 -}; -#else -enum exception_number { - // Assigned to VTOR indices - MIN_EXCEPTION_NUM = 2, - NMI_EXCEPTION = 2, ///< Non Maskable Interrupt - HARDFAULT_EXCEPTION = 3, ///< HardFault Interrupt - SVCALL_EXCEPTION = 11, ///< SV Call Interrupt - PENDSV_EXCEPTION = 14, ///< Pend SV Interrupt - SYSTICK_EXCEPTION = 15, ///< System Tick Interrupt - MAX_EXCEPTION_NUM = 15 -}; -#endif - -#define PICO_LOWEST_EXCEPTION_PRIORITY 0xff -#define PICO_HIGHEST_EXCEPTION_PRIORITY 0x00 - - -/*! \brief Exception handler function type - * \ingroup hardware_exception - * - * All exception handlers should be of this type, and follow normal ARM EABI register saving conventions - */ -typedef void (*exception_handler_t)(void); - -/*! \brief Set the exception handler for an exception on the executing core. - * \ingroup hardware_exception - * - * This method will assert if an exception handler has been set for this exception number on this core via - * this method, without an intervening restore via exception_restore_handler. - * - * \note this method may not be used to override an exception handler that was specified at link time by - * providing a strong replacement for the weakly defined stub exception handlers. It will assert in this case too. - * - * \param num Exception number - * \param handler The handler to set - * \see exception_number - */ -exception_handler_t exception_set_exclusive_handler(enum exception_number num, exception_handler_t handler); - -/*! \brief Restore the original exception handler for an exception on this core - * \ingroup hardware_exception - * - * This method may be used to restore the exception handler for an exception on this core to the state - * prior to the call to exception_set_exclusive_handler(), so that exception_set_exclusive_handler() - * may be called again in the future. - * - * \param num Exception number \ref exception_number - * \param original_handler The original handler returned from \ref exception_set_exclusive_handler - * \see exception_set_exclusive_handler() - */ -void exception_restore_handler(enum exception_number num, exception_handler_t original_handler); - -/*! \brief Get the current exception handler for the specified exception from the currently installed vector table - * of the execution core - * \ingroup hardware_exception - * - * \param num Exception number - * \return the address stored in the VTABLE for the given exception number - */ -exception_handler_t exception_get_vtable_handler(enum exception_number num); - -#ifndef __riscv -/*! \brief Set specified exception's priority - * \ingroup hardware_exception - * - * \param num Exception number \ref exception_number - * \param hardware_priority Priority to set. - * - * Numerically-lower values indicate a higher priority. Hardware priorities - * range from 0 (highest priority) to 255 (lowest priority). - * - * \if rp2040_specific - * Only the top 2 bits are significant on ARM Cortex-M0+ on RP2040. - * \endif - * - * \if rp2350_specific - * Only the top 4 bits are significant on ARM Cortex-M33 on RP2350, and exception priorities - * are not supported on RISC-V - * \endif - */ -bool exception_set_priority(uint num, uint8_t hardware_priority); - -/*! \brief Get specified exception's priority - * \ingroup hardware_exception - * - * Numerically-lower values indicate a higher priority. Hardware priorities - * range from 0 (highest priority) to 255 (lowest priority). - * - * \if rp2040_specific - * Only the top 2 bits are significant on ARM Cortex-M0+ on RP2040. - * \endif - * - * \if rp2350_specific - * Only the top 4 bits are significant on ARM Cortex-M33 on RP2350, and exception priorities - * are not supported on RISC-V - * \endif - * - * \param num Exception number \ref exception_number - * \return the exception priority - */ -uint exception_get_priority(uint num); -#endif - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/lib/main/pico-sdk/rp2_common/hardware_flash/flash.c b/lib/main/pico-sdk/rp2_common/hardware_flash/flash.c deleted file mode 100644 index cd2eafe4fb..0000000000 --- a/lib/main/pico-sdk/rp2_common/hardware_flash/flash.c +++ /dev/null @@ -1,221 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "hardware/flash.h" -#include "pico/bootrom.h" - -#if PICO_RP2040 -#include "hardware/structs/io_qspi.h" -#include "hardware/structs/ssi.h" -#else -#include "hardware/structs/qmi.h" -#endif - -#define FLASH_BLOCK_ERASE_CMD 0xd8 - -// Standard RUID instruction: 4Bh command prefix, 32 dummy bits, 64 data bits. -#define FLASH_RUID_CMD 0x4b -#define FLASH_RUID_DUMMY_BYTES 4 -#define FLASH_RUID_DATA_BYTES FLASH_UNIQUE_ID_SIZE_BYTES -#define FLASH_RUID_TOTAL_BYTES (1 + FLASH_RUID_DUMMY_BYTES + FLASH_RUID_DATA_BYTES) - -//----------------------------------------------------------------------------- -// Infrastructure for reentering XIP mode after exiting for programming (take -// a copy of boot2 before XIP exit). Calling boot2 as a function works because -// it accepts a return vector in LR (and doesn't trash r4-r7). Bootrom passes -// NULL in LR, instructing boot2 to enter flash vector table's reset handler. - -#if !PICO_NO_FLASH - -#define BOOT2_SIZE_WORDS 64 - -static uint32_t boot2_copyout[BOOT2_SIZE_WORDS]; -static bool boot2_copyout_valid = false; - -static void __no_inline_not_in_flash_func(flash_init_boot2_copyout)(void) { - if (boot2_copyout_valid) - return; - // todo we may want the option of boot2 just being a free function in - // user RAM, e.g. if it is larger than 256 bytes -#if PICO_RP2040 - const volatile uint32_t *copy_from = (uint32_t *)XIP_BASE; -#else - const volatile uint32_t *copy_from = (uint32_t *)BOOTRAM_BASE; -#endif - for (int i = 0; i < BOOT2_SIZE_WORDS; ++i) - boot2_copyout[i] = copy_from[i]; - __compiler_memory_barrier(); - boot2_copyout_valid = true; -} - - -static void __no_inline_not_in_flash_func(flash_enable_xip_via_boot2)(void) { - ((void (*)(void))((intptr_t)boot2_copyout+1))(); -} - -#else - -static void __no_inline_not_in_flash_func(flash_init_boot2_copyout)(void) {} - -static void __no_inline_not_in_flash_func(flash_enable_xip_via_boot2)(void) { - // Set up XIP for 03h read on bus access (slow but generic) - rom_flash_enter_cmd_xip_fn flash_enter_cmd_xip_func = (rom_flash_enter_cmd_xip_fn)rom_func_lookup_inline(ROM_FUNC_FLASH_ENTER_CMD_XIP); - assert(flash_enter_cmd_xip_func); - flash_enter_cmd_xip_func(); -} - -#endif - -//----------------------------------------------------------------------------- -// Actual flash programming shims (work whether or not PICO_NO_FLASH==1) - -void __no_inline_not_in_flash_func(flash_range_erase)(uint32_t flash_offs, size_t count) { -#ifdef PICO_FLASH_SIZE_BYTES - hard_assert(flash_offs + count <= PICO_FLASH_SIZE_BYTES); -#endif - invalid_params_if(HARDWARE_FLASH, flash_offs & (FLASH_SECTOR_SIZE - 1)); - invalid_params_if(HARDWARE_FLASH, count & (FLASH_SECTOR_SIZE - 1)); - rom_connect_internal_flash_fn connect_internal_flash_func = (rom_connect_internal_flash_fn)rom_func_lookup_inline(ROM_FUNC_CONNECT_INTERNAL_FLASH); - rom_flash_exit_xip_fn flash_exit_xip_func = (rom_flash_exit_xip_fn)rom_func_lookup_inline(ROM_FUNC_FLASH_EXIT_XIP); - rom_flash_range_erase_fn flash_range_erase_func = (rom_flash_range_erase_fn)rom_func_lookup_inline(ROM_FUNC_FLASH_RANGE_ERASE); - rom_flash_flush_cache_fn flash_flush_cache_func = (rom_flash_flush_cache_fn)rom_func_lookup_inline(ROM_FUNC_FLASH_FLUSH_CACHE); - assert(connect_internal_flash_func && flash_exit_xip_func && flash_range_erase_func && flash_flush_cache_func); - flash_init_boot2_copyout(); - - // No flash accesses after this point - __compiler_memory_barrier(); - - connect_internal_flash_func(); - flash_exit_xip_func(); - flash_range_erase_func(flash_offs, count, FLASH_BLOCK_SIZE, FLASH_BLOCK_ERASE_CMD); - flash_flush_cache_func(); // Note this is needed to remove CSn IO force as well as cache flushing - flash_enable_xip_via_boot2(); -} - -void __no_inline_not_in_flash_func(flash_flush_cache)(void) { - rom_flash_flush_cache_fn flash_flush_cache_func = (rom_flash_flush_cache_fn)rom_func_lookup_inline(ROM_FUNC_FLASH_FLUSH_CACHE); - flash_flush_cache_func(); -} - -void __no_inline_not_in_flash_func(flash_range_program)(uint32_t flash_offs, const uint8_t *data, size_t count) { -#ifdef PICO_FLASH_SIZE_BYTES - hard_assert(flash_offs + count <= PICO_FLASH_SIZE_BYTES); -#endif - invalid_params_if(HARDWARE_FLASH, flash_offs & (FLASH_PAGE_SIZE - 1)); - invalid_params_if(HARDWARE_FLASH, count & (FLASH_PAGE_SIZE - 1)); - rom_connect_internal_flash_fn connect_internal_flash_func = (rom_connect_internal_flash_fn)rom_func_lookup_inline(ROM_FUNC_CONNECT_INTERNAL_FLASH); - rom_flash_exit_xip_fn flash_exit_xip_func = (rom_flash_exit_xip_fn)rom_func_lookup_inline(ROM_FUNC_FLASH_EXIT_XIP); - rom_flash_range_program_fn flash_range_program_func = (rom_flash_range_program_fn)rom_func_lookup_inline(ROM_FUNC_FLASH_RANGE_PROGRAM); - rom_flash_flush_cache_fn flash_flush_cache_func = (rom_flash_flush_cache_fn)rom_func_lookup_inline(ROM_FUNC_FLASH_FLUSH_CACHE); - assert(connect_internal_flash_func && flash_exit_xip_func && flash_range_program_func && flash_flush_cache_func); - flash_init_boot2_copyout(); - - __compiler_memory_barrier(); - - connect_internal_flash_func(); - flash_exit_xip_func(); - flash_range_program_func(flash_offs, data, count); - flash_flush_cache_func(); // Note this is needed to remove CSn IO force as well as cache flushing - flash_enable_xip_via_boot2(); -} - -//----------------------------------------------------------------------------- -// Lower-level flash access functions - -#if !PICO_NO_FLASH -// Bitbanging the chip select using IO overrides, in case RAM-resident IRQs -// are still running, and the FIFO bottoms out. (the bootrom does the same) -static void __no_inline_not_in_flash_func(flash_cs_force)(bool high) { -#if PICO_RP2040 - uint32_t field_val = high ? - IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_VALUE_HIGH : - IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_VALUE_LOW; - hw_write_masked(&io_qspi_hw->io[1].ctrl, - field_val << IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_LSB, - IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_BITS - ); -#else - if (high) { - hw_clear_bits(&qmi_hw->direct_csr, QMI_DIRECT_CSR_ASSERT_CS0N_BITS); - } else { - hw_set_bits(&qmi_hw->direct_csr, QMI_DIRECT_CSR_ASSERT_CS0N_BITS); - } -#endif -} - -void __no_inline_not_in_flash_func(flash_do_cmd)(const uint8_t *txbuf, uint8_t *rxbuf, size_t count) { - rom_connect_internal_flash_fn connect_internal_flash_func = (rom_connect_internal_flash_fn)rom_func_lookup_inline(ROM_FUNC_CONNECT_INTERNAL_FLASH); - rom_flash_exit_xip_fn flash_exit_xip_func = (rom_flash_exit_xip_fn)rom_func_lookup_inline(ROM_FUNC_FLASH_EXIT_XIP); - rom_flash_flush_cache_fn flash_flush_cache_func = (rom_flash_flush_cache_fn)rom_func_lookup_inline(ROM_FUNC_FLASH_FLUSH_CACHE); - assert(connect_internal_flash_func && flash_exit_xip_func && flash_flush_cache_func); - flash_init_boot2_copyout(); - __compiler_memory_barrier(); - connect_internal_flash_func(); - flash_exit_xip_func(); - - flash_cs_force(0); - size_t tx_remaining = count; - size_t rx_remaining = count; -#if PICO_RP2040 - // Synopsys SSI version - // We may be interrupted -- don't want FIFO to overflow if we're distracted. - const size_t max_in_flight = 16 - 2; - while (tx_remaining || rx_remaining) { - uint32_t flags = ssi_hw->sr; - bool can_put = flags & SSI_SR_TFNF_BITS; - bool can_get = flags & SSI_SR_RFNE_BITS; - if (can_put && tx_remaining && rx_remaining - tx_remaining < max_in_flight) { - ssi_hw->dr0 = *txbuf++; - --tx_remaining; - } - if (can_get && rx_remaining) { - *rxbuf++ = (uint8_t)ssi_hw->dr0; - --rx_remaining; - } - } -#else - // QMI version -- no need to bound FIFO contents as QMI stalls on full DIRECT_RX. - hw_set_bits(&qmi_hw->direct_csr, QMI_DIRECT_CSR_EN_BITS); - while (tx_remaining || rx_remaining) { - uint32_t flags = qmi_hw->direct_csr; - bool can_put = !(flags & QMI_DIRECT_CSR_TXFULL_BITS); - bool can_get = !(flags & QMI_DIRECT_CSR_RXEMPTY_BITS); - if (can_put && tx_remaining) { - qmi_hw->direct_tx = *txbuf++; - --tx_remaining; - } - if (can_get && rx_remaining) { - *rxbuf++ = (uint8_t)qmi_hw->direct_rx; - --rx_remaining; - } - } - hw_clear_bits(&qmi_hw->direct_csr, QMI_DIRECT_CSR_EN_BITS); -#endif - flash_cs_force(1); - - flash_flush_cache_func(); - flash_enable_xip_via_boot2(); -} -#endif - -// Use standard RUID command to get a unique identifier for the flash (and -// hence the board) - -static_assert(FLASH_UNIQUE_ID_SIZE_BYTES == FLASH_RUID_DATA_BYTES, ""); - -void flash_get_unique_id(uint8_t *id_out) { -#if PICO_NO_FLASH - __unused uint8_t *ignore = id_out; - panic_unsupported(); -#else - uint8_t txbuf[FLASH_RUID_TOTAL_BYTES] = {0}; - uint8_t rxbuf[FLASH_RUID_TOTAL_BYTES] = {0}; - txbuf[0] = FLASH_RUID_CMD; - flash_do_cmd(txbuf, rxbuf, FLASH_RUID_TOTAL_BYTES); - for (int i = 0; i < FLASH_RUID_DATA_BYTES; i++) - id_out[i] = rxbuf[i + 1 + FLASH_RUID_DUMMY_BYTES]; -#endif -} diff --git a/lib/main/pico-sdk/rp2_common/hardware_flash/include/hardware/flash.h b/lib/main/pico-sdk/rp2_common/hardware_flash/include/hardware/flash.h deleted file mode 100644 index 0e2b91de8e..0000000000 --- a/lib/main/pico-sdk/rp2_common/hardware_flash/include/hardware/flash.h +++ /dev/null @@ -1,128 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _HARDWARE_FLASH_H -#define _HARDWARE_FLASH_H - -#include "pico.h" - -/** \file flash.h - * \defgroup hardware_flash hardware_flash - * - * \brief Low level flash programming and erase API - * - * Note these functions are *unsafe* if you are using both cores, and the other - * is executing from flash concurrently with the operation. In this could be the - * case, you must perform your own synchronisation to make sure that no XIP - * accesses take place during flash programming. One option is to use the - * \ref multicore_lockout functions. - * - * Likewise they are *unsafe* if you have interrupt handlers or an interrupt - * vector table in flash, so you must disable interrupts before calling in - * this case. - * - * If PICO_NO_FLASH=1 is not defined (i.e. if the program is built to run from - * flash) then these functions will make a static copy of the second stage - * bootloader in SRAM, and use this to reenter execute-in-place mode after - * programming or erasing flash, so that they can safely be called from - * flash-resident code. - * - * \subsection flash_example Example - * \include flash_program.c - */ - -// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_HARDWARE_FLASH, Enable/disable assertions in the hardware_flash module, type=bool, default=0, group=hardware_flash -#ifndef PARAM_ASSERTIONS_ENABLED_HARDWARE_FLASH -#ifdef PARAM_ASSERTIONS_ENABLED_FLASH // backwards compatibility with SDK < 2.0.0 -#define PARAM_ASSERTIONS_ENABLED_HARDWARE_FLASH PARAM_ASSERTIONS_ENABLED_FLASH -#else -#define PARAM_ASSERTIONS_ENABLED_HARDWARE_FLASH 0 -#endif -#endif -#define FLASH_PAGE_SIZE (1u << 8) -#define FLASH_SECTOR_SIZE (1u << 12) -#define FLASH_BLOCK_SIZE (1u << 16) - -#ifndef FLASH_UNIQUE_ID_SIZE_BYTES -#define FLASH_UNIQUE_ID_SIZE_BYTES 8 -#endif - -// PICO_CONFIG: PICO_FLASH_SIZE_BYTES, size of primary flash in bytes, type=int, default=Usually provided via board header, group=hardware_flash - -#ifdef __cplusplus -extern "C" { -#endif - -/*! \brief Erase areas of flash - * \ingroup hardware_flash - * - * \param flash_offs Offset into flash, in bytes, to start the erase. Must be aligned to a 4096-byte flash sector. - * \param count Number of bytes to be erased. Must be a multiple of 4096 bytes (one sector). - * - * @note Erasing a flash sector sets all the bits in all the pages in that sector to one. - * You can then "program" flash pages in the sector to turn some of the bits to zero. - * Once a bit is set to zero it can only be changed back to one by erasing the whole sector again. - */ -void flash_range_erase(uint32_t flash_offs, size_t count); - -/*! \brief Program flash - * \ingroup hardware_flash - * - * \param flash_offs Flash address of the first byte to be programmed. Must be aligned to a 256-byte flash page. - * \param data Pointer to the data to program into flash - * \param count Number of bytes to program. Must be a multiple of 256 bytes (one page). - * - * @note: Programming a flash page effectively changes some of the bits from one to zero. - * The only way to change a zero bit back to one is to "erase" the whole sector that the page resides in. - * So you may need to make sure you have called flash_range_erase before calling flash_range_program. - */ - -void flash_range_program(uint32_t flash_offs, const uint8_t *data, size_t count); - -/*! \brief Get flash unique 64 bit identifier - * \ingroup hardware_flash - * - * Use a standard 4Bh RUID instruction to retrieve the 64 bit unique - * identifier from a flash device attached to the QSPI interface. Since there - * is a 1:1 association between the MCU and this flash, this also serves as a - * unique identifier for the board. - * - * \param id_out Pointer to an 8-byte buffer to which the ID will be written - */ -void flash_get_unique_id(uint8_t *id_out); - -/*! \brief Execute bidirectional flash command - * \ingroup hardware_flash - * - * Low-level function to execute a serial command on a flash device attached - * to the QSPI interface. Bytes are simultaneously transmitted and received - * from txbuf and to rxbuf. Therefore, both buffers must be the same length, - * count, which is the length of the overall transaction. This is useful for - * reading metadata from the flash chip, such as device ID or SFDP - * parameters. - * - * The XIP cache is flushed following each command, in case flash state - * has been modified. Like other hardware_flash functions, the flash is not - * accessible for execute-in-place transfers whilst the command is in - * progress, so entering a flash-resident interrupt handler or executing flash - * code on the second core concurrently will be fatal. To avoid these pitfalls - * it is recommended that this function only be used to extract flash metadata - * during startup, before the main application begins to run: see the - * implementation of pico_get_unique_id() for an example of this. - * - * \param txbuf Pointer to a byte buffer which will be transmitted to the flash - * \param rxbuf Pointer to a byte buffer where data received from the flash will be written. txbuf and rxbuf may be the same buffer. - * \param count Length in bytes of txbuf and of rxbuf - */ -void flash_do_cmd(const uint8_t *txbuf, uint8_t *rxbuf, size_t count); - -void flash_flush_cache(void); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/lib/main/pico-sdk/rp2_common/hardware_gpio/gpio.c b/lib/main/pico-sdk/rp2_common/hardware_gpio/gpio.c deleted file mode 100644 index 44c39e9c40..0000000000 --- a/lib/main/pico-sdk/rp2_common/hardware_gpio/gpio.c +++ /dev/null @@ -1,316 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "hardware/gpio.h" -#include "hardware/sync.h" - -#include "hardware/structs/io_bank0.h" -#include "hardware/irq.h" - -#if LIB_PICO_BINARY_INFO -#include "pico/binary_info.h" -#endif - -static gpio_irq_callback_t callbacks[NUM_CORES]; -// a 1 bit means the IRQ is handled by a raw IRQ handler -#if NUM_BANK0_GPIOS > 32 -typedef uint64_t raw_irq_mask_type_t; -#else -typedef uint32_t raw_irq_mask_type_t; -#endif - -static raw_irq_mask_type_t raw_irq_mask[NUM_CORES]; - -// Get the raw value from the pin, bypassing any muxing or overrides. -int gpio_get_pad(uint gpio) { - check_gpio_param(gpio); - hw_set_bits(&pads_bank0_hw->io[gpio], PADS_BANK0_GPIO0_IE_BITS); - return (io_bank0_hw->io[gpio].status & IO_BANK0_GPIO0_STATUS_INFROMPAD_BITS) - >> IO_BANK0_GPIO0_STATUS_INFROMPAD_LSB; -} - -/// \tag::gpio_set_function[] -// Select function for this GPIO, and ensure input/output are enabled at the pad. -// This also clears the input/output/irq override bits. -void gpio_set_function(uint gpio, gpio_function_t fn) { - check_gpio_param(gpio); - invalid_params_if(HARDWARE_GPIO, ((uint32_t)fn << IO_BANK0_GPIO0_CTRL_FUNCSEL_LSB) & ~IO_BANK0_GPIO0_CTRL_FUNCSEL_BITS); - // Set input enable on, output disable off - hw_write_masked(&pads_bank0_hw->io[gpio], - PADS_BANK0_GPIO0_IE_BITS, - PADS_BANK0_GPIO0_IE_BITS | PADS_BANK0_GPIO0_OD_BITS - ); - // Zero all fields apart from fsel; we want this IO to do what the peripheral tells it. - // This doesn't affect e.g. pullup/pulldown, as these are in pad controls. - io_bank0_hw->io[gpio].ctrl = fn << IO_BANK0_GPIO0_CTRL_FUNCSEL_LSB; -#if !PICO_RP2040 - // Remove pad isolation now that the correct peripheral is in control of the pad - hw_clear_bits(&pads_bank0_hw->io[gpio], PADS_BANK0_GPIO0_ISO_BITS); -#endif -} -/// \end::gpio_set_function[] - -gpio_function_t gpio_get_function(uint gpio) { - check_gpio_param(gpio); - return (gpio_function_t) ((io_bank0_hw->io[gpio].ctrl & IO_BANK0_GPIO0_CTRL_FUNCSEL_BITS) >> IO_BANK0_GPIO0_CTRL_FUNCSEL_LSB); -} - -// Note that, on RP2040, setting both pulls enables a "bus keep" function, -// i.e. weak pull to whatever is current high/low state of GPIO. -void gpio_set_pulls(uint gpio, bool up, bool down) { - check_gpio_param(gpio); - hw_write_masked( - &pads_bank0_hw->io[gpio], - (bool_to_bit(up) << PADS_BANK0_GPIO0_PUE_LSB) | (bool_to_bit(down) << PADS_BANK0_GPIO0_PDE_LSB), - PADS_BANK0_GPIO0_PUE_BITS | PADS_BANK0_GPIO0_PDE_BITS - ); -} - -// Direct override for per-GPIO IRQ signal -void gpio_set_irqover(uint gpio, uint value) { - check_gpio_param(gpio); - hw_write_masked(&io_bank0_hw->io[gpio].ctrl, - value << IO_BANK0_GPIO0_CTRL_IRQOVER_LSB, - IO_BANK0_GPIO0_CTRL_IRQOVER_BITS - ); -} - -// Direct overrides for pad controls -void gpio_set_inover(uint gpio, uint value) { - check_gpio_param(gpio); - hw_write_masked(&io_bank0_hw->io[gpio].ctrl, - value << IO_BANK0_GPIO0_CTRL_INOVER_LSB, - IO_BANK0_GPIO0_CTRL_INOVER_BITS - ); -} - -void gpio_set_outover(uint gpio, uint value) { - check_gpio_param(gpio); - hw_write_masked(&io_bank0_hw->io[gpio].ctrl, - value << IO_BANK0_GPIO0_CTRL_OUTOVER_LSB, - IO_BANK0_GPIO0_CTRL_OUTOVER_BITS - ); -} - -void gpio_set_oeover(uint gpio, uint value) { - check_gpio_param(gpio); - hw_write_masked(&io_bank0_hw->io[gpio].ctrl, - value << IO_BANK0_GPIO0_CTRL_OEOVER_LSB, - IO_BANK0_GPIO0_CTRL_OEOVER_BITS - ); -} - -void gpio_set_input_hysteresis_enabled(uint gpio, bool enabled) { - check_gpio_param(gpio); - if (enabled) - hw_set_bits(&pads_bank0_hw->io[gpio], PADS_BANK0_GPIO0_SCHMITT_BITS); - else - hw_clear_bits(&pads_bank0_hw->io[gpio], PADS_BANK0_GPIO0_SCHMITT_BITS); -} - - -bool gpio_is_input_hysteresis_enabled(uint gpio) { - check_gpio_param(gpio); - return (pads_bank0_hw->io[gpio] & PADS_BANK0_GPIO0_SCHMITT_BITS) != 0; -} - -void gpio_set_slew_rate(uint gpio, enum gpio_slew_rate slew) { - check_gpio_param(gpio); - hw_write_masked(&pads_bank0_hw->io[gpio], - (uint)slew << PADS_BANK0_GPIO0_SLEWFAST_LSB, - PADS_BANK0_GPIO0_SLEWFAST_BITS - ); -} - -enum gpio_slew_rate gpio_get_slew_rate(uint gpio) { - check_gpio_param(gpio); - return (enum gpio_slew_rate)((pads_bank0_hw->io[gpio] - & PADS_BANK0_GPIO0_SLEWFAST_BITS) - >> PADS_BANK0_GPIO0_SLEWFAST_LSB); -} - - -// Enum encoding should match hardware encoding on RP2040 -static_assert(PADS_BANK0_GPIO0_DRIVE_VALUE_8MA == GPIO_DRIVE_STRENGTH_8MA, ""); -void gpio_set_drive_strength(uint gpio, enum gpio_drive_strength drive) { - check_gpio_param(gpio); - hw_write_masked(&pads_bank0_hw->io[gpio], - (uint)drive << PADS_BANK0_GPIO0_DRIVE_LSB, - PADS_BANK0_GPIO0_DRIVE_BITS - ); -} - -enum gpio_drive_strength gpio_get_drive_strength(uint gpio) { - check_gpio_param(gpio); - return (enum gpio_drive_strength)((pads_bank0_hw->io[gpio] - & PADS_BANK0_GPIO0_DRIVE_BITS) - >> PADS_BANK0_GPIO0_DRIVE_LSB); -} - -static void gpio_default_irq_handler(void) { - uint core = get_core_num(); - gpio_irq_callback_t callback = callbacks[core]; - io_bank0_irq_ctrl_hw_t *irq_ctrl_base = core ? &io_bank0_hw->proc1_irq_ctrl : &io_bank0_hw->proc0_irq_ctrl; - for (uint gpio = 0; gpio < NUM_BANK0_GPIOS; gpio+=8) { - uint32_t events8 = irq_ctrl_base->ints[gpio >> 3u]; - // note we assume events8 is 0 for non-existent GPIO - for(uint i=gpio;events8 && i>= 4; - } - } -} - -static void _gpio_set_irq_enabled(uint gpio, uint32_t events, bool enabled, io_bank0_irq_ctrl_hw_t *irq_ctrl_base) { - // Clear stale events which might cause immediate spurious handler entry - gpio_acknowledge_irq(gpio, events); - - io_rw_32 *en_reg = &irq_ctrl_base->inte[gpio / 8]; - events <<= 4 * (gpio % 8); - - if (enabled) - hw_set_bits(en_reg, events); - else - hw_clear_bits(en_reg, events); -} - -void gpio_set_irq_enabled(uint gpio, uint32_t events, bool enabled) { - // either this call disables the interrupt - // or callback should already be set (raw or using gpio_set_irq_callback) - // this protects against enabling the interrupt without callback set - assert(!enabled - || (raw_irq_mask[get_core_num()] & (1ull<proc1_irq_ctrl : &io_bank0_hw->proc0_irq_ctrl; - _gpio_set_irq_enabled(gpio, events, enabled, irq_ctrl_base); -} - -void gpio_set_irq_enabled_with_callback(uint gpio, uint32_t events, bool enabled, gpio_irq_callback_t callback) { - // first set callback, then enable the interrupt - gpio_set_irq_callback(callback); - gpio_set_irq_enabled(gpio, events, enabled); - if (enabled) irq_set_enabled(IO_IRQ_BANK0, true); -} - -void gpio_set_irq_callback(gpio_irq_callback_t callback) { - uint core = get_core_num(); - if (callbacks[core]) { - if (!callback) { - irq_remove_handler(IO_IRQ_BANK0, gpio_default_irq_handler); - } - callbacks[core] = callback; - } else if (callback) { - callbacks[core] = callback; - irq_add_shared_handler(IO_IRQ_BANK0, gpio_default_irq_handler, GPIO_IRQ_CALLBACK_ORDER_PRIORITY); - } -} - -void gpio_add_raw_irq_handler_with_order_priority_masked(uint32_t gpio_mask, irq_handler_t handler, uint8_t order_priority) { - hard_assert(!(raw_irq_mask[get_core_num()] & gpio_mask)); // should not add multiple handlers for the same event - raw_irq_mask[get_core_num()] |= gpio_mask; - irq_add_shared_handler(IO_IRQ_BANK0, handler, order_priority); -} - -void gpio_add_raw_irq_handler_with_order_priority_masked64(uint64_t gpio_mask, irq_handler_t handler, uint8_t order_priority) { - hard_assert(!(raw_irq_mask[get_core_num()] & gpio_mask)); // should not add multiple handlers for the same event - raw_irq_mask[get_core_num()] |= (raw_irq_mask_type_t) gpio_mask; - irq_add_shared_handler(IO_IRQ_BANK0, handler, order_priority); -} - -void gpio_add_raw_irq_handler_masked(uint32_t gpio_mask, irq_handler_t handler) { - gpio_add_raw_irq_handler_with_order_priority_masked(gpio_mask, handler, GPIO_RAW_IRQ_HANDLER_DEFAULT_ORDER_PRIORITY); -} - -void gpio_add_raw_irq_handler_masked64(uint64_t gpio_mask, irq_handler_t handler) { - gpio_add_raw_irq_handler_with_order_priority_masked64(gpio_mask, handler, GPIO_RAW_IRQ_HANDLER_DEFAULT_ORDER_PRIORITY); -} - -void gpio_remove_raw_irq_handler_masked(uint32_t gpio_mask, irq_handler_t handler) { - assert(raw_irq_mask[get_core_num()] & gpio_mask); // should not remove handlers that are not added - irq_remove_handler(IO_IRQ_BANK0, handler); - raw_irq_mask[get_core_num()] &= ~gpio_mask; -} - -void gpio_remove_raw_irq_handler_masked64(uint64_t gpio_mask, irq_handler_t handler) { - assert(raw_irq_mask[get_core_num()] & gpio_mask); // should not remove handlers that are not added - irq_remove_handler(IO_IRQ_BANK0, handler); - raw_irq_mask[get_core_num()] &= (raw_irq_mask_type_t)~gpio_mask; -} - -void gpio_set_dormant_irq_enabled(uint gpio, uint32_t events, bool enabled) { - check_gpio_param(gpio); - io_bank0_irq_ctrl_hw_t *irq_ctrl_base = &io_bank0_hw->dormant_wake_irq_ctrl; - _gpio_set_irq_enabled(gpio, events, enabled, irq_ctrl_base); -} - -void gpio_acknowledge_irq(uint gpio, uint32_t events) { - check_gpio_param(gpio); - io_bank0_hw->intr[gpio / 8] = events << (4 * (gpio % 8)); -} - -#define DEBUG_PIN_MASK (((1u << PICO_DEBUG_PIN_COUNT)-1) << PICO_DEBUG_PIN_BASE) -void gpio_debug_pins_init(void) { - gpio_init_mask(DEBUG_PIN_MASK); - gpio_set_dir_masked(DEBUG_PIN_MASK, DEBUG_PIN_MASK); -#if LIB_PICO_BINARY_INFO - bi_decl_if_func_used(bi_pin_mask_with_names(DEBUG_PIN_MASK, "Debug")); -#endif -} - -void gpio_set_input_enabled(uint gpio, bool enabled) { - check_gpio_param(gpio); - if (enabled) - hw_set_bits(&pads_bank0_hw->io[gpio], PADS_BANK0_GPIO0_IE_BITS); - else - hw_clear_bits(&pads_bank0_hw->io[gpio], PADS_BANK0_GPIO0_IE_BITS); -} - -void gpio_init(uint gpio) { - gpio_set_dir(gpio, GPIO_IN); - gpio_put(gpio, 0); - gpio_set_function(gpio, GPIO_FUNC_SIO); -} - -void gpio_deinit(uint gpio) { - gpio_set_function(gpio, GPIO_FUNC_NULL); -} - -void gpio_init_mask(uint gpio_mask) { - for(uint i=0;i>= 1; - } -} - -void gpio_set_function_masked(uint32_t gpio_mask, gpio_function_t fn) { - for (uint i = 0; i < MIN(NUM_BANK0_GPIOS, 32u); i++) { - if (gpio_mask & 1u) { - gpio_set_function(i, fn); - } - gpio_mask >>= 1; - } -} - -void gpio_set_function_masked64(uint64_t gpio_mask, gpio_function_t fn) { - for (uint i = 0; i < MIN(NUM_BANK0_GPIOS, 64u); i++) { - if (gpio_mask & 1u) { - gpio_set_function(i, fn); - } - gpio_mask >>= 1; - } -} diff --git a/lib/main/pico-sdk/rp2_common/hardware_gpio/include/hardware/gpio.h b/lib/main/pico-sdk/rp2_common/hardware_gpio/include/hardware/gpio.h deleted file mode 100644 index d1cb13e89c..0000000000 --- a/lib/main/pico-sdk/rp2_common/hardware_gpio/include/hardware/gpio.h +++ /dev/null @@ -1,1435 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _HARDWARE_GPIO_H -#define _HARDWARE_GPIO_H - -#include "pico.h" -#include "hardware/structs/sio.h" -#include "hardware/structs/pads_bank0.h" -#include "hardware/structs/io_bank0.h" -#include "hardware/irq.h" - -// PICO_CONFIG: PICO_USE_GPIO_COPROCESSOR, Enable/disable use of the GPIO coprocessor for GPIO access, type=bool, default=1, group=hardware_gpio -#if !defined(PICO_USE_GPIO_COPROCESSOR) && HAS_GPIO_COPROCESSOR -#define PICO_USE_GPIO_COPROCESSOR 1 -#endif - -#if PICO_USE_GPIO_COPROCESSOR -#include "hardware/gpio_coproc.h" -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_HARDWARE_GPIO, Enable/disable assertions in the hardware_gpio module, type=bool, default=0, group=hardware_gpio -#ifndef PARAM_ASSERTIONS_ENABLED_HARDWARE_GPIO -#ifdef PARAM_ASSERTIONS_ENABLED_GPIO // backwards compatibility with SDK < 2.0.0 -#define PARAM_ASSERTIONS_ENABLED_HARDWARE_GPIO PARAM_ASSERTIONS_ENABLED_GPIO -#else -#define PARAM_ASSERTIONS_ENABLED_HARDWARE_GPIO 0 -#endif -#endif - -/** \file gpio.h - * \defgroup hardware_gpio hardware_gpio - * - * \brief General Purpose Input/Output (GPIO) API - * - * RP-series microcontrollers have two banks of General Purpose Input / Output (GPIO) pins, which are assigned as follows: - * - * \if rp2040-specific - * RP2040 has 30 user GPIO pins in bank 0, and 6 QSPI pins in the QSPI bank 1 (QSPI_SS, QSPI_SCLK and QSPI_SD0 to QSPI_SD3). The QSPI - * pins are used to execute code from an external flash device, leaving the User bank (GPIO0 to GPIO29) for the programmer to use. - * \endif - * - * \if rp2350-specific - * The number of GPIO pins available depends on the package. There are 30 user GPIOs in bank 0 in the QFN-60 package (RP2350A), or 48 user GPIOs - * in the QFN-80 package. Bank 1 contains the 6 QSPI pins and the USB DP/DM pins. - * \endif - * - * All GPIOs support digital input and output, but a subset can also be used as inputs to the chip’s Analogue to Digital - * Converter (ADC). The allocation of GPIO pins to the ADC depends on the packaging. - * - * RP2040 and RP2350 QFN-60 GPIO, ADC pins are 26-29. - * RP2350 QFN-80, ADC pins are 40-47. - * - * Each GPIO can be controlled directly by software running on the processors, or by a number of other functional blocks. - * - * The function allocated to each GPIO is selected by calling the \ref gpio_set_function function. \note Not all functions - * are available on all pins. - * - * Each GPIO can have one function selected at a time. Likewise, each peripheral input (e.g. UART0 RX) should only be selected on - * one _GPIO_ at a time. If the same peripheral input is connected to multiple GPIOs, the peripheral sees the logical OR of these - * GPIO inputs. Please refer to the datasheet for more information on GPIO function select. - * - * ### Function Select Table - * - * \if rp2040_specific - * On RP2040 the function selects are: - * - * | GPIO | F1 | F2 | F3 | F4 | F5 | F6 | F7 | F8 | F9 | - * |--------|----------|-----------|----------|--------|-----|------|------|---------------|---------------| - * | 0 | SPI0 RX | UART0 TX | I2C0 SDA | PWM0 A | SIO | PIO0 | PIO1 | | USB OVCUR DET | - * | 1 | SPI0 CSn | UART0 RX | I2C0 SCL | PWM0 B | SIO | PIO0 | PIO1 | | USB VBUS DET | - * | 2 | SPI0 SCK | UART0 CTS | I2C1 SDA | PWM1 A | SIO | PIO0 | PIO1 | | USB VBUS EN | - * | 3 | SPI0 TX | UART0 RTS | I2C1 SCL | PWM1 B | SIO | PIO0 | PIO1 | | USB OVCUR DET | - * | 4 | SPI0 RX | UART1 TX | I2C0 SDA | PWM2 A | SIO | PIO0 | PIO1 | | USB VBUS DET | - * | 5 | SPI0 CSn | UART1 RX | I2C0 SCL | PWM2 B | SIO | PIO0 | PIO1 | | USB VBUS EN | - * | 6 | SPI0 SCK | UART1 CTS | I2C1 SDA | PWM3 A | SIO | PIO0 | PIO1 | | USB OVCUR DET | - * | 7 | SPI0 TX | UART1 RTS | I2C1 SCL | PWM3 B | SIO | PIO0 | PIO1 | | USB VBUS DET | - * | 8 | SPI1 RX | UART1 TX | I2C0 SDA | PWM4 A | SIO | PIO0 | PIO1 | | USB VBUS EN | - * | 9 | SPI1 CSn | UART1 RX | I2C0 SCL | PWM4 B | SIO | PIO0 | PIO1 | | USB OVCUR DET | - * | 10 | SPI1 SCK | UART1 CTS | I2C1 SDA | PWM5 A | SIO | PIO0 | PIO1 | | USB VBUS DET | - * | 11 | SPI1 TX | UART1 RTS | I2C1 SCL | PWM5 B | SIO | PIO0 | PIO1 | | USB VBUS EN | - * | 12 | SPI1 RX | UART0 TX | I2C0 SDA | PWM6 A | SIO | PIO0 | PIO1 | | USB OVCUR DET | - * | 13 | SPI1 CSn | UART0 RX | I2C0 SCL | PWM6 B | SIO | PIO0 | PIO1 | | USB VBUS DET | - * | 14 | SPI1 SCK | UART0 CTS | I2C1 SDA | PWM7 A | SIO | PIO0 | PIO1 | | USB VBUS EN | - * | 15 | SPI1 TX | UART0 RTS | I2C1 SCL | PWM7 B | SIO | PIO0 | PIO1 | | USB OVCUR DET | - * | 16 | SPI0 RX | UART0 TX | I2C0 SDA | PWM0 A | SIO | PIO0 | PIO1 | | USB VBUS DET | - * | 17 | SPI0 CSn | UART0 RX | I2C0 SCL | PWM0 B | SIO | PIO0 | PIO1 | | USB VBUS EN | - * | 18 | SPI0 SCK | UART0 CTS | I2C1 SDA | PWM1 A | SIO | PIO0 | PIO1 | | USB OVCUR DET | - * | 19 | SPI0 TX | UART0 RTS | I2C1 SCL | PWM1 B | SIO | PIO0 | PIO1 | | USB VBUS DET | - * | 20 | SPI0 RX | UART1 TX | I2C0 SDA | PWM2 A | SIO | PIO0 | PIO1 | CLOCK GPIN0 | USB VBUS EN | - * | 21 | SPI0 CSn | UART1 RX | I2C0 SCL | PWM2 B | SIO | PIO0 | PIO1 | CLOCK GPOUT0 | USB OVCUR DET | - * | 22 | SPI0 SCK | UART1 CTS | I2C1 SDA | PWM3 A | SIO | PIO0 | PIO1 | CLOCK GPIN1 | USB VBUS DET | - * | 23 | SPI0 TX | UART1 RTS | I2C1 SCL | PWM3 B | SIO | PIO0 | PIO1 | CLOCK GPOUT1 | USB VBUS EN | - * | 24 | SPI1 RX | UART1 TX | I2C0 SDA | PWM4 A | SIO | PIO0 | PIO1 | CLOCK GPOUT2 | USB OVCUR DET | - * | 25 | SPI1 CSn | UART1 RX | I2C0 SCL | PWM4 B | SIO | PIO0 | PIO1 | CLOCK GPOUT3 | USB VBUS DET | - * | 26 | SPI1 SCK | UART1 CTS | I2C1 SDA | PWM5 A | SIO | PIO0 | PIO1 | | USB VBUS EN | - * | 27 | SPI1 TX | UART1 RTS | I2C1 SCL | PWM5 B | SIO | PIO0 | PIO1 | | USB OVCUR DET | - * | 28 | SPI1 RX | UART0 TX | I2C0 SDA | PWM6 A | SIO | PIO0 | PIO1 | | USB VBUS DET | - * | 29 | SPI1 CSn | UART0 RX | I2C0 SCL | PWM6 B | SIO | PIO0 | PIO1 | | USB VBUS EN | - * \endif - * \if rp2350_specific - * On RP2350 the function selects are: - * - * | GPIO | F0 | F1 | F2 | F3 | F4 | F5 | F6 | F7 | F8 | F9 | F10 | F11 | - * |-------|------|----------|-----------|----------|--------|-----|------|------|------|--------------|---------------|----------| - * | 0 | | SPI0 RX | UART0 TX | I2C0 SDA | PWM0 A | SIO | PIO0 | PIO1 | PIO2 | XIP_CS1n | USB OVCUR DET | | - * | 1 | | SPI0 CSn | UART0 RX | I2C0 SCL | PWM0 B | SIO | PIO0 | PIO1 | PIO2 | TRACECLK | USB VBUS DET | | - * | 2 | | SPI0 SCK | UART0 CTS | I2C1 SDA | PWM1 A | SIO | PIO0 | PIO1 | PIO2 | TRACEDATA0 | USB VBUS EN | UART0 TX | - * | 3 | | SPI0 TX | UART0 RTS | I2C1 SCL | PWM1 B | SIO | PIO0 | PIO1 | PIO2 | TRACEDATA1 | USB OVCUR DET | UART0 RX | - * | 4 | | SPI0 RX | UART1 TX | I2C0 SDA | PWM2 A | SIO | PIO0 | PIO1 | PIO2 | TRACEDATA2 | USB VBUS DET | | - * | 5 | | SPI0 CSn | UART1 RX | I2C0 SCL | PWM2 B | SIO | PIO0 | PIO1 | PIO2 | TRACEDATA3 | USB VBUS EN | | - * | 6 | | SPI0 SCK | UART1 CTS | I2C1 SDA | PWM3 A | SIO | PIO0 | PIO1 | PIO2 | | USB OVCUR DET | UART1 TX | - * | 7 | | SPI0 TX | UART1 RTS | I2C1 SCL | PWM3 B | SIO | PIO0 | PIO1 | PIO2 | | USB VBUS DET | UART1 RX | - * | 8 | | SPI1 RX | UART1 TX | I2C0 SDA | PWM4 A | SIO | PIO0 | PIO1 | PIO2 | XIP_CS1n | USB VBUS EN | | - * | 9 | | SPI1 CSn | UART1 RX | I2C0 SCL | PWM4 B | SIO | PIO0 | PIO1 | PIO2 | | USB OVCUR DET | | - * | 10 | | SPI1 SCK | UART1 CTS | I2C1 SDA | PWM5 A | SIO | PIO0 | PIO1 | PIO2 | | USB VBUS DET | UART1 TX | - * | 11 | | SPI1 TX | UART1 RTS | I2C1 SCL | PWM5 B | SIO | PIO0 | PIO1 | PIO2 | | USB VBUS EN | UART1 RX | - * | 12 | HSTX | SPI1 RX | UART0 TX | I2C0 SDA | PWM6 A | SIO | PIO0 | PIO1 | PIO2 | CLOCK GPIN0 | USB OVCUR DET | | - * | 13 | HSTX | SPI1 CSn | UART0 RX | I2C0 SCL | PWM6 B | SIO | PIO0 | PIO1 | PIO2 | CLOCK GPOUT0 | USB VBUS DET | | - * | 14 | HSTX | SPI1 SCK | UART0 CTS | I2C1 SDA | PWM7 A | SIO | PIO0 | PIO1 | PIO2 | CLOCK GPIN1 | USB VBUS EN | UART0 TX | - * | 15 | HSTX | SPI1 TX | UART0 RTS | I2C1 SCL | PWM7 B | SIO | PIO0 | PIO1 | PIO2 | CLOCK GPOUT1 | USB OVCUR DET | UART0 RX | - * | 16 | HSTX | SPI0 RX | UART0 TX | I2C0 SDA | PWM0 A | SIO | PIO0 | PIO1 | PIO2 | | USB VBUS DET | | - * | 17 | HSTX | SPI0 CSn | UART0 RX | I2C0 SCL | PWM0 B | SIO | PIO0 | PIO1 | PIO2 | | USB VBUS EN | | - * | 18 | HSTX | SPI0 SCK | UART0 CTS | I2C1 SDA | PWM1 A | SIO | PIO0 | PIO1 | PIO2 | | USB OVCUR DET | UART0 TX | - * | 19 | HSTX | SPI0 TX | UART0 RTS | I2C1 SCL | PWM1 B | SIO | PIO0 | PIO1 | PIO2 | XIP_CS1n | USB VBUS DET | UART0 RX | - * | 20 | | SPI0 RX | UART1 TX | I2C0 SDA | PWM2 A | SIO | PIO0 | PIO1 | PIO2 | CLOCK GPIN0 | USB VBUS EN | | - * | 21 | | SPI0 CSn | UART1 RX | I2C0 SCL | PWM2 B | SIO | PIO0 | PIO1 | PIO2 | CLOCK GPOUT0 | USB OVCUR DET | | - * | 22 | | SPI0 SCK | UART1 CTS | I2C1 SDA | PWM3 A | SIO | PIO0 | PIO1 | PIO2 | CLOCK GPIN1 | USB VBUS DET | UART1 TX | - * | 23 | | SPI0 TX | UART1 RTS | I2C1 SCL | PWM3 B | SIO | PIO0 | PIO1 | PIO2 | CLOCK GPOUT1 | USB VBUS EN | UART1 RX | - * | 24 | | SPI1 RX | UART1 TX | I2C0 SDA | PWM4 A | SIO | PIO0 | PIO1 | PIO2 | CLOCK GPOUT2 | USB OVCUR DET | | - * | 25 | | SPI1 CSn | UART1 RX | I2C0 SCL | PWM4 B | SIO | PIO0 | PIO1 | PIO2 | CLOCK GPOUT3 | USB VBUS DET | | - * | 26 | | SPI1 SCK | UART1 CTS | I2C1 SDA | PWM5 A | SIO | PIO0 | PIO1 | PIO2 | | USB VBUS EN | UART1 TX | - * | 27 | | SPI1 TX | UART1 RTS | I2C1 SCL | PWM5 B | SIO | PIO0 | PIO1 | PIO2 | | USB OVCUR DET | UART1 RX | - * | 28 | | SPI1 RX | UART0 TX | I2C0 SDA | PWM6 A | SIO | PIO0 | PIO1 | PIO2 | | USB VBUS DET | | - * | 29 | | SPI1 CSn | UART0 RX | I2C0 SCL | PWM6 B | SIO | PIO0 | PIO1 | PIO2 | | USB VBUS EN | | - * - * GPIOs 30 through 47 are QFN-80 only: - * - * | GPIO | F0 | F1 | F2 | F3 | F4 | F5 | F6 | F7 | F8 | F9 | F10 | F11 | - * |------|----|----------|----------|-----------|---------|-----|------|------|------|----------|---------------|----------| - * | 30 | | SPI1 SCK | UART0 CTS | I2C1 SDA | PWM7 A | SIO | PIO0 | PIO1 | PIO2 | | USB OVCUR DET | UART0 TX | - * | 31 | | SPI1 TX | UART0 RTS | I2C1 SCL | PWM7 B | SIO | PIO0 | PIO1 | PIO2 | | USB VBUS DET | UART0 RX | - * | 32 | | SPI0 RX | UART0 TX | I2C0 SDA | PWM8 A | SIO | PIO0 | PIO1 | PIO2 | | USB VBUS EN | | - * | 33 | | SPI0 CSn | UART0 RX | I2C0 SCL | PWM8 B | SIO | PIO0 | PIO1 | PIO2 | | USB OVCUR DET | | - * | 34 | | SPI0 SCK | UART0 CTS | I2C1 SDA | PWM9 A | SIO | PIO0 | PIO1 | PIO2 | | USB VBUS DET | UART0 TX | - * | 35 | | SPI0 TX | UART0 RTS | I2C1 SCL | PWM9 B | SIO | PIO0 | PIO1 | PIO2 | | USB VBUS EN | UART0 RX | - * | 36 | | SPI0 RX | UART1 TX | I2C0 SDA | PWM10 A | SIO | PIO0 | PIO1 | PIO2 | | USB OVCUR DET | | - * | 37 | | SPI0 CSn | UART1 RX | I2C0 SCL | PWM10 B | SIO | PIO0 | PIO1 | PIO2 | | USB VBUS DET | | - * | 38 | | SPI0 SCK | UART1 CTS | I2C1 SDA | PWM11 A | SIO | PIO0 | PIO1 | PIO2 | | USB VBUS EN | UART1 TX | - * | 39 | | SPI0 TX | UART1 RTS | I2C1 SCL | PWM11 B | SIO | PIO0 | PIO1 | PIO2 | | USB OVCUR DET | UART1 RX | - * | 40 | | SPI1 RX | UART1 TX | I2C0 SDA | PWM8 A | SIO | PIO0 | PIO1 | PIO2 | | USB VBUS DET | | - * | 41 | | SPI1 CSn | UART1 RX | I2C0 SCL | PWM8 B | SIO | PIO0 | PIO1 | PIO2 | | USB VBUS EN | | - * | 42 | | SPI1 SCK | UART1 CTS | I2C1 SDA | PWM9 A | SIO | PIO0 | PIO1 | PIO2 | | USB OVCUR DET | UART1 TX | - * | 43 | | SPI1 TX | UART1 RTS | I2C1 SCL | PWM9 B | SIO | PIO0 | PIO1 | PIO2 | | USB VBUS DET | UART1 RX | - * | 44 | | SPI1 RX | UART0 TX | I2C0 SDA | PWM10 A | SIO | PIO0 | PIO1 | PIO2 | | USB VBUS EN | | - * | 45 | | SPI1 CSn | UART0 RX | I2C0 SCL | PWM10 B | SIO | PIO0 | PIO1 | PIO2 | | USB OVCUR DET | | - * | 46 | | SPI1 SCK | UART0 CTS | I2C1 SDA | PWM11 A | SIO | PIO0 | PIO1 | PIO2 | | USB VBUS DET | UART0 TX | - * | 47 | | SPI1 TX | UART0 RTS | I2C1 SCL | PWM11 B | SIO | PIO0 | PIO1 | PIO2 | XIP_CS1n | USB VBUS EN | UART0 RX | - * - * \endif - */ - -enum gpio_dir { - GPIO_OUT = 1u, ///< set GPIO to output - GPIO_IN = 0u, ///< set GPIO to input -}; - -/*! \brief GPIO Interrupt level definitions (GPIO events) - * \ingroup hardware_gpio - * \brief GPIO Interrupt levels - * - * An interrupt can be generated for every GPIO pin in 4 scenarios: - * - * * Level High: the GPIO pin is a logical 1 - * * Level Low: the GPIO pin is a logical 0 - * * Edge High: the GPIO has transitioned from a logical 0 to a logical 1 - * * Edge Low: the GPIO has transitioned from a logical 1 to a logical 0 - * - * The level interrupts are not latched. This means that if the pin is a logical 1 and the level high interrupt is active, it will - * become inactive as soon as the pin changes to a logical 0. The edge interrupts are stored in the INTR register and can be - * cleared by writing to the INTR register. - */ -enum gpio_irq_level { - GPIO_IRQ_LEVEL_LOW = 0x1u, ///< IRQ when the GPIO pin is a logical 0 - GPIO_IRQ_LEVEL_HIGH = 0x2u, ///< IRQ when the GPIO pin is a logical 1 - GPIO_IRQ_EDGE_FALL = 0x4u, ///< IRQ when the GPIO has transitioned from a logical 1 to a logical 0 - GPIO_IRQ_EDGE_RISE = 0x8u, ///< IRQ when the GPIO has transitioned from a logical 0 to a logical 1 -}; - -/*! Callback function type for GPIO events - * \ingroup hardware_gpio - * - * \param gpio Which GPIO caused this interrupt - * \param event_mask Which events caused this interrupt. See \ref gpio_irq_level for details. - * \sa gpio_set_irq_enabled_with_callback() - * \sa gpio_set_irq_callback() - */ -typedef void (*gpio_irq_callback_t)(uint gpio, uint32_t event_mask); - -enum gpio_override { - GPIO_OVERRIDE_NORMAL = 0, ///< peripheral signal selected via \ref gpio_set_function - GPIO_OVERRIDE_INVERT = 1, ///< invert peripheral signal selected via \ref gpio_set_function - GPIO_OVERRIDE_LOW = 2, ///< drive low/disable output - GPIO_OVERRIDE_HIGH = 3, ///< drive high/enable output -}; - -/*! \brief Slew rate limiting levels for GPIO outputs - * \ingroup hardware_gpio - * - * Slew rate limiting increases the minimum rise/fall time when a GPIO output - * is lightly loaded, which can help to reduce electromagnetic emissions. - * \sa gpio_set_slew_rate - */ -enum gpio_slew_rate { - GPIO_SLEW_RATE_SLOW = 0, ///< Slew rate limiting enabled - GPIO_SLEW_RATE_FAST = 1 ///< Slew rate limiting disabled -}; - -/*! \brief Drive strength levels for GPIO outputs - * \ingroup hardware_gpio - * - * Drive strength levels for GPIO outputs. - * \sa gpio_set_drive_strength - */ -enum gpio_drive_strength { - GPIO_DRIVE_STRENGTH_2MA = 0, ///< 2 mA nominal drive strength - GPIO_DRIVE_STRENGTH_4MA = 1, ///< 4 mA nominal drive strength - GPIO_DRIVE_STRENGTH_8MA = 2, ///< 8 mA nominal drive strength - GPIO_DRIVE_STRENGTH_12MA = 3 ///< 12 mA nominal drive strength -}; - -static inline void check_gpio_param(__unused uint gpio) { - invalid_params_if(HARDWARE_GPIO, gpio >= NUM_BANK0_GPIOS); -} - -// ---------------------------------------------------------------------------- -// Pad Controls + IO Muxing -// ---------------------------------------------------------------------------- -// Declarations for gpio.c - -/*! \brief Select GPIO function - * \ingroup hardware_gpio - * - * \param gpio GPIO number - * \param fn Which GPIO function select to use from list \ref gpio_function_t - */ -void gpio_set_function(uint gpio, gpio_function_t fn); - -/*! \brief Select the function for multiple GPIOs - * \ingroup hardware_gpio - * - * \sa gpio_set_function - * \param gpio_mask Mask with 1 bit per GPIO number to set the function for - * \param fn Which GPIO function select to use from list \ref gpio_function_t -*/ -void gpio_set_function_masked(uint32_t gpio_mask, gpio_function_t fn); - -/*! \brief Select the function for multiple GPIOs - * \ingroup hardware_gpio - * - * \sa gpio_set_function - * \param gpio_mask Mask with 1 bit per GPIO number to set the function for - * \param fn Which GPIO function select to use from list \ref gpio_function_t -*/ -void gpio_set_function_masked64(uint64_t gpio_mask, gpio_function_t fn); - -/*! \brief Determine current GPIO function - * \ingroup hardware_gpio - * - * \param gpio GPIO number - * \return Which GPIO function is currently selected from list \ref gpio_function_t - */ -gpio_function_t gpio_get_function(uint gpio); - -/*! \brief Select up and down pulls on specific GPIO - * \ingroup hardware_gpio - * - * \param gpio GPIO number - * \param up If true set a pull up on the GPIO - * \param down If true set a pull down on the GPIO - * - * \note On the RP2040, setting both pulls enables a "bus keep" function, - * i.e. a weak pull to whatever is current high/low state of GPIO. - */ -void gpio_set_pulls(uint gpio, bool up, bool down); - -/*! \brief Set specified GPIO to be pulled up. - * \ingroup hardware_gpio - * - * \param gpio GPIO number - */ -static inline void gpio_pull_up(uint gpio) { - gpio_set_pulls(gpio, true, false); -} - -/*! \brief Determine if the specified GPIO is pulled up. - * \ingroup hardware_gpio - * - * \param gpio GPIO number - * \return true if the GPIO is pulled up - */ -static inline bool gpio_is_pulled_up(uint gpio) { - return (pads_bank0_hw->io[gpio] & PADS_BANK0_GPIO0_PUE_BITS) != 0; -} - -/*! \brief Set specified GPIO to be pulled down. - * \ingroup hardware_gpio - * - * \param gpio GPIO number - */ -static inline void gpio_pull_down(uint gpio) { - gpio_set_pulls(gpio, false, true); -} - -/*! \brief Determine if the specified GPIO is pulled down. - * \ingroup hardware_gpio - * - * \param gpio GPIO number - * \return true if the GPIO is pulled down - */ -static inline bool gpio_is_pulled_down(uint gpio) { - return (pads_bank0_hw->io[gpio] & PADS_BANK0_GPIO0_PDE_BITS) != 0; -} - -/*! \brief Disable pulls on specified GPIO - * \ingroup hardware_gpio - * - * \param gpio GPIO number - */ -static inline void gpio_disable_pulls(uint gpio) { - gpio_set_pulls(gpio, false, false); -} - -/*! \brief Set GPIO IRQ override - * \ingroup hardware_gpio - * - * Optionally invert a GPIO IRQ signal, or drive it high or low - * - * \param gpio GPIO number - * \param value See \ref gpio_override - */ -void gpio_set_irqover(uint gpio, uint value); - -/*! \brief Set GPIO output override - * \ingroup hardware_gpio - * - * \param gpio GPIO number - * \param value See \ref gpio_override - */ -void gpio_set_outover(uint gpio, uint value); - -/*! \brief Select GPIO input override - * \ingroup hardware_gpio - * - * \param gpio GPIO number - * \param value See \ref gpio_override - */ -void gpio_set_inover(uint gpio, uint value); - -/*! \brief Select GPIO output enable override - * \ingroup hardware_gpio - * - * \param gpio GPIO number - * \param value See \ref gpio_override - */ -void gpio_set_oeover(uint gpio, uint value); - -/*! \brief Enable GPIO input - * \ingroup hardware_gpio - * - * \param gpio GPIO number - * \param enabled true to enable input on specified GPIO - */ -void gpio_set_input_enabled(uint gpio, bool enabled); - -/*! \brief Enable/disable GPIO input hysteresis (Schmitt trigger) - * \ingroup hardware_gpio - * - * Enable or disable the Schmitt trigger hysteresis on a given GPIO. This is - * enabled on all GPIOs by default. Disabling input hysteresis can lead to - * inconsistent readings when the input signal has very long rise or fall - * times, but slightly reduces the GPIO's input delay. - * - * \sa gpio_is_input_hysteresis_enabled - * \param gpio GPIO number - * \param enabled true to enable input hysteresis on specified GPIO - */ -void gpio_set_input_hysteresis_enabled(uint gpio, bool enabled); - -/*! \brief Determine whether input hysteresis is enabled on a specified GPIO - * \ingroup hardware_gpio - * - * \sa gpio_set_input_hysteresis_enabled - * \param gpio GPIO number - */ -bool gpio_is_input_hysteresis_enabled(uint gpio); - -/*! \brief Set slew rate for a specified GPIO - * \ingroup hardware_gpio - * - * \sa gpio_get_slew_rate - * \param gpio GPIO number - * \param slew GPIO output slew rate - */ -void gpio_set_slew_rate(uint gpio, enum gpio_slew_rate slew); - -/*! \brief Determine current slew rate for a specified GPIO - * \ingroup hardware_gpio - * - * \sa gpio_set_slew_rate - * \param gpio GPIO number - * \return Current slew rate of that GPIO - */ -enum gpio_slew_rate gpio_get_slew_rate(uint gpio); - -/*! \brief Set drive strength for a specified GPIO - * \ingroup hardware_gpio - * - * \sa gpio_get_drive_strength - * \param gpio GPIO number - * \param drive GPIO output drive strength - */ -void gpio_set_drive_strength(uint gpio, enum gpio_drive_strength drive); - -/*! \brief Determine current drive strength for a specified GPIO - * \ingroup hardware_gpio - * - * \sa gpio_set_drive_strength - * \param gpio GPIO number - * \return Current drive strength of that GPIO - */ -enum gpio_drive_strength gpio_get_drive_strength(uint gpio); - -/*! \brief Enable or disable specific interrupt events for specified GPIO - * \ingroup hardware_gpio - * - * This function sets which GPIO events cause a GPIO interrupt on the calling core. See - * \ref gpio_set_irq_callback, \ref gpio_set_irq_enabled_with_callback and - * \ref gpio_add_raw_irq_handler to set up a GPIO interrupt handler to handle the events. - * - * \note The IO IRQs are independent per-processor. This configures the interrupt events for - * the processor that calls the function. - * - * \param gpio GPIO number - * \param event_mask Which events will cause an interrupt - * \param enabled Enable or disable flag - * - * Events is a bitmask of the following \ref gpio_irq_level values: - * - * bit | constant | interrupt - * ----|---------------------|------------------------------------ - * 0 | GPIO_IRQ_LEVEL_LOW | Continuously while level is low - * 1 | GPIO_IRQ_LEVEL_HIGH | Continuously while level is high - * 2 | GPIO_IRQ_EDGE_FALL | On each transition from high to low - * 3 | GPIO_IRQ_EDGE_RISE | On each transition from low to high - * - * which are specified in \ref gpio_irq_level - */ -void gpio_set_irq_enabled(uint gpio, uint32_t event_mask, bool enabled); - -// PICO_CONFIG: GPIO_IRQ_CALLBACK_ORDER_PRIORITY, IRQ priority order of the default IRQ callback, min=0, max=255, default=PICO_SHARED_IRQ_HANDLER_LOWEST_ORDER_PRIORITY, group=hardware_gpio -#ifndef GPIO_IRQ_CALLBACK_ORDER_PRIORITY -#define GPIO_IRQ_CALLBACK_ORDER_PRIORITY PICO_SHARED_IRQ_HANDLER_LOWEST_ORDER_PRIORITY -#endif - -// PICO_CONFIG: GPIO_RAW_IRQ_HANDLER_DEFAULT_ORDER_PRIORITY, IRQ priority order of raw IRQ handlers if the priority is not specified, min=0, max=255, default=PICO_SHARED_IRQ_HANDLER_DEFAULT_ORDER_PRIORITY, group=hardware_gpio -#ifndef GPIO_RAW_IRQ_HANDLER_DEFAULT_ORDER_PRIORITY -#define GPIO_RAW_IRQ_HANDLER_DEFAULT_ORDER_PRIORITY PICO_SHARED_IRQ_HANDLER_DEFAULT_ORDER_PRIORITY -#endif - -/*! \brief Set the generic callback used for GPIO IRQ events for the current core - * \ingroup hardware_gpio - * - * This function sets the callback used for all GPIO IRQs on the current core that are not explicitly - * hooked via \ref gpio_add_raw_irq_handler or other gpio_add_raw_irq_handler_ functions. - * - * This function is called with the GPIO number and event mask for each of the (not explicitly hooked) - * GPIOs that have events enabled and that are pending (see \ref gpio_get_irq_event_mask). - * - * \note The IO IRQs are independent per-processor. This function affects - * the processor that calls the function. - * - * \param callback default user function to call on GPIO irq. Note only one of these can be set per processor. - */ -void gpio_set_irq_callback(gpio_irq_callback_t callback); - -/*! \brief Convenience function which performs multiple GPIO IRQ related initializations - * \ingroup hardware_gpio - * - * This method is a slightly eclectic mix of initialization, that: - * - * \li Updates whether the specified events for the specified GPIO causes an interrupt on the calling core based - * on the enable flag. - * - * \li Sets the callback handler for the calling core to callback (or clears the handler if the callback is NULL). - * - * \li Enables GPIO IRQs on the current core if enabled is true. - * - * This method is commonly used to perform a one time setup, and following that any additional IRQs/events are enabled - * via \ref gpio_set_irq_enabled. All GPIOs/events added in this way on the same core share the same callback; for multiple - * independent handlers for different GPIOs you should use \ref gpio_add_raw_irq_handler and related functions. - * - * This method is equivalent to: - * - * \code{.c} - * gpio_set_irq_enabled(gpio, event_mask, enabled); - * gpio_set_irq_callback(callback); - * if (enabled) irq_set_enabled(IO_IRQ_BANK0, true); - * \endcode - * - * \note The IO IRQs are independent per-processor. This method affects only the processor that calls the function. - * - * \param gpio GPIO number - * \param event_mask Which events will cause an interrupt. See \ref gpio_irq_level for details. - * \param enabled Enable or disable flag - * \param callback user function to call on GPIO irq. if NULL, the callback is removed - */ -void gpio_set_irq_enabled_with_callback(uint gpio, uint32_t event_mask, bool enabled, gpio_irq_callback_t callback); - -/*! \brief Enable dormant wake up interrupt for specified GPIO and events - * \ingroup hardware_gpio - * - * This configures IRQs to restart the XOSC or ROSC when they are - * disabled in dormant mode - * - * \param gpio GPIO number - * \param event_mask Which events will cause an interrupt. See \ref gpio_irq_level for details. - * \param enabled Enable/disable flag - */ -void gpio_set_dormant_irq_enabled(uint gpio, uint32_t event_mask, bool enabled); - -/*! \brief Return the current interrupt status (pending events) for the given GPIO - * \ingroup hardware_gpio - * - * \param gpio GPIO number - * \return Bitmask of events that are currently pending for the GPIO. See \ref gpio_irq_level for details. - * \sa gpio_acknowledge_irq - */ -static inline uint32_t gpio_get_irq_event_mask(uint gpio) { - check_gpio_param(gpio); - io_bank0_irq_ctrl_hw_t *irq_ctrl_base = get_core_num() ? - &io_bank0_hw->proc1_irq_ctrl : &io_bank0_hw->proc0_irq_ctrl; - io_ro_32 *status_reg = &irq_ctrl_base->ints[gpio >> 3u]; - return (*status_reg >> (4 * (gpio & 7u))) & 0xfu; -} - -/*! \brief Acknowledge a GPIO interrupt for the specified events on the calling core - * \ingroup hardware_gpio - * - * \note This may be called with a mask of any of valid bits specified in \ref gpio_irq_level, however - * it has no effect on \a level sensitive interrupts which remain pending while the GPIO is at the specified - * level. When handling \a level sensitive interrupts, you should generally disable the interrupt (see - * \ref gpio_set_irq_enabled) and then set it up again later once the GPIO level has changed (or to catch - * the opposite level). - * - * \param gpio GPIO number - * - * \note For callbacks set with \ref gpio_set_irq_enabled_with_callback, or \ref gpio_set_irq_callback, this function is called automatically. - * \param event_mask Bitmask of events to clear. See \ref gpio_irq_level for details. - */ -void gpio_acknowledge_irq(uint gpio, uint32_t event_mask); - -/*! \brief Adds a raw GPIO IRQ handler for the specified GPIOs on the current core - * \ingroup hardware_gpio - * - * In addition to the default mechanism of a single GPIO IRQ event callback per core (see \ref gpio_set_irq_callback), - * it is possible to add explicit GPIO IRQ handlers which are called independent of the default callback. The order - * relative to the default callback can be controlled via the order_priority parameter (the default callback has the priority - * \ref GPIO_IRQ_CALLBACK_ORDER_PRIORITY which defaults to the lowest priority with the intention of it running last). - * - * This method adds such an explicit GPIO IRQ handler, and disables the "default" callback for the specified GPIOs. - * - * \note Multiple raw handlers should not be added for the same GPIOs, and this method will assert if you attempt to. - * Internally, this function calls \ref irq_add_shared_handler, which will assert if the maximum number of shared handlers - * (configurable via PICO_MAX_IRQ_SHARED_HANDLERS) would be exceeded. - * - * A raw handler should check for whichever GPIOs and events it handles, and acknowledge them itself; it might look something like: - * - * \code{.c} - * void my_irq_handler(void) { - * if (gpio_get_irq_event_mask(my_gpio_num) & my_gpio_event_mask) { - * gpio_acknowledge_irq(my_gpio_num, my_gpio_event_mask); - * // handle the IRQ - * } - * if (gpio_get_irq_event_mask(my_gpio_num2) & my_gpio_event_mask2) { - * gpio_acknowledge_irq(my_gpio_num2, my_gpio_event_mask2); - * // handle the IRQ - * } - * } - * \endcode - * - * @param gpio_mask a bit mask of the GPIO numbers that will no longer be passed to the default callback for this core - * @param handler the handler to add to the list of GPIO IRQ handlers for this core - * @param order_priority the priority order to determine the relative position of the handler in the list of GPIO IRQ handlers for this core. - */ -void gpio_add_raw_irq_handler_with_order_priority_masked(uint32_t gpio_mask, irq_handler_t handler, uint8_t order_priority); - -/*! \brief Adds a raw GPIO IRQ handler for the specified GPIOs on the current core - * \ingroup hardware_gpio - * - * In addition to the default mechanism of a single GPIO IRQ event callback per core (see \ref gpio_set_irq_callback), - * it is possible to add explicit GPIO IRQ handlers which are called independent of the default callback. The order - * relative to the default callback can be controlled via the order_priority parameter (the default callback has the priority - * \ref GPIO_IRQ_CALLBACK_ORDER_PRIORITY which defaults to the lowest priority with the intention of it running last). - * - * This method adds such an explicit GPIO IRQ handler, and disables the "default" callback for the specified GPIOs. - * - * \note Multiple raw handlers should not be added for the same GPIOs, and this method will assert if you attempt to. - * Internally, this function calls \ref irq_add_shared_handler, which will assert if the maximum number of shared handlers - * (configurable via PICO_MAX_IRQ_SHARED_HANDLERS) would be exceeded. - * - * A raw handler should check for whichever GPIOs and events it handles, and acknowledge them itself; it might look something like: - * - * \code{.c} - * void my_irq_handler(void) { - * if (gpio_get_irq_event_mask(my_gpio_num) & my_gpio_event_mask) { - * gpio_acknowledge_irq(my_gpio_num, my_gpio_event_mask); - * // handle the IRQ - * } - * if (gpio_get_irq_event_mask(my_gpio_num2) & my_gpio_event_mask2) { - * gpio_acknowledge_irq(my_gpio_num2, my_gpio_event_mask2); - * // handle the IRQ - * } - * } - * \endcode - * - * @param gpio_mask a bit mask of the GPIO numbers that will no longer be passed to the default callback for this core - * @param handler the handler to add to the list of GPIO IRQ handlers for this core - * @param order_priority the priority order to determine the relative position of the handler in the list of GPIO IRQ handlers for this core. - */ -void gpio_add_raw_irq_handler_with_order_priority_masked64(uint64_t gpio_mask, irq_handler_t handler, uint8_t order_priority); - -/*! \brief Adds a raw GPIO IRQ handler for a specific GPIO on the current core - * \ingroup hardware_gpio - * - * In addition to the default mechanism of a single GPIO IRQ event callback per core (see \ref gpio_set_irq_callback), - * it is possible to add explicit GPIO IRQ handlers which are called independent of the default callback. The order - * relative to the default callback can be controlled via the order_priority parameter(the default callback has the priority - * \ref GPIO_IRQ_CALLBACK_ORDER_PRIORITY which defaults to the lowest priority with the intention of it running last). - * - * This method adds such a callback, and disables the "default" callback for the specified GPIO. - * - * \note Multiple raw handlers should not be added for the same GPIO, and this method will assert if you attempt to. - * Internally, this function calls \ref irq_add_shared_handler, which will assert if the maximum number of shared handlers - * (configurable via PICO_MAX_IRQ_SHARED_HANDLERS) would be exceeded. - * - * A raw handler should check for whichever GPIOs and events it handles, and acknowledge them itself; it might look something like: - * - * \code{.c} - * void my_irq_handler(void) { - * if (gpio_get_irq_event_mask(my_gpio_num) & my_gpio_event_mask) { - * gpio_acknowledge_irq(my_gpio_num, my_gpio_event_mask); - * // handle the IRQ - * } - * } - * \endcode - * - * @param gpio the GPIO number that will no longer be passed to the default callback for this core - * @param handler the handler to add to the list of GPIO IRQ handlers for this core - * @param order_priority the priority order to determine the relative position of the handler in the list of GPIO IRQ handlers for this core. - */ -static inline void gpio_add_raw_irq_handler_with_order_priority(uint gpio, irq_handler_t handler, uint8_t order_priority) { - check_gpio_param(gpio); -#if NUM_BANK0_GPIOS > 32 - gpio_add_raw_irq_handler_with_order_priority_masked64(1ull << gpio, handler, order_priority); -#else - gpio_add_raw_irq_handler_with_order_priority_masked(1u << gpio, handler, order_priority); -#endif -} - -/*! \brief Adds a raw GPIO IRQ handler for the specified GPIOs on the current core - * \ingroup hardware_gpio - * - * In addition to the default mechanism of a single GPIO IRQ event callback per core (see \ref gpio_set_irq_callback), - * it is possible to add explicit GPIO IRQ handlers which are called independent of the default event callback. - * - * This method adds such a callback, and disables the "default" callback for the specified GPIOs. - * - * \note Multiple raw handlers should not be added for the same GPIOs, and this method will assert if you attempt to. - * Internally, this function calls \ref irq_add_shared_handler, which will assert if the maximum number of shared handlers - * (configurable via PICO_MAX_IRQ_SHARED_HANDLERS) would be exceeded. - * - * A raw handler should check for whichever GPIOs and events it handles, and acknowledge them itself; it might look something like: - * - * \code{.c} - * void my_irq_handler(void) { - * if (gpio_get_irq_event_mask(my_gpio_num) & my_gpio_event_mask) { - * gpio_acknowledge_irq(my_gpio_num, my_gpio_event_mask); - * // handle the IRQ - * } - * if (gpio_get_irq_event_mask(my_gpio_num2) & my_gpio_event_mask2) { - * gpio_acknowledge_irq(my_gpio_num2, my_gpio_event_mask2); - * // handle the IRQ - * } - * } - * \endcode - * - * @param gpio_mask a bit mask of the GPIO numbers that will no longer be passed to the default callback for this core - * @param handler the handler to add to the list of GPIO IRQ handlers for this core - */ -void gpio_add_raw_irq_handler_masked(uint32_t gpio_mask, irq_handler_t handler); - -/*! \brief Adds a raw GPIO IRQ handler for the specified GPIOs on the current core - * \ingroup hardware_gpio - * - * In addition to the default mechanism of a single GPIO IRQ event callback per core (see \ref gpio_set_irq_callback), - * it is possible to add explicit GPIO IRQ handlers which are called independent of the default event callback. - * - * This method adds such a callback, and disables the "default" callback for the specified GPIOs. - * - * \note Multiple raw handlers should not be added for the same GPIOs, and this method will assert if you attempt to. - * Internally, this function calls \ref irq_add_shared_handler, which will assert if the maximum number of shared handlers - * (configurable via PICO_MAX_IRQ_SHARED_HANDLERS) would be exceeded. - * - * A raw handler should check for whichever GPIOs and events it handles, and acknowledge them itself; it might look something like: - * - * \code{.c} - * void my_irq_handler(void) { - * if (gpio_get_irq_event_mask(my_gpio_num) & my_gpio_event_mask) { - * gpio_acknowledge_irq(my_gpio_num, my_gpio_event_mask); - * // handle the IRQ - * } - * if (gpio_get_irq_event_mask(my_gpio_num2) & my_gpio_event_mask2) { - * gpio_acknowledge_irq(my_gpio_num2, my_gpio_event_mask2); - * // handle the IRQ - * } - * } - * \endcode - * - * @param gpio_mask a 64 bit mask of the GPIO numbers that will no longer be passed to the default callback for this core - * @param handler the handler to add to the list of GPIO IRQ handlers for this core - */ -void gpio_add_raw_irq_handler_masked64(uint64_t gpio_mask, irq_handler_t handler); - -/*! \brief Adds a raw GPIO IRQ handler for a specific GPIO on the current core - * \ingroup hardware_gpio - * - * In addition to the default mechanism of a single GPIO IRQ event callback per core (see \ref gpio_set_irq_callback), - * it is possible to add explicit GPIO IRQ handlers which are called independent of the default event callback. - * - * This method adds such a callback, and disables the "default" callback for the specified GPIO. - * - * \note Multiple raw handlers should not be added for the same GPIO, and this method will assert if you attempt to. - * Internally, this function calls \ref irq_add_shared_handler, which will assert if the maximum number of shared handlers - * (configurable via PICO_MAX_IRQ_SHARED_HANDLERS) would be exceeded. - * - * A raw handler should check for whichever GPIOs and events it handles, and acknowledge them itself; it might look something like: - * - * \code{.c} - * void my_irq_handler(void) { - * if (gpio_get_irq_event_mask(my_gpio_num) & my_gpio_event_mask) { - * gpio_acknowledge_irq(my_gpio_num, my_gpio_event_mask); - * // handle the IRQ - * } - * } - * \endcode - * - * @param gpio the GPIO number that will no longer be passed to the default callback for this core - * @param handler the handler to add to the list of GPIO IRQ handlers for this core - */ -static inline void gpio_add_raw_irq_handler(uint gpio, irq_handler_t handler) { - check_gpio_param(gpio); -#if NUM_BANK0_GPIOS > 32 - gpio_add_raw_irq_handler_masked64(1ull << gpio, handler); -#else - gpio_add_raw_irq_handler_masked(1u << gpio, handler); -#endif -} - -/*! \brief Removes a raw GPIO IRQ handler for the specified GPIOs on the current core - * \ingroup hardware_gpio - * - * In addition to the default mechanism of a single GPIO IRQ event callback per core (see \ref gpio_set_irq_callback), - * it is possible to add explicit GPIO IRQ handlers which are called independent of the default event callback. - * - * This method removes such a callback, and enables the "default" callback for the specified GPIOs. - * - * @param gpio_mask a bit mask of the GPIO numbers that will now be passed to the default callback for this core - * @param handler the handler to remove from the list of GPIO IRQ handlers for this core - */ -void gpio_remove_raw_irq_handler_masked(uint32_t gpio_mask, irq_handler_t handler); - -/*! \brief Removes a raw GPIO IRQ handler for the specified GPIOs on the current core - * \ingroup hardware_gpio - * - * In addition to the default mechanism of a single GPIO IRQ event callback per core (see \ref gpio_set_irq_callback), - * it is possible to add explicit GPIO IRQ handlers which are called independent of the default event callback. - * - * This method removes such a callback, and enables the "default" callback for the specified GPIOs. - * - * @param gpio_mask a bit mask of the GPIO numbers that will now be passed to the default callback for this core - * @param handler the handler to remove from the list of GPIO IRQ handlers for this core - */ -void gpio_remove_raw_irq_handler_masked64(uint64_t gpio_mask, irq_handler_t handler); - -/*! \brief Removes a raw GPIO IRQ handler for the specified GPIO on the current core - * \ingroup hardware_gpio - * - * In addition to the default mechanism of a single GPIO IRQ event callback per core (see \ref gpio_set_irq_callback), - * it is possible to add explicit GPIO IRQ handlers which are called independent of the default event callback. - * - * This method removes such a callback, and enables the "default" callback for the specified GPIO. - * - * @param gpio the GPIO number that will now be passed to the default callback for this core - * @param handler the handler to remove from the list of GPIO IRQ handlers for this core - */ -static inline void gpio_remove_raw_irq_handler(uint gpio, irq_handler_t handler) { - check_gpio_param(gpio); -#if NUM_BANK0_GPIOS > 32 - gpio_remove_raw_irq_handler_masked64(1ull << gpio, handler); -#else - gpio_remove_raw_irq_handler_masked(1u << gpio, handler); -#endif -} - -/*! \brief Initialise a GPIO for (enabled I/O and set func to GPIO_FUNC_SIO) - * \ingroup hardware_gpio - * - * Clear the output enable (i.e. set to input). - * Clear any output value. - * - * \param gpio GPIO number - */ -void gpio_init(uint gpio); - -/*! \brief Resets a GPIO back to the NULL function, i.e. disables it. - * \ingroup hardware_gpio - * - * \param gpio GPIO number - */ -void gpio_deinit(uint gpio); - -/*! \brief Initialise multiple GPIOs (enabled I/O and set func to GPIO_FUNC_SIO) - * \ingroup hardware_gpio - * - * Clear the output enable (i.e. set to input). - * Clear any output value. - * - * \param gpio_mask Mask with 1 bit per GPIO number to initialize - */ -void gpio_init_mask(uint gpio_mask); -// ---------------------------------------------------------------------------- -// Input -// ---------------------------------------------------------------------------- - -/*! \brief Get state of a single specified GPIO - * \ingroup hardware_gpio - * - * \param gpio GPIO number - * \return Current state of the GPIO. 0 for low, non-zero for high - */ -static inline bool gpio_get(uint gpio) { -#if NUM_BANK0_GPIOS <= 32 - return sio_hw->gpio_in & (1u << gpio); -#else - if (gpio < 32) { - return sio_hw->gpio_in & (1u << gpio); - } else { - return sio_hw->gpio_hi_in & (1u << (gpio - 32)); - } -#endif -} - -/*! \brief Get raw value of all GPIOs - * \ingroup hardware_gpio - * - * \return Bitmask of raw GPIO values - */ -static inline uint32_t gpio_get_all(void) { -#if PICO_USE_GPIO_COPROCESSOR - return gpioc_lo_in_get(); -#else - return sio_hw->gpio_in; -#endif -} - -/*! \brief Get raw value of all GPIOs - * \ingroup hardware_gpio - * - * \return Bitmask of raw GPIO values - */ -static inline uint64_t gpio_get_all64(void) { -#if PICO_USE_GPIO_COPROCESSOR - return gpioc_hilo_in_get(); -#elif NUM_BANK0_GPIOS <= 32 - return sio_hw->gpio_in; -#else - return sio_hw->gpio_in | (((uint64_t)sio_hw->gpio_hi_in) << 32u); -#endif -} - -// ---------------------------------------------------------------------------- -// Output -// ---------------------------------------------------------------------------- - -/*! \brief Drive high every GPIO appearing in mask - * \ingroup hardware_gpio - * - * \param mask Bitmask of GPIO values to set - */ -static inline void gpio_set_mask(uint32_t mask) { -#if PICO_USE_GPIO_COPROCESSOR - gpioc_lo_out_set(mask); -#else - sio_hw->gpio_set = mask; -#endif -} - -/*! \brief Drive high every GPIO appearing in mask - * \ingroup hardware_gpio - * - * \param mask Bitmask of GPIO values to set - */ -static inline void gpio_set_mask64(uint64_t mask) { -#if PICO_USE_GPIO_COPROCESSOR - gpioc_hilo_out_set(mask); -#elif NUM_BANK0_GPIOS <= 32 - sio_hw->gpio_set = (uint32_t)mask; -#else - sio_hw->gpio_set = (uint32_t)mask; - sio_hw->gpio_hi_set = (uint32_t)(mask >> 32u); -#endif -} - -/*! \brief Drive high every GPIO appearing in mask - * \ingroup hardware_gpio - * - * \param n the base GPIO index of the mask to update. n == 0 means 0->31, n == 1 mean 32->63 etc. - * \param mask Bitmask of 32 GPIO values to set - */ -static inline void gpio_set_mask_n(uint n, uint32_t mask) { - if (!n) { - gpio_set_mask(mask); - } else if (n == 1) { -#if PICO_USE_GPIO_COPROCESSOR - gpioc_hi_out_set(mask); -#elif NUM_BANK0_GPIOS >= 32 - sio_hw->gpio_hi_set = mask; -#endif - } -} - -/*! \brief Drive low every GPIO appearing in mask - * \ingroup hardware_gpio - * - * \param mask Bitmask of GPIO values to clear - */ -static inline void gpio_clr_mask(uint32_t mask) { -#if PICO_USE_GPIO_COPROCESSOR - gpioc_lo_out_clr(mask); -#else - sio_hw->gpio_clr = mask; -#endif -} - -/*! \brief Drive low every GPIO appearing in mask -* \ingroup hardware_gpio -* -* \param mask Bitmask of GPIO values to clear -*/ -static inline void gpio_clr_mask64(uint64_t mask) { -#if PICO_USE_GPIO_COPROCESSOR - gpioc_hilo_out_clr(mask); -#elif NUM_BANK0_GPIOS <= 32 - sio_hw->gpio_clr = (uint32_t)mask; -#else - sio_hw->gpio_clr = (uint32_t)mask; - sio_hw->gpio_hi_clr = (uint32_t)(mask >> 32u); -#endif -} - - -/*! \brief Drive low every GPIO appearing in mask - * \ingroup hardware_gpio - * - * \param n the base GPIO index of the mask to update. n == 0 means 0->31, n == 1 mean 32->63 etc. - * \param mask Bitmask of 32 GPIO values to clear - */ -static inline void gpio_clr_mask_n(uint n, uint32_t mask) { - if (!n) { - gpio_clr_mask(mask); - } else if (n == 1) { -#if PICO_USE_GPIO_COPROCESSOR - gpioc_hi_out_clr(mask); -#elif NUM_BANK0_GPIOS >= 32 - sio_hw->gpio_hi_clr = mask; -#endif - } -} - -/*! \brief Toggle every GPIO appearing in mask - * \ingroup hardware_gpio - * - * \param mask Bitmask of GPIO values to toggle - */ -static inline void gpio_xor_mask(uint32_t mask) { -#if PICO_USE_GPIO_COPROCESSOR - gpioc_lo_out_xor(mask); -#else - sio_hw->gpio_togl = mask; -#endif -} - -/*! \brief Toggle every GPIO appearing in mask - * \ingroup hardware_gpio - * - * \param mask Bitmask of GPIO values to toggle - */ -static inline void gpio_xor_mask64(uint64_t mask) { -#if PICO_USE_GPIO_COPROCESSOR - gpioc_hilo_out_xor(mask); -#elif NUM_BANK0_GPIOS <= 32 - sio_hw->gpio_togl = (uint32_t)mask; -#else - sio_hw->gpio_togl = (uint32_t)mask; - sio_hw->gpio_hi_togl = (uint32_t)(mask >> 32u); -#endif -} - -/*! \brief Toggle every GPIO appearing in mask - * \ingroup hardware_gpio - * - * \param n the base GPIO index of the mask to update. n == 0 means 0->31, n == 1 mean 32->63 etc. - * \param mask Bitmask of 32 GPIO values to toggle - */ -static inline void gpio_xor_mask_n(uint n, uint32_t mask) { - if (!n) { - gpio_xor_mask(mask); - } else if (n == 1) { -#if PICO_USE_GPIO_COPROCESSOR - gpioc_hi_out_xor(mask); -#elif NUM_BANK0_GPIOS >= 32 - sio_hw->gpio_hi_togl = mask; -#endif - } -} - -/*! \brief Drive GPIOs high/low depending on parameters - * \ingroup hardware_gpio - * - * \param mask Bitmask of GPIO values to change - * \param value Value to set - * - * For each 1 bit in \p mask, drive that pin to the value given by - * corresponding bit in \p value, leaving other pins unchanged. - * Since this uses the TOGL alias, it is concurrency-safe with e.g. an IRQ - * bashing different pins from the same core. - */ -static inline void gpio_put_masked(uint32_t mask, uint32_t value) { -#if PICO_USE_GPIO_COPROCESSOR - gpioc_lo_out_xor((gpioc_lo_out_get() ^ value) & mask); -#else - sio_hw->gpio_togl = (sio_hw->gpio_out ^ value) & mask; -#endif -} - -/*! \brief Drive GPIOs high/low depending on parameters - * \ingroup hardware_gpio - * - * \param mask Bitmask of GPIO values to change - * \param value Value to set - * - * For each 1 bit in \p mask, drive that pin to the value given by - * corresponding bit in \p value, leaving other pins unchanged. - * Since this uses the TOGL alias, it is concurrency-safe with e.g. an IRQ - * bashing different pins from the same core. - */ -static inline void gpio_put_masked64(uint64_t mask, uint64_t value) { -#if PICO_USE_GPIO_COPROCESSOR - gpioc_hilo_out_xor((gpioc_hilo_out_get() ^ value) & mask); -#elif NUM_BANK0_GPIOS <= 32 - sio_hw->gpio_togl = (sio_hw->gpio_out ^ (uint32_t)value) & (uint32_t)mask; -#else - sio_hw->gpio_togl = (sio_hw->gpio_out ^ (uint32_t)value) & (uint32_t)mask; - sio_hw->gpio_hi_togl = (sio_hw->gpio_hi_out ^ (uint32_t)(value>>32u)) & (uint32_t)(mask>>32u); -#endif -} - -/*! \brief Drive GPIOs high/low depending on parameters - * \ingroup hardware_gpio - * - * \param n the base GPIO index of the mask to update. n == 0 means 0->31, n == 1 mean 32->63 etc. - * \param mask Bitmask of GPIO values to change - * \param value Value to set - * - * For each 1 bit in \p mask, drive that pin to the value given by - * corresponding bit in \p value, leaving other pins unchanged. - * Since this uses the TOGL alias, it is concurrency-safe with e.g. an IRQ - * bashing different pins from the same core. - */ -static inline void gpio_put_masked_n(uint n, uint32_t mask, uint32_t value) { - if (!n) { - gpio_put_masked(mask, value); - } else if (n == 1) { -#if PICO_USE_GPIO_COPROCESSOR - gpioc_hi_out_xor((gpioc_hi_out_get() ^ value) & mask); -#else - sio_hw->gpio_hi_togl = (sio_hw->gpio_hi_out ^ value) & mask; -#endif - } -} - -/*! \brief Drive all pins simultaneously - * \ingroup hardware_gpio - * - * \param value Bitmask of GPIO values to change - */ -static inline void gpio_put_all(uint32_t value) { -#if PICO_USE_GPIO_COPROCESSOR - gpioc_lo_out_put(value); -#else - sio_hw->gpio_out = value; -#endif -} - -/*! \brief Drive all pins simultaneously - * \ingroup hardware_gpio - * - * \param value Bitmask of GPIO values to change - */ -static inline void gpio_put_all64(uint64_t value) { -#if PICO_USE_GPIO_COPROCESSOR - gpioc_hilo_out_put(value); -#elif NUM_BANK0_GPIOS <= 32 - sio_hw->gpio_out = (uint32_t)value; -#else - sio_hw->gpio_out = (uint32_t)value; - sio_hw->gpio_hi_out = (uint32_t)(value >> 32u); -#endif -} - -/*! \brief Drive a single GPIO high/low - * \ingroup hardware_gpio - * - * \param gpio GPIO number - * \param value If false clear the GPIO, otherwise set it. - */ -static inline void gpio_put(uint gpio, bool value) { -#if PICO_USE_GPIO_COPROCESSOR - gpioc_bit_out_put(gpio, value); -#elif NUM_BANK0_GPIOS <= 32 - uint32_t mask = 1ul << gpio; - if (value) - gpio_set_mask(mask); - else - gpio_clr_mask(mask); -#else - uint32_t mask = 1ul << (gpio & 0x1fu); - if (gpio < 32) { - if (value) { - sio_hw->gpio_set = mask; - } else { - sio_hw->gpio_clr = mask; - } - } else { - if (value) { - sio_hw->gpio_hi_set = mask; - } else { - sio_hw->gpio_hi_clr = mask; - } - } -#endif -} - -/*! \brief Determine whether a GPIO is currently driven high or low - * \ingroup hardware_gpio - * - * This function returns the high/low output level most recently assigned to a - * GPIO via gpio_put() or similar. This is the value that is presented outward - * to the IO muxing, *not* the input level back from the pad (which can be - * read using gpio_get()). - * - * To avoid races, this function must not be used for read-modify-write - * sequences when driving GPIOs -- instead functions like gpio_put() should be - * used to atomically update GPIOs. This accessor is intended for debug use - * only. - * - * \param gpio GPIO number - * \return true if the GPIO output level is high, false if low. - */ -static inline bool gpio_get_out_level(uint gpio) { -#if NUM_BANK0_GPIOS <= 32 - return sio_hw->gpio_out & (1u << gpio); -#else - uint32_t bits = gpio < 32 ? sio_hw->gpio_out : sio_hw->gpio_hi_out; - return bits & (1u << (gpio & 0x1fu)); -#endif -} - -// ---------------------------------------------------------------------------- -// Direction -// ---------------------------------------------------------------------------- - -/*! \brief Set a number of GPIOs to output - * \ingroup hardware_gpio - * - * Switch all GPIOs in "mask" to output - * - * \param mask Bitmask of GPIO to set to output - */ -static inline void gpio_set_dir_out_masked(uint32_t mask) { -#if PICO_USE_GPIO_COPROCESSOR - gpioc_lo_oe_set(mask); -#else - sio_hw->gpio_oe_set = mask; -#endif -} - -/*! \brief Set a number of GPIOs to output - * \ingroup hardware_gpio - * - * Switch all GPIOs in "mask" to output - * - * \param mask Bitmask of GPIO to set to output - */ -static inline void gpio_set_dir_out_masked64(uint64_t mask) { -#if PICO_USE_GPIO_COPROCESSOR - gpioc_hilo_oe_set(mask); -#elif NUM_BANK0_GPIOS <= 32 - sio_hw->gpio_oe_set = mask; -#else - sio_hw->gpio_oe_set = (uint32_t)mask; - sio_hw->gpio_hi_oe_set = (uint32_t)(mask >> 32u); -#endif -} - -/*! \brief Set a number of GPIOs to input - * \ingroup hardware_gpio - * - * \param mask Bitmask of GPIO to set to input - */ -static inline void gpio_set_dir_in_masked(uint32_t mask) { -#if PICO_USE_GPIO_COPROCESSOR - gpioc_lo_oe_clr(mask); -#else - sio_hw->gpio_oe_clr = mask; -#endif -} - -/*! \brief Set a number of GPIOs to input - * \ingroup hardware_gpio - * - * \param mask Bitmask of GPIO to set to input - */ -static inline void gpio_set_dir_in_masked64(uint64_t mask) { -#if PICO_USE_GPIO_COPROCESSOR - gpioc_hilo_oe_clr(mask); -#elif NUM_BANK0_GPIOS <= 32 - sio_hw->gpio_oe_clr = mask; -#else - sio_hw->gpio_oe_clr = (uint32_t)mask; - sio_hw->gpio_hi_oe_clr = (uint32_t)(mask >> 32u); -#endif -} - -/*! \brief Set multiple GPIO directions - * \ingroup hardware_gpio - * - * \param mask Bitmask of GPIO to set to input, as bits 0-29 - * \param value Values to set - * - * For each 1 bit in "mask", switch that pin to the direction given by - * corresponding bit in "value", leaving other pins unchanged. - * E.g. gpio_set_dir_masked(0x3, 0x2); -> set pin 0 to input, pin 1 to output, - * simultaneously. - */ -static inline void gpio_set_dir_masked(uint32_t mask, uint32_t value) { -#if PICO_USE_GPIO_COPROCESSOR - gpioc_lo_oe_xor((gpioc_lo_oe_get() ^ value) & mask); -#else - sio_hw->gpio_oe_togl = (sio_hw->gpio_oe ^ value) & mask; -#endif -} - -/*! \brief Set multiple GPIO directions - * \ingroup hardware_gpio - * - * \param mask Bitmask of GPIO to set to input, as bits 0-29 - * \param value Values to set - * - * For each 1 bit in "mask", switch that pin to the direction given by - * corresponding bit in "value", leaving other pins unchanged. - * E.g. gpio_set_dir_masked(0x3, 0x2); -> set pin 0 to input, pin 1 to output, - * simultaneously. - */ -static inline void gpio_set_dir_masked64(uint64_t mask, uint64_t value) { -#if PICO_USE_GPIO_COPROCESSOR - gpioc_hilo_oe_xor((gpioc_hilo_oe_get() ^ value) & mask); -#elif NUM_BANK0_GPIOS <= 32 - sio_hw->gpio_oe_togl = (sio_hw->gpio_oe ^ (uint32_t)value) & (uint32_t)mask; -#else - sio_hw->gpio_oe_togl = (sio_hw->gpio_oe ^ (uint32_t)value) & (uint32_t)mask; - sio_hw->gpio_hi_oe_togl = (sio_hw->gpio_hi_oe ^ (uint32_t)(value >> 32u)) & (uint32_t)(mask >> 32u); -#endif -} - - -/*! \brief Set direction of all pins simultaneously. - * \ingroup hardware_gpio - * - * \param values individual settings for each gpio; for GPIO N, bit N is 1 for out, 0 for in - */ -static inline void gpio_set_dir_all_bits(uint32_t values) { -#if PICO_USE_GPIO_COPROCESSOR - gpioc_lo_oe_put(values); -#else - sio_hw->gpio_oe = values; -#endif -} - -/*! \brief Set direction of all pins simultaneously. - * \ingroup hardware_gpio - * - * \param values individual settings for each gpio; for GPIO N, bit N is 1 for out, 0 for in - */ -static inline void gpio_set_dir_all_bits64(uint64_t values) { -#if PICO_USE_GPIO_COPROCESSOR - gpioc_hilo_oe_put(values); -#elif NUM_BANK0_GPIOS <= 32 - sio_hw->gpio_oe = (uint32_t)values; -#else - sio_hw->gpio_oe = (uint32_t)values; - sio_hw->gpio_hi_oe = (uint32_t)(values >> 32u); -#endif -} - -/*! \brief Set a single GPIO direction - * \ingroup hardware_gpio - * - * \param gpio GPIO number - * \param out true for out, false for in - */ -static inline void gpio_set_dir(uint gpio, bool out) { -#if PICO_USE_GPIO_COPROCESSOR - gpioc_bit_oe_put(gpio, out); -#elif PICO_RP2040 || NUM_BANK0_GPIOS <= 32 - uint32_t mask = 1ul << gpio; - if (out) - gpio_set_dir_out_masked(mask); - else - gpio_set_dir_in_masked(mask); -#else - uint32_t mask = 1u << (gpio & 0x1fu); - if (gpio < 32) { - if (out) { - sio_hw->gpio_oe_set = mask; - } else { - sio_hw->gpio_oe_clr = mask; - } - } else { - if (out) { - sio_hw->gpio_hi_oe_set = mask; - } else { - sio_hw->gpio_hi_oe_clr = mask; - } - } -#endif -} - -/*! \brief Check if a specific GPIO direction is OUT - * \ingroup hardware_gpio - * - * \param gpio GPIO number - * \return true if the direction for the pin is OUT - */ -static inline bool gpio_is_dir_out(uint gpio) { -#if NUM_BANK0_GPIOS <= 32 - return sio_hw->gpio_oe & (1u << (gpio)); -#else - uint32_t bits = gpio < 32 ? sio_hw->gpio_oe : sio_hw->gpio_hi_oe; - return bits & (1u << (gpio & 0x1fu)); -#endif -} - -/*! \brief Get a specific GPIO direction - * \ingroup hardware_gpio - * - * \param gpio GPIO number - * \return 1 for out, 0 for in - */ -static inline uint gpio_get_dir(uint gpio) { - return gpio_is_dir_out(gpio); // note GPIO_OUT is 1/true and GPIO_IN is 0/false anyway -} - -#if PICO_SECURE -static inline void gpio_assign_to_ns(uint gpio, bool ns) { - check_gpio_param(gpio); - if (ns) hw_set_bits(&accessctrl_hw->gpio_nsmask[gpio/32], 1u << (gpio & 0x1fu)); - else hw_clear_bits(&accessctrl_hw->gpio_nsmask[gpio/32], 1u << (gpio & 0x1fu)); -} -#endif -extern void gpio_debug_pins_init(void); - -#ifdef __cplusplus -} -#endif - - -// PICO_CONFIG: PICO_DEBUG_PIN_BASE, First pin to use for debug output (if enabled), min=0, max=28, default=19, group=hardware_gpio -#ifndef PICO_DEBUG_PIN_BASE -#define PICO_DEBUG_PIN_BASE 19u -#endif - -// PICO_CONFIG: PICO_DEBUG_PIN_COUNT, Number of pins to use for debug output (if enabled), min=1, max=28, default=3, group=hardware_gpio -#ifndef PICO_DEBUG_PIN_COUNT -#define PICO_DEBUG_PIN_COUNT 3u -#endif - -#ifndef __cplusplus -// note these two macros may only be used once per and only apply per compilation unit (hence the CU_) -#define CU_REGISTER_DEBUG_PINS(...) enum __unused DEBUG_PIN_TYPE { _none = 0, __VA_ARGS__ }; static enum DEBUG_PIN_TYPE __selected_debug_pins; -#define CU_SELECT_DEBUG_PINS(x) static enum DEBUG_PIN_TYPE __selected_debug_pins = (x); -#define DEBUG_PINS_ENABLED(p) (__selected_debug_pins == (p)) -#else -#define CU_REGISTER_DEBUG_PINS(p...) \ - enum DEBUG_PIN_TYPE { _none = 0, p }; \ - template class __debug_pin_settings { \ - public: \ - static inline bool enabled() { return false; } \ - }; -#define CU_SELECT_DEBUG_PINS(x) template<> inline bool __debug_pin_settings::enabled() { return true; }; -#define DEBUG_PINS_ENABLED(p) (__debug_pin_settings

::enabled()) -#endif -#define DEBUG_PINS_SET(p, v) if (DEBUG_PINS_ENABLED(p)) gpio_set_mask((unsigned)(v)<gpio_out = x; -__force_inline static void gpioc_lo_out_put(uint32_t x) { - pico_default_asm_volatile ("mcr p0, #0, %0, c0, c0" : : "r" (x)); -} - -// Equivalent to sio_hw->gpio_togl = x; -__force_inline static void gpioc_lo_out_xor(uint32_t x) { - pico_default_asm_volatile ("mcr p0, #1, %0, c0, c0" : : "r" (x)); -} - -// Equivalent to sio_hw->gpio_set = x; -__force_inline static void gpioc_lo_out_set(uint32_t x) { - pico_default_asm_volatile ("mcr p0, #2, %0, c0, c0" : : "r" (x)); -} - -// Equivalent to sio_hw->gpio_clr = x; -__force_inline static void gpioc_lo_out_clr(uint32_t x) { - pico_default_asm_volatile ("mcr p0, #3, %0, c0, c0" : : "r" (x)); -} - -// Equivalent to sio_hw->gpio_hi_out = x; -__force_inline static void gpioc_hi_out_put(uint32_t x) { - pico_default_asm_volatile ("mcr p0, #0, %0, c0, c1" : : "r" (x)); -} - -// Equivalent to sio_hw->gpio_hi_togl = x; -__force_inline static void gpioc_hi_out_xor(uint32_t x) { - pico_default_asm_volatile ("mcr p0, #1, %0, c0, c1" : : "r" (x)); -} - -// Equivalent to sio_hw->gpio_hi_set = x; -__force_inline static void gpioc_hi_out_set(uint32_t x) { - pico_default_asm_volatile ("mcr p0, #2, %0, c0, c1" : : "r" (x)); -} - -// Equivalent to sio_hw->gpio_hi_clr = x; -__force_inline static void gpioc_hi_out_clr(uint32_t x) { - pico_default_asm_volatile ("mcr p0, #3, %0, c0, c1" : : "r" (x)); -} - -// Equivalent to these two operations performed on the same cycle: -// - sio_hw->gpio_out = x & 0xffffffff; -// - sio_hw->gpio_hi_out = x >> 32; -__force_inline static void gpioc_hilo_out_put(uint64_t x) { - pico_default_asm_volatile ("mcrr p0, #0, %0, %1, c0" : : "r" (x & 0xffffffffu), "r" (x >> 32)); -} - -// Equivalent to these two operations performed on the same cycle: -// - sio_hw->gpio_togl = x & 0xffffffff; -// - sio_hw->gpio_hi_togl = x >> 32; -__force_inline static void gpioc_hilo_out_xor(uint64_t x) { - pico_default_asm_volatile ("mcrr p0, #1, %0, %1, c0" : : "r" (x & 0xffffffffu), "r" (x >> 32)); -} - -// Equivalent to these two operations performed on the same cycle: -// - sio_hw->gpio_set = x & 0xffffffff; -// - sio_hw->gpio_hi_set = x >> 32; -__force_inline static void gpioc_hilo_out_set(uint64_t x) { - pico_default_asm_volatile ("mcrr p0, #2, %0, %1, c0" : : "r" (x & 0xffffffffu), "r" (x >> 32)); -} - -// Equivalent to these two operations performed on the same cycle: -// - sio_hw->gpio_clr = x & 0xffffffff; -// - sio_hw->gpio_hi_clr = x >> 32; -__force_inline static void gpioc_hilo_out_clr(uint64_t x) { - pico_default_asm_volatile ("mcrr p0, #3, %0, %1, c0" : : "r" (x & 0xffffffffu), "r" (x >> 32)); -} - -// ---------------------------------------------------------------------------- -// OE mask write instructions - -// Equivalent to sio_hw->gpio_oe = x; -__force_inline static void gpioc_lo_oe_put(uint32_t x) { - pico_default_asm_volatile ("mcr p0, #0, %0, c0, c4" : : "r" (x)); -} - -// Equivalent to sio_hw->gpio_oe_togl = x; -__force_inline static void gpioc_lo_oe_xor(uint32_t x) { - pico_default_asm_volatile ("mcr p0, #1, %0, c0, c4" : : "r" (x)); -} - -// Equivalent to sio_hw->gpio_oe_set = x; -__force_inline static void gpioc_lo_oe_set(uint32_t x) { - pico_default_asm_volatile ("mcr p0, #2, %0, c0, c4" : : "r" (x)); -} - -// Equivalent to sio_hw->gpio_oe_clr = x; -__force_inline static void gpioc_lo_oe_clr(uint32_t x) { - pico_default_asm_volatile ("mcr p0, #3, %0, c0, c4" : : "r" (x)); -} - -// Equivalent to sio_hw->gpio_hi_oe = x; -__force_inline static void gpioc_hi_oe_put(uint32_t x) { - pico_default_asm_volatile ("mcr p0, #0, %0, c0, c5" : : "r" (x)); -} - -// Equivalent to sio_hw->gpio_hi_oe_togl = x; -__force_inline static void gpioc_hi_oe_xor(uint32_t x) { - pico_default_asm_volatile ("mcr p0, #1, %0, c0, c5" : : "r" (x)); -} - -// Equivalent to sio_hw->gpio_hi_oe_set = x; -__force_inline static void gpioc_hi_oe_set(uint32_t x) { - pico_default_asm_volatile ("mcr p0, #2, %0, c0, c5" : : "r" (x)); -} - -// Equivalent to sio_hw->gpio_hi_oe_clr = x; -__force_inline static void gpioc_hi_oe_clr(uint32_t x) { - pico_default_asm_volatile ("mcr p0, #3, %0, c0, c5" : : "r" (x)); -} - -// Equivalent to these two operations performed on the same cycle: -// - sio_hw->gpio_oe = x & 0xffffffff; -// - sio_hw->gpio_hi_oe = x >> 32; -__force_inline static void gpioc_hilo_oe_put(uint64_t x) { - pico_default_asm_volatile ("mcrr p0, #0, %0, %1, c4" : : "r" (x & 0xffffffffu), "r" (x >> 32)); -} - -// Equivalent to these two operations performed on the same cycle: -// - sio_hw->gpio_oe_togl = x & 0xffffffff; -// - sio_hw->gpio_hi_oe_togl = x >> 32; -__force_inline static void gpioc_hilo_oe_xor(uint64_t x) { - pico_default_asm_volatile ("mcrr p0, #1, %0, %1, c4" : : "r" (x & 0xffffffffu), "r" (x >> 32)); -} - -// Equivalent to these two operations performed on the same cycle: -// - sio_hw->gpio_oe_set = x & 0xffffffff; -// - sio_hw->gpio_hi_oe_set = x >> 32; -__force_inline static void gpioc_hilo_oe_set(uint64_t x) { - pico_default_asm_volatile ("mcrr p0, #2, %0, %1, c4" : : "r" (x & 0xffffffffu), "r" (x >> 32)); -} - -// Equivalent to these two operations performed on the same cycle: -// - sio_hw->gpio_oe_clr = x & 0xffffffff; -// - sio_hw->gpio_hi_oe_clr = x >> 32; -__force_inline static void gpioc_hilo_oe_clr(uint64_t x) { - pico_default_asm_volatile ("mcrr p0, #3, %0, %1, c4" : : "r" (x & 0xffffffffu), "r" (x >> 32)); -} - -// ---------------------------------------------------------------------------- -// Single-bit write instructions - -// Write a 1-bit value to any output. Equivalent to: -// -// if (val) -// gpioc_hilo_out_set(1ull << pin); -// else -// gpioc_hilo_out_clr(1ull << pin); -__force_inline static void gpioc_bit_out_put(uint pin, bool val) { - pico_default_asm_volatile ("mcrr p0, #4, %0, %1, c0" : : "r" (pin), "r" (val)); -} - -// Unconditionally toggle any single output. Equivalent to: -// -// gpioc_hilo_out_xor(1ull << pin); -__force_inline static void gpioc_bit_out_xor(uint pin) { - pico_default_asm_volatile ("mcr p0, #5, %0, c0, c0" : : "r" (pin)); -} - -// Unconditionally set any single output. Equivalent to: -// -// gpioc_hilo_out_set(1ull << pin); -__force_inline static void gpioc_bit_out_set(uint pin) { - pico_default_asm_volatile ("mcr p0, #6, %0, c0, c0" : : "r" (pin)); -} - -// Unconditionally clear any single output. Equivalent to: -// -// gpioc_hilo_out_clr(1ull << pin); -__force_inline static void gpioc_bit_out_clr(uint pin) { - pico_default_asm_volatile ("mcr p0, #7, %0, c0, c0" : : "r" (pin)); -} - -// Conditionally toggle any single output. Equivalent to: -// -// gpioc_hilo_out_xor((uint64_t)val << pin); -__force_inline static void gpioc_bit_out_xor2(uint pin, bool val) { - pico_default_asm_volatile ("mcrr p0, #5, %0, %1, c0" : : "r" (pin), "r" (val)); -} - -// Conditionally set any single output. Equivalent to: -// -// gpioc_hilo_out_set((uint64_t)val << pin); -__force_inline static void gpioc_bit_out_set2(uint pin, bool val) { - pico_default_asm_volatile ("mcrr p0, #6, %0, %1, c0" : : "r" (pin), "r" (val)); -} - -// Conditionally clear any single output. Equivalent to: -// -// gpioc_hilo_out_clr((uint64_t)val << pin); -__force_inline static void gpioc_bit_out_clr2(uint pin, bool val) { - pico_default_asm_volatile ("mcrr p0, #7, %0, %1, c0" : : "r" (pin), "r" (val)); -} - -// Write a 1-bit value to any output enable. Equivalent to: -// -// if (val) -// gpioc_hilo_oe_set(1ull << pin); -// else -// gpioc_hilo_oe_clr(1ull << pin); -__force_inline static void gpioc_bit_oe_put(uint pin, bool val) { - pico_default_asm_volatile ("mcrr p0, #4, %0, %1, c4" : : "r" (pin), "r" (val)); -} - -// Unconditionally toggle any output enable. Equivalent to: -// -// gpioc_hilo_oe_xor(1ull << pin); -__force_inline static void gpioc_bit_oe_xor(uint pin) { - pico_default_asm_volatile ("mcr p0, #5, %0, c0, c4" : : "r" (pin)); -} - -// Unconditionally set any output enable (set to output). Equivalent to: -// -// gpioc_hilo_oe_set(1ull << pin); -__force_inline static void gpioc_bit_oe_set(uint pin) { - pico_default_asm_volatile ("mcr p0, #6, %0, c0, c4" : : "r" (pin)); -} - -// Unconditionally clear any output enable (set to input). Equivalent to: -// -// gpioc_hilo_oe_clr(1ull << pin); -__force_inline static void gpioc_bit_oe_clr(uint pin) { - pico_default_asm_volatile ("mcr p0, #7, %0, c0, c4" : : "r" (pin)); -} - -// Conditionally toggle any output enable. Equivalent to: -// -// gpioc_hilo_oe_xor((uint64_t)val << pin); -__force_inline static void gpioc_bit_oe_xor2(uint pin, bool val) { - pico_default_asm_volatile ("mcrr p0, #5, %0, %1, c4" : : "r" (pin), "r" (val)); -} - -// Conditionally set any output enable (set to output). Equivalent to: -// -// gpioc_hilo_oe_set((uint64_t)val << pin); -__force_inline static void gpioc_bit_oe_set2(uint pin, bool val) { - pico_default_asm_volatile ("mcrr p0, #6, %0, %1, c4" : : "r" (pin), "r" (val)); -} - -// Conditionally clear any output enable (set to input). Equivalent to: -// -// gpioc_hilo_oe_clr((uint64_t)val << pin); -__force_inline static void gpioc_bit_oe_clr2(uint pin, bool val) { - pico_default_asm_volatile ("mcrr p0, #7, %0, %1, c4" : : "r" (pin), "r" (val)); -} - -// ---------------------------------------------------------------------------- -// Indexed mask write instructions -- write to a dynamically selected 32-bit -// GPIO register - -// Write to a selected GPIO output register. Equivalent to: -// -// if (reg_index == 0) { -// gpioc_lo_out_put(val); -// } else if (reg_index == 1) { -// gpioc_hi_out_put(val); -// } else { -// // undefined -// } -__force_inline static void gpioc_index_out_put(uint reg_index, uint32_t val) { - pico_default_asm_volatile ("mcrr p0, #8, %1, %0, c0" : : "r" (reg_index), "r" (val)); -} - -// Toggle bits in a selected GPIO output register. Equivalent to: -// -// if (reg_index == 0) { -// gpioc_lo_out_xor(val); -// } else if (reg_index == 1) { -// gpioc_hi_out_xor(val); -// } else { -// // undefined -// } -__force_inline static void gpioc_index_out_xor(uint reg_index, uint32_t mask) { - pico_default_asm_volatile ("mcrr p0, #9, %1, %0, c0" : : "r" (reg_index), "r" (mask)); -} - -// Set bits in a selected GPIO output register. Equivalent to: -// -// if (reg_index == 0) { -// gpioc_lo_out_set(val); -// } else if (reg_index == 1) { -// gpioc_hi_out_set(val); -// } else { -// // undefined -// } -__force_inline static void gpioc_index_out_set(uint reg_index, uint32_t mask) { - pico_default_asm_volatile ("mcrr p0, #10, %1, %0, c0" : : "r" (reg_index), "r" (mask)); -} - -// Clear bits in a selected GPIO output register. Equivalent to: -// -// if (reg_index == 0) { -// gpioc_lo_out_clr(val); -// } else if (reg_index == 1) { -// gpioc_hi_out_clr(val); -// } else { -// // undefined -// } -__force_inline static void gpioc_index_out_clr(uint reg_index, uint32_t mask) { - pico_default_asm_volatile ("mcrr p0, #11, %1, %0, c0" : : "r" (reg_index), "r" (mask)); -} - -// Write to a selected GPIO output enable register. Equivalent to: -// -// if (reg_index == 0) { -// gpioc_lo_oe_put(val); -// } else if (reg_index == 1) { -// gpioc_hi_oe_put(val); -// } else { -// // undefined -// } -__force_inline static void gpioc_index_oe_put(uint reg_index, uint32_t val) { - pico_default_asm_volatile ("mcrr p0, #8, %1, %0, c4" : : "r" (reg_index), "r" (val)); -} - -// Toggle bits in a selected GPIO output enable register. Equivalent to: -// -// if (reg_index == 0) { -// gpioc_lo_oe_xor(val); -// } else if (reg_index == 1) { -// gpioc_hi_oe_xor(val); -// } else { -// // undefined -// } -__force_inline static void gpioc_index_oe_xor(uint reg_index, uint32_t mask) { - pico_default_asm_volatile ("mcrr p0, #9, %1, %0, c4" : : "r" (reg_index), "r" (mask)); -} - -// Set bits in a selected GPIO output enable register (set to output). Equivalent to: -// -// if (reg_index == 0) { -// gpioc_lo_oe_set(val); -// } else if (reg_index == 1) { -// gpioc_hi_oe_set(val); -// } else { -// // undefined -// } -__force_inline static void gpioc_index_oe_set(uint reg_index, uint32_t mask) { - pico_default_asm_volatile ("mcrr p0, #10, %1, %0, c4" : : "r" (reg_index), "r" (mask)); -} - -// Clear bits in a selected GPIO output enable register (set to input). Equivalent to: -// -// if (reg_index == 0) { -// gpioc_lo_oe_clr(val); -// } else if (reg_index == 1) { -// gpioc_hi_oe_clr(val); -// } else { -// // undefined -// } -__force_inline static void gpioc_index_oe_clr(uint reg_index, uint32_t mask) { - pico_default_asm_volatile ("mcrr p0, #11, %1, %0, c4" : : "r" (reg_index), "r" (mask)); -} - -// ---------------------------------------------------------------------------- -// Read instructions - -// Read back the lower 32-bit output register. Equivalent to: -// -// return sio_hw->gpio_out; -__force_inline static uint32_t gpioc_lo_out_get(void) { - uint32_t lo; - pico_default_asm_volatile ("mrc p0, #0, %0, c0, c0" : "=r" (lo)); - return lo; -} - -// Read back the upper 32-bit output register. Equivalent to: -// -// return sio_hw->gpio_hi_out; -__force_inline static uint32_t gpioc_hi_out_get(void) { - uint32_t hi; - pico_default_asm_volatile ("mrc p0, #0, %0, c0, c1" : "=r" (hi)); - return hi; -} - -// Read back two 32-bit output registers in a single operation. Equivalent to: -// -// return sio_hw->gpio_out | ((uint64_t)sio_hw->gpio_hi_out << 32); -__force_inline static uint64_t gpioc_hilo_out_get(void) { - uint32_t hi, lo; - pico_default_asm_volatile ("mrrc p0, #0, %0, %1, c0" : "=r" (lo), "=r" (hi)); - return ((uint64_t)hi << 32) | lo; -} - -// Read back the lower 32-bit output enable register. Equivalent to: -// -// return sio_hw->gpio_oe; -__force_inline static uint32_t gpioc_lo_oe_get(void) { - uint32_t lo; - pico_default_asm_volatile ("mrc p0, #0, %0, c0, c4" : "=r" (lo)); - return lo; -} - -// Read back the upper 32-bit output enable register. Equivalent to: -// -// return sio_hw->gpio_hi_oe; -__force_inline static uint32_t gpioc_hi_oe_get(void) { - uint32_t hi; - pico_default_asm_volatile ("mrc p0, #0, %0, c0, c5" : "=r" (hi)); - return hi; -} - -// Read back two 32-bit output enable registers in a single operation. Equivalent to: -// -// return sio_hw->gpio_oe | ((uint64_t)sio_hw->gpio_hi_oe << 32); -__force_inline static uint64_t gpioc_hilo_oe_get(void) { - uint32_t hi, lo; - pico_default_asm_volatile ("mrrc p0, #0, %0, %1, c4" : "=r" (lo), "=r" (hi)); - return ((uint64_t)hi << 32) | lo; -} - -// Sample the lower 32 GPIOs. Equivalent to: -// -// return sio_hw->gpio_in; -__force_inline static uint32_t gpioc_lo_in_get(void) { - uint32_t lo; - pico_default_asm_volatile ("mrc p0, #0, %0, c0, c8" : "=r" (lo)); - return lo; -} - -// Sample the upper 32 GPIOs. Equivalent to: -// -// return sio_hw->gpio_hi_in; -__force_inline static uint32_t gpioc_hi_in_get(void) { - uint32_t hi; - pico_default_asm_volatile ("mrc p0, #0, %0, c0, c9" : "=r" (hi)); - return hi; -} - -// Sample 64 GPIOs on the same cycle. Equivalent to: -// -// return sio_hw->gpio_in | ((uint64_t)sio_hw->gpio_hi_in << 32); -__force_inline static uint64_t gpioc_hilo_in_get(void) { - uint32_t hi, lo; - pico_default_asm_volatile ("mrrc p0, #0, %0, %1, c8" : "=r" (lo), "=r" (hi)); - return ((uint64_t)hi << 32) | lo; -} - -#endif diff --git a/lib/main/pico-sdk/rp2_common/hardware_hazard3/include/hardware/hazard3.h b/lib/main/pico-sdk/rp2_common/hardware_hazard3/include/hardware/hazard3.h deleted file mode 100644 index 84dea665e3..0000000000 --- a/lib/main/pico-sdk/rp2_common/hardware_hazard3/include/hardware/hazard3.h +++ /dev/null @@ -1,62 +0,0 @@ -/* - * Copyright (c) 2022 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _HARDWARE_HAZARD3_H -#define _HARDWARE_HAZARD3_H - -#include "pico.h" -#include "hardware/riscv.h" - -// This includes both standard and Hazard3 custom CSRs: -#include "hardware/regs/rvcsr.h" - -#include "hardware/hazard3/features.h" -#include "hardware/hazard3/instructions.h" - -/** \file hardware/hazard3.h - * \defgroup hardware_hazard3 hardware_hazard3 - * - * \brief Accessors for Hazard3-specific RISC-V CSRs, and intrinsics for Hazard3 custom instructions - * - */ - -#ifndef __ASSEMBLER__ - -#ifdef __cplusplus -extern "C" { -#endif - -#ifdef __hazard3_extension_xh3irq -#define hazard3_irqarray_read(csr, index) (riscv_read_set_csr(csr, (index)) >> 16) -#else -#define hazard3_irqarray_read(csr, index) static_assert(false, "Not supported: Xh3irq extension") -#endif - -#ifdef __hazard3_extension_xh3irq -#define hazard3_irqarray_write(csr, index, data) (riscv_write_csr(csr, (index) | ((uint32_t)(data) << 16))) -#else -#define hazard3_irqarray_write(csr, index, data) static_assert(false, "Not supported: Xh3irq extension") -#endif - -#ifdef __hazard3_extension_xh3irq -#define hazard3_irqarray_set(csr, index, data) (riscv_set_csr(csr, (index) | ((uint32_t)(data) << 16))) -#else -#define hazard3_irqarray_set(csr, index, data) static_assert(false, "Not supported: Xh3irq extension") -#endif - -#ifdef __hazard3_extension_xh3irq -#define hazard3_irqarray_clear(csr, index, data) (riscv_clear_csr(csr, (index) | ((uint32_t)(data) << 16))) -#else -#define hazard3_irqarray_clear(csr, index, data) static_assert(false, "Not supported: Xh3irq extension") -#endif - -#ifdef __cplusplus -} -#endif - -#endif - -#endif diff --git a/lib/main/pico-sdk/rp2_common/hardware_hazard3/include/hardware/hazard3/features.h b/lib/main/pico-sdk/rp2_common/hardware_hazard3/include/hardware/hazard3/features.h deleted file mode 100644 index 25e5d2fbae..0000000000 --- a/lib/main/pico-sdk/rp2_common/hardware_hazard3/include/hardware/hazard3/features.h +++ /dev/null @@ -1,29 +0,0 @@ -/* - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _HARDWARE_HAZARD3_FEATURES_H -#define _HARDWARE_HAZARD3_FEATURES_H - -#include "pico.h" - -/** \file hardware/hazard3/features.h - * \addtogroup hardware_hazard3 - * - * \brief Sets macros for supported Hazard3 custom extensions (features) based on PICO_PLATFORM macros - * - */ - -// Feature detection macros for Hazard3 custom extensions -#if PICO_RP2350 -// Version 1.0 of these four extensions -// (encoded as major * 100 + minor) -#define __hazard3_extension_xh3power 100 -#define __hazard3_extension_xh3bextm 100 -#define __hazard3_extension_xh3irq 100 -#define __hazard3_extension_xh3pmpm 100 -#endif - -#endif diff --git a/lib/main/pico-sdk/rp2_common/hardware_hazard3/include/hardware/hazard3/instructions.h b/lib/main/pico-sdk/rp2_common/hardware_hazard3/include/hardware/hazard3/instructions.h deleted file mode 100644 index 7abeb5ba64..0000000000 --- a/lib/main/pico-sdk/rp2_common/hardware_hazard3/include/hardware/hazard3/instructions.h +++ /dev/null @@ -1,152 +0,0 @@ -/* - * Copyright (c) 2024 Raspberry Pi Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _HARDWARE_HAZARD3_INSTRUCTIONS_H -#define _HARDWARE_HAZARD3_INSTRUCTIONS_H - -#include "pico.h" - -// Get list of supported extensions based on platform: -#include "hardware/hazard3/features.h" - -/** \file hardware/hazard3/instructions.h - * \addtogroup hardware_hazard3 - * - * \brief Intrinsics and asm macros for Hazard3 custom instructions - * - * The implementation of these intrinsics depends on the feature macros - * defined in hardware/hazard3/features.h. When the relevant feature is not - * present, the intrinsics fall back on an RV32I equivalent if possible. - * - */ - -#ifdef __ASSEMBLER__ - -// Assembly language instruction macros for Hazard3 custom instructions - -// h3.bextm: Extract up to 8 consecutive bits from register rs1, with the -// first bit indexed by rs2, and bit count configured by an immediate value. -// R-format instruction. Pseudocode: -// -// rd = (rs1 >> rs2[4:0]) & ~(-1 << nbits) - -.macro h3.bextm rd rs1 rs2 nbits -.if (\nbits < 1) || (\nbits > 8) -.err -.endif -#ifdef __hazard3_extension_xh3bextm - .insn r 0x0b, 0x4, (((\nbits - 1) & 0x7 ) << 1), \rd, \rs1, \rs2 -#else - srl \rd, \rs1, \rs2 - andi \rd, \rd, ((1 << \nbits) - 1) -#endif -.endm - -// h3.bextmi: Extract up to 8 consecutive bits from register rs1, with the -// first bit index and the number of bits both configured by immediate -// values. I-format instruction. Pseudocode: -// -// rd = (rs1 >> shamt) & ~(-1 << nbits) - -.macro h3.bextmi rd rs1 shamt nbits -.if (\nbits < 1) || (\nbits > 8) -.err -.endif -.if (\shamt < 0) || (\shamt > 31) -.err -.endif -#ifdef __hazard3_extension_xh3bextm - .insn i 0x0b, 0x4, \rd, \rs1, (\shamt & 0x1f) | (((\nbits - 1) & 0x7 ) << 6) -#else - srli \rd, \rs1, \shamt - andi \rd, \rd, ((1 << \nbits) - 1) -#endif -.endm - -// h3.block: enter an idle state until another processor in the same -// multiprocessor complex executes an h3.unblock instruction, or the -// processor is interrupted. Fall through immediately if an h3.unblock has -// been received since the last execution of an h3.block on this processor. -// On RP2350, processors also have their own h3.unblock signals reflected -// back to them. - -.macro h3.block -#ifdef __hazard3_extension_xh3power - slt x0, x0, x0 -#else - nop -#endif -.endm - -// h3.unblock: signal other processors in the same multiprocessor complex to -// exit the idle state entered by an h3.block instruction. On RP2350, this -// signal is also reflected back to the processor that executed the -// h3.unblock, which will cause that processor's next h3.block to fall -// through immediately. - -.macro h3.unblock -#ifdef __hazard3_extension_xh3power - slt x0, x0, x1 -#else - nop -#endif -.endm - -#else // !__ASSEMBLER__ - -// C language instruction macros for Hazard3 custom instructions - -#ifdef __cplusplus -extern "C" { -#endif - -// nbits must be a constant expression -#ifdef __hazard3_extension_xh3bextm -#define __hazard3_bextm(nbits, rs1, rs2) ({\ - uint32_t __h3_bextm_rd; \ - asm (".insn r 0x0b, 0, %3, %0, %1, %2"\ - : "=r" (__h3_bextm_rd) \ - : "r" (rs1), "r" (rs2), "i" ((((nbits) - 1) & 0x7) << 1)\ - ); \ - __h3_bextm_rd; \ -}) -#else -#define __hazard3_bextm(nbits, rs1, rs2) (((rs1) >> ((rs2) & 0x1f)) & (0xffu >> (7 - (((nbits) - 1) & 0x7)))) -#endif - -// nbits and shamt must be constant expressions -#ifdef __hazard3_extension_xh3bextm -#define __hazard3_bextmi(nbits, rs1, shamt) ({\ - uint32_t __h3_bextmi_rd; \ - asm (".insn i 0x0b, 0x4, %0, %1, %2"\ - : "=r" (__h3_bextmi_rd) \ - : "r" (rs1), "i" ((((nbits) - 1) & 0x7) << 6 | ((shamt) & 0x1f)) \ - ); \ - __h3_bextmi_rd; \ -}) -#else -#define __hazard3_bextm(nbits, rs1, rs2) (((rs1) >> ((shamt) & 0x1f)) & (0xffu >> (7 - (((nbits) - 1) & 0x7)))) -#endif - -#ifdef __hazard3_extension_xh3power -#define __hazard3_block() asm volatile ("slt x0, x0, x0" : : : "memory") -#else -#define __hazard3_block() do {} while (0) -#endif - -#ifdef __hazard3_extension_xh3power -#define __hazard3_unblock() asm volatile ("slt x0, x0, x1" : : : "memory") -#else -#define __hazard3_unblock() do {} while (0) -#endif - -#ifdef __cplusplus -} -#endif - -#endif // !__ASSEMBLER__ - -#endif diff --git a/lib/main/pico-sdk/rp2_common/hardware_i2c/i2c.c b/lib/main/pico-sdk/rp2_common/hardware_i2c/i2c.c deleted file mode 100644 index 0bf88eb505..0000000000 --- a/lib/main/pico-sdk/rp2_common/hardware_i2c/i2c.c +++ /dev/null @@ -1,355 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "hardware/i2c.h" -#include "hardware/resets.h" -#include "hardware/clocks.h" -#include "pico/timeout_helper.h" - -check_hw_layout(i2c_hw_t, enable, I2C_IC_ENABLE_OFFSET); -check_hw_layout(i2c_hw_t, clr_restart_det, I2C_IC_CLR_RESTART_DET_OFFSET); - -i2c_inst_t i2c0_inst = {i2c0_hw, false}; -i2c_inst_t i2c1_inst = {i2c1_hw, false}; - -static inline void i2c_reset(i2c_inst_t *i2c) { - invalid_params_if(HARDWARE_I2C, i2c != i2c0 && i2c != i2c1); - reset_block_num(i2c == i2c0 ? RESET_I2C0 : RESET_I2C1); -} - -static inline void i2c_unreset(i2c_inst_t *i2c) { - invalid_params_if(HARDWARE_I2C, i2c != i2c0 && i2c != i2c1); - unreset_block_num_wait_blocking(i2c == i2c0 ? RESET_I2C0 : RESET_I2C1); -} - -// Addresses of the form 000 0xxx or 111 1xxx are reserved. No slave should -// have these addresses. -#define i2c_reserved_addr(addr) (((addr) & 0x78) == 0 || ((addr) & 0x78) == 0x78) - -uint i2c_init(i2c_inst_t *i2c, uint baudrate) { - i2c_reset(i2c); - i2c_unreset(i2c); - i2c->restart_on_next = false; - - i2c->hw->enable = 0; - - // Configure as a fast-mode master with RepStart support, 7-bit addresses - i2c->hw->con = - I2C_IC_CON_SPEED_VALUE_FAST << I2C_IC_CON_SPEED_LSB | - I2C_IC_CON_MASTER_MODE_BITS | - I2C_IC_CON_IC_SLAVE_DISABLE_BITS | - I2C_IC_CON_IC_RESTART_EN_BITS | - I2C_IC_CON_TX_EMPTY_CTRL_BITS; - - // Set FIFO watermarks to 1 to make things simpler. This is encoded by a register value of 0. - i2c->hw->tx_tl = 0; - i2c->hw->rx_tl = 0; - - // Always enable the DREQ signalling -- harmless if DMA isn't listening - i2c->hw->dma_cr = I2C_IC_DMA_CR_TDMAE_BITS | I2C_IC_DMA_CR_RDMAE_BITS; - - // Re-sets i2c->hw->enable upon returning: - return i2c_set_baudrate(i2c, baudrate); -} - -void i2c_deinit(i2c_inst_t *i2c) { - i2c_reset(i2c); -} - -uint i2c_set_baudrate(i2c_inst_t *i2c, uint baudrate) { - invalid_params_if(HARDWARE_I2C, baudrate == 0); - // I2C is synchronous design that runs from clk_sys - uint freq_in = clock_get_hz(clk_sys); - - // TODO there are some subtleties to I2C timing which we are completely ignoring here - uint period = (freq_in + baudrate / 2) / baudrate; - uint lcnt = period * 3 / 5; // oof this one hurts - uint hcnt = period - lcnt; - // Check for out-of-range divisors: - invalid_params_if(HARDWARE_I2C, hcnt > I2C_IC_FS_SCL_HCNT_IC_FS_SCL_HCNT_BITS); - invalid_params_if(HARDWARE_I2C, lcnt > I2C_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT_BITS); - invalid_params_if(HARDWARE_I2C, hcnt < 8); - invalid_params_if(HARDWARE_I2C, lcnt < 8); - - // Per I2C-bus specification a device in standard or fast mode must - // internally provide a hold time of at least 300ns for the SDA signal to - // bridge the undefined region of the falling edge of SCL. A smaller hold - // time of 120ns is used for fast mode plus. - uint sda_tx_hold_count; - if (baudrate < 1000000) { - // sda_tx_hold_count = freq_in [cycles/s] * 300ns * (1s / 1e9ns) - // Reduce 300/1e9 to 3/1e7 to avoid numbers that don't fit in uint. - // Add 1 to avoid division truncation. - sda_tx_hold_count = ((freq_in * 3) / 10000000) + 1; - } else { - // sda_tx_hold_count = freq_in [cycles/s] * 120ns * (1s / 1e9ns) - // Reduce 120/1e9 to 3/25e6 to avoid numbers that don't fit in uint. - // Add 1 to avoid division truncation. - sda_tx_hold_count = ((freq_in * 3) / 25000000) + 1; - } - assert(sda_tx_hold_count <= lcnt - 2); - - i2c->hw->enable = 0; - // Always use "fast" mode (<= 400 kHz, works fine for standard mode too) - hw_write_masked(&i2c->hw->con, - I2C_IC_CON_SPEED_VALUE_FAST << I2C_IC_CON_SPEED_LSB, - I2C_IC_CON_SPEED_BITS - ); - i2c->hw->fs_scl_hcnt = hcnt; - i2c->hw->fs_scl_lcnt = lcnt; - i2c->hw->fs_spklen = lcnt < 16 ? 1 : lcnt / 16; - hw_write_masked(&i2c->hw->sda_hold, - sda_tx_hold_count << I2C_IC_SDA_HOLD_IC_SDA_TX_HOLD_LSB, - I2C_IC_SDA_HOLD_IC_SDA_TX_HOLD_BITS); - - i2c->hw->enable = 1; - return freq_in / period; -} - -void i2c_set_slave_mode(i2c_inst_t *i2c, bool slave, uint8_t addr) { - invalid_params_if(HARDWARE_I2C, addr >= 0x80); // 7-bit addresses - invalid_params_if(HARDWARE_I2C, i2c_reserved_addr(addr)); - i2c->hw->enable = 0; - uint32_t ctrl_set_if_master = I2C_IC_CON_MASTER_MODE_BITS | I2C_IC_CON_IC_SLAVE_DISABLE_BITS; - uint32_t ctrl_set_if_slave = I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_BITS; - if (slave) { - hw_write_masked(&i2c->hw->con, - ctrl_set_if_slave, - ctrl_set_if_master | ctrl_set_if_slave - ); - i2c->hw->sar = addr; - } else { - hw_write_masked(&i2c->hw->con, - ctrl_set_if_master, - ctrl_set_if_master | ctrl_set_if_slave - ); - } - i2c->hw->enable = 1; -} - -static int i2c_write_blocking_internal(i2c_inst_t *i2c, uint8_t addr, const uint8_t *src, size_t len, bool nostop, - check_timeout_fn timeout_check, struct timeout_state *ts) { - invalid_params_if(HARDWARE_I2C, addr >= 0x80); // 7-bit addresses - invalid_params_if(HARDWARE_I2C, i2c_reserved_addr(addr)); - // Synopsys hw accepts start/stop flags alongside data items in the same - // FIFO word, so no 0 byte transfers. - invalid_params_if(HARDWARE_I2C, len == 0); - invalid_params_if(HARDWARE_I2C, ((int)len) < 0); - - i2c->hw->enable = 0; - i2c->hw->tar = addr; - i2c->hw->enable = 1; - - bool abort = false; - bool timeout = false; - - uint32_t abort_reason = 0; - int byte_ctr; - - int ilen = (int)len; - for (byte_ctr = 0; byte_ctr < ilen; ++byte_ctr) { - bool first = byte_ctr == 0; - bool last = byte_ctr == ilen - 1; - - if (timeout_check) { - timeout_check(ts, true); // for per iteration checks, this will reset the timeout - } - - i2c->hw->data_cmd = - bool_to_bit(first && i2c->restart_on_next) << I2C_IC_DATA_CMD_RESTART_LSB | - bool_to_bit(last && !nostop) << I2C_IC_DATA_CMD_STOP_LSB | - *src++; - - // Wait until the transmission of the address/data from the internal - // shift register has completed. For this to function correctly, the - // TX_EMPTY_CTRL flag in IC_CON must be set. The TX_EMPTY_CTRL flag - // was set in i2c_init. - do { - if (timeout_check) { - timeout = timeout_check(ts, false); - abort |= timeout; - } - tight_loop_contents(); - } while (!timeout && !(i2c->hw->raw_intr_stat & I2C_IC_RAW_INTR_STAT_TX_EMPTY_BITS)); - - // If there was a timeout, don't attempt to do anything else. - if (!timeout) { - abort_reason = i2c->hw->tx_abrt_source; - if (abort_reason) { - // Note clearing the abort flag also clears the reason, and - // this instance of flag is clear-on-read! Note also the - // IC_CLR_TX_ABRT register always reads as 0. - i2c->hw->clr_tx_abrt; - abort = true; - } - - if (abort || (last && !nostop)) { - // If the transaction was aborted or if it completed - // successfully wait until the STOP condition has occurred. - - // TODO Could there be an abort while waiting for the STOP - // condition here? If so, additional code would be needed here - // to take care of the abort. - do { - if (timeout_check) { - timeout = timeout_check(ts, false); - abort |= timeout; - } - tight_loop_contents(); - } while (!timeout && !(i2c->hw->raw_intr_stat & I2C_IC_RAW_INTR_STAT_STOP_DET_BITS)); - - // If there was a timeout, don't attempt to do anything else. - if (!timeout) { - i2c->hw->clr_stop_det; - } - } - } - - // Note the hardware issues a STOP automatically on an abort condition. - // Note also the hardware clears RX FIFO as well as TX on abort, - // because we set hwparam IC_AVOID_RX_FIFO_FLUSH_ON_TX_ABRT to 0. - if (abort) - break; - } - - int rval; - - // A lot of things could have just happened due to the ingenious and - // creative design of I2C. Try to figure things out. - if (abort) { - if (timeout) - rval = PICO_ERROR_TIMEOUT; - else if (!abort_reason || abort_reason & I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_BITS) { - // No reported errors - seems to happen if there is nothing connected to the bus. - // Address byte not acknowledged - rval = PICO_ERROR_GENERIC; - } else if (abort_reason & I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_BITS) { - // Address acknowledged, some data not acknowledged - rval = byte_ctr; - } else { - //panic("Unknown abort from I2C instance @%08x: %08x\n", (uint32_t) i2c->hw, abort_reason); - rval = PICO_ERROR_GENERIC; - } - } else { - rval = byte_ctr; - } - - // nostop means we are now at the end of a *message* but not the end of a *transfer* - i2c->restart_on_next = nostop; - return rval; -} - -int i2c_write_blocking(i2c_inst_t *i2c, uint8_t addr, const uint8_t *src, size_t len, bool nostop) { - return i2c_write_blocking_internal(i2c, addr, src, len, nostop, NULL, NULL); -} - -int i2c_write_blocking_until(i2c_inst_t *i2c, uint8_t addr, const uint8_t *src, size_t len, bool nostop, - absolute_time_t until) { - timeout_state_t ts; - return i2c_write_blocking_internal(i2c, addr, src, len, nostop, init_single_timeout_until(&ts, until), &ts); -} - -int i2c_write_timeout_per_char_us(i2c_inst_t *i2c, uint8_t addr, const uint8_t *src, size_t len, bool nostop, - uint timeout_per_char_us) { - timeout_state_t ts; - return i2c_write_blocking_internal(i2c, addr, src, len, nostop, - init_per_iteration_timeout_us(&ts, timeout_per_char_us), &ts); -} - -int i2c_write_burst_blocking(i2c_inst_t *i2c, uint8_t addr, const uint8_t *src, size_t len) { - int rc = i2c_write_blocking_internal(i2c, addr, src, len, true, NULL, NULL); - i2c->restart_on_next = false; - return rc; -} - -static int i2c_read_blocking_internal(i2c_inst_t *i2c, uint8_t addr, uint8_t *dst, size_t len, bool nostop, - check_timeout_fn timeout_check, timeout_state_t *ts) { - invalid_params_if(HARDWARE_I2C, addr >= 0x80); // 7-bit addresses - invalid_params_if(HARDWARE_I2C, i2c_reserved_addr(addr)); - invalid_params_if(HARDWARE_I2C, len == 0); - invalid_params_if(HARDWARE_I2C, ((int)len) < 0); - - i2c->hw->enable = 0; - i2c->hw->tar = addr; - i2c->hw->enable = 1; - - bool abort = false; - bool timeout = false; - uint32_t abort_reason; - int byte_ctr; - int ilen = (int)len; - for (byte_ctr = 0; byte_ctr < ilen; ++byte_ctr) { - bool first = byte_ctr == 0; - bool last = byte_ctr == ilen - 1; - if (timeout_check) { - timeout_check(ts, true); // for per iteration checks, this will reset the timeout - } - - while (!i2c_get_write_available(i2c)) - tight_loop_contents(); - - i2c->hw->data_cmd = - bool_to_bit(first && i2c->restart_on_next) << I2C_IC_DATA_CMD_RESTART_LSB | - bool_to_bit(last && !nostop) << I2C_IC_DATA_CMD_STOP_LSB | - I2C_IC_DATA_CMD_CMD_BITS; // -> 1 for read - - do { - abort_reason = i2c->hw->tx_abrt_source; - abort = (bool) i2c->hw->clr_tx_abrt; - if (timeout_check) { - timeout = timeout_check(ts, false); - abort |= timeout; - } - } while (!abort && !i2c_get_read_available(i2c)); - - if (abort) - break; - - *dst++ = (uint8_t) i2c->hw->data_cmd; - } - - int rval; - - if (abort) { - if (timeout) - rval = PICO_ERROR_TIMEOUT; - else if (!abort_reason || abort_reason & I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_BITS) { - // No reported errors - seems to happen if there is nothing connected to the bus. - // Address byte not acknowledged - rval = PICO_ERROR_GENERIC; - } else { -// panic("Unknown abort from I2C instance @%08x: %08x\n", (uint32_t) i2c->hw, abort_reason); - rval = PICO_ERROR_GENERIC; - } - } else { - rval = byte_ctr; - } - - i2c->restart_on_next = nostop; - return rval; -} - -int i2c_read_blocking(i2c_inst_t *i2c, uint8_t addr, uint8_t *dst, size_t len, bool nostop) { - return i2c_read_blocking_internal(i2c, addr, dst, len, nostop, NULL, NULL); -} - -int i2c_read_blocking_until(i2c_inst_t *i2c, uint8_t addr, uint8_t *dst, size_t len, bool nostop, absolute_time_t until) { - timeout_state_t ts; - return i2c_read_blocking_internal(i2c, addr, dst, len, nostop, init_single_timeout_until(&ts, until), &ts); -} - -int i2c_read_timeout_per_char_us(i2c_inst_t *i2c, uint8_t addr, uint8_t *dst, size_t len, bool nostop, - uint timeout_per_char_us) { - timeout_state_t ts; - return i2c_read_blocking_internal(i2c, addr, dst, len, nostop, - init_per_iteration_timeout_us(&ts, timeout_per_char_us), &ts); -} - -int i2c_read_burst_blocking(i2c_inst_t *i2c, uint8_t addr, uint8_t *dst, size_t len) { - int rc = i2c_read_blocking_internal(i2c, addr, dst, len, true, NULL, NULL); - i2c->restart_on_next = false; - return rc; -} diff --git a/lib/main/pico-sdk/rp2_common/hardware_i2c/include/hardware/i2c.h b/lib/main/pico-sdk/rp2_common/hardware_i2c/include/hardware/i2c.h deleted file mode 100644 index 9a9cdb080b..0000000000 --- a/lib/main/pico-sdk/rp2_common/hardware_i2c/include/hardware/i2c.h +++ /dev/null @@ -1,466 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _HARDWARE_I2C_H -#define _HARDWARE_I2C_H - -#include "pico.h" -#include "pico/time.h" -#include "hardware/structs/i2c.h" -#include "hardware/regs/dreq.h" - -// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_HARDWARE_I2C, Enable/disable assertions in the hardware_i2c module, type=bool, default=0, group=hardware_i2c -#ifndef PARAM_ASSERTIONS_ENABLED_HARDWARE_I2C -#ifdef PARAM_ASSERTIONS_ENABLED_I2C // backwards compatibility with SDK < 2.0.0 -#define PARAM_ASSERTIONS_ENABLED_HARDWARE_I2C PARAM_ASSERTIONS_ENABLED_I2C -#else -#define PARAM_ASSERTIONS_ENABLED_HARDWARE_I2C 0 -#endif -#endif -#ifdef __cplusplus -extern "C" { -#endif - -/** \file hardware/i2c.h - * \defgroup hardware_i2c hardware_i2c - * - * \brief I2C Controller API - * - * The I2C bus is a two-wire serial interface, consisting of a serial data line SDA and a serial clock SCL. These wires carry - * information between the devices connected to the bus. Each device is recognized by a unique 7-bit address and can operate as - * either a “transmitter” or “receiver”, depending on the function of the device. Devices can also be considered as masters or - * slaves when performing data transfers. A master is a device that initiates a data transfer on the bus and generates the - * clock signals to permit that transfer. The first byte in the data transfer always contains the 7-bit address and - * a read/write bit in the LSB position. This API takes care of toggling the read/write bit. After this, any device addressed - * is considered a slave. - * - * This API allows the controller to be set up as a master or a slave using the \ref i2c_set_slave_mode function. - * - * The external pins of each controller are connected to GPIO pins as defined in the GPIO muxing table in the datasheet. The muxing options - * give some IO flexibility, but each controller external pin should be connected to only one GPIO. - * - * Note that the controller does NOT support High speed mode or Ultra-fast speed mode, the fastest operation being fast mode plus - * at up to 1000Kb/s. - * - * See the datasheet for more information on the I2C controller and its usage. - * - * \subsection i2c_example Example - * \addtogroup hardware_i2c - * \include bus_scan.c - */ - -typedef struct i2c_inst i2c_inst_t; - -// PICO_CONFIG: PICO_DEFAULT_I2C, Define the default I2C for a board, min=0, max=1, default=Usually provided via board header, group=hardware_i2c -// PICO_CONFIG: PICO_DEFAULT_I2C_SDA_PIN, Define the default I2C SDA pin, min=0, max=29, default=Usually provided via board header, group=hardware_i2c -// PICO_CONFIG: PICO_DEFAULT_I2C_SCL_PIN, Define the default I2C SCL pin, min=0, max=29, default=Usually provided via board header, group=hardware_i2c - -/** The I2C identifiers for use in I2C functions. - * - * e.g. i2c_init(i2c0, 48000) - * - * \ingroup hardware_i2c - * @{ - */ -extern i2c_inst_t i2c0_inst; -extern i2c_inst_t i2c1_inst; - -#define i2c0 (&i2c0_inst) ///< Identifier for I2C HW Block 0 -#define i2c1 (&i2c1_inst) ///< Identifier for I2C HW Block 1 - -#if !defined(PICO_DEFAULT_I2C_INSTANCE) && defined(PICO_DEFAULT_I2C) -#define PICO_DEFAULT_I2C_INSTANCE() (__CONCAT(i2c,PICO_DEFAULT_I2C)) -#endif - -/** - * \def PICO_DEFAULT_I2C - * \ingroup hardware_i2c - * \hideinitializer - * \brief The default I2C instance number - */ - -/** - * \def PICO_DEFAULT_I2C_INSTANCE() - * \ingroup hardware_i2c - * \hideinitializer - * \brief Returns the default I2C instance based on the value of PICO_DEFAULT_I2C - */ -#ifdef PICO_DEFAULT_I2C_INSTANCE -#define i2c_default PICO_DEFAULT_I2C_INSTANCE() -#endif - -/** @} */ - -// ---------------------------------------------------------------------------- -// Setup - -/*! \brief Initialise the I2C HW block - * \ingroup hardware_i2c - * - * Put the I2C hardware into a known state, and enable it. Must be called - * before other functions. By default, the I2C is configured to operate as a - * master. - * - * The I2C bus frequency is set as close as possible to requested, and - * the actual rate set is returned - * - * \param i2c Either \ref i2c0 or \ref i2c1 - * \param baudrate Baudrate in Hz (e.g. 100kHz is 100000) - * \return Actual set baudrate - */ -uint i2c_init(i2c_inst_t *i2c, uint baudrate); - -/*! \brief Disable the I2C HW block - * \ingroup hardware_i2c - * - * \param i2c Either \ref i2c0 or \ref i2c1 - * - * Disable the I2C again if it is no longer used. Must be reinitialised before - * being used again. - */ -void i2c_deinit(i2c_inst_t *i2c); - -/*! \brief Set I2C baudrate - * \ingroup hardware_i2c - * - * Set I2C bus frequency as close as possible to requested, and return actual - * rate set. - * Baudrate may not be as exactly requested due to clocking limitations. - * - * \param i2c Either \ref i2c0 or \ref i2c1 - * \param baudrate Baudrate in Hz (e.g. 100kHz is 100000) - * \return Actual set baudrate - */ -uint i2c_set_baudrate(i2c_inst_t *i2c, uint baudrate); - -/*! \brief Set I2C port to slave mode - * \ingroup hardware_i2c - * - * \param i2c Either \ref i2c0 or \ref i2c1 - * \param slave true to use slave mode, false to use master mode - * \param addr If \p slave is true, set the slave address to this value - */ -void i2c_set_slave_mode(i2c_inst_t *i2c, bool slave, uint8_t addr); - -// ---------------------------------------------------------------------------- -// Generic input/output - -struct i2c_inst { - i2c_hw_t *hw; - bool restart_on_next; -}; - -/** - * \def I2C_NUM(i2c) - * \ingroup hardware_i2c - * \hideinitializer - * \brief Returns the I2C number for a I2C instance - * - * Note this macro is intended to resolve at compile time, and does no parameter checking - */ -#ifndef I2C_NUM -static_assert(NUM_I2CS == 2, ""); -#define I2C_NUM(i2c) ((i2c) == i2c1) -#endif - -/** - * \def I2C_INSTANCE(i2c_num) - * \ingroup hardware_i2c - * \hideinitializer - * \brief Returns the I2C instance with the given I2C number - * - * Note this macro is intended to resolve at compile time, and does no parameter checking - */ -#ifndef I2C_INSTANCE -static_assert(NUM_I2CS == 2, ""); -#define I2C_INSTANCE(num) ((num) ? i2c1 : i2c0) -#endif - -/** - * \def I2C_DREQ_NUM(i2c, is_tx) - * \ingroup hardware_i2c - * \hideinitializer - * \brief Returns the \ref dreq_num_t used for pacing DMA transfers to or from this I2C instance. - * If is_tx is true, then it is for transfers to the I2C instance else for transfers from the I2C instance. - * - * Note this macro is intended to resolve at compile time, and does no parameter checking - */ -#ifndef I2C_DREQ_NUM -static_assert(DREQ_I2C0_RX == DREQ_I2C0_TX + 1, ""); -static_assert(DREQ_I2C1_RX == DREQ_I2C1_TX + 1, ""); -static_assert(DREQ_I2C1_TX == DREQ_I2C0_TX + 2, ""); -#define I2C_DREQ_NUM(i2c,is_tx) (DREQ_I2C0_TX + I2C_NUM(i2c) * 2 + !(is_tx)) -#endif - -/*! \brief Convert I2C instance to hardware instance number - * \ingroup hardware_i2c - * - * \param i2c I2C instance - * \return Number of I2C, 0 or 1. - */ -static inline uint i2c_get_index(i2c_inst_t *i2c) { - invalid_params_if(HARDWARE_I2C, i2c != i2c0 && i2c != i2c1); - return I2C_NUM(i2c); -} - -// backward compatibility -#define i2c_hw_index(i2c) i2c_get_index(i2c) - -/*! \brief Return pointer to structure containing i2c hardware registers - * \ingroup hardware_i2c - * - * \param i2c I2C instance - * \return pointer to \ref i2c_hw_t - */ -static inline i2c_hw_t *i2c_get_hw(i2c_inst_t *i2c) { - i2c_hw_index(i2c); // check it is a hw i2c - return i2c->hw; -} - -/*! \brief Convert I2C hardware instance number to I2C instance - * \ingroup hardware_i2c - * - * \param num Number of I2C, 0 or 1 - * \return I2C hardware instance - */ -static inline i2c_inst_t *i2c_get_instance(uint num) { - invalid_params_if(HARDWARE_I2C, num >= NUM_I2CS); - return I2C_INSTANCE(num); -} - -/*! \brief Attempt to write specified number of bytes to address, blocking until the specified absolute time is reached. - * \ingroup hardware_i2c - * - * \param i2c Either \ref i2c0 or \ref i2c1 - * \param addr 7-bit address of device to write to - * \param src Pointer to data to send - * \param len Length of data in bytes to send - * \param nostop If true, master retains control of the bus at the end of the transfer (no Stop is issued), - * and the next transfer will begin with a Restart rather than a Start. - * \param until The absolute time that the block will wait until the entire transaction is complete. Note, an individual timeout of - * this value divided by the length of data is applied for each byte transfer, so if the first or subsequent - * bytes fails to transfer within that sub timeout, the function will return with an error. - * - * \return Number of bytes written, or PICO_ERROR_GENERIC if address not acknowledged, no device present, or PICO_ERROR_TIMEOUT if a timeout occurred. - */ -int i2c_write_blocking_until(i2c_inst_t *i2c, uint8_t addr, const uint8_t *src, size_t len, bool nostop, absolute_time_t until); - -/*! \brief Attempt to read specified number of bytes from address, blocking until the specified absolute time is reached. - * \ingroup hardware_i2c - * - * \param i2c Either \ref i2c0 or \ref i2c1 - * \param addr 7-bit address of device to read from - * \param dst Pointer to buffer to receive data - * \param len Length of data in bytes to receive - * \param nostop If true, master retains control of the bus at the end of the transfer (no Stop is issued), - * and the next transfer will begin with a Restart rather than a Start. - * \param until The absolute time that the block will wait until the entire transaction is complete. - * \return Number of bytes read, or PICO_ERROR_GENERIC if address not acknowledged, no device present, or PICO_ERROR_TIMEOUT if a timeout occurred. - */ -int i2c_read_blocking_until(i2c_inst_t *i2c, uint8_t addr, uint8_t *dst, size_t len, bool nostop, absolute_time_t until); - -/*! \brief Attempt to write specified number of bytes to address, with timeout - * \ingroup hardware_i2c - * - * \param i2c Either \ref i2c0 or \ref i2c1 - * \param addr 7-bit address of device to write to - * \param src Pointer to data to send - * \param len Length of data in bytes to send - * \param nostop If true, master retains control of the bus at the end of the transfer (no Stop is issued), - * and the next transfer will begin with a Restart rather than a Start. - * \param timeout_us The time that the function will wait for the entire transaction to complete. Note, an individual timeout of - * this value divided by the length of data is applied for each byte transfer, so if the first or subsequent - * bytes fails to transfer within that sub timeout, the function will return with an error. - * - * \return Number of bytes written, or PICO_ERROR_GENERIC if address not acknowledged, no device present, or PICO_ERROR_TIMEOUT if a timeout occurred. - */ -static inline int i2c_write_timeout_us(i2c_inst_t *i2c, uint8_t addr, const uint8_t *src, size_t len, bool nostop, uint timeout_us) { - absolute_time_t t = make_timeout_time_us(timeout_us); - return i2c_write_blocking_until(i2c, addr, src, len, nostop, t); -} - -int i2c_write_timeout_per_char_us(i2c_inst_t *i2c, uint8_t addr, const uint8_t *src, size_t len, bool nostop, uint timeout_per_char_us); - -/*! \brief Attempt to read specified number of bytes from address, with timeout - * \ingroup hardware_i2c - * - * \param i2c Either \ref i2c0 or \ref i2c1 - * \param addr 7-bit address of device to read from - * \param dst Pointer to buffer to receive data - * \param len Length of data in bytes to receive - * \param nostop If true, master retains control of the bus at the end of the transfer (no Stop is issued), - * and the next transfer will begin with a Restart rather than a Start. - * \param timeout_us The time that the function will wait for the entire transaction to complete - * \return Number of bytes read, or PICO_ERROR_GENERIC if address not acknowledged, no device present, or PICO_ERROR_TIMEOUT if a timeout occurred. - */ -static inline int i2c_read_timeout_us(i2c_inst_t *i2c, uint8_t addr, uint8_t *dst, size_t len, bool nostop, uint timeout_us) { - absolute_time_t t = make_timeout_time_us(timeout_us); - return i2c_read_blocking_until(i2c, addr, dst, len, nostop, t); -} - -int i2c_read_timeout_per_char_us(i2c_inst_t *i2c, uint8_t addr, uint8_t *dst, size_t len, bool nostop, uint timeout_per_char_us); - -/*! \brief Attempt to write specified number of bytes to address, blocking - * \ingroup hardware_i2c - * - * \param i2c Either \ref i2c0 or \ref i2c1 - * \param addr 7-bit address of device to write to - * \param src Pointer to data to send - * \param len Length of data in bytes to send - * \param nostop If true, master retains control of the bus at the end of the transfer (no Stop is issued), - * and the next transfer will begin with a Restart rather than a Start. - * \return Number of bytes written, or PICO_ERROR_GENERIC if address not acknowledged, no device present. - */ -int i2c_write_blocking(i2c_inst_t *i2c, uint8_t addr, const uint8_t *src, size_t len, bool nostop); - -/*! \brief Attempt to write specified number of bytes to address, blocking in burst mode - * \ingroup hardware_i2c - * - * This version of the function will not issue a stop and will not restart on the next write. - * This allows you to write consecutive bytes of data without having to resend a stop bit and - * (for example) without having to send address byte(s) repeatedly - * - * \param i2c Either \ref i2c0 or \ref i2c1 - * \param addr 7-bit address of device to read from - * \param dst Pointer to buffer to receive data - * \param len Length of data in bytes to receive - * \return Number of bytes read, or PICO_ERROR_GENERIC if address not acknowledged or no device present. - */ -int i2c_write_burst_blocking(i2c_inst_t *i2c, uint8_t addr, const uint8_t *src, size_t len); - -/*! \brief Attempt to read specified number of bytes from address, blocking - * \ingroup hardware_i2c - * - * \param i2c Either \ref i2c0 or \ref i2c1 - * \param addr 7-bit address of device to read from - * \param dst Pointer to buffer to receive data - * \param len Length of data in bytes to receive - * \param nostop If true, master retains control of the bus at the end of the transfer (no Stop is issued), - * and the next transfer will begin with a Restart rather than a Start. - * \return Number of bytes read, or PICO_ERROR_GENERIC if address not acknowledged or no device present. - */ -int i2c_read_blocking(i2c_inst_t *i2c, uint8_t addr, uint8_t *dst, size_t len, bool nostop); - -/*! \brief Attempt to read specified number of bytes from address, blocking in burst mode - * \ingroup hardware_i2c - * - * This version of the function will not issue a stop and will not restart on the next read. - * This allows you to read consecutive bytes of data without having to resend a stop bit and - * (for example) without having to send address byte(s) repeatedly - * - * \param i2c Either \ref i2c0 or \ref i2c1 - * \param addr 7-bit address of device to read from - * \param dst Pointer to buffer to receive data - * \param len Length of data in bytes to receive - * \return Number of bytes read, or PICO_ERROR_GENERIC if address not acknowledged or no device present. - */ -int i2c_read_burst_blocking(i2c_inst_t *i2c, uint8_t addr, uint8_t *dst, size_t len); - -/*! \brief Determine non-blocking write space available - * \ingroup hardware_i2c - * - * \param i2c Either \ref i2c0 or \ref i2c1 - * \return 0 if no space is available in the I2C to write more data. If return is nonzero, at - * least that many bytes can be written without blocking. - */ -static inline size_t i2c_get_write_available(i2c_inst_t *i2c) { - const size_t IC_TX_BUFFER_DEPTH = 16; - return IC_TX_BUFFER_DEPTH - i2c_get_hw(i2c)->txflr; -} - -/*! \brief Determine number of bytes received - * \ingroup hardware_i2c - * - * \param i2c Either \ref i2c0 or \ref i2c1 - * \return 0 if no data available, if return is nonzero at - * least that many bytes can be read without blocking. - */ -static inline size_t i2c_get_read_available(i2c_inst_t *i2c) { - return i2c_get_hw(i2c)->rxflr; -} - -/*! \brief Write direct to TX FIFO - * \ingroup hardware_i2c - * - * \param i2c Either \ref i2c0 or \ref i2c1 - * \param src Data to send - * \param len Number of bytes to send - * - * Writes directly to the I2C TX FIFO which is mainly useful for - * slave-mode operation. - */ -static inline void i2c_write_raw_blocking(i2c_inst_t *i2c, const uint8_t *src, size_t len) { - for (size_t i = 0; i < len; ++i) { - // TODO NACK or STOP on end? - while (!i2c_get_write_available(i2c)) - tight_loop_contents(); - i2c_get_hw(i2c)->data_cmd = *src++; - } -} - -/*! \brief Read direct from RX FIFO - * \ingroup hardware_i2c - * - * \param i2c Either \ref i2c0 or \ref i2c1 - * \param dst Buffer to accept data - * \param len Number of bytes to read - * - * Reads directly from the I2C RX FIFO which is mainly useful for - * slave-mode operation. - */ -static inline void i2c_read_raw_blocking(i2c_inst_t *i2c, uint8_t *dst, size_t len) { - for (size_t i = 0; i < len; ++i) { - while (!i2c_get_read_available(i2c)) - tight_loop_contents(); - *dst++ = (uint8_t)i2c_get_hw(i2c)->data_cmd; - } -} - -/** - * \brief Pop a byte from I2C Rx FIFO. - * \ingroup hardware_i2c - * - * This function is non-blocking and assumes the Rx FIFO isn't empty. - * - * \param i2c I2C instance. - * \return uint8_t Byte value. - */ -static inline uint8_t i2c_read_byte_raw(i2c_inst_t *i2c) { - i2c_hw_t *hw = i2c_get_hw(i2c); - assert(hw->status & I2C_IC_STATUS_RFNE_BITS); // Rx FIFO must not be empty - return (uint8_t)hw->data_cmd; -} - -/** - * \brief Push a byte into I2C Tx FIFO. - * \ingroup hardware_i2c - * - * This function is non-blocking and assumes the Tx FIFO isn't full. - * - * \param i2c I2C instance. - * \param value Byte value. - */ -static inline void i2c_write_byte_raw(i2c_inst_t *i2c, uint8_t value) { - i2c_hw_t *hw = i2c_get_hw(i2c); - assert(hw->status & I2C_IC_STATUS_TFNF_BITS); // Tx FIFO must not be full - hw->data_cmd = value; -} - -/*! \brief Return the DREQ to use for pacing transfers to/from a particular I2C instance - * \ingroup hardware_i2c - * - * \param i2c Either \ref i2c0 or \ref i2c1 - * \param is_tx true for sending data to the I2C instance, false for receiving data from the I2C instance - */ -static inline uint i2c_get_dreq(i2c_inst_t *i2c, bool is_tx) { - return I2C_DREQ_NUM(i2c, is_tx); -} - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/lib/main/pico-sdk/rp2_common/hardware_interp/include/hardware/interp.h b/lib/main/pico-sdk/rp2_common/hardware_interp/include/hardware/interp.h deleted file mode 100644 index edf541c8ae..0000000000 --- a/lib/main/pico-sdk/rp2_common/hardware_interp/include/hardware/interp.h +++ /dev/null @@ -1,462 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _HARDWARE_INTERP_H -#define _HARDWARE_INTERP_H - -#include "pico.h" -#include "hardware/structs/interp.h" -#include "hardware/regs/sio.h" - -// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_HARDWARE_INTERP, Enable/disable assertions in the hardware_interp module, type=bool, default=0, group=hardware_interp -#ifndef PARAM_ASSERTIONS_ENABLED_HARDWARE_INTERP -#ifdef PARAM_ASSERTIONS_ENABLED_INTERP // backwards compatibility with SDK < 2.0.0 -#define PARAM_ASSERTIONS_ENABLED_HARDWARE_INTERP PARAM_ASSERTIONS_ENABLED_INTERP -#else -#define PARAM_ASSERTIONS_ENABLED_HARDWARE_INTERP 0 -#endif -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -/** \file hardware/interp.h - * \defgroup hardware_interp hardware_interp - * - * \brief Hardware Interpolator API - * - * Each core is equipped with two interpolators (INTERP0 and INTERP1) which can be used to accelerate - * tasks by combining certain pre-configured simple operations into a single processor cycle. Intended - * for cases where the pre-configured operation is repeated a large number of times, this results in - * code which uses both fewer CPU cycles and fewer CPU registers in the time critical sections of the - * code. - * - * The interpolators are used heavily to accelerate audio operations within the SDK, but their - * flexible configuration make it possible to optimise many other tasks such as quantization and - * dithering, table lookup address generation, affine texture mapping, decompression and linear feedback. - * - * Please refer to the appropriate RP-series microcontroller datasheet for more information on the HW - * interpolators and how they work. - */ - -#define interp0 interp0_hw -#define interp1 interp1_hw - -/** \brief Interpolator configuration - * \defgroup interp_config interp_config - * \ingroup hardware_interp - * - * Each interpolator needs to be configured, these functions provide handy helpers to set up configuration - * structures. - * - */ - -typedef struct { - uint32_t ctrl; -} interp_config; - -static inline uint interp_index(interp_hw_t *interp) { - valid_params_if(HARDWARE_INTERP, interp == interp0 || interp == interp1); - return interp == interp1 ? 1 : 0; -} - -/*! \brief Claim the interpolator lane specified - * \ingroup hardware_interp - * - * Use this function to claim exclusive access to the specified interpolator lane. - * - * This function will panic if the lane is already claimed. - * - * \param interp Interpolator on which to claim a lane. interp0 or interp1 - * \param lane The lane number, 0 or 1. - */ -void interp_claim_lane(interp_hw_t *interp, uint lane); -// The above really should be called this for consistency -#define interp_lane_claim interp_claim_lane - -/*! \brief Claim the interpolator lanes specified in the mask - * \ingroup hardware_interp - * - * \param interp Interpolator on which to claim lanes. interp0 or interp1 - * \param lane_mask Bit pattern of lanes to claim (only bits 0 and 1 are valid) - */ -void interp_claim_lane_mask(interp_hw_t *interp, uint lane_mask); - -/*! \brief Release a previously claimed interpolator lane - * \ingroup hardware_interp - * - * \param interp Interpolator on which to release a lane. interp0 or interp1 - * \param lane The lane number, 0 or 1 - */ -void interp_unclaim_lane(interp_hw_t *interp, uint lane); -// The above really should be called this for consistency -#define interp_lane_unclaim interp_unclaim_lane - -/*! \brief Determine if an interpolator lane is claimed - * \ingroup hardware_interp - * - * \param interp Interpolator whose lane to check - * \param lane The lane number, 0 or 1 - * \return true if claimed, false otherwise - * \see interp_claim_lane - * \see interp_claim_lane_mask - */ -bool interp_lane_is_claimed(interp_hw_t *interp, uint lane); - -/*! \brief Release previously claimed interpolator lanes \see interp_claim_lane_mask - * \ingroup hardware_interp - * - * \param interp Interpolator on which to release lanes. interp0 or interp1 - * \param lane_mask Bit pattern of lanes to unclaim (only bits 0 and 1 are valid) - */ -void interp_unclaim_lane_mask(interp_hw_t *interp, uint lane_mask); - -/*! \brief Set the interpolator shift value - * \ingroup interp_config - * - * Sets the number of bits the accumulator is shifted before masking, on each iteration. - * - * \param c Pointer to an interpolator config - * \param shift Number of bits - */ -static inline void interp_config_set_shift(interp_config *c, uint shift) { - valid_params_if(HARDWARE_INTERP, shift < 32); - c->ctrl = (c->ctrl & ~SIO_INTERP0_CTRL_LANE0_SHIFT_BITS) | - ((shift << SIO_INTERP0_CTRL_LANE0_SHIFT_LSB) & SIO_INTERP0_CTRL_LANE0_SHIFT_BITS); -} - -/*! \brief Set the interpolator mask range - * \ingroup interp_config - * - * Sets the range of bits (least to most) that are allowed to pass through the interpolator - * - * \param c Pointer to interpolation config - * \param mask_lsb The least significant bit allowed to pass - * \param mask_msb The most significant bit allowed to pass - */ -static inline void interp_config_set_mask(interp_config *c, uint mask_lsb, uint mask_msb) { - valid_params_if(HARDWARE_INTERP, mask_msb < 32); - valid_params_if(HARDWARE_INTERP, mask_lsb <= mask_msb); - c->ctrl = (c->ctrl & ~(SIO_INTERP0_CTRL_LANE0_MASK_LSB_BITS | SIO_INTERP0_CTRL_LANE0_MASK_MSB_BITS)) | - ((mask_lsb << SIO_INTERP0_CTRL_LANE0_MASK_LSB_LSB) & SIO_INTERP0_CTRL_LANE0_MASK_LSB_BITS) | - ((mask_msb << SIO_INTERP0_CTRL_LANE0_MASK_MSB_LSB) & SIO_INTERP0_CTRL_LANE0_MASK_MSB_BITS); -} - -/*! \brief Enable cross input - * \ingroup interp_config - * - * Allows feeding of the accumulator content from the other lane back in to this lanes shift+mask hardware. - * This will take effect even if the interp_config_set_add_raw option is set as the cross input mux is before the - * shift+mask bypass - * - * \param c Pointer to interpolation config - * \param cross_input If true, enable the cross input. - */ -static inline void interp_config_set_cross_input(interp_config *c, bool cross_input) { - c->ctrl = (c->ctrl & ~SIO_INTERP0_CTRL_LANE0_CROSS_INPUT_BITS) | - (cross_input ? SIO_INTERP0_CTRL_LANE0_CROSS_INPUT_BITS : 0); -} - -/*! \brief Enable cross results - * \ingroup interp_config - * - * Allows feeding of the other lane’s result into this lane’s accumulator on a POP operation. - * - * \param c Pointer to interpolation config - * \param cross_result If true, enables the cross result - */ -static inline void interp_config_set_cross_result(interp_config *c, bool cross_result) { - c->ctrl = (c->ctrl & ~SIO_INTERP0_CTRL_LANE0_CROSS_RESULT_BITS) | - (cross_result ? SIO_INTERP0_CTRL_LANE0_CROSS_RESULT_BITS : 0); -} - -/*! \brief Set sign extension - * \ingroup interp_config - * - * Enables signed mode, where the shifted and masked accumulator value is sign-extended to 32 bits - * before adding to BASE1, and LANE1 PEEK/POP results appear extended to 32 bits when read by processor. - * - * \param c Pointer to interpolation config - * \param _signed If true, enables sign extension - */ -static inline void interp_config_set_signed(interp_config *c, bool _signed) { - c->ctrl = (c->ctrl & ~SIO_INTERP0_CTRL_LANE0_SIGNED_BITS) | - (_signed ? SIO_INTERP0_CTRL_LANE0_SIGNED_BITS : 0); -} - -/*! \brief Set raw add option - * \ingroup interp_config - * - * When enabled, mask + shift is bypassed for LANE0 result. This does not affect the FULL result. - * - * \param c Pointer to interpolation config - * \param add_raw If true, enable raw add option. - */ -static inline void interp_config_set_add_raw(interp_config *c, bool add_raw) { - c->ctrl = (c->ctrl & ~SIO_INTERP0_CTRL_LANE0_ADD_RAW_BITS) | - (add_raw ? SIO_INTERP0_CTRL_LANE0_ADD_RAW_BITS : 0); -} - -/*! \brief Set blend mode - * \ingroup interp_config - * - * If enabled, LANE1 result is a linear interpolation between BASE0 and BASE1, controlled - * by the 8 LSBs of lane 1 shift and mask value (a fractional number between 0 and 255/256ths) - * - * LANE0 result does not have BASE0 added (yields only the 8 LSBs of lane 1 shift+mask value) - * - * FULL result does not have lane 1 shift+mask value added (BASE2 + lane 0 shift+mask) - * - * LANE1 SIGNED flag controls whether the interpolation is signed or unsig - * - * \param c Pointer to interpolation config - * \param blend Set true to enable blend mode. -*/ -static inline void interp_config_set_blend(interp_config *c, bool blend) { - c->ctrl = (c->ctrl & ~SIO_INTERP0_CTRL_LANE0_BLEND_BITS) | - (blend ? SIO_INTERP0_CTRL_LANE0_BLEND_BITS : 0); -} - -/*! \brief Set interpolator clamp mode (Interpolator 1 only) - * \ingroup interp_config - * - * Only present on INTERP1 on each core. If CLAMP mode is enabled: - * - LANE0 result is a shifted and masked ACCUM0, clamped by a lower bound of BASE0 and an upper bound of BASE1. - * - Signedness of these comparisons is determined by LANE0_CTRL_SIGNED - * - * \param c Pointer to interpolation config - * \param clamp Set true to enable clamp mode - */ -static inline void interp_config_set_clamp(interp_config *c, bool clamp) { - c->ctrl = (c->ctrl & ~SIO_INTERP1_CTRL_LANE0_CLAMP_BITS) | - (clamp ? SIO_INTERP1_CTRL_LANE0_CLAMP_BITS : 0); -} - -/*! \brief Set interpolator Force bits - * \ingroup interp_config - * - * ORed into bits 29:28 of the lane result presented to the processor on the bus. - * - * No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence - * of pointers into flash or SRAM - * - * \param c Pointer to interpolation config - * \param bits Sets the force bits to that specified. Range 0-3 (two bits) - */ -static inline void interp_config_set_force_bits(interp_config *c, uint bits) { - invalid_params_if(HARDWARE_INTERP, bits > 3); - // note cannot use hw_set_bits on SIO - c->ctrl = (c->ctrl & ~SIO_INTERP0_CTRL_LANE0_FORCE_MSB_BITS) | - (bits << SIO_INTERP0_CTRL_LANE0_FORCE_MSB_LSB); -} - -/*! \brief Get a default configuration - * \ingroup interp_config - * - * \return A default interpolation configuration - */ -static inline interp_config interp_default_config(void) { - interp_config c = {0}; - // Just pass through everything - interp_config_set_mask(&c, 0, 31); - return c; -} - -/*! \brief Send configuration to a lane - * \ingroup interp_config - * - * If an invalid configuration is specified (ie a lane specific item is set on wrong lane), - * depending on setup this function can panic. - * - * \param interp Interpolator instance, interp0 or interp1. - * \param lane The lane to set - * \param config Pointer to interpolation config - */ - -static inline void interp_set_config(interp_hw_t *interp, uint lane, interp_config *config) { - invalid_params_if(HARDWARE_INTERP, lane > 1); - invalid_params_if(HARDWARE_INTERP, config->ctrl & SIO_INTERP1_CTRL_LANE0_CLAMP_BITS && - (!interp_index(interp) || lane)); // only interp1 lane 0 has clamp bit - invalid_params_if(HARDWARE_INTERP, config->ctrl & SIO_INTERP0_CTRL_LANE0_BLEND_BITS && - (interp_index(interp) || lane)); // only interp0 lane 0 has blend bit - interp->ctrl[lane] = config->ctrl; -} - -/*! \brief Directly set the force bits on a specified lane - * \ingroup hardware_interp - * - * These bits are ORed into bits 29:28 of the lane result presented to the processor on the bus. - * There is no effect on the internal 32-bit datapath. - * - * Useful for using a lane to generate sequence of pointers into flash or SRAM, saving a subsequent - * OR or add operation. - * - * \param interp Interpolator instance, interp0 or interp1. - * \param lane The lane to set - * \param bits The bits to set (bits 0 and 1, value range 0-3) - */ -static inline void interp_set_force_bits(interp_hw_t *interp, uint lane, uint bits) { - // note cannot use hw_set_bits on SIO - interp->ctrl[lane] = interp->ctrl[lane] | (bits << SIO_INTERP0_CTRL_LANE0_FORCE_MSB_LSB); -} - -typedef struct { - uint32_t accum[2]; - uint32_t base[3]; - uint32_t ctrl[2]; -} interp_hw_save_t; - -/*! \brief Save the specified interpolator state - * \ingroup hardware_interp - * - * Can be used to save state if you need an interpolator for another purpose, state - * can then be recovered afterwards and continue from that point - * - * \param interp Interpolator instance, interp0 or interp1. - * \param saver Pointer to the save structure to fill in - */ -void interp_save(interp_hw_t *interp, interp_hw_save_t *saver); - -/*! \brief Restore an interpolator state - * \ingroup hardware_interp - * - * \param interp Interpolator instance, interp0 or interp1. - * \param saver Pointer to save structure to reapply to the specified interpolator - */ -void interp_restore(interp_hw_t *interp, interp_hw_save_t *saver); - -/*! \brief Sets the interpolator base register by lane - * \ingroup hardware_interp - * - * \param interp Interpolator instance, interp0 or interp1. - * \param lane The lane number, 0 or 1 or 2 - * \param val The value to apply to the register - */ -static inline void interp_set_base(interp_hw_t *interp, uint lane, uint32_t val) { - interp->base[lane] = val; -} - -/*! \brief Gets the content of interpolator base register by lane - * \ingroup hardware_interp - * - * \param interp Interpolator instance, interp0 or interp1. - * \param lane The lane number, 0 or 1 or 2 - * \return The current content of the lane base register - */ -static inline uint32_t interp_get_base(interp_hw_t *interp, uint lane) { - return interp->base[lane]; -} - -/*! \brief Sets the interpolator base registers simultaneously - * \ingroup hardware_interp - * - * The lower 16 bits go to BASE0, upper bits to BASE1 simultaneously. - * Each half is sign-extended to 32 bits if that lane’s SIGNED flag is set. - * - * \param interp Interpolator instance, interp0 or interp1. - * \param val The value to apply to the register - */ -static inline void interp_set_base_both(interp_hw_t *interp, uint32_t val) { - interp->base01 = val; -} - - -/*! \brief Sets the interpolator accumulator register by lane - * \ingroup hardware_interp - * - * \param interp Interpolator instance, interp0 or interp1. - * \param lane The lane number, 0 or 1 - * \param val The value to apply to the register - */ -static inline void interp_set_accumulator(interp_hw_t *interp, uint lane, uint32_t val) { - interp->accum[lane] = val; -} - -/*! \brief Gets the content of the interpolator accumulator register by lane - * \ingroup hardware_interp - * - * \param interp Interpolator instance, interp0 or interp1. - * \param lane The lane number, 0 or 1 - * \return The current content of the register - */ -static inline uint32_t interp_get_accumulator(interp_hw_t *interp, uint lane) { - return interp->accum[lane]; -} - -/*! \brief Read lane result, and write lane results to both accumulators to update the interpolator - * \ingroup hardware_interp - * - * \param interp Interpolator instance, interp0 or interp1. - * \param lane The lane number, 0 or 1 - * \return The content of the lane result register - */ -static inline uint32_t interp_pop_lane_result(interp_hw_t *interp, uint lane) { - return interp->pop[lane]; -} - -/*! \brief Read lane result - * \ingroup hardware_interp - * - * \param interp Interpolator instance, interp0 or interp1. - * \param lane The lane number, 0 or 1 - * \return The content of the lane result register - */ -static inline uint32_t interp_peek_lane_result(interp_hw_t *interp, uint lane) { - return interp->peek[lane]; -} - -/*! \brief Read lane result, and write lane results to both accumulators to update the interpolator - * \ingroup hardware_interp - * - * \param interp Interpolator instance, interp0 or interp1. - * \return The content of the FULL register - */ -static inline uint32_t interp_pop_full_result(interp_hw_t *interp) { - return interp->pop[2]; -} - -/*! \brief Read lane result - * \ingroup hardware_interp - * - * \param interp Interpolator instance, interp0 or interp1. - * \return The content of the FULL register - */ -static inline uint32_t interp_peek_full_result(interp_hw_t *interp) { - return interp->peek[2]; -} - -/*! \brief Add to accumulator - * \ingroup hardware_interp - * - * Atomically add the specified value to the accumulator on the specified lane - * - * \param interp Interpolator instance, interp0 or interp1. - * \param lane The lane number, 0 or 1 - * \param val Value to add - */ -static inline void interp_add_accumulater(interp_hw_t *interp, uint lane, uint32_t val) { - interp->add_raw[lane] = val; -} - -/*! \brief Get raw lane value - * \ingroup hardware_interp - * - * Returns the raw shift and mask value from the specified lane, BASE0 is NOT added - * - * \param interp Interpolator instance, interp0 or interp1. - * \param lane The lane number, 0 or 1 - * \return The raw shift/mask value - */ -static inline uint32_t interp_get_raw(interp_hw_t *interp, uint lane) { - return interp->add_raw[lane]; -} - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/lib/main/pico-sdk/rp2_common/hardware_interp/interp.c b/lib/main/pico-sdk/rp2_common/hardware_interp/interp.c deleted file mode 100644 index eaa408b317..0000000000 --- a/lib/main/pico-sdk/rp2_common/hardware_interp/interp.c +++ /dev/null @@ -1,66 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "hardware/interp.h" -#include "hardware/structs/sio.h" -#include "hardware/claim.h" - -check_hw_size(interp_hw_t, SIO_INTERP1_ACCUM0_OFFSET - SIO_INTERP0_ACCUM0_OFFSET); - -check_hw_layout(sio_hw_t, interp, SIO_INTERP0_ACCUM0_OFFSET); - -static uint8_t _claimed; - -static inline uint interp_lane_bit(interp_hw_t * interp, uint lane) { - return (interp_index(interp) << 1u) | lane; -} - -void interp_claim_lane(interp_hw_t *interp, uint lane) { - valid_params_if(HARDWARE_INTERP, lane < 2); - hw_claim_or_assert((uint8_t *) &_claimed, interp_lane_bit(interp, lane), "Lane is already claimed"); -} - -void interp_claim_lane_mask(interp_hw_t *interp, uint lane_mask) { - valid_params_if(HARDWARE_INTERP, lane_mask && lane_mask <= 0x3); - if (lane_mask & 1u) interp_claim_lane(interp, 0); - if (lane_mask & 2u) interp_claim_lane(interp, 1); -} - -void interp_unclaim_lane(interp_hw_t *interp, uint lane) { - valid_params_if(HARDWARE_INTERP, lane < 2); - hw_claim_clear((uint8_t *) &_claimed, interp_lane_bit(interp, lane)); -} - -bool interp_lane_is_claimed(interp_hw_t *interp, uint lane) { - valid_params_if(HARDWARE_INTERP, lane < 2); - return hw_is_claimed((uint8_t *) &_claimed, interp_lane_bit(interp, lane)); -} - -void interp_unclaim_lane_mask(interp_hw_t *interp, uint lane_mask) { - valid_params_if(HARDWARE_INTERP, lane_mask <= 0x3); - if (lane_mask & 1u) interp_unclaim_lane(interp, 0); - if (lane_mask & 2u) interp_unclaim_lane(interp, 1); -} - -void interp_save(interp_hw_t *interp, interp_hw_save_t *saver) { - saver->accum[0] = interp->accum[0]; - saver->accum[1] = interp->accum[1]; - saver->base[0] = interp->base[0]; - saver->base[1] = interp->base[1]; - saver->base[2] = interp->base[2]; - saver->ctrl[0] = interp->ctrl[0]; - saver->ctrl[1] = interp->ctrl[1]; -} - -void interp_restore(interp_hw_t *interp, interp_hw_save_t *saver) { - interp->accum[0] = saver->accum[0]; - interp->accum[1] = saver->accum[1]; - interp->base[0] = saver->base[0]; - interp->base[1] = saver->base[1]; - interp->base[2] = saver->base[2]; - interp->ctrl[0] = saver->ctrl[0]; - interp->ctrl[1] = saver->ctrl[1]; -} diff --git a/lib/main/pico-sdk/rp2_common/hardware_irq/include/hardware/irq.h b/lib/main/pico-sdk/rp2_common/hardware_irq/include/hardware/irq.h deleted file mode 100644 index 78548ad9b2..0000000000 --- a/lib/main/pico-sdk/rp2_common/hardware_irq/include/hardware/irq.h +++ /dev/null @@ -1,496 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _HARDWARE_IRQ_H -#define _HARDWARE_IRQ_H - -// These two config items are also used by assembler, so keeping separate -// PICO_CONFIG: PICO_MAX_SHARED_IRQ_HANDLERS, Maximum number of shared IRQ handlers, default=4, advanced=true, group=hardware_irq -#ifndef PICO_MAX_SHARED_IRQ_HANDLERS -#define PICO_MAX_SHARED_IRQ_HANDLERS 4 -#endif - -// PICO_CONFIG: PICO_DISABLE_SHARED_IRQ_HANDLERS, Disable shared IRQ handlers, type=bool, default=0, group=hardware_irq -#ifndef PICO_DISABLE_SHARED_IRQ_HANDLERS -#define PICO_DISABLE_SHARED_IRQ_HANDLERS 0 -#endif - -// PICO_CONFIG: PICO_VTABLE_PER_CORE, User is using separate vector tables per core, type=bool, default=0, group=hardware_irq -#ifndef PICO_VTABLE_PER_CORE -#define PICO_VTABLE_PER_CORE 0 -#endif - -#ifndef __ASSEMBLER__ - -#include "pico.h" -#include "hardware/address_mapped.h" -#include "hardware/regs/intctrl.h" - -#include "pico/platform/cpu_regs.h" - -/** \file irq.h - * \defgroup hardware_irq hardware_irq - * - * \brief Hardware interrupt handling API - * - * The RP2040 uses the standard ARM nested vectored interrupt controller (NVIC). - * - * Interrupts are identified by a number from 0 to 31. - * - * On the RP2040, only the lower 26 IRQ signals are connected on the NVIC; IRQs 26 to 31 are tied to zero (never firing). - * - * There is one NVIC per core, and each core's NVIC has the same hardware interrupt lines routed to it, with the exception of the IO interrupts - * where there is one IO interrupt per bank, per core. These are completely independent, so, for example, processor 0 can be - * interrupted by GPIO 0 in bank 0, and processor 1 by GPIO 1 in the same bank. - * - * \note That all IRQ APIs affect the executing core only (i.e. the core calling the function). - * - * \note You should not enable the same (shared) IRQ number on both cores, as this will lead to race conditions - * or starvation of one of the cores. Additionally, don't forget that disabling interrupts on one core does not disable interrupts - * on the other core. - * - * There are three different ways to set handlers for an IRQ: - * - Calling irq_add_shared_handler() at runtime to add a handler for a multiplexed interrupt (e.g. GPIO bank) on the current core. Each handler, should check and clear the relevant hardware interrupt source - * - Calling irq_set_exclusive_handler() at runtime to install a single handler for the interrupt on the current core - * - Defining the interrupt handler explicitly in your application (e.g. by defining void `isr_dma_0` will make that function the handler for the DMA_IRQ_0 on core 0, and - * you will not be able to change it using the above APIs at runtime). Using this method can cause link conflicts at runtime, and offers no runtime performance benefit (i.e, it should not generally be used). - * - * \note If an IRQ is enabled and fires with no handler installed, a breakpoint will be hit and the IRQ number will - * be in register r0. - * - * \section interrupt_nums Interrupt Numbers - * - * A set of defines is available (intctrl.h) with these names to avoid using the numbers directly. - * - * \if rp2040_specific - * On RP2040 the interrupt numbers are as follows: - * - * IRQ | Interrupt Source - * ----|----------------- - * 0 | TIMER_IRQ_0 - * 1 | TIMER_IRQ_1 - * 2 | TIMER_IRQ_2 - * 3 | TIMER_IRQ_3 - * 4 | PWM_IRQ_WRAP - * 5 | USBCTRL_IRQ - * 6 | XIP_IRQ - * 7 | PIO0_IRQ_0 - * 8 | PIO0_IRQ_1 - * 9 | PIO1_IRQ_0 - * 10 | PIO1_IRQ_1 - * 11 | DMA_IRQ_0 - * 12 | DMA_IRQ_1 - * 13 | IO_IRQ_BANK0 - * 14 | IO_IRQ_QSPI - * 15 | SIO_IRQ_PROC0 - * 16 | SIO_IRQ_PROC1 - * 17 | CLOCKS_IRQ - * 18 | SPI0_IRQ - * 19 | SPI1_IRQ - * 20 | UART0_IRQ - * 21 | UART1_IRQ - * 22 | ADC0_IRQ_FIFO - * 23 | I2C0_IRQ - * 24 | I2C1_IRQ - * 25 | RTC_IRQ - * \endif - * - * \if rp2350_specific - * On RP2350 the interrupt numbers are as follows: - * - * IRQ | Interrupt Source - * ----|----------------- - * 0 | TIMER0_IRQ_0 - * 1 | TIMER0_IRQ_1 - * 2 | TIMER0_IRQ_2 - * 3 | TIMER0_IRQ_3 - * 4 | TIMER1_IRQ_0 - * 5 | TIMER1_IRQ_1 - * 6 | TIMER1_IRQ_2 - * 7 | TIMER1_IRQ_3 - * 8 | PWM_IRQ_WRAP_0 - * 9 | PWM_IRQ_WRAP_1 - * 10 | DMA_IRQ_0 - * 11 | DMA_IRQ_1 - * 12 | DMA_IRQ_2 - * 13 | DMA_IRQ_3 - * 14 | USBCTRL_IRQ - * 15 | PIO0_IRQ_0 - * 16 | PIO0_IRQ_1 - * 17 | PIO1_IRQ_0 - * 18 | PIO1_IRQ_1 - * 19 | PIO2_IRQ_0 - * 20 | PIO2_IRQ_1 - * 21 | IO_IRQ_BANK0 - * 22 | IO_IRQ_BANK0_NS - * 23 | IO_IRQ_QSPI - * 24 | IO_IRQ_QSPI_NS - * 25 | SIO_IRQ_FIFO - * 26 | SIO_IRQ_BELL - * 27 | SIO_IRQ_FIFO_NS - * 28 | SIO_IRQ_BELL_NS - * 29 | SIO_IRQ_MTIMECMP - * 30 | CLOCKS_IRQ - * 31 | SPI0_IRQ - * 32 | SPI1_IRQ - * 33 | UART0_IRQ - * 34 | UART1_IRQ - * 35 | ADC_IRQ_FIFO - * 36 | I2C0_IRQ - * 37 | I2C1_IRQ - * 38 | OTP_IRQ - * 39 | TRNG_IRQ - * 40 | PROC0_IRQ_CTI - * 41 | PROC1_IRQ_CTI - * 42 | PLL_SYS_IRQ - * 43 | PLL_USB_IRQ - * 44 | POWMAN_IRQ_POW - * 45 | POWMAN_IRQ_TIMER - * 46 | SPAREIRQ_IRQ_0 - * 47 | SPAREIRQ_IRQ_1 - * 48 | SPAREIRQ_IRQ_2 - * 49 | SPAREIRQ_IRQ_3 - * 50 | SPAREIRQ_IRQ_4 - * 51 | SPAREIRQ_IRQ_5 - * \endif - */ - -// PICO_CONFIG: PICO_DEFAULT_IRQ_PRIORITY, Define the default IRQ priority, default=0x80, group=hardware_irq -#ifndef PICO_DEFAULT_IRQ_PRIORITY -#define PICO_DEFAULT_IRQ_PRIORITY 0x80 -#endif - -#define PICO_LOWEST_IRQ_PRIORITY 0xff -#define PICO_HIGHEST_IRQ_PRIORITY 0x00 - -// PICO_CONFIG: PICO_SHARED_IRQ_HANDLER_DEFAULT_ORDER_PRIORITY, Set default shared IRQ order priority, default=0x80, group=hardware_irq -#ifndef PICO_SHARED_IRQ_HANDLER_DEFAULT_ORDER_PRIORITY -#define PICO_SHARED_IRQ_HANDLER_DEFAULT_ORDER_PRIORITY 0x80 -#endif - -#define PICO_SHARED_IRQ_HANDLER_HIGHEST_ORDER_PRIORITY 0xff -#define PICO_SHARED_IRQ_HANDLER_LOWEST_ORDER_PRIORITY 0x00 - -// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_HARDWARE_IRQ, Enable/disable assertions in the hardware_irq module, type=bool, default=0, group=hardware_irq -#ifndef PARAM_ASSERTIONS_ENABLED_HARDWARE_IRQ -#ifdef PARAM_ASSERTIONS_ENABLED_IRQ // backwards compatibility with SDK < 2.0.0 -#define PARAM_ASSERTIONS_ENABLED_HARDWARE_IRQ PARAM_ASSERTIONS_ENABLED_IRQ -#else -#define PARAM_ASSERTIONS_ENABLED_HARDWARE_IRQ 0 -#endif -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -/*! \brief Interrupt handler function type - * \ingroup hardware_irq - * - * All interrupts handlers should be of this type, and follow normal ARM EABI register saving conventions - */ -typedef void (*irq_handler_t)(void); - -static inline void check_irq_param(__unused uint num) { - invalid_params_if(HARDWARE_IRQ, num >= NUM_IRQS); -} - -/*! \brief Set specified interrupt's priority - * \ingroup hardware_irq - * - * \param num Interrupt number \ref interrupt_nums - * \param hardware_priority Priority to set. - * Numerically-lower values indicate a higher priority. Hardware priorities - * range from 0 (highest priority) to 255 (lowest priority). To make it easier to specify - * higher or lower priorities than the default, all IRQ priorities are - * initialized to PICO_DEFAULT_IRQ_PRIORITY by the SDK runtime at startup. - * PICO_DEFAULT_IRQ_PRIORITY defaults to 0x80 - * - * \if rp2040_specific - * Only the top 2 bits are significant on ARM Cortex-M0+ on RP2040. - * \endif - * - * \if rp2350_specific - * Only the top 4 bits are significant on ARM Cortex-M33 or Hazard3 (RISC-V) on RP2350. - * Note that this API uses the same (inverted) ordering as ARM on RISC-V - * \endif - */ -void irq_set_priority(uint num, uint8_t hardware_priority); - -/*! \brief Get specified interrupt's priority - * \ingroup hardware_irq - * - * Numerically-lower values indicate a higher priority. Hardware priorities - * range from 0 (highest priority) to 255 (lowest priority). To make it easier to specify - * higher or lower priorities than the default, all IRQ priorities are - * initialized to PICO_DEFAULT_IRQ_PRIORITY by the SDK runtime at startup. - * PICO_DEFAULT_IRQ_PRIORITY defaults to 0x80 - * - * \if rp2040_specific - * Only the top 2 bits are significant on ARM Cortex-M0+ on RP2040. - * \endif - * - * \if rp2350_specific - * Only the top 4 bits are significant on ARM Cortex-M33 or Hazard3 (RISC-V) on RP2350. - * Note that this API uses the same (inverted) ordering as ARM on RISC-V - * \endif - * - * \param num Interrupt number \ref interrupt_nums - * \return the IRQ priority - */ -uint irq_get_priority(uint num); - -/*! \brief Enable or disable a specific interrupt on the executing core - * \ingroup hardware_irq - * - * \param num Interrupt number \ref interrupt_nums - * \param enabled true to enable the interrupt, false to disable - */ -void irq_set_enabled(uint num, bool enabled); - -/*! \brief Determine if a specific interrupt is enabled on the executing core - * \ingroup hardware_irq - * - * \param num Interrupt number \ref interrupt_nums - * \return true if the interrupt is enabled - */ -bool irq_is_enabled(uint num); - -/*! \brief Enable/disable multiple interrupts on the executing core - * \ingroup hardware_irq - * - * \param mask 32-bit mask with one bits set for the interrupts to enable/disable \ref interrupt_nums - * \param enabled true to enable the interrupts, false to disable them. - */ -void irq_set_mask_enabled(uint32_t mask, bool enabled); - -/*! \brief Enable/disable multiple interrupts on the executing core - * \ingroup hardware_irq - * - * \param n the index of the mask to update. n == 0 means 0->31, n == 1 mean 32->63 etc. - * \param mask 32-bit mask with one bits set for the interrupts to enable/disable \ref interrupt_nums - * \param enabled true to enable the interrupts, false to disable them. - */ -void irq_set_mask_n_enabled(uint n, uint32_t mask, bool enabled); - -/*! \brief Set an exclusive interrupt handler for an interrupt on the executing core. - * \ingroup hardware_irq - * - * Use this method to set a handler for single IRQ source interrupts, or when - * your code, use case or performance requirements dictate that there should - * no other handlers for the interrupt. - * - * This method will assert if there is already any sort of interrupt handler installed - * for the specified irq number. - * - * \param num Interrupt number \ref interrupt_nums - * \param handler The handler to set. See \ref irq_handler_t - * \see irq_add_shared_handler() - */ -void irq_set_exclusive_handler(uint num, irq_handler_t handler); - -/*! \brief Get the exclusive interrupt handler for an interrupt on the executing core. - * \ingroup hardware_irq - * - * This method will return an exclusive IRQ handler set on this core - * by irq_set_exclusive_handler if there is one. - * - * \param num Interrupt number \ref interrupt_nums - * \see irq_set_exclusive_handler() - * \return handler The handler if an exclusive handler is set for the IRQ, - * NULL if no handler is set or shared/shareable handlers are installed - */ -irq_handler_t irq_get_exclusive_handler(uint num); - -/*! \brief Add a shared interrupt handler for an interrupt on the executing core - * \ingroup hardware_irq - * - * Use this method to add a handler on an irq number shared between multiple distinct hardware sources (e.g. GPIO, DMA or PIO IRQs). - * Handlers added by this method will all be called in sequence from highest order_priority to lowest. The - * irq_set_exclusive_handler() method should be used instead if you know there will or should only ever be one handler for the interrupt. - * - * This method will assert if there is an exclusive interrupt handler set for this irq number on this core, or if - * the (total across all IRQs on both cores) maximum (configurable via PICO_MAX_SHARED_IRQ_HANDLERS) number of shared handlers - * would be exceeded. - * - * \param num Interrupt number \ref interrupt_nums - * \param handler The handler to set. See \ref irq_handler_t - * \param order_priority The order priority controls the order that handlers for the same IRQ number on the core are called. - * The shared irq handlers for an interrupt are all called when an IRQ fires, however the order of the calls is based - * on the order_priority (higher priorities are called first, identical priorities are called in undefined order). A good - * rule of thumb is to use PICO_SHARED_IRQ_HANDLER_DEFAULT_ORDER_PRIORITY if you don't much care, as it is in the middle of - * the priority range by default. - * - * \note The order_priority uses \em higher values for higher priorities which is the \em opposite of the CPU interrupt priorities passed - * to irq_set_priority() which use lower values for higher priorities. - * - * \see irq_set_exclusive_handler() - */ -void irq_add_shared_handler(uint num, irq_handler_t handler, uint8_t order_priority); - -/*! \brief Remove a specific interrupt handler for the given irq number on the executing core - * \ingroup hardware_irq - * - * This method may be used to remove an irq set via either irq_set_exclusive_handler() or - * irq_add_shared_handler(), and will assert if the handler is not currently installed for the given - * IRQ number - * - * \note This method may *only* be called from user (non IRQ code) or from within the handler - * itself (i.e. an IRQ handler may remove itself as part of handling the IRQ). Attempts to call - * from another IRQ will cause an assertion. - * - * \param num Interrupt number \ref interrupt_nums - * \param handler The handler to removed. - * \see irq_set_exclusive_handler() - * \see irq_add_shared_handler() - */ -void irq_remove_handler(uint num, irq_handler_t handler); - -/*! \brief Determine if the current handler for the given number is shared - * \ingroup hardware_irq - * - * \param num Interrupt number \ref interrupt_nums - * \return true if the specified IRQ has a shared handler - */ -bool irq_has_shared_handler(uint num); - -/*! \brief Get the current IRQ handler for the specified IRQ from the currently installed hardware vector table (VTOR) - * of the execution core - * \ingroup hardware_irq - * - * \param num Interrupt number \ref interrupt_nums - * \return the address stored in the VTABLE for the given irq number - */ -irq_handler_t irq_get_vtable_handler(uint num); - -/*! \brief Clear a specific interrupt on the executing core - * \ingroup hardware_irq - * - * This method is only useful for "software" IRQs that are not connected to hardware (e.g. IRQs 26-31 on RP2040) - * as the the NVIC always reflects the current state of the IRQ state of the hardware for hardware IRQs, and clearing - * of the IRQ state of the hardware is performed via the hardware's registers instead. - * - * \param int_num Interrupt number \ref interrupt_nums - */ -static inline void irq_clear(uint int_num) { -#if PICO_RP2040 - *((volatile uint32_t *) (PPB_BASE + M0PLUS_NVIC_ICPR_OFFSET)) = (1u << ((uint32_t) (int_num & 0x1F))); -#elif defined(__riscv) - // External IRQs are not latched, but we should clear the IRQ force bit here - hazard3_irqarray_clear(RVCSR_MEIFA_OFFSET, int_num / 16, 1u << (int_num % 16)); -#else - nvic_hw->icpr[int_num/32] = 1 << (int_num % 32); -#endif -} - -/*! \brief Force an interrupt to be pending on the executing core - * \ingroup hardware_irq - * - * This should generally not be used for IRQs connected to hardware. - * - * \param num Interrupt number \ref interrupt_nums - */ -void irq_set_pending(uint num); - - -/*! \brief Perform IRQ priority initialization for the current core - * - * \note This is an internal method and user should generally not call it. - */ -void runtime_init_per_core_irq_priorities(void); - -static __force_inline void irq_init_priorities(void) { - runtime_init_per_core_irq_priorities(); -} - -/*! \brief Claim ownership of a user IRQ on the calling core - * \ingroup hardware_irq - * - * User IRQs starting from FIRST_USER_IRQ are not connected to any hardware, but can be triggered by \ref irq_set_pending. - * - * \note User IRQs are a core local feature; they cannot be used to communicate between cores. Therefore all functions - * dealing with Uer IRQs affect only the calling core - * - * This method explicitly claims ownership of a user IRQ, so other code can know it is being used. - * - * \param irq_num the user IRQ to claim - */ -void user_irq_claim(uint irq_num); - -/*! \brief Mark a user IRQ as no longer used on the calling core - * \ingroup hardware_irq - * - * User IRQs starting from FIRST_USER_IRQ are not connected to any hardware, but can be triggered by \ref irq_set_pending. - * - * \note User IRQs are a core local feature; they cannot be used to communicate between cores. Therefore all functions - * dealing with Uer IRQs affect only the calling core - * - * This method explicitly releases ownership of a user IRQ, so other code can know it is free to use. - * - * \note it is customary to have disabled the irq and removed the handler prior to calling this method. - * - * \param irq_num the irq irq_num to unclaim - */ -void user_irq_unclaim(uint irq_num); - -/*! \brief Claim ownership of a free user IRQ on the calling core - * \ingroup hardware_irq - * - * User IRQs starting from FIRST_USER_IRQ are not connected to any hardware, but can be triggered by \ref irq_set_pending. - * - * \note User IRQs are a core local feature; they cannot be used to communicate between cores. Therefore all functions - * dealing with Uer IRQs affect only the calling core - * - * This method explicitly claims ownership of an unused user IRQ if there is one, so other code can know it is being used. - * - * \param required if true the function will panic if none are available - * \return the user IRQ number or -1 if required was false, and none were free - */ -int user_irq_claim_unused(bool required); - -/* -*! \brief Check if a user IRQ is in use on the calling core - * \ingroup hardware_irq - * - * User IRQs starting from FIRST_USER_IRQ are not connected to any hardware, but can be triggered by \ref irq_set_pending. - * - * \note User IRQs are a core local feature; they cannot be used to communicate between cores. Therefore all functions - * dealing with Uer IRQs affect only the calling core - * - * \param irq_num the irq irq_num - * \return true if the irq_num is claimed, false otherwise - * \sa user_irq_claim - * \sa user_irq_unclaim - * \sa user_irq_claim_unused - */ -bool user_irq_is_claimed(uint irq_num); - -void __unhandled_user_irq(void); - -#ifdef __riscv -enum riscv_vector_num { - RISCV_VEC_MACHINE_EXCEPTION = 0, - RISCV_VEC_MACHINE_SOFTWARE_IRQ = 3, - RISCV_VEC_MACHINE_TIMER_IRQ = 7, - RISCV_VEC_MACHINE_EXTERNAL_IRQ = 11, -}; - -irq_handler_t irq_set_riscv_vector_handler(enum riscv_vector_num index, irq_handler_t handler); -#endif - -#if PICO_SECURE -static inline void irq_assign_to_ns(uint irq_num, bool ns) { - check_irq_param(irq_num); - if (ns) nvic_hw->itns[irq_num >> 5] |= 1u << (irq_num & 0x1fu); - else nvic_hw->itns[irq_num >> 5] &= ~(1u << (irq_num & 0x1fu)); -} -#endif -#ifdef __cplusplus -} -#endif - -#endif -#endif diff --git a/lib/main/pico-sdk/rp2_common/hardware_irq/irq.c b/lib/main/pico-sdk/rp2_common/hardware_irq/irq.c deleted file mode 100644 index 916338858f..0000000000 --- a/lib/main/pico-sdk/rp2_common/hardware_irq/irq.c +++ /dev/null @@ -1,709 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "hardware/irq.h" -#include "pico/runtime_init.h" - -#include "hardware/claim.h" -#include "pico/mutex.h" -#include "pico/assert.h" - -#if defined(PICO_RUNTIME_INIT_PER_CORE_IRQ_PRIORITIES) && !PICO_RUNTIME_SKIP_INIT_PER_CORE_IRQ_PRIORITIES -PICO_RUNTIME_INIT_FUNC_PER_CORE(runtime_init_per_core_irq_priorities, PICO_RUNTIME_INIT_PER_CORE_IRQ_PRIORITIES); -#endif - -#if PICO_VTABLE_PER_CORE -static uint8_t user_irq_claimed[NUM_CORES]; -static inline uint8_t *user_irq_claimed_ptr(void) { - return &user_irq_claimed[get_core_num()]; -} -#else -static uint8_t user_irq_claimed; -static inline uint8_t *user_irq_claimed_ptr(void) { - return &user_irq_claimed; -} -#endif - -static inline irq_handler_t *get_vtable(void) { -#ifdef __riscv - return (irq_handler_t *) (riscv_read_csr(RVCSR_MTVEC_OFFSET) & ~0x3u); -#else - return (irq_handler_t *) scb_hw->vtor; -#endif -} - -static inline void *add_thumb_bit(void *addr) { -#ifdef __riscv - return addr; -#else - return (void *) (((uintptr_t) addr) | 0x1); -#endif -} - -static inline void *remove_thumb_bit(void *addr) { -#ifdef __riscv - return addr; -#else - return (void *) (((uintptr_t) addr) & (uint)~0x1); -#endif -} - -static void set_raw_irq_handler_and_unlock(uint num, irq_handler_t handler, uint32_t save) { - // update vtable (vtable_handler may be same or updated depending on cases, but we do it anyway for compactness) - get_vtable()[VTABLE_FIRST_IRQ + num] = handler; - __dmb(); - spin_unlock(spin_lock_instance(PICO_SPINLOCK_ID_IRQ), save); -} - -void irq_set_enabled(uint num, bool enabled) { - check_irq_param(num); - // really should update irq_set_mask_enabled? - irq_set_mask_n_enabled(num / 32, 1u << (num % 32), enabled); -} - -bool irq_is_enabled(uint num) { - check_irq_param(num); -#if PICO_RP2040 - return 0 != ((1u << num) & *((io_rw_32 *) (PPB_BASE + M0PLUS_NVIC_ISER_OFFSET))); -#elif defined(__riscv) - return 0 != (hazard3_irqarray_read(RVCSR_MEIEA_OFFSET, num / 16) & (1u << (num % 16))); -#else - return 0 != (nvic_hw->iser[num/32] & (1 << num % 32)); -#endif -} - -static inline void irq_set_mask_n_enabled_internal(uint n, uint32_t mask, bool enabled) { - invalid_params_if(HARDWARE_IRQ, n * 32u >= ((NUM_IRQS + 31u) & ~31u)); -#if defined(__riscv) - if (enabled) { - hazard3_irqarray_clear(RVCSR_MEIFA_OFFSET, 2 * n, mask & 0xffffu); - hazard3_irqarray_clear(RVCSR_MEIFA_OFFSET, 2 * n + 1, mask >> 16); - hazard3_irqarray_set(RVCSR_MEIEA_OFFSET, 2 * n, mask & 0xffffu); - hazard3_irqarray_set(RVCSR_MEIEA_OFFSET, 2 * n + 1, mask >> 16); - } else { - hazard3_irqarray_clear(RVCSR_MEIEA_OFFSET, 2 * n, mask & 0xffffu); - hazard3_irqarray_clear(RVCSR_MEIEA_OFFSET, 2 * n + 1, mask >> 16); - } -#elif PICO_RP2040 - ((void)n); - if (enabled) { - nvic_hw->icpr = mask; - nvic_hw->iser = mask; - } else { - nvic_hw->icer = mask; - } -#else - // >32 IRQs (well this works for the bottom 32 which is all that is passed in - if (enabled) { - nvic_hw->icpr[n] = mask; - nvic_hw->iser[n] = mask; - } else { - nvic_hw->icer[n] = mask; - } -#endif -} - -void irq_set_mask_enabled(uint32_t mask, bool enabled) { - irq_set_mask_n_enabled_internal(0, mask, enabled); -} - -void irq_set_mask_n_enabled(uint n, uint32_t mask, bool enabled) { - irq_set_mask_n_enabled_internal(n, mask, enabled); -} - -void irq_set_pending(uint num) { - check_irq_param(num); -#ifdef __riscv - // Interrupt force is subsequently cleared by any read of meinext that - // indicates the forced IRQ (can also be cleared manually) - hazard3_irqarray_set(RVCSR_MEIFA_OFFSET, num / 16, 1u << (num % 16)); -#else -#if PICO_RP2040 - *((io_rw_32 *) (PPB_BASE + M0PLUS_NVIC_ISPR_OFFSET)) = 1u << num; -#else - nvic_hw->ispr[num/32] = 1 << (num % 32); -#endif -#endif -} - -#if !PICO_DISABLE_SHARED_IRQ_HANDLERS -// limited by 8 bit relative links (and reality) -static_assert(PICO_MAX_SHARED_IRQ_HANDLERS >= 1 && PICO_MAX_SHARED_IRQ_HANDLERS < 0x7f, ""); - -// note these are not real functions, they are code fragments (i.e. don't call them) -extern void irq_handler_chain_first_slot(void); -extern void irq_handler_chain_remove_tail(void); - -// On Arm: -// -// - The first slot begins with a tail call to irq_handler_chain_first_slot, passing a pointer to -// the slot in r1; this pushes the initial link register to the stack, invokes the slot's handler -// and then returns into the latter half of the slot -// -// - Non-first slots begin with a call of the slot's handler -// -// - Non-last slots end with a tail into the next slot in the chain -// -// - The last slot ends with a pop of the return address pushed by irq_handler_chain_first_slot -// -// On RISC-V: -// -// - The first slot begins with jal t0, irq_handler_first_chain_slot followed by a 32-bit pointer to -// the handler; this pushes the ultimate return address to the stack, invokes the slot's handler -// and then returns into the latter half of the slot -// -// - Non-first slots begin with an lui; jalr sequence to call the handler -// -// - Non-last slots end with a tail into the next slot in the chain -// -// - The last slot ends with a pop of the return address pushed by irq_handler_chain_first_slot -// -// This means the layout is different between Arm and RISC-V (though total size is the same): Arm is -// 6 bytes of code, 2 bytes of link and 4 bytes of pointer. RISC-V is 10 bytes of code and 2 bytes -// of link. - -extern struct irq_handler_chain_slot { -#ifndef __riscv - uint16_t inst1; - uint16_t inst2; -#else - uint32_t inst1; - uint32_t inst2; -#endif - uint16_t inst3; - union { - // On Arm, when a handler is removed while executing, it needs a 32-bit instruction at - // inst3, which overwrites the link and the priority; this is ok because no one else is - // modifying the chain, as the chain is effectively core-local, and the user code which - // might still need this link disables the IRQ in question before updating, which means we - // aren't executing! - struct { - int8_t link; - uint8_t priority; - }; - uint16_t inst4; - }; -#ifndef __riscv - irq_handler_t handler; -#endif -} irq_handler_chain_slots[PICO_MAX_SHARED_IRQ_HANDLERS]; - -static int8_t irq_handler_chain_free_slot_head; - -static inline bool is_shared_irq_raw_handler(irq_handler_t raw_handler) { - return (uintptr_t)raw_handler - (uintptr_t)irq_handler_chain_slots < sizeof(irq_handler_chain_slots); -} - -bool irq_has_shared_handler(uint irq_num) { - check_irq_param(irq_num); - irq_handler_t handler = irq_get_vtable_handler(irq_num); - return handler && is_shared_irq_raw_handler(handler); -} - -#else // PICO_DISABLE_SHARED_IRQ_HANDLERS -#define is_shared_irq_raw_handler(h) false -bool irq_has_shared_handler(uint irq_num) { - return false; -} -#endif - - -irq_handler_t irq_get_vtable_handler(uint num) { - check_irq_param(num); - return get_vtable()[VTABLE_FIRST_IRQ + num]; -} - -void irq_set_exclusive_handler(uint num, irq_handler_t handler) { - check_irq_param(num); -#if !PICO_NO_RAM_VECTOR_TABLE - spin_lock_t *lock = spin_lock_instance(PICO_SPINLOCK_ID_IRQ); - uint32_t save = spin_lock_blocking(lock); - __unused irq_handler_t current = irq_get_vtable_handler(num); - hard_assert(current == __unhandled_user_irq || current == handler); - set_raw_irq_handler_and_unlock(num, handler, save); -#else - panic_unsupported(); -#endif -} - -irq_handler_t irq_get_exclusive_handler(uint num) { - check_irq_param(num); -#if !PICO_NO_RAM_VECTOR_TABLE - spin_lock_t *lock = spin_lock_instance(PICO_SPINLOCK_ID_IRQ); - uint32_t save = spin_lock_blocking(lock); - irq_handler_t current = irq_get_vtable_handler(num); - spin_unlock(lock, save); - if (current == __unhandled_user_irq || is_shared_irq_raw_handler(current)) { - return NULL; - } - return current; -#else - panic_unsupported(); -#endif -} - - -#if !PICO_DISABLE_SHARED_IRQ_HANDLERS - -#ifndef __riscv - -static uint16_t make_j_16(uint16_t *from, void *to) { - uint32_t ui_from = (uint32_t)from; - uint32_t ui_to = (uint32_t)to; - int32_t delta = (int32_t)(ui_to - ui_from - 4); - assert(delta >= -2048 && delta <= 2046 && !(delta & 1)); - return (uint16_t)(0xe000 | ((delta >> 1) & 0x7ff)); -} - -static void insert_bl_32(uint16_t *from, void *to) { - uint32_t ui_from = (uint32_t)from; - uint32_t ui_to = (uint32_t)to; - uint32_t delta = (ui_to - ui_from - 4) / 2; - assert(!(delta >> 11u)); - from[0] = (uint16_t)(0xf000 | ((delta >> 11u) & 0x7ffu)); - from[1] = (uint16_t)(0xf800 | (delta & 0x7ffu)); -} - -static inline void *resolve_j_16(uint16_t *inst) { - assert(0x1c == (*inst)>>11u); - int32_t i_addr = (*inst) << 21u; - i_addr /= (int32_t)(1u<<21u); - return inst + 2 + i_addr; -} - -#else - -static uint16_t make_jal_16(uint16_t *from, void *to) { - uint32_t ui_from = (uint32_t)from; - uint32_t ui_to = (uint32_t)to; - int32_t delta = (int32_t)(ui_to - ui_from); - assert(delta >= -2048 && delta <= 2046 && !(delta & 1)); - return 0x2001u | riscv_encode_imm_cj((uint32_t)delta); -} - -static uint16_t make_j_16(uint16_t *from, void *to) { - return 0x8000u | make_jal_16(from, to); -} - -static inline uint32_t make_call_inst1(void *to) { - // lui ra, %hi(to) - return 0x000000b7u | riscv_encode_imm_u_hi((uintptr_t)to); -} - -static inline uint32_t make_call_inst2(void *to) { - // jalr ra, %lo(to)(ra) - return 0x000080e7u | riscv_encode_imm_i((uintptr_t)to); -} - -static inline uint32_t make_jal_t0_32(uint32_t *from, void *to) { - // jal t0, to - return 0x000002efu | riscv_encode_imm_j((uintptr_t)to - (uintptr_t)from); -} - -static void *resolve_j_16(uint16_t *inst) { - uint32_t inst32 = (uint32_t)*inst; - uint32_t udiff = - ((inst32 & 0x0038) >> 2) + - ((inst32 & 0x0800) >> 7) + - ((inst32 & 0x0004) << 3) + - ((inst32 & 0x0080) >> 1) + - ((inst32 & 0x0040) << 1) + - ((inst32 & 0x0600) >> 1) + - ((inst32 & 0x0100) << 2) - - ((inst32 & 0x2000) >> 2); - return (void *)((uint32_t)inst + udiff); -} - -#endif - -// GCC produces horrible code for subtraction of pointers here, and it was bugging me -static inline int8_t slot_diff(struct irq_handler_chain_slot *to, struct irq_handler_chain_slot *from) { - static_assert(sizeof(struct irq_handler_chain_slot) == 12, ""); -#ifdef __riscv - // todo I think RISC-V also deserves a fancy pointer diff implementation - return (int8_t)(to - from); -#else - int32_t result = 0xaaaa; - // return (to - from); - // note this implementation has limited range, but is fine for plenty more than -128->127 result - pico_default_asm ( - "subs %1, %2\n" - "adcs %1, %1\n" // * 2 (and + 1 if negative for rounding) - "muls %0, %1\n" - "lsrs %0, %0, #20\n" - : "+l" (result), "+l" (to) - : "l" (from) - : "cc" - ); - return (int8_t)result; -#endif -} - -#ifndef __riscv -static const uint16_t inst16_return_from_last_slot = 0xbd01; // pop {r0, pc} -#else -static const uint16_t inst16_return_from_last_slot = 0xbe42; // cm.popret {ra}, 16 -#endif - -static inline int8_t get_slot_index(struct irq_handler_chain_slot *slot) { - return slot_diff(slot, irq_handler_chain_slots); -} -#endif - -void irq_add_shared_handler(uint num, irq_handler_t handler, uint8_t order_priority) { - check_irq_param(num); -#if PICO_NO_RAM_VECTOR_TABLE - panic_unsupported(); -#elif PICO_DISABLE_SHARED_IRQ_HANDLERS - irq_set_exclusive_handler(num, handler); -#else - spin_lock_t *lock = spin_lock_instance(PICO_SPINLOCK_ID_IRQ); - uint32_t save = spin_lock_blocking(lock); - hard_assert(irq_handler_chain_free_slot_head >= 0); // we must have a slot - struct irq_handler_chain_slot *slot = &irq_handler_chain_slots[irq_handler_chain_free_slot_head]; - int8_t slot_index = irq_handler_chain_free_slot_head; - irq_handler_chain_free_slot_head = slot->link; - irq_handler_t vtable_handler = get_vtable()[VTABLE_FIRST_IRQ + num]; - if (!is_shared_irq_raw_handler(vtable_handler)) { - // start new chain - hard_assert(vtable_handler == __unhandled_user_irq); - struct irq_handler_chain_slot slot_data = { -#ifndef __riscv - .inst1 = 0xa100, // add r1, pc, #0 - .inst2 = make_j_16(&slot->inst2, (void *) irq_handler_chain_first_slot), // b irq_handler_chain_first_slot - .handler = handler, -#else - .inst1 = make_jal_t0_32(&slot->inst1, irq_handler_chain_first_slot), // jal t0, irq_handler_chain_first_slot - .inst2 = (uint32_t)handler, // (t0 points to handler) -#endif - .inst3 = inst16_return_from_last_slot, - .link = -1, - .priority = order_priority - }; - *slot = slot_data; - vtable_handler = (irq_handler_t)add_thumb_bit(slot); - } else { - assert(!((((uintptr_t)remove_thumb_bit(vtable_handler)) - ((uintptr_t)irq_handler_chain_slots)) % sizeof(struct irq_handler_chain_slot))); - struct irq_handler_chain_slot *prev_slot = NULL; - struct irq_handler_chain_slot *existing_vtable_slot = remove_thumb_bit((void *) vtable_handler); - struct irq_handler_chain_slot *cur_slot = existing_vtable_slot; - while (cur_slot->priority > order_priority) { - prev_slot = cur_slot; - if (cur_slot->link < 0) break; - cur_slot = &irq_handler_chain_slots[cur_slot->link]; - } - if (prev_slot) { - // insert into chain - struct irq_handler_chain_slot slot_data = { -#ifndef __riscv - .inst1 = 0x4801, // ldr r0, [pc, #4] - .inst2 = 0x4780, // blx r0 - .handler = handler, -#else - .inst1 = make_call_inst1(handler), // lui ra, %hi(handler) - .inst2 = make_call_inst2(handler), // jalr ra, %lo(handler)(ra) -#endif - .inst3 = prev_slot->link >= 0 ? - make_j_16(&slot->inst3, resolve_j_16(&prev_slot->inst3)) : // b next_slot - inst16_return_from_last_slot, - .link = prev_slot->link, - .priority = order_priority - }; - // update code and data links - prev_slot->inst3 = make_j_16(&prev_slot->inst3, slot), - prev_slot->link = slot_index; - *slot = slot_data; - } else { - // update with new chain head - struct irq_handler_chain_slot slot_data = { -#ifndef __riscv - .inst1 = 0xa100, // add r1, pc, #0 - .inst2 = make_j_16(&slot->inst2, (void *) irq_handler_chain_first_slot), // b irq_handler_chain_first_slot - .handler = handler, -#else - .inst1 = make_jal_t0_32(&slot->inst1, irq_handler_chain_first_slot), // jal t0, irq_handler_chain_first_slot - .inst2 = (uint32_t)handler, // (t0 points to handler) -#endif - .inst3 = make_j_16(&slot->inst3, existing_vtable_slot), // b existing_slot - .link = get_slot_index(existing_vtable_slot), - .priority = order_priority, - }; - *slot = slot_data; - // fixup previous head slot -#ifndef __riscv - existing_vtable_slot->inst1 = 0x4801; // ldr r0, [pc, #4] - existing_vtable_slot->inst2 = 0x4780; // blx r0 -#else - // todo lock-freeness? - void *handler_of_existing_head = (void*)existing_vtable_slot->inst2; - existing_vtable_slot->inst1 = make_call_inst1(handler_of_existing_head); - existing_vtable_slot->inst2 = make_call_inst2(handler_of_existing_head); -#endif - vtable_handler = (irq_handler_t)add_thumb_bit(slot); - } - } - set_raw_irq_handler_and_unlock(num, vtable_handler, save); -#endif // !PICO_NO_RAM_VECTOR_TABLE && !PICO_DISABLE_SHARED_IRQ_HANDLERS -} - -#if !PICO_DISABLE_SHARED_IRQ_HANDLERS -static inline irq_handler_t handler_from_slot(struct irq_handler_chain_slot *slot) { -#ifndef __riscv - return slot->handler; -#else - if (slot->inst1 & 0x8u) { - // jal t0, irq_handler_chain_first_slot; .word handler - return (irq_handler_t)slot->inst2; - } else { - // lui ra, %hi(handler); jalr ra, %lo(handler)(ra) - return (irq_handler_t)( - ((slot->inst1 >> 12) << 12) + (uint32_t)((int32_t)slot->inst2 >> 20) - ); - } -#endif -} -#endif - -void irq_remove_handler(uint num, irq_handler_t handler) { -#if !PICO_NO_RAM_VECTOR_TABLE - spin_lock_t *lock = spin_lock_instance(PICO_SPINLOCK_ID_IRQ); - uint32_t save = spin_lock_blocking(lock); - irq_handler_t vtable_handler = get_vtable()[VTABLE_FIRST_IRQ + num]; - if (vtable_handler != __unhandled_user_irq && vtable_handler != handler) { -#if !PICO_DISABLE_SHARED_IRQ_HANDLERS - if (is_shared_irq_raw_handler(vtable_handler)) { - // This is a bit tricky, as an executing IRQ handler doesn't take a lock. - - // First thing to do is to disable the IRQ in question; that takes care of calls from user code. - // Note that a irq handler chain is local to our own core, so we don't need to worry about the other core - bool was_enabled = irq_is_enabled(num); - irq_set_enabled(num, false); - __dmb(); - - // It is possible we are being called while an IRQ for this chain is already in progress. - // The issue we have here is that we must not free a slot that is currently being executed, because - // inst3 is still to be executed, and inst3 might get overwritten if the slot is re-used. - - // By disallowing other exceptions from removing an IRQ handler (which seems fair) - // we now only have to worry about removing a slot from a chain that is currently executing. - - // Note we expect that the slot we are deleting is the one that is executing. - // In particular, bad things happen if the caller were to delete the handler in the chain - // before it. This is not an allowed use case though, and I can't imagine anyone wanting to in practice. - // Sadly this is not something we can detect. - - uint exception = __get_current_exception(); - hard_assert(!exception || exception == num + VTABLE_FIRST_IRQ); - - struct irq_handler_chain_slot *prev_slot = NULL; - struct irq_handler_chain_slot *existing_vtable_slot = remove_thumb_bit((void *) vtable_handler); - struct irq_handler_chain_slot *to_free_slot = existing_vtable_slot; - while (handler_from_slot(to_free_slot) != handler) { - prev_slot = to_free_slot; - if (to_free_slot->link < 0) break; - to_free_slot = &irq_handler_chain_slots[to_free_slot->link]; - } - if (handler_from_slot(to_free_slot) == handler) { - int8_t next_slot_index = to_free_slot->link; - if (next_slot_index >= 0) { - // There is another slot in the chain, so copy that over us, so that our inst3 points at something valid - // Note this only matters in the exception case anyway, and it that case, we will skip the next handler, - // however in that case its IRQ cause should immediately cause re-entry of the IRQ and the only side - // effect will be that there was potentially brief out of priority order execution of the handlers - struct irq_handler_chain_slot *next_slot = &irq_handler_chain_slots[next_slot_index]; -#ifndef __riscv - to_free_slot->handler = next_slot->handler; -#else - irq_handler_t handler_of_next_slot = handler_from_slot(next_slot); - if (to_free_slot == existing_vtable_slot) { - to_free_slot->inst2 = (uint32_t)handler_of_next_slot; - } else { - to_free_slot->inst1 = make_call_inst1(handler_of_next_slot); - to_free_slot->inst2 = make_call_inst2(handler_of_next_slot); - } -#endif - to_free_slot->priority = next_slot->priority; - to_free_slot->link = next_slot->link; - to_free_slot->inst3 = next_slot->link >= 0 ? - make_j_16(&to_free_slot->inst3, resolve_j_16(&next_slot->inst3)) : // b next_>slot->next_slot - inst16_return_from_last_slot, - - // add old next slot back to free list - next_slot->link = irq_handler_chain_free_slot_head; - irq_handler_chain_free_slot_head = next_slot_index; - } else { - // Slot being removed is at the end of the chain - if (!exception) { - // case when we're not in exception, we physically unlink now - if (prev_slot) { - // chain is not empty - prev_slot->link = -1; - prev_slot->inst3 = inst16_return_from_last_slot; - } else { - // chain is not empty - vtable_handler = __unhandled_user_irq; - } - // add slot back to free list - to_free_slot->link = irq_handler_chain_free_slot_head; - irq_handler_chain_free_slot_head = get_slot_index(to_free_slot); - } else { - // since we are the last slot we know that our inst3 hasn't executed yet, so we change - // it to bl to irq_handler_chain_remove_tail which will remove the slot. -#ifndef __riscv - // NOTE THAT THIS TRASHES PRIORITY AND LINK SINCE THIS IS A 4 BYTE INSTRUCTION - // BUT THEY ARE NOT NEEDED NOW - insert_bl_32(&to_free_slot->inst3, (void *) irq_handler_chain_remove_tail); -#else - to_free_slot->inst3 = make_jal_16(&to_free_slot->inst3, (void*) irq_handler_chain_remove_tail); -#endif - } - } - } else { - assert(false); // not found - } - irq_set_enabled(num, was_enabled); - } -#else - assert(false); // not found -#endif - } else { - vtable_handler = __unhandled_user_irq; - } - set_raw_irq_handler_and_unlock(num, vtable_handler, save); -#else - panic_unsupported(); -#endif -} - -#ifndef __riscv -static io_rw_32 *nvic_ipr0(void) { - return (io_rw_32 *)(PPB_BASE + ARM_CPU_PREFIXED(NVIC_IPR0_OFFSET)); -} -#endif - -void irq_set_priority(uint num, uint8_t hardware_priority) { - check_irq_param(num); -#ifdef __riscv - // SDK priorities are upside down due to Cortex-M influence - hardware_priority = (uint8_t)((hardware_priority >> 4) ^ 0xf); - // There is no atomic field write operation, so first drop the IRQ to its - // lowest priority (safe even if it is in a preemption frame below us) and - // then use a set to raise it to the target priority. - hazard3_irqarray_clear(RVCSR_MEIPRA_OFFSET, num / 4, 0xfu << (4 * (num % 4))); - hazard3_irqarray_set(RVCSR_MEIPRA_OFFSET, num / 4, hardware_priority << (4 * (num % 4))); -#else - io_rw_32 *p = nvic_ipr0() + (num >> 2); - // note that only 32 bit writes are supported - *p = (*p & ~(0xffu << (8 * (num & 3u)))) | (((uint32_t) hardware_priority) << (8 * (num & 3u))); -#endif -} - -uint irq_get_priority(uint num) { - check_irq_param(num); -#ifdef __riscv - uint16_t priority_row = (uint16_t) hazard3_irqarray_read(RVCSR_MEIPRA_OFFSET, num / 4u); - uint8_t priority_4bit = (priority_row >> (4 * (num % 4))) & 0xfu; - return ((priority_4bit ^ 0xfu) << 4u); -#else - // note that only 32 bit reads are supported - io_rw_32 *p = nvic_ipr0() + (num >> 2); - return (uint8_t)(*p >> (8 * (num & 3u))); -#endif -} - -#if !PICO_DISABLE_SHARED_IRQ_HANDLERS -// used by irq_handler_chain.S to remove the last link in a handler chain after it executes -// note this must be called only with the last slot in a chain (and during the exception) -void irq_add_tail_to_free_list(struct irq_handler_chain_slot *slot) { - irq_handler_t slot_handler = (irq_handler_t) add_thumb_bit(slot); - assert(is_shared_irq_raw_handler(slot_handler)); - - uint exception = __get_current_exception(); - assert(exception); - spin_lock_t *lock = spin_lock_instance(PICO_SPINLOCK_ID_IRQ); - uint32_t save = spin_lock_blocking(lock); - int8_t slot_index = get_slot_index(slot); - if (slot_handler == get_vtable()[exception]) { - get_vtable()[exception] = __unhandled_user_irq; - } else { - bool __unused found = false; - // need to find who points at the slot and update it - for(uint i=0;ilink = irq_handler_chain_free_slot_head; - irq_handler_chain_free_slot_head = slot_index; - spin_unlock(lock, save); -} -#endif - -__weak void runtime_init_per_core_irq_priorities(void) { -#if PICO_DEFAULT_IRQ_PRIORITY != 0 -#ifndef __riscv - // static_assert(!(NUM_IRQS & 3), ""); // this isn't really required - the reg is still 32 bit - uint32_t prio4 = (PICO_DEFAULT_IRQ_PRIORITY & 0xff) * 0x1010101u; - io_rw_32 *p = nvic_ipr0(); - for (uint i = 0; i < (NUM_IRQS + 3) / 4; i++) { - *p++ = prio4; - } -#else - for (uint i = 0; i < NUM_IRQS; ++i) { - irq_set_priority(i, PICO_DEFAULT_IRQ_PRIORITY); - } -#endif -#endif -} - -static uint get_user_irq_claim_index(uint irq_num) { - invalid_params_if(HARDWARE_IRQ, irq_num < FIRST_USER_IRQ || irq_num >= NUM_IRQS); - // we count backwards from the last, to match the existing hard coded uses of user IRQs in the SDK which were previously using 31 - static_assert(NUM_IRQS - FIRST_USER_IRQ <= 8, ""); // we only use a single byte's worth of claim bits today. - return NUM_IRQS - irq_num - 1u; -} - -void user_irq_claim(uint irq_num) { - hw_claim_or_assert(user_irq_claimed_ptr(), get_user_irq_claim_index(irq_num), "User IRQ is already claimed"); -} - -void user_irq_unclaim(uint irq_num) { - hw_claim_clear(user_irq_claimed_ptr(), get_user_irq_claim_index(irq_num)); -} - -int user_irq_claim_unused(bool required) { - int bit = hw_claim_unused_from_range(user_irq_claimed_ptr(), required, 0, NUM_USER_IRQS - 1, "No user IRQs are available"); - if (bit >= 0) bit = (int)NUM_IRQS - bit - 1; - return bit; -} - -bool user_irq_is_claimed(uint irq_num) { - return hw_is_claimed(user_irq_claimed_ptr(), get_user_irq_claim_index(irq_num)); -} - -#ifdef __riscv -static uint32_t encode_j_instruction(uintptr_t from, uintptr_t to) { - intptr_t delta = (intptr_t) (to - from); - invalid_params_if(HARDWARE_IRQ, delta & 1); - valid_params_if(HARDWARE_IRQ, ((delta >> 21) == 0 || (delta >> 21) == -1)); // range check +- 1 MiB - return 0x6fu | riscv_encode_imm_j((uint32_t)delta); -} - -irq_handler_t irq_set_riscv_vector_handler(enum riscv_vector_num index, irq_handler_t handler) { - invalid_params_if(HARDWARE_IRQ, index > RISCV_VEC_MACHINE_EXTERNAL_IRQ); - irq_handler_t *vtable = get_vtable(); - valid_params_if(HARDWARE_IRQ, ((uintptr_t)vtable & 0x3) == 0x1); // check we are in vector mode - irq_handler_t old = vtable[index]; - vtable[index] = (irq_handler_t)encode_j_instruction((uintptr_t)&vtable[index], (uintptr_t)handler); - return old; -} -#endif diff --git a/lib/main/pico-sdk/rp2_common/hardware_irq/irq_handler_chain.S b/lib/main/pico-sdk/rp2_common/hardware_irq/irq_handler_chain.S deleted file mode 100644 index fd4141a5ba..0000000000 --- a/lib/main/pico-sdk/rp2_common/hardware_irq/irq_handler_chain.S +++ /dev/null @@ -1,94 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "pico.h" -#include "hardware/irq.h" -#include "pico/asm_helper.S" - -pico_default_asm_setup - -#if !PICO_DISABLE_SHARED_IRQ_HANDLERS - -.data -.align 2 - -.global irq_handler_chain_slots - -.global irq_handler_chain_first_slot -.global irq_handler_chain_remove_tail - -// -// These Slots make up the code and structure of the handler chains; the only external information are the VTABLE entries -// (obviously one set per core) and a free list head. Each individual handler chain starts with the VTABLE entry I -// pointing at the address of slot S (with thumb bit set). Thus each slot which is part of a chain is executable. -// -// The execution jumps (via branch instruction) from one slot to the other, then jumps to the end of chain handler. -// The entirety of the state needed to traverse the chain is contained within the slots of the chain, which is why -// a VTABLE entry is all that is needed per chain (rather than requiring a separarte set of head pointers) -// - -irq_handler_chain_slots: -.set next_slot_number, 1 -.rept PICO_MAX_SHARED_IRQ_HANDLERS - // a slot is executable and is always 3 instructions long. -#ifndef __riscv - .hword 0 // inst1 (either: ldr r0, [pc, #4] or for the FIRST slot: add r1, pc, #0 ) - .hword 0 // inst2 ( blx r0 b irq_handler_chain_first_slot ) - - .hword 0 // inst3 (either: b next_slot or for the LAST pop {pc} ) -#else - .word 0 // inst1 (either: lui ra, %hi(handler) or for the FIRST slot: jal t0, irq_handler_chain_first_slot) - .word 0 // inst2 (either: jalr ra. %lo(handler)(ra) .word handler ) - - .hword 0 // inst3 (either: j next_slot or for the LAST slot: cm.popret {ra}, 16 ) -#endif - - // next is a single byte index of next slot in chain (or -1 to end) -.if next_slot_number == PICO_MAX_SHARED_IRQ_HANDLERS - .byte 0xff -.else - .byte next_slot_number -.endif - // next is the 8 bit unsigned priority - .byte 0x00 -1: - // and finally the handler function pointer for Arm: -#ifndef __riscv - .word 0x0000000 -#endif - .set next_slot_number, next_slot_number + 1 -.endr - -irq_handler_chain_first_slot: -#ifndef __riscv - push {r0, lr} // Save EXC_RETURN token, so `pop {r0, pc}` will return from interrupt - // Note that r0 does not NEED to be saved, however we must maintain - // an 8 byte stack alignment, and this is the cheapest way to do so - ldr r0, [r1, #4] // Get `handler` field of irq_handler_chain_slot - adds r1, #1 // r1 points to `inst3` field of slot struct. Set Thumb bit on r1, - mov lr, r1 // and copy to lr, so `inst3` is executed on return from handler - bx r0 // Enter handler -#else - .insn 0xb842 // cm.push {ra}, -16: Save ultimate return address - add ra, t0, 4 // Set up function call to return to offset 8 of the slot - lw t0, (t0) // Load pointer from offset 4 of the slot - jr t0 // Call it, with our calculated return address -#endif - -irq_handler_chain_remove_tail: -#ifndef __riscv - mov r0, lr // Get start of struct. This function was called by a bl at offset +4, - subs r0, #9 // so lr points to offset +8. Note also lr has its Thumb bit set! - ldr r1, =irq_add_tail_to_free_list - blx r1 - pop {r0, pc} // Top of stack is EXC_RETURN -#else - add a0, ra, -10 // Expect to be called with a 16-bit jal, at 8-byte offset in the slot. - call irq_add_tail_to_free_list - .insn 0xbe42 // cm.popret {ra}, 16 -#endif - -#endif diff --git a/lib/main/pico-sdk/rp2_common/hardware_pio/include/hardware/pio.h b/lib/main/pico-sdk/rp2_common/hardware_pio/include/hardware/pio.h deleted file mode 100644 index 2adab14dab..0000000000 --- a/lib/main/pico-sdk/rp2_common/hardware_pio/include/hardware/pio.h +++ /dev/null @@ -1,1889 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _HARDWARE_PIO_H -#define _HARDWARE_PIO_H - -#include "pico.h" -#include "hardware/address_mapped.h" -#include "hardware/structs/pio.h" -#include "hardware/gpio.h" -#include "hardware/regs/dreq.h" -#include "hardware/pio_instructions.h" - -// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_HARDWARE_PIO, Enable/disable assertions in the hardware_pio module, type=bool, default=0, group=hardware_pio -#ifndef PARAM_ASSERTIONS_ENABLED_HARDWARE_PIO -#ifdef PARAM_ASSERTIONS_ENABLED_PIO // backwards compatibility with SDK < 2.0.0 -#define PARAM_ASSERTIONS_ENABLED_HARDWARE_PIO PARAM_ASSERTIONS_ENABLED_PIO -#else -#define PARAM_ASSERTIONS_ENABLED_HARDWARE_PIO 0 -#endif -#endif - -// PICO_CONFIG: PICO_PIO_VERSION, PIO hardware version, type=int, default=0 on RP2040 and 1 on RP2350, group=hardware_pio -#ifndef PICO_PIO_VERSION -#if PIO_GPIOBASE_BITS -#define PICO_PIO_VERSION 1 -#else -#define PICO_PIO_VERSION 0 -#endif -#endif -/** \file hardware/pio.h - * \defgroup hardware_pio hardware_pio - * - * \brief Programmable I/O (PIO) API - * - * A programmable input/output block (PIO) is a versatile hardware interface which - * can support a number of different IO standards. - * - * \if rp2040_specific - * There are two PIO blocks in the RP2040. - * \endif - * - * \if rp2350_specific - * There are three PIO blocks in the RP2350 - * \endif - * - * Each PIO is programmable in the same sense as a processor: the four state machines independently - * execute short, sequential programs, to manipulate GPIOs and transfer data. Unlike a general - * purpose processor, PIO state machines are highly specialised for IO, with a focus on determinism, - * precise timing, and close integration with fixed-function hardware. Each state machine is equipped - * with: - * * Two 32-bit shift registers – either direction, any shift count - * * Two 32-bit scratch registers - * * 4×32 bit bus FIFO in each direction (TX/RX), reconfigurable as 8×32 in a single direction - * * Fractional clock divider (16 integer, 8 fractional bits) - * * Flexible GPIO mapping - * * DMA interface, sustained throughput up to 1 word per clock from system DMA - * * IRQ flag set/clear/status - * - * Full details of the PIO can be found in the appropriate RP-series datasheet. Note that there are - * additional features in the RP2350 PIO implementation that mean care should be taken when writing PIO - * code that needs to run on both the RP2040 and the RP2350. - */ - -#ifdef __cplusplus -extern "C" { -#endif - -static_assert(PIO_SM0_SHIFTCTRL_FJOIN_RX_LSB == PIO_SM0_SHIFTCTRL_FJOIN_TX_LSB + 1, ""); - -/** \brief FIFO join states - * \ingroup hardware_pio - */ -enum pio_fifo_join { - PIO_FIFO_JOIN_NONE = 0, ///< TX FIFO length=4 is used for transmit, RX FIFO length=4 is used for receive - PIO_FIFO_JOIN_TX = 1, ///< TX FIFO length=8 is used for transmit, RX FIFO is disabled - PIO_FIFO_JOIN_RX = 2, ///< RX FIFO length=8 is used for receive, TX FIFO is disabled -#if PICO_PIO_VERSION > 0 - PIO_FIFO_JOIN_TXGET = 4, ///< TX FIFO length=4 is used for transmit, RX FIFO is disabled; space is used for "get" instructions or processor writes - PIO_FIFO_JOIN_TXPUT = 8, ///< TX FIFO length=4 is used for transmit, RX FIFO is disabled; space is used for "put" instructions or processor reads - PIO_FIFO_JOIN_PUTGET = 12, ///< TX FIFO length=4 is used for transmit, RX FIFO is disabled; space is used for "put"/"get" instructions with no processor access -#endif -}; - -/** \brief MOV status types - * \ingroup hardware_pio - */ -enum pio_mov_status_type { - STATUS_TX_LESSTHAN = 0, - STATUS_RX_LESSTHAN = 1, -#if PICO_PIO_VERSION > 0 - STATUS_IRQ_SET = 2 -#endif -}; - -typedef pio_hw_t *PIO; - -/** Identifier for the first (PIO 0) hardware PIO instance (for use in PIO functions). - * - * e.g. pio_gpio_init(pio0, 5) - * - * \ingroup hardware_pio - */ -#define pio0 pio0_hw - -/** Identifier for the second (PIO 1) hardware PIO instance (for use in PIO functions). - * - * e.g. pio_gpio_init(pio1, 5) - * - * \ingroup hardware_pio - */ -#define pio1 pio1_hw - -#if NUM_PIOS > 2 -/** Identifier for the second (PIO 1) hardware PIO instance (for use in PIO functions). - * - * e.g. pio_gpio_init(pio1, 5) - * - * \ingroup hardware_pio - */ -#define pio2 pio2_hw -#endif - -#if PICO_PIO_VERSION > 0 -#ifndef PICO_PIO_USE_GPIO_BASE -// PICO_CONFIG: PICO_PIO_USE_GPIO_BASE, Enable code for handling more than 32 PIO pins, type=bool, default=true when supported and when the device has more than 32 pins, group=hardware_pio -#define PICO_PIO_USE_GPIO_BASE ((NUM_BANK0_GPIOS) > 32) -#endif -#endif - -/** - * \def PIO_NUM(pio) - * \ingroup hardware_pio - * \hideinitializer - * \brief Returns the PIO number for a PIO instance - * - * Note this macro is intended to resolve at compile time, and does no parameter checking - */ -#ifndef PIO_NUM -static_assert(PIO1_BASE - PIO0_BASE == (1u << 20), "hardware layout mismatch"); -#define PIO_NUM(pio) (((uintptr_t)(pio) - PIO0_BASE) >> 20) -#endif - -/** - * \def PIO_INSTANCE(pio_num) - * \ingroup hardware_pio - * \hideinitializer - * \brief Returns the PIO instance with the given PIO number - * - * Note this macro is intended to resolve at compile time, and does no parameter checking - */ -#ifndef PIO_INSTANCE -static_assert(PIO1_BASE - PIO0_BASE == (1u << 20), "hardware layout mismatch"); -#define PIO_INSTANCE(instance) ((pio_hw_t *)(PIO0_BASE + (instance) * (1u << 20))) -#endif - -/** - * \def PIO_FUNCSEL_NUM(pio, gpio) - * \ingroup hardware_pio - * \hideinitializer - * \brief Returns \ref gpio_function_t needed to select the PIO function for the given PIO instance on the given GPIO - * - * Note this macro is intended to resolve at compile time, and does no parameter checking - */ -#ifndef PIO_FUNCSEL_NUM -#define PIO_FUNCSEL_NUM(pio, gpio) ((gpio_function_t) (GPIO_FUNC_PIO0 + PIO_NUM(pio))) -#endif - -/** - * \def PIO_DREQ_NUM(pio, sm, is_tx) - * \ingroup hardware_pio - * \hideinitializer - * \brief Returns the \ref dreq_num_t used for pacing DMA transfers to or from a given state machine's FIFOs on this PIO instance. - * If is_tx is true, then it is for transfers to the PIO state machine TX FIFO else for transfers from the PIO state machine RX FIFO. - * - * Note this macro is intended to resolve at compile time, and does no parameter checking - */ -#ifndef PIO_DREQ_NUM -static_assert(DREQ_PIO0_TX1 == DREQ_PIO0_TX0 + 1, ""); -static_assert(DREQ_PIO0_TX2 == DREQ_PIO0_TX0 + 2, ""); -static_assert(DREQ_PIO0_TX3 == DREQ_PIO0_TX0 + 3, ""); -static_assert(DREQ_PIO0_RX0 == DREQ_PIO0_TX0 + NUM_PIO_STATE_MACHINES, ""); -static_assert(DREQ_PIO1_RX0 == DREQ_PIO1_TX0 + NUM_PIO_STATE_MACHINES, ""); -#define PIO_DREQ_NUM(pio, sm, is_tx) ((sm) + (((is_tx) ? 0 : NUM_PIO_STATE_MACHINES) + PIO_NUM(pio) * (DREQ_PIO1_TX0 - DREQ_PIO0_TX0))) -#endif - -/** - * \def PIO_IRQ_NUM(pio) - * \ingroup hardware_pio - * \hideinitializer - * \brief Returns the \ref irq_num_t for processor interrupts from the given PIO instance - * - * Note this macro is intended to resolve at compile time, and does no parameter checking - */ -#ifndef PIO_IRQ_NUM -#define PIO_IRQ_NUM(pio, irqn) (PIO0_IRQ_0 + NUM_PIO_IRQS * PIO_NUM(pio) + (irqn)) -#endif - -/** \brief PIO state machine configuration - * \defgroup sm_config sm_config - * \ingroup hardware_pio - * - * A PIO block needs to be configured, these functions provide helpers to set up configuration - * structures. See \ref pio_sm_set_config - * - */ - -/** \brief PIO Configuration structure - * \ingroup sm_config - * - * This structure is an in-memory representation of the configuration that can be applied to a PIO - * state machine later using pio_sm_set_config() or pio_sm_init(). - */ -typedef struct { - uint32_t clkdiv; - uint32_t execctrl; - uint32_t shiftctrl; - uint32_t pinctrl; -#if PICO_PIO_USE_GPIO_BASE -#define PINHI_ALL_PINCTRL_LSBS ((1u << PIO_SM0_PINCTRL_IN_BASE_LSB) | (1u << PIO_SM0_PINCTRL_OUT_BASE_LSB) | \ - (1u << PIO_SM0_PINCTRL_SET_BASE_LSB) | (1u << PIO_SM0_PINCTRL_SIDESET_BASE_LSB)) -static_assert( 0 == (0xff000000u & (PINHI_ALL_PINCTRL_LSBS * 0x1f)), ""); -// note we put the jmp_ctrl pin starting at bit 24 -#define PINHI_ALL_PIN_LSBS ((1u << 24) | (1u << PIO_SM0_PINCTRL_IN_BASE_LSB) | (1u << PIO_SM0_PINCTRL_OUT_BASE_LSB) | \ - (1u << PIO_SM0_PINCTRL_SET_BASE_LSB) | (1u << PIO_SM0_PINCTRL_SIDESET_BASE_LSB)) - // each 5-bit field which would usually be used for the pin_base in pin_ctrl, is used for: - // 0b11111 - corresponding field not specified - // 0b00000 - pin is in range 0-15 - // 0b00001 - pin is in range 16-31 - // 0b00010 - pin is in range 32-47 - uint32_t pinhi; -#endif -} pio_sm_config; - -static inline void check_sm_param(__unused uint sm) { - valid_params_if(HARDWARE_PIO, sm < NUM_PIO_STATE_MACHINES); -} - -static inline void check_sm_mask(__unused uint mask) { - valid_params_if(HARDWARE_PIO, mask < (1u << NUM_PIO_STATE_MACHINES)); -} - -static inline void check_pio_param(__unused PIO pio) { -#if NUM_PIOS == 2 - valid_params_if(HARDWARE_PIO, pio == pio0 || pio == pio1); -#elif NUM_PIOS == 3 - valid_params_if(HARDWARE_PIO, pio == pio0 || pio == pio1 || pio == pio2); -#endif -} - -static inline void check_pio_pin_param(__unused uint pin) { -#if !PICO_PIO_USE_GPIO_BASE - invalid_params_if(HARDWARE_PIO, pin >= 32); -#else - // pin base allows us to move up 16 pins at a time - invalid_params_if(HARDWARE_PIO, pin >= ((NUM_BANK0_GPIOS + 15u)&~15u)); -#endif -} - -/*! \brief Set the base of the 'out' pins in a state machine configuration - * \ingroup sm_config - * - * 'out' pins can overlap with the 'in', 'set' and 'sideset' pins - * - * \param c Pointer to the configuration structure to modify - * \param out_base 0-31 First pin to set as output - */ -static inline void sm_config_set_out_pin_base(pio_sm_config *c, uint out_base) { - check_pio_pin_param(out_base); - c->pinctrl = (c->pinctrl & ~PIO_SM0_PINCTRL_OUT_BASE_BITS) | - ((out_base & 31) << PIO_SM0_PINCTRL_OUT_BASE_LSB); -#if PICO_PIO_USE_GPIO_BASE - c->pinhi = (c->pinhi & ~(31u << PIO_SM0_PINCTRL_OUT_BASE_LSB)) | - ((out_base >> 4) << PIO_SM0_PINCTRL_OUT_BASE_LSB); -#endif -} - -/*! \brief Set the number of 'out' pins in a state machine configuration - * \ingroup sm_config - * - * 'out' pins can overlap with the 'in', 'set' and 'sideset' pins - * - * \param c Pointer to the configuration structure to modify - * \param out_count 0-32 Number of pins to set. - */ -static inline void sm_config_set_out_pin_count(pio_sm_config *c, uint out_count) { - valid_params_if(HARDWARE_PIO, out_count <= 32); - c->pinctrl = (c->pinctrl & ~PIO_SM0_PINCTRL_OUT_COUNT_BITS) | - (out_count << PIO_SM0_PINCTRL_OUT_COUNT_LSB); -} - -/*! \brief Set the 'out' pins in a state machine configuration - * \ingroup sm_config - * - * 'out' pins can overlap with the 'in', 'set' and 'sideset' pins - * - * \param c Pointer to the configuration structure to modify - * \param out_base 0-31 First pin to set as output - * \param out_count 0-32 Number of pins to set. - */ -static inline void sm_config_set_out_pins(pio_sm_config *c, uint out_base, uint out_count) { - sm_config_set_out_pin_base(c, out_base); - sm_config_set_out_pin_count(c, out_count); -} - -/*! \brief Set the base of the 'set' pins in a state machine configuration - * \ingroup sm_config - * - * 'set' pins can overlap with the 'in', 'out' and 'sideset' pins - * - * \param c Pointer to the configuration structure to modify - * \param set_base 0-31 First pin to set as - */ -static inline void sm_config_set_set_pin_base(pio_sm_config *c, uint set_base) { - check_pio_pin_param(set_base); - c->pinctrl = (c->pinctrl & ~PIO_SM0_PINCTRL_SET_BASE_BITS) | - ((set_base & 31) << PIO_SM0_PINCTRL_SET_BASE_LSB); -#if PICO_PIO_USE_GPIO_BASE - c->pinhi = (c->pinhi & ~(31u << PIO_SM0_PINCTRL_SET_BASE_LSB)) | - ((set_base >> 4) << PIO_SM0_PINCTRL_SET_BASE_LSB); -#endif -} - -/*! \brief Set the count of 'set' pins in a state machine configuration - * \ingroup sm_config - * - * 'set' pins can overlap with the 'in', 'out' and 'sideset' pins - * - * \param c Pointer to the configuration structure to modify - * \param set_count 0-5 Number of pins to set. - */ -static inline void sm_config_set_set_pin_count(pio_sm_config *c, uint set_count) { - valid_params_if(HARDWARE_PIO, set_count <= 5); - c->pinctrl = (c->pinctrl & ~PIO_SM0_PINCTRL_SET_COUNT_BITS) | - (set_count << PIO_SM0_PINCTRL_SET_COUNT_LSB); -} - -/*! \brief Set the 'set' pins in a state machine configuration - * \ingroup sm_config - * - * 'set' pins can overlap with the 'in', 'out' and 'sideset' pins - * - * \param c Pointer to the configuration structure to modify - * \param set_base 0-31 First pin to set as - * \param set_count 0-5 Number of pins to set. - */ -static inline void sm_config_set_set_pins(pio_sm_config *c, uint set_base, uint set_count) { - sm_config_set_set_pin_base(c, set_base); - sm_config_set_set_pin_count(c, set_count); -} - -/*! \brief Set the base of the 'in' pins in a state machine configuration - * \ingroup sm_config - * - * 'in' pins can overlap with the 'out', 'set' and 'sideset' pins - * - * \param c Pointer to the configuration structure to modify - * \param in_base 0-31 First pin to use as input - */ -static inline void sm_config_set_in_pin_base(pio_sm_config *c, uint in_base) { - check_pio_pin_param(in_base); - c->pinctrl = (c->pinctrl & ~PIO_SM0_PINCTRL_IN_BASE_BITS) | - ((in_base & 31) << PIO_SM0_PINCTRL_IN_BASE_LSB); -#if PICO_PIO_USE_GPIO_BASE - c->pinhi = (c->pinhi & ~(31u << PIO_SM0_PINCTRL_IN_BASE_LSB)) | - ((in_base >> 4) << PIO_SM0_PINCTRL_IN_BASE_LSB); -#endif -} - -/*! \brief Set the base for the 'in' pins in a state machine configuration - * \ingroup sm_config - * - * 'in' pins can overlap with the 'out', 'set' and 'sideset' pins - * - * \param c Pointer to the configuration structure to modify - * \param in_base 0-31 First pin to use as input - */ -static inline void sm_config_set_in_pins(pio_sm_config *c, uint in_base) { - sm_config_set_in_pin_base(c, in_base); -} - -/*! \brief Set the count of 'in' pins in a state machine configuration - * \ingroup sm_config - * - * When reading pins using the IN pin mapping, this many (low) bits will be read, with the rest taking - * the value zero. - * - * \if rp2040_specific - * RP2040 does not have the ability to mask unused input pins, so the in_count must be 32 - * \endif - * - * \param c Pointer to the configuration structure to modify - * \param in_count 1-32 The number of pins to include when reading via the IN pin mapping - */ -static inline void sm_config_set_in_pin_count(pio_sm_config *c, uint in_count) { -#if PICO_PIO_VERSION == 0 - // can't be changed from 32 on PIO v0 - ((void)c); - valid_params_if(HARDWARE_PIO, in_count == 32); -#else - valid_params_if(HARDWARE_PIO, in_count && in_count <= 32); - c->shiftctrl = (c->shiftctrl & ~PIO_SM0_SHIFTCTRL_IN_COUNT_BITS) | - ((in_count & 0x1fu) << PIO_SM0_SHIFTCTRL_IN_COUNT_LSB); -#endif -} - -/*! \brief Set the base of the 'sideset' pins in a state machine configuration - * \ingroup sm_config - * - * 'sideset' pins can overlap with the 'in', 'out' and 'set' pins - * - * \param c Pointer to the configuration structure to modify - * \param sideset_base 0-31 base pin for 'side set' - */ -static inline void sm_config_set_sideset_pin_base(pio_sm_config *c, uint sideset_base) { - check_pio_pin_param(sideset_base); - c->pinctrl = (c->pinctrl & ~PIO_SM0_PINCTRL_SIDESET_BASE_BITS) | - ((sideset_base & 31) << PIO_SM0_PINCTRL_SIDESET_BASE_LSB); -#if PICO_PIO_USE_GPIO_BASE - c->pinhi = (c->pinhi & ~(31u << PIO_SM0_PINCTRL_SIDESET_BASE_LSB)) | - ((sideset_base >> 4) << PIO_SM0_PINCTRL_SIDESET_BASE_LSB); -#endif -} - -/*! \brief Set the 'sideset' pins in a state machine configuration - * \ingroup sm_config - * - * This method is identical to \ref sm_config_set_sideset_pin_base, and is provided - * for backwards compatibility - * - * 'sideset' pins can overlap with the 'in', 'out' and 'set' pins - * - * \param c Pointer to the configuration structure to modify - * \param sideset_base 0-31 base pin for 'side set' - */ -static inline void sm_config_set_sideset_pins(pio_sm_config *c, uint sideset_base) { - sm_config_set_sideset_pin_base(c, sideset_base); -} - -/*! \brief Set the 'sideset' options in a state machine configuration - * \ingroup sm_config - * - * \param c Pointer to the configuration structure to modify - * \param bit_count Number of bits to steal from delay field in the instruction for use of side set (max 5) - * \param optional True if the topmost side set bit is used as a flag for whether to apply side set on that instruction - * \param pindirs True if the side set affects pin directions rather than values - */ -static inline void sm_config_set_sideset(pio_sm_config *c, uint bit_count, bool optional, bool pindirs) { - valid_params_if(HARDWARE_PIO, bit_count <= 5); - valid_params_if(HARDWARE_PIO, !optional || bit_count >= 1); - c->pinctrl = (c->pinctrl & ~PIO_SM0_PINCTRL_SIDESET_COUNT_BITS) | - (bit_count << PIO_SM0_PINCTRL_SIDESET_COUNT_LSB); - c->execctrl = (c->execctrl & ~(PIO_SM0_EXECCTRL_SIDE_EN_BITS | PIO_SM0_EXECCTRL_SIDE_PINDIR_BITS)) | - (bool_to_bit(optional) << PIO_SM0_EXECCTRL_SIDE_EN_LSB) | - (bool_to_bit(pindirs) << PIO_SM0_EXECCTRL_SIDE_PINDIR_LSB); -} - -/*! \brief Set the state machine clock divider (from integer and fractional parts - 16:8) in a state machine configuration - * \ingroup sm_config - * - * The clock divider can slow the state machine's execution to some rate below - * the system clock frequency, by enabling the state machine on some cycles - * but not on others, in a regular pattern. This can be used to generate e.g. - * a given UART baud rate. See the datasheet for further detail. - * - * \param c Pointer to the configuration structure to modify - * \param div_int Integer part of the divisor - * \param div_frac Fractional part in 1/256ths - * \sa sm_config_set_clkdiv() - */ -static inline void sm_config_set_clkdiv_int_frac(pio_sm_config *c, uint16_t div_int, uint8_t div_frac) { - invalid_params_if(HARDWARE_PIO, div_int == 0 && div_frac != 0); - c->clkdiv = - (((uint)div_frac) << PIO_SM0_CLKDIV_FRAC_LSB) | - (((uint)div_int) << PIO_SM0_CLKDIV_INT_LSB); -} - -static inline void pio_calculate_clkdiv_from_float(float div, uint16_t *div_int, uint8_t *div_frac) { - valid_params_if(HARDWARE_PIO, div >= 1 && div <= 65536); - *div_int = (uint16_t)div; - if (*div_int == 0) { - *div_frac = 0; - } else { - *div_frac = (uint8_t)((div - (float)*div_int) * (1u << 8u)); - } -} - -/*! \brief Set the state machine clock divider (from a floating point value) in a state machine configuration - * \ingroup sm_config - * - * The clock divider slows the state machine's execution by masking the - * system clock on some cycles, in a repeating pattern, so that the state - * machine does not advance. Effectively this produces a slower clock for the - * state machine to run from, which can be used to generate e.g. a particular - * UART baud rate. See the datasheet for further detail. - * - * \param c Pointer to the configuration structure to modify - * \param div The fractional divisor to be set. 1 for full speed. An integer clock divisor of n - * will cause the state machine to run 1 cycle in every n. - * Note that for small n, the jitter introduced by a fractional divider (e.g. 2.5) may be unacceptable - * although it will depend on the use case. - */ -static inline void sm_config_set_clkdiv(pio_sm_config *c, float div) { - uint16_t div_int; - uint8_t div_frac; - pio_calculate_clkdiv_from_float(div, &div_int, &div_frac); - sm_config_set_clkdiv_int_frac(c, div_int, div_frac); -} - -/*! \brief Set the wrap addresses in a state machine configuration - * \ingroup sm_config - * - * \param c Pointer to the configuration structure to modify - * \param wrap_target the instruction memory address to wrap to - * \param wrap the instruction memory address after which to set the program counter to wrap_target - * if the instruction does not itself update the program_counter - */ -static inline void sm_config_set_wrap(pio_sm_config *c, uint wrap_target, uint wrap) { - valid_params_if(HARDWARE_PIO, wrap < PIO_INSTRUCTION_COUNT); - valid_params_if(HARDWARE_PIO, wrap_target < PIO_INSTRUCTION_COUNT); - c->execctrl = (c->execctrl & ~(PIO_SM0_EXECCTRL_WRAP_TOP_BITS | PIO_SM0_EXECCTRL_WRAP_BOTTOM_BITS)) | - (wrap_target << PIO_SM0_EXECCTRL_WRAP_BOTTOM_LSB) | - (wrap << PIO_SM0_EXECCTRL_WRAP_TOP_LSB); -} - -/*! \brief Set the 'jmp' pin in a state machine configuration - * \ingroup sm_config - * - * \param c Pointer to the configuration structure to modify - * \param pin The raw GPIO pin number to use as the source for a `jmp pin` instruction - */ -static inline void sm_config_set_jmp_pin(pio_sm_config *c, uint pin) { - check_pio_pin_param(pin); - c->execctrl = (c->execctrl & ~PIO_SM0_EXECCTRL_JMP_PIN_BITS) | - ((pin & 31) << PIO_SM0_EXECCTRL_JMP_PIN_LSB); -#if PICO_PIO_USE_GPIO_BASE - c->pinhi = (c->pinhi & ~(31u << 24)) | - ((pin >> 4) << 24); -#endif -} - -/*! \brief Setup 'in' shifting parameters in a state machine configuration - * \ingroup sm_config - * - * \param c Pointer to the configuration structure to modify - * \param shift_right true to shift ISR to right, false to shift ISR to left - * \param autopush whether autopush is enabled - * \param push_threshold threshold in bits to shift in before auto/conditional re-pushing of the ISR - */ -static inline void sm_config_set_in_shift(pio_sm_config *c, bool shift_right, bool autopush, uint push_threshold) { - valid_params_if(HARDWARE_PIO, push_threshold <= 32); - c->shiftctrl = (c->shiftctrl & - ~(PIO_SM0_SHIFTCTRL_IN_SHIFTDIR_BITS | - PIO_SM0_SHIFTCTRL_AUTOPUSH_BITS | - PIO_SM0_SHIFTCTRL_PUSH_THRESH_BITS)) | - (bool_to_bit(shift_right) << PIO_SM0_SHIFTCTRL_IN_SHIFTDIR_LSB) | - (bool_to_bit(autopush) << PIO_SM0_SHIFTCTRL_AUTOPUSH_LSB) | - ((push_threshold & 0x1fu) << PIO_SM0_SHIFTCTRL_PUSH_THRESH_LSB); -} - -/*! \brief Setup 'out' shifting parameters in a state machine configuration - * \ingroup sm_config - * - * \param c Pointer to the configuration structure to modify - * \param shift_right true to shift OSR to right, false to shift OSR to left - * \param autopull whether autopull is enabled - * \param pull_threshold threshold in bits to shift out before auto/conditional re-pulling of the OSR - */ -static inline void sm_config_set_out_shift(pio_sm_config *c, bool shift_right, bool autopull, uint pull_threshold) { - valid_params_if(HARDWARE_PIO, pull_threshold <= 32); - c->shiftctrl = (c->shiftctrl & - ~(PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR_BITS | - PIO_SM0_SHIFTCTRL_AUTOPULL_BITS | - PIO_SM0_SHIFTCTRL_PULL_THRESH_BITS)) | - (bool_to_bit(shift_right) << PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR_LSB) | - (bool_to_bit(autopull) << PIO_SM0_SHIFTCTRL_AUTOPULL_LSB) | - ((pull_threshold & 0x1fu) << PIO_SM0_SHIFTCTRL_PULL_THRESH_LSB); -} - -/*! \brief Setup the FIFO joining in a state machine configuration - * \ingroup sm_config - * - * \param c Pointer to the configuration structure to modify - * \param join Specifies the join type. \see enum pio_fifo_join - */ -static inline void sm_config_set_fifo_join(pio_sm_config *c, enum pio_fifo_join join) { - valid_params_if(HARDWARE_PIO, join == PIO_FIFO_JOIN_NONE || join == PIO_FIFO_JOIN_TX || join == PIO_FIFO_JOIN_RX -#if PICO_PIO_VERSION > 0 - || join == PIO_FIFO_JOIN_TXPUT || join == PIO_FIFO_JOIN_TXGET || join == PIO_FIFO_JOIN_PUTGET -#endif - ); -#if PICO_PIO_VERSION == 0 - c->shiftctrl = (c->shiftctrl & (uint)~(PIO_SM0_SHIFTCTRL_FJOIN_TX_BITS | PIO_SM0_SHIFTCTRL_FJOIN_RX_BITS)) | - (((uint)join) << PIO_SM0_SHIFTCTRL_FJOIN_TX_LSB); -#else - c->shiftctrl = (c->shiftctrl & (uint)~(PIO_SM0_SHIFTCTRL_FJOIN_TX_BITS | PIO_SM0_SHIFTCTRL_FJOIN_RX_BITS | - PIO_SM0_SHIFTCTRL_FJOIN_RX_PUT_BITS | PIO_SM0_SHIFTCTRL_FJOIN_RX_GET_BITS)) | - (((uint)(join & 3)) << PIO_SM0_SHIFTCTRL_FJOIN_TX_LSB) | - (((uint)(join >> 2)) << PIO_SM0_SHIFTCTRL_FJOIN_RX_GET_LSB); -#endif -} - -/*! \brief Set special 'out' operations in a state machine configuration - * \ingroup sm_config - * - * \param c Pointer to the configuration structure to modify - * \param sticky to enable 'sticky' output (i.e. re-asserting most recent OUT/SET pin values on subsequent cycles) - * \param has_enable_pin true to enable auxiliary OUT enable pin - * \param enable_pin_index pin index for auxiliary OUT enable - */ -static inline void sm_config_set_out_special(pio_sm_config *c, bool sticky, bool has_enable_pin, uint enable_pin_index) { - c->execctrl = (c->execctrl & - (uint)~(PIO_SM0_EXECCTRL_OUT_STICKY_BITS | PIO_SM0_EXECCTRL_INLINE_OUT_EN_BITS | - PIO_SM0_EXECCTRL_OUT_EN_SEL_BITS)) | - (bool_to_bit(sticky) << PIO_SM0_EXECCTRL_OUT_STICKY_LSB) | - (bool_to_bit(has_enable_pin) << PIO_SM0_EXECCTRL_INLINE_OUT_EN_LSB) | - ((enable_pin_index << PIO_SM0_EXECCTRL_OUT_EN_SEL_LSB) & PIO_SM0_EXECCTRL_OUT_EN_SEL_BITS); -} - -/*! \brief Set source for 'mov status' in a state machine configuration - * \ingroup sm_config - * - * \param c Pointer to the configuration structure to modify - * \param status_sel the status operation selector. \see enum pio_mov_status_type - * \param status_n parameter for the mov status operation (currently a bit count) - */ -static inline void sm_config_set_mov_status(pio_sm_config *c, enum pio_mov_status_type status_sel, uint status_n) { - valid_params_if(HARDWARE_PIO, - status_sel == STATUS_TX_LESSTHAN || status_sel == STATUS_RX_LESSTHAN -#if PICO_PIO_VERSION > 0 - || status_sel == STATUS_IRQ_SET -#endif - ); - c->execctrl = (c->execctrl - & ~(PIO_SM0_EXECCTRL_STATUS_SEL_BITS | PIO_SM0_EXECCTRL_STATUS_N_BITS)) - | ((((uint)status_sel) << PIO_SM0_EXECCTRL_STATUS_SEL_LSB) & PIO_SM0_EXECCTRL_STATUS_SEL_BITS) - | ((status_n << PIO_SM0_EXECCTRL_STATUS_N_LSB) & PIO_SM0_EXECCTRL_STATUS_N_BITS); -} - -/*! \brief Get the default state machine configuration - * \ingroup sm_config - * - * Setting | Default - * --------|-------- - * Out Pins | 32 starting at 0 - * Set Pins | 0 starting at 0 - * In Pins | 32 starting at 0 - * Side Set Pins (base) | 0 - * Side Set | disabled - * Wrap | wrap=31, wrap_to=0 - * In Shift | shift_direction=right, autopush=false, push_threshold=32 - * Out Shift | shift_direction=right, autopull=false, pull_threshold=32 - * Jmp Pin | 0 - * Out Special | sticky=false, has_enable_pin=false, enable_pin_index=0 - * Mov Status | status_sel=STATUS_TX_LESSTHAN, n=0 - * - * \return the default state machine configuration which can then be modified. - */ -static inline pio_sm_config pio_get_default_sm_config(void) { - pio_sm_config c = {0}; -#if PICO_PIO_USE_GPIO_BASE - c.pinhi = -1; -#endif - sm_config_set_clkdiv_int_frac(&c, 1, 0); - sm_config_set_wrap(&c, 0, 31); - sm_config_set_in_shift(&c, true, false, 32); - sm_config_set_out_shift(&c, true, false, 32); - return c; -} - -/*! \brief Return the base GPIO base for the PIO instance - * \ingroup hardware_pio - * - * \if rp2040_specific - * This method always return 0 in RP2040 - * \endif - * - * \param pio The PIO instance; e.g. \ref pio0 or \ref pio1 - * \return the current GPIO base for the PIO instance - */ -static inline uint pio_get_gpio_base(PIO pio) { -#if PICO_PIO_VERSION > 0 - return pio->gpiobase; -#else - ((void)pio); - return 0; -#endif -} - -/*! \brief Apply a state machine configuration to a state machine - * \ingroup hardware_pio - * - * \param pio Handle to PIO instance; e.g. \ref pio0 or \ref pio1 - * \param sm State machine index (0..3) - * \param config the configuration to apply - * \return PICO_OK (0) on success, negative error code otherwise -*/ -static inline int pio_sm_set_config(PIO pio, uint sm, const pio_sm_config *config) { - check_pio_param(pio); - check_sm_param(sm); - pio->sm[sm].clkdiv = config->clkdiv; - pio->sm[sm].execctrl = config->execctrl; - pio->sm[sm].shiftctrl = config->shiftctrl; -#if PICO_PIO_USE_GPIO_BASE - uint used = (~config->pinhi >> 4) & PINHI_ALL_PIN_LSBS; - // configs that use pins 0-15 - uint gpio_under_16 = (~config->pinhi) & (~config->pinhi >> 1) & used; - // configs that use pins 32-47 - uint gpio_over_32 = (config->pinhi >> 1) & used; - uint gpio_base = pio_get_gpio_base(pio); - invalid_params_if_and_return(PIO, gpio_under_16 && gpio_base, PICO_ERROR_BAD_ALIGNMENT); - invalid_params_if_and_return(PIO, gpio_over_32 && !gpio_base, PICO_ERROR_BAD_ALIGNMENT); - // flip the top bit of any used (pinctrl) values to turn: - // bit6(32) + 0-15 -> base(16) + 16-31 - // bit6(0) + 16-31 -> base(16) + 0-15 - pio->sm[sm].pinctrl = config->pinctrl ^ (gpio_base ? ((used << 12) >> 8) : 0); -#else - pio->sm[sm].pinctrl = config->pinctrl; -#endif - return PICO_OK; -} - -/*! \brief Return the instance number of a PIO instance - * \ingroup hardware_pio - * - * \param pio The PIO instance; e.g. \ref pio0 or \ref pio1 - * \return the PIO instance number (0, 1, ...) - */ -static inline uint pio_get_index(PIO pio) { - check_pio_param(pio); - return PIO_NUM(pio); -} - -/*! \brief Return the funcsel number of a PIO instance - * \ingroup hardware_pio - * - * \param pio The PIO instance; e.g. \ref pio0 or \ref pio1 - * \return the PIO instance number (0, 1, ...) - * \see gpio_function - */ -static inline uint pio_get_funcsel(PIO pio) { - check_pio_param(pio); - return PIO_FUNCSEL_NUM(pio, 0); // note GPIO currently unused, so won't bother updating API -} - -/*! \brief Convert PIO instance to hardware instance - * \ingroup hardware_pio - * - * \param instance Instance of PIO, 0 or 1 - * \return the PIO hardware instance - */ -static inline PIO pio_get_instance(uint instance) { - invalid_params_if(HARDWARE_PIO, instance >= NUM_PIOS); - return PIO_INSTANCE(instance); -} - -/*! \brief Setup the function select for a GPIO to use output from the given PIO instance - * \ingroup hardware_pio - * - * PIO appears as an alternate function in the GPIO muxing, just like an SPI - * or UART. This function configures that multiplexing to connect a given PIO - * instance to a GPIO. Note that this is not necessary for a state machine to - * be able to read the *input* value from a GPIO, but only for it to set the - * output value or output enable. - * - * \param pio The PIO instance; e.g. \ref pio0 or \ref pio1 - * \param pin the GPIO pin whose function select to set - */ -static inline void pio_gpio_init(PIO pio, uint pin) { - check_pio_param(pio); - valid_params_if(HARDWARE_PIO, pin < NUM_BANK0_GPIOS); - gpio_set_function(pin, PIO_FUNCSEL_NUM(pio, pin)); -} - -/*! \brief Return the DREQ to use for pacing transfers to/from a particular state machine FIFO - * \ingroup hardware_pio - * - * \param pio The PIO instance; e.g. \ref pio0 or \ref pio1 - * \param sm State machine index (0..3) - * \param is_tx true for sending data to the state machine, false for receiving data from the state machine - */ -static inline uint pio_get_dreq(PIO pio, uint sm, bool is_tx) { - check_pio_param(pio); - check_sm_param(sm); - return PIO_DREQ_NUM(pio, sm, is_tx); -} - -typedef struct pio_program { - const uint16_t *instructions; - uint8_t length; - int8_t origin; // required instruction memory origin or -1 - uint8_t pio_version; -#if PICO_PIO_VERSION > 0 - uint8_t used_gpio_ranges; // bitmap with one bit per 16 pins -#endif -} pio_program_t; - -/*! \brief Set the base GPIO base for the PIO instance - * \ingroup hardware_pio - * - * Since an individual PIO accesses only 32 pins, to be able to access more pins, the PIO - * instance must specify a base GPIO where the instance's "pin 0" maps. For RP2350 the valid - * values are 0 and 16, indicating the PIO instance has access to pins 0-31, or 16-47 respectively. - * - * \param pio The PIO instance; e.g. \ref pio0 or \ref pio1 - * \param gpio_base the GPIO base (either 0 or 16) - * \return PICO_OK (0) on success, error code otherwise - */ -int pio_set_gpio_base(PIO pio, uint gpio_base); - -/*! \brief Determine whether the given program can (at the time of the call) be loaded onto the PIO instance - * \ingroup hardware_pio - * - * \param pio The PIO instance; e.g. \ref pio0 or \ref pio1 - * \param program the program definition - * \return true if the program can be loaded; false if there is not suitable space in the instruction memory - */ -bool pio_can_add_program(PIO pio, const pio_program_t *program); - -/*! \brief Determine whether the given program can (at the time of the call) be loaded onto the PIO instance starting at a particular location - * \ingroup hardware_pio - * - * \param pio The PIO instance; e.g. \ref pio0 or \ref pio1 - * \param program the program definition - * \param offset the instruction memory offset wanted for the start of the program - * \return true if the program can be loaded at that location; false if there is not space in the instruction memory - */ -bool pio_can_add_program_at_offset(PIO pio, const pio_program_t *program, uint offset); - -/*! \brief Attempt to load the program - * \ingroup hardware_pio - * - * \see pio_can_add_program() if you need to check whether the program can be loaded - * - * \param pio The PIO instance; e.g. \ref pio0 or \ref pio1 - * \param program the program definition - * \return the instruction memory offset the program is loaded at, or negative for error (for - * backwards compatibility with prior SDK the error value is -1 i.e. PICO_ERROR_GENERIC) - */ -int pio_add_program(PIO pio, const pio_program_t *program); - -/*! \brief Attempt to load the program at the specified instruction memory offset - * \ingroup hardware_pio - * - * \see pio_can_add_program_at_offset() if you need to check whether the program can be loaded - * - * \param pio The PIO instance; e.g. \ref pio0 or \ref pio1 - * \param program the program definition - * \param offset the instruction memory offset wanted for the start of the program - * \return the instruction memory offset the program is loaded at, or negative for error (for - * backwards compatibility with prior SDK the error value is -1 i.e. PICO_ERROR_GENERIC) - */ -int pio_add_program_at_offset(PIO pio, const pio_program_t *program, uint offset); - -/*! \brief Remove a program from a PIO instance's instruction memory - * \ingroup hardware_pio - * - * \param pio The PIO instance; e.g. \ref pio0 or \ref pio1 - * \param program the program definition - * \param loaded_offset the loaded offset returned when the program was added - */ -void pio_remove_program(PIO pio, const pio_program_t *program, uint loaded_offset); - -/*! \brief Clears all of a PIO instance's instruction memory - * \ingroup hardware_pio - * - * \param pio The PIO instance; e.g. \ref pio0 or \ref pio1 - */ -void pio_clear_instruction_memory(PIO pio); - -/*! \brief Resets the state machine to a consistent state, and configures it - * \ingroup hardware_pio - * - * This method: - * - Disables the state machine (if running) - * - Clears the FIFOs - * - Applies the configuration specified by 'config' - * - Resets any internal state e.g. shift counters - * - Jumps to the initial program location given by 'initial_pc' - * - * The state machine is left disabled on return from this call. - * - * \param pio The PIO instance; e.g. \ref pio0 or \ref pio1 - * \param sm State machine index (0..3) - * \param initial_pc the initial program memory offset to run from - * \param config the configuration to apply (or NULL to apply defaults) - * \return PICO_OK, or < 0 for an error (see \enum pico_error_codes) - */ -int pio_sm_init(PIO pio, uint sm, uint initial_pc, const pio_sm_config *config); - -/*! \brief Enable or disable a PIO state machine - * \ingroup hardware_pio - * - * \param pio The PIO instance; e.g. \ref pio0 or \ref pio1 - * \param sm State machine index (0..3) - * \param enabled true to enable the state machine; false to disable - */ -static inline void pio_sm_set_enabled(PIO pio, uint sm, bool enabled) { - check_pio_param(pio); - check_sm_param(sm); - pio->ctrl = (pio->ctrl & ~(1u << sm)) | (bool_to_bit(enabled) << sm); -} - -/*! \brief Enable or disable multiple PIO state machines - * \ingroup hardware_pio - * - * Note that this method just sets the enabled state of the state machine; - * if now enabled they continue exactly from where they left off. - * - * \see pio_enable_sm_mask_in_sync() if you wish to enable multiple state machines - * and ensure their clock dividers are in sync. - * - * \param pio The PIO instance; e.g. \ref pio0 or \ref pio1 - * \param mask bit mask of state machine indexes to modify the enabled state of - * \param enabled true to enable the state machines; false to disable - */ -static inline void pio_set_sm_mask_enabled(PIO pio, uint32_t mask, bool enabled) { - check_pio_param(pio); - check_sm_mask(mask); - pio->ctrl = (pio->ctrl & ~mask) | (enabled ? mask : 0u); -} - -#if PICO_PIO_VERSION > 0 -/*! \brief Enable or disable multiple PIO state machines - * \ingroup hardware_pio - * - * Note that this method just sets the enabled state of the state machine; - * if now enabled they continue exactly from where they left off. - * - * \see pio_enable_sm_mask_in_sync() if you wish to enable multiple state machines - * and ensure their clock dividers are in sync. - * - * \param pio The PIO instance; e.g. \ref pio0 or \ref pio1 - * \param mask_prev bit mask of state machine indexes to modify the enabled state of, in the next-lower numbered PIO instance - * \param mask bit mask of state machine indexes to modify the enabled state of, in this PIO instance - * \param mask bit mask of state machine indexes to modify the enabled state of, in the next-higher numbered PIO instance - * \param enabled true to enable the state machines; false to disable - */ -static inline void pio_set_sm_multi_mask_enabled(PIO pio, uint32_t mask_prev, uint32_t mask, uint32_t mask_next, bool enabled) { - check_pio_param(pio); - check_sm_mask(mask); - pio->ctrl = (pio->ctrl & ~(mask << PIO_CTRL_SM_ENABLE_LSB)) | - (enabled ? ((mask << PIO_CTRL_SM_ENABLE_LSB) & PIO_CTRL_SM_ENABLE_BITS) : 0) | - (enabled ? PIO_CTRL_NEXTPREV_SM_ENABLE_BITS : PIO_CTRL_NEXTPREV_SM_DISABLE_BITS) | - ((mask_prev << PIO_CTRL_PREV_PIO_MASK_LSB) & PIO_CTRL_PREV_PIO_MASK_BITS) | - ((mask_next << PIO_CTRL_NEXT_PIO_MASK_LSB) & PIO_CTRL_NEXT_PIO_MASK_BITS); - -} -#endif - -/*! \brief Restart a state machine with a known state - * \ingroup hardware_pio - * - * This method clears the ISR, shift counters, clock divider counter - * pin write flags, delay counter, latched EXEC instruction, and IRQ wait condition. - * - * \param pio The PIO instance; e.g. \ref pio0 or \ref pio1 - * \param sm State machine index (0..3) - */ -static inline void pio_sm_restart(PIO pio, uint sm) { - check_pio_param(pio); - check_sm_param(sm); - hw_set_bits(&pio->ctrl, 1u << (PIO_CTRL_SM_RESTART_LSB + sm)); -} - -/*! \brief Restart multiple state machine with a known state - * \ingroup hardware_pio - * - * This method clears the ISR, shift counters, clock divider counter - * pin write flags, delay counter, latched EXEC instruction, and IRQ wait condition. - * - * \param pio The PIO instance; e.g. \ref pio0 or \ref pio1 - * \param mask bit mask of state machine indexes to modify the enabled state of - */ -static inline void pio_restart_sm_mask(PIO pio, uint32_t mask) { - check_pio_param(pio); - check_sm_mask(mask); - hw_set_bits(&pio->ctrl, (mask << PIO_CTRL_SM_RESTART_LSB) & PIO_CTRL_SM_RESTART_BITS); -} - -/*! \brief Restart a state machine's clock divider from a phase of 0 - * \ingroup hardware_pio - * - * Each state machine's clock divider is a free-running piece of hardware, - * that generates a pattern of clock enable pulses for the state machine, - * based *only* on the configured integer/fractional divisor. The pattern of - * running/halted cycles slows the state machine's execution to some - * controlled rate. - * - * This function clears the divider's integer and fractional phase - * accumulators so that it restarts this pattern from the beginning. It is - * called automatically by pio_sm_init() but can also be called at a later - * time, when you enable the state machine, to ensure precisely consistent - * timing each time you load and run a given PIO program. - * - * More commonly this hardware mechanism is used to synchronise the execution - * clocks of multiple state machines -- see pio_clkdiv_restart_sm_mask(). - * - * \param pio The PIO instance; e.g. \ref pio0 or \ref pio1 - * \param sm State machine index (0..3) - */ -static inline void pio_sm_clkdiv_restart(PIO pio, uint sm) { - check_pio_param(pio); - check_sm_param(sm); - hw_set_bits(&pio->ctrl, 1u << (PIO_CTRL_CLKDIV_RESTART_LSB + sm)); -} - -/*! \brief Restart multiple state machines' clock dividers from a phase of 0. - * \ingroup hardware_pio - * - * Each state machine's clock divider is a free-running piece of hardware, - * that generates a pattern of clock enable pulses for the state machine, - * based *only* on the configured integer/fractional divisor. The pattern of - * running/halted cycles slows the state machine's execution to some - * controlled rate. - * - * This function simultaneously clears the integer and fractional phase - * accumulators of multiple state machines' clock dividers. If these state - * machines all have the same integer and fractional divisors configured, - * their clock dividers will run in precise deterministic lockstep from this - * point. - * - * With their execution clocks synchronised in this way, it is then safe to - * e.g. have multiple state machines performing a 'wait irq' on the same flag, - * and all clear it on the same cycle. - * - * Also note that this function can be called whilst state machines are - * running (e.g. if you have just changed the clock divisors of some state - * machines and wish to resynchronise them), and that disabling a state - * machine does not halt its clock divider: that is, if multiple state - * machines have their clocks synchronised, you can safely disable and - * re-enable one of the state machines without losing synchronisation. - * - * \param pio The PIO instance; e.g. \ref pio0 or \ref pio1 - * \param mask bit mask of state machine indexes to modify the enabled state of - */ -static inline void pio_clkdiv_restart_sm_mask(PIO pio, uint32_t mask) { - check_pio_param(pio); - check_sm_mask(mask); - hw_set_bits(&pio->ctrl, (mask << PIO_CTRL_CLKDIV_RESTART_LSB) & PIO_CTRL_CLKDIV_RESTART_BITS); -} - -#if PICO_PIO_VERSION > 0 -/*! \brief Restart multiple state machines' clock dividers on multiple PIOs from a phase of 0. - * \ingroup hardware_pio - * - * Each state machine's clock divider is a free-running piece of hardware, - * that generates a pattern of clock enable pulses for the state machine, - * based *only* on the configured integer/fractional divisor. The pattern of - * running/halted cycles slows the state machine's execution to some - * controlled rate. - * - * This function simultaneously clears the integer and fractional phase - * accumulators of multiple state machines' clock dividers. If these state - * machines all have the same integer and fractional divisors configured, - * their clock dividers will run in precise deterministic lockstep from this - * point. - * - * With their execution clocks synchronised in this way, it is then safe to - * e.g. have multiple state machines performing a 'wait irq' on the same flag, - * and all clear it on the same cycle. - * - * Also note that this function can be called whilst state machines are - * running (e.g. if you have just changed the clock divisors of some state - * machines and wish to resynchronise them), and that disabling a state - * machine does not halt its clock divider: that is, if multiple state - * machines have their clocks synchronised, you can safely disable and - * re-enable one of the state machines without losing synchronisation. - * - * \param pio The PIO instance; e.g. \ref pio0 or \ref pio1 - * \param mask_prev bit mask of state machine indexes to modify the enabled state of, in the next-lower numbered PIO instance - * \param mask bit mask of state machine indexes to modify the enabled state of, in this PIO instance - * \param mask_next bit mask of state machine indexes to modify the enabled state of, in the next-higher numbered PIO instance - */ -static inline void pio_clkdiv_restart_sm_multi_mask(PIO pio, uint32_t mask_prev, uint32_t mask, uint32_t mask_next) { - check_pio_param(pio); - check_sm_mask(mask); - hw_set_bits(&pio->ctrl, ((mask << PIO_CTRL_CLKDIV_RESTART_LSB) & PIO_CTRL_CLKDIV_RESTART_BITS) | - PIO_CTRL_NEXTPREV_CLKDIV_RESTART_BITS | - ((mask_prev << PIO_CTRL_PREV_PIO_MASK_LSB) & PIO_CTRL_PREV_PIO_MASK_BITS) | - ((mask_next << PIO_CTRL_NEXT_PIO_MASK_LSB) & PIO_CTRL_NEXT_PIO_MASK_BITS)); -} -#endif - -/*! \brief Enable multiple PIO state machines synchronizing their clock dividers - * \ingroup hardware_pio - * - * This is equivalent to calling both pio_set_sm_mask_enabled() and - * pio_clkdiv_restart_sm_mask() on the *same* clock cycle. All state machines - * specified by 'mask' are started simultaneously and, assuming they have the - * same clock divisors, their divided clocks will stay precisely synchronised. - * - * \param pio The PIO instance; e.g. \ref pio0 or \ref pio1 - * \param mask bit mask of state machine indexes to modify the enabled state of - */ -static inline void pio_enable_sm_mask_in_sync(PIO pio, uint32_t mask) { - check_pio_param(pio); - check_sm_mask(mask); - hw_set_bits(&pio->ctrl, - ((mask << PIO_CTRL_CLKDIV_RESTART_LSB) & PIO_CTRL_CLKDIV_RESTART_BITS) | - ((mask << PIO_CTRL_SM_ENABLE_LSB) & PIO_CTRL_SM_ENABLE_BITS)); -} - -#if PICO_PIO_VERSION > 0 -/*! \brief Enable multiple PIO state machines on multiple PIOs synchronizing their clock dividers - * \ingroup hardware_pio - * - * This is equivalent to calling both pio_set_sm_multi_mask_enabled() and - * pio_clkdiv_restart_sm_multi_mask() on the *same* clock cycle. All state machines - * specified by 'mask' are started simultaneously and, assuming they have the - * same clock divisors, their divided clocks will stay precisely synchronised. - * - * \param pio The PIO instance; e.g. \ref pio0 or \ref pio1 - * \param mask_prev bit mask of state machine indexes to modify the enabled state of, in the next-lower numbered PIO instance - * \param mask bit mask of state machine indexes to modify the enabled state of, in this PIO instance - * \param mask_next bit mask of state machine indexes to modify the enabled state of, in the next-higher numbered PIO instance - */ -static inline void pio_enable_sm_multi_mask_in_sync(PIO pio, uint32_t mask_prev, uint32_t mask, uint32_t mask_next) { - check_pio_param(pio); - check_sm_mask(mask); - check_pio_param(pio); - check_sm_mask(mask); - hw_set_bits(&pio->ctrl, ((mask << PIO_CTRL_CLKDIV_RESTART_LSB) & PIO_CTRL_CLKDIV_RESTART_BITS) | - ((mask << PIO_CTRL_SM_ENABLE_LSB) & PIO_CTRL_SM_ENABLE_BITS) | - PIO_CTRL_NEXTPREV_CLKDIV_RESTART_BITS | PIO_CTRL_NEXTPREV_SM_ENABLE_BITS | - ((mask_prev << PIO_CTRL_PREV_PIO_MASK_LSB) & PIO_CTRL_PREV_PIO_MASK_BITS) | - ((mask_next << PIO_CTRL_NEXT_PIO_MASK_LSB) & PIO_CTRL_NEXT_PIO_MASK_BITS)); -} -#endif - -/*! \brief PIO interrupt source numbers for pio related IRQs - * \ingroup hardware_pio - */ -typedef enum pio_interrupt_source { - pis_interrupt0 = PIO_INTR_SM0_LSB, ///< PIO interrupt 0 is raised - pis_interrupt1 = PIO_INTR_SM1_LSB, ///< PIO interrupt 1 is raised - pis_interrupt2 = PIO_INTR_SM2_LSB, ///< PIO interrupt 2 is raised - pis_interrupt3 = PIO_INTR_SM3_LSB, ///< PIO interrupt 3 is raised -#if PICO_PIO_VERSION > 0 - pis_interrupt4 = PIO_INTR_SM4_LSB, ///< PIO interrupt 4 is raised - pis_interrupt5 = PIO_INTR_SM5_LSB, ///< PIO interrupt 5 is raised - pis_interrupt6 = PIO_INTR_SM6_LSB, ///< PIO interrupt 6 is raised - pis_interrupt7 = PIO_INTR_SM7_LSB, ///< PIO interrupt 7 is raised -#endif - pis_sm0_tx_fifo_not_full = PIO_INTR_SM0_TXNFULL_LSB, ///< State machine 0 TX FIFO is not full - pis_sm1_tx_fifo_not_full = PIO_INTR_SM1_TXNFULL_LSB, ///< State machine 1 TX FIFO is not full - pis_sm2_tx_fifo_not_full = PIO_INTR_SM2_TXNFULL_LSB, ///< State machine 2 TX FIFO is not full - pis_sm3_tx_fifo_not_full = PIO_INTR_SM3_TXNFULL_LSB, ///< State machine 3 TX FIFO is not full - pis_sm0_rx_fifo_not_empty = PIO_INTR_SM0_RXNEMPTY_LSB, ///< State machine 0 RX FIFO is not empty - pis_sm1_rx_fifo_not_empty = PIO_INTR_SM1_RXNEMPTY_LSB, ///< State machine 1 RX FIFO is not empty - pis_sm2_rx_fifo_not_empty = PIO_INTR_SM2_RXNEMPTY_LSB, ///< State machine 2 RX FIFO is not empty - pis_sm3_rx_fifo_not_empty = PIO_INTR_SM3_RXNEMPTY_LSB, ///< State machine 3 RX FIFO is not empty -} pio_interrupt_source_t; - -/*! \brief Enable/Disable a single source on a PIO's IRQ 0 - * \ingroup hardware_pio - * - * \param pio The PIO instance; e.g. \ref pio0 or \ref pio1 - * \param source the source number (see \ref pio_interrupt_source) - * \param enabled true to enable IRQ 0 for the source, false to disable. - */ -static inline void pio_set_irq0_source_enabled(PIO pio, pio_interrupt_source_t source, bool enabled) { - check_pio_param(pio); - invalid_params_if(HARDWARE_PIO, source >= 32u || (1u << source) > PIO_INTR_BITS); - if (enabled) - hw_set_bits(&pio->inte0, 1u << source); - else - hw_clear_bits(&pio->inte0, 1u << source); -} - -/*! \brief Enable/Disable a single source on a PIO's IRQ 1 - * \ingroup hardware_pio - * - * \param pio The PIO instance; e.g. \ref pio0 or \ref pio1 - * \param source the source number (see \ref pio_interrupt_source) - * \param enabled true to enable IRQ 0 for the source, false to disable. - */ -static inline void pio_set_irq1_source_enabled(PIO pio, pio_interrupt_source_t source, bool enabled) { - check_pio_param(pio); - invalid_params_if(HARDWARE_PIO, source >= 32 || (1u << source) > PIO_INTR_BITS); - if (enabled) - hw_set_bits(&pio->inte1, 1u << source); - else - hw_clear_bits(&pio->inte1, 1u << source); -} - -/*! \brief Enable/Disable multiple sources on a PIO's IRQ 0 - * \ingroup hardware_pio - * - * \param pio The PIO instance; e.g. \ref pio0 or \ref pio1 - * \param source_mask Mask of bits, one for each source number (see \ref pio_interrupt_source) to affect - * \param enabled true to enable all the sources specified in the mask on IRQ 0, false to disable all the sources specified in the mask on IRQ 0 - */ -static inline void pio_set_irq0_source_mask_enabled(PIO pio, uint32_t source_mask, bool enabled) { - check_pio_param(pio); - invalid_params_if(HARDWARE_PIO, source_mask > PIO_INTR_BITS); - if (enabled) { - hw_set_bits(&pio->inte0, source_mask); - } else { - hw_clear_bits(&pio->inte0, source_mask); - } -} - -/*! \brief Enable/Disable multiple sources on a PIO's IRQ 1 - * \ingroup hardware_pio - * - * \param pio The PIO instance; e.g. \ref pio0 or \ref pio1 - * \param source_mask Mask of bits, one for each source number (see \ref pio_interrupt_source) to affect - * \param enabled true to enable all the sources specified in the mask on IRQ 1, false to disable all the source specified in the mask on IRQ 1 - */ -static inline void pio_set_irq1_source_mask_enabled(PIO pio, uint32_t source_mask, bool enabled) { - check_pio_param(pio); - invalid_params_if(HARDWARE_PIO, source_mask > PIO_INTR_BITS); - if (enabled) { - hw_set_bits(&pio->inte1, source_mask); - } else { - hw_clear_bits(&pio->inte1, source_mask); - } -} - -/*! \brief Enable/Disable a single source on a PIO's specified (0/1) IRQ index - * \ingroup hardware_pio - * - * \param pio The PIO instance; e.g. \ref pio0 or \ref pio1 - * \param irq_index the IRQ index; either 0 or 1 - * \param source the source number (see \ref pio_interrupt_source) - * \param enabled true to enable the source on the specified IRQ, false to disable. - */ -static inline void pio_set_irqn_source_enabled(PIO pio, uint irq_index, pio_interrupt_source_t source, bool enabled) { - invalid_params_if(HARDWARE_PIO, irq_index > NUM_PIO_IRQS); - invalid_params_if(HARDWARE_PIO, source >= 32 || (1u << source) > PIO_INTR_BITS); - if (enabled) - hw_set_bits(&pio->irq_ctrl[irq_index].inte, 1u << source); - else - hw_clear_bits(&pio->irq_ctrl[irq_index].inte, 1u << source); -} - -/*! \brief Enable/Disable multiple sources on a PIO's specified (0/1) IRQ index - * \ingroup hardware_pio - * - * \param pio The PIO instance; e.g. \ref pio0 or \ref pio1 - * \param irq_index the IRQ index; either 0 or 1 - * \param source_mask Mask of bits, one for each source number (see \ref pio_interrupt_source) to affect - * \param enabled true to enable all the sources specified in the mask on the specified IRQ, false to disable all the sources specified in the mask on the specified IRQ - */ -static inline void pio_set_irqn_source_mask_enabled(PIO pio, uint irq_index, uint32_t source_mask, bool enabled) { - invalid_params_if(HARDWARE_PIO, irq_index > NUM_PIO_IRQS); - static_assert(NUM_PIO_IRQS == 2, ""); - invalid_params_if(HARDWARE_PIO, source_mask > PIO_INTR_BITS); - if (enabled) { - hw_set_bits(&pio->irq_ctrl[irq_index].inte, source_mask); - } else { - hw_clear_bits(&pio->irq_ctrl[irq_index].inte, source_mask); - } -} - -/*! \brief Determine if a particular PIO interrupt is set - * \ingroup hardware_pio - * - * \param pio The PIO instance; e.g. \ref pio0 or \ref pio1 - * \param pio_interrupt_num the PIO interrupt number 0-7 - * \return true if corresponding PIO interrupt is currently set - */ -static inline bool pio_interrupt_get(PIO pio, uint pio_interrupt_num) { - check_pio_param(pio); - invalid_params_if(HARDWARE_PIO, pio_interrupt_num >= 8); - return pio->irq & (1u << pio_interrupt_num); -} - -/*! \brief Clear a particular PIO interrupt - * \ingroup hardware_pio - * - * \param pio The PIO instance; e.g. \ref pio0 or \ref pio1 - * \param pio_interrupt_num the PIO interrupt number 0-7 - */ -static inline void pio_interrupt_clear(PIO pio, uint pio_interrupt_num) { - check_pio_param(pio); - invalid_params_if(HARDWARE_PIO, pio_interrupt_num >= 8); - pio->irq = (1u << pio_interrupt_num); -} - -/*! \brief Return the current program counter for a state machine - * \ingroup hardware_pio - * - * \param pio The PIO instance; e.g. \ref pio0 or \ref pio1 - * \param sm State machine index (0..3) - * \return the program counter - */ -static inline uint8_t pio_sm_get_pc(PIO pio, uint sm) { - check_pio_param(pio); - check_sm_param(sm); - return (uint8_t) pio->sm[sm].addr; -} - -/*! \brief Immediately execute an instruction on a state machine - * \ingroup hardware_pio - * - * This instruction is executed instead of the next instruction in the normal control flow on the state machine. - * Subsequent calls to this method replace the previous executed - * instruction if it is still running. \see pio_sm_is_exec_stalled() to see if an executed instruction - * is still running (i.e. it is stalled on some condition) - * - * \param pio The PIO instance; e.g. \ref pio0 or \ref pio1 - * \param sm State machine index (0..3) - * \param instr the encoded PIO instruction - */ -inline static void pio_sm_exec(PIO pio, uint sm, uint instr) { - check_pio_param(pio); - check_sm_param(sm); - pio->sm[sm].instr = instr; -} - -/*! \brief Determine if an instruction set by pio_sm_exec() is stalled executing - * \ingroup hardware_pio - * - * \param pio The PIO instance; e.g. \ref pio0 or \ref pio1 - * \param sm State machine index (0..3) - * \return true if the executed instruction is still running (stalled) - */ -static inline bool pio_sm_is_exec_stalled(PIO pio, uint sm) { - check_pio_param(pio); - check_sm_param(sm); - return pio->sm[sm].execctrl & PIO_SM0_EXECCTRL_EXEC_STALLED_BITS; -} - -/*! \brief Immediately execute an instruction on a state machine and wait for it to complete - * \ingroup hardware_pio - * - * This instruction is executed instead of the next instruction in the normal control flow on the state machine. - * Subsequent calls to this method replace the previous executed - * instruction if it is still running. \see pio_sm_is_exec_stalled() to see if an executed instruction - * is still running (i.e. it is stalled on some condition) - * - * \param pio The PIO instance; e.g. \ref pio0 or \ref pio1 - * \param sm State machine index (0..3) - * \param instr the encoded PIO instruction - */ -static inline void pio_sm_exec_wait_blocking(PIO pio, uint sm, uint instr) { - check_pio_param(pio); - check_sm_param(sm); - pio_sm_exec(pio, sm, instr); - while (pio_sm_is_exec_stalled(pio, sm)) tight_loop_contents(); -} - -/*! \brief Set the current wrap configuration for a state machine - * \ingroup hardware_pio - * - * \param pio The PIO instance; e.g. \ref pio0 or \ref pio1 - * \param sm State machine index (0..3) - * \param wrap_target the instruction memory address to wrap to - * \param wrap the instruction memory address after which to set the program counter to wrap_target - * if the instruction does not itself update the program_counter - */ -static inline void pio_sm_set_wrap(PIO pio, uint sm, uint wrap_target, uint wrap) { - check_pio_param(pio); - check_sm_param(sm); - valid_params_if(HARDWARE_PIO, wrap < PIO_INSTRUCTION_COUNT); - valid_params_if(HARDWARE_PIO, wrap_target < PIO_INSTRUCTION_COUNT); - pio->sm[sm].execctrl = - (pio->sm[sm].execctrl & ~(PIO_SM0_EXECCTRL_WRAP_TOP_BITS | PIO_SM0_EXECCTRL_WRAP_BOTTOM_BITS)) | - (wrap_target << PIO_SM0_EXECCTRL_WRAP_BOTTOM_LSB) | - (wrap << PIO_SM0_EXECCTRL_WRAP_TOP_LSB); -} - -/*! \brief Set the current 'out' pins for a state machine - * \ingroup hardware_pio - * - * 'out' pins can overlap with the 'in', 'set' and 'sideset' pins - * - * \param pio The PIO instance; e.g. \ref pio0 or \ref pio1 - * \param sm State machine index (0..3) - * \param out_base 0-31 First pin to set as output - * \param out_count 0-32 Number of pins to set. - */ -static inline void pio_sm_set_out_pins(PIO pio, uint sm, uint out_base, uint out_count) { - check_pio_param(pio); - check_sm_param(sm); -#if PICO_PIO_USE_GPIO_BASE - out_base -= pio_get_gpio_base(pio); -#endif - valid_params_if(HARDWARE_PIO, out_base < 32); - valid_params_if(HARDWARE_PIO, out_count <= 32); - pio->sm[sm].pinctrl = (pio->sm[sm].pinctrl & ~(PIO_SM0_PINCTRL_OUT_BASE_BITS | PIO_SM0_PINCTRL_OUT_COUNT_BITS)) | - (out_base << PIO_SM0_PINCTRL_OUT_BASE_LSB) | - (out_count << PIO_SM0_PINCTRL_OUT_COUNT_LSB); -} - - -/*! \brief Set the current 'set' pins for a state machine - * \ingroup hardware_pio - * - * 'set' pins can overlap with the 'in', 'out' and 'sideset' pins - * - * \param pio The PIO instance; e.g. \ref pio0 or \ref pio1 - * \param sm State machine index (0..3) - * \param set_base 0-31 First pin to set as - * \param set_count 0-5 Number of pins to set. - */ -static inline void pio_sm_set_set_pins(PIO pio, uint sm, uint set_base, uint set_count) { - check_pio_param(pio); - check_sm_param(sm); -#if PICO_PIO_USE_GPIO_BASE - set_base -= pio_get_gpio_base(pio); -#endif - valid_params_if(HARDWARE_PIO, set_base < 32); - valid_params_if(HARDWARE_PIO, set_count <= 5); - pio->sm[sm].pinctrl = (pio->sm[sm].pinctrl & ~(PIO_SM0_PINCTRL_SET_BASE_BITS | PIO_SM0_PINCTRL_SET_COUNT_BITS)) | - (set_base << PIO_SM0_PINCTRL_SET_BASE_LSB) | - (set_count << PIO_SM0_PINCTRL_SET_COUNT_LSB); -} - -/*! \brief Set the current 'in' pins for a state machine - * \ingroup hardware_pio - * - * 'in' pins can overlap with the 'out', 'set' and 'sideset' pins - * - * \param pio The PIO instance; e.g. \ref pio0 or \ref pio1 - * \param sm State machine index (0..3) - * \param in_base 0-31 First pin to use as input - */ -static inline void pio_sm_set_in_pins(PIO pio, uint sm, uint in_base) { - check_pio_param(pio); - check_sm_param(sm); -#if PICO_PIO_USE_GPIO_BASE - in_base -= pio_get_gpio_base(pio); -#endif - valid_params_if(HARDWARE_PIO, in_base < 32); - pio->sm[sm].pinctrl = (pio->sm[sm].pinctrl & ~PIO_SM0_PINCTRL_IN_BASE_BITS) | - (in_base << PIO_SM0_PINCTRL_IN_BASE_LSB); -} - -/*! \brief Set the current 'sideset' pins for a state machine - * \ingroup hardware_pio - * - * 'sideset' pins can overlap with the 'in', 'out' and 'set' pins - * - * \param pio The PIO instance; e.g. \ref pio0 or \ref pio1 - * \param sm State machine index (0..3) - * \param sideset_base 0-31 base pin for 'side set' - */ -static inline void pio_sm_set_sideset_pins(PIO pio, uint sm, uint sideset_base) { - check_pio_param(pio); - check_sm_param(sm); -#if PICO_PIO_USE_GPIO_BASE - sideset_base -= pio_get_gpio_base(pio); -#endif - valid_params_if(HARDWARE_PIO, sideset_base < 32); - pio->sm[sm].pinctrl = (pio->sm[sm].pinctrl & ~PIO_SM0_PINCTRL_SIDESET_BASE_BITS) | - (sideset_base << PIO_SM0_PINCTRL_SIDESET_BASE_LSB); -} - -/*! \brief Set the 'jmp' pin for a state machine - * \ingroup hardware_pio - * - * \param pio The PIO instance; e.g. \ref pio0 or \ref pio1 - * \param sm State machine index (0..3) - * \param pin The raw GPIO pin number to use as the source for a `jmp pin` instruction - */ - -static inline void pio_sm_set_jmp_pin(PIO pio, uint sm, uint pin) { - check_pio_param(pio); - check_sm_param(sm); -#if PICO_PIO_USE_GPIO_BASE - pin -= pio_get_gpio_base(pio); -#endif - valid_params_if(HARDWARE_PIO, pin < 32); - pio->sm[sm].execctrl = - (pio->sm[sm].execctrl & ~PIO_SM0_EXECCTRL_JMP_PIN_BITS) - | (pin << PIO_SM0_EXECCTRL_JMP_PIN_LSB); -} - -/*! \brief Write a word of data to a state machine's TX FIFO - * \ingroup hardware_pio - * - * This is a raw FIFO access that does not check for fullness. If the FIFO is - * full, the FIFO contents and state are not affected by the write attempt. - * Hardware sets the TXOVER sticky flag for this FIFO in FDEBUG, to indicate - * that the system attempted to write to a full FIFO. - * - * \param pio The PIO instance; e.g. \ref pio0 or \ref pio1 - * \param sm State machine index (0..3) - * \param data the 32 bit data value - * - * \sa pio_sm_put_blocking() - */ -static inline void pio_sm_put(PIO pio, uint sm, uint32_t data) { - check_pio_param(pio); - check_sm_param(sm); - pio->txf[sm] = data; -} - -/*! \brief Read a word of data from a state machine's RX FIFO - * \ingroup hardware_pio - * - * This is a raw FIFO access that does not check for emptiness. If the FIFO is - * empty, the hardware ignores the attempt to read from the FIFO (the FIFO - * remains in an empty state following the read) and the sticky RXUNDER flag - * for this FIFO is set in FDEBUG to indicate that the system tried to read - * from this FIFO when empty. The data returned by this function is undefined - * when the FIFO is empty. - * - * \param pio The PIO instance; e.g. \ref pio0 or \ref pio1 - * \param sm State machine index (0..3) - * - * \sa pio_sm_get_blocking() - */ -static inline uint32_t pio_sm_get(PIO pio, uint sm) { - check_pio_param(pio); - check_sm_param(sm); - return pio->rxf[sm]; -} - -/*! \brief Determine if a state machine's RX FIFO is full - * \ingroup hardware_pio - * - * \param pio The PIO instance; e.g. \ref pio0 or \ref pio1 - * \param sm State machine index (0..3) - * \return true if the RX FIFO is full - */ -static inline bool pio_sm_is_rx_fifo_full(PIO pio, uint sm) { - check_pio_param(pio); - check_sm_param(sm); - return (pio->fstat & (1u << (PIO_FSTAT_RXFULL_LSB + sm))) != 0; -} - -/*! \brief Determine if a state machine's RX FIFO is empty - * \ingroup hardware_pio - * - * \param pio The PIO instance; e.g. \ref pio0 or \ref pio1 - * \param sm State machine index (0..3) - * \return true if the RX FIFO is empty - */ -static inline bool pio_sm_is_rx_fifo_empty(PIO pio, uint sm) { - check_pio_param(pio); - check_sm_param(sm); - return (pio->fstat & (1u << (PIO_FSTAT_RXEMPTY_LSB + sm))) != 0; -} - -/*! \brief Return the number of elements currently in a state machine's RX FIFO - * \ingroup hardware_pio - * - * \param pio The PIO instance; e.g. \ref pio0 or \ref pio1 - * \param sm State machine index (0..3) - * \return the number of elements in the RX FIFO - */ -static inline uint pio_sm_get_rx_fifo_level(PIO pio, uint sm) { - check_pio_param(pio); - check_sm_param(sm); - uint bitoffs = PIO_FLEVEL_RX0_LSB + sm * (PIO_FLEVEL_RX1_LSB - PIO_FLEVEL_RX0_LSB); - const uint32_t mask = PIO_FLEVEL_RX0_BITS >> PIO_FLEVEL_RX0_LSB; - return (pio->flevel >> bitoffs) & mask; -} - -/*! \brief Determine if a state machine's TX FIFO is full - * \ingroup hardware_pio - * - * \param pio The PIO instance; e.g. \ref pio0 or \ref pio1 - * \param sm State machine index (0..3) - * \return true if the TX FIFO is full - */ -static inline bool pio_sm_is_tx_fifo_full(PIO pio, uint sm) { - check_pio_param(pio); - check_sm_param(sm); - return (pio->fstat & (1u << (PIO_FSTAT_TXFULL_LSB + sm))) != 0; -} - -/*! \brief Determine if a state machine's TX FIFO is empty - * \ingroup hardware_pio - * - * \param pio The PIO instance; e.g. \ref pio0 or \ref pio1 - * \param sm State machine index (0..3) - * \return true if the TX FIFO is empty - */ -static inline bool pio_sm_is_tx_fifo_empty(PIO pio, uint sm) { - check_pio_param(pio); - check_sm_param(sm); - return (pio->fstat & (1u << (PIO_FSTAT_TXEMPTY_LSB + sm))) != 0; -} - -/*! \brief Return the number of elements currently in a state machine's TX FIFO - * \ingroup hardware_pio - * - * \param pio The PIO instance; e.g. \ref pio0 or \ref pio1 - * \param sm State machine index (0..3) - * \return the number of elements in the TX FIFO - */ -static inline uint pio_sm_get_tx_fifo_level(PIO pio, uint sm) { - check_pio_param(pio); - check_sm_param(sm); - unsigned int bitoffs = PIO_FLEVEL_TX0_LSB + sm * (PIO_FLEVEL_TX1_LSB - PIO_FLEVEL_TX0_LSB); - const uint32_t mask = PIO_FLEVEL_TX0_BITS >> PIO_FLEVEL_TX0_LSB; - return (pio->flevel >> bitoffs) & mask; -} - -/*! \brief Write a word of data to a state machine's TX FIFO, blocking if the FIFO is full - * \ingroup hardware_pio - * - * \param pio The PIO instance; e.g. \ref pio0 or \ref pio1 - * \param sm State machine index (0..3) - * \param data the 32 bit data value - */ -static inline void pio_sm_put_blocking(PIO pio, uint sm, uint32_t data) { - check_pio_param(pio); - check_sm_param(sm); - while (pio_sm_is_tx_fifo_full(pio, sm)) tight_loop_contents(); - pio_sm_put(pio, sm, data); -} - -/*! \brief Read a word of data from a state machine's RX FIFO, blocking if the FIFO is empty - * \ingroup hardware_pio - * - * \param pio The PIO instance; e.g. \ref pio0 or \ref pio1 - * \param sm State machine index (0..3) - */ -static inline uint32_t pio_sm_get_blocking(PIO pio, uint sm) { - check_pio_param(pio); - check_sm_param(sm); - while (pio_sm_is_rx_fifo_empty(pio, sm)) tight_loop_contents(); - return pio_sm_get(pio, sm); -} - -/*! \brief Empty out a state machine's TX FIFO - * \ingroup hardware_pio - * - * This method executes `pull` instructions on the state machine until the TX - * FIFO is empty. This disturbs the contents of the OSR, so see also - * pio_sm_clear_fifos() which clears both FIFOs but leaves the state machine's - * internal state undisturbed. - * - * \param pio The PIO instance; e.g. \ref pio0 or \ref pio1 - * \param sm State machine index (0..3) - * - * \sa pio_sm_clear_fifos() - */ -void pio_sm_drain_tx_fifo(PIO pio, uint sm); - -/*! \brief set the current clock divider for a state machine using a 16:8 fraction - * \ingroup hardware_pio - * - * \param pio The PIO instance; e.g. \ref pio0 or \ref pio1 - * \param sm State machine index (0..3) - * \param div_int the integer part of the clock divider - * \param div_frac the fractional part of the clock divider in 1/256s - */ -static inline void pio_sm_set_clkdiv_int_frac(PIO pio, uint sm, uint16_t div_int, uint8_t div_frac) { - check_pio_param(pio); - check_sm_param(sm); - invalid_params_if(HARDWARE_PIO, div_int == 0 && div_frac != 0); - pio->sm[sm].clkdiv = - (((uint)div_frac) << PIO_SM0_CLKDIV_FRAC_LSB) | - (((uint)div_int) << PIO_SM0_CLKDIV_INT_LSB); -} - -/*! \brief set the current clock divider for a state machine - * \ingroup hardware_pio - * - * \param pio The PIO instance; e.g. \ref pio0 or \ref pio1 - * \param sm State machine index (0..3) - * \param div the floating point clock divider - */ -static inline void pio_sm_set_clkdiv(PIO pio, uint sm, float div) { - check_pio_param(pio); - check_sm_param(sm); - uint16_t div_int; - uint8_t div_frac; - pio_calculate_clkdiv_from_float(div, &div_int, &div_frac); - pio_sm_set_clkdiv_int_frac(pio, sm, div_int, div_frac); -} - -/*! \brief Clear a state machine's TX and RX FIFOs - * \ingroup hardware_pio - * - * \param pio The PIO instance; e.g. \ref pio0 or \ref pio1 - * \param sm State machine index (0..3) - */ -static inline void pio_sm_clear_fifos(PIO pio, uint sm) { - // changing the FIFO join state clears the fifo - check_pio_param(pio); - check_sm_param(sm); - hw_xor_bits(&pio->sm[sm].shiftctrl, PIO_SM0_SHIFTCTRL_FJOIN_RX_BITS); - hw_xor_bits(&pio->sm[sm].shiftctrl, PIO_SM0_SHIFTCTRL_FJOIN_RX_BITS); -} - -/*! \brief Use a state machine to set a value on all pins for the PIO instance - * \ingroup hardware_pio - * - * This method repeatedly reconfigures the target state machine's pin configuration and executes 'set' instructions to set values on all 32 pins, - * before restoring the state machine's pin configuration to what it was. - * - * This method is provided as a convenience to set initial pin states, and should not be used against a state machine that is enabled. - * - * \param pio The PIO instance; e.g. \ref pio0 or \ref pio1 - * \param sm State machine index (0..3) to use - * \param pin_values the pin values to set - */ -void pio_sm_set_pins(PIO pio, uint sm, uint32_t pin_values); - -/*! \brief Use a state machine to set a value on multiple pins for the PIO instance - * \ingroup hardware_pio - * - * This method repeatedly reconfigures the target state machine's pin configuration and executes 'set' instructions to set values on up to 32 pins, - * before restoring the state machine's pin configuration to what it was. - * - * This method is provided as a convenience to set initial pin states, and should not be used against a state machine that is enabled. - * - * \param pio The PIO instance; e.g. \ref pio0 or \ref pio1 - * \param sm State machine index (0..3) to use - * \param pin_values the pin values to set (if the corresponding bit in pin_mask is set) - * \param pin_mask a bit for each pin to indicate whether the corresponding pin_value for that pin should be applied. - */ -void pio_sm_set_pins_with_mask(PIO pio, uint sm, uint32_t pin_values, uint32_t pin_mask); - -/*! \brief Use a state machine to set the pin directions for multiple pins for the PIO instance - * \ingroup hardware_pio - * - * This method repeatedly reconfigures the target state machine's pin configuration and executes 'set' instructions to set pin directions on up to 32 pins, - * before restoring the state machine's pin configuration to what it was. - * - * This method is provided as a convenience to set initial pin directions, and should not be used against a state machine that is enabled. - * - * \param pio The PIO instance; e.g. \ref pio0 or \ref pio1 - * \param sm State machine index (0..3) to use - * \param pin_dirs the pin directions to set - 1 = out, 0 = in (if the corresponding bit in pin_mask is set) - * \param pin_mask a bit for each pin to indicate whether the corresponding pin_value for that pin should be applied. - */ -void pio_sm_set_pindirs_with_mask(PIO pio, uint sm, uint32_t pin_dirs, uint32_t pin_mask); - -/*! \brief Use a state machine to set the same pin direction for multiple consecutive pins for the PIO instance - * \ingroup hardware_pio - * - * This method repeatedly reconfigures the target state machine's pin configuration and executes 'set' instructions to set the pin direction on consecutive pins, - * before restoring the state machine's pin configuration to what it was. - * - * This method is provided as a convenience to set initial pin directions, and should not be used against a state machine that is enabled. - * - * \param pio The PIO instance; e.g. \ref pio0 or \ref pio1 - * \param sm State machine index (0..3) to use - * \param pins_base the first pin to set a direction for - * \param pin_count the count of consecutive pins to set the direction for - * \param is_out the direction to set; true = out, false = in - * \return PICO_OK (0) on success, error code otherwise - */ -int pio_sm_set_consecutive_pindirs(PIO pio, uint sm, uint pins_base, uint pin_count, bool is_out); - -/*! \brief Mark a state machine as used - * \ingroup hardware_pio - * - * Method for cooperative claiming of hardware. Will cause a panic if the state machine - * is already claimed. Use of this method by libraries detects accidental - * configurations that would fail in unpredictable ways. - * - * \param pio The PIO instance; e.g. \ref pio0 or \ref pio1 - * \param sm State machine index (0..3) - */ -void pio_sm_claim(PIO pio, uint sm); - -/*! \brief Mark multiple state machines as used - * \ingroup hardware_pio - * - * Method for cooperative claiming of hardware. Will cause a panic if any of the state machines - * are already claimed. Use of this method by libraries detects accidental - * configurations that would fail in unpredictable ways. - * - * \param pio The PIO instance; e.g. \ref pio0 or \ref pio1 - * \param sm_mask Mask of state machine indexes - */ -void pio_claim_sm_mask(PIO pio, uint sm_mask); - -/*! \brief Mark a state machine as no longer used - * \ingroup hardware_pio - * - * Method for cooperative claiming of hardware. - * - * \param pio The PIO instance; e.g. \ref pio0 or \ref pio1 - * \param sm State machine index (0..3) - */ -void pio_sm_unclaim(PIO pio, uint sm); - -/*! \brief Claim a free state machine on a PIO instance - * \ingroup hardware_pio - * - * \param pio The PIO instance; e.g. \ref pio0 or \ref pio1 - * \param required if true the function will panic if none are available - * \return the state machine index or negative if required was false, and none were free (for - * backwards compatibility with prior SDK the error value is -1 i.e. PICO_ERROR_GENERIC) - */ -int pio_claim_unused_sm(PIO pio, bool required); - -/*! \brief Determine if a PIO state machine is claimed - * \ingroup hardware_pio - * - * \param pio The PIO instance; e.g. \ref pio0 or \ref pio1 - * \param sm State machine index (0..3) - * \return true if claimed, false otherwise - * \see pio_sm_claim - * \see pio_claim_sm_mask - */ -bool pio_sm_is_claimed(PIO pio, uint sm); - -/*! \brief Finds a PIO and statemachine and adds a program into PIO memory - * \ingroup hardware_pio - * - * \param program PIO program to add - * \param pio Returns the PIO hardware instance or NULL if no PIO is available - * \param sm Returns the index of the PIO state machine that was claimed - * \param offset Returns the instruction memory offset of the start of the program - * \return true on success, false otherwise - * \see pio_remove_program_unclaim_sm - */ -bool pio_claim_free_sm_and_add_program(const pio_program_t *program, PIO *pio, uint *sm, uint *offset); - -/*! \brief Finds a PIO and statemachine and adds a program into PIO memory - * \ingroup hardware_pio - * - * This variation of \ref pio_claim_free_sm_and_add_program is useful on RP2350 QFN80 where the "GPIO Base" - * must be set per PIO instance to either address the 32 GPIOs (0->31) or the 32 GPIOS (16-47). No single - * PIO instance can interact with both pins 0->15 or 32->47 at the same time. - * - * This method takes additional information about the GPIO pins needed (via gpi_base and gpio_count), - * and optionally will set the GPIO base (\see pio_set_gpio_base) of an unused PIO instance if necessary - * - * \param program PIO program to add - * \param pio Returns the PIO hardware instance or NULL if no PIO is available - * \param sm Returns the index of the PIO state machine that was claimed - * \param offset Returns the instruction memory offset of the start of the program - * \param gpio_base the lowest GPIO number required - * \param gpio_count the count of GPIOs required - * \param set_gpio_base if there is no free SM on a PIO instance with the right GPIO base, and there IS an unused PIO - * instance, then that PIO will be reconfigured so that this method can succeed - * - * \return true on success, false otherwise - * \see pio_remove_program_unclaim_sm - */ -bool pio_claim_free_sm_and_add_program_for_gpio_range(const pio_program_t *program, PIO *pio, uint *sm, uint *offset, uint gpio_base, uint gpio_count, bool set_gpio_base); - -/*! \brief Removes a program from PIO memory and unclaims the state machine - * \ingroup hardware_pio - * - * \param program PIO program to remove from memory - * \param pio PIO hardware instance being used - * \param sm PIO state machine that was claimed - * \param offset offset of the program in PIO memory - * \see pio_claim_free_sm_and_add_program - */ -void pio_remove_program_and_unclaim_sm(const pio_program_t *program, PIO pio, uint sm, uint offset); - -/*! \brief Return an IRQ for a PIO hardware instance - * \ingroup hardware_pio - * - * \param pio PIO hardware instance - * \param irqn 0 for PIOx_IRQ_0 or 1 for PIOx_IRQ_1 etc where x is the PIO number - * \return The IRQ number to use for the PIO - */ -static inline int pio_get_irq_num(PIO pio, uint irqn) { - check_pio_param(pio); - valid_params_if(HARDWARE_PIO, irqn < NUM_PIO_IRQS); - return PIO_IRQ_NUM(pio, irqn); -} - -/*! \brief Return the interrupt source for a state machines TX FIFO not full interrupt - * \ingroup hardware_pio - * - * \param sm State machine index (0..3) - * \return The interrupt source number for use in \ref pio_set_irqn_source_enabled or similar functions - */ -static inline pio_interrupt_source_t pio_get_tx_fifo_not_full_interrupt_source(uint sm) { - check_sm_param(sm); - return ((pio_interrupt_source_t)(pis_sm0_tx_fifo_not_full + sm)); -} - -/*! \brief Return the interrupt source for a state machines RX FIFO not empty interrupt - * \ingroup hardware_pio - * - * \param sm State machine index (0..3) - * \return The interrupt source number for use in \ref pio_set_irqn_source_enabled or similar functions - */ -static inline pio_interrupt_source_t pio_get_rx_fifo_not_empty_interrupt_source(uint sm) { - check_sm_param(sm); - return ((pio_interrupt_source_t)(pis_sm0_rx_fifo_not_empty + sm)); -} - -#ifdef __cplusplus -} -#endif - -#endif // _PIO_H_ diff --git a/lib/main/pico-sdk/rp2_common/hardware_pio/include/hardware/pio_instructions.h b/lib/main/pico-sdk/rp2_common/hardware_pio/include/hardware/pio_instructions.h deleted file mode 100644 index c27a4c1787..0000000000 --- a/lib/main/pico-sdk/rp2_common/hardware_pio/include/hardware/pio_instructions.h +++ /dev/null @@ -1,484 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _HARDWARE_PIO_INSTRUCTIONS_H -#define _HARDWARE_PIO_INSTRUCTIONS_H - -#include "pico.h" - -/** \brief PIO instruction encoding - * \defgroup pio_instructions pio_instructions - * \ingroup hardware_pio - * - * Functions for generating PIO instruction encodings programmatically. In debug builds - *`PARAM_ASSERTIONS_ENABLED_PIO_INSTRUCTIONS` can be set to 1 to enable validation of encoding function - * parameters. - * - * For fuller descriptions of the instructions in question see the "RP2040 Datasheet" - */ - -// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_PIO_INSTRUCTIONS, Enable/disable assertions in the PIO instructions, type=bool, default=0, group=pio_instructions -#ifndef PARAM_ASSERTIONS_ENABLED_PIO_INSTRUCTIONS -#define PARAM_ASSERTIONS_ENABLED_PIO_INSTRUCTIONS 0 -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -enum pio_instr_bits { - pio_instr_bits_jmp = 0x0000, - pio_instr_bits_wait = 0x2000, - pio_instr_bits_in = 0x4000, - pio_instr_bits_out = 0x6000, - pio_instr_bits_push = 0x8000, - pio_instr_bits_pull = 0x8080, - pio_instr_bits_mov = 0xa000, - pio_instr_bits_irq = 0xc000, - pio_instr_bits_set = 0xe000, -}; - -#ifndef NDEBUG -#define _PIO_INVALID_IN_SRC 0x08u -#define _PIO_INVALID_OUT_DEST 0x10u -#define _PIO_INVALID_SET_DEST 0x20u -#define _PIO_INVALID_MOV_SRC 0x40u -#define _PIO_INVALID_MOV_DEST 0x80u -#else -#define _PIO_INVALID_IN_SRC 0u -#define _PIO_INVALID_OUT_DEST 0u -#define _PIO_INVALID_SET_DEST 0u -#define _PIO_INVALID_MOV_SRC 0u -#define _PIO_INVALID_MOV_DEST 0u -#endif - -/*! \brief Enumeration of values to pass for source/destination args for instruction encoding functions - * \ingroup pio_instructions - * - * \note Not all values are suitable for all functions. Validity is only checked in debug mode when - * `PARAM_ASSERTIONS_ENABLED_PIO_INSTRUCTIONS` is 1 - */ -enum pio_src_dest { - pio_pins = 0u, - pio_x = 1u, - pio_y = 2u, - pio_null = 3u | _PIO_INVALID_SET_DEST | _PIO_INVALID_MOV_DEST, - pio_pindirs = 4u | _PIO_INVALID_IN_SRC | _PIO_INVALID_MOV_SRC | _PIO_INVALID_MOV_DEST, - pio_exec_mov = 4u | _PIO_INVALID_IN_SRC | _PIO_INVALID_OUT_DEST | _PIO_INVALID_SET_DEST | _PIO_INVALID_MOV_SRC, - pio_status = 5u | _PIO_INVALID_IN_SRC | _PIO_INVALID_OUT_DEST | _PIO_INVALID_SET_DEST | _PIO_INVALID_MOV_DEST, - pio_pc = 5u | _PIO_INVALID_IN_SRC | _PIO_INVALID_SET_DEST | _PIO_INVALID_MOV_SRC, - pio_isr = 6u | _PIO_INVALID_SET_DEST, - pio_osr = 7u | _PIO_INVALID_OUT_DEST | _PIO_INVALID_SET_DEST, - pio_exec_out = 7u | _PIO_INVALID_IN_SRC | _PIO_INVALID_SET_DEST | _PIO_INVALID_MOV_SRC | _PIO_INVALID_MOV_DEST, -}; - -static inline uint _pio_major_instr_bits(uint instr) { - return instr & 0xe000u; -} - -static inline uint _pio_encode_instr_and_args(enum pio_instr_bits instr_bits, uint arg1, uint arg2) { - valid_params_if(PIO_INSTRUCTIONS, arg1 <= 0x7); -#if PARAM_ASSERTIONS_ENABLED(PIO_INSTRUCTIONS) - uint32_t major = _pio_major_instr_bits(instr_bits); - if (major == pio_instr_bits_in || major == pio_instr_bits_out) { - assert(arg2 && arg2 <= 32); - } else { - assert(arg2 <= 31); - } -#endif - return instr_bits | (arg1 << 5u) | (arg2 & 0x1fu); -} - -static inline uint _pio_encode_instr_and_src_dest(enum pio_instr_bits instr_bits, enum pio_src_dest dest, uint value) { - return _pio_encode_instr_and_args(instr_bits, dest & 7u, value); -} - -/*! \brief Encode just the delay slot bits of an instruction - * \ingroup pio_instructions - * - * \note This function does not return a valid instruction encoding; instead it returns an encoding of the delay - * slot suitable for `OR`ing with the result of an encoding function for an actual instruction. Care should be taken when - * combining the results of this function with the results of \ref pio_encode_sideset and \ref pio_encode_sideset_opt - * as they share the same bits within the instruction encoding. - * - * \param cycles the number of cycles 0-31 (or less if side set is being used) - * \return the delay slot bits to be ORed with an instruction encoding - */ -static inline uint pio_encode_delay(uint cycles) { - // note that the maximum cycles will be smaller if sideset_bit_count > 0 - valid_params_if(PIO_INSTRUCTIONS, cycles <= 0x1f); - return cycles << 8u; -} - -/*! \brief Encode just the side set bits of an instruction (in non optional side set mode) - * \ingroup pio_instructions - * - * \note This function does not return a valid instruction encoding; instead it returns an encoding of the side set bits - * suitable for `OR`ing with the result of an encoding function for an actual instruction. Care should be taken when - * combining the results of this function with the results of \ref pio_encode_delay as they share the same bits - * within the instruction encoding. - * - * \param sideset_bit_count number of side set bits as would be specified via `.sideset` in pioasm - * \param value the value to sideset on the pins - * \return the side set bits to be ORed with an instruction encoding - */ -static inline uint pio_encode_sideset(uint sideset_bit_count, uint value) { - valid_params_if(PIO_INSTRUCTIONS, sideset_bit_count >= 1 && sideset_bit_count <= 5); - valid_params_if(PIO_INSTRUCTIONS, value <= ((1u << sideset_bit_count) - 1)); - return value << (13u - sideset_bit_count); -} - -/*! \brief Encode just the side set bits of an instruction (in optional -`opt` side set mode) - * \ingroup pio_instructions - * - * \note This function does not return a valid instruction encoding; instead it returns an encoding of the side set bits - * suitable for `OR`ing with the result of an encoding function for an actual instruction. Care should be taken when - * combining the results of this function with the results of \ref pio_encode_delay as they share the same bits - * within the instruction encoding. - * - * \param sideset_bit_count number of side set bits as would be specified via `.sideset opt` in pioasm - * \param value the value to sideset on the pins - * \return the side set bits to be ORed with an instruction encoding - */ -static inline uint pio_encode_sideset_opt(uint sideset_bit_count, uint value) { - valid_params_if(PIO_INSTRUCTIONS, sideset_bit_count >= 1 && sideset_bit_count <= 4); - valid_params_if(PIO_INSTRUCTIONS, value <= ((1u << sideset_bit_count) - 1)); - return 0x1000u | value << (12u - sideset_bit_count); -} - -/*! \brief Encode an unconditional JMP instruction - * \ingroup pio_instructions - * - * This is the equivalent of `JMP ` - * - * \param addr The target address 0-31 (an absolute address within the PIO instruction memory) - * \return The instruction encoding with 0 delay and no side set value - * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt - */ -static inline uint pio_encode_jmp(uint addr) { - return _pio_encode_instr_and_args(pio_instr_bits_jmp, 0, addr); -} - -/*! \brief Encode a conditional JMP if scratch X zero instruction - * \ingroup pio_instructions - * - * This is the equivalent of `JMP !X ` - * - * \param addr The target address 0-31 (an absolute address within the PIO instruction memory) - * \return The instruction encoding with 0 delay and no side set value - * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt - */ -static inline uint pio_encode_jmp_not_x(uint addr) { - return _pio_encode_instr_and_args(pio_instr_bits_jmp, 1, addr); -} - -/*! \brief Encode a conditional JMP if scratch X non-zero (and post-decrement X) instruction - * \ingroup pio_instructions - * - * This is the equivalent of `JMP X-- ` - * - * \param addr The target address 0-31 (an absolute address within the PIO instruction memory) - * \return The instruction encoding with 0 delay and no side set value - * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt - */ -static inline uint pio_encode_jmp_x_dec(uint addr) { - return _pio_encode_instr_and_args(pio_instr_bits_jmp, 2, addr); -} - -/*! \brief Encode a conditional JMP if scratch Y zero instruction - * \ingroup pio_instructions - * - * This is the equivalent of `JMP !Y ` - * - * \param addr The target address 0-31 (an absolute address within the PIO instruction memory) - * \return The instruction encoding with 0 delay and no side set value - * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt - */ -static inline uint pio_encode_jmp_not_y(uint addr) { - return _pio_encode_instr_and_args(pio_instr_bits_jmp, 3, addr); -} - -/*! \brief Encode a conditional JMP if scratch Y non-zero (and post-decrement Y) instruction - * \ingroup pio_instructions - * - * This is the equivalent of `JMP Y-- ` - * - * \param addr The target address 0-31 (an absolute address within the PIO instruction memory) - * \return The instruction encoding with 0 delay and no side set value - * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt - */ -static inline uint pio_encode_jmp_y_dec(uint addr) { - return _pio_encode_instr_and_args(pio_instr_bits_jmp, 4, addr); -} - -/*! \brief Encode a conditional JMP if scratch X not equal scratch Y instruction - * \ingroup pio_instructions - * - * This is the equivalent of `JMP X!=Y ` - * - * \param addr The target address 0-31 (an absolute address within the PIO instruction memory) - * \return The instruction encoding with 0 delay and no side set value - * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt - */ -static inline uint pio_encode_jmp_x_ne_y(uint addr) { - return _pio_encode_instr_and_args(pio_instr_bits_jmp, 5, addr); -} - -/*! \brief Encode a conditional JMP if input pin high instruction - * \ingroup pio_instructions - * - * This is the equivalent of `JMP PIN ` - * - * \param addr The target address 0-31 (an absolute address within the PIO instruction memory) - * \return The instruction encoding with 0 delay and no side set value - * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt - */ -static inline uint pio_encode_jmp_pin(uint addr) { - return _pio_encode_instr_and_args(pio_instr_bits_jmp, 6, addr); -} - -/*! \brief Encode a conditional JMP if output shift register not empty instruction - * \ingroup pio_instructions - * - * This is the equivalent of `JMP !OSRE ` - * - * \param addr The target address 0-31 (an absolute address within the PIO instruction memory) - * \return The instruction encoding with 0 delay and no side set value - * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt - */ -static inline uint pio_encode_jmp_not_osre(uint addr) { - return _pio_encode_instr_and_args(pio_instr_bits_jmp, 7, addr); -} - -static inline uint _pio_encode_irq(bool relative, uint irq) { - valid_params_if(PIO_INSTRUCTIONS, irq <= 7); - return (relative ? 0x10u : 0x0u) | irq; -} - -/*! \brief Encode a WAIT for GPIO pin instruction - * \ingroup pio_instructions - * - * This is the equivalent of `WAIT GPIO ` - * - * \param polarity true for `WAIT 1`, false for `WAIT 0` - * \param gpio The real GPIO number 0-31 - * \return The instruction encoding with 0 delay and no side set value - * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt - */ -static inline uint pio_encode_wait_gpio(bool polarity, uint gpio) { - return _pio_encode_instr_and_args(pio_instr_bits_wait, 0u | (polarity ? 4u : 0u), gpio); -} - -/*! \brief Encode a WAIT for pin instruction - * \ingroup pio_instructions - * - * This is the equivalent of `WAIT PIN ` - * - * \param polarity true for `WAIT 1`, false for `WAIT 0` - * \param pin The pin number 0-31 relative to the executing SM's input pin mapping - * \return The instruction encoding with 0 delay and no side set value - * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt - */ -static inline uint pio_encode_wait_pin(bool polarity, uint pin) { - return _pio_encode_instr_and_args(pio_instr_bits_wait, 1u | (polarity ? 4u : 0u), pin); -} - -/*! \brief Encode a WAIT for IRQ instruction - * \ingroup pio_instructions - * - * This is the equivalent of `WAIT IRQ ` - * - * \param polarity true for `WAIT 1`, false for `WAIT 0` - * \param relative true for a `WAIT IRQ REL`, false for regular `WAIT IRQ ` - * \param irq the irq number 0-7 - * \return The instruction encoding with 0 delay and no side set value - * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt - */ -static inline uint pio_encode_wait_irq(bool polarity, bool relative, uint irq) { - valid_params_if(PIO_INSTRUCTIONS, irq <= 7); - return _pio_encode_instr_and_args(pio_instr_bits_wait, 2u | (polarity ? 4u : 0u), _pio_encode_irq(relative, irq)); -} - -/*! \brief Encode an IN instruction - * \ingroup pio_instructions - * - * This is the equivalent of `IN , ` - * - * \param src The source to take data from - * \param count The number of bits 1-32 - * \return The instruction encoding with 0 delay and no side set value - * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt - */ -static inline uint pio_encode_in(enum pio_src_dest src, uint count) { - valid_params_if(PIO_INSTRUCTIONS, !(src & _PIO_INVALID_IN_SRC)); - return _pio_encode_instr_and_src_dest(pio_instr_bits_in, src, count); -} - -/*! \brief Encode an OUT instruction - * \ingroup pio_instructions - * - * This is the equivalent of `OUT , ` - * - * \param dest The destination to write data to - * \param count The number of bits 1-32 - * \return The instruction encoding with 0 delay and no side set value - * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt - */ -static inline uint pio_encode_out(enum pio_src_dest dest, uint count) { - valid_params_if(PIO_INSTRUCTIONS, !(dest & _PIO_INVALID_OUT_DEST)); - return _pio_encode_instr_and_src_dest(pio_instr_bits_out, dest, count); -} - -/*! \brief Encode a PUSH instruction - * \ingroup pio_instructions - * - * This is the equivalent of `PUSH , ` - * - * \param if_full true for `PUSH IF_FULL ...`, false for `PUSH ...` - * \param block true for `PUSH ... BLOCK`, false for `PUSH ...` - * \return The instruction encoding with 0 delay and no side set value - * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt - */ -static inline uint pio_encode_push(bool if_full, bool block) { - return _pio_encode_instr_and_args(pio_instr_bits_push, (if_full ? 2u : 0u) | (block ? 1u : 0u), 0); -} - -/*! \brief Encode a PULL instruction - * \ingroup pio_instructions - * - * This is the equivalent of `PULL , ` - * - * \param if_empty true for `PULL IF_EMPTY ...`, false for `PULL ...` - * \param block true for `PULL ... BLOCK`, false for `PULL ...` - * \return The instruction encoding with 0 delay and no side set value - * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt - */ -static inline uint pio_encode_pull(bool if_empty, bool block) { - return _pio_encode_instr_and_args(pio_instr_bits_pull, (if_empty ? 2u : 0u) | (block ? 1u : 0u), 0); -} - -/*! \brief Encode a MOV instruction - * \ingroup pio_instructions - * - * This is the equivalent of `MOV , ` - * - * \param dest The destination to write data to - * \param src The source to take data from - * \return The instruction encoding with 0 delay and no side set value - * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt - */ -static inline uint pio_encode_mov(enum pio_src_dest dest, enum pio_src_dest src) { - valid_params_if(PIO_INSTRUCTIONS, !(dest & _PIO_INVALID_MOV_DEST)); - valid_params_if(PIO_INSTRUCTIONS, !(src & _PIO_INVALID_MOV_SRC)); - return _pio_encode_instr_and_src_dest(pio_instr_bits_mov, dest, src & 7u); -} - -/*! \brief Encode a MOV instruction with bit invert - * \ingroup pio_instructions - * - * This is the equivalent of `MOV , ~` - * - * \param dest The destination to write inverted data to - * \param src The source to take data from - * \return The instruction encoding with 0 delay and no side set value - * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt - */ -static inline uint pio_encode_mov_not(enum pio_src_dest dest, enum pio_src_dest src) { - valid_params_if(PIO_INSTRUCTIONS, !(dest & _PIO_INVALID_MOV_DEST)); - valid_params_if(PIO_INSTRUCTIONS, !(src & _PIO_INVALID_MOV_SRC)); - return _pio_encode_instr_and_src_dest(pio_instr_bits_mov, dest, (1u << 3u) | (src & 7u)); -} - -/*! \brief Encode a MOV instruction with bit reverse - * \ingroup pio_instructions - * - * This is the equivalent of `MOV , ::` - * - * \param dest The destination to write bit reversed data to - * \param src The source to take data from - * \return The instruction encoding with 0 delay and no side set value - * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt - */ -static inline uint pio_encode_mov_reverse(enum pio_src_dest dest, enum pio_src_dest src) { - valid_params_if(PIO_INSTRUCTIONS, !(dest & _PIO_INVALID_MOV_DEST)); - valid_params_if(PIO_INSTRUCTIONS, !(src & _PIO_INVALID_MOV_SRC)); - return _pio_encode_instr_and_src_dest(pio_instr_bits_mov, dest, (2u << 3u) | (src & 7u)); -} - -/*! \brief Encode a IRQ SET instruction - * \ingroup pio_instructions - * - * This is the equivalent of `IRQ SET ` - * - * \param relative true for a `IRQ SET REL`, false for regular `IRQ SET ` - * \param irq the irq number 0-7 - * \return The instruction encoding with 0 delay and no side set value - * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt - */ -static inline uint pio_encode_irq_set(bool relative, uint irq) { - return _pio_encode_instr_and_args(pio_instr_bits_irq, 0, _pio_encode_irq(relative, irq)); -} - -/*! \brief Encode a IRQ WAIT instruction - * \ingroup pio_instructions - * - * This is the equivalent of `IRQ WAIT ` - * - * \param relative true for a `IRQ WAIT REL`, false for regular `IRQ WAIT ` - * \param irq the irq number 0-7 - * \return The instruction encoding with 0 delay and no side set value - * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt - */ -static inline uint pio_encode_irq_wait(bool relative, uint irq) { - return _pio_encode_instr_and_args(pio_instr_bits_irq, 1, _pio_encode_irq(relative, irq)); -} - -/*! \brief Encode a IRQ CLEAR instruction - * \ingroup pio_instructions - * - * This is the equivalent of `IRQ CLEAR ` - * - * \param relative true for a `IRQ CLEAR REL`, false for regular `IRQ CLEAR ` - * \param irq the irq number 0-7 - * \return The instruction encoding with 0 delay and no side set value - * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt - */ -static inline uint pio_encode_irq_clear(bool relative, uint irq) { - return _pio_encode_instr_and_args(pio_instr_bits_irq, 2, _pio_encode_irq(relative, irq)); -} - -/*! \brief Encode a SET instruction - * \ingroup pio_instructions - * - * This is the equivalent of `SET , ` - * - * \param dest The destination to apply the value to - * \param value The value 0-31 - * \return The instruction encoding with 0 delay and no side set value - * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt - */ -static inline uint pio_encode_set(enum pio_src_dest dest, uint value) { - valid_params_if(PIO_INSTRUCTIONS, !(dest & _PIO_INVALID_SET_DEST)); - return _pio_encode_instr_and_src_dest(pio_instr_bits_set, dest, value); -} - -/*! \brief Encode a NOP instruction - * \ingroup pio_instructions - * - * This is the equivalent of `NOP` which is itself encoded as `MOV y, y` - * - * \return The instruction encoding with 0 delay and no side set value - * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt - */ -static inline uint pio_encode_nop(void) { - return pio_encode_mov(pio_y, pio_y); -} - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/lib/main/pico-sdk/rp2_common/hardware_pio/pio.c b/lib/main/pico-sdk/rp2_common/hardware_pio/pio.c deleted file mode 100644 index 120dbf3f10..0000000000 --- a/lib/main/pico-sdk/rp2_common/hardware_pio/pio.c +++ /dev/null @@ -1,396 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "hardware/claim.h" -#include "hardware/pio.h" -#include "hardware/pio_instructions.h" - -// sanity check -check_hw_layout(pio_hw_t, sm[0].clkdiv, PIO_SM0_CLKDIV_OFFSET); -check_hw_layout(pio_hw_t, sm[1].clkdiv, PIO_SM1_CLKDIV_OFFSET); -check_hw_layout(pio_hw_t, instr_mem[0], PIO_INSTR_MEM0_OFFSET); -check_hw_layout(pio_hw_t, inte0, PIO_IRQ0_INTE_OFFSET); -check_hw_layout(pio_hw_t, irq_ctrl[0].inte, PIO_IRQ0_INTE_OFFSET); -check_hw_layout(pio_hw_t, txf[1], PIO_TXF1_OFFSET); -check_hw_layout(pio_hw_t, rxf[3], PIO_RXF3_OFFSET); -check_hw_layout(pio_hw_t, ints1, PIO_IRQ1_INTS_OFFSET); -check_hw_layout(pio_hw_t, irq_ctrl[1].ints, PIO_IRQ1_INTS_OFFSET); - -static uint8_t claimed[(NUM_PIO_STATE_MACHINES * NUM_PIOS + 7) >> 3]; - -void pio_sm_claim(PIO pio, uint sm) { - check_sm_param(sm); - uint which = pio_get_index(pio); - const char *msg = -#if PICO_PIO_VERSION > 0 - which == 2 ? "PIO 2 SM (%d - 8) already claimed" : -#endif - which == 1 ? "PIO 1 SM (%d - 4) already claimed" : - "PIO 0 SM %d already claimed"; - hw_claim_or_assert(&claimed[0], which * NUM_PIO_STATE_MACHINES + sm, msg); -} - -void pio_claim_sm_mask(PIO pio, uint sm_mask) { - for(uint i = 0; sm_mask; i++, sm_mask >>= 1u) { - if (sm_mask & 1u) pio_sm_claim(pio, i); - } -} - -void pio_sm_unclaim(PIO pio, uint sm) { - check_sm_param(sm); - uint which = pio_get_index(pio); - hw_claim_clear(&claimed[0], which * NUM_PIO_STATE_MACHINES + sm); -} - -int pio_claim_unused_sm(PIO pio, bool required) { - // PIO index ranges from 0 to NUM_PIOS - 1. - uint which = pio_get_index(pio); - uint base = which * NUM_PIO_STATE_MACHINES; - int index = hw_claim_unused_from_range((uint8_t*)&claimed[0], required, base, - base + NUM_PIO_STATE_MACHINES - 1, "No PIO state machines are available"); - return index >= (int)base ? index - (int)base : -1; -} - -bool pio_sm_is_claimed(PIO pio, uint sm) { - check_sm_param(sm); - uint which = pio_get_index(pio); - return hw_is_claimed(&claimed[0], which * NUM_PIO_STATE_MACHINES + sm); -} - -static_assert(PIO_INSTRUCTION_COUNT <= 32, ""); -static uint32_t _used_instruction_space[NUM_PIOS]; - -static int find_offset_for_program(PIO pio, const pio_program_t *program) { - assert(program->length <= PIO_INSTRUCTION_COUNT); - uint32_t used_mask = _used_instruction_space[pio_get_index(pio)]; - uint32_t program_mask = (1u << program->length) - 1; - if (program->origin >= 0) { - if (program->origin > 32 - program->length) return PICO_ERROR_GENERIC; - return used_mask & (program_mask << program->origin) ? -1 : program->origin; - } else { - // work down from the top always - for (int i = 32 - program->length; i >= 0; i--) { - if (!(used_mask & (program_mask << (uint) i))) { - return i; - } - } - return PICO_ERROR_INSUFFICIENT_RESOURCES; - } -} - -static int pio_set_gpio_base_unsafe(PIO pio, uint gpio_base) { - invalid_params_if_and_return(PIO, gpio_base != 0 && (!PICO_PIO_VERSION || gpio_base != 16), PICO_ERROR_BAD_ALIGNMENT); -#if PICO_PIO_VERSION > 0 - uint32_t used_mask = _used_instruction_space[pio_get_index(pio)]; - invalid_params_if_and_return(PIO, used_mask, PICO_ERROR_INVALID_STATE); - pio->gpiobase = gpio_base; -#else - ((void)pio); - ((void)gpio_base); -#endif - return PICO_OK; -} - -int pio_set_gpio_base(PIO pio, uint gpio_base) { - int rc = PICO_OK; -#if PICO_PIO_VERSION > 0 - uint32_t save = hw_claim_lock(); - rc = pio_set_gpio_base_unsafe(pio, gpio_base); - hw_claim_unlock(save); -#else - ((void)pio); - ((void)gpio_base); -#endif - return rc; -} - -static bool is_gpio_compatible(PIO pio, uint32_t used_gpio_ranges) { -#if PICO_PIO_VERSION > 0 - bool gpio_base = pio_get_gpio_base(pio); - return !((gpio_base && (used_gpio_ranges & 1)) || - (!gpio_base && (used_gpio_ranges & 4))); -#else - ((void)pio); - ((void)used_gpio_ranges); - return true; -#endif -} - -static bool is_program_gpio_compatible(PIO pio, const pio_program_t *program) { -#if PICO_PIO_VERSION > 0 - return is_gpio_compatible(pio, program->used_gpio_ranges); -#else - ((void)pio); - ((void)program); - return true; -#endif -} - -static int add_program_at_offset_check(PIO pio, const pio_program_t *program, uint offset) { - valid_params_if(HARDWARE_PIO, offset < PIO_INSTRUCTION_COUNT); - valid_params_if(HARDWARE_PIO, offset + program->length <= PIO_INSTRUCTION_COUNT); -#if PICO_PIO_VERSION == 0 - if (program->pio_version) return PICO_ERROR_VERSION_MISMATCH; -#endif - if (!is_program_gpio_compatible(pio, program)) return PICO_ERROR_BAD_ALIGNMENT; // todo better error? - if (program->origin >= 0 && (uint)program->origin != offset) return PICO_ERROR_BAD_ALIGNMENT; // todo better error? - uint32_t used_mask = _used_instruction_space[pio_get_index(pio)]; - uint32_t program_mask = (1u << program->length) - 1; - return (used_mask & (program_mask << offset)) ? PICO_ERROR_INSUFFICIENT_RESOURCES : PICO_OK; -} - -bool pio_can_add_program(PIO pio, const pio_program_t *program) { - uint32_t save = hw_claim_lock(); - int rc = find_offset_for_program(pio, program); - if (rc >= 0) rc = add_program_at_offset_check(pio, program, (uint)rc); - hw_claim_unlock(save); - return rc == 0; -} - -bool pio_can_add_program_at_offset(PIO pio, const pio_program_t *program, uint offset) { - uint32_t save = hw_claim_lock(); - bool rc = add_program_at_offset_check(pio, program, offset) == 0; - hw_claim_unlock(save); - return rc; -} - -static int add_program_at_offset(PIO pio, const pio_program_t *program, uint offset) { - int rc = add_program_at_offset_check(pio, program, offset); - if (rc != 0) return rc; - for (uint i = 0; i < program->length; ++i) { - uint16_t instr = program->instructions[i]; - pio->instr_mem[offset + i] = pio_instr_bits_jmp != _pio_major_instr_bits(instr) ? instr : instr + offset; - } - uint32_t program_mask = (1u << program->length) - 1; - _used_instruction_space[pio_get_index(pio)] |= program_mask << offset; - return (int)offset; -} - -// these assert if unable -int pio_add_program(PIO pio, const pio_program_t *program) { - uint32_t save = hw_claim_lock(); - int offset = find_offset_for_program(pio, program); - if (offset >= 0) { - offset = add_program_at_offset(pio, program, (uint) offset); - } - hw_claim_unlock(save); - return offset; -} - -int pio_add_program_at_offset(PIO pio, const pio_program_t *program, uint offset) { - uint32_t save = hw_claim_lock(); - int rc = add_program_at_offset(pio, program, offset); - hw_claim_unlock(save); - return rc; -} - -void pio_remove_program(PIO pio, const pio_program_t *program, uint loaded_offset) { - uint32_t program_mask = (1u << program->length) - 1; - program_mask <<= loaded_offset; - uint32_t save = hw_claim_lock(); - assert(program_mask == (_used_instruction_space[pio_get_index(pio)] & program_mask)); - _used_instruction_space[pio_get_index(pio)] &= ~program_mask; - hw_claim_unlock(save); -} - -void pio_clear_instruction_memory(PIO pio) { - uint32_t save = hw_claim_lock(); - _used_instruction_space[pio_get_index(pio)] = 0; - for(uint i=0;iinstr_mem[i] = pio_encode_jmp(i); - } - hw_claim_unlock(save); -} - -// Set the value of all PIO pins. This is done by forcibly executing -// instructions on a "victim" state machine, sm. Ideally you should choose one -// which is not currently running a program. This is intended for one-time -// setup of initial pin states. -void pio_sm_set_pins(PIO pio, uint sm, uint32_t pins) { - check_pio_param(pio); - check_sm_param(sm); - uint32_t pinctrl_saved = pio->sm[sm].pinctrl; - uint32_t execctrl_saved = pio->sm[sm].execctrl; - hw_clear_bits(&pio->sm[sm].execctrl, 1u << PIO_SM0_EXECCTRL_OUT_STICKY_LSB); - uint remaining = 32; - uint base = 0; - while (remaining) { - uint decrement = remaining > 5 ? 5 : remaining; - pio->sm[sm].pinctrl = - (decrement << PIO_SM0_PINCTRL_SET_COUNT_LSB) | - (base << PIO_SM0_PINCTRL_SET_BASE_LSB); - pio_sm_exec(pio, sm, pio_encode_set(pio_pins, pins & 0x1fu)); - remaining -= decrement; - base += decrement; - pins >>= 5; - } - pio->sm[sm].pinctrl = pinctrl_saved; - pio->sm[sm].execctrl = execctrl_saved; -} - -void pio_sm_set_pins_with_mask(PIO pio, uint sm, uint32_t pinvals, uint32_t pin_mask) { - check_pio_param(pio); - check_sm_param(sm); - uint32_t pinctrl_saved = pio->sm[sm].pinctrl; - uint32_t execctrl_saved = pio->sm[sm].execctrl; - hw_clear_bits(&pio->sm[sm].execctrl, 1u << PIO_SM0_EXECCTRL_OUT_STICKY_LSB); - while (pin_mask) { - uint base = (uint)__builtin_ctz(pin_mask); - pio->sm[sm].pinctrl = - (1u << PIO_SM0_PINCTRL_SET_COUNT_LSB) | - (base << PIO_SM0_PINCTRL_SET_BASE_LSB); - pio_sm_exec(pio, sm, pio_encode_set(pio_pins, (pinvals >> base) & 0x1u)); - pin_mask &= pin_mask - 1; - } - pio->sm[sm].pinctrl = pinctrl_saved; - pio->sm[sm].execctrl = execctrl_saved; -} - -void pio_sm_set_pindirs_with_mask(PIO pio, uint sm, uint32_t pindirs, uint32_t pin_mask) { - check_pio_param(pio); - check_sm_param(sm); - uint32_t pinctrl_saved = pio->sm[sm].pinctrl; - uint32_t execctrl_saved = pio->sm[sm].execctrl; - hw_clear_bits(&pio->sm[sm].execctrl, 1u << PIO_SM0_EXECCTRL_OUT_STICKY_LSB); - while (pin_mask) { - uint base = (uint)__builtin_ctz(pin_mask); - pio->sm[sm].pinctrl = - (1u << PIO_SM0_PINCTRL_SET_COUNT_LSB) | - (base << PIO_SM0_PINCTRL_SET_BASE_LSB); - pio_sm_exec(pio, sm, pio_encode_set(pio_pindirs, (pindirs >> base) & 0x1u)); - pin_mask &= pin_mask - 1; - } - pio->sm[sm].pinctrl = pinctrl_saved; - pio->sm[sm].execctrl = execctrl_saved; -} - -int pio_sm_set_consecutive_pindirs(PIO pio, uint sm, uint pin, uint count, bool is_out) { - check_pio_param(pio); - check_sm_param(sm); - pin -= pio_get_gpio_base(pio); - invalid_params_if_and_return(PIO, pin >= 32u, PICO_ERROR_INVALID_ARG); - uint32_t pinctrl_saved = pio->sm[sm].pinctrl; - uint32_t execctrl_saved = pio->sm[sm].execctrl; - hw_clear_bits(&pio->sm[sm].execctrl, 1u << PIO_SM0_EXECCTRL_OUT_STICKY_LSB); - uint pindir_val = is_out ? 0x1f : 0; - while (count > 5) { - pio->sm[sm].pinctrl = (5u << PIO_SM0_PINCTRL_SET_COUNT_LSB) | (pin << PIO_SM0_PINCTRL_SET_BASE_LSB); - pio_sm_exec(pio, sm, pio_encode_set(pio_pindirs, pindir_val)); - count -= 5; - pin = (pin + 5) & 0x1f; - } - pio->sm[sm].pinctrl = (count << PIO_SM0_PINCTRL_SET_COUNT_LSB) | (pin << PIO_SM0_PINCTRL_SET_BASE_LSB); - pio_sm_exec(pio, sm, pio_encode_set(pio_pindirs, pindir_val)); - pio->sm[sm].pinctrl = pinctrl_saved; - pio->sm[sm].execctrl = execctrl_saved; - return PICO_OK; -} - -int pio_sm_init(PIO pio, uint sm, uint initial_pc, const pio_sm_config *config) { - valid_params_if(HARDWARE_PIO, initial_pc < PIO_INSTRUCTION_COUNT); - // Halt the machine, set some sensible defaults - pio_sm_set_enabled(pio, sm, false); - - int rc; - if (config) { - rc = pio_sm_set_config(pio, sm, config); - } else { - pio_sm_config c = pio_get_default_sm_config(); - rc = pio_sm_set_config(pio, sm, &c); - } - if (rc) return rc; - - pio_sm_clear_fifos(pio, sm); - - // Clear FIFO debug flags - const uint32_t fdebug_sm_mask = - (1u << PIO_FDEBUG_TXOVER_LSB) | - (1u << PIO_FDEBUG_RXUNDER_LSB) | - (1u << PIO_FDEBUG_TXSTALL_LSB) | - (1u << PIO_FDEBUG_RXSTALL_LSB); - pio->fdebug = fdebug_sm_mask << sm; - - // Finally, clear some internal SM state - pio_sm_restart(pio, sm); - pio_sm_clkdiv_restart(pio, sm); - pio_sm_exec(pio, sm, pio_encode_jmp(initial_pc)); - return PICO_OK; -} - -void pio_sm_drain_tx_fifo(PIO pio, uint sm) { - uint instr = (pio->sm[sm].shiftctrl & PIO_SM0_SHIFTCTRL_AUTOPULL_BITS) ? pio_encode_out(pio_null, 32) : - pio_encode_pull(false, false); - while (!pio_sm_is_tx_fifo_empty(pio, sm)) { - pio_sm_exec(pio, sm, instr); - } -} - -bool pio_claim_free_sm_and_add_program(const pio_program_t *program, PIO *pio, uint *sm, uint *offset) { - return pio_claim_free_sm_and_add_program_for_gpio_range(program, pio, sm, offset, 0, 0, false); -} - -bool pio_claim_free_sm_and_add_program_for_gpio_range(const pio_program_t *program, PIO *pio, uint *sm, uint *offset, uint gpio_base, uint gpio_count, bool set_gpio_base) { - invalid_params_if(HARDWARE_PIO, (gpio_base + gpio_count) > NUM_BANK0_GPIOS); - -#if !PICO_PIO_USE_GPIO_BASE - // short-circuit some logic when not using GIO_BASE - set_gpio_base = 0; - gpio_count = 0; -#endif - - // note if we gpio_count == 0, we don't care about GPIOs so use a zero mask for what we require - // if gpio_count > 0, then we just set used mask for the ends, since that is all that is checked at the moment - uint32_t required_gpio_ranges; - if (gpio_count) required_gpio_ranges = (1u << (gpio_base >> 4)) | (1u << ((gpio_base + gpio_count - 1) >> 4)); - else required_gpio_ranges = 0; - int passes = set_gpio_base ? 2 : 1; - - for(int pass = 0; pass < passes; pass++) { - int pio_num = NUM_PIOS; - while (pio_num--) { - *pio = pio_get_instance((uint)pio_num); - // We need to claim an SM on the PIO - int8_t sm_index[NUM_PIO_STATE_MACHINES]; - // on second pass, if there is one, we try and claim all the state machines so that we can change the GPIO base - uint num_claimed; - for(num_claimed = 0; num_claimed < (pass ? NUM_PIO_STATE_MACHINES : 1u) ; num_claimed++) { - sm_index[num_claimed] = (int8_t)pio_claim_unused_sm(*pio, false); - if (sm_index[num_claimed] < 0) break; - } - if (num_claimed && (!pass || num_claimed == NUM_PIO_STATE_MACHINES)) { - uint32_t save = hw_claim_lock(); - if (pass) { - pio_set_gpio_base_unsafe(*pio, required_gpio_ranges & 4 ? 16 : 0); - } - int rc = is_gpio_compatible(*pio, required_gpio_ranges) ? PICO_OK : PICO_ERROR_BAD_ALIGNMENT; - if (rc == PICO_OK) rc = find_offset_for_program(*pio, program); - if (rc >= 0) rc = add_program_at_offset(*pio, program, (uint)rc); - if (rc >= 0) { - *sm = (uint) sm_index[0]; - *offset = (uint) rc; - } - hw_claim_unlock(save); - // always un-claim all SMs other than the one we need (array index 0), - // or all of them if we had an error - for (uint i = (rc >= 0); i < num_claimed; i++) { - pio_sm_unclaim(*pio, (uint) sm_index[i]); - } - if (rc >= 0) { - return true; - } - } - } - } - *pio = NULL; - return false; -} - -void pio_remove_program_and_unclaim_sm(const pio_program_t *program, PIO pio, uint sm, uint offset) { - check_pio_param(pio); - check_sm_param(sm); - pio_remove_program(pio, program, offset); - pio_sm_unclaim(pio, sm); -} diff --git a/lib/main/pico-sdk/rp2_common/hardware_pll/include/hardware/pll.h b/lib/main/pico-sdk/rp2_common/hardware_pll/include/hardware/pll.h deleted file mode 100644 index 357660a736..0000000000 --- a/lib/main/pico-sdk/rp2_common/hardware_pll/include/hardware/pll.h +++ /dev/null @@ -1,90 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _HARDWARE_PLL_H -#define _HARDWARE_PLL_H - -#include "pico.h" -#include "hardware/structs/pll.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** \file hardware/pll.h - * \defgroup hardware_pll hardware_pll - * - * \brief Phase Locked Loop control APIs - * - * There are two PLLs in RP2040. They are: - * - pll_sys - Used to generate up to a 133MHz system clock - * - pll_usb - Used to generate a 48MHz USB reference clock - * - * For details on how the PLLs are calculated, please refer to the RP2040 datasheet. - */ - -typedef pll_hw_t *PLL; - -#define pll_sys pll_sys_hw -#define pll_usb pll_usb_hw - -#ifndef PICO_PLL_VCO_MIN_FREQ_HZ -#ifdef PICO_PLL_VCO_MIN_FREQ_MHZ -#define PICO_PLL_VCO_MIN_FREQ_HZ (PICO_PLL_VCO_MIN_FREQ_MHZ * MHZ) -#elif defined(PICO_PLL_VCO_MIN_FREQ_KHZ) -#define PICO_PLL_VCO_MIN_FREQ_HZ (PICO_PLL_VCO_MIN_FREQ_KHZ * KHZ) -#else -#define PICO_PLL_VCO_MIN_FREQ_HZ (750 * MHZ) -#endif -#endif - -#ifndef PICO_PLL_VCO_MAX_FREQ_HZ -#ifdef PICO_PLL_VCO_MAX_FREQ_MHZ -#define PICO_PLL_VCO_MAX_FREQ_HZ (PICO_PLL_VCO_MAX_FREQ_MHZ * MHZ) -#elif defined(PICO_PLL_VCO_MAX_FREQ_KHZ) -#define PICO_PLL_VCO_MAX_FREQ_HZ (PICO_PLL_VCO_MAX_FREQ_KHZ * KHZ) -#else -#define PICO_PLL_VCO_MAX_FREQ_HZ (1600 * MHZ) -#endif -#endif - -/*! \brief Initialise specified PLL. - * \ingroup hardware_pll - * \param pll pll_sys or pll_usb - * \param ref_div Input clock divider. - * \param vco_freq Requested output from the VCO (voltage controlled oscillator) - * \param post_div1 Post Divider 1 - range 1-7. Must be >= post_div2 - * \param post_div2 Post Divider 2 - range 1-7 - */ -void pll_init(PLL pll, uint ref_div, uint vco_freq, uint post_div1, uint post_div2); - -/*! \brief Release/uninitialise specified PLL. - * \ingroup hardware_pll - * - * This will turn off the power to the specified PLL. Note this function does not currently check if - * the PLL is in use before powering it off so should be used with care. - * - * \param pll pll_sys or pll_usb - */ -void pll_deinit(PLL pll); - -/** - * \def PLL_RESET_NUM(pll) - * \ingroup hardware_pll - * \hideinitializer - * \brief Returns the \ref reset_num_t used to reset a given PLL instance - * - * Note this macro is intended to resolve at compile time, and does no parameter checking - */ -#ifndef PLL_RESET_NUM -#define PLL_RESET_NUM(pll) ((pll_usb_hw == (pll)) ? RESET_PLL_USB : RESET_PLL_SYS) -#endif - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/lib/main/pico-sdk/rp2_common/hardware_pll/pll.c b/lib/main/pico-sdk/rp2_common/hardware_pll/pll.c deleted file mode 100644 index 5df52e2364..0000000000 --- a/lib/main/pico-sdk/rp2_common/hardware_pll/pll.c +++ /dev/null @@ -1,76 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -// For frequency and PLL definitions etc. -#include "hardware/clocks.h" -#include "hardware/pll.h" -#include "hardware/resets.h" - -/// \tag::pll_init_calculations[] -void pll_init(PLL pll, uint refdiv, uint vco_freq, uint post_div1, uint post_div2) { - uint32_t ref_freq = XOSC_HZ / refdiv; - - // Check vco freq is in an acceptable range - assert(vco_freq >= PICO_PLL_VCO_MIN_FREQ_HZ && vco_freq <= PICO_PLL_VCO_MAX_FREQ_HZ); - - // What are we multiplying the reference clock by to get the vco freq - // (The regs are called div, because you divide the vco output and compare it to the refclk) - uint32_t fbdiv = vco_freq / ref_freq; -/// \end::pll_init_calculations[] - - // fbdiv - assert(fbdiv >= 16 && fbdiv <= 320); - - // Check divider ranges - assert((post_div1 >= 1 && post_div1 <= 7) && (post_div2 >= 1 && post_div2 <= 7)); - - // post_div1 should be >= post_div2 - // from appnote page 11 - // postdiv1 is designed to operate with a higher input frequency than postdiv2 - - // Check that reference frequency is no greater than vco / 16 - assert(ref_freq <= (vco_freq / 16)); - - // div1 feeds into div2 so if div1 is 5 and div2 is 2 then you get a divide by 10 - uint32_t pdiv = (post_div1 << PLL_PRIM_POSTDIV1_LSB) | - (post_div2 << PLL_PRIM_POSTDIV2_LSB); - -/// \tag::pll_init_finish[] - if ((pll->cs & PLL_CS_LOCK_BITS) && - (refdiv == (pll->cs & PLL_CS_REFDIV_BITS)) && - (fbdiv == (pll->fbdiv_int & PLL_FBDIV_INT_BITS)) && - (pdiv == (pll->prim & (PLL_PRIM_POSTDIV1_BITS | PLL_PRIM_POSTDIV2_BITS)))) { - // do not disrupt PLL that is already correctly configured and operating - return; - } - - reset_unreset_block_num_wait_blocking(PLL_RESET_NUM(pll)); - - // Load VCO-related dividers before starting VCO - pll->cs = refdiv; - pll->fbdiv_int = fbdiv; - - // Turn on PLL - uint32_t power = PLL_PWR_PD_BITS | // Main power - PLL_PWR_VCOPD_BITS; // VCO Power - - hw_clear_bits(&pll->pwr, power); - - // Wait for PLL to lock - while (!(pll->cs & PLL_CS_LOCK_BITS)) tight_loop_contents(); - - // Set up post dividers - pll->prim = pdiv; - - // Turn on post divider - hw_clear_bits(&pll->pwr, PLL_PWR_POSTDIVPD_BITS); -/// \end::pll_init_finish[] -} - -void pll_deinit(PLL pll) { - // todo: Make sure there are no sources running from this pll? - pll->pwr = PLL_PWR_BITS; -} diff --git a/lib/main/pico-sdk/rp2_common/hardware_powman/include/hardware/powman.h b/lib/main/pico-sdk/rp2_common/hardware_powman/include/hardware/powman.h deleted file mode 100644 index fce8c14cd2..0000000000 --- a/lib/main/pico-sdk/rp2_common/hardware_powman/include/hardware/powman.h +++ /dev/null @@ -1,275 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _HARDWARE_POWMAN_H -#define _HARDWARE_POWMAN_H - -#include "pico.h" -#include "hardware/structs/powman.h" - -/** \file hardware/powman.h - * \defgroup hardware_powman hardware_powman - * - * \brief Power Management API - * - */ - -// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_HARDWARE_POWMAN, Enable/disable hardware_powman assertions, type=bool, default=0, group=hardware_powman -#ifndef PARAM_ASSERTIONS_ENABLED_HARDWARE_POWMAN -#define PARAM_ASSERTIONS_ENABLED_HARDWARE_POWMAN 0 -#endif - -/*! \brief Use the ~32KHz low power oscillator as the powman timer source - * \ingroup hardware_powman - */ -void powman_timer_set_1khz_tick_source_lposc(void); - -/*! \brief Use the low power oscillator (specifying frequency) as the powman timer source - * \ingroup hardware_powman - * \param lposc_freq_hz specify an exact lposc freq to trim it - */ -void powman_timer_set_1khz_tick_source_lposc_with_hz(uint32_t lposc_freq_hz); - -/*! \brief Use the crystal oscillator as the powman timer source - * \ingroup hardware_powman - */ -void powman_timer_set_1khz_tick_source_xosc(void); - -/*! \brief Use the crystal oscillator as the powman timer source - * \ingroup hardware_powman - * \param xosc_freq_hz specify a crystal frequency - */ -void powman_timer_set_1khz_tick_source_xosc_with_hz(uint32_t xosc_freq_hz); - -/*! \brief Use a 1KHz external tick as the powman timer source - * \ingroup hardware_powman - * \param gpio the gpio to use. must be 12, 14, 20, 22 - */ -void powman_timer_set_1khz_tick_source_gpio(uint32_t gpio); - -/*! \brief Use a 1Hz external signal as the powman timer source for seconds only - * \ingroup hardware_powman - * - * Use a 1hz sync signal, such as from a gps for the seconds component of the timer. - * The milliseconds will still come from another configured source such as xosc or lposc - * - * \param gpio the gpio to use. must be 12, 14, 20, 22 - */ -void powman_timer_enable_gpio_1hz_sync(uint32_t gpio); - -/*! \brief Stop using 1Hz external signal as the powman timer source for seconds - * \ingroup hardware_powman - */ -void powman_timer_disable_gpio_1hz_sync(void); - -/*! \brief Returns current time in ms - * \ingroup hardware_powman - */ -uint64_t powman_timer_get_ms(void); - -/*! \brief Set current time in ms - * \ingroup hardware_powman - * - * \param time_ms Current time in ms - */ -void powman_timer_set_ms(uint64_t time_ms); - -/*! \brief Set an alarm at an absolute time in ms - * \ingroup hardware_powman - * - * Note, the timer is stopped and then restarted as part of this function. This only controls the alarm - * if you want to use the alarm to wake up powman then you should use \ref powman_enable_alarm_wakeup_at_ms - * - * \param alarm_time_ms time at which the alarm will fire - */ -void powman_timer_enable_alarm_at_ms(uint64_t alarm_time_ms); - -/*! \brief Disable the alarm - * \ingroup hardware_powman - * - * Once an alarm has fired it must be disabled to stop firing as the alarm - * comparison is alarm = alarm_time >= current_time - */ -void powman_timer_disable_alarm(void); - -/*! \brief hw_set_bits helper function - * \ingroup hardware_powman - * - * \param reg register to set - * \param bits bits of register to set - * Powman needs a password for writes, to prevent accidentally writing to it. - * This function implements hw_set_bits with an appropriate password. - */ -static inline void powman_set_bits(volatile uint32_t *reg, uint32_t bits) { - invalid_params_if(HARDWARE_POWMAN, bits >> 16); - hw_set_bits(reg, POWMAN_PASSWORD_BITS | bits); -} - -/*! \brief hw_clear_bits helper function - * \ingroup hardware_powman - * - * Powman needs a password for writes, to prevent accidentally writing to it. - * This function implements hw_clear_bits with an appropriate password. - * - * \param reg register to clear - * \param bits bits of register to clear - */ -static inline void powman_clear_bits(volatile uint32_t *reg, uint32_t bits) { - invalid_params_if(HARDWARE_POWMAN, bits >> 16); - hw_clear_bits(reg, POWMAN_PASSWORD_BITS | bits); -} - -/*! \brief Determine if the powman timer is running - * \ingroup hardware_powman - */ -static inline bool powman_timer_is_running(void) { - return powman_hw->timer & POWMAN_TIMER_RUN_BITS; -} - -/*! \brief Stop the powman timer - * \ingroup hardware_powman - */ -static inline void powman_timer_stop(void) { - powman_clear_bits(&powman_hw->timer, POWMAN_TIMER_RUN_BITS); -} - -/*! \brief Start the powman timer - * \ingroup hardware_powman - */ -static inline void powman_timer_start(void) { - powman_set_bits(&powman_hw->timer, POWMAN_TIMER_RUN_BITS); -} - -/*! \brief Clears the powman alarm - * \ingroup hardware_powman - * - * Note, the alarm must be disabled (see \ref powman_timer_disable_alarm) before clearing the alarm, as the alarm fires if - * the time is greater than equal to the target, so once the time has passed the alarm will always fire while enabled. - */ -static inline void powman_clear_alarm(void) { - powman_clear_bits(&powman_hw->timer, POWMAN_TIMER_ALARM_BITS); -} - -/*! \brief Power domains of powman - * \ingroup hardware_powman - */ -enum powman_power_domains { - POWMAN_POWER_DOMAIN_SRAM_BANK1 = 0, ///< bank1 includes the top 256K of sram plus sram 8 and 9 (scratch x and scratch y) - POWMAN_POWER_DOMAIN_SRAM_BANK0 = 1, ///< bank0 is bottom 256K of sSRAM - POWMAN_POWER_DOMAIN_XIP_CACHE = 2, ///< XIP cache is 2x8K instances - POWMAN_POWER_DOMAIN_SWITCHED_CORE = 3, ///< Switched core logic (processors, busfabric, peris etc) - POWMAN_POWER_DOMAIN_COUNT = 4, -}; - -typedef uint32_t powman_power_state; - -/*! \brief Get the current power state - * \ingroup hardware_powman - */ -powman_power_state powman_get_power_state(void); - -/*! \brief Set the power state - * \ingroup hardware_powman - * - * Check the desired state is valid. Powman will go to the state if it is valid and there are no pending power up requests. - * - * Note that if you are turning off the switched core then this function will never return as the processor will have - * been turned off at the end. - * - * \param state the power state to go to - * \returns PICO_OK if the state is valid. Misc PICO_ERRORs are returned if not - */ -int powman_set_power_state(powman_power_state state); - -#define POWMAN_POWER_STATE_NONE 0 - -/*! \brief Helper function modify a powman_power_state to turn a domain on - * \ingroup hardware_powman - * \param orig original state - * \param domain domain to turn on - */ -static inline powman_power_state powman_power_state_with_domain_on(powman_power_state orig, enum powman_power_domains domain) { - invalid_params_if(HARDWARE_POWMAN, domain >= POWMAN_POWER_DOMAIN_COUNT); - return orig | (1u << domain); -} - -/*! \brief Helper function modify a powman_power_state to turn a domain off - * \ingroup hardware_powman - * \param orig original state - * \param domain domain to turn off - */ -static inline powman_power_state powman_power_state_with_domain_off(powman_power_state orig, enum powman_power_domains domain) { - invalid_params_if(HARDWARE_POWMAN, domain >= POWMAN_POWER_DOMAIN_COUNT); - return orig &= ~(1u << domain); -} - -/*! \brief Helper function to check if a domain is on in a given powman_power_state - * \ingroup hardware_powman - * \param state powman_power_state - * \param domain domain to check is on - */ -static inline bool powman_power_state_is_domain_on(powman_power_state state, enum powman_power_domains domain) { - invalid_params_if(HARDWARE_POWMAN, domain >= POWMAN_POWER_DOMAIN_COUNT); - return state & (1u << domain); -} - -/*! \brief Wake up from an alarm at a given time - * \ingroup hardware_powman - * \param alarm_time_ms time to wake up in ms - */ -void powman_enable_alarm_wakeup_at_ms(uint64_t alarm_time_ms); - -/*! \brief Wake up from a gpio - * \ingroup hardware_powman - * \param gpio_wakeup_num hardware wakeup instance to use (0-3) - * \param gpio gpio to wake up from (0-47) - * \param edge true for edge sensitive, false for level sensitive - * \param high true for active high, false active low - */ -void powman_enable_gpio_wakeup(uint gpio_wakeup_num, uint32_t gpio, bool edge, bool high); - -/*! \brief Disable waking up from alarm - * \ingroup hardware_powman - */ -void powman_disable_alarm_wakeup(void); - -/*! \brief Disable wake up from a gpio - * \ingroup hardware_powman - * \param gpio_wakeup_num hardware wakeup instance to use (0-3) - */ -void powman_disable_gpio_wakeup(uint gpio_wakeup_num); - -/*! \brief Disable all wakeup sources - * \ingroup hardware_powman - */ -void powman_disable_all_wakeups(void); - -/*! \brief Configure sleep state and wakeup state - * \ingroup hardware_powman - * \param sleep_state power state powman will go to when sleeping, used to validate the wakeup state - * \param wakeup_state power state powman will go to when waking up. Note switched core and xip always power up. SRAM bank0 and bank1 can be left powered off - * \returns true if the state is valid, false if not - */ -bool powman_configure_wakeup_state(powman_power_state sleep_state, powman_power_state wakeup_state); - -/*! \brief Ignore wake up when the debugger is attached - * \ingroup hardware_powman - * - * Typically, when a debugger is attached it will assert the pwrupreq signal. OpenOCD does not clear this signal, even when you quit. - * This means once you have attached a debugger powman will never go to sleep. This function lets you ignore the debugger - * pwrupreq which means you can go to sleep with a debugger attached. The debugger will error out if you go to turn off the switch core with it attached, - * as the processors have been powered off. - * - * \param ignored should the debugger power up request be ignored - */ -static inline void powman_set_debug_power_request_ignored(bool ignored) { - if (ignored) - powman_set_bits(&powman_hw->dbg_pwrcfg, 1); - else - powman_clear_bits(&powman_hw->dbg_pwrcfg, 0); -} - -#endif \ No newline at end of file diff --git a/lib/main/pico-sdk/rp2_common/hardware_powman/powman.c b/lib/main/pico-sdk/rp2_common/hardware_powman/powman.c deleted file mode 100644 index b9c5564824..0000000000 --- a/lib/main/pico-sdk/rp2_common/hardware_powman/powman.c +++ /dev/null @@ -1,259 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include -#include - -#include "pico.h" - -#include "hardware/gpio.h" -#include "hardware/powman.h" - -#ifndef PICO_POWMAN_DEBUG -#define PICO_POWMAN_DEBUG 0 -#endif - -#if PICO_POWMAN_DEBUG -bool powman_debug_printf = false; -void powman_enable_debug_printf(void) { - powman_debug_printf = true; -} -#define powman_debug(format, args...) if (powman_debug_printf) printf(format, ## args) -#else -#define powman_debug(...) -#endif - -static inline void powman_write(volatile uint32_t *reg, uint32_t value) { - // Write needs a password in top 16 bits - invalid_params_if(HARDWARE_POWMAN, value >> 16); - *reg = POWMAN_PASSWORD_BITS | value; -} - -void powman_timer_set_ms(uint64_t time_ms) { - bool was_running = powman_timer_is_running(); - if (was_running) powman_timer_stop(); - powman_write(&powman_hw->set_time_15to0, time_ms & 0xffff); - powman_write(&powman_hw->set_time_31to16, (time_ms >> 16) & 0xffff); - powman_write(&powman_hw->set_time_47to32, (time_ms >> 32) & 0xffff); - powman_write(&powman_hw->set_time_63to48, (time_ms >> 48) & 0xffff); - if (was_running) powman_timer_start(); -} - -uint64_t powman_timer_get_ms(void) { - // Need to make sure that the upper 32 bits of the timer - // don't change, so read that first - uint32_t hi = powman_hw->read_time_upper; - uint32_t lo; - do { - // Read the lower 32 bits - lo = powman_hw->read_time_lower; - // Now read the upper 32 bits again and - // check that it hasn't incremented. If it has loop around - // and read the lower 32 bits again to get an accurate value - uint32_t next_hi = powman_hw->read_time_upper; - if (hi == next_hi) break; - hi = next_hi; - } while (true); - return ((uint64_t) hi << 32u) | lo; -} - -void powman_timer_set_1khz_tick_source_lposc(void) { - powman_timer_set_1khz_tick_source_lposc_with_hz(32768); -} - -void powman_timer_set_1khz_tick_source_lposc_with_hz(uint32_t lposc_freq_hz) { - bool was_running = powman_timer_is_running(); - if (was_running) powman_timer_stop(); - uint32_t lposc_freq_khz = lposc_freq_hz / 1000; - uint32_t lposc_freq_khz_frac16 = (lposc_freq_khz % 1000) * 65536 / 1000; - powman_write(&powman_hw->lposc_freq_khz_int, lposc_freq_khz); - powman_write(&powman_hw->lposc_freq_khz_frac, lposc_freq_khz_frac16); - powman_set_bits(&powman_hw->timer, POWMAN_TIMER_USE_LPOSC_BITS); - if (was_running) { - powman_timer_start(); - while(!(powman_hw->timer & POWMAN_TIMER_USING_LPOSC_BITS)); - } -} - -void powman_timer_set_1khz_tick_source_xosc(void) { - powman_timer_set_1khz_tick_source_xosc_with_hz(XOSC_HZ); -} - -void powman_timer_set_1khz_tick_source_xosc_with_hz(uint32_t xosc_freq_hz) { - bool was_running = powman_timer_is_running(); - if (was_running) powman_timer_stop(); - uint32_t xosc_freq_khz = xosc_freq_hz / 1000; - uint32_t xosc_freq_khz_frac16 = (xosc_freq_khz % 1000) * 65536 / 1000; - powman_write(&powman_hw->xosc_freq_khz_int, xosc_freq_khz); - powman_write(&powman_hw->xosc_freq_khz_frac, xosc_freq_khz_frac16); - powman_set_bits(&powman_hw->timer, POWMAN_TIMER_USE_XOSC_BITS); - if (was_running) { - powman_timer_start(); - while(!(powman_hw->timer & POWMAN_TIMER_USING_XOSC_BITS)); - } -} - -static void powman_timer_use_gpio(uint32_t gpio, uint32_t use, uint32_t using) { - bool was_running = powman_timer_is_running(); - if (was_running) powman_timer_stop(); - invalid_params_if(HARDWARE_POWMAN, !((gpio == 12) || (gpio == 14) || (gpio == 20) || (gpio == 22))); - gpio_set_input_enabled(gpio, true); - powman_write(&powman_hw->ext_time_ref, gpio); - powman_set_bits(&powman_hw->timer, use); - if (was_running) { - powman_timer_start(); - while(!(powman_hw->timer & using)); - } -} - -void powman_timer_set_1khz_tick_source_gpio(uint32_t gpio) { - // todo check if we're using the GPIO setup already? - powman_timer_use_gpio(gpio, POWMAN_TIMER_USE_GPIO_1KHZ_BITS, POWMAN_TIMER_USING_GPIO_1KHZ_BITS); -} - -void powman_timer_enable_gpio_1hz_sync(uint32_t gpio) { - // todo check if we're using the GPIO setup already? - powman_timer_use_gpio(gpio, POWMAN_TIMER_USE_GPIO_1HZ_BITS, POWMAN_TIMER_USING_GPIO_1HZ_BITS); -} - -void powman_timer_disable_gpio_1hz_sync(void) { - powman_clear_bits(&powman_hw->timer, POWMAN_TIMER_USE_GPIO_1HZ_BITS); -} - -powman_power_state powman_get_power_state(void) { - uint32_t state_reg = powman_hw->state & POWMAN_STATE_CURRENT_BITS; - // todo we should have hardware/regs/powman.h values for these - static_assert(POWMAN_POWER_DOMAIN_SRAM_BANK1 == 0, ""); - static_assert(POWMAN_POWER_DOMAIN_SRAM_BANK0 == 1, ""); - static_assert(POWMAN_POWER_DOMAIN_XIP_CACHE == 2, ""); - static_assert(POWMAN_POWER_DOMAIN_SWITCHED_CORE == 3, ""); - static_assert(POWMAN_STATE_CURRENT_BITS == 0xf, ""); - return (powman_power_state) state_reg; -} - -// TODO: Should this fail to go to sleep if there is no wakeup alarm -int powman_set_power_state(powman_power_state state) { - // Clear req ignored in case it has been set - powman_clear_bits(&powman_hw->state, POWMAN_STATE_REQ_IGNORED_BITS); - powman_debug("powman: Requesting state %x\n", state); - powman_write(&powman_hw->state, (~state << POWMAN_STATE_REQ_LSB) & POWMAN_STATE_REQ_BITS); - - // Has it been ignored? - if (powman_hw->state & POWMAN_STATE_REQ_IGNORED_BITS) { - powman_debug("State req ignored because of a pending pwrup req: %"PRIx32"\n", powman_hw->current_pwrup_req); - return PICO_ERROR_PRECONDITION_NOT_MET; - } - - bool state_valid = (powman_hw->state & POWMAN_STATE_BAD_SW_REQ_BITS) == 0; - if (!state_valid) { - powman_debug("powman: Requested state invalid\n"); - return PICO_ERROR_INVALID_ARG; - } else { - powman_debug("powman: Requested state valid\n"); - } - if (!powman_power_state_is_domain_on(state, POWMAN_POWER_DOMAIN_SWITCHED_CORE)) { - // If we are turning off switched core then POWMAN_STATE_WAITING_BITS will be - // set because we are waiting for proc to go to sleep, so return ok and then the proc - // can go to sleep - - // Note if the powerdown is being blocked by a pending pwrup request we will break out of this and return a failure - - // Clk pow is slow so can take a few clk_pow cycles for waiting to turn up - for (int i = 0; i < 100; i++) { - if (powman_hw->state & POWMAN_STATE_WAITING_BITS) { - return PICO_OK; - } - } - - // If it hasn't turned up then false - powman_debug("powman: STATE_WAITING hasn't turned up\n"); - return PICO_ERROR_TIMEOUT; - } - // Wait while the state is changing then return true as we will be in the new state - powman_debug("powman: waiting for state change\n"); - while(powman_hw->state & POWMAN_STATE_CHANGING_BITS) tight_loop_contents(); - powman_debug("powman: state changed to %x\n", state); - return PICO_OK; -} - -bool powman_configure_wakeup_state(powman_power_state sleep_state, powman_power_state wakeup_state) { - // When powman wakes up it can keep the state of the sram0 and sram1 banks. Note, it can't - // explicitly - bool valid = powman_power_state_is_domain_on(wakeup_state, POWMAN_POWER_DOMAIN_XIP_CACHE); - valid &= powman_power_state_is_domain_on(wakeup_state, POWMAN_POWER_DOMAIN_SWITCHED_CORE); - valid &= powman_power_state_is_domain_on(sleep_state, POWMAN_POWER_DOMAIN_SRAM_BANK0) == - powman_power_state_is_domain_on(wakeup_state, POWMAN_POWER_DOMAIN_SRAM_BANK0); - valid &= powman_power_state_is_domain_on(sleep_state, POWMAN_POWER_DOMAIN_SRAM_BANK1) == - powman_power_state_is_domain_on(wakeup_state, POWMAN_POWER_DOMAIN_SRAM_BANK1); - if (valid) { - powman_clear_bits(&powman_hw->seq_cfg, POWMAN_SEQ_CFG_HW_PWRUP_SRAM0_BITS | POWMAN_SEQ_CFG_HW_PWRUP_SRAM1_BITS); - uint32_t seq_cfg_set = 0; - if (!powman_power_state_is_domain_on(sleep_state, POWMAN_POWER_DOMAIN_SRAM_BANK0)) seq_cfg_set |= POWMAN_SEQ_CFG_HW_PWRUP_SRAM0_BITS; - if (!powman_power_state_is_domain_on(sleep_state, POWMAN_POWER_DOMAIN_SRAM_BANK1)) seq_cfg_set |= POWMAN_SEQ_CFG_HW_PWRUP_SRAM1_BITS; - powman_set_bits(&powman_hw->seq_cfg, seq_cfg_set); - } - return valid; -} - -void powman_timer_enable_alarm_at_ms(uint64_t alarm_time_ms) { - powman_set_bits(&powman_hw->inte, POWMAN_INTE_TIMER_BITS); - powman_clear_bits(&powman_hw->timer, POWMAN_TIMER_ALARM_ENAB_BITS); - // Alarm must be disabled to set the alarm time - powman_write(&powman_hw->alarm_time_15to0, alarm_time_ms & 0xffff); - powman_write(&powman_hw->alarm_time_31to16, (alarm_time_ms >> 16) & 0xffff); - powman_write(&powman_hw->alarm_time_47to32, (alarm_time_ms >> 32) & 0xffff); - powman_write(&powman_hw->alarm_time_63to48, (alarm_time_ms >> 48) & 0xffff); - powman_clear_alarm(); - // TODO: Assuming pwrup on alarm has no bad side effects if already powered up - powman_set_bits(&powman_hw->timer, POWMAN_TIMER_ALARM_ENAB_BITS); -} - -void powman_timer_disable_alarm(void) { - powman_clear_bits(&powman_hw->inte, POWMAN_INTE_TIMER_BITS); - powman_clear_bits(&powman_hw->timer, POWMAN_TIMER_ALARM_ENAB_BITS); -} - -void powman_enable_alarm_wakeup_at_ms(uint64_t alarm_time_ms) { - powman_timer_enable_alarm_at_ms(alarm_time_ms); - powman_set_bits(&powman_hw->timer, POWMAN_TIMER_PWRUP_ON_ALARM_BITS); -} - -void powman_disable_alarm_wakeup(void) { - powman_timer_disable_alarm(); - powman_clear_bits(&powman_hw->timer, POWMAN_TIMER_PWRUP_ON_ALARM_BITS); -} - -void powman_enable_gpio_wakeup(uint gpio_wakeup_num, uint32_t gpio, bool edge, bool high) { - invalid_params_if(HARDWARE_POWMAN, gpio_wakeup_num >= count_of(powman_hw->pwrup)); - - // Need to make sure pad is input enabled - gpio_set_input_enabled(gpio, true); - - // Set up gpio hardware for what we want - uint32_t pwrup = (edge ? POWMAN_PWRUP0_MODE_VALUE_EDGE : POWMAN_PWRUP0_MODE_VALUE_LEVEL) << POWMAN_PWRUP0_MODE_LSB; - pwrup |= (high ? POWMAN_PWRUP0_DIRECTION_BITS : 0); - pwrup |= gpio << POWMAN_PWRUP0_SOURCE_LSB; - powman_write(&powman_hw->pwrup[gpio_wakeup_num], pwrup); - - // Clear the status bit in case an edge is already latched - powman_clear_bits(&powman_hw->pwrup[gpio_wakeup_num], POWMAN_PWRUP0_STATUS_BITS); - - // Important to enable it separately to allow the gpio to change - powman_set_bits(&powman_hw->pwrup[gpio_wakeup_num], POWMAN_PWRUP0_ENABLE_BITS); -} - -void powman_disable_gpio_wakeup(uint gpio_wakeup_num) { - invalid_params_if(HARDWARE_POWMAN, gpio_wakeup_num >= count_of(powman_hw->pwrup)); - powman_clear_bits(&powman_hw->pwrup[gpio_wakeup_num], POWMAN_PWRUP0_ENABLE_BITS); -} - -void powman_disable_all_wakeups(void) { - for (uint i = 0; i < count_of(powman_hw->pwrup); i++) { - powman_disable_gpio_wakeup(i); - } - powman_disable_alarm_wakeup(); -} diff --git a/lib/main/pico-sdk/rp2_common/hardware_pwm/include/hardware/pwm.h b/lib/main/pico-sdk/rp2_common/hardware_pwm/include/hardware/pwm.h deleted file mode 100644 index d4da7e52b0..0000000000 --- a/lib/main/pico-sdk/rp2_common/hardware_pwm/include/hardware/pwm.h +++ /dev/null @@ -1,822 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _HARDWARE_PWM_H -#define _HARDWARE_PWM_H - -#include "pico.h" -#include "hardware/structs/pwm.h" -#include "hardware/regs/dreq.h" -#include "hardware/regs/intctrl.h" - -#ifdef __cplusplus -extern "C" { -#endif - -// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_HARDWARE_PWM, Enable/disable assertions in the hardware_pwm module, type=bool, default=0, group=hardware_pwm -#ifndef PARAM_ASSERTIONS_ENABLED_HARDWARE_PWM -#ifdef PARAM_ASSERTIONS_ENABLED_PWM // backwards compatibility with SDK < 2.0.0 -#define PARAM_ASSERTIONS_ENABLED_HARDWARE_PWM PARAM_ASSERTIONS_ENABLED_PWM -#else -#define PARAM_ASSERTIONS_ENABLED_HARDWARE_PWM 0 -#endif -#endif - -/** \file hardware/pwm.h - * \defgroup hardware_pwm hardware_pwm - * - * \brief Hardware Pulse Width Modulation (PWM) API - * - * The RP2040 PWM block has 8 identical slices, the RP2350 has 12. Each slice can drive two PWM output signals, or - * measure the frequency or duty cycle of an input signal. This gives a total of up to 16/24 controllable - * PWM outputs. All 30 GPIOs can be driven by the PWM block. - * - * The PWM hardware functions by continuously comparing the input value to a free-running counter. This produces a - * toggling output where the amount of time spent at the high output level is proportional to the input value. The fraction of - * time spent at the high signal level is known as the duty cycle of the signal. - * - * The default behaviour of a PWM slice is to count upward until the wrap value (\ref pwm_config_set_wrap) is reached, and then - * immediately wrap to 0. PWM slices also offer a phase-correct mode, where the counter starts to count downward after - * reaching TOP, until it reaches 0 again. - * - * \subsection pwm_example Example - * \addtogroup hardware_pwm - * \include hello_pwm.c - */ - -/** \brief PWM Divider mode settings - * \ingroup hardware_pwm - * - */ -enum pwm_clkdiv_mode -{ - PWM_DIV_FREE_RUNNING = 0, ///< Free-running counting at rate dictated by fractional divider - PWM_DIV_B_HIGH = 1, ///< Fractional divider is gated by the PWM B pin - PWM_DIV_B_RISING = 2, ///< Fractional divider advances with each rising edge of the PWM B pin - PWM_DIV_B_FALLING = 3 ///< Fractional divider advances with each falling edge of the PWM B pin -}; - -enum pwm_chan -{ - PWM_CHAN_A = 0, - PWM_CHAN_B = 1 -}; - -typedef struct { - uint32_t csr; - uint32_t div; - uint32_t top; -} pwm_config; - -/** - * \def PWM_DREQ_NUM(slice_num) - * \ingroup hardware_pwm - * \hideinitializer - * \brief Returns the \ref dreq_num_t used for pacing DMA transfers for a given PWM slice - * - * Note this macro is intended to resolve at compile time, and does no parameter checking - */ -#ifndef PWM_DREQ_NUM -static_assert(DREQ_PWM_WRAP1 == DREQ_PWM_WRAP0 + 1, ""); -static_assert(DREQ_PWM_WRAP7 == DREQ_PWM_WRAP0 + 7, ""); -#define PWM_DREQ_NUM(slice_num) (DREQ_PWM_WRAP0 + (slice_num)) -#endif - -/** - * \def PWM_GPIO_SLICE_NUM(gpio) - * \ingroup hardware_pwm - * \hideinitializer - * \brief Returns the PWM slice number for a given GPIO number - */ -#ifndef PWM_GPIO_SLICE_NUM -#define PWM_GPIO_SLICE_NUM(gpio) ({ \ - uint slice_num; \ - if ((gpio) < 32) { \ - slice_num = ((gpio) >> 1u) & 7u; \ - } else { \ - slice_num = 8u + (((gpio) >> 1u) & 3u); \ - } \ - slice_num; \ -}) -#endif - -static inline void check_slice_num_param(__unused uint slice_num) { - valid_params_if(HARDWARE_PWM, slice_num < NUM_PWM_SLICES); -} - -/** \brief Determine the PWM slice that is attached to the specified GPIO - * \ingroup hardware_pwm - * - * \return The PWM slice number that controls the specified GPIO. - */ -static inline uint pwm_gpio_to_slice_num(uint gpio) { - valid_params_if(HARDWARE_PWM, gpio < NUM_BANK0_GPIOS); - return PWM_GPIO_SLICE_NUM(gpio); -} - -/** \brief Determine the PWM channel that is attached to the specified GPIO. - * \ingroup hardware_pwm - * - * Each slice 0 to 7 has two channels, A and B. - * - * \return The PWM channel that controls the specified GPIO. - */ -static inline uint pwm_gpio_to_channel(uint gpio) { - valid_params_if(HARDWARE_PWM, gpio < NUM_BANK0_GPIOS); - return gpio & 1u; -} - -/** \brief Set phase correction in a PWM configuration - * \ingroup hardware_pwm - * - * \param c PWM configuration struct to modify - * \param phase_correct true to set phase correct modulation, false to set trailing edge - * - * Setting phase control to true means that instead of wrapping back to zero when the wrap point is reached, - * the PWM starts counting back down. The output frequency is halved when phase-correct mode is enabled. - */ -static inline void pwm_config_set_phase_correct(pwm_config *c, bool phase_correct) { - c->csr = (c->csr & ~PWM_CH0_CSR_PH_CORRECT_BITS) - | (bool_to_bit(phase_correct) << PWM_CH0_CSR_PH_CORRECT_LSB); -} - -/** \brief Set PWM clock divider in a PWM configuration - * \ingroup hardware_pwm - * - * \param c PWM configuration struct to modify - * \param div Value to divide counting rate by. Must be greater than or equal to 1. - * - * If the divide mode is free-running, the PWM counter runs at clk_sys / div. - * Otherwise, the divider reduces the rate of events seen on the B pin input (level or edge) - * before passing them on to the PWM counter. - */ -static inline void pwm_config_set_clkdiv(pwm_config *c, float div) { - valid_params_if(HARDWARE_PWM, div >= 1.f && div < 256.f); - c->div = (uint32_t)(div * (float)(1u << PWM_CH0_DIV_INT_LSB)); -} - -/** \brief Set PWM clock divider in a PWM configuration using an 8:4 fractional value - * \ingroup hardware_pwm - * - * \param c PWM configuration struct to modify - * \param integer 8 bit integer part of the clock divider. Must be greater than or equal to 1. - * \param fract 4 bit fractional part of the clock divider - * - * If the divide mode is free-running, the PWM counter runs at clk_sys / div. - * Otherwise, the divider reduces the rate of events seen on the B pin input (level or edge) - * before passing them on to the PWM counter. - */ -static inline void pwm_config_set_clkdiv_int_frac(pwm_config *c, uint8_t integer, uint8_t fract) { - valid_params_if(HARDWARE_PWM, integer >= 1); - valid_params_if(HARDWARE_PWM, fract < 16); - c->div = (((uint)integer) << PWM_CH0_DIV_INT_LSB) | (((uint)fract) << PWM_CH0_DIV_FRAC_LSB); -} - -/** \brief Set PWM clock divider in a PWM configuration - * \ingroup hardware_pwm - * - * \param c PWM configuration struct to modify - * \param div Integer value to reduce counting rate by. Must be greater than or equal to 1. - * - * If the divide mode is free-running, the PWM counter runs at clk_sys / div. - * Otherwise, the divider reduces the rate of events seen on the B pin input (level or edge) - * before passing them on to the PWM counter. - */ -static inline void pwm_config_set_clkdiv_int(pwm_config *c, uint div) { - valid_params_if(HARDWARE_PWM, div >= 1 && div < 256); - pwm_config_set_clkdiv_int_frac(c, (uint8_t)div, 0); -} - -/** \brief Set PWM counting mode in a PWM configuration - * \ingroup hardware_pwm - * - * \param c PWM configuration struct to modify - * \param mode PWM divide/count mode - * - * Configure which event gates the operation of the fractional divider. - * The default is always-on (free-running PWM). Can also be configured to count on - * high level, rising edge or falling edge of the B pin input. - */ -static inline void pwm_config_set_clkdiv_mode(pwm_config *c, enum pwm_clkdiv_mode mode) { - valid_params_if(HARDWARE_PWM, mode == PWM_DIV_FREE_RUNNING || - mode == PWM_DIV_B_RISING || - mode == PWM_DIV_B_HIGH || - mode == PWM_DIV_B_FALLING); - c->csr = (c->csr & ~PWM_CH0_CSR_DIVMODE_BITS) - | (((uint)mode) << PWM_CH0_CSR_DIVMODE_LSB); -} - -/** \brief Set output polarity in a PWM configuration - * \ingroup hardware_pwm - * - * \param c PWM configuration struct to modify - * \param a true to invert output A - * \param b true to invert output B - */ -static inline void pwm_config_set_output_polarity(pwm_config *c, bool a, bool b) { - c->csr = (c->csr & ~(PWM_CH0_CSR_A_INV_BITS | PWM_CH0_CSR_B_INV_BITS)) - | ((bool_to_bit(a) << PWM_CH0_CSR_A_INV_LSB) | (bool_to_bit(b) << PWM_CH0_CSR_B_INV_LSB)); -} - -/** \brief Set PWM counter wrap value in a PWM configuration - * \ingroup hardware_pwm - * - * Set the highest value the counter will reach before returning to 0. Also known as TOP. - * - * \param c PWM configuration struct to modify - * \param wrap Value to set wrap to - */ -static inline void pwm_config_set_wrap(pwm_config *c, uint16_t wrap) { - c->top = wrap; -} - -/** \brief Initialise a PWM with settings from a configuration object - * \ingroup hardware_pwm - * - * Use the \ref pwm_get_default_config() function to initialise a config structure, make changes as - * needed using the pwm_config_* functions, then call this function to set up the PWM. - * - * \param slice_num PWM slice number - * \param c The configuration to use - * \param start If true the PWM will be started running once configured. If false you will need to start - * manually using \ref pwm_set_enabled() or \ref pwm_set_mask_enabled() - */ -static inline void pwm_init(uint slice_num, pwm_config *c, bool start) { - check_slice_num_param(slice_num); - pwm_hw->slice[slice_num].csr = 0; - - pwm_hw->slice[slice_num].ctr = PWM_CH0_CTR_RESET; - pwm_hw->slice[slice_num].cc = PWM_CH0_CC_RESET; - pwm_hw->slice[slice_num].top = c->top; - pwm_hw->slice[slice_num].div = c->div; - pwm_hw->slice[slice_num].csr = c->csr | (bool_to_bit(start) << PWM_CH0_CSR_EN_LSB); -} - -/** \brief Get a set of default values for PWM configuration - * \ingroup hardware_pwm - * - * PWM config is free-running at system clock speed, no phase correction, wrapping at 0xffff, - * with standard polarities for channels A and B. - * - * \return Set of default values. - */ -static inline pwm_config pwm_get_default_config(void) { - pwm_config c = {0, 0, 0}; - pwm_config_set_phase_correct(&c, false); - pwm_config_set_clkdiv_int(&c, 1); - pwm_config_set_clkdiv_mode(&c, PWM_DIV_FREE_RUNNING); - pwm_config_set_output_polarity(&c, false, false); - pwm_config_set_wrap(&c, 0xffffu); - return c; -} - -/** \brief Set the current PWM counter wrap value - * \ingroup hardware_pwm - * - * Set the highest value the counter will reach before returning to 0. Also - * known as TOP. - * - * The counter wrap value is double-buffered in hardware. This means that, - * when the PWM is running, a write to the counter wrap value does not take - * effect until after the next time the PWM slice wraps (or, in phase-correct - * mode, the next time the slice reaches 0). If the PWM is not running, the - * write is latched in immediately. - * - * \param slice_num PWM slice number - * \param wrap Value to set wrap to - */ -static inline void pwm_set_wrap(uint slice_num, uint16_t wrap) { - check_slice_num_param(slice_num); - pwm_hw->slice[slice_num].top = wrap; -} - -/** \brief Set the current PWM counter compare value for one channel - * \ingroup hardware_pwm - * - * Set the value of the PWM counter compare value, for either channel A or channel B. - * - * The counter compare register is double-buffered in hardware. This means - * that, when the PWM is running, a write to the counter compare values does - * not take effect until the next time the PWM slice wraps (or, in - * phase-correct mode, the next time the slice reaches 0). If the PWM is not - * running, the write is latched in immediately. - * - * \param slice_num PWM slice number - * \param chan Which channel to update. 0 for A, 1 for B. - * \param level new level for the selected output - */ -static inline void pwm_set_chan_level(uint slice_num, uint chan, uint16_t level) { - check_slice_num_param(slice_num); - hw_write_masked( - &pwm_hw->slice[slice_num].cc, - ((uint)level) << (chan ? PWM_CH0_CC_B_LSB : PWM_CH0_CC_A_LSB), - chan ? PWM_CH0_CC_B_BITS : PWM_CH0_CC_A_BITS - ); -} - -/** \brief Set PWM counter compare values - * \ingroup hardware_pwm - * - * Set the value of the PWM counter compare values, A and B. - * - * The counter compare register is double-buffered in hardware. This means - * that, when the PWM is running, a write to the counter compare values does - * not take effect until the next time the PWM slice wraps (or, in - * phase-correct mode, the next time the slice reaches 0). If the PWM is not - * running, the write is latched in immediately. - * - * \param slice_num PWM slice number - * \param level_a Value to set compare A to. When the counter reaches this value the A output is deasserted - * \param level_b Value to set compare B to. When the counter reaches this value the B output is deasserted - */ -static inline void pwm_set_both_levels(uint slice_num, uint16_t level_a, uint16_t level_b) { - check_slice_num_param(slice_num); - pwm_hw->slice[slice_num].cc = (((uint)level_b) << PWM_CH0_CC_B_LSB) | (((uint)level_a) << PWM_CH0_CC_A_LSB); -} - -/** \brief Helper function to set the PWM level for the slice and channel associated with a GPIO. - * \ingroup hardware_pwm - * - * Look up the correct slice (0 to 7) and channel (A or B) for a given GPIO, and update the corresponding - * counter compare field. - * - * This PWM slice should already have been configured and set running. Also be careful of multiple GPIOs - * mapping to the same slice and channel (if GPIOs have a difference of 16). - * - * The counter compare register is double-buffered in hardware. This means - * that, when the PWM is running, a write to the counter compare values does - * not take effect until the next time the PWM slice wraps (or, in - * phase-correct mode, the next time the slice reaches 0). If the PWM is not - * running, the write is latched in immediately. - * - * \param gpio GPIO to set level of - * \param level PWM level for this GPIO - */ -static inline void pwm_set_gpio_level(uint gpio, uint16_t level) { - valid_params_if(HARDWARE_PWM, gpio < NUM_BANK0_GPIOS); - pwm_set_chan_level(pwm_gpio_to_slice_num(gpio), pwm_gpio_to_channel(gpio), level); -} - -/** \brief Get PWM counter - * \ingroup hardware_pwm - * - * Get current value of PWM counter - * - * \param slice_num PWM slice number - * \return Current value of the PWM counter - */ -static inline uint16_t pwm_get_counter(uint slice_num) { - check_slice_num_param(slice_num); - return (uint16_t)(pwm_hw->slice[slice_num].ctr); -} - -/** \brief Set PWM counter - * \ingroup hardware_pwm - * - * Set the value of the PWM counter - * - * \param slice_num PWM slice number - * \param c Value to set the PWM counter to - * - */ -static inline void pwm_set_counter(uint slice_num, uint16_t c) { - check_slice_num_param(slice_num); - pwm_hw->slice[slice_num].ctr = c; -} - -/** \brief Advance PWM count - * \ingroup hardware_pwm - * - * Advance the phase of a running the counter by 1 count. - * - * This function will return once the increment is complete. - * - * \param slice_num PWM slice number - */ -static inline void pwm_advance_count(uint slice_num) { - check_slice_num_param(slice_num); - hw_set_bits(&pwm_hw->slice[slice_num].csr, PWM_CH0_CSR_PH_ADV_BITS); - while (pwm_hw->slice[slice_num].csr & PWM_CH0_CSR_PH_ADV_BITS) { - tight_loop_contents(); - } -} - -/** \brief Retard PWM count - * \ingroup hardware_pwm - * - * Retard the phase of a running counter by 1 count - * - * This function will return once the retardation is complete. - * - * \param slice_num PWM slice number - */ -static inline void pwm_retard_count(uint slice_num) { - check_slice_num_param(slice_num); - hw_set_bits(&pwm_hw->slice[slice_num].csr, PWM_CH0_CSR_PH_RET_BITS); - while (pwm_hw->slice[slice_num].csr & PWM_CH0_CSR_PH_RET_BITS) { - tight_loop_contents(); - } -} - -/** \brief Set PWM clock divider using an 8:4 fractional value - * \ingroup hardware_pwm - * - * Set the clock divider. Counter increment will be on sysclock divided by this value, taking into account the gating. - * - * \param slice_num PWM slice number - * \param integer 8 bit integer part of the clock divider - * \param fract 4 bit fractional part of the clock divider - */ -static inline void pwm_set_clkdiv_int_frac(uint slice_num, uint8_t integer, uint8_t fract) { - check_slice_num_param(slice_num); - valid_params_if(HARDWARE_PWM, integer >= 1); - valid_params_if(HARDWARE_PWM, fract < 16); - pwm_hw->slice[slice_num].div = (((uint)integer) << PWM_CH0_DIV_INT_LSB) | (((uint)fract) << PWM_CH0_DIV_FRAC_LSB); -} - -/** \brief Set PWM clock divider - * \ingroup hardware_pwm - * - * Set the clock divider. Counter increment will be on sysclock divided by this value, taking into account the gating. - * - * \param slice_num PWM slice number - * \param divider Floating point clock divider, 1.f <= value < 256.f - */ -static inline void pwm_set_clkdiv(uint slice_num, float divider) { - check_slice_num_param(slice_num); - valid_params_if(HARDWARE_PWM, divider >= 1.f && divider < 256.f); - uint8_t i = (uint8_t)divider; - uint8_t f = (uint8_t)((divider - i) * (0x01 << 4)); - pwm_set_clkdiv_int_frac(slice_num, i, f); -} - -/** \brief Set PWM output polarity - * \ingroup hardware_pwm - * - * \param slice_num PWM slice number - * \param a true to invert output A - * \param b true to invert output B - */ -static inline void pwm_set_output_polarity(uint slice_num, bool a, bool b) { - check_slice_num_param(slice_num); - hw_write_masked(&pwm_hw->slice[slice_num].csr, bool_to_bit(a) << PWM_CH0_CSR_A_INV_LSB | bool_to_bit(b) << PWM_CH0_CSR_B_INV_LSB, - PWM_CH0_CSR_A_INV_BITS | PWM_CH0_CSR_B_INV_BITS); -} - - -/** \brief Set PWM divider mode - * \ingroup hardware_pwm - * - * \param slice_num PWM slice number - * \param mode Required divider mode - */ -static inline void pwm_set_clkdiv_mode(uint slice_num, enum pwm_clkdiv_mode mode) { - check_slice_num_param(slice_num); - valid_params_if(HARDWARE_PWM, mode == PWM_DIV_FREE_RUNNING || - mode == PWM_DIV_B_RISING || - mode == PWM_DIV_B_HIGH || - mode == PWM_DIV_B_FALLING); - hw_write_masked(&pwm_hw->slice[slice_num].csr, ((uint)mode) << PWM_CH0_CSR_DIVMODE_LSB, PWM_CH0_CSR_DIVMODE_BITS); -} - -/** \brief Set PWM phase correct on/off - * \ingroup hardware_pwm - * - * \param slice_num PWM slice number - * \param phase_correct true to set phase correct modulation, false to set trailing edge - * - * Setting phase control to true means that instead of wrapping back to zero when the wrap point is reached, - * the PWM starts counting back down. The output frequency is halved when phase-correct mode is enabled. - */ -static inline void pwm_set_phase_correct(uint slice_num, bool phase_correct) { - check_slice_num_param(slice_num); - hw_write_masked(&pwm_hw->slice[slice_num].csr, bool_to_bit(phase_correct) << PWM_CH0_CSR_PH_CORRECT_LSB, PWM_CH0_CSR_PH_CORRECT_BITS); -} - -/** \brief Enable/Disable PWM - * \ingroup hardware_pwm - * - * When a PWM is disabled, it halts its counter, and the output pins are left - * high or low depending on exactly when the counter is halted. When - * re-enabled the PWM resumes immediately from where it left off. - * - * If the PWM's output pins need to be low when halted: - * - * - The counter compare can be set to zero whilst the PWM is enabled, and - * then the PWM disabled once both pins are seen to be low - * - * - The GPIO output overrides can be used to force the actual pins low - * - * - The PWM can be run for one cycle (i.e. enabled then immediately disabled) - * with a TOP of 0, count of 0 and counter compare of 0, to force the pins - * low when the PWM has already been halted. The same method can be used - * with a counter compare value of 1 to force a pin high. - * - * Note that, when disabled, the PWM can still be advanced one count at a time - * by pulsing the PH_ADV bit in its CSR. The output pins transition as though - * the PWM were enabled. - * - * \param slice_num PWM slice number - * \param enabled true to enable the specified PWM, false to disable. - */ -static inline void pwm_set_enabled(uint slice_num, bool enabled) { - check_slice_num_param(slice_num); - hw_write_masked(&pwm_hw->slice[slice_num].csr, bool_to_bit(enabled) << PWM_CH0_CSR_EN_LSB, PWM_CH0_CSR_EN_BITS); -} - -/** \brief Enable/Disable multiple PWM slices simultaneously - * \ingroup hardware_pwm - * - * \param mask Bitmap of PWMs to enable/disable. Bits 0 to 7 enable slices 0-7 respectively - */ -static inline void pwm_set_mask_enabled(uint32_t mask) { - pwm_hw->en = mask; -} - -/** - * \def PWM_DEFAULT_IRQ_NUM() - * \ingroup hardware_pwm - * \hideinitializer - * \brief Returns the \ref irq_num_t for the default PWM IRQ. - * - * \if rp2040_specific - * On RP2040, there is only one PWM irq: PWM_IRQ_WRAP - * \endif - * - * \if rp2350_specific - * On RP2350 this returns to PWM_IRQ_WRAP0 - * \endif - * - * Note this macro is intended to resolve at compile time, and does no parameter checking - */ -#ifndef PWM_DEFAULT_IRQ_NUM -#if PICO_RP2040 -#define PWM_DEFAULT_IRQ_NUM() PWM_IRQ_WRAP -#else -#define PWM_DEFAULT_IRQ_NUM() PWM_IRQ_WRAP_0 -// backwards compatibility with RP2040 -#define PWM_IRQ_WRAP PWM_IRQ_WRAP_0 -#define isr_pwm_wrap isr_pwm_wrap_0 -#endif -#endif - -/*! \brief Enable PWM instance interrupt via the default PWM IRQ (PWM_IRQ_WRAP_0 on RP2350) - * \ingroup hardware_pwm - * - * Used to enable a single PWM instance interrupt. - * - * Note there is only one PWM_IRQ_WRAP on RP2040. - * - * \param slice_num PWM block to enable/disable - * \param enabled true to enable, false to disable - */ -static inline void pwm_set_irq_enabled(uint slice_num, bool enabled) { - check_slice_num_param(slice_num); - if (enabled) { - hw_set_bits(&pwm_hw->inte, 1u << slice_num); - } else { - hw_clear_bits(&pwm_hw->inte, 1u << slice_num); - } -} - -/*! \brief Enable PWM instance interrupt via PWM_IRQ_WRAP_0 - * \ingroup hardware_pwm - * - * Used to enable a single PWM instance interrupt. - * - * \param slice_num PWM block to enable/disable - * \param enabled true to enable, false to disable - */ -static inline void pwm_set_irq0_enabled(uint slice_num, bool enabled) { - // irq0 always corresponds to the default IRQ - pwm_set_irq_enabled(slice_num, enabled); -} - -#if NUM_PWM_IRQS > 1 -/*! \brief Enable PWM instance interrupt via PWM_IRQ_WRAP_1 - * \ingroup hardware_pwm - * - * Used to enable a single PWM instance interrupt. - * - * \param slice_num PWM block to enable/disable - * \param enabled true to enable, false to disable - */ -static inline void pwm_set_irq1_enabled(uint slice_num, bool enabled) { - check_slice_num_param(slice_num); - if (enabled) { - hw_set_bits(&pwm_hw->inte1, 1u << slice_num); - } else { - hw_clear_bits(&pwm_hw->inte1, 1u << slice_num); - } -} -#endif - -/*! \brief Enable PWM instance interrupt via either PWM_IRQ_WRAP_0 or PWM_IRQ_WRAP_1 - * \ingroup hardware_pwm - * - * Used to enable a single PWM instance interrupt. - * - * Note there is only one PWM_IRQ_WRAP on RP2040. - * - * \param irq_index the IRQ index; either 0 or 1 for PWM_IRQ_WRAP_0 or PWM_IRQ_WRAP_1 - * \param slice_num PWM block to enable/disable - * \param enabled true to enable, false to disable - */ -static inline void pwm_irqn_set_slice_enabled(uint irq_index, uint slice_num, bool enabled) { - check_slice_num_param(slice_num); - invalid_params_if(HARDWARE_PWM, irq_index >= NUM_PWM_IRQS); - check_slice_num_param(slice_num); - if (enabled) { - hw_set_bits(&pwm_hw->irq_ctrl[irq_index].inte, 1u << slice_num); - } else { - hw_clear_bits(&pwm_hw->irq_ctrl[irq_index].inte, 1u << slice_num); - } -} - -/*! \brief Enable multiple PWM instance interrupts via the default PWM IRQ (PWM_IRQ_WRAP_0 on RP2350) - * \ingroup hardware_pwm - * - * Use this to enable multiple PWM interrupts at once. - * - * Note there is only one PWM_IRQ_WRAP on RP2040. - * - * \param slice_mask Bitmask of all the blocks to enable/disable. Channel 0 = bit 0, channel 1 = bit 1 etc. - * \param enabled true to enable, false to disable - */ -static inline void pwm_set_irq_mask_enabled(uint32_t slice_mask, bool enabled) { - valid_params_if(HARDWARE_PWM, slice_mask < 256); -#if PICO_RP2040 - if (enabled) { - hw_set_bits(&pwm_hw->inte, slice_mask); - } else { - hw_clear_bits(&pwm_hw->inte, slice_mask); - } -#else - static_assert(PWM_IRQ_WRAP_1 == PWM_IRQ_WRAP_0 + 1, ""); - uint irq_index = PWM_DEFAULT_IRQ_NUM() - PWM_IRQ_WRAP_0; - if (enabled) { - hw_set_bits(&pwm_hw->irq_ctrl[irq_index].inte, slice_mask); - } else { - hw_clear_bits(&pwm_hw->irq_ctrl[irq_index].inte, slice_mask); - } -#endif -} - -/*! \brief Enable multiple PWM instance interrupts via PWM_IRQ_WRAP_0 - * \ingroup hardware_pwm - * - * Use this to enable multiple PWM interrupts at once. - * - * \param slice_mask Bitmask of all the blocks to enable/disable. Channel 0 = bit 0, channel 1 = bit 1 etc. - * \param enabled true to enable, false to disable - */ -static inline void pwm_set_irq0_mask_enabled(uint32_t slice_mask, bool enabled) { - // default irq is irq0 - pwm_set_irq_mask_enabled(slice_mask, enabled); -} - -#if NUM_PWM_IRQS > 1 -/*! \brief Enable multiple PWM instance interrupts via PWM_IRQ_WRAP_1 - * \ingroup hardware_pwm - * - * Use this to enable multiple PWM interrupts at once. - * - * \param slice_mask Bitmask of all the blocks to enable/disable. Channel 0 = bit 0, channel 1 = bit 1 etc. - * \param enabled true to enable, false to disable - */ -static inline void pwm_set_irq1_mask_enabled(uint32_t slice_mask, bool enabled) { - if (enabled) { - hw_set_bits(&pwm_hw->inte1, slice_mask); - } else { - hw_clear_bits(&pwm_hw->inte1, slice_mask); - } -} -#endif - -/*! \brief Enable PWM instance interrupts via either PWM_IRQ_WRAP_0 or PWM_IRQ_WRAP_1 -* \ingroup hardware_pwm -* -* Used to enable a single PWM instance interrupt. -* -* Note there is only one PWM_IRQ_WRAP on RP2040. -* -* \param irq_index the IRQ index; either 0 or 1 for PWM_IRQ_WRAP_0 or PWM_IRQ_WRAP_1 -* \param slice_mask Bitmask of all the blocks to enable/disable. Channel 0 = bit 0, channel 1 = bit 1 etc. -* \param enabled true to enable, false to disable -*/ -static inline void pwm_irqn_set_slice_mask_enabled(uint irq_index, uint slice_mask, bool enabled) { - invalid_params_if(HARDWARE_PWM, irq_index >= NUM_PWM_IRQS); - if (enabled) { - hw_set_bits(&pwm_hw->irq_ctrl[irq_index].inte, slice_mask); - } else { - hw_clear_bits(&pwm_hw->irq_ctrl[irq_index].inte, slice_mask); - } -} - -/*! \brief Clear a single PWM channel interrupt - * \ingroup hardware_pwm - * - * \param slice_num PWM slice number - */ -static inline void pwm_clear_irq(uint slice_num) { - pwm_hw->intr = 1u << slice_num; -} - -/*! \brief Get PWM interrupt status, raw for the default PWM IRQ (PWM_IRQ_WRAP_0 on RP2350) - * \ingroup hardware_pwm - * - * \return Bitmask of all PWM interrupts currently set - */ -static inline uint32_t pwm_get_irq_status_mask(void) { - return pwm_hw->ints; -} - -/*! \brief Get PWM interrupt status, raw for the PWM_IRQ_WRAP_0 - * \ingroup hardware_pwm - * - * \return Bitmask of all PWM interrupts currently set - */ -static inline uint32_t pwm_get_irq0_status_mask(void) { - return pwm_get_irq_status_mask(); -} - -#if NUM_PWM_IRQS > 1 -/*! \brief Get PWM interrupt status, raw for the PWM_IRQ_WRAP_1 - * \ingroup hardware_pwm - * - * \return Bitmask of all PWM interrupts currently set - */ -static inline uint32_t pwm_get_irq1_status_mask(void) { - return pwm_hw->ints1; -} -#endif - -/*! \brief Get PWM interrupt status, raw for either PWM_IRQ_WRAP_0 or PWM_IRQ_WRAP_1 - * \ingroup hardware_pwm - * -* \param irq_index the IRQ index; either 0 or 1 for PWM_IRQ_WRAP_0 or PWM_IRQ_WRAP_1 - * \return Bitmask of all PWM interrupts currently set - */ -static inline uint32_t pwm_irqn_get_status_mask(uint irq_index) { - invalid_params_if(HARDWARE_PWM, irq_index >= NUM_DMA_IRQS); - return pwm_hw->irq_ctrl[irq_index].ints; -} - -/*! \brief Force PWM interrupt for the default PWM IRQ (PWM_IRQ_WRAP_0 on RP2350) - * \ingroup hardware_pwm - * - * \param slice_num PWM slice number - */ -static inline void pwm_force_irq(uint slice_num) { - pwm_hw->intf = 1u << slice_num; -} - -/*! \brief Force PWM interrupt via PWM_IRQ_WRAP_0 - * \ingroup hardware_pwm - * - * \param slice_num PWM slice number - */ -static inline void pwm_force_irq0(uint slice_num) { - pwm_force_irq(slice_num); -} - -#if NUM_PWM_IRQS > 1 -/*! \brief Force PWM interrupt via PWM_IRQ_WRAP_0 - * \ingroup hardware_pwm - * - * \param slice_num PWM slice number - */ -static inline void pwm_force_irq1(uint slice_num) { - pwm_hw->intf1 = 1u << slice_num; -} -#endif - -/*! \brief Force PWM interrupt via PWM_IRQ_WRAP_0 or PWM_IRQ_WRAP_1 - * \ingroup hardware_pwm - * - * \param irq_index the IRQ index; either 0 or 1 for PWM_IRQ_WRAP_0 or PWM_IRQ_WRAP_1 - * \param slice_num PWM slice number - */ -static inline void pwm_irqn_force(uint irq_index, uint slice_num) { - invalid_params_if(HARDWARE_PWM, irq_index >= NUM_PWM_IRQS); - pwm_hw->irq_ctrl[irq_index].intf = 1u << slice_num; -} - -/*! \brief Return the DREQ to use for pacing transfers to a particular PWM slice - * \ingroup hardware_pwm - * - * \param slice_num PWM slice number - */ -static inline uint pwm_get_dreq(uint slice_num) { - check_slice_num_param(slice_num); - return PWM_DREQ_NUM(slice_num); -} - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/lib/main/pico-sdk/rp2_common/hardware_rcp/include/hardware/rcp.h b/lib/main/pico-sdk/rp2_common/hardware_rcp/include/hardware/rcp.h deleted file mode 100644 index b75f182d96..0000000000 --- a/lib/main/pico-sdk/rp2_common/hardware_rcp/include/hardware/rcp.h +++ /dev/null @@ -1,1005 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _PICO_RCP_H -#define _PICO_RCP_H - -#include "pico.h" - -/** \file hardware/rcp.h - * \defgroup hardware_rcp hardware_rcp - * \brief Inline functions and assembly macros for the Redundancy Coprocessor - */ - -// ---------------------------------------------------------------------------- -// RCP instructions (this header is Arm-only) -#if defined(PICO_RP2350) && !defined(__riscv) - -#define RCP_MASK_TRUE _u(0xa500a500) -#define RCP_MASK_FALSE _u(0x00c300c3) -#define RCP_MASK_INTXOR _u(0x96009600) - -// ---------------------------------------------------------------------------- -// Macros and inline functions for use in C files -#ifndef __ASSEMBLER__ - -#define __rcpinline __force_inline - -#ifdef __cplusplus -extern "C" { -#endif - -#ifndef __riscv // should never do an rcp_asm in risc-v code -#if __ARM_ARCH_8M_MAIN__ -#define rcp_asm pico_default_asm_volatile -#elif __ARM_ARCH_8M_BASE__ -#define rcp_asm(...) ({pico_default_asm_volatile(".cpu cortex-m33\n" __VA_ARGS__); pico_default_asm_volatile(".cpu cortex-m23"); }) -#elif __ARM_ARCH_6M__ -#define rcp_asm(...) ({pico_default_asm_volatile(".cpu cortex-m33\n" __VA_ARGS__); pico_default_asm_volatile(".cpu cortex-m0plus"); }) -#else -#error unknown ARM architecture -#endif - -// Each macro has a default version (e.g. rcp_salt_core0) and a no-delay version -// (e.g. rcp_salt_core0_nodelay). The default version adds an up to 127-cycle -// pseudorandom delay on each coprocessor instruction, whereas the no-delay version -// does not have this delay. The difference in the generated code is whether an MCR -// (e.g.) or MCR2 opcode is emitted. - -// ---------------------------------------------------------------------------- -// RCP Canary instructions - -// Initialise 64-bit salt value for core 0 -static __rcpinline void rcp_salt_core0(uint64_t salt) { - rcp_asm ( - "mcrr p7, #8, %0, %1, c0\n" - : : "r" (salt & 0xffffffffu), "r" (salt >> 32) - ); -} - -static __rcpinline void rcp_salt_core0_nodelay(uint64_t salt) { - rcp_asm ( - "mcrr2 p7, #8, %0, %1, c0\n" - : : "r" (salt & 0xffffffffu), "r" (salt >> 32) - ); -} - -// Initialise 64-bit salt value for core 1 -static __rcpinline void rcp_salt_core1(uint64_t salt) { - rcp_asm ( - "mcrr p7, #8, %0, %1, c1\n" - : : "r" (salt & 0xffffffffu), "r" (salt >> 32) - ); -} - -static __rcpinline void rcp_salt_core1_nodelay(uint64_t salt) { - rcp_asm ( - "mcrr2 p7, #8, %0, %1, c1\n" - : : "r" (salt & 0xffffffffu), "r" (salt >> 32) - ); -} - -// Get a 32-bit canary value. `tag` must be a constant expression. -#define rcp_canary_get(tag) ({ \ - uint32_t __canary_u32; \ - rcp_asm ( \ - "mrc p7, #0, %0, c%c1, c%c2, #1\n" \ - : "=r" (__canary_u32) \ - : "i" ((tag >> 4) & 0xf), "i" (tag & 0xf) \ - ); \ - __canary_u32; \ -}) - -#define rcp_canary_get_nodelay(tag) ({ \ - uint32_t __canary_u32; \ - rcp_asm ( \ - "mrc2 p7, #0, %0, c%c1, c%c2, #1\n" \ - : "=r" (__canary_u32) \ - : "i" (((tag) >> 4) & 0xf), "i" ((tag) & 0xf) \ - ); \ - __canary_u32; \ -}) - -// Assert that canary matches result of rcp_canary_get with the same tags: -#define rcp_canary_check(tag, canary) ({ \ - rcp_asm ( \ - "mcr p7, #0, %0, c%c1, c%c2, #1\n" \ - : : "r" (canary), \ - "i" (((tag) >> 4) & 0xf), "i" ((tag) & 0xf) \ - ); \ -}) - -#define rcp_canary_check_nodelay(tag, canary) ({ \ - rcp_asm ( \ - "mcr2 p7, #0, %0, c%c1, c%c2, #1\n" \ - : : "r" (canary), \ - "i" (((tag) >> 4) & 0xf), "i" ((tag) & 0xf) \ - ); \ -}) - -// Return true/false bit pattern for whether the salt for this core has been -// initialised. (Invoking with Rt=0xf will set the Arm N flag if initialised.) -// If the salt has not been initialised then any operation other than -// initialising the salt or checking the canary status is a hard error. -static __rcpinline uint32_t rcp_canary_status(void) { - uint32_t ret; - rcp_asm ("mrc p7, #1, %0, c0, c0, #0\n" : "=r" (ret)); - return ret; -} - -static __rcpinline uint32_t rcp_canary_status_nodelay(void) { - uint32_t ret; - rcp_asm ("mrc2 p7, #1, %0, c0, c0, #0\n" : "=r" (ret)); - return ret; -} - -// ---------------------------------------------------------------------------- -// RCP Boolean instructions - -// Assert b is a valid boolean (0xa500a500u or 0x00c300c3u) -static __rcpinline void rcp_bvalid(uint32_t b) { - rcp_asm ("mcr p7, #1, %0, c0, c0, #0\n" : : "r" (b)); -} - -static __rcpinline void rcp_bvalid_nodelay(uint32_t b) { - rcp_asm ("mcr2 p7, #1, %0, c0, c0, #0\n" : : "r" (b)); -} - -// Assert b is true (0xa500a500u) -static __rcpinline void rcp_btrue(uint32_t b) { - rcp_asm ("mcr p7, #2, %0, c0, c0, #0\n" : : "r" (b)); -} - -static __rcpinline void rcp_btrue_nodelay(uint32_t b) { - rcp_asm ("mcr2 p7, #2, %0, c0, c0, #0\n" : : "r" (b)); -} - -// Assert b is false (0x00c300c3u) -static __rcpinline void rcp_bfalse(uint32_t b) { - rcp_asm ("mcr p7, #3, %0, c0, c0, #1\n" : : "r" (b)); -} - -static __rcpinline void rcp_bfalse_nodelay(uint32_t b) { - rcp_asm ("mcr2 p7, #3, %0, c0, c0, #1\n" : : "r" (b)); -} - -// Assert b0 and b1 are both valid booleans -static __rcpinline void rcp_b2valid(uint32_t b0, uint32_t b1) { - rcp_asm ("mcrr p7, #0, %0, %1, c8\n" : : "r" (b0), "r" (b1)); -} - -static __rcpinline void rcp_b2valid_nodelay(uint32_t b0, uint32_t b1) { - rcp_asm ("mcrr2 p7, #0, %0, %1, c8\n" : : "r" (b0), "r" (b1)); -} - -// Assert b0 and b1 are both true -static __rcpinline void rcp_b2and(uint32_t b0, uint32_t b1) { - rcp_asm ("mcrr p7, #1, %0, %1, c0\n" : : "r" (b0), "r" (b1)); -} - -static __rcpinline void rcp_b2and_nodelay(uint32_t b0, uint32_t b1) { - rcp_asm ("mcrr2 p7, #1, %0, %1, c0\n" : : "r" (b0), "r" (b1)); -} - -// Assert b0 and b1 are valid, and at least one is true -static __rcpinline void rcp_b2or(uint32_t b0, uint32_t b1) { - rcp_asm ("mcrr p7, #2, %0, %1, c0\n" : : "r" (b0), "r" (b1)); -} - -static __rcpinline void rcp_b2or_nodelay(uint32_t b0, uint32_t b1) { - rcp_asm ("mcrr2 p7, #2, %0, %1, c0\n" : : "r" (b0), "r" (b1)); -} - -// Assert (b ^ mask) is a valid boolean -static __rcpinline void rcp_bxorvalid(uint32_t b, uint32_t mask) { - rcp_asm ("mcrr p7, #3, %0, %1, c8\n" : : "r" (b), "r" (mask)); -} - -static __rcpinline void rcp_bxorvalid_nodelay(uint32_t b, uint32_t mask) { - rcp_asm ("mcrr2 p7, #3, %0, %1, c8\n" : : "r" (b), "r" (mask)); -} - -// Assert (b ^ mask) is true -static __rcpinline void rcp_bxortrue(uint32_t b, uint32_t mask) { - rcp_asm ("mcrr p7, #4, %0, %1, c0\n" : : "r" (b), "r" (mask)); -} - -static __rcpinline void rcp_bxortrue_nodelay(uint32_t b, uint32_t mask) { - rcp_asm ("mcrr2 p7, #4, %0, %1, c0\n" : : "r" (b), "r" (mask)); -} - -// Assert (b ^ mask) is false -static __rcpinline void rcp_bxorfalse(uint32_t b, uint32_t mask) { - rcp_asm ("mcrr p7, #5, %0, %1, c8\n" : : "r" (b), "r" (mask)); -} - -static __rcpinline void rcp_bxorfalse_nodelay(uint32_t b, uint32_t mask) { - rcp_asm ("mcrr2 p7, #5, %0, %1, c8\n" : : "r" (b), "r" (mask)); -} - -// ---------------------------------------------------------------------------- -// RCP Integer instructions - -// Assert (x ^ parity) == 0x96009600u -static __rcpinline void rcp_ivalid(uint32_t x, uint32_t parity) { - rcp_asm ("mcrr p7, #6, %0, %1, c8\n" : : "r" (x), "r" (parity)); -} - -static __rcpinline void rcp_ivalid_nodelay(uint32_t x, uint32_t parity) { - rcp_asm ("mcrr2 p7, #6, %0, %1, c8\n" : : "r" (x), "r" (parity)); -} - -// Assert x == y -static __rcpinline void rcp_iequal(uint32_t x, uint32_t y) { - rcp_asm ("mcrr p7, #7, %0, %1, c0\n" : : "r" (x), "r" (y)); -} - -static __rcpinline void rcp_iequal_nodelay(uint32_t x, uint32_t y) { - rcp_asm ("mcrr2 p7, #7, %0, %1, c0\n" : : "r" (x), "r" (y)); -} - -// ---------------------------------------------------------------------------- -// RCP Random instructions - -// Return a random 8-bit value generated from the upper 24 bits of the 64-bit -// salt value. This is the same PRNG used for random delay values. -static __rcpinline uint8_t rcp_random_byte(void) { - uint8_t ret; - rcp_asm ("mrc2 p7, #2, %0, c0, c0, #0\n" : "=r" (ret)); - return ret; -} - -// Note neither version of this has delay, since the PRNG for the random delay -// is the same as the one read by this MRC instruction (and it's only stepped -// once). -static __rcpinline uint8_t rcp_random_byte_nodelay(void) { - uint8_t ret; - rcp_asm ("mrc2 p7, #2, %0, c0, c0, #0\n" : "=r" (ret)); - return ret; -} - -// ---------------------------------------------------------------------------- -// RCP Sequence count instructions - -// Directly write value cnt to the sequence counter. -// cnt must be a constant expression. -#define rcp_count_set(cnt) rcp_asm ( \ - "mcr p7, #4, r0, c%c0, c%c1, #0\n" \ - : : "i"(((cnt) >> 4) & 0xf), "i"((cnt) & 0xf) \ -); - -#define rcp_count_set_nodelay(cnt) rcp_asm ( \ - "mcr2 p7, #4, r0, c%c0, c%c1, #0\n" \ - : : "i"(((cnt) >> 4) & 0xf), "i"((cnt) & 0xf) \ -); - -// Check value cnt against the sequence counter, then increment the counter. -// cnt must be a constant expression. -#define rcp_count_check(cnt) rcp_asm ( \ - "mcr p7, #5, r0, c%c0, c%c1, #1\n" \ - : : "i"(((cnt) >> 4) & 0xf), "i"((cnt) & 0xf) \ -); - -#define rcp_count_check_nodelay(cnt) rcp_asm ( \ - "mcr2 p7, #5, r0, c%c0, c%c1, #1\n" \ - : : "i"(((cnt) >> 4) & 0xf), "i"((cnt) & 0xf) \ -); - -// ---------------------------------------------------------------------------- -// RCP Panic instructions - -// Stall the coprocessor port. If the coprocessor access goes away, assert NMI - -static __rcpinline __attribute__((noreturn)) void rcp_panic(void) { - rcp_asm("cdp p7, #0, c0, c0, c0, #1"); - __builtin_unreachable(); -} - -// There is no nodelay version. - -#endif // !__riscv -// ---------------------------------------------------------------------------- -// GAS macros for RCP instructions, for direct use in ASM files -#else // __ASSEMBLER__ -#ifndef __riscv - -// Assert b is a valid boolean (0xa500a500u or 0x00c300c3u) -.macro rcp_bvalid r - mcr p7, #1, \r , c0, c0, #0 -.endm - -.macro rcp_bvalid_nodelay r - mcr2 p7, #1, \r , c0, c0, #0 -.endm - -// Assert b is true (0xa500a500u) -.macro rcp_btrue r - mcr p7, #2, \r , c0, c0, #0 -.endm - -.macro rcp_btrue_nodelay r - mcr2 p7, #2, \r , c0, c0, #0 -.endm - -// Assert b is false (0x00c300c3u) -.macro rcp_bfalse r - mcr p7, #3, \r , c0, c0, #1 -.endm - -.macro rcp_bfalse_nodelay r - mcr2 p7, #3, \r , c0, c0, #1 -.endm - -// Assert b0 and b1 are both valid booleans -.macro rcp_b2valid b0, b1 - mcrr p7, #0, \b0 , \b1 , c8 -.endm - -.macro rcp_b2valid_nodelay b0, b1 - mcrr2 p7, #0, \b0 , \b1 , c8 -.endm - -// Assert b0 and b1 are both true -.macro rcp_b2and b0, b1 - mcrr p7, #1, \b0 , \b1 , c0 -.endm - -.macro rcp_b2and_nodelay b0, b1 - mcrr2 p7, #1, \b0 , \b1 , c0 -.endm - -// Assert b0 and b1 are valid, and at least one is true -.macro rcp_b2or b0, b1 - mcrr p7, #2, \b0 , \b1 , c0 -.endm - -.macro rcp_b2or_nodelay b0, b1 - mcrr2 p7, #2, \b0 , \b1 , c0 -.endm - -// Assert (b ^ mask) is a valid boolean -.macro rcp_bxorvalid b, mask - mcrr p7, #3, \b , \mask , c8 -.endm - -.macro rcp_bxorvalid_nodelay b, mask - mcrr2 p7, #3, \b , \mask , c8 -.endm - -// Assert (b ^ mask) is true -.macro rcp_bxortrue b, mask - mcrr p7, #4, \b , \mask , c0 -.endm - -.macro rcp_bxortrue_nodelay b, mask - mcrr2 p7, #4, \b , \mask , c0 -.endm - -// Assert (b ^ mask) is false -.macro rcp_bxorfalse b, mask - mcrr p7, #5, \b , \mask , c8 -.endm - -.macro rcp_bxorfalse_nodelay b, mask - mcrr2 p7, #5, \b , \mask , c8 -.endm - -// Assert (x ^ parity) == 0x96009600u -.macro rcp_ivalid x, parity - mcrr p7, #6, \x , \parity , c8 -.endm - -.macro rcp_ivalid_nodelay x, parity - mcrr2 p7, #6, \x , \parity , c8 -.endm - -// Assert x == y -.macro rcp_iequal x, y - mcrr p7, #7, \x , \y , c0 -.endm - -.macro rcp_iequal_nodelay x, y - mcrr2 p7, #7, \x , \y , c0 -.endm - -// They call this "metaprogramming" I think -.macro rcp_switch_u8_to_ch_cl macro_name, x, args:vararg -.if (\x) == 0 -\macro_name c0, c0, \args -.elseif (\x) == 1 -\macro_name c0, c1, \args -.elseif (\x) == 2 -\macro_name c0, c2, \args -.elseif (\x) == 3 -\macro_name c0, c3, \args -.elseif (\x) == 4 -\macro_name c0, c4, \args -.elseif (\x) == 5 -\macro_name c0, c5, \args -.elseif (\x) == 6 -\macro_name c0, c6, \args -.elseif (\x) == 7 -\macro_name c0, c7, \args -.elseif (\x) == 8 -\macro_name c0, c8, \args -.elseif (\x) == 9 -\macro_name c0, c9, \args -.elseif (\x) == 10 -\macro_name c0, c10, \args -.elseif (\x) == 11 -\macro_name c0, c11, \args -.elseif (\x) == 12 -\macro_name c0, c12, \args -.elseif (\x) == 13 -\macro_name c0, c13, \args -.elseif (\x) == 14 -\macro_name c0, c14, \args -.elseif (\x) == 15 -\macro_name c0, c15, \args -.elseif (\x) == 16 -\macro_name c1, c0, \args -.elseif (\x) == 17 -\macro_name c1, c1, \args -.elseif (\x) == 18 -\macro_name c1, c2, \args -.elseif (\x) == 19 -\macro_name c1, c3, \args -.elseif (\x) == 20 -\macro_name c1, c4, \args -.elseif (\x) == 21 -\macro_name c1, c5, \args -.elseif (\x) == 22 -\macro_name c1, c6, \args -.elseif (\x) == 23 -\macro_name c1, c7, \args -.elseif (\x) == 24 -\macro_name c1, c8, \args -.elseif (\x) == 25 -\macro_name c1, c9, \args -.elseif (\x) == 26 -\macro_name c1, c10, \args -.elseif (\x) == 27 -\macro_name c1, c11, \args -.elseif (\x) == 28 -\macro_name c1, c12, \args -.elseif (\x) == 29 -\macro_name c1, c13, \args -.elseif (\x) == 30 -\macro_name c1, c14, \args -.elseif (\x) == 31 -\macro_name c1, c15, \args -.elseif (\x) == 32 -\macro_name c2, c0, \args -.elseif (\x) == 33 -\macro_name c2, c1, \args -.elseif (\x) == 34 -\macro_name c2, c2, \args -.elseif (\x) == 35 -\macro_name c2, c3, \args -.elseif (\x) == 36 -\macro_name c2, c4, \args -.elseif (\x) == 37 -\macro_name c2, c5, \args -.elseif (\x) == 38 -\macro_name c2, c6, \args -.elseif (\x) == 39 -\macro_name c2, c7, \args -.elseif (\x) == 40 -\macro_name c2, c8, \args -.elseif (\x) == 41 -\macro_name c2, c9, \args -.elseif (\x) == 42 -\macro_name c2, c10, \args -.elseif (\x) == 43 -\macro_name c2, c11, \args -.elseif (\x) == 44 -\macro_name c2, c12, \args -.elseif (\x) == 45 -\macro_name c2, c13, \args -.elseif (\x) == 46 -\macro_name c2, c14, \args -.elseif (\x) == 47 -\macro_name c2, c15, \args -.elseif (\x) == 48 -\macro_name c3, c0, \args -.elseif (\x) == 49 -\macro_name c3, c1, \args -.elseif (\x) == 50 -\macro_name c3, c2, \args -.elseif (\x) == 51 -\macro_name c3, c3, \args -.elseif (\x) == 52 -\macro_name c3, c4, \args -.elseif (\x) == 53 -\macro_name c3, c5, \args -.elseif (\x) == 54 -\macro_name c3, c6, \args -.elseif (\x) == 55 -\macro_name c3, c7, \args -.elseif (\x) == 56 -\macro_name c3, c8, \args -.elseif (\x) == 57 -\macro_name c3, c9, \args -.elseif (\x) == 58 -\macro_name c3, c10, \args -.elseif (\x) == 59 -\macro_name c3, c11, \args -.elseif (\x) == 60 -\macro_name c3, c12, \args -.elseif (\x) == 61 -\macro_name c3, c13, \args -.elseif (\x) == 62 -\macro_name c3, c14, \args -.elseif (\x) == 63 -\macro_name c3, c15, \args -.elseif (\x) == 64 -\macro_name c4, c0, \args -.elseif (\x) == 65 -\macro_name c4, c1, \args -.elseif (\x) == 66 -\macro_name c4, c2, \args -.elseif (\x) == 67 -\macro_name c4, c3, \args -.elseif (\x) == 68 -\macro_name c4, c4, \args -.elseif (\x) == 69 -\macro_name c4, c5, \args -.elseif (\x) == 70 -\macro_name c4, c6, \args -.elseif (\x) == 71 -\macro_name c4, c7, \args -.elseif (\x) == 72 -\macro_name c4, c8, \args -.elseif (\x) == 73 -\macro_name c4, c9, \args -.elseif (\x) == 74 -\macro_name c4, c10, \args -.elseif (\x) == 75 -\macro_name c4, c11, \args -.elseif (\x) == 76 -\macro_name c4, c12, \args -.elseif (\x) == 77 -\macro_name c4, c13, \args -.elseif (\x) == 78 -\macro_name c4, c14, \args -.elseif (\x) == 79 -\macro_name c4, c15, \args -.elseif (\x) == 80 -\macro_name c5, c0, \args -.elseif (\x) == 81 -\macro_name c5, c1, \args -.elseif (\x) == 82 -\macro_name c5, c2, \args -.elseif (\x) == 83 -\macro_name c5, c3, \args -.elseif (\x) == 84 -\macro_name c5, c4, \args -.elseif (\x) == 85 -\macro_name c5, c5, \args -.elseif (\x) == 86 -\macro_name c5, c6, \args -.elseif (\x) == 87 -\macro_name c5, c7, \args -.elseif (\x) == 88 -\macro_name c5, c8, \args -.elseif (\x) == 89 -\macro_name c5, c9, \args -.elseif (\x) == 90 -\macro_name c5, c10, \args -.elseif (\x) == 91 -\macro_name c5, c11, \args -.elseif (\x) == 92 -\macro_name c5, c12, \args -.elseif (\x) == 93 -\macro_name c5, c13, \args -.elseif (\x) == 94 -\macro_name c5, c14, \args -.elseif (\x) == 95 -\macro_name c5, c15, \args -.elseif (\x) == 96 -\macro_name c6, c0, \args -.elseif (\x) == 97 -\macro_name c6, c1, \args -.elseif (\x) == 98 -\macro_name c6, c2, \args -.elseif (\x) == 99 -\macro_name c6, c3, \args -.elseif (\x) == 100 -\macro_name c6, c4, \args -.elseif (\x) == 101 -\macro_name c6, c5, \args -.elseif (\x) == 102 -\macro_name c6, c6, \args -.elseif (\x) == 103 -\macro_name c6, c7, \args -.elseif (\x) == 104 -\macro_name c6, c8, \args -.elseif (\x) == 105 -\macro_name c6, c9, \args -.elseif (\x) == 106 -\macro_name c6, c10, \args -.elseif (\x) == 107 -\macro_name c6, c11, \args -.elseif (\x) == 108 -\macro_name c6, c12, \args -.elseif (\x) == 109 -\macro_name c6, c13, \args -.elseif (\x) == 110 -\macro_name c6, c14, \args -.elseif (\x) == 111 -\macro_name c6, c15, \args -.elseif (\x) == 112 -\macro_name c7, c0, \args -.elseif (\x) == 113 -\macro_name c7, c1, \args -.elseif (\x) == 114 -\macro_name c7, c2, \args -.elseif (\x) == 115 -\macro_name c7, c3, \args -.elseif (\x) == 116 -\macro_name c7, c4, \args -.elseif (\x) == 117 -\macro_name c7, c5, \args -.elseif (\x) == 118 -\macro_name c7, c6, \args -.elseif (\x) == 119 -\macro_name c7, c7, \args -.elseif (\x) == 120 -\macro_name c7, c8, \args -.elseif (\x) == 121 -\macro_name c7, c9, \args -.elseif (\x) == 122 -\macro_name c7, c10, \args -.elseif (\x) == 123 -\macro_name c7, c11, \args -.elseif (\x) == 124 -\macro_name c7, c12, \args -.elseif (\x) == 125 -\macro_name c7, c13, \args -.elseif (\x) == 126 -\macro_name c7, c14, \args -.elseif (\x) == 127 -\macro_name c7, c15, \args -.elseif (\x) == 128 -\macro_name c8, c0, \args -.elseif (\x) == 129 -\macro_name c8, c1, \args -.elseif (\x) == 130 -\macro_name c8, c2, \args -.elseif (\x) == 131 -\macro_name c8, c3, \args -.elseif (\x) == 132 -\macro_name c8, c4, \args -.elseif (\x) == 133 -\macro_name c8, c5, \args -.elseif (\x) == 134 -\macro_name c8, c6, \args -.elseif (\x) == 135 -\macro_name c8, c7, \args -.elseif (\x) == 136 -\macro_name c8, c8, \args -.elseif (\x) == 137 -\macro_name c8, c9, \args -.elseif (\x) == 138 -\macro_name c8, c10, \args -.elseif (\x) == 139 -\macro_name c8, c11, \args -.elseif (\x) == 140 -\macro_name c8, c12, \args -.elseif (\x) == 141 -\macro_name c8, c13, \args -.elseif (\x) == 142 -\macro_name c8, c14, \args -.elseif (\x) == 143 -\macro_name c8, c15, \args -.elseif (\x) == 144 -\macro_name c9, c0, \args -.elseif (\x) == 145 -\macro_name c9, c1, \args -.elseif (\x) == 146 -\macro_name c9, c2, \args -.elseif (\x) == 147 -\macro_name c9, c3, \args -.elseif (\x) == 148 -\macro_name c9, c4, \args -.elseif (\x) == 149 -\macro_name c9, c5, \args -.elseif (\x) == 150 -\macro_name c9, c6, \args -.elseif (\x) == 151 -\macro_name c9, c7, \args -.elseif (\x) == 152 -\macro_name c9, c8, \args -.elseif (\x) == 153 -\macro_name c9, c9, \args -.elseif (\x) == 154 -\macro_name c9, c10, \args -.elseif (\x) == 155 -\macro_name c9, c11, \args -.elseif (\x) == 156 -\macro_name c9, c12, \args -.elseif (\x) == 157 -\macro_name c9, c13, \args -.elseif (\x) == 158 -\macro_name c9, c14, \args -.elseif (\x) == 159 -\macro_name c9, c15, \args -.elseif (\x) == 160 -\macro_name c10, c0, \args -.elseif (\x) == 161 -\macro_name c10, c1, \args -.elseif (\x) == 162 -\macro_name c10, c2, \args -.elseif (\x) == 163 -\macro_name c10, c3, \args -.elseif (\x) == 164 -\macro_name c10, c4, \args -.elseif (\x) == 165 -\macro_name c10, c5, \args -.elseif (\x) == 166 -\macro_name c10, c6, \args -.elseif (\x) == 167 -\macro_name c10, c7, \args -.elseif (\x) == 168 -\macro_name c10, c8, \args -.elseif (\x) == 169 -\macro_name c10, c9, \args -.elseif (\x) == 170 -\macro_name c10, c10, \args -.elseif (\x) == 171 -\macro_name c10, c11, \args -.elseif (\x) == 172 -\macro_name c10, c12, \args -.elseif (\x) == 173 -\macro_name c10, c13, \args -.elseif (\x) == 174 -\macro_name c10, c14, \args -.elseif (\x) == 175 -\macro_name c10, c15, \args -.elseif (\x) == 176 -\macro_name c11, c0, \args -.elseif (\x) == 177 -\macro_name c11, c1, \args -.elseif (\x) == 178 -\macro_name c11, c2, \args -.elseif (\x) == 179 -\macro_name c11, c3, \args -.elseif (\x) == 180 -\macro_name c11, c4, \args -.elseif (\x) == 181 -\macro_name c11, c5, \args -.elseif (\x) == 182 -\macro_name c11, c6, \args -.elseif (\x) == 183 -\macro_name c11, c7, \args -.elseif (\x) == 184 -\macro_name c11, c8, \args -.elseif (\x) == 185 -\macro_name c11, c9, \args -.elseif (\x) == 186 -\macro_name c11, c10, \args -.elseif (\x) == 187 -\macro_name c11, c11, \args -.elseif (\x) == 188 -\macro_name c11, c12, \args -.elseif (\x) == 189 -\macro_name c11, c13, \args -.elseif (\x) == 190 -\macro_name c11, c14, \args -.elseif (\x) == 191 -\macro_name c11, c15, \args -.elseif (\x) == 192 -\macro_name c12, c0, \args -.elseif (\x) == 193 -\macro_name c12, c1, \args -.elseif (\x) == 194 -\macro_name c12, c2, \args -.elseif (\x) == 195 -\macro_name c12, c3, \args -.elseif (\x) == 196 -\macro_name c12, c4, \args -.elseif (\x) == 197 -\macro_name c12, c5, \args -.elseif (\x) == 198 -\macro_name c12, c6, \args -.elseif (\x) == 199 -\macro_name c12, c7, \args -.elseif (\x) == 200 -\macro_name c12, c8, \args -.elseif (\x) == 201 -\macro_name c12, c9, \args -.elseif (\x) == 202 -\macro_name c12, c10, \args -.elseif (\x) == 203 -\macro_name c12, c11, \args -.elseif (\x) == 204 -\macro_name c12, c12, \args -.elseif (\x) == 205 -\macro_name c12, c13, \args -.elseif (\x) == 206 -\macro_name c12, c14, \args -.elseif (\x) == 207 -\macro_name c12, c15, \args -.elseif (\x) == 208 -\macro_name c13, c0, \args -.elseif (\x) == 209 -\macro_name c13, c1, \args -.elseif (\x) == 210 -\macro_name c13, c2, \args -.elseif (\x) == 211 -\macro_name c13, c3, \args -.elseif (\x) == 212 -\macro_name c13, c4, \args -.elseif (\x) == 213 -\macro_name c13, c5, \args -.elseif (\x) == 214 -\macro_name c13, c6, \args -.elseif (\x) == 215 -\macro_name c13, c7, \args -.elseif (\x) == 216 -\macro_name c13, c8, \args -.elseif (\x) == 217 -\macro_name c13, c9, \args -.elseif (\x) == 218 -\macro_name c13, c10, \args -.elseif (\x) == 219 -\macro_name c13, c11, \args -.elseif (\x) == 220 -\macro_name c13, c12, \args -.elseif (\x) == 221 -\macro_name c13, c13, \args -.elseif (\x) == 222 -\macro_name c13, c14, \args -.elseif (\x) == 223 -\macro_name c13, c15, \args -.elseif (\x) == 224 -\macro_name c14, c0, \args -.elseif (\x) == 225 -\macro_name c14, c1, \args -.elseif (\x) == 226 -\macro_name c14, c2, \args -.elseif (\x) == 227 -\macro_name c14, c3, \args -.elseif (\x) == 228 -\macro_name c14, c4, \args -.elseif (\x) == 229 -\macro_name c14, c5, \args -.elseif (\x) == 230 -\macro_name c14, c6, \args -.elseif (\x) == 231 -\macro_name c14, c7, \args -.elseif (\x) == 232 -\macro_name c14, c8, \args -.elseif (\x) == 233 -\macro_name c14, c9, \args -.elseif (\x) == 234 -\macro_name c14, c10, \args -.elseif (\x) == 235 -\macro_name c14, c11, \args -.elseif (\x) == 236 -\macro_name c14, c12, \args -.elseif (\x) == 237 -\macro_name c14, c13, \args -.elseif (\x) == 238 -\macro_name c14, c14, \args -.elseif (\x) == 239 -\macro_name c14, c15, \args -.elseif (\x) == 240 -\macro_name c15, c0, \args -.elseif (\x) == 241 -\macro_name c15, c1, \args -.elseif (\x) == 242 -\macro_name c15, c2, \args -.elseif (\x) == 243 -\macro_name c15, c3, \args -.elseif (\x) == 244 -\macro_name c15, c4, \args -.elseif (\x) == 245 -\macro_name c15, c5, \args -.elseif (\x) == 246 -\macro_name c15, c6, \args -.elseif (\x) == 247 -\macro_name c15, c7, \args -.elseif (\x) == 248 -\macro_name c15, c8, \args -.elseif (\x) == 249 -\macro_name c15, c9, \args -.elseif (\x) == 250 -\macro_name c15, c10, \args -.elseif (\x) == 251 -\macro_name c15, c11, \args -.elseif (\x) == 252 -\macro_name c15, c12, \args -.elseif (\x) == 253 -\macro_name c15, c13, \args -.elseif (\x) == 254 -\macro_name c15, c14, \args -.elseif (\x) == 255 -\macro_name c15, c15, \args -.else -.error "Value outside of range 0-255" -.endif -.endm - -// Directly write 8-bit constant expression cnt to the sequence counter. -.macro rcp_count_set_impl h, l -mcr p7, #4, r0, \h , \l , #0 -.endm -.macro rcp_count_set cnt -rcp_switch_u8_to_ch_cl rcp_count_set_impl, \cnt -.endm - -.macro rcp_count_set_nodelay_impl h, l -mcr2 p7, #4, r0, \h , \l , #0 -.endm -.macro rcp_count_set_nodelay cnt -rcp_switch_u8_to_ch_cl rcp_count_set_nodelay_impl, \cnt -.endm - -// Check 8-bit constant expression cnt against the sequence counter, then -// increment the counter. -.macro rcp_count_check_impl h, l - mcr p7, #5, r0, \h, \l, #1 -.endm -.macro rcp_count_check cnt -rcp_switch_u8_to_ch_cl rcp_count_check_impl, \cnt -.endm - -.macro rcp_count_check_nodelay_impl h, l - mcr2 p7, #5, r0, \h, \l, #1 -.endm -.macro rcp_count_check_nodelay cnt -rcp_switch_u8_to_ch_cl rcp_count_check_nodelay_impl, \cnt -.endm - -// Get a 32-bit canary value. `tag` must be a constant expression. -.macro rcp_canary_get_impl h, l, x - mrc p7, #0, \x, \h, \l, #1 -.endm - -.macro rcp_canary_get x, tag -rcp_switch_u8_to_ch_cl rcp_canary_get_impl \tag, \x -.endm - -// Get a 32-bit canary value. `tag` must be a constant expression. -.macro rcp_canary_get_nodelay_impl h, l, x - mrc2 p7, #0, \x, \h, \l, #1 -.endm - -.macro rcp_canary_get_nodelay x, tag -rcp_switch_u8_to_ch_cl rcp_canary_get_nodelay_impl \tag, \x -.endm - -// Assert that canary matches result of rcp_canary_get with the same tags: -.macro rcp_canary_check_impl h, l, x - mcr p7, #0, \x, \h, \l, #1 -.endm - -.macro rcp_canary_check x, tag -rcp_switch_u8_to_ch_cl rcp_canary_check_impl \tag, \x -.endm - -.macro rcp_canary_check_nodelay_impl h, l, x - mcr2 p7, #0, \x, \h, \l, #1 -.endm - -.macro rcp_canary_check_nodelay x, tag -rcp_switch_u8_to_ch_cl rcp_canary_check_nodelay_impl \tag, \x -.endm - -.macro rcp_panic - cdp p7, #0, c0, c0, c0, #1 -.endm - -#endif // !__riscv -#endif // __ASSEMBLER__ -// ---------------------------------------------------------------------------- - -#ifdef __cplusplus -} -#endif -#endif -#endif diff --git a/lib/main/pico-sdk/rp2_common/hardware_resets/include/hardware/resets.h b/lib/main/pico-sdk/rp2_common/hardware_resets/include/hardware/resets.h deleted file mode 100644 index 8baef728b5..0000000000 --- a/lib/main/pico-sdk/rp2_common/hardware_resets/include/hardware/resets.h +++ /dev/null @@ -1,178 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _HARDWARE_RESETS_H -#define _HARDWARE_RESETS_H - -#include "pico.h" -#include "hardware/structs/resets.h" - -/** \file hardware/resets.h - * \defgroup hardware_resets hardware_resets - * - * \brief Hardware Reset API - * - * The reset controller allows software control of the resets to all of the peripherals that are not - * critical to boot the processor in the RP-series microcontroller. - * - * \subsubsection reset_bitmask - * \addtogroup hardware_resets - * - * Multiple blocks are referred to using a bitmask as follows: - * - * Block to reset | Bit - * ---------------|---- - * USB | 24 - * UART 1 | 23 - * UART 0 | 22 - * Timer | 21 - * TB Manager | 20 - * SysInfo | 19 - * System Config | 18 - * SPI 1 | 17 - * SPI 0 | 16 - * RTC | 15 - * PWM | 14 - * PLL USB | 13 - * PLL System | 12 - * PIO 1 | 11 - * PIO 0 | 10 - * Pads - QSPI | 9 - * Pads - bank 0 | 8 - * JTAG | 7 - * IO Bank 1 | 6 - * IO Bank 0 | 5 - * I2C 1 | 4 - * I2C 0 | 3 - * DMA | 2 - * Bus Control | 1 - * ADC 0 | 0 - * - * \subsection reset_example Example - * \addtogroup hardware_resets - * \include hello_reset.c - */ - -// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_HARDWARE_RESETS, Enable/disable assertions in the hardware_resets module, type=bool, default=0, group=hardware_adc -#ifndef PARAM_ASSERTIONS_ENABLED_HARDWARE_RESETS -#ifdef PARAM_ASSERTIONS_ENABLED_RESET // backwards compatibility with SDK < 2.0.0 -#define PARAM_ASSERTIONS_ENABLED_HARDWARE_RESETS PARAM_ASSERTIONS_ENABLED_RESET -#else -#define PARAM_ASSERTIONS_ENABLED_HARDWARE_RESETS 0 -#endif -#endif -#ifdef __cplusplus -extern "C" { -#endif - -static __force_inline void reset_block_reg_mask(io_rw_32 *reset, uint32_t mask) { - hw_set_bits(reset, mask); -} - -static __force_inline void unreset_block_reg_mask(io_rw_32 *reset, uint32_t mask) { - hw_clear_bits(reset, mask); -} - -static __force_inline void unreset_block_reg_mask_wait_blocking(io_rw_32 *reset, io_ro_32 *reset_done, uint32_t mask) { - hw_clear_bits(reset, mask); - while (~*reset_done & mask) - tight_loop_contents(); -} - -/// \tag::reset_funcs[] - -/*! \brief Reset the specified HW blocks - * \ingroup hardware_resets - * - * \param bits Bit pattern indicating blocks to reset. See \ref reset_bitmask - */ -static __force_inline void reset_block_mask(uint32_t bits) { - reset_block_reg_mask(&resets_hw->reset, bits); -} - -/*! \brief bring specified HW blocks out of reset - * \ingroup hardware_resets - * - * \param bits Bit pattern indicating blocks to unreset. See \ref reset_bitmask - */ -static __force_inline void unreset_block_mask(uint32_t bits) { - unreset_block_reg_mask(&resets_hw->reset, bits); -} - -/*! \brief Bring specified HW blocks out of reset and wait for completion - * \ingroup hardware_resets - * - * \param bits Bit pattern indicating blocks to unreset. See \ref reset_bitmask - */ -static __force_inline void unreset_block_mask_wait_blocking(uint32_t bits) { - unreset_block_reg_mask_wait_blocking(&resets_hw->reset, &resets_hw->reset_done, bits); -} - -/// \end::reset_funcs[] - -#ifndef HARDWARE_RESETS_ENABLE_SDK1XX_COMPATIBILITY -#define HARDWARE_RESETS_ENABLE_SDK1XX_COMPATIBILITY 1 -#endif - -#if HARDWARE_RESETS_ENABLE_SDK1XX_COMPATIBILITY -static __force_inline void reset_block(uint32_t bits) { - reset_block_mask(bits); -} - -static __force_inline void unreset_block(uint32_t bits) { - unreset_block_mask(bits); -} - -static __force_inline void unreset_block_wait(uint32_t bits) { - return unreset_block_mask_wait_blocking(bits); -} -#endif - -/*! \brief Reset the specified HW block - * \ingroup hardware_resets - * - * \param block_num the block number - */ -static inline void reset_block_num(uint32_t block_num) { - reset_block_reg_mask(&resets_hw->reset, 1u << block_num); -} - -/*! \brief bring specified HW block out of reset - * \ingroup hardware_resets - * - * \param block_num the block number - */ -static inline void unreset_block_num(uint block_num) { - invalid_params_if(HARDWARE_RESETS, block_num > NUM_RESETS); - unreset_block_reg_mask(&resets_hw->reset, 1u << block_num); -} - -/*! \brief Bring specified HW block out of reset and wait for completion - * \ingroup hardware_resets - * - * \param block_num the block number - */ -static inline void unreset_block_num_wait_blocking(uint block_num) { - invalid_params_if(HARDWARE_RESETS, block_num > NUM_RESETS); - unreset_block_reg_mask_wait_blocking(&resets_hw->reset, &resets_hw->reset_done, 1u << block_num); -} - -/*! \brief Reset the specified HW block, and then bring at back out of reset and wait for completion - * \ingroup hardware_resets - * - * \param block_num the block number - */ -static inline void reset_unreset_block_num_wait_blocking(uint block_num) { - invalid_params_if(HARDWARE_RESETS, block_num > NUM_RESETS); - reset_block_reg_mask(&resets_hw->reset, 1u << block_num); - unreset_block_reg_mask_wait_blocking(&resets_hw->reset, &resets_hw->reset_done, 1u << block_num); -} - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/lib/main/pico-sdk/rp2_common/hardware_riscv/include/hardware/riscv.h b/lib/main/pico-sdk/rp2_common/hardware_riscv/include/hardware/riscv.h deleted file mode 100644 index afdd2e55de..0000000000 --- a/lib/main/pico-sdk/rp2_common/hardware_riscv/include/hardware/riscv.h +++ /dev/null @@ -1,179 +0,0 @@ -/* - * Copyright (c) 2022 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _HARDWARE_RISCV_ -#define _HARDWARE_RISCV_ - -#include "pico.h" -#include "hardware/regs/rvcsr.h" - -#ifndef __ASSEMBLER__ - -#ifdef __cplusplus -extern "C" { -#endif - -/** \file hardware/riscv.h - * \defgroup hardware_riscv hardware_riscv - * - * \brief Accessors for standard RISC-V hardware (mainly CSRs) - * - */ - -#define _riscv_read_csr(csrname) ({ \ - uint32_t __csr_tmp_u32; \ - asm volatile ("csrr %0, " #csrname : "=r" (__csr_tmp_u32)); \ - __csr_tmp_u32; \ -}) - -#define _riscv_write_csr(csrname, data) ({ \ - if (__builtin_constant_p(data) && !((data) & -32u)) { \ - asm volatile ("csrwi " #csrname ", %0" : : "i" (data)); \ - } else { \ - asm volatile ("csrw " #csrname ", %0" : : "r" (data)); \ - } \ -}) - -#define _riscv_set_csr(csrname, data) ({ \ - if (__builtin_constant_p(data) && !((data) & -32u)) { \ - asm volatile ("csrsi " #csrname ", %0" : : "i" (data)); \ - } else { \ - asm volatile ("csrs " #csrname ", %0" : : "r" (data)); \ - } \ -}) - -#define _riscv_clear_csr(csrname, data) ({ \ - if (__builtin_constant_p(data) && !((data) & -32u)) { \ - asm volatile ("csrci " #csrname ", %0" : : "i" (data)); \ - } else { \ - asm volatile ("csrc " #csrname ", %0" : : "r" (data)); \ - } \ -}) - -#define _riscv_read_write_csr(csrname, data) ({ \ - uint32_t __csr_tmp_u32; \ - if (__builtin_constant_p(data) && !((data) & -32u)) { \ - asm volatile ("csrrwi %0, " #csrname ", %1": "=r" (__csr_tmp_u32) : "i" (data)); \ - } else { \ - asm volatile ("csrrw %0, " #csrname ", %1": "=r" (__csr_tmp_u32) : "r" (data)); \ - } \ - __csr_tmp_u32; \ -}) - -#define _riscv_read_set_csr(csrname, data) ({ \ - uint32_t __csr_tmp_u32; \ - if (__builtin_constant_p(data) && !((data) & -32u)) { \ - asm volatile ("csrrsi %0, " #csrname ", %1": "=r" (__csr_tmp_u32) : "i" (data)); \ - } else { \ - asm volatile ("csrrs %0, " #csrname ", %1": "=r" (__csr_tmp_u32) : "r" (data)); \ - } \ - __csr_tmp_u32; \ -}) - -#define _riscv_read_clear_csr(csrname, data) ({ \ - uint32_t __csr_tmp_u32; \ - if (__builtin_constant_p(data) && !((data) & -32u)) { \ - asm volatile ("csrrci %0, " #csrname ", %1": "=r" (__csr_tmp_u32) : "i" (data)); \ - } else { \ - asm volatile ("csrrc %0, " #csrname ", %1": "=r" (__csr_tmp_u32) : "r" (data)); \ - } \ - __csr_tmp_u32; \ -}) - -// Argument macro expansion layer (CSR name may be a macro that expands to a -// CSR number, or it may be a bare name that the assembler knows about.) -#define riscv_read_csr(csrname) _riscv_read_csr(csrname) -#define riscv_write_csr(csrname, data) _riscv_write_csr(csrname, data) -#define riscv_set_csr(csrname, data) _riscv_set_csr(csrname, data) -#define riscv_clear_csr(csrname, data) _riscv_clear_csr(csrname, data) -#define riscv_read_write_csr(csrname, data) _riscv_read_write_csr(csrname, data) -#define riscv_read_set_csr(csrname, data) _riscv_read_set_csr(csrname, data) -#define riscv_read_clear_csr(csrname, data) _riscv_read_clear_csr(csrname, data) - -// Helpers for encoding RISC-V immediates - -// U format, e.g. lui -static inline uint32_t riscv_encode_imm_u(uint32_t x) { - return (x >> 12) << 12; -} - -// I format, e.g. addi -static inline uint32_t riscv_encode_imm_i(uint32_t x) { - return (x & 0xfff) << 20; -} - -// The U-format part of a U+I 32-bit immediate: -static inline uint32_t riscv_encode_imm_u_hi(uint32_t x) { - // We will add a signed 12 bit constant to the "lui" value, - // so we need to correct for the carry here. - x += (x & 0x800) << 1; - return riscv_encode_imm_u(x); -} - -// B format, e.g. bgeu -static inline uint32_t riscv_encode_imm_b(uint32_t x) { - return - (((x >> 12) & 0x01) << 31) | - (((x >> 5) & 0x3f) << 25) | - (((x >> 1) & 0x0f) << 8) | - (((x >> 11) & 0x01) << 7); -} - -// S format, e.g. sw -static inline uint32_t riscv_encode_imm_s(uint32_t x) { - return - (((x >> 5) & 0x7f) << 25) | - (((x >> 0) & 0x1f) << 7); -} - -// J format, e.g. jal -static inline uint32_t riscv_encode_imm_j(uint32_t x) { - return - (((x >> 20) & 0x001) << 31) | - (((x >> 1) & 0x3ff) << 21) | - (((x >> 11) & 0x001) << 20) | - (((x >> 12) & 0x0ff) << 12); -} - -// CJ format, e.g. c.jal -static inline uint16_t riscv_encode_imm_cj(uint32_t x) { - return (uint16_t)( - (((x >> 11) & 0x1) << 12) | - (((x >> 4) & 0x1) << 11) | - (((x >> 8) & 0x3) << 9) | - (((x >> 10) & 0x1) << 8) | - (((x >> 6) & 0x1) << 7) | - (((x >> 7) & 0x1) << 6) | - (((x >> 1) & 0x7) << 3) | - (((x >> 5) & 0x1) << 2) - ); -} - -// CB format, e.g. c.beqz -static inline uint16_t riscv_encode_imm_cb(uint32_t x) { - return (uint16_t)( - (((x >> 8) & 0x1) << 12) | - (((x >> 3) & 0x3) << 10) | - (((x >> 6) & 0x3) << 5) | - (((x >> 1) & 0x3) << 3) | - (((x >> 5) & 0x1) << 2) - ); -} - -// CI format, e.g. c.addi -static inline uint16_t riscv_encode_imm_ci(uint32_t x) { - return (uint16_t)( - (((x >> 5) & 0x01) << 12) | - (((x >> 0) & 0x1f) << 2) - ); -} - -#ifdef __cplusplus -} -#endif - -#endif -#endif diff --git a/lib/main/pico-sdk/rp2_common/hardware_riscv_platform_timer/include/hardware/riscv_platform_timer.h b/lib/main/pico-sdk/rp2_common/hardware_riscv_platform_timer/include/hardware/riscv_platform_timer.h deleted file mode 100644 index c2dfeccc74..0000000000 --- a/lib/main/pico-sdk/rp2_common/hardware_riscv_platform_timer/include/hardware/riscv_platform_timer.h +++ /dev/null @@ -1,145 +0,0 @@ -#ifndef _HARDWARE_RISCV_PLATFORM_TIMER_ -#define _HARDWARE_RISCV_PLATFORM_TIMER_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include "pico.h" -#include "hardware/structs/sio.h" - -/** \file hardware/riscv_platform_timer.h - * \defgroup hardware_riscv_platform_timer hardware_riscv_platform_timer - * - * \brief Accessors for standard RISC-V platform timer (mtime/mtimecmp), available on - * Raspberry Pi microcontrollers with RISC-V processors - * - * Note this header can be used by Arm as well as RISC-V processors, as the - * timer is a memory-mapped peripheral external to the processors. The name - * refers to this timer being a standard RISC-V peripheral. - * - */ - -/*! \brief Enable or disable the RISC-V platform timer - * \ingroup hardware_riscv_platform_timer - * - * This enables and disables the counting of the RISC-V platform timer. It - * does not enable or disable the interrupts, which are asserted - * unconditionally when a given core's mtimecmp/mtimecmph registers are - * greater than the current 64-bit value of the mtime/mtimeh registers. - * - * \param enabled Pass true to enable, false to disable - */ -static inline void riscv_timer_set_enabled(bool enabled) { - if (enabled) { - // Note atomic rwtype is not supported on SIO - sio_hw->mtime_ctrl |= SIO_MTIME_CTRL_EN_BITS; - } else { - sio_hw->mtime_ctrl &= ~SIO_MTIME_CTRL_EN_BITS; - } -} - -/*! \brief Configure the RISC-V platform timer to run at full system clock speed - * \ingroup hardware_riscv_platform_timer - * - * \param fullspeed Pass true to increment at system clock speed, false to - * increment at the frequency defined by the system tick generator - * (the `ticks` block) - */ -static inline void riscv_timer_set_fullspeed(bool fullspeed) { - if (fullspeed) { - sio_hw->mtime_ctrl |= SIO_MTIME_CTRL_FULLSPEED_BITS; - } else { - sio_hw->mtime_ctrl &= ~SIO_MTIME_CTRL_FULLSPEED_BITS; - } -} - -/*! \brief Read the RISC-V platform timer - * \ingroup hardware_riscv_platform_timer - * - * \return Current 64-bit mtime value - */ -static inline uint64_t riscv_timer_get_mtime(void) { - // Read procedure from RISC-V ISA manual to avoid being off by 2**32 on - // low half rollover -- note this loop generally executes only once, and - // should never execute more than twice: - uint32_t h0, l, h1; - do { - h0 = sio_hw->mtimeh; - l = sio_hw->mtime; - h1 = sio_hw->mtimeh; - } while (h0 != h1); - return l | (uint64_t)h1 << 32; -} - -/*! \brief Update the RISC-V platform timer - * \ingroup hardware_riscv_platform_timer - * - * This function should only be called when the timer is disabled via - * riscv_timer_set_enabled(). Note also that unlike the mtimecmp comparison - * values, mtime is *not* core-local, so updates on one core will be visible - * to the other core. - * - * \param mtime New value to set the RISC-V platform timer to - */ -static inline void riscv_timer_set_mtime(uint64_t mtime) { - // This ought really only be done when the timer is stopped, but we can - // make things a bit safer by clearing the low half of the counter, then - // writing high half, then low half. This protects against the low half - // rolling over, and largely avoids getting an intermediate value that is - // higher than either the original or new value, if the timer is running. - // - // Note that on RP2350, mtime is shared between the two cores!(mtimcemp is - // core-local however.) - sio_hw->mtime = 0; - sio_hw->mtimeh = mtime >> 32; - sio_hw->mtime = mtime & 0xffffffffu; -} - -/*! \brief Get the current RISC-V platform timer mtimecmp value for this core - * \ingroup hardware_riscv_platform_timer - * - * Get the current mtimecmp value for the calling core. This function is - * interrupt-safe as long as timer interrupts only increase the value of - * mtimecmp. Otherwise, it must be called with timer interrupts disabled. - * - * \return Current value of mtimecmp - */ -static inline uint64_t riscv_timer_get_mtimecmp(void) { - // Use the same procedure as reading mtime, which should be safe assuming - // mtimecmp increases monotonically with successive interrupts. - uint32_t h0, l, h1; - do { - h0 = sio_hw->mtimecmph; - l = sio_hw->mtimecmp; - h1 = sio_hw->mtimecmph; - } while (h0 != h1); - return l | (uint64_t)h1 << 32; -} - -/*! \brief Set a new RISC-V platform timer interrupt comparison value (mtimecmp) for this core - * \ingroup hardware_riscv_platform_timer - * - * This function updates the mtimecmp value for the current core. The calling - * core's RISC-V platform timer interrupt is asserted whenever the 64-bit - * mtime value (stored in 32-bit mtime/mtimeh registers) is greater than or - * equal to this core's current mtime/mtimecmph value. - * - * \param mtime New value to set the RISC-V platform timer to - */ -static inline void riscv_timer_set_mtimecmp(uint64_t mtimecmp) { - // Use write procedure from RISC-V ISA manual to avoid causing a spurious - // interrupt when updating the two halves of mtimecmp. - // No lower than original: - sio_hw->mtimecmp = -1u; - // No lower than original, no lower than new (assuming new >= original): - sio_hw->mtimecmph = mtimecmp >> 32; - // Equal to new: - sio_hw->mtimecmp = mtimecmp & 0xffffffffu; -} - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/lib/main/pico-sdk/rp2_common/hardware_rtc/include/hardware/rtc.h b/lib/main/pico-sdk/rp2_common/hardware_rtc/include/hardware/rtc.h deleted file mode 100644 index 32317879c4..0000000000 --- a/lib/main/pico-sdk/rp2_common/hardware_rtc/include/hardware/rtc.h +++ /dev/null @@ -1,95 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _HARDWARE_RTC_H -#define _HARDWARE_RTC_H - -#include "pico.h" -#include "hardware/structs/rtc.h" - -/** \file hardware/rtc.h - * \defgroup hardware_rtc hardware_rtc - * - * \brief Hardware Real Time Clock API - * - * The RTC keeps track of time in human readable format and generates events when the time is equal - * to a preset value. Think of a digital clock, not epoch time used by most computers. There are seven - * fields, one each for year (12 bit), month (4 bit), day (5 bit), day of the week (3 bit), hour (5 bit) - * minute (6 bit) and second (6 bit), storing the data in binary format. - * - * \sa datetime_t - * - * \subsection rtc_example Example - * \addtogroup hardware_rtc - * - * \include hello_rtc.c - */ - -#ifdef __cplusplus -extern "C" { -#endif - -/*! Callback function type for RTC alarms - * \ingroup hardware_rtc - * - * \sa rtc_set_alarm() - */ -typedef void (*rtc_callback_t)(void); - -/*! \brief Initialise the RTC system - * \ingroup hardware_rtc - */ -void rtc_init(void); - -/*! \brief Set the RTC to the specified time - * \ingroup hardware_rtc - * - * \note Note that after setting the RTC date and time, a subsequent read of the values (e.g. via rtc_get_datetime()) may not - * reflect the new setting until up to three cycles of the potentially-much-slower RTC clock domain have passed. This represents a period - * of 64 microseconds with the default RTC clock configuration. - * - * \param t Pointer to a \ref datetime_t structure contains time to set - * \return true if set, false if the passed in datetime was invalid. - */ -bool rtc_set_datetime(const datetime_t *t); - -/*! \brief Get the current time from the RTC - * \ingroup hardware_rtc - * - * \param t Pointer to a \ref datetime_t structure to receive the current RTC time - * \return true if datetime is valid, false if the RTC is not running. - */ -bool rtc_get_datetime(datetime_t *t); - -/*! \brief Is the RTC running? - * \ingroup hardware_rtc - * - */ -bool rtc_running(void); - -/*! \brief Set a time in the future for the RTC to call a user provided callback - * \ingroup hardware_rtc - * - * \param t Pointer to a \ref datetime_t structure containing a time in the future to fire the alarm. Any values set to -1 will not be matched on. - * \param user_callback pointer to a \ref rtc_callback_t to call when the alarm fires - */ -void rtc_set_alarm(const datetime_t *t, rtc_callback_t user_callback); - -/*! \brief Enable the RTC alarm (if inactive) - * \ingroup hardware_rtc - */ -void rtc_enable_alarm(void); - -/*! \brief Disable the RTC alarm (if active) - * \ingroup hardware_rtc - */ -void rtc_disable_alarm(void); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/lib/main/pico-sdk/rp2_common/hardware_rtc/rtc.c b/lib/main/pico-sdk/rp2_common/hardware_rtc/rtc.c deleted file mode 100644 index f3f61eabfa..0000000000 --- a/lib/main/pico-sdk/rp2_common/hardware_rtc/rtc.c +++ /dev/null @@ -1,190 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "pico.h" - -#include "hardware/irq.h" -#include "hardware/rtc.h" -#include "hardware/resets.h" -#include "hardware/clocks.h" - -// Set this when setting an alarm -static rtc_callback_t _callback = NULL; -static bool _alarm_repeats = false; - -bool rtc_running(void) { - return (rtc_hw->ctrl & RTC_CTRL_RTC_ACTIVE_BITS); -} - -void rtc_init(void) { - // Get clk_rtc freq and make sure it is running - uint rtc_freq = clock_get_hz(clk_rtc); - assert(rtc_freq != 0); - - // Take rtc out of reset now that we know clk_rtc is running - reset_unreset_block_num_wait_blocking(RESET_RTC); - - // Set up the 1 second divider. - // If rtc_freq is 400 then clkdiv_m1 should be 399 - rtc_freq -= 1; - - // Check the freq is not too big to divide - assert(rtc_freq <= RTC_CLKDIV_M1_BITS); - - // Write divide value - rtc_hw->clkdiv_m1 = rtc_freq; -} - -static bool valid_datetime(const datetime_t *t) { - // Valid ranges taken from RTC doc. Note when setting an RTC alarm - // these values are allowed to be -1 to say "don't match this value" - if (!(t->year >= 0 && t->year <= 4095)) return false; - if (!(t->month >= 1 && t->month <= 12)) return false; - if (!(t->day >= 1 && t->day <= 31)) return false; - if (!(t->dotw >= 0 && t->dotw <= 6)) return false; - if (!(t->hour >= 0 && t->hour <= 23)) return false; - if (!(t->min >= 0 && t->min <= 59)) return false; - if (!(t->sec >= 0 && t->sec <= 59)) return false; - return true; -} - -bool rtc_set_datetime(const datetime_t *t) { - if (!valid_datetime(t)) { - return false; - } - - // Disable RTC - rtc_hw->ctrl = 0; - // Wait while it is still active - while (rtc_running()) { - tight_loop_contents(); - } - - // Write to setup registers - rtc_hw->setup_0 = (((uint32_t)t->year) << RTC_SETUP_0_YEAR_LSB ) | - (((uint32_t)t->month) << RTC_SETUP_0_MONTH_LSB) | - (((uint32_t)t->day) << RTC_SETUP_0_DAY_LSB); - rtc_hw->setup_1 = (((uint32_t)t->dotw) << RTC_SETUP_1_DOTW_LSB) | - (((uint32_t)t->hour) << RTC_SETUP_1_HOUR_LSB) | - (((uint32_t)t->min) << RTC_SETUP_1_MIN_LSB) | - (((uint32_t)t->sec) << RTC_SETUP_1_SEC_LSB); - - // Load setup values into rtc clock domain - rtc_hw->ctrl = RTC_CTRL_LOAD_BITS; - - // Enable RTC and wait for it to be running - rtc_hw->ctrl = RTC_CTRL_RTC_ENABLE_BITS; - while (!rtc_running()) { - tight_loop_contents(); - } - - return true; -} - -bool rtc_get_datetime(datetime_t *t) { - // Make sure RTC is running - if (!rtc_running()) { - return false; - } - - // Note: RTC_0 should be read before RTC_1 - uint32_t rtc_0 = rtc_hw->rtc_0; - uint32_t rtc_1 = rtc_hw->rtc_1; - - t->dotw = (int8_t) ((rtc_0 & RTC_RTC_0_DOTW_BITS ) >> RTC_RTC_0_DOTW_LSB); - t->hour = (int8_t) ((rtc_0 & RTC_RTC_0_HOUR_BITS ) >> RTC_RTC_0_HOUR_LSB); - t->min = (int8_t) ((rtc_0 & RTC_RTC_0_MIN_BITS ) >> RTC_RTC_0_MIN_LSB); - t->sec = (int8_t) ((rtc_0 & RTC_RTC_0_SEC_BITS ) >> RTC_RTC_0_SEC_LSB); - t->year = (int16_t) ((rtc_1 & RTC_RTC_1_YEAR_BITS ) >> RTC_RTC_1_YEAR_LSB); - t->month = (int8_t) ((rtc_1 & RTC_RTC_1_MONTH_BITS) >> RTC_RTC_1_MONTH_LSB); - t->day = (int8_t) ((rtc_1 & RTC_RTC_1_DAY_BITS ) >> RTC_RTC_1_DAY_LSB); - - return true; -} - -void rtc_enable_alarm(void) { - // Set matching and wait for it to be enabled - hw_set_bits(&rtc_hw->irq_setup_0, RTC_IRQ_SETUP_0_MATCH_ENA_BITS); - while(!(rtc_hw->irq_setup_0 & RTC_IRQ_SETUP_0_MATCH_ACTIVE_BITS)) { - tight_loop_contents(); - } -} - -static void rtc_irq_handler(void) { - // Always disable the alarm to clear the current IRQ. - // Even if it is a repeatable alarm, we don't want it to keep firing. - // If it matches on a second it can keep firing for that second. - rtc_disable_alarm(); - - if (_alarm_repeats) { - // If it is a repeatable alarm, re enable the alarm. - rtc_enable_alarm(); - } - - // Call user callback function - if (_callback) { - _callback(); - } -} - -static bool rtc_alarm_repeats(const datetime_t *t) { - // If any value is set to -1 then we don't match on that value - // hence the alarm will eventually repeat - if (t->year < 0) return true; - if (t->month < 0) return true; - if (t->day < 0) return true; - if (t->dotw < 0) return true; - if (t->hour < 0) return true; - if (t->min < 0) return true; - if (t->sec < 0) return true; - return false; -} - -void rtc_set_alarm(const datetime_t *t, rtc_callback_t user_callback) { - rtc_disable_alarm(); - - // Only add to setup if it isn't -1 - rtc_hw->irq_setup_0 = ((t->year < 0) ? 0 : (((uint32_t)t->year) << RTC_IRQ_SETUP_0_YEAR_LSB )) | - ((t->month < 0) ? 0 : (((uint32_t)t->month) << RTC_IRQ_SETUP_0_MONTH_LSB)) | - ((t->day < 0) ? 0 : (((uint32_t)t->day) << RTC_IRQ_SETUP_0_DAY_LSB )); - rtc_hw->irq_setup_1 = ((t->dotw < 0) ? 0 : (((uint32_t)t->dotw) << RTC_IRQ_SETUP_1_DOTW_LSB)) | - ((t->hour < 0) ? 0 : (((uint32_t)t->hour) << RTC_IRQ_SETUP_1_HOUR_LSB)) | - ((t->min < 0) ? 0 : (((uint32_t)t->min) << RTC_IRQ_SETUP_1_MIN_LSB )) | - ((t->sec < 0) ? 0 : (((uint32_t)t->sec) << RTC_IRQ_SETUP_1_SEC_LSB )); - - // Set the match enable bits for things we care about - if (t->year >= 0) hw_set_bits(&rtc_hw->irq_setup_0, RTC_IRQ_SETUP_0_YEAR_ENA_BITS); - if (t->month >= 0) hw_set_bits(&rtc_hw->irq_setup_0, RTC_IRQ_SETUP_0_MONTH_ENA_BITS); - if (t->day >= 0) hw_set_bits(&rtc_hw->irq_setup_0, RTC_IRQ_SETUP_0_DAY_ENA_BITS); - if (t->dotw >= 0) hw_set_bits(&rtc_hw->irq_setup_1, RTC_IRQ_SETUP_1_DOTW_ENA_BITS); - if (t->hour >= 0) hw_set_bits(&rtc_hw->irq_setup_1, RTC_IRQ_SETUP_1_HOUR_ENA_BITS); - if (t->min >= 0) hw_set_bits(&rtc_hw->irq_setup_1, RTC_IRQ_SETUP_1_MIN_ENA_BITS); - if (t->sec >= 0) hw_set_bits(&rtc_hw->irq_setup_1, RTC_IRQ_SETUP_1_SEC_ENA_BITS); - - // Does it repeat? I.e. do we not match on any of the bits - _alarm_repeats = rtc_alarm_repeats(t); - - // Store function pointer we can call later - _callback = user_callback; - - irq_set_exclusive_handler(RTC_IRQ, rtc_irq_handler); - - // Enable the IRQ at the peri - rtc_hw->inte = RTC_INTE_RTC_BITS; - - // Enable the IRQ at the proc - irq_set_enabled(RTC_IRQ, true); - - rtc_enable_alarm(); -} - -void rtc_disable_alarm(void) { - // Disable matching and wait for it to stop being active - hw_clear_bits(&rtc_hw->irq_setup_0, RTC_IRQ_SETUP_0_MATCH_ENA_BITS); - while(rtc_hw->irq_setup_0 & RTC_IRQ_SETUP_0_MATCH_ACTIVE_BITS) { - tight_loop_contents(); - } -} diff --git a/lib/main/pico-sdk/rp2_common/hardware_sha256/include/hardware/sha256.h b/lib/main/pico-sdk/rp2_common/hardware_sha256/include/hardware/sha256.h deleted file mode 100644 index db8fca6ffc..0000000000 --- a/lib/main/pico-sdk/rp2_common/hardware_sha256/include/hardware/sha256.h +++ /dev/null @@ -1,220 +0,0 @@ -/* - * Copyright (c) 2024 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _HARDWARE_SHA256_H -#define _HARDWARE_SHA256_H - -#include "pico.h" -#include "hardware/structs/sha256.h" - -/** \file hardware/sha256.h - * \defgroup hardware_sha256 hardware_sha256 - * - * \brief Hardware SHA-256 Accelerator API - * - * RP2350 is equipped with an implementation of the SHA-256 hash algorithm. - * The hardware should first be configured by calling the \ref sha256_set_dma_size and \ref sha256_set_bswap functions. - * To generate a new hash the hardware should first be initialised by calling \ref sha256_start. - * The hardware is ready to accept data when \ref sha256_is_ready returns true, - * at which point the data to be hashed can be written to the address returned by \ref sha256_get_write_addr. - * The hardware requires 64 bytes to be written in one go or else \ref sha256_err_not_ready will indicate an error and - * the hashing process must be restarted. - * \ref sha256_is_sum_valid will return true when there is a valid checksum result which can be retrieved by calling \ref sha256_get_result. - */ - -#ifdef __cplusplus -extern "C" { -#endif - -// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_HARDWARE_SHA256, Enable/disable hardware_sha256 assertions, type=bool, default=0, group=hardware_sha256 -#ifndef PARAM_ASSERTIONS_ENABLED_HARDWARE_SHA256 -#ifdef PARAM_ASSERTIONS_ENABLED_SHA256 // backwards compatibility with SDK < 2.0.0 -#define PARAM_ASSERTIONS_ENABLED_HARDWARE_SHA256 PARAM_ASSERTIONS_ENABLED_SHA256 -#else -#define PARAM_ASSERTIONS_ENABLED_HARDWARE_SHA256 0 -#endif -#endif - -/*! \brief Size of a sha256 result in bytes. - * \ingroup hardware_sha256 - */ -#define SHA256_RESULT_BYTES 32 - -/*! \brief SHA-256 endianness definition used in the API - * \ingroup hardware_sha256 - */ -enum sha256_endianness { - SHA256_LITTLE_ENDIAN, ///< Little Endian - SHA256_BIG_ENDIAN, ///< Big Endian -}; - -/*! \brief SHA-256 result generated by the API - * \ingroup hardware_sha256 - */ -typedef union { - uint32_t words[SHA256_RESULT_BYTES/4]; - uint8_t bytes[SHA256_RESULT_BYTES]; -} sha256_result_t; - -/*! \brief Configure the correct DMA data size. - * \ingroup hardware_sha256 - * - * This must be configured before the DMA channel is triggered and ensures the correct number of transfers is requested per block. - * - * \param size_in_bytes Size of DMA transfers, either 1, 2 or 4 bytes only. - */ -static inline void sha256_set_dma_size(uint size_in_bytes) { - uint32_t val; - invalid_params_if(HARDWARE_SHA256, size_in_bytes != 1 && size_in_bytes != 2 && size_in_bytes != 4); - if (size_in_bytes == 1) { - val = SHA256_CSR_DMA_SIZE_VALUE_8BIT; - } else if (size_in_bytes == 2) { - val = SHA256_CSR_DMA_SIZE_VALUE_16BIT; - } else { - val = SHA256_CSR_DMA_SIZE_VALUE_32BIT; - } - hw_write_masked(&sha256_hw->csr, val << SHA256_CSR_DMA_SIZE_LSB, SHA256_CSR_DMA_SIZE_BITS); -} - - -/*! \brief Enable or disable byte swapping of 32-bit values. - * \ingroup hardware_sha256 - * - * The SHA256 algorithm expects bytes in big endian order, but the system bus deals with little endian data, - * so control is provided to convert little endian bus data to big endian internal data. This defaults to true - * - * \param swap false to disable byte swapping - */ -static inline void sha256_set_bswap(bool swap) { - if (swap) { - hw_set_bits(&sha256_hw->csr, SHA256_CSR_BSWAP_BITS); - } else { - hw_clear_bits(&sha256_hw->csr, SHA256_CSR_BSWAP_BITS); - } -} - -/*! \brief Prepare the hardware for a new checksum. - * \ingroup hardware_sha256 - * - * Called to initialise the hardware before starting the checksum calculation - */ -static inline void sha256_start(void) { - hw_set_bits(&sha256_hw->csr, SHA256_CSR_START_BITS); -} - -/*! \brief Check if a valid checksum has been calculated - * \ingroup hardware_sha256 - * - * The checksum result will be invalid when data is first written to the hardware, - * and then once 64 bytes of data has been written it may take some time to complete the digest of the current block. - * This function can be used to determine when the checksum is valid. - * - * \return True if \ref sha256_get_result would return a valid result - */ -static inline bool sha256_is_sum_valid(void) { - return sha256_hw->csr & SHA256_CSR_SUM_VLD_BITS; -} - -/*! \brief Check if a the hardware is ready to accept more data - * \ingroup hardware_sha256 - * - * After writing 64 bytes of data to the hardware, it will be unable to accept more data for a time. - * Call this to check if the hardware is ready for more data to be written. \see sha256_err_not_ready - * - * \return True if the hardware is ready to receive more data - */ -static inline bool sha256_is_ready(void) { - return sha256_hw->csr & SHA256_CSR_WDATA_RDY_BITS; -} - -/*! \brief Wait until the checksum is valid - * \ingroup hardware_sha256 - * - * When a multiple of 64 bytes of data has been written to the hardware, - * the checksum will be valid once the digest of the current block is complete. - * This function waits until when the checksum result is valid. - */ -static inline void sha256_wait_valid_blocking(void) { - while (!sha256_is_sum_valid()) { - tight_loop_contents(); - } -} - -/*! \brief Wait until the hardware is ready to accept more data - * \ingroup hardware_sha256 - * - * Before writing to the hardware, it's necessary to check it is ready to accept more data. - * This function waits until the hardware is ready to accept more data - */ -static inline void sha256_wait_ready_blocking(void) { - while (!sha256_is_ready()) { - tight_loop_contents(); - } -} - -/*! \brief Get the checksum result - * \ingroup hardware_sha256 - * - * Read the 32 byte result calculated by the hardware. Only valid if \ref sha256_is_sum_valid is True - * - * \param out The checksum result - */ -void sha256_get_result(sha256_result_t *out, enum sha256_endianness endianness); - -/*! \brief Check if data was written before the hardware was ready - * \ingroup hardware_sha256 - * - * Indicates if an error has occurred due to data being written when the hardware is not ready. - * - * \return True if data was written before the hardware was ready - */ -static inline bool sha256_err_not_ready(void) { - return sha256_hw->csr & SHA256_CSR_ERR_WDATA_NOT_RDY_BITS; -} - -/*! \brief Clear the "not ready" error condition - * \ingroup hardware_sha256 - * - * Resets the hardware if a "not ready" error condition is indicated. - */ -static inline void sha256_err_not_ready_clear(void) { - hw_clear_bits(&sha256_hw->csr, SHA256_CSR_ERR_WDATA_NOT_RDY_BITS); -} - -/*! \brief Address to write the data to be hashed - * \ingroup hardware_sha256 - * - * Returns the hardware address where data to be hashed should be written - * - * \return Address to write data to be hashed - */ -static inline volatile void *sha256_get_write_addr(void) { - return &sha256_hw->wdata; -} - -/*! \brief Write one 32bit word of data to the SHA-256 hardware - * \ingroup hardware_sha256 - * - * \param word data to write - */ -static inline void sha256_put_word(uint32_t word) { - sha256_hw->wdata = word; -} - -/*! \brief Write one byte of data to the SHA-256 hardware - * \ingroup hardware_sha256 - * - * \param b data to write - */ -static inline void sha256_put_byte(uint8_t b) { - *((io_rw_8*)&sha256_hw->wdata) = b; -} - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/lib/main/pico-sdk/rp2_common/hardware_sha256/sha256.c b/lib/main/pico-sdk/rp2_common/hardware_sha256/sha256.c deleted file mode 100644 index 0d13e3bc2c..0000000000 --- a/lib/main/pico-sdk/rp2_common/hardware_sha256/sha256.c +++ /dev/null @@ -1,15 +0,0 @@ -/** - * Copyright (c) 2024 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "hardware/sha256.h" - -void sha256_get_result(sha256_result_t *out, enum sha256_endianness endianness) { - for (uint i = 0; i < count_of(out->words); i++) { - uint32_t data = sha256_hw->sum[i]; - if (endianness == SHA256_BIG_ENDIAN) data = __builtin_bswap32(data); - out->words[i] = data; - } -} diff --git a/lib/main/pico-sdk/rp2_common/hardware_spi/include/hardware/spi.h b/lib/main/pico-sdk/rp2_common/hardware_spi/include/hardware/spi.h deleted file mode 100644 index 2f3b84e6b2..0000000000 --- a/lib/main/pico-sdk/rp2_common/hardware_spi/include/hardware/spi.h +++ /dev/null @@ -1,436 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _HARDWARE_SPI_H -#define _HARDWARE_SPI_H - -#include "pico.h" -#include "hardware/structs/spi.h" -#include "hardware/regs/dreq.h" - -// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_HARDWARE_SPI, Enable/disable assertions in the hardware_spi module, type=bool, default=0, group=hardware_spi -#ifndef PARAM_ASSERTIONS_ENABLED_HARDWARE_SPI -#ifdef PARAM_ASSERTIONS_ENABLED_SPI // backwards compatibility with SDK < 2.0.0 -#define PARAM_ASSERTIONS_ENABLED_HARDWARE_SPI PARAM_ASSERTIONS_ENABLED_SPI -#else -#define PARAM_ASSERTIONS_ENABLED_HARDWARE_SPI 0 -#endif -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -/** \file hardware/spi.h - * \defgroup hardware_spi hardware_spi - * - * \brief Hardware SPI API - * - * RP-series microcontrollers have 2 identical instances of the Serial Peripheral Interface (SPI) controller. - * - * The PrimeCell SSP is a master or slave interface for synchronous serial communication with peripheral devices that have - * Motorola SPI, National Semiconductor Microwire, or Texas Instruments synchronous serial interfaces. - * - * Controller can be defined as master or slave using the \ref spi_set_slave function. - * - * Each controller can be connected to a number of GPIO pins, see the datasheet GPIO function selection table for more information. - */ - -// PICO_CONFIG: PICO_DEFAULT_SPI, Define the default SPI for a board, min=0, max=1, default=Usually provided via board header, group=hardware_spi -// PICO_CONFIG: PICO_DEFAULT_SPI_SCK_PIN, Define the default SPI SCK pin, min=0, max=29, default=Usually provided via board header, group=hardware_spi -// PICO_CONFIG: PICO_DEFAULT_SPI_TX_PIN, Define the default SPI TX pin, min=0, max=29, default=Usually provided via board header, group=hardware_spi -// PICO_CONFIG: PICO_DEFAULT_SPI_RX_PIN, Define the default SPI RX pin, min=0, max=29, default=Usually provided via board header, group=hardware_spi -// PICO_CONFIG: PICO_DEFAULT_SPI_CSN_PIN, Define the default SPI CSN pin, min=0, max=29, default=Usually provided via board header, group=hardware_spi - -/** - * \brief Opaque type representing an SPI instance. - */ -typedef struct spi_inst spi_inst_t; - -/** Identifier for the first (SPI 0) hardware SPI instance (for use in SPI functions). - * - * e.g. spi_init(spi0, 48000) - * - * \ingroup hardware_spi - */ -#define spi0 ((spi_inst_t *)spi0_hw) - -/** Identifier for the second (SPI 1) hardware SPI instance (for use in SPI functions). - * - * e.g. spi_init(spi1, 48000) - * - * \ingroup hardware_spi - */ -#define spi1 ((spi_inst_t *)spi1_hw) - -/** - * \def PICO_DEFAULT_SPI_INSTANCE() - * \ingroup hardware_spi - * \hideinitializer - * \brief Returns the default SPI instance - */ -#if !defined(PICO_DEFAULT_SPI_INSTANCE) && defined(PICO_DEFAULT_SPI) -#define PICO_DEFAULT_SPI_INSTANCE() (__CONCAT(spi,PICO_DEFAULT_SPI)) -#endif - -/** - * \def PICO_DEFAULT_SPI - * \ingroup hardware_spi - * \hideinitializer - * \brief The default SPI instance number - */ - -/** - * \def PICO_DEFAULT_SPI_INSTANCE() - * \ingroup hardware_spi - * \hideinitializer - * \brief Returns the default SPI instance - */ -#ifdef PICO_DEFAULT_SPI_INSTANCE -#define spi_default PICO_DEFAULT_SPI_INSTANCE() -#endif - -/** - * \def SPI_NUM(spi) - * \ingroup hardware_spi - * \hideinitializer - * \brief Returns the SPI number for a SPI instance - * - * Note this macro is intended to resolve at compile time, and does no parameter checking - */ -#ifndef SPI_NUM -static_assert(NUM_SPIS == 2, ""); -#define SPI_NUM(spi) ((spi) == spi1) -#endif - -/** - * \def SPI_INSTANCE(spi_num) - * \ingroup hardware_spi - * \hideinitializer - * \brief Returns the SPI instance with the given SPI number - * - * Note this macro is intended to resolve at compile time, and does no parameter checking - */ -#ifndef SPI_INSTANCE -static_assert(NUM_SPIS == 2, ""); -#define SPI_INSTANCE(num) ((num) ? spi1 : spi0) -#endif - -/** - * \def SPI_DREQ_NUM(spi, is_tx) - * \ingroup hardware_spi - * \hideinitializer - * \brief Returns the \ref dreq_num_t used for pacing DMA transfers to or from this SPI instance. - * If is_tx is true, then it is for transfers to the SPI else for transfers from the SPI. - * - * Note this macro is intended to resolve at compile time, and does no parameter checking - */ -#ifndef SPI_DREQ_NUM -static_assert(DREQ_SPI0_RX == DREQ_SPI0_TX + 1, ""); -static_assert(DREQ_SPI1_RX == DREQ_SPI1_TX + 1, ""); -static_assert(DREQ_SPI1_TX == DREQ_SPI0_TX + 2, ""); -#define SPI_DREQ_NUM(spi, is_tx) (DREQ_SPI0_TX + SPI_NUM(spi) * 2 + !(is_tx)) -#endif - -/** \brief Enumeration of SPI CPHA (clock phase) values. - * \ingroup hardware_spi - */ -typedef enum { - SPI_CPHA_0 = 0, - SPI_CPHA_1 = 1 -} spi_cpha_t; - -/** \brief Enumeration of SPI CPOL (clock polarity) values. - * \ingroup hardware_spi - */ -typedef enum { - SPI_CPOL_0 = 0, - SPI_CPOL_1 = 1 -} spi_cpol_t; - -/** \brief Enumeration of SPI bit-order values. - * \ingroup hardware_spi - */ -typedef enum { - SPI_LSB_FIRST = 0, - SPI_MSB_FIRST = 1 -} spi_order_t; - -// ---------------------------------------------------------------------------- -// Setup - -/*! \brief Initialise SPI instances - * \ingroup hardware_spi - * - * Puts the SPI into a known state, and enable it. Must be called before other - * functions. - * - * \note There is no guarantee that the baudrate requested can be achieved exactly; the nearest will be chosen - * and returned - * - * \param spi SPI instance specifier, either \ref spi0 or \ref spi1 - * \param baudrate Baudrate requested in Hz - * \return the actual baud rate set - */ -uint spi_init(spi_inst_t *spi, uint baudrate); - -/*! \brief Deinitialise SPI instances - * \ingroup hardware_spi - * - * Puts the SPI into a disabled state. Init will need to be called to re-enable the device - * functions. - * - * \param spi SPI instance specifier, either \ref spi0 or \ref spi1 - */ -void spi_deinit(spi_inst_t *spi); - -/*! \brief Set SPI baudrate - * \ingroup hardware_spi - * - * Set SPI frequency as close as possible to baudrate, and return the actual - * achieved rate. - * - * \param spi SPI instance specifier, either \ref spi0 or \ref spi1 - * \param baudrate Baudrate required in Hz, should be capable of a bitrate of at least 2Mbps, or higher, depending on system clock settings. - * \return The actual baudrate set - */ -uint spi_set_baudrate(spi_inst_t *spi, uint baudrate); - -/*! \brief Get SPI baudrate - * \ingroup hardware_spi - * - * Get SPI baudrate which was set by \see spi_set_baudrate - * - * \param spi SPI instance specifier, either \ref spi0 or \ref spi1 - * \return The actual baudrate set - */ -uint spi_get_baudrate(const spi_inst_t *spi); - -/*! \brief Convert SPI instance to hardware instance number - * \ingroup hardware_spi - * - * \param spi SPI instance - * \return Number of SPI, 0 or 1. - */ -static inline uint spi_get_index(const spi_inst_t *spi) { - invalid_params_if(HARDWARE_SPI, spi != spi0 && spi != spi1); - return SPI_NUM(spi); -} - -static inline spi_hw_t *spi_get_hw(spi_inst_t *spi) { - spi_get_index(spi); // check it is a hw spi - return (spi_hw_t *)spi; -} - -static inline const spi_hw_t *spi_get_const_hw(const spi_inst_t *spi) { - spi_get_index(spi); // check it is a hw spi - return (const spi_hw_t *)spi; -} - -/*! \brief Configure SPI - * \ingroup hardware_spi - * - * Configure how the SPI serialises and deserialises data on the wire - * - * \param spi SPI instance specifier, either \ref spi0 or \ref spi1 - * \param data_bits Number of data bits per transfer. Valid values 4..16. - * \param cpol SSPCLKOUT polarity, applicable to Motorola SPI frame format only. - * \param cpha SSPCLKOUT phase, applicable to Motorola SPI frame format only - * \param order Must be SPI_MSB_FIRST, no other values supported on the PL022 - */ -static inline void spi_set_format(spi_inst_t *spi, uint data_bits, spi_cpol_t cpol, spi_cpha_t cpha, __unused spi_order_t order) { - invalid_params_if(HARDWARE_SPI, data_bits < 4 || data_bits > 16); - // LSB-first not supported on PL022: - invalid_params_if(HARDWARE_SPI, order != SPI_MSB_FIRST); - invalid_params_if(HARDWARE_SPI, cpol != SPI_CPOL_0 && cpol != SPI_CPOL_1); - invalid_params_if(HARDWARE_SPI, cpha != SPI_CPHA_0 && cpha != SPI_CPHA_1); - - // Disable the SPI - uint32_t enable_mask = spi_get_hw(spi)->cr1 & SPI_SSPCR1_SSE_BITS; - hw_clear_bits(&spi_get_hw(spi)->cr1, SPI_SSPCR1_SSE_BITS); - - hw_write_masked(&spi_get_hw(spi)->cr0, - ((uint)(data_bits - 1)) << SPI_SSPCR0_DSS_LSB | - ((uint)cpol) << SPI_SSPCR0_SPO_LSB | - ((uint)cpha) << SPI_SSPCR0_SPH_LSB, - SPI_SSPCR0_DSS_BITS | - SPI_SSPCR0_SPO_BITS | - SPI_SSPCR0_SPH_BITS); - - // Re-enable the SPI - hw_set_bits(&spi_get_hw(spi)->cr1, enable_mask); -} - -/*! \brief Set SPI master/slave - * \ingroup hardware_spi - * - * Configure the SPI for master- or slave-mode operation. By default, - * spi_init() sets master-mode. - * - * \param spi SPI instance specifier, either \ref spi0 or \ref spi1 - * \param slave true to set SPI device as a slave device, false for master. - */ -static inline void spi_set_slave(spi_inst_t *spi, bool slave) { - // Disable the SPI - uint32_t enable_mask = spi_get_hw(spi)->cr1 & SPI_SSPCR1_SSE_BITS; - hw_clear_bits(&spi_get_hw(spi)->cr1, SPI_SSPCR1_SSE_BITS); - - if (slave) - hw_set_bits(&spi_get_hw(spi)->cr1, SPI_SSPCR1_MS_BITS); - else - hw_clear_bits(&spi_get_hw(spi)->cr1, SPI_SSPCR1_MS_BITS); - - // Re-enable the SPI - hw_set_bits(&spi_get_hw(spi)->cr1, enable_mask); -} - -// ---------------------------------------------------------------------------- -// Generic input/output - -/*! \brief Check whether a write can be done on SPI device - * \ingroup hardware_spi - * - * \param spi SPI instance specifier, either \ref spi0 or \ref spi1 - * \return false if no space is available to write. True if a write is possible - */ -static inline bool spi_is_writable(const spi_inst_t *spi) { - return (spi_get_const_hw(spi)->sr & SPI_SSPSR_TNF_BITS); -} - -/*! \brief Check whether a read can be done on SPI device - * \ingroup hardware_spi - * - * \param spi SPI instance specifier, either \ref spi0 or \ref spi1 - * \return true if a read is possible i.e. data is present - */ -static inline bool spi_is_readable(const spi_inst_t *spi) { - return (spi_get_const_hw(spi)->sr & SPI_SSPSR_RNE_BITS); -} - -/*! \brief Check whether SPI is busy - * \ingroup hardware_spi - * - * \param spi SPI instance specifier, either \ref spi0 or \ref spi1 - * \return true if SPI is busy - */ -static inline bool spi_is_busy(const spi_inst_t *spi) { - return (spi_get_const_hw(spi)->sr & SPI_SSPSR_BSY_BITS); -} - -/*! \brief Write/Read to/from an SPI device - * \ingroup hardware_spi - * - * Write \p len bytes from \p src to SPI. Simultaneously read \p len bytes from SPI to \p dst. - * Blocks until all data is transferred. No timeout, as SPI hardware always transfers at a known data rate. - * - * \param spi SPI instance specifier, either \ref spi0 or \ref spi1 - * \param src Buffer of data to write - * \param dst Buffer for read data - * \param len Length of BOTH buffers - * \return Number of bytes written/read -*/ -int spi_write_read_blocking(spi_inst_t *spi, const uint8_t *src, uint8_t *dst, size_t len); - -/*! \brief Write to an SPI device, blocking - * \ingroup hardware_spi - * - * Write \p len bytes from \p src to SPI, and discard any data received back - * Blocks until all data is transferred. No timeout, as SPI hardware always transfers at a known data rate. - * - * \param spi SPI instance specifier, either \ref spi0 or \ref spi1 - * \param src Buffer of data to write - * \param len Length of \p src - * \return Number of bytes written/read - */ -int spi_write_blocking(spi_inst_t *spi, const uint8_t *src, size_t len); - -/*! \brief Read from an SPI device - * \ingroup hardware_spi - * - * Read \p len bytes from SPI to \p dst. - * Blocks until all data is transferred. No timeout, as SPI hardware always transfers at a known data rate. - * \p repeated_tx_data is output repeatedly on TX as data is read in from RX. - * Generally this can be 0, but some devices require a specific value here, - * e.g. SD cards expect 0xff - * - * \param spi SPI instance specifier, either \ref spi0 or \ref spi1 - * \param repeated_tx_data Buffer of data to write - * \param dst Buffer for read data - * \param len Length of buffer \p dst - * \return Number of bytes written/read - */ -int spi_read_blocking(spi_inst_t *spi, uint8_t repeated_tx_data, uint8_t *dst, size_t len); - -// ---------------------------------------------------------------------------- -// SPI-specific operations and aliases - -// FIXME need some instance-private data for select() and deselect() if we are going that route - -/*! \brief Write/Read half words to/from an SPI device - * \ingroup hardware_spi - * - * Write \p len halfwords from \p src to SPI. Simultaneously read \p len halfwords from SPI to \p dst. - * Blocks until all data is transferred. No timeout, as SPI hardware always transfers at a known data rate. - * - * \note SPI should be initialised with 16 data_bits using \ref spi_set_format first, otherwise this function will only read/write 8 data_bits. - * - * \param spi SPI instance specifier, either \ref spi0 or \ref spi1 - * \param src Buffer of data to write - * \param dst Buffer for read data - * \param len Length of BOTH buffers in halfwords - * \return Number of halfwords written/read -*/ -int spi_write16_read16_blocking(spi_inst_t *spi, const uint16_t *src, uint16_t *dst, size_t len); - -/*! \brief Write to an SPI device - * \ingroup hardware_spi - * - * Write \p len halfwords from \p src to SPI. Discard any data received back. - * Blocks until all data is transferred. No timeout, as SPI hardware always transfers at a known data rate. - * - * \note SPI should be initialised with 16 data_bits using \ref spi_set_format first, otherwise this function will only write 8 data_bits. - * - * \param spi SPI instance specifier, either \ref spi0 or \ref spi1 - * \param src Buffer of data to write - * \param len Length of buffers - * \return Number of halfwords written/read -*/ -int spi_write16_blocking(spi_inst_t *spi, const uint16_t *src, size_t len); - -/*! \brief Read from an SPI device - * \ingroup hardware_spi - * - * Read \p len halfwords from SPI to \p dst. - * Blocks until all data is transferred. No timeout, as SPI hardware always transfers at a known data rate. - * \p repeated_tx_data is output repeatedly on TX as data is read in from RX. - * Generally this can be 0, but some devices require a specific value here, - * e.g. SD cards expect 0xff - * - * \note SPI should be initialised with 16 data_bits using \ref spi_set_format first, otherwise this function will only read 8 data_bits. - * - * \param spi SPI instance specifier, either \ref spi0 or \ref spi1 - * \param repeated_tx_data Buffer of data to write - * \param dst Buffer for read data - * \param len Length of buffer \p dst in halfwords - * \return Number of halfwords written/read - */ -int spi_read16_blocking(spi_inst_t *spi, uint16_t repeated_tx_data, uint16_t *dst, size_t len); - -/*! \brief Return the DREQ to use for pacing transfers to/from a particular SPI instance - * \ingroup hardware_spi - * - * \param spi SPI instance specifier, either \ref spi0 or \ref spi1 - * \param is_tx true for sending data to the SPI instance, false for receiving data from the SPI instance - */ -static inline uint spi_get_dreq(spi_inst_t *spi, bool is_tx) { - return SPI_DREQ_NUM(spi, is_tx); -} - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/lib/main/pico-sdk/rp2_common/hardware_spi/spi.c b/lib/main/pico-sdk/rp2_common/hardware_spi/spi.c deleted file mode 100644 index 86c79de9ee..0000000000 --- a/lib/main/pico-sdk/rp2_common/hardware_spi/spi.c +++ /dev/null @@ -1,220 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "hardware/resets.h" -#include "hardware/clocks.h" -#include "hardware/spi.h" - -static inline void spi_reset(spi_inst_t *spi) { - invalid_params_if(HARDWARE_SPI, spi != spi0 && spi != spi1); - reset_block_num(spi == spi0 ? RESET_SPI0 : RESET_SPI1); -} - -static inline void spi_unreset(spi_inst_t *spi) { - invalid_params_if(HARDWARE_SPI, spi != spi0 && spi != spi1); - unreset_block_num_wait_blocking(spi == spi0 ? RESET_SPI0 : RESET_SPI1); -} - -uint spi_init(spi_inst_t *spi, uint baudrate) { - spi_reset(spi); - spi_unreset(spi); - - uint baud = spi_set_baudrate(spi, baudrate); - spi_set_format(spi, 8, SPI_CPOL_0, SPI_CPHA_0, SPI_MSB_FIRST); - // Always enable DREQ signals -- harmless if DMA is not listening - hw_set_bits(&spi_get_hw(spi)->dmacr, SPI_SSPDMACR_TXDMAE_BITS | SPI_SSPDMACR_RXDMAE_BITS); - - // Finally enable the SPI - hw_set_bits(&spi_get_hw(spi)->cr1, SPI_SSPCR1_SSE_BITS); - - return baud; -} - -void spi_deinit(spi_inst_t *spi) { - hw_clear_bits(&spi_get_hw(spi)->cr1, SPI_SSPCR1_SSE_BITS); - hw_clear_bits(&spi_get_hw(spi)->dmacr, SPI_SSPDMACR_TXDMAE_BITS | SPI_SSPDMACR_RXDMAE_BITS); - spi_reset(spi); -} - -uint spi_set_baudrate(spi_inst_t *spi, uint baudrate) { - uint freq_in = clock_get_hz(clk_peri); - uint prescale, postdiv; - invalid_params_if(HARDWARE_SPI, baudrate > freq_in); - - // Disable the SPI - uint32_t enable_mask = spi_get_hw(spi)->cr1 & SPI_SSPCR1_SSE_BITS; - hw_clear_bits(&spi_get_hw(spi)->cr1, SPI_SSPCR1_SSE_BITS); - - // Find smallest prescale value which puts output frequency in range of - // post-divide. Prescale is an even number from 2 to 254 inclusive. - for (prescale = 2; prescale <= 254; prescale += 2) { - if (freq_in < prescale * 256 * (uint64_t) baudrate) - break; - } - invalid_params_if(HARDWARE_SPI, prescale > 254); // Frequency too low - - // Find largest post-divide which makes output <= baudrate. Post-divide is - // an integer in the range 1 to 256 inclusive. - for (postdiv = 256; postdiv > 1; --postdiv) { - if (freq_in / (prescale * (postdiv - 1)) > baudrate) - break; - } - - spi_get_hw(spi)->cpsr = prescale; - hw_write_masked(&spi_get_hw(spi)->cr0, (postdiv - 1) << SPI_SSPCR0_SCR_LSB, SPI_SSPCR0_SCR_BITS); - - // Re-enable the SPI - hw_set_bits(&spi_get_hw(spi)->cr1, enable_mask); - - // Return the frequency we were able to achieve - return freq_in / (prescale * postdiv); -} - -uint spi_get_baudrate(const spi_inst_t *spi) { - uint prescale = spi_get_const_hw(spi)->cpsr; - uint postdiv = ((spi_get_const_hw(spi)->cr0 & SPI_SSPCR0_SCR_BITS) >> SPI_SSPCR0_SCR_LSB) + 1; - return clock_get_hz(clk_peri) / (prescale * postdiv); -} - -// Write len bytes from src to SPI. Simultaneously read len bytes from SPI to dst. -// Note this function is guaranteed to exit in a known amount of time (bits sent * time per bit) -int __not_in_flash_func(spi_write_read_blocking)(spi_inst_t *spi, const uint8_t *src, uint8_t *dst, size_t len) { - invalid_params_if(HARDWARE_SPI, 0 > (int)len); - - // Never have more transfers in flight than will fit into the RX FIFO, - // else FIFO will overflow if this code is heavily interrupted. - const size_t fifo_depth = 8; - size_t rx_remaining = len, tx_remaining = len; - - while (rx_remaining || tx_remaining) { - if (tx_remaining && spi_is_writable(spi) && rx_remaining < tx_remaining + fifo_depth) { - spi_get_hw(spi)->dr = (uint32_t) *src++; - --tx_remaining; - } - if (rx_remaining && spi_is_readable(spi)) { - *dst++ = (uint8_t) spi_get_hw(spi)->dr; - --rx_remaining; - } - } - - return (int)len; -} - -// Write len bytes directly from src to the SPI, and discard any data received back -int __not_in_flash_func(spi_write_blocking)(spi_inst_t *spi, const uint8_t *src, size_t len) { - invalid_params_if(HARDWARE_SPI, 0 > (int)len); - // Write to TX FIFO whilst ignoring RX, then clean up afterward. When RX - // is full, PL022 inhibits RX pushes, and sets a sticky flag on - // push-on-full, but continues shifting. Safe if SSPIMSC_RORIM is not set. - for (size_t i = 0; i < len; ++i) { - while (!spi_is_writable(spi)) - tight_loop_contents(); - spi_get_hw(spi)->dr = (uint32_t)src[i]; - } - // Drain RX FIFO, then wait for shifting to finish (which may be *after* - // TX FIFO drains), then drain RX FIFO again - while (spi_is_readable(spi)) - (void)spi_get_hw(spi)->dr; - while (spi_get_hw(spi)->sr & SPI_SSPSR_BSY_BITS) - tight_loop_contents(); - while (spi_is_readable(spi)) - (void)spi_get_hw(spi)->dr; - - // Don't leave overrun flag set - spi_get_hw(spi)->icr = SPI_SSPICR_RORIC_BITS; - - return (int)len; -} - -// Read len bytes directly from the SPI to dst. -// repeated_tx_data is output repeatedly on SO as data is read in from SI. -// Generally this can be 0, but some devices require a specific value here, -// e.g. SD cards expect 0xff -int __not_in_flash_func(spi_read_blocking)(spi_inst_t *spi, uint8_t repeated_tx_data, uint8_t *dst, size_t len) { - invalid_params_if(HARDWARE_SPI, 0 > (int)len); - const size_t fifo_depth = 8; - size_t rx_remaining = len, tx_remaining = len; - - while (rx_remaining || tx_remaining) { - if (tx_remaining && spi_is_writable(spi) && rx_remaining < tx_remaining + fifo_depth) { - spi_get_hw(spi)->dr = (uint32_t) repeated_tx_data; - --tx_remaining; - } - if (rx_remaining && spi_is_readable(spi)) { - *dst++ = (uint8_t) spi_get_hw(spi)->dr; - --rx_remaining; - } - } - - return (int)len; -} - -// Write len halfwords from src to SPI. Simultaneously read len halfwords from SPI to dst. -int __not_in_flash_func(spi_write16_read16_blocking)(spi_inst_t *spi, const uint16_t *src, uint16_t *dst, size_t len) { - invalid_params_if(HARDWARE_SPI, 0 > (int)len); - // Never have more transfers in flight than will fit into the RX FIFO, - // else FIFO will overflow if this code is heavily interrupted. - const size_t fifo_depth = 8; - size_t rx_remaining = len, tx_remaining = len; - - while (rx_remaining || tx_remaining) { - if (tx_remaining && spi_is_writable(spi) && rx_remaining < tx_remaining + fifo_depth) { - spi_get_hw(spi)->dr = (uint32_t) *src++; - --tx_remaining; - } - if (rx_remaining && spi_is_readable(spi)) { - *dst++ = (uint16_t) spi_get_hw(spi)->dr; - --rx_remaining; - } - } - - return (int)len; -} - -// Write len bytes directly from src to the SPI, and discard any data received back -int __not_in_flash_func(spi_write16_blocking)(spi_inst_t *spi, const uint16_t *src, size_t len) { - invalid_params_if(HARDWARE_SPI, 0 > (int)len); - // Deliberately overflow FIFO, then clean up afterward, to minimise amount - // of APB polling required per halfword - for (size_t i = 0; i < len; ++i) { - while (!spi_is_writable(spi)) - tight_loop_contents(); - spi_get_hw(spi)->dr = (uint32_t)src[i]; - } - - while (spi_is_readable(spi)) - (void)spi_get_hw(spi)->dr; - while (spi_get_hw(spi)->sr & SPI_SSPSR_BSY_BITS) - tight_loop_contents(); - while (spi_is_readable(spi)) - (void)spi_get_hw(spi)->dr; - - // Don't leave overrun flag set - spi_get_hw(spi)->icr = SPI_SSPICR_RORIC_BITS; - - return (int)len; -} - -// Read len halfwords directly from the SPI to dst. -// repeated_tx_data is output repeatedly on SO as data is read in from SI. -int __not_in_flash_func(spi_read16_blocking)(spi_inst_t *spi, uint16_t repeated_tx_data, uint16_t *dst, size_t len) { - invalid_params_if(HARDWARE_SPI, 0 > (int)len); - const size_t fifo_depth = 8; - size_t rx_remaining = len, tx_remaining = len; - - while (rx_remaining || tx_remaining) { - if (tx_remaining && spi_is_writable(spi) && rx_remaining < tx_remaining + fifo_depth) { - spi_get_hw(spi)->dr = (uint32_t) repeated_tx_data; - --tx_remaining; - } - if (rx_remaining && spi_is_readable(spi)) { - *dst++ = (uint16_t) spi_get_hw(spi)->dr; - --rx_remaining; - } - } - - return (int)len; -} diff --git a/lib/main/pico-sdk/rp2_common/hardware_sync/include/hardware/sync.h b/lib/main/pico-sdk/rp2_common/hardware_sync/include/hardware/sync.h deleted file mode 100644 index 474b279361..0000000000 --- a/lib/main/pico-sdk/rp2_common/hardware_sync/include/hardware/sync.h +++ /dev/null @@ -1,343 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _HARDWARE_SYNC_H -#define _HARDWARE_SYNC_H - -#include "pico.h" -#include "hardware/address_mapped.h" - -#ifdef __riscv -#include "hardware/hazard3.h" -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -/** \file hardware/sync.h - * \defgroup hardware_sync hardware_sync - * - * \brief Low level hardware spin locks, barrier and processor event APIs - * - * Spin Locks - * ---------- - * - * The RP-series microcontrollers provide 32 hardware spin locks, which can be used to manage mutually-exclusive access to shared software - * and hardware resources. - * - * Generally each spin lock itself is a shared resource, - * i.e. the same hardware spin lock can be used by multiple higher level primitives (as long as the spin locks are neither held for long periods, nor - * held concurrently with other spin locks by the same core - which could lead to deadlock). A hardware spin lock that is exclusively owned can be used - * individually without more flexibility and without regard to other software. Note that no hardware spin lock may - * be acquired re-entrantly (i.e. hardware spin locks are not on their own safe for use by both thread code and IRQs) however the default spinlock related - * methods here (e.g. \ref spin_lock_blocking) always disable interrupts while the lock is held as use by IRQ handlers and user code is common/desirable, - * and spin locks are only expected to be held for brief periods. - * - * \if rp2350_specific - * RP2350 Warning. Due to erratum RP2350-E2, writes to new SIO registers above an offset of +0x180 alias the spinlocks, causing spurious lock releases. - * This SDK by default uses atomic memory accesses to implement the hardware_sync_spin_lock API, as a workaround on RP2350 A2. - * \endif - * - * The SDK uses the following default spin lock assignments, classifying which spin locks are reserved for exclusive/special purposes - * vs those suitable for more general shared use: - * - * Number (ID) | Description - * :---------: | ----------- - * 0-13 | Currently reserved for exclusive use by the SDK and other libraries. If you use these spin locks, you risk breaking SDK or other library functionality. Each reserved spin lock used individually has its own PICO_SPINLOCK_ID so you can search for those. - * 14,15 | (\ref PICO_SPINLOCK_ID_OS1 and \ref PICO_SPINLOCK_ID_OS2). Currently reserved for exclusive use by an operating system (or other system level software) co-existing with the SDK. - * 16-23 | (\ref PICO_SPINLOCK_ID_STRIPED_FIRST - \ref PICO_SPINLOCK_ID_STRIPED_LAST). Spin locks from this range are assigned in a round-robin fashion via \ref next_striped_spin_lock_num(). These spin locks are shared, but assigning numbers from a range reduces the probability that two higher level locking primitives using _striped_ spin locks will actually be using the same spin lock. - * 24-31 | (\ref PICO_SPINLOCK_ID_CLAIM_FREE_FIRST - \ref PICO_SPINLOCK_ID_CLAIM_FREE_LAST). These are reserved for exclusive use and are allocated on a first come first served basis at runtime via \ref spin_lock_claim_unused() - */ - -// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_HARDWARE_SYNC, Enable/disable assertions in the hardware_sync module, type=bool, default=0, group=hardware_sync -#ifndef PARAM_ASSERTIONS_ENABLED_HARDWARE_SYNC -#ifdef PARAM_ASSERTIONS_ENABLED_SYNC // backwards compatibility with SDK < 2.0.0 -#define PARAM_ASSERTIONS_ENABLED_HARDWARE_SYNC PARAM_ASSERTIONS_ENABLED_SYNC -#else -#define PARAM_ASSERTIONS_ENABLED_HARDWARE_SYNC 0 -#endif -#endif - -/*! \brief Insert a NOP instruction in to the code path. - * \ingroup hardware_sync - * - * NOP does nothing for one cycle. On RP2350 Arm binaries this is forced to be - * a 32-bit instruction to avoid dual-issue of NOPs. - */ -__force_inline static void __nop(void) { -#if !__ARM_ARCH_6M__ -#ifdef __riscv - __asm volatile ("nop"); -#else - __asm volatile ("nop.w"); -#endif -#else - __asm volatile ("nop"); -#endif -} - - -/*! \brief Insert a SEV instruction in to the code path. - * \ingroup hardware_sync - - * The SEV (send event) instruction sends an event to both cores. - */ -#if !__has_builtin(__sev) -__force_inline static void __sev(void) { -#ifdef __riscv - __hazard3_unblock(); -#else - pico_default_asm_volatile ("sev"); -#endif -} -#endif - -/*! \brief Insert a WFE instruction in to the code path. - * \ingroup hardware_sync - * - * The WFE (wait for event) instruction waits until one of a number of - * events occurs, including events signalled by the SEV instruction on either core. - */ -#if !__has_builtin(__wfe) -__force_inline static void __wfe(void) { -#ifdef __riscv - __hazard3_block(); -#else - pico_default_asm_volatile ("wfe"); -#endif -} -#endif - -/*! \brief Insert a WFI instruction in to the code path. - * \ingroup hardware_sync -* - * The WFI (wait for interrupt) instruction waits for a interrupt to wake up the core. - */ -#if !__has_builtin(__wfi) -__force_inline static void __wfi(void) { - pico_default_asm_volatile("wfi"); -} -#endif - -/*! \brief Insert a DMB instruction in to the code path. - * \ingroup hardware_sync - * - * The DMB (data memory barrier) acts as a memory barrier, all memory accesses prior to this - * instruction will be observed before any explicit access after the instruction. - */ -__force_inline static void __dmb(void) { -#ifdef __riscv - __asm volatile ("fence rw, rw" : : : "memory"); -#else - pico_default_asm_volatile ("dmb" : : : "memory"); -#endif -} - -/*! \brief Insert a DSB instruction in to the code path. - * \ingroup hardware_sync - * - * The DSB (data synchronization barrier) acts as a special kind of data - * memory barrier (DMB). The DSB operation completes when all explicit memory - * accesses before this instruction complete. - */ -__force_inline static void __dsb(void) { -#ifdef __riscv - __asm volatile ("fence rw, rw" : : : "memory"); -#else - pico_default_asm_volatile ("dsb" : : : "memory"); -#endif -} - -/*! \brief Insert a ISB instruction in to the code path. - * \ingroup hardware_sync - * - * ISB acts as an instruction synchronization barrier. It flushes the pipeline of the processor, - * so that all instructions following the ISB are fetched from cache or memory again, after - * the ISB instruction has been completed. - */ -__force_inline static void __isb(void) { -#ifdef __riscv - __asm volatile ("fence.i" : : : "memory"); -#else - pico_default_asm_volatile("isb" ::: "memory"); -#endif -} - -/*! \brief Acquire a memory fence - * \ingroup hardware_sync - */ -__force_inline static void __mem_fence_acquire(void) { - // the original code below makes it hard for us to be included from C++ via a header - // which itself is in an extern "C", so just use __dmb instead, which is what - // is required on Cortex M0+ - __dmb(); -//#ifndef __cplusplus -// atomic_thread_fence(memory_order_acquire); -//#else -// std::atomic_thread_fence(std::memory_order_acquire); -//#endif -} - -/*! \brief Release a memory fence - * \ingroup hardware_sync - * - */ -__force_inline static void __mem_fence_release(void) { - // the original code below makes it hard for us to be included from C++ via a header - // which itself is in an extern "C", so just use __dmb instead, which is what - // is required on Cortex M0+ - __dmb(); -//#ifndef __cplusplus -// atomic_thread_fence(memory_order_release); -//#else -// std::atomic_thread_fence(std::memory_order_release); -//#endif -} - -/*! \brief Save and disable interrupts - * \ingroup hardware_sync - * - * \return The prior interrupt enable status for restoration later via restore_interrupts() - */ -__force_inline static uint32_t save_and_disable_interrupts(void) { - uint32_t status; -#ifdef __riscv - pico_default_asm_volatile ( - "csrrci %0, mstatus, 0x8\n" - : "=r" (status) :: "memory" - ); -#else - pico_default_asm_volatile ( - "mrs %0, PRIMASK\n" - "cpsid i" - : "=r" (status) :: "memory"); -#endif - return status; -} - -/*! \brief Restore interrupts to a specified state - * \ingroup hardware_sync - * - * \param status Previous interrupt status from save_and_disable_interrupts() - */ -__force_inline static void restore_interrupts(uint32_t status) { -#ifdef __riscv - __compiler_memory_barrier(); - if (status & 0x8) { - riscv_set_csr(mstatus, 8); - } else { - riscv_clear_csr(mstatus, 8); - } - __compiler_memory_barrier(); -#else - pico_default_asm_volatile ("msr PRIMASK,%0"::"r" (status) : "memory" ); -#endif -} - -/*! \brief Restore interrupts to a specified state with restricted transitions - * \ingroup hardware_sync - * - * This method should only be used when the interrupt state is known to be disabled, - * e.g. when paired with \ref save_and_disable_interrupts() - * - * \param status Previous interrupt status from save_and_disable_interrupts() - */ -__force_inline static void restore_interrupts_from_disabled(uint32_t status) { -#ifdef __riscv - // on RISC-V this can enable interrupts, but not disable interrupts... which - // is the common case and doesn't require a branch - __compiler_memory_barrier(); - riscv_set_csr(mstatus, status & 8); - __compiler_memory_barrier(); -#else - // on ARM, this behaves the same as restore_interrupts() - pico_default_asm_volatile ("msr PRIMASK,%0"::"r" (status) : "memory" ); -#endif -} - -#include "hardware/sync/spin_lock.h" - -/*! \brief Return a spin lock number from the _striped_ range - * \ingroup hardware_sync - * - * Returns a spin lock number in the range PICO_SPINLOCK_ID_STRIPED_FIRST to PICO_SPINLOCK_ID_STRIPED_LAST - * in a round robin fashion. This does not grant the caller exclusive access to the spin lock, so the caller - * must: - * - * -# Abide (with other callers) by the contract of only holding this spin lock briefly (and with IRQs disabled - the default via \ref spin_lock_blocking()), - * and not whilst holding other spin locks. - * -# Be OK with any contention caused by the - brief due to the above requirement - contention with other possible users of the spin lock. - * - * \return lock_num a spin lock number the caller may use (non exclusively) - * \see PICO_SPINLOCK_ID_STRIPED_FIRST - * \see PICO_SPINLOCK_ID_STRIPED_LAST - */ -uint next_striped_spin_lock_num(void); - -/*! \brief Mark a spin lock as used - * \ingroup hardware_sync - * - * Method for cooperative claiming of hardware. Will cause a panic if the spin lock - * is already claimed. Use of this method by libraries detects accidental - * configurations that would fail in unpredictable ways. - * - * \param lock_num the spin lock number - */ -void spin_lock_claim(uint lock_num); - -/*! \brief Mark multiple spin locks as used - * \ingroup hardware_sync - * - * Method for cooperative claiming of hardware. Will cause a panic if any of the spin locks - * are already claimed. Use of this method by libraries detects accidental - * configurations that would fail in unpredictable ways. - * - * \param lock_num_mask Bitfield of all required spin locks to claim (bit 0 == spin lock 0, bit 1 == spin lock 1 etc) - */ -void spin_lock_claim_mask(uint32_t lock_num_mask); - -/*! \brief Mark a spin lock as no longer used - * \ingroup hardware_sync - * - * Method for cooperative claiming of hardware. - * - * \param lock_num the spin lock number to release - */ -void spin_lock_unclaim(uint lock_num); - -/*! \brief Claim a free spin lock - * \ingroup hardware_sync - * - * \param required if true the function will panic if none are available - * \return the spin lock number or -1 if required was false, and none were free - */ -int spin_lock_claim_unused(bool required); - -/*! \brief Determine if a spin lock is claimed - * \ingroup hardware_sync - * - * \param lock_num the spin lock number - * \return true if claimed, false otherwise - * \see spin_lock_claim - * \see spin_lock_claim_mask - */ -bool spin_lock_is_claimed(uint lock_num); - -// no longer use __mem_fence_acquire here, as it is overkill on cortex M0+ -#if PICO_C_COMPILER_IS_GNU -#define remove_volatile_cast(t, x) (t)(x) -#define remove_volatile_cast_no_barrier(t, x) (t)(x) -#else -#define remove_volatile_cast(t, x) ({__compiler_memory_barrier(); Clang_Pragma("clang diagnostic push"); Clang_Pragma("clang diagnostic ignored \"-Wcast-qual\""); (t)(x); Clang_Pragma("clang diagnostic pop"); }) -#define remove_volatile_cast_no_barrier(t, x) ({ Clang_Pragma("clang diagnostic push"); Clang_Pragma("clang diagnostic ignored \"-Wcast-qual\""); (t)(x); Clang_Pragma("clang diagnostic pop"); }) -#endif - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/lib/main/pico-sdk/rp2_common/hardware_sync/sync.c b/lib/main/pico-sdk/rp2_common/hardware_sync/sync.c deleted file mode 100644 index e0fbd2bb2b..0000000000 --- a/lib/main/pico-sdk/rp2_common/hardware_sync/sync.c +++ /dev/null @@ -1,51 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "hardware/sync.h" -#include "hardware/claim.h" - -static_assert(PICO_SPINLOCK_ID_STRIPED_LAST >= PICO_SPINLOCK_ID_STRIPED_FIRST, ""); -static uint8_t striped_spin_lock_num = PICO_SPINLOCK_ID_STRIPED_FIRST; -static uint32_t claimed; - -static void check_lock_num(uint __unused lock_num) { - invalid_params_if(HARDWARE_SYNC, lock_num >= 32); -} - -uint next_striped_spin_lock_num(void) { - uint rc = striped_spin_lock_num++; - if (striped_spin_lock_num > PICO_SPINLOCK_ID_STRIPED_LAST) { - striped_spin_lock_num = PICO_SPINLOCK_ID_STRIPED_FIRST; - } - return rc; -} - -void spin_lock_claim(uint lock_num) { - check_lock_num(lock_num); - hw_claim_or_assert((uint8_t *) &claimed, lock_num, "Spinlock %d is already claimed"); -} - -void spin_lock_claim_mask(uint32_t mask) { - for(uint i = 0; mask; i++, mask >>= 1u) { - if (mask & 1u) spin_lock_claim(i); - } -} - -void spin_lock_unclaim(uint lock_num) { - check_lock_num(lock_num); - spin_unlock_unsafe(spin_lock_instance(lock_num)); - hw_claim_clear((uint8_t *) &claimed, lock_num); -} - -int spin_lock_claim_unused(bool required) { - return hw_claim_unused_from_range((uint8_t*)&claimed, required, PICO_SPINLOCK_ID_CLAIM_FREE_FIRST, PICO_SPINLOCK_ID_CLAIM_FREE_LAST, "No spinlocks are available"); -} - -bool spin_lock_is_claimed(uint lock_num) { - check_lock_num(lock_num); - return hw_is_claimed((uint8_t *) &claimed, lock_num); -} - diff --git a/lib/main/pico-sdk/rp2_common/hardware_sync_spin_lock/include/hardware/sync/spin_lock.h b/lib/main/pico-sdk/rp2_common/hardware_sync_spin_lock/include/hardware/sync/spin_lock.h deleted file mode 100644 index 6885efd795..0000000000 --- a/lib/main/pico-sdk/rp2_common/hardware_sync_spin_lock/include/hardware/sync/spin_lock.h +++ /dev/null @@ -1,352 +0,0 @@ -/* - * Copyright (c) 2024 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _HARDWARE_SYNC_SPIN_LOCK_H -#define _HARDWARE_SYNC_SPIN_LOCK_H - -#include "pico.h" -#include "hardware/sync.h" - -// PICO_CONFIG: PICO_USE_SW_SPIN_LOCKS, Use software implementation for spin locks, type=bool, default=1 on RP2350 due to errata, group=hardware_sync -#ifndef PICO_USE_SW_SPIN_LOCKS -#if PICO_RP2350 -#define PICO_USE_SW_SPIN_LOCKS 1 -#endif -#endif - -// PICO_CONFIG: PICO_SPINLOCK_ID_IRQ, Spinlock ID for IRQ protection, min=0, max=31, default=9, group=hardware_sync -#ifndef PICO_SPINLOCK_ID_IRQ -#define PICO_SPINLOCK_ID_IRQ 9 -#endif - -// PICO_CONFIG: PICO_SPINLOCK_ID_TIMER, Spinlock ID for Timer protection, min=0, max=31, default=10, group=hardware_sync -#ifndef PICO_SPINLOCK_ID_TIMER -#define PICO_SPINLOCK_ID_TIMER 10 -#endif - -// PICO_CONFIG: PICO_SPINLOCK_ID_HARDWARE_CLAIM, Spinlock ID for Hardware claim protection, min=0, max=31, default=11, group=hardware_sync -#ifndef PICO_SPINLOCK_ID_HARDWARE_CLAIM -#define PICO_SPINLOCK_ID_HARDWARE_CLAIM 11 -#endif - -// PICO_CONFIG: PICO_SPINLOCK_ID_RAND, Spinlock ID for Random Number Generator, min=0, max=31, default=12, group=hardware_sync -#ifndef PICO_SPINLOCK_ID_RAND -#define PICO_SPINLOCK_ID_RAND 12 -#endif - -// PICO_CONFIG: PICO_SPINLOCK_ID_ATOMIC, Spinlock ID for atomics, min=0, max=31, default=13, group=hardware_sync -#ifndef PICO_SPINLOCK_ID_ATOMIC -#define PICO_SPINLOCK_ID_ATOMIC 13 -#endif - -// PICO_CONFIG: PICO_SPINLOCK_ID_OS1, First Spinlock ID reserved for use by low level OS style software, min=0, max=31, default=14, group=hardware_sync -#ifndef PICO_SPINLOCK_ID_OS1 -#define PICO_SPINLOCK_ID_OS1 14 -#endif - -// PICO_CONFIG: PICO_SPINLOCK_ID_OS2, Second Spinlock ID reserved for use by low level OS style software, min=0, max=31, default=15, group=hardware_sync -#ifndef PICO_SPINLOCK_ID_OS2 -#define PICO_SPINLOCK_ID_OS2 15 -#endif - -// PICO_CONFIG: PICO_SPINLOCK_ID_STRIPED_FIRST, Lowest Spinlock ID in the 'striped' range, min=0, max=31, default=16, group=hardware_sync -#ifndef PICO_SPINLOCK_ID_STRIPED_FIRST -#define PICO_SPINLOCK_ID_STRIPED_FIRST 16 -#endif - -// PICO_CONFIG: PICO_SPINLOCK_ID_STRIPED_LAST, Highest Spinlock ID in the 'striped' range, min=0, max=31, default=23, group=hardware_sync -#ifndef PICO_SPINLOCK_ID_STRIPED_LAST -#define PICO_SPINLOCK_ID_STRIPED_LAST 23 -#endif - -// PICO_CONFIG: PICO_SPINLOCK_ID_CLAIM_FREE_FIRST, Lowest Spinlock ID in the 'claim free' range, min=0, max=31, default=24, group=hardware_sync -#ifndef PICO_SPINLOCK_ID_CLAIM_FREE_FIRST -#define PICO_SPINLOCK_ID_CLAIM_FREE_FIRST 24 -#endif - -#ifdef PICO_SPINLOCK_ID_CLAIM_FREE_END -#warning PICO_SPINLOCK_ID_CLAIM_FREE_END has been renamed to PICO_SPINLOCK_ID_CLAIM_FREE_LAST -#endif - -// PICO_CONFIG: PICO_SPINLOCK_ID_CLAIM_FREE_LAST, Highest Spinlock ID in the 'claim free' range, min=0, max=31, default=31, group=hardware_sync -#ifndef PICO_SPINLOCK_ID_CLAIM_FREE_LAST -#define PICO_SPINLOCK_ID_CLAIM_FREE_LAST 31 -#endif - -/** \brief A spin lock identifier - * \ingroup hardware_sync - */ -#if !PICO_USE_SW_SPIN_LOCKS -// Hardware lock flag in SIO: -typedef io_rw_32 spin_lock_t; -#else -#ifndef SW_SPIN_LOCK_TYPE -// Byte flag in memory: -#define SW_SPIN_LOCK_TYPE volatile uint8_t -#endif -typedef SW_SPIN_LOCK_TYPE spin_lock_t; -#endif - -#if PICO_USE_SW_SPIN_LOCKS -#ifndef SW_SPIN_LOCK_INSTANCE -#define SW_SPIN_LOCK_INSTANCE(lock_num) ({ \ - extern spin_lock_t _sw_spin_locks[NUM_SPIN_LOCKS]; \ - &_sw_spin_locks[lock_num]; \ - }) -#endif - -#ifndef SW_SPIN_LOCK_NUM -#define SW_SPIN_LOCK_NUM(lock) ({ \ - extern spin_lock_t _sw_spin_locks[NUM_SPIN_LOCKS]; \ - (lock) - _sw_spin_locks; \ - }) -#endif - -#ifndef SW_SPIN_LOCK_IS_LOCKED -#define SW_SPIN_LOCK_IS_LOCKED(lock) ((bool) *(lock)) -#endif - -#ifndef SW_SPIN_LOCK_LOCK -#if __ARM_ARCH_8M_MAIN__ -#define SW_SPIN_LOCK_LOCK(lock) ({ \ - uint32_t _tmp0, _tmp1; \ - pico_default_asm_volatile ( \ - "1:\n" \ - "ldaexb %1, [%2]\n" \ - "movs %0, #1\n" /* fill dependency slot */ \ - "cmp %1, #0\n" \ - /* Immediately retry if lock is seen to be taken */ \ - "bne 1b\n" \ - /* Attempt to claim */ \ - "strexb %1, %0, [%2]\n" \ - "cmp %1, #0\n" \ - /* Claim failed due to intervening write, so retry */ \ - "bne 1b\n" \ - : "=&r" (_tmp0), "=&r" (_tmp1) : "r" (lock) \ - ); \ - __mem_fence_acquire(); \ - }) -#elif __riscv && (defined(__riscv_a) || defined(__riscv_zaamo)) -#define SW_SPIN_LOCK_LOCK(lock) ({ \ - uint32_t _tmp0, _tmp1; \ - pico_default_asm_volatile ( \ - /* Get word address, and bit mask for LSB of the */ \ - /* correct byte within that word -- note shamt is modulo xlen: */ \ - "slli %1, %0, 3\n" \ - "bset %1, zero, %1\n" \ - "andi %0, %0, -4\n" \ - /* Repeatedly set the bit until we see that it was clear at the */ \ - /* point we set it. A set from 0 -> 1 is a successful lock take. */ \ - "1:" \ - "amoor.w.aq %2, %1, (%0)\n" \ - "and %2, %2, %1\n" \ - "bnez %2, 1b\n" \ - : "+r" (lock), "=r" (_tmp0), "=r" (_tmp1) \ - ); \ - __mem_fence_acquire(); \ - }) -#else -#error no SW_SPIN_TRY_LOCK available for PICO_USE_SW_SPIN_LOCK on this platform -#endif -#endif - -#ifndef SW_SPIN_TRY_LOCK -#if __ARM_ARCH_8M_MAIN__ -#define SW_SPIN_TRY_LOCK(lock) ({ \ - uint32_t _tmp0, _tmp1; \ - pico_default_asm_volatile ( \ - "ldaexb %1, [%2]\n" \ - "movs %0, #1\n" /* fill dependency slot */ \ - "cmp %1, #0\n" \ - /* Immediately give up if lock is seen to be taken */ \ - "bne 1f\n" \ - /* Otherwise attempt to claim, once. */ \ - "strexb %1, %0, [%2]\n" \ - "1:\n" \ - : "=&r" (_tmp0), "=&r" (_tmp1) : "r" (lock) \ - ); \ - __mem_fence_acquire(); \ - !_tmp1; \ - }) -#elif __riscv && (defined(__riscv_a) || defined(__riscv_zaamo)) -#define SW_SPIN_TRY_LOCK(lock) ({ \ - uint32_t _tmp0; \ - pico_default_asm_volatile ( \ - /* Get word address, and bit mask for LSB of the */ \ - /* correct byte within that word -- note shamt is modulo xlen: */ \ - "slli %1, %0, 3\n" \ - "bset %1, zero, %1\n" \ - "andi %0, %0, -4\n" \ - /* Set the bit. If it was clear at the point we set it, then we took */ \ - /* the lock. Otherwise the lock was already held, and we give up. */ \ - "amoor.w.aq %0, %1, (%0)\n" \ - "and %1, %1, %0\n" \ - : "+r" (lock), "=r" (_tmp0) \ - ); \ - __mem_fence_acquire(); \ - !_tmp0; \ - }) -#else -#error no SW_SPIN_TRY_LOCK available for PICO_USE_SW_SPIN_LOCK on this platform -#endif -#endif - -#ifndef SW_SPIN_LOCK_UNLOCK -#if __ARM_ARCH_8M_MAIN__ -#define SW_SPIN_LOCK_UNLOCK(lock) ({ \ - /* Release-ordered store is available: use instead of separate fence */ \ - uint32_t zero = 0; \ - pico_default_asm_volatile( \ - "stlb %0, [%1]\n" \ - : : "r" (zero), "r" (lock) \ - ); \ - }) -#elif __riscv -#define SW_SPIN_LOCK_UNLOCK(lock) ({ \ - __mem_fence_release(); \ - *(lock) = 0; /* write to spinlock register (release lock) */ \ - }) -#else -#error no SW_SPIN_TRY_LOCK available for PICO_USE_SW_SPIN_LOCK on this platform -#endif -#endif - -#endif - -/*! \brief Get HW Spinlock instance from number - * \ingroup hardware_sync - * - * \param lock_num Spinlock ID - * \return The spinlock instance - */ -__force_inline static spin_lock_t *spin_lock_instance(uint lock_num) { - invalid_params_if(HARDWARE_SYNC, lock_num >= NUM_SPIN_LOCKS); -#if PICO_USE_SW_SPIN_LOCKS - return SW_SPIN_LOCK_INSTANCE(lock_num); -#else - return (spin_lock_t *) (SIO_BASE + SIO_SPINLOCK0_OFFSET + lock_num * 4); -#endif -} - -/*! \brief Get HW Spinlock number from instance - * \ingroup hardware_sync - * - * \param lock The Spinlock instance - * \return The Spinlock ID - */ -__force_inline static uint spin_lock_get_num(spin_lock_t *lock) { -#if PICO_USE_SW_SPIN_LOCKS - uint lock_num = SW_SPIN_LOCK_NUM(lock); - invalid_params_if(HARDWARE_SYNC, lock_num >= (uint)NUM_SPIN_LOCKS); - return lock_num; -#else - invalid_params_if(HARDWARE_SYNC, (uint) lock < SIO_BASE + SIO_SPINLOCK0_OFFSET || - (uint) lock >= NUM_SPIN_LOCKS * sizeof(spin_lock_t) + SIO_BASE + SIO_SPINLOCK0_OFFSET || - ((uint) lock - SIO_BASE + SIO_SPINLOCK0_OFFSET) % sizeof(spin_lock_t) != 0); - return (uint) (lock - (spin_lock_t *) (SIO_BASE + SIO_SPINLOCK0_OFFSET)); -#endif -} - -/*! \brief Acquire a spin lock without disabling interrupts (hence unsafe) - * \ingroup hardware_sync - * - * \param lock Spinlock instance - */ -__force_inline static void spin_lock_unsafe_blocking(spin_lock_t *lock) { - // Note we don't do a wfe or anything, because by convention these spin_locks are VERY SHORT LIVED and NEVER BLOCK and run - // with INTERRUPTS disabled (to ensure that)... therefore nothing on our core could be blocking us, so we just need to wait on another core - // anyway which should be finished soon -#if PICO_USE_SW_SPIN_LOCKS - SW_SPIN_LOCK_LOCK(lock); -#else - while (__builtin_expect(!*lock, 0)) { // read from spinlock register (tries to acquire the lock) - tight_loop_contents(); - } - __mem_fence_acquire(); -#endif -} - -__force_inline static bool spin_try_lock_unsafe(spin_lock_t *lock) { -#if PICO_USE_SW_SPIN_LOCKS - return SW_SPIN_TRY_LOCK(lock); -#else - return *lock; -#endif -} -/*! \brief Release a spin lock without re-enabling interrupts - * \ingroup hardware_sync - * - * \param lock Spinlock instance - */ -__force_inline static void spin_unlock_unsafe(spin_lock_t *lock) { -#if PICO_USE_SW_SPIN_LOCKS - SW_SPIN_LOCK_UNLOCK(lock); -#else - __mem_fence_release(); - *lock = 0; // write to spinlock register (release lock) -#endif -} - -/*! \brief Acquire a spin lock safely - * \ingroup hardware_sync - * - * This function will disable interrupts prior to acquiring the spinlock - * - * \param lock Spinlock instance - * \return interrupt status to be used when unlocking, to restore to original state - */ -__force_inline static uint32_t spin_lock_blocking(spin_lock_t *lock) { - uint32_t save = save_and_disable_interrupts(); - spin_lock_unsafe_blocking(lock); - return save; -} - -/*! \brief Check to see if a spinlock is currently acquired elsewhere. - * \ingroup hardware_sync - * - * \param lock Spinlock instance - */ -inline static bool is_spin_locked(spin_lock_t *lock) { -#if PICO_USE_SW_SPIN_LOCKS - return SW_SPIN_LOCK_IS_LOCKED(lock); -#else - check_hw_size(spin_lock_t, 4); - uint lock_num = spin_lock_get_num(lock); - return 0 != (*(io_ro_32 *) (SIO_BASE + SIO_SPINLOCK_ST_OFFSET) & (1u << lock_num)); -#endif -} - -/*! \brief Release a spin lock safely - * \ingroup hardware_sync - * - * This function will re-enable interrupts according to the parameters. - * - * \param lock Spinlock instance - * \param saved_irq Return value from the \ref spin_lock_blocking() function. - * - * \sa spin_lock_blocking() - */ -__force_inline static void spin_unlock(spin_lock_t *lock, uint32_t saved_irq) { - spin_unlock_unsafe(lock); - restore_interrupts_from_disabled(saved_irq); -} - -/*! \brief Initialise a spin lock - * \ingroup hardware_sync - * - * The spin lock is initially unlocked - * - * \param lock_num The spin lock number - * \return The spin lock instance - */ -spin_lock_t *spin_lock_init(uint lock_num); - -/*! \brief Release all spin locks - * \ingroup hardware_sync - */ -void spin_locks_reset(void); - -#endif diff --git a/lib/main/pico-sdk/rp2_common/hardware_sync_spin_lock/sync_spin_lock.c b/lib/main/pico-sdk/rp2_common/hardware_sync_spin_lock/sync_spin_lock.c deleted file mode 100644 index 82ac8b9c2f..0000000000 --- a/lib/main/pico-sdk/rp2_common/hardware_sync_spin_lock/sync_spin_lock.c +++ /dev/null @@ -1,44 +0,0 @@ -/* - * Copyright (c) 2024 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#include "hardware/sync/spin_lock.h" - -void spin_locks_reset(void) { - for (uint i = 0; i < NUM_SPIN_LOCKS; i++) { - spin_unlock_unsafe(spin_lock_instance(i)); - } -} - -spin_lock_t *spin_lock_init(uint lock_num) { - assert(lock_num < NUM_SPIN_LOCKS); - spin_lock_t *lock = spin_lock_instance(lock_num); - spin_unlock_unsafe(lock); - return lock; -} - -#if PICO_USE_SW_SPIN_LOCKS -spin_lock_t _sw_spin_locks[NUM_SPIN_LOCKS]; - -#if __ARM_ARCH_8M_MAIN__ && !PICO_SW_SPIN_LOCKS_NO_EXTEXCLALL -#include "pico/runtime_init.h" -#include "hardware/structs/m33.h" - -static void spinlock_set_extexclall(void) { - // Force use of global exclusive monitor for all exclusive load/stores: - // makes multicore exclusives work without adding MPU regions. For - // something more exotic, like having multicore exclusives in internal - // SRAM and also single-core exclusives in external PSRAM (not covered by - // the global monitor on RP2350) you must clear this and add your own - // Shareable regions. - // - // Setting PICO_SW_SPIN_LOCKS_NO_EXTEXCLALL == 1 will disable this code - m33_hw->actlr |= M33_ACTLR_EXTEXCLALL_BITS; -} - -// PICO_RUNTIME_INIT_SPIN_LOCKS_RESET is fine as resetting them does not require EXTEXCLALL -PICO_RUNTIME_INIT_FUNC_PER_CORE(spinlock_set_extexclall, PICO_RUNTIME_INIT_SPIN_LOCKS_RESET); -#endif -#endif - diff --git a/lib/main/pico-sdk/rp2_common/hardware_ticks/include/hardware/ticks.h b/lib/main/pico-sdk/rp2_common/hardware_ticks/include/hardware/ticks.h deleted file mode 100644 index a7c7d59988..0000000000 --- a/lib/main/pico-sdk/rp2_common/hardware_ticks/include/hardware/ticks.h +++ /dev/null @@ -1,78 +0,0 @@ -/* - * Copyright (c) 2024 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _HARDWARE_TICKS_H -#define _HARDWARE_TICKS_H - -/** \file hardware/tick.h - * \defgroup hardware_ticks hardware_ticks - * - * \brief Hardware Tick API - * - * \if rp2040_specific - * RP2040 only has one tick generator, and it is part of the watchdog hardware. - * \endif - * - * \if rp2350_specific - * The RP2350 has a dedicated Tick block that is used to supply ticks to TIMER0, TIMER1, - * RISC-V platform timer, Arm Cortex-M33 0 timer, Arm Cortex-M33 1 timer and the WATCHDOG block. - * \endif - */ - -#include "pico.h" -#if !PICO_RP2040 -#include "hardware/structs/ticks.h" -#else -#include "hardware/watchdog.h" -/*! \brief Tick generator numbers on RP2040 (used as typedef \ref tick_gen_num_t) - * \ingroup hardware_ticks - * - * RP2040 only has one tick generator, and it is part of the watchdog hardware - */ -typedef enum tick_gen_num_rp2040 { - TICK_WATCHDOG = 0, - TICK_COUNT -} tick_gen_num_t; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_HARDWARE_TICKS, Enable/disable assertions in the hardware_ticks module, type=bool, default=0, group=hardware_ticks -#ifndef PARAM_ASSERTIONS_ENABLED_HARDWARE_TICKS -#define PARAM_ASSERTIONS_ENABLED_HARDWARE_TICKS 0 -#endif - -/*! \brief Start a tick generator - * \ingroup hardware_ticks - * - * \param tick The tick generator number - * \param cycles The number of clock cycles per tick - */ -void tick_start(tick_gen_num_t tick, uint cycles); - - -/*! \brief Stop a tick generator - * \ingroup hardware_ticks - * - * \param tick The tick generator number - */ -void tick_stop(tick_gen_num_t tick); - -/*! \brief Check if a tick genererator is currently running - * \ingroup hardware_ticks - * - * \param tick The tick generator number - * \return true if the specific ticker is running. - */ -bool tick_is_running(tick_gen_num_t tick); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/lib/main/pico-sdk/rp2_common/hardware_ticks/ticks.c b/lib/main/pico-sdk/rp2_common/hardware_ticks/ticks.c deleted file mode 100644 index 484602838c..0000000000 --- a/lib/main/pico-sdk/rp2_common/hardware_ticks/ticks.c +++ /dev/null @@ -1,45 +0,0 @@ -/* - * Copyright (c) 2024 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "hardware/ticks.h" - -void tick_start(tick_gen_num_t tick, uint cycles) { - valid_params_if(HARDWARE_TICKS, tick < TICK_COUNT); -#if PICO_RP2040 - ((void)tick); - cycles <<= WATCHDOG_TICK_CYCLES_LSB; - valid_params_if(HARDWARE_TICKS, cycles <= WATCHDOG_TICK_CYCLES_BITS); - // On RP2040, this also provides a tick reference to the timer and SysTick - watchdog_hw->tick = cycles | WATCHDOG_TICK_ENABLE_BITS; -#else - cycles <<= TICKS_WATCHDOG_CYCLES_LSB; - valid_params_if(HARDWARE_TICKS, cycles <= TICKS_WATCHDOG_CYCLES_BITS); - // On later hardware, separate tick generators for every tick destination. - ticks_hw->ticks[tick].cycles = cycles; - ticks_hw->ticks[tick].ctrl = TICKS_WATCHDOG_CTRL_ENABLE_BITS; -#endif -} - -void tick_stop(tick_gen_num_t tick) { - valid_params_if(HARDWARE_TICKS, tick < TICK_COUNT); -#if PICO_RP2040 - ((void)tick); - hw_clear_bits(&watchdog_hw->tick, WATCHDOG_TICK_ENABLE_BITS); -#else - hw_clear_bits(&ticks_hw->ticks[tick].ctrl, TICKS_WATCHDOG_CTRL_ENABLE_BITS); -#endif -} - -bool tick_is_running(tick_gen_num_t tick) { - valid_params_if(HARDWARE_TICKS, tick < TICK_COUNT); -#if PICO_RP2040 - ((void)tick); - return watchdog_hw->tick & WATCHDOG_TICK_ENABLE_BITS; -#else - // On later hardware, separate tick generators for every tick destination. - return ticks_hw->ticks[tick].ctrl & TICKS_WATCHDOG_CTRL_RUNNING_BITS; -#endif -} \ No newline at end of file diff --git a/lib/main/pico-sdk/rp2_common/hardware_timer/include/hardware/timer.h b/lib/main/pico-sdk/rp2_common/hardware_timer/include/hardware/timer.h deleted file mode 100644 index 289a28a34c..0000000000 --- a/lib/main/pico-sdk/rp2_common/hardware_timer/include/hardware/timer.h +++ /dev/null @@ -1,598 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _HARDWARE_TIMER_H -#define _HARDWARE_TIMER_H - -#include "pico.h" -#include "hardware/structs/timer.h" -#include "hardware/regs/intctrl.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** \file hardware/timer.h - * \defgroup hardware_timer hardware_timer - * - * \brief Low-level hardware timer API - * - * This API provides medium level access to the timer HW. - * See also \ref pico_time which provides higher levels functionality using the hardware timer. - * - * The timer peripheral on RP-series microcontrollers supports the following features: - * - RP2040 single 64-bit counter, incrementing once per microsecond - * - RP2350 two 64-bit counters, ticks generated from the tick block - * - Latching two-stage read of counter, for race-free read over 32 bit bus - * - Four alarms: match on the lower 32 bits of counter, IRQ on match. - * - * \if rp2040_specific - * On RP2040, by default the timer uses a one microsecond reference that is generated in the Watchdog (see RP2040 Datasheet Section 4.8.2) which is derived - * from the clk_ref. - * \endif - * - * \if rp2350_specific - * On RP2350, by default the timer uses a one microsecond reference that is generated by the tick block (see RP2350 Datasheet Section 8.5) - * \endif - * - * The timer has 4 alarms, and can output a separate interrupt for each alarm. The alarms match on the lower 32 bits of the 64 - * bit counter which means they can be fired a maximum of 2^32 microseconds into the future. This is equivalent to: - * - 2^32 ÷ 10^6: ~4295 seconds - * - 4295 ÷ 60: ~72 minutes - * - * The timer is expected to be used for short sleeps, if you want a longer alarm see the \ref hardware_rtc functions. - * - * \subsection timer_example Example - * \addtogroup hardware_timer - * - * \include hello_timer.c - * - * \see pico_time - */ - -// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_HARDWARE_TIMER, Enable/disable assertions in the hardware_timer module, type=bool, default=0, group=hardware_timer -#ifndef PARAM_ASSERTIONS_ENABLED_HARDWARE_TIMER -#ifdef PARAM_ASSERTIONS_ENABLED_TIMER // backwards compatibility with SDK < 2.0.0 -#define PARAM_ASSERTIONS_ENABLED_HARDWARE_TIMER PARAM_ASSERTIONS_ENABLED_TIMER -#else -#define PARAM_ASSERTIONS_ENABLED_HARDWARE_TIMER 0 -#endif -#endif - -/** - * \def TIMER_NUM(timer) - * \ingroup hardware_timer - * \hideinitializer - * \brief Returns the timer number for a timer instance - * - * Note this macro is intended to resolve at compile time, and does no parameter checking - */ -#ifndef TIMER_NUM -#if NUM_GENERIC_TIMERS == 1 -#define TIMER_NUM(timer) ({ (void) (timer); 0; }) -#elif NUM_GENERIC_TIMERS == 2 -#define TIMER_NUM(timer) ((timer) == timer1_hw) -#endif -#endif - -/** - * \def TIMER_INSTANCE(timer_num) - * \ingroup hardware_timer - * \hideinitializer - * \brief Returns the timer instance with the given timer number - * - * Note this macro is intended to resolve at compile time, and does no parameter checking - */ -#ifndef TIMER_INSTANCE -#if NUM_GENERIC_TIMERS == 1 -#define TIMER_INSTANCE(num) timer_hw -#elif NUM_GENERIC_TIMERS == 2 -#define TIMER_INSTANCE(num) ((num) ? timer1_hw : timer0_hw) -#endif -#endif - -/** - * \def TIMER_ALARM_IRQ_NUM(timer,alarm_num) - * \ingroup hardware_timer - * \hideinitializer - * \brief Returns the \ref irq_num_t for the alarm interrupt from the given alarm on the given timer instance - * - * Note this macro is intended to resolve at compile time, and does no parameter checking - */ -#ifndef TIMER_ALARM_IRQ_NUM -#if NUM_GENERIC_TIMERS == 1 -static_assert(TIMER_IRQ_3 == TIMER_IRQ_0 + 3, ""); -#define TIMER_ALARM_IRQ_NUM(timer, alarm_num) ({ ((void)(timer)); (TIMER_IRQ_0 + (alarm_num)); }) -#else -static_assert(TIMER1_IRQ_3 == TIMER0_IRQ_0 + 7, ""); -#define TIMER_ALARM_IRQ_NUM(timer, alarm_num) (TIMER0_IRQ_0 + TIMER_NUM(timer) * NUM_ALARMS + (alarm_num)) -#endif -#endif - -/** - * \def TIMER_ALARM_NUM_FROM_IRQ(irq_num) - * \ingroup hardware_timer - * \hideinitializer - * \brief Returns the alarm number from an \ref irq_num_t. See \ref TIMER_INSTANCE_NUM_FROM_IRQ to get the timer instance number - * - * Note this macro is intended to resolve at compile time, and does no parameter checking - */ -#ifndef TIMER_ALARM_NUM_FROM_IRQ -#if NUM_GENERIC_TIMERS == 1 -static_assert(TIMER_IRQ_3 == TIMER_IRQ_0 + 3, ""); -#define TIMER_ALARM_NUM_FROM_IRQ(irq_num) (((irq_num) - TIMER_IRQ_0) & 3u) -#else -static_assert(TIMER1_IRQ_3 == TIMER0_IRQ_0 + 7, ""); -#define TIMER_ALARM_NUM_FROM_IRQ(irq_num) (((irq_num) - TIMER0_IRQ_0) & 3u) -#endif -#endif - -/** - * \def TIMER_NUM_FROM_IRQ(irq_num) - * \ingroup hardware_timer - * \hideinitializer - * \brief Returns the alarm number from an \ref irq_num_t. See \ref TIMER_INSTANCE_NUM_FROM_IRQ to get the alarm number - * - * Note this macro is intended to resolve at compile time, and does no parameter checking - */ -#ifndef TIMER_NUM_FROM_IRQ -#if NUM_GENERIC_TIMERS == 1 -static_assert(TIMER_IRQ_3 == TIMER_IRQ_0 + 3, ""); -#define TIMER_NUM_FROM_IRQ(irq_num) (((irq_num) - TIMER_IRQ_0) >> 2) -#else -static_assert(TIMER1_IRQ_3 == TIMER0_IRQ_0 + 7, ""); -#define TIMER_NUM_FROM_IRQ(irq_num) (((irq_num) - TIMER0_IRQ_0) >> 2) -#endif -#endif - -// PICO_CONFIG: PICO_DEFAULT_TIMER, Timer instance number to use for RP2040-period hardware_timer APIs that assumed a single timer instance, min=0, max=1, default=0, group=hardware_timer - -/** - * \ingroup hardware_timer - * \brief The default timer instance number of the timer instance used for APIs that don't take an explicit timer instance - * \if rp2040_specific - * On RP2040 this must be 0 as there is only one timer instance - * \endif - * \if rp2350_specific - * On RP2040 this may be set to 0 or 1 - * \endif - */ -#ifndef PICO_DEFAULT_TIMER -#define PICO_DEFAULT_TIMER 0 -#endif - -/** - * \def PICO_DEFAULT_TIMER_INSTANCE() - * \ingroup hardware_timer - * \hideinitializer - * \brief Returns the default timer instance on the platform based on the setting of PICO_DEFAULT_TIMER - * - * Note this macro is intended to resolve at compile time, and does no parameter checking - */ -#ifndef PICO_DEFAULT_TIMER_INSTANCE -#if NUM_GENERIC_TIMERS == 1 -#if PICO_DEFAULT_TIMER -#error Setting PICO_DEFAULT_TIMER to non zero is meaningless as there is only one TIMER instance on this platform -#endif -#define PICO_DEFAULT_TIMER_INSTANCE() timer_hw -#else -#define PICO_DEFAULT_TIMER_INSTANCE() (__CONCAT(__CONCAT(timer,PICO_DEFAULT_TIMER), _hw)) -// also define timer_hw for backwards compatibility (just accesses the default instance) -#define timer_hw PICO_DEFAULT_TIMER_INSTANCE() -#endif -#endif - -static inline void check_hardware_alarm_num_param(__unused uint alarm_num) { - invalid_params_if(HARDWARE_TIMER, alarm_num >= NUM_ALARMS); -} - -/*! \brief Return a 32 bit timestamp value in microseconds for a given timer instance -* \ingroup hardware_timer -* -* Returns the low 32 bits of the hardware timer. -* \note This value wraps roughly every 1 hour 11 minutes and 35 seconds. -* -* \param timer the timer instance -* \return the 32 bit timestamp -* \sa time_us_32 -*/ -static inline uint32_t timer_time_us_32(timer_hw_t *timer) { - return timer->timerawl; -} - -/*! \brief Return a 32 bit timestamp value in microseconds for the default timer instance -* \ingroup hardware_timer -* -* Returns the low 32 bits of the hardware timer. -* \note This value wraps roughly every 1 hour 11 minutes and 35 seconds. -* -* \return the 32 bit timestamp -* \sa timer_time_us_32 -*/ -static inline uint32_t time_us_32(void) { - return timer_time_us_32(PICO_DEFAULT_TIMER_INSTANCE()); -} - -/*! \brief Return the current 64 bit timestamp value in microseconds for a given timer instance -* \ingroup hardware_timer -* -* Returns the full 64 bits of the hardware timer. The \ref pico_time and other functions rely on the fact that this -* value monotonically increases from power up. As such it is expected that this value counts upwards and never wraps -* (we apologize for introducing a potential year 5851444 bug). -* -* \param timer the timer instance -* \return the 64 bit timestamp -* \sa time_us_64 -*/ -uint64_t timer_time_us_64(timer_hw_t *timer); - -/*! \brief Return the current 64 bit timestamp value in microseconds for the default timer instance -* \ingroup hardware_timer -* -* Returns the full 64 bits of the hardware timer. The \ref pico_time and other functions rely on the fact that this -* value monotonically increases from power up. As such it is expected that this value counts upwards and never wraps -* (we apologize for introducing a potential year 5851444 bug). -* -* \return the 64 bit timestamp -* \sa timer_time_us_64 -* */ -uint64_t time_us_64(void); - -/*! \brief Busy wait wasting cycles for the given (32 bit) number of microseconds using the given timer instance - * \ingroup hardware_timer - * - * \param timer the timer instance - * \param delay_us delay amount in microseconds - * \sa busy_wait_us_32 - */ -void timer_busy_wait_us_32(timer_hw_t *timer, uint32_t delay_us); - -/*! \brief Busy wait wasting cycles for the given (32 bit) number of microseconds using the default timer instance - * \ingroup hardware_timer - * - * \param delay_us delay amount in microseconds - * \sa timer_busy_wait_us_32 - */ -void busy_wait_us_32(uint32_t delay_us); - -/*! \brief Busy wait wasting cycles for the given (64 bit) number of microseconds using the given timer instance - * \ingroup hardware_timer - * - * \param timer the timer instance - * \param delay_us delay amount in microseconds - * \sa busy_wait_us - */ -void timer_busy_wait_us(timer_hw_t *timer, uint64_t delay_us); - -/*! \brief Busy wait wasting cycles for the given (64 bit) number of microseconds using the default timer instance - * \ingroup hardware_timer - * - * \param delay_us delay amount in microseconds - * \sa timer_busy_wait_us - */ -void busy_wait_us(uint64_t delay_us); - -/*! \brief Busy wait wasting cycles for the given number of milliseconds using the given timer instance - * \ingroup hardware_timer - * - * \param timer the timer instance - * \param delay_ms delay amount in milliseconds - * \sa busy_wait_ms - */ -void timer_busy_wait_ms(timer_hw_t *timer, uint32_t delay_ms); - -/*! \brief Busy wait wasting cycles for the given number of milliseconds using the default timer instance - * \ingroup hardware_timer - * - * \param delay_ms delay amount in milliseconds - * \sa timer_busy_wait_ms - */ -void busy_wait_ms(uint32_t delay_ms); - -/*! \brief Busy wait wasting cycles until after the specified timestamp using the given timer instance - * \ingroup hardware_timer - * - * \param timer the timer instance - * \param t Absolute time to wait until - * \sa busy_wait_until - */ -void timer_busy_wait_until(timer_hw_t *timer, absolute_time_t t); - -/*! \brief Busy wait wasting cycles until after the specified timestamp using the default timer instance - * \ingroup hardware_timer - * - * \param t Absolute time to wait until - * \sa timer_busy_wait_until - */ -void busy_wait_until(absolute_time_t t); - -/*! \brief Check if the specified timestamp has been reached on the given timer instance - * \ingroup hardware_timer - * - * \param timer the timer instance - * \param t Absolute time to compare against current time - * \return true if it is now after the specified timestamp - * \sa time_reached - */ -static inline bool timer_time_reached(timer_hw_t *timer, absolute_time_t t) { - uint64_t target = to_us_since_boot(t); - uint32_t hi_target = (uint32_t)(target >> 32u); - uint32_t hi = timer->timerawh; - return (hi >= hi_target && (timer->timerawl >= (uint32_t) target || hi != hi_target)); -} - -/*! \brief Check if the specified timestamp has been reached on the default timer instance - * \ingroup hardware_timer - * - * \param t Absolute time to compare against current time - * \return true if it is now after the specified timestamp - * \sa timer_time_reached - */ -static inline bool time_reached(absolute_time_t t) { - return timer_time_reached(PICO_DEFAULT_TIMER_INSTANCE(), t); -} - -/*! Callback function type for hardware alarms - * \ingroup hardware_timer - * - * \param alarm_num the hardware alarm number - * \sa hardware_alarm_set_callback() - */ -typedef void (*hardware_alarm_callback_t)(uint alarm_num); - -/*! \brief cooperatively claim the use of this hardware alarm_num on the given timer instance - * \ingroup hardware_timer - * - * This method hard asserts if the hardware alarm is currently claimed. - * - * \param timer the timer instance - * \param alarm_num the hardware alarm to claim - * \sa hardware_alarm_claim - * \sa hardware_claiming - */ -void timer_hardware_alarm_claim(timer_hw_t *timer, uint alarm_num); - -/*! \brief cooperatively claim the use of this hardware alarm_num on the default timer instance - * \ingroup hardware_timer - * - * This method hard asserts if the hardware alarm is currently claimed. - * - * \param alarm_num the hardware alarm to claim - * \sa timer_hardware_alarm_claim - * \sa hardware_claiming - */ -void hardware_alarm_claim(uint alarm_num); - -/*! \brief cooperatively claim the use of a hardware alarm_num on the given timer instance - * \ingroup hardware_timer - * - * This method attempts to claim an unused hardware alarm - * - * \param timer the timer instance - * \param required if true the function will panic if none are available - * \return alarm_num the hardware alarm claimed or -1 if required was false, and none are available - * \sa hardware_alarm_claim_unused - * \sa hardware_claiming - */ -int timer_hardware_alarm_claim_unused(timer_hw_t *timer, bool required); - -/*! \brief cooperatively claim the use of a hardware alarm_num on the default timer instance - * \ingroup hardware_timer - * - * This method attempts to claim an unused hardware alarm - * - * \param required if true the function will panic if none are available - * \return alarm_num the hardware alarm claimed or -1 if required was false, and none are available - * \sa timer_hardware_alarm_claim_unused - * \sa hardware_claiming - */ -int hardware_alarm_claim_unused(bool required); - -/*! \brief cooperatively release the claim on use of this hardware alarm_num on the given timer instance - * \ingroup hardware_timer - * - * \param timer the timer instance - * \param alarm_num the hardware alarm to unclaim - * \sa hardware_alarm_unclaim - * \sa hardware_claiming - */ -void timer_hardware_alarm_unclaim(timer_hw_t *timer, uint alarm_num); - -/*! \brief cooperatively release the claim on use of this hardware alarm_num on the default timer instance - * \ingroup hardware_timer - * - * \param alarm_num the hardware alarm to unclaim - * \sa timer_hardware_alarm_unclaim - * \sa hardware_claiming - */ -void hardware_alarm_unclaim(uint alarm_num); - -/*! \brief Determine if a hardware alarm has been claimed on the given timer instance - * \ingroup hardware_timer - * - * \param timer the timer instance - * \param alarm_num the hardware alarm number - * \return true if claimed, false otherwise - * \sa hardware_alarm_is_claimed - * \sa hardware_alarm_claim - */ -bool timer_hardware_alarm_is_claimed(timer_hw_t *timer, uint alarm_num); - -/*! \brief Determine if a hardware alarm has been claimed on the default timer instance - * \ingroup hardware_timer - * - * \param alarm_num the hardware alarm number - * \return true if claimed, false otherwise - * \sa timer_hardware_alarm_is_claimed - * \sa hardware_alarm_claim - */ -bool hardware_alarm_is_claimed(uint alarm_num); - -/*! \brief Enable/Disable a callback for a hardware alarm for a given timer instance on this core - * \ingroup hardware_timer - * - * This method enables/disables the alarm IRQ for the specified hardware alarm on the - * calling core, and set the specified callback to be associated with that alarm. - * - * This callback will be used for the timeout set via hardware_alarm_set_target - * - * \note This will install the handler on the current core if the IRQ handler isn't already set. - * Therefore the user has the opportunity to call this up from the core of their choice - * - * \param timer the timer instance - * \param alarm_num the hardware alarm number - * \param callback the callback to install, or NULL to unset - * - * \sa hardware_alarm_set_callback - * \sa timer_hardware_alarm_set_target() - */ -void timer_hardware_alarm_set_callback(timer_hw_t *timer, uint alarm_num, hardware_alarm_callback_t callback); - -/*! \brief Enable/Disable a callback for a hardware alarm on the default timer instance on this core - * \ingroup hardware_timer - * - * This method enables/disables the alarm IRQ for the specified hardware alarm on the - * calling core, and set the specified callback to be associated with that alarm. - * - * This callback will be used for the timeout set via hardware_alarm_set_target - * - * \note This will install the handler on the current core if the IRQ handler isn't already set. - * Therefore the user has the opportunity to call this up from the core of their choice - * - * \param alarm_num the hardware alarm number - * \param callback the callback to install, or NULL to unset - * - * \sa timer_hardware_alarm_set_callback - * \sa hardware_alarm_set_target() - */ -void hardware_alarm_set_callback(uint alarm_num, hardware_alarm_callback_t callback); - -/** - * \brief Set the current target for a specific hardware alarm on the given timer instance - * \ingroup hardware_timer - * - * This will replace any existing target - * - * \param timer the timer instance - * \param alarm_num the hardware alarm number - * \param t the target timestamp - * \return true if the target was "missed"; i.e. it was in the past, or occurred before a future hardware timeout could be set - * \sa hardware_alarm_set_target - */ -bool timer_hardware_alarm_set_target(timer_hw_t *timer, uint alarm_num, absolute_time_t t); - -/** - * \brief Set the current target for the specified hardware alarm on the default timer instance - * \ingroup hardware_timer - * - * This will replace any existing target - * - * \param alarm_num the hardware alarm number - * \param t the target timestamp - * \return true if the target was "missed"; i.e. it was in the past, or occurred before a future hardware timeout could be set - * \sa timer_hardware_alarm_set_target - */ -bool hardware_alarm_set_target(uint alarm_num, absolute_time_t t); - -/** - * \brief Cancel an existing target (if any) for a specific hardware_alarm on the given timer instance - * \ingroup hardware_timer - * - * \param timer the timer instance - * \param alarm_num the hardware alarm number - * \sa hardware_alarm_cancel - */ -void timer_hardware_alarm_cancel(timer_hw_t *timer, uint alarm_num); - -/** - * \brief Cancel an existing target (if any) for the specified hardware_alarm on the default timer instance - * \ingroup hardware_timer - * - * \param alarm_num the hardware alarm number - * \sa timer_hardware_alarm_cancel - */ -void hardware_alarm_cancel(uint alarm_num); - -/** - * \brief Force and IRQ for a specific hardware alarm on the given timer instance - * \ingroup hardware_timer - * - * This method will forcibly make sure the current alarm callback (if present) for the hardware - * alarm is called from an IRQ context after this call. If an actual callback is due at the same - * time then the callback may only be called once. - * - * Calling this method does not otherwise interfere with regular callback operations. - * - * \param timer the timer instance - * \param alarm_num the hardware alarm number - * \sa hardware_alarm_force_irq - */ -void timer_hardware_alarm_force_irq(timer_hw_t *timer, uint alarm_num); - -/** - * \brief Force and IRQ for a specific hardware alarm on the default timer instance - * \ingroup hardware_timer - * - * This method will forcibly make sure the current alarm callback (if present) for the hardware - * alarm is called from an IRQ context after this call. If an actual callback is due at the same - * time then the callback may only be called once. - * - * Calling this method does not otherwise interfere with regular callback operations. - * - * \param alarm_num the hardware alarm number - * \sa timer_hardware_alarm_force_irq - */ -void hardware_alarm_force_irq(uint alarm_num); - -/** - * \ingroup hardware_timer - * \brief Returns the \ref irq_num_t for the alarm interrupt from the given alarm on the given timer instance - * \param timer the timer instance - * \param alarm_num the alarm number - * \sa TIMER_ALARM_IRQ_NUM - */ -static inline uint timer_hardware_alarm_get_irq_num(timer_hw_t *timer, uint alarm_num) { - check_hardware_alarm_num_param(alarm_num); - return TIMER_ALARM_IRQ_NUM(timer, alarm_num); -} - -/** - * \ingroup hardware_timer - * \brief Returns the \ref irq_num_t for the alarm interrupt from the given alarm on the default timer instance - * \param alarm_num the alarm number - */ -static inline uint hardware_alarm_get_irq_num(uint alarm_num) { - return timer_hardware_alarm_get_irq_num(PICO_DEFAULT_TIMER_INSTANCE(), alarm_num); -} - -/** - * \ingroup hardware_timer - * \brief Returns the timer number for a timer instance - * - * \param timer the timer instance - * \return the timer number - * \sa TIMER_NUM - */ -static inline uint timer_get_index(timer_hw_t *timer) { - return TIMER_NUM(timer); -} - -/** - * \ingroup hardware_timer - * \brief Returns the timer instance with the given timer number - * - * \param timer_num the timer number - * \return the timer instance - */ -static inline timer_hw_t *timer_get_instance(uint timer_num) { - invalid_params_if(HARDWARE_TIMER, timer_num >= NUM_GENERIC_TIMERS); - return TIMER_INSTANCE(timer_num); -} - -#ifdef __cplusplus -} -#endif -#endif diff --git a/lib/main/pico-sdk/rp2_common/hardware_timer/timer.c b/lib/main/pico-sdk/rp2_common/hardware_timer/timer.c deleted file mode 100644 index 0d8dc32c7a..0000000000 --- a/lib/main/pico-sdk/rp2_common/hardware_timer/timer.c +++ /dev/null @@ -1,295 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "hardware/timer.h" -#include "hardware/irq.h" -#include "hardware/sync.h" -#include "hardware/claim.h" - -check_hw_layout(timer_hw_t, ints, TIMER_INTS_OFFSET); - -static hardware_alarm_callback_t alarm_callbacks[NUM_GENERIC_TIMERS][NUM_ALARMS]; -static uint32_t target_hi[NUM_GENERIC_TIMERS][NUM_ALARMS]; -static uint8_t timer_callbacks_pending[NUM_GENERIC_TIMERS]; - -static_assert(NUM_ALARMS * NUM_GENERIC_TIMERS <= 8, ""); -static uint8_t claimed[NUM_GENERIC_TIMERS]; - -void timer_hardware_alarm_claim(timer_hw_t *timer, uint alarm_num) { - check_hardware_alarm_num_param(alarm_num); - hw_claim_or_assert(&claimed[timer_get_index(timer)], alarm_num, "Hardware alarm %d already claimed"); -} - -void hardware_alarm_claim(uint alarm_num) { - timer_hardware_alarm_claim(PICO_DEFAULT_TIMER_INSTANCE(), alarm_num); -} - -void timer_hardware_alarm_unclaim(timer_hw_t *timer, uint alarm_num) { - check_hardware_alarm_num_param(alarm_num); - hw_claim_clear(&claimed[timer_get_index(timer)], alarm_num); -} - -void hardware_alarm_unclaim(uint alarm_num) { - timer_hardware_alarm_unclaim(PICO_DEFAULT_TIMER_INSTANCE(), alarm_num); -} - -bool timer_hardware_alarm_is_claimed(timer_hw_t *timer, uint alarm_num) { - check_hardware_alarm_num_param(alarm_num); - return hw_is_claimed(&claimed[timer_get_index(timer)], alarm_num); -} - -bool hardware_alarm_is_claimed(uint alarm_num) { - return timer_hardware_alarm_is_claimed(PICO_DEFAULT_TIMER_INSTANCE(), alarm_num); -} - -int timer_hardware_alarm_claim_unused(timer_hw_t *timer, bool required) { - return hw_claim_unused_from_range(&claimed[timer_get_index(timer)], required, 0, NUM_ALARMS - 1, "No alarms available"); -} - -int hardware_alarm_claim_unused(bool required) { - return timer_hardware_alarm_claim_unused(PICO_DEFAULT_TIMER_INSTANCE(), required); -} - -/// tag::time_us_64[] -uint64_t timer_time_us_64(timer_hw_t *timer) { - // Need to make sure that the upper 32 bits of the timer - // don't change, so read that first - uint32_t hi = timer->timerawh; - uint32_t lo; - do { - // Read the lower 32 bits - lo = timer->timerawl; - // Now read the upper 32 bits again and - // check that it hasn't incremented. If it has loop around - // and read the lower 32 bits again to get an accurate value - uint32_t next_hi = timer->timerawh; - if (hi == next_hi) break; - hi = next_hi; - } while (true); - return ((uint64_t) hi << 32u) | lo; -} -/// end::time_us_64[] - -/// \tag::busy_wait[] -void timer_busy_wait_us_32(timer_hw_t *timer, uint32_t delay_us) { - if (0 <= (int32_t)delay_us) { - // we only allow 31 bits, otherwise we could have a race in the loop below with - // values very close to 2^32 - uint32_t start = timer->timerawl; - while (timer->timerawl - start < delay_us) { - tight_loop_contents(); - } - } else { - busy_wait_us(delay_us); - } -} - -void timer_busy_wait_us(timer_hw_t *timer, uint64_t delay_us) { - uint64_t base = timer_time_us_64(timer); - uint64_t target = base + delay_us; - if (target < base) { - target = (uint64_t)-1; - } - absolute_time_t t; - update_us_since_boot(&t, target); - timer_busy_wait_until(timer, t); -} - -void timer_busy_wait_ms(timer_hw_t *timer, uint32_t delay_ms) -{ - if (delay_ms <= 0x7fffffffu / 1000) { - timer_busy_wait_us_32(timer, delay_ms * 1000); - } else { - timer_busy_wait_us(timer, delay_ms * 1000ull); - } -} - -void timer_busy_wait_until(timer_hw_t *timer, absolute_time_t t) { - uint64_t target = to_us_since_boot(t); - uint32_t hi_target = (uint32_t)(target >> 32u); - uint32_t hi = timer->timerawh; - while (hi < hi_target) { - hi = timer->timerawh; - tight_loop_contents(); - } - while (hi == hi_target && timer->timerawl < (uint32_t) target) { - hi = timer->timerawh; - tight_loop_contents(); - } -} -/// \end::busy_wait[] - -uint64_t time_us_64(void) { - return timer_time_us_64(PICO_DEFAULT_TIMER_INSTANCE()); -} - -void busy_wait_us_32(uint32_t delay_us) { - timer_busy_wait_us_32(PICO_DEFAULT_TIMER_INSTANCE(), delay_us); -} - -void busy_wait_us(uint64_t delay_us) { - timer_busy_wait_us(PICO_DEFAULT_TIMER_INSTANCE(), delay_us); -} - -void busy_wait_ms(uint32_t delay_ms) -{ - timer_busy_wait_ms(PICO_DEFAULT_TIMER_INSTANCE(), delay_ms); -} - -void busy_wait_until(absolute_time_t t) { - timer_busy_wait_until(PICO_DEFAULT_TIMER_INSTANCE(), t); -} - -static void hardware_alarm_irq_handler(void) { - // Determine which timer this IRQ is for - uint irq_num = __get_current_exception() - VTABLE_FIRST_IRQ; - uint alarm_num = TIMER_ALARM_NUM_FROM_IRQ(irq_num); - check_hardware_alarm_num_param(alarm_num); - uint timer_num = TIMER_NUM_FROM_IRQ(irq_num); - timer_hw_t *timer = timer_get_instance(timer_num); - hardware_alarm_callback_t callback = NULL; - - spin_lock_t *lock = spin_lock_instance(PICO_SPINLOCK_ID_TIMER); - uint32_t save = spin_lock_blocking(lock); - - // Clear the timer IRQ (inside lock, because we check whether we have handled the IRQ yet in alarm_set by looking at the interrupt status - timer->intr = 1u << alarm_num; - // Clear any forced IRQ - hw_clear_bits(&timer->intf, 1u << alarm_num); - - // make sure the IRQ is still valid - if (timer_callbacks_pending[timer_num] & (1u << alarm_num)) { - // Now check whether we have a timer event to handle that isn't already obsolete (this could happen if we - // were already in the IRQ handler before someone else changed the timer setup - if (timer->timerawh >= target_hi[timer_num][alarm_num]) { - // we have reached the right high word as well as low word value - callback = alarm_callbacks[timer_num][alarm_num]; - timer_callbacks_pending[timer_num] &= (uint8_t)~(1u << alarm_num); - } else { - // try again in 2^32 us - timer->alarm[alarm_num] = timer->alarm[alarm_num]; // re-arm the timer - } - } - - spin_unlock(lock, save); - - if (callback) { - callback(alarm_num); - } -} - -void timer_hardware_alarm_set_callback(timer_hw_t *timer, uint alarm_num, hardware_alarm_callback_t callback) { - // todo check current core owner - // note this should probably be subsumed by irq_set_exclusive_handler anyway, since that - // should disallow IRQ handlers on both cores - check_hardware_alarm_num_param(alarm_num); - uint timer_num = timer_get_index(timer); - uint irq_num = TIMER_ALARM_IRQ_NUM(timer, alarm_num); - spin_lock_t *lock = spin_lock_instance(PICO_SPINLOCK_ID_TIMER); - uint32_t save = spin_lock_blocking(lock); - if (callback) { - if (hardware_alarm_irq_handler != irq_get_vtable_handler(irq_num)) { - // note that set_exclusive will silently allow you to set the handler to the same thing - // since it is idempotent, which means we don't need to worry about locking ourselves - irq_set_exclusive_handler(irq_num, hardware_alarm_irq_handler); - irq_set_enabled(irq_num, true); - // Enable interrupt in block and at processor - hw_set_bits(&timer->inte, 1u << alarm_num); - } - alarm_callbacks[timer_num][alarm_num] = callback; - } else { - alarm_callbacks[timer_num][alarm_num] = NULL; - timer_callbacks_pending[timer_num] &= (uint8_t)~(1u << alarm_num); - irq_remove_handler(irq_num, hardware_alarm_irq_handler); - irq_set_enabled(irq_num, false); - } - spin_unlock(lock, save); -} - -void hardware_alarm_set_callback(uint alarm_num, hardware_alarm_callback_t callback) { - timer_hardware_alarm_set_callback(PICO_DEFAULT_TIMER_INSTANCE(), alarm_num, callback); -} - -bool timer_hardware_alarm_set_target(timer_hw_t *timer, uint alarm_num, absolute_time_t target) { - bool missed; - uint64_t now = timer_time_us_64(timer); - uint64_t t = to_us_since_boot(target); - if (now >= t) { - missed = true; - } else { - missed = false; - uint timer_num = timer_get_index(timer); - - // 1) actually set the hardware timer - spin_lock_t *lock = spin_lock_instance(PICO_SPINLOCK_ID_TIMER); - uint32_t save = spin_lock_blocking(lock); - uint8_t old_timer_callbacks_pending = timer_callbacks_pending[timer_num]; - timer_callbacks_pending[timer_num] |= (uint8_t)(1u << alarm_num); - timer->intr = 1u << alarm_num; // clear any IRQ - timer->alarm[alarm_num] = (uint32_t) t; - // Set the alarm. Writing time should arm it - target_hi[timer_num][alarm_num] = (uint32_t)(t >> 32u); - - // 2) check for races - if (!(timer->armed & 1u << alarm_num)) { - // not armed, so has already fired .. IRQ must be pending (we are still under lock) - assert(timer->ints & 1u << alarm_num); - } else { - if (timer_time_us_64(timer) >= t) { - // we are already at or past the right time; there is no point in us racing against the IRQ - // we are about to generate. note however that, if there was already a timer pending before, - // then we still let the IRQ fire, as whatever it was, is not handled by our setting missed=true here - missed = true; - if (timer_callbacks_pending[timer_num] != old_timer_callbacks_pending) { - // disarm the timer - timer->armed = 1u << alarm_num; - // clear the IRQ... - timer->intr = 1u << alarm_num; - // ... including anything pending on the processor - perhaps unnecessary, but - // our timer flag says we aren't expecting anything. - irq_clear(timer_hardware_alarm_get_irq_num(timer, alarm_num)); - // and clear our flag so that if the IRQ handler is already active (because it is on - // the other core) it will also skip doing anything - timer_callbacks_pending[timer_num] = old_timer_callbacks_pending; - } - } - } - spin_unlock(lock, save); - // note at this point any pending timer IRQ can likely run - } - return missed; -} - -bool hardware_alarm_set_target(uint alarm_num, absolute_time_t t) { - return timer_hardware_alarm_set_target(PICO_DEFAULT_TIMER_INSTANCE(), alarm_num, t); -} - -void timer_hardware_alarm_cancel(timer_hw_t *timer, uint alarm_num) { - check_hardware_alarm_num_param(alarm_num); - - spin_lock_t *lock = spin_lock_instance(PICO_SPINLOCK_ID_TIMER); - uint32_t save = spin_lock_blocking(lock); - timer->armed = 1u << alarm_num; - timer_callbacks_pending[timer_get_index(timer)] &= (uint8_t)~(1u << alarm_num); - spin_unlock(lock, save); -} - -void hardware_alarm_cancel(uint alarm_num) { - timer_hardware_alarm_cancel(PICO_DEFAULT_TIMER_INSTANCE(), alarm_num); -} - -void timer_hardware_alarm_force_irq(timer_hw_t *timer, uint alarm_num) { - check_hardware_alarm_num_param(alarm_num); - spin_lock_t *lock = spin_lock_instance(PICO_SPINLOCK_ID_TIMER); - uint32_t save = spin_lock_blocking(lock); - timer_callbacks_pending[timer_get_index(timer)] |= (uint8_t)(1u << alarm_num); - spin_unlock(lock, save); - hw_set_bits(&timer->intf, 1u << alarm_num); -} - -void hardware_alarm_force_irq(uint alarm_num) { - timer_hardware_alarm_force_irq(PICO_DEFAULT_TIMER_INSTANCE(), alarm_num); -} diff --git a/lib/main/pico-sdk/rp2_common/hardware_uart/include/hardware/uart.h b/lib/main/pico-sdk/rp2_common/hardware_uart/include/hardware/uart.h deleted file mode 100644 index 0cf2c6eaed..0000000000 --- a/lib/main/pico-sdk/rp2_common/hardware_uart/include/hardware/uart.h +++ /dev/null @@ -1,619 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _HARDWARE_UART_H -#define _HARDWARE_UART_H - -#include "pico.h" -#include "hardware/structs/uart.h" - -// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_HARDWARE_UART, Enable/disable assertions in the hardware_uart module, type=bool, default=0, group=hardware_uart -#ifndef PARAM_ASSERTIONS_ENABLED_HARDWARE_UART -#ifdef PARAM_ASSERTIONS_ENABLED_UART // backwards compatibility with SDK < 2.0.0 -#define PARAM_ASSERTIONS_ENABLED_HARDWARE_UART PARAM_ASSERTIONS_ENABLED_UART -#else -#define PARAM_ASSERTIONS_ENABLED_HARDWARE_UART 0 -#endif -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -// PICO_CONFIG: PICO_UART_ENABLE_CRLF_SUPPORT, Enable/disable CR/LF translation support, type=bool, default=1, group=hardware_uart -#ifndef PICO_UART_ENABLE_CRLF_SUPPORT -#define PICO_UART_ENABLE_CRLF_SUPPORT 1 -#endif - -// PICO_CONFIG: PICO_UART_DEFAULT_CRLF, Enable/disable CR/LF translation on UART, type=bool, default=0, depends=PICO_UART_ENABLE_CRLF_SUPPORT, group=hardware_uart -#ifndef PICO_UART_DEFAULT_CRLF -#define PICO_UART_DEFAULT_CRLF 0 -#endif - -// PICO_CONFIG: PICO_DEFAULT_UART, Define the default UART used for printf etc, min=0, max=1, default=Usually provided via board header, group=hardware_uart -// PICO_CONFIG: PICO_DEFAULT_UART_TX_PIN, Define the default UART TX pin, min=0, max=29, default=Usually provided via board header, group=hardware_uart -// PICO_CONFIG: PICO_DEFAULT_UART_RX_PIN, Define the default UART RX pin, min=0, max=29, default=Usually provided via board header, group=hardware_uart - -// PICO_CONFIG: PICO_DEFAULT_UART_BAUD_RATE, Define the default UART baudrate, max=921600, default=115200, group=hardware_uart -#ifndef PICO_DEFAULT_UART_BAUD_RATE -#define PICO_DEFAULT_UART_BAUD_RATE 115200 ///< Default baud rate -#endif - -/** \file hardware/uart.h - * \defgroup hardware_uart hardware_uart - * - * \brief Hardware UART API - * - * RP-series microcontrollers have 2 identical instances of a UART peripheral, based on the ARM PL011. Each UART can be connected to a number - * of GPIO pins as defined in the GPIO muxing. - * - * Only the TX, RX, RTS, and CTS signals are - * connected, meaning that the modem mode and IrDA mode of the PL011 are not supported. - * - * \subsection uart_example Example - * \addtogroup hardware_uart - * - * \code - * int main() { - * - * // Set the GPIO pin mux to the UART - pin 0 is TX, 1 is RX; note use of UART_FUNCSEL_NUM for the general - * // case where the func sel used for UART depends on the pin number - * // Do this before calling uart_init to avoid losing data - * gpio_set_function(0, UART_FUNCSEL_NUM(uart0, 0)); - * gpio_set_function(1, UART_FUNCSEL_NUM(uart0, 1)); - * - * // Initialise UART 0 - * uart_init(uart0, 115200); - * - * uart_puts(uart0, "Hello world!"); - * } - * \endcode - */ - -// Currently always a pointer to hw but it might not be in the future -typedef struct uart_inst uart_inst_t; - -/** The UART identifiers for use in UART functions. - * - * e.g. uart_init(uart1, 48000) - * - * \ingroup hardware_uart - * @{ - */ -#define uart0 ((uart_inst_t *)uart0_hw) ///< Identifier for UART instance 0 -#define uart1 ((uart_inst_t *)uart1_hw) ///< Identifier for UART instance 1 - -/** @} */ - -/** - * \def PICO_DEFAULT_UART_INSTANCE() - * \ingroup hardware_uart - * \hideinitializer - * \brief Returns the default UART instance based on the value of PICO_DEFAULT_UART - */ -#if !defined(PICO_DEFAULT_UART_INSTANCE) && defined(PICO_DEFAULT_UART) -#define PICO_DEFAULT_UART_INSTANCE() (__CONCAT(uart,PICO_DEFAULT_UART)) -#endif - -/** - * \def PICO_DEFAULT_UART - * \ingroup hardware_uart - * \hideinitializer - * \brief The default UART instance number - */ - -#ifdef PICO_DEFAULT_UART_INSTANCE -#define uart_default PICO_DEFAULT_UART_INSTANCE() -#endif - -/** - * \def UART_NUM(uart) - * \ingroup hardware_uart - * \hideinitializer - * \brief Returns the UART number for a UART instance - * - * Note this macro is intended to resolve at compile time, and does no parameter checking - */ -#ifndef UART_NUM -static_assert(NUM_UARTS == 2, ""); -#define UART_NUM(uart) ((uart) == uart1) -#endif - -/** - * \def UART_INSTANCE(uart_num) - * \ingroup hardware_uart - * \hideinitializer - * \brief Returns the UART instance with the given UART number - * - * Note this macro is intended to resolve at compile time, and does no parameter checking - */ -#ifndef UART_INSTANCE -static_assert(NUM_UARTS == 2, ""); -#define UART_INSTANCE(num) ((num) ? uart1 : uart0) -#endif - -/** - * \def UART_DREQ_NUM(uart, is_tx) - * \ingroup hardware_uart - * \hideinitializer - * \brief Returns the \ref dreq_num_t used for pacing DMA transfers to or from this UART instance. - * If is_tx is true, then it is for transfers to the UART else for transfers from the UART. - * - * Note this macro is intended to resolve at compile time, and does no parameter checking - */ -#ifndef UART_DREQ_NUM -#include "hardware/regs/dreq.h" -static_assert(DREQ_UART0_RX == DREQ_UART0_TX + 1, ""); -static_assert(DREQ_UART1_RX == DREQ_UART1_TX + 1, ""); -static_assert(DREQ_UART1_TX == DREQ_UART0_TX + 2, ""); -#define UART_DREQ_NUM(uart, is_tx) ({ \ - DREQ_UART0_TX + UART_NUM(uart) * 2 + !(is_tx); \ -}) -#endif - -/** - * \def UART_CLOCK_NUM(uart) - * \ingroup hardware_uart - * \hideinitializer - * \brief Returns \ref clock_num_t of the clock for the given UART instance - * - * Note this macro is intended to resolve at compile time, and does no parameter checking - */ -#ifndef UART_CLOCK_NUM -#define UART_CLOCK_NUM(uart) clk_peri -#endif - -/** - * \def UART_FUNCSEL_NUM(uart, gpio) - * \ingroup hardware_uart - * \hideinitializer - * \brief Returns \ref gpio_function_t needed to select the UART function for the given UART instance on the given GPIO number. - * - * Note this macro is intended to resolve at compile time, and does no parameter checking - */ -#ifndef UART_FUNCSEL_NUM -#if PICO_RP2040 -#define UART_FUNCSEL_NUM(uart, gpio) GPIO_FUNC_UART -#else -#define UART_FUNCSEL_NUM(uart, gpio) ((gpio) & 0x2 ? GPIO_FUNC_UART_AUX : GPIO_FUNC_UART) -#endif -#endif - -/** - * \def UART_IRQ_NUM(uart) - * \ingroup hardware_uart - * \hideinitializer - * \brief Returns the \ref irq_num_t for processor interrupts from the given UART instance - * - * Note this macro is intended to resolve at compile time, and does no parameter checking - */ -#ifndef UART_IRQ_NUM -#include "hardware/regs/intctrl.h" -static_assert(UART1_IRQ == UART0_IRQ + 1, ""); -#define UART_IRQ_NUM(uart) (UART0_IRQ + UART_NUM(uart)) -#endif - -/** - * \def UART_RESET_NUM(uart) - * \ingroup hardware_uart - * \hideinitializer - * \brief Returns the \ref reset_num_t used to reset a given UART instance - * - * Note this macro is intended to resolve at compile time, and does no parameter checking - */ -#ifndef UART_RESET_NUM -#include "hardware/resets.h" -#define UART_RESET_NUM(uart) (uart_get_index(uart) ? RESET_UART1 : RESET_UART0) -#endif - -/*! \brief Convert UART instance to hardware instance number - * \ingroup hardware_uart - * - * \param uart UART instance - * \return Number of UART, 0 or 1 - */ -static inline uint uart_get_index(uart_inst_t *uart) { - invalid_params_if(HARDWARE_UART, uart != uart0 && uart != uart1); - return UART_NUM(uart); -} - -/*! \brief Get the UART instance from an instance number - * \ingroup hardware_uart - * - * \param num Number of UART, 0 or 1 - * \return UART instance - */ -static inline uart_inst_t *uart_get_instance(uint num) { - invalid_params_if(HARDWARE_UART, num >= NUM_UARTS); - return UART_INSTANCE(num); -} - -/*! \brief Get the real hardware UART instance from a UART instance - * \ingroup hardware_uart - * - * This extra level of abstraction was added to facilitate adding PIO UARTs in the future. - * It currently does nothing, and costs nothing. - * - * \param uart UART instance - * \return The uart_hw_t pointer to the UART instance registers - */ -static inline uart_hw_t *uart_get_hw(uart_inst_t *uart) { - uart_get_index(uart); // check it is a hw uart - return (uart_hw_t *)uart; -} - -/** \brief UART Parity enumeration - * \ingroup hardware_uart - */ -typedef enum { - UART_PARITY_NONE, - UART_PARITY_EVEN, - UART_PARITY_ODD -} uart_parity_t; - -// ---------------------------------------------------------------------------- -// Setup - -/*! \brief Initialise a UART - * \ingroup hardware_uart - * - * Put the UART into a known state, and enable it. Must be called before other - * functions. - * - * This function always enables the FIFOs, and configures the UART for the - * following default line format: - * - * - 8 data bits - * - No parity bit - * - One stop bit - * - * \note There is no guarantee that the baudrate requested will be possible, the nearest will be chosen, - * and this function will return the configured baud rate. - * - * \param uart UART instance. \ref uart0 or \ref uart1 - * \param baudrate Baudrate of UART in Hz - * \return Actual set baudrate - */ -uint uart_init(uart_inst_t *uart, uint baudrate); - -/*! \brief DeInitialise a UART - * \ingroup hardware_uart - * - * Disable the UART if it is no longer used. Must be reinitialised before - * being used again. - * - * \param uart UART instance. \ref uart0 or \ref uart1 - */ -void uart_deinit(uart_inst_t *uart); - -/*! \brief Set UART baud rate - * \ingroup hardware_uart - * - * Set baud rate as close as possible to requested, and return actual rate selected. - * - * The UART is paused for around two character periods whilst the settings are - * changed. Data received during this time may be dropped by the UART. - * - * Any characters still in the transmit buffer will be sent using the new - * updated baud rate. uart_tx_wait_blocking() can be called before this - * function to ensure all characters at the old baud rate have been sent - * before the rate is changed. - * - * This function should not be called from an interrupt context, and the UART - * interrupt should be disabled before calling this function. - * - * \param uart UART instance. \ref uart0 or \ref uart1 - * \param baudrate Baudrate in Hz - * \return Actual set baudrate - */ -uint uart_set_baudrate(uart_inst_t *uart, uint baudrate); - -/*! \brief Set UART flow control CTS/RTS - * \ingroup hardware_uart - * - * \param uart UART instance. \ref uart0 or \ref uart1 - * \param cts If true enable flow control of TX by clear-to-send input - * \param rts If true enable assertion of request-to-send output by RX flow control - */ -static inline void uart_set_hw_flow(uart_inst_t *uart, bool cts, bool rts) { - hw_write_masked(&uart_get_hw(uart)->cr, - (bool_to_bit(cts) << UART_UARTCR_CTSEN_LSB) | (bool_to_bit(rts) << UART_UARTCR_RTSEN_LSB), - UART_UARTCR_RTSEN_BITS | UART_UARTCR_CTSEN_BITS); -} - -/*! \brief Set UART data format - * \ingroup hardware_uart - * - * Configure the data format (bits etc) for the UART. - * - * The UART is paused for around two character periods whilst the settings are - * changed. Data received during this time may be dropped by the UART. - * - * Any characters still in the transmit buffer will be sent using the new - * updated data format. uart_tx_wait_blocking() can be called before this - * function to ensure all characters needing the old format have been sent - * before the format is changed. - * - * This function should not be called from an interrupt context, and the UART - * interrupt should be disabled before calling this function. - * - * \param uart UART instance. \ref uart0 or \ref uart1 - * \param data_bits Number of bits of data. 5..8 - * \param stop_bits Number of stop bits 1..2 - * \param parity Parity option. - */ -void uart_set_format(uart_inst_t *uart, uint data_bits, uint stop_bits, uart_parity_t parity); - -/*! \brief Enable/Disable UART interrupt outputs - * \ingroup hardware_uart - * - * Enable/Disable the UART's interrupt outputs. An interrupt handler should be installed prior to calling - * this function. - * - * \param uart UART instance. \ref uart0 or \ref uart1 - * \param rx_has_data If true an interrupt will be fired when the RX FIFO contains data. - * \param tx_needs_data If true an interrupt will be fired when the TX FIFO needs data. - */ -static inline void uart_set_irqs_enabled(uart_inst_t *uart, bool rx_has_data, bool tx_needs_data) { - // Both UARTRXINTR (RX) and UARTRTINTR (RX timeout) interrupts are - // required for rx_has_data. RX asserts when >=4 characters are in the RX - // FIFO (for RXIFLSEL=0). RT asserts when there are >=1 characters and no - // more have been received for 32 bit periods. - uart_get_hw(uart)->imsc = (bool_to_bit(tx_needs_data) << UART_UARTIMSC_TXIM_LSB) | - (bool_to_bit(rx_has_data) << UART_UARTIMSC_RXIM_LSB) | - (bool_to_bit(rx_has_data) << UART_UARTIMSC_RTIM_LSB); - if (rx_has_data) { - // Set minimum threshold - hw_write_masked(&uart_get_hw(uart)->ifls, 0 << UART_UARTIFLS_RXIFLSEL_LSB, - UART_UARTIFLS_RXIFLSEL_BITS); - } - if (tx_needs_data) { - // Set maximum threshold - hw_write_masked(&uart_get_hw(uart)->ifls, 0 << UART_UARTIFLS_TXIFLSEL_LSB, - UART_UARTIFLS_TXIFLSEL_BITS); - } -} - -// backwards compatibility with SDK version < 2.0.0 -static inline void uart_set_irq_enables(uart_inst_t *uart, bool rx_has_data, bool tx_needs_data) { - uart_set_irqs_enabled(uart, rx_has_data, tx_needs_data); -} - -/*! \brief Test if specific UART is enabled - * \ingroup hardware_uart - * - * \param uart UART instance. \ref uart0 or \ref uart1 - * \return true if the UART is enabled - */ -static inline bool uart_is_enabled(uart_inst_t *uart) { - return uart_get_hw(uart)->cr & UART_UARTCR_UARTEN_BITS; -} - -/*! \brief Enable/Disable the FIFOs on specified UART - * \ingroup hardware_uart - * - * The UART is paused for around two character periods whilst the settings are - * changed. Data received during this time may be dropped by the UART. - * - * Any characters still in the transmit FIFO will be lost if the FIFO is - * disabled. uart_tx_wait_blocking() can be called before this - * function to avoid this. - * - * This function should not be called from an interrupt context, and the UART - * interrupt should be disabled when calling this function. - * - * \param uart UART instance. \ref uart0 or \ref uart1 - * \param enabled true to enable FIFO (default), false to disable - */ -void uart_set_fifo_enabled(uart_inst_t *uart, bool enabled); - -// ---------------------------------------------------------------------------- -// Generic input/output - -/*! \brief Determine if space is available in the TX FIFO - * \ingroup hardware_uart - * - * \param uart UART instance. \ref uart0 or \ref uart1 - * \return false if no space available, true otherwise - */ -static inline bool uart_is_writable(uart_inst_t *uart) { - return !(uart_get_hw(uart)->fr & UART_UARTFR_TXFF_BITS); -} - -/*! \brief Wait for the UART TX fifo to be drained - * \ingroup hardware_uart - * - * \param uart UART instance. \ref uart0 or \ref uart1 - */ -static inline void uart_tx_wait_blocking(uart_inst_t *uart) { - while (uart_get_hw(uart)->fr & UART_UARTFR_BUSY_BITS) tight_loop_contents(); -} - -/*! \brief Determine whether data is waiting in the RX FIFO - * \ingroup hardware_uart - * - * \param uart UART instance. \ref uart0 or \ref uart1 - * \return true if the RX FIFO is not empty, otherwise false. - * - */ -static inline bool uart_is_readable(uart_inst_t *uart) { - // PL011 doesn't expose levels directly, so return values are only 0 or 1 - return !(uart_get_hw(uart)->fr & UART_UARTFR_RXFE_BITS); -} - -/*! \brief Write to the UART for transmission. - * \ingroup hardware_uart - * - * This function will block until all the data has been sent to the UART transmit buffer - * hardware. Note: Serial data transmission will continue until the Tx FIFO and - * the transmit shift register (not programmer-accessible) are empty. - * To ensure the UART FIFO has been emptied, you can use \ref uart_tx_wait_blocking() - * - * \param uart UART instance. \ref uart0 or \ref uart1 - * \param src The bytes to send - * \param len The number of bytes to send - */ -static inline void uart_write_blocking(uart_inst_t *uart, const uint8_t *src, size_t len) { - for (size_t i = 0; i < len; ++i) { - while (!uart_is_writable(uart)) - tight_loop_contents(); - uart_get_hw(uart)->dr = *src++; - } -} - -/*! \brief Read from the UART - * \ingroup hardware_uart - * - * This function blocks until len characters have been read from the UART - * - * \param uart UART instance. \ref uart0 or \ref uart1 - * \param dst Buffer to accept received bytes - * \param len The number of bytes to receive. - */ -static inline void uart_read_blocking(uart_inst_t *uart, uint8_t *dst, size_t len) { - for (size_t i = 0; i < len; ++i) { - while (!uart_is_readable(uart)) - tight_loop_contents(); - *dst++ = (uint8_t) uart_get_hw(uart)->dr; - } -} - -// ---------------------------------------------------------------------------- -// UART-specific operations and aliases - -/*! \brief Write single character to UART for transmission. - * \ingroup hardware_uart - * - * This function will block until the entire character has been sent to the UART transmit buffer - * - * \param uart UART instance. \ref uart0 or \ref uart1 - * \param c The character to send - */ -static inline void uart_putc_raw(uart_inst_t *uart, char c) { - uart_write_blocking(uart, (const uint8_t *) &c, 1); -} - -/*! \brief Write single character to UART for transmission, with optional CR/LF conversions - * \ingroup hardware_uart - * - * This function will block until the character has been sent to the UART transmit buffer - * - * \param uart UART instance. \ref uart0 or \ref uart1 - * \param c The character to send - */ -static inline void uart_putc(uart_inst_t *uart, char c) { -#if PICO_UART_ENABLE_CRLF_SUPPORT - extern short uart_char_to_line_feed[NUM_UARTS]; - if (uart_char_to_line_feed[uart_get_index(uart)] == c) - uart_putc_raw(uart, '\r'); -#endif - uart_putc_raw(uart, c); -} - -/*! \brief Write string to UART for transmission, doing any CR/LF conversions - * \ingroup hardware_uart - * - * This function will block until the entire string has been sent to the UART transmit buffer - * - * \param uart UART instance. \ref uart0 or \ref uart1 - * \param s The null terminated string to send - */ -static inline void uart_puts(uart_inst_t *uart, const char *s) { -#if PICO_UART_ENABLE_CRLF_SUPPORT - bool last_was_cr = false; - while (*s) { - // Don't add extra carriage returns if one is present - if (last_was_cr) - uart_putc_raw(uart, *s); - else - uart_putc(uart, *s); - last_was_cr = *s++ == '\r'; - } -#else - while (*s) - uart_putc(uart, *s++); -#endif -} - -/*! \brief Read a single character from the UART - * \ingroup hardware_uart - * - * This function will block until a character has been read - * - * \param uart UART instance. \ref uart0 or \ref uart1 - * \return The character read. - */ -static inline char uart_getc(uart_inst_t *uart) { - char c; - uart_read_blocking(uart, (uint8_t *) &c, 1); - return c; -} - -/*! \brief Assert a break condition on the UART transmission. - * \ingroup hardware_uart - * - * \param uart UART instance. \ref uart0 or \ref uart1 - * \param en Assert break condition (TX held low) if true. Clear break condition if false. - */ -void uart_set_break(uart_inst_t *uart, bool en); - -/*! \brief Set CR/LF conversion on UART - * \ingroup hardware_uart - * - * \param uart UART instance. \ref uart0 or \ref uart1 - * \param translate If true, convert line feeds to carriage return on transmissions - */ -void uart_set_translate_crlf(uart_inst_t *uart, bool translate); - -/*! \brief Wait for the default UART's TX FIFO to be drained - * \ingroup hardware_uart - */ -static inline void uart_default_tx_wait_blocking(void) { -#ifdef uart_default - uart_tx_wait_blocking(uart_default); -#else - assert(false); -#endif -} - -/*! \brief Wait for up to a certain number of microseconds for the RX FIFO to be non empty - * \ingroup hardware_uart - * - * \param uart UART instance. \ref uart0 or \ref uart1 - * \param us the number of microseconds to wait at most (may be 0 for an instantaneous check) - * \return true if the RX FIFO became non empty before the timeout, false otherwise - */ -bool uart_is_readable_within_us(uart_inst_t *uart, uint32_t us); - -/*! \brief Return the \ref dreq_num_t to use for pacing transfers to/from a particular UART instance - * \ingroup hardware_uart - * - * \param uart UART instance. \ref uart0 or \ref uart1 - * \param is_tx true for sending data to the UART instance, false for receiving data from the UART instance - */ -static inline uint uart_get_dreq_num(uart_inst_t *uart, bool is_tx) { - return UART_DREQ_NUM(uart, is_tx); -} - -/*! \brief Return the \ref reset_num_t to use to reset a particular UART instance - * \ingroup hardware_uart - * - * \param uart UART instance. \ref uart0 or \ref uart1 - */ -static inline uint uart_get_reset_num(uart_inst_t *uart) { - return UART_RESET_NUM(uart); -} - -// backwards compatibility -static inline uint uart_get_dreq(uart_inst_t *uart, bool is_tx) { - return uart_get_dreq_num(uart, is_tx); -} - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/lib/main/pico-sdk/rp2_common/hardware_uart/uart.c b/lib/main/pico-sdk/rp2_common/hardware_uart/uart.c deleted file mode 100644 index be2df57c55..0000000000 --- a/lib/main/pico-sdk/rp2_common/hardware_uart/uart.c +++ /dev/null @@ -1,237 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "hardware/address_mapped.h" -#include "hardware/platform_defs.h" -#include "hardware/uart.h" - -#include "hardware/structs/uart.h" -#include "hardware/resets.h" -#include "hardware/clocks.h" - -static inline uint32_t uart_clock_get_hz(__unused uart_inst_t *inst) { - return clock_get_hz(UART_CLOCK_NUM(inst)); -} - -#include "hardware/timer.h" - -#include "pico/assert.h" -#include "pico.h" - -check_hw_layout(uart_hw_t, fr, UART_UARTFR_OFFSET); -check_hw_layout(uart_hw_t, dmacr, UART_UARTDMACR_OFFSET); - -#if PICO_UART_ENABLE_CRLF_SUPPORT -short uart_char_to_line_feed[NUM_UARTS]; -#endif - -/// \tag::uart_reset[] -static inline void uart_reset(uart_inst_t *uart) { - reset_block_num(uart_get_reset_num(uart)); -} - -static inline void uart_unreset(uart_inst_t *uart) { - unreset_block_num_wait_blocking(uart_get_reset_num(uart)); -} -/// \end::uart_reset[] - -/// \tag::uart_init[] -uint uart_init(uart_inst_t *uart, uint baudrate) { - invalid_params_if(HARDWARE_UART, uart != uart0 && uart != uart1); - - if (uart_clock_get_hz(uart) == 0) { - return 0; - } - - uart_reset(uart); - uart_unreset(uart); - -#if PICO_UART_ENABLE_CRLF_SUPPORT - uart_set_translate_crlf(uart, PICO_UART_DEFAULT_CRLF); -#endif - - // Any LCR writes need to take place before enabling the UART - uint baud = uart_set_baudrate(uart, baudrate); - - // inline the uart_set_format() call, as we don't need the CR disable/re-enable - // protection, and also many people will never call it again, so having - // the generic function is not useful, and much bigger than this inlined - // code which is only a handful of instructions. - // - // The UART_UARTLCR_H_FEN_BITS setting is combined as well as it is the same register -#if 0 - uart_set_format(uart, 8, 1, UART_PARITY_NONE); - // Enable FIFOs (must be before setting UARTEN, as this is an LCR access) - hw_set_bits(&uart_get_hw(uart)->lcr_h, UART_UARTLCR_H_FEN_BITS); -#else - uint data_bits = 8; - uint stop_bits = 1; - uint parity = UART_PARITY_NONE; - hw_write_masked(&uart_get_hw(uart)->lcr_h, - ((data_bits - 5u) << UART_UARTLCR_H_WLEN_LSB) | - ((stop_bits - 1u) << UART_UARTLCR_H_STP2_LSB) | - (bool_to_bit(parity != UART_PARITY_NONE) << UART_UARTLCR_H_PEN_LSB) | - (bool_to_bit(parity == UART_PARITY_EVEN) << UART_UARTLCR_H_EPS_LSB) | - UART_UARTLCR_H_FEN_BITS, - UART_UARTLCR_H_WLEN_BITS | UART_UARTLCR_H_STP2_BITS | - UART_UARTLCR_H_PEN_BITS | UART_UARTLCR_H_EPS_BITS | - UART_UARTLCR_H_FEN_BITS); -#endif - - // Enable the UART, both TX and RX - uart_get_hw(uart)->cr = UART_UARTCR_UARTEN_BITS | UART_UARTCR_TXE_BITS | UART_UARTCR_RXE_BITS; -#if !PICO_UART_NO_DMACR_ENABLE - // Always enable DREQ signals -- no harm in this if DMA is not listening - uart_get_hw(uart)->dmacr = UART_UARTDMACR_TXDMAE_BITS | UART_UARTDMACR_RXDMAE_BITS; -#endif - - return baud; -} -/// \end::uart_init[] - -void uart_deinit(uart_inst_t *uart) { - invalid_params_if(HARDWARE_UART, uart != uart0 && uart != uart1); - uart_reset(uart); -} - -static uint32_t uart_disable_before_lcr_write(uart_inst_t *uart) { - // Notes from PL011 reference manual: - // - // - Before writing the LCR, if the UART is enabled it needs to be - // disabled and any current TX + RX activity has to be completed - // - // - There is a BUSY flag which waits for the current TX char, but this is - // OR'd with TX FIFO !FULL, so not usable when FIFOs are enabled and - // potentially nonempty - // - // - FIFOs can't be set to disabled whilst a character is in progress - // (else "FIFO integrity is not guaranteed") - // - // Combination of these means there is no general way to halt and poll for - // end of TX character, if FIFOs may be enabled. Either way, there is no - // way to poll for end of RX character. - // - // So, insert a 15 Baud period delay before changing the settings. - // 15 Baud is comfortably higher than start + max data + parity + stop. - // Anything else would require API changes to permit a non-enabled UART - // state after init() where settings can be changed safely. - uint32_t cr_save = uart_get_hw(uart)->cr; - - if (cr_save & UART_UARTCR_UARTEN_BITS) { - hw_clear_bits(&uart_get_hw(uart)->cr, - UART_UARTCR_UARTEN_BITS | UART_UARTCR_TXE_BITS | UART_UARTCR_RXE_BITS); - - uint32_t current_ibrd = uart_get_hw(uart)->ibrd; - uint32_t current_fbrd = uart_get_hw(uart)->fbrd; - - // Note: Maximise precision here. Show working, the compiler will mop this up. - // Create a 16.6 fixed-point fractional division ratio; then scale to 32-bits. - uint32_t brdiv_ratio = 64u * current_ibrd + current_fbrd; - brdiv_ratio <<= 10; - // 3662 is ~(15 * 244.14) where 244.14 is 16e6 / 2^16 - uint32_t scaled_freq = uart_clock_get_hz(uart) / 3662ul; - uint32_t wait_time_us = brdiv_ratio / scaled_freq; - busy_wait_us(wait_time_us); - } - - return cr_save; -} - -static void uart_write_lcr_bits_masked(uart_inst_t *uart, uint32_t values, uint32_t write_mask) { - invalid_params_if(HARDWARE_UART, uart != uart0 && uart != uart1); - - // (Potentially) Cleanly handle disabling the UART before touching LCR - uint32_t cr_save = uart_disable_before_lcr_write(uart); - - hw_write_masked(&uart_get_hw(uart)->lcr_h, values, write_mask); - - uart_get_hw(uart)->cr = cr_save; -} - -/// \tag::uart_set_baudrate[] -uint uart_set_baudrate(uart_inst_t *uart, uint baudrate) { - invalid_params_if(HARDWARE_UART, baudrate == 0); - uint32_t baud_rate_div = (8 * uart_clock_get_hz(uart) / baudrate) + 1; - uint32_t baud_ibrd = baud_rate_div >> 7; - uint32_t baud_fbrd; - - if (baud_ibrd == 0) { - baud_ibrd = 1; - baud_fbrd = 0; - } else if (baud_ibrd >= 65535) { - baud_ibrd = 65535; - baud_fbrd = 0; - } else { - baud_fbrd = (baud_rate_div & 0x7f) >> 1; - } - - uart_get_hw(uart)->ibrd = baud_ibrd; - uart_get_hw(uart)->fbrd = baud_fbrd; - - // PL011 needs a (dummy) LCR_H write to latch in the divisors. - // We don't want to actually change LCR_H contents here. - uart_write_lcr_bits_masked(uart, 0, 0); - - // See datasheet - return (4 * uart_clock_get_hz(uart)) / (64 * baud_ibrd + baud_fbrd); -} -/// \end::uart_set_baudrate[] - -void uart_set_format(uart_inst_t *uart, uint data_bits, uint stop_bits, uart_parity_t parity) { - invalid_params_if(HARDWARE_UART, data_bits < 5 || data_bits > 8); - invalid_params_if(HARDWARE_UART, stop_bits != 1 && stop_bits != 2); - invalid_params_if(HARDWARE_UART, parity != UART_PARITY_NONE && parity != UART_PARITY_EVEN && parity != UART_PARITY_ODD); - - uart_write_lcr_bits_masked(uart, - ((data_bits - 5u) << UART_UARTLCR_H_WLEN_LSB) | - ((stop_bits - 1u) << UART_UARTLCR_H_STP2_LSB) | - (bool_to_bit(parity != UART_PARITY_NONE) << UART_UARTLCR_H_PEN_LSB) | - (bool_to_bit(parity == UART_PARITY_EVEN) << UART_UARTLCR_H_EPS_LSB), - UART_UARTLCR_H_WLEN_BITS | - UART_UARTLCR_H_STP2_BITS | - UART_UARTLCR_H_PEN_BITS | - UART_UARTLCR_H_EPS_BITS); -} - -void uart_set_fifo_enabled(uart_inst_t *uart, bool enabled) { - - uint32_t lcr_h_fen_bits = 0; - - if (enabled) { - lcr_h_fen_bits = UART_UARTLCR_H_FEN_BITS; - } - - uart_write_lcr_bits_masked(uart, lcr_h_fen_bits, UART_UARTLCR_H_FEN_BITS); -} - -void uart_set_break(uart_inst_t *uart, bool en) { - - uint32_t lcr_h_brk_bits = 0; - - if (en) { - lcr_h_brk_bits = UART_UARTLCR_H_BRK_BITS; - } - - uart_write_lcr_bits_masked(uart, lcr_h_brk_bits, UART_UARTLCR_H_BRK_BITS); -} - -void uart_set_translate_crlf(uart_inst_t *uart, bool crlf) { -#if PICO_UART_ENABLE_CRLF_SUPPORT - uart_char_to_line_feed[uart_get_index(uart)] = crlf ? '\n' : 0x100; -#else - panic_unsupported(); -#endif -} - -bool uart_is_readable_within_us(uart_inst_t *uart, uint32_t us) { - uint32_t t = time_us_32(); - do { - if (uart_is_readable(uart)) { - return true; - } - } while ((time_us_32() - t) <= us); - return false; -} diff --git a/lib/main/pico-sdk/rp2_common/hardware_vreg/include/hardware/vreg.h b/lib/main/pico-sdk/rp2_common/hardware_vreg/include/hardware/vreg.h deleted file mode 100644 index ce6ad0ca66..0000000000 --- a/lib/main/pico-sdk/rp2_common/hardware_vreg/include/hardware/vreg.h +++ /dev/null @@ -1,99 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _HARDWARE_VREG_H -#define _HARDWARE_VREG_H - -#include "pico.h" - -#if PICO_RP2040 -#include "hardware/structs/vreg_and_chip_reset.h" -#else -#include "hardware/structs/powman.h" -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -/** \file vreg.h - * \defgroup hardware_vreg hardware_vreg - * - * \brief Voltage Regulation API - * - */ - -/** Possible voltage values that can be applied to the regulator - */ -enum vreg_voltage { -#if !PICO_RP2040 - VREG_VOLTAGE_0_55 = 0b00000, - VREG_VOLTAGE_0_60 = 0b00001, - VREG_VOLTAGE_0_65 = 0b00010, - VREG_VOLTAGE_0_70 = 0b00011, - VREG_VOLTAGE_0_75 = 0b00100, - VREG_VOLTAGE_0_80 = 0b00101, -#endif - VREG_VOLTAGE_0_85 = 0b00110, ///< 0.85 V - VREG_VOLTAGE_0_90 = 0b00111, ///< 0.90 V - VREG_VOLTAGE_0_95 = 0b01000, ///< 0.95 V - VREG_VOLTAGE_1_00 = 0b01001, ///< 1.00 V - VREG_VOLTAGE_1_05 = 0b01010, ///< 1.05 V - VREG_VOLTAGE_1_10 = 0b01011, ///< 1.10 V - VREG_VOLTAGE_1_15 = 0b01100, ///< 1.15 V - VREG_VOLTAGE_1_20 = 0b01101, ///< 1.20 V - VREG_VOLTAGE_1_25 = 0b01110, ///< 1.25 V - VREG_VOLTAGE_1_30 = 0b01111, ///< 1.30 V -#if !PICO_RP2040 - // Above this point you will need to set POWMAN_VREG_CTRL_DISABLE_VOLTAGE_LIMIT - VREG_VOLTAGE_1_35 = 0b10000, - VREG_VOLTAGE_1_40 = 0b10001, - VREG_VOLTAGE_1_50 = 0b10010, - VREG_VOLTAGE_1_60 = 0b10011, - VREG_VOLTAGE_1_65 = 0b10100, - VREG_VOLTAGE_1_70 = 0b10101, - VREG_VOLTAGE_1_80 = 0b10110, - VREG_VOLTAGE_1_90 = 0b10111, - VREG_VOLTAGE_2_00 = 0b11000, - VREG_VOLTAGE_2_35 = 0b11001, - VREG_VOLTAGE_2_50 = 0b11010, - VREG_VOLTAGE_2_65 = 0b11011, - VREG_VOLTAGE_2_80 = 0b11100, - VREG_VOLTAGE_3_00 = 0b11101, - VREG_VOLTAGE_3_15 = 0b11110, - VREG_VOLTAGE_3_30 = 0b11111, -#endif - - // Note the "max" here assumes that VREG_CTRL_DISABLE_VOLTAGE_LIMIT is not set - VREG_VOLTAGE_MIN = VREG_VOLTAGE_0_85, ///< Always the minimum possible voltage - VREG_VOLTAGE_DEFAULT = VREG_VOLTAGE_1_10, ///< Default voltage on power up. - VREG_VOLTAGE_MAX = VREG_VOLTAGE_1_30, ///< Always the maximum possible voltage -}; - - -/*! \brief Set voltage - * \ingroup hardware_vreg - * - * \param voltage The voltage (from enumeration \ref vreg_voltage) to apply to the voltage regulator - **/ -void vreg_set_voltage(enum vreg_voltage voltage); - - -/*! \brief Enable use of voltages beyond the safe range of operation - * \ingroup hardware_vreg - * - * This allows voltages beyond VREG_VOLTAGE_MAX to be used, on platforms where - * they are available (e.g. RP2350). Attempting to set a higher voltage - * without first calling this function will result in a voltage of - * VREG_VOLTAGE_MAX. - **/ -void vreg_disable_voltage_limit(void); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/lib/main/pico-sdk/rp2_common/hardware_vreg/vreg.c b/lib/main/pico-sdk/rp2_common/hardware_vreg/vreg.c deleted file mode 100644 index 61fd080425..0000000000 --- a/lib/main/pico-sdk/rp2_common/hardware_vreg/vreg.c +++ /dev/null @@ -1,50 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "pico.h" -#include "hardware/vreg.h" - -void vreg_set_voltage(enum vreg_voltage voltage) { -#if PICO_RP2040 - - hw_write_masked( - &vreg_and_chip_reset_hw->vreg, - ((uint)voltage) << VREG_AND_CHIP_RESET_VREG_VSEL_LSB, - VREG_AND_CHIP_RESET_VREG_VSEL_BITS - ); - -#elif PICO_RP2350 - - hw_set_bits(&powman_hw->vreg_ctrl, POWMAN_PASSWORD_BITS | POWMAN_VREG_CTRL_UNLOCK_BITS); - - // Wait for any prior change to finish before making a new change - while (powman_hw->vreg & POWMAN_VREG_UPDATE_IN_PROGRESS_BITS) - tight_loop_contents(); - - hw_write_masked( - &powman_hw->vreg, - POWMAN_PASSWORD_BITS | ((uint)voltage << POWMAN_VREG_VSEL_LSB), - POWMAN_PASSWORD_BITS | POWMAN_VREG_VSEL_BITS - ); - while (powman_hw->vreg & POWMAN_VREG_UPDATE_IN_PROGRESS_BITS) - tight_loop_contents(); - -#else - panic_unsupported(); -#endif -} - -void vreg_disable_voltage_limit(void) { -#if PICO_RP2040 - // The voltage limit can't be disabled on RP2040 (was implemented by - // hardwiring the LDO controls) - return; -#elif PICO_RP2350 - hw_set_bits(&powman_hw->vreg_ctrl, POWMAN_PASSWORD_BITS | POWMAN_VREG_CTRL_DISABLE_VOLTAGE_LIMIT_BITS); -#else - panic_unsupported(); -#endif -} diff --git a/lib/main/pico-sdk/rp2_common/hardware_watchdog/include/hardware/watchdog.h b/lib/main/pico-sdk/rp2_common/hardware_watchdog/include/hardware/watchdog.h deleted file mode 100644 index e6adf65afc..0000000000 --- a/lib/main/pico-sdk/rp2_common/hardware_watchdog/include/hardware/watchdog.h +++ /dev/null @@ -1,143 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _HARDWARE_WATCHDOG_H -#define _HARDWARE_WATCHDOG_H - -#include "pico.h" -#include "hardware/structs/watchdog.h" - -/** \file hardware/watchdog.h - * \defgroup hardware_watchdog hardware_watchdog - * - * \brief Hardware Watchdog Timer API - * - * Supporting functions for the Pico hardware watchdog timer. - * - * The RP-series microcontrollers have a built in HW watchdog Timer. This is a countdown timer that can restart parts of the chip if it reaches zero. - * For example, this can be used to restart the processor if the software running on it gets stuck in an infinite loop - * or similar. The programmer has to periodically write a value to the watchdog to stop it reaching zero. - * - * \subsection watchdog_example Example - * \addtogroup hardware_watchdog - * \include hello_watchdog.c - */ - -#ifdef __cplusplus -extern "C" { -#endif - -// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_HARDWARE_WATCHDOG, Enable/disable assertions in the hardware_watchdog module, type=bool, default=0, group=hardware_watchdog -#ifndef PARAM_ASSERTIONS_ENABLED_HARDWARE_WATCHDOG -#ifdef PARAM_ASSERTIONS_ENABLED_WATCHDOG // backwards compatibility with SDK < 2.0.0 -#define PARAM_ASSERTIONS_ENABLED_HARDWARE_WATCHDOG PARAM_ASSERTIONS_ENABLED_WATCHDOG -#else -#define PARAM_ASSERTIONS_ENABLED_HARDWARE_WATCHDOG 0 -#endif -#endif - -/*! \brief Define actions to perform at watchdog timeout - * \ingroup hardware_watchdog - * - * \note If \ref watchdog_start_tick value does not give a 1MHz clock to the watchdog system, then the \p delay_ms - * parameter will not be in milliseconds. See the datasheet for more details. - * - * By default the SDK assumes a 12MHz XOSC and sets the \ref watchdog_start_tick appropriately. - * - * \param pc If Zero, a standard boot will be performed, if non-zero this is the program counter to jump to on reset. - * \param sp If \p pc is non-zero, this will be the stack pointer used. - * \param delay_ms Initial load value. Maximum value 8388, approximately 8.3s. - */ -void watchdog_reboot(uint32_t pc, uint32_t sp, uint32_t delay_ms); - -/*! \brief Start the watchdog tick - * \ingroup hardware_watchdog - * - * \param cycles This needs to be a divider that when applied to the XOSC input, produces a 1MHz clock. So if the XOSC is - * 12MHz, this will need to be 12. - */ -void watchdog_start_tick(uint cycles); - -/*! \brief Reload the watchdog counter with the amount of time set in watchdog_enable - * \ingroup hardware_watchdog - * - */ -void watchdog_update(void); - -/** - * \brief Enable the watchdog - * \ingroup hardware_watchdog - * - * \note If \ref watchdog_start_tick value does not give a 1MHz clock to the watchdog system, then the \p delay_ms - * parameter will not be in milliseconds. See the datasheet for more details. - * - * By default the SDK assumes a 12MHz XOSC and sets the \ref watchdog_start_tick appropriately. - * - * This method sets a marker in the watchdog scratch register 4 that is checked by \ref watchdog_enable_caused_reboot. - * If the device is subsequently reset via a call to watchdog_reboot (including for example by dragging a UF2 - * onto the RPI-RP2), then this value will be cleared, and so \ref watchdog_enable_caused_reboot will - * return false. - * - * \param delay_ms Number of milliseconds before watchdog will reboot without watchdog_update being called. Maximum of 8388, which is approximately 8.3 seconds - * \param pause_on_debug If the watchdog should be paused when the debugger is stepping through code - */ -void watchdog_enable(uint32_t delay_ms, bool pause_on_debug); - -/** - * \brief Disable the watchdog - * \ingroup hardware_watchdog - */ -void watchdog_disable(void); - -/** - * \brief Did the watchdog cause the last reboot? - * \ingroup hardware_watchdog - * - * @return true If the watchdog timer or a watchdog force caused the last reboot - * @return false If there has been no watchdog reboot since the last power on reset. A power on reset is typically caused by a power cycle or the run pin (reset button) being toggled. - */ -bool watchdog_caused_reboot(void); - -/** - * \brief Did watchdog_enable cause the last reboot? - * \ingroup hardware_watchdog - * - * Perform additional checking along with \ref watchdog_caused_reboot to determine if a watchdog timeout initiated by - * \ref watchdog_enable caused the last reboot. - * - * This method checks for a special value in watchdog scratch register 4 placed there by \ref watchdog_enable. - * This would not be present if a watchdog reset is initiated by \ref watchdog_reboot or by the RP-series microcontroller bootrom - * (e.g. dragging a UF2 onto the RPI-RP2 drive). - * - * @return true If the watchdog timer or a watchdog force caused (see \ref watchdog_caused_reboot) the last reboot - * and the watchdog reboot happened after \ref watchdog_enable was called - * @return false If there has been no watchdog reboot since the last power on reset, or the watchdog reboot was not caused - * by a watchdog timeout after \ref watchdog_enable was called. - * A power on reset is typically caused by a power cycle or the run pin (reset button) being toggled. - */ -bool watchdog_enable_caused_reboot(void); - -/** - * \brief Returns the number of microseconds before the watchdog will reboot the chip. - * \ingroup hardware_watchdog - * - * \if rp2040_specicifc - * On RP2040 this method returns the last value set instead of the remaining time due to a h/w bug. - * \endif - * - * @return The number of microseconds before the watchdog will reboot the chip. - */ -uint32_t watchdog_get_time_remaining_ms(void); - -// backwards compatibility with SDK < 2.0.0 -static inline uint32_t watchdog_get_count(void) { - return watchdog_get_time_remaining_ms(); -} -#ifdef __cplusplus -} -#endif - -#endif diff --git a/lib/main/pico-sdk/rp2_common/hardware_watchdog/watchdog.c b/lib/main/pico-sdk/rp2_common/hardware_watchdog/watchdog.c deleted file mode 100644 index 45528ce436..0000000000 --- a/lib/main/pico-sdk/rp2_common/hardware_watchdog/watchdog.c +++ /dev/null @@ -1,125 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include - -#include "hardware/watchdog.h" -#include "hardware/structs/watchdog.h" -#include "hardware/structs/psm.h" -#include "hardware/ticks.h" -#include "pico/bootrom.h" - -/// \tag::watchdog_start_tick[] -void watchdog_start_tick(uint cycles) { - tick_start(TICK_WATCHDOG, cycles); -} -/// \end::watchdog_start_tick[] - -// Value to load when updating the watchdog - -// tag::watchdog_update[] -static uint32_t load_value; - -void watchdog_update(void) { - watchdog_hw->load = load_value; -} -// end::watchdog_update[] - -uint32_t watchdog_get_time_remaining_ms(void) { - return watchdog_hw->ctrl & WATCHDOG_CTRL_TIME_BITS; -} - -#if PICO_RP2040 -// Note, we have x2 here as the watchdog HW currently decrements twice per tick -#define WATCHDOG_XFACTOR 2 -#else -#define WATCHDOG_XFACTOR 1 -#endif -// tag::watchdog_enable[] -// Helper function used by both watchdog_enable and watchdog_reboot -void _watchdog_enable(uint32_t delay_ms, bool pause_on_debug) { - valid_params_if(HARDWARE_WATCHDOG, delay_ms <= WATCHDOG_LOAD_BITS / (1000 * WATCHDOG_XFACTOR)); - hw_clear_bits(&watchdog_hw->ctrl, WATCHDOG_CTRL_ENABLE_BITS); - - // Reset everything apart from ROSC and XOSC - hw_set_bits(&psm_hw->wdsel, PSM_WDSEL_BITS & ~(PSM_WDSEL_ROSC_BITS | PSM_WDSEL_XOSC_BITS)); - - uint32_t dbg_bits = WATCHDOG_CTRL_PAUSE_DBG0_BITS | - WATCHDOG_CTRL_PAUSE_DBG1_BITS | - WATCHDOG_CTRL_PAUSE_JTAG_BITS; - - if (pause_on_debug) { - hw_set_bits(&watchdog_hw->ctrl, dbg_bits); - } else { - hw_clear_bits(&watchdog_hw->ctrl, dbg_bits); - } - - if (!delay_ms) { - hw_set_bits(&watchdog_hw->ctrl, WATCHDOG_CTRL_TRIGGER_BITS); - } else { - load_value = delay_ms * 1000; -#if PICO_RP2040 - load_value *= 2; -#endif - if (load_value > WATCHDOG_LOAD_BITS) - load_value = WATCHDOG_LOAD_BITS; - - watchdog_update(); - - hw_set_bits(&watchdog_hw->ctrl, WATCHDOG_CTRL_ENABLE_BITS); - } -} -// end::watchdog_enable[] - -#define WATCHDOG_NON_REBOOT_MAGIC 0x6ab73121 - -void watchdog_enable(uint32_t delay_ms, bool pause_on_debug) { - // update scratch[4] to distinguish from magic used for reboot to specific address, or 0 used to reboot - // into regular flash path - watchdog_hw->scratch[4] = WATCHDOG_NON_REBOOT_MAGIC; - _watchdog_enable(delay_ms, pause_on_debug); -} - -void watchdog_disable(void) { - hw_clear_bits(&watchdog_hw->ctrl, WATCHDOG_CTRL_ENABLE_BITS); -} - -void watchdog_reboot(uint32_t pc, uint32_t sp, uint32_t delay_ms) { - check_hw_layout(watchdog_hw_t, scratch[7], WATCHDOG_SCRATCH7_OFFSET); - - // Clear enable before setting up scratch registers - hw_clear_bits(&watchdog_hw->ctrl, WATCHDOG_CTRL_ENABLE_BITS); - - if (pc) { -#ifndef __riscv - pc |= 1u; // thumb mode -#endif - watchdog_hw->scratch[4] = 0xb007c0d3; - watchdog_hw->scratch[5] = pc ^ -0xb007c0d3; - watchdog_hw->scratch[6] = sp; - watchdog_hw->scratch[7] = pc; -// printf("rebooting %08x/%08x in %dms...\n", (uint) pc, (uint) sp, (uint) delay_ms); - } else { - watchdog_hw->scratch[4] = 0; -// printf("rebooting (regular)) in %dms...\n", (uint) delay_ms); - } - - // Don't pause watchdog for debug - _watchdog_enable(delay_ms, 0); -} - -bool watchdog_caused_reboot(void) { - // If any reason bits are set this is true -#if PICO_RP2040 - return watchdog_hw->reason; -#else - return watchdog_hw->reason && rom_get_last_boot_type() == BOOT_TYPE_NORMAL; -#endif -} - -bool watchdog_enable_caused_reboot(void) { - return watchdog_hw->reason && watchdog_hw->scratch[4] == WATCHDOG_NON_REBOOT_MAGIC; -} diff --git a/lib/main/pico-sdk/rp2_common/hardware_xosc/include/hardware/xosc.h b/lib/main/pico-sdk/rp2_common/hardware_xosc/include/hardware/xosc.h deleted file mode 100644 index 1153b93622..0000000000 --- a/lib/main/pico-sdk/rp2_common/hardware_xosc/include/hardware/xosc.h +++ /dev/null @@ -1,59 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _HARDWARE_XOSC_H -#define _HARDWARE_XOSC_H - -#include "pico.h" -#include "hardware/structs/xosc.h" - - -// Allow lengthening startup delay to accommodate slow-starting oscillators - -// PICO_CONFIG: PICO_XOSC_STARTUP_DELAY_MULTIPLIER, Multiplier to lengthen xosc startup delay to accommodate slow-starting oscillators, type=int, min=1, default=1, group=hardware_xosc -#ifndef PICO_XOSC_STARTUP_DELAY_MULTIPLIER -#define PICO_XOSC_STARTUP_DELAY_MULTIPLIER 1 -#endif - - -#ifdef __cplusplus -extern "C" { -#endif - -/** \file hardware/xosc.h - * \defgroup hardware_xosc hardware_xosc - * - * \brief Crystal Oscillator (XOSC) API - */ - -/*! \brief Initialise the crystal oscillator system - * \ingroup hardware_xosc - * - * This function will block until the crystal oscillator has stabilised. - **/ -void xosc_init(void); - -/*! \brief Disable the Crystal oscillator - * \ingroup hardware_xosc - * - * Turns off the crystal oscillator source, and waits for it to become unstable - **/ -void xosc_disable(void); - -/*! \brief Set the crystal oscillator system to dormant - * \ingroup hardware_xosc - * - * Turns off the crystal oscillator until it is woken by an interrupt. This will block and hence - * the entire system will stop, until an interrupt wakes it up. This function will - * continue to block until the oscillator becomes stable after its wakeup. - **/ -void xosc_dormant(void); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/lib/main/pico-sdk/rp2_common/hardware_xosc/xosc.c b/lib/main/pico-sdk/rp2_common/hardware_xosc/xosc.c deleted file mode 100644 index d32442ef5b..0000000000 --- a/lib/main/pico-sdk/rp2_common/hardware_xosc/xosc.c +++ /dev/null @@ -1,63 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "pico.h" - -// For frequency related definitions etc -#include "hardware/clocks.h" - -#include "hardware/platform_defs.h" -#include "hardware/regs/xosc.h" -#include "hardware/xosc.h" - -#if XOSC_HZ < (1 * MHZ) || XOSC_HZ > (50 * MHZ) -// Note: Although an external clock can be supplied up to 50 MHz, the maximum frequency the -// XOSC cell is specified to work with a crystal is less, please see the appropriate RP-series datasheet. -#error XOSC_HZ must be in the range 1,000,000-50,000,000 i.e. 1-50MHz XOSC frequency -#endif - -#define STARTUP_DELAY ((((XOSC_HZ / KHZ) + 128) / 256) * PICO_XOSC_STARTUP_DELAY_MULTIPLIER) - -// The DELAY field in xosc_hw->startup is 14 bits wide. -#if STARTUP_DELAY >= (1 << 13) -#error PICO_XOSC_STARTUP_DELAY_MULTIPLIER is too large: XOSC STARTUP.DELAY must be < 8192 -#endif - -void xosc_init(void) { - // Assumes 1-15 MHz input, checked above. - xosc_hw->ctrl = XOSC_CTRL_FREQ_RANGE_VALUE_1_15MHZ; - - // Set xosc startup delay - xosc_hw->startup = STARTUP_DELAY; - - // Set the enable bit now that we have set freq range and startup delay - hw_set_bits(&xosc_hw->ctrl, XOSC_CTRL_ENABLE_VALUE_ENABLE << XOSC_CTRL_ENABLE_LSB); - - // Wait for XOSC to be stable - while(!(xosc_hw->status & XOSC_STATUS_STABLE_BITS)) { - tight_loop_contents(); - } -} - -void xosc_disable(void) { - uint32_t tmp = xosc_hw->ctrl; - tmp &= (~XOSC_CTRL_ENABLE_BITS); - tmp |= (XOSC_CTRL_ENABLE_VALUE_DISABLE << XOSC_CTRL_ENABLE_LSB); - xosc_hw->ctrl = tmp; - // Wait for stable to go away - while(xosc_hw->status & XOSC_STATUS_STABLE_BITS) { - tight_loop_contents(); - } -} - -void xosc_dormant(void) { - // WARNING: This stops the xosc until woken up by an irq - xosc_hw->dormant = XOSC_DORMANT_VALUE_DORMANT; - // Wait for it to become stable once woken up - while(!(xosc_hw->status & XOSC_STATUS_STABLE_BITS)) { - tight_loop_contents(); - } -} diff --git a/lib/main/pico-sdk/rp2_common/pico_aon_timer/aon_timer.c b/lib/main/pico-sdk/rp2_common/pico_aon_timer/aon_timer.c deleted file mode 100644 index 35173cf892..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_aon_timer/aon_timer.c +++ /dev/null @@ -1,167 +0,0 @@ -/* - * Copyright (c) 2024 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "pico/aon_timer.h" -#include "hardware/irq.h" -#include "hardware/sync.h" - -static aon_timer_alarm_handler_t aon_timer_alarm_handler; - -#if HAS_RP2040_RTC -#include "hardware/rtc.h" -#include "pico/util/datetime.h" -#elif HAS_POWMAN_TIMER -#include "hardware/powman.h" - -static void powman_timer_irq_handler(void) { - uint irq_num = aon_timer_get_irq_num(); - // we are one-shot, so remove ourselves - irq_set_enabled(irq_num, false); - irq_remove_handler(irq_num, powman_timer_irq_handler); - if (aon_timer_alarm_handler) aon_timer_alarm_handler(); -} -#endif - -void aon_timer_set_time(const struct timespec *ts) { -#if HAS_RP2040_RTC - datetime_t dt; - bool ok = time_to_datetime(ts->tv_sec, &dt); - assert(ok); - if (ok) rtc_set_datetime(&dt); -#elif HAS_POWMAN_TIMER - powman_timer_set_ms(timespec_to_ms(ts)); -#else - panic_unsupported(); -#endif -} - -void aon_timer_get_time(struct timespec *ts) { -#if HAS_RP2040_RTC - datetime_t dt; - rtc_get_datetime(&dt); - time_t t; - bool ok = datetime_to_time(&dt, &t); - assert(ok); - ts->tv_nsec = 0; - if (ok) { - ts->tv_sec = t; - } else { - ts->tv_sec = -1; - } -#elif HAS_POWMAN_TIMER - ms_to_timespec(powman_timer_get_ms(), ts); -#else - panic_unsupported(); -#endif -} - -aon_timer_alarm_handler_t aon_timer_enable_alarm(const struct timespec *ts, aon_timer_alarm_handler_t handler, bool wakeup_from_low_power) { - uint32_t save = save_and_disable_interrupts(); - aon_timer_alarm_handler_t old_handler = aon_timer_alarm_handler; - struct timespec ts_adjusted = *ts; -#if HAS_RP2040_RTC - ((void)wakeup_from_low_power); // don't have a choice - datetime_t dt; - // adjust to after the target time - if (ts_adjusted.tv_nsec) ts_adjusted.tv_sec++; - bool ok = time_to_datetime(ts_adjusted.tv_sec, &dt); - assert(ok); - if (ok) { - rtc_set_alarm(&dt, handler); - } -#elif HAS_POWMAN_TIMER - uint irq_num = aon_timer_get_irq_num(); - powman_timer_disable_alarm(); - // adjust to after the target time - ts_adjusted.tv_nsec += 999999; - if (ts_adjusted.tv_nsec > 1000000000) { - ts_adjusted.tv_nsec -= 1000000000; - ts_adjusted.tv_sec++; - } - if (ts_adjusted.tv_nsec) ts_adjusted.tv_sec++; - if (wakeup_from_low_power) { - powman_enable_alarm_wakeup_at_ms(timespec_to_ms(ts)); - } else { - powman_disable_alarm_wakeup(); - powman_timer_enable_alarm_at_ms(timespec_to_ms(ts)); - } - if (handler) { - irq_set_exclusive_handler(irq_num, powman_timer_irq_handler); - irq_set_enabled(irq_num, true); - } -#else - panic_unsupported(); -#endif - aon_timer_alarm_handler = handler; - restore_interrupts_from_disabled(save); - return old_handler; -} - -void aon_timer_disable_alarm(void) { - irq_set_enabled(aon_timer_get_irq_num(), false); -#if HAS_RP2040_RTC - rtc_disable_alarm(); -#elif HAS_POWMAN_TIMER - powman_timer_disable_alarm(); -#else - panic_unsupported(); -#endif -} - -void aon_timer_start_with_timeofday(void) { - struct timeval tv; - gettimeofday(&tv, NULL); - struct timespec ts; - ts.tv_sec = tv.tv_sec; - ts.tv_nsec = tv.tv_usec * 1000; - aon_timer_start(&ts); -} - -void aon_timer_start(const struct timespec *ts) { -#if HAS_RP2040_RTC - rtc_init(); - aon_timer_set_time(ts); -#elif HAS_POWMAN_TIMER - // todo how best to allow different configurations; this should just be the default - powman_timer_set_1khz_tick_source_xosc(); - powman_timer_set_ms(timespec_to_ms(ts)); - powman_timer_start(); -#else - panic_unsupported(); -#endif -} - -void aon_timer_stop(void) { -#if HAS_RP2040_RTC - hw_clear_bits(&rtc_hw->ctrl, RTC_CTRL_RTC_ENABLE_BITS); -#elif HAS_POWMAN_TIMER - powman_timer_stop(); -#else - panic_unsupported(); -#endif -} - -void aon_timer_get_resolution(struct timespec *ts) { -#if HAS_RP2040_RTC - ts->tv_sec = 1; - ts->tv_nsec = 0; -#elif HAS_POWMAN_TIMER - ts->tv_sec = 0; - ts->tv_nsec = 1000000000 / 1000; -#else - panic_unsupported(); -#endif -} - -bool aon_timer_is_running(void) { -#if HAS_RP2040_RTC - return rtc_running(); -#elif HAS_POWMAN_TIMER - return powman_timer_is_running(); -#else - panic_unsupported(); -#endif -} diff --git a/lib/main/pico-sdk/rp2_common/pico_aon_timer/include/pico/aon_timer.h b/lib/main/pico-sdk/rp2_common/pico_aon_timer/include/pico/aon_timer.h deleted file mode 100644 index 49a7c2a5d9..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_aon_timer/include/pico/aon_timer.h +++ /dev/null @@ -1,128 +0,0 @@ -/* - * Copyright (c) 2024 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _PICO_AON_TIMER_H -#define _PICO_AON_TIMER_H - -#include "pico.h" -#include -#include "pico/util/datetime.h" -#include "hardware/regs/intctrl.h" - -/** \file pico/aon_timer.h - * \defgroup pico_aon_timer pico_aon_timer - * - * \brief High Level "Always on Timer" Abstraction - * - * \if rp2040_specific - * This library uses the RTC on RP2040. - * \endif - * \if rp2350_specific - * This library uses the Powman Timer on RP2350. - * \endif - */ - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \def AON_TIMER_IRQ_NUM() - * \ingroup pico_aon_timer - * \hideinitializer - * \brief Returns the \ref irq_num_t for interrupts for the actual hardware backing the AON timer abstraction - * - * Note this macro is intended to resolve at compile time, and does no parameter checking - */ -#ifndef AON_TIMER_IRQ_NUM -#if HAS_RP2040_RTC -#define AON_TIMER_IRQ_NUM() RTC_IRQ -#elif HAS_POWMAN_TIMER -#define AON_TIMER_IRQ_NUM() POWMAN_IRQ_TIMER -#endif -#endif - -typedef void (*aon_timer_alarm_handler_t)(void); - -/** - * \brief Start the AON timer running using the result from the gettimeofday() function as the current time - * \ingroup pico_aon_timer - */ -void aon_timer_start_with_timeofday(void); - -/** - * \brief Start the AON timer running using the specified timespec as the current time - * \ingroup pico_aon_timer - * \param ts the current time - */ -void aon_timer_start(const struct timespec *ts); - -/** - * \brief Stop the AON timer - * \ingroup pico_aon_timer - */ -void aon_timer_stop(void); - -/** - * \brief Update the current time of the AON timer - * \ingroup pico_aon_timer - * \param ts the new current time - */ -void aon_timer_set_time(const struct timespec *ts); - -/** - * \brief Get the current time of the AON timer - * \ingroup pico_aon_timer - * \param ts out value for the current time - */ -void aon_timer_get_time(struct timespec *ts); - -/** - * \brief Get the resolution of the AON timer - * \ingroup pico_aon_timer - * \param ts out value for the resolution of the AON timer - */ -void aon_timer_get_resolution(struct timespec *ts); - -/** - * \brief Enable an AON timer alarm for a specified time - * \ingroup pico_aon_timer - * - * \if rp2040_specific - * On RP2040 the alarm will not fire if it is in the past - * \endif - * \if rp2350_specific - * On RP2350 the alarm will fire if it is in the past - * \endif - * - * \param ts the alarm time - * \param handler a callback to call when the timer fires (may be NULL for wakeup_from_low_power = true) - * \param wakeup_from_low_power true if the AON timer is to be used to wake up from a DORMANT state - */ -aon_timer_alarm_handler_t aon_timer_enable_alarm(const struct timespec *ts, aon_timer_alarm_handler_t handler, bool wakeup_from_low_power); - -/** - * \brief Disable the currently enabled AON timer alarm if any - * \ingroup pico_aon_timer - */ -void aon_timer_disable_alarm(void); - -/** - * \brief Disable the currently enabled AON timer alarm if any - * \ingroup pico_aon_timer - * \return true if the AON timer is running - */ -bool aon_timer_is_running(void); - -static inline uint aon_timer_get_irq_num(void) { - return AON_TIMER_IRQ_NUM(); -} - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/lib/main/pico-sdk/rp2_common/pico_async_context/async_context_base.c b/lib/main/pico-sdk/rp2_common/pico_async_context/async_context_base.c deleted file mode 100644 index 9e385471a6..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_async_context/async_context_base.c +++ /dev/null @@ -1,123 +0,0 @@ -/* - * Copyright (c) 2022 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "pico/async_context_base.h" - -bool async_context_base_add_at_time_worker(async_context_t *self, async_at_time_worker_t *worker) { - async_at_time_worker_t **prev = &self->at_time_list; - while (*prev) { - if (worker == *prev) { - return false; - } - prev = &(*prev)->next; - } - *prev = worker; - worker->next = NULL; - return true; -} - -bool async_context_base_remove_at_time_worker(async_context_t *self, async_at_time_worker_t *worker) { - async_at_time_worker_t **prev = &self->at_time_list; - while (*prev) { - if (worker == *prev) { - *prev = worker->next; - return true; - } - prev = &(*prev)->next; - } - return false; -} - -bool async_context_base_add_when_pending_worker(async_context_t *self, async_when_pending_worker_t *worker) { - async_when_pending_worker_t **prev = &self->when_pending_list; - while (*prev) { - if (worker == *prev) { - return false; - } - prev = &(*prev)->next; - } - *prev = worker; - worker->next = NULL; - return true; -} - -bool async_context_base_remove_when_pending_worker(async_context_t *self, async_when_pending_worker_t *worker) { - async_when_pending_worker_t **prev = &self->when_pending_list; - while (*prev) { - if (worker == *prev) { - *prev = worker->next; - return true; - } - prev = &(*prev)->next; - } - return false; -} - -async_at_time_worker_t *async_context_base_remove_ready_at_time_worker(async_context_t *self) { - async_at_time_worker_t **best_prev = NULL; - if (self->at_time_list) { - absolute_time_t earliest = get_absolute_time(); - for (async_at_time_worker_t **prev = &self->at_time_list; *prev; prev = &(*prev)->next) { - if (absolute_time_diff_us((*prev)->next_time, earliest) >= 0) { - earliest = (*prev)->next_time; - assert(!is_at_the_end_of_time(earliest)); // should never be less than now - best_prev = prev; - } - } - } - async_at_time_worker_t *rc; - if (best_prev) { - rc = *best_prev; - *best_prev = rc->next; - } else { - rc = NULL; - } - return rc; -} - -void async_context_base_refresh_next_timeout(async_context_t *self) { - absolute_time_t earliest = at_the_end_of_time; - for (async_at_time_worker_t *worker = self->at_time_list; worker; ) { - async_at_time_worker_t *next = worker->next; - if (absolute_time_diff_us(worker->next_time, earliest) > 0) { - earliest = worker->next_time; - } - worker = next; - } - self->next_time = earliest; -} - -absolute_time_t async_context_base_execute_once(async_context_t *self) { - async_at_time_worker_t *at_time_worker; - while (NULL != (at_time_worker = async_context_base_remove_ready_at_time_worker(self))) { - at_time_worker->do_work(self, at_time_worker); - } - for(async_when_pending_worker_t *when_pending_worker = self->when_pending_list; when_pending_worker; when_pending_worker = when_pending_worker->next) { - if (when_pending_worker->work_pending) { - when_pending_worker->work_pending = false; - when_pending_worker->do_work(self, when_pending_worker); - } - } - async_context_base_refresh_next_timeout(self); - return self->next_time; -} - -bool async_context_base_needs_servicing(async_context_t *self) { - absolute_time_t now = get_absolute_time(); - if (self->at_time_list) { - for (async_at_time_worker_t *worker = self->at_time_list; worker; worker = worker->next) { - if (absolute_time_diff_us(worker->next_time, now) >= 0) { - return true; - } - } - } - for(async_when_pending_worker_t *when_pending_worker = self->when_pending_list; when_pending_worker; when_pending_worker = when_pending_worker->next) { - if (when_pending_worker->work_pending) { - return true; - } - } - return false; -} \ No newline at end of file diff --git a/lib/main/pico-sdk/rp2_common/pico_async_context/async_context_freertos.c b/lib/main/pico-sdk/rp2_common/pico_async_context/async_context_freertos.c deleted file mode 100644 index a4304d4763..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_async_context/async_context_freertos.c +++ /dev/null @@ -1,295 +0,0 @@ -/* - * Copyright (c) 2022 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include "pico/async_context_freertos.h" -#include "pico/async_context_base.h" -#include "pico/sync.h" -#include "hardware/irq.h" - -#include "semphr.h" - -#if configNUMBER_OF_CORES > 1 && !defined(configUSE_CORE_AFFINITY) -#error async_context_freertos requires configUSE_CORE_AFFINITY under SMP -#endif - -static const async_context_type_t template; - -static void async_context_freertos_acquire_lock_blocking(async_context_t *self_base); -static void async_context_freertos_release_lock(async_context_t *self_base); -static void async_context_freertos_lock_check(async_context_t *self_base); - -static TickType_t sensible_ticks_until(absolute_time_t until) { - TickType_t ticks; - int64_t delay_us = absolute_time_diff_us(get_absolute_time(), until); - if (delay_us <= 0) { - ticks = 0; - } else { - static const uint32_t max_delay = 60000000; - uint32_t delay_us_32 = delay_us > max_delay ? max_delay : (uint32_t) delay_us; - ticks = pdMS_TO_TICKS((delay_us_32+999)/1000); - // we want to round up, as both rounding down to zero is wrong (may produce no delays - // where delays are needed), but also we don't want to wake up, and then realize there - // is no work to do yet! - ticks++; - } - return ticks; -} - -static void process_under_lock(async_context_freertos_t *self) { -#ifndef NDEBUG - async_context_freertos_lock_check(&self->core); -#endif - bool repeat; - do { - repeat = false; - absolute_time_t next_time = async_context_base_execute_once(&self->core); - TickType_t ticks; - if (is_at_the_end_of_time(next_time)) { - ticks = portMAX_DELAY; - } else { - ticks = sensible_ticks_until(next_time); - } - if (ticks) { - // last parameter (timeout) is also 'ticks', since there is no point waiting to change the period - // for longer than the period itself! - repeat = pdFALSE == xTimerChangePeriod(self->timer_handle, ticks, ticks); - } else { - repeat = true; - } - } while (repeat); -} - -static void async_context_task(__unused void *vself) { - async_context_freertos_t *self = (async_context_freertos_t *)vself; - do { - ulTaskNotifyTake(pdFALSE, portMAX_DELAY); - if (self->task_should_exit) break; - async_context_freertos_acquire_lock_blocking(&self->core); - process_under_lock(self); - async_context_freertos_release_lock(&self->core); - __sev(); // it is possible regular code is waiting on a WFE on the other core - } while (!self->task_should_exit); - vTaskDelete(NULL); -} - -static void async_context_freertos_wake_up(async_context_t *self_base) { - async_context_freertos_t *self = (async_context_freertos_t *)self_base; - if (self->task_handle) { - if (portCHECK_IF_IN_ISR()) { - vTaskNotifyGiveFromISR(self->task_handle, NULL); - xSemaphoreGiveFromISR(self->work_needed_sem, NULL); - } else { - // we don't want to wake ourselves up (we will only ever be called - // from the async_context_task if we own the lock, in which case processing - // will already happen when the lock is finally unlocked - if (xTaskGetCurrentTaskHandle() != self->task_handle) { - xTaskNotifyGive(self->task_handle); - xSemaphoreGive(self->work_needed_sem); - } else { -#ifndef NDEBUG - async_context_freertos_lock_check(self_base); -#endif - } - } - } -} - -static void timer_handler(__unused TimerHandle_t handle) -{ - async_context_freertos_t *self = (async_context_freertos_t *)pvTimerGetTimerID(handle); - async_context_freertos_wake_up(&self->core); -} - -bool async_context_freertos_init(async_context_freertos_t *self, async_context_freertos_config_t *config) { - memset(self, 0, sizeof(*self)); - self->core.type = &template; - self->core.flags = ASYNC_CONTEXT_FLAG_CALLBACK_FROM_NON_IRQ; - self->core.core_num = get_core_num(); - self->lock_mutex = xSemaphoreCreateRecursiveMutex(); - self->work_needed_sem = xSemaphoreCreateBinary(); - self->timer_handle = xTimerCreate( "async_context_timer", // Just a text name, not used by the kernel. - portMAX_DELAY, - pdFALSE, // The timers will auto-reload themselves when they expire. - self, - timer_handler); - - if (!self->lock_mutex || - !self->work_needed_sem || - !self->timer_handle || - pdPASS != xTaskCreate(async_context_task, "async_context_task", config->task_stack_size, self, - config->task_priority, &self->task_handle)) { - async_context_deinit(&self->core); - return false; - } -#if configNUMBER_OF_CORES > 1 - UBaseType_t core_id = config->task_core_id; - if (core_id == (UBaseType_t)-1) { - core_id = portGET_CORE_ID(); - } - // we must run on a single core - vTaskCoreAffinitySet(self->task_handle, 1u << core_id); -#endif - return true; -} - -static uint32_t end_task_func(void *param) { - async_context_freertos_t *self = (async_context_freertos_t *)param; - // we will immediately exit - self->task_should_exit = true; - return 0; -} - -void async_context_freertos_deinit(async_context_t *self_base) { - async_context_freertos_t *self = (async_context_freertos_t *)self_base; - if (self->task_handle) { - async_context_execute_sync(self_base, end_task_func, self_base); - } - if (self->timer_handle) { - xTimerDelete(self->timer_handle, 0); - } - if (self->lock_mutex) { - vSemaphoreDelete(self->lock_mutex); - } - if (self->work_needed_sem) { - vSemaphoreDelete(self->work_needed_sem); - } - memset(self, 0, sizeof(*self)); -} - -void async_context_freertos_acquire_lock_blocking(async_context_t *self_base) { - async_context_freertos_t *self = (async_context_freertos_t *)self_base; - // Lock the other core and stop low_prio_irq running - assert(!portCHECK_IF_IN_ISR()); - xSemaphoreTakeRecursive(self->lock_mutex, portMAX_DELAY); - self->nesting++; -} - -void async_context_freertos_lock_check(__unused async_context_t *self_base) { -#ifndef NDEBUG - async_context_freertos_t *self = (async_context_freertos_t *)self_base; - // Lock the other core and stop low_prio_irq running - assert(xSemaphoreGetMutexHolder(self->lock_mutex) == xTaskGetCurrentTaskHandle()); -#endif -} - -typedef struct sync_func_call{ - async_when_pending_worker_t worker; - SemaphoreHandle_t sem; - uint32_t (*func)(void *param); - void *param; - uint32_t rc; -} sync_func_call_t; - -static void handle_sync_func_call(async_context_t *context, async_when_pending_worker_t *worker) { - sync_func_call_t *call = (sync_func_call_t *)worker; - call->rc = call->func(call->param); - xSemaphoreGive(call->sem); - async_context_remove_when_pending_worker(context, worker); -} - -uint32_t async_context_freertos_execute_sync(async_context_t *self_base, uint32_t (*func)(void *param), void *param) { - async_context_freertos_t *self = (async_context_freertos_t*)self_base; - hard_assert(xSemaphoreGetMutexHolder(self->lock_mutex) != xTaskGetCurrentTaskHandle()); - sync_func_call_t call; - call.worker.do_work = handle_sync_func_call; - call.func = func; - call.param = param; - call.sem = xSemaphoreCreateBinary(); - async_context_add_when_pending_worker(self_base, &call.worker); - async_context_set_work_pending(self_base, &call.worker); - xSemaphoreTake(call.sem, portMAX_DELAY); - vSemaphoreDelete(call.sem); - return call.rc; -} - -void async_context_freertos_release_lock(async_context_t *self_base) { - async_context_freertos_t *self = (async_context_freertos_t *)self_base; - bool do_wakeup = false; - if (self->nesting == 1) { - // note that we always do a processing on outermost lock exit, to facilitate cases - // like lwIP where we have no notification when lwIP timers are added. - // - // this operation must be done from the right task - if (self->task_handle != xTaskGetCurrentTaskHandle()) { - // note we defer the wakeup until after we release the lock, otherwise it can be wasteful - // (waking up the task, but then having it block immediately on us) - do_wakeup = true; - } else { - process_under_lock(self); - } - } - --self->nesting; - xSemaphoreGiveRecursive(self->lock_mutex); - if (do_wakeup) { - async_context_freertos_wake_up(self_base); - } -} - -static bool async_context_freertos_add_at_time_worker(async_context_t *self_base, async_at_time_worker_t *worker) { - async_context_freertos_acquire_lock_blocking(self_base); - bool rc = async_context_base_add_at_time_worker(self_base, worker); - async_context_freertos_release_lock(self_base); - return rc; -} - -static bool async_context_freertos_remove_at_time_worker(async_context_t *self_base, async_at_time_worker_t *worker) { - async_context_freertos_acquire_lock_blocking(self_base); - bool rc = async_context_base_remove_at_time_worker(self_base, worker); - async_context_freertos_release_lock(self_base); - return rc; -} - -static bool async_context_freertos_add_when_pending_worker(async_context_t *self_base, async_when_pending_worker_t *worker) { - async_context_freertos_acquire_lock_blocking(self_base); - bool rc = async_context_base_add_when_pending_worker(self_base, worker); - async_context_freertos_release_lock(self_base); - return rc; -} - -static bool async_context_freertos_remove_when_pending_worker(async_context_t *self_base, async_when_pending_worker_t *worker) { - async_context_freertos_acquire_lock_blocking(self_base); - bool rc = async_context_base_remove_when_pending_worker(self_base, worker); - async_context_freertos_release_lock(self_base); - return rc; -} - -static void async_context_freertos_set_work_pending(async_context_t *self_base, async_when_pending_worker_t *worker) { - worker->work_pending = true; - async_context_freertos_wake_up(self_base); -} - -static void async_context_freertos_wait_until(__unused async_context_t *self_base, absolute_time_t until) { - assert(!portCHECK_IF_IN_ISR()); - TickType_t ticks = sensible_ticks_until(until); - vTaskDelay(ticks); -} - -static void async_context_freertos_wait_for_work_until(async_context_t *self_base, absolute_time_t until) { - async_context_freertos_t *self = (async_context_freertos_t *)self_base; - assert(!portCHECK_IF_IN_ISR()); - while (!time_reached(until)) { - TickType_t ticks = sensible_ticks_until(until); - if (!ticks || xSemaphoreTake(self->work_needed_sem, ticks)) return; - } -} - -static const async_context_type_t template = { - .type = ASYNC_CONTEXT_FREERTOS, - .acquire_lock_blocking = async_context_freertos_acquire_lock_blocking, - .release_lock = async_context_freertos_release_lock, - .lock_check = async_context_freertos_lock_check, - .execute_sync = async_context_freertos_execute_sync, - .add_at_time_worker = async_context_freertos_add_at_time_worker, - .remove_at_time_worker = async_context_freertos_remove_at_time_worker, - .add_when_pending_worker = async_context_freertos_add_when_pending_worker, - .remove_when_pending_worker = async_context_freertos_remove_when_pending_worker, - .set_work_pending = async_context_freertos_set_work_pending, - .poll = 0, - .wait_until = async_context_freertos_wait_until, - .wait_for_work_until = async_context_freertos_wait_for_work_until, - .deinit = async_context_freertos_deinit, -}; diff --git a/lib/main/pico-sdk/rp2_common/pico_async_context/async_context_poll.c b/lib/main/pico-sdk/rp2_common/pico_async_context/async_context_poll.c deleted file mode 100644 index 47991b40d6..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_async_context/async_context_poll.c +++ /dev/null @@ -1,73 +0,0 @@ -/* - * Copyright (c) 2022 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include "pico/async_context_poll.h" -#include "pico/async_context_base.h" -#include "pico/sync.h" - -static void noop(__unused async_context_t *context) { } - -static const async_context_type_t template; - -bool async_context_poll_init_with_defaults(async_context_poll_t *self) { - memset(self, 0, sizeof(*self)); - self->core.core_num = get_core_num(); - self->core.type = &template; - self->core.flags = ASYNC_CONTEXT_FLAG_POLLED | ASYNC_CONTEXT_FLAG_CALLBACK_FROM_NON_IRQ; - sem_init(&self->sem, 1, 1); - return true; -} - -static void async_context_poll_wake_up(async_context_t *self_base) { - sem_release(&((async_context_poll_t *)self_base)->sem); -} - -static void async_context_poll_requires_update(async_context_t *self_base, async_when_pending_worker_t *worker) { - worker->work_pending = true; - async_context_poll_wake_up(self_base); -} - -static void async_context_poll_poll(async_context_t *self_base) { - async_context_base_execute_once(self_base); -} - -static void async_context_poll_wait_until(__unused async_context_t *self_base, absolute_time_t until) { - sleep_until(until); -} - -static void async_context_poll_wait_for_work_until(async_context_t *self_base, absolute_time_t until) { - absolute_time_t next_time = self_base->next_time; - async_context_poll_t *self = (async_context_poll_t *)self_base; - sem_acquire_block_until(&self->sem, absolute_time_min(next_time, until)); -} - -static void async_context_poll_lock_check(async_context_t *self_base) { - if (__get_current_exception() || get_core_num() != self_base->core_num) { - panic("async_context_poll context check failed (IRQ or wrong core)"); - } -} - -uint32_t async_context_poll_execute_sync(__unused async_context_t *context, uint32_t (*func)(void *param), void *param) { - return func(param); -} - -static const async_context_type_t template = { - .type = ASYNC_CONTEXT_POLL, - .acquire_lock_blocking = noop, - .release_lock = noop, - .lock_check = async_context_poll_lock_check, - .execute_sync = async_context_poll_execute_sync, - .add_at_time_worker = async_context_base_add_at_time_worker, - .remove_at_time_worker = async_context_base_remove_at_time_worker, - .add_when_pending_worker = async_context_base_add_when_pending_worker, - .remove_when_pending_worker = async_context_base_remove_when_pending_worker, - .set_work_pending = async_context_poll_requires_update, - .poll = async_context_poll_poll, - .wait_until = async_context_poll_wait_until, - .wait_for_work_until = async_context_poll_wait_for_work_until, - .deinit = noop, -}; diff --git a/lib/main/pico-sdk/rp2_common/pico_async_context/async_context_threadsafe_background.c b/lib/main/pico-sdk/rp2_common/pico_async_context/async_context_threadsafe_background.c deleted file mode 100644 index 33f3d45c8a..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_async_context/async_context_threadsafe_background.c +++ /dev/null @@ -1,370 +0,0 @@ -/* - * Copyright (c) 2022 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include "pico/async_context_threadsafe_background.h" -#include "pico/async_context_base.h" -#include "pico/sync.h" -#include "hardware/irq.h" - -static const async_context_type_t template; -static async_context_threadsafe_background_t *async_contexts_by_user_irq[NUM_USER_IRQS]; - -static void low_priority_irq_handler(void); -static void process_under_lock(async_context_threadsafe_background_t *self); -static int64_t alarm_handler(alarm_id_t id, void *user_data); - -#ifndef ASYNC_CONTEXT_THREADSAFE_BACKGROUND_DEFAULT_LOW_PRIORITY_IRQ_HANDLER_PRIORITY -#define ASYNC_CONTEXT_THREADSAFE_BACKGROUND_DEFAULT_LOW_PRIORITY_IRQ_HANDLER_PRIORITY PICO_LOWEST_IRQ_PRIORITY -#endif - -#ifndef ASYNC_CONTEXT_THREADSAFE_BACKGROUND_ALARM_POOL_MAX_ALARMS -#define ASYNC_CONTEXT_THREADSAFE_BACKGROUND_ALARM_POOL_MAX_ALARMS 4 -#endif - -async_context_threadsafe_background_config_t async_context_threadsafe_background_default_config(void) { - async_context_threadsafe_background_config_t config = { - .low_priority_irq_handler_priority = ASYNC_CONTEXT_THREADSAFE_BACKGROUND_DEFAULT_LOW_PRIORITY_IRQ_HANDLER_PRIORITY, - .custom_alarm_pool = NULL, - }; - return config; -} - -static inline uint recursive_mutex_enter_count(recursive_mutex_t *mutex) { - return mutex->enter_count; -} - -static inline lock_owner_id_t recursive_mutex_owner(recursive_mutex_t *mutex) { - return mutex->owner; -} - -static void async_context_threadsafe_background_wake_up(async_context_t *self_base) { - async_context_threadsafe_background_t *self = (async_context_threadsafe_background_t *)self_base; -#if ASYNC_CONTEXT_THREADSAFE_BACKGROUND_MULTI_CORE - if (self_base->core_num == get_core_num()) { - // on same core, can dispatch directly - irq_set_pending(self->low_priority_irq_num); - } else { - // remove the existing alarm (it may have already fired) so we don't overflow the pool with repeats - // - // note that force_alarm_id is not protected here, however if we miss removing one, they will fire - // almost immediately anyway (since they were set in the past) - alarm_id_t force_alarm_id = self->force_alarm_id; - if (force_alarm_id > 0) { - alarm_pool_cancel_alarm(self->alarm_pool, force_alarm_id); - } - // we cause an early timeout (0 is always in the past) on the alarm_pool core - // note that by the time this returns, the timer may already have fired, so we - // may end up setting self->force_alarm_id to a stale timer id, but that is fine as we - // will harmlessly cancel it again next time - self->force_alarm_id = alarm_pool_add_alarm_at_force_in_context(self->alarm_pool, from_us_since_boot(0), - alarm_handler, self); - } -#else - // on same core, can dispatch directly - irq_set_pending(self->low_priority_irq_num); -#endif - sem_release(&self->work_needed_sem); -} - -// Prevent background processing in pensv and access by the other core -// These methods are called in pensv context and on either core -// They can be called recursively -static inline void lock_acquire(async_context_threadsafe_background_t *self) { - // Lock the other core and stop low_prio_irq running - recursive_mutex_enter_blocking(&self->lock_mutex); -} - -static void async_context_threadsafe_background_lock_check(async_context_t *self_base) { - async_context_threadsafe_background_t *self = (async_context_threadsafe_background_t *)self_base; - // Lock the other core and stop low_prio_irq running - if (recursive_mutex_enter_count(&self->lock_mutex) < 1 || recursive_mutex_owner(&self->lock_mutex) != lock_get_caller_owner_id()) { - panic_compact("async_context lock_check failed"); - } -} - -#if ASYNC_CONTEXT_THREADSAFE_BACKGROUND_MULTI_CORE -typedef struct sync_func_call{ - async_when_pending_worker_t worker; - semaphore_t sem; - uint32_t (*func)(void *param); - void *param; - uint32_t rc; -} sync_func_call_t; - -static void handle_sync_func_call(async_context_t *context, async_when_pending_worker_t *worker) { - sync_func_call_t *call = (sync_func_call_t *)worker; - call->rc = call->func(call->param); - sem_release(&call->sem); - async_context_remove_when_pending_worker(context, worker); -} -#endif - -static void lock_release(async_context_threadsafe_background_t *self) { - bool outermost = 1 == recursive_mutex_enter_count(&self->lock_mutex); - // note that it is *not* a requirement to have low_prio_irq_missed handled on the - // same core and in low-priority riq, as we are only *logically* a single thread. the user - // is already free to call from either core, and this would only happen on a different - // core, if the user *themselves* is acquiring the lock from other cores anyway - -#if ASYNC_CONTEXT_THREADSAFE_BACKGROUND_MULTI_CORE - bool wake_other_core = false; -#endif - if (outermost) { - // note that we always do a processing on outermost lock exit, to facilitate cases - // like lwIP where we have no notification when lwIP timers are added. -#if ASYNC_CONTEXT_THREADSAFE_BACKGROUND_MULTI_CORE - if (self->core.core_num == get_core_num()) { - process_under_lock(self); - } else if (async_context_base_needs_servicing(&self->core)) { - // have to wake up other core - wake_other_core = true; - } -#else - process_under_lock(self); -#endif - } - recursive_mutex_exit(&self->lock_mutex); -#if ASYNC_CONTEXT_THREADSAFE_BACKGROUND_MULTI_CORE - if (wake_other_core) { - async_context_threadsafe_background_wake_up(&self->core); - } -#endif -} - -uint32_t async_context_threadsafe_background_execute_sync(async_context_t *self_base, uint32_t (*func)(void *param), void *param) { - async_context_threadsafe_background_t *self = (async_context_threadsafe_background_t*)self_base; -#if ASYNC_CONTEXT_THREADSAFE_BACKGROUND_MULTI_CORE - if (self_base->core_num != get_core_num()) { - hard_assert(!recursive_mutex_enter_count(&self->lock_mutex)); - sync_func_call_t call; - call.worker.do_work = handle_sync_func_call; - call.func = func; - call.param = param; - sem_init(&call.sem, 0, 1); - async_context_add_when_pending_worker(self_base, &call.worker); - async_context_set_work_pending(self_base, &call.worker); - sem_acquire_blocking(&call.sem); - return call.rc; - } -#endif - // short-circuit if we are on the right core - lock_acquire(self); - uint32_t rc = func(param); - lock_release(self); - return rc; -} - -static bool low_prio_irq_init(async_context_threadsafe_background_t *self, uint8_t priority) { - assert(get_core_num() == self->core.core_num); - int irq = user_irq_claim_unused(false); - if (irq < 0) return false; - self->low_priority_irq_num = (uint8_t) irq; - uint index = irq - FIRST_USER_IRQ; - assert(index < count_of(async_contexts_by_user_irq)); - async_contexts_by_user_irq[index] = self; - irq_set_exclusive_handler(self->low_priority_irq_num, low_priority_irq_handler); - irq_set_enabled(self->low_priority_irq_num, true); - irq_set_priority(self->low_priority_irq_num, priority); - return true; -} - -static void low_prio_irq_deinit(async_context_threadsafe_background_t *self) { - if (self->low_priority_irq_num > 0) { - assert(get_core_num() == self->core.core_num); - irq_set_enabled(self->low_priority_irq_num, false); - irq_remove_handler(self->low_priority_irq_num, low_priority_irq_handler); - user_irq_unclaim(self->low_priority_irq_num); - self->low_priority_irq_num = 0; - } -} - -static int64_t alarm_handler(__unused alarm_id_t id, void *user_data) { - async_context_threadsafe_background_t *self = (async_context_threadsafe_background_t*)user_data; -#if ASYNC_CONTEXT_THREADSAFE_BACKGROUND_MULTI_CORE - self->force_alarm_id = 0; -#endif - self->alarm_pending = false; - async_context_threadsafe_background_wake_up(&self->core); - return 0; -} - -bool async_context_threadsafe_background_init(async_context_threadsafe_background_t *self, async_context_threadsafe_background_config_t *config) { - memset(self, 0, sizeof(*self)); - self->core.type = &template; - self->core.flags = ASYNC_CONTEXT_FLAG_CALLBACK_FROM_IRQ | ASYNC_CONTEXT_FLAG_CALLBACK_FROM_NON_IRQ; - self->core.core_num = get_core_num(); - if (config->custom_alarm_pool) { - self->alarm_pool = config->custom_alarm_pool; - } else { -#if PICO_TIME_DEFAULT_ALARM_POOL_DISABLED - self->alarm_pool = alarm_pool_create_with_unused_hardware_alarm(ASYNC_CONTEXT_THREADSAFE_BACKGROUND_ALARM_POOL_MAX_ALARMS); - self->alarm_pool_owned = true; -#else - self->alarm_pool = alarm_pool_get_default(); -#if ASYNC_CONTEXT_THREADSAFE_BACKGROUND_MULTI_CORE - if (self->core.core_num != alarm_pool_core_num(self->alarm_pool)) { - self->alarm_pool = alarm_pool_create_with_unused_hardware_alarm(ASYNC_CONTEXT_THREADSAFE_BACKGROUND_ALARM_POOL_MAX_ALARMS); - self->alarm_pool_owned = true; - } -#endif -#endif - } - assert(self->core.core_num == alarm_pool_core_num(self->alarm_pool)); - sem_init(&self->work_needed_sem, 1, 1); - recursive_mutex_init(&self->lock_mutex); - bool ok = low_prio_irq_init(self, config->low_priority_irq_handler_priority); - return ok; -} - -static void async_context_threadsafe_background_set_work_pending(async_context_t *self_base, async_when_pending_worker_t *worker) { - worker->work_pending = true; - async_context_threadsafe_background_wake_up(self_base); -} - -static void async_context_threadsafe_background_deinit(async_context_t *self_base) { - async_context_threadsafe_background_t *self = (async_context_threadsafe_background_t *)self_base; - // todo we do not currently handle this correctly; we could, but seems like a rare case - assert(get_core_num() == self_base->core_num); - low_prio_irq_deinit(self); - if (self->alarm_id > 0) alarm_pool_cancel_alarm(self->alarm_pool, self->alarm_id); -#if ASYNC_CONTEXT_THREADSAFE_BACKGROUND_MULTI_CORE - if (self->alarm_pool_owned) { - alarm_pool_destroy(self->alarm_pool); - } -#endif - // acquire the lock to make sure the callback is not running (we have already disabled the IRQ - recursive_mutex_enter_blocking(&self->lock_mutex); - recursive_mutex_exit(&self->lock_mutex); - memset(self, 0, sizeof(*self)); -} - -static void process_under_lock(async_context_threadsafe_background_t *self) { -#ifndef NDEBUG - async_context_threadsafe_background_lock_check(&self->core); - assert(self->core.core_num == get_core_num()); -#endif - do { - absolute_time_t next_time = async_context_base_execute_once(&self->core); - // if the next wakeup time is in the past then loop - if (absolute_time_diff_us(get_absolute_time(), next_time) <= 0) continue; - // if there is no next wakeup time, we're done - if (is_at_the_end_of_time(next_time)) { - // cancel the alarm early (we will have been called soon after an alarm wakeup), so that - // we don't risk alarm_id collision. - if (self->alarm_id > 0) { - alarm_pool_cancel_alarm(self->alarm_pool, self->alarm_id); - self->alarm_id = 0; - } - break; - } - // the following is an optimization; we are often called much more frequently than timeouts actually change, - // and removing and re-adding the timers has some non-trivial overhead (10s of microseconds), we choose - // to allow the existing timeout to run to completion, and then re-asses from there, unless the new wakeup - // time is before the last one set. - // - // note that alarm_pending is not protected, however, if it is wrong, it is wrong in the sense that it is - // false when it should be true, so if it is wrong due to a race, we will cancel and re-add the alarm which is safe. - if (self->alarm_pending && absolute_time_diff_us(self->last_set_alarm_time, next_time) > 0) break; - // cancel the existing alarm (it may no longer exist) - if (self->alarm_id > 0) alarm_pool_cancel_alarm(self->alarm_pool, self->alarm_id); - self->last_set_alarm_time = next_time; - self->alarm_pending = true; - self->alarm_id = alarm_pool_add_alarm_at(self->alarm_pool, next_time, alarm_handler, self, false); - if (self->alarm_id > 0) break; - self->alarm_pending = false; - } while (true); -} - -// Low priority interrupt handler to perform background processing -static void low_priority_irq_handler(void) { - uint index = __get_current_exception() - VTABLE_FIRST_IRQ - FIRST_USER_IRQ; - assert(index < count_of(async_contexts_by_user_irq)); - async_context_threadsafe_background_t *self = async_contexts_by_user_irq[index]; - if (!self) return; - assert(self->core.core_num == get_core_num()); - if (recursive_mutex_try_enter(&self->lock_mutex, NULL)) { - // if the recurse count is not 1 then we have pre-empted something which held the lock on the same core, - // so we cannot do processing here (however processing will be done when that lock is released) - if (recursive_mutex_enter_count(&self->lock_mutex) == 1) { - process_under_lock(self); - } - recursive_mutex_exit(&self->lock_mutex); - } -} - -static void async_context_threadsafe_background_wait_until(__unused async_context_t *self_base, absolute_time_t until) { - // can be called in IRQs, in which case we just have to wait - if (__get_current_exception()) { - busy_wait_until(until); - } else { - sleep_until(until); - } -} - -static void async_context_threadsafe_background_wait_for_work_until(async_context_t *self_base, absolute_time_t until) { - async_context_threadsafe_background_t *self = (async_context_threadsafe_background_t *)self_base; - sem_acquire_block_until(&self->work_needed_sem, until); -} - -static bool async_context_threadsafe_background_add_at_time_worker(async_context_t *self_base, async_at_time_worker_t *worker) { - async_context_threadsafe_background_t *self = (async_context_threadsafe_background_t *)self_base; - lock_acquire(self); - bool rc = async_context_base_add_at_time_worker(self_base, worker); - lock_release(self); - return rc; -} - -static bool async_context_threadsafe_background_remove_at_time_worker(async_context_t *self_base, async_at_time_worker_t *worker) { - async_context_threadsafe_background_t *self = (async_context_threadsafe_background_t *)self_base; - lock_acquire(self); - bool rc = async_context_base_remove_at_time_worker(self_base, worker); - lock_release(self); - return rc; -} - -static bool async_context_threadsafe_background_add_when_pending_worker(async_context_t *self_base, async_when_pending_worker_t *worker) { - async_context_threadsafe_background_t *self = (async_context_threadsafe_background_t *)self_base; - lock_acquire(self); - bool rc = async_context_base_add_when_pending_worker(self_base, worker); - lock_release(self); - return rc; -} - -static bool async_context_threadsafe_background_when_pending_worker(async_context_t *self_base, async_when_pending_worker_t *worker) { - async_context_threadsafe_background_t *self = (async_context_threadsafe_background_t *)self_base; - lock_acquire(self); - bool rc = async_context_base_remove_when_pending_worker(self_base, worker); - lock_release(self); - return rc; -} - -static void async_context_threadsafe_background_acquire_lock_blocking(async_context_t *self_base) { - lock_acquire((async_context_threadsafe_background_t *) self_base); -} - -static void async_context_threadsafe_background_release_lock(async_context_t *self_base) { - lock_release((async_context_threadsafe_background_t *)self_base); -} - -static const async_context_type_t template = { - .type = ASYNC_CONTEXT_THREADSAFE_BACKGROUND, - .acquire_lock_blocking = async_context_threadsafe_background_acquire_lock_blocking, - .release_lock = async_context_threadsafe_background_release_lock, - .lock_check = async_context_threadsafe_background_lock_check, - .execute_sync = async_context_threadsafe_background_execute_sync, - .add_at_time_worker = async_context_threadsafe_background_add_at_time_worker, - .remove_at_time_worker = async_context_threadsafe_background_remove_at_time_worker, - .add_when_pending_worker = async_context_threadsafe_background_add_when_pending_worker, - .remove_when_pending_worker = async_context_threadsafe_background_when_pending_worker, - .set_work_pending = async_context_threadsafe_background_set_work_pending, - .poll = 0, - .wait_until = async_context_threadsafe_background_wait_until, - .wait_for_work_until = async_context_threadsafe_background_wait_for_work_until, - .deinit = async_context_threadsafe_background_deinit, -}; - - diff --git a/lib/main/pico-sdk/rp2_common/pico_async_context/include/pico/async_context.h b/lib/main/pico-sdk/rp2_common/pico_async_context/include/pico/async_context.h deleted file mode 100644 index 6f7c4f0dcd..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_async_context/include/pico/async_context.h +++ /dev/null @@ -1,471 +0,0 @@ -/* - * Copyright (c) 2022 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -/** \file pico/async_context.h - * \defgroup pico_async_context pico_async_context - * - * \brief An \ref async_context provides a logically single-threaded context for performing work, and responding - * to asynchronous events. Thus an async_context instance is suitable for servicing third-party libraries - * that are not re-entrant. - * - * The "context" in async_context refers to the fact that when calling workers or timeouts within the - * async_context various pre-conditions hold: - * - *

    - *
  1. That there is a single logical thread of execution; i.e. that the context does not call any worker - * functions concurrently. - *
  2. That the context always calls workers from the same processor core, as most uses of async_context rely on interaction - * with IRQs which are themselves core-specific. - *
- * - * THe async_context provides two mechanisms for asynchronous work: - * - * * when_pending workers, which are processed whenever they have work pending. See \ref async_context_add_when_pending_worker, - * \ref async_context_remove_when_pending_worker, and \ref async_context_set_work_pending, the latter of which can be used from an interrupt handler - * to signal that servicing work is required to be performed by the worker from the regular async_context. - * * at_time workers, that are executed after at a specific time. - * - * Note: "when pending" workers with work pending are executed before "at time" workers. - * - * The async_context provides locking mechanisms, see \ref async_context_acquire_lock_blocking, - * \ref async_context_release_lock and \ref async_context_lock_check which can be used by - * external code to ensure execution of external code does not happen concurrently with worker code. - * Locked code runs on the calling core, however \ref async_context_execute_sync is provided to - * synchronously run a function from the core of the async_context. - * - * The SDK ships with the following default async_contexts: - * - * async_context_poll - this context is not thread-safe, and the user is responsible for calling - * \ref async_context_poll() periodically, and can use async_context_wait_for_work_until() to sleep - * between calls until work is needed if the user has nothing else to do. - * - * async_context_threadsafe_background - in order to work in the background, a low priority IRQ is used - * to handle callbacks. Code is usually invoked from this IRQ context, but may be invoked after any other code - * that uses the async context in another (non-IRQ) context on the same core. Calling \ref async_context_poll() is - * not required, and is a no-op. This context implements async_context locking and is thus safe to call - * from either core, according to the specific notes on each API. - * - * async_context_freertos - Work is performed from a separate "async_context" task, however once again, code may - * also be invoked after a direct use of the async_context on the same core that the async_context belongs to. Calling - * \ref async_context_poll() is not required, and is a no-op. This context implements async_context locking and is thus - * safe to call from any task, and from either core, according to the specific notes on each API. - * - * Each async_context provides bespoke methods of instantiation which are provided in the corresponding headers (e.g. - * async_context_poll.h, async_context_threadsafe_background.h, asycn_context_freertos.h). - * async_contexts are de-initialized by the common async_context_deint() method. - * - * Multiple async_context instances can be used by a single application, and they will operate independently. - */ - -#ifndef _PICO_ASYNC_CONTEXT_H -#define _PICO_ASYNC_CONTEXT_H - -#include "pico.h" -#include "pico/time.h" - -#ifdef __cplusplus -extern "C" { -#endif - -enum { - ASYNC_CONTEXT_POLL = 1, - ASYNC_CONTEXT_THREADSAFE_BACKGROUND = 2, - ASYNC_CONTEXT_FREERTOS = 3, -}; - -typedef struct async_context async_context_t; - -/*! \brief A "timeout" instance used by an async_context - * \ingroup pico_async_context - * - * A "timeout" represents some future action that must be taken at a specific time. - * Its methods are called from the async_context under lock at the given time - * - * \see async_context_add_worker_at - * \see async_context_add_worker_in_ms - */ -typedef struct async_work_on_timeout { - /*! - * \brief private link list pointer - */ - struct async_work_on_timeout *next; - /*! - * \brief Method called when the timeout is reached; may not be NULL - * - * Note, that when this method is called, the timeout has been removed from the async_context, so - * if you want the timeout to repeat, you should re-add it during this callback - * @param context - * @param timeout - */ - void (*do_work)(async_context_t *context, struct async_work_on_timeout *timeout); - /*! - * \brief The next timeout time; this should only be modified during the above methods - * or via async_context methods - */ - absolute_time_t next_time; - /*! - * \brief User data associated with the timeout instance - */ - void *user_data; -} async_at_time_worker_t; - -/*! \brief A "worker" instance used by an async_context - * \ingroup pico_async_context - * - * A "worker" represents some external entity that must do work in response - * to some external stimulus (usually an IRQ). - * Its methods are called from the async_context under lock at the given time - * - * \see async_context_add_worker_at - * \see async_context_add_worker_in_ms - */ -typedef struct async_when_pending_worker { - /*! - * \brief private link list pointer - */ - struct async_when_pending_worker *next; - /*! - * \brief Called by the async_context when the worker has been marked as having "work pending" - * - * @param context the async_context - * @param worker the function to be called when work is pending - */ - void (*do_work)(async_context_t *context, struct async_when_pending_worker *worker); - /** - * \brief True if the worker need do_work called - */ - bool work_pending; - /*! - * \brief User data associated with the worker instance - */ - void *user_data; -} async_when_pending_worker_t; - -#define ASYNC_CONTEXT_FLAG_CALLBACK_FROM_NON_IRQ 0x1 -#define ASYNC_CONTEXT_FLAG_CALLBACK_FROM_IRQ 0x2 -#define ASYNC_CONTEXT_FLAG_POLLED 0x4 - -/*! - * \brief Implementation of an async_context type, providing methods common to that type - * \ingroup pico_async_context - */ -typedef struct async_context_type { - uint16_t type; - // see wrapper functions for documentation - void (*acquire_lock_blocking)(async_context_t *self); - void (*release_lock)(async_context_t *self); - void (*lock_check)(async_context_t *self); - uint32_t (*execute_sync)(async_context_t *context, uint32_t (*func)(void *param), void *param); - bool (*add_at_time_worker)(async_context_t *self, async_at_time_worker_t *worker); - bool (*remove_at_time_worker)(async_context_t *self, async_at_time_worker_t *worker); - bool (*add_when_pending_worker)(async_context_t *self, async_when_pending_worker_t *worker); - bool (*remove_when_pending_worker)(async_context_t *self, async_when_pending_worker_t *worker); - void (*set_work_pending)(async_context_t *self, async_when_pending_worker_t *worker); - void (*poll)(async_context_t *self); // may be NULL - void (*wait_until)(async_context_t *self, absolute_time_t until); - void (*wait_for_work_until)(async_context_t *self, absolute_time_t until); - void (*deinit)(async_context_t *self); -} async_context_type_t; - -/*! - * \brief Base structure type of all async_contexts. For details about its use, see \ref pico_async_context. - * \ingroup pico_async_context - * - * Individual async_context_types with additional state, should contain this structure at the start. - */ -struct async_context { - const async_context_type_t *type; - async_when_pending_worker_t *when_pending_list; - async_at_time_worker_t *at_time_list; - absolute_time_t next_time; - uint16_t flags; - uint8_t core_num; -}; - -/*! - * \brief Acquire the async_context lock - * \ingroup pico_async_context - * - * The owner of the async_context lock is the logic owner of the async_context - * and other work related to this async_context will not happen concurrently. - * - * This method may be called in a nested fashion by the the lock owner. - * - * \note the async_context lock is nestable by the same caller, so an internal count is maintained - * - * \note for async_contexts that provide locking (not async_context_poll), this method is threadsafe. and may be called from within any - * worker method called by the async_context or from any other non-IRQ context. - * - * \param context the async_context - * - * \see async_context_release_lock - */ -static inline void async_context_acquire_lock_blocking(async_context_t *context) { - context->type->acquire_lock_blocking(context); -} - -/*! - * \brief Release the async_context lock - * \ingroup pico_async_context - * - * \note the async_context lock may be called in a nested fashion, so an internal count is maintained. On the outermost - * release, When the outermost lock is released, a check is made for work which might have been skipped while the lock was held, - * and any such work may be performed during this call IF the call is made from the same core that the async_context belongs to. - * - * \note for async_contexts that provide locking (not async_context_poll), this method is threadsafe. and may be called from within any - * worker method called by the async_context or from any other non-IRQ context. - * - * \param context the async_context - * - * \see async_context_acquire_lock_blocking - */ -static inline void async_context_release_lock(async_context_t *context) { - context->type->release_lock(context); -} - -/*! - * \brief Assert if the caller does not own the lock for the async_context - * \ingroup pico_async_context - * \note this method is thread-safe - * - * \param context the async_context - */ -static inline void async_context_lock_check(async_context_t *context) { - context->type->lock_check(context); -} - -/*! - * \brief Execute work synchronously on the core the async_context belongs to. - * \ingroup pico_async_context - * - * This method is intended for code external to the async_context (e.g. another thread/task) to - * execute a function with the same guarantees (single core, logical thread of execution) that - * async_context workers are called with. - * - * \note you should NOT call this method while holding the async_context's lock - * - * \param context the async_context - * \param func the function to call - * \param param the parameter to pass to the function - * \return the return value from func - */ -static inline uint32_t async_context_execute_sync(async_context_t *context, uint32_t (*func)(void *param), void *param) { - return context->type->execute_sync(context, func, param); -} - -/*! - * \brief Add an "at time" worker to a context - * \ingroup pico_async_context - * - * An "at time" worker will run at or after a specific point in time, and is automatically when (just before) it runs. - * - * The time to fire is specified in the next_time field of the worker. - * - * \note for async_contexts that provide locking (not async_context_poll), this method is threadsafe. and may be called from within any - * worker method called by the async_context or from any other non-IRQ context. - * - * \param context the async_context - * \param worker the "at time" worker to add - * \return true if the worker was added, false if the worker was already present. - */ -static inline bool async_context_add_at_time_worker(async_context_t *context, async_at_time_worker_t *worker) { - return context->type->add_at_time_worker(context, worker); -} - -/*! - * \brief Add an "at time" worker to a context - * \ingroup pico_async_context - * - * An "at time" worker will run at or after a specific point in time, and is automatically when (just before) it runs. - * - * The time to fire is specified by the at parameter. - * - * \note for async_contexts that provide locking (not async_context_poll), this method is threadsafe. and may be called from within any - * worker method called by the async_context or from any other non-IRQ context. - * - * \param context the async_context - * \param worker the "at time" worker to add - * \param at the time to fire at - * \return true if the worker was added, false if the worker was already present. - */ -static inline bool async_context_add_at_time_worker_at(async_context_t *context, async_at_time_worker_t *worker, absolute_time_t at) { - worker->next_time = at; - return context->type->add_at_time_worker(context, worker); -} - -/*! - * \brief Add an "at time" worker to a context - * \ingroup pico_async_context - * - * An "at time" worker will run at or after a specific point in time, and is automatically when (just before) it runs. - * - * The time to fire is specified by a delay via the ms parameter - * - * \note for async_contexts that provide locking (not async_context_poll), this method is threadsafe. and may be called from within any - * worker method called by the async_context or from any other non-IRQ context. - * - * \param context the async_context - * \param worker the "at time" worker to add - * \param ms the number of milliseconds from now to fire after - * \return true if the worker was added, false if the worker was already present. - */ -static inline bool async_context_add_at_time_worker_in_ms(async_context_t *context, async_at_time_worker_t *worker, uint32_t ms) { - worker->next_time = make_timeout_time_ms(ms); - return context->type->add_at_time_worker(context, worker); -} - -/*! - * \brief Remove an "at time" worker from a context - * \ingroup pico_async_context - * - * \note for async_contexts that provide locking (not async_context_poll), this method is threadsafe. and may be called from within any - * worker method called by the async_context or from any other non-IRQ context. - * - * \param context the async_context - * \param worker the "at time" worker to remove - * \return true if the worker was removed, false if the instance not present. - */ -static inline bool async_context_remove_at_time_worker(async_context_t *context, async_at_time_worker_t *worker) { - return context->type->remove_at_time_worker(context, worker); -} - -/*! - * \brief Add a "when pending" worker to a context - * \ingroup pico_async_context - * - * An "when pending" worker will run when it is pending (can be set via \ref async_context_set_work_pending), and - * is NOT automatically removed when it runs. - * - * The time to fire is specified by a delay via the ms parameter - * - * \note for async_contexts that provide locking (not async_context_poll), this method is threadsafe. and may be called from within any - * worker method called by the async_context or from any other non-IRQ context. - * - * \param context the async_context - * \param worker the "when pending" worker to add - * \return true if the worker was added, false if the worker was already present. - */ -static inline bool async_context_add_when_pending_worker(async_context_t *context, async_when_pending_worker_t *worker) { - return context->type->add_when_pending_worker(context, worker); -} - -/*! - * \brief Remove a "when pending" worker from a context - * \ingroup pico_async_context - * - * \note for async_contexts that provide locking (not async_context_poll), this method is threadsafe. and may be called from within any - * worker method called by the async_context or from any other non-IRQ context. - * - * \param context the async_context - * \param worker the "when pending" worker to remove - * \return true if the worker was removed, false if the instance not present. - */ -static inline bool async_context_remove_when_pending_worker(async_context_t *context, async_when_pending_worker_t *worker) { - return context->type->remove_when_pending_worker(context, worker); -} - -/*! - * \brief Mark a "when pending" worker as having work pending - * \ingroup pico_async_context - * - * The worker will be run from the async_context at a later time. - * - * \note this method may be called from any context including IRQs - * - * \param context the async_context - * \param worker the "when pending" worker to mark as pending. - */ -static inline void async_context_set_work_pending(async_context_t *context, async_when_pending_worker_t *worker) { - context->type->set_work_pending(context, worker); -} - -/*! - * \brief Perform any pending work for polling style async_context - * \ingroup pico_async_context - * - * For a polled async_context (e.g. \ref async_context_poll) the user is responsible for calling this method - * periodically to perform any required work. - * - * This method may immediately perform outstanding work on other context types, but is not required to. - * - * \param context the async_context - */ -static inline void async_context_poll(async_context_t *context) { - if (context->type->poll) context->type->poll(context); -} - -/*! - * \brief sleep until the specified time in an async_context callback safe way - * \ingroup pico_async_context - * - * \note for async_contexts that provide locking (not async_context_poll), this method is threadsafe. and may be called from within any - * worker method called by the async_context or from any other non-IRQ context. - * - * \param context the async_context - * \param until the time to sleep until - */ -static inline void async_context_wait_until(async_context_t *context, absolute_time_t until) { - context->type->wait_until(context, until); -} - -/*! - * \brief Block until work needs to be done or the specified time has been reached - * \ingroup pico_async_context - * - * \note this method should not be called from a worker callback - * - * \param context the async_context - * \param until the time to return at if no work is required - */ -static inline void async_context_wait_for_work_until(async_context_t *context, absolute_time_t until) { - context->type->wait_for_work_until(context, until); -} - -/*! - * \brief Block until work needs to be done or the specified number of milliseconds have passed - * \ingroup pico_async_context - * - * \note this method should not be called from a worker callback - * - * \param context the async_context - * \param ms the number of milliseconds to return after if no work is required - */ -static inline void async_context_wait_for_work_ms(async_context_t *context, uint32_t ms) { - async_context_wait_for_work_until(context, make_timeout_time_ms(ms)); -} - -/*! - * \brief Return the processor core this async_context belongs to - * \ingroup pico_async_context - * - * \param context the async_context - * \return the physical core number - */ -static inline uint async_context_core_num(const async_context_t *context) { - return context->core_num; -} - -/*! - * \brief End async_context processing, and free any resources - * \ingroup pico_async_context - * - * Note the user should clean up any resources associated with workers - * in the async_context themselves. - * - * Asynchronous (non-polled) async_contexts guarantee that no - * callback is being called once this method returns. - * - * \param context the async_context - */ -static inline void async_context_deinit(async_context_t *context) { - context->type->deinit(context); -} - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/lib/main/pico-sdk/rp2_common/pico_async_context/include/pico/async_context_base.h b/lib/main/pico-sdk/rp2_common/pico_async_context/include/pico/async_context_base.h deleted file mode 100644 index a8eeb42d98..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_async_context/include/pico/async_context_base.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * Copyright (c) 2022 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _PICO_ASYNC_CONTEXT_BASE_H -#define _PICO_ASYNC_CONTEXT_BASE_H - -#include "pico/async_context.h" - -#ifdef __cplusplus -extern "C" { -#endif - -// common functions for async_context implementations to use -bool async_context_base_add_at_time_worker(async_context_t *self, async_at_time_worker_t *worker); -bool async_context_base_remove_at_time_worker(async_context_t *self, async_at_time_worker_t *worker); - -bool async_context_base_add_when_pending_worker(async_context_t *self, async_when_pending_worker_t *worker); -bool async_context_base_remove_when_pending_worker(async_context_t *self, async_when_pending_worker_t *worker); - -async_at_time_worker_t *async_context_base_remove_ready_at_time_worker(async_context_t *self); -void async_context_base_refresh_next_timeout(async_context_t *self); - -absolute_time_t async_context_base_execute_once(async_context_t *self); -bool async_context_base_needs_servicing(async_context_t *self); - -#ifdef __cplusplus -} -#endif - -#endif \ No newline at end of file diff --git a/lib/main/pico-sdk/rp2_common/pico_async_context/include/pico/async_context_freertos.h b/lib/main/pico-sdk/rp2_common/pico_async_context/include/pico/async_context_freertos.h deleted file mode 100644 index bc51312582..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_async_context/include/pico/async_context_freertos.h +++ /dev/null @@ -1,129 +0,0 @@ -/* - * Copyright (c) 2022 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _PICO_ASYNC_CONTEXT_FREERTOS_H -#define _PICO_ASYNC_CONTEXT_FREERTOS_H - -/** \file pico/async_context.h - * \defgroup async_context_freertos async_context_freertos - * \ingroup pico_async_context - * - * \brief async_context_freertos provides an implementation of \ref async_context that handles asynchronous - * work in a separate FreeRTOS task. - */ -#include "pico/async_context.h" - -// FreeRTOS includes -#include "FreeRTOS.h" -#include "semphr.h" -#include "timers.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#ifndef ASYNC_CONTEXT_DEFAULT_FREERTOS_TASK_PRIORITY -#define ASYNC_CONTEXT_DEFAULT_FREERTOS_TASK_PRIORITY ( tskIDLE_PRIORITY + 4) -#endif - -#ifndef ASYNC_CONTEXT_DEFAULT_FREERTOS_TASK_STACK_SIZE -#define ASYNC_CONTEXT_DEFAULT_FREERTOS_TASK_STACK_SIZE configMINIMAL_STACK_SIZE -#endif - -typedef struct async_context_freertos async_context_freertos_t; - -#if !defined(configNUMBER_OF_CORES) && defined(configNUM_CORES) -#if !portSUPPORT_SMP -#error configNUMBER_OF_CORES is the new name for configNUM_CORES -#else -// portSUPPORT_SMP was defined in old smp branch -#error configNUMBER_OF_CORES is the new name for configNUM_CORES, however it looks like you may need to define both as you are using an old SMP branch of FreeRTOS -#endif -#endif - -/** - * \brief Configuration object for async_context_freertos instances. - */ -typedef struct async_context_freertos_config { - /** - * \brief Task priority for the async_context task - */ - UBaseType_t task_priority; - /** - * \brief Stack size for the async_context task - */ - configSTACK_DEPTH_TYPE task_stack_size; - /** - * \brief the core ID (see \ref portGET_CORE_ID()) to pin the task to. - * This is only relevant in SMP mode. - */ -#if configUSE_CORE_AFFINITY && configNUMBER_OF_CORES > 1 - UBaseType_t task_core_id; -#endif -} async_context_freertos_config_t; - -struct async_context_freertos { - async_context_t core; - SemaphoreHandle_t lock_mutex; - SemaphoreHandle_t work_needed_sem; - TimerHandle_t timer_handle; - TaskHandle_t task_handle; - uint8_t nesting; - volatile bool task_should_exit; -}; - -/*! - * \brief Initialize an async_context_freertos instance using the specified configuration - * \ingroup async_context_freertos - * - * If this method succeeds (returns true), then the async_context is available for use - * and can be de-initialized by calling async_context_deinit(). - * - * \param self a pointer to async_context_freertos structure to initialize - * \param config the configuration object specifying characteristics for the async_context - * \return true if initialization is successful, false otherwise - */ -bool async_context_freertos_init(async_context_freertos_t *self, async_context_freertos_config_t *config); - -/*! - * \brief Return a copy of the default configuration object used by \ref async_context_freertos_init_with_defaults() - * \ingroup async_context_freertos - * - * The caller can then modify just the settings it cares about, and call \ref async_context_freertos_init() - * \return the default configuration object - */ - static inline async_context_freertos_config_t async_context_freertos_default_config(void) { - async_context_freertos_config_t config = { - .task_priority = ASYNC_CONTEXT_DEFAULT_FREERTOS_TASK_PRIORITY, - .task_stack_size = ASYNC_CONTEXT_DEFAULT_FREERTOS_TASK_STACK_SIZE, -#if configUSE_CORE_AFFINITY && configNUMBER_OF_CORES > 1 - .task_core_id = (UBaseType_t)-1, // none -#endif - }; - return config; - -} - -/*! - * \brief Initialize an async_context_freertos instance with default values - * \ingroup async_context_freertos - * - * If this method succeeds (returns true), then the async_context is available for use - * and can be de-initialized by calling async_context_deinit(). - * - * \param self a pointer to async_context_freertos structure to initialize - * \return true if initialization is successful, false otherwise - */ - static inline bool async_context_freertos_init_with_defaults(async_context_freertos_t *self) { - async_context_freertos_config_t config = async_context_freertos_default_config(); - return async_context_freertos_init(self, &config); -} - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/lib/main/pico-sdk/rp2_common/pico_async_context/include/pico/async_context_poll.h b/lib/main/pico-sdk/rp2_common/pico_async_context/include/pico/async_context_poll.h deleted file mode 100644 index 22745765e4..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_async_context/include/pico/async_context_poll.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * Copyright (c) 2022 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _PICO_ASYNC_CONTEXT_POLL_H -#define _PICO_ASYNC_CONTEXT_POLL_H - -/** \file pico/async_context.h - * \defgroup async_context_poll async_context_poll - * \ingroup pico_async_context - * - * \brief async_context_poll provides an implementation of \ref async_context that is intended for use with a simple - * polling loop on one core. It is not thread safe. - * - * The \ref async_context_poll() method must be called periodically to handle asynchronous work that may now be - * pending. \ref async_context_wait_for_work_until() may be used to block a polling loop until there is work to do, - * and prevent tight spinning. - */ -#include "pico/async_context.h" -#include "pico/sem.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef struct async_context_poll { - async_context_t core; - semaphore_t sem; -} async_context_poll_t; - -/*! - * \brief Initialize an async_context_poll instance with default values - * \ingroup async_context_poll - * - * If this method succeeds (returns true), then the async_context is available for use - * and can be de-initialized by calling async_context_deinit(). - * - * \param self a pointer to async_context_poll structure to initialize - * \return true if initialization is successful, false otherwise - */ -bool async_context_poll_init_with_defaults(async_context_poll_t *self); - -#ifdef __cplusplus -} -#endif - -#endif \ No newline at end of file diff --git a/lib/main/pico-sdk/rp2_common/pico_async_context/include/pico/async_context_threadsafe_background.h b/lib/main/pico-sdk/rp2_common/pico_async_context/include/pico/async_context_threadsafe_background.h deleted file mode 100644 index 1b6b1e0b94..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_async_context/include/pico/async_context_threadsafe_background.h +++ /dev/null @@ -1,112 +0,0 @@ -/* - * Copyright (c) 2022 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _PICO_ASYNC_CONTEXT_THREADSAFE_BACKGROUND_H -#define _PICO_ASYNC_CONTEXT_THREADSAFE_BACKGROUND_H - -/** \file pico/async_context.h - * \defgroup async_context_threadsafe_background async_context_threadsafe_background - * \ingroup pico_async_context - * - * \brief async_context_threadsafe_background provides an implementation of \ref async_context that handles asynchronous - * work in a low priority IRQ, and there is no need for the user to poll for work - * - * \note The workers used with this async_context MUST be safe to call from an IRQ. - */ - -#include "pico/async_context.h" -#include "pico/sem.h" -#include "pico/mutex.h" -#include "hardware/irq.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#ifndef ASYNC_CONTEXT_THREADSAFE_BACKGROUND_MULTI_CORE -#define ASYNC_CONTEXT_THREADSAFE_BACKGROUND_MULTI_CORE LIB_PICO_MULTICORE -#endif - -typedef struct async_context_threadsafe_background async_context_threadsafe_background_t; - -/** - * \brief Configuration object for async_context_threadsafe_background instances. - */ -typedef struct async_context_threadsafe_background_config { -/** - * \brief the priority of the low priority IRQ - */ - uint8_t low_priority_irq_handler_priority; - /** - * \brief a specific alarm pool to use (or NULL to use ta default) - * - * \note this alarm pool MUST be on the same core as the async_context - * - * The default alarm pool used is the "default alarm pool" (see - * \ref alarm_pool_get_default()) if available, and if that is on the same - * core, otherwise a private alarm_pool instance created during - * initialization. - */ - alarm_pool_t *custom_alarm_pool; -} async_context_threadsafe_background_config_t; - -struct async_context_threadsafe_background { - async_context_t core; - alarm_pool_t *alarm_pool; // this must be on the same core as core_num - absolute_time_t last_set_alarm_time; - recursive_mutex_t lock_mutex; - semaphore_t work_needed_sem; - volatile alarm_id_t alarm_id; -#if ASYNC_CONTEXT_THREADSAFE_BACKGROUND_MULTI_CORE - volatile alarm_id_t force_alarm_id; - bool alarm_pool_owned; -#endif - uint8_t low_priority_irq_num; - volatile bool alarm_pending; -}; - -/*! - * \brief Initialize an async_context_threadsafe_background instance using the specified configuration - * \ingroup async_context_threadsafe_background - * - * If this method succeeds (returns true), then the async_context is available for use - * and can be de-initialized by calling async_context_deinit(). - * - * \param self a pointer to async_context_threadsafe_background structure to initialize - * \param config the configuration object specifying characteristics for the async_context - * \return true if initialization is successful, false otherwise - */ -bool async_context_threadsafe_background_init(async_context_threadsafe_background_t *self, async_context_threadsafe_background_config_t *config); - -/*! - * \brief Return a copy of the default configuration object used by \ref async_context_threadsafe_background_init_with_defaults() - * \ingroup async_context_threadsafe_background - * - * The caller can then modify just the settings it cares about, and call \ref async_context_threadsafe_background_init() - * \return the default configuration object - */ -async_context_threadsafe_background_config_t async_context_threadsafe_background_default_config(void); - -/*! - * \brief Initialize an async_context_threadsafe_background instance with default values - * \ingroup async_context_threadsafe_background - * - * If this method succeeds (returns true), then the async_context is available for use - * and can be de-initialized by calling async_context_deinit(). - * - * \param self a pointer to async_context_threadsafe_background structure to initialize - * \return true if initialization is successful, false otherwise - */ -static inline bool async_context_threadsafe_background_init_with_defaults(async_context_threadsafe_background_t *self) { - async_context_threadsafe_background_config_t config = async_context_threadsafe_background_default_config(); - return async_context_threadsafe_background_init(self, &config); -} - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/lib/main/pico-sdk/rp2_common/pico_atomic/atomic.c b/lib/main/pico-sdk/rp2_common/pico_atomic/atomic.c deleted file mode 100644 index 2bbf3cdbd3..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_atomic/atomic.c +++ /dev/null @@ -1,217 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include "pico/sync.h" - -// We use __builtin_mem* to avoid libc dependency. -#define memcpy __builtin_memcpy -#define memcmp __builtin_memcmp - -static inline uint32_t atomic_lock(__unused const volatile void *ptr) { - return spin_lock_blocking(spin_lock_instance(PICO_SPINLOCK_ID_ATOMIC)); -} - -static inline void atomic_unlock(__unused const volatile void *ptr, uint32_t save) { - spin_unlock(spin_lock_instance(PICO_SPINLOCK_ID_ATOMIC), save); -} - -#if PICO_C_COMPILER_IS_GNU - -_Bool __atomic_test_and_set_c(volatile void *mem, __unused int model) { - uint32_t save = atomic_lock(mem); - bool result = *(volatile bool *) mem; - *(volatile bool *) mem = true; - atomic_unlock(mem, save); - return result; -} - -#define __atomic_load_c __atomic_load -#define __atomic_store_c __atomic_store -#define __atomic_exchange_c __atomic_exchange -#define __atomic_compare_exchange_c __atomic_compare_exchange -#define __atomic_is_lock_free_c __atomic_is_lock_free -#else -// Clang objects if you redefine a builtin. -#pragma redefine_extname __atomic_load_c __atomic_load -#pragma redefine_extname __atomic_store_c __atomic_store -#pragma redefine_extname __atomic_exchange_c __atomic_exchange -#pragma redefine_extname __atomic_compare_exchange_c __atomic_compare_exchange -#pragma redefine_extname __atomic_is_lock_free_c __atomic_is_lock_free -#endif - -// Whether atomic operations for the given size (and alignment) are lock-free. -bool __atomic_is_lock_free_c(__unused size_t size, __unused const volatile void *ptr) { -#if !__ARM_ARCH_6M__ - if (size == 1 || size == 2 || size == 4) { - size_t align = size - 1; - return (((uintptr_t)ptr) & align) == 0; - } -#endif - return false; -} - - - -// An atomic load operation. This is atomic with respect to the source pointer only. -void __atomic_load_c(uint size, const volatile void *src, void *dest, __unused int model) { - uint32_t save = atomic_lock(src); - memcpy(dest, remove_volatile_cast_no_barrier(const void *, src), size); - atomic_unlock(src, save); -} - -// An atomic store operation. This is atomic with respect to the destination -// pointer only. -void __atomic_store_c(uint size, volatile void *dest, void *src, __unused int model) { - uint32_t save = atomic_lock(src); - memcpy(remove_volatile_cast_no_barrier(void *, dest), src, size); - atomic_unlock(src, save); -} - -// Atomic compare and exchange operation. If the value at *ptr is identical -// to the value at *expected, then this copies value at *desired to *ptr. If -// they are not, then this stores the current value from *ptr in *expected. -// -// This function returns 1 if the exchange takes place or 0 if it fails. -_Bool __atomic_compare_exchange_c(uint size, volatile void *ptr, void *expected, - void *desired, __unused int success, __unused int failure) { - uint32_t save = atomic_lock(ptr); - if (memcmp(remove_volatile_cast_no_barrier(void *, ptr), expected, size) == 0) { - memcpy(remove_volatile_cast_no_barrier(void *, ptr), desired, size); - atomic_unlock(ptr, save); - return 1; - } - memcpy(expected, remove_volatile_cast_no_barrier(void *, ptr), size); - atomic_unlock(ptr, save); - return 0; -} - -// Performs an atomic exchange operation between two pointers. This is atomic -// with respect to the target address. -void __atomic_exchange_c(uint size, volatile void *ptr, void *val, void *old, __unused int model) { - - uint32_t save = atomic_lock(ptr); - memcpy(old, remove_volatile_cast_no_barrier(void *, ptr), size); - memcpy(remove_volatile_cast_no_barrier(void *, ptr), val, size); - atomic_unlock(ptr, save); -} - -#if __ARM_ARCH_6M__ -#define ATOMIC_OPTIMIZED_CASES \ - ATOMIC_OPTIMIZED_CASE(1, uint8_t) \ - ATOMIC_OPTIMIZED_CASE(2, uint16_t) \ - ATOMIC_OPTIMIZED_CASE(4, uint) \ - ATOMIC_OPTIMIZED_CASE(8, uint64_t) -#else -#define ATOMIC_OPTIMIZED_CASES \ - ATOMIC_OPTIMIZED_CASE(8, uint64_t) -#endif - -#define ATOMIC_OPTIMIZED_CASE(n, type) \ - type __atomic_load_##n(const volatile void *src, __unused int memorder) { \ - uint32_t save = atomic_lock(src); \ - type val = *(const volatile type *)src; \ - atomic_unlock(src, save); \ - return val; \ - } - -ATOMIC_OPTIMIZED_CASES - -#undef ATOMIC_OPTIMIZED_CASE - -#define ATOMIC_OPTIMIZED_CASE(n, type) \ - void __atomic_store_##n(volatile void *dest, type val, __unused int model) { \ - uint32_t save = atomic_lock(dest); \ - *(volatile type *)dest = val; \ - atomic_unlock(dest, save); \ - } - -ATOMIC_OPTIMIZED_CASES - -#undef ATOMIC_OPTIMIZED_CASE - -#define ATOMIC_OPTIMIZED_CASE(n, type) \ - bool __atomic_compare_exchange_##n(volatile void *ptr, void *expected, type desired, \ - __unused bool weak, __unused int success, __unused int failure) { \ - uint32_t save = atomic_lock(ptr); \ - if (*(volatile type *)ptr == *(type *)expected) { \ - *(volatile type *)ptr = desired; \ - atomic_unlock(ptr, save); \ - return true; \ - } \ - *(type *)expected = *(volatile type *)ptr; \ - atomic_unlock(ptr, save); \ - return false; \ - } - -ATOMIC_OPTIMIZED_CASES - -#undef ATOMIC_OPTIMIZED_CASE - -#define ATOMIC_OPTIMIZED_CASE(n, type) \ - type __atomic_exchange_##n(volatile void *dest, type val, __unused int model) { \ - uint32_t save = atomic_lock(dest); \ - type tmp = *(volatile type *)dest; \ - *(volatile type *)dest = val; \ - atomic_unlock(dest, save); \ - return tmp; \ - } - -ATOMIC_OPTIMIZED_CASES - -#undef ATOMIC_OPTIMIZED_CASE - -// Atomic read-modify-write operations for integers of various sizes. - -#define ATOMIC_RMW(n, type, opname, op) \ - type __atomic_fetch_##opname##_##n(volatile void *ptr, type val, __unused int model) { \ - uint32_t save = atomic_lock(ptr); \ - type tmp = *(volatile type *)ptr; \ - *(volatile type *)ptr = tmp op val; \ - atomic_unlock(ptr, save); \ - return tmp; \ - } - -#define ATOMIC_RMW_NAND(n, type) \ - type __atomic_fetch_nand_##n(type *ptr, type val, __unused int model) { \ - uint32_t save = atomic_lock(ptr); \ - type tmp = *ptr; \ - *ptr = ~(tmp & val); \ - atomic_unlock(ptr, save); \ - return tmp; \ - } - -#define ATOMIC_OPTIMIZED_CASE(n, type) ATOMIC_RMW(n, type, add, +) - -ATOMIC_OPTIMIZED_CASES - -#undef ATOMIC_OPTIMIZED_CASE -#define ATOMIC_OPTIMIZED_CASE(n, type) ATOMIC_RMW(n, type, sub, -) - -ATOMIC_OPTIMIZED_CASES - -#undef ATOMIC_OPTIMIZED_CASE -#define ATOMIC_OPTIMIZED_CASE(n, type) ATOMIC_RMW(n, type, and, &) - -ATOMIC_OPTIMIZED_CASES - -#undef ATOMIC_OPTIMIZED_CASE -#define ATOMIC_OPTIMIZED_CASE(n, type) ATOMIC_RMW(n, type, or, |) - -ATOMIC_OPTIMIZED_CASES - -#undef ATOMIC_OPTIMIZED_CASE -#define ATOMIC_OPTIMIZED_CASE(n, type) ATOMIC_RMW(n, type, xor, ^) - -ATOMIC_OPTIMIZED_CASES - -#undef ATOMIC_OPTIMIZED_CASE - -#if __has_builtin(__c11_atomic_fetch_nand) -#define ATOMIC_OPTIMIZED_CASE(n, type) ATOMIC_RMW_NAND(n, type) -ATOMIC_OPTIMIZED_CASES -#undef ATOMIC_OPTIMIZED_CASE -#endif diff --git a/lib/main/pico-sdk/rp2_common/pico_atomic/include/stdatomic.h b/lib/main/pico-sdk/rp2_common/pico_atomic/include/stdatomic.h deleted file mode 100644 index f5ec4597cd..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_atomic/include/stdatomic.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * Copyright (c) 2024 Raspberry Pi (Trading) Ltd. - * Copyright (c) 2024 Stephen Street (stephen@redrocketcomputing.com). - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef __STDATOMIC_H -#define __STDATOMIC_H - -#ifdef __cplusplus -extern "C" { -#endif - -/** \file stdatomic.h - * \defgroup pico_atomic pico_atomic - * - * \brief Helper implementations for C11 atomics - * - * \if rp2040_specific - * On RP2040 a spin lock is used as protection for all atomic operations, since there is no C library support. - * \endif - * - * \if rp2350_specific - * On RP2350 the C-library provides implementations for all 1-byte, 2-byte and 4-byte atomics using processor - * exclusive operations. This library provides a spin-lock protected version for arbitrary-sized atomics (including 64-bit). - * \endif -*/ -#include -#include_next - -// needed for PICO_C_COMPILER_IS_GNU -#include "pico.h" - -#if PICO_RP2040 && PICO_C_COMPILER_IS_GNU -// on GNU without exclusive instructions these don't get routed thru _1 functions for some reason -#undef atomic_flag_test_and_set -#undef atomic_flag_test_and_set_explicit - -extern _Bool __atomic_test_and_set_c(volatile void *mem, int model); - -#define atomic_flag_test_and_set(PTR) __atomic_test_and_set_c((PTR), __ATOMIC_SEQ_CST) -#define atomic_flag_test_and_set_explicit(PTR, MO) __atomic_test_and_set_c((PTR), (MO)) -#endif - -#ifdef __cplusplus -} -#endif -#endif diff --git a/lib/main/pico-sdk/rp2_common/pico_bit_ops/bit_ops_aeabi.S b/lib/main/pico-sdk/rp2_common/pico_bit_ops/bit_ops_aeabi.S deleted file mode 100644 index 65a1bb4c97..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_bit_ops/bit_ops_aeabi.S +++ /dev/null @@ -1,190 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "pico/asm_helper.S" -#include "pico/bootrom.h" -#include "pico/runtime_init.h" - -pico_default_asm_setup - -.macro bits_section name -#if PICO_BITS_IN_RAM -.section RAM_SECTION_NAME(\name), "ax" -#else -.section SECTION_NAME(\name), "ax" -#endif -.endm - -#if PICO_RP2040 -PICO_RUNTIME_INIT_FUNC_RUNTIME(__aeabi_bits_init, PICO_RUNTIME_INIT_AEABI_BIT_OPS) - -.section .data.aeabi_bits_funcs -.global aeabi_bits_funcs, aeabi_bits_funcs_end -.equ BITS_FUNC_COUNT, 4 -.align 4 -aeabi_bits_funcs: - .word ROM_FUNC_POPCOUNT32 - .word ROM_FUNC_CLZ32 - .word ROM_FUNC_CTZ32 - .word ROM_FUNC_REVERSE32 -aeabi_bits_funcs_end: - -.section .text -.thumb_func -__aeabi_bits_init: - ldr r0, =aeabi_bits_funcs - movs r1, #BITS_FUNC_COUNT - ldr r3, =rom_funcs_lookup - bx r3 - -.equ POPCOUNT32, 0 -.equ CLZ32, 4 -.equ CTZ32, 8 -.equ REVERSE32, 12 - -bits_section clzsi -wrapper_func __clz -wrapper_func __clzl -wrapper_func __clzsi2 - ldr r3, =aeabi_bits_funcs - ldr r3, [r3, #CLZ32] - bx r3 - -bits_section ctzsi -wrapper_func __ctzsi2 - ldr r3, =aeabi_bits_funcs - ldr r3, [r3, #CTZ32] - bx r3 - -bits_section popcountsi -wrapper_func __popcountsi2 - ldr r3, =aeabi_bits_funcs - ldr r3, [r3, #POPCOUNT32] - bx r3 - -bits_section clzdi -wrapper_func __clzll -wrapper_func __clzdi2 - ldr r3, =aeabi_bits_funcs - ldr r3, [r3, #CLZ32] - cmp r1, #0 - bne 1f - push {lr} - blx r3 - adds r0, #32 - pop {pc} -1: - mov r0, r1 - bx r3 - -bits_section ctzdi -wrapper_func __ctzdi2 - ldr r3, =aeabi_bits_funcs - ldr r3, [r3, #CTZ32] - cmp r0, #0 - beq 1f - bx r3 -1: - push {lr} - mov r0, r1 - blx r3 - adds r0, #32 - pop {pc} - -bits_section popcountdi -wrapper_func __popcountdi2 - ldr r3, =aeabi_bits_funcs - ldr r3, [r3, #POPCOUNT32] - push {r1, r3, lr} - blx r3 - mov ip, r0 - pop {r0, r3} - blx r3 - mov r1, ip - add r0, r1 - pop {pc} - -bits_section __rev -regular_func __rev -regular_func __revl -regular_func reverse32 - ldr r3, =aeabi_bits_funcs - ldr r3, [r3, #REVERSE32] - bx r3 - -bits_section __revll -regular_func __revll -regular_func reverse64 - push {lr} - ldr r3, =aeabi_bits_funcs - ldr r3, [r3, #REVERSE32] - push {r1, r3} - blx r3 - mov ip, r0 // reverse32 preserves ip - pop {r0, r3} - blx r3 - mov r1, ip - pop {pc} - -#else // RP2350 - -bits_section __rev -regular_func __rev -regular_func __revl -regular_func reverse32 -#ifdef __riscv - rev8 a0, a0 - brev8 a0, a0 - ret -#else - rbit r0, r0 - bx lr -#endif - -bits_section __revll -regular_func __revll -regular_func reverse64 -#ifdef __riscv - rev8 a0, a0 - brev8 a0, a0 - rev8 a1, a1 - brev8 a1, a1 - mv a2, a0 - mv a0, a1 - mv a1, a2 - ret -#else - mov r2, r1 - rbit r1, r0 - rbit r0, r2 - bx lr -#endif - -// todo gcc riscv version is nuts; we'll provide both versions for simplicity in CMakeLists.txt -// (also gcc arm version is a bit pants) -bits_section ctzdi -wrapper_func __ctzdi2 -#ifdef __riscv - beqz a0, 1f - ctz a0, a0 - ret -1: - ctz a0, a1 - addi a0, a0, 32 - ret -#else - cbz r0, 1f - rbit r0, r0 - clz r0, r0 - bx lr -1: - rbit r0, r1 - clz r0, r0 - adds r0, #32 - bx lr -#endif - -#endif \ No newline at end of file diff --git a/lib/main/pico-sdk/rp2_common/pico_bootrom/bootrom.c b/lib/main/pico-sdk/rp2_common/pico_bootrom/bootrom.c deleted file mode 100644 index 84fbffd06e..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_bootrom/bootrom.c +++ /dev/null @@ -1,102 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "pico/bootrom.h" -#include "boot/picoboot.h" -#include "boot/picobin.h" - -/// \tag::table_lookup[] - -void *rom_func_lookup(uint32_t code) { - return rom_func_lookup_inline(code); -} - -#pragma GCC diagnostic push -// diagnostic: GCC thinks near-zero value is a null pointer member access, but it's not -#pragma GCC diagnostic ignored "-Warray-bounds" -void *rom_data_lookup(uint32_t code) { -#if PICO_RP2040 - rom_table_lookup_fn rom_table_lookup = (rom_table_lookup_fn) rom_hword_as_ptr(BOOTROM_TABLE_LOOKUP_OFFSET); - uint16_t *data_table = (uint16_t *) rom_hword_as_ptr(BOOTROM_DATA_TABLE_OFFSET); - return rom_table_lookup(data_table, code); -#else - rom_table_lookup_fn rom_table_lookup = (rom_table_lookup_fn) (uintptr_t)*(uint16_t*)(BOOTROM_TABLE_LOOKUP_OFFSET); - return rom_table_lookup(code, RT_FLAG_DATA); -#endif -} -#pragma GCC diagnostic pop -/// \end::table_lookup[] - -bool rom_funcs_lookup(uint32_t *table, unsigned int count) { - bool ok = true; - for (unsigned int i = 0; i < count; i++) { - table[i] = (uintptr_t) rom_func_lookup(table[i]); - if (!table[i]) ok = false; - } - return ok; -} - - -void __attribute__((noreturn)) rom_reset_usb_boot(uint32_t usb_activity_gpio_pin_mask, uint32_t disable_interface_mask) { -#ifdef ROM_FUNC_RESET_USB_BOOT - rom_reset_usb_boot_fn func = (rom_reset_usb_boot_fn) rom_func_lookup(ROM_FUNC_RESET_USB_BOOT); - func(usb_activity_gpio_pin_mask, disable_interface_mask); -#elif defined(ROM_FUNC_REBOOT) - uint32_t flags = disable_interface_mask; - if (usb_activity_gpio_pin_mask) { - flags |= BOOTSEL_FLAG_GPIO_PIN_SPECIFIED; - // the parameter is actually the gpio number, but we only care if BOOTSEL_FLAG_GPIO_PIN_SPECIFIED - usb_activity_gpio_pin_mask = (uint32_t)__builtin_ctz(usb_activity_gpio_pin_mask); - } - rom_reboot(REBOOT2_FLAG_REBOOT_TYPE_BOOTSEL | REBOOT2_FLAG_NO_RETURN_ON_SUCCESS, 10, flags, usb_activity_gpio_pin_mask); - __builtin_unreachable(); -#else - panic_unsupported(); -#endif -} - -#if !PICO_RP2040 -bool rom_get_boot_random(uint32_t out[4]) { - uint32_t result[5]; - rom_get_sys_info_fn func = (rom_get_sys_info_fn) rom_func_lookup_inline(ROM_FUNC_GET_SYS_INFO); - if (5 == func(result, count_of(result), SYS_INFO_BOOT_RANDOM)) { - for(uint i=0;i<4;i++) { - out[i] = result[i+1]; - } - return true; - } - return false; -} - -int rom_add_flash_runtime_partition(uint32_t start_offset, uint32_t size, uint32_t permissions) { - if ((start_offset) & 4095 || (size & 4095)) return PICO_ERROR_BAD_ALIGNMENT; - if (!size || start_offset + size > 32 * 1024 * 1024) return PICO_ERROR_INVALID_ARG; - if (permissions & ~PICOBIN_PARTITION_PERMISSIONS_BITS) return PICO_ERROR_INVALID_ARG; - - void **ptr = (void **)rom_data_lookup(ROM_DATA_PARTITION_TABLE_PTR); - assert(ptr); - assert(*ptr); - struct pt { - struct { - uint8_t partition_count; - uint8_t permission_partition_count; // >= partition_count and includes any regions added at runtime - bool loaded; - }; - uint32_t unpartitioned_space_permissions_and_flags; - resident_partition_t partitions[PARTITION_TABLE_MAX_PARTITIONS]; - } *pt = (struct pt *)*ptr; - assert(pt->loaded); // even if empty it should have been populated by the bootrom - if (pt->permission_partition_count < pt->partition_count) pt->permission_partition_count = pt->partition_count; - if (pt->permission_partition_count < PARTITION_TABLE_MAX_PARTITIONS) { - pt->partitions[pt->permission_partition_count].permissions_and_location = permissions | - ((start_offset / 4096) << PICOBIN_PARTITION_LOCATION_FIRST_SECTOR_LSB) | - ((start_offset + size - 4096) / 4096) << PICOBIN_PARTITION_LOCATION_LAST_SECTOR_LSB; - pt->partitions[pt->permission_partition_count].permissions_and_flags = permissions; - return pt->permission_partition_count++; - } - return PICO_ERROR_INSUFFICIENT_RESOURCES; -} -#endif \ No newline at end of file diff --git a/lib/main/pico-sdk/rp2_common/pico_bootrom/bootrom_lock.c b/lib/main/pico-sdk/rp2_common/pico_bootrom/bootrom_lock.c deleted file mode 100644 index 9f59d05045..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_bootrom/bootrom_lock.c +++ /dev/null @@ -1,21 +0,0 @@ -/* - * Copyright (c) 2024 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "pico/bootrom/lock.h" -#include "pico/runtime_init.h" - -#if PICO_BOOTROM_LOCKING_ENABLED -#if !PICO_RUNTIME_NO_INIT_BOOTROM_LOCKING_ENABLE -#include "hardware/sync.h" -void __weak runtime_init_bootrom_locking_enable(void) { - bootrom_acquire_lock_blocking(BOOTROM_LOCK_ENABLE); -} -#endif - -#if !PICO_RUNTIME_SKIP_INIT_BOOTROM_LOCKING_ENABLE -PICO_RUNTIME_INIT_FUNC_RUNTIME(runtime_init_bootrom_locking_enable, PICO_RUNTIME_INIT_BOOTROM_LOCKING_ENABLE); -#endif -#endif diff --git a/lib/main/pico-sdk/rp2_common/pico_bootrom/include/pico/bootrom.h b/lib/main/pico-sdk/rp2_common/pico_bootrom/include/pico/bootrom.h deleted file mode 100644 index 05bf1aa2f2..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_bootrom/include/pico/bootrom.h +++ /dev/null @@ -1,1081 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _PICO_BOOTROM_H -#define _PICO_BOOTROM_H - -#include "pico.h" -#include "pico/bootrom_constants.h" - -/** \file bootrom.h - * \defgroup pico_bootrom pico_bootrom - * \brief Access to functions and data in the bootrom - * - * This header may be included by assembly code - */ - -#ifndef __ASSEMBLER__ -#include -#include "pico/bootrom/lock.h" -#include "pico/flash.h" -// ROM FUNCTION SIGNATURES - -#if PICO_RP2040 -typedef uint32_t (*rom_popcount32_fn)(uint32_t); -typedef uint32_t (*rom_reverse32_fn)(uint32_t); -typedef uint32_t (*rom_clz32_fn)(uint32_t); -typedef uint32_t (*rom_ctz32_fn)(uint32_t); -typedef uint8_t *(*rom_memset_fn)(uint8_t *, uint8_t, uint32_t); -typedef uint32_t *(*rom_memset4_fn)(uint32_t *, uint8_t, uint32_t); -typedef uint32_t *(*rom_memcpy_fn)(uint8_t *, const uint8_t *, uint32_t); -typedef uint32_t *(*rom_memcpy44_fn)(uint32_t *, const uint32_t *, uint32_t); -#endif -typedef void __attribute__((noreturn)) (*rom_reset_usb_boot_fn)(uint32_t, uint32_t); -typedef int (*rom_reboot_fn)(uint32_t flags, uint32_t delay_ms, uint32_t p0, uint32_t p1); -typedef rom_reset_usb_boot_fn reset_usb_boot_fn; // kept for backwards compatibility -typedef void (*rom_connect_internal_flash_fn)(void); -typedef void (*rom_flash_exit_xip_fn)(void); -typedef void (*rom_flash_range_erase_fn)(uint32_t, size_t, uint32_t, uint8_t); -typedef void (*rom_flash_range_program_fn)(uint32_t, const uint8_t*, size_t); -typedef void (*rom_flash_flush_cache_fn)(void); -typedef void (*rom_flash_enter_cmd_xip_fn)(void); -#if !PICO_RP2040 -typedef void (*rom_bootrom_state_reset_fn)(uint32_t flags); -typedef void (*rom_flash_reset_address_trans_fn)(void); -typedef void (*rom_flash_select_xip_read_mode_fn)(bootrom_xip_mode_t mode, uint8_t clkdiv); -typedef int (*rom_get_sys_info_fn)(uint32_t *out_buffer, uint32_t out_buffer_word_size, uint32_t flags); -typedef int (*rom_get_partition_table_info_fn)(uint32_t *out_buffer, uint32_t out_buffer_word_size, uint32_t partition_and_flags); -typedef int (*rom_explicit_buy_fn)(uint8_t *buffer, uint32_t buffer_size); -typedef void* (*rom_validate_ns_buffer_fn)(const void *addr, uint32_t size, uint32_t write, uint32_t *ok); -/** - * @return BOOTROM_OK if successful - * BOOTROM_ERROR_INVALID_ARG if ns_api_num is out of range - */ -typedef intptr_t (*rom_set_rom_callback_fn)(uint callback_num, bootrom_api_callback_generic_t funcptr); -typedef int (*rom_chain_image_fn)(uint8_t *workarea_base, uint32_t workarea_size, uint32_t window_base, uint32_t window_size); -typedef int (*rom_load_partition_table_fn)(uint8_t *workarea_base, uint32_t workarea_size, bool force_reload); -typedef int (*rom_pick_ab_partition_fn)(uint8_t *workarea_base, uint32_t workarea_size, uint partition_a_num, uint32_t flash_update_boot_window_base); -typedef int (*rom_get_b_partition_fn)(uint pi_a); -typedef int (*rom_get_uf2_target_partition_fn)(uint8_t *workarea_base, uint32_t workarea_size, uint32_t family_id, resident_partition_t *partition_out); -typedef int (*rom_func_otp_access_fn)(uint8_t *buf, uint32_t buf_len, otp_cmd_t cmd); -// Apply the address translation currently specified in QMI_ATRANSx ("rolling window" hardware -// translation). Need to take care using this on the boot path, as the QMI may not yet have been -// set up, but this should be suitable for translating system bus addresses into flash storage -// addresses in user callbacks. Returns all-ones for an invalid address, which is also an invalid -// flash storage address, so invalidity is propagated. -typedef intptr_t (*rom_flash_runtime_to_storage_addr_fn)(uintptr_t flash_runtime_addr); - -// Perform the specified erase/program/read operation, translating addresses according to -// QMI_ATRANSx if necessary, and checking flash permissions based on the resident partition table -// and the specified effective security level. `addr` may be either a flash runtime address or a -// flash storage address, depending on the ASPACE given in `flags`. -// -// NOTE: This function does not validate the buffer for NS access. This must be validated before -// calling if the caller is reachable from a Secure Gateway. -typedef int (*rom_flash_op_fn)(cflash_flags_t flags, uintptr_t addr, uint32_t size_bytes, uint8_t *buf); - -#ifndef __riscv -typedef int (*rom_set_ns_api_permission_fn)(uint ns_api_num, bool allowed); -/** - * Note this is not strictly a C function; you must pass the function you are calling in r4 - * @param in_r4 - * `0b0xxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx` - a "well known" function selector; do not use for your own methods - * `0b10xx xxxx xxxx xxxx xxxx xxxx xxxx xxxx` - a "unique" function selector intended to be unlikely to clash with others'. - * The lower 30 bits should be chosen at random - * `0b11xx xxxx xxxx xxxx xxxx xxxx xxxx xxxx` - a "private" function selector intended for use by tightly coupled NS and S code - * - * @return whatever the secure call returns - * BOOTROM_ERROR_INVALID_STATE if no secure handler has been set from the secure side - * via rom_set_rom_callback_fn(BOOTROM_API_CALLBACK_secure_call, ...) - */ -typedef int (*rom_func_secure_call)(uintptr_t a0, ...); -#endif - -#ifdef __riscv -typedef struct { - uint32_t *base; - uint32_t size; -} bootrom_stack_t; -// passed in, and out. -typedef int (*rom_set_bootrom_stack_fn)(bootrom_stack_t *stack); -#endif -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -/*! \brief Return a bootrom lookup code based on two ASCII characters - * \ingroup pico_bootrom - * - * These codes are uses to lookup data or function addresses in the bootrom - * - * \param c1 the first character - * \param c2 the second character - * \return the 'code' to use in rom_func_lookup() or rom_data_lookup() - */ -static inline uint32_t rom_table_code(uint8_t c1, uint8_t c2) { - return ROM_TABLE_CODE((uint32_t) c1, (uint32_t) c2); -} - -/*! - * \brief Lookup a bootrom function by its code - * \ingroup pico_bootrom - * \param code the code - * \return a pointer to the function, or NULL if the code does not match any bootrom function - */ -void *rom_func_lookup(uint32_t code); - -/*! - * \brief Lookup a bootrom data address by its code - * \ingroup pico_bootrom - * \param code the code - * \return a pointer to the data, or NULL if the code does not match any bootrom function - */ -void *rom_data_lookup(uint32_t code); - -/*! - * \brief Helper function to lookup the addresses of multiple bootrom functions - * \ingroup pico_bootrom - * - * This method looks up the 'codes' in the table, and convert each table entry to the looked up - * function pointer, if there is a function for that code in the bootrom. - * - * \param table an IN/OUT array, elements are codes on input, function pointers on success. - * \param count the number of elements in the table - * \return true if all the codes were found, and converted to function pointers, false otherwise - */ -bool rom_funcs_lookup(uint32_t *table, unsigned int count); - -// Bootrom function: rom_table_lookup -// Returns the 32 bit pointer into the ROM if found or NULL otherwise. -#if PICO_RP2040 -typedef void *(*rom_table_lookup_fn)(uint16_t *table, uint32_t code); -#else -typedef void *(*rom_table_lookup_fn)(uint32_t code, uint32_t mask); -#endif - -#if PICO_C_COMPILER_IS_GNU && (__GNUC__ >= 12) -// Convert a 16 bit pointer stored at the given rom address into a 32 bit pointer -__force_inline static void *rom_hword_as_ptr(uint16_t rom_address) { -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Warray-bounds" - return (void *)(uintptr_t)*(uint16_t *)(uintptr_t)rom_address; -#pragma GCC diagnostic pop -} -#else -// Convert a 16 bit pointer stored at the given rom address into a 32 bit pointer -#define rom_hword_as_ptr(rom_address) (void *)(uintptr_t)(*(uint16_t *)(uintptr_t)(rom_address)) -#endif - -#ifdef __riscv -static __force_inline bool rom_size_is_64k(void) { -#ifdef RASPBERRYPI_AMETHYST_FPGA - // Detect ROM size by testing for bus fault at +32k - uint result; - pico_default_asm_volatile ( - "li %0, 0\n" - // Save and disable IRQs before touching trap vector - "csrr t2, mstatus\n" - "csrci mstatus, 0x8\n" - // Set up trap vector to skip the instruction which sets the %0 flag - "la t0, 1f\n" - "csrrw t0, mtvec, t0\n" - // This load will fault if the bootrom is no larger than 32k: - "li t1, 32 * 1024\n" - "lw t1, (t1)\n" - // No fault, so set return to true - "li %0, 1\n" - ".p2align 2\n" - // Always end up back here, restore the trap table - "1:\n" - "csrw mtvec, t0\n" - // Now safe to restore interrupts - "csrw mstatus, t2\n" - : "=r" (result) - : - : "t0", "t1", "t2" - ); - return result; -#else - return false; -#endif -} -#endif - -/*! - * \brief Lookup a bootrom function by code. This method is forcibly inlined into the caller for FLASH/RAM sensitive code usage - * \ingroup pico_bootrom - * \param code the code - * \return a pointer to the function, or NULL if the code does not match any bootrom function - */ -#pragma GCC diagnostic push -// diagnostic: GCC thinks near-zero value is a null pointer member access, but it's not -#pragma GCC diagnostic ignored "-Warray-bounds" -static __force_inline void *rom_func_lookup_inline(uint32_t code) { -#if PICO_RP2040 - rom_table_lookup_fn rom_table_lookup = (rom_table_lookup_fn) rom_hword_as_ptr(BOOTROM_TABLE_LOOKUP_OFFSET); - uint16_t *func_table = (uint16_t *) rom_hword_as_ptr(BOOTROM_FUNC_TABLE_OFFSET); - return rom_table_lookup(func_table, code); -#else -#ifdef __riscv - uint32_t rom_offset_adjust = rom_size_is_64k() ? 32 * 1024 : 0; - // on RISC-V the code (a jmp) is actually embedded in the table - rom_table_lookup_fn rom_table_lookup = (rom_table_lookup_fn) (uintptr_t)*(uint16_t*)(BOOTROM_TABLE_LOOKUP_ENTRY_OFFSET + rom_offset_adjust); - return rom_table_lookup(code, RT_FLAG_FUNC_RISCV); -#else - // on ARM the function pointer is stored in the table, so we dereference it - // via lookup() rather than lookup_entry() - rom_table_lookup_fn rom_table_lookup = (rom_table_lookup_fn) (uintptr_t)*(uint16_t*)(BOOTROM_TABLE_LOOKUP_OFFSET); - if (pico_processor_state_is_nonsecure()) { - return rom_table_lookup(code, RT_FLAG_FUNC_ARM_NONSEC); - } else { - return rom_table_lookup(code, RT_FLAG_FUNC_ARM_SEC); - } -#endif -#endif -} -#pragma GCC diagnostic pop - -/*! - * \brief Reboot the device into BOOTSEL mode - * \ingroup pico_bootrom - * - * This function reboots the device into the BOOTSEL mode ('usb boot"). - * - * Facilities are provided to enable an "activity light" via GPIO attached LED for the USB Mass Storage Device, - * and to limit the USB interfaces exposed. - * - * \param usb_activity_gpio_pin_mask 0 No pins are used as per a cold boot. Otherwise a single bit set indicating which - * GPIO pin should be set to output and raised whenever there is mass storage activity - * from the host. - * \param disable_interface_mask value to control exposed interfaces - * - 0 To enable both interfaces (as per a cold boot) - * - 1 To disable the USB Mass Storage Interface - * - 2 To disable the USB PICOBOOT Interface - */ -void __attribute__((noreturn)) rom_reset_usb_boot(uint32_t usb_activity_gpio_pin_mask, uint32_t disable_interface_mask); -static inline void __attribute__((noreturn)) reset_usb_boot(uint32_t usb_activity_gpio_pin_mask, uint32_t disable_interface_mask) { - rom_reset_usb_boot(usb_activity_gpio_pin_mask, disable_interface_mask); -} - -/*! - * \brief Connect the SSI/QMI to the QSPI pads - * \ingroup pico_bootrom - * - * Restore all QSPI pad controls to their default state, and connect the SSI/QMI peripheral to the QSPI pads. - * - * \if rp2350_specific - * On RP2350 if a secondary flash chip select GPIO has been configured via OTP OTP_DATA_FLASH_DEVINFO, or by writing to the runtime - * copy of FLASH_DEVINFO in bootram, then this bank 0 GPIO is also initialised and the QMI peripheral is connected. Otherwise, - * bank 0 IOs are untouched. - * \endif - */ -static inline void rom_connect_internal_flash(void) { - rom_connect_internal_flash_fn func = (rom_connect_internal_flash_fn) rom_func_lookup_inline(ROM_FUNC_CONNECT_INTERNAL_FLASH); - func(); -} - -/*! - * \brief Return the QSPI device from its XIP state to a serial command state - * \ingroup pico_bootrom - * - * \if rp2040_specific - * On RP2040, first set up the SSI for serial-mode operations, then issue the fixed XIP exit sequence described in Section 2.8.1.2 - * of the datasheet. Note that the bootrom code uses the IO forcing logic to drive the CS pin, which must be cleared before returning - * the SSI to XIP mode (e.g. by a call to _flash_flush_cache). This function configures the SSI with a fixed SCK clock divisor of /6. - * \endif - * - * \if rp2350_specific - * On RP2350, Initialise the QMI for serial operations (direct mode), and also initialise a basic XIP mode, where the QMI will perform - * 03h serial read commands at low speed (CLKDIV=12) in response to XIP reads. - * - * Then, issue a sequence to the QSPI device on chip select 0, designed to return it from continuous read mode ("XIP mode") and/or - * QPI mode to a state where it will accept serial commands. This is necessary after system reset to restore the QSPI device to a known - * state, because resetting RP2350 does not reset attached QSPI devices. It is also necessary when user code, having already performed - * some continuous-read-mode or QPI-mode accesses, wishes to return the QSPI device to a state where it will accept the serial erase and - * programming commands issued by the bootrom's flash access functions. - * - * If a GPIO for the secondary chip select is configured via FLASH_DEVINFO, then the XIP exit sequence is also issued to chip select 1. - * - * The QSPI device should be accessible for XIP reads after calling this function; the name flash_exit_xip refers to returning the QSPI - * device from its XIP state to a serial command state. - * \endif - */ -static inline void rom_flash_exit_xip(void) { - rom_flash_exit_xip_fn func = (rom_flash_exit_xip_fn) rom_func_lookup_inline(ROM_FUNC_FLASH_EXIT_XIP); - func(); -} - -/*! - * \brief Erase bytes in flash - * \ingroup pico_bootrom - * - * Erase count bytes, starting at addr (offset from start of flash). Optionally, pass a block erase command e.g. D8h block erase, - * and the size of the block erased by this command - this function will use the larger block erase where possible, for much higher - * erase speed. addr must be aligned to a 4096-byte sector, and count must be a multiple of 4096 bytes. - * - * This is a low-level flash API, and no validation of the arguments is performed. - * - * \if rp2350_specific - * See rom_flash_op on RP2350 for a higher-level API which checks alignment, flash bounds and partition permissions, and can transparently - * apply a runtime-to-storage address translation. - * - * The QSPI device must be in a serial command state before calling this API, which can be achieved by calling rom_connect_internal_flash() - * followed by rom_flash_exit_xip(). After the erase, the flash cache should be flushed via rom_flash_flush_cache() to ensure the modified - * flash data is visible to cached XIP accesses. - * - * Finally, the original XIP mode should be restored by copying the saved XIP setup function from bootram into SRAM, and executing it: - * the bootrom provides a default function which restores the flash mode/clkdiv discovered during flash scanning, and user programs can - * override this with their own XIP setup function. - * - * For the duration of the erase operation, QMI is in direct mode and attempting to access XIP from DMA, the debugger or the other core will - * return a bus fault. XIP becomes accessible again once the function returns. - * \endif - * - * \param addr the offset from start of flash to be erased - * \param count number of bytes to erase - * \param block_size optional size of block erased by block_cmd - * \param block_cmd optional block erase command e.g. D8h block erase - */ -static inline void rom_flash_range_erase(uint32_t addr, size_t count, uint32_t block_size, uint8_t block_cmd) { - rom_flash_range_erase_fn func = (rom_flash_range_erase_fn) rom_func_lookup_inline(ROM_FUNC_FLASH_RANGE_ERASE); - func(addr, count, block_size, block_cmd); -} - -/*! - * \brief Program bytes in flash - * \ingroup pico_bootrom - * - * Program data to a range of flash addresses starting at addr (offset from the start of flash) and count bytes in size. addr must be - * aligned to a 256-byte boundary, and count must be a multiple of 256. - * - * This is a low-level flash API, and no validation of the arguments is performed. - * - * \if rp2350_specific - * See rom_flash_op on RP2350 for a higher-level API which checks alignment, flash bounds and partition permissions, - * and can transparently apply a runtime-to-storage address translation. - * - * The QSPI device must be in a serial command state before calling this API - see notes on rom_flash_range_erase - * \endif - * - * \param addr the offset from start of flash to be erased - * \param data buffer containing the data to be written - * \param count number of bytes to erase - */ -static inline void rom_flash_range_program(uint32_t addr, const uint8_t *data, size_t count) { - rom_flash_range_program_fn func = (rom_flash_range_program_fn) rom_func_lookup_inline(ROM_FUNC_FLASH_RANGE_PROGRAM); - func(addr, data, count); -} - -/*! - * \brief Flush the XIP cache - * \ingroup pico_bootrom - * - * \if rp2040_specific - * Flush and enable the XIP cache. Also clears the IO forcing on QSPI CSn, so that the SSI can drive the flash chip select as normal. - * \endif - * - * \if rp2350_specific - * Flush the entire XIP cache, by issuing an invalidate by set/way maintenance operation to every cache line. This ensures that flash - * program/erase operations are visible to subsequent cached XIP reads. - * - * Note that this unpins pinned cache lines, which may interfere with cache-as-SRAM use of the XIP cache. - * - * No other operations are performed. - * \endif - */ -static inline void rom_flash_flush_cache(void) { - rom_flash_flush_cache_fn func = (rom_flash_flush_cache_fn) rom_func_lookup_inline(ROM_FUNC_FLASH_FLUSH_CACHE); - func(); -} - -/*! - * \brief Configure the SSI/QMI with a standard command - * \ingroup pico_bootrom - * - * Configure the SSI/QMI to generate a standard 03h serial read command, with 24 address bits, upon each XIP access. This is a slow XIP - * configuration, but is widely supported. CLKDIV is set to 12 on RP2350. The debugger may call this function to ensure that flash is - * readable following a program/erase operation. - * - * Note that the same setup is performed by flash_exit_xip(), and the RP2350 flash program/erase functions do not leave XIP in an - * inaccessible state, so calls to this function are largely redundant on RP2350. It is provided on RP2350 for compatibility with RP2040. - */ -static inline void rom_flash_enter_cmd_xip(void) { - rom_flash_enter_cmd_xip_fn func = (rom_flash_enter_cmd_xip_fn) rom_func_lookup_inline(ROM_FUNC_FLASH_ENTER_CMD_XIP); - func(); -} - -#if !PICO_RP2040 -#ifdef __riscv -/*! - * \brief Give the bootrom a new stack - * \ingroup pico_bootrom - * - * Most bootrom functions are written just once, in Arm code, to save space. As a result these functions are emulated when - * running under the RISC-V architecture. This is largely transparent to the user, however the stack used by the Arm emulation - * is separate from the calling user's stack, and is stored in boot RAM but is of quite limited size. When using certain of the more - * complex APIs or if nesting bootrom calls from within IRQs, you may need to provide a large stack. - * - * This method allows the caller to specify a region of RAM to use as the stack for the current core by passing a pointer to two values: the word aligned base address, - * and the size in bytes (multiple of 4). - * - * The method fills in the previous base/size values into the passed array before returning. - * - * \param stack bootrom_stack_t struct containing base and size - */ -static inline int rom_set_bootrom_stack(bootrom_stack_t *stack) { - rom_set_bootrom_stack_fn func = (rom_set_bootrom_stack_fn) rom_func_lookup_inline(ROM_FUNC_SET_BOOTROM_STACK); - return func(stack); -} -#endif - -/*! - * \brief Reboot using the watchdog - * \ingroup pico_bootrom - * - * Resets the chip and uses the watchdog facility to restart. - * - * The delay_ms is the millisecond delay before the reboot occurs. Note: by default this method is asynchronous - * (unless NO_RETURN_ON_SUCCESS is set - see below), so the method will return and the reboot will happen this many milliseconds later. - * - * The flags field contains one of the following values: - * - * REBOOT_TYPE_NORMAL - reboot into the normal boot path. - * - * REBOOT_TYPE_BOOTSEL - reboot into BOOTSEL mode. - * p0 - the GPIO number to use as an activity indicator (enabled by flag in p1). - * p1 - a set of flags: - * 0x01 : DISABLE_MSD_INTERFACE - Disable the BOOTSEL USB drive (see <>) - * 0x02 : DISABLE_PICOBOOT_INTERFACE - Disable the {picoboot} interface (see <>). - * 0x10 : GPIO_PIN_ACTIVE_LOW - The GPIO in p0 is active low. - * 0x20 : GPIO_PIN_ENABLED - Enable the activity indicator on the specified GPIO. - * - * REBOOT_TYPE_RAM_IMAGE - reboot into an image in RAM. The region of RAM or XIP RAM is searched for an image to run. This is the type - * of reboot used when a RAM UF2 is dragged onto the BOOTSEL USB drive. - * p0 - the region start address (word-aligned). - * p1 - the region size (word-aligned). - * - * REBOOT_TYPE_FLASH_UPDATE - variant of REBOOT_TYPE_NORMAL to use when flash has been updated. This is the type - * of reboot used after dragging a flash UF2 onto the BOOTSEL USB drive. - * p0 - the address of the start of the region of flash that was updated. If this address matches the start address of a partition or slot, then that - * partition or slot is treated preferentially during boot (when there is a choice). This type of boot facilitates TBYB and version downgrades. - * - * REBOOT_TYPE_PC_SP - reboot to a specific PC and SP. Note: this is not allowed in the ARM-NS variant. - * p0 - the initial program counter (PC) to start executing at. This must have the lowest bit set for Arm and clear for RISC-V - * p1 - the initial stack pointer (SP). - * - * All of the above, can have optional flags ORed in: - * - * REBOOT_TO_ARM - switch both cores to the Arm architecture (rather than leaving them as is). The call will fail with BOOTROM_ERROR_INVALID_STATE if the Arm architecture is not supported. - * REBOOT_TO_RISCV - switch both cores to the RISC-V architecture (rather than leaving them as is). The call will fail with BOOTROM_ERROR_INVALID_STATE if the RISC-V architecture is not supported. - * NO_RETURN_ON_SUCCESS - the watchdog h/w is asynchronous. Setting this bit forces this method not to return if the reboot is successfully initiated. - * - * \param flags the reboot flags, as detailed above - * \param delay_ms millisecond delay before the reboot occurs - * \param p0 parameter 0, depends on flags - * \param p1 parameter 1, depends on flags - */ -static inline int rom_reboot(uint32_t flags, uint32_t delay_ms, uint32_t p0, uint32_t p1) { - rom_reboot_fn func = (rom_reboot_fn) rom_func_lookup_inline(ROM_FUNC_REBOOT); - return func(flags, delay_ms, p0, p1); -} - -bool rom_get_boot_random(uint32_t out[4]); - -/*! - * \brief Reset bootrom state - * \ingroup pico_bootrom - * - * Resets internal bootrom state, based on the following flags: - * - * STATE_RESET_CURRENT_CORE - Resets any internal bootrom state for the current core into a clean state. - * This method should be called prior to calling any other bootrom APIs on the current core, - * and is called automatically by the bootrom during normal boot of core 0 and launch of code on core 1. - * - * STATE_RESET_OTHER_CORE - Resets any internal bootrom state for the other core into a clean state. This is generally called by - * a debugger when resetting the state of one core via code running on the other. - * - * STATE_RESET_GLOBAL_STATE - Resets all non core-specific state, including: - * Disables access to bootrom APIs from ARM-NS - * Unlocks all BOOT spinlocks - * Clears any secure code callbacks - * - * Note: the sdk calls this method on runtime initialisation to put the bootrom into a known state. This - * allows the program to function correctly if it is entered (e.g. from a debugger) without taking the usual boot path (which - * resets the state appropriately itself). - * - * \param flags flags, as detailed above - */ -static inline void rom_bootrom_state_reset(uint32_t flags) { - rom_bootrom_state_reset_fn func = (rom_bootrom_state_reset_fn) rom_func_lookup_inline(ROM_FUNC_BOOTROM_STATE_RESET); - return func(flags); -} - -/*! - * \brief Reset address translation - * \ingroup pico_bootrom - * - * Restore the QMI address translation registers, QMI_ATRANS0 through QMI_ATRANS7, to their reset state. This makes the - * runtime-to-storage address map an identity map, i.e. the mapped and unmapped address are equal, and the entire space is - * fully mapped. - */ -static inline void rom_flash_reset_address_trans(void) { - rom_flash_reset_address_trans_fn func = (rom_flash_reset_address_trans_fn) rom_func_lookup_inline(ROM_FUNC_FLASH_RESET_ADDRESS_TRANS); - func(); -} - -/*! - * \brief Configure QMI in a XIP read mode - * \ingroup pico_bootrom - * - * Configure QMI for one of a small menu of XIP read modes supported by the bootrom. This mode is configured for both memory - * windows (both chip selects), and the clock divisor is also applied to direct mode. - * - * \param mode bootrom_xip_mode_t mode to use - * \param clkdiv clock divider - */ -static inline void rom_flash_select_xip_read_mode(bootrom_xip_mode_t mode, uint8_t clkdiv) { - rom_flash_select_xip_read_mode_fn func = (rom_flash_select_xip_read_mode_fn) rom_func_lookup_inline(ROM_FUNC_FLASH_SELECT_XIP_READ_MODE); - func(mode, clkdiv); -} - -typedef struct { - cflash_flags_t flags; - uintptr_t addr; - uint32_t size_bytes; - uint8_t *buf; - int *res; -} rom_helper_flash_op_params_t; - -static inline void rom_helper_flash_op(void *param) { - const rom_helper_flash_op_params_t *op = (const rom_helper_flash_op_params_t *)param; - rom_flash_op_fn func = (rom_flash_op_fn) rom_func_lookup_inline(ROM_FUNC_FLASH_OP); - *(op->res) = func(op->flags, op->addr, op->size_bytes, op->buf); -} - -/*! - * \brief Perform a flash read, erase, or program operation - * \ingroup pico_bootrom - * - * The flash operation is bounds-checked against the known flash devices specified by the runtime value of FLASH_DEVINFO, - * stored in bootram. This is initialised by the bootrom to the OTP value OTP_DATA_FLASH_DEVINFO, if - * OTP_DATA_BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is set; otherwise it is initialised to 16 MiB for chip select 0 and 0 bytes - * for chip select 1. FLASH_DEVINFO can be updated at runtime by writing to its location in bootram, the pointer to which - * can be looked up in the ROM table. - * - * If a resident partition table is in effect, then the flash operation is also checked against the partition permissions. - * The Secure version of this function can specify the caller's effective security level (Secure, Non-secure, bootloader) - * using the CFLASH_SECLEVEL_BITS bitfield of the flags argument, whereas the Non-secure function is always checked against - * the Non-secure permissions for the partition. Flash operations which span two partitions are not allowed, and will fail - * address validation. - * - * If OTP_DATA_FLASH_DEVINFO_D8H_ERASE_SUPPORTED is set, erase operations will use a D8h 64 kiB block erase command where - * possible (without erasing outside the specified region), for faster erase time. Otherwise, only 20h 4 kiB sector erase - * commands are used. - * - * Optionally, this API can translate addr from flash runtime addresses to flash storage addresses, according to the - * translation currently configured by QMI address translation registers, QMI_ATRANS0 through QMI_ATRANS7. For example, an - * image stored at a +2 MiB offset in flash (but mapped at XIP address 0 at runtime), writing to an offset of +1 MiB into - * the image, will write to a physical flash storage address of 3 MiB. Translation is enabled by setting the - * CFLASH_ASPACE_BITS bitfield in the flags argument. - * - * When translation is enabled, flash operations which cross address holes in the XIP runtime address space (created by - * non-maximum ATRANSx_SIZE) will return an error response. This check may tear: the transfer may be partially performed - * before encountering an address hole and ultimately returning failure. - * - * When translation is enabled, flash operations are permitted to cross chip select boundaries, provided this does not - * span an ATRANS address hole. When translation is disabled, the entire operation must target a single flash chip select - * (as determined by bits 24 and upward of the address), else address validation will fail. - * - * \param flags controls the security level, address space, and flash operation - * \param addr the address of the first flash byte to be accessed, ranging from XIP_BASE to XIP_BASE + 0x1ffffff - * \param size_bytes size of buf, in bytes - * \param buf contains data to be written to flash, for program operations, and data read back from flash, for read operations - */ -static inline int rom_flash_op(cflash_flags_t flags, uintptr_t addr, uint32_t size_bytes, uint8_t *buf) { - if (!bootrom_try_acquire_lock(BOOTROM_LOCK_FLASH_OP)) - return BOOTROM_ERROR_LOCK_REQUIRED; - int rc = 0; - rom_helper_flash_op_params_t params = { - .flags = flags, - .addr = addr, - .size_bytes = size_bytes, - .buf = buf, - .res = &rc - }; - int flash_rc = flash_safe_execute(rom_helper_flash_op, ¶ms, UINT32_MAX); - bootrom_release_lock(BOOTROM_LOCK_FLASH_OP); - if (flash_rc != PICO_OK) { - return flash_rc; - } else { - return rc; - } -} - -/*! - * \brief Writes data from a buffer into OTP, or reads data from OTP into a buffer - * \ingroup pico_bootrom - * - * The buffer must be aligned to 2 bytes or 4 bytes according to the IS_ECC flag. - * - * This method will read and write rows until the first row it encounters that fails a key or permission check at which - * it will return BOOTROM_ERROR_NOT_PERMITTED. - * - * Writing will also stop at the first row where an attempt is made to set an OTP bit from a 1 to a 0, and - * BOOTROM_ERROR_UNSUPPORTED_MODIFICATION will be returned. - * - * If all rows are read/written successfully, then BOOTROM_OK will be returned. - * - * \param buf buffer to read to/write from - * \param buf_len size of buf - * \param cmd OTP command to execute - * - 0x0000ffff - ROW_NUMBER: 16 low bits are row number (0-4095) - * - 0x00010000 - IS_WRITE: if set, do a write (not a read) - * - 0x00020000 - IS_ECC: if this bit is set, each value in the buffer is 2 bytes and ECC is used when read/writing from 24 - * bit value in OTP. If this bit is not set, each value in the buffer is 4 bytes, the low 24-bits of which are written - * to or read from OTP. - - */ -static inline int rom_func_otp_access(uint8_t *buf, uint32_t buf_len, otp_cmd_t cmd) { - rom_func_otp_access_fn func = (rom_func_otp_access_fn) rom_func_lookup_inline(ROM_FUNC_OTP_ACCESS); - if (!bootrom_try_acquire_lock(BOOTROM_LOCK_OTP)) - return BOOTROM_ERROR_LOCK_REQUIRED; - int rc = func(buf, buf_len, cmd); - bootrom_release_lock(BOOTROM_LOCK_OTP); - return rc; -} - -/*! - * \brief Fills a buffer with information from the partition table - * \ingroup pico_bootrom - * - * Fills a buffer with information from the partition table. Note that this API is also used to return information over the - * picoboot interface. - * - * On success, the buffer is filled, and the number of words filled in the buffer is returned. If the partition table - * has not been loaded (e.g. from a watchdog or RAM boot), then this method will return BOOTROM_ERROR_NO_DATA, and you - * should load the partition table via load_partition_table() first. - * - * Note that not all data from the partition table is kept resident in memory by the bootrom due to size constraints. - * To protect against changes being made in flash after the bootrom has loaded the resident portion, the bootrom keeps - * a hash of the partition table as of the time it loaded it. If the hash has changed by the time this method is called, - * then it will return BOOTROM_ERROR_INVALID_STATE. - * - * The information returned is chosen by the flags_and_partition parameter; the first word in the returned buffer, - * is the (sub)set of those flags that the API supports. You should always check this value before interpreting - * the buffer. - * - * Following the first word, returns words of data for each present flag in order. With the exception of PT_INFO, - * all the flags select "per partition" information, so each field is returned in flag order for one partition after - * the next. The special SINGLE_PARTITION flag indicates that data for only a single partition is required. - * - * \param out_buffer buffer to write data to - * \param out_buffer_word_size size of out_buffer, in words - * \param partition_and_flags partition number and flags - */ -static inline int rom_get_partition_table_info(uint32_t *out_buffer, uint32_t out_buffer_word_size, uint32_t partition_and_flags) { - rom_get_partition_table_info_fn func = (rom_get_partition_table_info_fn) rom_func_lookup_inline(ROM_FUNC_GET_PARTITION_TABLE_INFO); - if (!bootrom_try_acquire_lock(BOOTROM_LOCK_SHA_256)) - return BOOTROM_ERROR_LOCK_REQUIRED; - int rc = func(out_buffer, out_buffer_word_size, partition_and_flags); - bootrom_release_lock(BOOTROM_LOCK_SHA_256); - return rc; -} - -// todo SECURE only -/*! - * \brief Loads the current partition table from flash, if present - * \ingroup pico_bootrom - * - * This method potentially requires similar complexity to the boot path in terms of picking amongst versions, checking signatures etc. - * As a result it requires a user provided memory buffer as a work area. The work area should byte word-aligned and of sufficient size - * or BOOTROM_ERROR_INSUFFICIENT_RESOURCES will be returned. The work area size currently required is 3064, so 3K is a good choice. - * - * If force_reload is false, then this method will return BOOTROM_OK immediately if the bootrom is loaded, otherwise it will - * reload the partition table if it has been loaded already, allowing for the partition table to be updated in a running program. - * - * \param workarea_base base address of work area - * \param workarea_size size of work area - * \param force_reload force reloading of the partition table - */ -static inline int rom_load_partition_table(uint8_t *workarea_base, uint32_t workarea_size, bool force_reload) { - rom_load_partition_table_fn func = (rom_load_partition_table_fn) rom_func_lookup_inline(ROM_FUNC_LOAD_PARTITION_TABLE); - if (!bootrom_try_acquire_lock(BOOTROM_LOCK_SHA_256)) - return BOOTROM_ERROR_LOCK_REQUIRED; - int rc = func(workarea_base, workarea_size, force_reload); - bootrom_release_lock(BOOTROM_LOCK_SHA_256); - return rc; -} - -// todo SECURE only -/*! - * \brief Pick a partition from an A/B pair - * \ingroup pico_bootrom - * - * Determines which of the partitions has the "better" IMAGE_DEF. In the case of executable images, this is the one that would be booted - * - * This method potentially requires similar complexity to the boot path in terms of picking amongst versions, checking signatures etc. - * As a result it requires a user provided memory buffer as a work area. The work area should bye word aligned, and of sufficient size - * or BOOTROM_ERROR_INSUFFICIENT_RESOURCES will be returned. The work area size currently required is 3064, so 3K is a good choice. - * - * The passed partition number can be any valid partition number other than the "B" partition of an A/B pair. - * - * This method returns a negative error code, or the partition number of the picked partition if (i.e. partition_a_num or the - * number of its "B" partition if any). - * - * NOTE: This method does not look at owner partitions, only the A partition passed and it's corresponding B partition. - * - * \param workarea_base base address of work area - * \param workarea_size size of work area - * \param partition_a_num the A partition of the pair - * \param flash_update_boot_window_base the flash update base, to pick that partition instead of the normally "better" partition - */ -static inline int rom_pick_ab_partition(uint8_t *workarea_base, uint32_t workarea_size, uint partition_a_num, uint32_t flash_update_boot_window_base) { - rom_pick_ab_partition_fn func = (rom_pick_ab_partition_fn) rom_func_lookup_inline(ROM_FUNC_PICK_AB_PARTITION); - if (!bootrom_try_acquire_lock(BOOTROM_LOCK_SHA_256)) - return BOOTROM_ERROR_LOCK_REQUIRED; - int rc = func(workarea_base, workarea_size, partition_a_num, flash_update_boot_window_base); - bootrom_release_lock(BOOTROM_LOCK_SHA_256); - return rc; -} - -/*! - * \brief Get B partition - * \ingroup pico_bootrom - * - * Returns the index of the B partition of partition A if a partition table is present and loaded, and there is a partition A with a B partition; - * otherwise returns BOOTROM_ERROR_NOT_FOUND. - * - * \param pi_a the A partition number - */ -static inline int rom_get_b_partition(uint pi_a) { - rom_get_b_partition_fn func = (rom_get_b_partition_fn) rom_func_lookup_inline(ROM_FUNC_GET_B_PARTITION); - return func(pi_a); -} - -// todo SECURE only -/*! - * \brief Get UF2 Target Partition - * \ingroup pico_bootrom - * - * This method performs the same operation to decide on a target partition for a UF2 family ID as when a UF2 is dragged onto the USB - * drive in BOOTSEL mode. - * - * This method potentially requires similar complexity to the boot path in terms of picking amongst versions, checking signatures etc. - * As a result it requires a user provided memory buffer as a work area. The work area should byte word-aligned and of sufficient size - * or `BOOTROM_ERROR_INSUFFICIENT_RESOURCES` will be returned. The work area size currently required is 3064, so 3K is a good choice. - * - * If the partition table - * has not been loaded (e.g. from a watchdog or RAM boot), then this method will return `BOOTROM_ERROR_PRECONDITION_NOT_MET`, and you - * should load the partition table via <> first. - * - * \param workarea_base base address of work area - * \param workarea_size size of work area - * \param family_id the family ID to place - * \param partition_out pointer to the resident_partition_t to fill with the partition data - */ -static inline int rom_get_uf2_target_partition(uint8_t *workarea_base, uint32_t workarea_size, uint32_t family_id, resident_partition_t *partition_out) { - rom_get_uf2_target_partition_fn func = (rom_get_uf2_target_partition_fn) rom_func_lookup_inline(ROM_FUNC_GET_UF2_TARGET_PARTITION); - if (!bootrom_try_acquire_lock(BOOTROM_LOCK_SHA_256)) - return BOOTROM_ERROR_LOCK_REQUIRED; - int rc = func(workarea_base, workarea_size, family_id, partition_out); - bootrom_release_lock(BOOTROM_LOCK_SHA_256); - return rc; -} - -/*! - * \brief Translate runtime to storage address - * \ingroup pico_bootrom - * - * Applies the address translation currently configured by QMI address translation registers. - * - * Translating an address outside of the XIP runtime address window, or beyond the bounds of an ATRANSx_SIZE field, returns BOOTROM_ERROR_INVALID_ADDRESS, - * which is not a valid flash storage address. Otherwise, return the storage address which QMI would access when presented with the runtime address addr. - * This is effectively a virtual-to-physical address translation for QMI. - * - * \param flash_runtime_addr the address to translate - */ -static inline intptr_t rom_flash_runtime_to_storage_addr(uintptr_t flash_runtime_addr) { - rom_flash_runtime_to_storage_addr_fn func = (rom_flash_runtime_to_storage_addr_fn) rom_func_lookup_inline(ROM_FUNC_FLASH_RUNTIME_TO_STORAGE_ADDR); - return func(flash_runtime_addr); -} - -// todo SECURE only -/*! - * \brief Chain into a launchable image - * \ingroup pico_bootrom - * - * Searches a memory region for a launchable image, and executes it if possible. - * - * The region_base and region_size specify a word-aligned, word-multiple-sized area of RAM, XIP RAM or flash to search. - * The first 4 kiB of the region must contain the start of a Block Loop with an IMAGE_DEF. If the new image is launched, - * the call does not return otherwise an error is returned. - * - * The region_base is signed, as a negative value can be passed, which indicates that the (negated back to positive value) - * is both the region_base and the base of the "flash update" region. - * - * This method potentially requires similar complexity to the boot path in terms of picking amongst versions, checking signatures etc. - * As a result it requires a user provided memory buffer as a work area. The work area should be word aligned, and of sufficient size - * or BOOTROM_ERROR_INSUFFICIENT_RESOURCES will be returned. The work area size currently required is 3064, so 3K is a good choice. - * - * NOTE: This method is primarily expected to be used when implementing bootloaders. - * - * NOTE: When chaining into an image, the OTP_DATA_BOOT_FLAGS0_ROLLBACK_REQUIRED flag will not be set, to prevent invalidating a bootloader - * without a rollback version by booting a binary which has one. - * - * \param workarea_base base address of work area - * \param workarea_size size of work area - * \param region_base base address of image - * \param region_size size of window containing image - */ -static inline int rom_chain_image(uint8_t *workarea_base, uint32_t workarea_size, uint32_t region_base, uint32_t region_size) { - rom_chain_image_fn func = (rom_chain_image_fn) rom_func_lookup_inline(ROM_FUNC_CHAIN_IMAGE); - bootrom_release_lock(BOOTROM_LOCK_ENABLE); - uint32_t interrupt_flags = save_and_disable_interrupts(); - int rc = func(workarea_base, workarea_size, region_base, region_size); - restore_interrupts_from_disabled(interrupt_flags); - bootrom_acquire_lock_blocking(BOOTROM_LOCK_ENABLE); - return rc; -} - -typedef struct { - uint8_t *buffer; - uint32_t buffer_size; - int *res; -} rom_helper_explicit_buy_params_t; - -static inline void rom_helper_explicit_buy(void *param) { - const rom_helper_explicit_buy_params_t *op = (const rom_helper_explicit_buy_params_t *)param; - rom_explicit_buy_fn func = (rom_explicit_buy_fn) rom_func_lookup_inline(ROM_FUNC_EXPLICIT_BUY); - *(op->res) = func(op->buffer, op->buffer_size); -} - -// todo SECURE only -/*! - * \brief Buy an image - * \ingroup pico_bootrom - * - * Perform an "explicit" buy of an executable launched via an IMAGE_DEF which was "explicit buy" flagged. A "flash update" - * boot of such an image is a way to have the image execute once, but only become the "current" image if it calls - * back into the bootrom via this call. - * - * This call may perform the following: - * - * - Erase and rewrite the part of flash containing the "explicit buy" flag in order to clear said flag. - * - Erase the first sector of the other partition in an A/B partition scenario, if this new IMAGE_DEF is a version downgrade - * (so this image will boot again when not doing a "flash update" boot) - * - Update the rollback version in OTP if the chip is secure, and a rollback version is present in the image. - * - * NOTE: The device may reboot while updating the rollback version, if multiple rollback rows need to be written - this occurs - * when the version crosses a multiple of 24 (for example upgrading from version 23 to 25 requires a reboot, but 23 to 24 or 24 to 25 doesn't). - * The application should therefore be prepared to reboot when calling this function, if rollback versions are in use. - * - * Note that the first of the above requires 4 kiB of scratch space, so you should pass a word aligned buffer of at least 4 kiB to this method, - * or it will return BOOTROM_ERROR_INSUFFICIENT_RESOURCES if the "explicit buy" flag needs to be cleared. - * - * \param buffer base address of scratch space - * \param buffer_size size of scratch space - */ -static inline int rom_explicit_buy(uint8_t *buffer, uint32_t buffer_size) { - int rc = 0; - rom_helper_explicit_buy_params_t params = { - .buffer = buffer, - .buffer_size = buffer_size, - .res = &rc - }; - int flash_rc = flash_safe_execute(rom_helper_explicit_buy, ¶ms, UINT32_MAX); - if (flash_rc != PICO_OK) { - return flash_rc; - } else { - return rc; - } -} - -#ifndef __riscv -/*! - * \brief Set NS API Permission - * \ingroup pico_bootrom - * - * Allow or disallow the specific NS API (note all NS APIs default to disabled). - * - * ns_api_num configures ARM-NS access to the given API. When an NS API is disabled, - * calling it will return BOOTROM_ERROR_NOT_PERMITTED. - * - * NOTE: All permissions default to disallowed after a reset. - * - * \param ns_api_num ns api number - * \param allowed permission - */ -static inline int rom_set_ns_api_permission(uint ns_api_num, bool allowed) { - rom_set_ns_api_permission_fn func = (rom_set_ns_api_permission_fn) rom_func_lookup_inline(ROM_FUNC_SET_NS_API_PERMISSION); - return func(ns_api_num, allowed); -} -#endif - -// todo SECURE only -/*! - * \brief Validate NS Buffer - * \ingroup pico_bootrom - * - * Utility method that can be used by secure ARM code to validate a buffer passed to it from Non-secure code. - * - * Both the write parameter and the (out) result parameter ok are RCP booleans, so 0xa500a500 for true, and 0x00c300c3 - * for false. This enables hardening of this function, and indeed the write parameter must be one of these values or the RCP - * will hang the system. - * - * For success, the entire buffer must fit in range XIP_BASE -> SRAM_END, and must be accessible by the Non-secure - * caller according to SAU + NS MPU (privileged or not based on current processor IPSR and NS CONTROL flag). Buffers - * in USB RAM are also allowed if access is granted to NS via ACCESSCTRL. - * - * \param addr buffer address - * \param size buffer size - * \param write rcp boolean, true if writeable - * \param ok rcp boolean result - */ -static inline void* rom_validate_ns_buffer(const void *addr, uint32_t size, uint32_t write, uint32_t *ok) { - rom_validate_ns_buffer_fn func = (rom_validate_ns_buffer_fn) rom_func_lookup_inline(ROM_FUNC_VALIDATE_NS_BUFFER); - return func(addr, size, write, ok); -} - -/*! - * \brief Set ROM callback function - * \ingroup pico_bootrom - * - * The only currently supported callback_number is 0 which sets the callback used for the secure_call API. - * - * A callback pointer of 0 deletes the callback function, a positive callback pointer (all valid function pointers are on RP2350) - * sets the callback function, but a negative callback pointer can be passed to get the old value without setting a new value. - * - * If successful, returns >=0 (the existing value of the function pointer on entry to the function). - * - * \param callback_num the callback number to set - only 0 is supported on RP2350 - * \param funcptr pointer to the callback function - */ -static inline intptr_t rom_set_rom_callback(uint callback_num, bootrom_api_callback_generic_t funcptr) { - rom_set_rom_callback_fn func = (rom_set_rom_callback_fn) rom_func_lookup_inline(ROM_FUNC_SET_ROM_CALLBACK); - return func(callback_num, funcptr); -} - -#define BOOT_TYPE_NORMAL 0 -#define BOOT_TYPE_BOOTSEL 2 -#define BOOT_TYPE_RAM_IMAGE 3 -#define BOOT_TYPE_FLASH_UPDATE 4 - -// values 8-15 are secure only -#define BOOT_TYPE_PC_SP 0xd - -// ORed in if a bootloader chained into the image -#define BOOT_TYPE_CHAINED_FLAG 0x80 - -/*! - * \brief Get system information - * \ingroup pico_bootrom - * - * Fills a buffer with various system information. Note that this API is also used to return information over the picoboot interface. - * - * On success, the buffer is filled, and the number of words filled in the buffer is returned. - * - * The information returned is chosen by the flags parameter; the first word in the returned buffer, - * is the (sub)set of those flags that the API supports. You should always check this value before interpreting - * the buffer. - * - * "Boot Diagnostic" information is intended to help identify the cause of a failed boot, or booting into an unexpected binary. - * This information can be retrieved via picoboot after a watchdog reboot, however it will not survive - * a reset via the RUN pin or POWMAN reset. - * - * There is only one word of diagnostic information. What it records is based on the pp selection above, which - * is itself set as a parameter when rebooting programmatically into a normal boot. - * - * To get diagnostic info, pp must refer to a slot or an "A" partition; image diagnostics are automatically selected on boot - * from OTP or RAM image, or when chain_image() is called.) - * - * The diagnostic word thus contains data for either slot 0 and slot 1, or the "A" partition (and its "B" partition if it has one). The low half word - * of the diagnostic word contains information from slot 0 or partition A; the high half word contains information from slot 1 or partition B. - * - * To get a full picture of a failed boot involving slots and multiple partitions, the device can be rebooted - * multiple times to gather the information. - * - * \param out_buffer buffer to write data to - * \param out_buffer_word_size size of out_buffer, in words - * \param flags flags - */ -static inline int rom_get_sys_info(uint32_t *out_buffer, uint32_t out_buffer_word_size, uint32_t flags) { - rom_get_sys_info_fn func = (rom_get_sys_info_fn)rom_func_lookup_inline(ROM_FUNC_GET_SYS_INFO); - return func(out_buffer, out_buffer_word_size, flags); -} - -typedef struct { - union { - struct __packed { - int8_t diagnostic_partition_index; // used BOOT_PARTITION constants - uint8_t boot_type; - int8_t partition; - uint8_t tbyb_and_update_info; - }; - uint32_t boot_word; - }; - uint32_t boot_diagnostic; - uint32_t reboot_params[2]; -} boot_info_t; - -static inline int rom_get_boot_info(boot_info_t *info) { - uint32_t result[5]; - int words_returned = rom_get_sys_info(result, 5, SYS_INFO_BOOT_INFO); - if (words_returned == (sizeof(result)/sizeof(result[0])) && result[0] == SYS_INFO_BOOT_INFO) { - memcpy(info, &result[1], sizeof(boot_info_t)); - return true; - } else { - return false; - } -} - -static inline int rom_get_last_boot_type_with_chained_flag(void) { - uint32_t result[5]; - int words_returned = rom_get_sys_info(result, 5, SYS_INFO_BOOT_INFO); - if (words_returned == count_of(result) && result[0] == SYS_INFO_BOOT_INFO) { - // todo use struct - return (int)((result[1] & 0xff00u) >> 8); - } else { - return PICO_ERROR_INVALID_DATA; - } -} - -// BOOT_TYPE_NORMAL 0x0 -// BOOT_TYPE_BOOTSEL 0x2 -// BOOT_TYPE_RAM_IMAGE 0x3 -// BOOT_TYPE_FLASH_UPDATE 0x4 -// BOOT_TYPE_PC_SP 0xd -static inline int rom_get_last_boot_type(void) { - int rc = rom_get_last_boot_type_with_chained_flag(); - if (rc >= 0) rc &= ~BOOT_TYPE_CHAINED_FLAG; - return rc; -} - -/*! \brief Add a runtime partition to the partition table to specify flash permissions - * \ingroup pico_bootrom - * - * Note that a partition is added to the runtime view of the partition table maintained by the bootrom if there is space to do so - * - * Note that these permissions cannot override the permissions for any pre-existing partitions, as permission matches are made on a first partition found basis. - * - * @param start_offset the start_offset into flash in bytes (must be a multiple of 4K) - * @param size the size in byte (must be a multiple of 4K) - * @param permissions the bitwise OR of permissions from PICOBIN_PARTITION_PERMISSION_ constants, e.g. \ref PICOBIN_PARTITION_PERMISSION_S_R_BITS from boot/picobin.h - * @return >= 0 the partition number added if - * PICO_ERROR_BAD_ALIGNMENT if the start_offset or size aren't multiples of 4K. - * PICO_ERROR_INVALID_ARG if the start_offset or size are out of range, or invalid permission bits are set. - */ -int rom_add_flash_runtime_partition(uint32_t start_offset, uint32_t size, uint32_t permissions); - -#endif - -#ifdef __cplusplus -} -#endif - -#endif // !__ASSEMBLER__ -#endif diff --git a/lib/main/pico-sdk/rp2_common/pico_bootrom/include/pico/bootrom/lock.h b/lib/main/pico-sdk/rp2_common/pico_bootrom/include/pico/bootrom/lock.h deleted file mode 100644 index ff36eed373..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_bootrom/include/pico/bootrom/lock.h +++ /dev/null @@ -1,69 +0,0 @@ -/* - * Copyright (c) 2024 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _PICO_BOOTROM_LOCK_H -#define _PICO_BOOTROM_LOCK_H - -#include "hardware/boot_lock.h" -#include "pico/bootrom_constants.h" - -// PICO_CONFIG: PICO_BOOTROM_LOCKING_ENABLED, Enable/disable locking for bootrom functions that use shared resources. If this flag is enabled bootrom lock checking is turned on and BOOT locks are taken around the relevant bootrom functions, type=bool, default=1, group=pico_bootrom -#ifndef PICO_BOOTROM_LOCKING_ENABLED -#if NUM_BOOT_LOCKS > 0 -#define PICO_BOOTROM_LOCKING_ENABLED 1 -#endif -#endif - -/** - * \brief Try to acquire a bootrom lock - * - * If PICO_BOOTROM_LOCKING_ENABLED is false, this method returns true immediately - * - * \param lock_num the lock numbers - BOOTROM_LOCK_SHA_256, BOOTROM_LOCK_FLASH_OP or BOOTROM_LOCK_OTP - * \return true if the lock was acquired - */ -static inline bool bootrom_try_acquire_lock(uint lock_num) { -#if PICO_BOOTROM_LOCKING_ENABLED - // unsafe as this is a long term lock (so no irq disable) - return boot_try_lock_unsafe(boot_lock_instance(lock_num)); -#else - (void)lock_num; - return true; -#endif -} - -/** - * \brief Acquire a bootrom lock. If the lock is unavailable, block until it is available - * - * If PICO_BOOTROM_LOCKING_ENABLED is false, this method does nothing - * - * \param lock_num the lock numbers - BOOTROM_LOCK_SHA_256, BOOTROM_LOCK_FLASH_OP or BOOTROM_LOCK_OTP - */ -static inline void bootrom_acquire_lock_blocking(uint lock_num) { -#if PICO_BOOTROM_LOCKING_ENABLED - // unsafe as this is a long term lock (so no irq disable) - boot_lock_unsafe_blocking(boot_lock_instance(lock_num)); -#else - (void)lock_num; -#endif -} - -/** - * \brief Release a bootrom lock - * - * If PICO_BOOTROM_LOCKING_ENABLED is false, this method does nothing - * - * \param lock_num the lock numbers - BOOTROM_LOCK_SHA_256, BOOTROM_LOCK_FLASH_OP or BOOTROM_LOCK_OTP - */ -static inline void bootrom_release_lock(uint lock_num) { -#if PICO_BOOTROM_LOCKING_ENABLED - boot_unlock_unsafe(boot_lock_instance(lock_num)); -#else - (void)lock_num; -#endif -} - -#endif diff --git a/lib/main/pico-sdk/rp2_common/pico_bootrom/include/pico/bootrom/sf_table.h b/lib/main/pico-sdk/rp2_common/pico_bootrom/include/pico/bootrom/sf_table.h deleted file mode 100644 index 2bb5435071..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_bootrom/include/pico/bootrom/sf_table.h +++ /dev/null @@ -1,50 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _PICO_BOOTROM_SF_TABLE_H -#define _PICO_BOOTROM_SF_TABLE_H - -// NOTE THESE FUNCTION IMPLEMENTATIONS MATCH THE BEHAVIOR DESCRIBED IN THE BOOTROM SECTION OF THE RP2040 DATASHEET - -#define SF_TABLE_FADD 0x00 -#define SF_TABLE_FSUB 0x04 -#define SF_TABLE_FMUL 0x08 -#define SF_TABLE_FDIV 0x0c -#define SF_TABLE_FCMP_FAST 0x10 -#define SF_TABLE_FCMP_FAST_FLAGS 0x14 -#define SF_TABLE_FSQRT 0x18 -#define SF_TABLE_FLOAT2INT 0x1c -#define SF_TABLE_FLOAT2FIX 0x20 -#define SF_TABLE_FLOAT2UINT 0x24 -#define SF_TABLE_FLOAT2UFIX 0x28 -#define SF_TABLE_INT2FLOAT 0x2c -#define SF_TABLE_FIX2FLOAT 0x30 -#define SF_TABLE_UINT2FLOAT 0x34 -#define SF_TABLE_UFIX2FLOAT 0x38 -#define SF_TABLE_FCOS 0x3c -#define SF_TABLE_FSIN 0x40 -#define SF_TABLE_FTAN 0x44 -#define SF_TABLE_V3_FSINCOS 0x48 -#define SF_TABLE_FEXP 0x4c -#define SF_TABLE_FLN 0x50 - -#define SF_TABLE_V1_SIZE 0x54 - -#define SF_TABLE_FCMP_BASIC 0x54 -#define SF_TABLE_FATAN2 0x58 -#define SF_TABLE_INT642FLOAT 0x5c -#define SF_TABLE_FIX642FLOAT 0x60 -#define SF_TABLE_UINT642FLOAT 0x64 -#define SF_TABLE_UFIX642FLOAT 0x68 -#define SF_TABLE_FLOAT2INT64 0x6c -#define SF_TABLE_FLOAT2FIX64 0x70 -#define SF_TABLE_FLOAT2UINT64 0x74 -#define SF_TABLE_FLOAT2UFIX64 0x78 -#define SF_TABLE_FLOAT2DOUBLE 0x7c - -#define SF_TABLE_V2_SIZE 0x80 - -#endif diff --git a/lib/main/pico-sdk/rp2_common/pico_bootrom/include/pico/bootrom_constants.h b/lib/main/pico-sdk/rp2_common/pico_bootrom/include/pico/bootrom_constants.h deleted file mode 100644 index b3bfd47ea4..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_bootrom/include/pico/bootrom_constants.h +++ /dev/null @@ -1,8 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -// new location; this file kept for backwards compatibility -#include "boot/bootrom_constants.h" diff --git a/lib/main/pico-sdk/rp2_common/pico_bootsel_via_double_reset/pico_bootsel_via_double_reset.c b/lib/main/pico-sdk/rp2_common/pico_bootsel_via_double_reset/pico_bootsel_via_double_reset.c deleted file mode 100644 index ae86c5bed2..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_bootsel_via_double_reset/pico_bootsel_via_double_reset.c +++ /dev/null @@ -1,89 +0,0 @@ -/* - * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "pico.h" - -// Doesn't make any sense for a RAM only binary -#if !PICO_NO_FLASH - -#include "pico/time.h" -#include "pico/bootrom.h" -#include "pico/binary_info.h" - -// PICO_CONFIG: PICO_BOOTSEL_VIA_DOUBLE_RESET_TIMEOUT_MS, Window of opportunity for a second press of a reset button to enter BOOTSEL mode (milliseconds), type=int, default=200, group=pico_bootsel_via_double_reset -#ifndef PICO_BOOTSEL_VIA_DOUBLE_RESET_TIMEOUT_MS -#define PICO_BOOTSEL_VIA_DOUBLE_RESET_TIMEOUT_MS 200 -#endif - -// PICO_CONFIG: PICO_BOOTSEL_VIA_DOUBLE_RESET_ACTIVITY_LED, Optionally define a pin to use as bootloader activity LED when BOOTSEL mode is entered via reset double tap, type=int, min=0, max=29, group=pico_bootsel_via_double_reset - -// PICO_CONFIG: PICO_BOOTSEL_VIA_DOUBLE_RESET_INTERFACE_DISABLE_MASK, Optionally disable either the mass storage interface (bit 0) or the PICOBOOT interface (bit 1) when entering BOOTSEL mode via double reset, type=int, min=0, max=3, default=0, group=pico_bootsel_via_double_reset -#ifndef PICO_BOOTSEL_VIA_DOUBLE_RESET_INTERFACE_DISABLE_MASK -#define PICO_BOOTSEL_VIA_DOUBLE_RESET_INTERFACE_DISABLE_MASK 0u -#endif - -/** \defgroup pico_bootsel_via_double_reset pico_bootsel_via_double_reset - * - * \brief Optional support to make fast double reset of the system enter BOOTSEL mode - * - * \brief When the 'pico_bootsel_via_double_reset' library is linked, a function is - * injected before main() which will detect when the system has been reset - * twice in quick succession, and enter the USB ROM bootloader (BOOTSEL mode) - * when this happens. This allows a double tap of a reset button on a - * development board to be used to enter the ROM bootloader, provided this - * library is always linked. - */ - -#if !PICO_NO_BI_BOOTSEL_VIA_DOUBLE_RESET -bi_decl(bi_program_feature("double reset -> BOOTSEL")); -#endif - -static const uint32_t magic_token[] = { - 0xf01681de, 0xbd729b29, 0xd359be7a, -}; - -static uint32_t __uninitialized_ram(magic_location)[count_of(magic_token)]; - -/* Check for double reset and enter BOOTSEL mode if detected - * - * This function is registered to run automatically before main(). The - * algorithm is: - * - * 1. Check for magic token in memory; enter BOOTSEL mode if found. - * 2. Initialise that memory with that magic token. - * 3. Do nothing for a short while (few hundred ms). - * 4. Clear the magic token. - * 5. Continue with normal boot. - * - * Resetting the device twice quickly will interrupt step 3, leaving the token - * in place so that the second boot will go to the bootloader. - */ -static void __attribute__((constructor)) boot_double_tap_check(void) { - for (uint i = 0; i < count_of(magic_token); i++) { - if (magic_location[i] != magic_token[i]) { - // Arm, wait, then disarm and continue booting - for (i = 0; i < count_of(magic_token); i++) { - magic_location[i] = magic_token[i]; - } - busy_wait_us(PICO_BOOTSEL_VIA_DOUBLE_RESET_TIMEOUT_MS * 1000); - magic_location[0] = 0; - return; - } - } - // Detected a double reset, so enter USB bootloader - magic_location[0] = 0; -#ifdef PICO_BOOTSEL_VIA_DOUBLE_RESET_ACTIVITY_LED - const uint32_t led_mask = 1u << PICO_BOOTSEL_VIA_DOUBLE_RESET_ACTIVITY_LED; -#else - const uint32_t led_mask = 0u; -#endif - reset_usb_boot( - led_mask, - PICO_BOOTSEL_VIA_DOUBLE_RESET_INTERFACE_DISABLE_MASK - ); -} - -#endif diff --git a/lib/main/pico-sdk/rp2_common/pico_btstack/LICENSE.RP b/lib/main/pico-sdk/rp2_common/pico_btstack/LICENSE.RP deleted file mode 100644 index 79e0080db0..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_btstack/LICENSE.RP +++ /dev/null @@ -1,30 +0,0 @@ -“BlueKitchen” shall refer to BlueKitchen GmbH. -“Raspberry Pi” shall refer to Raspberry Pi Ltd. -“Product” shall refer to Raspberry Pi hardware products Raspberry Pi Pico W or Raspberry Pi Pico WH. -“Customer” means any purchaser of a Product. -“Customer Products” means products manufactured or distributed by Customers which use or are derived from Products. - -Raspberry Pi grants to the Customer a non-exclusive, non-transferable, non-sublicensable, irrevocable, perpetual -and worldwide licence to use, copy, store, develop, modify, and transmit BTstack in order to use BTstack with or -integrate BTstack into Products or Customer Products, and distribute BTstack as part of these Products or -Customer Products or their related documentation or SDKs. - -All use of BTstack by the Customer is limited to Products or Customer Products, and the Customer represents and -warrants that all such use shall be in compliance with the terms of this licence and all applicable laws and -regulations, including but not limited to, copyright and other intellectual property laws and privacy regulations. - -BlueKitchen retains all rights, title and interest in, to and associated with BTstack and associated websites. -Customer shall not take any action inconsistent with BlueKitchen’s ownership of BTstack, any associated services, -websites and related content. - -There are no implied licences under the terms set forth in this licence, and any rights not expressly granted -hereunder are reserved by BlueKitchen. - -BTSTACK IS PROVIDED BY RASPBERRY PI "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED TO THE FULLEST EXTENT -PERMISSIBLE UNDER APPLICABLE LAW. IN NO EVENT SHALL RASPBERRY PI OR BLUEKITCHEN BE LIABLE FOR ANY DIRECT, INDIRECT, -INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE -GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY -OUT OF THE USE OF BTSTACK, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - diff --git a/lib/main/pico-sdk/rp2_common/pico_btstack/btstack.BUILD b/lib/main/pico-sdk/rp2_common/pico_btstack/btstack.BUILD deleted file mode 100644 index ac009d9e93..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_btstack/btstack.BUILD +++ /dev/null @@ -1,197 +0,0 @@ -load("@pico-sdk//bazel:defs.bzl", "incompatible_with_config") - -package(default_visibility = ["//visibility:public"]) - -_DISABLE_WARNINGS = [ - "-Wno-cast-qual", - "-Wno-format", - "-Wno-maybe-uninitialized", - "-Wno-null-dereference", - "-Wno-sign-compare", - "-Wno-stringop-overflow", - "-Wno-suggest-attribute=format", - "-Wno-type-limits", - "-Wno-unused-parameter", -] - -cc_library( - name = "pico_btstack_base", - srcs = [ - "3rd-party/md5/md5.c", - "3rd-party/micro-ecc/uECC.c", - "3rd-party/rijndael/rijndael.c", - "3rd-party/segger-rtt/SEGGER_RTT.c", - "3rd-party/segger-rtt/SEGGER_RTT_printf.c", - "3rd-party/yxml/yxml.c", - "platform/embedded/btstack_tlv_flash_bank.c", - "platform/embedded/hci_dump_embedded_stdout.c", - "platform/embedded/hci_dump_segger_rtt_stdout.c", - "src/ad_parser.c", - "src/btstack_audio.c", - "src/btstack_base64_decoder.c", - "src/btstack_crypto.c", - "src/btstack_hid_parser.c", - "src/btstack_linked_list.c", - "src/btstack_memory.c", - "src/btstack_memory_pool.c", - "src/btstack_resample.c", - "src/btstack_ring_buffer.c", - "src/btstack_run_loop.c", - "src/btstack_run_loop_base.c", - "src/btstack_slip.c", - "src/btstack_tlv.c", - "src/btstack_tlv_none.c", - "src/btstack_util.c", - "src/hci.c", - "src/hci_cmd.c", - "src/hci_dump.c", - "src/hci_event.c", - "src/l2cap.c", - "src/l2cap_signaling.c", - "src/mesh/gatt-service/mesh_provisioning_service_server.c", - "src/mesh/gatt-service/mesh_proxy_service_server.c", - ], - hdrs = glob(["**/*.h"]), - copts = _DISABLE_WARNINGS, - includes = [ - ".", - "3rd-party/md5", - "3rd-party/micro-ecc", - "3rd-party/rijndael", - "3rd-party/segger-rtt", - "3rd-party/yxml", - "platform/embedded", - "src", - ], - target_compatible_with = incompatible_with_config( - "@pico-sdk//bazel/constraint:pico_btstack_config_unset", - ), - deps = ["@pico-sdk//bazel/config:PICO_BTSTACK_CONFIG"], -) - -cc_library( - name = "pico_btstack_ble", - srcs = [ - "src/ble/att_db.c", - "src/ble/att_db_util.c", - "src/ble/att_dispatch.c", - "src/ble/att_server.c", - "src/ble/gatt-service/ancs_client.c", - "src/ble/gatt-service/battery_service_client.c", - "src/ble/gatt-service/battery_service_server.c", - "src/ble/gatt-service/cycling_power_service_server.c", - "src/ble/gatt-service/cycling_speed_and_cadence_service_server.c", - "src/ble/gatt-service/device_information_service_client.c", - "src/ble/gatt-service/device_information_service_server.c", - "src/ble/gatt-service/heart_rate_service_server.c", - "src/ble/gatt-service/hids_client.c", - "src/ble/gatt-service/hids_device.c", - "src/ble/gatt-service/nordic_spp_service_server.c", - "src/ble/gatt-service/ublox_spp_service_server.c", - "src/ble/gatt_client.c", - "src/ble/le_device_db_memory.c", - "src/ble/le_device_db_tlv.c", - "src/ble/sm.c", - ], - copts = _DISABLE_WARNINGS, - deps = [":pico_btstack_base"], -) - -cc_library( - name = "pico_btstack_classic", - srcs = [ - "src/classic/a2dp.c", - "src/classic/a2dp_sink.c", - "src/classic/a2dp_source.c", - "src/classic/avdtp.c", - "src/classic/avdtp_acceptor.c", - "src/classic/avdtp_initiator.c", - "src/classic/avdtp_sink.c", - "src/classic/avdtp_source.c", - "src/classic/avdtp_util.c", - "src/classic/avrcp.c", - "src/classic/avrcp_browsing.c", - "src/classic/avrcp_browsing_controller.c", - "src/classic/avrcp_browsing_target.c", - "src/classic/avrcp_controller.c", - "src/classic/avrcp_cover_art_client.c", - "src/classic/avrcp_media_item_iterator.c", - "src/classic/avrcp_target.c", - "src/classic/btstack_cvsd_plc.c", - "src/classic/btstack_link_key_db_tlv.c", - "src/classic/btstack_sbc_plc.c", - "src/classic/device_id_server.c", - "src/classic/gatt_sdp.c", - "src/classic/goep_client.c", - "src/classic/goep_server.c", - "src/classic/hfp.c", - "src/classic/hfp_ag.c", - "src/classic/hfp_gsm_model.c", - "src/classic/hfp_hf.c", - "src/classic/hfp_msbc.c", - "src/classic/hid_device.c", - "src/classic/hid_host.c", - "src/classic/hsp_ag.c", - "src/classic/hsp_hs.c", - "src/classic/obex_iterator.c", - "src/classic/obex_message_builder.c", - "src/classic/obex_parser.c", - "src/classic/pan.c", - "src/classic/pbap_client.c", - "src/classic/rfcomm.c", - "src/classic/sdp_client.c", - "src/classic/sdp_client_rfcomm.c", - "src/classic/sdp_server.c", - "src/classic/sdp_util.c", - "src/classic/spp_server.c", - ], - copts = _DISABLE_WARNINGS, - deps = [":pico_btstack_base"], -) - -cc_library( - name = "pico_btstack_sbc_encoder", - srcs = [ - "3rd-party/bluedroid/encoder/srce/sbc_analysis.c", - "3rd-party/bluedroid/encoder/srce/sbc_dct.c", - "3rd-party/bluedroid/encoder/srce/sbc_dct_coeffs.c", - "3rd-party/bluedroid/encoder/srce/sbc_enc_bit_alloc_mono.c", - "3rd-party/bluedroid/encoder/srce/sbc_enc_bit_alloc_ste.c", - "3rd-party/bluedroid/encoder/srce/sbc_enc_coeffs.c", - "3rd-party/bluedroid/encoder/srce/sbc_encoder.c", - "3rd-party/bluedroid/encoder/srce/sbc_packing.c", - "src/classic/btstack_sbc_encoder_bluedroid.c", - ], - copts = _DISABLE_WARNINGS, - includes = ["3rd-party/bluedroid/decoder/include"], - deps = [":pico_btstack_base"], -) - -cc_library( - name = "pico_btstack_bnep_lwip", - srcs = [ - "platform/lwip/bnep_lwip.c", - "src/classic/bnep.c", - ], - copts = _DISABLE_WARNINGS, - includes = ["platform/lwip"], - deps = [":pico_btstack_base"], -) - -cc_library( - name = "pico_btstack_bnep_lwip_sys_freertos", - srcs = [ - "platform/lwip/bnep_lwip.c", - "src/classic/bnep.c", - ], - copts = _DISABLE_WARNINGS, - defines = [ - "LWIP_PROVIDE_ERRNO=1", - "PICO_LWIP_CUSTOM_LOCK_TCPIP_CORE=1", - ], - includes = [ - "platform/freertos", - "platform/lwip", - ], - deps = [":pico_btstack_base"], -) diff --git a/lib/main/pico-sdk/rp2_common/pico_btstack/btstack_flash_bank.c b/lib/main/pico-sdk/rp2_common/pico_btstack/btstack_flash_bank.c deleted file mode 100644 index 54111ff747..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_btstack/btstack_flash_bank.c +++ /dev/null @@ -1,178 +0,0 @@ -/* - * Copyright (c) 2023 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "pico/btstack_flash_bank.h" -#include "pico/flash.h" -#include "hardware/sync.h" -#include "hardware/flash.h" -#include - -// Check sizes -static_assert(PICO_FLASH_BANK_TOTAL_SIZE % (FLASH_SECTOR_SIZE * 2) == 0, "PICO_FLASH_BANK_TOTAL_SIZE invalid"); -static_assert(PICO_FLASH_BANK_TOTAL_SIZE <= PICO_FLASH_SIZE_BYTES, "PICO_FLASH_BANK_TOTAL_SIZE too big"); - -// Size of one bank -#define PICO_FLASH_BANK_SIZE (PICO_FLASH_BANK_TOTAL_SIZE / 2) - -#if 0 -#define DEBUG_PRINT(format,args...) printf(format, ## args) -#else -#define DEBUG_PRINT(...) -#endif - -static uint32_t pico_flash_bank_get_size(void * context) { - (void)(context); - return PICO_FLASH_BANK_SIZE; -} - -static uint32_t pico_flash_bank_get_alignment(void * context) { - (void)(context); - return 1; -} - -typedef struct { - bool op_is_erase; - uintptr_t p0; - uintptr_t p1; -} mutation_operation_t; - -static void pico_flash_bank_perform_flash_mutation_operation(void *param) { - const mutation_operation_t *mop = (const mutation_operation_t *)param; - if (mop->op_is_erase) { - flash_range_erase(mop->p0, PICO_FLASH_BANK_SIZE); - } else { - flash_range_program(mop->p0, (const uint8_t *)mop->p1, FLASH_PAGE_SIZE); - } -} - -#ifndef pico_flash_bank_get_storage_offset_func -static inline uint32_t pico_flash_bank_get_fixed_storage_offset(void) { - static_assert(PICO_FLASH_BANK_STORAGE_OFFSET + PICO_FLASH_BANK_TOTAL_SIZE <= PICO_FLASH_SIZE_BYTES, "PICO_FLASH_BANK_TOTAL_SIZE too big"); -#ifndef NDEBUG - // Check we're not overlapping the binary in flash - extern char __flash_binary_end; - assert(((uintptr_t)&__flash_binary_end - XIP_BASE <= PICO_FLASH_BANK_STORAGE_OFFSET)); -#endif - return PICO_FLASH_BANK_STORAGE_OFFSET; -} -#define pico_flash_bank_get_storage_offset_func pico_flash_bank_get_fixed_storage_offset -#else -extern uint32_t pico_flash_bank_get_storage_offset_func(void); -#endif - -static void pico_flash_bank_erase(void * context, int bank) { - (void)(context); - DEBUG_PRINT("erase: bank %d\n", bank); - mutation_operation_t mop = { - .op_is_erase = true, - .p0 = pico_flash_bank_get_storage_offset_func() + (PICO_FLASH_BANK_SIZE * bank), - }; - // todo choice of timeout and check return code... currently we have no way to return an error - // to the caller anyway. flash_safe_execute asserts by default on problem other than timeout, - // so that's fine for now, and UINT32_MAX is a timeout of 49 days which seems long enough - flash_safe_execute(pico_flash_bank_perform_flash_mutation_operation, &mop, UINT32_MAX); -} - -static void pico_flash_bank_read(void *context, int bank, uint32_t offset, uint8_t *buffer, uint32_t size) { - (void)(context); - DEBUG_PRINT("read: bank %d offset %u size %u\n", bank, offset, size); - - assert(bank <= 1); - if (bank > 1) return; - - assert(offset < PICO_FLASH_BANK_SIZE); - if (offset >= PICO_FLASH_BANK_SIZE) return; - - assert((offset + size) <= PICO_FLASH_BANK_SIZE); - if ((offset + size) > PICO_FLASH_BANK_SIZE) return; - - // Flash is xip - memcpy(buffer, (void *)(XIP_BASE + pico_flash_bank_get_storage_offset_func() + (PICO_FLASH_BANK_SIZE * bank) + offset), size); -} - -static void pico_flash_bank_write(void * context, int bank, uint32_t offset, const uint8_t *data, uint32_t size) { - (void)(context); - DEBUG_PRINT("write: bank %d offset %u size %u\n", bank, offset, size); - - assert(bank <= 1); - if (bank > 1) return; - - assert(offset < PICO_FLASH_BANK_SIZE); - if (offset >= PICO_FLASH_BANK_SIZE) return; - - assert((offset + size) <= PICO_FLASH_BANK_SIZE); - if ((offset + size) > PICO_FLASH_BANK_SIZE) return; - - if (size == 0) return; - - // calc bank start position - const uint32_t bank_start_pos = pico_flash_bank_get_storage_offset_func() + (PICO_FLASH_BANK_SIZE * bank); - - // Calculate first and last page in the bank - const uint32_t first_page = offset / FLASH_PAGE_SIZE; - const uint32_t last_page = (offset + size + FLASH_PAGE_SIZE - 1) / FLASH_PAGE_SIZE; - - // Now we only care about the offset in the first page - offset %= FLASH_PAGE_SIZE; - - // Amount of data we've copied - uint32_t data_pos = 0; - uint32_t size_left = size; - - // Write all the pages required - for(uint32_t page = first_page; page < last_page; page++) { - uint8_t page_data[FLASH_PAGE_SIZE]; - - assert(data_pos < size && size_left <= size); - - // Copy data we're not going to overwrite in the first page - if (page == first_page && offset > 0) { - memcpy(page_data, - (void *)(XIP_BASE + bank_start_pos + (page * FLASH_PAGE_SIZE)), - offset); - } - - // Copy the data we're not going to overwrite in the last page - if (page == last_page - 1 && (offset + size_left) < FLASH_PAGE_SIZE) { - memcpy(page_data + offset + size_left, - (void *)(XIP_BASE + bank_start_pos + (page * FLASH_PAGE_SIZE) + offset + size_left), - FLASH_PAGE_SIZE - offset - size_left); - } - - // Now copy the new data into the page - const uint32_t size_to_copy = MIN(size_left, FLASH_PAGE_SIZE - offset); - memcpy(page_data + offset, data + data_pos, size_to_copy); - - data_pos += size_to_copy; - size_left -= size_to_copy; - - // zero offset for the following pages - offset = 0; - - // Now program the entire page - mutation_operation_t mop = { - .op_is_erase = false, - .p0 = bank_start_pos + (page * FLASH_PAGE_SIZE), - .p1 = (uintptr_t)page_data - }; - // todo choice of timeout and check return code... currently we have no way to return an error - // to the caller anyway. flash_safe_execute asserts by default on problem other than timeout, - // so that's fine for now, and UINT32_MAX is a timeout of 49 days which seems long enough - flash_safe_execute(pico_flash_bank_perform_flash_mutation_operation, &mop, UINT32_MAX); - } -} - -static const hal_flash_bank_t pico_flash_bank_instance_obj = { - /* uint32_t (*get_size)(..) */ &pico_flash_bank_get_size, - /* uint32_t (*get_alignment)(..); */ &pico_flash_bank_get_alignment, - /* void (*erase)(..); */ &pico_flash_bank_erase, - /* void (*read)(..); */ &pico_flash_bank_read, - /* void (*write)(..); */ &pico_flash_bank_write, -}; - -const hal_flash_bank_t *pico_flash_bank_instance(void) { - return &pico_flash_bank_instance_obj; -} diff --git a/lib/main/pico-sdk/rp2_common/pico_btstack/btstack_run_loop_async_context.c b/lib/main/pico-sdk/rp2_common/pico_btstack/btstack_run_loop_async_context.c deleted file mode 100644 index 9847be90de..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_btstack/btstack_run_loop_async_context.c +++ /dev/null @@ -1,155 +0,0 @@ -/* - * Copyright (c) 2023 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "pico/btstack_run_loop_async_context.h" -#include "hardware/sync.h" - -static async_context_t *btstack_async_context; -static async_at_time_worker_t btstack_timeout_worker; -static async_when_pending_worker_t btstack_processing_worker; -static void btstack_timeout_reached(async_context_t *context, async_at_time_worker_t *worker); -static void btstack_work_pending(async_context_t *context, async_when_pending_worker_t *worker); -static volatile bool run_loop_exit; - -static void btstack_run_loop_async_context_init(void) { - btstack_run_loop_base_init(); - btstack_timeout_worker.do_work = btstack_timeout_reached; - btstack_processing_worker.do_work = btstack_work_pending; - async_context_add_when_pending_worker(btstack_async_context, &btstack_processing_worker); -} - -static void btstack_run_loop_async_context_add_data_source(btstack_data_source_t * data_source) { - async_context_acquire_lock_blocking(btstack_async_context); - btstack_run_loop_base_add_data_source(data_source); - async_context_release_lock(btstack_async_context); -} - -static bool btstack_run_loop_async_context_remove_data_source(btstack_data_source_t * data_source) { - async_context_acquire_lock_blocking(btstack_async_context); - bool rc = btstack_run_loop_base_remove_data_source(data_source); - async_context_release_lock(btstack_async_context); - return rc; -} - -static void btstack_run_loop_async_context_enable_data_source_callbacks(btstack_data_source_t * data_source, uint16_t callbacks) { - async_context_acquire_lock_blocking(btstack_async_context); - btstack_run_loop_base_enable_data_source_callbacks(data_source, callbacks); - async_context_release_lock(btstack_async_context); -} - -static void btstack_run_loop_async_context_disable_data_source_callbacks(btstack_data_source_t * data_source, uint16_t callbacks) { - async_context_acquire_lock_blocking(btstack_async_context); - btstack_run_loop_base_disable_data_source_callbacks(data_source, callbacks); - async_context_release_lock(btstack_async_context); -} - -static void btstack_run_loop_async_context_set_timer(btstack_timer_source_t *ts, uint32_t timeout_in_ms){ - async_context_acquire_lock_blocking(btstack_async_context); - ts->timeout = to_ms_since_boot(get_absolute_time()) + timeout_in_ms + 1; - async_context_set_work_pending(btstack_async_context, &btstack_processing_worker); - async_context_release_lock(btstack_async_context); -} - -static void btstack_run_loop_async_context_add_timer(btstack_timer_source_t *timer) { - async_context_acquire_lock_blocking(btstack_async_context); - btstack_run_loop_base_add_timer(timer); - async_context_set_work_pending(btstack_async_context, &btstack_processing_worker); - async_context_release_lock(btstack_async_context); -} - -static bool btstack_run_loop_async_context_remove_timer(btstack_timer_source_t *timer) { - async_context_acquire_lock_blocking(btstack_async_context); - bool rc = btstack_run_loop_base_remove_timer(timer); - async_context_release_lock(btstack_async_context); - return rc; -} - -static void btstack_run_loop_async_context_dump_timer(void){ - async_context_acquire_lock_blocking(btstack_async_context); - btstack_run_loop_base_dump_timer(); - async_context_release_lock(btstack_async_context); -} - -static uint32_t btstack_run_loop_async_context_get_time_ms(void) -{ - return to_ms_since_boot(get_absolute_time()); -} - -static void btstack_run_loop_async_context_execute(void) -{ - run_loop_exit = false; - while (!run_loop_exit) { - async_context_poll(btstack_async_context); - async_context_wait_for_work_until(btstack_async_context, at_the_end_of_time); - } -} - -static void btstack_run_loop_async_context_trigger_exit(void) -{ - run_loop_exit = true; -} - -static void btstack_run_loop_async_context_execute_on_main_thread(btstack_context_callback_registration_t *callback_registration) -{ - async_context_acquire_lock_blocking(btstack_async_context); - btstack_run_loop_base_add_callback(callback_registration); - async_context_set_work_pending(btstack_async_context, &btstack_processing_worker); - async_context_release_lock(btstack_async_context); -} - -static void btstack_run_loop_async_context_poll_data_sources_from_irq(void) -{ - async_context_set_work_pending(btstack_async_context, &btstack_processing_worker); -} - -static const btstack_run_loop_t btstack_run_loop_async_context = { - &btstack_run_loop_async_context_init, - &btstack_run_loop_async_context_add_data_source, - &btstack_run_loop_async_context_remove_data_source, - &btstack_run_loop_async_context_enable_data_source_callbacks, - &btstack_run_loop_async_context_disable_data_source_callbacks, - &btstack_run_loop_async_context_set_timer, - &btstack_run_loop_async_context_add_timer, - &btstack_run_loop_async_context_remove_timer, - &btstack_run_loop_async_context_execute, - &btstack_run_loop_async_context_dump_timer, - &btstack_run_loop_async_context_get_time_ms, - &btstack_run_loop_async_context_poll_data_sources_from_irq, - &btstack_run_loop_async_context_execute_on_main_thread, - &btstack_run_loop_async_context_trigger_exit, -}; - -const btstack_run_loop_t *btstack_run_loop_async_context_get_instance(async_context_t *async_context) -{ - assert(!btstack_async_context || btstack_async_context == async_context); - btstack_async_context = async_context; - return &btstack_run_loop_async_context; -} - -static void btstack_timeout_reached(__unused async_context_t *context, __unused async_at_time_worker_t *worker) { - // simply wakeup worker - async_context_set_work_pending(btstack_async_context, &btstack_processing_worker); -} - -static void btstack_work_pending(__unused async_context_t *context, __unused async_when_pending_worker_t *worker) { - // poll data sources - btstack_run_loop_base_poll_data_sources(); - - // execute callbacks - btstack_run_loop_base_execute_callbacks(); - - uint32_t now = to_ms_since_boot(get_absolute_time()); - - // process timers - btstack_run_loop_base_process_timers(now); - now = to_ms_since_boot(get_absolute_time()); - int ms = btstack_run_loop_base_get_time_until_timeout(now); - if (ms == -1) { - async_context_remove_at_time_worker(btstack_async_context, &btstack_timeout_worker); - } else { - async_context_add_at_time_worker_in_ms(btstack_async_context, &btstack_timeout_worker, ms); - } -} diff --git a/lib/main/pico-sdk/rp2_common/pico_btstack/btstack_stdin_pico.c b/lib/main/pico-sdk/rp2_common/pico_btstack/btstack_stdin_pico.c deleted file mode 100644 index 1afa4cc883..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_btstack/btstack_stdin_pico.c +++ /dev/null @@ -1,60 +0,0 @@ -/* - * Copyright (c) 2023 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "btstack_config.h" - -#ifdef HAVE_BTSTACK_STDIN - -#include "btstack_stdin.h" -#include "btstack_run_loop.h" -#include "pico/stdio.h" - -static btstack_data_source_t stdin_data_source; -static void (*stdin_handler)(char c); - -// Data source callback, return any character received -static void btstack_stdin_process(__unused struct btstack_data_source *ds, __unused btstack_data_source_callback_type_t callback_type){ - if (stdin_handler) { - while(true) { - int c = getchar_timeout_us(0); - if (c == PICO_ERROR_TIMEOUT) return; - (*stdin_handler)(c); - } - } -} - -void on_chars_available_callback(__unused void *param) { - btstack_run_loop_poll_data_sources_from_irq(); -} - -// Test code calls this if HAVE_BTSTACK_STDIN is defined and it wants key presses -void btstack_stdin_setup(void (*handler)(char c)) { - if (stdin_handler) { - return; - } - - // set handler - stdin_handler = handler; - - // set up polling data_source - btstack_run_loop_set_data_source_handler(&stdin_data_source, &btstack_stdin_process); - btstack_run_loop_enable_data_source_callbacks(&stdin_data_source, DATA_SOURCE_CALLBACK_POLL); - btstack_run_loop_add_data_source(&stdin_data_source); - - stdio_set_chars_available_callback(on_chars_available_callback, NULL); -} - -// Deinit everything -void btstack_stdin_reset(void){ - if (!stdin_handler) { - return; - } - stdio_set_chars_available_callback(NULL, NULL); - stdin_handler = NULL; - btstack_run_loop_remove_data_source(&stdin_data_source); -} - -#endif \ No newline at end of file diff --git a/lib/main/pico-sdk/rp2_common/pico_btstack/doc.h b/lib/main/pico-sdk/rp2_common/pico_btstack/doc.h deleted file mode 100644 index 0adf21901f..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_btstack/doc.h +++ /dev/null @@ -1,27 +0,0 @@ -/** - * \defgroup pico_btstack pico_btstack - * \brief Integration/wrapper libraries for BTstack - * the documentation for which is here. - * - * A supplemental license for BTstack (in addition to the stock BTstack licensing terms) is provided here. - * - * The \c \b pico_btstack_ble library adds the support needed for Bluetooth Low Energy (BLE). The \c \b pico_btstack_classic library adds the support needed for Bluetooth Classic. - * You can link to either library individually, or to both libraries thus enabling dual-mode support provided by BTstack. - * - * To use BTstack you need to provide a \c btstack_config.h file in your source tree and add its location to your include path. - * The BTstack configuration macros \c ENABLE_CLASSIC and \c ENABLE_BLE are defined for you when you link the \c pico_btstack_classic and \c pico_btstack_ble libraries respectively, so you should not define them yourself. - * - * For more details, see How to configure BTstack and the relevant pico-examples. - * - * The follow libraries are provided for you to link. - * * \c \b pico_btstack_ble - Adds Bluetooth Low Energy (LE) support. - * * \c \b pico_btstack_classic - Adds Bluetooth Classic support. - * * \c \b pico_btstack_sbc_encoder - Adds Bluetooth Sub Band Coding (SBC) encoder support. - * * \c \b pico_btstack_sbc_decoder - Adds Bluetooth Sub Band Coding (SBC) decoder support. - * * \c \b pico_btstack_bnep_lwip - Adds Bluetooth Network Encapsulation Protocol (BNEP) support using LwIP. - * * \c \b pico_btstack_bnep_lwip_sys_freertos - Adds Bluetooth Network Encapsulation Protocol (BNEP) support using LwIP with FreeRTOS for NO_SYS=0. - * - * \note The CMake function pico_btstack_make_gatt_header can be used to run the BTstack compile_gatt tool to make a GATT header file from a BTstack GATT file. - * - * \sa pico_btstack_cyw43 in pico_cyw43_driver, which adds the cyw43 driver support needed for BTstack including BTstack run loop support. - */ diff --git a/lib/main/pico-sdk/rp2_common/pico_btstack/include/pico/btstack_flash_bank.h b/lib/main/pico-sdk/rp2_common/pico_btstack/include/pico/btstack_flash_bank.h deleted file mode 100644 index 6d914f00e4..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_btstack/include/pico/btstack_flash_bank.h +++ /dev/null @@ -1,39 +0,0 @@ -/* - * Copyright (c) 2023 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _PICO_BTSTACK_FLASH_BANK_H -#define _PICO_BTSTACK_FLASH_BANK_H - -#include "pico.h" -#include "hardware/flash.h" -#include "hal_flash_bank.h" - -#ifdef __cplusplus -extern "C" { -#endif - -// PICO_CONFIG: PICO_FLASH_BANK_TOTAL_SIZE, Total size of the Bluetooth flash storage. Must be an even multiple of FLASH_SECTOR_SIZE, type=int, default=FLASH_SECTOR_SIZE * 2, group=pico_btstack -#ifndef PICO_FLASH_BANK_TOTAL_SIZE -#define PICO_FLASH_BANK_TOTAL_SIZE (FLASH_SECTOR_SIZE * 2u) -#endif - -// PICO_CONFIG: PICO_FLASH_BANK_STORAGE_OFFSET, Offset in flash of the Bluetooth flash storage, type=int, default=PICO_FLASH_SIZE_BYTES - PICO_FLASH_BANK_TOTAL_SIZE, group=pico_btstack -#ifndef PICO_FLASH_BANK_STORAGE_OFFSET -#define PICO_FLASH_BANK_STORAGE_OFFSET (PICO_FLASH_SIZE_BYTES - PICO_FLASH_BANK_TOTAL_SIZE) -#endif - -/** - * \brief Return the singleton BTstack HAL flash instance, used for non-volatile storage - * \ingroup pico_btstack - * - * \note By default two sectors at the end of flash are used (see \c PICO_FLASH_BANK_STORAGE_OFFSET and \c PICO_FLASH_BANK_TOTAL_SIZE) - */ -const hal_flash_bank_t *pico_flash_bank_instance(void); - -#ifdef __cplusplus -} -#endif -#endif diff --git a/lib/main/pico-sdk/rp2_common/pico_btstack/include/pico/btstack_run_loop_async_context.h b/lib/main/pico-sdk/rp2_common/pico_btstack/include/pico/btstack_run_loop_async_context.h deleted file mode 100644 index d1b09b7dc8..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_btstack/include/pico/btstack_run_loop_async_context.h +++ /dev/null @@ -1,29 +0,0 @@ -/* - * Copyright (c) 2023 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _PICO_BTSTACK_RUN_LOOP_ASYNC_CONTEXT_H -#define _PICO_BTSTACK_RUN_LOOP_ASYNC_CONTEXT_H - -#include "btstack_run_loop.h" -#include "pico/async_context.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief Initialize and return the singleton BTstack run loop instance that integrates with the async_context API - * \ingroup pico_btstack - * - * \param context the async_context instance that provides the abstraction for handling asynchronous work. - * \return the BTstack run loop instance - */ -const btstack_run_loop_t *btstack_run_loop_async_context_get_instance(async_context_t *context); - -#ifdef __cplusplus -} -#endif -#endif diff --git a/lib/main/pico-sdk/rp2_common/pico_clib_interface/doc.h b/lib/main/pico-sdk/rp2_common/pico_clib_interface/doc.h deleted file mode 100644 index 1fa325800d..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_clib_interface/doc.h +++ /dev/null @@ -1,4 +0,0 @@ -/** - * \defgroup pico_clib_interface pico_clib_interface - * \brief Provides the necessary glue code required by the particular C/C++ runtime being used - */ diff --git a/lib/main/pico-sdk/rp2_common/pico_clib_interface/include/llvm_libc/sys/cdefs.h b/lib/main/pico-sdk/rp2_common/pico_clib_interface/include/llvm_libc/sys/cdefs.h deleted file mode 100644 index 0047d0bd34..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_clib_interface/include/llvm_libc/sys/cdefs.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef __PICO_LLVM_LIBC_SYS_CDEFS_H -#define __PICO_LLVM_LIBC_SYS_CDEFS_H - -#if defined(__STDC__) || defined(__cplusplus) - -#define __CONCAT1(x,y) x ## y -#define __CONCAT(x,y) __CONCAT1(x,y) -#define __STRING(x) #x -#define __XSTRING(x) __STRING(x) - -#endif - -#define __unused __attribute__((__unused__)) -#define __used __attribute__((__used__)) -#define __packed __attribute__((__packed__)) -#define __aligned(x) __attribute__((__aligned__(x))) - -#define __always_inline __inline__ __attribute__((__always_inline__)) -#define __noinline __attribute__((__noinline__)) - -#define __printflike(fmtarg, firstvararg) \ - __attribute__((__format__ (__printf__, fmtarg, firstvararg))) - -#endif diff --git a/lib/main/pico-sdk/rp2_common/pico_clib_interface/include/llvm_libc/sys/stat.h b/lib/main/pico-sdk/rp2_common/pico_clib_interface/include/llvm_libc/sys/stat.h deleted file mode 100644 index b34a5c8d32..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_clib_interface/include/llvm_libc/sys/stat.h +++ /dev/null @@ -1,14 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _PICO_LLVM_LIBC_SYS_STAT_H -#define _PICO_LLVM_LIBC_SYS_STAT_H - -typedef int off_t; - -struct stat {}; - -#endif diff --git a/lib/main/pico-sdk/rp2_common/pico_clib_interface/include/llvm_libc/sys/time.h b/lib/main/pico-sdk/rp2_common/pico_clib_interface/include/llvm_libc/sys/time.h deleted file mode 100644 index 3d37f1c252..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_clib_interface/include/llvm_libc/sys/time.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _PICO_LLVM_LIBC_SYS_TIME_H -#define _PICO_LLVM_LIBC_SYS_TIME_H - -#include <__llvm-libc-common.h> - -#include -#include - -typedef long suseconds_t; - -struct timeval { - time_t tv_sec; - suseconds_t tv_usec; -}; - -struct timezone { - int tz_minuteswest; - int tz_dsttime; -}; - -__BEGIN_C_DECLS - -int gettimeofday(struct timeval *tv, struct timezone *tz); -int settimeofday(const struct timeval *tv, const struct timezone *tz); - -__END_C_DECLS - -#endif // _PICO_LLVM_LIBC_SYS_TIME_H diff --git a/lib/main/pico-sdk/rp2_common/pico_clib_interface/include/llvm_libc/sys/times.h b/lib/main/pico-sdk/rp2_common/pico_clib_interface/include/llvm_libc/sys/times.h deleted file mode 100644 index 16dee1e5b1..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_clib_interface/include/llvm_libc/sys/times.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _PICO_LLVM_LIBC_SYS_TIMES_H -#define _PICO_LLVM_LIBC_SYS_TIMES_H - -#include - -#define CLOCKS_PER_SEC 100 - -typedef int clock_t; - -struct tms { - clock_t tms_utime; - clock_t tms_stime; - clock_t tms_cutime; - clock_t tms_cstime; -}; - -#endif diff --git a/lib/main/pico-sdk/rp2_common/pico_clib_interface/include/llvm_libc/sys/types.h b/lib/main/pico-sdk/rp2_common/pico_clib_interface/include/llvm_libc/sys/types.h deleted file mode 100644 index 33406d9c32..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_clib_interface/include/llvm_libc/sys/types.h +++ /dev/null @@ -1,10 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _PICO_LLVM_LIBC_SYS_TYPES_H -#define _PICO_LLVM_LIBC_SYS_TYPES_H - -#endif diff --git a/lib/main/pico-sdk/rp2_common/pico_clib_interface/include/llvm_libc/time.h b/lib/main/pico-sdk/rp2_common/pico_clib_interface/include/llvm_libc/time.h deleted file mode 100644 index bb37c7effd..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_clib_interface/include/llvm_libc/time.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _PICO_LLVM_LIBC_TIME_H -#define _PICO_LLVM_LIBC_TIME_H - -#include <__llvm-libc-common.h> - -#include -#include - -__BEGIN_C_DECLS - -struct tm* localtime_r(const time_t* timer, struct tm* buf); - -__END_C_DECLS - -#include_next - -#endif // _PICO_LLVM_LIBC_TIME_H diff --git a/lib/main/pico-sdk/rp2_common/pico_clib_interface/include/llvm_libc/unistd.h b/lib/main/pico-sdk/rp2_common/pico_clib_interface/include/llvm_libc/unistd.h deleted file mode 100644 index 1322eae949..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_clib_interface/include/llvm_libc/unistd.h +++ /dev/null @@ -1,20 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _PICO_LLVM_LIBC_UNISTD_H -#define _PICO_LLVM_LIBC_UNISTD_H - -#include <__llvm-libc-common.h> - -typedef int pid_t; - -__BEGIN_C_DECLS - -_Noreturn void _exit(int) __NOEXCEPT; - -__END_C_DECLS - -#endif // _PICO_LLVM_LIBC_UNISTD_H diff --git a/lib/main/pico-sdk/rp2_common/pico_clib_interface/llvm_libc_interface.c b/lib/main/pico-sdk/rp2_common/pico_clib_interface/llvm_libc_interface.c deleted file mode 100644 index da42813351..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_clib_interface/llvm_libc_interface.c +++ /dev/null @@ -1,110 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include -#include - -#include - -#include "pico/runtime_init.h" -#include "pico/stdio.h" -#include "pico/time.h" - -#if PICO_ENTER_USB_BOOT_ON_EXIT -#include "pico/bootrom.h" -#endif - -// These functions are defined by POSIX and not C standard. - -static int64_t epoch_time_us_since_boot; - -int gettimeofday(struct timeval *__restrict tv, __unused struct timezone *__restrict tz) { - if (tv) { - int64_t us_since_epoch = ((int64_t)to_us_since_boot(get_absolute_time())) - epoch_time_us_since_boot; - tv->tv_sec = (time_t)(us_since_epoch / 1000000); - tv->tv_usec = (suseconds_t)(us_since_epoch % 1000000); - } - return 0; -} - -int settimeofday(__unused const struct timeval *tv, __unused const struct timezone *tz) { - if (tv) { - int64_t us_since_epoch = tv->tv_sec * 1000000 + tv->tv_usec; - epoch_time_us_since_boot = (int64_t)to_us_since_boot(get_absolute_time()) - us_since_epoch; - } - return 0; -} - -// TODO: This should be a thread-local variable. -int errno; - -int *__llvm_libc_errno(void) { return &errno; } - -struct __llvm_libc_stdio_cookie {}; - -struct __llvm_libc_stdio_cookie __llvm_libc_stdin_cookie; -struct __llvm_libc_stdio_cookie __llvm_libc_stdout_cookie; -struct __llvm_libc_stdio_cookie __llvm_libc_stderr_cookie; - -ssize_t __llvm_libc_stdio_read(__unused void *cookie, char *buf, size_t size) { - for (size_t i = 0; i < size; i++) { - buf[i] = getchar_timeout_us(0); - } - return size; -} - -ssize_t __llvm_libc_stdio_write(__unused void *cookie, const char *buf, size_t size) { - // TODO: We would ideally use `stdio_put_string` from pico_stdio. - for (size_t i = 0; i < size; i++) { - putchar_raw(buf[i]); - } - return size; -} - -void __cxa_finalize(__unused void *dso) {} - -void __attribute__((noreturn)) __llvm_libc_exit(__unused int status) { -#if PICO_ENTER_USB_BOOT_ON_EXIT - reset_usb_boot(0,0); -#else - while (1) { - __breakpoint(); - } -#endif -} - -void _exit(int) __attribute__((noreturn, alias("__llvm_libc_exit"))); - -void runtime_init(void) { -#ifndef NDEBUG - if (__get_current_exception()) { - // crap; started in exception handler - __breakpoint(); - } -#endif - -#if !PICO_RUNTIME_SKIP_INIT_PER_CORE_INSTALL_STACK_GUARD - // install core0 stack guard - extern char __StackBottom; - runtime_init_per_core_install_stack_guard(&__StackBottom); -#endif - - // todo maybe we want to do this in the future, but it does stuff like register_tm_clones - // which we didn't do in previous SDKs - //extern void __libc_init_array(void); - //__libc_init_array(); - - // ... so instead just do the __preinit_array - runtime_run_initializers(); - // ... and the __init_array - extern void (*__init_array_start)(void); - extern void (*__init_array_end)(void); - for (void (**p)(void) = &__init_array_start; p < &__init_array_end; ++p) { - (*p)(); - } -} - diff --git a/lib/main/pico-sdk/rp2_common/pico_clib_interface/newlib_interface.c b/lib/main/pico-sdk/rp2_common/pico_clib_interface/newlib_interface.c deleted file mode 100644 index 8925e54640..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_clib_interface/newlib_interface.c +++ /dev/null @@ -1,199 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include -#include -#include -#include -#include -#include -#if PICO_ENTER_USB_BOOT_ON_EXIT -#include "pico/bootrom.h" -#endif -#include "pico/time.h" -#include "pico/runtime_init.h" - -#if LIB_PICO_PRINTF_PICO -#include "pico/printf.h" -#else -#define weak_raw_printf printf -#define weak_raw_vprintf vprintf -#endif -#if LIB_PICO_STDIO -#include "pico/stdio.h" -#endif - -#if PICO_ENTER_USB_BOOT_ON_EXIT -#include "pico/bootrom.h" -#endif - -extern char __StackLimit; /* Set by linker. */ - -#define STDIO_HANDLE_STDIN 0 -#define STDIO_HANDLE_STDOUT 1 -#define STDIO_HANDLE_STDERR 2 - -void __attribute__((noreturn)) __weak _exit(__unused int status) { -#if PICO_ENTER_USB_BOOT_ON_EXIT - reset_usb_boot(0,0); -#else - while (1) { - __breakpoint(); - } -#endif -} - -__weak void *_sbrk(int incr) { - extern char end; /* Set by linker. */ - static char *heap_end; - char *prev_heap_end; - - if (heap_end == 0) - heap_end = &end; - - prev_heap_end = heap_end; - char *next_heap_end = heap_end + incr; - - if (__builtin_expect(next_heap_end > (&__StackLimit), false)) { -#if PICO_USE_OPTIMISTIC_SBRK - if (heap_end == &__StackLimit) { -// errno = ENOMEM; - return (char *) -1; - } - next_heap_end = &__StackLimit; -#else - return (char *) -1; -#endif - } - - heap_end = next_heap_end; - return (void *) prev_heap_end; -} - -static int64_t epoch_time_us_since_boot; - -__weak int _gettimeofday (struct timeval *__restrict tv, __unused void *__restrict tz) { - if (tv) { - int64_t us_since_epoch = ((int64_t)to_us_since_boot(get_absolute_time())) - epoch_time_us_since_boot; - tv->tv_sec = (time_t)(us_since_epoch / 1000000); - tv->tv_usec = (suseconds_t)(us_since_epoch % 1000000); - } - return 0; -} - -__weak int settimeofday(__unused const struct timeval *tv, __unused const struct timezone *tz) { - if (tv) { - int64_t us_since_epoch = tv->tv_sec * 1000000 + tv->tv_usec; - epoch_time_us_since_boot = (int64_t)to_us_since_boot(get_absolute_time()) - us_since_epoch; - } - return 0; -} - -__weak int _times(struct tms *tms) { -#if CLOCKS_PER_SEC >= 1000000 - tms->tms_utime = (clock_t)(to_us_since_boot(get_absolute_time()) * (CLOCKS_PER_SEC / 1000000)); -#else - tms->tms_utime = (clock_t)(to_us_since_boot(get_absolute_time()) / (1000000 / CLOCKS_PER_SEC)); -#endif - tms->tms_stime = 0; - tms->tms_cutime = 0; - tms->tms_cstime = 0; - return 0; -} - -__weak pid_t _getpid(void) { - return 0; -} - -__weak int _kill(__unused pid_t pid, __unused int sig) { - return -1; -} - -int __attribute__((weak)) _read(int handle, char *buffer, int length) { -#if LIB_PICO_STDIO - if (handle == STDIO_HANDLE_STDIN) { - return stdio_get_until(buffer, length, at_the_end_of_time); - } -#endif - return -1; -} - -int __attribute__((weak)) _write(int handle, char *buffer, int length) { -#if LIB_PICO_STDIO - if (handle == STDIO_HANDLE_STDOUT || handle == STDIO_HANDLE_STDERR) { - stdio_put_string(buffer, length, false, true); - return length; - } -#endif - return -1; -} - -int __attribute__((weak)) _open(__unused const char *fn, __unused int oflag, ...) { - return -1; -} - -int __attribute__((weak)) _close(__unused int fd) { - return -1; -} - -off_t __attribute__((weak)) _lseek(__unused int fd, __unused off_t pos, __unused int whence) { - return -1; -} - -int __attribute__((weak)) _fstat(__unused int fd, __unused struct stat *buf) { - return -1; -} - -int __attribute__((weak)) _isatty(int fd) { - return fd == STDIO_HANDLE_STDIN || fd == STDIO_HANDLE_STDOUT || fd == STDIO_HANDLE_STDERR; -} - -// exit is not useful... no desire to pull in __call_exitprocs -void exit(int status) { - _exit(status); -} - -// incorrect warning from GCC 6 -GCC_Pragma("GCC diagnostic push") -GCC_Pragma("GCC diagnostic ignored \"-Wsuggest-attribute=format\"") -void __weak __assert_func(const char *file, int line, const char *func, const char *failedexpr) { - weak_raw_printf("assertion \"%s\" failed: file \"%s\", line %d%s%s\n", - failedexpr, file, line, func ? ", function: " : "", - func ? func : ""); - - _exit(1); -} -GCC_Pragma("GCC diagnostic pop") - -void runtime_init(void) { -#ifndef NDEBUG - if (__get_current_exception()) { - // crap; started in exception handler - __breakpoint(); - } -#endif - -#if !PICO_RUNTIME_SKIP_INIT_PER_CORE_INSTALL_STACK_GUARD - // install core0 stack guard - extern char __StackBottom; - runtime_init_per_core_install_stack_guard(&__StackBottom); -#endif - - // todo maybe we want to do this in the future, but it does stuff like register_tm_clones - // which we didn't do in previous SDKs - //extern void __libc_init_array(void); - //__libc_init_array(); - - // ... so instead just do the __preinit_array - runtime_run_initializers(); - // ... and the __init_array - extern void (*__init_array_start)(void); - extern void (*__init_array_end)(void); - for (void (**p)(void) = &__init_array_start; p < &__init_array_end; ++p) { - (*p)(); - } -} \ No newline at end of file diff --git a/lib/main/pico-sdk/rp2_common/pico_clib_interface/picolibc_interface.c b/lib/main/pico-sdk/rp2_common/pico_clib_interface/picolibc_interface.c deleted file mode 100644 index b10bb418d6..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_clib_interface/picolibc_interface.c +++ /dev/null @@ -1,138 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include -#include -#include - -#include "pico.h" -#if LIB_PICO_STDIO -#include "pico/stdio.h" -#endif - -#if PICO_ENTER_USB_BOOT_ON_EXIT -#include "pico/bootrom.h" -#endif - -#include "pico/time.h" -#include "pico/runtime_init.h" - -#if LIB_PICO_PRINTF_PICO -#include "pico/printf.h" -#else -#define weak_raw_printf printf -#define weak_raw_vprintf vprintf -#endif - -static int picolibc_putc(char c, __unused FILE *file) { -#if LIB_PICO_STDIO - stdio_putchar(c); -#endif - return c; -} - -static int picolibc_getc(__unused FILE *file) { -#if LIB_PICO_STDIO - return stdio_getchar(); -#endif -} - -static int picolibc_flush(__unused FILE *file) { -#if LIB_PICO_STDIO - stdio_flush(); -#endif - return 0; -} - -static FILE __stdio = FDEV_SETUP_STREAM(picolibc_putc, - picolibc_getc, - picolibc_flush, - _FDEV_SETUP_RW); - -FILE *const stdin = &__stdio; __strong_reference(stdin, stdout); __strong_reference(stdin, stderr); - -void __weak __assert_func(const char *file, int line, const char *func, const char *failedexpr) { - weak_raw_printf("assertion \"%s\" failed: file \"%s\", line %d%s%s\n", - failedexpr, file, line, func ? ", function: " : "", - func ? func : ""); - - _exit(1); -} - - -void __attribute__((noreturn)) __weak _exit(__unused int status) { -#if PICO_ENTER_USB_BOOT_ON_EXIT - reset_usb_boot(0,0); -#else - while (1) { - __breakpoint(); - } -#endif -} - -static int64_t epoch_time_us_since_boot; - -__weak int gettimeofday (struct timeval *__restrict tv, __unused void *__restrict tz) { - if (tv) { - int64_t us_since_epoch = ((int64_t)to_us_since_boot(get_absolute_time())) - epoch_time_us_since_boot; - tv->tv_sec = (time_t)(us_since_epoch / 1000000); - tv->tv_usec = (suseconds_t)(us_since_epoch % 1000000); - } - return 0; -} - -__weak int settimeofday(__unused const struct timeval *tv, __unused const struct timezone *tz) { - if (tv) { - int64_t us_since_epoch = tv->tv_sec * 1000000 + tv->tv_usec; - epoch_time_us_since_boot = (int64_t)to_us_since_boot(get_absolute_time()) - us_since_epoch; - } - return 0; -} - - -void runtime_init(void) { -#ifndef NDEBUG - if (__get_current_exception()) { - // crap; started in exception handler - __breakpoint(); - } -#endif - -#if !PICO_RUNTIME_SKIP_INIT_PER_CORE_INSTALL_STACK_GUARD - // install core0 stack guard - extern char __StackBottom; - runtime_init_per_core_install_stack_guard(&__StackBottom); -#endif - - // piolibc __libc_init_array does __preint_array and __init_array - extern void __libc_init_array(void); - __libc_init_array(); -} - -#if !PICO_RUNTIME_NO_INIT_PER_CORE_TLS_SETUP -__weak void runtime_init_pre_core_tls_setup(void) { - // for now we just set the same global area on both cores - // note: that this is superfluous with the stock picolibc it seems, since it is itself - // using a version of __aeabi_read_tp that returns the same pointer on both cores - extern void __tls_base; - extern void _set_tls(void *tls); - _set_tls(&__tls_base); -} -#endif - -#if !PICO_RUNTIME_SKIP_INIT_PER_CORE_TLS_SETUP -PICO_RUNTIME_INIT_FUNC_PER_CORE(runtime_init_pre_core_tls_setup, PICO_RUNTIME_INIT_PER_CORE_TLS_SETUP); -#endif - -//// naked as it must preserve everything except r0 and lr -//uint32_t __attribute__((naked)) WRAPPER_FUNC(__aeabi_read_tp)() { -// // note for now we are just returning a shared instance on both cores -// pico_default_asm_volatile( -// "ldr r0, =__tls_base\n" -// "bx lr\n" -// ); -//} \ No newline at end of file diff --git a/lib/main/pico-sdk/rp2_common/pico_crt0/crt0.S b/lib/main/pico-sdk/rp2_common/pico_crt0/crt0.S deleted file mode 100644 index e408b7ded1..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_crt0/crt0.S +++ /dev/null @@ -1,544 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "pico.h" -#include "pico/asm_helper.S" - -#include "pico/platform/cpu_regs.h" - -#include "hardware/regs/addressmap.h" -#include "hardware/regs/sio.h" -#include "pico/binary_info/defs.h" -#include "boot/picobin.h" -#include "pico/bootrom.h" - -#ifdef NDEBUG -#ifndef COLLAPSE_IRQS -#define COLLAPSE_IRQS -#endif -#endif - -pico_default_asm_setup - -.section .vectors, "ax" -.align 2 - -.global __vectors, __VECTOR_TABLE -__VECTOR_TABLE: -__vectors: -.word __StackTop -.word _reset_handler -.word isr_nmi -.word isr_hardfault -.word isr_invalid // Reserved, should never fire -.word isr_invalid // Reserved, should never fire -.word isr_invalid // Reserved, should never fire -.word isr_invalid // Reserved, should never fire -.word isr_invalid // Reserved, should never fire -.word isr_invalid // Reserved, should never fire -.word isr_invalid // Reserved, should never fire -.word isr_svcall -.word isr_invalid // Reserved, should never fire -.word isr_invalid // Reserved, should never fire -.word isr_pendsv -.word isr_systick -#if PICO_NO_STORED_VECTOR_TABLE && !PICO_NO_FLASH // note in no flash binary, we only have the single RAM vector table anyway -#if PICO_NO_RAM_VECTOR_TABLE -#error Can't specify PICO_NO_STORED_VECTOR_TABLE and PICO_NO_RAM_VECTOR_TABLE -#endif -// we don't include any IRQ vectors; we will initialize them during runtime_init in the RAM vector table -#else - -.macro if_irq_word num func -.if \num < NUM_IRQS -.word \func -.endif -.endm - -// we include a lot of these to allow for different number of IRQs. -// if_irq_word will only include IRQs that are valid, but we can't -// use a macro loop because isr_irqx MUST appear in the source -// as CMSIS rename exceptions #defines it to another value -if_irq_word 0 isr_irq0 -if_irq_word 1 isr_irq1 -if_irq_word 2 isr_irq2 -if_irq_word 3 isr_irq3 -if_irq_word 4 isr_irq4 -if_irq_word 5 isr_irq5 -if_irq_word 6 isr_irq6 -if_irq_word 7 isr_irq7 -if_irq_word 8 isr_irq8 -if_irq_word 9 isr_irq9 -if_irq_word 10 isr_irq10 -if_irq_word 11 isr_irq11 -if_irq_word 12 isr_irq12 -if_irq_word 13 isr_irq13 -if_irq_word 14 isr_irq14 -if_irq_word 15 isr_irq15 -if_irq_word 16 isr_irq16 -if_irq_word 17 isr_irq17 -if_irq_word 18 isr_irq18 -if_irq_word 19 isr_irq19 -if_irq_word 20 isr_irq20 -if_irq_word 21 isr_irq21 -if_irq_word 22 isr_irq22 -if_irq_word 23 isr_irq23 -if_irq_word 24 isr_irq24 -if_irq_word 25 isr_irq25 -if_irq_word 26 isr_irq26 -if_irq_word 27 isr_irq27 -if_irq_word 28 isr_irq28 -if_irq_word 29 isr_irq29 -if_irq_word 30 isr_irq30 -if_irq_word 31 isr_irq31 -if_irq_word 32 isr_irq32 -if_irq_word 33 isr_irq33 -if_irq_word 34 isr_irq34 -if_irq_word 35 isr_irq35 -if_irq_word 36 isr_irq36 -if_irq_word 37 isr_irq37 -if_irq_word 38 isr_irq38 -if_irq_word 39 isr_irq39 -if_irq_word 40 isr_irq40 -if_irq_word 41 isr_irq41 -if_irq_word 42 isr_irq42 -if_irq_word 43 isr_irq43 -if_irq_word 44 isr_irq44 -if_irq_word 45 isr_irq45 -if_irq_word 46 isr_irq46 -if_irq_word 47 isr_irq47 -if_irq_word 48 isr_irq48 -if_irq_word 49 isr_irq49 -if_irq_word 50 isr_irq50 -if_irq_word 51 isr_irq51 -if_irq_word 52 isr_irq52 -if_irq_word 53 isr_irq53 -if_irq_word 54 isr_irq54 -if_irq_word 55 isr_irq55 -if_irq_word 56 isr_irq56 -if_irq_word 57 isr_irq57 -if_irq_word 58 isr_irq58 -if_irq_word 59 isr_irq59 -if_irq_word 60 isr_irq60 -if_irq_word 61 isr_irq61 -if_irq_word 62 isr_irq62 -if_irq_word 63 isr_irq63 -if_irq_word 64 isr_irq64 -if_irq_word 65 isr_irq65 -if_irq_word 66 isr_irq66 -if_irq_word 67 isr_irq67 -if_irq_word 68 isr_irq68 -if_irq_word 69 isr_irq69 -if_irq_word 70 isr_irq70 -if_irq_word 71 isr_irq71 -if_irq_word 72 isr_irq72 -if_irq_word 73 isr_irq73 -if_irq_word 74 isr_irq74 -if_irq_word 75 isr_irq75 -if_irq_word 76 isr_irq76 -if_irq_word 77 isr_irq77 -if_irq_word 78 isr_irq78 -if_irq_word 79 isr_irq79 -#if NUM_IRQS > 80 -#error more IRQ entries required -#endif -#endif - -// all default exception handlers do nothing, and we can check for them being set to our -// default values by seeing if they point to somewhere between __defaults_isrs_start and __default_isrs_end -.global __default_isrs_start -__default_isrs_start: - -// Declare a weak symbol for each ISR. -// By default, they will fall through to the undefined IRQ handler below (breakpoint), -// but can be overridden by C functions with correct name. - -.macro decl_isr_bkpt name -.weak \name -.type \name,%function -.thumb_func -\name: - bkpt #0 -.endm - -// these are separated out for clarity -decl_isr_bkpt isr_invalid -decl_isr_bkpt isr_nmi -decl_isr_bkpt isr_hardfault -decl_isr_bkpt isr_svcall -decl_isr_bkpt isr_pendsv -decl_isr_bkpt isr_systick - -.global __default_isrs_end -__default_isrs_end: - -.altmacro -.macro decl_isr name -#if !PICO_NO_STORED_VECTOR_TABLE | PICO_NO_FLASH -// We declare a weak label, so user can override -.weak \name -#else -// We declare a strong label, so user can't override (their version would not automatically be used) -#endif -.type \name,%function -.thumb_func -\name: -.endm - -.macro if_irq_decl num func -.if \num < NUM_IRQS -decl_isr \func -.endif -.endm - -if_irq_decl 0 isr_irq0 -if_irq_decl 1 isr_irq1 -if_irq_decl 2 isr_irq2 -if_irq_decl 3 isr_irq3 -if_irq_decl 4 isr_irq4 -if_irq_decl 5 isr_irq5 -if_irq_decl 6 isr_irq6 -if_irq_decl 7 isr_irq7 -if_irq_decl 8 isr_irq8 -if_irq_decl 9 isr_irq9 -if_irq_decl 10 isr_irq10 -if_irq_decl 11 isr_irq11 -if_irq_decl 12 isr_irq12 -if_irq_decl 13 isr_irq13 -if_irq_decl 14 isr_irq14 -if_irq_decl 15 isr_irq15 -if_irq_decl 16 isr_irq16 -if_irq_decl 17 isr_irq17 -if_irq_decl 18 isr_irq18 -if_irq_decl 19 isr_irq19 -if_irq_decl 20 isr_irq20 -if_irq_decl 21 isr_irq21 -if_irq_decl 22 isr_irq22 -if_irq_decl 23 isr_irq23 -if_irq_decl 24 isr_irq24 -if_irq_decl 25 isr_irq25 -if_irq_decl 26 isr_irq26 -if_irq_decl 27 isr_irq27 -if_irq_decl 28 isr_irq28 -if_irq_decl 29 isr_irq29 -if_irq_decl 30 isr_irq30 -if_irq_decl 31 isr_irq31 -if_irq_decl 32 isr_irq32 -if_irq_decl 33 isr_irq33 -if_irq_decl 34 isr_irq34 -if_irq_decl 35 isr_irq35 -if_irq_decl 36 isr_irq36 -if_irq_decl 37 isr_irq37 -if_irq_decl 38 isr_irq38 -if_irq_decl 39 isr_irq39 -if_irq_decl 40 isr_irq40 -if_irq_decl 41 isr_irq41 -if_irq_decl 42 isr_irq42 -if_irq_decl 43 isr_irq43 -if_irq_decl 44 isr_irq44 -if_irq_decl 45 isr_irq45 -if_irq_decl 46 isr_irq46 -if_irq_decl 47 isr_irq47 -if_irq_decl 48 isr_irq48 -if_irq_decl 49 isr_irq49 -if_irq_decl 50 isr_irq50 -if_irq_decl 51 isr_irq51 -if_irq_decl 52 isr_irq52 -if_irq_decl 53 isr_irq53 -if_irq_decl 54 isr_irq54 -if_irq_decl 55 isr_irq55 -if_irq_decl 56 isr_irq56 -if_irq_decl 57 isr_irq57 -if_irq_decl 58 isr_irq58 -if_irq_decl 59 isr_irq59 -if_irq_decl 60 isr_irq60 -if_irq_decl 61 isr_irq61 -if_irq_decl 62 isr_irq62 -if_irq_decl 63 isr_irq63 -if_irq_decl 64 isr_irq64 -if_irq_decl 65 isr_irq65 -if_irq_decl 66 isr_irq66 -if_irq_decl 67 isr_irq67 -if_irq_decl 68 isr_irq68 -if_irq_decl 69 isr_irq69 -if_irq_decl 70 isr_irq70 -if_irq_decl 71 isr_irq71 -if_irq_decl 72 isr_irq72 -if_irq_decl 73 isr_irq73 -if_irq_decl 74 isr_irq74 -if_irq_decl 75 isr_irq75 -if_irq_decl 76 isr_irq76 -if_irq_decl 77 isr_irq77 -if_irq_decl 78 isr_irq78 -if_irq_decl 79 isr_irq79 -#if NUM_IRQS > 80 -#error more IRQ entries required -#endif - -// All unhandled USER IRQs fall through to here -.global __unhandled_user_irq -.thumb_func -__unhandled_user_irq: - mrs r0, ipsr - subs r0, #16 -.global unhandled_user_irq_num_in_r0 -unhandled_user_irq_num_in_r0: - bkpt #0 - -// ---------------------------------------------------------------------------- - -.section .binary_info_header, "a" - -// Header must be in first 256 bytes of main image (i.e. excluding flash boot2). -// For flash builds we put it immediately after vector table; for NO_FLASH the -// vectors are at a +0x100 offset because the bootrom enters RAM images directly -// at their lowest address, so we put the header in the VTOR alignment hole. - -#if !PICO_NO_BINARY_INFO -binary_info_header: -.word BINARY_INFO_MARKER_START -.word __binary_info_start -.word __binary_info_end -.word data_cpy_table // we may need to decode pointers that are in RAM at runtime. -.word BINARY_INFO_MARKER_END -#endif - -#include "embedded_start_block.inc.S" - -// ---------------------------------------------------------------------------- - -.section .reset, "ax" - -// On flash builds, the vector table comes first in the image (conventional). -// On NO_FLASH builds, the reset handler section comes first, as the entry -// point is at offset 0 (fixed due to bootrom), and VTOR is highly-aligned. -// Image is entered in various ways: -// -// - NO_FLASH builds are entered from beginning by UF2 bootloader -// -// - Flash builds vector through the table into _reset_handler from boot2 -// -// - Either type can be entered via _entry_point by the debugger, and flash builds -// must then be sent back round the boot sequence to properly initialise flash - -// ELF entry point: -.type _entry_point,%function -.thumb_func -.global _entry_point -_entry_point: - -#if PICO_NO_FLASH - // on the NO_FLASH case, we do not do a rest thru bootrom below, so the RCP may or may not have been initialized: - // - // in the normal (e.g. UF2 download etc. case) we will have passed thru bootrom initialization, but if - // a NO_FLASH binary is loaded by the debugger, and run directly after a reset, then we won't have. - // - // we must therefore initialize the RCP if it hasn't already been - -#if HAS_REDUNDANCY_COPROCESSOR - // just enable the RCP which is fine if it already was (we assume no other co-processors are enabled at this point to save space) - ldr r0, = PPB_BASE + M33_CPACR_OFFSET - movs r1, #ARM_CPU_PREFIXED(CPACR_CP7_BITS) - str r1, [r0] - // only initialize canary seeds if they haven't been (as to do so twice is a fault) - mrc p7, #1, apsr_nzcv, c0, c0, #0 - bmi 1f - // i dont think it much matters what we initialized to, as to have gotten here we must have not - // gone thru the bootrom (which a secure boot would have) - mcrr p7, #8, r0, r0, c0 - mcrr p7, #8, r0, r0, c1 - sev -1: -#endif - ldr r0, =__vectors - // Vector through our own table (SP, VTOR will not have been set up at - // this point). Same path for debugger entry and bootloader entry. -#else - // Debugger tried to run code after loading, so SSI is in 03h-only mode. - // Go back through bootrom + boot2 to properly initialise flash. - ldr r0, =BOOTROM_VTABLE_OFFSET -#endif - -_enter_vtable_in_r0: - ldr r1, =(PPB_BASE + ARM_CPU_PREFIXED(VTOR_OFFSET)) - str r0, [r1] - ldmia r0!, {r1, r2} - msr msp, r1 - bx r2 - -// Reset handler: -// - initialises .data -// - clears .bss -// - calls runtime_init -// - calls main -// - calls exit (which should eventually hang the processor via _exit) - -.type _reset_handler,%function -.thumb_func -_reset_handler: - // Only core 0 should run the C runtime startup code; core 1 is normally - // sleeping in the bootrom at this point but check to be sure (e.g. if - // debugger put core 1 at the ELF entry point for some reason) - ldr r0, =(SIO_BASE + SIO_CPUID_OFFSET) - ldr r0, [r0] -#if __ARM_ARCH_6M__ - cmp r0, #0 - beq 1f -#else - cbz r0, 1f -#endif -hold_non_core0_in_bootrom: - // Send back to the ROM to wait for core 0 to launch it. - ldr r0, =BOOTROM_VTABLE_OFFSET - b _enter_vtable_in_r0 -1: - -#if !PICO_RP2040 && PICO_EMBED_XIP_SETUP && !PICO_NO_FLASH - // Execute boot2 on the core 0 stack (it also gets copied into BOOTRAM due - // to inclusion in the data copy table below). Note the reference - // to __boot2_entry_point here is what prevents the .boot2 section from - // being garbage-collected. -_copy_xip_setup: - ldr r1, =__boot2_entry_point - mov r3, sp - add sp, #-256 - mov r2, sp - bl data_cpy -_call_xip_setup: - mov r0, sp - adds r0, #1 - blx r0 - add sp, #256 -#endif - - // In a NO_FLASH binary, don't perform .data etc copy, since it's loaded - // in-place by the SRAM load. Still need to clear .bss -#if !PICO_NO_FLASH - adr r4, data_cpy_table - - // assume there is at least one entry -1: - ldmia r4!, {r1-r3} - cmp r1, #0 - beq 2f - bl data_cpy - b 1b -2: -#endif - - // Zero out the BSS - ldr r1, =__bss_start__ - ldr r2, =__bss_end__ - movs r0, #0 - b bss_fill_test -bss_fill_loop: - stm r1!, {r0} -bss_fill_test: - cmp r1, r2 - bne bss_fill_loop - -platform_entry: // symbol for stack traces - // Use 32-bit jumps, in case these symbols are moved out of branch range - // (e.g. if main is in SRAM and crt0 in flash) -#if !__ARM_ARCH_6M__ - // Make sure stack limit is 0 - the user can set it themselves - // todo probably worth adding to the EXE_DEF in the future - movs r0, #0 - msr msplim, r0 -#endif - ldr r1, =runtime_init - blx r1 - ldr r1, =main - blx r1 - ldr r1, =exit - blx r1 - // exit should not return. If it does, hang the core. -1: // separate label because _exit can be moved out of branch range - bkpt #0 - b 1b - - -#if !PICO_NO_FLASH -data_cpy_loop: - ldm r1!, {r0} - stm r2!, {r0} -data_cpy: - cmp r2, r3 - blo data_cpy_loop - bx lr -#endif - -// Note the data copy table is still included for NO_FLASH builds, even though -// we skip the copy, because it is listed in binary info - -.align 2 -data_cpy_table: -#if PICO_RP2350 && PICO_EMBED_XIP_SETUP && !PICO_NO_FLASH -.word __boot2_start__ -.word BOOTRAM_BASE -.word BOOTRAM_BASE + 256 -#endif - -#if PICO_COPY_TO_RAM -.word __ram_text_source__ -.word __ram_text_start__ -.word __ram_text_end__ -#endif -.word __etext -.word __data_start__ -.word __data_end__ - -.word __scratch_x_source__ -.word __scratch_x_start__ -.word __scratch_x_end__ - -.word __scratch_y_source__ -.word __scratch_y_start__ -.word __scratch_y_end__ - -.word 0 // null terminator - -// ---------------------------------------------------------------------------- -// Provide safe defaults for _exit and runtime_init -// Full implementations usually provided by platform.c - -.weak runtime_init -.type runtime_init,%function -.thumb_func -runtime_init: - bx lr - -// ---------------------------------------------------------------------------- -// Stack/heap dummies to set size - -// Prior to SDK 1.5.1 these were `.section .stack` without the `, "a"`... Clang linker gives a warning about this, -// however setting it explicitly to `, "a"` makes GCC *now* discard the section unless it is also KEEP. This -// seems like very surprising behavior! -// -// Strictly the most correct thing to do (as .stack and .heap are unreferenced) is to mark them as "a", and also KEEP, which -// works correctly for both GCC and Clang, however doing so may break anyone who already has custom linker scripts without -// the KEEP. Therefore we will only add the "a" on Clang, but will also use KEEP to our own linker scripts. - -.macro spacer_section name -#if PICO_ASSEMBLER_IS_CLANG -.section \name, "a" -#else -.section \name -#endif -.endm - -spacer_section .stack -// align to allow for memory protection (although this alignment is pretty much ignored by linker script) -.p2align 5 - .equ StackSize, PICO_STACK_SIZE -.space StackSize - -spacer_section .heap -.p2align 2 - .equ HeapSize, PICO_HEAP_SIZE -.space HeapSize - -#include "embedded_end_block.inc.S" diff --git a/lib/main/pico-sdk/rp2_common/pico_crt0/crt0_riscv.S b/lib/main/pico-sdk/rp2_common/pico_crt0/crt0_riscv.S deleted file mode 100644 index 0e89ab150e..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_crt0/crt0_riscv.S +++ /dev/null @@ -1,593 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "pico.h" - -#include "hardware/regs/addressmap.h" -#include "hardware/regs/rvcsr.h" -#include "pico/binary_info/defs.h" -#include "boot/picobin.h" -#include "pico/bootrom_constants.h" - -#ifdef NDEBUG -#ifndef COLLAPSE_IRQS -#define COLLAPSE_IRQS -#endif -#endif - -#if !defined(PICO_CRT0_INCLUDE_PICOBIN_IMAGE_TYPE_ITEM) -#define PICO_CRT0_INCLUDE_PICOBIN_IMAGE_TYPE_ITEM 1 -#endif - -#ifndef PICO_CRT0_INCLUDE_PICOBIN_BLOCK -#define PICO_CRT0_INCLUDE_PICOBIN_BLOCK PICO_CRT0_INCLUDE_PICOBIN_IMAGE_TYPE_ITEM -#endif - -#ifndef PICO_CRT0_INCLUDE_PICOBIN_END_BLOCK -#define PICO_CRT0_INCLUDE_PICOBIN_END_BLOCK (PICO_CRT0_INCLUDE_PICOBIN_BLOCK && !PICO_NO_FLASH) -#endif - -// If vectors are in RAM, we put them in the .data section, so that they are -// preloaded by _reset_handler (assuming this is not a loaded-in-place -// binary). -#if PICO_NO_RAM_VECTOR_TABLE || PICO_NO_FLASH -.section .vectors, "ax" -#else -.section .data -#endif - -.p2align 6 -.global __vectors, __VECTOR_TABLE -__VECTOR_TABLE: -__vectors: - -// Hardware vector table for standard RISC-V interrupts, indicated by `mtvec`. - -.option push -.option norvc -.option norelax -j isr_riscv_machine_exception -.word 0 -.word 0 -j isr_riscv_machine_soft_irq -.word 0 -.word 0 -.word 0 -j isr_riscv_machine_timer -.word 0 -.word 0 -.word 0 -// j isr_riscv_machine_external_irq -> inlined below -.option pop - -// External IRQ dispatch, inlined into the last vector table slot. Note if -// this code is modified, the VTABLE_FIRST_IRQ define in platform_defs.h also -// needs to be modified (it identifies the beginning of the soft vector table) -.global isr_riscv_machine_external_irq -.weak isr_riscv_machine_external_irq -isr_riscv_machine_external_irq: - // Save caller saves and exception return state whilst IRQs are disabled. - // We can't be preempted during this time, but if a higher-priority IRQ - // arrives before we read meinext, that will be the one we enter. - addi sp, sp, -80 - sw ra, 0(sp) - sw t0, 4(sp) - sw t1, 8(sp) - sw t2, 12(sp) - sw a0, 16(sp) - sw a1, 20(sp) - sw a2, 24(sp) - sw a3, 28(sp) - sw a4, 32(sp) - sw a5, 36(sp) - sw a6, 40(sp) - sw a7, 44(sp) - sw t3, 48(sp) - sw t4, 52(sp) - sw t5, 56(sp) - sw t6, 60(sp) - csrr a0, mepc - csrr a1, mstatus - sw a0, 64(sp) - sw a1, 68(sp) -save_meicontext: - // Make sure to set meicontext.clearts to clear+save mie.msie/mtie along - // with ext IRQ context. We don't let these preempt ext IRQs because they - // clear meicontext.mreteirq, which breaks __get_current_exception(). - csrrsi a2, RVCSR_MEICONTEXT_OFFSET, RVCSR_MEICONTEXT_CLEARTS_BITS - sw a2, 72(sp) - -get_first_irq: - // Sample the current highest-priority active IRQ (left-shifted by 2) from - // meinext, and write 1 to meinext.update to update meicontext with the - // preemption priority and IRQ number of this IRQ - csrrsi a0, RVCSR_MEINEXT_OFFSET, RVCSR_MEINEXT_UPDATE_BITS - // MSB will be set if there is no active IRQ at the current priority level - bltz a0, no_more_irqs -dispatch_irq: - // Preemption priority was configured by meinext update, so enable preemption: - csrsi mstatus, 0x8 - // <- from this point we can be preempted by a higher-priority interrupt. - // meinext is pre-shifted by 2, so only an add is required to index table - lui a1, %hi(__soft_vector_table) - add a1, a1, a0 - lw a1, %lo(__soft_vector_table)(a1) - jalr ra, a1 - // Disable IRQs on returning so we can sample the next IRQ - csrci mstatus, 0x8 -get_next_irq: - // Get the next-highest-priority IRQ that is active at this level. If - // there is such an IRQ, update meicontext with new preemption priority. - csrrsi a0, RVCSR_MEINEXT_OFFSET, RVCSR_MEINEXT_UPDATE_BITS - // MSB will be set if there is no active IRQ at the current priority level - bgez a0, dispatch_irq - -no_more_irqs: - // Restore saved context and return from IRQ - lw a0, 64(sp) - lw a1, 68(sp) - lw a2, 72(sp) - csrw mepc, a0 - csrw mstatus, a1 - csrw RVCSR_MEICONTEXT_OFFSET, a2 - lw ra, 0(sp) - lw t0, 4(sp) - lw t1, 8(sp) - lw t2, 12(sp) - // skip a0 for now - lw a1, 20(sp) - lw a2, 24(sp) - lw a3, 28(sp) - lw a4, 32(sp) - lw a5, 36(sp) - lw a6, 40(sp) - lw a7, 44(sp) - lw t3, 48(sp) - lw t4, 52(sp) - lw t5, 56(sp) - lw t6, 60(sp) - // Before popping the stack frame, check if there is a new IRQ, and if so, - // abandon the mret and take the IRQ. This avoids a worst-case (restore -> - // mret -> enter -> save) latency. Note since we have already restored - // meicontext, we will have to re-save it, to re-clear mtie/msie. -check_irq_before_exit: - csrr a0, RVCSR_MEINEXT_OFFSET - bgez a0, save_meicontext - lw a0, 16(sp) - addi sp, sp, 80 - mret - -// Default software vector table for system interrupts, routed through -// mip.meip. Note this is assumed in e.g. hardware_irq to begin exactly 0x34 -// words after the hardware vector table indicated by mtvec (defined above). -.p2align 4 -.global __soft_vector_table -__soft_vector_table: -.word isr_irq0 -.word isr_irq1 -.word isr_irq2 -.word isr_irq3 -.word isr_irq4 -.word isr_irq5 -.word isr_irq6 -.word isr_irq7 -.word isr_irq8 -.word isr_irq9 -.word isr_irq10 -.word isr_irq11 -.word isr_irq12 -.word isr_irq13 -.word isr_irq14 -.word isr_irq15 -.word isr_irq16 -.word isr_irq17 -.word isr_irq18 -.word isr_irq19 -.word isr_irq20 -.word isr_irq21 -.word isr_irq22 -.word isr_irq23 -.word isr_irq24 -.word isr_irq25 -.word isr_irq26 -.word isr_irq27 -.word isr_irq28 -.word isr_irq29 -.word isr_irq30 -.word isr_irq31 -.word isr_irq32 -.word isr_irq33 -.word isr_irq34 -.word isr_irq35 -.word isr_irq36 -.word isr_irq37 -.word isr_irq38 -.word isr_irq39 -.word isr_irq40 -.word isr_irq41 -.word isr_irq42 -.word isr_irq43 -.word isr_irq44 -.word isr_irq45 -.word isr_irq46 -.word isr_irq47 -.word isr_irq48 -.word isr_irq49 -.word isr_irq50 -.word isr_irq51 - -// all default trap handlers do nothing, and we can check for them being set to our -// default values by seeing if they point to somewhere between __defaults_isrs_start and __default_isrs_end -.global __default_isrs_start -__default_isrs_start: - -// Declare a weak symbol for each ISR. -// By default, they will fall through to the undefined IRQ handler below (breakpoint), -// but can be overridden by C functions with correct name. - -.macro decl_isr name -.weak \name -\name: -.endm - -.macro decl_isr_bkpt name -.weak \name -\name: - ebreak -.endm - -// hardware_exception on RISC-V defines its own weak handler -#if !PICO_CRT0_NO_ISR_RISCV_MACHINE_EXCEPTION -// Breakpoint will just cause another exception and trash the exception -// state, since there is no double fault lockup on RISC-V. Instead, just -// sleep the core indefinitely, or until debugger connects. -decl_isr isr_riscv_machine_exception -#endif - -// Note the mip.mtip is also available as SIO_IRQ_MTIMECMP, and this may be a -// better option, because it plays nicely with interrupt preemption. -decl_isr_bkpt isr_riscv_machine_timer -decl_isr_bkpt isr_riscv_machine_soft_irq - -decl_isr isr_irq0 -decl_isr isr_irq1 -decl_isr isr_irq2 -decl_isr isr_irq3 -decl_isr isr_irq4 -decl_isr isr_irq5 -decl_isr isr_irq6 -decl_isr isr_irq7 -decl_isr isr_irq8 -decl_isr isr_irq9 -decl_isr isr_irq10 -decl_isr isr_irq11 -decl_isr isr_irq12 -decl_isr isr_irq13 -decl_isr isr_irq14 -decl_isr isr_irq15 -decl_isr isr_irq16 -decl_isr isr_irq17 -decl_isr isr_irq18 -decl_isr isr_irq19 -decl_isr isr_irq20 -decl_isr isr_irq21 -decl_isr isr_irq22 -decl_isr isr_irq23 -decl_isr isr_irq24 -decl_isr isr_irq25 -decl_isr isr_irq26 -decl_isr isr_irq27 -decl_isr isr_irq28 -decl_isr isr_irq29 -decl_isr isr_irq30 -decl_isr isr_irq31 -decl_isr isr_irq32 -decl_isr isr_irq33 -decl_isr isr_irq34 -decl_isr isr_irq35 -decl_isr isr_irq36 -decl_isr isr_irq37 -decl_isr isr_irq38 -decl_isr isr_irq39 -decl_isr isr_irq40 -decl_isr isr_irq41 -decl_isr isr_irq42 -decl_isr isr_irq43 -decl_isr isr_irq44 -decl_isr isr_irq45 -decl_isr isr_irq46 -decl_isr isr_irq47 -decl_isr isr_irq48 -decl_isr isr_irq49 -decl_isr isr_irq50 -decl_isr isr_irq51 - // fall through - -// All unhandled USER IRQs fall through to here. Note there is no way to get -// the "current exception" on RISC-V (as there is no such thing -- the -// hardware does not model the exception lifecycle like on Arm) so instead we -// just pass the IRQ number into the IRQ handler in a0. -.global __unhandled_user_irq -__unhandled_user_irq: -.global unhandled_user_irq_num_in_a0 -unhandled_user_irq_num_in_a0: - // The dispatch code will have left IRQ << 2 in a0 from its meinext read, - // so just need to shift it back down - srli a0, a0, 2 - ebreak - -.global __default_isrs_end -__default_isrs_end: - -// ---------------------------------------------------------------------------- - -.section .binary_info_header, "a" - -// Header must be in first 256 bytes of main image (i.e. excluding flash boot2). -// For flash builds we put it immediately after vector table; for NO_FLASH the -// vectors are at a +0x100 offset because the bootrom enters RAM images directly -// at their lowest address, so we put the header in the VTOR alignment hole. - -#if !PICO_NO_BINARY_INFO -binary_info_header: -.word BINARY_INFO_MARKER_START -.word __binary_info_start -.word __binary_info_end -.word data_cpy_table // we may need to decode pointers that are in RAM at runtime. -.word BINARY_INFO_MARKER_END -#endif - -#include "embedded_start_block.inc.S" - -// ---------------------------------------------------------------------------- - -.section .reset, "ax" - -// On flash builds, the vector table comes first in the image (conventional). -// On NO_FLASH builds, the reset handler section comes first, as the entry -// point is at offset 0 (fixed due to bootrom), and VTOR is highly-aligned. -// Image is entered in various ways: -// -// - NO_FLASH builds are entered from beginning by UF2 bootloader -// -// - Flash builds vector through the table into _reset_handler from boot2 -// -// - Either type can be entered via _entry_point by the debugger, and flash builds -// must then be sent back round the boot sequence to properly initialise flash - -// ELF entry point: -.global _entry_point -_entry_point: - -#if PICO_NO_FLASH - // Go through our own reset handler. Same path for debugger entry and - // bootloader entry. - j _reset_handler -#else - // Debugger tried to run code after loading, so SSI is in 03h-only mode. - // Go back through bootrom + boot2 to properly initialise flash. - j reenter_bootrom -#endif - -// Reset handler: -// - initialises .data -// - clears .bss -// - calls runtime_init -// - calls main -// - calls exit (which should eventually hang the processor via _exit) - -_reset_handler: -.option push -.option norelax - la gp, __global_pointer$ -.option pop - la sp, __StackTop - // Leave interrupts globally disabled for now, we will set that up later - // in runtime_init_per_core_h3_irq_registers. Still worth installing the vector table: - la a0, __vectors + 1 - csrw mtvec, a0 - - // Only core 0 should run the C runtime startup code; core 1 is normally - // sleeping in the bootrom at this point but check to be sure - csrr a0, mhartid - bnez a0, reenter_bootrom - -#if PICO_RP2350 && PICO_EMBED_XIP_SETUP && !PICO_NO_FLASH - // Execute boot2 on the core 0 stack (it also gets copied into BOOTRAM due - // to inclusion in the data copy table below) -_copy_xip_setup: - mv a2, sp - addi sp, sp, -256 - mv a0, sp - la a1, __boot2_entry_point -1: - // Iterate forward, as sequential flash access is faster - lw a3, (a1) - sw a3, (a0) - addi a0, a0, 4 - addi a1, a1, 4 - bltu a0, a2, 1b -_call_xip_setup: - jalr sp - addi sp, sp, 256 -#endif - - // In a NO_FLASH binary, don't perform .data etc copy, since it's loaded - // in-place by the SRAM load. Still need to clear .bss -#if !PICO_NO_FLASH - la a4, data_cpy_table - - // assume there is at least one entry -1: - lw a1, 0(a4) - beqz a1, 2f - lw a2, 4(a4) - lw a3, 8(a4) - addi a4, a4, 12 - jal data_cpy - j 1b -2: -#endif - - // Zero out the BSS - la a1, __bss_start__ - la a2, __bss_end__ - j bss_fill_test -bss_fill_loop: - sw zero, (a1) - addi a1, a1, 4 -bss_fill_test: - bne a1, a2, bss_fill_loop - -platform_entry: // symbol for stack traces - // Use `call` pseudo-instruction instead of a bare `jal` so that the - // linker can use longer sequences if these are out of `jal` range. Will - // still get relaxed to a `jal` if possible. - // call runtime_init_per_core_h3_irq_registers (now called in runtime_init) - call runtime_init - call main - call exit - // exit should not return. If it does, hang the core. - // (fall thru into our hang _exit impl -1: // separate label because _exit can be moved out of branch range - ebreak - j 1b - -data_cpy_loop: - lw a0, (a1) - sw a0, (a2) - addi a1, a1, 4 - addi a2, a2, 4 -data_cpy: - bltu a2, a3, data_cpy_loop - ret - -.align 2 -data_cpy_table: -#if PICO_RP2350 && PICO_EMBED_XIP_SETUP && !PICO_NO_FLASH -.word __boot2_start__ -.word BOOTRAM_BASE -.word BOOTRAM_BASE + 256 -#endif -#if PICO_COPY_TO_RAM -.word __ram_text_source__ -.word __ram_text_start__ -.word __ram_text_end__ -#endif -.word __etext -.word __data_start__ -.word __data_end__ - -.word __scratch_x_source__ -.word __scratch_x_start__ -.word __scratch_x_end__ - -.word __scratch_y_source__ -.word __scratch_y_start__ -.word __scratch_y_end__ - -.word 0 // null terminator - -// ---------------------------------------------------------------------------- -// Provide safe defaults for _exit and runtime_init -// Full implementations usually provided by platform.c - -.weak runtime_init -runtime_init: - ret - -// ---------------------------------------------------------------------------- -// If core 1 somehow gets into crt0, we need to catch it and send back to the -// sleep-and-launch code in the bootrom. Shouldn't happen (it should sleep in -// the ROM until given an entry point via the cross-core FIFOs) but it's good -// to be defensive. - -// Enter through the shared reset handler: on core 1 this should quickly reach -// the wait-for-vector code. -reenter_bootrom: - -#ifdef RASPBERRYPI_AMETHYST_FPGA - // todo remove once 64k bootrom support is not required: vvvvvvvvvvvvvvvvvvvvv - // Try jumping 32k higher and see if we get a fault :) - li a0, BOOTROM_ENTRY_OFFSET + 32 * 1024 - la a1, 1f - csrw mtvec, a1 - jr a0 - // Go here if we trapped: -.p2align 2 -1: -#endif - - li a0, BOOTROM_ENTRY_OFFSET - jr a0 - -// ---------------------------------------------------------------------------- -// IRQ register clearing - -// Enable interrupts globally, but disable all interrupt sources. -// -// This is put in the .text section as it is called again on core 1 launch. In -// COPY_TO_RAM binaries, the .reset section is always in flash, whereas .text -// is in SRAM, and we try to avoid running any code from flash after entering -// user code in a COPY_TO_RAM binary. Note because of this we don't call this -// function here in crt0 until after the flash-to-RAM copying is finished. - -.section .text -.global runtime_init_per_core_h3_irq_registers -runtime_init_per_core_h3_irq_registers: - // First clear all IRQ force array bits. Iterate over array registers 0 - // through 3 inclusive, allowing for up to 64 IRQs. Don't clear the - // enable array as earlier (non-per-core) init stages may have already - // set up IRQs. - li a0, 3 -1: - csrw RVCSR_MEIFA_OFFSET, a0 - addi a0, a0, -1 - bgez a0, 1b - // Setting the global external IRQ enable in mie prepares us to enable - // IRQs one-by-one later. Also clear the soft IRQ and timer IRQ enables: - li a0, RVCSR_MIE_MEIE_BITS - csrw mie, a0 - // Set the global IRQ: we will now take any individual interrupt that is - // pending && enabled - csrsi mstatus, RVCSR_MSTATUS_MIE_BITS - // Take this chance to clear mscratch, which is used to detect nested - // exceptions in isr_riscv_machine_exception: - csrw mscratch, zero - ret - -// ---------------------------------------------------------------------------- -// Stack/heap dummies to set size - -// Prior to SDK 1.5.1 these were `.section .stack` without the `, "a"`... Clang linker gives a warning about this, -// however setting it explicitly to `, "a"` makes GCC *now* discard the section unless it is also KEEP. This -// seems like very surprising behavior! -// -// Strictly the most correct thing to do (as .stack and .heap are unreferenced) is to mark them as "a", and also KEEP, which -// works correctly for both GCC and Clang, however doing so may break anyone who already has custom linker scripts without -// the KEEP. Therefore we will only add the "a" on Clang, but will also use KEEP to our own linker scripts. - -.macro spacer_section name -#if PICO_ASSEMBLER_IS_CLANG -.section \name, "a" -#else -.section \name -#endif -.endm - -spacer_section .stack -// align to allow for memory protection (although this alignment is pretty much ignored by linker script) -.p2align 5 - .equ StackSize, PICO_STACK_SIZE -.space StackSize - -spacer_section .heap -.p2align 2 - .equ HeapSize, PICO_HEAP_SIZE -.space HeapSize - -#include "embedded_end_block.inc.S" - diff --git a/lib/main/pico-sdk/rp2_common/pico_crt0/doc.h b/lib/main/pico-sdk/rp2_common/pico_crt0/doc.h deleted file mode 100644 index c48eb2b184..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_crt0/doc.h +++ /dev/null @@ -1,8 +0,0 @@ -/** - * \defgroup pico_crt0 pico_crt0 - * \brief Provides the default linker scripts and the program entry/exit point - */ - -// PICO_CONFIG: PICO_EMBED_XIP_SETUP, Embed custom XIP setup (boot2) in an RP2350 binary, type=bool, default=0, group=pico_base -// unused but keeps tooling happy -#define PICO_EMBED_XIP_SETUP 0 \ No newline at end of file diff --git a/lib/main/pico-sdk/rp2_common/pico_crt0/embedded_end_block.inc.S b/lib/main/pico-sdk/rp2_common/pico_crt0/embedded_end_block.inc.S deleted file mode 100644 index 9b56633f2a..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_crt0/embedded_end_block.inc.S +++ /dev/null @@ -1,17 +0,0 @@ -#if PICO_CRT0_INCLUDE_PICOBIN_END_BLOCK -.section .embedded_end_block, "a" -embedded_end_block: -.word PICOBIN_BLOCK_MARKER_START - -.byte PICOBIN_BLOCK_ITEM_2BS_IGNORED -.byte 0x1 // 1 word -.hword 0 - -.byte PICOBIN_BLOCK_ITEM_2BS_LAST -.hword (embedded_end_block_end - embedded_end_block - 16 ) / 4 // total size of all items -.byte 0 -// offset from this block to first block -.word embedded_block - embedded_end_block -.word PICOBIN_BLOCK_MARKER_END -embedded_end_block_end: -#endif diff --git a/lib/main/pico-sdk/rp2_common/pico_crt0/embedded_start_block.inc.S b/lib/main/pico-sdk/rp2_common/pico_crt0/embedded_start_block.inc.S deleted file mode 100644 index 8f1b622d4b..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_crt0/embedded_start_block.inc.S +++ /dev/null @@ -1,109 +0,0 @@ -#if !defined(PICO_CRT0_INCLUDE_PICOBIN_IMAGE_TYPE_ITEM) -// todo decide whether we want this item for RP2040 by default, probably not (there are a zilloon binaries out there without it) -#if !PICO_RP2040 -#define PICO_CRT0_INCLUDE_PICOBIN_IMAGE_TYPE_ITEM 1 -#endif -#endif - -#ifndef PICO_CRT0_INCLUDE_PICOBIN_BLOCK -#define PICO_CRT0_INCLUDE_PICOBIN_BLOCK PICO_CRT0_INCLUDE_PICOBIN_IMAGE_TYPE_ITEM -#endif - -#ifndef PICO_CRT0_INCLUDE_PICOBIN_END_BLOCK -#define PICO_CRT0_INCLUDE_PICOBIN_END_BLOCK (PICO_CRT0_INCLUDE_PICOBIN_BLOCK && !PICO_NO_FLASH) -#endif - -#if PICO_CRT0_IMAGE_TYPE_TBYB -#define CRT0_TBYB_FLAG PICOBIN_IMAGE_TYPE_EXE_TBYB_BITS -#else -#define CRT0_TBYB_FLAG 0 -#endif - -#if defined(PICO_CRT0_VERSION_MINOR) && !defined(PICO_CRT0_VERSION_MAJOR) -#define PICO_CRT0_VERSION_MAJOR 0 -#endif - -#if PICO_CRT0_INCLUDE_PICOBIN_BLOCK -.section .embedded_block, "a" -.p2align 2 -embedded_block: -.word PICOBIN_BLOCK_MARKER_START - -#if PICO_CRT0_INCLUDE_PICOBIN_IMAGE_TYPE_ITEM -// include an IMAGE_TYPE item at the start so this block is a valid IMAGE_DEF block, and can be used as a basis -// for booting the binary with a known type. -.byte PICOBIN_BLOCK_ITEM_1BS_IMAGE_TYPE -.byte 0x1 // 1 word -#ifdef PICO_CRT0_IMAGE_TYPE_ITEM_VALUE -.hword PICO_CRT0_IMAGE_TYPE_ITEM_VALUE -#elif defined(__riscv) -.hword PICOBIN_IMAGE_TYPE_IMAGE_TYPE_AS_BITS(EXE) | \ - PICOBIN_IMAGE_TYPE_EXE_CPU_AS_BITS(RISCV) | \ - PICOBIN_IMAGE_TYPE_EXE_CHIP_AS_BITS(RP2350) | \ - CRT0_TBYB_FLAG -#elif defined(PICO_RP2040) -.hword PICOBIN_IMAGE_TYPE_IMAGE_TYPE_AS_BITS(EXE) | \ - PICOBIN_IMAGE_TYPE_EXE_SECURITY_AS_BITS(NS) | \ - PICOBIN_IMAGE_TYPE_EXE_CPU_AS_BITS(ARM) | \ - PICOBIN_IMAGE_TYPE_EXE_CHIP_AS_BITS(RP2040) | \ - CRT0_TBYB_FLAG -#else -.hword PICOBIN_IMAGE_TYPE_IMAGE_TYPE_AS_BITS(EXE) | \ - PICOBIN_IMAGE_TYPE_EXE_SECURITY_AS_BITS(S) | \ - PICOBIN_IMAGE_TYPE_EXE_CPU_AS_BITS(ARM) | \ - PICOBIN_IMAGE_TYPE_EXE_CHIP_AS_BITS(RP2350) | \ - CRT0_TBYB_FLAG -#endif -#else -// if no image type, then add ignored item -.byte PICOBIN_BLOCK_ITEM_2BS_IGNORED -.byte 0x1 // 1 word -.hword 0 -#endif - -#ifdef PICO_CRT0_VERSION_MAJOR -.byte PICOBIN_BLOCK_ITEM_1BS_VERSION -.byte 0x2 // 2 words -.hword 0 -#ifdef PICO_CRT0_VERSION_MINOR -.hword PICO_CRT0_VERSION_MINOR -#else -.hword 0 -#endif -.hword PICO_CRT0_VERSION_MAJOR -#endif - -#ifdef __riscv -// On RISC-V the default entry point from bootrom is the start of the binary, but -// we have our vtable at the start, so we must include an entry point -.byte PICOBIN_BLOCK_ITEM_1BS_ENTRY_POINT -.byte 0x3 // word size to next item -.byte 0 // pad -.byte 0 // pad -.word _reset_handler -.word SRAM_END // stack pointer -#endif - -#ifndef PICO_RP2040 -#if PICO_NO_FLASH -// If no_flash bin, then include a vector table item -.byte PICOBIN_BLOCK_ITEM_1BS_VECTOR_TABLE -.byte 0x2 -.hword 0 -.word __vectors -#endif -#endif - -.byte PICOBIN_BLOCK_ITEM_2BS_LAST -.hword (embedded_block_end - embedded_block - 16 ) / 4 // total size of all -.byte 0 -#if PICO_CRT0_INCLUDE_PICOBIN_END_BLOCK -.word embedded_end_block - embedded_block -#else -// offset from this block to next block in loop (since we are a single block loop, we point back to ourselves -// so the offset is 0) -.word 0 -#endif -.word PICOBIN_BLOCK_MARKER_END -embedded_block_end: -#endif \ No newline at end of file diff --git a/lib/main/pico-sdk/rp2_common/pico_crt0/rp2040/memmap_blocked_ram.ld b/lib/main/pico-sdk/rp2_common/pico_crt0/rp2040/memmap_blocked_ram.ld deleted file mode 100644 index 6f5000566e..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_crt0/rp2040/memmap_blocked_ram.ld +++ /dev/null @@ -1,286 +0,0 @@ -/* Based on GCC ARM embedded samples. - Defines the following symbols for use by code: - __exidx_start - __exidx_end - __etext - __data_start__ - __preinit_array_start - __preinit_array_end - __init_array_start - __init_array_end - __fini_array_start - __fini_array_end - __data_end__ - __bss_start__ - __bss_end__ - __end__ - end - __HeapLimit - __StackLimit - __StackTop - __stack (== StackTop) -*/ - -MEMORY -{ - INCLUDE "pico_flash_region.ld" - RAM(rwx) : ORIGIN = 0x21000000, LENGTH = 256k - SCRATCH_X(rwx) : ORIGIN = 0x20040000, LENGTH = 4k - SCRATCH_Y(rwx) : ORIGIN = 0x20041000, LENGTH = 4k -} - -ENTRY(_entry_point) - -SECTIONS -{ - /* Second stage bootloader is prepended to the image. It must be 256 bytes big - and checksummed. It is usually built by the boot_stage2 target - in the Raspberry Pi Pico SDK - */ - - .flash_begin : { - __flash_binary_start = .; - } > FLASH - - .boot2 : { - __boot2_start__ = .; - KEEP (*(.boot2)) - __boot2_end__ = .; - } > FLASH - - ASSERT(__boot2_end__ - __boot2_start__ == 256, - "ERROR: Pico second stage bootloader must be 256 bytes in size") - - /* The second stage will always enter the image at the start of .text. - The debugger will use the ELF entry point, which is the _entry_point - symbol if present, otherwise defaults to start of .text. - This can be used to transfer control back to the bootrom on debugger - launches only, to perform proper flash setup. - */ - - .text : { - __logical_binary_start = .; - KEEP (*(.vectors)) - KEEP (*(.binary_info_header)) - __binary_info_header_end = .; - KEEP (*(.embedded_block)) - __embedded_block_end = .; - KEEP (*(.reset)) - /* TODO revisit this now memset/memcpy/float in ROM */ - /* bit of a hack right now to exclude all floating point and time critical (e.g. memset, memcpy) code from - * FLASH ... we will include any thing excluded here in .data below by default */ - *(.init) - *(EXCLUDE_FILE(*libgcc.a: *libc.a:*lib_a-mem*.o *libm.a:) .text*) - *(.fini) - /* Pull all c'tors into .text */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - /* Followed by destructors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(SORT(.preinit_array.*))) - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - *(SORT(.fini_array.*)) - *(.fini_array) - PROVIDE_HIDDEN (__fini_array_end = .); - - *(.eh_frame*) - . = ALIGN(4); - } > FLASH - - .rodata : { - *(EXCLUDE_FILE(*libgcc.a: *libc.a:*lib_a-mem*.o *libm.a:) .rodata*) - . = ALIGN(4); - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.flashdata*))) - . = ALIGN(4); - } > FLASH - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - /* Machine inspectable binary information */ - . = ALIGN(4); - __binary_info_start = .; - .binary_info : - { - KEEP(*(.binary_info.keep.*)) - *(.binary_info.*) - } > FLASH - __binary_info_end = .; - . = ALIGN(4); - - .ram_vector_table (NOLOAD): { - *(.ram_vector_table) - } > RAM - - .uninitialized_data (NOLOAD): { - . = ALIGN(4); - *(.uninitialized_data*) - } > RAM - - .data : { - __data_start__ = .; - *(vtable) - - *(.time_critical*) - - /* remaining .text and .rodata; i.e. stuff we exclude above because we want it in RAM */ - *(.text*) - . = ALIGN(4); - *(.rodata*) - . = ALIGN(4); - - *(.data*) - - . = ALIGN(4); - *(.after_data.*) - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__mutex_array_start = .); - KEEP(*(SORT(.mutex_array.*))) - KEEP(*(.mutex_array)) - PROVIDE_HIDDEN (__mutex_array_end = .); - - . = ALIGN(4); - *(.jcr) - . = ALIGN(4); - } > RAM AT> FLASH - - .tdata : { - . = ALIGN(4); - *(.tdata .tdata.* .gnu.linkonce.td.*) - /* All data end */ - __tdata_end = .; - } > RAM AT> FLASH - PROVIDE(__data_end__ = .); - - /* __etext is (for backwards compatibility) the name of the .data init source pointer (...) */ - __etext = LOADADDR(.data); - - .tbss (NOLOAD) : { - . = ALIGN(4); - __bss_start__ = .; - __tls_base = .; - *(.tbss .tbss.* .gnu.linkonce.tb.*) - *(.tcommon) - - __tls_end = .; - } > RAM - - .bss (NOLOAD) : { - . = ALIGN(4); - __tbss_end = .; - - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.bss*))) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM - - .heap (NOLOAD): - { - __end__ = .; - end = __end__; - KEEP(*(.heap*)) - } > RAM - /* historically on GCC sbrk was growing past __HeapLimit to __StackLimit, however - to be more compatible, we now set __HeapLimit explicitly to where the end of the heap is */ - __HeapLimit = ORIGIN(RAM) + LENGTH(RAM); - - /* Start and end symbols must be word-aligned */ - .scratch_x : { - __scratch_x_start__ = .; - *(.scratch_x.*) - . = ALIGN(4); - __scratch_x_end__ = .; - } > SCRATCH_X AT > FLASH - __scratch_x_source__ = LOADADDR(.scratch_x); - - .scratch_y : { - __scratch_y_start__ = .; - *(.scratch_y.*) - . = ALIGN(4); - __scratch_y_end__ = .; - } > SCRATCH_Y AT > FLASH - __scratch_y_source__ = LOADADDR(.scratch_y); - - /* .stack*_dummy section doesn't contains any symbols. It is only - * used for linker to calculate size of stack sections, and assign - * values to stack symbols later - * - * stack1 section may be empty/missing if platform_launch_core1 is not used */ - - /* by default we put core 0 stack at the end of scratch Y, so that if core 1 - * stack is not used then all of SCRATCH_X is free. - */ - .stack1_dummy (NOLOAD): - { - *(.stack1*) - } > SCRATCH_X - .stack_dummy (NOLOAD): - { - KEEP(*(.stack*)) - } > SCRATCH_Y - - .flash_end : { - KEEP(*(.embedded_end_block*)) - PROVIDE(__flash_binary_end = .); - } > FLASH - - /* stack limit is poorly named, but historically is maximum heap ptr */ - __StackLimit = ORIGIN(RAM) + LENGTH(RAM); - __StackOneTop = ORIGIN(SCRATCH_X) + LENGTH(SCRATCH_X); - __StackTop = ORIGIN(SCRATCH_Y) + LENGTH(SCRATCH_Y); - __StackOneBottom = __StackOneTop - SIZEOF(.stack1_dummy); - __StackBottom = __StackTop - SIZEOF(.stack_dummy); - PROVIDE(__stack = __StackTop); - - /* picolibc and LLVM */ - PROVIDE (__heap_start = __end__); - PROVIDE (__heap_end = __HeapLimit); - PROVIDE( __tls_align = MAX(ALIGNOF(.tdata), ALIGNOF(.tbss)) ); - PROVIDE( __tls_size_align = (__tls_size + __tls_align - 1) & ~(__tls_align - 1)); - PROVIDE( __arm32_tls_tcb_offset = MAX(8, __tls_align) ); - - /* llvm-libc */ - PROVIDE (_end = __end__); - PROVIDE (__llvm_libc_heap_limit = __HeapLimit); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed") - - ASSERT( __binary_info_header_end - __logical_binary_start <= 256, "Binary info must be in first 256 bytes of the binary") - /* todo assert on extra code */ -} - diff --git a/lib/main/pico-sdk/rp2_common/pico_crt0/rp2040/memmap_copy_to_ram.ld b/lib/main/pico-sdk/rp2_common/pico_crt0/rp2040/memmap_copy_to_ram.ld deleted file mode 100644 index 842ebfd3c5..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_crt0/rp2040/memmap_copy_to_ram.ld +++ /dev/null @@ -1,287 +0,0 @@ -/* Based on GCC ARM embedded samples. - Defines the following symbols for use by code: - __exidx_start - __exidx_end - __etext - __data_start__ - __preinit_array_start - __preinit_array_end - __init_array_start - __init_array_end - __fini_array_start - __fini_array_end - __data_end__ - __bss_start__ - __bss_end__ - __end__ - end - __HeapLimit - __StackLimit - __StackTop - __stack (== StackTop) -*/ - -MEMORY -{ - INCLUDE "pico_flash_region.ld" - RAM(rwx) : ORIGIN = 0x20000000, LENGTH = 256k - SCRATCH_X(rwx) : ORIGIN = 0x20040000, LENGTH = 4k - SCRATCH_Y(rwx) : ORIGIN = 0x20041000, LENGTH = 4k -} - -ENTRY(_entry_point) - -SECTIONS -{ - /* Second stage bootloader is prepended to the image. It must be 256 bytes big - and checksummed. It is usually built by the boot_stage2 target - in the Raspberry Pi Pico SDK - */ - - .flash_begin : { - __flash_binary_start = .; - } > FLASH - - .boot2 : { - __boot2_start__ = .; - KEEP (*(.boot2)) - __boot2_end__ = .; - } > FLASH - - ASSERT(__boot2_end__ - __boot2_start__ == 256, - "ERROR: Pico second stage bootloader must be 256 bytes in size") - - /* The second stage will always enter the image at the start of .text. - The debugger will use the ELF entry point, which is the _entry_point - symbol if present, otherwise defaults to start of .text. - This can be used to transfer control back to the bootrom on debugger - launches only, to perform proper flash setup. - */ - - .flashtext : { - __logical_binary_start = .; - KEEP (*(.vectors)) - KEEP (*(.binary_info_header)) - __binary_info_header_end = .; - KEEP (*(.embedded_block)) - __embedded_block_end = .; - KEEP (*(.reset)) - } - - .rodata : { - /* segments not marked as .flashdata are instead pulled into .data (in RAM) to avoid accidental flash accesses */ - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.flashdata*))) - . = ALIGN(4); - } > FLASH - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - /* Machine inspectable binary information */ - . = ALIGN(4); - __binary_info_start = .; - .binary_info : - { - KEEP(*(.binary_info.keep.*)) - *(.binary_info.*) - } > FLASH - __binary_info_end = .; - . = ALIGN(4); - - /* Vector table goes first in RAM, to avoid large alignment hole */ - .ram_vector_table (NOLOAD): { - *(.ram_vector_table) - } > RAM - - .uninitialized_data (NOLOAD): { - . = ALIGN(4); - *(.uninitialized_data*) - } > RAM - - .text : { - __ram_text_start__ = .; - *(.init) - *(.text*) - *(.fini) - /* Pull all c'tors into .text */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - /* Followed by destructors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.eh_frame*) - . = ALIGN(4); - __ram_text_end__ = .; - } > RAM AT> FLASH - __ram_text_source__ = LOADADDR(.text); - . = ALIGN(4); - - .data : { - __data_start__ = .; - *(vtable) - - *(.time_critical*) - - . = ALIGN(4); - *(.rodata*) - . = ALIGN(4); - - *(.data*) - - . = ALIGN(4); - *(.after_data.*) - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__mutex_array_start = .); - KEEP(*(SORT(.mutex_array.*))) - KEEP(*(.mutex_array)) - PROVIDE_HIDDEN (__mutex_array_end = .); - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(SORT(.preinit_array.*))) - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - *(SORT(.fini_array.*)) - *(.fini_array) - PROVIDE_HIDDEN (__fini_array_end = .); - - *(.jcr) - . = ALIGN(4); - } > RAM AT> FLASH - - .tdata : { - . = ALIGN(4); - *(.tdata .tdata.* .gnu.linkonce.td.*) - /* All data end */ - __tdata_end = .; - } > RAM AT> FLASH - PROVIDE(__data_end__ = .); - - /* __etext is (for backwards compatibility) the name of the .data init source pointer (...) */ - __etext = LOADADDR(.data); - - .tbss (NOLOAD) : { - . = ALIGN(4); - __bss_start__ = .; - __tls_base = .; - *(.tbss .tbss.* .gnu.linkonce.tb.*) - *(.tcommon) - - __tls_end = .; - } > RAM - - .bss : { - . = ALIGN(4); - __tbss_end = .; - - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.bss*))) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM - - .heap (NOLOAD): - { - __end__ = .; - end = __end__; - KEEP(*(.heap*)) - } > RAM - /* historically on GCC sbrk was growing past __HeapLimit to __StackLimit, however - to be more compatible, we now set __HeapLimit explicitly to where the end of the heap is */ - __HeapLimit = ORIGIN(RAM) + LENGTH(RAM); - - /* Start and end symbols must be word-aligned */ - .scratch_x : { - __scratch_x_start__ = .; - *(.scratch_x.*) - . = ALIGN(4); - __scratch_x_end__ = .; - } > SCRATCH_X AT > FLASH - __scratch_x_source__ = LOADADDR(.scratch_x); - - .scratch_y : { - __scratch_y_start__ = .; - *(.scratch_y.*) - . = ALIGN(4); - __scratch_y_end__ = .; - } > SCRATCH_Y AT > FLASH - __scratch_y_source__ = LOADADDR(.scratch_y); - - /* .stack*_dummy section doesn't contains any symbols. It is only - * used for linker to calculate size of stack sections, and assign - * values to stack symbols later - * - * stack1 section may be empty/missing if platform_launch_core1 is not used */ - - /* by default we put core 0 stack at the end of scratch Y, so that if core 1 - * stack is not used then all of SCRATCH_X is free. - */ - .stack1_dummy (NOLOAD): - { - *(.stack1*) - } > SCRATCH_X - .stack_dummy (NOLOAD): - { - KEEP(*(.stack*)) - } > SCRATCH_Y - - .flash_end : { - KEEP(*(.embedded_end_block*)) - PROVIDE(__flash_binary_end = .); - } > FLASH - - /* stack limit is poorly named, but historically is maximum heap ptr */ - __StackLimit = ORIGIN(RAM) + LENGTH(RAM); - __StackOneTop = ORIGIN(SCRATCH_X) + LENGTH(SCRATCH_X); - __StackTop = ORIGIN(SCRATCH_Y) + LENGTH(SCRATCH_Y); - __StackOneBottom = __StackOneTop - SIZEOF(.stack1_dummy); - __StackBottom = __StackTop - SIZEOF(.stack_dummy); - PROVIDE(__stack = __StackTop); - - /* picolibc and LLVM */ - PROVIDE (__heap_start = __end__); - PROVIDE (__heap_end = __HeapLimit); - PROVIDE( __tls_align = MAX(ALIGNOF(.tdata), ALIGNOF(.tbss)) ); - PROVIDE( __tls_size_align = (__tls_size + __tls_align - 1) & ~(__tls_align - 1)); - PROVIDE( __arm32_tls_tcb_offset = MAX(8, __tls_align) ); - - /* llvm-libc */ - PROVIDE (_end = __end__); - PROVIDE (__llvm_libc_heap_limit = __HeapLimit); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed") - - ASSERT( __binary_info_header_end - __logical_binary_start <= 256, "Binary info must be in first 256 bytes of the binary") - /* todo assert on extra code */ -} - diff --git a/lib/main/pico-sdk/rp2_common/pico_crt0/rp2040/memmap_default.ld b/lib/main/pico-sdk/rp2_common/pico_crt0/rp2040/memmap_default.ld deleted file mode 100644 index 51254012dc..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_crt0/rp2040/memmap_default.ld +++ /dev/null @@ -1,286 +0,0 @@ -/* Based on GCC ARM embedded samples. - Defines the following symbols for use by code: - __exidx_start - __exidx_end - __etext - __data_start__ - __preinit_array_start - __preinit_array_end - __init_array_start - __init_array_end - __fini_array_start - __fini_array_end - __data_end__ - __bss_start__ - __bss_end__ - __end__ - end - __HeapLimit - __StackLimit - __StackTop - __stack (== StackTop) -*/ - -MEMORY -{ - INCLUDE "pico_flash_region.ld" - RAM(rwx) : ORIGIN = 0x20000000, LENGTH = 256k - SCRATCH_X(rwx) : ORIGIN = 0x20040000, LENGTH = 4k - SCRATCH_Y(rwx) : ORIGIN = 0x20041000, LENGTH = 4k -} - -ENTRY(_entry_point) - -SECTIONS -{ - /* Second stage bootloader is prepended to the image. It must be 256 bytes big - and checksummed. It is usually built by the boot_stage2 target - in the Raspberry Pi Pico SDK - */ - - .flash_begin : { - __flash_binary_start = .; - } > FLASH - - .boot2 : { - __boot2_start__ = .; - KEEP (*(.boot2)) - __boot2_end__ = .; - } > FLASH - - ASSERT(__boot2_end__ - __boot2_start__ == 256, - "ERROR: Pico second stage bootloader must be 256 bytes in size") - - /* The second stage will always enter the image at the start of .text. - The debugger will use the ELF entry point, which is the _entry_point - symbol if present, otherwise defaults to start of .text. - This can be used to transfer control back to the bootrom on debugger - launches only, to perform proper flash setup. - */ - - .text : { - __logical_binary_start = .; - KEEP (*(.vectors)) - KEEP (*(.binary_info_header)) - __binary_info_header_end = .; - KEEP (*(.embedded_block)) - __embedded_block_end = .; - KEEP (*(.reset)) - /* TODO revisit this now memset/memcpy/float in ROM */ - /* bit of a hack right now to exclude all floating point and time critical (e.g. memset, memcpy) code from - * FLASH ... we will include any thing excluded here in .data below by default */ - *(.init) - *(EXCLUDE_FILE(*libgcc.a: *libc.a:*lib_a-mem*.o *libm.a:) .text*) - *(.fini) - /* Pull all c'tors into .text */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - /* Followed by destructors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(SORT(.preinit_array.*))) - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - *(SORT(.fini_array.*)) - *(.fini_array) - PROVIDE_HIDDEN (__fini_array_end = .); - - *(.eh_frame*) - . = ALIGN(4); - } > FLASH - - .rodata : { - *(EXCLUDE_FILE(*libgcc.a: *libc.a:*lib_a-mem*.o *libm.a:) .rodata*) - . = ALIGN(4); - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.flashdata*))) - . = ALIGN(4); - } > FLASH - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - /* Machine inspectable binary information */ - . = ALIGN(4); - __binary_info_start = .; - .binary_info : - { - KEEP(*(.binary_info.keep.*)) - *(.binary_info.*) - } > FLASH - __binary_info_end = .; - . = ALIGN(4); - - .ram_vector_table (NOLOAD): { - *(.ram_vector_table) - } > RAM - - .uninitialized_data (NOLOAD): { - . = ALIGN(4); - *(.uninitialized_data*) - } > RAM - - .data : { - __data_start__ = .; - *(vtable) - - *(.time_critical*) - - /* remaining .text and .rodata; i.e. stuff we exclude above because we want it in RAM */ - *(.text*) - . = ALIGN(4); - *(.rodata*) - . = ALIGN(4); - - *(.data*) - - . = ALIGN(4); - *(.after_data.*) - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__mutex_array_start = .); - KEEP(*(SORT(.mutex_array.*))) - KEEP(*(.mutex_array)) - PROVIDE_HIDDEN (__mutex_array_end = .); - - . = ALIGN(4); - *(.jcr) - . = ALIGN(4); - } > RAM AT> FLASH - - .tdata : { - . = ALIGN(4); - *(.tdata .tdata.* .gnu.linkonce.td.*) - /* All data end */ - __tdata_end = .; - } > RAM AT> FLASH - PROVIDE(__data_end__ = .); - - /* __etext is (for backwards compatibility) the name of the .data init source pointer (...) */ - __etext = LOADADDR(.data); - - .tbss (NOLOAD) : { - . = ALIGN(4); - __bss_start__ = .; - __tls_base = .; - *(.tbss .tbss.* .gnu.linkonce.tb.*) - *(.tcommon) - - __tls_end = .; - } > RAM - - .bss (NOLOAD) : { - . = ALIGN(4); - __tbss_end = .; - - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.bss*))) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM - - .heap (NOLOAD): - { - __end__ = .; - end = __end__; - KEEP(*(.heap*)) - } > RAM - /* historically on GCC sbrk was growing past __HeapLimit to __StackLimit, however - to be more compatible, we now set __HeapLimit explicitly to where the end of the heap is */ - __HeapLimit = ORIGIN(RAM) + LENGTH(RAM); - - /* Start and end symbols must be word-aligned */ - .scratch_x : { - __scratch_x_start__ = .; - *(.scratch_x.*) - . = ALIGN(4); - __scratch_x_end__ = .; - } > SCRATCH_X AT > FLASH - __scratch_x_source__ = LOADADDR(.scratch_x); - - .scratch_y : { - __scratch_y_start__ = .; - *(.scratch_y.*) - . = ALIGN(4); - __scratch_y_end__ = .; - } > SCRATCH_Y AT > FLASH - __scratch_y_source__ = LOADADDR(.scratch_y); - - /* .stack*_dummy section doesn't contains any symbols. It is only - * used for linker to calculate size of stack sections, and assign - * values to stack symbols later - * - * stack1 section may be empty/missing if platform_launch_core1 is not used */ - - /* by default we put core 0 stack at the end of scratch Y, so that if core 1 - * stack is not used then all of SCRATCH_X is free. - */ - .stack1_dummy (NOLOAD): - { - *(.stack1*) - } > SCRATCH_X - .stack_dummy (NOLOAD): - { - KEEP(*(.stack*)) - } > SCRATCH_Y - - .flash_end : { - KEEP(*(.embedded_end_block*)) - PROVIDE(__flash_binary_end = .); - } > FLASH - - /* stack limit is poorly named, but historically is maximum heap ptr */ - __StackLimit = ORIGIN(RAM) + LENGTH(RAM); - __StackOneTop = ORIGIN(SCRATCH_X) + LENGTH(SCRATCH_X); - __StackTop = ORIGIN(SCRATCH_Y) + LENGTH(SCRATCH_Y); - __StackOneBottom = __StackOneTop - SIZEOF(.stack1_dummy); - __StackBottom = __StackTop - SIZEOF(.stack_dummy); - PROVIDE(__stack = __StackTop); - - /* picolibc and LLVM */ - PROVIDE (__heap_start = __end__); - PROVIDE (__heap_end = __HeapLimit); - PROVIDE( __tls_align = MAX(ALIGNOF(.tdata), ALIGNOF(.tbss)) ); - PROVIDE( __tls_size_align = (__tls_size + __tls_align - 1) & ~(__tls_align - 1)); - PROVIDE( __arm32_tls_tcb_offset = MAX(8, __tls_align) ); - - /* llvm-libc */ - PROVIDE (_end = __end__); - PROVIDE (__llvm_libc_heap_limit = __HeapLimit); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed") - - ASSERT( __binary_info_header_end - __logical_binary_start <= 256, "Binary info must be in first 256 bytes of the binary") - /* todo assert on extra code */ -} - diff --git a/lib/main/pico-sdk/rp2_common/pico_crt0/rp2040/memmap_no_flash.ld b/lib/main/pico-sdk/rp2_common/pico_crt0/rp2040/memmap_no_flash.ld deleted file mode 100644 index dbf006a8c2..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_crt0/rp2040/memmap_no_flash.ld +++ /dev/null @@ -1,249 +0,0 @@ -/* Based on GCC ARM embedded samples. - Defines the following symbols for use by code: - __exidx_start - __exidx_end - __etext - __data_start__ - __preinit_array_start - __preinit_array_end - __init_array_start - __init_array_end - __fini_array_start - __fini_array_end - __data_end__ - __bss_start__ - __bss_end__ - __end__ - end - __HeapLimit - __StackLimit - __StackTop - __stack (== StackTop) -*/ - -MEMORY -{ - RAM(rwx) : ORIGIN = 0x20000000, LENGTH = 256k - SCRATCH_X(rwx) : ORIGIN = 0x20040000, LENGTH = 4k - SCRATCH_Y(rwx) : ORIGIN = 0x20041000, LENGTH = 4k -} - -ENTRY(_entry_point) - -SECTIONS -{ - /* Note in NO_FLASH builds the entry point for both the bootrom, and debugger - entry (ELF entry point), are *first* in the image, and the vector table - follows immediately afterward. This is because the bootrom enters RAM - binaries directly at their lowest address (preferring main RAM over XIP - cache-as-SRAM if both are used). - */ - - .text : { - __logical_binary_start = .; - __reset_start = .; - KEEP (*(.reset)) - __reset_end = .; - KEEP (*(.binary_info_header)) - __binary_info_header_end = .; - KEEP (*(.embedded_block)) - __embedded_block_end = .; - . = ALIGN(256); - KEEP (*(.vectors)) - *(.time_critical*) - *(.text*) - . = ALIGN(4); - *(.init) - *(.fini) - /* Pull all c'tors into .text */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - /* Followed by destructors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.eh_frame*) - } > RAM - - .rodata : { - . = ALIGN(4); - *(.rodata*) - . = ALIGN(4); - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.flashdata*))) - . = ALIGN(4); - } > RAM - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > RAM - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > RAM - __exidx_end = .; - - /* Machine inspectable binary information */ - . = ALIGN(4); - __binary_info_start = .; - .binary_info : - { - KEEP(*(.binary_info.keep.*)) - *(.binary_info.*) - } > RAM - __binary_info_end = .; - . = ALIGN(4); - - .data : { - __data_start__ = .; - *(vtable) - *(.data*) - - . = ALIGN(4); - *(.after_data.*) - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__mutex_array_start = .); - KEEP(*(SORT(.mutex_array.*))) - KEEP(*(.mutex_array)) - PROVIDE_HIDDEN (__mutex_array_end = .); - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(SORT(.preinit_array.*))) - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - *(SORT(.fini_array.*)) - *(.fini_array) - PROVIDE_HIDDEN (__fini_array_end = .); - - *(.jcr) - . = ALIGN(4); - } > RAM - - .tdata : { - . = ALIGN(4); - *(.tdata .tdata.* .gnu.linkonce.td.*) - /* All data end */ - __tdata_end = .; - } > RAM - PROVIDE(__data_end__ = .); - - .uninitialized_data (NOLOAD): { - . = ALIGN(4); - *(.uninitialized_data*) - } > RAM - /* __etext is (for backwards compatibility) the name of the .data init source pointer (...) */ - __etext = LOADADDR(.data); - - .tbss (NOLOAD) : { - . = ALIGN(4); - __bss_start__ = .; - __tls_base = .; - *(.tbss .tbss.* .gnu.linkonce.tb.*) - *(.tcommon) - - __tls_end = .; - } > RAM - - .bss (NOLOAD) : { - . = ALIGN(4); - __tbss_end = .; - - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.bss*))) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM - - .heap (NOLOAD): - { - __end__ = .; - end = __end__; - KEEP(*(.heap*)) - } > RAM - /* historically on GCC sbrk was growing past __HeapLimit to __StackLimit, however - to be more compatible, we now set __HeapLimit explicitly to where the end of the heap is */ - __HeapLimit = ORIGIN(RAM) + LENGTH(RAM); - - /* Start and end symbols must be word-aligned */ - .scratch_x : { - __scratch_x_start__ = .; - *(.scratch_x.*) - . = ALIGN(4); - __scratch_x_end__ = .; - } > SCRATCH_X - __scratch_x_source__ = LOADADDR(.scratch_x); - - .scratch_y : { - __scratch_y_start__ = .; - *(.scratch_y.*) - . = ALIGN(4); - __scratch_y_end__ = .; - } > SCRATCH_Y - __scratch_y_source__ = LOADADDR(.scratch_y); - - /* .stack*_dummy section doesn't contains any symbols. It is only - * used for linker to calculate size of stack sections, and assign - * values to stack symbols later - * - * stack1 section may be empty/missing if platform_launch_core1 is not used */ - - /* by default we put core 0 stack at the end of scratch Y, so that if core 1 - * stack is not used then all of SCRATCH_X is free. - */ - .stack1_dummy (NOLOAD): - { - *(.stack1*) - } > SCRATCH_X - .stack_dummy (NOLOAD): - { - KEEP(*(.stack*)) - } > SCRATCH_Y - - /* stack limit is poorly named, but historically is maximum heap ptr */ - __StackLimit = ORIGIN(RAM) + LENGTH(RAM); - __StackOneTop = ORIGIN(SCRATCH_X) + LENGTH(SCRATCH_X); - __StackTop = ORIGIN(SCRATCH_Y) + LENGTH(SCRATCH_Y); - __StackOneBottom = __StackOneTop - SIZEOF(.stack1_dummy); - __StackBottom = __StackTop - SIZEOF(.stack_dummy); - PROVIDE(__stack = __StackTop); - - /* picolibc and LLVM */ - PROVIDE (__heap_start = __end__); - PROVIDE (__heap_end = __HeapLimit); - PROVIDE( __tls_align = MAX(ALIGNOF(.tdata), ALIGNOF(.tbss)) ); - PROVIDE( __tls_size_align = (__tls_size + __tls_align - 1) & ~(__tls_align - 1)); - PROVIDE( __arm32_tls_tcb_offset = MAX(8, __tls_align) ); - - /* llvm-libc */ - PROVIDE (_end = __end__); - PROVIDE (__llvm_libc_heap_limit = __HeapLimit); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed") - - ASSERT( __binary_info_header_end - __logical_binary_start <= 256, "Binary info must be in first 256 bytes of the binary") - /* todo assert on extra code */ -} - diff --git a/lib/main/pico-sdk/rp2_common/pico_crt0/rp2350/memmap_copy_to_ram.ld b/lib/main/pico-sdk/rp2_common/pico_crt0/rp2350/memmap_copy_to_ram.ld deleted file mode 100644 index 89d63a9f06..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_crt0/rp2350/memmap_copy_to_ram.ld +++ /dev/null @@ -1,309 +0,0 @@ -/* Based on GCC ARM embedded samples. - Defines the following symbols for use by code: - __exidx_start - __exidx_end - __etext - __data_start__ - __preinit_array_start - __preinit_array_end - __init_array_start - __init_array_end - __fini_array_start - __fini_array_end - __data_end__ - __bss_start__ - __bss_end__ - __end__ - end - __HeapLimit - __StackLimit - __StackTop - __stack (== StackTop) -*/ - -MEMORY -{ - INCLUDE "pico_flash_region.ld" - RAM(rwx) : ORIGIN = 0x20000000, LENGTH = 512k - SCRATCH_X(rwx) : ORIGIN = 0x20080000, LENGTH = 4k - SCRATCH_Y(rwx) : ORIGIN = 0x20081000, LENGTH = 4k -} - -ENTRY(_entry_point) - -SECTIONS -{ - /* Second stage bootloader is prepended to the image. It must be 256 bytes big - and checksummed. It is usually built by the boot_stage2 target - in the Raspberry Pi Pico SDK - */ - - .flash_begin : { - __flash_binary_start = .; - } > FLASH - - /* The bootrom will enter the image at the point indicated in your - IMAGE_DEF, which is usually the reset handler of your vector table. - - The debugger will use the ELF entry point, which is the _entry_point - symbol, and in our case is *different from the bootrom's entry point.* - This is used to go back through the bootrom on debugger launches only, - to perform the same initial flash setup that would be performed on a - cold boot. - */ - - .flashtext : { - __logical_binary_start = .; - KEEP (*(.vectors)) - KEEP (*(.binary_info_header)) - __binary_info_header_end = .; - KEEP (*(.embedded_block)) - __embedded_block_end = .; - KEEP (*(.reset)) - . = ALIGN(4); - } > FLASH - - /* Note the boot2 section is optional, and should be discarded if there is - no reference to it *inside* the binary, as it is not called by the - bootrom. (The bootrom performs a simple best-effort XIP setup and - leaves it to the binary to do anything more sophisticated.) However - there is still a size limit of 256 bytes, to ensure the boot2 can be - stored in boot RAM. - - Really this is a "XIP setup function" -- the name boot2 is historic and - refers to its dual-purpose on RP2040, where it also handled vectoring - from the bootrom into the user image. - */ - - .boot2 : { - __boot2_start__ = .; - *(.boot2) - __boot2_end__ = .; - } > FLASH - - ASSERT(__boot2_end__ - __boot2_start__ <= 256, - "ERROR: Pico second stage bootloader must be no more than 256 bytes in size") - - .rodata : { - /* segments not marked as .flashdata are instead pulled into .data (in RAM) to avoid accidental flash accesses */ - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.flashdata*))) - . = ALIGN(4); - } > FLASH - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - /* Machine inspectable binary information */ - . = ALIGN(4); - __binary_info_start = .; - .binary_info : - { - KEEP(*(.binary_info.keep.*)) - *(.binary_info.*) - } > FLASH - __binary_info_end = .; - . = ALIGN(4); - - /* Vector table goes first in RAM, to avoid large alignment hole */ - .ram_vector_table (NOLOAD): { - *(.ram_vector_table) - } > RAM - - .uninitialized_data (NOLOAD): { - . = ALIGN(4); - *(.uninitialized_data*) - } > RAM - - .text : { - __ram_text_start__ = .; - *(.init) - *(.text*) - *(.fini) - /* Pull all c'tors into .text */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - /* Followed by destructors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.eh_frame*) - . = ALIGN(4); - __ram_text_end__ = .; - } > RAM AT> FLASH - __ram_text_source__ = LOADADDR(.text); - . = ALIGN(4); - - .data : { - __data_start__ = .; - *(vtable) - - *(.time_critical*) - - . = ALIGN(4); - *(.rodata*) - *(.srodata*) - . = ALIGN(4); - - *(.data*) - *(.sdata*) - - . = ALIGN(4); - *(.after_data.*) - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__mutex_array_start = .); - KEEP(*(SORT(.mutex_array.*))) - KEEP(*(.mutex_array)) - PROVIDE_HIDDEN (__mutex_array_end = .); - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(SORT(.preinit_array.*))) - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - *(SORT(.fini_array.*)) - *(.fini_array) - PROVIDE_HIDDEN (__fini_array_end = .); - - *(.jcr) - . = ALIGN(4); - } > RAM AT> FLASH - - .tdata : { - . = ALIGN(4); - *(.tdata .tdata.* .gnu.linkonce.td.*) - /* All data end */ - __tdata_end = .; - } > RAM AT> FLASH - PROVIDE(__data_end__ = .); - - /* __etext is (for backwards compatibility) the name of the .data init source pointer (...) */ - __etext = LOADADDR(.data); - - .tbss (NOLOAD) : { - . = ALIGN(4); - __bss_start__ = .; - __tls_base = .; - *(.tbss .tbss.* .gnu.linkonce.tb.*) - *(.tcommon) - - __tls_end = .; - } > RAM - - .bss : { - . = ALIGN(4); - __tbss_end = .; - - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.bss*))) - *(COMMON) - PROVIDE(__global_pointer$ = . + 2K); - *(.sbss*) - . = ALIGN(4); - __bss_end__ = .; - } > RAM - - .heap (NOLOAD): - { - __end__ = .; - end = __end__; - KEEP(*(.heap*)) - } > RAM - /* historically on GCC sbrk was growing past __HeapLimit to __StackLimit, however - to be more compatible, we now set __HeapLimit explicitly to where the end of the heap is */ - __HeapLimit = ORIGIN(RAM) + LENGTH(RAM); - - /* Start and end symbols must be word-aligned */ - .scratch_x : { - __scratch_x_start__ = .; - *(.scratch_x.*) - . = ALIGN(4); - __scratch_x_end__ = .; - } > SCRATCH_X AT > FLASH - __scratch_x_source__ = LOADADDR(.scratch_x); - - .scratch_y : { - __scratch_y_start__ = .; - *(.scratch_y.*) - . = ALIGN(4); - __scratch_y_end__ = .; - } > SCRATCH_Y AT > FLASH - __scratch_y_source__ = LOADADDR(.scratch_y); - - /* .stack*_dummy section doesn't contains any symbols. It is only - * used for linker to calculate size of stack sections, and assign - * values to stack symbols later - * - * stack1 section may be empty/missing if platform_launch_core1 is not used */ - - /* by default we put core 0 stack at the end of scratch Y, so that if core 1 - * stack is not used then all of SCRATCH_X is free. - */ - .stack1_dummy (NOLOAD): - { - *(.stack1*) - } > SCRATCH_X - .stack_dummy (NOLOAD): - { - KEEP(*(.stack*)) - } > SCRATCH_Y - - .flash_end : { - KEEP(*(.embedded_end_block*)) - PROVIDE(__flash_binary_end = .); - } > FLASH =0xaa - - /* stack limit is poorly named, but historically is maximum heap ptr */ - __StackLimit = ORIGIN(RAM) + LENGTH(RAM); - __StackOneTop = ORIGIN(SCRATCH_X) + LENGTH(SCRATCH_X); - __StackTop = ORIGIN(SCRATCH_Y) + LENGTH(SCRATCH_Y); - __StackOneBottom = __StackOneTop - SIZEOF(.stack1_dummy); - __StackBottom = __StackTop - SIZEOF(.stack_dummy); - PROVIDE(__stack = __StackTop); - - /* picolibc and LLVM */ - PROVIDE (__heap_start = __end__); - PROVIDE (__heap_end = __HeapLimit); - PROVIDE( __tls_align = MAX(ALIGNOF(.tdata), ALIGNOF(.tbss)) ); - PROVIDE( __tls_size_align = (__tls_size + __tls_align - 1) & ~(__tls_align - 1)); - PROVIDE( __arm32_tls_tcb_offset = MAX(8, __tls_align) ); - - /* llvm-libc */ - PROVIDE (_end = __end__); - PROVIDE (__llvm_libc_heap_limit = __HeapLimit); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed") - - ASSERT( __binary_info_header_end - __logical_binary_start <= 1024, "Binary info must be in first 1024 bytes of the binary") - ASSERT( __embedded_block_end - __logical_binary_start <= 4096, "Embedded block must be in first 4096 bytes of the binary") - - /* todo assert on extra code */ -} - diff --git a/lib/main/pico-sdk/rp2_common/pico_crt0/rp2350/memmap_default.ld b/lib/main/pico-sdk/rp2_common/pico_crt0/rp2350/memmap_default.ld deleted file mode 100644 index bce316d143..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_crt0/rp2350/memmap_default.ld +++ /dev/null @@ -1,302 +0,0 @@ -/* Based on GCC ARM embedded samples. - Defines the following symbols for use by code: - __exidx_start - __exidx_end - __etext - __data_start__ - __preinit_array_start - __preinit_array_end - __init_array_start - __init_array_end - __fini_array_start - __fini_array_end - __data_end__ - __bss_start__ - __bss_end__ - __end__ - end - __HeapLimit - __StackLimit - __StackTop - __stack (== StackTop) -*/ - -MEMORY -{ - INCLUDE "pico_flash_region.ld" - RAM(rwx) : ORIGIN = 0x20000000, LENGTH = 512k - SCRATCH_X(rwx) : ORIGIN = 0x20080000, LENGTH = 4k - SCRATCH_Y(rwx) : ORIGIN = 0x20081000, LENGTH = 4k -} - -ENTRY(_entry_point) - -SECTIONS -{ - .flash_begin : { - __flash_binary_start = .; - } > FLASH - - /* The bootrom will enter the image at the point indicated in your - IMAGE_DEF, which is usually the reset handler of your vector table. - - The debugger will use the ELF entry point, which is the _entry_point - symbol, and in our case is *different from the bootrom's entry point.* - This is used to go back through the bootrom on debugger launches only, - to perform the same initial flash setup that would be performed on a - cold boot. - */ - - .text : { - __logical_binary_start = .; - KEEP (*(.vectors)) - KEEP (*(.binary_info_header)) - __binary_info_header_end = .; - KEEP (*(.embedded_block)) - __embedded_block_end = .; - KEEP (*(.reset)) - /* TODO revisit this now memset/memcpy/float in ROM */ - /* bit of a hack right now to exclude all floating point and time critical (e.g. memset, memcpy) code from - * FLASH ... we will include any thing excluded here in .data below by default */ - *(.init) - *libgcc.a:cmse_nonsecure_call.o - *(EXCLUDE_FILE(*libgcc.a: *libc.a:*lib_a-mem*.o *libm.a:) .text*) - *(.fini) - /* Pull all c'tors into .text */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - /* Followed by destructors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(SORT(.preinit_array.*))) - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - *(SORT(.fini_array.*)) - *(.fini_array) - PROVIDE_HIDDEN (__fini_array_end = .); - - *(.eh_frame*) - . = ALIGN(4); - } > FLASH - - /* Note the boot2 section is optional, and should be discarded if there is - no reference to it *inside* the binary, as it is not called by the - bootrom. (The bootrom performs a simple best-effort XIP setup and - leaves it to the binary to do anything more sophisticated.) However - there is still a size limit of 256 bytes, to ensure the boot2 can be - stored in boot RAM. - - Really this is a "XIP setup function" -- the name boot2 is historic and - refers to its dual-purpose on RP2040, where it also handled vectoring - from the bootrom into the user image. - */ - - .boot2 : { - __boot2_start__ = .; - *(.boot2) - __boot2_end__ = .; - } > FLASH - - ASSERT(__boot2_end__ - __boot2_start__ <= 256, - "ERROR: Pico second stage bootloader must be no more than 256 bytes in size") - - .rodata : { - *(EXCLUDE_FILE(*libgcc.a: *libc.a:*lib_a-mem*.o *libm.a:) .rodata*) - *(.srodata*) - . = ALIGN(4); - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.flashdata*))) - . = ALIGN(4); - } > FLASH - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - /* Machine inspectable binary information */ - . = ALIGN(4); - __binary_info_start = .; - .binary_info : - { - KEEP(*(.binary_info.keep.*)) - *(.binary_info.*) - } > FLASH - __binary_info_end = .; - . = ALIGN(4); - - .ram_vector_table (NOLOAD): { - *(.ram_vector_table) - } > RAM - - .uninitialized_data (NOLOAD): { - . = ALIGN(4); - *(.uninitialized_data*) - } > RAM - - .data : { - __data_start__ = .; - *(vtable) - - *(.time_critical*) - - /* remaining .text and .rodata; i.e. stuff we exclude above because we want it in RAM */ - *(.text*) - . = ALIGN(4); - *(.rodata*) - . = ALIGN(4); - - *(.data*) - *(.sdata*) - - . = ALIGN(4); - *(.after_data.*) - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__mutex_array_start = .); - KEEP(*(SORT(.mutex_array.*))) - KEEP(*(.mutex_array)) - PROVIDE_HIDDEN (__mutex_array_end = .); - - *(.jcr) - . = ALIGN(4); - } > RAM AT> FLASH - - .tdata : { - . = ALIGN(4); - *(.tdata .tdata.* .gnu.linkonce.td.*) - /* All data end */ - __tdata_end = .; - } > RAM AT> FLASH - PROVIDE(__data_end__ = .); - - /* __etext is (for backwards compatibility) the name of the .data init source pointer (...) */ - __etext = LOADADDR(.data); - - .tbss (NOLOAD) : { - . = ALIGN(4); - __bss_start__ = .; - __tls_base = .; - *(.tbss .tbss.* .gnu.linkonce.tb.*) - *(.tcommon) - - __tls_end = .; - } > RAM - - .bss (NOLOAD) : { - . = ALIGN(4); - __tbss_end = .; - - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.bss*))) - *(COMMON) - PROVIDE(__global_pointer$ = . + 2K); - *(.sbss*) - . = ALIGN(4); - __bss_end__ = .; - } > RAM - - .heap (NOLOAD): - { - __end__ = .; - end = __end__; - KEEP(*(.heap*)) - } > RAM - /* historically on GCC sbrk was growing past __HeapLimit to __StackLimit, however - to be more compatible, we now set __HeapLimit explicitly to where the end of the heap is */ - __HeapLimit = ORIGIN(RAM) + LENGTH(RAM); - - /* Start and end symbols must be word-aligned */ - .scratch_x : { - __scratch_x_start__ = .; - *(.scratch_x.*) - . = ALIGN(4); - __scratch_x_end__ = .; - } > SCRATCH_X AT > FLASH - __scratch_x_source__ = LOADADDR(.scratch_x); - - .scratch_y : { - __scratch_y_start__ = .; - *(.scratch_y.*) - . = ALIGN(4); - __scratch_y_end__ = .; - } > SCRATCH_Y AT > FLASH - __scratch_y_source__ = LOADADDR(.scratch_y); - - /* .stack*_dummy section doesn't contains any symbols. It is only - * used for linker to calculate size of stack sections, and assign - * values to stack symbols later - * - * stack1 section may be empty/missing if platform_launch_core1 is not used */ - - /* by default we put core 0 stack at the end of scratch Y, so that if core 1 - * stack is not used then all of SCRATCH_X is free. - */ - .stack1_dummy (NOLOAD): - { - *(.stack1*) - } > SCRATCH_X - .stack_dummy (NOLOAD): - { - KEEP(*(.stack*)) - } > SCRATCH_Y - - .flash_end : { - KEEP(*(.embedded_end_block*)) - PROVIDE(__flash_binary_end = .); - } > FLASH =0xaa - - /* stack limit is poorly named, but historically is maximum heap ptr */ - __StackLimit = ORIGIN(RAM) + LENGTH(RAM); - __StackOneTop = ORIGIN(SCRATCH_X) + LENGTH(SCRATCH_X); - __StackTop = ORIGIN(SCRATCH_Y) + LENGTH(SCRATCH_Y); - __StackOneBottom = __StackOneTop - SIZEOF(.stack1_dummy); - __StackBottom = __StackTop - SIZEOF(.stack_dummy); - PROVIDE(__stack = __StackTop); - - /* picolibc and LLVM */ - PROVIDE (__heap_start = __end__); - PROVIDE (__heap_end = __HeapLimit); - PROVIDE( __tls_align = MAX(ALIGNOF(.tdata), ALIGNOF(.tbss)) ); - PROVIDE( __tls_size_align = (__tls_size + __tls_align - 1) & ~(__tls_align - 1)); - PROVIDE( __arm32_tls_tcb_offset = MAX(8, __tls_align) ); - - /* llvm-libc */ - PROVIDE (_end = __end__); - PROVIDE (__llvm_libc_heap_limit = __HeapLimit); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed") - - ASSERT( __binary_info_header_end - __logical_binary_start <= 1024, "Binary info must be in first 1024 bytes of the binary") - ASSERT( __embedded_block_end - __logical_binary_start <= 4096, "Embedded block must be in first 4096 bytes of the binary") - - /* todo assert on extra code */ -} - diff --git a/lib/main/pico-sdk/rp2_common/pico_crt0/rp2350/memmap_no_flash.ld b/lib/main/pico-sdk/rp2_common/pico_crt0/rp2350/memmap_no_flash.ld deleted file mode 100644 index 98088cdfc1..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_crt0/rp2350/memmap_no_flash.ld +++ /dev/null @@ -1,256 +0,0 @@ -/* Based on GCC ARM embedded samples. - Defines the following symbols for use by code: - __exidx_start - __exidx_end - __etext - __data_start__ - __preinit_array_start - __preinit_array_end - __init_array_start - __init_array_end - __fini_array_start - __fini_array_end - __data_end__ - __bss_start__ - __bss_end__ - __end__ - end - __HeapLimit - __StackLimit - __StackTop - __stack (== StackTop) -*/ - -MEMORY -{ - RAM(rwx) : ORIGIN = 0x20000000, LENGTH = 512k - SCRATCH_X(rwx) : ORIGIN = 0x20080000, LENGTH = 4k - SCRATCH_Y(rwx) : ORIGIN = 0x20081000, LENGTH = 4k -} - -ENTRY(_entry_point) - -SECTIONS -{ - /* Note unlike RP2040, we start the image with a vector table even for - NO_FLASH builds. On Arm, the bootrom expects a VT at the start of the - image by default; on RISC-V, the default is to enter the image at its - lowest address, so an IMAGEDEF item is required to specify the - nondefault entry point. */ - - .text : { - __logical_binary_start = .; - /* Vectors require 512-byte alignment on v8-M when >48 IRQs are used, - so we would waste RAM if the vector table were not at the - start. */ - KEEP (*(.vectors)) - KEEP (*(.binary_info_header)) - __binary_info_header_end = .; - KEEP (*(.embedded_block)) - __embedded_block_end = .; - __reset_start = .; - KEEP (*(.reset)) - __reset_end = .; - *(.time_critical*) - *(.text*) - . = ALIGN(4); - *(.init) - *(.fini) - /* Pull all c'tors into .text */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - /* Followed by destructors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.eh_frame*) - } > RAM - - .rodata : { - . = ALIGN(4); - *(.rodata*) - *(.srodata*) - . = ALIGN(4); - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.flashdata*))) - . = ALIGN(4); - } > RAM - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > RAM - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > RAM - __exidx_end = .; - - /* Machine inspectable binary information */ - . = ALIGN(4); - __binary_info_start = .; - .binary_info : - { - KEEP(*(.binary_info.keep.*)) - *(.binary_info.*) - } > RAM - __binary_info_end = .; - . = ALIGN(4); - - .data : { - __data_start__ = .; - *(vtable) - *(.data*) - *(.sdata*) - - . = ALIGN(4); - *(.after_data.*) - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__mutex_array_start = .); - KEEP(*(SORT(.mutex_array.*))) - KEEP(*(.mutex_array)) - PROVIDE_HIDDEN (__mutex_array_end = .); - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(SORT(.preinit_array.*))) - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - *(SORT(.fini_array.*)) - *(.fini_array) - PROVIDE_HIDDEN (__fini_array_end = .); - - *(.jcr) - . = ALIGN(4); - } > RAM - - .tdata : { - . = ALIGN(4); - *(.tdata .tdata.* .gnu.linkonce.td.*) - /* All data end */ - __tdata_end = .; - } > RAM - PROVIDE(__data_end__ = .); - - .uninitialized_data (NOLOAD): { - . = ALIGN(4); - *(.uninitialized_data*) - } > RAM - /* __etext is (for backwards compatibility) the name of the .data init source pointer (...) */ - __etext = LOADADDR(.data); - - .tbss (NOLOAD) : { - . = ALIGN(4); - __bss_start__ = .; - __tls_base = .; - *(.tbss .tbss.* .gnu.linkonce.tb.*) - *(.tcommon) - - __tls_end = .; - } > RAM - - .bss (NOLOAD) : { - . = ALIGN(4); - __tbss_end = .; - - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.bss*))) - *(COMMON) - PROVIDE(__global_pointer$ = . + 2K); - *(.sbss*) - . = ALIGN(4); - __bss_end__ = .; - } > RAM - - .heap (NOLOAD): - { - __end__ = .; - end = __end__; - KEEP(*(.heap*)) - } > RAM - /* historically on GCC sbrk was growing past __HeapLimit to __StackLimit, however - to be more compatible, we now set __HeapLimit explicitly to where the end of the heap is */ - __HeapLimit = ORIGIN(RAM) + LENGTH(RAM); - - /* Start and end symbols must be word-aligned */ - .scratch_x : { - __scratch_x_start__ = .; - *(.scratch_x.*) - . = ALIGN(4); - __scratch_x_end__ = .; - } > SCRATCH_X - __scratch_x_source__ = LOADADDR(.scratch_x); - - .scratch_y : { - __scratch_y_start__ = .; - *(.scratch_y.*) - . = ALIGN(4); - __scratch_y_end__ = .; - } > SCRATCH_Y - __scratch_y_source__ = LOADADDR(.scratch_y); - - /* .stack*_dummy section doesn't contains any symbols. It is only - * used for linker to calculate size of stack sections, and assign - * values to stack symbols later - * - * stack1 section may be empty/missing if platform_launch_core1 is not used */ - - /* by default we put core 0 stack at the end of scratch Y, so that if core 1 - * stack is not used then all of SCRATCH_X is free. - */ - .stack1_dummy (NOLOAD): - { - *(.stack1*) - } > SCRATCH_X - .stack_dummy (NOLOAD): - { - KEEP(*(.stack*)) - } > SCRATCH_Y - - /* stack limit is poorly named, but historically is maximum heap ptr */ - __StackLimit = ORIGIN(RAM) + LENGTH(RAM); - __StackOneTop = ORIGIN(SCRATCH_X) + LENGTH(SCRATCH_X); - __StackTop = ORIGIN(SCRATCH_Y) + LENGTH(SCRATCH_Y); - __StackOneBottom = __StackOneTop - SIZEOF(.stack1_dummy); - __StackBottom = __StackTop - SIZEOF(.stack_dummy); - PROVIDE(__stack = __StackTop); - - /* picolibc and LLVM */ - PROVIDE (__heap_start = __end__); - PROVIDE (__heap_end = __HeapLimit); - PROVIDE( __tls_align = MAX(ALIGNOF(.tdata), ALIGNOF(.tbss)) ); - PROVIDE( __tls_size_align = (__tls_size + __tls_align - 1) & ~(__tls_align - 1)); - PROVIDE( __arm32_tls_tcb_offset = MAX(8, __tls_align) ); - - /* llvm-libc */ - PROVIDE (_end = __end__); - PROVIDE (__llvm_libc_heap_limit = __HeapLimit); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed") - - ASSERT( __binary_info_header_end - __logical_binary_start <= 1024, "Binary info must be in first 1024 bytes of the binary") - ASSERT( __embedded_block_end - __logical_binary_start <= 4096, "Embedded block must be in first 4096 bytes of the binary") - - /* todo assert on extra code */ -} - diff --git a/lib/main/pico-sdk/rp2_common/pico_cxx_options/doc.h b/lib/main/pico-sdk/rp2_common/pico_cxx_options/doc.h deleted file mode 100644 index 5d84e22549..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_cxx_options/doc.h +++ /dev/null @@ -1,4 +0,0 @@ -/** - * \defgroup pico_cxx_options pico_cxx_options - * \brief non-code library controlling C++ related compile options - */ diff --git a/lib/main/pico-sdk/rp2_common/pico_cxx_options/new_delete.cpp b/lib/main/pico-sdk/rp2_common/pico_cxx_options/new_delete.cpp deleted file mode 100644 index 19adddab31..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_cxx_options/new_delete.cpp +++ /dev/null @@ -1,36 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#if !PICO_CXX_ENABLE_EXCEPTIONS -// Override the standard allocators to use regular malloc/free - -#if !PICO_CXX_DISABLE_ALLOCATION_OVERRIDES // Let user override -#include -#include "pico.h" - -void *operator new(std::size_t n) { - return std::malloc(n); -} - -void *operator new[](std::size_t n) { - return std::malloc(n); -} - -void operator delete(void *p) { std::free(p); } - -void operator delete[](void *p) noexcept { std::free(p); } - -#if __cpp_sized_deallocation - -void operator delete(void *p, __unused std::size_t n) noexcept { std::free(p); } - -void operator delete[](void *p, __unused std::size_t n) noexcept { std::free(p); } - -#endif - -#endif - -#endif diff --git a/lib/main/pico-sdk/rp2_common/pico_cyw43_arch/cyw43_arch.c b/lib/main/pico-sdk/rp2_common/pico_cyw43_arch/cyw43_arch.c deleted file mode 100644 index 024e3aecd5..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_cyw43_arch/cyw43_arch.c +++ /dev/null @@ -1,188 +0,0 @@ -/* - * Copyright (c) 2022 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include -#include - -#include "pico/unique_id.h" -#include "cyw43.h" -#include "pico/cyw43_arch.h" -#include "cyw43_ll.h" -#include "cyw43_stats.h" - -#if PICO_CYW43_ARCH_DEBUG_ENABLED -#define CYW43_ARCH_DEBUG(...) printf(__VA_ARGS__) -#else -#define CYW43_ARCH_DEBUG(...) ((void)0) -#endif - -static uint32_t country_code = PICO_CYW43_ARCH_DEFAULT_COUNTRY_CODE; - -static async_context_t *async_context; - -void cyw43_arch_set_async_context(async_context_t *context) { - async_context = context; -} - -void cyw43_arch_enable_sta_mode(void) { - assert(cyw43_is_initialized(&cyw43_state)); - cyw43_wifi_set_up(&cyw43_state, CYW43_ITF_STA, true, cyw43_arch_get_country_code()); -} - -void cyw43_arch_disable_sta_mode(void) { - assert(cyw43_is_initialized(&cyw43_state)); - if (cyw43_state.itf_state & (1 << CYW43_ITF_STA)) { - cyw43_cb_tcpip_deinit(&cyw43_state, CYW43_ITF_STA); - cyw43_state.itf_state &= ~(1 << CYW43_ITF_STA); - } - if (cyw43_state.wifi_join_state) { - cyw43_wifi_leave(&cyw43_state, CYW43_ITF_STA); - } -} - -void cyw43_arch_enable_ap_mode(const char *ssid, const char *password, uint32_t auth) { - assert(cyw43_is_initialized(&cyw43_state)); - cyw43_wifi_ap_set_ssid(&cyw43_state, strlen(ssid), (const uint8_t *) ssid); - if (password) { - cyw43_wifi_ap_set_password(&cyw43_state, strlen(password), (const uint8_t *) password); - cyw43_wifi_ap_set_auth(&cyw43_state, auth); - } else { - cyw43_wifi_ap_set_auth(&cyw43_state, CYW43_AUTH_OPEN); - } - cyw43_wifi_set_up(&cyw43_state, CYW43_ITF_AP, true, cyw43_arch_get_country_code()); -} - -void cyw43_arch_disable_ap_mode(void) { - assert(cyw43_is_initialized(&cyw43_state)); - cyw43_wifi_set_up(&cyw43_state, CYW43_ITF_AP, false, cyw43_arch_get_country_code()); - cyw43_state.itf_state &= ~(1 << CYW43_ITF_AP); -} - -#if PICO_CYW43_ARCH_DEBUG_ENABLED -// Return a string for the wireless state -static const char* cyw43_tcpip_link_status_name(int status) -{ - switch (status) { - case CYW43_LINK_DOWN: - return "link down"; - case CYW43_LINK_JOIN: - return "joining"; - case CYW43_LINK_NOIP: - return "no ip"; - case CYW43_LINK_UP: - return "link up"; - case CYW43_LINK_FAIL: - return "link fail"; - case CYW43_LINK_NONET: - return "network fail"; - case CYW43_LINK_BADAUTH: - return "bad auth"; - } - return "unknown"; -} -#endif - - -int cyw43_arch_wifi_connect_bssid_async(const char *ssid, const uint8_t *bssid, const char *pw, uint32_t auth) { - if (!pw) auth = CYW43_AUTH_OPEN; - // Connect to wireless - return cyw43_wifi_join(&cyw43_state, strlen(ssid), (const uint8_t *)ssid, pw ? strlen(pw) : 0, (const uint8_t *)pw, auth, bssid, CYW43_CHANNEL_NONE); -} - -int cyw43_arch_wifi_connect_async(const char *ssid, const char *pw, uint32_t auth) { - return cyw43_arch_wifi_connect_bssid_async(ssid, NULL, pw, auth); -} - -static int cyw43_arch_wifi_connect_bssid_until(const char *ssid, const uint8_t *bssid, const char *pw, uint32_t auth, absolute_time_t until) { - int err = cyw43_arch_wifi_connect_bssid_async(ssid, bssid, pw, auth); - if (err) return err; - - int status = CYW43_LINK_UP + 1; - while(status >= 0 && status != CYW43_LINK_UP) { - int new_status = cyw43_tcpip_link_status(&cyw43_state, CYW43_ITF_STA); - // If there was no network, keep trying - if (new_status == CYW43_LINK_NONET) { - new_status = CYW43_LINK_JOIN; - err = cyw43_arch_wifi_connect_bssid_async(ssid, bssid, pw, auth); - if (err) return err; - } - if (new_status != status) { - status = new_status; - CYW43_ARCH_DEBUG("connect status: %s\n", cyw43_tcpip_link_status_name(status)); - } - if (time_reached(until)) { - return PICO_ERROR_TIMEOUT; - } - // Do polling - cyw43_arch_poll(); - cyw43_arch_wait_for_work_until(until); - } - // Turn status into a pico_error_codes, CYW43_LINK_NONET shouldn't happen as we fail with PICO_ERROR_TIMEOUT instead - assert(status == CYW43_LINK_UP || status == CYW43_LINK_BADAUTH || status == CYW43_LINK_FAIL); - if (status == CYW43_LINK_UP) { - return PICO_OK; // success - } else if (status == CYW43_LINK_BADAUTH) { - return PICO_ERROR_BADAUTH; - } else { - return PICO_ERROR_CONNECT_FAILED; - } -} - -// Connect to wireless, return with success when an IP address has been assigned -static int cyw43_arch_wifi_connect_until(const char *ssid, const char *pw, uint32_t auth, absolute_time_t until) { - return cyw43_arch_wifi_connect_bssid_until(ssid, NULL, pw, auth, until); -} - -int cyw43_arch_wifi_connect_blocking(const char *ssid, const char *pw, uint32_t auth) { - return cyw43_arch_wifi_connect_until(ssid, pw, auth, at_the_end_of_time); -} - -int cyw43_arch_wifi_connect_bssid_blocking(const char *ssid, const uint8_t *bssid, const char *pw, uint32_t auth) { - return cyw43_arch_wifi_connect_bssid_until(ssid, bssid, pw, auth, at_the_end_of_time); -} - -int cyw43_arch_wifi_connect_timeout_ms(const char *ssid, const char *pw, uint32_t auth, uint32_t timeout_ms) { - return cyw43_arch_wifi_connect_until(ssid, pw, auth, make_timeout_time_ms(timeout_ms)); -} - -int cyw43_arch_wifi_connect_bssid_timeout_ms(const char *ssid, const uint8_t *bssid, const char *pw, uint32_t auth, uint32_t timeout_ms) { - return cyw43_arch_wifi_connect_bssid_until(ssid, bssid, pw, auth, make_timeout_time_ms(timeout_ms)); -} - -uint32_t cyw43_arch_get_country_code(void) { - return country_code; -} - -int cyw43_arch_init_with_country(uint32_t country) { - country_code = country; - return cyw43_arch_init(); -} - -void cyw43_arch_gpio_put(uint wl_gpio, bool value) { - invalid_params_if(PICO_CYW43_ARCH, wl_gpio >= CYW43_WL_GPIO_COUNT); - cyw43_gpio_set(&cyw43_state, (int)wl_gpio, value); -} - -bool cyw43_arch_gpio_get(uint wl_gpio) { - invalid_params_if(PICO_CYW43_ARCH, wl_gpio >= CYW43_WL_GPIO_COUNT); - bool value = false; - cyw43_gpio_get(&cyw43_state, (int)wl_gpio, &value); - return value; -} - -async_context_t *cyw43_arch_async_context(void) { - return async_context; -} - -void cyw43_arch_poll(void) -{ - async_context_poll(async_context); -} - -void cyw43_arch_wait_for_work_until(absolute_time_t until) { - async_context_wait_for_work_until(async_context, until); -} diff --git a/lib/main/pico-sdk/rp2_common/pico_cyw43_arch/cyw43_arch_freertos.c b/lib/main/pico-sdk/rp2_common/pico_cyw43_arch/cyw43_arch_freertos.c deleted file mode 100644 index 93f73ad5d3..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_cyw43_arch/cyw43_arch_freertos.c +++ /dev/null @@ -1,84 +0,0 @@ -/* - * Copyright (c) 2022 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#if PICO_CYW43_ARCH_FREERTOS - -#include "pico/cyw43_arch.h" -#include "pico/cyw43_driver.h" -#include "pico/async_context_freertos.h" - -#if CYW43_LWIP -#include "pico/lwip_freertos.h" -#include -#endif - -#if CYW43_ENABLE_BLUETOOTH -#include "pico/btstack_cyw43.h" -#endif - -#if NO_SYS -#error example_cyw43_arch_freetos_sys requires NO_SYS=0 -#endif - -static async_context_freertos_t cyw43_async_context_freertos; - -async_context_t *cyw43_arch_init_default_async_context(void) { - async_context_freertos_config_t config = async_context_freertos_default_config(); -#ifdef CYW43_TASK_PRIORITY - config.task_priority = CYW43_TASK_PRIORITY; -#endif -#ifdef CYW43_TASK_STACK_SIZE - config.task_stack_size = CYW43_TASK_STACK_SIZE; -#endif - if (async_context_freertos_init(&cyw43_async_context_freertos, &config)) - return &cyw43_async_context_freertos.core; - return NULL; -} - -int cyw43_arch_init(void) { - async_context_t *context = cyw43_arch_async_context(); - if (!context) { - context = cyw43_arch_init_default_async_context(); - if (!context) return PICO_ERROR_GENERIC; - cyw43_arch_set_async_context(context); - } - bool ok = cyw43_driver_init(context); -#if CYW43_LWIP - ok &= lwip_freertos_init(context); -#endif -#if CYW43_ENABLE_BLUETOOTH - ok &= btstack_cyw43_init(context); -#endif - if (!ok) { - cyw43_arch_deinit(); - return PICO_ERROR_GENERIC; - } else { - return 0; - } -} - -void cyw43_arch_deinit(void) { - async_context_t *context = cyw43_arch_async_context(); -#if CYW43_ENABLE_BLUETOOTH - btstack_cyw43_deinit(context); -#endif - // there is a bit of a circular dependency here between lwIP and cyw43_driver. We - // shut down cyw43_driver first as it has IRQs calling back into lwIP. Also lwIP itself - // does not actually get shut down. - // todo add a "pause" method to async_context if we need to provide some atomicity (we - // don't want to take the lock as these methods may invoke execute_sync() - cyw43_driver_deinit(context); -#if CYW43_LWIP - lwip_freertos_deinit(context); -#endif - // if it is our context, then we de-init it. - if (context == &cyw43_async_context_freertos.core) { - async_context_deinit(context); - cyw43_arch_set_async_context(NULL); - } -} - -#endif \ No newline at end of file diff --git a/lib/main/pico-sdk/rp2_common/pico_cyw43_arch/cyw43_arch_poll.c b/lib/main/pico-sdk/rp2_common/pico_cyw43_arch/cyw43_arch_poll.c deleted file mode 100644 index e885985e22..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_cyw43_arch/cyw43_arch_poll.c +++ /dev/null @@ -1,76 +0,0 @@ -/* - * Copyright (c) 2022 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#if PICO_CYW43_ARCH_POLL - -#include "pico/cyw43_arch.h" -#include "pico/cyw43_driver.h" - -#include "pico/async_context_poll.h" -#if CYW43_LWIP -#include "pico/lwip_nosys.h" -#endif - -#if CYW43_ENABLE_BLUETOOTH -#include "pico/btstack_cyw43.h" -#endif - -#if CYW43_LWIP && !NO_SYS -#error PICO_CYW43_ARCH_POLL requires lwIP NO_SYS=1 -#endif - -static async_context_poll_t cyw43_async_context_poll; - -async_context_t *cyw43_arch_init_default_async_context(void) { - if (async_context_poll_init_with_defaults(&cyw43_async_context_poll)) - return &cyw43_async_context_poll.core; - return NULL; -} - -int cyw43_arch_init(void) { - async_context_t *context = cyw43_arch_async_context(); - if (!context) { - context = cyw43_arch_init_default_async_context(); - if (!context) return PICO_ERROR_GENERIC; - cyw43_arch_set_async_context(context); - } - bool ok = cyw43_driver_init(context); -#if CYW43_LWIP - ok &= lwip_nosys_init(context); -#endif -#if CYW43_ENABLE_BLUETOOTH - ok &= btstack_cyw43_init(context); -#endif - if (!ok) { - cyw43_arch_deinit(); - return PICO_ERROR_GENERIC; - } else { - return 0; - } -} - -void cyw43_arch_deinit(void) { - async_context_t *context = cyw43_arch_async_context(); -#if CYW43_ENABLE_BLUETOOTH - btstack_cyw43_deinit(context); -#endif - // there is a bit of a circular dependency here between lwIP and cyw43_driver. We - // shut down cyw43_driver first as it has IRQs calling back into lwIP. Also lwIP itself - // does not actually get shut down. - // todo add a "pause" method to async_context if we need to provide some atomicity (we - // don't want to take the lock as these methods may invoke execute_sync() - cyw43_driver_deinit(context); -#if CYW43_LWIP - lwip_nosys_deinit(context); -#endif - // if it is our context, then we de-init it. - if (context == &cyw43_async_context_poll.core) { - async_context_deinit(context); - cyw43_arch_set_async_context(NULL); - } -} - -#endif diff --git a/lib/main/pico-sdk/rp2_common/pico_cyw43_arch/cyw43_arch_threadsafe_background.c b/lib/main/pico-sdk/rp2_common/pico_cyw43_arch/cyw43_arch_threadsafe_background.c deleted file mode 100644 index 397da8a92e..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_cyw43_arch/cyw43_arch_threadsafe_background.c +++ /dev/null @@ -1,81 +0,0 @@ -/* - * Copyright (c) 2022 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#if PICO_CYW43_ARCH_THREADSAFE_BACKGROUND - -#include "pico/cyw43_arch.h" -#include "pico/cyw43_driver.h" -#include "pico/async_context_threadsafe_background.h" - -#if CYW43_LWIP -#include "pico/lwip_nosys.h" -#endif - -#if CYW43_ENABLE_BLUETOOTH -#include "pico/btstack_cyw43.h" -#endif - -#if CYW43_LWIP && !NO_SYS -#error PICO_CYW43_ARCH_THREADSAFE_BACKGROUND requires lwIP NO_SYS=1 -#endif -#if CYW43_LWIP && MEM_LIBC_MALLOC -// would attempt to use malloc from IRQ context -#error MEM_LIBC_MALLOC is incompatible with PICO_CYW43_ARCH_THREADSAFE_BACKGROUND -#endif - -static async_context_threadsafe_background_t cyw43_async_context_threadsafe_background; - -async_context_t *cyw43_arch_init_default_async_context(void) { - async_context_threadsafe_background_config_t config = async_context_threadsafe_background_default_config(); - if (async_context_threadsafe_background_init(&cyw43_async_context_threadsafe_background, &config)) - return &cyw43_async_context_threadsafe_background.core; - return NULL; -} - -int cyw43_arch_init(void) { - async_context_t *context = cyw43_arch_async_context(); - if (!context) { - context = cyw43_arch_init_default_async_context(); - if (!context) return PICO_ERROR_GENERIC; - cyw43_arch_set_async_context(context); - } - bool ok = cyw43_driver_init(context); -#if CYW43_LWIP - ok &= lwip_nosys_init(context); -#endif -#if CYW43_ENABLE_BLUETOOTH - ok &= btstack_cyw43_init(context); -#endif - if (!ok) { - cyw43_arch_deinit(); - return PICO_ERROR_GENERIC; - } else { - return 0; - } -} - -void cyw43_arch_deinit(void) { - async_context_t *context = cyw43_arch_async_context(); -#if CYW43_ENABLE_BLUETOOTH - btstack_cyw43_deinit(context); -#endif - // there is a bit of a circular dependency here between lwIP and cyw43_driver. We - // shut down cyw43_driver first as it has IRQs calling back into lwIP. Also lwIP itself - // does not actually get shut down. - // todo add a "pause" method to async_context if we need to provide some atomicity (we - // don't want to take the lock as these methods may invoke execute_sync() - cyw43_driver_deinit(context); -#if CYW43_LWIP - lwip_nosys_deinit(context); -#endif - // if it is our context, then we de-init it. - if (context == &cyw43_async_context_threadsafe_background.core) { - async_context_deinit(context); - cyw43_arch_set_async_context(NULL); - } -} - -#endif diff --git a/lib/main/pico-sdk/rp2_common/pico_cyw43_arch/include/pico/cyw43_arch.h b/lib/main/pico-sdk/rp2_common/pico_cyw43_arch/include/pico/cyw43_arch.h deleted file mode 100644 index 46aa098966..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_cyw43_arch/include/pico/cyw43_arch.h +++ /dev/null @@ -1,508 +0,0 @@ -/* - * Copyright (c) 2022 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _PICO_CYW43_ARCH_H -#define _PICO_CYW43_ARCH_H - -#include "pico.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#include "cyw43.h" -#include "cyw43_country.h" -#include "pico/async_context.h" - -#ifdef PICO_CYW43_ARCH_HEADER -#include __XSTRING(PICO_CYW43_ARCH_HEADER) -#else -#if PICO_CYW43_ARCH_POLL -#include "pico/cyw43_arch/arch_poll.h" -#elif PICO_CYW43_ARCH_THREADSAFE_BACKGROUND -#include "pico/cyw43_arch/arch_threadsafe_background.h" -#elif PICO_CYW43_ARCH_FREERTOS -#include "pico/cyw43_arch/arch_freertos.h" -#else -#error must specify support pico_cyw43_arch architecture type or set PICO_CYW43_ARCH_HEADER -#endif -#endif - -/** - * \defgroup cyw43_driver cyw43_driver - * \ingroup pico_cyw43_arch - * \brief Driver used for Pico W wireless -*/ - -/** - * \defgroup cyw43_ll cyw43_ll - * \ingroup cyw43_driver - * \brief Low Level CYW43 driver interface -*/ - -/** \file pico/cyw43_arch.h - * \defgroup pico_cyw43_arch pico_cyw43_arch - * - * \brief Architecture for integrating the CYW43 driver (for the wireless on Pico W) and lwIP (for TCP/IP stack) into the SDK. It is also necessary for accessing the on-board LED on Pico W - * - * Both the low level \c cyw43_driver and the lwIP stack require periodic servicing, and have limitations - * on whether they can be called from multiple cores/threads. - * - * \c pico_cyw43_arch attempts to abstract these complications into several behavioral groups: - * - * * \em 'poll' - This not multi-core/IRQ safe, and requires the user to call \ref cyw43_arch_poll periodically from their main loop - * * \em 'thread_safe_background' - This is multi-core/thread/task safe, and maintenance of the driver and TCP/IP stack is handled automatically in the background - * * \em 'freertos' - This is multi-core/thread/task safe, and uses a separate FreeRTOS task to handle lwIP and and driver work. - * - * As of right now, lwIP is the only supported TCP/IP stack, however the use of \c pico_cyw43_arch is intended to be independent of - * the particular TCP/IP stack used (and possibly Bluetooth stack used) in the future. For this reason, the integration of lwIP - * is handled in the base (\c pico_cyw43_arch) library based on the #define \ref CYW43_LWIP used by the \c cyw43_driver. - * - * \note As of version 1.5.0 of the Raspberry Pi Pico SDK, the \c pico_cyw43_arch library no longer directly implements - * the distinct behavioral abstractions. This is now handled by the more general \ref pico_async_context library. The - * user facing behavior of pico_cyw43_arch has not changed as a result of this implementation detail, however pico_cyw43_arch - * is now just a thin wrapper which creates an appropriate async_context and makes a simple call to add lwIP or cyw43_driver support - * as appropriate. You are free to perform this context creation and adding of lwIP, cyw43_driver or indeed any other additional - * future protocol/driver support to your async_context, however for now pico_cyw43_arch does still provide a few cyw43_ specific (i.e. Pico W) - * APIs for connection management, locking and GPIO interaction. - * - * \note The connection management APIs at least may be moved - * to a more generic library in a future release. The locking methods are now backed by their \ref pico_async_context equivalents, and - * those methods may be used interchangeably (see \ref cyw43_arch_lwip_begin, \ref cyw43_arch_lwip_end and \ref cyw43_arch_lwip_check for more details). - * - * \note For examples of creating of your own async_context and addition of \c cyw43_driver and \c lwIP support, please - * refer to the specific source files \c cyw43_arch_poll.c, \c cyw43_arch_threadsafe_background.c and \c cyw43_arch_freertos.c. - * - * Whilst you can use the \c pico_cyw43_arch library directly and specify \ref CYW43_LWIP (and other defines) yourself, several - * other libraries are made available to the build which aggregate the defines and other dependencies for you: - * - * * \b pico_cyw43_arch_lwip_poll - For using the RAW lwIP API (in `NO_SYS=1` mode) without any background processing or multi-core/thread safety. - * - * The user must call \ref cyw43_arch_poll periodically from their main loop. - * - * This wrapper library: - * - Sets \c CYW43_LWIP=1 to enable lwIP support in \c pico_cyw43_arch and \c cyw43_driver. - * - Sets \c PICO_CYW43_ARCH_POLL=1 to select the polling behavior. - * - Adds the \c pico_lwip as a dependency to pull in lwIP. - * - * * \b pico_cyw43_arch_lwip_threadsafe_background - For using the RAW lwIP API (in `NO_SYS=1` mode) with multi-core/thread safety, and automatic servicing of the \c cyw43_driver and - * lwIP in background. - * - * Calls into the \c cyw43_driver high level API (cyw43.h) may be made from either core or from lwIP callbacks, however calls into lwIP (which - * is not thread-safe) other than those made from lwIP callbacks, must be bracketed with \ref cyw43_arch_lwip_begin and \ref cyw43_arch_lwip_end. It is fine to bracket - * calls made from within lwIP callbacks too; you just don't have to. - * - * \note lwIP callbacks happen in a (low priority) IRQ context (similar to an alarm callback), so care should be taken when interacting - * with other code. - * - * This wrapper library: - * - Sets \c CYW43_LWIP=1 to enable lwIP support in \c pico_cyw43_arch and \c cyw43_driver - * - Sets \c PICO_CYW43_ARCH_THREADSAFE_BACKGROUND=1 to select the thread-safe/non-polling behavior. - * - Adds the pico_lwip as a dependency to pull in lwIP. - * - * - * This library \em can also be used under the RP2040 port of FreeRTOS with lwIP in `NO_SYS=1` mode (allowing you to call \c cyw43_driver APIs - * from any task, and to call lwIP from lwIP callbacks, or from any task if you bracket the calls with \ref cyw43_arch_lwip_begin and \ref cyw43_arch_lwip_end. Again, you should be - * careful about what you do in lwIP callbacks, as you cannot call most FreeRTOS APIs from within an IRQ context. Unless you have good reason, you should probably - * use the full FreeRTOS integration (with `NO_SYS=0`) provided by \c pico_cyw43_arch_lwip_sys_freertos. - * - * * \b pico_cyw43_arch_lwip_sys_freertos - For using the full lwIP API including blocking sockets in OS (`NO_SYS=0`) mode, along with with multi-core/task/thread safety, and automatic servicing of the \c cyw43_driver and - * the lwIP stack. - * - * This wrapper library: - * - Sets \c CYW43_LWIP=1 to enable lwIP support in \c pico_cyw43_arch and \c cyw43_driver. - * - Sets \c PICO_CYW43_ARCH_FREERTOS=1 to select the NO_SYS=0 lwip/FreeRTOS integration - * - Sets \c LWIP_PROVIDE_ERRNO=1 to provide error numbers needed for compilation without an OS - * - Adds the \c pico_lwip as a dependency to pull in lwIP. - * - Adds the lwIP/FreeRTOS code from lwip-contrib (in the contrib directory of lwIP) - * - * Calls into the \c cyw43_driver high level API (cyw43.h) may be made from any task or from lwIP callbacks, but not from IRQs. Calls into the lwIP RAW API (which is not thread safe) - * must be bracketed with \ref cyw43_arch_lwip_begin and \ref cyw43_arch_lwip_end. It is fine to bracket calls made from within lwIP callbacks too; you just don't have to. - * - * \note this wrapper library requires you to link FreeRTOS functionality with your application yourself. - * - * * \b pico_cyw43_arch_none - If you do not need the TCP/IP stack but wish to use the on-board LED. - * - * This wrapper library: - * - Sets \c CYW43_LWIP=0 to disable lwIP support in \c pico_cyw43_arch and \c cyw43_driver - */ - -// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_PICO_CYW43_ARCH, Enable/disable assertions in the pico_cyw43_arch module, type=bool, default=0, group=pico_cyw43_arch -#ifndef PARAM_ASSERTIONS_ENABLED_PICO_CYW43_ARCH -#ifdef PARAM_ASSERTIONS_ENABLED_CYW43_ARCH // backwards compatibility with SDK < 2.0.0 -#define PARAM_ASSERTIONS_ENABLED_PICO_CYW43_ARCH PARAM_ASSERTIONS_ENABLED_CYW43_ARCH -#else -#define PARAM_ASSERTIONS_ENABLED_PICO_CYW43_ARCH 0 -#endif -#endif - -// PICO_CONFIG: PICO_CYW43_ARCH_DEBUG_ENABLED, Enable/disable some debugging output in the pico_cyw43_arch module, type=bool, default=1 in debug builds, group=pico_cyw43_arch -#ifndef PICO_CYW43_ARCH_DEBUG_ENABLED -#ifndef NDEBUG -#define PICO_CYW43_ARCH_DEBUG_ENABLED 1 -#else -#define PICO_CYW43_ARCH_DEBUG_ENABLED 0 -#endif -#endif - -// PICO_CONFIG: PICO_CYW43_ARCH_DEFAULT_COUNTRY_CODE, Default country code for the cyw43 wireless driver, default=CYW43_COUNTRY_WORLDWIDE, group=pico_cyw43_arch -#ifndef PICO_CYW43_ARCH_DEFAULT_COUNTRY_CODE -#define PICO_CYW43_ARCH_DEFAULT_COUNTRY_CODE CYW43_COUNTRY_WORLDWIDE -#endif - -/*! - * \brief Initialize the CYW43 architecture - * \ingroup pico_cyw43_arch - * - * This method initializes the `cyw43_driver` code and initializes the lwIP stack (if it - * was enabled at build time). This method must be called prior to using any other \c pico_cyw43_arch, - * \c cyw43_driver or lwIP functions. - * - * \note this method initializes wireless with a country code of \c PICO_CYW43_ARCH_DEFAULT_COUNTRY_CODE - * which defaults to \c CYW43_COUNTRY_WORLDWIDE. Worldwide settings may not give the best performance; consider - * setting PICO_CYW43_ARCH_DEFAULT_COUNTRY_CODE to a different value or calling \ref cyw43_arch_init_with_country - * - * By default this method initializes the cyw43_arch code's own async_context by calling - * \ref cyw43_arch_init_default_async_context, however the user can specify use of their own async_context - * by calling \ref cyw43_arch_set_async_context() before calling this method - * - * \return 0 if the initialization is successful, an error code otherwise \see pico_error_codes - */ -int cyw43_arch_init(void); - -/*! - * \brief Initialize the CYW43 architecture for use in a specific country - * \ingroup pico_cyw43_arch - * - * This method initializes the `cyw43_driver` code and initializes the lwIP stack (if it - * was enabled at build time). This method must be called prior to using any other \c pico_cyw43_arch, - * \c cyw43_driver or lwIP functions. - * - * By default this method initializes the cyw43_arch code's own async_context by calling - * \ref cyw43_arch_init_default_async_context, however the user can specify use of their own async_context - * by calling \ref cyw43_arch_set_async_context() before calling this method - * - * \param country the country code to use (see \ref CYW43_COUNTRY_) - * \return 0 if the initialization is successful, an error code otherwise \see pico_error_codes - */ -int cyw43_arch_init_with_country(uint32_t country); - -/*! - * \brief De-initialize the CYW43 architecture - * \ingroup pico_cyw43_arch - * - * This method de-initializes the `cyw43_driver` code and de-initializes the lwIP stack (if it - * was enabled at build time). Note this method should always be called from the same core (or RTOS - * task, depending on the environment) as \ref cyw43_arch_init. - * - * Additionally if the cyw43_arch is using its own async_context instance, then that instance is de-initialized. - */ -void cyw43_arch_deinit(void); - -/*! - * \brief Return the current async_context currently in use by the cyw43_arch code - * \ingroup pico_cyw43_arch - * - * \return the async_context. - */ -async_context_t *cyw43_arch_async_context(void); - -/*! - * \brief Set the async_context to be used by the cyw43_arch_init - * \ingroup pico_cyw43_arch - * - * \note This method must be called before calling cyw43_arch_init or cyw43_arch_init_with_country - * if you wish to use a custom async_context instance. - * - * \param context the async_context to be used - */ -void cyw43_arch_set_async_context(async_context_t *context); - -/*! - * \brief Initialize the default async_context for the current cyw43_arch type - * \ingroup pico_cyw43_arch - * - * This method initializes and returns a pointer to the static async_context associated - * with cyw43_arch. This method is called by \ref cyw43_arch_init automatically - * if a different async_context has not been set by \ref cyw43_arch_set_async_context - * - * \return the context or NULL if initialization failed. - */ -async_context_t *cyw43_arch_init_default_async_context(void); - -/*! - * \brief Perform any processing required by the \c cyw43_driver or the TCP/IP stack - * \ingroup pico_cyw43_arch - * - * This method must be called periodically from the main loop when using a - * \em polling style \c pico_cyw43_arch (e.g. \c pico_cyw43_arch_lwip_poll ). It - * may be called in other styles, but it is unnecessary to do so. - */ -void cyw43_arch_poll(void); - -/*! - * \brief Sleep until there is cyw43_driver work to be done - * \ingroup pico_cyw43_arch - * - * This method may be called by code that is waiting for an event to - * come from the cyw43_driver, and has no work to do, but would like - * to sleep without blocking any background work associated with the cyw43_driver. - * - * \param until the time to wait until if there is no work to do. - */ -void cyw43_arch_wait_for_work_until(absolute_time_t until); - -/*! - * \fn cyw43_arch_lwip_begin - * \brief Acquire any locks required to call into lwIP - * \ingroup pico_cyw43_arch - * - * The lwIP API is not thread safe. You should surround calls into the lwIP API - * with calls to this method and \ref cyw43_arch_lwip_end. Note these calls are not - * necessary (but harmless) when you are calling back into the lwIP API from an lwIP callback. - * If you are using single-core polling only (pico_cyw43_arch_poll) then these calls are no-ops - * anyway it is good practice to call them anyway where they are necessary. - * - * \note as of SDK release 1.5.0, this is now equivalent to calling \ref async_context_acquire_lock_blocking - * on the async_context associated with cyw43_arch and lwIP. - * - * \sa cyw43_arch_lwip_end - * \sa cyw43_arch_lwip_protect - * \sa async_context_acquire_lock_blocking - * \sa cyw43_arch_async_context - */ -static inline void cyw43_arch_lwip_begin(void) { - cyw43_thread_enter(); -} - -/*! - * \fn void cyw43_arch_lwip_end(void) - * \brief Release any locks required for calling into lwIP - * \ingroup pico_cyw43_arch - * - * The lwIP API is not thread safe. You should surround calls into the lwIP API - * with calls to \ref cyw43_arch_lwip_begin and this method. Note these calls are not - * necessary (but harmless) when you are calling back into the lwIP API from an lwIP callback. - * If you are using single-core polling only (pico_cyw43_arch_poll) then these calls are no-ops - * anyway it is good practice to call them anyway where they are necessary. - * - * \note as of SDK release 1.5.0, this is now equivalent to calling \ref async_context_release_lock - * on the async_context associated with cyw43_arch and lwIP. - * - * \sa cyw43_arch_lwip_begin - * \sa cyw43_arch_lwip_protect - * \sa async_context_release_lock - * \sa cyw43_arch_async_context - */ -static inline void cyw43_arch_lwip_end(void) { - cyw43_thread_exit(); -} - -/*! - * \fn int cyw43_arch_lwip_protect(int (*func)(void *param), void *param) - * \brief sad Release any locks required for calling into lwIP - * \ingroup pico_cyw43_arch - * - * The lwIP API is not thread safe. You can use this method to wrap a function - * with any locking required to call into the lwIP API. If you are using - * single-core polling only (pico_cyw43_arch_poll) then there are no - * locks to required, but it is still good practice to use this function. - * - * \param func the function ta call with any required locks held - * \param param parameter to pass to \c func - * \return the return value from \c func - * \sa cyw43_arch_lwip_begin - * \sa cyw43_arch_lwip_end - */ -static inline int cyw43_arch_lwip_protect(int (*func)(void *param), void *param) { - cyw43_arch_lwip_begin(); - int rc = func(param); - cyw43_arch_lwip_end(); - return rc; -} - -/*! - * \fn void cyw43_arch_lwip_check(void) - * \brief Checks the caller has any locks required for calling into lwIP - * \ingroup pico_cyw43_arch - * - * The lwIP API is not thread safe. You should surround calls into the lwIP API - * with calls to \ref cyw43_arch_lwip_begin and this method. Note these calls are not - * necessary (but harmless) when you are calling back into the lwIP API from an lwIP callback. - * - * This method will assert in debug mode, if the above conditions are not met (i.e. it is not safe to - * call into the lwIP API) - * - * \note as of SDK release 1.5.0, this is now equivalent to calling \ref async_context_lock_check - * on the async_context associated with cyw43_arch and lwIP. - * - * \sa cyw43_arch_lwip_begin - * \sa cyw43_arch_lwip_protect - * \sa async_context_lock_check - * \sa cyw43_arch_async_context - */ - -/*! - * \brief Return the country code used to initialize cyw43_arch - * \ingroup pico_cyw43_arch - * - * \return the country code (see \ref CYW43_COUNTRY_) - */ -uint32_t cyw43_arch_get_country_code(void); - -/*! - * \brief Enables Wi-Fi STA (Station) mode. - * \ingroup pico_cyw43_arch - * - * This enables the Wi-Fi in \em Station mode such that connections can be made to other Wi-Fi Access Points - */ -void cyw43_arch_enable_sta_mode(void); - -/*! - * \brief Disables Wi-Fi STA (Station) mode. - * \ingroup pico_cyw43_arch - * - * This disables the Wi-Fi in \em Station mode, disconnecting any active connection. - * You should subsequently check the status by calling \ref cyw43_wifi_link_status. - */ -void cyw43_arch_disable_sta_mode(void); - -/*! - * \brief Enables Wi-Fi AP (Access point) mode. - * \ingroup pico_cyw43_arch - * - * This enables the Wi-Fi in \em Access \em Point mode such that connections can be made to the device by other Wi-Fi clients - * \param ssid the name for the access point - * \param password the password to use or NULL for no password. - * \param auth the authorization type to use when the password is enabled. Values are \ref CYW43_AUTH_WPA_TKIP_PSK, - * \ref CYW43_AUTH_WPA2_AES_PSK, or \ref CYW43_AUTH_WPA2_MIXED_PSK (see \ref CYW43_AUTH_) - */ -void cyw43_arch_enable_ap_mode(const char *ssid, const char *password, uint32_t auth); - -/*! - * \brief Disables Wi-Fi AP (Access point) mode. - * \ingroup pico_cyw43_arch - * - * This Disbles the Wi-Fi in \em Access \em Point mode. - */ -void cyw43_arch_disable_ap_mode(void); - -/*! - * \brief Attempt to connect to a wireless access point, blocking until the network is joined or a failure is detected. - * \ingroup pico_cyw43_arch - * - * \param ssid the network name to connect to - * \param pw the network password or NULL if there is no password required - * \param auth the authorization type to use when the password is enabled. Values are \ref CYW43_AUTH_WPA_TKIP_PSK, - * \ref CYW43_AUTH_WPA2_AES_PSK, or \ref CYW43_AUTH_WPA2_MIXED_PSK (see \ref CYW43_AUTH_) - * - * \return 0 if the initialization is successful, an error code otherwise \see pico_error_codes - */ -int cyw43_arch_wifi_connect_blocking(const char *ssid, const char *pw, uint32_t auth); - -/*! - * \brief Attempt to connect to a wireless access point specified by SSID and BSSID, blocking until the network is joined or a failure is detected. - * \ingroup pico_cyw43_arch - * - * \param ssid the network name to connect to - * \param bssid the network BSSID to connect to or NULL if ignored - * \param pw the network password or NULL if there is no password required - * \param auth the authorization type to use when the password is enabled. Values are \ref CYW43_AUTH_WPA_TKIP_PSK, - * \ref CYW43_AUTH_WPA2_AES_PSK, or \ref CYW43_AUTH_WPA2_MIXED_PSK (see \ref CYW43_AUTH_) - * - * \return 0 if the initialization is successful, an error code otherwise \see pico_error_codes - */ -int cyw43_arch_wifi_connect_bssid_blocking(const char *ssid, const uint8_t *bssid, const char *pw, uint32_t auth); - -/*! - * \brief Attempt to connect to a wireless access point, blocking until the network is joined, a failure is detected or a timeout occurs - * \ingroup pico_cyw43_arch - * - * \param ssid the network name to connect to - * \param pw the network password or NULL if there is no password required - * \param auth the authorization type to use when the password is enabled. Values are \ref CYW43_AUTH_WPA_TKIP_PSK, - * \ref CYW43_AUTH_WPA2_AES_PSK, or \ref CYW43_AUTH_WPA2_MIXED_PSK (see \ref CYW43_AUTH_) - * \param timeout how long to wait in milliseconds for a connection to succeed before giving up - * - * \return 0 if the initialization is successful, an error code otherwise \see pico_error_codes - */ -int cyw43_arch_wifi_connect_timeout_ms(const char *ssid, const char *pw, uint32_t auth, uint32_t timeout); - -/*! - * \brief Attempt to connect to a wireless access point specified by SSID and BSSID, blocking until the network is joined, a failure is detected or a timeout occurs - * \ingroup pico_cyw43_arch - * - * \param ssid the network name to connect to - * \param bssid the network BSSID to connect to or NULL if ignored - * \param pw the network password or NULL if there is no password required - * \param auth the authorization type to use when the password is enabled. Values are \ref CYW43_AUTH_WPA_TKIP_PSK, - * \ref CYW43_AUTH_WPA2_AES_PSK, or \ref CYW43_AUTH_WPA2_MIXED_PSK (see \ref CYW43_AUTH_) - * \param timeout how long to wait in milliseconds for a connection to succeed before giving up - * - * \return 0 if the initialization is successful, an error code otherwise \see pico_error_codes - */ -int cyw43_arch_wifi_connect_bssid_timeout_ms(const char *ssid, const uint8_t *bssid, const char *pw, uint32_t auth, uint32_t timeout); - -/*! - * \brief Start attempting to connect to a wireless access point - * \ingroup pico_cyw43_arch - * - * This method tells the CYW43 driver to start connecting to an access point. You should subsequently check the - * status by calling \ref cyw43_wifi_link_status. - * - * \param ssid the network name to connect to - * \param pw the network password or NULL if there is no password required - * \param auth the authorization type to use when the password is enabled. Values are \ref CYW43_AUTH_WPA_TKIP_PSK, - * \ref CYW43_AUTH_WPA2_AES_PSK, or \ref CYW43_AUTH_WPA2_MIXED_PSK (see \ref CYW43_AUTH_) - * - * \return 0 if the scan was started successfully, an error code otherwise \see pico_error_codes - */ -int cyw43_arch_wifi_connect_async(const char *ssid, const char *pw, uint32_t auth); - -/*! - * \brief Start attempting to connect to a wireless access point specified by SSID and BSSID - * \ingroup pico_cyw43_arch - * - * This method tells the CYW43 driver to start connecting to an access point. You should subsequently check the - * status by calling \ref cyw43_wifi_link_status. - * - * \param ssid the network name to connect to - * \param bssid the network BSSID to connect to or NULL if ignored - * \param pw the network password or NULL if there is no password required - * \param auth the authorization type to use when the password is enabled. Values are \ref CYW43_AUTH_WPA_TKIP_PSK, - * \ref CYW43_AUTH_WPA2_AES_PSK, or \ref CYW43_AUTH_WPA2_MIXED_PSK (see \ref CYW43_AUTH_) - * - * \return 0 if the scan was started successfully, an error code otherwise \see pico_error_codes - */ -int cyw43_arch_wifi_connect_bssid_async(const char *ssid, const uint8_t *bssid, const char *pw, uint32_t auth); - -/*! - * \brief Set a GPIO pin on the wireless chip to a given value - * \ingroup pico_cyw43_arch - * \note this method does not check for errors setting the GPIO. You can use the lower level \ref cyw43_gpio_set instead if you wish - * to check for errors. - * - * \param wl_gpio the GPIO number on the wireless chip - * \param value true to set the GPIO, false to clear it. - */ -void cyw43_arch_gpio_put(uint wl_gpio, bool value); - -/*! - * \brief Read the value of a GPIO pin on the wireless chip - * \ingroup pico_cyw43_arch - * \note this method does not check for errors setting the GPIO. You can use the lower level \ref cyw43_gpio_get instead if you wish - * to check for errors. - * - * \param wl_gpio the GPIO number on the wireless chip - * \return true if the GPIO is high, false otherwise - */ -bool cyw43_arch_gpio_get(uint wl_gpio); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/lib/main/pico-sdk/rp2_common/pico_cyw43_arch/include/pico/cyw43_arch/arch_freertos.h b/lib/main/pico-sdk/rp2_common/pico_cyw43_arch/include/pico/cyw43_arch/arch_freertos.h deleted file mode 100644 index 1ba23eff93..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_cyw43_arch/include/pico/cyw43_arch/arch_freertos.h +++ /dev/null @@ -1,20 +0,0 @@ -/* - * Copyright (c) 2022 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _PICO_CYW43_ARCH_ARCH_FREERTOS_H -#define _PICO_CYW43_ARCH_ARCH_FREERTOS_H - -// PICO_CONFIG: CYW43_TASK_STACK_SIZE, Stack size for the CYW43 FreeRTOS task in 4-byte words, type=int, default=1024, group=pico_cyw43_arch -#ifndef CYW43_TASK_STACK_SIZE -#define CYW43_TASK_STACK_SIZE 1024 -#endif - -// PICO_CONFIG: CYW43_TASK_PRIORITY, Priority for the CYW43 FreeRTOS task, type=int, default=tskIDLE_PRIORITY + 4, group=pico_cyw43_arch -#ifndef CYW43_TASK_PRIORITY -#define CYW43_TASK_PRIORITY (tskIDLE_PRIORITY + 4) -#endif - -#endif diff --git a/lib/main/pico-sdk/rp2_common/pico_cyw43_arch/include/pico/cyw43_arch/arch_poll.h b/lib/main/pico-sdk/rp2_common/pico_cyw43_arch/include/pico/cyw43_arch/arch_poll.h deleted file mode 100644 index a221917d97..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_cyw43_arch/include/pico/cyw43_arch/arch_poll.h +++ /dev/null @@ -1,12 +0,0 @@ -/* - * Copyright (c) 2022 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _PICO_CYW43_ARCH_ARCH_POLL_H -#define _PICO_CYW43_ARCH_ARCH_POLL_H - -// now obsolete; kept for backwards compatibility - -#endif diff --git a/lib/main/pico-sdk/rp2_common/pico_cyw43_arch/include/pico/cyw43_arch/arch_threadsafe_background.h b/lib/main/pico-sdk/rp2_common/pico_cyw43_arch/include/pico/cyw43_arch/arch_threadsafe_background.h deleted file mode 100644 index 005c15a846..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_cyw43_arch/include/pico/cyw43_arch/arch_threadsafe_background.h +++ /dev/null @@ -1,12 +0,0 @@ -/* - * Copyright (c) 2022 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _PICO_CYW43_ARCH_ARCH_THREADSAFE_BACKGROUND_H -#define _PICO_CYW43_ARCH_ARCH_THREADSAFE_BACKGROUND_H - -// now obsolete; kept for backwards compatibility - -#endif \ No newline at end of file diff --git a/lib/main/pico-sdk/rp2_common/pico_cyw43_driver/btstack_chipset_cyw43.c b/lib/main/pico-sdk/rp2_common/pico_cyw43_driver/btstack_chipset_cyw43.c deleted file mode 100644 index 2c481ed2b6..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_cyw43_driver/btstack_chipset_cyw43.c +++ /dev/null @@ -1,26 +0,0 @@ -/* - * Copyright (c) 2023 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "pico/btstack_chipset_cyw43.h" - -static void chipset_set_bd_addr_command(bd_addr_t addr, uint8_t *hci_cmd_buffer) { - hci_cmd_buffer[0] = 0x01; - hci_cmd_buffer[1] = 0xfc; - hci_cmd_buffer[2] = 0x06; - reverse_bd_addr(addr, &hci_cmd_buffer[3]); -} - -static const btstack_chipset_t btstack_chipset_cyw43 = { - .name = "CYW43", - .init = NULL, - .next_command = NULL, - .set_baudrate_command = NULL, - .set_bd_addr_command = chipset_set_bd_addr_command, -}; - -const btstack_chipset_t * btstack_chipset_cyw43_instance(void) { - return &btstack_chipset_cyw43; -} diff --git a/lib/main/pico-sdk/rp2_common/pico_cyw43_driver/btstack_cyw43.c b/lib/main/pico-sdk/rp2_common/pico_cyw43_driver/btstack_cyw43.c deleted file mode 100644 index 75061f1679..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_cyw43_driver/btstack_cyw43.c +++ /dev/null @@ -1,74 +0,0 @@ -/* - * Copyright (c) 2023 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "ble/le_device_db_tlv.h" -#include "classic/btstack_link_key_db_tlv.h" -#include "btstack_tlv.h" -#include "btstack_tlv_flash_bank.h" -#include "btstack_memory.h" -#include "hci.h" - -#if WANT_HCI_DUMP -#include "hci_dump.h" -#ifdef ENABLE_SEGGER_RTT -#include "hci_dump_segger_rtt_stdout.h" -#else -#include "hci_dump_embedded_stdout.h" -#endif -#endif - -#include "pico/btstack_hci_transport_cyw43.h" -#include "pico/btstack_run_loop_async_context.h" -#include "pico/btstack_flash_bank.h" -#include "pico/btstack_cyw43.h" - -static void setup_tlv(void) { - static btstack_tlv_flash_bank_t btstack_tlv_flash_bank_context; - const hal_flash_bank_t *hal_flash_bank_impl = pico_flash_bank_instance(); - - const btstack_tlv_t *btstack_tlv_impl = btstack_tlv_flash_bank_init_instance( - &btstack_tlv_flash_bank_context, - hal_flash_bank_impl, - NULL); - - // setup global TLV - btstack_tlv_set_instance(btstack_tlv_impl, &btstack_tlv_flash_bank_context); -#ifdef ENABLE_CLASSIC - const btstack_link_key_db_t *btstack_link_key_db = btstack_link_key_db_tlv_get_instance(btstack_tlv_impl, &btstack_tlv_flash_bank_context); - hci_set_link_key_db(btstack_link_key_db); -#endif -#ifdef ENABLE_BLE - // configure LE Device DB for TLV - le_device_db_tlv_configure(btstack_tlv_impl, &btstack_tlv_flash_bank_context); -#endif -} - -bool btstack_cyw43_init(async_context_t *context) { - // Initialise bluetooth - btstack_memory_init(); - btstack_run_loop_init(btstack_run_loop_async_context_get_instance(context)); - -#if WANT_HCI_DUMP -#ifdef ENABLE_SEGGER_RTT - hci_dump_init(hci_dump_segger_rtt_stdout_get_instance()); -#else - hci_dump_init(hci_dump_embedded_stdout_get_instance()); -#endif -#endif - - hci_init(hci_transport_cyw43_instance(), NULL); - - // setup TLV storage - setup_tlv(); - return true; -} - -void btstack_cyw43_deinit(__unused async_context_t *context) { - hci_power_control(HCI_POWER_OFF); - hci_close(); - btstack_run_loop_deinit(); - btstack_memory_deinit(); -} \ No newline at end of file diff --git a/lib/main/pico-sdk/rp2_common/pico_cyw43_driver/btstack_hci_transport_cyw43.c b/lib/main/pico-sdk/rp2_common/pico_cyw43_driver/btstack_hci_transport_cyw43.c deleted file mode 100644 index c0210b6512..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_cyw43_driver/btstack_hci_transport_cyw43.c +++ /dev/null @@ -1,159 +0,0 @@ -/* - * Copyright (c) 2023 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "pico.h" -#include "cyw43.h" -#include "hci_transport.h" -#include "hci.h" -#include "pico/btstack_hci_transport_cyw43.h" -#include "pico/btstack_chipset_cyw43.h" - -// assert outgoing pre-buffer for cyw43 header is available -#if !defined(HCI_OUTGOING_PRE_BUFFER_SIZE) || (HCI_OUTGOING_PRE_BUFFER_SIZE < 4) -#error HCI_OUTGOING_PRE_BUFFER_SIZE not defined or smaller than 4. Please update btstack_config.h -#endif - -// assert outgoing packet fragments are word aligned -#if !defined(HCI_ACL_CHUNK_SIZE_ALIGNMENT) || ((HCI_ACL_CHUNK_SIZE_ALIGNMENT & 3) != 0) -#error HCI_ACL_CHUNK_SIZE_ALIGNMENT not defined or not a multiply of 4. Please update btstack_config.h -#endif - -#define BT_DEBUG_ENABLED 0 -#if BT_DEBUG_ENABLED -#define BT_DEBUG(...) CYW43_PRINTF(__VA_ARGS__) -#else -#define BT_DEBUG(...) (void)0 -#endif - -// Callback when we have data -static void (*hci_transport_cyw43_packet_handler)(uint8_t packet_type, uint8_t *packet, uint16_t size) = NULL; - -// Incoming packet buffer - cyw43 packet header (incl packet type) + incoming pre buffer + max(acl header + acl payload, event header + event data) -__attribute__((aligned(4))) -static uint8_t hci_packet_with_pre_buffer[4 + HCI_INCOMING_PRE_BUFFER_SIZE + HCI_INCOMING_PACKET_BUFFER_SIZE ]; - -static btstack_data_source_t transport_data_source; -static bool hci_transport_ready; - -// Forward declaration -static void hci_transport_cyw43_process(void); - -static void hci_transport_data_source_process(btstack_data_source_t *ds, btstack_data_source_callback_type_t callback_type) { - assert(callback_type == DATA_SOURCE_CALLBACK_POLL); - assert(ds == &transport_data_source); - (void)callback_type; - (void)ds; - hci_transport_cyw43_process(); -} - -static void hci_transport_cyw43_init(const void *transport_config) { - UNUSED(transport_config); -} - -static int hci_transport_cyw43_open(void) { - int err = cyw43_bluetooth_hci_init(); - if (err != 0) { - CYW43_PRINTF("Failed to open cyw43 hci controller: %d\n", err); - return err; - } - - // OTP should be set in which case BT gets an address of wifi mac + 1 - // If OTP is not set for some reason BT gets set to 43:43:A2:12:1F:AC. - // So for safety, set the bluetooth device address here. - bd_addr_t addr; - cyw43_hal_get_mac(0, (uint8_t*)&addr); - addr[BD_ADDR_LEN - 1]++; - hci_set_chipset(btstack_chipset_cyw43_instance()); - hci_set_bd_addr(addr); - - btstack_run_loop_set_data_source_handler(&transport_data_source, &hci_transport_data_source_process); - btstack_run_loop_enable_data_source_callbacks(&transport_data_source, DATA_SOURCE_CALLBACK_POLL); - btstack_run_loop_add_data_source(&transport_data_source); - hci_transport_ready = true; - - return 0; -} - -static int hci_transport_cyw43_close(void) { - btstack_run_loop_disable_data_source_callbacks(&transport_data_source, DATA_SOURCE_CALLBACK_POLL); - btstack_run_loop_remove_data_source(&transport_data_source); - hci_transport_ready = false; - - return 0; -} - -static void hci_transport_cyw43_register_packet_handler(void (*handler)(uint8_t packet_type, uint8_t *packet, uint16_t size)) { - hci_transport_cyw43_packet_handler = handler; -} - -static int hci_transport_cyw43_can_send_now(uint8_t packet_type) { - UNUSED(packet_type); - return true; -} - -static int hci_transport_cyw43_send_packet(uint8_t packet_type, uint8_t *packet, int size) { - // store packet type before actual data and increase size - // This relies on HCI_OUTGOING_PRE_BUFFER_SIZE being set - uint8_t *buffer = &packet[-4]; - uint32_t buffer_size = size + 4; - buffer[3] = packet_type; - - CYW43_THREAD_ENTER - int err = cyw43_bluetooth_hci_write(buffer, buffer_size); - - if (err != 0) { - CYW43_PRINTF("Failed to send cyw43 hci packet: %d\n", err); - assert(false); - } else { - BT_DEBUG("bt sent %lu\n", buffer_size); - static uint8_t packet_sent_event[] = { HCI_EVENT_TRANSPORT_PACKET_SENT, 0}; - hci_transport_cyw43_packet_handler(HCI_EVENT_PACKET, &packet_sent_event[0], sizeof(packet_sent_event)); - } - CYW43_THREAD_EXIT - return err; -} - -// configure and return hci transport singleton -static const hci_transport_t hci_transport_cyw43 = { - /* const char * name; */ "CYW43", - /* void (*init) (const void *transport_config); */ &hci_transport_cyw43_init, - /* int (*open)(void); */ &hci_transport_cyw43_open, - /* int (*close)(void); */ &hci_transport_cyw43_close, - /* void (*register_packet_handler)(void (*handler)(...); */ &hci_transport_cyw43_register_packet_handler, - /* int (*can_send_packet_now)(uint8_t packet_type); */ &hci_transport_cyw43_can_send_now, - /* int (*send_packet)(...); */ &hci_transport_cyw43_send_packet, - /* int (*set_baudrate)(uint32_t baudrate); */ NULL, - /* void (*reset_link)(void); */ NULL, - /* void (*set_sco_config)(uint16_t voice_setting, int num_connections); */ NULL, -}; - -const hci_transport_t *hci_transport_cyw43_instance(void) { - return &hci_transport_cyw43; -} - -// Called to perform bt work from a data source -static void hci_transport_cyw43_process(void) { - CYW43_THREAD_LOCK_CHECK - uint32_t len = 0; - bool has_work; - do { - int err = cyw43_bluetooth_hci_read(hci_packet_with_pre_buffer, sizeof(hci_packet_with_pre_buffer), &len); - BT_DEBUG("bt in len=%lu err=%d\n", len, err); - if (err == 0 && len > 0) { - hci_transport_cyw43_packet_handler(hci_packet_with_pre_buffer[3], hci_packet_with_pre_buffer + 4, len - 4); - has_work = true; - } else { - has_work = false; - } - } while (has_work); -} - -// This is called from cyw43_poll_func. -void cyw43_bluetooth_hci_process(void) { - if (hci_transport_ready) { - btstack_run_loop_poll_data_sources_from_irq(); - } -} diff --git a/lib/main/pico-sdk/rp2_common/pico_cyw43_driver/cybt_shared_bus/cybt_shared_bus.c b/lib/main/pico-sdk/rp2_common/pico_cyw43_driver/cybt_shared_bus/cybt_shared_bus.c deleted file mode 100644 index b464b3f78a..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_cyw43_driver/cybt_shared_bus/cybt_shared_bus.c +++ /dev/null @@ -1,431 +0,0 @@ -/* - * Copyright (c) 2023 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include -#include -#include - -#include "cyw43_btbus.h" -#include "cyw43_ll.h" -#include "cyw43_config.h" -#include "cybt_shared_bus_driver.h" - -#include "cyw43_btfw_43439.h" - -#if CYW43_USE_HEX_BTFW -extern const char brcm_patch_version[]; -extern const uint8_t brcm_patchram_buf[]; -extern const int brcm_patch_ram_length; -#endif - -#define BTSDIO_FW_READY_POLLING_INTERVAL_MS (1) -#define BTSDIO_BT_AWAKE_POLLING_INTERVAL_MS (1) - -#define BTSDIO_FW_READY_POLLING_RETRY_COUNT (300) -#define BTSDIO_FW_AWAKE_POLLING_RETRY_COUNT (300) - -#define BTSDIO_FWBUF_OPER_DELAY_US (250) -#define BTFW_WAIT_TIME_MS (150) - -#define CYBT_DEBUG 0 -#define CYBT_VDEBUG 0 - -#if CYBT_DEBUG -#define cybt_debug(format,args...) printf("%d.%d: " format, (int)cyw43_hal_ticks_ms() / 1000, (int)cyw43_hal_ticks_ms() % 1000, ## args) -#else -#define cybt_debug(format, ...) ((void)0) -#endif -#define cybt_printf(format, args...) printf("%d.%d: " format, (int)cyw43_hal_ticks_ms() / 1000, (int)cyw43_hal_ticks_ms() % 1000, ## args) - -#define ROUNDUP(x, a) ((((x) + ((a) - 1)) / (a)) * (a)) -#define ROUNDDN(x, a) ((x) & ~((a) - 1)) -#define ISALIGNED(a, x) (((uint32_t)(a) & ((x) - 1)) == 0) - -#define CIRC_BUF_CNT(in, out) (((in) - (out)) & ((BTSDIO_FWBUF_SIZE)-1)) -#define CIRC_BUF_SPACE(in, out) CIRC_BUF_CNT((out), ((in) + 4)) - -typedef enum { - HCI_PACKET_TYPE_IGNORE = 0x00, - HCI_PACKET_TYPE_COMMAND = 0x01, - HCI_PACKET_TYPE_ACL = 0x02, - HCI_PACKET_TYPE_SCO = 0x03, - HCI_PACKET_TYPE_EVENT = 0x04, - HCI_PACKET_TYPE_DIAG = 0x07, - HCI_PACKET_TYPE_LOOPBACK = 0xFF -} hci_packet_type_t; - -static cybt_result_t cybt_fw_download_prepare(uint8_t **p_write_buf, uint8_t **p_hex_buf) { - *p_write_buf = NULL; - *p_hex_buf = NULL; - - *p_write_buf = cyw43_malloc(BTFW_DOWNLOAD_BLK_SIZE + BTFW_SD_ALIGN); - if (NULL == *p_write_buf) { - return CYBT_ERR_OUT_OF_MEMORY; - } - - *p_hex_buf = cyw43_malloc(BTFW_MAX_STR_LEN); - if (NULL == *p_hex_buf) { - cyw43_free(*p_write_buf); - return CYBT_ERR_OUT_OF_MEMORY; - } - - return CYBT_SUCCESS; -} - -static cybt_result_t cybt_fw_download_finish(uint8_t *p_write_buf, uint8_t *p_hex_buf) { - if (p_write_buf) { - cyw43_free(p_write_buf); - } - - if (p_hex_buf) { - cyw43_free(p_hex_buf); - } - - return CYBT_SUCCESS; -} - -static cybt_result_t cybt_wait_bt_ready(uint32_t max_polling_times) { - cyw43_delay_ms(BTFW_WAIT_TIME_MS); - do { - if (cybt_ready()) { - return CYBT_SUCCESS; - } - cyw43_delay_ms(BTSDIO_FW_READY_POLLING_INTERVAL_MS); - } while (max_polling_times--); - return CYBT_ERR_TIMEOUT; -} - -static cybt_result_t cybt_wait_bt_awake(uint32_t max_polling_times) { - do { - if (cybt_awake()) { - return CYBT_SUCCESS; - } - cyw43_delay_ms(BTSDIO_BT_AWAKE_POLLING_INTERVAL_MS); - } while (max_polling_times--); - return CYBT_ERR_TIMEOUT; -} - -int cyw43_btbus_init(cyw43_ll_t *self) { - cybt_result_t ret; - - uint8_t *p_write_buf = NULL; - uint8_t *p_hex_buf = NULL; - - cybt_sharedbus_driver_init(self); - - ret = cybt_fw_download_prepare(&p_write_buf, &p_hex_buf); - if (CYBT_SUCCESS != ret) { - cybt_printf("Could not allocate memory\n"); - return ret; - } - - cybt_debug("cybt_fw_download\n"); - const uint8_t *fw_data_buf; - uint32_t fw_data_len; -#if CYW43_USE_HEX_BTFW - cybt_printf("CYW43_USE_HEX_BTFW is true\n"); -#ifndef NDEBUG - cybt_printf("BT FW download, version = %s\n", brcm_patch_version); -#endif - fw_data_len = brcm_patch_ram_length; - fw_data_buf = brcm_patchram_buf; -#else - fw_data_len = cyw43_btfw_43439_len; - fw_data_buf = cyw43_btfw_43439; -#endif - ret = cybt_fw_download(fw_data_buf, - fw_data_len, - p_write_buf, - p_hex_buf - ); - - cybt_debug("cybt_fw_download_finish\n"); - cybt_fw_download_finish(p_write_buf, p_hex_buf); - - if (CYBT_SUCCESS != ret) { - cybt_printf("hci_open(): FW download failed (0x%x)\n", ret); - return CYBT_ERR_HCI_INIT_FAILED; - } - - cybt_debug("// cybt_wait_bt_ready\n"); - ret = cybt_wait_bt_ready(BTSDIO_FW_READY_POLLING_RETRY_COUNT); - assert(ret == CYBT_SUCCESS); - if (CYBT_SUCCESS == ret) { - cybt_debug("hci_open(): FW download successfully\n"); - } else { - cybt_printf("hci_open(): Failed to download FW\n"); - return CYBT_ERR_HCI_INIT_FAILED; - } - - ret = cybt_init_buffer(); - assert(ret == 0); - if (ret != 0) { - return ret; - } - ret = cybt_wait_bt_awake(BTSDIO_FW_AWAKE_POLLING_RETRY_COUNT); - assert(ret == 0); - if (ret != 0) { - return ret; - } - - cybt_set_host_ready(); - cybt_toggle_bt_intr(); - - return CYBT_SUCCESS; -} - -#if CYBT_VDEBUG -static void dump_bytes(const uint8_t *bptr, uint32_t len) { - unsigned int i = 0; - - for (i = 0; i < len; i++) { - if ((i & 0x07) == 0) { - printf("\n "); - } - printf("0x%02x", bptr[i]); - if (i != (len-1)) { - printf(", "); - } else { - } - } - printf("\n"); -} -#endif - -static cybt_result_t cybt_hci_write_buf(const uint8_t *p_data, uint32_t length) { - cybt_result_t ret_result = CYBT_SUCCESS; - cybt_fw_membuf_index_t fw_membuf_info = {0}; - - assert(ISALIGNED(p_data, 4)); - if (!ISALIGNED(p_data, 4)) { - cybt_printf("cybt_hci_write_hdr: buffer not aligned\n"); - return CYBT_ERR_BADARG; - } - - // total length including header - length = ROUNDUP(length, 4); - cybt_get_bt_buf_index(&fw_membuf_info); - uint32_t buf_space = CIRC_BUF_SPACE(fw_membuf_info.host2bt_in_val, fw_membuf_info.host2bt_out_val); - assert(length <= buf_space); // queue full? - if (length > buf_space) { - return CYBT_ERR_QUEUE_FULL; - } - - if (fw_membuf_info.host2bt_in_val + length <= BTSDIO_FWBUF_SIZE) { - // Don't need to wrap circular buf - cybt_debug("cybt_hci_write_hdr: 1-round write, len = %" PRId32 "\n", length); - cybt_mem_write_idx(H2B_BUF_ADDR_IDX, fw_membuf_info.host2bt_in_val, p_data, length); - fw_membuf_info.host2bt_in_val += length; - } else { - // Need to wrap circular buf - uint32_t first_write_len = BTSDIO_FWBUF_SIZE - fw_membuf_info.host2bt_in_val; - if (first_write_len >= 4) { - cybt_mem_write_idx(H2B_BUF_ADDR_IDX, fw_membuf_info.host2bt_in_val, p_data, first_write_len); - fw_membuf_info.host2bt_in_val += first_write_len; - } else { - first_write_len = 0; - } - uint32_t second_write_len = length - first_write_len; - cybt_debug("cybt_hci_write_hdr: 2-round write, 1st_len = %" PRId32 ", 2nd_len = %" PRId32 "\n", first_write_len, - second_write_len); - if (second_write_len > 0) { - cybt_mem_write_idx(H2B_BUF_ADDR_IDX, 0, p_data + first_write_len, second_write_len); - fw_membuf_info.host2bt_in_val += second_write_len; - } - } - - // Update circular buf pointer - const uint32_t new_h2b_in_val = fw_membuf_info.host2bt_in_val & (BTSDIO_FWBUF_SIZE - 1); - cybt_reg_write_idx(H2B_BUF_IN_ADDR_IDX, new_h2b_in_val); - - cybt_toggle_bt_intr(); - return ret_result; -} - -static cybt_result_t cybt_hci_read(uint8_t *p_data, uint32_t *p_length) { - cybt_result_t ret_result = CYBT_SUCCESS; - uint32_t fw_b2h_buf_count; - uint32_t new_b2h_out_val; - cybt_fw_membuf_index_t fw_membuf_info = {0}; - static uint32_t available = 0; - - assert(ISALIGNED(p_data, 4)); - if (!ISALIGNED(p_data, 4)) { - assert(false); - cybt_printf("cybt_hci_read: buffer not aligned\n"); - return CYBT_ERR_BADARG; - } - - uint32_t read_len = ROUNDUP(*p_length, 4); - - cybt_get_bt_buf_index(&fw_membuf_info); - fw_b2h_buf_count = CIRC_BUF_CNT(fw_membuf_info.bt2host_in_val, - fw_membuf_info.bt2host_out_val); - cybt_debug("cybt_hci_read: bt2host_in_val=%lu bt2host_out_val=%lu fw_b2h_buf_count=%ld\n", - fw_membuf_info.bt2host_in_val, fw_membuf_info.bt2host_out_val, fw_b2h_buf_count); - if (fw_b2h_buf_count < available) { - cybt_printf("error: cybt_hci_read buffer overflow fw_b2h_buf_count=%ld available=%lu\n", fw_b2h_buf_count, - available); - cybt_printf("error: cybt_hci_read bt2host_in_val=%lu bt2host_out_val=%lu\n", fw_membuf_info.bt2host_in_val, - fw_membuf_info.bt2host_out_val); - panic("cyw43 buffer overflow"); - } - - // No space in buffer - if (fw_b2h_buf_count == 0) { - *p_length = 0; - } else { - if (read_len > fw_b2h_buf_count) { - read_len = fw_b2h_buf_count; - } - - if (fw_membuf_info.bt2host_out_val + read_len <= BTSDIO_FWBUF_SIZE) { - // Don't need to wrap the circular buf - cybt_debug("cybt_hci_read: 1-round read, len = %" PRId32 "\n", read_len); - cybt_mem_read_idx(B2H_BUF_ADDR_IDX, fw_membuf_info.bt2host_out_val, p_data, read_len); - fw_membuf_info.bt2host_out_val += read_len; - } else { - // Need to wrap the circular buf - uint32_t first_read_len = BTSDIO_FWBUF_SIZE - fw_membuf_info.bt2host_out_val; - if (first_read_len >= 4) { - cybt_mem_read_idx(B2H_BUF_ADDR_IDX, fw_membuf_info.bt2host_out_val, p_data, first_read_len); - fw_membuf_info.bt2host_out_val += first_read_len; - } else { - first_read_len = 0; - } - uint32_t second_read_len = read_len - first_read_len; - cybt_debug("cybt_hci_read: 2-round read, 1st_len = %" PRId32 ", 2nd_len = %" PRId32 "\n", first_read_len, - second_read_len); - if (second_read_len > 0) { - cybt_mem_read_idx(B2H_BUF_ADDR_IDX, 0, p_data + first_read_len, second_read_len); - fw_membuf_info.bt2host_out_val += second_read_len; - } - } - available = fw_b2h_buf_count - read_len; // remember amount available to check for buffer overflow - - // Update pointer - new_b2h_out_val = fw_membuf_info.bt2host_out_val & (BTSDIO_FWBUF_SIZE - 1); - cybt_debug("cybt_hci_read new b2h_out = %" PRId32 "\n", new_b2h_out_val); - cybt_reg_write_idx(B2H_BUF_OUT_ADDR_IDX, new_b2h_out_val); - - // in case the real length is less than the requested one - *p_length = read_len; - } - cybt_toggle_bt_intr(); - return ret_result; -} - -static void cybt_bus_request(void) { - CYW43_THREAD_ENTER - // todo: Handle failure - cybt_result_t err = cybt_set_bt_awake(true); - assert(err == 0); - err = cybt_wait_bt_awake(BTSDIO_FW_AWAKE_POLLING_RETRY_COUNT); - assert(err == 0); - (void) err; -} - -static void cybt_bus_release(void) { - // mutex if using wifi - CYW43_THREAD_EXIT -} - -// Send the buffer which includes space for a 4 byte header at the start -// The last byte of the header should already be set to the packet type -int cyw43_btbus_write(uint8_t *buf, uint32_t size) { - uint16_t cmd_len = 0; - - // The size of the buffer should include a 4 byte header at the start - cmd_len = size - 4; //in BTSDIO, cmd_len does not include header length - - // Create payload starting with required headers - // Format: Cmd Len B0, Cmd Len B1, Cmd Len B2, HCI pckt type, Data - buf[0] = (uint8_t) (cmd_len & 0xFF); - buf[1] = (uint8_t) ((cmd_len & 0xFF00) >> 8); - buf[2] = 0; - - cybt_bus_request(); - - cybt_debug("cyw43_btbus_write: %d\n", cmd_len); -#if CYBT_VDEBUG - dump_bytes(buf, size); // dump header and data -#endif - - cybt_hci_write_buf(buf, size); - cybt_bus_release(); - - return 0; -} - -static bool cybt_hci_read_packet(uint8_t *buf, uint32_t max_buf_size, uint32_t *size) { - uint32_t total_read_len = 0; - uint32_t read_len = 0; - cybt_result_t bt_result; - - // Read the header into the first 4 bytes of the buffer - read_len = 4; //3 bytes BTSDIO packet length + 1 bytes PTI - bt_result = cybt_hci_read(buf, &read_len); - - if (bt_result != CYBT_SUCCESS) { - *size = 0; - cybt_printf("cybt_hci_read_packet: error %d", bt_result); - return true; - } - - if (read_len == 0) { - // No data is read from SPI - *size = 0; - cybt_debug("cybt_hci_read_packet: no data\n"); - return true; - } - - uint32_t hci_read_len = ((buf[2] << 16) & 0xFFFF00) | ((buf[1] << 8) & 0xFF00) | (buf[0] & 0xFF); - if (hci_read_len > max_buf_size - 4) { - *size = 0; - cybt_printf("cybt_hci_read_packet: too much data len %" PRId32"\n", hci_read_len); - assert(false); - return false; - } - total_read_len = hci_read_len; - - // Read the packet data after the header - cybt_debug("cybt_hci_read_packet: packet type 0x%" PRIx8 " len %" PRId32 "\n", buf[3], hci_read_len); - bt_result = cybt_hci_read(buf + 4, &total_read_len); - if (bt_result != CYBT_SUCCESS) { - *size = 0; - cybt_printf("cybt_hci_read_packet: read failed\n"); - assert(false); - return false; - } - - // Might read more because of alignment - if (total_read_len >= hci_read_len) { - assert(total_read_len == ROUNDUP(hci_read_len, 4)); // check if we're losing data? - *size = hci_read_len + 4; - } else { - assert(total_read_len > 0); - *size = total_read_len + 4; - cybt_printf("cybt_hci_read_packet: failed to read all data %lu < %lu\n", total_read_len, hci_read_len); - //assert(false); - return true; - } - - cybt_debug("cybt_hci_read_packet: %ld\n", *size); -#if CYBT_VDEBUG - dump_bytes(buf, *size); -#endif - - return true; -} - -// Reads the hci packet prepended with 4 byte header. The last header byte is the packet type -int cyw43_btbus_read(uint8_t *buf, uint32_t max_buf_size, uint32_t *size) { - cybt_bus_request(); - bool result = cybt_hci_read_packet(buf, max_buf_size, size); - cybt_bus_release(); - return result ? 0 : -1; -} diff --git a/lib/main/pico-sdk/rp2_common/pico_cyw43_driver/cybt_shared_bus/cybt_shared_bus_driver.c b/lib/main/pico-sdk/rp2_common/pico_cyw43_driver/cybt_shared_bus/cybt_shared_bus_driver.c deleted file mode 100644 index 452337f99c..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_cyw43_driver/cybt_shared_bus/cybt_shared_bus_driver.c +++ /dev/null @@ -1,721 +0,0 @@ -/* - * Copyright (c) 2023 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include -#include -#include - -#include "cyw43_ll.h" -#include "cybt_shared_bus_driver.h" - -// Bluetooth register corruption occurs if both wifi and bluetooth are fully utilised. -#define CYBT_CORRUPTION_TEST 1 -#if CYBT_CORRUPTION_TEST -static cybt_fw_membuf_index_t last_buf_index; -static uint32_t last_host_ctrl_reg; -static uint32_t last_bt_ctrl_reg; - -#include - -#endif - -#ifndef NDEBUG -#define cybt_printf(format, args ...) printf(format,##args) -#else -#define cybt_printf(...) -#endif - -#ifndef CYBT_DEBUG -#define CYBT_DEBUG 0 -#endif - -#if CYBT_DEBUG -#include -#define cybt_debug(format, args ...) printf(format,##args) -#else -#define cybt_debug(format, ...) ((void)0) -#endif - - -/****************************************************************************** - * Constants - ******************************************************************************/ -#define BTFW_MEM_OFFSET (0x19000000) - -/* BIT0 => WLAN Power UP and BIT1=> WLAN Wake */ -#define BT2WLAN_PWRUP_WAKE (0x03) -#define BT2WLAN_PWRUP_ADDR (0x640894)/* This address is specific to 43012B0 */ - -#define BTSDIO_OFFSET_HOST2BT_IN (0x00002000) -#define BTSDIO_OFFSET_HOST2BT_OUT (0x00002004) -#define BTSDIO_OFFSET_BT2HOST_IN (0x00002008) -#define BTSDIO_OFFSET_BT2HOST_OUT (0x0000200C) - -#define H2B_BUF_ADDR (buf_info.host2bt_buf_addr) -#define H2B_BUF_IN_ADDR (buf_info.host2bt_in_addr) -#define H2B_BUF_OUT_ADDR (buf_info.host2bt_out_addr) -#define B2H_BUF_ADDR (buf_info.bt2host_buf_addr) -#define B2H_BUF_IN_ADDR (buf_info.bt2host_in_addr) -#define B2H_BUF_OUT_ADDR (buf_info.bt2host_out_addr) - -static uint32_t wlan_ram_base_addr; -volatile uint32_t host_ctrl_cache_reg = 0; -#define WLAN_RAM_BASE_ADDR (wlan_ram_base_addr) - -// In wifi host driver these are all constants -#define BT_CTRL_REG_ADDR ((uint32_t)0x18000c7c) -#define HOST_CTRL_REG_ADDR ((uint32_t)0x18000d6c) -#define WLAN_RAM_BASE_REG_ADDR ((uint32_t)0x18000d68) - -typedef struct { - uint32_t host2bt_buf_addr; - uint32_t host2bt_in_addr; - uint32_t host2bt_out_addr; - uint32_t bt2host_buf_addr; - uint32_t bt2host_in_addr; - uint32_t bt2host_out_addr; -} cybt_fw_membuf_info_t; - -cybt_fw_membuf_info_t buf_info; - -#define BTFW_ADDR_MODE_UNKNOWN (0) -#define BTFW_ADDR_MODE_EXTENDED (1) -#define BTFW_ADDR_MODE_SEGMENT (2) -#define BTFW_ADDR_MODE_LINEAR32 (3) - -#define BTFW_HEX_LINE_TYPE_DATA (0) -#define BTFW_HEX_LINE_TYPE_END_OF_DATA (1) -#define BTFW_HEX_LINE_TYPE_EXTENDED_SEGMENT_ADDRESS (2) -#define BTFW_HEX_LINE_TYPE_EXTENDED_ADDRESS (4) -#define BTFW_HEX_LINE_TYPE_ABSOLUTE_32BIT_ADDRESS (5) - -#define BTSDIO_REG_DATA_VALID_BITMASK (1 << 1) -#define BTSDIO_REG_WAKE_BT_BITMASK (1 << 17) -#define BTSDIO_REG_SW_RDY_BITMASK (1 << 24) - -#define BTSDIO_REG_BT_AWAKE_BITMASK (1 << 8) -#define BTSDIO_REG_FW_RDY_BITMASK (1 << 24) - -#define BTSDIO_OFFSET_HOST_WRITE_BUF (0) -#define BTSDIO_OFFSET_HOST_READ_BUF BTSDIO_FWBUF_SIZE - -#define BTSDIO_FWBUF_OPER_DELAY_US (250) - -#define ROUNDUP(x, a) ((((x) + ((a) - 1)) / (a)) * (a)) -#define ROUNDDN(x, a) ((x) & ~((a) - 1)) -#define ISALIGNED(a, x) (((uint32_t)(a) & ((x) - 1)) == 0) - -typedef struct cybt_fw_cb { - const uint8_t *p_fw_mem_start; - uint32_t fw_len; - const uint8_t *p_next_line_start; -} cybt_fw_cb_t; - -typedef struct hex_file_data { - int addr_mode; - uint16_t hi_addr; - uint32_t dest_addr; - uint8_t *p_ds; -} hex_file_data_t; - -static cyw43_ll_t *cyw43_ll = NULL; - -static cybt_result_t cybt_reg_write(uint32_t reg_addr, uint32_t value); -static cybt_result_t cybt_reg_read(uint32_t reg_addr, uint32_t *p_value); -static cybt_result_t cybt_mem_write(uint32_t mem_addr, const uint8_t *p_data, uint32_t data_len); -static cybt_result_t cybt_mem_read(uint32_t mem_addr, uint8_t *p_data, uint32_t data_len); - -#if CYW43_USE_HEX_BTFW -const char *strnchr(const char *str, uint32_t len, int character) { - const char *end = str + len; - char c = (char)character; - do { - if (*str == c) { - return str; - } - } while (++str <= end); - return NULL; -} - -static uint32_t cybt_fw_hex_read_line(cybt_fw_cb_t *p_btfw_cb, - const char **p_line_start, - int len - ) { - uint32_t str_len = 0; - const char *p_str_end = NULL; - - if (NULL == p_btfw_cb || NULL == p_line_start) { - return str_len; - } - - *p_line_start = (const char *)p_btfw_cb->p_next_line_start; - p_str_end = strnchr(*p_line_start, len, '\n'); - if (p_str_end == NULL) { - return str_len; - } - - str_len = (uint32_t)(p_str_end - *p_line_start); - - /* Advance file pointer past the string length */ - p_btfw_cb->p_next_line_start += str_len + 1; - - return str_len; -} - -static inline uint8_t nibble_for_char(char c) { - if ((c >= '0') && (c <= '9')) return c - '0'; - if ((c >= 'A') && (c <= 'F')) return c - 'A' + 10; - return -1; -} - -static inline uint8_t read_hex_byte(const char *str) { - return nibble_for_char(*str) << 4 | nibble_for_char(*(str + 1)); -} - -static uint32_t read_hex(const char *str, int nchars) { - uint32_t result = 0; - assert(nchars > 0 && nchars <= 8 && nchars % 2 == 0); - for(int pos = 0; pos < nchars; pos += 2) { - result <<= 8; - result |= read_hex_byte(str + pos); - } - return result; -} - -static uint32_t cybt_fw_get_data(cybt_fw_cb_t *p_btfw_cb, - hex_file_data_t *hfd - ) { - uint32_t line_len; - uint16_t num_bytes, addr, data_pos, type, idx, octet; - uint32_t abs_base_addr32 = 0; - uint32_t data_len = 0; - const char *p_line_start = NULL; - - if (NULL == p_btfw_cb || NULL == hfd->p_ds) { - return data_len; - } - - while (data_len == 0) { - line_len = cybt_fw_hex_read_line(p_btfw_cb, &p_line_start, BTFW_MAX_STR_LEN); - if (line_len == 0) { - break; - } else if (line_len > 9) { - - num_bytes = (uint16_t)read_hex(p_line_start + 1, 2); - assert(num_bytes * 2 + 8 + 2 + 1 == line_len); - - int addr32 = read_hex(p_line_start + 3, 4); - assert(addr32 <= 0xffff); - addr = (uint16_t)addr32; - type = (uint16_t)read_hex(p_line_start + 7, 2); - assert(type <= 0xff); - - data_pos = 9; - - for (idx = 0; idx < num_bytes; idx++) - { - octet = (uint16_t)read_hex(p_line_start + data_pos, 2); - hfd->p_ds[idx] = (uint8_t)(octet & 0x00FF); - data_pos += 2; - } - - if (type == BTFW_HEX_LINE_TYPE_EXTENDED_ADDRESS) { - hfd->hi_addr = (hfd->p_ds[0] << 8) | hfd->p_ds[1]; - hfd->addr_mode = BTFW_ADDR_MODE_EXTENDED; - } else if (type == BTFW_HEX_LINE_TYPE_EXTENDED_SEGMENT_ADDRESS) { - hfd->hi_addr = (hfd->p_ds[0] << 8) | hfd->p_ds[1]; - hfd->addr_mode = BTFW_ADDR_MODE_SEGMENT; - } else if (type == BTFW_HEX_LINE_TYPE_ABSOLUTE_32BIT_ADDRESS) { - abs_base_addr32 = (hfd->p_ds[0] << 24) | (hfd->p_ds[1] << 16) | - (hfd->p_ds[2] << 8) | hfd->p_ds[3]; - hfd->addr_mode = BTFW_ADDR_MODE_LINEAR32; - } else if (type == BTFW_HEX_LINE_TYPE_DATA) { - hfd->dest_addr = addr; - - if (hfd->addr_mode == BTFW_ADDR_MODE_EXTENDED) { - hfd->dest_addr += (hfd->hi_addr << 16); - } else if (hfd->addr_mode == BTFW_ADDR_MODE_SEGMENT) { - hfd->dest_addr += (hfd->hi_addr << 4); - } else if (hfd->addr_mode == BTFW_ADDR_MODE_LINEAR32) { - hfd->dest_addr += abs_base_addr32; - } - - data_len = num_bytes; - } - } - } - - return data_len; -} -#else - -static uint32_t cybt_fw_get_data(cybt_fw_cb_t *p_btfw_cb, hex_file_data_t *hfd) { - uint32_t abs_base_addr32 = 0; - while (true) { - // 4 byte header - uint8_t num_bytes = *(p_btfw_cb->p_next_line_start)++; - uint16_t addr = *(p_btfw_cb->p_next_line_start)++ << 8; - addr |= *(p_btfw_cb->p_next_line_start)++; - uint8_t type = *(p_btfw_cb->p_next_line_start)++; - - // No data? - if (num_bytes == 0) break; - - // Copy the data - memcpy(hfd->p_ds, p_btfw_cb->p_next_line_start, num_bytes); - p_btfw_cb->p_next_line_start += num_bytes; - - // Adjust address based on type - if (type == BTFW_HEX_LINE_TYPE_EXTENDED_ADDRESS) { - hfd->hi_addr = (hfd->p_ds[0] << 8) | hfd->p_ds[1]; - hfd->addr_mode = BTFW_ADDR_MODE_EXTENDED; - } else if (type == BTFW_HEX_LINE_TYPE_EXTENDED_SEGMENT_ADDRESS) { - hfd->hi_addr = (hfd->p_ds[0] << 8) | hfd->p_ds[1]; - hfd->addr_mode = BTFW_ADDR_MODE_SEGMENT; - } else if (type == BTFW_HEX_LINE_TYPE_ABSOLUTE_32BIT_ADDRESS) { - abs_base_addr32 = (hfd->p_ds[0] << 24) | (hfd->p_ds[1] << 16) | - (hfd->p_ds[2] << 8) | hfd->p_ds[3]; - hfd->addr_mode = BTFW_ADDR_MODE_LINEAR32; - } else if (type == BTFW_HEX_LINE_TYPE_DATA) { - hfd->dest_addr = addr; - if (hfd->addr_mode == BTFW_ADDR_MODE_EXTENDED) { - hfd->dest_addr += (hfd->hi_addr << 16); - } else if (hfd->addr_mode == BTFW_ADDR_MODE_SEGMENT) { - hfd->dest_addr += (hfd->hi_addr << 4); - } else if (hfd->addr_mode == BTFW_ADDR_MODE_LINEAR32) { - hfd->dest_addr += abs_base_addr32; - } - return num_bytes; - } - } - return 0; -} - -#endif - -cybt_result_t cybt_fw_download(const uint8_t *p_bt_firmware, - uint32_t bt_firmware_len, - uint8_t *p_write_buf, - uint8_t *p_hex_buf) { - cybt_fw_cb_t btfw_cb; - hex_file_data_t hfd = {BTFW_ADDR_MODE_EXTENDED, 0, 0, NULL}; - uint8_t *p_mem_ptr; - uint32_t data_len; - - if (cyw43_ll == NULL) { - return CYBT_ERR_BADARG; - } - - if (NULL == p_bt_firmware || 0 == bt_firmware_len || NULL == p_write_buf || NULL == p_hex_buf) { - return CYBT_ERR_BADARG; - } - - // BT firmware starts with length of version string including a null terminator -#if !CYW43_USE_HEX_BTFW - uint8_t version_len = *p_bt_firmware; - assert(*(p_bt_firmware + version_len) == 0); -#ifndef NDEBUG - cybt_printf("BT FW download, version = %s\n", p_bt_firmware + 1); -#endif - p_bt_firmware += version_len + 1; // skip over version - p_bt_firmware += 1; // skip over record count -#endif - - p_mem_ptr = p_write_buf; - if ((uint32_t) (uintptr_t) p_mem_ptr % BTFW_SD_ALIGN) { - p_mem_ptr += (BTFW_SD_ALIGN - ((uint32_t) (uintptr_t) p_mem_ptr % BTFW_SD_ALIGN)); - } - - hfd.p_ds = p_hex_buf; - - btfw_cb.p_fw_mem_start = p_bt_firmware; - btfw_cb.fw_len = bt_firmware_len; - btfw_cb.p_next_line_start = p_bt_firmware; - - cybt_reg_write(BTFW_MEM_OFFSET + BT2WLAN_PWRUP_ADDR, BT2WLAN_PWRUP_WAKE); - - while ((data_len = cybt_fw_get_data(&btfw_cb, &hfd)) > 0) { - uint32_t fwmem_start_addr, fwmem_start_data, fwmem_end_addr, fwmem_end_data; - uint32_t write_data_len, idx, pad; - - fwmem_start_addr = BTFW_MEM_OFFSET + hfd.dest_addr; - write_data_len = 0; - - /** - * Make sure the start address is 4 byte aligned to avoid alignment issues - * with SD host controllers - */ - if (!ISALIGNED(fwmem_start_addr, 4)) { - pad = fwmem_start_addr % 4; - fwmem_start_addr = ROUNDDN(fwmem_start_addr, 4); - - cybt_mem_read(fwmem_start_addr, (uint8_t *) &fwmem_start_data, sizeof(uint32_t)); - - for (idx = 0; idx < pad; idx++, write_data_len++) { - p_mem_ptr[write_data_len] = (uint8_t) ((uint8_t *) &fwmem_start_data)[idx]; - } - } - memcpy(&(p_mem_ptr[write_data_len]), hfd.p_ds, data_len); - write_data_len += data_len; - - /** - * Make sure the length is multiple of 4bytes to avoid alignment issues - * with SD host controllers - */ - fwmem_end_addr = fwmem_start_addr + write_data_len; - if (!ISALIGNED(fwmem_end_addr, 4)) { - cybt_mem_read(ROUNDDN(fwmem_end_addr, 4), (uint8_t *) &fwmem_end_data, sizeof(uint32_t)); - for (idx = (fwmem_end_addr % 4); idx < 4; idx++, write_data_len++) { - p_mem_ptr[write_data_len] = (uint8_t) ((uint8_t *) &fwmem_end_data)[idx]; - } - } - - /* - * write ram - */ - if (((fwmem_start_addr & 0xFFF) + write_data_len) <= 0x1000) { - cybt_mem_write(fwmem_start_addr, p_mem_ptr, write_data_len); - } else { - uint32_t first_write_len = 0x1000 - (fwmem_start_addr & 0xFFF); - cybt_mem_write(fwmem_start_addr, p_mem_ptr, first_write_len); - cybt_mem_write(fwmem_start_addr + first_write_len, - p_mem_ptr + first_write_len, - write_data_len - first_write_len); - } - } - - return CYBT_SUCCESS; -} - -cybt_result_t cybt_set_host_ready(void) { - uint32_t reg_val; - - cybt_reg_read(HOST_CTRL_REG_ADDR, ®_val); - reg_val |= BTSDIO_REG_SW_RDY_BITMASK; - cybt_reg_write(HOST_CTRL_REG_ADDR, reg_val); -#if CYBT_CORRUPTION_TEST - last_host_ctrl_reg = reg_val; -#endif - return CYBT_SUCCESS; -} - -cybt_result_t cybt_toggle_bt_intr(void) { - uint32_t reg_val, new_val; - - cybt_reg_read(HOST_CTRL_REG_ADDR, ®_val); -#if CYBT_CORRUPTION_TEST - if ((reg_val & ~(BTSDIO_REG_SW_RDY_BITMASK | BTSDIO_REG_WAKE_BT_BITMASK | BTSDIO_REG_DATA_VALID_BITMASK)) != 0) { - cybt_printf("cybt_toggle_bt_intr read HOST_CTRL_REG_ADDR as 0x%08lx\n", reg_val); - cybt_debug_dump(); - panic("cyw43 btsdio register corruption"); - } - assert((reg_val & ~(BTSDIO_REG_SW_RDY_BITMASK | BTSDIO_REG_WAKE_BT_BITMASK | BTSDIO_REG_DATA_VALID_BITMASK)) == 0); -#endif - new_val = reg_val ^ BTSDIO_REG_DATA_VALID_BITMASK; - cybt_reg_write(HOST_CTRL_REG_ADDR, new_val); -#if CYBT_CORRUPTION_TEST - last_host_ctrl_reg = new_val; -#endif - return CYBT_SUCCESS; -} - -cybt_result_t cybt_set_bt_intr(int value) { - uint32_t reg_val, new_val; - - cybt_reg_read(HOST_CTRL_REG_ADDR, ®_val); - if (value) { - new_val = reg_val | BTSDIO_REG_DATA_VALID_BITMASK; - } else { - new_val = reg_val & ~BTSDIO_REG_DATA_VALID_BITMASK; - } - cybt_reg_write(HOST_CTRL_REG_ADDR, new_val); -#if CYBT_CORRUPTION_TEST - last_host_ctrl_reg = new_val; -#endif - return CYBT_SUCCESS; -} - -int cybt_ready(void) { - uint32_t reg_val; - cybt_reg_read(BT_CTRL_REG_ADDR, ®_val); -#if CYBT_CORRUPTION_TEST - if (reg_val & BTSDIO_REG_FW_RDY_BITMASK) { - last_bt_ctrl_reg = reg_val; - } -#endif - return (reg_val & BTSDIO_REG_FW_RDY_BITMASK) ? 1 : 0; -} - -int cybt_awake(void) { - uint32_t reg_val; - cybt_reg_read(BT_CTRL_REG_ADDR, ®_val); -#if CYBT_CORRUPTION_TEST - if (reg_val & BTSDIO_REG_BT_AWAKE_BITMASK) { - last_bt_ctrl_reg = reg_val; - } -#endif - return (reg_val & BTSDIO_REG_BT_AWAKE_BITMASK) ? 1 : 0; -} - -cybt_result_t cybt_set_bt_awake(int value) { - uint32_t reg_val_before; - cybt_reg_read(HOST_CTRL_REG_ADDR, ®_val_before); - - uint32_t reg_val_after = reg_val_before; - if (value) - reg_val_after |= BTSDIO_REG_WAKE_BT_BITMASK; - else - reg_val_after &= ~BTSDIO_REG_WAKE_BT_BITMASK; - - if (reg_val_before != reg_val_after) { - cybt_reg_write(HOST_CTRL_REG_ADDR, reg_val_after); -#if CYBT_CORRUPTION_TEST - last_host_ctrl_reg = reg_val_after; -#endif - } - return 0; -} - -void cybt_debug_dump(void) { -#if CYBT_CORRUPTION_TEST - uint32_t reg_val = 0; - cybt_fw_membuf_index_t buf_index; - - cybt_printf("WLAN_RAM_BASE_ADDR: 0x%08lx\n", WLAN_RAM_BASE_ADDR); - cybt_printf("H2B_BUF_ADDR: 0x%08lx\n", H2B_BUF_ADDR); - cybt_printf("B2H_BUF_ADDR: 0x%08lx\n", B2H_BUF_ADDR); - - cybt_reg_read(H2B_BUF_IN_ADDR, &buf_index.host2bt_in_val); - cybt_printf("H2B_BUF_IN_ADDR: 0x%08lx = 0x%08lx (last 0x%08lx)\n", H2B_BUF_IN_ADDR, buf_index.host2bt_in_val, - last_buf_index.host2bt_in_val); - - cybt_reg_read(H2B_BUF_OUT_ADDR, &buf_index.host2bt_out_val); - cybt_printf("H2B_BUF_OUT_ADDR: 0x%08lx = 0x%08lx (last 0x%08lx)\n", H2B_BUF_OUT_ADDR, buf_index.host2bt_out_val, - last_buf_index.host2bt_out_val); - - cybt_reg_read(B2H_BUF_IN_ADDR, &buf_index.bt2host_in_val); - cybt_printf("B2H_BUF_IN_ADDR: 0x%08lx = 0x%08lx (last 0x%08lx)\n", B2H_BUF_IN_ADDR, buf_index.bt2host_in_val, - last_buf_index.bt2host_in_val); - - cybt_reg_read(B2H_BUF_OUT_ADDR, &buf_index.bt2host_out_val); - cybt_printf("B2H_BUF_OUT_ADDR: 0x%08lx = 0x%08lx (last 0x%08lx)\n", B2H_BUF_OUT_ADDR, buf_index.bt2host_out_val, - last_buf_index.bt2host_out_val); - - cybt_reg_read(HOST_CTRL_REG_ADDR, ®_val); - cybt_printf("HOST_CTRL_REG_ADDR: 0x%08lx = 0x%08lx (last 0x%08lx)\n", HOST_CTRL_REG_ADDR, reg_val, - last_host_ctrl_reg); - - cybt_reg_read(BT_CTRL_REG_ADDR, ®_val); - cybt_printf("BT_CTRL_REG_ADDR: 0x%08lx = 0x%08lx (last 0x%08lx)\n", BT_CTRL_REG_ADDR, reg_val, last_bt_ctrl_reg); -#endif -} - -cybt_result_t cybt_get_bt_buf_index(cybt_fw_membuf_index_t *p_buf_index) { - uint32_t buf[4]; - - cybt_mem_read(H2B_BUF_IN_ADDR, (uint8_t *) buf, sizeof(buf)); - - p_buf_index->host2bt_in_val = buf[0]; - p_buf_index->host2bt_out_val = buf[1]; - p_buf_index->bt2host_in_val = buf[2]; - p_buf_index->bt2host_out_val = buf[3]; - - cybt_debug("cybt_get_bt_buf_index: h2b_in = 0x%08lx, h2b_out = 0x%08lx, b2h_in = 0x%08lx, b2h_out = 0x%08lx\n", - p_buf_index->host2bt_in_val, - p_buf_index->host2bt_out_val, - p_buf_index->bt2host_in_val, - p_buf_index->bt2host_out_val); - -#if CYBT_CORRUPTION_TEST - if (p_buf_index->host2bt_in_val >= BTSDIO_FWBUF_SIZE || p_buf_index->host2bt_out_val >= BTSDIO_FWBUF_SIZE || - p_buf_index->bt2host_in_val >= BTSDIO_FWBUF_SIZE || p_buf_index->bt2host_out_val >= BTSDIO_FWBUF_SIZE) { - cybt_printf("cybt_get_bt_buf_index invalid buffer value\n"); - cybt_debug_dump(); - } else { - memcpy((uint8_t *) &last_buf_index, (uint8_t *) p_buf_index, sizeof(cybt_fw_membuf_index_t)); - } -#endif - - assert(p_buf_index->host2bt_in_val < BTSDIO_FWBUF_SIZE); - assert(p_buf_index->host2bt_out_val < BTSDIO_FWBUF_SIZE); - assert(p_buf_index->bt2host_in_val < BTSDIO_FWBUF_SIZE); - assert(p_buf_index->bt2host_out_val < BTSDIO_FWBUF_SIZE); - - return CYBT_SUCCESS; -} - -static cybt_result_t cybt_reg_write(uint32_t reg_addr, uint32_t value) { - cybt_debug("cybt_reg_write 0x%08lx 0x%08lx\n", reg_addr, value); - cyw43_ll_write_backplane_reg(cyw43_ll, reg_addr, value); - if (reg_addr == HOST_CTRL_REG_ADDR) { - host_ctrl_cache_reg = value; - } - return CYBT_SUCCESS; -} - -static cybt_result_t cybt_reg_read(uint32_t reg_addr, uint32_t *p_value) { - if (reg_addr == HOST_CTRL_REG_ADDR) { - *p_value = host_ctrl_cache_reg; - return CYBT_SUCCESS; - } - *p_value = cyw43_ll_read_backplane_reg(cyw43_ll, reg_addr); - cybt_debug("cybt_reg_read 0x%08lx == 0x%08lx\n", reg_addr, *p_value); - return CYBT_SUCCESS; -} - -#if CYBT_DEBUG -static void dump_bytes(const uint8_t *bptr, uint32_t len) { - unsigned int i = 0; - - for (i = 0; i < len; i++) { - if ((i & 0x07) == 0) { - cybt_debug("\n "); - } - cybt_debug("0x%02x", bptr[i]); - if (i != (len - 1)) { - cybt_debug(", "); - } - } - cybt_debug("\n"); -} -#define DUMP_BYTES dump_bytes -#else -#define DUMP_BYTES(...) -#endif - -static cybt_result_t cybt_mem_write(uint32_t mem_addr, const uint8_t *p_data, uint32_t data_len) { - cybt_debug("cybt_mem_write addr 0x%08lx len %ld\n", mem_addr, data_len); - do { - uint32_t transfer_size = (data_len > CYW43_BUS_MAX_BLOCK_SIZE) ? CYW43_BUS_MAX_BLOCK_SIZE : data_len; - if ((mem_addr & 0xFFF) + transfer_size > 0x1000) { - transfer_size = 0x1000 - (mem_addr & 0xFFF); - } - cyw43_ll_write_backplane_mem(cyw43_ll, mem_addr, transfer_size, p_data); - cybt_debug(" write_mem addr 0x%08lx len %ld\n", mem_addr, transfer_size); - DUMP_BYTES(p_data, transfer_size); - data_len -= transfer_size; - p_data += transfer_size; - mem_addr += transfer_size; - } while (data_len > 0); - return CYBT_SUCCESS; -} - -static cybt_result_t cybt_mem_read(uint32_t mem_addr, uint8_t *p_data, uint32_t data_len) { - assert(data_len >= 4); - cybt_debug("cybt_mem_read addr 0x%08lx len %ld\n", mem_addr, data_len); - do { - uint32_t transfer_size = (data_len > CYW43_BUS_MAX_BLOCK_SIZE) ? CYW43_BUS_MAX_BLOCK_SIZE : data_len; - if ((mem_addr & 0xFFF) + transfer_size > 0x1000) { - transfer_size = 0x1000 - (mem_addr & 0xFFF); - } - cyw43_ll_read_backplane_mem(cyw43_ll, mem_addr, transfer_size, p_data); - cybt_debug(" read_mem addr 0x%08lx len %ld\n", mem_addr, transfer_size); - DUMP_BYTES(p_data, transfer_size); - data_len -= transfer_size; - p_data += transfer_size; - mem_addr += transfer_size; - } while (data_len > 0); - return CYBT_SUCCESS; -} - -static uint32_t cybt_get_addr(cybt_addr_idx_t addr_idx) { - uint32_t addr = 0; - - switch (addr_idx) { - case H2B_BUF_ADDR_IDX: - addr = H2B_BUF_ADDR; - break; - case H2B_BUF_IN_ADDR_IDX: - addr = H2B_BUF_IN_ADDR; - break; - case H2B_BUF_OUT_ADDR_IDX: - addr = H2B_BUF_OUT_ADDR; - break; - case B2H_BUF_ADDR_IDX: - addr = B2H_BUF_ADDR; - break; - case B2H_BUF_IN_ADDR_IDX: - addr = B2H_BUF_IN_ADDR; - break; - case B2H_BUF_OUT_ADDR_IDX: - addr = B2H_BUF_OUT_ADDR; - break; - default: - assert(0); - break; - } - return addr; -} - -cybt_result_t cybt_reg_write_idx(cybt_addr_idx_t reg_idx, uint32_t value) { - assert(reg_idx == H2B_BUF_IN_ADDR_IDX || reg_idx == B2H_BUF_OUT_ADDR_IDX); - assert(value < BTSDIO_FWBUF_SIZE); // writing out of bounds register value? - if ((reg_idx != H2B_BUF_IN_ADDR_IDX && reg_idx != B2H_BUF_OUT_ADDR_IDX) || value >= BTSDIO_FWBUF_SIZE) { - assert(0); - return CYBT_ERR_BADARG; - } - uint32_t reg_addr = cybt_get_addr(reg_idx); - return cybt_reg_write(reg_addr, value); -} - -cybt_result_t cybt_mem_write_idx(cybt_addr_idx_t mem_idx, uint32_t offset, const uint8_t *p_data, uint32_t data_len) { - assert(mem_idx == H2B_BUF_ADDR_IDX); // caller should only be writing to here? - assert(offset + data_len <= BTSDIO_FWBUF_SIZE); // writing out of bounds? - if (mem_idx != H2B_BUF_ADDR_IDX || (offset + data_len) > BTSDIO_FWBUF_SIZE) { - assert(0); - return CYBT_ERR_BADARG; - } - if (!ISALIGNED(p_data, 4)) { - return CYBT_ERR_BADARG; - } - uint32_t mem_addr = cybt_get_addr(mem_idx) + offset; - return cybt_mem_write(mem_addr, p_data, data_len); -} - -cybt_result_t cybt_mem_read_idx(cybt_addr_idx_t mem_idx, uint32_t offset, uint8_t *p_data, uint32_t data_len) { - assert(mem_idx == B2H_BUF_ADDR_IDX); // caller should only be reading from here? - assert(offset + data_len <= BTSDIO_FWBUF_SIZE); // reading out of bounds? - if (mem_idx != B2H_BUF_ADDR_IDX || (offset + data_len) > BTSDIO_FWBUF_SIZE) { - assert(0); - return CYBT_ERR_BADARG; - } - uint32_t mem_addr = cybt_get_addr(mem_idx) + offset; - return cybt_mem_read(mem_addr, p_data, data_len); -} - -cybt_result_t cybt_init_buffer(void) { - int result; - result = cybt_reg_read(WLAN_RAM_BASE_REG_ADDR, &WLAN_RAM_BASE_ADDR); - if (CYBT_SUCCESS != result) { - return result; - } - - cybt_debug("hci_open(): btfw ram base = 0x%" PRIx32 "\n", WLAN_RAM_BASE_ADDR); - - // Fill in reg info - // Data buffers - H2B_BUF_ADDR = WLAN_RAM_BASE_ADDR + BTSDIO_OFFSET_HOST_WRITE_BUF; - B2H_BUF_ADDR = WLAN_RAM_BASE_ADDR + BTSDIO_OFFSET_HOST_READ_BUF; - - // circular buffer indexes - H2B_BUF_IN_ADDR = WLAN_RAM_BASE_ADDR + BTSDIO_OFFSET_HOST2BT_IN; - H2B_BUF_OUT_ADDR = WLAN_RAM_BASE_ADDR + BTSDIO_OFFSET_HOST2BT_OUT; - B2H_BUF_IN_ADDR = WLAN_RAM_BASE_ADDR + BTSDIO_OFFSET_BT2HOST_IN; - B2H_BUF_OUT_ADDR = WLAN_RAM_BASE_ADDR + BTSDIO_OFFSET_BT2HOST_OUT; - - uint32_t reg_val = 0; - cybt_reg_write(H2B_BUF_IN_ADDR, reg_val); - cybt_reg_write(H2B_BUF_OUT_ADDR, reg_val); - cybt_reg_write(B2H_BUF_IN_ADDR, reg_val); - cybt_reg_write(B2H_BUF_OUT_ADDR, reg_val); - - return CYBT_SUCCESS; -} - -void cybt_sharedbus_driver_init(cyw43_ll_t *driver) { - cyw43_ll = driver; -} diff --git a/lib/main/pico-sdk/rp2_common/pico_cyw43_driver/cybt_shared_bus/cybt_shared_bus_driver.h b/lib/main/pico-sdk/rp2_common/pico_cyw43_driver/cybt_shared_bus/cybt_shared_bus_driver.h deleted file mode 100644 index c5e6e991e7..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_cyw43_driver/cybt_shared_bus/cybt_shared_bus_driver.h +++ /dev/null @@ -1,81 +0,0 @@ -/* - * Copyright (c) 2023 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef CYBT_SHARE_BUS_DRIVER_H -#define CYBT_SHARE_BUS_DRIVER_H - -#define BTSDIO_FWBUF_SIZE (0x1000) -#define BTFW_MAX_STR_LEN (600) -#define BTFW_SD_ALIGN (32) -#define BTFW_DOWNLOAD_BLK_SIZE (((BTFW_MAX_STR_LEN) / 2) + 8) - -typedef enum { - CYBT_SUCCESS = 0, - CYBT_ERR_BADARG = 0xB1, - CYBT_ERR_OUT_OF_MEMORY, - CYBT_ERR_TIMEOUT, - CYBT_ERR_HCI_INIT_FAILED, - CYBT_ERR_HCI_UNSUPPORTED_IF, - CYBT_ERR_HCI_UNSUPPORTED_BAUDRATE, - CYBT_ERR_HCI_NOT_INITIALIZE, - CYBT_ERR_HCI_WRITE_FAILED, - CYBT_ERR_HCI_READ_FAILED, - CYBT_ERR_HCI_GET_TX_MUTEX_FAILED, - CYBT_ERR_HCI_GET_RX_MUTEX_FAILED, - CYBT_ERR_HCI_SET_BAUDRATE_FAILED, - CYBT_ERR_HCI_SET_FLOW_CTRL_FAILED, - CYBT_ERR_INIT_MEMPOOL_FAILED, - CYBT_ERR_INIT_QUEUE_FAILED, - CYBT_ERR_CREATE_TASK_FAILED, - CYBT_ERR_SEND_QUEUE_FAILED, - CYBT_ERR_MEMPOOL_NOT_INITIALIZE, - CYBT_ERR_QUEUE_ALMOST_FULL, - CYBT_ERR_QUEUE_FULL, - CYBT_ERR_GPIO_POWER_INIT_FAILED, - CYBT_ERR_GPIO_DEV_WAKE_INIT_FAILED, - CYBT_ERR_GPIO_HOST_WAKE_INIT_FAILED, - CYBT_ERR_GENERIC -} cybt_result_t; - -typedef enum { - H2B_BUF_ADDR_IDX = 0x10, - H2B_BUF_IN_ADDR_IDX, - H2B_BUF_OUT_ADDR_IDX, - B2H_BUF_ADDR_IDX, - B2H_BUF_IN_ADDR_IDX, - B2H_BUF_OUT_ADDR_IDX, -} cybt_addr_idx_t; - -typedef struct { - uint32_t host2bt_in_val; - uint32_t host2bt_out_val; - uint32_t bt2host_in_val; - uint32_t bt2host_out_val; -} cybt_fw_membuf_index_t; - -struct _cyw43_ll_t; -void cybt_sharedbus_driver_init(struct _cyw43_ll_t *driver); - -cybt_result_t cybt_init_buffer(void); - -cybt_result_t cybt_reg_write_idx(cybt_addr_idx_t reg_idx, uint32_t value); -cybt_result_t cybt_mem_write_idx(cybt_addr_idx_t mem_idx, uint32_t offset, const uint8_t *p_data, uint32_t data_len); -cybt_result_t cybt_mem_read_idx(cybt_addr_idx_t mem_idx, uint32_t offset, uint8_t *p_data, uint32_t data_len); - -cybt_result_t cybt_fw_download(const uint8_t *p_bt_firmware, uint32_t bt_firmware_len, uint8_t *p_write_buf, uint8_t *p_hex_buf); - -int cybt_ready(void); -int cybt_awake(void); - -cybt_result_t cybt_set_bt_awake(int value); -cybt_result_t cybt_set_host_ready(void); -cybt_result_t cybt_set_bt_intr(int value); -cybt_result_t cybt_toggle_bt_intr(void); -cybt_result_t cybt_get_bt_buf_index(cybt_fw_membuf_index_t *p_buf_index); - -void cybt_debug_dump(void); - -#endif diff --git a/lib/main/pico-sdk/rp2_common/pico_cyw43_driver/cyw43-driver.BUILD b/lib/main/pico-sdk/rp2_common/pico_cyw43_driver/cyw43-driver.BUILD deleted file mode 100644 index 58148d868a..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_cyw43_driver/cyw43-driver.BUILD +++ /dev/null @@ -1,31 +0,0 @@ -load("@pico-sdk//bazel:defs.bzl", "compatible_with_pico_w") - -package(default_visibility = ["//visibility:public"]) - -cc_library( - name = "cyw43_driver", - srcs = [ - "src/cyw43_ctrl.c", - "src/cyw43_ll.c", - "src/cyw43_lwip.c", - "src/cyw43_stats.c", - ], - hdrs = glob(["**/*.h"]), - defines = select({ - "@pico-sdk//bazel/constraint:pico_btstack_config_unset": [ - "CYW43_ENABLE_BLUETOOTH=0", - ], - "//conditions:default": [ - "CYW43_ENABLE_BLUETOOTH=1", - ], - }), - includes = [ - "firmware", - "src", - ], - target_compatible_with = compatible_with_pico_w(), - deps = [ - "@pico-sdk//src/rp2_common/pico_cyw43_driver:cyw43_configport", - "@pico-sdk//src/rp2_common/pico_lwip", - ], -) diff --git a/lib/main/pico-sdk/rp2_common/pico_cyw43_driver/cyw43_bus_pio_spi.c b/lib/main/pico-sdk/rp2_common/pico_cyw43_driver/cyw43_bus_pio_spi.c deleted file mode 100644 index d9265dd0b6..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_cyw43_driver/cyw43_bus_pio_spi.c +++ /dev/null @@ -1,599 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include -#include - -#include "hardware/gpio.h" -#include "hardware/pio.h" -#include "hardware/clocks.h" -#include "hardware/sync.h" -#include "hardware/dma.h" -#include "cyw43_bus_pio_spi.pio.h" -#include "cyw43.h" -#include "cyw43_internal.h" -#include "cyw43_spi.h" -#include "cyw43_debug_pins.h" -#include "pico/cyw43_driver.h" - -#if CYW43_SPI_PIO - -#define IRQ_SAMPLE_DELAY_NS 100 - -#if !CYW43_PIN_WL_DYNAMIC && PICO_PIO_USE_GPIO_BASE -// The pins should all work in the same gpio base -static_assert((CYW43_PIN_WL_DATA_OUT < 32 && CYW43_PIN_WL_DATA_IN < 32 && CYW43_PIN_WL_CLOCK < 32) || - (CYW43_PIN_WL_DATA_OUT >= 16 && CYW43_PIN_WL_DATA_IN >= 16 && CYW43_PIN_WL_CLOCK >= 16), ""); -#endif - -#ifdef CYW43_SPI_PROGRAM_NAME -#define SPI_PROGRAM_NAME CYW43_SPI_PROGRAM_NAME -#else -//#define SPI_PROGRAM_NAME spi_gap0_sample1 // for lower cpu speed -#define SPI_PROGRAM_NAME spi_gap01_sample0 // for high cpu speed -#endif -#define SPI_PROGRAM_FUNC __CONCAT(SPI_PROGRAM_NAME, _program) -#define SPI_PROGRAM_GET_DEFAULT_CONFIG_FUNC __CONCAT(SPI_PROGRAM_NAME, _program_get_default_config) -#define SPI_OFFSET_END __CONCAT(SPI_PROGRAM_NAME, _offset_end) -#define SPI_OFFSET_LP1_END __CONCAT(SPI_PROGRAM_NAME, _offset_lp1_end) - -#if !CYW43_PIO_CLOCK_DIV_DYNAMIC -#define cyw43_pio_clock_div_int CYW43_PIO_CLOCK_DIV_INT -#define cyw43_pio_clock_div_frac CYW43_PIO_CLOCK_DIV_FRAC -#else -static uint16_t cyw43_pio_clock_div_int = CYW43_PIO_CLOCK_DIV_INT; -static uint8_t cyw43_pio_clock_div_frac = CYW43_PIO_CLOCK_DIV_FRAC; - -void cyw43_set_pio_clock_divisor(uint16_t clock_div_int, uint8_t clock_div_frac) { - cyw43_pio_clock_div_int = clock_div_int; - cyw43_pio_clock_div_frac = clock_div_frac; -} -#endif - -#define PADS_DRIVE_STRENGTH PADS_BANK0_GPIO0_DRIVE_VALUE_12MA - -#if !CYW43_USE_SPI -#error CYW43_USE_SPI should be true -#endif - -#ifndef NDEBUG -//#define ENABLE_SPI_DUMPING 1 -#endif - -// Set to 1 to enable -#if ENABLE_SPI_DUMPING //NDEBUG -#if 0 -#define DUMP_SPI_TRANSACTIONS(A) A -#else -static bool enable_spi_packet_dumping; // set to true to dump -#define DUMP_SPI_TRANSACTIONS(A) if (enable_spi_packet_dumping) {A} -#endif - -static uint32_t counter = 0; -#else -#define DUMP_SPI_TRANSACTIONS(A) -#endif - -//#define SWAP32(A) ((((A) & 0xff000000U) >> 8) | (((A) & 0xff0000U) << 8) | (((A) & 0xff00U) >> 8) | (((A) & 0xffU) << 8)) -__force_inline static uint32_t __swap16x2(uint32_t a) { - pico_default_asm ("rev16 %0, %0" : "+l" (a) : : ); - return a; -} -#define SWAP32(a) __swap16x2(a) - -typedef struct { - PIO pio; - uint pio_offset; - uint pio_sm; - int8_t dma_out; - int8_t dma_in; -} bus_data_t; - -static bus_data_t bus_data_instance; - -int cyw43_spi_init(cyw43_int_t *self) { - // Only does something if CYW43_LOGIC_DEBUG=1 - logic_debug_init(); - - assert(!self->bus_data); - self->bus_data = &bus_data_instance; - bus_data_t *bus_data = (bus_data_t *)self->bus_data; - bus_data->pio = NULL; - bus_data->dma_in = -1; - bus_data->dma_out = -1; - - const uint min_gpio = MIN(CYW43_PIN_WL_CLOCK, MIN(CYW43_PIN_WL_DATA_IN, CYW43_PIN_WL_DATA_OUT)); - const uint max_gpio = MAX(CYW43_PIN_WL_CLOCK, MAX(CYW43_PIN_WL_DATA_IN, CYW43_PIN_WL_DATA_OUT)); - if (!pio_claim_free_sm_and_add_program_for_gpio_range(&SPI_PROGRAM_FUNC, &bus_data->pio, &bus_data->pio_sm, &bus_data->pio_offset, min_gpio, max_gpio - min_gpio + 1, true)) { - cyw43_spi_deinit(self); - return CYW43_FAIL_FAST_CHECK(-CYW43_EIO); - } - pio_sm_config config = SPI_PROGRAM_GET_DEFAULT_CONFIG_FUNC(bus_data->pio_offset); - - sm_config_set_clkdiv_int_frac(&config, cyw43_pio_clock_div_int, cyw43_pio_clock_div_frac); - hw_write_masked(&pads_bank0_hw->io[CYW43_PIN_WL_CLOCK], - (uint)PADS_DRIVE_STRENGTH << PADS_BANK0_GPIO0_DRIVE_LSB, - PADS_BANK0_GPIO0_DRIVE_BITS - ); - hw_write_masked(&pads_bank0_hw->io[CYW43_PIN_WL_CLOCK], - (uint)1 << PADS_BANK0_GPIO0_SLEWFAST_LSB, - PADS_BANK0_GPIO0_SLEWFAST_BITS - ); - - sm_config_set_out_pins(&config, CYW43_PIN_WL_DATA_OUT, 1); - sm_config_set_in_pins(&config, CYW43_PIN_WL_DATA_IN); - sm_config_set_set_pins(&config, CYW43_PIN_WL_DATA_OUT, 1); - sm_config_set_sideset(&config, 1, false, false); - sm_config_set_sideset_pins(&config, CYW43_PIN_WL_CLOCK); - sm_config_set_in_shift(&config, false, true, 32); - sm_config_set_out_shift(&config, false, true, 32); - hw_set_bits(&bus_data->pio->input_sync_bypass, 1u << (CYW43_PIN_WL_DATA_IN - pio_get_gpio_base(bus_data->pio))); - pio_sm_set_config(bus_data->pio, bus_data->pio_sm, &config); - pio_sm_set_consecutive_pindirs(bus_data->pio, bus_data->pio_sm, CYW43_PIN_WL_CLOCK, 1, true); - gpio_set_function(CYW43_PIN_WL_DATA_OUT, pio_get_funcsel(bus_data->pio)); - - // Set data pin to pull down and schmitt - gpio_set_pulls(CYW43_PIN_WL_DATA_IN, false, true); - gpio_set_input_hysteresis_enabled(CYW43_PIN_WL_DATA_IN, true); - - pio_sm_exec(bus_data->pio, bus_data->pio_sm, pio_encode_set(pio_pins, 1)); - - bus_data->dma_out = (int8_t) dma_claim_unused_channel(false); - bus_data->dma_in = (int8_t) dma_claim_unused_channel(false); - if (bus_data->dma_out < 0 || bus_data->dma_in < 0) { - cyw43_spi_deinit(self); - return CYW43_FAIL_FAST_CHECK(-CYW43_EIO); - } - return 0; -} - -void cyw43_spi_deinit(cyw43_int_t *self) { - if (self->bus_data) { - bus_data_t *bus_data = (bus_data_t *)self->bus_data; - if (bus_data->pio) { - pio_remove_program_and_unclaim_sm(&SPI_PROGRAM_FUNC, bus_data->pio, bus_data->pio_sm, bus_data->pio_offset); - bus_data->pio = NULL; - } - if (bus_data->dma_out >= 0) { - dma_channel_cleanup(bus_data->dma_out); - dma_channel_unclaim(bus_data->dma_out); - bus_data->dma_out = -1; - } - if (bus_data->dma_in >= 0) { - dma_channel_cleanup(bus_data->dma_in); - dma_channel_unclaim(bus_data->dma_in); - bus_data->dma_in = -1; - } - self->bus_data = NULL; - } -} - -static void cs_set(bool value) { - gpio_put(CYW43_PIN_WL_CS, value); -} - -static __noinline void ns_delay(uint32_t ns) { - // cycles = ns * clk_sys_hz / 1,000,000,000 - uint32_t cycles = ns * (clock_get_hz(clk_sys) >> 16u) / (1000000000u >> 16u); - busy_wait_at_least_cycles(cycles); -} - -static void start_spi_comms(cyw43_int_t *self) { - bus_data_t *bus_data = (bus_data_t *)self->bus_data; - gpio_set_function(CYW43_PIN_WL_DATA_OUT, pio_get_funcsel(bus_data->pio)); - gpio_set_function(CYW43_PIN_WL_CLOCK, pio_get_funcsel(bus_data->pio)); - gpio_pull_down(CYW43_PIN_WL_CLOCK); - // Pull CS low - cs_set(false); -} - -// we need to atomically de-assert CS and enable IRQ -static void stop_spi_comms(void) { - // from this point a positive edge will cause an IRQ to be pending - cs_set(true); - - // we need to wait a bit in case the irq line is incorrectly high - ns_delay(IRQ_SAMPLE_DELAY_NS); -} - -#if ENABLE_SPI_DUMPING -static void dump_bytes(const uint8_t *bptr, uint32_t len) { - unsigned int i = 0; - - for (i = 0; i < len;) { - if ((i & 0x0f) == 0) { - printf("\n"); - } else if ((i & 0x07) == 0) { - printf(" "); - } - printf("%02x ", bptr[i++]); - } - printf("\n"); -} -#endif - -int cyw43_spi_transfer(cyw43_int_t *self, const uint8_t *tx, size_t tx_length, uint8_t *rx, - size_t rx_length) { - - if ((tx == NULL) && (rx == NULL)) { - return CYW43_FAIL_FAST_CHECK(-CYW43_EINVAL); - } - - bus_data_t *bus_data = (bus_data_t *)self->bus_data; - start_spi_comms(self); - if (rx != NULL) { - if (tx == NULL) { - tx = rx; - assert(tx_length && tx_length < rx_length); - } - DUMP_SPI_TRANSACTIONS( - printf("[%lu] bus TX/RX %u bytes rx %u:", counter++, tx_length, rx_length); - dump_bytes(tx, tx_length); - ) - assert(!(tx_length & 3)); - assert(!(((uintptr_t)tx) & 3)); - assert(!(((uintptr_t)rx) & 3)); - assert(!(rx_length & 3)); - - pio_sm_set_enabled(bus_data->pio, bus_data->pio_sm, false); - pio_sm_set_wrap(bus_data->pio, bus_data->pio_sm, bus_data->pio_offset, bus_data->pio_offset + SPI_OFFSET_END - 1); - pio_sm_clear_fifos(bus_data->pio, bus_data->pio_sm); - pio_sm_set_pindirs_with_mask(bus_data->pio, bus_data->pio_sm, - 1u << (CYW43_PIN_WL_DATA_OUT - pio_get_gpio_base(bus_data->pio)), - 1u << (CYW43_PIN_WL_DATA_OUT - pio_get_gpio_base(bus_data->pio))); - pio_sm_restart(bus_data->pio, bus_data->pio_sm); - pio_sm_clkdiv_restart(bus_data->pio, bus_data->pio_sm); - pio_sm_put(bus_data->pio, bus_data->pio_sm, tx_length * 8 - 1); - pio_sm_exec(bus_data->pio, bus_data->pio_sm, pio_encode_out(pio_x, 32)); - pio_sm_put(bus_data->pio, bus_data->pio_sm, (rx_length - tx_length) * 8 - 1); - pio_sm_exec(bus_data->pio, bus_data->pio_sm, pio_encode_out(pio_y, 32)); - pio_sm_exec(bus_data->pio, bus_data->pio_sm, pio_encode_jmp(bus_data->pio_offset)); - dma_channel_abort(bus_data->dma_out); - dma_channel_abort(bus_data->dma_in); - - dma_channel_config out_config = dma_channel_get_default_config(bus_data->dma_out); - channel_config_set_bswap(&out_config, true); - channel_config_set_dreq(&out_config, pio_get_dreq(bus_data->pio, bus_data->pio_sm, true)); - - dma_channel_configure(bus_data->dma_out, &out_config, &bus_data->pio->txf[bus_data->pio_sm], tx, tx_length / 4, true); - - dma_channel_config in_config = dma_channel_get_default_config(bus_data->dma_in); - channel_config_set_bswap(&in_config, true); - channel_config_set_dreq(&in_config, pio_get_dreq(bus_data->pio, bus_data->pio_sm, false)); - channel_config_set_write_increment(&in_config, true); - channel_config_set_read_increment(&in_config, false); - dma_channel_configure(bus_data->dma_in, &in_config, rx + tx_length, &bus_data->pio->rxf[bus_data->pio_sm], rx_length / 4 - tx_length / 4, true); - - pio_sm_set_enabled(bus_data->pio, bus_data->pio_sm, true); - __compiler_memory_barrier(); - - dma_channel_wait_for_finish_blocking(bus_data->dma_out); - dma_channel_wait_for_finish_blocking(bus_data->dma_in); - - __compiler_memory_barrier(); - memset(rx, 0, tx_length); // make sure we don't have garbage in what would have been returned data if using real SPI - } else if (tx != NULL) { - DUMP_SPI_TRANSACTIONS( - printf("[%lu] bus TX only %u bytes:", counter++, tx_length); - dump_bytes(tx, tx_length); - ) - assert(!(((uintptr_t)tx) & 3)); - assert(!(tx_length & 3)); - pio_sm_set_enabled(bus_data->pio, bus_data->pio_sm, false); - pio_sm_set_wrap(bus_data->pio, bus_data->pio_sm, bus_data->pio_offset, bus_data->pio_offset + SPI_OFFSET_LP1_END - 1); - pio_sm_clear_fifos(bus_data->pio, bus_data->pio_sm); - pio_sm_set_pindirs_with_mask(bus_data->pio, bus_data->pio_sm, - 1u << (CYW43_PIN_WL_DATA_OUT - pio_get_gpio_base(bus_data->pio)), - 1u << (CYW43_PIN_WL_DATA_OUT - pio_get_gpio_base(bus_data->pio))); - pio_sm_restart(bus_data->pio, bus_data->pio_sm); - pio_sm_clkdiv_restart(bus_data->pio, bus_data->pio_sm); - pio_sm_put(bus_data->pio, bus_data->pio_sm, tx_length * 8 - 1); - pio_sm_exec(bus_data->pio, bus_data->pio_sm, pio_encode_out(pio_x, 32)); - pio_sm_put(bus_data->pio, bus_data->pio_sm, 0); - pio_sm_exec(bus_data->pio, bus_data->pio_sm, pio_encode_out(pio_y, 32)); - pio_sm_exec(bus_data->pio, bus_data->pio_sm, pio_encode_jmp(bus_data->pio_offset)); - dma_channel_abort(bus_data->dma_out); - - dma_channel_config out_config = dma_channel_get_default_config(bus_data->dma_out); - channel_config_set_bswap(&out_config, true); - channel_config_set_dreq(&out_config, pio_get_dreq(bus_data->pio, bus_data->pio_sm, true)); - - dma_channel_configure(bus_data->dma_out, &out_config, &bus_data->pio->txf[bus_data->pio_sm], tx, tx_length / 4, true); - - uint32_t fdebug_tx_stall = 1u << (PIO_FDEBUG_TXSTALL_LSB + bus_data->pio_sm); - bus_data->pio->fdebug = fdebug_tx_stall; - pio_sm_set_enabled(bus_data->pio, bus_data->pio_sm, true); - while (!(bus_data->pio->fdebug & fdebug_tx_stall)) { - tight_loop_contents(); // todo timeout - } - __compiler_memory_barrier(); - pio_sm_set_enabled(bus_data->pio, bus_data->pio_sm, false); - pio_sm_set_consecutive_pindirs(bus_data->pio, bus_data->pio_sm, CYW43_PIN_WL_DATA_IN, 1, false); - } else if (rx != NULL) { /* currently do one at a time */ - DUMP_SPI_TRANSACTIONS( - printf("[%lu] bus TX %u bytes:", counter++, rx_length); - dump_bytes(rx, rx_length); - ) - panic_unsupported(); - } - pio_sm_exec(bus_data->pio, bus_data->pio_sm, pio_encode_mov(pio_pins, pio_null)); // for next time we turn output on - - stop_spi_comms(); - DUMP_SPI_TRANSACTIONS( - printf("RXed:"); - dump_bytes(rx, rx_length); - printf("\n"); - ) - - return 0; -} - -// Initialise our gpios -void cyw43_spi_gpio_setup(void) { - // Setup CYW43_PIN_WL_REG_ON (23) - gpio_init(CYW43_PIN_WL_REG_ON); - gpio_set_dir(CYW43_PIN_WL_REG_ON, GPIO_OUT); - gpio_pull_up(CYW43_PIN_WL_REG_ON); - - // Setup DO, DI and IRQ (24) - gpio_init(CYW43_PIN_WL_DATA_OUT); - gpio_set_dir(CYW43_PIN_WL_DATA_OUT, GPIO_OUT); - gpio_put(CYW43_PIN_WL_DATA_OUT, false); - - // Setup CS (25) - gpio_init(CYW43_PIN_WL_CS); - gpio_set_dir(CYW43_PIN_WL_CS, GPIO_OUT); - gpio_put(CYW43_PIN_WL_CS, true); -} - -// Reset wifi chip -void cyw43_spi_reset(void) { - gpio_put(CYW43_PIN_WL_REG_ON, false); // off - sleep_ms(20); - gpio_put(CYW43_PIN_WL_REG_ON, true); // on - sleep_ms(250); - - // Setup IRQ (24) - also used for DO, DI - gpio_init(CYW43_PIN_WL_HOST_WAKE); - gpio_set_dir(CYW43_PIN_WL_HOST_WAKE, GPIO_IN); -} - -static inline uint32_t make_cmd(bool write, bool inc, uint32_t fn, uint32_t addr, uint32_t sz) { - return write << 31 | inc << 30 | fn << 28 | (addr & 0x1ffff) << 11 | sz; -} - -#if CYW43_VERBOSE_DEBUG -static const char *func_name(int fn) { - switch (fn) - { - case BUS_FUNCTION: - return "BUS_FUNCTION"; - case BACKPLANE_FUNCTION: - return "BACKPLANE_FUNCTION"; - case WLAN_FUNCTION: - return "WLAN_FUNCTION"; - default: - return "UNKNOWN"; - } -} -#endif - -uint32_t read_reg_u32_swap(cyw43_int_t *self, uint32_t fn, uint32_t reg) { - uint32_t buf[2] = {0}; - assert(fn != BACKPLANE_FUNCTION); - buf[0] = SWAP32(make_cmd(false, true, fn, reg, 4)); - int ret = cyw43_spi_transfer(self, NULL, 4, (uint8_t *)buf, 8); - if (ret != 0) { - return ret; - } - return SWAP32(buf[1]); -} - -static inline uint32_t _cyw43_read_reg(cyw43_int_t *self, uint32_t fn, uint32_t reg, uint size) { - // Padding plus max read size of 32 bits + another 4? - static_assert(CYW43_BACKPLANE_READ_PAD_LEN_BYTES % 4 == 0, ""); - int index = (CYW43_BACKPLANE_READ_PAD_LEN_BYTES / 4) + 1 + 1; - uint32_t buf32[index]; - uint8_t *buf = (uint8_t *)buf32; - const uint32_t padding = (fn == BACKPLANE_FUNCTION) ? CYW43_BACKPLANE_READ_PAD_LEN_BYTES : 0; // Add response delay - buf32[0] = make_cmd(false, true, fn, reg, size); - - if (fn == BACKPLANE_FUNCTION) { - logic_debug_set(pin_BACKPLANE_READ, 1); - } - int ret = cyw43_spi_transfer(self, NULL, 4, buf, 8 + padding); - if (fn == BACKPLANE_FUNCTION) { - logic_debug_set(pin_BACKPLANE_READ, 0); - } - - if (ret != 0) { - return ret; - } - uint32_t result = buf32[padding > 0 ? index - 1 : 1]; - CYW43_VDEBUG("cyw43_read_reg_u%d %s 0x%lx=0x%lx\n", size * 8, func_name(fn), reg, result); - return result; -} - -uint32_t cyw43_read_reg_u32(cyw43_int_t *self, uint32_t fn, uint32_t reg) { - return _cyw43_read_reg(self, fn, reg, 4); -} - -int cyw43_read_reg_u16(cyw43_int_t *self, uint32_t fn, uint32_t reg) { - return _cyw43_read_reg(self, fn, reg, 2); -} - -int cyw43_read_reg_u8(cyw43_int_t *self, uint32_t fn, uint32_t reg) { - return _cyw43_read_reg(self, fn, reg, 1); -} - -// This is only used to switch the word order on boot -int write_reg_u32_swap(cyw43_int_t *self, uint32_t fn, uint32_t reg, uint32_t val) { - uint32_t buf[2]; - // Boots up in little endian so command needs swapping too - buf[0] = SWAP32(make_cmd(true, true, fn, reg, 4)); - buf[1] = SWAP32(val); - int ret = cyw43_spi_transfer(self, (uint8_t *)buf, 8, NULL, 0); - CYW43_VDEBUG("write_reg_u32_swap %s 0x%lx=0x%lx\n", func_name(fn), reg, val); - return ret; -} - -static inline int _cyw43_write_reg(cyw43_int_t *self, uint32_t fn, uint32_t reg, uint32_t val, uint size) { - uint32_t buf[2]; - buf[0] = make_cmd(true, true, fn, reg, size); - buf[1] = val; - if (fn == BACKPLANE_FUNCTION) { - // In case of f1 overflow - self->last_size = 8; - self->last_header[0] = buf[0]; - self->last_header[1] = buf[1]; - self->last_backplane_window = self->cur_backplane_window; - } - - if (fn == BACKPLANE_FUNCTION) { - logic_debug_set(pin_BACKPLANE_WRITE, 1); - } - - int ret = cyw43_spi_transfer(self, (uint8_t *)buf, 8, NULL, 0); - - if (fn == BACKPLANE_FUNCTION) { - logic_debug_set(pin_BACKPLANE_WRITE, 0); - } - - CYW43_VDEBUG("cyw43_write_reg_u%d %s 0x%lx=0x%lx\n", size * 8, func_name(fn), reg, val); - return ret; -} - -int cyw43_write_reg_u32(cyw43_int_t *self, uint32_t fn, uint32_t reg, uint32_t val) { - return _cyw43_write_reg(self, fn, reg, val, 4); -} - -int cyw43_write_reg_u16(cyw43_int_t *self, uint32_t fn, uint32_t reg, uint16_t val) { - return _cyw43_write_reg(self, fn, reg, val, 2); -} - -int cyw43_write_reg_u8(cyw43_int_t *self, uint32_t fn, uint32_t reg, uint32_t val) { - return _cyw43_write_reg(self, fn, reg, val, 1); -} - -#if CYW43_BUS_MAX_BLOCK_SIZE > 0x7f8 -#error Block size is wrong for SPI -#endif - -int cyw43_read_bytes(cyw43_int_t *self, uint32_t fn, uint32_t addr, size_t len, uint8_t *buf) { - assert(fn != BACKPLANE_FUNCTION || (len <= CYW43_BUS_MAX_BLOCK_SIZE)); - const uint32_t padding = (fn == BACKPLANE_FUNCTION) ? CYW43_BACKPLANE_READ_PAD_LEN_BYTES : 0; // Add response delay - size_t aligned_len = (len + 3) & ~3; - assert(aligned_len > 0 && aligned_len <= 0x7f8); - assert(buf == self->spid_buf || buf < self->spid_buf || buf >= (self->spid_buf + sizeof(self->spid_buf))); - self->spi_header[padding > 0 ? 0 : (CYW43_BACKPLANE_READ_PAD_LEN_BYTES / 4)] = make_cmd(false, true, fn, addr, len); - if (fn == WLAN_FUNCTION) { - logic_debug_set(pin_WIFI_RX, 1); - } - int ret = cyw43_spi_transfer(self, NULL, 4, (uint8_t *)&self->spi_header[padding > 0 ? 0 : (CYW43_BACKPLANE_READ_PAD_LEN_BYTES / 4)], aligned_len + 4 + padding); - if (fn == WLAN_FUNCTION) { - logic_debug_set(pin_WIFI_RX, 0); - } - if (ret != 0) { - CYW43_PRINTF("cyw43_read_bytes error %d", ret); - return ret; - } - if (buf != self->spid_buf) { // avoid a copy in the usual case just to add the header - memcpy(buf, self->spid_buf, len); - } - return 0; -} - -// See whd_bus_spi_transfer_bytes -// Note, uses spid_buf if src isn't using it already -// Apart from firmware download this appears to only be used for wlan functions? -int cyw43_write_bytes(cyw43_int_t *self, uint32_t fn, uint32_t addr, size_t len, const uint8_t *src) { - assert(fn != BACKPLANE_FUNCTION || (len <= CYW43_BUS_MAX_BLOCK_SIZE)); - const size_t aligned_len = (len + 3) & ~3u; - assert(aligned_len > 0 && aligned_len <= 0x7f8); - if (fn == WLAN_FUNCTION) { - // Wait for FIFO to be ready to accept data - int f2_ready_attempts = 1000; - while (f2_ready_attempts-- > 0) { - uint32_t bus_status = cyw43_read_reg_u32(self, BUS_FUNCTION, SPI_STATUS_REGISTER); - if (bus_status & STATUS_F2_RX_READY) { - logic_debug_set(pin_F2_RX_READY_WAIT, 0); - break; - } else { - logic_debug_set(pin_F2_RX_READY_WAIT, 1); - } - } - if (f2_ready_attempts <= 0) { - CYW43_PRINTF("F2 not ready\n"); - return CYW43_FAIL_FAST_CHECK(-CYW43_EIO); - } - } - if (src == self->spid_buf) { // avoid a copy in the usual case just to add the header - self->spi_header[(CYW43_BACKPLANE_READ_PAD_LEN_BYTES / 4)] = make_cmd(true, true, fn, addr, len); - logic_debug_set(pin_WIFI_TX, 1); - int res = cyw43_spi_transfer(self, (uint8_t *)&self->spi_header[(CYW43_BACKPLANE_READ_PAD_LEN_BYTES / 4)], aligned_len + 4, NULL, 0); - logic_debug_set(pin_WIFI_TX, 0); - return res; - } else { - // todo: would be nice to get rid of this. Only used for firmware download? - assert(src < self->spid_buf || src >= (self->spid_buf + sizeof(self->spid_buf))); - self->spi_header[(CYW43_BACKPLANE_READ_PAD_LEN_BYTES / 4)] = make_cmd(true, true, fn, addr, len); - memcpy(self->spid_buf, src, len); - return cyw43_spi_transfer(self, (uint8_t *)&self->spi_header[(CYW43_BACKPLANE_READ_PAD_LEN_BYTES / 4)], aligned_len + 4, NULL, 0); - } -} -#endif - -#if CYW43_PIN_WL_DYNAMIC - -// storage for cyw43 pins -static uint cyw43_pin_array[CYW43_PIN_INDEX_WL_COUNT] = { - CYW43_DEFAULT_PIN_WL_REG_ON, - CYW43_DEFAULT_PIN_WL_DATA_OUT, - CYW43_DEFAULT_PIN_WL_DATA_IN, - CYW43_DEFAULT_PIN_WL_HOST_WAKE, - CYW43_DEFAULT_PIN_WL_CLOCK, - CYW43_DEFAULT_PIN_WL_CS -}; - -// Check the cyw43 gpio pin array is valid -static bool cyw43_pins_valid(uint pins[CYW43_PIN_INDEX_WL_COUNT]) { - // check the gpios are valid - for(int i = 0; i < CYW43_PIN_INDEX_WL_COUNT; i++) { - if (pins[i] >= NUM_BANK0_GPIOS) { - return false; - } - } -#if PICO_PIO_USE_GPIO_BASE - // These pins should use the same gpio base - return (pins[CYW43_PIN_INDEX_WL_DATA_OUT] < 32 && pins[CYW43_PIN_INDEX_WL_DATA_IN] < 32 && pins[CYW43_PIN_INDEX_WL_CLOCK] < 32) || - (pins[CYW43_PIN_INDEX_WL_DATA_OUT] >= 16 && pins[CYW43_PIN_INDEX_WL_DATA_IN] >= 16 && pins[CYW43_PIN_INDEX_WL_CLOCK] >= 16); -#else - return true; -#endif -} - -// Set the gpio pin array -int cyw43_set_pins_wl(uint pins[CYW43_PIN_INDEX_WL_COUNT]) { - assert(!bus_data_instance.pio); - if (bus_data_instance.pio) { - return PICO_ERROR_RESOURCE_IN_USE; - } - assert(cyw43_pins_valid(pins)); - if (!cyw43_pins_valid(pins)) { - return PICO_ERROR_INVALID_ARG; - } - memcpy(cyw43_pin_array, pins, sizeof(cyw43_pin_array)); - return PICO_OK; -} - -// Get a gpio pin -uint cyw43_get_pin_wl(cyw43_pin_index_t pin_id) { - assert(pin_id < CYW43_PIN_INDEX_WL_COUNT); - assert(cyw43_pin_array[pin_id] < NUM_BANK0_GPIOS); - return cyw43_pin_array[pin_id]; -} -#endif // CYW43_PIN_WL_DYNAMIC \ No newline at end of file diff --git a/lib/main/pico-sdk/rp2_common/pico_cyw43_driver/cyw43_bus_pio_spi.pio b/lib/main/pico-sdk/rp2_common/pico_cyw43_driver/cyw43_bus_pio_spi.pio deleted file mode 100644 index ea0d19549a..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_cyw43_driver/cyw43_bus_pio_spi.pio +++ /dev/null @@ -1,61 +0,0 @@ -; -; Copyright (c) 2020 Raspberry Pi (Trading) Ltd. -; -; SPDX-License-Identifier: BSD-3-Clause -; - -.program spi_gap0_sample1 -.side_set 1 - -; always transmit multiple of 32 bytes -lp: out pins, 1 side 0 - jmp x-- lp side 1 -public lp1_end: - set pindirs, 0 side 0 -lp2: - in pins, 1 side 1 - jmp y-- lp2 side 0 -public end: - -.program spi_gap01_sample0 -.side_set 1 - -; always transmit multiple of 32 bytes -lp: out pins, 1 side 0 - jmp x-- lp side 1 -public lp1_end: - set pindirs, 0 side 0 - nop side 1 -lp2: - in pins, 1 side 0 - jmp y-- lp2 side 1 -public end: - -.program spi_gap010_sample1 -.side_set 1 - -; always transmit multiple of 32 bytes -lp: out pins, 1 side 0 - jmp x-- lp side 1 -public lp1_end: - set pindirs, 0 side 0 - nop side 1 - nop side 0 -lp2: - in pins, 1 side 1 - jmp y-- lp2 side 0 -public end: - -.program spi_gap0_sample1_regular -.side_set 1 - -; always transmit multiple of 32 bytes -lp: out pins, 1 side 0 - jmp x-- lp side 1 -public lp1_end: - set pindirs, 0 side 0 -lp2: - in pins, 1 side 1 - jmp y-- lp2 side 0 -public end: - diff --git a/lib/main/pico-sdk/rp2_common/pico_cyw43_driver/cyw43_driver.c b/lib/main/pico-sdk/rp2_common/pico_cyw43_driver/cyw43_driver.c deleted file mode 100644 index 11d2652e00..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_cyw43_driver/cyw43_driver.c +++ /dev/null @@ -1,200 +0,0 @@ -/* - * Copyright (c) 2022 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "hardware/gpio.h" -#include "hardware/irq.h" -#include "pico/unique_id.h" -#include "cyw43.h" -#include "pico/cyw43_driver.h" -#include "pico/async_context.h" - -#ifndef CYW43_GPIO_IRQ_HANDLER_PRIORITY -#define CYW43_GPIO_IRQ_HANDLER_PRIORITY 0x40 -#endif - -#ifndef CYW43_SLEEP_CHECK_MS -#define CYW43_SLEEP_CHECK_MS 50 -#endif - -static async_context_t *cyw43_async_context; - -static void cyw43_sleep_timeout_reached(async_context_t *context, async_at_time_worker_t *worker); -static void cyw43_do_poll(async_context_t *context, async_when_pending_worker_t *worker); - -static async_at_time_worker_t sleep_timeout_worker = { - .do_work = cyw43_sleep_timeout_reached -}; - -static async_when_pending_worker_t cyw43_poll_worker = { - .do_work = cyw43_do_poll -}; - -static void cyw43_set_irq_enabled(bool enabled) { - gpio_set_irq_enabled(CYW43_PIN_WL_HOST_WAKE, GPIO_IRQ_LEVEL_HIGH, enabled); -} - -// GPIO interrupt handler to tell us there's cyw43 has work to do -static void cyw43_gpio_irq_handler(void) -{ - uint32_t events = gpio_get_irq_event_mask(CYW43_PIN_WL_HOST_WAKE); - if (events & GPIO_IRQ_LEVEL_HIGH) { - // As we use a high level interrupt, it will go off forever until it's serviced - // So disable the interrupt until this is done. It's re-enabled again by CYW43_POST_POLL_HOOK - // which is called at the end of cyw43_poll_func - cyw43_set_irq_enabled(false); - async_context_set_work_pending(cyw43_async_context, &cyw43_poll_worker); - } -} - -uint32_t cyw43_irq_init(__unused void *param) { -#ifndef NDEBUG - assert(get_core_num() == async_context_core_num(cyw43_async_context)); -#endif - gpio_add_raw_irq_handler_with_order_priority(CYW43_PIN_WL_HOST_WAKE, cyw43_gpio_irq_handler, CYW43_GPIO_IRQ_HANDLER_PRIORITY); - cyw43_set_irq_enabled(true); - irq_set_enabled(IO_IRQ_BANK0, true); - return 0; -} - -uint32_t cyw43_irq_deinit(__unused void *param) { -#ifndef NDEBUG - assert(get_core_num() == async_context_core_num(cyw43_async_context)); -#endif - gpio_remove_raw_irq_handler(CYW43_PIN_WL_HOST_WAKE, cyw43_gpio_irq_handler); - cyw43_set_irq_enabled(false); - return 0; -} - -void cyw43_post_poll_hook(void) { -#ifndef NDEBUG - assert(get_core_num() == async_context_core_num(cyw43_async_context)); -#endif - cyw43_set_irq_enabled(true); -} - -void cyw43_schedule_internal_poll_dispatch(__unused void (*func)(void)) { - assert(func == cyw43_poll); - async_context_set_work_pending(cyw43_async_context, &cyw43_poll_worker); -} - -static void cyw43_do_poll(async_context_t *context, __unused async_when_pending_worker_t *worker) { -#ifndef NDEBUG - assert(get_core_num() == async_context_core_num(cyw43_async_context)); -#endif - if (cyw43_poll) { - if (cyw43_sleep > 0) { - cyw43_sleep--; - } - cyw43_poll(); - if (cyw43_sleep) { - async_context_add_at_time_worker_in_ms(context, &sleep_timeout_worker, CYW43_SLEEP_CHECK_MS); - } else { - async_context_remove_at_time_worker(context, &sleep_timeout_worker); - } - } -} - -static void cyw43_sleep_timeout_reached(async_context_t *context, __unused async_at_time_worker_t *worker) { - assert(context == cyw43_async_context); - assert(worker == &sleep_timeout_worker); - async_context_set_work_pending(context, &cyw43_poll_worker); -} - -bool cyw43_driver_init(async_context_t *context) { - cyw43_init(&cyw43_state); - cyw43_async_context = context; - // we need the IRQ to be on the same core as the context, because we need to be able to enable/disable the IRQ - // from there later - async_context_execute_sync(context, cyw43_irq_init, NULL); - async_context_add_when_pending_worker(context, &cyw43_poll_worker); - return true; -} - -void cyw43_driver_deinit(async_context_t *context) { - assert(context == cyw43_async_context); - async_context_remove_at_time_worker(context, &sleep_timeout_worker); - async_context_remove_when_pending_worker(context, &cyw43_poll_worker); - // the IRQ IS on the same core as the context, so must be de-initialized there - async_context_execute_sync(context, cyw43_irq_deinit, NULL); - cyw43_deinit(&cyw43_state); - cyw43_async_context = NULL; -} - -// todo maybe add an #ifdef in cyw43_driver -uint32_t storage_read_blocks(__unused uint8_t *dest, __unused uint32_t block_num, __unused uint32_t num_blocks) { - // shouldn't be used - panic_unsupported(); -} - -// Generate a mac address if one is not set in otp -void __attribute__((weak)) cyw43_hal_generate_laa_mac(__unused int idx, uint8_t buf[6]) { - CYW43_DEBUG("Warning. No mac in otp. Generating mac from board id\n"); - pico_unique_board_id_t board_id; - pico_get_unique_board_id(&board_id); - memcpy(buf, &board_id.id[2], 6); - buf[0] &= (uint8_t)~0x1; // unicast - buf[0] |= 0x2; // locally administered -} - -// Return mac address -void cyw43_hal_get_mac(__unused int idx, uint8_t buf[6]) { - // The mac should come from cyw43 otp. - // This is loaded into the state after the driver is initialised - // cyw43_hal_generate_laa_mac is called by the driver to generate a mac if otp is not set - memcpy(buf, cyw43_state.mac, 6); -} - -// Prevent background processing in pensv and access by the other core -// These methods are called in pensv context and on either core -// They can be called recursively -void cyw43_thread_enter(void) { - async_context_acquire_lock_blocking(cyw43_async_context); -} - -void cyw43_thread_exit(void) { - async_context_release_lock(cyw43_async_context); -} - -#ifndef NDEBUG -void cyw43_thread_lock_check(void) { - async_context_lock_check(cyw43_async_context); -} -#endif - -void cyw43_await_background_or_timeout_us(uint32_t timeout_us) { - if (__get_current_exception() > 0) { - async_context_wait_until(cyw43_async_context, make_timeout_time_us(timeout_us)); - return; - } - async_context_wait_for_work_until(cyw43_async_context, make_timeout_time_us(timeout_us)); -} - -void cyw43_delay_ms(uint32_t ms) { - async_context_wait_until(cyw43_async_context, make_timeout_time_ms(ms)); -} - -void cyw43_delay_us(uint32_t us) { - async_context_wait_until(cyw43_async_context, make_timeout_time_us(us)); -} - -#if !CYW43_LWIP -static void no_lwip_fail() { - panic("cyw43 has no ethernet interface"); -} -void __attribute__((weak)) cyw43_cb_tcpip_init(cyw43_t *self, int itf) { -} -void __attribute__((weak)) cyw43_cb_tcpip_deinit(cyw43_t *self, int itf) { -} -void __attribute__((weak)) cyw43_cb_tcpip_set_link_up(cyw43_t *self, int itf) { - no_lwip_fail(); -} -void __attribute__((weak)) cyw43_cb_tcpip_set_link_down(cyw43_t *self, int itf) { - no_lwip_fail(); -} -void __attribute__((weak)) cyw43_cb_process_ethernet(void *cb_data, int itf, size_t len, const uint8_t *buf) { - no_lwip_fail(); -} -#endif diff --git a/lib/main/pico-sdk/rp2_common/pico_cyw43_driver/include/cyw43_configport.h b/lib/main/pico-sdk/rp2_common/pico_cyw43_driver/include/cyw43_configport.h deleted file mode 100644 index 704871ee2e..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_cyw43_driver/include/cyw43_configport.h +++ /dev/null @@ -1,236 +0,0 @@ -/* - * Copyright (c) 2022 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -// This header is included by cyw43_driver to setup its environment - -#ifndef _CYW43_CONFIGPORT_H -#define _CYW43_CONFIGPORT_H - -#include "pico.h" -#include "hardware/gpio.h" -#include "pico/time.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#ifndef CYW43_HOST_NAME -#define CYW43_HOST_NAME "PicoW" -#endif - -#ifndef CYW43_GPIO -#define CYW43_GPIO 1 -#endif - -#ifndef CYW43_LOGIC_DEBUG -#define CYW43_LOGIC_DEBUG 0 -#endif - -#ifndef CYW43_USE_OTP_MAC -#define CYW43_USE_OTP_MAC 1 -#endif - -#ifndef CYW43_NO_NETUTILS -#define CYW43_NO_NETUTILS 1 -#endif - -#ifndef CYW43_IOCTL_TIMEOUT_US -#define CYW43_IOCTL_TIMEOUT_US 1000000 -#endif - -#ifndef CYW43_USE_STATS -#define CYW43_USE_STATS 0 -#endif - -// todo should this be user settable? -#ifndef CYW43_HAL_MAC_WLAN0 -#define CYW43_HAL_MAC_WLAN0 0 -#endif - -#ifndef STATIC -#define STATIC static -#endif - -#ifndef CYW43_USE_SPI -#define CYW43_USE_SPI 1 -#endif - -#ifndef CYW43_SPI_PIO -#define CYW43_SPI_PIO 1 -#endif - -#ifndef CYW43_CHIPSET_FIRMWARE_INCLUDE_FILE -#if CYW43_ENABLE_BLUETOOTH -#define CYW43_CHIPSET_FIRMWARE_INCLUDE_FILE "wb43439A0_7_95_49_00_combined.h" -#else -#define CYW43_CHIPSET_FIRMWARE_INCLUDE_FILE "w43439A0_7_95_49_00_combined.h" -#endif -#endif - -#ifndef CYW43_WIFI_NVRAM_INCLUDE_FILE -#define CYW43_WIFI_NVRAM_INCLUDE_FILE "wifi_nvram_43439.h" -#endif - -// Note, these are negated, because cyw43_driver negates them before returning! -#define CYW43_EPERM (-PICO_ERROR_NOT_PERMITTED) // Operation not permitted -#define CYW43_EIO (-PICO_ERROR_IO) // I/O error -#define CYW43_EINVAL (-PICO_ERROR_INVALID_ARG) // Invalid argument -#define CYW43_ETIMEDOUT (-PICO_ERROR_TIMEOUT) // Connection timed out - -#ifndef CYW43_WL_GPIO_COUNT -#define CYW43_WL_GPIO_COUNT 3 -#endif - -#define CYW43_NUM_GPIOS CYW43_WL_GPIO_COUNT - -#define cyw43_hal_pin_obj_t uint - -// get the number of elements in a fixed-size array -#define CYW43_ARRAY_SIZE(a) count_of(a) - -static inline uint32_t cyw43_hal_ticks_us(void) { - return time_us_32(); -} - -static inline uint32_t cyw43_hal_ticks_ms(void) { - return to_ms_since_boot(get_absolute_time()); -} - -// PICO_CONFIG: CYW43_DEFAULT_PIN_WL_REG_ON, gpio pin to power up the cyw43 chip, type=int, default=23, advanced=true, group=pico_cyw43_driver -#ifndef CYW43_DEFAULT_PIN_WL_REG_ON -#define CYW43_DEFAULT_PIN_WL_REG_ON 23 -#endif -// PICO_CONFIG: CYW43_DEFAULT_PIN_WL_DATA_OUT, gpio pin for spi data out to the cyw43 chip, type=int, default=24, advanced=true, group=pico_cyw43_driver -#ifndef CYW43_DEFAULT_PIN_WL_DATA_OUT -#define CYW43_DEFAULT_PIN_WL_DATA_OUT 24u -#endif -// PICO_CONFIG: CYW43_DEFAULT_PIN_WL_DATA_IN, gpio pin for spi data in from the cyw43 chip, type=int, default=24, advanced=true, group=pico_cyw43_driver -#ifndef CYW43_DEFAULT_PIN_WL_DATA_IN -#define CYW43_DEFAULT_PIN_WL_DATA_IN 24u -#endif -// PICO_CONFIG: CYW43_DEFAULT_PIN_WL_HOST_WAKE, gpio (irq) pin for the irq line from the cyw43 chip, type=int, default=24, advanced=true, group=pico_cyw43_driver -#ifndef CYW43_DEFAULT_PIN_WL_HOST_WAKE -#define CYW43_DEFAULT_PIN_WL_HOST_WAKE 24u -#endif -// PICO_CONFIG: CYW43_DEFAULT_PIN_WL_CLOCK, gpio pin for the spi clock line to the cyw43 chip, type=int, default=29, advanced=true, group=pico_cyw43_driver -#ifndef CYW43_DEFAULT_PIN_WL_CLOCK -#define CYW43_DEFAULT_PIN_WL_CLOCK 29u -#endif -// PICO_CONFIG: CYW43_DEFAULT_PIN_WL_CS, gpio pin for the spi chip select to the cyw43 chip, type=int, default=25, advanced=true, group=pico_cyw43_driver -#ifndef CYW43_DEFAULT_PIN_WL_CS -#define CYW43_DEFAULT_PIN_WL_CS 25u -#endif - -// PICO_CONFIG: CYW43_PIN_WL_DYNAMIC, flag to indicate if cyw43 SPI pins can be changed at runtime, type=bool, default=false, advanced=true, group=pico_cyw43_driver -#ifndef CYW43_PIN_WL_DYNAMIC -#define CYW43_PIN_WL_DYNAMIC 0 -#endif - -#if CYW43_PIN_WL_DYNAMIC -// these are just an index into an array -typedef enum cyw43_pin_index_t { - CYW43_PIN_INDEX_WL_REG_ON, - CYW43_PIN_INDEX_WL_DATA_OUT, - CYW43_PIN_INDEX_WL_DATA_IN, - CYW43_PIN_INDEX_WL_HOST_WAKE, - CYW43_PIN_INDEX_WL_CLOCK, - CYW43_PIN_INDEX_WL_CS, - CYW43_PIN_INDEX_WL_COUNT // last -} cyw43_pin_index_t; -#define CYW43_PIN_WL_REG_ON cyw43_get_pin_wl(CYW43_PIN_INDEX_WL_REG_ON) -#define CYW43_PIN_WL_DATA_OUT cyw43_get_pin_wl(CYW43_PIN_INDEX_WL_DATA_OUT) -#define CYW43_PIN_WL_DATA_IN cyw43_get_pin_wl(CYW43_PIN_INDEX_WL_DATA_IN) -#define CYW43_PIN_WL_HOST_WAKE cyw43_get_pin_wl(CYW43_PIN_INDEX_WL_HOST_WAKE) -#define CYW43_PIN_WL_CLOCK cyw43_get_pin_wl(CYW43_PIN_INDEX_WL_CLOCK) -#define CYW43_PIN_WL_CS cyw43_get_pin_wl(CYW43_PIN_INDEX_WL_CS) -// Lookup the gpio value in an array -uint cyw43_get_pin_wl(cyw43_pin_index_t pin_id); -#else -// Just return the gpio number configured at build time -#define CYW43_PIN_WL_REG_ON CYW43_DEFAULT_PIN_WL_REG_ON -#define CYW43_PIN_WL_DATA_OUT CYW43_DEFAULT_PIN_WL_DATA_OUT -#define CYW43_PIN_WL_DATA_IN CYW43_DEFAULT_PIN_WL_DATA_IN -#define CYW43_PIN_WL_HOST_WAKE CYW43_DEFAULT_PIN_WL_HOST_WAKE -#define CYW43_PIN_WL_CLOCK CYW43_DEFAULT_PIN_WL_CLOCK -#define CYW43_PIN_WL_CS CYW43_DEFAULT_PIN_WL_CS -#endif // !CYW43_PIN_WL_DYNAMIC - -static inline int cyw43_hal_pin_read(cyw43_hal_pin_obj_t pin) { - return gpio_get(pin); -} - -static inline void cyw43_hal_pin_low(cyw43_hal_pin_obj_t pin) { - gpio_put(pin, false); -} - -static inline void cyw43_hal_pin_high(cyw43_hal_pin_obj_t pin) { - gpio_put(pin, true); -} - -#define CYW43_HAL_PIN_MODE_INPUT (GPIO_IN) -#define CYW43_HAL_PIN_MODE_OUTPUT (GPIO_OUT) - -#define CYW43_HAL_PIN_PULL_NONE (0) -#define CYW43_HAL_PIN_PULL_UP (1) -#define CYW43_HAL_PIN_PULL_DOWN (2) - -static inline void cyw43_hal_pin_config(cyw43_hal_pin_obj_t pin, uint32_t mode, uint32_t pull, __unused uint32_t alt) { - assert((mode == CYW43_HAL_PIN_MODE_INPUT || mode == CYW43_HAL_PIN_MODE_OUTPUT) && alt == 0); - gpio_set_dir(pin, mode); - gpio_set_pulls(pin, pull == CYW43_HAL_PIN_PULL_UP, pull == CYW43_HAL_PIN_PULL_DOWN); -} - -void cyw43_hal_get_mac(int idx, uint8_t buf[6]); - -void cyw43_hal_generate_laa_mac(int idx, uint8_t buf[6]); - - -void cyw43_thread_enter(void); - -void cyw43_thread_exit(void); - -#define CYW43_THREAD_ENTER cyw43_thread_enter(); -#define CYW43_THREAD_EXIT cyw43_thread_exit(); -#ifndef NDEBUG - -void cyw43_thread_lock_check(void); - -#define cyw43_arch_lwip_check() cyw43_thread_lock_check() -#define CYW43_THREAD_LOCK_CHECK cyw43_arch_lwip_check(); -#else -#define cyw43_arch_lwip_check() ((void)0) -#define CYW43_THREAD_LOCK_CHECK -#endif - -void cyw43_await_background_or_timeout_us(uint32_t timeout_us); -// todo not 100% sure about the timeouts here; MP uses __WFI which will always wakeup periodically -#define CYW43_SDPCM_SEND_COMMON_WAIT cyw43_await_background_or_timeout_us(1000); -#define CYW43_DO_IOCTL_WAIT cyw43_await_background_or_timeout_us(1000); - -void cyw43_delay_ms(uint32_t ms); - -void cyw43_delay_us(uint32_t us); - -void cyw43_schedule_internal_poll_dispatch(void (*func)(void)); - -void cyw43_post_poll_hook(void); - -#define CYW43_POST_POLL_HOOK cyw43_post_poll_hook(); - -// Allow malloc and free to be changed -#ifndef cyw43_malloc -#define cyw43_malloc malloc -#endif -#ifndef cyw43_free -#define cyw43_free free -#endif - -#ifdef __cplusplus -} -#endif - - -#endif \ No newline at end of file diff --git a/lib/main/pico-sdk/rp2_common/pico_cyw43_driver/include/pico/btstack_chipset_cyw43.h b/lib/main/pico-sdk/rp2_common/pico_cyw43_driver/include/pico/btstack_chipset_cyw43.h deleted file mode 100644 index 037b68ddfe..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_cyw43_driver/include/pico/btstack_chipset_cyw43.h +++ /dev/null @@ -1,18 +0,0 @@ -/* - * Copyright (c) 2023 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _PICO_BTSTACK_CHIPSET_CYW43_H -#define _PICO_BTSTACK_CHIPSET_CYW43_H - -#include "btstack_chipset.h" - -/** - * \brief Return the singleton BTstack chipset CY43 API instance - * \ingroup pico_btstack - */ -const btstack_chipset_t * btstack_chipset_cyw43_instance(void); - -#endif diff --git a/lib/main/pico-sdk/rp2_common/pico_cyw43_driver/include/pico/btstack_cyw43.h b/lib/main/pico-sdk/rp2_common/pico_cyw43_driver/include/pico/btstack_cyw43.h deleted file mode 100644 index 37d3648b7e..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_cyw43_driver/include/pico/btstack_cyw43.h +++ /dev/null @@ -1,44 +0,0 @@ -/* - * Copyright (c) 2023 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _PICO_BTSTACK_CYW43_H -#define _PICO_BTSTACK_CYW43_H - -#include "pico/async_context.h" -#ifdef __cplusplus -extern "C" { -#endif - -/** \file pico/btstack_cyw43.h - * \defgroup pico_btstack_cyw43 pico_btstack_cyw43 - * \ingroup pico_cyw43_driver - * - * \brief Low-level Bluetooth HCI support - * - * This library provides utility functions to initialise and de-initialise BTstack for CYW43, -*/ - -/* - * \brief Perform initialisation of BTstack/CYW43 integration - * \ingroup pico_btstack_cyw43 - * - * \param context the async_context instance that provides the abstraction for handling asynchronous work. - * \return true on success or false an error - */ -bool btstack_cyw43_init(async_context_t *context); - -/* - * \brief De-initialise BTstack/CYW43 integration - * \ingroup pico_btstack_cyw43 - * - * \param context the async_context the btstack_cyw43 support was added to via \ref btstack_cyw43_init - */ -void btstack_cyw43_deinit(async_context_t *context); - -#ifdef __cplusplus -} -#endif -#endif diff --git a/lib/main/pico-sdk/rp2_common/pico_cyw43_driver/include/pico/btstack_hci_transport_cyw43.h b/lib/main/pico-sdk/rp2_common/pico_cyw43_driver/include/pico/btstack_hci_transport_cyw43.h deleted file mode 100644 index e025858bb5..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_cyw43_driver/include/pico/btstack_hci_transport_cyw43.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * Copyright (c) 2023 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _PICO_BTSTACK_HCI_TRANSPORT_CYW43_H -#define _PICO_BTSTACK_HCI_TRANSPORT_CYW43_H - -#ifdef __cplusplus -extern "C" { -#endif - -/** \file pico/btstack_hci_transport_cyw43.h -* \ingroup pico_cyw43_driver -* \brief Adds low level Bluetooth HCI support -*/ - -/** - * \brief Get the Bluetooth HCI transport instance for cyw43 - * \ingroup pico_cyw43_driver - * - * \return An instantiation of the hci_transport_t interface for the cyw43 chipset - */ -const hci_transport_t *hci_transport_cyw43_instance(void); - -#ifdef __cplusplus -} -#endif - -#endif // HCI_TRANSPORT_CYW43_H diff --git a/lib/main/pico-sdk/rp2_common/pico_cyw43_driver/include/pico/cyw43_driver.h b/lib/main/pico-sdk/rp2_common/pico_cyw43_driver/include/pico/cyw43_driver.h deleted file mode 100644 index 633c7ad1f0..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_cyw43_driver/include/pico/cyw43_driver.h +++ /dev/null @@ -1,98 +0,0 @@ -/* - * Copyright (c) 2022 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _PICO_CYW43_DRIVER_H -#define _PICO_CYW43_DRIVER_H - -/** \file pico/cyw43_driver.h - * \defgroup pico_cyw43_driver pico_cyw43_driver - * - * \brief A wrapper around the lower level cyw43_driver, that integrates it with \ref pico_async_context - * for handling background work - */ - -#include "pico.h" - -#if CYW43_PIN_WL_DYNAMIC -#include "cyw43_configport.h" -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -struct async_context; - -/*! \brief Initializes the lower level cyw43_driver and integrates it with the provided async_context - * \ingroup pico_cyw43_driver - * - * If the initialization succeeds, \ref lwip_nosys_deinit() can be called to shutdown lwIP support - * - * \param context the async_context instance that provides the abstraction for handling asynchronous work. - * \return true if the initialization succeeded -*/ -bool cyw43_driver_init(struct async_context *context); - -/*! \brief De-initialize the lowever level cyw43_driver and unhooks it from the async_context - * \ingroup pico_cyw43_driver - * - * \param context the async_context the cyw43_driver support was added to via \ref cyw43_driver_init -*/ -void cyw43_driver_deinit(struct async_context *context); - -// PICO_CONFIG: CYW43_PIO_CLOCK_DIV_DYNAMIC, Enable runtime configuration of the clock divider for communication with the wireless chip, type=bool, default=0, group=pico_cyw43_driver -#ifndef CYW43_PIO_CLOCK_DIV_DYNAMIC -#define CYW43_PIO_CLOCK_DIV_DYNAMIC 0 -#endif - -// PICO_CONFIG: CYW43_PIO_CLOCK_DIV_INT, Integer part of the clock divider for communication with the wireless chip, type=bool, default=2, group=pico_cyw43_driver -#ifndef CYW43_PIO_CLOCK_DIV_INT -// backwards compatibility using old define -#ifdef CYW43_PIO_CLOCK_DIV -#define CYW43_PIO_CLOCK_DIV_INT CYW43_PIO_CLOCK_DIV -#else -#define CYW43_PIO_CLOCK_DIV_INT 2 -#endif -#endif - -// PICO_CONFIG: CYW43_PIO_CLOCK_DIV_FRAC, Fractional part of the clock divider for communication with the wireless chip, type=bool, default=0, group=pico_cyw43_driver -#ifndef CYW43_PIO_CLOCK_DIV_FRAC -#define CYW43_PIO_CLOCK_DIV_FRAC 0 -#endif - -#if CYW43_PIO_CLOCK_DIV_DYNAMIC -/*! \brief Set the clock divisor for the cyw43 pio clock - * \ingroup pico_cyw43_driver - * - * SPI is used to communicate with the CYW43 device and this is implemented using a PIO running with a divisor of 2. - * If the system clock is changed it may be necessary to adjust for this to allow communications to succeed. - * This function is only available if \ref CYW43_PIO_CLOCK_DIV_DYNAMIC is true - * - * \param clock_div_int Integer part of the divisor - * \param clock_div_frac Fractional part in 1/256ths -*/ -void cyw43_set_pio_clock_divisor(uint16_t clock_div_int, uint8_t clock_div_frac); -#endif - -#if CYW43_PIN_WL_DYNAMIC -/*! \brief Set the gpio pins for the communication with the cyw43 device - * \ingroup pico_cyw43_driver - * - * Set or change the pins used to communicate with the cyw43 device - * This function is only available if \ref CYW43_PIN_WL_DYNAMIC is true - * - * \note The cyw43 driver should not be de-initialised before this function is called or else the behaviour is undefined. - * - * \param pins An array containing the gpio pins to use - * \return PICO_OK if the pin configuration could be changed and is valid -*/ -int cyw43_set_pins_wl(uint pins[CYW43_PIN_INDEX_WL_COUNT]); -#endif - -#ifdef __cplusplus -} -#endif -#endif \ No newline at end of file diff --git a/lib/main/pico-sdk/rp2_common/pico_divider/divider_compiler.c b/lib/main/pico-sdk/rp2_common/pico_divider/divider_compiler.c deleted file mode 100644 index 82e43390ab..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_divider/divider_compiler.c +++ /dev/null @@ -1,116 +0,0 @@ -/* - * Copyright (c) 2023 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "pico/divider.h" - -// These functions save/restore divider state, so are safe to call from interrupts -int32_t div_s32s32(int32_t a, int32_t b) { - return hw_divider_quotient_s32(a, b); -} - -divmod_result_t divmod_s32s32(int32_t a, int32_t b) { - return hw_divider_divmod_s32(a, b); -} - -uint32_t div_u32u32(uint32_t a, uint32_t b) { - return hw_divider_u32_quotient(a, b); -} - -divmod_result_t divmod_u32u32(uint32_t a, uint32_t b) { - return hw_divider_divmod_u32(a, b); -} - -static inline int __sign_of_64(int64_t v) { - return v > 0 ? 1 : (v < 0 ? -1 : 0); -} - -typedef struct { - uint64_t quotient; - uint64_t remainder; -} qr_u64; - -typedef struct { - int64_t quotient; - int64_t remainder; -} qr_s64; - -// divides unsigned values a by b... (a/b) returned in low 32 bits, (a%b) in high 32 bits... results undefined for b==0 -static inline qr_u64 udiv64(uint64_t a, uint64_t b) { - qr_u64 rc; - if (!b) { - rc.quotient = (uint64_t)-1; // todo check this - rc.remainder = a; - } else { - rc.quotient = a/b; - rc.remainder = a%b; - } - return rc; -} - -// divides signed values a by b... (a/b) returned in low 32 bits, (a%b) in high 32 bits... results undefined for b==0 -static inline qr_s64 div64(int64_t a, int64_t b) { - qr_s64 rc; - if (!b) { - rc.quotient = (uint64_t)(-__sign_of_64(a)); - rc.remainder = a; - } else { - rc.quotient = a/b; - rc.remainder = a%b; - } - return rc; -} - -int64_t div_s64s64(int64_t a, int64_t b) { - qr_s64 qr = div64(a, b); - return qr.quotient; -} - -int64_t divmod_s64s64_rem(int64_t a, int64_t b, int64_t *rem) { - qr_s64 qr = div64(a, b); - *rem = qr.remainder; - return qr.quotient; -} - -int64_t divmod_s64s64(int64_t a, int64_t b) { - qr_s64 qr = div64(a, b); - return qr.quotient; -} - -uint64_t div_u64u64(uint64_t a, uint64_t b) { - qr_u64 qr = udiv64(a, b); - return qr.quotient; -} - -uint64_t divmod_u64u64_rem(uint64_t a, uint64_t b, uint64_t *rem) { - qr_u64 qr = udiv64(a, b); - *rem = qr.remainder; - return qr.quotient; -} - -uint64_t divmod_u64u64(uint64_t a, uint64_t b) { - qr_u64 qr = udiv64(a, b); - return qr.quotient; -} - -// these functions are slightly faster, but unsafe the divider state, so are not generally safe to be called from interrupts - -int32_t div_s32s32_unsafe(int32_t a, int32_t b) { return div_s32s32(a,b); } -int32_t divmod_s32s32_rem_unsafe(int32_t a, int32_t b, int32_t *rem) { return divmod_s32s32_rem(a, b, rem); } -divmod_result_t divmod_s32s32_unsafe(int32_t a, int32_t b) { return divmod_s32s32(a, b); } - -uint32_t div_u32u32_unsafe(uint32_t a, uint32_t b) { return div_u32u32(a, b); } -uint32_t divmod_u32u32_rem_unsafe(uint32_t a, uint32_t b, uint32_t *rem) { return divmod_u32u32_rem(a, b, rem); } -divmod_result_t divmod_u32u32_unsafe(uint32_t a, uint32_t b) { return divmod_u32u32(a, b); } - -int64_t div_s64s64_unsafe(int64_t a, int64_t b) { return div_s64s64(a, b); } -int64_t divmod_s64s64_rem_unsafe(int64_t a, int64_t b, int64_t *rem) { return divmod_s64s64_rem(a, b, rem); } -// todo this doesn't implement the contract -//int64_t divmod_s64s64_unsafe(int64_t a, int64_t b) { return divmod_s64s64(a, b); } - -uint64_t div_u64u64_unsafe(uint64_t a, uint64_t b) { return div_u64u64(a, b); } -uint64_t divmod_u64u64_rem_unsafe(uint64_t a, uint64_t b, uint64_t *rem) { return divmod_u64u64_rem(a, b, rem); } -// todo this doesn't implement the contract -//uint64_t divmod_u64u64_unsafe(uint64_t a, uint64_t b) { return divmod_u64u64(a, b); } diff --git a/lib/main/pico-sdk/rp2_common/pico_divider/divider_hardware.S b/lib/main/pico-sdk/rp2_common/pico_divider/divider_hardware.S deleted file mode 100644 index cb3f541629..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_divider/divider_hardware.S +++ /dev/null @@ -1,877 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "pico/asm_helper.S" -#include "hardware/regs/addressmap.h" -#include "hardware/divider_helper.S" - -#if !HAS_SIO_DIVIDER -#warning "Building divider_hardware.S on a platform with no SIO divider hardware" -#endif - -// PICO_CONFIG: PICO_DIVIDER_DISABLE_INTERRUPTS, Disable interrupts around division such that divider state need not be saved/restored in exception handlers, default=0, group=pico_divider - -// PICO_CONFIG: PICO_DIVIDER_CALL_IDIV0, Whether 32 bit division by zero should call __aeabi_idiv0, default=1, group=pico_divider -#ifndef PICO_DIVIDER_CALL_IDIV0 -#define PICO_DIVIDER_CALL_IDIV0 1 -#endif - -// PICO_CONFIG: PICO_DIVIDER_CALL_IDIV0, Whether 64 bit division by zero should call __aeabi_ldiv0, default=1, group=pico_divider -#ifndef PICO_DIVIDER_CALL_LDIV0 -#define PICO_DIVIDER_CALL_LDIV0 1 -#endif - -pico_default_asm_setup - -// PICO_CONFIG: PICO_DIVIDER_IN_RAM, Whether divider functions should be placed in RAM, default=0, group=pico_divider -.macro div_section name -#if PICO_DIVIDER_IN_RAM -.section RAM_SECTION_NAME(\name), "ax" -#else -.section SECTION_NAME(\name), "ax" -#endif -.endm - -@ wait 8-n cycles for the hardware divider -.macro wait_div n -.rept (8-\n) / 2 - b 9f -9: -.endr -.if (8-\n) % 2 - nop -.endif -.endm - -#if (SIO_DIV_SDIVISOR_OFFSET != SIO_DIV_SDIVIDEND_OFFSET + 4) || (SIO_DIV_QUOTIENT_OFFSET != SIO_DIV_SDIVISOR_OFFSET + 4) || (SIO_DIV_REMAINDER_OFFSET != SIO_DIV_QUOTIENT_OFFSET + 4) -#error register layout has changed - we rely on this order to make sure we save/restore in the right order -#endif - -#if !PICO_DIVIDER_DISABLE_INTERRUPTS -.macro save_div_state_and_lr_64 - push {r4, r5, r6, r7, lr} - ldr r6, =SIO_BASE - // note we must read quotient last, and since it isn't the last reg, we'll not use ldmia! - ldr r4, [r6, #SIO_DIV_UDIVIDEND_OFFSET] - ldr r5, [r6, #SIO_DIV_UDIVISOR_OFFSET] - // No need to wait before reading result as long as preceding code takes more than 8 cycles - ldr r7, [r6, #SIO_DIV_REMAINDER_OFFSET] - ldr r6, [r6, #SIO_DIV_QUOTIENT_OFFSET] -.endm - -.macro restore_div_state_and_return_64 - // writing sdividend (r4), sdivisor (r5), quotient (r6), remainder (r7) in that order - // - // it is worth considering what happens if we are interrupted - // - // after writing r4: we are DIRTY and !READY - // ... interruptor using div will complete based on incorrect inputs, but dividend at least will be - // saved/restored correctly and we'll restore the rest ourselves - // after writing r4, r5: we are DIRTY and !READY - // ... interruptor using div will complete based on possibly wrongly signed inputs, but dividend, divisor - // at least will be saved/restored correctly and and we'll restore the rest ourselves - // after writing r4, r5, r6: we are DIRTY and READY - // ... interruptor using div will dividend, divisor, quotient registers as is (what we just restored ourselves), - // and we'll restore the remainder after the fact - - mov ip, r2 - ldr r2, =SIO_BASE - // note we are not use STM not because it can be restarted due to interrupt which is harmless, more because this is 1 cycle IO space - // and so 4 reads is cheaper (and we don't have to adjust r2) - str r4, [r2, #SIO_DIV_UDIVIDEND_OFFSET] - str r5, [r2, #SIO_DIV_UDIVISOR_OFFSET] - str r7, [r2, #SIO_DIV_REMAINDER_OFFSET] - str r6, [r2, #SIO_DIV_QUOTIENT_OFFSET] - mov r2, ip - pop {r4, r5, r6, r7, pc} -.endm - -#endif /* !PICO_DIVIDER_DISABLE_INTERRUPTS */ - -// since idiv and idivmod only differ by a cycle, we'll make them the same! -div_section WRAPPER_FUNC_NAME(__aeabi_idiv) -.align 2 -wrapper_func __aeabi_idiv -wrapper_func __aeabi_idivmod -regular_func div_s32s32 -regular_func divmod_s32s32 -#if !PICO_DIVIDER_DISABLE_INTERRUPTS - // to support IRQ usage (or context switch) we must save/restore divider state around call if state is dirty - ldr r2, =SIO_BASE - ldr r3, [r2, #SIO_DIV_CSR_OFFSET] - lsrs r3, #SIO_DIV_CSR_DIRTY_SHIFT_FOR_CARRY - bcs divmod_s32s32_savestate -regular_func divmod_s32s32_unsafe -#else -// to avoid too much source code spaghetti with restoring interrupts, we make this the same as the other funcs -// in the PICO_DIVIDER_DISABLE_INTERRUPTS case; i.e. it is not a faster function; this seems reasonable as there -// are the hardware_divider functions that can be used instead anyway -regular_func divmod_s32s32_unsafe - // to avoid worrying about IRQs (or context switches), simply disable interrupts around call - ldr r2, =SIO_BASE - mrs r3, PRIMASK - cpsid i -#endif /* !PICO_DIVIDER_DISABLE_INTERRUPTS */ - str r0, [r2, #SIO_DIV_SDIVIDEND_OFFSET] - str r1, [r2, #SIO_DIV_SDIVISOR_OFFSET] - cmp r1, #0 - beq 1f - wait_div 2 - // return 64 bit value so we can efficiently return both (note read order is important since QUOTIENT must be read last) - ldr r1, [r2, #SIO_DIV_REMAINDER_OFFSET] - ldr r0, [r2, #SIO_DIV_QUOTIENT_OFFSET] -#if PICO_DIVIDER_DISABLE_INTERRUPTS - msr PRIMASK, r3 -#endif /* PICO_DIVIDER_DISABLE_INTERRUPTS */ - bx lr -1: -#if PICO_DIVIDER_DISABLE_INTERRUPTS - msr PRIMASK, r3 -#endif /* PICO_DIVIDER_DISABLE_INTERRUPTS */ - push {r2, lr} - movs r1, #0x80 - lsls r1, #24 - asrs r2, r0, #31 - eors r1, r2 - cmp r0, #0 - beq 1f - mvns r0, r1 -1: -#if PICO_DIVIDER_CALL_IDIV0 - bl __aeabi_idiv0 -#endif - movs r1, #0 // remainder 0 - // need to restore saved r2 as it hold SIO ptr - pop {r2, pc} -#if !PICO_DIVIDER_DISABLE_INTERRUPTS -.align 2 -regular_func divmod_s32s32_savestate - save_div_state_and_lr - bl divmod_s32s32_unsafe - restore_div_state_and_return -#endif /* !PICO_DIVIDER_DISABLE_INTERRUPTS */ - -// since uidiv and uidivmod only differ by a cycle, we'll make them the same! -div_section WRAPPER_FUNC_NAME(__aeabi_uidiv) -regular_func div_u32u32 -regular_func divmod_u32u32 -wrapper_func __aeabi_uidiv -wrapper_func __aeabi_uidivmod -#if !PICO_DIVIDER_DISABLE_INTERRUPTS - // to support IRQ usage (or context switch) we must save/restore divider state around call if state is dirty - ldr r2, =SIO_BASE - ldr r3, [r2, #SIO_DIV_CSR_OFFSET] - lsrs r3, #SIO_DIV_CSR_DIRTY_SHIFT_FOR_CARRY - bcs divmod_u32u32_savestate -regular_func divmod_u32u32_unsafe -#else -// to avoid too much source code spaghetti with restoring interrupts, we make this the same as the other funcs -// in the PICO_DIVIDER_DISABLE_INTERRUPTS case; i.e. it is not a faster function; this seems reasonable as there -// are the hardware_divider functions that can be used instead anyway -regular_func divmod_u32u32_unsafe - // to avoid worrying about IRQs (or context switches), simply disable interrupts around call - ldr r2, =SIO_BASE - mrs r3, PRIMASK - cpsid i -#endif /* !PICO_DIVIDER_DISABLE_INTERRUPTS */ - str r0, [r2, #SIO_DIV_UDIVIDEND_OFFSET] - str r1, [r2, #SIO_DIV_UDIVISOR_OFFSET] - cmp r1, #0 - beq 1f - wait_div 2 - // return 64 bit value so we can efficiently return both (note read order is important since QUOTIENT must be read last) - ldr r1, [r2, #SIO_DIV_REMAINDER_OFFSET] - ldr r0, [r2, #SIO_DIV_QUOTIENT_OFFSET] -#if PICO_DIVIDER_DISABLE_INTERRUPTS - msr PRIMASK, r3 -#endif /* PICO_DIVIDER_DISABLE_INTERRUPTS */ - bx lr -1: -#if PICO_DIVIDER_DISABLE_INTERRUPTS - msr PRIMASK, r3 -#endif /* PICO_DIVIDER_DISABLE_INTERRUPTS */ - push {r2, lr} - cmp r0, #0 - beq 1f - movs r0, #0 - mvns r0, r0 -1: -#if PICO_DIVIDER_CALL_IDIV0 - bl __aeabi_idiv0 -#endif - movs r1, #0 // remainder 0 - // need to restore saved r2 as it hold SIO ptr - pop {r2, pc} -#if !PICO_DIVIDER_DISABLE_INTERRUPTS -.align 2 -regular_func divmod_u32u32_savestate - save_div_state_and_lr - bl divmod_u32u32_unsafe - restore_div_state_and_return -#endif /* !PICO_DIVIDER_DISABLE_INTERRUPTS */ - -div_section WRAPPER_FUNC_NAME(__aeabi_ldiv) - -.align 2 -wrapper_func __aeabi_ldivmod -regular_func div_s64s64 -regular_func divmod_s64s64 -#if !PICO_DIVIDER_DISABLE_INTERRUPTS - // to support IRQ usage (or context switch) we must save/restore divider state around call if state is dirty - mov ip, r2 - ldr r2, =SIO_BASE - ldr r2, [r2, #SIO_DIV_CSR_OFFSET] - lsrs r2, #SIO_DIV_CSR_DIRTY_SHIFT_FOR_CARRY - mov r2, ip - bcs divmod_s64s64_savestate - b divmod_s64s64_unsafe -.align 2 -divmod_s64s64_savestate: - save_div_state_and_lr_64 - bl divmod_s64s64_unsafe - restore_div_state_and_return_64 -#else - // to avoid worrying about IRQs (or context switches), simply disable interrupts around call - push {r4, lr} - mrs r4, PRIMASK - cpsid i - bl divmod_s64s64_unsafe - msr PRIMASK, r4 - pop {r4, pc} -#endif /* !PICO_DIVIDER_DISABLE_INTERRUPTS */ - -.align 2 -wrapper_func __aeabi_uldivmod -regular_func div_u64u64 -regular_func divmod_u64u64 -#if !PICO_DIVIDER_DISABLE_INTERRUPTS - // to support IRQ usage (or context switch) we must save/restore divider state around call if state is dirty - mov ip, r2 - ldr r2, =SIO_BASE - ldr r2, [r2, #SIO_DIV_CSR_OFFSET] - lsrs r2, #SIO_DIV_CSR_DIRTY_SHIFT_FOR_CARRY - mov r2, ip - bcs divmod_u64u64_savestate - b divmod_u64u64_unsafe -.align 2 -regular_func divmod_u64u64_savestate - save_div_state_and_lr_64 - bl divmod_u64u64_unsafe - restore_div_state_and_return_64 -#else - // to avoid worrying about IRQs (or context switches), simply disable interrupts around call - push {r4, lr} - mrs r4, PRIMASK - cpsid i - bl divmod_u64u64_unsafe - msr PRIMASK, r4 - pop {r4, pc} -#endif /* !PICO_DIVIDER_DISABLE_INTERRUPTS */ - -.macro dneg lo,hi - mvns \hi,\hi - negs \lo,\lo - bne l\@_1 - adds \hi,#1 -l\@_1: -.endm - -.align 2 -regular_func divmod_s64s64_unsafe - cmp r3,#0 - blt 1f -@ here x +ve - beq 2f @ could x be zero? -3: - cmp r1,#0 - bge divmod_u64u64_unsafe @ both positive -@ y -ve, x +ve - push {r14} - dneg r0,r1 - bl divmod_u64u64_unsafe - dneg r0,r1 - dneg r2,r3 - pop {r15} - -2: - cmp r2,#0 - bne 3b @ back if x not zero - - cmp r0,#0 @ y==0? - bne 4f - cmp r1,#0 - beq 5f @ then pass 0 to __aeabi_ldiv0 -4: - movs r0,#0 - lsrs r1,#31 - lsls r1,#31 @ get sign bit - bne 5f @ y -ve? pass -2^63 to __aeabi_ldiv0 - mvns r0,r0 - lsrs r1,r0,#1 @ y +ve: pass 2^63-1 to __aeabi_ldiv0 -5: - push {r14} -#if PICO_DIVIDER_CALL_LDIV0 - bl __aeabi_ldiv0 -#endif - movs r2,#0 @ and return 0 for the remainder - movs r3,#0 - pop {r15} - -1: -@ here x -ve - push {r14} - cmp r1,#0 - blt 1f -@ y +ve, x -ve - dneg r2,r3 - bl divmod_u64u64_unsafe - dneg r0,r1 - pop {r15} - -1: -@ y -ve, x -ve - dneg r0,r1 - dneg r2,r3 - bl divmod_u64u64_unsafe - dneg r2,r3 - pop {r15} - -regular_func divmod_u64u64_unsafe - cmp r1,#0 - bne y64 @ y fits in 32 bits? - cmp r3,#0 @ yes; and x? - bne 1f - cmp r2,#0 - beq 2f @ x==0? - mov r12,r7 - ldr r7,=SIO_BASE - str r0,[r7,#SIO_DIV_UDIVIDEND_OFFSET] - str r2,[r7,#SIO_DIV_UDIVISOR_OFFSET] - movs r1,#0 - movs r3,#0 - wait_div 2 - ldr r2,[r7,#SIO_DIV_REMAINDER_OFFSET] - ldr r0,[r7,#SIO_DIV_QUOTIENT_OFFSET] - mov r7,r12 - bx r14 - -2: @ divide by 0 with y<2^32 - cmp r0,#0 @ y==0? - beq 3f @ then pass 0 to __aeabi_ldiv0 -udiv0: - ldr r0,=0xffffffff - movs r1,r0 @ pass 2^64-1 to __aeabi_ldiv0 -3: - push {r14} -#if PICO_DIVIDER_CALL_LDIV0 - bl __aeabi_ldiv0 -#endif - movs r2,#0 @ and return 0 for the remainder - movs r3,#0 - pop {r15} - -1: - movs r2,r0 @ x>y, so result is 0 remainder y - movs r3,r1 - movs r0,#0 - movs r1,#0 - bx r14 - -.ltorg - -@ here y occupies more than 32 bits -@ split into cases according to the size of x -y64: - cmp r3,#0 - beq 1f - b y64_x48 @ if x does not fit in 32 bits, go to 48- and 64-bit cases -1: - lsrs r3,r2,#16 - bne y64_x32 @ jump if x is 17..32 bits - -@ here x is at most 16 bits - - cmp r2,#0 - beq udiv0 @ x==0? exit as with y!=0 case above - push {r7} - ldr r7,=SIO_BASE - str r1,[r7,#SIO_DIV_UDIVIDEND_OFFSET] - str r2,[r7,#SIO_DIV_UDIVISOR_OFFSET] - wait_div 4 - push {r4, r5} - lsrs r4,r0,#16 - ldr r3,[r7,#SIO_DIV_REMAINDER_OFFSET] @ r0=y0-q0*x; 0<=r0>16); - str r2,[r7,#SIO_DIV_UDIVISOR_OFFSET] @ must set divisor again, as we do not save/restore regs at all in IRQs if not dirty - wait_div 1 - uxth r4,r0 - ldr r3,[r7,#SIO_DIV_REMAINDER_OFFSET] @ r1=y1-q1*x; 0<=r1>16); - str r2,[r7,#SIO_DIV_UDIVISOR_OFFSET] @ must set divisor again, as we do not save/restore regs at all in IRQs if not dirty - wait_div 3 - movs r3,#0 - lsls r4,r5,#16 @ quotient=(q0<<32)+(q1<<16)+q2 - lsrs r5,#16 - ldr r2,[r7,#SIO_DIV_REMAINDER_OFFSET] @ r2=y2-q2*x; 0<=r2>15)+1; 2^16>48)*r)>>16; - lsls r7,r6,#13 - mov r14,r7 @ quh=q0<<13 - - muls r3,r6 @ x0l*q - lsrs r7,r3,#15 - lsls r3,#17 @ r3:r7 is (x0l*q)<<17 - subs r0,r3 - sbcs r1,r7 @ y-=(x0l*q)<<17 - - lsrs r3,r2,#16 @ x0h - muls r3,r6 @ q*x0h - adds r3,r3 - subs r1,r3 @ y-=(x0h*q)<<17 - - lsrs r6,r1,#3 - muls r6,r4 - lsrs r6,#16 @ q=((ui32)(y>>35)*r)>>16; - add r14,r6 @ quh+=q1 - - uxth r3,r2 @ x0l - muls r3,r6 @ x0l*q - lsrs r7,r3,#28 - lsls r3,#4 @ r3:r7 is (x0l*q)<<4 - subs r0,r3 - sbcs r1,r7 @ y-=(x0l*q)<<4 - - lsrs r3,r2,#16 @ x0h - muls r3,r6 @ x0h*q - lsrs r7,r3,#12 - lsls r3,#20 @ r3:r7 is (x0h*q)<<4 - subs r0,r3 - sbcs r1,r7 @ y-=(x0h*q)<<4 - - lsrs r6,r0,#22 - lsls r7,r1,#10 - orrs r6,r7 @ y>>22 - muls r6,r4 - lsrs r6,#16 @ q=((ui32)(y>>22)*r)>>16; - - cmp r5,#9 - blt last0 @ if(xsh<9) goto last0; - -@ on this path xsh>=9, which means x<2^23 - lsrs r2,#9 @ x0>>9: this shift loses no bits -@ the remainder y-x0*q is guaranteed less than a very small multiple of the remaining quotient -@ bits (at most 6 bits) times x, and so fits in one word - muls r2,r6 @ x0*q - subs r0,r2 @ y-x0*q - lsls r7,r6,#13 @ qul=q<<13 -1: - lsrs r6,r0,#9 - muls r6,r4 - lsrs r6,#16 @ q=((ui32)(y>>9)*r)>>16; - -@ here -@ r0 y -@ r2 x0>>9 -@ r5 xsh -@ r6 q -@ r7 qul -@ r12 x -@ r14 quh - - movs r3,#22 - subs r3,r5 @ 22-xsh - lsrs r6,r3 @ q>>=22-xsh - lsrs r7,r3 @ qul>>=22-xsh - adds r7,r6 @ qul+=q - mov r4,r12 - muls r6,r4 @ x*q - subs r2,r0,r6 @ y-=x*q - mov r0,r14 @ quh - adds r5,#4 @ xsh+4 - adds r3,#6 @ 28-xsh - movs r1,r0 - lsrs r1,r3 - lsls r0,r5 @ r0:r1 is quh<<(4+xsh) - adds r0,r7 - bcc 1f -2: - adds r1,#1 -1: @ qu=((ui64)quh<<(4+xsh))+qul - cmp r2,r4 - bhs 3f - movs r3,#0 - pop {r4-r7,r15} - -.ltorg - -3: - subs r2,r4 - adds r0,#1 - bcc 1b - b 2b @ while(y>=x) y-=x,qu++; - -@ here: -@ r0:r1 y -@ r2 x0 -@ r4 r -@ r5 xsh; xsh<9 -@ r6 q - -last0: - movs r7,#9 - subs r7,r5 @ 9-xsh - lsrs r6,r7 - mov r4,r12 @ x - uxth r2,r4 - muls r2,r6 @ q*xlo - subs r0,r2 - bcs 1f - subs r1,#1 @ y-=q*xlo -1: - lsrs r2,r4,#16 @ xhi - muls r2,r6 @ q*xhi - lsrs r3,r2,#16 - lsls r2,#16 - subs r2,r0,r2 - sbcs r1,r3 @ y-q*xhi - movs r3,r1 @ y now in r2:r3 - mov r0,r14 @ quh - adds r5,#4 @ xsh+4 - adds r7,#19 @ 28-xsh - movs r1,r0 - lsrs r1,r7 - lsls r0,r5 @ r0:r1 is quh<<(4+xsh) - adds r0,r6 - bcc 1f - adds r1,#1 @ quh<<(xsh+4))+q -1: - cmp r3,#0 @ y>=2^32? - bne 3f - cmp r2,r4 @ y>=x? - bhs 4f - pop {r4-r7,r15} - -3: - adds r0,#1 @ qu++ - bcc 2f - adds r1,#1 -2: - subs r2,r4 @ y-=x - bcs 3b - subs r3,#1 - bne 3b - -1: - cmp r2,r4 - bhs 4f - pop {r4-r7,r15} - -4: - adds r0,#1 @ qu++ - bcc 2f - adds r1,#1 -2: - subs r2,r4 @ y-=x - b 1b - -y64_x48: -@ here x is 33..64 bits - push {r4-r7,r14} @ save a copy of x - lsrs r4,r3,#16 - beq 1f - b y64_x64 @ jump if x is 49..64 bits -1: - push {r2-r3} @ save a copy of x -@ here x is 33..48 bits - movs r5,#0 @ xsh=0 - lsrs r4,r3,#8 - bne 1f - lsls r3,#8 - lsrs r6,r2,#24 - orrs r3,r6 - lsls r2,#8 @ if(x0<1U<<40) x0<<=8,xsh =8; - adds r5,#8 -1: - lsrs r4,r3,#12 - bne 1f - lsls r3,#4 - lsrs r6,r2,#28 - orrs r3,r6 - lsls r2,#4 @ if(x0<1U<<44) x0<<=4,xsh+=4; - adds r5,#4 -1: - lsrs r4,r3,#14 - bne 1f - lsls r3,#2 - lsrs r6,r2,#30 - orrs r3,r6 - lsls r2,#2 @ if(x0<1U<<46) x0<<=2,xsh+=2; - adds r5,#2 -1: - lsrs r4,r3,#15 - bne 1f - adds r2,r2 - adcs r3,r3 @ if(x0<1U<<47) x0<<=1,xsh+=1; - adds r5,#1 -1: -@ now 2^47<=x0<2^48, 0<=xsh<16 (amount x is shifted in x0); number of quotient bits to be calculated qb=xsh+17 17<=qb<33 - movs r4,r3 - adds r7,r2,r2 - adcs r4,r4 - adds r4,#1 @ x1=(ui32)(x0>>31)+1; // 2^16>48)*r)>>16; - lsls r7,r6,#13 - mov r14,r7 @ save q<<13 - uxth r7,r2 @ x0l - muls r7,r6 - subs r0,r7 - bcs 1f - subs r1,#1 -1: - subs r0,r7 - bcs 1f - subs r1,#1 -1: - uxth r7,r3 @ x0h - muls r7,r6 - subs r1,r7 - subs r1,r7 - lsrs r7,r2,#16 @ x0m - muls r7,r6 - lsls r6,r7,#17 - lsrs r7,#15 - subs r0,r6 - sbcs r1,r7 @ y-=((ui64)q*x0)<<1; - - lsrs r6,r1,#3 @ y>>35 - muls r6,r4 - lsrs r6,#16 @ q=((ui32)(y>>35)*r)>>16; - - cmp r5,#12 - blt last1 @ if(xsh<12) goto last1; - - add r14,r6 @ qu<<13+q - lsrs r2,#12 - lsls r7,r3,#20 - orrs r2,r7 - lsrs r3,#12 @ x0>>12 - - uxth r7,r2 @ x0l - muls r7,r6 - subs r0,r7 - bcs 1f - subs r1,#1 -1: - uxth r7,r3 @ x0h - muls r7,r6 - subs r1,r7 - lsrs r7,r2,#16 @ x0m - muls r7,r6 - lsls r6,r7,#16 - lsrs r7,#16 - subs r0,r6 - sbcs r1,r7 @ y-=((ui64)q*x0)>>12 - - lsrs r6,r0,#22 - lsls r7,r1,#10 - orrs r6,r7 @ y>>22 - muls r6,r4 - movs r7,#41 - subs r7,r5 - lsrs r6,r7 @ q=((ui32)(y>>22)*r)>>(16+25-xsh) - - subs r5,#12 - mov r7,r14 - lsls r7,r5 -2: - adds r7,r6 @ qu=(qu<<(xsh-12))+q - pop {r4,r5} @ recall x - -@ here -@ r0:r1 y -@ r4:r5 x -@ r6 q -@ r7 qu - - uxth r2,r4 - uxth r3,r5 - muls r2,r6 @ xlo*q - muls r3,r6 @ xhi*q - subs r0,r2 - sbcs r1,r3 - lsrs r2,r4,#16 - muls r2,r6 - lsrs r3,r2,#16 - lsls r2,#16 @ xm*q - subs r0,r2 - sbcs r1,r3 @ y-=(ui64)q*x - -1: - movs r2,r0 - movs r3,r1 - adds r7,#1 - subs r0,r4 - sbcs r1,r5 @ while(y>=x) y-=x,qu++; - bhs 1b - subs r0,r7,#1 @ correction to qu - movs r1,#0 - pop {r4-r7,r15} - -last1: -@ r0:r1 y -@ r2:r3 x0 -@ r5 xsh -@ r6 q - - movs r7,#12 - subs r7,r5 - lsrs r6,r7 @ q>>=12-xsh - mov r7,r14 - lsrs r7,#13 - lsls r7,r5 - adds r7,r7 @ qu<<(xsh+1) - b 2b - -y64_x64: -@ here x is 49..64 bits - movs r4,#0 @ q=0 if x>>32==0xffffffff - adds r5,r3,#1 - beq 1f - - ldr r7,=SIO_BASE - str r5,[r7,#SIO_DIV_UDIVISOR_OFFSET] - str r1,[r7,#SIO_DIV_UDIVIDEND_OFFSET] - wait_div 0 - ldr r4,[r7,#SIO_DIV_QUOTIENT_OFFSET] @ q=(ui32)(y>>32)/((x>>32)+1) -1: - uxth r5,r2 - uxth r6,r3 - muls r5,r4 - muls r6,r4 - subs r0,r5 - sbcs r1,r6 - lsrs r5,r2,#16 - lsrs r6,r3,#16 - muls r5,r4 - muls r6,r4 - lsls r6,#16 - lsrs r7,r5,#16 - orrs r6,r7 - lsls r5,#16 - subs r0,r5 - sbcs r1,r6 @ y-=(ui64)q*x - - cmp r1,r3 @ while(y>=x) y-=x,q++ - bhs 1f -3: - movs r2,r0 - movs r3,r1 - movs r0,r4 - movs r1,#0 - pop {r4-r7,r15} - -1: - bne 2f - cmp r0,r2 - blo 3b -2: - subs r0,r2 - sbcs r1,r3 - adds r4,#1 - cmp r1,r3 - blo 3b - b 1b - -div_section divmod_s64s64_rem -regular_func divmod_s64s64_rem - push {r4, lr} - bl divmod_s64s64 - ldr r4, [sp, #8] - stmia r4!, {r2,r3} - pop {r4, pc} - -div_section divmod_u64u64_rem -regular_func divmod_u64u64_rem - push {r4, lr} - bl divmod_u64u64 - ldr r4, [sp, #8] - stmia r4!, {r2,r3} - pop {r4, pc} diff --git a/lib/main/pico-sdk/rp2_common/pico_double/double_aeabi_dcp.S b/lib/main/pico-sdk/rp2_common/pico_double/double_aeabi_dcp.S deleted file mode 100644 index 9579c70e45..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_double/double_aeabi_dcp.S +++ /dev/null @@ -1,266 +0,0 @@ -/* - * Copyright (c) 2024 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "pico/asm_helper.S" - -#if !HAS_DOUBLE_COPROCESSOR -#error attempt to compile double_aeabi_rp2350 when there is no DCP -#else - -#include "hardware/dcp_instr.inc.S" -#include "hardware/dcp_canned.inc.S" - -pico_default_asm_setup - -.macro double_section name -#if PICO_DOUBLE_IN_RAM -.section RAM_SECTION_NAME(\name), "ax" -#else -.section SECTION_NAME(\name), "ax" -#endif -.endm - -.macro double_wrapper_section func -double_section WRAPPER_FUNC_NAME(\func) -.endm - -// ============== STATE SAVE AND RESTORE =============== - -.macro saving_func type func - // Note we are usually 32-bit aligned already at this point, as most of the - // function bodies contain exactly two 16-bit instructions: bmi and bx lr. - // We want the PCMP word-aligned. -.p2align 2 - // When the engaged flag is set, branch back here to invoke save routine and - // hook lr with the restore routine, then fall back through to the entry - // point. The engaged flag will be clear when checked a second time. -1: - push {lr} // 16-bit instruction - bl generic_save_state // 32-bit instruction - b 1f // 16-bit instruction - // This is the actual entry point: -\type\()_func \func - PCMP apsr_nzcv - bmi 1b -1: -.endm - -.macro saving_func_return - bx lr -.endm - -double_section __rp2350_dcp_engaged_state_save_restore -.thumb_func -generic_save_state: - sub sp, #24 - push {r0, r1} - // do save here - PXMD r0, r1 - strd r0, r1, [sp, #8 + 0] - PYMD r0, r1 - strd r0, r1, [sp, #8 + 8] - REFD r0, r1 - strd r0, r1, [sp, #8 + 16] - pop {r0, r1} - blx lr - // <- wrapped function returns here - // fall through into restore: -.thumb_func -generic_restore_state: - // do restore here - pop {r12, r14} - WXMD r12, r14 - pop {r12, r14} - WYMD r12, r14 - pop {r12, r14} - WEFD r12, r14 - pop {pc} - -// ============== ARITHMETIC FUNCTIONS =============== - -double_wrapper_section __aeabi_dadd -saving_func wrapper __aeabi_dadd - dcp_dadd_m r0,r1,r0,r1,r2,r3 - saving_func_return - -double_wrapper_section __aeabi_dsub -saving_func wrapper __aeabi_dsub - dcp_dsub_m r0,r1,r0,r1,r2,r3 - saving_func_return - -double_wrapper_section __aeabi_drsub -saving_func wrapper __aeabi_drsub - dcp_dsub_m r0,r1,r2,r3,r0,r1 - saving_func_return - -double_wrapper_section __aeabi_dmul -saving_func wrapper __aeabi_dmul - - // todo optimize this based on final decision on saving_func_entry - push {r4,r14} - dcp_dmul_m r0,r1,r0,r1,r2,r3,r0,r1,r2,r3,r4,r12,r14 - // todo optimize this based on final decision on saving_func_entry - pop {r4,lr} - saving_func_return - -double_section ddiv_fast -saving_func regular ddiv_fast - dcp_ddiv_fast_m r0,r1,r0,r1,r2,r3,r0,r1,r2,r3,r12 - saving_func_return - -double_wrapper_section __aeabi_ddiv -saving_func wrapper __aeabi_ddiv -@ with correct rounding - dcp_ddiv_m r0,r1,r0,r1,r2,r3,r0,r1,r2,r3,r12 - saving_func_return - -double_section sqrt_fast -saving_func regular sqrt_fast - dcp_dsqrt_fast_m r0,r1,r0,r1,r0,r1,r2,r3,r12 - saving_func_return - -double_wrapper_section sqrt -saving_func wrapper sqrt -@ with correct rounding - dcp_dsqrt_m r0,r1,r0,r1,r0,r1,r2,r3,r12 - saving_func_return - -// todo not a real thing -double_wrapper_section __aeabi_dclassify -saving_func wrapper __aeabi_dclassify -@ with correct rounding - dcp_dclassify_m apsr_nzcv,r0,r1 - saving_func_return - -// ============== CONVERSION FUNCTIONS =============== - -double_wrapper_section __aeabi_d2f -saving_func wrapper __aeabi_d2f -@ with rounding - dcp_double2float_m r0,r0,r1 - saving_func_return - -double_wrapper_section __aeabi_i2d -saving_func wrapper __aeabi_i2d - dcp_int2double_m r0,r1,r0 - saving_func_return - -double_wrapper_section __aeabi_ui2d -saving_func wrapper __aeabi_ui2d - dcp_uint2double_m r0,r1,r0 - saving_func_return - -double_wrapper_section __aeabi_d2iz -saving_func wrapper __aeabi_d2iz -@ with truncation towards 0 - dcp_double2int_m r0,r0,r1 - saving_func_return - -double_wrapper_section __aeabi_d2uiz -saving_func wrapper __aeabi_d2uiz -@ with truncation towards 0 - dcp_double2uint_m r0,r0,r1 - saving_func_return - -// todo not a real thing -double_wrapper_section __aeabi_d2i_r -saving_func wrapper __aeabi_d2i_r -@ with rounding - dcp_double2int_r_m r0,r0,r1 - saving_func_return - -// todo not a real thing -double_wrapper_section __aeabi_d2ui_r -saving_func wrapper __aeabi_d2ui_r -@ with rounding - dcp_double2uint_r_m r0,r0,r1 - saving_func_return - -// ============== COMPARISON FUNCTIONS =============== - -double_wrapper_section __aeabi_dcmpun -saving_func wrapper __aeabi_dcmpun - dcp_dcmp_m r0,r0,r1,r2,r3 - // extract unordered bit - ubfx r0, r0, #28, #1 - saving_func_return - -double_wrapper_section __aeabi_dcmp - -saving_func wrapper __aeabi_cdrcmple - dcp_dcmp_m apsr_nzcv,r2,r3,r0,r1 // with arguments reversed - bvs cmp_nan - saving_func_return - -// these next two can be the same function in the absence of exceptions -saving_func wrapper __aeabi_cdcmple -//wrapper_func __aeabi_dcmp - dcp_dcmp_m apsr_nzcv,r0,r1,r2,r3 - bvs cmp_nan - saving_func_return - -// It is not clear from the ABI documentation whether cdcmpeq must set the C flag -// in the same way as cdcmple. If not, we could save the "bvs" below; but we -// err on the side of caution. -saving_func wrapper __aeabi_cdcmpeq -//wrapper_func __aeabi_dcmp - dcp_dcmp_m apsr_nzcv,r0,r1,r2,r3 - bvs cmp_nan - saving_func_return - -// If the result of a flag-setting comparison is "unordered" then we need to set C and clear Z. -// We could conceivably just do lsrs r12,r14,#1, or even cmp r14,r14,lsr#1 as (a) r14 here is a -// return address and r14b0=1 for Thumb mode; (b) we are unlikely to be returning to address 0. -cmp_nan: - movs r12, #3 // r12 does not need to be preserved by the flag-setting comparisons - lsrs r12, #1 // set C, clear Z - saving_func_return - -// int FUNC_NAME(__aeabi_dcmpeq)(double, double) result (1, 0) denotes (=, ?<>) [2], use for C == and != -double_wrapper_section __aeabi_dcmpeq -saving_func wrapper __aeabi_dcmpeq - dcp_dcmp_m r0,r0,r1,r2,r3 - // extract Z - ubfx r0, r0, #30, #1 - saving_func_return - -// int FUNC_NAME(__aeabi_dcmplt)(double, double) result (1, 0) denotes (<, ?>=) [2], use for C < -double_wrapper_section __aeabi_dcmplt -saving_func wrapper __aeabi_dcmplt - dcp_dcmp_m apsr_nzcv,r2,r3,r0,r1 - ite hi - movhi r0,#1 - movls r0,#0 - saving_func_return - -// int FUNC_NAME(__aeabi_dcmple)(double, double) result (1, 0) denotes (<=, ?>) [2], use for C <= -double_wrapper_section __aeabi_dcmple -saving_func wrapper __aeabi_dcmple - dcp_dcmp_m apsr_nzcv,r2,r3,r0,r1 - ite hs - movhs r0,#1 - movlo r0,#0 - saving_func_return - -// int FUNC_NAME(__aeabi_dcmpge)(double, double) result (1, 0) denotes (>=, ?<) [2], use for C >= -double_wrapper_section __aeabi_dcmpge -saving_func wrapper __aeabi_dcmpge - dcp_dcmp_m apsr_nzcv,r0,r1,r2,r3 - ite hs - movhs r0,#1 - movlo r0,#0 - saving_func_return - -// int FUNC_NAME(__aeabi_dcmpgt)(double, double) result (1, 0) denotes (>, ?<=) [2], use for C > -double_wrapper_section __aeabi_dcmpgt -saving_func wrapper __aeabi_dcmpgt - dcp_dcmp_m apsr_nzcv,r0,r1,r2,r3 - ite hi - movhi r0,#1 - movls r0,#0 - saving_func_return - -#endif diff --git a/lib/main/pico-sdk/rp2_common/pico_double/double_aeabi_rp2040.S b/lib/main/pico-sdk/rp2_common/pico_double/double_aeabi_rp2040.S deleted file mode 100644 index 284846fd9b..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_double/double_aeabi_rp2040.S +++ /dev/null @@ -1,847 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#if PICO_RP2040 -#include "pico/asm_helper.S" -#include "pico/runtime_init.h" -#include "pico/bootrom/sf_table.h" -#include "hardware/divider_helper.S" - -pico_default_asm_setup - -PICO_RUNTIME_INIT_FUNC_RUNTIME(__aeabi_double_init, PICO_RUNTIME_INIT_AEABI_DOUBLE) - -.macro double_section name -#if PICO_DOUBLE_IN_RAM -.section RAM_SECTION_NAME(\name), "ax" -#else -.section SECTION_NAME(\name), "ax" -#endif -.endm - -.macro _double_wrapper_func x - wrapper_func \x -.endm - -.macro wrapper_func_d1 x - _double_wrapper_func \x -#if PICO_DOUBLE_PROPAGATE_NANS - mov ip, lr - bl __check_nan_d1 - mov lr, ip -#endif -.endm - -.macro wrapper_func_d2 x - _double_wrapper_func \x -#if PICO_DOUBLE_PROPAGATE_NANS - mov ip, lr - bl __check_nan_d2 - mov lr, ip -#endif -.endm - -.section .text - -#if PICO_DOUBLE_PROPAGATE_NANS -.thumb_func -__check_nan_d1: - movs r3, #1 - lsls r3, #21 - lsls r2, r1, #1 - adds r2, r3 - bhi 1f - bx lr -1: - bx ip - -.thumb_func -__check_nan_d2: - push {r0, r2} - movs r2, #1 - lsls r2, #21 - lsls r0, r1, #1 - adds r0, r2 - bhi 1f - lsls r0, r3, #1 - adds r0, r2 - bhi 2f - pop {r0, r2} - bx lr -2: - pop {r0, r2} - mov r0, r2 - mov r1, r3 - bx ip -1: - pop {r0, r2} - bx ip -#endif - -.macro table_tail_call SF_TABLE_OFFSET - push {r3, r4} -#if PICO_DOUBLE_SUPPORT_ROM_V1 && PICO_RP2040_B0_SUPPORTED -#ifndef NDEBUG - movs r3, #0 - mov ip, r3 -#endif -#endif - ldr r3, =sd_table - ldr r3, [r3, #\SF_TABLE_OFFSET] - str r3, [sp, #4] - pop {r3, pc} -.endm - -.macro shimmable_table_tail_call SF_TABLE_OFFSET shim - push {r3, r4} - ldr r3, =sd_table - ldr r3, [r3, #\SF_TABLE_OFFSET] -#if PICO_DOUBLE_SUPPORT_ROM_V1 && PICO_RP2040_B0_SUPPORTED - mov ip, pc -#endif - str r3, [sp, #4] - pop {r3, pc} -#if PICO_DOUBLE_SUPPORT_ROM_V1 && PICO_RP2040_B0_SUPPORTED -.byte \SF_TABLE_OFFSET, 0xdf -.word \shim -#endif -.endm - -.macro double_wrapper_section func -double_section WRAPPER_FUNC_NAME(\func) -.endm - -double_section push_r8_r11 -regular_func push_r8_r11 - mov r4,r8 - mov r5,r9 - mov r6,r10 - mov r7,r11 - push {r4-r7} - bx r14 - -double_section pop_r8_r11 -regular_func pop_r8_r11 - pop {r4-r7} - mov r8,r4 - mov r9,r5 - mov r10,r6 - mov r11,r7 - bx r14 - -// note generally each function is in a separate section unless there is fall thru or branching between them -// note fadd, fsub, fmul, fdiv are so tiny and just defer to rom so are lumped together so they can share constant pool - -// note functions are word aligned except where they are an odd number of linear instructions - -// double FUNC_NAME(__aeabi_dadd)(double, double) double-precision addition -double_wrapper_section __aeabi_darithmetic -// double FUNC_NAME(__aeabi_drsub)(double x, double y) double-precision reverse subtraction, y - x - -// frsub first because it is the only one that needs alignment -.align 2 -wrapper_func __aeabi_drsub - eors r0, r1 - eors r1, r0 - eors r0, r1 - // fall thru - -// double FUNC_NAME(__aeabi_dsub)(double x, double y) double-precision subtraction, x - y -wrapper_func_d2 __aeabi_dsub -#if PICO_DOUBLE_PROPAGATE_NANS - // we want to return nan for inf-inf or -inf - -inf, but without too much upfront cost - mov ip, r0 - mov r0, r1 - eors r0, r3 - bmi 1f // different signs - mov r0, ip - push {r0-r3, lr} - bl 2f - b ddiv_dsub_nan_helper -1: - mov r0, ip -2: -#endif - shimmable_table_tail_call SF_TABLE_FSUB dsub_shim - -wrapper_func_d2 __aeabi_dadd - shimmable_table_tail_call SF_TABLE_FADD dadd_shim - -// double FUNC_NAME(__aeabi_ddiv)(double n, double d) double-precision division, n / d -wrapper_func_d2 __aeabi_ddiv -#if PICO_DOUBLE_PROPAGATE_NANS - push {r0-r3, lr} - bl 1f - b ddiv_dsub_nan_helper -1: -#endif -#if !PICO_DIVIDER_DISABLE_INTERRUPTS - // to support IRQ usage (or context switch) we must save/restore divider state around call if state is dirty - mov ip, r2 - ldr r2, =(SIO_BASE) - ldr r2, [r2, #SIO_DIV_CSR_OFFSET] - lsrs r2, #SIO_DIV_CSR_DIRTY_SHIFT_FOR_CARRY - bcs ddiv_save_state - mov r2, ip -#else - // to avoid worrying about IRQs (or context switches), simply disable interrupts around call - push {r4, lr} - mrs r4, PRIMASK - cpsid i - bl ddiv_shim_call - msr PRIMASK, r4 - pop {r4, pc} -#endif -ddiv_shim_call: - shimmable_table_tail_call SF_TABLE_FDIV ddiv_shim - -#if !PICO_DIVIDER_DISABLE_INTERRUPTS -ddiv_save_state: - ldr r2, =(SIO_BASE) - save_div_state_and_lr - mov r2, ip - bl ddiv_shim_call - ldr r2, =(SIO_BASE) - restore_div_state_and_return -#endif - -ddiv_dsub_nan_helper: -#if PICO_DOUBLE_PROPAGATE_NANS - // check for infinite op infinite (or rather check for infinite result with both - // operands being infinite) - lsls r2, r1, #1 - asrs r2, r2, #21 - adds r2, #1 - beq 2f - add sp, #16 - pop {pc} -2: - ldr r2, [sp, #4] - ldr r3, [sp, #12] - lsls r2, #1 - asrs r2, r2, #21 - lsls r3, #1 - asrs r3, r3, #24 - ands r2, r3 - adds r2, #1 - bne 3f - // infinite to nan - movs r2, #1 - lsls r2, #19 - orrs r1, r2 -3: - add sp, #16 - pop {pc} -#endif - -// double FUNC_NAME(__aeabi_dmul)(double, double) double-precision multiplication -wrapper_func_d2 __aeabi_dmul -#if PICO_DOUBLE_PROPAGATE_NANS - push {r0-r3, lr} - bl 1f - - // check for multiplication of infinite by zero (or rather check for infinite result with either - // operand 0) - lsls r3, r1, #1 - asrs r3, r3, #21 - adds r3, #1 - beq 2f - add sp, #16 - pop {pc} -2: - ldr r2, [sp, #4] - ldr r3, [sp, #12] - ands r2, r3 - bne 3f - // infinite to nan - movs r2, #1 - lsls r2, #19 - orrs r1, r2 -3: - add sp, #16 - pop {pc} -1: -#endif - shimmable_table_tail_call SF_TABLE_FMUL dmul_shim - -// void FUNC_NAME(__aeabi_cdrcmple)(double, double) reversed 3-way (<, =, ?>) compare [1], result in PSR ZC flags -double_wrapper_section __aeabi_cdcmple - -wrapper_func __aeabi_cdrcmple - push {r0-r7,r14} - eors r0, r2 - eors r2, r0 - eors r0, r2 - eors r1, r3 - eors r3, r1 - eors r1, r3 - b __aeabi_dfcmple_guts - -// NOTE these share an implementation as we have no excepting NaNs. -// void FUNC_NAME(__aeabi_cdcmple)(double, double) 3-way (<, =, ?>) compare [1], result in PSR ZC flags -// void FUNC_NAME(__aeabi_cdcmpeq)(double, double) non-excepting equality comparison [1], result in PSR ZC flags -@ compare r0:r1 against r2:r3, returning -1/0/1 for <, =, > -@ also set flags accordingly -.align 2 -wrapper_func __aeabi_cdcmple -wrapper_func __aeabi_cdcmpeq - push {r0-r7,r14} -__aeabi_dfcmple_guts: - ldr r7,=0x7ff @ flush NaNs and denormals - lsls r4,r1,#1 - lsrs r4,#21 - beq 1f - cmp r4,r7 - bne 2f - lsls r4, r1, #12 - bhi 7f -1: - movs r0,#0 - lsrs r1,#20 - lsls r1,#20 -2: - lsls r4,r3,#1 - lsrs r4,#21 - beq 1f - cmp r4,r7 - bne 2f - lsls r4, r3, #12 - bhi 7f -1: - movs r2,#0 - lsrs r3,#20 - lsls r3,#20 -2: - movs r6,#1 - eors r3,r1 - bmi 4f @ opposite signs? then can proceed on basis of sign of x - eors r3,r1 @ restore r3 - bpl 2f - cmp r3,r1 - bne 7f -1: - cmp r2,r0 -7: - pop {r0-r7,r15} -2: - cmp r1,r3 - bne 7b -1: - cmp r0,r2 - pop {r0-r7,r15} -4: - orrs r3,r1 @ make -0==+0 - adds r3,r3 - orrs r3,r0 - orrs r3,r2 - beq 7b - mvns r1, r1 @ carry inverse of r1 sign - adds r1, r1 - pop {r0-r7,r15} - - -// int FUNC_NAME(__aeabi_dcmpeq)(double, double) result (1, 0) denotes (=, ?<>) [2], use for C == and != -double_wrapper_section __aeabi_dcmpeq -.align 2 -wrapper_func __aeabi_dcmpeq - push {lr} - bl __aeabi_cdcmpeq - beq 1f - movs r0, #0 - pop {pc} -1: - movs r0, #1 - pop {pc} - -// int FUNC_NAME(__aeabi_dcmplt)(double, double) result (1, 0) denotes (<, ?>=) [2], use for C < -double_wrapper_section __aeabi_dcmplt -.align 2 -wrapper_func __aeabi_dcmplt - push {lr} - bl __aeabi_cdcmple - sbcs r0, r0 - pop {pc} - -// int FUNC_NAME(__aeabi_dcmple)(double, double) result (1, 0) denotes (<=, ?>) [2], use for C <= -double_wrapper_section __aeabi_dcmple -.align 2 -wrapper_func __aeabi_dcmple - push {lr} - bl __aeabi_cdcmple - bls 1f - movs r0, #0 - pop {pc} -1: - movs r0, #1 - pop {pc} - -// int FUNC_NAME(__aeabi_dcmpge)(double, double) result (1, 0) denotes (>=, ?<) [2], use for C >= -double_wrapper_section __aeabi_dcmpge -.align 2 -wrapper_func __aeabi_dcmpge - push {lr} - // because of NaNs it is better to reverse the args than the result - bl __aeabi_cdrcmple - bls 1f - movs r0, #0 - pop {pc} -1: - movs r0, #1 - pop {pc} - -// int FUNC_NAME(__aeabi_dcmpgt)(double, double) result (1, 0) denotes (>, ?<=) [2], use for C > -double_wrapper_section __aeabi_dcmpgt -wrapper_func __aeabi_dcmpgt - push {lr} - // because of NaNs it is better to reverse the args than the result - bl __aeabi_cdrcmple - sbcs r0, r0 - pop {pc} - -// int FUNC_NAME(__aeabi_dcmpun)(double, double) result (1, 0) denotes (?, <=>) [2], use for C99 isunordered() -double_wrapper_section __aeabi_dcmpun -wrapper_func __aeabi_dcmpun - movs r0, #1 - lsls r0, #21 - lsls r2, r1, #1 - adds r2, r0 - bhi 1f - lsls r2, r3, #1 - adds r2, r0 - bhi 1f - movs r0, #0 - bx lr -1: - movs r0, #1 - bx lr - -// double FUNC_NAME(__aeabi_ui2d)(unsigned) unsigned to double (double precision) conversion -double_wrapper_section __aeabi_ui2d - shimmable_table_tail_call SF_TABLE_UINT2FLOAT uint2double_shim - -double_wrapper_section __aeabi_i2d - -wrapper_func __aeabi_ui2d - movs r1, #0 - cmp r0, #0 - bne 2f -1: - bx lr -// double FUNC_NAME(__aeabi_i2d)(int) integer to double (double precision) conversion -wrapper_func __aeabi_i2d - asrs r1, r0, #31 - eors r0, r1 - subs r0, r1 - beq 1b - lsls r1, #31 -2: - push {r0, r1, r4, lr} - ldr r3, =sf_clz_func - ldr r3, [r3] - blx r3 - pop {r2, r3} - adds r4, r0, #1 - lsls r2, r4 - lsls r0, r2, #20 - lsrs r2, #12 - ldr r1,=1055 - subs r1, r4 - lsls r1, #20 - orrs r1, r3 - orrs r1, r2 - pop {r4, pc} - -// int FUNC_NAME(__aeabi_d2iz)(double) double (double precision) to integer C-style conversion [3] -double_wrapper_section __aeabi_d2iz -wrapper_func __aeabi_d2iz -regular_func double2int_z - push {r4, lr} - lsls r4, r1, #1 - lsrs r2, r4, #21 - movs r3, #0x80 - adds r2, r3 - lsls r3, #3 - subs r2, r3 - lsls r3, #21 - cmp r2, #126 - ble 1f - subs r2, #158 - bge 2f - asrs r4, r1, #31 - lsls r1, #12 - lsrs r1, #1 - orrs r1, r3 - negs r2, r2 - lsrs r1, r2 - lsls r4, #1 - adds r4, #1 - adds r2, #21 - cmp r2, #32 - bge 3f - lsrs r0, r2 - orrs r0, r1 - muls r0, r4 - pop {r4, pc} -1: - movs r0, #0 - pop {r4, pc} -3: - mov r0, r1 - muls r0, r4 - pop {r4, pc} -2: - // overflow - lsrs r0, r1, #31 - adds r0, r3 - subs r0, #1 - pop {r4, pc} - -double_section double2int -regular_func double2int - shimmable_table_tail_call SF_TABLE_FLOAT2INT double2int_shim - -// unsigned FUNC_NAME(__aeabi_d2uiz)(double) double (double precision) to unsigned C-style conversion [3] -double_wrapper_section __aeabi_d2uiz -wrapper_func __aeabi_d2uiz -regular_func double2uint - shimmable_table_tail_call SF_TABLE_FLOAT2UINT double2uint_shim - -double_section fix2double -regular_func fix2double - shimmable_table_tail_call SF_TABLE_FIX2FLOAT fix2double_shim - -double_section ufix2double -regular_func ufix2double - shimmable_table_tail_call SF_TABLE_UFIX2FLOAT ufix2double_shim - -double_section fix642double -regular_func fix642double - shimmable_table_tail_call SF_TABLE_FIX642FLOAT fix642double_shim - -double_section ufix2double -regular_func ufix642double - shimmable_table_tail_call SF_TABLE_UFIX642FLOAT ufix642double_shim - -// double FUNC_NAME(__aeabi_l2d)(long long) long long to double (double precision) conversion -double_wrapper_section __aeabi_l2d -wrapper_func __aeabi_l2d - shimmable_table_tail_call SF_TABLE_INT642FLOAT int642double_shim - -// double FUNC_NAME(__aeabi_l2f)(long long) long long to double (double precision) conversion -double_wrapper_section __aeabi_ul2d -wrapper_func __aeabi_ul2d - shimmable_table_tail_call SF_TABLE_UINT642FLOAT uint642double_shim - -// long long FUNC_NAME(__aeabi_d2lz)(double) double (double precision) to long long C-style conversion [3] -double_wrapper_section __aeabi_d2lz -wrapper_func __aeabi_d2lz -regular_func double2int64_z - cmn r1, r1 - bcc double2int64 - push {lr} - lsls r1, #1 - lsrs r1, #1 - movs r2, #0 - bl double2ufix64 - cmp r1, #0 - bmi 1f - movs r2, #0 - negs r0, r0 - sbcs r2, r1 - mov r1, r2 - pop {pc} -1: - movs r1, #128 - lsls r1, #24 - movs r0, #0 - pop {pc} - -double_section double2int64 -regular_func double2int64 - shimmable_table_tail_call SF_TABLE_FLOAT2INT64 double2int64_shim - -// unsigned long long FUNC_NAME(__aeabi_d2ulz)(double) double to unsigned long long C-style conversion [3] -double_wrapper_section __aeabi_d2ulz -wrapper_func __aeabi_d2ulz - shimmable_table_tail_call SF_TABLE_FLOAT2UINT64 double2uint64_shim - -double_section double2fix64 -regular_func double2fix64 - shimmable_table_tail_call SF_TABLE_FLOAT2FIX64 double2fix64_shim - -double_section double2ufix64 -regular_func double2ufix64 - shimmable_table_tail_call SF_TABLE_FLOAT2UFIX64 double2ufix64_shim - -double_section double2fix -regular_func double2fix - shimmable_table_tail_call SF_TABLE_FLOAT2FIX double2fix_shim - -double_section double2ufix -regular_func double2ufix - shimmable_table_tail_call SF_TABLE_FLOAT2UFIX double2ufix_shim - -double_wrapper_section __aeabi_d2f -1: -#if PICO_DOUBLE_PROPAGATE_NANS - // copy sign bit and 23 NAN id bits into sign bit and significant id bits, also set high id bit - - lsrs r0, #30 - lsls r2, r1, #12 - lsrs r2, #9 - asrs r1, #22 - lsls r1, #22 - orrs r0, r1 - orrs r0, r2 - bx lr -#endif -wrapper_func __aeabi_d2f -#if PICO_DOUBLE_PROPAGATE_NANS - movs r3, #1 - lsls r3, #21 - lsls r2, r1, #1 - adds r2, r3 - bhi 1b -#endif - // note double->float in double table at same index as float->double in double table - shimmable_table_tail_call SF_TABLE_FLOAT2DOUBLE double2float_shim - -double_wrapper_section srqt -wrapper_func_d1 sqrt - shimmable_table_tail_call SF_TABLE_FSQRT dsqrt_shim - -double_wrapper_section sincostan_remainder -regular_func sincostan_remainder - ldr r2, =0x54442D18 // 2 * M_PI - ldr r3, =0x401921FB - push {lr} - // note remainder only uses the divider thru integer divider functions - // which save and restore themselves - bl remainder - pop {pc} - -double_wrapper_section cos -#don't use _d1 as we're doing a range check anyway and infinites/nans are bigger than 1024 -wrapper_func cos - // rom version only works for -1024 < angle < 1024 - lsls r2, r1, #2 - bcc 1f - lsrs r2, #22 - cmp r2, #9 - bge 2f -1: - shimmable_table_tail_call SF_TABLE_FCOS dcos_shim -2: -#if PICO_DOUBLE_PROPAGATE_NANS - lsls r2, r1, #1 - asrs r2, #21 - adds r2, #1 - bne 3f - // infinite to nan - movs r2, #1 - lsls r2, #19 - orrs r1, r2 - bx lr -3: -#endif - push {lr} - bl sincostan_remainder - pop {r2} - mov lr, r2 - b 1b - -double_wrapper_section sin -#don't use _d1 as we're doing a range check anyway and infinites/nans are bigger than 1024 -wrapper_func sin - // rom version only works for -1024 < angle < 1024 - lsls r2, r1, #2 - bcc 1f - lsrs r2, #22 - cmp r2, #9 - bge 2f -1: - shimmable_table_tail_call SF_TABLE_FSIN dsin_shim -2: -#if PICO_DOUBLE_PROPAGATE_NANS - lsls r2, r1, #1 - asrs r2, #21 - adds r2, #1 - bne 3f - // infinite to nan - movs r2, #1 - lsls r2, #19 - orrs r1, r2 - bx lr -3: -#endif - push {lr} - bl sincostan_remainder - pop {r2} - mov lr, r2 - b 1b - -double_wrapper_section sincos - // out of line remainder code for abs(angle)>=1024 -2: -#if PICO_DOUBLE_PROPAGATE_NANS - lsls r2, r1, #1 - asrs r2, #21 - adds r2, #1 - bne 3f - // infinite to nan - movs r2, #1 - lsls r2, #19 - orrs r1, r2 - pop {r4-r5} - stmia r4!, {r0, r1} - stmia r5!, {r0, r1} - pop {r4, r5, pc} -3: -#endif - push {lr} - bl sincostan_remainder - pop {r2} - mov lr, r2 - b 1f // continue with sincos - -wrapper_func sincos - push {r2-r5, lr} - // rom version only works for -1024 < angle < 1024 - lsls r2, r1, #2 - bcc 1f - lsrs r2, #22 - cmp r2, #9 - bge 2b -1: - bl 2f // call the shim - pop {r4-r5} - stmia r4!, {r0, r1} - stmia r5!, {r2, r3} - pop {r4, r5, pc} - -2: - shimmable_table_tail_call SF_TABLE_V3_FSINCOS sincos_shim_bootstrap - -.thumb_func -sincos_shim_bootstrap: - push {r2, r3, r4} - movs r3, #0x13 - ldrb r3, [r3] -#if PICO_DOUBLE_SUPPORT_ROM_V1 && PICO_RP2040_B0_SUPPORTED - cmp r3, #1 - bne 1f - ldr r3, =dsincos_shim - b 2f -#endif -1: - ldr r3, =dsincos_shim_v2 -2: - ldr r2, =sd_table - str r3, [r2, #SF_TABLE_V3_FSINCOS] - str r3, [sp, #8] - pop {r2, r3, pc} -.thumb_func -dsincos_shim_v2: - push {r4-r7,r14} - bl push_r8_r11 - bl v2_rom_dsincos_internal - mov r12,r0 @ save ε - bl v2_rom_dcos_finish - push {r0,r1} - mov r0,r12 - bl v2_rom_dsin_finish - pop {r2,r3} - bl pop_r8_r11 - pop {r4-r7,r15} -.thumb_func -v2_rom_dsincos_internal: - push {r0, lr} - ldr r0, =0x3855 - str r0, [sp, #4] - pop {r0, pc} -.thumb_func -v2_rom_dcos_finish: - push {r0, r1} - ldr r0, =0x389d - str r0, [sp, #4] - pop {r0, pc} -.thumb_func -v2_rom_dsin_finish: - push {r0, r1} - ldr r0, =0x38d9 - str r0, [sp, #4] - pop {r0, pc} - -double_wrapper_section tan -#don't use _d1 as we're doing a range check anyway and infinites/nans are bigger than 1024 -wrapper_func tan - // rom version only works for -1024 < angle < 1024 - lsls r2, r1, #2 - bcc dtan_in_range - lsrs r2, #22 - cmp r2, #9 - bge dtan_angle_out_of_range -dtan_in_range: -#if !PICO_DIVIDER_DISABLE_INTERRUPTS - // to support IRQ usage (or context switch) we must save/restore divider state around call if state is dirty - mov ip, r2 - ldr r2, =(SIO_BASE) - ldr r2, [r2, #SIO_DIV_CSR_OFFSET] - lsrs r2, #SIO_DIV_CSR_DIRTY_SHIFT_FOR_CARRY - bcs dtan_save_state - mov r2, ip -#else - // to avoid worrying about IRQs (or context switches), simply disable interrupts around call - push {r4, lr} - mrs r4, PRIMASK - cpsid i - bl dtan_shim_call - msr PRIMASK, r4 - pop {r4, pc} -#endif -dtan_shim_call: - shimmable_table_tail_call SF_TABLE_FTAN dtan_shim -#if !PICO_DIVIDER_DISABLE_INTERRUPTS -dtan_save_state: - ldr r2, =(SIO_BASE) - save_div_state_and_lr - mov r2, ip - bl dtan_shim_call - ldr r2, =(SIO_BASE) - restore_div_state_and_return -#endif -dtan_angle_out_of_range: -#if PICO_DOUBLE_PROPAGATE_NANS - lsls r2, r1, #1 - asrs r2, #21 - adds r2, #1 - bne 3f - // infinite to nan - movs r2, #1 - lsls r2, #19 - orrs r1, r2 - bx lr -3: -#endif - push {lr} - bl sincostan_remainder - pop {r2} - mov lr, r2 - b dtan_in_range - -double_wrapper_section atan2 -wrapper_func_d2 atan2 - shimmable_table_tail_call SF_TABLE_FATAN2 datan2_shim - -double_wrapper_section exp -wrapper_func_d1 exp - shimmable_table_tail_call SF_TABLE_FEXP dexp_shim - -double_wrapper_section log -wrapper_func_d1 log - shimmable_table_tail_call SF_TABLE_FLN dln_shim - -#endif \ No newline at end of file diff --git a/lib/main/pico-sdk/rp2_common/pico_double/double_conv_m33.S b/lib/main/pico-sdk/rp2_common/pico_double/double_conv_m33.S deleted file mode 100644 index 606cbfc306..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_double/double_conv_m33.S +++ /dev/null @@ -1,387 +0,0 @@ -/* - * Copyright (c) 2024 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "pico/asm_helper.S" -#if HAS_DOUBLE_COPROCESSOR - -pico_default_asm_setup - -.macro double_section name -#if PICO_DOUBLE_IN_RAM -.section RAM_SECTION_NAME(\name), "ax" -#else -.section SECTION_NAME(\name), "ax" -#endif -.endm - -.macro double_wrapper_section func -double_section WRAPPER_FUNC_NAME(\func) -.endm - -double_wrapper_section conv_tod - -@ convert int64 to double, rounding -wrapper_func __aeabi_l2d -regular_func int642double - movs r2,#0 @ fall through -@ convert unsigned 64-bit fix to double, rounding; number of r0:r1 bits after point in r2 -regular_func fix642double - cmp r1,#0 - bge 10f @ positive? can use unsigned code - rsbs r0,#0 - sbc r1,r1,r1,lsl#1 @ make positive - cbz r1,7f @ high word is zero? - clz r3,r1 - subs r3,#11 - bmi 2f - rsbs r12,r3,#32 - lsrs r12,r0,r12 - lsls r0,r3 - lsls r1,r3 - orrs r1,r1,r12 - add r2,r2,r3 - rsbs r2,#0 - add r2,#0x3ff+19+32 - add r1,r1,r2,lsl#20 @ insert exponent - orr r1,#0x80000000 - mov r3,0x7fe - cmp r2,r3 - it lo @ over/underflow? - bxlo r14 - b 3f -7: - mov r1,r2 - b fix2double_neg -2: - add r3,#33 - lsls r12,r0,r3 @ rounding bit in carry, sticky bits in Z - sub r3,#1 - lsl r12,r1,r3 - rsb r3,#32 - lsr r0,r3 - lsr r1,r3 - orr r0,r0,r12 -@ push {r14} -@ bl dumpreg -@ pop {r14} - sub r2,r3,r2 - add r2,#0x3ff+19+32 - beq 4f @ potential rounding tie? - adcs r0,r0,#0 -5: - adc r1,r1,r2,lsl#20 @ insert exponent, add rounding - orr r1,#0x80000000 - mov r3,0x7fe - cmp r2,r3 - it lo - bxlo r14 -@ over/underflow? -3: - mov r1,#0 - it ge - movtge r1,#0x7ff0 @ overflow - mov r0,#0 - bx r14 -1: - movs r1,#0 - bx r14 -4: - bcc 5b @ not a rounding tie after all - adcs r0,r0,#0 - bic r0,r0,#1 @ force to even - b 5b - -@ convert uint64 to double, rounding -wrapper_func __aeabi_ul2d -regular_func uint642double - movs r2,#0 @ fall through -@ convert unsigned 64-bit fix to double, rounding; number of r0:r1 bits after point in r2 -regular_func ufix642double -10: - cbz r1,7f @ high word zero? - clz r3,r1 - subs r3,#11 - bmi 2f - rsbs r12,r3,#32 - lsrs r12,r0,r12 - lsls r0,r3 - lsls r1,r3 - orrs r1,r1,r12 - add r2,r2,r3 - rsbs r2,#0 - add r2,#0x3ff+19+32 - add r1,r1,r2,lsl#20 @ insert exponent - mov r3,0x7fe - cmp r2,r3 - it lo @ over/underflow? - bxlo r14 - b 3f -7: - mov r1,r2 - b ufix2double -2: - add r3,#33 - lsls r12,r0,r3 @ rounding bit in carry, sticky bits in Z - sub r3,#1 - lsl r12,r1,r3 - rsb r3,#32 - lsr r0,r3 - lsr r1,r3 - orr r0,r0,r12 -@ push {r14} -@ bl dumpreg -@ pop {r14} - sub r2,r3,r2 - add r2,#0x3ff+19+32 - beq 4f @ potential rounding tie? - adcs r0,r0,#0 -5: - adc r1,r1,r2,lsl#20 @ insert exponent, add rounding - mov r3,0x7fe - cmp r2,r3 - it lo - bxlo r14 -@ over/underflow? -3: - mov r1,#0 - it ge - movtge r1,#0x7ff0 @ overflow - mov r0,#0 - bx r14 -1: - movs r1,#0 - bx r14 -4: - bcc 5b @ not a rounding tie after all - adcs r0,r0,#0 - bic r0,r0,#1 @ force to even - b 5b - -regular_func fix2double - cmp r0,#0 - bge ufix2double @ positive? can use unsigned code - rsbs r0,#0 @ make positive -fix2double_neg: - clz r3,r0 - subs r3,#11 - bmi 2f - lsls r0,r3 - add r2,r1,r3 - rsbs r2,#0 - add r2,#0x3ff+19 - add r1,r0,r2,lsl#20 @ insert exponent - orr r1,#0x80000000 - mov r0,#0 - mov r3,0x7fe - cmp r2,r3 - it lo @ over/underflow? - bxlo r14 - b 3f -2: - rsb r3,#0 - lsrs r12,r0,r3 - rsb r2,r3,#32 - lsls r0,r0,r2 -@ push {r14} -@ bl dumpreg -@ pop {r14} - sub r2,r3,r1 - add r2,#0x3ff+19 - add r1,r12,r2,lsl#20 @ insert exponent - orr r1,#0x80000000 - mov r3,0x7fe - cmp r2,r3 - it lo - bxlo r14 -@ over/underflow? -3: - mov r1,#0x80000000 - it ge - movtge r1,#0xfff0 @ overflow - mov r0,#0 - bx r14 -1: - movs r1,#0 - bx r14 - -regular_func ufix2double - cbz r0,1f @ zero? return it - clz r3,r0 - subs r3,#11 - bmi 2f - lsls r0,r3 - add r2,r1,r3 - rsbs r2,#0 - add r2,#0x3ff+19 - add r1,r0,r2,lsl#20 @ insert exponent - mov r0,#0 - mov r3,0x7fe - cmp r2,r3 - it lo @ over/underflow? - bxlo r14 - b 3f -2: - rsbs r3,#0 - lsrs r12,r0,r3 - rsb r2,r3,#32 - lsls r0,r0,r2 -@ push {r14} -@ bl dumpreg -@ pop {r14} - sub r2,r3,r1 - add r2,#0x3ff+19 - add r1,r12,r2,lsl#20 @ insert exponent - mov r3,0x7fe - cmp r2,r3 - it lo - bxlo r14 -@ over/underflow? -3: - mov r1,#0 - it ge - movtge r1,#0x7ff0 @ overflow - mov r0,#0 - bx r14 -1: - movs r1,#0 - bx r14 - -double_wrapper_section conv_dtoi64 - -@ convert double to signed int64, rounding towards 0, clamping -wrapper_func __aeabi_d2lz -regular_func double2int64_z - movs r2,#0 @ fall through -@ convert double in r0:r1 to signed fixed point in r0:r1, clamping -regular_func double2fix64_z - sub r2,#0x3ff+52-1 @ remove exponent bias, compensate for mantissa length - asrs r12,r1,#20 @ sign and exponent - sub r3,r12,#1 - sub r1,r1,r3,lsl#20 @ install implied 1, clear exponent - lsls r3,#21 -@ push {r14} -@ bl dumpreg -@ pop {r14} - cmp r3,#0xffc00000 - bhs 1f @ 0, ∞/NaN? - adds r2,r2,r3,lsr#21 @ offset exponent by fix precision; r1 is now required left shift - bmi 4f @ actually a right shift? - cmp r2,#11 @ overflow? - bge 5f - lsls r1,r2 - rsbs r3,r2,#32 - lsrs r3,r0,r3 - orrs r1,r1,r3 - lsls r0,r2 - cmp r12,#0 - it ge - bxge r14 - rsbs r0,#0 - sbc r1,r1,r1,lsl#1 - bx r14 -4: - adds r2,#32 - ble 6f @ result fits in low word? - lsl r3,r1,r2 - rsbs r2,#32 - lsrs r1,r2 - lsrs r0,r2 - orrs r0,r0,r3 - cmp r12,#0 - it ge - bxge r14 - rsbs r0,#0 - sbc r1,r1,r1,lsl#1 - bx r14 -6: - rsbs r2,#0 - usat r2,#5,r2 @ underflow to 0 - lsrs r0,r1,r2 - movs r1,#0 - cmp r12,#0 - it ge - bxge r14 - rsbs r0,#0 - sbc r1,r1,r1,lsl#1 - bx r14 -1: - beq 3f @ ±∞/±NaN? -2: - movs r0,#0 @ ±0: return 0 - movs r1,#0 - bx r14 -3: - orrs r1,r0,r1,lsl#12 @ mantissa field - it ne @ NaN? - movne r12,#0 @ treat NaNs as +∞ -@ here original argument was ±Inf or we have under/overflow -5: - mvn r1,#0x80000000 - add r1,r1,r12,lsr#31 @ so -Inf → 0x80000000, +Inf → 0x7fffffff - mvn r0,r12,asr#31 - bx r14 - -double_wrapper_section conv_dtoui64 - -@ convert double to unsigned int64, rounding towards -Inf, clamping -wrapper_func __aeabi_d2ulz -regular_func double2uint64 -regular_func double2uint64_z - movs r2,#0 @ fall through -@ convert double in r0:r1 to unsigned fixed point in r0:r1, clamping -regular_func double2ufix64 -regular_func double2ufix64_z - subw r2,r2,#0x3ff+52-1 @ remove exponent bias, compensate for mantissa length - asrs r3,r1,#20 @ sign and exponent - sub r3,#1 - sub r1,r1,r3,lsl#20 @ install implied 1, clear exponent and sign - bmi 7f @ argument negative? - movw r12,#0x7fe - cmp r3,r12 - bhs 1f @ 0, ∞/NaN? - adds r2,r3 @ offset exponent by fix precision; r2 is now required left shift - bmi 2f @ actually a right shift? - cmp r2,#12 @ overflow? - bge 4f - lsls r1,r2 - rsbs r3,r2,#32 - lsrs r3,r0,r3 - lsls r0,r2 - orrs r1,r1,r3 - bx r14 -2: - adds r2,#32 - ble 5f @ result fits in low word? - lsl r3,r1,r2 - rsbs r2,#32 - lsrs r1,r2 - lsrs r0,r2 - orrs r0,r0,r3 - bx r14 -5: - rsbs r2,#0 - usat r2,#5,r2 @ underflow to 0 - lsrs r0,r1,r2 - movs r1,#0 - bx r14 -1: - bhi 3f @ 0? return 0 -4: -@ here overflow has occurred - mvn r0,#0 - mvn r1,#0 - bx r14 -7: - cmp r3,#0xfffffffe - bne 3f @ -0? return 0 - orrs r2,r0,r1,lsl#12 @ mantissa field - bne 4b -3: - movs r0,#0 - movs r1,#0 - bx r14 - -#endif diff --git a/lib/main/pico-sdk/rp2_common/pico_double/double_fma_dcp.S b/lib/main/pico-sdk/rp2_common/pico_double/double_fma_dcp.S deleted file mode 100644 index 30f669bd9e..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_double/double_fma_dcp.S +++ /dev/null @@ -1,608 +0,0 @@ -/* - * Copyright (c) 2024 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "pico/asm_helper.S" - -#if !HAS_DOUBLE_COPROCESSOR -#error attempt to compile double_fma_rp2350 when there is no DCP -#else - -#include "hardware/dcp_instr.inc.S" -#include "hardware/dcp_canned.inc.S" - -pico_default_asm_setup - -// factor out save/restore (there is a copy in float code) - -.macro double_section name -#if PICO_DOUBLE_IN_RAM -.section RAM_SECTION_NAME(\name), "ax" -#else -.section SECTION_NAME(\name), "ax" -#endif -.endm - -.macro double_wrapper_section func -double_section WRAPPER_FUNC_NAME(\func) -.endm - -// ============== STATE SAVE AND RESTORE =============== - -.macro saving_func_return - bx lr -.endm - -double_section __rp2350_dcp_engaged_state_save_restore_copy -.thumb_func -__dcp_save_state: - sub sp, #24 - push {r0, r1} - // do save here - PXMD r0, r1 - strd r0, r1, [sp, #8 + 0] - PYMD r0, r1 - strd r0, r1, [sp, #8 + 8] - REFD r0, r1 - strd r0, r1, [sp, #8 + 16] - pop {r0, r1} - blx lr - // <- wrapped function returns here - // fall through into restore: -.thumb_func -__dcp_restore_state: - // do restore here - pop {r12, r14} - WXMD r12, r14 - pop {r12, r14} - WYMD r12, r14 - pop {r12, r14} - WEFD r12, r14 - pop {pc} - -double_wrapper_section __dfma -@ cf saving_func macro: but here we need to record the SP before the state save possibly changes it -1: - push {lr} // 16-bit instruction - bl __dcp_save_state // 32-bit instruction - b 1f // 16-bit instruction - -@ compute mn+a with full intermediate precision -@ r0:r1 m -@ r2:r3 n -@ [r13,#0] a -wrapper_func fma - mov r12,sp @ save the SP - PCMP apsr_nzcv @ test the engaged flag - bmi 1b -1: - push {r4-r8,r14} - ldrd r4,r5,[r12,#0] @ fetch a using original SP - ubfx r7,r1,#20,#11 @ r7=em - ubfx r8,r3,#20,#11 @ r8=en - add r8,r7,r8 @ em+en - - eors r6,r1,r3 @ get sign of mn - eors r6,r6,r5 @ set N if mn has opposite sign to a, i.e. if the operation is essentially a subtraction - WXUP r4,r5 @ write a to coprocessor to get its classification - PEFD r14,r12 @ r14=fa - WXUP r0,r1 @ write m and n to coprocessor to get their classifications - WYUP r2,r3 - PEFD r6,r12 @ r6=fm, r12=fn, r14=fa - orr r14,r14,r6 - orr r14,r14,r12 @ OR of all the classification flags, so we can check if any are zero/Inf/NaN - - RXMS r3,r6,0 @ we will almost always need the full product so compute it here (cf dmul macro) - RYMS r7,r12,0 - umull r0,r1,r3,r7 - mov r2,#0 @ seems to be no 16-bit instruction which zeros a register without affecting the flags - umlal r1,r2,r3,r12 - umlal r1,r2,r6,r7 - mov r3,#0 - umlal r2,r3,r6,r12 @ r0:r1:r2:r3: full product mn Q124 1≤mn<4 - - bmi 50f @ mn has opposite sign to a so operation is essentially a subtraction - -@ ======================== ADDITION PATH ======================== - - tst r14,#0x70000000 @ were any of the arguments zero/inf/NaN? - bne 90f @ then use mla path which gives the correct result in all these cases - ubfx r14,r5,#20,#11 @ r14=ea -@ here all operands are finite and non-zero -@ r0:r1:r2:r3: full product mn Q124 1≤mn<4 -@ r4:r5 a IEEE packed -@ r8: em+en [biased +0x3ff*2] -@ r14: ea [biased +0x3ff] - subw r7,r8,#0x3fd - subs r7,r7,r14 @ em+en-ea+2 (debiased) - blt 80f @ branch if |a| is big compared to |mn|, more precisely if ea-(em+en)≥3 so e.g. if ea=0 (hence 1≤a<2) then em+en≤-3 and mn<4.2¯³=1/2 - -@ ======================== ADDITION PATH, RESULT HAS COMPARABLE MAGNITUDE TO mn ======================== - -@ here |mn| is big compared to |a|; e.g. if em+en=0 (so 1≤mn<4) then ea≤2 and a<8 - movs r8,#1 - bfi r5,r8,#20,#12 @ insert implied 1 in a - rsbs r7,r7,#74 @ shift up ≤74 (can be negative) that will be required for a (Q52) to align with mn (Q124, ending in 20 zeros) -@ now add (shifted) a into mn, preserving flags - and r8,r7,#0x1f @ k=shift mod 32 - mov r12,#1 - lsl r12,r12,r8 @ 2^k - umull r5,r6,r5,r12 @ shift up high word: r4:r5:r6 is now a_lo + 2^k a_hi - sub r12,#1 @ 2^k-1 - umlal r4,r5,r4,r12 @ shift up low word, adding in: r4:r5:r6 is now (a_lo + 2^k a_hi) + (2^k-1) a_lo = 2^k (a_lo + a_hi) = a shifted up by k - bmi 91f @ use flags: will a be shifted down? - cmp r7,#64 @ shift up by two more words? - bge 92f - cmp r7,#32 @ shift up by one more word? - bge 93f - adds r0,r0,r4 @ no more word shifts - adcs r1,r1,r5 - adcs r2,r2,r6 - adcs r3,r3,#0 @ r0:r1:r2:r3: mn + a (cf dmul macro) - WXMS r0,r1 @ write sticky bits - WXMO r2,r3 @ write sticky+result bits - NRDD @ as dmul macro tail: exponent computed in coprocessor is correct - RDDM r0,r1 -// todo optimize this based on final decision on saving_func_entry - pop {r4-r8,lr} - saving_func_return - -93: - adds r1,r1,r4 - adcs r2,r2,r5 - adcs r3,r3,r6 @ r0:r1:r2:r3: mn + (a<<32) - WXMS r0,r1 @ write sticky bits - WXMO r2,r3 @ write sticky+result bits - NRDD - RDDM r0,r1 -// todo optimize this based on final decision on saving_func_entry - pop {r4-r8,lr} - saving_func_return - -92: - adds r2,r2,r4 - adcs r3,r3,r5 @ r0:r1:r2:r3: mn + (a<<64); note this cannot overflow as total shift was at most 74 (see above) - WXMS r0,r1 @ write sticky bits - WXMO r2,r3 @ write sticky+result bits - NRDD - RDDM r0,r1 -// todo optimize this based on final decision on saving_func_entry - pop {r4-r8,lr} - saving_func_return - -91: @ case where a (Q52) is shifted down relative to mn (Q124); the mod 32 part of the shift of a has already been done -@ r0:r1:r2:r3: mn -@ r4:r5:r6: a -@ r7: alignment shift required (negative) - cmn r7,#32 @ shift down one word? - bge 94f - cmn r7,#64 @ shift down two words? - bge 95f -@ here a is shifted entirely below the bottom of m - orr r0,r0,#1 @ a is non-zero so ensure we set the sticky bit - WXMS r0,r1 @ write sticky bits - WXMO r2,r3 @ write sticky+result bits - NRDD - RDDM r0,r1 -// todo optimize this based on final decision on saving_func_entry - pop {r4-r8,lr} - saving_func_return - -94: - adds r0,r0,r5 @ one word shift down - adcs r1,r1,r6 - adcs r2,r2,#0 - adcs r3,r3,#0 - orr r0,r0,r4 @ contribution from a to sticky bits - WXMS r0,r1 @ write sticky bits - WXMO r2,r3 @ write sticky+result bits - NRDD - RDDM r0,r1 -// todo optimize this based on final decision on saving_func_entry - pop {r4-r8,lr} - saving_func_return - -95: - adds r0,r0,r6 @ two word shift down - adcs r1,r1,#0 - adcs r2,r2,#0 - adcs r3,r3,#0 - orr r0,r0,r4 @ contribution from a to sticky bits - orr r0,r0,r5 - WXMS r0,r1 @ write sticky bits - WXMO r2,r3 @ write sticky+result bits - NRDD - RDDM r0,r1 -// todo optimize this based on final decision on saving_func_entry - pop {r4-r8,lr} - saving_func_return - -@ ======================== ADDITION PATH, RESULT HAS COMPARABLE MAGNITUDE TO a ======================== - -80: -@ here |mn|<~|a| -@ r0:r1:r2:r3: mn Q124 -@ r4:r5 a IEEE packed -@ r7: -(shift down required to align mn with a), guaranteed negative -@ r8: em+en [biased +0x3ff*2] -@ r14: ea [biased +0x3ff] - tst r3,#0x20000000 - bne 1f @ 2≤mn<4? - adds r2,r2,r2 @ normalise so mn is 2..4 Q124; note that the contents of r0 and r1 are always destined for the sticky bit in this path - adcs r3,r3,r3 - subs r7,r7,#1 @ correction to alignment shift -1: -@ now we construct an IEEE packed value in r2:r3 such that adding it to r4:r5 gives the correct final result -@ observe that the exponent of this constructed value will be at least two less than that of a (by the "|a| is big compared to |mn|" test above) -@ so the alignment shift in the final addition will be by at least two places; thus we can use bit 0 of the constructed -@ value as a sticky bit, and we still have one bit in hand for rounding - subs r7,r7,#2 @ now r7 < -2 - orr r0,r0,r2,lsl#23 @ shift r2:r3 down 9 places, ORing excess into sticky bits - lsrs r2,r2,#9 - orr r2,r2,r3,lsl#23 - lsrs r3,r3,#9 - orrs r0,r0,r1 - it ne - orrne r2,r2,#1 @ sticky bit from bottom 64 bits of mn as shifted -@ r2:r3 mn 2..4 Q51, i.e. 1..2 Q52 -@ r2b0 holds sticky bit; note that for alignment with a in r4:r5, r2:r3 will be shifted down at least one place - - lsrs r6,r5,#31 @ get sign of a (which in this path is the same as the sign of mn, and of the result) - orr r3,r3,r6,lsl#31 @ set sign in mn - - adds r14,r7,r14 @ get exponent for mn relative to a; note this can go negative - add r3,r3,r14,lsl#20 @ note that "implied" 1 is present in r3, giving an offset of 1 in the exponent - bmi 1f @ negative? then we have just constructed a denormal (or less) and the addition will give an incorrect result - dcp_dadd_m r0,r1,r2,r3,r4,r5 -// todo optimize this based on final decision on saving_func_entry - pop {r4-r8,lr} - saving_func_return - -1: -@ compare with similar code in subtraction path: here we cannot underflow - cmn r7,#64 @ if the alignment shift for mn is very large then the result is just a - ble 82f - add r3,r3,#0x40000000 @ ea cannot be very large (as adding r7 made it negative), so safe to add 1024 to exponents of both a and mn - add r5,r5,#0x40000000 - dcp_dadd_m r0,r1,r2,r3,r4,r5 - sub r1,r1,#0x40000000 @ fix exponent -// todo optimize this based on final decision on saving_func_entry - pop {r4-r8,lr} - saving_func_return - -90: -@ dcp_dmul_m tail then dadd ("mla path") - WXMS r0,r1 @ write sticky bits - WXMO r2,r3 @ write sticky+result bits - NRDD - RDDM r0,r1 - dcp_dadd_m r0,r1,r0,r1,r4,r5 -// todo optimize this based on final decision on saving_func_entry - pop {r4-r8,lr} - saving_func_return - -82: @ |mn| is very small compared to |a|, so result is a - RDDM r0,r1 @ clear the engaged flag - movs r0,r4 - movs r1,r5 -// todo optimize this based on final decision on saving_func_entry - pop {r4-r8,lr} - saving_func_return - -@ ======================== SUBTRACTION PATH ======================== - -50: - tst r14,#0x70000000 @ were any of the arguments zero/inf/NaN? - bne 90b @ then use mla path which gives the correct result in all these cases - ubfx r14,r5,#20,#11 @ r14=ea -@ now all operands are finite and non-zero -@ r0:r1:r2:r3: full product mn Q124 1≤mn<4 -@ r4:r5 a IEEE packed (including sign bit; sign of mn is opposite as we are in the subtraction path) -@ r8: em+en [+0x3ff*2] -@ r14: ea [+0x3ff] - subw r8,r8,#0x3fc @ em+en+3 - subs r7,r8,r14 @ em+en-ea+3 (debiased) - blt 80f @ branch if |a| is big compared to |mn|, more precisely if ea-(em+en)≥4 so e.g. if ea=0 then em+en≤-4 and mn<4.2^-4=1/4 - beq 94f @ branch if ea-(em+en)=3 e.g. if ea=0 then em+en=-3 and 1/8=2^-3≤mn<4.2^-3=1/2 -@ in this branch, if e.g. em+en=0 (so 1≤mn<4) then ea≤2 and a<8 - rsbs r7,r7,#75 @ 75-(em+en-ea+3) = 72-(em+en-ea), shift up 0..74 that will be required for a (Q52) to align with mn (Q124, ending in 20 zeros) - mvn r14,r5,lsr#31 @ save complement of sign of a -@ subtract (shifted) a from mn - and r6,r7,#0x1f @ k=shift mod 32 - mov r12,#1 - bfi r5,r12,#20,#12 @ insert implied 1 in a - lsl r12,r12,r6 @ 2^k - umull r5,r6,r5,r12 - sub r12,#1 - umlal r4,r5,r4,r12 @ shift a up by shift amount mod 32 (see comment in addition path) -@ r4:r5:r6: a shifted up by k=shift mod 32 - bmi 91f @ will a be shifted down? - cmp r7,#64 @ shift up by two more words? - bge 92f - cmp r7,#32 @ shift up by one more word? - bge 93f - subs r0,r0,r4 @ no more word shifts; this cannot go negative or have bad cancellation - sbcs r1,r1,r5 - sbcs r2,r2,r6 - sbcs r3,r3,#0 @ r0:r1:r2:r3: mn - a (cf dmul macro) - WXMS r0,r1 @ write sticky bits - WXMO r2,r3 @ write sticky+result bits - NRDD @ as dmul macro tail: exponent and sign computed in coprocessor is correct - RDDM r0,r1 -// todo optimize this based on final decision on saving_func_entry - pop {r4-r8,lr} - saving_func_return - -94: -@ here if ea-(em+en)=3 e.g. if ea=0 then em+en=-3 and 1/8=2^-3≤mn<4.2^-3=1/2 -@ r0:r1:r2:r3: full product mn Q124 1≤mn<4 -@ r4:r5 a IEEE packed (including sign bit; sign of mn is opposite as we are in the subtraction path) - lsls r5,r5,#11 @ convert a to mantissa Q63 in r4:r5 - orrs r5,r5,r4,lsr#21 - lsls r4,r4,#11 - orrs r5,r5,0x80000000 @ implied 1 - movs r6,#0 - subs r0,r6,r0 @ compute |a|-|mn| - sbcs r6,r6,r1 - sbcs r4,r4,r2 - sbcs r5,r5,r3 - WXMS r0,r6 @ write sticky bits - WXMO r4,r5 @ write sticky+result bits - NRDD - RDDM r0,r1 - eor r1,r1,0x80000000 @ sign of result is opposite to that of product as yielded by coprocessor -// todo optimize this based on final decision on saving_func_entry - pop {r4-r8,lr} - saving_func_return - -93: - subs r1,r1,r4 @ shifting a up by one word: this cannot go negative or have bad cancellation - sbcs r2,r2,r5 - sbcs r3,r3,r6 - WXMS r0,r1 @ write sticky bits - WXMO r2,r3 @ write sticky+result bits - NRDD - RDDM r0,r1 -// todo optimize this based on final decision on saving_func_entry - pop {r4-r8,lr} - saving_func_return - -92: - subs r2,r2,r4 @ shifting a up by two words: this /can/ go negative or have bad cancellation - sbcs r3,r3,r5 - cmp r3,#0x01000000 @ check we have at least 57 bits of product so that dmul tail will round correctly (this test is slightly conservative - 55 needed?) - blt 1f @ also trap case where result is negative - WXMS r0,r1 @ write sticky bits - WXMO r2,r3 @ write sticky+result bits - NRDD - RDDM r0,r1 -// todo optimize this based on final decision on saving_func_entry - pop {r4-r8,lr} - saving_func_return - -@ heavy cancellation case -@ r0:r1:r2:r3: result Q124, signed -@ r8: em+en+3 -@ r14b0: save complement of sign of a -1: - sub r8,r8,#1 @ em+en+2 - RDDM r6,r7 @ clear engaged flag - blo 2f @ if result is negative... - movs r6,#0 @ ... negate it... - subs r0,r6,r0 - sbcs r1,r6,r1 - sbcs r2,r6,r2 - sbcs r3,r6,r3 - eor r14,r14,#1 @ ... and flip saved sign -2: @ now normalise result - orrs r6,r2,r3 @ shift up by 64 possible? - bne 7f - movs r3,r1 @ do it - movs r2,r0 - movs r1,#0 - movs r0,#0 - sub r8,r8,#64 @ fix exponent -7: - cmp r3,#0 @ shift up by 32 possible? - bne 8f - movs r3,r2 @ do it - movs r2,r1 - movs r1,r0 - movs r0,#0 - sub r8,r8,#32 -8: - cmp r3,#0 @ is result zero? return it - beq 9f - clz r6,r3 @ k=amount of final shift - subs r8,r8,r6 @ final exponent - movs r7,#1 - lsls r7,r7,r6 @ r7=2^k - muls r3,r3,r7 - subs r7,r7,#1 @ 2^k-1 - umlal r2,r3,r2,r7 - umlal r1,r2,r1,r7 - umlal r0,r1,r0,r7 @ r0:r1:r2:r3: normalised result - orrs r0,r0,r1 @ any sticky bits below top 64? - it ne - orrne r2,r2,#1 @ or into sticky bit - lsrs r0,r2,#11 @ align to mantissa position for IEEE format - lsrs r1,r3,#11 - orr r0,r0,r3,lsl#21 - lsls r2,r2,#22 @ rounding bit in C, sticky bit in ~Z - bcc 10f @ no rounding? - beq 11f @ rounding tie? - adcs r0,r0,#0 @ round up (C is set) - adcs r1,r1,#0 - adds r8,r8,r1,lsr#20 @ candidate for exponent field - ble 12f @ underflow? overflow cannot occur here as the result is smaller in magnitude than a - bfi r1,r8,#20,#11 @ insert exponent - orr r1,r1,r14,lsl#31 @ or in sign -// todo optimize this based on final decision on saving_func_entry - pop {r4-r8,lr} - saving_func_return - -11: - adcs r0,r0,#0 @ round up as above - adcs r1,r1,#0 - bic r0,r0,#1 @ to even - adds r8,r8,r1,lsr#20 @ candidate for exponent field - ble 12f @ underflow? - bfi r1,r8,#20,#11 @ insert exponent - orr r1,r1,r14,lsl#31 @ or in sign -// todo optimize this based on final decision on saving_func_entry - pop {r4-r8,lr} - saving_func_return - -10: - adds r8,r8,r1,lsr#20 @ candidate for exponent field - ble 12f @ underflow? - bfi r1,r8,#20,#11 @ insert exponent - orr r1,r1,r14,lsl#31 @ or in sign -9: -// todo optimize this based on final decision on saving_func_entry - pop {r4-r8,lr} - saving_func_return - -12: - mov r1,r14,lsl#31 @ underflow: return signed zero - movs r0,#0 -// todo optimize this based on final decision on saving_func_entry - pop {r4-r8,lr} - saving_func_return - -91: @ case where a (Q52) is shifted down relative to mn (Q124); the mod 32 part of the shift of a has already been done -@ r0:r1:r2:r3: mn -@ r4:r5:r6: a -@ r7: alignment shift required (negative) - cmn r7,#32 @ shift down one word? - bge 94f - cmn r7,#64 @ shift down two words? - bge 95f -@ here a is shifted entirely below the bottom of m - subs r0,r0,#1 @ subtract an epsilon (a is non-zero) - sbcs r1,r1,#0 - sbcs r2,r2,#0 - sbcs r3,r3,#0 - orr r0,r0,#1 @ ensure the sticky bit is set (a is non-zero) - WXMS r0,r1 @ write sticky bits - WXMO r2,r3 @ write sticky+result bits - NRDD - RDDM r0,r1 -// todo optimize this based on final decision on saving_func_entry - pop {r4-r8,lr} - saving_func_return - -94: - rsbs r4,r4,#0 @ one word shift down - sbcs r0,r0,r5 - sbcs r1,r1,r6 - sbcs r2,r2,#0 - sbcs r3,r3,#0 - orr r0,r0,r4 @ sticky bits - WXMS r0,r1 @ write sticky bits - WXMO r2,r3 @ write sticky+result bits - NRDD - RDDM r0,r1 -// todo optimize this based on final decision on saving_func_entry - pop {r4-r8,lr} - saving_func_return - -95: - movs r7,#0 @ two words shift down - subs r4,r7,r4 - sbcs r5,r7,r5 - sbcs r0,r0,r6 - sbcs r1,r1,r7 - sbcs r2,r2,r7 - sbcs r3,r3,r7 - orrs r0,r0,r4 @ sticky bits - orrs r0,r0,r5 - WXMS r0,r1 @ write sticky bits - WXMO r2,r3 @ write sticky+result bits - NRDD - RDDM r0,r1 -// todo optimize this based on final decision on saving_func_entry - pop {r4-r8,lr} - saving_func_return - -80: -@ here |a| is big compared to |mn|, more precisely ea-(em+en)≥4 so e.g. if ea=0 then em+en≤-4 and mn<4.2^-4=1/4 -@ r0:r1:r2:r3: mn Q124 -@ r4:r5: a IEEE packed -@ r7<0, em+en-ea+3 (debiased) -@ r14: ea [+0x3ff] - lsrs r6,r3,#29 - bne 1f @ 2≤mn<4? - adds r2,r2,r2 @ shift up one place - adcs r3,r3,r3 - subs r7,r7,#1 @ fix exponent -1: @ now r2:r3 is mn Q61, sticky bits in r0:r1 - subs r7,r7,#3 -@ r7=emn-ea <-3 - orr r0,r0,r2,lsl#23 @ gather sticky bits - lsrs r2,r2,#9 @ adjust mn to Q52 ready to create packed IEEE version of mn - orr r2,r2,r3,lsl#23 - lsrs r3,r3,#9 - orrs r0,r0,r1 @ or of all sticky bits - it ne - orrne r2,r2,#1 @ sticky bit from bottom 64 bits of mn - - mvn r6,r5,lsr#31 @ complement of sign of a - orr r3,r3,r6,lsl#31 @ fix sign of mn so we do a subtraction - - adds r14,r7,r14 @ this can go negative; r14 is now at most ea[+0x3ff]-4 - add r3,r3,r14,lsl#20 -@ the exponent field in r2:r3 (mn) is now at most ea[+0x3ff]-3 -@ that means that in the dadd operation that follows, mn will be shifted down at least three places to align with a, -@ and a post-normalisation shift up of at most one place will be needed -@ therefore in the worst case r2b2 affects b0 of the result; r2b1 affects the rounding of the result; and r2b0 can be used as a sticky bit - bmi 1f @ did exponent go negative? - - dcp_dadd_m r0,r1,r2,r3,r4,r5 -// todo optimize this based on final decision on saving_func_entry - pop {r4-r8,lr} - saving_func_return - -1: - cmn r7,#64 @ is mn being shifted well below the bottom of a? - ble 82b @ then result is just a - add r3,r3,#0x40000000 @ otherwise offset exponents by +1024 - add r5,r5,#0x40000000 - dcp_dadd_m r0,r1,r2,r3,r4,r5 - ubfx r2,r1,#20,#11 @ get exponent - cmp r2,#0x400 @ too small? - itte ls - andls r1,r1,0x80000000 @ flush to signed zero - movls r0,#0 - subhi r1,r1,#0x40000000 @ else fix exponent of result -// todo optimize this based on final decision on saving_func_entry - pop {r4-r8,lr} - saving_func_return - - -double_wrapper_section __dmla -@ cf saving_func macro: but here we need to record the SP before the state save possibly changes it -1: - push {lr} // 16-bit instruction - bl __dcp_save_state // 32-bit instruction - b 1f // 16-bit instruction - -@ r0:r1 m -@ r2:r3 n -@ [r13,#0] a -regular_func mla - mov r12,sp @ save the SP - PCMP apsr_nzcv @ test the engaged flag - bmi 1b -1: - push {r4,r5,r14} - dcp_dmul_m r0,r1,r0,r1,r2,r3,r0,r1,r2,r3,r4,r5,r14 - ldrd r2,r3,[r12,#0] @ fetch a using original SP - dcp_dadd_m r0,r1,r0,r1,r2,r3 -// todo optimize this based on final decision on saving_func_entry - pop {r4,r5,r14} - saving_func_return - -#endif diff --git a/lib/main/pico-sdk/rp2_common/pico_double/double_init_rom_rp2040.c b/lib/main/pico-sdk/rp2_common/pico_double/double_init_rom_rp2040.c deleted file mode 100644 index af958358ce..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_double/double_init_rom_rp2040.c +++ /dev/null @@ -1,72 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include "pico/bootrom.h" -#include "pico/bootrom/sf_table.h" - -// NOTE THIS FUNCTION TABLE IS NOT PUBLIC OR NECESSARILY COMPLETE... -// IT IS ***NOT*** SAFE TO CALL THESE FUNCTION POINTERS FROM ARBITRARY CODE -uint32_t sd_table[SF_TABLE_V2_SIZE / 2]; - -#if !(PICO_DOUBLE_SUPPORT_ROM_V1 && PICO_RP2040_B0_SUPPORTED) -static __attribute__((noreturn)) void missing_double_func_shim(void) { - panic("missing double function"); -} -#endif -extern void double_table_shim_on_use_helper(void); - -void __attribute__((weak)) *sf_clz_func; - -void __aeabi_double_init(void) { - int rom_version = rp2040_rom_version(); -#if PICO_DOUBLE_SUPPORT_ROM_V1 && PICO_RP2040_B0_SUPPORTED - if (rom_version == 1) { - - // this is a little tricky.. we only want to pull in a shim if the corresponding function - // is called. to that end we include a SVC instruction with the table offset as the call number - // followed by the shim function pointer inside the actual wrapper function. that way if the wrapper - // function is garbage collected, so is the shim function. - // - // double_table_shim_on_use_helper expects this SVC instruction in the calling code soon after the address - // pointed to by IP and patches the double_table entry with the real shim the first time the function is called. - for(uint i=0; i= 2) { - void *rom_table_double = rom_data_lookup(rom_table_code('S', 'D')); - void *rom_table_float = rom_data_lookup(rom_table_code('S', 'F')); - assert(*((uint8_t *)(((void *)rom_table_float)-2)) * 4 >= SF_TABLE_V2_SIZE); - (void)rom_table_float; - memcpy(&sd_table, rom_table_double, SF_TABLE_V2_SIZE); - if (rom_version == 2) { -#ifndef NDEBUG - if (*(uint16_t *)0x3854 != 0xb500 || // this is dsincos(_internal) - - *(uint16_t *)0x38d8 != 0x4649 || // this is dsin_finish - *(uint16_t *)0x389c != 0x4659 // this is dcos_finish - ) { - panic(NULL); - } -#endif - } - } - if (rom_version < 3) { - // we use the unused entry for SINCOS - sd_table[SF_TABLE_V3_FSINCOS / 4] = (uintptr_t) double_table_shim_on_use_helper; - } - - sf_clz_func = rom_func_lookup(ROM_FUNC_CLZ32); -} diff --git a/lib/main/pico-sdk/rp2_common/pico_double/double_math.c b/lib/main/pico-sdk/rp2_common/pico_double/double_math.c deleted file mode 100644 index 26ff1f40c0..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_double/double_math.c +++ /dev/null @@ -1,626 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include "pico/double.h" - -// opened a separate issue https://github.com/raspberrypi/pico-sdk/issues/166 to deal with these warnings if at all -GCC_Pragma("GCC diagnostic push") -GCC_Pragma("GCC diagnostic ignored \"-Wconversion\"") -GCC_Pragma("GCC diagnostic ignored \"-Wsign-conversion\"") - -typedef uint64_t ui64; -typedef uint32_t ui32; -typedef int64_t i64; - -#define PINF ( HUGE_VAL) -#define MINF (-HUGE_VAL) -#define PZERO (+0.0) -#define MZERO (-0.0) - - -#define PI 3.14159265358979323846 -#define LOG2 0.69314718055994530941 -// Unfortunately in double precision ln(10) is very close to half-way between to representable numbers -#define LOG10 2.30258509299404568401 -#define LOG2E 1.44269504088896340737 -#define LOG10E 0.43429448190325182765 -#define ONETHIRD 0.33333333333333333333 - -#define PIf 3.14159265358979323846f -#define LOG2f 0.69314718055994530941f -#define LOG2Ef 1.44269504088896340737f -#define LOG10Ef 0.43429448190325182765f -#define ONETHIRDf 0.33333333333333333333f - -#define DUNPACK(x,e,m) e=((x)>>52)&0x7ff,m=((x)&0x000fffffffffffffULL)|0x0010000000000000ULL -#define DUNPACKS(x,s,e,m) s=((x)>>63),DUNPACK((x),(e),(m)) - -typedef union { - double d; - ui64 ix; -} double_ui64; - -static inline double ui642double(ui64 ix) { - double_ui64 tmp; - tmp.ix = ix; - return tmp.d; -} - -static inline ui64 double2ui64(double d) { - double_ui64 tmp; - tmp.d = d; - return tmp.ix; -} - -#if PICO_DOUBLE_PROPAGATE_NANS -static inline bool disnan(double x) { - ui64 ix= double2ui64(x); - // checks the top bit of the low 32 bit of the NAN, but it I think that is ok - return ((uint32_t)(ix >> 31)) > 0xffe00000u; -} - -#define check_nan_d1(x) if (disnan((x))) return (x) -#define check_nan_d2(x,y) if (disnan((x))) return (x); else if (disnan((y))) return (y); -#else -#define check_nan_d1(x) ((void)0) -#define check_nan_d2(x,y) ((void)0) -#endif - -static inline int dgetsignexp(double x) { - ui64 ix=double2ui64(x); - return (ix>>52)&0xfff; -} - -static inline int dgetexp(double x) { - ui64 ix=double2ui64(x); - return (ix>>52)&0x7ff; -} - -static inline double dldexp(double x,int de) { - ui64 ix=double2ui64(x),iy; - int e; - e=dgetexp(x); - if(e==0||e==0x7ff) return x; - e+=de; - if(e<=0) iy=ix&0x8000000000000000ULL; // signed zero for underflow - else if(e>=0x7ff) iy=(ix&0x8000000000000000ULL)|0x7ff0000000000000ULL; // signed infinity on overflow - else iy=ix+((ui64)de<<52); - return ui642double(iy); -} - -double WRAPPER_FUNC(ldexp)(double x, int de) { - check_nan_d1(x); - return dldexp(x, de); -} - - -static inline double dcopysign(double x,double y) { - ui64 ix=double2ui64(x),iy=double2ui64(y); - ix=((ix&0x7fffffffffffffffULL)|(iy&0x8000000000000000ULL)); - return ui642double(ix); -} - -double WRAPPER_FUNC(copysign)(double x, double y) { - check_nan_d2(x,y); - return dcopysign(x, y); -} -static inline int diszero(double x) { return dgetexp (x)==0; } -//static inline int dispzero(double x) { return dgetsignexp(x)==0; } -//static inline int dismzero(double x) { return dgetsignexp(x)==0x800; } -static inline int disinf(double x) { return dgetexp (x)==0x7ff; } -static inline int dispinf(double x) { return dgetsignexp(x)==0x7ff; } -static inline int disminf(double x) { return dgetsignexp(x)==0xfff; } - -static inline int disint(double x) { - ui64 ix=double2ui64(x),m; - int e=dgetexp(x); - if(e==0) return 1; // 0 is an integer - e-=0x3ff; // remove exponent bias - if(e<0) return 0; // |x|<1 - e=52-e; // bit position in mantissa with significance 1 - if(e<=0) return 1; // |x| large, so must be an integer - m=(1ULL<>e)&1; -} - -static inline int disstrictneg(double x) { - ui64 ix=double2ui64(x); - if(diszero(x)) return 0; - return ix>>63; -} - -static inline int disneg(double x) { - ui64 ix=double2ui64(x); - return ix>>63; -} - -static inline double dneg(double x) { - ui64 ix=double2ui64(x); - ix^=0x8000000000000000ULL; - return ui642double(ix); -} - -static inline int dispo2(double x) { - ui64 ix=double2ui64(x); - if(diszero(x)) return 0; - if(disinf(x)) return 0; - ix&=0x000fffffffffffffULL; - return ix==0; -} - -static inline double dnan_or(double x) { -#if PICO_DOUBLE_PROPAGATE_NANS - return NAN; -#else - return x; -#endif -} - -double WRAPPER_FUNC(trunc)(double x) { - check_nan_d1(x); - ui64 ix=double2ui64(x),m; - int e=dgetexp(x); - e-=0x3ff; // remove exponent bias - if(e<0) { // |x|<1 - ix&=0x8000000000000000ULL; - return ui642double(ix); - } - e=52-e; // bit position in mantissa with significance 1 - if(e<=0) return x; // |x| large, so must be an integer - m=(1ULL<=5+0x3ff) { // |x|>=32? - if(!disneg(x)) return 1; // 1 << exp 2x; avoid generating infinities later - else return -1; // 1 >> exp 2x - } - u=exp(dldexp(x,1)); - return (u-1)/(u+1); -} - -double WRAPPER_FUNC(asinh)(double x) { - check_nan_d1(x); - int e; - e=dgetexp(x); - if(e>=32+0x3ff) { // |x|>=2^32? - if(!disneg(x)) return log( x )+LOG2; // 1/x^2 << 1 - else return dneg(log(dneg(x))+LOG2); // 1/x^2 << 1 - } - if(x>0) return log(sqrt(x*x+1)+x); - else return dneg(log(sqrt(x*x+1)-x)); -} - -double WRAPPER_FUNC(acosh)(double x) { - check_nan_d1(x); - int e; - if(disneg(x)) x=dneg(x); - e=dgetexp(x); - if(e>=32+0x3ff) return log(x)+LOG2; // |x|>=2^32? - return log(sqrt((x-1)*(x+1))+x); -} - -double WRAPPER_FUNC(atanh)(double x) { - check_nan_d1(x); - return dldexp(log((1+x)/(1-x)),-1); -} - -double WRAPPER_FUNC(exp2)(double x) { - check_nan_d1(x); - int e; - // extra check for disminf as this catches -Nan, and x<=-4096 doesn't. - if (disminf(x) || x<=-4096) return 0; // easily underflows - else if (x>=4096) return PINF; // easily overflows - e=(int)round(x); - x-=e; - return dldexp(exp(x*LOG2),e); -} -double WRAPPER_FUNC(log2)(double x) { check_nan_d1(x); return log(x)*LOG2E; } -double WRAPPER_FUNC(exp10)(double x) { check_nan_d1(x); return pow(10,x); } -double WRAPPER_FUNC(log10)(double x) { check_nan_d1(x); return log(x)*LOG10E; } - -// todo these are marked as lofi -double WRAPPER_FUNC(expm1)(double x) { check_nan_d1(x); return exp(x)-1; } -double WRAPPER_FUNC(log1p)(double x) { check_nan_d1(x); return log(1+x); } -#if !HAS_DOUBLE_COPROCESSOR -double WRAPPER_FUNC(fma)(double x,double y,double z) { check_nan_d1(x); return x*y+z; } -#endif - -// general power, x>0, finite -static double dpow_1(double x,double y) { - int a,b,c; - double t,rt,u,v,v0,v1,w,ry; - a=dgetexp(x)-0x3ff; - u=log2(dldexp(x,-a)); // now log_2 x = a+u - if(u>0.5) u-=1,a++; // |u|<=~0.5 - if(a==0) return exp2(u*y); - // here |log_2 x| >~0.5 - if(y>= 4096) { // then easily over/underflows - if(a<0) return 0; - return PINF; - } - if(y<=-4096) { // then easily over/underflows - if(a<0) return PINF; - return 0; - } - ry=round(y); - v=y-ry; - v0=dldexp(round(ldexp(v,26)),-26); - v1=v-v0; - b=(int)ry; // guaranteed to fit in an int; y=b+v0+v1 - // now the result is exp2( (a+u) * (b+v0+v1) ) - c=a*b; // integer - t=a*v0; - rt=round(t); - c+=(int)rt; - w=t-rt; - t=a*v1; - w+=t; - t=u*b; - rt=round(t); - c+=(int)rt; - w+=t-rt; - w+=u*v; - return dldexp(exp2(w),c); -} - -static double dpow_int2(double x,int y) { - double u; - if(y==1) return x; - u=dpow_int2(x,y/2); - u*=u; - if(y&1) u*=x; - return u; -} - -// for the case where x not zero or infinity, y small and not zero -static inline double dpowint_1(double x,int y) { - if(y<0) x=1/x,y=-y; - return dpow_int2(x,y); -} - -// for the case where x not zero or infinity -static double dpowint_0(double x,int y) { - int e; - if(disneg(x)) { - if(disoddint(y)) return dneg(dpowint_0(dneg(x),y)); - else return dpowint_0(dneg(x),y); - } - if(dispo2(x)) { - e=dgetexp(x)-0x3ff; - if(y>=2048) y= 2047; // avoid overflow - if(y<-2048) y=-2048; - y*=e; - return dldexp(1,y); - } - if(y==0) return 1; - if(y>=-32&&y<=32) return dpowint_1(x,y); - return dpow_1(x,y); -} - -double WRAPPER_FUNC(powint)(double x,int y) { - GCC_Like_Pragma("GCC diagnostic push") - GCC_Like_Pragma("GCC diagnostic ignored \"-Wfloat-equal\"") - if(x==1.0||y==0) return 1; - GCC_Like_Pragma("GCC diagnostic pop") - check_nan_d1(x); - if(diszero(x)) { - if(y>0) { - if(y&1) return x; - else return 0; - } - if((y&1)) return dcopysign(PINF,x); - return PINF; - } - if(dispinf(x)) { - if(y<0) return 0; - else return PINF; - } - if(disminf(x)) { - if(y>0) { - if((y&1)) return MINF; - else return PINF; - } - if((y&1)) return MZERO; - else return PZERO; - } - return dpowint_0(x,y); -} - -// for the case where y is guaranteed a finite integer, x not zero or infinity -static double dpow_0(double x,double y) { - int e,p; - if(disneg(x)) { - if(disoddint(y)) return dneg(dpow_0(dneg(x),y)); - else return dpow_0(dneg(x),y); - } - p=(int)y; - if(dispo2(x)) { - e=dgetexp(x)-0x3ff; - if(p>=2048) p= 2047; // avoid overflow - if(p<-2048) p=-2048; - p*=e; - return dldexp(1,p); - } - if(p==0) return 1; - if(p>=-32&&p<=32) return dpowint_1(x,p); - return dpow_1(x,y); -} - -double WRAPPER_FUNC(pow)(double x,double y) { - GCC_Like_Pragma("GCC diagnostic push") - GCC_Like_Pragma("GCC diagnostic ignored \"-Wfloat-equal\"") - - if(x==1.0||diszero(y)) return 1; - check_nan_d2(x, y); - if(x==-1.0&&disinf(y)) return 1; - GCC_Like_Pragma("GCC diagnostic pop") - - if(diszero(x)) { - if(!disneg(y)) { - if(disoddint(y)) return x; - else return 0; - } - if(disoddint(y)) return dcopysign(PINF,x); - return PINF; - } - if(dispinf(x)) { - if(disneg(y)) return 0; - else return PINF; - } - if(disminf(x)) { - if(!disneg(y)) { - if(disoddint(y)) return MINF; - else return PINF; - } - if(disoddint(y)) return MZERO; - else return PZERO; - } - if(dispinf(y)) { - if(dgetexp(x)<0x3ff) return PZERO; - else return PINF; - } - if(disminf(y)) { - if(dgetexp(x)<0x3ff) return PINF; - else return PZERO; - } - if(disint(y)) return dpow_0(x,y); - if(disneg(x)) return PINF; - return dpow_1(x,y); -} - -double WRAPPER_FUNC(hypot)(double x,double y) { - check_nan_d2(x, y); - int ex,ey; - ex=dgetexp(x); ey=dgetexp(y); - if(ex>=0x3ff+400||ey>=0x3ff+400) { // overflow, or nearly so - x=dldexp(x,-600),y=dldexp(y,-600); - return dldexp(sqrt(x*x+y*y), 600); - } - else if(ex<=0x3ff-400&&ey<=0x3ff-400) { // underflow, or nearly so - x=dldexp(x, 600),y=dldexp(y, 600); - return dldexp(sqrt(x*x+y*y),-600); - } - return sqrt(x*x+y*y); -} - -double WRAPPER_FUNC(cbrt)(double x) { - check_nan_d1(x); - int e; - if(disneg(x)) return dneg(cbrt(dneg(x))); - if(diszero(x)) return dcopysign(PZERO,x); - e=dgetexp(x)-0x3ff; - e=(e*0x5555+0x8000)>>16; // ~e/3, rounded - x=dldexp(x,-e*3); - x=exp(log(x)*ONETHIRD); - return dldexp(x,e); -} - -// reduces mx*2^e modulo my, returning bottom bits of quotient at *pquo -// 2^52<=|mx|,my<2^53, e>=0; 0<=result0) { - r=0xffffffffU/(ui32)(my>>36); // reciprocal estimate Q16 - } - while(e>0) { - s=e; if(s>12) s=12; // gain up to 12 bits on each iteration - q=(mx>>38)*r; // Q30 - q=((q>>(29-s))+1)>>1; // Q(s), rounded - mx=(mx<=my) mx-=my,quo++; // when e==0 mx can be nearly as big as 2my - if(mx>=my) mx-=my,quo++; - if(mx<0) mx+=my,quo--; - if(mx<0) mx+=my,quo--; - if(pquo) *pquo=quo; - return mx; -} - -double WRAPPER_FUNC(fmod)(double x,double y) { - check_nan_d2(x, y); - ui64 ix=double2ui64(x),iy=double2ui64(y); - int sx,ex,ey; - i64 mx,my; - DUNPACKS(ix,sx,ex,mx); - DUNPACK(iy,ey,my); - if(ex==0x7ff) return dnan_or(PINF); - if(ey==0) return PINF; - if(ex==0) { - if(!disneg(x)) return PZERO; - return MZERO; - } - if(ex|y|/2 - mx-=my+my; - ey--; - q=1; - } else { // x<-|y|/2 - mx=my+my-mx; - ey--; - q=-1; - } - } - else { - if(sx) mx=-mx; - mx=drem_0(mx,my,ex-ey,&q); - if(mx+mx>my || (mx+mx==my&&(q&1)) ) { // |x|>|y|/2, or equality and an odd quotient? - mx-=my; - q++; - } - } - if(sy) q=-q; - if(quo) *quo=q; - return fix642double(mx,0x3ff-ey+52); -} - -double WRAPPER_FUNC(drem)(double x,double y) { check_nan_d2(x, y); return remquo(x,y,0); } - -double WRAPPER_FUNC(remainder)(double x,double y) { check_nan_d2(x, y); return remquo(x,y,0); } - -GCC_Pragma("GCC diagnostic pop") // conversion \ No newline at end of file diff --git a/lib/main/pico-sdk/rp2_common/pico_double/double_none.S b/lib/main/pico-sdk/rp2_common/pico_double/double_none.S deleted file mode 100644 index 3ff0b30805..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_double/double_none.S +++ /dev/null @@ -1,85 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "pico/asm_helper.S" -#include "pico/bootrom/sf_table.h" - -pico_default_asm_setup - - wrapper_func __aeabi_dadd - wrapper_func __aeabi_ddiv - wrapper_func __aeabi_dmul - wrapper_func __aeabi_drsub - wrapper_func __aeabi_dsub - wrapper_func __aeabi_cdcmpeq - wrapper_func __aeabi_cdrcmple - wrapper_func __aeabi_cdcmple - wrapper_func __aeabi_dcmpeq - wrapper_func __aeabi_dcmplt - wrapper_func __aeabi_dcmple - wrapper_func __aeabi_dcmpge - wrapper_func __aeabi_dcmpgt - wrapper_func __aeabi_dcmpun - wrapper_func __aeabi_i2d - wrapper_func __aeabi_l2d - wrapper_func __aeabi_ui2d - wrapper_func __aeabi_ul2d - wrapper_func __aeabi_d2iz - wrapper_func __aeabi_d2lz - wrapper_func __aeabi_d2uiz - wrapper_func __aeabi_d2ulz - wrapper_func __aeabi_d2f - wrapper_func sqrt - wrapper_func cos - wrapper_func sin - wrapper_func tan - wrapper_func atan2 - wrapper_func exp - wrapper_func log - - wrapper_func ldexp - wrapper_func copysign - wrapper_func trunc - wrapper_func floor - wrapper_func ceil - wrapper_func round - wrapper_func sincos - wrapper_func asin - wrapper_func acos - wrapper_func atan - wrapper_func sinh - wrapper_func cosh - wrapper_func tanh - wrapper_func asinh - wrapper_func acosh - wrapper_func atanh - wrapper_func exp2 - wrapper_func log2 - wrapper_func exp10 - wrapper_func log10 - wrapper_func pow - wrapper_func powint - wrapper_func hypot - wrapper_func cbrt - wrapper_func fmod - wrapper_func drem - wrapper_func remainder - wrapper_func remquo - wrapper_func expm1 - wrapper_func log1p - wrapper_func fma - -#ifdef __riscv - la a0, str - j panic -#else - push {lr} // keep stack trace sane - ldr r0, =str - bl panic -#endif - -str: - .asciz "double support is disabled" \ No newline at end of file diff --git a/lib/main/pico-sdk/rp2_common/pico_double/double_sci_m33.S b/lib/main/pico-sdk/rp2_common/pico_double/double_sci_m33.S deleted file mode 100644 index bb41975aa9..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_double/double_sci_m33.S +++ /dev/null @@ -1,1518 +0,0 @@ -/* - * Copyright (c) 2024 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#if !PICO_RP2040 -#include "pico/asm_helper.S" - -pico_default_asm_setup - -.macro double_section name -#if PICO_DOUBLE_IN_RAM -.section RAM_SECTION_NAME(\name), "ax" -#else -.section SECTION_NAME(\name), "ax" -#endif -.endm - -.macro double_wrapper_section func -double_section WRAPPER_FUNC_NAME(\func) -.endm - -.global rtwopi -.global logtab0 -.global exptab0 -.global exptab1 -.global exptab2 -.global trigtab - -@ load a 32-bit constant n into register rx -.macro movlong rx,n - movw \rx,#(\n)&0xffff - movt \rx,#((\n)>>16)&0xffff -.endm - -double_section rtwopi - -// 1/2π to plenty of accuracy, 256 bits per line -.long 0 @ this allows values of e down to -32 -rtwopi: -.long 0,0 -.long 0x28BE60DB, 0x9391054A, 0x7F09D5F4, 0x7D4D3770, 0x36D8A566, 0x4F10E410, 0x7F9458EA, 0xF7AEF158 -.long 0x6DC91B8E, 0x909374B8, 0x01924BBA, 0x82746487, 0x3F877AC7, 0x2C4A69CF, 0xBA208D7D, 0x4BAED121 -.long 0x3A671C09, 0xAD17DF90, 0x4E64758E, 0x60D4CE7D, 0x272117E2, 0xEF7E4A0E, 0xC7FE25FF, 0xF7816603 -.long 0xFBCBC462, 0xD6829B47, 0xDB4D9FB3, 0xC9F2C26D, 0xD3D18FD9, 0xA797FA8B, 0x5D49EEB1, 0xFAF97C5E -.long 0xCF41CE7D, 0xE294A4BA, 0x9AFED7EC, 0x47E35742, 0x1580CC11 - -double_section drrcore - -@ input: -@ r0:r1 mantissa m Q52 -@ r2 exponent e>=-32, typically offset by +12 -@ r3 pointer to rtwopi table -@ output: -@ r0..r2 preserved -@ r7:r8 range reduced result -@ r3,r4,r5,r6,r9,r10 trashed -.thumb_func -drr_core: - ldr r3,=rtwopi - and r5,r2,#31 @ s=e%32 - mov r7,#1 - lsls r7,r7,r5 @ 1< +2 quadrants - ands r12,#4 - b 1f - -wrapper_func cos - movs r12,#2 @ cos -> +1 quadrant -1: - ubfx r3,r1,#20,#11 @ get exponent - sub r2,r3,#0x3ff - cmp r2,#0x400 - beq 10b @ Inf or NaN? - cmn r2,#32 - blt 32b @ very small argument? - movs r3,#1 - bfi r1,r3,#20,#12 @ fix implied 1 in mantissa - push {r4-r10,r14} - add r2,#12 @ e+12 - bl drr_core -@ r7:r8 θ/2π 0..1 Q64 - lsrs r4,r8,#30 @ quadrant count - adc r4,r4,#0 @ rounded - sub r8,r8,r4,lsl#30 @ now -0.125≤r7:r8<+0.125 Q64 - add r12,r12,r4,lsl#1 - orr r12,r12,r8,lsr#31 @ sign into r12b0 -@ r12b2..1: quadrant count -@ r12b0: sign of reduced angle - eors r7,r7,r8,asr#31 - eors r8,r8,r8,asr#31 @ absolute value of reduced angle 0≤r7:r8<0.125 Q64 - cmp r8,#1<<22 @ < 2^-10? - blo 40b - -@ 2π=6.487ED511 0B4611A6 (2633...) - movlong r9,0x0B4611A6 @ 2π Q64 low fractional word - umull r10,r0,r8,r9 - movlong r9,0x487ED511 @ 2π Q64 high fractional word - umull r10,r1,r7,r9 - umaal r0,r1,r8,r9 - movs r9,#6 @ 2π integer part - umlal r0,r1,r7,r9 - mla r1,r8,r9,r1 -@ r0:r1 range reduced angle θ 0..π/4 Q64 - - cmp r1,#1<<25 @ θ < 2^-7? - blo 30b - lsrs r2,r1,#27 - ldr r3,=trigtab - add r3,r3,r2,lsl#4 - ldmia r3,{r2-r5} -31: - subs r0,r0,r2 - sbcs r1,r1,r3 @ ε=Θ-φ Q64 - bmi 2f @ ε negative? - - asrs r6,r12,#1 - bmi 5f @ doing dsincos? - asrs r6,#1 - bcs 3f @ need cosine? - -@ here ε is positive, we need the sin of θ and the sign of the result is r12b0^r12b2 - bl dsc_h0 - bl dsc_h0s - bl dpack_q63 -21: - eors r12,r12,r12,lsr#2 - orrs r1,r1,r12,lsl#31 @ insert sign - pop {r4-r10,r15} - -2: - asrs r6,r12,#1 - bmi 6f @ doing dsincos? - asrs r6,#1 - bcs 4f @ need cosine? - -@ here ε is negative, we need the sin of θ and the sign of the result is r12b0^r12b2 - bl dsc_h1 - bl dsc_h1s - bl dnegpack_q63 - eors r12,r12,r12,lsr#2 - orrs r1,r1,r12,lsl#31 @ insert sign - pop {r4-r10,r15} - -@ here ε is positive, we need the cos of θ and the sign of the result is r12b2 -3: - bl dsc_h0 - bl dsc_h0c - bl dnegpack_q63 -22: - ands r12,#4 - orrs r1,r1,r12,lsl#29 @ insert sign - pop {r4-r10,r15} - -@ here ε is negative, we need the cos of θ and the sign of the result is r12b2 -4: - bl dsc_h1 - bl dsc_h1c -15: - bl dpack_q63 - ands r12,#4 - orrs r1,r1,r12,lsl#29 @ insert sign - pop {r4-r10,r15} - -5: -@ dsincos, ε positive - bl dsc_h0 - push {r2-r7} - bl dsc_h0c - bl dnegpack_q63 - ands r4,r12,#4 - eors r1,r1,r4,lsl#29 @ negate cosine in quadrants 2 and 3 - pop {r2-r7} - push {r0,r1} - bl dsc_h0s - bl dpack_q63 -20: - eors r4,r12,r12,lsr#1 - eors r4,r4,r12,lsr#2 - eors r1,r1,r4,lsl#31 @ negate sine on b0^b1^b2 - tst r12,#2 @ exchange sine and cosine in odd quadrants - ittte ne - movne r2,r0 - movne r3,r1 - popne {r0,r1} - popeq {r2,r3} - ands r4,r12,#1<<30 - eors r1,r1,r4,lsl#1 @ negate sine result if argument was negative - pop {r4-r10,r15} - -6: -@ dsincos, ε negative - bl dsc_h1 - push {r2-r7} - bl dsc_h1c - bl dpack_q63 - ands r4,r12,#4 - eors r1,r1,r4,lsl#29 @ negate cosine in quadrants 2 and 3 - pop {r2-r7} - push {r0,r1} - bl dsc_h1s - bl dnegpack_q63 - b 20b - -@ sin/cos power series for negative ε -dsc_h1: - rsbs r0,r0,#0 - sbc r1,r1,r1,lsl#1 -@ drop into positive ε code - -@ sin/cos power series for positive ε -dsc_h0: -@ r0:r1 ε Q64 -@ r4: sin φ Q32 -@ r5: cos φ Q32 - umull r6,r7,r1,r1 - umull r2,r3,r0,r1 - lsrs r7,#1 - rrx r6,r6 - adds r2,r6,r3 - adc r3,r7,#0 -@ r2:r3 ε²/2 Q64 - umull r7,r6,r3,r0 - umlal r7,r6,r2,r1 - movs r7,#0 - umlal r6,r7,r3,r1 -@ r6:r7 ε³/2 Q64 - mov r8,#0x55555555 - umull r9,r6,r6,r8 - mov r9,#0 - umlal r6,r9,r7,r8 - adds r6,r6,r9 - adcs r7,r9,#0 -@ r6:r7 ε³/6 Q64 - subs r6,r0,r6 - sbcs r7,r1,r7 -@ r6:r7 ε-ε³/6 Q64 - mov r0,r3,lsl#12 @ ε²/2 Q44 - orr r0,r0,r2,lsr#20 - umull r0,r9,r0,r0 @ r9: ε⁴/4 Q88-32=Q56 = ε⁴/32 Q59 - umlal r0,r9,r9,r8 @ r9: ε⁴/24 Q59 - - umull r0,r8,r9,r1 @ ε⁵/24 Q59 - mov r0,#0x33333333 - umull r0,r8,r8,r0 @ r8: ε⁵/120 Q59 -@ r6:r7 ε-ε³/6+ε⁵/120 Q64 - smmulr r10,r8,r1 @ r10: ε⁶/120 Q59 - movlong r0,0x2aaaaaaa - smmlsr r9,r0,r10,r9 @ ε⁴/24-ε⁶/720 - subs r2,r2,r9,lsl#5 - sbcs r3,r3,r9,lsr#27 -@ r2:r3 ε²/2-ε⁴/24+ε⁶/720 Q64 - smmulr r10,r10,r1 @ r10: ε⁷/120 Q59 - mov r0,#0x6180000 @ 1/42 Q64 - smmlsr r8,r10,r0,r8 @ r8: ε⁵/120-ε⁷/5040 Q59 - adds r6,r6,r8,lsl#5 - adcs r7,r7,r8,lsr#27 - bx r14 - -dsc_h0s: -@ postprocess for sine, positive ε -@ r2:r3 1-cos |ε| Q64 -@ r4: sin φ Q31 -@ r5: cos φ Q31 -@ r6:r7 sin |ε| Q64 - umull r8,r0,r2,r4 - mov r1,#0 - umlal r0,r1,r3,r4 -@ r0:r1 sin φ(1-cos ε) - umull r8,r3,r6,r5 - umlal r3,r4,r7,r5 -@ r3:r4 sin φ+cos φ.sin ε - subs r0,r3,r0 - sbc r1,r4,r1 -@ r0:r1 sin φ+cos φ.sin ε - sin φ(1-cos ε) = sin φ.cos ε + cos φ.sin ε = sin(φ+ε) - bx r14 - -dsc_h1s: -@ postprocess for sine, negative ε -@ r2:r3 1-cos |ε| Q64 -@ r4: sin φ Q31 -@ r5: cos φ Q31 -@ r6:r7 sin |ε| Q64 - umull r8,r0,r2,r4 - mov r1,#0 - umlal r0,r1,r3,r4 -@ r0:r1 sin φ(1-cos ε) - umull r8,r3,r6,r5 - rsbs r4,r4,#0 - umlal r3,r4,r7,r5 -@ r3:r4 -sin φ-cos φ.sin ε - adds r0,r3,r0 - adc r1,r4,r1 -@ r0:r1 -sin φ-cos φ.sin ε + sin φ(1-cos ε) = -sin φ.cos ε - cos φ.sin ε = -sin(φ+ε) - bx r14 - -dsc_h0c: -@ postprocess for cosine, positive ε -@ r2:r3 1-cos |ε| Q64 -@ r4: sin φ Q32 -@ r5: cos φ Q32 -@ r6:r7 sin |ε| Q64 - umull r8,r0,r2,r5 - mov r1,#0 - umlal r0,r1,r3,r5 -@ r0:r1 cos φ(1-cos ε) - umull r8,r3,r6,r4 - rsbs r5,#0 - umlal r3,r5,r7,r4 -@ r3:r5 -cos φ+sin φ.sin ε - adds r0,r3,r0 - adc r1,r5,r1 -@ r0:r1 -cos φ+sin φ.sin ε + cos φ(1-cos ε) = - cos φ.cos ε + sin φ.sin ε = -cos(φ+ε) - bx r14 - -dsc_h1c: -@ postprocess for cosine, negative ε -@ r2:r3 1-cos |ε| Q64 -@ r4: sin φ Q32 -@ r5: cos φ Q32 -@ r6:r7 sin |ε| Q64 - umull r8,r0,r2,r5 - mov r1,#0 - umlal r0,r1,r3,r5 -@ r0:r1 cos φ(1-cos ε) - umull r8,r3,r6,r4 - umlal r3,r5,r7,r4 -@ r3:r5 cos φ-sin φ.sin ε - subs r0,r3,r0 - sbc r1,r5,r1 -@ r0:r1 cos φ-sin φ.sin ε - cos φ(1-cos ε) = cos φ.cos ε - sin φ.sin ε = cos(φ+ε) - bx r14 - -double_section dpack - -@ dnegpack: negate and pack -@ dpack_q63: -@ input -@ r0:r1 Q63 result, must not be zero -@ r4 exponent offset [dpack_q only] -@ output -@ r0:r1 IEEE double -@ trashes r2,r3,r4 -.thumb_func -dnegpack_q63: - rsbs r0,r0,#0 - sbc r1,r1,r1,lsl#1 -.thumb_func -dpack_q63: - mov r4,#0x3ff-12 @ exponent -.thumb_func -dpack_q: - clz r2,r1 - cmp r2,#12 - bhs 1f - adds r2,#21 - lsls r3,r1,r2 - rsb r2,#32 - lsrs r0,r0,r2 @ save rounding bit in carry - lsr r1,r1,r2 - add r2,r2,r4 - adcs r0,r0,r3 @ with rounding - adc r1,r1,r2,lsl#20 @ insert exponent - bx r14 - -1: - cbz r1,2f - rsb r2,#43 - lsrs r3,r0,r2 - rsb r2,#32 - lsls r1,r1,r2 - lsls r0,r0,r2 - orrs r1,r3 - sub r2,r4,r2 - add r1,r1,r2,lsl#20 - bx r14 - -2: - movs r1,r0 - mov r0,#0 - sub r4,#32 - bne dpack_q - bx r14 - - - -double_section dreduce - -@ input: -@ r0:r1 x, double (only mantissa bits used) -@ r2 quotient offset -@ r3 exponent e of x with 0x3ff bias removed, -32≤e<12 so 2^-32≤x<2^12 -@ r4:r5 r Q64, 0.5≤r<1 -@ r6 1/r underestimate Q31 -@ output: -@ r0:r1 x mod r Q64 [possibly slightly > r?] -@ r2 quotient+offset -@ r4:r5 r preserved -@ trashes r7,r8 -@ increases r2 by up to 2^13 -@ this version only used by dexp -.thumb_func -dreduce: - movs r7,#1 - bfi r1,r7,#20,#12 @ insert implied 1, clear exponent and sign - lsls r8,r7,r3 - beq 1f @ e<0, x<1 - umull r0,r7,r0,r8 - mla r1,r1,r8,r7 -@ r0:r1 x Q52 - umull r7,r8,r1,r6 @ Q83-32=Q51 - lsrs r6,r8,#19 @ q Q0 - adds r2,r2,r6 - umull r7,r8,r6,r4 - mla r8,r6,r5,r8 @ r7:r8 q*r Q64 - lsls r1,#12 - orrs r1,r1,r0,lsr#20 - rsbs r0,r7,r0,lsl#12 - sbc r1,r1,r8 @ x-qr Q64 -@ check we never return slightly more than r - cmp r1,r5 @ quick comparison - it lo - bxlo r14 - b 2f - -1: - adds r3,#12 - movs r7,#1 - lsls r8,r7,r3 - beq 1f @ e<-12 - umull r0,r7,r0,r8 - mla r1,r1,r8,r7 @ x Q64 - cmp r1,r5 @ quick comparison - it lo - bxlo r14 -2: - it eq - cmpeq r0,r4 - it lo - bxlo r14 - subs r0,r0,r4 @ subtract one r - sbc r1,r1,r5 - adds r2,#1 - bx r14 - -1: -@ here e<-12, have to shift r0:r1 down by -r3 places - add r3,#32 - lsls r6,r1,r3 - rsbs r3,#32 - lsrs r0,r0,r3 - lsrs r1,r1,r3 - orrs r0,r0,r6 - bx r14 - -double_section exptab - -.align 2 -exptab0: -.quad 0x0000000000000000,0x0f85186008b15304,0x1e27076e2af2e5c8,0x2f57120421b2120d -.quad 0x3f7230dabc7c5512,0x4e993155a517a717,0x5fabe0ee0abf0d9d,0x6fad36769c6defe3 -.quad 0x7ebd623de3cc7b69,0x8f42faf3820681f0,0x9ec813538ab7d537,0xaf70154920b3ab7f -exptab1: -.quad 0x0000000000000000,0x00ff805515885e02,0x01fe02a6b1067890,0x02fb88ebf0214edc -.quad 0x03f815161f807c7a,0x04f3a910d1a95d3c,0x05ee46c1f56c46aa,0x06e7f009ebe465ff -.quad 0x07e0a6c39e0cc013,0x08d86cc491ecbfe1,0x09cf43dcff5eafd5,0x0ac52dd7e4726a46 -.quad 0x0bba2c7b196e7e23,0x0cae41876471f5bf,0x0da16eb88cb8df61,0x0e93b5c56d85a909 -.quad 0x0f85186008b15331,0x1075983598e47130 -exptab2: -.quad 0x000fff8005551559,0x002ffb808febc309,0x004ff3829a0e91b1,0x006fe78722fde71f -.quad 0x008fd78f299aa0c3,0x00afc39bac66434f,0x00cfabada9832a41,0x00ef8fc61eb4b74f -.quad 0x010f6fe6095f81b6,0x012f4c0e66898567,0x014f244032da521a,0x016ef87c6a9b3a48 -.quad 0x018ec8c409b781ff,0x01ae95180bbc8d9c,0x01ce5d796bda1070,0x01ee21e924e23b3a -logtab0: -.quad 0xa0ec7f4233957338,0x918986bdf5fa1431,0x8391f2e0e6fa026b,0x7751a813071282e6 -.quad 0x6a73b26a68212621,0x5fabe0ee0abf0d9d,0x546ab61cb7e0b419,0x48a507ef3de59695 -.quad 0x3c4e0edc55e5cbd1,0x32a4b539e8ad68ce,0x289a56d996fa3ccb,0x21aefcf9a11cb2c9 -.quad 0x16f0d28ae56b4b86,0x0f85186008b15304,0x07e0a6c39e0cc002,0x0000000000000000 - -.align 2 -exprrdata: -.quad 0xB17217F7D1CF79AC @ ln2 Q64 -.long 0xB8AA3B29 @ 1/ln2 Q31, rounded down - -double_wrapper_section exp - -2: -@ could use dadd macro to calculate x+1 here - lsl r0,r1,#11 - orr r0,#0x80000000 - lsls r1,#1 - adc r3,r3,#32 - movlong r1,0x3ff00000 - rsb r3,#11 - lsr r0,r3 - it cc - bxcc r14 - rsbs r0,#0 - sbc r1,r1,#0 - bx r14 - -wrapper_func exp - movs r12,r1,lsr#31 @ save sign - ubfx r3,r1,#20,#11 @ get exponent - sub r3,r3,#0x3ff - cmp r3,#12 - bge 20f @ overflow, Inf or NaN? - cmn r3,#0x20 - ble 2b @ <2^-32? return x+1 - push {r4-r8,r14} - ldr r4,=exprrdata - ldmia r4,{r4-r6} - mov r2,#0 - bl dreduce - tst r12,#1 - beq 1f - mvn r2,r2 @ quotient is now signed - subs r0,r4,r0 - sbc r1,r5,r1 -1: - add r12,r2,#0x3fe @ exponent offset - mov r3,#0x7fe - cmp r12,r3 - bhs 1f @ under/overflow - lsrs r2,r1,#28 - ldr r3,=exptab0 - add r3,r3,r2,lsl#3 - ldmia r3,{r2-r3} - and r5,r2,#63 - orr r5,#64 @ y=(t&0x3f)+0x40; Q6 - subs r0,r2 - sbcs r1,r3 - lsrs r2,r1,#24 - ldr r3,=exptab1 - add r3,r3,r2,lsl#3 - ldmia r3,{r3-r4} - add r2,#256 - muls r5,r5,r2 @ y Q14 - subs r0,r3 - sbcs r1,r4 - lsrs r2,r1,#21 - ldr r3,=exptab2 - add r3,r3,r2,lsl#3 - ldmia r3,{r3-r4} - add r2,r2,r2 - add r2,#4096 - mla r5,r5,r2,r5 @ y Q26 - subs r0,r3 - sbcs r1,r4 - - movs r2,r1,lsl#10 - orrs r2,r2,r0,lsr#22 - adc r2,r2,#0 @ ε Q42, rounded - smull r3,r4,r2,r2 @ ε² Q84-32=Q52 - lsrs r3,#21 - orrs r3,r3,r4,lsl#11 - adds r0,r0,r3 - adc r1,r1,r4,lsr#21 @ ε+ε²/2 Q64 - smull r3,r4,r4,r2 @ Q52*Q42=Q94; Q94-32=Q62 - mov r3,#0x55555555 @ 1/6 Q33 - smull r3,r4,r3,r4 @ ε³/6 Q63 - smmulr r3,r4,r1 @ ε⁴/6+ε⁵/12 Q63+Q32-32=Q63 - add r4,r4,r3,lsr#2 - adds r2,r0,r4,lsl#1 - adc r3,r1,r4,asr#31 - lsls r1,r5,#3 @ y Q29 - umull r4,r0,r1,r2 @ εlo * y Q61+32 - smlal r0,r1,r1,r3 @ εhi * y + y Q61 -@ assert result is in range 1..2 - lsrs r0,#9 - adcs r0,r0,r1,lsl#23 - lsr r1,#9 - adcs r1,r1,r12,lsl#20 - pop {r4-r8,r15} - -20: -@ process Inf/NaN for dexp - cmp r3,#0x400 - bne 22f - orrs r2,r0,r1,lsl#12 - ite eq - biceq r1,r1,r1,asr#31 @ +Inf -> + Inf; -Inf -> +0 - orrne r1,r1,#0x00080000 - bx r14 - -22: - movs r0,#0 - movs r1,#0 - tst r12,#1 - it eq - movteq r1,0x7ff0 - bx r14 - -1: @ under/overflow - mov r0,#0 - mov r1,#0 - it ge - movtge r1,#0x7ff0 - pop {r4-r8,r15} - - - - -double_wrapper_section log - -1: - movlong r1,0xfff00000 @ return -Inf - movs r0,#0 - bx r14 - -4: - orrs r2,r0,r1,lsl#12 - it ne - orrne r1,#0x00080000 - bx r14 - -10: - mvns r5,r6,asr#22 @ very small argument? - bne 10f - mov r4,#4096 - b 11f - -@ check for argument near 1: here -@ r1 : mantissa -@ r12: exponent, -1 or 0 -12: - eor r3,r12,r1,lsr#12 - lsls r3,r3,#24 @ check 8 bits of mantissa - bne 12f @ not very close to 1 - cmp r12,#0 - bne 13f -@ argument is 1+ε, result will be positive - lsls r1,#19 - orrs r1,r1,r0,lsr#13 - lsls r0,#19 -@ r0:r1 ε Q71 0≤ε<2^-8 - clz r4,r1 @ r4≥1 - cmp r4,#32 - bhs 14f - movs r5,#1 - lsls r5,r4 - umull r2,r3,r0,r5 - mla r3,r1,r5,r3 @ r2:r3 ε Q71+r4 - umull r12,r5,r0,r3 - umull r12,r6,r1,r2 - umaal r5,r6,r1,r3 @ r5:r6 ε² Q142+r4-64 = Q78+r4 - - subs r2,r2,r5,lsr#8 - sbc r3,r3,#0 - subs r2,r2,r6,lsl#24 - sbcs r3,r3,r6,lsr#8 - - umull r12,r7,r0,r6 - umull r12,r8,r1,r5 - umaal r7,r8,r1,r6 @ r7:r8 ε³ Q149+r4-64 = Q85+r4: when ε is nearly 2^-8, r4=1 and Q86, so r8<0x40000000 - mov r5,#0x55555555 @ ~1/3 Q32 - - umull r12,r6,r7,r5 - movs r12,#0 - umlal r6,r12,r8,r5 - adds r6,r6,r12 - adc r12,r12,#0 @ multiply by 0x5555555555555555 - - adds r2,r2,r6,lsr#14 - adc r3,r3,#0 - adds r2,r2,r12,lsl#18 - adc r3,r3,r12,lsr#14 - - smmulr r5,r8,r1 @ ε⁴ Q53+r4+Q71-Q64=Q60+r4 ~ 2^-32 - movs r7,#0x33333333 @ 1/5 Q32 - smmulr r6,r5,r1 @ ε⁵ Q60+r4+q71-Q64=Q67+r4 ~ 2^-40 - smmulr r8,r6,r7 @ ε⁵/5 Q67+r4 ~ 2^-42 - sub r7,r5,r8,lsr#5 - smmulr r5,r6,r1 @ ε⁶ Q67+r4+q71-Q64=Q74+r4 ~ 2^-48 - movt r6,#0x2a80 @ 1/6 Q32 fiddled slightly (PMC) - smmulr r5,r6,r5 @ ε⁶/6 Q75+r4 ~ 2^-50 - add r7,r7,r5,lsr#12 - - subs r0,r2,r7,lsl#9 - sbc r1,r3,r7,lsr#23 - - rsb r4,#0x400 - sub r4,#0x15 - bl dpack_q - pop {r4-r8,r15} - -@ here we have positive ε sufficiently small we need (at most) a quadratic term -14: -@ here r0=ε Q71, 0≤ε<2^-40 - clz r4,r0 - lsls r1,r0,r4 @ ε Q71+r4 - umull r2,r3,r0,r1 @ ε² Q142+r4 - mov r0,#0 - subs r0,r0,r3,lsr#8 - sbc r1,r1,#0 - rsb r4,#0x400 - sub r4,#0x35 - bl dpack_q - pop {r4-r8,r15} - - - -13: @ argument is 1-ε, result will be negative - movs r1,r1,lsl#18 - orrs r1,r1,r0,lsr#14 - movs r0,r0,lsl#18 - rsbs r0,#0 - sbc r1,r1,r1,lsl#1 -@ r0:r1 -ε Q71 -2^-9≤ε<0 - clz r4,r1 - cmp r4,#32 - bhs 15f - subs r4,#1 @ 0≤r4<31 - movs r5,#1 - lsls r5,r4 - umull r2,r3,r0,r5 - mla r3,r1,r5,r3 @ r2:r3 ε Q71+r4 - umull r12,r5,r0,r3 - umull r12,r6,r1,r2 - umaal r5,r6,r1,r3 @ r5:r6 ε² Q142+r4-64 = Q78+r4 - - adds r2,r2,r5,lsr#8 - adc r3,r3,#0 - adds r2,r2,r6,lsl#24 - adcs r3,r3,r6,lsr#8 - - umull r12,r7,r0,r6 - umull r12,r8,r1,r5 - umaal r7,r8,r1,r6 @ r7:r8 ε³ Q149+r4-64 = Q85+r4: when ε is nearly 2^-8, r4=0 and Q85, so r8<0x20000000 - mov r5,#0x55555555 @ ~1/3 Q32 - - umull r12,r6,r7,r5 - movs r12,#0 - umlal r6,r12,r8,r5 - adds r6,r6,r12 - adc r12,r12,#0 @ multiply by 0x5555555555555555 - - adds r2,r2,r6,lsr#14 - adc r3,r3,#0 - adds r2,r2,r12,lsl#18 - adc r3,r3,r12,lsr#14 - - smmulr r5,r8,r1 @ ε⁴ Q53+r4+Q71-Q64=Q60+r4 ~ 2^-32 - movs r7,#0x33333333 @ 1/5 Q32 - smmulr r6,r5,r1 @ ε⁵ Q60+r4+q71-Q64=Q67+r4 ~ 2^-40 - smmulr r8,r6,r7 @ ε⁵/5 Q67+r4 ~ 2^-42 - add r7,r5,r8,lsr#5 - smmulr r5,r6,r1 @ ε⁶ Q67+r4+q71-Q64=Q74+r4 ~ 2^-48 - movt r6,#0x2a80 @ 1/6 Q32 fiddled slightly (PMC) - smmulr r5,r6,r5 @ ε⁶/6 Q75+r4 ~ 2^-50 - add r7,r7,r5,lsr#12 - - adds r0,r2,r7,lsl#9 - adc r1,r3,r7,lsr#23 - - rsb r4,#0x400 - sub r4,#0x15 - bl dpack_q - orr r1,r1,#1<<31 - pop {r4-r8,r15} - -@ here we have negative ε sufficiently small we need (at most) a quadratic term -@ here r0=ε Q71, |ε|<2^-41 -15: - clz r4,r0 - lsls r1,r0,r4 @ ε Q71+r4 - umull r2,r3,r0,r1 @ ε² Q142+r4 - mov r0,r3,lsr#8 - rsb r4,#0x400 - sub r4,#0x35 - bl dpack_q - eors r1,r1,#0x80000000 - pop {r4-r8,r15} - -wrapper_func log - lsls r12,r1,#1 - bcs 1b @ x<0? - lsrs r12,#21 - beq 1b @ x==0/denormal? - sub r12,#0x3ff - cmp r12,#0x400 @ +Inf/NaN? - beq 4b - movs r2,#1 - bfi r1,r2,#20,#12 @ set implied 1, clear exponent Q52 - push {r4-r8,r14} - cmp r12,r12,asr#31 @ exponent = -1 or 0? - beq 12b -12: - lsrs r4,r1,#16 - ldr r5,=logtab0-16*8 - add r5,r5,r4,lsl#3 - ldmia r5,{r2-r3} - and r5,r2,#63 - add r5,#64 - umull r0,r6,r5,r0 - mla r1,r5,r1,r6 @ Q59 - - mvn r4,r1,asr#19 - and r4,#31 - ldr r5,=exptab1 - add r5,r5,r4,lsl#3 - ldmia r5,{r5-r6} - adds r2,r2,r5 - adc r3,r3,r6 - add r4,#256 - umull r0,r6,r4,r0 - mla r6,r4,r1,r6 @ r0:r6 Q67 - - mvns r4,r6,asr#24 - beq 10b @ small argument at this stage? -10: - ldr r5,=exptab2 - add r5,r5,r4,lsl#3 - ldmia r5,{r1,r5} - adds r2,r2,r1 - adc r3,r3,r5 - mov r5,#4097 - add r4,r5,r4,lsl#1 @ 4097+2k -11: - lsls r4,#17 - umull r5,r0,r4,r0 - rsb r1,r4,r4,lsl#3 - umlal r0,r1,r4,r6 @ Q96=Q64 - -@ r0:r1 ε Q64 -@ r2:r3 y Q64 - - eor r4,r0,r1,asr#31 - eor r5,r1,r1,asr#31 @ r4:r5 |ε| Q64 - umull r6,r7,r5,r5 - umull r4,r8,r4,r5 - lsrs r7,#1 - rrx r6,r6 - adds r6,r6,r8 - adc r7,r7,#0 @ r6:r7 ε²/2 Q64 - - movs r4,r1,lsl#10 - orrs r4,r4,r0,lsr#22 - adc r4,r4,#0 @ ε Q42, rounded - - subs r0,r0,r6 - sbc r1,r1,r7 @ r0:r1 ε-ε²/2 Q64 - - smmulr r5,r4,r4 @ ε² Q42+42-32=Q52 - smmulr r6,r5,r4 @ ε³ Q52+42-32=Q62 - smmulr r7,r5,r5 @ ε⁴ Q52+52-32=Q72 ε⁴/4 Q74 - mov r4,#0x55555555 @ 1/3 Q32 - smmulr r6,r6,r4 @ ε³/3 Q62 - subs r6,r6,r7,lsr#12 @ ε³/3-ε⁴/4 Q62 - - adds r0,r0,r6,lsl#2 @ Q64 - adc r1,r1,r6,asr#30 - - subs r0,r2,r0 - sbc r1,r3,r1 - ldr r2,=exprrdata - ldmia r2,{r2,r5} - adds r12,#1 - ble 1f -@ positive result - umull r2,r3,r2,r12 - movs r4,#0 - umlal r3,r4,r5,r12 - subs r2,r2,r0 - sbcs r3,r3,r1 - sbc r4,r4,#0 - movs r1,#0x40000000 - b 2f @ to pack result - -@ negative result -1: - rsbs r12,#0 - umull r2,r3,r2,r12 - movs r4,#0 - umlal r3,r4,r5,r12 - adds r2,r0,r2 - adcs r3,r1,r3 - adc r4,r4,#0 - movs r1,#0xc0000000 -2: - cbnz r4,2f - movs r4,r3 - movs r3,r2 - movs r2,#0 - subs r1,#32<<20 -1: -@ here r3:r4 is guaranteed nonzero - cbnz r4,2f - movs r4,r3 - movs r3,#0 - subs r1,#32<<20 -2: - clz r5,r4 - sub r6,r5,#0x1d - sub r1,r1,r6,lsl#20 - lsls r4,r5 - lsls r0,r3,r5 - rsb r5,#32 - lsrs r3,r5 - orrs r4,r4,r3 - lsrs r2,r5 - orrs r0,r0,r2 -@ now r0:r4 is normalised to Q63 - lsrs r0,#11 - adcs r0,r0,r4,lsl#21 @ with rounding - adc r1,r1,r4,lsr#11 - pop {r4-r8,r15} - -@=========================================== - -double_section trigtab -trigtab: -// φ Q64 lo φ Q64 hi sin φ Q31 cos φ Q31 -.long 0x25735c0b, 0x03f574a9, 0x01fab529, 0x7ffc1500 -.long 0x00aa2feb, 0x0c44d954, 0x0621d2c8, 0x7fda601f -.long 0x42e86336, 0x13d9d3cf, 0x09ea5e3c, 0x7f9d88f0 -.long 0x046dc42f, 0x1c0a86d9, 0x0dfe171f, 0x7f3b9ed0 -.long 0xec509ba7, 0x23ebf53e, 0x11e6e7bc, 0x7ebdefc7 -.long 0x039c1cd2, 0x2bf112b2, 0x15dcf546, 0x7e1e7749 -.long 0x3d7a05ca, 0x33f293f4, 0x19cbc014, 0x7d5fac9c -.long 0x7aefa0a0, 0x3c19321d, 0x1dc6221d, 0x7c7d2f2f -.long 0x12fb0fb5, 0x4450ef70, 0x21c10c53, 0x7b782235 -.long 0x476b8d5c, 0x4bf1a045, 0x256adc18, 0x7a68ad16 -.long 0x576940c1, 0x53ead96d, 0x29361639, 0x792f2d3c -.long 0xd34eeadf, 0x5bb34289, 0x2ce039d6, 0x77e02625 -.long 0x31ea5069, 0x641107d9, 0x30c4d3c0, 0x76586270 -.long 0xf36756cb, 0x6bfda2b3, 0x34687e1c, 0x74c77a22 -.long 0x2f7aed0e, 0x73e07531, 0x37fae7cc, 0x731c1127 -.long 0xfcc48ec0, 0x7c14790e, 0x3ba3a70e, 0x7141cd8e -.long 0x3b04b713, 0x83547b8f, 0x3ed289d4, 0x6f85d8eb -.long 0x135b369a, 0x8c0b6fd9, 0x4294ead4, 0x6d51efa3 -.long 0x4aca525f, 0x9439d326, 0x460a6e70, 0x6b230540 -.long 0x41c44083, 0x9c0e0b34, 0x4948b03d, 0x68f1ef07 -.long 0xa36d08bf, 0xa47961fd, 0x4cb1f285, 0x667a849d -.long 0xc8f81636, 0xabe547d2, 0x4fa2221e, 0x6436622f -.long 0xd0c8c9ad, 0xb3feade1, 0x52c37024, 0x61a4af86 -.long 0x64730e73, 0xbbfe356a, 0x55c5f028, 0x5f02a3a3 -.long 0xb08ca5c6, 0xc412b955, 0x58ba9208, 0x5c4194a3 -.long 0x54530090, 0xcbb02d37, 0x5b6ef419, 0x59938ed8 -.long 0xa18d7c36, 0xd3aa3c6e, 0x5e2e0225, 0x56af32fc -.long 0x48a2c7d0, 0xdbff19f6, 0x60f35332, 0x5392ed7e -.long 0x7aad9a94, 0xe422ade1, 0x638edfca, 0x50732bc7 -.long 0x19ef15ff, 0xebfb85bd, 0x65fa18bb, 0x4d5c61c7 -.long 0x7e0f96bd, 0xf44c4b49, 0x686f81f7, 0x4a0217e6 -.long 0x1def09eb, 0xfc4dbdfd, 0x6ab2d2c4, 0x46b4e413 -// maximum e=0.002617 = 0.167497*2^-6 - -double_wrapper_section atan2 - -@ datan small reduced angle case I -20: -@ r0:r1 has z=y/x in IEEE format, <2^-11 -@ r2 e+11 - rsbs r12,r2,#0 @ shift down of mantissa required to get to Q63 >0 - subs r10,r12,#32 - bge 1f @ very small reduced angle? - bfi r1,r3,#20,#12 @ fix up mantissa - cmp r7,#4 - bhs 2f @ at least one quadrant to add? then don't need extreme accuracy -@ otherwise we need to do a power series for accuracy - - rsbs r10,#0 - lsr r3,r1,r12 - lsr r2,r0,r12 - lsl r9,r1,r10 - orr r2,r9 -@ r2:r3 z Q63 (with r12 bits of loss of precision) - lsls r1,#11 - orrs r1,r1,r0,lsr#21 - lsls r0,#11 -@ r0:r1 z Q74+r12 - umull r9,r4,r2,r3 - umull r9,r5,r2,r3 - umaal r4,r5,r3,r3 -@ r4:r5 z² Q62 < 2^-22 - umull r9,r2,r0,r5 - umull r9,r3,r1,r4 - umaal r2,r3,r1,r5 -@ r2:r3 z³ Q72+r12 <2^-33 - umull r9,r6,r2,r5 - umull r9,r8,r3,r4 - umaal r6,r8,r3,r5 -@ r6:r8 z⁵ Q70+r12 <2^-55; in fact r8 is always 0 - mov r9,#0xaaaaaaaa @ 2/3 Q32 - umull r10,r4,r2,r9 - movs r5,#0 - umlal r4,r5,r3,r9 - adds r4,r4,r5 - adcs r5,r5,#0 -@ r4:r5 z³*2/3 Q72+r12 = z³/3 Q73+r12 - mov r9,#0x33333333 @ 1/5 Q32 - umull r2,r3,r6,r9 -@ r3 z⁵*1/5 Q70+r12 - subs r4,r4,r3,lsl#3 - sbc r5,r5,#0 -@ r4:r5 z³/3-z⁵/5 Q73+r12 - subs r0,r0,r4,lsl#1 - sbc r1,r1,r5,lsl#1 - sub r1,r1,r4,lsr#31 -@ r0:r1 z-z³/3+z⁵/5 Q74+r12 - rsb r4,r12,#0x400 - sub r4,#24 - b 60f @ pack and return - -2: - rsbs r10,#0 - lsls r4,r1,r10 - lsrs r0,r0,r12 - lsrs r1,r1,r12 - orrs r0,r0,r4 @ shift down r12 places - b 50f - - -1: - cmp r7,#4 - bhs 2f @ at least one quadrant to add? - eors r1,r1,r7,lsl#31 @ no: return y/x with the correct sign - pop {r4-r11,r15} - -2: - bfi r1,r3,#20,#12 @ fix up mantissa - usat r10,#6,r10 @ saturate r10 to 63 - lsrs r0,r1,r10 - movs r1,#0 @ shift down 32+r10 places - b 40f - -@ datan small reduced angle case II -10: - lsrs r1,#1 - rrxs r0,r0 - movs r2,#0 - movs r3,#0 - movs r6,#0 - mov r7,#1<<30 - b 11f - -@ case where reduced (x',y') has x' infinite -71: - sbfx r4,r1,#20,#11 - movs r0,#0 - movs r1,#0 - cmn r4,#1 @ y' also infinite? - bne 80f - movt r1,#0x3ff0 @ both infinite: pretend ∞/∞=1 - b 80f - -@ case where reduced (x',y') has y' zero -70: - ubfx r4,r3,#20,#11 - movs r0,#0 - movs r1,#0 - cbnz r4,80f @ x' also zero? - tst r7,#4 - beq 80f @ already in quadrants 0/±2? then 0/0 result will be correct - tst r7,#2 - ite eq - addeq r7,#6 - subne r7,#6 @ fix up when in quadrants ±0 - b 80f - -90: - movs r0,r2 - movs r1,r3 -91: - orrs r1,r1,#0x00080000 - bx r14 - -wrapper_func atan2 - cmp r2,#1 @ set C if low word is non-zero - adc r12,r3,r3 - cmn r12,#0x00200000 @ y NaN? - bhi 90b - cmp r0,#1 @ set C if low word is non-zero - adc r12,r1,r1 - cmn r12,#0x00200000 @ x NaN? - bhi 91b - push {r4-r11,r14} - lsrs r7,r1,#31 @ b31..2: quadrant count; b1: sign to apply before addition; b0: sign to apply after addition - bic r1,#1<<31 -@ y now positive - movs r3,r3 - bpl 1f - -@ here y positive, x negative - adds r7,#10 - bic r3,r3,#1<<31 - cmp r3,r1 - bhi 4f @ |x| > y: 3rd octant -@ |x| < y: 2nd octant - subs r7,#6 - b 3f - -1: -@ here x and y positive - cmp r3,r1 - bhi 4f -@ x < y: 1st octant - adds r7,#6 -3: - movs r4,r2 @ exchange x and y - movs r5,r3 - movs r2,r0 - movs r3,r1 - movs r0,r4 - movs r1,r5 -4: - -@ here -@ r0:r1 y' -@ r2:r3 x' -@ where both x' and y' are positive, y'/x' < 1+δ, and the final result is -@ ± (Q.π/2 ± atn y/x) where 0≤Q≤2 is a quadrant count in r7b3..2, the inner negation -@ is given by r7b1 and the outer negation by r7b0. x' can be infinite, or both x' and -@ y' can be infinite, but not y' alone. - - sbfx r4,r3,#20,#11 - cmn r4,#1 - beq 71b @ x' infinite? - ubfx r4,r1,#20,#11 - cmp r4,#0 - beq 70b @ y' zero? - bl __aeabi_ddiv -80: -@ r0:r1 y/x in IEEE format, 0..1 - lsr r2,r1,#20 @ exponent - movs r3,#1 - subs r2,#0x3ff-11 - bmi 20b - bfi r1,r3,#20,#12 @ fix up mantissa - movs r3,#1 - lsl r3,r2 - umull r0,r4,r0,r3 - mla r1,r1,r3,r4 -50: - push {r7} @ save flags - -@ from here atan2(y,1) where 1 implied -@ r0:r1 y Q63 0≤y<1+δ - - lsrs r2,r1,#16 - cmp r2,#0x100 - blo 10b @ small angle? - mul r3,r2,r2 @ y^2 - movw r4,#0x895c - muls r2,r2,r4 @ y*0x895c - movw r5,#0x1227 - lsrs r3,#14 - mls r2,r3,r5,r2 - subs r2,#0x330000 @ Chebyshev approximation to atn(y) - lsrs r2,#25 - ldr r3,=trigtab - add r3,r3,r2,lsl#4 - ldmia r3,{r2-r5} - lsrs r3,#1 - rrxs r2,r2 -@ r2:r3 phi0 Q63 -@ r4 sphi0 -@ r5 cphi0 - umull r12,r6,r4,r0 - movs r7,#0 - umlal r6,r7,r4,r1 - adds r6,r6,r5,lsl#31 - adc r7,r7,r5,lsr#1 @ x0= ((i128)cphi0<<31)+(((i128)sphi0*(i128)y)>>32); // Q62 -@ r6:r7 x0 - umull r12,r0,r5,r0 - movs r8,#0 - umlal r0,r8,r5,r1 - subs r0,r0,r4,lsl#31 - sbc r1,r8,r4,lsr#1 @ y0=-((i128)sphi0<<31)+(((i128)cphi0*(i128)y)>>32); // Q62 -11: -@ r0:r1 y0 -@ r2:r3 phi0 -@ r6:r7 x0 - - lsls r4,r1,#6 - orr r4,r4,r0,lsr#26 - lsrs r5,r7,#15 - sdiv r4,r4,r5 @ t2=(y0>>26)/(x0>>47); // Q62-26/Q62-47=Q21 - - mul r5,r4,r4 @ t2_2 Q42 - add r3,r3,r4,lsl#10 @ phi0+t2 - smull r8,r9,r4,r5 @ t2_3 Q63 - mov r10,r9,lsl#16 - orr r10,r10,r8,lsr#16 - smmulr r10,r10,r5 @ t2_5 Q57 - mov r12,#0x66666666 @ 1/5 Q33 - smmulr r11,r10,r5 @ t2_7 Q67 - smmulr r10,r10,r12 @ t2_5/5 Q57+33-32=Q58 - - movlong r12,0x124925 @ 1/7 Q23 - smmulr r11,r11,r12 @ t2_7/7 Q67+23-32=Q58 - mov r12,#0x55555555 - sub r11,r11,r11,asr#12 @ Q58 PMC correction - sub r10,r10,r11 - - adds r2,r2,r10,lsl#5 - adc r3,r3,r10,asr#27 @ Q63 phi0 + t_2 + t2_5/5 - t2_7/7 + t2_7/7/4096 - umull r5,r10,r8,r12 - mov r11,#0 - smlal r10,r11,r9,r12 @ t2_3 * 0x55555555 - adds r10,r10,r11 - adc r11,r11,r11,asr#31 @ t2_3/3 Q63 - subs r2,r2,r10 - sbc r3,r3,r11 @ Q63 phi0+phi1 - - lsls r4,r4,#11 @ t2 Q32 - umull r5,r8,r4,r0 @ t2*y0l - it mi - submi r8,r8,r0 @ correction if t2 is negative - mov r9,r8,asr#31 @ sign extend - smlal r8,r9,r4,r1 @ t2*y0h -@ r8:r9 (t2*y0)<<11 - - umull r5,r10,r4,r6 @ t2*x0l - it mi - submi r10,r10,r6 @ correction if t2 is negative - mov r11,r10,asr#31 @ sign extend - smlal r10,r11,r4,r7 -@ r10:r11 (t2*x0)<<11 - - adds r6,r8 - adc r7,r7,r9 - subs r0,r10 - sbc r1,r1,r11 -@ r0:r1 y1=y0-t2*x0 -@ r2:r3 phi0+phi1 -@ r6:r7 x1=x0+t2*y0 - - mov r4,#0xffffffff - lsrs r5,r7,#14 - udiv r4,r4,r5 @ rx1 Q16 - lsrs r5,r0,#11 - orrs r5,r5,r1,lsl#21 @ N set according to y1, hence also t3 - smmul r5,r4,r5 @ t3=(y1>>11)*rx1 Q35 - lsr r6,r6,#3 - orr r6,r6,r7,lsl#29 - umull r11,r8,r5,r6 @ t3*x1l - lsr r10,r7,#3 - it mi - submi r8,r8,r6 @ correction if t3 is negative - mla r8,r5,r10,r8 - adds r2,r2,r5,lsl#28 - adc r3,r3,r5,asr#4 - sub r0,r0,r8 -@ r0: y2 -@ r2:r3 phi0+phi1+phi2 -@ r4: rx1 -@ r5: t3 - - smull r8,r9,r0,r4 @ y2*rx1 -@ stall - lsrs r8,#14 - orr r8,r8,r9,lsl#18 @ t4 - smmlsr r0,r8,r7,r0 - adds r2,r2,r8,asr#1 - adc r3,r3,r8,asr#31 -@ r0: y3 -@ r4: rx1 - mul r4,r4,r0 - adds r0,r2,r4,asr#15 - adc r1,r3,r4,asr#31 -@ r0:r1 result over reduced range Q63 - pop {r7} @ restore flags -40: - lsrs r1,#1 - rrxs r0,r0 -@ r0:r1 result over reduced range Q62 - lsl r6,r7,#30 @ b1 -> b31 - eor r0,r0,r6,asr#31 @ negate if required - eor r1,r1,r6,asr#31 - movlong r2,0x10B4611A @ π/2 Q62 low word - movlong r3,0x6487ED51 @ π/2 Q62 high word - lsr r6,r7,#2 @ quadrants to add - umlal r0,r1,r6,r2 - mla r1,r6,r3,r1 - mov r4,#0x400-12 @ for packing Q62 -60: - bl dpack_q - eors r1,r1,r7,lsl#31 - pop {r4-r11,r15} - -#endif diff --git a/lib/main/pico-sdk/rp2_common/pico_double/double_v1_rom_shim_rp2040.S b/lib/main/pico-sdk/rp2_common/pico_double/double_v1_rom_shim_rp2040.S deleted file mode 100644 index dc0207f4c3..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_double/double_v1_rom_shim_rp2040.S +++ /dev/null @@ -1,2174 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "pico/asm_helper.S" - -pico_default_asm_setup - -.macro double_section name -// todo separate flag for shims? -#if PICO_DOUBLE_IN_RAM -.section RAM_SECTION_NAME(\name), "ax" -#else -.section SECTION_NAME(\name), "ax" -#endif -.endm - -double_section double_table_shim_on_use_helper -regular_func double_table_shim_on_use_helper - push {r0-r2, lr} - mov r0, ip -#ifndef NDEBUG - // sanity check to make sure we weren't called by non (shimmable_) table_tail_call macro - cmp r0, #0 - bne 1f - bkpt #0 -#endif -1: - ldrh r1, [r0] - lsrs r2, r1, #8 - adds r0, #2 - cmp r2, #0xdf - bne 1b - uxtb r1, r1 // r1 holds table offset - lsrs r2, r0, #2 - bcc 1f - // unaligned - ldrh r2, [r0, #0] - ldrh r0, [r0, #2] - lsls r0, #16 - orrs r0, r2 - b 2f -1: - ldr r0, [r0] -2: - ldr r2, =sd_table - str r0, [r2, r1] - str r0, [sp, #12] - pop {r0-r2, pc} - -#if PICO_DOUBLE_SUPPORT_ROM_V1 && PICO_RP2040_B0_SUPPORTED -// Note that the V1 ROM has no double support, so this is basically the identical -// library, and shim inter-function calls do not bother to redirect back thru the -// wrapper functions - -.equ use_hw_div,1 -.equ IOPORT ,0xd0000000 -.equ DIV_UDIVIDEND,0x00000060 -.equ DIV_UDIVISOR ,0x00000064 -.equ DIV_QUOTIENT ,0x00000070 -.equ DIV_CSR ,0x00000078 - -@ Notation: -@ rx:ry means the concatenation of rx and ry with rx having the less significant bits - -.equ debug,0 -.macro mdump k -.if debug - push {r0-r3} - push {r14} - push {r0-r3} - bl osp - movs r0,#\k - bl o1ch - pop {r0-r3} - bl dump - bl osp - bl osp - ldr r0,[r13] - bl o8hex @ r14 - bl onl - pop {r0} - mov r14,r0 - pop {r0-r3} -.endif -.endm - - -@ IEEE double in ra:rb -> -@ mantissa in ra:rb 12Q52 (53 significant bits) with implied 1 set -@ exponent in re -@ sign in rs -@ trashes rt -.macro mdunpack ra,rb,re,rs,rt - lsrs \re,\rb,#20 @ extract sign and exponent - subs \rs,\re,#1 - lsls \rs,#20 - subs \rb,\rs @ clear sign and exponent in mantissa; insert implied 1 - lsrs \rs,\re,#11 @ sign - lsls \re,#21 - lsrs \re,#21 @ exponent - beq l\@_1 @ zero exponent? - adds \rt,\re,#1 - lsrs \rt,#11 - beq l\@_2 @ exponent != 0x7ff? then done -l\@_1: - movs \ra,#0 - movs \rb,#1 - lsls \rb,#20 - subs \re,#128 - lsls \re,#12 -l\@_2: -.endm - -@ IEEE double in ra:rb -> -@ signed mantissa in ra:rb 12Q52 (53 significant bits) with implied 1 -@ exponent in re -@ trashes rt0 and rt1 -@ +zero, +denormal -> exponent=-0x80000 -@ -zero, -denormal -> exponent=-0x80000 -@ +Inf, +NaN -> exponent=+0x77f000 -@ -Inf, -NaN -> exponent=+0x77e000 -.macro mdunpacks ra,rb,re,rt0,rt1 - lsrs \re,\rb,#20 @ extract sign and exponent - lsrs \rt1,\rb,#31 @ sign only - subs \rt0,\re,#1 - lsls \rt0,#20 - subs \rb,\rt0 @ clear sign and exponent in mantissa; insert implied 1 - lsls \re,#21 - bcc l\@_1 @ skip on positive - mvns \rb,\rb @ negate mantissa - negs \ra,\ra - bcc l\@_1 - adds \rb,#1 -l\@_1: - lsrs \re,#21 - beq l\@_2 @ zero exponent? - adds \rt0,\re,#1 - lsrs \rt0,#11 - beq l\@_3 @ exponent != 0x7ff? then done - subs \re,\rt1 -l\@_2: - movs \ra,#0 - lsls \rt1,#1 @ +ve: 0 -ve: 2 - adds \rb,\rt1,#1 @ +ve: 1 -ve: 3 - lsls \rb,#30 @ create +/-1 mantissa - asrs \rb,#10 - subs \re,#128 - lsls \re,#12 -l\@_3: -.endm - -double_section WRAPPER_FUNC_NAME(__aeabi_dsub) - -# frsub first because it is the only one that needs alignment -regular_func drsub_shim - push {r0-r3} - pop {r0-r1} - pop {r2-r3} - // fall thru - -regular_func dsub_shim - push {r4-r7,r14} - movs r4,#1 - lsls r4,#31 - eors r3,r4 @ flip sign on second argument - b da_entry @ continue in dadd - -.align 2 -double_section dadd_shim -regular_func dadd_shim - push {r4-r7,r14} -da_entry: - mdunpacks r0,r1,r4,r6,r7 - mdunpacks r2,r3,r5,r6,r7 - subs r7,r5,r4 @ ye-xe - subs r6,r4,r5 @ xe-ye - bmi da_ygtx -@ here xe>=ye: need to shift y down r6 places - mov r12,r4 @ save exponent - cmp r6,#32 - bge da_xrgty @ xe rather greater than ye? - adds r7,#32 - movs r4,r2 - lsls r4,r4,r7 @ rounding bit + sticky bits -da_xgty0: - movs r5,r3 - lsls r5,r5,r7 - lsrs r2,r6 - asrs r3,r6 - orrs r2,r5 -da_add: - adds r0,r2 - adcs r1,r3 -da_pack: -@ here unnormalised signed result (possibly 0) is in r0:r1 with exponent r12, rounding + sticky bits in r4 -@ Note that if a large normalisation shift is required then the arguments were close in magnitude and so we -@ cannot have not gone via the xrgty/yrgtx paths. There will therefore always be enough high bits in r4 -@ to provide a correct continuation of the exact result. -@ now pack result back up - lsrs r3,r1,#31 @ get sign bit - beq 1f @ skip on positive - mvns r1,r1 @ negate mantissa - mvns r0,r0 - movs r2,#0 - negs r4,r4 - adcs r0,r2 - adcs r1,r2 -1: - mov r2,r12 @ get exponent - lsrs r5,r1,#21 - bne da_0 @ shift down required? - lsrs r5,r1,#20 - bne da_1 @ normalised? - cmp r0,#0 - beq da_5 @ could mantissa be zero? -da_2: - adds r4,r4 - adcs r0,r0 - adcs r1,r1 - subs r2,#1 @ adjust exponent - lsrs r5,r1,#20 - beq da_2 -da_1: - lsls r4,#1 @ check rounding bit - bcc da_3 -da_4: - adds r0,#1 @ round up - bcc 2f - adds r1,#1 -2: - cmp r4,#0 @ sticky bits zero? - bne da_3 - lsrs r0,#1 @ round to even - lsls r0,#1 -da_3: - subs r2,#1 - bmi da_6 - adds r4,r2,#2 @ check if exponent is overflowing - lsrs r4,#11 - bne da_7 - lsls r2,#20 @ pack exponent and sign - add r1,r2 - lsls r3,#31 - add r1,r3 - pop {r4-r7,r15} - -da_7: -@ here exponent overflow: return signed infinity - lsls r1,r3,#31 - ldr r3,=0x7ff00000 - orrs r1,r3 - b 1f -da_6: -@ here exponent underflow: return signed zero - lsls r1,r3,#31 -1: - movs r0,#0 - pop {r4-r7,r15} - -da_5: -@ here mantissa could be zero - cmp r1,#0 - bne da_2 - cmp r4,#0 - bne da_2 -@ inputs must have been of identical magnitude and opposite sign, so return +0 - pop {r4-r7,r15} - -da_0: -@ here a shift down by one place is required for normalisation - adds r2,#1 @ adjust exponent - lsls r6,r0,#31 @ save rounding bit - lsrs r0,#1 - lsls r5,r1,#31 - orrs r0,r5 - lsrs r1,#1 - cmp r6,#0 - beq da_3 - b da_4 - -da_xrgty: @ xe>ye and shift>=32 places - cmp r6,#60 - bge da_xmgty @ xe much greater than ye? - subs r6,#32 - adds r7,#64 - - movs r4,r2 - lsls r4,r4,r7 @ these would be shifted off the bottom of the sticky bits - beq 1f - movs r4,#1 -1: - lsrs r2,r2,r6 - orrs r4,r2 - movs r2,r3 - lsls r3,r3,r7 - orrs r4,r3 - asrs r3,r2,#31 @ propagate sign bit - b da_xgty0 - -da_ygtx: -@ here ye>xe: need to shift x down r7 places - mov r12,r5 @ save exponent - cmp r7,#32 - bge da_yrgtx @ ye rather greater than xe? - adds r6,#32 - movs r4,r0 - lsls r4,r4,r6 @ rounding bit + sticky bits -da_ygtx0: - movs r5,r1 - lsls r5,r5,r6 - lsrs r0,r7 - asrs r1,r7 - orrs r0,r5 - b da_add - -da_yrgtx: - cmp r7,#60 - bge da_ymgtx @ ye much greater than xe? - subs r7,#32 - adds r6,#64 - - movs r4,r0 - lsls r4,r4,r6 @ these would be shifted off the bottom of the sticky bits - beq 1f - movs r4,#1 -1: - lsrs r0,r0,r7 - orrs r4,r0 - movs r0,r1 - lsls r1,r1,r6 - orrs r4,r1 - asrs r1,r0,#31 @ propagate sign bit - b da_ygtx0 - -da_ymgtx: @ result is just y - movs r0,r2 - movs r1,r3 -da_xmgty: @ result is just x - movs r4,#0 @ clear sticky bits - b da_pack - -.ltorg - -@ equivalent of UMULL -@ needs five temporary registers -@ can have rt3==rx, in which case rx trashed -@ can have rt4==ry, in which case ry trashed -@ can have rzl==rx -@ can have rzh==ry -@ can have rzl,rzh==rt3,rt4 -.macro mul32_32_64 rx,ry,rzl,rzh,rt0,rt1,rt2,rt3,rt4 - @ t0 t1 t2 t3 t4 - @ (x) (y) - uxth \rt0,\rx @ xl - uxth \rt1,\ry @ yl - muls \rt0,\rt1 @ xlyl=L - lsrs \rt2,\rx,#16 @ xh - muls \rt1,\rt2 @ xhyl=M0 - lsrs \rt4,\ry,#16 @ yh - muls \rt2,\rt4 @ xhyh=H - uxth \rt3,\rx @ xl - muls \rt3,\rt4 @ xlyh=M1 - adds \rt1,\rt3 @ M0+M1=M - bcc l\@_1 @ addition of the two cross terms can overflow, so add carry into H - movs \rt3,#1 @ 1 - lsls \rt3,#16 @ 0x10000 - adds \rt2,\rt3 @ H' -l\@_1: - @ t0 t1 t2 t3 t4 - @ (zl) (zh) - lsls \rzl,\rt1,#16 @ ML - lsrs \rzh,\rt1,#16 @ MH - adds \rzl,\rt0 @ ZL - adcs \rzh,\rt2 @ ZH -.endm - -@ SUMULL: x signed, y unsigned -@ in table below ¯ means signed variable -@ needs five temporary registers -@ can have rt3==rx, in which case rx trashed -@ can have rt4==ry, in which case ry trashed -@ can have rzl==rx -@ can have rzh==ry -@ can have rzl,rzh==rt3,rt4 -.macro muls32_32_64 rx,ry,rzl,rzh,rt0,rt1,rt2,rt3,rt4 - @ t0 t1 t2 t3 t4 - @ ¯(x) (y) - uxth \rt0,\rx @ xl - uxth \rt1,\ry @ yl - muls \rt0,\rt1 @ xlyl=L - asrs \rt2,\rx,#16 @ ¯xh - muls \rt1,\rt2 @ ¯xhyl=M0 - lsrs \rt4,\ry,#16 @ yh - muls \rt2,\rt4 @ ¯xhyh=H - uxth \rt3,\rx @ xl - muls \rt3,\rt4 @ xlyh=M1 - asrs \rt4,\rt1,#31 @ M0sx (M1 sign extension is zero) - adds \rt1,\rt3 @ M0+M1=M - movs \rt3,#0 @ 0 - adcs \rt4,\rt3 @ ¯Msx - lsls \rt4,#16 @ ¯Msx<<16 - adds \rt2,\rt4 @ H' - - @ t0 t1 t2 t3 t4 - @ (zl) (zh) - lsls \rzl,\rt1,#16 @ M~ - lsrs \rzh,\rt1,#16 @ M~ - adds \rzl,\rt0 @ ZL - adcs \rzh,\rt2 @ ¯ZH -.endm - -@ SSMULL: x signed, y signed -@ in table below ¯ means signed variable -@ needs five temporary registers -@ can have rt3==rx, in which case rx trashed -@ can have rt4==ry, in which case ry trashed -@ can have rzl==rx -@ can have rzh==ry -@ can have rzl,rzh==rt3,rt4 -.macro muls32_s32_64 rx,ry,rzl,rzh,rt0,rt1,rt2,rt3,rt4 - @ t0 t1 t2 t3 t4 - @ ¯(x) (y) - uxth \rt0,\rx @ xl - uxth \rt1,\ry @ yl - muls \rt0,\rt1 @ xlyl=L - asrs \rt2,\rx,#16 @ ¯xh - muls \rt1,\rt2 @ ¯xhyl=M0 - asrs \rt4,\ry,#16 @ ¯yh - muls \rt2,\rt4 @ ¯xhyh=H - uxth \rt3,\rx @ xl - muls \rt3,\rt4 @ ¯xlyh=M1 - adds \rt1,\rt3 @ ¯M0+M1=M - asrs \rt3,\rt1,#31 @ Msx - bvc l\@_1 @ - mvns \rt3,\rt3 @ ¯Msx flip sign extension bits if overflow -l\@_1: - lsls \rt3,#16 @ ¯Msx<<16 - adds \rt2,\rt3 @ H' - - @ t0 t1 t2 t3 t4 - @ (zl) (zh) - lsls \rzl,\rt1,#16 @ M~ - lsrs \rzh,\rt1,#16 @ M~ - adds \rzl,\rt0 @ ZL - adcs \rzh,\rt2 @ ¯ZH -.endm - -@ can have rt2==rx, in which case rx trashed -@ can have rzl==rx -@ can have rzh==rt1 -.macro square32_64 rx,rzl,rzh,rt0,rt1,rt2 - @ t0 t1 t2 zl zh - uxth \rt0,\rx @ xl - muls \rt0,\rt0 @ xlxl=L - uxth \rt1,\rx @ xl - lsrs \rt2,\rx,#16 @ xh - muls \rt1,\rt2 @ xlxh=M - muls \rt2,\rt2 @ xhxh=H - lsls \rzl,\rt1,#17 @ ML - lsrs \rzh,\rt1,#15 @ MH - adds \rzl,\rt0 @ ZL - adcs \rzh,\rt2 @ ZH -.endm - -double_section dmul_shim - regular_func dmul_shim - push {r4-r7,r14} - mdunpack r0,r1,r4,r6,r5 - mov r12,r4 - mdunpack r2,r3,r4,r7,r5 - eors r7,r6 @ sign of result - add r4,r12 @ exponent of result - push {r0-r2,r4,r7} - -@ accumulate full product in r12:r5:r6:r7 - mul32_32_64 r0,r2, r0,r5, r4,r6,r7,r0,r5 @ XL*YL - mov r12,r0 @ save LL bits - - mul32_32_64 r1,r3, r6,r7, r0,r2,r4,r6,r7 @ XH*YH - - pop {r0} @ XL - mul32_32_64 r0,r3, r0,r3, r1,r2,r4,r0,r3 @ XL*YH - adds r5,r0 - adcs r6,r3 - movs r0,#0 - adcs r7,r0 - - pop {r1,r2} @ XH,YL - mul32_32_64 r1,r2, r1,r2, r0,r3,r4, r1,r2 @ XH*YL - adds r5,r1 - adcs r6,r2 - movs r0,#0 - adcs r7,r0 - -@ here r5:r6:r7 holds the product [1..4) in Q(104-32)=Q72, with extra LSBs in r12 - pop {r3,r4} @ exponent in r3, sign in r4 - lsls r1,r7,#11 - lsrs r2,r6,#21 - orrs r1,r2 - lsls r0,r6,#11 - lsrs r2,r5,#21 - orrs r0,r2 - lsls r5,#11 @ now r5:r0:r1 Q83=Q(51+32), extra LSBs in r12 - lsrs r2,r1,#20 - bne 1f @ skip if in range [2..4) - adds r5,r5 @ shift up so always [2..4) Q83, i.e. [1..2) Q84=Q(52+32) - adcs r0,r0 - adcs r1,r1 - subs r3,#1 @ correct exponent -1: - ldr r6,=0x3ff - subs r3,r6 @ correct for exponent bias - lsls r6,#1 @ 0x7fe - cmp r3,r6 - bhs dm_0 @ exponent over- or underflow - lsls r5,#1 @ rounding bit to carry - bcc 1f @ result is correctly rounded - adds r0,#1 - movs r6,#0 - adcs r1,r6 @ round up - mov r6,r12 @ remaining sticky bits - orrs r5,r6 - bne 1f @ some sticky bits set? - lsrs r0,#1 - lsls r0,#1 @ round to even -1: - lsls r3,#20 - adds r1,r3 -dm_2: - lsls r4,#31 - add r1,r4 - pop {r4-r7,r15} - -@ here for exponent over- or underflow -dm_0: - bge dm_1 @ overflow? - adds r3,#1 @ would-be zero exponent? - bne 1f - adds r0,#1 - bne 1f @ all-ones mantissa? - adds r1,#1 - lsrs r7,r1,#21 - beq 1f - lsrs r1,#1 - b dm_2 -1: - lsls r1,r4,#31 - movs r0,#0 - pop {r4-r7,r15} - -@ here for exponent overflow -dm_1: - adds r6,#1 @ 0x7ff - lsls r1,r6,#20 - movs r0,#0 - b dm_2 - -.ltorg - -@ Approach to division y/x is as follows. -@ -@ First generate u1, an approximation to 1/x to about 29 bits. Multiply this by the top -@ 32 bits of y to generate a0, a first approximation to the result (good to 28 bits or so). -@ Calculate the exact remainder r0=y-a0*x, which will be about 0. Calculate a correction -@ d0=r0*u1, and then write a1=a0+d0. If near a rounding boundary, compute the exact -@ remainder r1=y-a1*x (which can be done using r0 as a basis) to determine whether to -@ round up or down. -@ -@ The calculation of 1/x is as given in dreciptest.c. That code verifies exhaustively -@ that | u1*x-1 | < 10*2^-32. -@ -@ More precisely: -@ -@ x0=(q16)x; -@ x1=(q30)x; -@ y0=(q31)y; -@ u0=(q15~)"(0xffffffffU/(unsigned int)roundq(x/x_ulp))/powq(2,16)"(x0); // q15 approximation to 1/x; "~" denotes rounding rather than truncation -@ v=(q30)(u0*x1-1); -@ u1=(q30)u0-(q30~)(u0*v); -@ -@ a0=(q30)(u1*y0); -@ r0=(q82)y-a0*x; -@ r0x=(q57)r0; -@ d0=r0x*u1; -@ a1=d0+a0; -@ -@ Error analysis -@ -@ Use Greek letters to represent the errors introduced by rounding and truncation. -@ -@ r₀ = y - a₀x -@ = y - [ u₁ ( y - α ) - β ] x where 0 ≤ α < 2^-31, 0 ≤ β < 2^-30 -@ = y ( 1 - u₁x ) + ( u₁α + β ) x -@ -@ Hence -@ -@ | r₀ / x | < 2 * 10*2^-32 + 2^-31 + 2^-30 -@ = 26*2^-32 -@ -@ r₁ = y - a₁x -@ = y - a₀x - d₀x -@ = r₀ - d₀x -@ = r₀ - u₁ ( r₀ - γ ) x where 0 ≤ γ < 2^-57 -@ = r₀ ( 1 - u₁x ) + u₁γx -@ -@ Hence -@ -@ | r₁ / x | < 26*2^-32 * 10*2^-32 + 2^-57 -@ = (260+128)*2^-64 -@ < 2^-55 -@ -@ Empirically it seems to be nearly twice as good as this. -@ -@ To determine correctly whether the exact remainder calculation can be skipped we need a result -@ accurate to < 0.25ulp. In the case where x>y the quotient will be shifted up one place for normalisation -@ and so 1ulp is 2^-53 and so the calculation above suffices. - -double_section ddiv_shim - regular_func ddiv_shim - push {r4-r7,r14} -ddiv0: @ entry point from dtan - mdunpack r2,r3,r4,r7,r6 @ unpack divisor - -.if use_hw_div - - movs r5,#IOPORT>>24 - lsls r5,#24 - movs r6,#0 - mvns r6,r6 - str r6,[r5,#DIV_UDIVIDEND] - lsrs r6,r3,#4 @ x0=(q16)x - str r6,[r5,#DIV_UDIVISOR] -@ if there are not enough cycles from now to the read of the quotient for -@ the divider to do its stuff we need a busy-wait here - -.endif - -@ unpack dividend by hand to save on register use - lsrs r6,r1,#31 - adds r6,r7 - mov r12,r6 @ result sign in r12b0; r12b1 trashed - lsls r1,#1 - lsrs r7,r1,#21 @ exponent - beq 1f @ zero exponent? - adds r6,r7,#1 - lsrs r6,#11 - beq 2f @ exponent != 0x7ff? then done -1: - movs r0,#0 - movs r1,#0 - subs r7,#64 @ less drastic fiddling of exponents to get 0/0, Inf/Inf correct - lsls r7,#12 -2: - subs r6,r7,r4 - lsls r6,#2 - add r12,r12,r6 @ (signed) exponent in r12[31..8] - subs r7,#1 @ implied 1 - lsls r7,#21 - subs r1,r7 - lsrs r1,#1 - -.if use_hw_div - - ldr r6,[r5,#DIV_QUOTIENT] - adds r6,#1 - lsrs r6,#1 - -.else - -@ this is not beautiful; could be replaced by better code that uses knowledge of divisor range - push {r0-r3} - movs r0,#0 - mvns r0,r0 - lsrs r1,r3,#4 @ x0=(q16)x - bl __aeabi_uidiv @ !!! this could (but apparently does not) trash R12 - adds r6,r0,#1 - lsrs r6,#1 - pop {r0-r3} - -.endif - -@ here -@ r0:r1 y mantissa -@ r2:r3 x mantissa -@ r6 u0, first approximation to 1/x Q15 -@ r12: result sign, exponent - - lsls r4,r3,#10 - lsrs r5,r2,#22 - orrs r5,r4 @ x1=(q30)x - muls r5,r6 @ u0*x1 Q45 - asrs r5,#15 @ v=u0*x1-1 Q30 - muls r5,r6 @ u0*v Q45 - asrs r5,#14 - adds r5,#1 - asrs r5,#1 @ round u0*v to Q30 - lsls r6,#15 - subs r6,r5 @ u1 Q30 - -@ here -@ r0:r1 y mantissa -@ r2:r3 x mantissa -@ r6 u1, second approximation to 1/x Q30 -@ r12: result sign, exponent - - push {r2,r3} - lsls r4,r1,#11 - lsrs r5,r0,#21 - orrs r4,r5 @ y0=(q31)y - mul32_32_64 r4,r6, r4,r5, r2,r3,r7,r4,r5 @ y0*u1 Q61 - adds r4,r4 - adcs r5,r5 @ a0=(q30)(y0*u1) - -@ here -@ r0:r1 y mantissa -@ r5 a0, first approximation to y/x Q30 -@ r6 u1, second approximation to 1/x Q30 -@ r12 result sign, exponent - - ldr r2,[r13,#0] @ xL - mul32_32_64 r2,r5, r2,r3, r1,r4,r7,r2,r3 @ xL*a0 - ldr r4,[r13,#4] @ xH - muls r4,r5 @ xH*a0 - adds r3,r4 @ r2:r3 now x*a0 Q82 - lsrs r2,#25 - lsls r1,r3,#7 - orrs r2,r1 @ r2 now x*a0 Q57; r7:r2 is x*a0 Q89 - lsls r4,r0,#5 @ y Q57 - subs r0,r4,r2 @ r0x=y-x*a0 Q57 (signed) - -@ here -@ r0 r0x Q57 -@ r5 a0, first approximation to y/x Q30 -@ r4 yL Q57 -@ r6 u1 Q30 -@ r12 result sign, exponent - - muls32_32_64 r0,r6, r7,r6, r1,r2,r3, r7,r6 @ r7:r6 r0x*u1 Q87 - asrs r3,r6,#25 - adds r5,r3 - lsls r3,r6,#7 @ r3:r5 a1 Q62 (but bottom 7 bits are zero so 55 bits of precision after binary point) -@ here we could recover another 7 bits of precision (but not accuracy) from the top of r7 -@ but these bits are thrown away in the rounding and conversion to Q52 below - -@ here -@ r3:r5 a1 Q62 candidate quotient [0.5,2) or so -@ r4 yL Q57 -@ r12 result sign, exponent - - movs r6,#0 - adds r3,#128 @ for initial rounding to Q53 - adcs r5,r5,r6 - lsrs r1,r5,#30 - bne dd_0 -@ here candidate quotient a1 is in range [0.5,1) -@ so 30 significant bits in r5 - - lsls r4,#1 @ y now Q58 - lsrs r1,r5,#9 @ to Q52 - lsls r0,r5,#23 - lsrs r3,#9 @ 0.5ulp-significance bit in carry: if this is 1 we may need to correct result - orrs r0,r3 - bcs dd_1 - b dd_2 -dd_0: -@ here candidate quotient a1 is in range [1,2) -@ so 31 significant bits in r5 - - movs r2,#4 - add r12,r12,r2 @ fix exponent; r3:r5 now effectively Q61 - adds r3,#128 @ complete rounding to Q53 - adcs r5,r5,r6 - lsrs r1,r5,#10 - lsls r0,r5,#22 - lsrs r3,#10 @ 0.5ulp-significance bit in carry: if this is 1 we may need to correct result - orrs r0,r3 - bcc dd_2 -dd_1: - -@ here -@ r0:r1 rounded result Q53 [0.5,1) or Q52 [1,2), but may not be correctly rounded-to-nearest -@ r4 yL Q58 or Q57 -@ r12 result sign, exponent -@ carry set - - adcs r0,r0,r0 - adcs r1,r1,r1 @ z Q53 with 1 in LSB - lsls r4,#16 @ Q105-32=Q73 - ldr r2,[r13,#0] @ xL Q52 - ldr r3,[r13,#4] @ xH Q20 - - movs r5,r1 @ zH Q21 - muls r5,r2 @ zH*xL Q73 - subs r4,r5 - muls r3,r0 @ zL*xH Q73 - subs r4,r3 - mul32_32_64 r2,r0, r2,r3, r5,r6,r7,r2,r3 @ xL*zL - negs r2,r2 @ borrow from low half? - sbcs r4,r3 @ y-xz Q73 (remainder bits 52..73) - - cmp r4,#0 - - bmi 1f - movs r2,#0 @ round up - adds r0,#1 - adcs r1,r2 -1: - lsrs r0,#1 @ shift back down to Q52 - lsls r2,r1,#31 - orrs r0,r2 - lsrs r1,#1 -dd_2: - add r13,#8 - mov r2,r12 - lsls r7,r2,#31 @ result sign - asrs r2,#2 @ result exponent - ldr r3,=0x3fd - adds r2,r3 - ldr r3,=0x7fe - cmp r2,r3 - bhs dd_3 @ over- or underflow? - lsls r2,#20 - adds r1,r2 @ pack exponent -dd_5: - adds r1,r7 @ pack sign - pop {r4-r7,r15} - -dd_3: - movs r0,#0 - cmp r2,#0 - bgt dd_4 @ overflow? - movs r1,r7 - pop {r4-r7,r15} - -dd_4: - adds r3,#1 @ 0x7ff - lsls r1,r3,#20 - b dd_5 - -.section SECTION_NAME(dsqrt_shim) -/* -Approach to square root x=sqrt(y) is as follows. - -First generate a3, an approximation to 1/sqrt(y) to about 30 bits. Multiply this by y -to give a4~sqrt(y) to about 28 bits and a remainder r4=y-a4^2. Then, because -d sqrt(y) / dy = 1 / (2 sqrt(y)) let d4=r4*a3/2 and then the value a5=a4+d4 is -a better approximation to sqrt(y). If this is near a rounding boundary we -compute an exact remainder y-a5*a5 to decide whether to round up or down. - -The calculation of a3 and a4 is as given in dsqrttest.c. That code verifies exhaustively -that | 1 - a3a4 | < 10*2^-32, | r4 | < 40*2^-32 and | r4/y | < 20*2^-32. - -More precisely, with "y" representing y truncated to 30 binary places: - -u=(q3)y; // 24-entry table -a0=(q8~)"1/sqrtq(x+x_ulp/2)"(u); // first approximation from table -p0=(q16)(a0*a0) * (q16)y; -r0=(q20)(p0-1); -dy0=(q15)(r0*a0); // Newton-Raphson correction term -a1=(q16)a0-dy0/2; // good to ~9 bits - -p1=(q19)(a1*a1)*(q19)y; -r1=(q23)(p1-1); -dy1=(q15~)(r1*a1); // second Newton-Raphson correction -a2x=(q16)a1-dy1/2; // good to ~16 bits -a2=a2x-a2x/1t16; // prevent overflow of a2*a2 in 32 bits - -p2=(a2*a2)*(q30)y; // Q62 -r2=(q36)(p2-1+1t-31); -dy2=(q30)(r2*a2); // Q52->Q30 -a3=(q31)a2-dy2/2; // good to about 30 bits -a4=(q30)(a3*(q30)y+1t-31); // good to about 28 bits - -Error analysis - - r₄ = y - a₄² - d₄ = 1/2 a₃r₄ - a₅ = a₄ + d₄ - r₅ = y - a₅² - = y - ( a₄ + d₄ )² - = y - a₄² - a₃a₄r₄ - 1/4 a₃²r₄² - = r₄ - a₃a₄r₄ - 1/4 a₃²r₄² - - | r₅ | < | r₄ | | 1 - a₃a₄ | + 1/4 r₄² - - a₅ = √y √( 1 - r₅/y ) - = √y ( 1 - 1/2 r₅/y + ... ) - -So to first order (second order being very tiny) - - √y - a₅ = 1/2 r₅/y - -and - - | √y - a₅ | < 1/2 ( | r₄/y | | 1 - a₃a₄ | + 1/4 r₄²/y ) - -From dsqrttest.c (conservatively): - - < 1/2 ( 20*2^-32 * 10*2^-32 + 1/4 * 40*2^-32*20*2^-32 ) - = 1/2 ( 200 + 200 ) * 2^-64 - < 2^-56 - -Empirically we see about 1ulp worst-case error including rounding at Q57. - -To determine correctly whether the exact remainder calculation can be skipped we need a result -accurate to < 0.25ulp at Q52, or 2^-54. -*/ - -dq_2: - bge dq_3 @ +Inf? - movs r1,#0 - b dq_4 - -dq_0: - lsrs r1,#31 - lsls r1,#31 @ preserve sign bit - lsrs r2,#21 @ extract exponent - beq dq_4 @ -0? return it - asrs r1,#11 @ make -Inf - b dq_4 - -dq_3: - ldr r1,=0x7ff - lsls r1,#20 @ return +Inf -dq_4: - movs r0,#0 -dq_1: - bx r14 - -.align 2 -regular_func dsqrt_shim - lsls r2,r1,#1 - bcs dq_0 @ negative? - lsrs r2,#21 @ extract exponent - subs r2,#1 - ldr r3,=0x7fe - cmp r2,r3 - bhs dq_2 @ catches 0 and +Inf - push {r4-r7,r14} - lsls r4,r2,#20 - subs r1,r4 @ insert implied 1 - lsrs r2,#1 - bcc 1f @ even exponent? skip - adds r0,r0,r0 @ odd exponent: shift up mantissa - adcs r1,r1,r1 -1: - lsrs r3,#2 - adds r2,r3 - lsls r2,#20 - mov r12,r2 @ save result exponent - -@ here -@ r0:r1 y mantissa Q52 [1,4) -@ r12 result exponent -.equ drsqrtapp_minus_8, (drsqrtapp-8) - adr r4,drsqrtapp_minus_8 @ first eight table entries are never accessed because of the mantissa's leading 1 - lsrs r2,r1,#17 @ y Q3 - ldrb r2,[r4,r2] @ initial approximation to reciprocal square root a0 Q8 - lsrs r3,r1,#4 @ first Newton-Raphson iteration - muls r3,r2 - muls r3,r2 @ i32 p0=a0*a0*(y>>14); // Q32 - asrs r3,r3,#12 @ i32 r0=p0>>12; // Q20 - muls r3,r2 - asrs r3,#13 @ i32 dy0=(r0*a0)>>13; // Q15 - lsls r2,#8 - subs r2,r3 @ i32 a1=(a0<<8)-dy0; // Q16 - - movs r3,r2 - muls r3,r3 - lsrs r3,#13 - lsrs r4,r1,#1 - muls r3,r4 @ i32 p1=((a1*a1)>>11)*(y>>11); // Q19*Q19=Q38 - asrs r3,#15 @ i32 r1=p1>>15; // Q23 - muls r3,r2 - asrs r3,#23 - adds r3,#1 - asrs r3,#1 @ i32 dy1=(r1*a1+(1<<23))>>24; // Q23*Q16=Q39; Q15 - subs r2,r3 @ i32 a2=a1-dy1; // Q16 - lsrs r3,r2,#16 - subs r2,r3 @ if(a2>=0x10000) a2=0xffff; to prevent overflow of a2*a2 - -@ here -@ r0:r1 y mantissa -@ r2 a2 ~ 1/sqrt(y) Q16 -@ r12 result exponent - - movs r3,r2 - muls r3,r3 - lsls r1,#10 - lsrs r4,r0,#22 - orrs r1,r4 @ y Q30 - mul32_32_64 r1,r3, r4,r3, r5,r6,r7,r4,r3 @ i64 p2=(ui64)(a2*a2)*(ui64)y; // Q62 r4:r3 - lsls r5,r3,#6 - lsrs r4,#26 - orrs r4,r5 - adds r4,#0x20 @ i32 r2=(p2>>26)+0x20; // Q36 r4 - uxth r5,r4 - muls r5,r2 - asrs r4,#16 - muls r4,r2 - lsrs r5,#16 - adds r4,r5 - asrs r4,#6 @ i32 dy2=((i64)r2*(i64)a2)>>22; // Q36*Q16=Q52; Q30 - lsls r2,#15 - subs r2,r4 - -@ here -@ r0 y low bits -@ r1 y Q30 -@ r2 a3 ~ 1/sqrt(y) Q31 -@ r12 result exponent - - mul32_32_64 r2,r1, r3,r4, r5,r6,r7,r3,r4 - adds r3,r3,r3 - adcs r4,r4,r4 - adds r3,r3,r3 - movs r3,#0 - adcs r3,r4 @ ui32 a4=((ui64)a3*(ui64)y+(1U<<31))>>31; // Q30 - -@ here -@ r0 y low bits -@ r1 y Q30 -@ r2 a3 Q31 ~ 1/sqrt(y) -@ r3 a4 Q30 ~ sqrt(y) -@ r12 result exponent - - square32_64 r3, r4,r5, r6,r5,r7 - lsls r6,r0,#8 - lsrs r7,r1,#2 - subs r6,r4 - sbcs r7,r5 @ r4=(q60)y-a4*a4 - -@ by exhaustive testing, r4 = fffffffc0e134fdc .. 00000003c2bf539c Q60 - - lsls r5,r7,#29 - lsrs r6,#3 - adcs r6,r5 @ r4 Q57 with rounding - muls32_32_64 r6,r2, r6,r2, r4,r5,r7,r6,r2 @ d4=a3*r4/2 Q89 -@ r4+d4 is correct to 1ULP at Q57, tested on ~9bn cases including all extreme values of r4 for each possible y Q30 - - adds r2,#8 - asrs r2,#5 @ d4 Q52, rounded to Q53 with spare bit in carry - -@ here -@ r0 y low bits -@ r1 y Q30 -@ r2 d4 Q52, rounded to Q53 -@ C flag contains d4_b53 -@ r3 a4 Q30 - - bcs dq_5 - - lsrs r5,r3,#10 @ a4 Q52 - lsls r4,r3,#22 - - asrs r1,r2,#31 - adds r0,r2,r4 - adcs r1,r5 @ a4+d4 - - add r1,r12 @ pack exponent - pop {r4-r7,r15} - -.ltorg - - -@ round(sqrt(2^22./[68:8:252])) -drsqrtapp: -.byte 0xf8,0xeb,0xdf,0xd6,0xcd,0xc5,0xbe,0xb8 -.byte 0xb2,0xad,0xa8,0xa4,0xa0,0x9c,0x99,0x95 -.byte 0x92,0x8f,0x8d,0x8a,0x88,0x85,0x83,0x81 - -dq_5: -@ here we are near a rounding boundary, C is set - adcs r2,r2,r2 @ d4 Q53+1ulp - lsrs r5,r3,#9 - lsls r4,r3,#23 @ r4:r5 a4 Q53 - asrs r1,r2,#31 - adds r4,r2,r4 - adcs r5,r1 @ r4:r5 a5=a4+d4 Q53+1ulp - movs r3,r5 - muls r3,r4 - square32_64 r4,r1,r2,r6,r2,r7 - adds r2,r3 - adds r2,r3 @ r1:r2 a5^2 Q106 - lsls r0,#22 @ y Q84 - - negs r1,r1 - sbcs r0,r2 @ remainder y-a5^2 - bmi 1f @ y=0 -@ ω+=dω -@ x+=y>>i, y-=x>>i - adds r0,r3 - adcs r1,r4 - - mov r3,r11 - asrs r3,r7 - mov r4,r11 - lsls r4,r6 - mov r2,r10 - lsrs r2,r7 - orrs r2,r4 @ r2:r3 y>>i, rounding in carry - mov r4,r8 - mov r5,r9 @ r4:r5 x - adcs r2,r4 - adcs r3,r5 @ r2:r3 x+(y>>i) - mov r8,r2 - mov r9,r3 - - mov r3,r5 - lsls r3,r6 - asrs r5,r7 - lsrs r4,r7 - orrs r4,r3 @ r4:r5 x>>i, rounding in carry - mov r2,r10 - mov r3,r11 - sbcs r2,r4 - sbcs r3,r5 @ r2:r3 y-(x>>i) - mov r10,r2 - mov r11,r3 - bx r14 - - -@ ω>0 / y<0 -@ ω-=dω -@ x-=y>>i, y+=x>>i -1: - subs r0,r3 - sbcs r1,r4 - - mov r3,r9 - asrs r3,r7 - mov r4,r9 - lsls r4,r6 - mov r2,r8 - lsrs r2,r7 - orrs r2,r4 @ r2:r3 x>>i, rounding in carry - mov r4,r10 - mov r5,r11 @ r4:r5 y - adcs r2,r4 - adcs r3,r5 @ r2:r3 y+(x>>i) - mov r10,r2 - mov r11,r3 - - mov r3,r5 - lsls r3,r6 - asrs r5,r7 - lsrs r4,r7 - orrs r4,r3 @ r4:r5 y>>i, rounding in carry - mov r2,r8 - mov r3,r9 - sbcs r2,r4 - sbcs r3,r5 @ r2:r3 x-(y>>i) - mov r8,r2 - mov r9,r3 - bx r14 - -@ convert packed double in r0:r1 to signed/unsigned 32/64-bit integer/fixed-point value in r0:r1 [with r2 places after point], with rounding towards -Inf -@ fixed-point versions only work with reasonable values in r2 because of the way dunpacks works - -double_section double2int_shim - regular_func double2int_shim - movs r2,#0 @ and fall through -regular_func double2fix_shim - push {r14} - adds r2,#32 - bl double2fix64_shim - movs r0,r1 - pop {r15} - -double_section double2uint_shim - regular_func double2uint_shim - movs r2,#0 @ and fall through -regular_func double2ufix_shim - push {r14} - adds r2,#32 - bl double2ufix64_shim - movs r0,r1 - pop {r15} - -double_section double2int64_shim - regular_func double2int64_shim - movs r2,#0 @ and fall through -regular_func double2fix64_shim - push {r14} - bl d2fix - - asrs r2,r1,#31 - cmp r2,r3 - bne 1f @ sign extension bits fail to match sign of result? - pop {r15} -1: - mvns r0,r3 - movs r1,#1 - lsls r1,#31 - eors r1,r1,r0 @ generate extreme fixed-point values - pop {r15} - -double_section double2uint64_shim - regular_func double2uint64_shim - movs r2,#0 @ and fall through -regular_func double2ufix64_shim - asrs r3,r1,#20 @ negative? return 0 - bmi ret_dzero -@ and fall through - -@ convert double in r0:r1 to signed fixed point in r0:r1:r3, r2 places after point, rounding towards -Inf -@ result clamped so that r3 can only be 0 or -1 -@ trashes r12 -.thumb_func -d2fix: - push {r4,r14} - mov r12,r2 - bl dunpacks - asrs r4,r2,#16 - adds r4,#1 - bge 1f - movs r1,#0 @ -0 -> +0 -1: - asrs r3,r1,#31 - ldr r4, =d2fix_a - bx r4 - -ret_dzero: - movs r0,#0 - movs r1,#0 - bx r14 - -.weak d2fix_a // weak because it exists in float code too -.thumb_func -d2fix_a: -@ here -@ r0:r1 two's complement mantissa -@ r2 unbaised exponent -@ r3 mantissa sign extension bits - add r2,r12 @ exponent plus offset for required binary point position - subs r2,#52 @ required shift - bmi 1f @ shift down? -@ here a shift up by r2 places - cmp r2,#12 @ will clamp? - bge 2f - movs r4,r0 - lsls r1,r2 - lsls r0,r2 - negs r2,r2 - adds r2,#32 @ complementary shift - lsrs r4,r2 - orrs r1,r4 - pop {r4,r15} -2: - mvns r0,r3 - mvns r1,r3 @ overflow: clamp to extreme fixed-point values - pop {r4,r15} -1: -@ here a shift down by -r2 places - adds r2,#32 - bmi 1f @ long shift? - mov r4,r1 - lsls r4,r2 - negs r2,r2 - adds r2,#32 @ complementary shift - asrs r1,r2 - lsrs r0,r2 - orrs r0,r4 - pop {r4,r15} -1: -@ here a long shift down - movs r0,r1 - asrs r1,#31 @ shift down 32 places - adds r2,#32 - bmi 1f @ very long shift? - negs r2,r2 - adds r2,#32 - asrs r0,r2 - pop {r4,r15} -1: - movs r0,r3 @ result very near zero: use sign extension bits - movs r1,r3 - pop {r4,r15} - -double_section double2float_shim - regular_func double2float_shim - lsls r2,r1,#1 - lsrs r2,#21 @ exponent - ldr r3,=0x3ff-0x7f - subs r2,r3 @ fix exponent bias - ble 1f @ underflow or zero - cmp r2,#0xff - bge 2f @ overflow or infinity - lsls r2,#23 @ position exponent of result - lsrs r3,r1,#31 - lsls r3,#31 - orrs r2,r3 @ insert sign - lsls r3,r0,#3 @ rounding bits - lsrs r0,#29 - lsls r1,#12 - lsrs r1,#9 - orrs r0,r1 @ assemble mantissa - orrs r0,r2 @ insert exponent and sign - lsls r3,#1 - bcc 3f @ no rounding - beq 4f @ all sticky bits 0? -5: - adds r0,#1 -3: - bx r14 -4: - lsrs r3,r0,#1 @ odd? then round up - bcs 5b - bx r14 -1: - beq 6f @ check case where value is just less than smallest normal -7: - lsrs r0,r1,#31 - lsls r0,#31 - bx r14 -6: - lsls r2,r1,#12 @ 20 1:s at top of mantissa? - asrs r2,#12 - adds r2,#1 - bne 7b - lsrs r2,r0,#29 @ and 3 more 1:s? - cmp r2,#7 - bne 7b - movs r2,#1 @ return smallest normal with correct sign - b 8f -2: - movs r2,#0xff -8: - lsrs r0,r1,#31 @ return signed infinity - lsls r0,#8 - adds r0,r2 - lsls r0,#23 - bx r14 - -double_section x2double_shims -@ convert signed/unsigned 32/64-bit integer/fixed-point value in r0:r1 [with r2 places after point] to packed double in r0:r1, with rounding - -.align 2 -regular_func uint2double_shim - movs r1,#0 @ and fall through -regular_func ufix2double_shim - movs r2,r1 - movs r1,#0 - b ufix642double_shim - -.align 2 -regular_func int2double_shim - movs r1,#0 @ and fall through -regular_func fix2double_shim - movs r2,r1 - asrs r1,r0,#31 @ sign extend - b fix642double_shim - -.align 2 -regular_func uint642double_shim - movs r2,#0 @ and fall through -regular_func ufix642double_shim - movs r3,#0 - b uf2d - -.align 2 -regular_func int642double_shim - movs r2,#0 @ and fall through -regular_func fix642double_shim - asrs r3,r1,#31 @ sign bit across all bits - eors r0,r3 - eors r1,r3 - subs r0,r3 - sbcs r1,r3 -uf2d: - push {r4,r5,r14} - ldr r4,=0x432 - subs r2,r4,r2 @ form biased exponent -@ here -@ r0:r1 unnormalised mantissa -@ r2 -Q (will become exponent) -@ r3 sign across all bits - cmp r1,#0 - bne 1f @ short normalising shift? - movs r1,r0 - beq 2f @ zero? return it - movs r0,#0 - subs r2,#32 @ fix exponent -1: - asrs r4,r1,#21 - bne 3f @ will need shift down (and rounding?) - bcs 4f @ normalised already? -5: - subs r2,#1 - adds r0,r0 @ shift up - adcs r1,r1 - lsrs r4,r1,#21 - bcc 5b -4: - ldr r4,=0x7fe - cmp r2,r4 - bhs 6f @ over/underflow? return signed zero/infinity -7: - lsls r2,#20 @ pack and return - adds r1,r2 - lsls r3,#31 - adds r1,r3 -2: - pop {r4,r5,r15} -6: @ return signed zero/infinity according to unclamped exponent in r2 - mvns r2,r2 - lsrs r2,#21 - movs r0,#0 - movs r1,#0 - b 7b - -3: -@ here we need to shift down to normalise and possibly round - bmi 1f @ already normalised to Q63? -2: - subs r2,#1 - adds r0,r0 @ shift up - adcs r1,r1 - bpl 2b -1: -@ here we have a 1 in b63 of r0:r1 - adds r2,#11 @ correct exponent for subsequent shift down - lsls r4,r0,#21 @ save bits for rounding - lsrs r0,#11 - lsls r5,r1,#21 - orrs r0,r5 - lsrs r1,#11 - lsls r4,#1 - beq 1f @ sticky bits are zero? -8: - movs r4,#0 - adcs r0,r4 - adcs r1,r4 - b 4b -1: - bcc 4b @ sticky bits are zero but not on rounding boundary - lsrs r4,r0,#1 @ increment if odd (force round to even) - b 8b - - -.ltorg - -double_section dunpacks - regular_func dunpacks - mdunpacks r0,r1,r2,r3,r4 - ldr r3,=0x3ff - subs r2,r3 @ exponent without offset - bx r14 - -@ r0:r1 signed mantissa Q52 -@ r2 unbiased exponent < 10 (i.e., |x|<2^10) -@ r4 pointer to: -@ - divisor reciprocal approximation r=1/d Q15 -@ - divisor d Q62 0..20 -@ - divisor d Q62 21..41 -@ - divisor d Q62 42..62 -@ returns: -@ r0:r1 reduced result y Q62, -0.6 d < y < 0.6 d (better in practice) -@ r2 quotient q (number of reductions) -@ if exponent >=10, returns r0:r1=0, r2=1024*mantissa sign -@ designed to work for 0.5=0: in quadrant 0 - cmp r1,r3 - ble 2f @ y<~x so 0≤θ<~π/4: skip - adds r6,#1 - eors r1,r5 @ negate x - b 3f @ and exchange x and y = rotate by -π/2 -1: - cmp r3,r7 - bge 2f @ -y<~x so -π/4<~θ≤0: skip - subs r6,#1 - eors r3,r5 @ negate y and ... -3: - movs r7,r0 @ exchange x and y - movs r0,r2 - movs r2,r7 - movs r7,r1 - movs r1,r3 - movs r3,r7 -2: -@ here -π/4<~θ<~π/4 -@ r6 has quadrant offset - push {r6} - cmp r2,#0 - bne 1f - cmp r3,#0 - beq 10f @ x==0 going into division? - lsls r4,r3,#1 - asrs r4,#21 - adds r4,#1 - bne 1f @ x==Inf going into division? - lsls r4,r1,#1 - asrs r4,#21 - adds r4,#1 @ y also ±Inf? - bne 10f - subs r1,#1 @ make them both just finite - subs r3,#1 - b 1f - -10: - movs r0,#0 - movs r1,#0 - b 12f - -1: - bl ddiv_shim - movs r2,#62 - bl double2fix64_shim -@ r0:r1 y/x - mov r10,r0 - mov r11,r1 - movs r0,#0 @ ω=0 - movs r1,#0 - mov r8,r0 - movs r2,#1 - lsls r2,#30 - mov r9,r2 @ x=1 - - adr r4,dtab_cc - mov r12,r4 - movs r7,#1 - movs r6,#31 -1: - bl dcordic_vec_step - adds r7,#1 - subs r6,#1 - cmp r7,#33 - bne 1b -@ r0:r1 atan(y/x) Q62 -@ r8:r9 x residual Q62 -@ r10:r11 y residual Q62 - mov r2,r9 - mov r3,r10 - subs r2,#12 @ this makes atan(0)==0 -@ the following is basically a division residual y/x ~ atan(residual y/x) - movs r4,#1 - lsls r4,#29 - movs r7,#0 -2: - lsrs r2,#1 - movs r3,r3 @ preserve carry - bmi 1f - sbcs r3,r2 - adds r0,r4 - adcs r1,r7 - lsrs r4,#1 - bne 2b - b 3f -1: - adcs r3,r2 - subs r0,r4 - sbcs r1,r7 - lsrs r4,#1 - bne 2b -3: - lsls r6,r1,#31 - asrs r1,#1 - lsrs r0,#1 - orrs r0,r6 @ Q61 - -12: - pop {r6} - - cmp r6,#0 - beq 1f - ldr r4,=0x885A308D @ π/2 Q61 - ldr r5,=0x3243F6A8 - bpl 2f - mvns r4,r4 @ negative quadrant offset - mvns r5,r5 -2: - lsls r6,#31 - bne 2f @ skip if quadrant offset is ±1 - adds r0,r4 - adcs r1,r5 -2: - adds r0,r4 - adcs r1,r5 -1: - movs r2,#61 - bl fix642double_shim - - bl pop_r8_r11 - pop {r4-r7,r15} - -.ltorg - -dtab_cc: -.word 0x61bb4f69, 0x1dac6705 @ atan 2^-1 Q62 -.word 0x96406eb1, 0x0fadbafc @ atan 2^-2 Q62 -.word 0xab0bdb72, 0x07f56ea6 @ atan 2^-3 Q62 -.word 0xe59fbd39, 0x03feab76 @ atan 2^-4 Q62 -.word 0xba97624b, 0x01ffd55b @ atan 2^-5 Q62 -.word 0xdddb94d6, 0x00fffaaa @ atan 2^-6 Q62 -.word 0x56eeea5d, 0x007fff55 @ atan 2^-7 Q62 -.word 0xaab7776e, 0x003fffea @ atan 2^-8 Q62 -.word 0x5555bbbc, 0x001ffffd @ atan 2^-9 Q62 -.word 0xaaaaadde, 0x000fffff @ atan 2^-10 Q62 -.word 0xf555556f, 0x0007ffff @ atan 2^-11 Q62 -.word 0xfeaaaaab, 0x0003ffff @ atan 2^-12 Q62 -.word 0xffd55555, 0x0001ffff @ atan 2^-13 Q62 -.word 0xfffaaaab, 0x0000ffff @ atan 2^-14 Q62 -.word 0xffff5555, 0x00007fff @ atan 2^-15 Q62 -.word 0xffffeaab, 0x00003fff @ atan 2^-16 Q62 -.word 0xfffffd55, 0x00001fff @ atan 2^-17 Q62 -.word 0xffffffab, 0x00000fff @ atan 2^-18 Q62 -.word 0xfffffff5, 0x000007ff @ atan 2^-19 Q62 -.word 0xffffffff, 0x000003ff @ atan 2^-20 Q62 -.word 0x00000000, 0x00000200 @ atan 2^-21 Q62 @ consider optimising these -.word 0x00000000, 0x00000100 @ atan 2^-22 Q62 -.word 0x00000000, 0x00000080 @ atan 2^-23 Q62 -.word 0x00000000, 0x00000040 @ atan 2^-24 Q62 -.word 0x00000000, 0x00000020 @ atan 2^-25 Q62 -.word 0x00000000, 0x00000010 @ atan 2^-26 Q62 -.word 0x00000000, 0x00000008 @ atan 2^-27 Q62 -.word 0x00000000, 0x00000004 @ atan 2^-28 Q62 -.word 0x00000000, 0x00000002 @ atan 2^-29 Q62 -.word 0x00000000, 0x00000001 @ atan 2^-30 Q62 -.word 0x80000000, 0x00000000 @ atan 2^-31 Q62 -.word 0x40000000, 0x00000000 @ atan 2^-32 Q62 - -double_section dexp_guts -regular_func dexp_shim - push {r4-r7,r14} - bl dunpacks - adr r4,dreddata1 - bl dreduce - cmp r1,#0 - bge 1f - ldr r4,=0xF473DE6B - ldr r5,=0x2C5C85FD @ ln2 Q62 - adds r0,r4 - adcs r1,r5 - subs r2,#1 -1: - push {r2} - movs r7,#1 @ shift - adr r6,dtab_exp - movs r2,#0 - movs r3,#1 - lsls r3,#30 @ x=1 Q62 - -3: - ldmia r6!,{r4,r5} - mov r12,r6 - subs r0,r4 - sbcs r1,r5 - bmi 1f - - negs r6,r7 - adds r6,#32 @ complementary shift - movs r5,r3 - asrs r5,r7 - movs r4,r3 - lsls r4,r6 - movs r6,r2 - lsrs r6,r7 @ rounding bit in carry - orrs r4,r6 - adcs r2,r4 - adcs r3,r5 @ x+=x>>i - b 2f - -1: - adds r0,r4 @ restore argument - adcs r1,r5 -2: - mov r6,r12 - adds r7,#1 - cmp r7,#33 - bne 3b - -@ here -@ r0:r1 ε (residual x, where x=a+ε) Q62, |ε|≤2^-32 (so fits in r0) -@ r2:r3 exp a Q62 -@ and we wish to calculate exp x=exp a exp ε~(exp a)(1+ε) - muls32_32_64 r0,r3, r4,r1, r5,r6,r7,r4,r1 -@ r4:r1 ε exp a Q(62+62-32)=Q92 - lsrs r4,#30 - lsls r0,r1,#2 - orrs r0,r4 - asrs r1,#30 - adds r0,r2 - adcs r1,r3 - - pop {r2} - negs r2,r2 - adds r2,#62 - bl fix642double_shim @ in principle we can pack faster than this because we know the exponent - pop {r4-r7,r15} - -.ltorg - -.align 2 -regular_func dln_shim - push {r4-r7,r14} - lsls r7,r1,#1 - bcs 5f @ <0 ... - asrs r7,#21 - beq 5f @ ... or =0? return -Inf - adds r7,#1 - beq 6f @ Inf/NaN? return +Inf - bl dunpacks - push {r2} - lsls r1,#9 - lsrs r2,r0,#23 - orrs r1,r2 - lsls r0,#9 -@ r0:r1 m Q61 = m/2 Q62 0.5≤m/2<1 - - movs r7,#1 @ shift - adr r6,dtab_exp - mov r12,r6 - movs r2,#0 - movs r3,#0 @ y=0 Q62 - -3: - negs r6,r7 - adds r6,#32 @ complementary shift - movs r5,r1 - asrs r5,r7 - movs r4,r1 - lsls r4,r6 - movs r6,r0 - lsrs r6,r7 - orrs r4,r6 @ x>>i, rounding bit in carry - adcs r4,r0 - adcs r5,r1 @ x+(x>>i) - - lsrs r6,r5,#30 - bne 1f @ x+(x>>i)>1? - movs r0,r4 - movs r1,r5 @ x+=x>>i - mov r6,r12 - ldmia r6!,{r4,r5} - subs r2,r4 - sbcs r3,r5 - -1: - movs r4,#8 - add r12,r4 - adds r7,#1 - cmp r7,#33 - bne 3b -@ here: -@ r0:r1 residual x, nearly 1 Q62 -@ r2:r3 y ~ ln m/2 = ln m - ln2 Q62 -@ result is y + ln2 + ln x ~ y + ln2 + (x-1) - lsls r1,#2 - asrs r1,#2 @ x-1 - adds r2,r0 - adcs r3,r1 - - pop {r7} -@ here: -@ r2:r3 ln m/2 = ln m - ln2 Q62 -@ r7 unbiased exponent -.equ dreddata1_plus_4, (dreddata1+4) - adr r4,dreddata1_plus_4 - ldmia r4,{r0,r1,r4} - adds r7,#1 - muls r0,r7 @ Q62 - muls r1,r7 @ Q41 - muls r4,r7 @ Q20 - lsls r7,r1,#21 - asrs r1,#11 - asrs r5,r1,#31 - adds r0,r7 - adcs r1,r5 - lsls r7,r4,#10 - asrs r4,#22 - asrs r5,r1,#31 - adds r1,r7 - adcs r4,r5 -@ r0:r1:r4 exponent*ln2 Q62 - asrs r5,r3,#31 - adds r0,r2 - adcs r1,r3 - adcs r4,r5 -@ r0:r1:r4 result Q62 - movs r2,#62 -1: - asrs r5,r1,#31 - cmp r4,r5 - beq 2f @ r4 a sign extension of r1? - lsrs r0,#4 @ no: shift down 4 places and try again - lsls r6,r1,#28 - orrs r0,r6 - lsrs r1,#4 - lsls r6,r4,#28 - orrs r1,r6 - asrs r4,#4 - subs r2,#4 - b 1b -2: - bl fix642double_shim - pop {r4-r7,r15} - -5: - ldr r1,=0xfff00000 - movs r0,#0 - pop {r4-r7,r15} - -6: - ldr r1,=0x7ff00000 - movs r0,#0 - pop {r4-r7,r15} - -.ltorg - -.align 2 -dreddata1: -.word 0x0000B8AA @ 1/ln2 Q15 -.word 0x0013DE6B @ ln2 Q62 Q62=2C5C85FDF473DE6B split into 21-bit pieces -.word 0x000FEFA3 -.word 0x000B1721 - -dtab_exp: -.word 0xbf984bf3, 0x19f323ec @ log 1+2^-1 Q62 -.word 0xcd4d10d6, 0x0e47fbe3 @ log 1+2^-2 Q62 -.word 0x8abcb97a, 0x0789c1db @ log 1+2^-3 Q62 -.word 0x022c54cc, 0x03e14618 @ log 1+2^-4 Q62 -.word 0xe7833005, 0x01f829b0 @ log 1+2^-5 Q62 -.word 0x87e01f1e, 0x00fe0545 @ log 1+2^-6 Q62 -.word 0xac419e24, 0x007f80a9 @ log 1+2^-7 Q62 -.word 0x45621781, 0x003fe015 @ log 1+2^-8 Q62 -.word 0xa9ab10e6, 0x001ff802 @ log 1+2^-9 Q62 -.word 0x55455888, 0x000ffe00 @ log 1+2^-10 Q62 -.word 0x0aa9aac4, 0x0007ff80 @ log 1+2^-11 Q62 -.word 0x01554556, 0x0003ffe0 @ log 1+2^-12 Q62 -.word 0x002aa9ab, 0x0001fff8 @ log 1+2^-13 Q62 -.word 0x00055545, 0x0000fffe @ log 1+2^-14 Q62 -.word 0x8000aaaa, 0x00007fff @ log 1+2^-15 Q62 -.word 0xe0001555, 0x00003fff @ log 1+2^-16 Q62 -.word 0xf80002ab, 0x00001fff @ log 1+2^-17 Q62 -.word 0xfe000055, 0x00000fff @ log 1+2^-18 Q62 -.word 0xff80000b, 0x000007ff @ log 1+2^-19 Q62 -.word 0xffe00001, 0x000003ff @ log 1+2^-20 Q62 -.word 0xfff80000, 0x000001ff @ log 1+2^-21 Q62 -.word 0xfffe0000, 0x000000ff @ log 1+2^-22 Q62 -.word 0xffff8000, 0x0000007f @ log 1+2^-23 Q62 -.word 0xffffe000, 0x0000003f @ log 1+2^-24 Q62 -.word 0xfffff800, 0x0000001f @ log 1+2^-25 Q62 -.word 0xfffffe00, 0x0000000f @ log 1+2^-26 Q62 -.word 0xffffff80, 0x00000007 @ log 1+2^-27 Q62 -.word 0xffffffe0, 0x00000003 @ log 1+2^-28 Q62 -.word 0xfffffff8, 0x00000001 @ log 1+2^-29 Q62 -.word 0xfffffffe, 0x00000000 @ log 1+2^-30 Q62 -.word 0x80000000, 0x00000000 @ log 1+2^-31 Q62 -.word 0x40000000, 0x00000000 @ log 1+2^-32 Q62 - - -#endif diff --git a/lib/main/pico-sdk/rp2_common/pico_double/include/pico/double.h b/lib/main/pico-sdk/rp2_common/pico_double/include/pico/double.h deleted file mode 100644 index f8c2b4dd56..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_double/include/pico/double.h +++ /dev/null @@ -1,79 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _PICO_DOUBLE_H -#define _PICO_DOUBLE_H - -#include -#include "pico.h" -#include "pico/bootrom/sf_table.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** \file double.h -* \defgroup pico_double pico_double -* -* \brief Optimized double-precision floating point functions -* -* (Replacement) optimized implementations are provided of the following compiler built-ins -* and math library functions: -* -* - __aeabi_dadd, __aeabi_ddiv, __aeabi_dmul, __aeabi_drsub, __aeabi_dsub, __aeabi_cdcmpeq, __aeabi_cdrcmple, __aeabi_cdcmple, __aeabi_dcmpeq, __aeabi_dcmplt, __aeabi_dcmple, __aeabi_dcmpge, __aeabi_dcmpgt, __aeabi_dcmpun, __aeabi_i2d, __aeabi_l2d, __aeabi_ui2d, __aeabi_ul2d, __aeabi_d2iz, __aeabi_d2lz, __aeabi_d2uiz, __aeabi_d2ulz, __aeabi_d2f -* - sqrt, cos, sin, tan, atan2, exp, log, ldexp, copysign, trunc, floor, ceil, round, asin, acos, atan, sinh, cosh, tanh, asinh, acosh, atanh, exp2, log2, exp10, log10, pow,, hypot, cbrt, fmod, drem, remainder, remquo, expm1, log1p, fma -* - powint, sincos (GNU extensions) -* -* The following additional optimized functions are also provided: -* -* - int2double, uint2double, int642double, uint642double, fix2double, ufix2double, fix642double, ufix642double -* - double2fix, double2ufix, double2fix64, double2ufix64, double2int, double2uint, double2int64, double2uint64, double2int_z, double2int64_z, -* - exp10, sincos, powint -* -* On RP2350 the following additional functions are available; the _fast methods are faster but do not round correctly" -* -* - ddiv_fast, sqrt_fast -*/ - -double int2double(int32_t i); -double uint2double(uint32_t u); -double int642double(int64_t i); -double uint642double(uint64_t u); -double fix2double(int32_t m, int e); -double ufix2double(uint32_t m, int e); -double fix642double(int64_t m, int e); -double ufix642double(uint64_t m, int e); - -// These methods round towards -Infinity. -int32_t double2fix(double d, int e); -uint32_t double2ufix(double d, int e); -int64_t double2fix64(double d, int e); -uint64_t double2ufix64(double d, int e); -int32_t double2int(double d); -uint32_t double2uint(double d); -int64_t double2int64(double d); -uint64_t double2uint64(double d); - -// These methods round towards 0. -int32_t double2int_z(double d); -int64_t double2int64_z(double d); - -double exp10(double x); -void sincos(double x, double *sinx, double *cosx); -double powint(double x, int y); - -#if !PICO_RP2040 -double ddiv_fast(double n, double d); -double sqrt_fast(double d); -double mla(double x, double y, double z); // note this is not fused -#endif - -#ifdef __cplusplus -} -#endif - -#endif - diff --git a/lib/main/pico-sdk/rp2_common/pico_fix/rp2040_usb_device_enumeration/include/pico/fix/rp2040_usb_device_enumeration.h b/lib/main/pico-sdk/rp2_common/pico_fix/rp2040_usb_device_enumeration/include/pico/fix/rp2040_usb_device_enumeration.h deleted file mode 100644 index 49f115e907..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_fix/rp2040_usb_device_enumeration/include/pico/fix/rp2040_usb_device_enumeration.h +++ /dev/null @@ -1,17 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _PICO_FIX_RP2040_USB_DEVICE_ENUMERATION_H -#define _PICO_FIX_RP2040_USB_DEVICE_ENUMERATION_H - -/*! \brief Perform a brute force workaround for USB device enumeration issue - * \ingroup pico_fix - * - * This method should be called during the IRQ handler for a bus reset - */ -void rp2040_usb_device_enumeration_fix(void); - -#endif \ No newline at end of file diff --git a/lib/main/pico-sdk/rp2_common/pico_fix/rp2040_usb_device_enumeration/rp2040_usb_device_enumeration.c b/lib/main/pico-sdk/rp2_common/pico_fix/rp2040_usb_device_enumeration/rp2040_usb_device_enumeration.c deleted file mode 100644 index 91315d1939..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_fix/rp2040_usb_device_enumeration/rp2040_usb_device_enumeration.c +++ /dev/null @@ -1,154 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "pico.h" -#include "pico/time.h" -#include "hardware/structs/usb.h" -#include "hardware/gpio.h" -#include "hardware/structs/io_bank0.h" -#include "hardware/structs/pads_bank0.h" -#include "pico/fix/rp2040_usb_device_enumeration.h" - -#define LS_SE0 0b00 -#define LS_J 0b01 -#define LS_K 0b10 -#define LS_SE1 0b11 - -#if PICO_RP2040_B0_SUPPORTED || PICO_RP2040_B1_SUPPORTED -static void hw_enumeration_fix_wait_se0(void); -static void hw_enumeration_fix_force_ls_j(void); -static void hw_enumeration_fix_finish(void); - -void rp2040_usb_device_enumeration_fix(void) { - // Actually check for B0/B1 h/w - if (rp2040_chip_version() == 1) { - // After coming out of reset, the hardware expects 800us of LS_J (linestate J) time - // before it will move to the connected state. However on a hub that broadcasts packets - // for other devices this isn't the case. The plan here is to wait for the end of the bus - // reset, force an LS_J for 1ms and then switch control back to the USB phy. Unfortunately - // this requires us to use GPIO15 as there is no other way to force the input path. - // We only need to force DP as DM can be left at zero. It will be gated off by GPIO - // logic if it isn't func selected. - - // Wait SE0 phase will call force ls_j phase which will call finish phase - hw_enumeration_fix_wait_se0(); - } -} - -static inline uint8_t hw_line_state(void) { - return (usb_hw->sie_status & USB_SIE_STATUS_LINE_STATE_BITS) >> USB_SIE_STATUS_LINE_STATE_LSB; -} - -int64_t hw_enumeration_fix_wait_se0_callback(__unused alarm_id_t id, __unused void *user_data) { - if (hw_line_state() == LS_SE0) { - // Come back in 1ms and check again - return 1000; - } else { - // Now force LS_J (next stage of fix) - hw_enumeration_fix_force_ls_j(); - // No more repeats - return 0; - } -} - -static inline void hw_enumeration_fix_busy_wait_se0(void) { - while (hw_line_state() == LS_SE0) tight_loop_contents(); - // Now force LS_J (next stage of fix) - hw_enumeration_fix_force_ls_j(); -} - -static void hw_enumeration_fix_wait_se0(void) { - // Wait for SE0 to end (i.e. the host to stop resetting). This reset can last quite long. - // 10-15ms so we are going to set a timer callback. - -#if !PICO_TIME_DEFAULT_ALARM_POOL_DISABLED - if (add_alarm_in_ms(1, hw_enumeration_fix_wait_se0_callback, NULL, true) >= 0) { - // hw_enumeration_fix_wait_se0_callback will be called in 1ms to check if se0 has finished - // (and will poll every 1ms from there) - return; - } -#endif - // if timer pool disabled, or no timer available, have to busy wait. - hw_enumeration_fix_busy_wait_se0(); -} - -int64_t hw_enumeration_fix_force_ls_j_done(__unused alarm_id_t id, __unused void *user_data) { - hw_enumeration_fix_finish(); - return 0; -} - -static uint32_t gpio_ctrl_prev = 0; -static uint32_t pad_ctrl_prev = 0; -static const uint dp = 15; -static const uint dm = 16; - -static void hw_enumeration_fix_force_ls_j(void) { - // DM must be 0 for this to work. This is true if it is selected - // to any other function. fn 8 on this pin is only for debug so shouldn't - // be selected - hard_assert(gpio_get_function(dm) != 8); - - // Before changing any pin state, take a copy of the current gpio control register - gpio_ctrl_prev = io_bank0_hw->io[dp].ctrl; - // Also take a copy of the pads register - pad_ctrl_prev = pads_bank0_hw->io[dp]; - - // Enable bus keep and force pin to tristate, so USB DP muxing doesn't affect - // pin state - gpio_set_pulls(dp, true, true); - gpio_set_oeover(dp, GPIO_OVERRIDE_LOW); - // Select function 8 (USB debug muxing) without disturbing other controls - hw_write_masked(&io_bank0_hw->io[dp].ctrl, - 8 << IO_BANK0_GPIO15_CTRL_FUNCSEL_LSB, IO_BANK0_GPIO15_CTRL_FUNCSEL_BITS); - - // J state is a differential 1 for a full speed device so - // DP = 1 and DM = 0. Don't actually need to set DM low as it - // is already gated assuming it isn't funcseld. - gpio_set_inover(dp, GPIO_OVERRIDE_HIGH); - - // Force PHY pull up to stay before switching away from the phy - usb_hw_t *usb_hw_set = (usb_hw_t *)hw_set_alias_untyped(usb_hw); - usb_hw_set->phy_direct = USB_USBPHY_DIRECT_DP_PULLUP_EN_BITS; - usb_hw_set->phy_direct_override = USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_EN_OVERRIDE_EN_BITS; - - // Switch to GPIO phy with LS_J forced - usb_hw->muxing = USB_USB_MUXING_TO_DIGITAL_PAD_BITS | USB_USB_MUXING_SOFTCON_BITS; - - // LS_J is now forced but while loop here just to check - hard_assert(hw_line_state() == LS_J); // "LS_J not forced!" - -#if !PICO_TIME_DEFAULT_ALARM_POOL_DISABLED - if (add_alarm_in_ms(1, hw_enumeration_fix_force_ls_j_done, NULL, true) >= 0) { - // hw_enumeration_fix_force_ls_j_done will be called in 1ms - return; - } -#endif - // if timer pool disabled, or no timer available, have to busy wait. - busy_wait_us(1000); - hw_enumeration_fix_finish(); -} - -static void hw_enumeration_fix_finish(void) { - // Should think we are connected now - while (!(usb_hw->sie_status & USB_SIE_STATUS_CONNECTED_BITS)) tight_loop_contents(); - - // Switch back to USB phy - usb_hw->muxing = USB_USB_MUXING_TO_PHY_BITS | USB_USB_MUXING_SOFTCON_BITS; - - // Get rid of DP pullup override - hw_clear_bits(&usb_hw->phy_direct_override, USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_EN_OVERRIDE_EN_BITS); - - // Finally, restore the gpio ctrl value back to GPIO15 - io_bank0_hw->io[dp].ctrl = gpio_ctrl_prev; - // Restore the pad ctrl value - pads_bank0_hw->io[dp] = pad_ctrl_prev; -} - -#else -void rp2040_usb_device_enumeration_fix(void) { - // nothing to do -} -#endif \ No newline at end of file diff --git a/lib/main/pico-sdk/rp2_common/pico_flash/flash.c b/lib/main/pico-sdk/rp2_common/pico_flash/flash.c deleted file mode 100644 index 0d56067485..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_flash/flash.c +++ /dev/null @@ -1,220 +0,0 @@ -/* - * Copyright (c) 2023 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "pico/flash.h" -#include "hardware/sync.h" -#if PICO_FLASH_SAFE_EXECUTE_PICO_SUPPORT_MULTICORE_LOCKOUT -#include "pico/multicore.h" -#endif -#if PICO_FLASH_SAFE_EXECUTE_SUPPORT_FREERTOS_SMP -#include "FreeRTOS.h" -#include "task.h" -// now we have FreeRTOS header we can check core count... we can only use FreeRTOS SMP mechanism -// with two cores -#if configNUMBER_OF_CORES == 2 -#if configUSE_CORE_AFFINITY -#define PICO_FLASH_SAFE_EXECUTE_USE_FREERTOS_SMP 1 -#else -#error configUSE_CORE_AFFINITY is required for PICO_FLASH_SAFE_EXECUTE_SUPPORT_FREERTOS_SMP -#endif -#endif -#endif - -// There are multiple scenarios: -// -// 1. No use of core 1 - we just want to disable IRQs and not wait on core 1 to acquiesce -// 2. Regular pico_multicore - we need to use multicore lockout. -// 3. FreeRTOS on core 0, no use of core 1 - we just want to disable IRQs -// 4. FreeRTOS SMP on both cores - we need to schedule a high priority task on the other core to disable IRQs. -// 5. FreeRTOS on one core, but application is using the other core. ** WE CANNOT SUPPORT THIS TODAY ** without -// the equivalent PICO_FLASH_ASSUME_COREx_SAFE (i.e. the user making sure the other core is fine) - -static bool default_core_init_deinit(bool init); -static int default_enter_safe_zone_timeout_ms(uint32_t timeout_ms); -static int default_exit_safe_zone_timeout_ms(uint32_t timeout_ms); - -// note the default methods are combined, rather than having a separate helper for -// FreeRTOS, as we may support mixed multicore and non SMP FreeRTOS in the future - -static flash_safety_helper_t default_flash_safety_helper = { - .core_init_deinit = default_core_init_deinit, - .enter_safe_zone_timeout_ms = default_enter_safe_zone_timeout_ms, - .exit_safe_zone_timeout_ms = default_exit_safe_zone_timeout_ms -}; - -#if PICO_FLASH_SAFE_EXECUTE_USE_FREERTOS_SMP -enum { - FREERTOS_LOCKOUT_NONE = 0, - FREERTOS_LOCKOUT_LOCKER_WAITING, - FREERTOS_LOCKOUT_LOCKEE_READY, - FREERTOS_LOCKOUT_LOCKER_DONE, - FREERTOS_LOCKOUT_LOCKEE_DONE, -}; -// state for the lockout operation launched from the corresponding core -static volatile uint8_t lockout_state[NUM_CORES]; -#endif - -__attribute__((weak)) flash_safety_helper_t *get_flash_safety_helper(void) { - return &default_flash_safety_helper; -} - -bool flash_safe_execute_core_init(void) { - flash_safety_helper_t *helper = get_flash_safety_helper(); - return helper ? helper->core_init_deinit(true) : false; -} - -bool flash_safe_execute_core_deinit(void) { - flash_safety_helper_t *helper = get_flash_safety_helper(); - return helper ? helper->core_init_deinit(false) : false; -} - -int flash_safe_execute(void (*func)(void *), void *param, uint32_t enter_exit_timeout_ms) { - flash_safety_helper_t *helper = get_flash_safety_helper(); - if (!helper) return PICO_ERROR_NOT_PERMITTED; - int rc = helper->enter_safe_zone_timeout_ms(enter_exit_timeout_ms); - if (!rc) { - func(param); - rc = helper->exit_safe_zone_timeout_ms(enter_exit_timeout_ms); - } - return rc; -} - -static bool default_core_init_deinit(__unused bool init) { -#if PICO_FLASH_ASSUME_CORE0_SAFE - if (!get_core_num()) return true; -#endif -#if PICO_FLASH_ASSUME_CORE1_SAFE - if (get_core_num()) return true; -#endif -#if PICO_FLASH_SAFE_EXECUTE_USE_FREERTOS_SMP - return true; -#endif -#if PICO_FLASH_SAFE_EXECUTE_PICO_SUPPORT_MULTICORE_LOCKOUT - if (!init) { - return false; - } - multicore_lockout_victim_init(); -#endif - return true; -} - -// irq_state for the lockout operation launched from the corresponding core -static uint32_t irq_state[NUM_CORES]; - -static bool use_irq_only(void) { -#if PICO_FLASH_ASSUME_CORE0_SAFE - if (get_core_num()) return true; -#endif -#if PICO_FLASH_ASSUME_CORE1_SAFE - if (!get_core_num()) return true; -#endif - return false; -} - -#if PICO_FLASH_SAFE_EXECUTE_USE_FREERTOS_SMP -static void __not_in_flash_func(flash_lockout_task)(__unused void *vother_core_num) { - uint other_core_num = (uintptr_t)vother_core_num; - while (lockout_state[other_core_num] != FREERTOS_LOCKOUT_LOCKER_WAITING) { - __wfe(); // we don't bother to try to let lower priority tasks run - } - uint32_t save = save_and_disable_interrupts(); - lockout_state[other_core_num] = FREERTOS_LOCKOUT_LOCKEE_READY; - __sev(); - while (lockout_state[other_core_num] == FREERTOS_LOCKOUT_LOCKEE_READY) { - __wfe(); // we don't bother to try to let lower priority tasks run - } - restore_interrupts(save); - lockout_state[other_core_num] = FREERTOS_LOCKOUT_LOCKEE_DONE; - __sev(); - // bye bye - vTaskDelete(NULL); -} -#endif - -static int default_enter_safe_zone_timeout_ms(__unused uint32_t timeout_ms) { - int rc = PICO_OK; - if (!use_irq_only()) { -#if PICO_FLASH_SAFE_EXECUTE_USE_FREERTOS_SMP - // Note that whilst taskENTER_CRITICAL sounds promising (and on non SMP it disabled IRQs), on SMP - // it only prevents the other core from also entering a critical section. - // Therefore, we must do our own handshake which starts a task on the other core and have it disable interrupts - uint core_num = get_core_num(); - // create at low priority - TaskHandle_t task_handle; - if (pdPASS != xTaskCreate(flash_lockout_task, "flash lockout", configMINIMAL_STACK_SIZE, (void *)core_num, 0, &task_handle)) { - return PICO_ERROR_INSUFFICIENT_RESOURCES; - } - lockout_state[core_num] = FREERTOS_LOCKOUT_LOCKER_WAITING; - __sev(); - // bind to other core - vTaskCoreAffinitySet(task_handle, 1u << (core_num ^ 1)); - // and make it super high priority - vTaskPrioritySet(task_handle, configMAX_PRIORITIES -1); - absolute_time_t until = make_timeout_time_ms(timeout_ms); - while (lockout_state[core_num] != FREERTOS_LOCKOUT_LOCKEE_READY && !time_reached(until)) { - __wfe(); // we don't bother to try to let lower priority tasks run - } - if (lockout_state[core_num] != FREERTOS_LOCKOUT_LOCKEE_READY) { - lockout_state[core_num] = FREERTOS_LOCKOUT_LOCKER_DONE; - rc = PICO_ERROR_TIMEOUT; - } - // todo we may get preempted here, but I think that is OK unless what is pre-empts requires - // the other core to be running. -#elif PICO_FLASH_SAFE_EXECUTE_PICO_SUPPORT_MULTICORE_LOCKOUT - // we cannot mix multicore_lockout and FreeRTOS as they both use the multicore FIFO... - // the user, will have to roll their own mechanism in this case. -#if LIB_FREERTOS_KERNEL -#if PICO_FLASH_ASSERT_ON_UNSAFE - assert(false); // we expect the other core to have been initialized via flash_safe_execute_core_init() - // unless PICO_FLASH_ASSUME_COREX_SAFE is set -#endif - rc = PICO_ERROR_NOT_PERMITTED; -#else // !LIB_FREERTOS_KERNEL - if (multicore_lockout_victim_is_initialized(get_core_num()^1)) { - if (!multicore_lockout_start_timeout_us(timeout_ms * 1000ull)) { - rc = PICO_ERROR_TIMEOUT; - } - } else { -#if PICO_FLASH_ASSERT_ON_UNSAFE - assert(false); // we expect the other core to have been initialized via flash_safe_execute_core_init() - // unless PICO_FLASH_ASSUME_COREX_SAFE is set -#endif - rc = PICO_ERROR_NOT_PERMITTED; - } -#endif // !LIB_FREERTOS_KERNEL -#else - // no support for making other core safe provided, so fall through to irq - // note this is the case for a regular single core program -#endif - } - if (rc == PICO_OK) { - // we always want to disable IRQs on our core - irq_state[get_core_num()] = save_and_disable_interrupts(); - } - return rc; -} - -static int default_exit_safe_zone_timeout_ms(__unused uint32_t timeout_ms) { - // assume if we're exiting we're called then entry happened successfully - restore_interrupts_from_disabled(irq_state[get_core_num()]); - if (!use_irq_only()) { -#if PICO_FLASH_SAFE_EXECUTE_USE_FREERTOS_SMP - uint core_num = get_core_num(); - lockout_state[core_num] = FREERTOS_LOCKOUT_LOCKER_DONE; - __sev(); - absolute_time_t until = make_timeout_time_ms(timeout_ms); - while (lockout_state[core_num] != FREERTOS_LOCKOUT_LOCKEE_DONE && !time_reached(until)) { - __wfe(); // we don't bother to try to let lower priority tasks run - } - if (lockout_state[core_num] != FREERTOS_LOCKOUT_LOCKEE_DONE) { - return PICO_ERROR_TIMEOUT; - } -#elif PICO_FLASH_SAFE_EXECUTE_PICO_SUPPORT_MULTICORE_LOCKOUT - return multicore_lockout_end_timeout_us(timeout_ms * 1000ull) ? PICO_OK : PICO_ERROR_TIMEOUT; -#endif - } - return PICO_OK; -} \ No newline at end of file diff --git a/lib/main/pico-sdk/rp2_common/pico_flash/include/pico/flash.h b/lib/main/pico-sdk/rp2_common/pico_flash/include/pico/flash.h deleted file mode 100644 index ae16d76d95..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_flash/include/pico/flash.h +++ /dev/null @@ -1,139 +0,0 @@ -/* - * Copyright (c) 2023 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _PICO_FLASH_H -#define _PICO_FLASH_H - -#include "pico.h" - -/** \file pico/flash.h - * \defgroup pico_flash pico_flash - * - * \brief High level flash API - * - * Flash cannot be erased or written to when in XIP mode. However the system cannot directly access memory in the flash - * address space when not in XIP mode. - * - * It is therefore critical that no code or data is being read from flash while flash is been written or erased. - * - * If only one core is being used, then the problem is simple - just disable interrupts; however if code is running on - * the other core, then it has to be asked, nicely, to avoid flash for a bit. This is hard to do if you don't have - * complete control of the code running on that core at all times. - * - * This library provides a \ref flash_safe_execute method which calls a function back having successfully gotten - * into a state where interrupts are disabled, and the other core is not executing or reading from flash. - * - * How it does this is dependent on the supported environment (Free RTOS SMP or pico_multicore). Additionally - * the user can provide their own mechanism by providing a strong definition of \ref get_flash_safety_helper(). - * - * Using the default settings, flash_safe_execute will only call the callback function if the state is safe - * otherwise returning an error (or an assert depending on \ref PICO_FLASH_ASSERT_ON_UNSAFE). - * - * There are conditions where safety would not be guaranteed: - * - * 1. FreeRTOS smp with `configNUM_CORES=1` - FreeRTOS still uses pico_multicore in this case, so \ref flash_safe_execute - * cannot know what the other core is doing, and there is no way to force code execution between a FreeRTOS core - * and a non FreeRTOS core. - * 2. FreeRTOS non SMP with pico_multicore - Again, there is no way to force code execution between a FreeRTOS core and - * a non FreeRTOS core. - * 3. pico_multicore without \ref flash_safe_execute_core_init() having been called on the other core - The - * \ref flash_safe_execute method does not know if code is executing on the other core, so it has to assume it is. Either - * way, it is not able to intervene if \ref flash_safe_execute_core_init() has not been called on the other core. - * - * Fortunately, all is not lost in this situation, you may: - * - * * Set \ref PICO_FLASH_ASSUME_CORE0_SAFE=1 to explicitly say that core 0 is never using flash. - * * Set \ref PICO_FLASH_ASSUME_CORE1_SAFE=1 to explicitly say that core 1 is never using flash. - */ - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief Initialize a core such that the other core can lock it out during \ref flash_safe_execute. - * \ingroup pico_flash - * - * \note This is not necessary for FreeRTOS SMP, but should be used when launching via \ref multicore_launch_core1 - * \return true on success; there is no need to call \ref flash_safe_execute_core_deinit() on failure. - */ -bool flash_safe_execute_core_init(void); - -/** - * \brief De-initialize work done by \ref flash_safe_execute_core_init - * \ingroup pico_flash - * \return true on success - */ -bool flash_safe_execute_core_deinit(void); - -/** - * \brief Execute a function with IRQs disabled and with the other core also not executing/reading flash - * \ingroup pico_flash - * - * \param func the function to call - * \param param the parameter to pass to the function - * \param enter_exit_timeout_ms the timeout for each of the enter/exit phases when coordinating with the other core - * - * \return PICO_OK on success (the function will have been called). - * PICO_ERROR_TIMEOUT on timeout (the function may have been called). - * PICO_ERROR_NOT_PERMITTED if safe execution is not possible (the function will not have been called). - * PICO_ERROR_INSUFFICIENT_RESOURCES if the method fails due to dynamic resource exhaustion (the function will not have been called) - * \note if \ref PICO_FLASH_ASSERT_ON_UNSAFE is 1, this function will assert in debug mode vs returning - * PICO_ERROR_NOT_PERMITTED - */ -int flash_safe_execute(void (*func)(void *), void *param, uint32_t enter_exit_timeout_ms); - -// PICO_CONFIG: PICO_FLASH_ASSERT_ON_UNSAFE, Assert in debug mode rather than returning an error if flash_safe_execute cannot guarantee safety to catch bugs early, type=bool, default=1, group=pico_flash -#ifndef PICO_FLASH_ASSERT_ON_UNSAFE -#define PICO_FLASH_ASSERT_ON_UNSAFE 1 -#endif - -// PICO_CONFIG: PICO_FLASH_ASSUME_CORE0_SAFE, Assume that core 0 will never be accessing flash and so doesn't need to be considered during flash_safe_execute, type=bool, default=0, group=pico_flash -#ifndef PICO_FLASH_ASSUME_CORE0_SAFE -#define PICO_FLASH_ASSUME_CORE0_SAFE 0 -#endif - -// PICO_CONFIG: PICO_FLASH_ASSUME_CORE1_SAFE, Assume that core 1 will never be accessing flash and so doesn't need to be considered during flash_safe_execute, type=bool, default=0, group=pico_flash -#ifndef PICO_FLASH_ASSUME_CORE1_SAFE -#define PICO_FLASH_ASSUME_CORE1_SAFE 0 -#endif - -// PICO_CONFIG: PICO_FLASH_SAFE_EXECUTE_SUPPORT_FREERTOS_SMP, Support using FreeRTOS SMP to make the other core safe during flash_safe_execute, type=bool, default=1 when using FreeRTOS SMP, group=pico_flash -#ifndef PICO_FLASH_SAFE_EXECUTE_SUPPORT_FREERTOS_SMP -#if LIB_FREERTOS_KERNEL && FREE_RTOS_KERNEL_SMP // set by RP2040 SMP port -#define PICO_FLASH_SAFE_EXECUTE_SUPPORT_FREERTOS_SMP 1 -#endif -#endif - -// PICO_CONFIG: PICO_FLASH_SAFE_EXECUTE_PICO_SUPPORT_MULTICORE_LOCKOUT, Support using multicore_lockout functions to make the other core safe during flash_safe_execute, type=bool, default=1 when using pico_multicore, group=pico_flash -#ifndef PICO_FLASH_SAFE_EXECUTE_PICO_SUPPORT_MULTICORE_LOCKOUT -#if LIB_PICO_MULTICORE -#define PICO_FLASH_SAFE_EXECUTE_PICO_SUPPORT_MULTICORE_LOCKOUT 1 -#endif -#endif - -typedef struct { - bool (*core_init_deinit)(bool init); - int (*enter_safe_zone_timeout_ms)(uint32_t timeout_ms); - int (*exit_safe_zone_timeout_ms)(uint32_t timeout_ms); -} flash_safety_helper_t; - -/** - * \brief Internal method to return the flash safety helper implementation. - * \ingroup pico_flash - * - * Advanced users can provide their own implementation of this function to perform - * different inter-core coordination before disabling XIP mode. - * - * @return the \ref flash_safety_helper_t - */ -flash_safety_helper_t *get_flash_safety_helper(void); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/lib/main/pico-sdk/rp2_common/pico_float/float_aeabi_dcp.S b/lib/main/pico-sdk/rp2_common/pico_float/float_aeabi_dcp.S deleted file mode 100644 index 61c2409191..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_float/float_aeabi_dcp.S +++ /dev/null @@ -1,253 +0,0 @@ -/* - * Copyright (c) 2024 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "pico/asm_helper.S" -#if HAS_DOUBLE_COPROCESSOR -#include "hardware/dcp_instr.inc.S" -#include "hardware/dcp_canned.inc.S" - -pico_default_asm_setup - -// todo alignment -//__pre_init __aeabi_float_init, 00020 -// factor out save/restore (there is a copy in double code) - -.macro float_section name -#if PICO_FLOAT_IN_RAM -.section RAM_SECTION_NAME(\name), "ax" -#else -.section SECTION_NAME(\name), "ax" -#endif -.endm - -.macro float_wrapper_section func -float_section WRAPPER_FUNC_NAME(\func) -.endm - -// ============== STATE SAVE AND RESTORE =============== - -.macro saving_func func - // Note we are usually 32-bit aligned already at this point, as most of the - // function bodies contain exactly two 16-bit instructions: bmi and bx lr. - // We want the PCMP word-aligned. -.p2align 2 - // When the engaged flag is set, branch back here to invoke save routine and - // hook lr with the restore routine, then fall back through to the entry - // point. The engaged flag will be clear when checked a second time. -1: - push {lr} // 16-bit instruction - bl generic_save_state // 32-bit instruction - b 1f // 16-bit instruction - // This is the actual entry point: -wrapper_func \func - PCMP apsr_nzcv - bmi 1b -1: -.endm - -.macro saving_func_return - bx lr -.endm - -float_section __rp2350_dcp_engaged_state_save_restore -.thumb_func -generic_save_state: - sub sp, #24 - push {r0, r1} - // do save here - PXMD r0, r1 - strd r0, r1, [sp, #8 + 0] - PYMD r0, r1 - strd r0, r1, [sp, #8 + 8] - REFD r0, r1 - strd r0, r1, [sp, #8 + 16] - pop {r0, r1} - blx lr - // <- wrapped function returns here - // fall through into restore: -.thumb_func -generic_restore_state: - // do restore here - pop {r12, r14} - WXMD r12, r14 - pop {r12, r14} - WYMD r12, r14 - pop {r12, r14} - WEFD r12, r14 - pop {pc} - -// ============== ARITHMETIC FUNCTIONS =============== - -float_wrapper_section __aeabi_fadd -saving_func __aeabi_fadd - dcp_fadd_m r0,r0,r1 - saving_func_return - -float_wrapper_section __aeabi_fsub -saving_func __aeabi_fsub - dcp_fsub_m r0,r0,r1 - saving_func_return - -float_wrapper_section __aeabi_frsub -saving_func __aeabi_frsub - dcp_fsub_m r0,r1,r0 - saving_func_return - -float_wrapper_section __aeabi_fmul -saving_func __aeabi_fmul - dcp_fmul_m r0,r0,r1,r0,r1 - saving_func_return - -float_section fdiv_fast -saving_func fdiv_fast - dcp_fdiv_fast_m r0,r0,r1,r0,r1,r2 - saving_func_return - -float_wrapper_section __aeabi_fdiv -saving_func __aeabi_fdiv -@ with correct rounding - dcp_fdiv_m r0,r0,r1,r0,r1,r2,r3 - saving_func_return - -float_section sqrtf_fast -saving_func sqrtf_fast - dcp_fsqrt_fast_m r0,r0,r0,r1,r2,r3 - saving_func_return - -float_wrapper_section sqrtf -saving_func sqrtf -@ with correct rounding - dcp_fsqrt_m r0,r0,r0,r1,r2,r3 - saving_func_return - -// todo not a real thing -float_wrapper_section __aeabi_fclassify -saving_func __aeabi_fclassify - dcp_fclassify_m apsr_nzcv,r0 - saving_func_return - -// ============== CONVERSION FUNCTIONS =============== - -float_wrapper_section __aeabi_f2d -saving_func __aeabi_f2d - dcp_float2double_m r0,r1,r0 - saving_func_return - -float_wrapper_section __aeabi_i2f -saving_func __aeabi_i2f -@ with rounding - dcp_int2float_m r0,r0 - saving_func_return - -float_wrapper_section __aeabi_ui2f -saving_func __aeabi_ui2f -@ with rounding - dcp_uint2float_m r0,r0 - saving_func_return - -float_wrapper_section __aeabi_f2iz -saving_func __aeabi_f2iz -@ with truncation towards 0 - dcp_float2int_m r0,r0 - saving_func_return - -float_wrapper_section __aeabi_f2uiz -saving_func __aeabi_f2uiz -@ with truncation towards 0 - dcp_float2uint_m r0,r0 - saving_func_return - -// todo not a real thing -float_wrapper_section __aeabi_f2i_r -saving_func __aeabi_f2i_r -@ with rounding - dcp_float2int_r_m r0,r0 - saving_func_return - -// todo not a real thing -float_wrapper_section __aeabi_f2ui_r -saving_func __aeabi_f2ui_r -@ with rounding - dcp_float2uint_r_m r0,r0 - saving_func_return - -// ============== COMPARISON FUNCTIONS =============== - -float_wrapper_section __aeabi_fcmpun -saving_func __aeabi_fcmpun - dcp_fcmp_m r0,r0,r1 - // extract unordered bit - ubfx r0, r0, #28, #1 - saving_func_return - -float_wrapper_section __aeabi_fcmp -saving_func __aeabi_cfrcmple - dcp_fcmp_m apsr_nzcv,r1,r0 // with arguments reversed - bvs cmp_nan - saving_func_return - -// these next two can be the same function in the absence of exceptions -saving_func __aeabi_cfcmple - dcp_fcmp_m apsr_nzcv,r0,r1 - bvs cmp_nan - saving_func_return - -// It is not clear from the ABI documentation whether cfcmpeq must set the C flag -// in the same way as cfcmple. If not, we could save the "bvs" below; but we -// err on the side of caution. -saving_func __aeabi_cfcmpeq - dcp_fcmp_m apsr_nzcv,r0,r1 - bvs cmp_nan - saving_func_return - -// If the result of a flag-setting comparison is "unordered" then we need to set C and clear Z. -// We could conceivably just do lsrs r12,r14,#1, or even cmp r14,r14,lsr#1 as (a) r14 here is a -// return address and r14b0=1 for Thumb mode; (b) we are unlikely to be returning to address 0. -cmp_nan: - movs r12, #3 // r12 does not need to be preserved by the flag-setting comparisons - lsrs r12, #1 // set C, clear Z - saving_func_return - -float_wrapper_section __aeabi_fcmpeq -saving_func __aeabi_fcmpeq - dcp_fcmp_m r0,r0,r1 - // extract Z - ubfx r0, r0, #30, #1 - saving_func_return - -float_wrapper_section __aeabi_fcmplt -saving_func __aeabi_fcmplt - dcp_fcmp_m apsr_nzcv,r1,r0 - ite hi - movhi r0,#1 - movls r0,#0 - saving_func_return - -float_wrapper_section __aeabi_fcmple -saving_func __aeabi_fcmple - dcp_fcmp_m apsr_nzcv,r1,r0 - ite hs - movhs r0,#1 - movlo r0,#0 - saving_func_return - -float_wrapper_section __aeabi_fcmpge -saving_func __aeabi_fcmpge - dcp_fcmp_m apsr_nzcv,r0,r1 - ite hs - movhs r0,#1 - movlo r0,#0 - saving_func_return - -float_wrapper_section __aeabi_fcmpgt -saving_func __aeabi_fcmpgt - dcp_fcmp_m apsr_nzcv,r0,r1 - ite hi - movhi r0,#1 - movls r0,#0 - saving_func_return - -#endif diff --git a/lib/main/pico-sdk/rp2_common/pico_float/float_aeabi_rp2040.S b/lib/main/pico-sdk/rp2_common/pico_float/float_aeabi_rp2040.S deleted file mode 100644 index 8eb83fc220..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_float/float_aeabi_rp2040.S +++ /dev/null @@ -1,776 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "pico/asm_helper.S" -#include "pico/runtime_init.h" -#include "pico/bootrom/sf_table.h" -#include "hardware/divider_helper.S" - -PICO_RUNTIME_INIT_FUNC_RUNTIME(__aeabi_float_init, PICO_RUNTIME_INIT_AEABI_FLOAT) - -pico_default_asm_setup - -.macro float_section name -#if PICO_FLOAT_IN_RAM -.section RAM_SECTION_NAME(\name), "ax" -#else -.section SECTION_NAME(\name), "ax" -#endif -.endm - -.macro float_wrapper_section func -float_section WRAPPER_FUNC_NAME(\func) -.endm - -.macro _float_wrapper_func x - wrapper_func \x -.endm - -.macro wrapper_func_f1 x - _float_wrapper_func \x -#if PICO_FLOAT_PROPAGATE_NANS - mov ip, lr - bl __check_nan_f1 - mov lr, ip -#endif -.endm - -.macro wrapper_func_f2 x - _float_wrapper_func \x -#if PICO_FLOAT_PROPAGATE_NANS - mov ip, lr - bl __check_nan_f2 - mov lr, ip -#endif -.endm - -.section .text - -#if PICO_FLOAT_PROPAGATE_NANS -.thumb_func -__check_nan_f1: - movs r3, #1 - lsls r3, #24 - lsls r2, r0, #1 - adds r2, r3 - bhi 1f - bx lr -1: - bx ip - -.thumb_func -__check_nan_f2: - movs r3, #1 - lsls r3, #24 - lsls r2, r0, #1 - adds r2, r3 - bhi 1f - lsls r2, r1, #1 - adds r2, r3 - bhi 2f - bx lr -2: - mov r0, r1 -1: - bx ip -#endif - -.macro table_tail_call SF_TABLE_OFFSET -#if PICO_FLOAT_SUPPORT_ROM_V1 && PICO_RP2040_B0_SUPPORTED -#ifndef NDEBUG - movs r3, #0 - mov ip, r3 -#endif -#endif - ldr r3, =sf_table - ldr r3, [r3, #\SF_TABLE_OFFSET] - bx r3 -.endm - -.macro shimmable_table_tail_call SF_TABLE_OFFSET shim - ldr r3, =sf_table - ldr r3, [r3, #\SF_TABLE_OFFSET] -#if PICO_FLOAT_SUPPORT_ROM_V1 && PICO_RP2040_B0_SUPPORTED - mov ip, pc -#endif - bx r3 -#if PICO_FLOAT_SUPPORT_ROM_V1 && PICO_RP2040_B0_SUPPORTED -.byte \SF_TABLE_OFFSET, 0xdf -.word \shim -#endif -.endm - - -// note generally each function is in a separate section unless there is fall thru or branching between them -// note fadd, fsub, fmul, fdiv are so tiny and just defer to rom so are lumped together so they can share constant pool - -// note functions are word aligned except where they are an odd number of linear instructions - -// float FUNC_NAME(__aeabi_fadd)(float, float) single-precision addition -float_wrapper_section __aeabi_farithmetic -// float FUNC_NAME(__aeabi_frsub)(float x, float y) single-precision reverse subtraction, y - x - -// frsub first because it is the only one that needs alignment -.align 2 -wrapper_func __aeabi_frsub - eors r0, r1 - eors r1, r0 - eors r0, r1 - // fall thru - -// float FUNC_NAME(__aeabi_fsub)(float x, float y) single-precision subtraction, x - y -wrapper_func_f2 __aeabi_fsub -#if PICO_FLOAT_PROPAGATE_NANS - // we want to return nan for inf-inf or -inf - -inf, but without too much upfront cost - mov r2, r0 - eors r2, r1 - bmi 1f // different signs - push {r0, r1, lr} - bl 1f - b fdiv_fsub_nan_helper -1: -#endif - table_tail_call SF_TABLE_FSUB - -wrapper_func_f2 __aeabi_fadd - table_tail_call SF_TABLE_FADD - -// float FUNC_NAME(__aeabi_fdiv)(float n, float d) single-precision division, n / d -wrapper_func_f2 __aeabi_fdiv -#if PICO_FLOAT_PROPAGATE_NANS - push {r0, r1, lr} - bl 1f - b fdiv_fsub_nan_helper -1: -#endif -#if !PICO_DIVIDER_DISABLE_INTERRUPTS - // to support IRQ usage (or context switch) we must save/restore divider state around call if state is dirty - ldr r2, =(SIO_BASE) - ldr r3, [r2, #SIO_DIV_CSR_OFFSET] - lsrs r3, #SIO_DIV_CSR_DIRTY_SHIFT_FOR_CARRY - bcs fdiv_save_state -#else - // to avoid worrying about IRQs (or context switches), simply disable interrupts around call - push {r4, lr} - mrs r4, PRIMASK - cpsid i - bl fdiv_shim_call - msr PRIMASK, r4 - pop {r4, pc} -#endif -fdiv_shim_call: - table_tail_call SF_TABLE_FDIV -#if !PICO_DIVIDER_DISABLE_INTERRUPTS -fdiv_save_state: - save_div_state_and_lr - bl fdiv_shim_call - ldr r2, =(SIO_BASE) - restore_div_state_and_return -#endif - -fdiv_fsub_nan_helper: -#if PICO_FLOAT_PROPAGATE_NANS - pop {r1, r2} - - // check for infinite op infinite (or rather check for infinite result with both - // operands being infinite) - lsls r3, r0, #1 - asrs r3, r3, #24 - adds r3, #1 - beq 2f - pop {pc} -2: - lsls r1, #1 - asrs r1, r1, #24 - lsls r2, #1 - asrs r2, r2, #24 - ands r1, r2 - adds r1, #1 - bne 3f - // infinite to nan - movs r1, #1 - lsls r1, #22 - orrs r0, r1 -3: - pop {pc} -#endif - -// float FUNC_NAME(__aeabi_fmul)(float, float) single-precision multiplication -wrapper_func_f2 __aeabi_fmul -#if PICO_FLOAT_PROPAGATE_NANS - push {r0, r1, lr} - bl 1f - pop {r1, r2} - - // check for multiplication of infinite by zero (or rather check for infinite result with either - // operand 0) - lsls r3, r0, #1 - asrs r3, r3, #24 - adds r3, #1 - beq 2f - pop {pc} -2: - ands r1, r2 - bne 3f - // infinite to nan - movs r1, #1 - lsls r1, #22 - orrs r0, r1 -3: - pop {pc} -1: -#endif - table_tail_call SF_TABLE_FMUL - -// void FUNC_NAME(__aeabi_cfrcmple)(float, float) reversed 3-way (<, =, ?>) compare [1], result in PSR ZC flags -float_wrapper_section __aeabi_cfcmple -.align 2 -wrapper_func __aeabi_cfrcmple - push {r0-r2, lr} - eors r0, r1 - eors r1, r0 - eors r0, r1 - b __aeabi_cfcmple_guts - -// NOTE these share an implementation as we have no excepting NaNs. -// void FUNC_NAME(__aeabi_cfcmple)(float, float) 3-way (<, =, ?>) compare [1], result in PSR ZC flags -// void FUNC_NAME(__aeabi_cfcmpeq)(float, float) non-excepting equality comparison [1], result in PSR ZC flags -.align 2 -wrapper_func __aeabi_cfcmple -wrapper_func __aeabi_cfcmpeq - push {r0-r2, lr} - -__aeabi_cfcmple_guts: - lsls r2,r0,#1 - lsrs r2,#24 - beq 1f - cmp r2,#0xff - bne 2f - lsls r2, r0, #9 - bhi 3f -1: - lsrs r0,#23 @ clear mantissa if denormal or infinite - lsls r0,#23 -2: - lsls r2,r1,#1 - lsrs r2,#24 - beq 1f - cmp r2,#0xff - bne 2f - lsls r2, r1, #9 - bhi 3f -1: - lsrs r1,#23 @ clear mantissa if denormal or infinite - lsls r1,#23 -2: - movs r2,#1 @ initialise result - eors r1,r0 - bmi 2f @ opposite signs? then can proceed on basis of sign of x - eors r1,r0 @ restore y - bpl 1f - cmp r1,r0 - pop {r0-r2, pc} -1: - cmp r0,r1 - pop {r0-r2, pc} -2: - orrs r1, r0 @ handle 0/-0 - adds r1, r1 @ note this always sets C - beq 3f - mvns r0, r0 @ carry inverse of r0 sign - adds r0, r0 -3: - pop {r0-r2, pc} - - -// int FUNC_NAME(__aeabi_fcmpeq)(float, float) result (1, 0) denotes (=, ?<>) [2], use for C == and != -float_wrapper_section __aeabi_fcmpeq -.align 2 -wrapper_func __aeabi_fcmpeq - push {lr} - bl __aeabi_cfcmpeq - beq 1f - movs r0, #0 - pop {pc} -1: - movs r0, #1 - pop {pc} - -// int FUNC_NAME(__aeabi_fcmplt)(float, float) result (1, 0) denotes (<, ?>=) [2], use for C < -float_wrapper_section __aeabi_fcmplt -.align 2 -wrapper_func __aeabi_fcmplt - push {lr} - bl __aeabi_cfcmple - sbcs r0, r0 - pop {pc} - -// int FUNC_NAME(__aeabi_fcmple)(float, float) result (1, 0) denotes (<=, ?>) [2], use for C <= -float_wrapper_section __aeabi_fcmple -.align 2 -wrapper_func __aeabi_fcmple - push {lr} - bl __aeabi_cfcmple - bls 1f - movs r0, #0 - pop {pc} -1: - movs r0, #1 - pop {pc} - -// int FUNC_NAME(__aeabi_fcmpge)(float, float) result (1, 0) denotes (>=, ?<) [2], use for C >= -float_wrapper_section __aeabi_fcmpge -.align 2 -wrapper_func __aeabi_fcmpge - push {lr} - // because of NaNs it is better to reverse the args than the result - bl __aeabi_cfrcmple - bls 1f - movs r0, #0 - pop {pc} -1: - movs r0, #1 - pop {pc} - -// int FUNC_NAME(__aeabi_fcmpgt)(float, float) result (1, 0) denotes (>, ?<=) [2], use for C > -float_wrapper_section __aeabi_fcmpgt -wrapper_func __aeabi_fcmpgt - push {lr} - // because of NaNs it is better to reverse the args than the result - bl __aeabi_cfrcmple - sbcs r0, r0 - pop {pc} - -// int FUNC_NAME(__aeabi_fcmpun)(float, float) result (1, 0) denotes (?, <=>) [2], use for C99 isunordered() -float_wrapper_section __aeabi_fcmpun -wrapper_func __aeabi_fcmpun - movs r3, #1 - lsls r3, #24 - lsls r2, r0, #1 - adds r2, r3 - bhi 1f - lsls r2, r1, #1 - adds r2, r3 - bhi 1f - movs r0, #0 - bx lr -1: - movs r0, #1 - bx lr - - -// float FUNC_NAME(__aeabi_ui2f)(unsigned) unsigned to float (single precision) conversion -float_wrapper_section __aeabi_ui2f -wrapper_func __aeabi_ui2f -regular_func uint2float - subs r1, r1 - cmp r0, #0 - bne __aeabi_i2f_main - mov r0, r1 - bx lr - -float_wrapper_section __aeabi_i2f -// float FUNC_NAME(__aeabi_i2f)(int) integer to float (single precision) conversion -wrapper_func __aeabi_i2f -regular_func int2float - lsrs r1, r0, #31 - lsls r1, #31 - bpl 1f - negs r0, r0 -1: - cmp r0, #0 - beq 7f -__aeabi_i2f_main: - - mov ip, lr - push {r0, r1} - ldr r3, =sf_clz_func - ldr r3, [r3] - blx r3 - pop {r1, r2} - lsls r1, r0 - subs r0, #158 - negs r0, r0 - - adds r1,#0x80 @ rounding - bcs 5f @ tripped carry? then have leading 1 in C as required (and result is even so can ignore sticky bits) - - lsls r3,r1,#24 @ check bottom 8 bits of r1 - beq 6f @ in rounding-tie case? - lsls r1,#1 @ remove leading 1 -3: - lsrs r1,#9 @ align mantissa - lsls r0,#23 @ align exponent - orrs r0,r2 @ assemble exponent and mantissa -4: - orrs r0,r1 @ apply sign -1: - bx ip -5: - adds r0,#1 @ correct exponent offset - b 3b -6: - lsrs r1,#9 @ ensure even result - lsls r1,#10 - b 3b -7: - bx lr - - -// int FUNC_NAME(__aeabi_f2iz)(float) float (single precision) to integer C-style conversion [3] -float_wrapper_section __aeabi_f2iz -wrapper_func __aeabi_f2iz -regular_func float2int_z - lsls r1, r0, #1 - lsrs r2, r1, #24 - movs r3, #0x80 - lsls r3, #24 - cmp r2, #126 - ble 1f - subs r2, #158 - bge 2f - asrs r1, r0, #31 - lsls r0, #9 - lsrs r0, #1 - orrs r0, r3 - negs r2, r2 - lsrs r0, r2 - lsls r1, #1 - adds r1, #1 - muls r0, r1 - bx lr -1: - movs r0, #0 - bx lr -2: - lsrs r0, #31 - adds r0, r3 - subs r0, #1 - bx lr - - cmn r0, r0 - bcc float2int - push {lr} - lsls r0, #1 - lsrs r0, #1 - movs r1, #0 - bl __aeabi_f2uiz - cmp r0, #0 - bmi 1f - negs r0, r0 - pop {pc} -1: - movs r0, #128 - lsls r0, #24 - pop {pc} - -float_section float2int -regular_func float2int - shimmable_table_tail_call SF_TABLE_FLOAT2INT float2int_shim - -float_section float2fix -regular_func float2fix - shimmable_table_tail_call SF_TABLE_FLOAT2FIX float2fix_shim - -float_section float2ufix -regular_func float2ufix - table_tail_call SF_TABLE_FLOAT2UFIX - -// unsigned FUNC_NAME(__aeabi_f2uiz)(float) float (single precision) to unsigned C-style conversion [3] -float_wrapper_section __aeabi_f2uiz -wrapper_func __aeabi_f2uiz -regular_func float2uint_z - table_tail_call SF_TABLE_FLOAT2UINT - -float_section fix2float -regular_func fix2float - table_tail_call SF_TABLE_FIX2FLOAT - -float_section ufix2float -regular_func ufix2float - table_tail_call SF_TABLE_UFIX2FLOAT - -float_section fix642float -regular_func fix642float - shimmable_table_tail_call SF_TABLE_FIX642FLOAT fix642float_shim - -float_section ufix642float -regular_func ufix642float - shimmable_table_tail_call SF_TABLE_UFIX642FLOAT ufix642float_shim - -// float FUNC_NAME(__aeabi_l2f)(long long) long long to float (single precision) conversion -float_wrapper_section __aeabi_l2f -1: - ldr r2, =__aeabi_i2f - bx r2 -wrapper_func __aeabi_l2f -regular_func int642float - asrs r2, r0, #31 - cmp r1, r2 - beq 1b - shimmable_table_tail_call SF_TABLE_INT642FLOAT int642float_shim - -// float FUNC_NAME(__aeabi_l2f)(long long) long long to float (single precision) conversion -float_wrapper_section __aeabi_ul2f -1: - ldr r2, =__aeabi_ui2f - bx r2 -wrapper_func __aeabi_ul2f -regular_func uint642float - cmp r1, #0 - beq 1b - shimmable_table_tail_call SF_TABLE_UINT642FLOAT uint642float_shim - -// long long FUNC_NAME(__aeabi_f2lz)(float) float (single precision) to long long C-style conversion [3] -float_wrapper_section __aeabi_f2lz -wrapper_func __aeabi_f2lz -regular_func float2int64_z - cmn r0, r0 - bcc float2int64 - push {lr} - lsls r0, #1 - lsrs r0, #1 - movs r1, #0 - bl float2ufix64 - cmp r1, #0 - bmi 1f - movs r2, #0 - negs r0, r0 - sbcs r2, r1 - mov r1, r2 - pop {pc} -1: - movs r1, #128 - lsls r1, #24 - movs r0, #0 - pop {pc} - -float_section float2int64 -regular_func float2int64 - shimmable_table_tail_call SF_TABLE_FLOAT2INT64 float2int64_shim - -float_section float2fix64 -regular_func float2fix64 - shimmable_table_tail_call SF_TABLE_FLOAT2FIX64 float2fix64_shim - -// unsigned long long FUNC_NAME(__aeabi_f2ulz)(float) float to unsigned long long C-style conversion [3] -float_wrapper_section __aeabi_f2ulz -wrapper_func __aeabi_f2ulz -regular_func float2uint64_z - shimmable_table_tail_call SF_TABLE_FLOAT2UINT64 float2uint64_shim - -float_section float2ufix64 -regular_func float2ufix64 - shimmable_table_tail_call SF_TABLE_FLOAT2UFIX64 float2ufix64_shim - -float_wrapper_section __aeabi_f2d -1: -#if PICO_FLOAT_PROPAGATE_NANS - // copy sign bit and 25 NAN id bits into sign bit and significant ID bits, also setting the high id bit - asrs r1, r0, #3 - movs r2, #0xf - lsls r2, #27 - orrs r1, r2 - lsls r0, #25 - bx lr -#endif -wrapper_func __aeabi_f2d -#if PICO_FLOAT_PROPAGATE_NANS - movs r3, #1 - lsls r3, #24 - lsls r2, r0, #1 - adds r2, r3 - bhi 1b -#endif - shimmable_table_tail_call SF_TABLE_FLOAT2DOUBLE float2double_shim - -float_wrapper_section sqrtf -wrapper_func_f1 sqrtf -#if PICO_FLOAT_SUPPORT_ROM_V1 && PICO_RP2040_B0_SUPPORTED - // check for negative - asrs r1, r0, #23 - bmi 1f -#endif - table_tail_call SF_TABLE_FSQRT -#if PICO_FLOAT_SUPPORT_ROM_V1 && PICO_RP2040_B0_SUPPORTED -1: - mvns r0, r1 - cmp r0, #255 - bne 2f - // -0 or -Denormal return -0 (0x80000000) - lsls r0, #31 - bx lr -2: - // return -Inf (0xff800000) - asrs r0, r1, #31 - lsls r0, #23 - bx lr -#endif - -float_wrapper_section cosf -// note we don't use _f1 since we do an infinity/nan check for outside of range -wrapper_func cosf - // rom version only works for -128 < angle < 128 - lsls r1, r0, #1 - lsrs r1, #24 - cmp r1, #127 + 7 - bge 1f -2: - table_tail_call SF_TABLE_FCOS -1: -#if PICO_FLOAT_PROPAGATE_NANS - // also check for infinites - cmp r1, #255 - bne 3f - // infinite to nan - movs r1, #1 - lsls r1, #22 - orrs r0, r1 - bx lr -3: -#endif - ldr r1, =0x40c90fdb // 2 * M_PI - push {lr} - bl remainderf - pop {r1} - mov lr, r1 - b 2b - -float_wrapper_section sinf -// note we don't use _f1 since we do an infinity/nan check for outside of range -wrapper_func sinf - // rom version only works for -128 < angle < 128 - lsls r1, r0, #1 - lsrs r1, #24 - cmp r1, #127 + 7 - bge 1f -2: - table_tail_call SF_TABLE_FSIN -1: -#if PICO_FLOAT_PROPAGATE_NANS - // also check for infinites - cmp r1, #255 - bne 3f - // infinite to nan - movs r1, #1 - lsls r1, #22 - orrs r0, r1 - bx lr -3: -#endif - ldr r1, =0x40c90fdb // 2 * M_PI - push {lr} - bl remainderf - pop {r1} - mov lr, r1 - b 2b - -float_wrapper_section sincosf -// note we don't use _f1 since we do an infinity/nan check for outside of range -wrapper_func sincosf - push {r1, r2, lr} - // rom version only works for -128 < angle < 128 - lsls r3, r0, #1 - lsrs r3, #24 - cmp r3, #127 + 7 - bge 3f -2: - ldr r3, =sf_table - ldr r3, [r3, #SF_TABLE_FSIN] - blx r3 - pop {r2, r3} - str r0, [r2] - str r1, [r3] - pop {pc} -#if PICO_FLOAT_PROPAGATE_NANS -.align 2 - pop {pc} -#endif -3: -#if PICO_FLOAT_PROPAGATE_NANS - // also check for infinites - cmp r3, #255 - bne 4f - // infinite to nan - movs r3, #1 - lsls r3, #22 - orrs r0, r3 - str r0, [r1] - str r0, [r2] - add sp, #12 - bx lr -4: -#endif - ldr r1, =0x40c90fdb // 2 * M_PI - push {lr} - bl remainderf - pop {r1} - mov lr, r1 - b 2b - -float_wrapper_section tanf -// note we don't use _f1 since we do an infinity/nan check for outside of range -wrapper_func tanf - // rom version only works for -128 < angle < 128 - lsls r1, r0, #1 - lsrs r1, #24 - cmp r1, #127 + 7 - bge ftan_out_of_range -ftan_in_range: -#if !PICO_DIVIDER_DISABLE_INTERRUPTS - // to support IRQ usage (or context switch) we must save/restore divider state around call if state is dirty - ldr r2, =(SIO_BASE) - ldr r3, [r2, #SIO_DIV_CSR_OFFSET] - lsrs r3, #SIO_DIV_CSR_DIRTY_SHIFT_FOR_CARRY - bcs ftan_save_state -#else - // to avoid worrying about IRQs (or context switches), simply disable interrupts around call - push {r4, lr} - mrs r4, PRIMASK - cpsid i - bl ftan_shim_call - msr PRIMASK, r4 - pop {r4, pc} -#endif -ftan_shim_call: - table_tail_call SF_TABLE_FTAN -#if !PICO_DIVIDER_DISABLE_INTERRUPTS -ftan_save_state: - save_div_state_and_lr - bl ftan_shim_call - ldr r2, =(SIO_BASE) - restore_div_state_and_return -#endif -ftan_out_of_range: -#if PICO_FLOAT_PROPAGATE_NANS - // also check for infinites - cmp r1, #255 - bne 3f - // infinite to nan - movs r1, #1 - lsls r1, #22 - orrs r0, r1 - bx lr -3: -#endif - ldr r1, =0x40c90fdb // 2 * M_PI - push {lr} - bl remainderf - pop {r1} - mov lr, r1 - b ftan_in_range - -float_wrapper_section atan2f -wrapper_func_f2 atan2f - shimmable_table_tail_call SF_TABLE_FATAN2 fatan2_shim - -float_wrapper_section expf -wrapper_func_f1 expf - table_tail_call SF_TABLE_FEXP - -float_wrapper_section logf -wrapper_func_f1 logf - table_tail_call SF_TABLE_FLN diff --git a/lib/main/pico-sdk/rp2_common/pico_float/float_conv_m33.S b/lib/main/pico-sdk/rp2_common/pico_float/float_conv_m33.S deleted file mode 100644 index dd47a939e1..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_float/float_conv_m33.S +++ /dev/null @@ -1,369 +0,0 @@ -/* - * Copyright (c) 2024 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#if !PICO_RP2040 -#include "pico/asm_helper.S" - -pico_default_asm_setup - -.macro float_section name -#if PICO_FLOAT_IN_RAM -.section RAM_SECTION_NAME(\name), "ax" -#else -.section SECTION_NAME(\name), "ax" -#endif -.endm - -.macro float_wrapper_section func -float_section WRAPPER_FUNC_NAME(\func) -.endm - -float_wrapper_section conv_tof - -@ convert int64 to float, rounding -wrapper_func __aeabi_l2f -regular_func int642float - movs r2,#0 @ fall through -@ convert signed 64-bit fix to float, rounding; number of r0:r1 bits after point in r2 -regular_func fix642float - cmp r1,#0 - bge 10f @ positive? use unsigned code - rsbs r0,#0 - sbc r1,r1,r1,lsl#1 @ make positive - cbz r1,7f @ high word is zero? - clz r3,r1 - subs r3,#8 - bmi 2f - lsls r1,r3 - lsls r12,r0,r3 @ bits that will be lost - rsb r3,#32 - lsr r0,r3 - orr r0,r0,r1 - sub r2,r2,r3 - rsb r2,#149 - adds r12,r12,r12 @ rounding bit into carry - adc r0,r0,r2,lsl#23 @ insert exponent, add rounding - orr r0,r0,#0x80000000 - beq 4f @ potential rounding tie? - cmp r2,#0xfe - bhs 3f @ over/underflow? - bx r14 -2: - add r3,#33 - lsls r12,r1,r3 @ rounding bit in carry, sticky bits in r12 - orrs r12,r12,r0 @ all of low word into sticky bits: affects Z but not C - rsb r3,#33 - lsr r0,r1,r3 -@ push {r14} -@ bl dumpreg -@ pop {r14} - sub r2,r3,r2 - add r2,#22+127+32 - adc r0,r0,r2,lsl#23 @ insert exponent, add rounding - orr r0,r0,#0x80000000 - beq 4f @ potential rounding tie? - cmp r2,#0xfe - it lo - bxlo r14 -@ over/underflow? -3: - mov r0,#0x80000000 @ underflow - it ge - movtge r0,#0xff80 @ overflow -1: - bx r14 -7: - mov r1,r2 - b fix2float_neg -4: - it cs @ rounding tie? - biccs r0,r0,#1 @ force to even if we rounded up - cmp r2,#0xfe - it lo - bxlo r14 - b 3b - -@ convert signed 32-bit fix to float, rounding; number of r0 bits after point in r1 -.thumb_func -regular_func fix2float - cmp r0,#0 - bge ufix2float @ positive? can use unsigned code - rsbs r0,#0 @ make positive -fix2float_neg: - clz r3,r0 - subs r3,#8 - bmi 2f - lsls r0,r3 - add r2,r1,r3 - rsb r2,#149 - add r0,r0,r2,lsl#23 @ insert exponent - orr r0,#0x80000000 - cmp r2,#0xfe - it lo @ over/underflow? - bxlo r14 - b 3f -2: - add r3,#33 - lsls r12,r0,r3 @ rounding bit in carry, sticky bits in r12 - rsb r3,#33 - lsr r0,r3 -@ push {r14} -@ bl dumpreg -@ pop {r14} - sub r2,r3,r1 - add r2,#22+127 - adc r0,r0,r2,lsl#23 @ insert exponent - orr r0,#0x80000000 - beq 4f @ potential rounding tie? - cmp r2,#0xfe - it lo - bxlo r14 -@ over/underflow? -3: - mov r0,#0x80000000 @ underflow - it ge - orrge r0,#0x7f800000 @ overflow -1: - bx r14 -4: - it cs @ rounding tie? - biccs r0,r0,#1 @ force to even if we rounded up - cmp r2,#0xfe - it lo - bxlo r14 - b 3b - -@ convert unsigned 32-bit fix to float, rounding; number of r0 bits after point in r1 -regular_func ufix2float - cbz r0,1f @ zero? return it - clz r3,r0 - subs r3,#8 - bmi 2f - lsls r0,r3 - add r2,r1,r3 - rsb r2,#149 - add r0,r0,r2,lsl#23 @ insert exponent -@ push {r14} -@ bl dumpreg -@ pop {r14} - cmp r2,#0xfe - it lo @ over/underflow? - bxlo r14 - b 3f -2: - add r3,#33 - lsls r12,r0,r3 @ rounding bit in carry, sticky bits in r12 - rsb r3,#33 - lsr r0,r3 -@ push {r14} -@ bl dumpreg -@ pop {r14} - sub r2,r3,r1 - add r2,#22+127 - adc r0,r0,r2,lsl#23 @ insert exponent - beq 4f @ potential rounding tie? - cmp r2,#0xfe - it lo - bxlo r14 -@ over/underflow? -3: - ite ge - movge r0,#0x7f800000 @ overflow - movlt r0,#0x00000000 @ underflow -1: - bx r14 -4: - it cs @ rounding tie? - biccs r0,r0,#1 @ force to even if we rounded up - cmp r2,#0xfe - it lo - bxlo r14 - b 3b - -@ convert uint64 to float, rounding -wrapper_func __aeabi_ul2f -regular_func uint642float - movs r2,#0 @ fall through -@ convert unsigned 64-bit fix to float, rounding; number of r0:r1 bits after point in r2 -regular_func ufix642float -10: - cbz r1,7f @ high word is zero? - clz r3,r1 - subs r3,#8 - bmi 2f - lsls r1,r3 - lsls r12,r0,r3 @ bits that will be lost - rsb r3,#32 - lsr r0,r3 - orr r0,r0,r1 - sub r2,r2,r3 - rsb r2,#149 - adds r12,r12,r12 @ rounding bit into carry - adc r0,r0,r2,lsl#23 @ insert exponent, add rounding - beq 4f @ potential rounding tie? - cmp r2,#0xfe - bhs 3f @ over/underflow? - bx r14 -2: - add r3,#33 - lsls r12,r1,r3 @ rounding bit in carry, sticky bits in r12 - orrs r12,r12,r0 @ all of low word into sticky bits: affects Z but not C - rsb r3,#33 - lsr r0,r1,r3 -@ push {r14} -@ bl dumpreg -@ pop {r14} - sub r2,r3,r2 - add r2,#22+127+32 - adc r0,r0,r2,lsl#23 @ insert exponent, add rounding - beq 4f @ potential rounding tie? - cmp r2,#0xfe - it lo - bxlo r14 -@ over/underflow? -3: - ite ge - movge r0,#0x7f800000 @ overflow - movlt r0,#0x00000000 @ underflow -1: - bx r14 -7: - mov r1,r2 - b ufix2float -4: - it cs @ rounding tie? - biccs r0,r0,#1 @ force to even if we rounded up - cmp r2,#0xfe - it lo - bxlo r14 - b 3b - -float_wrapper_section conv_ftoi64 - -@ convert float to signed int64, rounding towards 0, clamping -wrapper_func __aeabi_f2lz -regular_func float2int64_z - movs r1,#0 @ fall through -@ convert float in r0 to signed fixed point in r0:r1, clamping -regular_func float2fix64_z - subs r1,#0x95 @ remove exponent bias, compensate for mantissa length - asrs r2,r0,#23 @ sign and exponent - sub r3,r2,#1 - sub r0,r0,r3,lsl#23 @ install implied 1, clear exponent - uxtb r3,r3 - cmp r3,#0xfe - bhs 1f @ 0 or Inf/NaN? - adds r1,r3 @ offset exponent by fix precision; r1 is now required left shift - bmi 4f @ actually a right shift? - subs r3,r1,#32 @ result fits in high 32 bits only? - bge 8f - subs r3,r1,#8 @ result fits in low 32 bits only? - ble 7f - lsls r0,#8 - rsbs r1,r3,#32 - lsrs r1,r0,r1 - lsls r0,r3 - cmp r2,#0 - it ge - bxge r14 - rsbs r0,#0 @ negate if necessary - sbcs r1,r1,r1,lsl#1 - bx r14 -7: - lsls r0,r0,r1 - movs r1,r2,asr#31 @ sign extend - eors r0,r0,r1 @ negate if necessary - subs r0,r0,r1 - bx r14 -8: - cmp r3,#8 @ overflow? - bge 5f - lsls r0,r0,r3 - eor r1,r0,r2,asr#31 @ negate if necessary - add r1,r1,r2,lsr#31 - movs r0,#0 - bx r14 -1: - bhi 3f @ 0? - lsls r1,r0,#9 @ mantissa field - it ne @ NaN? - movne r2,#0 @ treat NaNs as +∞ -5: - mvn r1,#0x80000000 @ = 0x7fffffff - add r1,r1,r2,lsr#31 @ so -Inf → 0x80000000, +Inf → 0x7fffffff - mvn r0,r2,asr#31 - bx r14 -3: - movs r0,#0 - movs r1,#0 - bx r14 -4: - rsbs r1,#0 - usat r1,#5,r1 - lsrs r0,r0,r1 - eors r0,r0,r2,asr#31 @ negate if necessary - adds r0,r0,r2,lsr#31 - movs r1,r0,asr#31 @ sign extend - bx r14 - -float_wrapper_section conv_ftoui64 - -@ convert float to unsigned int64, rounding towards -Inf, clamping -wrapper_func __aeabi_f2ulz -regular_func float2uint64 -regular_func float2uint64_z - movs r1,#0 @ fall through -@ convert float in r0 to unsigned fixed point in r0:r1, clamping -regular_func float2ufix64 -//regular_func float2ufix64_z - subs r1,#0x96 @ remove exponent bias, compensate for mantissa length - asrs r2,r0,#23 @ sign and exponent - sub r3,r2,#1 - cmp r3,#0xfe - bhs 1f @ -ve, 0 or Inf/NaN? - sub r0,r0,r3,lsl#23 @ install implied 1, clear exponent - adds r1,r2 @ offset exponent by fix precision; r1 is now required left shift - bmi 4f @ actually a right shift? - subs r2,r1,#7 - ble 7f @ result (easily) fits in lo 32 bits? - subs r3,r1,#32 - bge 8f @ results might fit in hi 32 bits? - lsls r0,r0,#7 - rsbs r3,r2,#32 - lsrs r1,r0,r3 - lsls r0,r0,r2 - bx r14 -7: - lsls r0,r1 - movs r1,#0 - bx r14 -8: - cmp r1,#32+9 @ overflow? - bge 5f - lsls r1,r0,r3 - movs r0,#0 - bx r14 -5: - mvn r0,#0 @ = 0xffffffff - mvn r1,#0 @ = 0xffffffff - bx r14 -4: - rsbs r1,#0 - usat r1,#5,r1 @ if shift is long return 0 - lsrs r0,r0,r1 - movs r1,#0 - bx r14 -1: - cmp r0,#0xff800000 - bhi 5b @ -NaN, return 0xffffffff - cmp r0,#0x00800000 - bgt 5b @ +Inf or +NaN, return 0xfffffff -2: - movs r0,#0 @ return 0 - movs r1,#0 - bx r14 - -#endif diff --git a/lib/main/pico-sdk/rp2_common/pico_float/float_init_rom_rp2040.c b/lib/main/pico-sdk/rp2_common/pico_float/float_init_rom_rp2040.c deleted file mode 100644 index 062bfe707e..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_float/float_init_rom_rp2040.c +++ /dev/null @@ -1,70 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include "pico/bootrom.h" -#include "pico/bootrom/sf_table.h" - -// NOTE THIS FUNCTION TABLE IS NOT PUBLIC OR NECESSARILY COMPLETE... -// IT IS ***NOT*** SAFE TO CALL THESE FUNCTION POINTERS FROM ARBITRARY CODE -uint32_t sf_table[SF_TABLE_V2_SIZE / 2]; -void __attribute__((weak)) *sf_clz_func; - -#if !(PICO_FLOAT_SUPPORT_ROM_V1 && PICO_RP2040_B0_SUPPORTED) -static __attribute__((noreturn)) void missing_float_func_shim(void) { - panic(""); -} -#endif - -void __aeabi_float_init(void) { - int rom_version = rp2040_rom_version(); - void *rom_table = rom_data_lookup(rom_table_code('S', 'F')); -#if PICO_FLOAT_SUPPORT_ROM_V1 && PICO_RP2040_B0_SUPPORTED - if (rom_version == 1) { - memcpy(&sf_table, rom_table, SF_TABLE_V1_SIZE); - extern void float_table_shim_on_use_helper(void); - // todo replace NDEBUG with a more exclusive assertion guard -#ifndef NDEBUG - if (*(uint16_t *)0x29ee != 0x0fc4 || // this is packx - *(uint16_t *)0x29c0 != 0x0dc2 || // this is upackx - *(uint16_t *)0x2b96 != 0xb5c0 || // this is cordic_vec - *(uint16_t *)0x2b18 != 0x2500 || // this is packretns - *(uint16_t *)0x2acc != 0xb510 || // this is float2fix - *(uint32_t *)0x2cfc != 0x6487ed51 // pi_q29 - ) { - panic(""); - } -#endif - - // this is a little tricky.. we only want to pull in a shim if the corresponding function - // is called. to that end we include a SVC instruction with the table offset as the call number - // followed by the shim function pointer inside the actual wrapper function. that way if the wrapper - // function is garbage collected, so is the shim function. - // - // float_table_shim_on_use_helper expects this SVC instruction in the calling code soon after the address - // pointed to by IP and patches the float_table entry with the real shim the first time the function is called. - - for(uint i=SF_TABLE_V1_SIZE/4; i= 2) { - assert(*((uint8_t *)rom_table-2) * 4 >= SF_TABLE_V2_SIZE); - memcpy(&sf_table, rom_table, SF_TABLE_V2_SIZE); - } - sf_clz_func = rom_func_lookup(ROM_FUNC_CLZ32); -} diff --git a/lib/main/pico-sdk/rp2_common/pico_float/float_math.c b/lib/main/pico-sdk/rp2_common/pico_float/float_math.c deleted file mode 100644 index 93eb01dff1..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_float/float_math.c +++ /dev/null @@ -1,582 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "pico/float.h" - -// opened a separate issue https://github.com/raspberrypi/pico-sdk/issues/166 to deal with these warnings if at all -GCC_Pragma("GCC diagnostic push") -GCC_Pragma("GCC diagnostic ignored \"-Wconversion\"") -GCC_Pragma("GCC diagnostic ignored \"-Wsign-conversion\"") - -typedef uint32_t ui32; -typedef int32_t i32; - -#define FPINF ( HUGE_VALF) -#define FMINF (-HUGE_VALF) -#define NANF ((float)NAN) -#define PZERO (+0.0) -#define MZERO (-0.0) - -#define PI 3.14159265358979323846 -#define LOG2 0.69314718055994530941 -// Unfortunately in double precision ln(10) is very close to half-way between to representable numbers -#define LOG10 2.30258509299404568401 -#define LOG2E 1.44269504088896340737 -#define LOG10E 0.43429448190325182765 -#define ONETHIRD 0.33333333333333333333 - -#define PIf 3.14159265358979323846f -#define LOG2f 0.69314718055994530941f -#define LOG2Ef 1.44269504088896340737f -#define LOG10Ef 0.43429448190325182765f -#define ONETHIRDf 0.33333333333333333333f - -#define FUNPACK(x,e,m) e=((x)>>23)&0xff,m=((x)&0x007fffff)|0x00800000 -#define FUNPACKS(x,s,e,m) s=((x)>>31),FUNPACK((x),(e),(m)) - -typedef union { - float f; - ui32 ix; -} float_ui32; - -static inline float ui322float(ui32 ix) { - float_ui32 tmp; - tmp.ix = ix; - return tmp.f; -} - -static inline ui32 float2ui32(float f) { - float_ui32 tmp; - tmp.f = f; - return tmp.ix; -} - -#if PICO_FLOAT_PROPAGATE_NANS -static inline bool fisnan(float x) { - ui32 ix=float2ui32(x); - return ix * 2 > 0xff000000u; -} - -#define check_nan_f1(x) if (fisnan((x))) return (x) -#define check_nan_f2(x,y) if (fisnan((x))) return (x); else if (fisnan((y))) return (y); -#else -#define check_nan_f1(x) ((void)0) -#define check_nan_f2(x,y) ((void)0) -#endif - -static inline int fgetsignexp(float x) { - ui32 ix=float2ui32(x); - return (ix>>23)&0x1ff; -} - -static inline int fgetexp(float x) { - ui32 ix=float2ui32(x); - return (ix>>23)&0xff; -} - -static inline float fldexp(float x,int de) { - ui32 ix=float2ui32(x),iy; - int e; - e=fgetexp(x); - if(e==0||e==0xff) return x; - e+=de; - if(e<=0) iy=ix&0x80000000; // signed zero for underflow - else if(e>=0xff) iy=(ix&0x80000000)|0x7f800000ULL; // signed infinity on overflow - else iy=ix+((ui32)de<<23); - return ui322float(iy); -} - -float WRAPPER_FUNC(ldexpf)(float x, int de) { - check_nan_f1(x); - return fldexp(x, de); -} - -static inline float fcopysign(float x,float y) { - ui32 ix=float2ui32(x),iy=float2ui32(y); - ix=((ix&0x7fffffff)|(iy&0x80000000)); - return ui322float(ix); -} - -float WRAPPER_FUNC(copysignf)(float x, float y) { - check_nan_f2(x,y); - return fcopysign(x, y); -} - -static inline int fiszero(float x) { return fgetexp (x)==0; } -//static inline int fispzero(float x) { return fgetsignexp(x)==0; } -//static inline int fismzero(float x) { return fgetsignexp(x)==0x100; } -static inline int fisinf(float x) { return fgetexp (x)==0xff; } -static inline int fispinf(float x) { return fgetsignexp(x)==0xff; } -static inline int fisminf(float x) { return fgetsignexp(x)==0x1ff; } - -static inline int fisint(float x) { - ui32 ix=float2ui32(x),m; - int e=fgetexp(x); - if(e==0) return 1; // 0 is an integer - e-=0x7f; // remove exponent bias - if(e<0) return 0; // |x|<1 - e=23-e; // bit position in mantissa with significance 1 - if(e<=0) return 1; // |x| large, so must be an integer - m=(1<>e)&1; -} - -static inline int fisstrictneg(float x) { - ui32 ix=float2ui32(x); - if(fiszero(x)) return 0; - return ix>>31; -} - -static inline int fisneg(float x) { - ui32 ix=float2ui32(x); - return ix>>31; -} - -static inline float fneg(float x) { - ui32 ix=float2ui32(x); - ix^=0x80000000; - return ui322float(ix); -} - -static inline int fispo2(float x) { - ui32 ix=float2ui32(x); - if(fiszero(x)) return 0; - if(fisinf(x)) return 0; - ix&=0x007fffff; - return ix==0; -} - -static inline float fnan_or(float x) { -#if PICO_FLOAT_PROPAGATE_NANS - return NANF; -#else - return x; -#endif -} - -float WRAPPER_FUNC(truncf)(float x) { - check_nan_f1(x); - ui32 ix=float2ui32(x),m; - int e=fgetexp(x); - e-=0x7f; // remove exponent bias - if(e<0) { // |x|<1 - ix&=0x80000000; - return ui322float(ix); - } - e=23-e; // bit position in mantissa with significance 1 - if(e<=0) return x; // |x| large, so must be an integer - m=(1<=4+0x7f) { // |x|>=16? - if(!fisneg(x)) return 1; // 1 << exp 2x; avoid generating infinities later - else return -1; // 1 >> exp 2x - } - u=expf(fldexp(x,1)); - return (u-1.0f)/(u+1.0f); -} - -float WRAPPER_FUNC(asinhf)(float x) { - check_nan_f1(x); - int e; - e=fgetexp(x); - if(e>=16+0x7f) { // |x|>=2^16? - if(!fisneg(x)) return logf( x )+LOG2f; // 1/x^2 << 1 - else return fneg(logf(fneg(x))+LOG2f); // 1/x^2 << 1 - } - if(x>0) return (float)log(sqrt((double)x*(double)x+1.0)+(double)x); - else return fneg((float)log(sqrt((double)x*(double)x+1.0)-(double)x)); -} - -float WRAPPER_FUNC(acoshf)(float x) { - check_nan_f1(x); - int e; - if(fisneg(x)) x=fneg(x); - e=fgetexp(x); - if(e>=16+0x7f) return logf(x)+LOG2f; // |x|>=2^16? - return (float)log(sqrt(((double)x+1.0)*((double)x-1.0))+(double)x); -} - -float WRAPPER_FUNC(atanhf)(float x) { - check_nan_f1(x); - return fldexp(logf((1.0f+x)/(1.0f-x)),-1); -} - -float WRAPPER_FUNC(exp2f)(float x) { check_nan_f1(x); return (float)exp((double)x*LOG2); } -float WRAPPER_FUNC(log2f)(float x) { check_nan_f1(x); return logf(x)*LOG2Ef; } -float WRAPPER_FUNC(exp10f)(float x) { check_nan_f1(x); return (float)exp((double)x*LOG10); } -float WRAPPER_FUNC(log10f)(float x) { check_nan_f1(x); return logf(x)*LOG10Ef; } - -float WRAPPER_FUNC(expm1f)(float x) { check_nan_f1(x); return (float)(exp((double)x)-1); } -float WRAPPER_FUNC(log1pf)(float x) { check_nan_f1(x); return (float)(log(1+(double)x)); } -float WRAPPER_FUNC(fmaf)(float x,float y,float z) { - check_nan_f2(x,y); - check_nan_f1(z); - return (float)((double)x*(double)y+(double)z); -} // has double rounding so not exact - -// general power, x>0 -static inline float fpow_1(float x,float y) { - return (float)exp(log((double)x)*(double)y); // using double-precision intermediates for better accuracy -} - -static float fpow_int2(float x,int y) { - float u; - if(y==1) return x; - u=fpow_int2(x,y/2); - u*=u; - if(y&1) u*=x; - return u; -} - -// for the case where x not zero or infinity, y small and not zero -static inline float fpowint_1(float x,int y) { - if(y<0) x=1.0f/x,y=-y; - return fpow_int2(x,y); -} - -// for the case where x not zero or infinity -static float fpowint_0(float x,int y) { - int e; - if(fisneg(x)) { - if(fisoddint(y)) return fneg(fpowint_0(fneg(x),y)); - else return fpowint_0(fneg(x),y); - } - if(fispo2(x)) { - e=fgetexp(x)-0x7f; - if(y>=256) y= 255; // avoid overflow - if(y<-256) y=-256; - y*=e; - return fldexp(1,y); - } - if(y==0) return 1; - if(y>=-32&&y<=32) return fpowint_1(x,y); - return fpow_1(x,y); -} - -float WRAPPER_FUNC(powintf)(float x,int y) { - GCC_Pragma("GCC diagnostic push") - GCC_Pragma("GCC diagnostic ignored \"-Wfloat-equal\"") - if(x==1.0f||y==0) return 1; - if(x==0.0f) { - if(y>0) { - if(y&1) return x; - else return 0; - } - if((y&1)) return fcopysign(FPINF,x); - return FPINF; - } - GCC_Pragma("GCC diagnostic pop") - check_nan_f1(x); - if(fispinf(x)) { - if(y<0) return 0; - else return FPINF; - } - if(fisminf(x)) { - if(y>0) { - if((y&1)) return FMINF; - else return FPINF; - } - if((y&1)) return MZERO; - else return PZERO; - } - return fpowint_0(x,y); -} - -// for the case where y is guaranteed a finite integer, x not zero or infinity -static float fpow_0(float x,float y) { - int e,p; - if(fisneg(x)) { - if(fisoddint(y)) return fneg(fpow_0(fneg(x),y)); - else return fpow_0(fneg(x),y); - } - p=(int)y; - if(fispo2(x)) { - e=fgetexp(x)-0x7f; - if(p>=256) p= 255; // avoid overflow - if(p<-256) p=-256; - p*=e; - return fldexp(1,p); - } - if(p==0) return 1; - if(p>=-32&&p<=32) return fpowint_1(x,p); - return fpow_1(x,y); -} - -float WRAPPER_FUNC(powf)(float x,float y) { - GCC_Like_Pragma("GCC diagnostic push") - GCC_Like_Pragma("GCC diagnostic ignored \"-Wfloat-equal\"") - if(x==1.0f||fiszero(y)) return 1; - check_nan_f2(x,y); - if(x==-1.0f&&fisinf(y)) return 1; - GCC_Like_Pragma("GCC diagnostic pop") - if(fiszero(x)) { - if(!fisneg(y)) { - if(fisoddint(y)) return x; - else return 0; - } - if(fisoddint(y)) return fcopysign(FPINF,x); - return FPINF; - } - if(fispinf(x)) { - if(fisneg(y)) return 0; - else return FPINF; - } - if(fisminf(x)) { - if(!fisneg(y)) { - if(fisoddint(y)) return FMINF; - else return FPINF; - } - if(fisoddint(y)) return MZERO; - else return PZERO; - } - if(fispinf(y)) { - if(fgetexp(x)<0x7f) return PZERO; - else return FPINF; - } - if(fisminf(y)) { - if(fgetexp(x)<0x7f) return FPINF; - else return PZERO; - } - if(fisint(y)) return fpow_0(x,y); - if(fisneg(x)) return FPINF; - return fpow_1(x,y); -} - -float WRAPPER_FUNC(hypotf)(float x,float y) { - check_nan_f2(x,y); - int ex,ey; - ex=fgetexp(x); ey=fgetexp(y); - if(ex>=0x7f+50||ey>=0x7f+50) { // overflow, or nearly so - x=fldexp(x,-70),y=fldexp(y,-70); - return fldexp(sqrtf(x*x+y*y), 70); - } - else if(ex<=0x7f-50&&ey<=0x7f-50) { // underflow, or nearly so - x=fldexp(x, 70),y=fldexp(y, 70); - return fldexp(sqrtf(x*x+y*y),-70); - } - return sqrtf(x*x+y*y); -} - -float WRAPPER_FUNC(cbrtf)(float x) { - check_nan_f1(x); - int e; - if(fisneg(x)) return fneg(cbrtf(fneg(x))); - if(fiszero(x)) return fcopysign(PZERO,x); - e=fgetexp(x)-0x7f; - e=(e*0x5555+0x8000)>>16; // ~e/3, rounded - x=fldexp(x,-e*3); - x=expf(logf(x)*ONETHIRDf); - return fldexp(x,e); -} - -// reduces mx*2^e modulo my, returning bottom bits of quotient at *pquo -// 2^23<=|mx|,my<2^24, e>=0; 0<=result0) { - r=0xffffffffU/(ui32)(my>>7); // reciprocal estimate Q16 - } - while(e>0) { - s=e; if(s>12) s=12; // gain up to 12 bits on each iteration - q=(mx>>9)*r; // Q30 - q=((q>>(29-s))+1)>>1; // Q(s), rounded - mx=(mx<=my) mx-=my,quo++; // when e==0 mx can be nearly as big as 2my - if(mx>=my) mx-=my,quo++; - if(mx<0) mx+=my,quo--; - if(mx<0) mx+=my,quo--; - if(pquo) *pquo=quo; - return mx; -} - -float WRAPPER_FUNC(fmodf)(float x,float y) { - check_nan_f2(x,y); - ui32 ix=float2ui32(x),iy=float2ui32(y); - int sx,ex,ey; - i32 mx,my; - FUNPACKS(ix,sx,ex,mx); - FUNPACK(iy,ey,my); - if(ex==0xff) { - return fnan_or(FPINF); - } - if(ey==0) return FPINF; - if(ex==0) { - if(!fisneg(x)) return PZERO; - return MZERO; - } - if(ex|y|/2 - mx-=my+my; - ey--; - q=1; - } else { // x<-|y|/2 - mx=my+my-mx; - ey--; - q=-1; - } - } - else { - if(sx) mx=-mx; - mx=frem_0(mx,my,ex-ey,&q); - if(mx+mx>my || (mx+mx==my&&(q&1)) ) { // |x|>|y|/2, or equality and an odd quotient? - mx-=my; - q++; - } - } - if(sy) q=-q; - if(quo) *quo=q; - return fix2float(mx,0x7f-ey+23); -} - -float WRAPPER_FUNC(dremf)(float x,float y) { check_nan_f2(x,y); return remquof(x,y,0); } - -float WRAPPER_FUNC(remainderf)(float x,float y) { check_nan_f2(x,y); return remquof(x,y,0); } - -GCC_Pragma("GCC diagnostic pop") // conversion \ No newline at end of file diff --git a/lib/main/pico-sdk/rp2_common/pico_float/float_none.S b/lib/main/pico-sdk/rp2_common/pico_float/float_none.S deleted file mode 100644 index ad0df2f9b6..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_float/float_none.S +++ /dev/null @@ -1,82 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "pico/asm_helper.S" -#include "pico/bootrom/sf_table.h" - -pico_default_asm_setup - -wrapper_func __aeabi_fadd -wrapper_func __aeabi_fdiv -wrapper_func __aeabi_fmul -wrapper_func __aeabi_frsub -wrapper_func __aeabi_fsub -wrapper_func __aeabi_cfcmpeq -wrapper_func __aeabi_cfrcmple -wrapper_func __aeabi_cfcmple -wrapper_func __aeabi_fcmpeq -wrapper_func __aeabi_fcmplt -wrapper_func __aeabi_fcmple -wrapper_func __aeabi_fcmpge -wrapper_func __aeabi_fcmpgt -wrapper_func __aeabi_fcmpun -wrapper_func __aeabi_i2f -wrapper_func __aeabi_l2f -wrapper_func __aeabi_ui2f -wrapper_func __aeabi_ul2f -wrapper_func __aeabi_f2iz -wrapper_func __aeabi_f2lz -wrapper_func __aeabi_f2uiz -wrapper_func __aeabi_f2ulz -wrapper_func __aeabi_f2d -wrapper_func sqrtf -wrapper_func cosf -wrapper_func sinf -wrapper_func tanf -wrapper_func atan2f -wrapper_func expf -wrapper_func logf -wrapper_func ldexpf -wrapper_func copysignf -wrapper_func truncf -wrapper_func floorf -wrapper_func ceilf -wrapper_func roundf -wrapper_func sincosf -wrapper_func asinf -wrapper_func acosf -wrapper_func atanf -wrapper_func sinhf -wrapper_func coshf -wrapper_func tanhf -wrapper_func asinhf -wrapper_func acoshf -wrapper_func atanhf -wrapper_func exp2f -wrapper_func log2f -wrapper_func exp10f -wrapper_func log10f -wrapper_func powf -wrapper_func powintf -wrapper_func hypotf -wrapper_func cbrtf -wrapper_func fmodf -wrapper_func dremf -wrapper_func remainderf -wrapper_func remquof -wrapper_func expm1f -wrapper_func log1pf -wrapper_func fmaf -#ifdef __riscv - la a0, str - j panic -#else - push {lr} // keep stack trace sane - ldr r0, =str - bl panic -#endif -str: - .asciz "float support is disabled" \ No newline at end of file diff --git a/lib/main/pico-sdk/rp2_common/pico_float/float_sci_m33.S b/lib/main/pico-sdk/rp2_common/pico_float/float_sci_m33.S deleted file mode 100644 index f4648a35d3..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_float/float_sci_m33.S +++ /dev/null @@ -1,801 +0,0 @@ -/* - * Copyright (c) 2024 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#if !PICO_RP2040 -#include "pico/asm_helper.S" - -pico_default_asm_setup - -.macro float_section name -#if PICO_FLOAT_IN_RAM -.section RAM_SECTION_NAME(\name), "ax" -#else -.section SECTION_NAME(\name), "ax" -#endif -.endm - -.macro float_wrapper_section func -float_section WRAPPER_FUNC_NAME(\func) -.endm - -.extern rtwopi -.extern logtab0 -.extern exptab0 -.extern exptab1 -.extern exptab2 -.extern trigtab - -@ load a 32-bit constant n into register rx -.macro movlong rx,n - movw \rx,#(\n)&0xffff - movt \rx,#((\n)>>16)&0xffff -.endm - -float_section frrcore - -@ input: -@ r0 mantissa m Q23 -@ r1 exponent e>=-32, typically offset by +9 -@ output: -@ r0..r1 preserved -@ r6 range reduced result -@ r2,r3,r4,r5 trashed -frr_core: - ldr r2,=rtwopi - asrs r3,r1,#5 @ k=e/32, k<=5 for e offsets up to 9+32 - add r2,r2,r3,lsl#2 @ p - and r3,r1,#31 @ s=e%32 - mov r4,#1 - lsls r4,r4,r3 @ 1< + Inf; -Inf -> +0 - orrne r0,r0,#0x00400000 - bx r14 - -23: - ands r12,r12,#1<<31 -22: - eors r0,r12,#1<<31 - subs r0,r0,r0,lsr#8 @ overflow: convert to +0 or +Inf - bx r14 - - - - -float_wrapper_section logf - -1: - movlong r0,0xff800000 @ return -Inf - bx r14 - -4: - lsls r1,r0,#9 - it ne - orrne r0,r0,#0x00400000 - bx r14 - -@ here result may be close to zero -5: - sub r1,r0,#0x3f800000 - bmi 7f - cmp r1,#0x8000 - bge 6f @ |ε|>~2^-8? -@ here ε positive - clz r12,r1 - sub r3,r12,#1 - b 8f - -7: - rsbs r2,r1,#0 - cmp r2,#0x8000 - bge 6f @ |ε|>~2^-8? -@ here ε negative -@ r1: x Q24 - clz r12,r2 - sub r3,r12,#2 -8: - sub r12,#10 - lsls r0,r1,r3 @ ε Q24+r3 - beq 10f @ ε=0? - smmulr r1,r0,r0 - asrs r1,r1,r12 - sub r0,r0,r1,asr#1 @ - ε²/2 - smmulr r1,r1,r0 - asrs r2,r1,r12 - movs r3,#0x55 - mul r2,r2,r3 - adds r0,r0,r2,asr#8 @ + ~ ε³/3 - rsb r1,r12,#117 - b 9f - -wrapper_func logf - lsls r3,r0,#1 - bcs 1b @ x<0? - lsrs r3,#24 - beq 1b @ x==0/denormal? - sub r12,r3,#0x7e - cmp r12,#0x81 @ +Inf/NaN? - beq 4b - push {r14} - cmp r12,#1 @ result will be near zero? - bls 5b -6: - movs r2,#1 - bfi r0,r2,#23,#9 @ set implied 1, clear exponent Q52 - - lsls r0,#8 - - lsrs r1,r0,#27 - ldr r2,=logtab0-16*8 - add r2,r2,r1,lsl#3 - ldmia r2,{r2-r3} - lsls r2,#26 - umlal r2,r0,r2,r0 - - mvn r1,r0,asr#24 - ldr r2,=exptab1+4 - ldr r2,[r2,r1,lsl#3] - add r3,r3,r2 - lsls r1,#24 - umlal r1,r0,r1,r0 - - ldr r2,=exptab2+4 - mvn r1,r0,asr#21 - ldr r2,[r2,r1,lsl#3] - lsls r1,#21 - orr r1,#0x00100000 - umlal r1,r0,r1,r0 - add r3,r3,r2 - -@ r0: ε Q32 -@ r3: log y - smmulr r1,r0,r0 @ ε² Q32 - sub r3,r0 - add r3,r3,r1,lsr#1 @ log u - ε + ε²/2 Q32 - movlong r2,0xb17218 @ ln2 Q24, but accurate to 2^-29 or so - cmp r12,#1 @ result will be near zero? - bls 2f - mul r2,r2,r12 - mov r1,#125 - add r3,#255 @ reduce systematic error - subs r0,r2,r3,lsr#8 -9: - bmi 1f - bl fpack_q -10: - pop {r15} - -2: - mov r1,#117 - bne 3f @ r12=0? -@ here r12=1 - movlong r2,0xb17217f8 - sub r0,r2,r3 - bl fpack_q - pop {r15} - -3: - mov r0,r3 - bl fpack_q - orrs r0,r0,#1<<31 - pop {r15} - -1: - rsbs r0,#0 - bl fpack_q - orrs r0,r0,#1<<31 - pop {r15} - - -float_wrapper_section atan2f - -@ fatan small reduced angle case -@ r0 y/x in IEEE format, 0..2^-8 -@ r2 e+6 <0 -@ r3 #1 -@ r6 flags -20: - rsbs r4,r2,#0 @ -e-6 = shift down of mantissa required to get to Q29 >0 - cmp r4,#7 @ -e-6 ≥ 7 [ e ≤ -13 ] - bge 1f @ very small reduced angle? atn θ ~ θ -@ do a power series - bfi r0,r3,#23,#9 @ fix up mantissa Q23-e - lsls r0,#7 @ Q30-e - smmulr r1,r0,r0 @ θ² Q60-2e-Q32=Q28-2e - lsrs r1,r4 @ Q28-2e + (e+6) = Q34-e - smmulr r1,r1,r0 @ θ³ Q34-e+Q30-e-Q32=Q32-2e - mov r3,#0x55555555 @ 1/3 Q32 - lsrs r1,r4 @ Q32-2e + e+6 = Q38-e - smmulr r1,r1,r3 @ θ³/3 Q38-e - sub r0,r0,r1,lsr#8 @ Q30-e - cmp r6,#4 @ at least one quadrant to add? - bhs 2f - add r1,r2,#113 - bl fpack_q - eors r0,r0,r6,lsl#31 @ fix sign - pop {r4-r6,r15} - -@ here reduced angle is < 2^-12 -1: - cmp r6,#4 - bhs 3f @ at least one quadrant to add? - eors r0,r0,r6,lsl#31 @ no: return y/x with the correct sign - pop {r4-r6,r15} - -3: - bfi r0,r3,#23,#9 @ fix up mantissa - lsrs r0,r4 @ Q29 - lsls r0,#1 @ Q30 - b 40f - -2: - lsrs r0,r4 @ Q30-e + e+6 = Q36 - lsrs r0,#6 @ Q30 - b 40f - -@ case where reduced (x',y') has x' infinite -71: - sbfx r4,r0,#23,#8 - movs r0,#0 - cmn r4,#1 @ y' also infinite? - bne 80f - mov r0,#0x3f800000 @ both infinite: pretend ∞/∞=1 - b 80f - -@ case where reduced (x',y') has y' zero -70: - ubfx r4,r1,#23,#8 - movs r0,#0 - cbnz r4,80f @ x' also zero? - tst r6,#4 - beq 80f @ already in quadrants 0/±2? then 0/0 result will be correct - tst r6,#2 - ite eq - addeq r6,#6 - subne r6,#6 @ fix up when in quadrants ±0 - b 80f - -90: - movs r0,r1 -91: - orrs r0,r0,#0x00400000 - pop {r4-r6,r15} - -wrapper_func atan2f - push {r4-r6,r14} - lsls r4,r1,#1 - cmp r4,#0xff000000 - bhi 90b @ y NaN? - lsls r4,r0,#1 - cmp r4,#0xff000000 - bhi 91b @ x NaN? - lsrs r6,r0,#31 @ b31..2: quadrant count; b1: sign to apply before addition; b0: sign to apply after addition - bic r0,#1<<31 -@ y now positive - movs r1,r1 - bpl 1f - -@ here y positive, x negative - adds r6,#10 - bic r1,r1,#1<<31 - cmp r1,r0 - bhi 4f @ |x| > y: 3rd octant -@ |x| < y: 2nd octant - subs r6,#6 - b 3f - -1: -@ here x and y positive - cmp r1,r0 - bhs 4f -@ x < y: 1st octant - adds r6,#6 -3: - movs r2,r1 @ exchange x and y - movs r1,r0 - movs r0,r2 -4: -@ here -@ r0 y' -@ r1 x' -@ where both x' and y' are positive, y'/x' < 1+δ, and the final result is -@ ± (Q.π/2 ± atn y/x) where 0≤Q≤2 is a quadrant count in r6b3..2, the inner negation -@ is given by r6b1 and the outer negation by r6b0. x' can be infinite, or both x' and -@ y' can be infinite, but not y' alone. - - sbfx r2,r1,#23,#8 - cmn r2,#1 - beq 71b @ x' infinite? - ubfx r2,r0,#23,#8 - cmp r2,#0 - beq 70b @ y' zero? - bl __aeabi_fdiv -80: - @ r0 y/x in IEEE format, 0..1 - lsr r2,r0,#23 @ exponent - movs r3,#1 - subs r2,#0x7f-6 - bmi 20b - bfi r0,r3,#23,#9 @ fix up mantissa - lsls r0,r2 - lsls r0,#2 -50: - -@ from here atan2(y,1) where 1 implied -@ r0 y Q31 0≤y<1+δ - - lsrs r2,r0,#16 - mul r3,r2,r2 @ y^2 - movw r4,#0x895c - muls r2,r2,r4 @ y*0x895c - movw r5,#0x1227 - lsrs r3,#14 - mls r2,r3,r5,r2 - subs r2,#0x330000 @ Chebyshev approximation to atn(y) - lsrs r2,#25 - ldr r3,=trigtab+4 - add r3,r3,r2,lsl#4 - ldmia r3,{r3-r5} -@ r0 y Q30 -@ r3 phi0 Q32 -@ r4 sphi0 Q31 -@ r5 cphi0 Q31 -@ r6 flags -@ x0= cphi0 + sphi0*y -@ y0=-sphi0 + cphi0*y - umull r12,r1,r0,r4 @ sphi0*y - umull r12,r2,r0,r5 @ cphi0*y - add r1,r1,r5,lsr#1 @ x0 Q30 - sub r2,r2,r4,lsr#1 @ y0 Q30 -11: -@ r1 x0 Q30 -@ r2 y0 Q30 -@ r3 phi0 Q32 -@ r6 flags - mov r0,#0xffffffff - lsrs r4,r1,#15 - udiv r12,r0,r4 @ rx0 Q17 - lsls r4,r2,#6 @ y0 Q36 - smmul r4,r4,r12 @ t2=y0*rx0 Q21 - lsls r5,r4,#11 @ t2 Q32 - smmlar r0,r5,r2,r1 - smmlsr r1,r5,r1,r2 -@ r0 x1 Q30 -@ r1 y1 Q30 -@ r3 phi0 -@ r4 r2 Q21 -@ r12 rx0 Q17 - mul r5,r4,r4 @ t2_2 Q42 - smull r2,r5,r4,r5 @ t2_3 Q63 - add r3,r3,r4,lsl#11 @ Q32 - lsls r5,#1 @ Q32 - mov r2,#0x55555555 @ 1/3 - smmlsr r3,r2,r5,r3 @ t2_3/3 - -@ r0 x1 Q30 -@ r1 y1 Q30 -@ r3 phi0+phi1 Q32 -@ r12 rx0 Q17 - mul r0,r1,r12 @ y1*rx0 Q30+Q17=Q47 - add r3,r3,r0,asr#15 -@ r3 phi0+phi1+phi2, result over reduced range Q32 -@ r6 flags - - lsrs r0,r3,#2 @ Q30 -@ adc r0,#0 @ rounding -40: - lsl r5,r6,#30 @ b1 -> b31 - eor r0,r0,r5,asr#31 @ negate if required - movlong r1,0x6487ED51 @ π/2 Q30 - - lsr r5,r6,#2 @ quadrants to add - mla r0,r5,r1,r0 - mov r1,#0x80-9 @ for packing Q30 -60: - bl fpack_q - eors r0,r0,r6,lsl#31 - pop {r4-r6,r15} - -@======================================= - -float_wrapper_section fpack - -@ fnegpack: negate and pack -@ fpack_q31: -@ input -@ r0 Q31 result, must not be zero -@ r1 exponent offset [fpack_q only] -@ output -@ r0 IEEE single -@ trashes (r1,)r2 -fnegpack_q31: - rsbs r0,r0,#0 -fpack_q31: - mov r1,#0x7f-9 @ exponent -fpack_q: - clz r2,r0 - rsbs r2,#8 - bmi 1f - lsrs r0,r0,r2 @ save rounding bit in carry - add r2,r2,r1 - adc r0,r0,r2,lsl#23 @ insert exponent - bx r14 - -1: - rsb r2,#0 - lsls r0,r0,r2 - sub r2,r1,r2 - add r0,r0,r2,lsl#23 - bx r14 - -float_wrapper_section tanf - -wrapper_func tanf - push {r14} - bl sincosf_raw - bl __aeabi_fdiv - pop {r15} - -float_wrapper_section fsin_fcos - -10: @ process Inf/NaN for sinf and fcos - lsls r1,r0,#9 - it eq - orreq r0,#0x80000000 - orr r0,#0x00400000 @ turn Inf into NaN - movs r1,r0 @ copy result to cosine output - bx r14 - -@ case where angle is very small (<2^-32) before reduction -32: - adds r1,r1,#0x7f - it eq - moveq r0,#0 @ flush denormal to zero - - movs r1,0x3f800000 @ return x for sine, 1 for cosine - tst r12,#2 - it ne - movne r0,r1 @ calculating cosine? move to result registers - bx r14 - -40: -@ case where range-reduced angle is very small -@ here -@ r0 mantissa -@ r1 exponent+9 -@ r6 abs range-reduced angle / 2π < 2^-7 Q32 -@ r12b31: dsincos flag -@ r12b30: original argument sign -@ r12b2..1: quadrant count -@ r12b0: sign of reduced angle - push {r12} - movs r12,#0 -2: - add r12,#2 - add r1,#2 - bl frr_core @ repeat range reduction with extra factor of 2^2 (, 2^4, 2^6, 2^8,...) - eors r4,r6,r6,asr#31 @ we want to keep the sign in r6b31 for later - cmp r4,#1<<26 @ ≥ 2^-6? - bhs 1f @ loop until the result is big enough - cmp r12,#32 @ safety net - bne 2b -1: -@ here r4 is the abs range-reduced angle Q32+r12, 2^-6..2^-4 in Q32 terms - -@ 2π=6.487ED511 (0B4611A6...) - movlong r5,0x487ED511 @ 2π Q64 high fractional word - umull r2,r0,r4,r5 - movs r5,#6 @ 2π integer part - mla r0,r4,r5,r0 - -@ here -@ r0 θ, abs range reduced angle θ 0..π/4 Q32+r12, 2π * 2^-6..2^-4 in Q32 terms (so top bit is clear) -@ r6b31: sign of reduced angle -@ r12: excess exponent ≥2, multiple of 2 -@ r0 / 2^r12 < ~ 2π * 2^-7 so for sin we need to go to term in x^3 - - smmulr r1,r0,r0 @ θ² Q32+2*r12 - lsrs r1,r1,r12 @ θ² Q32+r12 - lsrs r1,r1,r12 @ θ² Q32 - movs r4,#0x55555555 @ 1/3 Q32 - smmulr r4,r1,r4 @ θ²/3 Q32 - smmulr r2,r4,r1 @ θ⁴/3 Q32 - rsb r3,r1,r2,lsr#2 @ -θ²+θ⁴/12) Q32 - asrs r3,#9 @ -θ²/2+θ⁴/24 Q24 - adc r3,r3,#0x3f800000 @ IEEE single with rounding - - smmulr r2,r4,r0 @ θ³/3 Q32+r12 - sub r0,r0,r2,lsr#1 @ θ-θ³/6 Q32+r12 - rsb r1,r12,#117 - bl fpack_q -@ here -@ r0 packed sin -@ r3 packed cos -@ r6b31: sign of reduced angle - pop {r12} @ get flags - lsrs r6,#31 - bfi r12,r6,#0,#1 - - asrs r2,r12,#1 - bmi 23f @ doing sincos? - asrs r2,#1 - bcc 21f @ need sine? -@ need cosine: - ands r12,#4 - orrs r0,r3,r12,lsl#29 @ insert sign - pop {r4-r6,r15} - -21: - eors r12,r12,r12,lsr#2 - orrs r0,r0,r12,lsl#31 @ insert sign - pop {r4-r6,r15} - -23: - ands r2,r12,#4 - orrs r3,r3,r2,lsl#29 @ insert sign - push {r3} -@ drop into sincosf code below... - b 20f - -wrapper_func sincosf - push {r1, r2, lr} - bl sincosf_raw - pop {r2, r3} - str r0, [r2] - str r1, [r3] - pop {pc} - -sincosf_raw: - ands r12,r0,#1<<31 - lsrs r12,#1 @ save argument sign in r12b30 - orrs r12,r12,#1<<31 @ flag we want both results in r12b31 - b 1f - -wrapper_func sinf - lsrs r12,r0,#29 @ negative argument -> +2 quadrants - ands r12,#4 - b 1f - -wrapper_func cosf - movs r12,#2 @ cos -> +1 quadrant -1: - ubfx r1,r0,#23,#8 @ get exponent - sub r1,r1,#0x7f - cmp r1,#0x80 - beq 10b @ Inf or NaN? - cmn r1,#32 - blt 32b @ very small argument? - movs r3,#1 - bfi r0,r3,#23,#9 @ fix implied 1 in mantissa - push {r4-r6,r14} - add r1,#9 @ e+9 - bl frr_core -@ r6 θ/2π 0..1 Q64 - lsrs r4,r6,#30 @ quadrant count - adc r4,r4,#0 @ rounded - sub r6,r6,r4,lsl#30 @ now -0.125≤r6<+0.125 Q32 - add r12,r12,r4,lsl#1 - orr r12,r12,r6,lsr#31 @ sign into r12b0 -@ r12b2..1: quadrant count -@ r12b0: sign of reduced angle - eors r6,r6,r6,asr#31 @ absolute value of reduced angle 0≤r7<0.125 Q32 - cmp r6,#1<<25 @ θ / 2π < 2^-7? - blo 40b - -@ 2π=6.487ED511 (0B4611A6...) - movlong r5,0x487ED511 @ 2π Q64 high fractional word - umull r2,r0,r6,r5 - movs r5,#6 @ 2π integer part - mla r0,r6,r5,r0 -@ r0 range reduced angle θ 0..π/4 Q32 - lsrs r2,r0,#27 - ldr r3,=trigtab+4 - add r3,r3,r2,lsl#4 - ldmia r3,{r1-r3} - subs r0,r1 -@ r0: ε Q32 |ε| < 1.17*2^-6 -@ r2: sin φ Q31 -@ r3: cos φ Q31 - asrs r1,r12,#1 - bmi 5f @ doing sincosf? - asrs r1,#1 - bcs 3f @ need cosine? -@ here need sine - smmulr r1,r0,r0 @ ε² Q32 - mov r4,#0x55555555 @ 1/3 Q32 - asrs r1,#1 - smmlsr r2,r1,r2,r2 @ sin φ - ε²/2*sin φ ~ sin φ cos ε - smmulr r1,r1,r0 @ ε³/2 - smmlsr r1,r1,r4,r0 @ ε - ε³/6 - - smmlar r0,r1,r3,r2 @ sin φ cos ε + cos φ (ε - ε³/6) ~ sin (φ+ε) -@ the sign of the result is r12b0^r12b2 - bl fpack_q31 - eors r12,r12,r12,lsr#2 - orrs r0,r0,r12,lsl#31 @ insert sign - pop {r4-r6,r15} - -3: -@ here need cosine - smmulr r1,r0,r0 @ ε² Q32 - mov r4,#0x55555555 @ 1/3 Q32 - asrs r1,#1 - smmlsr r3,r1,r3,r3 @ cos φ - ε²/2*cos φ ~ cos φ cos ε - smmulr r1,r1,r0 @ ε³/2 - smmlsr r1,r1,r4,r0 @ ε - ε³/6 - - smmlsr r0,r1,r2,r3 @ cos φ cos ε - sin φ (ε - ε³/6) ~ cos (φ+ε) -@ the sign of the result is r12b2 - bl fpack_q31 - ands r12,#4 - orrs r0,r0,r12,lsl#29 @ insert sign - pop {r4-r6,r15} - -5: -@ here doing sincosf - smmulr r1,r0,r0 @ ε² Q32 - mov r6,#0x55555555 @ 1/3 Q32 - asrs r1,#1 - smmlsr r4,r1,r2,r2 @ sin φ - ε²/2*sin φ ~ sin φ cos ε - smmlsr r5,r1,r3,r3 @ cos φ - ε²/2*cos φ ~ cos φ cos ε - smmulr r1,r1,r0 @ ε³/2 - smmlsr r6,r1,r6,r0 @ ε - ε³/6 -@ here -@ r2 sin φ -@ r3 cos φ -@ r4 sin φ cos ε -@ r5 cos φ cos ε -@ r6 ε - ε³/6 ~ sin ε - smmlsr r0,r6,r2,r5 @ cos φ cos ε - sin φ (ε - ε³/6) ~ cos (φ+ε) - bl fpack_q31 - ands r5,r12,#4 - eors r0,r0,r5,lsl#29 @ negate cosine in quadrants 2 and 3 - push {r0} - smmlar r0,r6,r3,r4 @ sin φ cos ε + cos φ (ε - ε³/6) ~ sin (φ+ε) - bl fpack_q31 -20: - eors r4,r12,r12,lsr#1 - eors r4,r4,r12,lsr#2 - ands r5,r12,#1<<30 - tst r12,#2 @ exchange sine and cosine in odd quadrants - beq 1f - eors r1,r0,r4,lsl#31 @ negate sine on b0^b1^b2 - pop {r0} - eors r0,r0,r5,lsl#1 @ negate sine result if argument was negative - pop {r4-r6,r15} -1: - pop {r1} - eors r0,r0,r4,lsl#31 @ negate sine on b0^b1^b2 - eors r0,r0,r5,lsl#1 @ negate sine result if argument was negative - pop {r4-r6,r15} - -#endif diff --git a/lib/main/pico-sdk/rp2_common/pico_float/float_sci_m33_vfp.S b/lib/main/pico-sdk/rp2_common/pico_float/float_sci_m33_vfp.S deleted file mode 100644 index 86e8b27500..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_float/float_sci_m33_vfp.S +++ /dev/null @@ -1,856 +0,0 @@ -/* - * Copyright (c) 2024 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#if !PICO_RP2040 -#include "pico/asm_helper.S" - -pico_default_asm_setup - -.macro float_section name -#if PICO_FLOAT_IN_RAM -.section RAM_SECTION_NAME(\name), "ax" -#else -.section SECTION_NAME(\name), "ax" -#endif -.endm - -.macro float_wrapper_section func -float_section WRAPPER_FUNC_NAME(\func) -.endm - -@ load a 32-bit constant n into register rx -.macro movlong rx,n - movw \rx,#(\n)&0xffff - movt \rx,#((\n)>>16)&0xffff -.endm - -float_section frrcore_v - -// 1/2π to plenty of accuracy -.long 0 @ this allows values of e down to -32 -rtwopi: -.long 0,0 -.long 0x28BE60DB, 0x9391054A, 0x7F09D5F4, 0x7D4D3770, 0x36D8A566, 0x4F10E410 - -@ input: -@ r0 mantissa m Q23 -@ r1 exponent e>=-32, typically offset by +9 -@ output: -@ r0..r1 preserved -@ r6 range reduced result in revolutions Q32 -@ r2,r3,r4,r5 trashed -.thumb_func -frr_core: - adr r2,rtwopi - asrs r3,r1,#5 @ k=e/32, k<=5 for e offsets up to 9+32 - add r2,r2,r3,lsl#2 @ p - and r3,r1,#31 @ s=e%32 - mov r4,#1 - lsls r4,r4,r3 @ 1<>19 rounded, preserving flags - bic r3,#7 - - ldrd r2,r3,[r3] - mul r0,r0,r2 @ ε - vmov s0,s1,r3,r0 @ s0=-log u, s1=ε - - vcvt.f32.s32 s1,s1,#32 - vmul.f32 s2,s1,s1 @ power series in ε - sbc r1,r1,#0x7e @ ... and here - vmul.f32 s3,s1,s2 - lsls r1,#23 @ e Q23 - vmul.f32 s4,s2,s2 @ to ε⁴ -@ movlong r2,0x58b90bfc @ log 2 Q31, more accurate than we deserve - movw r2,0x0bfc - vmul.f32 s2,s2,s8 - movt r2,0x58b9 - vmul.f32 s3,s3,s9 - smmulr r1,r1,r2 @ Q22 - vmul.f32 s4,s4,s10 - vmov s7,r1 - vsub.f32 s3,s3,s4 - vcvt.f32.s32 s7,s7,#22 - vsub.f32 s2,s2,s3 - vsub.f32 s1,s1,s2 - vadd.f32 s0,s0,s1 @ log ε - log u - vadd.f32 s0,s0,s7 @ e log 2 + log ε - log u - vmov r0,s0 - bx r14 - -1: - bgt 3f @ +NaN? - beq 10f @ +Inf? -2: - cmp r0,#0x80800000 @ -0? - blo 11f - cmp r0,#0xff800000 @ -NaN/-Inf? -3: - orr r0,#0x00400000 - bhi 10f - movlong r0,0xffc00000 -10: - bx r14 -11: - movlong r0,0xff800000 - bx r14 - -.align 3 -k_log3: -.float 0.5 -.float 0.333333333333333 -.float 0.25 -.float 0 @ alignment - -logtab3: -@ u=64/[48:2:96]; u Q8, -log u F32 -.word 0x0155,0xbe92cb01 @ 00003e9b..00004145 -.word 0x0148,0xbe7dc8c3 @ 00003ec8..00004158 -.word 0x013b,0xbe545f68 @ 00003ec1..00004137 -.word 0x012f,0xbe2c99c7 @ 00003ebb..00004119 -.word 0x0125,0xbe0a3c2c @ 00003ef3..0000413d -.word 0x011a,0xbdc61a2f @ 00003eca..000040fe -.word 0x0111,0xbd83acc2 @ 00003eeb..0000410d -.word 0x0108,0xbcfc14d8 @ 00003ee8..000040f8 -.word 0x0100,0x00000000 @ 00003f00..00004100 -.word 0x00f8,0x3d020aec @ 00003ef8..000040e8 -.word 0x00f1,0x3d77518e @ 00003f13..000040f5 -.word 0x00ea,0x3db80698 @ 00003f12..000040e6 -.word 0x00e4,0x3ded393b @ 00003f3c..00004104 -.word 0x00dd,0x3e168b08 @ 00003f05..000040bf -.word 0x00d8,0x3e2dfa03 @ 00003f48..000040f8 -.word 0x00d2,0x3e4ad2d7 @ 00003f2a..000040ce -.word 0x00cd,0x3e637fde @ 00003f43..000040dd -.word 0x00c8,0x3e7cc8e3 @ 00003f48..000040d8 -.word 0x00c3,0x3e8b5ae6 @ 00003f39..000040bf -.word 0x00bf,0x3e95f784 @ 00003f6b..000040e9 -.word 0x00ba,0x3ea38c6e @ 00003f36..000040aa -.word 0x00b6,0x3eaeadef @ 00003f46..000040b2 -.word 0x00b2,0x3eba0ec4 @ 00003f46..000040aa -.word 0x00ae,0x3ec5b1cd @ 00003f36..00004092 -.word 0x00ab,0x3ece995f @ 00003f75..000040cb - -float_wrapper_section fsin_fcos - -30: - lsls r1,r0,#9 - bne 1f @ NaN? return it - orrs r0,r0,#0x80000000 @ Inf: make a NaN -1: - orrs r0,r0,#0x00400000 @ set top mantissa bit of NaN - bx r14 - -@ heavy-duty range reduction -@ here x≥256, -e in r1 -40: - push {r4-r7,r14} - movs r3,#1 - bfi r0,r3,#23,#9 @ insert implied 1 in mantissa, clear sign - rsb r1,#9 @ e+9 - mov r7,#0x7e @ this will be the exponent of the reduced angle - 1 -42: - bl frr_core -@ here r6 is revolutions Q32 - lsrs r3,r6,#30 @ quadrant count - adcs r3,r3,#0 @ rounded - add r12,r12,r3 - subs r6,r6,r3,lsl#30 @ reduced angle/2π Q32 -.125≤x<+.125 -@ comment out from here... - lsls r2,r6,#2 @ Q34 - it cs - rsbcs r2,r2,#0 @ absolute value - cmp r2,#1<<28 @ big enough for accuracy? - bhs 41f -@ ... to here for slightly better accuracy -43: - adds r1,r1,#2 @ try again with increased exponent - bl frr_core - eors r2,r6,r6,asr#32 @ absolute value - adc r2,r2,#0 - cmp r2,#1<<28 @ big enough yet? - bhs 44f - subs r7,r7,#2 - bpl 43b @ safety net -44: - -41: - ldr r4,=0xC90FDAA2 @ 2π Q29 - umull r2,r4,r2,r4 @ r4 has reduced angle Q34+Q29-Q32=Q31 -@ add r4,r4,r2,lsr#31 - clz r2,r4 @ normalise - lsls r4,r4,r2 - lsrs r4,r4,#8 - sub r2,r7,r2 - adc r0,r4,r2,lsl#23 @ with rounding - lsrs r1,r0,#23 @ re-extract exponent as there may have been a carry into it - rsbs r1,r1,#0x7f @ prepare exponent for re-entry - lsrs r6,r6,#31 - add r3,r0,r6,lsl#31 @ apply sign of reduced angle - pop {r4-r7,r14} - b 5f @ re-enter with no risk of looping - -.ltorg - -@ light-duty range reduction -@ here argument ≥1 -@ r0: argument -@ r1: -e -@ r12: quadrant count -@ required result is sin(r0+r12*π/2) -10: - cmn r1,#0x80 - beq 30b @ Inf/NaN - bics r2,r0,r12,lsl#31 @ negative argument,doing sin -> +2 quadrants - it mi - addmi r12,r12,#2 - bic r0,r0,#0x80000000 @ make positive: original sign is now captured in quadrant count in r12 - -@ this may not actually be faster than doing it in integer registers - vmov s0,r0 - adr r2,k_sc4 - vldmia r2!,{s5-s7} -@ vmul.f32 s4,s4,s0 @ this accurate calculation of the quadrant count does not seem necessary -@ vfma.f32 s4,s5,s0 - vmul.f32 s4,s5,s0 @ this is BALGE - cmn r1,#8 @ ≥256? - vrintn.f32.f32 s4,s4 @ round to quadrant count: x<256 so count≤163 - ble 40b @ then do heavy-duty range reduction - vfms.f32 s0,s4,s7 - vfms.f32 s0,s4,s6 - vmov r3,s0 @ reduced angle - vcvt.s32.f32 s3,s4 - ubfx r2,r3,#23,#8 @ get exponent - cmp r2,#0x78 - blo 40b @ very small result? use heavy-duty reduction to get a more accurate answer - rsbs r1,r2,#0x7f @ ready for re-entry - vmov r2,s3 @ integer quadrant count - add r12,r12,r2 -@ prepare to re-enter with no risk of looping - b 5f - -k_sc4: -@ 2/π=0.A2F9836E4E441529FC... -.word 0x3f22f983 @ 2/π -@ π/2=1.921FB54442D1846989... -.word 0xb695777a,0x3fc91000 @ these two add up to π/2 with error ~1.6e-13 - -wrapper_func sincosf - - push {r0-r2,r14} - ubfx r1,r0,#23,#8 - cmp r1,#0xff @ Inf/NaN? - beq 2f - bl cosf_entry @ this will exit via 1f or 2f... - pop {r1-r2,r14} - str r0,[r14] -@ here C is still set from lsrs r12,r12,#1 - bcs 1f - mvns r1,r1 - eor r12,r12,r1,lsr#31 -@ this is fsc_costail: -@ here calculate cos φ+ε = cosθ - vmul.f32 s5,s7,s1 @ sinφ sinε - vfma.f32 s5,s2,s6 @ sinφ sinε + cosφ(1-cosε) - vsub.f32 s5,s6,s5 @ cosφ - (sinφ sinε + cosφ(1-cosε)) = cosφ cosε - sinφ sinε - vmov.f32 r0,s5 - eor r0,r0,r12,lsl#31 - str r0,[r2] - pop {r15} - -1: - eor r12,r12,r1,lsr#31 -@ this is fsc_sintail: -@ here calculate sin φ+ε = sinθ - vmul.f32 s4,s2,s7 @ sinφ(1-cosε) - vfms.f32 s4,s6,s1 @ sinφ(1-cosε) - cosφ sinε - eor r1,r12,r3,lsr#31 @ flip sign if (reduced) argument was negative - vsub.f32 s4,s7,s4 @ cosφ sinε + sinφ cosε - vmov.f32 r0,s4 - eor r0,r0,r1,lsl#31 - str r0,[r2] @ save cos result - pop {r15} - -@ sincos of Inf or NaN -2: - lsls r1,r0,#9 - pop {r1-r3,r14} - bne 1f @ NaN? return it - orrs r0,r0,#0x80000000 @ Inf: make a NaN -1: - orrs r0,r0,#0x00400000 @ set top mantissa bit of NaN - str r0,[r2] @ both sin and cos results - str r0,[r3] - bx r14 - -wrapper_func sinf -@ r12b1..0: quadrant count - movs r12,#0 - b 1f - -wrapper_func cosf -.thumb_func -cosf_entry: - movs r12,#1 @ cos -> +1 quadrant -1: - ubfx r1,r0,#23,#8 @ get exponent - cbz r1,20f @ 0/denormal? -22: - rsbs r1,r1,#0x7f - bls 10b @ argument ≥1? needs reduction; also Inf/NaN handling - bic r3,r0,r12,lsl#31 @ this would mess up NaNs so do it here -5: -@ here we have a quadrant count in r12 and a signed offset r0 from r12*π/2 - bic r0,r3,#0x80000000 @ this would mess up NaNs so do it here - vmov s0,r0 - ubfx r0,r0,#18,#5 @ extract top of mantissa - adds r0,r0,#32 @ insert implied 1 - lsrs r1,r0,r1 @ to fixed point Q5 - ldr r2,=k_sc3 - adcs r1,r1,#0 @ rounding - vldmia r2!,{s8-s9} - add r2,r2,r1,lsl#2 @ 12 bytes per entry - add r2,r2,r1,lsl#3 - - vldmia r2,{s5-s7} @ φ, cosφ, sinφ - vsub.f32 s1,s0,s5 @ ε - vmul.f32 s2,s1,s1 @ ε² - lsrs r12,r12,#1 @ computing cosine? - vmul.f32 s3,s2,s1 @ ε³ - bcs 2f - - vmul.f32 s2,s2,s8 @ ε²/2! ~ 1-cosε - vmul.f32 s3,s3,s9 @ ε³/3! - vsub.f32 s1,s1,s3 @ ε-ε³/3! ~ sinε - -@ here: -@ s1: sinε -@ s2: 1-cosε -@ s6: cosφ -@ s7: sinφ -@ r12: quadrant count -fsc_sintail: -@ here calculate sin φ+ε = sinθ - vmul.f32 s4,s2,s7 @ sinφ(1-cosε) - vfms.f32 s4,s6,s1 @ sinφ(1-cosε) - cosφ sinε - eor r1,r12,r3,lsr#31 @ flip sign if (reduced) argument was negative - vsub.f32 s4,s7,s4 @ cosφ sinε + sinφ cosε - vmov.f32 r0,s4 - eor r0,r0,r1,lsl#31 - bx r14 - -20: - and r0,r0,#0x80000000 @ make signed zero - b 22b - -.align 2 -2: - vmul.f32 s3,s3,s9 @ ε³/3! - vsub.f32 s1,s1,s3 @ ε-ε³/3! ~ sinε - vmul.f32 s2,s2,s8 @ ε²/2! ~ 1-cosε -fsc_costail: -@ here calculate cos φ+ε = cosθ - vmul.f32 s5,s7,s1 @ sinφ sinε - vfma.f32 s5,s2,s6 @ sinφ sinε + cosφ(1-cosε) - vsub.f32 s5,s6,s5 @ cosφ - (sinφ sinε + cosφ(1-cosε)) = cosφ cosε - sinφ sinε - vmov.f32 r0,s5 - eor r0,r0,r12,lsl#31 - bx r14 - -.align 3 -k_sc3: -.word 0x3EFFFEC1 @ ~ 1/2! with PMC -.word 0x3e2aaa25 @ ~ 1/3! with PMC - -trigtab2: -// φ cos φ sin φ -.word 0x00000000,0x3f800000,0x00000000 -.word 0x3cfcc961,0x3f7fe0cd,0x3cfcbf1c @ φ=0.03085774 : cos φ=3feffc199ff28ef4 33.3b; sin φ=3f9f97e38006c678 39.2b -.word 0x3d810576,0x3f7f7dfe,0x3d80ef9e @ φ=0.06299870 : cos φ=3fefefbfc00d6b6d 33.3b; sin φ=3fb01df3c000dfd5 40.2b -.word 0x3dbf0c09,0x3f7ee30f,0x3dbec522 @ φ=0.09328467 : cos φ=3fefdc61dff4f58e 33.5b; sin φ=3fb7d8a43ffdf9ac 39.0b -.word 0x3dff24b6,0x3f7e0414,0x3dfe7be2 @ φ=0.12458174 : cos φ=3fefc0827fdaf90f 31.8b; sin φ=3fbfcf7c3ff9dd0c 37.4b -.word 0x3e1f0713,0x3f7ceb48,0x3e1e63a0 @ φ=0.15530042 : cos φ=3fef9d68ffe680a0 32.3b; sin φ=3fc3cc73fffa6d09 36.5b -.word 0x3e40306d,0x3f7b811d,0x3e3f1015 @ φ=0.18768473 : cos φ=3fef70239fe32301 32.1b; sin φ=3fc7e2029ffdbc2c 37.8b -.word 0x3e60ada2,0x3f79dccf,0x3e5ee13e @ φ=0.21941236 : cos φ=3fef3b99e023f5aa 31.8b; sin φ=3fcbdc27bffe216d 38.1b -.word 0x3e800d7b,0x3f7808fa,0x3e7d7196 @ φ=0.25010285 : cos φ=3fef011f401572a6 32.6b; sin φ=3fcfae32c00328bb 37.3b -.word 0x3e8f986e,0x3f75ff65,0x3e8db868 @ φ=0.28045982 : cos φ=3feebfeca0aaaf99 29.6b; sin φ=3fd1b70cfffc1468 36.0b -.word 0x3e9fe1f4,0x3f739e93,0x3e9d4bfd @ φ=0.31227076 : cos φ=3fee73d25fbf733b 31.0b; sin φ=3fd3a97fa0002ced 40.5b -.word 0x3eb054c6,0x3f70f7ae,0x3eacddb3 @ φ=0.34439677 : cos φ=3fee1ef5bfcf70cb 31.4b; sin φ=3fd59bb65fff5c30 38.6b -.word 0x3ebf89c5,0x3f6e4b60,0x3ebb1a0a @ φ=0.37409797 : cos φ=3fedc96bffdebb8a 31.9b; sin φ=3fd763414003344b 36.3b -.word 0x3ecfc426,0x3f6b35ca,0x3eca1c63 @ φ=0.40579337 : cos φ=3fed66b93fe27dc6 32.1b; sin φ=3fd9438c5ffe5d45 37.3b -.word 0x3ee054f2,0x3f67d166,0x3ed93907 @ φ=0.43814808 : cos φ=3fecfa2cbffc16e9 35.0b; sin φ=3fdb2720dffef5b6 37.9b -.word 0x3eeff0dd,0x3f64664b,0x3ee74116 @ φ=0.46863452 : cos φ=3fec8cc95f714272 29.8b; sin φ=3fdce822c00479ad 35.8b -.word 0x3f002b31,0x3f609488,0x3ef5c30f @ φ=0.50065905 : cos φ=3fec1290ffc99208 31.2b; sin φ=3fdeb861dfff3932 38.4b -.word 0x3f07e407,0x3f5cc5a2,0x3f01992b @ φ=0.53082317 : cos φ=3feb98b44034cd46 31.3b; sin φ=3fe033255ffff628 41.7b -.word 0x3f101fc5,0x3f587d8f,0x3f08a165 @ φ=0.56298476 : cos φ=3feb0fb1e0ceda6f 29.3b; sin φ=3fe1142c9ffd5ae4 35.6b -.word 0x3f17f68a,0x3f5434b5,0x3f0f31ca @ φ=0.59360564 : cos φ=3fea8696a038a06f 31.2b; sin φ=3fe1e639400269fb 35.7b -.word 0x3f1fffe2,0x3f4f9b59,0x3f15c8d7 @ φ=0.62499821 : cos φ=3fe9f36b1f428363 29.4b; sin φ=3fe2b91ae001d55d 36.1b -.word 0x3f280646,0x3f4acf6b,0x3f1c37c4 @ φ=0.65634573 : cos φ=3fe959ed61449f08 28.7b; sin φ=3fe386f87ffd9617 35.7b -.word 0x3f303041,0x3f45b9e0,0x3f229ae4 @ φ=0.68823630 : cos φ=3fe8b73c0047ae7a 30.8b; sin φ=3fe4535c7ffdf1ac 36.0b -.word 0x3f381da7,0x3f4098ca,0x3f28a620 @ φ=0.71920246 : cos φ=3fe81319402ae6e1 31.6b; sin φ=3fe514c3ffff423c 37.4b -.word 0x3f3fc72f,0x3f3b76ac,0x3f2e564a @ φ=0.74913305 : cos φ=3fe76ed5809d419f 29.7b; sin φ=3fe5cac93fffaf1d 38.7b -.word 0x3f4813db,0x3f35b6cc,0x3f34526b @ φ=0.78155297 : cos φ=3fe6b6d9800e8b52 33.1b; sin φ=3fe68a4d5ffe89fc 36.5b -.word 0x3f4fc779,0x3f30352f,0x3f39b4d0 @ φ=0.81163746 : cos φ=3fe606a5dfdc2b5b 31.8b; sin φ=3fe73699fffd7fc8 35.7b -.word 0x3f57dd52,0x3f2a4170,0x3f3f2d91 @ φ=0.84322083 : cos φ=3fe5482e011ba752 28.9b; sin φ=3fe7e5b21ffcb223 35.3b -.word 0x3f5fce26,0x3f243e9f,0x3f445dc3 @ φ=0.87423933 : cos φ=3fe487d3e0b9864b 29.5b; sin φ=3fe88bb85ffde6d5 35.9b -.word 0x3f6825f1,0x3f1dc250,0x3f499d1c @ φ=0.90682894 : cos φ=3fe3b849ffea9b8f 32.6b; sin φ=3fe933a38002730d 35.7b -.word 0x3f703be1,0x3f175041,0x3f4e7ebf @ φ=0.93841368 : cos φ=3fe2ea0820791b4e 30.1b; sin φ=3fe9cfd7e0053e65 34.6b -.word 0x3f781078,0x3f10ed71,0x3f5306af @ φ=0.96900129 : cos φ=3fe21dae1fdea23e 31.9b; sin φ=3fea60d5e001b90b 36.2b -.word 0x3f7ff4d4,0x3f0a5aa7,0x3f57649b @ φ=0.99982953 : cos φ=3fe14b54deeaa407 28.9b; sin φ=3feaec9360012825 36.8b - -float_wrapper_section tanf - -wrapper_func tanf - push {r0,r14} - ubfx r1,r0,#23,#8 - cmp r1,#0xff @ Inf/NaN? - beq 2f - bl cosf_entry @ this will exit via sintail or costail... - ldr r1,[sp,#0] -@ here C is still set from lsrs r12,r12,#1 - bcs 1f -@ we exited via sintail -@ this is fsc_costail: -@ here calculate cos φ+ε = cosθ - vmul.f32 s5,s7,s1 @ sinφ sinε - vfma.f32 s5,s2,s6 @ sinφ sinε + cosφ(1-cosε) - eors r1,r1,r3 - vsub.f32 s5,s6,s5 @ cosφ - (sinφ sinε + cosφ(1-cosε)) = cosφ cosε - sinφ sinε - vdiv.f32 s0,s5,s4 - vmov.f32 r0,s0 - it pl - eorpl r0,r0,#0x80000000 - pop {r1,r15} - -1: -@ we exited via costail -@ this is fsc_sintail: -@ here calculate sin φ+ε = sinθ - vmul.f32 s4,s2,s7 @ sinφ(1-cosε) - vfms.f32 s4,s6,s1 @ sinφ(1-cosε) - cosφ sinε - eors r1,r1,r3 - vsub.f32 s4,s7,s4 @ cosφ sinε + sinφ cosε - vdiv.f32 s0,s4,s5 - vmov.f32 r0,s0 - it mi - eormi r0,r0,#0x80000000 - pop {r1,r15} - -@ tan of Inf or NaN -2: - lsls r1,r0,#9 - bne 1f @ NaN? return it - orrs r0,r0,#0x80000000 @ Inf: make a NaN -1: - orrs r0,r0,#0x00400000 @ set top mantissa bit of NaN - pop {r3,r15} - - -float_wrapper_section atan2f - -50: -60: - orrs r0,r1,#0x00400000 - bx r14 - -51: - bne 52f @ NaN? - cmp r3,#0x7f800000 @ y an infinity; x an infinity too? - bne 55f @ no: carry on -@ here x and y are both infinities - b 66f - -52: -62: - orrs r0,r0,#0x00400000 - bx r14 - -61: - bne 62b @ NaN? - cmp r3,#0x7f800000 @ y an infinity; x an infinity too? - bne 65f @ no: carry on -66: -@ here x and y are both infinities - subs r0,r0,#1 @ make both finite (and equal) with same sign and retry - subs r1,r1,#1 - b 86f - -70: - and r3,#0x80000000 - cmp r2,#0x00800000 - bhs 72f @ y 0 or denormal? -@ here both x and y are zeros - b 85f -71: - and r2,#0x80000000 -72: - vmov s0,s1,r2,r3 - vdiv.f32 s2,s0,s1 @ restart the division - b 73f @ and go back and check for NaNs - -80: - and r3,#0x80000000 - cmp r2,#0x00800000 - bhs 82f @ y 0 or denormal? -85: -@ here both x and y are zeros - orr r1,r1,0x3f800000 @ retry with x replaced by ~1 with appropriate sign - b 86f - -81: - and r2,#0x80000000 -82: - vmov s0,s1,r2,r3 - vdiv.f32 s2,s1,s0 @ restart the division - b 83f @ and go back and check for NaNs - -wrapper_func atan2f -86: - bic r2,r0,#0x80000000 - bic r3,r1,#0x80000000 - vmov s0,s1,r2,r3 - cmp r2,r3 @ |y| vs. |x| - bhi 1f -@ here |x|≥|y| so we need |y|/|x|; octant/xs/ys: 0++,3-+,4--,7+- - vdiv.f32 s2,s0,s1 @ get this division started; result ≤1 - cmp r3,#0x00800000 - blo 70b @ x 0 or denormal? - cmp r2,#0x00800000 - blo 71b @ y 0 or denormal? -73: - cmp r3,#0x7f800000 - bhi 50b @ x NaN? - cmp r2,#0x7f800000 - bhs 51b @ y Inf or NaN? -55: - cmp r1,#0 - ite mi - ldrmi r12,pi @ if x<0, need two extra quadrants - movpl r12,#0 - @ inner negation is the sign of x - b 2f - -1: -@ here |x|<|y| so we need |x|/|y|; octant/xs/ys: 1++,2-+,5--,6+- - vdiv.f32 s2,s1,s0 @ result <1 - cmp r3,#0x00800000 - blo 80b @ x 0 or denormal? - cmp r2,#0x00800000 - blo 81b @ y 0 or denormal? -83: - cmp r3,#0x7f800000 - bhi 60b @ x NaN? - cmp r2,#0x7f800000 - bhs 61b @ y Inf or NaN? -65: - ldr r12,piover2 @ always one extra quadrant in this path - eors r1,r1,#0x80000000 @ inner negation is the complement of the sign of x - -2: -@ here -@ r0 y -@ r1 ±x -@ r2 |y| -@ r3 |x| -@ s0,s1 = |x|,|y| -@ s2=s0/s1 or s1/s0, 0≤s2≤1 -@ r12=quadrant count * π/2 -@ where the final result is -@ ± (r12 ± atn s2) where the inner negation is given by r1b31 and the outer negation by r0b31 - - adr r2,trigtab3 - vmov.f32 s3,s2 - vcvt.u32.f32 s3,s3,#6 - vmov.f32 r3,s3 - lsrs r3,r3,#1 - adcs r3,r3,#0 @ rounding; set Z if in φ==0 case - add r2,r2,r3,lsl#3 - vldr s5,[r2,#4] @ t=tanφ - vmul.f32 s0,s5,s2 @ ty - vsub.f32 s1,s2,s5 @ y-t - vmov.f32 s5,#1.0 - vadd.f32 s0,s5,s0 @ 1+ty - beq 9f @ did we look up zeroth table entry? - -@ now (s0,s1) = (x,y) - vdiv.f32 s0,s1,s0 @ ε - ldr r2,[r2] @ φ Q29 -@ result is now ±(r12±(r2+atn(s0)) - cmp r1,#0 @ inner negation - it mi - rsbmi r2,r2,#0 - add r2,r12,r2 @ Q29 - cmp r0,#0 @ outer negation - it mi - rsbmi r2,r2,#0 - cmp r2,#0 - bpl 1f - rsbs r2,r2,#0 - clz r3,r2 - lsls r2,r2,r3 - beq 3f - rsb r3,#0x180 - b 2f -1: - clz r3,r2 - lsls r2,r2,r3 - beq 3f - rsb r3,#0x80 -2: - lsrs r2,r2,#8 @ rounding bit to carry - adc r2,r2,r3,lsl#23 @ with rounding -3: - vmul.f32 s2,s0,s0 @ ε² - vldr.f32 s3,onethird - vmul.f32 s2,s2,s0 @ ε³ - teq r0,r1 - vmul.f32 s2,s2,s3 @ ε³/3 - vmov.f32 s4,r2 - vsub.f32 s0,s0,s2 @ ~atn(ε) - ite pl - vaddpl.f32 s0,s4,s0 - vsubmi.f32 s0,s4,s0 - vmov.f32 r0,s0 - bx r14 - -9: @ we looked up the zeroth table entry; we could generate slightly more accurate results here -@ now (s0,s1) = (x,y) - vdiv.f32 s0,s1,s0 @ ε -@ result is now ±(r12±(0+atn(s0)) - mov r2,r12 @ Q29; in fact r12 is only ±π/2 or ±π so can probably simplify this - cmp r0,#0 @ outer negation - it mi - rsbmi r2,r2,#0 - cmp r2,#0 - bpl 1f - rsbs r2,r2,#0 - clz r3,r2 - lsls r2,r2,r3 - beq 3f - rsb r3,#0x180 - b 2f -1: - clz r3,r2 - lsls r2,r2,r3 - beq 3f - rsb r3,#0x80 -2: - lsrs r2,r2,#8 @ rounding bit to carry - adc r2,r2,r3,lsl#23 @ with rounding -3: - vmul.f32 s2,s0,s0 @ ε² - vldr.f32 s3,onethird - vmul.f32 s2,s2,s0 @ ε³ - teq r0,r1 - vmul.f32 s2,s2,s3 @ ε³/3 - vmov.f32 s4,r2 - vsub.f32 s0,s0,s2 @ ~atn(ε) - ite pl - vaddpl.f32 s0,s4,s0 - vsubmi.f32 s0,s4,s0 - vmov.f32 r0,s0 - tst r0,#0x7f800000 @ about to return a denormal? - it ne - bxne r14 - and r0,r0,#0x80000000 @ make it zero - bx r14 - -piover2: .word 0x3243f6a9 @ Q29 -pi: .word 0x6487ed51 @ Q29 -onethird: .float 0.33333333 - -trigtab3: -// φ Q29 tan φ SP -.word 0x00000000,0x00000000 -.word 0x00ffee23,0x3d0001bb @ φ=0.03124148 : tan φ=3fa000375fffff9d 50.4b -.word 0x01fe88dc,0x3d7f992a @ φ=0.06232112 : tan φ=3faff3253fffea1f 44.5b -.word 0x02fe0a70,0x3dc01203 @ φ=0.09351084 : tan φ=3fb8024060002522 42.8b -.word 0x03fad228,0x3e000368 @ φ=0.12436779 : tan φ=3fc0006cfffffc90 45.2b -.word 0x04f5ab70,0x3e1ffdea @ φ=0.15498897 : tan φ=3fc3ffbd400014d5 42.6b -.word 0x05ed56f8,0x3e3fdddc @ φ=0.18522213 : tan φ=3fc7fbbb80000beb 43.4b -.word 0x06e4cfa0,0x3e601425 @ φ=0.21543103 : tan φ=3fcc02849fffe817 42.4b -.word 0x07d8d3e0,0x3e80215d @ φ=0.24521822 : tan φ=3fd0042b9ffff89f 43.1b -.word 0x08c60460,0x3e9000a5 @ φ=0.27417201 : tan φ=3fd20014a000182b 41.4b -.word 0x09b26770,0x3ea01492 @ φ=0.30302784 : tan φ=3fd402923ffff932 43.2b -.word 0x0a996d50,0x3eb01377 @ φ=0.33122888 : tan φ=3fd6026ee0001062 42.0b -.word 0x0b7a6d10,0x3ebff4a0 @ φ=0.35869458 : tan φ=3fd7fe93ffff8c38 39.1b -.word 0x0c593ce0,0x3ed0019f @ φ=0.38589329 : tan φ=3fda0033e0001354 41.7b -.word 0x0d33ebd0,0x3ee01bbc @ φ=0.41258803 : tan φ=3fdc0377800162a1 37.5b -.word 0x0e087ab0,0x3ef01fbd @ φ=0.43853506 : tan φ=3fde03f79fffddf2 40.9b -.word 0x0ed56180,0x3effef98 @ φ=0.46354747 : tan φ=3fdffdf30000767d 39.1b -.word 0x0fa1de80,0x3f080ebf @ φ=0.48850942 : tan φ=3fe101d7dfffb9fc 38.9b -.word 0x10639d00,0x3f0fec31 @ φ=0.51215982 : tan φ=3fe1fd862000aad5 37.6b -.word 0x112690e0,0x3f180cfd @ φ=0.53595775 : tan φ=3fe3019fa00069ea 38.3b -.word 0x11e014c0,0x3f200065 @ φ=0.55860364 : tan φ=3fe4000ca00022e5 39.9b -.word 0x129651e0,0x3f2808be @ φ=0.58084959 : tan φ=3fe50117c00015a7 40.6b -.word 0x1346d400,0x3f300a7d @ φ=0.60239601 : tan φ=3fe6014f9fffa020 38.4b -.word 0x13efc7c0,0x3f37ee2f @ φ=0.62302005 : tan φ=3fe6fdc5dfff98d7 38.3b -.word 0x14988960,0x3f400c32 @ φ=0.64362019 : tan φ=3fe801863fffff81 46.0b -.word 0x1537a8c0,0x3f47ef42 @ φ=0.66304433 : tan φ=3fe8fde8400062a4 38.4b -.word 0x15d4cc60,0x3f4ff630 @ φ=0.68222636 : tan φ=3fe9fec5ffff76e2 37.9b -.word 0x166ef280,0x3f581534 @ φ=0.70104337 : tan φ=3feb02a680004e91 38.7b -.word 0x16ff75c0,0x3f5fef1e @ φ=0.71868408 : tan φ=3febfde3c0001404 40.7b -.word 0x179116a0,0x3f68184d @ φ=0.73646098 : tan φ=3fed03099ffed6e5 36.8b -.word 0x181b5aa0,0x3f701722 @ φ=0.75333911 : tan φ=3fee02e43fffd351 39.5b -.word 0x18a10560,0x3f781071 @ φ=0.76965588 : tan φ=3fef020e20005c05 38.5b -.word 0x19214060,0x3f7ff451 @ φ=0.78530902 : tan φ=3feffe8a1fffe11b 40.1b - -#endif diff --git a/lib/main/pico-sdk/rp2_common/pico_float/float_single_hazard3.S b/lib/main/pico-sdk/rp2_common/pico_float/float_single_hazard3.S deleted file mode 100644 index 1e57f1f257..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_float/float_single_hazard3.S +++ /dev/null @@ -1,318 +0,0 @@ -/* - * Copyright (c) 2024 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "pico/asm_helper.S" -#include "hardware/hazard3.h" - -// This file reimplements some common single-precision soft float routines -// from libgcc. It targets the RV32IMBZbkb dialect (plus optionally Xh3bextm) -// and is tuned for Hazard3 execution timings. - -// Subnormal values are always flushed to zero on both input and output. -// Rounding is always to nearest (even on tie). - -pico_default_asm_setup - -.macro float_section name -#if PICO_FLOAT_IN_RAM -.section RAM_SECTION_NAME(\name), "ax" -#else -.section SECTION_NAME(\name), "ax" -#endif -.endm - -float_section __addsf3 -.global __subsf3 -.p2align 2 -__subsf3: - binvi a1, a1, 31 -.global __addsf3 -__addsf3: - // Unpack exponent: - h3.bextmi a2, a0, 23, 8 - h3.bextmi a3, a1, 23, 8 - // Flush-to-zero => 0 + y = y applies, including nan, with the sole - // exception of y being subnormal (which also needs to be flushed) - beqz a2, __addsf_return_y_flushed - // Don't have to handle this case for x + 0 = 0 because we already know x - // is nonzero - beqz a3, __addsf_return_x - // Unpack significand, plus 3 extra zeroes for working space: - slli a4, a0, 9 - slli a5, a1, 9 - // check nan/inf on input - li t0, 255 - beq a2, t0, __addsf_x_nan_inf - beq a3, t0, __addsf_y_nan_inf - // (finish unpacking significand) - srli a4, a4, 6 - srli a5, a5, 6 - - // If we're still on the straight path then we are adding two normal - // values. Add implicit one (1.xx...xx000) - bseti a4, a4, 23 + 3 - bseti a5, a5, 23 + 3 - // Negate if sign bit is set - bgez a0, 1f - neg a4, a4 -1: - // (tuck this 16-bit here to avoid alignment penalty) - li t1, 25 - bgez a1, 1f - neg a5, a5 -1: - - bltu a2, a3, __addsf_ye_gt_xe - - // The main body is repeated twice with different register assignments. - // lhs is the more-significant addend: -.macro addsf_core packed_lhs, packed_rhs, sig_lhs, sig_rhs, exp_lhs, exp_rhs, rhs_is_x - sub \packed_rhs, \exp_lhs, \exp_rhs - // If there is a large exponent difference then there is no effect on lhs -.if \rhs_is_x - bgeu \packed_rhs, t1, __addsf_return_y -.else - bgeu \packed_rhs, t1, __addsf_return_x -.endif - // Shift rhs down to correct relative significance - sra \packed_lhs, \sig_rhs, \packed_rhs - // Set sticky bit if ones were shifted out - sll \packed_rhs, \packed_lhs, \packed_rhs - sltu \packed_rhs, \packed_rhs, \sig_rhs - or \packed_lhs, \packed_lhs, \packed_rhs - // Add significands - add \sig_lhs, \sig_lhs, \packed_lhs - // Detect exact cancellation (may be beyond max normalisation shift; also - // IEEE 754 requires +0 for exact cancellation, no matter input signs) - beqz \sig_lhs, __addsf_return_0 - // Convert two's complement back to sign + magnitude - srai \exp_rhs, \sig_lhs, 31 - xor \sig_lhs, \sig_lhs, \exp_rhs - sub \sig_lhs, \sig_lhs, \exp_rhs - // Renormalise significand: bit 31 is now implicit one - clz \packed_lhs, \sig_lhs - sll \sig_lhs, \sig_lhs, \packed_lhs - // Adjust exponent - addi \packed_lhs, \packed_lhs, -5 - sub \exp_lhs, \exp_lhs, \packed_lhs - - // Round to nearest, even on tie (bias upward if above odd number) - bexti \packed_lhs, \sig_lhs, 8 - addi \sig_lhs, \sig_lhs, 127 - add \sig_lhs, \sig_lhs, \packed_lhs - // Exponent may increase by one due to rounding up from all-ones; this is - // detected by clearing of implicit one (there is a carry-out too) - bgez \sig_lhs, 3f -4: - // Detect underflow/overflow - bgeu \exp_lhs, t0, 1f - - // Pack and return - packh \exp_lhs, \exp_lhs, \exp_rhs - slli \exp_lhs, \exp_lhs, 23 - slli \sig_lhs, \sig_lhs, 1 - srli \sig_lhs, \sig_lhs, 9 - add a0, \sig_lhs, \exp_lhs - ret -1: - bgez \exp_lhs, 2f - // Signed zero on underflow - slli a0, \exp_rhs, 31 - ret -2: - // Signed infinity on overflow - packh a0, t0, \exp_rhs - slli a0, a0, 23 - ret -3: - // Exponent increase due to rounding (uncommon) - srli \sig_lhs, \sig_lhs, 1 - addi \exp_lhs, \exp_lhs, 1 - j 4b -.endm - -__addsf_xe_gte_ye: - addsf_core a0, a1, a4, a5, a2, a3, 0 -.p2align 2 -__addsf_ye_gt_xe: - addsf_core a1, a0, a5, a4, a3, a2, 1 - -__addsf_x_nan_inf: - // When at least one operand is nan, we must propagate at least one of - // those nan payloads (sign of nan result is unspecified, which we take - // advantage of by implementing x - y as x + -y). Check x nan vs inf: - bnez a4, __addsf_return_x -__addsf_x_inf: - // If x is +-inf, need to distinguish the following cases: - bne a3, t0, __addsf_return_x // y is neither inf nor nan -> return x (propagate inf) - bnez a5, __addsf_return_y // y is nan: -> return y (propagate nan) - xor a5, a0, a1 - srli a5, a5, 31 - beqz a5, __addsf_return_x // y is inf of same sign -> return either x or y (x is faster) - li a0, -1 // y is inf of different sign -> return nan - ret - -__addsf_y_nan_inf: - // Mirror of __addsf_x_nan_inf - bnez a5, __addsf_return_y -__addsf_y_inf: - bne a2, t0, __addsf_return_y - bnez a4, __addsf_return_x - xor a4, a0, a1 - srli a4, a4, 31 - beqz a4, __addsf_return_x - li a0, -1 - ret - -__addsf_return_y_flushed: - bnez a3, 1f - srli a1, a1, 23 - slli a1, a1, 23 -1: -__addsf_return_y: - mv a0, a1 -__addsf_return_x: - ret -__addsf_return_0: - li a0, 0 - ret - - -float_section __mulsf3 -.global __mulsf3 -.p2align 2 -__mulsf3: - // Force y to be positive (by possibly negating x) *before* unpacking. - // This allows many special cases to be handled without repacking. - bgez a1, 1f - binvi a0, a0, 31 -1: - // Unpack exponent: - h3.bextmi a2, a0, 23, 8 - h3.bextmi a3, a1, 23, 8 - // Check special cases - li t0, 255 - beqz a2, __mulsf_x_0 - beqz a3, __mulsf_y_0 - beq a2, t0, __mulsf_x_nan_inf - beq a3, t0, __mulsf_y_nan_inf - - // Finish unpacking sign - srai a6, a0, 31 - // Unpack significand (with implicit one in MSB) - slli a4, a0, 8 - slli a5, a1, 8 - bseti a4, a4, 31 - bseti a5, a5, 31 - // Get full 64-bit multiply result in a4:a1 (one cycle each half) - // Going from Q1.23 to Q2.46 (both left-justified) - mul a1, a4, a5 - mulhu a4, a4, a5 - // Normalise (shift left by either 0 or 1) -- bit 8 is the LSB of the - // final significand (ignoring rounding) - clz a0, a4 - sll a4, a4, a0 - sub a2, a2, a0 - // After normalising we can calculate the final exponent, since rounding - // cannot increase the exponent for multiplication (unlike addition) - add a2, a2, a3 - // Subtract redundant bias term (127), add 1 for normalisation correction - addi a2, a2, -126 - blez a2, __mulsf_underflow - bge a2, t0, __mulsf_overflow - - // Gather sticky bits from low fraction: - snez a1, a1 - or a4, a4, a1 - // Round to nearest, even on tie (aka bias upward if odd) - bexti a1, a4, 8 - add a4, a4, a1 - addi a4, a4, 127 - // Pack it and ship it - packh a2, a2, a6 - slli a2, a2, 23 - slli a4, a4, 1 - srli a4, a4, 9 - add a0, a4, a2 - ret - -__mulsf_underflow: - // Signed zero - slli a0, a6, 31 - ret -__mulsf_overflow: - // Signed inf - packh a0, t0, a6 - slli a0, a0, 23 - ret - -__mulsf_x_0: - // 0 times nan -> propagate nan - // 0 times inf -> generate nan - // 0 times others -> 0 (need to flush significand too as we are FTZ) - bne a3, t0, __mulsf_return_flushed_x - slli a5, a1, 9 - beqz a5, 1f - // Propagate nan from y -__mulsf_return_y: - mv a0, a1 - ret -1: - // Generate new nan - li a0, -1 - ret - -__mulsf_y_0: - // Mirror image of x_0 except we still return x for signed 0, since the - // signs were already resolved. - bne a2, t0, __mulsf_return_flushed_x - slli a1, a0, 9 - bnez a1, 1f - li a0, -1 -1: - ret - -__mulsf_return_flushed_x: - // If we don't support subnormals we at least need to flush to a canonical - // zero. This is just a sign bit in bit 31. - srli a0, a0, 31 - slli a0, a0, 31 -__mulsf_return_x: - ret - -__mulsf_x_nan_inf: - // We know that y is not zero and is positive. So... - // x is nan -> return x - // else y is nan -> return y - // else y is inf -> return x - // else y is normal -> return x - // (the order of the first two clauses is actually our free choice) - slli a4, a0, 9 - bnez a4, __mulsf_return_x - bne a3, t0, __mulsf_return_x - slli a5, a1, 9 - bnez a5, __mulsf_return_y - ret // return x - -__mulsf_y_nan_inf: - // We know that x is not zero, nan, nor inf. That just leaves normals. - // y is nan -> return y - // y is inf -> return inf * sgn(x) (since we already merged the signs) - slli a5, a1, 9 - bnez a5, __mulsf_return_y - srai a0, a0, 31 - packh a0, t0, a0 - slli a0, a0, 23 - ret - - -// This is a hack to improve soft float performance for the routines we don't -// implement (e.g. libm) in libraries built against a non-Zbb ISA dialect: -float_section __clz2si -.global __clz2si -__clz2si: - clz a0, a0 - ret diff --git a/lib/main/pico-sdk/rp2_common/pico_float/float_v1_rom_shim_rp2040.S b/lib/main/pico-sdk/rp2_common/pico_float/float_v1_rom_shim_rp2040.S deleted file mode 100644 index 665a61038b..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_float/float_v1_rom_shim_rp2040.S +++ /dev/null @@ -1,346 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "pico/asm_helper.S" - -#if PICO_FLOAT_SUPPORT_ROM_V1 && PICO_RP2040_B0_SUPPORTED - -#ifndef PICO_FLOAT_IN_RAM -#define PICO_FLOAT_IN_RAM 0 -#endif - -pico_default_asm_setup - -.macro float_section name -// todo separate flag for shims? -#if PICO_FLOAT_IN_RAM -.section RAM_SECTION_NAME(\name), "ax" -#else -.section SECTION_NAME(\name), "ax" -#endif -.endm - -float_section float_table_shim_on_use_helper -regular_func float_table_shim_on_use_helper - push {r0-r2, lr} - mov r0, ip -#ifndef NDEBUG - // sanity check to make sure we weren't called by non (shimmable_) table_tail_call macro - cmp r0, #0 - bne 1f - bkpt #0 -#endif -1: - ldrh r1, [r0] - lsrs r2, r1, #8 - adds r0, #2 - cmp r2, #0xdf - bne 1b - uxtb r1, r1 // r1 holds table offset - lsrs r2, r0, #2 - bcc 1f - // unaligned - ldrh r2, [r0, #0] - ldrh r0, [r0, #2] - lsls r0, #16 - orrs r0, r2 - b 2f -1: - ldr r0, [r0] -2: - ldr r2, =sf_table - str r0, [r2, r1] - str r0, [sp, #12] - pop {r0-r2, pc} - -float_section 642float_shims - -@ convert uint64 to float, rounding -regular_func uint642float_shim - movs r2,#0 @ fall through - -@ convert unsigned 64-bit fix to float, rounding; number of r0:r1 bits after point in r2 -regular_func ufix642float_shim - push {r4,r5,r14} - cmp r1,#0 - bpl 3f @ positive? we can use signed code - lsls r5,r1,#31 @ contribution to sticky bits - orrs r5,r0 - lsrs r0,r1,#1 - subs r2,#1 - b 4f - -@ convert int64 to float, rounding -regular_func int642float_shim - movs r2,#0 @ fall through - -@ convert signed 64-bit fix to float, rounding; number of r0:r1 bits after point in r2 -regular_func fix642float_shim - push {r4,r5,r14} -3: - movs r5,r0 - orrs r5,r1 - beq ret_pop45 @ zero? return +0 - asrs r5,r1,#31 @ sign bits -2: - asrs r4,r1,#24 @ try shifting 7 bits at a time - cmp r4,r5 - bne 1f @ next shift will overflow? - lsls r1,#7 - lsrs r4,r0,#25 - orrs r1,r4 - lsls r0,#7 - adds r2,#7 - b 2b -1: - movs r5,r0 - movs r0,r1 -4: - negs r2,r2 - adds r2,#32+29 - - // bl packx - ldr r1, =0x29ef // packx - blx r1 -ret_pop45: - pop {r4,r5,r15} - -float_section fatan2_shim -regular_func fatan2_shim - push {r4,r5,r14} - - ldr r4, =0x29c1 // unpackx - mov ip, r4 -@ unpack arguments and shift one down to have common exponent - blx ip - mov r4,r0 - mov r0,r1 - mov r1,r4 - mov r4,r2 - mov r2,r3 - mov r3,r4 - blx ip - lsls r0,r0,#5 @ Q28 - lsls r1,r1,#5 @ Q28 - adds r4,r2,r3 @ this is -760 if both arguments are 0 and at least -380-126=-506 otherwise - asrs r4,#9 - adds r4,#1 - bmi 2f @ force y to 0 proper, so result will be zero - subs r4,r2,r3 @ calculate shift - bge 1f @ ex>=ey? - negs r4,r4 @ make shift positive - asrs r0,r4 - cmp r4,#28 - blo 3f - asrs r0,#31 - b 3f -1: - asrs r1,r4 - cmp r4,#28 - blo 3f -2: -@ here |x|>>|y| or both x and y are ±0 - cmp r0,#0 - bge 4f @ x positive, return signed 0 - ldr r3, =0x2cfc @ &pi_q29, circular coefficients - ldr r0,[r3] @ x negative, return +/- pi - asrs r1,#31 - eors r0,r1 - b 7f -4: - asrs r0,r1,#31 - b 7f -3: - movs r2,#0 @ initial angle - ldr r3, =0x2cfc @ &pi_q29, circular coefficients - cmp r0,#0 @ x negative - bge 5f - negs r0,r0 @ rotate to 1st/4th quadrants - negs r1,r1 - ldr r2,[r3] @ pi Q29 -5: - movs r4,#1 @ m=1 - ldr r5, =0x2b97 @ cordic_vec - blx r5 @ also produces magnitude (with scaling factor 1.646760119), which is discarded - mov r0,r2 @ result here is -pi/2..3pi/2 Q29 -@ asrs r2,#29 -@ subs r0,r2 - ldr r3, =0x2cfc @ &pi_q29, circular coefficients - ldr r2,[r3] @ pi Q29 - adds r4,r0,r2 @ attempt to fix -3pi/2..-pi case - bcs 6f @ -pi/2..0? leave result as is - subs r4,r0,r2 @ pi: take off 2pi -6: - subs r0,#1 @ fiddle factor so atan2(0,1)==0 -7: - movs r2,#0 @ exponent for pack - ldr r3, =0x2b19 - bx r3 - -float_section float232_shims - -regular_func float2int_shim - movs r1,#0 @ fall through -regular_func float2fix_shim - // check for -0 or -denormal upfront - asrs r2, r0, #23 - adds r2, #128 - adds r2, #128 - beq 1f - // call original - ldr r2, =0x2acd - bx r2 - 1: - movs r0, #0 - bx lr - -float_section float264_shims - -regular_func float2int64_shim - movs r1,#0 @ and fall through -regular_func float2fix64_shim - push {r14} - bl f2fix - b d2f64_a - -regular_func float2uint64_shim - movs r1,#0 @ and fall through -regular_func float2ufix64_shim - asrs r3,r0,#23 @ negative? return 0 - bmi ret_dzero -@ and fall through - -@ convert float in r0 to signed fixed point in r0:r1:r3, r1 places after point, rounding towards -Inf -@ result clamped so that r3 can only be 0 or -1 -@ trashes r12 -.thumb_func -f2fix: - push {r4,r14} - mov r12,r1 - asrs r3,r0,#31 - lsls r0,#1 - lsrs r2,r0,#24 - beq 1f @ zero? - cmp r2,#0xff @ Inf? - beq 2f - subs r1,r2,#1 - subs r2,#0x7f @ remove exponent bias - lsls r1,#24 - subs r0,r1 @ insert implied 1 - eors r0,r3 - subs r0,r3 @ top two's complement - asrs r1,r0,#4 @ convert to double format - lsls r0,#28 - ldr r4, =d2fix_a - bx r4 -1: - movs r0,#0 - movs r1,r0 - movs r3,r0 - pop {r4,r15} -2: - mvns r0,r3 @ return max/min value - mvns r1,r3 - pop {r4,r15} - -ret_dzero: - movs r0,#0 - movs r1,#0 - bx r14 - -float_section d2fix_a_float - -.weak d2fix_a // weak because it exists in float shims too -.thumb_func -d2fix_a: -@ here -@ r0:r1 two's complement mantissa -@ r2 unbaised exponent -@ r3 mantissa sign extension bits - add r2,r12 @ exponent plus offset for required binary point position - subs r2,#52 @ required shift - bmi 1f @ shift down? -@ here a shift up by r2 places - cmp r2,#12 @ will clamp? - bge 2f - movs r4,r0 - lsls r1,r2 - lsls r0,r2 - negs r2,r2 - adds r2,#32 @ complementary shift - lsrs r4,r2 - orrs r1,r4 - pop {r4,r15} -2: - mvns r0,r3 - mvns r1,r3 @ overflow: clamp to extreme fixed-point values - pop {r4,r15} -1: -@ here a shift down by -r2 places - adds r2,#32 - bmi 1f @ long shift? - mov r4,r1 - lsls r4,r2 - negs r2,r2 - adds r2,#32 @ complementary shift - asrs r1,r2 - lsrs r0,r2 - orrs r0,r4 - pop {r4,r15} -1: -@ here a long shift down - movs r0,r1 - asrs r1,#31 @ shift down 32 places - adds r2,#32 - bmi 1f @ very long shift? - negs r2,r2 - adds r2,#32 - asrs r0,r2 - pop {r4,r15} -1: - movs r0,r3 @ result very near zero: use sign extension bits - movs r1,r3 - pop {r4,r15} -d2f64_a: - asrs r2,r1,#31 - cmp r2,r3 - bne 1f @ sign extension bits fail to match sign of result? - pop {r15} -1: - mvns r0,r3 - movs r1,#1 - lsls r1,#31 - eors r1,r1,r0 @ generate extreme fixed-point values - pop {r15} - -float_section float2double_shim -regular_func float2double_shim - lsrs r3,r0,#31 @ sign bit - lsls r3,#31 - lsls r1,r0,#1 - lsrs r2,r1,#24 @ exponent - beq 1f @ zero? - cmp r2,#0xff @ Inf? - beq 2f - lsrs r1,#4 @ exponent and top 20 bits of mantissa - ldr r2,=(0x3ff-0x7f)<<20 @ difference in exponent offsets - adds r1,r2 - orrs r1,r3 - lsls r0,#29 @ bottom 3 bits of mantissa - bx r14 -1: - movs r1,r3 @ return signed zero -3: - movs r0,#0 - bx r14 -2: - ldr r1,=0x7ff00000 @ return signed infinity - adds r1,r3 - b 3b - -#endif \ No newline at end of file diff --git a/lib/main/pico-sdk/rp2_common/pico_float/include/pico/float.h b/lib/main/pico-sdk/rp2_common/pico_float/include/pico/float.h deleted file mode 100644 index 6cafc83e45..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_float/include/pico/float.h +++ /dev/null @@ -1,90 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _PICO_FLOAT_H -#define _PICO_FLOAT_H - -#include -#include -#include "pico.h" -#include "pico/bootrom/sf_table.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** \file float.h -* \defgroup pico_float pico_float -* -* \brief Optimized single-precision floating point functions -* -* (Replacement) optimized implementations are provided for the following compiler built-ins -* and math library functions on Arm: -* -* - __aeabi_fadd, __aeabi_fdiv, __aeabi_fmul, __aeabi_frsub, __aeabi_fsub, __aeabi_cfcmpeq, __aeabi_cfrcmple, __aeabi_cfcmple, __aeabi_fcmpeq, __aeabi_fcmplt, __aeabi_fcmple, __aeabi_fcmpge, __aeabi_fcmpgt, __aeabi_fcmpun, __aeabi_i2f, __aeabi_l2f, __aeabi_ui2f, __aeabi_ul2f, __aeabi_f2iz, __aeabi_f2lz, __aeabi_f2uiz, __aeabi_f2ulz, __aeabi_f2d, sqrtf, cosf, sinf, tanf, atan2f, expf, logf -* - ldexpf, copysignf, truncf, floorf, ceilf, roundf, asinf, acosf, atanf, sinhf, coshf, tanhf, asinhf, acoshf, atanhf, exp2f, log2f, exp10f, log10f, powf, hypotf, cbrtf, fmodf, dremf, remainderf, remquof, expm1f, log1pf, fmaf -* - powintf, sincosf (GNU extensions) -* -* The following additional optimized functions are also provided: -* -* - int2float, uint2float, int642float, uint642float, fix2float, ufix2float, fix642float, ufix642float -* - float2fix, float2ufix, float2fix64, float2ufix64, float2int, float2uint, float2int64, float2uint64, float2int_z, float2int64_z, float2uint_z, float2uint64_z -* - exp10f, sincosf, powintf -* -* On RP2350 (Arm) the following additional functions are available; the _fast methods are faster but do not round correctly -* -* - float2fix64_z, fdiv_fast, fsqrt_fast, -* -* On RP2350 RISC-V, only a small number of compiler runtime functions are overridden with faster implementations: -* -* - __addsf3, __subsf3, __mulsf3 -*/ - -// None of these functions are available on RISC-V: -#if !defined(__riscv) || PICO_COMBINED_DOCS - -float int2float(int32_t f); -float uint2float(uint32_t f); -float int642float(int64_t f); -float uint642float(uint64_t f); -float fix2float(int32_t m, int e); -float ufix2float(uint32_t m, int e); -float fix642float(int64_t m, int e); -float ufix642float(uint64_t m, int e); - -// These methods round towards -Infinity. -int32_t float2fix(float f, int e); -uint32_t float2ufix(float f, int e); -int64_t float2fix64(float f, int e); -uint64_t float2ufix64(float f, int e); -int32_t float2int(float f); -uint32_t float2uint(float f); -int64_t float2int64(float f); -uint64_t float2uint64(float f); - -// These methods round towards 0. -int32_t float2int_z(float f); -int64_t float2int64_z(float f); -int32_t float2uint_z(float f); -int64_t float2uint64_z(float f); - -float exp10f(float x); -void sincosf(float x, float *sinx, float *cosx); -float powintf(float x, int y); - -#if !PICO_RP2040 || PICO_COMBINED_DOCS -int64_t float2fix64_z(float f, int e); -float fdiv_fast(float n, float d); -float fsqrt_fast(float f); -#endif - -#endif - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/lib/main/pico-sdk/rp2_common/pico_i2c_slave/i2c_slave.c b/lib/main/pico-sdk/rp2_common/pico_i2c_slave/i2c_slave.c deleted file mode 100644 index 1ef24c829d..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_i2c_slave/i2c_slave.c +++ /dev/null @@ -1,98 +0,0 @@ -/* - * Copyright (c) 2021 Valentin Milea - * Copyright (c) 2023 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "pico/i2c_slave.h" -#include "hardware/irq.h" - -typedef struct i2c_slave { - i2c_slave_handler_t handler; - bool transfer_in_progress; -} i2c_slave_t; - -static i2c_slave_t i2c_slaves[2]; - -static void __isr __not_in_flash_func(i2c_slave_irq_handler)(void) { - uint i2c_index = __get_current_exception() - VTABLE_FIRST_IRQ - I2C0_IRQ; - i2c_slave_t *slave = &i2c_slaves[i2c_index]; - i2c_inst_t *i2c = i2c_get_instance(i2c_index); - i2c_hw_t *hw = i2c_get_hw(i2c); - - uint32_t intr_stat = hw->intr_stat; - if (intr_stat == 0) { - return; - } - bool do_finish_transfer = false; - if (intr_stat & I2C_IC_INTR_STAT_R_TX_ABRT_BITS) { - hw->clr_tx_abrt; - do_finish_transfer = true; - } - if (intr_stat & I2C_IC_INTR_STAT_R_START_DET_BITS) { - hw->clr_start_det; - do_finish_transfer = true; - } - if (intr_stat & I2C_IC_INTR_STAT_R_STOP_DET_BITS) { - hw->clr_stop_det; - do_finish_transfer = true; - } - if (do_finish_transfer && slave->transfer_in_progress) { - slave->handler(i2c, I2C_SLAVE_FINISH); - slave->transfer_in_progress = false; - } - if (intr_stat & I2C_IC_INTR_STAT_R_RX_FULL_BITS) { - slave->transfer_in_progress = true; - slave->handler(i2c, I2C_SLAVE_RECEIVE); - } - if (intr_stat & I2C_IC_INTR_STAT_R_RD_REQ_BITS) { - hw->clr_rd_req; - slave->transfer_in_progress = true; - slave->handler(i2c, I2C_SLAVE_REQUEST); - } -} - -void i2c_slave_init(i2c_inst_t *i2c, uint8_t address, i2c_slave_handler_t handler) { - assert(i2c == i2c0 || i2c == i2c1); - assert(handler != NULL); - - uint i2c_index = i2c_hw_index(i2c); - i2c_slave_t *slave = &i2c_slaves[i2c_index]; - slave->handler = handler; - - // Note: The I2C slave does clock stretching implicitly after a RD_REQ, while the Tx FIFO is empty. - // Clock stretching while the Rx FIFO is full is also enabled by default. - i2c_set_slave_mode(i2c, true, address); - - i2c_hw_t *hw = i2c_get_hw(i2c); - // unmask necessary interrupts - hw->intr_mask = - I2C_IC_INTR_MASK_M_RX_FULL_BITS | I2C_IC_INTR_MASK_M_RD_REQ_BITS | I2C_IC_INTR_MASK_M_TX_ABRT_BITS | - I2C_IC_INTR_MASK_M_STOP_DET_BITS | I2C_IC_INTR_MASK_M_START_DET_BITS; - - // enable interrupt for current core - uint num = I2C0_IRQ + i2c_index; - irq_set_exclusive_handler(num, i2c_slave_irq_handler); - irq_set_enabled(num, true); -} - -void i2c_slave_deinit(i2c_inst_t *i2c) { - assert(i2c == i2c0 || i2c == i2c1); - - uint i2c_index = i2c_hw_index(i2c); - i2c_slave_t *slave = &i2c_slaves[i2c_index]; - assert(slave->handler); // should be called after i2c_slave_init() - - slave->handler = NULL; - slave->transfer_in_progress = false; - - uint num = I2C0_IRQ + i2c_index; - irq_set_enabled(num, false); - irq_remove_handler(num, i2c_slave_irq_handler); - - i2c_hw_t *hw = i2c_get_hw(i2c); - hw->intr_mask = I2C_IC_INTR_MASK_RESET; - - i2c_set_slave_mode(i2c, false, 0); -} diff --git a/lib/main/pico-sdk/rp2_common/pico_i2c_slave/include/pico/i2c_slave.h b/lib/main/pico-sdk/rp2_common/pico_i2c_slave/include/pico/i2c_slave.h deleted file mode 100644 index ddae0dca51..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_i2c_slave/include/pico/i2c_slave.h +++ /dev/null @@ -1,75 +0,0 @@ -/* - * Copyright (c) 2021 Valentin Milea - * Copyright (c) 2023 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _PICO_I2C_SLAVE_H -#define _PICO_I2C_SLAVE_H - -#include "hardware/i2c.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** \file pico/i2c_slave.h - * \defgroup pico_i2c_slave pico_i2c_slave - * - * \brief Functions providing an interrupt driven I2C slave interface - * - * This I2C slave helper library configures slave mode and hooks the relevant I2C IRQ - * so that a user supplied handler is called with enumerated I2C events. - * - * An example application \c slave_mem_i2c, which makes use of this library, can be found in - * pico_examples. - */ - -/** - * \brief I2C slave event types. - * \ingroup pico_i2c_slave - */ -typedef enum i2c_slave_event_t -{ - I2C_SLAVE_RECEIVE, ///< Data from master is available for reading. Slave must read from Rx FIFO. - I2C_SLAVE_REQUEST, ///< Master is requesting data. Slave must write into Tx FIFO. - I2C_SLAVE_FINISH, ///< Master has sent a Stop or Restart signal. Slave may prepare for the next transfer. -} i2c_slave_event_t; - -/** - * \brief I2C slave event handler - * \ingroup pico_i2c_slave - * - * The event handler will run from the I2C ISR, so it should return quickly (under 25 us at 400 kb/s). - * Avoid blocking inside the handler and split large data transfers across multiple calls for best results. - * When sending data to master, up to \ref i2c_get_write_available() bytes can be written without blocking. - * When receiving data from master, up to \ref i2c_get_read_available() bytes can be read without blocking. - * - * \param i2c Either \ref i2c0 or \ref i2c1 - * \param event Event type. - */ -typedef void (*i2c_slave_handler_t)(i2c_inst_t *i2c, i2c_slave_event_t event); - -/** - * \brief Configure an I2C instance for slave mode. - * \ingroup pico_i2c_slave - * \param i2c I2C instance. - * \param address 7-bit slave address. - * \param handler Callback for events from I2C master. It will run from the I2C ISR, on the CPU core - * where the slave was initialised. - */ -void i2c_slave_init(i2c_inst_t *i2c, uint8_t address, i2c_slave_handler_t handler); - -/** - * \brief Restore an I2C instance to master mode. - * \ingroup pico_i2c_slave - * \param i2c Either \ref i2c0 or \ref i2c1 - */ -void i2c_slave_deinit(i2c_inst_t *i2c); - -#ifdef __cplusplus -} -#endif - -#endif // _PICO_I2C_SLAVE_H_ diff --git a/lib/main/pico-sdk/rp2_common/pico_int64_ops/include/pico/int64_ops.h b/lib/main/pico-sdk/rp2_common/pico_int64_ops/include/pico/int64_ops.h deleted file mode 100644 index 794b7683eb..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_int64_ops/include/pico/int64_ops.h +++ /dev/null @@ -1,20 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _PICO_INT64_OPS_H -#define _PICO_INT64_OPS_H - -#include "pico/types.h" - -/** \file int64_ops.h - * \defgroup pico_int64_ops pico_int64_ops - * - * \brief Optimized replacement implementations of the compiler built-in 64 bit multiplication - * - * This library does not provide any additional functions -*/ - -#endif \ No newline at end of file diff --git a/lib/main/pico-sdk/rp2_common/pico_int64_ops/pico_int64_ops_aeabi.S b/lib/main/pico-sdk/rp2_common/pico_int64_ops/pico_int64_ops_aeabi.S deleted file mode 100644 index a1ad7e21df..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_int64_ops/pico_int64_ops_aeabi.S +++ /dev/null @@ -1,46 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "pico/asm_helper.S" - -pico_default_asm_setup - -.macro int64_section name -#if PICO_INT64_OPS_IN_RAM -.section RAM_SECTION_NAME(\name), "ax" -#else -.section SECTION_NAME(\name), "ax" -#endif -.endm - -int64_section __aeabi_lmul - -wrapper_func __aeabi_lmul - muls r1, r2 - muls r3, r0 - adds r1, r3 - mov r12, r1 - lsrs r1, r2, #16 - uxth r3, r0 - muls r3, r1 - push {r4} - lsrs r4, r0, #16 - muls r1, r4 - uxth r2, r2 - uxth r0, r0 - muls r0, r2 - muls r2, r4 - lsls r4, r3, #16 - lsrs r3, #16 - adds r0, r4 - pop {r4} - adcs r1, r3 - lsls r3, r2, #16 - lsrs r2, #16 - adds r0, r3 - adcs r1, r2 - add r1, r12 - bx lr diff --git a/lib/main/pico-sdk/rp2_common/pico_lwip/doc.h b/lib/main/pico-sdk/rp2_common/pico_lwip/doc.h deleted file mode 100644 index 0825fabb6c..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_lwip/doc.h +++ /dev/null @@ -1,46 +0,0 @@ -/** - * \defgroup pico_lwip pico_lwip - * \brief Integration/wrapper libraries for lwIP - * the documentation for which is here. - * - * The main \c \b pico_lwip library itself aggregates the lwIP RAW API: \c \b pico_lwip_core, \c \b pico_lwip_core4, \c \b pico_lwip_core6, \c \b pico_lwip_api, \c \b pico_lwip_netif, \c \b pico_lwip_sixlowpan and \c \b pico_lwip_ppp. - * - * If you wish to run in NO_SYS=1 mode, then you can link \c \b pico_lwip along with \ref pico_lwip_nosys. - * - * If you wish to run in NO_SYS=0 mode, then you can link \c \b pico_lwip with (for instance) \ref pico_lwip_freertos, - * and also link in pico_lwip_api for the additional blocking/thread-safe APIs. - * - * Additionally you must link in \ref pico_lwip_arch unless you provide your own compiler bindings for lwIP. - * - * Additional individual pieces of lwIP functionality are available à la cart, by linking any of the libraries below. - * - * The following libraries are provided that contain exactly the equivalent lwIP functionality groups: - * - * * \c \b pico_lwip_core - - * * \c \b pico_lwip_core4 - - * * \c \b pico_lwip_core6 - - * * \c \b pico_lwip_netif - - * * \c \b pico_lwip_sixlowpan - - * * \c \b pico_lwip_ppp - - * * \c \b pico_lwip_api - - * - * The following libraries are provided that contain exactly the equivalent lwIP application support: - * - * * \c \b pico_lwip_snmp - - * * \c \b pico_lwip_http - - * * \c \b pico_lwip_makefsdata - - * * \c \b pico_lwip_iperf - - * * \c \b pico_lwip_smtp - - * * \c \b pico_lwip_sntp - - * * \c \b pico_lwip_mdns - - * * \c \b pico_lwip_netbios - - * * \c \b pico_lwip_tftp - - * * \c \b pico_lwip_mbedtls - - * * \c \b pico_lwip_mqtt - - * - */ - -/** \defgroup pico_lwip_arch pico_lwip_arch - * \ingroup pico_lwip - * \brief lwIP compiler adapters. This is not included by default in \c \b pico_lwip in case you wish to implement your own. - */ diff --git a/lib/main/pico-sdk/rp2_common/pico_lwip/include/arch/cc.h b/lib/main/pico-sdk/rp2_common/pico_lwip/include/arch/cc.h deleted file mode 100644 index 1e7c94c7ca..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_lwip/include/arch/cc.h +++ /dev/null @@ -1,102 +0,0 @@ -/* - * Copyright (c) 2001-2003 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ -#ifndef __CC_H__ -#define __CC_H__ - -#include - -#ifndef PICO_LWIP_CUSTOM_LOCK_TCPIP_CORE -#define PICO_LWIP_CUSTOM_LOCK_TCPIP_CORE 1 -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -#if NO_SYS -// todo really we should just not allow SYS_LIGHTWEIGHT_PROT for nosys mode (it doesn't do anything anyway) -typedef int sys_prot_t; -#elif PICO_LWIP_CUSTOM_LOCK_TCPIP_CORE -void pico_lwip_custom_lock_tcpip_core(void); -void pico_lwip_custom_unlock_tcpip_core(void); -#define LOCK_TCPIP_CORE() pico_lwip_custom_lock_tcpip_core() -#define UNLOCK_TCPIP_CORE() pico_lwip_custom_unlock_tcpip_core() -#endif - -/* define compiler specific symbols */ -#if defined (__ICCARM__) - -#define PACK_STRUCT_BEGIN -#define PACK_STRUCT_STRUCT -#define PACK_STRUCT_END -#define PACK_STRUCT_FIELD(x) x -#define PACK_STRUCT_USE_INCLUDES - -#elif defined (__CC_ARM) - -#define PACK_STRUCT_BEGIN __packed -#define PACK_STRUCT_STRUCT -#define PACK_STRUCT_END -#define PACK_STRUCT_FIELD(x) x - -#elif defined (__GNUC__) - -#define PACK_STRUCT_BEGIN -#define PACK_STRUCT_STRUCT __attribute__ ((__packed__)) -#define PACK_STRUCT_END -#define PACK_STRUCT_FIELD(x) x - -#elif defined (__TASKING__) - -#define PACK_STRUCT_BEGIN -#define PACK_STRUCT_STRUCT -#define PACK_STRUCT_END -#define PACK_STRUCT_FIELD(x) x - -#endif - -#ifndef LWIP_PLATFORM_ASSERT -#include "pico.h" -#define LWIP_PLATFORM_ASSERT(x) panic(x) -#endif - -#ifndef LWIP_RAND -#include "pico/rand.h" -// Use the pico_rand library which goes to reasonable lengths to try to provide good entropy -#define LWIP_RAND() get_rand_32() -#endif - -#ifdef __cplusplus -} -#endif - -#endif /* __CC_H__ */ diff --git a/lib/main/pico-sdk/rp2_common/pico_lwip/include/pico/lwip_freertos.h b/lib/main/pico-sdk/rp2_common/pico_lwip/include/pico/lwip_freertos.h deleted file mode 100644 index 72d6ccf62f..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_lwip/include/pico/lwip_freertos.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Copyright (c) 2022 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _PICO_LWIP_FREERTOS_H -#define _PICO_LWIP_FREERTOS_H - -#include "pico.h" -#include "pico/async_context.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** \file pico/lwip_freertos.h -* \defgroup pico_lwip_freertos pico_lwip_freertos -* \ingroup pico_lwip -* \brief Glue library for integration lwIP in \c NO_SYS=0 mode with the SDK -* -* Simple \c init and \c deinit are all that is required to hook up lwIP (with full blocking API support) via an \ref async_context instance -*/ - -/*! \brief Initializes lwIP (NO_SYS=0 mode) support support for FreeRTOS using the provided async_context - * \ingroup pico_lwip_freertos - * - * If the initialization succeeds, \ref lwip_freertos_deinit() can be called to shutdown lwIP support - * - * \param context the async_context instance that provides the abstraction for handling asynchronous work. Note in general - * this would be an \ref async_context_freertos instance, though it doesn't have to be. - * - * \return true if the initialization succeeded -*/ -bool lwip_freertos_init(async_context_t *context); - -/*! \brief De-initialize lwIP (NO_SYS=0 mode) support for FreeRTOS - * \ingroup pico_lwip_freertos - * - * Note that since lwIP may only be initialized once, and doesn't itself provide a shutdown mechanism, lwIP - * itself may still consume resources. - * - * It is however safe to call \ref lwip_freertos_init again later. - * - * \param context the async_context the lwip_freertos support was added to via \ref lwip_freertos_init -*/ -void lwip_freertos_deinit(async_context_t *context); - -#ifdef __cplusplus -} -#endif -#endif \ No newline at end of file diff --git a/lib/main/pico-sdk/rp2_common/pico_lwip/include/pico/lwip_nosys.h b/lib/main/pico-sdk/rp2_common/pico_lwip/include/pico/lwip_nosys.h deleted file mode 100644 index e87ddf3c47..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_lwip/include/pico/lwip_nosys.h +++ /dev/null @@ -1,50 +0,0 @@ -/* - * Copyright (c) 2022 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _PICO_LWIP_NOSYS_H -#define _PICO_LWIP_NOSYS_H - -#include "pico.h" -#include "pico/async_context.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** \file pico/lwip_nosys.h -* \defgroup pico_lwip_nosys pico_lwip_nosys -* \ingroup pico_lwip -* \brief Glue library for integration lwIP in \c NO_SYS=1 mode with the SDK -* -* Simple \c init and \c deinit are all that is required to hook up lwIP via an \ref async_context instance. -*/ - -/*! \brief Initializes lwIP (NO_SYS=1 mode) support support using the provided async_context -* \ingroup pico_lwip_nosys -* -* If the initialization succeeds, \ref lwip_nosys_deinit() can be called to shutdown lwIP support -* -* \param context the async_context instance that provides the abstraction for handling asynchronous work. -* \return true if the initialization succeeded -*/ -bool lwip_nosys_init(async_context_t *context); - -/*! \brief De-initialize lwIP (NO_SYS=1 mode) support - * \ingroup pico_lwip_nosys - * - * Note that since lwIP may only be initialized once, and doesn't itself provide a shutdown mechanism, lwIP - * itself may still consume resources - * - * It is however safe to call \ref lwip_nosys_init again later. - * - * \param context the async_context the lwip_nosys support was added to via \ref lwip_nosys_init -*/ -void lwip_nosys_deinit(async_context_t *context); - -#ifdef __cplusplus -} -#endif -#endif \ No newline at end of file diff --git a/lib/main/pico-sdk/rp2_common/pico_lwip/lwip.BUILD b/lib/main/pico-sdk/rp2_common/pico_lwip/lwip.BUILD deleted file mode 100644 index 39b7ed2dd1..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_lwip/lwip.BUILD +++ /dev/null @@ -1,181 +0,0 @@ -load("@pico-sdk//bazel:defs.bzl", "incompatible_with_config") - -package(default_visibility = ["//visibility:public"]) - -# Some of the LWIP sys_arch.h and the lwip headers depend circularly on one -# another. Include them all in the same target. -cc_library( - name = "pico_lwip_headers", - hdrs = glob(["**/*.h"]), - includes = [ - "contrib/ports/freertos/include/arch", - "src/include", - ], - visibility = ["//visibility:private"], - deps = [ - "@pico-sdk//bazel/config:PICO_LWIP_CONFIG", - "@pico-sdk//src/rp2_common/pico_lwip:pico_lwip_config", - ], -) - -cc_library( - name = "pico_lwip_core", - srcs = glob(["src/core/*.c"]), - target_compatible_with = incompatible_with_config( - "@pico-sdk//bazel/constraint:pico_lwip_config_unset", - ), - deps = [ - ":pico_lwip_headers", - ] + select({ - "@pico-sdk//bazel/constraint:pico_freertos_unset": [], - "//conditions:default": [ - ":pico_lwip_contrib_freertos", - ], - }), -) - -cc_library( - name = "pico_lwip_core4", - srcs = glob(["src/core/ipv4/*.c"]), - deps = [":pico_lwip_core"], -) - -cc_library( - name = "pico_lwip_core6", - srcs = glob(["src/core/ipv6/*.c"]), - deps = [":pico_lwip_core"], -) - -cc_library( - name = "pico_lwip_api", - srcs = glob(["src/api/*.c"]), - deps = [":pico_lwip_core"], -) - -cc_library( - name = "pico_lwip_netif", - srcs = [ - "src/netif/bridgeif.c", - "src/netif/bridgeif_fdb.c", - "src/netif/ethernet.c", - "src/netif/slipif.c", - ], - deps = [":pico_lwip_core"], -) - -cc_library( - name = "pico_lwip_sixlowpan", - srcs = [ - "src/netif/lowpan6.c", - "src/netif/lowpan6_ble.c", - "src/netif/lowpan6_common.c", - "src/netif/zepif.c", - ], - deps = [":pico_lwip_core"], -) - -cc_library( - name = "pico_lwip_ppp", - srcs = glob(["src/netif/ppp/*/*.c"]), - deps = [":pico_lwip_core"], -) - -cc_library( - name = "pico_lwip_snmp", - srcs = glob( - ["src/apps/snmp/*.c"], - # mbedtls is provided through pico_lwip_mbedtls. - exclude = ["*mbedtls.c"], - ), - deps = [":pico_lwip_core"], -) - -cc_library( - name = "pico_lwip_http", - srcs = glob(["src/apps/http/*.c"]), - deps = [":pico_lwip_core"], -) - -cc_library( - name = "pico_lwip_makefsdata", - srcs = ["src/apps/http/makefsdata/makefsdata.c"], - deps = [":pico_lwip_core"], -) - -cc_library( - name = "pico_lwip_iperf", - srcs = ["src/apps/lwiperf/lwiperf.c"], - deps = [":pico_lwip_core"], -) - -cc_library( - name = "pico_lwip_smtp", - srcs = ["src/apps/smtp/smtp.c"], - deps = [":pico_lwip_core"], -) - -cc_library( - name = "pico_lwip_sntp", - srcs = ["src/apps/sntp/sntp.c"], - deps = [":pico_lwip_core"], -) - -cc_library( - name = "pico_lwip_mdns", - srcs = glob(["src/apps/mdns/*.c"]), - deps = [":pico_lwip_core"], -) - -cc_library( - name = "pico_lwip_netbios", - srcs = ["src/apps/netbiosns/netbiosns.c"], - deps = [":pico_lwip_core"], -) - -cc_library( - name = "pico_lwip_tftp", - srcs = ["src/apps/tftp/tftp.c"], - deps = [":pico_lwip_core"], -) - -cc_library( - name = "pico_lwip_mbedtls", - srcs = [ - "src/apps/altcp_tls/altcp_tls_mbedtls.c", - "src/apps/altcp_tls/altcp_tls_mbedtls_mem.c", - "src/apps/snmp/snmpv3_mbedtls.c", - ], - deps = [":pico_lwip_core"], -) - -cc_library( - name = "pico_lwip_mqttt", - srcs = ["src/apps/mqtt/mqtt.c"], - deps = [":pico_lwip_core"], -) - -cc_library( - name = "pico_lwip", - deps = [ - ":pico_lwip_api", - ":pico_lwip_core", - ":pico_lwip_core4", - ":pico_lwip_core6", - ":pico_lwip_netif", - ":pico_lwip_ppp", - ":pico_lwip_sixlowpan", - ], -) - -cc_library( - name = "pico_lwip_contrib_freertos", - srcs = ["contrib/ports/freertos/sys_arch.c"], - includes = ["contrib/ports/freertos/include"], - target_compatible_with = incompatible_with_config( - "@pico-sdk//bazel/constraint:pico_freertos_unset", - ), - deps = [ - ":pico_lwip_headers", - "@pico-sdk//bazel/config:PICO_FREERTOS_LIB", - ], -) diff --git a/lib/main/pico-sdk/rp2_common/pico_lwip/lwip_freertos.c b/lib/main/pico-sdk/rp2_common/pico_lwip/lwip_freertos.c deleted file mode 100644 index 7d28d9716e..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_lwip/lwip_freertos.c +++ /dev/null @@ -1,63 +0,0 @@ -/* - * Copyright (c) 2022 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "pico/async_context.h" -#include "pico/time.h" -#include "lwip/tcpip.h" -#include "lwip/timeouts.h" - -#include "FreeRTOS.h" -#include "semphr.h" - -#if NO_SYS -#error lwip_freertos_async_context_bindings requires NO_SYS=0 -#endif - -static async_context_t * volatile lwip_context; -// lwIP tcpip_task cannot be shutdown, so we block it when we are de-initialized. -static SemaphoreHandle_t tcpip_task_blocker; - -static void tcpip_init_done(void *param) { - xSemaphoreGive((SemaphoreHandle_t)param); -} - -bool lwip_freertos_init(async_context_t *context) { - assert(!lwip_context); - lwip_context = context; - static bool done_lwip_init; - if (!done_lwip_init) { - done_lwip_init = true; - SemaphoreHandle_t init_sem = xSemaphoreCreateBinary(); - tcpip_task_blocker = xSemaphoreCreateBinary(); - tcpip_init(tcpip_init_done, init_sem); - xSemaphoreTake(init_sem, portMAX_DELAY); - vSemaphoreDelete(init_sem); - } else { - xSemaphoreGive(tcpip_task_blocker); - } - return true; -} - -static uint32_t clear_lwip_context(__unused void *param) { - lwip_context = NULL; - return 0; -} - -void lwip_freertos_deinit(__unused async_context_t *context) { - // clear the lwip context under lock as lwIP may still be running in tcpip_task - async_context_execute_sync(context, clear_lwip_context, NULL); -} - -void pico_lwip_custom_lock_tcpip_core(void) { - while (!lwip_context) { - xSemaphoreTake(tcpip_task_blocker, portMAX_DELAY); - } - async_context_acquire_lock_blocking(lwip_context); -} - -void pico_lwip_custom_unlock_tcpip_core(void) { - async_context_release_lock(lwip_context); -} diff --git a/lib/main/pico-sdk/rp2_common/pico_lwip/lwip_nosys.c b/lib/main/pico-sdk/rp2_common/pico_lwip/lwip_nosys.c deleted file mode 100644 index 856affa568..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_lwip/lwip_nosys.c +++ /dev/null @@ -1,74 +0,0 @@ -/* - * Copyright (c) 2022 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "pico/async_context.h" - -#include -#include "lwip/timeouts.h" - -static void update_next_timeout(async_context_t *context, async_when_pending_worker_t *worker); -static void lwip_timeout_reached(async_context_t *context, async_at_time_worker_t *worker); - -static async_when_pending_worker_t always_pending_update_timeout_worker = { - .do_work = update_next_timeout -}; - -static async_at_time_worker_t lwip_timeout_worker = { - .do_work = lwip_timeout_reached, -}; - -static void lwip_timeout_reached(__unused async_context_t *context, __unused async_at_time_worker_t *worker) { - assert(worker == &lwip_timeout_worker); - sys_check_timeouts(); -} - -static void update_next_timeout(async_context_t *context, async_when_pending_worker_t *worker) { - assert(worker == &always_pending_update_timeout_worker); - // we want to run on every execution of the helper to re-reflect any changes - // to the underlying lwIP timers which may have happened in the interim - // (note that worker will be called on every outermost exit of the async_context - // lock, and lwIP timers should not be modified whilst not holding the lock. - worker->work_pending = true; - uint32_t sleep_ms = sys_timeouts_sleeptime(); - if (sleep_ms == SYS_TIMEOUTS_SLEEPTIME_INFINITE) { - lwip_timeout_worker.next_time = at_the_end_of_time; - } else { - lwip_timeout_worker.next_time = make_timeout_time_ms(sleep_ms); - } - async_context_add_at_time_worker(context, &lwip_timeout_worker); -} - -bool lwip_nosys_init(async_context_t *context) { - static bool done_lwip_init; - if (!done_lwip_init) { - lwip_init(); - done_lwip_init = true; - } - // we want the worker to be called on every async helper run (starting with the next) - always_pending_update_timeout_worker.work_pending = true; - async_context_add_when_pending_worker(context, &always_pending_update_timeout_worker); - return true; -} - -void lwip_nosys_deinit(async_context_t *context) { - async_context_remove_at_time_worker(context, &lwip_timeout_worker); - async_context_remove_when_pending_worker(context, &always_pending_update_timeout_worker); -} - -#if NO_SYS -/* lwip has provision for using a mutex, when applicable */ -sys_prot_t sys_arch_protect(void) { - return 0; -} - -void sys_arch_unprotect(__unused sys_prot_t pval) { -} - -/* lwip needs a millisecond time source, and the TinyUSB board support code has one available */ -uint32_t sys_now(void) { - return to_ms_since_boot(get_absolute_time()); -} -#endif \ No newline at end of file diff --git a/lib/main/pico-sdk/rp2_common/pico_lwip/tools/makefsdata.py b/lib/main/pico-sdk/rp2_common/pico_lwip/tools/makefsdata.py deleted file mode 100644 index 88fca43a64..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_lwip/tools/makefsdata.py +++ /dev/null @@ -1,159 +0,0 @@ -#!/usr/bin/env python3 -import argparse -import mimetypes -from pathlib import Path -import re - -response_types = { - 200: "HTTP/1.0 200 OK", - 400: "HTTP/1.0 400 Bad Request", - 404: "HTTP/1.0 404 File not found", - 501: "HTTP/1.0 501 Not Implemented", -} - -PAYLOAD_ALIGNMENT = 4 -HTTPD_SERVER_AGENT = "lwIP/2.2.0d (http://savannah.nongnu.org/projects/lwip)" -LWIP_HTTPD_SSI_EXTENSIONS = [".shtml", ".shtm", ".ssi", ".xml", ".json"] - -def process_file(input_dir, file): - results = [] - - # Check content type - content_type, _ = mimetypes.guess_type(file) - if content_type is None: - content_type = "application/octet-stream" - - # file name - data = f"/{file.relative_to(input_dir)}\x00" - comment = f"\"/{file.relative_to(input_dir)}\" ({len(data)} chars)" - while(len(data) % PAYLOAD_ALIGNMENT != 0): - data += "\x00" - results.append({'data': bytes(data, "utf-8"), 'comment': comment}); - - # Header - response_type = 200 - for response_id in response_types: - if file.name.startswith(f"{response_id}."): - response_type = response_id - break - data = f"{response_types[response_type]}\r\n" - comment = f"\"{response_types[response_type]}\" ({len(data)} chars)" - results.append({'data': bytes(data, "utf-8"), 'comment': comment}); - - # user agent - data = f"Server: {HTTPD_SERVER_AGENT}\r\n" - comment = f"\"Server: {HTTPD_SERVER_AGENT}\" ({len(data)} chars)" - results.append({'data': bytes(data, "utf-8"), 'comment': comment}); - - if file.suffix not in LWIP_HTTPD_SSI_EXTENSIONS: - # content length - file_size = file.stat().st_size - data = f"Content-Length: {file_size}\r\n" - comment = f"\"Content-Length: {file_size}\" ({len(data)} chars)" - results.append({'data': bytes(data, "utf-8"), 'comment': comment}); - - # content type - data = f"Content-Type: {content_type}\r\n\r\n" - comment = f"\"Content-Type: {content_type}\" ({len(data)} chars)" - results.append({'data': bytes(data, "utf-8"), 'comment': comment}); - - # file contents - data = file.read_bytes() - comment = f"raw file data ({len(data)} bytes)" - results.append({'data': data, 'comment': comment}); - - return results; - -def process_file_list(fd, input): - data = [] - fd.write("#include \"lwip/apps/fs.h\"\n") - fd.write("\n") - # generate the page contents - input_dir = None - for name in input: - file = Path(name) - if not file.is_file(): - raise RuntimeError(f"File not found: {name}") - # Take the input directory from the first file - if input_dir is None: - input_dir = file.parent - results = process_file(input_dir, file) - - # make a variable name - var_name = str(file.relative_to(input_dir)) - var_name = re.sub(r"\W+", "_", var_name, flags=re.ASCII) - - # Add a suffix if the variable name is used already - if any(d["data_var"] == f"data_{var_name}" for d in data): - var_name += f"_{len(data)}" - - data_var = f"data_{var_name}" - file_var = f"file_{var_name}" - - # variable containing the raw data - fd.write(f"static const unsigned char {data_var}[] = {{\n") - for entry in results: - fd.write(f"\n /* {entry['comment']} */\n") - byte_count = 0; - for b in entry['data']: - if byte_count % 16 == 0: - fd.write(" ") - byte_count += 1 - fd.write(f"0x{b:02x},") - if byte_count % 16 == 0: - fd.write("\n") - if byte_count % 16 != 0: - fd.write("\n") - fd.write(f"}};\n\n") - - # set the flags - flags = "FS_FILE_FLAGS_HEADER_INCLUDED" - if file.suffix not in LWIP_HTTPD_SSI_EXTENSIONS: - flags += " | FS_FILE_FLAGS_HEADER_PERSISTENT" - else: - flags += " | FS_FILE_FLAGS_SSI" - - # add variable details to the list - data.append({'data_var': data_var, 'file_var': file_var, 'name_size': len(results[0]['data']), 'flags': flags}) - - # generate the page details - last_var = "NULL" - for entry in data: - fd.write(f"const struct fsdata_file {entry['file_var']}[] = {{{{\n") - fd.write(f" {last_var},\n") - fd.write(f" {entry['data_var']},\n") - fd.write(f" {entry['data_var']} + {entry['name_size']},\n") - fd.write(f" sizeof({entry['data_var']}) - {entry['name_size']},\n") - fd.write(f" {entry['flags']},\n") - fd.write(f"}}}};\n\n") - last_var = entry['file_var'] - fd.write(f"#define FS_ROOT {last_var}\n") - fd.write(f"#define FS_NUMFILES {len(data)}\n") - -def run_tool(): - parser = argparse.ArgumentParser(prog="makefsdata.py", description="Generates a source file for the lwip httpd server") - parser.add_argument( - "-i", - "--input", - help="input files to add as http content", - required=True, - nargs='+' - ) - parser.add_argument( - "-o", - "--output", - help="name of the source file to generate", - required=True, - ) - args = parser.parse_args() - print(args.input) - - mimetypes.init() - for ext in [".shtml", ".shtm", ".ssi"]: - mimetypes.add_type("text/html", ext) - - with open(args.output, "w") as fd: - process_file_list(fd, args.input) - -if __name__ == "__main__": - run_tool() diff --git a/lib/main/pico-sdk/rp2_common/pico_malloc/include/pico/malloc.h b/lib/main/pico-sdk/rp2_common/pico_malloc/include/pico/malloc.h deleted file mode 100644 index c498ea064a..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_malloc/include/pico/malloc.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _PICO_MALLOC_H -#define _PICO_MALLOC_H - -/** \file malloc.h -* \defgroup pico_malloc pico_malloc -* -* \brief Multi-core safety for malloc, calloc and free -* -* This library does not provide any additional functions -*/ - -// PICO_CONFIG: PICO_USE_MALLOC_MUTEX, Whether to protect malloc etc with a mutex, type=bool, default=1 with pico_multicore, 0 otherwise, group=pico_malloc -#if LIB_PICO_MULTICORE && !defined(PICO_USE_MALLOC_MUTEX) -#define PICO_USE_MALLOC_MUTEX 1 -#endif - -// PICO_CONFIG: PICO_MALLOC_PANIC, Enable/disable panic when an allocation failure occurs, type=bool, default=1, group=pico_malloc -#ifndef PICO_MALLOC_PANIC -#define PICO_MALLOC_PANIC 1 -#endif - -// PICO_CONFIG: PICO_DEBUG_MALLOC, Enable/disable debug printf from malloc, type=bool, default=0, group=pico_malloc -#ifndef PICO_DEBUG_MALLOC -#define PICO_DEBUG_MALLOC 0 -#endif - -// PICO_CONFIG: PICO_DEBUG_MALLOC_LOW_WATER, Define the lower bound for allocation addresses to be printed by PICO_DEBUG_MALLOC, min=0, default=0, group=pico_malloc -#ifndef PICO_DEBUG_MALLOC_LOW_WATER -#define PICO_DEBUG_MALLOC_LOW_WATER 0 -#endif - -#endif \ No newline at end of file diff --git a/lib/main/pico-sdk/rp2_common/pico_malloc/malloc.c b/lib/main/pico-sdk/rp2_common/pico_malloc/malloc.c deleted file mode 100644 index ca5411fc3c..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_malloc/malloc.c +++ /dev/null @@ -1,100 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include "pico.h" -#include "pico/malloc.h" - -#if PICO_USE_MALLOC_MUTEX -#include "pico/mutex.h" -auto_init_mutex(malloc_mutex); -#endif - -#if PICO_DEBUG_MALLOC -#include -#endif - -extern void *REAL_FUNC(malloc)(size_t size); -extern void *REAL_FUNC(calloc)(size_t count, size_t size); -extern void *REAL_FUNC(realloc)(void *mem, size_t size); -extern void REAL_FUNC(free)(void *mem); - -extern char __StackLimit; /* Set by linker. */ - -static inline void check_alloc(__unused void *mem, __unused uint size) { -#if PICO_MALLOC_PANIC - if (!mem || (((char *)mem) + size) > &__StackLimit) { - panic("Out of memory"); - } -#endif -} - -void *WRAPPER_FUNC(malloc)(size_t size) { -#if PICO_USE_MALLOC_MUTEX - mutex_enter_blocking(&malloc_mutex); -#endif - void *rc = REAL_FUNC(malloc)(size); -#if PICO_USE_MALLOC_MUTEX - mutex_exit(&malloc_mutex); -#endif -#if PICO_DEBUG_MALLOC - if (!rc) { - printf("malloc %d failed to allocate memory\n", (uint) size); - } else if (((uint8_t *)rc) + size > (uint8_t*)PICO_DEBUG_MALLOC_LOW_WATER) { - printf("malloc %d %p->%p\n", (uint) size, rc, ((uint8_t *) rc) + size); - } -#endif - check_alloc(rc, size); - return rc; -} - -void *WRAPPER_FUNC(calloc)(size_t count, size_t size) { -#if PICO_USE_MALLOC_MUTEX - mutex_enter_blocking(&malloc_mutex); -#endif - void *rc = REAL_FUNC(calloc)(count, size); -#if PICO_USE_MALLOC_MUTEX - mutex_exit(&malloc_mutex); -#endif -#if PICO_DEBUG_MALLOC - if (!rc) { - printf("calloc %d failed to allocate memory\n", (uint) (count * size)); - } else if (((uint8_t *)rc) + count * size > (uint8_t*)PICO_DEBUG_MALLOC_LOW_WATER) { - printf("calloc %d %p->%p\n", (uint) (count * size), rc, ((uint8_t *) rc) + size); - } -#endif - check_alloc(rc, count * size); - return rc; -} - -void *WRAPPER_FUNC(realloc)(void *mem, size_t size) { -#if PICO_USE_MALLOC_MUTEX - mutex_enter_blocking(&malloc_mutex); -#endif - void *rc = REAL_FUNC(realloc)(mem, size); -#if PICO_USE_MALLOC_MUTEX - mutex_exit(&malloc_mutex); -#endif -#if PICO_DEBUG_MALLOC - if (!rc) { - printf("realloc %d failed to allocate memory\n", (uint) size); - } else if (((uint8_t *)rc) + size > (uint8_t*)PICO_DEBUG_MALLOC_LOW_WATER) { - printf("realloc %p %d->%p\n", mem, (uint) size, rc); - } -#endif - check_alloc(rc, size); - return rc; -} - -void WRAPPER_FUNC(free)(void *mem) { -#if PICO_USE_MALLOC_MUTEX - mutex_enter_blocking(&malloc_mutex); -#endif - REAL_FUNC(free)(mem); -#if PICO_USE_MALLOC_MUTEX - mutex_exit(&malloc_mutex); -#endif -} diff --git a/lib/main/pico-sdk/rp2_common/pico_mbedtls/include/sha256_alt.h b/lib/main/pico-sdk/rp2_common/pico_mbedtls/include/sha256_alt.h deleted file mode 100644 index b6658b2a78..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_mbedtls/include/sha256_alt.h +++ /dev/null @@ -1,16 +0,0 @@ -/* - * Copyright (c) 2024 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef PICO_MBEDTLS_SHA256_ALT_H -#define PICO_MBEDTLS_SHA256_ALT_H - -#if LIB_PICO_SHA256 -#include "pico/sha256.h" - -typedef struct pico_sha256_state mbedtls_sha256_context; -#endif // PICO_RP2350 - -#endif diff --git a/lib/main/pico-sdk/rp2_common/pico_mbedtls/pico_mbedtls.c b/lib/main/pico-sdk/rp2_common/pico_mbedtls/pico_mbedtls.c deleted file mode 100644 index 3279a42d17..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_mbedtls/pico_mbedtls.c +++ /dev/null @@ -1,57 +0,0 @@ -/* - * Copyright (c) 2024 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include "pico.h" -#include "pico/rand.h" -#include "mbedtls/sha256.h" -#include "common.h" - -/* Function to feed mbedtls entropy. */ -int mbedtls_hardware_poll(void *data __unused, unsigned char *output, size_t len, size_t *olen) { - *olen = 0; - while(*olen < len) { - uint64_t rand_data = get_rand_64(); - size_t to_copy = MIN(len, sizeof(rand_data)); - memcpy(output + *olen, &rand_data, to_copy); - *olen += to_copy; - } - return 0; -} - -#ifdef MBEDTLS_SHA256_ALT -#if !LIB_PICO_SHA256 -#error SHA256 hardware acceleration not supported -#endif - -// PICO_CONFIG: PICO_MBEDTLS_SHA256_ALT_USE_DMA, Whether to use DMA for writing to hardware for the mbedtls SHA-256 hardware acceleration, type=int, default=1, group=pico_stdlib -#ifndef PICO_MBEDTLS_SHA256_ALT_USE_DMA -#define PICO_MBEDTLS_SHA256_ALT_USE_DMA 1 -#endif - -void mbedtls_sha256_init(__unused mbedtls_sha256_context *ctx) { -} - -void mbedtls_sha256_free(__unused mbedtls_sha256_context *ctx) { -} - -int mbedtls_sha256_starts_ret(mbedtls_sha256_context *ctx, int is224) { - hard_assert(!is224); // that's annoying - return pico_sha256_start_blocking(ctx, SHA256_BIG_ENDIAN, PICO_MBEDTLS_SHA256_ALT_USE_DMA); -} - -int mbedtls_sha256_update_ret(mbedtls_sha256_context *ctx, const unsigned char *input, size_t ilen) { - pico_sha256_update_blocking(ctx, input, ilen); - return 0; -} - -int mbedtls_sha256_finish_ret( mbedtls_sha256_context *ctx, unsigned char output[32]) { - sha256_result_t result; - pico_sha256_finish(ctx, &result); - memcpy(output, result.bytes, 32); - return 0; -} -#endif // MBEDTLS_SHA256_ALT diff --git a/lib/main/pico-sdk/rp2_common/pico_mem_ops/include/pico/mem_ops.h b/lib/main/pico-sdk/rp2_common/pico_mem_ops/include/pico/mem_ops.h deleted file mode 100644 index 978d3b3083..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_mem_ops/include/pico/mem_ops.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _PICO_MEM_OPS_H -#define _PICO_MEM_OPS_H - -#include "pico/types.h" - -/** \file mem_ops.h - * \defgroup pico_mem_ops pico_mem_ops - * - * \brief Provides optimized replacement implementations of the compiler built-in memcpy, memset and related functions - * - * The functions include: - * - memset, memcpy - * - __aeabi_memset, __aeabi_memset4, __aeabi_memset8, __aeabi_memcpy, __aeabi_memcpy4, __aeabi_memcpy8 - * - * This library does not provide any additional functions - */ -#endif \ No newline at end of file diff --git a/lib/main/pico-sdk/rp2_common/pico_mem_ops/mem_ops.c b/lib/main/pico-sdk/rp2_common/pico_mem_ops/mem_ops.c deleted file mode 100644 index 4047d231bc..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_mem_ops/mem_ops.c +++ /dev/null @@ -1,7 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "pico/mem_ops.h" diff --git a/lib/main/pico-sdk/rp2_common/pico_mem_ops/mem_ops_aeabi.S b/lib/main/pico-sdk/rp2_common/pico_mem_ops/mem_ops_aeabi.S deleted file mode 100644 index 3af1378b02..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_mem_ops/mem_ops_aeabi.S +++ /dev/null @@ -1,98 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "pico/asm_helper.S" -#include "pico/bootrom.h" -#include "pico/runtime_init.h" - -pico_default_asm_setup - -PICO_RUNTIME_INIT_FUNC_RUNTIME(__aeabi_mem_init, PICO_RUNTIME_INIT_AEABI_MEM_OPS) - -.macro mem_section name -#if PICO_MEM_IN_RAM -.section RAM_SECTION_NAME(\name), "ax" -#else -.section SECTION_NAME(\name), "ax" -#endif -.endm - -.equ MEMSET, 0 -.equ MEMCPY, 4 -.equ MEMSET4, 8 -.equ MEMCPY4, 12 -.equ MEM_FUNC_COUNT, 4 - -# NOTE: All code sections are placed in RAM (at the expense of some veneer cost for calls from flash) because -# otherwise code using basic c division operators will require XIP flash access. - -.section .data.aeabi_mem_funcs -.global aeabi_mem_funcs, aeabi_mem_funcs_end - -.align 2 -aeabi_mem_funcs: - .word ROM_FUNC_MEMSET - .word ROM_FUNC_MEMCPY - .word ROM_FUNC_MEMSET4 - .word ROM_FUNC_MEMCPY44 -aeabi_mem_funcs_end: - -.section .text -regular_func __aeabi_mem_init - ldr r0, =aeabi_mem_funcs - movs r1, #MEM_FUNC_COUNT - ldr r3, =rom_funcs_lookup - bx r3 - -# lump them both together because likely both to be used, in which case doing so saves 1 word -# and it only costs 1 word if not - -// Note from Run-time ABI for the ARM architecture 4.3.4: -// If there is an attached device with efficient memory copying or clearing operations -// (such as a DMA engine), its device supplement specifies whether it may be used in -// implementations of these functions and what effect such use has on the device’s state. - -mem_section aeabi_memset_memcpy - -wrapper_func __aeabi_memset - // 2nd/3rd args are reversed - eors r2, r1 - eors r1, r2 - eors r2, r1 - ldr r3, =aeabi_mem_funcs - ldr r3, [r3, #MEMSET] - bx r3 - -wrapper_func __aeabi_memset4 -wrapper_func __aeabi_memset8 - // 2nd/3rd args are reversed - eors r2, r1 - eors r1, r2 - eors r2, r1 - ldr r3, =aeabi_mem_funcs - ldr r3, [r3, #MEMSET4] - bx r3 - -wrapper_func __aeabi_memcpy4 -wrapper_func __aeabi_memcpy8 - ldr r3, =aeabi_mem_funcs - ldr r3, [r3, #MEMCPY4] - bx r3 - -mem_section memset - -wrapper_func memset - ldr r3, =aeabi_mem_funcs - ldr r3, [r3, #MEMSET] - bx r3 - -mem_section memcpy -wrapper_func __aeabi_memcpy -wrapper_func memcpy - ldr r3, =aeabi_mem_funcs - ldr r3, [r3, #MEMCPY] - bx r3 - diff --git a/lib/main/pico-sdk/rp2_common/pico_multicore/include/pico/multicore.h b/lib/main/pico-sdk/rp2_common/pico_multicore/include/pico/multicore.h deleted file mode 100644 index aa7bb5d71f..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_multicore/include/pico/multicore.h +++ /dev/null @@ -1,514 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _PICO_MULTICORE_H -#define _PICO_MULTICORE_H - -#include "pico/types.h" -#include "pico/sync.h" -#include "hardware/structs/sio.h" - -#ifdef __cplusplus -extern "C" { -#endif - -// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_PICO_MULTICORE, Enable/disable assertions in the pico_multicore module, type=bool, default=0, group=pico_multicore -#ifndef PARAM_ASSERTIONS_ENABLED_PICO_MULTICORE -#define PARAM_ASSERTIONS_ENABLED_PICO_MULTICORE 0 -#endif - -/** \file multicore.h - * \defgroup pico_multicore pico_multicore - * \brief Adds support for running code on, and interacting with the second processor core (core 1). - * - * \subsection multicore_example Example - * \addtogroup pico_multicore - * \include multicore.c -*/ - -// PICO_CONFIG: PICO_CORE1_STACK_SIZE, Minimum amount of stack space reserved in the linker script for core 1, min=0x100, max=0x10000, default=PICO_STACK_SIZE (0x800), group=pico_multicore -#ifndef PICO_CORE1_STACK_SIZE -#ifdef PICO_STACK_SIZE -#define PICO_CORE1_STACK_SIZE PICO_STACK_SIZE -#else -#define PICO_CORE1_STACK_SIZE 0x800 -#endif -#endif - -/** - * \def SIO_FIFO_IRQ_NUM(core) - * \ingroup pico_multicore - * \hideinitializer - * \brief Returns the \ref irq_num_t for the FIFO IRQ on the given core. - * - * \if rp2040_specific - * On RP2040 each core has a different IRQ number: `SIO_IRQ_PROC0` and `SIO_IRQ_PROC1`. - * \endif - * \if rp2350_specific - * On RP2350 both cores share the same irq number (`SIO_IRQ_PROC`) just with a different SIO - * interrupt output routed to that IRQ input on each core. - * \endif - * - * Note this macro is intended to resolve at compile time, and does no parameter checking - */ -#ifndef SIO_FIFO_IRQ_NUM -#if !PICO_RP2040 -#define SIO_FIFO_IRQ_NUM(core) SIO_IRQ_FIFO -#else -static_assert(SIO_IRQ_PROC1 == SIO_IRQ_PROC0 + 1, ""); -#define SIO_FIFO_IRQ_NUM(core) (SIO_IRQ_PROC0 + (core)) -#endif -#endif - -/*! \brief Reset core 1 - * \ingroup pico_multicore - * - * This function can be used to reset core 1 into its initial state (ready for launching code against via \ref multicore_launch_core1 and similar methods) - * - * \note this function should only be called from core 0 - */ -void multicore_reset_core1(void); - -/*! \brief Run code on core 1 - * \ingroup pico_multicore - * - * Wake up (a previously reset) core 1 and enter the given function on core 1 using the default core 1 stack (below core 0 stack). - * - * core 1 must previously have been reset either as a result of a system reset or by calling \ref multicore_reset_core1 - * - * core 1 will use the same vector table as core 0 - * - * \param entry Function entry point - * \see multicore_reset_core1 - */ -void multicore_launch_core1(void (*entry)(void)); - -/*! \brief Launch code on core 1 with stack - * \ingroup pico_multicore - * - * Wake up (a previously reset) core 1 and enter the given function on core 1 using the passed stack for core 1 - * - * core 1 must previously have been reset either as a result of a system reset or by calling \ref multicore_reset_core1 - * - * core 1 will use the same vector table as core 0 - * - * \param entry Function entry point - * \param stack_bottom The bottom (lowest address) of the stack - * \param stack_size_bytes The size of the stack in bytes (must be a multiple of 4) - * \see multicore_reset_core1 - */ -void multicore_launch_core1_with_stack(void (*entry)(void), uint32_t *stack_bottom, size_t stack_size_bytes); - -/*! \brief Launch code on core 1 with no stack protection - * \ingroup pico_multicore - * - * Wake up (a previously reset) core 1 and start it executing with a specific entry point, stack pointer - * and vector table. - * - * This is a low level function that does not provide a stack guard even if USE_STACK_GUARDS is defined - * - * core 1 must previously have been reset either as a result of a system reset or by calling \ref multicore_reset_core1 - * - * \param entry Function entry point - * \param sp Pointer to the top of the core 1 stack - * \param vector_table address of the vector table to use for core 1 - * \see multicore_reset_core1 - */ -void multicore_launch_core1_raw(void (*entry)(void), uint32_t *sp, uint32_t vector_table); - -/*! - * \defgroup multicore_fifo fifo - * \ingroup pico_multicore - * \brief Functions for the inter-core FIFOs - * - * RP-series microcontrollers contains two FIFOs for passing data, messages or ordered events between the two cores. Each FIFO - * is 32 bits wide, and 8 entries deep on the RP2040, and 4 entries deep on the RP2350. One of the FIFOs can only be written by - * core 0, and read by core 1. The other can only be written by core 1, and read by core 0. - * - * \note The inter-core FIFOs are a very precious resource and are frequently used for SDK functionality (e.g. during - * core 1 launch or by the \ref multicore_lockout functions). Additionally they are often required for the exclusive use - * of an RTOS (e.g. FreeRTOS SMP). For these reasons it is suggested that you do not use the FIFO for your own purposes - * unless none of the above concerns apply; the majority of cases for transferring data between cores can be eqaully - * well handled by using a \ref queue - */ - -/*! \brief Check the read FIFO to see if there is data available (sent by the other core) - * \ingroup multicore_fifo - * - * See the note in the \ref multicore_fifo section for considerations regarding use of the inter-core FIFOs - * - * \return true if the FIFO has data in it, false otherwise - */ -static inline bool multicore_fifo_rvalid(void) { - return sio_hw->fifo_st & SIO_FIFO_ST_VLD_BITS; -} - -/*! \brief Check the write FIFO to see if it has space for more data - * \ingroup multicore_fifo - * - * See the note in the \ref multicore_fifo section for considerations regarding use of the inter-core FIFOs - * - * @return true if the FIFO has room for more data, false otherwise - */ -static inline bool multicore_fifo_wready(void) { - return sio_hw->fifo_st & SIO_FIFO_ST_RDY_BITS; -} - -/*! \brief Push data on to the write FIFO (data to the other core). - * \ingroup multicore_fifo - * - * This function will block until there is space for the data to be sent. - * Use \ref multicore_fifo_wready() to check if it is possible to write to the - * FIFO if you don't want to block. - * - * See the note in the \ref multicore_fifo section for considerations regarding use of the inter-core FIFOs - * - * \param data A 32 bit value to push on to the FIFO - */ -void multicore_fifo_push_blocking(uint32_t data); - -/*! \brief Push data on to the write FIFO (data to the other core). - * \ingroup multicore_fifo - * - * This function will block until there is space for the data to be sent. - * Use multicore_fifo_wready() to check if it is possible to write to the - * FIFO if you don't want to block. - * - * See the note in the \ref multicore_fifo section for considerations regarding use of the inter-core FIFOs - * - * \param data A 32 bit value to push on to the FIFO - */ -static inline void multicore_fifo_push_blocking_inline(uint32_t data) { - // We wait for the fifo to have some space - while (!multicore_fifo_wready()) - tight_loop_contents(); - - sio_hw->fifo_wr = data; - - // Fire off an event to the other core - __sev(); -} - -/*! \brief Push data on to the write FIFO (data to the other core) with timeout. - * \ingroup multicore_fifo - * - * This function will block until there is space for the data to be sent - * or the timeout is reached - * - * \param data A 32 bit value to push on to the FIFO - * \param timeout_us the timeout in microseconds - * \return true if the data was pushed, false if the timeout occurred before data could be pushed - */ -bool multicore_fifo_push_timeout_us(uint32_t data, uint64_t timeout_us); - -/*! \brief Pop data from the read FIFO (data from the other core). - * \ingroup multicore_fifo - * - * This function will block until there is data ready to be read - * Use multicore_fifo_rvalid() to check if data is ready to be read if you don't - * want to block. - * - * See the note in the \ref multicore_fifo section for considerations regarding use of the inter-core FIFOs - * - * \return 32 bit data from the read FIFO. - */ -uint32_t multicore_fifo_pop_blocking(void); - -/*! \brief Pop data from the read FIFO (data from the other core). - * \ingroup multicore_fifo - * - * This function will block until there is data ready to be read - * Use multicore_fifo_rvalid() to check if data is ready to be read if you don't - * want to block. - * - * See the note in the \ref multicore_fifo section for considerations regarding use of the inter-core FIFOs - * - * \return 32 bit data from the read FIFO. - */ -static inline uint32_t multicore_fifo_pop_blocking_inline(void) { - // If nothing there yet, we wait for an event first, - // to try and avoid too much busy waiting - while (!multicore_fifo_rvalid()) - __wfe(); - - return sio_hw->fifo_rd; -} - -/*! \brief Pop data from the read FIFO (data from the other core) with timeout. - * \ingroup multicore_fifo - * - * This function will block until there is data ready to be read or the timeout is reached - * - * See the note in the \ref multicore_fifo section for considerations regarding use of the inter-core FIFOs - * - * \param timeout_us the timeout in microseconds - * \param out the location to store the popped data if available - * \return true if the data was popped and a value copied into `out`, false if the timeout occurred before data could be popped - */ -bool multicore_fifo_pop_timeout_us(uint64_t timeout_us, uint32_t *out); - -/*! \brief Discard any data in the read FIFO - * \ingroup multicore_fifo - * - * See the note in the \ref multicore_fifo section for considerations regarding use of the inter-core FIFOs - */ -static inline void multicore_fifo_drain(void) { - while (multicore_fifo_rvalid()) - (void) sio_hw->fifo_rd; -} - -/*! \brief Clear FIFO interrupt - * \ingroup multicore_fifo - * - * Note that this only clears an interrupt that was caused by the ROE or WOF flags. - * To clear the VLD flag you need to use one of the 'pop' or 'drain' functions. - * - * See the note in the \ref multicore_fifo section for considerations regarding use of the inter-core FIFOs - * - * \see multicore_fifo_get_status -*/ -static inline void multicore_fifo_clear_irq(void) { - // Write any value to clear the error flags - sio_hw->fifo_st = 0xff; -} - -/*! \brief Get FIFO statuses - * \ingroup multicore_fifo - * - * \return The statuses as a bitfield - * - * Bit | Description - * ----|------------ - * 3 | Sticky flag indicating the RX FIFO was read when empty (ROE). This read was ignored by the FIFO. - * 2 | Sticky flag indicating the TX FIFO was written when full (WOF). This write was ignored by the FIFO. - * 1 | Value is 1 if this core’s TX FIFO is not full (i.e. if FIFO_WR is ready for more data) - * 0 | Value is 1 if this core’s RX FIFO is not empty (i.e. if FIFO_RD is valid) - * - * See the note in the \ref multicore_fifo section for considerations regarding use of the inter-core FIFOs - * -*/ -static inline uint32_t multicore_fifo_get_status(void) { - return sio_hw->fifo_st; -} - -/*! - * \defgroup multicore_doorbell doorbell - * \ingroup pico_multicore - * \brief Functions related to doorbells which a core can use to raise IRQs on itself or the other core. - * - * \if (rp2040_specific && !combined_docs) - * The doorbell functionality is not available on RP2040. - * \endif - */ - -#if NUM_DOORBELLS -static inline void check_doorbell_num_param(__unused uint doorbell_num) { - invalid_params_if(PICO_MULTICORE, doorbell_num >= NUM_DOORBELLS); -} - -/*! \brief Cooperatively claim the use of this hardware alarm_num - * \ingroup multicore_doorbell - * - * This method hard asserts if the hardware alarm is currently claimed. - * - * \param doorbell_num the doorbell number to claim - * \param core_mask 0b01: core 0, 0b10: core 1, 0b11 both core 0 and core 1 - * \sa hardware_claiming - */ -void multicore_doorbell_claim(uint doorbell_num, uint core_mask); - -/*! \brief Cooperatively claim the use of this hardware alarm_num - * \ingroup multicore_doorbell - * - * This method attempts to claim an unused hardware alarm - * - * \param core_mask 0b01: core 0, 0b10: core 1, 0b11 both core 0 and core 1 - * \param required if true the function will panic if none are available - * \return the doorbell number claimed or -1 if required was false, and none are available - * \sa hardware_claiming - */ -int multicore_doorbell_claim_unused(uint core_mask, bool required); - -/*! \brief Cooperatively release the claim on use of this hardware alarm_num - * \ingroup multicore_doorbell - * - * \param doorbell_num the doorbell number to unclaim - * \param core_mask 0b01: core 0, 0b10: core 1, 0b11 both core 0 and core 1 - * \sa hardware_claiming - */ -void multicore_doorbell_unclaim(uint doorbell_num, uint core_mask); - -/*! \brief Activate the given doorbell on the other core - * \ingroup multicore_doorbell - * \param doorbell_num the doorbell number - */ -static inline void multicore_doorbell_set_other_core(uint doorbell_num) { - check_doorbell_num_param(doorbell_num); - sio_hw->doorbell_out_set = 1u << doorbell_num; -} - -/*! \brief Deactivate the given doorbell on the other core - * \ingroup multicore_doorbell - * \param doorbell_num the doorbell number - */ -static inline void multicore_doorbell_clear_other_core(uint doorbell_num) { - check_doorbell_num_param(doorbell_num); - sio_hw->doorbell_out_clr = 1u << doorbell_num; -} - -/*! \brief Activate the given doorbell on this core - * \ingroup multicore_doorbell - * \param doorbell_num the doorbell number - */ -static inline void multicore_doorbell_set_current_core(uint doorbell_num) { - check_doorbell_num_param(doorbell_num); - sio_hw->doorbell_in_set = 1u << doorbell_num; -} - -/*! \brief Deactivate the given doorbell on this core - * \ingroup multicore_doorbell - * \param doorbell_num the doorbell number - */ -static inline void multicore_doorbell_clear_current_core(uint doorbell_num) { - check_doorbell_num_param(doorbell_num); - sio_hw->doorbell_in_clr = 1u << doorbell_num; -} - -/*! \brief Determine if the given doorbell is active on the other core - * \ingroup multicore_doorbell - * \param doorbell_num the doorbell number - */ -static inline bool multicore_doorbell_is_set_current_core(uint doorbell_num) { - check_doorbell_num_param(doorbell_num); - return sio_hw->doorbell_in_set & (1u << doorbell_num); -} - -/*! \brief Determine if the given doorbell is active on the this core - * \ingroup multicore_doorbell - * \param doorbell_num the doorbell number - */ -static inline bool multicore_doorbell_is_set_other_core(uint doorbell_num) { - check_doorbell_num_param(doorbell_num); - return sio_hw->doorbell_out_set & (1u << doorbell_num); -} - -/** - * \def DOORBELL_IRQ_NUM(doorbell_num) - * \ingroup multicore_doorbell - * \hideinitializer - * \brief Returns the \ref irq_num_t for processor interrupts for the given doorbell number - * - * Note this macro is intended to resolve at compile time, and does no parameter checking - */ -#ifndef DOORBELL_IRQ_NUM -#define DOORBELL_IRQ_NUM(doorbell_num) SIO_IRQ_BELL -#endif - -static inline uint multicore_doorbell_irq_num(uint doorbell_num) { - check_doorbell_num_param(doorbell_num); - return DOORBELL_IRQ_NUM(doorbell_num); -} - -#endif - -/*! - * \defgroup multicore_lockout lockout - * \ingroup pico_multicore - * \brief Functions to enable one core to force the other core to pause execution in a known state - * - * Sometimes it is useful to enter a critical section on both cores at once. On a single - * core system a critical section can trivially be entered by disabling interrupts, however on a multi-core - * system that is not sufficient, and unless the other core is polling in some way, then it will need to be interrupted - * in order to cooperatively enter a blocked state. - * - * These "lockout" functions use the inter core FIFOs to cause an interrupt on one core from the other, and manage - * waiting for the other core to enter the "locked out" state. - * - * The usage is that the "victim" core ... i.e the core that can be "locked out" by the other core calls - * \ref multicore_lockout_victim_init to hook the FIFO interrupt. Note that either or both cores may do this. - * - * \note When "locked out" the victim core is paused (it is actually executing a tight loop with code in RAM) and has interrupts disabled. - * This makes the lockout functions suitable for use by code that wants to write to flash (at which point no code may be executing - * from flash) - * - * The core which wishes to lockout the other core calls \ref multicore_lockout_start_blocking or - * \ref multicore_lockout_start_timeout_us to interrupt the other "victim" core and wait for it to be in a - * "locked out" state. Once the lockout is no longer needed it calls \ref multicore_lockout_end_blocking or - * \ref multicore_lockout_end_timeout_us to release the lockout and wait for confirmation. - * - * \note Because multicore lockout uses the intercore FIFOs, the FIFOs cannot be used for any other purpose - */ - -/*! \brief Initialize the current core such that it can be a "victim" of lockout (i.e. forced to pause in a known state by the other core) - * \ingroup multicore_lockout - * - * This code hooks the intercore FIFO IRQ, and the FIFO may not be used for any other purpose after this. - */ -void multicore_lockout_victim_init(void); - -/*! \brief Determine if \ref multicore_lockout_victim_init() has been called on the specified core. - * \ingroup multicore_lockout - * - * \note this state persists even if the core is subsequently reset; therefore you are advised to - * always call \ref multicore_lockout_victim_init() again after resetting a core, which had previously - * been initialized. - * - * \param core_num the core number (0 or 1) - * \return true if \ref multicore_lockout_victim_init() has been called on the specified core, false otherwise. - */ -bool multicore_lockout_victim_is_initialized(uint core_num); - -/*! \brief Request the other core to pause in a known state and wait for it to do so - * \ingroup multicore_lockout - * - * The other (victim) core must have previously executed \ref multicore_lockout_victim_init() - * - * \note multicore_lockout_start_ functions are not nestable, and must be paired with a call to a corresponding - * \ref multicore_lockout_end_blocking - */ -void multicore_lockout_start_blocking(void); - -/*! \brief Request the other core to pause in a known state and wait up to a time limit for it to do so - * \ingroup multicore_lockout - * - * The other core must have previously executed \ref multicore_lockout_victim_init() - * - * \note multicore_lockout_start_ functions are not nestable, and must be paired with a call to a corresponding - * \ref multicore_lockout_end_blocking - * - * \param timeout_us the timeout in microseconds - * \return true if the other core entered the locked out state within the timeout, false otherwise - */ -bool multicore_lockout_start_timeout_us(uint64_t timeout_us); - -/*! \brief Release the other core from a locked out state amd wait for it to acknowledge - * \ingroup multicore_lockout - * - * \note The other core must previously have been "locked out" by calling a `multicore_lockout_start_` function - * from this core - */ -void multicore_lockout_end_blocking(void); - -/*! \brief Release the other core from a locked out state amd wait up to a time limit for it to acknowledge - * \ingroup multicore_lockout - * - * The other core must previously have been "locked out" by calling a `multicore_lockout_start_` function - * from this core - * - * \note be very careful using small timeout values, as a timeout here will leave the "lockout" functionality - * in a bad state. It is probably preferable to use \ref multicore_lockout_end_blocking anyway as if you have - * already waited for the victim core to enter the lockout state, then the victim core will be ready to exit - * the lockout state very quickly. - * - * \param timeout_us the timeout in microseconds - * \return true if the other core successfully exited locked out state within the timeout, false otherwise - */ -bool multicore_lockout_end_timeout_us(uint64_t timeout_us); - -#ifdef __cplusplus -} -#endif -#endif diff --git a/lib/main/pico-sdk/rp2_common/pico_multicore/multicore.c b/lib/main/pico-sdk/rp2_common/pico_multicore/multicore.c deleted file mode 100644 index 58c2ee2897..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_multicore/multicore.c +++ /dev/null @@ -1,385 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "pico/multicore.h" -#include "hardware/sync.h" -#include "hardware/irq.h" -#include "pico/runtime_init.h" -#ifdef __riscv -#include "hardware/riscv.h" -#else -#include "hardware/structs/scb.h" -#endif -#include "hardware/structs/sio.h" -#include "hardware/regs/psm.h" -#include "hardware/claim.h" - -#if !PICO_RP2040 -#ifndef __riscv -#include "hardware/structs/m33.h" -#endif -#endif - -// note that these are not reset by core reset, however for now, I think people resetting cores -// and then relying on multicore_lockout for that core without re-initializing, is probably -// something we can live with breaking. -// -// whilst we could clear this in core 1 reset path, that doesn't necessarily catch all, -// and means pulling in this array even if multicore_lockout is not used. -static bool lockout_victim_initialized[NUM_CORES]; - -void multicore_fifo_push_blocking(uint32_t data) { - multicore_fifo_push_blocking_inline(data); -} - -bool multicore_fifo_push_timeout_us(uint32_t data, uint64_t timeout_us) { - absolute_time_t end_time = make_timeout_time_us(timeout_us); - // We wait for the fifo to have some space - while (!multicore_fifo_wready()) { - tight_loop_contents(); - if (time_reached(end_time)) return false; - } - - sio_hw->fifo_wr = data; - - // Fire off an event to the other core - __sev(); - return true; -} - -uint32_t multicore_fifo_pop_blocking(void) { - return multicore_fifo_pop_blocking_inline(); -} - -bool multicore_fifo_pop_timeout_us(uint64_t timeout_us, uint32_t *out) { - absolute_time_t end_time = make_timeout_time_us(timeout_us); - // If nothing there yet, we wait for an event first, - // to try and avoid too much busy waiting - while (!multicore_fifo_rvalid()) { - if (best_effort_wfe_or_timeout(end_time)) return false; - } - - *out = sio_hw->fifo_rd; - return true; -} - -// Default stack for core1 ... if multicore_launch_core1 is not included then .stack1 section will be garbage collected -static uint32_t __attribute__((section(".stack1"))) core1_stack[PICO_CORE1_STACK_SIZE / sizeof(uint32_t)]; - -static void __attribute__ ((naked)) core1_trampoline(void) { -#ifdef __riscv - // Do not add function calls here, because we want to preserve the return - // address pointing back to the bootrom launch routine. - pico_default_asm( - "lw a0, 0(sp)\n" - "lw a1, 4(sp)\n" - "lw a2, 8(sp)\n" - "lw gp, 12(sp)\n" - "addi sp, sp, 16\n" - "jr a2\n" - ); -#else - pico_default_asm("pop {r0, r1, pc}"); -#endif -} - -int core1_wrapper(int (*entry)(void), void *stack_base) { -#if !PICO_RUNTIME_SKIP_INIT_PER_CORE_INSTALL_STACK_GUARD - // install core1 stack guard - runtime_init_per_core_install_stack_guard(stack_base); -#else - (void)stack_base; -#endif - runtime_run_per_core_initializers(); - return (*entry)(); -} - -void multicore_reset_core1(void) { - // Use atomic aliases just in case core 1 is also manipulating some PSM state - io_rw_32 *power_off = (io_rw_32 *) (PSM_BASE + PSM_FRCE_OFF_OFFSET); - io_rw_32 *power_off_set = hw_set_alias(power_off); - io_rw_32 *power_off_clr = hw_clear_alias(power_off); - - // Hard-reset core 1. - // Reading back confirms the core 1 reset is in the correct state, but also - // forces APB IO bridges to fence on any internal store buffering - *power_off_set = PSM_FRCE_OFF_PROC1_BITS; - while (!(*power_off & PSM_FRCE_OFF_PROC1_BITS)) tight_loop_contents(); - - // Allow for the fact that the caller may have already enabled the FIFO IRQ for their - // own purposes (expecting FIFO content after core 1 is launched). We must disable - // the IRQ during the handshake, then restore afterward - uint irq_num = SIO_FIFO_IRQ_NUM(0); - bool enabled = irq_is_enabled(irq_num); - irq_set_enabled(irq_num, false); - - // Bring core 1 back out of reset. It will drain its own mailbox FIFO, then push - // a 0 to our mailbox to tell us it has done this. - *power_off_clr = PSM_FRCE_OFF_PROC1_BITS; - - // check the pushed value - uint32_t value = multicore_fifo_pop_blocking(); - assert(value == 0); - (void) value; // silence warning - - // restore interrupt state - irq_set_enabled(irq_num, enabled); -} - -void multicore_launch_core1_with_stack(void (*entry)(void), uint32_t *stack_bottom, size_t stack_size_bytes) { - assert(!(stack_size_bytes & 3u)); - uint32_t *stack_ptr = stack_bottom + stack_size_bytes / sizeof(uint32_t); - // Push values onto top of stack for core1_trampoline -#ifdef __riscv - // On RISC-V we also need to initialise the global pointer - stack_ptr -= 4; - uint32_t vector_table = riscv_read_csr(mtvec); - asm volatile ("mv %0, gp" : "=r"(stack_ptr[3])); -#else - stack_ptr -= 3; - uint32_t vector_table = scb_hw->vtor; -#endif - stack_ptr[0] = (uintptr_t) entry; - stack_ptr[1] = (uintptr_t) stack_bottom; - stack_ptr[2] = (uintptr_t) core1_wrapper; -#if PICO_VTABLE_PER_CORE - #warning PICO_VTABLE_PER_CORE==1 is not currently supported in pico_multicore - panic_unsupported(); -#endif - multicore_launch_core1_raw(core1_trampoline, stack_ptr, vector_table); -} - -void multicore_launch_core1(void (*entry)(void)) { - extern uint32_t __StackOneBottom; - uint32_t *stack_limit = (uint32_t *) &__StackOneBottom; - // hack to reference core1_stack although that pointer is wrong.... core1_stack should always be <= stack_limit, if not boom! - uint32_t *stack = core1_stack <= stack_limit ? stack_limit : (uint32_t *) -1; - multicore_launch_core1_with_stack(entry, stack, sizeof(core1_stack)); -} - -void multicore_launch_core1_raw(void (*entry)(void), uint32_t *sp, uint32_t vector_table) { - // Allow for the fact that the caller may have already enabled the FIFO IRQ for their - // own purposes (expecting FIFO content after core 1 is launched). We must disable - // the IRQ during the handshake, then restore afterwards. - uint irq_num = SIO_FIFO_IRQ_NUM(0); - bool enabled = irq_is_enabled(irq_num); - irq_set_enabled(irq_num, false); - - // Values to be sent in order over the FIFO from core 0 to core 1 - // - // vector_table is value for VTOR register - // sp is initial stack pointer (SP) - // entry is the initial program counter (PC) (don't forget to set the thumb bit!) - const uint32_t cmd_sequence[] = - {0, 0, 1, (uintptr_t) vector_table, (uintptr_t) sp, (uintptr_t) entry}; - - uint seq = 0; - do { - uint cmd = cmd_sequence[seq]; - // Always drain the READ FIFO (from core 1) before sending a 0 - if (!cmd) { - multicore_fifo_drain(); - // Execute a SEV as core 1 may be waiting for FIFO space via WFE - __sev(); - } - multicore_fifo_push_blocking(cmd); - uint32_t response = multicore_fifo_pop_blocking(); - // Move to next state on correct response (echo-d value) otherwise start over - seq = cmd == response ? seq + 1 : 0; - } while (seq < count_of(cmd_sequence)); - - irq_set_enabled(irq_num, enabled); -} - -#define LOCKOUT_MAGIC_START 0x73a8831eu -#define LOCKOUT_MAGIC_END (~LOCKOUT_MAGIC_START) - -static mutex_t lockout_mutex; -static bool lockout_in_progress; - -// note this method is in RAM because lockout is used when writing to flash -// it only makes inline calls -static void __isr __not_in_flash_func(multicore_lockout_handler)(void) { - multicore_fifo_clear_irq(); - while (multicore_fifo_rvalid()) { - if (sio_hw->fifo_rd == LOCKOUT_MAGIC_START) { - uint32_t save = save_and_disable_interrupts(); - multicore_fifo_push_blocking_inline(LOCKOUT_MAGIC_START); - while (multicore_fifo_pop_blocking_inline() != LOCKOUT_MAGIC_END) { - tight_loop_contents(); // not tight but endless potentially - } - restore_interrupts_from_disabled(save); - multicore_fifo_push_blocking_inline(LOCKOUT_MAGIC_END); - } - } -} - -static void check_lockout_mutex_init(void) { - // use known available lock - we only need it briefly - uint32_t save = hw_claim_lock(); - if (!mutex_is_initialized(&lockout_mutex)) { - mutex_init(&lockout_mutex); - } - hw_claim_unlock(save); -} - -void multicore_lockout_victim_init(void) { - check_lockout_mutex_init(); - // On platforms other than RP2040, these are actually the same IRQ number - // (each core only sees its own IRQ, always at the same IRQ number). - uint core_num = get_core_num(); - uint fifo_irq_this_core = SIO_FIFO_IRQ_NUM(core_num); - irq_set_exclusive_handler(fifo_irq_this_core, multicore_lockout_handler); - irq_set_enabled(fifo_irq_this_core, true); - lockout_victim_initialized[core_num] = true; -} - -static bool multicore_lockout_handshake(uint32_t magic, absolute_time_t until) { - uint irq_num = SIO_FIFO_IRQ_NUM(get_core_num()); - bool enabled = irq_is_enabled(irq_num); - if (enabled) irq_set_enabled(irq_num, false); - bool rc = false; - do { - int64_t next_timeout_us = absolute_time_diff_us(get_absolute_time(), until); - if (next_timeout_us < 0) { - break; - } - multicore_fifo_push_timeout_us(magic, (uint64_t)next_timeout_us); - next_timeout_us = absolute_time_diff_us(get_absolute_time(), until); - if (next_timeout_us < 0) { - break; - } - uint32_t word = 0; - if (!multicore_fifo_pop_timeout_us((uint64_t)next_timeout_us, &word)) { - break; - } - if (word == magic) { - rc = true; - } - } while (!rc); - if (enabled) irq_set_enabled(irq_num, true); - return rc; -} - -static bool multicore_lockout_start_block_until(absolute_time_t until) { - check_lockout_mutex_init(); - if (!mutex_enter_block_until(&lockout_mutex, until)) { - return false; - } - hard_assert(!lockout_in_progress); - bool rc = multicore_lockout_handshake(LOCKOUT_MAGIC_START, until); - lockout_in_progress = rc; - mutex_exit(&lockout_mutex); - return rc; -} - -bool multicore_lockout_start_timeout_us(uint64_t timeout_us) { - return multicore_lockout_start_block_until(make_timeout_time_us(timeout_us)); -} - -void multicore_lockout_start_blocking(void) { - multicore_lockout_start_block_until(at_the_end_of_time); -} - -static bool multicore_lockout_end_block_until(absolute_time_t until) { - assert(mutex_is_initialized(&lockout_mutex)); - if (!mutex_enter_block_until(&lockout_mutex, until)) { - return false; - } - assert(lockout_in_progress); - bool rc = multicore_lockout_handshake(LOCKOUT_MAGIC_END, until); - if (rc) { - lockout_in_progress = false; - } - mutex_exit(&lockout_mutex); - return rc; -} - -bool multicore_lockout_end_timeout_us(uint64_t timeout_us) { - return multicore_lockout_end_block_until(make_timeout_time_us(timeout_us)); -} - -void multicore_lockout_end_blocking(void) { - multicore_lockout_end_block_until(at_the_end_of_time); -} - -bool multicore_lockout_victim_is_initialized(uint core_num) { - return lockout_victim_initialized[core_num]; -} - -#if NUM_DOORBELLS - -static uint8_t doorbell_claimed[NUM_CORES][(NUM_DOORBELLS + 7) >> 3]; - -static inline bool is_bit_claimed(const uint8_t *bits, uint bit_index) { - return (bits[bit_index >> 3u] & (1u << (bit_index & 7u))); -} - -static inline void set_claimed_bit(uint8_t *bits, uint bit_index) { - bits[bit_index >> 3u] |= ( uint8_t ) ( 1u << ( bit_index & 7u )); -} - -static inline void clear_claimed_bit(uint8_t *bits, uint bit_index) { - bits[bit_index >> 3u] &= ( uint8_t ) ~( 1u << ( bit_index & 7u )); -} - -static bool multicore_doorbell_claim_under_lock(uint doorbell_num, uint core_mask, bool required) { - static_assert(NUM_CORES == 2, ""); - uint claimed_cores_for_doorbell = (uint) (is_bit_claimed(doorbell_claimed[0], doorbell_num) | - (is_bit_claimed(doorbell_claimed[1], doorbell_num + 1u) << 1)); - if (claimed_cores_for_doorbell & core_mask) { - if (required) { - panic( "Multicoore doorbell %d already claimed on core mask 0x%x; requested core mask 0x%x\n", - claimed_cores_for_doorbell, core_mask); - } - return false; - } else { - for(uint i=0; i=0; i--) { - if (multicore_doorbell_claim_under_lock((uint) i, core_mask, false)) { - rc = i; - break; - } - } - if (required && rc < 0) { - panic("No free doorbells"); - } - hw_claim_unlock(save); - return rc; -} - -void multicore_doorbell_unclaim(uint doorbell_num, uint core_mask) { - check_doorbell_num_param(doorbell_num); - uint32_t save = hw_claim_lock(); - for(uint i=0; i < NUM_CORES; i++) { - if (core_mask & (1u << i)) { - assert(is_bit_claimed(doorbell_claimed[i], doorbell_num)); - clear_claimed_bit(doorbell_claimed[i], doorbell_num); - } - } - hw_claim_unlock(save); -} - - -#endif \ No newline at end of file diff --git a/lib/main/pico-sdk/rp2_common/pico_platform_compiler/include/pico/platform/compiler.h b/lib/main/pico-sdk/rp2_common/pico_platform_compiler/include/pico/platform/compiler.h deleted file mode 100644 index cd1ad526fe..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_platform_compiler/include/pico/platform/compiler.h +++ /dev/null @@ -1,208 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _PICO_PLATFORM_COMPILER_H -#define _PICO_PLATFORM_COMPILER_H - -/** \file platform_compiler.h - * \defgroup pico_platform pico_platform - * - * \brief Macros and definitions (and functions when included by non assembly code) to adapt for different compilers - * - * This header may be included by assembly code - */ - -#include "hardware/platform_defs.h" - -#ifndef __ASSEMBLER__ - -#if defined __GNUC__ -#include -// note LLVM defines __GNUC__ -#ifdef __clang__ -#define PICO_C_COMPILER_IS_CLANG 1 -#else -#define PICO_C_COMPILER_IS_GNU 1 -#endif -#elif defined __ICCARM__ -#ifndef __aligned -#define __aligned(x) __attribute__((__aligned__(x))) -#endif -#ifndef __always_inline -#define __always_inline __attribute__((__always_inline__)) -#endif -#ifndef __noinline -#define __noinline __attribute__((__noinline__)) -#endif -#ifndef __packed -#define __packed __attribute__((__packed__)) -#endif -#ifndef __printflike -#define __printflike(a, b) -#endif -#ifndef __unused -#define __unused __attribute__((__unused__)) -#endif -#ifndef __used -#define __used __attribute__((__used__)) -#endif -#ifndef __CONCAT1 -#define __CONCAT1(a, b) a ## b -#endif -#ifndef __CONCAT -#define __CONCAT(a, b) __CONCAT1(a, b) -#endif -#ifndef __STRING -#define __STRING(a) #a -#endif -/* Compatible definitions of GCC builtins */ - -static inline uint __builtin_ctz(uint x) { - extern uint32_t __ctzsi2(uint32_t); - return __ctzsi2(x); -} -#define __builtin_expect(x, y) (x) -#define __builtin_isnan(x) __iar_isnan(x) -#else -#error Unsupported toolchain -#endif - -#define __weak __attribute__((weak)) - -#include "pico/types.h" - -// GCC_Like_Pragma(x) is a pragma on GNUC compatible compilers -#ifdef __GNUC__ -#define GCC_Like_Pragma _Pragma -#else -#define GCC_Like_Pragma(x) -#endif - -// Clang_Pragma(x) is a pragma on Clang only -#ifdef __clang__ -#define Clang_Pragma _Pragma -#else -#define Clang_Pragma(x) -#endif - -// GCC_Pragma(x) is a pragma on GCC only -#if PICO_C_COMPILER_IS_GNU -#define GCC_Pragma _Pragma -#else -#define GCC_Pragma(x) -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -/*! \brief Marker for an interrupt handler - * \ingroup pico_platform - * - * For example an IRQ handler function called my_interrupt_handler: - * - * void __isr my_interrupt_handler(void) { - */ -#define __isr - -#define __packed_aligned __packed __aligned(4) - -/*! \brief Attribute to force inlining of a function regardless of optimization level - * \ingroup pico_platform - * - * For example my_function here will always be inlined: - * - * int __force_inline my_function(int x) { - * - */ - -#if PICO_C_COMPILER_IS_GNU && (__GNUC__ <= 6 || (__GNUC__ == 7 && (__GNUC_MINOR__ < 3 || !defined(__cplusplus)))) -#define __force_inline inline __always_inline -#else -#define __force_inline __always_inline -#endif - -/*! \brief Macro to determine the number of elements in an array - * \ingroup pico_platform - */ -#ifndef count_of -#define count_of(a) (sizeof(a)/sizeof((a)[0])) -#endif - -/*! \brief Macro to return the maximum of two comparable values - * \ingroup pico_platform - */ -#ifndef MAX -#define MAX(a, b) ((a)>(b)?(a):(b)) -#endif - -/*! \brief Macro to return the minimum of two comparable values - * \ingroup pico_platform - */ -#ifndef MIN -#define MIN(a, b) ((b)>(a)?(a):(b)) -#endif - -#ifdef __ARM_ARCH_ISA_THUMB -#define pico_default_asm(...) __asm (".syntax unified\n" __VA_ARGS__) -#define pico_default_asm_volatile(...) __asm volatile (".syntax unified\n" __VA_ARGS__) -#define pico_default_asm_goto(...) __asm goto (".syntax unified\n" __VA_ARGS__) -#else -#define pico_default_asm(...) __asm (__VA_ARGS__) -#define pico_default_asm_volatile(...) __asm volatile (__VA_ARGS__) -#define pico_default_asm_goto(...) __asm goto (__VA_ARGS__) -#endif - -/*! \brief Ensure that the compiler does not move memory access across this method call - * \ingroup pico_platform - * - * For example in the following code: - * - * *some_memory_location = var_a; - * __compiler_memory_barrier(); - * uint32_t var_b = *some_other_memory_location - * - * The compiler will not move the load from `some_other_memory_location` above the memory barrier (which it otherwise - * might - even above the memory store!) - */ -__force_inline static void __compiler_memory_barrier(void) { - pico_default_asm_volatile ("" : : : "memory"); -} - -/*! \brief Utility macro to assert two types are equivalent. - * \ingroup pico_platform - * - * This macro can be useful in other macros along with `typeof` to assert that two parameters are of equivalent type - * (or that a single parameter is of an expected type) - */ -#define __check_type_compatible(type_a, type_b) static_assert(__builtin_types_compatible_p(type_a, type_b), __STRING(type_a) " is not compatible with " __STRING(type_b)); - -#define WRAPPER_FUNC(x) __wrap_ ## x -#define REAL_FUNC(x) __real_ ## x - -#ifdef __cplusplus -} -#endif - -#else // __ASSEMBLER__ - -#if defined __GNUC__ -// note LLVM defines __GNUC__ -#ifdef __clang__ -#define PICO_ASSEMBLER_IS_CLANG 1 -#else -#define PICO_ASSEMBLER_IS_GNU 1 -#endif -#elif defined __ICCARM__ -#else -#error Unsupported toolchain -#endif - -#define WRAPPER_FUNC_NAME(x) __wrap_##x - -#endif // !__ASSEMBLER__ - -#endif diff --git a/lib/main/pico-sdk/rp2_common/pico_platform_panic/include/pico/platform/panic.h b/lib/main/pico-sdk/rp2_common/pico_platform_panic/include/pico/platform/panic.h deleted file mode 100644 index a358e17006..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_platform_panic/include/pico/platform/panic.h +++ /dev/null @@ -1,44 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _PICO_PLATFORM_PANIC_H -#define _PICO_PLATFORM_PANIC_H - -#ifdef __cplusplus -extern "C" { -#endif - -#ifndef __ASSEMBLER__ - -/*! \brief Panics with the message "Unsupported" - * \ingroup pico_platform - * \see panic - */ -void __attribute__((noreturn)) panic_unsupported(void); - -/*! \brief Displays a panic message and halts execution - * \ingroup pico_platform - * - * An attempt is made to output the message to all registered STDOUT drivers - * after which this method executes a BKPT instruction. - * - * @param fmt format string (printf-like) - * @param ... printf-like arguments - */ -void __attribute__((noreturn)) panic(const char *fmt, ...); - -#ifdef NDEBUG -#define panic_compact(...) panic(__VA_ARGS__) -#else -#define panic_compact(...) panic("") -#endif -#endif - -#ifdef __cplusplus -} -#endif - -#endif \ No newline at end of file diff --git a/lib/main/pico-sdk/rp2_common/pico_platform_panic/panic.c b/lib/main/pico-sdk/rp2_common/pico_platform_panic/panic.c deleted file mode 100644 index d3eca23eea..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_platform_panic/panic.c +++ /dev/null @@ -1,85 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include -#include -#include -#include "pico.h" -#include "pico/platform/panic.h" - -#if LIB_PICO_PRINTF_PICO -#include "pico/printf.h" -#else -#define weak_raw_printf printf -#define weak_raw_vprintf vprintf -#endif - -void __attribute__((noreturn)) panic_unsupported(void) { - panic("not supported"); -} - -// PICO_CONFIG: PICO_PANIC_FUNCTION, Name of a function to use in place of the stock panic function or empty string to simply breakpoint on panic, group=pico_runtime -// note the default is not "panic" it is undefined -#ifdef PICO_PANIC_FUNCTION -#define PICO_PANIC_FUNCTION_EMPTY (__CONCAT(PICO_PANIC_FUNCTION, 1) == 1) -#if !PICO_PANIC_FUNCTION_EMPTY -extern void __attribute__((noreturn)) __printflike(1, 0) PICO_PANIC_FUNCTION(__unused const char *fmt, ...); -#endif -// Use a forwarding method here as it is a little simpler than renaming the symbol as it is used from assembler -void __attribute__((naked, noreturn)) __printflike(1, 0) panic(__unused const char *fmt, ...) { - // if you get an undefined reference here, you didn't define your PICO_PANIC_FUNCTION! - pico_default_asm ( -#ifdef __riscv - -#if !PICO_PANIC_FUNCTION_EMPTY - "jal " __XSTRING(PICO_PANIC_FUNCTION) "\n" -#endif - "ebreak\n" - "1: j 1b\n" - -#else - - "push {lr}\n" -#if !PICO_PANIC_FUNCTION_EMPTY - "bl " __XSTRING(PICO_PANIC_FUNCTION) "\n" -#endif - "bkpt #0\n" - "1: b 1b\n" // loop for ever as we are no return - -#endif - : - : - : - ); -} -#else -// todo consider making this try harder to output if we panic early -// right now, print mutex may be uninitialised (in which case it deadlocks - although after printing "PANIC") -// more importantly there may be no stdout/UART initialized yet -// todo we may want to think about where we print panic messages to; writing to USB appears to work -// though it doesn't seem like we can expect it to... fine for now -void __attribute__((noreturn)) __printflike(1, 0) panic(const char *fmt, ...) { - puts("\n*** PANIC ***\n"); - if (fmt) { -#if LIB_PICO_PRINTF_NONE - puts(fmt); -#else - va_list args; - va_start(args, fmt); -#if PICO_PRINTF_ALWAYS_INCLUDED - vprintf(fmt, args); -#else - weak_raw_vprintf(fmt, args); -#endif - va_end(args); - puts("\n"); -#endif - } - - _exit(1); -} -#endif diff --git a/lib/main/pico-sdk/rp2_common/pico_platform_sections/include/pico/platform/sections.h b/lib/main/pico-sdk/rp2_common/pico_platform_sections/include/pico/platform/sections.h deleted file mode 100644 index e85700295b..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_platform_sections/include/pico/platform/sections.h +++ /dev/null @@ -1,185 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _PICO_PLATFORM_SECTION_MACROS_H -#define _PICO_PLATFORM_SECTION_MACROS_H - -#ifndef __ASSEMBLER__ - -/*! \brief Section attribute macro for placement in RAM after the `.data` section - * \ingroup pico_platform - * - * For example a 400 element `uint32_t` array placed after the .data section - * - * uint32_t __after_data("my_group_name") a_big_array[400]; - * - * The section attribute is `.after_data.` - * - * \param group a string suffix to use in the section name to distinguish groups that can be linker - * garbage-collected independently - */ -#ifndef __after_data -#define __after_data(group) __attribute__((section(".after_data." group))) -#endif - -/*! \brief Section attribute macro for placement not in flash (i.e in RAM) - * \ingroup pico_platform - * - * For example a 3 element `uint32_t` array placed in RAM (even though it is `static const`) - * - * static const uint32_t __not_in_flash("my_group_name") an_array[3]; - * - * The section attribute is `.time_critical.` - * - * \param group a string suffix to use in the section name to distinguish groups that can be linker - * garbage-collected independently - */ -#ifndef __not_in_flash -#define __not_in_flash(group) __attribute__((section(".time_critical." group))) -#endif - -/*! \brief Section attribute macro for placement in the SRAM bank 4 (known as "scratch X") - * \ingroup pico_platform - * - * Scratch X is commonly used for critical data and functions accessed only by one core (when only - * one core is accessing the RAM bank, there is no opportunity for stalls) - * - * For example a `uint32_t` variable placed in "scratch X" - * - * uint32_t __scratch_x("my_group_name") foo = 23; - * - * The section attribute is `.scratch_x.` - * - * \param group a string suffix to use in the section name to distinguish groups that can be linker - * garbage-collected independently - */ -#ifndef __scratch_x -#define __scratch_x(group) __attribute__((section(".scratch_x." group))) -#endif - -/*! \brief Section attribute macro for placement in the SRAM bank 5 (known as "scratch Y") - * \ingroup pico_platform - * - * Scratch Y is commonly used for critical data and functions accessed only by one core (when only - * one core is accessing the RAM bank, there is no opportunity for stalls) - * - * For example a `uint32_t` variable placed in "scratch Y" - * - * uint32_t __scratch_y("my_group_name") foo = 23; - * - * The section attribute is `.scratch_y.` - * - * \param group a string suffix to use in the section name to distinguish groups that can be linker - * garbage-collected independently - */ -#ifndef __scratch_y -#define __scratch_y(group) __attribute__((section(".scratch_y." group))) -#endif - -/*! \brief Section attribute macro for data that is to be left uninitialized - * \ingroup pico_platform - * - * Data marked this way will retain its value across a reset (normally uninitialized data - in the .bss - * section) is initialized to zero during runtime initialization - * - * For example a `uint32_t` foo that will retain its value if the program is restarted by reset. - * - * uint32_t __uninitialized_ram(foo); - * - * The section attribute is `.uninitialized_data.` - * - * \param group a string suffix to use in the section name to distinguish groups that can be linker - * garbage-collected independently - */ -#ifndef __uninitialized_ram -#define __uninitialized_ram(group) __attribute__((section(".uninitialized_data." #group))) group -#endif - -/*! \brief Section attribute macro for placement in flash even in a COPY_TO_RAM binary - * \ingroup pico_platform - * - * For example a `uint32_t` variable explicitly placed in flash (it will hard fault if you attempt to write it!) - * - * uint32_t __in_flash("my_group_name") foo = 23; - * - * The section attribute is `.flashdata.` - * - * \param group a string suffix to use in the section name to distinguish groups that can be linker - * garbage-collected independently - */ -#ifndef __in_flash -#define __in_flash(group) __attribute__((section(".flashdata." group))) -#endif - -/*! \brief Indicates a function should not be stored in flash - * \ingroup pico_platform - * - * Decorates a function name, such that the function will execute from RAM (assuming it is not inlined - * into a flash function by the compiler) - * - * For example a function called my_func taking an int parameter: - * - * void __not_in_flash_func(my_func)(int some_arg) { - * - * The function is placed in the `.time_critical.` linker section - * - * \see __no_inline_not_in_flash_func - */ -#ifndef __not_in_flash_func -#define __not_in_flash_func(func_name) __not_in_flash(__STRING(func_name)) func_name -#endif - -/*! \brief Indicates a function is time/latency critical and should not run from flash - * \ingroup pico_platform - * - * Decorates a function name, such that the function will execute from RAM (assuming it is not inlined - * into a flash function by the compiler) to avoid possible flash latency. Currently this macro is identical - * in implementation to `__not_in_flash_func`, however the semantics are distinct and a `__time_critical_func` - * may in the future be treated more specially to reduce the overhead when calling such function from a flash - * function. - * - * For example a function called my_func taking an int parameter: - * - * void __time_critical_func(my_func)(int some_arg) { - * - * The function is placed in the `.time_critical.` linker section - * - * \see __not_in_flash_func - */ -#ifndef __time_critical_func -#define __time_critical_func(func_name) __not_in_flash_func(func_name) -#endif - -/*! \brief Indicate a function should not be stored in flash and should not be inlined - * \ingroup pico_platform - * - * Decorates a function name, such that the function will execute from RAM, explicitly marking it as - * noinline to prevent it being inlined into a flash function by the compiler - * - * For example a function called my_func taking an int parameter: - * - * void __no_inline_not_in_flash_func(my_func)(int some_arg) { - * - * The function is placed in the `.time_critical.` linker section - */ -#ifndef __no_inline_not_in_flash_func -#define __no_inline_not_in_flash_func(func_name) __noinline __not_in_flash_func(func_name) -#endif - -#else - -#ifndef RAM_SECTION_NAME -#define RAM_SECTION_NAME(x) .time_critical.##x -#endif - -#ifndef SECTION_NAME -#define SECTION_NAME(x) .text.##x -#endif - -#endif // !__ASSEMBLER__ - -#endif - diff --git a/lib/main/pico-sdk/rp2_common/pico_printf/LICENSE b/lib/main/pico-sdk/rp2_common/pico_printf/LICENSE deleted file mode 100644 index 8f7ebd0b98..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_printf/LICENSE +++ /dev/null @@ -1,22 +0,0 @@ -The MIT License (MIT) - -Copyright (c) 2014 Marco Paland - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in all -copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -SOFTWARE. - diff --git a/lib/main/pico-sdk/rp2_common/pico_printf/include/pico/printf.h b/lib/main/pico-sdk/rp2_common/pico_printf/include/pico/printf.h deleted file mode 100644 index c047eb6abd..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_printf/include/pico/printf.h +++ /dev/null @@ -1,93 +0,0 @@ -/////////////////////////////////////////////////////////////////////////////// -// \author (c) Marco Paland (info@paland.com) -// 2014-2019, PALANDesign Hannover, Germany -// -// \license The MIT License (MIT) -// -// Permission is hereby granted, free of charge, to any person obtaining a copy -// of this software and associated documentation files (the "Software"), to deal -// in the Software without restriction, including without limitation the rights -// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -// copies of the Software, and to permit persons to whom the Software is -// furnished to do so, subject to the following conditions: -// -// The above copyright notice and this permission notice shall be included in -// all copies or substantial portions of the Software. -// -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -// THE SOFTWARE. -// -// \brief Tiny printf, sprintf and snprintf implementation, optimized for speed on -// embedded systems with a very limited resources. -// Use this instead of bloated standard/newlib printf. -// These routines are thread safe and reentrant. -// -/////////////////////////////////////////////////////////////////////////////// - -#ifndef _PICO_PRINTF_H -#define _PICO_PRINTF_H - -/** \file printf.h - * \defgroup pico_printf pico_printf - * - * \brief Compact replacement for printf by Marco Paland (info@paland.com) - */ - -#ifdef __cplusplus -extern "C" { -#endif - -#include "pico.h" -#include -#include - -// PICO_CONFIG: PICO_PRINTF_ALWAYS_INCLUDED, Whether to always include printf code even if only called weakly (by panic), type=bool, default=1 in debug build 0 otherwise, group=pico_printf -#ifndef PICO_PRINTF_ALWAYS_INCLUDED -#ifndef NDEBUG -#define PICO_PRINTF_ALWAYS_INCLUDED 1 -#else -#define PICO_PRINTF_ALWAYS_INCLUDED 0 -#endif -#endif - -#if LIB_PICO_PRINTF_PICO -// weak raw printf may be a puts if printf has not been called, -// so that we can support gc of printf when it isn't called -// -// it is called raw to distinguish it from the regular printf which -// is in stdio.c and does mutex protection -#if !PICO_PRINTF_ALWAYS_INCLUDED -bool __printflike(1, 0) weak_raw_printf(const char *fmt, ...); -bool weak_raw_vprintf(const char *fmt, va_list args); -#else -#define weak_raw_printf(...) ({printf(__VA_ARGS__); true;}) -#define weak_raw_vprintf(fmt,va) ({vprintf(fmt,va); true;}) -#endif - -/** - * \brief printf with output function - * You may use this as dynamic alternative to printf() with its fixed _putchar() output - * \param out An output function which takes one character and an argument pointer - * \param arg An argument pointer for user data passed to output function - * \param format A string that specifies the format of the output - * \return The number of characters that are sent to the output function, not counting the terminating null character - */ -int vfctprintf(void (*out)(char character, void *arg), void *arg, const char *format, va_list va); - -#else - -#define weak_raw_printf(...) ({printf(__VA_ARGS__); true;}) -#define weak_raw_vprintf(fmt,va) ({vprintf(fmt,va); true;}) - -#endif - -#ifdef __cplusplus -} -#endif - -#endif // _PRINTF_H_ diff --git a/lib/main/pico-sdk/rp2_common/pico_printf/printf.c b/lib/main/pico-sdk/rp2_common/pico_printf/printf.c deleted file mode 100644 index 7ae526ff79..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_printf/printf.c +++ /dev/null @@ -1,941 +0,0 @@ -/////////////////////////////////////////////////////////////////////////////// -// \author (c) Marco Paland (info@paland.com) -// 2014-2019, PALANDesign Hannover, Germany -// -// \license The MIT License (MIT) -// -// Permission is hereby granted, free of charge, to any person obtaining a copy -// of this software and associated documentation files (the "Software"), to deal -// in the Software without restriction, including without limitation the rights -// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -// copies of the Software, and to permit persons to whom the Software is -// furnished to do so, subject to the following conditions: -// -// The above copyright notice and this permission notice shall be included in -// all copies or substantial portions of the Software. -// -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -// THE SOFTWARE. -// -// \brief Tiny printf, sprintf and (v)snprintf implementation, optimized for speed on -// embedded systems with a very limited resources. These routines are thread -// safe and reentrant! -// Use this instead of the bloated standard/newlib printf cause these use -// malloc for printf (and may not be thread safe). -// -/////////////////////////////////////////////////////////////////////////////// - -#include -#include -#include - -#include "pico.h" -#include "pico/printf.h" - -// PICO_CONFIG: PICO_PRINTF_NTOA_BUFFER_SIZE, Define printf ntoa buffer size, min=0, max=128, default=32, group=pico_printf -// 'ntoa' conversion buffer size, this must be big enough to hold one converted -// numeric number including padded zeros (dynamically created on stack) -#ifndef PICO_PRINTF_NTOA_BUFFER_SIZE -#define PICO_PRINTF_NTOA_BUFFER_SIZE 32U -#endif - -// PICO_CONFIG: PICO_PRINTF_FTOA_BUFFER_SIZE, Define printf ftoa buffer size, min=0, max=128, default=32, group=pico_printf -// 'ftoa' conversion buffer size, this must be big enough to hold one converted -// float number including padded zeros (dynamically created on stack) -#ifndef PICO_PRINTF_FTOA_BUFFER_SIZE -#define PICO_PRINTF_FTOA_BUFFER_SIZE 32U -#endif - -// PICO_CONFIG: PICO_PRINTF_SUPPORT_FLOAT, Enable floating point printing, type=bool, default=1, group=pico_printf -// support for the floating point type (%f) -#ifndef PICO_PRINTF_SUPPORT_FLOAT -#define PICO_PRINTF_SUPPORT_FLOAT 1 -#endif - -// PICO_CONFIG: PICO_PRINTF_SUPPORT_EXPONENTIAL, Enable exponential floating point printing, type=bool, default=1, group=pico_printf -// support for exponential floating point notation (%e/%g) -#ifndef PICO_PRINTF_SUPPORT_EXPONENTIAL -#define PICO_PRINTF_SUPPORT_EXPONENTIAL 1 -#endif - -// PICO_CONFIG: PICO_PRINTF_DEFAULT_FLOAT_PRECISION, Define default floating point precision, min=1, max=16, default=6, group=pico_printf -#ifndef PICO_PRINTF_DEFAULT_FLOAT_PRECISION -#define PICO_PRINTF_DEFAULT_FLOAT_PRECISION 6U -#endif - -// PICO_CONFIG: PICO_PRINTF_MAX_FLOAT, Define the largest float suitable to print with %f, min=1, max=1e9, default=1e9, group=pico_printf -#ifndef PICO_PRINTF_MAX_FLOAT -#define PICO_PRINTF_MAX_FLOAT 1e9 -#endif - -// PICO_CONFIG: PICO_PRINTF_SUPPORT_LONG_LONG, Enable support for long long types (%llu or %p), type=bool, default=1, group=pico_printf -#ifndef PICO_PRINTF_SUPPORT_LONG_LONG -#define PICO_PRINTF_SUPPORT_LONG_LONG 1 -#endif - -// PICO_CONFIG: PICO_PRINTF_SUPPORT_PTRDIFF_T, Enable support for the ptrdiff_t type (%t), type=bool, default=1, group=pico_printf -// ptrdiff_t is normally defined in as long or long long type -#ifndef PICO_PRINTF_SUPPORT_PTRDIFF_T -#define PICO_PRINTF_SUPPORT_PTRDIFF_T 1 -#endif - -/////////////////////////////////////////////////////////////////////////////// - -// internal flag definitions -#define FLAGS_ZEROPAD (1U << 0U) -#define FLAGS_LEFT (1U << 1U) -#define FLAGS_PLUS (1U << 2U) -#define FLAGS_SPACE (1U << 3U) -#define FLAGS_HASH (1U << 4U) -#define FLAGS_UPPERCASE (1U << 5U) -#define FLAGS_CHAR (1U << 6U) -#define FLAGS_SHORT (1U << 7U) -#define FLAGS_LONG (1U << 8U) -#define FLAGS_LONG_LONG (1U << 9U) -#define FLAGS_PRECISION (1U << 10U) -#define FLAGS_ADAPT_EXP (1U << 11U) - -// import float.h for DBL_MAX -#if PICO_PRINTF_SUPPORT_FLOAT - -#include - -#endif - -// output function type -typedef void (*out_fct_type)(char character, void *buffer, size_t idx, size_t maxlen); - -#if !PICO_PRINTF_ALWAYS_INCLUDED -// we don't have a way to specify a truly weak symbol reference (the linker will always include targets in a single link step, -// so we make a function pointer that is initialized on the first printf called... if printf is not included in the binary -// (or has never been called - we can't tell) then this will be null. the assumption is that if you are using printf -// you are likely to have printed something. -static int (*lazy_vsnprintf)(out_fct_type out, char *buffer, const size_t maxlen, const char *format, va_list va); -#endif - -// wrapper (used as buffer) for output function type -typedef struct { - void (*fct)(char character, void *arg); - void *arg; -} out_fct_wrap_type; - -// internal buffer output -static inline void _out_buffer(char character, void *buffer, size_t idx, size_t maxlen) { - if (idx < maxlen) { - ((char *) buffer)[idx] = character; - } -} - -// internal null output -static inline void _out_null(char character, void *buffer, size_t idx, size_t maxlen) { - (void) character; - (void) buffer; - (void) idx; - (void) maxlen; -} - -// internal output function wrapper -static inline void _out_fct(char character, void *buffer, size_t idx, size_t maxlen) { - (void) idx; - (void) maxlen; - if (character) { - // buffer is the output fct pointer - ((out_fct_wrap_type *) buffer)->fct(character, ((out_fct_wrap_type *) buffer)->arg); - } -} - - -// internal secure strlen -// \return The length of the string (excluding the terminating 0) limited by 'maxsize' -static inline unsigned int _strnlen_s(const char *str, size_t maxsize) { - const char *s; - for (s = str; *s && maxsize--; ++s); - return (unsigned int) (s - str); -} - - -// internal test if char is a digit (0-9) -// \return true if char is a digit -static inline bool _is_digit(char ch) { - return (ch >= '0') && (ch <= '9'); -} - - -// internal ASCII string to unsigned int conversion -static unsigned int _atoi(const char **str) { - unsigned int i = 0U; - while (_is_digit(**str)) { - i = i * 10U + (unsigned int) (*((*str)++) - '0'); - } - return i; -} - - -// output the specified string in reverse, taking care of any zero-padding -static size_t _out_rev(out_fct_type out, char *buffer, size_t idx, size_t maxlen, const char *buf, size_t len, - unsigned int width, unsigned int flags) { - const size_t start_idx = idx; - - // pad spaces up to given width - if (!(flags & FLAGS_LEFT) && !(flags & FLAGS_ZEROPAD)) { - for (size_t i = len; i < width; i++) { - out(' ', buffer, idx++, maxlen); - } - } - - // reverse string - while (len) { - out(buf[--len], buffer, idx++, maxlen); - } - - // append pad spaces up to given width - if (flags & FLAGS_LEFT) { - while (idx - start_idx < width) { - out(' ', buffer, idx++, maxlen); - } - } - - return idx; -} - - -// internal itoa format -static size_t _ntoa_format(out_fct_type out, char *buffer, size_t idx, size_t maxlen, char *buf, size_t len, - bool negative, unsigned int base, unsigned int prec, unsigned int width, - unsigned int flags) { - // pad leading zeros - if (!(flags & FLAGS_LEFT)) { - if (width && (flags & FLAGS_ZEROPAD) && (negative || (flags & (FLAGS_PLUS | FLAGS_SPACE)))) { - width--; - } - while ((len < prec) && (len < PICO_PRINTF_NTOA_BUFFER_SIZE)) { - buf[len++] = '0'; - } - while ((flags & FLAGS_ZEROPAD) && (len < width) && (len < PICO_PRINTF_NTOA_BUFFER_SIZE)) { - buf[len++] = '0'; - } - } - - // handle hash - if (flags & FLAGS_HASH) { - if (!(flags & FLAGS_PRECISION) && len && ((len == prec) || (len == width))) { - len--; - if (len && (base == 16U)) { - len--; - } - } - if ((base == 16U) && !(flags & FLAGS_UPPERCASE) && (len < PICO_PRINTF_NTOA_BUFFER_SIZE)) { - buf[len++] = 'x'; - } else if ((base == 16U) && (flags & FLAGS_UPPERCASE) && (len < PICO_PRINTF_NTOA_BUFFER_SIZE)) { - buf[len++] = 'X'; - } else if ((base == 2U) && (len < PICO_PRINTF_NTOA_BUFFER_SIZE)) { - buf[len++] = 'b'; - } - if (len < PICO_PRINTF_NTOA_BUFFER_SIZE) { - buf[len++] = '0'; - } - } - - if (len < PICO_PRINTF_NTOA_BUFFER_SIZE) { - if (negative) { - buf[len++] = '-'; - } else if (flags & FLAGS_PLUS) { - buf[len++] = '+'; // ignore the space if the '+' exists - } else if (flags & FLAGS_SPACE) { - buf[len++] = ' '; - } - } - - return _out_rev(out, buffer, idx, maxlen, buf, len, width, flags); -} - - -// internal itoa for 'long' type -static size_t _ntoa_long(out_fct_type out, char *buffer, size_t idx, size_t maxlen, unsigned long value, bool negative, - unsigned long base, unsigned int prec, unsigned int width, unsigned int flags) { - char buf[PICO_PRINTF_NTOA_BUFFER_SIZE]; - size_t len = 0U; - - // no hash for 0 values - if (!value) { - flags &= ~FLAGS_HASH; - } - - // write if precision != 0 and value is != 0 - if (!(flags & FLAGS_PRECISION) || value) { - do { - const char digit = (char) (value % base); - buf[len++] = (char)(digit < 10 ? '0' + digit : (flags & FLAGS_UPPERCASE ? 'A' : 'a') + digit - 10); - value /= base; - } while (value && (len < PICO_PRINTF_NTOA_BUFFER_SIZE)); - } - - return _ntoa_format(out, buffer, idx, maxlen, buf, len, negative, (unsigned int) base, prec, width, flags); -} - - -// internal itoa for 'long long' type -#if PICO_PRINTF_SUPPORT_LONG_LONG - -static size_t _ntoa_long_long(out_fct_type out, char *buffer, size_t idx, size_t maxlen, unsigned long long value, - bool negative, unsigned long long base, unsigned int prec, unsigned int width, - unsigned int flags) { - char buf[PICO_PRINTF_NTOA_BUFFER_SIZE]; - size_t len = 0U; - - // no hash for 0 values - if (!value) { - flags &= ~FLAGS_HASH; - } - - // write if precision != 0 and value is != 0 - if (!(flags & FLAGS_PRECISION) || value) { - do { - const char digit = (char) (value % base); - buf[len++] = (char)(digit < 10 ? '0' + digit : (flags & FLAGS_UPPERCASE ? 'A' : 'a') + digit - 10); - value /= base; - } while (value && (len < PICO_PRINTF_NTOA_BUFFER_SIZE)); - } - - return _ntoa_format(out, buffer, idx, maxlen, buf, len, negative, (unsigned int) base, prec, width, flags); -} - -#endif // PICO_PRINTF_SUPPORT_LONG_LONG - - -#if PICO_PRINTF_SUPPORT_FLOAT - -#if PICO_PRINTF_SUPPORT_EXPONENTIAL -// forward declaration so that _ftoa can switch to exp notation for values > PICO_PRINTF_MAX_FLOAT -static size_t _etoa(out_fct_type out, char *buffer, size_t idx, size_t maxlen, double value, unsigned int prec, - unsigned int width, unsigned int flags); -#endif - -#define is_nan __builtin_isnan - -// internal ftoa for fixed decimal floating point -static size_t _ftoa(out_fct_type out, char *buffer, size_t idx, size_t maxlen, double value, unsigned int prec, - unsigned int width, unsigned int flags) { - char buf[PICO_PRINTF_FTOA_BUFFER_SIZE]; - size_t len = 0U; - double diff = 0.0; - - // powers of 10 - static const double pow10[] = {1, 10, 100, 1000, 10000, 100000, 1000000, 10000000, 100000000, 1000000000}; - - // test for special values - if (is_nan(value)) - return _out_rev(out, buffer, idx, maxlen, "nan", 3, width, flags); - if (value < -DBL_MAX) - return _out_rev(out, buffer, idx, maxlen, "fni-", 4, width, flags); - if (value > DBL_MAX) - return _out_rev(out, buffer, idx, maxlen, (flags & FLAGS_PLUS) ? "fni+" : "fni", (flags & FLAGS_PLUS) ? 4U : 3U, - width, flags); - - // test for very large values - // standard printf behavior is to print EVERY whole number digit -- which could be 100s of characters overflowing your buffers == bad - if ((value > PICO_PRINTF_MAX_FLOAT) || (value < -PICO_PRINTF_MAX_FLOAT)) { -#if PICO_PRINTF_SUPPORT_EXPONENTIAL - return _etoa(out, buffer, idx, maxlen, value, prec, width, flags); -#else - return 0U; -#endif - } - - // test for negative - bool negative = false; - if (value < 0) { - negative = true; - value = 0 - value; - } - - // set default precision, if not set explicitly - if (!(flags & FLAGS_PRECISION)) { - prec = PICO_PRINTF_DEFAULT_FLOAT_PRECISION; - } - // limit precision to 9, cause a prec >= 10 can lead to overflow errors - while ((len < PICO_PRINTF_FTOA_BUFFER_SIZE) && (prec > 9U)) { - buf[len++] = '0'; - prec--; - } - - int whole = (int) value; - double tmp = (value - whole) * pow10[prec]; - unsigned long frac = (unsigned long) tmp; - diff = tmp - frac; - - if (diff > 0.5) { - ++frac; - // handle rollover, e.g. case 0.99 with prec 1 is 1.0 - if (frac >= pow10[prec]) { - frac = 0; - ++whole; - } - } else if (diff < 0.5) { - } else if ((frac == 0U) || (frac & 1U)) { - // if halfway, round up if odd OR if last digit is 0 - ++frac; - } - - if (prec == 0U) { - diff = value - (double) whole; - if (!((diff < 0.5) || (diff > 0.5)) && (whole & 1)) { - // exactly 0.5 and ODD, then round up - // 1.5 -> 2, but 2.5 -> 2 - ++whole; - } - } else { - unsigned int count = prec; - // now do fractional part, as an unsigned number - while (len < PICO_PRINTF_FTOA_BUFFER_SIZE) { - --count; - buf[len++] = (char) (48U + (frac % 10U)); - if (!(frac /= 10U)) { - break; - } - } - // add extra 0s - while ((len < PICO_PRINTF_FTOA_BUFFER_SIZE) && (count-- > 0U)) { - buf[len++] = '0'; - } - if (len < PICO_PRINTF_FTOA_BUFFER_SIZE) { - // add decimal - buf[len++] = '.'; - } - } - - // do whole part, number is reversed - while (len < PICO_PRINTF_FTOA_BUFFER_SIZE) { - buf[len++] = (char) (48 + (whole % 10)); - if (!(whole /= 10)) { - break; - } - } - - // pad leading zeros - if (!(flags & FLAGS_LEFT) && (flags & FLAGS_ZEROPAD)) { - if (width && (negative || (flags & (FLAGS_PLUS | FLAGS_SPACE)))) { - width--; - } - while ((len < width) && (len < PICO_PRINTF_FTOA_BUFFER_SIZE)) { - buf[len++] = '0'; - } - } - - if (len < PICO_PRINTF_FTOA_BUFFER_SIZE) { - if (negative) { - buf[len++] = '-'; - } else if (flags & FLAGS_PLUS) { - buf[len++] = '+'; // ignore the space if the '+' exists - } else if (flags & FLAGS_SPACE) { - buf[len++] = ' '; - } - } - - return _out_rev(out, buffer, idx, maxlen, buf, len, width, flags); -} - - -#if PICO_PRINTF_SUPPORT_EXPONENTIAL - -// internal ftoa variant for exponential floating-point type, contributed by Martijn Jasperse -static size_t _etoa(out_fct_type out, char *buffer, size_t idx, size_t maxlen, double value, unsigned int prec, - unsigned int width, unsigned int flags) { - // check for NaN and special values - if (is_nan(value) || (value > DBL_MAX) || (value < -DBL_MAX)) { - return _ftoa(out, buffer, idx, maxlen, value, prec, width, flags); - } - - // determine the sign - const bool negative = value < 0; - if (negative) { - value = -value; - } - - // default precision - if (!(flags & FLAGS_PRECISION)) { - prec = PICO_PRINTF_DEFAULT_FLOAT_PRECISION; - } - - // determine the decimal exponent - // based on the algorithm by David Gay (https://www.ampl.com/netlib/fp/dtoa.c) - union { - uint64_t U; - double F; - } conv; - - conv.F = value; - int expval; - if (conv.U) { - int exp2 = (int) ((conv.U >> 52U) & 0x07FFU) - 1023; // effectively log2 - conv.U = (conv.U & ((1ULL << 52U) - 1U)) | (1023ULL << 52U); // drop the exponent so conv.F is now in [1,2) - // now approximate log10 from the log2 integer part and an expansion of ln around 1.5 - expval = (int) (0.1760912590558 + exp2 * 0.301029995663981 + (conv.F - 1.5) * 0.289529654602168); - // now we want to compute 10^expval but we want to be sure it won't overflow - exp2 = (int) (expval * 3.321928094887362 + 0.5); - const double z = expval * 2.302585092994046 - exp2 * 0.6931471805599453; - const double z2 = z * z; - conv.U = (uint64_t) (exp2 + 1023) << 52U; - // compute exp(z) using continued fractions, see https://en.wikipedia.org/wiki/Exponential_function#Continued_fractions_for_ex - conv.F *= 1 + 2 * z / (2 - z + (z2 / (6 + (z2 / (10 + z2 / 14))))); - // correct for rounding errors - if (value < conv.F) { - expval--; - conv.F /= 10; - } - } else { - expval = 0; - } - - // the exponent format is "%+03d" and largest value is "307", so set aside 4-5 characters - unsigned int minwidth = ((expval < 100) && (expval > -100)) ? 4U : 5U; - - // in "%g" mode, "prec" is the number of *significant figures* not decimals - if (flags & FLAGS_ADAPT_EXP) { - // do we want to fall-back to "%f" mode? - if ((conv.U == 0) || ((value >= 1e-4) && (value < 1e6))) { - if ((int) prec > expval) { - prec = (unsigned) ((int) prec - expval - 1); - } else { - prec = 0; - } - flags |= FLAGS_PRECISION; // make sure _ftoa respects precision - // no characters in exponent - minwidth = 0U; - expval = 0; - } else { - // we use one sigfig for the whole part - if ((prec > 0) && (flags & FLAGS_PRECISION)) { - --prec; - } - } - } - - // will everything fit? - unsigned int fwidth = width; - if (width > minwidth) { - // we didn't fall-back so subtract the characters required for the exponent - fwidth -= minwidth; - } else { - // not enough characters, so go back to default sizing - fwidth = 0U; - } - if ((flags & FLAGS_LEFT) && minwidth) { - // if we're padding on the right, DON'T pad the floating part - fwidth = 0U; - } - - // rescale the float value - if (expval) { - value /= conv.F; - } - - // output the floating part - const size_t start_idx = idx; - idx = _ftoa(out, buffer, idx, maxlen, negative ? -value : value, prec, fwidth, flags & ~FLAGS_ADAPT_EXP); - - // output the exponent part - if (minwidth) { - // output the exponential symbol - out((flags & FLAGS_UPPERCASE) ? 'E' : 'e', buffer, idx++, maxlen); - // output the exponent value - idx = _ntoa_long(out, buffer, idx, maxlen, (uint)((expval < 0) ? -expval : expval), expval < 0, 10, 0, minwidth - 1, - FLAGS_ZEROPAD | FLAGS_PLUS); - // might need to right-pad spaces - if (flags & FLAGS_LEFT) { - while (idx - start_idx < width) out(' ', buffer, idx++, maxlen); - } - } - return idx; -} - -#endif // PICO_PRINTF_SUPPORT_EXPONENTIAL -#endif // PICO_PRINTF_SUPPORT_FLOAT - -// internal vsnprintf -static int _vsnprintf(out_fct_type out, char *buffer, const size_t maxlen, const char *format, va_list va) { -#if !PICO_PRINTF_ALWAYS_INCLUDED - lazy_vsnprintf = _vsnprintf; -#endif - unsigned int flags, width, precision, n; - size_t idx = 0U; - - if (!buffer) { - // use null output function - out = _out_null; - } - - while (*format) { - // format specifier? %[flags][width][.precision][length] - if (*format != '%') { - // no - out(*format, buffer, idx++, maxlen); - format++; - continue; - } else { - // yes, evaluate it - format++; - } - - // evaluate flags - flags = 0U; - do { - switch (*format) { - case '0': - flags |= FLAGS_ZEROPAD; - format++; - n = 1U; - break; - case '-': - flags |= FLAGS_LEFT; - format++; - n = 1U; - break; - case '+': - flags |= FLAGS_PLUS; - format++; - n = 1U; - break; - case ' ': - flags |= FLAGS_SPACE; - format++; - n = 1U; - break; - case '#': - flags |= FLAGS_HASH; - format++; - n = 1U; - break; - default : - n = 0U; - break; - } - } while (n); - - // evaluate width field - width = 0U; - if (_is_digit(*format)) { - width = _atoi(&format); - } else if (*format == '*') { - const int w = va_arg(va, int); - if (w < 0) { - flags |= FLAGS_LEFT; // reverse padding - width = (unsigned int) -w; - } else { - width = (unsigned int) w; - } - format++; - } - - // evaluate precision field - precision = 0U; - if (*format == '.') { - flags |= FLAGS_PRECISION; - format++; - if (_is_digit(*format)) { - precision = _atoi(&format); - } else if (*format == '*') { - const int prec = (int) va_arg(va, int); - precision = prec > 0 ? (unsigned int) prec : 0U; - format++; - } - } - - // evaluate length field - switch (*format) { - case 'l' : - flags |= FLAGS_LONG; - format++; - if (*format == 'l') { - flags |= FLAGS_LONG_LONG; - format++; - } - break; - case 'h' : - flags |= FLAGS_SHORT; - format++; - if (*format == 'h') { - flags |= FLAGS_CHAR; - format++; - } - break; -#if PICO_PRINTF_SUPPORT_PTRDIFF_T - case 't' : - flags |= (sizeof(ptrdiff_t) == sizeof(long) ? FLAGS_LONG : FLAGS_LONG_LONG); - format++; - break; -#endif - case 'j' : - flags |= (sizeof(intmax_t) == sizeof(long) ? FLAGS_LONG : FLAGS_LONG_LONG); - format++; - break; - case 'z' : - flags |= (sizeof(size_t) == sizeof(long) ? FLAGS_LONG : FLAGS_LONG_LONG); - format++; - break; - default : - break; - } - - // evaluate specifier - switch (*format) { - case 'd' : - case 'i' : - case 'u' : - case 'x' : - case 'X' : - case 'o' : - case 'b' : { - // set the base - unsigned int base; - if (*format == 'x' || *format == 'X') { - base = 16U; - } else if (*format == 'o') { - base = 8U; - } else if (*format == 'b') { - base = 2U; - } else { - base = 10U; - flags &= ~FLAGS_HASH; // no hash for dec format - } - // uppercase - if (*format == 'X') { - flags |= FLAGS_UPPERCASE; - } - - // no plus or space flag for u, x, X, o, b - if ((*format != 'i') && (*format != 'd')) { - flags &= ~(FLAGS_PLUS | FLAGS_SPACE); - } - - // ignore '0' flag when precision is given - if (flags & FLAGS_PRECISION) { - flags &= ~FLAGS_ZEROPAD; - } - - // convert the integer - if ((*format == 'i') || (*format == 'd')) { - // signed - if (flags & FLAGS_LONG_LONG) { -#if PICO_PRINTF_SUPPORT_LONG_LONG - const long long value = va_arg(va, long long); - idx = _ntoa_long_long(out, buffer, idx, maxlen, - (unsigned long long) (value > 0 ? value : 0 - value), value < 0, base, - precision, width, flags); -#endif - } else if (flags & FLAGS_LONG) { - const long value = va_arg(va, long); - idx = _ntoa_long(out, buffer, idx, maxlen, (unsigned long) (value > 0 ? value : 0 - value), - value < 0, base, precision, width, flags); - } else { - const int value = (flags & FLAGS_CHAR) ? (char) va_arg(va, int) : (flags & FLAGS_SHORT) - ? (short int) va_arg(va, int) - : va_arg(va, int); - idx = _ntoa_long(out, buffer, idx, maxlen, (unsigned int) (value > 0 ? value : 0 - value), - value < 0, base, precision, width, flags); - } - } else { - // unsigned - if (flags & FLAGS_LONG_LONG) { -#if PICO_PRINTF_SUPPORT_LONG_LONG - idx = _ntoa_long_long(out, buffer, idx, maxlen, va_arg(va, unsigned long long), false, base, - precision, width, flags); -#endif - } else if (flags & FLAGS_LONG) { - idx = _ntoa_long(out, buffer, idx, maxlen, va_arg(va, unsigned long), false, base, precision, - width, flags); - } else { - const unsigned int value = (flags & FLAGS_CHAR) ? (unsigned char) va_arg(va, unsigned int) - : (flags & FLAGS_SHORT) - ? (unsigned short int) va_arg(va, - unsigned int) - : va_arg(va, unsigned int); - idx = _ntoa_long(out, buffer, idx, maxlen, value, false, base, precision, width, flags); - } - } - format++; - break; - } - case 'f' : - case 'F' : -#if PICO_PRINTF_SUPPORT_FLOAT - if (*format == 'F') flags |= FLAGS_UPPERCASE; - idx = _ftoa(out, buffer, idx, maxlen, va_arg(va, double), precision, width, flags); -#else - for(int i=0;i<2;i++) out('?', buffer, idx++, maxlen); - va_arg(va, double); -#endif - format++; - break; - case 'e': - case 'E': - case 'g': - case 'G': -#if PICO_PRINTF_SUPPORT_FLOAT && PICO_PRINTF_SUPPORT_EXPONENTIAL - if ((*format == 'g') || (*format == 'G')) flags |= FLAGS_ADAPT_EXP; - if ((*format == 'E') || (*format == 'G')) flags |= FLAGS_UPPERCASE; - idx = _etoa(out, buffer, idx, maxlen, va_arg(va, double), precision, width, flags); -#else - for(int i=0;i<2;i++) out('?', buffer, idx++, maxlen); - va_arg(va, double); -#endif - format++; - break; - case 'c' : { - unsigned int l = 1U; - // pre padding - if (!(flags & FLAGS_LEFT)) { - while (l++ < width) { - out(' ', buffer, idx++, maxlen); - } - } - // char output - out((char) va_arg(va, int), buffer, idx++, maxlen); - // post padding - if (flags & FLAGS_LEFT) { - while (l++ < width) { - out(' ', buffer, idx++, maxlen); - } - } - format++; - break; - } - - case 's' : { - const char *p = va_arg(va, char*); - unsigned int l = _strnlen_s(p, precision ? precision : (size_t) -1); - // pre padding - if (flags & FLAGS_PRECISION) { - l = (l < precision ? l : precision); - } - if (!(flags & FLAGS_LEFT)) { - while (l++ < width) { - out(' ', buffer, idx++, maxlen); - } - } - // string output - while ((*p != 0) && (!(flags & FLAGS_PRECISION) || precision--)) { - out(*(p++), buffer, idx++, maxlen); - } - // post padding - if (flags & FLAGS_LEFT) { - while (l++ < width) { - out(' ', buffer, idx++, maxlen); - } - } - format++; - break; - } - - case 'p' : { - width = sizeof(void *) * 2U; - flags |= FLAGS_ZEROPAD | FLAGS_UPPERCASE; -#if PICO_PRINTF_SUPPORT_LONG_LONG - const bool is_ll = sizeof(uintptr_t) == sizeof(long long); - if (is_ll) { - idx = _ntoa_long_long(out, buffer, idx, maxlen, (uintptr_t) va_arg(va, void*), false, 16U, - precision, width, flags); - } else { -#endif - idx = _ntoa_long(out, buffer, idx, maxlen, (unsigned long) ((uintptr_t) va_arg(va, void*)), false, - 16U, precision, width, flags); -#if PICO_PRINTF_SUPPORT_LONG_LONG - } -#endif - format++; - break; - } - - case '%' : - out('%', buffer, idx++, maxlen); - format++; - break; - - default : - out(*format, buffer, idx++, maxlen); - format++; - break; - } - } - - // termination - out((char) 0, buffer, idx < maxlen ? idx : maxlen - 1U, maxlen); - - // return written chars without terminating \0 - return (int) idx; -} - - -/////////////////////////////////////////////////////////////////////////////// - -int WRAPPER_FUNC(sprintf)(char *buffer, const char *format, ...) { - va_list va; - va_start(va, format); - const int ret = _vsnprintf(_out_buffer, buffer, (size_t) -1, format, va); - va_end(va); - return ret; -} - -int WRAPPER_FUNC(snprintf)(char *buffer, size_t count, const char *format, ...) { - va_list va; - va_start(va, format); - const int ret = _vsnprintf(_out_buffer, buffer, count, format, va); - va_end(va); - return ret; -} - -int WRAPPER_FUNC(vsnprintf)(char *buffer, size_t count, const char *format, va_list va) { - return _vsnprintf(_out_buffer, buffer, count, format, va); -} - -int vfctprintf(void (*out)(char character, void *arg), void *arg, const char *format, va_list va) { - const out_fct_wrap_type out_fct_wrap = {out, arg}; - return _vsnprintf(_out_fct, (char *) (uintptr_t) &out_fct_wrap, (size_t) -1, format, va); -} - -#if LIB_PICO_PRINTF_PICO -#if !PICO_PRINTF_ALWAYS_INCLUDED -/** - * Output a character to a custom device like UART, used by the printf() function - * This function is declared here only. You have to write your custom implementation somewhere - * \param character Character to output - */ -static void _putchar(char character) { - putchar(character); -} - -// internal _putchar wrapper -static inline void _out_char(char character, void *buffer, size_t idx, size_t maxlen) { - (void) buffer; - (void) idx; - (void) maxlen; - if (character) { - _putchar(character); - } -} - -bool weak_raw_printf(const char *fmt, ...) { - va_list va; - va_start(va, fmt); - bool rc = weak_raw_vprintf(fmt, va); - va_end(va); - return rc; -} - -bool weak_raw_vprintf(const char *fmt, va_list args) { - if (lazy_vsnprintf) { - char buffer[1]; - lazy_vsnprintf(_out_char, buffer, (size_t) -1, fmt, args); - return true; - } else { - puts(fmt); - return false; - } -} -#endif -#endif diff --git a/lib/main/pico-sdk/rp2_common/pico_printf/printf_none.S b/lib/main/pico-sdk/rp2_common/pico_printf/printf_none.S deleted file mode 100644 index 0148f265fb..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_printf/printf_none.S +++ /dev/null @@ -1,29 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "pico/asm_helper.S" -#include "pico/bootrom/sf_table.h" - -pico_default_asm_setup - -wrapper_func sprintf -wrapper_func snprintf -wrapper_func vsnprintf -// pico_stdio may itself overwrite printf, so we want to support that (hence weak), but override it -// here to in case pico_stdio is not used -weak_wrapper_func printf -regular_func printf_none_assert -#ifndef __riscv - push {lr} // keep stack trace sane - ldr r0, =str - bl panic -#else - la a0, str - call panic -#endif - -str: - .asciz "printf support is disabled" \ No newline at end of file diff --git a/lib/main/pico-sdk/rp2_common/pico_rand/include/pico/rand.h b/lib/main/pico-sdk/rp2_common/pico_rand/include/pico/rand.h deleted file mode 100644 index b0a337f246..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_rand/include/pico/rand.h +++ /dev/null @@ -1,217 +0,0 @@ -/* - * Copyright (c) 2022 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _PICO_RAND_H -#define _PICO_RAND_H - -#include "pico.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** \file pico/rand.h - * \defgroup pico_rand pico_rand - * - * \brief Random Number Generator API - * - * This module generates random numbers at runtime utilizing a number of possible entropy - * sources and uses those sources to modify the state of a 128-bit 'Pseudo - * Random Number Generator' implemented in software. - * - * The random numbers (32 to 128 bit) to be supplied are read from the PRNG which is used - * to help provide a large number space. - * - * The following (multiple) sources of entropy are available (of varying quality), each enabled by a #define: - * - * - The Ring Oscillator (ROSC) (\ref PICO_RAND_ENTROPY_SRC_ROSC == 1): - * \ref PICO_RAND_ROSC_BIT_SAMPLE_COUNT bits are gathered from the ring oscillator "random bit" and mixed in each - * time. This should not be used if the ROSC is off, or the processor is running from - * the ROSC. - * \note the maximum throughput of ROSC bit sampling is controlled by PICO_RAND_MIN_ROSC_BIT_SAMPLE_TIME_US which defaults - * to 10us, i.e. 100,000 bits per second. - * - Time (\ref PICO_RAND_ENTROPY_SRC_TIME == 1): The 64-bit microsecond timer is mixed in each time. - * - Bus Performance Counter (\ref PICO_RAND_ENTROPY_SRC_BUS_PERF_COUNTER == 1): One of the bus fabric's performance - * counters is mixed in each time. - * - * \note All entropy sources are hashed before application to the PRNG state machine. - * - * The \em first time a random number is requested, the 128-bit PRNG state - * must be seeded. Multiple entropy sources are also available for the seeding operation: - * - * - The Ring Oscillator (ROSC) (\ref PICO_RAND_SEED_ENTROPY_SRC_ROSC == 1): - * 64 bits are gathered from the ring oscillator "random bit" and mixed into the seed. - * - Time (\ref PICO_RAND_SEED_ENTROPY_SRC_TIME == 1): The 64-bit microsecond timer is mixed into the seed. - * - Board Identifier (PICO_RAND_SEED_ENTROPY_SRC_BOARD_ID == 1): The board id via \ref pico_get_unique_board_id - * is mixed into the seed. - * - RAM hash (\ref PICO_RAND_SEED_ENTROPY_SRC_RAM_HASH (\ref PICO_RAND_SEED_ENTROPY_SRC_RAM_HASH): The hashed contents of a - * subset of RAM are mixed in. Initial RAM contents are undefined on power up, so provide a reasonable source of entropy. - * By default the last 1K of RAM (which usually contains the core 0 stack) is hashed, which may also provide for differences - * after each warm reset. - * - * With default settings, the seed generation takes approximately 1 millisecond while - * subsequent random numbers generally take between 10 and 20 microseconds to generate. - * - * pico_rand methods may be safely called from either core or from an IRQ, but be careful in the latter case as - * the calls may block for a number of microseconds waiting on more entropy. - */ - -// --------------- -// ENTROPY SOURCES -// --------------- - -// PICO_CONFIG: PICO_RAND_ENTROPY_SRC_ROSC, Enable/disable use of ROSC as an entropy source, type=bool, default=1 if no hardware TRNG, group=pico_rand -#ifndef PICO_RAND_ENTROPY_SRC_ROSC -#if !HAS_RP2350_TRNG -#define PICO_RAND_ENTROPY_SRC_ROSC 1 -#endif -#endif - -// PICO_CONFIG: PICO_RAND_ENTROPY_SRC_TRNG, Enable/disable use of hardware TRNG as an entropy source, type=bool, default=1 if hardware TRNG is available, group=pico_rand -#ifndef PICO_RAND_ENTROPY_SRC_TRNG -#if HAS_RP2350_TRNG -#define PICO_RAND_ENTROPY_SRC_TRNG 1 -#endif -#endif - -// PICO_CONFIG: PICO_RAND_ENTROPY_SRC_TIME, Enable/disable use of hardware timestamp as an entropy source, type=bool, default=1, group=pico_rand -#ifndef PICO_RAND_ENTROPY_SRC_TIME -#define PICO_RAND_ENTROPY_SRC_TIME 1 -#endif - -// PICO_CONFIG: PICO_RAND_ENTROPY_SRC_BUS_PERF_COUNTER, Enable/disable use of a bus performance counter as an entropy source, type=bool, default=1 if no hardware TRNG, group=pico_rand -#ifndef PICO_RAND_ENTROPY_SRC_BUS_PERF_COUNTER -#if !HAS_RP2350_TRNG -#define PICO_RAND_ENTROPY_SRC_BUS_PERF_COUNTER 1 -#endif -#endif - -// -------------------- -// SEED ENTROPY SOURCES -// -------------------- - -// PICO_CONFIG: PICO_RAND_SEED_ENTROPY_SRC_ROSC, Enable/disable use of ROSC as an entropy source for the random seed, type=bool, default=PICO_RAND_ENTROPY_SRC_ROSC, group=pico_rand -#ifndef PICO_RAND_SEED_ENTROPY_SRC_ROSC -#define PICO_RAND_SEED_ENTROPY_SRC_ROSC PICO_RAND_ENTROPY_SRC_ROSC -#endif - -// PICO_CONFIG: PICO_RAND_SEED_ENTROPY_SRC_TRNG, Enable/disable use of hardware TRNG as an entropy source for the random seed, type=bool, default=PICO_RAND_ENTROPY_SRC_TRNG, group=pico_rand -#if !defined(PICO_RAND_SEED_ENTROPY_SRC_TRNG) && HAS_RP2350_TRNG -#define PICO_RAND_SEED_ENTROPY_SRC_TRNG PICO_RAND_ENTROPY_SRC_TRNG -#endif - -// PICO_CONFIG: PICO_RAND_SEED_ENTROPY_SRC_TIME, Enable/disable use of hardware timestamp as an entropy source for the random seed, type=bool, default=PICO_RAND_ENTROPY_SRC_TIME, group=pico_rand -#ifndef PICO_RAND_SEED_ENTROPY_SRC_TIME -#define PICO_RAND_SEED_ENTROPY_SRC_TIME PICO_RAND_ENTROPY_SRC_TIME -#endif - -// PICO_CONFIG: PICO_RAND_SEED_ENTROPY_SRC_BUS_PERF_COUNTER, Enable/disable use of a bus performance counter as an entropy source for the random seed, type=bool, default=PICO_RAND_ENTROPY_SRC_BUS_PERF_COUNTER, group=pico_rand -#ifndef PICO_RAND_SEED_ENTROPY_SRC_BUS_PERF_COUNTER -#define PICO_RAND_SEED_ENTROPY_SRC_BUS_PERF_COUNTER PICO_RAND_ENTROPY_SRC_BUS_PERF_COUNTER -#endif - -// PICO_CONFIG: PICO_RAND_SEED_ENTROPY_SRC_BOOT_RANDOM, Enable/disable use of the per boot random number as an entropy source for the random seed, type=bool, default=0 on RP2040 which has none, group=pico_rand -#ifndef PICO_RAND_SEED_ENTROPY_SRC_BOOT_RANDOM -#if !PICO_RP2040 -#define PICO_RAND_SEED_ENTROPY_SRC_BOOT_RANDOM 1 -#endif -#endif - -// PICO_CONFIG: PICO_RAND_SEED_ENTROPY_SRC_BOARD_ID, Enable/disable use of board id as part of the random seed, type=bool, default=not PICO_RAND_SEED_ENTROPY_SRC_BOOT_RANDOM, group=pico_rand -#ifndef PICO_RAND_SEED_ENTROPY_SRC_BOARD_ID -#define PICO_RAND_SEED_ENTROPY_SRC_BOARD_ID (!PICO_RAND_SEED_ENTROPY_SRC_BOOT_RANDOM) -#endif - -// PICO_CONFIG: PICO_RAND_SEED_ENTROPY_SRC_RAM_HASH, Enable/disable use of a RAM hash as an entropy source for the random seed, type=bool, default=1 if no hardware TRNG, group=pico_rand -#ifndef PICO_RAND_SEED_ENTROPY_SRC_RAM_HASH -#if !HAS_RP2350_TRNG -#define PICO_RAND_SEED_ENTROPY_SRC_RAM_HASH 1 -#endif -#endif - -// --------------------------------- -// PICO_RAND_ENTROPY_SRC_ROSC CONFIG -// --------------------------------- - -// PICO_CONFIG: PICO_RAND_ROSC_BIT_SAMPLE_COUNT, Number of samples to take of the ROSC random bit per random number generation , min=1, max=64, default=1, group=pico_rand -#ifndef PICO_RAND_ROSC_BIT_SAMPLE_COUNT -#define PICO_RAND_ROSC_BIT_SAMPLE_COUNT 1 -#endif - -// PICO_CONFIG: PICO_RAND_MIN_ROSC_BIT_SAMPLE_TIME_US, Define a default minimum time between sampling the ROSC random bit, min=5, max=20, default=10, group=pico_rand -#ifndef PICO_RAND_MIN_ROSC_BIT_SAMPLE_TIME_US -// (Arbitrary / tested) minimum time between sampling the ROSC random bit -#define PICO_RAND_MIN_ROSC_BIT_SAMPLE_TIME_US 10u -#endif - -// --------------------------------------------- -// PICO_RAND_ENTROPY_SRC_BUS_PERF_COUNTER CONFIG -// --------------------------------------------- - -// PICO_CONFIG: PICO_RAND_BUS_PERF_COUNTER_INDEX, Bus performance counter index to use for sourcing entropy, min=0, max=3, default=Undefined meaning pick one that is not counting any valid event already, group=pico_rand -// this is deliberately undefined by default, meaning the code will pick that appears unused -#if 0 // make tooling checks happy -#define PICO_RAND_BUS_PERF_COUNTER_INDEX 0 -#endif - -// PICO_CONFIG: PICO_RAND_BUS_PERF_COUNTER_EVENT, Bus performance counter event to use for sourcing entropy, default=arbiter_sram5_perf_event_access, group=pico_rand -#ifndef PICO_RAND_BUS_PERF_COUNTER_EVENT -#define PICO_RAND_BUS_PERF_COUNTER_EVENT arbiter_sram5_perf_event_access -#endif - -// ------------------------------------------ -// PICO_RAND_SEED_ENTROPY_SRC_RAM_HASH CONFIG -// ------------------------------------------ - -// PICO_CONFIG: PICO_RAND_RAM_HASH_END, End of address in RAM (non-inclusive) to hash during pico_rand seed initialization, default=SRAM_END, group=pico_rand -#ifndef PICO_RAND_RAM_HASH_END -#define PICO_RAND_RAM_HASH_END SRAM_END -#endif -// PICO_CONFIG: PICO_RAND_RAM_HASH_START, Start of address in RAM (inclusive) to hash during pico_rand seed initialization, default=PICO_RAND_RAM_HASH_END - 1024, group=pico_rand -#ifndef PICO_RAND_RAM_HASH_START -#define PICO_RAND_RAM_HASH_START (PICO_RAND_RAM_HASH_END - 1024u) -#endif - -// We provide a maximum of 128 bits entropy in one go -typedef struct rng_128 { - uint64_t r[2]; -} rng_128_t; - -/*! \brief Get 128-bit random number - * \ingroup pico_rand - * - * This method may be safely called from either core or from an IRQ, but be careful in the latter case as - * the call may block for a number of microseconds waiting on more entropy. - * - * \param rand128 Pointer to storage to accept a 128-bit random number - */ -void get_rand_128(rng_128_t *rand128); - -/*! \brief Get 64-bit random number - * \ingroup pico_rand - * - * This method may be safely called from either core or from an IRQ, but be careful in the latter case as - * the call may block for a number of microseconds waiting on more entropy. - * - * \return 64-bit random number - */ -uint64_t get_rand_64(void); - -/*! \brief Get 32-bit random number - * \ingroup pico_rand - * - * This method may be safely called from either core or from an IRQ, but be careful in the latter case as - * the call may block for a number of microseconds waiting on more entropy. - * - * \return 32-bit random number - */ -uint32_t get_rand_32(void); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/lib/main/pico-sdk/rp2_common/pico_rand/rand.c b/lib/main/pico-sdk/rp2_common/pico_rand/rand.c deleted file mode 100644 index 794c63e4cd..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_rand/rand.c +++ /dev/null @@ -1,381 +0,0 @@ -/* - * Copyright (c) 2022 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -/* xoroshiro128ss(), rotl(): - - Written in 2018 by David Blackman and Sebastiano Vigna (vigna@acm.org) - - To the extent possible under law, the author has dedicated all copyright - and related and neighboring rights to this software to the public domain - worldwide. This software is distributed without any warranty. - - See - - splitmix64() implementation: - - Written in 2015 by Sebastiano Vigna (vigna@acm.org) - To the extent possible under law, the author has dedicated all copyright - and related and neighboring rights to this software to the public domain - worldwide. This software is distributed without any warranty. - - See -*/ - -#include "pico/rand.h" -#include "pico/unique_id.h" -#include "pico/time.h" -#include "hardware/clocks.h" -#include "hardware/structs/rosc.h" -#include "hardware/structs/busctrl.h" -#include "hardware/sync.h" - -static bool rng_initialised = false; - -// Note: By design, do not initialise any of the variables that hold entropy, -// they may have useful junk in them, either from power-up or a previous boot. -static rng_128_t __uninitialized_ram(rng_state); -#if PICO_RAND_SEED_ENTROPY_SRC_RAM_HASH -static uint64_t __uninitialized_ram(ram_hash); -#endif - -#if PICO_RAND_ENTROPY_SRC_ROSC | PICO_RAND_SEED_ENTROPY_SRC_ROSC -static uint64_t __uninitialized_ram(rosc_samples); -#endif - -#if PICO_RAND_ENTROPY_SRC_BUS_PERF_COUNTER -static uint8_t bus_counter_idx; -#endif - -/* From the original source: - - This is a fixed-increment version of Java 8's SplittableRandom generator - See http://dx.doi.org/10.1145/2714064.2660195 and - http://docs.oracle.com/javase/8/docs/api/java/util/SplittableRandom.html - - It is a very fast generator passing BigCrush, and it can be useful if - for some reason you absolutely want 64 bits of state; otherwise, we - rather suggest to use a xoroshiro128+ (for moderately parallel - computations) or xorshift1024* (for massively parallel computations) - generator. - - Note: This can be called with any value (i.e. including 0) -*/ -static __noinline uint64_t splitmix64(uint64_t x) { - uint64_t z = x + 0x9E3779B97F4A7C15ull; - z = (z ^ (z >> 30)) * 0xBF58476D1CE4E5B9ull; - z = (z ^ (z >> 27)) * 0x94D049BB133111EBull; - return z ^ (z >> 31); -} - -/* From the original source: - - This is xoroshiro128** 1.0, one of our all-purpose, rock-solid, - small-state generators. It is extremely (sub-ns) fast and it passes all - tests we are aware of, but its state space is large enough only for - mild parallelism. - - For generating just floating-point numbers, xoroshiro128+ is even - faster (but it has a very mild bias, see notes in the comments). - - The state must be seeded so that it is not everywhere zero. If you have - a 64-bit seed, we suggest to seed a splitmix64 generator and use its - output to fill s. -*/ -static inline uint64_t rotl(const uint64_t x, int k) { - return (x << k) | (x >> (64 - k)); -} - -static __noinline uint64_t xoroshiro128ss(rng_128_t *local_rng_state) { - const uint64_t s0 = local_rng_state->r[0]; - uint64_t s1 = local_rng_state->r[1]; - - // Because the state is *modified* outside of this function, there is a - // 1 in 2^128 chance that it could be all zeroes (which is not allowed). - while (s0 == 0 && s1 == 0) { - s1 = time_us_64(); // should not be 0, but loop anyway - } - - const uint64_t result = rotl(s0 * 5, 7) * 9; - - s1 ^= s0; - local_rng_state->r[0] = rotl(s0, 24) ^ s1 ^ (s1 << 16); // a, b - local_rng_state->r[1] = rotl(s1, 37); // c - - return result; -} - -#if PICO_RAND_SEED_ENTROPY_SRC_RAM_HASH -static uint64_t sdbm_hash64_sram(uint64_t hash) { - // save some time by hashing a word at a time - for (uint i = (PICO_RAND_RAM_HASH_START + 3) & ~3; i < PICO_RAND_RAM_HASH_END; i+=4) { - uint32_t c = *(uint32_t *) i; - hash = (uint64_t) c + (hash << 6) + (hash << 16) - hash; - } - return hash; -} -#endif - -#if PICO_RAND_SEED_ENTROPY_SRC_TRNG | PICO_RAND_ENTROPY_SRC_TRNG -#if !HAS_RP2350_TRNG -#error PICO_RAND_SEED_ENTROPY_SRC_TRNG and PICO_RAND_ENTROPY_SRC_TRNG are only valid on RP2350 -#endif -#include "hardware/structs/trng.h" - -uint32_t trng_sample_words[count_of(trng_hw->ehr_data)]; -static_assert(count_of(trng_hw->ehr_data) >= 2 && count_of(trng_hw->ehr_data) < 255, ""); -uint8_t trng_sample_word_count; - -static uint64_t capture_additional_trng_samples(void) { - spin_lock_t *lock = spin_lock_instance(PICO_SPINLOCK_ID_RAND); - uint32_t save = spin_lock_blocking(lock); - if (trng_sample_word_count < 2) { - // Sample one ROSC bit into EHR every cycle, subject to CPU keeping up. - // More temporal resolution to measure ROSC phase noise is better, if we - // use a high quality hash function instead of naive VN decorrelation. - // (Also more metastability events, which are a secondary noise source) - // - // This is out of the loop because writing to this register seems to - // restart the sampling, slowing things down. We don't care if this write - // is skipped as that would just make sampling take longer. - trng_hw->sample_cnt1 = 0; - - // TRNG setup is inside loop in case it is skipped. Disable checks and - // bypass decorrelators, to stream raw TRNG ROSC samples: - trng_hw->trng_debug_control = -1u; - // Start ROSC if it is not already started - trng_hw->rnd_source_enable = -1u; - // Clear all interrupts (including EHR_VLD) -- we will check this - // later, after seeding RCP. - trng_hw->rng_icr = -1u; - - // Wait for 192 ROSC samples to fill EHR, this should take constant time: - while (trng_hw->trng_busy); - - for (uint i = 0; i < count_of(trng_sample_words); i++) { - trng_sample_words[i] = trng_hw->ehr_data[i]; - } - trng_sample_word_count = count_of(trng_sample_words); - - // TRNG is now sampling again, having started after we read the last - // EHR word. Grab some random bits and use them to modulate - // the chain length, to reduce chance of injection locking: - trng_hw->trng_config = rng_state.r[0]; - } - trng_sample_word_count -= 2; - uint64_t rc = trng_sample_words[trng_sample_word_count] | - (((uint64_t)trng_sample_words[trng_sample_word_count + 1]) << 32); - spin_unlock(lock, save); - return rc; -} - -#endif -#if PICO_RAND_SEED_ENTROPY_SRC_ROSC | PICO_RAND_ENTROPY_SRC_ROSC -/* gather an additional n bits of entropy, and shift them into the 64 bit entropy counter */ -static uint64_t capture_additional_rosc_samples(uint n) { - static absolute_time_t next_sample_time; - - // provide an override if someone really wants it, but disabling ROSC as an entropy source makes more sense -#if !PICO_RAND_DISABLE_ROSC_CHECK - // check that the ROSC is running but that the processors are NOT running from it - hard_assert((rosc_hw->status & ROSC_STATUS_ENABLED_BITS) && - ((clocks_hw->clk[clk_sys].ctrl & CLOCKS_CLK_SYS_CTRL_AUXSRC_BITS) != (CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_ROSC_CLKSRC << CLOCKS_CLK_SYS_CTRL_AUXSRC_LSB))); -#endif - - bool in_exception = __get_current_exception(); - assert(n); // save us having to special case samples for this - uint64_t samples = 0; - for(uint i=0; irandombit & 1u; - // use of relative time to now, rather than offset from before makes things - // a bit less predictable at the cost of some speed. - next_sample_time = make_timeout_time_us(PICO_RAND_MIN_ROSC_BIT_SAMPLE_TIME_US); - bit_done = true; - if (i == n - 1) { - // samples has our random bits, so let's mix them in now - samples = rosc_samples = (rosc_samples << n) | samples; - } - } - spin_unlock(lock, save); - } while (!bit_done); - } - return samples; -} -#endif - -#if PICO_RAND_SEED_ENTROPY_SRC_BOOT_RANDOM -#include "pico/bootrom.h" -#endif - -static void initialise_rand(void) { - rng_128_t local_rng_state = local_rng_state; - uint which = 0; -#if PICO_RAND_SEED_ENTROPY_SRC_RAM_HASH - ram_hash = sdbm_hash64_sram(ram_hash); - local_rng_state.r[which] ^= splitmix64(ram_hash); - which ^= 1; -#endif - -#if PICO_RAND_SEED_ENTROPY_SRC_BOARD_ID - static_assert(PICO_UNIQUE_BOARD_ID_SIZE_BYTES == sizeof(uint64_t), - "Code below requires that 'board_id' is 64-bits in size"); - - // Note! The safety of the length assumption here is protected by a 'static_assert' above - union unique_id_u { - pico_unique_board_id_t board_id_native; - uint64_t board_id_u64; - } unique_id; - // Note! The safety of the length assumption here is protected by a 'static_assert' above - pico_get_unique_board_id(&unique_id.board_id_native); - local_rng_state.r[which] ^= splitmix64(unique_id.board_id_u64); - which ^= 1; -#endif - -#if PICO_RAND_SEED_ENTROPY_SRC_ROSC - // this is really quite slow (10ms per iteration), and I'm not sure that it adds value over the 64 random bits -// uint ref_khz = clock_get_hz(clk_ref) / 100; -// for (int i = 0; i < 5; i++) { -// // Apply hash of the rosc frequency, limited but still 'extra' entropy -// uint measurement = frequency_count_raw(CLOCKS_FC0_SRC_VALUE_ROSC_CLKSRC, ref_khz); -// local_rng_state.r[which] ^= splitmix64(measurement); -// (void) xoroshiro128ss(&local_rng_state); //churn to mix seed sources -// } - - // Gather a full ROSC sample array with sample bits - local_rng_state.r[which] ^= splitmix64(capture_additional_rosc_samples(8 * sizeof(rosc_samples))); - which ^= 1; -#endif - -#if PICO_RAND_SEED_ENTROPY_SRC_BOOT_RANDOM - // Mix in boot random. - union { - uint64_t u64[2]; - uint32_t u32[4]; - } br; - rom_get_boot_random(br.u32); - local_rng_state.r[which] ^= splitmix64(br.u64[0]); - local_rng_state.r[which ^ 1] ^= splitmix64(br.u64[1]); -#endif - -#if PICO_RAND_SEED_ENTROPY_SRC_TIME - // Mix in hashed time. This is [possibly] predictable boot-to-boot - // but will vary application-to-application. - local_rng_state.r[which] ^= splitmix64(time_us_64()); - which ^= 1; -#endif -#if PICO_RAND_SEED_ENTROPY_SRC_TRNG - local_rng_state.r[which] ^= splitmix64(capture_additional_trng_samples()); - which ^= 1; -#endif - - spin_lock_t *lock = spin_lock_instance(PICO_SPINLOCK_ID_RAND); - uint32_t save = spin_lock_blocking(lock); - if (!rng_initialised) { -#if PICO_RAND_SEED_ENTROPY_SRC_BUS_PERF_COUNTER -#if !PICO_RAND_BUS_PERF_COUNTER_INDEX - int idx = -1; - for(uint i = 0; i < count_of(busctrl_hw->counter); i++) { - if (busctrl_hw->counter[i].sel == BUSCTRL_PERFSEL0_RESET) { - idx = (int)i; - break; - } - } - hard_assert(idx != -1); - bus_counter_idx = (uint8_t)idx; -#else - bus_counter_idx = (uint8_t)PICO_RAND_BUS_PERF_COUNTER_INDEX; -#endif - busctrl_hw->counter[bus_counter_idx].sel = PICO_RAND_BUS_PERF_COUNTER_EVENT; -#endif - (void) xoroshiro128ss(&local_rng_state); - rng_state = local_rng_state; - rng_initialised = true; - } - spin_unlock(lock, save); -} - -uint64_t get_rand_64(void) { - if (!rng_initialised) { - // Do not provide 'RNs' until the system has been initialised. Note: - // The first initialisation can be quite time-consuming depending on - // the amount of RAM hashed, see RAM_HASH_START and RAM_HASH_END - initialise_rand(); - } - - static volatile uint8_t check_byte; - rng_128_t local_rng_state = rng_state; - uint8_t local_check_byte = check_byte; - // Modify PRNG state with the run-time entropy sources, - // hashed to reduce correlation with previous modifications. - uint which = 0; -#if PICO_RAND_ENTROPY_SRC_TIME - local_rng_state.r[which] ^= splitmix64(time_us_64()); - which ^= 1; -#endif -#if PICO_RAND_ENTROPY_SRC_ROSC - local_rng_state.r[which] ^= splitmix64(capture_additional_rosc_samples(PICO_RAND_ROSC_BIT_SAMPLE_COUNT)); - which ^= 1; -#endif -#if PICO_RAND_ENTROPY_SRC_TRNG - uint64_t foo = capture_additional_trng_samples(); - local_rng_state.r[which] ^= splitmix64(foo); - which ^= 1; -#endif -#if PICO_RAND_ENTROPY_SRC_BUS_PERF_COUNTER - uint32_t bus_counter_value = busctrl_hw->counter[bus_counter_idx].value; - // counter is saturating, so clear it if it has reached saturation - if (bus_counter_value == BUSCTRL_PERFCTR0_BITS) { - busctrl_hw->counter[bus_counter_idx].value = 0; - } - local_rng_state.r[which] ^= splitmix64(bus_counter_value); - which ^= 1; -#endif - - spin_lock_t *lock = spin_lock_instance(PICO_SPINLOCK_ID_RAND); - uint32_t save = spin_lock_blocking(lock); - if (local_check_byte != check_byte) { - // someone got a random number in the interim, so mix it in - local_rng_state.r[0] ^= rng_state.r[0]; - local_rng_state.r[1] ^= rng_state.r[1]; - } - // Generate a 64-bit RN from the modified PRNG state. - // Note: This also "churns" the 128-bit state for next time. - uint64_t rand64 = xoroshiro128ss(&local_rng_state); - rng_state = local_rng_state; - check_byte++; - spin_unlock(lock, save); - - return rand64; -} - -void get_rand_128(rng_128_t *ptr128) { - ptr128->r[0] = get_rand_64(); - ptr128->r[1] = get_rand_64(); -} - -uint32_t get_rand_32(void) { - return (uint32_t) get_rand_64(); -} diff --git a/lib/main/pico-sdk/rp2_common/pico_runtime/include/pico/runtime.h b/lib/main/pico-sdk/rp2_common/pico_runtime/include/pico/runtime.h deleted file mode 100644 index 35d871d92d..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_runtime/include/pico/runtime.h +++ /dev/null @@ -1,70 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _PICO_RUNTIME_H -#define _PICO_RUNTIME_H - -#include "pico.h" - -/** \file runtime.h -* \defgroup pico_runtime pico_runtime -* \brief Basic runtime support for running pre-main initializers provided by other libraries -* -* This library aggregates the following other libraries (if available): -* -* * \ref hardware_uart -* * \ref pico_bit_ops -* * \ref pico_divider -* * \ref pico_double -* * \ref pico_int64_ops -* * \ref pico_float -* * \ref pico_malloc -* * \ref pico_mem_ops -* * \ref pico_atomic -* * \ref pico_cxx_options -* * \ref pico_standard_binary_info -* * \ref pico_standard_link -* * \ref pico_sync -* * \ref pico_printf -* * \ref pico_crt0 -* * \ref pico_clib_interface -* * \ref pico_stdio -*/ - -#ifdef __cplusplus -extern "C" { -#endif - -#ifndef __ASSEMBLER__ -/*! \brief Run all the initializations that are usually called by crt0.S before entering main - * \ingroup pico_runtime - * - * This method is useful to set up the runtime after performing a watchdog or powman reboot - * via scratch vector. - */ -void runtime_init(void); - -void runtime_run_initializers(void); -void runtime_run_per_core_initializers(void); - -#ifndef PICO_RUNTIME_INIT_FUNC -#define PICO_RUNTIME_INIT_FUNC(func, priority_string) uintptr_t __used __attribute__((section(".preinit_array." priority_string))) __pre_init_ ## func = (uintptr_t)(void (*)(void)) (func) -#endif -#else -#ifndef PICO_RUNTIME_INIT_FUNC -#define PICO_RUNTIME_INIT_FUNC(func, priority_string) __pre_init func, priority_string -#endif -#endif -#define PICO_RUNTIME_INIT_FUNC_HW(func, priority_string) PICO_RUNTIME_INIT_FUNC(func, priority_string) -#define PICO_RUNTIME_INIT_FUNC_RUNTIME(func, priority_string) PICO_RUNTIME_INIT_FUNC(func, priority_string) -// priority strings are of the form 00000->99999; we want the per core stuff all at the end, so prefix with ZZZZZ which is clearly after 99999 -#define PICO_RUNTIME_INIT_FUNC_PER_CORE(func, priority_string) PICO_RUNTIME_INIT_FUNC(func, "ZZZZZ." priority_string) - -#ifdef __cplusplus -} -#endif - -#endif \ No newline at end of file diff --git a/lib/main/pico-sdk/rp2_common/pico_runtime/runtime.c b/lib/main/pico-sdk/rp2_common/pico_runtime/runtime.c deleted file mode 100644 index 42452e5bb4..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_runtime/runtime.c +++ /dev/null @@ -1,50 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "pico/runtime.h" -#include "pico/runtime_init.h" - - -void __weak hard_assertion_failure(void) { - panic("Hard assert"); -} - -static void runtime_run_initializers_from(uintptr_t *from) { - - // Start and end points of the constructor list, - // defined by the linker script. - extern uintptr_t __preinit_array_end; - - // Call each function in the list, based on the mask - // We have to take the address of the symbols, as __preinit_array_start *is* - // the first function value, not the address of it. - for (uintptr_t *p = from; p < &__preinit_array_end; p++) { - uintptr_t val = *p; - ((void (*)(void))val)(); - } -} - -void runtime_run_initializers(void) { - extern uintptr_t __preinit_array_start; - runtime_run_initializers_from(&__preinit_array_start); -} - -// We keep the per-core initializers in the standard __preinit_array so a standard C library -// initialization will force the core 0 initialization, however we also want to be able to find -// them after the fact so that we can run them on core 1. Per core initializers have sections -// __preinit_array.ZZZZZ.nnnnn i.e. the ZZZZZ sorts below all the standard __preinit_array.nnnnn -// values, and then we sort within the ZZZZZ. -// -// We create a dummy initializer in __preinit_array.YYYYY (between the standard initializers -// and the per core initializers), so we find the first per core initializer. Whilst we could -// have done this via an entry in the linker script, we want to preserve backwards compatibility -// with RP2040 custom linker scripts. -static void first_per_core_initializer(void) {} -PICO_RUNTIME_INIT_FUNC(first_per_core_initializer, "YYYYY"); - -void runtime_run_per_core_initializers(void) { - runtime_run_initializers_from(&__pre_init_first_per_core_initializer); -} \ No newline at end of file diff --git a/lib/main/pico-sdk/rp2_common/pico_runtime_init/include/pico/runtime_init.h b/lib/main/pico-sdk/rp2_common/pico_runtime_init/include/pico/runtime_init.h deleted file mode 100644 index c6ed4cf8e2..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_runtime_init/include/pico/runtime_init.h +++ /dev/null @@ -1,455 +0,0 @@ -/* - * Copyright (c) 2024 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _PICO_RUNTIME_INITS_H -#define _PICO_RUNTIME_INITS_H - -#include "pico.h" -#include "pico/runtime.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** \file pico/runtime_init.h - * \defgroup pico_runtime_init pico_runtime_init - * - * \brief Main runtime initialization functions required to set up the runtime environment before entering main - * - * The runtime initialization is registration based: - * - * For each step of the initialization there is a 5 digit ordinal which indicates - * the ordering (alphabetic increasing sort of the 5 digits) of the steps. - * - * e.g. for the step "bootrom_reset", there is: - * - * \code - * #ifndef PICO_RUNTIME_INIT_BOOTROM_RESET - * #define PICO_RUNTIME_INIT_BOOTROM_RESET "00050" - * #endif - * \endcode - * - * The user can override the order if they wish, by redefining PICO_RUNTIME_INIT_BOOTROM_RESET - * - * For each step, the automatic initialization may be skipped by defining (in this case) - * PICO_RUNTIME_SKIP_INIT_BOOTROM_RESET = 1. The user can then choose to either omit the step - * completely or register their own replacement initialization. - * - * The default method used to perform the initialization is provided, in case the user - * wishes to call it manually; in this case: - * - * \code - * void runtime_init_bootrom_reset(void); - * \endcode - * - * If PICO_RUNTIME_NO_INIT_BOOTOROM_RESET define is set (NO vs SKIP above), then the function - * is not defined, allowing the user to provide a replacement (and also avoiding - * cases where the default implementation won't compile due to missing dependencies) - */ - -// must have no dependency on any other initialization code -#define PICO_RUNTIME_INIT_EARLIEST "00001" - -// ----------------------------------------------------------------------------------------------- -// Reset of global bootrom state (can be skipped if boot path was via bootrom); not used on RP2040 -// ----------------------------------------------------------------------------------------------- -// PICO_CONFIG: PICO_RUNTIME_SKIP_INIT_BOOTROM_RESET, Skip calling of `runtime_init_bootrom_reset` function during runtime init, type=bool, default=1 on RP2040, group=pico_runtime_init -// PICO_CONFIG: PICO_RUNTIME_NO_INIT_BOOTROM_RESET, Do not include SDK implementation of `runtime_init_bootrom_reset` function, type=bool, default=1 on RP2040, group=pico_runtime_init - -#ifndef PICO_RUNTIME_INIT_BOOTROM_RESET -#define PICO_RUNTIME_INIT_BOOTROM_RESET "00050" -#endif - -#ifndef PICO_RUNTIME_SKIP_INIT_BOOTROM_RESET -#if PICO_RP2040 || (!LIB_PICO_MULTICORE && PICO_NO_FLASH) -#define PICO_RUNTIME_SKIP_INIT_BOOTROM_RESET 1 -#endif -#endif - -#ifndef PICO_RUNTIME_NO_INIT_BOOTROM_RESET -#if PICO_RP2040 || (!LIB_PICO_MULTICORE && PICO_NO_FLASH) -#define PICO_RUNTIME_NO_INIT_BOOTROM_RESET 1 -#endif -#endif - -#ifndef __ASSEMBLER__ -void runtime_init_bootrom_reset(void); -#endif - -// --------------------------------------------------------------------------------------- -// Non-boot core eset of bootrom state, not needed if only using core 0 not used on RP2040 -// --------------------------------------------------------------------------------------- -#ifndef PICO_RUNTIME_INIT_PER_CORE_BOOTROM_RESET -#define PICO_RUNTIME_INIT_PER_CORE_BOOTROM_RESET "00051" -#endif - -// PICO_CONFIG: PICO_RUNTIME_SKIP_INIT_PER_CORE_BOOTROM_RESET, Skip calling of `runtime_init_per_core_bootrom_reset` function during per-core init, type=bool, default=1 on RP2040, group=pico_runtime_init -// PICO_CONFIG: PICO_RUNTIME_NO_INIT_PER_CORE_BOOTROM_RESET, Do not include SDK implementation of `runtime_init_per_core_bootrom_reset` function, type=bool, default=1 on RP2040, group=pico_runtime_init -#ifndef PICO_RUNTIME_SKIP_INIT_PER_CORE_BOOTROM_RESET -#if PICO_RP2040 -#define PICO_RUNTIME_SKIP_INIT_PER_CORE_BOOTROM_RESET 1 -#endif -#endif - -#ifndef PICO_RUNTIME_NO_INIT_PER_CORE_BOOTROM_RESET -#if PICO_RP2040 -#define PICO_RUNTIME_NO_INIT_PER_CORE_BOOTROM_RESET 1 -#endif -#endif - -#ifndef __ASSEMBLER__ -void runtime_init_per_core_bootrom_reset(void); -#endif - -// --------------------------- -// Hazard3 processor IRQ setup -// --------------------------- - -// PICO_CONFIG: PICO_RUNTIME_SKIP_INIT_PER_CORE_H3_IRQ_REGISTERS, Skip calling of `runtime_init_per_core_h3_irq_registers` function during per-core init, type=bool, default=1 on non RISC-V, group=pico_runtime_init - -#ifndef PICO_RUNTIME_INIT_PER_CORE_H3_IRQ_REGISTERS -#define PICO_RUNTIME_INIT_PER_CORE_H3_IRQ_REGISTERS "00060" -#endif - -#ifndef PICO_RUNTIME_SKIP_INIT_PER_CORE_H3_IRQ_REGISTERS -#ifndef __riscv -#define PICO_RUNTIME_SKIP_INIT_PER_CORE_H3_IRQ_REGISTERS 1 -#endif -#endif - -// ------------------------------- -// Earliest resets (no clocks yet) -// ------------------------------- -#ifndef PICO_RUNTIME_INIT_EARLY_RESETS -#define PICO_RUNTIME_INIT_EARLY_RESETS "00100" -#endif - -// PICO_CONFIG: PICO_RUNTIME_SKIP_INIT_EARLY_RESETS, Skip calling of `runtime_init_early_resets` function during runtime init, type=bool, default=1 on RP2040, group=pico_runtime_init -// PICO_CONFIG: PICO_RUNTIME_NO_INIT_EARLY_RESETS, Do not include SDK implementation of `runtime_init_early_resets` function, type=bool, default=1 on RP2040, group=pico_runtime_init -#ifndef PICO_RUNTIME_SKIP_INIT_EARLY_RESETS -#define PICO_RUNTIME_SKIP_INIT_EARLY_RESETS 0 -#endif - -#ifndef PICO_RUNTIME_NO_INIT_EARLY_RESETS -#define PICO_RUNTIME_NO_INIT_EARLY_RESETS 0 -#endif - -#ifndef __ASSEMBLER__ -void runtime_init_early_resets(void); -#endif - -// -------------- -// USB power down -// -------------- -// PICO_CONFIG: PICO_RUNTIME_SKIP_INIT_USB_POWER_DOWN, Skip calling of `runtime_init_usb_power_down` function during runtime init, type=bool, default=0, group=pico_runtime_init -// PICO_CONFIG: PICO_RUNTIME_NO_INIT_USB_POWER_DOWN, Do not include SDK implementation of `runtime_init_usb_power_down` function, type=bool, default=0, group=pico_runtime_init - -#ifndef PICO_RUNTIME_INIT_USB_POWER_DOWN -#define PICO_RUNTIME_INIT_USB_POWER_DOWN "00101" -#endif - -#ifndef PICO_RUNTIME_SKIP_INIT_USB_POWER_DOWN -#define PICO_RUNTIME_SKIP_INIT_USB_POWER_DOWN 0 -#endif - -#ifndef PICO_RUNTIME_NO_INIT_USB_POWER_DOWN -#define PICO_RUNTIME_NO_INIT_USB_POWER_DOWN 0 -#endif - -#ifndef __ASSEMBLER__ -void runtime_init_usb_power_down(void); -#endif - -// ------------------------------------ -// per core co-processor initialization -// ------------------------------------ - -// PICO_CONFIG: PICO_RUNTIME_SKIP_INIT_PER_CORE_ENABLE_COPROCESSORS, Skip calling of `runtime_init_per_core_enable_coprocessors` function during per-core init, type=bool, default=1 on RP2040 or RISC-V, group=pico_runtime_init -// PICO_CONFIG: PICO_RUNTIME_NO_INIT_PER_CORE_ENABLE_COPROCESSORS, Do not include SDK implementation of `runtime_init_per_core_enable_coprocessors` function, type=bool, default=1 on RP2040 or RISC-V, group=pico_runtime_init - -#ifndef PICO_RUNTIME_INIT_PER_CORE_ENABLE_COPROCESSORS -#define PICO_RUNTIME_INIT_PER_CORE_ENABLE_COPROCESSORS "00200" -#endif - -#ifndef PICO_RUNTIME_SKIP_INIT_PER_CORE_ENABLE_COPROCESSORS -#if PICO_RP2040 || defined(__riscv) -#define PICO_RUNTIME_SKIP_INIT_PER_CORE_ENABLE_COPROCESSORS 1 -#endif -#endif - -#ifndef PICO_RUNTIME_NO_INIT_PER_CORE_ENABLE_COPROCESSORS -#if PICO_RP2040 || defined(__riscv) -#define PICO_RUNTIME_NO_INIT_PER_CORE_ENABLE_COPROCESSORS 1 -#endif -#endif - -#ifndef __ASSEMBLER__ -void runtime_init_per_core_enable_coprocessors(void); -#endif - -// AEABI init; this initialization is auto-injected byte pico_aeebi_mem_ops if present -#ifndef PICO_RUNTIME_INIT_AEABI_MEM_OPS -// on RP2040 we need to get memcpy and memset hooked up to bootrom -#define PICO_RUNTIME_INIT_AEABI_MEM_OPS "00300" -#endif - -// AEABI init; this initialization is auto-injected byte pico_aeebi_bit_ops if present -#ifndef PICO_RUNTIME_INIT_AEABI_BIT_OPS -#define PICO_RUNTIME_INIT_AEABI_BIT_OPS "00275" -#endif - -// AEABI init; this initialization is auto-injected byte pico_aeebi_float if present -#ifndef PICO_RUNTIME_INIT_AEABI_FLOAT -#define PICO_RUNTIME_INIT_AEABI_FLOAT "00350" -#endif - -// AEABI init; this initialization is auto-injected byte pico_aeebi_double if present -#ifndef PICO_RUNTIME_INIT_AEABI_DOUBLE -#define PICO_RUNTIME_INIT_AEABI_DOUBLE "00350" -#endif - -// ------------------------ -// Initialization of clocks -// ------------------------ -// PICO_CONFIG: PICO_RUNTIME_SKIP_INIT_CLOCKS, Skip calling of `runtime_init_clocks` function during runtime init, type=bool, default=0, group=pico_runtime_init -// PICO_CONFIG: PICO_RUNTIME_NO_INIT_CLOCKS, Do not include SDK implementation of `runtime_init_clocks` function, type=bool, default=0, group=pico_runtime_init - -#ifndef PICO_RUNTIME_INIT_CLOCKS -// on RP2040 we need some of the AEABI init by this point to do clock math -#define PICO_RUNTIME_INIT_CLOCKS "00500" -#endif - -#ifndef PICO_RUNTIME_SKIP_INIT_CLOCKS -#define PICO_RUNTIME_SKIP_INIT_CLOCKS 0 -#endif - -#ifndef PICO_RUNTIME_NO_INIT_CLOCKS -#define PICO_RUNTIME_NO_INIT_CLOCKS 0 -#endif -#ifndef __ASSEMBLER__ -void runtime_init_clocks(void); - -/*! \brief Initialise the clock hardware - * \ingroup pico_runtime_init - * - * Must be called before any other clock function. - */ -static inline void clocks_init(void) { - // backwards compatibility with earlier SDK - runtime_init_clocks(); -} -#endif - -// ---------------------------------------- -// Remaining h/w initialization post clocks -// ---------------------------------------- -#ifndef PICO_RUNTIME_INIT_POST_CLOCK_RESETS -#define PICO_RUNTIME_INIT_POST_CLOCK_RESETS "00600" -#endif - -// PICO_RUNTIME_INIT_POST_CLOCKS_RESETS defaults to 0 -#ifndef __ASSEMBLER__ -void runtime_init_post_clock_resets(void); -#endif - -// ---------------------------------------- -// RP2040 IE disable for GPIO 26-29 -// ---------------------------------------- - -// PICO_CONFIG: PICO_RUNTIME_SKIP_INIT_RP2040_GPIO_IE_DISABLE, Skip calling of `runtime_init_rp2040_gpio_ie_disable` function during runtime init, type=bool, default=0 on RP2040, group=pico_runtime_init -// PICO_CONFIG: PICO_RUNTIME_NO_INIT_RP2040_GPIO_IE_DISABLE, Do not include SDK implementation of `runtime_init_rp2040_gpio_ie_disable` function, type=bool, default=0 on RP2040, group=pico_runtime_init - -#ifndef PICO_RUNTIME_INIT_RP2040_GPIO_IE_DISABLE -#define PICO_RUNTIME_INIT_RP2040_GPIO_IE_DISABLE "00700" -#endif - -#ifndef PICO_RUNTIME_SKIP_INIT_RP2040_GPIO_IE_DISABLE -#if !PICO_RP2040 || PICO_IE_26_29_UNCHANGED_ON_RESET -#define PICO_RUNTIME_SKIP_INIT_RP2040_GPIO_IE_DISABLE 1 -#endif -#endif -#ifndef PICO_RUNTIME_NO_INIT_RP2040_GPIO_IE_DISABLE -#if !PICO_RP2040 -#define PICO_RUNTIME_NO_INIT_RP2040_GPIO_IE_DISABLE 1 -#endif -#endif - -#ifndef __ASSEMBLER__ -void runtime_init_rp2040_gpio_ie_disable(void); -#endif - -// ----------------------------- -// Reset all spin SIO spin locks -// ----------------------------- - -// PICO_CONFIG: PICO_RUNTIME_SKIP_INIT_SPIN_LOCKS_RESET, Skip calling of `runtime_init_spin_locks_reset` function during runtime init, type=bool, default=0, group=pico_runtime_init -// PICO_CONFIG: PICO_RUNTIME_NO_INIT_SPIN_LOCKS_RESET, Do not include SDK implementation of `runtime_init_spin_locks_reset` function, type=bool, default=0, group=pico_runtime_init - -#ifndef PICO_RUNTIME_INIT_SPIN_LOCKS_RESET -// clearing of all spin locks -#define PICO_RUNTIME_INIT_SPIN_LOCKS_RESET "01000" -#endif - -#ifndef PICO_RUNTIME_SKIP_INIT_SPIN_LOCKS_RESET -#define PICO_RUNTIME_SKIP_INIT_SPIN_LOCKS_RESET 0 -#endif - -#ifndef PICO_RUNTIME_NO_INIT_SPIN_LOCKS_RESET -#define PICO_RUNTIME_NO_INIT_SPIN_LOCKS_RESET 0 -#endif - -#ifndef __ASSEMBLER__ -void runtime_init_spin_locks_reset(void); -#endif - -// ----------------------------- -// Reset all bootram boot locks -// ----------------------------- - -// PICO_CONFIG: PICO_RUNTIME_SKIP_INIT_BOOT_LOCKS_RESET, Skip calling of `runtime_init_boot_locks_reset` function during runtime init, type=bool, default=0, group=pico_runtime_init - -#ifndef PICO_RUNTIME_INIT_BOOT_LOCKS_RESET -// clearing of all spin locks -#define PICO_RUNTIME_INIT_BOOT_LOCKS_RESET "01000" -#endif - -#ifndef PICO_RUNTIME_SKIP_INIT_BOOT_LOCKS_RESET -#define PICO_RUNTIME_SKIP_INIT_BOOT_LOCKS_RESET 0 -#endif -#ifndef __ASSEMBLER__ -void runtime_init_boot_locks_reset(void); -#endif - -// ------------------------------ -// Enable bootrom locking support -// ------------------------------ -// PICO_CONFIG: PICO_RUNTIME_SKIP_INIT_BOOTROM_LOCKING_ENABLE, Skip calling of `runtime_init_bootrom_locking_enable` function during runtime init, type=bool, default=0, group=pico_runtime_init -#ifndef PICO_RUNTIME_INIT_BOOTROM_LOCKING_ENABLE -// clearing of all spin locks -#define PICO_RUNTIME_INIT_BOOTROM_LOCKING_ENABLE "01010" -#endif - -#ifndef PICO_RUNTIME_SKIP_INIT_BOOTROM_LOCKING_ENABLE -#define PICO_RUNTIME_SKIP_INIT_BOOTROM_LOCKING_ENABLE 0 -#endif - -#ifndef __ASSEMBLER__ -void runtime_init_bootrom_locking_enable(void); -#endif - -// PICO_RUNTIME_INIT_MUTEX is registered automatically by pico_sync -// PICO_CONFIG: PICO_RUNTIME_SKIP_INIT_MUTEX, Skip calling of `runtime_init_mutex` function during runtime init, type=bool, default=0, group=pico_runtime_init -// PICO_CONFIG: PICO_RUNTIME_NO_INIT_MUTEX, Do not include SDK implementation of `runtime_init_mutex` function, type=bool, default=0, group=pico_runtime_init - -#ifndef PICO_RUNTIME_INIT_MUTEX -// depends on SPIN_LOCKS -// initialize auto_init mutexes -#define PICO_RUNTIME_INIT_MUTEX "01100" -#endif - -#ifndef PICO_RUNTIME_SKIP_INIT_MUTEX -#define PICO_RUNTIME_SKIP_INIT_MUTEX 0 -#endif - -#ifndef PICO_RUNTIME_NO_INIT_MUTEX -#define PICO_RUNTIME_NO_INIT_MUTEX 0 -#endif - -// ------------------------------------------------------------ -// Initialization of IRQs, added by hardware_irq -// ------------------------------------------------------------ - -#ifndef PICO_RUNTIME_INIT_PER_CORE_IRQ_PRIORITIES -#define PICO_RUNTIME_INIT_PER_CORE_IRQ_PRIORITIES "01200" -#endif - -// PICO_RUNTIME_SKIP_INIT_PER_CORE_TLS_SETUP defaults to 0 -#ifndef PICO_RUNTIME_INIT_PER_CORE_TLS_SETUP -#define PICO_RUNTIME_INIT_PER_CORE_TLS_SETUP "10060" -#endif - -// PICO_CONFIG: PICO_RUNTIME_SKIP_INIT_INSTALL_RAM_VECTOR_TABLE, Skip calling of `runtime_init_install_ram_vector_table` function during runtime init, type=bool, default=0 unless RISC-V or RAM binary, group=pico_runtime_init -// PICO_CONFIG: PICO_RUNTIME_NO_INIT_INSTALL_RAM_VECTOR_TABLE, Do not include SDK implementation of `runtime_init_install_ram_vector_table` function, type=bool, default=0 unless RISC-V or RAM binary, group=pico_runtime_init -#ifndef PICO_RUNTIME_INIT_INSTALL_RAM_VECTOR_TABLE -#define PICO_RUNTIME_INIT_INSTALL_RAM_VECTOR_TABLE "10080" -#endif - -// ------------------------------------------------------ -// Copy of ROM vector table to RAM; not used on RISC-V or -// no_flash which has a RAM vector table anyway -// ------------------------------------------------------ - -#ifndef PICO_RUNTIME_SKIP_INIT_INSTALL_RAM_VECTOR_TABLE -#if PICO_NO_RAM_VECTOR_TABLE || PICO_NO_FLASH || defined(__riscv) -#define PICO_RUNTIME_SKIP_INIT_INSTALL_RAM_VECTOR_TABLE 1 -#endif -#endif - -#ifndef PICO_RUNTIME_NO_INIT_INSTALL_RAM_VECTOR_TABLE -#if PICO_NO_RAM_VECTOR_TABLE || PICO_NO_FLASH || defined(__riscv) -#define PICO_RUNTIME_NO_INIT_INSTALL_RAM_VECTOR_TABLE 1 -#endif -#endif - -// ------------------------------------------------------------ -// Default alarm pool initialization, added by pico_time unless -// PICO_TIME_DEFAULT_ALARM_POOL_DISABLED == 1 -// ------------------------------------------------------------ -#ifndef PICO_RUNTIME_INIT_DEFAULT_ALARM_POOL -#define PICO_RUNTIME_INIT_DEFAULT_ALARM_POOL "11000" -#endif - -// PICO_CONFIG: PICO_RUNTIME_SKIP_INIT_DEFAULT_ALARM_POOL, Skip calling of `runtime_init_default_alarm_pool` function during runtime init, type=bool, default=1 if `PICO_TIME_DEFAULT_ALARM_POOL_DISABLED` is 1, group=pico_runtime_init -// PICO_CONFIG: PICO_RUNTIME_NO_INIT_DEFAULT_ALARM_POOL, Do not include SDK implementation of `runtime_init_default_alarm_pool` function, type=bool, default=1 if `PICO_TIME_DEFAULT_ALARM_POOL_DISABLED` is , group=pico_runtime_init -#ifndef PICO_RUNTIME_SKIP_INIT_DEFAULT_ALARM_POOL -#if PICO_TIME_DEFAULT_ALARM_POOL_DISABLED -#define PICO_RUNTIME_SKIP_INIT_DEFAULT_ALARM_POOL 1 -#endif -#endif - -#ifndef PICO_RUNTIME_NO_INIT_DEFAULT_ALARM_POOL -#if PICO_TIME_DEFAULT_ALARM_POOL_DISABLED -#define PICO_RUNTIME_NO_INIT_DEFAULT_ALARM_POOL 1 -#endif -#endif - -// ------------------------------------------------------------------------------------------------ -// stack guard; these are a special case as they take a parameter; however the normal defines apply -// ------------------------------------------------------------------------------------------------ - -// PICO_CONFIG: PICO_RUNTIME_SKIP_INIT_PER_CORE_INSTALL_STACK_GUARD, Skip calling of `runtime_init_per_core_install_stack_guard` function during runtime init, type=bool, default=1 unless `PICO_USE_STACK_GUARDS` is 1, group=pico_runtime_init -// PICO_CONFIG: PICO_RUNTIME_NO_INIT_PER_CORE_INSTALL_STACK_GUARD, Do not include SDK implementation of `runtime_init_per_core_install_stack_guard` function, type=bool, default=1 unless `PICO_USE_STACK_GUARDS` is 1, group=pico_runtime_init - -#ifndef PICO_RUNTIME_INIT_PER_CORE_INSTALL_STACK_GUARD -#define PICO_RUNTIME_INIT_PER_CORE_INSTALL_STACK_GUARD "10050" -#endif - -#ifndef PICO_RUNTIME_SKIP_INIT_PER_CORE_INSTALL_STACK_GUARD -#if !PICO_USE_STACK_GUARDS -#define PICO_RUNTIME_SKIP_INIT_PER_CORE_INSTALL_STACK_GUARD 1 -#endif -#endif - -#ifndef PICO_RUNTIME_NO_INIT_PER_CORE_INSTALL_STACK_GUARD -#if !PICO_USE_STACK_GUARDS -#define PICO_RUNTIME_NO_INIT_PER_CORE_INSTALL_STACK_GUARD 1 -#endif -#endif - -#ifndef __ASSEMBLER__ -void runtime_init_per_core_install_stack_guard(void *stack_bottom); -// backwards compatibility -static __force_inline void runtime_install_stack_guard(void *stack_bottom) { - runtime_init_per_core_install_stack_guard(stack_bottom); -} - -#endif - -#ifdef __cplusplus -} -#endif - -#endif \ No newline at end of file diff --git a/lib/main/pico-sdk/rp2_common/pico_runtime_init/runtime_init.c b/lib/main/pico-sdk/rp2_common/pico_runtime_init/runtime_init.c deleted file mode 100644 index 2b69c8069f..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_runtime_init/runtime_init.c +++ /dev/null @@ -1,224 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "pico/runtime_init.h" - -// This file is sorted in the order of initialization - -// ------------------------------------- -// 00050 PICO_RUNTIME_INIT_BOOTROM_RESET -// ------------------------------------- -#if !PICO_RUNTIME_NO_INIT_BOOTROM_RESET -#include "pico/bootrom.h" -void __weak runtime_init_bootrom_reset(void) { - // todo can we tell if we came in thru the bootrom where this is not necessary (this is necessary for debugger) - rom_bootrom_state_reset_fn state_reset = rom_func_lookup(ROM_FUNC_BOOTROM_STATE_RESET); - state_reset(BOOTROM_STATE_RESET_GLOBAL_STATE); -} -#endif - -#if !PICO_RUNTIME_SKIP_INIT_BOOTROM_RESET -PICO_RUNTIME_INIT_FUNC_RUNTIME(runtime_init_bootrom_reset, PICO_RUNTIME_INIT_BOOTROM_RESET); -#endif - -// ---------------------------------------------- -// 00051 PICO_RUNTIME_INIT_PER_CORE_BOOTROM_RESET -// ---------------------------------------------- -#if !PICO_RUNTIME_NO_INIT_PER_CORE_BOOTROM_RESET -#include "pico/bootrom.h" -void __weak runtime_init_per_core_bootrom_reset(void) { - // todo can we tell if we came in thru the bootrom where this is not necessary (this is necessary for debugger) - rom_bootrom_state_reset_fn state_reset = rom_func_lookup(ROM_FUNC_BOOTROM_STATE_RESET); - state_reset(BOOTROM_STATE_RESET_CURRENT_CORE); -} -#endif - -#if !PICO_RUNTIME_SKIP_INIT_PER_CORE_BOOTROM_RESET -PICO_RUNTIME_INIT_FUNC_PER_CORE(runtime_init_per_core_bootrom_reset, PICO_RUNTIME_INIT_PER_CORE_BOOTROM_RESET); -#endif - -// ------------------------------------ -// 00060 PICO_RUNTIME_INIT_H3_IRQ_REGISTERS -// ------------------------------------ -#if !PICO_RUNTIME_SKIP_INIT_PER_CORE_H3_IRQ_REGISTERS -extern void runtime_init_per_core_h3_irq_registers(void); -PICO_RUNTIME_INIT_FUNC_PER_CORE(runtime_init_per_core_h3_irq_registers, PICO_RUNTIME_INIT_PER_CORE_H3_IRQ_REGISTERS); -#endif - -// ------------------------------------ -// 00100 PICO_RUNTIME_INIT_EARLY_RESETS -// ------------------------------------ -#if !PICO_RUNTIME_NO_INIT_EARLY_RESETS -#include "hardware/resets.h" -void __weak runtime_init_early_resets(void) { - static_assert(NUM_RESETS <= 32, ""); - // Reset all peripherals to put system into a known state, - // - except for QSPI pads and the XIP IO bank, as this is fatal if running from flash - // - and the PLLs, as this is fatal if clock muxing has not been reset on this boot - // - and USB, syscfg, as this disturbs USB-to-SWD on core 1 - reset_block_mask(~( - (1u << RESET_IO_QSPI) | - (1u << RESET_PADS_QSPI) | - (1u << RESET_PLL_USB) | - (1u << RESET_USBCTRL) | - (1u << RESET_SYSCFG) | - (1u << RESET_PLL_SYS) - )); - - // Remove reset from peripherals which are clocked only by clk_sys and - // clk_ref. Other peripherals stay in reset until we've configured clocks. - unreset_block_mask_wait_blocking(RESETS_RESET_BITS & ~( -#if !PICO_RP2040 - (1u << RESET_HSTX) | - #endif - (1u << RESET_ADC) | - #if PICO_RP2040 - (1u << RESET_RTC) | - #endif - (1u << RESET_SPI0) | - (1u << RESET_SPI1) | - (1u << RESET_UART0) | - (1u << RESET_UART1) | - (1u << RESET_USBCTRL) - )); - -} -#endif - -#if !PICO_RUNTIME_SKIP_INIT_EARLY_RESETS -PICO_RUNTIME_INIT_FUNC_HW(runtime_init_early_resets, PICO_RUNTIME_INIT_EARLY_RESETS); -#endif - -#if !PICO_RUNTIME_NO_INIT_USB_POWER_DOWN -#include "hardware/structs/usb.h" -void __weak runtime_init_usb_power_down(void) { - // Ensure USB PHY is in low-power state -- must be cleared before beginning USB operations. Only - // do this if USB appears to be in the reset state, to avoid breaking core1-as-debugger. - if (usb_hw->sie_ctrl == USB_SIE_CTRL_RESET) { - hw_set_bits(&usb_hw->sie_ctrl, USB_SIE_CTRL_TRANSCEIVER_PD_BITS); - } -} -#endif - -#if !PICO_RUNTIME_SKIP_INIT_USB_POWER_DOWN -PICO_RUNTIME_INIT_FUNC_HW(runtime_init_usb_power_down, PICO_RUNTIME_INIT_USB_POWER_DOWN); -#endif - -#if !PICO_RUNTIME_NO_INIT_PER_CORE_ENABLE_COPROCESSORS -#include "hardware/gpio.h" // PICO_USE_GPIO_COPROCESSOR is defined here -#include "hardware/structs/m33.h" -// ---------------------------------------------------- -// 00200 PICO_RUNTIME_INIT_PER_CORE_ENABLE_COPROCESSORS -// ---------------------------------------------------- -void __weak runtime_init_per_core_enable_coprocessors(void) { - // VFP copro (float) - uint32_t cpacr = M33_CPACR_CP10_BITS; -#if HAS_DOUBLE_COPROCESSOR - cpacr |= M33_CPACR_CP4_BITS; -#endif -#if PICO_USE_GPIO_COPROCESSOR - cpacr |= M33_CPACR_CP0_BITS; -#endif - arm_cpu_hw->cpacr |= cpacr; -#if HAS_DOUBLE_COPROCESSOR - asm volatile ("mrc p4,#0,r0,c0,c0,#1" : : : "r0"); // clear engaged flag via RCMP -#endif -} -#endif - -#if !PICO_RUNTIME_SKIP_INIT_PER_CORE_ENABLE_COPROCESSORS -PICO_RUNTIME_INIT_FUNC_PER_CORE(runtime_init_per_core_enable_coprocessors, PICO_RUNTIME_INIT_PER_CORE_ENABLE_COPROCESSORS); -#endif - -// ---------------------------------------------------- -// 00500 PICO_RUNTIME_INIT_CLOCKS -// ---------------------------------------------------- -#if !PICO_RUNTIME_SKIP_INIT_CLOCKS -PICO_RUNTIME_INIT_FUNC_HW(runtime_init_clocks, PICO_RUNTIME_INIT_CLOCKS); -#endif - -// ---------------------------------------------------- -// 00600 PICO_RUNTIME_INIT_POST_CLOCK_RESETS -// ---------------------------------------------------- -#if !PICO_RUNTIME_NO_INIT_POST_CLOCK_RESETS -#include "hardware/resets.h" -void __weak runtime_init_post_clock_resets(void) { - // Peripheral clocks should now all be running - static_assert(NUM_RESETS <= 32, ""); - unreset_block_mask_wait_blocking(RESETS_RESET_BITS); -} -#endif - -#if !PICO_RUNTIME_SKIP_POST_CLOCK_RESETS -PICO_RUNTIME_INIT_FUNC_HW(runtime_init_post_clock_resets, PICO_RUNTIME_INIT_POST_CLOCK_RESETS); -#endif - -// ---------------------------------------------------- -// 00700 PICO_RUNTIME_INIT_RP2040_GPIO_IE_DISABLE -// ---------------------------------------------------- - -#if !PICO_RUNTIME_NO_INIT_RP2040_GPIO_IE_DISABLE -#include "hardware/structs/pads_bank0.h" -void __weak runtime_init_rp2040_gpio_ie_disable(void) { -#if PICO_RP2040 && !PICO_IE_26_29_UNCHANGED_ON_RESET - // after resetting BANK0 we should disable IE on 26-29 as these may have mid-rail voltages when - // ADC is in use (on RP2040 B2 and later, and non-RP2040 chips, ADC pins should already have - // the correct reset state): - pads_bank0_hw_t *pads_bank0_hw_clear = (pads_bank0_hw_t *)hw_clear_alias_untyped(pads_bank0_hw); - pads_bank0_hw_clear->io[26] = pads_bank0_hw_clear->io[27] = - pads_bank0_hw_clear->io[28] = pads_bank0_hw_clear->io[29] = PADS_BANK0_GPIO0_IE_BITS; -#endif -} -#endif - -#if !PICO_RUNTIME_SKIP_INIT_RP2040_GPIO_IE_DISABLE -PICO_RUNTIME_INIT_FUNC_HW(runtime_init_rp2040_gpio_ie_disable, PICO_RUNTIME_INIT_RP2040_GPIO_IE_DISABLE); -#endif - -#if !PICO_RUNTIME_NO_INIT_SPIN_LOCKS_RESET -#include "hardware/sync.h" -void __weak runtime_init_spin_locks_reset(void) { - spin_locks_reset(); -} -#endif - -#if !PICO_RUNTIME_SKIP_INIT_SPIN_LOCKS_RESET -PICO_RUNTIME_INIT_FUNC_RUNTIME(runtime_init_spin_locks_reset, PICO_RUNTIME_INIT_SPIN_LOCKS_RESET); -#endif - -// On RISC-V the vector table is not relocatable since it contains PC-relative -// jump instructions, so rather than copying it into a RAM-resident array, we -// just link it in an initialised RAM section. Note there is no requirement on -// RISC-V to have an initial flash-resident vector table at a well-known -// location, unlike Cortex-M which can take an NMI on cycle 0. -#ifndef __riscv - -#if !PICO_RUNTIME_NO_INIT_INSTALL_RAM_VECTOR_TABLE -uint32_t __attribute__((section(".ram_vector_table"))) ram_vector_table[PICO_RAM_VECTOR_TABLE_SIZE]; - -#include "hardware/structs/scb.h" -void runtime_init_install_ram_vector_table(void) { - // Note on RISC-V the RAM vector table is initialised during crt0 -#if !(PICO_NO_RAM_VECTOR_TABLE || PICO_NO_FLASH) && !defined(__riscv) -#if !PICO_NO_STORED_VECTOR_TABLE - __builtin_memcpy(ram_vector_table, (uint32_t *) scb_hw->vtor, sizeof(ram_vector_table)); -#else - __builtin_memcpy(ram_vector_table, (uint32_t *) scb_hw->vtor, MIN(VTABLE_FIRST_IRQ, sizeof(ram_vector_table))); - for(uint i = VTABLE_FIRST_IRQ; ivtor = (uintptr_t) ram_vector_table; -#endif -} -#endif -#endif - -#if !PICO_RUNTIME_SKIP_INIT_INSTALL_RAM_VECTOR_TABLE -// todo this wants to be per core if we decide to support per core vector tables -PICO_RUNTIME_INIT_FUNC_RUNTIME(runtime_init_install_ram_vector_table, PICO_RUNTIME_INIT_INSTALL_RAM_VECTOR_TABLE); -#endif diff --git a/lib/main/pico-sdk/rp2_common/pico_runtime_init/runtime_init_clocks.c b/lib/main/pico-sdk/rp2_common/pico_runtime_init/runtime_init_clocks.c deleted file mode 100644 index 435a80166e..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_runtime_init/runtime_init_clocks.c +++ /dev/null @@ -1,148 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "pico/runtime_init.h" -#if !PICO_RUNTIME_NO_INIT_CLOCKS - -#include "hardware/clocks.h" -#include "hardware/pll.h" -#include "hardware/ticks.h" -#include "hardware/xosc.h" -#if PICO_RP2040 -#include "hardware/regs/rtc.h" -#endif - -#if PICO_RP2040 -// The RTC clock frequency is 48MHz divided by power of 2 (to ensure an integer -// division ratio will be used in the clocks block). A divisor of 1024 generates -// an RTC clock tick of 46875Hz. This frequency is relatively close to the -// customary 32 or 32.768kHz 'slow clock' crystals and provides good timing resolution. -#define RTC_CLOCK_FREQ_HZ (USB_CLK_HZ / 1024) -#endif - -static void start_all_ticks(void) { - uint32_t cycles = clock_get_hz(clk_ref) / MHZ; - // Note RP2040 has a single tick generator in the watchdog which serves - // watchdog, system timer and M0+ SysTick; The tick generator is clocked from clk_ref - // but is now adapted by the hardware_ticks library for compatibility with RP2350 - // npte: hardware_ticks library now provides an adapter for RP2040 - - for (int i = 0; i < (int)TICK_COUNT; ++i) { - tick_start((tick_gen_num_t)i, cycles); - } -} - -void __weak runtime_init_clocks(void) { - // Note: These need setting *before* the ticks are started - if (running_on_fpga()) { - for (uint i = 0; i < CLK_COUNT; i++) { - clock_set_reported_hz(i, 48 * MHZ); - } - // clk_ref is 12MHz in both RP2040 and RP2350 FPGA - clock_set_reported_hz(clk_ref, 12 * MHZ); - // RP2040 has an extra clock, the rtc -#if HAS_RP2040_RTC - clock_set_reported_hz(clk_rtc, RTC_CLOCK_FREQ_HZ); -#endif - } else { - // Disable resus that may be enabled from previous software - clocks_hw->resus.ctrl = 0; - - // Enable the xosc - xosc_init(); - - // Before we touch PLLs, switch sys and ref cleanly away from their aux sources. - hw_clear_bits(&clocks_hw->clk[clk_sys].ctrl, CLOCKS_CLK_SYS_CTRL_SRC_BITS); - while (clocks_hw->clk[clk_sys].selected != 0x1) - tight_loop_contents(); - hw_clear_bits(&clocks_hw->clk[clk_ref].ctrl, CLOCKS_CLK_REF_CTRL_SRC_BITS); - while (clocks_hw->clk[clk_ref].selected != 0x1) - tight_loop_contents(); - - /// \tag::pll_init[] - pll_init(pll_sys, PLL_SYS_REFDIV, PLL_SYS_VCO_FREQ_HZ, PLL_SYS_POSTDIV1, PLL_SYS_POSTDIV2); - pll_init(pll_usb, PLL_USB_REFDIV, PLL_USB_VCO_FREQ_HZ, PLL_USB_POSTDIV1, PLL_USB_POSTDIV2); - /// \end::pll_init[] - - // Configure clocks - - // RP2040 CLK_REF = XOSC (usually) 12MHz / 1 = 12MHz - // RP2350 CLK_REF = XOSC (XOSC_MHZ) / N (1,2,4) = 12MHz - - // clk_ref aux select is 0 because: - // - // - RP2040: no aux mux on clk_ref, so this field is don't-care. - // - // - RP2350: there is an aux mux, but we are selecting one of the - // non-aux inputs to the glitchless mux, so the aux select doesn't - // matter. The value of 0 here happens to be the sys PLL. - - clock_configure_undivided(clk_ref, - CLOCKS_CLK_REF_CTRL_SRC_VALUE_XOSC_CLKSRC, - 0, - XOSC_HZ); - - /// \tag::configure_clk_sys[] - // CLK SYS = PLL SYS (usually) 125MHz / 1 = 125MHz - clock_configure_undivided(clk_sys, - CLOCKS_CLK_SYS_CTRL_SRC_VALUE_CLKSRC_CLK_SYS_AUX, - CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS, - SYS_CLK_HZ); - /// \end::configure_clk_sys[] - - // CLK USB = PLL USB 48MHz / 1 = 48MHz - clock_configure_undivided(clk_usb, - 0, // No GLMUX - CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB, - USB_CLK_HZ); - - // CLK ADC = PLL USB 48MHZ / 1 = 48MHz - clock_configure_undivided(clk_adc, - 0, // No GLMUX - CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB, - USB_CLK_HZ); - -#if HAS_RP2040_RTC - // CLK RTC = PLL USB 48MHz / 1024 = 46875Hz -#if (USB_CLK_HZ % RTC_CLOCK_FREQ_HZ == 0) - // this doesn't pull in 64 bit arithmetic - clock_configure_int_divider(clk_rtc, - 0, // No GLMUX - CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB, - USB_CLK_HZ, - USB_CLK_HZ / RTC_CLOCK_FREQ_HZ); - -#else - clock_configure(clk_rtc, - 0, // No GLMUX - CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB, - USB_CLK_HZ, - RTC_CLOCK_FREQ_HZ); - -#endif -#endif - - // CLK PERI = clk_sys. Used as reference clock for UART and SPI serial. - clock_configure_undivided(clk_peri, - 0, - CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLK_SYS, - SYS_CLK_HZ); - -#if HAS_HSTX - // CLK_HSTX = clk_sys. Transmit bit clock for the HSTX peripheral. - clock_configure_undivided(clk_hstx, - 0, - CLOCKS_CLK_HSTX_CTRL_AUXSRC_VALUE_CLK_SYS, - SYS_CLK_HZ); -#endif - } - - // Finally, all clocks are configured so start the ticks - // The ticks use clk_ref so now that is configured we can start them - start_all_ticks(); -} - -#endif \ No newline at end of file diff --git a/lib/main/pico-sdk/rp2_common/pico_runtime_init/runtime_init_stack_guard.c b/lib/main/pico-sdk/rp2_common/pico_runtime_init/runtime_init_stack_guard.c deleted file mode 100644 index 27480f2cee..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_runtime_init/runtime_init_stack_guard.c +++ /dev/null @@ -1,77 +0,0 @@ -#include "pico/runtime.h" - -#if !PICO_RUNTIME_NO_INIT_PER_CORE_INSTALL_STACK_GUARD -#if PICO_RP2040 -#include "hardware/structs/mpu.h" -#elif defined(__riscv) -#include "hardware/riscv.h" -#endif -// this is called for each thread since they have their own MPU -void runtime_init_per_core_install_stack_guard(void *stack_bottom) { - // this is called b4 runtime_init is complete, so beware printf or assert - - uintptr_t addr = (uintptr_t) stack_bottom; - // the minimum we can protect is 32 bytes on a 32 byte boundary, so round up which will - // just shorten the valid stack range a tad - addr = (addr + 31u) & ~31u; - -#if PICO_RP2040 - // Armv6-M MPU - // make sure no one is using the MPU yet - if (mpu_hw->ctrl) { - // Note that it would be tempting to change this to a panic, but it happens so early, printing is not a good idea - __breakpoint(); - } - // mask is 1 bit per 32 bytes of the 256 byte range... clear the bit for the segment we want - uint32_t subregion_select = 0xffu ^ (1u << ((addr >> 5u) & 7u)); - mpu_hw->ctrl = 5; // enable mpu with background default map - mpu_hw->rbar = (addr & (uint)~0xff) | M0PLUS_MPU_RBAR_VALID_BITS | 0; - mpu_hw->rasr = 1 // enable region - | (0x7 << 1) // size 2^(7 + 1) = 256 - | (subregion_select << 8) - | 0x10000000; // XN = disable instruction fetch; no other bits means no permissions - -#elif defined(__riscv) - #if !PICO_RP2350 -#error "Check PMP configuration for new platform" -#endif - // RISC-V PMP, RP2350 configuration of Hazard3: 8 non-hardwired regions, - // NAPOT only, 32-byte granule, with nonstandard PMPCFGM0 register to - // apply regions to M-mode without locking them. - // Make sure no one is using the PMP yet - bool dirty_pmp = - riscv_read_csr(pmpcfg0) != 0 || - riscv_read_csr(pmpcfg1) != 0 || - riscv_read_csr(RVCSR_PMPCFGM0_OFFSET) != 0; - - if (dirty_pmp) { - __breakpoint(); - } - - // Note pmpaddr is in units of 4 bytes, so right-shift 2. - riscv_write_csr(pmpaddr0, (addr | 0x0fu) >> 2); - // Make this region inaccessible in both M-mode and U-mode (but don't lock it) - riscv_write_csr(RVCSR_PMPCFGM0_OFFSET, 0x1u); - riscv_write_csr(pmpcfg0, RVCSR_PMPCFG0_R0_A_VALUE_NAPOT << RVCSR_PMPCFG0_R0_A_LSB); - -#else -// // Armv8-M MPU -// // make sure no one is using the MPU yet -// if (mpu_hw->ctrl) { -// __breakpoint(); -// } -// mpu_hw->rnr = 0; -// // Read-only, privileged-only, nonexecutable. (Good enough because stack -// // is usually written first, on a stack push) -// mpu_hw->rbar = addr | (2u << M33_MPU_RBAR_AP_LSB) | (M33_MPU_RBAR_XN_BITS); -// mpu_hw->rlar = addr | M33_MPU_RLAR_EN_BITS; -// // Enable MPU (and leave default attributes applied even for privileged software) -// mpu_hw->ctrl = M33_MPU_CTRL_PRIVDEFENA_BITS | M33_MPU_CTRL_ENABLE_BITS; - pico_default_asm_volatile( - "msr msplim, %0" - : - : "r" (stack_bottom)); -#endif -} - -#endif \ No newline at end of file diff --git a/lib/main/pico-sdk/rp2_common/pico_sha256/include/pico/sha256.h b/lib/main/pico-sdk/rp2_common/pico_sha256/include/pico/sha256.h deleted file mode 100644 index 80aa5af379..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_sha256/include/pico/sha256.h +++ /dev/null @@ -1,150 +0,0 @@ -/* - * Copyright (c) 2024 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _PICO_SHA256_H -#define _PICO_SHA256_H - -#include "pico/time.h" -#include "hardware/dma.h" -#include "hardware/sha256.h" - -/** \file pico/sha256.h - * \defgroup pico_sha256 pico_sha256 - * - * \brief SHA-256 Hardware Accelerated implementation - * - * RP2350 is equipped with a hardware accelerated implementation of the SHA-256 hash algorithm. - * This should be much quicker than performing a SHA-256 checksum in software. - * - * \code - * pico_sha256_state_t state; - * if (pico_sha256_try_start(&state, SHA256_BIG_ENDIAN, true) == PICO_OK) { - * sha256_result_t result; - * pico_sha256_update(&state, some_data, sizeof(some_data)); - * pico_sha256_update(&state, some_more_data, sizeof(some_more_data)); - * pico_sha256_finish(&state, &result); - * for (int i = 0; i < SHA256_RESULT_BYTES; i++) { - * printf("%02x", result.bytes[i]); - * } - * } - * \endcode - * - * \subsection sha256_example Example - * \addtogroup pico_sha256 - * - * \include hello_sha256.c - */ - -#ifdef __cplusplus -extern "C" { -#endif - -/*! \brief SHA-256 state used by the API - * \ingroup pico_sha256 - */ -typedef struct pico_sha256_state { - enum sha256_endianness endianness; - int8_t channel; - bool locked; - uint8_t cache_used; - union { - uint32_t word; - uint8_t bytes[4]; - } cache; - dma_channel_config config; - size_t total_data_size; -} pico_sha256_state_t; - -/*! \brief Start a SHA-256 calculation returning immediately with an error if the SHA-256 hardware is not available - * \ingroup pico_sha256 - * - * Initialises the hardware and state ready to start a new SHA-256 calculation. - * Only one instance can be started at any time. - * - * @param state A pointer to a pico_sha256_state_t instance - * @param endianness SHA256_BIG_ENDIAN or SHA256_LITTLE_ENDIAN for data in and data out - * @param use_dma Set to true to use DMA internally to copy data to hardware. This is quicker at the expense of hardware DMA resources. - * @return Returns PICO_OK if the hardware was available for use and the sha256 calculation could be started, otherwise an error is returned - */ -int pico_sha256_try_start(pico_sha256_state_t *state, enum sha256_endianness endianness, bool use_dma); - -/*! \brief Start a SHA-256 calculation waiting for a defined period for the SHA-256 hardware to be available - * \ingroup pico_sha256 - * - * Initialises the hardware and state ready to start a new SHA-256 calculation. - * Only one instance can be started at any time. - * - * @param state A pointer to a pico_sha256_state_t instance - * @param endianness SHA256_BIG_ENDIAN or SHA256_LITTLE_ENDIAN for data in and data out - * @param use_dma Set to true to use DMA internally to copy data to hardware. This is quicker at the expense of hardware DMA resources. - * @param until How long to wait for the SHA hardware to be available - * @return Returns PICO_OK if the hardware was available for use and the sha256 calculation could be started in time, otherwise an error is returned - */ -int pico_sha256_start_blocking_until(pico_sha256_state_t *state, enum sha256_endianness endianness, bool use_dma, absolute_time_t until); - -/*! \brief Start a SHA-256 calculation, blocking forever waiting until the SHA-256 hardware is available - * \ingroup pico_sha256 - * - * Initialises the hardware and state ready to start a new SHA-256 calculation. - * Only one instance can be started at any time. - * - * @param state A pointer to a pico_sha256_state_t instance - * @param endianness SHA256_BIG_ENDIAN or SHA256_LITTLE_ENDIAN for data in and data out - * @param use_dma Set to true to use DMA internally to copy data to hardware. This is quicker at the expense of hardware DMA resources. - * @return Returns PICO_OK if the hardware was available for use and the sha256 calculation could be started, otherwise an error is returned - */ -static inline int pico_sha256_start_blocking(pico_sha256_state_t *state, enum sha256_endianness endianness, bool use_dma) { - return pico_sha256_start_blocking_until(state, endianness, use_dma, at_the_end_of_time); -} - -/*! \brief Add byte data to be SHA-256 calculation - * \ingroup pico_sha256 - * - * Add byte data to be SHA-256 calculation - * You may call this as many times as required to add all the data needed. - * You must have called pico_sha256_try_start (or equivalent) already. - * - * @param state A pointer to a pico_sha256_state_t instance - * @param data Pointer to the data to be added to the calculation - * @param data_size_bytes Amount of data to add - * - * @note This function may return before the copy has completed in which case the data passed to the function must remain valid and - * unchanged until a further call to pico_sha256_update or pico_sha256_finish. If this is not done, corrupt data may be used for the - * SHA-256 calculation giving an unexpected result. - */ -void pico_sha256_update(pico_sha256_state_t *state, const uint8_t *data, size_t data_size_bytes); - -/*! \brief Add byte data to be SHA-256 calculation - * \ingroup pico_sha256 - * - * Add byte data to be SHA-256 calculation - * You may call this as many times as required to add all the data needed. - * You must have called pico_sha256_try_start already. - * - * @param state A pointer to a pico_sha256_state_t instance - * @param data Pointer to the data to be added to the calculation - * @param data_size_bytes Amount of data to add - * - * @note This function will only return when the data passed in is no longer required, so it can be freed or changed on return. - */ -void pico_sha256_update_blocking(pico_sha256_state_t *state, const uint8_t *data, size_t data_size_bytes); - -/*! \brief Finish the SHA-256 calculation and return the result - * \ingroup pico_sha256 - * - * Ends the SHA-256 calculation freeing the hardware for use by another caller. - * You must have called pico_sha256_try_start already. - * - * @param state A pointer to a pico_sha256_state_t instance - * @param out The SHA-256 checksum - */ -void pico_sha256_finish(pico_sha256_state_t *state, sha256_result_t *out); - -#ifdef __cplusplus -} -#endif - -#endif \ No newline at end of file diff --git a/lib/main/pico-sdk/rp2_common/pico_sha256/sha256.c b/lib/main/pico-sdk/rp2_common/pico_sha256/sha256.c deleted file mode 100644 index e0cc739741..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_sha256/sha256.c +++ /dev/null @@ -1,185 +0,0 @@ -/* - * Copyright (c) 2024 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include -#include - -#include "hardware/sha256.h" -#include "pico/bootrom/lock.h" -#include "pico/sha256.h" -#include "pico/time.h" - -// We add one 0x80 byte, then 8 bytes for the size -#define SHA256_PADDING_DATA_BYTES 9 -#define SHA256_BLOCK_SIZE_BYTES 64 - -bool __weak pico_sha256_lock(pico_sha256_state_t *state) { - if (!bootrom_try_acquire_lock(BOOTROM_LOCK_SHA_256)) - return false; - state->locked = true; - return true; -} - -void __weak pico_sha256_unlock(pico_sha256_state_t *state) { - assert(state->locked); - bootrom_release_lock(BOOTROM_LOCK_SHA_256); - state->locked = false; -} - -int pico_sha256_try_start(pico_sha256_state_t *state, enum sha256_endianness endianness, bool use_dma) { - memset(state, 0, sizeof(*state)); - if (!pico_sha256_lock(state)) return PICO_ERROR_RESOURCE_IN_USE; - state->endianness = endianness; - if (use_dma) { - state->channel = (int8_t)dma_claim_unused_channel(false); - if (state->channel < 0) { - pico_sha256_unlock(state); - return PICO_ERROR_INSUFFICIENT_RESOURCES; - } - state->config = dma_channel_get_default_config(state->channel); - channel_config_set_transfer_data_size(&state->config, DMA_SIZE_8); - channel_config_set_read_increment(&state->config, true); - channel_config_set_write_increment(&state->config, false); - channel_config_set_dreq(&state->config, DREQ_SHA256); - sha256_set_dma_size(1); - } else { - state->channel = -1; - } - sha256_err_not_ready_clear(); - sha256_set_bswap(endianness == SHA256_BIG_ENDIAN); - sha256_start(); - state->total_data_size = 0; - return PICO_OK; -} - -int pico_sha256_start_blocking_until(pico_sha256_state_t *state, enum sha256_endianness endianness, bool use_dma, absolute_time_t until) { - int rc; - do { - rc = pico_sha256_try_start(state, endianness, use_dma); - if (rc != PICO_ERROR_RESOURCE_IN_USE) break; - if (time_reached(until)) { - rc = PICO_ERROR_TIMEOUT; - break; - } - } while (true); - return rc; -} - -static void write_to_hardware(pico_sha256_state_t *state, const uint8_t *data, size_t data_size_bytes) { - if (state->channel >= 0) { - dma_channel_wait_for_finish_blocking(state->channel); - assert(!sha256_err_not_ready()); - sha256_wait_ready_blocking(); - dma_channel_configure( - state->channel, - &state->config, - sha256_get_write_addr(), - data, - data_size_bytes, - true - ); - } else { - if (!state->cache_used && !(((uintptr_t)data)&3u)) { - GCC_Like_Pragma("GCC diagnostic ignored \"-Wcast-align\"") - const uint32_t *data32 = (const uint32_t *)data; - // aligned writes - while (data_size_bytes >= 4) { - // write a whole word - sha256_wait_ready_blocking(); - sha256_put_word(*data32++); - data_size_bytes -= 4; - } - data = (const uint8_t *)data32; - } - while (data_size_bytes--) { - state->cache.bytes[state->cache_used++] = *data++; - if (state->cache_used == 4) { - state->cache_used = 0; - sha256_wait_ready_blocking(); - sha256_put_word(state->cache.word); - } - } - } -} - -static void update_internal(pico_sha256_state_t *state, const uint8_t *data, size_t data_size_bytes) { - assert(state->locked); - // must finish off the last 64 byte block first or else sha256_err_not_ready will be true - size_t bytes_left = ((state->total_data_size + (SHA256_BLOCK_SIZE_BYTES - 1)) & ~(SHA256_BLOCK_SIZE_BYTES - 1)) - state->total_data_size; - if (bytes_left > data_size_bytes) bytes_left = data_size_bytes; - if (bytes_left > 0) { - write_to_hardware(state, data, bytes_left); - state->total_data_size += bytes_left; - data_size_bytes -= bytes_left; - data += bytes_left; - } - // Write the rest of the data - if (data_size_bytes > 0) { - write_to_hardware(state, data, data_size_bytes); - state->total_data_size += data_size_bytes; - } -} - -static void add_zero_bytes(pico_sha256_state_t *state, size_t data_size_bytes) { - uint32_t zero = 0; - // todo: can be done a bit more efficiently with dma? - assert(data_size_bytes < INT32_MAX); - while((int32_t)data_size_bytes > 0) { - update_internal(state, (uint8_t *)&zero, MIN(4, data_size_bytes)); - data_size_bytes -= 4; - } -} - -void pico_sha256_update(pico_sha256_state_t *state, const uint8_t *data, size_t data_size_bytes) { - update_internal(state, data, data_size_bytes); -} - -void pico_sha256_update_blocking(pico_sha256_state_t *state, const uint8_t *data, size_t data_size_bytes) { - update_internal(state, data, data_size_bytes); - if (state->channel >= 0) { - dma_channel_wait_for_finish_blocking(state->channel); - } -} - -// write the SHA-256 padding to hardware -static void write_padding(pico_sha256_state_t *state) { - // Has to be a multiple of 64 bytes - uint64_t size = (state->total_data_size + SHA256_PADDING_DATA_BYTES + (SHA256_BLOCK_SIZE_BYTES - 1)) & ~(SHA256_BLOCK_SIZE_BYTES - 1); - const size_t user_data_size = state->total_data_size; - const size_t padding_size_bytes = size - state->total_data_size; - - // append a single '1' bit - const uint8_t one_bit = 0x80; - update_internal(state, &one_bit, 1); - - // Zero unused padding - add_zero_bytes(state, padding_size_bytes - SHA256_PADDING_DATA_BYTES); - - // Add size in bits, big endian - size = __builtin_bswap64(user_data_size * 8); - update_internal(state, (uint8_t*)&size, sizeof(uint64_t)); // last write -} - -void pico_sha256_finish(pico_sha256_state_t *state, sha256_result_t *out) { - assert(state->locked); - // pass NULL to abandon the current hash in case of an error - if (out) { - write_padding(state); - if (state->channel >= 0) { - dma_channel_wait_for_finish_blocking(state->channel); - assert(!sha256_err_not_ready()); - } - sha256_wait_valid_blocking(); - sha256_get_result(out, state->endianness); - } - if (state->channel >= 0) { - dma_channel_cleanup(state->channel); - dma_channel_unclaim(state->channel); - state->channel = -1; - } - pico_sha256_unlock(state); -} diff --git a/lib/main/pico-sdk/rp2_common/pico_standard_binary_info/doc.h b/lib/main/pico-sdk/rp2_common/pico_standard_binary_info/doc.h deleted file mode 100644 index e24741ec16..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_standard_binary_info/doc.h +++ /dev/null @@ -1,19 +0,0 @@ -/** - * \defgroup pico_standard_binary_info pico_standard_binary_info - * \brief Includes default information about the binary that can be displayed by picotool - * - * Information is included only if `PICO_NO_BINARY_INFO` and `PICO_NO_PROGRAM_INFO` are both false. - * - * This library adds the following information to the binary: - * - * * The program name if defined (unless `PICO_NO_BINARY_SIZE=1`). The value is `PICO_PROGRAM_NAME` or `PICO_TARGET_NAME` if the former isn't defined - * * The value of PICO_BOARD (unless `PICO_NO_BI_PICO_BOARD=1`) - * * The SDK version (unless `PICO_NO_BI_SDK_VERSION=1`) - * * The program version string if defined (unless `PICO_NO_BI_PROGRAM_VERSION_STRING=1`). The value is `PICO_PROGRAM_VERSION_STRING`` - * * The program description if defined (unless `PICO_NO_BI_PROGRAM_DESCRIPTION=1`). The value is `PICO_PROGRAM_DESCRIPTION` - * * The program url if defined (unless `PICO_NO_BI_PROGRAM_URL=1`). The value is `PICO_PROGRAM_URL` - * * The boot stage 2 used if any (unless `PICO_NO_BI_BOOT_STAGE2_NAME=1`). The value is `PICO_BOOT_STAGE2_NAME` - * * The program build date (unless `PICO_NO_BI_PROGRAM_BUILD_DATE=1). The value defaults to the C preprocessor value `__DATE__`, but can be overridden with `PICO_PROGRAM_BUILD_DATE`. Note you should do a clean build if you want to be sure this value is up to date. - * * The program build type (unless `PICO_NO_BI_BUILD_TYPE=1`). The value is `PICO_CMAKE_BUILD_TYPE` which comes from the CMake build - e.g. Release, Debug, RelMinSize - * * The binary size (unless `PICO_NO_BI_BINARY_SIZE=1`) - */ diff --git a/lib/main/pico-sdk/rp2_common/pico_standard_binary_info/standard_binary_info.c b/lib/main/pico-sdk/rp2_common/pico_standard_binary_info/standard_binary_info.c deleted file mode 100644 index c950f8db15..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_standard_binary_info/standard_binary_info.c +++ /dev/null @@ -1,98 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#if !PICO_NO_BINARY_INFO && !PICO_NO_PROGRAM_INFO -#include "pico/binary_info.h" - -#if LIB_BOOT_STAGE2_HEADERS && !PICO_NO_FLASH -#include "boot_stage2/config.h" -#endif - -// Note we put at most 4 pieces of binary info in the binary_info_header section because that's how much spare space we -// have before the vector table in a RAM binary (we use the attribute for the most common ones since the choice is static)... -// if there is a link failure because of .reset section overflow then move more out. -#if PICO_NO_FLASH -#define section_hack_attr __attribute__((section(".binary_info_header"))) -#else -#define section_hack_attr -#endif - -#if !PICO_NO_FLASH -#ifndef PICO_NO_BI_BINARY_SIZE -extern char __flash_binary_end; -bi_decl_with_attr(bi_binary_end((intptr_t)&__flash_binary_end), section_hack_attr) -#endif -#endif - -#if !PICO_NO_BI_PROGRAM_BUILD_DATE -#ifndef PICO_PROGRAM_BUILD_DATE -#define PICO_PROGRAM_BUILD_DATE __DATE__ -#endif -bi_decl_with_attr(bi_program_build_date_string(PICO_PROGRAM_BUILD_DATE), section_hack_attr); -#endif - -#if !PICO_NO_BI_PROGRAM_NAME -#if !defined(PICO_PROGRAM_NAME) && defined(PICO_TARGET_NAME) -#define PICO_PROGRAM_NAME PICO_TARGET_NAME -#endif -#ifdef PICO_PROGRAM_NAME -bi_decl_with_attr(bi_program_name(PICO_PROGRAM_NAME), section_hack_attr) -#endif -#endif - -#if !PICO_NO_BI_PICO_BOARD -#ifdef PICO_BOARD -bi_decl(bi_string(BINARY_INFO_TAG_RASPBERRY_PI, BINARY_INFO_ID_RP_PICO_BOARD, PICO_BOARD)) -#endif -#endif - -#if !PICO_NO_BI_SDK_VERSION -#ifdef PICO_SDK_VERSION_STRING -bi_decl_with_attr(bi_string(BINARY_INFO_TAG_RASPBERRY_PI, BINARY_INFO_ID_RP_SDK_VERSION, PICO_SDK_VERSION_STRING), section_hack_attr) -#endif -#endif - -#if !PICO_NO_BI_PROGRAM_VERSION_STRING -#ifdef PICO_PROGRAM_VERSION_STRING -bi_decl(bi_program_version_string(PICO_PROGRAM_VERSION_STRING)) -#endif -#endif - -#if !PICO_NO_BI_PROGRAM_DESCRIPTION -#ifdef PICO_PROGRAM_DESCRIPTION -bi_decl(bi_program_description(PICO_PROGRAM_DESCRIPTION)) -#endif -#endif - -#if !PICO_NO_BI_PROGRAM_URL -#ifdef PICO_PROGRAM_URL -bi_decl(bi_program_url(PICO_PROGRAM_URL)) -#endif -#endif - -#if !PICO_NO_BI_BOOT_STAGE2_NAME -#ifdef PICO_BOOT_STAGE2_NAME -bi_decl(bi_string(BINARY_INFO_TAG_RASPBERRY_PI, BINARY_INFO_ID_RP_BOOT2_NAME, PICO_BOOT_STAGE2_NAME)) -#endif -#endif - -#if !PICO_NO_BI_BUILD_TYPE -#ifdef PICO_CMAKE_BUILD_TYPE -bi_decl(bi_program_build_attribute(PICO_CMAKE_BUILD_TYPE)) -#else -#ifndef NDEBUG -bi_decl(bi_program_build_attribute("Debug")) -#else -bi_decl(bi_program_build_attribute("Release")) -#endif -#endif - -#if PICO_DEOPTIMIZED_DEBUG -bi_decl(bi_program_build_attribute("All optimization disabled")) -#endif -#endif - -#endif diff --git a/lib/main/pico-sdk/rp2_common/pico_standard_link/doc.h b/lib/main/pico-sdk/rp2_common/pico_standard_link/doc.h deleted file mode 100644 index b413fb3820..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_standard_link/doc.h +++ /dev/null @@ -1,10 +0,0 @@ -/** - * \defgroup pico_standard_link pico_standard_link - * \brief Setup for link options for a standard SDK executable - * - * This includes - * - C runtime initialization - * - Linker scripts for 'default', 'no_flash', 'blocked_ram' and 'copy_to_ram' binaries - * - 'Binary Information' support - * - Linker option control - */ diff --git a/lib/main/pico-sdk/rp2_common/pico_standard_link/pico_flash_region.template.ld b/lib/main/pico-sdk/rp2_common/pico_standard_link/pico_flash_region.template.ld deleted file mode 100644 index 123bd56c2f..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_standard_link/pico_flash_region.template.ld +++ /dev/null @@ -1 +0,0 @@ -FLASH(rx) : ORIGIN = 0x10000000, LENGTH = ${PICO_FLASH_SIZE_BYTES_STRING} \ No newline at end of file diff --git a/lib/main/pico-sdk/rp2_common/pico_stdio/include/pico/stdio.h b/lib/main/pico-sdk/rp2_common/pico_stdio/include/pico/stdio.h deleted file mode 100644 index cba3b27c4f..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_stdio/include/pico/stdio.h +++ /dev/null @@ -1,228 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _PICO_STDIO_H -#define _PICO_STDIO_H - -/** \file stdio.h -* \defgroup pico_stdio pico_stdio -* \brief Customized stdio support allowing for input and output from UART, USB, semi-hosting etc -* -* Note the API for adding additional input output devices is not yet considered stable -*/ - -#include "pico.h" - -// PICO_CONFIG: PICO_STDOUT_MUTEX, Enable/disable mutex around stdout, type=bool, default=1, group=pico_stdio -#ifndef PICO_STDOUT_MUTEX -#define PICO_STDOUT_MUTEX 1 -#endif - -// PICO_CONFIG: PICO_STDIO_ENABLE_CRLF_SUPPORT, Enable/disable CR/LF output conversion support, type=bool, default=1, group=pico_stdio -#ifndef PICO_STDIO_ENABLE_CRLF_SUPPORT -#define PICO_STDIO_ENABLE_CRLF_SUPPORT 1 -#endif - -// PICO_CONFIG: PICO_STDIO_DEFAULT_CRLF, Default for CR/LF conversion enabled on all stdio outputs, type=bool, default=1, depends=PICO_STDIO_ENABLE_CRLF_SUPPORT, group=pico_stdio -#ifndef PICO_STDIO_DEFAULT_CRLF -#define PICO_STDIO_DEFAULT_CRLF 1 -#endif - -// PICO_CONFIG: PICO_STDIO_STACK_BUFFER_SIZE, Define printf buffer size (on stack)... this is just a working buffer not a max output size, min=0, max=512, default=128, group=pico_stdio -#ifndef PICO_STDIO_STACK_BUFFER_SIZE -#define PICO_STDIO_STACK_BUFFER_SIZE 128 -#endif - -// PICO_CONFIG: PICO_STDIO_DEADLOCK_TIMEOUT_MS, Time after which to assume stdio_usb is deadlocked by use in IRQ and give up, type=int, default=1000, group=pico_stdio -#ifndef PICO_STDIO_DEADLOCK_TIMEOUT_MS -#define PICO_STDIO_DEADLOCK_TIMEOUT_MS 1000 -#endif - -// PICO_CONFIG: PICO_STDIO_SHORT_CIRCUIT_CLIB_FUNCS, Directly replace common stdio functions such as putchar from the C-library to avoid pulling in lots of c library code for simple output, type=bool, default=1, advanced=true, group=pico_stdio -#ifndef PICO_STDIO_SHORT_CIRCUIT_CLIB_FUNCS -#define PICO_STDIO_SHORT_CIRCUIT_CLIB_FUNCS 1 -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -typedef struct stdio_driver stdio_driver_t; - -/*! \brief Initialize all of the present standard stdio types that are linked into the binary. - * \ingroup pico_stdio - * - * Call this method once you have set up your clocks to enable the stdio support for UART, USB, - * semihosting, and RTT based on the presence of the respective libraries in the binary. - * - * When stdio_usb is configured, this method can be optionally made to block, waiting for a connection - * via the variables specified in \ref stdio_usb_init (i.e. \ref PICO_STDIO_USB_CONNECT_WAIT_TIMEOUT_MS) - * - * \return true if at least one output was successfully initialized, false otherwise. - * \see stdio_uart, stdio_usb, stdio_semihosting, stdio_rtt - */ -bool stdio_init_all(void); - -/*! \brief Deinitialize all of the present standard stdio types that are linked into the binary. - * \ingroup pico_stdio - * - * This method currently only supports stdio_uart and stdio_semihosting - * - * \return true if all outputs was successfully deinitialized, false otherwise. - * \see stdio_uart, stdio_usb, stdio_semihosting, stdio_rtt - */ -bool stdio_deinit_all(void); - -/*! \brief Flushes any buffered output. - * \ingroup pico_stdio - */ -void stdio_flush(void); - -/*! \brief Return a character from stdin if there is one available within a timeout - * \ingroup pico_stdio - * - * \param timeout_us the timeout in microseconds, or 0 to not wait for a character if none available. - * \return the character from 0-255 or PICO_ERROR_TIMEOUT if timeout occurs - */ -int stdio_getchar_timeout_us(uint32_t timeout_us); - -/*! \brief Alias for \ref stdio_getchar_timeout_us for backwards compatibility - * \ingroup pico_stdio - */ -static inline int getchar_timeout_us(uint32_t timeout_us) { - return stdio_getchar_timeout_us(timeout_us); -} - -/*! \brief Adds or removes a driver from the list of active drivers used for input/output - * \ingroup pico_stdio - * - * \note this method should always be called on an initialized driver and is not re-entrant - * \param driver the driver - * \param enabled true to add, false to remove - */ -void stdio_set_driver_enabled(stdio_driver_t *driver, bool enabled); - -/*! \brief Control limiting of output to a single driver - * \ingroup pico_stdio - * - * \note this method should always be called on an initialized driver - * - * \param driver if non-null then output only that driver will be used for input/output (assuming it is in the list of enabled drivers). - * if NULL then all enabled drivers will be used - */ -void stdio_filter_driver(stdio_driver_t *driver); - -/*! \brief control conversion of line feeds to carriage return on transmissions - * \ingroup pico_stdio - * - * \note this method should always be called on an initialized driver - * - * \param driver the driver - * \param translate If true, convert line feeds to carriage return on transmissions - */ -void stdio_set_translate_crlf(stdio_driver_t *driver, bool translate); - -/*! \brief putchar variant that skips any CR/LF conversion if enabled - * \ingroup pico_stdio - */ -int stdio_putchar_raw(int c); - -/*! \brief Alias for \ref stdio_putchar_raw for backwards compatibility - * \ingroup pico_stdio - */ -static inline int putchar_raw(int c) { - return stdio_putchar_raw(c); -} - -/*! \brief puts variant that skips any CR/LF conversion if enabled - * \ingroup pico_stdio - */ -int stdio_puts_raw(const char *s); - -/*! \brief Alias for \ref stdio_puts_raw for backwards compatibility - * \ingroup pico_stdio - */ -static inline int puts_raw(const char *s) { - return stdio_puts_raw(s); -} - -/*! \brief get notified when there are input characters available - * \ingroup pico_stdio - * - * \param fn Callback function to be called when characters are available. Pass NULL to cancel any existing callback - * \param param Pointer to pass to the callback - */ -void stdio_set_chars_available_callback(void (*fn)(void*), void *param); - -/*! \brief Waits until a timeout to reard at least one character into a buffer - * \ingroup pico_stdio - * - * This method returns as soon as input is available, but more characters may - * be returned up to the end of the buffer. - * - * \param buf the buffer to read into - * \param len the length of the buffer - * \return the number of characters read or PICO_ERROR_TIMEOUT - * \param until the time after which to return PICO_ERROR_TIMEOUT if no characters are available - */ -int stdio_get_until(char *buf, int len, absolute_time_t until); - -/*! \brief Prints a buffer to stdout with optional newline and carriage return insertion - * \ingroup pico_stdio - * - * This method returns as soon as input is available, but more characters may - * be returned up to the end of the buffer. - * - * \param s the characters to print - * \param len the length of s - * \param newline true if a newline should be added after the string - * \param cr_translation true if line feed to carriage return translation should be performed - * \return the number of characters written - */ -int stdio_put_string(const char *s, int len, bool newline, bool cr_translation); - -/*! \brief stdio_getchar Alias for \ref getchar that definitely does not go thru the implementation - * in the standard C library even when \ref PICO_STDIO_SHORT_CIRCUIT_CLIB_FUNCS == 0 - * - * \ingroup pico_stdio - */ -int stdio_getchar(void); - -/*! \brief stdio_getchar Alias for \ref putchar that definitely does not go thru the implementation - * in the standard C library even when \ref PICO_STDIO_SHORT_CIRCUIT_CLIB_FUNCS == 0 - * - * \ingroup pico_stdio - */ -int stdio_putchar(int); - -/*! \brief stdio_getchar Alias for \ref puts that definitely does not go thru the implementation - * in the standard C library even when \ref PICO_STDIO_SHORT_CIRCUIT_CLIB_FUNCS == 0 - * - * \ingroup pico_stdio - */ -int stdio_puts(const char *s); - -/*! \brief stdio_getchar Alias for \ref vprintf that definitely does not go thru the implementation - * in the standard C library even when \ref PICO_STDIO_SHORT_CIRCUIT_CLIB_FUNCS == 0 - * - * \ingroup pico_stdio - */ -int stdio_vprintf(const char *format, va_list va); - -/*! \brief stdio_getchar Alias for \ref printf that definitely does not go thru the implementation - * in the standard C library even when \ref PICO_STDIO_SHORT_CIRCUIT_CLIB_FUNCS == 0 - * - * \ingroup pico_stdio - */ -int __printflike(1, 0) stdio_printf(const char* format, ...); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/lib/main/pico-sdk/rp2_common/pico_stdio/include/pico/stdio/driver.h b/lib/main/pico-sdk/rp2_common/pico_stdio/include/pico/stdio/driver.h deleted file mode 100644 index 9ed1ebd41b..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_stdio/include/pico/stdio/driver.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _PICO_STDIO_DRIVER_H -#define _PICO_STDIO_DRIVER_H - -#include "pico/stdio.h" - -struct stdio_driver { - void (*out_chars)(const char *buf, int len); - void (*out_flush)(void); - int (*in_chars)(char *buf, int len); - void (*set_chars_available_callback)(void (*fn)(void*), void *param); - stdio_driver_t *next; -#if PICO_STDIO_ENABLE_CRLF_SUPPORT - bool last_ended_with_cr; - bool crlf_enabled; -#endif -}; - -#endif diff --git a/lib/main/pico-sdk/rp2_common/pico_stdio/stdio.c b/lib/main/pico-sdk/rp2_common/pico_stdio/stdio.c deleted file mode 100644 index d2ce14556c..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_stdio/stdio.c +++ /dev/null @@ -1,391 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include -#include - -#include "pico.h" -#if LIB_PICO_PRINTF_PICO -#include "pico/printf.h" -#endif -#include "pico/stdio.h" -#include "pico/stdio/driver.h" -#include "pico/time.h" -#if PICO_STDOUT_MUTEX -#include "pico/mutex.h" -#endif - -#if LIB_PICO_STDIO_UART -#include "pico/stdio_uart.h" -#endif - -#if LIB_PICO_STDIO_USB -#include "pico/stdio_usb.h" -#endif - -#if LIB_PICO_STDIO_SEMIHOSTING -#include "pico/stdio_semihosting.h" -#endif - -#if LIB_PICO_STDIO_RTT -#include "pico/stdio_rtt.h" -#endif - -static stdio_driver_t *drivers; -static stdio_driver_t *filter; - -#if PICO_STDOUT_MUTEX -auto_init_mutex(print_mutex); - -bool stdout_serialize_begin(void) { - return mutex_try_enter_block_until(&print_mutex, make_timeout_time_ms(PICO_STDIO_DEADLOCK_TIMEOUT_MS)); -} - -void stdout_serialize_end(void) { - mutex_exit(&print_mutex); -} - -#else -static bool stdout_serialize_begin(void) { - return true; -} -static void stdout_serialize_end(void) { -} -#endif -static void stdio_out_chars_no_crlf(stdio_driver_t *driver, const char *s, int len) { - driver->out_chars(s, len); -} - -static void stdio_out_chars_crlf(stdio_driver_t *driver, const char *s, int len) { -#if PICO_STDIO_ENABLE_CRLF_SUPPORT - if (!driver->crlf_enabled) { - driver->out_chars(s, len); - return; - } - int first_of_chunk = 0; - static const char crlf_str[] = {'\r', '\n'}; - for (int i = 0; i < len; i++) { - bool prev_char_was_cr = i > 0 ? s[i - 1] == '\r' : driver->last_ended_with_cr; - if (s[i] == '\n' && !prev_char_was_cr) { - if (i > first_of_chunk) { - driver->out_chars(&s[first_of_chunk], i - first_of_chunk); - } - driver->out_chars(crlf_str, 2); - first_of_chunk = i + 1; - } - } - if (first_of_chunk < len) { - driver->out_chars(&s[first_of_chunk], len - first_of_chunk); - } - if (len > 0) { - driver->last_ended_with_cr = s[len - 1] == '\r'; - } -#else - driver->out_chars(s, len); -#endif -} - -int stdio_put_string(const char *s, int len, bool newline, bool cr_translation) { - bool serialized = stdout_serialize_begin(); - if (!serialized) { -#if PICO_STDIO_IGNORE_NESTED_STDOUT - return 0; -#endif - } - if (len == -1) len = (int)strlen(s); - void (*out_func)(stdio_driver_t *, const char *, int) = cr_translation ? stdio_out_chars_crlf : stdio_out_chars_no_crlf; - for (stdio_driver_t *driver = drivers; driver; driver = driver->next) { - if (!driver->out_chars) continue; - if (filter && filter != driver) continue; - out_func(driver, s, len); - if (newline) { - const char c = '\n'; - out_func(driver, &c, 1); - } - } - if (serialized) { - stdout_serialize_end(); - } - return len; -} - -int stdio_get_until(char *buf, int len, absolute_time_t until) { - do { - // todo round robin might be nice on each call, but then again hopefully - // no source will starve the others - for (stdio_driver_t *driver = drivers; driver; driver = driver->next) { - if (filter && filter != driver) continue; - if (driver->in_chars) { - int read = driver->in_chars(buf, len); - if (read > 0) { - return read; - } - } - } - if (time_reached(until)) { - return PICO_ERROR_TIMEOUT; - } - // we sleep here in case the in_chars methods acquire mutexes or disable IRQs and - // potentially starve out what they are waiting on (have seen this with USB) - busy_wait_us(1); - } while (true); -} - -int stdio_putchar_raw(int c) { - char cc = (char)c; - stdio_put_string(&cc, 1, false, false); - return c; -} - -int stdio_puts_raw(const char *s) { - int len = (int)strlen(s); - stdio_put_string(s, len, true, false); - stdio_flush(); - return len; -} - -void stdio_set_driver_enabled(stdio_driver_t *driver, bool enable) { - stdio_driver_t **prev = &drivers; - while (*prev) { - if (*prev == driver) { - if (!enable) { - *prev = driver->next; - driver->next = NULL; - } - return; - } - prev = &(*prev)->next; - } - if (enable) { - *prev = driver; - } -} - -void stdio_flush(void) { - for (stdio_driver_t *d = drivers; d; d = d->next) { - if (d->out_flush) d->out_flush(); - } -} - -#if LIB_PICO_PRINTF_PICO -typedef struct stdio_stack_buffer { - int used; - char buf[PICO_STDIO_STACK_BUFFER_SIZE]; -} stdio_stack_buffer_t; - -static void stdio_stack_buffer_flush(stdio_stack_buffer_t *buffer) { - if (buffer->used) { - for (stdio_driver_t *d = drivers; d; d = d->next) { - if (!d->out_chars) continue; - if (filter && filter != d) continue; - stdio_out_chars_crlf(d, buffer->buf, buffer->used); - } - buffer->used = 0; - } -} - -static void stdio_buffered_printer(char c, void *arg) { - stdio_stack_buffer_t *buffer = (stdio_stack_buffer_t *)arg; - if (buffer->used == PICO_STDIO_STACK_BUFFER_SIZE) { - stdio_stack_buffer_flush(buffer); - } - buffer->buf[buffer->used++] = c; -} -#endif - -bool stdio_init_all(void) { - // todo add explicit custom, or registered although you can call stdio_enable_driver explicitly anyway - // These are well known ones - - bool rc = false; -#if LIB_PICO_STDIO_UART - stdio_uart_init(); - rc = true; -#endif - -#if LIB_PICO_STDIO_SEMIHOSTING - stdio_semihosting_init(); - rc = true; -#endif - -#if LIB_PICO_STDIO_RTT - stdio_rtt_init(); - rc = true; -#endif - -#if LIB_PICO_STDIO_USB - rc |= stdio_usb_init(); -#endif - return rc; -} - -bool stdio_deinit_all(void) { - // todo add explicit custom, or registered although you can call stdio_enable_driver explicitly anyway - // These are well known ones - - // First flush, to make sure everything is printed - stdio_flush(); - - bool rc = false; -#if LIB_PICO_STDIO_UART - stdio_uart_deinit(); - rc = true; -#endif - -#if LIB_PICO_STDIO_SEMIHOSTING - stdio_semihosting_deinit(); - rc = true; -#endif - -#if LIB_PICO_STDIO_RTT - stdio_rtt_deinit(); - rc = true; -#endif - -#if LIB_PICO_STDIO_USB - rc = stdio_usb_deinit(); -#endif - return rc; -} - -int stdio_getchar_timeout_us(uint32_t timeout_us) { - char buf[1]; - int rc = stdio_get_until(buf, sizeof(buf), make_timeout_time_us(timeout_us)); - if (rc < 0) return rc; - assert(rc); - return (uint8_t)buf[0]; -} - -void stdio_filter_driver(stdio_driver_t *driver) { - filter = driver; -} - -void stdio_set_translate_crlf(stdio_driver_t *driver, bool enabled) { -#if PICO_STDIO_ENABLE_CRLF_SUPPORT - if (enabled && !driver->crlf_enabled) { - driver->last_ended_with_cr = false; - } - driver->crlf_enabled = enabled; -#else - // Suppress -Wunused-parameter - (void)driver; - (void)enabled; - - panic_unsupported(); -#endif -} - -void stdio_set_chars_available_callback(void (*fn)(void*), void *param) { - for (stdio_driver_t *s = drivers; s; s = s->next) { - if (s->set_chars_available_callback) s->set_chars_available_callback(fn, param); - } -} - -#if PICO_STDIO_SHORT_CIRCUIT_CLIB_FUNCS -#define PRIMARY_STDIO_FUNC(x) WRAPPER_FUNC(x) -#else -#define PRIMARY_STDIO_FUNC(x) stdio_ ## x -#endif - -int PRIMARY_STDIO_FUNC(getchar)(void) { - char buf[1]; - int len = stdio_get_until(buf, 1, at_the_end_of_time); - if (len < 0) return len; - assert(len == 1); - return (uint8_t)buf[0]; -} - -int PRIMARY_STDIO_FUNC(putchar)(int c) { - char cc = (char)c; - stdio_put_string(&cc, 1, false, true); - return c; -} - -int PRIMARY_STDIO_FUNC(puts)(const char *s) { - int len = (int)strlen(s); - stdio_put_string(s, len, true, true); - stdio_flush(); - return len; -} - -int REAL_FUNC(vprintf)(const char *format, va_list va); - -int PRIMARY_STDIO_FUNC(vprintf)(const char *format, va_list va) { - bool serialzed = stdout_serialize_begin(); - if (!serialzed) { -#if PICO_STDIO_IGNORE_NESTED_STDOUT - return 0; -#endif - } - int ret; -#if LIB_PICO_PRINTF_PICO - struct stdio_stack_buffer buffer; - buffer.used = 0; - ret = vfctprintf(stdio_buffered_printer, &buffer, format, va); - stdio_stack_buffer_flush(&buffer); - stdio_flush(); -#elif LIB_PICO_PRINTF_NONE - ((void)format); - ((void)va); - extern void printf_none_assert(void); - printf_none_assert(); - ret = 0; -#else - ret = REAL_FUNC(vprintf)(format, va); -#endif - if (serialzed) { - stdout_serialize_end(); - } - return ret; -} - -int __printflike(1, 0) PRIMARY_STDIO_FUNC(printf)(const char* format, ...) -{ - va_list va; - va_start(va, format); - int ret = vprintf(format, va); - va_end(va); - return ret; -} - -#if PICO_STDIO_SHORT_CIRCUIT_CLIB_FUNCS -// define the stdio_ versions to be the same as our wrappers -int stdio_getchar(void) __attribute__((alias(__XSTRING(WRAPPER_FUNC(getchar))))); -int stdio_putchar(int) __attribute__((alias(__XSTRING(WRAPPER_FUNC(putchar))))); -int stdio_puts(const char *s) __attribute__((alias(__XSTRING(WRAPPER_FUNC(puts))))); -int stdio_vprintf(const char *format, va_list va) __attribute__((alias(__XSTRING(WRAPPER_FUNC(vprintf))))); -int __printflike(1, 0) stdio_printf(const char* format, ...) __attribute__((alias(__XSTRING(WRAPPER_FUNC(printf))))); -#else -// todo there is no easy way to avoid the wrapper functions since they are in the CMake, so lets just forward for now - -int REAL_FUNC(getchar)(void); -int REAL_FUNC(putchar)(int); -int REAL_FUNC(puts)(const char *s); -int __printflike(1, 0) REAL_FUNC(printf)(const char* format, ...); - -int WRAPPER_FUNC(getchar)(void) { - return REAL_FUNC(getchar)(); -} -int WRAPPER_FUNC(putchar)(int c) { - return REAL_FUNC(putchar)(c); -} -int WRAPPER_FUNC(puts)(const char *s) { - return REAL_FUNC(puts)(s); -} -int WRAPPER_FUNC(vprintf)(const char *format, va_list va) { - return REAL_FUNC(vprintf)(format, va); -} -int __printflike(1, 0) WRAPPER_FUNC(printf)(const char* format, ...) { - va_list va; - va_start(va, format); - int ret = REAL_FUNC(vprintf)(format, va); - va_end(va); - return ret; -} -#endif - - diff --git a/lib/main/pico-sdk/rp2_common/pico_stdio_rtt/SEGGER/Config/SEGGER_RTT_Conf.h b/lib/main/pico-sdk/rp2_common/pico_stdio_rtt/SEGGER/Config/SEGGER_RTT_Conf.h deleted file mode 100644 index 4cdb6f419f..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_stdio_rtt/SEGGER/Config/SEGGER_RTT_Conf.h +++ /dev/null @@ -1,429 +0,0 @@ -/********************************************************************* -* SEGGER Microcontroller GmbH * -* The Embedded Experts * -********************************************************************** -* * -* (c) 1995 - 2021 SEGGER Microcontroller GmbH * -* * -* www.segger.com Support: support@segger.com * -* * -********************************************************************** -* * -* SEGGER RTT * Real Time Transfer for embedded targets * -* * -********************************************************************** -* * -* All rights reserved. * -* * -* SEGGER strongly recommends to not make any changes * -* to or modify the source code of this software in order to stay * -* compatible with the RTT protocol and J-Link. * -* * -* Redistribution and use in source and binary forms, with or * -* without modification, are permitted provided that the following * -* condition is met: * -* * -* o Redistributions of source code must retain the above copyright * -* notice, this condition and the following disclaimer. * -* * -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * -* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * -* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * -* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * -* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR * -* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT * -* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * -* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * -* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * -* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * -* DAMAGE. * -* * -********************************************************************** -* * -* RTT version: 7.88c * -* * -********************************************************************** - ----------------------------END-OF-HEADER------------------------------ -File : SEGGER_RTT_Conf.h -Purpose : Implementation of SEGGER real-time transfer (RTT) which - allows real-time communication on targets which support - debugger memory accesses while the CPU is running. -Revision: $Rev: 24316 $ - -*/ - -#ifndef SEGGER_RTT_CONF_H -#define SEGGER_RTT_CONF_H - -#ifdef __IAR_SYSTEMS_ICC__ - #include -#endif - -/********************************************************************* -* -* Defines, configurable -* -********************************************************************** -*/ - -// -// Take in and set to correct values for Cortex-A systems with CPU cache -// -//#define SEGGER_RTT_CPU_CACHE_LINE_SIZE (32) // Largest cache line size (in bytes) in the current system -//#define SEGGER_RTT_UNCACHED_OFF (0xFB000000) // Address alias where RTT CB and buffers can be accessed uncached -// -// Most common case: -// Up-channel 0: RTT -// Up-channel 1: SystemView -// -#ifndef SEGGER_RTT_MAX_NUM_UP_BUFFERS - #define SEGGER_RTT_MAX_NUM_UP_BUFFERS (3) // Max. number of up-buffers (T->H) available on this target (Default: 3) -#endif -// -// Most common case: -// Down-channel 0: RTT -// Down-channel 1: SystemView -// -#ifndef SEGGER_RTT_MAX_NUM_DOWN_BUFFERS - #define SEGGER_RTT_MAX_NUM_DOWN_BUFFERS (3) // Max. number of down-buffers (H->T) available on this target (Default: 3) -#endif - -#ifndef BUFFER_SIZE_UP - #define BUFFER_SIZE_UP (1024) // Size of the buffer for terminal output of target, up to host (Default: 1k) -#endif - -#ifndef BUFFER_SIZE_DOWN - #define BUFFER_SIZE_DOWN (16) // Size of the buffer for terminal input to target from host (Usually keyboard input) (Default: 16) -#endif - -#ifndef SEGGER_RTT_PRINTF_BUFFER_SIZE - #define SEGGER_RTT_PRINTF_BUFFER_SIZE (64u) // Size of buffer for RTT printf to bulk-send chars via RTT (Default: 64) -#endif - -#ifndef SEGGER_RTT_MODE_DEFAULT - #define SEGGER_RTT_MODE_DEFAULT SEGGER_RTT_MODE_NO_BLOCK_SKIP // Mode for pre-initialized terminal channel (buffer 0) -#endif - -/********************************************************************* -* -* RTT memcpy configuration -* -* memcpy() is good for large amounts of data, -* but the overhead is big for small amounts, which are usually stored via RTT. -* With SEGGER_RTT_MEMCPY_USE_BYTELOOP a simple byte loop can be used instead. -* -* SEGGER_RTT_MEMCPY() can be used to replace standard memcpy() in RTT functions. -* This is may be required with memory access restrictions, -* such as on Cortex-A devices with MMU. -*/ -#ifndef SEGGER_RTT_MEMCPY_USE_BYTELOOP - #define SEGGER_RTT_MEMCPY_USE_BYTELOOP 0 // 0: Use memcpy/SEGGER_RTT_MEMCPY, 1: Use a simple byte-loop -#endif -// -// Example definition of SEGGER_RTT_MEMCPY to external memcpy with GCC toolchains and Cortex-A targets -// -//#if ((defined __SES_ARM) || (defined __CROSSWORKS_ARM) || (defined __GNUC__)) && (defined (__ARM_ARCH_7A__)) -// #define SEGGER_RTT_MEMCPY(pDest, pSrc, NumBytes) SEGGER_memcpy((pDest), (pSrc), (NumBytes)) -//#endif - -// -// Target is not allowed to perform other RTT operations while string still has not been stored completely. -// Otherwise we would probably end up with a mixed string in the buffer. -// If using RTT from within interrupts, multiple tasks or multi processors, define the SEGGER_RTT_LOCK() and SEGGER_RTT_UNLOCK() function here. -// -// SEGGER_RTT_MAX_INTERRUPT_PRIORITY can be used in the sample lock routines on Cortex-M3/4. -// Make sure to mask all interrupts which can send RTT data, i.e. generate SystemView events, or cause task switches. -// When high-priority interrupts must not be masked while sending RTT data, SEGGER_RTT_MAX_INTERRUPT_PRIORITY needs to be adjusted accordingly. -// (Higher priority = lower priority number) -// Default value for embOS: 128u -// Default configuration in FreeRTOS: configMAX_SYSCALL_INTERRUPT_PRIORITY: ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) ) -// In case of doubt mask all interrupts: 1 << (8 - BASEPRI_PRIO_BITS) i.e. 1 << 5 when 3 bits are implemented in NVIC -// or define SEGGER_RTT_LOCK() to completely disable interrupts. -// -#ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY - #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20) // Interrupt priority to lock on SEGGER_RTT_LOCK on Cortex-M3/4 (Default: 0x20) -#endif - -/********************************************************************* -* -* RTT lock configuration for SEGGER Embedded Studio, -* Rowley CrossStudio and GCC -*/ -#if ((defined(__SES_ARM) || defined(__SES_RISCV) || defined(__CROSSWORKS_ARM) || defined(__GNUC__) || defined(__clang__)) && !defined (__CC_ARM) && !defined(WIN32)) - #if (defined(__ARM_ARCH_6M__) || defined(__ARM_ARCH_8M_BASE__)) - #define SEGGER_RTT_LOCK() { \ - unsigned int _SEGGER_RTT__LockState; \ - __asm volatile ("mrs %0, primask \n\t" \ - "movs r1, #1 \n\t" \ - "msr primask, r1 \n\t" \ - : "=r" (_SEGGER_RTT__LockState) \ - : \ - : "r1", "cc" \ - ); - - #define SEGGER_RTT_UNLOCK() __asm volatile ("msr primask, %0 \n\t" \ - : \ - : "r" (_SEGGER_RTT__LockState) \ - : \ - ); \ - } - #elif (defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) || defined(__ARM_ARCH_8M_MAIN__)) - #ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY - #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20) - #endif - #define SEGGER_RTT_LOCK() { \ - unsigned int _SEGGER_RTT__LockState; \ - __asm volatile ("mrs %0, basepri \n\t" \ - "mov r1, %1 \n\t" \ - "msr basepri, r1 \n\t" \ - : "=r" (_SEGGER_RTT__LockState) \ - : "i"(SEGGER_RTT_MAX_INTERRUPT_PRIORITY) \ - : "r1", "cc" \ - ); - - #define SEGGER_RTT_UNLOCK() __asm volatile ("msr basepri, %0 \n\t" \ - : \ - : "r" (_SEGGER_RTT__LockState) \ - : \ - ); \ - } - - #elif (defined(__ARM_ARCH_7A__) || defined(__ARM_ARCH_7R__)) - #define SEGGER_RTT_LOCK() { \ - unsigned int _SEGGER_RTT__LockState; \ - __asm volatile ("mrs r1, CPSR \n\t" \ - "mov %0, r1 \n\t" \ - "orr r1, r1, #0xC0 \n\t" \ - "msr CPSR_c, r1 \n\t" \ - : "=r" (_SEGGER_RTT__LockState) \ - : \ - : "r1", "cc" \ - ); - - #define SEGGER_RTT_UNLOCK() __asm volatile ("mov r0, %0 \n\t" \ - "mrs r1, CPSR \n\t" \ - "bic r1, r1, #0xC0 \n\t" \ - "and r0, r0, #0xC0 \n\t" \ - "orr r1, r1, r0 \n\t" \ - "msr CPSR_c, r1 \n\t" \ - : \ - : "r" (_SEGGER_RTT__LockState) \ - : "r0", "r1", "cc" \ - ); \ - } - #elif defined(__riscv) || defined(__riscv_xlen) - #define SEGGER_RTT_LOCK() { \ - unsigned int _SEGGER_RTT__LockState; \ - __asm volatile ("csrr %0, mstatus \n\t" \ - "csrci mstatus, 8 \n\t" \ - "andi %0, %0, 8 \n\t" \ - : "=r" (_SEGGER_RTT__LockState) \ - : \ - : \ - ); - - #define SEGGER_RTT_UNLOCK() __asm volatile ("csrr a1, mstatus \n\t" \ - "or %0, %0, a1 \n\t" \ - "csrs mstatus, %0 \n\t" \ - : \ - : "r" (_SEGGER_RTT__LockState) \ - : "a1" \ - ); \ - } - #else - #define SEGGER_RTT_LOCK() - #define SEGGER_RTT_UNLOCK() - #endif -#endif - -/********************************************************************* -* -* RTT lock configuration for IAR EWARM -*/ -#ifdef __ICCARM__ - #if (defined (__ARM6M__) && (__CORE__ == __ARM6M__)) || \ - (defined (__ARM8M_BASELINE__) && (__CORE__ == __ARM8M_BASELINE__)) - #define SEGGER_RTT_LOCK() { \ - unsigned int _SEGGER_RTT__LockState; \ - _SEGGER_RTT__LockState = __get_PRIMASK(); \ - __set_PRIMASK(1); - - #define SEGGER_RTT_UNLOCK() __set_PRIMASK(_SEGGER_RTT__LockState); \ - } - #elif (defined (__ARM7EM__) && (__CORE__ == __ARM7EM__)) || \ - (defined (__ARM7M__) && (__CORE__ == __ARM7M__)) || \ - (defined (__ARM8M_MAINLINE__) && (__CORE__ == __ARM8M_MAINLINE__)) || \ - (defined (__ARM8M_MAINLINE__) && (__CORE__ == __ARM8M_MAINLINE__)) - #ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY - #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20) - #endif - #define SEGGER_RTT_LOCK() { \ - unsigned int _SEGGER_RTT__LockState; \ - _SEGGER_RTT__LockState = __get_BASEPRI(); \ - __set_BASEPRI(SEGGER_RTT_MAX_INTERRUPT_PRIORITY); - - #define SEGGER_RTT_UNLOCK() __set_BASEPRI(_SEGGER_RTT__LockState); \ - } - #elif (defined (__ARM7A__) && (__CORE__ == __ARM7A__)) || \ - (defined (__ARM7R__) && (__CORE__ == __ARM7R__)) - #define SEGGER_RTT_LOCK() { \ - unsigned int _SEGGER_RTT__LockState; \ - __asm volatile ("mrs r1, CPSR \n\t" \ - "mov %0, r1 \n\t" \ - "orr r1, r1, #0xC0 \n\t" \ - "msr CPSR_c, r1 \n\t" \ - : "=r" (_SEGGER_RTT__LockState) \ - : \ - : "r1", "cc" \ - ); - - #define SEGGER_RTT_UNLOCK() __asm volatile ("mov r0, %0 \n\t" \ - "mrs r1, CPSR \n\t" \ - "bic r1, r1, #0xC0 \n\t" \ - "and r0, r0, #0xC0 \n\t" \ - "orr r1, r1, r0 \n\t" \ - "msr CPSR_c, r1 \n\t" \ - : \ - : "r" (_SEGGER_RTT__LockState) \ - : "r0", "r1", "cc" \ - ); \ - } - #endif -#endif - -/********************************************************************* -* -* RTT lock configuration for IAR RX -*/ -#ifdef __ICCRX__ - #define SEGGER_RTT_LOCK() { \ - unsigned long _SEGGER_RTT__LockState; \ - _SEGGER_RTT__LockState = __get_interrupt_state(); \ - __disable_interrupt(); - - #define SEGGER_RTT_UNLOCK() __set_interrupt_state(_SEGGER_RTT__LockState); \ - } -#endif - -/********************************************************************* -* -* RTT lock configuration for IAR RL78 -*/ -#ifdef __ICCRL78__ - #define SEGGER_RTT_LOCK() { \ - __istate_t _SEGGER_RTT__LockState; \ - _SEGGER_RTT__LockState = __get_interrupt_state(); \ - __disable_interrupt(); - - #define SEGGER_RTT_UNLOCK() __set_interrupt_state(_SEGGER_RTT__LockState); \ - } -#endif - -/********************************************************************* -* -* RTT lock configuration for KEIL ARM -*/ -#ifdef __CC_ARM - #if (defined __TARGET_ARCH_6S_M) - #define SEGGER_RTT_LOCK() { \ - unsigned int _SEGGER_RTT__LockState; \ - register unsigned char _SEGGER_RTT__PRIMASK __asm( "primask"); \ - _SEGGER_RTT__LockState = _SEGGER_RTT__PRIMASK; \ - _SEGGER_RTT__PRIMASK = 1u; \ - __schedule_barrier(); - - #define SEGGER_RTT_UNLOCK() _SEGGER_RTT__PRIMASK = _SEGGER_RTT__LockState; \ - __schedule_barrier(); \ - } - #elif (defined(__TARGET_ARCH_7_M) || defined(__TARGET_ARCH_7E_M)) - #ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY - #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20) - #endif - #define SEGGER_RTT_LOCK() { \ - unsigned int _SEGGER_RTT__LockState; \ - register unsigned char BASEPRI __asm( "basepri"); \ - _SEGGER_RTT__LockState = BASEPRI; \ - BASEPRI = SEGGER_RTT_MAX_INTERRUPT_PRIORITY; \ - __schedule_barrier(); - - #define SEGGER_RTT_UNLOCK() BASEPRI = _SEGGER_RTT__LockState; \ - __schedule_barrier(); \ - } - #endif -#endif - -/********************************************************************* -* -* RTT lock configuration for TI ARM -*/ -#ifdef __TI_ARM__ - #if defined (__TI_ARM_V6M0__) - #define SEGGER_RTT_LOCK() { \ - unsigned int _SEGGER_RTT__LockState; \ - _SEGGER_RTT__LockState = __get_PRIMASK(); \ - __set_PRIMASK(1); - - #define SEGGER_RTT_UNLOCK() __set_PRIMASK(_SEGGER_RTT__LockState); \ - } - #elif (defined (__TI_ARM_V7M3__) || defined (__TI_ARM_V7M4__)) - #ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY - #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20) - #endif - #define SEGGER_RTT_LOCK() { \ - unsigned int _SEGGER_RTT__LockState; \ - _SEGGER_RTT__LockState = _set_interrupt_priority(SEGGER_RTT_MAX_INTERRUPT_PRIORITY); - - #define SEGGER_RTT_UNLOCK() _set_interrupt_priority(_SEGGER_RTT__LockState); \ - } - #endif -#endif - -/********************************************************************* -* -* RTT lock configuration for CCRX -*/ -#ifdef __RX - #include - #define SEGGER_RTT_LOCK() { \ - unsigned long _SEGGER_RTT__LockState; \ - _SEGGER_RTT__LockState = get_psw() & 0x010000; \ - clrpsw_i(); - - #define SEGGER_RTT_UNLOCK() set_psw(get_psw() | _SEGGER_RTT__LockState); \ - } -#endif - -/********************************************************************* -* -* RTT lock configuration for embOS Simulation on Windows -* (Can also be used for generic RTT locking with embOS) -*/ -#if defined(WIN32) || defined(SEGGER_RTT_LOCK_EMBOS) - -void OS_SIM_EnterCriticalSection(void); -void OS_SIM_LeaveCriticalSection(void); - -#define SEGGER_RTT_LOCK() { \ - OS_SIM_EnterCriticalSection(); - -#define SEGGER_RTT_UNLOCK() OS_SIM_LeaveCriticalSection(); \ - } -#endif - -/********************************************************************* -* -* RTT lock configuration fallback -*/ -#ifndef SEGGER_RTT_LOCK - #define SEGGER_RTT_LOCK() // Lock RTT (nestable) (i.e. disable interrupts) -#endif - -#ifndef SEGGER_RTT_UNLOCK - #define SEGGER_RTT_UNLOCK() // Unlock RTT (nestable) (i.e. enable previous interrupt lock state) -#endif - -#endif -/*************************** End of file ****************************/ diff --git a/lib/main/pico-sdk/rp2_common/pico_stdio_rtt/SEGGER/RTT/SEGGER_RTT.c b/lib/main/pico-sdk/rp2_common/pico_stdio_rtt/SEGGER/RTT/SEGGER_RTT.c deleted file mode 100644 index f355404178..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_stdio_rtt/SEGGER/RTT/SEGGER_RTT.c +++ /dev/null @@ -1,2105 +0,0 @@ -/********************************************************************* -* SEGGER Microcontroller GmbH * -* The Embedded Experts * -********************************************************************** -* * -* (c) 1995 - 2021 SEGGER Microcontroller GmbH * -* * -* www.segger.com Support: support@segger.com * -* * -********************************************************************** -* * -* SEGGER RTT * Real Time Transfer for embedded targets * -* * -********************************************************************** -* * -* All rights reserved. * -* * -* SEGGER strongly recommends to not make any changes * -* to or modify the source code of this software in order to stay * -* compatible with the RTT protocol and J-Link. * -* * -* Redistribution and use in source and binary forms, with or * -* without modification, are permitted provided that the following * -* condition is met: * -* * -* o Redistributions of source code must retain the above copyright * -* notice, this condition and the following disclaimer. * -* * -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * -* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * -* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * -* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * -* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR * -* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT * -* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * -* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * -* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * -* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * -* DAMAGE. * -* * -********************************************************************** -* * -* RTT version: 7.88c * -* * -********************************************************************** - ----------------------------END-OF-HEADER------------------------------ -File : SEGGER_RTT.c -Purpose : Implementation of SEGGER real-time transfer (RTT) which - allows real-time communication on targets which support - debugger memory accesses while the CPU is running. -Revision: $Rev: 29668 $ - -Additional information: - Type "int" is assumed to be 32-bits in size - H->T Host to target communication - T->H Target to host communication - - RTT channel 0 is always present and reserved for Terminal usage. - Name is fixed to "Terminal" - - Effective buffer size: SizeOfBuffer - 1 - - WrOff == RdOff: Buffer is empty - WrOff == (RdOff - 1): Buffer is full - WrOff > RdOff: Free space includes wrap-around - WrOff < RdOff: Used space includes wrap-around - (WrOff == (SizeOfBuffer - 1)) && (RdOff == 0): - Buffer full and wrap-around after next byte - - ----------------------------------------------------------------------- -*/ - -#include "SEGGER_RTT.h" - -#include // for memcpy - -/********************************************************************* -* -* Configuration, default values -* -********************************************************************** -*/ - -#if SEGGER_RTT_CPU_CACHE_LINE_SIZE - #ifdef SEGGER_RTT_CB_ALIGN - #error "Custom SEGGER_RTT_CB_ALIGN() is not supported for SEGGER_RTT_CPU_CACHE_LINE_SIZE != 0" - #endif - #ifdef SEGGER_RTT_BUFFER_ALIGN - #error "Custom SEGGER_RTT_BUFFER_ALIGN() is not supported for SEGGER_RTT_CPU_CACHE_LINE_SIZE != 0" - #endif - #ifdef SEGGER_RTT_PUT_CB_SECTION - #error "Custom SEGGER_RTT_PUT_CB_SECTION() is not supported for SEGGER_RTT_CPU_CACHE_LINE_SIZE != 0" - #endif - #ifdef SEGGER_RTT_PUT_BUFFER_SECTION - #error "Custom SEGGER_RTT_PUT_BUFFER_SECTION() is not supported for SEGGER_RTT_CPU_CACHE_LINE_SIZE != 0" - #endif - #ifdef SEGGER_RTT_BUFFER_ALIGNMENT - #error "Custom SEGGER_RTT_BUFFER_ALIGNMENT is not supported for SEGGER_RTT_CPU_CACHE_LINE_SIZE != 0" - #endif - #ifdef SEGGER_RTT_ALIGNMENT - #error "Custom SEGGER_RTT_ALIGNMENT is not supported for SEGGER_RTT_CPU_CACHE_LINE_SIZE != 0" - #endif -#endif - -#ifndef BUFFER_SIZE_UP - #define BUFFER_SIZE_UP 1024 // Size of the buffer for terminal output of target, up to host -#endif - -#ifndef BUFFER_SIZE_DOWN - #define BUFFER_SIZE_DOWN 16 // Size of the buffer for terminal input to target from host (Usually keyboard input) -#endif - -#ifndef SEGGER_RTT_MAX_NUM_UP_BUFFERS - #define SEGGER_RTT_MAX_NUM_UP_BUFFERS 2 // Number of up-buffers (T->H) available on this target -#endif - -#ifndef SEGGER_RTT_MAX_NUM_DOWN_BUFFERS - #define SEGGER_RTT_MAX_NUM_DOWN_BUFFERS 2 // Number of down-buffers (H->T) available on this target -#endif - -#ifndef SEGGER_RTT_BUFFER_SECTION - #if defined(SEGGER_RTT_SECTION) - #define SEGGER_RTT_BUFFER_SECTION SEGGER_RTT_SECTION - #endif -#endif - -#ifndef SEGGER_RTT_ALIGNMENT - #define SEGGER_RTT_ALIGNMENT SEGGER_RTT_CPU_CACHE_LINE_SIZE -#endif - -#ifndef SEGGER_RTT_BUFFER_ALIGNMENT - #define SEGGER_RTT_BUFFER_ALIGNMENT SEGGER_RTT_CPU_CACHE_LINE_SIZE -#endif - -#ifndef SEGGER_RTT_MODE_DEFAULT - #define SEGGER_RTT_MODE_DEFAULT SEGGER_RTT_MODE_NO_BLOCK_SKIP -#endif - -#ifndef SEGGER_RTT_LOCK - #define SEGGER_RTT_LOCK() -#endif - -#ifndef SEGGER_RTT_UNLOCK - #define SEGGER_RTT_UNLOCK() -#endif - -#ifndef STRLEN - #define STRLEN(a) strlen((a)) -#endif - -#ifndef STRCPY - #define STRCPY(pDest, pSrc) strcpy((pDest), (pSrc)) -#endif - -#ifndef SEGGER_RTT_MEMCPY_USE_BYTELOOP - #define SEGGER_RTT_MEMCPY_USE_BYTELOOP 0 -#endif - -#ifndef SEGGER_RTT_MEMCPY - #ifdef MEMCPY - #define SEGGER_RTT_MEMCPY(pDest, pSrc, NumBytes) MEMCPY((pDest), (pSrc), (NumBytes)) - #else - #define SEGGER_RTT_MEMCPY(pDest, pSrc, NumBytes) memcpy((pDest), (pSrc), (NumBytes)) - #endif -#endif - -#ifndef MIN - #define MIN(a, b) (((a) < (b)) ? (a) : (b)) -#endif - -#ifndef MAX - #define MAX(a, b) (((a) > (b)) ? (a) : (b)) -#endif -// -// For some environments, NULL may not be defined until certain headers are included -// -#ifndef NULL - #define NULL 0 -#endif - -/********************************************************************* -* -* Defines, fixed -* -********************************************************************** -*/ -#if (defined __ICCARM__) || (defined __ICCRX__) - #define RTT_PRAGMA(P) _Pragma(#P) -#endif - -#if SEGGER_RTT_ALIGNMENT || SEGGER_RTT_BUFFER_ALIGNMENT - #if ((defined __GNUC__) || (defined __clang__)) - #define SEGGER_RTT_ALIGN(Var, Alignment) Var __attribute__ ((aligned (Alignment))) - #elif (defined __ICCARM__) || (defined __ICCRX__) - #define PRAGMA(A) _Pragma(#A) -#define SEGGER_RTT_ALIGN(Var, Alignment) RTT_PRAGMA(data_alignment=Alignment) \ - Var - #elif (defined __CC_ARM) - #define SEGGER_RTT_ALIGN(Var, Alignment) Var __attribute__ ((aligned (Alignment))) - #else - #error "Alignment not supported for this compiler." - #endif -#else - #define SEGGER_RTT_ALIGN(Var, Alignment) Var -#endif - -#if defined(SEGGER_RTT_SECTION) || defined (SEGGER_RTT_BUFFER_SECTION) - #if ((defined __GNUC__) || (defined __clang__)) - #define SEGGER_RTT_PUT_SECTION(Var, Section) __attribute__ ((section (Section))) Var - #elif (defined __ICCARM__) || (defined __ICCRX__) -#define SEGGER_RTT_PUT_SECTION(Var, Section) RTT_PRAGMA(location=Section) \ - Var - #elif (defined __CC_ARM) - #define SEGGER_RTT_PUT_SECTION(Var, Section) __attribute__ ((section (Section), zero_init)) Var - #else - #error "Section placement not supported for this compiler." - #endif -#else - #define SEGGER_RTT_PUT_SECTION(Var, Section) Var -#endif - -#if SEGGER_RTT_ALIGNMENT - #define SEGGER_RTT_CB_ALIGN(Var) SEGGER_RTT_ALIGN(Var, SEGGER_RTT_ALIGNMENT) -#else - #define SEGGER_RTT_CB_ALIGN(Var) Var -#endif - -#if SEGGER_RTT_BUFFER_ALIGNMENT - #define SEGGER_RTT_BUFFER_ALIGN(Var) SEGGER_RTT_ALIGN(Var, SEGGER_RTT_BUFFER_ALIGNMENT) -#else - #define SEGGER_RTT_BUFFER_ALIGN(Var) Var -#endif - - -#if defined(SEGGER_RTT_SECTION) - #define SEGGER_RTT_PUT_CB_SECTION(Var) SEGGER_RTT_PUT_SECTION(Var, SEGGER_RTT_SECTION) -#else - #define SEGGER_RTT_PUT_CB_SECTION(Var) Var -#endif - -#if defined(SEGGER_RTT_BUFFER_SECTION) - #define SEGGER_RTT_PUT_BUFFER_SECTION(Var) SEGGER_RTT_PUT_SECTION(Var, SEGGER_RTT_BUFFER_SECTION) -#else - #define SEGGER_RTT_PUT_BUFFER_SECTION(Var) Var -#endif - -/********************************************************************* -* -* Static const data -* -********************************************************************** -*/ - -static const unsigned char _aTerminalId[16] = { '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'A', 'B', 'C', 'D', 'E', 'F' }; - -/********************************************************************* -* -* Static data -* -********************************************************************** -*/ - -// -// RTT Control Block and allocate buffers for channel 0 -// -#if SEGGER_RTT_CPU_CACHE_LINE_SIZE - #if ((defined __GNUC__) || (defined __clang__)) - SEGGER_RTT_CB _SEGGER_RTT __attribute__ ((aligned (SEGGER_RTT_CPU_CACHE_LINE_SIZE))); - static char _acUpBuffer [SEGGER_RTT__ROUND_UP_2_CACHE_LINE_SIZE(BUFFER_SIZE_UP)] __attribute__ ((aligned (SEGGER_RTT_CPU_CACHE_LINE_SIZE))); - static char _acDownBuffer[SEGGER_RTT__ROUND_UP_2_CACHE_LINE_SIZE(BUFFER_SIZE_DOWN)] __attribute__ ((aligned (SEGGER_RTT_CPU_CACHE_LINE_SIZE))); - #elif (defined __ICCARM__) - #pragma data_alignment=SEGGER_RTT_CPU_CACHE_LINE_SIZE - SEGGER_RTT_CB _SEGGER_RTT; - #pragma data_alignment=SEGGER_RTT_CPU_CACHE_LINE_SIZE - static char _acUpBuffer [SEGGER_RTT__ROUND_UP_2_CACHE_LINE_SIZE(BUFFER_SIZE_UP)]; - #pragma data_alignment=SEGGER_RTT_CPU_CACHE_LINE_SIZE - static char _acDownBuffer[SEGGER_RTT__ROUND_UP_2_CACHE_LINE_SIZE(BUFFER_SIZE_DOWN)]; - #else - #error "Don't know how to place _SEGGER_RTT, _acUpBuffer, _acDownBuffer cache-line aligned" - #endif -#else - SEGGER_RTT_PUT_CB_SECTION(SEGGER_RTT_CB_ALIGN(SEGGER_RTT_CB _SEGGER_RTT)); - SEGGER_RTT_PUT_BUFFER_SECTION(SEGGER_RTT_BUFFER_ALIGN(static char _acUpBuffer [BUFFER_SIZE_UP])); - SEGGER_RTT_PUT_BUFFER_SECTION(SEGGER_RTT_BUFFER_ALIGN(static char _acDownBuffer[BUFFER_SIZE_DOWN])); -#endif - -static unsigned char _ActiveTerminal; - -/********************************************************************* -* -* Static functions -* -********************************************************************** -*/ - -/********************************************************************* -* -* _DoInit() -* -* Function description -* Initializes the control block an buffers. -* -* Notes -* (1) May only be called via INIT() to avoid overriding settings. -* The only exception is SEGGER_RTT_Init(), to make an intentional override possible. -*/ - #define INIT() \ - do { \ - volatile SEGGER_RTT_CB* pRTTCBInit; \ - pRTTCBInit = (volatile SEGGER_RTT_CB*)((char*)&_SEGGER_RTT + SEGGER_RTT_UNCACHED_OFF); \ - if (pRTTCBInit->acID[0] != 'S') { \ - _DoInit(); \ - } \ - } while (0) - -static void _DoInit(void) { - volatile SEGGER_RTT_CB* p; // Volatile to make sure that compiler cannot change the order of accesses to the control block - static const char _aInitStr[] = "\0\0\0\0\0\0TTR REGGES"; // Init complete ID string to make sure that things also work if RTT is linked to a no-init memory area - unsigned i; - // - // Initialize control block - // - p = (volatile SEGGER_RTT_CB*)((char*)&_SEGGER_RTT + SEGGER_RTT_UNCACHED_OFF); // Access control block uncached so that nothing in the cache ever becomes dirty and all changes are visible in HW directly - memset((SEGGER_RTT_CB*)p, 0, sizeof(_SEGGER_RTT)); // Make sure that the RTT CB is always zero initialized. - p->MaxNumUpBuffers = SEGGER_RTT_MAX_NUM_UP_BUFFERS; - p->MaxNumDownBuffers = SEGGER_RTT_MAX_NUM_DOWN_BUFFERS; - // - // Initialize up buffer 0 - // - p->aUp[0].sName = "Terminal"; - p->aUp[0].pBuffer = _acUpBuffer; - p->aUp[0].SizeOfBuffer = BUFFER_SIZE_UP; - p->aUp[0].RdOff = 0u; - p->aUp[0].WrOff = 0u; - p->aUp[0].Flags = SEGGER_RTT_MODE_DEFAULT; - // - // Initialize down buffer 0 - // - p->aDown[0].sName = "Terminal"; - p->aDown[0].pBuffer = _acDownBuffer; - p->aDown[0].SizeOfBuffer = BUFFER_SIZE_DOWN; - p->aDown[0].RdOff = 0u; - p->aDown[0].WrOff = 0u; - p->aDown[0].Flags = SEGGER_RTT_MODE_DEFAULT; - // - // Finish initialization of the control block. - // Copy Id string backwards to make sure that "SEGGER RTT" is not found in initializer memory (usually flash), - // as this would cause J-Link to "find" the control block at a wrong address. - // - RTT__DMB(); // Force order of memory accesses for cores that may perform out-of-order memory accesses - for (i = 0; i < sizeof(_aInitStr) - 1; ++i) { - p->acID[i] = _aInitStr[sizeof(_aInitStr) - 2 - i]; // Skip terminating \0 at the end of the array - } - RTT__DMB(); // Force order of memory accesses for cores that may perform out-of-order memory accesses -} - -/********************************************************************* -* -* _WriteBlocking() -* -* Function description -* Stores a specified number of characters in SEGGER RTT ring buffer -* and updates the associated write pointer which is periodically -* read by the host. -* The caller is responsible for managing the write chunk sizes as -* _WriteBlocking() will block until all data has been posted successfully. -* -* Parameters -* pRing Ring buffer to post to. -* pBuffer Pointer to character array. Does not need to point to a \0 terminated string. -* NumBytes Number of bytes to be stored in the SEGGER RTT control block. -* -* Return value -* >= 0 - Number of bytes written into buffer. -*/ -static unsigned _WriteBlocking(SEGGER_RTT_BUFFER_UP* pRing, const char* pBuffer, unsigned NumBytes) { - unsigned NumBytesToWrite; - unsigned NumBytesWritten; - unsigned RdOff; - unsigned WrOff; - volatile char* pDst; - // - // Write data to buffer and handle wrap-around if necessary - // - NumBytesWritten = 0u; - WrOff = pRing->WrOff; - do { - RdOff = pRing->RdOff; // May be changed by host (debug probe) in the meantime - if (RdOff > WrOff) { - NumBytesToWrite = RdOff - WrOff - 1u; - } else { - NumBytesToWrite = pRing->SizeOfBuffer - (WrOff - RdOff + 1u); - } - NumBytesToWrite = MIN(NumBytesToWrite, (pRing->SizeOfBuffer - WrOff)); // Number of bytes that can be written until buffer wrap-around - NumBytesToWrite = MIN(NumBytesToWrite, NumBytes); - pDst = (pRing->pBuffer + WrOff) + SEGGER_RTT_UNCACHED_OFF; -#if SEGGER_RTT_MEMCPY_USE_BYTELOOP - NumBytesWritten += NumBytesToWrite; - NumBytes -= NumBytesToWrite; - WrOff += NumBytesToWrite; - while (NumBytesToWrite--) { - *pDst++ = *pBuffer++; - }; -#else - SEGGER_RTT_MEMCPY((void*)pDst, pBuffer, NumBytesToWrite); - NumBytesWritten += NumBytesToWrite; - pBuffer += NumBytesToWrite; - NumBytes -= NumBytesToWrite; - WrOff += NumBytesToWrite; -#endif - if (WrOff == pRing->SizeOfBuffer) { - WrOff = 0u; - } - RTT__DMB(); // Force data write to be complete before writing the , in case CPU is allowed to change the order of memory accesses - pRing->WrOff = WrOff; - } while (NumBytes); - return NumBytesWritten; -} - -/********************************************************************* -* -* _WriteNoCheck() -* -* Function description -* Stores a specified number of characters in SEGGER RTT ring buffer -* and updates the associated write pointer which is periodically -* read by the host. -* It is callers responsibility to make sure data actually fits in buffer. -* -* Parameters -* pRing Ring buffer to post to. -* pBuffer Pointer to character array. Does not need to point to a \0 terminated string. -* NumBytes Number of bytes to be stored in the SEGGER RTT control block. -* -* Notes -* (1) If there might not be enough space in the "Up"-buffer, call _WriteBlocking -*/ -static void _WriteNoCheck(SEGGER_RTT_BUFFER_UP* pRing, const char* pData, unsigned NumBytes) { - unsigned NumBytesAtOnce; - unsigned WrOff; - unsigned Rem; - volatile char* pDst; - - WrOff = pRing->WrOff; - Rem = pRing->SizeOfBuffer - WrOff; - if (Rem > NumBytes) { - // - // All data fits before wrap around - // - pDst = (pRing->pBuffer + WrOff) + SEGGER_RTT_UNCACHED_OFF; -#if SEGGER_RTT_MEMCPY_USE_BYTELOOP - WrOff += NumBytes; - while (NumBytes--) { - *pDst++ = *pData++; - }; - RTT__DMB(); // Force data write to be complete before writing the , in case CPU is allowed to change the order of memory accesses - pRing->WrOff = WrOff; -#else - SEGGER_RTT_MEMCPY((void*)pDst, pData, NumBytes); - RTT__DMB(); // Force data write to be complete before writing the , in case CPU is allowed to change the order of memory accesses - pRing->WrOff = WrOff + NumBytes; -#endif - } else { - // - // We reach the end of the buffer, so need to wrap around - // -#if SEGGER_RTT_MEMCPY_USE_BYTELOOP - pDst = (pRing->pBuffer + WrOff) + SEGGER_RTT_UNCACHED_OFF; - NumBytesAtOnce = Rem; - while (NumBytesAtOnce--) { - *pDst++ = *pData++; - }; - pDst = pRing->pBuffer + SEGGER_RTT_UNCACHED_OFF; - NumBytesAtOnce = NumBytes - Rem; - while (NumBytesAtOnce--) { - *pDst++ = *pData++; - }; - RTT__DMB(); // Force data write to be complete before writing the , in case CPU is allowed to change the order of memory accesses - pRing->WrOff = NumBytes - Rem; -#else - NumBytesAtOnce = Rem; - pDst = (pRing->pBuffer + WrOff) + SEGGER_RTT_UNCACHED_OFF; - SEGGER_RTT_MEMCPY((void*)pDst, pData, NumBytesAtOnce); - NumBytesAtOnce = NumBytes - Rem; - pDst = pRing->pBuffer + SEGGER_RTT_UNCACHED_OFF; - SEGGER_RTT_MEMCPY((void*)pDst, pData + Rem, NumBytesAtOnce); - RTT__DMB(); // Force data write to be complete before writing the , in case CPU is allowed to change the order of memory accesses - pRing->WrOff = NumBytesAtOnce; -#endif - } -} - -/********************************************************************* -* -* _PostTerminalSwitch() -* -* Function description -* Switch terminal to the given terminal ID. It is the caller's -* responsibility to ensure the terminal ID is correct and there is -* enough space in the buffer for this to complete successfully. -* -* Parameters -* pRing Ring buffer to post to. -* TerminalId Terminal ID to switch to. -*/ -static void _PostTerminalSwitch(SEGGER_RTT_BUFFER_UP* pRing, unsigned char TerminalId) { - unsigned char ac[2]; - - ac[0] = 0xFFu; - ac[1] = _aTerminalId[TerminalId]; // Caller made already sure that TerminalId does not exceed our terminal limit - _WriteBlocking(pRing, (const char*)ac, 2u); -} - -/********************************************************************* -* -* _GetAvailWriteSpace() -* -* Function description -* Returns the number of bytes that can be written to the ring -* buffer without blocking. -* -* Parameters -* pRing Ring buffer to check. -* -* Return value -* Number of bytes that are free in the buffer. -*/ -static unsigned _GetAvailWriteSpace(SEGGER_RTT_BUFFER_UP* pRing) { - unsigned RdOff; - unsigned WrOff; - unsigned r; - // - // Avoid warnings regarding volatile access order. It's not a problem - // in this case, but dampen compiler enthusiasm. - // - RdOff = pRing->RdOff; - WrOff = pRing->WrOff; - if (RdOff <= WrOff) { - r = pRing->SizeOfBuffer - 1u - WrOff + RdOff; - } else { - r = RdOff - WrOff - 1u; - } - return r; -} - -/********************************************************************* -* -* Public code -* -********************************************************************** -*/ - -/********************************************************************* -* -* SEGGER_RTT_ReadUpBufferNoLock() -* -* Function description -* Reads characters from SEGGER real-time-terminal control block -* which have been previously stored by the application. -* Do not lock against interrupts and multiple access. -* Used to do the same operation that J-Link does, to transfer -* RTT data via other channels, such as TCP/IP or UART. -* -* Parameters -* BufferIndex Index of Up-buffer to be used. -* pBuffer Pointer to buffer provided by target application, to copy characters from RTT-up-buffer to. -* BufferSize Size of the target application buffer. -* -* Return value -* Number of bytes that have been read. -* -* Additional information -* This function must not be called when J-Link might also do RTT. -*/ -unsigned SEGGER_RTT_ReadUpBufferNoLock(unsigned BufferIndex, void* pData, unsigned BufferSize) { - unsigned NumBytesRem; - unsigned NumBytesRead; - unsigned RdOff; - unsigned WrOff; - unsigned char* pBuffer; - SEGGER_RTT_BUFFER_UP* pRing; - volatile char* pSrc; - - INIT(); - pRing = (SEGGER_RTT_BUFFER_UP*)((char*)&_SEGGER_RTT.aUp[BufferIndex] + SEGGER_RTT_UNCACHED_OFF); // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly - pBuffer = (unsigned char*)pData; - RdOff = pRing->RdOff; - WrOff = pRing->WrOff; - NumBytesRead = 0u; - // - // Read from current read position to wrap-around of buffer, first - // - if (RdOff > WrOff) { - NumBytesRem = pRing->SizeOfBuffer - RdOff; - NumBytesRem = MIN(NumBytesRem, BufferSize); - pSrc = (pRing->pBuffer + RdOff) + SEGGER_RTT_UNCACHED_OFF; -#if SEGGER_RTT_MEMCPY_USE_BYTELOOP - NumBytesRead += NumBytesRem; - BufferSize -= NumBytesRem; - RdOff += NumBytesRem; - while (NumBytesRem--) { - *pBuffer++ = *pSrc++; - }; -#else - SEGGER_RTT_MEMCPY(pBuffer, (void*)pSrc, NumBytesRem); - NumBytesRead += NumBytesRem; - pBuffer += NumBytesRem; - BufferSize -= NumBytesRem; - RdOff += NumBytesRem; -#endif - // - // Handle wrap-around of buffer - // - if (RdOff == pRing->SizeOfBuffer) { - RdOff = 0u; - } - } - // - // Read remaining items of buffer - // - NumBytesRem = WrOff - RdOff; - NumBytesRem = MIN(NumBytesRem, BufferSize); - if (NumBytesRem > 0u) { - pSrc = (pRing->pBuffer + RdOff) + SEGGER_RTT_UNCACHED_OFF; -#if SEGGER_RTT_MEMCPY_USE_BYTELOOP - NumBytesRead += NumBytesRem; - BufferSize -= NumBytesRem; - RdOff += NumBytesRem; - while (NumBytesRem--) { - *pBuffer++ = *pSrc++; - }; -#else - SEGGER_RTT_MEMCPY(pBuffer, (void*)pSrc, NumBytesRem); - NumBytesRead += NumBytesRem; - pBuffer += NumBytesRem; - BufferSize -= NumBytesRem; - RdOff += NumBytesRem; -#endif - } - // - // Update read offset of buffer - // - if (NumBytesRead) { - pRing->RdOff = RdOff; - } - // - return NumBytesRead; -} - -/********************************************************************* -* -* SEGGER_RTT_ReadNoLock() -* -* Function description -* Reads characters from SEGGER real-time-terminal control block -* which have been previously stored by the host. -* Do not lock against interrupts and multiple access. -* -* Parameters -* BufferIndex Index of Down-buffer to be used (e.g. 0 for "Terminal"). -* pBuffer Pointer to buffer provided by target application, to copy characters from RTT-down-buffer to. -* BufferSize Size of the target application buffer. -* -* Return value -* Number of bytes that have been read. -*/ -unsigned SEGGER_RTT_ReadNoLock(unsigned BufferIndex, void* pData, unsigned BufferSize) { - unsigned NumBytesRem; - unsigned NumBytesRead; - unsigned RdOff; - unsigned WrOff; - unsigned char* pBuffer; - SEGGER_RTT_BUFFER_DOWN* pRing; - volatile char* pSrc; - // - INIT(); - pRing = (SEGGER_RTT_BUFFER_DOWN*)((char*)&_SEGGER_RTT.aDown[BufferIndex] + SEGGER_RTT_UNCACHED_OFF); // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly - pBuffer = (unsigned char*)pData; - RdOff = pRing->RdOff; - WrOff = pRing->WrOff; - NumBytesRead = 0u; - // - // Read from current read position to wrap-around of buffer, first - // - if (RdOff > WrOff) { - NumBytesRem = pRing->SizeOfBuffer - RdOff; - NumBytesRem = MIN(NumBytesRem, BufferSize); - pSrc = (pRing->pBuffer + RdOff) + SEGGER_RTT_UNCACHED_OFF; -#if SEGGER_RTT_MEMCPY_USE_BYTELOOP - NumBytesRead += NumBytesRem; - BufferSize -= NumBytesRem; - RdOff += NumBytesRem; - while (NumBytesRem--) { - *pBuffer++ = *pSrc++; - }; -#else - SEGGER_RTT_MEMCPY(pBuffer, (void*)pSrc, NumBytesRem); - NumBytesRead += NumBytesRem; - pBuffer += NumBytesRem; - BufferSize -= NumBytesRem; - RdOff += NumBytesRem; -#endif - // - // Handle wrap-around of buffer - // - if (RdOff == pRing->SizeOfBuffer) { - RdOff = 0u; - } - } - // - // Read remaining items of buffer - // - NumBytesRem = WrOff - RdOff; - NumBytesRem = MIN(NumBytesRem, BufferSize); - if (NumBytesRem > 0u) { - pSrc = (pRing->pBuffer + RdOff) + SEGGER_RTT_UNCACHED_OFF; -#if SEGGER_RTT_MEMCPY_USE_BYTELOOP - NumBytesRead += NumBytesRem; - BufferSize -= NumBytesRem; - RdOff += NumBytesRem; - while (NumBytesRem--) { - *pBuffer++ = *pSrc++; - }; -#else - SEGGER_RTT_MEMCPY(pBuffer, (void*)pSrc, NumBytesRem); - NumBytesRead += NumBytesRem; - pBuffer += NumBytesRem; - BufferSize -= NumBytesRem; - RdOff += NumBytesRem; -#endif - } - if (NumBytesRead) { - pRing->RdOff = RdOff; - } - // - return NumBytesRead; -} - -/********************************************************************* -* -* SEGGER_RTT_ReadUpBuffer -* -* Function description -* Reads characters from SEGGER real-time-terminal control block -* which have been previously stored by the application. -* Used to do the same operation that J-Link does, to transfer -* RTT data via other channels, such as TCP/IP or UART. -* -* Parameters -* BufferIndex Index of Up-buffer to be used. -* pBuffer Pointer to buffer provided by target application, to copy characters from RTT-up-buffer to. -* BufferSize Size of the target application buffer. -* -* Return value -* Number of bytes that have been read. -* -* Additional information -* This function must not be called when J-Link might also do RTT. -* This function locks against all other RTT operations. I.e. during -* the read operation, writing is also locked. -* If only one consumer reads from the up buffer, -* call sEGGER_RTT_ReadUpBufferNoLock() instead. -*/ -unsigned SEGGER_RTT_ReadUpBuffer(unsigned BufferIndex, void* pBuffer, unsigned BufferSize) { - unsigned NumBytesRead; - - SEGGER_RTT_LOCK(); - // - // Call the non-locking read function - // - NumBytesRead = SEGGER_RTT_ReadUpBufferNoLock(BufferIndex, pBuffer, BufferSize); - // - // Finish up. - // - SEGGER_RTT_UNLOCK(); - // - return NumBytesRead; -} - -/********************************************************************* -* -* SEGGER_RTT_Read -* -* Function description -* Reads characters from SEGGER real-time-terminal control block -* which have been previously stored by the host. -* -* Parameters -* BufferIndex Index of Down-buffer to be used (e.g. 0 for "Terminal"). -* pBuffer Pointer to buffer provided by target application, to copy characters from RTT-down-buffer to. -* BufferSize Size of the target application buffer. -* -* Return value -* Number of bytes that have been read. -*/ -unsigned SEGGER_RTT_Read(unsigned BufferIndex, void* pBuffer, unsigned BufferSize) { - unsigned NumBytesRead; - - SEGGER_RTT_LOCK(); - // - // Call the non-locking read function - // - NumBytesRead = SEGGER_RTT_ReadNoLock(BufferIndex, pBuffer, BufferSize); - // - // Finish up. - // - SEGGER_RTT_UNLOCK(); - // - return NumBytesRead; -} - -/********************************************************************* -* -* SEGGER_RTT_WriteWithOverwriteNoLock -* -* Function description -* Stores a specified number of characters in SEGGER RTT -* control block. -* SEGGER_RTT_WriteWithOverwriteNoLock does not lock the application -* and overwrites data if the data does not fit into the buffer. -* -* Parameters -* BufferIndex Index of "Up"-buffer to be used (e.g. 0 for "Terminal"). -* pBuffer Pointer to character array. Does not need to point to a \0 terminated string. -* NumBytes Number of bytes to be stored in the SEGGER RTT control block. -* -* Notes -* (1) If there is not enough space in the "Up"-buffer, data is overwritten. -* (2) For performance reasons this function does not call Init() -* and may only be called after RTT has been initialized. -* Either by calling SEGGER_RTT_Init() or calling another RTT API function first. -* (3) Do not use SEGGER_RTT_WriteWithOverwriteNoLock if a J-Link -* connection reads RTT data. -*/ -void SEGGER_RTT_WriteWithOverwriteNoLock(unsigned BufferIndex, const void* pBuffer, unsigned NumBytes) { - const char* pData; - SEGGER_RTT_BUFFER_UP* pRing; - unsigned Avail; - volatile char* pDst; - // - // Get "to-host" ring buffer and copy some elements into local variables. - // - pData = (const char *)pBuffer; - pRing = (SEGGER_RTT_BUFFER_UP*)((char*)&_SEGGER_RTT.aUp[BufferIndex] + SEGGER_RTT_UNCACHED_OFF); // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly - // - // Check if we will overwrite data and need to adjust the RdOff. - // - if (pRing->WrOff == pRing->RdOff) { - Avail = pRing->SizeOfBuffer - 1u; - } else if ( pRing->WrOff < pRing->RdOff) { - Avail = pRing->RdOff - pRing->WrOff - 1u; - } else { - Avail = pRing->RdOff - pRing->WrOff - 1u + pRing->SizeOfBuffer; - } - if (NumBytes > Avail) { - pRing->RdOff += (NumBytes - Avail); - while (pRing->RdOff >= pRing->SizeOfBuffer) { - pRing->RdOff -= pRing->SizeOfBuffer; - } - } - // - // Write all data, no need to check the RdOff, but possibly handle multiple wrap-arounds - // - Avail = pRing->SizeOfBuffer - pRing->WrOff; - do { - if (Avail > NumBytes) { - // - // Last round - // - pDst = (pRing->pBuffer + pRing->WrOff) + SEGGER_RTT_UNCACHED_OFF; -#if SEGGER_RTT_MEMCPY_USE_BYTELOOP - Avail = NumBytes; - while (NumBytes--) { - *pDst++ = *pData++; - }; - RTT__DMB(); // Force data write to be complete before writing the , in case CPU is allowed to change the order of memory accesses - pRing->WrOff += Avail; -#else - SEGGER_RTT_MEMCPY((void*)pDst, pData, NumBytes); - RTT__DMB(); // Force data write to be complete before writing the , in case CPU is allowed to change the order of memory accesses - pRing->WrOff += NumBytes; -#endif - break; - } else { - // - // Wrap-around necessary, write until wrap-around and reset WrOff - // - pDst = (pRing->pBuffer + pRing->WrOff) + SEGGER_RTT_UNCACHED_OFF; -#if SEGGER_RTT_MEMCPY_USE_BYTELOOP - NumBytes -= Avail; - while (Avail--) { - *pDst++ = *pData++; - }; - RTT__DMB(); // Force data write to be complete before writing the , in case CPU is allowed to change the order of memory accesses - pRing->WrOff = 0; -#else - SEGGER_RTT_MEMCPY((void*)pDst, pData, Avail); - pData += Avail; - RTT__DMB(); // Force data write to be complete before writing the , in case CPU is allowed to change the order of memory accesses - pRing->WrOff = 0; - NumBytes -= Avail; -#endif - Avail = (pRing->SizeOfBuffer - 1); - } - } while (NumBytes); -} - -/********************************************************************* -* -* SEGGER_RTT_WriteSkipNoLock -* -* Function description -* Stores a specified number of characters in SEGGER RTT -* control block which is then read by the host. -* SEGGER_RTT_WriteSkipNoLock does not lock the application and -* skips all data, if the data does not fit into the buffer. -* -* Parameters -* BufferIndex Index of "Up"-buffer to be used (e.g. 0 for "Terminal"). -* pBuffer Pointer to character array. Does not need to point to a \0 terminated string. -* NumBytes Number of bytes to be stored in the SEGGER RTT control block. -* MUST be > 0!!! -* This is done for performance reasons, so no initial check has do be done. -* -* Return value -* 1: Data has been copied -* 0: No space, data has not been copied -* -* Notes -* (1) If there is not enough space in the "Up"-buffer, all data is dropped. -* (2) For performance reasons this function does not call Init() -* and may only be called after RTT has been initialized. -* Either by calling SEGGER_RTT_Init() or calling another RTT API function first. -*/ -#if (RTT_USE_ASM == 0) -unsigned SEGGER_RTT_WriteSkipNoLock(unsigned BufferIndex, const void* pBuffer, unsigned NumBytes) { - const char* pData; - SEGGER_RTT_BUFFER_UP* pRing; - unsigned Avail; - unsigned RdOff; - unsigned WrOff; - unsigned Rem; - volatile char* pDst; - // - // Cases: - // 1) RdOff <= WrOff => Space until wrap-around is sufficient - // 2) RdOff <= WrOff => Space after wrap-around needed (copy in 2 chunks) - // 3) RdOff < WrOff => No space in buf - // 4) RdOff > WrOff => Space is sufficient - // 5) RdOff > WrOff => No space in buf - // - // 1) is the most common case for large buffers and assuming that J-Link reads the data fast enough - // - pData = (const char *)pBuffer; - pRing = (SEGGER_RTT_BUFFER_UP*)((char*)&_SEGGER_RTT.aUp[BufferIndex] + SEGGER_RTT_UNCACHED_OFF); // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly - RdOff = pRing->RdOff; - WrOff = pRing->WrOff; - pDst = (pRing->pBuffer + WrOff) + SEGGER_RTT_UNCACHED_OFF; - if (RdOff <= WrOff) { // Case 1), 2) or 3) - Avail = pRing->SizeOfBuffer - WrOff - 1u; // Space until wrap-around (assume 1 byte not usable for case that RdOff == 0) - if (Avail >= NumBytes) { // Case 1)? - memcpy((void*)pDst, pData, NumBytes); - RTT__DMB(); // Force data write to be complete before writing the , in case CPU is allowed to change the order of memory accesses - pRing->WrOff = WrOff + NumBytes; - return 1; - } - Avail += RdOff; // Space incl. wrap-around - if (Avail >= NumBytes) { // Case 2? => If not, we have case 3) (does not fit) - Rem = pRing->SizeOfBuffer - WrOff; // Space until end of buffer - memcpy((void*)pDst, pData, Rem); // Copy 1st chunk - NumBytes -= Rem; - // - // Special case: First check that assumed RdOff == 0 calculated that last element before wrap-around could not be used - // But 2nd check (considering space until wrap-around and until RdOff) revealed that RdOff is not 0, so we can use the last element - // In this case, we may use a copy straight until buffer end anyway without needing to copy 2 chunks - // Therefore, check if 2nd memcpy is necessary at all - // - if (NumBytes) { - pDst = pRing->pBuffer + SEGGER_RTT_UNCACHED_OFF; - memcpy((void*)pDst, pData + Rem, NumBytes); - } - RTT__DMB(); // Force data write to be complete before writing the , in case CPU is allowed to change the order of memory accesses - pRing->WrOff = NumBytes; - return 1; - } - } else { // Potential case 4) - Avail = RdOff - WrOff - 1u; - if (Avail >= NumBytes) { // Case 4)? => If not, we have case 5) (does not fit) - memcpy((void*)pDst, pData, NumBytes); - RTT__DMB(); // Force data write to be complete before writing the , in case CPU is allowed to change the order of memory accesses - pRing->WrOff = WrOff + NumBytes; - return 1; - } - } - return 0; // No space in buffer -} -#endif - -/********************************************************************* -* -* SEGGER_RTT_WriteDownBufferNoLock -* -* Function description -* Stores a specified number of characters in SEGGER RTT -* control block inside a buffer. -* SEGGER_RTT_WriteDownBufferNoLock does not lock the application. -* Used to do the same operation that J-Link does, to transfer -* RTT data from other channels, such as TCP/IP or UART. -* -* Parameters -* BufferIndex Index of "Down"-buffer to be used. -* pBuffer Pointer to character array. Does not need to point to a \0 terminated string. -* NumBytes Number of bytes to be stored in the SEGGER RTT control block. -* -* Return value -* Number of bytes which have been stored in the "Down"-buffer. -* -* Notes -* (1) Data is stored according to buffer flags. -* (2) For performance reasons this function does not call Init() -* and may only be called after RTT has been initialized. -* Either by calling SEGGER_RTT_Init() or calling another RTT API function first. -* -* Additional information -* This function must not be called when J-Link might also do RTT. -*/ -unsigned SEGGER_RTT_WriteDownBufferNoLock(unsigned BufferIndex, const void* pBuffer, unsigned NumBytes) { - unsigned Status; - unsigned Avail; - const char* pData; - SEGGER_RTT_BUFFER_UP* pRing; - // - // Get "to-target" ring buffer. - // It is save to cast that to a "to-host" buffer. Up and Down buffer differ in volatility of offsets that might be modified by J-Link. - // - pData = (const char *)pBuffer; - pRing = (SEGGER_RTT_BUFFER_UP*)((char*)&_SEGGER_RTT.aDown[BufferIndex] + SEGGER_RTT_UNCACHED_OFF); // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly - // - // How we output depends upon the mode... - // - switch (pRing->Flags) { - case SEGGER_RTT_MODE_NO_BLOCK_SKIP: - // - // If we are in skip mode and there is no space for the whole - // of this output, don't bother. - // - Avail = _GetAvailWriteSpace(pRing); - if (Avail < NumBytes) { - Status = 0u; - } else { - Status = NumBytes; - _WriteNoCheck(pRing, pData, NumBytes); - } - break; - case SEGGER_RTT_MODE_NO_BLOCK_TRIM: - // - // If we are in trim mode, trim to what we can output without blocking. - // - Avail = _GetAvailWriteSpace(pRing); - Status = Avail < NumBytes ? Avail : NumBytes; - _WriteNoCheck(pRing, pData, Status); - break; - case SEGGER_RTT_MODE_BLOCK_IF_FIFO_FULL: - // - // If we are in blocking mode, output everything. - // - Status = _WriteBlocking(pRing, pData, NumBytes); - break; - default: - Status = 0u; - break; - } - // - // Finish up. - // - return Status; -} - -/********************************************************************* -* -* SEGGER_RTT_WriteNoLock -* -* Function description -* Stores a specified number of characters in SEGGER RTT -* control block which is then read by the host. -* SEGGER_RTT_WriteNoLock does not lock the application. -* -* Parameters -* BufferIndex Index of "Up"-buffer to be used (e.g. 0 for "Terminal"). -* pBuffer Pointer to character array. Does not need to point to a \0 terminated string. -* NumBytes Number of bytes to be stored in the SEGGER RTT control block. -* -* Return value -* Number of bytes which have been stored in the "Up"-buffer. -* -* Notes -* (1) Data is stored according to buffer flags. -* (2) For performance reasons this function does not call Init() -* and may only be called after RTT has been initialized. -* Either by calling SEGGER_RTT_Init() or calling another RTT API function first. -*/ -unsigned SEGGER_RTT_WriteNoLock(unsigned BufferIndex, const void* pBuffer, unsigned NumBytes) { - unsigned Status; - unsigned Avail; - const char* pData; - SEGGER_RTT_BUFFER_UP* pRing; - // - // Get "to-host" ring buffer. - // - pData = (const char *)pBuffer; - pRing = (SEGGER_RTT_BUFFER_UP*)((char*)&_SEGGER_RTT.aUp[BufferIndex] + SEGGER_RTT_UNCACHED_OFF); // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly - // - // How we output depends upon the mode... - // - switch (pRing->Flags) { - case SEGGER_RTT_MODE_NO_BLOCK_SKIP: - // - // If we are in skip mode and there is no space for the whole - // of this output, don't bother. - // - Avail = _GetAvailWriteSpace(pRing); - if (Avail < NumBytes) { - Status = 0u; - } else { - Status = NumBytes; - _WriteNoCheck(pRing, pData, NumBytes); - } - break; - case SEGGER_RTT_MODE_NO_BLOCK_TRIM: - // - // If we are in trim mode, trim to what we can output without blocking. - // - Avail = _GetAvailWriteSpace(pRing); - Status = Avail < NumBytes ? Avail : NumBytes; - _WriteNoCheck(pRing, pData, Status); - break; - case SEGGER_RTT_MODE_BLOCK_IF_FIFO_FULL: - // - // If we are in blocking mode, output everything. - // - Status = _WriteBlocking(pRing, pData, NumBytes); - break; - default: - Status = 0u; - break; - } - // - // Finish up. - // - return Status; -} - -/********************************************************************* -* -* SEGGER_RTT_WriteDownBuffer -* -* Function description -* Stores a specified number of characters in SEGGER RTT control block in a buffer. -* -* Parameters -* BufferIndex Index of "Up"-buffer to be used (e.g. 0 for "Terminal"). -* pBuffer Pointer to character array. Does not need to point to a \0 terminated string. -* NumBytes Number of bytes to be stored in the SEGGER RTT control block. -* -* Return value -* Number of bytes which have been stored in the "Down"-buffer. -* -* Notes -* (1) Data is stored according to buffer flags. -* -* Additional information -* This function must not be called when J-Link might also do RTT. -* This function locks against all other RTT operations. I.e. during -* the write operation, writing from the application is also locked. -* If only one consumer writes to the down buffer, -* call SEGGER_RTT_WriteDownBufferNoLock() instead. -*/ -unsigned SEGGER_RTT_WriteDownBuffer(unsigned BufferIndex, const void* pBuffer, unsigned NumBytes) { - unsigned Status; - - INIT(); - SEGGER_RTT_LOCK(); - Status = SEGGER_RTT_WriteDownBufferNoLock(BufferIndex, pBuffer, NumBytes); // Call the non-locking write function - SEGGER_RTT_UNLOCK(); - return Status; -} - -/********************************************************************* -* -* SEGGER_RTT_Write -* -* Function description -* Stores a specified number of characters in SEGGER RTT -* control block which is then read by the host. -* -* Parameters -* BufferIndex Index of "Up"-buffer to be used (e.g. 0 for "Terminal"). -* pBuffer Pointer to character array. Does not need to point to a \0 terminated string. -* NumBytes Number of bytes to be stored in the SEGGER RTT control block. -* -* Return value -* Number of bytes which have been stored in the "Up"-buffer. -* -* Notes -* (1) Data is stored according to buffer flags. -*/ -unsigned SEGGER_RTT_Write(unsigned BufferIndex, const void* pBuffer, unsigned NumBytes) { - unsigned Status; - - INIT(); - SEGGER_RTT_LOCK(); - Status = SEGGER_RTT_WriteNoLock(BufferIndex, pBuffer, NumBytes); // Call the non-locking write function - SEGGER_RTT_UNLOCK(); - return Status; -} - -/********************************************************************* -* -* SEGGER_RTT_WriteString -* -* Function description -* Stores string in SEGGER RTT control block. -* This data is read by the host. -* -* Parameters -* BufferIndex Index of "Up"-buffer to be used (e.g. 0 for "Terminal"). -* s Pointer to string. -* -* Return value -* Number of bytes which have been stored in the "Up"-buffer. -* -* Notes -* (1) Data is stored according to buffer flags. -* (2) String passed to this function has to be \0 terminated -* (3) \0 termination character is *not* stored in RTT buffer -*/ -unsigned SEGGER_RTT_WriteString(unsigned BufferIndex, const char* s) { - unsigned Len; - - Len = STRLEN(s); - return SEGGER_RTT_Write(BufferIndex, s, Len); -} - -/********************************************************************* -* -* SEGGER_RTT_PutCharSkipNoLock -* -* Function description -* Stores a single character/byte in SEGGER RTT buffer. -* SEGGER_RTT_PutCharSkipNoLock does not lock the application and -* skips the byte, if it does not fit into the buffer. -* -* Parameters -* BufferIndex Index of "Up"-buffer to be used (e.g. 0 for "Terminal"). -* c Byte to be stored. -* -* Return value -* Number of bytes which have been stored in the "Up"-buffer. -* -* Notes -* (1) If there is not enough space in the "Up"-buffer, the character is dropped. -* (2) For performance reasons this function does not call Init() -* and may only be called after RTT has been initialized. -* Either by calling SEGGER_RTT_Init() or calling another RTT API function first. -*/ - -unsigned SEGGER_RTT_PutCharSkipNoLock(unsigned BufferIndex, char c) { - SEGGER_RTT_BUFFER_UP* pRing; - unsigned WrOff; - unsigned Status; - volatile char* pDst; - // - // Get "to-host" ring buffer. - // - pRing = (SEGGER_RTT_BUFFER_UP*)((char*)&_SEGGER_RTT.aUp[BufferIndex] + SEGGER_RTT_UNCACHED_OFF); // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly - // - // Get write position and handle wrap-around if necessary - // - WrOff = pRing->WrOff + 1; - if (WrOff == pRing->SizeOfBuffer) { - WrOff = 0; - } - // - // Output byte if free space is available - // - if (WrOff != pRing->RdOff) { - pDst = (pRing->pBuffer + pRing->WrOff) + SEGGER_RTT_UNCACHED_OFF; - *pDst = c; - RTT__DMB(); // Force data write to be complete before writing the , in case CPU is allowed to change the order of memory accesses - pRing->WrOff = WrOff; - Status = 1; - } else { - Status = 0; - } - // - return Status; -} - -/********************************************************************* -* -* SEGGER_RTT_PutCharSkip -* -* Function description -* Stores a single character/byte in SEGGER RTT buffer. -* -* Parameters -* BufferIndex Index of "Up"-buffer to be used (e.g. 0 for "Terminal"). -* c Byte to be stored. -* -* Return value -* Number of bytes which have been stored in the "Up"-buffer. -* -* Notes -* (1) If there is not enough space in the "Up"-buffer, the character is dropped. -*/ - -unsigned SEGGER_RTT_PutCharSkip(unsigned BufferIndex, char c) { - SEGGER_RTT_BUFFER_UP* pRing; - unsigned WrOff; - unsigned Status; - volatile char* pDst; - // - // Prepare - // - INIT(); - SEGGER_RTT_LOCK(); - // - // Get "to-host" ring buffer. - // - pRing = (SEGGER_RTT_BUFFER_UP*)((char*)&_SEGGER_RTT.aUp[BufferIndex] + SEGGER_RTT_UNCACHED_OFF); // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly - // - // Get write position and handle wrap-around if necessary - // - WrOff = pRing->WrOff + 1; - if (WrOff == pRing->SizeOfBuffer) { - WrOff = 0; - } - // - // Output byte if free space is available - // - if (WrOff != pRing->RdOff) { - pDst = (pRing->pBuffer + pRing->WrOff) + SEGGER_RTT_UNCACHED_OFF; - *pDst = c; - RTT__DMB(); // Force data write to be complete before writing the , in case CPU is allowed to change the order of memory accesses - pRing->WrOff = WrOff; - Status = 1; - } else { - Status = 0; - } - // - // Finish up. - // - SEGGER_RTT_UNLOCK(); - // - return Status; -} - - /********************************************************************* -* -* SEGGER_RTT_PutChar -* -* Function description -* Stores a single character/byte in SEGGER RTT buffer. -* -* Parameters -* BufferIndex Index of "Up"-buffer to be used (e.g. 0 for "Terminal"). -* c Byte to be stored. -* -* Return value -* Number of bytes which have been stored in the "Up"-buffer. -* -* Notes -* (1) Data is stored according to buffer flags. -*/ - -unsigned SEGGER_RTT_PutChar(unsigned BufferIndex, char c) { - SEGGER_RTT_BUFFER_UP* pRing; - unsigned WrOff; - unsigned Status; - volatile char* pDst; - // - // Prepare - // - INIT(); - SEGGER_RTT_LOCK(); - // - // Get "to-host" ring buffer. - // - pRing = (SEGGER_RTT_BUFFER_UP*)((char*)&_SEGGER_RTT.aUp[BufferIndex] + SEGGER_RTT_UNCACHED_OFF); // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly - // - // Get write position and handle wrap-around if necessary - // - WrOff = pRing->WrOff + 1; - if (WrOff == pRing->SizeOfBuffer) { - WrOff = 0; - } - // - // Wait for free space if mode is set to blocking - // - if (pRing->Flags == SEGGER_RTT_MODE_BLOCK_IF_FIFO_FULL) { - while (WrOff == pRing->RdOff) { - ; - } - } - // - // Output byte if free space is available - // - if (WrOff != pRing->RdOff) { - pDst = (pRing->pBuffer + pRing->WrOff) + SEGGER_RTT_UNCACHED_OFF; - *pDst = c; - RTT__DMB(); // Force data write to be complete before writing the , in case CPU is allowed to change the order of memory accesses - pRing->WrOff = WrOff; - Status = 1; - } else { - Status = 0; - } - // - // Finish up. - // - SEGGER_RTT_UNLOCK(); - return Status; -} - -/********************************************************************* -* -* SEGGER_RTT_GetKey -* -* Function description -* Reads one character from the SEGGER RTT buffer. -* Host has previously stored data there. -* -* Return value -* < 0 - No character available (buffer empty). -* >= 0 - Character which has been read. (Possible values: 0 - 255) -* -* Notes -* (1) This function is only specified for accesses to RTT buffer 0. -*/ -int SEGGER_RTT_GetKey(void) { - char c; - int r; - - r = (int)SEGGER_RTT_Read(0u, &c, 1u); - if (r == 1) { - r = (int)(unsigned char)c; - } else { - r = -1; - } - return r; -} - -/********************************************************************* -* -* SEGGER_RTT_WaitKey -* -* Function description -* Waits until at least one character is avaible in the SEGGER RTT buffer. -* Once a character is available, it is read and this function returns. -* -* Return value -* >=0 - Character which has been read. -* -* Notes -* (1) This function is only specified for accesses to RTT buffer 0 -* (2) This function is blocking if no character is present in RTT buffer -*/ -int SEGGER_RTT_WaitKey(void) { - int r; - - do { - r = SEGGER_RTT_GetKey(); - } while (r < 0); - return r; -} - -/********************************************************************* -* -* SEGGER_RTT_HasKey -* -* Function description -* Checks if at least one character for reading is available in the SEGGER RTT buffer. -* -* Return value -* == 0 - No characters are available to read. -* == 1 - At least one character is available. -* -* Notes -* (1) This function is only specified for accesses to RTT buffer 0 -*/ -int SEGGER_RTT_HasKey(void) { - SEGGER_RTT_BUFFER_DOWN* pRing; - unsigned RdOff; - int r; - - INIT(); - pRing = (SEGGER_RTT_BUFFER_DOWN*)((char*)&_SEGGER_RTT.aDown[0] + SEGGER_RTT_UNCACHED_OFF); // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly - RdOff = pRing->RdOff; - if (RdOff != pRing->WrOff) { - r = 1; - } else { - r = 0; - } - return r; -} - -/********************************************************************* -* -* SEGGER_RTT_HasData -* -* Function description -* Check if there is data from the host in the given buffer. -* -* Return value: -* ==0: No data -* !=0: Data in buffer -* -*/ -unsigned SEGGER_RTT_HasData(unsigned BufferIndex) { - SEGGER_RTT_BUFFER_DOWN* pRing; - unsigned v; - - pRing = (SEGGER_RTT_BUFFER_DOWN*)((char*)&_SEGGER_RTT.aDown[BufferIndex] + SEGGER_RTT_UNCACHED_OFF); // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly - v = pRing->WrOff; - return v - pRing->RdOff; -} - -/********************************************************************* -* -* SEGGER_RTT_HasDataUp -* -* Function description -* Check if there is data remaining to be sent in the given buffer. -* -* Return value: -* ==0: No data -* !=0: Data in buffer -* -*/ -unsigned SEGGER_RTT_HasDataUp(unsigned BufferIndex) { - SEGGER_RTT_BUFFER_UP* pRing; - unsigned v; - - pRing = (SEGGER_RTT_BUFFER_UP*)((char*)&_SEGGER_RTT.aUp[BufferIndex] + SEGGER_RTT_UNCACHED_OFF); // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly - v = pRing->RdOff; - return pRing->WrOff - v; -} - -/********************************************************************* -* -* SEGGER_RTT_AllocDownBuffer -* -* Function description -* Run-time configuration of the next down-buffer (H->T). -* The next buffer, which is not used yet is configured. -* This includes: Buffer address, size, name, flags, ... -* -* Parameters -* sName Pointer to a constant name string. -* pBuffer Pointer to a buffer to be used. -* BufferSize Size of the buffer. -* Flags Operating modes. Define behavior if buffer is full (not enough space for entire message). -* Flags[31:24] are used for validity check and must be zero. Flags[23:2] are reserved for future use. Flags[1:0] = RTT operating mode. -* -* Return value -* >= 0 - O.K. Buffer Index -* < 0 - Error -*/ -int SEGGER_RTT_AllocDownBuffer(const char* sName, void* pBuffer, unsigned BufferSize, unsigned Flags) { - int BufferIndex; - volatile SEGGER_RTT_CB* pRTTCB; - - INIT(); - SEGGER_RTT_LOCK(); - pRTTCB = (volatile SEGGER_RTT_CB*)((unsigned char*)&_SEGGER_RTT + SEGGER_RTT_UNCACHED_OFF); // Access RTTCB uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly - BufferIndex = 0; - do { - if (pRTTCB->aDown[BufferIndex].pBuffer == NULL) { - break; - } - BufferIndex++; - } while (BufferIndex < pRTTCB->MaxNumDownBuffers); - if (BufferIndex < pRTTCB->MaxNumDownBuffers) { - pRTTCB->aDown[BufferIndex].sName = sName; - pRTTCB->aDown[BufferIndex].pBuffer = (char*)pBuffer; - pRTTCB->aDown[BufferIndex].SizeOfBuffer = BufferSize; - pRTTCB->aDown[BufferIndex].RdOff = 0u; - pRTTCB->aDown[BufferIndex].WrOff = 0u; - pRTTCB->aDown[BufferIndex].Flags = Flags; - RTT__DMB(); // Force data write to be complete before writing the , in case CPU is allowed to change the order of memory accesses - } else { - BufferIndex = -1; - } - SEGGER_RTT_UNLOCK(); - return BufferIndex; -} - -/********************************************************************* -* -* SEGGER_RTT_AllocUpBuffer -* -* Function description -* Run-time configuration of the next up-buffer (T->H). -* The next buffer, which is not used yet is configured. -* This includes: Buffer address, size, name, flags, ... -* -* Parameters -* sName Pointer to a constant name string. -* pBuffer Pointer to a buffer to be used. -* BufferSize Size of the buffer. -* Flags Operating modes. Define behavior if buffer is full (not enough space for entire message). -* Flags[31:24] are used for validity check and must be zero. Flags[23:2] are reserved for future use. Flags[1:0] = RTT operating mode. -* -* Return value -* >= 0 - O.K. Buffer Index -* < 0 - Error -*/ -int SEGGER_RTT_AllocUpBuffer(const char* sName, void* pBuffer, unsigned BufferSize, unsigned Flags) { - int BufferIndex; - volatile SEGGER_RTT_CB* pRTTCB; - - INIT(); - SEGGER_RTT_LOCK(); - pRTTCB = (volatile SEGGER_RTT_CB*)((unsigned char*)&_SEGGER_RTT + SEGGER_RTT_UNCACHED_OFF); // Access RTTCB uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly - BufferIndex = 0; - do { - if (pRTTCB->aUp[BufferIndex].pBuffer == NULL) { - break; - } - BufferIndex++; - } while (BufferIndex < pRTTCB->MaxNumUpBuffers); - if (BufferIndex < pRTTCB->MaxNumUpBuffers) { - pRTTCB->aUp[BufferIndex].sName = sName; - pRTTCB->aUp[BufferIndex].pBuffer = (char*)pBuffer; - pRTTCB->aUp[BufferIndex].SizeOfBuffer = BufferSize; - pRTTCB->aUp[BufferIndex].RdOff = 0u; - pRTTCB->aUp[BufferIndex].WrOff = 0u; - pRTTCB->aUp[BufferIndex].Flags = Flags; - RTT__DMB(); // Force data write to be complete before writing the , in case CPU is allowed to change the order of memory accesses - } else { - BufferIndex = -1; - } - SEGGER_RTT_UNLOCK(); - return BufferIndex; -} - -/********************************************************************* -* -* SEGGER_RTT_ConfigUpBuffer -* -* Function description -* Run-time configuration of a specific up-buffer (T->H). -* Buffer to be configured is specified by index. -* This includes: Buffer address, size, name, flags, ... -* -* Parameters -* BufferIndex Index of the buffer to configure. -* sName Pointer to a constant name string. -* pBuffer Pointer to a buffer to be used. -* BufferSize Size of the buffer. -* Flags Operating modes. Define behavior if buffer is full (not enough space for entire message). -* Flags[31:24] are used for validity check and must be zero. Flags[23:2] are reserved for future use. Flags[1:0] = RTT operating mode. -* -* Return value -* >= 0 - O.K. -* < 0 - Error -* -* Additional information -* Buffer 0 is configured on compile-time. -* May only be called once per buffer. -* Buffer name and flags can be reconfigured using the appropriate functions. -*/ -int SEGGER_RTT_ConfigUpBuffer(unsigned BufferIndex, const char* sName, void* pBuffer, unsigned BufferSize, unsigned Flags) { - int r; - volatile SEGGER_RTT_CB* pRTTCB; - volatile SEGGER_RTT_BUFFER_UP* pUp; - - INIT(); - pRTTCB = (volatile SEGGER_RTT_CB*)((unsigned char*)&_SEGGER_RTT + SEGGER_RTT_UNCACHED_OFF); // Access RTTCB uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly - if (BufferIndex < SEGGER_RTT_MAX_NUM_UP_BUFFERS) { - SEGGER_RTT_LOCK(); - pUp = &pRTTCB->aUp[BufferIndex]; - if (BufferIndex) { - pUp->sName = sName; - pUp->pBuffer = (char*)pBuffer; - pUp->SizeOfBuffer = BufferSize; - pUp->RdOff = 0u; - pUp->WrOff = 0u; - } - pUp->Flags = Flags; - SEGGER_RTT_UNLOCK(); - r = 0; - } else { - r = -1; - } - return r; -} - -/********************************************************************* -* -* SEGGER_RTT_ConfigDownBuffer -* -* Function description -* Run-time configuration of a specific down-buffer (H->T). -* Buffer to be configured is specified by index. -* This includes: Buffer address, size, name, flags, ... -* -* Parameters -* BufferIndex Index of the buffer to configure. -* sName Pointer to a constant name string. -* pBuffer Pointer to a buffer to be used. -* BufferSize Size of the buffer. -* Flags Operating modes. Define behavior if buffer is full (not enough space for entire message). -* Flags[31:24] are used for validity check and must be zero. Flags[23:2] are reserved for future use. Flags[1:0] = RTT operating mode. -* -* Return value -* >= 0 O.K. -* < 0 Error -* -* Additional information -* Buffer 0 is configured on compile-time. -* May only be called once per buffer. -* Buffer name and flags can be reconfigured using the appropriate functions. -*/ -int SEGGER_RTT_ConfigDownBuffer(unsigned BufferIndex, const char* sName, void* pBuffer, unsigned BufferSize, unsigned Flags) { - int r; - volatile SEGGER_RTT_CB* pRTTCB; - volatile SEGGER_RTT_BUFFER_DOWN* pDown; - - INIT(); - pRTTCB = (volatile SEGGER_RTT_CB*)((unsigned char*)&_SEGGER_RTT + SEGGER_RTT_UNCACHED_OFF); // Access RTTCB uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly - if (BufferIndex < SEGGER_RTT_MAX_NUM_DOWN_BUFFERS) { - SEGGER_RTT_LOCK(); - pDown = &pRTTCB->aDown[BufferIndex]; - if (BufferIndex) { - pDown->sName = sName; - pDown->pBuffer = (char*)pBuffer; - pDown->SizeOfBuffer = BufferSize; - pDown->RdOff = 0u; - pDown->WrOff = 0u; - } - pDown->Flags = Flags; - RTT__DMB(); // Force data write to be complete before writing the , in case CPU is allowed to change the order of memory accesses - SEGGER_RTT_UNLOCK(); - r = 0; - } else { - r = -1; - } - return r; -} - -/********************************************************************* -* -* SEGGER_RTT_SetNameUpBuffer -* -* Function description -* Run-time configuration of a specific up-buffer name (T->H). -* Buffer to be configured is specified by index. -* -* Parameters -* BufferIndex Index of the buffer to renamed. -* sName Pointer to a constant name string. -* -* Return value -* >= 0 O.K. -* < 0 Error -*/ -int SEGGER_RTT_SetNameUpBuffer(unsigned BufferIndex, const char* sName) { - int r; - volatile SEGGER_RTT_CB* pRTTCB; - volatile SEGGER_RTT_BUFFER_UP* pUp; - - INIT(); - pRTTCB = (volatile SEGGER_RTT_CB*)((unsigned char*)&_SEGGER_RTT + SEGGER_RTT_UNCACHED_OFF); // Access RTTCB uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly - if (BufferIndex < SEGGER_RTT_MAX_NUM_UP_BUFFERS) { - SEGGER_RTT_LOCK(); - pUp = &pRTTCB->aUp[BufferIndex]; - pUp->sName = sName; - SEGGER_RTT_UNLOCK(); - r = 0; - } else { - r = -1; - } - return r; -} - -/********************************************************************* -* -* SEGGER_RTT_SetNameDownBuffer -* -* Function description -* Run-time configuration of a specific Down-buffer name (T->H). -* Buffer to be configured is specified by index. -* -* Parameters -* BufferIndex Index of the buffer to renamed. -* sName Pointer to a constant name string. -* -* Return value -* >= 0 O.K. -* < 0 Error -*/ -int SEGGER_RTT_SetNameDownBuffer(unsigned BufferIndex, const char* sName) { - int r; - volatile SEGGER_RTT_CB* pRTTCB; - volatile SEGGER_RTT_BUFFER_DOWN* pDown; - - INIT(); - pRTTCB = (volatile SEGGER_RTT_CB*)((unsigned char*)&_SEGGER_RTT + SEGGER_RTT_UNCACHED_OFF); // Access RTTCB uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly - if (BufferIndex < SEGGER_RTT_MAX_NUM_DOWN_BUFFERS) { - SEGGER_RTT_LOCK(); - pDown = &pRTTCB->aDown[BufferIndex]; - pDown->sName = sName; - SEGGER_RTT_UNLOCK(); - r = 0; - } else { - r = -1; - } - return r; -} - -/********************************************************************* -* -* SEGGER_RTT_SetFlagsUpBuffer -* -* Function description -* Run-time configuration of specific up-buffer flags (T->H). -* Buffer to be configured is specified by index. -* -* Parameters -* BufferIndex Index of the buffer. -* Flags Flags to set for the buffer. -* Flags[31:24] are used for validity check and must be zero. Flags[23:2] are reserved for future use. Flags[1:0] = RTT operating mode. -* -* Return value -* >= 0 O.K. -* < 0 Error -*/ -int SEGGER_RTT_SetFlagsUpBuffer(unsigned BufferIndex, unsigned Flags) { - int r; - volatile SEGGER_RTT_CB* pRTTCB; - volatile SEGGER_RTT_BUFFER_UP* pUp; - - INIT(); - pRTTCB = (volatile SEGGER_RTT_CB*)((unsigned char*)&_SEGGER_RTT + SEGGER_RTT_UNCACHED_OFF); // Access RTTCB uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly - if (BufferIndex < SEGGER_RTT_MAX_NUM_UP_BUFFERS) { - SEGGER_RTT_LOCK(); - pUp = &pRTTCB->aUp[BufferIndex]; - pUp->Flags = Flags; - SEGGER_RTT_UNLOCK(); - r = 0; - } else { - r = -1; - } - return r; -} - -/********************************************************************* -* -* SEGGER_RTT_SetFlagsDownBuffer -* -* Function description -* Run-time configuration of specific Down-buffer flags (T->H). -* Buffer to be configured is specified by index. -* -* Parameters -* BufferIndex Index of the buffer to renamed. -* Flags Flags to set for the buffer. -* Flags[31:24] are used for validity check and must be zero. Flags[23:2] are reserved for future use. Flags[1:0] = RTT operating mode. -* -* Return value -* >= 0 O.K. -* < 0 Error -*/ -int SEGGER_RTT_SetFlagsDownBuffer(unsigned BufferIndex, unsigned Flags) { - int r; - volatile SEGGER_RTT_CB* pRTTCB; - volatile SEGGER_RTT_BUFFER_DOWN* pDown; - - INIT(); - pRTTCB = (volatile SEGGER_RTT_CB*)((unsigned char*)&_SEGGER_RTT + SEGGER_RTT_UNCACHED_OFF); // Access RTTCB uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly - if (BufferIndex < SEGGER_RTT_MAX_NUM_DOWN_BUFFERS) { - SEGGER_RTT_LOCK(); - pDown = &pRTTCB->aDown[BufferIndex]; - pDown->Flags = Flags; - SEGGER_RTT_UNLOCK(); - r = 0; - } else { - r = -1; - } - return r; -} - -/********************************************************************* -* -* SEGGER_RTT_Init -* -* Function description -* Initializes the RTT Control Block. -* Should be used in RAM targets, at start of the application. -* -*/ -void SEGGER_RTT_Init (void) { - _DoInit(); -} - -/********************************************************************* -* -* SEGGER_RTT_SetTerminal -* -* Function description -* Sets the terminal to be used for output on channel 0. -* -* Parameters -* TerminalId Index of the terminal. -* -* Return value -* >= 0 O.K. -* < 0 Error (e.g. if RTT is configured for non-blocking mode and there was no space in the buffer to set the new terminal Id) -* -* Notes -* (1) Buffer 0 is always reserved for terminal I/O, so we can use index 0 here, fixed -*/ -int SEGGER_RTT_SetTerminal (unsigned char TerminalId) { - unsigned char ac[2]; - SEGGER_RTT_BUFFER_UP* pRing; - unsigned Avail; - int r; - - INIT(); - r = 0; - ac[0] = 0xFFu; - if (TerminalId < sizeof(_aTerminalId)) { // We only support a certain number of channels - ac[1] = _aTerminalId[TerminalId]; - pRing = (SEGGER_RTT_BUFFER_UP*)((char*)&_SEGGER_RTT.aUp[0] + SEGGER_RTT_UNCACHED_OFF); // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly - SEGGER_RTT_LOCK(); // Lock to make sure that no other task is writing into buffer, while we are and number of free bytes in buffer does not change downwards after checking and before writing - if ((pRing->Flags & SEGGER_RTT_MODE_MASK) == SEGGER_RTT_MODE_BLOCK_IF_FIFO_FULL) { - _ActiveTerminal = TerminalId; - _WriteBlocking(pRing, (const char*)ac, 2u); - } else { // Skipping mode or trim mode? => We cannot trim this command so handling is the same for both modes - Avail = _GetAvailWriteSpace(pRing); - if (Avail >= 2) { - _ActiveTerminal = TerminalId; // Only change active terminal in case of success - _WriteNoCheck(pRing, (const char*)ac, 2u); - } else { - r = -1; - } - } - SEGGER_RTT_UNLOCK(); - } else { - r = -1; - } - return r; -} - -/********************************************************************* -* -* SEGGER_RTT_TerminalOut -* -* Function description -* Writes a string to the given terminal -* without changing the terminal for channel 0. -* -* Parameters -* TerminalId Index of the terminal. -* s String to be printed on the terminal. -* -* Return value -* >= 0 - Number of bytes written. -* < 0 - Error. -* -*/ -int SEGGER_RTT_TerminalOut (unsigned char TerminalId, const char* s) { - int Status; - unsigned FragLen; - unsigned Avail; - SEGGER_RTT_BUFFER_UP* pRing; - // - INIT(); - // - // Validate terminal ID. - // - if (TerminalId < (char)sizeof(_aTerminalId)) { // We only support a certain number of channels - // - // Get "to-host" ring buffer. - // - pRing = (SEGGER_RTT_BUFFER_UP*)((char*)&_SEGGER_RTT.aUp[0] + SEGGER_RTT_UNCACHED_OFF); // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly - // - // Need to be able to change terminal, write data, change back. - // Compute the fixed and variable sizes. - // - FragLen = STRLEN(s); - // - // How we output depends upon the mode... - // - SEGGER_RTT_LOCK(); - Avail = _GetAvailWriteSpace(pRing); - switch (pRing->Flags & SEGGER_RTT_MODE_MASK) { - case SEGGER_RTT_MODE_NO_BLOCK_SKIP: - // - // If we are in skip mode and there is no space for the whole - // of this output, don't bother switching terminals at all. - // - if (Avail < (FragLen + 4u)) { - Status = 0; - } else { - _PostTerminalSwitch(pRing, TerminalId); - Status = (int)_WriteBlocking(pRing, s, FragLen); - _PostTerminalSwitch(pRing, _ActiveTerminal); - } - break; - case SEGGER_RTT_MODE_NO_BLOCK_TRIM: - // - // If we are in trim mode and there is not enough space for everything, - // trim the output but always include the terminal switch. If no room - // for terminal switch, skip that totally. - // - if (Avail < 4u) { - Status = -1; - } else { - _PostTerminalSwitch(pRing, TerminalId); - Status = (int)_WriteBlocking(pRing, s, (FragLen < (Avail - 4u)) ? FragLen : (Avail - 4u)); - _PostTerminalSwitch(pRing, _ActiveTerminal); - } - break; - case SEGGER_RTT_MODE_BLOCK_IF_FIFO_FULL: - // - // If we are in blocking mode, output everything. - // - _PostTerminalSwitch(pRing, TerminalId); - Status = (int)_WriteBlocking(pRing, s, FragLen); - _PostTerminalSwitch(pRing, _ActiveTerminal); - break; - default: - Status = -1; - break; - } - // - // Finish up. - // - SEGGER_RTT_UNLOCK(); - } else { - Status = -1; - } - return Status; -} - -/********************************************************************* -* -* SEGGER_RTT_GetAvailWriteSpace -* -* Function description -* Returns the number of bytes available in the ring buffer. -* -* Parameters -* BufferIndex Index of the up buffer. -* -* Return value -* Number of bytes that are free in the selected up buffer. -*/ -unsigned SEGGER_RTT_GetAvailWriteSpace (unsigned BufferIndex) { - SEGGER_RTT_BUFFER_UP* pRing; - - pRing = (SEGGER_RTT_BUFFER_UP*)((char*)&_SEGGER_RTT.aUp[BufferIndex] + SEGGER_RTT_UNCACHED_OFF); // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly - return _GetAvailWriteSpace(pRing); -} - - -/********************************************************************* -* -* SEGGER_RTT_GetBytesInBuffer() -* -* Function description -* Returns the number of bytes currently used in the up buffer. -* -* Parameters -* BufferIndex Index of the up buffer. -* -* Return value -* Number of bytes that are used in the buffer. -*/ -unsigned SEGGER_RTT_GetBytesInBuffer(unsigned BufferIndex) { - unsigned RdOff; - unsigned WrOff; - unsigned r; - volatile SEGGER_RTT_CB* pRTTCB; - // - // Avoid warnings regarding volatile access order. It's not a problem - // in this case, but dampen compiler enthusiasm. - // - pRTTCB = (volatile SEGGER_RTT_CB*)((unsigned char*)&_SEGGER_RTT + SEGGER_RTT_UNCACHED_OFF); // Access RTTCB uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly - RdOff = pRTTCB->aUp[BufferIndex].RdOff; - WrOff = pRTTCB->aUp[BufferIndex].WrOff; - if (RdOff <= WrOff) { - r = WrOff - RdOff; - } else { - r = pRTTCB->aUp[BufferIndex].SizeOfBuffer - (WrOff - RdOff); - } - return r; -} - -/*************************** End of file ****************************/ diff --git a/lib/main/pico-sdk/rp2_common/pico_stdio_rtt/SEGGER/RTT/SEGGER_RTT.h b/lib/main/pico-sdk/rp2_common/pico_stdio_rtt/SEGGER/RTT/SEGGER_RTT.h deleted file mode 100644 index 3ae3ab9130..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_stdio_rtt/SEGGER/RTT/SEGGER_RTT.h +++ /dev/null @@ -1,493 +0,0 @@ -/********************************************************************* -* SEGGER Microcontroller GmbH * -* The Embedded Experts * -********************************************************************** -* * -* (c) 1995 - 2021 SEGGER Microcontroller GmbH * -* * -* www.segger.com Support: support@segger.com * -* * -********************************************************************** -* * -* SEGGER RTT * Real Time Transfer for embedded targets * -* * -********************************************************************** -* * -* All rights reserved. * -* * -* SEGGER strongly recommends to not make any changes * -* to or modify the source code of this software in order to stay * -* compatible with the RTT protocol and J-Link. * -* * -* Redistribution and use in source and binary forms, with or * -* without modification, are permitted provided that the following * -* condition is met: * -* * -* o Redistributions of source code must retain the above copyright * -* notice, this condition and the following disclaimer. * -* * -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * -* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * -* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * -* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * -* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR * -* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT * -* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * -* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * -* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * -* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * -* DAMAGE. * -* * -********************************************************************** -* * -* RTT version: 7.88c * -* * -********************************************************************** - ----------------------------END-OF-HEADER------------------------------ -File : SEGGER_RTT.h -Purpose : Implementation of SEGGER real-time transfer which allows - real-time communication on targets which support debugger - memory accesses while the CPU is running. -Revision: $Rev: 25842 $ ----------------------------------------------------------------------- -*/ - -#ifndef SEGGER_RTT_H -#define SEGGER_RTT_H - -#include "../Config/SEGGER_RTT_Conf.h" - -/********************************************************************* -* -* Defines, defaults -* -********************************************************************** -*/ - -#ifndef RTT_USE_ASM - // - // Some cores support out-of-order memory accesses (reordering of memory accesses in the core) - // For such cores, we need to define a memory barrier to guarantee the order of certain accesses to the RTT ring buffers. - // Needed for: - // Cortex-M7 (ARMv7-M) - // Cortex-M23 (ARM-v8M) - // Cortex-M33 (ARM-v8M) - // Cortex-A/R (ARM-v7A/R) - // - // We do not explicitly check for "Embedded Studio" as the compiler in use determines what we support. - // You can use an external toolchain like IAR inside ES. So there is no point in checking for "Embedded Studio" - // - #if (defined __CROSSWORKS_ARM) // Rowley Crossworks - #define _CC_HAS_RTT_ASM_SUPPORT 1 - #if (defined __ARM_ARCH_7M__) // Cortex-M3 - #define _CORE_HAS_RTT_ASM_SUPPORT 1 - #elif (defined __ARM_ARCH_7EM__) // Cortex-M4/M7 - #define _CORE_HAS_RTT_ASM_SUPPORT 1 - #define _CORE_NEEDS_DMB 1 - #define RTT__DMB() __asm volatile ("dmb\n" : : :); - #elif (defined __ARM_ARCH_8M_BASE__) // Cortex-M23 - #define _CORE_HAS_RTT_ASM_SUPPORT 0 - #define _CORE_NEEDS_DMB 1 - #define RTT__DMB() __asm volatile ("dmb\n" : : :); - #elif (defined __ARM_ARCH_8M_MAIN__) // Cortex-M33 - #define _CORE_HAS_RTT_ASM_SUPPORT 1 - #define _CORE_NEEDS_DMB 1 - #define RTT__DMB() __asm volatile ("dmb\n" : : :); - #else - #define _CORE_HAS_RTT_ASM_SUPPORT 0 - #endif - #elif (defined __ARMCC_VERSION) - // - // ARM compiler - // ARM compiler V6.0 and later is clang based. - // Our ASM part is compatible to clang. - // - #if (__ARMCC_VERSION >= 6000000) - #define _CC_HAS_RTT_ASM_SUPPORT 1 - #else - #define _CC_HAS_RTT_ASM_SUPPORT 0 - #endif - #if (defined __ARM_ARCH_6M__) // Cortex-M0 / M1 - #define _CORE_HAS_RTT_ASM_SUPPORT 0 // No ASM support for this architecture - #elif (defined __ARM_ARCH_7M__) // Cortex-M3 - #define _CORE_HAS_RTT_ASM_SUPPORT 1 - #elif (defined __ARM_ARCH_7EM__) // Cortex-M4/M7 - #define _CORE_HAS_RTT_ASM_SUPPORT 1 - #define _CORE_NEEDS_DMB 1 - #define RTT__DMB() __asm volatile ("dmb\n" : : :); - #elif (defined __ARM_ARCH_8M_BASE__) // Cortex-M23 - #define _CORE_HAS_RTT_ASM_SUPPORT 0 - #define _CORE_NEEDS_DMB 1 - #define RTT__DMB() __asm volatile ("dmb\n" : : :); - #elif (defined __ARM_ARCH_8M_MAIN__) // Cortex-M33 - #define _CORE_HAS_RTT_ASM_SUPPORT 1 - #define _CORE_NEEDS_DMB 1 - #define RTT__DMB() __asm volatile ("dmb\n" : : :); - #elif ((defined __ARM_ARCH_7A__) || (defined __ARM_ARCH_7R__)) // Cortex-A/R 32-bit ARMv7-A/R - #define _CORE_NEEDS_DMB 1 - #define RTT__DMB() __asm volatile ("dmb\n" : : :); - #else - #define _CORE_HAS_RTT_ASM_SUPPORT 0 - #endif - #elif ((defined __GNUC__) || (defined __clang__)) - // - // GCC / Clang - // - #define _CC_HAS_RTT_ASM_SUPPORT 1 - // ARM 7/9: __ARM_ARCH_5__ / __ARM_ARCH_5E__ / __ARM_ARCH_5T__ / __ARM_ARCH_5T__ / __ARM_ARCH_5TE__ - #if (defined __ARM_ARCH_7M__) // Cortex-M3 - #define _CORE_HAS_RTT_ASM_SUPPORT 1 - #elif (defined __ARM_ARCH_7EM__) // Cortex-M4/M7 - #define _CORE_HAS_RTT_ASM_SUPPORT 1 - #define _CORE_NEEDS_DMB 1 // Only Cortex-M7 needs a DMB but we cannot distinguish M4 and M7 here... - #define RTT__DMB() __asm volatile ("dmb\n" : : :); - #elif (defined __ARM_ARCH_8M_BASE__) // Cortex-M23 - #define _CORE_HAS_RTT_ASM_SUPPORT 0 - #define _CORE_NEEDS_DMB 1 - #define RTT__DMB() __asm volatile ("dmb\n" : : :); - #elif (defined __ARM_ARCH_8M_MAIN__) // Cortex-M33 - #define _CORE_HAS_RTT_ASM_SUPPORT 1 - #define _CORE_NEEDS_DMB 1 - #define RTT__DMB() __asm volatile ("dmb\n" : : :); - #elif ((defined __ARM_ARCH_7A__) || (defined __ARM_ARCH_7R__)) // Cortex-A/R 32-bit ARMv7-A/R - #define _CORE_NEEDS_DMB 1 - #define RTT__DMB() __asm volatile ("dmb\n" : : :); - #else - #define _CORE_HAS_RTT_ASM_SUPPORT 0 - #endif - #elif ((defined __IASMARM__) || (defined __ICCARM__)) - // - // IAR assembler/compiler - // - #define _CC_HAS_RTT_ASM_SUPPORT 1 - #if (__VER__ < 6300000) - #define VOLATILE - #else - #define VOLATILE volatile - #endif - #if (defined __ARM7M__) // Needed for old versions that do not know the define yet - #if (__CORE__ == __ARM7M__) // Cortex-M3 - #define _CORE_HAS_RTT_ASM_SUPPORT 1 - #endif - #endif - #if (defined __ARM7EM__) - #if (__CORE__ == __ARM7EM__) // Cortex-M4/M7 - #define _CORE_HAS_RTT_ASM_SUPPORT 1 - #define _CORE_NEEDS_DMB 1 - #define RTT__DMB() asm VOLATILE ("DMB"); - #endif - #endif - #if (defined __ARM8M_BASELINE__) - #if (__CORE__ == __ARM8M_BASELINE__) // Cortex-M23 - #define _CORE_HAS_RTT_ASM_SUPPORT 0 - #define _CORE_NEEDS_DMB 1 - #define RTT__DMB() asm VOLATILE ("DMB"); - #endif - #endif - #if (defined __ARM8M_MAINLINE__) - #if (__CORE__ == __ARM8M_MAINLINE__) // Cortex-M33 - #define _CORE_HAS_RTT_ASM_SUPPORT 1 - #define _CORE_NEEDS_DMB 1 - #define RTT__DMB() asm VOLATILE ("DMB"); - #endif - #endif - #if (defined __ARM8EM_MAINLINE__) - #if (__CORE__ == __ARM8EM_MAINLINE__) // Cortex-??? - #define _CORE_HAS_RTT_ASM_SUPPORT 1 - #define _CORE_NEEDS_DMB 1 - #define RTT__DMB() asm VOLATILE ("DMB"); - #endif - #endif - #if (defined __ARM7A__) - #if (__CORE__ == __ARM7A__) // Cortex-A 32-bit ARMv7-A - #define _CORE_NEEDS_DMB 1 - #define RTT__DMB() asm VOLATILE ("DMB"); - #endif - #endif - #if (defined __ARM7R__) - #if (__CORE__ == __ARM7R__) // Cortex-R 32-bit ARMv7-R - #define _CORE_NEEDS_DMB 1 - #define RTT__DMB() asm VOLATILE ("DMB"); - #endif - #endif -// TBD: __ARM8A__ => Cortex-A 64-bit ARMv8-A -// TBD: __ARM8R__ => Cortex-R 64-bit ARMv8-R - #else - // - // Other compilers - // - #define _CC_HAS_RTT_ASM_SUPPORT 0 - #define _CORE_HAS_RTT_ASM_SUPPORT 0 - #endif - // - // If IDE and core support the ASM version, enable ASM version by default - // - #ifndef _CORE_HAS_RTT_ASM_SUPPORT - #define _CORE_HAS_RTT_ASM_SUPPORT 0 // Default for unknown cores - #endif - #if (_CC_HAS_RTT_ASM_SUPPORT && _CORE_HAS_RTT_ASM_SUPPORT) - #define RTT_USE_ASM (1) - #else - #define RTT_USE_ASM (0) - #endif -#endif - -#ifndef _CORE_NEEDS_DMB - #define _CORE_NEEDS_DMB 0 -#endif - -#ifndef RTT__DMB - #if _CORE_NEEDS_DMB - #error "Don't know how to place inline assembly for DMB" - #else - #define RTT__DMB() - #endif -#endif - -#ifndef SEGGER_RTT_CPU_CACHE_LINE_SIZE - #define SEGGER_RTT_CPU_CACHE_LINE_SIZE (0) // On most target systems where RTT is used, we do not have a CPU cache, therefore 0 is a good default here -#endif - -#ifndef SEGGER_RTT_UNCACHED_OFF - #if SEGGER_RTT_CPU_CACHE_LINE_SIZE - #error "SEGGER_RTT_UNCACHED_OFF must be defined when setting SEGGER_RTT_CPU_CACHE_LINE_SIZE != 0" - #else - #define SEGGER_RTT_UNCACHED_OFF (0) - #endif -#endif -#if RTT_USE_ASM - #if SEGGER_RTT_CPU_CACHE_LINE_SIZE - #error "RTT_USE_ASM is not available if SEGGER_RTT_CPU_CACHE_LINE_SIZE != 0" - #endif -#endif - -#ifndef SEGGER_RTT_ASM // defined when SEGGER_RTT.h is included from assembly file -#include -#include - -/********************************************************************* -* -* Defines, fixed -* -********************************************************************** -*/ - -// -// Determine how much we must pad the control block to make it a multiple of a cache line in size -// Assuming: U8 = 1B -// U16 = 2B -// U32 = 4B -// U8/U16/U32* = 4B -// -#if SEGGER_RTT_CPU_CACHE_LINE_SIZE // Avoid division by zero in case we do not have any cache - #define SEGGER_RTT__ROUND_UP_2_CACHE_LINE_SIZE(NumBytes) (((NumBytes + SEGGER_RTT_CPU_CACHE_LINE_SIZE - 1) / SEGGER_RTT_CPU_CACHE_LINE_SIZE) * SEGGER_RTT_CPU_CACHE_LINE_SIZE) -#else - #define SEGGER_RTT__ROUND_UP_2_CACHE_LINE_SIZE(NumBytes) (NumBytes) -#endif -#define SEGGER_RTT__CB_SIZE (16 + 4 + 4 + (SEGGER_RTT_MAX_NUM_UP_BUFFERS * 24) + (SEGGER_RTT_MAX_NUM_DOWN_BUFFERS * 24)) -#define SEGGER_RTT__CB_PADDING (SEGGER_RTT__ROUND_UP_2_CACHE_LINE_SIZE(SEGGER_RTT__CB_SIZE) - SEGGER_RTT__CB_SIZE) - -/********************************************************************* -* -* Types -* -********************************************************************** -*/ - -// -// Description for a circular buffer (also called "ring buffer") -// which is used as up-buffer (T->H) -// -typedef struct { - const char* sName; // Optional name. Standard names so far are: "Terminal", "SysView", "J-Scope_t4i4" - char* pBuffer; // Pointer to start of buffer - unsigned SizeOfBuffer; // Buffer size in bytes. Note that one byte is lost, as this implementation does not fill up the buffer in order to avoid the problem of being unable to distinguish between full and empty. - unsigned WrOff; // Position of next item to be written by either target. - volatile unsigned RdOff; // Position of next item to be read by host. Must be volatile since it may be modified by host. - unsigned Flags; // Contains configuration flags. Flags[31:24] are used for validity check and must be zero. Flags[23:2] are reserved for future use. Flags[1:0] = RTT operating mode. -} SEGGER_RTT_BUFFER_UP; - -// -// Description for a circular buffer (also called "ring buffer") -// which is used as down-buffer (H->T) -// -typedef struct { - const char* sName; // Optional name. Standard names so far are: "Terminal", "SysView", "J-Scope_t4i4" - char* pBuffer; // Pointer to start of buffer - unsigned SizeOfBuffer; // Buffer size in bytes. Note that one byte is lost, as this implementation does not fill up the buffer in order to avoid the problem of being unable to distinguish between full and empty. - volatile unsigned WrOff; // Position of next item to be written by host. Must be volatile since it may be modified by host. - unsigned RdOff; // Position of next item to be read by target (down-buffer). - unsigned Flags; // Contains configuration flags. Flags[31:24] are used for validity check and must be zero. Flags[23:2] are reserved for future use. Flags[1:0] = RTT operating mode. -} SEGGER_RTT_BUFFER_DOWN; - -// -// RTT control block which describes the number of buffers available -// as well as the configuration for each buffer -// -// -typedef struct { - char acID[16]; // Initialized to "SEGGER RTT" - int MaxNumUpBuffers; // Initialized to SEGGER_RTT_MAX_NUM_UP_BUFFERS (type. 2) - int MaxNumDownBuffers; // Initialized to SEGGER_RTT_MAX_NUM_DOWN_BUFFERS (type. 2) - SEGGER_RTT_BUFFER_UP aUp[SEGGER_RTT_MAX_NUM_UP_BUFFERS]; // Up buffers, transferring information up from target via debug probe to host - SEGGER_RTT_BUFFER_DOWN aDown[SEGGER_RTT_MAX_NUM_DOWN_BUFFERS]; // Down buffers, transferring information down from host via debug probe to target -#if SEGGER_RTT__CB_PADDING - unsigned char aDummy[SEGGER_RTT__CB_PADDING]; -#endif -} SEGGER_RTT_CB; - -/********************************************************************* -* -* Global data -* -********************************************************************** -*/ -extern SEGGER_RTT_CB _SEGGER_RTT; - -/********************************************************************* -* -* RTT API functions -* -********************************************************************** -*/ -#ifdef __cplusplus - extern "C" { -#endif -int SEGGER_RTT_AllocDownBuffer (const char* sName, void* pBuffer, unsigned BufferSize, unsigned Flags); -int SEGGER_RTT_AllocUpBuffer (const char* sName, void* pBuffer, unsigned BufferSize, unsigned Flags); -int SEGGER_RTT_ConfigUpBuffer (unsigned BufferIndex, const char* sName, void* pBuffer, unsigned BufferSize, unsigned Flags); -int SEGGER_RTT_ConfigDownBuffer (unsigned BufferIndex, const char* sName, void* pBuffer, unsigned BufferSize, unsigned Flags); -int SEGGER_RTT_GetKey (void); -unsigned SEGGER_RTT_HasData (unsigned BufferIndex); -int SEGGER_RTT_HasKey (void); -unsigned SEGGER_RTT_HasDataUp (unsigned BufferIndex); -void SEGGER_RTT_Init (void); -unsigned SEGGER_RTT_Read (unsigned BufferIndex, void* pBuffer, unsigned BufferSize); -unsigned SEGGER_RTT_ReadNoLock (unsigned BufferIndex, void* pData, unsigned BufferSize); -int SEGGER_RTT_SetNameDownBuffer (unsigned BufferIndex, const char* sName); -int SEGGER_RTT_SetNameUpBuffer (unsigned BufferIndex, const char* sName); -int SEGGER_RTT_SetFlagsDownBuffer (unsigned BufferIndex, unsigned Flags); -int SEGGER_RTT_SetFlagsUpBuffer (unsigned BufferIndex, unsigned Flags); -int SEGGER_RTT_WaitKey (void); -unsigned SEGGER_RTT_Write (unsigned BufferIndex, const void* pBuffer, unsigned NumBytes); -unsigned SEGGER_RTT_WriteNoLock (unsigned BufferIndex, const void* pBuffer, unsigned NumBytes); -unsigned SEGGER_RTT_WriteSkipNoLock (unsigned BufferIndex, const void* pBuffer, unsigned NumBytes); -unsigned SEGGER_RTT_ASM_WriteSkipNoLock (unsigned BufferIndex, const void* pBuffer, unsigned NumBytes); -unsigned SEGGER_RTT_WriteString (unsigned BufferIndex, const char* s); -void SEGGER_RTT_WriteWithOverwriteNoLock(unsigned BufferIndex, const void* pBuffer, unsigned NumBytes); -unsigned SEGGER_RTT_PutChar (unsigned BufferIndex, char c); -unsigned SEGGER_RTT_PutCharSkip (unsigned BufferIndex, char c); -unsigned SEGGER_RTT_PutCharSkipNoLock (unsigned BufferIndex, char c); -unsigned SEGGER_RTT_GetAvailWriteSpace (unsigned BufferIndex); -unsigned SEGGER_RTT_GetBytesInBuffer (unsigned BufferIndex); -// -// Function macro for performance optimization -// -#define SEGGER_RTT_HASDATA(n) (((SEGGER_RTT_BUFFER_DOWN*)((char*)&_SEGGER_RTT.aDown[n] + SEGGER_RTT_UNCACHED_OFF))->WrOff - ((SEGGER_RTT_BUFFER_DOWN*)((char*)&_SEGGER_RTT.aDown[n] + SEGGER_RTT_UNCACHED_OFF))->RdOff) - -#if RTT_USE_ASM - #define SEGGER_RTT_WriteSkipNoLock SEGGER_RTT_ASM_WriteSkipNoLock -#endif - -/********************************************************************* -* -* RTT transfer functions to send RTT data via other channels. -* -********************************************************************** -*/ -unsigned SEGGER_RTT_ReadUpBuffer (unsigned BufferIndex, void* pBuffer, unsigned BufferSize); -unsigned SEGGER_RTT_ReadUpBufferNoLock (unsigned BufferIndex, void* pData, unsigned BufferSize); -unsigned SEGGER_RTT_WriteDownBuffer (unsigned BufferIndex, const void* pBuffer, unsigned NumBytes); -unsigned SEGGER_RTT_WriteDownBufferNoLock (unsigned BufferIndex, const void* pBuffer, unsigned NumBytes); - -#define SEGGER_RTT_HASDATA_UP(n) (((SEGGER_RTT_BUFFER_UP*)((char*)&_SEGGER_RTT.aUp[n] + SEGGER_RTT_UNCACHED_OFF))->WrOff - ((SEGGER_RTT_BUFFER_UP*)((char*)&_SEGGER_RTT.aUp[n] + SEGGER_RTT_UNCACHED_OFF))->RdOff) // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly - -/********************************************************************* -* -* RTT "Terminal" API functions -* -********************************************************************** -*/ -int SEGGER_RTT_SetTerminal (unsigned char TerminalId); -int SEGGER_RTT_TerminalOut (unsigned char TerminalId, const char* s); - -/********************************************************************* -* -* RTT printf functions (require SEGGER_RTT_printf.c) -* -********************************************************************** -*/ -int SEGGER_RTT_printf(unsigned BufferIndex, const char * sFormat, ...); -int SEGGER_RTT_vprintf(unsigned BufferIndex, const char * sFormat, va_list * pParamList); - -#ifdef __cplusplus - } -#endif - -#endif // ifndef(SEGGER_RTT_ASM) - -/********************************************************************* -* -* Defines -* -********************************************************************** -*/ - -// -// Operating modes. Define behavior if buffer is full (not enough space for entire message) -// -#define SEGGER_RTT_MODE_NO_BLOCK_SKIP (0) // Skip. Do not block, output nothing. (Default) -#define SEGGER_RTT_MODE_NO_BLOCK_TRIM (1) // Trim: Do not block, output as much as fits. -#define SEGGER_RTT_MODE_BLOCK_IF_FIFO_FULL (2) // Block: Wait until there is space in the buffer. -#define SEGGER_RTT_MODE_MASK (3) - -// -// Control sequences, based on ANSI. -// Can be used to control color, and clear the screen -// -#define RTT_CTRL_RESET "\x1B[0m" // Reset to default colors -#define RTT_CTRL_CLEAR "\x1B[2J" // Clear screen, reposition cursor to top left - -#define RTT_CTRL_TEXT_BLACK "\x1B[2;30m" -#define RTT_CTRL_TEXT_RED "\x1B[2;31m" -#define RTT_CTRL_TEXT_GREEN "\x1B[2;32m" -#define RTT_CTRL_TEXT_YELLOW "\x1B[2;33m" -#define RTT_CTRL_TEXT_BLUE "\x1B[2;34m" -#define RTT_CTRL_TEXT_MAGENTA "\x1B[2;35m" -#define RTT_CTRL_TEXT_CYAN "\x1B[2;36m" -#define RTT_CTRL_TEXT_WHITE "\x1B[2;37m" - -#define RTT_CTRL_TEXT_BRIGHT_BLACK "\x1B[1;30m" -#define RTT_CTRL_TEXT_BRIGHT_RED "\x1B[1;31m" -#define RTT_CTRL_TEXT_BRIGHT_GREEN "\x1B[1;32m" -#define RTT_CTRL_TEXT_BRIGHT_YELLOW "\x1B[1;33m" -#define RTT_CTRL_TEXT_BRIGHT_BLUE "\x1B[1;34m" -#define RTT_CTRL_TEXT_BRIGHT_MAGENTA "\x1B[1;35m" -#define RTT_CTRL_TEXT_BRIGHT_CYAN "\x1B[1;36m" -#define RTT_CTRL_TEXT_BRIGHT_WHITE "\x1B[1;37m" - -#define RTT_CTRL_BG_BLACK "\x1B[24;40m" -#define RTT_CTRL_BG_RED "\x1B[24;41m" -#define RTT_CTRL_BG_GREEN "\x1B[24;42m" -#define RTT_CTRL_BG_YELLOW "\x1B[24;43m" -#define RTT_CTRL_BG_BLUE "\x1B[24;44m" -#define RTT_CTRL_BG_MAGENTA "\x1B[24;45m" -#define RTT_CTRL_BG_CYAN "\x1B[24;46m" -#define RTT_CTRL_BG_WHITE "\x1B[24;47m" - -#define RTT_CTRL_BG_BRIGHT_BLACK "\x1B[4;40m" -#define RTT_CTRL_BG_BRIGHT_RED "\x1B[4;41m" -#define RTT_CTRL_BG_BRIGHT_GREEN "\x1B[4;42m" -#define RTT_CTRL_BG_BRIGHT_YELLOW "\x1B[4;43m" -#define RTT_CTRL_BG_BRIGHT_BLUE "\x1B[4;44m" -#define RTT_CTRL_BG_BRIGHT_MAGENTA "\x1B[4;45m" -#define RTT_CTRL_BG_BRIGHT_CYAN "\x1B[4;46m" -#define RTT_CTRL_BG_BRIGHT_WHITE "\x1B[4;47m" - - -#endif - -/*************************** End of file ****************************/ diff --git a/lib/main/pico-sdk/rp2_common/pico_stdio_rtt/include/pico/stdio_rtt.h b/lib/main/pico-sdk/rp2_common/pico_stdio_rtt/include/pico/stdio_rtt.h deleted file mode 100644 index 2ed08e25ae..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_stdio_rtt/include/pico/stdio_rtt.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _PICO_STDIO_RTT_H -#define _PICO_STDIO_RTT_H - -#include "pico/stdio.h" - -/** \brief Support for stdin/stdout using SEGGER RTT - * \defgroup pico_stdio_rtt pico_stdio_rtt - * \ingroup pico_stdio - * - * Linking this library or calling `pico_enable_stdio_rtt(TARGET)` in the CMake (which - * achieves the same thing) will add RTT to the drivers used for standard output - */ - -// PICO_CONFIG: PICO_STDIO_RTT_DEFAULT_CRLF, Default state of CR/LF translation for rtt output, type=bool, default=PICO_STDIO_DEFAULT_CRLF, group=pico_stdio_rtt -#ifndef PICO_STDIO_RTT_DEFAULT_CRLF -#define PICO_STDIO_RTT_DEFAULT_CRLF PICO_STDIO_DEFAULT_CRLF -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -extern stdio_driver_t stdio_rtt; - -/*! \brief Explicitly initialize stdin/stdout over RTT and add it to the current set of stdin/stdout drivers - * \ingroup pico_stdio_rtt - * - * \note this method is automatically called by \ref stdio_init_all() if `pico_stdio_rtt` is included in the build - */ -void stdio_rtt_init(void); - -/*! \brief Explicitly deinitialize stdin/stdout over RTT and remove it from the current set of stdin/stdout drivers - * \ingroup pico_stdio_rtt - * - * \note this method is automatically called by \ref stdio_deinit_all() if `pico_stdio_rtt` is included in the build - */ -void stdio_rtt_deinit(void); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/lib/main/pico-sdk/rp2_common/pico_stdio_rtt/stdio_rtt.c b/lib/main/pico-sdk/rp2_common/pico_stdio_rtt/stdio_rtt.c deleted file mode 100644 index 2dc75579a6..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_stdio_rtt/stdio_rtt.c +++ /dev/null @@ -1,42 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "pico/binary_info.h" -#include "pico/stdio/driver.h" -#include "pico/stdio_rtt.h" -#include "SEGGER_RTT.h" - -#if PICO_NO_BI_STDIO_RTT -#define stdio_bi_decl_if_func_used(x) -#else -#define stdio_bi_decl_if_func_used bi_decl_if_func_used -#endif - -void stdio_rtt_init(void) { - SEGGER_RTT_Init(); - stdio_set_driver_enabled(&stdio_rtt, true); - stdio_bi_decl_if_func_used(bi_program_feature("RTT stdin / stdout")); -} - -void stdio_rtt_deinit(void) { - stdio_set_driver_enabled(&stdio_rtt, false); -} - -static void stdio_rtt_out_chars(const char *buf, int length) { - SEGGER_RTT_Write(0, buf, length); -} - -static int stdio_rtt_in_chars(char *buf, int length) { - return SEGGER_RTT_Read(0, buf, length); -} - -stdio_driver_t stdio_rtt = { - .out_chars = stdio_rtt_out_chars, - .in_chars = stdio_rtt_in_chars, -#if PICO_STDIO_ENABLE_CRLF_SUPPORT - .crlf_enabled = PICO_STDIO_RTT_DEFAULT_CRLF -#endif -}; diff --git a/lib/main/pico-sdk/rp2_common/pico_stdio_semihosting/include/pico/stdio_semihosting.h b/lib/main/pico-sdk/rp2_common/pico_stdio_semihosting/include/pico/stdio_semihosting.h deleted file mode 100644 index de46997d1e..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_stdio_semihosting/include/pico/stdio_semihosting.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _PICO_STDIO_SEMIHOSTING_H -#define _PICO_STDIO_SEMIHOSTING_H - -#include "pico/stdio.h" - -/** \brief Experimental support for stdout using RAM semihosting - * \defgroup pico_stdio_semihosting pico_stdio_semihosting - * \ingroup pico_stdio - * - * Linking this library or calling `pico_enable_stdio_semihosting(TARGET ENABLED)` in the CMake (which - * achieves the same thing) will add semihosting to the drivers used for standard output - */ - -// PICO_CONFIG: PICO_STDIO_SEMIHOSTING_DEFAULT_CRLF, Default state of CR/LF translation for semihosting output, type=bool, default=PICO_STDIO_DEFAULT_CRLF, group=pico_stdio_semihosting -#ifndef PICO_STDIO_SEMIHOSTING_DEFAULT_CRLF -#define PICO_STDIO_SEMIHOSTING_DEFAULT_CRLF PICO_STDIO_DEFAULT_CRLF -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -extern stdio_driver_t stdio_semihosting; - -/*! \brief Explicitly initialize stdout over semihosting and add it to the current set of stdout targets - * \ingroup pico_stdio_semihosting - * - * \note this method is automatically called by \ref stdio_init_all() if `pico_stdio_semihosting` is included in the build - */ -void stdio_semihosting_init(void); - -/*! \brief Explicitly deinitialize stdout over semihosting and add it to the current set of stdout targets - * \ingroup pico_stdio_semihosting - * - * \note this method is automatically called by \ref stdio_deinit_all() if `pico_stdio_semihosting` is included in the build - */ -void stdio_semihosting_deinit(void); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/lib/main/pico-sdk/rp2_common/pico_stdio_semihosting/stdio_semihosting.c b/lib/main/pico-sdk/rp2_common/pico_stdio_semihosting/stdio_semihosting.c deleted file mode 100644 index 94c43fc8d5..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_stdio_semihosting/stdio_semihosting.c +++ /dev/null @@ -1,77 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "pico/stdio/driver.h" -#include "pico/stdio_semihosting.h" -#include "pico/binary_info.h" - -static void stdio_semihosting_out_chars(const char *buf, int length) { - // must be volatile or the buffer gets put in registers & optimized away - volatile struct { - // https://developer.arm.com/documentation/dui0375/g/What-is-Semihosting-/SYS-WRITE--0x05- - // arguments, in order: - // word 0 = file handle (1 = stdout) - // word 1 = pointer to buffer - // word 2 = length of buffer - size_t fd; - const char *buf; - size_t len; - } args; - - args.fd = 1; // 1 = stdout - args.buf = buf; - args.len = length; - - pico_default_asm ( -#ifdef __riscv - // a0 encodes the semihosting call number, 0x05 = SYS_WRITE - "li a0, 0x05\n" - // a1 points to the arguments - "mv a1, %[args]\n" - // Magic three-instruction sequence, containing a breakpoint. Note the - // RISC-V unpriv spec implies the final instruction might encode the - // call number (passed in a1) but openocd source shows this is just a - // constant value of 0x07. These instructions must be uncompressed: - ".option push\n" - ".option norvc\n" - "slli x0, x0, 0x1f\n" - "ebreak\n" - "srai x0, x0, 0x07\n" - ".option pop\n" - : - : [args] "r" (&args) - : "a0", "a1" -#else - // r1 must contain a pointer to the arguments - "movs r1, %[args]\n" - // semihosting call number 0x05 = SYS_WRITE - "movs r0, #5\n" - // make the semihosting call: https://developer.arm.com/documentation/dui0375/g/What-is-Semihosting-/The-semihosting-interface - "bkpt 0xab\n" - : - : [args] "r" (&args) - : "r0", "r1", "cc", "memory" -#endif - ); -} - -stdio_driver_t stdio_semihosting = { - .out_chars = stdio_semihosting_out_chars, -#if PICO_STDIO_ENABLE_CRLF_SUPPORT - .crlf_enabled = PICO_STDIO_SEMIHOSTING_DEFAULT_CRLF -#endif -}; - -void stdio_semihosting_init(void) { -#if !PICO_NO_BI_STDIO_SEMIHOSTING - bi_decl_if_func_used(bi_program_feature("semihosting stdout")); -#endif - stdio_set_driver_enabled(&stdio_semihosting, true); -} - -void stdio_semihosting_deinit(void) { - stdio_set_driver_enabled(&stdio_semihosting, false); -} diff --git a/lib/main/pico-sdk/rp2_common/pico_stdio_uart/include/pico/stdio_uart.h b/lib/main/pico-sdk/rp2_common/pico_stdio_uart/include/pico/stdio_uart.h deleted file mode 100644 index 504837fbc2..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_stdio_uart/include/pico/stdio_uart.h +++ /dev/null @@ -1,108 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _PICO_STDIO_UART_H -#define _PICO_STDIO_UART_H - -#include "pico/stdio.h" -#include "hardware/uart.h" - -/** \brief Support for stdin/stdout using UART - * \defgroup pico_stdio_uart pico_stdio_uart - * \ingroup pico_stdio - * - * Linking this library or calling `pico_enable_stdio_uart(TARGET ENABLED)` in the CMake (which - * achieves the same thing) will add UART to the drivers used for standard input/output - */ - -// PICO_CONFIG: PICO_STDIO_UART_DEFAULT_CRLF, Default state of CR/LF translation for UART output, type=bool, default=PICO_STDIO_DEFAULT_CRLF, group=pico_stdio_uart -#ifndef PICO_STDIO_UART_DEFAULT_CRLF -#define PICO_STDIO_UART_DEFAULT_CRLF PICO_STDIO_DEFAULT_CRLF -#endif - -// PICO_CONFIG: PICO_STDIO_UART_SUPPORT_CHARS_AVAILABLE_CALLBACK, Enable UART STDIO support for stdio_set_chars_available_callback. Can be disabled to make use of the uart elsewhere, type=bool, default=1, group=pico_stdio_uart -#ifndef PICO_STDIO_UART_SUPPORT_CHARS_AVAILABLE_CALLBACK -#define PICO_STDIO_UART_SUPPORT_CHARS_AVAILABLE_CALLBACK 1 -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -extern stdio_driver_t stdio_uart; - -/*! \brief Explicitly initialize stdin/stdout over UART and add it to the current set of stdin/stdout drivers - * \ingroup pico_stdio_uart - * - * This method sets up PICO_DEFAULT_UART_TX_PIN for UART output (if defined), PICO_DEFAULT_UART_RX_PIN for input (if defined) - * and configures the baud rate as PICO_DEFAULT_UART_BAUD_RATE. - * - * \note this method is automatically called by \ref stdio_init_all() if `pico_stdio_uart` is included in the build - */ -void stdio_uart_init(void); - -/*! \brief Explicitly initialize stdout only (no stdin) over UART and add it to the current set of stdout drivers - * \ingroup pico_stdio_uart - * - * This method sets up PICO_DEFAULT_UART_TX_PIN for UART output (if defined) , and configures the baud rate as PICO_DEFAULT_UART_BAUD_RATE - */ -void stdout_uart_init(void); - -/*! \brief Explicitly initialize stdin only (no stdout) over UART and add it to the current set of stdin drivers - * \ingroup pico_stdio_uart - * - * This method sets up PICO_DEFAULT_UART_RX_PIN for UART input (if defined) , and configures the baud rate as PICO_DEFAULT_UART_BAUD_RATE - */ -void stdin_uart_init(void); - -/*! \brief Perform custom initialization initialize stdin/stdout over UART and add it to the current set of stdin/stdout drivers - * \ingroup pico_stdio_uart - * - * \param uart the uart instance to use, \ref uart0 or \ref uart1 - * \param baud_rate the baud rate in Hz - * \param tx_pin the UART pin to use for stdout (or -1 for no stdout) - * \param rx_pin the UART pin to use for stdin (or -1 for no stdin) - */ -void stdio_uart_init_full(uart_inst_t *uart, uint baud_rate, int tx_pin, int rx_pin); - -/*! \brief Explicitly deinitialize stdin/stdout over UART and remove it from the current set of stdin/stdout drivers - * \ingroup pico_stdio_uart - * - * This method disables PICO_DEFAULT_UART_TX_PIN for UART output (if defined), PICO_DEFAULT_UART_RX_PIN for input (if defined) - * and leaves the pads isolated. - * - * \note this method is automatically called by \ref stdio_deinit_all() if `pico_stdio_uart` is included in the build - */ -void stdio_uart_deinit(void); - -/*! \brief Explicitly deinitialize stdout only (no stdin) over UART and remove it from the current set of stdout drivers - * \ingroup pico_stdio_uart - * - * This method disables PICO_DEFAULT_UART_TX_PIN for UART output (if defined), and leaves the pad isolated - */ -void stdout_uart_deinit(void); - -/*! \brief Explicitly deinitialize stdin only (no stdout) over UART and remove it from the current set of stdin drivers - * \ingroup pico_stdio_uart - * - * This method disables PICO_DEFAULT_UART_RX_PIN for UART input (if defined), and leaves the pads isolated - */ -void stdin_uart_deinit(void); - -/*! \brief Perform custom deinitialization deinitialize stdin/stdout over UART and remove it from the current set of stdin/stdout drivers - * \ingroup pico_stdio_uart - * - * \param uart the uart instance to use, \ref uart0 or \ref uart1 - * \param tx_pin the UART pin to use for stdout (or -1 for no stdout) - * \param rx_pin the UART pin to use for stdin (or -1 for no stdin) - */ -void stdio_uart_deinit_full(uart_inst_t *uart, int tx_pin, int rx_pin); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/lib/main/pico-sdk/rp2_common/pico_stdio_uart/stdio_uart.c b/lib/main/pico-sdk/rp2_common/pico_stdio_uart/stdio_uart.c deleted file mode 100644 index 620e25d15b..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_stdio_uart/stdio_uart.c +++ /dev/null @@ -1,202 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "pico/stdio/driver.h" -#include "pico/stdio_uart.h" -#include "pico/binary_info.h" -#include "hardware/gpio.h" - -static uart_inst_t *uart_instance; - -#if PICO_STDIO_UART_SUPPORT_CHARS_AVAILABLE_CALLBACK -static void (*chars_available_callback)(void*); -static void *chars_available_param; -#endif - -#if PICO_NO_BI_STDIO_UART -#define stdio_bi_decl_if_func_used(x) -#else -#define stdio_bi_decl_if_func_used bi_decl_if_func_used -#endif - -#ifdef PICO_DEFAULT_UART_TX_PIN -#if (PICO_DEFAULT_UART_TX_PIN & 0x1) || (PICO_RP2040 && (PICO_DEFAULT_UART_TX_PIN & 0x2)) -#error "Specified PICO_DEFAULT_UART_TX_PIN does not support UART TX" -#endif -#endif - -#ifdef PICO_DEFAULT_UART_RX_PIN -#if !(PICO_DEFAULT_UART_RX_PIN & 0x1) || (PICO_RP2040 && (PICO_DEFAULT_UART_TX_PIN & 0x2)) -#error "Specified PICO_DEFAULT_UART_RX_PIN does not support UART RX" -#endif -#endif - -void stdio_uart_init(void) { -#ifdef uart_default - int tx_pin = -1; - int rx_pin = -1; -#ifdef PICO_DEFAULT_UART_TX_PIN - tx_pin = PICO_DEFAULT_UART_TX_PIN; -#ifdef PICO_DEFAULT_UART_RX_PIN - rx_pin = PICO_DEFAULT_UART_RX_PIN; - stdio_bi_decl_if_func_used(bi_program_feature("UART stdin / stdout")); -#if PICO_DEFAULT_UART_TX_PIN == PICO_DEFAULT_UART_RX_PIN - bi_decl_if_func_used(bi_2pins_with_func(PICO_DEFAULT_UART_RX_PIN, PICO_DEFAULT_UART_TX_PIN, uart_get_funcsel(uart_default, PICO_DEFAULT_UART_RX_PIN))); -#else - bi_decl_if_func_used(bi_1pin_with_func(PICO_DEFAULT_UART_TX_PIN, UART_FUNCSEL_NUM(uart_default, PICO_DEFAULT_UART_TX_PIN))); - bi_decl_if_func_used(bi_1pin_with_func(PICO_DEFAULT_UART_RX_PIN, UART_FUNCSEL_NUM(uart_default, PICO_DEFAULT_UART_RX_PIN))); -#endif -#else - stdio_bi_decl_if_func_used(bi_program_feature("UART stdout")); - bi_decl_if_func_used(bi_1pin_with_func(PICO_DEFAULT_UART_TX_PIN, GPIO_FUNC_UART)); -#endif -#elif defined(PICO_DEFAULT_UART_RX_PIN) - rx_pin = PICO_DEFAULT_UART_RX_PIN; - stdio_bi_decl_if_func_used(bi_program_feature("UART stdin")); - bi_decl_if_func_used(bi_1pin_with_func(PICO_DEFAULT_UART_RX_PIN, GPIO_FUNC_UART)); -#endif -#if !defined(PICO_DEFAULT_UART_BAUD_RATE) - panic("UART baud rate undefined"); -#else - stdio_uart_init_full(uart_default, PICO_DEFAULT_UART_BAUD_RATE, tx_pin, rx_pin); -#endif -#endif -} - -void stdout_uart_init(void) { -#if defined(uart_default) && defined(PICO_DEFAULT_UART_TX_PIN) - bi_decl_if_func_used(bi_1pin_with_func(PICO_DEFAULT_UART_TX_PIN, UART_FUNCSEL_NUM(uart_default, PICO_DEFAULT_UART_TX_PIN))); -#if !defined(PICO_DEFAULT_UART_BAUD_RATE) - panic("UART baud rate undefined"); -#else - stdio_bi_decl_if_func_used(bi_program_feature("UART stdout")); - stdio_uart_init_full(uart_default, PICO_DEFAULT_UART_BAUD_RATE, PICO_DEFAULT_UART_TX_PIN, -1); -#endif -#endif -} - -void stdin_uart_init(void) { -#if defined(uart_default) && defined(PICO_DEFAULT_UART_RX_PIN) - bi_decl_if_func_used(bi_1pin_with_func(PICO_DEFAULT_UART_RX_PIN, UART_FUNCSEL_NUM(uart_default, PICO_DEFAULT_UART_RX_PIN))); -#if !defined(PICO_DEFAULT_UART_BAUD_RATE) - panic("UART baud rate undefined"); -#else - stdio_bi_decl_if_func_used(bi_program_feature("UART stdin")); - stdio_uart_init_full(uart_default, PICO_DEFAULT_UART_BAUD_RATE, -1, PICO_DEFAULT_UART_RX_PIN); -#endif -#endif -} - -void stdio_uart_init_full(struct uart_inst *uart, uint baud_rate, int tx_pin, int rx_pin) { - uart_instance = uart; - if (tx_pin >= 0) gpio_set_function((uint)tx_pin, UART_FUNCSEL_NUM(uart, tx_pin)); - if (rx_pin >= 0) gpio_set_function((uint)rx_pin, UART_FUNCSEL_NUM(uart, rx_pin)); - uart_init(uart_instance, baud_rate); - stdio_set_driver_enabled(&stdio_uart, true); -} - -void stdio_uart_deinit(void) { -#ifdef uart_default - int tx_pin = -1; - int rx_pin = -1; -#ifdef PICO_DEFAULT_UART_TX_PIN - tx_pin = PICO_DEFAULT_UART_TX_PIN; -#endif -#ifdef PICO_DEFAULT_UART_RX_PIN - rx_pin = PICO_DEFAULT_UART_RX_PIN; -#endif - stdio_uart_deinit_full(uart_default, tx_pin, rx_pin); -#endif -} - -void stdout_uart_deinit(void) { -#if defined(uart_default) && defined(PICO_DEFAULT_UART_TX_PIN) - stdio_uart_deinit_full(uart_default, PICO_DEFAULT_UART_TX_PIN, -1); -#endif -} - -void stdin_uart_deinit(void) { -#if defined(uart_default) && defined(PICO_DEFAULT_UART_RX_PIN) - stdio_uart_deinit_full(uart_default, -1, PICO_DEFAULT_UART_RX_PIN); -#endif -} - -void stdio_uart_deinit_full(struct uart_inst *uart, int tx_pin, int rx_pin) { - uart_instance = uart; - stdio_set_driver_enabled(&stdio_uart, false); - uart_deinit(uart_instance); -#if PICO_RP2040 - ((void)tx_pin); - ((void)rx_pin); -#else - // Leave pads isolated - if (tx_pin >= 0) hw_set_bits(&pads_bank0_hw->io[tx_pin], PADS_BANK0_GPIO0_ISO_BITS); - if (rx_pin >= 0) hw_set_bits(&pads_bank0_hw->io[rx_pin], PADS_BANK0_GPIO0_ISO_BITS); -#endif -} - -static void stdio_uart_out_chars(const char *buf, int length) { - for (int i = 0; i bRequest == 1 && request->wIndex == 7) { - // Get Microsoft OS 2.0 compatible descriptor - return tud_control_xfer(rhport, request, (void*)(uintptr_t) desc_ms_os_20, sizeof(desc_ms_os_20)); - } else { - return false; - } - - // stall unknown request - return false; -} -#endif - -static void resetd_init(void) { -} - -static void resetd_reset(uint8_t __unused rhport) { - itf_num = 0; -} - -static uint16_t resetd_open(uint8_t __unused rhport, tusb_desc_interface_t const *itf_desc, uint16_t max_len) { - TU_VERIFY(TUSB_CLASS_VENDOR_SPECIFIC == itf_desc->bInterfaceClass && - RESET_INTERFACE_SUBCLASS == itf_desc->bInterfaceSubClass && - RESET_INTERFACE_PROTOCOL == itf_desc->bInterfaceProtocol, 0); - - uint16_t const drv_len = sizeof(tusb_desc_interface_t); - TU_VERIFY(max_len >= drv_len, 0); - - itf_num = itf_desc->bInterfaceNumber; - return drv_len; -} - -// Support for parameterized reset via vendor interface control request -static bool resetd_control_xfer_cb(uint8_t __unused rhport, uint8_t stage, tusb_control_request_t const * request) { - // nothing to do with DATA & ACK stage - if (stage != CONTROL_STAGE_SETUP) return true; - - if (request->wIndex == itf_num) { - -#if PICO_STDIO_USB_RESET_INTERFACE_SUPPORT_RESET_TO_BOOTSEL - if (request->bRequest == RESET_REQUEST_BOOTSEL) { -#ifdef PICO_STDIO_USB_RESET_BOOTSEL_ACTIVITY_LED - uint gpio_mask = 1u << PICO_STDIO_USB_RESET_BOOTSEL_ACTIVITY_LED; -#else - uint gpio_mask = 0u; -#endif -#if !PICO_STDIO_USB_RESET_BOOTSEL_FIXED_ACTIVITY_LED - if (request->wValue & 0x100) { - gpio_mask = 1u << (request->wValue >> 9u); - } -#endif - reset_usb_boot(gpio_mask, (request->wValue & 0x7f) | PICO_STDIO_USB_RESET_BOOTSEL_INTERFACE_DISABLE_MASK); - // does not return, otherwise we'd return true - } -#endif - -#if PICO_STDIO_USB_RESET_INTERFACE_SUPPORT_RESET_TO_FLASH_BOOT - if (request->bRequest == RESET_REQUEST_FLASH) { - watchdog_reboot(0, 0, PICO_STDIO_USB_RESET_RESET_TO_FLASH_DELAY_MS); - return true; - } -#endif - - } - return false; -} - -static bool resetd_xfer_cb(uint8_t __unused rhport, uint8_t __unused ep_addr, xfer_result_t __unused result, uint32_t __unused xferred_bytes) { - return true; -} - -static usbd_class_driver_t const _resetd_driver = -{ -#if CFG_TUSB_DEBUG >= 2 - .name = "RESET", -#endif - .init = resetd_init, - .reset = resetd_reset, - .open = resetd_open, - .control_xfer_cb = resetd_control_xfer_cb, - .xfer_cb = resetd_xfer_cb, - .sof = NULL -}; - -// Implement callback to add our custom driver -usbd_class_driver_t const *usbd_app_driver_get_cb(uint8_t *driver_count) { - *driver_count = 1; - return &_resetd_driver; -} -#endif - -#if PICO_STDIO_USB_ENABLE_RESET_VIA_BAUD_RATE -// Support for default BOOTSEL reset by changing baud rate -void tud_cdc_line_coding_cb(__unused uint8_t itf, cdc_line_coding_t const* p_line_coding) { - if (p_line_coding->bit_rate == PICO_STDIO_USB_RESET_MAGIC_BAUD_RATE) { -#ifdef PICO_STDIO_USB_RESET_BOOTSEL_ACTIVITY_LED - const uint gpio_mask = 1u << PICO_STDIO_USB_RESET_BOOTSEL_ACTIVITY_LED; -#else - const uint gpio_mask = 0u; -#endif - reset_usb_boot(gpio_mask, PICO_STDIO_USB_RESET_BOOTSEL_INTERFACE_DISABLE_MASK); - } -} -#endif - -#endif \ No newline at end of file diff --git a/lib/main/pico-sdk/rp2_common/pico_stdio_usb/stdio_usb.c b/lib/main/pico-sdk/rp2_common/pico_stdio_usb/stdio_usb.c deleted file mode 100644 index 0f9e3188d4..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_stdio_usb/stdio_usb.c +++ /dev/null @@ -1,305 +0,0 @@ -/** - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef LIB_TINYUSB_HOST -#include "tusb.h" -#include "pico/stdio_usb.h" - -// these may not be set if the user is providing tud support (i.e. LIB_TINYUSB_DEVICE is 1 because -// the user linked in tinyusb_device) but they haven't selected CDC -#if (CFG_TUD_ENABLED | TUSB_OPT_DEVICE_ENABLED) && CFG_TUD_CDC - -#include "pico/binary_info.h" -#include "pico/time.h" -#include "pico/stdio/driver.h" -#include "pico/mutex.h" -#include "hardware/irq.h" -#include "device/usbd_pvt.h" // for usbd_defer_func - -static mutex_t stdio_usb_mutex; - -#if PICO_STDIO_USB_SUPPORT_CHARS_AVAILABLE_CALLBACK -static void (*chars_available_callback)(void*); -static void *chars_available_param; -#endif - -// when tinyusb_device is explicitly linked we do no background tud processing -#if !LIB_TINYUSB_DEVICE -// if this crit_sec is initialized, we are not in periodic timer mode, and must make sure -// we don't either create multiple one shot timers, or miss creating one. this crit_sec -// is used to protect the one_shot_timer_pending flag -static critical_section_t one_shot_timer_crit_sec; -static volatile bool one_shot_timer_pending; -#ifdef PICO_STDIO_USB_LOW_PRIORITY_IRQ -static_assert(PICO_STDIO_USB_LOW_PRIORITY_IRQ >= NUM_IRQS - NUM_USER_IRQS, ""); -#define low_priority_irq_num PICO_STDIO_USB_LOW_PRIORITY_IRQ -#else -static uint8_t low_priority_irq_num; -#endif - -static int64_t timer_task(__unused alarm_id_t id, __unused void *user_data) { - int64_t repeat_time; - if (critical_section_is_initialized(&one_shot_timer_crit_sec)) { - critical_section_enter_blocking(&one_shot_timer_crit_sec); - one_shot_timer_pending = false; - critical_section_exit(&one_shot_timer_crit_sec); - repeat_time = 0; // don't repeat - } else { - repeat_time = PICO_STDIO_USB_TASK_INTERVAL_US; - } - if (irq_is_enabled(low_priority_irq_num)) { - irq_set_pending(low_priority_irq_num); - return repeat_time; - } else { - return 0; // don't repeat - } -} - -static void low_priority_worker_irq(void) { - if (mutex_try_enter(&stdio_usb_mutex, NULL)) { - tud_task(); -#if PICO_STDIO_USB_SUPPORT_CHARS_AVAILABLE_CALLBACK - uint32_t chars_avail = tud_cdc_available(); -#endif - mutex_exit(&stdio_usb_mutex); -#if PICO_STDIO_USB_SUPPORT_CHARS_AVAILABLE_CALLBACK - if (chars_avail && chars_available_callback) chars_available_callback(chars_available_param); -#endif - } else { - // if the mutex is already owned, then we are in non IRQ code in this file. - // - // it would seem simplest to just let that code call tud_task() at the end, however this - // code might run during the call to tud_task() and we might miss a necessary tud_task() call - // - // if we are using a periodic timer (crit_sec is not initialized in this case), - // then we are happy just to wait until the next tick, however when we are not using a periodic timer, - // we must kick off a one-shot timer to make sure the tud_task() DOES run (this method - // will be called again as a result, and will try the mutex_try_enter again, and if that fails - // create another one shot timer again, and so on). - if (critical_section_is_initialized(&one_shot_timer_crit_sec)) { - bool need_timer; - critical_section_enter_blocking(&one_shot_timer_crit_sec); - need_timer = !one_shot_timer_pending; - one_shot_timer_pending = true; - critical_section_exit(&one_shot_timer_crit_sec); - if (need_timer) { - add_alarm_in_us(PICO_STDIO_USB_TASK_INTERVAL_US, timer_task, NULL, true); - } - } - } -} - -static void usb_irq(void) { - irq_set_pending(low_priority_irq_num); -} - -#endif - -static void stdio_usb_out_chars(const char *buf, int length) { - static uint64_t last_avail_time; - if (!mutex_try_enter_block_until(&stdio_usb_mutex, make_timeout_time_ms(PICO_STDIO_DEADLOCK_TIMEOUT_MS))) { - return; - } - if (stdio_usb_connected()) { - for (int i = 0; i < length;) { - int n = length - i; - int avail = (int) tud_cdc_write_available(); - if (n > avail) n = avail; - if (n) { - int n2 = (int) tud_cdc_write(buf + i, (uint32_t)n); - tud_task(); - tud_cdc_write_flush(); - i += n2; - last_avail_time = time_us_64(); - } else { - tud_task(); - tud_cdc_write_flush(); - if (!stdio_usb_connected() || - (!tud_cdc_write_available() && time_us_64() > last_avail_time + PICO_STDIO_USB_STDOUT_TIMEOUT_US)) { - break; - } - } - } - } else { - // reset our timeout - last_avail_time = 0; - } - mutex_exit(&stdio_usb_mutex); -} - -static void stdio_usb_out_flush(void) { - if (!mutex_try_enter_block_until(&stdio_usb_mutex, make_timeout_time_ms(PICO_STDIO_DEADLOCK_TIMEOUT_MS))) { - return; - } - do { - tud_task(); - } while (tud_cdc_write_flush()); - mutex_exit(&stdio_usb_mutex); -} - -int stdio_usb_in_chars(char *buf, int length) { - // note we perform this check outside the lock, to try and prevent possible deadlock conditions - // with printf in IRQs (which we will escape through timeouts elsewhere, but that would be less graceful). - // - // these are just checks of state, so we can call them while not holding the lock. - // they may be wrong, but only if we are in the middle of a tud_task call, in which case at worst - // we will mistakenly think we have data available when we do not (we will check again), or - // tud_task will complete running and we will check the right values the next time. - // - int rc = PICO_ERROR_NO_DATA; - if (stdio_usb_connected() && tud_cdc_available()) { - if (!mutex_try_enter_block_until(&stdio_usb_mutex, make_timeout_time_ms(PICO_STDIO_DEADLOCK_TIMEOUT_MS))) { - return PICO_ERROR_NO_DATA; // would deadlock otherwise - } - if (stdio_usb_connected() && tud_cdc_available()) { - int count = (int) tud_cdc_read(buf, (uint32_t) length); - rc = count ? count : PICO_ERROR_NO_DATA; - } else { - // because our mutex use may starve out the background task, run tud_task here (we own the mutex) - tud_task(); - } - mutex_exit(&stdio_usb_mutex); - } - return rc; -} - -#if PICO_STDIO_USB_SUPPORT_CHARS_AVAILABLE_CALLBACK -void stdio_usb_set_chars_available_callback(void (*fn)(void*), void *param) { - chars_available_callback = fn; - chars_available_param = param; -} -#endif - -stdio_driver_t stdio_usb = { - .out_chars = stdio_usb_out_chars, - .out_flush = stdio_usb_out_flush, - .in_chars = stdio_usb_in_chars, -#if PICO_STDIO_USB_SUPPORT_CHARS_AVAILABLE_CALLBACK - .set_chars_available_callback = stdio_usb_set_chars_available_callback, -#endif -#if PICO_STDIO_ENABLE_CRLF_SUPPORT - .crlf_enabled = PICO_STDIO_USB_DEFAULT_CRLF -#endif - -}; - -bool stdio_usb_init(void) { - if (get_core_num() != alarm_pool_core_num(alarm_pool_get_default())) { - // included an assertion here rather than just returning false, as this is likely - // a coding bug, rather than anything else. - assert(false); - return false; - } -#if !PICO_NO_BI_STDIO_USB - bi_decl_if_func_used(bi_program_feature("USB stdin / stdout")); -#endif - -#if !defined(LIB_TINYUSB_DEVICE) - // initialize TinyUSB, as user hasn't explicitly linked it - tusb_init(); -#else - assert(tud_inited()); // we expect the caller to have initialized if they are using TinyUSB -#endif - - if (!mutex_is_initialized(&stdio_usb_mutex)) mutex_init(&stdio_usb_mutex); - bool rc = true; -#if !LIB_TINYUSB_DEVICE -#ifdef PICO_STDIO_USB_LOW_PRIORITY_IRQ - user_irq_claim(PICO_STDIO_USB_LOW_PRIORITY_IRQ); -#else - low_priority_irq_num = (uint8_t) user_irq_claim_unused(true); -#endif - irq_set_exclusive_handler(low_priority_irq_num, low_priority_worker_irq); - irq_set_enabled(low_priority_irq_num, true); - - if (irq_has_shared_handler(USBCTRL_IRQ)) { - critical_section_init_with_lock_num(&one_shot_timer_crit_sec, spin_lock_claim_unused(true)); - // we can use a shared handler to notice when there may be work to do - irq_add_shared_handler(USBCTRL_IRQ, usb_irq, PICO_SHARED_IRQ_HANDLER_LOWEST_ORDER_PRIORITY); - } else { - // we use initialization state of the one_shot_timer_critsec as a flag - memset(&one_shot_timer_crit_sec, 0, sizeof(one_shot_timer_crit_sec)); - rc = add_alarm_in_us(PICO_STDIO_USB_TASK_INTERVAL_US, timer_task, NULL, true) >= 0; - } -#endif - if (rc) { - stdio_set_driver_enabled(&stdio_usb, true); -#if PICO_STDIO_USB_CONNECT_WAIT_TIMEOUT_MS -#if PICO_STDIO_USB_CONNECT_WAIT_TIMEOUT_MS > 0 - absolute_time_t until = make_timeout_time_ms(PICO_STDIO_USB_CONNECT_WAIT_TIMEOUT_MS); -#else - absolute_time_t until = at_the_end_of_time; -#endif - do { - if (stdio_usb_connected()) { -#if PICO_STDIO_USB_POST_CONNECT_WAIT_DELAY_MS != 0 - sleep_ms(PICO_STDIO_USB_POST_CONNECT_WAIT_DELAY_MS); -#endif - break; - } - sleep_ms(10); - } while (!time_reached(until)); -#endif - } - return rc; -} - -bool stdio_usb_deinit(void) { - if (get_core_num() != alarm_pool_core_num(alarm_pool_get_default())) { - // included an assertion here rather than just returning false, as this is likely - // a coding bug, rather than anything else. - assert(false); - return false; - } - - assert(tud_inited()); // we expect the caller to have initialized when calling sdio_usb_init - - bool rc = true; - - stdio_set_driver_enabled(&stdio_usb, false); - -#if PICO_STDIO_USB_DEINIT_DELAY_MS != 0 - sleep_ms(PICO_STDIO_USB_DEINIT_DELAY_MS); -#endif - -#if !LIB_TINYUSB_DEVICE - if (irq_has_shared_handler(USBCTRL_IRQ)) { - spin_lock_unclaim(spin_lock_get_num(one_shot_timer_crit_sec.spin_lock)); - critical_section_deinit(&one_shot_timer_crit_sec); - // we can use a shared handler to notice when there may be work to do - irq_remove_handler(USBCTRL_IRQ, usb_irq); - } else { - // timer is disabled by disabling the irq - } - - irq_set_enabled(low_priority_irq_num, false); - user_irq_unclaim(low_priority_irq_num); -#endif - return rc; -} - -bool stdio_usb_connected(void) { -#if PICO_STDIO_USB_CONNECTION_WITHOUT_DTR - return tud_ready(); -#else - // this actually checks DTR - return tud_cdc_connected(); -#endif -} - -#else -#warning stdio USB was configured along with user use of TinyUSB device mode, but CDC is not enabled -bool stdio_usb_init(void) { - return false; -} -#endif // CFG_TUD_ENABLED && CFG_TUD_CDC -#else -#warning stdio USB was configured, but is being disabled as TinyUSB host is explicitly linked -bool stdio_usb_init(void) { - return false; -} -#endif // !LIB_TINYUSB_HOST - diff --git a/lib/main/pico-sdk/rp2_common/pico_stdio_usb/stdio_usb_descriptors.c b/lib/main/pico-sdk/rp2_common/pico_stdio_usb/stdio_usb_descriptors.c deleted file mode 100644 index 2f6e75877c..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_stdio_usb/stdio_usb_descriptors.c +++ /dev/null @@ -1,188 +0,0 @@ -/* - * This file is based on a file originally part of the - * MicroPython project, http://micropython.org/ - * - * The MIT License (MIT) - * - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * Copyright (c) 2019 Damien P. George - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#if !defined(LIB_TINYUSB_HOST) && !defined(LIB_TINYUSB_DEVICE) - -#include "tusb.h" -#include "pico/stdio_usb/reset_interface.h" -#include "pico/unique_id.h" - -#ifndef USBD_VID -#define USBD_VID (0x2E8A) // Raspberry Pi -#endif - -#ifndef USBD_PID -#if PICO_RP2040 -#define USBD_PID (0x000a) // Raspberry Pi Pico SDK CDC for RP2040 -#else -#define USBD_PID (0x0009) // Raspberry Pi Pico SDK CDC -#endif -#endif - -#ifndef USBD_MANUFACTURER -#define USBD_MANUFACTURER "Raspberry Pi" -#endif - -#ifndef USBD_PRODUCT -#define USBD_PRODUCT "Pico" -#endif - -#define TUD_RPI_RESET_DESC_LEN 9 -#if !PICO_STDIO_USB_ENABLE_RESET_VIA_VENDOR_INTERFACE -#define USBD_DESC_LEN (TUD_CONFIG_DESC_LEN + TUD_CDC_DESC_LEN) -#else -#define USBD_DESC_LEN (TUD_CONFIG_DESC_LEN + TUD_CDC_DESC_LEN + TUD_RPI_RESET_DESC_LEN) -#endif -#if !PICO_STDIO_USB_DEVICE_SELF_POWERED -#define USBD_CONFIGURATION_DESCRIPTOR_ATTRIBUTE (0) -#define USBD_MAX_POWER_MA (250) -#else -#define USBD_CONFIGURATION_DESCRIPTOR_ATTRIBUTE TUSB_DESC_CONFIG_ATT_SELF_POWERED -#define USBD_MAX_POWER_MA (1) -#endif - -#define USBD_ITF_CDC (0) // needs 2 interfaces -#if !PICO_STDIO_USB_ENABLE_RESET_VIA_VENDOR_INTERFACE -#define USBD_ITF_MAX (2) -#else -#define USBD_ITF_RPI_RESET (2) -#define USBD_ITF_MAX (3) -#endif - -#define USBD_CDC_EP_CMD (0x81) -#define USBD_CDC_EP_OUT (0x02) -#define USBD_CDC_EP_IN (0x82) -#define USBD_CDC_CMD_MAX_SIZE (8) -#define USBD_CDC_IN_OUT_MAX_SIZE (64) - -#define USBD_STR_0 (0x00) -#define USBD_STR_MANUF (0x01) -#define USBD_STR_PRODUCT (0x02) -#define USBD_STR_SERIAL (0x03) -#define USBD_STR_CDC (0x04) -#define USBD_STR_RPI_RESET (0x05) - -// Note: descriptors returned from callbacks must exist long enough for transfer to complete - -static const tusb_desc_device_t usbd_desc_device = { - .bLength = sizeof(tusb_desc_device_t), - .bDescriptorType = TUSB_DESC_DEVICE, -// On Windows, if bcdUSB = 0x210 then a Microsoft OS 2.0 descriptor is required, else the device won't be detected -// This is only needed for driverless access to the reset interface - the CDC interface doesn't require these descriptors -// for driverless access, but will still not work if bcdUSB = 0x210 and no descriptor is provided. Therefore always -// use bcdUSB = 0x200 if the Microsoft OS 2.0 descriptor isn't enabled -#if PICO_STDIO_USB_ENABLE_RESET_VIA_VENDOR_INTERFACE && PICO_STDIO_USB_RESET_INTERFACE_SUPPORT_MS_OS_20_DESCRIPTOR - .bcdUSB = 0x0210, -#else - .bcdUSB = 0x0200, -#endif - .bDeviceClass = TUSB_CLASS_MISC, - .bDeviceSubClass = MISC_SUBCLASS_COMMON, - .bDeviceProtocol = MISC_PROTOCOL_IAD, - .bMaxPacketSize0 = CFG_TUD_ENDPOINT0_SIZE, - .idVendor = USBD_VID, - .idProduct = USBD_PID, - .bcdDevice = 0x0100, - .iManufacturer = USBD_STR_MANUF, - .iProduct = USBD_STR_PRODUCT, - .iSerialNumber = USBD_STR_SERIAL, - .bNumConfigurations = 1, -}; - -#define TUD_RPI_RESET_DESCRIPTOR(_itfnum, _stridx) \ - /* Interface */\ - 9, TUSB_DESC_INTERFACE, _itfnum, 0, 0, TUSB_CLASS_VENDOR_SPECIFIC, RESET_INTERFACE_SUBCLASS, RESET_INTERFACE_PROTOCOL, _stridx, - -static const uint8_t usbd_desc_cfg[USBD_DESC_LEN] = { - TUD_CONFIG_DESCRIPTOR(1, USBD_ITF_MAX, USBD_STR_0, USBD_DESC_LEN, - USBD_CONFIGURATION_DESCRIPTOR_ATTRIBUTE, USBD_MAX_POWER_MA), - - TUD_CDC_DESCRIPTOR(USBD_ITF_CDC, USBD_STR_CDC, USBD_CDC_EP_CMD, - USBD_CDC_CMD_MAX_SIZE, USBD_CDC_EP_OUT, USBD_CDC_EP_IN, USBD_CDC_IN_OUT_MAX_SIZE), - -#if PICO_STDIO_USB_ENABLE_RESET_VIA_VENDOR_INTERFACE - TUD_RPI_RESET_DESCRIPTOR(USBD_ITF_RPI_RESET, USBD_STR_RPI_RESET) -#endif -}; - -static char usbd_serial_str[PICO_UNIQUE_BOARD_ID_SIZE_BYTES * 2 + 1]; - -static const char *const usbd_desc_str[] = { - [USBD_STR_MANUF] = USBD_MANUFACTURER, - [USBD_STR_PRODUCT] = USBD_PRODUCT, - [USBD_STR_SERIAL] = usbd_serial_str, - [USBD_STR_CDC] = "Board CDC", -#if PICO_STDIO_USB_ENABLE_RESET_VIA_VENDOR_INTERFACE - [USBD_STR_RPI_RESET] = "Reset", -#endif -}; - -const uint8_t *tud_descriptor_device_cb(void) { - return (const uint8_t *)&usbd_desc_device; -} - -const uint8_t *tud_descriptor_configuration_cb(__unused uint8_t index) { - return usbd_desc_cfg; -} - -const uint16_t *tud_descriptor_string_cb(uint8_t index, __unused uint16_t langid) { -#ifndef USBD_DESC_STR_MAX -#define USBD_DESC_STR_MAX (20) -#elif USBD_DESC_STR_MAX > 127 -#error USBD_DESC_STR_MAX too high (max is 127). -#elif USBD_DESC_STR_MAX < 17 -#error USBD_DESC_STR_MAX too low (min is 17). -#endif - static uint16_t desc_str[USBD_DESC_STR_MAX]; - - // Assign the SN using the unique flash id - if (!usbd_serial_str[0]) { - pico_get_unique_board_id_string(usbd_serial_str, sizeof(usbd_serial_str)); - } - - uint8_t len; - if (index == 0) { - desc_str[1] = 0x0409; // supported language is English - len = 1; - } else { - if (index >= sizeof(usbd_desc_str) / sizeof(usbd_desc_str[0])) { - return NULL; - } - const char *str = usbd_desc_str[index]; - for (len = 0; len < USBD_DESC_STR_MAX - 1 && str[len]; ++len) { - desc_str[1 + len] = str[len]; - } - } - - // first byte is length (including header), second byte is string type - desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8) | (2 * len + 2)); - - return desc_str; -} - -#endif diff --git a/lib/main/pico-sdk/rp2_common/pico_stdlib/stdlib.c b/lib/main/pico-sdk/rp2_common/pico_stdlib/stdlib.c deleted file mode 100644 index f61b34b568..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_stdlib/stdlib.c +++ /dev/null @@ -1,26 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "pico/stdlib.h" -#if LIB_PICO_STDIO_UART -#include "pico/stdio_uart.h" -#else -#include "pico/binary_info.h" -#endif - -void setup_default_uart(void) { -#if LIB_PICO_STDIO_UART - stdio_uart_init(); -#elif defined(PICO_DEFAULT_UART_BAUD_RATE) && defined(PICO_DEFAULT_UART_TX_PIN) && defined(PICO_DEFAULT_UART_RX_PIN) - // this is mostly for backwards compatibility - stdio_uart_init is a bit more nuanced, and usually likely to be present - uart_init(uart_default, PICO_DEFAULT_UART_BAUD_RATE); - if (PICO_DEFAULT_UART_TX_PIN >= 0) - gpio_set_function(PICO_DEFAULT_UART_TX_PIN, GPIO_FUNC_UART); - if (PICO_DEFAULT_UART_RX_PIN >= 0) - gpio_set_function(PICO_DEFAULT_UART_RX_PIN, GPIO_FUNC_UART); - bi_decl_if_func_used(bi_2pins_with_func(PICO_DEFAULT_UART_RX_PIN, PICO_DEFAULT_UART_TX_PIN, GPIO_FUNC_UART)); -#endif -} diff --git a/lib/main/pico-sdk/rp2_common/pico_time_adapter/include/pico/time_adapter.h b/lib/main/pico-sdk/rp2_common/pico_time_adapter/include/pico/time_adapter.h deleted file mode 100644 index 59308b4b9e..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_time_adapter/include/pico/time_adapter.h +++ /dev/null @@ -1,103 +0,0 @@ -/* - * Copyright (c) 2024 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _PICO_TIME_ADAPTER_H -#define _PICO_TIME_ADAPTER_H - -#include "hardware/irq.h" -#include "hardware/timer.h" -#include "pico/assert.h" - -#define TA_NUM_TIMERS NUM_GENERIC_TIMERS -#define TA_NUM_TIMER_ALARMS NUM_ALARMS - -#define timer_hw_from_timer(t) ((timer_hw_t *)(t)) - -static inline void ta_force_irq(alarm_pool_timer_t *timer, uint alarm_num) { - hw_set_bits(&timer_hw_from_timer(timer)->intf, 1u << alarm_num); -} - -static inline void ta_clear_force_irq(alarm_pool_timer_t *timer, uint alarm_num) { - hw_clear_bits(&timer_hw_from_timer(timer)->intf, 1u << alarm_num); -} - -static inline void ta_clear_irq(alarm_pool_timer_t *timer, uint alarm_num) { - timer_hw_from_timer(timer)->intr = 1u << alarm_num; -} - -static inline alarm_pool_timer_t *ta_from_current_irq(uint *alarm_num) { - uint irq_num = __get_current_exception() - VTABLE_FIRST_IRQ; - alarm_pool_timer_t *timer = timer_get_instance(TIMER_NUM_FROM_IRQ(irq_num)); - *alarm_num = TIMER_ALARM_NUM_FROM_IRQ(irq_num); - return timer; -} - -static inline void ta_set_timeout(alarm_pool_timer_t *timer, uint alarm_num, int64_t target) { - // We never want to set the timeout to be later than our current one. - uint32_t current = timer_time_us_32(timer_hw_from_timer(timer)); - uint32_t time_til_target = (uint32_t) target - current; - uint32_t time_til_alarm = timer_hw_from_timer(timer)->alarm[alarm_num] - current; - // Note: we are only dealing with the low 32 bits of the timer values, - // so there is some opportunity to make wrap-around errors. - // - // 1. If we just passed the alarm time, then time_til_alarm will be high, meaning we will - // likely do the update, but this is OK since the alarm will have just fired - // 2. If we just passed the target time, then time_til_target will be high, meaning we will - // likely not do the update, but this is OK since the caller who has the full 64 bits - // must check if the target time has passed when we return anyway to avoid races. - if (time_til_target < time_til_alarm) { - timer_hw_from_timer(timer)->alarm[alarm_num] = (uint32_t) target; - } -} - -static inline bool ta_wakes_up_on_or_before(alarm_pool_timer_t *timer, uint alarm_num, int64_t target) { - uint32_t current = timer_time_us_32(timer_hw_from_timer(timer)); - uint32_t time_til_target = (uint32_t) target - current; - uint32_t time_til_alarm = timer_hw_from_timer(timer)->alarm[alarm_num] - current; - return time_til_alarm <= time_til_target; -} - -static inline uint64_t ta_time_us_64(alarm_pool_timer_t *timer) { - return timer_time_us_64(timer_hw_from_timer(timer)); -} - -static inline void ta_enable_irq_handler(alarm_pool_timer_t *timer, uint alarm_num, irq_handler_t irq_handler) { - // disarm the timer - uint irq_num = timer_hardware_alarm_get_irq_num(timer, alarm_num); - timer_hw_from_timer(timer)->armed = 1u << alarm_num; - irq_set_exclusive_handler(irq_num, irq_handler); - irq_set_enabled(irq_num, true); - hw_set_bits(&timer_hw_from_timer(timer)->inte, 1u << alarm_num); -} - -static inline void ta_disable_irq_handler(alarm_pool_timer_t *timer, uint alarm_num, irq_handler_t irq_handler) { - uint irq_num = timer_hardware_alarm_get_irq_num(timer, alarm_num); - hw_clear_bits(&timer_hw_from_timer(timer)->inte, 1u << alarm_num); - irq_set_enabled(irq_num, true); - irq_remove_handler(irq_num, irq_handler); - hardware_alarm_unclaim(alarm_num); -} - -static inline void ta_hardware_alarm_claim(alarm_pool_timer_t *timer, uint hardware_alaram_num) { - timer_hardware_alarm_claim(timer_hw_from_timer(timer), hardware_alaram_num); -} - -static inline int ta_hardware_alarm_claim_unused(alarm_pool_timer_t *timer, bool required) { - return timer_hardware_alarm_claim_unused(timer, required); -} - -static inline alarm_pool_timer_t *ta_timer_instance(uint timer_num) { - return timer_get_instance(timer_num); -} - -static inline uint ta_timer_num(alarm_pool_timer_t *timer) { - return timer_get_index(timer_hw_from_timer(timer)); -} - -static inline alarm_pool_timer_t *ta_default_timer_instance(void) { - return PICO_DEFAULT_TIMER_INSTANCE(); -} -#endif diff --git a/lib/main/pico-sdk/rp2_common/pico_unique_id/include/pico/unique_id.h b/lib/main/pico-sdk/rp2_common/pico_unique_id/include/pico/unique_id.h deleted file mode 100644 index 367d32bffe..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_unique_id/include/pico/unique_id.h +++ /dev/null @@ -1,107 +0,0 @@ -/* - * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _PICO_UNIQUE_ID_H -#define _PICO_UNIQUE_ID_H - -#include "pico.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** \file pico/unique_id.h - * \defgroup pico_unique_id pico_unique_id - * - * \brief Unique device ID access API - * - * \if rp2040_specific - * RP2040 does not have an on-board unique identifier (all instances of RP2040 - * silicon are identical and have no persistent state). However, RP2040 boots - * from serial NOR flash devices which have at least a 64-bit unique ID as a standard - * feature, and there is a 1:1 association between RP2040 and flash, so this - * is suitable for use as a unique identifier for an RP2040-based board. - * - * This library injects a call to the flash_get_unique_id function from the - * hardware_flash library, to run before main, and stores the result in a - * static location which can safely be accessed at any time via - * pico_get_unique_id(). - * - * This avoids some pitfalls of the hardware_flash API, which requires any - * flash-resident interrupt routines to be disabled when called into. - * \endif - * - * \if rp2350_specific - * On boards using RP2350, the unique identifier is read from OTP memory on boot. - * \endif - */ - -#define PICO_UNIQUE_BOARD_ID_SIZE_BYTES 8 - -/** - * \brief Unique board identifier - * \ingroup pico_unique_id - * - * This structure contains an array of PICO_UNIQUE_BOARD_ID_SIZE_BYTES identifier bytes suitable for - * holding the unique identifier for the device. - * - * \if rp2040_specific - * On an RP2040-based board, the unique identifier is retrieved from the external NOR flash device at boot, - * or for PICO_NO_FLASH builds the unique identifier is set to all 0xEE. - * \endif - * - * \if rp2350_specific - * On an RP2350-based board, the unique identifier is retrieved from OTP memory at boot. - * \endif - * - */ -typedef struct { - uint8_t id[PICO_UNIQUE_BOARD_ID_SIZE_BYTES]; -} pico_unique_board_id_t; - -/*! \brief Get unique ID - * \ingroup pico_unique_id - * - * Get the unique 64-bit device identifier. - * - * \if rp2040_specific - * On an RP2040-based board, the unique identifier is retrieved from the external NOR flash device at boot, - * or for PICO_NO_FLASH builds the unique identifier is set to all 0xEE. - * \endif - * - * \if rp2350_specific - * On an RP2350-based board, the unique identifier is retrieved from OTP memory at boot. - * \endif - * - * \param id_out a pointer to a pico_unique_board_id_t struct, to which the identifier will be written - */ -void pico_get_unique_board_id(pico_unique_board_id_t *id_out); - -/*! \brief Get unique ID in string format - * \ingroup pico_unique_id - * - * Get the unique 64-bit device identifier formatted as a 0-terminated ASCII hex string. - * - * \if rp2040_specific - * On an RP2040-based board, the unique identifier is retrieved from the external NOR flash device at boot, - * or for PICO_NO_FLASH builds the unique identifier is set to all 0xEE. - * \endif - * - * \if rp2350_specific - * On an RP2350-based board, the unique identifier is retrieved from OTP memory at boot. - * \endif - * - * \param id_out a pointer to a char buffer of size len, to which the identifier will be written - * \param len the size of id_out. For full serial, len >= 2 * PICO_UNIQUE_BOARD_ID_SIZE_BYTES + 1 - */ -void pico_get_unique_board_id_string(char *id_out, uint len); - - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/lib/main/pico-sdk/rp2_common/pico_unique_id/unique_id.c b/lib/main/pico-sdk/rp2_common/pico_unique_id/unique_id.c deleted file mode 100644 index c027bf27d5..0000000000 --- a/lib/main/pico-sdk/rp2_common/pico_unique_id/unique_id.c +++ /dev/null @@ -1,61 +0,0 @@ -/* - * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "hardware/flash.h" -#include "pico/bootrom.h" -#include "pico/unique_id.h" - -static_assert(PICO_UNIQUE_BOARD_ID_SIZE_BYTES <= FLASH_UNIQUE_ID_SIZE_BYTES, "Board ID size must at least be the size of flash ID"); - -static pico_unique_board_id_t retrieved_id; - -static void __attribute__((constructor)) _retrieve_unique_id_on_boot(void) { -#if PICO_RP2040 - #if PICO_NO_FLASH - // The hardware_flash call will panic() if called directly on a NO_FLASH - // build. Since this constructor is pre-main it would be annoying to - // debug, so just produce something well-defined and obviously wrong. - for (int i = 0; i < PICO_UNIQUE_BOARD_ID_SIZE_BYTES; i++) - retrieved_id.id[i] = 0xee; - #elif (PICO_UNIQUE_BOARD_ID_SIZE_BYTES == FLASH_UNIQUE_ID_SIZE_BYTES) - flash_get_unique_id(retrieved_id.id); - #elif (PICO_UNIQUE_BOARD_ID_SIZE_BYTES < FLASH_UNIQUE_ID_SIZE_BYTES) - // The flash ID is >8 bytes (e.g. IS25LP016D) but we want to keep the - // pico unique board ID as 8 bytes, just use the last 8 bytes which are likely to change - uint8_t flash_id[FLASH_UNIQUE_ID_SIZE_BYTES]; - flash_get_unique_id(flash_id); - memcpy(retrieved_id.id, flash_id + FLASH_UNIQUE_ID_SIZE_BYTES - PICO_UNIQUE_BOARD_ID_SIZE_BYTES, PICO_UNIQUE_BOARD_ID_SIZE_BYTES); - #else - #error unique board ID size is greater than flash unique ID size - #endif -#else - rom_get_sys_info_fn func = (rom_get_sys_info_fn) rom_func_lookup(ROM_FUNC_GET_SYS_INFO); - union { - uint32_t words[9]; - uint8_t bytes[9 * 4]; - } out; - __unused int rc = func(out.words, 9, SYS_INFO_CHIP_INFO); - assert(rc == 4); - for (int i = 0; i < PICO_UNIQUE_BOARD_ID_SIZE_BYTES; i++) { - retrieved_id.id[i] = out.bytes[PICO_UNIQUE_BOARD_ID_SIZE_BYTES - 1 + 2 * 4 - i]; - } -#endif -} - -void pico_get_unique_board_id(pico_unique_board_id_t *id_out) { - *id_out = retrieved_id; -} - -void pico_get_unique_board_id_string(char *id_out, uint len) { - assert(len > 0); - size_t i; - // Generate hex one nibble at a time - for (i = 0; (i < len - 1) && (i < PICO_UNIQUE_BOARD_ID_SIZE_BYTES * 2); i++) { - int nibble = (retrieved_id.id[i/2] >> (4 - 4 * (i&1))) & 0xf; - id_out[i] = (char)(nibble < 10 ? nibble + '0' : nibble + 'A' - 10); - } - id_out[i] = 0; -} diff --git a/lib/main/pico-sdk/rp2_common/tinyusb/doc.h b/lib/main/pico-sdk/rp2_common/tinyusb/doc.h deleted file mode 100644 index 8dc0d8fe91..0000000000 --- a/lib/main/pico-sdk/rp2_common/tinyusb/doc.h +++ /dev/null @@ -1,7 +0,0 @@ -/** - * \defgroup tinyusb_device tinyusb_device - * \brief TinyUSB Device-mode support for the RP2040. The TinyUSB documentation site can be found here. - * - * \defgroup tinyusb_host tinyusb_host - * \brief TinyUSB Host-mode support for the RP2040. - */ diff --git a/lib/main/pico-sdk/rp2_common/tinyusb/include/bsp/board.h b/lib/main/pico-sdk/rp2_common/tinyusb/include/bsp/board.h deleted file mode 100644 index 0ebb6ba13a..0000000000 --- a/lib/main/pico-sdk/rp2_common/tinyusb/include/bsp/board.h +++ /dev/null @@ -1,11 +0,0 @@ -/* - * Copyright (c) 2024 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -// TinyUSB changed the location of this file, so we'll redirect to be friendly to end users -#ifndef _BSP_BOARD_H -#define _BSP_BOARD_H -#include "bsp/board_api.h" -#endif diff --git a/lib/main/pico-sdk/rp2_common/tinyusb/tinyusb.BUILD b/lib/main/pico-sdk/rp2_common/tinyusb/tinyusb.BUILD deleted file mode 100644 index ea0a5c3edd..0000000000 --- a/lib/main/pico-sdk/rp2_common/tinyusb/tinyusb.BUILD +++ /dev/null @@ -1,42 +0,0 @@ -package(default_visibility = ["//visibility:public"]) - -exports_files( - glob(["**/*"]), - visibility = ["//visibility:public"], -) - -cc_library( - name = "tinyusb", - srcs = [ - "hw/bsp/rp2040/family.c", - "src/class/audio/audio_device.c", - "src/class/cdc/cdc_device.c", - "src/class/dfu/dfu_device.c", - "src/class/dfu/dfu_rt_device.c", - "src/class/hid/hid_device.c", - "src/class/midi/midi_device.c", - "src/class/msc/msc_device.c", - "src/class/net/ecm_rndis_device.c", - "src/class/net/ncm_device.c", - "src/class/usbtmc/usbtmc_device.c", - "src/class/vendor/vendor_device.c", - "src/class/video/video_device.c", - "src/common/tusb_fifo.c", - "src/device/usbd.c", - "src/device/usbd_control.c", - "src/portable/raspberrypi/rp2040/dcd_rp2040.c", - "src/portable/raspberrypi/rp2040/rp2040_usb.c", - "src/tusb.c", - ], - hdrs = glob([ - "src/**/*.h", - "hw/bsp/*.h", - "hw/bsp/rp2040/**/*.h", - ]), - includes = [ - "hw", - "hw/bsp", - "src", - ], - deps = ["@pico-sdk//src/rp2_common/tinyusb:tinyusb_port"], -) From 60aaf1ef1e87380c35167ce4d9b87eccc838f8b7 Mon Sep 17 00:00:00 2001 From: LarryKarhu <98162801+LarryKarhu@users.noreply.github.com> Date: Sun, 25 May 2025 01:37:33 +0600 Subject: [PATCH 211/244] Add rangefinder TF-Nova (#14376) * Add rangefinder TF-Nova * fix * Return comments. Removed spaces * Removed invalid command. Expanded range * tfmini and tf02 united command for 100hz sampling * add aray and enum * add array and enum * rollback * add lidar data output to osd * tabs delete * returned whitespaces * switching OSD * delete icon 'lidar' --- src/main/cli/settings.c | 5 +- src/main/cms/cms_menu_osd.c | 3 + .../drivers/rangefinder/rangefinder_lidartf.c | 72 +++++++++++++++---- .../drivers/rangefinder/rangefinder_lidartf.h | 1 + src/main/osd/osd.h | 1 + src/main/osd/osd_elements.c | 26 ++++++- src/main/sensors/rangefinder.c | 9 +++ src/main/sensors/rangefinder.h | 1 + 8 files changed, 104 insertions(+), 14 deletions(-) diff --git a/src/main/cli/settings.c b/src/main/cli/settings.c index b0ad031be9..e1c33fd4b0 100644 --- a/src/main/cli/settings.c +++ b/src/main/cli/settings.c @@ -202,7 +202,7 @@ const char * const lookupTableMagHardware[] = { #endif #if defined(USE_SENSOR_NAMES) || defined(USE_RANGEFINDER) const char * const lookupTableRangefinderHardware[] = { - "NONE", "HCSR04", "TFMINI", "TF02", "MTF01", "MTF02", "MTF01P", "MTF02P" + "NONE", "HCSR04", "TFMINI", "TF02", "MTF01", "MTF02", "MTF01P", "MTF02P", "TFNOVA" }; #endif #if defined(USE_SENSOR_NAMES) || defined(USE_OPTICALFLOW) @@ -1671,6 +1671,9 @@ const clivalue_t valueTable[] = { #ifdef USE_CRAFTNAME_MSGS { "osd_craftname_msgs", VAR_UINT8 | MASTER_VALUE | MODE_LOOKUP, .config.lookup = { TABLE_OFF_ON }, PG_OSD_CONFIG, offsetof(osdConfig_t, osd_craftname_msgs) }, #endif //USE_CRAFTNAME_MSGS +#ifdef USE_RANGEFINDER + { "osd_lidar_dist_pos", VAR_UINT16 | MASTER_VALUE, .config.minmaxUnsigned = { 0, OSD_POSCFG_MAX }, PG_OSD_ELEMENT_CONFIG, offsetof(osdElementConfig_t, item_pos[OSD_LIDAR_DIST]) }, +#endif //USE_RANGEFINDER #endif // end of #ifdef USE_OSD // PG_SYSTEM_CONFIG diff --git a/src/main/cms/cms_menu_osd.c b/src/main/cms/cms_menu_osd.c index 1756ba3d80..296e176904 100644 --- a/src/main/cms/cms_menu_osd.c +++ b/src/main/cms/cms_menu_osd.c @@ -175,6 +175,9 @@ const OSD_Entry menuOsdActiveElemsEntries[] = {"CAMERA FRAME", OME_VISIBLE | DYNAMIC, NULL, &osdConfig_item_pos[OSD_CAMERA_FRAME]}, {"TOTAL FLIGHTS", OME_VISIBLE | DYNAMIC, NULL, &osdConfig_item_pos[OSD_TOTAL_FLIGHTS]}, {"AUX VALUE", OME_VISIBLE | DYNAMIC, NULL, &osdConfig_item_pos[OSD_AUX_VALUE]}, +#ifdef USE_RANGEFINDER + {"LIDAR DIST", OME_VISIBLE | DYNAMIC, NULL, &osdConfig_item_pos[OSD_LIDAR_DIST]}, +#endif {"BACK", OME_Back, NULL, NULL}, {NULL, OME_END, NULL, NULL} }; diff --git a/src/main/drivers/rangefinder/rangefinder_lidartf.c b/src/main/drivers/rangefinder/rangefinder_lidartf.c index 07d0c330ed..643b66694a 100644 --- a/src/main/drivers/rangefinder/rangefinder_lidartf.c +++ b/src/main/drivers/rangefinder/rangefinder_lidartf.c @@ -37,6 +37,7 @@ #define TF_DEVTYPE_NONE 0 #define TF_DEVTYPE_MINI 1 #define TF_DEVTYPE_02 2 +#define TF_DEVTYPE_NOVA 3 static uint8_t tfDevtype = TF_DEVTYPE_NONE; @@ -81,6 +82,25 @@ static uint8_t tfDevtype = TF_DEVTYPE_NONE; // #define TF_02_FRAME_SIG 4 +// +// Benewake TFnova frame format +// Byte Off Description +// 1 - SYNC +// 2 - SYNC +// 3 0 Measured distance (LSB) +// 4 1 Measured distance (MSB) +// 5 2 Signal strength (LSB) +// 6 3 Signal strength (MSB) +// 7 4 Temp (Chip Temperature, degrees Celsius) +// 8 5 Confidence (Confidence level 0-100) +// 9 - Checksum (Unsigned 8-bit sum of bytes 0~7) +// +// Credibility +// 1. If Confidence level < 90, unreliable +// 2. If distance is 14m (1400cm), then OoR. +// +#define TF_NOVA_FRAME_CONFIDENCE 5 + // Maximum ratings #define TF_MINI_RANGE_MIN 40 @@ -89,6 +109,9 @@ static uint8_t tfDevtype = TF_DEVTYPE_NONE; #define TF_02_RANGE_MIN 40 #define TF_02_RANGE_MAX 2200 +#define TF_NOVA_RANGE_MIN 10 +#define TF_NOVA_RANGE_MAX 1400 + #define TF_DETECTION_CONE_DECIDEGREES 900 static serialPort_t *tfSerialPort = NULL; @@ -104,14 +127,10 @@ static tfFrameState_e tfFrameState; static uint8_t tfFrame[TF_FRAME_LENGTH]; static uint8_t tfReceivePosition; -// TFmini +// TFmini and TF02 // Command for 100Hz sampling (10msec interval) // At 100Hz scheduling, skew will cause 10msec delay at the most. -static uint8_t tfCmdTFmini[] = { 0x42, 0x57, 0x02, 0x00, 0x00, 0x00, 0x01, 0x06 }; - -// TF02 -// Same as TFmini for now.. -static uint8_t tfCmdTF02[] = { 0x42, 0x57, 0x02, 0x00, 0x00, 0x00, 0x01, 0x06 }; +static const uint8_t tfCmd[] = { 0x42, 0x57, 0x02, 0x00, 0x00, 0x00, 0x01, 0x06 }; static int32_t lidarTFValue; static uint16_t lidarTFerrors = 0; @@ -120,11 +139,12 @@ static void lidarTFSendCommand(void) { switch (tfDevtype) { case TF_DEVTYPE_MINI: - serialWriteBuf(tfSerialPort, tfCmdTFmini, sizeof(tfCmdTFmini)); - break; case TF_DEVTYPE_02: - serialWriteBuf(tfSerialPort, tfCmdTF02, sizeof(tfCmdTF02)); + serialWriteBuf(tfSerialPort, tfCmd, sizeof(tfCmd)); break; + default: + break; + } } @@ -173,7 +193,7 @@ static void lidarTFUpdate(rangefinderDev_t *dev) case TF_FRAME_STATE_WAIT_CKSUM: { uint8_t cksum = TF_FRAME_SYNC_BYTE + TF_FRAME_SYNC_BYTE; - for (int i = 0 ; i < TF_FRAME_LENGTH ; i++) { + for (int i = 0; i < TF_FRAME_LENGTH; i++) { cksum += tfFrame[i]; } @@ -192,7 +212,7 @@ static void lidarTFUpdate(rangefinderDev_t *dev) if (distance >= TF_MINI_RANGE_MIN && distance < TF_MINI_RANGE_MAX) { lidarTFValue = distance; if (tfFrame[TF_MINI_FRAME_INTEGRAL_TIME] == 7) { - // When integral time is long (7), measured distance tends to be longer by 12~13. + // When integral time is long (7), measured distance tends to be longer by 12~13. lidarTFValue -= 13; } } else { @@ -207,6 +227,14 @@ static void lidarTFUpdate(rangefinderDev_t *dev) lidarTFValue = -1; } break; + + case TF_DEVTYPE_NOVA: + if (distance >= TF_NOVA_RANGE_MIN && distance <= TF_NOVA_RANGE_MAX && tfFrame[TF_NOVA_FRAME_CONFIDENCE] >= 90) { + lidarTFValue = distance; + } else { + lidarTFValue = -1; + } + break; } lastFrameReceivedMs = timeNowMs; } else { @@ -256,7 +284,21 @@ static bool lidarTFDetect(rangefinderDev_t *dev, uint8_t devtype) tfDevtype = devtype; dev->delayMs = 10; - dev->maxRangeCm = (devtype == TF_DEVTYPE_MINI) ? TF_MINI_RANGE_MAX : TF_02_RANGE_MAX; + switch (devtype) { + case TF_DEVTYPE_MINI: + dev->maxRangeCm = TF_MINI_RANGE_MAX; + break; + case TF_DEVTYPE_02: + dev->maxRangeCm = TF_02_RANGE_MAX; + break; + case TF_DEVTYPE_NOVA: + dev->maxRangeCm = TF_NOVA_RANGE_MAX; + break; + default: + dev->maxRangeCm = 0; + break; + } + dev->detectionConeDeciDegrees = TF_DETECTION_CONE_DECIDEGREES; dev->detectionConeExtendedDeciDegrees = TF_DETECTION_CONE_DECIDEGREES; @@ -276,4 +318,10 @@ bool lidarTF02Detect(rangefinderDev_t *dev) { return lidarTFDetect(dev, TF_DEVTYPE_02); } + +bool lidarTFNovaDetect(rangefinderDev_t *dev) +{ + return lidarTFDetect(dev, TF_DEVTYPE_NOVA); +} + #endif diff --git a/src/main/drivers/rangefinder/rangefinder_lidartf.h b/src/main/drivers/rangefinder/rangefinder_lidartf.h index 5ac34d4c62..cd786a79bc 100644 --- a/src/main/drivers/rangefinder/rangefinder_lidartf.h +++ b/src/main/drivers/rangefinder/rangefinder_lidartf.h @@ -26,3 +26,4 @@ bool lidarTFminiDetect(rangefinderDev_t *dev); bool lidarTF02Detect(rangefinderDev_t *dev); +bool lidarTFNovaDetect(rangefinderDev_t *dev); diff --git a/src/main/osd/osd.h b/src/main/osd/osd.h index eabb04d543..4cdb0f4d56 100644 --- a/src/main/osd/osd.h +++ b/src/main/osd/osd.h @@ -194,6 +194,7 @@ typedef enum { OSD_CUSTOM_MSG1, OSD_CUSTOM_MSG2, OSD_CUSTOM_MSG3, + OSD_LIDAR_DIST, OSD_ITEM_COUNT // MUST BE LAST } osd_items_e; diff --git a/src/main/osd/osd_elements.c b/src/main/osd/osd_elements.c index c4f92181b4..da59d7fae1 100644 --- a/src/main/osd/osd_elements.c +++ b/src/main/osd/osd_elements.c @@ -50,6 +50,8 @@ Add the mapping for the element ID to the background drawing function to the osdElementBackgroundFunction array. + + You should also add a corresponding entry to the file: cms_menu_osd.c Accelerometer reqirement: ------------------------- @@ -170,6 +172,7 @@ #include "sensors/barometer.h" #include "sensors/battery.h" #include "sensors/sensors.h" +#include "sensors/rangefinder.h" #ifdef USE_GPS_PLUS_CODES // located in lib/main/google/olc @@ -320,7 +323,6 @@ int osdConvertTemperatureToSelectedUnit(int tempInDegreesCelcius) } } #endif - static void osdFormatAltitudeString(char * buff, int32_t altitudeCm, osdElementType_e variantType) { static const struct { @@ -682,6 +684,22 @@ char osdGetTemperatureSymbolForSelectedUnit(void) // Element drawing functions // ************************* +#ifdef USE_RANGEFINDER +static void osdElementLidarDist(osdElementParms_t *element) +{ + int16_t dist = rangefinderGetLatestAltitude(); + + if (dist > 0) { + + tfp_sprintf(element->buff, "RF:%3d", dist); + + } else { + + tfp_sprintf(element->buff, "RF:---"); + } +} +#endif + #ifdef USE_OSD_ADJUSTMENTS static void osdElementAdjustmentRange(osdElementParms_t *element) { @@ -1918,6 +1936,9 @@ static const uint8_t osdElementDisplayOrder[] = { OSD_SYS_VTX_TEMP, OSD_SYS_FAN_SPEED, #endif +#ifdef USE_RANGEFINDER + OSD_LIDAR_DIST, +#endif }; // Define the mapping between the OSD element id and the function to draw it @@ -2062,6 +2083,9 @@ const osdElementDrawFn osdElementDrawFunction[OSD_ITEM_COUNT] = { [OSD_SYS_VTX_TEMP] = osdElementSys, [OSD_SYS_FAN_SPEED] = osdElementSys, #endif +#ifdef USE_RANGEFINDER + [OSD_LIDAR_DIST] = osdElementLidarDist, +#endif }; // Define the mapping between the OSD element id and the function to draw its background (static part) diff --git a/src/main/sensors/rangefinder.c b/src/main/sensors/rangefinder.c index 62790f036d..e243b5027f 100644 --- a/src/main/sensors/rangefinder.c +++ b/src/main/sensors/rangefinder.c @@ -127,6 +127,15 @@ static bool rangefinderDetect(rangefinderDev_t * dev, uint8_t rangefinderHardwar #endif break; + case RANGEFINDER_TFNOVA: +#if defined(USE_RANGEFINDER_TF) + if (lidarTFNovaDetect(dev)) { + rangefinderHardware = RANGEFINDER_TFNOVA; + rescheduleTask(TASK_RANGEFINDER, TASK_PERIOD_MS(RANGEFINDER_TF_TASK_PERIOD_MS)); + } +#endif + break; + #if defined(USE_RANGEFINDER_MT) case RANGEFINDER_MTF01: case RANGEFINDER_MTF02: diff --git a/src/main/sensors/rangefinder.h b/src/main/sensors/rangefinder.h index 6cc9684af1..7d4ba30e53 100644 --- a/src/main/sensors/rangefinder.h +++ b/src/main/sensors/rangefinder.h @@ -35,6 +35,7 @@ typedef enum { RANGEFINDER_MTF02 = 5, RANGEFINDER_MTF01P = 6, RANGEFINDER_MTF02P = 7, + RANGEFINDER_TFNOVA = 8, } rangefinderType_e; typedef struct rangefinderConfig_s { From 62be38297c7a09562ef3fa322c229f827cd84c8d Mon Sep 17 00:00:00 2001 From: "Git bot (blckmn)" Date: Sun, 25 May 2025 06:25:03 +0000 Subject: [PATCH 212/244] Auto updated submodule references [25-05-2025] --- src/config | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/config b/src/config index 17892ac1bd..22dc66d412 160000 --- a/src/config +++ b/src/config @@ -1 +1 @@ -Subproject commit 17892ac1bd9bc74f77870c14a2da386a1c614dd3 +Subproject commit 22dc66d412b21f9cbf78fe481b7a3c158c46ca68 From b389c2000dfc1eca4e56b365a5fafa91218ed26b Mon Sep 17 00:00:00 2001 From: cvetaevvitaliy Date: Mon, 26 May 2025 13:00:41 +0300 Subject: [PATCH 213/244] Implementation of the ICM456xx gyroscope driver (#14348) * add support ICM-45686, ICM45605 gyros Co-authored-by: Mark Haslinghuis Co-authored-by: Mark Haslinghuis * update PR issue * change IMU order * fix register AAF for Accel, update comments, configure LPF from config * change IMU order * fix access to IPREG_TOP1 registers, update define INT1_CONFIG2 * add read Gyro&Acc via SPI DMA * coderabbitai bot suggestion Co-authored-by: coderabbitai[bot] <136622811+coderabbitai[bot]@users.noreply.github.com> * fix buf len * codestyle Co-authored-by: Mark Haslinghuis * coderabbitai bot suggestion: SPI transfer, Inconsistent accelerometer scale setting * refactor read spi * update PR issue * revert "attempts remaining" for gyro detect * resolve issue Co-authored-by: Petr Ledvina --------- Co-authored-by: Mark Haslinghuis Co-authored-by: coderabbitai[bot] <136622811+coderabbitai[bot]@users.noreply.github.com> Co-authored-by: Petr Ledvina --- mk/source.mk | 1 + src/main/cli/settings.c | 4 + src/main/drivers/accgyro/accgyro.h | 2 + src/main/drivers/accgyro/accgyro_mpu.c | 4 + src/main/drivers/accgyro/accgyro_mpu.h | 6 +- .../drivers/accgyro/accgyro_spi_icm456xx.c | 630 ++++++++++++++++++ .../drivers/accgyro/accgyro_spi_icm456xx.h | 32 + src/main/drivers/accgyro/gyro_sync.c | 6 + src/main/sensors/acceleration.h | 2 + src/main/sensors/acceleration_init.c | 21 + src/main/sensors/gyro_init.c | 24 + src/main/target/common_post.h | 9 +- src/main/target/common_pre.h | 2 + 13 files changed, 740 insertions(+), 3 deletions(-) create mode 100644 src/main/drivers/accgyro/accgyro_spi_icm456xx.c create mode 100644 src/main/drivers/accgyro/accgyro_spi_icm456xx.h diff --git a/mk/source.mk b/mk/source.mk index b0606dbd6e..13e55fb4d6 100644 --- a/mk/source.mk +++ b/mk/source.mk @@ -298,6 +298,7 @@ COMMON_SRC += \ drivers/accgyro/accgyro_spi_icm20649.c \ drivers/accgyro/accgyro_spi_icm20689.c \ drivers/accgyro/accgyro_spi_icm426xx.c \ + drivers/accgyro/accgyro_spi_icm456xx.c \ drivers/accgyro/accgyro_spi_l3gd20.c \ drivers/accgyro/accgyro_spi_lsm6dso.c \ drivers/accgyro/accgyro_spi_lsm6dso_init.c \ diff --git a/src/main/cli/settings.c b/src/main/cli/settings.c index e1c33fd4b0..91e23d6d29 100644 --- a/src/main/cli/settings.c +++ b/src/main/cli/settings.c @@ -161,6 +161,8 @@ const char * const lookupTableAccHardware[] = { "LSM6DSO", "LSM6DSV16X", "IIM42653", + "ICM45605", + "ICM45686", "VIRTUAL" }; @@ -185,6 +187,8 @@ const char * const lookupTableGyroHardware[] = { "LSM6DSO", "LSM6DSV16X", "IIM42653", + "ICM45605", + "ICM45686", "VIRTUAL" }; diff --git a/src/main/drivers/accgyro/accgyro.h b/src/main/drivers/accgyro/accgyro.h index 51a7672b1f..d8be175115 100644 --- a/src/main/drivers/accgyro/accgyro.h +++ b/src/main/drivers/accgyro/accgyro.h @@ -62,6 +62,8 @@ typedef enum { GYRO_LSM6DSO, GYRO_LSM6DSV16X, GYRO_IIM42653, + GYRO_ICM45605, + GYRO_ICM45686, GYRO_VIRTUAL } gyroHardware_e; diff --git a/src/main/drivers/accgyro/accgyro_mpu.c b/src/main/drivers/accgyro/accgyro_mpu.c index 415e0af98b..930028f0a3 100644 --- a/src/main/drivers/accgyro/accgyro_mpu.c +++ b/src/main/drivers/accgyro/accgyro_mpu.c @@ -50,6 +50,7 @@ #include "drivers/accgyro/accgyro_spi_icm20649.h" #include "drivers/accgyro/accgyro_spi_icm20689.h" #include "drivers/accgyro/accgyro_spi_icm426xx.h" +#include "drivers/accgyro/accgyro_spi_icm456xx.h" #include "drivers/accgyro/accgyro_spi_lsm6dso.h" #include "drivers/accgyro/accgyro_spi_mpu6000.h" #include "drivers/accgyro/accgyro_spi_mpu6500.h" @@ -371,6 +372,9 @@ static gyroSpiDetectFn_t gyroSpiDetectFnTable[] = { #ifdef USE_GYRO_SPI_ICM20649 icm20649SpiDetect, #endif +#if defined(USE_ACCGYRO_ICM45686) || defined(USE_ACCGYRO_ICM45605) + icm456xxSpiDetect, +#endif #ifdef USE_GYRO_L3GD20 l3gd20Detect, #endif diff --git a/src/main/drivers/accgyro/accgyro_mpu.h b/src/main/drivers/accgyro/accgyro_mpu.h index 3c06a02ba2..b72356ddef 100644 --- a/src/main/drivers/accgyro/accgyro_mpu.h +++ b/src/main/drivers/accgyro/accgyro_mpu.h @@ -45,6 +45,8 @@ #define ICM20689_WHO_AM_I_CONST (0x98) #define ICM42605_WHO_AM_I_CONST (0x42) #define ICM42688P_WHO_AM_I_CONST (0x47) +#define ICM45686_WHO_AM_I_CONST (0xE9) +#define ICM45605_WHO_AM_I_CONST (0xE5) #define IIM42653_WHO_AM_I_CONST (0x56) #define LSM6DSV16X_WHO_AM_I_CONST (0x70) @@ -209,7 +211,9 @@ typedef enum { BMI_270_SPI, LSM6DSO_SPI, L3GD20_SPI, - LSM6DSV16X_SPI + LSM6DSV16X_SPI, + ICM_45605_SPI, + ICM_45686_SPI, } mpuSensor_e; typedef enum { diff --git a/src/main/drivers/accgyro/accgyro_spi_icm456xx.c b/src/main/drivers/accgyro/accgyro_spi_icm456xx.c new file mode 100644 index 0000000000..34b6a17b28 --- /dev/null +++ b/src/main/drivers/accgyro/accgyro_spi_icm456xx.c @@ -0,0 +1,630 @@ +/* + * This file is part of Betaflight. + * + * Betaflight is free software. You can redistribute this software + * and/or modify this software under the terms of the GNU General + * Public License as published by the Free Software Foundation, + * either version 3 of the License, or (at your option) any later + * version. + * + * Betaflight is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * See the GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this software. + * + * If not, see . + */ + +#include +#include +#include +#include + +#include "platform.h" + +#if defined(USE_ACCGYRO_ICM45686) || defined(USE_ACCGYRO_ICM45605) + +#include "common/axis.h" +#include "common/utils.h" +#include "build/debug.h" + +#include "drivers/accgyro/accgyro.h" +#include "drivers/accgyro/accgyro_mpu.h" +#include "drivers/accgyro/accgyro_spi_icm456xx.h" +#include "drivers/bus_spi.h" +#include "drivers/exti.h" +#include "drivers/io.h" +#include "drivers/pwm_output.h" +#include "drivers/sensor.h" +#include "drivers/time.h" +#include "drivers/system.h" + +#include "fc/runtime_config.h" + +#include "sensors/gyro.h" +#include "pg/gyrodev.h" + +/* +reference: https://github.com/tdk-invn-oss/motion.mcu.icm45686.driver +Datasheet: https://invensense.tdk.com/wp-content/uploads/documentation/DS-000577_ICM-45686.pdf +Datasheet: https://invensense.tdk.com/wp-content/uploads/documentation/DS-000576_ICM-45605.pdf + +Note: ICM456xx has two modes of operation: Low-Power Mode Low-Noise Mode +Note: Now implemented only UI Interface with Low-Noise Mode + + The following diagram shows the signal path for each mode: + The cut-off frequency of the filters is determined by the ODR setting. + + Low-Noise Mode + +------+ +--------------+ +-------------+ +--------------+ +------------------+ + | ADC |---->| Anti-Alias |--->| Interpolator|--->| LPF |--->| Sensor Registers |---> UI Interface + | | | Filter (AAF) | | | +->| & ODR Select | | | + +--|---+ +--------------+ +-------------+ | +--------------+ +------------------+ + | | + | Low-Power Mode | + | +--------------+ | + |-------->| Notch Filter |--------------------| + | | | + | +--------------+ + | + | + +--|---+ +--------------+ +------+ +------+ +------------------+ + | ADC | --------> | Notch Filter | ---> | HPF | ---> | LPF | ---> | Sensor Registers | ---> AUX1 Interface + | | | | | | | | | | + +------+ +--------------+ +------+ +------+ +------------------+ + + The AUX1 interface default configuration can be checked by read only register IOC_PAD_SCENARIO through host interface. + By default, AUX1 interface is enabled, and default interface for AUX1 is SPI3W or I3CSM. + + In Low-Noise Mode, the ADC output is sent through an Anti-Alias Filter (AAF). The AAF is an FIR filter with fixed + coefficients (not user configurable). The AAF can be enabled or disabled by the user using GYRO_SRC_CTRL and + ACCEL_SRC_CTRL. + + The AUX1 signal path includes a Notch Filter. The notch filter is not user programmable. The usage of the notch + filter in the auxiliary path is recommended for sharper roll-off and for the cases where user is asynchronously + sampling the auxiliary interface data output at integer multiples of 1 kHz rate. The notch filter may be bypassed + using GYRO_OIS_M6_BYP. + + The notch filter is followed by an HPF on the AUX1 signal path. HPF cut-off frequency can be selected using + GYRO_OIS_HPFBW_SEL and ACCEL_OIS_HPFBW_SEL. HPF can be bypassed using GYRO_OIS_HPF1_BYP and + ACCEL_OIS_HPF1_BYP. + + The HPF is followed by LPF on the AUX1 signal path. The AUX1 LPF BW is set by register bit field + GYRO_OIS_LPF1BW_SEL and ACCEL_OIS_LPF1BW_SEL for gyroscope and accelerometer respectively. This is + followed by Full Scale Range (FSR) selection based on user configurable settings for register fields + GYRO_AUX1_FS_SEL and ACCEL_AUX1_FS_SEL. AUX1 output is fixed at 6.4kHz ODR. +*/ + +#define ICM456XX_REG_BANK_SEL 0x75 +#define ICM456XX_BANK_0 0x00 +#define ICM456XX_BANK_1 0x01 + +// Register map Bank 0 +#define ICM456XX_WHO_AM_REGISTER 0x72 +#define ICM456XX_REG_MISC2 0x7F +#define ICM456XX_INT1_CONFIG0 0x16 +#define ICM456XX_INT1_CONFIG2 0x18 +#define ICM456XX_INT1_STATUS0 0x19 +#define ICM456XX_INT1_STATUS1 0x1A +#define ICM456XX_GYRO_CONFIG0 0x1C +#define ICM456XX_ACCEL_CONFIG0 0x1B +#define ICM456XX_PWR_MGMT0 0x10 + +// Register map IPREG_TOP1 +#define ICM456XX_RA_SREG_CTRL 0xA267 // To access register in IPREG_TOP1, add base address 0xA200 + offset + +// SREG_CTRL - 0x67 +#define ICM456XX_SREG_DATA_ENDIAN_SEL_LITTLE (0 << 1) +#define ICM456XX_SREG_DATA_ENDIAN_SEL_BIG (1 << 1) // not working set SREG_CTRL regiser + +// MGMT0 - 0x10 - Gyro +#define ICM456XX_GYRO_MODE_OFF (0x00 << 2) +#define ICM456XX_GYRO_MODE_STANDBY (0x01 << 2) +#define ICM456XX_GYRO_MODE_LP (0x02 << 2) // Low Power Mode +#define ICM456XX_GYRO_MODE_LN (0x03 << 2) // Low Noise Mode + +// MGMT0 - 0x10 - Accel +#define ICM456XX_ACCEL_MODE_OFF (0x00) +#define ICM456XX_ACCEL_MODE_OFF2 (0x01) +#define ICM456XX_ACCEL_MODE_LP (0x02) // Low Power Mode +#define ICM456XX_ACCEL_MODE_LN (0x03) // Low Noise Mode + +// INT1_CONFIG0 - 0x16 +#define ICM456XX_INT1_STATUS_EN_RESET_DONE (1 << 7) +#define ICM456XX_INT1_STATUS_EN_AUX1_AGC_RDY (1 << 6) +#define ICM456XX_INT1_STATUS_EN_AP_AGC_RDY (1 << 5) +#define ICM456XX_INT1_STATUS_EN_AP_FSYNC (1 << 4) +#define ICM456XX_INT1_STATUS_EN_AUX1_DRDY (1 << 3) +#define ICM456XX_INT1_STATUS_EN_DRDY (1 << 2) +#define ICM456XX_INT1_STATUS_EN_FIFO_THS (1 << 1) +#define ICM456XX_INT1_STATUS_EN_FIFO_FULL (1 << 0) + +// INT1_CONFIG2 - 0x18 +#define ICM456XX_INT1_DRIVE_CIRCUIT_PP (0 << 2) +#define ICM456XX_INT1_DRIVE_CIRCUIT_OD (1 << 2) +#define ICM456XX_INT1_MODE_PULSED (0 << 1) +#define ICM456XX_INT1_MODE_LATCHED (1 << 1) +#define ICM456XX_INT1_POLARITY_ACTIVE_LOW (0 << 0) +#define ICM456XX_INT1_POLARITY_ACTIVE_HIGH (1 << 0) + +// INT1_STATUS0 - 0x19 +#define ICM456XX_INT1_STATUS_RESET_DONE (1 << 7) +#define ICM456XX_INT1_STATUS_AUX1_AGC_RDY (1 << 6) +#define ICM456XX_INT1_STATUS_AP_AGC_RDY (1 << 5) +#define ICM456XX_INT1_STATUS_AP_FSYNC (1 << 4) +#define ICM456XX_INT1_STATUS_AUX1_DRDY (1 << 3) +#define ICM456XX_INT1_STATUS_DRDY (1 << 2) +#define ICM456XX_INT1_STATUS_FIFO_THS (1 << 1) +#define ICM456XX_INT1_STATUS_FIFO_FULL (1 << 0) + +// REG_MISC2 - 0x7F +#define ICM456XX_SOFT_RESET (1 << 1) +#define ICM456XX_RESET_TIMEOUT_US 20000 // 20 ms + +#define ICM456XX_ACCEL_DATA_X1_UI 0x00 +#define ICM456XX_GYRO_DATA_X1_UI 0x06 + +// ACCEL_CONFIG0 - 0x1B +#define ICM456XX_ACCEL_FS_SEL_32G (0x00 << 4) +#define ICM456XX_ACCEL_FS_SEL_16G (0x01 << 4) +#define ICM456XX_ACCEL_FS_SEL_8G (0x02 << 4) +#define ICM456XX_ACCEL_FS_SEL_4G (0x03 << 4) +#define ICM456XX_ACCEL_FS_SEL_2G (0x04 << 4) + +// ACCEL_CONFIG0 - 0x1B +#define ICM456XX_ACCEL_ODR_6K4_LN 0x03 +#define ICM456XX_ACCEL_ODR_3K2_LN 0x04 +#define ICM456XX_ACCEL_ODR_1K6_LN 0x05 +#define ICM456XX_ACCEL_ODR_800_LN 0x06 +#define ICM456XX_ACCEL_ODR_400_LP_LN 0x07 +#define ICM456XX_ACCEL_ODR_200_LP_LN 0x08 +#define ICM456XX_ACCEL_ODR_100_LP_LN 0x09 +#define ICM456XX_ACCEL_ODR_50_LP_LN 0x0A +#define ICM456XX_ACCEL_ODR_25_LP_LN 0x0B +#define ICM456XX_ACCEL_ODR_12_5_LP_LN 0x0C +#define ICM456XX_ACCEL_ODR_6_25_LP 0x0D +#define ICM456XX_ACCEL_ODR_3_125_LP 0x0E +#define ICM456XX_ACCEL_ODR_1_5625_LP 0x0F + +// GYRO_CONFIG0 - 0x1C +#define ICM456XX_GYRO_FS_SEL_4000DPS (0x00 << 4) +#define ICM456XX_GYRO_FS_SEL_2000DPS (0x01 << 4) +#define ICM456XX_GYRO_FS_SEL_1000DPS (0x02 << 4) +#define ICM456XX_GYRO_FS_SEL_500DPS (0x03 << 4) +#define ICM456XX_GYRO_FS_SEL_250DPS (0x04 << 4) +#define ICM456XX_GYRO_FS_SEL_125DPS (0x05 << 4) +#define ICM456XX_GYRO_FS_SEL_62_5DPS (0x06 << 4) +#define ICM456XX_GYRO_FS_SEL_31_25DPS (0x07 << 4) +#define ICM456XX_GYRO_FS_SEL_15_625DPS (0x08 << 4) + +// GYRO_CONFIG0 - 0x1C +#define ICM456XX_GYRO_ODR_6K4_LN 0x03 +#define ICM456XX_GYRO_ODR_3K2_LN 0x04 +#define ICM456XX_GYRO_ODR_1K6_LN 0x05 +#define ICM456XX_GYRO_ODR_800_LN 0x06 +#define ICM456XX_GYRO_ODR_400_LP_LN 0x07 +#define ICM456XX_GYRO_ODR_200_LP_LN 0x08 +#define ICM456XX_GYRO_ODR_100_LP_LN 0x09 +#define ICM456XX_GYRO_ODR_50_LP_LN 0x0A +#define ICM456XX_GYRO_ODR_25_LP_LN 0x0B +#define ICM456XX_GYRO_ODR_12_5_LP_LN 0x0C +#define ICM456XX_GYRO_ODR_6_25_LP 0x0D +#define ICM456XX_GYRO_ODR_3_125_LP 0x0E +#define ICM456XX_GYRO_ODR_1_5625_LP 0x0F + +// Accel IPREG_SYS2_REG_123 - 0x7B +#define ICM456XX_SRC_CTRL_AAF_ENABLE_BIT (1 << 0) // Anti-Alias Filter - AAF +#define ICM456XX_SRC_CTRL_INTERP_ENABLE_BIT (1 << 1) // Interpolator + +// IPREG_SYS2_REG_123 - 0x7B +#define ICM456XX_ACCEL_SRC_CTRL_IREG_ADDR 0xA57B // To access register in IPREG_SYS2, add base address 0xA500 + offset + +// IPREG_SYS1_REG_166 - 0xA6 +#define ICM456XX_GYRO_SRC_CTRL_IREG_ADDR 0xA4A6 // To access register in IPREG_SYS1, add base address 0xA400 + offset + +// HOST INDIRECT ACCESS REGISTER (IREG) +#define ICM456XX_REG_IREG_ADDR_15_8 0x7C +#define ICM456XX_REG_IREG_ADDR_7_0 0x7D +#define ICM456XX_REG_IREG_DATA 0x7E + + +// IPREG_SYS1_REG_172 - 0xAC +#define ICM456XX_GYRO_UI_LPF_CFG_IREG_ADDR 0xA4AC // To access register in IPREG_SYS1, add base address 0xA400 + offset + +// LPF UI - 0xAC PREG_SYS1_REG_172 (bits 2:0) +#define ICM456XX_GYRO_UI_LPFBW_BYPASS 0x00 +#define ICM456XX_GYRO_UI_LPFBW_ODR_DIV_4 0x01 // 1600 Hz ODR = 6400 Hz: +#define ICM456XX_GYRO_UI_LPFBW_ODR_DIV_8 0x02 // 800 Hz ODR = 6400 Hz: +#define ICM456XX_GYRO_UI_LPFBW_ODR_DIV_16 0x03 // 400 Hz ODR = 6400 Hz: +#define ICM456XX_GYRO_UI_LPFBW_ODR_DIV_32 0x04 // 200 Hz ODR = 6400 Hz +#define ICM456XX_GYRO_UI_LPFBW_ODR_DIV_64 0x05 // 100 Hz ODR = 6400 Hz +#define ICM456XX_GYRO_UI_LPFBW_ODR_DIV_128 0x06 // 50 Hz ODR = 6400 Hz + +// IPREG_SYS2_REG_131 - 0x83 +#define ICM456XX_ACCEL_UI_LPF_CFG_IREG_ADDR 0xA583 // To access register in IPREG_SYS2, add base address 0xA500 + offset + +// Accel UI path LPF - 0x83 IPREG_SYS2_REG_131 (bits 2:0) +#define ICM456XX_ACCEL_UI_LPFBW_BYPASS 0x00 +#define ICM456XX_ACCEL_UI_LPFBW_ODR_DIV_4 0x01 // 400 Hz ODR = 1600 Hz: +#define ICM456XX_ACCEL_UI_LPFBW_ODR_DIV_8 0x02 // 200 Hz ODR = 1600 Hz: +#define ICM456XX_ACCEL_UI_LPFBW_ODR_DIV_16 0x03 // 100 Hz ODR = 1600 Hz: +#define ICM456XX_ACCEL_UI_LPFBW_ODR_DIV_32 0x04 // 50 Hz ODR = 1600 Hz +#define ICM456XX_ACCEL_UI_LPFBW_ODR_DIV_64 0x05 // 25 Hz ODR = 1600 Hz +#define ICM456XX_ACCEL_UI_LPFBW_ODR_DIV_128 0x06 // 12.5 Hz ODR = 1600 Hz + + +#ifndef ICM456XX_CLOCK +// Default: 24 MHz max SPI frequency +#define ICM456XX_MAX_SPI_CLK_HZ 24000000 +#else +#define ICM456XX_MAX_SPI_CLK_HZ ICM456XX_CLOCK +#endif + +#define HZ_TO_US(hz) ((int32_t)((1000 * 1000) / (hz))) + +#define ICM456XX_BIT_IREG_DONE (1 << 0) + +#define ICM456XX_DATA_LENGTH 6 // 3 axes * 2 bytes per axis +#define ICM456XX_SPI_BUFFER_SIZE (1 + ICM456XX_DATA_LENGTH) // 1 byte register + 6 bytes data + +static uint8_t getGyroLpfConfig(const gyroHardwareLpf_e hardwareLpf) +{ + switch (hardwareLpf) { + case GYRO_HARDWARE_LPF_NORMAL: + return ICM456XX_GYRO_UI_LPFBW_ODR_DIV_32; + case GYRO_HARDWARE_LPF_OPTION_1: + return ICM456XX_GYRO_UI_LPFBW_ODR_DIV_16; + case GYRO_HARDWARE_LPF_OPTION_2: + return ICM456XX_GYRO_UI_LPFBW_ODR_DIV_8; +#ifdef USE_GYRO_DLPF_EXPERIMENTAL + case GYRO_HARDWARE_LPF_EXPERIMENTAL: + return ICM456XX_GYRO_UI_LPFBW_ODR_DIV_4; +#endif + default: + return ICM456XX_GYRO_UI_LPFBW_BYPASS; + } +} + +/** + * @brief This function follows the IREG WRITE procedure (Section 14.1-14.4 of the datasheet) + * using indirect addressing via IREG_ADDR_15_8, IREG_ADDR_7_0, and IREG_DATA registers. + * After writing, an internal operation transfers the data to the target IREG address. + * Ensures compliance with the required minimum time gap and checks the IREG_DONE bit. + * + * @param dev Pointer to the SPI device structure. + * @param reg 16-bit internal IREG register address. + * @param value Value to be written to the register. + * @return true if the write was successful + */ +static bool icm456xx_write_ireg(const extDevice_t *dev, uint16_t reg, uint8_t value) +{ + if (ARMING_FLAG(ARMED)) { + return false; // IREG write not allowed when armed + } + + const uint8_t msb = (reg >> 8) & 0xFF; + const uint8_t lsb = reg & 0xFF; + + spiWriteReg(dev, ICM456XX_REG_IREG_ADDR_15_8, msb); + spiWriteReg(dev, ICM456XX_REG_IREG_ADDR_7_0, lsb); + spiWriteReg(dev, ICM456XX_REG_IREG_DATA, value); + + // Check IREG_DONE (bit 0 of REG_MISC2 = 0x7F) + for (int i = 0; i < 100; i++) { + const uint8_t misc2 = spiReadRegMsk(dev, ICM456XX_REG_MISC2); + if (misc2 & ICM456XX_BIT_IREG_DONE) { + return true; + } + delayMicroseconds(10); + } + + return false; // timeout +} + +static inline void icm456xx_enableAAFandInterpolator(const extDevice_t *dev, uint16_t reg, bool enableAAF, bool enableInterp) +{ + const uint8_t value = (enableAAF ? ICM456XX_SRC_CTRL_AAF_ENABLE_BIT : 0) + | (enableInterp ? ICM456XX_SRC_CTRL_INTERP_ENABLE_BIT : 0); + icm456xx_write_ireg(dev, reg, value); +} + +static bool icm456xx_configureLPF(const extDevice_t *dev, uint16_t reg, uint8_t lpfDiv) +{ + if (lpfDiv > 0x07) { + return false; + } + + return icm456xx_write_ireg(dev, reg, lpfDiv & 0x07); +} + +static void icm456xx_enableSensors(const extDevice_t *dev, bool enable) +{ + uint8_t value = enable + ? (ICM456XX_GYRO_MODE_LN | ICM456XX_ACCEL_MODE_LN) + : (ICM456XX_GYRO_MODE_OFF | ICM456XX_ACCEL_MODE_OFF); + + spiWriteReg(dev, ICM456XX_PWR_MGMT0, value); +} + +void icm456xxAccInit(accDev_t *acc) +{ + const extDevice_t *dev = &acc->gyro->dev; + + spiWriteReg(dev, ICM456XX_REG_BANK_SEL, ICM456XX_BANK_0); + + switch (acc->mpuDetectionResult.sensor) { + case ICM_45686_SPI: + acc->acc_1G = 1024; // 32g scale = 1024 LSB/g + acc->gyro->accSampleRateHz = 1600; + spiWriteReg(dev, ICM456XX_ACCEL_CONFIG0, ICM456XX_ACCEL_FS_SEL_32G | ICM456XX_ACCEL_ODR_1K6_LN); + break; + case ICM_45605_SPI: + default: + acc->acc_1G = 2048; // 16g scale = 2048 LSB/g + acc->gyro->accSampleRateHz = 1600; + spiWriteReg(dev, ICM456XX_ACCEL_CONFIG0, ICM456XX_ACCEL_FS_SEL_16G | ICM456XX_ACCEL_ODR_1K6_LN); + break; + } + + // Enable Anti-Alias (AAF) Filter and Interpolator for Accel + icm456xx_enableAAFandInterpolator(dev, ICM456XX_ACCEL_SRC_CTRL_IREG_ADDR, true, true); + + // Set the Accel UI LPF bandwidth cut-off + icm456xx_configureLPF(dev, ICM456XX_ACCEL_UI_LPF_CFG_IREG_ADDR, ICM456XX_ACCEL_UI_LPFBW_ODR_DIV_8); +} + +void icm456xxGyroInit(gyroDev_t *gyro) +{ + const extDevice_t *dev = &gyro->dev; + + spiSetClkDivisor(dev, spiCalculateDivider(ICM456XX_MAX_SPI_CLK_HZ)); + + mpuGyroInit(gyro); + + spiWriteReg(dev, ICM456XX_REG_BANK_SEL, ICM456XX_BANK_0); + + icm456xx_enableSensors(dev, true); + + // Enable Anti-Alias (AAF) Filter and Interpolator for Gyro + icm456xx_enableAAFandInterpolator(dev, ICM456XX_GYRO_SRC_CTRL_IREG_ADDR, true, true); + + // Set the Gyro UI LPF bandwidth cut-off + icm456xx_configureLPF(dev, ICM456XX_GYRO_UI_LPF_CFG_IREG_ADDR, getGyroLpfConfig(gyroConfig()->gyro_hardware_lpf)); + + switch (gyro->mpuDetectionResult.sensor) { + case ICM_45686_SPI: + case ICM_45605_SPI: + default: + gyro->scale = GYRO_SCALE_2000DPS; + gyro->gyroRateKHz = GYRO_RATE_6400_Hz; + gyro->gyroSampleRateHz = 6400; + spiWriteReg(dev, ICM456XX_GYRO_CONFIG0, ICM456XX_GYRO_FS_SEL_2000DPS | ICM456XX_GYRO_ODR_6K4_LN); + break; + } + + gyro->gyroShortPeriod = clockMicrosToCycles(HZ_TO_US(gyro->gyroSampleRateHz)); + + spiWriteReg(dev, ICM456XX_INT1_CONFIG2, ICM456XX_INT1_MODE_PULSED | ICM456XX_INT1_DRIVE_CIRCUIT_PP | + ICM456XX_INT1_POLARITY_ACTIVE_HIGH); + + spiWriteReg(dev, ICM456XX_INT1_CONFIG0, ICM456XX_INT1_STATUS_EN_DRDY); + +} + +uint8_t icm456xxSpiDetect(const extDevice_t *dev) +{ + uint8_t icmDetected = MPU_NONE; + uint8_t attemptsRemaining = 20; + uint32_t waited_us = 0; + + spiWriteReg(dev, ICM456XX_REG_BANK_SEL, ICM456XX_BANK_0); + + // Soft reset + spiWriteReg(dev, ICM456XX_REG_MISC2, ICM456XX_SOFT_RESET); + + // Wait for reset to complete (bit 1 of REG_MISC2 becomes 0) + while ((spiReadRegMsk(dev, ICM456XX_REG_MISC2) & ICM456XX_SOFT_RESET) != 0) { + delayMicroseconds(10); + waited_us += 10; + + if (waited_us >= ICM456XX_RESET_TIMEOUT_US) { + return MPU_NONE; + } + } + + do { + const uint8_t whoAmI = spiReadRegMsk(dev, ICM456XX_WHO_AM_REGISTER); + switch (whoAmI) { + case ICM45686_WHO_AM_I_CONST: + icmDetected = ICM_45686_SPI; + break; + case ICM45605_WHO_AM_I_CONST: + icmDetected = ICM_45605_SPI; + break; + default: + icmDetected = MPU_NONE; + break; + } + + } while (icmDetected == MPU_NONE && attemptsRemaining--); + + return icmDetected; + +} + +bool icm456xxAccReadSPI(accDev_t *acc) +{ + switch (acc->gyro->gyroModeSPI) { + case GYRO_EXTI_INT: + case GYRO_EXTI_NO_INT: + { +#ifdef USE_DMA + if (spiUseDMA(&acc->gyro->dev)) { + acc->gyro->dev.txBuf[0] = ICM456XX_ACCEL_DATA_X1_UI | 0x80; + + busSegment_t segments[] = { + {.u.buffers = {NULL, NULL}, ICM456XX_SPI_BUFFER_SIZE, true, NULL}, + {.u.link = {NULL, NULL}, 0, true, NULL}, + }; + memset(&acc->gyro->dev.txBuf[1], 0xFF, 6); + segments[0].u.buffers.txData = acc->gyro->dev.txBuf; + segments[0].u.buffers.rxData = &acc->gyro->dev.rxBuf[1]; + spiSequence(&acc->gyro->dev, &segments[0]); + + // Wait for completion + spiWait(&acc->gyro->dev); + + } else +#else + { + // Interrupts are present, but no DMA. Non-DMA read + uint8_t raw[ICM456XX_DATA_LENGTH]; + const bool ack = spiReadRegMskBufRB(&acc->gyro->dev, ICM456XX_ACCEL_DATA_X1_UI, raw, ICM456XX_DATA_LENGTH); + if (!ack) { + return false; + } + + acc->ADCRaw[X] = (int16_t)((raw[1] << 8) | raw[0]); + acc->ADCRaw[Y] = (int16_t)((raw[3] << 8) | raw[2]); + acc->ADCRaw[Z] = (int16_t)((raw[5] << 8) | raw[4]); + + } +#endif + break; + } + + + case GYRO_EXTI_INT_DMA: + { + // If read was triggered in interrupt don't bother waiting. The worst that could happen is that we pick + // up an old value. + + // This data was read from the gyro, which is the same SPI device as the acc + acc->ADCRaw[X] = (int16_t)((acc->gyro->dev.rxBuf[2] << 8) | acc->gyro->dev.rxBuf[1]); + acc->ADCRaw[Y] = (int16_t)((acc->gyro->dev.rxBuf[4] << 8) | acc->gyro->dev.rxBuf[3]); + acc->ADCRaw[Z] = (int16_t)((acc->gyro->dev.rxBuf[6] << 8) | acc->gyro->dev.rxBuf[5]); + break; + } + + default: + break; + } + + return true; +} + +bool icm456xxSpiAccDetect(accDev_t *acc) +{ + switch (acc->mpuDetectionResult.sensor) { + case ICM_45686_SPI: + case ICM_45605_SPI: + acc->initFn = icm456xxAccInit; + acc->readFn = icm456xxAccReadSPI; + break; + default: + return false; + } + + return true; +} + +bool icm456xxGyroReadSPI(gyroDev_t *gyro) +{ + switch (gyro->gyroModeSPI) { + case GYRO_EXTI_INIT: + { + // Initialise the tx buffer to all 0xff + memset(gyro->dev.txBuf, 0xff, ICM456XX_SPI_BUFFER_SIZE); + + gyro->gyroDmaMaxDuration = 0; // INT gyroscope always calls that data is ready. We can read immediately +#ifdef USE_DMA + if (spiUseDMA(&gyro->dev)) { + gyro->dev.callbackArg = (uint32_t)gyro; + gyro->dev.txBuf[0] = ICM456XX_GYRO_DATA_X1_UI | 0x80; + gyro->segments[0].len = ICM456XX_SPI_BUFFER_SIZE; + gyro->segments[0].callback = mpuIntCallback; + gyro->segments[0].u.buffers.txData = gyro->dev.txBuf; + gyro->segments[0].u.buffers.rxData = gyro->dev.rxBuf; + gyro->segments[0].negateCS = true; + gyro->gyroModeSPI = GYRO_EXTI_INT_DMA; + } else +#endif + { + // Interrupts are present, but no DMA. Non-DMA read + uint8_t raw[ICM456XX_DATA_LENGTH]; + const bool ack = spiReadRegMskBufRB(&gyro->dev, ICM456XX_GYRO_DATA_X1_UI, raw, ICM456XX_DATA_LENGTH); + if (!ack) { + return false; + } + + gyro->gyroADCRaw[X] = (int16_t)((raw[1] << 8) | raw[0]); + gyro->gyroADCRaw[Y] = (int16_t)((raw[3] << 8) | raw[2]); + gyro->gyroADCRaw[Z] = (int16_t)((raw[5] << 8) | raw[4]); + gyro->gyroModeSPI = GYRO_EXTI_INT; + } + + break; + } + + case GYRO_EXTI_NO_INT: + { + gyro->dev.txBuf[0] = ICM456XX_GYRO_DATA_X1_UI | 0x80; + + busSegment_t segments[] = { + {.u.buffers = {NULL, NULL}, ICM456XX_SPI_BUFFER_SIZE, true, NULL}, + {.u.link = {NULL, NULL}, 0, true, NULL}, + }; + memset(&gyro->dev.txBuf[1], 0xFF, 6); + segments[0].u.buffers.txData = gyro->dev.txBuf; + segments[0].u.buffers.rxData = gyro->dev.rxBuf; + + spiSequence(&gyro->dev, &segments[0]); + + // Wait for completion + spiWait(&gyro->dev); + + gyro->gyroADCRaw[X] = (int16_t)((gyro->dev.rxBuf[2] << 8) | gyro->dev.rxBuf[1]); + gyro->gyroADCRaw[Y] = (int16_t)((gyro->dev.rxBuf[4] << 8) | gyro->dev.rxBuf[3]); + gyro->gyroADCRaw[Z] = (int16_t)((gyro->dev.rxBuf[6] << 8) | gyro->dev.rxBuf[5]); + break; + } + + case GYRO_EXTI_INT_DMA: + { + + // If read was triggered in interrupt don't bother waiting. The worst that could happen is that we pick + // up an old value. + gyro->gyroADCRaw[X] = (int16_t)((gyro->dev.rxBuf[2] << 8) | gyro->dev.rxBuf[1]); + gyro->gyroADCRaw[Y] = (int16_t)((gyro->dev.rxBuf[4] << 8) | gyro->dev.rxBuf[3]); + gyro->gyroADCRaw[Z] = (int16_t)((gyro->dev.rxBuf[6] << 8) | gyro->dev.rxBuf[5]); + break; + } + + default: + break; + } + + return true; +} + + +bool icm456xxSpiGyroDetect(gyroDev_t *gyro) +{ + switch (gyro->mpuDetectionResult.sensor) { + case ICM_45686_SPI: + case ICM_45605_SPI: + gyro->initFn = icm456xxGyroInit; + gyro->readFn = icm456xxGyroReadSPI; + break; + default: + return false; + } + + return true; +} + +#endif // USE_ACCGYRO_ICM45686 || USE_ACCGYRO_ICM45605 diff --git a/src/main/drivers/accgyro/accgyro_spi_icm456xx.h b/src/main/drivers/accgyro/accgyro_spi_icm456xx.h new file mode 100644 index 0000000000..db0be2a180 --- /dev/null +++ b/src/main/drivers/accgyro/accgyro_spi_icm456xx.h @@ -0,0 +1,32 @@ +/* + * This file is part of Betaflight. + * + * Betaflight is free software. You can redistribute this software + * and/or modify this software under the terms of the GNU General + * Public License as published by the Free Software Foundation, + * either version 3 of the License, or (at your option) any later + * version. + * + * Betaflight is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * See the GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this software. + * + * If not, see . + */ + +#pragma once + +#include "drivers/bus.h" + +void icm456xxAccInit(accDev_t *acc); +void icm456xxGyroInit(gyroDev_t *gyro); + +uint8_t icm456xxSpiDetect(const extDevice_t *dev); + +bool icm456xxSpiAccDetect(accDev_t *acc); +bool icm456xxSpiGyroDetect(gyroDev_t *gyro); diff --git a/src/main/drivers/accgyro/gyro_sync.c b/src/main/drivers/accgyro/gyro_sync.c index 48ca30039c..d4223d441d 100644 --- a/src/main/drivers/accgyro/gyro_sync.c +++ b/src/main/drivers/accgyro/gyro_sync.c @@ -83,6 +83,12 @@ uint16_t gyroSetSampleRate(gyroDev_t *gyro) accSampleRateHz = 833; break; #endif + case ICM_45686_SPI: + case ICM_45605_SPI: + gyro->gyroRateKHz = GYRO_RATE_6400_Hz; + gyroSampleRateHz = 6400; + accSampleRateHz = 1600; + break; default: gyro->gyroRateKHz = GYRO_RATE_8_kHz; gyroSampleRateHz = 8000; diff --git a/src/main/sensors/acceleration.h b/src/main/sensors/acceleration.h index 2f28e6879f..2c4706b9ed 100644 --- a/src/main/sensors/acceleration.h +++ b/src/main/sensors/acceleration.h @@ -51,6 +51,8 @@ typedef enum { ACC_LSM6DSO, ACC_LSM6DSV16X, ACC_IIM42653, + ACC_ICM45605, + ACC_ICM45686, ACC_VIRTUAL } accelerationSensor_e; diff --git a/src/main/sensors/acceleration_init.c b/src/main/sensors/acceleration_init.c index 6624253658..0d59e46858 100644 --- a/src/main/sensors/acceleration_init.c +++ b/src/main/sensors/acceleration_init.c @@ -47,6 +47,7 @@ #include "drivers/accgyro/accgyro_spi_icm20649.h" #include "drivers/accgyro/accgyro_spi_icm20689.h" #include "drivers/accgyro/accgyro_spi_icm426xx.h" +#include "drivers/accgyro/accgyro_spi_icm456xx.h" #include "drivers/accgyro/accgyro_spi_lsm6dso.h" #include "drivers/accgyro/accgyro_spi_lsm6dsv16x.h" @@ -240,6 +241,26 @@ retry: FALLTHROUGH; #endif +#if defined(USE_ACCGYRO_ICM45686) || defined(USE_ACCGYRO_ICM45605) + case ACC_ICM45686: + case ACC_ICM45605: + if (icm456xxSpiAccDetect(dev)) { + switch (dev->mpuDetectionResult.sensor) { + case ICM_45686_SPI: + accHardware = ACC_ICM45686; + break; + case ICM_45605_SPI: + accHardware = ACC_ICM45605; + break; + default: + accHardware = ACC_NONE; + break; + } + break; + } + FALLTHROUGH; +#endif + #ifdef USE_ACCGYRO_BMI160 case ACC_BMI160: if (bmi160SpiAccDetect(dev)) { diff --git a/src/main/sensors/gyro_init.c b/src/main/sensors/gyro_init.c index 151d9f8aeb..568386e560 100644 --- a/src/main/sensors/gyro_init.c +++ b/src/main/sensors/gyro_init.c @@ -47,6 +47,7 @@ #include "drivers/accgyro/accgyro_spi_icm20649.h" #include "drivers/accgyro/accgyro_spi_icm20689.h" #include "drivers/accgyro/accgyro_spi_icm426xx.h" +#include "drivers/accgyro/accgyro_spi_icm456xx.h" #include "drivers/accgyro/accgyro_spi_l3gd20.h" #include "drivers/accgyro/accgyro_spi_lsm6dso.h" @@ -318,6 +319,8 @@ void gyroInitSensor(gyroSensor_t *gyroSensor, const gyroDeviceConfig_t *config) case GYRO_ICM42688P: case GYRO_IIM42653: case GYRO_ICM42605: + case GYRO_ICM45686: + case GYRO_ICM45605: gyroSensor->gyroDev.gyroHasOverflowProtection = true; break; @@ -454,6 +457,27 @@ STATIC_UNIT_TESTED gyroHardware_e gyroDetect(gyroDev_t *dev) FALLTHROUGH; #endif +#if defined(USE_ACCGYRO_ICM45686) || defined(USE_ACCGYRO_ICM45605) + case GYRO_ICM45686: + case GYRO_ICM45605: + if (icm456xxSpiGyroDetect(dev)) { + switch (dev->mpuDetectionResult.sensor) { + case ICM_45686_SPI: + gyroHardware = GYRO_ICM45686; + break; + case ICM_45605_SPI: + gyroHardware = GYRO_ICM45605; + break; + + default: + gyroHardware = GYRO_NONE; + break; + } + break; + } + FALLTHROUGH; +#endif + #ifdef USE_ACCGYRO_BMI160 case GYRO_BMI160: if (bmi160SpiGyroDetect(dev)) { diff --git a/src/main/target/common_post.h b/src/main/target/common_post.h index cf35e11de9..6a732310cf 100644 --- a/src/main/target/common_post.h +++ b/src/main/target/common_post.h @@ -102,6 +102,8 @@ && !defined(USE_ACC_SPI_ICM20689) \ && !defined(USE_ACC_SPI_ICM42605) \ && !defined(USE_ACC_SPI_ICM42688P) \ + && !defined(USE_ACCGYRO_ICM45686) \ + && !defined(USE_ACCGYRO_ICM45605) \ && !defined(USE_ACCGYRO_LSM6DSO) \ && !defined(USE_ACCGYRO_LSM6DSV16X) \ && !defined(USE_ACC_SPI_MPU6000) \ @@ -122,6 +124,8 @@ && !defined(USE_GYRO_SPI_ICM20689) \ && !defined(USE_GYRO_SPI_ICM42605) \ && !defined(USE_GYRO_SPI_ICM42688P) \ + && !defined(USE_ACCGYRO_ICM45686) \ + && !defined(USE_ACCGYRO_ICM45605) \ && !defined(USE_ACCGYRO_LSM6DSO) \ && !defined(USE_ACCGYRO_LSM6DSV16X) \ && !defined(USE_GYRO_SPI_MPU6000) \ @@ -468,8 +472,9 @@ // Generate USE_SPI_GYRO or USE_I2C_GYRO #if defined(USE_GYRO_SPI_ICM20689) || defined(USE_GYRO_SPI_MPU6000) || defined(USE_GYRO_SPI_MPU6500) || defined(USE_GYRO_SPI_MPU9250) \ - || defined(USE_GYRO_L3GD20) || defined(USE_GYRO_SPI_ICM42605) || defined(USE_GYRO_SPI_ICM42688P) || defined(USE_ACCGYRO_IIM42653) \ - || defined(USE_ACCGYRO_BMI160) || defined(USE_ACCGYRO_BMI270) || defined(USE_ACCGYRO_LSM6DSV16X) || defined(USE_ACCGYRO_LSM6DSO) + || defined(USE_GYRO_L3GD20) || defined(USE_GYRO_SPI_ICM42605) || defined(USE_GYRO_SPI_ICM42688P) || defined(USE_ACCGYRO_ICM45686) \ + || defined(USE_ACCGYRO_ICM45605) || defined(USE_ACCGYRO_IIM42653) || defined(USE_ACCGYRO_BMI160) || defined(USE_ACCGYRO_BMI270) \ + || defined(USE_ACCGYRO_LSM6DSV16X) || defined(USE_ACCGYRO_LSM6DSO) #ifndef USE_SPI_GYRO #define USE_SPI_GYRO #endif diff --git a/src/main/target/common_pre.h b/src/main/target/common_pre.h index b616303190..d43b30aaaf 100644 --- a/src/main/target/common_pre.h +++ b/src/main/target/common_pre.h @@ -114,6 +114,8 @@ #define USE_ACCGYRO_BMI270 #define USE_GYRO_SPI_ICM42605 #define USE_GYRO_SPI_ICM42688P +#define USE_ACCGYRO_ICM45686 +#define USE_ACCGYRO_ICM45605 #define USE_ACCGYRO_IIM42653 #define USE_ACC_SPI_ICM42605 #define USE_ACC_SPI_ICM42688P From 77ceea93e4bb1e657de34e22c5b81c564bdb9d09 Mon Sep 17 00:00:00 2001 From: "Git bot (blckmn)" Date: Tue, 27 May 2025 06:25:03 +0000 Subject: [PATCH 214/244] Auto updated submodule references [27-05-2025] --- src/config | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/config b/src/config index 22dc66d412..5947a7af8e 160000 --- a/src/config +++ b/src/config @@ -1 +1 @@ -Subproject commit 22dc66d412b21f9cbf78fe481b7a3c158c46ca68 +Subproject commit 5947a7af8eed234fc9e1ad17294819ab966f5929 From dd0a37b41c4c3f24482fdd1721448974015f56c9 Mon Sep 17 00:00:00 2001 From: Steve Evans Date: Tue, 27 May 2025 18:02:24 +0100 Subject: [PATCH 215/244] Only wait for ESC to recognise DSHOT signal once at startup (#14408) * Only wait for ESC to recognise DSHOT signal once at startup * Use cmpTimeMs to compare time expressed in ms --- src/main/common/time.h | 1 + src/main/drivers/dshot_command.c | 15 ++++++++++++++- 2 files changed, 15 insertions(+), 1 deletion(-) diff --git a/src/main/common/time.h b/src/main/common/time.h index 33121739ab..9bf3b9c190 100644 --- a/src/main/common/time.h +++ b/src/main/common/time.h @@ -46,6 +46,7 @@ typedef uint32_t timeUs_t; #define SECONDS_PER_MINUTE 60.0f static inline timeDelta_t cmpTimeUs(timeUs_t a, timeUs_t b) { return (timeDelta_t)(a - b); } +static inline timeDelta_t cmpTimeMs(timeMs_t a, timeMs_t b) { return (timeDelta_t)(a - b); } static inline int32_t cmpTimeCycles(uint32_t a, uint32_t b) { return (int32_t)(a - b); } #define FORMATTED_DATE_TIME_BUFSIZE 30 diff --git a/src/main/drivers/dshot_command.c b/src/main/drivers/dshot_command.c index 90f80185d8..a2fa5da17c 100644 --- a/src/main/drivers/dshot_command.c +++ b/src/main/drivers/dshot_command.c @@ -149,7 +149,20 @@ static bool allMotorsAreIdle(void) bool dshotStreamingCommandsAreEnabled(void) { - return motorIsEnabled() && motorGetMotorEnableTimeMs() && millis() > motorGetMotorEnableTimeMs() + DSHOT_PROTOCOL_DETECTION_DELAY_MS; + static bool firstCommand = true; + bool goodMotorDetectDelay; + + if (firstCommand) { + goodMotorDetectDelay = motorGetMotorEnableTimeMs() && (cmpTimeMs(millis(), motorGetMotorEnableTimeMs()) > DSHOT_PROTOCOL_DETECTION_DELAY_MS); + + if (goodMotorDetectDelay) { + firstCommand = false; + } + } else { + goodMotorDetectDelay = true; + } + + return motorIsEnabled() && goodMotorDetectDelay; } static bool dshotCommandsAreEnabled(dshotCommandType_e commandType) From f217ba6d19e9d5361e205e1131b81d1d3df9ab06 Mon Sep 17 00:00:00 2001 From: cvetaevvitaliy Date: Tue, 27 May 2025 23:56:37 +0300 Subject: [PATCH 216/244] Implementation of the ICM-40609D gyroscope driver (#14367) * add icm40609d Co-authored-by: Mark Haslinghuis refactor include * add support for setting filters from config * set optimal settings for AAF * add settings DEC2 M2 filter for Gyro * set 3Rd hardware UI filters for Gyro&Accel * update comments filter order * set readFN for read SPI data via DMA, add INT1 to pulse mode, push-pull, active high * fix PR issue * revert INT1 POLARITY to ACTIVE HIGH * refactor icm40609GetAafParams * Update src/main/drivers/accgyro/accgyro_spi_icm40609.c Co-authored-by: coderabbitai[bot] <136622811+coderabbitai[bot]@users.noreply.github.com> * Update src/main/drivers/accgyro/accgyro_spi_icm40609.c * update link to datasheet * fix typo Co-authored-by: coderabbitai[bot] <136622811+coderabbitai[bot]@users.noreply.github.com> --------- Co-authored-by: Mark Haslinghuis Co-authored-by: coderabbitai[bot] <136622811+coderabbitai[bot]@users.noreply.github.com> --- mk/source.mk | 1 + src/main/cli/settings.c | 2 + src/main/drivers/accgyro/accgyro.h | 1 + src/main/drivers/accgyro/accgyro_mpu.c | 4 + src/main/drivers/accgyro/accgyro_mpu.h | 2 + .../drivers/accgyro/accgyro_spi_icm40609.c | 764 ++++++++++++++++++ .../drivers/accgyro/accgyro_spi_icm40609.h | 32 + src/main/sensors/acceleration.h | 1 + src/main/sensors/acceleration_init.c | 10 + src/main/sensors/gyro_init.c | 11 + src/main/target/common_post.h | 4 +- src/main/target/common_pre.h | 1 + 12 files changed, 832 insertions(+), 1 deletion(-) create mode 100644 src/main/drivers/accgyro/accgyro_spi_icm40609.c create mode 100644 src/main/drivers/accgyro/accgyro_spi_icm40609.h diff --git a/mk/source.mk b/mk/source.mk index 13e55fb4d6..ad3f7e4fc4 100644 --- a/mk/source.mk +++ b/mk/source.mk @@ -299,6 +299,7 @@ COMMON_SRC += \ drivers/accgyro/accgyro_spi_icm20689.c \ drivers/accgyro/accgyro_spi_icm426xx.c \ drivers/accgyro/accgyro_spi_icm456xx.c \ + drivers/accgyro/accgyro_spi_icm40609.c \ drivers/accgyro/accgyro_spi_l3gd20.c \ drivers/accgyro/accgyro_spi_lsm6dso.c \ drivers/accgyro/accgyro_spi_lsm6dso_init.c \ diff --git a/src/main/cli/settings.c b/src/main/cli/settings.c index 91e23d6d29..6fc140f4af 100644 --- a/src/main/cli/settings.c +++ b/src/main/cli/settings.c @@ -163,6 +163,7 @@ const char * const lookupTableAccHardware[] = { "IIM42653", "ICM45605", "ICM45686", + "ICM40609D", "VIRTUAL" }; @@ -189,6 +190,7 @@ const char * const lookupTableGyroHardware[] = { "IIM42653", "ICM45605", "ICM45686", + "ICM40609D", "VIRTUAL" }; diff --git a/src/main/drivers/accgyro/accgyro.h b/src/main/drivers/accgyro/accgyro.h index d8be175115..e969f92ec4 100644 --- a/src/main/drivers/accgyro/accgyro.h +++ b/src/main/drivers/accgyro/accgyro.h @@ -64,6 +64,7 @@ typedef enum { GYRO_IIM42653, GYRO_ICM45605, GYRO_ICM45686, + GYRO_ICM40609D, GYRO_VIRTUAL } gyroHardware_e; diff --git a/src/main/drivers/accgyro/accgyro_mpu.c b/src/main/drivers/accgyro/accgyro_mpu.c index 930028f0a3..f2a43ca6b6 100644 --- a/src/main/drivers/accgyro/accgyro_mpu.c +++ b/src/main/drivers/accgyro/accgyro_mpu.c @@ -58,6 +58,7 @@ #include "drivers/accgyro/accgyro_spi_l3gd20.h" #include "drivers/accgyro/accgyro_spi_lsm6dsv16x.h" #include "drivers/accgyro/accgyro_mpu.h" +#include "drivers/accgyro/accgyro_spi_icm40609.h" #include "pg/pg.h" #include "pg/gyrodev.h" @@ -377,6 +378,9 @@ static gyroSpiDetectFn_t gyroSpiDetectFnTable[] = { #endif #ifdef USE_GYRO_L3GD20 l3gd20Detect, +#endif +#ifdef USE_ACCGYRO_ICM40609D + icm40609SpiDetect, #endif NULL // Avoid an empty array }; diff --git a/src/main/drivers/accgyro/accgyro_mpu.h b/src/main/drivers/accgyro/accgyro_mpu.h index b72356ddef..20104d7fe2 100644 --- a/src/main/drivers/accgyro/accgyro_mpu.h +++ b/src/main/drivers/accgyro/accgyro_mpu.h @@ -49,6 +49,7 @@ #define ICM45605_WHO_AM_I_CONST (0xE5) #define IIM42653_WHO_AM_I_CONST (0x56) #define LSM6DSV16X_WHO_AM_I_CONST (0x70) +#define ICM40609_WHO_AM_I_CONST (0x3B) // RA = Register Address @@ -214,6 +215,7 @@ typedef enum { LSM6DSV16X_SPI, ICM_45605_SPI, ICM_45686_SPI, + ICM_40609_SPI } mpuSensor_e; typedef enum { diff --git a/src/main/drivers/accgyro/accgyro_spi_icm40609.c b/src/main/drivers/accgyro/accgyro_spi_icm40609.c new file mode 100644 index 0000000000..5ed6c8eb73 --- /dev/null +++ b/src/main/drivers/accgyro/accgyro_spi_icm40609.c @@ -0,0 +1,764 @@ +/* + * This file is part of Betaflight. + * + * Betaflight is free software. You can redistribute this software + * and/or modify this software under the terms of the GNU General + * Public License as published by the Free Software Foundation, + * either version 3 of the License, or (at your option) any later + * version. + * + * Betaflight is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * See the GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this software. + * + * If not, see . + */ + +#include +#include +#include +#include + +#include "platform.h" + +#if defined(USE_ACCGYRO_ICM40609D) + +#include "common/axis.h" +#include "common/maths.h" + +#include "drivers/accgyro/accgyro.h" +#include "drivers/accgyro/accgyro_mpu.h" +#include "drivers/accgyro/accgyro_spi_icm40609.h" +#include "drivers/bus_spi.h" +#include "drivers/exti.h" +#include "drivers/io.h" +#include "drivers/pwm_output.h" +#include "drivers/sensor.h" +#include "drivers/time.h" + +#include "fc/runtime_config.h" + +#include "sensors/gyro.h" +#include "pg/gyrodev.h" + +// Datasheet: https://invensense.tdk.com/wp-content/uploads/2022/07/DS-000330-ICM-40609-D-v1.2.pdf + +#define ICM40609_WHO_AM_I_REG 0x75 + +#define ICM40609_REG_BANK_SEL 0x76 + +#define ICM40609_USER_BANK_0 0x00 +#define ICM40609_USER_BANK_1 0x01 +#define ICM40609_USER_BANK_2 0x02 +#define ICM40609_USER_BANK_3 0x03 +#define ICM40609_USER_BANK_4 0x04 + +// Registers in BANK 0 +#define ICM40609_REG_INT_CONFIG 0x14 +#define ICM40609_REG_INTF_CONFIG0 0x4C +#define ICM40609_REG_PWR_MGMT0 0x4E +#define ICM40609_REG_GYRO_CONFIG0 0x4F +#define ICM40609_REG_ACCEL_CONFIG0 0x50 +#define ICM40609_REG_GYRO_CONFIG1 0x51 // Bandwidth of the temperature signal DLPF +#define ICM40609_REG_GYRO_ACCEL_CONFIG0 0x52 // Bandwidth for Gyro & Accel LPF +#define ICM40609_REG_GYRO_ACCEL_CONFIG1 0x53 // Bandwidth for Gyro & Accel LPF +#define ICM40609_REG_INT_CONFIG0 0x63 +#define ICM40609_REG_INT_CONFIG1 0x64 +#define ICM40609_REG_INT_SOURCE0 0x65 + +// Registers in BANK 1 +#define ICM40609_REG_GYRO_CONFIG_STATIC2 0x0B +#define ICM40609_REG_GYRO_CONFIG_STATIC3 0x0C +#define ICM40609_REG_GYRO_CONFIG_STATIC4 0x0D +#define ICM40609_REG_GYRO_CONFIG_STATIC5 0x0E +#define ICM40609_REG_GYRO_CONFIG_STATIC6 0x0F +#define ICM40609_REG_GYRO_CONFIG_STATIC7 0x10 +#define ICM40609_REG_GYRO_CONFIG_STATIC8 0x11 +#define ICM40609_REG_GYRO_CONFIG_STATIC9 0x12 +#define ICM40609_REG_GYRO_CONFIG_STATIC10 0x13 // gyro notch filter + +// Registers in BANK 2 +#define ICM40609_REG_ACCEL_CONFIG_STATIC2 0x03 +#define ICM40609_REG_ACCEL_CONFIG_STATIC3 0x04 +#define ICM40609_REG_ACCEL_CONFIG_STATIC4 0x05 + +// PWR_MGMT0_REG - 0x4E +#define ICM40609_TEMP_SENSOR_ENABLED (0 << 5) +#define ICM40609_TEMP_SENSOR_DISABLED (1 << 5) +#define ICM40609_IDLE (0 << 4) +#define ICM40609_RC_ON (1 << 4) + +// // PWR_MGMT0_REG - 0x4E bits [3:2] +#define ICM40609_GYRO_MODE_OFF (0 << 2) +#define ICM40609_GYRO_MODE_STANDBY (1 << 2) +#define ICM40609_GYRO_MODE_LN (3 << 2) + +// // PWR_MGMT0_REG - 0x4E bits [1:0] +#define ICM40609_ACCEL_MODE_OFF (0 << 0) // Of course, this is joke, but it's so easy to check bits orders in datasheet +#define ICM40609_ACCEL_MODE_PWR_OFF (1 << 0) +#define ICM40609_ACCEL_MODE_LP (2 << 0) +#define ICM40609_ACCEL_MODE_LN (3 << 0) + +// GYRO_CONFIG0_REG - 0x4F bits [7:5] +#define ICM40609_GYRO_FS_SEL_2000DPS (0 << 5) // default) +#define ICM40609_GYRO_FS_SEL_1000DPS (1 << 5) +#define ICM40609_GYRO_FS_SEL_500DPS (2 << 5) +#define ICM40609_GYRO_FS_SEL_250DPS (3 << 5) +#define ICM40609_GYRO_FS_SEL_125DPS (4 << 5) +#define ICM40609_GYRO_FS_SEL_62_5DPS (5 << 5) +#define ICM40609_GYRO_FS_SEL_31_25DPS (6 << 5) +#define ICM40609_GYRO_FS_SEL_15_625DPS (7 << 5) + +// GYRO_CONFIG0_REG - 0x4F bits [3:0] +#define ICM40609_GYRO_ODR_32KHZ 0x01 +#define ICM40609_GYRO_ODR_16KHZ 0x02 +#define ICM40609_GYRO_ODR_8KHZ 0x03 +#define ICM40609_GYRO_ODR_4KHZ 0x04 +#define ICM40609_GYRO_ODR_2KHZ 0x05 +#define ICM40609_GYRO_ODR_1KHZ 0x06 // default +#define ICM40609_GYRO_ODR_200HZ 0x07 +#define ICM40609_GYRO_ODR_100HZ 0x08 +#define ICM40609_GYRO_ODR_50HZ 0x09 +#define ICM40609_GYRO_ODR_25HZ 0x0A +#define ICM40609_GYRO_ODR_12_5HZ 0x0B +#define ICM40609_GYRO_ODR_RESERVED_C 0x0C +#define ICM40609_GYRO_ODR_RESERVED_D 0x0D +#define ICM40609_GYRO_ODR_RESERVED_E 0x0E +#define ICM40609_GYRO_ODR_500HZ 0x0F + +// ACCEL_CONFIG0_REG - 0x50 bits [7:5] +#define ICM40609_ACCEL_FS_SEL_16G (0 << 5) +#define ICM40609_ACCEL_FS_SEL_8G (1 << 5) +#define ICM40609_ACCEL_FS_SEL_4G (2 << 5) +#define ICM40609_ACCEL_FS_SEL_2G (3 << 5) +#define ICM40609_ACCEL_FS_SEL_1G (4 << 5) +#define ICM40609_ACCEL_FS_SEL_0_5G (5 << 5) +#define ICM40609_ACCEL_FS_SEL_0_25G (6 << 5) +#define ICM40609_ACCEL_FS_SEL_0_125G (7 << 5) + +// ACCEL_CONFIG0_REG - 0x50 bits [3:0] +#define ICM40609_ACCEL_ODR_32KHZ 0x01 +#define ICM40609_ACCEL_ODR_16KHZ 0x02 +#define ICM40609_ACCEL_ODR_8KHZ 0x03 +#define ICM40609_ACCEL_ODR_4KHZ 0x04 +#define ICM40609_ACCEL_ODR_2KHZ 0x05 +#define ICM40609_ACCEL_ODR_1KHZ 0x06 // 1kHz (LN mode) (default) +#define ICM40609_ACCEL_ODR_200HZ 0x07 +#define ICM40609_ACCEL_ODR_100HZ 0x08 +#define ICM40609_ACCEL_ODR_50HZ 0x09 +#define ICM40609_ACCEL_ODR_25HZ 0x0A +#define ICM40609_ACCEL_ODR_12_5HZ 0x0B +#define ICM40609_ACCEL_ODR_500HZ 0x0F + +// INT_CONFIG_REG - 0x14 +#define ICM40609_INT1_MODE_PULSED (0 << 2) +#define ICM40609_INT1_MODE_LATCHED (1 << 2) + +#define ICM40609_INT1_DRIVE_OPEN_DRAIN (0 << 1) +#define ICM40609_INT1_DRIVE_PUSH_PULL (1 << 1) + +#define ICM40609_INT1_POLARITY_ACTIVE_LOW (0 << 0) +#define ICM40609_INT1_POLARITY_ACTIVE_HIGH (1 << 0) + +// NT_SOURCE0_REG - 0x65 +#define ICM40609_UI_FSYNC_INT1_EN (1 << 6) +#define ICM40609_PLL_RDY_INT1_EN (1 << 5) +#define ICM40609_RESET_DONE_INT1_EN (1 << 4) +#define ICM40609_UI_DRDY_INT1_EN (1 << 3) +#define ICM40609_FIFO_THS_INT1_EN (1 << 2) +#define ICM40609_FIFO_FULL_INT1_EN (1 << 1) +#define ICM40609_UI_AGC_RDY_INT1_EN (1 << 0) + +// INT_CONFIG0 - 0x63 +#define ICM40609_UI_DRDY_INT_CLEAR_STATUS (0 << 4) + +// INT_CONFIG1 - 0x64 +#define ICM40609_INT_TPULSE_100US (0 << 6) // ODR < 4kHz, optional +#define ICM40609_INT_TPULSE_8US (1 << 6) // ODR ≥ 4kHz +#define ICM40609_INT_TDEASSERT_ENABLED (0 << 5) +#define ICM40609_INT_TDEASSERT_DISABLED (1 << 5) +#define ICM40609_INT_ASYNC_RESET_ENABLED (1 << 4) +#define ICM40609_INT_ASYNC_RESET_DISABLED (0 << 4) + +// REG_GYRO_CONFIG1 - 0x51 bits [3:2] +#define ICM40609_GYRO_UI_FILT_ORDER_1ST (0 << 2) +#define ICM40609_GYRO_UI_FILT_ORDER_2ND (1 << 2) +#define ICM40609_GYRO_UI_FILT_ORDER_3RD (2 << 2) + +// REG_GYRO_CONFIG1 - 0x51 bits [1:0] +#define ICM40609_GYRO_DEC2_M2_ORDER_3RD (2 << 0) + +// REG_GYRO_ACCEL_CONFIG0 - 0x52 bits [7:4] +#define ICM40609_ACCEL_UI_FILT_BW_ODR_DIV2 (0 << 4) +#define ICM40609_ACCEL_UI_FILT_BW_ODR_DIV4 (1 << 4) // default +#define ICM40609_ACCEL_UI_FILT_BW_ODR_DIV5 (2 << 4) +#define ICM40609_ACCEL_UI_FILT_BW_ODR_DIV8 (3 << 4) +#define ICM40609_ACCEL_UI_FILT_BW_ODR_DIV10 (4 << 4) +#define ICM40609_ACCEL_UI_FILT_BW_ODR_DIV16 (5 << 4) +#define ICM40609_ACCEL_UI_FILT_BW_ODR_DIV20 (6 << 4) +#define ICM40609_ACCEL_UI_FILT_BW_ODR_DIV40 (7 << 4) +#define ICM40609_ACCEL_UI_FILT_BW_LP_TRIVIAL_400HZ_ODR (14 << 4) // Bit[7:4] - Low Latency +#define ICM40609_ACCEL_UI_FILT_BW_LP_TRIVIAL_200HZ_8XODR (15 << 4) // Bit[7:4] - Low Latency + +// REG_GYRO_ACCEL_CONFIG0 - 0x52 bits [3:0] +#define ICM40609_GYRO_UI_FILT_BW_ODR_DIV2 (0 << 0) +#define ICM40609_GYRO_UI_FILT_BW_ODR_DIV4 (1 << 0) // default +#define ICM40609_GYRO_UI_FILT_BW_ODR_DIV5 (2 << 0) +#define ICM40609_GYRO_UI_FILT_BW_ODR_DIV8 (3 << 0) +#define ICM40609_GYRO_UI_FILT_BW_ODR_DIV10 (4 << 0) +#define ICM40609_GYRO_UI_FILT_BW_ODR_DIV16 (5 << 0) +#define ICM40609_GYRO_UI_FILT_BW_ODR_DIV20 (6 << 0) +#define ICM40609_GYRO_UI_FILT_BW_ODR_DIV40 (7 << 0) +#define ICM40609_GYRO_UI_FILT_BW_LP_TRIVIAL_400HZ_ODR (14 << 0) // Bit[3:0] - Low Latency +#define ICM40609_GYRO_UI_FILT_BW_LP_TRIVIAL_200HZ_8XODR (15 << 0) // Bit[3:0] - Low Latency + +// REG_ACCEL_CONFIG_STATIC2 - 0x03 bit [0] +#define ICM40609_ACCEL_AAF_DIS (1 << 0) + +// REG_GYRO_CONFIG_STATIC2 - 0x0B bit [1] +#define ICM40609_GYRO_AAF_DIS (1 << 1) + +//REG_GYRO_CONFIG_STATIC2 - 0x0B bit [0] +#define ICM40609_GYRO_NF_DIS_BIT (1 << 0) + +// GYRO_HPF_BW_IND - 0x13 bit [3:1] — High-pass filter 3dB cutoff frequency selection +#define ICM40609_GYRO_HPF_BW_IND_MASK (0x07 << 1) // bits [3:1] + +// GYRO_HPF_ORD_IND [0] — High-pass filter order (1st or 2nd) +#define ICM40609_GYRO_HPF_ORD_IND_MASK (1 << 0) + +// GYRO_CONFIG1 (0x51) +#define ICM40609_GYRO_UI_FILT_ORD_MASK (0x03 << 2) // bits [3:2] +#define ICM40609_GYRO_DEC2_M2_ORD_MASK (0x03 << 0) // bits [1:0] + +// ACCEL_CONFIG1 (0x53) +#define ICM40609_ACCEL_UI_FILT_ORD_MASK (0x03 << 3) // bits [4:3] +#define ICM40609_ACCEL_DEC2_M2_ORD_MASK (0x03 << 1) // bits [2:1] + +#define ICM40609_ACCEL_DATA_X1_UI 0x1F +#define ICM40609_GYRO_DATA_X1_UI 0x25 + +#define ICM40609_RESET_REG 0x4C +#define ICM40609_SOFT_RESET_VAL 0x01 + +#ifndef ICM40609_LOCK +// Default: 24 MHz max SPI frequency +#define ICM40609_MAX_SPI_CLK_HZ 24000000 +#else +// Use the supplied value +#define ICM40609_MAX_SPI_CLK_HZ ICM40609_LOCK +#endif + +#define ICM40609_AAF_PROFILE_COUNT 63 + +// Table 5.2 Bandwidth (Hz) +typedef struct { + uint16_t hz; + uint8_t delt; + uint16_t deltsqr; + uint8_t bitshift; +} ICM40609_AafProfile; + + +static const ICM40609_AafProfile aafProfiles[ICM40609_AAF_PROFILE_COUNT] = { + { 42, 1, 1, 15 }, + { 84, 2, 4, 13 }, + { 126, 3, 9, 12 }, + { 170, 4, 16, 11 }, + { 213, 5, 25, 10 }, + { 258, 6, 36, 10 }, + { 303, 7, 49, 9 }, + { 348, 8, 64, 9 }, + { 394, 9, 81, 9 }, + { 441, 10, 100, 8 }, + { 488, 11, 122, 8 }, + { 536, 12, 144, 8 }, + { 585, 13, 170, 8 }, + { 634, 14, 196, 8 }, + { 684, 15, 224, 7 }, + { 734, 16, 256, 7 }, + { 785, 17, 288, 7 }, + { 837, 18, 324, 7 }, + { 890, 19, 360, 6 }, + { 943, 20, 400, 6 }, + { 997, 21, 440, 6 }, + { 1051, 22, 488, 6 }, + { 1107, 23, 528, 6 }, + { 1163, 24, 576, 6 }, + { 1220, 25, 624, 6 }, + { 1277, 26, 680, 6 }, + { 1336, 27, 736, 5 }, + { 1395, 28, 784, 5 }, + { 1454, 29, 848, 5 }, + { 1515, 30, 896, 5 }, + { 1577, 31, 960, 5 }, + { 1639, 32, 1024, 5 }, + { 1702, 33, 1088, 5 }, + { 1766, 34, 1152, 5 }, + { 1830, 35, 1232, 5 }, + { 1896, 36, 1296, 5 }, + { 1962, 37, 1376, 4 }, + { 2029, 38, 1440, 4 }, + { 2097, 39, 1536, 4 }, + { 2166, 40, 1600, 4 }, + { 2235, 41, 1696, 4 }, + { 2306, 42, 1760, 4 }, + { 2377, 43, 1856, 4 }, + { 2449, 44, 1952, 4 }, + { 2522, 45, 2016, 4 }, + { 2596, 46, 2112, 4 }, + { 2671, 47, 2208, 4 }, + { 2746, 48, 2304, 4 }, + { 2823, 49, 2400, 4 }, + { 2900, 50, 2496, 4 }, + { 2978, 51, 2592, 4 }, + { 3057, 52, 2720, 4 }, + { 3137, 53, 2816, 4 }, + { 3217, 54, 2944, 3 }, + { 3299, 55, 3008, 3 }, + { 3381, 56, 3136, 3 }, + { 3464, 57, 3264, 3 }, + { 3548, 58, 3392, 3 }, + { 3633, 59, 3456, 3 }, + { 3718, 60, 3584, 3 }, + { 3805, 61, 3712, 3 }, + { 3892, 62, 3840, 3 }, + { 3979, 63, 3968, 3 }, +}; + +/* + * ICM-40609D Group Delay @DC (ODR = 8000 Hz) + * + * +-------------------+--------------------+----------+ + * | Filter Order | Delay (UI_FILT_BW) | NBW (Hz) | + * +-------------------+--------------------+----------+ + * | 1st order filter | 0.2 ms | 2204.6 | + * | 2nd order filter | 0.2 ms | 2204.6 | + * | 3rd order filter | 0.2 ms | 2096.3 | + * +-------------------+--------------------+----------+ + * + * Note: + * Delay is independent of UI_FILT_BW when ODR = 8000Hz. + * 5.4 UI FILTER BLOCK TDK ICM-40609D Datasheet Rev 1.2 (2023) + * + * Filter order (standard DSP behavior): + * 1st order -6 dB/octave + * 2nd order -12 dB/octave + * 3rd order -18 dB/octave + * These roll-off rates are typical for LPF/HPF filters in digital signal processing (DSP). + */ +typedef enum { + ICM40609_UI_FILT_ORDER_1ST = 0, + ICM40609_UI_FILT_ORDER_2ND = 1, + ICM40609_UI_FILT_ORDER_3RD = 2 +} icm40609UiFiltOrder_e; + +typedef enum { + ICM40609_HPF_ORDER_1ST = 0, + ICM40609_HPF_ORDER_2ND = 1 +} icm40609HpfOrder_e; + +// Bandwidth selection for High-Pass Filter +// ICM40609_REG_GYRO_CONFIG_STATIC10 - 0x13 bits [3:1] +// NOTE: clarify with new datasheet, section 5.6 not found in V1.2 +typedef enum { + ICM40609_HPF_BW_0 = 0, + ICM40609_HPF_BW_1 = 1, + ICM40609_HPF_BW_2 = 2, + ICM40609_HPF_BW_3 = 3, + ICM40609_HPF_BW_4 = 4, + ICM40609_HPF_BW_5 = 5, + ICM40609_HPF_BW_6 = 6, + ICM40609_HPF_BW_7 = 7, +} icm40609HpfBw_e; + +// Bandwidth selection for Notch Filter GYRO_NF_BW_SEL +// ICM40609_REG_GYRO_CONFIG_STATIC10 - 0x13 bits [6:4] +typedef enum { + ICM40609_GYRO_NF_BW_1449HZ = 0, + ICM40609_GYRO_NF_BW_680HZ = 1, + ICM40609_GYRO_NF_BW_329HZ = 2, + ICM40609_GYRO_NF_BW_162HZ = 3, + ICM40609_GYRO_NF_BW_80HZ = 4, + ICM40609_GYRO_NF_BW_40HZ = 5, + ICM40609_GYRO_NF_BW_20HZ = 6, + ICM40609_GYRO_NF_BW_10HZ = 7, +} icm40609GyroNfBw_e; + +typedef enum { + ICM40609_TEMP_FILT_BW_4000HZ = 0, // 4000Hz, 0.125ms latency (default) + ICM40609_TEMP_FILT_BW_170HZ = 1, // 170Hz, 1ms latency + ICM40609_TEMP_FILT_BW_82HZ = 2, // 82Hz, 2ms latency + ICM40609_TEMP_FILT_BW_40HZ = 3, // 40Hz, 4ms latency + ICM40609_TEMP_FILT_BW_20HZ = 4, // 20Hz, 8ms latency + ICM40609_TEMP_FILT_BW_10HZ = 5, // 10Hz, 16ms latency + ICM40609_TEMP_FILT_BW_5HZ = 6, // 5Hz, 32ms latency +} icm40609TempFiltBw_e; + +static void icm40609SelectUserBank(const extDevice_t *dev, uint8_t bank) +{ + if (bank > 4) { + return; // out of range + } + spiWriteReg(dev, ICM40609_REG_BANK_SEL, bank & 0x07); // bit [2:0] +} + +static void setGyroAccPowerMode(const extDevice_t *dev, bool enable) +{ + icm40609SelectUserBank(dev, ICM40609_USER_BANK_0); + + spiWriteReg(dev, ICM40609_REG_PWR_MGMT0, + ICM40609_RC_ON | + ICM40609_TEMP_SENSOR_ENABLED | + (enable ? ICM40609_GYRO_MODE_LN | ICM40609_ACCEL_MODE_LN + : ICM40609_GYRO_MODE_OFF | ICM40609_ACCEL_MODE_OFF)); + + if (enable) { + delayMicroseconds(200); + } else { + delay(50); + } +} + +static void icm40609GetAafParams(uint16_t targetHz, ICM40609_AafProfile* res) +{ + uint16_t i = 0; + while (i < ICM40609_AAF_PROFILE_COUNT && targetHz > aafProfiles[i].hz) { + i++; + } + if (i < ICM40609_AAF_PROFILE_COUNT) { + *res = aafProfiles[i]; + } else { + // not found - Requested frequency is higher than max available + *res = aafProfiles[ICM40609_AAF_PROFILE_COUNT - 1]; + } +} + +static void icm40609SetAccelAafByHz(const extDevice_t *dev, bool aafEnable, uint16_t targetHz) +{ + icm40609SelectUserBank(dev, ICM40609_USER_BANK_2); + + if (aafEnable && targetHz > 0) { + ICM40609_AafProfile aafProfile; + + icm40609GetAafParams(targetHz, &aafProfile); + + uint8_t reg03 = spiReadRegMsk(dev, ICM40609_REG_ACCEL_CONFIG_STATIC2); + + reg03 &= ~ICM40609_ACCEL_AAF_DIS; // Clear ACCEL_AAF_DIS to enable AAF + reg03 = (reg03 & 0x81) | (aafProfile.delt << 1); // Keep reserved bit 7, set ACCEL_AAF_DELT + spiWriteReg(dev, ICM40609_REG_ACCEL_CONFIG_STATIC2, reg03); + + uint8_t reg04 = aafProfile.deltsqr & 0xFF; + uint8_t reg05 = ((aafProfile.bitshift & 0x0F) << 4) | ((aafProfile.deltsqr >> 8) & 0x0F); + + spiWriteReg(dev, ICM40609_REG_ACCEL_CONFIG_STATIC3, reg04); + spiWriteReg(dev, ICM40609_REG_ACCEL_CONFIG_STATIC4, reg05); + + } else { + uint8_t reg03 = spiReadRegMsk(dev, ICM40609_REG_ACCEL_CONFIG_STATIC2); + reg03 |= ICM40609_ACCEL_AAF_DIS; // Set ACCEL_AAF_DIS to disable AAF + spiWriteReg(dev, ICM40609_REG_ACCEL_CONFIG_STATIC2, reg03); + } + + icm40609SelectUserBank(dev, ICM40609_USER_BANK_0); +} + +static void icm40609SetGyroAafByHz(const extDevice_t *dev, bool aafEnable, uint16_t targetHz) +{ + icm40609SelectUserBank(dev, ICM40609_USER_BANK_1); + + if (aafEnable && targetHz > 0) { + ICM40609_AafProfile aafProfile; + + icm40609GetAafParams(targetHz, &aafProfile); + + uint8_t reg0C = aafProfile.delt & 0x3F; + uint8_t reg0D = aafProfile.deltsqr & 0xFF; + uint8_t reg0E = ((aafProfile.bitshift & 0x0F) << 4) | ((aafProfile.deltsqr >> 8) & 0x0F); + + uint8_t reg0B = spiReadRegMsk(dev, ICM40609_REG_GYRO_CONFIG_STATIC2); + reg0B &= ~ICM40609_GYRO_AAF_DIS; // Clear AAF_DIS (bit1) to enable AAF + spiWriteReg(dev, ICM40609_REG_GYRO_CONFIG_STATIC2, reg0B); + + spiWriteReg(dev, ICM40609_REG_GYRO_CONFIG_STATIC3, reg0C); + spiWriteReg(dev, ICM40609_REG_GYRO_CONFIG_STATIC4, reg0D); + spiWriteReg(dev, ICM40609_REG_GYRO_CONFIG_STATIC5, reg0E); + + } else { + uint8_t reg0B = spiReadRegMsk(dev, ICM40609_REG_GYRO_CONFIG_STATIC2); + reg0B |= ICM40609_GYRO_AAF_DIS; // Set AAF_DIS (bit1) to disable AAF + spiWriteReg(dev, ICM40609_REG_GYRO_CONFIG_STATIC2, reg0B); + } + + icm40609SelectUserBank(dev, ICM40609_USER_BANK_0); +} + +static void icm40609SetGyroHPF(const extDevice_t *dev, bool hpfEnable, icm40609HpfBw_e hpfBwInd, icm40609HpfOrder_e hpfOrder) +{ + icm40609SelectUserBank(dev, ICM40609_USER_BANK_1); + + uint8_t reg13 = spiReadRegMsk(dev, ICM40609_REG_GYRO_CONFIG_STATIC10); + + reg13 &= ~(ICM40609_GYRO_HPF_BW_IND_MASK | ICM40609_GYRO_HPF_ORD_IND_MASK); // clear HPF bits + + if (hpfEnable) { + reg13 |= (hpfBwInd << 1) | (hpfOrder << 0); + } + + spiWriteReg(dev, ICM40609_REG_GYRO_CONFIG_STATIC10, reg13); + + icm40609SelectUserBank(dev, ICM40609_USER_BANK_0); +} + +static void icm40609SetGyroNotch(const extDevice_t *dev, bool notchEnable, icm40609GyroNfBw_e bwSel, float fdesiredKhz) +{ + if (fdesiredKhz < 1.0f || fdesiredKhz > 3.0f) { + return; // (1kHz to 3kHz) Operating the notch filter outside this range is not supported. + } + + icm40609SelectUserBank(dev, ICM40609_USER_BANK_1); + + // Enable/disable Notch filter + uint8_t reg2 = spiReadRegMsk(dev, ICM40609_REG_GYRO_CONFIG_STATIC2); + if (notchEnable) { + reg2 &= ~ICM40609_GYRO_NF_DIS_BIT; + } else { + reg2 |= ICM40609_GYRO_NF_DIS_BIT; // Bypass + } + spiWriteReg(dev, ICM40609_REG_GYRO_CONFIG_STATIC2, reg2); + + if (notchEnable) { + // Set Bandwidth in STATIC10 (0x13) + uint8_t reg13 = spiReadRegMsk(dev, ICM40609_REG_GYRO_CONFIG_STATIC10); + reg13 &= ~(0x07 << 4); + reg13 |= (bwSel & 0x07) << 4; // GYRO_NF_BW_SEL [6:4] + spiWriteReg(dev, ICM40609_REG_GYRO_CONFIG_STATIC10, reg13); + + // Section 5.1.1 (v1.2) Frequency of Notch Filter (each axis) + // Calculate COSWZ and SEL based on desired frequency + float coswz = cosf(2.0f * M_PIf * fdesiredKhz / 32.0f); + uint8_t nf_coswz_lsb = 0; + uint8_t nf_coswz_msb = 0; + uint8_t nf_coswz_sel = 0; + + if (fabsf(coswz) <= 0.875f) { + int16_t nf_coswz = (int16_t)roundf(coswz * 256.0f); + nf_coswz_lsb = nf_coswz & 0xFF; + nf_coswz_msb = (nf_coswz >> 8) & 0x01; + nf_coswz_sel = 0; + } else { + nf_coswz_sel = 1; + int16_t nf_coswz; + if (coswz > 0.875f) { + nf_coswz = (int16_t)roundf(8.0f * (1.0f - coswz) * 256.0f); + } else { + nf_coswz = (int16_t)roundf(8.0f * (1.0f + coswz) * 256.0f); + } + nf_coswz_lsb = nf_coswz & 0xFF; + nf_coswz_msb = (nf_coswz >> 8) & 0x01; + } + + // Write NF_COSWZ[7:0] for X, Y, Z + spiWriteReg(dev, ICM40609_REG_GYRO_CONFIG_STATIC6, nf_coswz_lsb); // X + spiWriteReg(dev, ICM40609_REG_GYRO_CONFIG_STATIC7, nf_coswz_lsb); // Y + spiWriteReg(dev, ICM40609_REG_GYRO_CONFIG_STATIC8, nf_coswz_lsb); // Z + + // Write NF_COSWZ[8] and NF_COSWZ_SEL into STATIC9 (0x12) + uint8_t reg9 = 0; + reg9 |= (nf_coswz_msb << 0); // X NF_COSWZ[8] + reg9 |= (nf_coswz_msb << 1); // Y NF_COSWZ[8] + reg9 |= (nf_coswz_msb << 2); // Z NF_COSWZ[8] + reg9 |= (nf_coswz_sel << 3); // X COSWZ_SEL + reg9 |= (nf_coswz_sel << 4); // Y COSWZ_SEL + reg9 |= (nf_coswz_sel << 5); // Z COSWZ_SEL + spiWriteReg(dev, ICM40609_REG_GYRO_CONFIG_STATIC9, reg9); + } + + icm40609SelectUserBank(dev, ICM40609_USER_BANK_0); +} + +static void icm40609SetTempFiltBw(const extDevice_t *dev, icm40609TempFiltBw_e bw) +{ + icm40609SelectUserBank(dev, ICM40609_USER_BANK_0); + + uint8_t reg51 = spiReadRegMsk(dev, ICM40609_REG_GYRO_CONFIG1); + reg51 &= ~(0x07 << 5); + reg51 |= (bw << 5); + spiWriteReg(dev, ICM40609_REG_GYRO_CONFIG1, reg51); +} + +static void icm40609SetGyroUiFiltOrder(const extDevice_t *dev, icm40609UiFiltOrder_e order) +{ + icm40609SelectUserBank(dev, ICM40609_USER_BANK_0); + + uint8_t reg51 = spiReadRegMsk(dev, ICM40609_REG_GYRO_CONFIG1); + reg51 &= ~ICM40609_GYRO_UI_FILT_ORD_MASK; + reg51 |= (order << 2); // Write GYRO_UI_FILT_ORD to bits [3:2] + spiWriteReg(dev, ICM40609_REG_GYRO_CONFIG1, reg51); +} + +static void icm40609SetAccelUiFiltOrder(const extDevice_t *dev, icm40609UiFiltOrder_e order) +{ + icm40609SelectUserBank(dev, ICM40609_USER_BANK_0); + + uint8_t reg53 = spiReadRegMsk(dev, ICM40609_REG_GYRO_ACCEL_CONFIG1); + reg53 &= ~ICM40609_ACCEL_UI_FILT_ORD_MASK; + reg53 |= (order << 3); // Write ACCEL_UI_FILT_ORD to bits [4:3] + spiWriteReg(dev, ICM40609_REG_GYRO_ACCEL_CONFIG1, reg53); +} + +static void icm40609SetGyroDec2M2(const extDevice_t *dev, bool enable) +{ + icm40609SelectUserBank(dev, ICM40609_USER_BANK_0); + + uint8_t reg51 = spiReadRegMsk(dev, ICM40609_REG_GYRO_CONFIG1); + reg51 &= ~ICM40609_GYRO_DEC2_M2_ORD_MASK; + + if (enable) { + reg51 |= (2 << 0); + } + + spiWriteReg(dev, ICM40609_REG_GYRO_CONFIG1, reg51); +} + +// Set endianness for sensor data (bit 4 of INTF_CONFIG0, reg 0x4C) +// true = Big Endian +// false = Little Endian +static void icm40609SetEndianess(const extDevice_t *dev, bool bigEndian) +{ + icm40609SelectUserBank(dev, ICM40609_USER_BANK_0); + + uint8_t reg4C = spiReadRegMsk(dev, ICM40609_REG_INTF_CONFIG0); + reg4C &= ~(1 << 4); + reg4C |= bigEndian << 4; + + spiWriteReg(dev, ICM40609_REG_INTF_CONFIG0, reg4C); +} + +void icm40609AccInit(accDev_t *acc) +{ + acc->acc_1G = 2048; // 16g scale + acc->gyro->accSampleRateHz = 1000; + +} + +void icm40609GyroInit(gyroDev_t *gyro) +{ + const extDevice_t *dev = &gyro->dev; + spiSetClkDivisor(dev, spiCalculateDivider(ICM40609_MAX_SPI_CLK_HZ)); + + mpuGyroInit(gyro); + gyro->accDataReg = ICM40609_ACCEL_DATA_X1_UI; + gyro->gyroDataReg = ICM40609_GYRO_DATA_X1_UI; + + setGyroAccPowerMode(dev, false); + + icm40609SetEndianess(dev, true); + + icm40609SelectUserBank(dev, ICM40609_USER_BANK_0); + spiWriteReg(dev, ICM40609_REG_GYRO_CONFIG0, ICM40609_GYRO_FS_SEL_2000DPS | ICM40609_GYRO_ODR_8KHZ); + gyro->scale = GYRO_SCALE_2000DPS; + gyro->gyroRateKHz = GYRO_RATE_8_kHz; + gyro->gyroSampleRateHz = 8000; + + spiWriteReg(dev, ICM40609_REG_ACCEL_CONFIG0, ICM40609_ACCEL_FS_SEL_16G | ICM40609_ACCEL_ODR_1KHZ ); + + icm40609SetTempFiltBw(dev, ICM40609_TEMP_FILT_BW_4000HZ); // 4000Hz, 0.125ms latency (default) + icm40609SetGyroUiFiltOrder(dev, ICM40609_UI_FILT_ORDER_3RD); + icm40609SetAccelUiFiltOrder(dev, ICM40609_UI_FILT_ORDER_3RD); + icm40609SetGyroDec2M2(dev, true); + + // Set filter bandwidth: Low Latency + spiWriteReg(&gyro->dev, ICM40609_REG_GYRO_ACCEL_CONFIG0, + ICM40609_ACCEL_UI_FILT_BW_LP_TRIVIAL_200HZ_8XODR | + ICM40609_GYRO_UI_FILT_BW_LP_TRIVIAL_200HZ_8XODR); + + uint16_t gyroHWLpf; // Anti-Alias Filter (AAF) in Hz + switch (gyroConfig()->gyro_hardware_lpf) { + case GYRO_HARDWARE_LPF_NORMAL: + gyroHWLpf = 213; + break; + case GYRO_HARDWARE_LPF_OPTION_1: + gyroHWLpf = 488; + break; + case GYRO_HARDWARE_LPF_OPTION_2: + gyroHWLpf = 997; + break; +#ifdef USE_GYRO_DLPF_EXPERIMENTAL + case GYRO_HARDWARE_LPF_EXPERIMENTAL: + gyroHWLpf = 1962; + break; +#endif + default: + gyroHWLpf = 213; + } + + icm40609SetGyroAafByHz(dev, true, gyroHWLpf); + icm40609SetAccelAafByHz(dev, true, gyroHWLpf); + + icm40609SetGyroNotch(dev, true, ICM40609_GYRO_NF_BW_1449HZ, 1.5f); + + icm40609SetGyroHPF(dev, true, ICM40609_HPF_BW_1, ICM40609_HPF_ORDER_1ST); + + // Enable interrupt + spiWriteReg(dev, ICM40609_REG_INT_SOURCE0, ICM40609_UI_DRDY_INT1_EN); + + // Set INT1 to pulse mode, push-pull, active high + spiWriteReg(dev, ICM40609_REG_INT_CONFIG, + ICM40609_INT1_MODE_PULSED | + ICM40609_INT1_DRIVE_PUSH_PULL | + ICM40609_INT1_POLARITY_ACTIVE_HIGH); + + spiWriteReg(dev, ICM40609_REG_INT_CONFIG0, ICM40609_UI_DRDY_INT_CLEAR_STATUS); // auto clear after read + + // Set INT1 pulse width to 8us, deassertion enabled, async reset disabled + spiWriteReg(dev, ICM40609_REG_INT_CONFIG1, + ICM40609_INT_TPULSE_8US | + ICM40609_INT_TDEASSERT_DISABLED | + ICM40609_INT_ASYNC_RESET_DISABLED); + + setGyroAccPowerMode(dev, true); + +} + +uint8_t icm40609SpiDetect(const extDevice_t *dev) +{ + icm40609SelectUserBank(dev, ICM40609_USER_BANK_0); + + spiWriteReg(dev, ICM40609_RESET_REG, ICM40609_SOFT_RESET_VAL); + delay(1); + + uint8_t whoAmI = spiReadRegMsk(dev, ICM40609_WHO_AM_I_REG); + if (whoAmI == ICM40609_WHO_AM_I_CONST) { + return ICM_40609_SPI; + } + return MPU_NONE; +} + +bool icm40609SpiAccDetect(accDev_t *acc) +{ + if (acc->mpuDetectionResult.sensor == ICM_40609_SPI) { + acc->initFn = icm40609AccInit; + acc->readFn = mpuAccReadSPI; + return true; + } + return false; +} + +bool icm40609SpiGyroDetect(gyroDev_t *gyro) +{ + if (gyro->mpuDetectionResult.sensor == ICM_40609_SPI) { + gyro->initFn = icm40609GyroInit; + gyro->readFn = mpuGyroReadSPI; + return true; + } + return false; +} + +#endif // USE_ACCGYRO_ICM40609D diff --git a/src/main/drivers/accgyro/accgyro_spi_icm40609.h b/src/main/drivers/accgyro/accgyro_spi_icm40609.h new file mode 100644 index 0000000000..0211311079 --- /dev/null +++ b/src/main/drivers/accgyro/accgyro_spi_icm40609.h @@ -0,0 +1,32 @@ +/* + * This file is part of Betaflight. + * + * Betaflight is free software. You can redistribute this software + * and/or modify this software under the terms of the GNU General + * Public License as published by the Free Software Foundation, + * either version 3 of the License, or (at your option) any later + * version. + * + * Betaflight is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * See the GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this software. + * + * If not, see . + */ + +#pragma once + +#include "drivers/bus.h" + +void icm40609AccInit(accDev_t *acc); +void icm40609GyroInit(gyroDev_t *gyro); + +uint8_t icm40609SpiDetect(const extDevice_t *dev); + +bool icm40609SpiAccDetect(accDev_t *acc); +bool icm40609SpiGyroDetect(gyroDev_t *gyro); diff --git a/src/main/sensors/acceleration.h b/src/main/sensors/acceleration.h index 2c4706b9ed..bb75d5cc61 100644 --- a/src/main/sensors/acceleration.h +++ b/src/main/sensors/acceleration.h @@ -53,6 +53,7 @@ typedef enum { ACC_IIM42653, ACC_ICM45605, ACC_ICM45686, + ACC_ICM40609D, ACC_VIRTUAL } accelerationSensor_e; diff --git a/src/main/sensors/acceleration_init.c b/src/main/sensors/acceleration_init.c index 0d59e46858..93426607ba 100644 --- a/src/main/sensors/acceleration_init.c +++ b/src/main/sensors/acceleration_init.c @@ -48,6 +48,7 @@ #include "drivers/accgyro/accgyro_spi_icm20689.h" #include "drivers/accgyro/accgyro_spi_icm426xx.h" #include "drivers/accgyro/accgyro_spi_icm456xx.h" +#include "drivers/accgyro/accgyro_spi_icm40609.h" #include "drivers/accgyro/accgyro_spi_lsm6dso.h" #include "drivers/accgyro/accgyro_spi_lsm6dsv16x.h" @@ -297,6 +298,15 @@ retry: FALLTHROUGH; #endif +#ifdef USE_ACCGYRO_ICM40609D + case ACC_ICM40609D: + if (icm40609SpiAccDetect(dev)) { + accHardware = ACC_ICM40609D; + break; + } + FALLTHROUGH; +#endif + #ifdef USE_VIRTUAL_ACC case ACC_VIRTUAL: if (virtualAccDetect(dev)) { diff --git a/src/main/sensors/gyro_init.c b/src/main/sensors/gyro_init.c index 568386e560..5afb37e5e9 100644 --- a/src/main/sensors/gyro_init.c +++ b/src/main/sensors/gyro_init.c @@ -48,6 +48,7 @@ #include "drivers/accgyro/accgyro_spi_icm20689.h" #include "drivers/accgyro/accgyro_spi_icm426xx.h" #include "drivers/accgyro/accgyro_spi_icm456xx.h" +#include "drivers/accgyro/accgyro_spi_icm40609.h" #include "drivers/accgyro/accgyro_spi_l3gd20.h" #include "drivers/accgyro/accgyro_spi_lsm6dso.h" @@ -514,6 +515,16 @@ STATIC_UNIT_TESTED gyroHardware_e gyroDetect(gyroDev_t *dev) FALLTHROUGH; #endif + +#ifdef USE_ACCGYRO_ICM40609D + case GYRO_ICM40609D: + if (icm40609SpiGyroDetect(dev)) { + gyroHardware = GYRO_ICM40609D; + break; + } + FALLTHROUGH; +#endif + #ifdef USE_VIRTUAL_GYRO case GYRO_VIRTUAL: if (virtualGyroDetect(dev)) { diff --git a/src/main/target/common_post.h b/src/main/target/common_post.h index 6a732310cf..b4ff315959 100644 --- a/src/main/target/common_post.h +++ b/src/main/target/common_post.h @@ -101,6 +101,7 @@ && !defined(USE_ACC_SPI_ICM20649) \ && !defined(USE_ACC_SPI_ICM20689) \ && !defined(USE_ACC_SPI_ICM42605) \ + && !defined(USE_ACCGYRO_ICM40609D) \ && !defined(USE_ACC_SPI_ICM42688P) \ && !defined(USE_ACCGYRO_ICM45686) \ && !defined(USE_ACCGYRO_ICM45605) \ @@ -126,6 +127,7 @@ && !defined(USE_GYRO_SPI_ICM42688P) \ && !defined(USE_ACCGYRO_ICM45686) \ && !defined(USE_ACCGYRO_ICM45605) \ + && !defined(USE_ACCGYRO_ICM40609D) \ && !defined(USE_ACCGYRO_LSM6DSO) \ && !defined(USE_ACCGYRO_LSM6DSV16X) \ && !defined(USE_GYRO_SPI_MPU6000) \ @@ -474,7 +476,7 @@ #if defined(USE_GYRO_SPI_ICM20689) || defined(USE_GYRO_SPI_MPU6000) || defined(USE_GYRO_SPI_MPU6500) || defined(USE_GYRO_SPI_MPU9250) \ || defined(USE_GYRO_L3GD20) || defined(USE_GYRO_SPI_ICM42605) || defined(USE_GYRO_SPI_ICM42688P) || defined(USE_ACCGYRO_ICM45686) \ || defined(USE_ACCGYRO_ICM45605) || defined(USE_ACCGYRO_IIM42653) || defined(USE_ACCGYRO_BMI160) || defined(USE_ACCGYRO_BMI270) \ - || defined(USE_ACCGYRO_LSM6DSV16X) || defined(USE_ACCGYRO_LSM6DSO) + || defined(USE_ACCGYRO_LSM6DSV16X) || defined(USE_ACCGYRO_LSM6DSO) || defined(USE_ACCGYRO_ICM40609D) #ifndef USE_SPI_GYRO #define USE_SPI_GYRO #endif diff --git a/src/main/target/common_pre.h b/src/main/target/common_pre.h index d43b30aaaf..326c7fd5ee 100644 --- a/src/main/target/common_pre.h +++ b/src/main/target/common_pre.h @@ -120,6 +120,7 @@ #define USE_ACC_SPI_ICM42605 #define USE_ACC_SPI_ICM42688P #define USE_ACCGYRO_LSM6DSV16X +#define USE_ACCGYRO_ICM40609D #if TARGET_FLASH_SIZE > 512 #define USE_ACC_MPU6050 From e74b3623413a7246e51ca95c9ac67a5c5128129a Mon Sep 17 00:00:00 2001 From: mjs1441 Date: Wed, 28 May 2025 05:57:46 +0100 Subject: [PATCH 217/244] Platform-dependent IO_GPIO.. functions, IO tags allow single port, more pins. (#14407) --- src/main/drivers/io.c | 38 +---------------------------- src/main/drivers/io_def.h | 19 ++++++++++++--- src/platform/common/stm32/io_impl.c | 33 +++++++++++++++++++++++++ 3 files changed, 50 insertions(+), 40 deletions(-) diff --git a/src/main/drivers/io.c b/src/main/drivers/io.c index 7c8dc12203..7c766d9430 100644 --- a/src/main/drivers/io.c +++ b/src/main/drivers/io.c @@ -26,10 +26,7 @@ #include "common/utils.h" -// io ports defs are stored in array by index now -struct ioPortDef_s { - rccPeriphTag_t rcc; -}; +// io ports defs are stored by index in array ioRecs of ioRec_t ioRec_t* IO_Rec(IO_t io) { @@ -48,39 +45,6 @@ uint16_t IO_Pin(IO_t io) return ioRec->pin; } -#if defined(STM32F4) || defined(APM32F4) -int IO_EXTI_PortSourceGPIO(IO_t io) -{ - return IO_GPIOPortIdx(io); -} -#endif - -int IO_GPIO_PortSource(IO_t io) -{ - return IO_GPIOPortIdx(io); -} - -// zero based pin index -int IO_GPIOPinIdx(IO_t io) -{ - if (!io) { - return -1; - } - return 31 - __builtin_clz(IO_Pin(io)); -} - -#if defined(STM32F4) || defined(APM32F4) -int IO_EXTI_PinSource(IO_t io) -{ - return IO_GPIOPinIdx(io); -} -#endif - -int IO_GPIO_PinSource(IO_t io) -{ - return IO_GPIOPinIdx(io); -} - // claim IO pin, set owner and resources void IOInit(IO_t io, resourceOwner_e owner, uint8_t index) { diff --git a/src/main/drivers/io_def.h b/src/main/drivers/io_def.h index 6566bd34fb..8906c71b2a 100644 --- a/src/main/drivers/io_def.h +++ b/src/main/drivers/io_def.h @@ -41,11 +41,24 @@ // get ioRec by index #define DEFIO_REC_INDEXED(idx) (ioRecs + (idx)) +// split ioTag bits between pin and port +// port is encoded as +1 to avoid collision with 0x0 (false as bool) +#ifndef DEFIO_PORT_PINS +// pins per port +#define DEFIO_PORT_PINS 16 +#endif + +STATIC_ASSERT((DEFIO_PORT_PINS & (DEFIO_PORT_PINS - 1)) == 0, "DEFIO_PORT_PINS must be power of 2"); + +#define DEFIO_PORT_BITSHIFT LOG2(DEFIO_PORT_PINS) +#define DEFIO_PIN_BITMASK ((1 << DEFIO_PORT_BITSHIFT ) - 1) + // ioTag_t accessor macros -#define DEFIO_TAG_MAKE(gpioid, pin) ((ioTag_t)((((gpioid) + 1) << 4) | (pin))) +#define DEFIO_TAG_MAKE(gpioid, pin) ((ioTag_t)((((gpioid) + 1) << DEFIO_PORT_BITSHIFT) | (pin))) #define DEFIO_TAG_ISEMPTY(tag) (!(tag)) -#define DEFIO_TAG_GPIOID(tag) (((tag) >> 4) - 1) -#define DEFIO_TAG_PIN(tag) ((tag) & 0x0f) +#define DEFIO_TAG_GPIOID(tag) (((tag) >> DEFIO_PORT_BITSHIFT) - 1) +#define DEFIO_TAG_PIN(tag) ((tag) & DEFIO_PIN_BITMASK) + // TARGET must define used pins #include "target.h" diff --git a/src/platform/common/stm32/io_impl.c b/src/platform/common/stm32/io_impl.c index c2a98ad40f..a7fabbd3f8 100644 --- a/src/platform/common/stm32/io_impl.c +++ b/src/platform/common/stm32/io_impl.c @@ -76,3 +76,36 @@ int IO_GPIOPortIdx(IO_t io) } return (((size_t)IO_GPIO(io) - GPIOA_BASE) >> 10); } + +#if defined(STM32F4) || defined(APM32F4) +int IO_EXTI_PortSourceGPIO(IO_t io) +{ + return IO_GPIOPortIdx(io); +} +#endif + +int IO_GPIO_PortSource(IO_t io) +{ + return IO_GPIOPortIdx(io); +} + +// zero based pin index +int IO_GPIOPinIdx(IO_t io) +{ + if (!io) { + return -1; + } + return 31 - __builtin_clz(IO_Pin(io)); +} + +#if defined(STM32F4) || defined(APM32F4) +int IO_EXTI_PinSource(IO_t io) +{ + return IO_GPIOPinIdx(io); +} +#endif + +int IO_GPIO_PinSource(IO_t io) +{ + return IO_GPIOPinIdx(io); +} From 66e19f9e2729e1d0c6daffad372b5bfd25d7f90a Mon Sep 17 00:00:00 2001 From: Steve Evans Date: Wed, 28 May 2025 05:59:45 +0100 Subject: [PATCH 218/244] Ensure that crash flip behaviour is consistent on every arm attempt (#14410) --- src/main/fc/core.c | 14 ++------------ 1 file changed, 2 insertions(+), 12 deletions(-) diff --git a/src/main/fc/core.c b/src/main/fc/core.c index cab68d4d30..4cdcc4ba77 100644 --- a/src/main/fc/core.c +++ b/src/main/fc/core.c @@ -558,18 +558,8 @@ void tryArm(void) } #endif // choose crashflip outcome on arming - // disarm can arise in processRx() if the crashflip switch is reversed while in crashflip mode - // if we were unsuccessful, or cannot determin success, arming will be blocked and we can't get here - // hence we only get here with crashFlipModeActive if the switch was reversed and result successful - if (crashFlipModeActive) { - // flip was successful, continue into normal flight without need to disarm/rearm - // note: preceding disarm will have set motors to normal rotation direction - crashFlipModeActive = false; - } else { - // when arming and not in crashflip mode, block entry to crashflip if delayed by the dshot beeper, - // otherwise consider only the switch position - crashFlipModeActive = (tryingToArm == ARMING_DELAYED_CRASHFLIP) ? false : IS_RC_MODE_ACTIVE(BOXCRASHFLIP); - } + // consider only the switch position + crashFlipModeActive = IS_RC_MODE_ACTIVE(BOXCRASHFLIP); setMotorSpinDirection(crashFlipModeActive ? DSHOT_CMD_SPIN_DIRECTION_REVERSED : DSHOT_CMD_SPIN_DIRECTION_NORMAL); } From 8fe88d4f4405d1344f4ac54159f7175f2902ea2a Mon Sep 17 00:00:00 2001 From: "Git bot (blckmn)" Date: Wed, 28 May 2025 06:25:03 +0000 Subject: [PATCH 219/244] Auto updated submodule references [28-05-2025] --- src/config | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/config b/src/config index 5947a7af8e..4136fa21f2 160000 --- a/src/config +++ b/src/config @@ -1 +1 @@ -Subproject commit 5947a7af8eed234fc9e1ad17294819ab966f5929 +Subproject commit 4136fa21f2902321caad438b73505caf0c64dda3 From 6b3bdef6fd4201fd46bc818777a8184bcd1d3831 Mon Sep 17 00:00:00 2001 From: "Git bot (blckmn)" Date: Fri, 30 May 2025 06:25:03 +0000 Subject: [PATCH 220/244] Auto updated submodule references [30-05-2025] --- src/config | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/config b/src/config index 4136fa21f2..0ce3bf0f2c 160000 --- a/src/config +++ b/src/config @@ -1 +1 @@ -Subproject commit 4136fa21f2902321caad438b73505caf0c64dda3 +Subproject commit 0ce3bf0f2c3749e93866a640f2af3fd6754db824 From 31e5644b560b09f19f9afe8e9e710f41604aa9f0 Mon Sep 17 00:00:00 2001 From: Petr Ledvina Date: Fri, 30 May 2025 18:54:54 +0200 Subject: [PATCH 221/244] rangefinderTF refactor + add TF-Nova (#14379) * Add rangefinder TF-Nova * fix * Return comments. Removed spaces * Removed invalid command. Expanded range * tfmini and tf02 united command for 100hz sampling * add aray and enum * add array and enum * RANGEFINDER - reafactor lidartf - use info array - rename some functions - init as for lidarMT - config lidar on initialization (functional change) * RANGEFINDER - common TF detection using rangefinderTYpe * prevent too frequent lidar reconf suggested by @coderabbitai * trace errors in debug * fix tfFrame length @coderabbitai * update public header @coderabbitai * Fix problems from upstream merge * RAngefinder - minor cleanup --------- Co-authored-by: LarryKarhu --- .../drivers/rangefinder/rangefinder_lidartf.c | 235 +++++++++--------- .../drivers/rangefinder/rangefinder_lidartf.h | 9 +- src/main/sensors/rangefinder.c | 24 +- 3 files changed, 120 insertions(+), 148 deletions(-) diff --git a/src/main/drivers/rangefinder/rangefinder_lidartf.c b/src/main/drivers/rangefinder/rangefinder_lidartf.c index 643b66694a..51e4043fa4 100644 --- a/src/main/drivers/rangefinder/rangefinder_lidartf.c +++ b/src/main/drivers/rangefinder/rangefinder_lidartf.c @@ -34,16 +34,24 @@ #include "drivers/rangefinder/rangefinder.h" #include "drivers/rangefinder/rangefinder_lidartf.h" -#define TF_DEVTYPE_NONE 0 -#define TF_DEVTYPE_MINI 1 -#define TF_DEVTYPE_02 2 -#define TF_DEVTYPE_NOVA 3 +typedef struct { + rangefinderType_e rfType; + uint16_t rangeMin; + uint16_t rangeMax; +} lidarTFInfo_t; -static uint8_t tfDevtype = TF_DEVTYPE_NONE; + +static const lidarTFInfo_t *devInfo = NULL; +static const lidarTFInfo_t devInfos[] = { + { .rfType = RANGEFINDER_TFMINI, .rangeMin = 40, .rangeMax = 1200}, + { .rfType = RANGEFINDER_TF02, .rangeMin = 40, .rangeMax = 2200}, + { .rfType = RANGEFINDER_TFNOVA, .rangeMin = 10, .rangeMax = 1400}, +}; #define TF_FRAME_LENGTH 6 // Excluding sync bytes (0x59) x 2 and checksum #define TF_FRAME_SYNC_BYTE 0x59 #define TF_TIMEOUT_MS (100 * 2) +#define TF_TASK_PERIOD_MS 10 // // Benewake TFmini frame format @@ -98,21 +106,10 @@ static uint8_t tfDevtype = TF_DEVTYPE_NONE; // Credibility // 1. If Confidence level < 90, unreliable // 2. If distance is 14m (1400cm), then OoR. -// + #define TF_NOVA_FRAME_CONFIDENCE 5 -// Maximum ratings - -#define TF_MINI_RANGE_MIN 40 -#define TF_MINI_RANGE_MAX 1200 - -#define TF_02_RANGE_MIN 40 -#define TF_02_RANGE_MAX 2200 - -#define TF_NOVA_RANGE_MIN 10 -#define TF_NOVA_RANGE_MAX 1400 - -#define TF_DETECTION_CONE_DECIDEGREES 900 +#define TF_DETECTION_CONE_DECIDEGREES 900 // TODO static serialPort_t *tfSerialPort = NULL; @@ -130,21 +127,35 @@ static uint8_t tfReceivePosition; // TFmini and TF02 // Command for 100Hz sampling (10msec interval) // At 100Hz scheduling, skew will cause 10msec delay at the most. -static const uint8_t tfCmd[] = { 0x42, 0x57, 0x02, 0x00, 0x00, 0x00, 0x01, 0x06 }; +// This command format does not match latest Benewake documentation +static const uint8_t tfConfigCmd[] = { 0x42, 0x57, 0x02, 0x00, 0x00, 0x00, 0x01, 0x06 }; -static int32_t lidarTFValue; -static uint16_t lidarTFerrors = 0; +static int lidarTFValue; +static unsigned lidarTFerrors = 0; -static void lidarTFSendCommand(void) + +static const lidarTFInfo_t* findInfo(rangefinderType_e rfType) { - switch (tfDevtype) { - case TF_DEVTYPE_MINI: - case TF_DEVTYPE_02: - serialWriteBuf(tfSerialPort, tfCmd, sizeof(tfCmd)); + for (const lidarTFInfo_t* p = devInfos; p < ARRAYEND(devInfos); p++) { + if (p->rfType == rfType) { + return p; + } + } + return NULL; +} + +// configure/reconfigure device +// may be called multiple times (when frames are missing) +static void lidarTFConfig(rangefinderDev_t *dev, const lidarTFInfo_t* inf) +{ + UNUSED(dev); + switch (inf->rfType) { + case RANGEFINDER_TFMINI: + case RANGEFINDER_TF02: + serialWriteBuf(tfSerialPort, tfConfigCmd, sizeof(tfConfigCmd)); break; default: break; - } } @@ -156,13 +167,54 @@ static void lidarTFInit(rangefinderDev_t *dev) tfReceivePosition = 0; } +static int tfProcessFrame(const uint8_t* frame, int len) +{ + UNUSED(len); + uint16_t distance = frame[0] | (frame[1] << 8); + uint16_t strength = frame[2] | (frame[3] << 8); + + DEBUG_SET(DEBUG_LIDAR_TF, 0, distance); // 0,1 + DEBUG_SET(DEBUG_LIDAR_TF, 1, strength); // 2,3 + DEBUG_SET(DEBUG_LIDAR_TF, 2, frame[4]); + DEBUG_SET(DEBUG_LIDAR_TF, 3, frame[5]); + + // common distance check + if (distance < devInfo->rangeMin || distance > devInfo->rangeMax) { + return RANGEFINDER_OUT_OF_RANGE; + } + + switch (devInfo->rfType) { + case RANGEFINDER_TFMINI: + if (frame[TF_MINI_FRAME_INTEGRAL_TIME] == 7) { + // When integral time is long (7), measured distance tends to be longer by 12~13. + distance -= 13; + } + break; + case RANGEFINDER_TF02: + if (frame[TF_02_FRAME_SIG] < 7) { + return RANGEFINDER_OUT_OF_RANGE; + + } + break; + case RANGEFINDER_TFNOVA: + if (frame[TF_NOVA_FRAME_CONFIDENCE] < 90) { + return RANGEFINDER_OUT_OF_RANGE; + } + break; + default: + return RANGEFINDER_HARDWARE_FAILURE; // internal error + } + // distance is valid + return distance; +} + static void lidarTFUpdate(rangefinderDev_t *dev) { - UNUSED(dev); static timeMs_t lastFrameReceivedMs = 0; + static timeMs_t lastReconfMs = 0; const timeMs_t timeNowMs = millis(); - if (tfSerialPort == NULL) { + if (tfSerialPort == NULL || devInfo == NULL) { return; } @@ -190,76 +242,37 @@ static void lidarTFUpdate(rangefinderDev_t *dev) } break; - case TF_FRAME_STATE_WAIT_CKSUM: - { - uint8_t cksum = TF_FRAME_SYNC_BYTE + TF_FRAME_SYNC_BYTE; - for (int i = 0; i < TF_FRAME_LENGTH; i++) { - cksum += tfFrame[i]; - } - - if (c == cksum) { - - uint16_t distance = tfFrame[0] | (tfFrame[1] << 8); - uint16_t strength = tfFrame[2] | (tfFrame[3] << 8); - - DEBUG_SET(DEBUG_LIDAR_TF, 0, distance); - DEBUG_SET(DEBUG_LIDAR_TF, 1, strength); - DEBUG_SET(DEBUG_LIDAR_TF, 2, tfFrame[4]); - DEBUG_SET(DEBUG_LIDAR_TF, 3, tfFrame[5]); - - switch (tfDevtype) { - case TF_DEVTYPE_MINI: - if (distance >= TF_MINI_RANGE_MIN && distance < TF_MINI_RANGE_MAX) { - lidarTFValue = distance; - if (tfFrame[TF_MINI_FRAME_INTEGRAL_TIME] == 7) { - // When integral time is long (7), measured distance tends to be longer by 12~13. - lidarTFValue -= 13; - } - } else { - lidarTFValue = -1; - } - break; - - case TF_DEVTYPE_02: - if (distance >= TF_02_RANGE_MIN && distance < TF_02_RANGE_MAX && tfFrame[TF_02_FRAME_SIG] >= 7) { - lidarTFValue = distance; - } else { - lidarTFValue = -1; - } - break; - - case TF_DEVTYPE_NOVA: - if (distance >= TF_NOVA_RANGE_MIN && distance <= TF_NOVA_RANGE_MAX && tfFrame[TF_NOVA_FRAME_CONFIDENCE] >= 90) { - lidarTFValue = distance; - } else { - lidarTFValue = -1; - } - break; - } - lastFrameReceivedMs = timeNowMs; - } else { - // Checksum error. Simply discard the current frame. - ++lidarTFerrors; - //DEBUG_SET(DEBUG_LIDAR_TF, 3, lidarTFerrors); - } + case TF_FRAME_STATE_WAIT_CKSUM: { + uint8_t cksum = TF_FRAME_SYNC_BYTE + TF_FRAME_SYNC_BYTE; // SYNC bytes are checksummed too, but not stored + for (int i = 0; i < TF_FRAME_LENGTH; i++) { + cksum += tfFrame[i]; } + if (c == cksum) { + lidarTFValue = tfProcessFrame(tfFrame, TF_FRAME_LENGTH); + lastFrameReceivedMs = timeNowMs; + } else { + // Checksum error. Simply ignore the current frame. + ++lidarTFerrors; + DEBUG_SET(DEBUG_LIDAR_TF, 4, lidarTFerrors); + } tfFrameState = TF_FRAME_STATE_WAIT_START1; tfReceivePosition = 0; - break; } + } } - // If valid frame hasn't been received for more than a timeout, resend command. - - if (timeNowMs - lastFrameReceivedMs > TF_TIMEOUT_MS) { - lidarTFSendCommand(); + // If valid frame hasn't been received for more than a timeout, try reinit. + if (cmp32(timeNowMs, lastFrameReceivedMs) > TF_TIMEOUT_MS + && cmp32(timeNowMs, lastReconfMs) > 500) { + lidarTFConfig(dev, devInfo); + lastReconfMs = timeNowMs; // delay sensor reconf } } // Return most recent device output in cm - +// TODO - handle timeout; return value only once (see lidarMT) static int32_t lidarTFGetDistance(rangefinderDev_t *dev) { UNUSED(dev); @@ -267,37 +280,25 @@ static int32_t lidarTFGetDistance(rangefinderDev_t *dev) return lidarTFValue; } -static bool lidarTFDetect(rangefinderDev_t *dev, uint8_t devtype) +bool lidarTFDetect(rangefinderDev_t *dev, rangefinderType_e rfType) { - const serialPortConfig_t *portConfig = findSerialPortConfig(FUNCTION_LIDAR_TF); + const lidarTFInfo_t* inf = findInfo(rfType); + if (!inf) { + return false; // supplied rfType is not TF + } + const serialPortConfig_t *portConfig = findSerialPortConfig(FUNCTION_LIDAR_TF); if (!portConfig) { return false; } tfSerialPort = openSerialPort(portConfig->identifier, FUNCTION_LIDAR_TF, NULL, NULL, 115200, MODE_RXTX, 0); - if (tfSerialPort == NULL) { return false; } - tfDevtype = devtype; - - dev->delayMs = 10; - switch (devtype) { - case TF_DEVTYPE_MINI: - dev->maxRangeCm = TF_MINI_RANGE_MAX; - break; - case TF_DEVTYPE_02: - dev->maxRangeCm = TF_02_RANGE_MAX; - break; - case TF_DEVTYPE_NOVA: - dev->maxRangeCm = TF_NOVA_RANGE_MAX; - break; - default: - dev->maxRangeCm = 0; - break; - } + dev->delayMs = TF_TASK_PERIOD_MS; + dev->maxRangeCm = inf->rangeMax; dev->detectionConeDeciDegrees = TF_DETECTION_CONE_DECIDEGREES; dev->detectionConeExtendedDeciDegrees = TF_DETECTION_CONE_DECIDEGREES; @@ -306,22 +307,12 @@ static bool lidarTFDetect(rangefinderDev_t *dev, uint8_t devtype) dev->update = &lidarTFUpdate; dev->read = &lidarTFGetDistance; + devInfo = inf; + + // configure device + lidarTFConfig(dev, devInfo); + return true; } -bool lidarTFminiDetect(rangefinderDev_t *dev) -{ - return lidarTFDetect(dev, TF_DEVTYPE_MINI); -} - -bool lidarTF02Detect(rangefinderDev_t *dev) -{ - return lidarTFDetect(dev, TF_DEVTYPE_02); -} - -bool lidarTFNovaDetect(rangefinderDev_t *dev) -{ - return lidarTFDetect(dev, TF_DEVTYPE_NOVA); -} - #endif diff --git a/src/main/drivers/rangefinder/rangefinder_lidartf.h b/src/main/drivers/rangefinder/rangefinder_lidartf.h index cd786a79bc..c84370dd4c 100644 --- a/src/main/drivers/rangefinder/rangefinder_lidartf.h +++ b/src/main/drivers/rangefinder/rangefinder_lidartf.h @@ -20,10 +20,7 @@ #pragma once -#include "common/time.h" +#include "drivers/rangefinder/rangefinder.h" +#include "sensors/rangefinder.h" -#define RANGEFINDER_TF_TASK_PERIOD_MS 10 - -bool lidarTFminiDetect(rangefinderDev_t *dev); -bool lidarTF02Detect(rangefinderDev_t *dev); -bool lidarTFNovaDetect(rangefinderDev_t *dev); +bool lidarTFDetect(rangefinderDev_t *dev, rangefinderType_e rfType); diff --git a/src/main/sensors/rangefinder.c b/src/main/sensors/rangefinder.c index e243b5027f..4c1ac78d69 100644 --- a/src/main/sensors/rangefinder.c +++ b/src/main/sensors/rangefinder.c @@ -109,29 +109,13 @@ static bool rangefinderDetect(rangefinderDev_t * dev, uint8_t rangefinderHardwar #endif break; +#if defined(USE_RANGEFINDER_TF) case RANGEFINDER_TFMINI: -#if defined(USE_RANGEFINDER_TF) - if (lidarTFminiDetect(dev)) { - rangefinderHardware = RANGEFINDER_TFMINI; - rescheduleTask(TASK_RANGEFINDER, TASK_PERIOD_MS(RANGEFINDER_TF_TASK_PERIOD_MS)); - } -#endif - break; - case RANGEFINDER_TF02: -#if defined(USE_RANGEFINDER_TF) - if (lidarTF02Detect(dev)) { - rangefinderHardware = RANGEFINDER_TF02; - rescheduleTask(TASK_RANGEFINDER, TASK_PERIOD_MS(RANGEFINDER_TF_TASK_PERIOD_MS)); - } -#endif - break; - case RANGEFINDER_TFNOVA: -#if defined(USE_RANGEFINDER_TF) - if (lidarTFNovaDetect(dev)) { - rangefinderHardware = RANGEFINDER_TFNOVA; - rescheduleTask(TASK_RANGEFINDER, TASK_PERIOD_MS(RANGEFINDER_TF_TASK_PERIOD_MS)); + if (lidarTFDetect(dev, rangefinderHardwareToUse)) { + rangefinderHardware = rangefinderHardwareToUse; + rescheduleTask(TASK_RANGEFINDER, TASK_PERIOD_MS(dev->delayMs)); } #endif break; From 2d81c87927ee8cb7719c04a2d5adebd0e338e74e Mon Sep 17 00:00:00 2001 From: Mark Haslinghuis Date: Fri, 30 May 2025 21:47:07 +0200 Subject: [PATCH 222/244] Improve 426xx detection time using soft reset (#14414) * Improve 426xx detection using softreset * Update src/main/drivers/accgyro/accgyro_spi_icm426xx.c Co-authored-by: Petr Ledvina * Update src/main/drivers/accgyro/accgyro_spi_icm426xx.c Co-authored-by: Petr Ledvina --------- Co-authored-by: Petr Ledvina --- src/main/drivers/accgyro/accgyro_spi_icm426xx.c | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/src/main/drivers/accgyro/accgyro_spi_icm426xx.c b/src/main/drivers/accgyro/accgyro_spi_icm426xx.c index 2a3a327e4d..b323d2211d 100644 --- a/src/main/drivers/accgyro/accgyro_spi_icm426xx.c +++ b/src/main/drivers/accgyro/accgyro_spi_icm426xx.c @@ -60,6 +60,10 @@ #define ICM426XX_CLKIN_FREQ 32000 +// Soft Reset +#define ICM426XX_RA_DEVICE_CONFIG 0x17 +#define DEVICE_CONFIG_SOFT_RESET_BIT (1 << 0) // Soft reset bit + #define ICM426XX_RA_REG_BANK_SEL 0x76 #define ICM426XX_BANK_SELECT0 0x00 #define ICM426XX_BANK_SELECT1 0x01 @@ -249,8 +253,19 @@ static void icm426xxEnableExternalClock(const extDevice_t *dev) } #endif +static void icm426xxSoftReset(const extDevice_t *dev) +{ + setUserBank(dev, ICM426XX_BANK_SELECT0); + + spiWriteReg(dev, ICM426XX_RA_DEVICE_CONFIG, DEVICE_CONFIG_SOFT_RESET_BIT); + + delay(1); +} + uint8_t icm426xxSpiDetect(const extDevice_t *dev) { + delay(1); // power-on time + icm426xxSoftReset(dev); spiWriteReg(dev, ICM426XX_RA_PWR_MGMT0, 0x00); #if defined(USE_GYRO_CLKIN) @@ -260,7 +275,7 @@ uint8_t icm426xxSpiDetect(const extDevice_t *dev) uint8_t icmDetected = MPU_NONE; uint8_t attemptsRemaining = 20; do { - delay(150); + delay(1); const uint8_t whoAmI = spiReadRegMsk(dev, MPU_RA_WHO_AM_I); switch (whoAmI) { case ICM42605_WHO_AM_I_CONST: From 62dd5f6e4cb0b1db8bc921eec2bbccbc50e9ad83 Mon Sep 17 00:00:00 2001 From: Steve Evans Date: Fri, 30 May 2025 20:55:04 +0100 Subject: [PATCH 223/244] Add missing OCTOX8P definition (#14418) --- src/main/cli/cli.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/src/main/cli/cli.c b/src/main/cli/cli.c index 8fd7d3aee2..e12cae2ae6 100644 --- a/src/main/cli/cli.c +++ b/src/main/cli/cli.c @@ -224,7 +224,8 @@ static const char * const mixerNames[] = { "FLYING_WING", "Y4", "HEX6X", "OCTOX8", "OCTOFLATP", "OCTOFLATX", "AIRPLANE", "HELI_120_CCPM", "HELI_90_DEG", "VTAIL4", "HEX6H", "PPM_TO_SERVO", "DUALCOPTER", "SINGLECOPTER", - "ATAIL4", "CUSTOM", "CUSTOMAIRPLANE", "CUSTOMTRI", "QUADX1234", NULL + "ATAIL4", "CUSTOM", "CUSTOMAIRPLANE", "CUSTOMTRI", "QUADX1234", + "OCTOX8P", NULL }; #endif @@ -5000,9 +5001,9 @@ static void cliRcSmoothing(const char *cmdName, char *cmdline) if (rcSmoothingAutoCalculate()) { cliPrint("# Detected Rx frequency: "); if (getRxRateValid()) { - cliPrintLinef("%dHz", lrintf(rcSmoothingData->smoothedRxRateHz)); + cliPrintLinef("%dHz", lrintf(rcSmoothingData->smoothedRxRateHz)); } else { - cliPrintLine("NO SIGNAL"); + cliPrintLine("NO SIGNAL"); } } cliPrintf("# Active setpoint cutoff: %dhz ", rcSmoothingData->setpointCutoffFrequency); From 98582c0c1894eaa1161e2385f13e9e540f43d402 Mon Sep 17 00:00:00 2001 From: Jay Blackman Date: Sat, 31 May 2025 13:35:39 +1000 Subject: [PATCH 224/244] Removing PICO directory, to be reinstated from RP2350 branch (#14413) --- src/main/drivers/io_def.h | 2 +- src/platform/PICO/link/pico_rp2350.ld | 302 ------------------ src/platform/PICO/mk/PICO.mk | 158 --------- src/platform/PICO/platform_mcu.h | 67 ---- .../startup/bs2_default_padded_checksummed.S | 25 -- src/platform/PICO/target/RP2350/.exclude | 0 src/platform/PICO/target/RP2350/target.h | 69 ---- src/platform/PICO/target/RP2350/target.mk | 2 - 8 files changed, 1 insertion(+), 624 deletions(-) delete mode 100644 src/platform/PICO/link/pico_rp2350.ld delete mode 100644 src/platform/PICO/mk/PICO.mk delete mode 100644 src/platform/PICO/platform_mcu.h delete mode 100644 src/platform/PICO/startup/bs2_default_padded_checksummed.S delete mode 100644 src/platform/PICO/target/RP2350/.exclude delete mode 100644 src/platform/PICO/target/RP2350/target.h delete mode 100644 src/platform/PICO/target/RP2350/target.mk diff --git a/src/main/drivers/io_def.h b/src/main/drivers/io_def.h index 8906c71b2a..2204005221 100644 --- a/src/main/drivers/io_def.h +++ b/src/main/drivers/io_def.h @@ -43,7 +43,7 @@ // split ioTag bits between pin and port // port is encoded as +1 to avoid collision with 0x0 (false as bool) -#ifndef DEFIO_PORT_PINS +#ifndef DEFIO_PORT_PINS // pins per port #define DEFIO_PORT_PINS 16 #endif diff --git a/src/platform/PICO/link/pico_rp2350.ld b/src/platform/PICO/link/pico_rp2350.ld deleted file mode 100644 index c8f3dd7c79..0000000000 --- a/src/platform/PICO/link/pico_rp2350.ld +++ /dev/null @@ -1,302 +0,0 @@ -/* Based on GCC ARM embedded samples. - Defines the following symbols for use by code: - __exidx_start - __exidx_end - __etext - __data_start__ - __preinit_array_start - __preinit_array_end - __init_array_start - __init_array_end - __fini_array_start - __fini_array_end - __data_end__ - __bss_start__ - __bss_end__ - __end__ - end - __HeapLimit - __StackLimit - __StackTop - __stack (== StackTop) -*/ - -MEMORY -{ - FLASH(rx) : ORIGIN = 0x10000000, LENGTH = 4m - RAM(rwx) : ORIGIN = 0x20000000, LENGTH = 512k - SCRATCH_X(rwx) : ORIGIN = 0x20080000, LENGTH = 4k - SCRATCH_Y(rwx) : ORIGIN = 0x20081000, LENGTH = 4k -} - -ENTRY(_entry_point) - -SECTIONS -{ - .flash_begin : { - __flash_binary_start = .; - } > FLASH - - /* The bootrom will enter the image at the point indicated in your - IMAGE_DEF, which is usually the reset handler of your vector table. - - The debugger will use the ELF entry point, which is the _entry_point - symbol, and in our case is *different from the bootrom's entry point.* - This is used to go back through the bootrom on debugger launches only, - to perform the same initial flash setup that would be performed on a - cold boot. - */ - - .text : { - __logical_binary_start = .; - KEEP (*(.vectors)) - KEEP (*(.binary_info_header)) - __binary_info_header_end = .; - KEEP (*(.embedded_block)) - __embedded_block_end = .; - KEEP (*(.reset)) - /* TODO revisit this now memset/memcpy/float in ROM */ - /* bit of a hack right now to exclude all floating point and time critical (e.g. memset, memcpy) code from - * FLASH ... we will include any thing excluded here in .data below by default */ - *(.init) - *libgcc.a:cmse_nonsecure_call.o - *(EXCLUDE_FILE(*libgcc.a: *libc.a:*lib_a-mem*.o *libm.a:) .text*) - *(.fini) - /* Pull all c'tors into .text */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - /* Followed by destructors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(SORT(.preinit_array.*))) - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - *(SORT(.fini_array.*)) - *(.fini_array) - PROVIDE_HIDDEN (__fini_array_end = .); - - *(.eh_frame*) - . = ALIGN(4); - } > FLASH - - /* Note the boot2 section is optional, and should be discarded if there is - no reference to it *inside* the binary, as it is not called by the - bootrom. (The bootrom performs a simple best-effort XIP setup and - leaves it to the binary to do anything more sophisticated.) However - there is still a size limit of 256 bytes, to ensure the boot2 can be - stored in boot RAM. - - Really this is a "XIP setup function" -- the name boot2 is historic and - refers to its dual-purpose on RP2040, where it also handled vectoring - from the bootrom into the user image. - */ - - .boot2 : { - __boot2_start__ = .; - *(.boot2) - __boot2_end__ = .; - } > FLASH - - ASSERT(__boot2_end__ - __boot2_start__ <= 256, - "ERROR: Pico second stage bootloader must be no more than 256 bytes in size") - - .rodata : { - *(EXCLUDE_FILE(*libgcc.a: *libc.a:*lib_a-mem*.o *libm.a:) .rodata*) - *(.srodata*) - . = ALIGN(4); - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.flashdata*))) - . = ALIGN(4); - } > FLASH - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - /* Machine inspectable binary information */ - . = ALIGN(4); - __binary_info_start = .; - .binary_info : - { - KEEP(*(.binary_info.keep.*)) - *(.binary_info.*) - } > FLASH - __binary_info_end = .; - . = ALIGN(4); - - .ram_vector_table (NOLOAD): { - *(.ram_vector_table) - } > RAM - - .uninitialized_data (NOLOAD): { - . = ALIGN(4); - *(.uninitialized_data*) - } > RAM - - .data : { - __data_start__ = .; - *(vtable) - - *(.time_critical*) - - /* remaining .text and .rodata; i.e. stuff we exclude above because we want it in RAM */ - *(.text*) - . = ALIGN(4); - *(.rodata*) - . = ALIGN(4); - - *(.data*) - *(.sdata*) - - . = ALIGN(4); - *(.after_data.*) - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__mutex_array_start = .); - KEEP(*(SORT(.mutex_array.*))) - KEEP(*(.mutex_array)) - PROVIDE_HIDDEN (__mutex_array_end = .); - - *(.jcr) - . = ALIGN(4); - } > RAM AT> FLASH - - .tdata : { - . = ALIGN(4); - *(.tdata .tdata.* .gnu.linkonce.td.*) - /* All data end */ - __tdata_end = .; - } > RAM AT> FLASH - PROVIDE(__data_end__ = .); - - /* __etext is (for backwards compatibility) the name of the .data init source pointer (...) */ - __etext = LOADADDR(.data); - - .tbss (NOLOAD) : { - . = ALIGN(4); - __bss_start__ = .; - __tls_base = .; - *(.tbss .tbss.* .gnu.linkonce.tb.*) - *(.tcommon) - - __tls_end = .; - } > RAM - - .bss (NOLOAD) : { - . = ALIGN(4); - __tbss_end = .; - - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.bss*))) - *(COMMON) - PROVIDE(__global_pointer$ = . + 2K); - *(.sbss*) - . = ALIGN(4); - __bss_end__ = .; - } > RAM - - .heap (NOLOAD): - { - __end__ = .; - end = __end__; - KEEP(*(.heap*)) - } > RAM - /* historically on GCC sbrk was growing past __HeapLimit to __StackLimit, however - to be more compatible, we now set __HeapLimit explicitly to where the end of the heap is */ - __HeapLimit = ORIGIN(RAM) + LENGTH(RAM); - - /* Start and end symbols must be word-aligned */ - .scratch_x : { - __scratch_x_start__ = .; - *(.scratch_x.*) - . = ALIGN(4); - __scratch_x_end__ = .; - } > SCRATCH_X AT > FLASH - __scratch_x_source__ = LOADADDR(.scratch_x); - - .scratch_y : { - __scratch_y_start__ = .; - *(.scratch_y.*) - . = ALIGN(4); - __scratch_y_end__ = .; - } > SCRATCH_Y AT > FLASH - __scratch_y_source__ = LOADADDR(.scratch_y); - - /* .stack*_dummy section doesn't contains any symbols. It is only - * used for linker to calculate size of stack sections, and assign - * values to stack symbols later - * - * stack1 section may be empty/missing if platform_launch_core1 is not used */ - - /* by default we put core 0 stack at the end of scratch Y, so that if core 1 - * stack is not used then all of SCRATCH_X is free. - */ - .stack1_dummy (NOLOAD): - { - *(.stack1*) - } > SCRATCH_X - .stack_dummy (NOLOAD): - { - KEEP(*(.stack*)) - } > SCRATCH_Y - - .flash_end : { - KEEP(*(.embedded_end_block*)) - PROVIDE(__flash_binary_end = .); - } > FLASH =0xaa - - /* stack limit is poorly named, but historically is maximum heap ptr */ - __StackLimit = ORIGIN(RAM) + LENGTH(RAM); - __StackOneTop = ORIGIN(SCRATCH_X) + LENGTH(SCRATCH_X); - __StackTop = ORIGIN(SCRATCH_Y) + LENGTH(SCRATCH_Y); - __StackOneBottom = __StackOneTop - SIZEOF(.stack1_dummy); - __StackBottom = __StackTop - SIZEOF(.stack_dummy); - PROVIDE(__stack = __StackTop); - - /* picolibc and LLVM */ - PROVIDE (__heap_start = __end__); - PROVIDE (__heap_end = __HeapLimit); - PROVIDE( __tls_align = MAX(ALIGNOF(.tdata), ALIGNOF(.tbss)) ); - PROVIDE( __tls_size_align = (__tls_size + __tls_align - 1) & ~(__tls_align - 1)); - PROVIDE( __arm32_tls_tcb_offset = MAX(8, __tls_align) ); - - /* llvm-libc */ - PROVIDE (_end = __end__); - PROVIDE (__llvm_libc_heap_limit = __HeapLimit); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed") - - ASSERT( __binary_info_header_end - __logical_binary_start <= 1024, "Binary info must be in first 1024 bytes of the binary") - ASSERT( __embedded_block_end - __logical_binary_start <= 4096, "Embedded block must be in first 4096 bytes of the binary") - - /* todo assert on extra code */ -} - diff --git a/src/platform/PICO/mk/PICO.mk b/src/platform/PICO/mk/PICO.mk deleted file mode 100644 index 699ee8f0fe..0000000000 --- a/src/platform/PICO/mk/PICO.mk +++ /dev/null @@ -1,158 +0,0 @@ -# -# Raspberry PICO Make file include -# - -ifeq ($(DEBUG_HARDFAULTS),PICO) -CFLAGS += -DDEBUG_HARDFAULTS -endif - -SDK_DIR = $(LIB_MAIN_DIR)/pico-sdk - -#CMSIS -CMSIS_DIR := $(SDK_DIR)/rp2_common/cmsis/stub/CMSIS - -#STDPERIPH -STDPERIPH_DIR = $(SDK_SIR) -STDPERIPH_SRC = \ - - -VPATH := $(VPATH):$(STDPERIPH_DIR) - -DEVICE_STDPERIPH_SRC := \ - $(STDPERIPH_SRC) \ - $(USBCORE_SRC) \ - $(USBCDC_SRC) \ - $(USBHID_SRC) \ - $(USBMSC_SRC) - -#CMSIS -VPATH := $(VPATH):$(CMSIS_DIR)/Core/Include:$(CMSIS_DIR)/Device/$(TARGET_MCU)/Include -CMSIS_SRC := - -#SRC -VPATH := $(VPATH):$(STDPERIPH_DIR) - -INCLUDE_DIRS := \ - $(INCLUDE_DIRS) \ - $(TARGET_PLATFORM_DIR) \ - $(TARGET_PLATFORM_DIR)/startup \ - $(SDK_DIR)/$(TARGET_MCU)/pico_platform/include \ - $(SDK_DIR)/$(TARGET_MCU)/hardware_regs/include \ - $(SDK_DIR)/$(TARGET_MCU)/hardware_structs/include \ - $(SDK_DIR)/common/pico_bit_ops_headers/include \ - $(SDK_DIR)/common/pico_base_headers/include \ - $(SDK_DIR)/common/boot_picoboot_headers/include \ - $(SDK_DIR)/common/pico_usb_reset_interface_headers/include \ - $(SDK_DIR)/common/pico_time/include \ - $(SDK_DIR)/common/boot_uf2_headers/include \ - $(SDK_DIR)/common/pico_divider_headers/include \ - $(SDK_DIR)/common/boot_picobin_headers/include \ - $(SDK_DIR)/common/pico_util/include \ - $(SDK_DIR)/common/pico_stdlib_headers/include \ - $(SDK_DIR)/common/hardware_claim/include \ - $(SDK_DIR)/common/pico_binary_info/include \ - $(SDK_DIR)/common/pico_sync/include \ - $(SDK_DIR)/rp2_common/pico_stdio_uart/include \ - $(SDK_DIR)/rp2_common/pico_stdio_usb/include \ - $(SDK_DIR)/rp2_common/pico_stdio_rtt/include \ - $(SDK_DIR)/rp2_common/tinyusb/include \ - $(SDK_DIR)/rp2_common/hardware_rtc/include \ - $(SDK_DIR)/rp2_common/hardware_boot_lock/include \ - $(SDK_DIR)/rp2_common/pico_mem_ops/include \ - $(SDK_DIR)/rp2_common/hardware_exception/include \ - $(SDK_DIR)/rp2_common/hardware_sync_spin_lock/include \ - $(SDK_DIR)/rp2_common/pico_runtime_init/include \ - $(SDK_DIR)/rp2_common/pico_standard_link/include \ - $(SDK_DIR)/rp2_common/hardware_pio/include \ - $(SDK_DIR)/rp2_common/pico_platform_compiler/include \ - $(SDK_DIR)/rp2_common/hardware_divider/include \ - $(SDK_DIR)/rp2_common/pico_bootsel_via_double_reset/include \ - $(SDK_DIR)/rp2_common/hardware_powman/include \ - $(SDK_DIR)/rp2_common/pico_btstack/include \ - $(SDK_DIR)/rp2_common/pico_cyw43_driver/include \ - $(SDK_DIR)/rp2_common/hardware_flash/include \ - $(SDK_DIR)/rp2_common/hardware_ticks/include \ - $(SDK_DIR)/rp2_common/hardware_dma/include \ - $(SDK_DIR)/rp2_common/pico_bit_ops/include \ - $(SDK_DIR)/rp2_common/hardware_clocks/include \ - $(SDK_DIR)/rp2_common/pico_unique_id/include \ - $(SDK_DIR)/rp2_common/hardware_dcp/include \ - $(SDK_DIR)/rp2_common/hardware_watchdog/include \ - $(SDK_DIR)/rp2_common/pico_rand/include \ - $(SDK_DIR)/rp2_common/hardware_hazard3/include \ - $(SDK_DIR)/rp2_common/hardware_uart/include \ - $(SDK_DIR)/rp2_common/hardware_interp/include \ - $(SDK_DIR)/rp2_common/pico_printf/include \ - $(SDK_DIR)/rp2_common/pico_aon_timer/include \ - $(SDK_DIR)/rp2_common/hardware_riscv_platform_timer/include \ - $(SDK_DIR)/rp2_common/pico_double/include \ - $(SDK_DIR)/rp2_common/pico_cyw43_arch/include \ - $(SDK_DIR)/rp2_common/hardware_vreg/include \ - $(SDK_DIR)/rp2_common/pico_mbedtls/include \ - $(SDK_DIR)/rp2_common/hardware_spi/include \ - $(SDK_DIR)/rp2_common/hardware_rcp/include \ - $(SDK_DIR)/rp2_common/hardware_riscv/include \ - $(SDK_DIR)/rp2_common/pico_standard_binary_info/include \ - $(SDK_DIR)/rp2_common/pico_i2c_slave/include \ - $(SDK_DIR)/rp2_common/pico_int64_ops/include \ - $(SDK_DIR)/rp2_common/pico_sha256/include \ - $(SDK_DIR)/rp2_common/hardware_irq/include \ - $(SDK_DIR)/rp2_common/pico_divider/include \ - $(SDK_DIR)/rp2_common/pico_flash/include \ - $(SDK_DIR)/rp2_common/hardware_sync/include \ - $(SDK_DIR)/rp2_common/pico_bootrom/include \ - $(SDK_DIR)/rp2_common/pico_crt0/include \ - $(SDK_DIR)/rp2_common/pico_clib_interface/include \ - $(SDK_DIR)/rp2_common/pico_stdio/include \ - $(SDK_DIR)/rp2_common/pico_runtime/include \ - $(SDK_DIR)/rp2_common/pico_time_adapter/include \ - $(SDK_DIR)/rp2_common/pico_platform_panic/include \ - $(SDK_DIR)/rp2_common/hardware_adc/include \ - $(SDK_DIR)/rp2_common/cmsis/include \ - $(SDK_DIR)/rp2_common/hardware_pll/include \ - $(SDK_DIR)/rp2_common/pico_platform_sections/include \ - $(SDK_DIR)/rp2_common/boot_bootrom_headers/include \ - $(SDK_DIR)/rp2_common/pico_fix/include \ - $(SDK_DIR)/rp2_common/pico_lwip/include \ - $(SDK_DIR)/rp2_common/hardware_base/include \ - $(SDK_DIR)/rp2_common/hardware_xosc/include \ - $(SDK_DIR)/rp2_common/pico_async_context/include \ - $(SDK_DIR)/rp2_common/hardware_pwm/include \ - $(SDK_DIR)/rp2_common/pico_stdio_semihosting/include \ - $(SDK_DIR)/rp2_common/pico_float/include \ - $(SDK_DIR)/rp2_common/hardware_resets/include \ - $(SDK_DIR)/rp2_common/pico_cxx_options/include \ - $(SDK_DIR)/rp2_common/pico_stdlib/include \ - $(SDK_DIR)/rp2_common/hardware_sha256/include \ - $(SDK_DIR)/rp2_common/hardware_i2c/include \ - $(SDK_DIR)/rp2_common/pico_atomic/include \ - $(SDK_DIR)/rp2_common/pico_multicore/include \ - $(SDK_DIR)/rp2_common/hardware_gpio/include \ - $(SDK_DIR)/rp2_common/pico_malloc/include \ - $(SDK_DIR)/rp2_common/hardware_timer/include \ - $(CMSIS_DIR)/Core/Include \ - $(CMSIS_DIR)/Device/$(TARGET_MCU)/Include - -#Flags -ARCH_FLAGS = -mthumb -mcpu=cortex-m33 -march=armv8-m.main+fp+dsp -mfloat-abi=softfp -mcmse - -DEVICE_FLAGS = - -ifeq ($(TARGET_MCU),RP2350) -DEVICE_FLAGS += -DRP2350 -DLIB_BOOT_STAGE2_HEADERS=1 -DLIB_PICO_ATOMIC=1 -DLIB_PICO_BIT_OPS=1 -DLIB_PICO_BIT_OPS_PICO=1 -DLIB_PICO_CLIB_INTERFACE=1 -DLIB_PICO_CRT0=1 -DLIB_PICO_CXX_OPTIONS=1 -DLIB_PICO_DIVIDER=1 -DLIB_PICO_DIVIDER_COMPILER=1 -DLIB_PICO_DOUBLE=1 -DLIB_PICO_DOUBLE_PICO=1 -DLIB_PICO_FLOAT=1 -DLIB_PICO_FLOAT_PICO=1 -DLIB_PICO_FLOAT_PICO_VFP=1 -DLIB_PICO_INT64_OPS=1 -DLIB_PICO_INT64_OPS_COMPILER=1 -DLIB_PICO_MALLOC=1 -DLIB_PICO_MEM_OPS=1 -DLIB_PICO_MEM_OPS_COMPILER=1 -DLIB_PICO_NEWLIB_INTERFACE=1 -DLIB_PICO_PLATFORM=1 -DLIB_PICO_PLATFORM_COMPILER=1 -DLIB_PICO_PLATFORM_PANIC=1 -DLIB_PICO_PLATFORM_SECTIONS=1 -DLIB_PICO_PRINTF=1 -DLIB_PICO_PRINTF_PICO=1 -DLIB_PICO_RUNTIME=1 -DLIB_PICO_RUNTIME_INIT=1 -DLIB_PICO_STANDARD_BINARY_INFO=1 -DLIB_PICO_STANDARD_LINK=1 -DLIB_PICO_STDIO=1 -DLIB_PICO_STDIO_UART=1 -DLIB_PICO_STDLIB=1 -DLIB_PICO_SYNC=1 -DLIB_PICO_SYNC_CRITICAL_SECTION=1 -DLIB_PICO_SYNC_MUTEX=1 -DLIB_PICO_SYNC_SEM=1 -DLIB_PICO_TIME=1 -DLIB_PICO_TIME_ADAPTER=1 -DLIB_PICO_UTIL=1 -DPICO_32BIT=1 -DPICO_BUILD=1 -DPICO_COPY_TO_RAM=0 -DPICO_CXX_ENABLE_EXCEPTIONS=0 -DPICO_NO_FLASH=0 -DPICO_NO_HARDWARE=0 -DPICO_ON_DEVICE=1 -DPICO_RP2350=1 -DPICO_USE_BLOCKED_RAM=0 -LD_SCRIPT = $(LINKER_DIR)/pico_rp2350.ld -STARTUP_SRC = startup/bs2_default_padded_checksummed.S -MCU_FLASH_SIZE = 4096 -# Override the OPTIMISE_SPEED compiler setting to save flash space on these 512KB targets. -# Performance is only slightly affected but around 50 kB of flash are saved. -OPTIMISE_SPEED = -O2 -else -$(error Unknown MCU for Raspberry PICO target) -endif - -DEVICE_FLAGS += -DHSE_VALUE=$(HSE_VALUE) -DPICO - -MCU_COMMON_SRC = \ - - -DEVICE_FLAGS += diff --git a/src/platform/PICO/platform_mcu.h b/src/platform/PICO/platform_mcu.h deleted file mode 100644 index 253dddd054..0000000000 --- a/src/platform/PICO/platform_mcu.h +++ /dev/null @@ -1,67 +0,0 @@ -/* - * This file is part of Betaflight. - * - * Betaflight is free software. You can redistribute this software - * and/or modify this software under the terms of the GNU General - * Public License as published by the Free Software Foundation, - * either version 3 of the License, or (at your option) any later - * version. - * - * Betaflight is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * - * See the GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public - * License along with this software. - * - * If not, see . - */ - -#pragma once - -#if defined(RP2350) - -#include "RP2350.h" - -typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; - -#define I2C_TypeDef I2C0_Type -//#define I2C_HandleTypeDef -#define GPIO_TypeDef IO_BANK0_Type -//#define GPIO_InitTypeDef -#define TIM_TypeDef TIMER0_Type -//#define TIM_OCInitTypeDef -#define DMA_TypeDef DMA_Type -//#define DMA_InitTypeDef -//#define DMA_Channel_TypeDef -#define SPI_TypeDef SPI0_Type -#define ADC_TypeDef ADC_Type -#define USART_TypeDef UART0_Type -#define TIM_OCInitTypeDef TIMER0_Type -#define TIM_ICInitTypeDef TIMER0_Type -//#define TIM_OCStructInit -//#define TIM_Cmd -//#define TIM_CtrlPWMOutputs -//#define TIM_TimeBaseInit -//#define TIM_ARRPreloadConfig -//#define SystemCoreClock -//#define EXTI_TypeDef -//#define EXTI_InitTypeDef - - -#endif - -#define DEFAULT_CPU_OVERCLOCK 0 -#define TASK_GYROPID_DESIRED_PERIOD 125 // 125us = 8kHz -#define SCHEDULER_DELAY_LIMIT 10 - -#define IOCFG_OUT_PP 0 -#define IOCFG_OUT_OD 0 -#define IOCFG_AF_PP 0 -#define IOCFG_AF_OD 0 -#define IOCFG_IPD 0 -#define IOCFG_IPU 0 -#define IOCFG_IN_FLOATING 0 - diff --git a/src/platform/PICO/startup/bs2_default_padded_checksummed.S b/src/platform/PICO/startup/bs2_default_padded_checksummed.S deleted file mode 100644 index 124bd8d265..0000000000 --- a/src/platform/PICO/startup/bs2_default_padded_checksummed.S +++ /dev/null @@ -1,25 +0,0 @@ -// Padded and checksummed version of: /home/black/src/pico/hello/build/pico-sdk/src/rp2350/boot_stage2/bs2_default.bin - -.cpu cortex-m0plus -.thumb - -.section .boot2, "ax" - -.global __boot2_entry_point -__boot2_entry_point: -.byte 0x00, 0xb5, 0x24, 0x4b, 0x21, 0x20, 0x58, 0x60, 0x13, 0xf5, 0x40, 0x53, 0x02, 0x20, 0x98, 0x60 -.byte 0xd8, 0x60, 0x18, 0x61, 0x58, 0x61, 0x13, 0xf5, 0x0d, 0x23, 0x1f, 0x49, 0x19, 0x60, 0x18, 0x68 -.byte 0x10, 0xf0, 0x02, 0x0f, 0xfb, 0xd1, 0x35, 0x20, 0x00, 0xf0, 0x2c, 0xf8, 0x02, 0x28, 0x14, 0xd0 -.byte 0x06, 0x20, 0x58, 0x60, 0x00, 0xf0, 0x22, 0xf8, 0x98, 0x68, 0x01, 0x20, 0x58, 0x60, 0x00, 0x20 -.byte 0x58, 0x60, 0x02, 0x20, 0x58, 0x60, 0x00, 0xf0, 0x19, 0xf8, 0x98, 0x68, 0x98, 0x68, 0x98, 0x68 -.byte 0x05, 0x20, 0x00, 0xf0, 0x17, 0xf8, 0x40, 0x08, 0xfa, 0xd2, 0x31, 0xf0, 0x01, 0x01, 0x19, 0x60 -.byte 0x0e, 0x48, 0xd8, 0x60, 0x4a, 0xf2, 0xeb, 0x00, 0x58, 0x61, 0x0d, 0x48, 0x18, 0x61, 0x4f, 0xf0 -.byte 0xa0, 0x51, 0x09, 0x78, 0x20, 0xf4, 0x80, 0x50, 0x18, 0x61, 0x00, 0xbd, 0x18, 0x68, 0x80, 0x08 -.byte 0xfc, 0xd2, 0x70, 0x47, 0x00, 0xb5, 0x58, 0x60, 0x58, 0x60, 0xff, 0xf7, 0xf7, 0xff, 0x98, 0x68 -.byte 0x98, 0x68, 0x00, 0xbd, 0x00, 0x00, 0x04, 0x40, 0x41, 0x00, 0x80, 0x07, 0x02, 0x02, 0x00, 0x40 -.byte 0xa8, 0x92, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 -.byte 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 -.byte 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 -.byte 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 -.byte 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 -.byte 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 diff --git a/src/platform/PICO/target/RP2350/.exclude b/src/platform/PICO/target/RP2350/.exclude deleted file mode 100644 index e69de29bb2..0000000000 diff --git a/src/platform/PICO/target/RP2350/target.h b/src/platform/PICO/target/RP2350/target.h deleted file mode 100644 index f7b9076ccc..0000000000 --- a/src/platform/PICO/target/RP2350/target.h +++ /dev/null @@ -1,69 +0,0 @@ -/* - * This file is part of Betaflight. - * - * Betaflight is free software. You can redistribute this software - * and/or modify this software under the terms of the GNU General - * Public License as published by the Free Software Foundation, - * either version 3 of the License, or (at your option) any later - * version. - * - * Betaflight is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * - * See the GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public - * License along with this software. - * - * If not, see . - */ - -#pragma once - -#ifndef TARGET_BOARD_IDENTIFIER -#define TARGET_BOARD_IDENTIFIER "R235" -#endif - -#ifndef USBD_PRODUCT_STRING -#define USBD_PRODUCT_STRING "Betaflight RP2350" -#endif - -#undef USE_DMA -#undef USE_FLASH -#undef USE_FLASH_CHIP - -#undef USE_TIMER -#undef USE_SPI -#undef USE_I2C -#undef USE_UART -#undef USE_DSHOT -#undef USE_RCC - -#define GPIOA_BASE ((intptr_t)0x0001) - -#define TARGET_IO_PORTA 0xffff -#define TARGET_IO_PORTB 0xffff -#define TARGET_IO_PORTC 0xffff -#define TARGET_IO_PORTD 0xffff -#define TARGET_IO_PORTE 0xffff -#define TARGET_IO_PORTF 0xffff - -#undef USE_FLASH -#undef USE_FLASH_CHIP -#undef USE_FLASH_M25P16 -#undef USE_FLASH_W25N01G -#undef USE_FLASH_W25N02K -#undef USE_FLASH_W25M -#undef USE_FLASH_W25M512 -#undef USE_FLASH_W25M02G -#undef USE_FLASH_W25Q128FV -#undef USE_FLASH_PY25Q128HA -#undef USE_FLASH_W25Q64FV - -#define FLASH_PAGE_SIZE 0x1000 -#define CONFIG_IN_RAM - -#define U_ID_0 0 -#define U_ID_1 1 -#define U_ID_2 2 diff --git a/src/platform/PICO/target/RP2350/target.mk b/src/platform/PICO/target/RP2350/target.mk deleted file mode 100644 index 94f4209a29..0000000000 --- a/src/platform/PICO/target/RP2350/target.mk +++ /dev/null @@ -1,2 +0,0 @@ -TARGET_MCU := RP2350 -TARGET_MCU_FAMILY := PICO From 5f539935eaf3ea25e5546cfa8a361effdb0a39a0 Mon Sep 17 00:00:00 2001 From: "Git bot (blckmn)" Date: Sat, 31 May 2025 06:25:03 +0000 Subject: [PATCH 225/244] Auto updated submodule references [31-05-2025] --- src/config | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/config b/src/config index 0ce3bf0f2c..eda6b30999 160000 --- a/src/config +++ b/src/config @@ -1 +1 @@ -Subproject commit 0ce3bf0f2c3749e93866a640f2af3fd6754db824 +Subproject commit eda6b309994923772eeab82fce3d6d8c3c0812a2 From f26efcc622b2b07c0c87a1bf7df8796c9903712d Mon Sep 17 00:00:00 2001 From: Mark Haslinghuis Date: Sat, 31 May 2025 11:38:35 +0200 Subject: [PATCH 226/244] Fix ICM40609D reset register (#14415) --- src/main/drivers/accgyro/accgyro_spi_icm40609.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/drivers/accgyro/accgyro_spi_icm40609.c b/src/main/drivers/accgyro/accgyro_spi_icm40609.c index 5ed6c8eb73..ed45cdb668 100644 --- a/src/main/drivers/accgyro/accgyro_spi_icm40609.c +++ b/src/main/drivers/accgyro/accgyro_spi_icm40609.c @@ -243,7 +243,7 @@ #define ICM40609_ACCEL_DATA_X1_UI 0x1F #define ICM40609_GYRO_DATA_X1_UI 0x25 -#define ICM40609_RESET_REG 0x4C +#define ICM40609_RESET_REG 0x11 #define ICM40609_SOFT_RESET_VAL 0x01 #ifndef ICM40609_LOCK From 1dcc61138813a9e0f20f01664f7b7cae66f97957 Mon Sep 17 00:00:00 2001 From: Jay Blackman Date: Sun, 1 Jun 2025 04:53:54 +1000 Subject: [PATCH 227/244] PICO: Makefile uf2 support using picotool (#14402) * Adding picotool build recipe in makefiles. * Use semaphore in directory for default goal recipe for target * Suggestions from coderabbitai * Further coderabbit suggestions * Wrong case * Minor change to improve logic * Further improvements. - submodules replaced with specific submodule for pico_sdk (to avoid all developers needing this) * Removing need for remote on git submodule update for configs, as we have the commit occurring daily. - made sure config also build uf2 * Simplified firmware output selection for target * Moved UF2 outside of EXST * Missed two remnants of HEX_TARGETS * Adding check for target * As target is known default output can be set in platform mk file or target mk file - no need for file indicator (i.e. .exe or .uf2) * Update config.mk for less verbosity --- Makefile | 141 +++++++++++++++++------------- mk/build_verbosity.mk | 1 + mk/config.mk | 12 +-- mk/tools.mk | 51 +++++++++++ src/platform/SIMULATOR/mk/SITL.mk | 4 + 5 files changed, 142 insertions(+), 67 deletions(-) diff --git a/Makefile b/Makefile index 7be4e6a6d2..c6d2c6463d 100644 --- a/Makefile +++ b/Makefile @@ -15,7 +15,7 @@ # Things that the user might override on the commandline # -# The target to build, see BASE_TARGETS/EXE_TARGETS below +# The target or config to build TARGET ?= CONFIG ?= @@ -57,7 +57,11 @@ CFLAGS_DISABLED := FORKNAME = betaflight # Working directories +# ROOT_DIR is the full path to the directory containing this Makefile +ROOT_DIR := $(realpath $(dir $(abspath $(lastword $(MAKEFILE_LIST))))) +# ROOT is the relative path to the directory containing this Makefile ROOT := $(patsubst %/,%,$(dir $(lastword $(MAKEFILE_LIST)))) + PLATFORM_DIR := $(ROOT)/src/platform SRC_DIR := $(ROOT)/src/main LIB_MAIN_DIR := $(ROOT)/lib/main @@ -90,12 +94,9 @@ MAKE_PARALLEL = $(if $(filter -j%, $(MAKEFLAGS)),$(EMPTY),-j$(DEFAULT_PAR # pre-build sanity checks include $(MAKE_SCRIPT_DIR)/checks.mk -# list of targets that are executed on host (using exe as goal) -EXE_TARGETS := SITL - # basic target list PLATFORMS := $(sort $(notdir $(patsubst /%,%, $(wildcard $(PLATFORM_DIR)/*)))) -BASE_TARGETS := $(filter-out $(EXE_TARGETS),$(sort $(notdir $(patsubst %/,%,$(dir $(wildcard $(PLATFORM_DIR)/*/target/*/target.mk)))))) +BASE_TARGETS := $(sort $(notdir $(patsubst %/,%,$(dir $(wildcard $(PLATFORM_DIR)/*/target/*/target.mk))))) # configure some directories that are relative to wherever ROOT_DIR is located TOOLS_DIR ?= $(ROOT)/tools @@ -126,7 +127,7 @@ FC_VER_PATCH := $(shell grep " FC_VERSION_PATCH" src/main/build/version.h | awk FC_VER := $(FC_VER_MAJOR).$(FC_VER_MINOR).$(FC_VER_PATCH) -# import config handling +# import config handling (must occur after the hydration of hex, exe and uf2 targets) include $(MAKE_SCRIPT_DIR)/config.mk # default xtal value @@ -134,7 +135,7 @@ HSE_VALUE ?= 8000000 CI_EXCLUDED_TARGETS := $(sort $(notdir $(patsubst %/,%,$(dir $(wildcard $(PLATFORM_DIR)/*/target/*/.exclude))))) CI_COMMON_TARGETS := STM32F4DISCOVERY CRAZYBEEF4SX1280 CRAZYBEEF4FR MATEKF405TE AIRBOTG4AIO TBS_LUCID_FC IFLIGHT_BLITZ_F722 NUCLEOF446 SPRACINGH7EXTREME SPRACINGH7RF -CI_TARGETS := $(filter-out $(CI_EXCLUDED_TARGETS), $(BASE_TARGETS) $(EXE_TARGETS)) $(filter $(CI_COMMON_TARGETS), $(BASE_CONFIGS)) +CI_TARGETS := $(filter-out $(CI_EXCLUDED_TARGETS), $(BASE_TARGETS) $(filter $(CI_COMMON_TARGETS), $(BASE_CONFIGS))) PREVIEW_TARGETS := MATEKF411 AIKONF4V2 AIRBOTG4AIO ZEEZF7V3 FOXEERF745V4_AIO KAKUTEH7 TBS_LUCID_FC SITL SPRACINGH7EXTREME SPRACINGH7RF TARGET_PLATFORM := $(notdir $(patsubst %/,%,$(subst target/$(TARGET)/,, $(dir $(wildcard $(PLATFORM_DIR)/*/target/$(TARGET)/target.mk))))) @@ -142,7 +143,8 @@ TARGET_PLATFORM_DIR := $(PLATFORM_DIR)/$(TARGET_PLATFORM) LINKER_DIR := $(TARGET_PLATFORM_DIR)/link ifneq ($(TARGET),) -include $(TARGET_PLATFORM_DIR)/target/$(TARGET)/target.mk +TARGET_DIR = $(TARGET_PLATFORM_DIR)/target/$(TARGET) +include $(TARGET_DIR)/target.mk endif REVISION := norevision @@ -221,24 +223,17 @@ ifneq ($(HSE_VALUE),) DEVICE_FLAGS := $(DEVICE_FLAGS) -DHSE_VALUE=$(HSE_VALUE) endif -TARGET_DIR = $(TARGET_PLATFORM_DIR)/target/$(TARGET) endif # TARGET specified +ifeq ($(or $(CONFIG),$(TARGET)),) +.DEFAULT_GOAL := all +else +.DEFAULT_GOAL := fwo +endif + # openocd specific includes include $(MAKE_SCRIPT_DIR)/openocd.mk -ifeq ($(CONFIG),) -ifeq ($(TARGET),) -.DEFAULT_GOAL := all -else ifneq ($(filter $(TARGET),$(EXE_TARGETS)),) -.DEFAULT_GOAL := exe -else -.DEFAULT_GOAL := hex -endif -else # ifeq ($(CONFIG),) -.DEFAULT_GOAL := hex -endif - INCLUDE_DIRS := $(INCLUDE_DIRS) \ $(ROOT)/lib/main/MAVLink @@ -364,6 +359,12 @@ CPPCHECK = cppcheck $(CSOURCES) --enable=all --platform=unix64 \ $(addprefix -isystem,$(SYS_INCLUDE_DIRS)) \ -I/usr/include -I/usr/include/linux +ifneq ($(filter fwo hex uf2 bin elf zip, $(MAKECMDGOALS)),) + ifeq ($(TARGET),) + $(error "You must specify a target to build.") + endif +endif + TARGET_NAME := $(TARGET) ifneq ($(CONFIG),) @@ -378,21 +379,22 @@ TARGET_FULLNAME = $(FORKNAME)_$(FC_VER)_$(TARGET_NAME) # # Things we will build # -TARGET_BIN = $(BIN_DIR)/$(TARGET_FULLNAME).bin -TARGET_HEX = $(BIN_DIR)/$(TARGET_FULLNAME).hex -TARGET_EXE = $(BIN_DIR)/$(TARGET_FULLNAME) -TARGET_DFU = $(BIN_DIR)/$(TARGET_FULLNAME).dfu -TARGET_ZIP = $(BIN_DIR)/$(TARGET_FULLNAME).zip -TARGET_OBJ_DIR = $(OBJECT_DIR)/$(TARGET_NAME) -TARGET_ELF = $(OBJECT_DIR)/$(FORKNAME)_$(TARGET_NAME).elf -TARGET_EXST_ELF = $(OBJECT_DIR)/$(FORKNAME)_$(TARGET_NAME)_EXST.elf -TARGET_UNPATCHED_BIN = $(OBJECT_DIR)/$(FORKNAME)_$(TARGET_NAME)_UNPATCHED.bin -TARGET_LST = $(OBJECT_DIR)/$(FORKNAME)_$(TARGET_NAME).lst -TARGET_OBJS = $(addsuffix .o,$(addprefix $(TARGET_OBJ_DIR)/,$(basename $(SRC)))) -TARGET_DEPS = $(addsuffix .d,$(addprefix $(TARGET_OBJ_DIR)/,$(basename $(SRC)))) -TARGET_MAP = $(OBJECT_DIR)/$(FORKNAME)_$(TARGET_NAME).map +TARGET_BIN := $(BIN_DIR)/$(TARGET_FULLNAME).bin +TARGET_HEX := $(BIN_DIR)/$(TARGET_FULLNAME).hex +TARGET_UF2 := $(BIN_DIR)/$(TARGET_FULLNAME).uf2 +TARGET_EXE := $(BIN_DIR)/$(TARGET_FULLNAME) +TARGET_DFU := $(BIN_DIR)/$(TARGET_FULLNAME).dfu +TARGET_ZIP := $(BIN_DIR)/$(TARGET_FULLNAME).zip +TARGET_OBJ_DIR := $(OBJECT_DIR)/$(TARGET_NAME) +TARGET_ELF := $(OBJECT_DIR)/$(FORKNAME)_$(TARGET_NAME).elf +TARGET_EXST_ELF := $(OBJECT_DIR)/$(FORKNAME)_$(TARGET_NAME)_EXST.elf +TARGET_UNPATCHED_BIN := $(OBJECT_DIR)/$(FORKNAME)_$(TARGET_NAME)_UNPATCHED.bin +TARGET_LST := $(OBJECT_DIR)/$(FORKNAME)_$(TARGET_NAME).lst +TARGET_OBJS := $(addsuffix .o,$(addprefix $(TARGET_OBJ_DIR)/,$(basename $(SRC)))) +TARGET_DEPS := $(addsuffix .d,$(addprefix $(TARGET_OBJ_DIR)/,$(basename $(SRC)))) +TARGET_MAP := $(OBJECT_DIR)/$(FORKNAME)_$(TARGET_NAME).map -TARGET_EXST_HASH_SECTION_FILE = $(TARGET_OBJ_DIR)/exst_hash_section.bin +TARGET_EXST_HASH_SECTION_FILE := $(TARGET_OBJ_DIR)/exst_hash_section.bin ifeq ($(DEBUG_MIXED),yes) TARGET_EF_HASH := $(shell echo -n -- "$(EXTRA_FLAGS)" "$(OPTIONS)" "$(DEVICE_FLAGS)" "$(TARGET_FLAGS)" | openssl dgst -md5 -r | awk '{print $$1;}') @@ -407,6 +409,7 @@ CLEAN_ARTIFACTS += $(TARGET_HEX_REV) $(TARGET_HEX) CLEAN_ARTIFACTS += $(TARGET_ELF) $(TARGET_OBJS) $(TARGET_MAP) CLEAN_ARTIFACTS += $(TARGET_LST) CLEAN_ARTIFACTS += $(TARGET_DFU) +CLEAN_ARTIFACTS += $(TARGET_UF2) # Make sure build date and revision is updated on every incremental build $(TARGET_OBJ_DIR)/build/version.o : $(SRC) @@ -482,8 +485,12 @@ $(TARGET_ELF): $(TARGET_OBJS) $(LD_SCRIPT) $(LD_SCRIPTS) $(V1) $(CROSS_CC) -o $@ $(filter-out %.ld,$^) $(LD_FLAGS) $(V1) $(SIZE) $(TARGET_ELF) +$(TARGET_UF2): $(TARGET_ELF) + @echo "Creating UF2 $(TARGET_UF2)" "$(STDOUT)" + $(V1) $(PICOTOOL) uf2 convert $< $@ || { echo "Failed to convert ELF to UF2 format"; exit 1; } + $(TARGET_EXE): $(TARGET_ELF) - @echo Copy $< to $@ "$(STDOUT)" + @echo "Creating exe - copying $< to $@" "$(STDOUT)" $(V1) cp $< $@ # Compile @@ -539,17 +546,11 @@ $(TARGET_OBJ_DIR)/%.o: %.S ## all : Build all currently built targets all: $(CI_TARGETS) +.PHONY: $(BASE_TARGETS) $(BASE_TARGETS): - $(V0) @echo "Building target $@" && \ - $(MAKE) hex TARGET=$@ && \ - echo "Building $@ succeeded." + $(MAKE) fwo TARGET=$@ -$(EXE_TARGETS): - $(V0) @echo "Building executable target $@" && \ - $(MAKE) exe TARGET=$@ && \ - echo "Building $@ succeeded." - -TARGETS_CLEAN = $(addsuffix _clean,$(BASE_TARGETS) $(EXE_TARGETS)) +TARGETS_CLEAN = $(addsuffix _clean,$(BASE_TARGETS)) CONFIGS_CLEAN = $(addsuffix _clean,$(BASE_CONFIGS)) @@ -625,39 +626,56 @@ endif TARGETS_ZIP = $(addsuffix _zip,$(BASE_TARGETS)) ## _zip : build target and zip it (useful for posting to GitHub) +.PHONY: $(TARGETS_ZIP) $(TARGETS_ZIP): - $(V0) $(MAKE) hex TARGET=$(subst _zip,,$@) - $(V0) $(MAKE) zip TARGET=$(subst _zip,,$@) + $(V1) $(MAKE) $(MAKE_PARALLEL) zip TARGET=$(subst _zip,,$@) -zip: - $(V0) zip $(TARGET_ZIP) $(TARGET_HEX) +.PHONY: zip +zip: $(TARGET_HEX) + $(V1) zip $(TARGET_ZIP) $(TARGET_HEX) +.PHONY: binary binary: - $(V0) $(MAKE) $(MAKE_PARALLEL) $(TARGET_BIN) + $(V1) $(MAKE) $(MAKE_PARALLEL) $(TARGET_BIN) +.PHONY: hex hex: - $(V0) $(MAKE) $(MAKE_PARALLEL) $(TARGET_HEX) + $(V1) $(MAKE) $(MAKE_PARALLEL) $(TARGET_HEX) -.phony: exe +.PHONY: uf2 +uf2: + $(V1) $(MAKE) $(MAKE_PARALLEL) $(TARGET_UF2) + +.PHONY: exe exe: $(TARGET_EXE) -TARGETS_REVISION = $(addsuffix _rev,$(BASE_TARGETS)) +# FWO (Firmware Output) is the default output for building the firmware +.PHONY: fwo +fwo: +ifeq ($(DEFAULT_OUTPUT),exe) + $(V1) $(MAKE) exe +else ifeq ($(DEFAULT_OUTPUT),uf2) + $(V1) $(MAKE) uf2 +else + $(V1) $(MAKE) hex +endif + +TARGETS_REVISION = $(addsuffix _rev, $(BASE_TARGETS)) ## _rev : build target and add revision to filename +.PHONY: $(TARGETS_REVISION) $(TARGETS_REVISION): - $(V0) $(MAKE) hex REV=yes TARGET=$(subst _rev,,$@) + $(V1) $(MAKE) fwo REV=yes TARGET=$(subst _rev,,$@) -EXE_TARGETS_REVISION = $(addsuffix _rev,$(EXE_TARGETS)) -## _rev : build executable target and add revision to filename -$(EXE_TARGETS_REVISION): - $(V0) $(MAKE) exe REV=yes TARGET=$(subst _rev,,$@) - -all_rev: $(addsuffix _rev,$(CI_TARGETS)) +.PHONY: all_rev +all_rev: $(addsuffix _rev, $(CI_TARGETS)) +.PHONY: unbrick_$(TARGET) unbrick_$(TARGET): $(TARGET_HEX) $(V0) stty -F $(SERIAL_DEVICE) raw speed 115200 -crtscts cs8 -parenb -cstopb -ixon $(V0) stm32flash -w $(TARGET_HEX) -v -g 0x0 -b 115200 $(SERIAL_DEVICE) ## unbrick : unbrick flight controller +.PHONY: unbrick unbrick: unbrick_$(TARGET) ## cppcheck : run static analysis on C source code @@ -690,7 +708,7 @@ help: Makefile mk/tools.mk @echo "To populate configuration targets:" @echo " make configs" @echo "" - @echo "Valid TARGET values are: $(EXE_TARGETS) $(BASE_TARGETS)" + @echo "Valid TARGET values are: $(BASE_TARGETS)" @echo "" @sed -n 's/^## //p' $? @@ -698,7 +716,6 @@ help: Makefile mk/tools.mk targets: @echo "Platforms: $(PLATFORMS)" @echo "Valid targets: $(BASE_TARGETS)" - @echo "Executable targets: $(EXE_TARGETS)" @echo "Built targets: $(CI_TARGETS)" @echo "Default target: $(TARGET)" @echo "CI common targets: $(CI_COMMON_TARGETS)" diff --git a/mk/build_verbosity.mk b/mk/build_verbosity.mk index 9d2f5dc3f3..c1c6206b43 100644 --- a/mk/build_verbosity.mk +++ b/mk/build_verbosity.mk @@ -9,6 +9,7 @@ ifndef V export V0 := export V1 := $(AT) export STDOUT := +export MAKE := $(MAKE) --no-print-directory else ifeq ($(V), 0) export V0 := $(AT) export V1 := $(AT) diff --git a/mk/config.mk b/mk/config.mk index 5f85d4987d..d1c9e54c65 100644 --- a/mk/config.mk +++ b/mk/config.mk @@ -57,21 +57,23 @@ endif #config .PHONY: configs configs: ifeq ($(shell realpath $(CONFIG_DIR)),$(shell realpath $(CONFIGS_SUBMODULE_DIR))) - git submodule update --init --remote -- $(CONFIGS_SUBMODULE_DIR) + @echo "Updating config submodule: $(CONFIGS_SUBMODULE_DIR)" + $(V1) git submodule update --init -- $(CONFIGS_SUBMODULE_DIR) || { echo "Config submodule update failed. Please check your git configuration."; exit 1; } + @echo "Submodule update succeeded." else ifeq ($(wildcard $(CONFIG_DIR)),) @echo "Hydrating clone for configs: $(CONFIG_DIR)" - $(V0) git clone $(CONFIGS_REPO_URL) $(CONFIG_DIR) + $(V1) git clone $(CONFIGS_REPO_URL) $(CONFIG_DIR) else - $(V0) git -C $(CONFIG_DIR) pull origin + $(V1) git -C $(CONFIG_DIR) pull origin endif endif $(BASE_CONFIGS): @echo "Building target config $@" - $(V0) $(MAKE) $(MAKE_PARALLEL) hex CONFIG=$@ + $(V0) $(MAKE) fwo CONFIG=$@ @echo "Building target config $@ succeeded." ## _rev : build configured target and add revision to filename $(addsuffix _rev,$(BASE_CONFIGS)): - $(V0) $(MAKE) $(MAKE_PARALLEL) hex CONFIG=$(subst _rev,,$@) REV=yes + $(V0) $(MAKE) fwo CONFIG=$(subst _rev,,$@) REV=yes diff --git a/mk/tools.mk b/mk/tools.mk index 3dc42ab47a..0b53aedecb 100644 --- a/mk/tools.mk +++ b/mk/tools.mk @@ -331,3 +331,54 @@ breakpad_clean: $(V1) [ ! -d "$(BREAKPAD_DIR)" ] || $(RM) -rf $(BREAKPAD_DIR) @echo " CLEAN $(BREAKPAD_DL_FILE)" $(V1) $(RM) -f $(BREAKPAD_DL_FILE) + +# Raspberry Pi Pico tools +PICOTOOL_REPO := https://github.com/raspberrypi/picotool.git +PICOTOOL_DL_DIR := $(DL_DIR)/picotool +PICOTOOL_BUILD_DIR := $(PICOTOOL_DL_DIR)/build +PICOTOOL_DIR := $(TOOLS_DIR)/picotool +PICO_SDK_PATH ?= $(ROOT_DIR)/lib/main/pico-sdk +PICOTOOL ?= $(PICOTOOL_DIR)/picotool + +ifneq ($(filter picotool_install uf2,$(MAKECMDGOALS)),) + ifeq ($(wildcard $(PICO_SDK_PATH)/CMakeLists.txt),) + $(error "PICO_SDK_PATH ($(PICO_SDK_PATH)) does not point to a valid Pico SDK. Please 'make pico_sdk' to hydrate the Pico SDK.") + endif +endif + +ifneq ($(filter uf2,$(MAKECMDGOALS)),) + ifeq (,$(wildcard $(PICOTOOL))) + ifeq (,$(shell which picotool 2>/dev/null)) + $(error "picotool not in the PATH or configured. Run 'make picotool_install' to install in the tools folder.") + else + PICOTOOL := picotool + endif + endif +endif + +.PHONY: pico_sdk +pico_sdk: + @echo "Updating pico-sdk" + $(V1) git submodule update --init --recursive -- lib/main/pico-sdk || { echo "Failed to update pico-sdk"; exit 1; } + @echo "pico-sdk updated" + +.PHONY: picotool_install +picotool_install: | $(DL_DIR) $(TOOLS_DIR) +picotool_install: picotool_clean + @echo "\n CLONE $(PICOTOOL_REPO)" + $(V1) git clone --depth 1 $(PICOTOOL_REPO) "$(PICOTOOL_DL_DIR)" || { echo "Failed to clone picotool repository"; exit 1; } + @echo "\n BUILD $(PICOTOOL_BUILD_DIR)" + $(V1) [ -d "$(PICOTOOL_DIR)" ] || mkdir -p $(PICOTOOL_DIR) + $(V1) [ -d "$(PICOTOOL_BUILD_DIR)" ] || mkdir -p $(PICOTOOL_BUILD_DIR) + $(V1) cmake -S $(PICOTOOL_DL_DIR) -B $(PICOTOOL_BUILD_DIR) -D PICO_SDK_PATH=$(PICO_SDK_PATH) || { echo "CMake configuration failed"; exit 1; } + $(V1) $(MAKE) -C $(PICOTOOL_BUILD_DIR) || { echo "picotool build failed"; exit 1; } + $(V1) cp $(PICOTOOL_BUILD_DIR)/picotool $(PICOTOOL_DIR)/picotool || { echo "Failed to install picotool binary"; exit 1; } + @echo "\n VERSION:" + $(V1) $(PICOTOOL_DIR)/picotool version + +.PHONY: picotool_clean +picotool_clean: + @echo " CLEAN $(PICOTOOL_DIR)" + $(V1) [ ! -d "$(PICOTOOL_DIR)" ] || $(RM) -rf $(PICOTOOL_DIR) + @echo " CLEAN $(PICOTOOL_DL_DIR)" + $(V1) [ ! -d "$(PICOTOOL_DL_DIR)" ] || $(RM) -rf $(PICOTOOL_DL_DIR) diff --git a/src/platform/SIMULATOR/mk/SITL.mk b/src/platform/SIMULATOR/mk/SITL.mk index 989306556f..757b0e4da8 100644 --- a/src/platform/SIMULATOR/mk/SITL.mk +++ b/src/platform/SIMULATOR/mk/SITL.mk @@ -1,3 +1,7 @@ +# SITL Makefile for the simulator platform + +# Default output is an exe file +DEFAULT_OUTPUT := exe INCLUDE_DIRS := \ $(INCLUDE_DIRS) \ From f4786d1569aa524bbefa7973f1f4edb19c174ca2 Mon Sep 17 00:00:00 2001 From: "Git bot (blckmn)" Date: Wed, 4 Jun 2025 06:25:03 +0000 Subject: [PATCH 228/244] Auto updated submodule references [04-06-2025] --- src/config | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/config b/src/config index eda6b30999..7970f07307 160000 --- a/src/config +++ b/src/config @@ -1 +1 @@ -Subproject commit eda6b309994923772eeab82fce3d6d8c3c0812a2 +Subproject commit 7970f0730766941d2202cf0174943bef7f85d3ce From 8853356e716505e27525f39f29fdaa6c28b37f46 Mon Sep 17 00:00:00 2001 From: mjs1441 Date: Wed, 4 Jun 2025 15:39:45 +0100 Subject: [PATCH 229/244] Allow for builds with certain features disabled. (#14420) * Allow for builds with certain features disabled. Fix build for when the following are disabled: USE_DMA USE_DSHOT_TELEMETRY USE_SERIAL_PASSTHROUGH * Tweak #ifdef / UNUSED as per code review. --- src/main/drivers/accgyro/accgyro_spi_bmi160.c | 2 ++ src/main/drivers/accgyro/accgyro_spi_bmi270.c | 2 ++ src/main/drivers/dshot.h | 7 ++----- src/main/drivers/dshot_command.c | 2 ++ src/main/msp/msp.c | 6 ++++++ 5 files changed, 14 insertions(+), 5 deletions(-) diff --git a/src/main/drivers/accgyro/accgyro_spi_bmi160.c b/src/main/drivers/accgyro/accgyro_spi_bmi160.c index 31260a0f96..fbf4aacb81 100644 --- a/src/main/drivers/accgyro/accgyro_spi_bmi160.c +++ b/src/main/drivers/accgyro/accgyro_spi_bmi160.c @@ -267,6 +267,7 @@ extiCallbackRec_t bmi160IntCallbackRec; // Called in ISR context // Gyro read has just completed +#ifdef USE_DMA static busStatus_e bmi160Intcallback(uint32_t arg) { gyroDev_t *gyro = (gyroDev_t *)arg; @@ -280,6 +281,7 @@ static busStatus_e bmi160Intcallback(uint32_t arg) return BUS_READY; } +#endif static void bmi160ExtiHandler(extiCallbackRec_t *cb) { diff --git a/src/main/drivers/accgyro/accgyro_spi_bmi270.c b/src/main/drivers/accgyro/accgyro_spi_bmi270.c index f13f39c75f..a64cfa64b4 100644 --- a/src/main/drivers/accgyro/accgyro_spi_bmi270.c +++ b/src/main/drivers/accgyro/accgyro_spi_bmi270.c @@ -278,6 +278,7 @@ extiCallbackRec_t bmi270IntCallbackRec; */ // Called in ISR context // Gyro read has just completed +#ifdef USE_DMA static busStatus_e bmi270Intcallback(uint32_t arg) { gyroDev_t *gyro = (gyroDev_t *)arg; @@ -291,6 +292,7 @@ static busStatus_e bmi270Intcallback(uint32_t arg) return BUS_READY; } +#endif static void bmi270ExtiHandler(extiCallbackRec_t *cb) { diff --git a/src/main/drivers/dshot.h b/src/main/drivers/dshot.h index 19105b0659..609fc22892 100644 --- a/src/main/drivers/dshot.h +++ b/src/main/drivers/dshot.h @@ -95,6 +95,8 @@ uint16_t prepareDshotPacket(dshotProtocolControl_t *pcb); extern bool useDshotTelemetry; extern uint8_t dshotMotorCount; +bool dshotPwmDevInit(motorDevice_t *device, const motorDevConfig_t *motorConfig); + #ifdef USE_DSHOT_TELEMETRY typedef struct dshotTelemetryMotorState_s { @@ -113,7 +115,6 @@ typedef struct dshotTelemetryState_s { dshotRawValueState_t rawValueState; } dshotTelemetryState_t; -#ifdef USE_DSHOT_TELEMETRY extern uint32_t readDoneCount; FAST_DATA_ZERO_INIT extern uint32_t inputStampUs; @@ -125,10 +126,6 @@ typedef struct dshotTelemetryCycleCounters_s { FAST_DATA_ZERO_INIT extern dshotTelemetryCycleCounters_t dshotDMAHandlerCycleCounters; -#endif - -bool dshotPwmDevInit(motorDevice_t *device, const motorDevConfig_t *motorConfig); - extern dshotTelemetryState_t dshotTelemetryState; #ifdef USE_DSHOT_TELEMETRY_STATS diff --git a/src/main/drivers/dshot_command.c b/src/main/drivers/dshot_command.c index a2fa5da17c..fc95dbc3aa 100644 --- a/src/main/drivers/dshot_command.c +++ b/src/main/drivers/dshot_command.c @@ -216,9 +216,11 @@ void dshotCommandWrite(uint8_t index, uint8_t motorCount, uint8_t command, dshot } if (commandType == DSHOT_CMD_TYPE_BLOCKING) { +#if defined(USE_DSHOT) && defined(USE_DSHOT_TELEMETRY) bool isBitbangActive = false; #ifdef USE_DSHOT_BITBANG isBitbangActive = isDshotBitbangActive(&motorConfig()->dev); +#endif #endif // Fake command in queue. Blocking commands are launched from cli, and no inline commands are running for (uint8_t i = 0; i < motorDeviceCount(); i++) { diff --git a/src/main/msp/msp.c b/src/main/msp/msp.c index de6d7d2492..9d4434cbe7 100644 --- a/src/main/msp/msp.c +++ b/src/main/msp/msp.c @@ -255,6 +255,7 @@ static void mspEscPassthroughFn(serialPort_t *serialPort) } #endif +#ifdef USE_SERIAL_PASSTHROUGH static serialPort_t *mspFindPassthroughSerialPort(void) { serialPortUsage_t *portUsage = NULL; @@ -284,6 +285,7 @@ static void mspSerialPassthroughFn(serialPort_t *serialPort) serialPassthrough(passthroughPort, serialPort, NULL, NULL); } } +#endif static void mspFcSetPassthroughCommand(sbuf_t *dst, sbuf_t *src, mspPostProcessFnPtr *mspPostProcessFn) { @@ -297,6 +299,7 @@ static void mspFcSetPassthroughCommand(sbuf_t *dst, sbuf_t *src, mspPostProcessF } switch (mspPassthroughMode) { +#ifdef USE_SERIAL_PASSTHROUGH case MSP_PASSTHROUGH_SERIAL_ID: case MSP_PASSTHROUGH_SERIAL_FUNCTION_ID: if (mspFindPassthroughSerialPort()) { @@ -308,6 +311,9 @@ static void mspFcSetPassthroughCommand(sbuf_t *dst, sbuf_t *src, mspPostProcessF sbufWriteU8(dst, 0); } break; +#else + UNUSED(mspPostProcessFn); +#endif #ifdef USE_SERIAL_4WAY_BLHELI_INTERFACE case MSP_PASSTHROUGH_ESC_4WAY: // get channel number From 31887f84b158d21488aa705d591ad250c1ca41ec Mon Sep 17 00:00:00 2001 From: Jay Blackman Date: Thu, 5 Jun 2025 10:28:31 +1000 Subject: [PATCH 230/244] PICO: Preparing for I2C device using I2C0 (#14422) --- src/main/drivers/bus_i2c.h | 16 +++++++--------- src/main/drivers/bus_i2c_impl.h | 14 ++++++++------ src/main/platform.h | 2 +- .../platform/platform.h} | 3 +++ .../platform/platform.h} | 11 +++++++---- .../platform/platform.h} | 2 ++ .../platform/platform.h} | 18 ++++++++++++++++++ src/test/unit/platform.h | 2 ++ 8 files changed, 48 insertions(+), 20 deletions(-) rename src/platform/APM32/{platform_mcu.h => include/platform/platform.h} (98%) rename src/platform/AT32/{platform_mcu.h => include/platform/platform.h} (96%) rename src/platform/SIMULATOR/{platform_mcu.h => include/platform/platform.h} (97%) rename src/platform/STM32/{platform_mcu.h => include/platform/platform.h} (97%) diff --git a/src/main/drivers/bus_i2c.h b/src/main/drivers/bus_i2c.h index 74dcfadb3d..91751dda24 100644 --- a/src/main/drivers/bus_i2c.h +++ b/src/main/drivers/bus_i2c.h @@ -31,20 +31,18 @@ typedef enum I2CDevice { I2CINVALID = -1, - I2CDEV_1 = 0, + I2CDEV_FIRST = 0, +#if defined(USE_I2C_DEVICE_0) + I2CDEV_0 = I2CDEV_FIRST, + I2CDEV_1, +#else + I2CDEV_1 = I2CDEV_FIRST, +#endif I2CDEV_2, I2CDEV_3, I2CDEV_4, } I2CDevice; -#if defined(STM32F4) || defined(APM32F4) -#define I2CDEV_COUNT 3 -#elif defined(STM32F7) -#define I2CDEV_COUNT 4 -#else -#define I2CDEV_COUNT 4 -#endif - // Macros to convert between CLI bus number and I2CDevice. #define I2C_CFG_TO_DEV(x) ((x) - 1) #define I2C_DEV_TO_CFG(x) ((x) + 1) diff --git a/src/main/drivers/bus_i2c_impl.h b/src/main/drivers/bus_i2c_impl.h index 0dd1fb2c99..34f932e248 100644 --- a/src/main/drivers/bus_i2c_impl.h +++ b/src/main/drivers/bus_i2c_impl.h @@ -32,12 +32,12 @@ typedef struct i2cPinDef_s { ioTag_t ioTag; -#if defined(STM32F4) || defined(STM32H7) || defined(STM32G4) || defined(AT32F4) || defined(APM32F4) +#if I2C_TRAIT_AF_PIN uint8_t af; #endif } i2cPinDef_t; -#if defined(STM32F4) || defined(STM32H7) || defined(STM32G4) || defined(AT32F4) || defined(APM32F4) +#if I2C_TRAIT_AF_PIN #define I2CPINDEF(pin, af) { DEFIO_TAG_E(pin), af } #else #define I2CPINDEF(pin) { DEFIO_TAG_E(pin) } @@ -48,14 +48,16 @@ typedef struct i2cHardware_s { I2C_TypeDef *reg; i2cPinDef_t sclPins[I2C_PIN_SEL_MAX]; i2cPinDef_t sdaPins[I2C_PIN_SEL_MAX]; +#if PLATFORM_TRAIT_RCC rccPeriphTag_t rcc; +#endif uint8_t ev_irq; uint8_t er_irq; } i2cHardware_t; extern const i2cHardware_t i2cHardware[]; -#if defined(STM32F4) +#if I2C_TRAIT_STATE typedef struct i2cState_s { volatile bool error; volatile bool busy; @@ -74,7 +76,7 @@ typedef struct i2cDevice_s { I2C_TypeDef *reg; IO_t scl; IO_t sda; -#if defined(STM32F4) || defined(STM32H7) || defined(STM32G4) || defined(AT32F4) || defined(APM32F4) +#if I2C_TRAIT_AF_PIN uint8_t sclAF; uint8_t sdaAF; #endif @@ -82,10 +84,10 @@ typedef struct i2cDevice_s { uint16_t clockSpeed; // MCU/Driver dependent member follows -#if defined(STM32F4) +#if I2C_TRAIT_STATE i2cState_t state; #endif -#if defined(USE_HAL_DRIVER) || defined(AT32F4) +#if I2C_TRAIT_HANDLE I2C_HandleTypeDef handle; #endif } i2cDevice_t; diff --git a/src/main/platform.h b/src/main/platform.h index 4f0a0f9ed1..e7c3583fdc 100644 --- a/src/main/platform.h +++ b/src/main/platform.h @@ -33,7 +33,7 @@ #include "target/common_pre.h" // MCU specific platform from platform/X -#include "platform_mcu.h" +#include "platform/platform.h" #include "target.h" #include "target/common_post.h" diff --git a/src/platform/APM32/platform_mcu.h b/src/platform/APM32/include/platform/platform.h similarity index 98% rename from src/platform/APM32/platform_mcu.h rename to src/platform/APM32/include/platform/platform.h index 10299b6d5c..a2798016e9 100644 --- a/src/platform/APM32/platform_mcu.h +++ b/src/platform/APM32/include/platform/platform.h @@ -193,6 +193,9 @@ #define PLATFORM_TRAIT_RCC 1 #define UART_TRAIT_AF_PORT 1 #define SERIAL_TRAIT_PIN_CONFIG 1 +#define I2C_TRAIT_AF_PIN 1 +#define I2CDEV_COUNT 3 +#define I2C_TRAIT_HANDLE 1 #define UARTHARDWARE_MAX_PINS 4 diff --git a/src/platform/AT32/platform_mcu.h b/src/platform/AT32/include/platform/platform.h similarity index 96% rename from src/platform/AT32/platform_mcu.h rename to src/platform/AT32/include/platform/platform.h index 2c55895061..9da68a042c 100644 --- a/src/platform/AT32/platform_mcu.h +++ b/src/platform/AT32/include/platform/platform.h @@ -144,12 +144,15 @@ typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; #define UART_TX_BUFFER_ATTRIBUTE // NONE #define UART_RX_BUFFER_ATTRIBUTE // NONE -#define PLATFORM_TRAIT_RCC 1 -#define UART_TRAIT_AF_PIN 1 -#define UART_TRAIT_PINSWAP 1 +#define PLATFORM_TRAIT_RCC 1 +#define UART_TRAIT_AF_PIN 1 +#define UART_TRAIT_PINSWAP 1 #define SERIAL_TRAIT_PIN_CONFIG 1 +#define I2C_TRAIT_AF_PIN 1 +#define I2CDEV_COUNT 4 +#define I2C_TRAIT_HANDLE 1 -#define UARTHARDWARE_MAX_PINS 5 +#define UARTHARDWARE_MAX_PINS 5 #define UART_REG_RXD(base) ((base)->dt) #define UART_REG_TXD(base) ((base)->dt) diff --git a/src/platform/SIMULATOR/platform_mcu.h b/src/platform/SIMULATOR/include/platform/platform.h similarity index 97% rename from src/platform/SIMULATOR/platform_mcu.h rename to src/platform/SIMULATOR/include/platform/platform.h index be11284f04..7fdf22c0f5 100644 --- a/src/platform/SIMULATOR/platform_mcu.h +++ b/src/platform/SIMULATOR/include/platform/platform.h @@ -33,3 +33,5 @@ // no serial pins are defined for the simulator #define SERIAL_TRAIT_PIN_CONFIG 0 + +#define I2CDEV_COUNT 0 diff --git a/src/platform/STM32/platform_mcu.h b/src/platform/STM32/include/platform/platform.h similarity index 97% rename from src/platform/STM32/platform_mcu.h rename to src/platform/STM32/include/platform/platform.h index f8c2e75d80..52f5ef8e56 100644 --- a/src/platform/STM32/platform_mcu.h +++ b/src/platform/STM32/include/platform/platform.h @@ -419,3 +419,21 @@ extern uint8_t _dmaram_end__; #define SERIAL_TRAIT_PIN_CONFIG 1 #define USB_DP_PIN PA12 + +#if defined(STM32F4) +#define I2C_TRAIT_STATE 1 +#endif + +#if defined(STM32F4) || defined(STM32H7) || defined(STM32G4) +#define I2C_TRAIT_AF_PIN 1 +#endif + +#if defined(USE_HAL_DRIVER) +#define I2C_TRAIT_HANDLE 1 +#endif + +#if defined(STM32F4) +#define I2CDEV_COUNT 3 +#else +#define I2CDEV_COUNT 4 +#endif diff --git a/src/test/unit/platform.h b/src/test/unit/platform.h index dd03dce802..8f59e69f76 100644 --- a/src/test/unit/platform.h +++ b/src/test/unit/platform.h @@ -124,6 +124,8 @@ typedef struct } ADC_TypeDef; #define SPIDEV_COUNT 0 +#define I2CDEV_COUNT 0 + #define WS2811_DMA_TC_FLAG (void *)1 #define WS2811_DMA_HANDLER_IDENTIFER 0 #define NVIC_PriorityGroup_2 0x500 From 0f294102428577646e90add5223d60c805eb6c7d Mon Sep 17 00:00:00 2001 From: "Git bot (blckmn)" Date: Thu, 5 Jun 2025 06:25:03 +0000 Subject: [PATCH 231/244] Auto updated submodule references [05-06-2025] --- src/config | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/config b/src/config index 7970f07307..737c3460fa 160000 --- a/src/config +++ b/src/config @@ -1 +1 @@ -Subproject commit 7970f0730766941d2202cf0174943bef7f85d3ce +Subproject commit 737c3460fa621696af079367c86ca2be28194631 From 4853ec7b8ab85f895b1ed63443ed14cacfc51f26 Mon Sep 17 00:00:00 2001 From: Jay Blackman Date: Fri, 6 Jun 2025 18:16:40 +1000 Subject: [PATCH 232/244] Adjusting SPI traits inline with recent i2c updates (#14428) --- src/main/drivers/bus_spi_impl.h | 14 +++++--- .../APM32/include/platform/platform.h | 4 +-- src/platform/AT32/include/platform/platform.h | 4 +-- .../STM32/include/platform/platform.h | 26 ++++++++------- src/platform/common/stm32/bus_spi_pinconfig.c | 32 ++++++++----------- 5 files changed, 41 insertions(+), 39 deletions(-) diff --git a/src/main/drivers/bus_spi_impl.h b/src/main/drivers/bus_spi_impl.h index cccca9a73d..556303da52 100644 --- a/src/main/drivers/bus_spi_impl.h +++ b/src/main/drivers/bus_spi_impl.h @@ -26,7 +26,7 @@ typedef struct spiPinDef_s { ioTag_t pin; -#if defined(STM32F7) || defined(STM32H7) || defined(STM32G4) || defined(AT32F4) || defined(APM32F4) +#if SPI_TRAIT_AF_PIN //TODO: move to GPIO uint8_t af; #endif } spiPinDef_t; @@ -37,33 +37,37 @@ typedef struct spiHardware_s { spiPinDef_t sckPins[MAX_SPI_PIN_SEL]; spiPinDef_t misoPins[MAX_SPI_PIN_SEL]; spiPinDef_t mosiPins[MAX_SPI_PIN_SEL]; -#ifndef STM32F7 +#if SPI_TRAIT_AF_PORT uint8_t af; #endif +#if PLATFORM_TRAIT_RCC rccPeriphTag_t rcc; +#endif #ifdef USE_DMA uint8_t dmaIrqHandler; #endif } spiHardware_t; -extern const spiHardware_t spiHardware[]; +extern const spiHardware_t spiHardware[SPIDEV_COUNT]; typedef struct SPIDevice_s { SPI_TypeDef *dev; ioTag_t sck; ioTag_t miso; ioTag_t mosi; -#if defined(STM32F7) || defined(STM32H7) || defined(STM32G4) || defined(AT32F4) || defined(APM32F4) +#if SPI_TRAIT_AF_PIN uint8_t sckAF; uint8_t misoAF; uint8_t mosiAF; #else uint8_t af; #endif -#if defined(HAL_SPI_MODULE_ENABLED) +#if SPI_TRAIT_HANDLE SPI_HandleTypeDef hspi; #endif +#if PLATFORM_TRAIT_RCC rccPeriphTag_t rcc; +#endif volatile uint16_t errorCount; bool leadingEdge; #ifdef USE_DMA diff --git a/src/platform/APM32/include/platform/platform.h b/src/platform/APM32/include/platform/platform.h index a2798016e9..368440773c 100644 --- a/src/platform/APM32/include/platform/platform.h +++ b/src/platform/APM32/include/platform/platform.h @@ -104,8 +104,6 @@ #define U_ID_1 (*(uint32_t*)0x1fff7a14) #define U_ID_2 (*(uint32_t*)0x1fff7a18) -#define USE_PIN_AF - #ifndef APM32F4 #define APM32F4 #endif @@ -197,6 +195,8 @@ #define I2CDEV_COUNT 3 #define I2C_TRAIT_HANDLE 1 +#define SPI_TRAIT_AF_PIN 1 + #define UARTHARDWARE_MAX_PINS 4 #define UART_REG_RXD(base) ((base)->DATA) diff --git a/src/platform/AT32/include/platform/platform.h b/src/platform/AT32/include/platform/platform.h index 9da68a042c..7e0a352450 100644 --- a/src/platform/AT32/include/platform/platform.h +++ b/src/platform/AT32/include/platform/platform.h @@ -57,8 +57,6 @@ typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; #define U_ID_1 (*(uint32_t*)0x1ffff7ec) #define U_ID_2 (*(uint32_t*)0x1ffff7f0) -#define USE_PIN_AF - #ifndef AT32F4 #define AT32F4 #endif @@ -151,7 +149,7 @@ typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; #define I2C_TRAIT_AF_PIN 1 #define I2CDEV_COUNT 4 #define I2C_TRAIT_HANDLE 1 - +#define SPI_TRAIT_AF_PIN 1 #define UARTHARDWARE_MAX_PINS 5 #define UART_REG_RXD(base) ((base)->dt) diff --git a/src/platform/STM32/include/platform/platform.h b/src/platform/STM32/include/platform/platform.h index 52f5ef8e56..53ea0cf11b 100644 --- a/src/platform/STM32/include/platform/platform.h +++ b/src/platform/STM32/include/platform/platform.h @@ -39,7 +39,8 @@ #define U_ID_1 (*(uint32_t*)(UID_BASE + 4)) #define U_ID_2 (*(uint32_t*)(UID_BASE + 8)) -#define USE_PIN_AF +#define SPI_TRAIT_AF_PIN 1 +#define I2C_TRAIT_AF_PIN 1 #ifndef STM32G4 #define STM32G4 @@ -64,7 +65,8 @@ #define U_ID_1 (*(uint32_t*)(UID_BASE + 4)) #define U_ID_2 (*(uint32_t*)(UID_BASE + 8)) -#define USE_PIN_AF +#define SPI_TRAIT_AF_PIN 1 +#define I2C_TRAIT_AF_PIN 1 #ifndef STM32H7 #define STM32H7 @@ -89,7 +91,7 @@ #define U_ID_1 (*(uint32_t*)(UID_BASE + 4)) #define U_ID_2 (*(uint32_t*)(UID_BASE + 8)) -#define USE_PIN_AF +#define SPI_TRAIT_AF_PIN 1 #ifndef STM32F7 #define STM32F7 @@ -104,6 +106,11 @@ #define U_ID_1 (*(uint32_t*)0x1fff7a14) #define U_ID_2 (*(uint32_t*)0x1fff7a18) +#define SPI_TRAIT_AF_PORT 1 + +#define I2C_TRAIT_STATE 1 +#define I2C_TRAIT_AF_PIN 1 + #ifndef STM32F4 #define STM32F4 #endif @@ -420,16 +427,13 @@ extern uint8_t _dmaram_end__; #define SERIAL_TRAIT_PIN_CONFIG 1 #define USB_DP_PIN PA12 -#if defined(STM32F4) -#define I2C_TRAIT_STATE 1 -#endif - -#if defined(STM32F4) || defined(STM32H7) || defined(STM32G4) -#define I2C_TRAIT_AF_PIN 1 -#endif - #if defined(USE_HAL_DRIVER) #define I2C_TRAIT_HANDLE 1 + +#if defined(HAL_SPI_MODULE_ENABLED) +#define SPI_TRAIT_HANDLE 1 +#endif + #endif #if defined(STM32F4) diff --git a/src/platform/common/stm32/bus_spi_pinconfig.c b/src/platform/common/stm32/bus_spi_pinconfig.c index 59c68b214a..02cc24ac9a 100644 --- a/src/platform/common/stm32/bus_spi_pinconfig.c +++ b/src/platform/common/stm32/bus_spi_pinconfig.c @@ -348,21 +348,20 @@ const spiHardware_t spiHardware[] = { .device = SPIDEV_1, .reg = SPI1, .sckPins = { - { DEFIO_TAG_E(PA5) ,GPIO_MUX_5}, - { DEFIO_TAG_E(PB3) ,GPIO_MUX_5}, - { DEFIO_TAG_E(PE13),GPIO_MUX_4}, + { DEFIO_TAG_E(PA5), GPIO_MUX_5}, + { DEFIO_TAG_E(PB3), GPIO_MUX_5}, + { DEFIO_TAG_E(PE13), GPIO_MUX_4}, }, .misoPins = { - { DEFIO_TAG_E(PA6) ,GPIO_MUX_5}, - { DEFIO_TAG_E(PB4) ,GPIO_MUX_5}, - { DEFIO_TAG_E(PE14),GPIO_MUX_4} + { DEFIO_TAG_E(PA6), GPIO_MUX_5}, + { DEFIO_TAG_E(PB4), GPIO_MUX_5}, + { DEFIO_TAG_E(PE14), GPIO_MUX_4} }, .mosiPins = { - { DEFIO_TAG_E(PA7) ,GPIO_MUX_5}, - { DEFIO_TAG_E(PB5) ,GPIO_MUX_5}, - { DEFIO_TAG_E(PE15),GPIO_MUX_4}, + { DEFIO_TAG_E(PA7), GPIO_MUX_5}, + { DEFIO_TAG_E(PB5), GPIO_MUX_5}, + { DEFIO_TAG_E(PE15), GPIO_MUX_4}, }, - .af= 0x00, .rcc = RCC_APB2(SPI1), }, { @@ -370,7 +369,7 @@ const spiHardware_t spiHardware[] = { .reg = SPI2, .sckPins = { { DEFIO_TAG_E(PB10), GPIO_MUX_5}, - { DEFIO_TAG_E(PB13) ,GPIO_MUX_5}, + { DEFIO_TAG_E(PB13), GPIO_MUX_5}, { DEFIO_TAG_E(PC7), GPIO_MUX_5}, { DEFIO_TAG_E(PD1), GPIO_MUX_6}, @@ -387,7 +386,6 @@ const spiHardware_t spiHardware[] = { { DEFIO_TAG_E(PC3), GPIO_MUX_5}, { DEFIO_TAG_E(PD4), GPIO_MUX_6}, }, - .af= 0x00, .rcc = RCC_APB1(SPI2), }, { @@ -409,7 +407,6 @@ const spiHardware_t spiHardware[] = { { DEFIO_TAG_E(PC12), GPIO_MUX_6}, { DEFIO_TAG_E(PD0), GPIO_MUX_6}, }, - .af= 0x00, .rcc = RCC_APB1(SPI3), }, { @@ -428,7 +425,6 @@ const spiHardware_t spiHardware[] = { { DEFIO_TAG_E(PA1), GPIO_MUX_5}, { DEFIO_TAG_E(PB9), GPIO_MUX_6}, }, - .af= 0x00, .rcc = RCC_APB2(SPI4), }, #endif @@ -505,19 +501,19 @@ void spiPinConfigure(const spiPinConfig_t *pConfig) for (int pindex = 0 ; pindex < MAX_SPI_PIN_SEL ; pindex++) { if (pConfig[device].ioTagSck == hw->sckPins[pindex].pin) { pDev->sck = hw->sckPins[pindex].pin; -#if defined(USE_PIN_AF) +#if SPI_TRAIT_AF_PIN pDev->sckAF = hw->sckPins[pindex].af; #endif } if (pConfig[device].ioTagMiso == hw->misoPins[pindex].pin) { pDev->miso = hw->misoPins[pindex].pin; -#if defined(USE_PIN_AF) +#if SPI_TRAIT_AF_PIN pDev->misoAF = hw->misoPins[pindex].af; #endif } if (pConfig[device].ioTagMosi == hw->mosiPins[pindex].pin) { pDev->mosi = hw->mosiPins[pindex].pin; -#if defined(USE_PIN_AF) +#if SPI_TRAIT_AF_PIN pDev->mosiAF = hw->mosiPins[pindex].af; #endif } @@ -525,7 +521,7 @@ void spiPinConfigure(const spiPinConfig_t *pConfig) if (pDev->sck && pDev->miso && pDev->mosi) { pDev->dev = hw->reg; -#if !defined(USE_PIN_AF) +#if SPI_TRAIT_AF_PORT pDev->af = hw->af; #endif pDev->rcc = hw->rcc; From 0bb1254ee830f1953b4bcbb9e7eee183891ad117 Mon Sep 17 00:00:00 2001 From: Jay Blackman Date: Sat, 7 Jun 2025 09:41:37 +1000 Subject: [PATCH 233/244] Move RCC from drivers to platform (#14430) * Move RCC from drivers to platform * Extra line removed * Suggestion from code rabbit * Remove else and require explicit --- src/main/drivers/adc_impl.h | 8 ++++++-- src/main/drivers/bus_i2c.h | 1 - src/main/drivers/bus_i2c_impl.h | 5 ++++- src/main/drivers/bus_quadspi.c | 7 ++++++- src/main/drivers/bus_quadspi.h | 1 - src/main/drivers/bus_quadspi_impl.h | 19 +++++++++++++------ src/main/drivers/bus_spi_impl.h | 11 ++++++++++- src/main/drivers/io.c | 1 - .../drivers/rangefinder/rangefinder_hcsr04.c | 1 - src/main/drivers/rx/rx_spi.c | 1 - src/main/drivers/serial_uart.c | 1 - src/main/drivers/serial_uart_impl.h | 4 ++++ src/main/drivers/serial_uart_pinconfig.c | 1 - src/main/drivers/timer.h | 10 +++++++++- src/main/pg/bus_i2c.h | 1 - src/platform/APM32/adc_apm32f4xx.c | 2 +- src/platform/APM32/bus_i2c_apm32.c | 2 +- src/platform/APM32/bus_i2c_apm32_init.c | 2 +- src/platform/APM32/bus_spi_apm32.c | 2 +- src/platform/APM32/dma_apm32f4xx.c | 2 +- src/platform/APM32/io_apm32.c | 2 +- src/platform/APM32/light_ws2811strip_apm32.c | 2 +- src/platform/APM32/pwm_output_dshot_apm32.c | 2 +- src/platform/APM32/rcm_apm32.c | 2 +- src/platform/APM32/serial_uart_apm32.c | 2 +- src/platform/APM32/serial_uart_apm32f4xx.c | 2 +- src/platform/APM32/timer_apm32.c | 2 +- src/platform/APM32/timer_apm32f4xx.c | 2 +- src/platform/APM32/transponder_ir_io_apm32.c | 2 +- src/platform/AT32/adc_at32f43x.c | 2 +- src/platform/AT32/bus_i2c_atbsp.c | 2 +- src/platform/AT32/bus_i2c_atbsp_init.c | 2 +- src/platform/AT32/bus_spi_at32bsp.c | 2 +- src/platform/AT32/camera_control_at32.c | 2 +- src/platform/AT32/dma_at32f43x.c | 2 +- src/platform/AT32/io_at32.c | 2 +- .../AT32/light_ws2811strip_at32f43x.c | 2 +- src/platform/AT32/pwm_output_dshot.c | 2 +- src/platform/AT32/rcc_at32.c | 2 +- src/platform/AT32/serial_uart_at32bsp.c | 2 +- src/platform/AT32/serial_uart_at32f43x.c | 2 +- src/platform/AT32/timer_at32bsp.c | 2 +- src/platform/AT32/timer_at32f43x.c | 2 +- .../SIMULATOR/include/platform/platform.h | 2 ++ src/platform/STM32/adc_stm32f4xx.c | 2 +- src/platform/STM32/adc_stm32f7xx.c | 2 +- src/platform/STM32/adc_stm32g4xx.c | 2 +- src/platform/STM32/adc_stm32h7xx.c | 2 +- src/platform/STM32/bus_i2c_hal.c | 2 +- src/platform/STM32/bus_i2c_hal_init.c | 2 +- src/platform/STM32/bus_i2c_stm32f4xx.c | 2 +- src/platform/STM32/bus_quadspi_hal.c | 2 +- src/platform/STM32/bus_spi_ll.c | 2 +- src/platform/STM32/bus_spi_stdperiph.c | 2 +- src/platform/STM32/dma_stm32f7xx.c | 2 +- src/platform/STM32/dma_stm32g4xx.c | 2 +- src/platform/STM32/dma_stm32h7xx.c | 2 +- .../STM32/include/platform/platform.h | 7 +++++++ src/platform/STM32/io_stm32.c | 2 +- src/platform/STM32/light_ws2811strip_hal.c | 2 +- .../STM32/light_ws2811strip_stdperiph.c | 2 +- src/platform/STM32/pwm_output_dshot.c | 2 +- src/platform/STM32/pwm_output_dshot_hal.c | 2 +- src/platform/STM32/rcc_stm32.c | 2 +- src/platform/STM32/sdio_f4xx.c | 2 +- src/platform/STM32/sdio_f7xx.c | 2 +- src/platform/STM32/serial_uart_hal.c | 2 +- src/platform/STM32/serial_uart_stdperiph.c | 2 +- src/platform/STM32/serial_uart_stm32f4xx.c | 2 +- src/platform/STM32/serial_uart_stm32f7xx.c | 2 +- src/platform/STM32/serial_uart_stm32g4xx.c | 2 +- src/platform/STM32/serial_uart_stm32h7xx.c | 2 +- src/platform/STM32/timer_hal.c | 2 +- src/platform/STM32/timer_stdperiph.c | 3 ++- src/platform/STM32/timer_stm32f4xx.c | 2 +- src/platform/STM32/timer_stm32f7xx.c | 2 +- src/platform/STM32/timer_stm32g4xx.c | 2 +- src/platform/STM32/timer_stm32h5xx.c | 2 +- src/platform/STM32/timer_stm32h7xx.c | 2 +- src/platform/STM32/transponder_ir_io_hal.c | 2 +- .../STM32/transponder_ir_io_stdperiph.c | 2 +- src/platform/common/stm32/bus_spi_pinconfig.c | 2 +- .../common/stm32/platform}/rcc.h | 2 +- .../common/stm32/platform}/rcc_types.h | 0 .../common/stm32/pwm_output_dshot_shared.c | 2 +- src/platform/common/stm32/serial_uart_hw.c | 2 +- 86 files changed, 130 insertions(+), 88 deletions(-) rename src/{main/drivers => platform/common/stm32/platform}/rcc.h (99%) rename src/{main/drivers => platform/common/stm32/platform}/rcc_types.h (100%) diff --git a/src/main/drivers/adc_impl.h b/src/main/drivers/adc_impl.h index 66baa5da9c..add1083bf2 100644 --- a/src/main/drivers/adc_impl.h +++ b/src/main/drivers/adc_impl.h @@ -20,10 +20,14 @@ #pragma once +#include "platform.h" #include "drivers/adc.h" #include "drivers/dma.h" #include "drivers/io_types.h" -#include "drivers/rcc_types.h" + +#if PLATFORM_TRAIT_RCC +#include "platform/rcc_types.h" +#endif #if defined(STM32F4) || defined(STM32F7) #define ADC_TAG_MAP_COUNT 16 @@ -73,8 +77,8 @@ typedef struct adcTagMap_s { #define ADC_DEVICES_345 ((1 << ADCDEV_3)|(1 << ADCDEV_4)|(1 << ADCDEV_5)) typedef struct adcDevice_s { -#if !defined(SIMULATOR_BUILD) ADC_TypeDef* ADCx; +#if PLATFORM_TRAIT_RCC rccPeriphTag_t rccADC; #endif #if !defined(USE_DMA_SPEC) diff --git a/src/main/drivers/bus_i2c.h b/src/main/drivers/bus_i2c.h index 91751dda24..0b34ea2e94 100644 --- a/src/main/drivers/bus_i2c.h +++ b/src/main/drivers/bus_i2c.h @@ -23,7 +23,6 @@ #include "platform.h" #include "drivers/io_types.h" -#include "drivers/rcc_types.h" #ifndef I2C_DEVICE #define I2C_DEVICE I2CINVALID diff --git a/src/main/drivers/bus_i2c_impl.h b/src/main/drivers/bus_i2c_impl.h index 34f932e248..2ce413685b 100644 --- a/src/main/drivers/bus_i2c_impl.h +++ b/src/main/drivers/bus_i2c_impl.h @@ -23,7 +23,10 @@ #include "platform.h" #include "drivers/io_types.h" -#include "drivers/rcc_types.h" + +#if PLATFORM_TRAIT_RCC +#include "platform/rcc_types.h" +#endif #define I2C_TIMEOUT_US 10000 #define I2C_TIMEOUT_SYS_TICKS (I2C_TIMEOUT_US / 1000) diff --git a/src/main/drivers/bus_quadspi.c b/src/main/drivers/bus_quadspi.c index 4944e12d0d..7ce4069cd4 100644 --- a/src/main/drivers/bus_quadspi.c +++ b/src/main/drivers/bus_quadspi.c @@ -32,7 +32,10 @@ #include "drivers/bus_quadspi_impl.h" #include "drivers/exti.h" #include "drivers/io.h" -#include "drivers/rcc.h" + +#if PLATFORM_TRAIT_RCC +#include "platform/rcc.h" +#endif #include "pg/bus_quadspi.h" @@ -264,7 +267,9 @@ void quadSpiPinConfigure(const quadSpiConfig_t *pConfig) if (haveResources) { pDev->dev = hw->reg; +#if PLATFORM_TRAIT_RCC pDev->rcc = hw->rcc; +#endif } } } diff --git a/src/main/drivers/bus_quadspi.h b/src/main/drivers/bus_quadspi.h index 6defb3514f..7fdb75cceb 100644 --- a/src/main/drivers/bus_quadspi.h +++ b/src/main/drivers/bus_quadspi.h @@ -23,7 +23,6 @@ #pragma once #include "drivers/io_types.h" -#include "drivers/rcc_types.h" #include "pg/pg.h" #include "pg/pg_ids.h" diff --git a/src/main/drivers/bus_quadspi_impl.h b/src/main/drivers/bus_quadspi_impl.h index eda709b918..b226f2723a 100644 --- a/src/main/drivers/bus_quadspi_impl.h +++ b/src/main/drivers/bus_quadspi_impl.h @@ -22,17 +22,19 @@ #pragma once +#include "platform.h" + +#if PLATFORM_TRAIT_RCC +#include "platform/rcc_types.h" +#endif + typedef struct quadSpiPinDef_s { ioTag_t pin; -#if defined(STM32H7) +#if QUADSPI_TRAIT_AF_PIN uint8_t af; #endif } quadSpiPinDef_t; -#if defined(STM32H7) -#define MAX_QUADSPI_PIN_SEL 3 -#endif - typedef struct quadSpiHardware_s { QUADSPIDevice device; QUADSPI_TypeDef *reg; @@ -48,7 +50,9 @@ typedef struct quadSpiHardware_s { quadSpiPinDef_t bk2IO3Pins[MAX_QUADSPI_PIN_SEL]; quadSpiPinDef_t bk2CSPins[MAX_QUADSPI_PIN_SEL]; +#if PLATFORM_TRAIT_RCC rccPeriphTag_t rcc; +#endif } quadSpiHardware_t; extern const quadSpiHardware_t quadSpiHardware[]; @@ -78,9 +82,12 @@ typedef struct QUADSPIDevice_s { uint8_t bk2IO3AF; uint8_t bk2CSAF; #endif + +#if PLATFORM_TRAIT_RCC rccPeriphTag_t rcc; +#endif volatile uint16_t errorCount; -#if defined(USE_HAL_DRIVER) +#if QUADSPI_TRAIT_HANDLE QSPI_HandleTypeDef hquadSpi; #endif } quadSpiDevice_t; diff --git a/src/main/drivers/bus_spi_impl.h b/src/main/drivers/bus_spi_impl.h index 556303da52..4b5106c8c4 100644 --- a/src/main/drivers/bus_spi_impl.h +++ b/src/main/drivers/bus_spi_impl.h @@ -20,6 +20,12 @@ #pragma once +#include "platform.h" + +#if PLATFORM_TRAIT_RCC +#include "platform/rcc_types.h" +#endif + #define SPI_TIMEOUT_US 10000 #define BUS_SPI_FREE 0x0 @@ -40,9 +46,11 @@ typedef struct spiHardware_s { #if SPI_TRAIT_AF_PORT uint8_t af; #endif + #if PLATFORM_TRAIT_RCC rccPeriphTag_t rcc; #endif + #ifdef USE_DMA uint8_t dmaIrqHandler; #endif @@ -59,7 +67,8 @@ typedef struct SPIDevice_s { uint8_t sckAF; uint8_t misoAF; uint8_t mosiAF; -#else +#endif +#if SPI_TRAIT_AF_PORT uint8_t af; #endif #if SPI_TRAIT_HANDLE diff --git a/src/main/drivers/io.c b/src/main/drivers/io.c index 7c766d9430..25f905143a 100644 --- a/src/main/drivers/io.c +++ b/src/main/drivers/io.c @@ -22,7 +22,6 @@ #include "drivers/io.h" #include "drivers/io_impl.h" -#include "drivers/rcc.h" #include "common/utils.h" diff --git a/src/main/drivers/rangefinder/rangefinder_hcsr04.c b/src/main/drivers/rangefinder/rangefinder_hcsr04.c index 72d3e201b8..dc01608565 100644 --- a/src/main/drivers/rangefinder/rangefinder_hcsr04.c +++ b/src/main/drivers/rangefinder/rangefinder_hcsr04.c @@ -30,7 +30,6 @@ #include "drivers/exti.h" #include "drivers/io.h" #include "drivers/nvic.h" -#include "drivers/rcc.h" #include "drivers/time.h" #include "drivers/rangefinder/rangefinder.h" diff --git a/src/main/drivers/rx/rx_spi.c b/src/main/drivers/rx/rx_spi.c index 05c6e803ea..19e7d69a1e 100644 --- a/src/main/drivers/rx/rx_spi.c +++ b/src/main/drivers/rx/rx_spi.c @@ -35,7 +35,6 @@ #include "drivers/io.h" #include "drivers/io_impl.h" #include "drivers/nvic.h" -#include "drivers/rcc.h" #include "drivers/system.h" #include "drivers/time.h" diff --git a/src/main/drivers/serial_uart.c b/src/main/drivers/serial_uart.c index fb5c5291e3..172719885e 100644 --- a/src/main/drivers/serial_uart.c +++ b/src/main/drivers/serial_uart.c @@ -42,7 +42,6 @@ #include "drivers/dma.h" #include "drivers/dma_reqmap.h" -#include "drivers/rcc.h" #include "drivers/serial.h" #include "drivers/serial_impl.h" #include "drivers/serial_uart.h" diff --git a/src/main/drivers/serial_uart_impl.h b/src/main/drivers/serial_uart_impl.h index 9a6304129c..988a2858b2 100644 --- a/src/main/drivers/serial_uart_impl.h +++ b/src/main/drivers/serial_uart_impl.h @@ -33,6 +33,10 @@ #include "platform.h" +#if PLATFORM_TRAIT_RCC +#include "platform/rcc_types.h" +#endif + #ifndef UART_RX_BUFFER_SIZE #define UART_RX_BUFFER_SIZE 256 #endif diff --git a/src/main/drivers/serial_uart_pinconfig.c b/src/main/drivers/serial_uart_pinconfig.c index 8d9b348354..896f0dce95 100644 --- a/src/main/drivers/serial_uart_pinconfig.c +++ b/src/main/drivers/serial_uart_pinconfig.c @@ -36,7 +36,6 @@ #include "build/build_config.h" -#include "drivers/rcc.h" #include "drivers/serial.h" #include "drivers/serial_uart.h" #include "drivers/serial_uart_impl.h" diff --git a/src/main/drivers/timer.h b/src/main/drivers/timer.h index 40bae0689c..13bfec69c5 100644 --- a/src/main/drivers/timer.h +++ b/src/main/drivers/timer.h @@ -25,7 +25,11 @@ #include "drivers/dma.h" #include "drivers/io_types.h" -#include "drivers/rcc_types.h" + +#if PLATFORM_TRAIT_RCC +#include "platform/rcc_types.h" +#endif + #include "drivers/resource.h" #ifdef USE_TIMER @@ -69,7 +73,9 @@ typedef struct timerOvrHandlerRec_s { typedef struct timerDef_s { TIM_TypeDef *TIMx; +#if PLATFORM_TRAIT_RCC rccPeriphTag_t rcc; +#endif uint8_t inputIrq; } timerDef_t; @@ -180,7 +186,9 @@ uint32_t timerClock(const TIM_TypeDef *tim); void configTimeBase(TIM_TypeDef *tim, uint16_t period, uint32_t hz); // TODO - just for migration void timerReconfigureTimeBase(TIM_TypeDef *tim, uint16_t period, uint32_t hz); +#if PLATFORM_TRAIT_RCC rccPeriphTag_t timerRCC(const TIM_TypeDef *tim); +#endif uint8_t timerInputIrq(const TIM_TypeDef *tim); #if defined(USE_TIMER_MGMT) diff --git a/src/main/pg/bus_i2c.h b/src/main/pg/bus_i2c.h index f460c48aa8..a8827f760f 100644 --- a/src/main/pg/bus_i2c.h +++ b/src/main/pg/bus_i2c.h @@ -22,7 +22,6 @@ #include "drivers/bus_i2c.h" #include "drivers/io_types.h" -#include "drivers/rcc_types.h" #include "pg/pg.h" diff --git a/src/platform/APM32/adc_apm32f4xx.c b/src/platform/APM32/adc_apm32f4xx.c index 2b93c1eba6..f577804602 100644 --- a/src/platform/APM32/adc_apm32f4xx.c +++ b/src/platform/APM32/adc_apm32f4xx.c @@ -32,7 +32,7 @@ #include "drivers/dma_reqmap.h" #include "drivers/io.h" #include "drivers/io_impl.h" -#include "drivers/rcc.h" +#include "platform/rcc.h" #include "drivers/dma.h" #include "drivers/sensor.h" #include "drivers/adc.h" diff --git a/src/platform/APM32/bus_i2c_apm32.c b/src/platform/APM32/bus_i2c_apm32.c index 12eb1d803a..3b51cee474 100644 --- a/src/platform/APM32/bus_i2c_apm32.c +++ b/src/platform/APM32/bus_i2c_apm32.c @@ -31,7 +31,7 @@ #include "drivers/io_impl.h" #include "drivers/nvic.h" #include "drivers/time.h" -#include "drivers/rcc.h" +#include "platform/rcc.h" #include "drivers/bus_i2c.h" #include "drivers/bus_i2c_impl.h" diff --git a/src/platform/APM32/bus_i2c_apm32_init.c b/src/platform/APM32/bus_i2c_apm32_init.c index 12dd1227d8..45fe92bfaa 100644 --- a/src/platform/APM32/bus_i2c_apm32_init.c +++ b/src/platform/APM32/bus_i2c_apm32_init.c @@ -30,7 +30,7 @@ #include "drivers/io.h" #include "drivers/nvic.h" #include "drivers/time.h" -#include "drivers/rcc.h" +#include "platform/rcc.h" #include "drivers/bus_i2c.h" #include "drivers/bus_i2c_impl.h" diff --git a/src/platform/APM32/bus_spi_apm32.c b/src/platform/APM32/bus_spi_apm32.c index 6b15adf29d..2b9a484975 100644 --- a/src/platform/APM32/bus_spi_apm32.c +++ b/src/platform/APM32/bus_spi_apm32.c @@ -35,7 +35,7 @@ #include "drivers/bus_spi_impl.h" #include "drivers/dma.h" #include "drivers/io.h" -#include "drivers/rcc.h" +#include "platform/rcc.h" // Use DMA if possible if this many bytes are to be transferred #define SPI_DMA_THRESHOLD 8 diff --git a/src/platform/APM32/dma_apm32f4xx.c b/src/platform/APM32/dma_apm32f4xx.c index 3c571a75e5..403f592fa4 100644 --- a/src/platform/APM32/dma_apm32f4xx.c +++ b/src/platform/APM32/dma_apm32f4xx.c @@ -29,7 +29,7 @@ #include "drivers/nvic.h" #include "drivers/dma.h" -#include "drivers/rcc.h" +#include "platform/rcc.h" #include "drivers/resource.h" /* diff --git a/src/platform/APM32/io_apm32.c b/src/platform/APM32/io_apm32.c index d744117646..482a6b8fd8 100644 --- a/src/platform/APM32/io_apm32.c +++ b/src/platform/APM32/io_apm32.c @@ -23,7 +23,7 @@ #include "drivers/io.h" #include "drivers/io_impl.h" -#include "drivers/rcc.h" +#include "platform/rcc.h" #include "common/utils.h" diff --git a/src/platform/APM32/light_ws2811strip_apm32.c b/src/platform/APM32/light_ws2811strip_apm32.c index 2ef5cbcb30..c2cafd8ba7 100644 --- a/src/platform/APM32/light_ws2811strip_apm32.c +++ b/src/platform/APM32/light_ws2811strip_apm32.c @@ -32,7 +32,7 @@ #include "drivers/dma_reqmap.h" #include "drivers/io.h" #include "drivers/nvic.h" -#include "drivers/rcc.h" +#include "platform/rcc.h" #include "drivers/system.h" #include "drivers/timer.h" diff --git a/src/platform/APM32/pwm_output_dshot_apm32.c b/src/platform/APM32/pwm_output_dshot_apm32.c index 499897394f..203df9fefc 100644 --- a/src/platform/APM32/pwm_output_dshot_apm32.c +++ b/src/platform/APM32/pwm_output_dshot_apm32.c @@ -41,7 +41,7 @@ #include "drivers/motor.h" #include "drivers/pwm_output.h" #include "pwm_output_dshot_shared.h" -#include "drivers/rcc.h" +#include "platform/rcc.h" #include "drivers/time.h" #include "drivers/timer.h" #include "drivers/system.h" diff --git a/src/platform/APM32/rcm_apm32.c b/src/platform/APM32/rcm_apm32.c index 96ecd59ac5..160dbfd723 100644 --- a/src/platform/APM32/rcm_apm32.c +++ b/src/platform/APM32/rcm_apm32.c @@ -20,7 +20,7 @@ */ #include "platform.h" -#include "drivers/rcc.h" +#include "platform/rcc.h" void RCC_ClockCmd(rccPeriphTag_t periphTag, FunctionalState NewState) { diff --git a/src/platform/APM32/serial_uart_apm32.c b/src/platform/APM32/serial_uart_apm32.c index e676ca2f93..eb6da0f291 100644 --- a/src/platform/APM32/serial_uart_apm32.c +++ b/src/platform/APM32/serial_uart_apm32.c @@ -39,7 +39,7 @@ #include "common/utils.h" #include "drivers/inverter.h" #include "drivers/nvic.h" -#include "drivers/rcc.h" +#include "platform/rcc.h" #include "drivers/serial.h" #include "drivers/serial_uart.h" diff --git a/src/platform/APM32/serial_uart_apm32f4xx.c b/src/platform/APM32/serial_uart_apm32f4xx.c index 2c5151b62f..7978e6315e 100644 --- a/src/platform/APM32/serial_uart_apm32f4xx.c +++ b/src/platform/APM32/serial_uart_apm32f4xx.c @@ -36,7 +36,7 @@ #include "drivers/io.h" #include "drivers/dma.h" #include "drivers/nvic.h" -#include "drivers/rcc.h" +#include "platform/rcc.h" #include "drivers/serial.h" #include "drivers/serial_uart.h" diff --git a/src/platform/APM32/timer_apm32.c b/src/platform/APM32/timer_apm32.c index 12ef8f197b..5e52ec654c 100644 --- a/src/platform/APM32/timer_apm32.c +++ b/src/platform/APM32/timer_apm32.c @@ -37,7 +37,7 @@ #include "drivers/io.h" #include "drivers/dma.h" -#include "drivers/rcc.h" +#include "platform/rcc.h" #include "drivers/timer.h" #include "drivers/timer_impl.h" diff --git a/src/platform/APM32/timer_apm32f4xx.c b/src/platform/APM32/timer_apm32f4xx.c index 708e6f3e29..e67e450306 100644 --- a/src/platform/APM32/timer_apm32f4xx.c +++ b/src/platform/APM32/timer_apm32f4xx.c @@ -30,7 +30,7 @@ #include "timer_def.h" #include "apm32f4xx.h" -#include "drivers/rcc.h" +#include "platform/rcc.h" #include "drivers/timer.h" const timerDef_t timerDefinitions[HARDWARE_TIMER_DEFINITION_COUNT] = { diff --git a/src/platform/APM32/transponder_ir_io_apm32.c b/src/platform/APM32/transponder_ir_io_apm32.c index 799ccb8494..ff4d778736 100644 --- a/src/platform/APM32/transponder_ir_io_apm32.c +++ b/src/platform/APM32/transponder_ir_io_apm32.c @@ -31,7 +31,7 @@ #include "drivers/dma_reqmap.h" #include "drivers/io.h" #include "drivers/nvic.h" -#include "drivers/rcc.h" +#include "platform/rcc.h" #include "drivers/timer.h" #include "drivers/transponder_ir_arcitimer.h" #include "drivers/transponder_ir_erlt.h" diff --git a/src/platform/AT32/adc_at32f43x.c b/src/platform/AT32/adc_at32f43x.c index 31b6a45b55..13e13b3c5e 100644 --- a/src/platform/AT32/adc_at32f43x.c +++ b/src/platform/AT32/adc_at32f43x.c @@ -54,7 +54,7 @@ #include "drivers/dma_reqmap.h" #include "drivers/io.h" #include "drivers/io_impl.h" -#include "drivers/rcc.h" +#include "platform/rcc.h" #include "drivers/resource.h" #include "drivers/dma.h" diff --git a/src/platform/AT32/bus_i2c_atbsp.c b/src/platform/AT32/bus_i2c_atbsp.c index daa9f4bc9a..1ddef8d7a0 100644 --- a/src/platform/AT32/bus_i2c_atbsp.c +++ b/src/platform/AT32/bus_i2c_atbsp.c @@ -31,7 +31,7 @@ #include "drivers/io_impl.h" #include "drivers/nvic.h" #include "drivers/time.h" -#include "drivers/rcc.h" +#include "platform/rcc.h" #include "drivers/bus_i2c.h" #include "drivers/bus_i2c_impl.h" diff --git a/src/platform/AT32/bus_i2c_atbsp_init.c b/src/platform/AT32/bus_i2c_atbsp_init.c index 0d3d4c2542..0e3c6aa740 100644 --- a/src/platform/AT32/bus_i2c_atbsp_init.c +++ b/src/platform/AT32/bus_i2c_atbsp_init.c @@ -30,7 +30,7 @@ #include "drivers/io.h" #include "drivers/nvic.h" #include "drivers/time.h" -#include "drivers/rcc.h" +#include "platform/rcc.h" #include "drivers/bus_i2c.h" #include "drivers/bus_i2c_impl.h" diff --git a/src/platform/AT32/bus_spi_at32bsp.c b/src/platform/AT32/bus_spi_at32bsp.c index 4182e195f1..fed36d685e 100644 --- a/src/platform/AT32/bus_spi_at32bsp.c +++ b/src/platform/AT32/bus_spi_at32bsp.c @@ -35,7 +35,7 @@ #include "drivers/bus_spi_impl.h" #include "drivers/exti.h" #include "drivers/io.h" -#include "drivers/rcc.h" +#include "platform/rcc.h" // Use DMA if possible if this many bytes are to be transferred #define SPI_DMA_THRESHOLD 8 diff --git a/src/platform/AT32/camera_control_at32.c b/src/platform/AT32/camera_control_at32.c index 12a69d18ca..05f8ef7b98 100644 --- a/src/platform/AT32/camera_control_at32.c +++ b/src/platform/AT32/camera_control_at32.c @@ -28,7 +28,7 @@ #include "drivers/camera_control_impl.h" #include "drivers/nvic.h" #include "drivers/pwm_output.h" -#include "drivers/rcc.h" +#include "platform/rcc.h" #ifdef CAMERA_CONTROL_SOFTWARE_PWM_AVAILABLE #include "build/atomic.h" diff --git a/src/platform/AT32/dma_at32f43x.c b/src/platform/AT32/dma_at32f43x.c index e233713a42..94710fb68d 100644 --- a/src/platform/AT32/dma_at32f43x.c +++ b/src/platform/AT32/dma_at32f43x.c @@ -29,7 +29,7 @@ #include "drivers/nvic.h" #include "drivers/dma.h" -#include "drivers/rcc.h" +#include "platform/rcc.h" #include "drivers/resource.h" /* diff --git a/src/platform/AT32/io_at32.c b/src/platform/AT32/io_at32.c index 5905f4055f..b5759f99f7 100644 --- a/src/platform/AT32/io_at32.c +++ b/src/platform/AT32/io_at32.c @@ -23,7 +23,7 @@ #include "drivers/io.h" #include "drivers/io_impl.h" -#include "drivers/rcc.h" +#include "platform/rcc.h" #include "common/utils.h" diff --git a/src/platform/AT32/light_ws2811strip_at32f43x.c b/src/platform/AT32/light_ws2811strip_at32f43x.c index 1827556d30..e4afd9f202 100644 --- a/src/platform/AT32/light_ws2811strip_at32f43x.c +++ b/src/platform/AT32/light_ws2811strip_at32f43x.c @@ -35,7 +35,7 @@ #include "drivers/dma_reqmap.h" #include "drivers/io.h" #include "drivers/nvic.h" -#include "drivers/rcc.h" +#include "platform/rcc.h" #include "drivers/timer.h" #include "drivers/light_ws2811strip.h" diff --git a/src/platform/AT32/pwm_output_dshot.c b/src/platform/AT32/pwm_output_dshot.c index 2d4722da04..eff7db614e 100644 --- a/src/platform/AT32/pwm_output_dshot.c +++ b/src/platform/AT32/pwm_output_dshot.c @@ -33,7 +33,7 @@ #include "drivers/dma_reqmap.h" #include "drivers/io.h" #include "drivers/nvic.h" -#include "drivers/rcc.h" +#include "platform/rcc.h" #include "drivers/time.h" #include "drivers/timer.h" #include "drivers/system.h" diff --git a/src/platform/AT32/rcc_at32.c b/src/platform/AT32/rcc_at32.c index d3b2d1a4f1..87f8030d4d 100644 --- a/src/platform/AT32/rcc_at32.c +++ b/src/platform/AT32/rcc_at32.c @@ -23,7 +23,7 @@ */ #include "platform.h" -#include "drivers/rcc.h" +#include "platform/rcc.h" void RCC_ClockCmd(rccPeriphTag_t periphTag, FunctionalState NewState) { diff --git a/src/platform/AT32/serial_uart_at32bsp.c b/src/platform/AT32/serial_uart_at32bsp.c index 0875364108..1752de4f71 100644 --- a/src/platform/AT32/serial_uart_at32bsp.c +++ b/src/platform/AT32/serial_uart_at32bsp.c @@ -41,7 +41,7 @@ #include "common/utils.h" #include "drivers/inverter.h" #include "drivers/nvic.h" -#include "drivers/rcc.h" +#include "platform/rcc.h" #include "drivers/dma.h" diff --git a/src/platform/AT32/serial_uart_at32f43x.c b/src/platform/AT32/serial_uart_at32f43x.c index 61733f5266..13f85194fd 100644 --- a/src/platform/AT32/serial_uart_at32f43x.c +++ b/src/platform/AT32/serial_uart_at32f43x.c @@ -31,7 +31,7 @@ #include "drivers/dma.h" #include "drivers/io.h" #include "drivers/nvic.h" -#include "drivers/rcc.h" +#include "platform/rcc.h" #include "drivers/serial.h" #include "drivers/serial_uart.h" diff --git a/src/platform/AT32/timer_at32bsp.c b/src/platform/AT32/timer_at32bsp.c index 6336ad1a2a..a6da1cb51c 100644 --- a/src/platform/AT32/timer_at32bsp.c +++ b/src/platform/AT32/timer_at32bsp.c @@ -35,7 +35,7 @@ #include "drivers/nvic.h" #include "drivers/io.h" -#include "drivers/rcc.h" +#include "platform/rcc.h" #include "drivers/system.h" #include "drivers/timer.h" #include "drivers/timer_impl.h" diff --git a/src/platform/AT32/timer_at32f43x.c b/src/platform/AT32/timer_at32f43x.c index 13c4b99b87..e2e8ecc8d4 100644 --- a/src/platform/AT32/timer_at32f43x.c +++ b/src/platform/AT32/timer_at32f43x.c @@ -28,7 +28,7 @@ #include "timer_def.h" #include "drivers/dma.h" #include "drivers/io.h" -#include "drivers/rcc.h" +#include "platform/rcc.h" #include "drivers/timer.h" const timerDef_t timerDefinitions[HARDWARE_TIMER_DEFINITION_COUNT] = { diff --git a/src/platform/SIMULATOR/include/platform/platform.h b/src/platform/SIMULATOR/include/platform/platform.h index 7fdf22c0f5..4331c71989 100644 --- a/src/platform/SIMULATOR/include/platform/platform.h +++ b/src/platform/SIMULATOR/include/platform/platform.h @@ -35,3 +35,5 @@ #define SERIAL_TRAIT_PIN_CONFIG 0 #define I2CDEV_COUNT 0 + +typedef void* ADC_TypeDef; // Dummy definition for ADC_TypeDef diff --git a/src/platform/STM32/adc_stm32f4xx.c b/src/platform/STM32/adc_stm32f4xx.c index 1a9de8f69d..f8c46d83e6 100644 --- a/src/platform/STM32/adc_stm32f4xx.c +++ b/src/platform/STM32/adc_stm32f4xx.c @@ -31,7 +31,7 @@ #include "drivers/dma_reqmap.h" #include "drivers/io.h" #include "drivers/io_impl.h" -#include "drivers/rcc.h" +#include "platform/rcc.h" #include "drivers/dma.h" #include "drivers/sensor.h" #include "drivers/adc.h" diff --git a/src/platform/STM32/adc_stm32f7xx.c b/src/platform/STM32/adc_stm32f7xx.c index f631543c47..0ef61b3f32 100644 --- a/src/platform/STM32/adc_stm32f7xx.c +++ b/src/platform/STM32/adc_stm32f7xx.c @@ -30,7 +30,7 @@ #include "drivers/dma_reqmap.h" #include "drivers/io.h" #include "drivers/io_impl.h" -#include "drivers/rcc.h" +#include "platform/rcc.h" #include "drivers/sensor.h" #include "drivers/adc.h" diff --git a/src/platform/STM32/adc_stm32g4xx.c b/src/platform/STM32/adc_stm32g4xx.c index 26e6ac9e6b..c378d9cbbd 100644 --- a/src/platform/STM32/adc_stm32g4xx.c +++ b/src/platform/STM32/adc_stm32g4xx.c @@ -31,7 +31,7 @@ #include "drivers/dma_reqmap.h" #include "drivers/io.h" #include "drivers/io_impl.h" -#include "drivers/rcc.h" +#include "platform/rcc.h" #include "drivers/resource.h" #include "drivers/dma.h" diff --git a/src/platform/STM32/adc_stm32h7xx.c b/src/platform/STM32/adc_stm32h7xx.c index 643fff600e..96a3327628 100644 --- a/src/platform/STM32/adc_stm32h7xx.c +++ b/src/platform/STM32/adc_stm32h7xx.c @@ -31,7 +31,7 @@ #include "drivers/dma_reqmap.h" #include "drivers/io.h" #include "drivers/io_impl.h" -#include "drivers/rcc.h" +#include "platform/rcc.h" #include "drivers/resource.h" #include "drivers/dma.h" diff --git a/src/platform/STM32/bus_i2c_hal.c b/src/platform/STM32/bus_i2c_hal.c index bdb3c5fd39..915cc9a7cf 100644 --- a/src/platform/STM32/bus_i2c_hal.c +++ b/src/platform/STM32/bus_i2c_hal.c @@ -30,7 +30,7 @@ #include "drivers/io_impl.h" #include "drivers/nvic.h" #include "drivers/time.h" -#include "drivers/rcc.h" +#include "platform/rcc.h" #include "drivers/bus_i2c.h" #include "drivers/bus_i2c_impl.h" diff --git a/src/platform/STM32/bus_i2c_hal_init.c b/src/platform/STM32/bus_i2c_hal_init.c index 650c034244..d41926a470 100644 --- a/src/platform/STM32/bus_i2c_hal_init.c +++ b/src/platform/STM32/bus_i2c_hal_init.c @@ -29,7 +29,7 @@ #include "drivers/io.h" #include "drivers/nvic.h" #include "drivers/time.h" -#include "drivers/rcc.h" +#include "platform/rcc.h" #include "drivers/bus_i2c.h" #include "drivers/bus_i2c_impl.h" diff --git a/src/platform/STM32/bus_i2c_stm32f4xx.c b/src/platform/STM32/bus_i2c_stm32f4xx.c index 2d7be2dfb5..3a27d75edd 100644 --- a/src/platform/STM32/bus_i2c_stm32f4xx.c +++ b/src/platform/STM32/bus_i2c_stm32f4xx.c @@ -30,7 +30,7 @@ #include "drivers/io.h" #include "drivers/time.h" #include "drivers/nvic.h" -#include "drivers/rcc.h" +#include "platform/rcc.h" #include "drivers/bus_i2c.h" #include "drivers/bus_i2c_impl.h" diff --git a/src/platform/STM32/bus_quadspi_hal.c b/src/platform/STM32/bus_quadspi_hal.c index bc119ee796..efb7226f93 100644 --- a/src/platform/STM32/bus_quadspi_hal.c +++ b/src/platform/STM32/bus_quadspi_hal.c @@ -33,7 +33,7 @@ #include "drivers/io.h" #include "drivers/io_impl.h" #include "drivers/nvic.h" -#include "drivers/rcc.h" +#include "platform/rcc.h" #include "pg/bus_quadspi.h" diff --git a/src/platform/STM32/bus_spi_ll.c b/src/platform/STM32/bus_spi_ll.c index 9e3d3ea21c..2a12575335 100644 --- a/src/platform/STM32/bus_spi_ll.c +++ b/src/platform/STM32/bus_spi_ll.c @@ -34,7 +34,7 @@ #include "drivers/bus_spi_impl.h" #include "drivers/dma.h" #include "drivers/io.h" -#include "drivers/rcc.h" +#include "platform/rcc.h" // Use DMA if possible if this many bytes are to be transferred #define SPI_DMA_THRESHOLD 8 diff --git a/src/platform/STM32/bus_spi_stdperiph.c b/src/platform/STM32/bus_spi_stdperiph.c index 5fcf671528..9bb02fba80 100644 --- a/src/platform/STM32/bus_spi_stdperiph.c +++ b/src/platform/STM32/bus_spi_stdperiph.c @@ -35,7 +35,7 @@ #include "drivers/bus_spi_impl.h" #include "drivers/exti.h" #include "drivers/io.h" -#include "drivers/rcc.h" +#include "platform/rcc.h" // Use DMA if possible if this many bytes are to be transferred #define SPI_DMA_THRESHOLD 8 diff --git a/src/platform/STM32/dma_stm32f7xx.c b/src/platform/STM32/dma_stm32f7xx.c index 14ece8e35c..eb432a39d7 100644 --- a/src/platform/STM32/dma_stm32f7xx.c +++ b/src/platform/STM32/dma_stm32f7xx.c @@ -28,7 +28,7 @@ #include "drivers/nvic.h" #include "drivers/dma.h" -#include "drivers/rcc.h" +#include "platform/rcc.h" #include "drivers/resource.h" /* diff --git a/src/platform/STM32/dma_stm32g4xx.c b/src/platform/STM32/dma_stm32g4xx.c index 6e0d805038..d8e9d25672 100644 --- a/src/platform/STM32/dma_stm32g4xx.c +++ b/src/platform/STM32/dma_stm32g4xx.c @@ -28,7 +28,7 @@ #include "drivers/nvic.h" #include "drivers/dma.h" -#include "drivers/rcc.h" +#include "platform/rcc.h" #include "drivers/resource.h" /* diff --git a/src/platform/STM32/dma_stm32h7xx.c b/src/platform/STM32/dma_stm32h7xx.c index 52d7aa1a27..9ecbc185a9 100644 --- a/src/platform/STM32/dma_stm32h7xx.c +++ b/src/platform/STM32/dma_stm32h7xx.c @@ -28,7 +28,7 @@ #include "drivers/nvic.h" #include "drivers/dma.h" -#include "drivers/rcc.h" +#include "platform/rcc.h" #include "drivers/resource.h" /* diff --git a/src/platform/STM32/include/platform/platform.h b/src/platform/STM32/include/platform/platform.h index 53ea0cf11b..3f9e13e5a1 100644 --- a/src/platform/STM32/include/platform/platform.h +++ b/src/platform/STM32/include/platform/platform.h @@ -441,3 +441,10 @@ extern uint8_t _dmaram_end__; #else #define I2CDEV_COUNT 4 #endif + +// QUAD SPI +#if defined(STM32H7) +#define QUADSPI_TRAIT_AF_PIN 1 +#define QUADSPI_TRAIT_HANDLE 1 +#define MAX_QUADSPI_PIN_SEL 3 +#endif diff --git a/src/platform/STM32/io_stm32.c b/src/platform/STM32/io_stm32.c index 2557f09764..abcde9cf92 100644 --- a/src/platform/STM32/io_stm32.c +++ b/src/platform/STM32/io_stm32.c @@ -22,7 +22,7 @@ #include "drivers/io.h" #include "drivers/io_impl.h" -#include "drivers/rcc.h" +#include "platform/rcc.h" #include "common/utils.h" diff --git a/src/platform/STM32/light_ws2811strip_hal.c b/src/platform/STM32/light_ws2811strip_hal.c index bdb9487851..c5f885c1b2 100644 --- a/src/platform/STM32/light_ws2811strip_hal.c +++ b/src/platform/STM32/light_ws2811strip_hal.c @@ -31,7 +31,7 @@ #include "drivers/dma_reqmap.h" #include "drivers/io.h" #include "drivers/nvic.h" -#include "drivers/rcc.h" +#include "platform/rcc.h" #include "drivers/system.h" #include "drivers/timer.h" diff --git a/src/platform/STM32/light_ws2811strip_stdperiph.c b/src/platform/STM32/light_ws2811strip_stdperiph.c index 1b4dbf9017..13723de3f5 100644 --- a/src/platform/STM32/light_ws2811strip_stdperiph.c +++ b/src/platform/STM32/light_ws2811strip_stdperiph.c @@ -34,7 +34,7 @@ #include "drivers/dma_reqmap.h" #include "drivers/io.h" #include "drivers/nvic.h" -#include "drivers/rcc.h" +#include "platform/rcc.h" #include "drivers/timer.h" #include "drivers/light_ws2811strip.h" diff --git a/src/platform/STM32/pwm_output_dshot.c b/src/platform/STM32/pwm_output_dshot.c index dcf2bba859..506a147364 100644 --- a/src/platform/STM32/pwm_output_dshot.c +++ b/src/platform/STM32/pwm_output_dshot.c @@ -32,7 +32,7 @@ #include "drivers/dma_reqmap.h" #include "drivers/io.h" #include "drivers/nvic.h" -#include "drivers/rcc.h" +#include "platform/rcc.h" #include "drivers/time.h" #include "drivers/timer.h" #include "drivers/system.h" diff --git a/src/platform/STM32/pwm_output_dshot_hal.c b/src/platform/STM32/pwm_output_dshot_hal.c index 3e6fe722a3..0c82414916 100644 --- a/src/platform/STM32/pwm_output_dshot_hal.c +++ b/src/platform/STM32/pwm_output_dshot_hal.c @@ -40,7 +40,7 @@ #include "drivers/motor.h" #include "drivers/pwm_output.h" #include "pwm_output_dshot_shared.h" -#include "drivers/rcc.h" +#include "platform/rcc.h" #include "drivers/time.h" #include "drivers/timer.h" #include "drivers/system.h" diff --git a/src/platform/STM32/rcc_stm32.c b/src/platform/STM32/rcc_stm32.c index f8afd03f36..17f10fbb52 100644 --- a/src/platform/STM32/rcc_stm32.c +++ b/src/platform/STM32/rcc_stm32.c @@ -19,7 +19,7 @@ */ #include "platform.h" -#include "drivers/rcc.h" +#include "platform/rcc.h" void RCC_ClockCmd(rccPeriphTag_t periphTag, FunctionalState NewState) { diff --git a/src/platform/STM32/sdio_f4xx.c b/src/platform/STM32/sdio_f4xx.c index ec64647c3f..3aba6decb5 100644 --- a/src/platform/STM32/sdio_f4xx.c +++ b/src/platform/STM32/sdio_f4xx.c @@ -44,7 +44,7 @@ #include "drivers/io_impl.h" #include "drivers/nvic.h" #include "drivers/time.h" -#include "drivers/rcc.h" +#include "platform/rcc.h" #include "drivers/dma.h" #include "drivers/light_led.h" diff --git a/src/platform/STM32/sdio_f7xx.c b/src/platform/STM32/sdio_f7xx.c index 2f1bc62b5c..112028e6f8 100644 --- a/src/platform/STM32/sdio_f7xx.c +++ b/src/platform/STM32/sdio_f7xx.c @@ -41,7 +41,7 @@ #include "drivers/io_impl.h" #include "drivers/nvic.h" #include "drivers/time.h" -#include "drivers/rcc.h" +#include "platform/rcc.h" #include "drivers/dma.h" #include "drivers/light_led.h" diff --git a/src/platform/STM32/serial_uart_hal.c b/src/platform/STM32/serial_uart_hal.c index f319bce78c..862bdb68d6 100644 --- a/src/platform/STM32/serial_uart_hal.c +++ b/src/platform/STM32/serial_uart_hal.c @@ -42,7 +42,7 @@ #include "drivers/nvic.h" #include "drivers/inverter.h" #include "drivers/dma.h" -#include "drivers/rcc.h" +#include "platform/rcc.h" #include "drivers/serial.h" #include "drivers/serial_uart.h" diff --git a/src/platform/STM32/serial_uart_stdperiph.c b/src/platform/STM32/serial_uart_stdperiph.c index b65275c427..b028371dff 100644 --- a/src/platform/STM32/serial_uart_stdperiph.c +++ b/src/platform/STM32/serial_uart_stdperiph.c @@ -42,7 +42,7 @@ #include "common/utils.h" #include "drivers/inverter.h" #include "drivers/nvic.h" -#include "drivers/rcc.h" +#include "platform/rcc.h" #include "drivers/serial.h" #include "drivers/serial_uart.h" diff --git a/src/platform/STM32/serial_uart_stm32f4xx.c b/src/platform/STM32/serial_uart_stm32f4xx.c index d289a1e671..a2ab2fc714 100644 --- a/src/platform/STM32/serial_uart_stm32f4xx.c +++ b/src/platform/STM32/serial_uart_stm32f4xx.c @@ -35,7 +35,7 @@ #include "drivers/io.h" #include "drivers/dma.h" #include "drivers/nvic.h" -#include "drivers/rcc.h" +#include "platform/rcc.h" #include "drivers/serial.h" #include "drivers/serial_uart.h" diff --git a/src/platform/STM32/serial_uart_stm32f7xx.c b/src/platform/STM32/serial_uart_stm32f7xx.c index 3205cf8620..ad67a92f0e 100644 --- a/src/platform/STM32/serial_uart_stm32f7xx.c +++ b/src/platform/STM32/serial_uart_stm32f7xx.c @@ -33,7 +33,7 @@ #include "drivers/dma.h" #include "drivers/io.h" #include "drivers/nvic.h" -#include "drivers/rcc.h" +#include "platform/rcc.h" #include "drivers/serial.h" #include "drivers/serial_uart.h" diff --git a/src/platform/STM32/serial_uart_stm32g4xx.c b/src/platform/STM32/serial_uart_stm32g4xx.c index 211e6f41fa..2042df06dd 100644 --- a/src/platform/STM32/serial_uart_stm32g4xx.c +++ b/src/platform/STM32/serial_uart_stm32g4xx.c @@ -31,7 +31,7 @@ #include "drivers/dma.h" #include "drivers/io.h" #include "drivers/nvic.h" -#include "drivers/rcc.h" +#include "platform/rcc.h" #include "drivers/serial.h" #include "drivers/serial_uart.h" diff --git a/src/platform/STM32/serial_uart_stm32h7xx.c b/src/platform/STM32/serial_uart_stm32h7xx.c index bbed4b6ed0..898fdf0937 100644 --- a/src/platform/STM32/serial_uart_stm32h7xx.c +++ b/src/platform/STM32/serial_uart_stm32h7xx.c @@ -33,7 +33,7 @@ #include "drivers/dma.h" #include "drivers/io.h" #include "drivers/nvic.h" -#include "drivers/rcc.h" +#include "platform/rcc.h" #include "drivers/serial.h" #include "drivers/serial_uart.h" diff --git a/src/platform/STM32/timer_hal.c b/src/platform/STM32/timer_hal.c index c9e9180f6c..e4ea1a413a 100644 --- a/src/platform/STM32/timer_hal.c +++ b/src/platform/STM32/timer_hal.c @@ -36,7 +36,7 @@ #include "drivers/io.h" #include "drivers/dma.h" -#include "drivers/rcc.h" +#include "platform/rcc.h" #include "drivers/timer.h" #include "drivers/timer_impl.h" diff --git a/src/platform/STM32/timer_stdperiph.c b/src/platform/STM32/timer_stdperiph.c index 8e0c2bc95a..c5ecefba24 100644 --- a/src/platform/STM32/timer_stdperiph.c +++ b/src/platform/STM32/timer_stdperiph.c @@ -34,12 +34,13 @@ #include "drivers/nvic.h" #include "drivers/io.h" -#include "drivers/rcc.h" #include "drivers/system.h" #include "drivers/timer.h" #include "drivers/timer_impl.h" +#include "platform/rcc.h" + #define TIM_N(n) (1 << (n)) /* diff --git a/src/platform/STM32/timer_stm32f4xx.c b/src/platform/STM32/timer_stm32f4xx.c index 4bc5b1d2db..ed193e64f7 100644 --- a/src/platform/STM32/timer_stm32f4xx.c +++ b/src/platform/STM32/timer_stm32f4xx.c @@ -29,7 +29,7 @@ #include "timer_def.h" #include "stm32f4xx.h" -#include "drivers/rcc.h" +#include "platform/rcc.h" #include "drivers/timer.h" const timerDef_t timerDefinitions[HARDWARE_TIMER_DEFINITION_COUNT] = { diff --git a/src/platform/STM32/timer_stm32f7xx.c b/src/platform/STM32/timer_stm32f7xx.c index 464873c89c..92f958929d 100644 --- a/src/platform/STM32/timer_stm32f7xx.c +++ b/src/platform/STM32/timer_stm32f7xx.c @@ -29,7 +29,7 @@ #include "timer_def.h" #include "stm32f7xx.h" -#include "drivers/rcc.h" +#include "platform/rcc.h" #include "drivers/timer.h" const timerDef_t timerDefinitions[HARDWARE_TIMER_DEFINITION_COUNT] = { diff --git a/src/platform/STM32/timer_stm32g4xx.c b/src/platform/STM32/timer_stm32g4xx.c index e93f79fbe2..c2256e6c67 100644 --- a/src/platform/STM32/timer_stm32g4xx.c +++ b/src/platform/STM32/timer_stm32g4xx.c @@ -29,7 +29,7 @@ #include "timer_def.h" #include "stm32g4xx.h" -#include "drivers/rcc.h" +#include "platform/rcc.h" #include "drivers/timer.h" const timerDef_t timerDefinitions[HARDWARE_TIMER_DEFINITION_COUNT] = { diff --git a/src/platform/STM32/timer_stm32h5xx.c b/src/platform/STM32/timer_stm32h5xx.c index e4d06b9335..c9edec4ba6 100644 --- a/src/platform/STM32/timer_stm32h5xx.c +++ b/src/platform/STM32/timer_stm32h5xx.c @@ -30,7 +30,7 @@ #include "timer_def.h" #include "stm32h5xx.h" -#include "drivers/rcc.h" +#include "platform/rcc.h" #include "drivers/timer.h" const timerDef_t timerDefinitions[HARDWARE_TIMER_DEFINITION_COUNT] = { diff --git a/src/platform/STM32/timer_stm32h7xx.c b/src/platform/STM32/timer_stm32h7xx.c index 3462e9d7f2..4fa37a0423 100644 --- a/src/platform/STM32/timer_stm32h7xx.c +++ b/src/platform/STM32/timer_stm32h7xx.c @@ -29,7 +29,7 @@ #include "timer_def.h" #include "stm32h7xx.h" -#include "drivers/rcc.h" +#include "platform/rcc.h" #include "drivers/timer.h" const timerDef_t timerDefinitions[HARDWARE_TIMER_DEFINITION_COUNT] = { diff --git a/src/platform/STM32/transponder_ir_io_hal.c b/src/platform/STM32/transponder_ir_io_hal.c index 1f3f203407..51ae36da97 100644 --- a/src/platform/STM32/transponder_ir_io_hal.c +++ b/src/platform/STM32/transponder_ir_io_hal.c @@ -30,7 +30,7 @@ #include "drivers/dma_reqmap.h" #include "drivers/io.h" #include "drivers/nvic.h" -#include "drivers/rcc.h" +#include "platform/rcc.h" #include "drivers/timer.h" #include "drivers/transponder_ir_arcitimer.h" #include "drivers/transponder_ir_erlt.h" diff --git a/src/platform/STM32/transponder_ir_io_stdperiph.c b/src/platform/STM32/transponder_ir_io_stdperiph.c index 0d4170cc0f..03d6c735c0 100644 --- a/src/platform/STM32/transponder_ir_io_stdperiph.c +++ b/src/platform/STM32/transponder_ir_io_stdperiph.c @@ -30,7 +30,7 @@ #include "drivers/dma_reqmap.h" #include "drivers/io.h" #include "drivers/nvic.h" -#include "drivers/rcc.h" +#include "platform/rcc.h" #include "drivers/timer.h" #include "drivers/transponder_ir_arcitimer.h" #include "drivers/transponder_ir_erlt.h" diff --git a/src/platform/common/stm32/bus_spi_pinconfig.c b/src/platform/common/stm32/bus_spi_pinconfig.c index 02cc24ac9a..52d2d456c2 100644 --- a/src/platform/common/stm32/bus_spi_pinconfig.c +++ b/src/platform/common/stm32/bus_spi_pinconfig.c @@ -33,7 +33,7 @@ #include "drivers/dma.h" #include "drivers/exti.h" #include "drivers/io.h" -#include "drivers/rcc.h" +#include "platform/rcc.h" #include "pg/bus_spi.h" diff --git a/src/main/drivers/rcc.h b/src/platform/common/stm32/platform/rcc.h similarity index 99% rename from src/main/drivers/rcc.h rename to src/platform/common/stm32/platform/rcc.h index cdd2e3d1dd..69641b5e2d 100644 --- a/src/main/drivers/rcc.h +++ b/src/platform/common/stm32/platform/rcc.h @@ -20,7 +20,7 @@ #pragma once -#include "rcc_types.h" +#include "platform/rcc_types.h" enum rcc_reg { RCC_EMPTY = 0, // make sure that default value (0) does not enable anything diff --git a/src/main/drivers/rcc_types.h b/src/platform/common/stm32/platform/rcc_types.h similarity index 100% rename from src/main/drivers/rcc_types.h rename to src/platform/common/stm32/platform/rcc_types.h diff --git a/src/platform/common/stm32/pwm_output_dshot_shared.c b/src/platform/common/stm32/pwm_output_dshot_shared.c index ccf2ab661d..1bf57ee98d 100644 --- a/src/platform/common/stm32/pwm_output_dshot_shared.c +++ b/src/platform/common/stm32/pwm_output_dshot_shared.c @@ -33,7 +33,7 @@ #include "drivers/dma_reqmap.h" #include "drivers/io.h" #include "drivers/nvic.h" -#include "drivers/rcc.h" +#include "platform/rcc.h" #include "drivers/time.h" #include "drivers/timer.h" #if defined(STM32F4) diff --git a/src/platform/common/stm32/serial_uart_hw.c b/src/platform/common/stm32/serial_uart_hw.c index 74e32147cf..1103a80db6 100644 --- a/src/platform/common/stm32/serial_uart_hw.c +++ b/src/platform/common/stm32/serial_uart_hw.c @@ -33,7 +33,7 @@ #include "build/build_config.h" #include "drivers/nvic.h" -#include "drivers/rcc.h" +#include "platform/rcc.h" #include "drivers/inverter.h" #include "drivers/serial.h" #include "drivers/serial_impl.h" From 3a70ece36485ac9b53a1f1469dcb66c14ade534a Mon Sep 17 00:00:00 2001 From: Jay Blackman Date: Sun, 8 Jun 2025 08:44:11 +1000 Subject: [PATCH 234/244] REFACTOR: missed trait defines (#14435) --- src/main/drivers/bus_i2c_config.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/main/drivers/bus_i2c_config.c b/src/main/drivers/bus_i2c_config.c index 4cf78c03ba..7b27532cbf 100644 --- a/src/main/drivers/bus_i2c_config.c +++ b/src/main/drivers/bus_i2c_config.c @@ -56,13 +56,13 @@ void i2cHardwareConfigure(const i2cConfig_t *i2cConfig) for (int pindex = 0 ; pindex < I2C_PIN_SEL_MAX ; pindex++) { if (i2cConfig[device].ioTagScl == hardware->sclPins[pindex].ioTag) { pDev->scl = IOGetByTag(i2cConfig[device].ioTagScl); -#if defined(STM32F4) || defined(STM32H7) || defined(STM32G4) || defined(AT32F4) || defined(APM32F4) +#if I2C_TRAIT_AF_PIN pDev->sclAF = hardware->sclPins[pindex].af; #endif } if (i2cConfig[device].ioTagSda == hardware->sdaPins[pindex].ioTag) { pDev->sda = IOGetByTag(i2cConfig[device].ioTagSda); -#if defined(STM32F4) || defined(STM32H7) || defined(STM32G4) || defined(AT32F4) || defined(APM32F4) +#if I2C_TRAIT_AF_PIN pDev->sdaAF = hardware->sdaPins[pindex].af; #endif } From e55aa12e6d4fafe6ad2283b39905ef373362022d Mon Sep 17 00:00:00 2001 From: "Git bot (blckmn)" Date: Mon, 9 Jun 2025 06:25:03 +0000 Subject: [PATCH 235/244] Auto updated submodule references [09-06-2025] --- src/config | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/config b/src/config index 737c3460fa..ebc7aa2c44 160000 --- a/src/config +++ b/src/config @@ -1 +1 @@ -Subproject commit 737c3460fa621696af079367c86ca2be28194631 +Subproject commit ebc7aa2c4498452b06a20e408080f51ce562f587 From e3267189ccfd754144b1184022c50589add7d7b8 Mon Sep 17 00:00:00 2001 From: "Git bot (blckmn)" Date: Tue, 10 Jun 2025 06:25:03 +0000 Subject: [PATCH 236/244] Auto updated submodule references [10-06-2025] --- src/config | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/config b/src/config index ebc7aa2c44..ec429513a6 160000 --- a/src/config +++ b/src/config @@ -1 +1 @@ -Subproject commit ebc7aa2c4498452b06a20e408080f51ce562f587 +Subproject commit ec429513a68b3362647ead039719f12f156edcf4 From 1b1648d135cc215f3ea64db334f42124a301953a Mon Sep 17 00:00:00 2001 From: Jay Blackman Date: Tue, 10 Jun 2025 19:37:03 +1000 Subject: [PATCH 237/244] APM: Formatting changes for cleanup (#14431) * APM: Formatting changes for cleanup * Formatting inconsistency * Missed in first round * Adjusted as per @ledvinap --- src/platform/APM32/adc_apm32f4xx.c | 3 +- src/platform/APM32/apm32f4xx_ddl_ex.h | 9 +- src/platform/APM32/bus_i2c_apm32.c | 22 ++-- src/platform/APM32/bus_spi_apm32.c | 3 +- src/platform/APM32/dshot_bitbang.c | 25 +++-- src/platform/APM32/dshot_bitbang_ddl.c | 19 +--- src/platform/APM32/pwm_output_dshot_apm32.c | 98 +++++++++--------- src/platform/APM32/serial_uart_apm32.c | 100 ++++++++++--------- src/platform/APM32/serial_uart_apm32f4xx.c | 2 + src/platform/APM32/system_apm32f4xx.c | 5 +- src/platform/APM32/timer_apm32.c | 81 +++++++++------ src/platform/APM32/transponder_ir_io_apm32.c | 1 + 12 files changed, 199 insertions(+), 169 deletions(-) diff --git a/src/platform/APM32/adc_apm32f4xx.c b/src/platform/APM32/adc_apm32f4xx.c index f577804602..38004b23be 100644 --- a/src/platform/APM32/adc_apm32f4xx.c +++ b/src/platform/APM32/adc_apm32f4xx.c @@ -270,8 +270,7 @@ void adcInit(const adcConfig_t *config) adcInitDevice(&adcInternal, 2); DDL_ADC_Enable(adcInternal.ADCx); adcInitInternalInjected(&adcInternal); - } - else { + } else { // Initialize for injected conversion adcInitInternalInjected(&adc); } diff --git a/src/platform/APM32/apm32f4xx_ddl_ex.h b/src/platform/APM32/apm32f4xx_ddl_ex.h index 187448df8d..30d53da2ac 100644 --- a/src/platform/APM32/apm32f4xx_ddl_ex.h +++ b/src/platform/APM32/apm32f4xx_ddl_ex.h @@ -31,10 +31,12 @@ __STATIC_INLINE void DDL_EX_TMR_DisableIT(TMR_TypeDef *TMRx, uint32_t Sources) { CLEAR_BIT(TMRx->DIEN, Sources); } + __STATIC_INLINE void DDL_EX_TMR_EnableIT(TMR_TypeDef *TMRx, uint32_t Sources) { SET_BIT(TMRx->DIEN, Sources); } + __STATIC_INLINE uint32_t DDL_EX_DMA_Stream_to_Stream(DMA_Stream_TypeDef *DMAx_Streamy) { STATIC_ASSERT(DMA1_Stream0_BASE - DMA1_BASE == sizeof(DMA_TypeDef), DMA_TypeDef_has_padding); @@ -45,11 +47,13 @@ __STATIC_INLINE uint32_t DDL_EX_DMA_Stream_to_Stream(DMA_Stream_TypeDef *DMAx_St return (((uint32_t) DMAx_Streamy & 0XFF) - firstStreamOffset) / streamSize; } + __STATIC_INLINE DMA_TypeDef *DDL_EX_DMA_Stream_to_DMA(DMA_Stream_TypeDef *DMAx_Streamy) { // clear stream address return (DMA_TypeDef *) (((uint32_t) DMAx_Streamy) & ((uint32_t) ~0XFF)); } + __STATIC_INLINE uint32_t DDL_EX_DMA_DeInit(DMA_Stream_TypeDef *DMAx_Streamy) { DMA_TypeDef *DMA = DDL_EX_DMA_Stream_to_DMA(DMAx_Streamy); @@ -57,6 +61,7 @@ __STATIC_INLINE uint32_t DDL_EX_DMA_DeInit(DMA_Stream_TypeDef *DMAx_Streamy) return DDL_DMA_DeInit(DMA, Stream); } + __STATIC_INLINE uint32_t DDL_EX_DMA_Init(DMA_Stream_TypeDef *DMAx_Streamy, DDL_DMA_InitTypeDef *DMA_InitStruct) { DMA_TypeDef *DMA = DDL_EX_DMA_Stream_to_DMA(DMAx_Streamy); @@ -64,6 +69,7 @@ __STATIC_INLINE uint32_t DDL_EX_DMA_Init(DMA_Stream_TypeDef *DMAx_Streamy, DDL_D return DDL_DMA_Init(DMA, Stream, DMA_InitStruct); } + __STATIC_INLINE void DDL_EX_DMA_SetDataLength(DMA_Stream_TypeDef* DMAx_Streamy, uint32_t NbData) { MODIFY_REG(DMAx_Streamy->NDATA, DMA_NDATAx, NbData); @@ -81,6 +87,7 @@ __STATIC_INLINE void DDL_EX_DMA_EnableResource(DMA_Stream_TypeDef *DMAx_Streamy) { SET_BIT(DMAx_Streamy->SCFG, DMA_SCFGx_EN); } + __STATIC_INLINE void DDL_EX_DMA_DisableResource(DMA_Stream_TypeDef *DMAx_Streamy) { CLEAR_BIT(DMAx_Streamy->SCFG, DMA_SCFGx_EN); @@ -94,4 +101,4 @@ __STATIC_INLINE void DDL_EX_DMA_EnableIT_TC(DMA_Stream_TypeDef *DMAx_Streamy) __STATIC_INLINE void DDL_EX_TMR_CC_EnableNChannel(TMR_TypeDef *TMRx, uint32_t Channel) { DDL_TMR_CC_EnableChannel(TMRx, 4 * Channel); -} \ No newline at end of file +} diff --git a/src/platform/APM32/bus_i2c_apm32.c b/src/platform/APM32/bus_i2c_apm32.c index 3b51cee474..147e5e986a 100644 --- a/src/platform/APM32/bus_i2c_apm32.c +++ b/src/platform/APM32/bus_i2c_apm32.c @@ -76,7 +76,7 @@ static volatile uint16_t i2cErrorCount = 0; static bool i2cHandleHardwareFailure(I2CDevice device) { - (void)device; + UNUSED(device); i2cErrorCount++; // reinit peripheral + clock out garbage //i2cInit(device); @@ -103,13 +103,15 @@ bool i2cWrite(I2CDevice device, uint8_t addr_, uint8_t reg_, uint8_t data) HAL_StatusTypeDef status; - if (reg_ == 0xFF) + if (reg_ == 0xFF) { status = DAL_I2C_Master_Transmit(pHandle ,addr_ << 1, &data, 1, I2C_TIMEOUT_SYS_TICKS); - else + } else { status = DAL_I2C_Mem_Write(pHandle ,addr_ << 1, reg_, I2C_MEMADD_SIZE_8BIT, &data, 1, I2C_TIMEOUT_SYS_TICKS); + } - if (status != DAL_OK) + if (status != DAL_OK) { return i2cHandleHardwareFailure(device); + } return true; } @@ -135,8 +137,7 @@ bool i2cWriteBuffer(I2CDevice device, uint8_t addr_, uint8_t reg_, uint8_t len_, return false; } - if (status != DAL_OK) - { + if (status != DAL_OK) { return i2cHandleHardwareFailure(device); } @@ -158,10 +159,11 @@ bool i2cRead(I2CDevice device, uint8_t addr_, uint8_t reg_, uint8_t len, uint8_t DAL_StatusTypeDef status; - if (reg_ == 0xFF) + if (reg_ == 0xFF) { status = DAL_I2C_Master_Receive(pHandle ,addr_ << 1, buf, len, I2C_TIMEOUT_SYS_TICKS); - else + } else { status = DAL_I2C_Mem_Read(pHandle, addr_ << 1, reg_, I2C_MEMADD_SIZE_8BIT,buf, len, I2C_TIMEOUT_SYS_TICKS); + } if (status != DAL_OK) { return i2cHandleHardwareFailure(device); @@ -206,8 +208,7 @@ bool i2cBusy(I2CDevice device, bool *error) *error = pHandle->ErrorCode; } - if (pHandle->State == DAL_I2C_STATE_READY) - { + if (pHandle->State == DAL_I2C_STATE_READY) { if (__DAL_I2C_GET_FLAG(pHandle, I2C_FLAG_BUSY) == SET) { return true; @@ -218,5 +219,4 @@ bool i2cBusy(I2CDevice device, bool *error) return true; } - #endif diff --git a/src/platform/APM32/bus_spi_apm32.c b/src/platform/APM32/bus_spi_apm32.c index 2b9a484975..6c58c5e8da 100644 --- a/src/platform/APM32/bus_spi_apm32.c +++ b/src/platform/APM32/bus_spi_apm32.c @@ -347,8 +347,7 @@ FAST_CODE void spiSequenceStart(const extDevice_t *dev) IOConfigGPIOAF(IOGetByTag(spi->sck), SPI_IO_AF_SCK_CFG_LOW, spi->sckAF); DDL_SPI_SetClockPhase(instance, DDL_SPI_PHASE_1EDGE); DDL_SPI_SetClockPolarity(instance, DDL_SPI_POLARITY_LOW); - } - else { + } else { IOConfigGPIOAF(IOGetByTag(spi->sck), SPI_IO_AF_SCK_CFG_HIGH, spi->sckAF); DDL_SPI_SetClockPhase(instance, DDL_SPI_PHASE_2EDGE); DDL_SPI_SetClockPolarity(instance, DDL_SPI_POLARITY_HIGH); diff --git a/src/platform/APM32/dshot_bitbang.c b/src/platform/APM32/dshot_bitbang.c index cf971adf97..caec5e0bec 100644 --- a/src/platform/APM32/dshot_bitbang.c +++ b/src/platform/APM32/dshot_bitbang.c @@ -450,14 +450,15 @@ static bool bbMotorConfig(IO_t io, uint8_t motorIndex, motorProtocolTypes_e pwmP bbGpioSetup(&bbMotors[motorIndex]); + do { #ifdef USE_DSHOT_TELEMETRY if (useDshotTelemetry) { bbOutputDataInit(bbPort->portOutputBuffer, (1 << pinIndex), DSHOT_BITBANG_INVERTED); - } else -#endif - { - bbOutputDataInit(bbPort->portOutputBuffer, (1 << pinIndex), DSHOT_BITBANG_NONINVERTED); + break; } +#endif + bbOutputDataInit(bbPort->portOutputBuffer, (1 << pinIndex), DSHOT_BITBANG_NONINVERTED); + } while (false); bbSwitchToOutput(bbPort); @@ -577,14 +578,15 @@ static void bbWriteInt(uint8_t motorIndex, uint16_t value) bbPort_t *bbPort = bbmotor->bbPort; + do { #ifdef USE_DSHOT_TELEMETRY - if (useDshotTelemetry) { - bbOutputDataSet(bbPort->portOutputBuffer, bbmotor->pinIndex, packet, DSHOT_BITBANG_INVERTED); - } else + if (useDshotTelemetry) { + bbOutputDataSet(bbPort->portOutputBuffer, bbmotor->pinIndex, packet, DSHOT_BITBANG_INVERTED); + break; + } #endif - { bbOutputDataSet(bbPort->portOutputBuffer, bbmotor->pinIndex, packet, DSHOT_BITBANG_NONINVERTED); - } + } while (false); } static void bbWrite(uint8_t motorIndex, float value) @@ -614,11 +616,8 @@ static void bbUpdateComplete(void) bbPort->inputActive = false; bbSwitchToOutput(bbPort); } - } else -#endif - { - // Nothing to do } +#endif bbDMA_Cmd(bbPort, ENABLE); } diff --git a/src/platform/APM32/dshot_bitbang_ddl.c b/src/platform/APM32/dshot_bitbang_ddl.c index dc7301c491..6e2eeff13b 100644 --- a/src/platform/APM32/dshot_bitbang_ddl.c +++ b/src/platform/APM32/dshot_bitbang_ddl.c @@ -56,23 +56,12 @@ void bbGpioSetup(bbMotor_t *bbMotor) bbPort->gpioModeInput |= (DDL_GPIO_MODE_INPUT << (pinIndex * 2)); bbPort->gpioModeOutput |= (DDL_GPIO_MODE_OUTPUT << (pinIndex * 2)); + bool inverted = false; #ifdef USE_DSHOT_TELEMETRY - if (useDshotTelemetry) { - bbPort->gpioIdleBSRR |= (1 << pinIndex); // BS (lower half) - } else + inverted = true; #endif - { - bbPort->gpioIdleBSRR |= (1 << (pinIndex + 16)); // BR (higher half) - } - -#ifdef USE_DSHOT_TELEMETRY - if (useDshotTelemetry) { - IOWrite(bbMotor->io, 1); - } else -#endif - { - IOWrite(bbMotor->io, 0); - } + bbPort->gpioIdleBSRR |= (1 << pinIndex) + (inverted ? 0 : 16); // write BITSET or BITRESET half of BSRR + IOWrite(bbMotor->io, inverted); } void bbTimerChannelInit(bbPort_t *bbPort) diff --git a/src/platform/APM32/pwm_output_dshot_apm32.c b/src/platform/APM32/pwm_output_dshot_apm32.c index 203df9fefc..57010f08e8 100644 --- a/src/platform/APM32/pwm_output_dshot_apm32.c +++ b/src/platform/APM32/pwm_output_dshot_apm32.c @@ -133,18 +133,19 @@ FAST_CODE void pwmCompleteDshotMotorUpdate(void) } for (int i = 0; i < dmaMotorTimerCount; i++) { + do { #ifdef USE_DSHOT_DMAR - if (useBurstDshot) { - xDDL_EX_DMA_SetDataLength(dmaMotorTimers[i].dmaBurstRef, dmaMotorTimers[i].dmaBurstLength); - xDDL_EX_DMA_EnableResource(dmaMotorTimers[i].dmaBurstRef); + if (useBurstDshot) { + xDDL_EX_DMA_SetDataLength(dmaMotorTimers[i].dmaBurstRef, dmaMotorTimers[i].dmaBurstLength); + xDDL_EX_DMA_EnableResource(dmaMotorTimers[i].dmaBurstRef); - /* configure the DMA Burst Mode */ - DDL_TMR_ConfigDMABurst(dmaMotorTimers[i].timer, DDL_TMR_DMABURST_BASEADDR_CC1, DDL_TMR_DMABURST_LENGTH_4TRANSFERS); - /* Enable the TIM DMA Request */ - DDL_TMR_EnableDMAReq_UPDATE(dmaMotorTimers[i].timer); - } else + /* configure the DMA Burst Mode */ + DDL_TMR_ConfigDMABurst(dmaMotorTimers[i].timer, DDL_TMR_DMABURST_BASEADDR_CC1, DDL_TMR_DMABURST_LENGTH_4TRANSFERS); + /* Enable the TIM DMA Request */ + DDL_TMR_EnableDMAReq_UPDATE(dmaMotorTimers[i].timer); + break; + } #endif - { DDL_TMR_DisableARRPreload(dmaMotorTimers[i].timer); dmaMotorTimers[i].timer->AUTORLD = dmaMotorTimers[i].outputPeriod; @@ -153,7 +154,7 @@ FAST_CODE void pwmCompleteDshotMotorUpdate(void) /* Enable channel DMA requests */ DDL_EX_TMR_EnableIT(dmaMotorTimers[i].timer, dmaMotorTimers[i].timerDmaSources); dmaMotorTimers[i].timerDmaSources = 0; - } + } while (false); } } @@ -164,16 +165,17 @@ FAST_CODE static void motor_DMA_IRQHandler(dmaChannelDescriptor_t* descriptor) #ifdef USE_DSHOT_TELEMETRY dshotDMAHandlerCycleCounters.irqAt = getCycleCounter(); #endif + do { #ifdef USE_DSHOT_DMAR - if (useBurstDshot) { - xDDL_EX_DMA_DisableResource(motor->timerHardware->dmaTimUPRef); - DDL_TMR_DisableDMAReq_UPDATE(motor->timerHardware->tim); - } else + if (useBurstDshot) { + xDDL_EX_DMA_DisableResource(motor->timerHardware->dmaTimUPRef); + DDL_TMR_DisableDMAReq_UPDATE(motor->timerHardware->tim); + break; + } #endif - { xDDL_EX_DMA_DisableResource(motor->dmaRef); DDL_EX_TMR_DisableIT(motor->timerHardware->tim, motor->timerDmaSource); - } + } while (false); #ifdef USE_DSHOT_TELEMETRY if (useDshotTelemetry) { @@ -228,21 +230,22 @@ bool pwmDshotMotorHardwareConfig(const timerHardware_t *timerHardware, uint8_t m dmaIdentifier_e dmaIdentifier = dmaGetIdentifier(dmaRef); bool dmaIsConfigured = false; + do { #ifdef USE_DSHOT_DMAR - if (useBurstDshot) { - const resourceOwner_t *owner = dmaGetOwner(dmaIdentifier); - if (owner->owner == OWNER_TIMUP && owner->resourceIndex == timerGetTIMNumber(timerHardware->tim)) { - dmaIsConfigured = true; - } else if (!dmaAllocate(dmaIdentifier, OWNER_TIMUP, timerGetTIMNumber(timerHardware->tim))) { - return false; + if (useBurstDshot) { + const resourceOwner_t *owner = dmaGetOwner(dmaIdentifier); + if (owner->owner == OWNER_TIMUP && owner->resourceIndex == timerGetTIMNumber(timerHardware->tim)) { + dmaIsConfigured = true; + } else if (!dmaAllocate(dmaIdentifier, OWNER_TIMUP, timerGetTIMNumber(timerHardware->tim))) { + return false; + } + break; } - } else #endif - { if (!dmaAllocate(dmaIdentifier, OWNER_MOTOR, RESOURCE_INDEX(reorderedMotorIndex))) { return false; } - } + } while (false); motorDmaOutput_t * const motor = &dmaMotors[motorIndex]; motor->dmaRef = dmaRef; @@ -312,18 +315,19 @@ bool pwmDshotMotorHardwareConfig(const timerHardware_t *timerHardware, uint8_t m } motor->llChannel = channel; + do { #ifdef USE_DSHOT_DMAR - if (useBurstDshot) { - motor->timer->dmaBurstRef = dmaRef; + if (useBurstDshot) { + motor->timer->dmaBurstRef = dmaRef; #ifdef USE_DSHOT_TELEMETRY - motor->dmaRef = dmaRef; + motor->dmaRef = dmaRef; #endif - } else + break; + } #endif - { motor->timerDmaSource = timerDmaSource(timerHardware->channel); motor->timer->timerDmaSources &= ~motor->timerDmaSource; - } + } while (false); if (!dmaIsConfigured) { xDDL_EX_DMA_DisableResource(dmaRef); @@ -333,24 +337,25 @@ bool pwmDshotMotorHardwareConfig(const timerHardware_t *timerHardware, uint8_t m } DDL_DMA_StructInit(&DMAINIT); + do { #ifdef USE_DSHOT_DMAR - if (useBurstDshot) { - motor->timer->dmaBurstBuffer = &dshotBurstDmaBuffer[timerIndex][0]; + if (useBurstDshot) { + motor->timer->dmaBurstBuffer = &dshotBurstDmaBuffer[timerIndex][0]; - DMAINIT.Channel = dmaChannel; - DMAINIT.MemoryOrM2MDstAddress = (uint32_t)motor->timer->dmaBurstBuffer; - DMAINIT.FIFOThreshold = DDL_DMA_FIFOTHRESHOLD_FULL; - DMAINIT.PeriphOrM2MSrcAddress = (uint32_t)&timerHardware->tim->DMAR; - } else + DMAINIT.Channel = dmaChannel; + DMAINIT.MemoryOrM2MDstAddress = (uint32_t)motor->timer->dmaBurstBuffer; + DMAINIT.FIFOThreshold = DDL_DMA_FIFOTHRESHOLD_FULL; + DMAINIT.PeriphOrM2MSrcAddress = (uint32_t)&timerHardware->tim->DMAR; + break; + } #endif - { motor->dmaBuffer = &dshotDmaBuffer[motorIndex][0]; DMAINIT.Channel = dmaChannel; DMAINIT.MemoryOrM2MDstAddress = (uint32_t)motor->dmaBuffer; DMAINIT.FIFOThreshold = DDL_DMA_FIFOTHRESHOLD_1_4; DMAINIT.PeriphOrM2MSrcAddress = (uint32_t)timerChCCR(timerHardware); - } + } while (false); DMAINIT.Direction = DDL_DMA_DIRECTION_MEMORY_TO_PERIPH; DMAINIT.FIFOMode = DDL_DMA_FIFOMODE_ENABLE; @@ -380,16 +385,17 @@ bool pwmDshotMotorHardwareConfig(const timerHardware_t *timerHardware, uint8_t m pwmDshotSetDirectionOutput(motor, &OCINIT, &DMAINIT); #endif + do { #ifdef USE_DSHOT_DMAR - if (useBurstDshot) { - if (!dmaIsConfigured) { - dmaSetHandler(dmaIdentifier, motor_DMA_IRQHandler, NVIC_PRIO_DSHOT_DMA, motor->index); + if (useBurstDshot) { + if (!dmaIsConfigured) { + dmaSetHandler(dmaIdentifier, motor_DMA_IRQHandler, NVIC_PRIO_DSHOT_DMA, motor->index); + } + break; } - } else #endif - { dmaSetHandler(dmaIdentifier, motor_DMA_IRQHandler, NVIC_PRIO_DSHOT_DMA, motor->index); - } + } while (false); DDL_TMR_OC_Init(timer, channel, &OCINIT); DDL_TMR_OC_EnablePreload(timer, channel); diff --git a/src/platform/APM32/serial_uart_apm32.c b/src/platform/APM32/serial_uart_apm32.c index eb6da0f291..64ac4a3da3 100644 --- a/src/platform/APM32/serial_uart_apm32.c +++ b/src/platform/APM32/serial_uart_apm32.c @@ -82,35 +82,37 @@ void uartReconfigure(uartPort_t *uartPort) // Receive DMA or IRQ if (uartPort->port.mode & MODE_RX) { + do { #ifdef USE_DMA - if (uartPort->rxDMAResource) { - uartPort->rxDMAHandle.Instance = (DMA_ARCH_TYPE *)uartPort->rxDMAResource; - uartPort->txDMAHandle.Init.Channel = uartPort->rxDMAChannel; - uartPort->rxDMAHandle.Init.Direction = DMA_PERIPH_TO_MEMORY; - uartPort->rxDMAHandle.Init.PeriphInc = DMA_PINC_DISABLE; - uartPort->rxDMAHandle.Init.MemInc = DMA_MINC_ENABLE; - uartPort->rxDMAHandle.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; - uartPort->rxDMAHandle.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; - uartPort->rxDMAHandle.Init.Mode = DMA_CIRCULAR; + if (uartPort->rxDMAResource) { + uartPort->rxDMAHandle.Instance = (DMA_ARCH_TYPE *)uartPort->rxDMAResource; + uartPort->txDMAHandle.Init.Channel = uartPort->rxDMAChannel; + uartPort->rxDMAHandle.Init.Direction = DMA_PERIPH_TO_MEMORY; + uartPort->rxDMAHandle.Init.PeriphInc = DMA_PINC_DISABLE; + uartPort->rxDMAHandle.Init.MemInc = DMA_MINC_ENABLE; + uartPort->rxDMAHandle.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; + uartPort->rxDMAHandle.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; + uartPort->rxDMAHandle.Init.Mode = DMA_CIRCULAR; #if defined(APM32F4) - uartPort->rxDMAHandle.Init.FIFOMode = DMA_FIFOMODE_DISABLE; - uartPort->rxDMAHandle.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_1QUARTERFULL; - uartPort->rxDMAHandle.Init.PeriphBurst = DMA_PBURST_SINGLE; - uartPort->rxDMAHandle.Init.MemBurst = DMA_MBURST_SINGLE; + uartPort->rxDMAHandle.Init.FIFOMode = DMA_FIFOMODE_DISABLE; + uartPort->rxDMAHandle.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_1QUARTERFULL; + uartPort->rxDMAHandle.Init.PeriphBurst = DMA_PBURST_SINGLE; + uartPort->rxDMAHandle.Init.MemBurst = DMA_MBURST_SINGLE; #endif - uartPort->rxDMAHandle.Init.Priority = DMA_PRIORITY_MEDIUM; + uartPort->rxDMAHandle.Init.Priority = DMA_PRIORITY_MEDIUM; - DAL_DMA_DeInit(&uartPort->rxDMAHandle); - DAL_DMA_Init(&uartPort->rxDMAHandle); - /* Associate the initialized DMA handle to the UART handle */ - __DAL_LINKDMA(&uartPort->Handle, hdmarx, uartPort->rxDMAHandle); + DAL_DMA_DeInit(&uartPort->rxDMAHandle); + DAL_DMA_Init(&uartPort->rxDMAHandle); + /* Associate the initialized DMA handle to the UART handle */ + __DAL_LINKDMA(&uartPort->Handle, hdmarx, uartPort->rxDMAHandle); - DAL_UART_Receive_DMA(&uartPort->Handle, (uint8_t*)uartPort->port.rxBuffer, uartPort->port.rxBufferSize); + DAL_UART_Receive_DMA(&uartPort->Handle, (uint8_t*)uartPort->port.rxBuffer, uartPort->port.rxBufferSize); - uartPort->rxDMAPos = __DAL_DMA_GET_COUNTER(&uartPort->rxDMAHandle); - } else + uartPort->rxDMAPos = __DAL_DMA_GET_COUNTER(&uartPort->rxDMAHandle); + break; + } #endif - { + /* Enable the UART Parity Error Interrupt */ SET_BIT(uartPort->USARTx->CTRL1, USART_CTRL1_PEIEN); @@ -122,44 +124,44 @@ void uartReconfigure(uartPort_t *uartPort) /* Enable Idle Line detection */ SET_BIT(uartPort->USARTx->CTRL1, USART_CTRL1_IDLEIEN); - } + } while(false); } // Transmit DMA or IRQ if (uartPort->port.mode & MODE_TX) { + do { #ifdef USE_DMA - if (uartPort->txDMAResource) { - uartPort->txDMAHandle.Instance = (DMA_ARCH_TYPE *)uartPort->txDMAResource; - uartPort->txDMAHandle.Init.Channel = uartPort->txDMAChannel; - uartPort->txDMAHandle.Init.Direction = DMA_MEMORY_TO_PERIPH; - uartPort->txDMAHandle.Init.PeriphInc = DMA_PINC_DISABLE; - uartPort->txDMAHandle.Init.MemInc = DMA_MINC_ENABLE; - uartPort->txDMAHandle.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; - uartPort->txDMAHandle.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; - uartPort->txDMAHandle.Init.Mode = DMA_NORMAL; - uartPort->txDMAHandle.Init.FIFOMode = DMA_FIFOMODE_DISABLE; - uartPort->txDMAHandle.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_1QUARTERFULL; - uartPort->txDMAHandle.Init.PeriphBurst = DMA_PBURST_SINGLE; - uartPort->txDMAHandle.Init.MemBurst = DMA_MBURST_SINGLE; - uartPort->txDMAHandle.Init.Priority = DMA_PRIORITY_MEDIUM; + if (uartPort->txDMAResource) { + uartPort->txDMAHandle.Instance = (DMA_ARCH_TYPE *)uartPort->txDMAResource; + uartPort->txDMAHandle.Init.Channel = uartPort->txDMAChannel; + uartPort->txDMAHandle.Init.Direction = DMA_MEMORY_TO_PERIPH; + uartPort->txDMAHandle.Init.PeriphInc = DMA_PINC_DISABLE; + uartPort->txDMAHandle.Init.MemInc = DMA_MINC_ENABLE; + uartPort->txDMAHandle.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; + uartPort->txDMAHandle.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; + uartPort->txDMAHandle.Init.Mode = DMA_NORMAL; + uartPort->txDMAHandle.Init.FIFOMode = DMA_FIFOMODE_DISABLE; + uartPort->txDMAHandle.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_1QUARTERFULL; + uartPort->txDMAHandle.Init.PeriphBurst = DMA_PBURST_SINGLE; + uartPort->txDMAHandle.Init.MemBurst = DMA_MBURST_SINGLE; + uartPort->txDMAHandle.Init.Priority = DMA_PRIORITY_MEDIUM; - DAL_DMA_DeInit(&uartPort->txDMAHandle); - DAL_StatusTypeDef status = DAL_DMA_Init(&uartPort->txDMAHandle); - if (status != DAL_OK) { - while (1); + DAL_DMA_DeInit(&uartPort->txDMAHandle); + DAL_StatusTypeDef status = DAL_DMA_Init(&uartPort->txDMAHandle); + if (status != DAL_OK) { + while (1); + } + /* Associate the initialized DMA handle to the UART handle */ + __DAL_LINKDMA(&uartPort->Handle, hdmatx, uartPort->txDMAHandle); + + __DAL_DMA_SET_COUNTER(&uartPort->txDMAHandle, 0); + break; } - /* Associate the initialized DMA handle to the UART handle */ - __DAL_LINKDMA(&uartPort->Handle, hdmatx, uartPort->txDMAHandle); - - __DAL_DMA_SET_COUNTER(&uartPort->txDMAHandle, 0); - } else #endif - { - /* Enable the UART Transmit Data Register Empty Interrupt */ SET_BIT(uartPort->USARTx->CTRL1, USART_CTRL1_TXBEIEN); SET_BIT(uartPort->USARTx->CTRL1, USART_CTRL1_TXCIEN); - } + } while(false); } } diff --git a/src/platform/APM32/serial_uart_apm32f4xx.c b/src/platform/APM32/serial_uart_apm32f4xx.c index 7978e6315e..2df52a9ffd 100644 --- a/src/platform/APM32/serial_uart_apm32f4xx.c +++ b/src/platform/APM32/serial_uart_apm32f4xx.c @@ -269,10 +269,12 @@ void uartDmaIrqHandler(dmaChannelDescriptor_t* descriptor) } handleUsartTxDma(s); } + if (DMA_GET_FLAG_STATUS(descriptor, DMA_IT_TEIF)) { DMA_CLEAR_FLAG(descriptor, DMA_IT_TEIF); } + if (DMA_GET_FLAG_STATUS(descriptor, DMA_IT_DMEIF)) { DMA_CLEAR_FLAG(descriptor, DMA_IT_DMEIF); diff --git a/src/platform/APM32/system_apm32f4xx.c b/src/platform/APM32/system_apm32f4xx.c index 0bf5b42231..75945bd924 100644 --- a/src/platform/APM32/system_apm32f4xx.c +++ b/src/platform/APM32/system_apm32f4xx.c @@ -121,10 +121,11 @@ void enableGPIOPowerUsageAndNoiseReductions(void) bool isMPUSoftReset(void) { - if (cachedRccCsrValue & RCM_CSTS_SWRSTFLG) + if (cachedRccCsrValue & RCM_CSTS_SWRSTFLG) { return true; - else + } else { return false; + } } void systemInit(void) diff --git a/src/platform/APM32/timer_apm32.c b/src/platform/APM32/timer_apm32.c index 5e52ec654c..710ebc509a 100644 --- a/src/platform/APM32/timer_apm32.c +++ b/src/platform/APM32/timer_apm32.c @@ -340,7 +340,9 @@ TMR_HandleTypeDef* timerFindTimerHandle(TMR_TypeDef *tim) void timerReconfigureTimeBase(TMR_TypeDef *tim, uint16_t period, uint32_t hz) { TMR_HandleTypeDef* handle = timerFindTimerHandle(tim); - if (handle == NULL) return; + if (handle == NULL) { + return; + } handle->Init.Period = (period - 1) & 0xffff; // AKA TIMx_ARR handle->Init.Prescaler = (timerClock(tim) / hz) - 1; @@ -351,7 +353,9 @@ void timerReconfigureTimeBase(TMR_TypeDef *tim, uint16_t period, uint32_t hz) void configTimeBase(TMR_TypeDef *tim, uint16_t period, uint32_t hz) { TMR_HandleTypeDef* handle = timerFindTimerHandle(tim); - if (handle == NULL) return; + if (handle == NULL) { + return; + } if (handle->Instance == tim) { // already configured @@ -368,8 +372,7 @@ void configTimeBase(TMR_TypeDef *tim, uint16_t period, uint32_t hz) handle->Init.RepetitionCounter = 0x0000; DAL_TMR_Base_Init(handle); - if (tim == TMR1 || tim == TMR2 || tim == TMR3 || tim == TMR4 || tim == TMR5 || tim == TMR8 || tim == TMR9) - { + if (tim == TMR1 || tim == TMR2 || tim == TMR3 || tim == TMR4 || tim == TMR5 || tim == TMR8 || tim == TMR9) { TMR_ClockConfigTypeDef sClockSourceConfig; memset(&sClockSourceConfig, 0, sizeof(sClockSourceConfig)); sClockSourceConfig.ClockSource = TMR_CLOCKSOURCE_INTERNAL; @@ -402,7 +405,6 @@ void timerConfigure(const timerHardware_t *timerHardwarePtr, uint16_t period, ui timerNVICConfigure(irq); // HACK - enable second IRQ on timers that need it switch (irq) { - case TMR1_CC_IRQn: timerNVICConfigure(TMR1_UP_TMR10_IRQn); break; @@ -421,13 +423,16 @@ void timerChInit(const timerHardware_t *timHw, channelType_t type, int irqPriori return; } unsigned channel = timHw - TIMER_HARDWARE; - if (channel >= TIMER_CHANNEL_COUNT) + if (channel >= TIMER_CHANNEL_COUNT) { return; + } timerChannelInfo[channel].type = type; unsigned timer = lookupTimerIndex(timHw->tim); - if (timer >= USED_TIMER_COUNT) + if (timer >= USED_TIMER_COUNT) { return; + } + if (irqPriority < timerInfo[timer].priority) { // it would be better to set priority in the end, but current startup sequence is not ready configTimeBase(usedTimers[timer], 0, 1); @@ -476,10 +481,11 @@ static void timerChConfig_UpdateOverflow(timerConfig_t *cfg, const TMR_TypeDef * *chain = NULL; } // enable or disable IRQ - if (cfg->overflowCallbackActive) + if (cfg->overflowCallbackActive) { __DAL_TMR_ENABLE_IT(&timerHandle[timerIndex].Handle, TMR_IT_UPDATE); - else + } else { __DAL_TMR_DISABLE_IT(&timerHandle[timerIndex].Handle, TMR_IT_UPDATE); + } } // config edge and overflow callback for channel. Try to avoid overflowCallback, it is a bit expensive @@ -490,14 +496,17 @@ void timerChConfigCallbacks(const timerHardware_t *timHw, timerCCHandlerRec_t *e return; } uint8_t channelIndex = lookupChannelIndex(timHw->channel); - if (edgeCallback == NULL) // disable irq before changing callback to NULL + if (edgeCallback == NULL) { // disable irq before changing callback to NULL __DAL_TMR_DISABLE_IT(&timerHandle[timerIndex].Handle, TIM_IT_CCx(timHw->channel)); + } + // setup callback info timerConfig[timerIndex].edgeCallback[channelIndex] = edgeCallback; timerConfig[timerIndex].overflowCallback[channelIndex] = overflowCallback; // enable channel IRQ - if (edgeCallback) + if (edgeCallback) { __DAL_TMR_ENABLE_IT(&timerHandle[timerIndex].Handle, TIM_IT_CCx(timHw->channel)); + } timerChConfig_UpdateOverflow(&timerConfig[timerIndex], timHw->tim); } @@ -525,10 +534,13 @@ void timerChConfigCallbacksDual(const timerHardware_t *timHw, timerCCHandlerRec_ uint16_t chHi = timHw->channel | TMR_CHANNEL_2; // upper channel uint8_t channelIndex = lookupChannelIndex(chLo); // get index of lower channel - if (edgeCallbackLo == NULL) // disable irq before changing setting callback to NULL + if (edgeCallbackLo == NULL) { // disable irq before changing setting callback to NULL __DAL_TMR_DISABLE_IT(&timerHandle[timerIndex].Handle, TIM_IT_CCx(chLo)); - if (edgeCallbackHi == NULL) // disable irq before changing setting callback to NULL + } + + if (edgeCallbackHi == NULL) { // disable irq before changing setting callback to NULL __DAL_TMR_DISABLE_IT(&timerHandle[timerIndex].Handle, TIM_IT_CCx(chHi)); + } // setup callback info timerConfig[timerIndex].edgeCallback[channelIndex] = edgeCallbackLo; @@ -541,6 +553,7 @@ void timerChConfigCallbacksDual(const timerHardware_t *timHw, timerCCHandlerRec_ __DAL_TMR_CLEAR_FLAG(&timerHandle[timerIndex].Handle, TIM_IT_CCx(chLo)); __DAL_TMR_ENABLE_IT(&timerHandle[timerIndex].Handle, TIM_IT_CCx(chLo)); } + if (edgeCallbackHi) { __DAL_TMR_CLEAR_FLAG(&timerHandle[timerIndex].Handle, TIM_IT_CCx(chHi)); __DAL_TMR_ENABLE_IT(&timerHandle[timerIndex].Handle, TIM_IT_CCx(chHi)); @@ -561,10 +574,11 @@ void timerChITConfigDualLo(const timerHardware_t *timHw, FunctionalState newStat return; } - if (newState) + if (newState) { __DAL_TMR_ENABLE_IT(&timerHandle[timerIndex].Handle, TIM_IT_CCx(timHw->channel & ~TMR_CHANNEL_2)); - else + } else { __DAL_TMR_DISABLE_IT(&timerHandle[timerIndex].Handle, TIM_IT_CCx(timHw->channel & ~TMR_CHANNEL_2)); + } } //// enable or disable IRQ @@ -580,10 +594,11 @@ void timerChITConfig(const timerHardware_t *timHw, FunctionalState newState) return; } - if (newState) + if (newState) { __DAL_TMR_ENABLE_IT(&timerHandle[timerIndex].Handle, TIM_IT_CCx(timHw->channel)); - else + } else { __DAL_TMR_DISABLE_IT(&timerHandle[timerIndex].Handle, TIM_IT_CCx(timHw->channel)); + } } // clear Compare/Capture flag for channel @@ -623,9 +638,11 @@ static unsigned getFilter(unsigned ticks) 16*5, 16*6, 16*8, 32*5, 32*6, 32*8 }; - for (unsigned i = 1; i < ARRAYLEN(ftab); i++) - if (ftab[i] > ticks) + for (unsigned i = 1; i < ARRAYLEN(ftab); i++) { + if (ftab[i] > ticks) { return i - 1; + } + } return 0x0f; } @@ -633,8 +650,9 @@ static unsigned getFilter(unsigned ticks) void timerChConfigIC(const timerHardware_t *timHw, bool polarityRising, unsigned inputFilterTicks) { unsigned timer = lookupTimerIndex(timHw->tim); - if (timer >= USED_TIMER_COUNT) + if (timer >= USED_TIMER_COUNT) { return; + } TMR_IC_InitTypeDef TIM_ICInitStructure; @@ -650,8 +668,9 @@ void timerChConfigIC(const timerHardware_t *timHw, bool polarityRising, unsigned void timerChConfigICDual(const timerHardware_t *timHw, bool polarityRising, unsigned inputFilterTicks) { unsigned timer = lookupTimerIndex(timHw->tim); - if (timer >= USED_TIMER_COUNT) + if (timer >= USED_TIMER_COUNT) { return; + } TMR_IC_InitTypeDef TIM_ICInitStructure; bool directRising = (timHw->channel & TMR_CHANNEL_2) ? !polarityRising : polarityRising; @@ -695,8 +714,9 @@ volatile timCCR_t* timerChCCR(const timerHardware_t *timHw) void timerChConfigOC(const timerHardware_t* timHw, bool outEnable, bool stateHigh) { unsigned timer = lookupTimerIndex(timHw->tim); - if (timer >= USED_TIMER_COUNT) + if (timer >= USED_TIMER_COUNT) { return; + } TMR_OC_InitTypeDef TIM_OCInitStructure; @@ -1000,7 +1020,9 @@ void timerInit(void) void timerStart(TMR_TypeDef *tim) { TMR_HandleTypeDef* handle = timerFindTimerHandle(tim); - if (handle == NULL) return; + if (handle == NULL) { + return; + } __DAL_TMR_ENABLE(handle); } @@ -1135,13 +1157,16 @@ DAL_StatusTypeDef DMA_SetCurrDataCounter(TMR_HandleTypeDef *htim, uint32_t Chann { if ((htim->State == DAL_TMR_STATE_BUSY)) { return DAL_BUSY; - } else if ((htim->State == DAL_TMR_STATE_READY)) { - if (((uint32_t) pData == 0) && (Length > 0)) { - return DAL_ERROR; - } else { - htim->State = DAL_TMR_STATE_BUSY; + } else { + if ((htim->State == DAL_TMR_STATE_READY)) { + if (((uint32_t) pData == 0) && (Length > 0)) { + return DAL_ERROR; + } else { + htim->State = DAL_TMR_STATE_BUSY; + } } } + switch (Channel) { case TMR_CHANNEL_1: { /* Set the DMA Period elapsed callback */ diff --git a/src/platform/APM32/transponder_ir_io_apm32.c b/src/platform/APM32/transponder_ir_io_apm32.c index ff4d778736..29a6786a80 100644 --- a/src/platform/APM32/transponder_ir_io_apm32.c +++ b/src/platform/APM32/transponder_ir_io_apm32.c @@ -165,6 +165,7 @@ void transponderIrHardwareInit(ioTag_t ioTag, transponder_t *transponder) /* Configuration Error */ return; } + if (timerHardware->output & TIMER_OUTPUT_N_CHANNEL) { if (DAL_TMREx_PWMN_Start(&TmrHandle, timerChannel) != DAL_OK) { /* Starting PWM generation Error */ From ec91238cd80061b37d35a258457eb75052641a72 Mon Sep 17 00:00:00 2001 From: Mark Haslinghuis Date: Wed, 11 Jun 2025 01:47:01 +0200 Subject: [PATCH 238/244] Add support for IIM42652 (#14424) --- src/main/cli/settings.c | 2 ++ src/main/drivers/accgyro/accgyro.h | 1 + src/main/drivers/accgyro/accgyro_mpu.h | 2 ++ src/main/drivers/accgyro/accgyro_spi_icm426xx.c | 13 ++++++++++--- src/main/sensors/acceleration.h | 1 + src/main/sensors/acceleration_init.c | 6 +++++- src/main/sensors/gyro_init.c | 7 ++++++- src/main/target/common_post.h | 14 ++++++++------ src/main/target/common_pre.h | 1 + 9 files changed, 36 insertions(+), 11 deletions(-) diff --git a/src/main/cli/settings.c b/src/main/cli/settings.c index 6fc140f4af..7cbcabfc6b 100644 --- a/src/main/cli/settings.c +++ b/src/main/cli/settings.c @@ -164,6 +164,7 @@ const char * const lookupTableAccHardware[] = { "ICM45605", "ICM45686", "ICM40609D", + "IIM42652", "VIRTUAL" }; @@ -191,6 +192,7 @@ const char * const lookupTableGyroHardware[] = { "ICM45605", "ICM45686", "ICM40609D", + "IIM42652", "VIRTUAL" }; diff --git a/src/main/drivers/accgyro/accgyro.h b/src/main/drivers/accgyro/accgyro.h index e969f92ec4..9a50c6b69b 100644 --- a/src/main/drivers/accgyro/accgyro.h +++ b/src/main/drivers/accgyro/accgyro.h @@ -65,6 +65,7 @@ typedef enum { GYRO_ICM45605, GYRO_ICM45686, GYRO_ICM40609D, + GYRO_IIM42652, GYRO_VIRTUAL } gyroHardware_e; diff --git a/src/main/drivers/accgyro/accgyro_mpu.h b/src/main/drivers/accgyro/accgyro_mpu.h index 20104d7fe2..b3e4fe7ef2 100644 --- a/src/main/drivers/accgyro/accgyro_mpu.h +++ b/src/main/drivers/accgyro/accgyro_mpu.h @@ -47,6 +47,7 @@ #define ICM42688P_WHO_AM_I_CONST (0x47) #define ICM45686_WHO_AM_I_CONST (0xE9) #define ICM45605_WHO_AM_I_CONST (0xE5) +#define IIM42652_WHO_AM_I_CONST (0x6F) #define IIM42653_WHO_AM_I_CONST (0x56) #define LSM6DSV16X_WHO_AM_I_CONST (0x70) #define ICM40609_WHO_AM_I_CONST (0x3B) @@ -207,6 +208,7 @@ typedef enum { ICM_20689_SPI, ICM_42605_SPI, ICM_42688P_SPI, + IIM_42652_SPI, IIM_42653_SPI, BMI_160_SPI, BMI_270_SPI, diff --git a/src/main/drivers/accgyro/accgyro_spi_icm426xx.c b/src/main/drivers/accgyro/accgyro_spi_icm426xx.c index b323d2211d..afdc21e2fa 100644 --- a/src/main/drivers/accgyro/accgyro_spi_icm426xx.c +++ b/src/main/drivers/accgyro/accgyro_spi_icm426xx.c @@ -28,7 +28,7 @@ #include "platform.h" -#if defined(USE_GYRO_SPI_ICM42605) || defined(USE_GYRO_SPI_ICM42688P) || defined(USE_ACCGYRO_IIM42653) +#if defined(USE_GYRO_SPI_ICM42605) || defined(USE_GYRO_SPI_ICM42688P) || defined(USE_ACCGYRO_IIM42652) || defined(USE_ACCGYRO_IIM42653) #include "common/axis.h" #include "common/utils.h" @@ -284,6 +284,9 @@ uint8_t icm426xxSpiDetect(const extDevice_t *dev) case ICM42688P_WHO_AM_I_CONST: icmDetected = ICM_42688P_SPI; break; + case IIM42652_WHO_AM_I_CONST: + icmDetected = IIM_42652_SPI; + break; case IIM42653_WHO_AM_I_CONST: icmDetected = IIM_42653_SPI; break; @@ -306,6 +309,7 @@ void icm426xxAccInit(accDev_t *acc) { switch (acc->mpuDetectionResult.sensor) { case IIM_42653_SPI: + case IIM_42652_SPI: acc->acc_1G = 512 * 2; // Accel scale 32g (1024 LSB/g) break; default: @@ -319,6 +323,7 @@ bool icm426xxSpiAccDetect(accDev_t *acc) switch (acc->mpuDetectionResult.sensor) { case ICM_42605_SPI: case ICM_42688P_SPI: + case IIM_42652_SPI: case IIM_42653_SPI: break; default: @@ -427,6 +432,7 @@ bool icm426xxSpiGyroDetect(gyroDev_t *gyro) case ICM_42688P_SPI: gyro->scale = GYRO_SCALE_2000DPS; break; + case IIM_42652_SPI: case IIM_42653_SPI: gyro->scale = GYRO_SCALE_4000DPS; break; @@ -444,6 +450,8 @@ static aafConfig_t getGyroAafConfig(const mpuSensor_e gyroModel, const aafConfig { switch (gyroModel){ case ICM_42605_SPI: + case IIM_42652_SPI: + case IIM_42653_SPI: switch (config) { case GYRO_HARDWARE_LPF_NORMAL: return aafLUT42605[AAF_CONFIG_258HZ]; @@ -456,7 +464,6 @@ static aafConfig_t getGyroAafConfig(const mpuSensor_e gyroModel, const aafConfig } case ICM_42688P_SPI: - case IIM_42653_SPI: default: switch (config) { case GYRO_HARDWARE_LPF_NORMAL: @@ -475,4 +482,4 @@ static aafConfig_t getGyroAafConfig(const mpuSensor_e gyroModel, const aafConfig } } -#endif // USE_GYRO_SPI_ICM42605 || USE_GYRO_SPI_ICM42688P || USE_ACCGYRO_IIM42653 +#endif // USE_GYRO_SPI_ICM42605 || USE_GYRO_SPI_ICM42688P || USE_ACCGYRO_IIM42652 || USE_ACCGYRO_IIM42653 diff --git a/src/main/sensors/acceleration.h b/src/main/sensors/acceleration.h index bb75d5cc61..9464544642 100644 --- a/src/main/sensors/acceleration.h +++ b/src/main/sensors/acceleration.h @@ -54,6 +54,7 @@ typedef enum { ACC_ICM45605, ACC_ICM45686, ACC_ICM40609D, + ACC_IIM42652, ACC_VIRTUAL } accelerationSensor_e; diff --git a/src/main/sensors/acceleration_init.c b/src/main/sensors/acceleration_init.c index 93426607ba..46a9943379 100644 --- a/src/main/sensors/acceleration_init.c +++ b/src/main/sensors/acceleration_init.c @@ -218,9 +218,10 @@ retry: FALLTHROUGH; #endif -#if defined(USE_ACC_SPI_ICM42605) || defined(USE_ACC_SPI_ICM42688P) || defined(USE_ACCGYRO_IIM42653) +#if defined(USE_ACC_SPI_ICM42605) || defined(USE_ACC_SPI_ICM42688P) || defined(USE_ACCGYRO_IIM42652) || defined(USE_ACCGYRO_IIM42653) case ACC_ICM42605: case ACC_ICM42688P: + case ACC_IIM42652: case ACC_IIM42653: if (icm426xxSpiAccDetect(dev)) { switch (dev->mpuDetectionResult.sensor) { @@ -230,6 +231,9 @@ retry: case ICM_42688P_SPI: accHardware = ACC_ICM42688P; break; + case IIM_42652_SPI: + accHardware = ACC_IIM42652; + break; case IIM_42653_SPI: accHardware = ACC_IIM42653; break; diff --git a/src/main/sensors/gyro_init.c b/src/main/sensors/gyro_init.c index 5afb37e5e9..7a2de5f353 100644 --- a/src/main/sensors/gyro_init.c +++ b/src/main/sensors/gyro_init.c @@ -318,6 +318,7 @@ void gyroInitSensor(gyroSensor_t *gyroSensor, const gyroDeviceConfig_t *config) case GYRO_LSM6DSO: case GYRO_LSM6DSV16X: case GYRO_ICM42688P: + case GYRO_IIM42652: case GYRO_IIM42653: case GYRO_ICM42605: case GYRO_ICM45686: @@ -434,9 +435,10 @@ STATIC_UNIT_TESTED gyroHardware_e gyroDetect(gyroDev_t *dev) FALLTHROUGH; #endif -#if defined(USE_GYRO_SPI_ICM42605) || defined(USE_GYRO_SPI_ICM42688P) || defined(USE_ACCGYRO_IIM42653) +#if defined(USE_GYRO_SPI_ICM42605) || defined(USE_GYRO_SPI_ICM42688P) || defined(USE_ACCGYRO_IIM42652) || defined(USE_ACCGYRO_IIM42653) case GYRO_ICM42605: case GYRO_ICM42688P: + case GYRO_IIM42652: case GYRO_IIM42653: if (icm426xxSpiGyroDetect(dev)) { switch (dev->mpuDetectionResult.sensor) { @@ -446,6 +448,9 @@ STATIC_UNIT_TESTED gyroHardware_e gyroDetect(gyroDev_t *dev) case ICM_42688P_SPI: gyroHardware = GYRO_ICM42688P; break; + case IIM_42652_SPI: + gyroHardware = GYRO_IIM42652; + break; case IIM_42653_SPI: gyroHardware = GYRO_IIM42653; break; diff --git a/src/main/target/common_post.h b/src/main/target/common_post.h index b4ff315959..b406583886 100644 --- a/src/main/target/common_post.h +++ b/src/main/target/common_post.h @@ -110,8 +110,9 @@ && !defined(USE_ACC_SPI_MPU6000) \ && !defined(USE_ACC_SPI_MPU6500) \ && !defined(USE_ACC_SPI_MPU9250) \ - && !defined(USE_VIRTUAL_ACC) \ - && !defined(USE_ACCGYRO_IIM42653) + && !defined(USE_ACCGYRO_IIM42652) \ + && !defined(USE_ACCGYRO_IIM42653) \ + && !defined(USE_VIRTUAL_ACC) #error At least one USE_ACC device definition required #endif @@ -133,8 +134,9 @@ && !defined(USE_GYRO_SPI_MPU6000) \ && !defined(USE_GYRO_SPI_MPU6500) \ && !defined(USE_GYRO_SPI_MPU9250) \ - && !defined(USE_VIRTUAL_GYRO) \ - && !defined(USE_ACCGYRO_IIM42653) + && !defined(USE_ACCGYRO_IIM42652) \ + && !defined(USE_ACCGYRO_IIM42653) \ + && !defined(USE_VIRTUAL_GYRO) #error At least one USE_GYRO device definition required #endif @@ -472,11 +474,11 @@ #define USE_GYRO_SPI_MPU6500 #endif -// Generate USE_SPI_GYRO or USE_I2C_GYRO +// Generate USE_SPI_GYRO #if defined(USE_GYRO_SPI_ICM20689) || defined(USE_GYRO_SPI_MPU6000) || defined(USE_GYRO_SPI_MPU6500) || defined(USE_GYRO_SPI_MPU9250) \ || defined(USE_GYRO_L3GD20) || defined(USE_GYRO_SPI_ICM42605) || defined(USE_GYRO_SPI_ICM42688P) || defined(USE_ACCGYRO_ICM45686) \ || defined(USE_ACCGYRO_ICM45605) || defined(USE_ACCGYRO_IIM42653) || defined(USE_ACCGYRO_BMI160) || defined(USE_ACCGYRO_BMI270) \ - || defined(USE_ACCGYRO_LSM6DSV16X) || defined(USE_ACCGYRO_LSM6DSO) || defined(USE_ACCGYRO_ICM40609D) + || defined(USE_ACCGYRO_LSM6DSV16X) || defined(USE_ACCGYRO_LSM6DSO) || defined(USE_ACCGYRO_ICM40609D) || defined(USE_ACCGYRO_IIM42652) #ifndef USE_SPI_GYRO #define USE_SPI_GYRO #endif diff --git a/src/main/target/common_pre.h b/src/main/target/common_pre.h index 326c7fd5ee..ed96a9f48f 100644 --- a/src/main/target/common_pre.h +++ b/src/main/target/common_pre.h @@ -116,6 +116,7 @@ #define USE_GYRO_SPI_ICM42688P #define USE_ACCGYRO_ICM45686 #define USE_ACCGYRO_ICM45605 +#define USE_ACCGYRO_IIM42652 #define USE_ACCGYRO_IIM42653 #define USE_ACC_SPI_ICM42605 #define USE_ACC_SPI_ICM42688P From a03ff788ae43682f3553d7e684832737948072fa Mon Sep 17 00:00:00 2001 From: mjs1441 Date: Wed, 11 Jun 2025 08:10:03 +0100 Subject: [PATCH 239/244] Move bus_i2c_config.c to platform (#14439) * Move bus_i2c_config.c to platform to allow different PICO implementation. * Rename bus_i2c_config.c -> bus_i2c_pinconfig.c and i2cHardwareConfigure() -> i2cPinConfigure() --- src/main/drivers/bus_i2c.h | 2 +- src/main/fc/init.c | 2 +- src/platform/APM32/mk/APM32F4.mk | 4 ++-- src/platform/AT32/mk/AT32F4.mk | 4 ++-- src/platform/STM32/mk/STM32_COMMON.mk | 4 ++-- .../common/stm32/bus_i2c_pinconfig.c} | 2 +- src/test/unit/timer_definition_unittest.include/pg/bus_i2c.h | 2 +- 7 files changed, 10 insertions(+), 10 deletions(-) rename src/{main/drivers/bus_i2c_config.c => platform/common/stm32/bus_i2c_pinconfig.c} (97%) diff --git a/src/main/drivers/bus_i2c.h b/src/main/drivers/bus_i2c.h index 0b34ea2e94..29176a9a7c 100644 --- a/src/main/drivers/bus_i2c.h +++ b/src/main/drivers/bus_i2c.h @@ -51,7 +51,7 @@ typedef enum I2CDevice { #define I2C_ADDR7_MAX 119 struct i2cConfig_s; -void i2cHardwareConfigure(const struct i2cConfig_s *i2cConfig); +void i2cPinConfigure(const struct i2cConfig_s *i2cConfig); void i2cInit(I2CDevice device); bool i2cWriteBuffer(I2CDevice device, uint8_t addr_, uint8_t reg_, uint8_t len_, uint8_t *data); bool i2cWrite(I2CDevice device, uint8_t addr_, uint8_t reg, uint8_t data); diff --git a/src/main/fc/init.c b/src/main/fc/init.c index d48b5d6128..0b22ec9ca0 100644 --- a/src/main/fc/init.c +++ b/src/main/fc/init.c @@ -624,7 +624,7 @@ void init(void) #endif #ifdef USE_I2C - i2cHardwareConfigure(i2cConfig(0)); + i2cPinConfigure(i2cConfig(0)); // Note: Unlike UARTs which are configured when client is present, // I2C buses are initialized unconditionally if they are configured. diff --git a/src/platform/APM32/mk/APM32F4.mk b/src/platform/APM32/mk/APM32F4.mk index c0b9a27c91..8bdb4b6cf7 100644 --- a/src/platform/APM32/mk/APM32F4.mk +++ b/src/platform/APM32/mk/APM32F4.mk @@ -179,8 +179,8 @@ MCU_COMMON_SRC = \ APM32/dma_apm32f4xx.c \ APM32/serial_uart_apm32f4xx.c \ drivers/adc.c \ - drivers/bus_i2c_config.c \ drivers/bus_spi_config.c \ + common/stm32/bus_i2c_pinconfig.c \ common/stm32/bus_spi_hw.c \ common/stm32/bus_spi_pinconfig.c \ common/stm32/serial_uart_hw.c \ @@ -217,8 +217,8 @@ SPEED_OPTIMISED_SRC += \ SIZE_OPTIMISED_SRC += \ APM32/usb/vcp/serial_usb_vcp.c \ drivers/inverter.c \ - drivers/bus_i2c_config.c \ drivers/bus_spi_config.c \ + common/stm32/bus_i2c_pinconfig.c \ common/stm32/bus_spi_pinconfig.c \ drivers/serial_escserial.c \ drivers/serial_pinconfig.c \ diff --git a/src/platform/AT32/mk/AT32F4.mk b/src/platform/AT32/mk/AT32F4.mk index ec377078aa..f78c4671c9 100644 --- a/src/platform/AT32/mk/AT32F4.mk +++ b/src/platform/AT32/mk/AT32F4.mk @@ -121,8 +121,8 @@ MCU_COMMON_SRC = \ drivers/bus_i2c_timing.c \ drivers/usb_msc_common.c \ drivers/adc.c \ - drivers/bus_i2c_config.c \ drivers/bus_spi_config.c \ + common/stm32/bus_i2c_pinconfig.c \ common/stm32/bus_spi_pinconfig.c \ common/stm32/bus_spi_hw.c \ common/stm32/serial_uart_hw.c \ @@ -144,8 +144,8 @@ SPEED_OPTIMISED_SRC += \ SIZE_OPTIMISED_SRC += \ drivers/bus_i2c_timing.c \ drivers/inverter.c \ - drivers/bus_i2c_config.c \ drivers/bus_spi_config.c \ + common/stm32/bus_i2c_pinconfig.c \ common/stm32/bus_spi_pinconfig.c \ drivers/serial_escserial.c \ drivers/serial_pinconfig.c \ diff --git a/src/platform/STM32/mk/STM32_COMMON.mk b/src/platform/STM32/mk/STM32_COMMON.mk index a70deb0de2..f300fd3b32 100644 --- a/src/platform/STM32/mk/STM32_COMMON.mk +++ b/src/platform/STM32/mk/STM32_COMMON.mk @@ -5,8 +5,8 @@ MCU_COMMON_SRC += \ common/stm32/system.c \ common/stm32/config_flash.c \ common/stm32/bus_spi_pinconfig.c \ - drivers/bus_i2c_config.c \ drivers/bus_spi_config.c \ + common/stm32/bus_i2c_pinconfig.c \ common/stm32/bus_spi_hw.c \ common/stm32/io_impl.c \ common/stm32/serial_uart_hw.c \ @@ -16,8 +16,8 @@ MCU_COMMON_SRC += \ common/stm32/dshot_bitbang_shared.c SIZE_OPTIMISED_SRC += \ - drivers/bus_i2c_config.c \ drivers/bus_spi_config.c \ + common/stm32/bus_i2c_pinconfig.c \ common/stm32/config_flash.c \ common/stm32/bus_spi_pinconfig.c diff --git a/src/main/drivers/bus_i2c_config.c b/src/platform/common/stm32/bus_i2c_pinconfig.c similarity index 97% rename from src/main/drivers/bus_i2c_config.c rename to src/platform/common/stm32/bus_i2c_pinconfig.c index 7b27532cbf..dfa1147c7d 100644 --- a/src/main/drivers/bus_i2c_config.c +++ b/src/platform/common/stm32/bus_i2c_pinconfig.c @@ -39,7 +39,7 @@ #include "pg/bus_i2c.h" -void i2cHardwareConfigure(const i2cConfig_t *i2cConfig) +void i2cPinConfigure(const i2cConfig_t *i2cConfig) { for (int index = 0 ; index < I2CDEV_COUNT ; index++) { const i2cHardware_t *hardware = &i2cHardware[index]; diff --git a/src/test/unit/timer_definition_unittest.include/pg/bus_i2c.h b/src/test/unit/timer_definition_unittest.include/pg/bus_i2c.h index b822be69bf..954add5c7d 100644 --- a/src/test/unit/timer_definition_unittest.include/pg/bus_i2c.h +++ b/src/test/unit/timer_definition_unittest.include/pg/bus_i2c.h @@ -1,5 +1,5 @@ #define I2CDEV_2 (1) int i2cConfig(int); -void i2cHardwareConfigure(int); +void i2cPinConfigure(int); void i2cInit(int); From 4769c2fcdf44cbf54edf6df0c54ae8755ff252b1 Mon Sep 17 00:00:00 2001 From: Jay Blackman Date: Wed, 11 Jun 2025 17:10:44 +1000 Subject: [PATCH 240/244] PICO: Adding RP2350A MCU (#14437) - allow for provision of libc - correction for unused function in msp --- src/main/build/build_config.h | 1 + src/main/common/strtol.c | 2 ++ src/main/msp/msp.c | 5 +++-- src/main/target/common_post.h | 4 ++++ 4 files changed, 10 insertions(+), 2 deletions(-) diff --git a/src/main/build/build_config.h b/src/main/build/build_config.h index 4665627e47..22a59c65f3 100644 --- a/src/main/build/build_config.h +++ b/src/main/build/build_config.h @@ -63,6 +63,7 @@ typedef enum { MCU_TYPE_APM32F405, MCU_TYPE_APM32F407, MCU_TYPE_AT32F435M, + MCU_TYPE_RP2350A, MCU_TYPE_RP2350B, MCU_TYPE_COUNT, MCU_TYPE_UNKNOWN = 255, diff --git a/src/main/common/strtol.c b/src/main/common/strtol.c index f94f3fc38d..0739cec593 100644 --- a/src/main/common/strtol.c +++ b/src/main/common/strtol.c @@ -30,6 +30,7 @@ #define _STRTO_ENDPTR 1 +#if PLATFORM_NO_LIBC static unsigned long _strto_l(const char * str, char ** endptr, int base, int sflag) { unsigned long number, cutoff; @@ -127,6 +128,7 @@ unsigned long strtoul(const char * str, char ** endptr, int base) { return _strto_l(str, endptr, base, 0); } +#endif int atoi(const char *str) { diff --git a/src/main/msp/msp.c b/src/main/msp/msp.c index 9d4434cbe7..3087069b9d 100644 --- a/src/main/msp/msp.c +++ b/src/main/msp/msp.c @@ -289,6 +289,9 @@ static void mspSerialPassthroughFn(serialPort_t *serialPort) static void mspFcSetPassthroughCommand(sbuf_t *dst, sbuf_t *src, mspPostProcessFnPtr *mspPostProcessFn) { +#ifndef USE_SERIAL_PASSTHROUGH + UNUSED(mspPostProcessFn); +#endif const unsigned int dataSize = sbufBytesRemaining(src); if (dataSize == 0) { // Legacy format @@ -311,8 +314,6 @@ static void mspFcSetPassthroughCommand(sbuf_t *dst, sbuf_t *src, mspPostProcessF sbufWriteU8(dst, 0); } break; -#else - UNUSED(mspPostProcessFn); #endif #ifdef USE_SERIAL_4WAY_BLHELI_INTERFACE case MSP_PASSTHROUGH_ESC_4WAY: diff --git a/src/main/target/common_post.h b/src/main/target/common_post.h index b406583886..33d53d6922 100644 --- a/src/main/target/common_post.h +++ b/src/main/target/common_post.h @@ -39,6 +39,10 @@ */ +#ifndef PLATFORM_NO_LIBC +#define PLATFORM_NO_LIBC 1 +#endif + #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) #define DEFAULT_AUX_CHANNEL_COUNT MAX_AUX_CHANNEL_COUNT #else From 6c07efce27fb7dd9a7f537379fc868765d592b31 Mon Sep 17 00:00:00 2001 From: Mark Haslinghuis Date: Wed, 11 Jun 2025 09:11:16 +0200 Subject: [PATCH 241/244] Remove unused rangefinder defines (#14429) Cleanup --- src/main/target/common_post.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/target/common_post.h b/src/main/target/common_post.h index 33d53d6922..ad68eee069 100644 --- a/src/main/target/common_post.h +++ b/src/main/target/common_post.h @@ -604,7 +604,7 @@ #endif #endif // USE_OPTICALFLOW_MT -#if defined(USE_RANGEFINDER_HCSR04) || defined(USE_RANGEFINDER_SRF10) || defined(USE_RANGEFINDER_HCSR04_I2C) || defined(USE_RANGEFINDER_VL53L0X) || defined(USE_RANGEFINDER_UIB) || defined(USE_RANGEFINDER_TF) || defined(USE_RANGEFINDER_MT) +#if defined(USE_RANGEFINDER_HCSR04) || defined(USE_RANGEFINDER_TF) || defined(USE_RANGEFINDER_MT) #ifndef USE_RANGEFINDER #define USE_RANGEFINDER #endif From 0e2faff6dcd6d18b61c93bc0d92df45938e9048c Mon Sep 17 00:00:00 2001 From: Jay Blackman Date: Sat, 14 Jun 2025 07:16:49 +1000 Subject: [PATCH 242/244] i2c changes required for I2CDEV_0 usage (#14443) * i2c changes required for I2CDEV_0 usage * Corrected offsets --- src/main/cli/settings.c | 20 ++++++++++++-------- src/main/fc/init.c | 3 +++ src/main/pg/bus_i2c.c | 9 +++++++++ src/main/target/common_defaults_post.h | 5 +++++ 4 files changed, 29 insertions(+), 8 deletions(-) diff --git a/src/main/cli/settings.c b/src/main/cli/settings.c index 7cbcabfc6b..5b5b0c4790 100644 --- a/src/main/cli/settings.c +++ b/src/main/cli/settings.c @@ -1845,21 +1845,25 @@ const clivalue_t valueTable[] = { { "gyro_2_align_yaw", VAR_INT16 | HARDWARE_VALUE, .config.minmax = { -3600, 3600 }, PG_GYRO_DEVICE_CONFIG, PG_ARRAY_ELEMENT_OFFSET(gyroDeviceConfig_t, 1, customAlignment.yaw) }, #endif #ifdef I2C_FULL_RECONFIGURABILITY +#ifdef USE_I2C_DEVICE_0 + { "i2c0_pullup", VAR_UINT8 | HARDWARE_VALUE | MODE_LOOKUP, .config.lookup = { TABLE_OFF_ON }, PG_I2C_CONFIG, PG_ARRAY_ELEMENT_OFFSET(i2cConfig_t, I2CDEV_0, pullUp) }, + { "i2c0_clockspeed_khz", VAR_UINT16 | HARDWARE_VALUE, .config.minmax = { I2C_CLOCKSPEED_MIN_KHZ, I2C_CLOCKSPEED_MAX_KHZ }, PG_I2C_CONFIG, PG_ARRAY_ELEMENT_OFFSET(i2cConfig_t, I2CDEV_0, clockSpeed) }, +#endif #ifdef USE_I2C_DEVICE_1 - { "i2c1_pullup", VAR_UINT8 | HARDWARE_VALUE | MODE_LOOKUP, .config.lookup = { TABLE_OFF_ON }, PG_I2C_CONFIG, PG_ARRAY_ELEMENT_OFFSET(i2cConfig_t, 0, pullUp) }, - { "i2c1_clockspeed_khz", VAR_UINT16 | HARDWARE_VALUE, .config.minmax = { I2C_CLOCKSPEED_MIN_KHZ, I2C_CLOCKSPEED_MAX_KHZ }, PG_I2C_CONFIG, PG_ARRAY_ELEMENT_OFFSET(i2cConfig_t, 0, clockSpeed) }, + { "i2c1_pullup", VAR_UINT8 | HARDWARE_VALUE | MODE_LOOKUP, .config.lookup = { TABLE_OFF_ON }, PG_I2C_CONFIG, PG_ARRAY_ELEMENT_OFFSET(i2cConfig_t, I2CDEV_1, pullUp) }, + { "i2c1_clockspeed_khz", VAR_UINT16 | HARDWARE_VALUE, .config.minmax = { I2C_CLOCKSPEED_MIN_KHZ, I2C_CLOCKSPEED_MAX_KHZ }, PG_I2C_CONFIG, PG_ARRAY_ELEMENT_OFFSET(i2cConfig_t, I2CDEV_1, clockSpeed) }, #endif #ifdef USE_I2C_DEVICE_2 - { "i2c2_pullup", VAR_UINT8 | HARDWARE_VALUE | MODE_LOOKUP, .config.lookup = { TABLE_OFF_ON }, PG_I2C_CONFIG, PG_ARRAY_ELEMENT_OFFSET(i2cConfig_t, 1, pullUp) }, - { "i2c2_clockspeed_khz", VAR_UINT16 | HARDWARE_VALUE, .config.minmax = { I2C_CLOCKSPEED_MIN_KHZ, I2C_CLOCKSPEED_MAX_KHZ }, PG_I2C_CONFIG, PG_ARRAY_ELEMENT_OFFSET(i2cConfig_t, 1, clockSpeed) }, + { "i2c2_pullup", VAR_UINT8 | HARDWARE_VALUE | MODE_LOOKUP, .config.lookup = { TABLE_OFF_ON }, PG_I2C_CONFIG, PG_ARRAY_ELEMENT_OFFSET(i2cConfig_t, I2CDEV_2, pullUp) }, + { "i2c2_clockspeed_khz", VAR_UINT16 | HARDWARE_VALUE, .config.minmax = { I2C_CLOCKSPEED_MIN_KHZ, I2C_CLOCKSPEED_MAX_KHZ }, PG_I2C_CONFIG, PG_ARRAY_ELEMENT_OFFSET(i2cConfig_t, I2CDEV_2, clockSpeed) }, #endif #ifdef USE_I2C_DEVICE_3 - { "i2c3_pullup", VAR_UINT8 | HARDWARE_VALUE | MODE_LOOKUP, .config.lookup = { TABLE_OFF_ON }, PG_I2C_CONFIG, PG_ARRAY_ELEMENT_OFFSET(i2cConfig_t, 2, pullUp) }, - { "i2c3_clockspeed_khz", VAR_UINT16 | HARDWARE_VALUE, .config.minmax = { I2C_CLOCKSPEED_MIN_KHZ, I2C_CLOCKSPEED_MAX_KHZ }, PG_I2C_CONFIG, PG_ARRAY_ELEMENT_OFFSET(i2cConfig_t, 2, clockSpeed) }, + { "i2c3_pullup", VAR_UINT8 | HARDWARE_VALUE | MODE_LOOKUP, .config.lookup = { TABLE_OFF_ON }, PG_I2C_CONFIG, PG_ARRAY_ELEMENT_OFFSET(i2cConfig_t, I2CDEV_3, pullUp) }, + { "i2c3_clockspeed_khz", VAR_UINT16 | HARDWARE_VALUE, .config.minmax = { I2C_CLOCKSPEED_MIN_KHZ, I2C_CLOCKSPEED_MAX_KHZ }, PG_I2C_CONFIG, PG_ARRAY_ELEMENT_OFFSET(i2cConfig_t, I2CDEV_3, clockSpeed) }, #endif #ifdef USE_I2C_DEVICE_4 - { "i2c4_pullup", VAR_UINT8 | HARDWARE_VALUE | MODE_LOOKUP, .config.lookup = { TABLE_OFF_ON }, PG_I2C_CONFIG, PG_ARRAY_ELEMENT_OFFSET(i2cConfig_t, 3, pullUp) }, - { "i2c4_clockspeed_khz", VAR_UINT16 | HARDWARE_VALUE, .config.minmax = { I2C_CLOCKSPEED_MIN_KHZ, I2C_CLOCKSPEED_MAX_KHZ }, PG_I2C_CONFIG, PG_ARRAY_ELEMENT_OFFSET(i2cConfig_t, 3, clockSpeed) }, + { "i2c4_pullup", VAR_UINT8 | HARDWARE_VALUE | MODE_LOOKUP, .config.lookup = { TABLE_OFF_ON }, PG_I2C_CONFIG, PG_ARRAY_ELEMENT_OFFSET(i2cConfig_t, I2CDEV_4, pullUp) }, + { "i2c4_clockspeed_khz", VAR_UINT16 | HARDWARE_VALUE, .config.minmax = { I2C_CLOCKSPEED_MIN_KHZ, I2C_CLOCKSPEED_MAX_KHZ }, PG_I2C_CONFIG, PG_ARRAY_ELEMENT_OFFSET(i2cConfig_t, I2CDEV_4, clockSpeed) }, #endif #endif #ifdef USE_MCO diff --git a/src/main/fc/init.c b/src/main/fc/init.c index 0b22ec9ca0..c156a4d0a6 100644 --- a/src/main/fc/init.c +++ b/src/main/fc/init.c @@ -629,6 +629,9 @@ void init(void) // Note: Unlike UARTs which are configured when client is present, // I2C buses are initialized unconditionally if they are configured. +#ifdef USE_I2C_DEVICE_0 + i2cInit(I2CDEV_0); +#endif #ifdef USE_I2C_DEVICE_1 i2cInit(I2CDEV_1); #endif diff --git a/src/main/pg/bus_i2c.c b/src/main/pg/bus_i2c.c index 20ce63365d..3b83ac0a1a 100644 --- a/src/main/pg/bus_i2c.c +++ b/src/main/pg/bus_i2c.c @@ -41,6 +41,12 @@ PG_REGISTER_ARRAY_WITH_RESET_FN(i2cConfig_t, I2CDEV_COUNT, i2cConfig, PG_I2C_CONFIG, 1); +#ifndef I2C0_SCL_PIN +#define I2C0_SCL_PIN NONE +#endif +#ifndef I2C0_SDA_PIN +#define I2C0_SDA_PIN NONE +#endif #ifndef I2C1_SCL_PIN #define I2C1_SCL_PIN NONE #endif @@ -74,6 +80,9 @@ typedef struct i2cDefaultConfig_s { } i2cDefaultConfig_t; static const i2cDefaultConfig_t i2cDefaultConfig[] = { +#ifdef USE_I2C_DEVICE_0 + { I2CDEV_0, IO_TAG(I2C0_SCL_PIN), IO_TAG(I2C0_SDA_PIN), I2C0_PULLUP, I2C0_CLOCKSPEED }, +#endif #ifdef USE_I2C_DEVICE_1 { I2CDEV_1, IO_TAG(I2C1_SCL_PIN), IO_TAG(I2C1_SDA_PIN), I2C1_PULLUP, I2C1_CLOCKSPEED }, #endif diff --git a/src/main/target/common_defaults_post.h b/src/main/target/common_defaults_post.h index e8b06bdf41..af162d6b5e 100644 --- a/src/main/target/common_defaults_post.h +++ b/src/main/target/common_defaults_post.h @@ -24,6 +24,9 @@ #define DEBUG_MODE DEBUG_NONE #endif +#ifndef I2C0_CLOCKSPEED +#define I2C0_CLOCKSPEED 800 +#endif #ifndef I2C1_CLOCKSPEED #define I2C1_CLOCKSPEED 800 #endif @@ -40,11 +43,13 @@ // Default values for internal pullup #if defined(USE_I2C_PULLUP) +#define I2C0_PULLUP true #define I2C1_PULLUP true #define I2C2_PULLUP true #define I2C3_PULLUP true #define I2C4_PULLUP true #else +#define I2C0_PULLUP false #define I2C1_PULLUP false #define I2C2_PULLUP false #define I2C3_PULLUP false From c3fe02be20ede4532c37a2641935f7ca338195cb Mon Sep 17 00:00:00 2001 From: mjs1441 Date: Sat, 14 Jun 2025 19:22:31 +0100 Subject: [PATCH 243/244] Fix misplaced #else/#endif in accgyro_spi_icm456xx.c (#14445) --- src/main/drivers/accgyro/accgyro_spi_icm456xx.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/main/drivers/accgyro/accgyro_spi_icm456xx.c b/src/main/drivers/accgyro/accgyro_spi_icm456xx.c index 34b6a17b28..d877a1c88b 100644 --- a/src/main/drivers/accgyro/accgyro_spi_icm456xx.c +++ b/src/main/drivers/accgyro/accgyro_spi_icm456xx.c @@ -479,7 +479,7 @@ bool icm456xxAccReadSPI(accDev_t *acc) spiWait(&acc->gyro->dev); } else -#else +#endif { // Interrupts are present, but no DMA. Non-DMA read uint8_t raw[ICM456XX_DATA_LENGTH]; @@ -493,7 +493,6 @@ bool icm456xxAccReadSPI(accDev_t *acc) acc->ADCRaw[Z] = (int16_t)((raw[5] << 8) | raw[4]); } -#endif break; } From a94083e77d6258bbf9b8b5388a82af9498c923e9 Mon Sep 17 00:00:00 2001 From: Eric Katzfey <53063038+katzfey@users.noreply.github.com> Date: Sat, 14 Jun 2025 11:24:31 -0700 Subject: [PATCH 244/244] Removed extraneous parentheses to resolve compiler warning (#14441) --- src/main/cli/cli.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/cli/cli.c b/src/main/cli/cli.c index e12cae2ae6..0090b0fa3f 100644 --- a/src/main/cli/cli.c +++ b/src/main/cli/cli.c @@ -1628,7 +1628,7 @@ static void cliSerialPassthrough(const char *cmdName, char *cmdline) cliPrintLinef("Forwarding, power cycle %sto exit.", resetMessage); - if ((ports[1].id == SERIAL_PORT_USB_VCP)) { + if (ports[1].id == SERIAL_PORT_USB_VCP) { do { if (port1ResetOnDtr) { serialSetCtrlLineStateCb(ports[1].port, cbCtrlLine_reset, NULL);